0 files changed, 0 insertions, 0 deletions
diff --git a/drivers/Kconfig b/drivers/Kconfig
index dcecc9f6e33f..c0f1fb893ec0 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -6,16 +6,29 @@ menu "Device Drivers"
 source "drivers/amba/Kconfig"
 source "drivers/eisa/Kconfig"
 source "drivers/pci/Kconfig"
+source "drivers/cxl/Kconfig"
 source "drivers/pcmcia/Kconfig"
 source "drivers/rapidio/Kconfig"
 
+config PC104
+	bool "PC/104 support" if EXPERT
+	help
+	  Expose PC/104 form factor device drivers and options available for
+	  selection and configuration. Enable this option if your target
+	  machine has a PC/104 bus.
 
 source "drivers/base/Kconfig"
 
 source "drivers/bus/Kconfig"
 
+source "drivers/cache/Kconfig"
+
 source "drivers/connector/Kconfig"
 
+source "drivers/firmware/Kconfig"
+
+source "drivers/fwctl/Kconfig"
+
 source "drivers/gnss/Kconfig"
 
 source "drivers/mtd/Kconfig"
@@ -32,8 +45,6 @@ source "drivers/nvme/Kconfig"
 
 source "drivers/misc/Kconfig"
 
-source "drivers/ide/Kconfig"
-
 source "drivers/scsi/Kconfig"
 
 source "drivers/ata/Kconfig"
@@ -52,8 +63,6 @@ source "drivers/net/Kconfig"
 
 source "drivers/isdn/Kconfig"
 
-source "drivers/lightnvm/Kconfig"
-
 # input before char - char/joystick depends on it. As does USB.
 
 source "drivers/input/Kconfig"
@@ -74,6 +83,8 @@ source "drivers/pps/Kconfig"
 
 source "drivers/ptp/Kconfig"
 
+source "drivers/dpll/Kconfig"
+
 source "drivers/pinctrl/Kconfig"
 
 source "drivers/gpio/Kconfig"
@@ -100,6 +111,8 @@ source "drivers/media/Kconfig"
 
 source "drivers/video/Kconfig"
 
+source "drivers/accel/Kconfig"
+
 source "sound/Kconfig"
 
 source "drivers/hid/Kconfig"
@@ -108,6 +121,8 @@ source "drivers/usb/Kconfig"
 
 source "drivers/mmc/Kconfig"
 
+source "drivers/ufs/Kconfig"
+
 source "drivers/memstick/Kconfig"
 
 source "drivers/leds/Kconfig"
@@ -126,14 +141,10 @@ source "drivers/dma-buf/Kconfig"
 
 source "drivers/dca/Kconfig"
 
-source "drivers/auxdisplay/Kconfig"
-
 source "drivers/uio/Kconfig"
 
 source "drivers/vfio/Kconfig"
 
-source "drivers/vlynq/Kconfig"
-
 source "drivers/virt/Kconfig"
 
 source "drivers/virtio/Kconfig"
@@ -148,6 +159,10 @@ source "drivers/xen/Kconfig"
 
 source "drivers/greybus/Kconfig"
 
+source "drivers/comedi/Kconfig"
+
+source "drivers/gpib/Kconfig"
+
 source "drivers/staging/Kconfig"
 
 source "drivers/platform/Kconfig"
@@ -170,6 +185,8 @@ source "drivers/soundwire/Kconfig"
 
 source "drivers/soc/Kconfig"
 
+source "drivers/pmdomain/Kconfig"
+
 source "drivers/devfreq/Kconfig"
 
 source "drivers/extcon/Kconfig"
@@ -180,8 +197,6 @@ source "drivers/iio/Kconfig"
 
 source "drivers/ntb/Kconfig"
 
-source "drivers/vme/Kconfig"
-
 source "drivers/pwm/Kconfig"
 
 source "drivers/irqchip/Kconfig"
@@ -204,8 +219,6 @@ source "drivers/thunderbolt/Kconfig"
 
 source "drivers/android/Kconfig"
 
-source "drivers/gpu/trace/Kconfig"
-
 source "drivers/nvdimm/Kconfig"
 
 source "drivers/dax/Kconfig"
@@ -224,8 +237,6 @@ source "drivers/mux/Kconfig"
 
 source "drivers/opp/Kconfig"
 
-source "drivers/visorbus/Kconfig"
-
 source "drivers/siox/Kconfig"
 
 source "drivers/slimbus/Kconfig"
@@ -235,4 +246,13 @@ source "drivers/interconnect/Kconfig"
 source "drivers/counter/Kconfig"
 
 source "drivers/most/Kconfig"
+
+source "drivers/peci/Kconfig"
+
+source "drivers/hte/Kconfig"
+
+source "drivers/cdx/Kconfig"
+
+source "drivers/resctrl/Kconfig"
+
 endmenu
diff --git a/drivers/Makefile b/drivers/Makefile
index c0cd1b9075e3..ccc05f1eae3e 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -6,6 +6,7 @@
 # Rewritten to use lists instead of if-statements.
 #
 
+obj-y				+= cache/
 obj-y				+= irqchip/
 obj-y				+= bus/
 
@@ -16,6 +17,9 @@ obj-$(CONFIG_PINCTRL)		+= pinctrl/
 obj-$(CONFIG_GPIOLIB)		+= gpio/
 obj-y				+= pwm/
 
+# LEDs must come before PCI, it is needed by NPEM driver
+obj-y				+= leds/
+
 obj-y				+= pci/
 
 obj-$(CONFIG_PARISC)		+= parisc/
@@ -27,7 +31,7 @@ obj-y				+= idle/
 obj-y				+= char/ipmi/
 
 obj-$(CONFIG_ACPI)		+= acpi/
-obj-$(CONFIG_SFI)		+= sfi/
+
 # PnP must come after ACPI since it will eventually need to check if acpi
 # was used and do nothing if so
 obj-$(CONFIG_PNP)		+= pnp/
@@ -40,8 +44,9 @@ obj-$(CONFIG_DMADEVICES)	+= dma/
 
 # SOC specific infrastructure drivers.
 obj-y				+= soc/
+obj-$(CONFIG_PM_GENERIC_DOMAINS)	+= pmdomain/
 
-obj-$(CONFIG_VIRTIO)		+= virtio/
+obj-y				+= virtio/
 obj-$(CONFIG_VDPA)		+= vdpa/
 obj-$(CONFIG_XEN)		+= xen/
 
@@ -64,19 +69,17 @@ obj-y				+= gpu/
 
 obj-$(CONFIG_CONNECTOR)		+= connector/
 
-# i810fb and intelfb depend on char/agp/
+# i810fb depends on char/agp/
 obj-$(CONFIG_FB_I810)           += video/fbdev/i810/
-obj-$(CONFIG_FB_INTEL)          += video/fbdev/intelfb/
 
 obj-$(CONFIG_PARPORT)		+= parport/
-obj-$(CONFIG_NVM)		+= lightnvm/
 obj-y				+= base/ block/ misc/ mfd/ nfc/
 obj-$(CONFIG_LIBNVDIMM)		+= nvdimm/
-obj-$(CONFIG_DAX)		+= dax/
+obj-y				+= dax/
 obj-$(CONFIG_DMA_SHARED_BUFFER) += dma-buf/
 obj-$(CONFIG_NUBUS)		+= nubus/
+obj-y				+= cxl/
 obj-y				+= macintosh/
-obj-$(CONFIG_IDE)		+= ide/
 obj-y				+= scsi/
 obj-y				+= nvme/
 obj-$(CONFIG_ATA)		+= ata/
@@ -99,7 +102,6 @@ obj-$(CONFIG_DIO)		+= dio/
 obj-$(CONFIG_SBUS)		+= sbus/
 obj-$(CONFIG_ZORRO)		+= zorro/
 obj-$(CONFIG_ATA_OVER_ETH)	+= block/aoe/
-obj-$(CONFIG_PARIDE) 		+= block/paride/
 obj-$(CONFIG_TC)		+= tc/
 obj-$(CONFIG_USB_PHY)		+= usb/
 obj-$(CONFIG_USB)		+= usb/
@@ -129,25 +131,26 @@ obj-$(CONFIG_PM_OPP)		+= opp/
 obj-$(CONFIG_CPU_FREQ)		+= cpufreq/
 obj-$(CONFIG_CPU_IDLE)		+= cpuidle/
 obj-y				+= mmc/
+obj-y				+= ufs/
 obj-$(CONFIG_MEMSTICK)		+= memstick/
-obj-$(CONFIG_NEW_LEDS)		+= leds/
 obj-$(CONFIG_INFINIBAND)	+= infiniband/
 obj-y				+= firmware/
+obj-$(CONFIG_FWCTL)		+= fwctl/
 obj-$(CONFIG_CRYPTO)		+= crypto/
 obj-$(CONFIG_SUPERH)		+= sh/
-ifndef CONFIG_ARCH_USES_GETTIMEOFFSET
 obj-y				+= clocksource/
-endif
 obj-$(CONFIG_DCA)		+= dca/
-obj-$(CONFIG_HID)		+= hid/
+obj-$(CONFIG_HID_SUPPORT)	+= hid/
 obj-$(CONFIG_PPC_PS3)		+= ps3/
 obj-$(CONFIG_OF)		+= of/
 obj-$(CONFIG_SSB)		+= ssb/
 obj-$(CONFIG_BCMA)		+= bcma/
 obj-$(CONFIG_VHOST_RING)	+= vhost/
+obj-$(CONFIG_VHOST_IOTLB)	+= vhost/
 obj-$(CONFIG_VHOST)		+= vhost/
-obj-$(CONFIG_VLYNQ)		+= vlynq/
 obj-$(CONFIG_GREYBUS)		+= greybus/
+obj-$(CONFIG_COMEDI)		+= comedi/
+obj-$(CONFIG_GPIB)		+= gpib/
 obj-$(CONFIG_STAGING)		+= staging/
 obj-y				+= platform/
 
@@ -158,14 +161,13 @@ obj-$(CONFIG_RPMSG)		+= rpmsg/
 obj-$(CONFIG_SOUNDWIRE)		+= soundwire/
 
 # Virtualization drivers
-obj-$(CONFIG_VIRT_DRIVERS)	+= virt/
+obj-y				+= virt/
 obj-$(CONFIG_HYPERV)		+= hv/
 
 obj-$(CONFIG_PM_DEVFREQ)	+= devfreq/
 obj-$(CONFIG_EXTCON)		+= extcon/
 obj-$(CONFIG_MEMORY)		+= memory/
 obj-$(CONFIG_IIO)		+= iio/
-obj-$(CONFIG_VME_BUS)		+= vme/
 obj-$(CONFIG_IPACK_BUS)		+= ipack/
 obj-$(CONFIG_NTB)		+= ntb/
 obj-$(CONFIG_POWERCAP)		+= powercap/
@@ -176,15 +178,24 @@ obj-$(CONFIG_USB4)		+= thunderbolt/
 obj-$(CONFIG_CORESIGHT)		+= hwtracing/coresight/
 obj-y				+= hwtracing/intel_th/
 obj-$(CONFIG_STM)		+= hwtracing/stm/
-obj-$(CONFIG_ANDROID)		+= android/
+obj-$(CONFIG_HISI_PTT)		+= hwtracing/ptt/
+obj-y				+= android/
 obj-$(CONFIG_NVMEM)		+= nvmem/
 obj-$(CONFIG_FPGA)		+= fpga/
 obj-$(CONFIG_FSI)		+= fsi/
 obj-$(CONFIG_TEE)		+= tee/
 obj-$(CONFIG_MULTIPLEXER)	+= mux/
-obj-$(CONFIG_UNISYS_VISORBUS)	+= visorbus/
 obj-$(CONFIG_SIOX)		+= siox/
 obj-$(CONFIG_GNSS)		+= gnss/
 obj-$(CONFIG_INTERCONNECT)	+= interconnect/
 obj-$(CONFIG_COUNTER)		+= counter/
 obj-$(CONFIG_MOST)		+= most/
+obj-$(CONFIG_PECI)		+= peci/
+obj-$(CONFIG_HTE)		+= hte/
+obj-$(CONFIG_DRM_ACCEL)		+= accel/
+obj-$(CONFIG_CDX_BUS)		+= cdx/
+obj-$(CONFIG_DPLL)		+= dpll/
+obj-y				+= resctrl/
+
+obj-$(CONFIG_DIBS)		+= dibs/
+obj-$(CONFIG_S390)		+= s390/
diff --git a/drivers/accel/Kconfig b/drivers/accel/Kconfig
new file mode 100644
index 000000000000..bdf48ccafcf2
--- /dev/null
+++ b/drivers/accel/Kconfig
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Compute Acceleration device configuration
+#
+# This framework provides support for compute acceleration devices, such
+# as, but not limited to, Machine-Learning and Deep-Learning acceleration
+# devices
+#
+if DRM
+
+menuconfig DRM_ACCEL
+	bool "Compute Acceleration Framework"
+	help
+	  Framework for device drivers of compute acceleration devices, such
+	  as, but not limited to, Machine-Learning and Deep-Learning
+	  acceleration devices.
+	  If you say Y here, you need to select the module that's right for
+	  your acceleration device from the list below.
+	  This framework is integrated with the DRM subsystem as compute
+	  accelerators and GPUs share a lot in common and can use almost the
+	  same infrastructure code.
+	  Having said that, acceleration devices will have a different
+	  major number than GPUs, and will be exposed to user-space using
+	  different device files, called accel/accel* (in /dev, sysfs
+	  and debugfs).
+
+source "drivers/accel/amdxdna/Kconfig"
+source "drivers/accel/ethosu/Kconfig"
+source "drivers/accel/habanalabs/Kconfig"
+source "drivers/accel/ivpu/Kconfig"
+source "drivers/accel/qaic/Kconfig"
+source "drivers/accel/rocket/Kconfig"
+
+endif
diff --git a/drivers/accel/Makefile b/drivers/accel/Makefile
new file mode 100644
index 000000000000..1d3a7251b950
--- /dev/null
+++ b/drivers/accel/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+obj-$(CONFIG_DRM_ACCEL_AMDXDNA)		+= amdxdna/
+obj-$(CONFIG_DRM_ACCEL_ARM_ETHOSU)	+= ethosu/
+obj-$(CONFIG_DRM_ACCEL_HABANALABS)	+= habanalabs/
+obj-$(CONFIG_DRM_ACCEL_IVPU)		+= ivpu/
+obj-$(CONFIG_DRM_ACCEL_QAIC)		+= qaic/
+obj-$(CONFIG_DRM_ACCEL_ROCKET)		+= rocket/
+\ No newline at end of file
diff --git a/drivers/accel/amdxdna/Kconfig b/drivers/accel/amdxdna/Kconfig
new file mode 100644
index 000000000000..f39d7a87296c
--- /dev/null
+++ b/drivers/accel/amdxdna/Kconfig
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config DRM_ACCEL_AMDXDNA
+	tristate "AMD AI Engine"
+	depends on AMD_IOMMU
+	depends on DRM_ACCEL
+	depends on PCI && HAS_IOMEM
+	depends on X86_64
+	select DRM_SCHED
+	select DRM_GEM_SHMEM_HELPER
+	select FW_LOADER
+	select HMM_MIRROR
+	help
+	  Choose this option to enable support for NPU integrated into AMD
+	  client CPUs like AMD Ryzen AI 300 Series. AMD NPU can be used to
+	  accelerate machine learning applications.
+
+	  If "M" is selected, the driver module will be amdxdna.
diff --git a/drivers/accel/amdxdna/Makefile b/drivers/accel/amdxdna/Makefile
new file mode 100644
index 000000000000..6344aaf523fa
--- /dev/null
+++ b/drivers/accel/amdxdna/Makefile
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+amdxdna-y := \
+	aie2_ctx.o \
+	aie2_error.o \
+	aie2_message.o \
+	aie2_pci.o \
+	aie2_pm.o \
+	aie2_psp.o \
+	aie2_smu.o \
+	aie2_solver.o \
+	amdxdna_ctx.o \
+	amdxdna_gem.o \
+	amdxdna_mailbox.o \
+	amdxdna_mailbox_helper.o \
+	amdxdna_pci_drv.o \
+	amdxdna_pm.o \
+	amdxdna_sysfs.o \
+	amdxdna_ubuf.o \
+	npu1_regs.o \
+	npu2_regs.o \
+	npu4_regs.o \
+	npu5_regs.o \
+	npu6_regs.o
+obj-$(CONFIG_DRM_ACCEL_AMDXDNA) = amdxdna.o
diff --git a/drivers/accel/amdxdna/TODO b/drivers/accel/amdxdna/TODO
new file mode 100644
index 000000000000..0e4bbebeaedf
--- /dev/null
+++ b/drivers/accel/amdxdna/TODO
@@ -0,0 +1 @@
+- Add debugfs support
diff --git a/drivers/accel/amdxdna/aie2_ctx.c b/drivers/accel/amdxdna/aie2_ctx.c
new file mode 100644
index 000000000000..42d876a427c5
--- /dev/null
+++ b/drivers/accel/amdxdna/aie2_ctx.c
@@ -0,0 +1,1079 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024, Advanced Micro Devices, Inc.
+ */
+
+#include <drm/amdxdna_accel.h>
+#include <drm/drm_device.h>
+#include <drm/drm_gem.h>
+#include <drm/drm_gem_shmem_helper.h>
+#include <drm/drm_print.h>
+#include <drm/drm_syncobj.h>
+#include <linux/hmm.h>
+#include <linux/types.h>
+#include <linux/xarray.h>
+#include <trace/events/amdxdna.h>
+
+#include "aie2_msg_priv.h"
+#include "aie2_pci.h"
+#include "aie2_solver.h"
+#include "amdxdna_ctx.h"
+#include "amdxdna_gem.h"
+#include "amdxdna_mailbox.h"
+#include "amdxdna_pci_drv.h"
+#include "amdxdna_pm.h"
+
+static bool force_cmdlist;
+module_param(force_cmdlist, bool, 0600);
+MODULE_PARM_DESC(force_cmdlist, "Force use command list (Default false)");
+
+#define HWCTX_MAX_TIMEOUT	60000 /* milliseconds */
+
+static void aie2_job_release(struct kref *ref)
+{
+	struct amdxdna_sched_job *job;
+
+	job = container_of(ref, struct amdxdna_sched_job, refcnt);
+	amdxdna_sched_job_cleanup(job);
+	atomic64_inc(&job->hwctx->job_free_cnt);
+	wake_up(&job->hwctx->priv->job_free_wq);
+	if (job->out_fence)
+		dma_fence_put(job->out_fence);
+	kfree(job);
+}
+
+static void aie2_job_put(struct amdxdna_sched_job *job)
+{
+	kref_put(&job->refcnt, aie2_job_release);
+}
+
+static void aie2_hwctx_status_shift_stop(struct amdxdna_hwctx *hwctx)
+{
+	 hwctx->old_status = hwctx->status;
+	 hwctx->status = HWCTX_STAT_STOP;
+}
+
+static void aie2_hwctx_status_restore(struct amdxdna_hwctx *hwctx)
+{
+	hwctx->status = hwctx->old_status;
+}
+
+/* The bad_job is used in aie2_sched_job_timedout, otherwise, set it to NULL */
+static void aie2_hwctx_stop(struct amdxdna_dev *xdna, struct amdxdna_hwctx *hwctx,
+			    struct drm_sched_job *bad_job)
+{
+	drm_sched_stop(&hwctx->priv->sched, bad_job);
+	aie2_destroy_context(xdna->dev_handle, hwctx);
+}
+
+static int aie2_hwctx_restart(struct amdxdna_dev *xdna, struct amdxdna_hwctx *hwctx)
+{
+	struct amdxdna_gem_obj *heap = hwctx->priv->heap;
+	int ret;
+
+	ret = aie2_create_context(xdna->dev_handle, hwctx);
+	if (ret) {
+		XDNA_ERR(xdna, "Create hwctx failed, ret %d", ret);
+		goto out;
+	}
+
+	ret = aie2_map_host_buf(xdna->dev_handle, hwctx->fw_ctx_id,
+				heap->mem.userptr, heap->mem.size);
+	if (ret) {
+		XDNA_ERR(xdna, "Map host buf failed, ret %d", ret);
+		goto out;
+	}
+
+	if (hwctx->status != HWCTX_STAT_READY) {
+		XDNA_DBG(xdna, "hwctx is not ready, status %d", hwctx->status);
+		goto out;
+	}
+
+	ret = aie2_config_cu(hwctx, NULL);
+	if (ret) {
+		XDNA_ERR(xdna, "Config cu failed, ret %d", ret);
+		goto out;
+	}
+
+out:
+	drm_sched_start(&hwctx->priv->sched, 0);
+	XDNA_DBG(xdna, "%s restarted, ret %d", hwctx->name, ret);
+	return ret;
+}
+
+static struct dma_fence *aie2_cmd_get_out_fence(struct amdxdna_hwctx *hwctx, u64 seq)
+{
+	struct dma_fence *fence, *out_fence = NULL;
+	int ret;
+
+	fence = drm_syncobj_fence_get(hwctx->priv->syncobj);
+	if (!fence)
+		return NULL;
+
+	ret = dma_fence_chain_find_seqno(&fence,  seq);
+	if (ret)
+		goto out;
+
+	out_fence = dma_fence_get(dma_fence_chain_contained(fence));
+
+out:
+	dma_fence_put(fence);
+	return out_fence;
+}
+
+static void aie2_hwctx_wait_for_idle(struct amdxdna_hwctx *hwctx)
+{
+	struct dma_fence *fence;
+
+	fence = aie2_cmd_get_out_fence(hwctx, hwctx->priv->seq - 1);
+	if (!fence)
+		return;
+
+	/* Wait up to 2 seconds for fw to finish all pending requests */
+	dma_fence_wait_timeout(fence, false, msecs_to_jiffies(2000));
+	dma_fence_put(fence);
+}
+
+static int aie2_hwctx_suspend_cb(struct amdxdna_hwctx *hwctx, void *arg)
+{
+	struct amdxdna_dev *xdna = hwctx->client->xdna;
+
+	aie2_hwctx_wait_for_idle(hwctx);
+	aie2_hwctx_stop(xdna, hwctx, NULL);
+	aie2_hwctx_status_shift_stop(hwctx);
+
+	return 0;
+}
+
+void aie2_hwctx_suspend(struct amdxdna_client *client)
+{
+	struct amdxdna_dev *xdna = client->xdna;
+
+	/*
+	 * Command timeout is unlikely. But if it happens, it doesn't
+	 * break the system. aie2_hwctx_stop() will destroy mailbox
+	 * and abort all commands.
+	 */
+	drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock));
+	amdxdna_hwctx_walk(client, NULL, aie2_hwctx_suspend_cb);
+}
+
+static int aie2_hwctx_resume_cb(struct amdxdna_hwctx *hwctx, void *arg)
+{
+	struct amdxdna_dev *xdna = hwctx->client->xdna;
+
+	aie2_hwctx_status_restore(hwctx);
+	return aie2_hwctx_restart(xdna, hwctx);
+}
+
+int aie2_hwctx_resume(struct amdxdna_client *client)
+{
+	/*
+	 * The resume path cannot guarantee that mailbox channel can be
+	 * regenerated. If this happen, when submit message to this
+	 * mailbox channel, error will return.
+	 */
+	return amdxdna_hwctx_walk(client, NULL, aie2_hwctx_resume_cb);
+}
+
+static void
+aie2_sched_notify(struct amdxdna_sched_job *job)
+{
+	struct dma_fence *fence = job->fence;
+
+	trace_xdna_job(&job->base, job->hwctx->name, "signaled fence", job->seq);
+
+	amdxdna_pm_suspend_put(job->hwctx->client->xdna);
+	job->hwctx->priv->completed++;
+	dma_fence_signal(fence);
+
+	up(&job->hwctx->priv->job_sem);
+	job->job_done = true;
+	mmput_async(job->mm);
+	aie2_job_put(job);
+}
+
+static int
+aie2_sched_resp_handler(void *handle, void __iomem *data, size_t size)
+{
+	struct amdxdna_sched_job *job = handle;
+	struct amdxdna_gem_obj *cmd_abo;
+	int ret = 0;
+	u32 status;
+
+	cmd_abo = job->cmd_bo;
+
+	if (unlikely(job->job_timeout)) {
+		amdxdna_cmd_set_state(cmd_abo, ERT_CMD_STATE_TIMEOUT);
+		ret = -EINVAL;
+		goto out;
+	}
+
+	if (unlikely(!data) || unlikely(size != sizeof(u32))) {
+		amdxdna_cmd_set_state(cmd_abo, ERT_CMD_STATE_ABORT);
+		ret = -EINVAL;
+		goto out;
+	}
+
+	status = readl(data);
+	XDNA_DBG(job->hwctx->client->xdna, "Resp status 0x%x", status);
+	if (status == AIE2_STATUS_SUCCESS)
+		amdxdna_cmd_set_state(cmd_abo, ERT_CMD_STATE_COMPLETED);
+	else
+		amdxdna_cmd_set_state(cmd_abo, ERT_CMD_STATE_ERROR);
+
+out:
+	aie2_sched_notify(job);
+	return ret;
+}
+
+static int
+aie2_sched_drvcmd_resp_handler(void *handle, void __iomem *data, size_t size)
+{
+	struct amdxdna_sched_job *job = handle;
+	int ret = 0;
+
+	if (unlikely(!data))
+		goto out;
+
+	if (unlikely(size != sizeof(u32))) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	job->drv_cmd->result = readl(data);
+
+out:
+	aie2_sched_notify(job);
+	return ret;
+}
+
+static int
+aie2_sched_cmdlist_resp_handler(void *handle, void __iomem *data, size_t size)
+{
+	struct amdxdna_sched_job *job = handle;
+	struct amdxdna_gem_obj *cmd_abo;
+	struct amdxdna_dev *xdna;
+	u32 fail_cmd_status;
+	u32 fail_cmd_idx;
+	u32 cmd_status;
+	int ret = 0;
+
+	cmd_abo = job->cmd_bo;
+
+	if (unlikely(job->job_timeout)) {
+		amdxdna_cmd_set_state(cmd_abo, ERT_CMD_STATE_TIMEOUT);
+		ret = -EINVAL;
+		goto out;
+	}
+
+	if (unlikely(!data) || unlikely(size != sizeof(u32) * 3)) {
+		amdxdna_cmd_set_state(cmd_abo, ERT_CMD_STATE_ABORT);
+		ret = -EINVAL;
+		goto out;
+	}
+
+	cmd_status = readl(data + offsetof(struct cmd_chain_resp, status));
+	xdna = job->hwctx->client->xdna;
+	XDNA_DBG(xdna, "Status 0x%x", cmd_status);
+	if (cmd_status == AIE2_STATUS_SUCCESS) {
+		amdxdna_cmd_set_state(cmd_abo, ERT_CMD_STATE_COMPLETED);
+		goto out;
+	}
+
+	/* Slow path to handle error, read from ringbuf on BAR */
+	fail_cmd_idx = readl(data + offsetof(struct cmd_chain_resp, fail_cmd_idx));
+	fail_cmd_status = readl(data + offsetof(struct cmd_chain_resp, fail_cmd_status));
+	XDNA_DBG(xdna, "Failed cmd idx %d, status 0x%x",
+		 fail_cmd_idx, fail_cmd_status);
+
+	if (fail_cmd_status == AIE2_STATUS_SUCCESS) {
+		amdxdna_cmd_set_state(cmd_abo, ERT_CMD_STATE_ABORT);
+		ret = -EINVAL;
+		goto out;
+	}
+	amdxdna_cmd_set_state(cmd_abo, fail_cmd_status);
+
+	if (amdxdna_cmd_get_op(cmd_abo) == ERT_CMD_CHAIN) {
+		struct amdxdna_cmd_chain *cc = amdxdna_cmd_get_payload(cmd_abo, NULL);
+
+		cc->error_index = fail_cmd_idx;
+		if (cc->error_index >= cc->command_count)
+			cc->error_index = 0;
+	}
+out:
+	aie2_sched_notify(job);
+	return ret;
+}
+
+static struct dma_fence *
+aie2_sched_job_run(struct drm_sched_job *sched_job)
+{
+	struct amdxdna_sched_job *job = drm_job_to_xdna_job(sched_job);
+	struct amdxdna_gem_obj *cmd_abo = job->cmd_bo;
+	struct amdxdna_hwctx *hwctx = job->hwctx;
+	struct dma_fence *fence;
+	int ret;
+
+	if (!mmget_not_zero(job->mm))
+		return ERR_PTR(-ESRCH);
+
+	kref_get(&job->refcnt);
+	fence = dma_fence_get(job->fence);
+
+	if (job->drv_cmd) {
+		switch (job->drv_cmd->opcode) {
+		case SYNC_DEBUG_BO:
+			ret = aie2_sync_bo(hwctx, job, aie2_sched_drvcmd_resp_handler);
+			break;
+		case ATTACH_DEBUG_BO:
+			ret = aie2_config_debug_bo(hwctx, job, aie2_sched_drvcmd_resp_handler);
+			break;
+		default:
+			ret = -EINVAL;
+			break;
+		}
+		goto out;
+	}
+
+	amdxdna_cmd_set_state(cmd_abo, ERT_CMD_STATE_NEW);
+
+	if (amdxdna_cmd_get_op(cmd_abo) == ERT_CMD_CHAIN)
+		ret = aie2_cmdlist_multi_execbuf(hwctx, job, aie2_sched_cmdlist_resp_handler);
+	else if (force_cmdlist)
+		ret = aie2_cmdlist_single_execbuf(hwctx, job, aie2_sched_cmdlist_resp_handler);
+	else
+		ret = aie2_execbuf(hwctx, job, aie2_sched_resp_handler);
+
+out:
+	if (ret) {
+		dma_fence_put(job->fence);
+		aie2_job_put(job);
+		mmput(job->mm);
+		fence = ERR_PTR(ret);
+	}
+	trace_xdna_job(sched_job, hwctx->name, "sent to device", job->seq);
+
+	return fence;
+}
+
+static void aie2_sched_job_free(struct drm_sched_job *sched_job)
+{
+	struct amdxdna_sched_job *job = drm_job_to_xdna_job(sched_job);
+	struct amdxdna_hwctx *hwctx = job->hwctx;
+
+	trace_xdna_job(sched_job, hwctx->name, "job free", job->seq);
+	if (!job->job_done)
+		up(&hwctx->priv->job_sem);
+
+	drm_sched_job_cleanup(sched_job);
+	aie2_job_put(job);
+}
+
+static enum drm_gpu_sched_stat
+aie2_sched_job_timedout(struct drm_sched_job *sched_job)
+{
+	struct amdxdna_sched_job *job = drm_job_to_xdna_job(sched_job);
+	struct amdxdna_hwctx *hwctx = job->hwctx;
+	struct amdxdna_dev *xdna;
+
+	xdna = hwctx->client->xdna;
+	trace_xdna_job(sched_job, hwctx->name, "job timedout", job->seq);
+	job->job_timeout = true;
+	mutex_lock(&xdna->dev_lock);
+	aie2_hwctx_stop(xdna, hwctx, sched_job);
+
+	aie2_hwctx_restart(xdna, hwctx);
+	mutex_unlock(&xdna->dev_lock);
+
+	return DRM_GPU_SCHED_STAT_RESET;
+}
+
+static const struct drm_sched_backend_ops sched_ops = {
+	.run_job = aie2_sched_job_run,
+	.free_job = aie2_sched_job_free,
+	.timedout_job = aie2_sched_job_timedout,
+};
+
+static int aie2_hwctx_col_list(struct amdxdna_hwctx *hwctx)
+{
+	struct amdxdna_dev *xdna = hwctx->client->xdna;
+	struct amdxdna_dev_hdl *ndev;
+	int start, end, first, last;
+	u32 width = 1, entries = 0;
+	int i;
+
+	if (!hwctx->num_tiles) {
+		XDNA_ERR(xdna, "Number of tiles is zero");
+		return -EINVAL;
+	}
+
+	ndev = xdna->dev_handle;
+	if (unlikely(!ndev->metadata.core.row_count)) {
+		XDNA_WARN(xdna, "Core tile row count is zero");
+		return -EINVAL;
+	}
+
+	hwctx->num_col = hwctx->num_tiles / ndev->metadata.core.row_count;
+	if (!hwctx->num_col || hwctx->num_col > ndev->total_col) {
+		XDNA_ERR(xdna, "Invalid num_col %d", hwctx->num_col);
+		return -EINVAL;
+	}
+
+	if (ndev->priv->col_align == COL_ALIGN_NATURE)
+		width = hwctx->num_col;
+
+	/*
+	 * In range [start, end], find out columns that is multiple of width.
+	 *	'first' is the first column,
+	 *	'last' is the last column,
+	 *	'entries' is the total number of columns.
+	 */
+	start =  xdna->dev_info->first_col;
+	end =  ndev->total_col - hwctx->num_col;
+	if (start > 0 && end == 0) {
+		XDNA_DBG(xdna, "Force start from col 0");
+		start = 0;
+	}
+	first = start + (width - start % width) % width;
+	last = end - end % width;
+	if (last >= first)
+		entries = (last - first) / width + 1;
+	XDNA_DBG(xdna, "start %d end %d first %d last %d",
+		 start, end, first, last);
+
+	if (unlikely(!entries)) {
+		XDNA_ERR(xdna, "Start %d end %d width %d",
+			 start, end, width);
+		return -EINVAL;
+	}
+
+	hwctx->col_list = kmalloc_array(entries, sizeof(*hwctx->col_list), GFP_KERNEL);
+	if (!hwctx->col_list)
+		return -ENOMEM;
+
+	hwctx->col_list_len = entries;
+	hwctx->col_list[0] = first;
+	for (i = 1; i < entries; i++)
+		hwctx->col_list[i] = hwctx->col_list[i - 1] + width;
+
+	print_hex_dump_debug("col_list: ", DUMP_PREFIX_OFFSET, 16, 4, hwctx->col_list,
+			     entries * sizeof(*hwctx->col_list), false);
+	return 0;
+}
+
+static int aie2_alloc_resource(struct amdxdna_hwctx *hwctx)
+{
+	struct amdxdna_dev *xdna = hwctx->client->xdna;
+	struct alloc_requests *xrs_req;
+	int ret;
+
+	xrs_req = kzalloc(sizeof(*xrs_req), GFP_KERNEL);
+	if (!xrs_req)
+		return -ENOMEM;
+
+	xrs_req->cdo.start_cols = hwctx->col_list;
+	xrs_req->cdo.cols_len = hwctx->col_list_len;
+	xrs_req->cdo.ncols = hwctx->num_col;
+	xrs_req->cdo.qos_cap.opc = hwctx->max_opc;
+
+	xrs_req->rqos.gops = hwctx->qos.gops;
+	xrs_req->rqos.fps = hwctx->qos.fps;
+	xrs_req->rqos.dma_bw = hwctx->qos.dma_bandwidth;
+	xrs_req->rqos.latency = hwctx->qos.latency;
+	xrs_req->rqos.exec_time = hwctx->qos.frame_exec_time;
+	xrs_req->rqos.priority = hwctx->qos.priority;
+
+	xrs_req->rid = (uintptr_t)hwctx;
+
+	ret = xrs_allocate_resource(xdna->xrs_hdl, xrs_req, hwctx);
+	if (ret)
+		XDNA_ERR(xdna, "Allocate AIE resource failed, ret %d", ret);
+
+	kfree(xrs_req);
+	return ret;
+}
+
+static void aie2_release_resource(struct amdxdna_hwctx *hwctx)
+{
+	struct amdxdna_dev *xdna = hwctx->client->xdna;
+	int ret;
+
+	ret = xrs_release_resource(xdna->xrs_hdl, (uintptr_t)hwctx);
+	if (ret)
+		XDNA_ERR(xdna, "Release AIE resource failed, ret %d", ret);
+}
+
+static int aie2_ctx_syncobj_create(struct amdxdna_hwctx *hwctx)
+{
+	struct amdxdna_dev *xdna = hwctx->client->xdna;
+	struct drm_file *filp = hwctx->client->filp;
+	struct drm_syncobj *syncobj;
+	u32 hdl;
+	int ret;
+
+	hwctx->syncobj_hdl = AMDXDNA_INVALID_FENCE_HANDLE;
+
+	ret = drm_syncobj_create(&syncobj, 0, NULL);
+	if (ret) {
+		XDNA_ERR(xdna, "Create ctx syncobj failed, ret %d", ret);
+		return ret;
+	}
+	ret = drm_syncobj_get_handle(filp, syncobj, &hdl);
+	if (ret) {
+		drm_syncobj_put(syncobj);
+		XDNA_ERR(xdna, "Create ctx syncobj handle failed, ret %d", ret);
+		return ret;
+	}
+	hwctx->priv->syncobj = syncobj;
+	hwctx->syncobj_hdl = hdl;
+
+	return 0;
+}
+
+static void aie2_ctx_syncobj_destroy(struct amdxdna_hwctx *hwctx)
+{
+	/*
+	 * The syncobj_hdl is owned by user space and will be cleaned up
+	 * separately.
+	 */
+	drm_syncobj_put(hwctx->priv->syncobj);
+}
+
+int aie2_hwctx_init(struct amdxdna_hwctx *hwctx)
+{
+	struct amdxdna_client *client = hwctx->client;
+	struct amdxdna_dev *xdna = client->xdna;
+	const struct drm_sched_init_args args = {
+		.ops = &sched_ops,
+		.num_rqs = DRM_SCHED_PRIORITY_COUNT,
+		.credit_limit = HWCTX_MAX_CMDS,
+		.timeout = msecs_to_jiffies(HWCTX_MAX_TIMEOUT),
+		.name = "amdxdna_js",
+		.dev = xdna->ddev.dev,
+	};
+	struct drm_gpu_scheduler *sched;
+	struct amdxdna_hwctx_priv *priv;
+	struct amdxdna_gem_obj *heap;
+	int i, ret;
+
+	priv = kzalloc(sizeof(*hwctx->priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+	hwctx->priv = priv;
+
+	mutex_lock(&client->mm_lock);
+	heap = client->dev_heap;
+	if (!heap) {
+		XDNA_ERR(xdna, "The client dev heap object not exist");
+		mutex_unlock(&client->mm_lock);
+		ret = -ENOENT;
+		goto free_priv;
+	}
+	drm_gem_object_get(to_gobj(heap));
+	mutex_unlock(&client->mm_lock);
+	priv->heap = heap;
+	sema_init(&priv->job_sem, HWCTX_MAX_CMDS);
+
+	ret = amdxdna_gem_pin(heap);
+	if (ret) {
+		XDNA_ERR(xdna, "Dev heap pin failed, ret %d", ret);
+		goto put_heap;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(priv->cmd_buf); i++) {
+		struct amdxdna_gem_obj *abo;
+		struct amdxdna_drm_create_bo args = {
+			.flags = 0,
+			.type = AMDXDNA_BO_DEV,
+			.vaddr = 0,
+			.size = MAX_CHAIN_CMDBUF_SIZE,
+		};
+
+		abo = amdxdna_drm_alloc_dev_bo(&xdna->ddev, &args, client->filp);
+		if (IS_ERR(abo)) {
+			ret = PTR_ERR(abo);
+			goto free_cmd_bufs;
+		}
+
+		XDNA_DBG(xdna, "Command buf %d addr 0x%llx size 0x%lx",
+			 i, abo->mem.dev_addr, abo->mem.size);
+		priv->cmd_buf[i] = abo;
+	}
+
+	sched = &priv->sched;
+	mutex_init(&priv->io_lock);
+
+	fs_reclaim_acquire(GFP_KERNEL);
+	might_lock(&priv->io_lock);
+	fs_reclaim_release(GFP_KERNEL);
+
+	ret = drm_sched_init(sched, &args);
+	if (ret) {
+		XDNA_ERR(xdna, "Failed to init DRM scheduler. ret %d", ret);
+		goto free_cmd_bufs;
+	}
+
+	ret = drm_sched_entity_init(&priv->entity, DRM_SCHED_PRIORITY_NORMAL,
+				    &sched, 1, NULL);
+	if (ret) {
+		XDNA_ERR(xdna, "Failed to initial sched entiry. ret %d", ret);
+		goto free_sched;
+	}
+
+	ret = aie2_hwctx_col_list(hwctx);
+	if (ret) {
+		XDNA_ERR(xdna, "Create col list failed, ret %d", ret);
+		goto free_entity;
+	}
+
+	ret = amdxdna_pm_resume_get(xdna);
+	if (ret)
+		goto free_col_list;
+
+	ret = aie2_alloc_resource(hwctx);
+	if (ret) {
+		XDNA_ERR(xdna, "Alloc hw resource failed, ret %d", ret);
+		goto suspend_put;
+	}
+
+	ret = aie2_map_host_buf(xdna->dev_handle, hwctx->fw_ctx_id,
+				heap->mem.userptr, heap->mem.size);
+	if (ret) {
+		XDNA_ERR(xdna, "Map host buffer failed, ret %d", ret);
+		goto release_resource;
+	}
+
+	ret = aie2_ctx_syncobj_create(hwctx);
+	if (ret) {
+		XDNA_ERR(xdna, "Create syncobj failed, ret %d", ret);
+		goto release_resource;
+	}
+	amdxdna_pm_suspend_put(xdna);
+
+	hwctx->status = HWCTX_STAT_INIT;
+	init_waitqueue_head(&priv->job_free_wq);
+
+	XDNA_DBG(xdna, "hwctx %s init completed", hwctx->name);
+
+	return 0;
+
+release_resource:
+	aie2_release_resource(hwctx);
+suspend_put:
+	amdxdna_pm_suspend_put(xdna);
+free_col_list:
+	kfree(hwctx->col_list);
+free_entity:
+	drm_sched_entity_destroy(&priv->entity);
+free_sched:
+	drm_sched_fini(&priv->sched);
+free_cmd_bufs:
+	for (i = 0; i < ARRAY_SIZE(priv->cmd_buf); i++) {
+		if (!priv->cmd_buf[i])
+			continue;
+		drm_gem_object_put(to_gobj(priv->cmd_buf[i]));
+	}
+	amdxdna_gem_unpin(heap);
+put_heap:
+	drm_gem_object_put(to_gobj(heap));
+free_priv:
+	kfree(priv);
+	return ret;
+}
+
+void aie2_hwctx_fini(struct amdxdna_hwctx *hwctx)
+{
+	struct amdxdna_dev *xdna;
+	int idx;
+
+	xdna = hwctx->client->xdna;
+
+	XDNA_DBG(xdna, "%s sequence number %lld", hwctx->name, hwctx->priv->seq);
+	aie2_hwctx_wait_for_idle(hwctx);
+
+	/* Request fw to destroy hwctx and cancel the rest pending requests */
+	aie2_release_resource(hwctx);
+
+	mutex_unlock(&xdna->dev_lock);
+	drm_sched_entity_destroy(&hwctx->priv->entity);
+
+	/* Wait for all submitted jobs to be completed or canceled */
+	wait_event(hwctx->priv->job_free_wq,
+		   atomic64_read(&hwctx->job_submit_cnt) ==
+		   atomic64_read(&hwctx->job_free_cnt));
+	mutex_lock(&xdna->dev_lock);
+
+	drm_sched_fini(&hwctx->priv->sched);
+	aie2_ctx_syncobj_destroy(hwctx);
+
+	for (idx = 0; idx < ARRAY_SIZE(hwctx->priv->cmd_buf); idx++)
+		drm_gem_object_put(to_gobj(hwctx->priv->cmd_buf[idx]));
+	amdxdna_gem_unpin(hwctx->priv->heap);
+	drm_gem_object_put(to_gobj(hwctx->priv->heap));
+
+	mutex_destroy(&hwctx->priv->io_lock);
+	kfree(hwctx->col_list);
+	kfree(hwctx->priv);
+	kfree(hwctx->cus);
+}
+
+static int aie2_config_cu_resp_handler(void *handle, void __iomem *data, size_t size)
+{
+	struct amdxdna_hwctx *hwctx = handle;
+
+	amdxdna_pm_suspend_put(hwctx->client->xdna);
+	return 0;
+}
+
+static int aie2_hwctx_cu_config(struct amdxdna_hwctx *hwctx, void *buf, u32 size)
+{
+	struct amdxdna_hwctx_param_config_cu *config = buf;
+	struct amdxdna_dev *xdna = hwctx->client->xdna;
+	u32 total_size;
+	int ret;
+
+	XDNA_DBG(xdna, "Config %d CU to %s", config->num_cus, hwctx->name);
+	if (XDNA_MBZ_DBG(xdna, config->pad, sizeof(config->pad)))
+		return -EINVAL;
+
+	if (hwctx->status != HWCTX_STAT_INIT) {
+		XDNA_ERR(xdna, "Not support re-config CU");
+		return -EINVAL;
+	}
+
+	if (!config->num_cus) {
+		XDNA_ERR(xdna, "Number of CU is zero");
+		return -EINVAL;
+	}
+
+	total_size = struct_size(config, cu_configs, config->num_cus);
+	if (total_size > size) {
+		XDNA_ERR(xdna, "CU config larger than size");
+		return -EINVAL;
+	}
+
+	hwctx->cus = kmemdup(config, total_size, GFP_KERNEL);
+	if (!hwctx->cus)
+		return -ENOMEM;
+
+	ret = amdxdna_pm_resume_get(xdna);
+	if (ret)
+		goto free_cus;
+
+	ret = aie2_config_cu(hwctx, aie2_config_cu_resp_handler);
+	if (ret) {
+		XDNA_ERR(xdna, "Config CU to firmware failed, ret %d", ret);
+		goto pm_suspend_put;
+	}
+
+	wmb(); /* To avoid locking in command submit when check status */
+	hwctx->status = HWCTX_STAT_READY;
+
+	return 0;
+
+pm_suspend_put:
+	amdxdna_pm_suspend_put(xdna);
+free_cus:
+	kfree(hwctx->cus);
+	hwctx->cus = NULL;
+	return ret;
+}
+
+static void aie2_cmd_wait(struct amdxdna_hwctx *hwctx, u64 seq)
+{
+	struct dma_fence *out_fence = aie2_cmd_get_out_fence(hwctx, seq);
+
+	if (!out_fence) {
+		XDNA_ERR(hwctx->client->xdna, "Failed to get fence");
+		return;
+	}
+
+	dma_fence_wait_timeout(out_fence, false, MAX_SCHEDULE_TIMEOUT);
+	dma_fence_put(out_fence);
+}
+
+static int aie2_hwctx_cfg_debug_bo(struct amdxdna_hwctx *hwctx, u32 bo_hdl,
+				   bool attach)
+{
+	struct amdxdna_client *client = hwctx->client;
+	struct amdxdna_dev *xdna = client->xdna;
+	struct amdxdna_drv_cmd cmd = { 0 };
+	struct amdxdna_gem_obj *abo;
+	u64 seq;
+	int ret;
+
+	abo = amdxdna_gem_get_obj(client, bo_hdl, AMDXDNA_BO_DEV);
+	if (!abo) {
+		XDNA_ERR(xdna, "Get bo %d failed", bo_hdl);
+		return -EINVAL;
+	}
+
+	if (attach) {
+		if (abo->assigned_hwctx != AMDXDNA_INVALID_CTX_HANDLE) {
+			ret = -EBUSY;
+			goto put_obj;
+		}
+		cmd.opcode = ATTACH_DEBUG_BO;
+	} else {
+		if (abo->assigned_hwctx != hwctx->id) {
+			ret = -EINVAL;
+			goto put_obj;
+		}
+		cmd.opcode = DETACH_DEBUG_BO;
+	}
+
+	ret = amdxdna_cmd_submit(client, &cmd, AMDXDNA_INVALID_BO_HANDLE,
+				 &bo_hdl, 1, hwctx->id, &seq);
+	if (ret) {
+		XDNA_ERR(xdna, "Submit command failed");
+		goto put_obj;
+	}
+
+	aie2_cmd_wait(hwctx, seq);
+	if (cmd.result) {
+		XDNA_ERR(xdna, "Response failure 0x%x", cmd.result);
+		goto put_obj;
+	}
+
+	if (attach)
+		abo->assigned_hwctx = hwctx->id;
+	else
+		abo->assigned_hwctx = AMDXDNA_INVALID_CTX_HANDLE;
+
+	XDNA_DBG(xdna, "Config debug BO %d to %s", bo_hdl, hwctx->name);
+
+put_obj:
+	amdxdna_gem_put_obj(abo);
+	return ret;
+}
+
+int aie2_hwctx_config(struct amdxdna_hwctx *hwctx, u32 type, u64 value, void *buf, u32 size)
+{
+	struct amdxdna_dev *xdna = hwctx->client->xdna;
+
+	drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock));
+	switch (type) {
+	case DRM_AMDXDNA_HWCTX_CONFIG_CU:
+		return aie2_hwctx_cu_config(hwctx, buf, size);
+	case DRM_AMDXDNA_HWCTX_ASSIGN_DBG_BUF:
+		return aie2_hwctx_cfg_debug_bo(hwctx, (u32)value, true);
+	case DRM_AMDXDNA_HWCTX_REMOVE_DBG_BUF:
+		return aie2_hwctx_cfg_debug_bo(hwctx, (u32)value, false);
+	default:
+		XDNA_DBG(xdna, "Not supported type %d", type);
+		return -EOPNOTSUPP;
+	}
+}
+
+int aie2_hwctx_sync_debug_bo(struct amdxdna_hwctx *hwctx, u32 debug_bo_hdl)
+{
+	struct amdxdna_client *client = hwctx->client;
+	struct amdxdna_dev *xdna = client->xdna;
+	struct amdxdna_drv_cmd cmd = { 0 };
+	u64 seq;
+	int ret;
+
+	cmd.opcode = SYNC_DEBUG_BO;
+	ret = amdxdna_cmd_submit(client, &cmd, AMDXDNA_INVALID_BO_HANDLE,
+				 &debug_bo_hdl, 1, hwctx->id, &seq);
+	if (ret) {
+		XDNA_ERR(xdna, "Submit command failed");
+		return ret;
+	}
+
+	aie2_cmd_wait(hwctx, seq);
+	if (cmd.result) {
+		XDNA_ERR(xdna, "Response failure 0x%x", cmd.result);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int aie2_populate_range(struct amdxdna_gem_obj *abo)
+{
+	struct amdxdna_dev *xdna = to_xdna_dev(to_gobj(abo)->dev);
+	struct amdxdna_umap *mapp;
+	unsigned long timeout;
+	struct mm_struct *mm;
+	bool found;
+	int ret;
+
+	timeout = jiffies + msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT);
+again:
+	found = false;
+	down_write(&xdna->notifier_lock);
+	list_for_each_entry(mapp, &abo->mem.umap_list, node) {
+		if (mapp->invalid) {
+			found = true;
+			break;
+		}
+	}
+
+	if (!found) {
+		abo->mem.map_invalid = false;
+		up_write(&xdna->notifier_lock);
+		return 0;
+	}
+	kref_get(&mapp->refcnt);
+	up_write(&xdna->notifier_lock);
+
+	XDNA_DBG(xdna, "populate memory range %lx %lx",
+		 mapp->vma->vm_start, mapp->vma->vm_end);
+	mm = mapp->notifier.mm;
+	if (!mmget_not_zero(mm)) {
+		amdxdna_umap_put(mapp);
+		return -EFAULT;
+	}
+
+	mapp->range.notifier_seq = mmu_interval_read_begin(&mapp->notifier);
+	mmap_read_lock(mm);
+	ret = hmm_range_fault(&mapp->range);
+	mmap_read_unlock(mm);
+	if (ret) {
+		if (time_after(jiffies, timeout)) {
+			ret = -ETIME;
+			goto put_mm;
+		}
+
+		if (ret == -EBUSY) {
+			amdxdna_umap_put(mapp);
+			goto again;
+		}
+
+		goto put_mm;
+	}
+
+	down_write(&xdna->notifier_lock);
+	if (mmu_interval_read_retry(&mapp->notifier, mapp->range.notifier_seq)) {
+		up_write(&xdna->notifier_lock);
+		amdxdna_umap_put(mapp);
+		goto again;
+	}
+	mapp->invalid = false;
+	up_write(&xdna->notifier_lock);
+	amdxdna_umap_put(mapp);
+	goto again;
+
+put_mm:
+	amdxdna_umap_put(mapp);
+	mmput(mm);
+	return ret;
+}
+
+int aie2_cmd_submit(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job, u64 *seq)
+{
+	struct amdxdna_dev *xdna = hwctx->client->xdna;
+	struct ww_acquire_ctx acquire_ctx;
+	struct dma_fence_chain *chain;
+	struct amdxdna_gem_obj *abo;
+	unsigned long timeout = 0;
+	int ret, i;
+
+	ret = down_interruptible(&hwctx->priv->job_sem);
+	if (ret) {
+		XDNA_ERR(xdna, "Grab job sem failed, ret %d", ret);
+		return ret;
+	}
+
+	chain = dma_fence_chain_alloc();
+	if (!chain) {
+		XDNA_ERR(xdna, "Alloc fence chain failed");
+		ret = -ENOMEM;
+		goto up_sem;
+	}
+
+	ret = drm_sched_job_init(&job->base, &hwctx->priv->entity, 1, hwctx,
+				 hwctx->client->filp->client_id);
+	if (ret) {
+		XDNA_ERR(xdna, "DRM job init failed, ret %d", ret);
+		goto free_chain;
+	}
+
+	ret = amdxdna_pm_resume_get(xdna);
+	if (ret)
+		goto cleanup_job;
+
+retry:
+	ret = drm_gem_lock_reservations(job->bos, job->bo_cnt, &acquire_ctx);
+	if (ret) {
+		XDNA_WARN(xdna, "Failed to lock BOs, ret %d", ret);
+		goto suspend_put;
+	}
+
+	for (i = 0; i < job->bo_cnt; i++) {
+		ret = dma_resv_reserve_fences(job->bos[i]->resv, 1);
+		if (ret) {
+			XDNA_WARN(xdna, "Failed to reserve fences %d", ret);
+			drm_gem_unlock_reservations(job->bos, job->bo_cnt, &acquire_ctx);
+			goto suspend_put;
+		}
+	}
+
+	down_read(&xdna->notifier_lock);
+	for (i = 0; i < job->bo_cnt; i++) {
+		abo = to_xdna_obj(job->bos[i]);
+		if (abo->mem.map_invalid) {
+			up_read(&xdna->notifier_lock);
+			drm_gem_unlock_reservations(job->bos, job->bo_cnt, &acquire_ctx);
+			if (!timeout) {
+				timeout = jiffies +
+					msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT);
+			} else if (time_after(jiffies, timeout)) {
+				ret = -ETIME;
+				goto suspend_put;
+			}
+
+			ret = aie2_populate_range(abo);
+			if (ret)
+				goto suspend_put;
+			goto retry;
+		}
+	}
+
+	mutex_lock(&hwctx->priv->io_lock);
+	drm_sched_job_arm(&job->base);
+	job->out_fence = dma_fence_get(&job->base.s_fence->finished);
+	for (i = 0; i < job->bo_cnt; i++)
+		dma_resv_add_fence(job->bos[i]->resv, job->out_fence, DMA_RESV_USAGE_WRITE);
+	job->seq = hwctx->priv->seq++;
+	kref_get(&job->refcnt);
+	drm_sched_entity_push_job(&job->base);
+
+	*seq = job->seq;
+	drm_syncobj_add_point(hwctx->priv->syncobj, chain, job->out_fence, *seq);
+	mutex_unlock(&hwctx->priv->io_lock);
+
+	up_read(&xdna->notifier_lock);
+	drm_gem_unlock_reservations(job->bos, job->bo_cnt, &acquire_ctx);
+
+	aie2_job_put(job);
+	atomic64_inc(&hwctx->job_submit_cnt);
+
+	return 0;
+
+suspend_put:
+	amdxdna_pm_suspend_put(xdna);
+cleanup_job:
+	drm_sched_job_cleanup(&job->base);
+free_chain:
+	dma_fence_chain_free(chain);
+up_sem:
+	up(&hwctx->priv->job_sem);
+	job->job_done = true;
+	return ret;
+}
+
+void aie2_hmm_invalidate(struct amdxdna_gem_obj *abo,
+			 unsigned long cur_seq)
+{
+	struct amdxdna_dev *xdna = to_xdna_dev(to_gobj(abo)->dev);
+	struct drm_gem_object *gobj = to_gobj(abo);
+	long ret;
+
+	ret = dma_resv_wait_timeout(gobj->resv, DMA_RESV_USAGE_BOOKKEEP,
+				    true, MAX_SCHEDULE_TIMEOUT);
+	if (!ret || ret == -ERESTARTSYS)
+		XDNA_ERR(xdna, "Failed to wait for bo, ret %ld", ret);
+}
diff --git a/drivers/accel/amdxdna/aie2_error.c b/drivers/accel/amdxdna/aie2_error.c
new file mode 100644
index 000000000000..d452008ec4f4
--- /dev/null
+++ b/drivers/accel/amdxdna/aie2_error.c
@@ -0,0 +1,419 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023-2024, Advanced Micro Devices, Inc.
+ */
+
+#include <drm/drm_cache.h>
+#include <drm/drm_device.h>
+#include <drm/drm_print.h>
+#include <drm/gpu_scheduler.h>
+#include <linux/dma-mapping.h>
+#include <linux/kthread.h>
+#include <linux/kernel.h>
+
+#include "aie2_msg_priv.h"
+#include "aie2_pci.h"
+#include "amdxdna_error.h"
+#include "amdxdna_mailbox.h"
+#include "amdxdna_pci_drv.h"
+
+struct async_event {
+	struct amdxdna_dev_hdl		*ndev;
+	struct async_event_msg_resp	resp;
+	struct workqueue_struct		*wq;
+	struct work_struct		work;
+	u8				*buf;
+	dma_addr_t			addr;
+	u32				size;
+};
+
+struct async_events {
+	struct workqueue_struct		*wq;
+	u8				*buf;
+	dma_addr_t			addr;
+	u32				size;
+	u32				event_cnt;
+	struct async_event		event[] __counted_by(event_cnt);
+};
+
+/*
+ * Below enum, struct and lookup tables are porting from XAIE util header file.
+ *
+ * Below data is defined by AIE device and it is used for decode error message
+ * from the device.
+ */
+
+enum aie_module_type {
+	AIE_MEM_MOD = 0,
+	AIE_CORE_MOD,
+	AIE_PL_MOD,
+	AIE_UNKNOWN_MOD,
+};
+
+enum aie_error_category {
+	AIE_ERROR_SATURATION = 0,
+	AIE_ERROR_FP,
+	AIE_ERROR_STREAM,
+	AIE_ERROR_ACCESS,
+	AIE_ERROR_BUS,
+	AIE_ERROR_INSTRUCTION,
+	AIE_ERROR_ECC,
+	AIE_ERROR_LOCK,
+	AIE_ERROR_DMA,
+	AIE_ERROR_MEM_PARITY,
+	/* Unknown is not from XAIE, added for better category */
+	AIE_ERROR_UNKNOWN,
+};
+
+/* Don't pack, unless XAIE side changed */
+struct aie_error {
+	__u8			row;
+	__u8			col;
+	__u32			mod_type;
+	__u8			event_id;
+};
+
+struct aie_err_info {
+	u32			err_cnt;
+	u32			ret_code;
+	u32			rsvd;
+	struct aie_error	payload[] __counted_by(err_cnt);
+};
+
+struct aie_event_category {
+	u8			event_id;
+	enum aie_error_category category;
+};
+
+#define EVENT_CATEGORY(id, cat) { id, cat }
+static const struct aie_event_category aie_ml_mem_event_cat[] = {
+	EVENT_CATEGORY(88U,  AIE_ERROR_ECC),
+	EVENT_CATEGORY(90U,  AIE_ERROR_ECC),
+	EVENT_CATEGORY(91U,  AIE_ERROR_MEM_PARITY),
+	EVENT_CATEGORY(92U,  AIE_ERROR_MEM_PARITY),
+	EVENT_CATEGORY(93U,  AIE_ERROR_MEM_PARITY),
+	EVENT_CATEGORY(94U,  AIE_ERROR_MEM_PARITY),
+	EVENT_CATEGORY(95U,  AIE_ERROR_MEM_PARITY),
+	EVENT_CATEGORY(96U,  AIE_ERROR_MEM_PARITY),
+	EVENT_CATEGORY(97U,  AIE_ERROR_DMA),
+	EVENT_CATEGORY(98U,  AIE_ERROR_DMA),
+	EVENT_CATEGORY(99U,  AIE_ERROR_DMA),
+	EVENT_CATEGORY(100U, AIE_ERROR_DMA),
+	EVENT_CATEGORY(101U, AIE_ERROR_LOCK),
+};
+
+static const struct aie_event_category aie_ml_core_event_cat[] = {
+	EVENT_CATEGORY(55U, AIE_ERROR_ACCESS),
+	EVENT_CATEGORY(56U, AIE_ERROR_STREAM),
+	EVENT_CATEGORY(57U, AIE_ERROR_STREAM),
+	EVENT_CATEGORY(58U, AIE_ERROR_BUS),
+	EVENT_CATEGORY(59U, AIE_ERROR_INSTRUCTION),
+	EVENT_CATEGORY(60U, AIE_ERROR_ACCESS),
+	EVENT_CATEGORY(62U, AIE_ERROR_ECC),
+	EVENT_CATEGORY(64U, AIE_ERROR_ECC),
+	EVENT_CATEGORY(65U, AIE_ERROR_ACCESS),
+	EVENT_CATEGORY(66U, AIE_ERROR_ACCESS),
+	EVENT_CATEGORY(67U, AIE_ERROR_LOCK),
+	EVENT_CATEGORY(70U, AIE_ERROR_INSTRUCTION),
+	EVENT_CATEGORY(71U, AIE_ERROR_STREAM),
+	EVENT_CATEGORY(72U, AIE_ERROR_BUS),
+};
+
+static const struct aie_event_category aie_ml_mem_tile_event_cat[] = {
+	EVENT_CATEGORY(130U, AIE_ERROR_ECC),
+	EVENT_CATEGORY(132U, AIE_ERROR_ECC),
+	EVENT_CATEGORY(133U, AIE_ERROR_DMA),
+	EVENT_CATEGORY(134U, AIE_ERROR_DMA),
+	EVENT_CATEGORY(135U, AIE_ERROR_STREAM),
+	EVENT_CATEGORY(136U, AIE_ERROR_STREAM),
+	EVENT_CATEGORY(137U, AIE_ERROR_STREAM),
+	EVENT_CATEGORY(138U, AIE_ERROR_BUS),
+	EVENT_CATEGORY(139U, AIE_ERROR_LOCK),
+};
+
+static const struct aie_event_category aie_ml_shim_tile_event_cat[] = {
+	EVENT_CATEGORY(64U, AIE_ERROR_BUS),
+	EVENT_CATEGORY(65U, AIE_ERROR_STREAM),
+	EVENT_CATEGORY(66U, AIE_ERROR_STREAM),
+	EVENT_CATEGORY(67U, AIE_ERROR_BUS),
+	EVENT_CATEGORY(68U, AIE_ERROR_BUS),
+	EVENT_CATEGORY(69U, AIE_ERROR_BUS),
+	EVENT_CATEGORY(70U, AIE_ERROR_BUS),
+	EVENT_CATEGORY(71U, AIE_ERROR_BUS),
+	EVENT_CATEGORY(72U, AIE_ERROR_DMA),
+	EVENT_CATEGORY(73U, AIE_ERROR_DMA),
+	EVENT_CATEGORY(74U, AIE_ERROR_LOCK),
+};
+
+static const enum amdxdna_error_num aie_cat_err_num_map[] = {
+	[AIE_ERROR_SATURATION] = AMDXDNA_ERROR_NUM_AIE_SATURATION,
+	[AIE_ERROR_FP] = AMDXDNA_ERROR_NUM_AIE_FP,
+	[AIE_ERROR_STREAM] = AMDXDNA_ERROR_NUM_AIE_STREAM,
+	[AIE_ERROR_ACCESS] = AMDXDNA_ERROR_NUM_AIE_ACCESS,
+	[AIE_ERROR_BUS] = AMDXDNA_ERROR_NUM_AIE_BUS,
+	[AIE_ERROR_INSTRUCTION] = AMDXDNA_ERROR_NUM_AIE_INSTRUCTION,
+	[AIE_ERROR_ECC] = AMDXDNA_ERROR_NUM_AIE_ECC,
+	[AIE_ERROR_LOCK] = AMDXDNA_ERROR_NUM_AIE_LOCK,
+	[AIE_ERROR_DMA] = AMDXDNA_ERROR_NUM_AIE_DMA,
+	[AIE_ERROR_MEM_PARITY] = AMDXDNA_ERROR_NUM_AIE_MEM_PARITY,
+	[AIE_ERROR_UNKNOWN] = AMDXDNA_ERROR_NUM_UNKNOWN,
+};
+
+static_assert(ARRAY_SIZE(aie_cat_err_num_map) == AIE_ERROR_UNKNOWN + 1);
+
+static const enum amdxdna_error_module aie_err_mod_map[] = {
+	[AIE_MEM_MOD] = AMDXDNA_ERROR_MODULE_AIE_MEMORY,
+	[AIE_CORE_MOD] = AMDXDNA_ERROR_MODULE_AIE_CORE,
+	[AIE_PL_MOD] = AMDXDNA_ERROR_MODULE_AIE_PL,
+	[AIE_UNKNOWN_MOD] = AMDXDNA_ERROR_MODULE_UNKNOWN,
+};
+
+static_assert(ARRAY_SIZE(aie_err_mod_map) == AIE_UNKNOWN_MOD + 1);
+
+static enum aie_error_category
+aie_get_error_category(u8 row, u8 event_id, enum aie_module_type mod_type)
+{
+	const struct aie_event_category *lut;
+	int num_entry;
+	int i;
+
+	switch (mod_type) {
+	case AIE_PL_MOD:
+		lut = aie_ml_shim_tile_event_cat;
+		num_entry = ARRAY_SIZE(aie_ml_shim_tile_event_cat);
+		break;
+	case AIE_CORE_MOD:
+		lut = aie_ml_core_event_cat;
+		num_entry = ARRAY_SIZE(aie_ml_core_event_cat);
+		break;
+	case AIE_MEM_MOD:
+		if (row == 1) {
+			lut = aie_ml_mem_tile_event_cat;
+			num_entry = ARRAY_SIZE(aie_ml_mem_tile_event_cat);
+		} else {
+			lut = aie_ml_mem_event_cat;
+			num_entry = ARRAY_SIZE(aie_ml_mem_event_cat);
+		}
+		break;
+	default:
+		return AIE_ERROR_UNKNOWN;
+	}
+
+	for (i = 0; i < num_entry; i++) {
+		if (event_id != lut[i].event_id)
+			continue;
+
+		if (lut[i].category > AIE_ERROR_UNKNOWN)
+			return AIE_ERROR_UNKNOWN;
+
+		return lut[i].category;
+	}
+
+	return AIE_ERROR_UNKNOWN;
+}
+
+static void aie2_update_last_async_error(struct amdxdna_dev_hdl *ndev, void *err_info, u32 num_err)
+{
+	struct aie_error *errs = err_info;
+	enum amdxdna_error_module err_mod;
+	enum aie_error_category aie_err;
+	enum amdxdna_error_num err_num;
+	struct aie_error *last_err;
+
+	last_err = &errs[num_err - 1];
+	if (last_err->mod_type >= AIE_UNKNOWN_MOD) {
+		err_num = aie_cat_err_num_map[AIE_ERROR_UNKNOWN];
+		err_mod = aie_err_mod_map[AIE_UNKNOWN_MOD];
+	} else {
+		aie_err = aie_get_error_category(last_err->row,
+						 last_err->event_id,
+						 last_err->mod_type);
+		err_num = aie_cat_err_num_map[aie_err];
+		err_mod = aie_err_mod_map[last_err->mod_type];
+	}
+
+	ndev->last_async_err.err_code = AMDXDNA_ERROR_ENCODE(err_num, err_mod);
+	ndev->last_async_err.ts_us = ktime_to_us(ktime_get_real());
+	ndev->last_async_err.ex_err_code = AMDXDNA_EXTRA_ERR_ENCODE(last_err->row, last_err->col);
+}
+
+static u32 aie2_error_backtrack(struct amdxdna_dev_hdl *ndev, void *err_info, u32 num_err)
+{
+	struct aie_error *errs = err_info;
+	u32 err_col = 0; /* assume that AIE has less than 32 columns */
+	int i;
+
+	/* Get err column bitmap */
+	for (i = 0; i < num_err; i++) {
+		struct aie_error *err = &errs[i];
+		enum aie_error_category cat;
+
+		cat = aie_get_error_category(err->row, err->event_id, err->mod_type);
+		XDNA_ERR(ndev->xdna, "Row: %d, Col: %d, module %d, event ID %d, category %d",
+			 err->row, err->col, err->mod_type,
+			 err->event_id, cat);
+
+		if (err->col >= 32) {
+			XDNA_WARN(ndev->xdna, "Invalid column number");
+			break;
+		}
+
+		err_col |= (1 << err->col);
+	}
+
+	return err_col;
+}
+
+static int aie2_error_async_cb(void *handle, void __iomem *data, size_t size)
+{
+	struct async_event *e = handle;
+
+	if (data) {
+		e->resp.type = readl(data + offsetof(struct async_event_msg_resp, type));
+		wmb(); /* Update status in the end, so that no lock for here */
+		e->resp.status = readl(data + offsetof(struct async_event_msg_resp, status));
+	}
+	queue_work(e->wq, &e->work);
+	return 0;
+}
+
+static int aie2_error_event_send(struct async_event *e)
+{
+	drm_clflush_virt_range(e->buf, e->size); /* device can access */
+	return aie2_register_asyn_event_msg(e->ndev, e->addr, e->size, e,
+					    aie2_error_async_cb);
+}
+
+static void aie2_error_worker(struct work_struct *err_work)
+{
+	struct aie_err_info *info;
+	struct amdxdna_dev *xdna;
+	struct async_event *e;
+	u32 max_err;
+	u32 err_col;
+
+	e = container_of(err_work, struct async_event, work);
+
+	xdna = e->ndev->xdna;
+
+	if (e->resp.status == MAX_AIE2_STATUS_CODE)
+		return;
+
+	e->resp.status = MAX_AIE2_STATUS_CODE;
+
+	print_hex_dump_debug("AIE error: ", DUMP_PREFIX_OFFSET, 16, 4,
+			     e->buf, 0x100, false);
+
+	info = (struct aie_err_info *)e->buf;
+	XDNA_DBG(xdna, "Error count %d return code %d", info->err_cnt, info->ret_code);
+
+	max_err = (e->size - sizeof(*info)) / sizeof(struct aie_error);
+	if (unlikely(info->err_cnt > max_err)) {
+		WARN_ONCE(1, "Error count too large %d\n", info->err_cnt);
+		return;
+	}
+	err_col = aie2_error_backtrack(e->ndev, info->payload, info->err_cnt);
+	if (!err_col) {
+		XDNA_WARN(xdna, "Did not get error column");
+		return;
+	}
+
+	mutex_lock(&xdna->dev_lock);
+	aie2_update_last_async_error(e->ndev, info->payload, info->err_cnt);
+
+	/* Re-sent this event to firmware */
+	if (aie2_error_event_send(e))
+		XDNA_WARN(xdna, "Unable to register async event");
+	mutex_unlock(&xdna->dev_lock);
+}
+
+void aie2_error_async_events_free(struct amdxdna_dev_hdl *ndev)
+{
+	struct amdxdna_dev *xdna = ndev->xdna;
+	struct async_events *events;
+
+	events = ndev->async_events;
+
+	mutex_unlock(&xdna->dev_lock);
+	destroy_workqueue(events->wq);
+	mutex_lock(&xdna->dev_lock);
+
+	dma_free_noncoherent(xdna->ddev.dev, events->size, events->buf,
+			     events->addr, DMA_FROM_DEVICE);
+	kfree(events);
+}
+
+int aie2_error_async_events_alloc(struct amdxdna_dev_hdl *ndev)
+{
+	struct amdxdna_dev *xdna = ndev->xdna;
+	u32 total_col = ndev->total_col;
+	u32 total_size = ASYNC_BUF_SIZE * total_col;
+	struct async_events *events;
+	int i, ret;
+
+	events = kzalloc(struct_size(events, event, total_col), GFP_KERNEL);
+	if (!events)
+		return -ENOMEM;
+
+	events->buf = dma_alloc_noncoherent(xdna->ddev.dev, total_size, &events->addr,
+					    DMA_FROM_DEVICE, GFP_KERNEL);
+	if (!events->buf) {
+		ret = -ENOMEM;
+		goto free_events;
+	}
+	events->size = total_size;
+	events->event_cnt = total_col;
+
+	events->wq = alloc_ordered_workqueue("async_wq", 0);
+	if (!events->wq) {
+		ret = -ENOMEM;
+		goto free_buf;
+	}
+
+	for (i = 0; i < events->event_cnt; i++) {
+		struct async_event *e = &events->event[i];
+		u32 offset = i * ASYNC_BUF_SIZE;
+
+		e->ndev = ndev;
+		e->wq = events->wq;
+		e->buf = &events->buf[offset];
+		e->addr = events->addr + offset;
+		e->size = ASYNC_BUF_SIZE;
+		e->resp.status = MAX_AIE2_STATUS_CODE;
+		INIT_WORK(&e->work, aie2_error_worker);
+
+		ret = aie2_error_event_send(e);
+		if (ret)
+			goto free_wq;
+	}
+
+	ndev->async_events = events;
+
+	XDNA_DBG(xdna, "Async event count %d, buf total size 0x%x",
+		 events->event_cnt, events->size);
+	return 0;
+
+free_wq:
+	destroy_workqueue(events->wq);
+free_buf:
+	dma_free_noncoherent(xdna->ddev.dev, events->size, events->buf,
+			     events->addr, DMA_FROM_DEVICE);
+free_events:
+	kfree(events);
+	return ret;
+}
+
+int aie2_get_array_async_error(struct amdxdna_dev_hdl *ndev, struct amdxdna_drm_get_array *args)
+{
+	struct amdxdna_dev *xdna = ndev->xdna;
+
+	drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock));
+
+	args->num_element = 1;
+	args->element_size = sizeof(ndev->last_async_err);
+	if (copy_to_user(u64_to_user_ptr(args->buffer),
+			 &ndev->last_async_err, args->element_size))
+		return -EFAULT;
+
+	return 0;
+}
diff --git a/drivers/accel/amdxdna/aie2_message.c b/drivers/accel/amdxdna/aie2_message.c
new file mode 100644
index 000000000000..d493bb1c3360
--- /dev/null
+++ b/drivers/accel/amdxdna/aie2_message.c
@@ -0,0 +1,1074 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023-2024, Advanced Micro Devices, Inc.
+ */
+
+#include <drm/amdxdna_accel.h>
+#include <drm/drm_cache.h>
+#include <drm/drm_device.h>
+#include <drm/drm_gem.h>
+#include <drm/drm_gem_shmem_helper.h>
+#include <drm/drm_print.h>
+#include <drm/gpu_scheduler.h>
+#include <linux/bitfield.h>
+#include <linux/errno.h>
+#include <linux/pci.h>
+#include <linux/types.h>
+#include <linux/xarray.h>
+
+#include "aie2_msg_priv.h"
+#include "aie2_pci.h"
+#include "amdxdna_ctx.h"
+#include "amdxdna_gem.h"
+#include "amdxdna_mailbox.h"
+#include "amdxdna_mailbox_helper.h"
+#include "amdxdna_pci_drv.h"
+
+#define DECLARE_AIE2_MSG(name, op) \
+	DECLARE_XDNA_MSG_COMMON(name, op, MAX_AIE2_STATUS_CODE)
+
+#define EXEC_MSG_OPS(xdna)	((xdna)->dev_handle->exec_msg_ops)
+
+static int aie2_send_mgmt_msg_wait(struct amdxdna_dev_hdl *ndev,
+				   struct xdna_mailbox_msg *msg)
+{
+	struct amdxdna_dev *xdna = ndev->xdna;
+	struct xdna_notify *hdl = msg->handle;
+	int ret;
+
+	if (!ndev->mgmt_chann)
+		return -ENODEV;
+
+	drm_WARN_ON(&xdna->ddev, xdna->rpm_on && !mutex_is_locked(&xdna->dev_lock));
+	ret = xdna_send_msg_wait(xdna, ndev->mgmt_chann, msg);
+	if (ret == -ETIME) {
+		xdna_mailbox_stop_channel(ndev->mgmt_chann);
+		xdna_mailbox_destroy_channel(ndev->mgmt_chann);
+		ndev->mgmt_chann = NULL;
+	}
+
+	if (!ret && *hdl->status != AIE2_STATUS_SUCCESS) {
+		XDNA_ERR(xdna, "command opcode 0x%x failed, status 0x%x",
+			 msg->opcode, *hdl->data);
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+int aie2_suspend_fw(struct amdxdna_dev_hdl *ndev)
+{
+	DECLARE_AIE2_MSG(suspend, MSG_OP_SUSPEND);
+
+	return aie2_send_mgmt_msg_wait(ndev, &msg);
+}
+
+int aie2_resume_fw(struct amdxdna_dev_hdl *ndev)
+{
+	DECLARE_AIE2_MSG(suspend, MSG_OP_RESUME);
+
+	return aie2_send_mgmt_msg_wait(ndev, &msg);
+}
+
+int aie2_set_runtime_cfg(struct amdxdna_dev_hdl *ndev, u32 type, u64 value)
+{
+	DECLARE_AIE2_MSG(set_runtime_cfg, MSG_OP_SET_RUNTIME_CONFIG);
+	int ret;
+
+	req.type = type;
+	req.value = value;
+
+	ret = aie2_send_mgmt_msg_wait(ndev, &msg);
+	if (ret) {
+		XDNA_ERR(ndev->xdna, "Failed to set runtime config, ret %d", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+int aie2_get_runtime_cfg(struct amdxdna_dev_hdl *ndev, u32 type, u64 *value)
+{
+	DECLARE_AIE2_MSG(get_runtime_cfg, MSG_OP_GET_RUNTIME_CONFIG);
+	int ret;
+
+	req.type = type;
+	ret = aie2_send_mgmt_msg_wait(ndev, &msg);
+	if (ret) {
+		XDNA_ERR(ndev->xdna, "Failed to get runtime config, ret %d", ret);
+		return ret;
+	}
+
+	*value = resp.value;
+	return 0;
+}
+
+int aie2_assign_mgmt_pasid(struct amdxdna_dev_hdl *ndev, u16 pasid)
+{
+	DECLARE_AIE2_MSG(assign_mgmt_pasid, MSG_OP_ASSIGN_MGMT_PASID);
+
+	req.pasid = pasid;
+
+	return aie2_send_mgmt_msg_wait(ndev, &msg);
+}
+
+int aie2_query_aie_version(struct amdxdna_dev_hdl *ndev, struct aie_version *version)
+{
+	DECLARE_AIE2_MSG(aie_version_info, MSG_OP_QUERY_AIE_VERSION);
+	struct amdxdna_dev *xdna = ndev->xdna;
+	int ret;
+
+	ret = aie2_send_mgmt_msg_wait(ndev, &msg);
+	if (ret)
+		return ret;
+
+	XDNA_DBG(xdna, "Query AIE version - major: %u minor: %u completed",
+		 resp.major, resp.minor);
+
+	version->major = resp.major;
+	version->minor = resp.minor;
+
+	return 0;
+}
+
+int aie2_query_aie_metadata(struct amdxdna_dev_hdl *ndev, struct aie_metadata *metadata)
+{
+	DECLARE_AIE2_MSG(aie_tile_info, MSG_OP_QUERY_AIE_TILE_INFO);
+	int ret;
+
+	ret = aie2_send_mgmt_msg_wait(ndev, &msg);
+	if (ret)
+		return ret;
+
+	metadata->size = resp.info.size;
+	metadata->cols = resp.info.cols;
+	metadata->rows = resp.info.rows;
+
+	metadata->version.major = resp.info.major;
+	metadata->version.minor = resp.info.minor;
+
+	metadata->core.row_count = resp.info.core_rows;
+	metadata->core.row_start = resp.info.core_row_start;
+	metadata->core.dma_channel_count = resp.info.core_dma_channels;
+	metadata->core.lock_count = resp.info.core_locks;
+	metadata->core.event_reg_count = resp.info.core_events;
+
+	metadata->mem.row_count = resp.info.mem_rows;
+	metadata->mem.row_start = resp.info.mem_row_start;
+	metadata->mem.dma_channel_count = resp.info.mem_dma_channels;
+	metadata->mem.lock_count = resp.info.mem_locks;
+	metadata->mem.event_reg_count = resp.info.mem_events;
+
+	metadata->shim.row_count = resp.info.shim_rows;
+	metadata->shim.row_start = resp.info.shim_row_start;
+	metadata->shim.dma_channel_count = resp.info.shim_dma_channels;
+	metadata->shim.lock_count = resp.info.shim_locks;
+	metadata->shim.event_reg_count = resp.info.shim_events;
+
+	return 0;
+}
+
+int aie2_query_firmware_version(struct amdxdna_dev_hdl *ndev,
+				struct amdxdna_fw_ver *fw_ver)
+{
+	DECLARE_AIE2_MSG(firmware_version, MSG_OP_GET_FIRMWARE_VERSION);
+	int ret;
+
+	ret = aie2_send_mgmt_msg_wait(ndev, &msg);
+	if (ret)
+		return ret;
+
+	fw_ver->major = resp.major;
+	fw_ver->minor = resp.minor;
+	fw_ver->sub = resp.sub;
+	fw_ver->build = resp.build;
+
+	return 0;
+}
+
+int aie2_create_context(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwctx)
+{
+	DECLARE_AIE2_MSG(create_ctx, MSG_OP_CREATE_CONTEXT);
+	struct amdxdna_dev *xdna = ndev->xdna;
+	struct xdna_mailbox_chann_res x2i;
+	struct xdna_mailbox_chann_res i2x;
+	struct cq_pair *cq_pair;
+	u32 intr_reg;
+	int ret;
+
+	req.aie_type = 1;
+	req.start_col = hwctx->start_col;
+	req.num_col = hwctx->num_col;
+	req.num_cq_pairs_requested = 1;
+	req.pasid = hwctx->client->pasid;
+	req.context_priority = 2;
+
+	ret = aie2_send_mgmt_msg_wait(ndev, &msg);
+	if (ret)
+		return ret;
+
+	hwctx->fw_ctx_id = resp.context_id;
+	WARN_ONCE(hwctx->fw_ctx_id == -1, "Unexpected context id");
+
+	if (ndev->force_preempt_enabled) {
+		ret = aie2_runtime_cfg(ndev, AIE2_RT_CFG_FORCE_PREEMPT, &hwctx->fw_ctx_id);
+		if (ret) {
+			XDNA_ERR(xdna, "failed to enable force preempt %d", ret);
+			return ret;
+		}
+	}
+
+	cq_pair = &resp.cq_pair[0];
+	x2i.mb_head_ptr_reg = AIE2_MBOX_OFF(ndev, cq_pair->x2i_q.head_addr);
+	x2i.mb_tail_ptr_reg = AIE2_MBOX_OFF(ndev, cq_pair->x2i_q.tail_addr);
+	x2i.rb_start_addr   = AIE2_SRAM_OFF(ndev, cq_pair->x2i_q.buf_addr);
+	x2i.rb_size	    = cq_pair->x2i_q.buf_size;
+
+	i2x.mb_head_ptr_reg = AIE2_MBOX_OFF(ndev, cq_pair->i2x_q.head_addr);
+	i2x.mb_tail_ptr_reg = AIE2_MBOX_OFF(ndev, cq_pair->i2x_q.tail_addr);
+	i2x.rb_start_addr   = AIE2_SRAM_OFF(ndev, cq_pair->i2x_q.buf_addr);
+	i2x.rb_size	    = cq_pair->i2x_q.buf_size;
+
+	ret = pci_irq_vector(to_pci_dev(xdna->ddev.dev), resp.msix_id);
+	if (ret == -EINVAL) {
+		XDNA_ERR(xdna, "not able to create channel");
+		goto out_destroy_context;
+	}
+
+	intr_reg = i2x.mb_head_ptr_reg + 4;
+	hwctx->priv->mbox_chann = xdna_mailbox_create_channel(ndev->mbox, &x2i, &i2x,
+							      intr_reg, ret);
+	if (!hwctx->priv->mbox_chann) {
+		XDNA_ERR(xdna, "not able to create channel");
+		ret = -EINVAL;
+		goto out_destroy_context;
+	}
+	ndev->hwctx_num++;
+
+	XDNA_DBG(xdna, "%s mailbox channel irq: %d, msix_id: %d",
+		 hwctx->name, ret, resp.msix_id);
+	XDNA_DBG(xdna, "%s created fw ctx %d pasid %d", hwctx->name,
+		 hwctx->fw_ctx_id, hwctx->client->pasid);
+
+	return 0;
+
+out_destroy_context:
+	aie2_destroy_context(ndev, hwctx);
+	return ret;
+}
+
+int aie2_destroy_context(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwctx)
+{
+	DECLARE_AIE2_MSG(destroy_ctx, MSG_OP_DESTROY_CONTEXT);
+	struct amdxdna_dev *xdna = ndev->xdna;
+	int ret;
+
+	if (hwctx->fw_ctx_id == -1)
+		return 0;
+
+	xdna_mailbox_stop_channel(hwctx->priv->mbox_chann);
+
+	req.context_id = hwctx->fw_ctx_id;
+	ret = aie2_send_mgmt_msg_wait(ndev, &msg);
+	if (ret)
+		XDNA_WARN(xdna, "%s destroy context failed, ret %d", hwctx->name, ret);
+
+	xdna_mailbox_destroy_channel(hwctx->priv->mbox_chann);
+	XDNA_DBG(xdna, "%s destroyed fw ctx %d", hwctx->name,
+		 hwctx->fw_ctx_id);
+	hwctx->priv->mbox_chann = NULL;
+	hwctx->fw_ctx_id = -1;
+	ndev->hwctx_num--;
+
+	return ret;
+}
+
+int aie2_map_host_buf(struct amdxdna_dev_hdl *ndev, u32 context_id, u64 addr, u64 size)
+{
+	DECLARE_AIE2_MSG(map_host_buffer, MSG_OP_MAP_HOST_BUFFER);
+	struct amdxdna_dev *xdna = ndev->xdna;
+	int ret;
+
+	req.context_id = context_id;
+	req.buf_addr = addr;
+	req.buf_size = size;
+	ret = aie2_send_mgmt_msg_wait(ndev, &msg);
+	if (ret)
+		return ret;
+
+	XDNA_DBG(xdna, "fw ctx %d map host buf addr 0x%llx size 0x%llx",
+		 context_id, addr, size);
+
+	return 0;
+}
+
+static int amdxdna_hwctx_col_map(struct amdxdna_hwctx *hwctx, void *arg)
+{
+	u32 *bitmap = arg;
+
+	*bitmap |= GENMASK(hwctx->start_col + hwctx->num_col - 1, hwctx->start_col);
+
+	return 0;
+}
+
+int aie2_query_status(struct amdxdna_dev_hdl *ndev, char __user *buf,
+		      u32 size, u32 *cols_filled)
+{
+	DECLARE_AIE2_MSG(aie_column_info, MSG_OP_QUERY_COL_STATUS);
+	struct amdxdna_dev *xdna = ndev->xdna;
+	struct amdxdna_client *client;
+	dma_addr_t dma_addr;
+	u32 aie_bitmap = 0;
+	u8 *buff_addr;
+	int ret;
+
+	buff_addr = dma_alloc_noncoherent(xdna->ddev.dev, size, &dma_addr,
+					  DMA_FROM_DEVICE, GFP_KERNEL);
+	if (!buff_addr)
+		return -ENOMEM;
+
+	/* Go through each hardware context and mark the AIE columns that are active */
+	list_for_each_entry(client, &xdna->client_list, node)
+		amdxdna_hwctx_walk(client, &aie_bitmap, amdxdna_hwctx_col_map);
+
+	*cols_filled = 0;
+	req.dump_buff_addr = dma_addr;
+	req.dump_buff_size = size;
+	req.num_cols = hweight32(aie_bitmap);
+	req.aie_bitmap = aie_bitmap;
+
+	drm_clflush_virt_range(buff_addr, size); /* device can access */
+	ret = aie2_send_mgmt_msg_wait(ndev, &msg);
+	if (ret) {
+		XDNA_ERR(xdna, "Error during NPU query, status %d", ret);
+		goto fail;
+	}
+
+	XDNA_DBG(xdna, "Query NPU status completed");
+
+	if (size < resp.size) {
+		ret = -EINVAL;
+		XDNA_ERR(xdna, "Bad buffer size. Available: %u. Needs: %u", size, resp.size);
+		goto fail;
+	}
+
+	if (copy_to_user(buf, buff_addr, resp.size)) {
+		ret = -EFAULT;
+		XDNA_ERR(xdna, "Failed to copy NPU status to user space");
+		goto fail;
+	}
+
+	*cols_filled = aie_bitmap;
+
+fail:
+	dma_free_noncoherent(xdna->ddev.dev, size, buff_addr, dma_addr, DMA_FROM_DEVICE);
+	return ret;
+}
+
+int aie2_query_telemetry(struct amdxdna_dev_hdl *ndev,
+			 char __user *buf, u32 size,
+			 struct amdxdna_drm_query_telemetry_header *header)
+{
+	DECLARE_AIE2_MSG(get_telemetry, MSG_OP_GET_TELEMETRY);
+	struct amdxdna_dev *xdna = ndev->xdna;
+	dma_addr_t dma_addr;
+	u8 *addr;
+	int ret;
+
+	if (header->type >= MAX_TELEMETRY_TYPE)
+		return -EINVAL;
+
+	addr = dma_alloc_noncoherent(xdna->ddev.dev, size, &dma_addr,
+				     DMA_FROM_DEVICE, GFP_KERNEL);
+	if (!addr)
+		return -ENOMEM;
+
+	req.buf_addr = dma_addr;
+	req.buf_size = size;
+	req.type = header->type;
+
+	drm_clflush_virt_range(addr, size); /* device can access */
+	ret = aie2_send_mgmt_msg_wait(ndev, &msg);
+	if (ret) {
+		XDNA_ERR(xdna, "Query telemetry failed, status %d", ret);
+		goto free_buf;
+	}
+
+	if (size < resp.size) {
+		ret = -EINVAL;
+		XDNA_ERR(xdna, "Bad buffer size. Available: %u. Needs: %u", size, resp.size);
+		goto free_buf;
+	}
+
+	if (copy_to_user(buf, addr, resp.size)) {
+		ret = -EFAULT;
+		XDNA_ERR(xdna, "Failed to copy telemetry to user space");
+		goto free_buf;
+	}
+
+	header->major = resp.major;
+	header->minor = resp.minor;
+
+free_buf:
+	dma_free_noncoherent(xdna->ddev.dev, size, addr, dma_addr, DMA_FROM_DEVICE);
+	return ret;
+}
+
+int aie2_register_asyn_event_msg(struct amdxdna_dev_hdl *ndev, dma_addr_t addr, u32 size,
+				 void *handle, int (*cb)(void*, void __iomem *, size_t))
+{
+	struct async_event_msg_req req = { 0 };
+	struct xdna_mailbox_msg msg = {
+		.send_data = (u8 *)&req,
+		.send_size = sizeof(req),
+		.handle = handle,
+		.opcode = MSG_OP_REGISTER_ASYNC_EVENT_MSG,
+		.notify_cb = cb,
+	};
+
+	req.buf_addr = addr;
+	req.buf_size = size;
+
+	XDNA_DBG(ndev->xdna, "Register addr 0x%llx size 0x%x", addr, size);
+	return xdna_mailbox_send_msg(ndev->mgmt_chann, &msg, TX_TIMEOUT);
+}
+
+int aie2_config_cu(struct amdxdna_hwctx *hwctx,
+		   int (*notify_cb)(void *, void __iomem *, size_t))
+{
+	struct mailbox_channel *chann = hwctx->priv->mbox_chann;
+	struct amdxdna_dev *xdna = hwctx->client->xdna;
+	u32 shift = xdna->dev_info->dev_mem_buf_shift;
+	struct config_cu_req req = { 0 };
+	struct xdna_mailbox_msg msg;
+	struct drm_gem_object *gobj;
+	struct amdxdna_gem_obj *abo;
+	int i;
+
+	if (!chann)
+		return -ENODEV;
+
+	if (hwctx->cus->num_cus > MAX_NUM_CUS) {
+		XDNA_DBG(xdna, "Exceed maximum CU %d", MAX_NUM_CUS);
+		return -EINVAL;
+	}
+
+	for (i = 0; i < hwctx->cus->num_cus; i++) {
+		struct amdxdna_cu_config *cu = &hwctx->cus->cu_configs[i];
+
+		if (XDNA_MBZ_DBG(xdna, cu->pad, sizeof(cu->pad)))
+			return -EINVAL;
+
+		gobj = drm_gem_object_lookup(hwctx->client->filp, cu->cu_bo);
+		if (!gobj) {
+			XDNA_ERR(xdna, "Lookup GEM object failed");
+			return -EINVAL;
+		}
+		abo = to_xdna_obj(gobj);
+
+		if (abo->type != AMDXDNA_BO_DEV) {
+			drm_gem_object_put(gobj);
+			XDNA_ERR(xdna, "Invalid BO type");
+			return -EINVAL;
+		}
+
+		req.cfgs[i] = FIELD_PREP(AIE2_MSG_CFG_CU_PDI_ADDR,
+					 abo->mem.dev_addr >> shift);
+		req.cfgs[i] |= FIELD_PREP(AIE2_MSG_CFG_CU_FUNC, cu->cu_func);
+		XDNA_DBG(xdna, "CU %d full addr 0x%llx, cfg 0x%x", i,
+			 abo->mem.dev_addr, req.cfgs[i]);
+		drm_gem_object_put(gobj);
+	}
+	req.num_cus = hwctx->cus->num_cus;
+
+	msg.send_data = (u8 *)&req;
+	msg.send_size = sizeof(req);
+	msg.handle = hwctx;
+	msg.opcode = MSG_OP_CONFIG_CU;
+	msg.notify_cb = notify_cb;
+	return xdna_mailbox_send_msg(chann, &msg, TX_TIMEOUT);
+}
+
+static int aie2_init_exec_cu_req(struct amdxdna_gem_obj *cmd_bo, void *req,
+				 size_t *size, u32 *msg_op)
+{
+	struct execute_buffer_req *cu_req = req;
+	u32 cmd_len;
+	void *cmd;
+
+	cmd = amdxdna_cmd_get_payload(cmd_bo, &cmd_len);
+	if (cmd_len > sizeof(cu_req->payload))
+		return -EINVAL;
+
+	cu_req->cu_idx = amdxdna_cmd_get_cu_idx(cmd_bo);
+	if (cu_req->cu_idx == INVALID_CU_IDX)
+		return -EINVAL;
+
+	memcpy(cu_req->payload, cmd, cmd_len);
+
+	*size = sizeof(*cu_req);
+	*msg_op = MSG_OP_EXECUTE_BUFFER_CF;
+	return 0;
+}
+
+static int aie2_init_exec_dpu_req(struct amdxdna_gem_obj *cmd_bo, void *req,
+				  size_t *size, u32 *msg_op)
+{
+	struct exec_dpu_req *dpu_req = req;
+	struct amdxdna_cmd_start_npu *sn;
+	u32 cmd_len;
+
+	sn = amdxdna_cmd_get_payload(cmd_bo, &cmd_len);
+	if (cmd_len - sizeof(*sn) > sizeof(dpu_req->payload))
+		return -EINVAL;
+
+	dpu_req->cu_idx = amdxdna_cmd_get_cu_idx(cmd_bo);
+	if (dpu_req->cu_idx == INVALID_CU_IDX)
+		return -EINVAL;
+
+	dpu_req->inst_buf_addr = sn->buffer;
+	dpu_req->inst_size = sn->buffer_size;
+	dpu_req->inst_prop_cnt = sn->prop_count;
+	memcpy(dpu_req->payload, sn->prop_args, cmd_len - sizeof(*sn));
+
+	*size = sizeof(*dpu_req);
+	*msg_op = MSG_OP_EXEC_DPU;
+	return 0;
+}
+
+static void aie2_init_exec_chain_req(void *req, u64 slot_addr, size_t size, u32 cmd_cnt)
+{
+	struct cmd_chain_req *chain_req = req;
+
+	chain_req->buf_addr = slot_addr;
+	chain_req->buf_size = size;
+	chain_req->count = cmd_cnt;
+}
+
+static void aie2_init_npu_chain_req(void *req, u64 slot_addr, size_t size, u32 cmd_cnt)
+{
+	struct cmd_chain_npu_req *npu_chain_req = req;
+
+	npu_chain_req->flags = 0;
+	npu_chain_req->reserved = 0;
+	npu_chain_req->buf_addr = slot_addr;
+	npu_chain_req->buf_size = size;
+	npu_chain_req->count = cmd_cnt;
+}
+
+static int
+aie2_cmdlist_fill_cf(struct amdxdna_gem_obj *cmd_bo, void *slot, size_t *size)
+{
+	struct cmd_chain_slot_execbuf_cf *cf_slot = slot;
+	u32 cmd_len;
+	void *cmd;
+
+	cmd = amdxdna_cmd_get_payload(cmd_bo, &cmd_len);
+	if (*size < sizeof(*cf_slot) + cmd_len)
+		return -EINVAL;
+
+	cf_slot->cu_idx = amdxdna_cmd_get_cu_idx(cmd_bo);
+	if (cf_slot->cu_idx == INVALID_CU_IDX)
+		return -EINVAL;
+
+	cf_slot->arg_cnt = cmd_len / sizeof(u32);
+	memcpy(cf_slot->args, cmd, cmd_len);
+	/* Accurate slot size to hint firmware to do necessary copy */
+	*size = sizeof(*cf_slot) + cmd_len;
+	return 0;
+}
+
+static int
+aie2_cmdlist_fill_dpu(struct amdxdna_gem_obj *cmd_bo, void *slot, size_t *size)
+{
+	struct cmd_chain_slot_dpu *dpu_slot = slot;
+	struct amdxdna_cmd_start_npu *sn;
+	u32 cmd_len;
+	u32 arg_sz;
+
+	sn = amdxdna_cmd_get_payload(cmd_bo, &cmd_len);
+	arg_sz = cmd_len - sizeof(*sn);
+	if (cmd_len < sizeof(*sn) || arg_sz > MAX_DPU_ARGS_SIZE)
+		return -EINVAL;
+
+	if (*size < sizeof(*dpu_slot) + arg_sz)
+		return -EINVAL;
+
+	dpu_slot->cu_idx = amdxdna_cmd_get_cu_idx(cmd_bo);
+	if (dpu_slot->cu_idx == INVALID_CU_IDX)
+		return -EINVAL;
+
+	dpu_slot->inst_buf_addr = sn->buffer;
+	dpu_slot->inst_size = sn->buffer_size;
+	dpu_slot->inst_prop_cnt = sn->prop_count;
+	dpu_slot->arg_cnt = arg_sz / sizeof(u32);
+	memcpy(dpu_slot->args, sn->prop_args, arg_sz);
+
+	/* Accurate slot size to hint firmware to do necessary copy */
+	*size = sizeof(*dpu_slot) + arg_sz;
+	return 0;
+}
+
+static int aie2_cmdlist_unsupp(struct amdxdna_gem_obj *cmd_bo, void *slot, size_t *size)
+{
+	return -EOPNOTSUPP;
+}
+
+static u32 aie2_get_chain_msg_op(u32 cmd_op)
+{
+	switch (cmd_op) {
+	case ERT_START_CU:
+		return MSG_OP_CHAIN_EXEC_BUFFER_CF;
+	case ERT_START_NPU:
+		return MSG_OP_CHAIN_EXEC_DPU;
+	default:
+		break;
+	}
+
+	return MSG_OP_MAX_OPCODE;
+}
+
+static struct aie2_exec_msg_ops legacy_exec_message_ops = {
+	.init_cu_req = aie2_init_exec_cu_req,
+	.init_dpu_req = aie2_init_exec_dpu_req,
+	.init_chain_req = aie2_init_exec_chain_req,
+	.fill_cf_slot = aie2_cmdlist_fill_cf,
+	.fill_dpu_slot = aie2_cmdlist_fill_dpu,
+	.fill_preempt_slot = aie2_cmdlist_unsupp,
+	.fill_elf_slot = aie2_cmdlist_unsupp,
+	.get_chain_msg_op = aie2_get_chain_msg_op,
+};
+
+static int
+aie2_cmdlist_fill_npu_cf(struct amdxdna_gem_obj *cmd_bo, void *slot, size_t *size)
+{
+	struct cmd_chain_slot_npu *npu_slot = slot;
+	u32 cmd_len;
+	void *cmd;
+
+	cmd = amdxdna_cmd_get_payload(cmd_bo, &cmd_len);
+	if (*size < sizeof(*npu_slot) + cmd_len)
+		return -EINVAL;
+
+	npu_slot->cu_idx = amdxdna_cmd_get_cu_idx(cmd_bo);
+	if (npu_slot->cu_idx == INVALID_CU_IDX)
+		return -EINVAL;
+
+	memset(npu_slot, 0, sizeof(*npu_slot));
+	npu_slot->type = EXEC_NPU_TYPE_NON_ELF;
+	npu_slot->arg_cnt = cmd_len / sizeof(u32);
+	memcpy(npu_slot->args, cmd, cmd_len);
+
+	*size = sizeof(*npu_slot) + cmd_len;
+	return 0;
+}
+
+static int
+aie2_cmdlist_fill_npu_dpu(struct amdxdna_gem_obj *cmd_bo, void *slot, size_t *size)
+{
+	struct cmd_chain_slot_npu *npu_slot = slot;
+	struct amdxdna_cmd_start_npu *sn;
+	u32 cmd_len;
+	u32 arg_sz;
+
+	sn = amdxdna_cmd_get_payload(cmd_bo, &cmd_len);
+	arg_sz = cmd_len - sizeof(*sn);
+	if (cmd_len < sizeof(*sn) || arg_sz > MAX_NPU_ARGS_SIZE)
+		return -EINVAL;
+
+	if (*size < sizeof(*npu_slot) + arg_sz)
+		return -EINVAL;
+
+	npu_slot->cu_idx = amdxdna_cmd_get_cu_idx(cmd_bo);
+	if (npu_slot->cu_idx == INVALID_CU_IDX)
+		return -EINVAL;
+
+	memset(npu_slot, 0, sizeof(*npu_slot));
+	npu_slot->type = EXEC_NPU_TYPE_PARTIAL_ELF;
+	npu_slot->inst_buf_addr = sn->buffer;
+	npu_slot->inst_size = sn->buffer_size;
+	npu_slot->inst_prop_cnt = sn->prop_count;
+	npu_slot->arg_cnt = arg_sz / sizeof(u32);
+	memcpy(npu_slot->args, sn->prop_args, arg_sz);
+
+	*size = sizeof(*npu_slot) + arg_sz;
+	return 0;
+}
+
+static int
+aie2_cmdlist_fill_npu_preempt(struct amdxdna_gem_obj *cmd_bo, void *slot, size_t *size)
+{
+	struct cmd_chain_slot_npu *npu_slot = slot;
+	struct amdxdna_cmd_preempt_data *pd;
+	u32 cmd_len;
+	u32 arg_sz;
+
+	pd = amdxdna_cmd_get_payload(cmd_bo, &cmd_len);
+	arg_sz = cmd_len - sizeof(*pd);
+	if (cmd_len < sizeof(*pd) || arg_sz > MAX_NPU_ARGS_SIZE)
+		return -EINVAL;
+
+	if (*size < sizeof(*npu_slot) + arg_sz)
+		return -EINVAL;
+
+	npu_slot->cu_idx = amdxdna_cmd_get_cu_idx(cmd_bo);
+	if (npu_slot->cu_idx == INVALID_CU_IDX)
+		return -EINVAL;
+
+	memset(npu_slot, 0, sizeof(*npu_slot));
+	npu_slot->type = EXEC_NPU_TYPE_PREEMPT;
+	npu_slot->inst_buf_addr = pd->inst_buf;
+	npu_slot->save_buf_addr = pd->save_buf;
+	npu_slot->restore_buf_addr = pd->restore_buf;
+	npu_slot->inst_size = pd->inst_size;
+	npu_slot->save_size = pd->save_size;
+	npu_slot->restore_size = pd->restore_size;
+	npu_slot->inst_prop_cnt = pd->inst_prop_cnt;
+	npu_slot->arg_cnt = arg_sz / sizeof(u32);
+	memcpy(npu_slot->args, pd->prop_args, arg_sz);
+
+	*size = sizeof(*npu_slot) + arg_sz;
+	return 0;
+}
+
+static int
+aie2_cmdlist_fill_npu_elf(struct amdxdna_gem_obj *cmd_bo, void *slot, size_t *size)
+{
+	struct cmd_chain_slot_npu *npu_slot = slot;
+	struct amdxdna_cmd_preempt_data *pd;
+	u32 cmd_len;
+	u32 arg_sz;
+
+	pd = amdxdna_cmd_get_payload(cmd_bo, &cmd_len);
+	arg_sz = cmd_len - sizeof(*pd);
+	if (cmd_len < sizeof(*pd) || arg_sz > MAX_NPU_ARGS_SIZE)
+		return -EINVAL;
+
+	if (*size < sizeof(*npu_slot) + arg_sz)
+		return -EINVAL;
+
+	memset(npu_slot, 0, sizeof(*npu_slot));
+	npu_slot->type = EXEC_NPU_TYPE_ELF;
+	npu_slot->inst_buf_addr = pd->inst_buf;
+	npu_slot->save_buf_addr = pd->save_buf;
+	npu_slot->restore_buf_addr = pd->restore_buf;
+	npu_slot->inst_size = pd->inst_size;
+	npu_slot->save_size = pd->save_size;
+	npu_slot->restore_size = pd->restore_size;
+	npu_slot->inst_prop_cnt = pd->inst_prop_cnt;
+	npu_slot->arg_cnt = 1;
+	npu_slot->args[0] = AIE2_EXEC_BUFFER_KERNEL_OP_TXN;
+
+	*size = struct_size(npu_slot, args, npu_slot->arg_cnt);
+	return 0;
+}
+
+static u32 aie2_get_npu_chain_msg_op(u32 cmd_op)
+{
+	return MSG_OP_CHAIN_EXEC_NPU;
+}
+
+static struct aie2_exec_msg_ops npu_exec_message_ops = {
+	.init_cu_req = aie2_init_exec_cu_req,
+	.init_dpu_req = aie2_init_exec_dpu_req,
+	.init_chain_req = aie2_init_npu_chain_req,
+	.fill_cf_slot = aie2_cmdlist_fill_npu_cf,
+	.fill_dpu_slot = aie2_cmdlist_fill_npu_dpu,
+	.fill_preempt_slot = aie2_cmdlist_fill_npu_preempt,
+	.fill_elf_slot = aie2_cmdlist_fill_npu_elf,
+	.get_chain_msg_op = aie2_get_npu_chain_msg_op,
+};
+
+static int aie2_init_exec_req(void *req, struct amdxdna_gem_obj *cmd_abo,
+			      size_t *size, u32 *msg_op)
+{
+	struct amdxdna_dev *xdna = cmd_abo->client->xdna;
+	int ret;
+	u32 op;
+
+
+	op = amdxdna_cmd_get_op(cmd_abo);
+	switch (op) {
+	case ERT_START_CU:
+		ret = EXEC_MSG_OPS(xdna)->init_cu_req(cmd_abo, req, size, msg_op);
+		if (ret) {
+			XDNA_DBG(xdna, "Init CU req failed ret %d", ret);
+			return ret;
+		}
+		break;
+	case ERT_START_NPU:
+		ret = EXEC_MSG_OPS(xdna)->init_dpu_req(cmd_abo, req, size, msg_op);
+		if (ret) {
+			XDNA_DBG(xdna, "Init DPU req failed ret %d", ret);
+			return ret;
+		}
+
+		break;
+	default:
+		XDNA_ERR(xdna, "Unsupported op %d", op);
+		ret = -EOPNOTSUPP;
+		break;
+	}
+
+	return ret;
+}
+
+static int
+aie2_cmdlist_fill_slot(void *slot, struct amdxdna_gem_obj *cmd_abo,
+		       size_t *size, u32 *cmd_op)
+{
+	struct amdxdna_dev *xdna = cmd_abo->client->xdna;
+	int ret;
+	u32 op;
+
+	op = amdxdna_cmd_get_op(cmd_abo);
+	if (*cmd_op == ERT_INVALID_CMD)
+		*cmd_op = op;
+	else if (op != *cmd_op)
+		return -EINVAL;
+
+	switch (op) {
+	case ERT_START_CU:
+		ret = EXEC_MSG_OPS(xdna)->fill_cf_slot(cmd_abo, slot, size);
+		break;
+	case ERT_START_NPU:
+		ret = EXEC_MSG_OPS(xdna)->fill_dpu_slot(cmd_abo, slot, size);
+		break;
+	case ERT_START_NPU_PREEMPT:
+		if (!AIE2_FEATURE_ON(xdna->dev_handle, AIE2_PREEMPT))
+			return -EOPNOTSUPP;
+		ret = EXEC_MSG_OPS(xdna)->fill_preempt_slot(cmd_abo, slot, size);
+		break;
+	case ERT_START_NPU_PREEMPT_ELF:
+		if (!AIE2_FEATURE_ON(xdna->dev_handle, AIE2_PREEMPT))
+			return -EOPNOTSUPP;
+		ret = EXEC_MSG_OPS(xdna)->fill_elf_slot(cmd_abo, slot, size);
+		break;
+	default:
+		XDNA_INFO(xdna, "Unsupported op %d", op);
+		ret = -EOPNOTSUPP;
+		break;
+	}
+
+	return ret;
+}
+
+void aie2_msg_init(struct amdxdna_dev_hdl *ndev)
+{
+	if (AIE2_FEATURE_ON(ndev, AIE2_NPU_COMMAND))
+		ndev->exec_msg_ops = &npu_exec_message_ops;
+	else
+		ndev->exec_msg_ops = &legacy_exec_message_ops;
+}
+
+static inline struct amdxdna_gem_obj *
+aie2_cmdlist_get_cmd_buf(struct amdxdna_sched_job *job)
+{
+	int idx = get_job_idx(job->seq);
+
+	return job->hwctx->priv->cmd_buf[idx];
+}
+
+int aie2_execbuf(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job,
+		 int (*notify_cb)(void *, void __iomem *, size_t))
+{
+	struct mailbox_channel *chann = hwctx->priv->mbox_chann;
+	struct amdxdna_dev *xdna = hwctx->client->xdna;
+	struct amdxdna_gem_obj *cmd_abo = job->cmd_bo;
+	struct xdna_mailbox_msg msg;
+	union exec_req req;
+	int ret;
+
+	if (!chann)
+		return -ENODEV;
+
+	ret = aie2_init_exec_req(&req, cmd_abo, &msg.send_size, &msg.opcode);
+	if (ret)
+		return ret;
+
+	msg.handle = job;
+	msg.notify_cb = notify_cb;
+	msg.send_data = (u8 *)&req;
+	print_hex_dump_debug("cmd: ", DUMP_PREFIX_OFFSET, 16, 4, &req,
+			     0x40, false);
+
+	ret = xdna_mailbox_send_msg(chann, &msg, TX_TIMEOUT);
+	if (ret) {
+		XDNA_ERR(xdna, "Send message failed");
+		return ret;
+	}
+
+	return 0;
+}
+
+int aie2_cmdlist_multi_execbuf(struct amdxdna_hwctx *hwctx,
+			       struct amdxdna_sched_job *job,
+			       int (*notify_cb)(void *, void __iomem *, size_t))
+{
+	struct amdxdna_gem_obj *cmdbuf_abo = aie2_cmdlist_get_cmd_buf(job);
+	struct mailbox_channel *chann = hwctx->priv->mbox_chann;
+	struct amdxdna_client *client = hwctx->client;
+	struct amdxdna_gem_obj *cmd_abo = job->cmd_bo;
+	struct amdxdna_dev *xdna = client->xdna;
+	struct amdxdna_cmd_chain *payload;
+	struct xdna_mailbox_msg msg;
+	union exec_chain_req req;
+	u32 payload_len;
+	u32 offset = 0;
+	size_t size;
+	int ret;
+	u32 op;
+	u32 i;
+
+	op = amdxdna_cmd_get_op(cmd_abo);
+	payload = amdxdna_cmd_get_payload(cmd_abo, &payload_len);
+	if (op != ERT_CMD_CHAIN || !payload ||
+	    payload_len < struct_size(payload, data, payload->command_count))
+		return -EINVAL;
+
+	op = ERT_INVALID_CMD;
+	for (i = 0; i < payload->command_count; i++) {
+		u32 boh = (u32)(payload->data[i]);
+		struct amdxdna_gem_obj *abo;
+
+		abo = amdxdna_gem_get_obj(client, boh, AMDXDNA_BO_CMD);
+		if (!abo) {
+			XDNA_ERR(xdna, "Failed to find cmd BO %d", boh);
+			return -ENOENT;
+		}
+
+		size = cmdbuf_abo->mem.size - offset;
+		ret = aie2_cmdlist_fill_slot(cmdbuf_abo->mem.kva + offset,
+					     abo, &size, &op);
+		amdxdna_gem_put_obj(abo);
+		if (ret)
+			return ret;
+
+		offset += size;
+	}
+	msg.opcode = EXEC_MSG_OPS(xdna)->get_chain_msg_op(op);
+	if (msg.opcode == MSG_OP_MAX_OPCODE)
+		return -EOPNOTSUPP;
+
+	/* The offset is the accumulated total size of the cmd buffer */
+	EXEC_MSG_OPS(xdna)->init_chain_req(&req, cmdbuf_abo->mem.dev_addr,
+					   offset, payload->command_count);
+	drm_clflush_virt_range(cmdbuf_abo->mem.kva, offset);
+
+	msg.handle = job;
+	msg.notify_cb = notify_cb;
+	msg.send_data = (u8 *)&req;
+	msg.send_size = sizeof(req);
+	ret = xdna_mailbox_send_msg(chann, &msg, TX_TIMEOUT);
+	if (ret) {
+		XDNA_ERR(xdna, "Send message failed");
+		return ret;
+	}
+
+	return 0;
+}
+
+int aie2_cmdlist_single_execbuf(struct amdxdna_hwctx *hwctx,
+				struct amdxdna_sched_job *job,
+				int (*notify_cb)(void *, void __iomem *, size_t))
+{
+	struct amdxdna_gem_obj *cmdbuf_abo = aie2_cmdlist_get_cmd_buf(job);
+	struct mailbox_channel *chann = hwctx->priv->mbox_chann;
+	struct amdxdna_dev *xdna = hwctx->client->xdna;
+	struct amdxdna_gem_obj *cmd_abo = job->cmd_bo;
+	struct xdna_mailbox_msg msg;
+	union exec_chain_req req;
+	u32 op = ERT_INVALID_CMD;
+	size_t size;
+	int ret;
+
+	size = cmdbuf_abo->mem.size;
+	ret = aie2_cmdlist_fill_slot(cmdbuf_abo->mem.kva, cmd_abo, &size, &op);
+	if (ret)
+		return ret;
+
+	msg.opcode = EXEC_MSG_OPS(xdna)->get_chain_msg_op(op);
+	if (msg.opcode == MSG_OP_MAX_OPCODE)
+		return -EOPNOTSUPP;
+
+	EXEC_MSG_OPS(xdna)->init_chain_req(&req, cmdbuf_abo->mem.dev_addr,
+					   size, 1);
+	drm_clflush_virt_range(cmdbuf_abo->mem.kva, size);
+
+	msg.handle = job;
+	msg.notify_cb = notify_cb;
+	msg.send_data = (u8 *)&req;
+	msg.send_size = sizeof(req);
+	ret = xdna_mailbox_send_msg(chann, &msg, TX_TIMEOUT);
+	if (ret) {
+		XDNA_ERR(hwctx->client->xdna, "Send message failed");
+		return ret;
+	}
+
+	return 0;
+}
+
+int aie2_sync_bo(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job,
+		 int (*notify_cb)(void *, void __iomem *, size_t))
+{
+	struct mailbox_channel *chann = hwctx->priv->mbox_chann;
+	struct amdxdna_gem_obj *abo = to_xdna_obj(job->bos[0]);
+	struct amdxdna_dev *xdna = hwctx->client->xdna;
+	struct xdna_mailbox_msg msg;
+	struct sync_bo_req req;
+	int ret = 0;
+
+	req.src_addr = 0;
+	req.dst_addr = amdxdna_dev_bo_offset(abo);
+	req.size = abo->mem.size;
+
+	/* Device to Host */
+	req.type = FIELD_PREP(AIE2_MSG_SYNC_BO_SRC_TYPE, SYNC_BO_DEV_MEM) |
+		FIELD_PREP(AIE2_MSG_SYNC_BO_DST_TYPE, SYNC_BO_HOST_MEM);
+
+	XDNA_DBG(xdna, "sync %d bytes src(0x%llx) to dst(0x%llx) completed",
+		 req.size, req.src_addr, req.dst_addr);
+
+	msg.handle = job;
+	msg.notify_cb = notify_cb;
+	msg.send_data = (u8 *)&req;
+	msg.send_size = sizeof(req);
+	msg.opcode = MSG_OP_SYNC_BO;
+
+	ret = xdna_mailbox_send_msg(chann, &msg, TX_TIMEOUT);
+	if (ret) {
+		XDNA_ERR(xdna, "Send message failed");
+		return ret;
+	}
+
+	return 0;
+}
+
+int aie2_config_debug_bo(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job,
+			 int (*notify_cb)(void *, void __iomem *, size_t))
+{
+	struct mailbox_channel *chann = hwctx->priv->mbox_chann;
+	struct amdxdna_gem_obj *abo = to_xdna_obj(job->bos[0]);
+	struct amdxdna_dev *xdna = hwctx->client->xdna;
+	struct config_debug_bo_req req;
+	struct xdna_mailbox_msg msg;
+
+	if (job->drv_cmd->opcode == ATTACH_DEBUG_BO)
+		req.config = DEBUG_BO_REGISTER;
+	else
+		req.config = DEBUG_BO_UNREGISTER;
+
+	req.offset = amdxdna_dev_bo_offset(abo);
+	req.size = abo->mem.size;
+
+	XDNA_DBG(xdna, "offset 0x%llx size 0x%llx config %d",
+		 req.offset, req.size, req.config);
+
+	msg.handle = job;
+	msg.notify_cb = notify_cb;
+	msg.send_data = (u8 *)&req;
+	msg.send_size = sizeof(req);
+	msg.opcode = MSG_OP_CONFIG_DEBUG_BO;
+
+	return xdna_mailbox_send_msg(chann, &msg, TX_TIMEOUT);
+}
diff --git a/drivers/accel/amdxdna/aie2_msg_priv.h b/drivers/accel/amdxdna/aie2_msg_priv.h
new file mode 100644
index 000000000000..1c957a6298d3
--- /dev/null
+++ b/drivers/accel/amdxdna/aie2_msg_priv.h
@@ -0,0 +1,448 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2022-2024, Advanced Micro Devices, Inc.
+ */
+
+#ifndef _AIE2_MSG_PRIV_H_
+#define _AIE2_MSG_PRIV_H_
+
+enum aie2_msg_opcode {
+	MSG_OP_CREATE_CONTEXT              = 0x2,
+	MSG_OP_DESTROY_CONTEXT             = 0x3,
+	MSG_OP_GET_TELEMETRY               = 0x4,
+	MSG_OP_SYNC_BO                     = 0x7,
+	MSG_OP_EXECUTE_BUFFER_CF           = 0xC,
+	MSG_OP_QUERY_COL_STATUS            = 0xD,
+	MSG_OP_QUERY_AIE_TILE_INFO         = 0xE,
+	MSG_OP_QUERY_AIE_VERSION           = 0xF,
+	MSG_OP_EXEC_DPU                    = 0x10,
+	MSG_OP_CONFIG_CU                   = 0x11,
+	MSG_OP_CHAIN_EXEC_BUFFER_CF        = 0x12,
+	MSG_OP_CHAIN_EXEC_DPU              = 0x13,
+	MSG_OP_CONFIG_DEBUG_BO             = 0x14,
+	MSG_OP_CHAIN_EXEC_NPU              = 0x18,
+	MSG_OP_MAX_XRT_OPCODE,
+	MSG_OP_SUSPEND                     = 0x101,
+	MSG_OP_RESUME                      = 0x102,
+	MSG_OP_ASSIGN_MGMT_PASID           = 0x103,
+	MSG_OP_INVOKE_SELF_TEST            = 0x104,
+	MSG_OP_MAP_HOST_BUFFER             = 0x106,
+	MSG_OP_GET_FIRMWARE_VERSION        = 0x108,
+	MSG_OP_SET_RUNTIME_CONFIG          = 0x10A,
+	MSG_OP_GET_RUNTIME_CONFIG          = 0x10B,
+	MSG_OP_REGISTER_ASYNC_EVENT_MSG    = 0x10C,
+	MSG_OP_MAX_DRV_OPCODE,
+	MSG_OP_GET_PROTOCOL_VERSION        = 0x301,
+	MSG_OP_MAX_OPCODE
+};
+
+enum aie2_msg_status {
+	AIE2_STATUS_SUCCESS				= 0x0,
+	/* AIE Error codes */
+	AIE2_STATUS_AIE_SATURATION_ERROR		= 0x1000001,
+	AIE2_STATUS_AIE_FP_ERROR			= 0x1000002,
+	AIE2_STATUS_AIE_STREAM_ERROR			= 0x1000003,
+	AIE2_STATUS_AIE_ACCESS_ERROR			= 0x1000004,
+	AIE2_STATUS_AIE_BUS_ERROR			= 0x1000005,
+	AIE2_STATUS_AIE_INSTRUCTION_ERROR		= 0x1000006,
+	AIE2_STATUS_AIE_ECC_ERROR			= 0x1000007,
+	AIE2_STATUS_AIE_LOCK_ERROR			= 0x1000008,
+	AIE2_STATUS_AIE_DMA_ERROR			= 0x1000009,
+	AIE2_STATUS_AIE_MEM_PARITY_ERROR		= 0x100000a,
+	AIE2_STATUS_AIE_PWR_CFG_ERROR			= 0x100000b,
+	AIE2_STATUS_AIE_BACKTRACK_ERROR			= 0x100000c,
+	AIE2_STATUS_MAX_AIE_STATUS_CODE,
+	/* MGMT ERT Error codes */
+	AIE2_STATUS_MGMT_ERT_SELF_TEST_FAILURE		= 0x2000001,
+	AIE2_STATUS_MGMT_ERT_HASH_MISMATCH,
+	AIE2_STATUS_MGMT_ERT_NOAVAIL,
+	AIE2_STATUS_MGMT_ERT_INVALID_PARAM,
+	AIE2_STATUS_MGMT_ERT_ENTER_SUSPEND_FAILURE,
+	AIE2_STATUS_MGMT_ERT_BUSY,
+	AIE2_STATUS_MGMT_ERT_APPLICATION_ACTIVE,
+	MAX_MGMT_ERT_STATUS_CODE,
+	/* APP ERT Error codes */
+	AIE2_STATUS_APP_ERT_FIRST_ERROR			= 0x3000001,
+	AIE2_STATUS_APP_INVALID_INSTR,
+	AIE2_STATUS_APP_LOAD_PDI_FAIL,
+	MAX_APP_ERT_STATUS_CODE,
+	/* NPU RTOS Error Codes */
+	AIE2_STATUS_INVALID_INPUT_BUFFER		= 0x4000001,
+	AIE2_STATUS_INVALID_COMMAND,
+	AIE2_STATUS_INVALID_PARAM,
+	AIE2_STATUS_INVALID_OPERATION			= 0x4000006,
+	AIE2_STATUS_ASYNC_EVENT_MSGS_FULL,
+	AIE2_STATUS_MAX_RTOS_STATUS_CODE,
+	MAX_AIE2_STATUS_CODE
+};
+
+struct assign_mgmt_pasid_req {
+	__u16	pasid;
+	__u16	reserved;
+} __packed;
+
+struct assign_mgmt_pasid_resp {
+	enum aie2_msg_status	status;
+} __packed;
+
+struct map_host_buffer_req {
+	__u32		context_id;
+	__u64		buf_addr;
+	__u64		buf_size;
+} __packed;
+
+struct map_host_buffer_resp {
+	enum aie2_msg_status	status;
+} __packed;
+
+#define MAX_CQ_PAIRS		2
+struct cq_info {
+	__u32 head_addr;
+	__u32 tail_addr;
+	__u32 buf_addr;
+	__u32 buf_size;
+};
+
+struct cq_pair {
+	struct cq_info x2i_q;
+	struct cq_info i2x_q;
+};
+
+struct create_ctx_req {
+	__u32	aie_type;
+	__u8	start_col;
+	__u8	num_col;
+	__u16	reserved;
+	__u8	num_cq_pairs_requested;
+	__u8	reserved1;
+	__u16	pasid;
+	__u32	pad[2];
+	__u32	sec_comm_target_type;
+	__u32	context_priority;
+} __packed;
+
+struct create_ctx_resp {
+	enum aie2_msg_status	status;
+	__u32			context_id;
+	__u16			msix_id;
+	__u8			num_cq_pairs_allocated;
+	__u8			reserved;
+	struct cq_pair		cq_pair[MAX_CQ_PAIRS];
+} __packed;
+
+struct destroy_ctx_req {
+	__u32	context_id;
+} __packed;
+
+struct destroy_ctx_resp {
+	enum aie2_msg_status	status;
+} __packed;
+
+enum telemetry_type {
+	TELEMETRY_TYPE_DISABLED,
+	TELEMETRY_TYPE_HEALTH,
+	TELEMETRY_TYPE_ERROR_INFO,
+	TELEMETRY_TYPE_PROFILING,
+	TELEMETRY_TYPE_DEBUG,
+	MAX_TELEMETRY_TYPE
+};
+
+struct get_telemetry_req {
+	enum telemetry_type	type;
+	__u64	buf_addr;
+	__u32	buf_size;
+} __packed;
+
+struct get_telemetry_resp {
+	__u32	major;
+	__u32	minor;
+	__u32	size;
+	enum aie2_msg_status	status;
+} __packed;
+
+struct execute_buffer_req {
+	__u32	cu_idx;
+	__u32	payload[19];
+} __packed;
+
+struct exec_dpu_req {
+	__u64	inst_buf_addr;
+	__u32	inst_size;
+	__u32	inst_prop_cnt;
+	__u32	cu_idx;
+	__u32	payload[35];
+} __packed;
+
+enum exec_npu_type {
+	EXEC_NPU_TYPE_NON_ELF		= 0x1,
+	EXEC_NPU_TYPE_PARTIAL_ELF	= 0x2,
+	EXEC_NPU_TYPE_PREEMPT		= 0x3,
+	EXEC_NPU_TYPE_ELF		= 0x4,
+};
+
+union exec_req {
+	struct execute_buffer_req ebuf;
+	struct exec_dpu_req dpu_req;
+};
+
+struct execute_buffer_resp {
+	enum aie2_msg_status	status;
+} __packed;
+
+struct aie_tile_info {
+	__u32		size;
+	__u16		major;
+	__u16		minor;
+	__u16		cols;
+	__u16		rows;
+	__u16		core_rows;
+	__u16		mem_rows;
+	__u16		shim_rows;
+	__u16		core_row_start;
+	__u16		mem_row_start;
+	__u16		shim_row_start;
+	__u16		core_dma_channels;
+	__u16		mem_dma_channels;
+	__u16		shim_dma_channels;
+	__u16		core_locks;
+	__u16		mem_locks;
+	__u16		shim_locks;
+	__u16		core_events;
+	__u16		mem_events;
+	__u16		shim_events;
+	__u16		reserved;
+};
+
+struct aie_tile_info_req {
+	__u32	reserved;
+} __packed;
+
+struct aie_tile_info_resp {
+	enum aie2_msg_status	status;
+	struct aie_tile_info	info;
+} __packed;
+
+struct aie_version_info_req {
+	__u32		reserved;
+} __packed;
+
+struct aie_version_info_resp {
+	enum aie2_msg_status	status;
+	__u16			major;
+	__u16			minor;
+} __packed;
+
+struct aie_column_info_req {
+	__u64 dump_buff_addr;
+	__u32 dump_buff_size;
+	__u32 num_cols;
+	__u32 aie_bitmap;
+} __packed;
+
+struct aie_column_info_resp {
+	enum aie2_msg_status	status;
+	__u32 size;
+} __packed;
+
+struct suspend_req {
+	__u32		place_holder;
+} __packed;
+
+struct suspend_resp {
+	enum aie2_msg_status	status;
+} __packed;
+
+struct resume_req {
+	__u32		place_holder;
+} __packed;
+
+struct resume_resp {
+	enum aie2_msg_status	status;
+} __packed;
+
+struct check_header_hash_req {
+	__u64		hash_high;
+	__u64		hash_low;
+} __packed;
+
+struct check_header_hash_resp {
+	enum aie2_msg_status	status;
+} __packed;
+
+struct query_error_req {
+	__u64		buf_addr;
+	__u32		buf_size;
+	__u32		next_row;
+	__u32		next_column;
+	__u32		next_module;
+} __packed;
+
+struct query_error_resp {
+	enum aie2_msg_status	status;
+	__u32			num_err;
+	__u32			has_next_err;
+	__u32			next_row;
+	__u32			next_column;
+	__u32			next_module;
+} __packed;
+
+struct protocol_version_req {
+	__u32		reserved;
+} __packed;
+
+struct protocol_version_resp {
+	enum aie2_msg_status	status;
+	__u32			major;
+	__u32			minor;
+} __packed;
+
+struct firmware_version_req {
+	__u32		reserved;
+} __packed;
+
+struct firmware_version_resp {
+	enum aie2_msg_status	status;
+	__u32			major;
+	__u32			minor;
+	__u32			sub;
+	__u32			build;
+} __packed;
+
+#define MAX_NUM_CUS			32
+#define AIE2_MSG_CFG_CU_PDI_ADDR	GENMASK(16, 0)
+#define AIE2_MSG_CFG_CU_FUNC		GENMASK(24, 17)
+struct config_cu_req {
+	__u32	num_cus;
+	__u32	cfgs[MAX_NUM_CUS];
+} __packed;
+
+struct config_cu_resp {
+	enum aie2_msg_status	status;
+} __packed;
+
+struct set_runtime_cfg_req {
+	__u32	type;
+	__u64	value;
+} __packed;
+
+struct set_runtime_cfg_resp {
+	enum aie2_msg_status	status;
+} __packed;
+
+struct get_runtime_cfg_req {
+	__u32	type;
+} __packed;
+
+struct get_runtime_cfg_resp {
+	enum aie2_msg_status	status;
+	__u64			value;
+} __packed;
+
+enum async_event_type {
+	ASYNC_EVENT_TYPE_AIE_ERROR,
+	ASYNC_EVENT_TYPE_EXCEPTION,
+	MAX_ASYNC_EVENT_TYPE
+};
+
+#define ASYNC_BUF_SIZE SZ_8K
+struct async_event_msg_req {
+	__u64 buf_addr;
+	__u32 buf_size;
+} __packed;
+
+struct async_event_msg_resp {
+	enum aie2_msg_status	status;
+	enum async_event_type	type;
+} __packed;
+
+#define MAX_CHAIN_CMDBUF_SIZE SZ_4K
+
+struct cmd_chain_slot_execbuf_cf {
+	__u32 cu_idx;
+	__u32 arg_cnt;
+	__u32 args[] __counted_by(arg_cnt);
+};
+
+struct cmd_chain_slot_dpu {
+	__u64 inst_buf_addr;
+	__u32 inst_size;
+	__u32 inst_prop_cnt;
+	__u32 cu_idx;
+	__u32 arg_cnt;
+#define MAX_DPU_ARGS_SIZE (34 * sizeof(__u32))
+	__u32 args[] __counted_by(arg_cnt);
+};
+
+#define MAX_NPU_ARGS_SIZE (26 * sizeof(__u32))
+#define AIE2_EXEC_BUFFER_KERNEL_OP_TXN	3
+struct cmd_chain_slot_npu {
+	enum exec_npu_type type;
+	u64 inst_buf_addr;
+	u64 save_buf_addr;
+	u64 restore_buf_addr;
+	u32 inst_size;
+	u32 save_size;
+	u32 restore_size;
+	u32 inst_prop_cnt;
+	u32 cu_idx;
+	u32 arg_cnt;
+	u32 args[] __counted_by(arg_cnt);
+} __packed;
+
+struct cmd_chain_req {
+	__u64 buf_addr;
+	__u32 buf_size;
+	__u32 count;
+} __packed;
+
+struct cmd_chain_npu_req {
+	u32 flags;
+	u32 reserved;
+	u64 buf_addr;
+	u32 buf_size;
+	u32 count;
+} __packed;
+
+union exec_chain_req {
+	struct cmd_chain_npu_req npu_req;
+	struct cmd_chain_req req;
+};
+
+struct cmd_chain_resp {
+	enum aie2_msg_status	status;
+	__u32			fail_cmd_idx;
+	enum aie2_msg_status	fail_cmd_status;
+} __packed;
+
+#define AIE2_MSG_SYNC_BO_SRC_TYPE	GENMASK(3, 0)
+#define AIE2_MSG_SYNC_BO_DST_TYPE	GENMASK(7, 4)
+struct sync_bo_req {
+	__u64 src_addr;
+	__u64 dst_addr;
+	__u32 size;
+#define SYNC_BO_DEV_MEM  0
+#define SYNC_BO_HOST_MEM 2
+	__u32 type;
+} __packed;
+
+struct sync_bo_resp {
+	enum aie2_msg_status	status;
+} __packed;
+
+#define DEBUG_BO_UNREGISTER 0
+#define DEBUG_BO_REGISTER   1
+struct config_debug_bo_req {
+	__u64	offset;
+	__u64	size;
+	/*
+	 * config operations.
+	 *   DEBUG_BO_REGISTER: Register debug buffer
+	 *   DEBUG_BO_UNREGISTER: Unregister debug buffer
+	 */
+	__u32	config;
+} __packed;
+
+struct config_debug_bo_resp {
+	enum aie2_msg_status	status;
+} __packed;
+#endif /* _AIE2_MSG_PRIV_H_ */
diff --git a/drivers/accel/amdxdna/aie2_pci.c b/drivers/accel/amdxdna/aie2_pci.c
new file mode 100644
index 000000000000..ceef1c502e9e
--- /dev/null
+++ b/drivers/accel/amdxdna/aie2_pci.c
@@ -0,0 +1,1187 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023-2024, Advanced Micro Devices, Inc.
+ */
+
+#include <drm/amdxdna_accel.h>
+#include <drm/drm_device.h>
+#include <drm/drm_drv.h>
+#include <drm/drm_gem_shmem_helper.h>
+#include <drm/drm_managed.h>
+#include <drm/drm_print.h>
+#include <drm/gpu_scheduler.h>
+#include <linux/cleanup.h>
+#include <linux/errno.h>
+#include <linux/firmware.h>
+#include <linux/iommu.h>
+#include <linux/iopoll.h>
+#include <linux/pci.h>
+#include <linux/xarray.h>
+
+#include "aie2_msg_priv.h"
+#include "aie2_pci.h"
+#include "aie2_solver.h"
+#include "amdxdna_ctx.h"
+#include "amdxdna_gem.h"
+#include "amdxdna_mailbox.h"
+#include "amdxdna_pci_drv.h"
+#include "amdxdna_pm.h"
+
+static int aie2_max_col = XRS_MAX_COL;
+module_param(aie2_max_col, uint, 0600);
+MODULE_PARM_DESC(aie2_max_col, "Maximum column could be used");
+
+/*
+ * The management mailbox channel is allocated by firmware.
+ * The related register and ring buffer information is on SRAM BAR.
+ * This struct is the register layout.
+ */
+#define MGMT_MBOX_MAGIC 0x55504e5f /* _NPU */
+struct mgmt_mbox_chann_info {
+	__u32	x2i_tail;
+	__u32	x2i_head;
+	__u32	x2i_buf;
+	__u32	x2i_buf_sz;
+	__u32	i2x_tail;
+	__u32	i2x_head;
+	__u32	i2x_buf;
+	__u32	i2x_buf_sz;
+	__u32	magic;
+	__u32	msi_id;
+	__u32	prot_major;
+	__u32	prot_minor;
+	__u32	rsvd[4];
+};
+
+static int aie2_check_protocol(struct amdxdna_dev_hdl *ndev, u32 fw_major, u32 fw_minor)
+{
+	const struct aie2_fw_feature_tbl *feature;
+	struct amdxdna_dev *xdna = ndev->xdna;
+
+	/*
+	 * The driver supported mailbox behavior is defined by
+	 * ndev->priv->protocol_major and protocol_minor.
+	 *
+	 * When protocol_major and fw_major are different, it means driver
+	 * and firmware are incompatible.
+	 */
+	if (ndev->priv->protocol_major != fw_major) {
+		XDNA_ERR(xdna, "Incompatible firmware protocol major %d minor %d",
+			 fw_major, fw_minor);
+		return -EINVAL;
+	}
+
+	/*
+	 * When protocol_minor is greater then fw_minor, that means driver
+	 * relies on operation the installed firmware does not support.
+	 */
+	if (ndev->priv->protocol_minor > fw_minor) {
+		XDNA_ERR(xdna, "Firmware minor version smaller than supported");
+		return -EINVAL;
+	}
+
+	for (feature = ndev->priv->fw_feature_tbl; feature && feature->min_minor;
+	     feature++) {
+		if (fw_minor < feature->min_minor)
+			continue;
+		if (feature->max_minor > 0 && fw_minor > feature->max_minor)
+			continue;
+
+		set_bit(feature->feature, &ndev->feature_mask);
+	}
+
+	return 0;
+}
+
+static void aie2_dump_chann_info_debug(struct amdxdna_dev_hdl *ndev)
+{
+	struct amdxdna_dev *xdna = ndev->xdna;
+
+	XDNA_DBG(xdna, "i2x tail    0x%x", ndev->mgmt_i2x.mb_tail_ptr_reg);
+	XDNA_DBG(xdna, "i2x head    0x%x", ndev->mgmt_i2x.mb_head_ptr_reg);
+	XDNA_DBG(xdna, "i2x ringbuf 0x%x", ndev->mgmt_i2x.rb_start_addr);
+	XDNA_DBG(xdna, "i2x rsize   0x%x", ndev->mgmt_i2x.rb_size);
+	XDNA_DBG(xdna, "x2i tail    0x%x", ndev->mgmt_x2i.mb_tail_ptr_reg);
+	XDNA_DBG(xdna, "x2i head    0x%x", ndev->mgmt_x2i.mb_head_ptr_reg);
+	XDNA_DBG(xdna, "x2i ringbuf 0x%x", ndev->mgmt_x2i.rb_start_addr);
+	XDNA_DBG(xdna, "x2i rsize   0x%x", ndev->mgmt_x2i.rb_size);
+	XDNA_DBG(xdna, "x2i chann index 0x%x", ndev->mgmt_chan_idx);
+	XDNA_DBG(xdna, "mailbox protocol major 0x%x", ndev->mgmt_prot_major);
+	XDNA_DBG(xdna, "mailbox protocol minor 0x%x", ndev->mgmt_prot_minor);
+}
+
+static int aie2_get_mgmt_chann_info(struct amdxdna_dev_hdl *ndev)
+{
+	struct mgmt_mbox_chann_info info_regs;
+	struct xdna_mailbox_chann_res *i2x;
+	struct xdna_mailbox_chann_res *x2i;
+	u32 addr, off;
+	u32 *reg;
+	int ret;
+	int i;
+
+	/*
+	 * Once firmware is alive, it will write management channel
+	 * information in SRAM BAR and write the address of that information
+	 * at FW_ALIVE_OFF offset in SRMA BAR.
+	 *
+	 * Read a non-zero value from FW_ALIVE_OFF implies that firmware
+	 * is alive.
+	 */
+	ret = readx_poll_timeout(readl, SRAM_GET_ADDR(ndev, FW_ALIVE_OFF),
+				 addr, addr, AIE2_INTERVAL, AIE2_TIMEOUT);
+	if (ret || !addr)
+		return -ETIME;
+
+	off = AIE2_SRAM_OFF(ndev, addr);
+	reg = (u32 *)&info_regs;
+	for (i = 0; i < sizeof(info_regs) / sizeof(u32); i++)
+		reg[i] = readl(ndev->sram_base + off + i * sizeof(u32));
+
+	if (info_regs.magic != MGMT_MBOX_MAGIC) {
+		XDNA_ERR(ndev->xdna, "Invalid mbox magic 0x%x", info_regs.magic);
+		ret = -EINVAL;
+		goto done;
+	}
+
+	i2x = &ndev->mgmt_i2x;
+	x2i = &ndev->mgmt_x2i;
+
+	i2x->mb_head_ptr_reg = AIE2_MBOX_OFF(ndev, info_regs.i2x_head);
+	i2x->mb_tail_ptr_reg = AIE2_MBOX_OFF(ndev, info_regs.i2x_tail);
+	i2x->rb_start_addr   = AIE2_SRAM_OFF(ndev, info_regs.i2x_buf);
+	i2x->rb_size         = info_regs.i2x_buf_sz;
+
+	x2i->mb_head_ptr_reg = AIE2_MBOX_OFF(ndev, info_regs.x2i_head);
+	x2i->mb_tail_ptr_reg = AIE2_MBOX_OFF(ndev, info_regs.x2i_tail);
+	x2i->rb_start_addr   = AIE2_SRAM_OFF(ndev, info_regs.x2i_buf);
+	x2i->rb_size         = info_regs.x2i_buf_sz;
+
+	ndev->mgmt_chan_idx  = info_regs.msi_id;
+	ndev->mgmt_prot_major = info_regs.prot_major;
+	ndev->mgmt_prot_minor = info_regs.prot_minor;
+
+	ret = aie2_check_protocol(ndev, ndev->mgmt_prot_major, ndev->mgmt_prot_minor);
+
+done:
+	aie2_dump_chann_info_debug(ndev);
+
+	/* Must clear address at FW_ALIVE_OFF */
+	writel(0, SRAM_GET_ADDR(ndev, FW_ALIVE_OFF));
+
+	return ret;
+}
+
+int aie2_runtime_cfg(struct amdxdna_dev_hdl *ndev,
+		     enum rt_config_category category, u32 *val)
+{
+	const struct rt_config *cfg;
+	u32 value;
+	int ret;
+
+	for (cfg = ndev->priv->rt_config; cfg->type; cfg++) {
+		if (cfg->category != category)
+			continue;
+
+		if (cfg->feature_mask &&
+		    bitmap_subset(&cfg->feature_mask, &ndev->feature_mask, AIE2_FEATURE_MAX))
+			continue;
+
+		value = val ? *val : cfg->value;
+		ret = aie2_set_runtime_cfg(ndev, cfg->type, value);
+		if (ret) {
+			XDNA_ERR(ndev->xdna, "Set type %d value %d failed",
+				 cfg->type, value);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static int aie2_xdna_reset(struct amdxdna_dev_hdl *ndev)
+{
+	int ret;
+
+	ret = aie2_suspend_fw(ndev);
+	if (ret) {
+		XDNA_ERR(ndev->xdna, "Suspend firmware failed");
+		return ret;
+	}
+
+	ret = aie2_resume_fw(ndev);
+	if (ret) {
+		XDNA_ERR(ndev->xdna, "Resume firmware failed");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int aie2_mgmt_fw_init(struct amdxdna_dev_hdl *ndev)
+{
+	int ret;
+
+	ret = aie2_runtime_cfg(ndev, AIE2_RT_CFG_INIT, NULL);
+	if (ret) {
+		XDNA_ERR(ndev->xdna, "Runtime config failed");
+		return ret;
+	}
+
+	ret = aie2_assign_mgmt_pasid(ndev, 0);
+	if (ret) {
+		XDNA_ERR(ndev->xdna, "Can not assign PASID");
+		return ret;
+	}
+
+	ret = aie2_xdna_reset(ndev);
+	if (ret) {
+		XDNA_ERR(ndev->xdna, "Reset firmware failed");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int aie2_mgmt_fw_query(struct amdxdna_dev_hdl *ndev)
+{
+	int ret;
+
+	ret = aie2_query_firmware_version(ndev, &ndev->xdna->fw_ver);
+	if (ret) {
+		XDNA_ERR(ndev->xdna, "query firmware version failed");
+		return ret;
+	}
+
+	ret = aie2_query_aie_version(ndev, &ndev->version);
+	if (ret) {
+		XDNA_ERR(ndev->xdna, "Query AIE version failed");
+		return ret;
+	}
+
+	ret = aie2_query_aie_metadata(ndev, &ndev->metadata);
+	if (ret) {
+		XDNA_ERR(ndev->xdna, "Query AIE metadata failed");
+		return ret;
+	}
+
+	ndev->total_col = min(aie2_max_col, ndev->metadata.cols);
+
+	return 0;
+}
+
+static void aie2_mgmt_fw_fini(struct amdxdna_dev_hdl *ndev)
+{
+	if (aie2_suspend_fw(ndev))
+		XDNA_ERR(ndev->xdna, "Suspend_fw failed");
+	XDNA_DBG(ndev->xdna, "Firmware suspended");
+}
+
+static int aie2_xrs_load(void *cb_arg, struct xrs_action_load *action)
+{
+	struct amdxdna_hwctx *hwctx = cb_arg;
+	struct amdxdna_dev *xdna;
+	int ret;
+
+	xdna = hwctx->client->xdna;
+
+	hwctx->start_col = action->part.start_col;
+	hwctx->num_col = action->part.ncols;
+	ret = aie2_create_context(xdna->dev_handle, hwctx);
+	if (ret)
+		XDNA_ERR(xdna, "create context failed, ret %d", ret);
+
+	return ret;
+}
+
+static int aie2_xrs_unload(void *cb_arg)
+{
+	struct amdxdna_hwctx *hwctx = cb_arg;
+	struct amdxdna_dev *xdna;
+	int ret;
+
+	xdna = hwctx->client->xdna;
+
+	ret = aie2_destroy_context(xdna->dev_handle, hwctx);
+	if (ret)
+		XDNA_ERR(xdna, "destroy context failed, ret %d", ret);
+
+	return ret;
+}
+
+static int aie2_xrs_set_dft_dpm_level(struct drm_device *ddev, u32 dpm_level)
+{
+	struct amdxdna_dev *xdna = to_xdna_dev(ddev);
+	struct amdxdna_dev_hdl *ndev;
+
+	drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock));
+
+	ndev = xdna->dev_handle;
+	ndev->dft_dpm_level = dpm_level;
+	if (ndev->pw_mode != POWER_MODE_DEFAULT || ndev->dpm_level == dpm_level)
+		return 0;
+
+	return ndev->priv->hw_ops.set_dpm(ndev, dpm_level);
+}
+
+static struct xrs_action_ops aie2_xrs_actions = {
+	.load = aie2_xrs_load,
+	.unload = aie2_xrs_unload,
+	.set_dft_dpm_level = aie2_xrs_set_dft_dpm_level,
+};
+
+static void aie2_hw_stop(struct amdxdna_dev *xdna)
+{
+	struct pci_dev *pdev = to_pci_dev(xdna->ddev.dev);
+	struct amdxdna_dev_hdl *ndev = xdna->dev_handle;
+
+	if (ndev->dev_status <= AIE2_DEV_INIT) {
+		XDNA_ERR(xdna, "device is already stopped");
+		return;
+	}
+
+	aie2_mgmt_fw_fini(ndev);
+	xdna_mailbox_stop_channel(ndev->mgmt_chann);
+	xdna_mailbox_destroy_channel(ndev->mgmt_chann);
+	ndev->mgmt_chann = NULL;
+	drmm_kfree(&xdna->ddev, ndev->mbox);
+	ndev->mbox = NULL;
+	aie2_psp_stop(ndev->psp_hdl);
+	aie2_smu_fini(ndev);
+	aie2_error_async_events_free(ndev);
+	pci_disable_device(pdev);
+
+	ndev->dev_status = AIE2_DEV_INIT;
+}
+
+static int aie2_hw_start(struct amdxdna_dev *xdna)
+{
+	struct pci_dev *pdev = to_pci_dev(xdna->ddev.dev);
+	struct amdxdna_dev_hdl *ndev = xdna->dev_handle;
+	struct xdna_mailbox_res mbox_res;
+	u32 xdna_mailbox_intr_reg;
+	int mgmt_mb_irq, ret;
+
+	if (ndev->dev_status >= AIE2_DEV_START) {
+		XDNA_INFO(xdna, "device is already started");
+		return 0;
+	}
+
+	ret = pci_enable_device(pdev);
+	if (ret) {
+		XDNA_ERR(xdna, "failed to enable device, ret %d", ret);
+		return ret;
+	}
+	pci_set_master(pdev);
+
+	ret = aie2_smu_init(ndev);
+	if (ret) {
+		XDNA_ERR(xdna, "failed to init smu, ret %d", ret);
+		goto disable_dev;
+	}
+
+	ret = aie2_psp_start(ndev->psp_hdl);
+	if (ret) {
+		XDNA_ERR(xdna, "failed to start psp, ret %d", ret);
+		goto fini_smu;
+	}
+
+	ret = aie2_get_mgmt_chann_info(ndev);
+	if (ret) {
+		XDNA_ERR(xdna, "firmware is not alive");
+		goto stop_psp;
+	}
+
+	mbox_res.ringbuf_base = ndev->sram_base;
+	mbox_res.ringbuf_size = pci_resource_len(pdev, xdna->dev_info->sram_bar);
+	mbox_res.mbox_base = ndev->mbox_base;
+	mbox_res.mbox_size = MBOX_SIZE(ndev);
+	mbox_res.name = "xdna_mailbox";
+	ndev->mbox = xdnam_mailbox_create(&xdna->ddev, &mbox_res);
+	if (!ndev->mbox) {
+		XDNA_ERR(xdna, "failed to create mailbox device");
+		ret = -ENODEV;
+		goto stop_psp;
+	}
+
+	mgmt_mb_irq = pci_irq_vector(pdev, ndev->mgmt_chan_idx);
+	if (mgmt_mb_irq < 0) {
+		ret = mgmt_mb_irq;
+		XDNA_ERR(xdna, "failed to alloc irq vector, ret %d", ret);
+		goto stop_psp;
+	}
+
+	xdna_mailbox_intr_reg = ndev->mgmt_i2x.mb_head_ptr_reg + 4;
+	ndev->mgmt_chann = xdna_mailbox_create_channel(ndev->mbox,
+						       &ndev->mgmt_x2i,
+						       &ndev->mgmt_i2x,
+						       xdna_mailbox_intr_reg,
+						       mgmt_mb_irq);
+	if (!ndev->mgmt_chann) {
+		XDNA_ERR(xdna, "failed to create management mailbox channel");
+		ret = -EINVAL;
+		goto stop_psp;
+	}
+
+	ret = aie2_pm_init(ndev);
+	if (ret) {
+		XDNA_ERR(xdna, "failed to init pm, ret %d", ret);
+		goto destroy_mgmt_chann;
+	}
+
+	ret = aie2_mgmt_fw_init(ndev);
+	if (ret) {
+		XDNA_ERR(xdna, "initial mgmt firmware failed, ret %d", ret);
+		goto destroy_mgmt_chann;
+	}
+
+	ret = aie2_mgmt_fw_query(ndev);
+	if (ret) {
+		XDNA_ERR(xdna, "failed to query fw, ret %d", ret);
+		goto destroy_mgmt_chann;
+	}
+
+	ret = aie2_error_async_events_alloc(ndev);
+	if (ret) {
+		XDNA_ERR(xdna, "Allocate async events failed, ret %d", ret);
+		goto destroy_mgmt_chann;
+	}
+
+	ndev->dev_status = AIE2_DEV_START;
+
+	return 0;
+
+destroy_mgmt_chann:
+	xdna_mailbox_stop_channel(ndev->mgmt_chann);
+	xdna_mailbox_destroy_channel(ndev->mgmt_chann);
+stop_psp:
+	aie2_psp_stop(ndev->psp_hdl);
+fini_smu:
+	aie2_smu_fini(ndev);
+disable_dev:
+	pci_disable_device(pdev);
+
+	return ret;
+}
+
+static int aie2_hw_suspend(struct amdxdna_dev *xdna)
+{
+	struct amdxdna_client *client;
+
+	guard(mutex)(&xdna->dev_lock);
+	list_for_each_entry(client, &xdna->client_list, node)
+		aie2_hwctx_suspend(client);
+
+	aie2_hw_stop(xdna);
+
+	return 0;
+}
+
+static int aie2_hw_resume(struct amdxdna_dev *xdna)
+{
+	struct amdxdna_client *client;
+	int ret;
+
+	ret = aie2_hw_start(xdna);
+	if (ret) {
+		XDNA_ERR(xdna, "Start hardware failed, %d", ret);
+		return ret;
+	}
+
+	list_for_each_entry(client, &xdna->client_list, node) {
+		ret = aie2_hwctx_resume(client);
+		if (ret)
+			break;
+	}
+
+	return ret;
+}
+
+static int aie2_init(struct amdxdna_dev *xdna)
+{
+	struct pci_dev *pdev = to_pci_dev(xdna->ddev.dev);
+	void __iomem *tbl[PCI_NUM_RESOURCES] = {0};
+	struct init_config xrs_cfg = { 0 };
+	struct amdxdna_dev_hdl *ndev;
+	struct psp_config psp_conf;
+	const struct firmware *fw;
+	unsigned long bars = 0;
+	int i, nvec, ret;
+
+	ndev = drmm_kzalloc(&xdna->ddev, sizeof(*ndev), GFP_KERNEL);
+	if (!ndev)
+		return -ENOMEM;
+
+	ndev->priv = xdna->dev_info->dev_priv;
+	ndev->xdna = xdna;
+
+	ret = request_firmware(&fw, ndev->priv->fw_path, &pdev->dev);
+	if (ret) {
+		XDNA_ERR(xdna, "failed to request_firmware %s, ret %d",
+			 ndev->priv->fw_path, ret);
+		return ret;
+	}
+
+	ret = pcim_enable_device(pdev);
+	if (ret) {
+		XDNA_ERR(xdna, "pcim enable device failed, ret %d", ret);
+		goto release_fw;
+	}
+
+	for (i = 0; i < PSP_MAX_REGS; i++)
+		set_bit(PSP_REG_BAR(ndev, i), &bars);
+
+	set_bit(xdna->dev_info->sram_bar, &bars);
+	set_bit(xdna->dev_info->smu_bar, &bars);
+	set_bit(xdna->dev_info->mbox_bar, &bars);
+
+	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
+		if (!test_bit(i, &bars))
+			continue;
+		tbl[i] = pcim_iomap(pdev, i, 0);
+		if (!tbl[i]) {
+			XDNA_ERR(xdna, "map bar %d failed", i);
+			ret = -ENOMEM;
+			goto release_fw;
+		}
+	}
+
+	ndev->sram_base = tbl[xdna->dev_info->sram_bar];
+	ndev->smu_base = tbl[xdna->dev_info->smu_bar];
+	ndev->mbox_base = tbl[xdna->dev_info->mbox_bar];
+
+	ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
+	if (ret) {
+		XDNA_ERR(xdna, "Failed to set DMA mask: %d", ret);
+		goto release_fw;
+	}
+
+	nvec = pci_msix_vec_count(pdev);
+	if (nvec <= 0) {
+		XDNA_ERR(xdna, "does not get number of interrupt vector");
+		ret = -EINVAL;
+		goto release_fw;
+	}
+
+	ret = pci_alloc_irq_vectors(pdev, nvec, nvec, PCI_IRQ_MSIX);
+	if (ret < 0) {
+		XDNA_ERR(xdna, "failed to alloc irq vectors, ret %d", ret);
+		goto release_fw;
+	}
+
+	psp_conf.fw_size = fw->size;
+	psp_conf.fw_buf = fw->data;
+	for (i = 0; i < PSP_MAX_REGS; i++)
+		psp_conf.psp_regs[i] = tbl[PSP_REG_BAR(ndev, i)] + PSP_REG_OFF(ndev, i);
+	ndev->psp_hdl = aie2m_psp_create(&xdna->ddev, &psp_conf);
+	if (!ndev->psp_hdl) {
+		XDNA_ERR(xdna, "failed to create psp");
+		ret = -ENOMEM;
+		goto release_fw;
+	}
+	xdna->dev_handle = ndev;
+
+	ret = aie2_hw_start(xdna);
+	if (ret) {
+		XDNA_ERR(xdna, "start npu failed, ret %d", ret);
+		goto release_fw;
+	}
+
+	xrs_cfg.clk_list.num_levels = ndev->max_dpm_level + 1;
+	for (i = 0; i < xrs_cfg.clk_list.num_levels; i++)
+		xrs_cfg.clk_list.cu_clk_list[i] = ndev->priv->dpm_clk_tbl[i].hclk;
+	xrs_cfg.sys_eff_factor = 1;
+	xrs_cfg.ddev = &xdna->ddev;
+	xrs_cfg.actions = &aie2_xrs_actions;
+	xrs_cfg.total_col = ndev->total_col;
+
+	xdna->xrs_hdl = xrsm_init(&xrs_cfg);
+	if (!xdna->xrs_hdl) {
+		XDNA_ERR(xdna, "Initialize resolver failed");
+		ret = -EINVAL;
+		goto stop_hw;
+	}
+
+	release_firmware(fw);
+	aie2_msg_init(ndev);
+	amdxdna_pm_init(xdna);
+	return 0;
+
+stop_hw:
+	aie2_hw_stop(xdna);
+release_fw:
+	release_firmware(fw);
+
+	return ret;
+}
+
+static void aie2_fini(struct amdxdna_dev *xdna)
+{
+	amdxdna_pm_fini(xdna);
+	aie2_hw_stop(xdna);
+}
+
+static int aie2_get_aie_status(struct amdxdna_client *client,
+			       struct amdxdna_drm_get_info *args)
+{
+	struct amdxdna_drm_query_aie_status status;
+	struct amdxdna_dev *xdna = client->xdna;
+	struct amdxdna_dev_hdl *ndev;
+	int ret;
+
+	ndev = xdna->dev_handle;
+	if (copy_from_user(&status, u64_to_user_ptr(args->buffer), sizeof(status))) {
+		XDNA_ERR(xdna, "Failed to copy AIE request into kernel");
+		return -EFAULT;
+	}
+
+	if (ndev->metadata.cols * ndev->metadata.size < status.buffer_size) {
+		XDNA_ERR(xdna, "Invalid buffer size. Given Size: %u. Need Size: %u.",
+			 status.buffer_size, ndev->metadata.cols * ndev->metadata.size);
+		return -EINVAL;
+	}
+
+	ret = aie2_query_status(ndev, u64_to_user_ptr(status.buffer),
+				status.buffer_size, &status.cols_filled);
+	if (ret) {
+		XDNA_ERR(xdna, "Failed to get AIE status info. Ret: %d", ret);
+		return ret;
+	}
+
+	if (copy_to_user(u64_to_user_ptr(args->buffer), &status, sizeof(status))) {
+		XDNA_ERR(xdna, "Failed to copy AIE request info to user space");
+		return -EFAULT;
+	}
+
+	return 0;
+}
+
+static int aie2_get_aie_metadata(struct amdxdna_client *client,
+				 struct amdxdna_drm_get_info *args)
+{
+	struct amdxdna_drm_query_aie_metadata *meta;
+	struct amdxdna_dev *xdna = client->xdna;
+	struct amdxdna_dev_hdl *ndev;
+	int ret = 0;
+
+	ndev = xdna->dev_handle;
+	meta = kzalloc(sizeof(*meta), GFP_KERNEL);
+	if (!meta)
+		return -ENOMEM;
+
+	meta->col_size = ndev->metadata.size;
+	meta->cols = ndev->metadata.cols;
+	meta->rows = ndev->metadata.rows;
+
+	meta->version.major = ndev->metadata.version.major;
+	meta->version.minor = ndev->metadata.version.minor;
+
+	meta->core.row_count = ndev->metadata.core.row_count;
+	meta->core.row_start = ndev->metadata.core.row_start;
+	meta->core.dma_channel_count = ndev->metadata.core.dma_channel_count;
+	meta->core.lock_count = ndev->metadata.core.lock_count;
+	meta->core.event_reg_count = ndev->metadata.core.event_reg_count;
+
+	meta->mem.row_count = ndev->metadata.mem.row_count;
+	meta->mem.row_start = ndev->metadata.mem.row_start;
+	meta->mem.dma_channel_count = ndev->metadata.mem.dma_channel_count;
+	meta->mem.lock_count = ndev->metadata.mem.lock_count;
+	meta->mem.event_reg_count = ndev->metadata.mem.event_reg_count;
+
+	meta->shim.row_count = ndev->metadata.shim.row_count;
+	meta->shim.row_start = ndev->metadata.shim.row_start;
+	meta->shim.dma_channel_count = ndev->metadata.shim.dma_channel_count;
+	meta->shim.lock_count = ndev->metadata.shim.lock_count;
+	meta->shim.event_reg_count = ndev->metadata.shim.event_reg_count;
+
+	if (copy_to_user(u64_to_user_ptr(args->buffer), meta, sizeof(*meta)))
+		ret = -EFAULT;
+
+	kfree(meta);
+	return ret;
+}
+
+static int aie2_get_aie_version(struct amdxdna_client *client,
+				struct amdxdna_drm_get_info *args)
+{
+	struct amdxdna_drm_query_aie_version version;
+	struct amdxdna_dev *xdna = client->xdna;
+	struct amdxdna_dev_hdl *ndev;
+
+	ndev = xdna->dev_handle;
+	version.major = ndev->version.major;
+	version.minor = ndev->version.minor;
+
+	if (copy_to_user(u64_to_user_ptr(args->buffer), &version, sizeof(version)))
+		return -EFAULT;
+
+	return 0;
+}
+
+static int aie2_get_firmware_version(struct amdxdna_client *client,
+				     struct amdxdna_drm_get_info *args)
+{
+	struct amdxdna_drm_query_firmware_version version;
+	struct amdxdna_dev *xdna = client->xdna;
+
+	version.major = xdna->fw_ver.major;
+	version.minor = xdna->fw_ver.minor;
+	version.patch = xdna->fw_ver.sub;
+	version.build = xdna->fw_ver.build;
+
+	if (copy_to_user(u64_to_user_ptr(args->buffer), &version, sizeof(version)))
+		return -EFAULT;
+
+	return 0;
+}
+
+static int aie2_get_power_mode(struct amdxdna_client *client,
+			       struct amdxdna_drm_get_info *args)
+{
+	struct amdxdna_drm_get_power_mode mode = {};
+	struct amdxdna_dev *xdna = client->xdna;
+	struct amdxdna_dev_hdl *ndev;
+
+	ndev = xdna->dev_handle;
+	mode.power_mode = ndev->pw_mode;
+
+	if (copy_to_user(u64_to_user_ptr(args->buffer), &mode, sizeof(mode)))
+		return -EFAULT;
+
+	return 0;
+}
+
+static int aie2_get_clock_metadata(struct amdxdna_client *client,
+				   struct amdxdna_drm_get_info *args)
+{
+	struct amdxdna_drm_query_clock_metadata *clock;
+	struct amdxdna_dev *xdna = client->xdna;
+	struct amdxdna_dev_hdl *ndev;
+	int ret = 0;
+
+	ndev = xdna->dev_handle;
+	clock = kzalloc(sizeof(*clock), GFP_KERNEL);
+	if (!clock)
+		return -ENOMEM;
+
+	snprintf(clock->mp_npu_clock.name, sizeof(clock->mp_npu_clock.name),
+		 "MP-NPU Clock");
+	clock->mp_npu_clock.freq_mhz = ndev->npuclk_freq;
+	snprintf(clock->h_clock.name, sizeof(clock->h_clock.name), "H Clock");
+	clock->h_clock.freq_mhz = ndev->hclk_freq;
+
+	if (copy_to_user(u64_to_user_ptr(args->buffer), clock, sizeof(*clock)))
+		ret = -EFAULT;
+
+	kfree(clock);
+	return ret;
+}
+
+static int aie2_hwctx_status_cb(struct amdxdna_hwctx *hwctx, void *arg)
+{
+	struct amdxdna_drm_hwctx_entry *tmp __free(kfree) = NULL;
+	struct amdxdna_drm_get_array *array_args = arg;
+	struct amdxdna_drm_hwctx_entry __user *buf;
+	u32 size;
+
+	if (!array_args->num_element)
+		return -EINVAL;
+
+	tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
+	if (!tmp)
+		return -ENOMEM;
+
+	tmp->pid = hwctx->client->pid;
+	tmp->context_id = hwctx->id;
+	tmp->start_col = hwctx->start_col;
+	tmp->num_col = hwctx->num_col;
+	tmp->command_submissions = hwctx->priv->seq;
+	tmp->command_completions = hwctx->priv->completed;
+	tmp->pasid = hwctx->client->pasid;
+	tmp->priority = hwctx->qos.priority;
+	tmp->gops = hwctx->qos.gops;
+	tmp->fps = hwctx->qos.fps;
+	tmp->dma_bandwidth = hwctx->qos.dma_bandwidth;
+	tmp->latency = hwctx->qos.latency;
+	tmp->frame_exec_time = hwctx->qos.frame_exec_time;
+	tmp->state = AMDXDNA_HWCTX_STATE_ACTIVE;
+
+	buf = u64_to_user_ptr(array_args->buffer);
+	size = min(sizeof(*tmp), array_args->element_size);
+
+	if (copy_to_user(buf, tmp, size))
+		return -EFAULT;
+
+	array_args->buffer += size;
+	array_args->num_element--;
+
+	return 0;
+}
+
+static int aie2_get_hwctx_status(struct amdxdna_client *client,
+				 struct amdxdna_drm_get_info *args)
+{
+	struct amdxdna_drm_get_array array_args;
+	struct amdxdna_dev *xdna = client->xdna;
+	struct amdxdna_client *tmp_client;
+	int ret;
+
+	drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock));
+
+	array_args.element_size = sizeof(struct amdxdna_drm_query_hwctx);
+	array_args.buffer = args->buffer;
+	array_args.num_element = args->buffer_size / array_args.element_size;
+	list_for_each_entry(tmp_client, &xdna->client_list, node) {
+		ret = amdxdna_hwctx_walk(tmp_client, &array_args,
+					 aie2_hwctx_status_cb);
+		if (ret)
+			break;
+	}
+
+	args->buffer_size -= (u32)(array_args.buffer - args->buffer);
+	return 0;
+}
+
+static int aie2_query_resource_info(struct amdxdna_client *client,
+				    struct amdxdna_drm_get_info *args)
+{
+	struct amdxdna_drm_get_resource_info res_info;
+	const struct amdxdna_dev_priv *priv;
+	struct amdxdna_dev_hdl *ndev;
+	struct amdxdna_dev *xdna;
+
+	xdna = client->xdna;
+	ndev = xdna->dev_handle;
+	priv = ndev->priv;
+
+	res_info.npu_clk_max = priv->dpm_clk_tbl[ndev->max_dpm_level].hclk;
+	res_info.npu_tops_max = ndev->max_tops;
+	res_info.npu_task_max = priv->hwctx_limit;
+	res_info.npu_tops_curr = ndev->curr_tops;
+	res_info.npu_task_curr = ndev->hwctx_num;
+
+	if (copy_to_user(u64_to_user_ptr(args->buffer), &res_info, sizeof(res_info)))
+		return -EFAULT;
+
+	return 0;
+}
+
+static int aie2_fill_hwctx_map(struct amdxdna_hwctx *hwctx, void *arg)
+{
+	struct amdxdna_dev *xdna = hwctx->client->xdna;
+	u32 *map = arg;
+
+	if (hwctx->fw_ctx_id >= xdna->dev_handle->priv->hwctx_limit) {
+		XDNA_ERR(xdna, "Invalid fw ctx id %d/%d ", hwctx->fw_ctx_id,
+			 xdna->dev_handle->priv->hwctx_limit);
+		return -EINVAL;
+	}
+
+	map[hwctx->fw_ctx_id] = hwctx->id;
+	return 0;
+}
+
+static int aie2_get_telemetry(struct amdxdna_client *client,
+			      struct amdxdna_drm_get_info *args)
+{
+	struct amdxdna_drm_query_telemetry_header *header __free(kfree) = NULL;
+	u32 telemetry_data_sz, header_sz, elem_num;
+	struct amdxdna_dev *xdna = client->xdna;
+	struct amdxdna_client *tmp_client;
+	int ret;
+
+	elem_num = xdna->dev_handle->priv->hwctx_limit;
+	header_sz = struct_size(header, map, elem_num);
+	if (args->buffer_size <= header_sz) {
+		XDNA_ERR(xdna, "Invalid buffer size");
+		return -EINVAL;
+	}
+
+	telemetry_data_sz = args->buffer_size - header_sz;
+	if (telemetry_data_sz > SZ_4M) {
+		XDNA_ERR(xdna, "Buffer size is too big, %d", telemetry_data_sz);
+		return -EINVAL;
+	}
+
+	header = kzalloc(header_sz, GFP_KERNEL);
+	if (!header)
+		return -ENOMEM;
+
+	if (copy_from_user(header, u64_to_user_ptr(args->buffer), sizeof(*header))) {
+		XDNA_ERR(xdna, "Failed to copy telemetry header from user");
+		return -EFAULT;
+	}
+
+	header->map_num_elements = elem_num;
+	list_for_each_entry(tmp_client, &xdna->client_list, node) {
+		ret = amdxdna_hwctx_walk(tmp_client, &header->map,
+					 aie2_fill_hwctx_map);
+		if (ret)
+			return ret;
+	}
+
+	ret = aie2_query_telemetry(xdna->dev_handle,
+				   u64_to_user_ptr(args->buffer + header_sz),
+				   telemetry_data_sz, header);
+	if (ret) {
+		XDNA_ERR(xdna, "Query telemetry failed ret %d", ret);
+		return ret;
+	}
+
+	if (copy_to_user(u64_to_user_ptr(args->buffer), header, header_sz)) {
+		XDNA_ERR(xdna, "Copy header failed");
+		return -EFAULT;
+	}
+
+	return 0;
+}
+
+static int aie2_get_preempt_state(struct amdxdna_client *client,
+				  struct amdxdna_drm_get_info *args)
+{
+	struct amdxdna_drm_attribute_state state = {};
+	struct amdxdna_dev *xdna = client->xdna;
+	struct amdxdna_dev_hdl *ndev;
+
+	ndev = xdna->dev_handle;
+	if (args->param == DRM_AMDXDNA_GET_FORCE_PREEMPT_STATE)
+		state.state = ndev->force_preempt_enabled;
+	else if (args->param == DRM_AMDXDNA_GET_FRAME_BOUNDARY_PREEMPT_STATE)
+		state.state = ndev->frame_boundary_preempt;
+
+	if (copy_to_user(u64_to_user_ptr(args->buffer), &state, sizeof(state)))
+		return -EFAULT;
+
+	return 0;
+}
+
+static int aie2_get_info(struct amdxdna_client *client, struct amdxdna_drm_get_info *args)
+{
+	struct amdxdna_dev *xdna = client->xdna;
+	int ret, idx;
+
+	if (!drm_dev_enter(&xdna->ddev, &idx))
+		return -ENODEV;
+
+	ret = amdxdna_pm_resume_get(xdna);
+	if (ret)
+		goto dev_exit;
+
+	switch (args->param) {
+	case DRM_AMDXDNA_QUERY_AIE_STATUS:
+		ret = aie2_get_aie_status(client, args);
+		break;
+	case DRM_AMDXDNA_QUERY_AIE_METADATA:
+		ret = aie2_get_aie_metadata(client, args);
+		break;
+	case DRM_AMDXDNA_QUERY_AIE_VERSION:
+		ret = aie2_get_aie_version(client, args);
+		break;
+	case DRM_AMDXDNA_QUERY_CLOCK_METADATA:
+		ret = aie2_get_clock_metadata(client, args);
+		break;
+	case DRM_AMDXDNA_QUERY_HW_CONTEXTS:
+		ret = aie2_get_hwctx_status(client, args);
+		break;
+	case DRM_AMDXDNA_QUERY_FIRMWARE_VERSION:
+		ret = aie2_get_firmware_version(client, args);
+		break;
+	case DRM_AMDXDNA_GET_POWER_MODE:
+		ret = aie2_get_power_mode(client, args);
+		break;
+	case DRM_AMDXDNA_QUERY_TELEMETRY:
+		ret = aie2_get_telemetry(client, args);
+		break;
+	case DRM_AMDXDNA_QUERY_RESOURCE_INFO:
+		ret = aie2_query_resource_info(client, args);
+		break;
+	case DRM_AMDXDNA_GET_FORCE_PREEMPT_STATE:
+	case DRM_AMDXDNA_GET_FRAME_BOUNDARY_PREEMPT_STATE:
+		ret = aie2_get_preempt_state(client, args);
+		break;
+	default:
+		XDNA_ERR(xdna, "Not supported request parameter %u", args->param);
+		ret = -EOPNOTSUPP;
+	}
+
+	amdxdna_pm_suspend_put(xdna);
+	XDNA_DBG(xdna, "Got param %d", args->param);
+
+dev_exit:
+	drm_dev_exit(idx);
+	return ret;
+}
+
+static int aie2_query_ctx_status_array(struct amdxdna_client *client,
+				       struct amdxdna_drm_get_array *args)
+{
+	struct amdxdna_drm_get_array array_args;
+	struct amdxdna_dev *xdna = client->xdna;
+	struct amdxdna_client *tmp_client;
+	int ret;
+
+	drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock));
+
+	if (args->element_size > SZ_4K || args->num_element > SZ_1K) {
+		XDNA_DBG(xdna, "Invalid element size %d or number of element %d",
+			 args->element_size, args->num_element);
+		return -EINVAL;
+	}
+
+	array_args.element_size = min(args->element_size,
+				      sizeof(struct amdxdna_drm_hwctx_entry));
+	array_args.buffer = args->buffer;
+	array_args.num_element = args->num_element * args->element_size /
+				array_args.element_size;
+	list_for_each_entry(tmp_client, &xdna->client_list, node) {
+		ret = amdxdna_hwctx_walk(tmp_client, &array_args,
+					 aie2_hwctx_status_cb);
+		if (ret)
+			break;
+	}
+
+	args->element_size = array_args.element_size;
+	args->num_element = (u32)((array_args.buffer - args->buffer) /
+				  args->element_size);
+
+	return 0;
+}
+
+static int aie2_get_array(struct amdxdna_client *client,
+			  struct amdxdna_drm_get_array *args)
+{
+	struct amdxdna_dev *xdna = client->xdna;
+	int ret, idx;
+
+	if (!drm_dev_enter(&xdna->ddev, &idx))
+		return -ENODEV;
+
+	ret = amdxdna_pm_resume_get(xdna);
+	if (ret)
+		goto dev_exit;
+
+	switch (args->param) {
+	case DRM_AMDXDNA_HW_CONTEXT_ALL:
+		ret = aie2_query_ctx_status_array(client, args);
+		break;
+	case DRM_AMDXDNA_HW_LAST_ASYNC_ERR:
+		ret = aie2_get_array_async_error(xdna->dev_handle, args);
+		break;
+	default:
+		XDNA_ERR(xdna, "Not supported request parameter %u", args->param);
+		ret = -EOPNOTSUPP;
+	}
+
+	amdxdna_pm_suspend_put(xdna);
+	XDNA_DBG(xdna, "Got param %d", args->param);
+
+dev_exit:
+	drm_dev_exit(idx);
+	return ret;
+}
+
+static int aie2_set_power_mode(struct amdxdna_client *client,
+			       struct amdxdna_drm_set_state *args)
+{
+	struct amdxdna_drm_set_power_mode power_state;
+	enum amdxdna_power_mode_type power_mode;
+	struct amdxdna_dev *xdna = client->xdna;
+
+	if (copy_from_user(&power_state, u64_to_user_ptr(args->buffer),
+			   sizeof(power_state))) {
+		XDNA_ERR(xdna, "Failed to copy power mode request into kernel");
+		return -EFAULT;
+	}
+
+	if (XDNA_MBZ_DBG(xdna, power_state.pad, sizeof(power_state.pad)))
+		return -EINVAL;
+
+	power_mode = power_state.power_mode;
+	if (power_mode > POWER_MODE_TURBO) {
+		XDNA_ERR(xdna, "Invalid power mode %d", power_mode);
+		return -EINVAL;
+	}
+
+	return aie2_pm_set_mode(xdna->dev_handle, power_mode);
+}
+
+static int aie2_set_preempt_state(struct amdxdna_client *client,
+				  struct amdxdna_drm_set_state *args)
+{
+	struct amdxdna_dev_hdl *ndev = client->xdna->dev_handle;
+	struct amdxdna_drm_attribute_state state;
+	u32 val;
+	int ret;
+
+	if (copy_from_user(&state, u64_to_user_ptr(args->buffer), sizeof(state)))
+		return -EFAULT;
+
+	if (state.state > 1)
+		return -EINVAL;
+
+	if (XDNA_MBZ_DBG(client->xdna, state.pad, sizeof(state.pad)))
+		return -EINVAL;
+
+	if (args->param == DRM_AMDXDNA_SET_FORCE_PREEMPT) {
+		ndev->force_preempt_enabled = state.state;
+	} else if (args->param == DRM_AMDXDNA_SET_FRAME_BOUNDARY_PREEMPT) {
+		val = state.state;
+		ret = aie2_runtime_cfg(ndev, AIE2_RT_CFG_FRAME_BOUNDARY_PREEMPT,
+				       &val);
+		if (ret)
+			return ret;
+
+		ndev->frame_boundary_preempt = state.state;
+	}
+
+	return 0;
+}
+
+static int aie2_set_state(struct amdxdna_client *client,
+			  struct amdxdna_drm_set_state *args)
+{
+	struct amdxdna_dev *xdna = client->xdna;
+	int ret, idx;
+
+	if (!drm_dev_enter(&xdna->ddev, &idx))
+		return -ENODEV;
+
+	ret = amdxdna_pm_resume_get(xdna);
+	if (ret)
+		goto dev_exit;
+
+	switch (args->param) {
+	case DRM_AMDXDNA_SET_POWER_MODE:
+		ret = aie2_set_power_mode(client, args);
+		break;
+	case DRM_AMDXDNA_SET_FORCE_PREEMPT:
+	case DRM_AMDXDNA_SET_FRAME_BOUNDARY_PREEMPT:
+		ret = aie2_set_preempt_state(client, args);
+		break;
+	default:
+		XDNA_ERR(xdna, "Not supported request parameter %u", args->param);
+		ret = -EOPNOTSUPP;
+		break;
+	}
+
+	amdxdna_pm_suspend_put(xdna);
+dev_exit:
+	drm_dev_exit(idx);
+	return ret;
+}
+
+const struct amdxdna_dev_ops aie2_ops = {
+	.init = aie2_init,
+	.fini = aie2_fini,
+	.resume = aie2_hw_resume,
+	.suspend = aie2_hw_suspend,
+	.get_aie_info = aie2_get_info,
+	.set_aie_state = aie2_set_state,
+	.hwctx_init = aie2_hwctx_init,
+	.hwctx_fini = aie2_hwctx_fini,
+	.hwctx_config = aie2_hwctx_config,
+	.hwctx_sync_debug_bo = aie2_hwctx_sync_debug_bo,
+	.cmd_submit = aie2_cmd_submit,
+	.hmm_invalidate = aie2_hmm_invalidate,
+	.get_array = aie2_get_array,
+};
diff --git a/drivers/accel/amdxdna/aie2_pci.h b/drivers/accel/amdxdna/aie2_pci.h
new file mode 100644
index 000000000000..a5f9c42155d1
--- /dev/null
+++ b/drivers/accel/amdxdna/aie2_pci.h
@@ -0,0 +1,346 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2023-2024, Advanced Micro Devices, Inc.
+ */
+
+#ifndef _AIE2_PCI_H_
+#define _AIE2_PCI_H_
+
+#include <drm/amdxdna_accel.h>
+#include <linux/semaphore.h>
+
+#include "amdxdna_mailbox.h"
+
+#define AIE2_INTERVAL	20000	/* us */
+#define AIE2_TIMEOUT	1000000	/* us */
+
+/* Firmware determines device memory base address and size */
+#define AIE2_DEVM_BASE	0x4000000
+#define AIE2_DEVM_SIZE	SZ_64M
+
+#define NDEV2PDEV(ndev) (to_pci_dev((ndev)->xdna->ddev.dev))
+
+#define AIE2_SRAM_OFF(ndev, addr) ((addr) - (ndev)->priv->sram_dev_addr)
+#define AIE2_MBOX_OFF(ndev, addr) ((addr) - (ndev)->priv->mbox_dev_addr)
+
+#define PSP_REG_BAR(ndev, idx) ((ndev)->priv->psp_regs_off[(idx)].bar_idx)
+#define PSP_REG_OFF(ndev, idx) ((ndev)->priv->psp_regs_off[(idx)].offset)
+#define SRAM_REG_OFF(ndev, idx) ((ndev)->priv->sram_offs[(idx)].offset)
+
+#define SMU_REG(ndev, idx) \
+({ \
+	typeof(ndev) _ndev = ndev; \
+	((_ndev)->smu_base + (_ndev)->priv->smu_regs_off[(idx)].offset); \
+})
+#define SRAM_GET_ADDR(ndev, idx) \
+({ \
+	typeof(ndev) _ndev = ndev; \
+	((_ndev)->sram_base + SRAM_REG_OFF((_ndev), (idx))); \
+})
+
+#define CHAN_SLOT_SZ SZ_8K
+#define MBOX_SIZE(ndev) \
+({ \
+	typeof(ndev) _ndev = (ndev); \
+	((_ndev)->priv->mbox_size) ? (_ndev)->priv->mbox_size : \
+	pci_resource_len(NDEV2PDEV(_ndev), (_ndev)->xdna->dev_info->mbox_bar); \
+})
+
+enum aie2_smu_reg_idx {
+	SMU_CMD_REG = 0,
+	SMU_ARG_REG,
+	SMU_INTR_REG,
+	SMU_RESP_REG,
+	SMU_OUT_REG,
+	SMU_MAX_REGS /* Keep this at the end */
+};
+
+enum aie2_sram_reg_idx {
+	MBOX_CHANN_OFF = 0,
+	FW_ALIVE_OFF,
+	SRAM_MAX_INDEX /* Keep this at the end */
+};
+
+enum psp_reg_idx {
+	PSP_CMD_REG = 0,
+	PSP_ARG0_REG,
+	PSP_ARG1_REG,
+	PSP_ARG2_REG,
+	PSP_NUM_IN_REGS, /* number of input registers */
+	PSP_INTR_REG = PSP_NUM_IN_REGS,
+	PSP_STATUS_REG,
+	PSP_RESP_REG,
+	PSP_MAX_REGS /* Keep this at the end */
+};
+
+struct amdxdna_client;
+struct amdxdna_fw_ver;
+struct amdxdna_hwctx;
+struct amdxdna_sched_job;
+
+struct psp_config {
+	const void	*fw_buf;
+	u32		fw_size;
+	void __iomem	*psp_regs[PSP_MAX_REGS];
+};
+
+struct aie_version {
+	u16 major;
+	u16 minor;
+};
+
+struct aie_tile_metadata {
+	u16 row_count;
+	u16 row_start;
+	u16 dma_channel_count;
+	u16 lock_count;
+	u16 event_reg_count;
+};
+
+struct aie_metadata {
+	u32 size;
+	u16 cols;
+	u16 rows;
+	struct aie_version version;
+	struct aie_tile_metadata core;
+	struct aie_tile_metadata mem;
+	struct aie_tile_metadata shim;
+};
+
+enum rt_config_category {
+	AIE2_RT_CFG_INIT,
+	AIE2_RT_CFG_CLK_GATING,
+	AIE2_RT_CFG_FORCE_PREEMPT,
+	AIE2_RT_CFG_FRAME_BOUNDARY_PREEMPT,
+};
+
+struct rt_config {
+	u32	type;
+	u32	value;
+	u32	category;
+	unsigned long feature_mask;
+};
+
+struct dpm_clk_freq {
+	u32	npuclk;
+	u32	hclk;
+};
+
+/*
+ * Define the maximum number of pending commands in a hardware context.
+ * Must be power of 2!
+ */
+#define HWCTX_MAX_CMDS		4
+#define get_job_idx(seq) ((seq) & (HWCTX_MAX_CMDS - 1))
+struct amdxdna_hwctx_priv {
+	struct amdxdna_gem_obj		*heap;
+	void				*mbox_chann;
+
+	struct drm_gpu_scheduler	sched;
+	struct drm_sched_entity		entity;
+
+	struct mutex			io_lock; /* protect seq and cmd order */
+	struct wait_queue_head		job_free_wq;
+	u32				num_pending;
+	u64				seq;
+	struct semaphore		job_sem;
+	bool				job_done;
+
+	/* Completed job counter */
+	u64				completed;
+
+	struct amdxdna_gem_obj		*cmd_buf[HWCTX_MAX_CMDS];
+	struct drm_syncobj		*syncobj;
+};
+
+enum aie2_dev_status {
+	AIE2_DEV_UNINIT,
+	AIE2_DEV_INIT,
+	AIE2_DEV_START,
+};
+
+struct aie2_exec_msg_ops {
+	int (*init_cu_req)(struct amdxdna_gem_obj *cmd_bo, void *req,
+			   size_t *size, u32 *msg_op);
+	int (*init_dpu_req)(struct amdxdna_gem_obj *cmd_bo, void *req,
+			    size_t *size, u32 *msg_op);
+	void (*init_chain_req)(void *req, u64 slot_addr, size_t size, u32 cmd_cnt);
+	int (*fill_cf_slot)(struct amdxdna_gem_obj *cmd_bo, void *slot, size_t *size);
+	int (*fill_dpu_slot)(struct amdxdna_gem_obj *cmd_bo, void *slot, size_t *size);
+	int (*fill_preempt_slot)(struct amdxdna_gem_obj *cmd_bo, void *slot, size_t *size);
+	int (*fill_elf_slot)(struct amdxdna_gem_obj *cmd_bo, void *slot, size_t *size);
+	u32 (*get_chain_msg_op)(u32 cmd_op);
+};
+
+struct amdxdna_dev_hdl {
+	struct amdxdna_dev		*xdna;
+	const struct amdxdna_dev_priv	*priv;
+	void			__iomem *sram_base;
+	void			__iomem *smu_base;
+	void			__iomem *mbox_base;
+	struct psp_device		*psp_hdl;
+
+	struct xdna_mailbox_chann_res	mgmt_x2i;
+	struct xdna_mailbox_chann_res	mgmt_i2x;
+	u32				mgmt_chan_idx;
+	u32				mgmt_prot_major;
+	u32				mgmt_prot_minor;
+
+	u32				total_col;
+	struct aie_version		version;
+	struct aie_metadata		metadata;
+	unsigned long			feature_mask;
+	struct aie2_exec_msg_ops	*exec_msg_ops;
+
+	/* power management and clock*/
+	enum amdxdna_power_mode_type	pw_mode;
+	u32				dpm_level;
+	u32				dft_dpm_level;
+	u32				max_dpm_level;
+	u32				clk_gating;
+	u32				npuclk_freq;
+	u32				hclk_freq;
+	u32				max_tops;
+	u32				curr_tops;
+	u32				force_preempt_enabled;
+	u32				frame_boundary_preempt;
+
+	/* Mailbox and the management channel */
+	struct mailbox			*mbox;
+	struct mailbox_channel		*mgmt_chann;
+	struct async_events		*async_events;
+
+	enum aie2_dev_status		dev_status;
+	u32				hwctx_num;
+
+	struct amdxdna_async_error	last_async_err;
+};
+
+#define DEFINE_BAR_OFFSET(reg_name, bar, reg_addr) \
+	[reg_name] = {bar##_BAR_INDEX, (reg_addr) - bar##_BAR_BASE}
+
+struct aie2_bar_off_pair {
+	int	bar_idx;
+	u32	offset;
+};
+
+struct aie2_hw_ops {
+	int (*set_dpm)(struct amdxdna_dev_hdl *ndev, u32 dpm_level);
+};
+
+enum aie2_fw_feature {
+	AIE2_NPU_COMMAND,
+	AIE2_PREEMPT,
+	AIE2_FEATURE_MAX
+};
+
+struct aie2_fw_feature_tbl {
+	enum aie2_fw_feature feature;
+	u32 max_minor;
+	u32 min_minor;
+};
+
+#define AIE2_FEATURE_ON(ndev, feature)	test_bit(feature, &(ndev)->feature_mask)
+
+struct amdxdna_dev_priv {
+	const char			*fw_path;
+	u64				protocol_major;
+	u64				protocol_minor;
+	const struct rt_config		*rt_config;
+	const struct dpm_clk_freq	*dpm_clk_tbl;
+	const struct aie2_fw_feature_tbl *fw_feature_tbl;
+
+#define COL_ALIGN_NONE   0
+#define COL_ALIGN_NATURE 1
+	u32				col_align;
+	u32				mbox_dev_addr;
+	/* If mbox_size is 0, use BAR size. See MBOX_SIZE macro */
+	u32				mbox_size;
+	u32				hwctx_limit;
+	u32				sram_dev_addr;
+	struct aie2_bar_off_pair	sram_offs[SRAM_MAX_INDEX];
+	struct aie2_bar_off_pair	psp_regs_off[PSP_MAX_REGS];
+	struct aie2_bar_off_pair	smu_regs_off[SMU_MAX_REGS];
+	struct aie2_hw_ops		hw_ops;
+};
+
+extern const struct amdxdna_dev_ops aie2_ops;
+
+int aie2_runtime_cfg(struct amdxdna_dev_hdl *ndev,
+		     enum rt_config_category category, u32 *val);
+
+/* aie2 npu hw config */
+extern const struct dpm_clk_freq npu1_dpm_clk_table[];
+extern const struct dpm_clk_freq npu4_dpm_clk_table[];
+extern const struct rt_config npu1_default_rt_cfg[];
+extern const struct rt_config npu4_default_rt_cfg[];
+extern const struct aie2_fw_feature_tbl npu4_fw_feature_table[];
+
+/* aie2_smu.c */
+int aie2_smu_init(struct amdxdna_dev_hdl *ndev);
+void aie2_smu_fini(struct amdxdna_dev_hdl *ndev);
+int npu1_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level);
+int npu4_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level);
+
+/* aie2_pm.c */
+int aie2_pm_init(struct amdxdna_dev_hdl *ndev);
+int aie2_pm_set_mode(struct amdxdna_dev_hdl *ndev, enum amdxdna_power_mode_type target);
+
+/* aie2_psp.c */
+struct psp_device *aie2m_psp_create(struct drm_device *ddev, struct psp_config *conf);
+int aie2_psp_start(struct psp_device *psp);
+void aie2_psp_stop(struct psp_device *psp);
+
+/* aie2_error.c */
+int aie2_error_async_events_alloc(struct amdxdna_dev_hdl *ndev);
+void aie2_error_async_events_free(struct amdxdna_dev_hdl *ndev);
+int aie2_error_async_msg_thread(void *data);
+int aie2_get_array_async_error(struct amdxdna_dev_hdl *ndev,
+			       struct amdxdna_drm_get_array *args);
+
+/* aie2_message.c */
+void aie2_msg_init(struct amdxdna_dev_hdl *ndev);
+int aie2_suspend_fw(struct amdxdna_dev_hdl *ndev);
+int aie2_resume_fw(struct amdxdna_dev_hdl *ndev);
+int aie2_set_runtime_cfg(struct amdxdna_dev_hdl *ndev, u32 type, u64 value);
+int aie2_get_runtime_cfg(struct amdxdna_dev_hdl *ndev, u32 type, u64 *value);
+int aie2_assign_mgmt_pasid(struct amdxdna_dev_hdl *ndev, u16 pasid);
+int aie2_query_aie_version(struct amdxdna_dev_hdl *ndev, struct aie_version *version);
+int aie2_query_aie_metadata(struct amdxdna_dev_hdl *ndev, struct aie_metadata *metadata);
+int aie2_query_firmware_version(struct amdxdna_dev_hdl *ndev,
+				struct amdxdna_fw_ver *fw_ver);
+int aie2_create_context(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwctx);
+int aie2_destroy_context(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwctx);
+int aie2_map_host_buf(struct amdxdna_dev_hdl *ndev, u32 context_id, u64 addr, u64 size);
+int aie2_query_status(struct amdxdna_dev_hdl *ndev, char __user *buf, u32 size, u32 *cols_filled);
+int aie2_query_telemetry(struct amdxdna_dev_hdl *ndev,
+			 char __user *buf, u32 size,
+			 struct amdxdna_drm_query_telemetry_header *header);
+int aie2_register_asyn_event_msg(struct amdxdna_dev_hdl *ndev, dma_addr_t addr, u32 size,
+				 void *handle, int (*cb)(void*, void __iomem *, size_t));
+int aie2_config_cu(struct amdxdna_hwctx *hwctx,
+		   int (*notify_cb)(void *, void __iomem *, size_t));
+int aie2_execbuf(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job,
+		 int (*notify_cb)(void *, void __iomem *, size_t));
+int aie2_cmdlist_single_execbuf(struct amdxdna_hwctx *hwctx,
+				struct amdxdna_sched_job *job,
+				int (*notify_cb)(void *, void __iomem *, size_t));
+int aie2_cmdlist_multi_execbuf(struct amdxdna_hwctx *hwctx,
+			       struct amdxdna_sched_job *job,
+			       int (*notify_cb)(void *, void __iomem *, size_t));
+int aie2_sync_bo(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job,
+		 int (*notify_cb)(void *, void __iomem *, size_t));
+int aie2_config_debug_bo(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job,
+			 int (*notify_cb)(void *, void __iomem *, size_t));
+
+/* aie2_hwctx.c */
+int aie2_hwctx_init(struct amdxdna_hwctx *hwctx);
+void aie2_hwctx_fini(struct amdxdna_hwctx *hwctx);
+int aie2_hwctx_config(struct amdxdna_hwctx *hwctx, u32 type, u64 value, void *buf, u32 size);
+int aie2_hwctx_sync_debug_bo(struct amdxdna_hwctx *hwctx, u32 debug_bo_hdl);
+void aie2_hwctx_suspend(struct amdxdna_client *client);
+int aie2_hwctx_resume(struct amdxdna_client *client);
+int aie2_cmd_submit(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job, u64 *seq);
+void aie2_hmm_invalidate(struct amdxdna_gem_obj *abo, unsigned long cur_seq);
+
+#endif /* _AIE2_PCI_H_ */
diff --git a/drivers/accel/amdxdna/aie2_pm.c b/drivers/accel/amdxdna/aie2_pm.c
new file mode 100644
index 000000000000..426c38fce848
--- /dev/null
+++ b/drivers/accel/amdxdna/aie2_pm.c
@@ -0,0 +1,108 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024, Advanced Micro Devices, Inc.
+ */
+
+#include <drm/amdxdna_accel.h>
+#include <drm/drm_device.h>
+#include <drm/drm_print.h>
+#include <drm/gpu_scheduler.h>
+
+#include "aie2_pci.h"
+#include "amdxdna_pci_drv.h"
+
+#define AIE2_CLK_GATING_ENABLE	1
+#define AIE2_CLK_GATING_DISABLE	0
+
+static int aie2_pm_set_clk_gating(struct amdxdna_dev_hdl *ndev, u32 val)
+{
+	int ret;
+
+	ret = aie2_runtime_cfg(ndev, AIE2_RT_CFG_CLK_GATING, &val);
+	if (ret)
+		return ret;
+
+	ndev->clk_gating = val;
+	return 0;
+}
+
+int aie2_pm_init(struct amdxdna_dev_hdl *ndev)
+{
+	int ret;
+
+	if (ndev->dev_status != AIE2_DEV_UNINIT) {
+		/* Resume device */
+		ret = ndev->priv->hw_ops.set_dpm(ndev, ndev->dpm_level);
+		if (ret)
+			return ret;
+
+		ret = aie2_pm_set_clk_gating(ndev, ndev->clk_gating);
+		if (ret)
+			return ret;
+
+		return 0;
+	}
+
+	while (ndev->priv->dpm_clk_tbl[ndev->max_dpm_level].hclk)
+		ndev->max_dpm_level++;
+	ndev->max_dpm_level--;
+
+	ret = ndev->priv->hw_ops.set_dpm(ndev, ndev->max_dpm_level);
+	if (ret)
+		return ret;
+
+	ret = aie2_pm_set_clk_gating(ndev, AIE2_CLK_GATING_ENABLE);
+	if (ret)
+		return ret;
+
+	ndev->pw_mode = POWER_MODE_DEFAULT;
+	ndev->dft_dpm_level = ndev->max_dpm_level;
+
+	return 0;
+}
+
+int aie2_pm_set_mode(struct amdxdna_dev_hdl *ndev, enum amdxdna_power_mode_type target)
+{
+	struct amdxdna_dev *xdna = ndev->xdna;
+	u32 clk_gating, dpm_level;
+	int ret;
+
+	drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock));
+
+	if (ndev->pw_mode == target)
+		return 0;
+
+	switch (target) {
+	case POWER_MODE_TURBO:
+		if (ndev->hwctx_num) {
+			XDNA_ERR(xdna, "Can not set turbo when there is active hwctx");
+			return -EINVAL;
+		}
+
+		clk_gating = AIE2_CLK_GATING_DISABLE;
+		dpm_level = ndev->max_dpm_level;
+		break;
+	case POWER_MODE_HIGH:
+		clk_gating = AIE2_CLK_GATING_ENABLE;
+		dpm_level = ndev->max_dpm_level;
+		break;
+	case POWER_MODE_DEFAULT:
+		clk_gating = AIE2_CLK_GATING_ENABLE;
+		dpm_level = ndev->dft_dpm_level;
+		break;
+	default:
+		return -EOPNOTSUPP;
+	}
+
+	ret = ndev->priv->hw_ops.set_dpm(ndev, dpm_level);
+	if (ret)
+		return ret;
+
+	ret = aie2_pm_set_clk_gating(ndev, clk_gating);
+	if (ret)
+		return ret;
+
+	ndev->pw_mode = target;
+
+	return 0;
+}
diff --git a/drivers/accel/amdxdna/aie2_psp.c b/drivers/accel/amdxdna/aie2_psp.c
new file mode 100644
index 000000000000..f28a060a8810
--- /dev/null
+++ b/drivers/accel/amdxdna/aie2_psp.c
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022-2024, Advanced Micro Devices, Inc.
+ */
+
+#include <drm/drm_device.h>
+#include <drm/drm_gem_shmem_helper.h>
+#include <drm/drm_managed.h>
+#include <drm/drm_print.h>
+#include <drm/gpu_scheduler.h>
+#include <linux/bitfield.h>
+#include <linux/iopoll.h>
+
+#include "aie2_pci.h"
+#include "amdxdna_mailbox.h"
+#include "amdxdna_pci_drv.h"
+
+#define PSP_STATUS_READY	BIT(31)
+
+/* PSP commands */
+#define PSP_VALIDATE		1
+#define PSP_START		2
+#define PSP_RELEASE_TMR		3
+
+/* PSP special arguments */
+#define PSP_START_COPY_FW	1
+
+/* PSP response error code */
+#define PSP_ERROR_CANCEL	0xFFFF0002
+#define PSP_ERROR_BAD_STATE	0xFFFF0007
+
+#define PSP_FW_ALIGN		0x10000
+#define PSP_POLL_INTERVAL	20000	/* us */
+#define PSP_POLL_TIMEOUT	1000000	/* us */
+
+#define PSP_REG(p, reg) ((p)->psp_regs[reg])
+
+struct psp_device {
+	struct drm_device	*ddev;
+	struct psp_config	conf;
+	u32			fw_buf_sz;
+	u64			fw_paddr;
+	void			*fw_buffer;
+	void __iomem		*psp_regs[PSP_MAX_REGS];
+};
+
+static int psp_exec(struct psp_device *psp, u32 *reg_vals)
+{
+	u32 resp_code;
+	int ret, i;
+	u32 ready;
+
+	/* Write command and argument registers */
+	for (i = 0; i < PSP_NUM_IN_REGS; i++)
+		writel(reg_vals[i], PSP_REG(psp, i));
+
+	/* clear and set PSP INTR register to kick off */
+	writel(0, PSP_REG(psp, PSP_INTR_REG));
+	writel(1, PSP_REG(psp, PSP_INTR_REG));
+
+	/* PSP should be busy. Wait for ready, so we know task is done. */
+	ret = readx_poll_timeout(readl, PSP_REG(psp, PSP_STATUS_REG), ready,
+				 FIELD_GET(PSP_STATUS_READY, ready),
+				 PSP_POLL_INTERVAL, PSP_POLL_TIMEOUT);
+	if (ret) {
+		drm_err(psp->ddev, "PSP is not ready, ret 0x%x", ret);
+		return ret;
+	}
+
+	resp_code = readl(PSP_REG(psp, PSP_RESP_REG));
+	if (resp_code) {
+		drm_err(psp->ddev, "fw return error 0x%x", resp_code);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+void aie2_psp_stop(struct psp_device *psp)
+{
+	u32 reg_vals[PSP_NUM_IN_REGS] = { PSP_RELEASE_TMR, };
+	int ret;
+
+	ret = psp_exec(psp, reg_vals);
+	if (ret)
+		drm_err(psp->ddev, "release tmr failed, ret %d", ret);
+}
+
+int aie2_psp_start(struct psp_device *psp)
+{
+	u32 reg_vals[PSP_NUM_IN_REGS];
+	int ret;
+
+	reg_vals[0] = PSP_VALIDATE;
+	reg_vals[1] = lower_32_bits(psp->fw_paddr);
+	reg_vals[2] = upper_32_bits(psp->fw_paddr);
+	reg_vals[3] = psp->fw_buf_sz;
+
+	ret = psp_exec(psp, reg_vals);
+	if (ret) {
+		drm_err(psp->ddev, "failed to validate fw, ret %d", ret);
+		return ret;
+	}
+
+	memset(reg_vals, 0, sizeof(reg_vals));
+	reg_vals[0] = PSP_START;
+	reg_vals[1] = PSP_START_COPY_FW;
+	ret = psp_exec(psp, reg_vals);
+	if (ret) {
+		drm_err(psp->ddev, "failed to start fw, ret %d", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+struct psp_device *aie2m_psp_create(struct drm_device *ddev, struct psp_config *conf)
+{
+	struct psp_device *psp;
+	u64 offset;
+
+	psp = drmm_kzalloc(ddev, sizeof(*psp), GFP_KERNEL);
+	if (!psp)
+		return NULL;
+
+	psp->ddev = ddev;
+	memcpy(psp->psp_regs, conf->psp_regs, sizeof(psp->psp_regs));
+
+	psp->fw_buf_sz = ALIGN(conf->fw_size, PSP_FW_ALIGN);
+	psp->fw_buffer = drmm_kmalloc(ddev, psp->fw_buf_sz + PSP_FW_ALIGN, GFP_KERNEL);
+	if (!psp->fw_buffer) {
+		drm_err(ddev, "no memory for fw buffer");
+		return NULL;
+	}
+
+	/*
+	 * AMD Platform Security Processor(PSP) requires host physical
+	 * address to load NPU firmware.
+	 */
+	psp->fw_paddr = virt_to_phys(psp->fw_buffer);
+	offset = ALIGN(psp->fw_paddr, PSP_FW_ALIGN) - psp->fw_paddr;
+	psp->fw_paddr += offset;
+	memcpy(psp->fw_buffer + offset, conf->fw_buf, conf->fw_size);
+
+	return psp;
+}
diff --git a/drivers/accel/amdxdna/aie2_smu.c b/drivers/accel/amdxdna/aie2_smu.c
new file mode 100644
index 000000000000..bd94ee96c2bc
--- /dev/null
+++ b/drivers/accel/amdxdna/aie2_smu.c
@@ -0,0 +1,177 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022-2024, Advanced Micro Devices, Inc.
+ */
+
+#include <drm/drm_device.h>
+#include <drm/drm_gem_shmem_helper.h>
+#include <drm/drm_print.h>
+#include <drm/gpu_scheduler.h>
+#include <linux/iopoll.h>
+
+#include "aie2_pci.h"
+#include "amdxdna_pci_drv.h"
+#include "amdxdna_pm.h"
+
+#define SMU_RESULT_OK		1
+
+/* SMU commands */
+#define AIE2_SMU_POWER_ON		0x3
+#define AIE2_SMU_POWER_OFF		0x4
+#define AIE2_SMU_SET_MPNPUCLK_FREQ	0x5
+#define AIE2_SMU_SET_HCLK_FREQ		0x6
+#define AIE2_SMU_SET_SOFT_DPMLEVEL	0x7
+#define AIE2_SMU_SET_HARD_DPMLEVEL	0x8
+
+#define NPU4_DPM_TOPS(ndev, dpm_level) \
+({ \
+	typeof(ndev) _ndev = ndev; \
+	(4096 * (_ndev)->total_col * \
+	 (_ndev)->priv->dpm_clk_tbl[dpm_level].hclk / 1000000); \
+})
+
+static int aie2_smu_exec(struct amdxdna_dev_hdl *ndev, u32 reg_cmd,
+			 u32 reg_arg, u32 *out)
+{
+	u32 resp;
+	int ret;
+
+	writel(0, SMU_REG(ndev, SMU_RESP_REG));
+	writel(reg_arg, SMU_REG(ndev, SMU_ARG_REG));
+	writel(reg_cmd, SMU_REG(ndev, SMU_CMD_REG));
+
+	/* Clear and set SMU_INTR_REG to kick off */
+	writel(0, SMU_REG(ndev, SMU_INTR_REG));
+	writel(1, SMU_REG(ndev, SMU_INTR_REG));
+
+	ret = readx_poll_timeout(readl, SMU_REG(ndev, SMU_RESP_REG), resp,
+				 resp, AIE2_INTERVAL, AIE2_TIMEOUT);
+	if (ret) {
+		XDNA_ERR(ndev->xdna, "smu cmd %d timed out", reg_cmd);
+		return ret;
+	}
+
+	if (out)
+		*out = readl(SMU_REG(ndev, SMU_OUT_REG));
+
+	if (resp != SMU_RESULT_OK) {
+		XDNA_ERR(ndev->xdna, "smu cmd %d failed, 0x%x", reg_cmd, resp);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int npu1_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level)
+{
+	u32 freq;
+	int ret;
+
+	ret = amdxdna_pm_resume_get(ndev->xdna);
+	if (ret)
+		return ret;
+
+	ret = aie2_smu_exec(ndev, AIE2_SMU_SET_MPNPUCLK_FREQ,
+			    ndev->priv->dpm_clk_tbl[dpm_level].npuclk, &freq);
+	if (ret) {
+		XDNA_ERR(ndev->xdna, "Set npu clock to %d failed, ret %d\n",
+			 ndev->priv->dpm_clk_tbl[dpm_level].npuclk, ret);
+		goto suspend_put;
+	}
+	ndev->npuclk_freq = freq;
+
+	ret = aie2_smu_exec(ndev, AIE2_SMU_SET_HCLK_FREQ,
+			    ndev->priv->dpm_clk_tbl[dpm_level].hclk, &freq);
+	if (ret) {
+		XDNA_ERR(ndev->xdna, "Set h clock to %d failed, ret %d\n",
+			 ndev->priv->dpm_clk_tbl[dpm_level].hclk, ret);
+		goto suspend_put;
+	}
+
+	amdxdna_pm_suspend_put(ndev->xdna);
+	ndev->hclk_freq = freq;
+	ndev->dpm_level = dpm_level;
+	ndev->max_tops = 2 * ndev->total_col;
+	ndev->curr_tops = ndev->max_tops * freq / 1028;
+
+	XDNA_DBG(ndev->xdna, "MP-NPU clock %d, H clock %d\n",
+		 ndev->npuclk_freq, ndev->hclk_freq);
+
+	return 0;
+
+suspend_put:
+	amdxdna_pm_suspend_put(ndev->xdna);
+	return ret;
+}
+
+int npu4_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level)
+{
+	int ret;
+
+	ret = amdxdna_pm_resume_get(ndev->xdna);
+	if (ret)
+		return ret;
+
+	ret = aie2_smu_exec(ndev, AIE2_SMU_SET_HARD_DPMLEVEL, dpm_level, NULL);
+	if (ret) {
+		XDNA_ERR(ndev->xdna, "Set hard dpm level %d failed, ret %d ",
+			 dpm_level, ret);
+		goto suspend_put;
+	}
+
+	ret = aie2_smu_exec(ndev, AIE2_SMU_SET_SOFT_DPMLEVEL, dpm_level, NULL);
+	if (ret) {
+		XDNA_ERR(ndev->xdna, "Set soft dpm level %d failed, ret %d",
+			 dpm_level, ret);
+		goto suspend_put;
+	}
+
+	amdxdna_pm_suspend_put(ndev->xdna);
+	ndev->npuclk_freq = ndev->priv->dpm_clk_tbl[dpm_level].npuclk;
+	ndev->hclk_freq = ndev->priv->dpm_clk_tbl[dpm_level].hclk;
+	ndev->dpm_level = dpm_level;
+	ndev->max_tops = NPU4_DPM_TOPS(ndev, ndev->max_dpm_level);
+	ndev->curr_tops = NPU4_DPM_TOPS(ndev, dpm_level);
+
+	XDNA_DBG(ndev->xdna, "MP-NPU clock %d, H clock %d\n",
+		 ndev->npuclk_freq, ndev->hclk_freq);
+
+	return 0;
+
+suspend_put:
+	amdxdna_pm_suspend_put(ndev->xdna);
+	return ret;
+}
+
+int aie2_smu_init(struct amdxdna_dev_hdl *ndev)
+{
+	int ret;
+
+	/*
+	 * Failing to set power off indicates an unrecoverable hardware or
+	 * firmware error.
+	 */
+	ret = aie2_smu_exec(ndev, AIE2_SMU_POWER_OFF, 0, NULL);
+	if (ret) {
+		XDNA_ERR(ndev->xdna, "Access power failed, ret %d", ret);
+		return ret;
+	}
+
+	ret = aie2_smu_exec(ndev, AIE2_SMU_POWER_ON, 0, NULL);
+	if (ret) {
+		XDNA_ERR(ndev->xdna, "Power on failed, ret %d", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+void aie2_smu_fini(struct amdxdna_dev_hdl *ndev)
+{
+	int ret;
+
+	ndev->priv->hw_ops.set_dpm(ndev, 0);
+	ret = aie2_smu_exec(ndev, AIE2_SMU_POWER_OFF, 0, NULL);
+	if (ret)
+		XDNA_ERR(ndev->xdna, "Power off failed, ret %d", ret);
+}
diff --git a/drivers/accel/amdxdna/aie2_solver.c b/drivers/accel/amdxdna/aie2_solver.c
new file mode 100644
index 000000000000..2013d1f13aae
--- /dev/null
+++ b/drivers/accel/amdxdna/aie2_solver.c
@@ -0,0 +1,380 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022-2024, Advanced Micro Devices, Inc.
+ */
+
+#include <drm/drm_device.h>
+#include <drm/drm_managed.h>
+#include <drm/drm_print.h>
+#include <linux/bitops.h>
+#include <linux/bitmap.h>
+#include <linux/slab.h>
+
+#include "aie2_solver.h"
+
+struct partition_node {
+	struct list_head	list;
+	u32			nshared;	/* # shared requests */
+	u32			start_col;	/* start column */
+	u32			ncols;		/* # columns */
+	bool			exclusive;	/* can not be shared if set */
+};
+
+struct solver_node {
+	struct list_head	list;
+	u64			rid;		/* Request ID from consumer */
+
+	struct partition_node	*pt_node;
+	void			*cb_arg;
+	u32			dpm_level;
+	u32			cols_len;
+	u32			start_cols[] __counted_by(cols_len);
+};
+
+struct solver_rgroup {
+	u32				rgid;
+	u32				nnode;
+	u32				npartition_node;
+
+	DECLARE_BITMAP(resbit, XRS_MAX_COL);
+	struct list_head		node_list;
+	struct list_head		pt_node_list;
+};
+
+struct solver_state {
+	struct solver_rgroup		rgp;
+	struct init_config		cfg;
+	struct xrs_action_ops		*actions;
+};
+
+static u32 calculate_gops(struct aie_qos *rqos)
+{
+	u32 service_rate = 0;
+
+	if (rqos->latency)
+		service_rate = (1000 / rqos->latency);
+
+	if (rqos->fps > service_rate)
+		return rqos->fps * rqos->gops;
+
+	return service_rate * rqos->gops;
+}
+
+/*
+ * qos_meet() - Check the QOS request can be met.
+ */
+static int qos_meet(struct solver_state *xrs, struct aie_qos *rqos, u32 cgops)
+{
+	u32 request_gops = calculate_gops(rqos) * xrs->cfg.sys_eff_factor;
+
+	if (request_gops <= cgops)
+		return 0;
+
+	return -EINVAL;
+}
+
+/*
+ * sanity_check() - Do a basic sanity check on allocation request.
+ */
+static int sanity_check(struct solver_state *xrs, struct alloc_requests *req)
+{
+	struct cdo_parts *cdop = &req->cdo;
+	struct aie_qos *rqos = &req->rqos;
+	u32 cu_clk_freq;
+
+	if (cdop->ncols > xrs->cfg.total_col)
+		return -EINVAL;
+
+	/*
+	 * We can find at least one CDOs groups that meet the
+	 * GOPs requirement.
+	 */
+	cu_clk_freq = xrs->cfg.clk_list.cu_clk_list[xrs->cfg.clk_list.num_levels - 1];
+
+	if (qos_meet(xrs, rqos, cdop->qos_cap.opc * cu_clk_freq / 1000))
+		return -EINVAL;
+
+	return 0;
+}
+
+static bool is_valid_qos_dpm_params(struct aie_qos *rqos)
+{
+	/*
+	 * gops is retrieved from the xmodel, so it's always set
+	 * fps and latency are the configurable params from the application
+	 */
+	if (rqos->gops > 0 && (rqos->fps > 0 ||  rqos->latency > 0))
+		return true;
+
+	return false;
+}
+
+static int set_dpm_level(struct solver_state *xrs, struct alloc_requests *req, u32 *dpm_level)
+{
+	struct solver_rgroup *rgp = &xrs->rgp;
+	struct cdo_parts *cdop = &req->cdo;
+	struct aie_qos *rqos = &req->rqos;
+	u32 freq, max_dpm_level, level;
+	struct solver_node *node;
+
+	max_dpm_level = xrs->cfg.clk_list.num_levels - 1;
+	/* If no QoS parameters are passed, set it to the max DPM level */
+	if (!is_valid_qos_dpm_params(rqos)) {
+		level = max_dpm_level;
+		goto set_dpm;
+	}
+
+	/* Find one CDO group that meet the GOPs requirement. */
+	for (level = 0; level < max_dpm_level; level++) {
+		freq = xrs->cfg.clk_list.cu_clk_list[level];
+		if (!qos_meet(xrs, rqos, cdop->qos_cap.opc * freq / 1000))
+			break;
+	}
+
+	/* set the dpm level which fits all the sessions */
+	list_for_each_entry(node, &rgp->node_list, list) {
+		if (node->dpm_level > level)
+			level = node->dpm_level;
+	}
+
+set_dpm:
+	*dpm_level = level;
+	return xrs->cfg.actions->set_dft_dpm_level(xrs->cfg.ddev, level);
+}
+
+static struct solver_node *rg_search_node(struct solver_rgroup *rgp, u64 rid)
+{
+	struct solver_node *node;
+
+	list_for_each_entry(node, &rgp->node_list, list) {
+		if (node->rid == rid)
+			return node;
+	}
+
+	return NULL;
+}
+
+static void remove_partition_node(struct solver_rgroup *rgp,
+				  struct partition_node *pt_node)
+{
+	pt_node->nshared--;
+	if (pt_node->nshared > 0)
+		return;
+
+	list_del(&pt_node->list);
+	rgp->npartition_node--;
+
+	bitmap_clear(rgp->resbit, pt_node->start_col, pt_node->ncols);
+	kfree(pt_node);
+}
+
+static void remove_solver_node(struct solver_rgroup *rgp,
+			       struct solver_node *node)
+{
+	list_del(&node->list);
+	rgp->nnode--;
+
+	if (node->pt_node)
+		remove_partition_node(rgp, node->pt_node);
+
+	kfree(node);
+}
+
+static int get_free_partition(struct solver_state *xrs,
+			      struct solver_node *snode,
+			      struct alloc_requests *req)
+{
+	struct partition_node *pt_node;
+	u32 ncols = req->cdo.ncols;
+	u32 col, i;
+
+	for (i = 0; i < snode->cols_len; i++) {
+		col = snode->start_cols[i];
+		if (find_next_bit(xrs->rgp.resbit, XRS_MAX_COL, col) >= col + ncols)
+			break;
+	}
+
+	if (i == snode->cols_len)
+		return -ENODEV;
+
+	pt_node = kzalloc(sizeof(*pt_node), GFP_KERNEL);
+	if (!pt_node)
+		return -ENOMEM;
+
+	pt_node->nshared = 1;
+	pt_node->start_col = col;
+	pt_node->ncols = ncols;
+
+	/*
+	 * Always set exclusive to false for now.
+	 */
+	pt_node->exclusive = false;
+
+	list_add_tail(&pt_node->list, &xrs->rgp.pt_node_list);
+	xrs->rgp.npartition_node++;
+	bitmap_set(xrs->rgp.resbit, pt_node->start_col, pt_node->ncols);
+
+	snode->pt_node = pt_node;
+
+	return 0;
+}
+
+static int allocate_partition(struct solver_state *xrs,
+			      struct solver_node *snode,
+			      struct alloc_requests *req)
+{
+	struct partition_node *pt_node, *rpt_node = NULL;
+	int idx, ret;
+
+	ret = get_free_partition(xrs, snode, req);
+	if (!ret)
+		return ret;
+
+	/* try to get a share-able partition */
+	list_for_each_entry(pt_node, &xrs->rgp.pt_node_list, list) {
+		if (pt_node->exclusive)
+			continue;
+
+		if (rpt_node && pt_node->nshared >= rpt_node->nshared)
+			continue;
+
+		for (idx = 0; idx < snode->cols_len; idx++) {
+			if (snode->start_cols[idx] != pt_node->start_col)
+				continue;
+
+			if (req->cdo.ncols != pt_node->ncols)
+				continue;
+
+			rpt_node = pt_node;
+			break;
+		}
+	}
+
+	if (!rpt_node)
+		return -ENODEV;
+
+	rpt_node->nshared++;
+	snode->pt_node = rpt_node;
+
+	return 0;
+}
+
+static struct solver_node *create_solver_node(struct solver_state *xrs,
+					      struct alloc_requests *req)
+{
+	struct cdo_parts *cdop = &req->cdo;
+	struct solver_node *node;
+	int ret;
+
+	node = kzalloc(struct_size(node, start_cols, cdop->cols_len), GFP_KERNEL);
+	if (!node)
+		return ERR_PTR(-ENOMEM);
+
+	node->rid = req->rid;
+	node->cols_len = cdop->cols_len;
+	memcpy(node->start_cols, cdop->start_cols, cdop->cols_len * sizeof(u32));
+
+	ret = allocate_partition(xrs, node, req);
+	if (ret)
+		goto free_node;
+
+	list_add_tail(&node->list, &xrs->rgp.node_list);
+	xrs->rgp.nnode++;
+	return node;
+
+free_node:
+	kfree(node);
+	return ERR_PTR(ret);
+}
+
+static void fill_load_action(struct solver_state *xrs,
+			     struct solver_node *snode,
+			     struct xrs_action_load *action)
+{
+	action->rid = snode->rid;
+	action->part.start_col = snode->pt_node->start_col;
+	action->part.ncols = snode->pt_node->ncols;
+}
+
+int xrs_allocate_resource(void *hdl, struct alloc_requests *req, void *cb_arg)
+{
+	struct xrs_action_load load_act;
+	struct solver_node *snode;
+	struct solver_state *xrs;
+	u32 dpm_level;
+	int ret;
+
+	xrs = (struct solver_state *)hdl;
+
+	ret = sanity_check(xrs, req);
+	if (ret) {
+		drm_err(xrs->cfg.ddev, "invalid request");
+		return ret;
+	}
+
+	if (rg_search_node(&xrs->rgp, req->rid)) {
+		drm_err(xrs->cfg.ddev, "rid %lld is in-use", req->rid);
+		return -EEXIST;
+	}
+
+	snode = create_solver_node(xrs, req);
+	if (IS_ERR(snode))
+		return PTR_ERR(snode);
+
+	fill_load_action(xrs, snode, &load_act);
+	ret = xrs->cfg.actions->load(cb_arg, &load_act);
+	if (ret)
+		goto free_node;
+
+	ret = set_dpm_level(xrs, req, &dpm_level);
+	if (ret)
+		goto free_node;
+
+	snode->dpm_level = dpm_level;
+	snode->cb_arg = cb_arg;
+
+	drm_dbg(xrs->cfg.ddev, "start col %d ncols %d\n",
+		snode->pt_node->start_col, snode->pt_node->ncols);
+
+	return 0;
+
+free_node:
+	remove_solver_node(&xrs->rgp, snode);
+
+	return ret;
+}
+
+int xrs_release_resource(void *hdl, u64 rid)
+{
+	struct solver_state *xrs = hdl;
+	struct solver_node *node;
+
+	node = rg_search_node(&xrs->rgp, rid);
+	if (!node) {
+		drm_err(xrs->cfg.ddev, "node not exist");
+		return -ENODEV;
+	}
+
+	xrs->cfg.actions->unload(node->cb_arg);
+	remove_solver_node(&xrs->rgp, node);
+
+	return 0;
+}
+
+void *xrsm_init(struct init_config *cfg)
+{
+	struct solver_rgroup *rgp;
+	struct solver_state *xrs;
+
+	xrs = drmm_kzalloc(cfg->ddev, sizeof(*xrs), GFP_KERNEL);
+	if (!xrs)
+		return NULL;
+
+	memcpy(&xrs->cfg, cfg, sizeof(*cfg));
+
+	rgp = &xrs->rgp;
+	INIT_LIST_HEAD(&rgp->node_list);
+	INIT_LIST_HEAD(&rgp->pt_node_list);
+
+	return xrs;
+}
diff --git a/drivers/accel/amdxdna/aie2_solver.h b/drivers/accel/amdxdna/aie2_solver.h
new file mode 100644
index 000000000000..a2e3c52229e9
--- /dev/null
+++ b/drivers/accel/amdxdna/aie2_solver.h
@@ -0,0 +1,155 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2023-2024, Advanced Micro Devices, Inc.
+ */
+
+#ifndef _AIE2_SOLVER_H
+#define _AIE2_SOLVER_H
+
+#define XRS_MAX_COL 128
+
+/*
+ * Structure used to describe a partition. A partition is column based
+ * allocation unit described by its start column and number of columns.
+ */
+struct aie_part {
+	u32	start_col;
+	u32	ncols;
+};
+
+/*
+ * The QoS capabilities of a given AIE partition.
+ */
+struct aie_qos_cap {
+	u32     opc;            /* operations per cycle */
+	u32     dma_bw;         /* DMA bandwidth */
+};
+
+/*
+ * QoS requirement of a resource allocation.
+ */
+struct aie_qos {
+	u32	gops;		/* Giga operations */
+	u32	fps;		/* Frames per second */
+	u32	dma_bw;		/* DMA bandwidth */
+	u32	latency;	/* Frame response latency */
+	u32	exec_time;	/* Frame execution time */
+	u32	priority;	/* Request priority */
+};
+
+/*
+ * Structure used to describe a relocatable CDO (Configuration Data Object).
+ */
+struct cdo_parts {
+	u32		   *start_cols;		/* Start column array */
+	u32		   cols_len;		/* Length of start column array */
+	u32		   ncols;		/* # of column */
+	struct aie_qos_cap qos_cap;		/* CDO QoS capabilities */
+};
+
+/*
+ * Structure used to describe a request to allocate.
+ */
+struct alloc_requests {
+	u64			rid;
+	struct cdo_parts	cdo;
+	struct aie_qos		rqos;		/* Requested QoS */
+};
+
+/*
+ * Load callback argument
+ */
+struct xrs_action_load {
+	u32                     rid;
+	struct aie_part         part;
+};
+
+/*
+ * Define the power level available
+ *
+ * POWER_LEVEL_MIN:
+ *     Lowest power level. Usually set when all actions are unloaded.
+ *
+ * POWER_LEVEL_n
+ *     Power levels 0 - n, is a step increase in system frequencies
+ */
+enum power_level {
+	POWER_LEVEL_MIN = 0x0,
+	POWER_LEVEL_0   = 0x1,
+	POWER_LEVEL_1   = 0x2,
+	POWER_LEVEL_2   = 0x3,
+	POWER_LEVEL_3   = 0x4,
+	POWER_LEVEL_4   = 0x5,
+	POWER_LEVEL_5   = 0x6,
+	POWER_LEVEL_6   = 0x7,
+	POWER_LEVEL_7   = 0x8,
+	POWER_LEVEL_NUM,
+};
+
+/*
+ * Structure used to describe the frequency table.
+ * Resource solver chooses the frequency from the table
+ * to meet the QOS requirements.
+ */
+struct clk_list_info {
+	u32        num_levels;                     /* available power levels */
+	u32        cu_clk_list[POWER_LEVEL_NUM];   /* available aie clock frequencies in Mhz*/
+};
+
+struct xrs_action_ops {
+	int (*load)(void *cb_arg, struct xrs_action_load *action);
+	int (*unload)(void *cb_arg);
+	int (*set_dft_dpm_level)(struct drm_device *ddev, u32 level);
+};
+
+/*
+ * Structure used to describe information for solver during initialization.
+ */
+struct init_config {
+	u32			total_col;
+	u32			sys_eff_factor; /* system efficiency factor */
+	u32			latency_adj;    /* latency adjustment in ms */
+	struct clk_list_info	clk_list;       /* List of frequencies available in system */
+	struct drm_device	*ddev;
+	struct xrs_action_ops	*actions;
+};
+
+/*
+ * xrsm_init() - Register resource solver. Resource solver client needs
+ *              to call this function to register itself.
+ *
+ * @cfg:	The system metrics for resource solver to use
+ *
+ * Return:	A resource solver handle
+ *
+ * Note: We should only create one handle per AIE array to be managed.
+ */
+void *xrsm_init(struct init_config *cfg);
+
+/*
+ * xrs_allocate_resource() - Request to allocate resources for a given context
+ *                           and a partition metadata. (See struct part_meta)
+ *
+ * @hdl:	Resource solver handle obtained from xrs_init()
+ * @req:	Input to the Resource solver including request id
+ *		and partition metadata.
+ * @cb_arg:	callback argument pointer
+ *
+ * Return:	0 when successful.
+ *		Or standard error number when failing
+ *
+ * Note:
+ *      There is no lock mechanism inside resource solver. So it is
+ *      the caller's responsibility to lock down XCLBINs and grab
+ *      necessary lock.
+ */
+int xrs_allocate_resource(void *hdl, struct alloc_requests *req, void *cb_arg);
+
+/*
+ * xrs_release_resource() - Request to free resources for a given context.
+ *
+ * @hdl:	Resource solver handle obtained from xrs_init()
+ * @rid:	The Request ID to identify the requesting context
+ */
+int xrs_release_resource(void *hdl, u64 rid);
+#endif /* _AIE2_SOLVER_H */
diff --git a/drivers/accel/amdxdna/amdxdna_ctx.c b/drivers/accel/amdxdna/amdxdna_ctx.c
new file mode 100644
index 000000000000..d17aef89a0ad
--- /dev/null
+++ b/drivers/accel/amdxdna/amdxdna_ctx.c
@@ -0,0 +1,572 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022-2024, Advanced Micro Devices, Inc.
+ */
+
+#include <drm/amdxdna_accel.h>
+#include <drm/drm_device.h>
+#include <drm/drm_drv.h>
+#include <drm/drm_file.h>
+#include <drm/drm_gem.h>
+#include <drm/drm_gem_shmem_helper.h>
+#include <drm/drm_print.h>
+#include <drm/gpu_scheduler.h>
+#include <linux/xarray.h>
+#include <trace/events/amdxdna.h>
+
+#include "amdxdna_ctx.h"
+#include "amdxdna_gem.h"
+#include "amdxdna_pci_drv.h"
+
+#define MAX_HWCTX_ID		255
+#define MAX_ARG_COUNT		4095
+
+struct amdxdna_fence {
+	struct dma_fence	base;
+	spinlock_t		lock; /* for base */
+	struct amdxdna_hwctx	*hwctx;
+};
+
+static const char *amdxdna_fence_get_driver_name(struct dma_fence *fence)
+{
+	return KBUILD_MODNAME;
+}
+
+static const char *amdxdna_fence_get_timeline_name(struct dma_fence *fence)
+{
+	struct amdxdna_fence *xdna_fence;
+
+	xdna_fence = container_of(fence, struct amdxdna_fence, base);
+
+	return xdna_fence->hwctx->name;
+}
+
+static const struct dma_fence_ops fence_ops = {
+	.get_driver_name = amdxdna_fence_get_driver_name,
+	.get_timeline_name = amdxdna_fence_get_timeline_name,
+};
+
+static struct dma_fence *amdxdna_fence_create(struct amdxdna_hwctx *hwctx)
+{
+	struct amdxdna_fence *fence;
+
+	fence = kzalloc(sizeof(*fence), GFP_KERNEL);
+	if (!fence)
+		return NULL;
+
+	fence->hwctx = hwctx;
+	spin_lock_init(&fence->lock);
+	dma_fence_init(&fence->base, &fence_ops, &fence->lock, hwctx->id, 0);
+	return &fence->base;
+}
+
+static void amdxdna_hwctx_destroy_rcu(struct amdxdna_hwctx *hwctx,
+				      struct srcu_struct *ss)
+{
+	struct amdxdna_dev *xdna = hwctx->client->xdna;
+
+	synchronize_srcu(ss);
+
+	/* At this point, user is not able to submit new commands */
+	xdna->dev_info->ops->hwctx_fini(hwctx);
+
+	kfree(hwctx->name);
+	kfree(hwctx);
+}
+
+int amdxdna_hwctx_walk(struct amdxdna_client *client, void *arg,
+		       int (*walk)(struct amdxdna_hwctx *hwctx, void *arg))
+{
+	struct amdxdna_hwctx *hwctx;
+	unsigned long hwctx_id;
+	int ret = 0, idx;
+
+	idx = srcu_read_lock(&client->hwctx_srcu);
+	amdxdna_for_each_hwctx(client, hwctx_id, hwctx) {
+		ret = walk(hwctx, arg);
+		if (ret)
+			break;
+	}
+	srcu_read_unlock(&client->hwctx_srcu, idx);
+
+	return ret;
+}
+
+void *amdxdna_cmd_get_payload(struct amdxdna_gem_obj *abo, u32 *size)
+{
+	struct amdxdna_cmd *cmd = abo->mem.kva;
+	u32 num_masks, count;
+
+	if (amdxdna_cmd_get_op(abo) == ERT_CMD_CHAIN)
+		num_masks = 0;
+	else
+		num_masks = 1 + FIELD_GET(AMDXDNA_CMD_EXTRA_CU_MASK, cmd->header);
+
+	if (size) {
+		count = FIELD_GET(AMDXDNA_CMD_COUNT, cmd->header);
+		if (unlikely(count <= num_masks)) {
+			*size = 0;
+			return NULL;
+		}
+		*size = (count - num_masks) * sizeof(u32);
+	}
+	return &cmd->data[num_masks];
+}
+
+u32 amdxdna_cmd_get_cu_idx(struct amdxdna_gem_obj *abo)
+{
+	struct amdxdna_cmd *cmd = abo->mem.kva;
+	u32 num_masks, i;
+	u32 *cu_mask;
+
+	if (amdxdna_cmd_get_op(abo) == ERT_CMD_CHAIN)
+		return INVALID_CU_IDX;
+
+	num_masks = 1 + FIELD_GET(AMDXDNA_CMD_EXTRA_CU_MASK, cmd->header);
+	cu_mask = cmd->data;
+	for (i = 0; i < num_masks; i++) {
+		if (cu_mask[i])
+			return ffs(cu_mask[i]) - 1;
+	}
+
+	return INVALID_CU_IDX;
+}
+
+/*
+ * This should be called in close() and remove(). DO NOT call in other syscalls.
+ * This guarantee that when hwctx and resources will be released, if user
+ * doesn't call amdxdna_drm_destroy_hwctx_ioctl.
+ */
+void amdxdna_hwctx_remove_all(struct amdxdna_client *client)
+{
+	struct amdxdna_hwctx *hwctx;
+	unsigned long hwctx_id;
+
+	amdxdna_for_each_hwctx(client, hwctx_id, hwctx) {
+		XDNA_DBG(client->xdna, "PID %d close HW context %d",
+			 client->pid, hwctx->id);
+		xa_erase(&client->hwctx_xa, hwctx->id);
+		amdxdna_hwctx_destroy_rcu(hwctx, &client->hwctx_srcu);
+	}
+}
+
+int amdxdna_drm_create_hwctx_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
+{
+	struct amdxdna_client *client = filp->driver_priv;
+	struct amdxdna_drm_create_hwctx *args = data;
+	struct amdxdna_dev *xdna = to_xdna_dev(dev);
+	struct amdxdna_hwctx *hwctx;
+	int ret, idx;
+
+	if (args->ext || args->ext_flags)
+		return -EINVAL;
+
+	hwctx = kzalloc(sizeof(*hwctx), GFP_KERNEL);
+	if (!hwctx)
+		return -ENOMEM;
+
+	if (copy_from_user(&hwctx->qos, u64_to_user_ptr(args->qos_p), sizeof(hwctx->qos))) {
+		XDNA_ERR(xdna, "Access QoS info failed");
+		kfree(hwctx);
+		return -EFAULT;
+	}
+
+	hwctx->client = client;
+	hwctx->fw_ctx_id = -1;
+	hwctx->num_tiles = args->num_tiles;
+	hwctx->mem_size = args->mem_size;
+	hwctx->max_opc = args->max_opc;
+
+	guard(mutex)(&xdna->dev_lock);
+
+	if (!drm_dev_enter(dev, &idx)) {
+		ret = -ENODEV;
+		goto free_hwctx;
+	}
+
+	ret = xdna->dev_info->ops->hwctx_init(hwctx);
+	if (ret) {
+		XDNA_ERR(xdna, "Init hwctx failed, ret %d", ret);
+		goto dev_exit;
+	}
+
+	hwctx->name = kasprintf(GFP_KERNEL, "hwctx.%d.%d", client->pid, hwctx->fw_ctx_id);
+	if (!hwctx->name) {
+		ret = -ENOMEM;
+		goto fini_hwctx;
+	}
+
+	ret = xa_alloc_cyclic(&client->hwctx_xa, &hwctx->id, hwctx,
+			      XA_LIMIT(AMDXDNA_INVALID_CTX_HANDLE + 1, MAX_HWCTX_ID),
+			      &client->next_hwctxid, GFP_KERNEL);
+	if (ret < 0) {
+		XDNA_ERR(xdna, "Allocate hwctx ID failed, ret %d", ret);
+		goto free_name;
+	}
+
+	args->handle = hwctx->id;
+	args->syncobj_handle = hwctx->syncobj_hdl;
+
+	atomic64_set(&hwctx->job_submit_cnt, 0);
+	atomic64_set(&hwctx->job_free_cnt, 0);
+	XDNA_DBG(xdna, "PID %d create HW context %d, ret %d", client->pid, args->handle, ret);
+	drm_dev_exit(idx);
+	return 0;
+
+free_name:
+	kfree(hwctx->name);
+fini_hwctx:
+	xdna->dev_info->ops->hwctx_fini(hwctx);
+dev_exit:
+	drm_dev_exit(idx);
+free_hwctx:
+	kfree(hwctx);
+	return ret;
+}
+
+int amdxdna_drm_destroy_hwctx_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
+{
+	struct amdxdna_client *client = filp->driver_priv;
+	struct amdxdna_drm_destroy_hwctx *args = data;
+	struct amdxdna_dev *xdna = to_xdna_dev(dev);
+	struct amdxdna_hwctx *hwctx;
+	int ret = 0, idx;
+
+	if (XDNA_MBZ_DBG(xdna, &args->pad, sizeof(args->pad)))
+		return -EINVAL;
+
+	if (!drm_dev_enter(dev, &idx))
+		return -ENODEV;
+
+	mutex_lock(&xdna->dev_lock);
+	hwctx = xa_erase(&client->hwctx_xa, args->handle);
+	if (!hwctx) {
+		ret = -EINVAL;
+		XDNA_DBG(xdna, "PID %d HW context %d not exist",
+			 client->pid, args->handle);
+		goto out;
+	}
+
+	/*
+	 * The pushed jobs are handled by DRM scheduler during destroy.
+	 * SRCU to synchronize with exec command ioctls.
+	 */
+	amdxdna_hwctx_destroy_rcu(hwctx, &client->hwctx_srcu);
+
+	XDNA_DBG(xdna, "PID %d destroyed HW context %d", client->pid, args->handle);
+out:
+	mutex_unlock(&xdna->dev_lock);
+	drm_dev_exit(idx);
+	return ret;
+}
+
+int amdxdna_drm_config_hwctx_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
+{
+	struct amdxdna_client *client = filp->driver_priv;
+	struct amdxdna_drm_config_hwctx *args = data;
+	struct amdxdna_dev *xdna = to_xdna_dev(dev);
+	struct amdxdna_hwctx *hwctx;
+	int ret, idx;
+	u32 buf_size;
+	void *buf;
+	u64 val;
+
+	if (XDNA_MBZ_DBG(xdna, &args->pad, sizeof(args->pad)))
+		return -EINVAL;
+
+	if (!xdna->dev_info->ops->hwctx_config)
+		return -EOPNOTSUPP;
+
+	val = args->param_val;
+	buf_size = args->param_val_size;
+
+	switch (args->param_type) {
+	case DRM_AMDXDNA_HWCTX_CONFIG_CU:
+		/* For those types that param_val is pointer */
+		if (buf_size > PAGE_SIZE) {
+			XDNA_ERR(xdna, "Config CU param buffer too large");
+			return -E2BIG;
+		}
+
+		/* Hwctx needs to keep buf */
+		buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
+		if (!buf)
+			return -ENOMEM;
+
+		if (copy_from_user(buf, u64_to_user_ptr(val), buf_size)) {
+			kfree(buf);
+			return -EFAULT;
+		}
+
+		break;
+	case DRM_AMDXDNA_HWCTX_ASSIGN_DBG_BUF:
+	case DRM_AMDXDNA_HWCTX_REMOVE_DBG_BUF:
+		/* For those types that param_val is a value */
+		buf = NULL;
+		buf_size = 0;
+		break;
+	default:
+		XDNA_DBG(xdna, "Unknown HW context config type %d", args->param_type);
+		return -EINVAL;
+	}
+
+	mutex_lock(&xdna->dev_lock);
+	idx = srcu_read_lock(&client->hwctx_srcu);
+	hwctx = xa_load(&client->hwctx_xa, args->handle);
+	if (!hwctx) {
+		XDNA_DBG(xdna, "PID %d failed to get hwctx %d", client->pid, args->handle);
+		ret = -EINVAL;
+		goto unlock_srcu;
+	}
+
+	ret = xdna->dev_info->ops->hwctx_config(hwctx, args->param_type, val, buf, buf_size);
+
+unlock_srcu:
+	srcu_read_unlock(&client->hwctx_srcu, idx);
+	mutex_unlock(&xdna->dev_lock);
+	kfree(buf);
+	return ret;
+}
+
+int amdxdna_hwctx_sync_debug_bo(struct amdxdna_client *client, u32 debug_bo_hdl)
+{
+	struct amdxdna_dev *xdna = client->xdna;
+	struct amdxdna_hwctx *hwctx;
+	struct amdxdna_gem_obj *abo;
+	struct drm_gem_object *gobj;
+	int ret, idx;
+
+	if (!xdna->dev_info->ops->hwctx_sync_debug_bo)
+		return -EOPNOTSUPP;
+
+	gobj = drm_gem_object_lookup(client->filp, debug_bo_hdl);
+	if (!gobj)
+		return -EINVAL;
+
+	abo = to_xdna_obj(gobj);
+	guard(mutex)(&xdna->dev_lock);
+	idx = srcu_read_lock(&client->hwctx_srcu);
+	hwctx = xa_load(&client->hwctx_xa, abo->assigned_hwctx);
+	if (!hwctx) {
+		ret = -EINVAL;
+		goto unlock_srcu;
+	}
+
+	ret = xdna->dev_info->ops->hwctx_sync_debug_bo(hwctx, debug_bo_hdl);
+
+unlock_srcu:
+	srcu_read_unlock(&client->hwctx_srcu, idx);
+	drm_gem_object_put(gobj);
+	return ret;
+}
+
+static void
+amdxdna_arg_bos_put(struct amdxdna_sched_job *job)
+{
+	int i;
+
+	for (i = 0; i < job->bo_cnt; i++) {
+		if (!job->bos[i])
+			break;
+		drm_gem_object_put(job->bos[i]);
+	}
+}
+
+static int
+amdxdna_arg_bos_lookup(struct amdxdna_client *client,
+		       struct amdxdna_sched_job *job,
+		       u32 *bo_hdls, u32 bo_cnt)
+{
+	struct drm_gem_object *gobj;
+	int i, ret;
+
+	job->bo_cnt = bo_cnt;
+	for (i = 0; i < job->bo_cnt; i++) {
+		struct amdxdna_gem_obj *abo;
+
+		gobj = drm_gem_object_lookup(client->filp, bo_hdls[i]);
+		if (!gobj) {
+			ret = -ENOENT;
+			goto put_shmem_bo;
+		}
+		abo = to_xdna_obj(gobj);
+
+		mutex_lock(&abo->lock);
+		if (abo->pinned) {
+			mutex_unlock(&abo->lock);
+			job->bos[i] = gobj;
+			continue;
+		}
+
+		ret = amdxdna_gem_pin_nolock(abo);
+		if (ret) {
+			mutex_unlock(&abo->lock);
+			drm_gem_object_put(gobj);
+			goto put_shmem_bo;
+		}
+		abo->pinned = true;
+		mutex_unlock(&abo->lock);
+
+		job->bos[i] = gobj;
+	}
+
+	return 0;
+
+put_shmem_bo:
+	amdxdna_arg_bos_put(job);
+	return ret;
+}
+
+void amdxdna_sched_job_cleanup(struct amdxdna_sched_job *job)
+{
+	trace_amdxdna_debug_point(job->hwctx->name, job->seq, "job release");
+	amdxdna_arg_bos_put(job);
+	amdxdna_gem_put_obj(job->cmd_bo);
+	dma_fence_put(job->fence);
+}
+
+int amdxdna_cmd_submit(struct amdxdna_client *client,
+		       struct amdxdna_drv_cmd *drv_cmd,
+		       u32 cmd_bo_hdl, u32 *arg_bo_hdls, u32 arg_bo_cnt,
+		       u32 hwctx_hdl, u64 *seq)
+{
+	struct amdxdna_dev *xdna = client->xdna;
+	struct amdxdna_sched_job *job;
+	struct amdxdna_hwctx *hwctx;
+	int ret, idx;
+
+	XDNA_DBG(xdna, "Command BO hdl %d, Arg BO count %d", cmd_bo_hdl, arg_bo_cnt);
+	job = kzalloc(struct_size(job, bos, arg_bo_cnt), GFP_KERNEL);
+	if (!job)
+		return -ENOMEM;
+
+	job->drv_cmd = drv_cmd;
+
+	if (cmd_bo_hdl != AMDXDNA_INVALID_BO_HANDLE) {
+		job->cmd_bo = amdxdna_gem_get_obj(client, cmd_bo_hdl, AMDXDNA_BO_CMD);
+		if (!job->cmd_bo) {
+			XDNA_ERR(xdna, "Failed to get cmd bo from %d", cmd_bo_hdl);
+			ret = -EINVAL;
+			goto free_job;
+		}
+	}
+
+	ret = amdxdna_arg_bos_lookup(client, job, arg_bo_hdls, arg_bo_cnt);
+	if (ret) {
+		XDNA_ERR(xdna, "Argument BOs lookup failed, ret %d", ret);
+		goto cmd_put;
+	}
+
+	idx = srcu_read_lock(&client->hwctx_srcu);
+	hwctx = xa_load(&client->hwctx_xa, hwctx_hdl);
+	if (!hwctx) {
+		XDNA_DBG(xdna, "PID %d failed to get hwctx %d",
+			 client->pid, hwctx_hdl);
+		ret = -EINVAL;
+		goto unlock_srcu;
+	}
+
+
+	job->hwctx = hwctx;
+	job->mm = current->mm;
+
+	job->fence = amdxdna_fence_create(hwctx);
+	if (!job->fence) {
+		XDNA_ERR(xdna, "Failed to create fence");
+		ret = -ENOMEM;
+		goto unlock_srcu;
+	}
+	kref_init(&job->refcnt);
+
+	ret = xdna->dev_info->ops->cmd_submit(hwctx, job, seq);
+	if (ret)
+		goto put_fence;
+
+	/*
+	 * The amdxdna_hwctx_destroy_rcu() will release hwctx and associated
+	 * resource after synchronize_srcu(). The submitted jobs should be
+	 * handled by the queue, for example DRM scheduler, in device layer.
+	 * For here we can unlock SRCU.
+	 */
+	srcu_read_unlock(&client->hwctx_srcu, idx);
+	trace_amdxdna_debug_point(hwctx->name, *seq, "job pushed");
+
+	return 0;
+
+put_fence:
+	dma_fence_put(job->fence);
+unlock_srcu:
+	srcu_read_unlock(&client->hwctx_srcu, idx);
+	amdxdna_arg_bos_put(job);
+cmd_put:
+	amdxdna_gem_put_obj(job->cmd_bo);
+free_job:
+	kfree(job);
+	return ret;
+}
+
+/*
+ * The submit command ioctl submits a command to firmware. One firmware command
+ * may contain multiple command BOs for processing as a whole.
+ * The command sequence number is returned which can be used for wait command ioctl.
+ */
+static int amdxdna_drm_submit_execbuf(struct amdxdna_client *client,
+				      struct amdxdna_drm_exec_cmd *args)
+{
+	struct amdxdna_dev *xdna = client->xdna;
+	u32 *arg_bo_hdls = NULL;
+	u32 cmd_bo_hdl;
+	int ret;
+
+	if (args->arg_count > MAX_ARG_COUNT) {
+		XDNA_ERR(xdna, "Invalid arg bo count %d", args->arg_count);
+		return -EINVAL;
+	}
+
+	/* Only support single command for now. */
+	if (args->cmd_count != 1) {
+		XDNA_ERR(xdna, "Invalid cmd bo count %d", args->cmd_count);
+		return -EINVAL;
+	}
+
+	cmd_bo_hdl = (u32)args->cmd_handles;
+	if (args->arg_count) {
+		arg_bo_hdls = kcalloc(args->arg_count, sizeof(u32), GFP_KERNEL);
+		if (!arg_bo_hdls)
+			return -ENOMEM;
+		ret = copy_from_user(arg_bo_hdls, u64_to_user_ptr(args->args),
+				     args->arg_count * sizeof(u32));
+		if (ret) {
+			ret = -EFAULT;
+			goto free_cmd_bo_hdls;
+		}
+	}
+
+	ret = amdxdna_cmd_submit(client, NULL, cmd_bo_hdl, arg_bo_hdls,
+				 args->arg_count, args->hwctx, &args->seq);
+	if (ret)
+		XDNA_DBG(xdna, "Submit cmds failed, ret %d", ret);
+
+free_cmd_bo_hdls:
+	kfree(arg_bo_hdls);
+	if (!ret)
+		XDNA_DBG(xdna, "Pushed cmd %lld to scheduler", args->seq);
+	return ret;
+}
+
+int amdxdna_drm_submit_cmd_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
+{
+	struct amdxdna_client *client = filp->driver_priv;
+	struct amdxdna_drm_exec_cmd *args = data;
+
+	if (args->ext || args->ext_flags)
+		return -EINVAL;
+
+	switch (args->type) {
+	case AMDXDNA_CMD_SUBMIT_EXEC_BUF:
+		return amdxdna_drm_submit_execbuf(client, args);
+	}
+
+	XDNA_ERR(client->xdna, "Invalid command type %d", args->type);
+	return -EINVAL;
+}
diff --git a/drivers/accel/amdxdna/amdxdna_ctx.h b/drivers/accel/amdxdna/amdxdna_ctx.h
new file mode 100644
index 000000000000..b6151244d64f
--- /dev/null
+++ b/drivers/accel/amdxdna/amdxdna_ctx.h
@@ -0,0 +1,194 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2022-2024, Advanced Micro Devices, Inc.
+ */
+
+#ifndef _AMDXDNA_CTX_H_
+#define _AMDXDNA_CTX_H_
+
+#include <linux/bitfield.h>
+
+#include "amdxdna_gem.h"
+
+struct amdxdna_hwctx_priv;
+
+enum ert_cmd_opcode {
+	ERT_START_CU = 0,
+	ERT_CMD_CHAIN = 19,
+	ERT_START_NPU = 20,
+	ERT_START_NPU_PREEMPT = 21,
+	ERT_START_NPU_PREEMPT_ELF = 22,
+	ERT_INVALID_CMD	= ~0U,
+};
+
+enum ert_cmd_state {
+	ERT_CMD_STATE_INVALID,
+	ERT_CMD_STATE_NEW,
+	ERT_CMD_STATE_QUEUED,
+	ERT_CMD_STATE_RUNNING,
+	ERT_CMD_STATE_COMPLETED,
+	ERT_CMD_STATE_ERROR,
+	ERT_CMD_STATE_ABORT,
+	ERT_CMD_STATE_SUBMITTED,
+	ERT_CMD_STATE_TIMEOUT,
+	ERT_CMD_STATE_NORESPONSE,
+};
+
+/*
+ * Interpretation of the beginning of data payload for ERT_START_NPU in
+ * amdxdna_cmd. The rest of the payload in amdxdna_cmd is regular kernel args.
+ */
+struct amdxdna_cmd_start_npu {
+	u64 buffer;       /* instruction buffer address */
+	u32 buffer_size;  /* size of buffer in bytes */
+	u32 prop_count;	  /* properties count */
+	u32 prop_args[];  /* properties and regular kernel arguments */
+};
+
+/*
+ * Interpretation of the beginning of data payload for ERT_CMD_CHAIN in
+ * amdxdna_cmd. The rest of the payload in amdxdna_cmd is cmd BO handles.
+ */
+struct amdxdna_cmd_chain {
+	u32 command_count;
+	u32 submit_index;
+	u32 error_index;
+	u32 reserved[3];
+	u64 data[] __counted_by(command_count);
+};
+
+/*
+ * Interpretation of the beginning of data payload for ERT_START_NPU_PREEMPT in
+ * amdxdna_cmd. The rest of the payload in amdxdna_cmd is regular kernel args.
+ */
+struct amdxdna_cmd_preempt_data {
+	u64 inst_buf;	    /* instruction buffer address */
+	u64 save_buf;	    /* save buffer address */
+	u64 restore_buf;    /* restore buffer address */
+	u32 inst_size;	    /* size of instruction buffer in bytes */
+	u32 save_size;	    /* size of save buffer in bytes */
+	u32 restore_size;   /* size of restore buffer in bytes */
+	u32 inst_prop_cnt;  /* properties count */
+	u32 prop_args[];    /* properties and regular kernel arguments */
+};
+
+/* Exec buffer command header format */
+#define AMDXDNA_CMD_STATE		GENMASK(3, 0)
+#define AMDXDNA_CMD_EXTRA_CU_MASK	GENMASK(11, 10)
+#define AMDXDNA_CMD_COUNT		GENMASK(22, 12)
+#define AMDXDNA_CMD_OPCODE		GENMASK(27, 23)
+struct amdxdna_cmd {
+	u32 header;
+	u32 data[];
+};
+
+#define INVALID_CU_IDX		(~0U)
+
+struct amdxdna_hwctx {
+	struct amdxdna_client		*client;
+	struct amdxdna_hwctx_priv	*priv;
+	char				*name;
+
+	u32				id;
+	u32				max_opc;
+	u32				num_tiles;
+	u32				mem_size;
+	u32				fw_ctx_id;
+	u32				col_list_len;
+	u32				*col_list;
+	u32				start_col;
+	u32				num_col;
+#define HWCTX_STAT_INIT  0
+#define HWCTX_STAT_READY 1
+#define HWCTX_STAT_STOP  2
+	u32				status;
+	u32				old_status;
+
+	struct amdxdna_qos_info		     qos;
+	struct amdxdna_hwctx_param_config_cu *cus;
+	u32				syncobj_hdl;
+
+	atomic64_t			job_submit_cnt;
+	atomic64_t			job_free_cnt ____cacheline_aligned_in_smp;
+};
+
+#define drm_job_to_xdna_job(j) \
+	container_of(j, struct amdxdna_sched_job, base)
+
+enum amdxdna_job_opcode {
+	SYNC_DEBUG_BO,
+	ATTACH_DEBUG_BO,
+	DETACH_DEBUG_BO,
+};
+
+struct amdxdna_drv_cmd {
+	enum amdxdna_job_opcode	opcode;
+	u32			result;
+};
+
+struct amdxdna_sched_job {
+	struct drm_sched_job	base;
+	struct kref		refcnt;
+	struct amdxdna_hwctx	*hwctx;
+	struct mm_struct	*mm;
+	/* The fence to notice DRM scheduler that job is done by hardware */
+	struct dma_fence	*fence;
+	/* user can wait on this fence */
+	struct dma_fence	*out_fence;
+	bool			job_done;
+	bool			job_timeout;
+	u64			seq;
+	struct amdxdna_drv_cmd	*drv_cmd;
+	struct amdxdna_gem_obj	*cmd_bo;
+	size_t			bo_cnt;
+	struct drm_gem_object	*bos[] __counted_by(bo_cnt);
+};
+
+static inline u32
+amdxdna_cmd_get_op(struct amdxdna_gem_obj *abo)
+{
+	struct amdxdna_cmd *cmd = abo->mem.kva;
+
+	return FIELD_GET(AMDXDNA_CMD_OPCODE, cmd->header);
+}
+
+static inline void
+amdxdna_cmd_set_state(struct amdxdna_gem_obj *abo, enum ert_cmd_state s)
+{
+	struct amdxdna_cmd *cmd = abo->mem.kva;
+
+	cmd->header &= ~AMDXDNA_CMD_STATE;
+	cmd->header |= FIELD_PREP(AMDXDNA_CMD_STATE, s);
+}
+
+static inline enum ert_cmd_state
+amdxdna_cmd_get_state(struct amdxdna_gem_obj *abo)
+{
+	struct amdxdna_cmd *cmd = abo->mem.kva;
+
+	return FIELD_GET(AMDXDNA_CMD_STATE, cmd->header);
+}
+
+void *amdxdna_cmd_get_payload(struct amdxdna_gem_obj *abo, u32 *size);
+u32 amdxdna_cmd_get_cu_idx(struct amdxdna_gem_obj *abo);
+
+void amdxdna_sched_job_cleanup(struct amdxdna_sched_job *job);
+void amdxdna_hwctx_remove_all(struct amdxdna_client *client);
+int amdxdna_hwctx_walk(struct amdxdna_client *client, void *arg,
+		       int (*walk)(struct amdxdna_hwctx *hwctx, void *arg));
+int amdxdna_hwctx_sync_debug_bo(struct amdxdna_client *client, u32 debug_bo_hdl);
+
+int amdxdna_cmd_submit(struct amdxdna_client *client,
+		       struct amdxdna_drv_cmd *drv_cmd, u32 cmd_bo_hdls,
+		       u32 *arg_bo_hdls, u32 arg_bo_cnt,
+		       u32 hwctx_hdl, u64 *seq);
+
+int amdxdna_cmd_wait(struct amdxdna_client *client, u32 hwctx_hdl,
+		     u64 seq, u32 timeout);
+
+int amdxdna_drm_create_hwctx_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
+int amdxdna_drm_config_hwctx_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
+int amdxdna_drm_destroy_hwctx_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
+int amdxdna_drm_submit_cmd_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
+
+#endif /* _AMDXDNA_CTX_H_ */
diff --git a/drivers/accel/amdxdna/amdxdna_error.h b/drivers/accel/amdxdna/amdxdna_error.h
new file mode 100644
index 000000000000..c51de86ec12b
--- /dev/null
+++ b/drivers/accel/amdxdna/amdxdna_error.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2025, Advanced Micro Devices, Inc.
+ */
+
+#ifndef _AMDXDNA_ERROR_H_
+#define _AMDXDNA_ERROR_H_
+
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+
+#define AMDXDNA_ERR_DRV_AIE		4
+#define AMDXDNA_ERR_SEV_CRITICAL	3
+#define AMDXDNA_ERR_CLASS_AIE		2
+
+#define AMDXDNA_ERR_NUM_MASK		GENMASK_U64(15, 0)
+#define AMDXDNA_ERR_DRV_MASK		GENMASK_U64(23, 16)
+#define AMDXDNA_ERR_SEV_MASK		GENMASK_U64(31, 24)
+#define AMDXDNA_ERR_MOD_MASK		GENMASK_U64(39, 32)
+#define AMDXDNA_ERR_CLASS_MASK		GENMASK_U64(47, 40)
+
+enum amdxdna_error_num {
+	AMDXDNA_ERROR_NUM_AIE_SATURATION = 3,
+	AMDXDNA_ERROR_NUM_AIE_FP,
+	AMDXDNA_ERROR_NUM_AIE_STREAM,
+	AMDXDNA_ERROR_NUM_AIE_ACCESS,
+	AMDXDNA_ERROR_NUM_AIE_BUS,
+	AMDXDNA_ERROR_NUM_AIE_INSTRUCTION,
+	AMDXDNA_ERROR_NUM_AIE_ECC,
+	AMDXDNA_ERROR_NUM_AIE_LOCK,
+	AMDXDNA_ERROR_NUM_AIE_DMA,
+	AMDXDNA_ERROR_NUM_AIE_MEM_PARITY,
+	AMDXDNA_ERROR_NUM_UNKNOWN = 15,
+};
+
+enum amdxdna_error_module {
+	AMDXDNA_ERROR_MODULE_AIE_CORE = 3,
+	AMDXDNA_ERROR_MODULE_AIE_MEMORY,
+	AMDXDNA_ERROR_MODULE_AIE_SHIM,
+	AMDXDNA_ERROR_MODULE_AIE_NOC,
+	AMDXDNA_ERROR_MODULE_AIE_PL,
+	AMDXDNA_ERROR_MODULE_UNKNOWN = 8,
+};
+
+#define AMDXDNA_ERROR_ENCODE(err_num, err_mod)				\
+	(FIELD_PREP(AMDXDNA_ERR_NUM_MASK, err_num) |			\
+	 FIELD_PREP_CONST(AMDXDNA_ERR_DRV_MASK, AMDXDNA_ERR_DRV_AIE) |	\
+	 FIELD_PREP_CONST(AMDXDNA_ERR_SEV_MASK, AMDXDNA_ERR_SEV_CRITICAL) | \
+	 FIELD_PREP(AMDXDNA_ERR_MOD_MASK, err_mod) |			\
+	 FIELD_PREP_CONST(AMDXDNA_ERR_CLASS_MASK, AMDXDNA_ERR_CLASS_AIE))
+
+#define AMDXDNA_EXTRA_ERR_COL_MASK	GENMASK_U64(7, 0)
+#define AMDXDNA_EXTRA_ERR_ROW_MASK	GENMASK_U64(15, 8)
+
+#define AMDXDNA_EXTRA_ERR_ENCODE(row, col)				\
+	(FIELD_PREP(AMDXDNA_EXTRA_ERR_COL_MASK, col) |			\
+	 FIELD_PREP(AMDXDNA_EXTRA_ERR_ROW_MASK, row))
+
+#endif /* _AMDXDNA_ERROR_H_ */
diff --git a/drivers/accel/amdxdna/amdxdna_gem.c b/drivers/accel/amdxdna/amdxdna_gem.c
new file mode 100644
index 000000000000..dfa916eeb2d9
--- /dev/null
+++ b/drivers/accel/amdxdna/amdxdna_gem.c
@@ -0,0 +1,972 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024, Advanced Micro Devices, Inc.
+ */
+
+#include <drm/amdxdna_accel.h>
+#include <drm/drm_cache.h>
+#include <drm/drm_device.h>
+#include <drm/drm_gem.h>
+#include <drm/drm_gem_shmem_helper.h>
+#include <drm/drm_print.h>
+#include <drm/gpu_scheduler.h>
+#include <linux/dma-buf.h>
+#include <linux/dma-direct.h>
+#include <linux/iosys-map.h>
+#include <linux/pagemap.h>
+#include <linux/vmalloc.h>
+
+#include "amdxdna_ctx.h"
+#include "amdxdna_gem.h"
+#include "amdxdna_pci_drv.h"
+#include "amdxdna_ubuf.h"
+
+#define XDNA_MAX_CMD_BO_SIZE	SZ_32K
+
+MODULE_IMPORT_NS("DMA_BUF");
+
+static int
+amdxdna_gem_heap_alloc(struct amdxdna_gem_obj *abo)
+{
+	struct amdxdna_client *client = abo->client;
+	struct amdxdna_dev *xdna = client->xdna;
+	struct amdxdna_mem *mem = &abo->mem;
+	struct amdxdna_gem_obj *heap;
+	u64 offset;
+	u32 align;
+	int ret;
+
+	mutex_lock(&client->mm_lock);
+
+	heap = client->dev_heap;
+	if (!heap) {
+		ret = -EINVAL;
+		goto unlock_out;
+	}
+
+	if (heap->mem.userptr == AMDXDNA_INVALID_ADDR) {
+		XDNA_ERR(xdna, "Invalid dev heap userptr");
+		ret = -EINVAL;
+		goto unlock_out;
+	}
+
+	if (mem->size == 0 || mem->size > heap->mem.size) {
+		XDNA_ERR(xdna, "Invalid dev bo size 0x%lx, limit 0x%lx",
+			 mem->size, heap->mem.size);
+		ret = -EINVAL;
+		goto unlock_out;
+	}
+
+	align = 1 << max(PAGE_SHIFT, xdna->dev_info->dev_mem_buf_shift);
+	ret = drm_mm_insert_node_generic(&heap->mm, &abo->mm_node,
+					 mem->size, align,
+					 0, DRM_MM_INSERT_BEST);
+	if (ret) {
+		XDNA_ERR(xdna, "Failed to alloc dev bo memory, ret %d", ret);
+		goto unlock_out;
+	}
+
+	mem->dev_addr = abo->mm_node.start;
+	offset = mem->dev_addr - heap->mem.dev_addr;
+	mem->userptr = heap->mem.userptr + offset;
+	mem->kva = heap->mem.kva + offset;
+
+	drm_gem_object_get(to_gobj(heap));
+
+unlock_out:
+	mutex_unlock(&client->mm_lock);
+
+	return ret;
+}
+
+static void
+amdxdna_gem_destroy_obj(struct amdxdna_gem_obj *abo)
+{
+	mutex_destroy(&abo->lock);
+	kfree(abo);
+}
+
+static void
+amdxdna_gem_heap_free(struct amdxdna_gem_obj *abo)
+{
+	struct amdxdna_gem_obj *heap;
+
+	mutex_lock(&abo->client->mm_lock);
+
+	drm_mm_remove_node(&abo->mm_node);
+
+	heap = abo->client->dev_heap;
+	drm_gem_object_put(to_gobj(heap));
+
+	mutex_unlock(&abo->client->mm_lock);
+}
+
+static bool amdxdna_hmm_invalidate(struct mmu_interval_notifier *mni,
+				   const struct mmu_notifier_range *range,
+				   unsigned long cur_seq)
+{
+	struct amdxdna_umap *mapp = container_of(mni, struct amdxdna_umap, notifier);
+	struct amdxdna_gem_obj *abo = mapp->abo;
+	struct amdxdna_dev *xdna;
+
+	xdna = to_xdna_dev(to_gobj(abo)->dev);
+	XDNA_DBG(xdna, "Invalidating range 0x%lx, 0x%lx, type %d",
+		 mapp->vma->vm_start, mapp->vma->vm_end, abo->type);
+
+	if (!mmu_notifier_range_blockable(range))
+		return false;
+
+	down_write(&xdna->notifier_lock);
+	abo->mem.map_invalid = true;
+	mapp->invalid = true;
+	mmu_interval_set_seq(&mapp->notifier, cur_seq);
+	up_write(&xdna->notifier_lock);
+
+	xdna->dev_info->ops->hmm_invalidate(abo, cur_seq);
+
+	if (range->event == MMU_NOTIFY_UNMAP) {
+		down_write(&xdna->notifier_lock);
+		if (!mapp->unmapped) {
+			queue_work(xdna->notifier_wq, &mapp->hmm_unreg_work);
+			mapp->unmapped = true;
+		}
+		up_write(&xdna->notifier_lock);
+	}
+
+	return true;
+}
+
+static const struct mmu_interval_notifier_ops amdxdna_hmm_ops = {
+	.invalidate = amdxdna_hmm_invalidate,
+};
+
+static void amdxdna_hmm_unregister(struct amdxdna_gem_obj *abo,
+				   struct vm_area_struct *vma)
+{
+	struct amdxdna_dev *xdna = to_xdna_dev(to_gobj(abo)->dev);
+	struct amdxdna_umap *mapp;
+
+	down_read(&xdna->notifier_lock);
+	list_for_each_entry(mapp, &abo->mem.umap_list, node) {
+		if (!vma || mapp->vma == vma) {
+			if (!mapp->unmapped) {
+				queue_work(xdna->notifier_wq, &mapp->hmm_unreg_work);
+				mapp->unmapped = true;
+			}
+			if (vma)
+				break;
+		}
+	}
+	up_read(&xdna->notifier_lock);
+}
+
+static void amdxdna_umap_release(struct kref *ref)
+{
+	struct amdxdna_umap *mapp = container_of(ref, struct amdxdna_umap, refcnt);
+	struct vm_area_struct *vma = mapp->vma;
+	struct amdxdna_dev *xdna;
+
+	mmu_interval_notifier_remove(&mapp->notifier);
+	if (is_import_bo(mapp->abo) && vma->vm_file && vma->vm_file->f_mapping)
+		mapping_clear_unevictable(vma->vm_file->f_mapping);
+
+	xdna = to_xdna_dev(to_gobj(mapp->abo)->dev);
+	down_write(&xdna->notifier_lock);
+	list_del(&mapp->node);
+	up_write(&xdna->notifier_lock);
+
+	kvfree(mapp->range.hmm_pfns);
+	kfree(mapp);
+}
+
+void amdxdna_umap_put(struct amdxdna_umap *mapp)
+{
+	kref_put(&mapp->refcnt, amdxdna_umap_release);
+}
+
+static void amdxdna_hmm_unreg_work(struct work_struct *work)
+{
+	struct amdxdna_umap *mapp = container_of(work, struct amdxdna_umap,
+						 hmm_unreg_work);
+
+	amdxdna_umap_put(mapp);
+}
+
+static int amdxdna_hmm_register(struct amdxdna_gem_obj *abo,
+				struct vm_area_struct *vma)
+{
+	struct amdxdna_dev *xdna = to_xdna_dev(to_gobj(abo)->dev);
+	unsigned long len = vma->vm_end - vma->vm_start;
+	unsigned long addr = vma->vm_start;
+	struct amdxdna_umap *mapp;
+	u32 nr_pages;
+	int ret;
+
+	if (!xdna->dev_info->ops->hmm_invalidate)
+		return 0;
+
+	mapp = kzalloc(sizeof(*mapp), GFP_KERNEL);
+	if (!mapp)
+		return -ENOMEM;
+
+	nr_pages = (PAGE_ALIGN(addr + len) - (addr & PAGE_MASK)) >> PAGE_SHIFT;
+	mapp->range.hmm_pfns = kvcalloc(nr_pages, sizeof(*mapp->range.hmm_pfns),
+					GFP_KERNEL);
+	if (!mapp->range.hmm_pfns) {
+		ret = -ENOMEM;
+		goto free_map;
+	}
+
+	ret = mmu_interval_notifier_insert_locked(&mapp->notifier,
+						  current->mm,
+						  addr,
+						  len,
+						  &amdxdna_hmm_ops);
+	if (ret) {
+		XDNA_ERR(xdna, "Insert mmu notifier failed, ret %d", ret);
+		goto free_pfns;
+	}
+
+	mapp->range.notifier = &mapp->notifier;
+	mapp->range.start = vma->vm_start;
+	mapp->range.end = vma->vm_end;
+	mapp->range.default_flags = HMM_PFN_REQ_FAULT;
+	mapp->vma = vma;
+	mapp->abo = abo;
+	kref_init(&mapp->refcnt);
+
+	if (abo->mem.userptr == AMDXDNA_INVALID_ADDR)
+		abo->mem.userptr = addr;
+	INIT_WORK(&mapp->hmm_unreg_work, amdxdna_hmm_unreg_work);
+	if (is_import_bo(abo) && vma->vm_file && vma->vm_file->f_mapping)
+		mapping_set_unevictable(vma->vm_file->f_mapping);
+
+	down_write(&xdna->notifier_lock);
+	list_add_tail(&mapp->node, &abo->mem.umap_list);
+	up_write(&xdna->notifier_lock);
+
+	return 0;
+
+free_pfns:
+	kvfree(mapp->range.hmm_pfns);
+free_map:
+	kfree(mapp);
+	return ret;
+}
+
+static void amdxdna_gem_dev_obj_free(struct drm_gem_object *gobj)
+{
+	struct amdxdna_dev *xdna = to_xdna_dev(gobj->dev);
+	struct amdxdna_gem_obj *abo = to_xdna_obj(gobj);
+
+	XDNA_DBG(xdna, "BO type %d xdna_addr 0x%llx", abo->type, abo->mem.dev_addr);
+	if (abo->pinned)
+		amdxdna_gem_unpin(abo);
+
+	amdxdna_gem_heap_free(abo);
+	drm_gem_object_release(gobj);
+	amdxdna_gem_destroy_obj(abo);
+}
+
+static int amdxdna_insert_pages(struct amdxdna_gem_obj *abo,
+				struct vm_area_struct *vma)
+{
+	struct amdxdna_dev *xdna = to_xdna_dev(to_gobj(abo)->dev);
+	unsigned long num_pages = vma_pages(vma);
+	unsigned long offset = 0;
+	int ret;
+
+	if (!is_import_bo(abo)) {
+		ret = drm_gem_shmem_mmap(&abo->base, vma);
+		if (ret) {
+			XDNA_ERR(xdna, "Failed shmem mmap %d", ret);
+			return ret;
+		}
+
+		/* The buffer is based on memory pages. Fix the flag. */
+		vm_flags_mod(vma, VM_MIXEDMAP, VM_PFNMAP);
+		ret = vm_insert_pages(vma, vma->vm_start, abo->base.pages,
+				      &num_pages);
+		if (ret) {
+			XDNA_ERR(xdna, "Failed insert pages %d", ret);
+			vma->vm_ops->close(vma);
+			return ret;
+		}
+
+		return 0;
+	}
+
+	vma->vm_private_data = NULL;
+	vma->vm_ops = NULL;
+	ret = dma_buf_mmap(abo->dma_buf, vma, 0);
+	if (ret) {
+		XDNA_ERR(xdna, "Failed to mmap dma buf %d", ret);
+		return ret;
+	}
+
+	do {
+		vm_fault_t fault_ret;
+
+		fault_ret = handle_mm_fault(vma, vma->vm_start + offset,
+					    FAULT_FLAG_WRITE, NULL);
+		if (fault_ret & VM_FAULT_ERROR) {
+			vma->vm_ops->close(vma);
+			XDNA_ERR(xdna, "Fault in page failed");
+			return -EFAULT;
+		}
+
+		offset += PAGE_SIZE;
+	} while (--num_pages);
+
+	/* Drop the reference drm_gem_mmap_obj() acquired.*/
+	drm_gem_object_put(to_gobj(abo));
+
+	return 0;
+}
+
+static int amdxdna_gem_obj_mmap(struct drm_gem_object *gobj,
+				struct vm_area_struct *vma)
+{
+	struct amdxdna_dev *xdna = to_xdna_dev(gobj->dev);
+	struct amdxdna_gem_obj *abo = to_xdna_obj(gobj);
+	int ret;
+
+	ret = amdxdna_hmm_register(abo, vma);
+	if (ret)
+		return ret;
+
+	ret = amdxdna_insert_pages(abo, vma);
+	if (ret) {
+		XDNA_ERR(xdna, "Failed insert pages, ret %d", ret);
+		goto hmm_unreg;
+	}
+
+	XDNA_DBG(xdna, "BO map_offset 0x%llx type %d userptr 0x%lx size 0x%lx",
+		 drm_vma_node_offset_addr(&gobj->vma_node), abo->type,
+		 vma->vm_start, gobj->size);
+	return 0;
+
+hmm_unreg:
+	amdxdna_hmm_unregister(abo, vma);
+	return ret;
+}
+
+static int amdxdna_gem_dmabuf_mmap(struct dma_buf *dma_buf, struct vm_area_struct *vma)
+{
+	struct drm_gem_object *gobj = dma_buf->priv;
+	struct amdxdna_gem_obj *abo = to_xdna_obj(gobj);
+	unsigned long num_pages = vma_pages(vma);
+	int ret;
+
+	vma->vm_ops = &drm_gem_shmem_vm_ops;
+	vma->vm_private_data = gobj;
+
+	drm_gem_object_get(gobj);
+	ret = drm_gem_shmem_mmap(&abo->base, vma);
+	if (ret)
+		goto put_obj;
+
+	/* The buffer is based on memory pages. Fix the flag. */
+	vm_flags_mod(vma, VM_MIXEDMAP, VM_PFNMAP);
+	ret = vm_insert_pages(vma, vma->vm_start, abo->base.pages,
+			      &num_pages);
+	if (ret)
+		goto close_vma;
+
+	return 0;
+
+close_vma:
+	vma->vm_ops->close(vma);
+put_obj:
+	drm_gem_object_put(gobj);
+	return ret;
+}
+
+static const struct dma_buf_ops amdxdna_dmabuf_ops = {
+	.attach = drm_gem_map_attach,
+	.detach = drm_gem_map_detach,
+	.map_dma_buf = drm_gem_map_dma_buf,
+	.unmap_dma_buf = drm_gem_unmap_dma_buf,
+	.release = drm_gem_dmabuf_release,
+	.mmap = amdxdna_gem_dmabuf_mmap,
+	.vmap = drm_gem_dmabuf_vmap,
+	.vunmap = drm_gem_dmabuf_vunmap,
+};
+
+static int amdxdna_gem_obj_vmap(struct amdxdna_gem_obj *abo, void **vaddr)
+{
+	struct iosys_map map = IOSYS_MAP_INIT_VADDR(NULL);
+	int ret;
+
+	if (is_import_bo(abo))
+		ret = dma_buf_vmap_unlocked(abo->dma_buf, &map);
+	else
+		ret = drm_gem_vmap(to_gobj(abo), &map);
+
+	*vaddr = map.vaddr;
+	return ret;
+}
+
+static void amdxdna_gem_obj_vunmap(struct amdxdna_gem_obj *abo)
+{
+	struct iosys_map map;
+
+	if (!abo->mem.kva)
+		return;
+
+	iosys_map_set_vaddr(&map, abo->mem.kva);
+
+	if (is_import_bo(abo))
+		dma_buf_vunmap_unlocked(abo->dma_buf, &map);
+	else
+		drm_gem_vunmap(to_gobj(abo), &map);
+}
+
+static struct dma_buf *amdxdna_gem_prime_export(struct drm_gem_object *gobj, int flags)
+{
+	struct amdxdna_gem_obj *abo = to_xdna_obj(gobj);
+	DEFINE_DMA_BUF_EXPORT_INFO(exp_info);
+
+	if (abo->dma_buf) {
+		get_dma_buf(abo->dma_buf);
+		return abo->dma_buf;
+	}
+
+	exp_info.ops = &amdxdna_dmabuf_ops;
+	exp_info.size = gobj->size;
+	exp_info.flags = flags;
+	exp_info.priv = gobj;
+	exp_info.resv = gobj->resv;
+
+	return drm_gem_dmabuf_export(gobj->dev, &exp_info);
+}
+
+static void amdxdna_imported_obj_free(struct amdxdna_gem_obj *abo)
+{
+	dma_buf_unmap_attachment_unlocked(abo->attach, abo->base.sgt, DMA_BIDIRECTIONAL);
+	dma_buf_detach(abo->dma_buf, abo->attach);
+	dma_buf_put(abo->dma_buf);
+	drm_gem_object_release(to_gobj(abo));
+	kfree(abo);
+}
+
+static void amdxdna_gem_obj_free(struct drm_gem_object *gobj)
+{
+	struct amdxdna_dev *xdna = to_xdna_dev(gobj->dev);
+	struct amdxdna_gem_obj *abo = to_xdna_obj(gobj);
+
+	XDNA_DBG(xdna, "BO type %d xdna_addr 0x%llx", abo->type, abo->mem.dev_addr);
+
+	amdxdna_hmm_unregister(abo, NULL);
+	flush_workqueue(xdna->notifier_wq);
+
+	if (abo->pinned)
+		amdxdna_gem_unpin(abo);
+
+	if (abo->type == AMDXDNA_BO_DEV_HEAP)
+		drm_mm_takedown(&abo->mm);
+
+	amdxdna_gem_obj_vunmap(abo);
+	mutex_destroy(&abo->lock);
+
+	if (is_import_bo(abo)) {
+		amdxdna_imported_obj_free(abo);
+		return;
+	}
+
+	drm_gem_shmem_free(&abo->base);
+}
+
+static const struct drm_gem_object_funcs amdxdna_gem_dev_obj_funcs = {
+	.free = amdxdna_gem_dev_obj_free,
+};
+
+static const struct drm_gem_object_funcs amdxdna_gem_shmem_funcs = {
+	.free = amdxdna_gem_obj_free,
+	.print_info = drm_gem_shmem_object_print_info,
+	.pin = drm_gem_shmem_object_pin,
+	.unpin = drm_gem_shmem_object_unpin,
+	.get_sg_table = drm_gem_shmem_object_get_sg_table,
+	.vmap = drm_gem_shmem_object_vmap,
+	.vunmap = drm_gem_shmem_object_vunmap,
+	.mmap = amdxdna_gem_obj_mmap,
+	.vm_ops = &drm_gem_shmem_vm_ops,
+	.export = amdxdna_gem_prime_export,
+};
+
+static struct amdxdna_gem_obj *
+amdxdna_gem_create_obj(struct drm_device *dev, size_t size)
+{
+	struct amdxdna_gem_obj *abo;
+
+	abo = kzalloc(sizeof(*abo), GFP_KERNEL);
+	if (!abo)
+		return ERR_PTR(-ENOMEM);
+
+	abo->pinned = false;
+	abo->assigned_hwctx = AMDXDNA_INVALID_CTX_HANDLE;
+	mutex_init(&abo->lock);
+
+	abo->mem.userptr = AMDXDNA_INVALID_ADDR;
+	abo->mem.dev_addr = AMDXDNA_INVALID_ADDR;
+	abo->mem.size = size;
+	INIT_LIST_HEAD(&abo->mem.umap_list);
+
+	return abo;
+}
+
+/* For drm_driver->gem_create_object callback */
+struct drm_gem_object *
+amdxdna_gem_create_object_cb(struct drm_device *dev, size_t size)
+{
+	struct amdxdna_gem_obj *abo;
+
+	abo = amdxdna_gem_create_obj(dev, size);
+	if (IS_ERR(abo))
+		return ERR_CAST(abo);
+
+	to_gobj(abo)->funcs = &amdxdna_gem_shmem_funcs;
+
+	return to_gobj(abo);
+}
+
+static struct amdxdna_gem_obj *
+amdxdna_gem_create_shmem_object(struct drm_device *dev, size_t size)
+{
+	struct drm_gem_shmem_object *shmem = drm_gem_shmem_create(dev, size);
+
+	if (IS_ERR(shmem))
+		return ERR_CAST(shmem);
+
+	shmem->map_wc = false;
+	return to_xdna_obj(&shmem->base);
+}
+
+static struct amdxdna_gem_obj *
+amdxdna_gem_create_ubuf_object(struct drm_device *dev, struct amdxdna_drm_create_bo *args)
+{
+	struct amdxdna_dev *xdna = to_xdna_dev(dev);
+	enum amdxdna_ubuf_flag flags = 0;
+	struct amdxdna_drm_va_tbl va_tbl;
+	struct drm_gem_object *gobj;
+	struct dma_buf *dma_buf;
+
+	if (copy_from_user(&va_tbl, u64_to_user_ptr(args->vaddr), sizeof(va_tbl))) {
+		XDNA_DBG(xdna, "Access va table failed");
+		return ERR_PTR(-EINVAL);
+	}
+
+	if (va_tbl.num_entries) {
+		if (args->type == AMDXDNA_BO_CMD)
+			flags |= AMDXDNA_UBUF_FLAG_MAP_DMA;
+
+		dma_buf = amdxdna_get_ubuf(dev, flags, va_tbl.num_entries,
+					   u64_to_user_ptr(args->vaddr + sizeof(va_tbl)));
+	} else {
+		dma_buf = dma_buf_get(va_tbl.dmabuf_fd);
+	}
+
+	if (IS_ERR(dma_buf))
+		return ERR_CAST(dma_buf);
+
+	gobj = amdxdna_gem_prime_import(dev, dma_buf);
+	if (IS_ERR(gobj)) {
+		dma_buf_put(dma_buf);
+		return ERR_CAST(gobj);
+	}
+
+	dma_buf_put(dma_buf);
+
+	return to_xdna_obj(gobj);
+}
+
+static struct amdxdna_gem_obj *
+amdxdna_gem_create_object(struct drm_device *dev,
+			  struct amdxdna_drm_create_bo *args)
+{
+	size_t aligned_sz = PAGE_ALIGN(args->size);
+
+	if (args->vaddr)
+		return amdxdna_gem_create_ubuf_object(dev, args);
+
+	return amdxdna_gem_create_shmem_object(dev, aligned_sz);
+}
+
+struct drm_gem_object *
+amdxdna_gem_prime_import(struct drm_device *dev, struct dma_buf *dma_buf)
+{
+	struct dma_buf_attachment *attach;
+	struct amdxdna_gem_obj *abo;
+	struct drm_gem_object *gobj;
+	struct sg_table *sgt;
+	int ret;
+
+	get_dma_buf(dma_buf);
+
+	attach = dma_buf_attach(dma_buf, dev->dev);
+	if (IS_ERR(attach)) {
+		ret = PTR_ERR(attach);
+		goto put_buf;
+	}
+
+	sgt = dma_buf_map_attachment_unlocked(attach, DMA_BIDIRECTIONAL);
+	if (IS_ERR(sgt)) {
+		ret = PTR_ERR(sgt);
+		goto fail_detach;
+	}
+
+	gobj = drm_gem_shmem_prime_import_sg_table(dev, attach, sgt);
+	if (IS_ERR(gobj)) {
+		ret = PTR_ERR(gobj);
+		goto fail_unmap;
+	}
+
+	abo = to_xdna_obj(gobj);
+	abo->attach = attach;
+	abo->dma_buf = dma_buf;
+
+	return gobj;
+
+fail_unmap:
+	dma_buf_unmap_attachment_unlocked(attach, sgt, DMA_BIDIRECTIONAL);
+fail_detach:
+	dma_buf_detach(dma_buf, attach);
+put_buf:
+	dma_buf_put(dma_buf);
+
+	return ERR_PTR(ret);
+}
+
+static struct amdxdna_gem_obj *
+amdxdna_drm_alloc_shmem(struct drm_device *dev,
+			struct amdxdna_drm_create_bo *args,
+			struct drm_file *filp)
+{
+	struct amdxdna_client *client = filp->driver_priv;
+	struct amdxdna_gem_obj *abo;
+
+	abo = amdxdna_gem_create_object(dev, args);
+	if (IS_ERR(abo))
+		return ERR_CAST(abo);
+
+	abo->client = client;
+	abo->type = AMDXDNA_BO_SHMEM;
+
+	return abo;
+}
+
+static struct amdxdna_gem_obj *
+amdxdna_drm_create_dev_heap(struct drm_device *dev,
+			    struct amdxdna_drm_create_bo *args,
+			    struct drm_file *filp)
+{
+	struct amdxdna_client *client = filp->driver_priv;
+	struct amdxdna_dev *xdna = to_xdna_dev(dev);
+	struct amdxdna_gem_obj *abo;
+	int ret;
+
+	if (args->size > xdna->dev_info->dev_mem_size) {
+		XDNA_DBG(xdna, "Invalid dev heap size 0x%llx, limit 0x%lx",
+			 args->size, xdna->dev_info->dev_mem_size);
+		return ERR_PTR(-EINVAL);
+	}
+
+	mutex_lock(&client->mm_lock);
+	if (client->dev_heap) {
+		XDNA_DBG(client->xdna, "dev heap is already created");
+		ret = -EBUSY;
+		goto mm_unlock;
+	}
+
+	abo = amdxdna_gem_create_object(dev, args);
+	if (IS_ERR(abo)) {
+		ret = PTR_ERR(abo);
+		goto mm_unlock;
+	}
+
+	abo->type = AMDXDNA_BO_DEV_HEAP;
+	abo->client = client;
+	abo->mem.dev_addr = client->xdna->dev_info->dev_mem_base;
+	drm_mm_init(&abo->mm, abo->mem.dev_addr, abo->mem.size);
+
+	ret = amdxdna_gem_obj_vmap(abo, &abo->mem.kva);
+	if (ret) {
+		XDNA_ERR(xdna, "Vmap heap bo failed, ret %d", ret);
+		goto release_obj;
+	}
+
+	client->dev_heap = abo;
+	drm_gem_object_get(to_gobj(abo));
+	mutex_unlock(&client->mm_lock);
+
+	return abo;
+
+release_obj:
+	drm_gem_object_put(to_gobj(abo));
+mm_unlock:
+	mutex_unlock(&client->mm_lock);
+	return ERR_PTR(ret);
+}
+
+struct amdxdna_gem_obj *
+amdxdna_drm_alloc_dev_bo(struct drm_device *dev,
+			 struct amdxdna_drm_create_bo *args,
+			 struct drm_file *filp)
+{
+	struct amdxdna_client *client = filp->driver_priv;
+	struct amdxdna_dev *xdna = to_xdna_dev(dev);
+	size_t aligned_sz = PAGE_ALIGN(args->size);
+	struct amdxdna_gem_obj *abo;
+	int ret;
+
+	abo = amdxdna_gem_create_obj(&xdna->ddev, aligned_sz);
+	if (IS_ERR(abo))
+		return abo;
+
+	to_gobj(abo)->funcs = &amdxdna_gem_dev_obj_funcs;
+	abo->type = AMDXDNA_BO_DEV;
+	abo->client = client;
+
+	ret = amdxdna_gem_heap_alloc(abo);
+	if (ret) {
+		XDNA_ERR(xdna, "Failed to alloc dev bo memory, ret %d", ret);
+		amdxdna_gem_destroy_obj(abo);
+		return ERR_PTR(ret);
+	}
+
+	drm_gem_private_object_init(&xdna->ddev, to_gobj(abo), aligned_sz);
+
+	return abo;
+}
+
+static struct amdxdna_gem_obj *
+amdxdna_drm_create_cmd_bo(struct drm_device *dev,
+			  struct amdxdna_drm_create_bo *args,
+			  struct drm_file *filp)
+{
+	struct amdxdna_dev *xdna = to_xdna_dev(dev);
+	struct amdxdna_gem_obj *abo;
+	int ret;
+
+	if (args->size > XDNA_MAX_CMD_BO_SIZE) {
+		XDNA_ERR(xdna, "Command bo size 0x%llx too large", args->size);
+		return ERR_PTR(-EINVAL);
+	}
+
+	if (args->size < sizeof(struct amdxdna_cmd)) {
+		XDNA_DBG(xdna, "Command BO size 0x%llx too small", args->size);
+		return ERR_PTR(-EINVAL);
+	}
+
+	abo = amdxdna_gem_create_object(dev, args);
+	if (IS_ERR(abo))
+		return ERR_CAST(abo);
+
+	abo->type = AMDXDNA_BO_CMD;
+	abo->client = filp->driver_priv;
+
+	ret = amdxdna_gem_obj_vmap(abo, &abo->mem.kva);
+	if (ret) {
+		XDNA_ERR(xdna, "Vmap cmd bo failed, ret %d", ret);
+		goto release_obj;
+	}
+
+	return abo;
+
+release_obj:
+	drm_gem_object_put(to_gobj(abo));
+	return ERR_PTR(ret);
+}
+
+int amdxdna_drm_create_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
+{
+	struct amdxdna_dev *xdna = to_xdna_dev(dev);
+	struct amdxdna_drm_create_bo *args = data;
+	struct amdxdna_gem_obj *abo;
+	int ret;
+
+	if (args->flags)
+		return -EINVAL;
+
+	XDNA_DBG(xdna, "BO arg type %d vaddr 0x%llx size 0x%llx flags 0x%llx",
+		 args->type, args->vaddr, args->size, args->flags);
+	switch (args->type) {
+	case AMDXDNA_BO_SHMEM:
+		abo = amdxdna_drm_alloc_shmem(dev, args, filp);
+		break;
+	case AMDXDNA_BO_DEV_HEAP:
+		abo = amdxdna_drm_create_dev_heap(dev, args, filp);
+		break;
+	case AMDXDNA_BO_DEV:
+		abo = amdxdna_drm_alloc_dev_bo(dev, args, filp);
+		break;
+	case AMDXDNA_BO_CMD:
+		abo = amdxdna_drm_create_cmd_bo(dev, args, filp);
+		break;
+	default:
+		return -EINVAL;
+	}
+	if (IS_ERR(abo))
+		return PTR_ERR(abo);
+
+	/* ready to publish object to userspace */
+	ret = drm_gem_handle_create(filp, to_gobj(abo), &args->handle);
+	if (ret) {
+		XDNA_ERR(xdna, "Create handle failed");
+		goto put_obj;
+	}
+
+	XDNA_DBG(xdna, "BO hdl %d type %d userptr 0x%llx xdna_addr 0x%llx size 0x%lx",
+		 args->handle, args->type, abo->mem.userptr,
+		 abo->mem.dev_addr, abo->mem.size);
+put_obj:
+	/* Dereference object reference. Handle holds it now. */
+	drm_gem_object_put(to_gobj(abo));
+	return ret;
+}
+
+int amdxdna_gem_pin_nolock(struct amdxdna_gem_obj *abo)
+{
+	struct amdxdna_dev *xdna = to_xdna_dev(to_gobj(abo)->dev);
+	int ret;
+
+	if (abo->type == AMDXDNA_BO_DEV)
+		abo = abo->client->dev_heap;
+
+	if (is_import_bo(abo))
+		return 0;
+
+	ret = drm_gem_shmem_pin(&abo->base);
+
+	XDNA_DBG(xdna, "BO type %d ret %d", abo->type, ret);
+	return ret;
+}
+
+int amdxdna_gem_pin(struct amdxdna_gem_obj *abo)
+{
+	int ret;
+
+	mutex_lock(&abo->lock);
+	ret = amdxdna_gem_pin_nolock(abo);
+	mutex_unlock(&abo->lock);
+
+	return ret;
+}
+
+void amdxdna_gem_unpin(struct amdxdna_gem_obj *abo)
+{
+	if (abo->type == AMDXDNA_BO_DEV)
+		abo = abo->client->dev_heap;
+
+	if (is_import_bo(abo))
+		return;
+
+	mutex_lock(&abo->lock);
+	drm_gem_shmem_unpin(&abo->base);
+	mutex_unlock(&abo->lock);
+}
+
+struct amdxdna_gem_obj *amdxdna_gem_get_obj(struct amdxdna_client *client,
+					    u32 bo_hdl, u8 bo_type)
+{
+	struct amdxdna_dev *xdna = client->xdna;
+	struct amdxdna_gem_obj *abo;
+	struct drm_gem_object *gobj;
+
+	gobj = drm_gem_object_lookup(client->filp, bo_hdl);
+	if (!gobj) {
+		XDNA_DBG(xdna, "Can not find bo %d", bo_hdl);
+		return NULL;
+	}
+
+	abo = to_xdna_obj(gobj);
+	if (bo_type == AMDXDNA_BO_INVALID || abo->type == bo_type)
+		return abo;
+
+	drm_gem_object_put(gobj);
+	return NULL;
+}
+
+int amdxdna_drm_get_bo_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
+{
+	struct amdxdna_drm_get_bo_info *args = data;
+	struct amdxdna_dev *xdna = to_xdna_dev(dev);
+	struct amdxdna_gem_obj *abo;
+	struct drm_gem_object *gobj;
+	int ret = 0;
+
+	if (args->ext || args->ext_flags || args->pad)
+		return -EINVAL;
+
+	gobj = drm_gem_object_lookup(filp, args->handle);
+	if (!gobj) {
+		XDNA_DBG(xdna, "Lookup GEM object %d failed", args->handle);
+		return -ENOENT;
+	}
+
+	abo = to_xdna_obj(gobj);
+	args->vaddr = abo->mem.userptr;
+	args->xdna_addr = abo->mem.dev_addr;
+
+	if (abo->type != AMDXDNA_BO_DEV)
+		args->map_offset = drm_vma_node_offset_addr(&gobj->vma_node);
+	else
+		args->map_offset = AMDXDNA_INVALID_ADDR;
+
+	XDNA_DBG(xdna, "BO hdl %d map_offset 0x%llx vaddr 0x%llx xdna_addr 0x%llx",
+		 args->handle, args->map_offset, args->vaddr, args->xdna_addr);
+
+	drm_gem_object_put(gobj);
+	return ret;
+}
+
+/*
+ * The sync bo ioctl is to make sure the CPU cache is in sync with memory.
+ * This is required because NPU is not cache coherent device. CPU cache
+ * flushing/invalidation is expensive so it is best to handle this outside
+ * of the command submission path. This ioctl allows explicit cache
+ * flushing/invalidation outside of the critical path.
+ */
+int amdxdna_drm_sync_bo_ioctl(struct drm_device *dev,
+			      void *data, struct drm_file *filp)
+{
+	struct amdxdna_dev *xdna = to_xdna_dev(dev);
+	struct amdxdna_drm_sync_bo *args = data;
+	struct amdxdna_gem_obj *abo;
+	struct drm_gem_object *gobj;
+	int ret;
+
+	gobj = drm_gem_object_lookup(filp, args->handle);
+	if (!gobj) {
+		XDNA_ERR(xdna, "Lookup GEM object failed");
+		return -ENOENT;
+	}
+	abo = to_xdna_obj(gobj);
+
+	ret = amdxdna_gem_pin(abo);
+	if (ret) {
+		XDNA_ERR(xdna, "Pin BO %d failed, ret %d", args->handle, ret);
+		goto put_obj;
+	}
+
+	if (is_import_bo(abo))
+		drm_clflush_sg(abo->base.sgt);
+	else if (abo->mem.kva)
+		drm_clflush_virt_range(abo->mem.kva + args->offset, args->size);
+	else if (abo->base.pages)
+		drm_clflush_pages(abo->base.pages, gobj->size >> PAGE_SHIFT);
+	else
+		drm_WARN(&xdna->ddev, 1, "Can not get flush memory");
+
+	amdxdna_gem_unpin(abo);
+
+	XDNA_DBG(xdna, "Sync bo %d offset 0x%llx, size 0x%llx\n",
+		 args->handle, args->offset, args->size);
+
+	if (args->direction == SYNC_DIRECT_FROM_DEVICE)
+		ret = amdxdna_hwctx_sync_debug_bo(abo->client, args->handle);
+
+put_obj:
+	drm_gem_object_put(gobj);
+	return ret;
+}
diff --git a/drivers/accel/amdxdna/amdxdna_gem.h b/drivers/accel/amdxdna/amdxdna_gem.h
new file mode 100644
index 000000000000..f79fc7f3c93b
--- /dev/null
+++ b/drivers/accel/amdxdna/amdxdna_gem.h
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2024, Advanced Micro Devices, Inc.
+ */
+
+#ifndef _AMDXDNA_GEM_H_
+#define _AMDXDNA_GEM_H_
+
+#include <linux/hmm.h>
+#include "amdxdna_pci_drv.h"
+
+struct amdxdna_umap {
+	struct vm_area_struct		*vma;
+	struct mmu_interval_notifier	notifier;
+	struct hmm_range		range;
+	struct work_struct		hmm_unreg_work;
+	struct amdxdna_gem_obj		*abo;
+	struct list_head		node;
+	struct kref			refcnt;
+	bool				invalid;
+	bool				unmapped;
+};
+
+struct amdxdna_mem {
+	u64				userptr;
+	void				*kva;
+	u64				dev_addr;
+	size_t				size;
+	struct page			**pages;
+	u32				nr_pages;
+	struct list_head		umap_list;
+	bool				map_invalid;
+};
+
+struct amdxdna_gem_obj {
+	struct drm_gem_shmem_object	base;
+	struct amdxdna_client		*client;
+	u8				type;
+	bool				pinned;
+	struct mutex			lock; /* Protects: pinned */
+	struct amdxdna_mem		mem;
+
+	/* Below members is uninitialized when needed */
+	struct drm_mm			mm; /* For AMDXDNA_BO_DEV_HEAP */
+	struct drm_mm_node		mm_node; /* For AMDXDNA_BO_DEV */
+	u32				assigned_hwctx;
+	struct dma_buf			*dma_buf;
+	struct dma_buf_attachment	*attach;
+};
+
+#define to_gobj(obj)    (&(obj)->base.base)
+#define is_import_bo(obj) ((obj)->attach)
+
+static inline struct amdxdna_gem_obj *to_xdna_obj(struct drm_gem_object *gobj)
+{
+	return container_of(gobj, struct amdxdna_gem_obj, base.base);
+}
+
+struct amdxdna_gem_obj *amdxdna_gem_get_obj(struct amdxdna_client *client,
+					    u32 bo_hdl, u8 bo_type);
+static inline void amdxdna_gem_put_obj(struct amdxdna_gem_obj *abo)
+{
+	drm_gem_object_put(to_gobj(abo));
+}
+
+static inline u64 amdxdna_dev_bo_offset(struct amdxdna_gem_obj *abo)
+{
+	return abo->mem.dev_addr - abo->client->dev_heap->mem.dev_addr;
+}
+
+void amdxdna_umap_put(struct amdxdna_umap *mapp);
+
+struct drm_gem_object *
+amdxdna_gem_create_object_cb(struct drm_device *dev, size_t size);
+struct drm_gem_object *
+amdxdna_gem_prime_import(struct drm_device *dev, struct dma_buf *dma_buf);
+struct amdxdna_gem_obj *
+amdxdna_drm_alloc_dev_bo(struct drm_device *dev,
+			 struct amdxdna_drm_create_bo *args,
+			 struct drm_file *filp);
+
+int amdxdna_gem_pin_nolock(struct amdxdna_gem_obj *abo);
+int amdxdna_gem_pin(struct amdxdna_gem_obj *abo);
+void amdxdna_gem_unpin(struct amdxdna_gem_obj *abo);
+
+int amdxdna_drm_create_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
+int amdxdna_drm_get_bo_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
+int amdxdna_drm_sync_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
+
+#endif /* _AMDXDNA_GEM_H_ */
diff --git a/drivers/accel/amdxdna/amdxdna_mailbox.c b/drivers/accel/amdxdna/amdxdna_mailbox.c
new file mode 100644
index 000000000000..858df97cd3fb
--- /dev/null
+++ b/drivers/accel/amdxdna/amdxdna_mailbox.c
@@ -0,0 +1,575 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022-2024, Advanced Micro Devices, Inc.
+ */
+
+#include <drm/drm_device.h>
+#include <drm/drm_managed.h>
+#include <linux/bitfield.h>
+#include <linux/interrupt.h>
+#include <linux/iopoll.h>
+#include <linux/slab.h>
+#include <linux/xarray.h>
+
+#define CREATE_TRACE_POINTS
+#include <trace/events/amdxdna.h>
+
+#include "amdxdna_mailbox.h"
+
+#define MB_ERR(chann, fmt, args...) \
+({ \
+	typeof(chann) _chann = chann; \
+	dev_err((_chann)->mb->dev, "xdna_mailbox.%d: "fmt, \
+		(_chann)->msix_irq, ##args); \
+})
+#define MB_DBG(chann, fmt, args...) \
+({ \
+	typeof(chann) _chann = chann; \
+	dev_dbg((_chann)->mb->dev, "xdna_mailbox.%d: "fmt, \
+		(_chann)->msix_irq, ##args); \
+})
+#define MB_WARN_ONCE(chann, fmt, args...) \
+({ \
+	typeof(chann) _chann = chann; \
+	dev_warn_once((_chann)->mb->dev, "xdna_mailbox.%d: "fmt, \
+		      (_chann)->msix_irq, ##args); \
+})
+
+#define MAGIC_VAL			0x1D000000U
+#define MAGIC_VAL_MASK			0xFF000000
+#define MAX_MSG_ID_ENTRIES		256
+#define MSG_RX_TIMER			200 /* milliseconds */
+#define MAILBOX_NAME			"xdna_mailbox"
+
+enum channel_res_type {
+	CHAN_RES_X2I,
+	CHAN_RES_I2X,
+	CHAN_RES_NUM
+};
+
+struct mailbox {
+	struct device		*dev;
+	struct xdna_mailbox_res	res;
+};
+
+struct mailbox_channel {
+	struct mailbox			*mb;
+	struct xdna_mailbox_chann_res	res[CHAN_RES_NUM];
+	int				msix_irq;
+	u32				iohub_int_addr;
+	struct xarray			chan_xa;
+	u32				next_msgid;
+	u32				x2i_tail;
+
+	/* Received msg related fields */
+	struct workqueue_struct		*work_q;
+	struct work_struct		rx_work;
+	u32				i2x_head;
+	bool				bad_state;
+};
+
+#define MSG_BODY_SZ		GENMASK(10, 0)
+#define MSG_PROTO_VER		GENMASK(23, 16)
+struct xdna_msg_header {
+	__u32 total_size;
+	__u32 sz_ver;
+	__u32 id;
+	__u32 opcode;
+} __packed;
+
+static_assert(sizeof(struct xdna_msg_header) == 16);
+
+struct mailbox_pkg {
+	struct xdna_msg_header	header;
+	__u32			payload[];
+};
+
+/* The protocol version. */
+#define MSG_PROTOCOL_VERSION	0x1
+/* The tombstone value. */
+#define TOMBSTONE		0xDEADFACE
+
+struct mailbox_msg {
+	void			*handle;
+	int			(*notify_cb)(void *handle, void __iomem *data, size_t size);
+	size_t			pkg_size; /* package size in bytes */
+	struct mailbox_pkg	pkg;
+};
+
+static void mailbox_reg_write(struct mailbox_channel *mb_chann, u32 mbox_reg, u32 data)
+{
+	struct xdna_mailbox_res *mb_res = &mb_chann->mb->res;
+	void __iomem *ringbuf_addr = mb_res->mbox_base + mbox_reg;
+
+	writel(data, ringbuf_addr);
+}
+
+static u32 mailbox_reg_read(struct mailbox_channel *mb_chann, u32 mbox_reg)
+{
+	struct xdna_mailbox_res *mb_res = &mb_chann->mb->res;
+	void __iomem *ringbuf_addr = mb_res->mbox_base + mbox_reg;
+
+	return readl(ringbuf_addr);
+}
+
+static int mailbox_reg_read_non_zero(struct mailbox_channel *mb_chann, u32 mbox_reg, u32 *val)
+{
+	struct xdna_mailbox_res *mb_res = &mb_chann->mb->res;
+	void __iomem *ringbuf_addr = mb_res->mbox_base + mbox_reg;
+	int ret, value;
+
+	/* Poll till value is not zero */
+	ret = readx_poll_timeout(readl, ringbuf_addr, value,
+				 value, 1 /* us */, 100);
+	if (ret < 0)
+		return ret;
+
+	*val = value;
+	return 0;
+}
+
+static inline void
+mailbox_set_headptr(struct mailbox_channel *mb_chann, u32 headptr_val)
+{
+	mailbox_reg_write(mb_chann, mb_chann->res[CHAN_RES_I2X].mb_head_ptr_reg, headptr_val);
+	mb_chann->i2x_head = headptr_val;
+}
+
+static inline void
+mailbox_set_tailptr(struct mailbox_channel *mb_chann, u32 tailptr_val)
+{
+	mailbox_reg_write(mb_chann, mb_chann->res[CHAN_RES_X2I].mb_tail_ptr_reg, tailptr_val);
+	mb_chann->x2i_tail = tailptr_val;
+}
+
+static inline u32
+mailbox_get_headptr(struct mailbox_channel *mb_chann, enum channel_res_type type)
+{
+	return mailbox_reg_read(mb_chann, mb_chann->res[type].mb_head_ptr_reg);
+}
+
+static inline u32
+mailbox_get_tailptr(struct mailbox_channel *mb_chann, enum channel_res_type type)
+{
+	return mailbox_reg_read(mb_chann, mb_chann->res[type].mb_tail_ptr_reg);
+}
+
+static inline u32
+mailbox_get_ringbuf_size(struct mailbox_channel *mb_chann, enum channel_res_type type)
+{
+	return mb_chann->res[type].rb_size;
+}
+
+static inline int mailbox_validate_msgid(int msg_id)
+{
+	return (msg_id & MAGIC_VAL_MASK) == MAGIC_VAL;
+}
+
+static int mailbox_acquire_msgid(struct mailbox_channel *mb_chann, struct mailbox_msg *mb_msg)
+{
+	u32 msg_id;
+	int ret;
+
+	ret = xa_alloc_cyclic_irq(&mb_chann->chan_xa, &msg_id, mb_msg,
+				  XA_LIMIT(0, MAX_MSG_ID_ENTRIES - 1),
+				  &mb_chann->next_msgid, GFP_NOWAIT);
+	if (ret < 0)
+		return ret;
+
+	/*
+	 * Add MAGIC_VAL to the higher bits.
+	 */
+	msg_id |= MAGIC_VAL;
+	return msg_id;
+}
+
+static void mailbox_release_msgid(struct mailbox_channel *mb_chann, int msg_id)
+{
+	msg_id &= ~MAGIC_VAL_MASK;
+	xa_erase_irq(&mb_chann->chan_xa, msg_id);
+}
+
+static void mailbox_release_msg(struct mailbox_channel *mb_chann,
+				struct mailbox_msg *mb_msg)
+{
+	MB_DBG(mb_chann, "msg_id 0x%x msg opcode 0x%x",
+	       mb_msg->pkg.header.id, mb_msg->pkg.header.opcode);
+	if (mb_msg->notify_cb)
+		mb_msg->notify_cb(mb_msg->handle, NULL, 0);
+	kfree(mb_msg);
+}
+
+static int
+mailbox_send_msg(struct mailbox_channel *mb_chann, struct mailbox_msg *mb_msg)
+{
+	void __iomem *write_addr;
+	u32 ringbuf_size;
+	u32 head, tail;
+	u32 start_addr;
+	u32 tmp_tail;
+
+	head = mailbox_get_headptr(mb_chann, CHAN_RES_X2I);
+	tail = mb_chann->x2i_tail;
+	ringbuf_size = mailbox_get_ringbuf_size(mb_chann, CHAN_RES_X2I);
+	start_addr = mb_chann->res[CHAN_RES_X2I].rb_start_addr;
+	tmp_tail = tail + mb_msg->pkg_size;
+
+	if (tail < head && tmp_tail >= head)
+		goto no_space;
+
+	if (tail >= head && (tmp_tail > ringbuf_size - sizeof(u32) &&
+			     mb_msg->pkg_size >= head))
+		goto no_space;
+
+	if (tail >= head && tmp_tail > ringbuf_size - sizeof(u32)) {
+		write_addr = mb_chann->mb->res.ringbuf_base + start_addr + tail;
+		writel(TOMBSTONE, write_addr);
+
+		/* tombstone is set. Write from the start of the ringbuf */
+		tail = 0;
+	}
+
+	write_addr = mb_chann->mb->res.ringbuf_base + start_addr + tail;
+	memcpy_toio(write_addr, &mb_msg->pkg, mb_msg->pkg_size);
+	mailbox_set_tailptr(mb_chann, tail + mb_msg->pkg_size);
+
+	trace_mbox_set_tail(MAILBOX_NAME, mb_chann->msix_irq,
+			    mb_msg->pkg.header.opcode,
+			    mb_msg->pkg.header.id);
+
+	return 0;
+
+no_space:
+	return -ENOSPC;
+}
+
+static int
+mailbox_get_resp(struct mailbox_channel *mb_chann, struct xdna_msg_header *header,
+		 void __iomem *data)
+{
+	struct mailbox_msg *mb_msg;
+	int msg_id;
+	int ret = 0;
+
+	msg_id = header->id;
+	if (!mailbox_validate_msgid(msg_id)) {
+		MB_ERR(mb_chann, "Bad message ID 0x%x", msg_id);
+		return -EINVAL;
+	}
+
+	msg_id &= ~MAGIC_VAL_MASK;
+	mb_msg = xa_erase_irq(&mb_chann->chan_xa, msg_id);
+	if (!mb_msg) {
+		MB_ERR(mb_chann, "Cannot find msg 0x%x", msg_id);
+		return -EINVAL;
+	}
+
+	MB_DBG(mb_chann, "opcode 0x%x size %d id 0x%x",
+	       header->opcode, header->total_size, header->id);
+	if (mb_msg->notify_cb) {
+		ret = mb_msg->notify_cb(mb_msg->handle, data, header->total_size);
+		if (unlikely(ret))
+			MB_ERR(mb_chann, "Message callback ret %d", ret);
+	}
+
+	kfree(mb_msg);
+	return ret;
+}
+
+static int mailbox_get_msg(struct mailbox_channel *mb_chann)
+{
+	struct xdna_msg_header header;
+	void __iomem *read_addr;
+	u32 msg_size, rest;
+	u32 ringbuf_size;
+	u32 head, tail;
+	u32 start_addr;
+	int ret;
+
+	if (mailbox_reg_read_non_zero(mb_chann, mb_chann->res[CHAN_RES_I2X].mb_tail_ptr_reg, &tail))
+		return -EINVAL;
+	head = mb_chann->i2x_head;
+	ringbuf_size = mailbox_get_ringbuf_size(mb_chann, CHAN_RES_I2X);
+	start_addr = mb_chann->res[CHAN_RES_I2X].rb_start_addr;
+
+	if (unlikely(tail > ringbuf_size || !IS_ALIGNED(tail, 4))) {
+		MB_WARN_ONCE(mb_chann, "Invalid tail 0x%x", tail);
+		return -EINVAL;
+	}
+
+	/* ringbuf empty */
+	if (head == tail)
+		return -ENOENT;
+
+	if (head == ringbuf_size)
+		head = 0;
+
+	/* Peek size of the message or TOMBSTONE */
+	read_addr = mb_chann->mb->res.ringbuf_base + start_addr + head;
+	header.total_size = readl(read_addr);
+	/* size is TOMBSTONE, set next read from 0 */
+	if (header.total_size == TOMBSTONE) {
+		if (head < tail) {
+			MB_WARN_ONCE(mb_chann, "Tombstone, head 0x%x tail 0x%x",
+				     head, tail);
+			return -EINVAL;
+		}
+		mailbox_set_headptr(mb_chann, 0);
+		return 0;
+	}
+
+	if (unlikely(!header.total_size || !IS_ALIGNED(header.total_size, 4))) {
+		MB_WARN_ONCE(mb_chann, "Invalid total size 0x%x", header.total_size);
+		return -EINVAL;
+	}
+	msg_size = sizeof(header) + header.total_size;
+
+	if (msg_size > ringbuf_size - head || msg_size > tail - head) {
+		MB_WARN_ONCE(mb_chann, "Invalid message size %d, tail %d, head %d",
+			     msg_size, tail, head);
+		return -EINVAL;
+	}
+
+	rest = sizeof(header) - sizeof(u32);
+	read_addr += sizeof(u32);
+	memcpy_fromio((u32 *)&header + 1, read_addr, rest);
+	read_addr += rest;
+
+	ret = mailbox_get_resp(mb_chann, &header, read_addr);
+
+	mailbox_set_headptr(mb_chann, head + msg_size);
+	/* After update head, it can equal to ringbuf_size. This is expected. */
+	trace_mbox_set_head(MAILBOX_NAME, mb_chann->msix_irq,
+			    header.opcode, header.id);
+
+	return ret;
+}
+
+static irqreturn_t mailbox_irq_handler(int irq, void *p)
+{
+	struct mailbox_channel *mb_chann = p;
+
+	trace_mbox_irq_handle(MAILBOX_NAME, irq);
+	/* Schedule a rx_work to call the callback functions */
+	queue_work(mb_chann->work_q, &mb_chann->rx_work);
+
+	return IRQ_HANDLED;
+}
+
+static void mailbox_rx_worker(struct work_struct *rx_work)
+{
+	struct mailbox_channel *mb_chann;
+	int ret;
+
+	mb_chann = container_of(rx_work, struct mailbox_channel, rx_work);
+
+	if (READ_ONCE(mb_chann->bad_state)) {
+		MB_ERR(mb_chann, "Channel in bad state, work aborted");
+		return;
+	}
+
+again:
+	mailbox_reg_write(mb_chann, mb_chann->iohub_int_addr, 0);
+
+	while (1) {
+		/*
+		 * If return is 0, keep consuming next message, until there is
+		 * no messages or an error happened.
+		 */
+		ret = mailbox_get_msg(mb_chann);
+		if (ret == -ENOENT)
+			break;
+
+		/* Other error means device doesn't look good, disable irq. */
+		if (unlikely(ret)) {
+			MB_ERR(mb_chann, "Unexpected ret %d, disable irq", ret);
+			WRITE_ONCE(mb_chann->bad_state, true);
+			return;
+		}
+	}
+
+	/*
+	 * The hardware will not generate interrupt if firmware creates a new
+	 * response right after driver clears interrupt register. Check
+	 * the interrupt register to make sure there is not any new response
+	 * before exiting.
+	 */
+	if (mailbox_reg_read(mb_chann, mb_chann->iohub_int_addr))
+		goto again;
+}
+
+int xdna_mailbox_send_msg(struct mailbox_channel *mb_chann,
+			  const struct xdna_mailbox_msg *msg, u64 tx_timeout)
+{
+	struct xdna_msg_header *header;
+	struct mailbox_msg *mb_msg;
+	size_t pkg_size;
+	int ret;
+
+	pkg_size = sizeof(*header) + msg->send_size;
+	if (pkg_size > mailbox_get_ringbuf_size(mb_chann, CHAN_RES_X2I)) {
+		MB_ERR(mb_chann, "Message size larger than ringbuf size");
+		return -EINVAL;
+	}
+
+	if (unlikely(!IS_ALIGNED(msg->send_size, 4))) {
+		MB_ERR(mb_chann, "Message must be 4 bytes align");
+		return -EINVAL;
+	}
+
+	/* The fist word in payload can NOT be TOMBSTONE */
+	if (unlikely(((u32 *)msg->send_data)[0] == TOMBSTONE)) {
+		MB_ERR(mb_chann, "Tomb stone in data");
+		return -EINVAL;
+	}
+
+	if (READ_ONCE(mb_chann->bad_state)) {
+		MB_ERR(mb_chann, "Channel in bad state");
+		return -EPIPE;
+	}
+
+	mb_msg = kzalloc(sizeof(*mb_msg) + pkg_size, GFP_KERNEL);
+	if (!mb_msg)
+		return -ENOMEM;
+
+	mb_msg->handle = msg->handle;
+	mb_msg->notify_cb = msg->notify_cb;
+	mb_msg->pkg_size = pkg_size;
+
+	header = &mb_msg->pkg.header;
+	/*
+	 * Hardware use total_size and size to split huge message.
+	 * We do not support it here. Thus the values are the same.
+	 */
+	header->total_size = msg->send_size;
+	header->sz_ver = FIELD_PREP(MSG_BODY_SZ, msg->send_size) |
+			FIELD_PREP(MSG_PROTO_VER, MSG_PROTOCOL_VERSION);
+	header->opcode = msg->opcode;
+	memcpy(mb_msg->pkg.payload, msg->send_data, msg->send_size);
+
+	ret = mailbox_acquire_msgid(mb_chann, mb_msg);
+	if (unlikely(ret < 0)) {
+		MB_ERR(mb_chann, "mailbox_acquire_msgid failed");
+		goto msg_id_failed;
+	}
+	header->id = ret;
+
+	MB_DBG(mb_chann, "opcode 0x%x size %d id 0x%x",
+	       header->opcode, header->total_size, header->id);
+
+	ret = mailbox_send_msg(mb_chann, mb_msg);
+	if (ret) {
+		MB_DBG(mb_chann, "Error in mailbox send msg, ret %d", ret);
+		goto release_id;
+	}
+
+	return 0;
+
+release_id:
+	mailbox_release_msgid(mb_chann, header->id);
+msg_id_failed:
+	kfree(mb_msg);
+	return ret;
+}
+
+struct mailbox_channel *
+xdna_mailbox_create_channel(struct mailbox *mb,
+			    const struct xdna_mailbox_chann_res *x2i,
+			    const struct xdna_mailbox_chann_res *i2x,
+			    u32 iohub_int_addr,
+			    int mb_irq)
+{
+	struct mailbox_channel *mb_chann;
+	int ret;
+
+	if (!is_power_of_2(x2i->rb_size) || !is_power_of_2(i2x->rb_size)) {
+		pr_err("Ring buf size must be power of 2");
+		return NULL;
+	}
+
+	mb_chann = kzalloc(sizeof(*mb_chann), GFP_KERNEL);
+	if (!mb_chann)
+		return NULL;
+
+	mb_chann->mb = mb;
+	mb_chann->msix_irq = mb_irq;
+	mb_chann->iohub_int_addr = iohub_int_addr;
+	memcpy(&mb_chann->res[CHAN_RES_X2I], x2i, sizeof(*x2i));
+	memcpy(&mb_chann->res[CHAN_RES_I2X], i2x, sizeof(*i2x));
+
+	xa_init_flags(&mb_chann->chan_xa, XA_FLAGS_ALLOC | XA_FLAGS_LOCK_IRQ);
+	mb_chann->x2i_tail = mailbox_get_tailptr(mb_chann, CHAN_RES_X2I);
+	mb_chann->i2x_head = mailbox_get_headptr(mb_chann, CHAN_RES_I2X);
+
+	INIT_WORK(&mb_chann->rx_work, mailbox_rx_worker);
+	mb_chann->work_q = create_singlethread_workqueue(MAILBOX_NAME);
+	if (!mb_chann->work_q) {
+		MB_ERR(mb_chann, "Create workqueue failed");
+		goto free_and_out;
+	}
+
+	/* Everything look good. Time to enable irq handler */
+	ret = request_irq(mb_irq, mailbox_irq_handler, 0, MAILBOX_NAME, mb_chann);
+	if (ret) {
+		MB_ERR(mb_chann, "Failed to request irq %d ret %d", mb_irq, ret);
+		goto destroy_wq;
+	}
+
+	mb_chann->bad_state = false;
+	mailbox_reg_write(mb_chann, mb_chann->iohub_int_addr, 0);
+
+	MB_DBG(mb_chann, "Mailbox channel created (irq: %d)", mb_chann->msix_irq);
+	return mb_chann;
+
+destroy_wq:
+	destroy_workqueue(mb_chann->work_q);
+free_and_out:
+	kfree(mb_chann);
+	return NULL;
+}
+
+int xdna_mailbox_destroy_channel(struct mailbox_channel *mb_chann)
+{
+	struct mailbox_msg *mb_msg;
+	unsigned long msg_id;
+
+	MB_DBG(mb_chann, "IRQ disabled and RX work cancelled");
+	free_irq(mb_chann->msix_irq, mb_chann);
+	destroy_workqueue(mb_chann->work_q);
+	/* We can clean up and release resources */
+
+	xa_for_each(&mb_chann->chan_xa, msg_id, mb_msg)
+		mailbox_release_msg(mb_chann, mb_msg);
+
+	xa_destroy(&mb_chann->chan_xa);
+
+	MB_DBG(mb_chann, "Mailbox channel destroyed, irq: %d", mb_chann->msix_irq);
+	kfree(mb_chann);
+	return 0;
+}
+
+void xdna_mailbox_stop_channel(struct mailbox_channel *mb_chann)
+{
+	/* Disable an irq and wait. This might sleep. */
+	disable_irq(mb_chann->msix_irq);
+
+	/* Cancel RX work and wait for it to finish */
+	cancel_work_sync(&mb_chann->rx_work);
+	MB_DBG(mb_chann, "IRQ disabled and RX work cancelled");
+}
+
+struct mailbox *xdnam_mailbox_create(struct drm_device *ddev,
+				     const struct xdna_mailbox_res *res)
+{
+	struct mailbox *mb;
+
+	mb = drmm_kzalloc(ddev, sizeof(*mb), GFP_KERNEL);
+	if (!mb)
+		return NULL;
+	mb->dev = ddev->dev;
+
+	/* mailbox and ring buf base and size information */
+	memcpy(&mb->res, res, sizeof(*res));
+
+	return mb;
+}
diff --git a/drivers/accel/amdxdna/amdxdna_mailbox.h b/drivers/accel/amdxdna/amdxdna_mailbox.h
new file mode 100644
index 000000000000..ea367f2fb738
--- /dev/null
+++ b/drivers/accel/amdxdna/amdxdna_mailbox.h
@@ -0,0 +1,124 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2022-2024, Advanced Micro Devices, Inc.
+ */
+
+#ifndef _AIE2_MAILBOX_H_
+#define _AIE2_MAILBOX_H_
+
+struct mailbox;
+struct mailbox_channel;
+
+/*
+ * xdna_mailbox_msg - message struct
+ *
+ * @opcode:	opcode for firmware
+ * @handle:	handle used for the notify callback
+ * @notify_cb:  callback function to notify the sender when there is response
+ * @send_data:	pointing to sending data
+ * @send_size:	size of the sending data
+ *
+ * The mailbox will split the sending data in to multiple firmware message if
+ * the size of the data is too big. This is transparent to the sender. The
+ * sender will receive one notification.
+ */
+struct xdna_mailbox_msg {
+	u32		opcode;
+	void		*handle;
+	int		(*notify_cb)(void *handle, void __iomem *data, size_t size);
+	u8		*send_data;
+	size_t		send_size;
+};
+
+/*
+ * xdna_mailbox_res - mailbox hardware resource
+ *
+ * @ringbuf_base:	ring buffer base address
+ * @ringbuf_size:	ring buffer size
+ * @mbox_base:		mailbox base address
+ * @mbox_size:		mailbox size
+ */
+struct xdna_mailbox_res {
+	void __iomem	*ringbuf_base;
+	size_t		ringbuf_size;
+	void __iomem	*mbox_base;
+	size_t		mbox_size;
+	const char	*name;
+};
+
+/*
+ * xdna_mailbox_chann_res - resources
+ *
+ * @rb_start_addr:	ring buffer start address
+ * @rb_size:		ring buffer size
+ * @mb_head_ptr_reg:	mailbox head pointer register
+ * @mb_tail_ptr_reg:	mailbox tail pointer register
+ */
+struct xdna_mailbox_chann_res {
+	u32 rb_start_addr;
+	u32 rb_size;
+	u32 mb_head_ptr_reg;
+	u32 mb_tail_ptr_reg;
+};
+
+/*
+ * xdna_mailbox_create() -- create mailbox subsystem and initialize
+ *
+ * @ddev: device pointer
+ * @res: SRAM and mailbox resources
+ *
+ * Return: If success, return a handle of mailbox subsystem.
+ * Otherwise, return NULL pointer.
+ */
+struct mailbox *xdnam_mailbox_create(struct drm_device *ddev,
+				     const struct xdna_mailbox_res *res);
+
+/*
+ * xdna_mailbox_create_channel() -- Create a mailbox channel instance
+ *
+ * @mailbox: the handle return from xdna_mailbox_create()
+ * @x2i: host to firmware mailbox resources
+ * @i2x: firmware to host mailbox resources
+ * @xdna_mailbox_intr_reg: register addr of MSI-X interrupt
+ * @mb_irq: Linux IRQ number associated with mailbox MSI-X interrupt vector index
+ *
+ * Return: If success, return a handle of mailbox channel. Otherwise, return NULL.
+ */
+struct mailbox_channel *
+xdna_mailbox_create_channel(struct mailbox *mailbox,
+			    const struct xdna_mailbox_chann_res *x2i,
+			    const struct xdna_mailbox_chann_res *i2x,
+			    u32 xdna_mailbox_intr_reg,
+			    int mb_irq);
+
+/*
+ * xdna_mailbox_destroy_channel() -- destroy mailbox channel
+ *
+ * @mailbox_chann: the handle return from xdna_mailbox_create_channel()
+ *
+ * Return: if success, return 0. otherwise return error code
+ */
+int xdna_mailbox_destroy_channel(struct mailbox_channel *mailbox_chann);
+
+/*
+ * xdna_mailbox_stop_channel() -- stop mailbox channel
+ *
+ * @mailbox_chann: the handle return from xdna_mailbox_create_channel()
+ *
+ * Return: if success, return 0. otherwise return error code
+ */
+void xdna_mailbox_stop_channel(struct mailbox_channel *mailbox_chann);
+
+/*
+ * xdna_mailbox_send_msg() -- Send a message
+ *
+ * @mailbox_chann: Mailbox channel handle
+ * @msg: message struct for message information
+ * @tx_timeout: the timeout value for sending the message in ms.
+ *
+ * Return: If success return 0, otherwise, return error code
+ */
+int xdna_mailbox_send_msg(struct mailbox_channel *mailbox_chann,
+			  const struct xdna_mailbox_msg *msg, u64 tx_timeout);
+
+#endif /* _AIE2_MAILBOX_ */
diff --git a/drivers/accel/amdxdna/amdxdna_mailbox_helper.c b/drivers/accel/amdxdna/amdxdna_mailbox_helper.c
new file mode 100644
index 000000000000..6d0c24513476
--- /dev/null
+++ b/drivers/accel/amdxdna/amdxdna_mailbox_helper.c
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024, Advanced Micro Devices, Inc.
+ */
+
+#include <drm/amdxdna_accel.h>
+#include <drm/drm_device.h>
+#include <drm/drm_print.h>
+#include <drm/drm_gem.h>
+#include <drm/drm_gem_shmem_helper.h>
+#include <drm/gpu_scheduler.h>
+#include <linux/completion.h>
+
+#include "amdxdna_gem.h"
+#include "amdxdna_mailbox.h"
+#include "amdxdna_mailbox_helper.h"
+#include "amdxdna_pci_drv.h"
+
+int xdna_msg_cb(void *handle, void __iomem *data, size_t size)
+{
+	struct xdna_notify *cb_arg = handle;
+	int ret;
+
+	if (unlikely(!data))
+		goto out;
+
+	if (unlikely(cb_arg->size != size)) {
+		cb_arg->error = -EINVAL;
+		goto out;
+	}
+
+	memcpy_fromio(cb_arg->data, data, cb_arg->size);
+	print_hex_dump_debug("resp data: ", DUMP_PREFIX_OFFSET,
+			     16, 4, cb_arg->data, cb_arg->size, true);
+out:
+	ret = cb_arg->error;
+	complete(&cb_arg->comp);
+	return ret;
+}
+
+int xdna_send_msg_wait(struct amdxdna_dev *xdna, struct mailbox_channel *chann,
+		       struct xdna_mailbox_msg *msg)
+{
+	struct xdna_notify *hdl = msg->handle;
+	int ret;
+
+	ret = xdna_mailbox_send_msg(chann, msg, TX_TIMEOUT);
+	if (ret) {
+		XDNA_ERR(xdna, "Send message failed, ret %d", ret);
+		return ret;
+	}
+
+	ret = wait_for_completion_timeout(&hdl->comp,
+					  msecs_to_jiffies(RX_TIMEOUT));
+	if (!ret) {
+		XDNA_ERR(xdna, "Wait for completion timeout");
+		return -ETIME;
+	}
+
+	return hdl->error;
+}
diff --git a/drivers/accel/amdxdna/amdxdna_mailbox_helper.h b/drivers/accel/amdxdna/amdxdna_mailbox_helper.h
new file mode 100644
index 000000000000..556c712cad0a
--- /dev/null
+++ b/drivers/accel/amdxdna/amdxdna_mailbox_helper.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2023-2024, Advanced Micro Devices, Inc.
+ */
+
+#ifndef _AMDXDNA_MAILBOX_HELPER_H
+#define _AMDXDNA_MAILBOX_HELPER_H
+
+#define TX_TIMEOUT 2000 /* milliseconds */
+#define RX_TIMEOUT 5000 /* milliseconds */
+
+struct amdxdna_dev;
+
+struct xdna_notify {
+	struct completion       comp;
+	u32			*data;
+	size_t			size;
+	int			error;
+	u32			*status;
+};
+
+#define DECLARE_XDNA_MSG_COMMON(name, op, s)				\
+	struct name##_req	req = { 0 };				\
+	struct name##_resp	resp = { .status = s };			\
+	struct xdna_notify	hdl = {					\
+		.error = 0,						\
+		.data = (u32 *)&resp,					\
+		.size = sizeof(resp),					\
+		.comp = COMPLETION_INITIALIZER_ONSTACK(hdl.comp),	\
+		.status = (u32 *)&resp.status,				\
+	};								\
+	struct xdna_mailbox_msg msg = {					\
+		.send_data = (u8 *)&req,				\
+		.send_size = sizeof(req),				\
+		.handle = &hdl,						\
+		.opcode = op,						\
+		.notify_cb = xdna_msg_cb,				\
+	}
+
+int xdna_msg_cb(void *handle, void __iomem *data, size_t size);
+int xdna_send_msg_wait(struct amdxdna_dev *xdna, struct mailbox_channel *chann,
+		       struct xdna_mailbox_msg *msg);
+
+#endif /* _AMDXDNA_MAILBOX_HELPER_H */
diff --git a/drivers/accel/amdxdna/amdxdna_pci_drv.c b/drivers/accel/amdxdna/amdxdna_pci_drv.c
new file mode 100644
index 000000000000..1973ab67721b
--- /dev/null
+++ b/drivers/accel/amdxdna/amdxdna_pci_drv.c
@@ -0,0 +1,364 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022-2024, Advanced Micro Devices, Inc.
+ */
+
+#include <drm/amdxdna_accel.h>
+#include <drm/drm_accel.h>
+#include <drm/drm_drv.h>
+#include <drm/drm_gem.h>
+#include <drm/drm_gem_shmem_helper.h>
+#include <drm/drm_ioctl.h>
+#include <drm/drm_managed.h>
+#include <drm/gpu_scheduler.h>
+#include <linux/iommu.h>
+#include <linux/pci.h>
+
+#include "amdxdna_ctx.h"
+#include "amdxdna_gem.h"
+#include "amdxdna_pci_drv.h"
+#include "amdxdna_pm.h"
+
+MODULE_FIRMWARE("amdnpu/1502_00/npu.sbin");
+MODULE_FIRMWARE("amdnpu/17f0_10/npu.sbin");
+MODULE_FIRMWARE("amdnpu/17f0_11/npu.sbin");
+MODULE_FIRMWARE("amdnpu/17f0_20/npu.sbin");
+
+/*
+ * 0.0: Initial version
+ * 0.1: Support getting all hardware contexts by DRM_IOCTL_AMDXDNA_GET_ARRAY
+ * 0.2: Support getting last error hardware error
+ * 0.3: Support firmware debug buffer
+ * 0.4: Support getting resource information
+ * 0.5: Support getting telemetry data
+ * 0.6: Support preemption
+ */
+#define AMDXDNA_DRIVER_MAJOR		0
+#define AMDXDNA_DRIVER_MINOR		6
+
+/*
+ * Bind the driver base on (vendor_id, device_id) pair and later use the
+ * (device_id, rev_id) pair as a key to select the devices. The devices with
+ * same device_id have very similar interface to host driver.
+ */
+static const struct pci_device_id pci_ids[] = {
+	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1502) },
+	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x17f0) },
+	{0}
+};
+
+MODULE_DEVICE_TABLE(pci, pci_ids);
+
+static const struct amdxdna_device_id amdxdna_ids[] = {
+	{ 0x1502, 0x0,  &dev_npu1_info },
+	{ 0x17f0, 0x0,  &dev_npu2_info },
+	{ 0x17f0, 0x10, &dev_npu4_info },
+	{ 0x17f0, 0x11, &dev_npu5_info },
+	{ 0x17f0, 0x20, &dev_npu6_info },
+	{0}
+};
+
+static int amdxdna_drm_open(struct drm_device *ddev, struct drm_file *filp)
+{
+	struct amdxdna_dev *xdna = to_xdna_dev(ddev);
+	struct amdxdna_client *client;
+	int ret;
+
+	client = kzalloc(sizeof(*client), GFP_KERNEL);
+	if (!client)
+		return -ENOMEM;
+
+	client->pid = pid_nr(rcu_access_pointer(filp->pid));
+	client->xdna = xdna;
+
+	client->sva = iommu_sva_bind_device(xdna->ddev.dev, current->mm);
+	if (IS_ERR(client->sva)) {
+		ret = PTR_ERR(client->sva);
+		XDNA_ERR(xdna, "SVA bind device failed, ret %d", ret);
+		goto failed;
+	}
+	client->pasid = iommu_sva_get_pasid(client->sva);
+	if (client->pasid == IOMMU_PASID_INVALID) {
+		XDNA_ERR(xdna, "SVA get pasid failed");
+		ret = -ENODEV;
+		goto unbind_sva;
+	}
+	init_srcu_struct(&client->hwctx_srcu);
+	xa_init_flags(&client->hwctx_xa, XA_FLAGS_ALLOC);
+	mutex_init(&client->mm_lock);
+
+	mutex_lock(&xdna->dev_lock);
+	list_add_tail(&client->node, &xdna->client_list);
+	mutex_unlock(&xdna->dev_lock);
+
+	filp->driver_priv = client;
+	client->filp = filp;
+
+	XDNA_DBG(xdna, "pid %d opened", client->pid);
+	return 0;
+
+unbind_sva:
+	iommu_sva_unbind_device(client->sva);
+failed:
+	kfree(client);
+
+	return ret;
+}
+
+static void amdxdna_drm_close(struct drm_device *ddev, struct drm_file *filp)
+{
+	struct amdxdna_client *client = filp->driver_priv;
+	struct amdxdna_dev *xdna = to_xdna_dev(ddev);
+
+	XDNA_DBG(xdna, "closing pid %d", client->pid);
+
+	xa_destroy(&client->hwctx_xa);
+	cleanup_srcu_struct(&client->hwctx_srcu);
+	mutex_destroy(&client->mm_lock);
+	if (client->dev_heap)
+		drm_gem_object_put(to_gobj(client->dev_heap));
+
+	iommu_sva_unbind_device(client->sva);
+
+	XDNA_DBG(xdna, "pid %d closed", client->pid);
+	kfree(client);
+}
+
+static int amdxdna_flush(struct file *f, fl_owner_t id)
+{
+	struct drm_file *filp = f->private_data;
+	struct amdxdna_client *client = filp->driver_priv;
+	struct amdxdna_dev *xdna = client->xdna;
+	int idx;
+
+	XDNA_DBG(xdna, "PID %d flushing...", client->pid);
+	if (!drm_dev_enter(&xdna->ddev, &idx))
+		return 0;
+
+	mutex_lock(&xdna->dev_lock);
+	list_del_init(&client->node);
+	amdxdna_hwctx_remove_all(client);
+	mutex_unlock(&xdna->dev_lock);
+
+	drm_dev_exit(idx);
+	return 0;
+}
+
+static int amdxdna_drm_get_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
+{
+	struct amdxdna_client *client = filp->driver_priv;
+	struct amdxdna_dev *xdna = to_xdna_dev(dev);
+	struct amdxdna_drm_get_info *args = data;
+	int ret;
+
+	if (!xdna->dev_info->ops->get_aie_info)
+		return -EOPNOTSUPP;
+
+	XDNA_DBG(xdna, "Request parameter %u", args->param);
+	mutex_lock(&xdna->dev_lock);
+	ret = xdna->dev_info->ops->get_aie_info(client, args);
+	mutex_unlock(&xdna->dev_lock);
+	return ret;
+}
+
+static int amdxdna_drm_get_array_ioctl(struct drm_device *dev, void *data,
+				       struct drm_file *filp)
+{
+	struct amdxdna_client *client = filp->driver_priv;
+	struct amdxdna_dev *xdna = to_xdna_dev(dev);
+	struct amdxdna_drm_get_array *args = data;
+
+	if (!xdna->dev_info->ops->get_array)
+		return -EOPNOTSUPP;
+
+	if (args->pad || !args->num_element || !args->element_size)
+		return -EINVAL;
+
+	guard(mutex)(&xdna->dev_lock);
+	return xdna->dev_info->ops->get_array(client, args);
+}
+
+static int amdxdna_drm_set_state_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
+{
+	struct amdxdna_client *client = filp->driver_priv;
+	struct amdxdna_dev *xdna = to_xdna_dev(dev);
+	struct amdxdna_drm_set_state *args = data;
+	int ret;
+
+	if (!xdna->dev_info->ops->set_aie_state)
+		return -EOPNOTSUPP;
+
+	XDNA_DBG(xdna, "Request parameter %u", args->param);
+	mutex_lock(&xdna->dev_lock);
+	ret = xdna->dev_info->ops->set_aie_state(client, args);
+	mutex_unlock(&xdna->dev_lock);
+
+	return ret;
+}
+
+static const struct drm_ioctl_desc amdxdna_drm_ioctls[] = {
+	/* Context */
+	DRM_IOCTL_DEF_DRV(AMDXDNA_CREATE_HWCTX, amdxdna_drm_create_hwctx_ioctl, 0),
+	DRM_IOCTL_DEF_DRV(AMDXDNA_DESTROY_HWCTX, amdxdna_drm_destroy_hwctx_ioctl, 0),
+	DRM_IOCTL_DEF_DRV(AMDXDNA_CONFIG_HWCTX, amdxdna_drm_config_hwctx_ioctl, 0),
+	/* BO */
+	DRM_IOCTL_DEF_DRV(AMDXDNA_CREATE_BO, amdxdna_drm_create_bo_ioctl, 0),
+	DRM_IOCTL_DEF_DRV(AMDXDNA_GET_BO_INFO, amdxdna_drm_get_bo_info_ioctl, 0),
+	DRM_IOCTL_DEF_DRV(AMDXDNA_SYNC_BO, amdxdna_drm_sync_bo_ioctl, 0),
+	/* Execution */
+	DRM_IOCTL_DEF_DRV(AMDXDNA_EXEC_CMD, amdxdna_drm_submit_cmd_ioctl, 0),
+	/* AIE hardware */
+	DRM_IOCTL_DEF_DRV(AMDXDNA_GET_INFO, amdxdna_drm_get_info_ioctl, 0),
+	DRM_IOCTL_DEF_DRV(AMDXDNA_GET_ARRAY, amdxdna_drm_get_array_ioctl, 0),
+	DRM_IOCTL_DEF_DRV(AMDXDNA_SET_STATE, amdxdna_drm_set_state_ioctl, DRM_ROOT_ONLY),
+};
+
+static const struct file_operations amdxdna_fops = {
+	.owner		= THIS_MODULE,
+	.open		= accel_open,
+	.release	= drm_release,
+	.flush		= amdxdna_flush,
+	.unlocked_ioctl	= drm_ioctl,
+	.compat_ioctl	= drm_compat_ioctl,
+	.poll		= drm_poll,
+	.read		= drm_read,
+	.llseek		= noop_llseek,
+	.mmap		= drm_gem_mmap,
+	.fop_flags	= FOP_UNSIGNED_OFFSET,
+};
+
+const struct drm_driver amdxdna_drm_drv = {
+	.driver_features = DRIVER_GEM | DRIVER_COMPUTE_ACCEL |
+		DRIVER_SYNCOBJ | DRIVER_SYNCOBJ_TIMELINE,
+	.fops = &amdxdna_fops,
+	.name = "amdxdna_accel_driver",
+	.desc = "AMD XDNA DRM implementation",
+	.major = AMDXDNA_DRIVER_MAJOR,
+	.minor = AMDXDNA_DRIVER_MINOR,
+	.open = amdxdna_drm_open,
+	.postclose = amdxdna_drm_close,
+	.ioctls = amdxdna_drm_ioctls,
+	.num_ioctls = ARRAY_SIZE(amdxdna_drm_ioctls),
+
+	.gem_create_object = amdxdna_gem_create_object_cb,
+	.gem_prime_import = amdxdna_gem_prime_import,
+};
+
+static const struct amdxdna_dev_info *
+amdxdna_get_dev_info(struct pci_dev *pdev)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(amdxdna_ids); i++) {
+		if (pdev->device == amdxdna_ids[i].device &&
+		    pdev->revision == amdxdna_ids[i].revision)
+			return amdxdna_ids[i].dev_info;
+	}
+	return NULL;
+}
+
+static int amdxdna_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+{
+	struct device *dev = &pdev->dev;
+	struct amdxdna_dev *xdna;
+	int ret;
+
+	xdna = devm_drm_dev_alloc(dev, &amdxdna_drm_drv, typeof(*xdna), ddev);
+	if (IS_ERR(xdna))
+		return PTR_ERR(xdna);
+
+	xdna->dev_info = amdxdna_get_dev_info(pdev);
+	if (!xdna->dev_info)
+		return -ENODEV;
+
+	drmm_mutex_init(&xdna->ddev, &xdna->dev_lock);
+	init_rwsem(&xdna->notifier_lock);
+	INIT_LIST_HEAD(&xdna->client_list);
+	pci_set_drvdata(pdev, xdna);
+
+	if (IS_ENABLED(CONFIG_LOCKDEP)) {
+		fs_reclaim_acquire(GFP_KERNEL);
+		might_lock(&xdna->notifier_lock);
+		fs_reclaim_release(GFP_KERNEL);
+	}
+
+	xdna->notifier_wq = alloc_ordered_workqueue("notifier_wq", 0);
+	if (!xdna->notifier_wq)
+		return -ENOMEM;
+
+	mutex_lock(&xdna->dev_lock);
+	ret = xdna->dev_info->ops->init(xdna);
+	mutex_unlock(&xdna->dev_lock);
+	if (ret) {
+		XDNA_ERR(xdna, "Hardware init failed, ret %d", ret);
+		goto destroy_notifier_wq;
+	}
+
+	ret = amdxdna_sysfs_init(xdna);
+	if (ret) {
+		XDNA_ERR(xdna, "Create amdxdna attrs failed: %d", ret);
+		goto failed_dev_fini;
+	}
+
+	ret = drm_dev_register(&xdna->ddev, 0);
+	if (ret) {
+		XDNA_ERR(xdna, "DRM register failed, ret %d", ret);
+		goto failed_sysfs_fini;
+	}
+
+	return 0;
+
+failed_sysfs_fini:
+	amdxdna_sysfs_fini(xdna);
+failed_dev_fini:
+	mutex_lock(&xdna->dev_lock);
+	xdna->dev_info->ops->fini(xdna);
+	mutex_unlock(&xdna->dev_lock);
+destroy_notifier_wq:
+	destroy_workqueue(xdna->notifier_wq);
+	return ret;
+}
+
+static void amdxdna_remove(struct pci_dev *pdev)
+{
+	struct amdxdna_dev *xdna = pci_get_drvdata(pdev);
+	struct amdxdna_client *client;
+
+	destroy_workqueue(xdna->notifier_wq);
+
+	drm_dev_unplug(&xdna->ddev);
+	amdxdna_sysfs_fini(xdna);
+
+	mutex_lock(&xdna->dev_lock);
+	client = list_first_entry_or_null(&xdna->client_list,
+					  struct amdxdna_client, node);
+	while (client) {
+		list_del_init(&client->node);
+		amdxdna_hwctx_remove_all(client);
+
+		client = list_first_entry_or_null(&xdna->client_list,
+						  struct amdxdna_client, node);
+	}
+
+	xdna->dev_info->ops->fini(xdna);
+	mutex_unlock(&xdna->dev_lock);
+}
+
+static const struct dev_pm_ops amdxdna_pm_ops = {
+	SYSTEM_SLEEP_PM_OPS(amdxdna_pm_suspend, amdxdna_pm_resume)
+	RUNTIME_PM_OPS(amdxdna_pm_suspend, amdxdna_pm_resume, NULL)
+};
+
+static struct pci_driver amdxdna_pci_driver = {
+	.name = KBUILD_MODNAME,
+	.id_table = pci_ids,
+	.probe = amdxdna_probe,
+	.remove = amdxdna_remove,
+	.driver.pm = &amdxdna_pm_ops,
+};
+
+module_pci_driver(amdxdna_pci_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("XRT Team <runtimeca39d@amd.com>");
+MODULE_DESCRIPTION("amdxdna driver");
diff --git a/drivers/accel/amdxdna/amdxdna_pci_drv.h b/drivers/accel/amdxdna/amdxdna_pci_drv.h
new file mode 100644
index 000000000000..c99477f5e454
--- /dev/null
+++ b/drivers/accel/amdxdna/amdxdna_pci_drv.h
@@ -0,0 +1,149 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2022-2024, Advanced Micro Devices, Inc.
+ */
+
+#ifndef _AMDXDNA_PCI_DRV_H_
+#define _AMDXDNA_PCI_DRV_H_
+
+#include <drm/drm_print.h>
+#include <linux/workqueue.h>
+#include <linux/xarray.h>
+
+#define XDNA_INFO(xdna, fmt, args...)	drm_info(&(xdna)->ddev, fmt, ##args)
+#define XDNA_WARN(xdna, fmt, args...)	drm_warn(&(xdna)->ddev, "%s: "fmt, __func__, ##args)
+#define XDNA_ERR(xdna, fmt, args...)	drm_err(&(xdna)->ddev, "%s: "fmt, __func__, ##args)
+#define XDNA_DBG(xdna, fmt, args...)	drm_dbg(&(xdna)->ddev, fmt, ##args)
+#define XDNA_INFO_ONCE(xdna, fmt, args...) drm_info_once(&(xdna)->ddev, fmt, ##args)
+
+#define XDNA_MBZ_DBG(xdna, ptr, sz)					\
+	({								\
+		int __i;						\
+		int __ret = 0;						\
+		u8 *__ptr = (u8 *)(ptr);				\
+		for (__i = 0; __i < (sz); __i++) {			\
+			if (__ptr[__i]) {				\
+				XDNA_DBG(xdna, "MBZ check failed");	\
+				__ret = -EINVAL;			\
+				break;					\
+			}						\
+		}							\
+		__ret;							\
+	})
+
+#define to_xdna_dev(drm_dev) \
+	((struct amdxdna_dev *)container_of(drm_dev, struct amdxdna_dev, ddev))
+
+extern const struct drm_driver amdxdna_drm_drv;
+
+struct amdxdna_client;
+struct amdxdna_dev;
+struct amdxdna_drm_get_info;
+struct amdxdna_drm_set_state;
+struct amdxdna_gem_obj;
+struct amdxdna_hwctx;
+struct amdxdna_sched_job;
+
+/*
+ * struct amdxdna_dev_ops - Device hardware operation callbacks
+ */
+struct amdxdna_dev_ops {
+	int (*init)(struct amdxdna_dev *xdna);
+	void (*fini)(struct amdxdna_dev *xdna);
+	int (*resume)(struct amdxdna_dev *xdna);
+	int (*suspend)(struct amdxdna_dev *xdna);
+	int (*hwctx_init)(struct amdxdna_hwctx *hwctx);
+	void (*hwctx_fini)(struct amdxdna_hwctx *hwctx);
+	int (*hwctx_config)(struct amdxdna_hwctx *hwctx, u32 type, u64 value, void *buf, u32 size);
+	int (*hwctx_sync_debug_bo)(struct amdxdna_hwctx *hwctx, u32 debug_bo_hdl);
+	void (*hmm_invalidate)(struct amdxdna_gem_obj *abo, unsigned long cur_seq);
+	int (*cmd_submit)(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job, u64 *seq);
+	int (*get_aie_info)(struct amdxdna_client *client, struct amdxdna_drm_get_info *args);
+	int (*set_aie_state)(struct amdxdna_client *client, struct amdxdna_drm_set_state *args);
+	int (*get_array)(struct amdxdna_client *client, struct amdxdna_drm_get_array *args);
+};
+
+/*
+ * struct amdxdna_dev_info - Device hardware information
+ * Record device static information, like reg, mbox, PSP, SMU bar index
+ */
+struct amdxdna_dev_info {
+	int				reg_bar;
+	int				mbox_bar;
+	int				sram_bar;
+	int				psp_bar;
+	int				smu_bar;
+	int				device_type;
+	int				first_col;
+	u32				dev_mem_buf_shift;
+	u64				dev_mem_base;
+	size_t				dev_mem_size;
+	char				*vbnv;
+	const struct amdxdna_dev_priv	*dev_priv;
+	const struct amdxdna_dev_ops	*ops;
+};
+
+struct amdxdna_fw_ver {
+	u32 major;
+	u32 minor;
+	u32 sub;
+	u32 build;
+};
+
+struct amdxdna_dev {
+	struct drm_device		ddev;
+	struct amdxdna_dev_hdl		*dev_handle;
+	const struct amdxdna_dev_info	*dev_info;
+	void				*xrs_hdl;
+
+	struct mutex			dev_lock; /* per device lock */
+	struct list_head		client_list;
+	struct amdxdna_fw_ver		fw_ver;
+	struct rw_semaphore		notifier_lock; /* for mmu notifier*/
+	struct workqueue_struct		*notifier_wq;
+	bool				rpm_on;
+};
+
+/*
+ * struct amdxdna_device_id - PCI device info
+ */
+struct amdxdna_device_id {
+	unsigned short device;
+	u8 revision;
+	const struct amdxdna_dev_info *dev_info;
+};
+
+/*
+ * struct amdxdna_client - amdxdna client
+ * A per fd data structure for managing context and other user process stuffs.
+ */
+struct amdxdna_client {
+	struct list_head		node;
+	pid_t				pid;
+	struct srcu_struct		hwctx_srcu;
+	struct xarray			hwctx_xa;
+	u32				next_hwctxid;
+	struct amdxdna_dev		*xdna;
+	struct drm_file			*filp;
+
+	struct mutex			mm_lock; /* protect memory related */
+	struct amdxdna_gem_obj		*dev_heap;
+
+	struct iommu_sva		*sva;
+	int				pasid;
+};
+
+#define amdxdna_for_each_hwctx(client, hwctx_id, entry)		\
+	xa_for_each(&(client)->hwctx_xa, hwctx_id, entry)
+
+/* Add device info below */
+extern const struct amdxdna_dev_info dev_npu1_info;
+extern const struct amdxdna_dev_info dev_npu2_info;
+extern const struct amdxdna_dev_info dev_npu4_info;
+extern const struct amdxdna_dev_info dev_npu5_info;
+extern const struct amdxdna_dev_info dev_npu6_info;
+
+int amdxdna_sysfs_init(struct amdxdna_dev *xdna);
+void amdxdna_sysfs_fini(struct amdxdna_dev *xdna);
+
+#endif /* _AMDXDNA_PCI_DRV_H_ */
diff --git a/drivers/accel/amdxdna/amdxdna_pm.c b/drivers/accel/amdxdna/amdxdna_pm.c
new file mode 100644
index 000000000000..fa38e65d617c
--- /dev/null
+++ b/drivers/accel/amdxdna/amdxdna_pm.c
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025, Advanced Micro Devices, Inc.
+ */
+
+#include <drm/amdxdna_accel.h>
+#include <drm/drm_drv.h>
+#include <linux/pm_runtime.h>
+
+#include "amdxdna_pm.h"
+
+#define AMDXDNA_AUTOSUSPEND_DELAY	5000 /* milliseconds */
+
+int amdxdna_pm_suspend(struct device *dev)
+{
+	struct amdxdna_dev *xdna = to_xdna_dev(dev_get_drvdata(dev));
+	int ret = -EOPNOTSUPP;
+	bool rpm;
+
+	if (xdna->dev_info->ops->suspend) {
+		rpm = xdna->rpm_on;
+		xdna->rpm_on = false;
+		ret = xdna->dev_info->ops->suspend(xdna);
+		xdna->rpm_on = rpm;
+	}
+
+	XDNA_DBG(xdna, "Suspend done ret %d", ret);
+	return ret;
+}
+
+int amdxdna_pm_resume(struct device *dev)
+{
+	struct amdxdna_dev *xdna = to_xdna_dev(dev_get_drvdata(dev));
+	int ret = -EOPNOTSUPP;
+	bool rpm;
+
+	if (xdna->dev_info->ops->resume) {
+		rpm = xdna->rpm_on;
+		xdna->rpm_on = false;
+		ret = xdna->dev_info->ops->resume(xdna);
+		xdna->rpm_on = rpm;
+	}
+
+	XDNA_DBG(xdna, "Resume done ret %d", ret);
+	return ret;
+}
+
+int amdxdna_pm_resume_get(struct amdxdna_dev *xdna)
+{
+	struct device *dev = xdna->ddev.dev;
+	int ret;
+
+	if (!xdna->rpm_on)
+		return 0;
+
+	ret = pm_runtime_resume_and_get(dev);
+	if (ret) {
+		XDNA_ERR(xdna, "Resume failed: %d", ret);
+		pm_runtime_set_suspended(dev);
+	}
+
+	return ret;
+}
+
+void amdxdna_pm_suspend_put(struct amdxdna_dev *xdna)
+{
+	struct device *dev = xdna->ddev.dev;
+
+	if (!xdna->rpm_on)
+		return;
+
+	pm_runtime_put_autosuspend(dev);
+}
+
+void amdxdna_pm_init(struct amdxdna_dev *xdna)
+{
+	struct device *dev = xdna->ddev.dev;
+
+	pm_runtime_set_active(dev);
+	pm_runtime_set_autosuspend_delay(dev, AMDXDNA_AUTOSUSPEND_DELAY);
+	pm_runtime_use_autosuspend(dev);
+	pm_runtime_allow(dev);
+	pm_runtime_put_autosuspend(dev);
+	xdna->rpm_on = true;
+}
+
+void amdxdna_pm_fini(struct amdxdna_dev *xdna)
+{
+	struct device *dev = xdna->ddev.dev;
+
+	xdna->rpm_on = false;
+	pm_runtime_get_noresume(dev);
+	pm_runtime_forbid(dev);
+}
diff --git a/drivers/accel/amdxdna/amdxdna_pm.h b/drivers/accel/amdxdna/amdxdna_pm.h
new file mode 100644
index 000000000000..77b2d6e45570
--- /dev/null
+++ b/drivers/accel/amdxdna/amdxdna_pm.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2025, Advanced Micro Devices, Inc.
+ */
+
+#ifndef _AMDXDNA_PM_H_
+#define _AMDXDNA_PM_H_
+
+#include "amdxdna_pci_drv.h"
+
+int amdxdna_pm_suspend(struct device *dev);
+int amdxdna_pm_resume(struct device  *dev);
+int amdxdna_pm_resume_get(struct amdxdna_dev *xdna);
+void amdxdna_pm_suspend_put(struct amdxdna_dev *xdna);
+void amdxdna_pm_init(struct amdxdna_dev *xdna);
+void amdxdna_pm_fini(struct amdxdna_dev *xdna);
+
+#endif /* _AMDXDNA_PM_H_ */
diff --git a/drivers/accel/amdxdna/amdxdna_sysfs.c b/drivers/accel/amdxdna/amdxdna_sysfs.c
new file mode 100644
index 000000000000..f27e4ee960a0
--- /dev/null
+++ b/drivers/accel/amdxdna/amdxdna_sysfs.c
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023-2024, Advanced Micro Devices, Inc.
+ */
+
+#include <drm/amdxdna_accel.h>
+#include <drm/drm_device.h>
+#include <drm/drm_gem_shmem_helper.h>
+#include <drm/drm_print.h>
+#include <drm/gpu_scheduler.h>
+#include <linux/types.h>
+
+#include "amdxdna_gem.h"
+#include "amdxdna_pci_drv.h"
+
+static ssize_t vbnv_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+	struct amdxdna_dev *xdna = dev_get_drvdata(dev);
+
+	return sprintf(buf, "%s\n", xdna->dev_info->vbnv);
+}
+static DEVICE_ATTR_RO(vbnv);
+
+static ssize_t device_type_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+	struct amdxdna_dev *xdna = dev_get_drvdata(dev);
+
+	return sprintf(buf, "%d\n", xdna->dev_info->device_type);
+}
+static DEVICE_ATTR_RO(device_type);
+
+static ssize_t fw_version_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+	struct amdxdna_dev *xdna = dev_get_drvdata(dev);
+
+	return sprintf(buf, "%d.%d.%d.%d\n", xdna->fw_ver.major,
+		       xdna->fw_ver.minor, xdna->fw_ver.sub,
+		       xdna->fw_ver.build);
+}
+static DEVICE_ATTR_RO(fw_version);
+
+static struct attribute *amdxdna_attrs[] = {
+	&dev_attr_device_type.attr,
+	&dev_attr_vbnv.attr,
+	&dev_attr_fw_version.attr,
+	NULL,
+};
+
+static struct attribute_group amdxdna_attr_group = {
+	.attrs = amdxdna_attrs,
+};
+
+int amdxdna_sysfs_init(struct amdxdna_dev *xdna)
+{
+	int ret;
+
+	ret = sysfs_create_group(&xdna->ddev.dev->kobj, &amdxdna_attr_group);
+	if (ret)
+		XDNA_ERR(xdna, "Create attr group failed");
+
+	return ret;
+}
+
+void amdxdna_sysfs_fini(struct amdxdna_dev *xdna)
+{
+	sysfs_remove_group(&xdna->ddev.dev->kobj, &amdxdna_attr_group);
+}
diff --git a/drivers/accel/amdxdna/amdxdna_ubuf.c b/drivers/accel/amdxdna/amdxdna_ubuf.c
new file mode 100644
index 000000000000..077b2261cf2a
--- /dev/null
+++ b/drivers/accel/amdxdna/amdxdna_ubuf.c
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025, Advanced Micro Devices, Inc.
+ */
+
+#include <drm/amdxdna_accel.h>
+#include <drm/drm_device.h>
+#include <drm/drm_print.h>
+#include <linux/dma-buf.h>
+#include <linux/pagemap.h>
+#include <linux/vmalloc.h>
+
+#include "amdxdna_pci_drv.h"
+#include "amdxdna_ubuf.h"
+
+struct amdxdna_ubuf_priv {
+	struct page **pages;
+	u64 nr_pages;
+	enum amdxdna_ubuf_flag flags;
+	struct mm_struct *mm;
+};
+
+static struct sg_table *amdxdna_ubuf_map(struct dma_buf_attachment *attach,
+					 enum dma_data_direction direction)
+{
+	struct amdxdna_ubuf_priv *ubuf = attach->dmabuf->priv;
+	struct sg_table *sg;
+	int ret;
+
+	sg = kzalloc(sizeof(*sg), GFP_KERNEL);
+	if (!sg)
+		return ERR_PTR(-ENOMEM);
+
+	ret = sg_alloc_table_from_pages(sg, ubuf->pages, ubuf->nr_pages, 0,
+					ubuf->nr_pages << PAGE_SHIFT, GFP_KERNEL);
+	if (ret)
+		return ERR_PTR(ret);
+
+	if (ubuf->flags & AMDXDNA_UBUF_FLAG_MAP_DMA) {
+		ret = dma_map_sgtable(attach->dev, sg, direction, 0);
+		if (ret)
+			return ERR_PTR(ret);
+	}
+
+	return sg;
+}
+
+static void amdxdna_ubuf_unmap(struct dma_buf_attachment *attach,
+			       struct sg_table *sg,
+			       enum dma_data_direction direction)
+{
+	struct amdxdna_ubuf_priv *ubuf = attach->dmabuf->priv;
+
+	if (ubuf->flags & AMDXDNA_UBUF_FLAG_MAP_DMA)
+		dma_unmap_sgtable(attach->dev, sg, direction, 0);
+
+	sg_free_table(sg);
+	kfree(sg);
+}
+
+static void amdxdna_ubuf_release(struct dma_buf *dbuf)
+{
+	struct amdxdna_ubuf_priv *ubuf = dbuf->priv;
+
+	unpin_user_pages(ubuf->pages, ubuf->nr_pages);
+	kvfree(ubuf->pages);
+	atomic64_sub(ubuf->nr_pages, &ubuf->mm->pinned_vm);
+	mmdrop(ubuf->mm);
+	kfree(ubuf);
+}
+
+static vm_fault_t amdxdna_ubuf_vm_fault(struct vm_fault *vmf)
+{
+	struct vm_area_struct *vma = vmf->vma;
+	struct amdxdna_ubuf_priv *ubuf;
+	unsigned long pfn;
+	pgoff_t pgoff;
+
+	ubuf = vma->vm_private_data;
+	pgoff = (vmf->address - vma->vm_start) >> PAGE_SHIFT;
+
+	pfn = page_to_pfn(ubuf->pages[pgoff]);
+	return vmf_insert_pfn(vma, vmf->address, pfn);
+}
+
+static const struct vm_operations_struct amdxdna_ubuf_vm_ops = {
+	.fault = amdxdna_ubuf_vm_fault,
+};
+
+static int amdxdna_ubuf_mmap(struct dma_buf *dbuf, struct vm_area_struct *vma)
+{
+	struct amdxdna_ubuf_priv *ubuf = dbuf->priv;
+
+	vma->vm_ops = &amdxdna_ubuf_vm_ops;
+	vma->vm_private_data = ubuf;
+	vm_flags_set(vma, VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP);
+
+	return 0;
+}
+
+static int amdxdna_ubuf_vmap(struct dma_buf *dbuf, struct iosys_map *map)
+{
+	struct amdxdna_ubuf_priv *ubuf = dbuf->priv;
+	void *kva;
+
+	kva = vmap(ubuf->pages, ubuf->nr_pages, VM_MAP, PAGE_KERNEL);
+	if (!kva)
+		return -EINVAL;
+
+	iosys_map_set_vaddr(map, kva);
+	return 0;
+}
+
+static void amdxdna_ubuf_vunmap(struct dma_buf *dbuf, struct iosys_map *map)
+{
+	vunmap(map->vaddr);
+}
+
+static const struct dma_buf_ops amdxdna_ubuf_dmabuf_ops = {
+	.map_dma_buf = amdxdna_ubuf_map,
+	.unmap_dma_buf = amdxdna_ubuf_unmap,
+	.release = amdxdna_ubuf_release,
+	.mmap = amdxdna_ubuf_mmap,
+	.vmap = amdxdna_ubuf_vmap,
+	.vunmap = amdxdna_ubuf_vunmap,
+};
+
+struct dma_buf *amdxdna_get_ubuf(struct drm_device *dev,
+				 enum amdxdna_ubuf_flag flags,
+				 u32 num_entries, void __user *va_entries)
+{
+	struct amdxdna_dev *xdna = to_xdna_dev(dev);
+	unsigned long lock_limit, new_pinned;
+	struct amdxdna_drm_va_entry *va_ent;
+	struct amdxdna_ubuf_priv *ubuf;
+	u32 npages, start = 0;
+	struct dma_buf *dbuf;
+	int i, ret;
+	DEFINE_DMA_BUF_EXPORT_INFO(exp_info);
+
+	if (!can_do_mlock())
+		return ERR_PTR(-EPERM);
+
+	ubuf = kzalloc(sizeof(*ubuf), GFP_KERNEL);
+	if (!ubuf)
+		return ERR_PTR(-ENOMEM);
+
+	ubuf->flags = flags;
+	ubuf->mm = current->mm;
+	mmgrab(ubuf->mm);
+
+	va_ent = kvcalloc(num_entries, sizeof(*va_ent), GFP_KERNEL);
+	if (!va_ent) {
+		ret = -ENOMEM;
+		goto free_ubuf;
+	}
+
+	if (copy_from_user(va_ent, va_entries, sizeof(*va_ent) * num_entries)) {
+		XDNA_DBG(xdna, "Access va entries failed");
+		ret = -EINVAL;
+		goto free_ent;
+	}
+
+	for (i = 0, exp_info.size = 0; i < num_entries; i++) {
+		if (!IS_ALIGNED(va_ent[i].vaddr, PAGE_SIZE) ||
+		    !IS_ALIGNED(va_ent[i].len, PAGE_SIZE)) {
+			XDNA_ERR(xdna, "Invalid address or len %llx, %llx",
+				 va_ent[i].vaddr, va_ent[i].len);
+			ret = -EINVAL;
+			goto free_ent;
+		}
+
+		exp_info.size += va_ent[i].len;
+	}
+
+	ubuf->nr_pages = exp_info.size >> PAGE_SHIFT;
+	lock_limit = rlimit(RLIMIT_MEMLOCK) >> PAGE_SHIFT;
+	new_pinned = atomic64_add_return(ubuf->nr_pages, &ubuf->mm->pinned_vm);
+	if (new_pinned > lock_limit && !capable(CAP_IPC_LOCK)) {
+		XDNA_DBG(xdna, "New pin %ld, limit %ld, cap %d",
+			 new_pinned, lock_limit, capable(CAP_IPC_LOCK));
+		ret = -ENOMEM;
+		goto sub_pin_cnt;
+	}
+
+	ubuf->pages = kvmalloc_array(ubuf->nr_pages, sizeof(*ubuf->pages), GFP_KERNEL);
+	if (!ubuf->pages) {
+		ret = -ENOMEM;
+		goto sub_pin_cnt;
+	}
+
+	for (i = 0; i < num_entries; i++) {
+		npages = va_ent[i].len >> PAGE_SHIFT;
+
+		ret = pin_user_pages_fast(va_ent[i].vaddr, npages,
+					  FOLL_WRITE | FOLL_LONGTERM,
+					  &ubuf->pages[start]);
+		if (ret < 0 || ret != npages) {
+			ret = -ENOMEM;
+			XDNA_ERR(xdna, "Failed to pin pages ret %d", ret);
+			goto destroy_pages;
+		}
+
+		start += ret;
+	}
+
+	exp_info.ops = &amdxdna_ubuf_dmabuf_ops;
+	exp_info.priv = ubuf;
+	exp_info.flags = O_RDWR | O_CLOEXEC;
+
+	dbuf = dma_buf_export(&exp_info);
+	if (IS_ERR(dbuf)) {
+		ret = PTR_ERR(dbuf);
+		goto destroy_pages;
+	}
+	kvfree(va_ent);
+
+	return dbuf;
+
+destroy_pages:
+	if (start)
+		unpin_user_pages(ubuf->pages, start);
+	kvfree(ubuf->pages);
+sub_pin_cnt:
+	atomic64_sub(ubuf->nr_pages, &ubuf->mm->pinned_vm);
+free_ent:
+	kvfree(va_ent);
+free_ubuf:
+	mmdrop(ubuf->mm);
+	kfree(ubuf);
+	return ERR_PTR(ret);
+}
diff --git a/drivers/accel/amdxdna/amdxdna_ubuf.h b/drivers/accel/amdxdna/amdxdna_ubuf.h
new file mode 100644
index 000000000000..e5cb3bdb3ec9
--- /dev/null
+++ b/drivers/accel/amdxdna/amdxdna_ubuf.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2025, Advanced Micro Devices, Inc.
+ */
+#ifndef _AMDXDNA_UBUF_H_
+#define _AMDXDNA_UBUF_H_
+
+#include <drm/drm_device.h>
+#include <linux/dma-buf.h>
+
+enum amdxdna_ubuf_flag {
+	AMDXDNA_UBUF_FLAG_MAP_DMA = 1,
+};
+
+struct dma_buf *amdxdna_get_ubuf(struct drm_device *dev,
+				 enum amdxdna_ubuf_flag flags,
+				 u32 num_entries, void __user *va_entries);
+
+#endif /* _AMDXDNA_UBUF_H_ */
diff --git a/drivers/accel/amdxdna/npu1_regs.c b/drivers/accel/amdxdna/npu1_regs.c
new file mode 100644
index 000000000000..ec407f3b48fc
--- /dev/null
+++ b/drivers/accel/amdxdna/npu1_regs.c
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023-2024, Advanced Micro Devices, Inc.
+ */
+
+#include <drm/amdxdna_accel.h>
+#include <drm/drm_device.h>
+#include <drm/gpu_scheduler.h>
+#include <linux/sizes.h>
+
+#include "aie2_pci.h"
+#include "amdxdna_mailbox.h"
+#include "amdxdna_pci_drv.h"
+
+/* Address definition from NPU1 docs */
+#define MPNPU_PUB_SEC_INTR		0x3010090
+#define MPNPU_PUB_PWRMGMT_INTR		0x3010094
+#define MPNPU_PUB_SCRATCH2		0x30100A0
+#define MPNPU_PUB_SCRATCH3		0x30100A4
+#define MPNPU_PUB_SCRATCH4		0x30100A8
+#define MPNPU_PUB_SCRATCH5		0x30100AC
+#define MPNPU_PUB_SCRATCH6		0x30100B0
+#define MPNPU_PUB_SCRATCH7		0x30100B4
+#define MPNPU_PUB_SCRATCH9		0x30100BC
+
+#define MPNPU_SRAM_X2I_MAILBOX_0	0x30A0000
+#define MPNPU_SRAM_X2I_MAILBOX_1	0x30A2000
+#define MPNPU_SRAM_I2X_MAILBOX_15	0x30BF000
+
+#define MPNPU_APERTURE0_BASE		0x3000000
+#define MPNPU_APERTURE1_BASE		0x3080000
+#define MPNPU_APERTURE2_BASE		0x30C0000
+
+/* PCIe BAR Index for NPU1 */
+#define NPU1_REG_BAR_INDEX  0
+#define NPU1_MBOX_BAR_INDEX 4
+#define NPU1_PSP_BAR_INDEX  0
+#define NPU1_SMU_BAR_INDEX  0
+#define NPU1_SRAM_BAR_INDEX 2
+/* Associated BARs and Apertures */
+#define NPU1_REG_BAR_BASE  MPNPU_APERTURE0_BASE
+#define NPU1_MBOX_BAR_BASE MPNPU_APERTURE2_BASE
+#define NPU1_PSP_BAR_BASE  MPNPU_APERTURE0_BASE
+#define NPU1_SMU_BAR_BASE  MPNPU_APERTURE0_BASE
+#define NPU1_SRAM_BAR_BASE MPNPU_APERTURE1_BASE
+
+const struct rt_config npu1_default_rt_cfg[] = {
+	{ 2, 1, AIE2_RT_CFG_INIT }, /* PDI APP LOAD MODE */
+	{ 4, 1, AIE2_RT_CFG_INIT }, /* Debug BO */
+	{ 1, 1, AIE2_RT_CFG_CLK_GATING }, /* Clock gating on */
+	{ 0 },
+};
+
+const struct dpm_clk_freq npu1_dpm_clk_table[] = {
+	{400, 800},
+	{600, 1024},
+	{600, 1024},
+	{600, 1024},
+	{600, 1024},
+	{720, 1309},
+	{720, 1309},
+	{847, 1600},
+	{ 0 }
+};
+
+static const struct aie2_fw_feature_tbl npu1_fw_feature_table[] = {
+	{ .feature = AIE2_NPU_COMMAND, .min_minor = 8 },
+	{ 0 }
+};
+
+static const struct amdxdna_dev_priv npu1_dev_priv = {
+	.fw_path        = "amdnpu/1502_00/npu.sbin",
+	.protocol_major = 0x5,
+	.protocol_minor = 0x7,
+	.rt_config	= npu1_default_rt_cfg,
+	.dpm_clk_tbl	= npu1_dpm_clk_table,
+	.fw_feature_tbl = npu1_fw_feature_table,
+	.col_align	= COL_ALIGN_NONE,
+	.mbox_dev_addr  = NPU1_MBOX_BAR_BASE,
+	.mbox_size      = 0, /* Use BAR size */
+	.sram_dev_addr  = NPU1_SRAM_BAR_BASE,
+	.hwctx_limit    = 6,
+	.sram_offs      = {
+		DEFINE_BAR_OFFSET(MBOX_CHANN_OFF, NPU1_SRAM, MPNPU_SRAM_X2I_MAILBOX_0),
+		DEFINE_BAR_OFFSET(FW_ALIVE_OFF,   NPU1_SRAM, MPNPU_SRAM_I2X_MAILBOX_15),
+	},
+	.psp_regs_off   = {
+		DEFINE_BAR_OFFSET(PSP_CMD_REG,    NPU1_PSP, MPNPU_PUB_SCRATCH2),
+		DEFINE_BAR_OFFSET(PSP_ARG0_REG,   NPU1_PSP, MPNPU_PUB_SCRATCH3),
+		DEFINE_BAR_OFFSET(PSP_ARG1_REG,   NPU1_PSP, MPNPU_PUB_SCRATCH4),
+		DEFINE_BAR_OFFSET(PSP_ARG2_REG,   NPU1_PSP, MPNPU_PUB_SCRATCH9),
+		DEFINE_BAR_OFFSET(PSP_INTR_REG,   NPU1_PSP, MPNPU_PUB_SEC_INTR),
+		DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU1_PSP, MPNPU_PUB_SCRATCH2),
+		DEFINE_BAR_OFFSET(PSP_RESP_REG,   NPU1_PSP, MPNPU_PUB_SCRATCH3),
+	},
+	.smu_regs_off   = {
+		DEFINE_BAR_OFFSET(SMU_CMD_REG,  NPU1_SMU, MPNPU_PUB_SCRATCH5),
+		DEFINE_BAR_OFFSET(SMU_ARG_REG,  NPU1_SMU, MPNPU_PUB_SCRATCH7),
+		DEFINE_BAR_OFFSET(SMU_INTR_REG, NPU1_SMU, MPNPU_PUB_PWRMGMT_INTR),
+		DEFINE_BAR_OFFSET(SMU_RESP_REG, NPU1_SMU, MPNPU_PUB_SCRATCH6),
+		DEFINE_BAR_OFFSET(SMU_OUT_REG,  NPU1_SMU, MPNPU_PUB_SCRATCH7),
+	},
+	.hw_ops		= {
+		.set_dpm = npu1_set_dpm,
+	},
+};
+
+const struct amdxdna_dev_info dev_npu1_info = {
+	.reg_bar           = NPU1_REG_BAR_INDEX,
+	.mbox_bar          = NPU1_MBOX_BAR_INDEX,
+	.sram_bar          = NPU1_SRAM_BAR_INDEX,
+	.psp_bar           = NPU1_PSP_BAR_INDEX,
+	.smu_bar           = NPU1_SMU_BAR_INDEX,
+	.first_col         = 1,
+	.dev_mem_buf_shift = 15, /* 32 KiB aligned */
+	.dev_mem_base      = AIE2_DEVM_BASE,
+	.dev_mem_size      = AIE2_DEVM_SIZE,
+	.vbnv              = "RyzenAI-npu1",
+	.device_type       = AMDXDNA_DEV_TYPE_KMQ,
+	.dev_priv          = &npu1_dev_priv,
+	.ops               = &aie2_ops,
+};
diff --git a/drivers/accel/amdxdna/npu2_regs.c b/drivers/accel/amdxdna/npu2_regs.c
new file mode 100644
index 000000000000..86f87d0d1354
--- /dev/null
+++ b/drivers/accel/amdxdna/npu2_regs.c
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023-2024, Advanced Micro Devices, Inc.
+ */
+
+#include <drm/amdxdna_accel.h>
+#include <drm/drm_device.h>
+#include <drm/gpu_scheduler.h>
+#include <linux/sizes.h>
+
+#include "aie2_pci.h"
+#include "amdxdna_mailbox.h"
+#include "amdxdna_pci_drv.h"
+
+/* NPU Public Registers on MpNPUAxiXbar (refer to Diag npu_registers.h) */
+#define MPNPU_PUB_SEC_INTR             0x3010060
+#define MPNPU_PUB_PWRMGMT_INTR         0x3010064
+#define MPNPU_PUB_SCRATCH0             0x301006C
+#define MPNPU_PUB_SCRATCH1             0x3010070
+#define MPNPU_PUB_SCRATCH2             0x3010074
+#define MPNPU_PUB_SCRATCH3             0x3010078
+#define MPNPU_PUB_SCRATCH4             0x301007C
+#define MPNPU_PUB_SCRATCH5             0x3010080
+#define MPNPU_PUB_SCRATCH6             0x3010084
+#define MPNPU_PUB_SCRATCH7             0x3010088
+#define MPNPU_PUB_SCRATCH8             0x301008C
+#define MPNPU_PUB_SCRATCH9             0x3010090
+#define MPNPU_PUB_SCRATCH10            0x3010094
+#define MPNPU_PUB_SCRATCH11            0x3010098
+#define MPNPU_PUB_SCRATCH12            0x301009C
+#define MPNPU_PUB_SCRATCH13            0x30100A0
+#define MPNPU_PUB_SCRATCH14            0x30100A4
+#define MPNPU_PUB_SCRATCH15            0x30100A8
+#define MP0_C2PMSG_73                  0x3810A24
+#define MP0_C2PMSG_123                 0x3810AEC
+
+#define MP1_C2PMSG_0                   0x3B10900
+#define MP1_C2PMSG_60                  0x3B109F0
+#define MP1_C2PMSG_61                  0x3B109F4
+
+#define MPNPU_SRAM_X2I_MAILBOX_0       0x3600000
+#define MPNPU_SRAM_X2I_MAILBOX_15      0x361E000
+#define MPNPU_SRAM_X2I_MAILBOX_31      0x363E000
+#define MPNPU_SRAM_I2X_MAILBOX_31      0x363F000
+
+#define MMNPU_APERTURE0_BASE           0x3000000
+#define MMNPU_APERTURE1_BASE           0x3600000
+#define MMNPU_APERTURE3_BASE           0x3810000
+#define MMNPU_APERTURE4_BASE           0x3B10000
+
+/* PCIe BAR Index for NPU2 */
+#define NPU2_REG_BAR_INDEX	0
+#define NPU2_MBOX_BAR_INDEX	0
+#define NPU2_PSP_BAR_INDEX	4
+#define NPU2_SMU_BAR_INDEX	5
+#define NPU2_SRAM_BAR_INDEX	2
+/* Associated BARs and Apertures */
+#define NPU2_REG_BAR_BASE	MMNPU_APERTURE0_BASE
+#define NPU2_MBOX_BAR_BASE	MMNPU_APERTURE0_BASE
+#define NPU2_PSP_BAR_BASE	MMNPU_APERTURE3_BASE
+#define NPU2_SMU_BAR_BASE	MMNPU_APERTURE4_BASE
+#define NPU2_SRAM_BAR_BASE	MMNPU_APERTURE1_BASE
+
+static const struct amdxdna_dev_priv npu2_dev_priv = {
+	.fw_path        = "amdnpu/17f0_00/npu.sbin",
+	.protocol_major = 0x6,
+	.protocol_minor = 0x6,
+	.rt_config	= npu4_default_rt_cfg,
+	.dpm_clk_tbl	= npu4_dpm_clk_table,
+	.fw_feature_tbl = npu4_fw_feature_table,
+	.col_align	= COL_ALIGN_NATURE,
+	.mbox_dev_addr  = NPU2_MBOX_BAR_BASE,
+	.mbox_size      = 0, /* Use BAR size */
+	.sram_dev_addr  = NPU2_SRAM_BAR_BASE,
+	.hwctx_limit    = 16,
+	.sram_offs      = {
+		DEFINE_BAR_OFFSET(MBOX_CHANN_OFF, NPU2_SRAM, MPNPU_SRAM_X2I_MAILBOX_0),
+		DEFINE_BAR_OFFSET(FW_ALIVE_OFF,   NPU2_SRAM, MPNPU_SRAM_X2I_MAILBOX_15),
+	},
+	.psp_regs_off   = {
+		DEFINE_BAR_OFFSET(PSP_CMD_REG,    NPU2_PSP, MP0_C2PMSG_123),
+		DEFINE_BAR_OFFSET(PSP_ARG0_REG,   NPU2_REG, MPNPU_PUB_SCRATCH3),
+		DEFINE_BAR_OFFSET(PSP_ARG1_REG,   NPU2_REG, MPNPU_PUB_SCRATCH4),
+		DEFINE_BAR_OFFSET(PSP_ARG2_REG,   NPU2_REG, MPNPU_PUB_SCRATCH9),
+		DEFINE_BAR_OFFSET(PSP_INTR_REG,   NPU2_PSP, MP0_C2PMSG_73),
+		DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU2_PSP, MP0_C2PMSG_123),
+		DEFINE_BAR_OFFSET(PSP_RESP_REG,   NPU2_REG, MPNPU_PUB_SCRATCH3),
+	},
+	.smu_regs_off   = {
+		DEFINE_BAR_OFFSET(SMU_CMD_REG,  NPU2_SMU, MP1_C2PMSG_0),
+		DEFINE_BAR_OFFSET(SMU_ARG_REG,  NPU2_SMU, MP1_C2PMSG_60),
+		DEFINE_BAR_OFFSET(SMU_INTR_REG, NPU2_SMU, MMNPU_APERTURE4_BASE),
+		DEFINE_BAR_OFFSET(SMU_RESP_REG, NPU2_SMU, MP1_C2PMSG_61),
+		DEFINE_BAR_OFFSET(SMU_OUT_REG,  NPU2_SMU, MP1_C2PMSG_60),
+	},
+	.hw_ops	=	 {
+		.set_dpm = npu4_set_dpm,
+	},
+};
+
+const struct amdxdna_dev_info dev_npu2_info = {
+	.reg_bar           = NPU2_REG_BAR_INDEX,
+	.mbox_bar          = NPU2_MBOX_BAR_INDEX,
+	.sram_bar          = NPU2_SRAM_BAR_INDEX,
+	.psp_bar           = NPU2_PSP_BAR_INDEX,
+	.smu_bar           = NPU2_SMU_BAR_INDEX,
+	.first_col         = 0,
+	.dev_mem_buf_shift = 15, /* 32 KiB aligned */
+	.dev_mem_base      = AIE2_DEVM_BASE,
+	.dev_mem_size      = AIE2_DEVM_SIZE,
+	.vbnv              = "RyzenAI-npu2",
+	.device_type       = AMDXDNA_DEV_TYPE_KMQ,
+	.dev_priv          = &npu2_dev_priv,
+	.ops               = &aie2_ops, /* NPU2 can share NPU1's callback */
+};
diff --git a/drivers/accel/amdxdna/npu4_regs.c b/drivers/accel/amdxdna/npu4_regs.c
new file mode 100644
index 000000000000..986a5f28ba24
--- /dev/null
+++ b/drivers/accel/amdxdna/npu4_regs.c
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023-2024, Advanced Micro Devices, Inc.
+ */
+
+#include <drm/amdxdna_accel.h>
+#include <drm/drm_device.h>
+#include <drm/gpu_scheduler.h>
+#include <linux/sizes.h>
+
+#include "aie2_pci.h"
+#include "amdxdna_mailbox.h"
+#include "amdxdna_pci_drv.h"
+
+/* NPU Public Registers on MpNPUAxiXbar (refer to Diag npu_registers.h) */
+#define MPNPU_PUB_SEC_INTR             0x3010060
+#define MPNPU_PUB_PWRMGMT_INTR         0x3010064
+#define MPNPU_PUB_SCRATCH0             0x301006C
+#define MPNPU_PUB_SCRATCH1             0x3010070
+#define MPNPU_PUB_SCRATCH2             0x3010074
+#define MPNPU_PUB_SCRATCH3             0x3010078
+#define MPNPU_PUB_SCRATCH4             0x301007C
+#define MPNPU_PUB_SCRATCH5             0x3010080
+#define MPNPU_PUB_SCRATCH6             0x3010084
+#define MPNPU_PUB_SCRATCH7             0x3010088
+#define MPNPU_PUB_SCRATCH8             0x301008C
+#define MPNPU_PUB_SCRATCH9             0x3010090
+#define MPNPU_PUB_SCRATCH10            0x3010094
+#define MPNPU_PUB_SCRATCH11            0x3010098
+#define MPNPU_PUB_SCRATCH12            0x301009C
+#define MPNPU_PUB_SCRATCH13            0x30100A0
+#define MPNPU_PUB_SCRATCH14            0x30100A4
+#define MPNPU_PUB_SCRATCH15            0x30100A8
+#define MP0_C2PMSG_73                  0x3810A24
+#define MP0_C2PMSG_123                 0x3810AEC
+
+#define MP1_C2PMSG_0                   0x3B10900
+#define MP1_C2PMSG_60                  0x3B109F0
+#define MP1_C2PMSG_61                  0x3B109F4
+
+#define MPNPU_SRAM_X2I_MAILBOX_0       0x3600000
+#define MPNPU_SRAM_X2I_MAILBOX_15      0x361E000
+#define MPNPU_SRAM_X2I_MAILBOX_31      0x363E000
+#define MPNPU_SRAM_I2X_MAILBOX_31      0x363F000
+
+#define MMNPU_APERTURE0_BASE           0x3000000
+#define MMNPU_APERTURE1_BASE           0x3600000
+#define MMNPU_APERTURE3_BASE           0x3810000
+#define MMNPU_APERTURE4_BASE           0x3B10000
+
+/* PCIe BAR Index for NPU4 */
+#define NPU4_REG_BAR_INDEX	0
+#define NPU4_MBOX_BAR_INDEX	0
+#define NPU4_PSP_BAR_INDEX	4
+#define NPU4_SMU_BAR_INDEX	5
+#define NPU4_SRAM_BAR_INDEX	2
+/* Associated BARs and Apertures */
+#define NPU4_REG_BAR_BASE	MMNPU_APERTURE0_BASE
+#define NPU4_MBOX_BAR_BASE	MMNPU_APERTURE0_BASE
+#define NPU4_PSP_BAR_BASE	MMNPU_APERTURE3_BASE
+#define NPU4_SMU_BAR_BASE	MMNPU_APERTURE4_BASE
+#define NPU4_SRAM_BAR_BASE	MMNPU_APERTURE1_BASE
+
+const struct rt_config npu4_default_rt_cfg[] = {
+	{ 5, 1, AIE2_RT_CFG_INIT }, /* PDI APP LOAD MODE */
+	{ 10, 1, AIE2_RT_CFG_INIT }, /* DEBUG BUF */
+	{ 14, 0, AIE2_RT_CFG_INIT, BIT_U64(AIE2_PREEMPT) }, /* Frame boundary preemption */
+	{ 1, 1, AIE2_RT_CFG_CLK_GATING }, /* Clock gating on */
+	{ 2, 1, AIE2_RT_CFG_CLK_GATING }, /* Clock gating on */
+	{ 3, 1, AIE2_RT_CFG_CLK_GATING }, /* Clock gating on */
+	{ 4, 1, AIE2_RT_CFG_CLK_GATING }, /* Clock gating on */
+	{ 13, 0, AIE2_RT_CFG_FORCE_PREEMPT },
+	{ 14, 0, AIE2_RT_CFG_FRAME_BOUNDARY_PREEMPT },
+	{ 0 },
+};
+
+const struct dpm_clk_freq npu4_dpm_clk_table[] = {
+	{396, 792},
+	{600, 1056},
+	{792, 1152},
+	{975, 1267},
+	{975, 1267},
+	{1056, 1408},
+	{1152, 1584},
+	{1267, 1800},
+	{ 0 }
+};
+
+const struct aie2_fw_feature_tbl npu4_fw_feature_table[] = {
+	{ .feature = AIE2_NPU_COMMAND, .min_minor = 15 },
+	{ .feature = AIE2_PREEMPT, .min_minor = 12 },
+	{ 0 }
+};
+
+static const struct amdxdna_dev_priv npu4_dev_priv = {
+	.fw_path        = "amdnpu/17f0_10/npu.sbin",
+	.protocol_major = 0x6,
+	.protocol_minor = 12,
+	.rt_config	= npu4_default_rt_cfg,
+	.dpm_clk_tbl	= npu4_dpm_clk_table,
+	.fw_feature_tbl = npu4_fw_feature_table,
+	.col_align	= COL_ALIGN_NATURE,
+	.mbox_dev_addr  = NPU4_MBOX_BAR_BASE,
+	.mbox_size      = 0, /* Use BAR size */
+	.sram_dev_addr  = NPU4_SRAM_BAR_BASE,
+	.hwctx_limit    = 16,
+	.sram_offs      = {
+		DEFINE_BAR_OFFSET(MBOX_CHANN_OFF, NPU4_SRAM, MPNPU_SRAM_X2I_MAILBOX_0),
+		DEFINE_BAR_OFFSET(FW_ALIVE_OFF,   NPU4_SRAM, MPNPU_SRAM_X2I_MAILBOX_15),
+	},
+	.psp_regs_off   = {
+		DEFINE_BAR_OFFSET(PSP_CMD_REG,    NPU4_PSP, MP0_C2PMSG_123),
+		DEFINE_BAR_OFFSET(PSP_ARG0_REG,   NPU4_REG, MPNPU_PUB_SCRATCH3),
+		DEFINE_BAR_OFFSET(PSP_ARG1_REG,   NPU4_REG, MPNPU_PUB_SCRATCH4),
+		DEFINE_BAR_OFFSET(PSP_ARG2_REG,   NPU4_REG, MPNPU_PUB_SCRATCH9),
+		DEFINE_BAR_OFFSET(PSP_INTR_REG,   NPU4_PSP, MP0_C2PMSG_73),
+		DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU4_PSP, MP0_C2PMSG_123),
+		DEFINE_BAR_OFFSET(PSP_RESP_REG,   NPU4_REG, MPNPU_PUB_SCRATCH3),
+	},
+	.smu_regs_off   = {
+		DEFINE_BAR_OFFSET(SMU_CMD_REG,  NPU4_SMU, MP1_C2PMSG_0),
+		DEFINE_BAR_OFFSET(SMU_ARG_REG,  NPU4_SMU, MP1_C2PMSG_60),
+		DEFINE_BAR_OFFSET(SMU_INTR_REG, NPU4_SMU, MMNPU_APERTURE4_BASE),
+		DEFINE_BAR_OFFSET(SMU_RESP_REG, NPU4_SMU, MP1_C2PMSG_61),
+		DEFINE_BAR_OFFSET(SMU_OUT_REG,  NPU4_SMU, MP1_C2PMSG_60),
+	},
+	.hw_ops		= {
+		.set_dpm = npu4_set_dpm,
+	},
+};
+
+const struct amdxdna_dev_info dev_npu4_info = {
+	.reg_bar           = NPU4_REG_BAR_INDEX,
+	.mbox_bar          = NPU4_MBOX_BAR_INDEX,
+	.sram_bar          = NPU4_SRAM_BAR_INDEX,
+	.psp_bar           = NPU4_PSP_BAR_INDEX,
+	.smu_bar           = NPU4_SMU_BAR_INDEX,
+	.first_col         = 0,
+	.dev_mem_buf_shift = 15, /* 32 KiB aligned */
+	.dev_mem_base      = AIE2_DEVM_BASE,
+	.dev_mem_size      = AIE2_DEVM_SIZE,
+	.vbnv              = "RyzenAI-npu4",
+	.device_type       = AMDXDNA_DEV_TYPE_KMQ,
+	.dev_priv          = &npu4_dev_priv,
+	.ops               = &aie2_ops, /* NPU4 can share NPU1's callback */
+};
diff --git a/drivers/accel/amdxdna/npu5_regs.c b/drivers/accel/amdxdna/npu5_regs.c
new file mode 100644
index 000000000000..75ad97f0b937
--- /dev/null
+++ b/drivers/accel/amdxdna/npu5_regs.c
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024, Advanced Micro Devices, Inc.
+ */
+
+#include <drm/amdxdna_accel.h>
+#include <drm/drm_device.h>
+#include <drm/gpu_scheduler.h>
+#include <linux/sizes.h>
+
+#include "aie2_pci.h"
+#include "amdxdna_mailbox.h"
+#include "amdxdna_pci_drv.h"
+
+/* NPU Public Registers on MpNPUAxiXbar (refer to Diag npu_registers.h) */
+#define MPNPU_PUB_SEC_INTR             0x3010060
+#define MPNPU_PUB_PWRMGMT_INTR         0x3010064
+#define MPNPU_PUB_SCRATCH0             0x301006C
+#define MPNPU_PUB_SCRATCH1             0x3010070
+#define MPNPU_PUB_SCRATCH2             0x3010074
+#define MPNPU_PUB_SCRATCH3             0x3010078
+#define MPNPU_PUB_SCRATCH4             0x301007C
+#define MPNPU_PUB_SCRATCH5             0x3010080
+#define MPNPU_PUB_SCRATCH6             0x3010084
+#define MPNPU_PUB_SCRATCH7             0x3010088
+#define MPNPU_PUB_SCRATCH8             0x301008C
+#define MPNPU_PUB_SCRATCH9             0x3010090
+#define MPNPU_PUB_SCRATCH10            0x3010094
+#define MPNPU_PUB_SCRATCH11            0x3010098
+#define MPNPU_PUB_SCRATCH12            0x301009C
+#define MPNPU_PUB_SCRATCH13            0x30100A0
+#define MPNPU_PUB_SCRATCH14            0x30100A4
+#define MPNPU_PUB_SCRATCH15            0x30100A8
+#define MP0_C2PMSG_73                  0x3810A24
+#define MP0_C2PMSG_123                 0x3810AEC
+
+#define MP1_C2PMSG_0                   0x3B10900
+#define MP1_C2PMSG_60                  0x3B109F0
+#define MP1_C2PMSG_61                  0x3B109F4
+
+#define MPNPU_SRAM_X2I_MAILBOX_0       0x3600000
+#define MPNPU_SRAM_X2I_MAILBOX_15      0x361E000
+#define MPNPU_SRAM_X2I_MAILBOX_31      0x363E000
+#define MPNPU_SRAM_I2X_MAILBOX_31      0x363F000
+
+#define MMNPU_APERTURE0_BASE           0x3000000
+#define MMNPU_APERTURE1_BASE           0x3600000
+#define MMNPU_APERTURE3_BASE           0x3810000
+#define MMNPU_APERTURE4_BASE           0x3B10000
+
+/* PCIe BAR Index for NPU5 */
+#define NPU5_REG_BAR_INDEX	0
+#define NPU5_MBOX_BAR_INDEX	0
+#define NPU5_PSP_BAR_INDEX	4
+#define NPU5_SMU_BAR_INDEX	5
+#define NPU5_SRAM_BAR_INDEX	2
+/* Associated BARs and Apertures */
+#define NPU5_REG_BAR_BASE	MMNPU_APERTURE0_BASE
+#define NPU5_MBOX_BAR_BASE	MMNPU_APERTURE0_BASE
+#define NPU5_PSP_BAR_BASE	MMNPU_APERTURE3_BASE
+#define NPU5_SMU_BAR_BASE	MMNPU_APERTURE4_BASE
+#define NPU5_SRAM_BAR_BASE	MMNPU_APERTURE1_BASE
+
+static const struct amdxdna_dev_priv npu5_dev_priv = {
+	.fw_path        = "amdnpu/17f0_11/npu.sbin",
+	.protocol_major = 0x6,
+	.protocol_minor = 12,
+	.rt_config	= npu4_default_rt_cfg,
+	.dpm_clk_tbl	= npu4_dpm_clk_table,
+	.fw_feature_tbl = npu4_fw_feature_table,
+	.col_align	= COL_ALIGN_NATURE,
+	.mbox_dev_addr  = NPU5_MBOX_BAR_BASE,
+	.mbox_size      = 0, /* Use BAR size */
+	.sram_dev_addr  = NPU5_SRAM_BAR_BASE,
+	.hwctx_limit    = 16,
+	.sram_offs      = {
+		DEFINE_BAR_OFFSET(MBOX_CHANN_OFF, NPU5_SRAM, MPNPU_SRAM_X2I_MAILBOX_0),
+		DEFINE_BAR_OFFSET(FW_ALIVE_OFF,   NPU5_SRAM, MPNPU_SRAM_X2I_MAILBOX_15),
+	},
+	.psp_regs_off   = {
+		DEFINE_BAR_OFFSET(PSP_CMD_REG,    NPU5_PSP, MP0_C2PMSG_123),
+		DEFINE_BAR_OFFSET(PSP_ARG0_REG,   NPU5_REG, MPNPU_PUB_SCRATCH3),
+		DEFINE_BAR_OFFSET(PSP_ARG1_REG,   NPU5_REG, MPNPU_PUB_SCRATCH4),
+		DEFINE_BAR_OFFSET(PSP_ARG2_REG,   NPU5_REG, MPNPU_PUB_SCRATCH9),
+		DEFINE_BAR_OFFSET(PSP_INTR_REG,   NPU5_PSP, MP0_C2PMSG_73),
+		DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU5_PSP, MP0_C2PMSG_123),
+		DEFINE_BAR_OFFSET(PSP_RESP_REG,   NPU5_REG, MPNPU_PUB_SCRATCH3),
+	},
+	.smu_regs_off   = {
+		DEFINE_BAR_OFFSET(SMU_CMD_REG,  NPU5_SMU, MP1_C2PMSG_0),
+		DEFINE_BAR_OFFSET(SMU_ARG_REG,  NPU5_SMU, MP1_C2PMSG_60),
+		DEFINE_BAR_OFFSET(SMU_INTR_REG, NPU5_SMU, MMNPU_APERTURE4_BASE),
+		DEFINE_BAR_OFFSET(SMU_RESP_REG, NPU5_SMU, MP1_C2PMSG_61),
+		DEFINE_BAR_OFFSET(SMU_OUT_REG,  NPU5_SMU, MP1_C2PMSG_60),
+	},
+	.hw_ops		= {
+		.set_dpm = npu4_set_dpm,
+	},
+};
+
+const struct amdxdna_dev_info dev_npu5_info = {
+	.reg_bar           = NPU5_REG_BAR_INDEX,
+	.mbox_bar          = NPU5_MBOX_BAR_INDEX,
+	.sram_bar          = NPU5_SRAM_BAR_INDEX,
+	.psp_bar           = NPU5_PSP_BAR_INDEX,
+	.smu_bar           = NPU5_SMU_BAR_INDEX,
+	.first_col         = 0,
+	.dev_mem_buf_shift = 15, /* 32 KiB aligned */
+	.dev_mem_base      = AIE2_DEVM_BASE,
+	.dev_mem_size      = AIE2_DEVM_SIZE,
+	.vbnv              = "RyzenAI-npu5",
+	.device_type       = AMDXDNA_DEV_TYPE_KMQ,
+	.dev_priv          = &npu5_dev_priv,
+	.ops               = &aie2_ops,
+};
diff --git a/drivers/accel/amdxdna/npu6_regs.c b/drivers/accel/amdxdna/npu6_regs.c
new file mode 100644
index 000000000000..758dc013fe13
--- /dev/null
+++ b/drivers/accel/amdxdna/npu6_regs.c
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024, Advanced Micro Devices, Inc.
+ */
+
+#include <drm/amdxdna_accel.h>
+#include <drm/drm_device.h>
+#include <drm/gpu_scheduler.h>
+#include <linux/sizes.h>
+
+#include "aie2_pci.h"
+#include "amdxdna_mailbox.h"
+#include "amdxdna_pci_drv.h"
+
+/* NPU Public Registers on MpNPUAxiXbar (refer to Diag npu_registers.h) */
+#define MPNPU_PUB_SEC_INTR             0x3010060
+#define MPNPU_PUB_PWRMGMT_INTR         0x3010064
+#define MPNPU_PUB_SCRATCH0             0x301006C
+#define MPNPU_PUB_SCRATCH1             0x3010070
+#define MPNPU_PUB_SCRATCH2             0x3010074
+#define MPNPU_PUB_SCRATCH3             0x3010078
+#define MPNPU_PUB_SCRATCH4             0x301007C
+#define MPNPU_PUB_SCRATCH5             0x3010080
+#define MPNPU_PUB_SCRATCH6             0x3010084
+#define MPNPU_PUB_SCRATCH7             0x3010088
+#define MPNPU_PUB_SCRATCH8             0x301008C
+#define MPNPU_PUB_SCRATCH9             0x3010090
+#define MPNPU_PUB_SCRATCH10            0x3010094
+#define MPNPU_PUB_SCRATCH11            0x3010098
+#define MPNPU_PUB_SCRATCH12            0x301009C
+#define MPNPU_PUB_SCRATCH13            0x30100A0
+#define MPNPU_PUB_SCRATCH14            0x30100A4
+#define MPNPU_PUB_SCRATCH15            0x30100A8
+#define MP0_C2PMSG_73                  0x3810A24
+#define MP0_C2PMSG_123                 0x3810AEC
+
+#define MP1_C2PMSG_0                   0x3B10900
+#define MP1_C2PMSG_60                  0x3B109F0
+#define MP1_C2PMSG_61                  0x3B109F4
+
+#define MPNPU_SRAM_X2I_MAILBOX_0       0x3600000
+#define MPNPU_SRAM_X2I_MAILBOX_15      0x361E000
+#define MPNPU_SRAM_X2I_MAILBOX_31      0x363E000
+#define MPNPU_SRAM_I2X_MAILBOX_31      0x363F000
+
+#define MMNPU_APERTURE0_BASE           0x3000000
+#define MMNPU_APERTURE1_BASE           0x3600000
+#define MMNPU_APERTURE3_BASE           0x3810000
+#define MMNPU_APERTURE4_BASE           0x3B10000
+
+/* PCIe BAR Index for NPU6 */
+#define NPU6_REG_BAR_INDEX	0
+#define NPU6_MBOX_BAR_INDEX	0
+#define NPU6_PSP_BAR_INDEX	4
+#define NPU6_SMU_BAR_INDEX	5
+#define NPU6_SRAM_BAR_INDEX	2
+/* Associated BARs and Apertures */
+#define NPU6_REG_BAR_BASE	MMNPU_APERTURE0_BASE
+#define NPU6_MBOX_BAR_BASE	MMNPU_APERTURE0_BASE
+#define NPU6_PSP_BAR_BASE	MMNPU_APERTURE3_BASE
+#define NPU6_SMU_BAR_BASE	MMNPU_APERTURE4_BASE
+#define NPU6_SRAM_BAR_BASE	MMNPU_APERTURE1_BASE
+
+static const struct amdxdna_dev_priv npu6_dev_priv = {
+	.fw_path        = "amdnpu/17f0_10/npu.sbin",
+	.protocol_major = 0x6,
+	.protocol_minor = 12,
+	.rt_config	= npu4_default_rt_cfg,
+	.dpm_clk_tbl	= npu4_dpm_clk_table,
+	.fw_feature_tbl = npu4_fw_feature_table,
+	.col_align	= COL_ALIGN_NATURE,
+	.mbox_dev_addr  = NPU6_MBOX_BAR_BASE,
+	.mbox_size      = 0, /* Use BAR size */
+	.sram_dev_addr  = NPU6_SRAM_BAR_BASE,
+	.hwctx_limit    = 16,
+	.sram_offs      = {
+		DEFINE_BAR_OFFSET(MBOX_CHANN_OFF, NPU6_SRAM, MPNPU_SRAM_X2I_MAILBOX_0),
+		DEFINE_BAR_OFFSET(FW_ALIVE_OFF,   NPU6_SRAM, MPNPU_SRAM_X2I_MAILBOX_15),
+	},
+	.psp_regs_off   = {
+		DEFINE_BAR_OFFSET(PSP_CMD_REG,    NPU6_PSP, MP0_C2PMSG_123),
+		DEFINE_BAR_OFFSET(PSP_ARG0_REG,   NPU6_REG, MPNPU_PUB_SCRATCH3),
+		DEFINE_BAR_OFFSET(PSP_ARG1_REG,   NPU6_REG, MPNPU_PUB_SCRATCH4),
+		DEFINE_BAR_OFFSET(PSP_ARG2_REG,   NPU6_REG, MPNPU_PUB_SCRATCH9),
+		DEFINE_BAR_OFFSET(PSP_INTR_REG,   NPU6_PSP, MP0_C2PMSG_73),
+		DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU6_PSP, MP0_C2PMSG_123),
+		DEFINE_BAR_OFFSET(PSP_RESP_REG,   NPU6_REG, MPNPU_PUB_SCRATCH3),
+	},
+	.smu_regs_off   = {
+		DEFINE_BAR_OFFSET(SMU_CMD_REG,  NPU6_SMU, MP1_C2PMSG_0),
+		DEFINE_BAR_OFFSET(SMU_ARG_REG,  NPU6_SMU, MP1_C2PMSG_60),
+		DEFINE_BAR_OFFSET(SMU_INTR_REG, NPU6_SMU, MMNPU_APERTURE4_BASE),
+		DEFINE_BAR_OFFSET(SMU_RESP_REG, NPU6_SMU, MP1_C2PMSG_61),
+		DEFINE_BAR_OFFSET(SMU_OUT_REG,  NPU6_SMU, MP1_C2PMSG_60),
+	},
+	.hw_ops         = {
+		.set_dpm = npu4_set_dpm,
+	},
+
+};
+
+const struct amdxdna_dev_info dev_npu6_info = {
+	.reg_bar           = NPU6_REG_BAR_INDEX,
+	.mbox_bar          = NPU6_MBOX_BAR_INDEX,
+	.sram_bar          = NPU6_SRAM_BAR_INDEX,
+	.psp_bar           = NPU6_PSP_BAR_INDEX,
+	.smu_bar           = NPU6_SMU_BAR_INDEX,
+	.first_col         = 0,
+	.dev_mem_buf_shift = 15, /* 32 KiB aligned */
+	.dev_mem_base      = AIE2_DEVM_BASE,
+	.dev_mem_size      = AIE2_DEVM_SIZE,
+	.vbnv              = "RyzenAI-npu6",
+	.device_type       = AMDXDNA_DEV_TYPE_KMQ,
+	.dev_priv          = &npu6_dev_priv,
+	.ops               = &aie2_ops,
+};
diff --git a/drivers/accel/drm_accel.c b/drivers/accel/drm_accel.c
new file mode 100644
index 000000000000..ca3357acd127
--- /dev/null
+++ b/drivers/accel/drm_accel.c
@@ -0,0 +1,208 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Copyright 2022 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+#include <linux/debugfs.h>
+#include <linux/device.h>
+#include <linux/xarray.h>
+
+#include <drm/drm_accel.h>
+#include <drm/drm_auth.h>
+#include <drm/drm_debugfs.h>
+#include <drm/drm_drv.h>
+#include <drm/drm_file.h>
+#include <drm/drm_ioctl.h>
+#include <drm/drm_print.h>
+
+DEFINE_XARRAY_ALLOC(accel_minors_xa);
+
+static const struct device_type accel_sysfs_device_minor = {
+	.name = "accel_minor"
+};
+
+static char *accel_devnode(const struct device *dev, umode_t *mode)
+{
+	return kasprintf(GFP_KERNEL, "accel/%s", dev_name(dev));
+}
+
+static const struct class accel_class = {
+	.name = "accel",
+	.devnode = accel_devnode,
+};
+
+static int accel_sysfs_init(void)
+{
+	return class_register(&accel_class);
+}
+
+static void accel_sysfs_destroy(void)
+{
+	class_unregister(&accel_class);
+}
+
+static int accel_name_info(struct seq_file *m, void *data)
+{
+	struct drm_info_node *node = (struct drm_info_node *) m->private;
+	struct drm_minor *minor = node->minor;
+	struct drm_device *dev = minor->dev;
+	struct drm_master *master;
+
+	mutex_lock(&dev->master_mutex);
+	master = dev->master;
+	seq_printf(m, "%s", dev->driver->name);
+	if (dev->dev)
+		seq_printf(m, " dev=%s", dev_name(dev->dev));
+	if (master && master->unique)
+		seq_printf(m, " master=%s", master->unique);
+	if (dev->unique)
+		seq_printf(m, " unique=%s", dev->unique);
+	seq_puts(m, "\n");
+	mutex_unlock(&dev->master_mutex);
+
+	return 0;
+}
+
+static const struct drm_info_list accel_debugfs_list[] = {
+	{"name", accel_name_info, 0}
+};
+#define ACCEL_DEBUGFS_ENTRIES ARRAY_SIZE(accel_debugfs_list)
+
+/**
+ * accel_debugfs_register() - Register debugfs for device
+ * @dev: Pointer to the device instance.
+ *
+ * Creates common files for accelerators.
+ */
+void accel_debugfs_register(struct drm_device *dev)
+{
+	struct drm_minor *minor = dev->accel;
+
+	minor->debugfs_root = dev->debugfs_root;
+
+	drm_debugfs_create_files(accel_debugfs_list, ACCEL_DEBUGFS_ENTRIES,
+				 dev->debugfs_root, minor);
+}
+
+/**
+ * accel_set_device_instance_params() - Set some device parameters for accel device
+ * @kdev: Pointer to the device instance.
+ * @index: The minor's index
+ *
+ * This function creates the dev_t of the device using the accel major and
+ * the device's minor number. In addition, it sets the class and type of the
+ * device instance to the accel sysfs class and device type, respectively.
+ */
+void accel_set_device_instance_params(struct device *kdev, int index)
+{
+	kdev->devt = MKDEV(ACCEL_MAJOR, index);
+	kdev->class = &accel_class;
+	kdev->type = &accel_sysfs_device_minor;
+}
+
+/**
+ * accel_open - open method for ACCEL file
+ * @inode: device inode
+ * @filp: file pointer.
+ *
+ * This function must be used by drivers as their &file_operations.open method.
+ * It looks up the correct ACCEL device and instantiates all the per-file
+ * resources for it. It also calls the &drm_driver.open driver callback.
+ *
+ * Return: 0 on success or negative errno value on failure.
+ */
+int accel_open(struct inode *inode, struct file *filp)
+{
+	struct drm_device *dev;
+	struct drm_minor *minor;
+	int retcode;
+
+	minor = drm_minor_acquire(&accel_minors_xa, iminor(inode));
+	if (IS_ERR(minor))
+		return PTR_ERR(minor);
+
+	dev = minor->dev;
+
+	atomic_fetch_inc(&dev->open_count);
+
+	/* share address_space across all char-devs of a single device */
+	filp->f_mapping = dev->anon_inode->i_mapping;
+
+	retcode = drm_open_helper(filp, minor);
+	if (retcode)
+		goto err_undo;
+
+	return 0;
+
+err_undo:
+	atomic_dec(&dev->open_count);
+	drm_minor_release(minor);
+	return retcode;
+}
+EXPORT_SYMBOL_GPL(accel_open);
+
+static int accel_stub_open(struct inode *inode, struct file *filp)
+{
+	const struct file_operations *new_fops;
+	struct drm_minor *minor;
+	int err;
+
+	minor = drm_minor_acquire(&accel_minors_xa, iminor(inode));
+	if (IS_ERR(minor))
+		return PTR_ERR(minor);
+
+	new_fops = fops_get(minor->dev->driver->fops);
+	if (!new_fops) {
+		err = -ENODEV;
+		goto out;
+	}
+
+	replace_fops(filp, new_fops);
+	if (filp->f_op->open)
+		err = filp->f_op->open(inode, filp);
+	else
+		err = 0;
+
+out:
+	drm_minor_release(minor);
+
+	return err;
+}
+
+static const struct file_operations accel_stub_fops = {
+	.owner = THIS_MODULE,
+	.open = accel_stub_open,
+	.llseek = noop_llseek,
+};
+
+void accel_core_exit(void)
+{
+	unregister_chrdev(ACCEL_MAJOR, "accel");
+	accel_sysfs_destroy();
+	WARN_ON(!xa_empty(&accel_minors_xa));
+}
+
+int __init accel_core_init(void)
+{
+	int ret;
+
+	ret = accel_sysfs_init();
+	if (ret < 0) {
+		DRM_ERROR("Cannot create ACCEL class: %d\n", ret);
+		goto error;
+	}
+
+	ret = register_chrdev(ACCEL_MAJOR, "accel", &accel_stub_fops);
+	if (ret < 0)
+		DRM_ERROR("Cannot register ACCEL major: %d\n", ret);
+
+error:
+	/*
+	 * Any cleanup due to errors will be done in drm_core_exit() that
+	 * will call accel_core_exit()
+	 */
+	return ret;
+}
diff --git a/drivers/accel/ethosu/Kconfig b/drivers/accel/ethosu/Kconfig
new file mode 100644
index 000000000000..d25f9b3eb317
--- /dev/null
+++ b/drivers/accel/ethosu/Kconfig
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config DRM_ACCEL_ARM_ETHOSU
+	tristate "Arm Ethos-U65/U85 NPU"
+	depends on HAS_IOMEM
+	depends on DRM_ACCEL
+	select DRM_GEM_DMA_HELPER
+	select DRM_SCHED
+	select GENERIC_ALLOCATOR
+	help
+	  Enables driver for Arm Ethos-U65/U85 NPUs
diff --git a/drivers/accel/ethosu/Makefile b/drivers/accel/ethosu/Makefile
new file mode 100644
index 000000000000..17db5a600416
--- /dev/null
+++ b/drivers/accel/ethosu/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+obj-$(CONFIG_DRM_ACCEL_ARM_ETHOSU) := ethosu.o
+ethosu-y += ethosu_drv.o ethosu_gem.o ethosu_job.o
diff --git a/drivers/accel/ethosu/ethosu_device.h b/drivers/accel/ethosu/ethosu_device.h
new file mode 100644
index 000000000000..b189fa783d6a
--- /dev/null
+++ b/drivers/accel/ethosu/ethosu_device.h
@@ -0,0 +1,197 @@
+/* SPDX-License-Identifier: GPL-2.0-only or MIT */
+/* Copyright 2025 Arm, Ltd. */
+
+#ifndef __ETHOSU_DEVICE_H__
+#define __ETHOSU_DEVICE_H__
+
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+#include <linux/types.h>
+
+#include <drm/drm_device.h>
+#include <drm/gpu_scheduler.h>
+
+#include <drm/ethosu_accel.h>
+
+struct clk;
+struct gen_pool;
+
+#define NPU_REG_ID		0x0000
+#define NPU_REG_STATUS		0x0004
+#define NPU_REG_CMD		0x0008
+#define NPU_REG_RESET		0x000c
+#define NPU_REG_QBASE		0x0010
+#define NPU_REG_QBASE_HI	0x0014
+#define NPU_REG_QREAD		0x0018
+#define NPU_REG_QCONFIG		0x001c
+#define NPU_REG_QSIZE		0x0020
+#define NPU_REG_PROT		0x0024
+#define NPU_REG_CONFIG		0x0028
+#define NPU_REG_REGIONCFG	0x003c
+#define NPU_REG_AXILIMIT0	0x0040		// U65
+#define NPU_REG_AXILIMIT1	0x0044		// U65
+#define NPU_REG_AXILIMIT2	0x0048		// U65
+#define NPU_REG_AXILIMIT3	0x004c		// U65
+#define NPU_REG_MEM_ATTR0	0x0040		// U85
+#define NPU_REG_MEM_ATTR1	0x0044		// U85
+#define NPU_REG_MEM_ATTR2	0x0048		// U85
+#define NPU_REG_MEM_ATTR3	0x004c		// U85
+#define NPU_REG_AXI_SRAM	0x0050		// U85
+#define NPU_REG_AXI_EXT		0x0054		// U85
+
+#define NPU_REG_BASEP(x)	(0x0080 + (x) * 8)
+#define NPU_REG_BASEP_HI(x)	(0x0084 + (x) * 8)
+#define NPU_BASEP_REGION_MAX	8
+
+#define ID_ARCH_MAJOR_MASK	GENMASK(31, 28)
+#define ID_ARCH_MINOR_MASK	GENMASK(27, 20)
+#define ID_ARCH_PATCH_MASK	GENMASK(19, 16)
+#define ID_VER_MAJOR_MASK	GENMASK(11, 8)
+#define ID_VER_MINOR_MASK	GENMASK(7, 4)
+
+#define CONFIG_MACS_PER_CC_MASK	GENMASK(3, 0)
+#define CONFIG_CMD_STREAM_VER_MASK	GENMASK(7, 4)
+
+#define STATUS_STATE_RUNNING	BIT(0)
+#define STATUS_IRQ_RAISED	BIT(1)
+#define STATUS_BUS_STATUS	BIT(2)
+#define STATUS_RESET_STATUS	BIT(3)
+#define STATUS_CMD_PARSE_ERR	BIT(4)
+#define STATUS_CMD_END_REACHED	BIT(5)
+
+#define CMD_CLEAR_IRQ		BIT(1)
+#define CMD_TRANSITION_TO_RUN	BIT(0)
+
+#define RESET_PENDING_CSL	BIT(1)
+#define RESET_PENDING_CPL	BIT(0)
+
+#define PROT_ACTIVE_CSL		BIT(1)
+
+enum ethosu_cmds {
+	NPU_OP_CONV = 0x2,
+	NPU_OP_DEPTHWISE = 0x3,
+	NPU_OP_POOL = 0x5,
+	NPU_OP_ELEMENTWISE = 0x6,
+	NPU_OP_RESIZE = 0x7,	// U85 only
+	NPU_OP_DMA_START = 0x10,
+	NPU_SET_IFM_PAD_TOP = 0x100,
+	NPU_SET_IFM_PAD_LEFT = 0x101,
+	NPU_SET_IFM_PAD_RIGHT = 0x102,
+	NPU_SET_IFM_PAD_BOTTOM = 0x103,
+	NPU_SET_IFM_DEPTH_M1 = 0x104,
+	NPU_SET_IFM_PRECISION = 0x105,
+	NPU_SET_IFM_BROADCAST = 0x108,
+	NPU_SET_IFM_WIDTH0_M1 = 0x10a,
+	NPU_SET_IFM_HEIGHT0_M1 = 0x10b,
+	NPU_SET_IFM_HEIGHT1_M1 = 0x10c,
+	NPU_SET_IFM_REGION = 0x10f,
+	NPU_SET_OFM_WIDTH_M1 = 0x111,
+	NPU_SET_OFM_HEIGHT_M1 = 0x112,
+	NPU_SET_OFM_DEPTH_M1 = 0x113,
+	NPU_SET_OFM_PRECISION = 0x114,
+	NPU_SET_OFM_WIDTH0_M1 = 0x11a,
+	NPU_SET_OFM_HEIGHT0_M1 = 0x11b,
+	NPU_SET_OFM_HEIGHT1_M1 = 0x11c,
+	NPU_SET_OFM_REGION = 0x11f,
+	NPU_SET_KERNEL_WIDTH_M1 = 0x120,
+	NPU_SET_KERNEL_HEIGHT_M1 = 0x121,
+	NPU_SET_KERNEL_STRIDE = 0x122,
+	NPU_SET_WEIGHT_REGION = 0x128,
+	NPU_SET_SCALE_REGION = 0x129,
+	NPU_SET_DMA0_SRC_REGION = 0x130,
+	NPU_SET_DMA0_DST_REGION = 0x131,
+	NPU_SET_DMA0_SIZE0 = 0x132,
+	NPU_SET_DMA0_SIZE1 = 0x133,
+	NPU_SET_IFM2_BROADCAST = 0x180,
+	NPU_SET_IFM2_PRECISION = 0x185,
+	NPU_SET_IFM2_WIDTH0_M1 = 0x18a,
+	NPU_SET_IFM2_HEIGHT0_M1 = 0x18b,
+	NPU_SET_IFM2_HEIGHT1_M1 = 0x18c,
+	NPU_SET_IFM2_REGION = 0x18f,
+	NPU_SET_IFM_BASE0 = 0x4000,
+	NPU_SET_IFM_BASE1 = 0x4001,
+	NPU_SET_IFM_BASE2 = 0x4002,
+	NPU_SET_IFM_BASE3 = 0x4003,
+	NPU_SET_IFM_STRIDE_X = 0x4004,
+	NPU_SET_IFM_STRIDE_Y = 0x4005,
+	NPU_SET_IFM_STRIDE_C = 0x4006,
+	NPU_SET_OFM_BASE0 = 0x4010,
+	NPU_SET_OFM_BASE1 = 0x4011,
+	NPU_SET_OFM_BASE2 = 0x4012,
+	NPU_SET_OFM_BASE3 = 0x4013,
+	NPU_SET_OFM_STRIDE_X = 0x4014,
+	NPU_SET_OFM_STRIDE_Y = 0x4015,
+	NPU_SET_OFM_STRIDE_C = 0x4016,
+	NPU_SET_WEIGHT_BASE = 0x4020,
+	NPU_SET_WEIGHT_LENGTH = 0x4021,
+	NPU_SET_SCALE_BASE = 0x4022,
+	NPU_SET_SCALE_LENGTH = 0x4023,
+	NPU_SET_DMA0_SRC = 0x4030,
+	NPU_SET_DMA0_DST = 0x4031,
+	NPU_SET_DMA0_LEN = 0x4032,
+	NPU_SET_DMA0_SRC_STRIDE0 = 0x4033,
+	NPU_SET_DMA0_SRC_STRIDE1 = 0x4034,
+	NPU_SET_DMA0_DST_STRIDE0 = 0x4035,
+	NPU_SET_DMA0_DST_STRIDE1 = 0x4036,
+	NPU_SET_IFM2_BASE0 = 0x4080,
+	NPU_SET_IFM2_BASE1 = 0x4081,
+	NPU_SET_IFM2_BASE2 = 0x4082,
+	NPU_SET_IFM2_BASE3 = 0x4083,
+	NPU_SET_IFM2_STRIDE_X = 0x4084,
+	NPU_SET_IFM2_STRIDE_Y = 0x4085,
+	NPU_SET_IFM2_STRIDE_C = 0x4086,
+	NPU_SET_WEIGHT1_BASE = 0x4090,
+	NPU_SET_WEIGHT1_LENGTH = 0x4091,
+	NPU_SET_SCALE1_BASE = 0x4092,
+	NPU_SET_WEIGHT2_BASE = 0x4092,
+	NPU_SET_SCALE1_LENGTH = 0x4093,
+	NPU_SET_WEIGHT2_LENGTH = 0x4093,
+	NPU_SET_WEIGHT3_BASE = 0x4094,
+	NPU_SET_WEIGHT3_LENGTH = 0x4095,
+};
+
+#define ETHOSU_SRAM_REGION	2	/* Matching Vela compiler */
+
+/**
+ * struct ethosu_device - Ethosu device
+ */
+struct ethosu_device {
+	/** @base: Base drm_device. */
+	struct drm_device base;
+
+	/** @iomem: CPU mapping of the registers. */
+	void __iomem *regs;
+
+	void __iomem *sram;
+	struct gen_pool *srampool;
+	dma_addr_t sramphys;
+
+	struct clk_bulk_data *clks;
+	int num_clks;
+	int irq;
+
+	struct drm_ethosu_npu_info npu_info;
+
+	struct ethosu_job *in_flight_job;
+	/* For in_flight_job and ethosu_job_hw_submit() */
+	struct mutex job_lock;
+
+	/* For dma_fence */
+	spinlock_t fence_lock;
+
+	struct drm_gpu_scheduler sched;
+	/* For ethosu_job_do_push() */
+	struct mutex sched_lock;
+	u64 fence_context;
+	u64 emit_seqno;
+};
+
+#define to_ethosu_device(drm_dev) \
+	((struct ethosu_device *)container_of(drm_dev, struct ethosu_device, base))
+
+static inline bool ethosu_is_u65(const struct ethosu_device *ethosudev)
+{
+	return FIELD_GET(ID_ARCH_MAJOR_MASK, ethosudev->npu_info.id) == 1;
+}
+
+#endif
diff --git a/drivers/accel/ethosu/ethosu_drv.c b/drivers/accel/ethosu/ethosu_drv.c
new file mode 100644
index 000000000000..e05a69bf5574
--- /dev/null
+++ b/drivers/accel/ethosu/ethosu_drv.c
@@ -0,0 +1,403 @@
+// SPDX-License-Identifier: GPL-2.0-only or MIT
+// Copyright (C) 2025 Arm, Ltd.
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/genalloc.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/mod_devicetable.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+
+#include <drm/drm_drv.h>
+#include <drm/drm_ioctl.h>
+#include <drm/drm_utils.h>
+#include <drm/drm_gem.h>
+#include <drm/drm_accel.h>
+#include <drm/ethosu_accel.h>
+
+#include "ethosu_drv.h"
+#include "ethosu_device.h"
+#include "ethosu_gem.h"
+#include "ethosu_job.h"
+
+static int ethosu_ioctl_dev_query(struct drm_device *ddev, void *data,
+				  struct drm_file *file)
+{
+	struct ethosu_device *ethosudev = to_ethosu_device(ddev);
+	struct drm_ethosu_dev_query *args = data;
+
+	if (!args->pointer) {
+		switch (args->type) {
+		case DRM_ETHOSU_DEV_QUERY_NPU_INFO:
+			args->size = sizeof(ethosudev->npu_info);
+			return 0;
+		default:
+			return -EINVAL;
+		}
+	}
+
+	switch (args->type) {
+	case DRM_ETHOSU_DEV_QUERY_NPU_INFO:
+		if (args->size < offsetofend(struct drm_ethosu_npu_info, sram_size))
+			return -EINVAL;
+		return copy_struct_to_user(u64_to_user_ptr(args->pointer),
+					   args->size,
+					   &ethosudev->npu_info,
+					   sizeof(ethosudev->npu_info), NULL);
+	default:
+		return -EINVAL;
+	}
+}
+
+#define ETHOSU_BO_FLAGS		DRM_ETHOSU_BO_NO_MMAP
+
+static int ethosu_ioctl_bo_create(struct drm_device *ddev, void *data,
+				  struct drm_file *file)
+{
+	struct drm_ethosu_bo_create *args = data;
+	int cookie, ret;
+
+	if (!drm_dev_enter(ddev, &cookie))
+		return -ENODEV;
+
+	if (!args->size || (args->flags & ~ETHOSU_BO_FLAGS)) {
+		ret = -EINVAL;
+		goto out_dev_exit;
+	}
+
+	ret = ethosu_gem_create_with_handle(file, ddev, &args->size,
+					    args->flags, &args->handle);
+
+out_dev_exit:
+	drm_dev_exit(cookie);
+	return ret;
+}
+
+static int ethosu_ioctl_bo_wait(struct drm_device *ddev, void *data,
+				struct drm_file *file)
+{
+	struct drm_ethosu_bo_wait *args = data;
+	int cookie, ret;
+	unsigned long timeout = drm_timeout_abs_to_jiffies(args->timeout_ns);
+
+	if (args->pad)
+		return -EINVAL;
+
+	if (!drm_dev_enter(ddev, &cookie))
+		return -ENODEV;
+
+	ret = drm_gem_dma_resv_wait(file, args->handle, true, timeout);
+
+	drm_dev_exit(cookie);
+	return ret;
+}
+
+static int ethosu_ioctl_bo_mmap_offset(struct drm_device *ddev, void *data,
+				       struct drm_file *file)
+{
+	struct drm_ethosu_bo_mmap_offset *args = data;
+	struct drm_gem_object *obj;
+
+	if (args->pad)
+		return -EINVAL;
+
+	obj = drm_gem_object_lookup(file, args->handle);
+	if (!obj)
+		return -ENOENT;
+
+	args->offset = drm_vma_node_offset_addr(&obj->vma_node);
+	drm_gem_object_put(obj);
+	return 0;
+}
+
+static int ethosu_ioctl_cmdstream_bo_create(struct drm_device *ddev, void *data,
+					    struct drm_file *file)
+{
+	struct drm_ethosu_cmdstream_bo_create *args = data;
+	int cookie, ret;
+
+	if (!drm_dev_enter(ddev, &cookie))
+		return -ENODEV;
+
+	if (!args->size || !args->data || args->pad || args->flags) {
+		ret = -EINVAL;
+		goto out_dev_exit;
+	}
+
+	args->flags |= DRM_ETHOSU_BO_NO_MMAP;
+
+	ret = ethosu_gem_cmdstream_create(file, ddev, args->size, args->data,
+					  args->flags, &args->handle);
+
+out_dev_exit:
+	drm_dev_exit(cookie);
+	return ret;
+}
+
+static int ethosu_open(struct drm_device *ddev, struct drm_file *file)
+{
+	int ret = 0;
+
+	if (!try_module_get(THIS_MODULE))
+		return -EINVAL;
+
+	struct ethosu_file_priv __free(kfree) *priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+	if (!priv) {
+		ret = -ENOMEM;
+		goto err_put_mod;
+	}
+	priv->edev = to_ethosu_device(ddev);
+
+	ret = ethosu_job_open(priv);
+	if (ret)
+		goto err_put_mod;
+
+	file->driver_priv = no_free_ptr(priv);
+	return 0;
+
+err_put_mod:
+	module_put(THIS_MODULE);
+	return ret;
+}
+
+static void ethosu_postclose(struct drm_device *ddev, struct drm_file *file)
+{
+	ethosu_job_close(file->driver_priv);
+	kfree(file->driver_priv);
+	module_put(THIS_MODULE);
+}
+
+static const struct drm_ioctl_desc ethosu_drm_driver_ioctls[] = {
+#define ETHOSU_IOCTL(n, func, flags) \
+	DRM_IOCTL_DEF_DRV(ETHOSU_##n, ethosu_ioctl_##func, flags)
+
+	ETHOSU_IOCTL(DEV_QUERY, dev_query, 0),
+	ETHOSU_IOCTL(BO_CREATE, bo_create, 0),
+	ETHOSU_IOCTL(BO_WAIT, bo_wait, 0),
+	ETHOSU_IOCTL(BO_MMAP_OFFSET, bo_mmap_offset, 0),
+	ETHOSU_IOCTL(CMDSTREAM_BO_CREATE, cmdstream_bo_create, 0),
+	ETHOSU_IOCTL(SUBMIT, submit, 0),
+};
+
+DEFINE_DRM_ACCEL_FOPS(ethosu_drm_driver_fops);
+
+/*
+ * Ethosu driver version:
+ * - 1.0 - initial interface
+ */
+static const struct drm_driver ethosu_drm_driver = {
+	.driver_features = DRIVER_COMPUTE_ACCEL | DRIVER_GEM,
+	.open = ethosu_open,
+	.postclose = ethosu_postclose,
+	.ioctls = ethosu_drm_driver_ioctls,
+	.num_ioctls = ARRAY_SIZE(ethosu_drm_driver_ioctls),
+	.fops = &ethosu_drm_driver_fops,
+	.name = "ethosu",
+	.desc = "Arm Ethos-U Accel driver",
+	.major = 1,
+	.minor = 0,
+
+	.gem_create_object = ethosu_gem_create_object,
+};
+
+#define U65_DRAM_AXI_LIMIT_CFG	0x1f3f0002
+#define U65_SRAM_AXI_LIMIT_CFG	0x1f3f00b0
+#define U85_AXI_EXT_CFG		0x00021f3f
+#define U85_AXI_SRAM_CFG	0x00021f3f
+#define U85_MEM_ATTR0_CFG	0x00000000
+#define U85_MEM_ATTR2_CFG	0x000000b7
+
+static int ethosu_reset(struct ethosu_device *ethosudev)
+{
+	int ret;
+	u32 reg;
+
+	writel_relaxed(RESET_PENDING_CSL, ethosudev->regs + NPU_REG_RESET);
+	ret = readl_poll_timeout(ethosudev->regs + NPU_REG_STATUS, reg,
+				 !FIELD_GET(STATUS_RESET_STATUS, reg),
+				 USEC_PER_MSEC, USEC_PER_SEC);
+	if (ret)
+		return ret;
+
+	if (!FIELD_GET(PROT_ACTIVE_CSL, readl_relaxed(ethosudev->regs + NPU_REG_PROT))) {
+		dev_warn(ethosudev->base.dev, "Could not reset to non-secure mode (PROT = %x)\n",
+			 readl_relaxed(ethosudev->regs + NPU_REG_PROT));
+	}
+
+	/*
+	 * Assign region 2 (SRAM) to AXI M0 (AXILIMIT0),
+	 * everything else to AXI M1 (AXILIMIT2)
+	 */
+	writel_relaxed(0x0000aa8a, ethosudev->regs + NPU_REG_REGIONCFG);
+	if (ethosu_is_u65(ethosudev)) {
+		writel_relaxed(U65_SRAM_AXI_LIMIT_CFG, ethosudev->regs + NPU_REG_AXILIMIT0);
+		writel_relaxed(U65_DRAM_AXI_LIMIT_CFG, ethosudev->regs + NPU_REG_AXILIMIT2);
+	} else {
+		writel_relaxed(U85_AXI_SRAM_CFG, ethosudev->regs + NPU_REG_AXI_SRAM);
+		writel_relaxed(U85_AXI_EXT_CFG, ethosudev->regs + NPU_REG_AXI_EXT);
+		writel_relaxed(U85_MEM_ATTR0_CFG, ethosudev->regs + NPU_REG_MEM_ATTR0);	// SRAM
+		writel_relaxed(U85_MEM_ATTR2_CFG, ethosudev->regs + NPU_REG_MEM_ATTR2);	// DRAM
+	}
+
+	if (ethosudev->sram)
+		memset_io(ethosudev->sram, 0, ethosudev->npu_info.sram_size);
+
+	return 0;
+}
+
+static int ethosu_device_resume(struct device *dev)
+{
+	struct ethosu_device *ethosudev = dev_get_drvdata(dev);
+	int ret;
+
+	ret = clk_bulk_prepare_enable(ethosudev->num_clks, ethosudev->clks);
+	if (ret)
+		return ret;
+
+	ret = ethosu_reset(ethosudev);
+	if (!ret)
+		return 0;
+
+	clk_bulk_disable_unprepare(ethosudev->num_clks, ethosudev->clks);
+	return ret;
+}
+
+static int ethosu_device_suspend(struct device *dev)
+{
+	struct ethosu_device *ethosudev = dev_get_drvdata(dev);
+
+	clk_bulk_disable_unprepare(ethosudev->num_clks, ethosudev->clks);
+	return 0;
+}
+
+static int ethosu_sram_init(struct ethosu_device *ethosudev)
+{
+	ethosudev->npu_info.sram_size = 0;
+
+	ethosudev->srampool = of_gen_pool_get(ethosudev->base.dev->of_node, "sram", 0);
+	if (!ethosudev->srampool)
+		return 0;
+
+	ethosudev->npu_info.sram_size = gen_pool_size(ethosudev->srampool);
+
+	ethosudev->sram = (void __iomem *)gen_pool_dma_alloc(ethosudev->srampool,
+							     ethosudev->npu_info.sram_size,
+							     &ethosudev->sramphys);
+	if (!ethosudev->sram) {
+		dev_err(ethosudev->base.dev, "failed to allocate from SRAM pool\n");
+		return -ENOMEM;
+	}
+
+	return 0;
+}
+
+static int ethosu_init(struct ethosu_device *ethosudev)
+{
+	int ret;
+	u32 id, config;
+
+	ret = ethosu_device_resume(ethosudev->base.dev);
+	if (ret)
+		return ret;
+
+	pm_runtime_set_autosuspend_delay(ethosudev->base.dev, 50);
+	pm_runtime_use_autosuspend(ethosudev->base.dev);
+	ret = devm_pm_runtime_set_active_enabled(ethosudev->base.dev);
+	if (ret)
+		return ret;
+	pm_runtime_get_noresume(ethosudev->base.dev);
+
+	ethosudev->npu_info.id = id = readl_relaxed(ethosudev->regs + NPU_REG_ID);
+	ethosudev->npu_info.config = config = readl_relaxed(ethosudev->regs + NPU_REG_CONFIG);
+
+	ethosu_sram_init(ethosudev);
+
+	dev_info(ethosudev->base.dev,
+		 "Ethos-U NPU, arch v%ld.%ld.%ld, rev r%ldp%ld, cmd stream ver%ld, %d MACs, %dKB SRAM\n",
+		 FIELD_GET(ID_ARCH_MAJOR_MASK, id),
+		 FIELD_GET(ID_ARCH_MINOR_MASK, id),
+		 FIELD_GET(ID_ARCH_PATCH_MASK, id),
+		 FIELD_GET(ID_VER_MAJOR_MASK, id),
+		 FIELD_GET(ID_VER_MINOR_MASK, id),
+		 FIELD_GET(CONFIG_CMD_STREAM_VER_MASK, config),
+		 1 << FIELD_GET(CONFIG_MACS_PER_CC_MASK, config),
+		 ethosudev->npu_info.sram_size / 1024);
+
+	return 0;
+}
+
+static int ethosu_probe(struct platform_device *pdev)
+{
+	int ret;
+	struct ethosu_device *ethosudev;
+
+	ethosudev = devm_drm_dev_alloc(&pdev->dev, &ethosu_drm_driver,
+				       struct ethosu_device, base);
+	if (IS_ERR(ethosudev))
+		return -ENOMEM;
+	platform_set_drvdata(pdev, ethosudev);
+
+	dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40));
+
+	ethosudev->regs = devm_platform_ioremap_resource(pdev, 0);
+
+	ethosudev->num_clks = devm_clk_bulk_get_all(&pdev->dev, &ethosudev->clks);
+	if (ethosudev->num_clks < 0)
+		return ethosudev->num_clks;
+
+	ret = ethosu_job_init(ethosudev);
+	if (ret)
+		return ret;
+
+	ret = ethosu_init(ethosudev);
+	if (ret)
+		return ret;
+
+	ret = drm_dev_register(&ethosudev->base, 0);
+	if (ret)
+		pm_runtime_dont_use_autosuspend(ethosudev->base.dev);
+
+	pm_runtime_put_autosuspend(ethosudev->base.dev);
+	return ret;
+}
+
+static void ethosu_remove(struct platform_device *pdev)
+{
+	struct ethosu_device *ethosudev = dev_get_drvdata(&pdev->dev);
+
+	drm_dev_unregister(&ethosudev->base);
+	ethosu_job_fini(ethosudev);
+	if (ethosudev->sram)
+		gen_pool_free(ethosudev->srampool, (unsigned long)ethosudev->sram,
+			      ethosudev->npu_info.sram_size);
+}
+
+static const struct of_device_id dt_match[] = {
+	{ .compatible = "arm,ethos-u65" },
+	{ .compatible = "arm,ethos-u85" },
+	{}
+};
+MODULE_DEVICE_TABLE(of, dt_match);
+
+static DEFINE_RUNTIME_DEV_PM_OPS(ethosu_pm_ops,
+				 ethosu_device_suspend,
+				 ethosu_device_resume,
+				 NULL);
+
+static struct platform_driver ethosu_driver = {
+	.probe = ethosu_probe,
+	.remove = ethosu_remove,
+	.driver = {
+		.name = "ethosu",
+		.pm = pm_ptr(&ethosu_pm_ops),
+		.of_match_table = dt_match,
+	},
+};
+module_platform_driver(ethosu_driver);
+
+MODULE_AUTHOR("Rob Herring <robh@kernel.org>");
+MODULE_DESCRIPTION("Arm Ethos-U Accel Driver");
+MODULE_LICENSE("Dual MIT/GPL");
diff --git a/drivers/accel/ethosu/ethosu_drv.h b/drivers/accel/ethosu/ethosu_drv.h
new file mode 100644
index 000000000000..9e21dfe94184
--- /dev/null
+++ b/drivers/accel/ethosu/ethosu_drv.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+/* Copyright 2025 Arm, Ltd. */
+#ifndef __ETHOSU_DRV_H__
+#define __ETHOSU_DRV_H__
+
+#include <drm/gpu_scheduler.h>
+
+struct ethosu_device;
+
+struct ethosu_file_priv {
+	struct ethosu_device *edev;
+	struct drm_sched_entity sched_entity;
+};
+
+#endif
diff --git a/drivers/accel/ethosu/ethosu_gem.c b/drivers/accel/ethosu/ethosu_gem.c
new file mode 100644
index 000000000000..473b5f5d7514
--- /dev/null
+++ b/drivers/accel/ethosu/ethosu_gem.c
@@ -0,0 +1,704 @@
+// SPDX-License-Identifier: GPL-2.0-only or MIT
+/* Copyright 2025 Arm, Ltd. */
+
+#include <linux/err.h>
+#include <linux/slab.h>
+
+#include <drm/ethosu_accel.h>
+
+#include "ethosu_device.h"
+#include "ethosu_gem.h"
+
+static void ethosu_gem_free_object(struct drm_gem_object *obj)
+{
+	struct ethosu_gem_object *bo = to_ethosu_bo(obj);
+
+	kfree(bo->info);
+	drm_gem_free_mmap_offset(&bo->base.base);
+	drm_gem_dma_free(&bo->base);
+}
+
+static int ethosu_gem_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma)
+{
+	struct ethosu_gem_object *bo = to_ethosu_bo(obj);
+
+	/* Don't allow mmap on objects that have the NO_MMAP flag set. */
+	if (bo->flags & DRM_ETHOSU_BO_NO_MMAP)
+		return -EINVAL;
+
+	return drm_gem_dma_object_mmap(obj, vma);
+}
+
+static const struct drm_gem_object_funcs ethosu_gem_funcs = {
+	.free = ethosu_gem_free_object,
+	.print_info = drm_gem_dma_object_print_info,
+	.get_sg_table = drm_gem_dma_object_get_sg_table,
+	.vmap = drm_gem_dma_object_vmap,
+	.mmap = ethosu_gem_mmap,
+	.vm_ops = &drm_gem_dma_vm_ops,
+};
+
+/**
+ * ethosu_gem_create_object - Implementation of driver->gem_create_object.
+ * @ddev: DRM device
+ * @size: Size in bytes of the memory the object will reference
+ *
+ * This lets the GEM helpers allocate object structs for us, and keep
+ * our BO stats correct.
+ */
+struct drm_gem_object *ethosu_gem_create_object(struct drm_device *ddev, size_t size)
+{
+	struct ethosu_gem_object *obj;
+
+	obj = kzalloc(sizeof(*obj), GFP_KERNEL);
+	if (!obj)
+		return ERR_PTR(-ENOMEM);
+
+	obj->base.base.funcs = &ethosu_gem_funcs;
+	return &obj->base.base;
+}
+
+/**
+ * ethosu_gem_create_with_handle() - Create a GEM object and attach it to a handle.
+ * @file: DRM file.
+ * @ddev: DRM device.
+ * @size: Size of the GEM object to allocate.
+ * @flags: Combination of drm_ethosu_bo_flags flags.
+ * @handle: Pointer holding the handle pointing to the new GEM object.
+ *
+ * Return: Zero on success
+ */
+int ethosu_gem_create_with_handle(struct drm_file *file,
+				  struct drm_device *ddev,
+				  u64 *size, u32 flags, u32 *handle)
+{
+	struct drm_gem_dma_object *mem;
+	struct ethosu_gem_object *bo;
+	int ret;
+
+	mem = drm_gem_dma_create(ddev, *size);
+	if (IS_ERR(mem))
+		return PTR_ERR(mem);
+
+	bo = to_ethosu_bo(&mem->base);
+	bo->flags = flags;
+
+	/*
+	 * Allocate an id of idr table where the obj is registered
+	 * and handle has the id what user can see.
+	 */
+	ret = drm_gem_handle_create(file, &mem->base, handle);
+	if (!ret)
+		*size = bo->base.base.size;
+
+	/* drop reference from allocate - handle holds it now. */
+	drm_gem_object_put(&mem->base);
+
+	return ret;
+}
+
+struct dma {
+	s8 region;
+	u64 len;
+	u64 offset;
+	s64 stride[2];
+};
+
+struct dma_state {
+	u16 size0;
+	u16 size1;
+	s8 mode;
+	struct dma src;
+	struct dma dst;
+};
+
+struct buffer {
+	u64 base;
+	u32 length;
+	s8 region;
+};
+
+struct feat_matrix {
+	u64 base[4];
+	s64 stride_x;
+	s64 stride_y;
+	s64 stride_c;
+	s8 region;
+	u8 broadcast;
+	u16 stride_kernel;
+	u16 precision;
+	u16 depth;
+	u16 width;
+	u16 width0;
+	u16 height[3];
+	u8 pad_top;
+	u8 pad_left;
+	u8 pad_bottom;
+	u8 pad_right;
+};
+
+struct cmd_state {
+	struct dma_state dma;
+	struct buffer scale[2];
+	struct buffer weight[4];
+	struct feat_matrix ofm;
+	struct feat_matrix ifm;
+	struct feat_matrix ifm2;
+};
+
+static void cmd_state_init(struct cmd_state *st)
+{
+	/* Initialize to all 1s to detect missing setup */
+	memset(st, 0xff, sizeof(*st));
+}
+
+static u64 cmd_to_addr(u32 *cmd)
+{
+	return ((u64)((cmd[0] & 0xff0000) << 16)) | cmd[1];
+}
+
+static u64 dma_length(struct ethosu_validated_cmdstream_info *info,
+		      struct dma_state *dma_st, struct dma *dma)
+{
+	s8 mode = dma_st->mode;
+	u64 len = dma->len;
+
+	if (mode >= 1) {
+		len += dma->stride[0];
+		len *= dma_st->size0;
+	}
+	if (mode == 2) {
+		len += dma->stride[1];
+		len *= dma_st->size1;
+	}
+	if (dma->region >= 0)
+		info->region_size[dma->region] = max(info->region_size[dma->region],
+						     len + dma->offset);
+
+	return len;
+}
+
+static u64 feat_matrix_length(struct ethosu_validated_cmdstream_info *info,
+			      struct feat_matrix *fm,
+			      u32 x, u32 y, u32 c)
+{
+	u32 element_size, storage = fm->precision >> 14;
+	int tile = 0;
+	u64 addr;
+
+	if (fm->region < 0)
+		return U64_MAX;
+
+	switch (storage) {
+	case 0:
+		if (x >= fm->width0 + 1) {
+			x -= fm->width0 + 1;
+			tile += 1;
+		}
+		if (y >= fm->height[tile] + 1) {
+			y -= fm->height[tile] + 1;
+			tile += 2;
+		}
+		break;
+	case 1:
+		if (y >= fm->height[1] + 1) {
+			y -= fm->height[1] + 1;
+			tile = 2;
+		} else if (y >= fm->height[0] + 1) {
+			y -= fm->height[0] + 1;
+			tile = 1;
+		}
+		break;
+	}
+	if (fm->base[tile] == U64_MAX)
+		return U64_MAX;
+
+	addr = fm->base[tile] + y * fm->stride_y;
+
+	switch ((fm->precision >> 6) & 0x3) { // format
+	case 0: //nhwc:
+		addr += x * fm->stride_x + c;
+		break;
+	case 1: //nhcwb16:
+		element_size = BIT((fm->precision >> 1) & 0x3);
+
+		addr += (c / 16) * fm->stride_c + (16 * x + (c & 0xf)) * element_size;
+		break;
+	}
+
+	info->region_size[fm->region] = max(info->region_size[fm->region], addr + 1);
+
+	return addr;
+}
+
+static int calc_sizes(struct drm_device *ddev,
+		      struct ethosu_validated_cmdstream_info *info,
+		      u16 op, struct cmd_state *st,
+		      bool ifm, bool ifm2, bool weight, bool scale)
+{
+	u64 len;
+
+	if (ifm) {
+		if (st->ifm.stride_kernel == U16_MAX)
+			return -EINVAL;
+		u32 stride_y = ((st->ifm.stride_kernel >> 8) & 0x2) +
+			((st->ifm.stride_kernel >> 1) & 0x1) + 1;
+		u32 stride_x = ((st->ifm.stride_kernel >> 5) & 0x2) +
+			(st->ifm.stride_kernel & 0x1) + 1;
+		u32 ifm_height = st->ofm.height[2] * stride_y +
+			st->ifm.height[2] - (st->ifm.pad_top + st->ifm.pad_bottom);
+		u32 ifm_width  = st->ofm.width * stride_x +
+			st->ifm.width - (st->ifm.pad_left + st->ifm.pad_right);
+
+		len = feat_matrix_length(info, &st->ifm, ifm_width,
+					 ifm_height, st->ifm.depth);
+		dev_dbg(ddev->dev, "op %d: IFM:%d:0x%llx-0x%llx\n",
+			op, st->ifm.region, st->ifm.base[0], len);
+		if (len == U64_MAX)
+			return -EINVAL;
+	}
+
+	if (ifm2) {
+		len = feat_matrix_length(info, &st->ifm2, st->ifm.depth,
+					 0, st->ofm.depth);
+		dev_dbg(ddev->dev, "op %d: IFM2:%d:0x%llx-0x%llx\n",
+			op, st->ifm2.region, st->ifm2.base[0], len);
+		if (len == U64_MAX)
+			return -EINVAL;
+	}
+
+	if (weight) {
+		dev_dbg(ddev->dev, "op %d: W:%d:0x%llx-0x%llx\n",
+			op, st->weight[0].region, st->weight[0].base,
+			st->weight[0].base + st->weight[0].length - 1);
+		if (st->weight[0].region < 0 || st->weight[0].base == U64_MAX ||
+		    st->weight[0].length == U32_MAX)
+			return -EINVAL;
+		info->region_size[st->weight[0].region] =
+			max(info->region_size[st->weight[0].region],
+			    st->weight[0].base + st->weight[0].length);
+	}
+
+	if (scale) {
+		dev_dbg(ddev->dev, "op %d: S:%d:0x%llx-0x%llx\n",
+			op, st->scale[0].region, st->scale[0].base,
+			st->scale[0].base + st->scale[0].length - 1);
+		if (st->scale[0].region < 0 || st->scale[0].base == U64_MAX ||
+		    st->scale[0].length == U32_MAX)
+			return -EINVAL;
+		info->region_size[st->scale[0].region] =
+			max(info->region_size[st->scale[0].region],
+			    st->scale[0].base + st->scale[0].length);
+	}
+
+	len = feat_matrix_length(info, &st->ofm, st->ofm.width,
+				 st->ofm.height[2], st->ofm.depth);
+	dev_dbg(ddev->dev, "op %d: OFM:%d:0x%llx-0x%llx\n",
+		op, st->ofm.region, st->ofm.base[0], len);
+	if (len == U64_MAX)
+		return -EINVAL;
+	info->output_region[st->ofm.region] = true;
+
+	return 0;
+}
+
+static int calc_sizes_elemwise(struct drm_device *ddev,
+			       struct ethosu_validated_cmdstream_info *info,
+			       u16 op, struct cmd_state *st,
+			       bool ifm, bool ifm2)
+{
+	u32 height, width, depth;
+	u64 len;
+
+	if (ifm) {
+		height = st->ifm.broadcast & 0x1 ? 0 : st->ofm.height[2];
+		width = st->ifm.broadcast & 0x2 ? 0 : st->ofm.width;
+		depth = st->ifm.broadcast & 0x4 ? 0 : st->ofm.depth;
+
+		len = feat_matrix_length(info, &st->ifm, width,
+					 height, depth);
+		dev_dbg(ddev->dev, "op %d: IFM:%d:0x%llx-0x%llx\n",
+			op, st->ifm.region, st->ifm.base[0], len);
+		if (len == U64_MAX)
+			return -EINVAL;
+	}
+
+	if (ifm2) {
+		height = st->ifm2.broadcast & 0x1 ? 0 : st->ofm.height[2];
+		width = st->ifm2.broadcast & 0x2 ? 0 : st->ofm.width;
+		depth = st->ifm2.broadcast & 0x4 ? 0 : st->ofm.depth;
+
+		len = feat_matrix_length(info, &st->ifm2, width,
+					 height, depth);
+		dev_dbg(ddev->dev, "op %d: IFM2:%d:0x%llx-0x%llx\n",
+			op, st->ifm2.region, st->ifm2.base[0], len);
+		if (len == U64_MAX)
+			return -EINVAL;
+	}
+
+	len = feat_matrix_length(info, &st->ofm, st->ofm.width,
+				 st->ofm.height[2], st->ofm.depth);
+	dev_dbg(ddev->dev, "op %d: OFM:%d:0x%llx-0x%llx\n",
+		op, st->ofm.region, st->ofm.base[0], len);
+	if (len == U64_MAX)
+		return -EINVAL;
+	info->output_region[st->ofm.region] = true;
+
+	return 0;
+}
+
+static int ethosu_gem_cmdstream_copy_and_validate(struct drm_device *ddev,
+						  u32 __user *ucmds,
+						  struct ethosu_gem_object *bo,
+						  u32 size)
+{
+	struct ethosu_validated_cmdstream_info __free(kfree) *info = kzalloc(sizeof(*info), GFP_KERNEL);
+	struct ethosu_device *edev = to_ethosu_device(ddev);
+	u32 *bocmds = bo->base.vaddr;
+	struct cmd_state st;
+	int i, ret;
+
+	if (!info)
+		return -ENOMEM;
+	info->cmd_size = size;
+
+	cmd_state_init(&st);
+
+	for (i = 0; i < size / 4; i++) {
+		bool use_ifm, use_ifm2, use_scale;
+		u64 dstlen, srclen;
+		u16 cmd, param;
+		u32 cmds[2];
+		u64 addr;
+
+		if (get_user(cmds[0], ucmds++))
+			return -EFAULT;
+
+		bocmds[i] = cmds[0];
+
+		cmd = cmds[0];
+		param = cmds[0] >> 16;
+
+		if (cmd & 0x4000) {
+			if (get_user(cmds[1], ucmds++))
+				return -EFAULT;
+
+			i++;
+			bocmds[i] = cmds[1];
+			addr = cmd_to_addr(cmds);
+		}
+
+		switch (cmd) {
+		case NPU_OP_DMA_START:
+			srclen = dma_length(info, &st.dma, &st.dma.src);
+			dstlen = dma_length(info, &st.dma, &st.dma.dst);
+
+			if (st.dma.dst.region >= 0)
+				info->output_region[st.dma.dst.region] = true;
+			dev_dbg(ddev->dev, "cmd: DMA SRC:%d:0x%llx+0x%llx DST:%d:0x%llx+0x%llx\n",
+				st.dma.src.region, st.dma.src.offset, srclen,
+				st.dma.dst.region, st.dma.dst.offset, dstlen);
+			break;
+		case NPU_OP_CONV:
+		case NPU_OP_DEPTHWISE:
+			use_ifm2 = param & 0x1;  // weights_ifm2
+			use_scale = !(st.ofm.precision & 0x100);
+			ret = calc_sizes(ddev, info, cmd, &st, true, use_ifm2,
+					 !use_ifm2, use_scale);
+			if (ret)
+				return ret;
+			break;
+		case NPU_OP_POOL:
+			use_ifm = param != 0x4;  // pooling mode
+			use_scale = !(st.ofm.precision & 0x100);
+			ret = calc_sizes(ddev, info, cmd, &st, use_ifm, false,
+					 false, use_scale);
+			if (ret)
+				return ret;
+			break;
+		case NPU_OP_ELEMENTWISE:
+			use_ifm2 = !((st.ifm2.broadcast == 8) || (param == 5) ||
+				(param == 6) || (param == 7) || (param == 0x24));
+			use_ifm = st.ifm.broadcast != 8;
+			ret = calc_sizes_elemwise(ddev, info, cmd, &st, use_ifm, use_ifm2);
+			if (ret)
+				return ret;
+			break;
+		case NPU_OP_RESIZE: // U85 only
+			WARN_ON(1); // TODO
+			break;
+		case NPU_SET_KERNEL_WIDTH_M1:
+			st.ifm.width = param;
+			break;
+		case NPU_SET_KERNEL_HEIGHT_M1:
+			st.ifm.height[2] = param;
+			break;
+		case NPU_SET_KERNEL_STRIDE:
+			st.ifm.stride_kernel = param;
+			break;
+		case NPU_SET_IFM_PAD_TOP:
+			st.ifm.pad_top = param & 0x7f;
+			break;
+		case NPU_SET_IFM_PAD_LEFT:
+			st.ifm.pad_left = param & 0x7f;
+			break;
+		case NPU_SET_IFM_PAD_RIGHT:
+			st.ifm.pad_right = param & 0xff;
+			break;
+		case NPU_SET_IFM_PAD_BOTTOM:
+			st.ifm.pad_bottom = param & 0xff;
+			break;
+		case NPU_SET_IFM_DEPTH_M1:
+			st.ifm.depth = param;
+			break;
+		case NPU_SET_IFM_PRECISION:
+			st.ifm.precision = param;
+			break;
+		case NPU_SET_IFM_BROADCAST:
+			st.ifm.broadcast = param;
+			break;
+		case NPU_SET_IFM_REGION:
+			st.ifm.region = param & 0x7f;
+			break;
+		case NPU_SET_IFM_WIDTH0_M1:
+			st.ifm.width0 = param;
+			break;
+		case NPU_SET_IFM_HEIGHT0_M1:
+			st.ifm.height[0] = param;
+			break;
+		case NPU_SET_IFM_HEIGHT1_M1:
+			st.ifm.height[1] = param;
+			break;
+		case NPU_SET_IFM_BASE0:
+		case NPU_SET_IFM_BASE1:
+		case NPU_SET_IFM_BASE2:
+		case NPU_SET_IFM_BASE3:
+			st.ifm.base[cmd & 0x3] = addr;
+			break;
+		case NPU_SET_IFM_STRIDE_X:
+			st.ifm.stride_x = addr;
+			break;
+		case NPU_SET_IFM_STRIDE_Y:
+			st.ifm.stride_y = addr;
+			break;
+		case NPU_SET_IFM_STRIDE_C:
+			st.ifm.stride_c = addr;
+			break;
+
+		case NPU_SET_OFM_WIDTH_M1:
+			st.ofm.width = param;
+			break;
+		case NPU_SET_OFM_HEIGHT_M1:
+			st.ofm.height[2] = param;
+			break;
+		case NPU_SET_OFM_DEPTH_M1:
+			st.ofm.depth = param;
+			break;
+		case NPU_SET_OFM_PRECISION:
+			st.ofm.precision = param;
+			break;
+		case NPU_SET_OFM_REGION:
+			st.ofm.region = param & 0x7;
+			break;
+		case NPU_SET_OFM_WIDTH0_M1:
+			st.ofm.width0 = param;
+			break;
+		case NPU_SET_OFM_HEIGHT0_M1:
+			st.ofm.height[0] = param;
+			break;
+		case NPU_SET_OFM_HEIGHT1_M1:
+			st.ofm.height[1] = param;
+			break;
+		case NPU_SET_OFM_BASE0:
+		case NPU_SET_OFM_BASE1:
+		case NPU_SET_OFM_BASE2:
+		case NPU_SET_OFM_BASE3:
+			st.ofm.base[cmd & 0x3] = addr;
+			break;
+		case NPU_SET_OFM_STRIDE_X:
+			st.ofm.stride_x = addr;
+			break;
+		case NPU_SET_OFM_STRIDE_Y:
+			st.ofm.stride_y = addr;
+			break;
+		case NPU_SET_OFM_STRIDE_C:
+			st.ofm.stride_c = addr;
+			break;
+
+		case NPU_SET_IFM2_BROADCAST:
+			st.ifm2.broadcast = param;
+			break;
+		case NPU_SET_IFM2_PRECISION:
+			st.ifm2.precision = param;
+			break;
+		case NPU_SET_IFM2_REGION:
+			st.ifm2.region = param & 0x7;
+			break;
+		case NPU_SET_IFM2_WIDTH0_M1:
+			st.ifm2.width0 = param;
+			break;
+		case NPU_SET_IFM2_HEIGHT0_M1:
+			st.ifm2.height[0] = param;
+			break;
+		case NPU_SET_IFM2_HEIGHT1_M1:
+			st.ifm2.height[1] = param;
+			break;
+		case NPU_SET_IFM2_BASE0:
+		case NPU_SET_IFM2_BASE1:
+		case NPU_SET_IFM2_BASE2:
+		case NPU_SET_IFM2_BASE3:
+			st.ifm2.base[cmd & 0x3] = addr;
+			break;
+		case NPU_SET_IFM2_STRIDE_X:
+			st.ifm2.stride_x = addr;
+			break;
+		case NPU_SET_IFM2_STRIDE_Y:
+			st.ifm2.stride_y = addr;
+			break;
+		case NPU_SET_IFM2_STRIDE_C:
+			st.ifm2.stride_c = addr;
+			break;
+
+		case NPU_SET_WEIGHT_REGION:
+			st.weight[0].region = param & 0x7;
+			break;
+		case NPU_SET_SCALE_REGION:
+			st.scale[0].region = param & 0x7;
+			break;
+		case NPU_SET_WEIGHT_BASE:
+			st.weight[0].base = addr;
+			break;
+		case NPU_SET_WEIGHT_LENGTH:
+			st.weight[0].length = cmds[1];
+			break;
+		case NPU_SET_SCALE_BASE:
+			st.scale[0].base = addr;
+			break;
+		case NPU_SET_SCALE_LENGTH:
+			st.scale[0].length = cmds[1];
+			break;
+		case NPU_SET_WEIGHT1_BASE:
+			st.weight[1].base = addr;
+			break;
+		case NPU_SET_WEIGHT1_LENGTH:
+			st.weight[1].length = cmds[1];
+			break;
+		case NPU_SET_SCALE1_BASE: // NPU_SET_WEIGHT2_BASE (U85)
+			if (ethosu_is_u65(edev))
+				st.scale[1].base = addr;
+			else
+				st.weight[2].base = addr;
+			break;
+		case NPU_SET_SCALE1_LENGTH: // NPU_SET_WEIGHT2_LENGTH (U85)
+			if (ethosu_is_u65(edev))
+				st.scale[1].length = cmds[1];
+			else
+				st.weight[1].length = cmds[1];
+			break;
+		case NPU_SET_WEIGHT3_BASE:
+			st.weight[3].base = addr;
+			break;
+		case NPU_SET_WEIGHT3_LENGTH:
+			st.weight[3].length = cmds[1];
+			break;
+
+		case NPU_SET_DMA0_SRC_REGION:
+			if (param & 0x100)
+				st.dma.src.region = -1;
+			else
+				st.dma.src.region = param & 0x7;
+			st.dma.mode = (param >> 9) & 0x3;
+			break;
+		case NPU_SET_DMA0_DST_REGION:
+			if (param & 0x100)
+				st.dma.dst.region = -1;
+			else
+				st.dma.dst.region = param & 0x7;
+			break;
+		case NPU_SET_DMA0_SIZE0:
+			st.dma.size0 = param;
+			break;
+		case NPU_SET_DMA0_SIZE1:
+			st.dma.size1 = param;
+			break;
+		case NPU_SET_DMA0_SRC_STRIDE0:
+			st.dma.src.stride[0] = ((s64)addr << 24) >> 24;
+			break;
+		case NPU_SET_DMA0_SRC_STRIDE1:
+			st.dma.src.stride[1] = ((s64)addr << 24) >> 24;
+			break;
+		case NPU_SET_DMA0_DST_STRIDE0:
+			st.dma.dst.stride[0] = ((s64)addr << 24) >> 24;
+			break;
+		case NPU_SET_DMA0_DST_STRIDE1:
+			st.dma.dst.stride[1] = ((s64)addr << 24) >> 24;
+			break;
+		case NPU_SET_DMA0_SRC:
+			st.dma.src.offset = addr;
+			break;
+		case NPU_SET_DMA0_DST:
+			st.dma.dst.offset = addr;
+			break;
+		case NPU_SET_DMA0_LEN:
+			st.dma.src.len = st.dma.dst.len = addr;
+			break;
+		default:
+			break;
+		}
+	}
+
+	for (i = 0; i < NPU_BASEP_REGION_MAX; i++) {
+		if (!info->region_size[i])
+			continue;
+		dev_dbg(ddev->dev, "region %d max size: 0x%llx\n",
+			i, info->region_size[i]);
+	}
+
+	bo->info = no_free_ptr(info);
+	return 0;
+}
+
+/**
+ * ethosu_gem_cmdstream_create() - Create a GEM object and attach it to a handle.
+ * @file: DRM file.
+ * @ddev: DRM device.
+ * @exclusive_vm: Exclusive VM. Not NULL if the GEM object can't be shared.
+ * @size: Size of the GEM object to allocate.
+ * @flags: Combination of drm_ethosu_bo_flags flags.
+ * @handle: Pointer holding the handle pointing to the new GEM object.
+ *
+ * Return: Zero on success
+ */
+int ethosu_gem_cmdstream_create(struct drm_file *file,
+				struct drm_device *ddev,
+				u32 size, u64 data, u32 flags, u32 *handle)
+{
+	int ret;
+	struct drm_gem_dma_object *mem;
+	struct ethosu_gem_object *bo;
+
+	mem = drm_gem_dma_create(ddev, size);
+	if (IS_ERR(mem))
+		return PTR_ERR(mem);
+
+	bo = to_ethosu_bo(&mem->base);
+	bo->flags = flags;
+
+	ret = ethosu_gem_cmdstream_copy_and_validate(ddev,
+						     (void __user *)(uintptr_t)data,
+						     bo, size);
+	if (ret)
+		goto fail;
+
+	/*
+	 * Allocate an id of idr table where the obj is registered
+	 * and handle has the id what user can see.
+	 */
+	ret = drm_gem_handle_create(file, &mem->base, handle);
+
+fail:
+	/* drop reference from allocate - handle holds it now. */
+	drm_gem_object_put(&mem->base);
+
+	return ret;
+}
diff --git a/drivers/accel/ethosu/ethosu_gem.h b/drivers/accel/ethosu/ethosu_gem.h
new file mode 100644
index 000000000000..3922895a60fb
--- /dev/null
+++ b/drivers/accel/ethosu/ethosu_gem.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0 or MIT */
+/* Copyright 2025 Arm, Ltd. */
+
+#ifndef __ETHOSU_GEM_H__
+#define __ETHOSU_GEM_H__
+
+#include "ethosu_device.h"
+#include <drm/drm_gem_dma_helper.h>
+
+struct ethosu_validated_cmdstream_info {
+	u32 cmd_size;
+	u64 region_size[NPU_BASEP_REGION_MAX];
+	bool output_region[NPU_BASEP_REGION_MAX];
+};
+
+/**
+ * struct ethosu_gem_object - Driver specific GEM object.
+ */
+struct ethosu_gem_object {
+	/** @base: Inherit from drm_gem_shmem_object. */
+	struct drm_gem_dma_object base;
+
+	struct ethosu_validated_cmdstream_info *info;
+
+	/** @flags: Combination of drm_ethosu_bo_flags flags. */
+	u32 flags;
+};
+
+static inline
+struct ethosu_gem_object *to_ethosu_bo(struct drm_gem_object *obj)
+{
+	return container_of(to_drm_gem_dma_obj(obj), struct ethosu_gem_object, base);
+}
+
+struct drm_gem_object *ethosu_gem_create_object(struct drm_device *ddev,
+						size_t size);
+
+int ethosu_gem_create_with_handle(struct drm_file *file,
+				  struct drm_device *ddev,
+				  u64 *size, u32 flags, uint32_t *handle);
+
+int ethosu_gem_cmdstream_create(struct drm_file *file,
+				struct drm_device *ddev,
+				u32 size, u64 data, u32 flags, u32 *handle);
+
+#endif /* __ETHOSU_GEM_H__ */
diff --git a/drivers/accel/ethosu/ethosu_job.c b/drivers/accel/ethosu/ethosu_job.c
new file mode 100644
index 000000000000..26e7a2f64d71
--- /dev/null
+++ b/drivers/accel/ethosu/ethosu_job.c
@@ -0,0 +1,497 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/* Copyright 2024-2025 Tomeu Vizoso <tomeu@tomeuvizoso.net> */
+/* Copyright 2025 Arm, Ltd. */
+
+#include <linux/bitfield.h>
+#include <linux/genalloc.h>
+#include <linux/interrupt.h>
+#include <linux/iopoll.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+
+#include <drm/drm_file.h>
+#include <drm/drm_gem.h>
+#include <drm/drm_gem_dma_helper.h>
+#include <drm/drm_print.h>
+#include <drm/ethosu_accel.h>
+
+#include "ethosu_device.h"
+#include "ethosu_drv.h"
+#include "ethosu_gem.h"
+#include "ethosu_job.h"
+
+#define JOB_TIMEOUT_MS 500
+
+static struct ethosu_job *to_ethosu_job(struct drm_sched_job *sched_job)
+{
+	return container_of(sched_job, struct ethosu_job, base);
+}
+
+static const char *ethosu_fence_get_driver_name(struct dma_fence *fence)
+{
+	return "ethosu";
+}
+
+static const char *ethosu_fence_get_timeline_name(struct dma_fence *fence)
+{
+	return "ethosu-npu";
+}
+
+static const struct dma_fence_ops ethosu_fence_ops = {
+	.get_driver_name = ethosu_fence_get_driver_name,
+	.get_timeline_name = ethosu_fence_get_timeline_name,
+};
+
+static void ethosu_job_hw_submit(struct ethosu_device *dev, struct ethosu_job *job)
+{
+	struct drm_gem_dma_object *cmd_bo = to_drm_gem_dma_obj(job->cmd_bo);
+	struct ethosu_validated_cmdstream_info *cmd_info = to_ethosu_bo(job->cmd_bo)->info;
+
+	for (int i = 0; i < job->region_cnt; i++) {
+		struct drm_gem_dma_object *bo;
+		int region = job->region_bo_num[i];
+
+		bo = to_drm_gem_dma_obj(job->region_bo[i]);
+		writel_relaxed(lower_32_bits(bo->dma_addr), dev->regs + NPU_REG_BASEP(region));
+		writel_relaxed(upper_32_bits(bo->dma_addr), dev->regs + NPU_REG_BASEP_HI(region));
+		dev_dbg(dev->base.dev, "Region %d base addr = %pad\n", region, &bo->dma_addr);
+	}
+
+	if (job->sram_size) {
+		writel_relaxed(lower_32_bits(dev->sramphys),
+			       dev->regs + NPU_REG_BASEP(ETHOSU_SRAM_REGION));
+		writel_relaxed(upper_32_bits(dev->sramphys),
+			       dev->regs + NPU_REG_BASEP_HI(ETHOSU_SRAM_REGION));
+		dev_dbg(dev->base.dev, "Region %d base addr = %pad (SRAM)\n",
+			ETHOSU_SRAM_REGION, &dev->sramphys);
+	}
+
+	writel_relaxed(lower_32_bits(cmd_bo->dma_addr), dev->regs + NPU_REG_QBASE);
+	writel_relaxed(upper_32_bits(cmd_bo->dma_addr), dev->regs + NPU_REG_QBASE_HI);
+	writel_relaxed(cmd_info->cmd_size, dev->regs + NPU_REG_QSIZE);
+
+	writel(CMD_TRANSITION_TO_RUN, dev->regs + NPU_REG_CMD);
+
+	dev_dbg(dev->base.dev,
+		"Submitted cmd at %pad to core\n", &cmd_bo->dma_addr);
+}
+
+static int ethosu_acquire_object_fences(struct ethosu_job *job)
+{
+	int i, ret;
+	struct drm_gem_object **bos = job->region_bo;
+	struct ethosu_validated_cmdstream_info *info = to_ethosu_bo(job->cmd_bo)->info;
+
+	for (i = 0; i < job->region_cnt; i++) {
+		bool is_write;
+
+		if (!bos[i])
+			break;
+
+		ret = dma_resv_reserve_fences(bos[i]->resv, 1);
+		if (ret)
+			return ret;
+
+		is_write = info->output_region[job->region_bo_num[i]];
+		ret = drm_sched_job_add_implicit_dependencies(&job->base, bos[i],
+							      is_write);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static void ethosu_attach_object_fences(struct ethosu_job *job)
+{
+	int i;
+	struct dma_fence *fence = job->inference_done_fence;
+	struct drm_gem_object **bos = job->region_bo;
+	struct ethosu_validated_cmdstream_info *info = to_ethosu_bo(job->cmd_bo)->info;
+
+	for (i = 0; i < job->region_cnt; i++)
+		if (info->output_region[job->region_bo_num[i]])
+			dma_resv_add_fence(bos[i]->resv, fence, DMA_RESV_USAGE_WRITE);
+}
+
+static int ethosu_job_push(struct ethosu_job *job)
+{
+	struct ww_acquire_ctx acquire_ctx;
+	int ret;
+
+	ret = drm_gem_lock_reservations(job->region_bo, job->region_cnt, &acquire_ctx);
+	if (ret)
+		return ret;
+
+	ret = ethosu_acquire_object_fences(job);
+	if (ret)
+		goto out;
+
+	ret = pm_runtime_resume_and_get(job->dev->base.dev);
+	if (!ret) {
+		guard(mutex)(&job->dev->sched_lock);
+
+		drm_sched_job_arm(&job->base);
+		job->inference_done_fence = dma_fence_get(&job->base.s_fence->finished);
+		kref_get(&job->refcount); /* put by scheduler job completion */
+		drm_sched_entity_push_job(&job->base);
+		ethosu_attach_object_fences(job);
+	}
+
+out:
+	drm_gem_unlock_reservations(job->region_bo, job->region_cnt, &acquire_ctx);
+	return ret;
+}
+
+static void ethosu_job_cleanup(struct kref *ref)
+{
+	struct ethosu_job *job = container_of(ref, struct ethosu_job,
+						refcount);
+	unsigned int i;
+
+	pm_runtime_put_autosuspend(job->dev->base.dev);
+
+	dma_fence_put(job->done_fence);
+	dma_fence_put(job->inference_done_fence);
+
+	for (i = 0; i < job->region_cnt; i++)
+		drm_gem_object_put(job->region_bo[i]);
+
+	drm_gem_object_put(job->cmd_bo);
+
+	kfree(job);
+}
+
+static void ethosu_job_put(struct ethosu_job *job)
+{
+	kref_put(&job->refcount, ethosu_job_cleanup);
+}
+
+static void ethosu_job_free(struct drm_sched_job *sched_job)
+{
+	struct ethosu_job *job = to_ethosu_job(sched_job);
+
+	drm_sched_job_cleanup(sched_job);
+	ethosu_job_put(job);
+}
+
+static struct dma_fence *ethosu_job_run(struct drm_sched_job *sched_job)
+{
+	struct ethosu_job *job = to_ethosu_job(sched_job);
+	struct ethosu_device *dev = job->dev;
+	struct dma_fence *fence = job->done_fence;
+
+	if (unlikely(job->base.s_fence->finished.error))
+		return NULL;
+
+	dma_fence_init(fence, &ethosu_fence_ops, &dev->fence_lock,
+		       dev->fence_context, ++dev->emit_seqno);
+	dma_fence_get(fence);
+
+	scoped_guard(mutex, &dev->job_lock) {
+		dev->in_flight_job = job;
+		ethosu_job_hw_submit(dev, job);
+	}
+
+	return fence;
+}
+
+static void ethosu_job_handle_irq(struct ethosu_device *dev)
+{
+	u32 status = readl_relaxed(dev->regs + NPU_REG_STATUS);
+
+	if (status & (STATUS_BUS_STATUS | STATUS_CMD_PARSE_ERR)) {
+		dev_err(dev->base.dev, "Error IRQ - %x\n", status);
+		drm_sched_fault(&dev->sched);
+		return;
+	}
+
+	scoped_guard(mutex, &dev->job_lock) {
+		if (dev->in_flight_job) {
+			dma_fence_signal(dev->in_flight_job->done_fence);
+			dev->in_flight_job = NULL;
+		}
+	}
+}
+
+static irqreturn_t ethosu_job_irq_handler_thread(int irq, void *data)
+{
+	struct ethosu_device *dev = data;
+
+	ethosu_job_handle_irq(dev);
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t ethosu_job_irq_handler(int irq, void *data)
+{
+	struct ethosu_device *dev = data;
+	u32 status = readl_relaxed(dev->regs + NPU_REG_STATUS);
+
+	if (!(status & STATUS_IRQ_RAISED))
+		return IRQ_NONE;
+
+	writel_relaxed(CMD_CLEAR_IRQ, dev->regs + NPU_REG_CMD);
+	return IRQ_WAKE_THREAD;
+}
+
+static enum drm_gpu_sched_stat ethosu_job_timedout(struct drm_sched_job *bad)
+{
+	struct ethosu_job *job = to_ethosu_job(bad);
+	struct ethosu_device *dev = job->dev;
+	bool running;
+	u32 *bocmds = to_drm_gem_dma_obj(job->cmd_bo)->vaddr;
+	u32 cmdaddr;
+
+	cmdaddr = readl_relaxed(dev->regs + NPU_REG_QREAD);
+	running = FIELD_GET(STATUS_STATE_RUNNING, readl_relaxed(dev->regs + NPU_REG_STATUS));
+
+	if (running) {
+		int ret;
+		u32 reg;
+
+		ret = readl_relaxed_poll_timeout(dev->regs + NPU_REG_QREAD,
+						 reg,
+						 reg != cmdaddr,
+						 USEC_PER_MSEC, 100 * USEC_PER_MSEC);
+
+		/* If still running and progress is being made, just return */
+		if (!ret)
+			return DRM_GPU_SCHED_STAT_NO_HANG;
+	}
+
+	dev_err(dev->base.dev, "NPU sched timed out: NPU %s, cmdstream offset 0x%x: 0x%x\n",
+		running ? "running" : "stopped",
+		cmdaddr, bocmds[cmdaddr / 4]);
+
+	drm_sched_stop(&dev->sched, bad);
+
+	scoped_guard(mutex, &dev->job_lock)
+		dev->in_flight_job = NULL;
+
+	/* Proceed with reset now. */
+	pm_runtime_force_suspend(dev->base.dev);
+	pm_runtime_force_resume(dev->base.dev);
+
+	/* Restart the scheduler */
+	drm_sched_start(&dev->sched, 0);
+
+	return DRM_GPU_SCHED_STAT_RESET;
+}
+
+static const struct drm_sched_backend_ops ethosu_sched_ops = {
+	.run_job = ethosu_job_run,
+	.timedout_job = ethosu_job_timedout,
+	.free_job = ethosu_job_free
+};
+
+int ethosu_job_init(struct ethosu_device *edev)
+{
+	struct device *dev = edev->base.dev;
+	struct drm_sched_init_args args = {
+		.ops = &ethosu_sched_ops,
+		.num_rqs = DRM_SCHED_PRIORITY_COUNT,
+		.credit_limit = 1,
+		.timeout = msecs_to_jiffies(JOB_TIMEOUT_MS),
+		.name = dev_name(dev),
+		.dev = dev,
+	};
+	int ret;
+
+	spin_lock_init(&edev->fence_lock);
+	ret = devm_mutex_init(dev, &edev->job_lock);
+	if (ret)
+		return ret;
+	ret = devm_mutex_init(dev, &edev->sched_lock);
+	if (ret)
+		return ret;
+
+	edev->irq = platform_get_irq(to_platform_device(dev), 0);
+	if (edev->irq < 0)
+		return edev->irq;
+
+	ret = devm_request_threaded_irq(dev, edev->irq,
+					ethosu_job_irq_handler,
+					ethosu_job_irq_handler_thread,
+					IRQF_SHARED, KBUILD_MODNAME,
+					edev);
+	if (ret) {
+		dev_err(dev, "failed to request irq\n");
+		return ret;
+	}
+
+	edev->fence_context = dma_fence_context_alloc(1);
+
+	ret = drm_sched_init(&edev->sched, &args);
+	if (ret) {
+		dev_err(dev, "Failed to create scheduler: %d\n", ret);
+		goto err_sched;
+	}
+
+	return 0;
+
+err_sched:
+	drm_sched_fini(&edev->sched);
+	return ret;
+}
+
+void ethosu_job_fini(struct ethosu_device *dev)
+{
+	drm_sched_fini(&dev->sched);
+}
+
+int ethosu_job_open(struct ethosu_file_priv *ethosu_priv)
+{
+	struct ethosu_device *dev = ethosu_priv->edev;
+	struct drm_gpu_scheduler *sched = &dev->sched;
+	int ret;
+
+	ret = drm_sched_entity_init(&ethosu_priv->sched_entity,
+				    DRM_SCHED_PRIORITY_NORMAL,
+				    &sched, 1, NULL);
+	return WARN_ON(ret);
+}
+
+void ethosu_job_close(struct ethosu_file_priv *ethosu_priv)
+{
+	struct drm_sched_entity *entity = &ethosu_priv->sched_entity;
+
+	drm_sched_entity_destroy(entity);
+}
+
+static int ethosu_ioctl_submit_job(struct drm_device *dev, struct drm_file *file,
+				   struct drm_ethosu_job *job)
+{
+	struct ethosu_device *edev = to_ethosu_device(dev);
+	struct ethosu_file_priv *file_priv = file->driver_priv;
+	struct ethosu_job *ejob = NULL;
+	struct ethosu_validated_cmdstream_info *cmd_info;
+	int ret = 0;
+
+	/* BO region 2 is reserved if SRAM is used */
+	if (job->region_bo_handles[ETHOSU_SRAM_REGION] && job->sram_size)
+		return -EINVAL;
+
+	if (edev->npu_info.sram_size < job->sram_size)
+		return -EINVAL;
+
+	ejob = kzalloc(sizeof(*ejob), GFP_KERNEL);
+	if (!ejob)
+		return -ENOMEM;
+
+	kref_init(&ejob->refcount);
+
+	ejob->dev = edev;
+	ejob->sram_size = job->sram_size;
+
+	ejob->done_fence = kzalloc(sizeof(*ejob->done_fence), GFP_KERNEL);
+	if (!ejob->done_fence) {
+		ret = -ENOMEM;
+		goto out_cleanup_job;
+	}
+
+	ret = drm_sched_job_init(&ejob->base,
+				 &file_priv->sched_entity,
+				 1, NULL, file->client_id);
+	if (ret)
+		goto out_put_job;
+
+	ejob->cmd_bo = drm_gem_object_lookup(file, job->cmd_bo);
+	if (!ejob->cmd_bo) {
+		ret = -ENOENT;
+		goto out_cleanup_job;
+	}
+	cmd_info = to_ethosu_bo(ejob->cmd_bo)->info;
+	if (!cmd_info) {
+		ret = -EINVAL;
+		goto out_cleanup_job;
+	}
+
+	for (int i = 0; i < NPU_BASEP_REGION_MAX; i++) {
+		struct drm_gem_object *gem;
+
+		/* Can only omit a BO handle if the region is not used or used for SRAM */
+		if (!job->region_bo_handles[i] &&
+		    (!cmd_info->region_size[i] || (i == ETHOSU_SRAM_REGION && job->sram_size)))
+			continue;
+
+		if (job->region_bo_handles[i] && !cmd_info->region_size[i]) {
+			dev_err(dev->dev,
+				"Cmdstream BO handle %d set for unused region %d\n",
+				job->region_bo_handles[i], i);
+			ret = -EINVAL;
+			goto out_cleanup_job;
+		}
+
+		gem = drm_gem_object_lookup(file, job->region_bo_handles[i]);
+		if (!gem) {
+			dev_err(dev->dev,
+				"Invalid BO handle %d for region %d\n",
+				job->region_bo_handles[i], i);
+			ret = -ENOENT;
+			goto out_cleanup_job;
+		}
+
+		ejob->region_bo[ejob->region_cnt] = gem;
+		ejob->region_bo_num[ejob->region_cnt] = i;
+		ejob->region_cnt++;
+
+		if (to_ethosu_bo(gem)->info) {
+			dev_err(dev->dev,
+				"Cmdstream BO handle %d used for region %d\n",
+				job->region_bo_handles[i], i);
+			ret = -EINVAL;
+			goto out_cleanup_job;
+		}
+
+		/* Verify the command stream doesn't have accesses outside the BO */
+		if (cmd_info->region_size[i] > gem->size) {
+			dev_err(dev->dev,
+				"cmd stream region %d size greater than BO size (%llu > %zu)\n",
+				i, cmd_info->region_size[i], gem->size);
+			ret = -EOVERFLOW;
+			goto out_cleanup_job;
+		}
+	}
+	ret = ethosu_job_push(ejob);
+
+out_cleanup_job:
+	if (ret)
+		drm_sched_job_cleanup(&ejob->base);
+out_put_job:
+	ethosu_job_put(ejob);
+
+	return ret;
+}
+
+int ethosu_ioctl_submit(struct drm_device *dev, void *data, struct drm_file *file)
+{
+	struct drm_ethosu_submit *args = data;
+	int ret = 0;
+	unsigned int i = 0;
+
+	if (args->pad) {
+		drm_dbg(dev, "Reserved field in drm_ethosu_submit struct should be 0.\n");
+		return -EINVAL;
+	}
+
+	struct drm_ethosu_job __free(kvfree) *jobs =
+		kvmalloc_array(args->job_count, sizeof(*jobs), GFP_KERNEL);
+	if (!jobs)
+		return -ENOMEM;
+
+	if (copy_from_user(jobs,
+			   (void __user *)(uintptr_t)args->jobs,
+			   args->job_count * sizeof(*jobs))) {
+		drm_dbg(dev, "Failed to copy incoming job array\n");
+		return -EFAULT;
+	}
+
+	for (i = 0; i < args->job_count; i++) {
+		ret = ethosu_ioctl_submit_job(dev, file, &jobs[i]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
diff --git a/drivers/accel/ethosu/ethosu_job.h b/drivers/accel/ethosu/ethosu_job.h
new file mode 100644
index 000000000000..ff1cf448d094
--- /dev/null
+++ b/drivers/accel/ethosu/ethosu_job.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+/* Copyright 2024-2025 Tomeu Vizoso <tomeu@tomeuvizoso.net> */
+/* Copyright 2025 Arm, Ltd. */
+
+#ifndef __ETHOSU_JOB_H__
+#define __ETHOSU_JOB_H__
+
+#include <linux/kref.h>
+#include <drm/gpu_scheduler.h>
+
+struct ethosu_device;
+struct ethosu_file_priv;
+
+struct ethosu_job {
+	struct drm_sched_job base;
+	struct ethosu_device *dev;
+
+	struct drm_gem_object *cmd_bo;
+	struct drm_gem_object *region_bo[NPU_BASEP_REGION_MAX];
+	u8 region_bo_num[NPU_BASEP_REGION_MAX];
+	u8 region_cnt;
+	u32 sram_size;
+
+	/* Fence to be signaled by drm-sched once its done with the job */
+	struct dma_fence *inference_done_fence;
+
+	/* Fence to be signaled by IRQ handler when the job is complete. */
+	struct dma_fence *done_fence;
+
+	struct kref refcount;
+};
+
+int ethosu_ioctl_submit(struct drm_device *dev, void *data, struct drm_file *file);
+
+int ethosu_job_init(struct ethosu_device *dev);
+void ethosu_job_fini(struct ethosu_device *dev);
+int ethosu_job_open(struct ethosu_file_priv *ethosu_priv);
+void ethosu_job_close(struct ethosu_file_priv *ethosu_priv);
+
+#endif
diff --git a/drivers/accel/habanalabs/Kconfig b/drivers/accel/habanalabs/Kconfig
new file mode 100644
index 000000000000..6d1506acbd72
--- /dev/null
+++ b/drivers/accel/habanalabs/Kconfig
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# HabanaLabs AI accelerators driver
+#
+
+config DRM_ACCEL_HABANALABS
+	tristate "HabanaLabs AI accelerators"
+	depends on DRM_ACCEL
+	depends on X86 && X86_64
+	depends on PCI && HAS_IOMEM
+	select GENERIC_ALLOCATOR
+	select HWMON
+	select DMA_SHARED_BUFFER
+	select CRC32
+	select FW_LOADER
+	help
+	  Enables PCIe card driver for Habana's AI Processors (AIP) that are
+	  designed to accelerate Deep Learning inference and training workloads.
+
+	  The driver manages the PCIe devices and provides IOCTL interface for
+	  the user to submit workloads to the devices.
+
+	  The user-space interface is described in
+	  include/uapi/drm/habanalabs_accel.h
+
+	  If unsure, say N.
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called habanalabs.
+
+if DRM_ACCEL_HABANALABS
+
+config HL_HLDIO
+	bool "Habanalabs NVMe Direct I/O (HLDIO)"
+	depends on PCI_P2PDMA
+	depends on BLOCK
+	help
+	  Enable NVMe peer-to-peer direct I/O support for Habanalabs AI
+	  accelerators.
+
+	  This allows direct data transfers between NVMe storage devices
+	  and Habanalabs accelerators without involving system memory,
+	  using PCI peer-to-peer DMA capabilities.
+
+	  Requirements:
+	  - CONFIG_PCI_P2PDMA=y
+	  - NVMe device and Habanalabs accelerator under same PCI root complex
+	  - IOMMU disabled or in passthrough mode
+	  - Hardware supporting PCI P2P DMA
+
+	  If unsure, say N
+endif # DRM_ACCEL_HABANALABS
diff --git a/drivers/accel/habanalabs/Makefile b/drivers/accel/habanalabs/Makefile
new file mode 100644
index 000000000000..98510cdd5066
--- /dev/null
+++ b/drivers/accel/habanalabs/Makefile
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Makefile for HabanaLabs AI accelerators driver
+#
+
+obj-$(CONFIG_DRM_ACCEL_HABANALABS) := habanalabs.o
+
+include $(src)/common/Makefile
+habanalabs-y += $(HL_COMMON_FILES)
+
+include $(src)/gaudi2/Makefile
+habanalabs-y += $(HL_GAUDI2_FILES)
+
+include $(src)/gaudi/Makefile
+habanalabs-y += $(HL_GAUDI_FILES)
+
+include $(src)/goya/Makefile
+habanalabs-y += $(HL_GOYA_FILES)
+
+habanalabs-$(CONFIG_DEBUG_FS) += common/debugfs.o
diff --git a/drivers/accel/habanalabs/common/Makefile b/drivers/accel/habanalabs/common/Makefile
new file mode 100644
index 000000000000..b6d00de09db5
--- /dev/null
+++ b/drivers/accel/habanalabs/common/Makefile
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+include $(src)/common/mmu/Makefile
+habanalabs-y += $(HL_COMMON_MMU_FILES)
+
+include $(src)/common/pci/Makefile
+habanalabs-y += $(HL_COMMON_PCI_FILES)
+
+HL_COMMON_FILES := common/habanalabs_drv.o common/device.o common/context.o \
+		common/asid.o common/habanalabs_ioctl.o \
+		common/command_buffer.o common/hw_queue.o common/irq.o \
+		common/sysfs.o common/hwmon.o common/memory.o \
+		common/command_submission.o common/firmware_if.o \
+		common/security.o common/state_dump.o \
+		common/memory_mgr.o common/decoder.o
+
+# Conditionally add HLDIO support
+ifdef CONFIG_HL_HLDIO
+HL_COMMON_FILES += common/hldio.o
+endif
+\ No newline at end of file
diff --git a/drivers/misc/habanalabs/asid.c b/drivers/accel/habanalabs/common/asid.c
index a2fdf31cf27c..c9c2619cc43d 100644
--- a/drivers/misc/habanalabs/asid.c
+++ b/drivers/accel/habanalabs/common/asid.c
@@ -11,8 +11,7 @@
 
 int hl_asid_init(struct hl_device *hdev)
 {
-	hdev->asid_bitmap = kcalloc(BITS_TO_LONGS(hdev->asic_prop.max_asid),
-					sizeof(*hdev->asid_bitmap), GFP_KERNEL);
+	hdev->asid_bitmap = bitmap_zalloc(hdev->asic_prop.max_asid, GFP_KERNEL);
 	if (!hdev->asid_bitmap)
 		return -ENOMEM;
 
@@ -27,7 +26,7 @@ int hl_asid_init(struct hl_device *hdev)
 void hl_asid_fini(struct hl_device *hdev)
 {
 	mutex_destroy(&hdev->asid_mutex);
-	kfree(hdev->asid_bitmap);
+	bitmap_free(hdev->asid_bitmap);
 }
 
 unsigned long hl_asid_alloc(struct hl_device *hdev)
@@ -50,8 +49,10 @@ unsigned long hl_asid_alloc(struct hl_device *hdev)
 
 void hl_asid_free(struct hl_device *hdev, unsigned long asid)
 {
-	if (WARN((asid == 0 || asid >= hdev->asic_prop.max_asid),
-						"Invalid ASID %lu", asid))
+	if (asid == HL_KERNEL_ASID_ID || asid >= hdev->asic_prop.max_asid) {
+		dev_crit(hdev->dev, "Invalid ASID %lu", asid);
 		return;
+	}
+
 	clear_bit(asid, hdev->asid_bitmap);
 }
diff --git a/drivers/accel/habanalabs/common/command_buffer.c b/drivers/accel/habanalabs/common/command_buffer.c
new file mode 100644
index 000000000000..0f0d295116e7
--- /dev/null
+++ b/drivers/accel/habanalabs/common/command_buffer.c
@@ -0,0 +1,558 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Copyright 2016-2019 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ */
+
+#include <uapi/drm/habanalabs_accel.h>
+#include "habanalabs.h"
+
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/uaccess.h>
+
+#define CB_VA_POOL_SIZE		(4UL * SZ_1G)
+
+static int cb_map_mem(struct hl_ctx *ctx, struct hl_cb *cb)
+{
+	struct hl_device *hdev = ctx->hdev;
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	u32 page_size = prop->pmmu.page_size;
+	int rc;
+
+	if (!hdev->supports_cb_mapping) {
+		dev_err_ratelimited(hdev->dev,
+				"Mapping a CB to the device's MMU is not supported\n");
+		return -EINVAL;
+	}
+
+	if (cb->is_mmu_mapped)
+		return 0;
+
+	cb->roundup_size = roundup(cb->size, page_size);
+
+	cb->virtual_addr = (u64) gen_pool_alloc(ctx->cb_va_pool, cb->roundup_size);
+	if (!cb->virtual_addr) {
+		dev_err(hdev->dev, "Failed to allocate device virtual address for CB\n");
+		return -ENOMEM;
+	}
+
+	mutex_lock(&hdev->mmu_lock);
+
+	rc = hl_mmu_map_contiguous(ctx, cb->virtual_addr, cb->bus_address, cb->roundup_size);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to map VA %#llx to CB\n", cb->virtual_addr);
+		goto err_va_pool_free;
+	}
+
+	rc = hl_mmu_invalidate_cache(hdev, false, MMU_OP_USERPTR | MMU_OP_SKIP_LOW_CACHE_INV);
+	if (rc)
+		goto err_mmu_unmap;
+
+	mutex_unlock(&hdev->mmu_lock);
+
+	cb->is_mmu_mapped = true;
+
+	return 0;
+
+err_mmu_unmap:
+	hl_mmu_unmap_contiguous(ctx, cb->virtual_addr, cb->roundup_size);
+err_va_pool_free:
+	mutex_unlock(&hdev->mmu_lock);
+	gen_pool_free(ctx->cb_va_pool, cb->virtual_addr, cb->roundup_size);
+
+	return rc;
+}
+
+static void cb_unmap_mem(struct hl_ctx *ctx, struct hl_cb *cb)
+{
+	struct hl_device *hdev = ctx->hdev;
+
+	mutex_lock(&hdev->mmu_lock);
+	hl_mmu_unmap_contiguous(ctx, cb->virtual_addr, cb->roundup_size);
+	hl_mmu_invalidate_cache(hdev, true, MMU_OP_USERPTR);
+	mutex_unlock(&hdev->mmu_lock);
+
+	gen_pool_free(ctx->cb_va_pool, cb->virtual_addr, cb->roundup_size);
+}
+
+static void cb_fini(struct hl_device *hdev, struct hl_cb *cb)
+{
+	if (cb->is_internal)
+		gen_pool_free(hdev->internal_cb_pool,
+				(uintptr_t)cb->kernel_address, cb->size);
+	else
+		hl_asic_dma_free_coherent(hdev, cb->size, cb->kernel_address, cb->bus_address);
+
+	kfree(cb);
+}
+
+static void cb_do_release(struct hl_device *hdev, struct hl_cb *cb)
+{
+	if (cb->is_pool) {
+		atomic_set(&cb->is_handle_destroyed, 0);
+		spin_lock(&hdev->cb_pool_lock);
+		list_add(&cb->pool_list, &hdev->cb_pool);
+		spin_unlock(&hdev->cb_pool_lock);
+	} else {
+		cb_fini(hdev, cb);
+	}
+}
+
+static struct hl_cb *hl_cb_alloc(struct hl_device *hdev, u32 cb_size,
+					int ctx_id, bool internal_cb)
+{
+	struct hl_cb *cb = NULL;
+	u32 cb_offset;
+	void *p;
+
+	/*
+	 * We use of GFP_ATOMIC here because this function can be called from
+	 * the latency-sensitive code path for command submission. Due to H/W
+	 * limitations in some of the ASICs, the kernel must copy the user CB
+	 * that is designated for an external queue and actually enqueue
+	 * the kernel's copy. Hence, we must never sleep in this code section
+	 * and must use GFP_ATOMIC for all memory allocations.
+	 */
+	if (ctx_id == HL_KERNEL_ASID_ID && !hdev->disabled)
+		cb = kzalloc(sizeof(*cb), GFP_ATOMIC);
+
+	if (!cb)
+		cb = kzalloc(sizeof(*cb), GFP_KERNEL);
+
+	if (!cb)
+		return NULL;
+
+	if (internal_cb) {
+		p = (void *) gen_pool_alloc(hdev->internal_cb_pool, cb_size);
+		if (!p) {
+			kfree(cb);
+			return NULL;
+		}
+
+		cb_offset = p - hdev->internal_cb_pool_virt_addr;
+		cb->is_internal = true;
+		cb->bus_address =  hdev->internal_cb_va_base + cb_offset;
+	} else if (ctx_id == HL_KERNEL_ASID_ID) {
+		p = hl_asic_dma_alloc_coherent(hdev, cb_size, &cb->bus_address, GFP_ATOMIC);
+		if (!p)
+			p = hl_asic_dma_alloc_coherent(hdev, cb_size, &cb->bus_address, GFP_KERNEL);
+	} else {
+		p = hl_asic_dma_alloc_coherent(hdev, cb_size, &cb->bus_address,
+						GFP_USER | __GFP_ZERO);
+	}
+
+	if (!p) {
+		dev_err(hdev->dev,
+			"failed to allocate %d of dma memory for CB\n",
+			cb_size);
+		kfree(cb);
+		return NULL;
+	}
+
+	cb->kernel_address = p;
+	cb->size = cb_size;
+
+	return cb;
+}
+
+struct hl_cb_mmap_mem_alloc_args {
+	struct hl_device *hdev;
+	struct hl_ctx *ctx;
+	u32 cb_size;
+	bool internal_cb;
+	bool map_cb;
+};
+
+static void hl_cb_mmap_mem_release(struct hl_mmap_mem_buf *buf)
+{
+	struct hl_cb *cb = buf->private;
+
+	hl_debugfs_remove_cb(cb);
+
+	if (cb->is_mmu_mapped)
+		cb_unmap_mem(cb->ctx, cb);
+
+	hl_ctx_put(cb->ctx);
+
+	cb_do_release(cb->hdev, cb);
+}
+
+static int hl_cb_mmap_mem_alloc(struct hl_mmap_mem_buf *buf, gfp_t gfp, void *args)
+{
+	struct hl_cb_mmap_mem_alloc_args *cb_args = args;
+	struct hl_cb *cb;
+	int rc, ctx_id = cb_args->ctx->asid;
+	bool alloc_new_cb = true;
+
+	if (!cb_args->internal_cb) {
+		/* Minimum allocation must be PAGE SIZE */
+		if (cb_args->cb_size < PAGE_SIZE)
+			cb_args->cb_size = PAGE_SIZE;
+
+		if (ctx_id == HL_KERNEL_ASID_ID &&
+				cb_args->cb_size <= cb_args->hdev->asic_prop.cb_pool_cb_size) {
+
+			spin_lock(&cb_args->hdev->cb_pool_lock);
+			if (!list_empty(&cb_args->hdev->cb_pool)) {
+				cb = list_first_entry(&cb_args->hdev->cb_pool,
+						typeof(*cb), pool_list);
+				list_del(&cb->pool_list);
+				spin_unlock(&cb_args->hdev->cb_pool_lock);
+				alloc_new_cb = false;
+			} else {
+				spin_unlock(&cb_args->hdev->cb_pool_lock);
+				dev_dbg(cb_args->hdev->dev, "CB pool is empty\n");
+			}
+		}
+	}
+
+	if (alloc_new_cb) {
+		cb = hl_cb_alloc(cb_args->hdev, cb_args->cb_size, ctx_id, cb_args->internal_cb);
+		if (!cb)
+			return -ENOMEM;
+	}
+
+	cb->hdev = cb_args->hdev;
+	cb->ctx = cb_args->ctx;
+	cb->buf = buf;
+	cb->buf->mappable_size = cb->size;
+	cb->buf->private = cb;
+
+	hl_ctx_get(cb->ctx);
+
+	if (cb_args->map_cb) {
+		if (ctx_id == HL_KERNEL_ASID_ID) {
+			dev_err(cb_args->hdev->dev,
+				"CB mapping is not supported for kernel context\n");
+			rc = -EINVAL;
+			goto release_cb;
+		}
+
+		rc = cb_map_mem(cb_args->ctx, cb);
+		if (rc)
+			goto release_cb;
+	}
+
+	hl_debugfs_add_cb(cb);
+
+	return 0;
+
+release_cb:
+	hl_ctx_put(cb->ctx);
+	cb_do_release(cb_args->hdev, cb);
+
+	return rc;
+}
+
+static int hl_cb_mmap(struct hl_mmap_mem_buf *buf,
+				      struct vm_area_struct *vma, void *args)
+{
+	struct hl_cb *cb = buf->private;
+
+	return cb->hdev->asic_funcs->mmap(cb->hdev, vma, cb->kernel_address,
+					cb->bus_address, cb->size);
+}
+
+static struct hl_mmap_mem_buf_behavior cb_behavior = {
+	.topic = "CB",
+	.mem_id = HL_MMAP_TYPE_CB,
+	.alloc = hl_cb_mmap_mem_alloc,
+	.release = hl_cb_mmap_mem_release,
+	.mmap = hl_cb_mmap,
+};
+
+int hl_cb_create(struct hl_device *hdev, struct hl_mem_mgr *mmg,
+			struct hl_ctx *ctx, u32 cb_size, bool internal_cb,
+			bool map_cb, u64 *handle)
+{
+	struct hl_cb_mmap_mem_alloc_args args = {
+		.hdev = hdev,
+		.ctx = ctx,
+		.cb_size = cb_size,
+		.internal_cb = internal_cb,
+		.map_cb = map_cb,
+	};
+	struct hl_mmap_mem_buf *buf;
+	int ctx_id = ctx->asid;
+
+	if ((hdev->disabled) || (hdev->reset_info.in_reset && (ctx_id != HL_KERNEL_ASID_ID))) {
+		dev_warn_ratelimited(hdev->dev,
+			"Device is disabled or in reset. Can't create new CBs\n");
+		return -EBUSY;
+	}
+
+	if (cb_size > SZ_2M) {
+		dev_err(hdev->dev, "CB size %d must be less than %d\n",
+			cb_size, SZ_2M);
+		return -EINVAL;
+	}
+
+	buf = hl_mmap_mem_buf_alloc(
+		mmg, &cb_behavior,
+		ctx_id == HL_KERNEL_ASID_ID ? GFP_ATOMIC : GFP_KERNEL, &args);
+	if (!buf)
+		return -ENOMEM;
+
+	*handle = buf->handle;
+
+	return 0;
+}
+
+int hl_cb_destroy(struct hl_mem_mgr *mmg, u64 cb_handle)
+{
+	struct hl_cb *cb;
+	int rc;
+
+	cb = hl_cb_get(mmg, cb_handle);
+	if (!cb) {
+		dev_dbg(mmg->dev, "CB destroy failed, no CB was found for handle %#llx\n",
+			cb_handle);
+		return -EINVAL;
+	}
+
+	/* Make sure that CB handle isn't destroyed more than once */
+	rc = atomic_cmpxchg(&cb->is_handle_destroyed, 0, 1);
+	hl_cb_put(cb);
+	if (rc) {
+		dev_dbg(mmg->dev, "CB destroy failed, handle %#llx was already destroyed\n",
+			cb_handle);
+		return -EINVAL;
+	}
+
+	rc = hl_mmap_mem_buf_put_handle(mmg, cb_handle);
+	if (rc < 0)
+		return rc; /* Invalid handle */
+
+	if (rc == 0)
+		dev_dbg(mmg->dev, "CB 0x%llx is destroyed while still in use\n", cb_handle);
+
+	return 0;
+}
+
+static int hl_cb_info(struct hl_mem_mgr *mmg,
+			u64 handle, u32 flags, u32 *usage_cnt, u64 *device_va)
+{
+	struct hl_cb *cb;
+	int rc = 0;
+
+	cb = hl_cb_get(mmg, handle);
+	if (!cb) {
+		dev_err(mmg->dev,
+			"CB info failed, no match to handle 0x%llx\n", handle);
+		return -EINVAL;
+	}
+
+	if (flags & HL_CB_FLAGS_GET_DEVICE_VA) {
+		if (cb->is_mmu_mapped) {
+			*device_va = cb->virtual_addr;
+		} else {
+			dev_err(mmg->dev, "CB is not mapped to the device's MMU\n");
+			rc = -EINVAL;
+			goto out;
+		}
+	} else {
+		*usage_cnt = atomic_read(&cb->cs_cnt);
+	}
+
+out:
+	hl_cb_put(cb);
+	return rc;
+}
+
+int hl_cb_ioctl(struct drm_device *ddev, void *data, struct drm_file *file_priv)
+{
+	struct hl_fpriv *hpriv = file_priv->driver_priv;
+	struct hl_device *hdev = hpriv->hdev;
+	union hl_cb_args *args = data;
+	u64 handle = 0, device_va = 0;
+	enum hl_device_status status;
+	u32 usage_cnt = 0;
+	int rc;
+
+	if (!hl_device_operational(hdev, &status)) {
+		dev_dbg_ratelimited(hdev->dev,
+			"Device is %s. Can't execute CB IOCTL\n",
+			hdev->status[status]);
+		return -EBUSY;
+	}
+
+	switch (args->in.op) {
+	case HL_CB_OP_CREATE:
+		if (args->in.cb_size > HL_MAX_CB_SIZE) {
+			dev_err(hdev->dev,
+				"User requested CB size %d must be less than %d\n",
+				args->in.cb_size, HL_MAX_CB_SIZE);
+			rc = -EINVAL;
+		} else {
+			rc = hl_cb_create(hdev, &hpriv->mem_mgr, hpriv->ctx,
+					args->in.cb_size, false,
+					!!(args->in.flags & HL_CB_FLAGS_MAP),
+					&handle);
+		}
+
+		memset(args, 0, sizeof(*args));
+		args->out.cb_handle = handle;
+		break;
+
+	case HL_CB_OP_DESTROY:
+		rc = hl_cb_destroy(&hpriv->mem_mgr,
+					args->in.cb_handle);
+		break;
+
+	case HL_CB_OP_INFO:
+		rc = hl_cb_info(&hpriv->mem_mgr, args->in.cb_handle,
+				args->in.flags,
+				&usage_cnt,
+				&device_va);
+		if (rc)
+			break;
+
+		memset(&args->out, 0, sizeof(args->out));
+
+		if (args->in.flags & HL_CB_FLAGS_GET_DEVICE_VA)
+			args->out.device_va = device_va;
+		else
+			args->out.usage_cnt = usage_cnt;
+		break;
+
+	default:
+		rc = -EINVAL;
+		break;
+	}
+
+	return rc;
+}
+
+struct hl_cb *hl_cb_get(struct hl_mem_mgr *mmg, u64 handle)
+{
+	struct hl_mmap_mem_buf *buf;
+
+	buf = hl_mmap_mem_buf_get(mmg, handle);
+	if (!buf)
+		return NULL;
+	return buf->private;
+
+}
+
+void hl_cb_put(struct hl_cb *cb)
+{
+	hl_mmap_mem_buf_put(cb->buf);
+}
+
+struct hl_cb *hl_cb_kernel_create(struct hl_device *hdev, u32 cb_size,
+					bool internal_cb)
+{
+	u64 cb_handle;
+	struct hl_cb *cb;
+	int rc;
+
+	rc = hl_cb_create(hdev, &hdev->kernel_mem_mgr, hdev->kernel_ctx, cb_size,
+				internal_cb, false, &cb_handle);
+	if (rc) {
+		dev_err(hdev->dev,
+			"Failed to allocate CB for the kernel driver %d\n", rc);
+		return NULL;
+	}
+
+	cb = hl_cb_get(&hdev->kernel_mem_mgr, cb_handle);
+	/* hl_cb_get should never fail here */
+	if (!cb) {
+		dev_crit(hdev->dev, "Kernel CB handle invalid 0x%x\n",
+				(u32) cb_handle);
+		goto destroy_cb;
+	}
+
+	return cb;
+
+destroy_cb:
+	hl_cb_destroy(&hdev->kernel_mem_mgr, cb_handle);
+
+	return NULL;
+}
+
+int hl_cb_pool_init(struct hl_device *hdev)
+{
+	struct hl_cb *cb;
+	int i;
+
+	INIT_LIST_HEAD(&hdev->cb_pool);
+	spin_lock_init(&hdev->cb_pool_lock);
+
+	for (i = 0 ; i < hdev->asic_prop.cb_pool_cb_cnt ; i++) {
+		cb = hl_cb_alloc(hdev, hdev->asic_prop.cb_pool_cb_size,
+				HL_KERNEL_ASID_ID, false);
+		if (cb) {
+			cb->is_pool = true;
+			list_add(&cb->pool_list, &hdev->cb_pool);
+		} else {
+			hl_cb_pool_fini(hdev);
+			return -ENOMEM;
+		}
+	}
+
+	return 0;
+}
+
+int hl_cb_pool_fini(struct hl_device *hdev)
+{
+	struct hl_cb *cb, *tmp;
+
+	list_for_each_entry_safe(cb, tmp, &hdev->cb_pool, pool_list) {
+		list_del(&cb->pool_list);
+		cb_fini(hdev, cb);
+	}
+
+	return 0;
+}
+
+int hl_cb_va_pool_init(struct hl_ctx *ctx)
+{
+	struct hl_device *hdev = ctx->hdev;
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	int rc;
+
+	if (!hdev->supports_cb_mapping)
+		return 0;
+
+	ctx->cb_va_pool = gen_pool_create(__ffs(prop->pmmu.page_size), -1);
+	if (!ctx->cb_va_pool) {
+		dev_err(hdev->dev,
+			"Failed to create VA gen pool for CB mapping\n");
+		return -ENOMEM;
+	}
+
+	ctx->cb_va_pool_base = hl_reserve_va_block(hdev, ctx, HL_VA_RANGE_TYPE_HOST,
+					CB_VA_POOL_SIZE, HL_MMU_VA_ALIGNMENT_NOT_NEEDED);
+	if (!ctx->cb_va_pool_base) {
+		rc = -ENOMEM;
+		goto err_pool_destroy;
+	}
+	rc = gen_pool_add(ctx->cb_va_pool, ctx->cb_va_pool_base, CB_VA_POOL_SIZE, -1);
+	if (rc) {
+		dev_err(hdev->dev,
+			"Failed to add memory to VA gen pool for CB mapping\n");
+		goto err_unreserve_va_block;
+	}
+
+	return 0;
+
+err_unreserve_va_block:
+	hl_unreserve_va_block(hdev, ctx, ctx->cb_va_pool_base, CB_VA_POOL_SIZE);
+err_pool_destroy:
+	gen_pool_destroy(ctx->cb_va_pool);
+
+	return rc;
+}
+
+void hl_cb_va_pool_fini(struct hl_ctx *ctx)
+{
+	struct hl_device *hdev = ctx->hdev;
+
+	if (!hdev->supports_cb_mapping)
+		return;
+
+	gen_pool_destroy(ctx->cb_va_pool);
+	hl_unreserve_va_block(hdev, ctx, ctx->cb_va_pool_base, CB_VA_POOL_SIZE);
+}
diff --git a/drivers/accel/habanalabs/common/command_submission.c b/drivers/accel/habanalabs/common/command_submission.c
new file mode 100644
index 000000000000..dee487724918
--- /dev/null
+++ b/drivers/accel/habanalabs/common/command_submission.c
@@ -0,0 +1,3744 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Copyright 2016-2021 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ */
+
+#include <uapi/drm/habanalabs_accel.h>
+#include "habanalabs.h"
+
+#include <linux/uaccess.h>
+#include <linux/slab.h>
+
+#define HL_CS_FLAGS_TYPE_MASK	(HL_CS_FLAGS_SIGNAL | HL_CS_FLAGS_WAIT | \
+			HL_CS_FLAGS_COLLECTIVE_WAIT | HL_CS_FLAGS_RESERVE_SIGNALS_ONLY | \
+			HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY | HL_CS_FLAGS_ENGINE_CORE_COMMAND | \
+			HL_CS_FLAGS_ENGINES_COMMAND | HL_CS_FLAGS_FLUSH_PCI_HBW_WRITES)
+
+
+#define MAX_TS_ITER_NUM 100
+
+/**
+ * enum hl_cs_wait_status - cs wait status
+ * @CS_WAIT_STATUS_BUSY: cs was not completed yet
+ * @CS_WAIT_STATUS_COMPLETED: cs completed
+ * @CS_WAIT_STATUS_GONE: cs completed but fence is already gone
+ */
+enum hl_cs_wait_status {
+	CS_WAIT_STATUS_BUSY,
+	CS_WAIT_STATUS_COMPLETED,
+	CS_WAIT_STATUS_GONE
+};
+
+/*
+ * Data used while handling wait/timestamp nodes.
+ * The purpose of this struct is to store the needed data for both operations
+ * in one variable instead of passing large number of arguments to functions.
+ */
+struct wait_interrupt_data {
+	struct hl_user_interrupt *interrupt;
+	struct hl_mmap_mem_buf *buf;
+	struct hl_mem_mgr *mmg;
+	struct hl_cb *cq_cb;
+	u64 ts_handle;
+	u64 ts_offset;
+	u64 cq_handle;
+	u64 cq_offset;
+	u64 target_value;
+	u64 intr_timeout_us;
+};
+
+static void job_wq_completion(struct work_struct *work);
+static int _hl_cs_wait_ioctl(struct hl_device *hdev, struct hl_ctx *ctx, u64 timeout_us, u64 seq,
+				enum hl_cs_wait_status *status, s64 *timestamp);
+static void cs_do_release(struct kref *ref);
+
+static void hl_push_cs_outcome(struct hl_device *hdev,
+			       struct hl_cs_outcome_store *outcome_store,
+			       u64 seq, ktime_t ts, int error)
+{
+	struct hl_cs_outcome *node;
+	unsigned long flags;
+
+	/*
+	 * CS outcome store supports the following operations:
+	 * push outcome - store a recent CS outcome in the store
+	 * pop outcome - retrieve a SPECIFIC (by seq) CS outcome from the store
+	 * It uses 2 lists: used list and free list.
+	 * It has a pre-allocated amount of nodes, each node stores
+	 * a single CS outcome.
+	 * Initially, all the nodes are in the free list.
+	 * On push outcome, a node (any) is taken from the free list, its
+	 * information is filled in, and the node is moved to the used list.
+	 * It is possible, that there are no nodes left in the free list.
+	 * In this case, we will lose some information about old outcomes. We
+	 * will pop the OLDEST node from the used list, and make it free.
+	 * On pop, the node is searched for in the used list (using a search
+	 * index).
+	 * If found, the node is then removed from the used list, and moved
+	 * back to the free list. The outcome data that the node contained is
+	 * returned back to the user.
+	 */
+
+	spin_lock_irqsave(&outcome_store->db_lock, flags);
+
+	if (list_empty(&outcome_store->free_list)) {
+		node = list_last_entry(&outcome_store->used_list,
+				       struct hl_cs_outcome, list_link);
+		hash_del(&node->map_link);
+		dev_dbg(hdev->dev, "CS %llu outcome was lost\n", node->seq);
+	} else {
+		node = list_last_entry(&outcome_store->free_list,
+				       struct hl_cs_outcome, list_link);
+	}
+
+	list_del_init(&node->list_link);
+
+	node->seq = seq;
+	node->ts = ts;
+	node->error = error;
+
+	list_add(&node->list_link, &outcome_store->used_list);
+	hash_add(outcome_store->outcome_map, &node->map_link, node->seq);
+
+	spin_unlock_irqrestore(&outcome_store->db_lock, flags);
+}
+
+static bool hl_pop_cs_outcome(struct hl_cs_outcome_store *outcome_store,
+			       u64 seq, ktime_t *ts, int *error)
+{
+	struct hl_cs_outcome *node;
+	unsigned long flags;
+
+	spin_lock_irqsave(&outcome_store->db_lock, flags);
+
+	hash_for_each_possible(outcome_store->outcome_map, node, map_link, seq)
+		if (node->seq == seq) {
+			*ts = node->ts;
+			*error = node->error;
+
+			hash_del(&node->map_link);
+			list_del_init(&node->list_link);
+			list_add(&node->list_link, &outcome_store->free_list);
+
+			spin_unlock_irqrestore(&outcome_store->db_lock, flags);
+
+			return true;
+		}
+
+	spin_unlock_irqrestore(&outcome_store->db_lock, flags);
+
+	return false;
+}
+
+static void hl_sob_reset(struct kref *ref)
+{
+	struct hl_hw_sob *hw_sob = container_of(ref, struct hl_hw_sob,
+							kref);
+	struct hl_device *hdev = hw_sob->hdev;
+
+	dev_dbg(hdev->dev, "reset sob id %u\n", hw_sob->sob_id);
+
+	hdev->asic_funcs->reset_sob(hdev, hw_sob);
+
+	hw_sob->need_reset = false;
+}
+
+void hl_sob_reset_error(struct kref *ref)
+{
+	struct hl_hw_sob *hw_sob = container_of(ref, struct hl_hw_sob,
+							kref);
+	struct hl_device *hdev = hw_sob->hdev;
+
+	dev_crit(hdev->dev,
+		"SOB release shouldn't be called here, q_idx: %d, sob_id: %d\n",
+		hw_sob->q_idx, hw_sob->sob_id);
+}
+
+void hw_sob_put(struct hl_hw_sob *hw_sob)
+{
+	if (hw_sob)
+		kref_put(&hw_sob->kref, hl_sob_reset);
+}
+
+static void hw_sob_put_err(struct hl_hw_sob *hw_sob)
+{
+	if (hw_sob)
+		kref_put(&hw_sob->kref, hl_sob_reset_error);
+}
+
+void hw_sob_get(struct hl_hw_sob *hw_sob)
+{
+	if (hw_sob)
+		kref_get(&hw_sob->kref);
+}
+
+/**
+ * hl_gen_sob_mask() - Generates a sob mask to be used in a monitor arm packet
+ * @sob_base: sob base id
+ * @sob_mask: sob user mask, each bit represents a sob offset from sob base
+ * @mask: generated mask
+ *
+ * Return: 0 if given parameters are valid
+ */
+int hl_gen_sob_mask(u16 sob_base, u8 sob_mask, u8 *mask)
+{
+	int i;
+
+	if (sob_mask == 0)
+		return -EINVAL;
+
+	if (sob_mask == 0x1) {
+		*mask = ~(1 << (sob_base & 0x7));
+	} else {
+		/* find msb in order to verify sob range is valid */
+		for (i = BITS_PER_BYTE - 1 ; i >= 0 ; i--)
+			if (BIT(i) & sob_mask)
+				break;
+
+		if (i > (HL_MAX_SOBS_PER_MONITOR - (sob_base & 0x7) - 1))
+			return -EINVAL;
+
+		*mask = ~sob_mask;
+	}
+
+	return 0;
+}
+
+static void hl_fence_release(struct kref *kref)
+{
+	struct hl_fence *fence =
+		container_of(kref, struct hl_fence, refcount);
+	struct hl_cs_compl *hl_cs_cmpl =
+		container_of(fence, struct hl_cs_compl, base_fence);
+
+	kfree(hl_cs_cmpl);
+}
+
+void hl_fence_put(struct hl_fence *fence)
+{
+	if (IS_ERR_OR_NULL(fence))
+		return;
+	kref_put(&fence->refcount, hl_fence_release);
+}
+
+void hl_fences_put(struct hl_fence **fence, int len)
+{
+	int i;
+
+	for (i = 0; i < len; i++, fence++)
+		hl_fence_put(*fence);
+}
+
+void hl_fence_get(struct hl_fence *fence)
+{
+	if (fence)
+		kref_get(&fence->refcount);
+}
+
+static void hl_fence_init(struct hl_fence *fence, u64 sequence)
+{
+	kref_init(&fence->refcount);
+	fence->cs_sequence = sequence;
+	fence->error = 0;
+	fence->timestamp = ktime_set(0, 0);
+	fence->mcs_handling_done = false;
+	init_completion(&fence->completion);
+}
+
+void cs_get(struct hl_cs *cs)
+{
+	kref_get(&cs->refcount);
+}
+
+static int cs_get_unless_zero(struct hl_cs *cs)
+{
+	return kref_get_unless_zero(&cs->refcount);
+}
+
+static void cs_put(struct hl_cs *cs)
+{
+	kref_put(&cs->refcount, cs_do_release);
+}
+
+static void cs_job_do_release(struct kref *ref)
+{
+	struct hl_cs_job *job = container_of(ref, struct hl_cs_job, refcount);
+
+	kfree(job);
+}
+
+static void hl_cs_job_put(struct hl_cs_job *job)
+{
+	kref_put(&job->refcount, cs_job_do_release);
+}
+
+bool cs_needs_completion(struct hl_cs *cs)
+{
+	/* In case this is a staged CS, only the last CS in sequence should
+	 * get a completion, any non staged CS will always get a completion
+	 */
+	if (cs->staged_cs && !cs->staged_last)
+		return false;
+
+	return true;
+}
+
+bool cs_needs_timeout(struct hl_cs *cs)
+{
+	/* In case this is a staged CS, only the first CS in sequence should
+	 * get a timeout, any non staged CS will always get a timeout
+	 */
+	if (cs->staged_cs && !cs->staged_first)
+		return false;
+
+	return true;
+}
+
+static bool is_cb_patched(struct hl_device *hdev, struct hl_cs_job *job)
+{
+	/* Patched CB is created for external queues jobs */
+	return (job->queue_type == QUEUE_TYPE_EXT);
+}
+
+/*
+ * cs_parser - parse the user command submission
+ *
+ * @hpriv	: pointer to the private data of the fd
+ * @job        : pointer to the job that holds the command submission info
+ *
+ * The function parses the command submission of the user. It calls the
+ * ASIC specific parser, which returns a list of memory blocks to send
+ * to the device as different command buffers
+ *
+ */
+static int cs_parser(struct hl_fpriv *hpriv, struct hl_cs_job *job)
+{
+	struct hl_device *hdev = hpriv->hdev;
+	struct hl_cs_parser parser;
+	int rc;
+
+	parser.ctx_id = job->cs->ctx->asid;
+	parser.cs_sequence = job->cs->sequence;
+	parser.job_id = job->id;
+
+	parser.hw_queue_id = job->hw_queue_id;
+	parser.job_userptr_list = &job->userptr_list;
+	parser.patched_cb = NULL;
+	parser.user_cb = job->user_cb;
+	parser.user_cb_size = job->user_cb_size;
+	parser.queue_type = job->queue_type;
+	parser.is_kernel_allocated_cb = job->is_kernel_allocated_cb;
+	job->patched_cb = NULL;
+	parser.completion = cs_needs_completion(job->cs);
+
+	rc = hdev->asic_funcs->cs_parser(hdev, &parser);
+
+	if (is_cb_patched(hdev, job)) {
+		if (!rc) {
+			job->patched_cb = parser.patched_cb;
+			job->job_cb_size = parser.patched_cb_size;
+			job->contains_dma_pkt = parser.contains_dma_pkt;
+			atomic_inc(&job->patched_cb->cs_cnt);
+		}
+
+		/*
+		 * Whether the parsing worked or not, we don't need the
+		 * original CB anymore because it was already parsed and
+		 * won't be accessed again for this CS
+		 */
+		atomic_dec(&job->user_cb->cs_cnt);
+		hl_cb_put(job->user_cb);
+		job->user_cb = NULL;
+	} else if (!rc) {
+		job->job_cb_size = job->user_cb_size;
+	}
+
+	return rc;
+}
+
+static void hl_complete_job(struct hl_device *hdev, struct hl_cs_job *job)
+{
+	struct hl_cs *cs = job->cs;
+
+	if (is_cb_patched(hdev, job)) {
+		hl_userptr_delete_list(hdev, &job->userptr_list);
+
+		/*
+		 * We might arrive here from rollback and patched CB wasn't
+		 * created, so we need to check it's not NULL
+		 */
+		if (job->patched_cb) {
+			atomic_dec(&job->patched_cb->cs_cnt);
+			hl_cb_put(job->patched_cb);
+		}
+	}
+
+	/* For H/W queue jobs, if a user CB was allocated by driver,
+	 * the user CB isn't released in cs_parser() and thus should be
+	 * released here. This is also true for INT queues jobs which were
+	 * allocated by driver.
+	 */
+	if (job->is_kernel_allocated_cb &&
+			(job->queue_type == QUEUE_TYPE_HW || job->queue_type == QUEUE_TYPE_INT)) {
+		atomic_dec(&job->user_cb->cs_cnt);
+		hl_cb_put(job->user_cb);
+	}
+
+	/*
+	 * This is the only place where there can be multiple threads
+	 * modifying the list at the same time
+	 */
+	spin_lock(&cs->job_lock);
+	list_del(&job->cs_node);
+	spin_unlock(&cs->job_lock);
+
+	hl_debugfs_remove_job(hdev, job);
+
+	/* We decrement reference only for a CS that gets completion
+	 * because the reference was incremented only for this kind of CS
+	 * right before it was scheduled.
+	 *
+	 * In staged submission, only the last CS marked as 'staged_last'
+	 * gets completion, hence its release function will be called from here.
+	 * As for all the rest CS's in the staged submission which do not get
+	 * completion, their CS reference will be decremented by the
+	 * 'staged_last' CS during the CS release flow.
+	 * All relevant PQ CI counters will be incremented during the CS release
+	 * flow by calling 'hl_hw_queue_update_ci'.
+	 */
+	if (cs_needs_completion(cs) &&
+			(job->queue_type == QUEUE_TYPE_EXT || job->queue_type == QUEUE_TYPE_HW)) {
+
+		/* In CS based completions, the timestamp is already available,
+		 * so no need to extract it from job
+		 */
+		if (hdev->asic_prop.completion_mode == HL_COMPLETION_MODE_JOB)
+			cs->completion_timestamp = job->timestamp;
+
+		cs_put(cs);
+	}
+
+	hl_cs_job_put(job);
+}
+
+/*
+ * hl_staged_cs_find_first - locate the first CS in this staged submission
+ *
+ * @hdev: pointer to device structure
+ * @cs_seq: staged submission sequence number
+ *
+ * @note: This function must be called under 'hdev->cs_mirror_lock'
+ *
+ * Find and return a CS pointer with the given sequence
+ */
+struct hl_cs *hl_staged_cs_find_first(struct hl_device *hdev, u64 cs_seq)
+{
+	struct hl_cs *cs;
+
+	list_for_each_entry_reverse(cs, &hdev->cs_mirror_list, mirror_node)
+		if (cs->staged_cs && cs->staged_first &&
+				cs->sequence == cs_seq)
+			return cs;
+
+	return NULL;
+}
+
+/*
+ * is_staged_cs_last_exists - returns true if the last CS in sequence exists
+ *
+ * @hdev: pointer to device structure
+ * @cs: staged submission member
+ *
+ */
+bool is_staged_cs_last_exists(struct hl_device *hdev, struct hl_cs *cs)
+{
+	struct hl_cs *last_entry;
+
+	last_entry = list_last_entry(&cs->staged_cs_node, struct hl_cs,
+								staged_cs_node);
+
+	if (last_entry->staged_last)
+		return true;
+
+	return false;
+}
+
+/*
+ * staged_cs_get - get CS reference if this CS is a part of a staged CS
+ *
+ * @hdev: pointer to device structure
+ * @cs: current CS
+ * @cs_seq: staged submission sequence number
+ *
+ * Increment CS reference for every CS in this staged submission except for
+ * the CS which get completion.
+ */
+static void staged_cs_get(struct hl_device *hdev, struct hl_cs *cs)
+{
+	/* Only the last CS in this staged submission will get a completion.
+	 * We must increment the reference for all other CS's in this
+	 * staged submission.
+	 * Once we get a completion we will release the whole staged submission.
+	 */
+	if (!cs->staged_last)
+		cs_get(cs);
+}
+
+/*
+ * staged_cs_put - put a CS in case it is part of staged submission
+ *
+ * @hdev: pointer to device structure
+ * @cs: CS to put
+ *
+ * This function decrements a CS reference (for a non completion CS)
+ */
+static void staged_cs_put(struct hl_device *hdev, struct hl_cs *cs)
+{
+	/* We release all CS's in a staged submission except the last
+	 * CS which we have never incremented its reference.
+	 */
+	if (!cs_needs_completion(cs))
+		cs_put(cs);
+}
+
+static void cs_handle_tdr(struct hl_device *hdev, struct hl_cs *cs)
+{
+	struct hl_cs *next = NULL, *iter, *first_cs;
+
+	if (!cs_needs_timeout(cs))
+		return;
+
+	spin_lock(&hdev->cs_mirror_lock);
+
+	/* We need to handle tdr only once for the complete staged submission.
+	 * Hence, we choose the CS that reaches this function first which is
+	 * the CS marked as 'staged_last'.
+	 * In case single staged cs was submitted which has both first and last
+	 * indications, then "cs_find_first" below will return NULL, since we
+	 * removed the cs node from the list before getting here,
+	 * in such cases just continue with the cs to cancel it's TDR work.
+	 */
+	if (cs->staged_cs && cs->staged_last) {
+		first_cs = hl_staged_cs_find_first(hdev, cs->staged_sequence);
+		if (first_cs)
+			cs = first_cs;
+	}
+
+	spin_unlock(&hdev->cs_mirror_lock);
+
+	/* Don't cancel TDR in case this CS was timedout because we might be
+	 * running from the TDR context
+	 */
+	if (cs->timedout || hdev->timeout_jiffies == MAX_SCHEDULE_TIMEOUT)
+		return;
+
+	if (cs->tdr_active)
+		cancel_delayed_work_sync(&cs->work_tdr);
+
+	spin_lock(&hdev->cs_mirror_lock);
+
+	/* queue TDR for next CS */
+	list_for_each_entry(iter, &hdev->cs_mirror_list, mirror_node)
+		if (cs_needs_timeout(iter)) {
+			next = iter;
+			break;
+		}
+
+	if (next && !next->tdr_active) {
+		next->tdr_active = true;
+		schedule_delayed_work(&next->work_tdr, next->timeout_jiffies);
+	}
+
+	spin_unlock(&hdev->cs_mirror_lock);
+}
+
+/*
+ * force_complete_multi_cs - complete all contexts that wait on multi-CS
+ *
+ * @hdev: pointer to habanalabs device structure
+ */
+static void force_complete_multi_cs(struct hl_device *hdev)
+{
+	int i;
+
+	for (i = 0; i < MULTI_CS_MAX_USER_CTX; i++) {
+		struct multi_cs_completion *mcs_compl;
+
+		mcs_compl = &hdev->multi_cs_completion[i];
+
+		spin_lock(&mcs_compl->lock);
+
+		if (!mcs_compl->used) {
+			spin_unlock(&mcs_compl->lock);
+			continue;
+		}
+
+		/* when calling force complete no context should be waiting on
+		 * multi-cS.
+		 * We are calling the function as a protection for such case
+		 * to free any pending context and print error message
+		 */
+		dev_err(hdev->dev,
+				"multi-CS completion context %d still waiting when calling force completion\n",
+				i);
+		complete_all(&mcs_compl->completion);
+		spin_unlock(&mcs_compl->lock);
+	}
+}
+
+/*
+ * complete_multi_cs - complete all waiting entities on multi-CS
+ *
+ * @hdev: pointer to habanalabs device structure
+ * @cs: CS structure
+ * The function signals a waiting entity that has an overlapping stream masters
+ * with the completed CS.
+ * For example:
+ * - a completed CS worked on stream master QID 4, multi CS completion
+ *   is actively waiting on stream master QIDs 3, 5. don't send signal as no
+ *   common stream master QID
+ * - a completed CS worked on stream master QID 4, multi CS completion
+ *   is actively waiting on stream master QIDs 3, 4. send signal as stream
+ *   master QID 4 is common
+ */
+static void complete_multi_cs(struct hl_device *hdev, struct hl_cs *cs)
+{
+	struct hl_fence *fence = cs->fence;
+	int i;
+
+	/* in case of multi CS check for completion only for the first CS */
+	if (cs->staged_cs && !cs->staged_first)
+		return;
+
+	for (i = 0; i < MULTI_CS_MAX_USER_CTX; i++) {
+		struct multi_cs_completion *mcs_compl;
+
+		mcs_compl = &hdev->multi_cs_completion[i];
+		if (!mcs_compl->used)
+			continue;
+
+		spin_lock(&mcs_compl->lock);
+
+		/*
+		 * complete if:
+		 * 1. still waiting for completion
+		 * 2. the completed CS has at least one overlapping stream
+		 *    master with the stream masters in the completion
+		 */
+		if (mcs_compl->used &&
+				(fence->stream_master_qid_map &
+					mcs_compl->stream_master_qid_map)) {
+			/* extract the timestamp only of first completed CS */
+			if (!mcs_compl->timestamp)
+				mcs_compl->timestamp = ktime_to_ns(fence->timestamp);
+
+			complete_all(&mcs_compl->completion);
+
+			/*
+			 * Setting mcs_handling_done inside the lock ensures
+			 * at least one fence have mcs_handling_done set to
+			 * true before wait for mcs finish. This ensures at
+			 * least one CS will be set as completed when polling
+			 * mcs fences.
+			 */
+			fence->mcs_handling_done = true;
+		}
+
+		spin_unlock(&mcs_compl->lock);
+	}
+	/* In case CS completed without mcs completion initialized */
+	fence->mcs_handling_done = true;
+}
+
+static inline void cs_release_sob_reset_handler(struct hl_device *hdev,
+					struct hl_cs *cs,
+					struct hl_cs_compl *hl_cs_cmpl)
+{
+	/* Skip this handler if the cs wasn't submitted, to avoid putting
+	 * the hw_sob twice, since this case already handled at this point,
+	 * also skip if the hw_sob pointer wasn't set.
+	 */
+	if (!hl_cs_cmpl->hw_sob || !cs->submitted)
+		return;
+
+	spin_lock(&hl_cs_cmpl->lock);
+
+	/*
+	 * we get refcount upon reservation of signals or signal/wait cs for the
+	 * hw_sob object, and need to put it when the first staged cs
+	 * (which contains the encaps signals) or cs signal/wait is completed.
+	 */
+	if ((hl_cs_cmpl->type == CS_TYPE_SIGNAL) ||
+			(hl_cs_cmpl->type == CS_TYPE_WAIT) ||
+			(hl_cs_cmpl->type == CS_TYPE_COLLECTIVE_WAIT) ||
+			(!!hl_cs_cmpl->encaps_signals)) {
+		dev_dbg(hdev->dev,
+				"CS 0x%llx type %d finished, sob_id: %d, sob_val: %u\n",
+				hl_cs_cmpl->cs_seq,
+				hl_cs_cmpl->type,
+				hl_cs_cmpl->hw_sob->sob_id,
+				hl_cs_cmpl->sob_val);
+
+		hw_sob_put(hl_cs_cmpl->hw_sob);
+
+		if (hl_cs_cmpl->type == CS_TYPE_COLLECTIVE_WAIT)
+			hdev->asic_funcs->reset_sob_group(hdev,
+					hl_cs_cmpl->sob_group);
+	}
+
+	spin_unlock(&hl_cs_cmpl->lock);
+}
+
+static void cs_do_release(struct kref *ref)
+{
+	struct hl_cs *cs = container_of(ref, struct hl_cs, refcount);
+	struct hl_device *hdev = cs->ctx->hdev;
+	struct hl_cs_job *job, *tmp;
+	struct hl_cs_compl *hl_cs_cmpl =
+			container_of(cs->fence, struct hl_cs_compl, base_fence);
+
+	cs->completed = true;
+
+	/*
+	 * Although if we reached here it means that all external jobs have
+	 * finished, because each one of them took refcnt to CS, we still
+	 * need to go over the internal jobs and complete them. Otherwise, we
+	 * will have leaked memory and what's worse, the CS object (and
+	 * potentially the CTX object) could be released, while the JOB
+	 * still holds a pointer to them (but no reference).
+	 */
+	list_for_each_entry_safe(job, tmp, &cs->job_list, cs_node)
+		hl_complete_job(hdev, job);
+
+	if (!cs->submitted) {
+		/*
+		 * In case the wait for signal CS was submitted, the fence put
+		 * occurs in init_signal_wait_cs() or collective_wait_init_cs()
+		 * right before hanging on the PQ.
+		 */
+		if (cs->type == CS_TYPE_WAIT ||
+				cs->type == CS_TYPE_COLLECTIVE_WAIT)
+			hl_fence_put(cs->signal_fence);
+
+		goto out;
+	}
+
+	/* Need to update CI for all queue jobs that does not get completion */
+	hl_hw_queue_update_ci(cs);
+
+	/* remove CS from CS mirror list */
+	spin_lock(&hdev->cs_mirror_lock);
+	list_del_init(&cs->mirror_node);
+	spin_unlock(&hdev->cs_mirror_lock);
+
+	cs_handle_tdr(hdev, cs);
+
+	if (cs->staged_cs) {
+		/* the completion CS decrements reference for the entire
+		 * staged submission
+		 */
+		if (cs->staged_last) {
+			struct hl_cs *staged_cs, *tmp_cs;
+
+			list_for_each_entry_safe(staged_cs, tmp_cs,
+					&cs->staged_cs_node, staged_cs_node)
+				staged_cs_put(hdev, staged_cs);
+		}
+
+		/* A staged CS will be a member in the list only after it
+		 * was submitted. We used 'cs_mirror_lock' when inserting
+		 * it to list so we will use it again when removing it
+		 */
+		if (cs->submitted) {
+			spin_lock(&hdev->cs_mirror_lock);
+			list_del(&cs->staged_cs_node);
+			spin_unlock(&hdev->cs_mirror_lock);
+		}
+
+		/* decrement refcount to handle when first staged cs
+		 * with encaps signals is completed.
+		 */
+		if (hl_cs_cmpl->encaps_signals)
+			kref_put(&hl_cs_cmpl->encaps_sig_hdl->refcount,
+					hl_encaps_release_handle_and_put_ctx);
+	}
+
+	if ((cs->type == CS_TYPE_WAIT || cs->type == CS_TYPE_COLLECTIVE_WAIT) && cs->encaps_signals)
+		kref_put(&cs->encaps_sig_hdl->refcount, hl_encaps_release_handle_and_put_ctx);
+
+out:
+	/* Must be called before hl_ctx_put because inside we use ctx to get
+	 * the device
+	 */
+	hl_debugfs_remove_cs(cs);
+
+	hdev->shadow_cs_queue[cs->sequence & (hdev->asic_prop.max_pending_cs - 1)] = NULL;
+
+	/* We need to mark an error for not submitted because in that case
+	 * the hl fence release flow is different. Mainly, we don't need
+	 * to handle hw_sob for signal/wait
+	 */
+	if (cs->timedout)
+		cs->fence->error = -ETIMEDOUT;
+	else if (cs->aborted)
+		cs->fence->error = -EIO;
+	else if (!cs->submitted)
+		cs->fence->error = -EBUSY;
+
+	if (unlikely(cs->skip_reset_on_timeout)) {
+		dev_err(hdev->dev,
+			"Command submission %llu completed after %llu (s)\n",
+			cs->sequence,
+			div_u64(jiffies - cs->submission_time_jiffies, HZ));
+	}
+
+	if (cs->timestamp) {
+		cs->fence->timestamp = cs->completion_timestamp;
+		hl_push_cs_outcome(hdev, &cs->ctx->outcome_store, cs->sequence,
+				   cs->fence->timestamp, cs->fence->error);
+	}
+
+	hl_ctx_put(cs->ctx);
+
+	complete_all(&cs->fence->completion);
+	complete_multi_cs(hdev, cs);
+
+	cs_release_sob_reset_handler(hdev, cs, hl_cs_cmpl);
+
+	hl_fence_put(cs->fence);
+
+	kfree(cs->jobs_in_queue_cnt);
+	kfree(cs);
+}
+
+static void cs_timedout(struct work_struct *work)
+{
+	struct hl_cs *cs = container_of(work, struct hl_cs, work_tdr.work);
+	bool skip_reset_on_timeout, device_reset = false;
+	struct hl_device *hdev;
+	u64 event_mask = 0x0;
+	uint timeout_sec;
+	int rc;
+
+	skip_reset_on_timeout = cs->skip_reset_on_timeout;
+
+	rc = cs_get_unless_zero(cs);
+	if (!rc)
+		return;
+
+	if ((!cs->submitted) || (cs->completed)) {
+		cs_put(cs);
+		return;
+	}
+
+	hdev = cs->ctx->hdev;
+
+	if (likely(!skip_reset_on_timeout)) {
+		if (hdev->reset_on_lockup)
+			device_reset = true;
+		else
+			hdev->reset_info.needs_reset = true;
+
+		/* Mark the CS is timed out so we won't try to cancel its TDR */
+		cs->timedout = true;
+	}
+
+	/* Save only the first CS timeout parameters */
+	rc = atomic_cmpxchg(&hdev->captured_err_info.cs_timeout.write_enable, 1, 0);
+	if (rc) {
+		hdev->captured_err_info.cs_timeout.timestamp = ktime_get();
+		hdev->captured_err_info.cs_timeout.seq = cs->sequence;
+		event_mask |= HL_NOTIFIER_EVENT_CS_TIMEOUT;
+	}
+
+	timeout_sec = jiffies_to_msecs(hdev->timeout_jiffies) / 1000;
+
+	switch (cs->type) {
+	case CS_TYPE_SIGNAL:
+		dev_err(hdev->dev,
+			"Signal command submission %llu has not finished in %u seconds!\n",
+			cs->sequence, timeout_sec);
+		break;
+
+	case CS_TYPE_WAIT:
+		dev_err(hdev->dev,
+			"Wait command submission %llu has not finished in %u seconds!\n",
+			cs->sequence, timeout_sec);
+		break;
+
+	case CS_TYPE_COLLECTIVE_WAIT:
+		dev_err(hdev->dev,
+			"Collective Wait command submission %llu has not finished in %u seconds!\n",
+			cs->sequence, timeout_sec);
+		break;
+
+	default:
+		dev_err(hdev->dev,
+			"Command submission %llu has not finished in %u seconds!\n",
+			cs->sequence, timeout_sec);
+		break;
+	}
+
+	rc = hl_state_dump(hdev);
+	if (rc)
+		dev_err(hdev->dev, "Error during system state dump %d\n", rc);
+
+	cs_put(cs);
+
+	if (device_reset) {
+		event_mask |= HL_NOTIFIER_EVENT_DEVICE_RESET;
+		hl_device_cond_reset(hdev, HL_DRV_RESET_TDR, event_mask);
+	} else if (event_mask) {
+		hl_notifier_event_send_all(hdev, event_mask);
+	}
+}
+
+static int allocate_cs(struct hl_device *hdev, struct hl_ctx *ctx,
+			enum hl_cs_type cs_type, u64 user_sequence,
+			struct hl_cs **cs_new, u32 flags, u32 timeout)
+{
+	struct hl_cs_counters_atomic *cntr;
+	struct hl_fence *other = NULL;
+	struct hl_cs_compl *cs_cmpl;
+	struct hl_cs *cs;
+	int rc;
+
+	cntr = &hdev->aggregated_cs_counters;
+
+	cs = kzalloc(sizeof(*cs), GFP_ATOMIC);
+	if (!cs)
+		cs = kzalloc(sizeof(*cs), GFP_KERNEL);
+
+	if (!cs) {
+		atomic64_inc(&ctx->cs_counters.out_of_mem_drop_cnt);
+		atomic64_inc(&cntr->out_of_mem_drop_cnt);
+		return -ENOMEM;
+	}
+
+	/* increment refcnt for context */
+	hl_ctx_get(ctx);
+
+	cs->ctx = ctx;
+	cs->submitted = false;
+	cs->completed = false;
+	cs->type = cs_type;
+	cs->timestamp = !!(flags & HL_CS_FLAGS_TIMESTAMP);
+	cs->encaps_signals = !!(flags & HL_CS_FLAGS_ENCAP_SIGNALS);
+	cs->timeout_jiffies = timeout;
+	cs->skip_reset_on_timeout =
+		hdev->reset_info.skip_reset_on_timeout ||
+		!!(flags & HL_CS_FLAGS_SKIP_RESET_ON_TIMEOUT);
+	cs->submission_time_jiffies = jiffies;
+	INIT_LIST_HEAD(&cs->job_list);
+	INIT_DELAYED_WORK(&cs->work_tdr, cs_timedout);
+	kref_init(&cs->refcount);
+	spin_lock_init(&cs->job_lock);
+
+	cs_cmpl = kzalloc(sizeof(*cs_cmpl), GFP_ATOMIC);
+	if (!cs_cmpl)
+		cs_cmpl = kzalloc(sizeof(*cs_cmpl), GFP_KERNEL);
+
+	if (!cs_cmpl) {
+		atomic64_inc(&ctx->cs_counters.out_of_mem_drop_cnt);
+		atomic64_inc(&cntr->out_of_mem_drop_cnt);
+		rc = -ENOMEM;
+		goto free_cs;
+	}
+
+	cs->jobs_in_queue_cnt = kcalloc(hdev->asic_prop.max_queues,
+			sizeof(*cs->jobs_in_queue_cnt), GFP_ATOMIC);
+	if (!cs->jobs_in_queue_cnt)
+		cs->jobs_in_queue_cnt = kcalloc(hdev->asic_prop.max_queues,
+				sizeof(*cs->jobs_in_queue_cnt), GFP_KERNEL);
+
+	if (!cs->jobs_in_queue_cnt) {
+		atomic64_inc(&ctx->cs_counters.out_of_mem_drop_cnt);
+		atomic64_inc(&cntr->out_of_mem_drop_cnt);
+		rc = -ENOMEM;
+		goto free_cs_cmpl;
+	}
+
+	cs_cmpl->hdev = hdev;
+	cs_cmpl->type = cs->type;
+	spin_lock_init(&cs_cmpl->lock);
+	cs->fence = &cs_cmpl->base_fence;
+
+	spin_lock(&ctx->cs_lock);
+
+	cs_cmpl->cs_seq = ctx->cs_sequence;
+	other = ctx->cs_pending[cs_cmpl->cs_seq &
+				(hdev->asic_prop.max_pending_cs - 1)];
+
+	if (other && !completion_done(&other->completion)) {
+		/* If the following statement is true, it means we have reached
+		 * a point in which only part of the staged submission was
+		 * submitted and we don't have enough room in the 'cs_pending'
+		 * array for the rest of the submission.
+		 * This causes a deadlock because this CS will never be
+		 * completed as it depends on future CS's for completion.
+		 */
+		if (other->cs_sequence == user_sequence)
+			dev_crit_ratelimited(hdev->dev,
+				"Staged CS %llu deadlock due to lack of resources",
+				user_sequence);
+
+		dev_dbg_ratelimited(hdev->dev,
+			"Rejecting CS because of too many in-flights CS\n");
+		atomic64_inc(&ctx->cs_counters.max_cs_in_flight_drop_cnt);
+		atomic64_inc(&cntr->max_cs_in_flight_drop_cnt);
+		rc = -EAGAIN;
+		goto free_fence;
+	}
+
+	/* init hl_fence */
+	hl_fence_init(&cs_cmpl->base_fence, cs_cmpl->cs_seq);
+
+	cs->sequence = cs_cmpl->cs_seq;
+
+	ctx->cs_pending[cs_cmpl->cs_seq &
+			(hdev->asic_prop.max_pending_cs - 1)] =
+							&cs_cmpl->base_fence;
+	ctx->cs_sequence++;
+
+	hl_fence_get(&cs_cmpl->base_fence);
+
+	hl_fence_put(other);
+
+	spin_unlock(&ctx->cs_lock);
+
+	*cs_new = cs;
+
+	return 0;
+
+free_fence:
+	spin_unlock(&ctx->cs_lock);
+	kfree(cs->jobs_in_queue_cnt);
+free_cs_cmpl:
+	kfree(cs_cmpl);
+free_cs:
+	kfree(cs);
+	hl_ctx_put(ctx);
+	return rc;
+}
+
+static void cs_rollback(struct hl_device *hdev, struct hl_cs *cs)
+{
+	struct hl_cs_job *job, *tmp;
+
+	staged_cs_put(hdev, cs);
+
+	list_for_each_entry_safe(job, tmp, &cs->job_list, cs_node)
+		hl_complete_job(hdev, job);
+}
+
+/*
+ * release_reserved_encaps_signals() - release reserved encapsulated signals.
+ * @hdev: pointer to habanalabs device structure
+ *
+ * Release reserved encapsulated signals which weren't un-reserved, or for which a CS with
+ * encapsulated signals wasn't submitted and thus weren't released as part of CS roll-back.
+ * For these signals need also to put the refcount of the H/W SOB which was taken at the
+ * reservation.
+ */
+static void release_reserved_encaps_signals(struct hl_device *hdev)
+{
+	struct hl_ctx *ctx = hl_get_compute_ctx(hdev);
+	struct hl_cs_encaps_sig_handle *handle;
+	struct hl_encaps_signals_mgr *mgr;
+	u32 id;
+
+	if (!ctx)
+		return;
+
+	mgr = &ctx->sig_mgr;
+
+	idr_for_each_entry(&mgr->handles, handle, id)
+		if (handle->cs_seq == ULLONG_MAX)
+			kref_put(&handle->refcount, hl_encaps_release_handle_and_put_sob_ctx);
+
+	hl_ctx_put(ctx);
+}
+
+void hl_cs_rollback_all(struct hl_device *hdev, bool skip_wq_flush)
+{
+	int i;
+	struct hl_cs *cs, *tmp;
+
+	if (!skip_wq_flush) {
+		flush_workqueue(hdev->ts_free_obj_wq);
+
+		/* flush all completions before iterating over the CS mirror list in
+		 * order to avoid a race with the release functions
+		 */
+		for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++)
+			flush_workqueue(hdev->cq_wq[i]);
+
+		flush_workqueue(hdev->cs_cmplt_wq);
+	}
+
+	/* Make sure we don't have leftovers in the CS mirror list */
+	list_for_each_entry_safe(cs, tmp, &hdev->cs_mirror_list, mirror_node) {
+		cs_get(cs);
+		cs->aborted = true;
+		dev_warn_ratelimited(hdev->dev, "Killing CS %d.%llu\n",
+					cs->ctx->asid, cs->sequence);
+		cs_rollback(hdev, cs);
+		cs_put(cs);
+	}
+
+	force_complete_multi_cs(hdev);
+
+	release_reserved_encaps_signals(hdev);
+}
+
+static void
+wake_pending_user_interrupt_threads(struct hl_user_interrupt *interrupt)
+{
+	struct hl_user_pending_interrupt *pend, *temp;
+	unsigned long flags;
+
+	spin_lock_irqsave(&interrupt->wait_list_lock, flags);
+	list_for_each_entry_safe(pend, temp, &interrupt->wait_list_head, list_node) {
+		pend->fence.error = -EIO;
+		complete_all(&pend->fence.completion);
+	}
+	spin_unlock_irqrestore(&interrupt->wait_list_lock, flags);
+
+	spin_lock_irqsave(&interrupt->ts_list_lock, flags);
+	list_for_each_entry_safe(pend, temp, &interrupt->ts_list_head, list_node) {
+		list_del(&pend->list_node);
+		hl_mmap_mem_buf_put(pend->ts_reg_info.buf);
+		hl_cb_put(pend->ts_reg_info.cq_cb);
+	}
+	spin_unlock_irqrestore(&interrupt->ts_list_lock, flags);
+}
+
+void hl_release_pending_user_interrupts(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct hl_user_interrupt *interrupt;
+	int i;
+
+	if (!prop->user_interrupt_count)
+		return;
+
+	/* We iterate through the user interrupt requests and waking up all
+	 * user threads waiting for interrupt completion. We iterate the
+	 * list under a lock, this is why all user threads, once awake,
+	 * will wait on the same lock and will release the waiting object upon
+	 * unlock.
+	 */
+
+	for (i = 0 ; i < prop->user_interrupt_count ; i++) {
+		interrupt = &hdev->user_interrupt[i];
+		wake_pending_user_interrupt_threads(interrupt);
+	}
+
+	interrupt = &hdev->common_user_cq_interrupt;
+	wake_pending_user_interrupt_threads(interrupt);
+
+	interrupt = &hdev->common_decoder_interrupt;
+	wake_pending_user_interrupt_threads(interrupt);
+}
+
+static void force_complete_cs(struct hl_device *hdev)
+{
+	struct hl_cs *cs;
+
+	spin_lock(&hdev->cs_mirror_lock);
+
+	list_for_each_entry(cs, &hdev->cs_mirror_list, mirror_node) {
+		cs->fence->error = -EIO;
+		complete_all(&cs->fence->completion);
+	}
+
+	spin_unlock(&hdev->cs_mirror_lock);
+}
+
+void hl_abort_waiting_for_cs_completions(struct hl_device *hdev)
+{
+	force_complete_cs(hdev);
+	force_complete_multi_cs(hdev);
+}
+
+static void job_wq_completion(struct work_struct *work)
+{
+	struct hl_cs_job *job = container_of(work, struct hl_cs_job,
+						finish_work);
+	struct hl_cs *cs = job->cs;
+	struct hl_device *hdev = cs->ctx->hdev;
+
+	/* job is no longer needed */
+	hl_complete_job(hdev, job);
+}
+
+static void cs_completion(struct work_struct *work)
+{
+	struct hl_cs *cs = container_of(work, struct hl_cs, finish_work);
+	struct hl_device *hdev = cs->ctx->hdev;
+	struct hl_cs_job *job, *tmp;
+
+	list_for_each_entry_safe(job, tmp, &cs->job_list, cs_node)
+		hl_complete_job(hdev, job);
+}
+
+u32 hl_get_active_cs_num(struct hl_device *hdev)
+{
+	u32 active_cs_num = 0;
+	struct hl_cs *cs;
+
+	spin_lock(&hdev->cs_mirror_lock);
+
+	list_for_each_entry(cs, &hdev->cs_mirror_list, mirror_node)
+		if (!cs->completed)
+			active_cs_num++;
+
+	spin_unlock(&hdev->cs_mirror_lock);
+
+	return active_cs_num;
+}
+
+static int validate_queue_index(struct hl_device *hdev,
+				struct hl_cs_chunk *chunk,
+				enum hl_queue_type *queue_type,
+				bool *is_kernel_allocated_cb)
+{
+	struct asic_fixed_properties *asic = &hdev->asic_prop;
+	struct hw_queue_properties *hw_queue_prop;
+
+	/* This must be checked here to prevent out-of-bounds access to
+	 * hw_queues_props array
+	 */
+	if (chunk->queue_index >= asic->max_queues) {
+		dev_err(hdev->dev, "Queue index %d is invalid\n",
+			chunk->queue_index);
+		return -EINVAL;
+	}
+
+	hw_queue_prop = &asic->hw_queues_props[chunk->queue_index];
+
+	if (hw_queue_prop->type == QUEUE_TYPE_NA) {
+		dev_err(hdev->dev, "Queue index %d is not applicable\n",
+			chunk->queue_index);
+		return -EINVAL;
+	}
+
+	if (hw_queue_prop->binned) {
+		dev_err(hdev->dev, "Queue index %d is binned out\n",
+			chunk->queue_index);
+		return -EINVAL;
+	}
+
+	if (hw_queue_prop->driver_only) {
+		dev_err(hdev->dev,
+			"Queue index %d is restricted for the kernel driver\n",
+			chunk->queue_index);
+		return -EINVAL;
+	}
+
+	/* When hw queue type isn't QUEUE_TYPE_HW,
+	 * USER_ALLOC_CB flag shall be referred as "don't care".
+	 */
+	if (hw_queue_prop->type == QUEUE_TYPE_HW) {
+		if (chunk->cs_chunk_flags & HL_CS_CHUNK_FLAGS_USER_ALLOC_CB) {
+			if (!(hw_queue_prop->cb_alloc_flags & CB_ALLOC_USER)) {
+				dev_err(hdev->dev,
+					"Queue index %d doesn't support user CB\n",
+					chunk->queue_index);
+				return -EINVAL;
+			}
+
+			*is_kernel_allocated_cb = false;
+		} else {
+			if (!(hw_queue_prop->cb_alloc_flags &
+					CB_ALLOC_KERNEL)) {
+				dev_err(hdev->dev,
+					"Queue index %d doesn't support kernel CB\n",
+					chunk->queue_index);
+				return -EINVAL;
+			}
+
+			*is_kernel_allocated_cb = true;
+		}
+	} else {
+		*is_kernel_allocated_cb = !!(hw_queue_prop->cb_alloc_flags
+						& CB_ALLOC_KERNEL);
+	}
+
+	*queue_type = hw_queue_prop->type;
+	return 0;
+}
+
+static struct hl_cb *get_cb_from_cs_chunk(struct hl_device *hdev,
+					struct hl_mem_mgr *mmg,
+					struct hl_cs_chunk *chunk)
+{
+	struct hl_cb *cb;
+
+	cb = hl_cb_get(mmg, chunk->cb_handle);
+	if (!cb) {
+		dev_err(hdev->dev, "CB handle 0x%llx invalid\n", chunk->cb_handle);
+		return NULL;
+	}
+
+	if ((chunk->cb_size < 8) || (chunk->cb_size > cb->size)) {
+		dev_err(hdev->dev, "CB size %u invalid\n", chunk->cb_size);
+		goto release_cb;
+	}
+
+	atomic_inc(&cb->cs_cnt);
+
+	return cb;
+
+release_cb:
+	hl_cb_put(cb);
+	return NULL;
+}
+
+struct hl_cs_job *hl_cs_allocate_job(struct hl_device *hdev,
+		enum hl_queue_type queue_type, bool is_kernel_allocated_cb)
+{
+	struct hl_cs_job *job;
+
+	job = kzalloc(sizeof(*job), GFP_ATOMIC);
+	if (!job)
+		job = kzalloc(sizeof(*job), GFP_KERNEL);
+
+	if (!job)
+		return NULL;
+
+	kref_init(&job->refcount);
+	job->queue_type = queue_type;
+	job->is_kernel_allocated_cb = is_kernel_allocated_cb;
+
+	if (is_cb_patched(hdev, job))
+		INIT_LIST_HEAD(&job->userptr_list);
+
+	if (job->queue_type == QUEUE_TYPE_EXT)
+		INIT_WORK(&job->finish_work, job_wq_completion);
+
+	return job;
+}
+
+static enum hl_cs_type hl_cs_get_cs_type(u32 cs_type_flags)
+{
+	if (cs_type_flags & HL_CS_FLAGS_SIGNAL)
+		return CS_TYPE_SIGNAL;
+	else if (cs_type_flags & HL_CS_FLAGS_WAIT)
+		return CS_TYPE_WAIT;
+	else if (cs_type_flags & HL_CS_FLAGS_COLLECTIVE_WAIT)
+		return CS_TYPE_COLLECTIVE_WAIT;
+	else if (cs_type_flags & HL_CS_FLAGS_RESERVE_SIGNALS_ONLY)
+		return CS_RESERVE_SIGNALS;
+	else if (cs_type_flags & HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY)
+		return CS_UNRESERVE_SIGNALS;
+	else if (cs_type_flags & HL_CS_FLAGS_ENGINE_CORE_COMMAND)
+		return CS_TYPE_ENGINE_CORE;
+	else if (cs_type_flags & HL_CS_FLAGS_ENGINES_COMMAND)
+		return CS_TYPE_ENGINES;
+	else if (cs_type_flags & HL_CS_FLAGS_FLUSH_PCI_HBW_WRITES)
+		return CS_TYPE_FLUSH_PCI_HBW_WRITES;
+	else
+		return CS_TYPE_DEFAULT;
+}
+
+static int hl_cs_sanity_checks(struct hl_fpriv *hpriv, union hl_cs_args *args)
+{
+	struct hl_device *hdev = hpriv->hdev;
+	struct hl_ctx *ctx = hpriv->ctx;
+	u32 cs_type_flags, num_chunks;
+	enum hl_device_status status;
+	enum hl_cs_type cs_type;
+	bool is_sync_stream;
+	int i;
+
+	for (i = 0 ; i < sizeof(args->in.pad) ; i++)
+		if (args->in.pad[i]) {
+			dev_dbg(hdev->dev, "Padding bytes must be 0\n");
+			return -EINVAL;
+		}
+
+	if (!hl_device_operational(hdev, &status))
+		return -EBUSY;
+
+	if ((args->in.cs_flags & HL_CS_FLAGS_STAGED_SUBMISSION) &&
+			!hdev->supports_staged_submission) {
+		dev_err(hdev->dev, "staged submission not supported");
+		return -EPERM;
+	}
+
+	cs_type_flags = args->in.cs_flags & HL_CS_FLAGS_TYPE_MASK;
+
+	if (unlikely(cs_type_flags && !is_power_of_2(cs_type_flags))) {
+		dev_err(hdev->dev,
+			"CS type flags are mutually exclusive, context %d\n",
+			ctx->asid);
+		return -EINVAL;
+	}
+
+	cs_type = hl_cs_get_cs_type(cs_type_flags);
+	num_chunks = args->in.num_chunks_execute;
+
+	is_sync_stream = (cs_type == CS_TYPE_SIGNAL || cs_type == CS_TYPE_WAIT ||
+			cs_type == CS_TYPE_COLLECTIVE_WAIT);
+
+	if (unlikely(is_sync_stream && !hdev->supports_sync_stream)) {
+		dev_err(hdev->dev, "Sync stream CS is not supported\n");
+		return -EINVAL;
+	}
+
+	if (cs_type == CS_TYPE_DEFAULT) {
+		if (!num_chunks) {
+			dev_err(hdev->dev, "Got execute CS with 0 chunks, context %d\n", ctx->asid);
+			return -EINVAL;
+		}
+	} else if (is_sync_stream && num_chunks != 1) {
+		dev_err(hdev->dev,
+			"Sync stream CS mandates one chunk only, context %d\n",
+			ctx->asid);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int hl_cs_copy_chunk_array(struct hl_device *hdev,
+					struct hl_cs_chunk **cs_chunk_array,
+					void __user *chunks, u32 num_chunks,
+					struct hl_ctx *ctx)
+{
+	u32 size_to_copy;
+
+	if (num_chunks > HL_MAX_JOBS_PER_CS) {
+		atomic64_inc(&ctx->cs_counters.validation_drop_cnt);
+		atomic64_inc(&hdev->aggregated_cs_counters.validation_drop_cnt);
+		dev_err(hdev->dev,
+			"Number of chunks can NOT be larger than %d\n",
+			HL_MAX_JOBS_PER_CS);
+		return -EINVAL;
+	}
+
+	*cs_chunk_array = kmalloc_array(num_chunks, sizeof(**cs_chunk_array),
+					GFP_ATOMIC);
+	if (!*cs_chunk_array)
+		*cs_chunk_array = kmalloc_array(num_chunks,
+					sizeof(**cs_chunk_array), GFP_KERNEL);
+	if (!*cs_chunk_array) {
+		atomic64_inc(&ctx->cs_counters.out_of_mem_drop_cnt);
+		atomic64_inc(&hdev->aggregated_cs_counters.out_of_mem_drop_cnt);
+		return -ENOMEM;
+	}
+
+	size_to_copy = num_chunks * sizeof(struct hl_cs_chunk);
+	if (copy_from_user(*cs_chunk_array, chunks, size_to_copy)) {
+		atomic64_inc(&ctx->cs_counters.validation_drop_cnt);
+		atomic64_inc(&hdev->aggregated_cs_counters.validation_drop_cnt);
+		dev_err(hdev->dev, "Failed to copy cs chunk array from user\n");
+		kfree(*cs_chunk_array);
+		return -EFAULT;
+	}
+
+	return 0;
+}
+
+static int cs_staged_submission(struct hl_device *hdev, struct hl_cs *cs,
+				u64 sequence, u32 flags,
+				u32 encaps_signal_handle)
+{
+	if (!(flags & HL_CS_FLAGS_STAGED_SUBMISSION))
+		return 0;
+
+	cs->staged_last = !!(flags & HL_CS_FLAGS_STAGED_SUBMISSION_LAST);
+	cs->staged_first = !!(flags & HL_CS_FLAGS_STAGED_SUBMISSION_FIRST);
+
+	if (cs->staged_first) {
+		/* Staged CS sequence is the first CS sequence */
+		INIT_LIST_HEAD(&cs->staged_cs_node);
+		cs->staged_sequence = cs->sequence;
+
+		if (cs->encaps_signals)
+			cs->encaps_sig_hdl_id = encaps_signal_handle;
+	} else {
+		/* User sequence will be validated in 'hl_hw_queue_schedule_cs'
+		 * under the cs_mirror_lock
+		 */
+		cs->staged_sequence = sequence;
+	}
+
+	/* Increment CS reference if needed */
+	staged_cs_get(hdev, cs);
+
+	cs->staged_cs = true;
+
+	return 0;
+}
+
+static u32 get_stream_master_qid_mask(struct hl_device *hdev, u32 qid)
+{
+	int i;
+
+	for (i = 0; i < hdev->stream_master_qid_arr_size; i++)
+		if (qid == hdev->stream_master_qid_arr[i])
+			return BIT(i);
+
+	return 0;
+}
+
+static int cs_ioctl_default(struct hl_fpriv *hpriv, void __user *chunks,
+				u32 num_chunks, u64 *cs_seq, u32 flags,
+				u32 encaps_signals_handle, u32 timeout,
+				u16 *signal_initial_sob_count)
+{
+	bool staged_mid, int_queues_only = true, using_hw_queues = false;
+	struct hl_device *hdev = hpriv->hdev;
+	struct hl_cs_chunk *cs_chunk_array;
+	struct hl_cs_counters_atomic *cntr;
+	struct hl_ctx *ctx = hpriv->ctx;
+	struct hl_cs_job *job;
+	struct hl_cs *cs;
+	struct hl_cb *cb;
+	u64 user_sequence;
+	u8 stream_master_qid_map = 0;
+	int rc, i;
+
+	cntr = &hdev->aggregated_cs_counters;
+	user_sequence = *cs_seq;
+	*cs_seq = ULLONG_MAX;
+
+	rc = hl_cs_copy_chunk_array(hdev, &cs_chunk_array, chunks, num_chunks,
+			hpriv->ctx);
+	if (rc)
+		goto out;
+
+	if ((flags & HL_CS_FLAGS_STAGED_SUBMISSION) &&
+			!(flags & HL_CS_FLAGS_STAGED_SUBMISSION_FIRST))
+		staged_mid = true;
+	else
+		staged_mid = false;
+
+	rc = allocate_cs(hdev, hpriv->ctx, CS_TYPE_DEFAULT,
+			staged_mid ? user_sequence : ULLONG_MAX, &cs, flags,
+			timeout);
+	if (rc)
+		goto free_cs_chunk_array;
+
+	*cs_seq = cs->sequence;
+
+	hl_debugfs_add_cs(cs);
+
+	rc = cs_staged_submission(hdev, cs, user_sequence, flags,
+						encaps_signals_handle);
+	if (rc)
+		goto free_cs_object;
+
+	/* If this is a staged submission we must return the staged sequence
+	 * rather than the internal CS sequence
+	 */
+	if (cs->staged_cs)
+		*cs_seq = cs->staged_sequence;
+
+	/* Validate ALL the CS chunks before submitting the CS */
+	for (i = 0 ; i < num_chunks ; i++) {
+		struct hl_cs_chunk *chunk = &cs_chunk_array[i];
+		enum hl_queue_type queue_type;
+		bool is_kernel_allocated_cb;
+
+		rc = validate_queue_index(hdev, chunk, &queue_type,
+						&is_kernel_allocated_cb);
+		if (rc) {
+			atomic64_inc(&ctx->cs_counters.validation_drop_cnt);
+			atomic64_inc(&cntr->validation_drop_cnt);
+			goto free_cs_object;
+		}
+
+		if (is_kernel_allocated_cb) {
+			cb = get_cb_from_cs_chunk(hdev, &hpriv->mem_mgr, chunk);
+			if (!cb) {
+				atomic64_inc(
+					&ctx->cs_counters.validation_drop_cnt);
+				atomic64_inc(&cntr->validation_drop_cnt);
+				rc = -EINVAL;
+				goto free_cs_object;
+			}
+		} else {
+			cb = (struct hl_cb *) (uintptr_t) chunk->cb_handle;
+		}
+
+		if (queue_type == QUEUE_TYPE_EXT ||
+						queue_type == QUEUE_TYPE_HW) {
+			int_queues_only = false;
+
+			/*
+			 * store which stream are being used for external/HW
+			 * queues of this CS
+			 */
+			if (hdev->supports_wait_for_multi_cs)
+				stream_master_qid_map |=
+					get_stream_master_qid_mask(hdev,
+							chunk->queue_index);
+		}
+
+		if (queue_type == QUEUE_TYPE_HW)
+			using_hw_queues = true;
+
+		job = hl_cs_allocate_job(hdev, queue_type,
+						is_kernel_allocated_cb);
+		if (!job) {
+			atomic64_inc(&ctx->cs_counters.out_of_mem_drop_cnt);
+			atomic64_inc(&cntr->out_of_mem_drop_cnt);
+			dev_err(hdev->dev, "Failed to allocate a new job\n");
+			rc = -ENOMEM;
+			if (is_kernel_allocated_cb)
+				goto release_cb;
+
+			goto free_cs_object;
+		}
+
+		job->id = i + 1;
+		job->cs = cs;
+		job->user_cb = cb;
+		job->user_cb_size = chunk->cb_size;
+		job->hw_queue_id = chunk->queue_index;
+
+		cs->jobs_in_queue_cnt[job->hw_queue_id]++;
+		cs->jobs_cnt++;
+
+		list_add_tail(&job->cs_node, &cs->job_list);
+
+		/*
+		 * Increment CS reference. When CS reference is 0, CS is
+		 * done and can be signaled to user and free all its resources
+		 * Only increment for JOB on external or H/W queues, because
+		 * only for those JOBs we get completion
+		 */
+		if (cs_needs_completion(cs) &&
+			(job->queue_type == QUEUE_TYPE_EXT ||
+				job->queue_type == QUEUE_TYPE_HW))
+			cs_get(cs);
+
+		hl_debugfs_add_job(hdev, job);
+
+		rc = cs_parser(hpriv, job);
+		if (rc) {
+			atomic64_inc(&ctx->cs_counters.parsing_drop_cnt);
+			atomic64_inc(&cntr->parsing_drop_cnt);
+			dev_err(hdev->dev,
+				"Failed to parse JOB %d.%llu.%d, err %d, rejecting the CS\n",
+				cs->ctx->asid, cs->sequence, job->id, rc);
+			goto free_cs_object;
+		}
+	}
+
+	/* We allow a CS with any queue type combination as long as it does
+	 * not get a completion
+	 */
+	if (int_queues_only && cs_needs_completion(cs)) {
+		atomic64_inc(&ctx->cs_counters.validation_drop_cnt);
+		atomic64_inc(&cntr->validation_drop_cnt);
+		dev_err(hdev->dev,
+			"Reject CS %d.%llu since it contains only internal queues jobs and needs completion\n",
+			cs->ctx->asid, cs->sequence);
+		rc = -EINVAL;
+		goto free_cs_object;
+	}
+
+	if (using_hw_queues)
+		INIT_WORK(&cs->finish_work, cs_completion);
+
+	/*
+	 * store the (external/HW queues) streams used by the CS in the
+	 * fence object for multi-CS completion
+	 */
+	if (hdev->supports_wait_for_multi_cs)
+		cs->fence->stream_master_qid_map = stream_master_qid_map;
+
+	rc = hl_hw_queue_schedule_cs(cs);
+	if (rc) {
+		if (rc != -EAGAIN)
+			dev_err(hdev->dev,
+				"Failed to submit CS %d.%llu to H/W queues, error %d\n",
+				cs->ctx->asid, cs->sequence, rc);
+		goto free_cs_object;
+	}
+
+	*signal_initial_sob_count = cs->initial_sob_count;
+
+	rc = HL_CS_STATUS_SUCCESS;
+	goto put_cs;
+
+release_cb:
+	atomic_dec(&cb->cs_cnt);
+	hl_cb_put(cb);
+free_cs_object:
+	cs_rollback(hdev, cs);
+	*cs_seq = ULLONG_MAX;
+	/* The path below is both for good and erroneous exits */
+put_cs:
+	/* We finished with the CS in this function, so put the ref */
+	cs_put(cs);
+free_cs_chunk_array:
+	kfree(cs_chunk_array);
+out:
+	return rc;
+}
+
+static int hl_cs_ctx_switch(struct hl_fpriv *hpriv, union hl_cs_args *args,
+				u64 *cs_seq)
+{
+	struct hl_device *hdev = hpriv->hdev;
+	struct hl_ctx *ctx = hpriv->ctx;
+	bool need_soft_reset = false;
+	int rc = 0, do_ctx_switch = 0;
+	void __user *chunks;
+	u32 num_chunks, tmp;
+	u16 sob_count;
+	int ret;
+
+	if (hdev->supports_ctx_switch)
+		do_ctx_switch = atomic_cmpxchg(&ctx->thread_ctx_switch_token, 1, 0);
+
+	if (do_ctx_switch || (args->in.cs_flags & HL_CS_FLAGS_FORCE_RESTORE)) {
+		mutex_lock(&hpriv->restore_phase_mutex);
+
+		if (do_ctx_switch) {
+			rc = hdev->asic_funcs->context_switch(hdev, ctx->asid);
+			if (rc) {
+				dev_err_ratelimited(hdev->dev,
+					"Failed to switch to context %d, rejecting CS! %d\n",
+					ctx->asid, rc);
+				/*
+				 * If we timedout, or if the device is not IDLE
+				 * while we want to do context-switch (-EBUSY),
+				 * we need to soft-reset because QMAN is
+				 * probably stuck. However, we can't call to
+				 * reset here directly because of deadlock, so
+				 * need to do it at the very end of this
+				 * function
+				 */
+				if ((rc == -ETIMEDOUT) || (rc == -EBUSY))
+					need_soft_reset = true;
+				mutex_unlock(&hpriv->restore_phase_mutex);
+				goto out;
+			}
+		}
+
+		hdev->asic_funcs->restore_phase_topology(hdev);
+
+		chunks = (void __user *) (uintptr_t) args->in.chunks_restore;
+		num_chunks = args->in.num_chunks_restore;
+
+		if (!num_chunks) {
+			dev_dbg(hdev->dev,
+				"Need to run restore phase but restore CS is empty\n");
+			rc = 0;
+		} else {
+			rc = cs_ioctl_default(hpriv, chunks, num_chunks,
+					cs_seq, 0, 0, hdev->timeout_jiffies, &sob_count);
+		}
+
+		mutex_unlock(&hpriv->restore_phase_mutex);
+
+		if (rc) {
+			dev_err(hdev->dev,
+				"Failed to submit restore CS for context %d (%d)\n",
+				ctx->asid, rc);
+			goto out;
+		}
+
+		/* Need to wait for restore completion before execution phase */
+		if (num_chunks) {
+			enum hl_cs_wait_status status;
+
+			ret = _hl_cs_wait_ioctl(hdev, ctx,
+					jiffies_to_usecs(hdev->timeout_jiffies),
+					*cs_seq, &status, NULL);
+			if (ret) {
+				dev_err(hdev->dev,
+					"Restore CS for context %d failed to complete %d\n",
+					ctx->asid, ret);
+				rc = -ENOEXEC;
+				goto out;
+			}
+		}
+
+		if (hdev->supports_ctx_switch)
+			ctx->thread_ctx_switch_wait_token = 1;
+
+	} else if (hdev->supports_ctx_switch && !ctx->thread_ctx_switch_wait_token) {
+		rc = hl_poll_timeout_memory(hdev,
+			&ctx->thread_ctx_switch_wait_token, tmp, (tmp == 1),
+			100, jiffies_to_usecs(hdev->timeout_jiffies), false);
+
+		if (rc == -ETIMEDOUT) {
+			dev_err(hdev->dev,
+				"context switch phase timeout (%d)\n", tmp);
+			goto out;
+		}
+	}
+
+out:
+	if ((rc == -ETIMEDOUT || rc == -EBUSY) && (need_soft_reset))
+		hl_device_reset(hdev, 0);
+
+	return rc;
+}
+
+/*
+ * hl_cs_signal_sob_wraparound_handler: handle SOB value wrapaound case.
+ * if the SOB value reaches the max value move to the other SOB reserved
+ * to the queue.
+ * @hdev: pointer to device structure
+ * @q_idx: stream queue index
+ * @hw_sob: the H/W SOB used in this signal CS.
+ * @count: signals count
+ * @encaps_sig: tells whether it's reservation for encaps signals or not.
+ *
+ * Note that this function must be called while hw_queues_lock is taken.
+ */
+int hl_cs_signal_sob_wraparound_handler(struct hl_device *hdev, u32 q_idx,
+			struct hl_hw_sob **hw_sob, u32 count, bool encaps_sig)
+
+{
+	struct hl_sync_stream_properties *prop;
+	struct hl_hw_sob *sob = *hw_sob, *other_sob;
+	u8 other_sob_offset;
+
+	prop = &hdev->kernel_queues[q_idx].sync_stream_prop;
+
+	hw_sob_get(sob);
+
+	/* check for wraparound */
+	if (prop->next_sob_val + count >= HL_MAX_SOB_VAL) {
+		/*
+		 * Decrement as we reached the max value.
+		 * The release function won't be called here as we've
+		 * just incremented the refcount right before calling this
+		 * function.
+		 */
+		hw_sob_put_err(sob);
+
+		/*
+		 * check the other sob value, if it still in use then fail
+		 * otherwise make the switch
+		 */
+		other_sob_offset = (prop->curr_sob_offset + 1) % HL_RSVD_SOBS;
+		other_sob = &prop->hw_sob[other_sob_offset];
+
+		if (kref_read(&other_sob->kref) != 1) {
+			dev_err(hdev->dev, "error: Cannot switch SOBs q_idx: %d\n",
+								q_idx);
+			return -EINVAL;
+		}
+
+		/*
+		 * next_sob_val always points to the next available signal
+		 * in the sob, so in encaps signals it will be the next one
+		 * after reserving the required amount.
+		 */
+		if (encaps_sig)
+			prop->next_sob_val = count + 1;
+		else
+			prop->next_sob_val = count;
+
+		/* only two SOBs are currently in use */
+		prop->curr_sob_offset = other_sob_offset;
+		*hw_sob = other_sob;
+
+		/*
+		 * check if other_sob needs reset, then do it before using it
+		 * for the reservation or the next signal cs.
+		 * we do it here, and for both encaps and regular signal cs
+		 * cases in order to avoid possible races of two kref_put
+		 * of the sob which can occur at the same time if we move the
+		 * sob reset(kref_put) to cs_do_release function.
+		 * in addition, if we have combination of cs signal and
+		 * encaps, and at the point we need to reset the sob there was
+		 * no more reservations and only signal cs keep coming,
+		 * in such case we need signal_cs to put the refcount and
+		 * reset the sob.
+		 */
+		if (other_sob->need_reset)
+			hw_sob_put(other_sob);
+
+		if (encaps_sig) {
+			/* set reset indication for the sob */
+			sob->need_reset = true;
+			hw_sob_get(other_sob);
+		}
+
+		dev_dbg(hdev->dev, "switched to SOB %d, q_idx: %d\n",
+				prop->curr_sob_offset, q_idx);
+	} else {
+		prop->next_sob_val += count;
+	}
+
+	return 0;
+}
+
+static int cs_ioctl_extract_signal_seq(struct hl_device *hdev,
+		struct hl_cs_chunk *chunk, u64 *signal_seq, struct hl_ctx *ctx,
+		bool encaps_signals)
+{
+	u64 *signal_seq_arr = NULL;
+	u32 size_to_copy, signal_seq_arr_len;
+	int rc = 0;
+
+	if (encaps_signals) {
+		*signal_seq = chunk->encaps_signal_seq;
+		return 0;
+	}
+
+	signal_seq_arr_len = chunk->num_signal_seq_arr;
+
+	/* currently only one signal seq is supported */
+	if (signal_seq_arr_len != 1) {
+		atomic64_inc(&ctx->cs_counters.validation_drop_cnt);
+		atomic64_inc(&hdev->aggregated_cs_counters.validation_drop_cnt);
+		dev_err(hdev->dev,
+			"Wait for signal CS supports only one signal CS seq\n");
+		return -EINVAL;
+	}
+
+	signal_seq_arr = kmalloc_array(signal_seq_arr_len,
+					sizeof(*signal_seq_arr),
+					GFP_ATOMIC);
+	if (!signal_seq_arr)
+		signal_seq_arr = kmalloc_array(signal_seq_arr_len,
+					sizeof(*signal_seq_arr),
+					GFP_KERNEL);
+	if (!signal_seq_arr) {
+		atomic64_inc(&ctx->cs_counters.out_of_mem_drop_cnt);
+		atomic64_inc(&hdev->aggregated_cs_counters.out_of_mem_drop_cnt);
+		return -ENOMEM;
+	}
+
+	size_to_copy = signal_seq_arr_len * sizeof(*signal_seq_arr);
+	if (copy_from_user(signal_seq_arr,
+				u64_to_user_ptr(chunk->signal_seq_arr),
+				size_to_copy)) {
+		atomic64_inc(&ctx->cs_counters.validation_drop_cnt);
+		atomic64_inc(&hdev->aggregated_cs_counters.validation_drop_cnt);
+		dev_err(hdev->dev,
+			"Failed to copy signal seq array from user\n");
+		rc = -EFAULT;
+		goto out;
+	}
+
+	/* currently it is guaranteed to have only one signal seq */
+	*signal_seq = signal_seq_arr[0];
+
+out:
+	kfree(signal_seq_arr);
+
+	return rc;
+}
+
+static int cs_ioctl_signal_wait_create_jobs(struct hl_device *hdev,
+		struct hl_ctx *ctx, struct hl_cs *cs,
+		enum hl_queue_type q_type, u32 q_idx, u32 encaps_signal_offset)
+{
+	struct hl_cs_counters_atomic *cntr;
+	struct hl_cs_job *job;
+	struct hl_cb *cb;
+	u32 cb_size;
+
+	cntr = &hdev->aggregated_cs_counters;
+
+	job = hl_cs_allocate_job(hdev, q_type, true);
+	if (!job) {
+		atomic64_inc(&ctx->cs_counters.out_of_mem_drop_cnt);
+		atomic64_inc(&cntr->out_of_mem_drop_cnt);
+		dev_err(hdev->dev, "Failed to allocate a new job\n");
+		return -ENOMEM;
+	}
+
+	if (cs->type == CS_TYPE_WAIT)
+		cb_size = hdev->asic_funcs->get_wait_cb_size(hdev);
+	else
+		cb_size = hdev->asic_funcs->get_signal_cb_size(hdev);
+
+	cb = hl_cb_kernel_create(hdev, cb_size, q_type == QUEUE_TYPE_HW);
+	if (!cb) {
+		atomic64_inc(&ctx->cs_counters.out_of_mem_drop_cnt);
+		atomic64_inc(&cntr->out_of_mem_drop_cnt);
+		kfree(job);
+		return -EFAULT;
+	}
+
+	job->id = 0;
+	job->cs = cs;
+	job->user_cb = cb;
+	atomic_inc(&job->user_cb->cs_cnt);
+	job->user_cb_size = cb_size;
+	job->hw_queue_id = q_idx;
+
+	if ((cs->type == CS_TYPE_WAIT || cs->type == CS_TYPE_COLLECTIVE_WAIT)
+			&& cs->encaps_signals)
+		job->encaps_sig_wait_offset = encaps_signal_offset;
+	/*
+	 * No need in parsing, user CB is the patched CB.
+	 * We call hl_cb_destroy() out of two reasons - we don't need the CB in
+	 * the CB idr anymore and to decrement its refcount as it was
+	 * incremented inside hl_cb_kernel_create().
+	 */
+	job->patched_cb = job->user_cb;
+	job->job_cb_size = job->user_cb_size;
+	hl_cb_destroy(&hdev->kernel_mem_mgr, cb->buf->handle);
+
+	/* increment refcount as for external queues we get completion */
+	cs_get(cs);
+
+	cs->jobs_in_queue_cnt[job->hw_queue_id]++;
+	cs->jobs_cnt++;
+
+	list_add_tail(&job->cs_node, &cs->job_list);
+
+	hl_debugfs_add_job(hdev, job);
+
+	return 0;
+}
+
+static int cs_ioctl_reserve_signals(struct hl_fpriv *hpriv,
+				u32 q_idx, u32 count,
+				u32 *handle_id, u32 *sob_addr,
+				u32 *signals_count)
+{
+	struct hw_queue_properties *hw_queue_prop;
+	struct hl_sync_stream_properties *prop;
+	struct hl_device *hdev = hpriv->hdev;
+	struct hl_cs_encaps_sig_handle *handle;
+	struct hl_encaps_signals_mgr *mgr;
+	struct hl_hw_sob *hw_sob;
+	int hdl_id;
+	int rc = 0;
+
+	if (count >= HL_MAX_SOB_VAL) {
+		dev_err(hdev->dev, "signals count(%u) exceeds the max SOB value\n",
+						count);
+		rc = -EINVAL;
+		goto out;
+	}
+
+	if (q_idx >= hdev->asic_prop.max_queues) {
+		dev_err(hdev->dev, "Queue index %d is invalid\n",
+			q_idx);
+		rc = -EINVAL;
+		goto out;
+	}
+
+	hw_queue_prop = &hdev->asic_prop.hw_queues_props[q_idx];
+
+	if (!hw_queue_prop->supports_sync_stream) {
+		dev_err(hdev->dev,
+			"Queue index %d does not support sync stream operations\n",
+									q_idx);
+		rc = -EINVAL;
+		goto out;
+	}
+
+	prop = &hdev->kernel_queues[q_idx].sync_stream_prop;
+
+	handle = kzalloc(sizeof(*handle), GFP_KERNEL);
+	if (!handle) {
+		rc = -ENOMEM;
+		goto out;
+	}
+
+	handle->count = count;
+
+	hl_ctx_get(hpriv->ctx);
+	handle->ctx = hpriv->ctx;
+	mgr = &hpriv->ctx->sig_mgr;
+
+	spin_lock(&mgr->lock);
+	hdl_id = idr_alloc(&mgr->handles, handle, 1, 0, GFP_ATOMIC);
+	spin_unlock(&mgr->lock);
+
+	if (hdl_id < 0) {
+		dev_err(hdev->dev, "Failed to allocate IDR for a new signal reservation\n");
+		rc = -EINVAL;
+		goto put_ctx;
+	}
+
+	handle->id = hdl_id;
+	handle->q_idx = q_idx;
+	handle->hdev = hdev;
+	kref_init(&handle->refcount);
+
+	hdev->asic_funcs->hw_queues_lock(hdev);
+
+	hw_sob = &prop->hw_sob[prop->curr_sob_offset];
+
+	/*
+	 * Increment the SOB value by count by user request
+	 * to reserve those signals
+	 * check if the signals amount to reserve is not exceeding the max sob
+	 * value, if yes then switch sob.
+	 */
+	rc = hl_cs_signal_sob_wraparound_handler(hdev, q_idx, &hw_sob, count,
+								true);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to switch SOB\n");
+		hdev->asic_funcs->hw_queues_unlock(hdev);
+		rc = -EINVAL;
+		goto remove_idr;
+	}
+	/* set the hw_sob to the handle after calling the sob wraparound handler
+	 * since sob could have changed.
+	 */
+	handle->hw_sob = hw_sob;
+
+	/* store the current sob value for unreserve validity check, and
+	 * signal offset support
+	 */
+	handle->pre_sob_val = prop->next_sob_val - handle->count;
+
+	handle->cs_seq = ULLONG_MAX;
+
+	*signals_count = prop->next_sob_val;
+	hdev->asic_funcs->hw_queues_unlock(hdev);
+
+	*sob_addr = handle->hw_sob->sob_addr;
+	*handle_id = hdl_id;
+
+	dev_dbg(hdev->dev,
+		"Signals reserved, sob_id: %d, sob addr: 0x%x, last sob_val: %u, q_idx: %d, hdl_id: %d\n",
+			hw_sob->sob_id, handle->hw_sob->sob_addr,
+			prop->next_sob_val - 1, q_idx, hdl_id);
+	goto out;
+
+remove_idr:
+	spin_lock(&mgr->lock);
+	idr_remove(&mgr->handles, hdl_id);
+	spin_unlock(&mgr->lock);
+
+put_ctx:
+	hl_ctx_put(handle->ctx);
+	kfree(handle);
+
+out:
+	return rc;
+}
+
+static int cs_ioctl_unreserve_signals(struct hl_fpriv *hpriv, u32 handle_id)
+{
+	struct hl_cs_encaps_sig_handle *encaps_sig_hdl;
+	struct hl_sync_stream_properties *prop;
+	struct hl_device *hdev = hpriv->hdev;
+	struct hl_encaps_signals_mgr *mgr;
+	struct hl_hw_sob *hw_sob;
+	u32 q_idx, sob_addr;
+	int rc = 0;
+
+	mgr = &hpriv->ctx->sig_mgr;
+
+	spin_lock(&mgr->lock);
+	encaps_sig_hdl = idr_find(&mgr->handles, handle_id);
+	if (encaps_sig_hdl) {
+		dev_dbg(hdev->dev, "unreserve signals, handle: %u, SOB:0x%x, count: %u\n",
+				handle_id, encaps_sig_hdl->hw_sob->sob_addr,
+					encaps_sig_hdl->count);
+
+		hdev->asic_funcs->hw_queues_lock(hdev);
+
+		q_idx = encaps_sig_hdl->q_idx;
+		prop = &hdev->kernel_queues[q_idx].sync_stream_prop;
+		hw_sob = &prop->hw_sob[prop->curr_sob_offset];
+		sob_addr = hdev->asic_funcs->get_sob_addr(hdev, hw_sob->sob_id);
+
+		/* Check if sob_val got out of sync due to other
+		 * signal submission requests which were handled
+		 * between the reserve-unreserve calls or SOB switch
+		 * upon reaching SOB max value.
+		 */
+		if (encaps_sig_hdl->pre_sob_val + encaps_sig_hdl->count
+				!= prop->next_sob_val ||
+				sob_addr != encaps_sig_hdl->hw_sob->sob_addr) {
+			dev_err(hdev->dev, "Cannot unreserve signals, SOB val ran out of sync, expected: %u, actual val: %u\n",
+				encaps_sig_hdl->pre_sob_val,
+				(prop->next_sob_val - encaps_sig_hdl->count));
+
+			hdev->asic_funcs->hw_queues_unlock(hdev);
+			rc = -EINVAL;
+			goto out_unlock;
+		}
+
+		/*
+		 * Decrement the SOB value by count by user request
+		 * to unreserve those signals
+		 */
+		prop->next_sob_val -= encaps_sig_hdl->count;
+
+		hdev->asic_funcs->hw_queues_unlock(hdev);
+
+		hw_sob_put(hw_sob);
+
+		/* Release the id and free allocated memory of the handle */
+		idr_remove(&mgr->handles, handle_id);
+
+		/* unlock before calling ctx_put, where we might sleep */
+		spin_unlock(&mgr->lock);
+		hl_ctx_put(encaps_sig_hdl->ctx);
+		kfree(encaps_sig_hdl);
+		goto out;
+	} else {
+		rc = -EINVAL;
+		dev_err(hdev->dev, "failed to unreserve signals, cannot find handler\n");
+	}
+
+out_unlock:
+	spin_unlock(&mgr->lock);
+
+out:
+	return rc;
+}
+
+static int cs_ioctl_signal_wait(struct hl_fpriv *hpriv, enum hl_cs_type cs_type,
+				void __user *chunks, u32 num_chunks,
+				u64 *cs_seq, u32 flags, u32 timeout,
+				u32 *signal_sob_addr_offset, u16 *signal_initial_sob_count)
+{
+	struct hl_cs_encaps_sig_handle *encaps_sig_hdl = NULL;
+	bool handle_found = false, is_wait_cs = false,
+			wait_cs_submitted = false,
+			cs_encaps_signals = false;
+	struct hl_cs_chunk *cs_chunk_array, *chunk;
+	bool staged_cs_with_encaps_signals = false;
+	struct hw_queue_properties *hw_queue_prop;
+	struct hl_device *hdev = hpriv->hdev;
+	struct hl_cs_compl *sig_waitcs_cmpl;
+	u32 q_idx, collective_engine_id = 0;
+	struct hl_cs_counters_atomic *cntr;
+	struct hl_fence *sig_fence = NULL;
+	struct hl_ctx *ctx = hpriv->ctx;
+	enum hl_queue_type q_type;
+	struct hl_cs *cs;
+	u64 signal_seq;
+	int rc;
+
+	cntr = &hdev->aggregated_cs_counters;
+	*cs_seq = ULLONG_MAX;
+
+	rc = hl_cs_copy_chunk_array(hdev, &cs_chunk_array, chunks, num_chunks,
+			ctx);
+	if (rc)
+		goto out;
+
+	/* currently it is guaranteed to have only one chunk */
+	chunk = &cs_chunk_array[0];
+
+	if (chunk->queue_index >= hdev->asic_prop.max_queues) {
+		atomic64_inc(&ctx->cs_counters.validation_drop_cnt);
+		atomic64_inc(&cntr->validation_drop_cnt);
+		dev_err(hdev->dev, "Queue index %d is invalid\n",
+			chunk->queue_index);
+		rc = -EINVAL;
+		goto free_cs_chunk_array;
+	}
+
+	q_idx = chunk->queue_index;
+	hw_queue_prop = &hdev->asic_prop.hw_queues_props[q_idx];
+	q_type = hw_queue_prop->type;
+
+	if (!hw_queue_prop->supports_sync_stream) {
+		atomic64_inc(&ctx->cs_counters.validation_drop_cnt);
+		atomic64_inc(&cntr->validation_drop_cnt);
+		dev_err(hdev->dev,
+			"Queue index %d does not support sync stream operations\n",
+			q_idx);
+		rc = -EINVAL;
+		goto free_cs_chunk_array;
+	}
+
+	if (cs_type == CS_TYPE_COLLECTIVE_WAIT) {
+		if (!(hw_queue_prop->collective_mode == HL_COLLECTIVE_MASTER)) {
+			atomic64_inc(&ctx->cs_counters.validation_drop_cnt);
+			atomic64_inc(&cntr->validation_drop_cnt);
+			dev_err(hdev->dev,
+				"Queue index %d is invalid\n", q_idx);
+			rc = -EINVAL;
+			goto free_cs_chunk_array;
+		}
+
+		if (!hdev->nic_ports_mask) {
+			atomic64_inc(&ctx->cs_counters.validation_drop_cnt);
+			atomic64_inc(&cntr->validation_drop_cnt);
+			dev_err(hdev->dev,
+				"Collective operations not supported when NIC ports are disabled");
+			rc = -EINVAL;
+			goto free_cs_chunk_array;
+		}
+
+		collective_engine_id = chunk->collective_engine_id;
+	}
+
+	is_wait_cs = !!(cs_type == CS_TYPE_WAIT ||
+			cs_type == CS_TYPE_COLLECTIVE_WAIT);
+
+	cs_encaps_signals = !!(flags & HL_CS_FLAGS_ENCAP_SIGNALS);
+
+	if (is_wait_cs) {
+		rc = cs_ioctl_extract_signal_seq(hdev, chunk, &signal_seq,
+				ctx, cs_encaps_signals);
+		if (rc)
+			goto free_cs_chunk_array;
+
+		if (cs_encaps_signals) {
+			/* check if cs sequence has encapsulated
+			 * signals handle
+			 */
+			struct idr *idp;
+			u32 id;
+
+			spin_lock(&ctx->sig_mgr.lock);
+			idp = &ctx->sig_mgr.handles;
+			idr_for_each_entry(idp, encaps_sig_hdl, id) {
+				if (encaps_sig_hdl->cs_seq == signal_seq) {
+					/* get refcount to protect removing this handle from idr,
+					 * needed when multiple wait cs are used with offset
+					 * to wait on reserved encaps signals.
+					 * Since kref_put of this handle is executed outside the
+					 * current lock, it is possible that the handle refcount
+					 * is 0 but it yet to be removed from the list. In this
+					 * case need to consider the handle as not valid.
+					 */
+					if (kref_get_unless_zero(&encaps_sig_hdl->refcount))
+						handle_found = true;
+					break;
+				}
+			}
+			spin_unlock(&ctx->sig_mgr.lock);
+
+			if (!handle_found) {
+				/* treat as signal CS already finished */
+				dev_dbg(hdev->dev, "Cannot find encapsulated signals handle for seq 0x%llx\n",
+						signal_seq);
+				rc = 0;
+				goto free_cs_chunk_array;
+			}
+
+			/* validate also the signal offset value */
+			if (chunk->encaps_signal_offset >
+					encaps_sig_hdl->count) {
+				dev_err(hdev->dev, "offset(%u) value exceed max reserved signals count(%u)!\n",
+						chunk->encaps_signal_offset,
+						encaps_sig_hdl->count);
+				rc = -EINVAL;
+				goto free_cs_chunk_array;
+			}
+		}
+
+		sig_fence = hl_ctx_get_fence(ctx, signal_seq);
+		if (IS_ERR(sig_fence)) {
+			atomic64_inc(&ctx->cs_counters.validation_drop_cnt);
+			atomic64_inc(&cntr->validation_drop_cnt);
+			dev_err(hdev->dev,
+				"Failed to get signal CS with seq 0x%llx\n",
+				signal_seq);
+			rc = PTR_ERR(sig_fence);
+			goto free_cs_chunk_array;
+		}
+
+		if (!sig_fence) {
+			/* signal CS already finished */
+			rc = 0;
+			goto free_cs_chunk_array;
+		}
+
+		sig_waitcs_cmpl =
+			container_of(sig_fence, struct hl_cs_compl, base_fence);
+
+		staged_cs_with_encaps_signals = !!
+				(sig_waitcs_cmpl->type == CS_TYPE_DEFAULT &&
+				(flags & HL_CS_FLAGS_ENCAP_SIGNALS));
+
+		if (sig_waitcs_cmpl->type != CS_TYPE_SIGNAL &&
+				!staged_cs_with_encaps_signals) {
+			atomic64_inc(&ctx->cs_counters.validation_drop_cnt);
+			atomic64_inc(&cntr->validation_drop_cnt);
+			dev_err(hdev->dev,
+				"CS seq 0x%llx is not of a signal/encaps-signal CS\n",
+				signal_seq);
+			hl_fence_put(sig_fence);
+			rc = -EINVAL;
+			goto free_cs_chunk_array;
+		}
+
+		if (completion_done(&sig_fence->completion)) {
+			/* signal CS already finished */
+			hl_fence_put(sig_fence);
+			rc = 0;
+			goto free_cs_chunk_array;
+		}
+	}
+
+	rc = allocate_cs(hdev, ctx, cs_type, ULLONG_MAX, &cs, flags, timeout);
+	if (rc) {
+		if (is_wait_cs)
+			hl_fence_put(sig_fence);
+
+		goto free_cs_chunk_array;
+	}
+
+	/*
+	 * Save the signal CS fence for later initialization right before
+	 * hanging the wait CS on the queue.
+	 * for encaps signals case, we save the cs sequence and handle pointer
+	 * for later initialization.
+	 */
+	if (is_wait_cs) {
+		cs->signal_fence = sig_fence;
+		/* store the handle pointer, so we don't have to
+		 * look for it again, later on the flow
+		 * when we need to set SOB info in hw_queue.
+		 */
+		if (cs->encaps_signals)
+			cs->encaps_sig_hdl = encaps_sig_hdl;
+	}
+
+	hl_debugfs_add_cs(cs);
+
+	*cs_seq = cs->sequence;
+
+	if (cs_type == CS_TYPE_WAIT || cs_type == CS_TYPE_SIGNAL)
+		rc = cs_ioctl_signal_wait_create_jobs(hdev, ctx, cs, q_type,
+				q_idx, chunk->encaps_signal_offset);
+	else if (cs_type == CS_TYPE_COLLECTIVE_WAIT)
+		rc = hdev->asic_funcs->collective_wait_create_jobs(hdev, ctx,
+				cs, q_idx, collective_engine_id,
+				chunk->encaps_signal_offset);
+	else {
+		atomic64_inc(&ctx->cs_counters.validation_drop_cnt);
+		atomic64_inc(&cntr->validation_drop_cnt);
+		rc = -EINVAL;
+	}
+
+	if (rc)
+		goto free_cs_object;
+
+	if (q_type == QUEUE_TYPE_HW)
+		INIT_WORK(&cs->finish_work, cs_completion);
+
+	rc = hl_hw_queue_schedule_cs(cs);
+	if (rc) {
+		/* In case wait cs failed here, it means the signal cs
+		 * already completed. we want to free all it's related objects
+		 * but we don't want to fail the ioctl.
+		 */
+		if (is_wait_cs)
+			rc = 0;
+		else if (rc != -EAGAIN)
+			dev_err(hdev->dev,
+				"Failed to submit CS %d.%llu to H/W queues, error %d\n",
+				ctx->asid, cs->sequence, rc);
+		goto free_cs_object;
+	}
+
+	*signal_sob_addr_offset = cs->sob_addr_offset;
+	*signal_initial_sob_count = cs->initial_sob_count;
+
+	rc = HL_CS_STATUS_SUCCESS;
+	if (is_wait_cs)
+		wait_cs_submitted = true;
+	goto put_cs;
+
+free_cs_object:
+	cs_rollback(hdev, cs);
+	*cs_seq = ULLONG_MAX;
+	/* The path below is both for good and erroneous exits */
+put_cs:
+	/* We finished with the CS in this function, so put the ref */
+	cs_put(cs);
+free_cs_chunk_array:
+	if (!wait_cs_submitted && cs_encaps_signals && handle_found && is_wait_cs)
+		kref_put(&encaps_sig_hdl->refcount, hl_encaps_release_handle_and_put_ctx);
+	kfree(cs_chunk_array);
+out:
+	return rc;
+}
+
+static int cs_ioctl_engine_cores(struct hl_fpriv *hpriv, u64 engine_cores,
+						u32 num_engine_cores, u32 core_command)
+{
+	struct hl_device *hdev = hpriv->hdev;
+	void __user *engine_cores_arr;
+	u32 *cores;
+	int rc;
+
+	if (!hdev->asic_prop.supports_engine_modes)
+		return -EPERM;
+
+	if (!num_engine_cores || num_engine_cores > hdev->asic_prop.num_engine_cores) {
+		dev_err(hdev->dev, "Number of engine cores %d is invalid\n", num_engine_cores);
+		return -EINVAL;
+	}
+
+	if (core_command != HL_ENGINE_CORE_RUN && core_command != HL_ENGINE_CORE_HALT) {
+		dev_err(hdev->dev, "Engine core command is invalid\n");
+		return -EINVAL;
+	}
+
+	engine_cores_arr = (void __user *) (uintptr_t) engine_cores;
+	cores = kmalloc_array(num_engine_cores, sizeof(u32), GFP_KERNEL);
+	if (!cores)
+		return -ENOMEM;
+
+	if (copy_from_user(cores, engine_cores_arr, num_engine_cores * sizeof(u32))) {
+		dev_err(hdev->dev, "Failed to copy core-ids array from user\n");
+		kfree(cores);
+		return -EFAULT;
+	}
+
+	rc = hdev->asic_funcs->set_engine_cores(hdev, cores, num_engine_cores, core_command);
+	kfree(cores);
+
+	return rc;
+}
+
+static int cs_ioctl_engines(struct hl_fpriv *hpriv, u64 engines_arr_user_addr,
+						u32 num_engines, enum hl_engine_command command)
+{
+	struct hl_device *hdev = hpriv->hdev;
+	u32 *engines, max_num_of_engines;
+	void __user *engines_arr;
+	int rc;
+
+	if (!hdev->asic_prop.supports_engine_modes)
+		return -EPERM;
+
+	if (command >= HL_ENGINE_COMMAND_MAX) {
+		dev_err(hdev->dev, "Engine command is invalid\n");
+		return -EINVAL;
+	}
+
+	max_num_of_engines = hdev->asic_prop.max_num_of_engines;
+	if (command == HL_ENGINE_CORE_RUN || command == HL_ENGINE_CORE_HALT)
+		max_num_of_engines = hdev->asic_prop.num_engine_cores;
+
+	if (!num_engines || num_engines > max_num_of_engines) {
+		dev_err(hdev->dev, "Number of engines %d is invalid\n", num_engines);
+		return -EINVAL;
+	}
+
+	engines_arr = (void __user *) (uintptr_t) engines_arr_user_addr;
+	engines = kmalloc_array(num_engines, sizeof(u32), GFP_KERNEL);
+	if (!engines)
+		return -ENOMEM;
+
+	if (copy_from_user(engines, engines_arr, num_engines * sizeof(u32))) {
+		dev_err(hdev->dev, "Failed to copy engine-ids array from user\n");
+		kfree(engines);
+		return -EFAULT;
+	}
+
+	rc = hdev->asic_funcs->set_engines(hdev, engines, num_engines, command);
+	kfree(engines);
+
+	return rc;
+}
+
+static int cs_ioctl_flush_pci_hbw_writes(struct hl_fpriv *hpriv)
+{
+	struct hl_device *hdev = hpriv->hdev;
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+
+	if (!prop->hbw_flush_reg) {
+		dev_dbg(hdev->dev, "HBW flush is not supported\n");
+		return -EOPNOTSUPP;
+	}
+
+	RREG32(prop->hbw_flush_reg);
+
+	return 0;
+}
+
+int hl_cs_ioctl(struct drm_device *ddev, void *data, struct drm_file *file_priv)
+{
+	struct hl_fpriv *hpriv = file_priv->driver_priv;
+	union hl_cs_args *args = data;
+	enum hl_cs_type cs_type = 0;
+	u64 cs_seq = ULONG_MAX;
+	void __user *chunks;
+	u32 num_chunks, flags, timeout,
+		signals_count = 0, sob_addr = 0, handle_id = 0;
+	u16 sob_initial_count = 0;
+	int rc;
+
+	rc = hl_cs_sanity_checks(hpriv, args);
+	if (rc)
+		goto out;
+
+	rc = hl_cs_ctx_switch(hpriv, args, &cs_seq);
+	if (rc)
+		goto out;
+
+	cs_type = hl_cs_get_cs_type(args->in.cs_flags &
+					~HL_CS_FLAGS_FORCE_RESTORE);
+	chunks = (void __user *) (uintptr_t) args->in.chunks_execute;
+	num_chunks = args->in.num_chunks_execute;
+	flags = args->in.cs_flags;
+
+	/* In case this is a staged CS, user should supply the CS sequence */
+	if ((flags & HL_CS_FLAGS_STAGED_SUBMISSION) &&
+			!(flags & HL_CS_FLAGS_STAGED_SUBMISSION_FIRST))
+		cs_seq = args->in.seq;
+
+	timeout = flags & HL_CS_FLAGS_CUSTOM_TIMEOUT
+			? secs_to_jiffies(args->in.timeout)
+			: hpriv->hdev->timeout_jiffies;
+
+	switch (cs_type) {
+	case CS_TYPE_SIGNAL:
+	case CS_TYPE_WAIT:
+	case CS_TYPE_COLLECTIVE_WAIT:
+		rc = cs_ioctl_signal_wait(hpriv, cs_type, chunks, num_chunks,
+					&cs_seq, args->in.cs_flags, timeout,
+					&sob_addr, &sob_initial_count);
+		break;
+	case CS_RESERVE_SIGNALS:
+		rc = cs_ioctl_reserve_signals(hpriv,
+					args->in.encaps_signals_q_idx,
+					args->in.encaps_signals_count,
+					&handle_id, &sob_addr, &signals_count);
+		break;
+	case CS_UNRESERVE_SIGNALS:
+		rc = cs_ioctl_unreserve_signals(hpriv,
+					args->in.encaps_sig_handle_id);
+		break;
+	case CS_TYPE_ENGINE_CORE:
+		rc = cs_ioctl_engine_cores(hpriv, args->in.engine_cores,
+				args->in.num_engine_cores, args->in.core_command);
+		break;
+	case CS_TYPE_ENGINES:
+		rc = cs_ioctl_engines(hpriv, args->in.engines,
+				args->in.num_engines, args->in.engine_command);
+		break;
+	case CS_TYPE_FLUSH_PCI_HBW_WRITES:
+		rc = cs_ioctl_flush_pci_hbw_writes(hpriv);
+		break;
+	default:
+		rc = cs_ioctl_default(hpriv, chunks, num_chunks, &cs_seq,
+						args->in.cs_flags,
+						args->in.encaps_sig_handle_id,
+						timeout, &sob_initial_count);
+		break;
+	}
+out:
+	if (rc != -EAGAIN) {
+		memset(args, 0, sizeof(*args));
+
+		switch (cs_type) {
+		case CS_RESERVE_SIGNALS:
+			args->out.handle_id = handle_id;
+			args->out.sob_base_addr_offset = sob_addr;
+			args->out.count = signals_count;
+			break;
+		case CS_TYPE_SIGNAL:
+			args->out.sob_base_addr_offset = sob_addr;
+			args->out.sob_count_before_submission = sob_initial_count;
+			args->out.seq = cs_seq;
+			break;
+		case CS_TYPE_DEFAULT:
+			args->out.sob_count_before_submission = sob_initial_count;
+			args->out.seq = cs_seq;
+			break;
+		default:
+			args->out.seq = cs_seq;
+			break;
+		}
+
+		args->out.status = rc;
+	}
+
+	return rc;
+}
+
+static int hl_wait_for_fence(struct hl_ctx *ctx, u64 seq, struct hl_fence *fence,
+				enum hl_cs_wait_status *status, u64 timeout_us, s64 *timestamp)
+{
+	struct hl_device *hdev = ctx->hdev;
+	ktime_t timestamp_kt;
+	long completion_rc;
+	int rc = 0, error;
+
+	if (IS_ERR(fence)) {
+		rc = PTR_ERR(fence);
+		if (rc == -EINVAL)
+			dev_notice_ratelimited(hdev->dev,
+				"Can't wait on CS %llu because current CS is at seq %llu\n",
+				seq, ctx->cs_sequence);
+		return rc;
+	}
+
+	if (!fence) {
+		if (!hl_pop_cs_outcome(&ctx->outcome_store, seq, &timestamp_kt, &error)) {
+			dev_dbg(hdev->dev,
+				"Can't wait on seq %llu because current CS is at seq %llu (Fence is gone)\n",
+				seq, ctx->cs_sequence);
+			*status = CS_WAIT_STATUS_GONE;
+			return 0;
+		}
+
+		completion_rc = 1;
+		goto report_results;
+	}
+
+	if (!timeout_us) {
+		completion_rc = completion_done(&fence->completion);
+	} else {
+		unsigned long timeout;
+
+		timeout = (timeout_us == MAX_SCHEDULE_TIMEOUT) ?
+				timeout_us : usecs_to_jiffies(timeout_us);
+		completion_rc =
+			wait_for_completion_interruptible_timeout(
+				&fence->completion, timeout);
+	}
+
+	error = fence->error;
+	timestamp_kt = fence->timestamp;
+
+report_results:
+	if (completion_rc > 0) {
+		*status = CS_WAIT_STATUS_COMPLETED;
+		if (timestamp)
+			*timestamp = ktime_to_ns(timestamp_kt);
+	} else {
+		*status = CS_WAIT_STATUS_BUSY;
+	}
+
+	if (completion_rc == -ERESTARTSYS)
+		rc = completion_rc;
+	else if (error == -ETIMEDOUT || error == -EIO)
+		rc = error;
+
+	return rc;
+}
+
+/*
+ * hl_cs_poll_fences - iterate CS fences to check for CS completion
+ *
+ * @mcs_data: multi-CS internal data
+ * @mcs_compl: multi-CS completion structure
+ *
+ * @return 0 on success, otherwise non 0 error code
+ *
+ * The function iterates on all CS sequence in the list and set bit in
+ * completion_bitmap for each completed CS.
+ * While iterating, the function sets the stream map of each fence in the fence
+ * array in the completion QID stream map to be used by CSs to perform
+ * completion to the multi-CS context.
+ * This function shall be called after taking context ref
+ */
+static int hl_cs_poll_fences(struct multi_cs_data *mcs_data, struct multi_cs_completion *mcs_compl)
+{
+	struct hl_fence **fence_ptr = mcs_data->fence_arr;
+	struct hl_device *hdev = mcs_data->ctx->hdev;
+	int i, rc, arr_len = mcs_data->arr_len;
+	u64 *seq_arr = mcs_data->seq_arr;
+	ktime_t max_ktime, first_cs_time;
+	enum hl_cs_wait_status status;
+
+	memset(fence_ptr, 0, arr_len * sizeof(struct hl_fence *));
+
+	/* get all fences under the same lock */
+	rc = hl_ctx_get_fences(mcs_data->ctx, seq_arr, fence_ptr, arr_len);
+	if (rc)
+		return rc;
+
+	/*
+	 * re-initialize the completion here to handle 2 possible cases:
+	 * 1. CS will complete the multi-CS prior clearing the completion. in which
+	 *    case the fence iteration is guaranteed to catch the CS completion.
+	 * 2. the completion will occur after re-init of the completion.
+	 *    in which case we will wake up immediately in wait_for_completion.
+	 */
+	reinit_completion(&mcs_compl->completion);
+
+	/*
+	 * set to maximum time to verify timestamp is valid: if at the end
+	 * this value is maintained- no timestamp was updated
+	 */
+	max_ktime = ktime_set(KTIME_SEC_MAX, 0);
+	first_cs_time = max_ktime;
+
+	for (i = 0; i < arr_len; i++, fence_ptr++) {
+		struct hl_fence *fence = *fence_ptr;
+
+		/*
+		 * In order to prevent case where we wait until timeout even though a CS associated
+		 * with the multi-CS actually completed we do things in the below order:
+		 * 1. for each fence set it's QID map in the multi-CS completion QID map. This way
+		 *    any CS can, potentially, complete the multi CS for the specific QID (note
+		 *    that once completion is initialized, calling complete* and then wait on the
+		 *    completion will cause it to return at once)
+		 * 2. only after allowing multi-CS completion for the specific QID we check whether
+		 *    the specific CS already completed (and thus the wait for completion part will
+		 *    be skipped). if the CS not completed it is guaranteed that completing CS will
+		 *    wake up the completion.
+		 */
+		if (fence)
+			mcs_compl->stream_master_qid_map |= fence->stream_master_qid_map;
+
+		/*
+		 * function won't sleep as it is called with timeout 0 (i.e.
+		 * poll the fence)
+		 */
+		rc = hl_wait_for_fence(mcs_data->ctx, seq_arr[i], fence, &status, 0, NULL);
+		if (rc) {
+			dev_err(hdev->dev,
+				"wait_for_fence error :%d for CS seq %llu\n",
+								rc, seq_arr[i]);
+			break;
+		}
+
+		switch (status) {
+		case CS_WAIT_STATUS_BUSY:
+			/* CS did not finished, QID to wait on already stored */
+			break;
+		case CS_WAIT_STATUS_COMPLETED:
+			/*
+			 * Using mcs_handling_done to avoid possibility of mcs_data
+			 * returns to user indicating CS completed before it finished
+			 * all of its mcs handling, to avoid race the next time the
+			 * user waits for mcs.
+			 * note: when reaching this case fence is definitely not NULL
+			 *       but NULL check was added to overcome static analysis
+			 */
+			if (fence && !fence->mcs_handling_done) {
+				/*
+				 * in case multi CS is completed but MCS handling not done
+				 * we "complete" the multi CS to prevent it from waiting
+				 * until time-out and the "multi-CS handling done" will have
+				 * another chance at the next iteration
+				 */
+				complete_all(&mcs_compl->completion);
+				break;
+			}
+
+			mcs_data->completion_bitmap |= BIT(i);
+			/*
+			 * For all completed CSs we take the earliest timestamp.
+			 * For this we have to validate that the timestamp is
+			 * earliest of all timestamps so far.
+			 */
+			if (fence && mcs_data->update_ts &&
+					(ktime_compare(fence->timestamp, first_cs_time) < 0))
+				first_cs_time = fence->timestamp;
+			break;
+		case CS_WAIT_STATUS_GONE:
+			mcs_data->update_ts = false;
+			mcs_data->gone_cs = true;
+			/*
+			 * It is possible to get an old sequence numbers from user
+			 * which related to already completed CSs and their fences
+			 * already gone. In this case, CS set as completed but
+			 * no need to consider its QID for mcs completion.
+			 */
+			mcs_data->completion_bitmap |= BIT(i);
+			break;
+		default:
+			dev_err(hdev->dev, "Invalid fence status\n");
+			rc = -EINVAL;
+			break;
+		}
+
+	}
+
+	hl_fences_put(mcs_data->fence_arr, arr_len);
+
+	if (mcs_data->update_ts &&
+			(ktime_compare(first_cs_time, max_ktime) != 0))
+		mcs_data->timestamp = ktime_to_ns(first_cs_time);
+
+	return rc;
+}
+
+static int _hl_cs_wait_ioctl(struct hl_device *hdev, struct hl_ctx *ctx, u64 timeout_us, u64 seq,
+				enum hl_cs_wait_status *status, s64 *timestamp)
+{
+	struct hl_fence *fence;
+	int rc = 0;
+
+	if (timestamp)
+		*timestamp = 0;
+
+	hl_ctx_get(ctx);
+
+	fence = hl_ctx_get_fence(ctx, seq);
+
+	rc = hl_wait_for_fence(ctx, seq, fence, status, timeout_us, timestamp);
+	hl_fence_put(fence);
+	hl_ctx_put(ctx);
+
+	return rc;
+}
+
+static inline unsigned long hl_usecs64_to_jiffies(const u64 usecs)
+{
+	if (usecs <= U32_MAX)
+		return usecs_to_jiffies(usecs);
+
+	/*
+	 * If the value in nanoseconds is larger than 64 bit, use the largest
+	 * 64 bit value.
+	 */
+	if (usecs >= ((u64)(U64_MAX / NSEC_PER_USEC)))
+		return nsecs_to_jiffies(U64_MAX);
+
+	return nsecs_to_jiffies(usecs * NSEC_PER_USEC);
+}
+
+/*
+ * hl_wait_multi_cs_completion_init - init completion structure
+ *
+ * @hdev: pointer to habanalabs device structure
+ * @stream_master_bitmap: stream master QIDs map, set bit indicates stream
+ *                        master QID to wait on
+ *
+ * @return valid completion struct pointer on success, otherwise error pointer
+ *
+ * up to MULTI_CS_MAX_USER_CTX calls can be done concurrently to the driver.
+ * the function gets the first available completion (by marking it "used")
+ * and initialize its values.
+ */
+static struct multi_cs_completion *hl_wait_multi_cs_completion_init(struct hl_device *hdev)
+{
+	struct multi_cs_completion *mcs_compl;
+	int i;
+
+	/* find free multi_cs completion structure */
+	for (i = 0; i < MULTI_CS_MAX_USER_CTX; i++) {
+		mcs_compl = &hdev->multi_cs_completion[i];
+		spin_lock(&mcs_compl->lock);
+		if (!mcs_compl->used) {
+			mcs_compl->used = 1;
+			mcs_compl->timestamp = 0;
+			/*
+			 * init QID map to 0 to avoid completion by CSs. the actual QID map
+			 * to multi-CS CSs will be set incrementally at a later stage
+			 */
+			mcs_compl->stream_master_qid_map = 0;
+			spin_unlock(&mcs_compl->lock);
+			break;
+		}
+		spin_unlock(&mcs_compl->lock);
+	}
+
+	if (i == MULTI_CS_MAX_USER_CTX) {
+		dev_err(hdev->dev, "no available multi-CS completion structure\n");
+		return ERR_PTR(-ENOMEM);
+	}
+	return mcs_compl;
+}
+
+/*
+ * hl_wait_multi_cs_completion_fini - return completion structure and set as
+ *                                    unused
+ *
+ * @mcs_compl: pointer to the completion structure
+ */
+static void hl_wait_multi_cs_completion_fini(
+					struct multi_cs_completion *mcs_compl)
+{
+	/*
+	 * free completion structure, do it under lock to be in-sync with the
+	 * thread that signals completion
+	 */
+	spin_lock(&mcs_compl->lock);
+	mcs_compl->used = 0;
+	spin_unlock(&mcs_compl->lock);
+}
+
+/*
+ * hl_wait_multi_cs_completion - wait for first CS to complete
+ *
+ * @mcs_data: multi-CS internal data
+ *
+ * @return 0 on success, otherwise non 0 error code
+ */
+static int hl_wait_multi_cs_completion(struct multi_cs_data *mcs_data,
+						struct multi_cs_completion *mcs_compl)
+{
+	long completion_rc;
+
+	completion_rc = wait_for_completion_interruptible_timeout(&mcs_compl->completion,
+									mcs_data->timeout_jiffies);
+
+	/* update timestamp */
+	if (completion_rc > 0)
+		mcs_data->timestamp = mcs_compl->timestamp;
+
+	if (completion_rc == -ERESTARTSYS)
+		return completion_rc;
+
+	mcs_data->wait_status = completion_rc;
+
+	return 0;
+}
+
+/*
+ * hl_multi_cs_completion_init - init array of multi-CS completion structures
+ *
+ * @hdev: pointer to habanalabs device structure
+ */
+void hl_multi_cs_completion_init(struct hl_device *hdev)
+{
+	struct multi_cs_completion *mcs_cmpl;
+	int i;
+
+	for (i = 0; i < MULTI_CS_MAX_USER_CTX; i++) {
+		mcs_cmpl = &hdev->multi_cs_completion[i];
+		mcs_cmpl->used = 0;
+		spin_lock_init(&mcs_cmpl->lock);
+		init_completion(&mcs_cmpl->completion);
+	}
+}
+
+/*
+ * hl_multi_cs_wait_ioctl - implementation of the multi-CS wait ioctl
+ *
+ * @hpriv: pointer to the private data of the fd
+ * @data: pointer to multi-CS wait ioctl in/out args
+ *
+ */
+static int hl_multi_cs_wait_ioctl(struct hl_fpriv *hpriv, void *data)
+{
+	struct multi_cs_completion *mcs_compl;
+	struct hl_device *hdev = hpriv->hdev;
+	struct multi_cs_data mcs_data = {};
+	union hl_wait_cs_args *args = data;
+	struct hl_ctx *ctx = hpriv->ctx;
+	struct hl_fence **fence_arr;
+	void __user *seq_arr;
+	u32 size_to_copy;
+	u64 *cs_seq_arr;
+	u8 seq_arr_len;
+	int rc, i;
+
+	for (i = 0 ; i < sizeof(args->in.pad) ; i++)
+		if (args->in.pad[i]) {
+			dev_dbg(hdev->dev, "Padding bytes must be 0\n");
+			return -EINVAL;
+		}
+
+	if (!hdev->supports_wait_for_multi_cs) {
+		dev_err(hdev->dev, "Wait for multi CS is not supported\n");
+		return -EPERM;
+	}
+
+	seq_arr_len = args->in.seq_arr_len;
+
+	if (seq_arr_len > HL_WAIT_MULTI_CS_LIST_MAX_LEN) {
+		dev_err(hdev->dev, "Can wait only up to %d CSs, input sequence is of length %u\n",
+				HL_WAIT_MULTI_CS_LIST_MAX_LEN, seq_arr_len);
+		return -EINVAL;
+	}
+
+	/* allocate memory for sequence array */
+	cs_seq_arr =
+		kmalloc_array(seq_arr_len, sizeof(*cs_seq_arr), GFP_KERNEL);
+	if (!cs_seq_arr)
+		return -ENOMEM;
+
+	/* copy CS sequence array from user */
+	seq_arr = (void __user *) (uintptr_t) args->in.seq;
+	size_to_copy = seq_arr_len * sizeof(*cs_seq_arr);
+	if (copy_from_user(cs_seq_arr, seq_arr, size_to_copy)) {
+		dev_err(hdev->dev, "Failed to copy multi-cs sequence array from user\n");
+		rc = -EFAULT;
+		goto free_seq_arr;
+	}
+
+	/* allocate array for the fences */
+	fence_arr = kmalloc_array(seq_arr_len, sizeof(struct hl_fence *), GFP_KERNEL);
+	if (!fence_arr) {
+		rc = -ENOMEM;
+		goto free_seq_arr;
+	}
+
+	/* initialize the multi-CS internal data */
+	mcs_data.ctx = ctx;
+	mcs_data.seq_arr = cs_seq_arr;
+	mcs_data.fence_arr = fence_arr;
+	mcs_data.arr_len = seq_arr_len;
+
+	hl_ctx_get(ctx);
+
+	/* wait (with timeout) for the first CS to be completed */
+	mcs_data.timeout_jiffies = hl_usecs64_to_jiffies(args->in.timeout_us);
+	mcs_compl = hl_wait_multi_cs_completion_init(hdev);
+	if (IS_ERR(mcs_compl)) {
+		rc = PTR_ERR(mcs_compl);
+		goto put_ctx;
+	}
+
+	/* poll all CS fences, extract timestamp */
+	mcs_data.update_ts = true;
+	rc = hl_cs_poll_fences(&mcs_data, mcs_compl);
+	/*
+	 * skip wait for CS completion when one of the below is true:
+	 * - an error on the poll function
+	 * - one or more CS in the list completed
+	 * - the user called ioctl with timeout 0
+	 */
+	if (rc || mcs_data.completion_bitmap || !args->in.timeout_us)
+		goto completion_fini;
+
+	while (true) {
+		rc = hl_wait_multi_cs_completion(&mcs_data, mcs_compl);
+		if (rc || (mcs_data.wait_status == 0))
+			break;
+
+		/*
+		 * poll fences once again to update the CS map.
+		 * no timestamp should be updated this time.
+		 */
+		mcs_data.update_ts = false;
+		rc = hl_cs_poll_fences(&mcs_data, mcs_compl);
+
+		if (rc || mcs_data.completion_bitmap)
+			break;
+
+		/*
+		 * if hl_wait_multi_cs_completion returned before timeout (i.e.
+		 * it got a completion) it either got completed by CS in the multi CS list
+		 * (in which case the indication will be non empty completion_bitmap) or it
+		 * got completed by CS submitted to one of the shared stream master but
+		 * not in the multi CS list (in which case we should wait again but modify
+		 * the timeout and set timestamp as zero to let a CS related to the current
+		 * multi-CS set a new, relevant, timestamp)
+		 */
+		mcs_data.timeout_jiffies = mcs_data.wait_status;
+		mcs_compl->timestamp = 0;
+	}
+
+completion_fini:
+	hl_wait_multi_cs_completion_fini(mcs_compl);
+
+put_ctx:
+	hl_ctx_put(ctx);
+	kfree(fence_arr);
+
+free_seq_arr:
+	kfree(cs_seq_arr);
+
+	if (rc == -ERESTARTSYS) {
+		dev_err_ratelimited(hdev->dev,
+				"user process got signal while waiting for Multi-CS\n");
+		rc = -EINTR;
+	}
+
+	if (rc)
+		return rc;
+
+	/* update output args */
+	memset(args, 0, sizeof(*args));
+
+	if (mcs_data.completion_bitmap) {
+		args->out.status = HL_WAIT_CS_STATUS_COMPLETED;
+		args->out.cs_completion_map = mcs_data.completion_bitmap;
+
+		/* if timestamp not 0- it's valid */
+		if (mcs_data.timestamp) {
+			args->out.timestamp_nsec = mcs_data.timestamp;
+			args->out.flags |= HL_WAIT_CS_STATUS_FLAG_TIMESTAMP_VLD;
+		}
+
+		/* update if some CS was gone */
+		if (!mcs_data.timestamp)
+			args->out.flags |= HL_WAIT_CS_STATUS_FLAG_GONE;
+	} else {
+		args->out.status = HL_WAIT_CS_STATUS_BUSY;
+	}
+
+	return 0;
+}
+
+static int hl_cs_wait_ioctl(struct hl_fpriv *hpriv, void *data)
+{
+	struct hl_device *hdev = hpriv->hdev;
+	union hl_wait_cs_args *args = data;
+	enum hl_cs_wait_status status;
+	u64 seq = args->in.seq;
+	s64 timestamp;
+	int rc;
+
+	rc = _hl_cs_wait_ioctl(hdev, hpriv->ctx, args->in.timeout_us, seq, &status, &timestamp);
+
+	if (rc == -ERESTARTSYS) {
+		dev_err_ratelimited(hdev->dev,
+			"user process got signal while waiting for CS handle %llu\n",
+			seq);
+		return -EINTR;
+	}
+
+	memset(args, 0, sizeof(*args));
+
+	if (rc) {
+		if (rc == -ETIMEDOUT) {
+			dev_err_ratelimited(hdev->dev,
+				"CS %llu has timed-out while user process is waiting for it\n",
+				seq);
+			args->out.status = HL_WAIT_CS_STATUS_TIMEDOUT;
+		} else if (rc == -EIO) {
+			dev_err_ratelimited(hdev->dev,
+				"CS %llu has been aborted while user process is waiting for it\n",
+				seq);
+			args->out.status = HL_WAIT_CS_STATUS_ABORTED;
+		}
+		return rc;
+	}
+
+	if (timestamp) {
+		args->out.flags |= HL_WAIT_CS_STATUS_FLAG_TIMESTAMP_VLD;
+		args->out.timestamp_nsec = timestamp;
+	}
+
+	switch (status) {
+	case CS_WAIT_STATUS_GONE:
+		args->out.flags |= HL_WAIT_CS_STATUS_FLAG_GONE;
+		fallthrough;
+	case CS_WAIT_STATUS_COMPLETED:
+		args->out.status = HL_WAIT_CS_STATUS_COMPLETED;
+		break;
+	case CS_WAIT_STATUS_BUSY:
+	default:
+		args->out.status = HL_WAIT_CS_STATUS_BUSY;
+		break;
+	}
+
+	return 0;
+}
+
+static inline void set_record_cq_info(struct hl_user_pending_interrupt *record,
+					struct hl_cb *cq_cb, u32 cq_offset, u32 target_value)
+{
+	record->ts_reg_info.cq_cb = cq_cb;
+	record->cq_kernel_addr = (u64 *) cq_cb->kernel_address + cq_offset;
+	record->cq_target_value = target_value;
+}
+
+static int validate_and_get_ts_record(struct device *dev,
+					struct hl_ts_buff *ts_buff, u64 ts_offset,
+					struct hl_user_pending_interrupt **req_event_record)
+{
+	struct hl_user_pending_interrupt *ts_cb_last;
+
+	*req_event_record = (struct hl_user_pending_interrupt *)ts_buff->kernel_buff_address +
+						ts_offset;
+	ts_cb_last = (struct hl_user_pending_interrupt *)ts_buff->kernel_buff_address +
+			(ts_buff->kernel_buff_size / sizeof(struct hl_user_pending_interrupt));
+
+	/* Validate ts_offset not exceeding last max */
+	if (*req_event_record >= ts_cb_last) {
+		dev_err(dev, "Ts offset(%llu) exceeds max CB offset(0x%llx)\n",
+				ts_offset, (u64)(uintptr_t)ts_cb_last);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static void unregister_timestamp_node(struct hl_device *hdev,
+			struct hl_user_pending_interrupt *record, bool need_lock)
+{
+	struct hl_user_interrupt *interrupt = record->ts_reg_info.interrupt;
+	bool ts_rec_found = false;
+	unsigned long flags;
+
+	if (need_lock)
+		spin_lock_irqsave(&interrupt->ts_list_lock, flags);
+
+	if (record->ts_reg_info.in_use) {
+		record->ts_reg_info.in_use = false;
+		list_del(&record->list_node);
+		ts_rec_found = true;
+	}
+
+	if (need_lock)
+		spin_unlock_irqrestore(&interrupt->ts_list_lock, flags);
+
+	/* Put refcounts that were taken when we registered the event */
+	if (ts_rec_found) {
+		hl_mmap_mem_buf_put(record->ts_reg_info.buf);
+		hl_cb_put(record->ts_reg_info.cq_cb);
+	}
+}
+
+static int ts_get_and_handle_kernel_record(struct hl_device *hdev, struct hl_ctx *ctx,
+					struct wait_interrupt_data *data, unsigned long *flags,
+					struct hl_user_pending_interrupt **pend)
+{
+	struct hl_user_pending_interrupt *req_offset_record;
+	struct hl_ts_buff *ts_buff = data->buf->private;
+	bool need_lock = false;
+	int rc;
+
+	rc = validate_and_get_ts_record(data->buf->mmg->dev, ts_buff, data->ts_offset,
+									&req_offset_record);
+	if (rc)
+		return rc;
+
+	/* In case the node already registered, need to unregister first then re-use */
+	if (req_offset_record->ts_reg_info.in_use) {
+		/*
+		 * Since interrupt here can be different than the one the node currently registered
+		 * on, and we don't want to lock two lists while we're doing unregister, so
+		 * unlock the new interrupt wait list here and acquire the lock again after you done
+		 */
+		if (data->interrupt->interrupt_id !=
+				req_offset_record->ts_reg_info.interrupt->interrupt_id) {
+
+			need_lock = true;
+			spin_unlock_irqrestore(&data->interrupt->ts_list_lock, *flags);
+		}
+
+		unregister_timestamp_node(hdev, req_offset_record, need_lock);
+
+		if (need_lock)
+			spin_lock_irqsave(&data->interrupt->ts_list_lock, *flags);
+	}
+
+	/* Fill up the new registration node info and add it to the list */
+	req_offset_record->ts_reg_info.in_use = true;
+	req_offset_record->ts_reg_info.buf = data->buf;
+	req_offset_record->ts_reg_info.timestamp_kernel_addr =
+			(u64 *) ts_buff->user_buff_address + data->ts_offset;
+	req_offset_record->ts_reg_info.interrupt = data->interrupt;
+	set_record_cq_info(req_offset_record, data->cq_cb, data->cq_offset,
+						data->target_value);
+
+	*pend = req_offset_record;
+
+	return rc;
+}
+
+static int _hl_interrupt_ts_reg_ioctl(struct hl_device *hdev, struct hl_ctx *ctx,
+				struct wait_interrupt_data *data,
+				u32 *status, u64 *timestamp)
+{
+	struct hl_user_pending_interrupt *pend;
+	unsigned long flags;
+	int rc = 0;
+
+	hl_ctx_get(ctx);
+
+	data->cq_cb = hl_cb_get(data->mmg, data->cq_handle);
+	if (!data->cq_cb) {
+		rc = -EINVAL;
+		goto put_ctx;
+	}
+
+	/* Validate the cq offset */
+	if (((u64 *) data->cq_cb->kernel_address + data->cq_offset) >=
+			((u64 *) data->cq_cb->kernel_address + (data->cq_cb->size / sizeof(u64)))) {
+		rc = -EINVAL;
+		goto put_cq_cb;
+	}
+
+	data->buf = hl_mmap_mem_buf_get(data->mmg, data->ts_handle);
+	if (!data->buf) {
+		rc = -EINVAL;
+		goto put_cq_cb;
+	}
+
+	spin_lock_irqsave(&data->interrupt->ts_list_lock, flags);
+
+	/* get ts buffer record */
+	rc = ts_get_and_handle_kernel_record(hdev, ctx, data, &flags, &pend);
+	if (rc) {
+		spin_unlock_irqrestore(&data->interrupt->ts_list_lock, flags);
+		goto put_ts_buff;
+	}
+
+	/* We check for completion value as interrupt could have been received
+	 * before we add the timestamp node to the ts list.
+	 */
+	if (*pend->cq_kernel_addr >= data->target_value) {
+		spin_unlock_irqrestore(&data->interrupt->ts_list_lock, flags);
+
+		pend->ts_reg_info.in_use = 0;
+		*status = HL_WAIT_CS_STATUS_COMPLETED;
+		*pend->ts_reg_info.timestamp_kernel_addr = ktime_get_ns();
+
+		goto put_ts_buff;
+	}
+
+	list_add_tail(&pend->list_node, &data->interrupt->ts_list_head);
+	spin_unlock_irqrestore(&data->interrupt->ts_list_lock, flags);
+
+	rc = *status = HL_WAIT_CS_STATUS_COMPLETED;
+
+	hl_ctx_put(ctx);
+
+	return rc;
+
+put_ts_buff:
+	hl_mmap_mem_buf_put(data->buf);
+put_cq_cb:
+	hl_cb_put(data->cq_cb);
+put_ctx:
+	hl_ctx_put(ctx);
+
+	return rc;
+}
+
+static int _hl_interrupt_wait_ioctl(struct hl_device *hdev, struct hl_ctx *ctx,
+				struct wait_interrupt_data *data,
+				u32 *status, u64 *timestamp)
+{
+	struct hl_user_pending_interrupt *pend;
+	unsigned long timeout, flags;
+	long completion_rc;
+	int rc = 0;
+
+	timeout = hl_usecs64_to_jiffies(data->intr_timeout_us);
+
+	hl_ctx_get(ctx);
+
+	data->cq_cb = hl_cb_get(data->mmg, data->cq_handle);
+	if (!data->cq_cb) {
+		rc = -EINVAL;
+		goto put_ctx;
+	}
+
+	/* Validate the cq offset */
+	if (((u64 *) data->cq_cb->kernel_address + data->cq_offset) >=
+			((u64 *) data->cq_cb->kernel_address + (data->cq_cb->size / sizeof(u64)))) {
+		rc = -EINVAL;
+		goto put_cq_cb;
+	}
+
+	pend = kzalloc(sizeof(*pend), GFP_KERNEL);
+	if (!pend) {
+		rc = -ENOMEM;
+		goto put_cq_cb;
+	}
+
+	hl_fence_init(&pend->fence, ULONG_MAX);
+	pend->cq_kernel_addr = (u64 *) data->cq_cb->kernel_address + data->cq_offset;
+	pend->cq_target_value = data->target_value;
+	spin_lock_irqsave(&data->interrupt->wait_list_lock, flags);
+
+
+	/* We check for completion value as interrupt could have been received
+	 * before we add the wait node to the wait list.
+	 */
+	if (*pend->cq_kernel_addr >= data->target_value || (!data->intr_timeout_us)) {
+		spin_unlock_irqrestore(&data->interrupt->wait_list_lock, flags);
+
+		if (*pend->cq_kernel_addr >= data->target_value)
+			*status = HL_WAIT_CS_STATUS_COMPLETED;
+		else
+			*status = HL_WAIT_CS_STATUS_BUSY;
+
+		pend->fence.timestamp = ktime_get();
+		goto set_timestamp;
+	}
+
+	/* Add pending user interrupt to relevant list for the interrupt
+	 * handler to monitor.
+	 * Note that we cannot have sorted list by target value,
+	 * in order to shorten the list pass loop, since
+	 * same list could have nodes for different cq counter handle.
+	 */
+	list_add_tail(&pend->list_node, &data->interrupt->wait_list_head);
+	spin_unlock_irqrestore(&data->interrupt->wait_list_lock, flags);
+
+	/* Wait for interrupt handler to signal completion */
+	completion_rc = wait_for_completion_interruptible_timeout(&pend->fence.completion,
+								timeout);
+	if (completion_rc > 0) {
+		if (pend->fence.error == -EIO) {
+			dev_err_ratelimited(hdev->dev,
+					"interrupt based wait ioctl aborted(error:%d) due to a reset cycle initiated\n",
+					pend->fence.error);
+			rc = -EIO;
+			*status = HL_WAIT_CS_STATUS_ABORTED;
+		} else {
+			*status = HL_WAIT_CS_STATUS_COMPLETED;
+		}
+	} else {
+		if (completion_rc == -ERESTARTSYS) {
+			dev_err_ratelimited(hdev->dev,
+					"user process got signal while waiting for interrupt ID %d\n",
+					data->interrupt->interrupt_id);
+			rc = -EINTR;
+			*status = HL_WAIT_CS_STATUS_ABORTED;
+		} else {
+			/* The wait has timed-out. We don't know anything beyond that
+			 * because the workload was not submitted through the driver.
+			 * Therefore, from driver's perspective, the workload is still
+			 * executing.
+			 */
+			rc = 0;
+			*status = HL_WAIT_CS_STATUS_BUSY;
+		}
+	}
+
+	/*
+	 * We keep removing the node from list here, and not at the irq handler
+	 * for completion timeout case. and if it's a registration
+	 * for ts record, the node will be deleted in the irq handler after
+	 * we reach the target value.
+	 */
+	spin_lock_irqsave(&data->interrupt->wait_list_lock, flags);
+	list_del(&pend->list_node);
+	spin_unlock_irqrestore(&data->interrupt->wait_list_lock, flags);
+
+set_timestamp:
+	*timestamp = ktime_to_ns(pend->fence.timestamp);
+	kfree(pend);
+	hl_cb_put(data->cq_cb);
+	hl_ctx_put(ctx);
+
+	return rc;
+
+put_cq_cb:
+	hl_cb_put(data->cq_cb);
+put_ctx:
+	hl_ctx_put(ctx);
+
+	return rc;
+}
+
+static int _hl_interrupt_wait_ioctl_user_addr(struct hl_device *hdev, struct hl_ctx *ctx,
+				u64 timeout_us, u64 user_address,
+				u64 target_value, struct hl_user_interrupt *interrupt,
+				u32 *status,
+				u64 *timestamp)
+{
+	struct hl_user_pending_interrupt *pend;
+	unsigned long timeout, flags;
+	u64 completion_value;
+	long completion_rc;
+	int rc = 0;
+
+	timeout = hl_usecs64_to_jiffies(timeout_us);
+
+	hl_ctx_get(ctx);
+
+	pend = kzalloc(sizeof(*pend), GFP_KERNEL);
+	if (!pend) {
+		hl_ctx_put(ctx);
+		return -ENOMEM;
+	}
+
+	hl_fence_init(&pend->fence, ULONG_MAX);
+
+	/* Add pending user interrupt to relevant list for the interrupt
+	 * handler to monitor
+	 */
+	spin_lock_irqsave(&interrupt->wait_list_lock, flags);
+	list_add_tail(&pend->list_node, &interrupt->wait_list_head);
+	spin_unlock_irqrestore(&interrupt->wait_list_lock, flags);
+
+	/* We check for completion value as interrupt could have been received
+	 * before we added the node to the wait list
+	 */
+	if (copy_from_user(&completion_value, u64_to_user_ptr(user_address), 8)) {
+		dev_err(hdev->dev, "Failed to copy completion value from user\n");
+		rc = -EFAULT;
+		goto remove_pending_user_interrupt;
+	}
+
+	if (completion_value >= target_value) {
+		*status = HL_WAIT_CS_STATUS_COMPLETED;
+		/* There was no interrupt, we assume the completion is now. */
+		pend->fence.timestamp = ktime_get();
+	} else {
+		*status = HL_WAIT_CS_STATUS_BUSY;
+	}
+
+	if (!timeout_us || (*status == HL_WAIT_CS_STATUS_COMPLETED))
+		goto remove_pending_user_interrupt;
+
+wait_again:
+	/* Wait for interrupt handler to signal completion */
+	completion_rc = wait_for_completion_interruptible_timeout(&pend->fence.completion,
+										timeout);
+
+	/* If timeout did not expire we need to perform the comparison.
+	 * If comparison fails, keep waiting until timeout expires
+	 */
+	if (completion_rc > 0) {
+		spin_lock_irqsave(&interrupt->wait_list_lock, flags);
+		/* reinit_completion must be called before we check for user
+		 * completion value, otherwise, if interrupt is received after
+		 * the comparison and before the next wait_for_completion,
+		 * we will reach timeout and fail
+		 */
+		reinit_completion(&pend->fence.completion);
+		spin_unlock_irqrestore(&interrupt->wait_list_lock, flags);
+
+		if (copy_from_user(&completion_value, u64_to_user_ptr(user_address), 8)) {
+			dev_err(hdev->dev, "Failed to copy completion value from user\n");
+			rc = -EFAULT;
+
+			goto remove_pending_user_interrupt;
+		}
+
+		if (completion_value >= target_value) {
+			*status = HL_WAIT_CS_STATUS_COMPLETED;
+		} else if (pend->fence.error) {
+			dev_err_ratelimited(hdev->dev,
+				"interrupt based wait ioctl aborted(error:%d) due to a reset cycle initiated\n",
+				pend->fence.error);
+			/* set the command completion status as ABORTED */
+			*status = HL_WAIT_CS_STATUS_ABORTED;
+		} else {
+			timeout = completion_rc;
+			goto wait_again;
+		}
+	} else if (completion_rc == -ERESTARTSYS) {
+		dev_err_ratelimited(hdev->dev,
+			"user process got signal while waiting for interrupt ID %d\n",
+			interrupt->interrupt_id);
+		rc = -EINTR;
+	} else {
+		/* The wait has timed-out. We don't know anything beyond that
+		 * because the workload wasn't submitted through the driver.
+		 * Therefore, from driver's perspective, the workload is still
+		 * executing.
+		 */
+		rc = 0;
+		*status = HL_WAIT_CS_STATUS_BUSY;
+	}
+
+remove_pending_user_interrupt:
+	spin_lock_irqsave(&interrupt->wait_list_lock, flags);
+	list_del(&pend->list_node);
+	spin_unlock_irqrestore(&interrupt->wait_list_lock, flags);
+
+	*timestamp = ktime_to_ns(pend->fence.timestamp);
+
+	kfree(pend);
+	hl_ctx_put(ctx);
+
+	return rc;
+}
+
+static int hl_interrupt_wait_ioctl(struct hl_fpriv *hpriv, void *data)
+{
+	u16 interrupt_id, first_interrupt, last_interrupt;
+	struct hl_device *hdev = hpriv->hdev;
+	struct asic_fixed_properties *prop;
+	struct hl_user_interrupt *interrupt;
+	union hl_wait_cs_args *args = data;
+	u32 status = HL_WAIT_CS_STATUS_BUSY;
+	u64 timestamp = 0;
+	int rc, int_idx;
+
+	prop = &hdev->asic_prop;
+
+	if (!(prop->user_interrupt_count + prop->user_dec_intr_count)) {
+		dev_err(hdev->dev, "no user interrupts allowed");
+		return -EPERM;
+	}
+
+	interrupt_id = FIELD_GET(HL_WAIT_CS_FLAGS_INTERRUPT_MASK, args->in.flags);
+
+	first_interrupt = prop->first_available_user_interrupt;
+	last_interrupt = prop->first_available_user_interrupt + prop->user_interrupt_count - 1;
+
+	if (interrupt_id < prop->user_dec_intr_count) {
+
+		/* Check if the requested core is enabled */
+		if (!(prop->decoder_enabled_mask & BIT(interrupt_id))) {
+			dev_err(hdev->dev, "interrupt on a disabled core(%u) not allowed",
+				interrupt_id);
+			return -EINVAL;
+		}
+
+		interrupt = &hdev->user_interrupt[interrupt_id];
+
+	} else if (interrupt_id >= first_interrupt && interrupt_id <= last_interrupt) {
+
+		int_idx = interrupt_id - first_interrupt + prop->user_dec_intr_count;
+		interrupt = &hdev->user_interrupt[int_idx];
+
+	} else if (interrupt_id == HL_COMMON_USER_CQ_INTERRUPT_ID) {
+		interrupt = &hdev->common_user_cq_interrupt;
+	} else if (interrupt_id == HL_COMMON_DEC_INTERRUPT_ID) {
+		interrupt = &hdev->common_decoder_interrupt;
+	} else {
+		dev_err(hdev->dev, "invalid user interrupt %u", interrupt_id);
+		return -EINVAL;
+	}
+
+	if (args->in.flags & HL_WAIT_CS_FLAGS_INTERRUPT_KERNEL_CQ) {
+		struct wait_interrupt_data wait_intr_data = {0};
+
+		wait_intr_data.interrupt = interrupt;
+		wait_intr_data.mmg = &hpriv->mem_mgr;
+		wait_intr_data.cq_handle = args->in.cq_counters_handle;
+		wait_intr_data.cq_offset = args->in.cq_counters_offset;
+		wait_intr_data.ts_handle = args->in.timestamp_handle;
+		wait_intr_data.ts_offset = args->in.timestamp_offset;
+		wait_intr_data.target_value = args->in.target;
+		wait_intr_data.intr_timeout_us = args->in.interrupt_timeout_us;
+
+		if (args->in.flags & HL_WAIT_CS_FLAGS_REGISTER_INTERRUPT) {
+			/*
+			 * Allow only one registration at a time. this is needed in order to prevent
+			 * issues while handling the flow of re-use of the same offset.
+			 * Since the registration flow is protected only by the interrupt lock,
+			 * re-use flow might request to move ts node to another interrupt list,
+			 * and in such case we're not protected.
+			 */
+			mutex_lock(&hpriv->ctx->ts_reg_lock);
+
+			rc = _hl_interrupt_ts_reg_ioctl(hdev, hpriv->ctx, &wait_intr_data,
+						&status, &timestamp);
+
+			mutex_unlock(&hpriv->ctx->ts_reg_lock);
+		} else
+			rc = _hl_interrupt_wait_ioctl(hdev, hpriv->ctx, &wait_intr_data,
+						&status, &timestamp);
+	} else {
+		rc = _hl_interrupt_wait_ioctl_user_addr(hdev, hpriv->ctx,
+				args->in.interrupt_timeout_us, args->in.addr,
+				args->in.target, interrupt, &status,
+				&timestamp);
+	}
+
+	if (rc)
+		return rc;
+
+	memset(args, 0, sizeof(*args));
+	args->out.status = status;
+
+	if (timestamp) {
+		args->out.timestamp_nsec = timestamp;
+		args->out.flags |= HL_WAIT_CS_STATUS_FLAG_TIMESTAMP_VLD;
+	}
+
+	return 0;
+}
+
+int hl_wait_ioctl(struct drm_device *ddev, void *data, struct drm_file *file_priv)
+{
+	struct hl_fpriv *hpriv = file_priv->driver_priv;
+	struct hl_device *hdev = hpriv->hdev;
+	union hl_wait_cs_args *args = data;
+	u32 flags = args->in.flags;
+	int rc;
+
+	/* If the device is not operational, or if an error has happened and user should release the
+	 * device, there is no point in waiting for any command submission or user interrupt.
+	 */
+	if (!hl_device_operational(hpriv->hdev, NULL) || hdev->reset_info.watchdog_active)
+		return -EBUSY;
+
+	if (flags & HL_WAIT_CS_FLAGS_INTERRUPT)
+		rc = hl_interrupt_wait_ioctl(hpriv, data);
+	else if (flags & HL_WAIT_CS_FLAGS_MULTI_CS)
+		rc = hl_multi_cs_wait_ioctl(hpriv, data);
+	else
+		rc = hl_cs_wait_ioctl(hpriv, data);
+
+	return rc;
+}
diff --git a/drivers/accel/habanalabs/common/context.c b/drivers/accel/habanalabs/common/context.c
new file mode 100644
index 000000000000..9f212b17611a
--- /dev/null
+++ b/drivers/accel/habanalabs/common/context.c
@@ -0,0 +1,449 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Copyright 2016-2021 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ */
+
+#include "habanalabs.h"
+
+#include <linux/slab.h>
+
+static void encaps_handle_do_release(struct hl_cs_encaps_sig_handle *handle, bool put_hw_sob,
+					bool put_ctx)
+{
+	struct hl_encaps_signals_mgr *mgr = &handle->ctx->sig_mgr;
+
+	if (put_hw_sob)
+		hw_sob_put(handle->hw_sob);
+
+	spin_lock(&mgr->lock);
+	idr_remove(&mgr->handles, handle->id);
+	spin_unlock(&mgr->lock);
+
+	if (put_ctx)
+		hl_ctx_put(handle->ctx);
+
+	kfree(handle);
+}
+
+void hl_encaps_release_handle_and_put_ctx(struct kref *ref)
+{
+	struct hl_cs_encaps_sig_handle *handle =
+			container_of(ref, struct hl_cs_encaps_sig_handle, refcount);
+
+	encaps_handle_do_release(handle, false, true);
+}
+
+static void hl_encaps_release_handle_and_put_sob(struct kref *ref)
+{
+	struct hl_cs_encaps_sig_handle *handle =
+			container_of(ref, struct hl_cs_encaps_sig_handle, refcount);
+
+	encaps_handle_do_release(handle, true, false);
+}
+
+void hl_encaps_release_handle_and_put_sob_ctx(struct kref *ref)
+{
+	struct hl_cs_encaps_sig_handle *handle =
+			container_of(ref, struct hl_cs_encaps_sig_handle, refcount);
+
+	encaps_handle_do_release(handle, true, true);
+}
+
+static void hl_encaps_sig_mgr_init(struct hl_encaps_signals_mgr *mgr)
+{
+	spin_lock_init(&mgr->lock);
+	idr_init(&mgr->handles);
+}
+
+static void hl_encaps_sig_mgr_fini(struct hl_device *hdev, struct hl_encaps_signals_mgr *mgr)
+{
+	struct hl_cs_encaps_sig_handle *handle;
+	struct idr *idp;
+	u32 id;
+
+	idp = &mgr->handles;
+
+	/* The IDR is expected to be empty at this stage, because any left signal should have been
+	 * released as part of CS roll-back.
+	 */
+	if (!idr_is_empty(idp)) {
+		dev_warn(hdev->dev,
+			"device released while some encaps signals handles are still allocated\n");
+		idr_for_each_entry(idp, handle, id)
+			kref_put(&handle->refcount, hl_encaps_release_handle_and_put_sob);
+	}
+
+	idr_destroy(&mgr->handles);
+}
+
+static void hl_ctx_fini(struct hl_ctx *ctx)
+{
+	struct hl_device *hdev = ctx->hdev;
+	int i;
+
+	/* Release all allocated HW block mapped list entries and destroy
+	 * the mutex.
+	 */
+	hl_hw_block_mem_fini(ctx);
+
+	/*
+	 * If we arrived here, there are no jobs waiting for this context
+	 * on its queues so we can safely remove it.
+	 * This is because for each CS, we increment the ref count and for
+	 * every CS that was finished we decrement it and we won't arrive
+	 * to this function unless the ref count is 0
+	 */
+
+	for (i = 0 ; i < hdev->asic_prop.max_pending_cs ; i++)
+		hl_fence_put(ctx->cs_pending[i]);
+
+	kfree(ctx->cs_pending);
+
+	if (ctx->asid != HL_KERNEL_ASID_ID) {
+		dev_dbg(hdev->dev, "closing user context, asid=%u\n", ctx->asid);
+
+		/* The engines are stopped as there is no executing CS, but the
+		 * Coresight might be still working by accessing addresses
+		 * related to the stopped engines. Hence stop it explicitly.
+		 */
+		if (hdev->in_debug)
+			hl_device_set_debug_mode(hdev, ctx, false);
+
+		hdev->asic_funcs->ctx_fini(ctx);
+
+		hl_dec_ctx_fini(ctx);
+
+		hl_cb_va_pool_fini(ctx);
+		hl_vm_ctx_fini(ctx);
+		hl_asid_free(hdev, ctx->asid);
+		hl_encaps_sig_mgr_fini(hdev, &ctx->sig_mgr);
+		mutex_destroy(&ctx->ts_reg_lock);
+	} else {
+		dev_dbg(hdev->dev, "closing kernel context\n");
+		hdev->asic_funcs->ctx_fini(ctx);
+		hl_vm_ctx_fini(ctx);
+		hl_mmu_ctx_fini(ctx);
+	}
+}
+
+void hl_ctx_do_release(struct kref *ref)
+{
+	struct hl_ctx *ctx;
+
+	ctx = container_of(ref, struct hl_ctx, refcount);
+
+	hl_ctx_fini(ctx);
+
+	if (ctx->hpriv) {
+		struct hl_fpriv *hpriv = ctx->hpriv;
+
+		mutex_lock(&hpriv->ctx_lock);
+		hpriv->ctx = NULL;
+		mutex_unlock(&hpriv->ctx_lock);
+
+		hl_hpriv_put(hpriv);
+	}
+
+	kfree(ctx);
+}
+
+int hl_ctx_create(struct hl_device *hdev, struct hl_fpriv *hpriv)
+{
+	struct hl_ctx_mgr *ctx_mgr = &hpriv->ctx_mgr;
+	struct hl_ctx *ctx;
+	int rc;
+
+	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
+	if (!ctx) {
+		rc = -ENOMEM;
+		goto out_err;
+	}
+
+	mutex_lock(&ctx_mgr->lock);
+	rc = idr_alloc(&ctx_mgr->handles, ctx, 1, 0, GFP_KERNEL);
+	mutex_unlock(&ctx_mgr->lock);
+
+	if (rc < 0) {
+		dev_err(hdev->dev, "Failed to allocate IDR for a new CTX\n");
+		goto free_ctx;
+	}
+
+	ctx->handle = rc;
+
+	rc = hl_ctx_init(hdev, ctx, false);
+	if (rc)
+		goto remove_from_idr;
+
+	hl_hpriv_get(hpriv);
+	ctx->hpriv = hpriv;
+
+	/* TODO: remove for multiple contexts per process */
+	hpriv->ctx = ctx;
+
+	/* TODO: remove the following line for multiple process support */
+	hdev->is_compute_ctx_active = true;
+
+	return 0;
+
+remove_from_idr:
+	mutex_lock(&ctx_mgr->lock);
+	idr_remove(&ctx_mgr->handles, ctx->handle);
+	mutex_unlock(&ctx_mgr->lock);
+free_ctx:
+	kfree(ctx);
+out_err:
+	return rc;
+}
+
+int hl_ctx_init(struct hl_device *hdev, struct hl_ctx *ctx, bool is_kernel_ctx)
+{
+	int rc = 0, i;
+
+	ctx->hdev = hdev;
+
+	kref_init(&ctx->refcount);
+
+	ctx->cs_sequence = 1;
+	spin_lock_init(&ctx->cs_lock);
+	atomic_set(&ctx->thread_ctx_switch_token, 1);
+	ctx->thread_ctx_switch_wait_token = 0;
+	ctx->cs_pending = kcalloc(hdev->asic_prop.max_pending_cs,
+				sizeof(struct hl_fence *),
+				GFP_KERNEL);
+	if (!ctx->cs_pending)
+		return -ENOMEM;
+
+	INIT_LIST_HEAD(&ctx->outcome_store.used_list);
+	INIT_LIST_HEAD(&ctx->outcome_store.free_list);
+	hash_init(ctx->outcome_store.outcome_map);
+	for (i = 0; i < ARRAY_SIZE(ctx->outcome_store.nodes_pool); ++i)
+		list_add(&ctx->outcome_store.nodes_pool[i].list_link,
+			 &ctx->outcome_store.free_list);
+
+	hl_hw_block_mem_init(ctx);
+
+	if (is_kernel_ctx) {
+		ctx->asid = HL_KERNEL_ASID_ID; /* Kernel driver gets ASID 0 */
+		rc = hl_vm_ctx_init(ctx);
+		if (rc) {
+			dev_err(hdev->dev, "Failed to init mem ctx module\n");
+			rc = -ENOMEM;
+			goto err_hw_block_mem_fini;
+		}
+
+		rc = hdev->asic_funcs->ctx_init(ctx);
+		if (rc) {
+			dev_err(hdev->dev, "ctx_init failed\n");
+			goto err_vm_ctx_fini;
+		}
+	} else {
+		ctx->asid = hl_asid_alloc(hdev);
+		if (!ctx->asid) {
+			dev_err(hdev->dev, "No free ASID, failed to create context\n");
+			rc = -ENOMEM;
+			goto err_hw_block_mem_fini;
+		}
+
+		rc = hl_vm_ctx_init(ctx);
+		if (rc) {
+			dev_err(hdev->dev, "Failed to init mem ctx module\n");
+			rc = -ENOMEM;
+			goto err_asid_free;
+		}
+
+		rc = hl_cb_va_pool_init(ctx);
+		if (rc) {
+			dev_err(hdev->dev,
+				"Failed to init VA pool for mapped CB\n");
+			goto err_vm_ctx_fini;
+		}
+
+		rc = hdev->asic_funcs->ctx_init(ctx);
+		if (rc) {
+			dev_err(hdev->dev, "ctx_init failed\n");
+			goto err_cb_va_pool_fini;
+		}
+
+		hl_encaps_sig_mgr_init(&ctx->sig_mgr);
+
+		mutex_init(&ctx->ts_reg_lock);
+
+		dev_dbg(hdev->dev, "create user context, comm=\"%s\", asid=%u\n",
+			current->comm, ctx->asid);
+	}
+
+	return 0;
+
+err_cb_va_pool_fini:
+	hl_cb_va_pool_fini(ctx);
+err_vm_ctx_fini:
+	hl_vm_ctx_fini(ctx);
+err_asid_free:
+	if (ctx->asid != HL_KERNEL_ASID_ID)
+		hl_asid_free(hdev, ctx->asid);
+err_hw_block_mem_fini:
+	hl_hw_block_mem_fini(ctx);
+	kfree(ctx->cs_pending);
+
+	return rc;
+}
+
+static int hl_ctx_get_unless_zero(struct hl_ctx *ctx)
+{
+	return kref_get_unless_zero(&ctx->refcount);
+}
+
+void hl_ctx_get(struct hl_ctx *ctx)
+{
+	kref_get(&ctx->refcount);
+}
+
+int hl_ctx_put(struct hl_ctx *ctx)
+{
+	return kref_put(&ctx->refcount, hl_ctx_do_release);
+}
+
+struct hl_ctx *hl_get_compute_ctx(struct hl_device *hdev)
+{
+	struct hl_ctx *ctx = NULL;
+	struct hl_fpriv *hpriv;
+
+	mutex_lock(&hdev->fpriv_list_lock);
+
+	list_for_each_entry(hpriv, &hdev->fpriv_list, dev_node) {
+		mutex_lock(&hpriv->ctx_lock);
+		ctx = hpriv->ctx;
+		if (ctx && !hl_ctx_get_unless_zero(ctx))
+			ctx = NULL;
+		mutex_unlock(&hpriv->ctx_lock);
+
+		/* There can only be a single user which has opened the compute device, so exit
+		 * immediately once we find its context or if we see that it has been released
+		 */
+		break;
+	}
+
+	mutex_unlock(&hdev->fpriv_list_lock);
+
+	return ctx;
+}
+
+/*
+ * hl_ctx_get_fence_locked - get CS fence under CS lock
+ *
+ * @ctx: pointer to the context structure.
+ * @seq: CS sequences number
+ *
+ * @return valid fence pointer on success, NULL if fence is gone, otherwise
+ *         error pointer.
+ *
+ * NOTE: this function shall be called with cs_lock locked
+ */
+static struct hl_fence *hl_ctx_get_fence_locked(struct hl_ctx *ctx, u64 seq)
+{
+	struct asic_fixed_properties *asic_prop = &ctx->hdev->asic_prop;
+	struct hl_fence *fence;
+
+	if (seq >= ctx->cs_sequence)
+		return ERR_PTR(-EINVAL);
+
+	if (seq + asic_prop->max_pending_cs < ctx->cs_sequence)
+		return NULL;
+
+	fence = ctx->cs_pending[seq & (asic_prop->max_pending_cs - 1)];
+	hl_fence_get(fence);
+	return fence;
+}
+
+struct hl_fence *hl_ctx_get_fence(struct hl_ctx *ctx, u64 seq)
+{
+	struct hl_fence *fence;
+
+	spin_lock(&ctx->cs_lock);
+
+	fence = hl_ctx_get_fence_locked(ctx, seq);
+
+	spin_unlock(&ctx->cs_lock);
+
+	return fence;
+}
+
+/*
+ * hl_ctx_get_fences - get multiple CS fences under the same CS lock
+ *
+ * @ctx: pointer to the context structure.
+ * @seq_arr: array of CS sequences to wait for
+ * @fence: fence array to store the CS fences
+ * @arr_len: length of seq_arr and fence_arr
+ *
+ * @return 0 on success, otherwise non 0 error code
+ */
+int hl_ctx_get_fences(struct hl_ctx *ctx, u64 *seq_arr,
+				struct hl_fence **fence, u32 arr_len)
+{
+	struct hl_fence **fence_arr_base = fence;
+	int i, rc = 0;
+
+	spin_lock(&ctx->cs_lock);
+
+	for (i = 0; i < arr_len; i++, fence++) {
+		u64 seq = seq_arr[i];
+
+		*fence = hl_ctx_get_fence_locked(ctx, seq);
+
+		if (IS_ERR(*fence)) {
+			dev_err(ctx->hdev->dev,
+				"Failed to get fence for CS with seq 0x%llx\n",
+					seq);
+			rc = PTR_ERR(*fence);
+			break;
+		}
+	}
+
+	spin_unlock(&ctx->cs_lock);
+
+	if (rc)
+		hl_fences_put(fence_arr_base, i);
+
+	return rc;
+}
+
+/*
+ * hl_ctx_mgr_init - initialize the context manager
+ *
+ * @ctx_mgr: pointer to context manager structure
+ *
+ * This manager is an object inside the hpriv object of the user process.
+ * The function is called when a user process opens the FD.
+ */
+void hl_ctx_mgr_init(struct hl_ctx_mgr *ctx_mgr)
+{
+	mutex_init(&ctx_mgr->lock);
+	idr_init(&ctx_mgr->handles);
+}
+
+/*
+ * hl_ctx_mgr_fini - finalize the context manager
+ *
+ * @hdev: pointer to device structure
+ * @ctx_mgr: pointer to context manager structure
+ *
+ * This function goes over all the contexts in the manager and frees them.
+ * It is called when a process closes the FD.
+ */
+void hl_ctx_mgr_fini(struct hl_device *hdev, struct hl_ctx_mgr *ctx_mgr)
+{
+	struct hl_ctx *ctx;
+	struct idr *idp;
+	u32 id;
+
+	idp = &ctx_mgr->handles;
+
+	idr_for_each_entry(idp, ctx, id)
+		kref_put(&ctx->refcount, hl_ctx_do_release);
+
+	idr_destroy(&ctx_mgr->handles);
+	mutex_destroy(&ctx_mgr->lock);
+}
diff --git a/drivers/accel/habanalabs/common/debugfs.c b/drivers/accel/habanalabs/common/debugfs.c
new file mode 100644
index 000000000000..5f0820b19ccb
--- /dev/null
+++ b/drivers/accel/habanalabs/common/debugfs.c
@@ -0,0 +1,2250 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Copyright 2016-2021 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ */
+
+#include "habanalabs.h"
+#include "hldio.h"
+#include "../include/hw_ip/mmu/mmu_general.h"
+
+#include <linux/pci.h>
+#include <linux/uaccess.h>
+#include <linux/vmalloc.h>
+#include <linux/iommu.h>
+
+#define MMU_ADDR_BUF_SIZE	40
+#define MMU_ASID_BUF_SIZE	10
+#define MMU_KBUF_SIZE		(MMU_ADDR_BUF_SIZE + MMU_ASID_BUF_SIZE)
+#define I2C_MAX_TRANSACTION_LEN	8
+
+static int hl_debugfs_i2c_read(struct hl_device *hdev, u8 i2c_bus, u8 i2c_addr,
+				u8 i2c_reg, u8 i2c_len, u64 *val)
+{
+	struct cpucp_packet pkt;
+	int rc;
+
+	if (!hl_device_operational(hdev, NULL))
+		return -EBUSY;
+
+	if (i2c_len > I2C_MAX_TRANSACTION_LEN) {
+		dev_err(hdev->dev, "I2C transaction length %u, exceeds maximum of %u\n",
+				i2c_len, I2C_MAX_TRANSACTION_LEN);
+		return -EINVAL;
+	}
+
+	memset(&pkt, 0, sizeof(pkt));
+
+	pkt.ctl = cpu_to_le32(CPUCP_PACKET_I2C_RD <<
+				CPUCP_PKT_CTL_OPCODE_SHIFT);
+	pkt.i2c_bus = i2c_bus;
+	pkt.i2c_addr = i2c_addr;
+	pkt.i2c_reg = i2c_reg;
+	pkt.i2c_len = i2c_len;
+
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), 0, val);
+	if (rc && rc != -EAGAIN)
+		dev_err(hdev->dev, "Failed to read from I2C, error %d\n", rc);
+
+	return rc;
+}
+
+static int hl_debugfs_i2c_write(struct hl_device *hdev, u8 i2c_bus, u8 i2c_addr,
+				u8 i2c_reg, u8 i2c_len, u64 val)
+{
+	struct cpucp_packet pkt;
+	int rc;
+
+	if (!hl_device_operational(hdev, NULL))
+		return -EBUSY;
+
+	if (i2c_len > I2C_MAX_TRANSACTION_LEN) {
+		dev_err(hdev->dev, "I2C transaction length %u, exceeds maximum of %u\n",
+				i2c_len, I2C_MAX_TRANSACTION_LEN);
+		return -EINVAL;
+	}
+
+	memset(&pkt, 0, sizeof(pkt));
+
+	pkt.ctl = cpu_to_le32(CPUCP_PACKET_I2C_WR <<
+				CPUCP_PKT_CTL_OPCODE_SHIFT);
+	pkt.i2c_bus = i2c_bus;
+	pkt.i2c_addr = i2c_addr;
+	pkt.i2c_reg = i2c_reg;
+	pkt.i2c_len = i2c_len;
+	pkt.value = cpu_to_le64(val);
+
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), 0, NULL);
+	if (rc && rc != -EAGAIN)
+		dev_err(hdev->dev, "Failed to write to I2C, error %d\n", rc);
+
+	return rc;
+}
+
+static void hl_debugfs_led_set(struct hl_device *hdev, u8 led, u8 state)
+{
+	struct cpucp_packet pkt;
+	int rc;
+
+	if (!hl_device_operational(hdev, NULL))
+		return;
+
+	memset(&pkt, 0, sizeof(pkt));
+
+	pkt.ctl = cpu_to_le32(CPUCP_PACKET_LED_SET <<
+				CPUCP_PKT_CTL_OPCODE_SHIFT);
+	pkt.led_index = cpu_to_le32(led);
+	pkt.value = cpu_to_le64(state);
+
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), 0, NULL);
+	if (rc && rc != -EAGAIN)
+		dev_err(hdev->dev, "Failed to set LED %d, error %d\n", led, rc);
+}
+
+static int command_buffers_show(struct seq_file *s, void *data)
+{
+	struct hl_debugfs_entry *entry = s->private;
+	struct hl_dbg_device_entry *dev_entry = entry->dev_entry;
+	struct hl_cb *cb;
+	bool first = true;
+
+	spin_lock(&dev_entry->cb_spinlock);
+
+	list_for_each_entry(cb, &dev_entry->cb_list, debugfs_list) {
+		if (first) {
+			first = false;
+			seq_puts(s, "\n");
+			seq_puts(s, " CB ID   CTX ID   CB size    CB RefCnt    mmap?   CS counter\n");
+			seq_puts(s, "---------------------------------------------------------------\n");
+		}
+		seq_printf(s,
+			"   %03llu        %d    0x%08x      %d          %d          %d\n",
+			cb->buf->handle, cb->ctx->asid, cb->size,
+			kref_read(&cb->buf->refcount),
+			atomic_read(&cb->buf->mmap), atomic_read(&cb->cs_cnt));
+	}
+
+	spin_unlock(&dev_entry->cb_spinlock);
+
+	if (!first)
+		seq_puts(s, "\n");
+
+	return 0;
+}
+
+static int command_submission_show(struct seq_file *s, void *data)
+{
+	struct hl_debugfs_entry *entry = s->private;
+	struct hl_dbg_device_entry *dev_entry = entry->dev_entry;
+	struct hl_cs *cs;
+	bool first = true;
+
+	spin_lock(&dev_entry->cs_spinlock);
+
+	list_for_each_entry(cs, &dev_entry->cs_list, debugfs_list) {
+		if (first) {
+			first = false;
+			seq_puts(s, "\n");
+			seq_puts(s, " CS ID   CS TYPE   CTX ASID   CS RefCnt   Submitted    Completed\n");
+			seq_puts(s, "----------------------------------------------------------------\n");
+		}
+		seq_printf(s,
+			"   %llu        %d          %d          %d           %d            %d\n",
+			cs->sequence, cs->type, cs->ctx->asid,
+			kref_read(&cs->refcount),
+			cs->submitted, cs->completed);
+	}
+
+	spin_unlock(&dev_entry->cs_spinlock);
+
+	if (!first)
+		seq_puts(s, "\n");
+
+	return 0;
+}
+
+static int command_submission_jobs_show(struct seq_file *s, void *data)
+{
+	struct hl_debugfs_entry *entry = s->private;
+	struct hl_dbg_device_entry *dev_entry = entry->dev_entry;
+	struct hl_cs_job *job;
+	bool first = true;
+
+	spin_lock(&dev_entry->cs_job_spinlock);
+
+	list_for_each_entry(job, &dev_entry->cs_job_list, debugfs_list) {
+		if (first) {
+			first = false;
+			seq_puts(s, "\n");
+			seq_puts(s, " JOB ID   CS ID    CS TYPE    CTX ASID   JOB RefCnt   H/W Queue\n");
+			seq_puts(s, "---------------------------------------------------------------\n");
+		}
+		if (job->cs)
+			seq_printf(s,
+				"   %02d      %llu        %d        %d          %d           %d\n",
+				job->id, job->cs->sequence, job->cs->type,
+				job->cs->ctx->asid, kref_read(&job->refcount),
+				job->hw_queue_id);
+		else
+			seq_printf(s,
+				"   %02d      0        0        %d          %d           %d\n",
+				job->id, HL_KERNEL_ASID_ID,
+				kref_read(&job->refcount), job->hw_queue_id);
+	}
+
+	spin_unlock(&dev_entry->cs_job_spinlock);
+
+	if (!first)
+		seq_puts(s, "\n");
+
+	return 0;
+}
+
+static int userptr_show(struct seq_file *s, void *data)
+{
+	struct hl_debugfs_entry *entry = s->private;
+	struct hl_dbg_device_entry *dev_entry = entry->dev_entry;
+	struct hl_userptr *userptr;
+	char dma_dir[4][30] = {"DMA_BIDIRECTIONAL", "DMA_TO_DEVICE",
+				"DMA_FROM_DEVICE", "DMA_NONE"};
+	bool first = true;
+
+	spin_lock(&dev_entry->userptr_spinlock);
+
+	list_for_each_entry(userptr, &dev_entry->userptr_list, debugfs_list) {
+		if (first) {
+			first = false;
+			seq_puts(s, "\n");
+			seq_puts(s, " pid      user virtual address     size             dma dir\n");
+			seq_puts(s, "----------------------------------------------------------\n");
+		}
+		seq_printf(s, " %-7d  0x%-14llx      %-10llu    %-30s\n",
+				userptr->pid, userptr->addr, userptr->size,
+				dma_dir[userptr->dir]);
+	}
+
+	spin_unlock(&dev_entry->userptr_spinlock);
+
+	if (!first)
+		seq_puts(s, "\n");
+
+	return 0;
+}
+
+static int vm_show(struct seq_file *s, void *data)
+{
+	struct hl_debugfs_entry *entry = s->private;
+	struct hl_dbg_device_entry *dev_entry = entry->dev_entry;
+	struct hl_vm_hw_block_list_node *lnode;
+	struct hl_ctx *ctx;
+	struct hl_vm *vm;
+	struct hl_vm_hash_node *hnode;
+	struct hl_userptr *userptr;
+	struct hl_vm_phys_pg_pack *phys_pg_pack = NULL;
+	struct hl_va_range *va_range;
+	struct hl_vm_va_block *va_block;
+	enum vm_type *vm_type;
+	bool once = true;
+	u64 j;
+	int i;
+
+	mutex_lock(&dev_entry->ctx_mem_hash_mutex);
+
+	list_for_each_entry(ctx, &dev_entry->ctx_mem_hash_list, debugfs_list) {
+		once = false;
+		seq_puts(s, "\n\n----------------------------------------------------");
+		seq_puts(s, "\n----------------------------------------------------\n\n");
+		seq_printf(s, "ctx asid: %u\n", ctx->asid);
+
+		seq_puts(s, "\nmappings:\n\n");
+		seq_puts(s, "    virtual address        size          handle\n");
+		seq_puts(s, "----------------------------------------------------\n");
+		mutex_lock(&ctx->mem_hash_lock);
+		hash_for_each(ctx->mem_hash, i, hnode, node) {
+			vm_type = hnode->ptr;
+
+			if (*vm_type == VM_TYPE_USERPTR) {
+				userptr = hnode->ptr;
+				seq_printf(s,
+					"    0x%-14llx      %-10llu\n",
+					hnode->vaddr, userptr->size);
+			} else {
+				phys_pg_pack = hnode->ptr;
+				seq_printf(s,
+					"    0x%-14llx      %-10llu       %-4u\n",
+					hnode->vaddr, phys_pg_pack->total_size,
+					phys_pg_pack->handle);
+			}
+		}
+		mutex_unlock(&ctx->mem_hash_lock);
+
+		if (ctx->asid != HL_KERNEL_ASID_ID &&
+		    !list_empty(&ctx->hw_block_mem_list)) {
+			seq_puts(s, "\nhw_block mappings:\n\n");
+			seq_puts(s,
+				"    virtual address    block size    mapped size    HW block id\n");
+			seq_puts(s,
+				"---------------------------------------------------------------\n");
+			mutex_lock(&ctx->hw_block_list_lock);
+			list_for_each_entry(lnode, &ctx->hw_block_mem_list, node) {
+				seq_printf(s,
+					"    0x%-14lx   %-6u        %-6u             %-9u\n",
+					lnode->vaddr, lnode->block_size, lnode->mapped_size,
+					lnode->id);
+			}
+			mutex_unlock(&ctx->hw_block_list_lock);
+		}
+
+		vm = &ctx->hdev->vm;
+		spin_lock(&vm->idr_lock);
+
+		if (!idr_is_empty(&vm->phys_pg_pack_handles))
+			seq_puts(s, "\n\nallocations:\n");
+
+		idr_for_each_entry(&vm->phys_pg_pack_handles, phys_pg_pack, i) {
+			if (phys_pg_pack->asid != ctx->asid)
+				continue;
+
+			seq_printf(s, "\nhandle: %u\n", phys_pg_pack->handle);
+			seq_printf(s, "page size: %u\n\n",
+						phys_pg_pack->page_size);
+			seq_puts(s, "   physical address\n");
+			seq_puts(s, "---------------------\n");
+			for (j = 0 ; j < phys_pg_pack->npages ; j++) {
+				seq_printf(s, "    0x%-14llx\n",
+						phys_pg_pack->pages[j]);
+			}
+		}
+		spin_unlock(&vm->idr_lock);
+
+	}
+
+	mutex_unlock(&dev_entry->ctx_mem_hash_mutex);
+
+	ctx = hl_get_compute_ctx(dev_entry->hdev);
+	if (ctx) {
+		seq_puts(s, "\nVA ranges:\n\n");
+		for (i = HL_VA_RANGE_TYPE_HOST ; i < HL_VA_RANGE_TYPE_MAX ; ++i) {
+			va_range = ctx->va_range[i];
+			seq_printf(s, "   va_range %d\n", i);
+			seq_puts(s, "---------------------\n");
+			mutex_lock(&va_range->lock);
+			list_for_each_entry(va_block, &va_range->list, node) {
+				seq_printf(s, "%#16llx - %#16llx (%#llx)\n",
+					   va_block->start, va_block->end,
+					   va_block->size);
+			}
+			mutex_unlock(&va_range->lock);
+			seq_puts(s, "\n");
+		}
+		hl_ctx_put(ctx);
+	}
+
+	if (!once)
+		seq_puts(s, "\n");
+
+	return 0;
+}
+
+static int userptr_lookup_show(struct seq_file *s, void *data)
+{
+	struct hl_debugfs_entry *entry = s->private;
+	struct hl_dbg_device_entry *dev_entry = entry->dev_entry;
+	struct scatterlist *sg;
+	struct hl_userptr *userptr;
+	bool first = true;
+	u64 total_npages, npages, sg_start, sg_end;
+	dma_addr_t dma_addr;
+	int i;
+
+	spin_lock(&dev_entry->userptr_spinlock);
+
+	list_for_each_entry(userptr, &dev_entry->userptr_list, debugfs_list) {
+		if (dev_entry->userptr_lookup >= userptr->addr &&
+		dev_entry->userptr_lookup < userptr->addr + userptr->size) {
+			total_npages = 0;
+			for_each_sgtable_dma_sg(userptr->sgt, sg, i) {
+				npages = hl_get_sg_info(sg, &dma_addr);
+				sg_start = userptr->addr +
+					total_npages * PAGE_SIZE;
+				sg_end = userptr->addr +
+					(total_npages + npages) * PAGE_SIZE;
+
+				if (dev_entry->userptr_lookup >= sg_start &&
+				    dev_entry->userptr_lookup < sg_end) {
+					dma_addr += (dev_entry->userptr_lookup -
+							sg_start);
+					if (first) {
+						first = false;
+						seq_puts(s, "\n");
+						seq_puts(s, " user virtual address         dma address       pid        region start     region size\n");
+						seq_puts(s, "---------------------------------------------------------------------------------------\n");
+					}
+					seq_printf(s, " 0x%-18llx  0x%-16llx  %-8u  0x%-16llx %-12llu\n",
+						dev_entry->userptr_lookup,
+						(u64)dma_addr, userptr->pid,
+						userptr->addr, userptr->size);
+				}
+				total_npages += npages;
+			}
+		}
+	}
+
+	spin_unlock(&dev_entry->userptr_spinlock);
+
+	if (!first)
+		seq_puts(s, "\n");
+
+	return 0;
+}
+
+static ssize_t userptr_lookup_write(struct file *file, const char __user *buf,
+		size_t count, loff_t *f_pos)
+{
+	struct seq_file *s = file->private_data;
+	struct hl_debugfs_entry *entry = s->private;
+	struct hl_dbg_device_entry *dev_entry = entry->dev_entry;
+	ssize_t rc;
+	u64 value;
+
+	rc = kstrtoull_from_user(buf, count, 16, &value);
+	if (rc)
+		return rc;
+
+	dev_entry->userptr_lookup = value;
+
+	return count;
+}
+
+static int mmu_show(struct seq_file *s, void *data)
+{
+	struct hl_debugfs_entry *entry = s->private;
+	struct hl_dbg_device_entry *dev_entry = entry->dev_entry;
+	struct hl_device *hdev = dev_entry->hdev;
+	struct hl_ctx *ctx;
+	struct hl_mmu_hop_info hops_info = {0};
+	u64 virt_addr = dev_entry->mmu_addr, phys_addr;
+	int i;
+
+	if (dev_entry->mmu_asid == HL_KERNEL_ASID_ID)
+		ctx = hdev->kernel_ctx;
+	else
+		ctx = hl_get_compute_ctx(hdev);
+
+	if (!ctx) {
+		dev_err(hdev->dev, "no ctx available\n");
+		return 0;
+	}
+
+	if (hl_mmu_get_tlb_info(ctx, virt_addr, &hops_info)) {
+		dev_err(hdev->dev, "virt addr 0x%llx is not mapped to phys addr\n",
+				virt_addr);
+		goto put_ctx;
+	}
+
+	hl_mmu_va_to_pa(ctx, virt_addr, &phys_addr);
+
+	if (hops_info.scrambled_vaddr &&
+		(dev_entry->mmu_addr != hops_info.scrambled_vaddr))
+		seq_printf(s,
+			"asid: %u, virt_addr: 0x%llx, scrambled virt_addr: 0x%llx,\nphys_addr: 0x%llx, scrambled_phys_addr: 0x%llx\n",
+			dev_entry->mmu_asid, dev_entry->mmu_addr,
+			hops_info.scrambled_vaddr,
+			hops_info.unscrambled_paddr, phys_addr);
+	else
+		seq_printf(s,
+			"asid: %u, virt_addr: 0x%llx, phys_addr: 0x%llx\n",
+			dev_entry->mmu_asid, dev_entry->mmu_addr, phys_addr);
+
+	for (i = 0 ; i < hops_info.used_hops ; i++) {
+		seq_printf(s, "hop%d_addr: 0x%llx\n",
+				i, hops_info.hop_info[i].hop_addr);
+		seq_printf(s, "hop%d_pte_addr: 0x%llx\n",
+				i, hops_info.hop_info[i].hop_pte_addr);
+		seq_printf(s, "hop%d_pte: 0x%llx\n",
+				i, hops_info.hop_info[i].hop_pte_val);
+	}
+
+put_ctx:
+	if (dev_entry->mmu_asid != HL_KERNEL_ASID_ID)
+		hl_ctx_put(ctx);
+
+	return 0;
+}
+
+static ssize_t mmu_asid_va_write(struct file *file, const char __user *buf,
+		size_t count, loff_t *f_pos)
+{
+	struct seq_file *s = file->private_data;
+	struct hl_debugfs_entry *entry = s->private;
+	struct hl_dbg_device_entry *dev_entry = entry->dev_entry;
+	struct hl_device *hdev = dev_entry->hdev;
+	char kbuf[MMU_KBUF_SIZE] = {0};
+	char *c;
+	ssize_t rc;
+
+	if (count > sizeof(kbuf) - 1)
+		goto err;
+	if (copy_from_user(kbuf, buf, count))
+		goto err;
+	kbuf[count] = 0;
+
+	c = strchr(kbuf, ' ');
+	if (!c)
+		goto err;
+	*c = '\0';
+
+	rc = kstrtouint(kbuf, 10, &dev_entry->mmu_asid);
+	if (rc)
+		goto err;
+
+	if (strncmp(c+1, "0x", 2))
+		goto err;
+	rc = kstrtoull(c+3, 16, &dev_entry->mmu_addr);
+	if (rc)
+		goto err;
+
+	return count;
+
+err:
+	dev_err(hdev->dev, "usage: echo <asid> <0xaddr> > mmu\n");
+
+	return -EINVAL;
+}
+
+static int mmu_ack_error(struct seq_file *s, void *data)
+{
+	struct hl_debugfs_entry *entry = s->private;
+	struct hl_dbg_device_entry *dev_entry = entry->dev_entry;
+	struct hl_device *hdev = dev_entry->hdev;
+	int rc;
+
+	if (!dev_entry->mmu_cap_mask) {
+		dev_err(hdev->dev, "mmu_cap_mask is not set\n");
+		goto err;
+	}
+
+	rc = hdev->asic_funcs->ack_mmu_errors(hdev, dev_entry->mmu_cap_mask);
+	if (rc)
+		goto err;
+
+	return 0;
+err:
+	return -EINVAL;
+}
+
+static ssize_t mmu_ack_error_value_write(struct file *file,
+		const char __user *buf,
+		size_t count, loff_t *f_pos)
+{
+	struct seq_file *s = file->private_data;
+	struct hl_debugfs_entry *entry = s->private;
+	struct hl_dbg_device_entry *dev_entry = entry->dev_entry;
+	struct hl_device *hdev = dev_entry->hdev;
+	char kbuf[MMU_KBUF_SIZE] = {0};
+	ssize_t rc;
+
+	if (count > sizeof(kbuf) - 1)
+		goto err;
+
+	if (copy_from_user(kbuf, buf, count))
+		goto err;
+
+	kbuf[count] = 0;
+
+	if (strncmp(kbuf, "0x", 2))
+		goto err;
+
+	rc = kstrtoull(kbuf, 16, &dev_entry->mmu_cap_mask);
+	if (rc)
+		goto err;
+
+	return count;
+err:
+	dev_err(hdev->dev, "usage: echo <0xmmu_cap_mask > > mmu_error\n");
+
+	return -EINVAL;
+}
+
+static int engines_show(struct seq_file *s, void *data)
+{
+	struct hl_debugfs_entry *entry = s->private;
+	struct hl_dbg_device_entry *dev_entry = entry->dev_entry;
+	struct hl_device *hdev = dev_entry->hdev;
+	struct engines_data eng_data;
+
+	if (hdev->reset_info.in_reset) {
+		dev_warn_ratelimited(hdev->dev,
+				"Can't check device idle during reset\n");
+		return 0;
+	}
+
+	eng_data.actual_size = 0;
+	eng_data.allocated_buf_size = HL_ENGINES_DATA_MAX_SIZE;
+	eng_data.buf = vmalloc(eng_data.allocated_buf_size);
+	if (!eng_data.buf)
+		return -ENOMEM;
+
+	hdev->asic_funcs->is_device_idle(hdev, NULL, 0, &eng_data);
+
+	if (eng_data.actual_size > eng_data.allocated_buf_size) {
+		dev_err(hdev->dev,
+				"Engines data size (%d Bytes) is bigger than allocated size (%u Bytes)\n",
+				eng_data.actual_size, eng_data.allocated_buf_size);
+		vfree(eng_data.buf);
+		return -ENOMEM;
+	}
+
+	seq_write(s, eng_data.buf, eng_data.actual_size);
+
+	vfree(eng_data.buf);
+
+	return 0;
+}
+
+#ifdef CONFIG_HL_HLDIO
+/* DIO debugfs functions following the standard pattern */
+static int dio_ssd2hl_show(struct seq_file *s, void *data)
+{
+	struct hl_debugfs_entry *entry = s->private;
+	struct hl_dbg_device_entry *dev_entry = entry->dev_entry;
+	struct hl_device *hdev = dev_entry->hdev;
+
+	if (!hdev->asic_prop.supports_nvme) {
+		seq_puts(s, "NVMe Direct I/O not supported\\n");
+		return 0;
+	}
+
+	seq_puts(s, "Usage: echo \"fd=N va=0xADDR off=N len=N\" > dio_ssd2hl\n");
+	seq_printf(s, "Last transfer: %zu bytes\\n", dev_entry->dio_stats.last_len_read);
+	seq_puts(s, "Note: All parameters must be page-aligned (4KB)\\n");
+
+	return 0;
+}
+
+static ssize_t dio_ssd2hl_write(struct file *file, const char __user *buf,
+				size_t count, loff_t *f_pos)
+{
+	struct seq_file *s = file->private_data;
+	struct hl_debugfs_entry *entry = s->private;
+	struct hl_dbg_device_entry *dev_entry = entry->dev_entry;
+	struct hl_device *hdev = dev_entry->hdev;
+	struct hl_ctx *ctx = hdev->kernel_ctx;
+	char kbuf[128];
+	u64 device_va = 0, off_bytes = 0, len_bytes = 0;
+	u32 fd = 0;
+	size_t len_read = 0;
+	int rc, parsed;
+
+	if (!hdev->asic_prop.supports_nvme)
+		return -EOPNOTSUPP;
+
+	if (count >= sizeof(kbuf))
+		return -EINVAL;
+
+	if (copy_from_user(kbuf, buf, count))
+		return -EFAULT;
+
+	kbuf[count] = 0;
+
+	/* Parse: fd=N va=0xADDR off=N len=N */
+	parsed = sscanf(kbuf, "fd=%u va=0x%llx off=%llu len=%llu",
+			&fd, &device_va, &off_bytes, &len_bytes);
+	if (parsed != 4) {
+		dev_err(hdev->dev, "Invalid format. Expected: fd=N va=0xADDR off=N len=N\\n");
+		return -EINVAL;
+	}
+
+	/* Validate file descriptor */
+	if (fd == 0) {
+		dev_err(hdev->dev, "Invalid file descriptor: %u\\n", fd);
+		return -EINVAL;
+	}
+
+	/* Validate alignment requirements */
+	if (!IS_ALIGNED(device_va, PAGE_SIZE) ||
+	    !IS_ALIGNED(off_bytes, PAGE_SIZE) ||
+	    !IS_ALIGNED(len_bytes, PAGE_SIZE)) {
+		dev_err(hdev->dev,
+			"All parameters must be page-aligned (4KB)\\n");
+		return -EINVAL;
+	}
+
+	/* Validate transfer size */
+	if (len_bytes == 0 || len_bytes > SZ_1G) {
+		dev_err(hdev->dev, "Invalid length: %llu (max 1GB)\\n",
+			len_bytes);
+		return -EINVAL;
+	}
+
+	dev_dbg(hdev->dev, "DIO SSD2HL: fd=%u va=0x%llx off=%llu len=%llu\\n",
+		fd, device_va, off_bytes, len_bytes);
+
+	rc = hl_dio_ssd2hl(hdev, ctx, fd, device_va, off_bytes, len_bytes, &len_read);
+	if (rc < 0) {
+		dev_entry->dio_stats.failed_ops++;
+		dev_err(hdev->dev, "SSD2HL operation failed: %d\\n", rc);
+		return rc;
+	}
+
+	/* Update statistics */
+	dev_entry->dio_stats.total_ops++;
+	dev_entry->dio_stats.successful_ops++;
+	dev_entry->dio_stats.bytes_transferred += len_read;
+	dev_entry->dio_stats.last_len_read = len_read;
+
+	dev_dbg(hdev->dev, "DIO SSD2HL completed: %zu bytes transferred\\n", len_read);
+
+	return count;
+}
+
+static int dio_hl2ssd_show(struct seq_file *s, void *data)
+{
+	seq_puts(s, "HL2SSD (device-to-SSD) transfers not implemented\\n");
+	return 0;
+}
+
+static ssize_t dio_hl2ssd_write(struct file *file, const char __user *buf,
+			       size_t count, loff_t *f_pos)
+{
+	struct seq_file *s = file->private_data;
+	struct hl_debugfs_entry *entry = s->private;
+	struct hl_dbg_device_entry *dev_entry = entry->dev_entry;
+	struct hl_device *hdev = dev_entry->hdev;
+
+	if (!hdev->asic_prop.supports_nvme)
+		return -EOPNOTSUPP;
+
+	dev_dbg(hdev->dev, "HL2SSD operation not implemented\\n");
+	return -EOPNOTSUPP;
+}
+
+static int dio_stats_show(struct seq_file *s, void *data)
+{
+	struct hl_debugfs_entry *entry = s->private;
+	struct hl_dbg_device_entry *dev_entry = entry->dev_entry;
+	struct hl_device *hdev = dev_entry->hdev;
+	struct hl_dio_stats *stats = &dev_entry->dio_stats;
+	u64 avg_bytes_per_op = 0, success_rate = 0;
+
+	if (!hdev->asic_prop.supports_nvme) {
+		seq_puts(s, "NVMe Direct I/O not supported\\n");
+		return 0;
+	}
+
+	if (stats->successful_ops > 0)
+		avg_bytes_per_op = stats->bytes_transferred / stats->successful_ops;
+
+	if (stats->total_ops > 0)
+		success_rate = (stats->successful_ops * 100) / stats->total_ops;
+
+	seq_puts(s, "=== Habanalabs Direct I/O Statistics ===\\n");
+	seq_printf(s, "Total operations:     %llu\\n", stats->total_ops);
+	seq_printf(s, "Successful ops:       %llu\\n", stats->successful_ops);
+	seq_printf(s, "Failed ops:           %llu\\n", stats->failed_ops);
+	seq_printf(s, "Success rate:         %llu%%\\n", success_rate);
+	seq_printf(s, "Total bytes:          %llu\\n", stats->bytes_transferred);
+	seq_printf(s, "Avg bytes per op:     %llu\\n", avg_bytes_per_op);
+	seq_printf(s, "Last transfer:        %zu bytes\\n", stats->last_len_read);
+
+	return 0;
+}
+
+static int dio_reset_show(struct seq_file *s, void *data)
+{
+	seq_puts(s, "Write '1' to reset DIO statistics\\n");
+	return 0;
+}
+
+static ssize_t dio_reset_write(struct file *file, const char __user *buf,
+			       size_t count, loff_t *f_pos)
+{
+	struct seq_file *s = file->private_data;
+	struct hl_debugfs_entry *entry = s->private;
+	struct hl_dbg_device_entry *dev_entry = entry->dev_entry;
+	struct hl_device *hdev = dev_entry->hdev;
+	char kbuf[8];
+	unsigned long val;
+	int rc;
+
+	if (!hdev->asic_prop.supports_nvme)
+		return -EOPNOTSUPP;
+
+	if (count >= sizeof(kbuf))
+		return -EINVAL;
+
+	if (copy_from_user(kbuf, buf, count))
+		return -EFAULT;
+
+	kbuf[count] = 0;
+
+	rc = kstrtoul(kbuf, 0, &val);
+	if (rc)
+		return rc;
+
+	if (val == 1) {
+		memset(&dev_entry->dio_stats, 0, sizeof(dev_entry->dio_stats));
+		dev_dbg(hdev->dev, "DIO statistics reset\\n");
+	} else {
+		dev_err(hdev->dev, "Write '1' to reset statistics\\n");
+		return -EINVAL;
+	}
+
+	return count;
+}
+#endif
+
+static ssize_t hl_memory_scrub(struct file *f, const char __user *buf,
+					size_t count, loff_t *ppos)
+{
+	struct hl_dbg_device_entry *entry = file_inode(f)->i_private;
+	struct hl_device *hdev = entry->hdev;
+	u64 val = hdev->memory_scrub_val;
+	int rc;
+
+	if (!hl_device_operational(hdev, NULL)) {
+		dev_warn_ratelimited(hdev->dev, "Can't scrub memory, device is not operational\n");
+		return -EIO;
+	}
+
+	mutex_lock(&hdev->fpriv_list_lock);
+	if (hdev->is_compute_ctx_active) {
+		mutex_unlock(&hdev->fpriv_list_lock);
+		dev_err(hdev->dev, "can't scrub dram, context exist\n");
+		return -EBUSY;
+	}
+	hdev->is_in_dram_scrub = true;
+	mutex_unlock(&hdev->fpriv_list_lock);
+
+	rc = hdev->asic_funcs->scrub_device_dram(hdev, val);
+
+	mutex_lock(&hdev->fpriv_list_lock);
+	hdev->is_in_dram_scrub = false;
+	mutex_unlock(&hdev->fpriv_list_lock);
+
+	if (rc)
+		return rc;
+	return count;
+}
+
+static bool hl_is_device_va(struct hl_device *hdev, u64 addr)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+
+	if (prop->dram_supports_virtual_memory &&
+		(addr >= prop->dmmu.start_addr && addr < prop->dmmu.end_addr))
+		return true;
+
+	if (addr >= prop->pmmu.start_addr &&
+		addr < prop->pmmu.end_addr)
+		return true;
+
+	if (addr >= prop->pmmu_huge.start_addr &&
+		addr < prop->pmmu_huge.end_addr)
+		return true;
+
+	return false;
+}
+
+static bool hl_is_device_internal_memory_va(struct hl_device *hdev, u64 addr,
+						u32 size)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	u64 dram_start_addr, dram_end_addr;
+
+	if (prop->dram_supports_virtual_memory) {
+		dram_start_addr = prop->dmmu.start_addr;
+		dram_end_addr = prop->dmmu.end_addr;
+	} else {
+		dram_start_addr = prop->dram_base_address;
+		dram_end_addr = prop->dram_end_address;
+	}
+
+	if (hl_mem_area_inside_range(addr, size, dram_start_addr,
+					dram_end_addr))
+		return true;
+
+	if (hl_mem_area_inside_range(addr, size, prop->sram_base_address,
+					prop->sram_end_address))
+		return true;
+
+	return false;
+}
+
+static int device_va_to_pa(struct hl_device *hdev, u64 virt_addr, u32 size,
+			u64 *phys_addr)
+{
+	struct hl_vm_phys_pg_pack *phys_pg_pack;
+	struct hl_ctx *ctx;
+	struct hl_vm_hash_node *hnode;
+	u64 end_address, range_size;
+	struct hl_userptr *userptr;
+	enum vm_type *vm_type;
+	bool valid = false;
+	int i, rc = 0;
+
+	ctx = hl_get_compute_ctx(hdev);
+
+	if (!ctx) {
+		dev_err(hdev->dev, "no ctx available\n");
+		return -EINVAL;
+	}
+
+	/* Verify address is mapped */
+	mutex_lock(&ctx->mem_hash_lock);
+	hash_for_each(ctx->mem_hash, i, hnode, node) {
+		vm_type = hnode->ptr;
+
+		if (*vm_type == VM_TYPE_USERPTR) {
+			userptr = hnode->ptr;
+			range_size = userptr->size;
+		} else {
+			phys_pg_pack = hnode->ptr;
+			range_size = phys_pg_pack->total_size;
+		}
+
+		end_address = virt_addr + size;
+		if ((virt_addr >= hnode->vaddr) &&
+				(end_address <= hnode->vaddr + range_size)) {
+			valid = true;
+			break;
+		}
+	}
+	mutex_unlock(&ctx->mem_hash_lock);
+
+	if (!valid) {
+		dev_err(hdev->dev,
+			"virt addr 0x%llx is not mapped\n",
+			virt_addr);
+		rc = -EINVAL;
+		goto put_ctx;
+	}
+
+	rc = hl_mmu_va_to_pa(ctx, virt_addr, phys_addr);
+	if (rc) {
+		dev_err(hdev->dev,
+			"virt addr 0x%llx is not mapped to phys addr\n",
+			virt_addr);
+		rc = -EINVAL;
+	}
+
+put_ctx:
+	hl_ctx_put(ctx);
+
+	return rc;
+}
+
+static int hl_access_dev_mem_by_region(struct hl_device *hdev, u64 addr,
+		u64 *val, enum debugfs_access_type acc_type, bool *found)
+{
+	size_t acc_size = (acc_type == DEBUGFS_READ64 || acc_type == DEBUGFS_WRITE64) ?
+		sizeof(u64) : sizeof(u32);
+	struct pci_mem_region *mem_reg;
+	int i;
+
+	for (i = 0; i < PCI_REGION_NUMBER; i++) {
+		mem_reg = &hdev->pci_mem_region[i];
+		if (!mem_reg->used)
+			continue;
+		if (addr >= mem_reg->region_base &&
+			addr <= mem_reg->region_base + mem_reg->region_size - acc_size) {
+			*found = true;
+			return hdev->asic_funcs->access_dev_mem(hdev, i, addr, val, acc_type);
+		}
+	}
+	return 0;
+}
+
+static void hl_access_host_mem(struct hl_device *hdev, u64 addr, u64 *val,
+		enum debugfs_access_type acc_type)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	u64 offset = prop->device_dma_offset_for_host_access;
+
+	switch (acc_type) {
+	case DEBUGFS_READ32:
+		*val = *(u32 *) phys_to_virt(addr - offset);
+		break;
+	case DEBUGFS_WRITE32:
+		*(u32 *) phys_to_virt(addr - offset) = *val;
+		break;
+	case DEBUGFS_READ64:
+		*val = *(u64 *) phys_to_virt(addr - offset);
+		break;
+	case DEBUGFS_WRITE64:
+		*(u64 *) phys_to_virt(addr - offset) = *val;
+		break;
+	default:
+		dev_err(hdev->dev, "hostmem access-type %d id not supported\n", acc_type);
+		break;
+	}
+}
+
+static void dump_cfg_access_entry(struct hl_device *hdev,
+				  struct hl_debugfs_cfg_access_entry *entry)
+{
+	char *access_type = "";
+	struct tm tm;
+
+	switch (entry->debugfs_type) {
+	case DEBUGFS_READ32:
+		access_type = "READ32 from";
+		break;
+	case DEBUGFS_WRITE32:
+		access_type = "WRITE32 to";
+		break;
+	case DEBUGFS_READ64:
+		access_type = "READ64 from";
+		break;
+	case DEBUGFS_WRITE64:
+		access_type = "WRITE64 to";
+		break;
+	default:
+		dev_err(hdev->dev, "Invalid DEBUGFS access type (%u)\n", entry->debugfs_type);
+		return;
+	}
+
+	time64_to_tm(entry->seconds_since_epoch, 0, &tm);
+	dev_info(hdev->dev,
+		"%ld-%02d-%02d %02d:%02d:%02d (UTC): %s %#llx\n", tm.tm_year + 1900, tm.tm_mon + 1,
+		tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec, access_type, entry->addr);
+}
+
+void hl_debugfs_cfg_access_history_dump(struct hl_device *hdev)
+{
+	struct hl_debugfs_cfg_access *dbgfs = &hdev->debugfs_cfg_accesses;
+	u32 i, head, count = 0;
+	time64_t entry_time, now;
+	unsigned long flags;
+
+	now = ktime_get_real_seconds();
+
+	spin_lock_irqsave(&dbgfs->lock, flags);
+	head = dbgfs->head;
+	if (head == 0)
+		i = HL_DBGFS_CFG_ACCESS_HIST_LEN - 1;
+	else
+		i = head - 1;
+
+	/* Walk back until timeout or invalid entry */
+	while (dbgfs->cfg_access_list[i].valid) {
+		entry_time = dbgfs->cfg_access_list[i].seconds_since_epoch;
+		/* Stop when entry is older than timeout */
+		if (now - entry_time > HL_DBGFS_CFG_ACCESS_HIST_TIMEOUT_SEC)
+			break;
+
+		/* print single entry under lock */
+		{
+			struct hl_debugfs_cfg_access_entry entry = dbgfs->cfg_access_list[i];
+			/*
+			 * We copy the entry out under lock and then print after
+			 * releasing the lock to minimize time under lock.
+			 */
+			spin_unlock_irqrestore(&dbgfs->lock, flags);
+			dump_cfg_access_entry(hdev, &entry);
+			spin_lock_irqsave(&dbgfs->lock, flags);
+		}
+
+		/* mark consumed */
+		dbgfs->cfg_access_list[i].valid = false;
+
+		if (i == 0)
+			i = HL_DBGFS_CFG_ACCESS_HIST_LEN - 1;
+		else
+			i--;
+		count++;
+		if (count >= HL_DBGFS_CFG_ACCESS_HIST_LEN)
+			break;
+	}
+	spin_unlock_irqrestore(&dbgfs->lock, flags);
+}
+
+static void check_if_cfg_access_and_log(struct hl_device *hdev, u64 addr, size_t access_size,
+					enum debugfs_access_type access_type)
+{
+	struct hl_debugfs_cfg_access *dbgfs_cfg_accesses = &hdev->debugfs_cfg_accesses;
+	struct pci_mem_region *mem_reg = &hdev->pci_mem_region[PCI_REGION_CFG];
+	struct hl_debugfs_cfg_access_entry *new_entry;
+	unsigned long flags;
+
+	/* Check if address is in config memory */
+	if (addr >= mem_reg->region_base &&
+		mem_reg->region_size >= access_size &&
+		addr <= mem_reg->region_base + mem_reg->region_size - access_size) {
+
+		spin_lock_irqsave(&dbgfs_cfg_accesses->lock, flags);
+
+		new_entry = &dbgfs_cfg_accesses->cfg_access_list[dbgfs_cfg_accesses->head];
+		new_entry->seconds_since_epoch = ktime_get_real_seconds();
+		new_entry->addr = addr;
+		new_entry->debugfs_type = access_type;
+		new_entry->valid = true;
+		dbgfs_cfg_accesses->head = (dbgfs_cfg_accesses->head + 1)
+						% HL_DBGFS_CFG_ACCESS_HIST_LEN;
+
+		spin_unlock_irqrestore(&dbgfs_cfg_accesses->lock, flags);
+
+	}
+}
+
+static int hl_access_mem(struct hl_device *hdev, u64 addr, u64 *val,
+				enum debugfs_access_type acc_type)
+{
+	size_t acc_size = (acc_type == DEBUGFS_READ64 || acc_type == DEBUGFS_WRITE64) ?
+		sizeof(u64) : sizeof(u32);
+	u64 host_start = hdev->asic_prop.host_base_address;
+	u64 host_end = hdev->asic_prop.host_end_address;
+	bool user_address, found = false;
+	int rc;
+
+	user_address = hl_is_device_va(hdev, addr);
+	if (user_address) {
+		rc = device_va_to_pa(hdev, addr, acc_size, &addr);
+		if (rc)
+			return rc;
+	}
+
+	check_if_cfg_access_and_log(hdev, addr, acc_size, acc_type);
+	rc = hl_access_dev_mem_by_region(hdev, addr, val, acc_type, &found);
+	if (rc) {
+		dev_err(hdev->dev,
+			"Failed reading addr %#llx from dev mem (%d)\n",
+			addr, rc);
+		return rc;
+	}
+
+	if (found)
+		return 0;
+
+	if (!user_address || device_iommu_mapped(&hdev->pdev->dev)) {
+		rc = -EINVAL;
+		goto err;
+	}
+
+	if (addr >= host_start && addr <= host_end - acc_size) {
+		hl_access_host_mem(hdev, addr, val, acc_type);
+	} else {
+		rc = -EINVAL;
+		goto err;
+	}
+
+	return 0;
+err:
+	dev_err(hdev->dev, "invalid addr %#llx\n", addr);
+	return rc;
+}
+
+static ssize_t hl_data_read32(struct file *f, char __user *buf,
+					size_t count, loff_t *ppos)
+{
+	struct hl_dbg_device_entry *entry = file_inode(f)->i_private;
+	struct hl_device *hdev = entry->hdev;
+	u64 value64, addr = entry->addr;
+	char tmp_buf[32];
+	ssize_t rc;
+	u32 val;
+
+	if (hdev->reset_info.in_reset) {
+		dev_warn_ratelimited(hdev->dev, "Can't read during reset\n");
+		return 0;
+	}
+
+	if (*ppos)
+		return 0;
+
+	rc = hl_access_mem(hdev, addr, &value64, DEBUGFS_READ32);
+	if (rc)
+		return rc;
+
+	val = value64; /* downcast back to 32 */
+
+	sprintf(tmp_buf, "0x%08x\n", val);
+	return simple_read_from_buffer(buf, count, ppos, tmp_buf,
+			strlen(tmp_buf));
+}
+
+static ssize_t hl_data_write32(struct file *f, const char __user *buf,
+					size_t count, loff_t *ppos)
+{
+	struct hl_dbg_device_entry *entry = file_inode(f)->i_private;
+	struct hl_device *hdev = entry->hdev;
+	u64 value64, addr = entry->addr;
+	u32 value;
+	ssize_t rc;
+
+	if (hdev->reset_info.in_reset) {
+		dev_warn_ratelimited(hdev->dev, "Can't write during reset\n");
+		return 0;
+	}
+
+	rc = kstrtouint_from_user(buf, count, 16, &value);
+	if (rc)
+		return rc;
+
+	value64 = value;
+	rc = hl_access_mem(hdev, addr, &value64, DEBUGFS_WRITE32);
+	if (rc)
+		return rc;
+
+	return count;
+}
+
+static ssize_t hl_data_read64(struct file *f, char __user *buf,
+					size_t count, loff_t *ppos)
+{
+	struct hl_dbg_device_entry *entry = file_inode(f)->i_private;
+	struct hl_device *hdev = entry->hdev;
+	u64 addr = entry->addr;
+	char tmp_buf[32];
+	ssize_t rc;
+	u64 val;
+
+	if (hdev->reset_info.in_reset) {
+		dev_warn_ratelimited(hdev->dev, "Can't read during reset\n");
+		return 0;
+	}
+
+	if (*ppos)
+		return 0;
+
+	rc = hl_access_mem(hdev, addr, &val, DEBUGFS_READ64);
+	if (rc)
+		return rc;
+
+	sprintf(tmp_buf, "0x%016llx\n", val);
+	return simple_read_from_buffer(buf, count, ppos, tmp_buf,
+			strlen(tmp_buf));
+}
+
+static ssize_t hl_data_write64(struct file *f, const char __user *buf,
+					size_t count, loff_t *ppos)
+{
+	struct hl_dbg_device_entry *entry = file_inode(f)->i_private;
+	struct hl_device *hdev = entry->hdev;
+	u64 addr = entry->addr;
+	u64 value;
+	ssize_t rc;
+
+	if (hdev->reset_info.in_reset) {
+		dev_warn_ratelimited(hdev->dev, "Can't write during reset\n");
+		return 0;
+	}
+
+	rc = kstrtoull_from_user(buf, count, 16, &value);
+	if (rc)
+		return rc;
+
+	rc = hl_access_mem(hdev, addr, &value, DEBUGFS_WRITE64);
+	if (rc)
+		return rc;
+
+	return count;
+}
+
+static ssize_t hl_dma_size_write(struct file *f, const char __user *buf,
+					size_t count, loff_t *ppos)
+{
+	struct hl_dbg_device_entry *entry = file_inode(f)->i_private;
+	struct hl_device *hdev = entry->hdev;
+	u64 addr = entry->addr;
+	ssize_t rc;
+	u32 size;
+
+	if (hdev->reset_info.in_reset) {
+		dev_warn_ratelimited(hdev->dev, "Can't DMA during reset\n");
+		return 0;
+	}
+	rc = kstrtouint_from_user(buf, count, 16, &size);
+	if (rc)
+		return rc;
+
+	if (!size) {
+		dev_err(hdev->dev, "DMA read failed. size can't be 0\n");
+		return -EINVAL;
+	}
+
+	if (size > SZ_128M) {
+		dev_err(hdev->dev,
+			"DMA read failed. size can't be larger than 128MB\n");
+		return -EINVAL;
+	}
+
+	if (!hl_is_device_internal_memory_va(hdev, addr, size)) {
+		dev_err(hdev->dev,
+			"DMA read failed. Invalid 0x%010llx + 0x%08x\n",
+			addr, size);
+		return -EINVAL;
+	}
+
+	/* Free the previous allocation, if there was any */
+	entry->data_dma_blob_desc.size = 0;
+	vfree(entry->data_dma_blob_desc.data);
+
+	entry->data_dma_blob_desc.data = vmalloc(size);
+	if (!entry->data_dma_blob_desc.data)
+		return -ENOMEM;
+
+	rc = hdev->asic_funcs->debugfs_read_dma(hdev, addr, size,
+						entry->data_dma_blob_desc.data);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to DMA from 0x%010llx\n", addr);
+		vfree(entry->data_dma_blob_desc.data);
+		entry->data_dma_blob_desc.data = NULL;
+		return -EIO;
+	}
+
+	entry->data_dma_blob_desc.size = size;
+
+	return count;
+}
+
+static ssize_t hl_monitor_dump_trigger(struct file *f, const char __user *buf,
+					size_t count, loff_t *ppos)
+{
+	struct hl_dbg_device_entry *entry = file_inode(f)->i_private;
+	struct hl_device *hdev = entry->hdev;
+	u32 size, trig;
+	ssize_t rc;
+
+	if (hdev->reset_info.in_reset) {
+		dev_warn_ratelimited(hdev->dev, "Can't dump monitors during reset\n");
+		return 0;
+	}
+	rc = kstrtouint_from_user(buf, count, 10, &trig);
+	if (rc)
+		return rc;
+
+	if (trig != 1) {
+		dev_err(hdev->dev, "Must write 1 to trigger monitor dump\n");
+		return -EINVAL;
+	}
+
+	size = sizeof(struct cpucp_monitor_dump);
+
+	/* Free the previous allocation, if there was any */
+	entry->mon_dump_blob_desc.size = 0;
+	vfree(entry->mon_dump_blob_desc.data);
+
+	entry->mon_dump_blob_desc.data = vmalloc(size);
+	if (!entry->mon_dump_blob_desc.data)
+		return -ENOMEM;
+
+	rc = hdev->asic_funcs->get_monitor_dump(hdev, entry->mon_dump_blob_desc.data);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to dump monitors\n");
+		vfree(entry->mon_dump_blob_desc.data);
+		entry->mon_dump_blob_desc.data = NULL;
+		return -EIO;
+	}
+
+	entry->mon_dump_blob_desc.size = size;
+
+	return count;
+}
+
+static ssize_t hl_get_power_state(struct file *f, char __user *buf,
+		size_t count, loff_t *ppos)
+{
+	struct hl_dbg_device_entry *entry = file_inode(f)->i_private;
+	struct hl_device *hdev = entry->hdev;
+	char tmp_buf[200];
+	int i;
+
+	if (*ppos)
+		return 0;
+
+	if (hdev->pdev->current_state == PCI_D0)
+		i = 1;
+	else if (hdev->pdev->current_state == PCI_D3hot)
+		i = 2;
+	else
+		i = 3;
+
+	sprintf(tmp_buf,
+		"current power state: %d\n1 - D0\n2 - D3hot\n3 - Unknown\n", i);
+	return simple_read_from_buffer(buf, count, ppos, tmp_buf,
+			strlen(tmp_buf));
+}
+
+static ssize_t hl_set_power_state(struct file *f, const char __user *buf,
+					size_t count, loff_t *ppos)
+{
+	struct hl_dbg_device_entry *entry = file_inode(f)->i_private;
+	struct hl_device *hdev = entry->hdev;
+	u32 value;
+	ssize_t rc;
+
+	rc = kstrtouint_from_user(buf, count, 10, &value);
+	if (rc)
+		return rc;
+
+	if (value == 1) {
+		pci_set_power_state(hdev->pdev, PCI_D0);
+		pci_restore_state(hdev->pdev);
+		rc = pci_enable_device(hdev->pdev);
+		if (rc < 0)
+			return rc;
+	} else if (value == 2) {
+		pci_save_state(hdev->pdev);
+		pci_disable_device(hdev->pdev);
+		pci_set_power_state(hdev->pdev, PCI_D3hot);
+	} else {
+		dev_dbg(hdev->dev, "invalid power state value %u\n", value);
+		return -EINVAL;
+	}
+
+	return count;
+}
+
+static ssize_t hl_i2c_data_read(struct file *f, char __user *buf,
+					size_t count, loff_t *ppos)
+{
+	struct hl_dbg_device_entry *entry = file_inode(f)->i_private;
+	struct hl_device *hdev = entry->hdev;
+	char tmp_buf[32];
+	u64 val;
+	ssize_t rc;
+
+	if (*ppos)
+		return 0;
+
+	rc = hl_debugfs_i2c_read(hdev, entry->i2c_bus, entry->i2c_addr,
+			entry->i2c_reg, entry->i2c_len, &val);
+	if (rc) {
+		dev_err(hdev->dev,
+			"Failed to read from I2C bus %d, addr %d, reg %d, len %d\n",
+			entry->i2c_bus, entry->i2c_addr, entry->i2c_reg, entry->i2c_len);
+		return rc;
+	}
+
+	sprintf(tmp_buf, "%#02llx\n", val);
+	rc = simple_read_from_buffer(buf, count, ppos, tmp_buf,
+			strlen(tmp_buf));
+
+	return rc;
+}
+
+static ssize_t hl_i2c_data_write(struct file *f, const char __user *buf,
+					size_t count, loff_t *ppos)
+{
+	struct hl_dbg_device_entry *entry = file_inode(f)->i_private;
+	struct hl_device *hdev = entry->hdev;
+	u64 value;
+	ssize_t rc;
+
+	rc = kstrtou64_from_user(buf, count, 16, &value);
+	if (rc)
+		return rc;
+
+	rc = hl_debugfs_i2c_write(hdev, entry->i2c_bus, entry->i2c_addr,
+			entry->i2c_reg, entry->i2c_len, value);
+	if (rc) {
+		dev_err(hdev->dev,
+			"Failed to write %#02llx to I2C bus %d, addr %d, reg %d, len %d\n",
+			value, entry->i2c_bus, entry->i2c_addr, entry->i2c_reg, entry->i2c_len);
+		return rc;
+	}
+
+	return count;
+}
+
+static ssize_t hl_led0_write(struct file *f, const char __user *buf,
+					size_t count, loff_t *ppos)
+{
+	struct hl_dbg_device_entry *entry = file_inode(f)->i_private;
+	struct hl_device *hdev = entry->hdev;
+	u32 value;
+	ssize_t rc;
+
+	rc = kstrtouint_from_user(buf, count, 10, &value);
+	if (rc)
+		return rc;
+
+	value = value ? 1 : 0;
+
+	hl_debugfs_led_set(hdev, 0, value);
+
+	return count;
+}
+
+static ssize_t hl_led1_write(struct file *f, const char __user *buf,
+					size_t count, loff_t *ppos)
+{
+	struct hl_dbg_device_entry *entry = file_inode(f)->i_private;
+	struct hl_device *hdev = entry->hdev;
+	u32 value;
+	ssize_t rc;
+
+	rc = kstrtouint_from_user(buf, count, 10, &value);
+	if (rc)
+		return rc;
+
+	value = value ? 1 : 0;
+
+	hl_debugfs_led_set(hdev, 1, value);
+
+	return count;
+}
+
+static ssize_t hl_led2_write(struct file *f, const char __user *buf,
+					size_t count, loff_t *ppos)
+{
+	struct hl_dbg_device_entry *entry = file_inode(f)->i_private;
+	struct hl_device *hdev = entry->hdev;
+	u32 value;
+	ssize_t rc;
+
+	rc = kstrtouint_from_user(buf, count, 10, &value);
+	if (rc)
+		return rc;
+
+	value = value ? 1 : 0;
+
+	hl_debugfs_led_set(hdev, 2, value);
+
+	return count;
+}
+
+static ssize_t hl_device_read(struct file *f, char __user *buf,
+					size_t count, loff_t *ppos)
+{
+	static const char *help =
+		"Valid values: disable, enable, suspend, resume, cpu_timeout\n";
+	return simple_read_from_buffer(buf, count, ppos, help, strlen(help));
+}
+
+static ssize_t hl_device_write(struct file *f, const char __user *buf,
+				     size_t count, loff_t *ppos)
+{
+	struct hl_dbg_device_entry *entry = file_inode(f)->i_private;
+	struct hl_device *hdev = entry->hdev;
+	char data[30] = {0};
+
+	/* don't allow partial writes */
+	if (*ppos != 0)
+		return 0;
+
+	simple_write_to_buffer(data, 29, ppos, buf, count);
+
+	if (strncmp("disable", data, strlen("disable")) == 0) {
+		hdev->disabled = true;
+	} else if (strncmp("enable", data, strlen("enable")) == 0) {
+		hdev->disabled = false;
+	} else if (strncmp("suspend", data, strlen("suspend")) == 0) {
+		hdev->asic_funcs->suspend(hdev);
+	} else if (strncmp("resume", data, strlen("resume")) == 0) {
+		hdev->asic_funcs->resume(hdev);
+	} else if (strncmp("cpu_timeout", data, strlen("cpu_timeout")) == 0) {
+		hdev->device_cpu_disabled = true;
+	} else {
+		dev_err(hdev->dev,
+			"Valid values: disable, enable, suspend, resume, cpu_timeout\n");
+		count = -EINVAL;
+	}
+
+	return count;
+}
+
+static ssize_t hl_clk_gate_read(struct file *f, char __user *buf,
+					size_t count, loff_t *ppos)
+{
+	return 0;
+}
+
+static ssize_t hl_clk_gate_write(struct file *f, const char __user *buf,
+				     size_t count, loff_t *ppos)
+{
+	return count;
+}
+
+static ssize_t hl_stop_on_err_read(struct file *f, char __user *buf,
+					size_t count, loff_t *ppos)
+{
+	struct hl_dbg_device_entry *entry = file_inode(f)->i_private;
+	struct hl_device *hdev = entry->hdev;
+	char tmp_buf[200];
+	ssize_t rc;
+
+	if (!hdev->asic_prop.configurable_stop_on_err)
+		return -EOPNOTSUPP;
+
+	if (*ppos)
+		return 0;
+
+	sprintf(tmp_buf, "%d\n", hdev->stop_on_err);
+	rc = simple_read_from_buffer(buf, strlen(tmp_buf) + 1, ppos, tmp_buf,
+			strlen(tmp_buf) + 1);
+
+	return rc;
+}
+
+static ssize_t hl_stop_on_err_write(struct file *f, const char __user *buf,
+				     size_t count, loff_t *ppos)
+{
+	struct hl_dbg_device_entry *entry = file_inode(f)->i_private;
+	struct hl_device *hdev = entry->hdev;
+	u32 value;
+	ssize_t rc;
+
+	if (!hdev->asic_prop.configurable_stop_on_err)
+		return -EOPNOTSUPP;
+
+	if (hdev->reset_info.in_reset) {
+		dev_warn_ratelimited(hdev->dev,
+				"Can't change stop on error during reset\n");
+		return 0;
+	}
+
+	rc = kstrtouint_from_user(buf, count, 10, &value);
+	if (rc)
+		return rc;
+
+	hdev->stop_on_err = value ? 1 : 0;
+
+	hl_device_reset(hdev, 0);
+
+	return count;
+}
+
+static ssize_t hl_security_violations_read(struct file *f, char __user *buf,
+					size_t count, loff_t *ppos)
+{
+	struct hl_dbg_device_entry *entry = file_inode(f)->i_private;
+	struct hl_device *hdev = entry->hdev;
+
+	hdev->asic_funcs->ack_protection_bits_errors(hdev);
+
+	return 0;
+}
+
+static ssize_t hl_state_dump_read(struct file *f, char __user *buf,
+					size_t count, loff_t *ppos)
+{
+	struct hl_dbg_device_entry *entry = file_inode(f)->i_private;
+	ssize_t rc;
+
+	down_read(&entry->state_dump_sem);
+	if (!entry->state_dump[entry->state_dump_head])
+		rc = 0;
+	else
+		rc = simple_read_from_buffer(
+			buf, count, ppos,
+			entry->state_dump[entry->state_dump_head],
+			strlen(entry->state_dump[entry->state_dump_head]));
+	up_read(&entry->state_dump_sem);
+
+	return rc;
+}
+
+static ssize_t hl_state_dump_write(struct file *f, const char __user *buf,
+					size_t count, loff_t *ppos)
+{
+	struct hl_dbg_device_entry *entry = file_inode(f)->i_private;
+	struct hl_device *hdev = entry->hdev;
+	ssize_t rc;
+	u32 size;
+	int i;
+
+	rc = kstrtouint_from_user(buf, count, 10, &size);
+	if (rc)
+		return rc;
+
+	if (size <= 0 || size >= ARRAY_SIZE(entry->state_dump)) {
+		dev_err(hdev->dev, "Invalid number of dumps to skip\n");
+		return -EINVAL;
+	}
+
+	if (entry->state_dump[entry->state_dump_head]) {
+		down_write(&entry->state_dump_sem);
+		for (i = 0; i < size; ++i) {
+			vfree(entry->state_dump[entry->state_dump_head]);
+			entry->state_dump[entry->state_dump_head] = NULL;
+			if (entry->state_dump_head > 0)
+				entry->state_dump_head--;
+			else
+				entry->state_dump_head =
+					ARRAY_SIZE(entry->state_dump) - 1;
+		}
+		up_write(&entry->state_dump_sem);
+	}
+
+	return count;
+}
+
+static ssize_t hl_timeout_locked_read(struct file *f, char __user *buf,
+					size_t count, loff_t *ppos)
+{
+	struct hl_dbg_device_entry *entry = file_inode(f)->i_private;
+	struct hl_device *hdev = entry->hdev;
+	char tmp_buf[200];
+	ssize_t rc;
+
+	if (*ppos)
+		return 0;
+
+	sprintf(tmp_buf, "%d\n",
+		jiffies_to_msecs(hdev->timeout_jiffies) / 1000);
+	rc = simple_read_from_buffer(buf, strlen(tmp_buf) + 1, ppos, tmp_buf,
+			strlen(tmp_buf) + 1);
+
+	return rc;
+}
+
+static ssize_t hl_timeout_locked_write(struct file *f, const char __user *buf,
+				     size_t count, loff_t *ppos)
+{
+	struct hl_dbg_device_entry *entry = file_inode(f)->i_private;
+	struct hl_device *hdev = entry->hdev;
+	u32 value;
+	ssize_t rc;
+
+	rc = kstrtouint_from_user(buf, count, 10, &value);
+	if (rc)
+		return rc;
+
+	if (value)
+		hdev->timeout_jiffies = secs_to_jiffies(value);
+	else
+		hdev->timeout_jiffies = MAX_SCHEDULE_TIMEOUT;
+
+	return count;
+}
+
+static ssize_t hl_check_razwi_happened(struct file *f, char __user *buf,
+					size_t count, loff_t *ppos)
+{
+	struct hl_dbg_device_entry *entry = file_inode(f)->i_private;
+	struct hl_device *hdev = entry->hdev;
+
+	hdev->asic_funcs->check_if_razwi_happened(hdev);
+
+	return 0;
+}
+
+static const struct file_operations hl_mem_scrub_fops = {
+	.owner = THIS_MODULE,
+	.write = hl_memory_scrub,
+};
+
+static const struct file_operations hl_data32b_fops = {
+	.owner = THIS_MODULE,
+	.read = hl_data_read32,
+	.write = hl_data_write32
+};
+
+static const struct file_operations hl_data64b_fops = {
+	.owner = THIS_MODULE,
+	.read = hl_data_read64,
+	.write = hl_data_write64
+};
+
+static const struct file_operations hl_dma_size_fops = {
+	.owner = THIS_MODULE,
+	.write = hl_dma_size_write
+};
+
+static const struct file_operations hl_monitor_dump_fops = {
+	.owner = THIS_MODULE,
+	.write = hl_monitor_dump_trigger
+};
+
+static const struct file_operations hl_i2c_data_fops = {
+	.owner = THIS_MODULE,
+	.read = hl_i2c_data_read,
+	.write = hl_i2c_data_write
+};
+
+static const struct file_operations hl_power_fops = {
+	.owner = THIS_MODULE,
+	.read = hl_get_power_state,
+	.write = hl_set_power_state
+};
+
+static const struct file_operations hl_led0_fops = {
+	.owner = THIS_MODULE,
+	.write = hl_led0_write
+};
+
+static const struct file_operations hl_led1_fops = {
+	.owner = THIS_MODULE,
+	.write = hl_led1_write
+};
+
+static const struct file_operations hl_led2_fops = {
+	.owner = THIS_MODULE,
+	.write = hl_led2_write
+};
+
+static const struct file_operations hl_device_fops = {
+	.owner = THIS_MODULE,
+	.read = hl_device_read,
+	.write = hl_device_write
+};
+
+static const struct file_operations hl_clk_gate_fops = {
+	.owner = THIS_MODULE,
+	.read = hl_clk_gate_read,
+	.write = hl_clk_gate_write
+};
+
+static const struct file_operations hl_stop_on_err_fops = {
+	.owner = THIS_MODULE,
+	.read = hl_stop_on_err_read,
+	.write = hl_stop_on_err_write
+};
+
+static const struct file_operations hl_security_violations_fops = {
+	.owner = THIS_MODULE,
+	.read = hl_security_violations_read
+};
+
+static const struct file_operations hl_state_dump_fops = {
+	.owner = THIS_MODULE,
+	.read = hl_state_dump_read,
+	.write = hl_state_dump_write
+};
+
+static const struct file_operations hl_timeout_locked_fops = {
+	.owner = THIS_MODULE,
+	.read = hl_timeout_locked_read,
+	.write = hl_timeout_locked_write
+};
+
+static const struct file_operations hl_razwi_check_fops = {
+	.owner = THIS_MODULE,
+	.read = hl_check_razwi_happened
+};
+
+static const struct hl_info_list hl_debugfs_list[] = {
+	{"command_buffers", command_buffers_show, NULL},
+	{"command_submission", command_submission_show, NULL},
+	{"command_submission_jobs", command_submission_jobs_show, NULL},
+	{"userptr", userptr_show, NULL},
+	{"vm", vm_show, NULL},
+	{"userptr_lookup", userptr_lookup_show, userptr_lookup_write},
+	{"mmu", mmu_show, mmu_asid_va_write},
+	{"mmu_error", mmu_ack_error, mmu_ack_error_value_write},
+	{"engines", engines_show, NULL},
+#ifdef CONFIG_HL_HLDIO
+	/* DIO entries - only created if NVMe is supported */
+	{"dio_ssd2hl", dio_ssd2hl_show, dio_ssd2hl_write},
+	{"dio_stats", dio_stats_show, NULL},
+	{"dio_reset", dio_reset_show, dio_reset_write},
+	{"dio_hl2ssd", dio_hl2ssd_show, dio_hl2ssd_write},
+#endif
+};
+
+static int hl_debugfs_open(struct inode *inode, struct file *file)
+{
+	struct hl_debugfs_entry *node = inode->i_private;
+
+	return single_open(file, node->info_ent->show, node);
+}
+
+static ssize_t hl_debugfs_write(struct file *file, const char __user *buf,
+		size_t count, loff_t *f_pos)
+{
+	struct hl_debugfs_entry *node = file->f_inode->i_private;
+
+	if (node->info_ent->write)
+		return node->info_ent->write(file, buf, count, f_pos);
+	else
+		return -EINVAL;
+
+}
+
+static const struct file_operations hl_debugfs_fops = {
+	.owner = THIS_MODULE,
+	.open = hl_debugfs_open,
+	.read = seq_read,
+	.write = hl_debugfs_write,
+	.llseek = seq_lseek,
+	.release = single_release,
+};
+
+static void add_secured_nodes(struct hl_dbg_device_entry *dev_entry, struct dentry *root)
+{
+	debugfs_create_u8("i2c_bus",
+				0644,
+				root,
+				&dev_entry->i2c_bus);
+
+	debugfs_create_u8("i2c_addr",
+				0644,
+				root,
+				&dev_entry->i2c_addr);
+
+	debugfs_create_u8("i2c_reg",
+				0644,
+				root,
+				&dev_entry->i2c_reg);
+
+	debugfs_create_u8("i2c_len",
+				0644,
+				root,
+				&dev_entry->i2c_len);
+
+	debugfs_create_file("i2c_data",
+				0644,
+				root,
+				dev_entry,
+				&hl_i2c_data_fops);
+
+	debugfs_create_file("led0",
+				0200,
+				root,
+				dev_entry,
+				&hl_led0_fops);
+
+	debugfs_create_file("led1",
+				0200,
+				root,
+				dev_entry,
+				&hl_led1_fops);
+
+	debugfs_create_file("led2",
+				0200,
+				root,
+				dev_entry,
+				&hl_led2_fops);
+}
+
+static void add_files_to_device(struct hl_device *hdev, struct hl_dbg_device_entry *dev_entry,
+				struct dentry *root)
+{
+	int count = ARRAY_SIZE(hl_debugfs_list);
+	struct hl_debugfs_entry *entry;
+	int i;
+
+	debugfs_create_x64("memory_scrub_val",
+				0644,
+				root,
+				&hdev->memory_scrub_val);
+
+	debugfs_create_file("memory_scrub",
+				0200,
+				root,
+				dev_entry,
+				&hl_mem_scrub_fops);
+
+	debugfs_create_x64("addr",
+				0644,
+				root,
+				&dev_entry->addr);
+
+	debugfs_create_file("data32",
+				0644,
+				root,
+				dev_entry,
+				&hl_data32b_fops);
+
+	debugfs_create_file("data64",
+				0644,
+				root,
+				dev_entry,
+				&hl_data64b_fops);
+
+	debugfs_create_file("set_power_state",
+				0644,
+				root,
+				dev_entry,
+				&hl_power_fops);
+
+	debugfs_create_file("device",
+				0644,
+				root,
+				dev_entry,
+				&hl_device_fops);
+
+	debugfs_create_file("clk_gate",
+				0644,
+				root,
+				dev_entry,
+				&hl_clk_gate_fops);
+
+	debugfs_create_file("stop_on_err",
+				0644,
+				root,
+				dev_entry,
+				&hl_stop_on_err_fops);
+
+	debugfs_create_file("dump_security_violations",
+				0400,
+				root,
+				dev_entry,
+				&hl_security_violations_fops);
+
+	debugfs_create_file("dump_razwi_events",
+				0400,
+				root,
+				dev_entry,
+				&hl_razwi_check_fops);
+
+	debugfs_create_file("dma_size",
+				0200,
+				root,
+				dev_entry,
+				&hl_dma_size_fops);
+
+	debugfs_create_blob("data_dma",
+				0400,
+				root,
+				&dev_entry->data_dma_blob_desc);
+
+	debugfs_create_file("monitor_dump_trig",
+				0200,
+				root,
+				dev_entry,
+				&hl_monitor_dump_fops);
+
+	debugfs_create_blob("monitor_dump",
+				0400,
+				root,
+				&dev_entry->mon_dump_blob_desc);
+
+	debugfs_create_x8("skip_reset_on_timeout",
+				0644,
+				root,
+				&hdev->reset_info.skip_reset_on_timeout);
+
+	debugfs_create_file("state_dump",
+				0644,
+				root,
+				dev_entry,
+				&hl_state_dump_fops);
+
+	debugfs_create_file("timeout_locked",
+				0644,
+				root,
+				dev_entry,
+				&hl_timeout_locked_fops);
+
+	debugfs_create_u32("device_release_watchdog_timeout",
+				0644,
+				root,
+				&hdev->device_release_watchdog_timeout_sec);
+
+	debugfs_create_u16("server_type",
+				0444,
+				root,
+				&hdev->asic_prop.server_type);
+
+	for (i = 0, entry = dev_entry->entry_arr ; i < count ; i++, entry++) {
+		/* Skip DIO entries if NVMe is not supported */
+		if (strncmp(hl_debugfs_list[i].name, "dio_", 4) == 0 &&
+		    !hdev->asic_prop.supports_nvme)
+			continue;
+
+		debugfs_create_file(hl_debugfs_list[i].name,
+					0644,
+					root,
+					entry,
+					&hl_debugfs_fops);
+		entry->info_ent = &hl_debugfs_list[i];
+		entry->dev_entry = dev_entry;
+	}
+}
+
+int hl_debugfs_device_init(struct hl_device *hdev)
+{
+	struct hl_dbg_device_entry *dev_entry = &hdev->hl_debugfs;
+	int count = ARRAY_SIZE(hl_debugfs_list);
+
+	dev_entry->hdev = hdev;
+	dev_entry->entry_arr = kmalloc_array(count, sizeof(struct hl_debugfs_entry), GFP_KERNEL);
+	if (!dev_entry->entry_arr)
+		return -ENOMEM;
+
+	dev_entry->data_dma_blob_desc.size = 0;
+	dev_entry->data_dma_blob_desc.data = NULL;
+	dev_entry->mon_dump_blob_desc.size = 0;
+	dev_entry->mon_dump_blob_desc.data = NULL;
+
+	INIT_LIST_HEAD(&dev_entry->file_list);
+	INIT_LIST_HEAD(&dev_entry->cb_list);
+	INIT_LIST_HEAD(&dev_entry->cs_list);
+	INIT_LIST_HEAD(&dev_entry->cs_job_list);
+	INIT_LIST_HEAD(&dev_entry->userptr_list);
+	INIT_LIST_HEAD(&dev_entry->ctx_mem_hash_list);
+	mutex_init(&dev_entry->file_mutex);
+	init_rwsem(&dev_entry->state_dump_sem);
+	spin_lock_init(&dev_entry->cb_spinlock);
+	spin_lock_init(&dev_entry->cs_spinlock);
+	spin_lock_init(&dev_entry->cs_job_spinlock);
+	spin_lock_init(&dev_entry->userptr_spinlock);
+	mutex_init(&dev_entry->ctx_mem_hash_mutex);
+
+	spin_lock_init(&hdev->debugfs_cfg_accesses.lock);
+	hdev->debugfs_cfg_accesses.head = 0; /* already zero by alloc but explicit init is fine */
+
+#ifdef CONFIG_HL_HLDIO
+	/* Initialize DIO statistics */
+	memset(&dev_entry->dio_stats, 0, sizeof(dev_entry->dio_stats));
+#endif
+
+	return 0;
+}
+
+void hl_debugfs_device_fini(struct hl_device *hdev)
+{
+	struct hl_dbg_device_entry *entry = &hdev->hl_debugfs;
+	int i;
+
+	mutex_destroy(&entry->ctx_mem_hash_mutex);
+	mutex_destroy(&entry->file_mutex);
+
+	vfree(entry->data_dma_blob_desc.data);
+	vfree(entry->mon_dump_blob_desc.data);
+
+	for (i = 0; i < ARRAY_SIZE(entry->state_dump); ++i)
+		vfree(entry->state_dump[i]);
+
+	kfree(entry->entry_arr);
+
+}
+
+void hl_debugfs_add_device(struct hl_device *hdev)
+{
+	struct hl_dbg_device_entry *dev_entry = &hdev->hl_debugfs;
+
+	dev_entry->root = hdev->drm.accel->debugfs_root;
+
+	add_files_to_device(hdev, dev_entry, dev_entry->root);
+
+	if (!hdev->asic_prop.fw_security_enabled)
+		add_secured_nodes(dev_entry, dev_entry->root);
+
+}
+
+void hl_debugfs_add_file(struct hl_fpriv *hpriv)
+{
+	struct hl_dbg_device_entry *dev_entry = &hpriv->hdev->hl_debugfs;
+
+	mutex_lock(&dev_entry->file_mutex);
+	list_add(&hpriv->debugfs_list, &dev_entry->file_list);
+	mutex_unlock(&dev_entry->file_mutex);
+}
+
+void hl_debugfs_remove_file(struct hl_fpriv *hpriv)
+{
+	struct hl_dbg_device_entry *dev_entry = &hpriv->hdev->hl_debugfs;
+
+	mutex_lock(&dev_entry->file_mutex);
+	list_del(&hpriv->debugfs_list);
+	mutex_unlock(&dev_entry->file_mutex);
+}
+
+void hl_debugfs_add_cb(struct hl_cb *cb)
+{
+	struct hl_dbg_device_entry *dev_entry = &cb->hdev->hl_debugfs;
+
+	spin_lock(&dev_entry->cb_spinlock);
+	list_add(&cb->debugfs_list, &dev_entry->cb_list);
+	spin_unlock(&dev_entry->cb_spinlock);
+}
+
+void hl_debugfs_remove_cb(struct hl_cb *cb)
+{
+	struct hl_dbg_device_entry *dev_entry = &cb->hdev->hl_debugfs;
+
+	spin_lock(&dev_entry->cb_spinlock);
+	list_del(&cb->debugfs_list);
+	spin_unlock(&dev_entry->cb_spinlock);
+}
+
+void hl_debugfs_add_cs(struct hl_cs *cs)
+{
+	struct hl_dbg_device_entry *dev_entry = &cs->ctx->hdev->hl_debugfs;
+
+	spin_lock(&dev_entry->cs_spinlock);
+	list_add(&cs->debugfs_list, &dev_entry->cs_list);
+	spin_unlock(&dev_entry->cs_spinlock);
+}
+
+void hl_debugfs_remove_cs(struct hl_cs *cs)
+{
+	struct hl_dbg_device_entry *dev_entry = &cs->ctx->hdev->hl_debugfs;
+
+	spin_lock(&dev_entry->cs_spinlock);
+	list_del(&cs->debugfs_list);
+	spin_unlock(&dev_entry->cs_spinlock);
+}
+
+void hl_debugfs_add_job(struct hl_device *hdev, struct hl_cs_job *job)
+{
+	struct hl_dbg_device_entry *dev_entry = &hdev->hl_debugfs;
+
+	spin_lock(&dev_entry->cs_job_spinlock);
+	list_add(&job->debugfs_list, &dev_entry->cs_job_list);
+	spin_unlock(&dev_entry->cs_job_spinlock);
+}
+
+void hl_debugfs_remove_job(struct hl_device *hdev, struct hl_cs_job *job)
+{
+	struct hl_dbg_device_entry *dev_entry = &hdev->hl_debugfs;
+
+	spin_lock(&dev_entry->cs_job_spinlock);
+	list_del(&job->debugfs_list);
+	spin_unlock(&dev_entry->cs_job_spinlock);
+}
+
+void hl_debugfs_add_userptr(struct hl_device *hdev, struct hl_userptr *userptr)
+{
+	struct hl_dbg_device_entry *dev_entry = &hdev->hl_debugfs;
+
+	spin_lock(&dev_entry->userptr_spinlock);
+	list_add(&userptr->debugfs_list, &dev_entry->userptr_list);
+	spin_unlock(&dev_entry->userptr_spinlock);
+}
+
+void hl_debugfs_remove_userptr(struct hl_device *hdev,
+				struct hl_userptr *userptr)
+{
+	struct hl_dbg_device_entry *dev_entry = &hdev->hl_debugfs;
+
+	spin_lock(&dev_entry->userptr_spinlock);
+	list_del(&userptr->debugfs_list);
+	spin_unlock(&dev_entry->userptr_spinlock);
+}
+
+void hl_debugfs_add_ctx_mem_hash(struct hl_device *hdev, struct hl_ctx *ctx)
+{
+	struct hl_dbg_device_entry *dev_entry = &hdev->hl_debugfs;
+
+	mutex_lock(&dev_entry->ctx_mem_hash_mutex);
+	list_add(&ctx->debugfs_list, &dev_entry->ctx_mem_hash_list);
+	mutex_unlock(&dev_entry->ctx_mem_hash_mutex);
+}
+
+void hl_debugfs_remove_ctx_mem_hash(struct hl_device *hdev, struct hl_ctx *ctx)
+{
+	struct hl_dbg_device_entry *dev_entry = &hdev->hl_debugfs;
+
+	mutex_lock(&dev_entry->ctx_mem_hash_mutex);
+	list_del(&ctx->debugfs_list);
+	mutex_unlock(&dev_entry->ctx_mem_hash_mutex);
+}
+
+/**
+ * hl_debugfs_set_state_dump - register state dump making it accessible via
+ *                             debugfs
+ * @hdev: pointer to the device structure
+ * @data: the actual dump data
+ * @length: the length of the data
+ */
+void hl_debugfs_set_state_dump(struct hl_device *hdev, char *data,
+					unsigned long length)
+{
+	struct hl_dbg_device_entry *dev_entry = &hdev->hl_debugfs;
+
+	down_write(&dev_entry->state_dump_sem);
+
+	dev_entry->state_dump_head = (dev_entry->state_dump_head + 1) %
+					ARRAY_SIZE(dev_entry->state_dump);
+	vfree(dev_entry->state_dump[dev_entry->state_dump_head]);
+	dev_entry->state_dump[dev_entry->state_dump_head] = data;
+
+	up_write(&dev_entry->state_dump_sem);
+}
+
diff --git a/drivers/accel/habanalabs/common/decoder.c b/drivers/accel/habanalabs/common/decoder.c
new file mode 100644
index 000000000000..c03a6da45d00
--- /dev/null
+++ b/drivers/accel/habanalabs/common/decoder.c
@@ -0,0 +1,141 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Copyright 2022 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ */
+
+#include "habanalabs.h"
+
+#define VCMD_CONTROL_OFFSET			0x40	/* SWREG16 */
+#define VCMD_IRQ_STATUS_OFFSET			0x44	/* SWREG17 */
+
+#define VCMD_IRQ_STATUS_ENDCMD_MASK		0x1
+#define VCMD_IRQ_STATUS_BUSERR_MASK		0x2
+#define VCMD_IRQ_STATUS_TIMEOUT_MASK		0x4
+#define VCMD_IRQ_STATUS_CMDERR_MASK		0x8
+#define VCMD_IRQ_STATUS_ABORT_MASK		0x10
+#define VCMD_IRQ_STATUS_RESET_MASK		0x20
+
+static void dec_print_abnrm_intr_source(struct hl_device *hdev, u32 irq_status)
+{
+	const char *format = "abnormal interrupt source:%s%s%s%s%s%s\n";
+	char *intr_source[6] = {"Unknown", "", "", "", "", ""};
+	int i = 0;
+
+	if (!irq_status)
+		return;
+
+	if (irq_status & VCMD_IRQ_STATUS_ENDCMD_MASK)
+		intr_source[i++] = " ENDCMD";
+	if (irq_status & VCMD_IRQ_STATUS_BUSERR_MASK)
+		intr_source[i++] = " BUSERR";
+	if (irq_status & VCMD_IRQ_STATUS_TIMEOUT_MASK)
+		intr_source[i++] = " TIMEOUT";
+	if (irq_status & VCMD_IRQ_STATUS_CMDERR_MASK)
+		intr_source[i++] = " CMDERR";
+	if (irq_status & VCMD_IRQ_STATUS_ABORT_MASK)
+		intr_source[i++] = " ABORT";
+	if (irq_status & VCMD_IRQ_STATUS_RESET_MASK)
+		intr_source[i++] = " RESET";
+
+	dev_err(hdev->dev, format, intr_source[0], intr_source[1],
+		intr_source[2], intr_source[3], intr_source[4], intr_source[5]);
+}
+
+static void dec_abnrm_intr_work(struct work_struct *work)
+{
+	struct hl_dec *dec = container_of(work, struct hl_dec, abnrm_intr_work);
+	struct hl_device *hdev = dec->hdev;
+	u32 irq_status, event_mask = 0;
+	bool reset_required = false;
+
+	irq_status = RREG32(dec->base_addr + VCMD_IRQ_STATUS_OFFSET);
+
+	dev_err(hdev->dev, "Decoder abnormal interrupt %#x, core %d\n", irq_status, dec->core_id);
+
+	dec_print_abnrm_intr_source(hdev, irq_status);
+
+	/* Clear the interrupt */
+	WREG32(dec->base_addr + VCMD_IRQ_STATUS_OFFSET, irq_status);
+
+	/* Flush the interrupt clear */
+	RREG32(dec->base_addr + VCMD_IRQ_STATUS_OFFSET);
+
+	if (irq_status & VCMD_IRQ_STATUS_TIMEOUT_MASK) {
+		reset_required = true;
+		event_mask |= HL_NOTIFIER_EVENT_GENERAL_HW_ERR;
+	}
+
+	if (irq_status & VCMD_IRQ_STATUS_CMDERR_MASK)
+		event_mask |= HL_NOTIFIER_EVENT_UNDEFINED_OPCODE;
+
+	if (irq_status & (VCMD_IRQ_STATUS_ENDCMD_MASK |
+				VCMD_IRQ_STATUS_BUSERR_MASK |
+				VCMD_IRQ_STATUS_ABORT_MASK))
+		event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR;
+
+	if (reset_required) {
+		event_mask |= HL_NOTIFIER_EVENT_DEVICE_RESET;
+		hl_device_cond_reset(hdev, 0, event_mask);
+	} else if (event_mask) {
+		hl_notifier_event_send_all(hdev, event_mask);
+	}
+}
+
+void hl_dec_fini(struct hl_device *hdev)
+{
+	kfree(hdev->dec);
+}
+
+int hl_dec_init(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct hl_dec *dec;
+	int rc, j;
+
+	/* if max core is 0, nothing to do*/
+	if (!prop->max_dec)
+		return 0;
+
+	hdev->dec = kcalloc(prop->max_dec, sizeof(struct hl_dec), GFP_KERNEL);
+	if (!hdev->dec)
+		return -ENOMEM;
+
+	for (j = 0 ; j < prop->max_dec ; j++) {
+		dec = hdev->dec + j;
+
+		dec->hdev = hdev;
+		INIT_WORK(&dec->abnrm_intr_work, dec_abnrm_intr_work);
+		dec->core_id = j;
+		dec->base_addr = hdev->asic_funcs->get_dec_base_addr(hdev, j);
+		if (!dec->base_addr) {
+			dev_err(hdev->dev, "Invalid base address of decoder %d\n", j);
+			rc = -EINVAL;
+			goto err_dec_fini;
+		}
+	}
+
+	return 0;
+
+err_dec_fini:
+	hl_dec_fini(hdev);
+
+	return rc;
+}
+
+void hl_dec_ctx_fini(struct hl_ctx *ctx)
+{
+	struct hl_device *hdev = ctx->hdev;
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct hl_dec *dec;
+	int j;
+
+	for (j = 0 ; j < prop->max_dec ; j++) {
+		if (!!(prop->decoder_enabled_mask & BIT(j))) {
+			dec = hdev->dec + j;
+			/* Stop the decoder */
+			WREG32(dec->base_addr + VCMD_CONTROL_OFFSET, 0);
+		}
+	}
+}
diff --git a/drivers/accel/habanalabs/common/device.c b/drivers/accel/habanalabs/common/device.c
new file mode 100644
index 000000000000..999c92d7036e
--- /dev/null
+++ b/drivers/accel/habanalabs/common/device.c
@@ -0,0 +1,2968 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Copyright 2016-2022 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ */
+
+#define pr_fmt(fmt)			"habanalabs: " fmt
+
+#include <uapi/drm/habanalabs_accel.h>
+#include "habanalabs.h"
+
+#include <linux/pci.h>
+#include <linux/hwmon.h>
+#include <linux/vmalloc.h>
+
+#include <drm/drm_accel.h>
+#include <drm/drm_drv.h>
+
+#include <trace/events/habanalabs.h>
+
+#define HL_RESET_DELAY_USEC			10000	/* 10ms */
+
+#define HL_DEVICE_RELEASE_WATCHDOG_TIMEOUT_SEC	30
+
+enum dma_alloc_type {
+	DMA_ALLOC_COHERENT,
+	DMA_ALLOC_POOL,
+};
+
+#define MEM_SCRUB_DEFAULT_VAL 0x1122334455667788
+
+static void hl_device_heartbeat(struct work_struct *work);
+
+/*
+ * hl_set_dram_bar- sets the bar to allow later access to address
+ *
+ * @hdev: pointer to habanalabs device structure.
+ * @addr: the address the caller wants to access.
+ * @region: the PCI region.
+ * @new_bar_region_base: the new BAR region base address.
+ *
+ * @return: the old BAR base address on success, U64_MAX for failure.
+ *	    The caller should set it back to the old address after use.
+ *
+ * In case the bar space does not cover the whole address space,
+ * the bar base address should be set to allow access to a given address.
+ * This function can be called also if the bar doesn't need to be set,
+ * in that case it just won't change the base.
+ */
+static u64 hl_set_dram_bar(struct hl_device *hdev, u64 addr, struct pci_mem_region *region,
+				u64 *new_bar_region_base)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	u64 bar_base_addr, old_base;
+
+	if (is_power_of_2(prop->dram_pci_bar_size))
+		bar_base_addr = addr & ~(prop->dram_pci_bar_size - 0x1ull);
+	else
+		bar_base_addr = region->region_base +
+				div64_u64((addr - region->region_base), prop->dram_pci_bar_size) *
+				prop->dram_pci_bar_size;
+
+	old_base = hdev->asic_funcs->set_dram_bar_base(hdev, bar_base_addr);
+
+	/* in case of success we need to update the new BAR base */
+	if ((old_base != U64_MAX) && new_bar_region_base)
+		*new_bar_region_base = bar_base_addr;
+
+	return old_base;
+}
+
+int hl_access_sram_dram_region(struct hl_device *hdev, u64 addr, u64 *val,
+	enum debugfs_access_type acc_type, enum pci_region region_type, bool set_dram_bar)
+{
+	struct pci_mem_region *region = &hdev->pci_mem_region[region_type];
+	u64 old_base = 0, rc, bar_region_base = region->region_base;
+	void __iomem *acc_addr;
+
+	if (set_dram_bar) {
+		old_base = hl_set_dram_bar(hdev, addr, region, &bar_region_base);
+		if (old_base == U64_MAX)
+			return -EIO;
+	}
+
+	acc_addr = hdev->pcie_bar[region->bar_id] + region->offset_in_bar +
+			(addr - bar_region_base);
+
+	switch (acc_type) {
+	case DEBUGFS_READ8:
+		*val = readb(acc_addr);
+		break;
+	case DEBUGFS_WRITE8:
+		writeb(*val, acc_addr);
+		break;
+	case DEBUGFS_READ32:
+		*val = readl(acc_addr);
+		break;
+	case DEBUGFS_WRITE32:
+		writel(*val, acc_addr);
+		break;
+	case DEBUGFS_READ64:
+		*val = readq(acc_addr);
+		break;
+	case DEBUGFS_WRITE64:
+		writeq(*val, acc_addr);
+		break;
+	}
+
+	if (set_dram_bar) {
+		rc = hl_set_dram_bar(hdev, old_base, region, NULL);
+		if (rc == U64_MAX)
+			return -EIO;
+	}
+
+	return 0;
+}
+
+static void *hl_dma_alloc_common(struct hl_device *hdev, size_t size, dma_addr_t *dma_handle,
+					gfp_t flag, enum dma_alloc_type alloc_type,
+					const char *caller)
+{
+	void *ptr = NULL;
+
+	switch (alloc_type) {
+	case DMA_ALLOC_COHERENT:
+		ptr = hdev->asic_funcs->asic_dma_alloc_coherent(hdev, size, dma_handle, flag);
+		break;
+	case DMA_ALLOC_POOL:
+		ptr = hdev->asic_funcs->asic_dma_pool_zalloc(hdev, size, flag, dma_handle);
+		break;
+	}
+
+	if (trace_habanalabs_dma_alloc_enabled() && !ZERO_OR_NULL_PTR(ptr))
+		trace_habanalabs_dma_alloc(&(hdev)->pdev->dev, (u64) (uintptr_t) ptr, *dma_handle,
+						size, caller);
+
+	return ptr;
+}
+
+static void hl_asic_dma_free_common(struct hl_device *hdev, size_t size, void *cpu_addr,
+					dma_addr_t dma_handle, enum dma_alloc_type alloc_type,
+					const char *caller)
+{
+	/* this is needed to avoid warning on using freed pointer */
+	u64 store_cpu_addr = (u64) (uintptr_t) cpu_addr;
+
+	switch (alloc_type) {
+	case DMA_ALLOC_COHERENT:
+		hdev->asic_funcs->asic_dma_free_coherent(hdev, size, cpu_addr, dma_handle);
+		break;
+	case DMA_ALLOC_POOL:
+		hdev->asic_funcs->asic_dma_pool_free(hdev, cpu_addr, dma_handle);
+		break;
+	}
+
+	trace_habanalabs_dma_free(&(hdev)->pdev->dev, store_cpu_addr, dma_handle, size, caller);
+}
+
+void *hl_asic_dma_alloc_coherent_caller(struct hl_device *hdev, size_t size, dma_addr_t *dma_handle,
+					gfp_t flag, const char *caller)
+{
+	return hl_dma_alloc_common(hdev, size, dma_handle, flag, DMA_ALLOC_COHERENT, caller);
+}
+
+void hl_asic_dma_free_coherent_caller(struct hl_device *hdev, size_t size, void *cpu_addr,
+					dma_addr_t dma_handle, const char *caller)
+{
+	hl_asic_dma_free_common(hdev, size, cpu_addr, dma_handle, DMA_ALLOC_COHERENT, caller);
+}
+
+void *hl_asic_dma_pool_zalloc_caller(struct hl_device *hdev, size_t size, gfp_t mem_flags,
+					dma_addr_t *dma_handle, const char *caller)
+{
+	return hl_dma_alloc_common(hdev, size, dma_handle, mem_flags, DMA_ALLOC_POOL, caller);
+}
+
+void hl_asic_dma_pool_free_caller(struct hl_device *hdev, void *vaddr, dma_addr_t dma_addr,
+					const char *caller)
+{
+	hl_asic_dma_free_common(hdev, 0, vaddr, dma_addr, DMA_ALLOC_POOL, caller);
+}
+
+void *hl_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, size_t size, dma_addr_t *dma_handle)
+{
+	return hdev->asic_funcs->cpu_accessible_dma_pool_alloc(hdev, size, dma_handle);
+}
+
+void hl_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size, void *vaddr)
+{
+	hdev->asic_funcs->cpu_accessible_dma_pool_free(hdev, size, vaddr);
+}
+
+int hl_dma_map_sgtable_caller(struct hl_device *hdev, struct sg_table *sgt,
+				enum dma_data_direction dir, const char *caller)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct scatterlist *sg;
+	int rc, i;
+
+	rc = hdev->asic_funcs->dma_map_sgtable(hdev, sgt, dir);
+	if (rc)
+		return rc;
+
+	if (!trace_habanalabs_dma_map_page_enabled())
+		return 0;
+
+	for_each_sgtable_dma_sg(sgt, sg, i)
+		trace_habanalabs_dma_map_page(&(hdev)->pdev->dev,
+					page_to_phys(sg_page(sg)),
+					sg->dma_address - prop->device_dma_offset_for_host_access,
+#ifdef CONFIG_NEED_SG_DMA_LENGTH
+					sg->dma_length,
+#else
+					sg->length,
+#endif
+					dir, caller);
+
+	return 0;
+}
+
+int hl_asic_dma_map_sgtable(struct hl_device *hdev, struct sg_table *sgt,
+				enum dma_data_direction dir)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct scatterlist *sg;
+	int rc, i;
+
+	rc = dma_map_sgtable(&hdev->pdev->dev, sgt, dir, 0);
+	if (rc)
+		return rc;
+
+	/* Shift to the device's base physical address of host memory if necessary */
+	if (prop->device_dma_offset_for_host_access)
+		for_each_sgtable_dma_sg(sgt, sg, i)
+			sg->dma_address += prop->device_dma_offset_for_host_access;
+
+	return 0;
+}
+
+void hl_dma_unmap_sgtable_caller(struct hl_device *hdev, struct sg_table *sgt,
+					enum dma_data_direction dir, const char *caller)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct scatterlist *sg;
+	int i;
+
+	hdev->asic_funcs->dma_unmap_sgtable(hdev, sgt, dir);
+
+	if (trace_habanalabs_dma_unmap_page_enabled()) {
+		for_each_sgtable_dma_sg(sgt, sg, i)
+			trace_habanalabs_dma_unmap_page(&(hdev)->pdev->dev,
+					page_to_phys(sg_page(sg)),
+					sg->dma_address - prop->device_dma_offset_for_host_access,
+#ifdef CONFIG_NEED_SG_DMA_LENGTH
+					sg->dma_length,
+#else
+					sg->length,
+#endif
+					dir, caller);
+	}
+}
+
+void hl_asic_dma_unmap_sgtable(struct hl_device *hdev, struct sg_table *sgt,
+				enum dma_data_direction dir)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct scatterlist *sg;
+	int i;
+
+	/* Cancel the device's base physical address of host memory if necessary */
+	if (prop->device_dma_offset_for_host_access)
+		for_each_sgtable_dma_sg(sgt, sg, i)
+			sg->dma_address -= prop->device_dma_offset_for_host_access;
+
+	dma_unmap_sgtable(&hdev->pdev->dev, sgt, dir, 0);
+}
+
+/*
+ * hl_access_cfg_region - access the config region
+ *
+ * @hdev: pointer to habanalabs device structure
+ * @addr: the address to access
+ * @val: the value to write from or read to
+ * @acc_type: the type of access (read/write 64/32)
+ */
+int hl_access_cfg_region(struct hl_device *hdev, u64 addr, u64 *val,
+	enum debugfs_access_type acc_type)
+{
+	struct pci_mem_region *cfg_region = &hdev->pci_mem_region[PCI_REGION_CFG];
+	u32 val_h, val_l;
+
+	if (!IS_ALIGNED(addr, sizeof(u32))) {
+		dev_err(hdev->dev, "address %#llx not a multiple of %zu\n", addr, sizeof(u32));
+		return -EINVAL;
+	}
+
+	switch (acc_type) {
+	case DEBUGFS_READ32:
+		*val = RREG32(addr - cfg_region->region_base);
+		break;
+	case DEBUGFS_WRITE32:
+		WREG32(addr - cfg_region->region_base, *val);
+		break;
+	case DEBUGFS_READ64:
+		val_l = RREG32(addr - cfg_region->region_base);
+		val_h = RREG32(addr + sizeof(u32) - cfg_region->region_base);
+
+		*val = (((u64) val_h) << 32) | val_l;
+		break;
+	case DEBUGFS_WRITE64:
+		WREG32(addr - cfg_region->region_base, lower_32_bits(*val));
+		WREG32(addr + sizeof(u32) - cfg_region->region_base, upper_32_bits(*val));
+		break;
+	default:
+		dev_err(hdev->dev, "access type %d is not supported\n", acc_type);
+		return -EOPNOTSUPP;
+	}
+
+	return 0;
+}
+
+/*
+ * hl_access_dev_mem - access device memory
+ *
+ * @hdev: pointer to habanalabs device structure
+ * @region_type: the type of the region the address belongs to
+ * @addr: the address to access
+ * @val: the value to write from or read to
+ * @acc_type: the type of access (r/w, 32/64)
+ */
+int hl_access_dev_mem(struct hl_device *hdev, enum pci_region region_type,
+			u64 addr, u64 *val, enum debugfs_access_type acc_type)
+{
+	switch (region_type) {
+	case PCI_REGION_CFG:
+		return hl_access_cfg_region(hdev, addr, val, acc_type);
+	case PCI_REGION_SRAM:
+	case PCI_REGION_DRAM:
+		return hl_access_sram_dram_region(hdev, addr, val, acc_type,
+				region_type, (region_type == PCI_REGION_DRAM));
+	default:
+		return -EFAULT;
+	}
+
+	return 0;
+}
+
+void hl_engine_data_sprintf(struct engines_data *e, const char *fmt, ...)
+{
+	va_list args;
+	int str_size;
+
+	va_start(args, fmt);
+	/* Calculate formatted string length. Assuming each string is null terminated, hence
+	 * increment result by 1
+	 */
+	str_size = vsnprintf(NULL, 0, fmt, args) + 1;
+	va_end(args);
+
+	if ((e->actual_size + str_size) < e->allocated_buf_size) {
+		va_start(args, fmt);
+		vsnprintf(e->buf + e->actual_size, str_size, fmt, args);
+		va_end(args);
+	}
+
+	/* Need to update the size even when not updating destination buffer to get the exact size
+	 * of all input strings
+	 */
+	e->actual_size += str_size;
+}
+
+enum hl_device_status hl_device_status(struct hl_device *hdev)
+{
+	enum hl_device_status status;
+
+	if (hdev->device_fini_pending) {
+		status = HL_DEVICE_STATUS_MALFUNCTION;
+	} else if (hdev->reset_info.in_reset) {
+		if (hdev->reset_info.in_compute_reset)
+			status = HL_DEVICE_STATUS_IN_RESET_AFTER_DEVICE_RELEASE;
+		else
+			status = HL_DEVICE_STATUS_IN_RESET;
+	} else if (hdev->reset_info.needs_reset) {
+		status = HL_DEVICE_STATUS_NEEDS_RESET;
+	} else if (hdev->disabled) {
+		status = HL_DEVICE_STATUS_MALFUNCTION;
+	} else if (!hdev->init_done) {
+		status = HL_DEVICE_STATUS_IN_DEVICE_CREATION;
+	} else {
+		status = HL_DEVICE_STATUS_OPERATIONAL;
+	}
+
+	return status;
+}
+
+bool hl_device_operational(struct hl_device *hdev,
+		enum hl_device_status *status)
+{
+	enum hl_device_status current_status;
+
+	current_status = hl_device_status(hdev);
+	if (status)
+		*status = current_status;
+
+	switch (current_status) {
+	case HL_DEVICE_STATUS_MALFUNCTION:
+	case HL_DEVICE_STATUS_IN_RESET:
+	case HL_DEVICE_STATUS_IN_RESET_AFTER_DEVICE_RELEASE:
+	case HL_DEVICE_STATUS_NEEDS_RESET:
+		return false;
+	case HL_DEVICE_STATUS_OPERATIONAL:
+	case HL_DEVICE_STATUS_IN_DEVICE_CREATION:
+	default:
+		return true;
+	}
+}
+
+bool hl_ctrl_device_operational(struct hl_device *hdev,
+		enum hl_device_status *status)
+{
+	enum hl_device_status current_status;
+
+	current_status = hl_device_status(hdev);
+	if (status)
+		*status = current_status;
+
+	switch (current_status) {
+	case HL_DEVICE_STATUS_MALFUNCTION:
+		return false;
+	case HL_DEVICE_STATUS_IN_RESET:
+	case HL_DEVICE_STATUS_IN_RESET_AFTER_DEVICE_RELEASE:
+	case HL_DEVICE_STATUS_NEEDS_RESET:
+	case HL_DEVICE_STATUS_OPERATIONAL:
+	case HL_DEVICE_STATUS_IN_DEVICE_CREATION:
+	default:
+		return true;
+	}
+}
+
+static void print_idle_status_mask(struct hl_device *hdev, const char *message,
+					u64 idle_mask[HL_BUSY_ENGINES_MASK_EXT_SIZE])
+{
+	if (idle_mask[3])
+		dev_err(hdev->dev, "%s %s (mask %#llx_%016llx_%016llx_%016llx)\n",
+			dev_name(&hdev->pdev->dev), message,
+			idle_mask[3], idle_mask[2], idle_mask[1], idle_mask[0]);
+	else if (idle_mask[2])
+		dev_err(hdev->dev, "%s %s (mask %#llx_%016llx_%016llx)\n",
+			dev_name(&hdev->pdev->dev), message,
+			idle_mask[2], idle_mask[1], idle_mask[0]);
+	else if (idle_mask[1])
+		dev_err(hdev->dev, "%s %s (mask %#llx_%016llx)\n",
+			dev_name(&hdev->pdev->dev), message, idle_mask[1], idle_mask[0]);
+	else
+		dev_err(hdev->dev, "%s %s (mask %#llx)\n", dev_name(&hdev->pdev->dev), message,
+			idle_mask[0]);
+}
+
+static void hpriv_release(struct kref *ref)
+{
+	u64 idle_mask[HL_BUSY_ENGINES_MASK_EXT_SIZE] = {0};
+	bool reset_device, device_is_idle = true;
+	struct hl_fpriv *hpriv;
+	struct hl_device *hdev;
+
+	hpriv = container_of(ref, struct hl_fpriv, refcount);
+
+	hdev = hpriv->hdev;
+
+	hdev->asic_funcs->send_device_activity(hdev, false);
+
+	hl_debugfs_remove_file(hpriv);
+
+	mutex_destroy(&hpriv->ctx_lock);
+	mutex_destroy(&hpriv->restore_phase_mutex);
+
+	/* There should be no memory buffers at this point and handles IDR can be destroyed */
+	hl_mem_mgr_idr_destroy(&hpriv->mem_mgr);
+
+	/* Device should be reset if reset-upon-device-release is enabled, or if there is a pending
+	 * reset that waits for device release.
+	 */
+	reset_device = hdev->reset_upon_device_release || hdev->reset_info.watchdog_active;
+
+	/* Check the device idle status and reset if not idle.
+	 * Skip it if already in reset, or if device is going to be reset in any case.
+	 */
+	if (!hdev->reset_info.in_reset && !reset_device && !hdev->pldm)
+		device_is_idle = hdev->asic_funcs->is_device_idle(hdev, idle_mask,
+							HL_BUSY_ENGINES_MASK_EXT_SIZE, NULL);
+	if (!device_is_idle) {
+		print_idle_status_mask(hdev, "device is not idle after user context is closed",
+					idle_mask);
+		reset_device = true;
+	}
+
+	/* We need to remove the user from the list to make sure the reset process won't
+	 * try to kill the user process. Because, if we got here, it means there are no
+	 * more driver/device resources that the user process is occupying so there is
+	 * no need to kill it
+	 *
+	 * However, we can't set the compute_ctx to NULL at this stage. This is to prevent
+	 * a race between the release and opening the device again. We don't want to let
+	 * a user open the device while there a reset is about to happen.
+	 */
+	mutex_lock(&hdev->fpriv_list_lock);
+	list_del(&hpriv->dev_node);
+	mutex_unlock(&hdev->fpriv_list_lock);
+
+	put_pid(hpriv->taskpid);
+
+	if (reset_device) {
+		hl_device_reset(hdev, HL_DRV_RESET_DEV_RELEASE);
+	} else {
+		/* Scrubbing is handled within hl_device_reset(), so here need to do it directly */
+		int rc = hdev->asic_funcs->scrub_device_mem(hdev);
+
+		if (rc) {
+			dev_err(hdev->dev, "failed to scrub memory from hpriv release (%d)\n", rc);
+			hl_device_reset(hdev, HL_DRV_RESET_HARD);
+		}
+	}
+
+	/* Now we can mark the compute_ctx as not active. Even if a reset is running in a different
+	 * thread, we don't care because the in_reset is marked so if a user will try to open
+	 * the device it will fail on that, even if compute_ctx is false.
+	 */
+	mutex_lock(&hdev->fpriv_list_lock);
+	hdev->is_compute_ctx_active = false;
+	mutex_unlock(&hdev->fpriv_list_lock);
+
+	hdev->compute_ctx_in_release = 0;
+
+	/* release the eventfd */
+	if (hpriv->notifier_event.eventfd)
+		eventfd_ctx_put(hpriv->notifier_event.eventfd);
+
+	mutex_destroy(&hpriv->notifier_event.lock);
+
+	kfree(hpriv);
+}
+
+void hl_hpriv_get(struct hl_fpriv *hpriv)
+{
+	kref_get(&hpriv->refcount);
+}
+
+int hl_hpriv_put(struct hl_fpriv *hpriv)
+{
+	return kref_put(&hpriv->refcount, hpriv_release);
+}
+
+static void print_device_in_use_info(struct hl_device *hdev,
+		struct hl_mem_mgr_fini_stats *mm_fini_stats, const char *message)
+{
+	u32 active_cs_num, dmabuf_export_cnt;
+	bool unknown_reason = true;
+	char buf[128];
+	size_t size;
+	int offset;
+
+	size = sizeof(buf);
+	offset = 0;
+
+	active_cs_num = hl_get_active_cs_num(hdev);
+	if (active_cs_num) {
+		unknown_reason = false;
+		offset += scnprintf(buf + offset, size - offset, " [%u active CS]", active_cs_num);
+	}
+
+	dmabuf_export_cnt = atomic_read(&hdev->dmabuf_export_cnt);
+	if (dmabuf_export_cnt) {
+		unknown_reason = false;
+		offset += scnprintf(buf + offset, size - offset, " [%u exported dma-buf]",
+					dmabuf_export_cnt);
+	}
+
+	if (mm_fini_stats->n_busy_cb) {
+		unknown_reason = false;
+		offset += scnprintf(buf + offset, size - offset, " [%u live CB handles]",
+				mm_fini_stats->n_busy_cb);
+	}
+
+	if (unknown_reason)
+		scnprintf(buf + offset, size - offset, " [unknown reason]");
+
+	dev_notice(hdev->dev, "%s%s\n", message, buf);
+}
+
+/*
+ * hl_device_release() - release function for habanalabs device.
+ * @ddev: pointer to DRM device structure.
+ * @file: pointer to DRM file private data structure.
+ *
+ * Called when process closes an habanalabs device
+ */
+void hl_device_release(struct drm_device *ddev, struct drm_file *file_priv)
+{
+	struct hl_fpriv *hpriv = file_priv->driver_priv;
+	struct hl_device *hdev = to_hl_device(ddev);
+	struct hl_mem_mgr_fini_stats mm_fini_stats;
+
+	if (!hdev) {
+		pr_crit("Closing FD after device was removed. Memory leak will occur and it is advised to reboot.\n");
+		put_pid(hpriv->taskpid);
+	}
+
+	hl_ctx_mgr_fini(hdev, &hpriv->ctx_mgr);
+
+	/* Memory buffers might be still in use at this point and thus the handles IDR destruction
+	 * is postponed to hpriv_release().
+	 */
+	hl_mem_mgr_fini(&hpriv->mem_mgr, &mm_fini_stats);
+
+	hdev->compute_ctx_in_release = 1;
+
+	if (!hl_hpriv_put(hpriv)) {
+		print_device_in_use_info(hdev, &mm_fini_stats,
+				"User process closed FD but device still in use");
+		hl_device_reset(hdev, HL_DRV_RESET_HARD);
+	}
+
+	hdev->last_open_session_duration_jif = jiffies - hdev->last_successful_open_jif;
+}
+
+static int hl_device_release_ctrl(struct inode *inode, struct file *filp)
+{
+	struct hl_fpriv *hpriv = filp->private_data;
+	struct hl_device *hdev = hpriv->hdev;
+
+	filp->private_data = NULL;
+
+	if (!hdev) {
+		pr_err("Closing FD after device was removed\n");
+		goto out;
+	}
+
+	mutex_lock(&hdev->fpriv_ctrl_list_lock);
+	list_del(&hpriv->dev_node);
+	mutex_unlock(&hdev->fpriv_ctrl_list_lock);
+out:
+	put_pid(hpriv->taskpid);
+
+	kfree(hpriv);
+
+	return 0;
+}
+
+static int __hl_mmap(struct hl_fpriv *hpriv, struct vm_area_struct *vma)
+{
+	struct hl_device *hdev = hpriv->hdev;
+	unsigned long vm_pgoff;
+
+	if (!hdev) {
+		pr_err_ratelimited("Trying to mmap after device was removed! Please close FD\n");
+		return -ENODEV;
+	}
+
+	vm_pgoff = vma->vm_pgoff;
+
+	switch (vm_pgoff & HL_MMAP_TYPE_MASK) {
+	case HL_MMAP_TYPE_BLOCK:
+		vma->vm_pgoff = HL_MMAP_OFFSET_VALUE_GET(vm_pgoff);
+		return hl_hw_block_mmap(hpriv, vma);
+
+	case HL_MMAP_TYPE_CB:
+	case HL_MMAP_TYPE_TS_BUFF:
+		return hl_mem_mgr_mmap(&hpriv->mem_mgr, vma, NULL);
+	}
+	return -EINVAL;
+}
+
+/*
+ * hl_mmap - mmap function for habanalabs device
+ *
+ * @*filp: pointer to file structure
+ * @*vma: pointer to vm_area_struct of the process
+ *
+ * Called when process does an mmap on habanalabs device. Call the relevant mmap
+ * function at the end of the common code.
+ */
+int hl_mmap(struct file *filp, struct vm_area_struct *vma)
+{
+	struct drm_file *file_priv = filp->private_data;
+	struct hl_fpriv *hpriv = file_priv->driver_priv;
+
+	return __hl_mmap(hpriv, vma);
+}
+
+static const struct file_operations hl_ctrl_ops = {
+	.owner = THIS_MODULE,
+	.open = hl_device_open_ctrl,
+	.release = hl_device_release_ctrl,
+	.unlocked_ioctl = hl_ioctl_control,
+	.compat_ioctl = hl_ioctl_control
+};
+
+static void device_release_func(struct device *dev)
+{
+	kfree(dev);
+}
+
+/*
+ * device_init_cdev - Initialize cdev and device for habanalabs device
+ *
+ * @hdev: pointer to habanalabs device structure
+ * @class: pointer to the class object of the device
+ * @minor: minor number of the specific device
+ * @fops: file operations to install for this device
+ * @name: name of the device as it will appear in the filesystem
+ * @cdev: pointer to the char device object that will be initialized
+ * @dev: pointer to the device object that will be initialized
+ *
+ * Initialize a cdev and a Linux device for habanalabs's device.
+ */
+static int device_init_cdev(struct hl_device *hdev, const struct class *class,
+				int minor, const struct file_operations *fops,
+				char *name, struct cdev *cdev,
+				struct device **dev)
+{
+	cdev_init(cdev, fops);
+	cdev->owner = THIS_MODULE;
+
+	*dev = kzalloc(sizeof(**dev), GFP_KERNEL);
+	if (!*dev)
+		return -ENOMEM;
+
+	device_initialize(*dev);
+	(*dev)->devt = MKDEV(hdev->major, minor);
+	(*dev)->class = class;
+	(*dev)->release = device_release_func;
+	dev_set_drvdata(*dev, hdev);
+	dev_set_name(*dev, "%s", name);
+
+	return 0;
+}
+
+static int cdev_sysfs_debugfs_add(struct hl_device *hdev)
+{
+	const struct class *accel_class = hdev->drm.accel->kdev->class;
+	char name[32];
+	int rc;
+
+	hdev->cdev_idx = hdev->drm.accel->index;
+
+	/* Initialize cdev and device structures for the control device */
+	snprintf(name, sizeof(name), "accel_controlD%d", hdev->cdev_idx);
+	rc = device_init_cdev(hdev, accel_class, hdev->cdev_idx, &hl_ctrl_ops, name,
+				&hdev->cdev_ctrl, &hdev->dev_ctrl);
+	if (rc)
+		return rc;
+
+	rc = cdev_device_add(&hdev->cdev_ctrl, hdev->dev_ctrl);
+	if (rc) {
+		dev_err(hdev->dev_ctrl,
+			"failed to add an accel control char device to the system\n");
+		goto free_ctrl_device;
+	}
+
+	rc = hl_sysfs_init(hdev);
+	if (rc) {
+		dev_err(hdev->dev, "failed to initialize sysfs\n");
+		goto delete_ctrl_cdev_device;
+	}
+
+	hl_debugfs_add_device(hdev);
+
+	hdev->cdev_sysfs_debugfs_created = true;
+
+	return 0;
+
+delete_ctrl_cdev_device:
+	cdev_device_del(&hdev->cdev_ctrl, hdev->dev_ctrl);
+free_ctrl_device:
+	put_device(hdev->dev_ctrl);
+	return rc;
+}
+
+static void cdev_sysfs_debugfs_remove(struct hl_device *hdev)
+{
+	if (!hdev->cdev_sysfs_debugfs_created)
+		return;
+
+	hl_sysfs_fini(hdev);
+
+	cdev_device_del(&hdev->cdev_ctrl, hdev->dev_ctrl);
+	put_device(hdev->dev_ctrl);
+}
+
+static void device_hard_reset_pending(struct work_struct *work)
+{
+	struct hl_device_reset_work *device_reset_work =
+		container_of(work, struct hl_device_reset_work, reset_work.work);
+	struct hl_device *hdev = device_reset_work->hdev;
+	u32 flags;
+	int rc;
+
+	flags = device_reset_work->flags | HL_DRV_RESET_FROM_RESET_THR;
+
+	rc = hl_device_reset(hdev, flags);
+
+	if ((rc == -EBUSY) && !hdev->device_fini_pending) {
+		struct hl_ctx *ctx = hl_get_compute_ctx(hdev);
+
+		if (ctx) {
+			/* The read refcount value should subtracted by one, because the read is
+			 * protected with hl_get_compute_ctx().
+			 */
+			dev_info(hdev->dev,
+				"Could not reset device (compute_ctx refcount %u). will try again in %u seconds",
+				kref_read(&ctx->refcount) - 1, HL_PENDING_RESET_PER_SEC);
+			hl_ctx_put(ctx);
+		} else {
+			dev_info(hdev->dev, "Could not reset device. will try again in %u seconds",
+				HL_PENDING_RESET_PER_SEC);
+		}
+
+		queue_delayed_work(hdev->reset_wq, &device_reset_work->reset_work,
+					secs_to_jiffies(HL_PENDING_RESET_PER_SEC));
+	}
+}
+
+static void device_release_watchdog_func(struct work_struct *work)
+{
+	struct hl_device_reset_work *watchdog_work =
+			container_of(work, struct hl_device_reset_work, reset_work.work);
+	struct hl_device *hdev = watchdog_work->hdev;
+	u32 flags;
+
+	dev_dbg(hdev->dev, "Device wasn't released in time. Initiate hard-reset.\n");
+
+	flags = watchdog_work->flags | HL_DRV_RESET_HARD | HL_DRV_RESET_FROM_WD_THR;
+
+	hl_device_reset(hdev, flags);
+}
+
+/*
+ * device_early_init - do some early initialization for the habanalabs device
+ *
+ * @hdev: pointer to habanalabs device structure
+ *
+ * Install the relevant function pointers and call the early_init function,
+ * if such a function exists
+ */
+static int device_early_init(struct hl_device *hdev)
+{
+	int i, rc;
+	char workq_name[32];
+
+	switch (hdev->asic_type) {
+	case ASIC_GOYA:
+		goya_set_asic_funcs(hdev);
+		strscpy(hdev->asic_name, "GOYA", sizeof(hdev->asic_name));
+		break;
+	case ASIC_GAUDI:
+		gaudi_set_asic_funcs(hdev);
+		strscpy(hdev->asic_name, "GAUDI", sizeof(hdev->asic_name));
+		break;
+	case ASIC_GAUDI_SEC:
+		gaudi_set_asic_funcs(hdev);
+		strscpy(hdev->asic_name, "GAUDI SEC", sizeof(hdev->asic_name));
+		break;
+	case ASIC_GAUDI2:
+		gaudi2_set_asic_funcs(hdev);
+		strscpy(hdev->asic_name, "GAUDI2", sizeof(hdev->asic_name));
+		break;
+	case ASIC_GAUDI2B:
+		gaudi2_set_asic_funcs(hdev);
+		strscpy(hdev->asic_name, "GAUDI2B", sizeof(hdev->asic_name));
+		break;
+	case ASIC_GAUDI2C:
+		gaudi2_set_asic_funcs(hdev);
+		strscpy(hdev->asic_name, "GAUDI2C", sizeof(hdev->asic_name));
+		break;
+	case ASIC_GAUDI2D:
+		gaudi2_set_asic_funcs(hdev);
+		strscpy(hdev->asic_name, "GAUDI2D", sizeof(hdev->asic_name));
+		break;
+	default:
+		dev_err(hdev->dev, "Unrecognized ASIC type %d\n",
+			hdev->asic_type);
+		return -EINVAL;
+	}
+
+	rc = hdev->asic_funcs->early_init(hdev);
+	if (rc)
+		return rc;
+
+	rc = hl_asid_init(hdev);
+	if (rc)
+		goto early_fini;
+
+	if (hdev->asic_prop.completion_queues_count) {
+		hdev->cq_wq = kcalloc(hdev->asic_prop.completion_queues_count,
+				sizeof(struct workqueue_struct *),
+				GFP_KERNEL);
+		if (!hdev->cq_wq) {
+			rc = -ENOMEM;
+			goto asid_fini;
+		}
+	}
+
+	for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++) {
+		snprintf(workq_name, 32, "hl%u-free-jobs-%u", hdev->cdev_idx, (u32) i);
+		hdev->cq_wq[i] = create_singlethread_workqueue(workq_name);
+		if (hdev->cq_wq[i] == NULL) {
+			dev_err(hdev->dev, "Failed to allocate CQ workqueue\n");
+			rc = -ENOMEM;
+			goto free_cq_wq;
+		}
+	}
+
+	snprintf(workq_name, 32, "hl%u-events", hdev->cdev_idx);
+	hdev->eq_wq = create_singlethread_workqueue(workq_name);
+	if (hdev->eq_wq == NULL) {
+		dev_err(hdev->dev, "Failed to allocate EQ workqueue\n");
+		rc = -ENOMEM;
+		goto free_cq_wq;
+	}
+
+	snprintf(workq_name, 32, "hl%u-cs-completions", hdev->cdev_idx);
+	hdev->cs_cmplt_wq = alloc_workqueue(workq_name, WQ_UNBOUND, 0);
+	if (!hdev->cs_cmplt_wq) {
+		dev_err(hdev->dev,
+			"Failed to allocate CS completions workqueue\n");
+		rc = -ENOMEM;
+		goto free_eq_wq;
+	}
+
+	snprintf(workq_name, 32, "hl%u-ts-free-obj", hdev->cdev_idx);
+	hdev->ts_free_obj_wq = alloc_workqueue(workq_name, WQ_UNBOUND, 0);
+	if (!hdev->ts_free_obj_wq) {
+		dev_err(hdev->dev,
+			"Failed to allocate Timestamp registration free workqueue\n");
+		rc = -ENOMEM;
+		goto free_cs_cmplt_wq;
+	}
+
+	snprintf(workq_name, 32, "hl%u-prefetch", hdev->cdev_idx);
+	hdev->prefetch_wq = alloc_workqueue(workq_name, WQ_UNBOUND, 0);
+	if (!hdev->prefetch_wq) {
+		dev_err(hdev->dev, "Failed to allocate MMU prefetch workqueue\n");
+		rc = -ENOMEM;
+		goto free_ts_free_wq;
+	}
+
+	hdev->hl_chip_info = kzalloc(sizeof(struct hwmon_chip_info), GFP_KERNEL);
+	if (!hdev->hl_chip_info) {
+		rc = -ENOMEM;
+		goto free_prefetch_wq;
+	}
+
+	rc = hl_mmu_if_set_funcs(hdev);
+	if (rc)
+		goto free_chip_info;
+
+	hl_mem_mgr_init(hdev->dev, &hdev->kernel_mem_mgr);
+
+	snprintf(workq_name, 32, "hl%u_device_reset", hdev->cdev_idx);
+	hdev->reset_wq = create_singlethread_workqueue(workq_name);
+	if (!hdev->reset_wq) {
+		rc = -ENOMEM;
+		dev_err(hdev->dev, "Failed to create device reset WQ\n");
+		goto free_cb_mgr;
+	}
+
+	INIT_DELAYED_WORK(&hdev->work_heartbeat, hl_device_heartbeat);
+
+	INIT_DELAYED_WORK(&hdev->device_reset_work.reset_work, device_hard_reset_pending);
+	hdev->device_reset_work.hdev = hdev;
+	hdev->device_fini_pending = 0;
+
+	INIT_DELAYED_WORK(&hdev->device_release_watchdog_work.reset_work,
+				device_release_watchdog_func);
+	hdev->device_release_watchdog_work.hdev = hdev;
+
+	mutex_init(&hdev->send_cpu_message_lock);
+	mutex_init(&hdev->debug_lock);
+	INIT_LIST_HEAD(&hdev->cs_mirror_list);
+	spin_lock_init(&hdev->cs_mirror_lock);
+	spin_lock_init(&hdev->reset_info.lock);
+	INIT_LIST_HEAD(&hdev->fpriv_list);
+	INIT_LIST_HEAD(&hdev->fpriv_ctrl_list);
+	mutex_init(&hdev->fpriv_list_lock);
+	mutex_init(&hdev->fpriv_ctrl_list_lock);
+	mutex_init(&hdev->clk_throttling.lock);
+
+	return 0;
+
+free_cb_mgr:
+	hl_mem_mgr_fini(&hdev->kernel_mem_mgr, NULL);
+	hl_mem_mgr_idr_destroy(&hdev->kernel_mem_mgr);
+free_chip_info:
+	kfree(hdev->hl_chip_info);
+free_prefetch_wq:
+	destroy_workqueue(hdev->prefetch_wq);
+free_ts_free_wq:
+	destroy_workqueue(hdev->ts_free_obj_wq);
+free_cs_cmplt_wq:
+	destroy_workqueue(hdev->cs_cmplt_wq);
+free_eq_wq:
+	destroy_workqueue(hdev->eq_wq);
+free_cq_wq:
+	for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++)
+		if (hdev->cq_wq[i])
+			destroy_workqueue(hdev->cq_wq[i]);
+	kfree(hdev->cq_wq);
+asid_fini:
+	hl_asid_fini(hdev);
+early_fini:
+	if (hdev->asic_funcs->early_fini)
+		hdev->asic_funcs->early_fini(hdev);
+
+	return rc;
+}
+
+/*
+ * device_early_fini - finalize all that was done in device_early_init
+ *
+ * @hdev: pointer to habanalabs device structure
+ *
+ */
+static void device_early_fini(struct hl_device *hdev)
+{
+	int i;
+
+	mutex_destroy(&hdev->debug_lock);
+	mutex_destroy(&hdev->send_cpu_message_lock);
+
+	mutex_destroy(&hdev->fpriv_list_lock);
+	mutex_destroy(&hdev->fpriv_ctrl_list_lock);
+
+	mutex_destroy(&hdev->clk_throttling.lock);
+
+	hl_mem_mgr_fini(&hdev->kernel_mem_mgr, NULL);
+	hl_mem_mgr_idr_destroy(&hdev->kernel_mem_mgr);
+
+	kfree(hdev->hl_chip_info);
+
+	destroy_workqueue(hdev->prefetch_wq);
+	destroy_workqueue(hdev->ts_free_obj_wq);
+	destroy_workqueue(hdev->cs_cmplt_wq);
+	destroy_workqueue(hdev->eq_wq);
+	destroy_workqueue(hdev->reset_wq);
+
+	for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++)
+		destroy_workqueue(hdev->cq_wq[i]);
+	kfree(hdev->cq_wq);
+
+	hl_asid_fini(hdev);
+
+	if (hdev->asic_funcs->early_fini)
+		hdev->asic_funcs->early_fini(hdev);
+}
+
+static bool is_pci_link_healthy(struct hl_device *hdev)
+{
+	u16 device_id;
+
+	if (!hdev->pdev)
+		return false;
+
+	pci_read_config_word(hdev->pdev, PCI_DEVICE_ID, &device_id);
+
+	return (device_id == hdev->pdev->device);
+}
+
+static bool hl_device_eq_heartbeat_received(struct hl_device *hdev)
+{
+	struct eq_heartbeat_debug_info *heartbeat_debug_info = &hdev->heartbeat_debug_info;
+	u32 cpu_q_id = heartbeat_debug_info->cpu_queue_id, pq_pi_mask = (HL_QUEUE_LENGTH << 1) - 1;
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+
+	if (!prop->cpucp_info.eq_health_check_supported)
+		return true;
+
+	if (!hdev->eq_heartbeat_received) {
+		dev_err(hdev->dev, "EQ heartbeat event was not received!\n");
+
+		dev_err(hdev->dev,
+			"EQ: {CI %u, HB counter %u, last HB time: %ptTs}, PQ: {PI: %u, CI: %u (%u), last HB time: %ptTs}\n",
+			hdev->event_queue.ci,
+			heartbeat_debug_info->heartbeat_event_counter,
+			&hdev->heartbeat_debug_info.last_eq_heartbeat_ts,
+			hdev->kernel_queues[cpu_q_id].pi,
+			atomic_read(&hdev->kernel_queues[cpu_q_id].ci),
+			atomic_read(&hdev->kernel_queues[cpu_q_id].ci) & pq_pi_mask,
+			&hdev->heartbeat_debug_info.last_pq_heartbeat_ts);
+
+		hl_eq_dump(hdev, &hdev->event_queue);
+
+		return false;
+	}
+
+	hdev->eq_heartbeat_received = false;
+
+	return true;
+}
+
+static void hl_device_heartbeat(struct work_struct *work)
+{
+	struct hl_device *hdev = container_of(work, struct hl_device,
+						work_heartbeat.work);
+	struct hl_info_fw_err_info info = {0};
+	u64 event_mask = HL_NOTIFIER_EVENT_DEVICE_RESET | HL_NOTIFIER_EVENT_DEVICE_UNAVAILABLE;
+
+	/* Start heartbeat checks only after driver has enabled events from FW */
+	if (!hl_device_operational(hdev, NULL) || !hdev->init_done)
+		goto reschedule;
+
+	/*
+	 * For EQ health check need to check if driver received the heartbeat eq event
+	 * in order to validate the eq is working.
+	 * Only if both the EQ is healthy and we managed to send the next heartbeat reschedule.
+	 */
+	if (hl_device_eq_heartbeat_received(hdev) && (!hdev->asic_funcs->send_heartbeat(hdev)))
+		goto reschedule;
+
+	if (hl_device_operational(hdev, NULL))
+		dev_err(hdev->dev, "Device heartbeat failed! PCI link is %s\n",
+			is_pci_link_healthy(hdev) ? "healthy" : "broken");
+
+	info.err_type = HL_INFO_FW_HEARTBEAT_ERR;
+	info.event_mask = &event_mask;
+	hl_handle_fw_err(hdev, &info);
+	hl_device_cond_reset(hdev, HL_DRV_RESET_HARD | HL_DRV_RESET_HEARTBEAT, event_mask);
+
+	return;
+
+reschedule:
+	/*
+	 * prev_reset_trigger tracks consecutive fatal h/w errors until first
+	 * heartbeat immediately post reset.
+	 * If control reached here, then at least one heartbeat work has been
+	 * scheduled since last reset/init cycle.
+	 * So if the device is not already in reset cycle, reset the flag
+	 * prev_reset_trigger as no reset occurred with HL_DRV_RESET_FW_FATAL_ERR
+	 * status for at least one heartbeat. From this point driver restarts
+	 * tracking future consecutive fatal errors.
+	 */
+	if (!hdev->reset_info.in_reset)
+		hdev->reset_info.prev_reset_trigger = HL_RESET_TRIGGER_DEFAULT;
+
+	schedule_delayed_work(&hdev->work_heartbeat,
+			usecs_to_jiffies(HL_HEARTBEAT_PER_USEC));
+}
+
+/*
+ * device_late_init - do late stuff initialization for the habanalabs device
+ *
+ * @hdev: pointer to habanalabs device structure
+ *
+ * Do stuff that either needs the device H/W queues to be active or needs
+ * to happen after all the rest of the initialization is finished
+ */
+static int device_late_init(struct hl_device *hdev)
+{
+	int rc;
+
+	if (hdev->asic_funcs->late_init) {
+		rc = hdev->asic_funcs->late_init(hdev);
+		if (rc) {
+			dev_err(hdev->dev,
+				"failed late initialization for the H/W\n");
+			return rc;
+		}
+	}
+
+	hdev->high_pll = hdev->asic_prop.high_pll;
+	hdev->late_init_done = true;
+
+	return 0;
+}
+
+/*
+ * device_late_fini - finalize all that was done in device_late_init
+ *
+ * @hdev: pointer to habanalabs device structure
+ *
+ */
+static void device_late_fini(struct hl_device *hdev)
+{
+	if (!hdev->late_init_done)
+		return;
+
+	if (hdev->asic_funcs->late_fini)
+		hdev->asic_funcs->late_fini(hdev);
+
+	hdev->late_init_done = false;
+}
+
+int hl_device_utilization(struct hl_device *hdev, u32 *utilization)
+{
+	u64 max_power, curr_power, dc_power, dividend, divisor;
+	int rc;
+
+	max_power = hdev->max_power;
+	dc_power = hdev->asic_prop.dc_power_default;
+	divisor = max_power - dc_power;
+	if (!divisor) {
+		dev_warn(hdev->dev, "device utilization is not supported\n");
+		return -EOPNOTSUPP;
+	}
+	rc = hl_fw_cpucp_power_get(hdev, &curr_power);
+
+	if (rc)
+		return rc;
+
+	curr_power = clamp(curr_power, dc_power, max_power);
+
+	dividend = (curr_power - dc_power) * 100;
+	*utilization = (u32) div_u64(dividend, divisor);
+
+	return 0;
+}
+
+int hl_device_set_debug_mode(struct hl_device *hdev, struct hl_ctx *ctx, bool enable)
+{
+	int rc = 0;
+
+	mutex_lock(&hdev->debug_lock);
+
+	if (!enable) {
+		if (!hdev->in_debug) {
+			dev_err(hdev->dev,
+				"Failed to disable debug mode because device was not in debug mode\n");
+			rc = -EFAULT;
+			goto out;
+		}
+
+		if (!hdev->reset_info.hard_reset_pending)
+			hdev->asic_funcs->halt_coresight(hdev, ctx);
+
+		hdev->in_debug = 0;
+
+		goto out;
+	}
+
+	if (hdev->in_debug) {
+		dev_err(hdev->dev,
+			"Failed to enable debug mode because device is already in debug mode\n");
+		rc = -EFAULT;
+		goto out;
+	}
+
+	hdev->in_debug = 1;
+
+out:
+	mutex_unlock(&hdev->debug_lock);
+
+	return rc;
+}
+
+static void take_release_locks(struct hl_device *hdev)
+{
+	/* Flush anyone that is inside the critical section of enqueue
+	 * jobs to the H/W
+	 */
+	hdev->asic_funcs->hw_queues_lock(hdev);
+	hdev->asic_funcs->hw_queues_unlock(hdev);
+
+	/* Flush processes that are sending message to CPU */
+	mutex_lock(&hdev->send_cpu_message_lock);
+	mutex_unlock(&hdev->send_cpu_message_lock);
+
+	/* Flush anyone that is inside device open */
+	mutex_lock(&hdev->fpriv_list_lock);
+	mutex_unlock(&hdev->fpriv_list_lock);
+	mutex_lock(&hdev->fpriv_ctrl_list_lock);
+	mutex_unlock(&hdev->fpriv_ctrl_list_lock);
+}
+
+static void hl_abort_waiting_for_completions(struct hl_device *hdev)
+{
+	hl_abort_waiting_for_cs_completions(hdev);
+
+	/* Release all pending user interrupts, each pending user interrupt
+	 * holds a reference to a user context.
+	 */
+	hl_release_pending_user_interrupts(hdev);
+}
+
+static void cleanup_resources(struct hl_device *hdev, bool hard_reset, bool fw_reset,
+				bool skip_wq_flush)
+{
+	if (hard_reset) {
+		if (hdev->heartbeat)
+			cancel_delayed_work_sync(&hdev->work_heartbeat);
+
+		device_late_fini(hdev);
+	}
+
+	/*
+	 * Halt the engines and disable interrupts so we won't get any more
+	 * completions from H/W and we won't have any accesses from the
+	 * H/W to the host machine
+	 */
+	hdev->asic_funcs->halt_engines(hdev, hard_reset, fw_reset);
+
+	/* Go over all the queues, release all CS and their jobs */
+	hl_cs_rollback_all(hdev, skip_wq_flush);
+
+	/* flush the MMU prefetch workqueue */
+	flush_workqueue(hdev->prefetch_wq);
+
+	hl_abort_waiting_for_completions(hdev);
+}
+
+/*
+ * hl_device_suspend - initiate device suspend
+ *
+ * @hdev: pointer to habanalabs device structure
+ *
+ * Puts the hw in the suspend state (all asics).
+ * Returns 0 for success or an error on failure.
+ * Called at driver suspend.
+ */
+int hl_device_suspend(struct hl_device *hdev)
+{
+	int rc;
+
+	pci_save_state(hdev->pdev);
+
+	/* Block future CS/VM/JOB completion operations */
+	spin_lock(&hdev->reset_info.lock);
+	if (hdev->reset_info.in_reset) {
+		spin_unlock(&hdev->reset_info.lock);
+		dev_err(hdev->dev, "Can't suspend while in reset\n");
+		return -EIO;
+	}
+	hdev->reset_info.in_reset = 1;
+	spin_unlock(&hdev->reset_info.lock);
+
+	/* This blocks all other stuff that is not blocked by in_reset */
+	hdev->disabled = true;
+
+	take_release_locks(hdev);
+
+	rc = hdev->asic_funcs->suspend(hdev);
+	if (rc)
+		dev_err(hdev->dev,
+			"Failed to disable PCI access of device CPU\n");
+
+	/* Shut down the device */
+	pci_disable_device(hdev->pdev);
+	pci_set_power_state(hdev->pdev, PCI_D3hot);
+
+	return 0;
+}
+
+/*
+ * hl_device_resume - initiate device resume
+ *
+ * @hdev: pointer to habanalabs device structure
+ *
+ * Bring the hw back to operating state (all asics).
+ * Returns 0 for success or an error on failure.
+ * Called at driver resume.
+ */
+int hl_device_resume(struct hl_device *hdev)
+{
+	int rc;
+
+	pci_set_power_state(hdev->pdev, PCI_D0);
+	pci_restore_state(hdev->pdev);
+	rc = pci_enable_device_mem(hdev->pdev);
+	if (rc) {
+		dev_err(hdev->dev,
+			"Failed to enable PCI device in resume\n");
+		return rc;
+	}
+
+	pci_set_master(hdev->pdev);
+
+	rc = hdev->asic_funcs->resume(hdev);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to resume device after suspend\n");
+		goto disable_device;
+	}
+
+
+	/* 'in_reset' was set to true during suspend, now we must clear it in order
+	 * for hard reset to be performed
+	 */
+	spin_lock(&hdev->reset_info.lock);
+	hdev->reset_info.in_reset = 0;
+	spin_unlock(&hdev->reset_info.lock);
+
+	rc = hl_device_reset(hdev, HL_DRV_RESET_HARD);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to reset device during resume\n");
+		goto disable_device;
+	}
+
+	return 0;
+
+disable_device:
+	pci_disable_device(hdev->pdev);
+
+	return rc;
+}
+
+static int device_kill_open_processes(struct hl_device *hdev, u32 timeout, bool control_dev)
+{
+	struct task_struct *task = NULL;
+	struct list_head *hpriv_list;
+	struct hl_fpriv *hpriv;
+	struct mutex *hpriv_lock;
+	u32 pending_cnt;
+
+	hpriv_lock = control_dev ? &hdev->fpriv_ctrl_list_lock : &hdev->fpriv_list_lock;
+	hpriv_list = control_dev ? &hdev->fpriv_ctrl_list : &hdev->fpriv_list;
+
+	/* Giving time for user to close FD, and for processes that are inside
+	 * hl_device_open to finish
+	 */
+	if (!list_empty(hpriv_list))
+		ssleep(1);
+
+	if (timeout) {
+		pending_cnt = timeout;
+	} else {
+		if (hdev->process_kill_trial_cnt) {
+			/* Processes have been already killed */
+			pending_cnt = 1;
+			goto wait_for_processes;
+		} else {
+			/* Wait a small period after process kill */
+			pending_cnt = HL_PENDING_RESET_PER_SEC;
+		}
+	}
+
+	mutex_lock(hpriv_lock);
+
+	/* This section must be protected because we are dereferencing
+	 * pointers that are freed if the process exits
+	 */
+	list_for_each_entry(hpriv, hpriv_list, dev_node) {
+		task = get_pid_task(hpriv->taskpid, PIDTYPE_PID);
+		if (task) {
+			dev_info(hdev->dev, "Killing user process pid=%d\n",
+				task_pid_nr(task));
+			send_sig(SIGKILL, task, 1);
+			usleep_range(1000, 10000);
+
+			put_task_struct(task);
+		} else {
+			dev_dbg(hdev->dev,
+				"Can't get task struct for user process %d, process was killed from outside the driver\n",
+				pid_nr(hpriv->taskpid));
+		}
+	}
+
+	mutex_unlock(hpriv_lock);
+
+	/*
+	 * We killed the open users, but that doesn't mean they are closed.
+	 * It could be that they are running a long cleanup phase in the driver
+	 * e.g. MMU unmappings, or running other long teardown flow even before
+	 * our cleanup.
+	 * Therefore we need to wait again to make sure they are closed before
+	 * continuing with the reset.
+	 */
+
+wait_for_processes:
+	while ((!list_empty(hpriv_list)) && (pending_cnt)) {
+		dev_dbg(hdev->dev,
+			"Waiting for all unmap operations to finish before hard reset\n");
+
+		pending_cnt--;
+
+		ssleep(1);
+	}
+
+	/* All processes exited successfully */
+	if (list_empty(hpriv_list))
+		return 0;
+
+	/* Give up waiting for processes to exit */
+	if (hdev->process_kill_trial_cnt == HL_PENDING_RESET_MAX_TRIALS)
+		return -ETIME;
+
+	hdev->process_kill_trial_cnt++;
+
+	return -EBUSY;
+}
+
+static void device_disable_open_processes(struct hl_device *hdev, bool control_dev)
+{
+	struct list_head *hpriv_list;
+	struct hl_fpriv *hpriv;
+	struct mutex *hpriv_lock;
+
+	hpriv_lock = control_dev ? &hdev->fpriv_ctrl_list_lock : &hdev->fpriv_list_lock;
+	hpriv_list = control_dev ? &hdev->fpriv_ctrl_list : &hdev->fpriv_list;
+
+	mutex_lock(hpriv_lock);
+	list_for_each_entry(hpriv, hpriv_list, dev_node)
+		hpriv->hdev = NULL;
+	mutex_unlock(hpriv_lock);
+}
+
+static void send_disable_pci_access(struct hl_device *hdev, u32 flags)
+{
+	/* If reset is due to heartbeat, device CPU is no responsive in
+	 * which case no point sending PCI disable message to it.
+	 */
+	if ((flags & HL_DRV_RESET_HARD) &&
+			!(flags & (HL_DRV_RESET_HEARTBEAT | HL_DRV_RESET_BYPASS_REQ_TO_FW))) {
+		/* Disable PCI access from device F/W so he won't send
+		 * us additional interrupts. We disable MSI/MSI-X at
+		 * the halt_engines function and we can't have the F/W
+		 * sending us interrupts after that. We need to disable
+		 * the access here because if the device is marked
+		 * disable, the message won't be send. Also, in case
+		 * of heartbeat, the device CPU is marked as disable
+		 * so this message won't be sent
+		 */
+		if (hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_DISABLE_PCI_ACCESS, 0x0))
+			return;
+
+		/* disable_irq also generates sync irq, this verifies that last EQs are handled
+		 * before disabled is set. The IRQ will be enabled again in request_irq call.
+		 */
+		if (hdev->cpu_queues_enable)
+			disable_irq(pci_irq_vector(hdev->pdev, hdev->asic_prop.eq_interrupt_id));
+	}
+}
+
+static void handle_reset_trigger(struct hl_device *hdev, u32 flags)
+{
+	u32 cur_reset_trigger = HL_RESET_TRIGGER_DEFAULT;
+
+	/* No consecutive mechanism when user context exists */
+	if (hdev->is_compute_ctx_active)
+		return;
+
+	/*
+	 * 'reset cause' is being updated here, because getting here
+	 * means that it's the 1st time and the last time we're here
+	 * ('in_reset' makes sure of it). This makes sure that
+	 * 'reset_cause' will continue holding its 1st recorded reason!
+	 */
+	if (flags & HL_DRV_RESET_HEARTBEAT) {
+		hdev->reset_info.curr_reset_cause = HL_RESET_CAUSE_HEARTBEAT;
+		cur_reset_trigger = HL_DRV_RESET_HEARTBEAT;
+	} else if (flags & HL_DRV_RESET_TDR) {
+		hdev->reset_info.curr_reset_cause = HL_RESET_CAUSE_TDR;
+		cur_reset_trigger = HL_DRV_RESET_TDR;
+	} else if (flags & HL_DRV_RESET_FW_FATAL_ERR) {
+		hdev->reset_info.curr_reset_cause = HL_RESET_CAUSE_UNKNOWN;
+		cur_reset_trigger = HL_DRV_RESET_FW_FATAL_ERR;
+	} else {
+		hdev->reset_info.curr_reset_cause = HL_RESET_CAUSE_UNKNOWN;
+	}
+
+	/*
+	 * If reset cause is same twice, then reset_trigger_repeated
+	 * is set and if this reset is due to a fatal FW error
+	 * device is set to an unstable state.
+	 */
+	if (hdev->reset_info.prev_reset_trigger != cur_reset_trigger) {
+		hdev->reset_info.prev_reset_trigger = cur_reset_trigger;
+		hdev->reset_info.reset_trigger_repeated = 0;
+	} else {
+		hdev->reset_info.reset_trigger_repeated = 1;
+	}
+}
+
+static void reset_heartbeat_debug_info(struct hl_device *hdev)
+{
+	hdev->heartbeat_debug_info.last_pq_heartbeat_ts = 0;
+	hdev->heartbeat_debug_info.last_eq_heartbeat_ts = 0;
+	hdev->heartbeat_debug_info.heartbeat_event_counter = 0;
+}
+
+static inline void device_heartbeat_schedule(struct hl_device *hdev)
+{
+	if (!hdev->heartbeat)
+		return;
+
+	reset_heartbeat_debug_info(hdev);
+
+	/*
+	 * Before scheduling the heartbeat driver will check if eq event has received.
+	 * for the first schedule we need to set the indication as true then for the next
+	 * one this indication will be true only if eq event was sent by FW.
+	 */
+	hdev->eq_heartbeat_received = true;
+
+	schedule_delayed_work(&hdev->work_heartbeat,
+			usecs_to_jiffies(HL_HEARTBEAT_PER_USEC));
+}
+
+/*
+ * hl_device_reset - reset the device
+ *
+ * @hdev: pointer to habanalabs device structure
+ * @flags: reset flags.
+ *
+ * Block future CS and wait for pending CS to be enqueued
+ * Call ASIC H/W fini
+ * Flush all completions
+ * Re-initialize all internal data structures
+ * Call ASIC H/W init, late_init
+ * Test queues
+ * Enable device
+ *
+ * Returns 0 for success or an error on failure.
+ */
+int hl_device_reset(struct hl_device *hdev, u32 flags)
+{
+	bool hard_reset, from_hard_reset_thread, fw_reset, reset_upon_device_release,
+		schedule_hard_reset = false, delay_reset, from_dev_release, from_watchdog_thread;
+	u64 idle_mask[HL_BUSY_ENGINES_MASK_EXT_SIZE] = {0};
+	struct hl_ctx *ctx;
+	int i, rc, hw_fini_rc;
+
+	if (!hdev->init_done) {
+		dev_err(hdev->dev, "Can't reset before initialization is done\n");
+		return 0;
+	}
+
+	hard_reset = !!(flags & HL_DRV_RESET_HARD);
+	from_hard_reset_thread = !!(flags & HL_DRV_RESET_FROM_RESET_THR);
+	fw_reset = !!(flags & HL_DRV_RESET_BYPASS_REQ_TO_FW);
+	from_dev_release = !!(flags & HL_DRV_RESET_DEV_RELEASE);
+	delay_reset = !!(flags & HL_DRV_RESET_DELAY);
+	from_watchdog_thread = !!(flags & HL_DRV_RESET_FROM_WD_THR);
+	reset_upon_device_release = hdev->reset_upon_device_release && from_dev_release;
+
+	if (hdev->cpld_shutdown) {
+		dev_err(hdev->dev, "Cannot reset device, cpld is shutdown! Device is NOT usable\n");
+		return -EIO;
+	}
+
+	if (!hard_reset && (hl_device_status(hdev) == HL_DEVICE_STATUS_MALFUNCTION)) {
+		dev_dbg(hdev->dev, "soft-reset isn't supported on a malfunctioning device\n");
+		return 0;
+	}
+
+	if (!hard_reset && !hdev->asic_prop.supports_compute_reset) {
+		dev_dbg(hdev->dev, "asic doesn't support compute reset - do hard-reset instead\n");
+		hard_reset = true;
+	}
+
+	if (reset_upon_device_release) {
+		if (hard_reset) {
+			dev_crit(hdev->dev,
+				"Aborting reset because hard-reset is mutually exclusive with reset-on-device-release\n");
+			return -EINVAL;
+		}
+
+		goto do_reset;
+	}
+
+	if (!hard_reset && !hdev->asic_prop.allow_inference_soft_reset) {
+		dev_dbg(hdev->dev,
+			"asic doesn't allow inference soft reset - do hard-reset instead\n");
+		hard_reset = true;
+	}
+
+do_reset:
+	/* Re-entry of reset thread */
+	if (from_hard_reset_thread && hdev->process_kill_trial_cnt)
+		goto kill_processes;
+
+	/*
+	 * Prevent concurrency in this function - only one reset should be
+	 * done at any given time. We need to perform this only if we didn't
+	 * get here from a dedicated hard reset thread.
+	 */
+	if (!from_hard_reset_thread) {
+		/* Block future CS/VM/JOB completion operations */
+		spin_lock(&hdev->reset_info.lock);
+		if (hdev->reset_info.in_reset) {
+			/* We allow scheduling of a hard reset only during a compute reset */
+			if (hard_reset && hdev->reset_info.in_compute_reset)
+				hdev->reset_info.hard_reset_schedule_flags = flags;
+			spin_unlock(&hdev->reset_info.lock);
+			return 0;
+		}
+
+		/* This still allows the completion of some KDMA ops
+		 * Update this before in_reset because in_compute_reset implies we are in reset
+		 */
+		hdev->reset_info.in_compute_reset = !hard_reset;
+
+		hdev->reset_info.in_reset = 1;
+
+		spin_unlock(&hdev->reset_info.lock);
+
+		/* Cancel the device release watchdog work if required.
+		 * In case of reset-upon-device-release while the release watchdog work is
+		 * scheduled due to a hard-reset, do hard-reset instead of compute-reset.
+		 */
+		if ((hard_reset || from_dev_release) && hdev->reset_info.watchdog_active) {
+			struct hl_device_reset_work *watchdog_work =
+					&hdev->device_release_watchdog_work;
+
+			hdev->reset_info.watchdog_active = 0;
+			if (!from_watchdog_thread)
+				cancel_delayed_work_sync(&watchdog_work->reset_work);
+
+			if (from_dev_release && (watchdog_work->flags & HL_DRV_RESET_HARD)) {
+				hdev->reset_info.in_compute_reset = 0;
+				flags |= HL_DRV_RESET_HARD;
+				flags &= ~HL_DRV_RESET_DEV_RELEASE;
+				hard_reset = true;
+			}
+		}
+
+		if (delay_reset)
+			usleep_range(HL_RESET_DELAY_USEC, HL_RESET_DELAY_USEC << 1);
+
+escalate_reset_flow:
+		handle_reset_trigger(hdev, flags);
+		send_disable_pci_access(hdev, flags);
+
+		/* This also blocks future CS/VM/JOB completion operations */
+		hdev->disabled = true;
+
+		take_release_locks(hdev);
+
+		if (hard_reset)
+			dev_info(hdev->dev, "Going to reset device\n");
+		else if (reset_upon_device_release)
+			dev_dbg(hdev->dev, "Going to reset device after release by user\n");
+		else
+			dev_dbg(hdev->dev, "Going to reset engines of inference device\n");
+	}
+
+	if ((hard_reset) && (!from_hard_reset_thread)) {
+		hdev->reset_info.hard_reset_pending = true;
+
+		hdev->process_kill_trial_cnt = 0;
+
+		hdev->device_reset_work.flags = flags;
+
+		/*
+		 * Because the reset function can't run from heartbeat work,
+		 * we need to call the reset function from a dedicated work.
+		 */
+		queue_delayed_work(hdev->reset_wq, &hdev->device_reset_work.reset_work, 0);
+
+		return 0;
+	}
+
+	cleanup_resources(hdev, hard_reset, fw_reset, from_dev_release);
+
+kill_processes:
+	if (hard_reset) {
+		/* Kill processes here after CS rollback. This is because the
+		 * process can't really exit until all its CSs are done, which
+		 * is what we do in cs rollback
+		 */
+		rc = device_kill_open_processes(hdev, 0, false);
+
+		if (rc == -EBUSY) {
+			if (hdev->device_fini_pending) {
+				dev_crit(hdev->dev,
+					"%s Failed to kill all open processes, stopping hard reset\n",
+					dev_name(&(hdev)->pdev->dev));
+				goto out_err;
+			}
+
+			/* signal reset thread to reschedule */
+			return rc;
+		}
+
+		if (rc) {
+			dev_crit(hdev->dev,
+				"%s Failed to kill all open processes, stopping hard reset\n",
+				dev_name(&(hdev)->pdev->dev));
+			goto out_err;
+		}
+
+		/* Flush the Event queue workers to make sure no other thread is
+		 * reading or writing to registers during the reset
+		 */
+		flush_workqueue(hdev->eq_wq);
+	}
+
+	/* Reset the H/W. It will be in idle state after this returns */
+	hw_fini_rc = hdev->asic_funcs->hw_fini(hdev, hard_reset, fw_reset);
+
+	if (hard_reset) {
+		hdev->fw_loader.fw_comp_loaded = FW_TYPE_NONE;
+
+		/* Release kernel context */
+		if (hdev->kernel_ctx && hl_ctx_put(hdev->kernel_ctx) == 1)
+			hdev->kernel_ctx = NULL;
+
+		hl_vm_fini(hdev);
+		hl_mmu_fini(hdev);
+		hl_eq_reset(hdev, &hdev->event_queue);
+	}
+
+	/* Re-initialize PI,CI to 0 in all queues (hw queue, cq) */
+	hl_hw_queue_reset(hdev, hard_reset);
+	for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++)
+		hl_cq_reset(hdev, &hdev->completion_queue[i]);
+
+	/* Make sure the context switch phase will run again */
+	ctx = hl_get_compute_ctx(hdev);
+	if (ctx) {
+		atomic_set(&ctx->thread_ctx_switch_token, 1);
+		ctx->thread_ctx_switch_wait_token = 0;
+		hl_ctx_put(ctx);
+	}
+
+	if (hw_fini_rc) {
+		rc = hw_fini_rc;
+		goto out_err;
+	}
+	/* Finished tear-down, starting to re-initialize */
+
+	if (hard_reset) {
+		hdev->device_cpu_disabled = false;
+		hdev->reset_info.hard_reset_pending = false;
+
+		/*
+		 * Put the device in an unusable state if there are 2 back to back resets due to
+		 * fatal errors.
+		 */
+		if (hdev->reset_info.reset_trigger_repeated &&
+				(hdev->reset_info.prev_reset_trigger == HL_DRV_RESET_FW_FATAL_ERR ||
+						hdev->reset_info.prev_reset_trigger ==
+								HL_DRV_RESET_HEARTBEAT)) {
+			dev_crit(hdev->dev,
+				"%s Consecutive fatal errors, stopping hard reset\n",
+				dev_name(&(hdev)->pdev->dev));
+			rc = -EIO;
+			goto out_err;
+		}
+
+		if (hdev->kernel_ctx) {
+			dev_crit(hdev->dev,
+				"%s kernel ctx was alive during hard reset, something is terribly wrong\n",
+				dev_name(&(hdev)->pdev->dev));
+			rc = -EBUSY;
+			goto out_err;
+		}
+
+		rc = hl_mmu_init(hdev);
+		if (rc) {
+			dev_err(hdev->dev,
+				"Failed to initialize MMU S/W after hard reset\n");
+			goto out_err;
+		}
+
+		/* Allocate the kernel context */
+		hdev->kernel_ctx = kzalloc(sizeof(*hdev->kernel_ctx),
+						GFP_KERNEL);
+		if (!hdev->kernel_ctx) {
+			rc = -ENOMEM;
+			hl_mmu_fini(hdev);
+			goto out_err;
+		}
+
+		hdev->is_compute_ctx_active = false;
+
+		rc = hl_ctx_init(hdev, hdev->kernel_ctx, true);
+		if (rc) {
+			dev_err(hdev->dev,
+				"failed to init kernel ctx in hard reset\n");
+			kfree(hdev->kernel_ctx);
+			hdev->kernel_ctx = NULL;
+			hl_mmu_fini(hdev);
+			goto out_err;
+		}
+	}
+
+	/* Device is now enabled as part of the initialization requires
+	 * communication with the device firmware to get information that
+	 * is required for the initialization itself
+	 */
+	hdev->disabled = false;
+
+	/* F/W security enabled indication might be updated after hard-reset */
+	if (hard_reset) {
+		rc = hl_fw_read_preboot_status(hdev);
+		if (rc)
+			goto out_err;
+	}
+
+	rc = hdev->asic_funcs->hw_init(hdev);
+	if (rc) {
+		dev_err(hdev->dev, "failed to initialize the H/W after reset\n");
+		goto out_err;
+	}
+
+	/* If device is not idle fail the reset process */
+	if (!hdev->asic_funcs->is_device_idle(hdev, idle_mask,
+						HL_BUSY_ENGINES_MASK_EXT_SIZE, NULL)) {
+		print_idle_status_mask(hdev, "device is not idle after reset", idle_mask);
+		rc = -EIO;
+		goto out_err;
+	}
+
+	/* Check that the communication with the device is working */
+	rc = hdev->asic_funcs->test_queues(hdev);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to detect if device is alive after reset\n");
+		goto out_err;
+	}
+
+	if (hard_reset) {
+		rc = device_late_init(hdev);
+		if (rc) {
+			dev_err(hdev->dev, "Failed late init after hard reset\n");
+			goto out_err;
+		}
+
+		rc = hl_vm_init(hdev);
+		if (rc) {
+			dev_err(hdev->dev, "Failed to init memory module after hard reset\n");
+			goto out_err;
+		}
+
+		if (!hdev->asic_prop.fw_security_enabled)
+			hl_fw_set_max_power(hdev);
+	} else {
+		rc = hdev->asic_funcs->compute_reset_late_init(hdev);
+		if (rc) {
+			if (reset_upon_device_release)
+				dev_err(hdev->dev,
+					"Failed late init in reset after device release\n");
+			else
+				dev_err(hdev->dev, "Failed late init after compute reset\n");
+			goto out_err;
+		}
+	}
+
+	rc = hdev->asic_funcs->scrub_device_mem(hdev);
+	if (rc) {
+		dev_err(hdev->dev, "scrub mem failed from device reset (%d)\n", rc);
+		goto out_err;
+	}
+
+	spin_lock(&hdev->reset_info.lock);
+	hdev->reset_info.in_compute_reset = 0;
+
+	/* Schedule hard reset only if requested and if not already in hard reset.
+	 * We keep 'in_reset' enabled, so no other reset can go in during the hard
+	 * reset schedule
+	 */
+	if (!hard_reset && hdev->reset_info.hard_reset_schedule_flags)
+		schedule_hard_reset = true;
+	else
+		hdev->reset_info.in_reset = 0;
+
+	spin_unlock(&hdev->reset_info.lock);
+
+	hdev->reset_info.needs_reset = false;
+
+	if (hard_reset)
+		dev_info(hdev->dev,
+			 "Successfully finished resetting the %s device\n",
+			 dev_name(&(hdev)->pdev->dev));
+	else
+		dev_dbg(hdev->dev,
+			"Successfully finished resetting the %s device\n",
+			dev_name(&(hdev)->pdev->dev));
+
+	if (hard_reset) {
+		hdev->reset_info.hard_reset_cnt++;
+
+		device_heartbeat_schedule(hdev);
+
+		/* After reset is done, we are ready to receive events from
+		 * the F/W. We can't do it before because we will ignore events
+		 * and if those events are fatal, we won't know about it and
+		 * the device will be operational although it shouldn't be
+		 */
+		hdev->asic_funcs->enable_events_from_fw(hdev);
+	} else {
+		if (!reset_upon_device_release)
+			hdev->reset_info.compute_reset_cnt++;
+
+		if (schedule_hard_reset) {
+			dev_info(hdev->dev, "Performing hard reset scheduled during compute reset\n");
+			flags = hdev->reset_info.hard_reset_schedule_flags;
+			hdev->reset_info.hard_reset_schedule_flags = 0;
+			hard_reset = true;
+			goto escalate_reset_flow;
+		}
+	}
+
+	return 0;
+
+out_err:
+	hdev->disabled = true;
+
+	spin_lock(&hdev->reset_info.lock);
+	hdev->reset_info.in_compute_reset = 0;
+
+	if (hard_reset) {
+		dev_err(hdev->dev,
+			"%s Failed to reset! Device is NOT usable\n",
+			dev_name(&(hdev)->pdev->dev));
+		hdev->reset_info.hard_reset_cnt++;
+	} else {
+		if (reset_upon_device_release) {
+			dev_err(hdev->dev, "Failed to reset device after user release\n");
+			flags &= ~HL_DRV_RESET_DEV_RELEASE;
+		} else {
+			dev_err(hdev->dev, "Failed to do compute reset\n");
+			hdev->reset_info.compute_reset_cnt++;
+		}
+
+		spin_unlock(&hdev->reset_info.lock);
+		flags |= HL_DRV_RESET_HARD;
+		hard_reset = true;
+		goto escalate_reset_flow;
+	}
+
+	hdev->reset_info.in_reset = 0;
+
+	spin_unlock(&hdev->reset_info.lock);
+
+	return rc;
+}
+
+/*
+ * hl_device_cond_reset() - conditionally reset the device.
+ * @hdev: pointer to habanalabs device structure.
+ * @reset_flags: reset flags.
+ * @event_mask: events to notify user about.
+ *
+ * Conditionally reset the device, or alternatively schedule a watchdog work to reset the device
+ * unless another reset precedes it.
+ */
+int hl_device_cond_reset(struct hl_device *hdev, u32 flags, u64 event_mask)
+{
+	struct hl_ctx *ctx = NULL;
+
+	/* F/W reset cannot be postponed */
+	if (flags & HL_DRV_RESET_BYPASS_REQ_TO_FW)
+		goto device_reset;
+
+	/* Device release watchdog is relevant only if user exists and gets a reset notification */
+	if (!(event_mask & HL_NOTIFIER_EVENT_DEVICE_RESET)) {
+		dev_err(hdev->dev, "Resetting device without a reset indication to user\n");
+		goto device_reset;
+	}
+
+	ctx = hl_get_compute_ctx(hdev);
+	if (!ctx)
+		goto device_reset;
+
+	/*
+	 * There is no point in postponing the reset if user is not registered for events.
+	 * However if no eventfd_ctx exists but the device release watchdog is already scheduled, it
+	 * just implies that user has unregistered as part of handling a previous event. In this
+	 * case an immediate reset is not required.
+	 */
+	if (!ctx->hpriv->notifier_event.eventfd && !hdev->reset_info.watchdog_active)
+		goto device_reset;
+
+	/* Schedule the device release watchdog work unless reset is already in progress or if the
+	 * work is already scheduled.
+	 */
+	spin_lock(&hdev->reset_info.lock);
+	if (hdev->reset_info.in_reset) {
+		spin_unlock(&hdev->reset_info.lock);
+		goto device_reset;
+	}
+
+	if (hdev->reset_info.watchdog_active) {
+		hdev->device_release_watchdog_work.flags |= flags;
+		goto out;
+	}
+
+	hdev->device_release_watchdog_work.flags = flags;
+	dev_dbg(hdev->dev, "Device is going to be hard-reset in %u sec unless being released\n",
+		hdev->device_release_watchdog_timeout_sec);
+	schedule_delayed_work(&hdev->device_release_watchdog_work.reset_work,
+				secs_to_jiffies(hdev->device_release_watchdog_timeout_sec));
+	hdev->reset_info.watchdog_active = 1;
+out:
+	spin_unlock(&hdev->reset_info.lock);
+
+	hl_notifier_event_send_all(hdev, event_mask);
+
+	hl_ctx_put(ctx);
+
+	hl_abort_waiting_for_completions(hdev);
+
+	return 0;
+
+device_reset:
+	if (event_mask)
+		hl_notifier_event_send_all(hdev, event_mask);
+	if (ctx)
+		hl_ctx_put(ctx);
+
+	return hl_device_reset(hdev, flags | HL_DRV_RESET_HARD);
+}
+
+static void hl_notifier_event_send(struct hl_notifier_event *notifier_event, u64 event_mask)
+{
+	mutex_lock(&notifier_event->lock);
+	notifier_event->events_mask |= event_mask;
+
+	if (notifier_event->eventfd)
+		eventfd_signal(notifier_event->eventfd);
+
+	mutex_unlock(&notifier_event->lock);
+}
+
+/*
+ * hl_notifier_event_send_all - notify all user processes via eventfd
+ *
+ * @hdev: pointer to habanalabs device structure
+ * @event_mask: the occurred event/s
+ * Returns 0 for success or an error on failure.
+ */
+void hl_notifier_event_send_all(struct hl_device *hdev, u64 event_mask)
+{
+	struct hl_fpriv	*hpriv;
+
+	if (!event_mask) {
+		dev_warn(hdev->dev, "Skip sending zero event");
+		return;
+	}
+
+	mutex_lock(&hdev->fpriv_list_lock);
+
+	list_for_each_entry(hpriv, &hdev->fpriv_list, dev_node)
+		hl_notifier_event_send(&hpriv->notifier_event, event_mask);
+
+	mutex_unlock(&hdev->fpriv_list_lock);
+}
+
+/*
+ * hl_device_init - main initialization function for habanalabs device
+ *
+ * @hdev: pointer to habanalabs device structure
+ *
+ * Allocate an id for the device, do early initialization and then call the
+ * ASIC specific initialization functions. Finally, create the cdev and the
+ * Linux device to expose it to the user
+ */
+int hl_device_init(struct hl_device *hdev)
+{
+	int i, rc, cq_cnt, user_interrupt_cnt, cq_ready_cnt;
+	struct hl_ts_free_jobs *free_jobs_data;
+	bool expose_interfaces_on_err = false;
+	void *p;
+
+	/* Initialize ASIC function pointers and perform early init */
+	rc = device_early_init(hdev);
+	if (rc)
+		goto out_disabled;
+
+	user_interrupt_cnt = hdev->asic_prop.user_dec_intr_count +
+				hdev->asic_prop.user_interrupt_count;
+
+	if (user_interrupt_cnt) {
+		hdev->user_interrupt = kcalloc(user_interrupt_cnt, sizeof(*hdev->user_interrupt),
+						GFP_KERNEL);
+		if (!hdev->user_interrupt) {
+			rc = -ENOMEM;
+			goto early_fini;
+		}
+
+		/* Timestamp records supported only if CQ supported in device */
+		if (hdev->asic_prop.first_available_cq[0] != USHRT_MAX) {
+			for (i = 0 ; i < user_interrupt_cnt ; i++) {
+				p = vzalloc(TIMESTAMP_FREE_NODES_NUM *
+						sizeof(struct timestamp_reg_free_node));
+				if (!p) {
+					rc = -ENOMEM;
+					goto free_usr_intr_mem;
+				}
+				free_jobs_data = &hdev->user_interrupt[i].ts_free_jobs_data;
+				free_jobs_data->free_nodes_pool = p;
+				free_jobs_data->free_nodes_length = TIMESTAMP_FREE_NODES_NUM;
+				free_jobs_data->next_avail_free_node_idx = 0;
+			}
+		}
+	}
+
+	free_jobs_data = &hdev->common_user_cq_interrupt.ts_free_jobs_data;
+	p = vzalloc(TIMESTAMP_FREE_NODES_NUM *
+				sizeof(struct timestamp_reg_free_node));
+	if (!p) {
+		rc = -ENOMEM;
+		goto free_usr_intr_mem;
+	}
+
+	free_jobs_data->free_nodes_pool = p;
+	free_jobs_data->free_nodes_length = TIMESTAMP_FREE_NODES_NUM;
+	free_jobs_data->next_avail_free_node_idx = 0;
+
+	/*
+	 * Start calling ASIC initialization. First S/W then H/W and finally
+	 * late init
+	 */
+	rc = hdev->asic_funcs->sw_init(hdev);
+	if (rc)
+		goto free_common_usr_intr_mem;
+
+
+	/* initialize completion structure for multi CS wait */
+	hl_multi_cs_completion_init(hdev);
+
+	/*
+	 * Initialize the H/W queues. Must be done before hw_init, because
+	 * there the addresses of the kernel queue are being written to the
+	 * registers of the device
+	 */
+	rc = hl_hw_queues_create(hdev);
+	if (rc) {
+		dev_err(hdev->dev, "failed to initialize kernel queues\n");
+		goto sw_fini;
+	}
+
+	cq_cnt = hdev->asic_prop.completion_queues_count;
+
+	/*
+	 * Initialize the completion queues. Must be done before hw_init,
+	 * because there the addresses of the completion queues are being
+	 * passed as arguments to request_irq
+	 */
+	if (cq_cnt) {
+		hdev->completion_queue = kcalloc(cq_cnt,
+				sizeof(*hdev->completion_queue),
+				GFP_KERNEL);
+
+		if (!hdev->completion_queue) {
+			dev_err(hdev->dev,
+				"failed to allocate completion queues\n");
+			rc = -ENOMEM;
+			goto hw_queues_destroy;
+		}
+	}
+
+	for (i = 0, cq_ready_cnt = 0 ; i < cq_cnt ; i++, cq_ready_cnt++) {
+		rc = hl_cq_init(hdev, &hdev->completion_queue[i],
+				hdev->asic_funcs->get_queue_id_for_cq(hdev, i));
+		if (rc) {
+			dev_err(hdev->dev,
+				"failed to initialize completion queue\n");
+			goto cq_fini;
+		}
+		hdev->completion_queue[i].cq_idx = i;
+	}
+
+	hdev->shadow_cs_queue = kcalloc(hdev->asic_prop.max_pending_cs,
+					sizeof(struct hl_cs *), GFP_KERNEL);
+	if (!hdev->shadow_cs_queue) {
+		rc = -ENOMEM;
+		goto cq_fini;
+	}
+
+	/*
+	 * Initialize the event queue. Must be done before hw_init,
+	 * because there the address of the event queue is being
+	 * passed as argument to request_irq
+	 */
+	rc = hl_eq_init(hdev, &hdev->event_queue);
+	if (rc) {
+		dev_err(hdev->dev, "failed to initialize event queue\n");
+		goto free_shadow_cs_queue;
+	}
+
+	/* MMU S/W must be initialized before kernel context is created */
+	rc = hl_mmu_init(hdev);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to initialize MMU S/W structures\n");
+		goto eq_fini;
+	}
+
+	/* Allocate the kernel context */
+	hdev->kernel_ctx = kzalloc(sizeof(*hdev->kernel_ctx), GFP_KERNEL);
+	if (!hdev->kernel_ctx) {
+		rc = -ENOMEM;
+		goto mmu_fini;
+	}
+
+	hdev->is_compute_ctx_active = false;
+
+	hdev->asic_funcs->state_dump_init(hdev);
+
+	hdev->device_release_watchdog_timeout_sec = HL_DEVICE_RELEASE_WATCHDOG_TIMEOUT_SEC;
+
+	hdev->memory_scrub_val = MEM_SCRUB_DEFAULT_VAL;
+
+	rc = hl_debugfs_device_init(hdev);
+	if (rc) {
+		dev_err(hdev->dev, "failed to initialize debugfs entry structure\n");
+		kfree(hdev->kernel_ctx);
+		goto mmu_fini;
+	}
+
+	/* The debugfs entry structure is accessed in hl_ctx_init(), so it must be called after
+	 * hl_debugfs_device_init().
+	 */
+	rc = hl_ctx_init(hdev, hdev->kernel_ctx, true);
+	if (rc) {
+		dev_err(hdev->dev, "failed to initialize kernel context\n");
+		kfree(hdev->kernel_ctx);
+		goto debugfs_device_fini;
+	}
+
+	rc = hl_cb_pool_init(hdev);
+	if (rc) {
+		dev_err(hdev->dev, "failed to initialize CB pool\n");
+		goto release_ctx;
+	}
+
+	rc = hl_dec_init(hdev);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to initialize the decoder module\n");
+		goto cb_pool_fini;
+	}
+
+	/*
+	 * From this point, override rc (=0) in case of an error to allow debugging
+	 * (by adding char devices and creating sysfs/debugfs files as part of the error flow).
+	 */
+	expose_interfaces_on_err = true;
+
+	/* Device is now enabled as part of the initialization requires
+	 * communication with the device firmware to get information that
+	 * is required for the initialization itself
+	 */
+	hdev->disabled = false;
+
+	rc = hdev->asic_funcs->hw_init(hdev);
+	if (rc) {
+		dev_err(hdev->dev, "failed to initialize the H/W\n");
+		rc = 0;
+		goto out_disabled;
+	}
+
+	/* Check that the communication with the device is working */
+	rc = hdev->asic_funcs->test_queues(hdev);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to detect if device is alive\n");
+		rc = 0;
+		goto out_disabled;
+	}
+
+	rc = device_late_init(hdev);
+	if (rc) {
+		dev_err(hdev->dev, "Failed late initialization\n");
+		rc = 0;
+		goto out_disabled;
+	}
+
+	dev_info(hdev->dev, "Found %s device with %lluGB DRAM\n",
+		hdev->asic_name,
+		hdev->asic_prop.dram_size / SZ_1G);
+
+	rc = hl_vm_init(hdev);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to initialize memory module\n");
+		rc = 0;
+		goto out_disabled;
+	}
+
+	/*
+	 * Expose devices and sysfs/debugfs files to user.
+	 * From here there is no need to expose them in case of an error.
+	 */
+	expose_interfaces_on_err = false;
+
+	rc = drm_dev_register(&hdev->drm, 0);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to register DRM device, rc %d\n", rc);
+		rc = 0;
+		goto out_disabled;
+	}
+
+	rc = cdev_sysfs_debugfs_add(hdev);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to add char devices and sysfs/debugfs files\n");
+		rc = 0;
+		goto out_disabled;
+	}
+
+	/* Need to call this again because the max power might change,
+	 * depending on card type for certain ASICs
+	 */
+	if (hdev->asic_prop.set_max_power_on_device_init &&
+			!hdev->asic_prop.fw_security_enabled)
+		hl_fw_set_max_power(hdev);
+
+	/*
+	 * hl_hwmon_init() must be called after device_late_init(), because only
+	 * there we get the information from the device about which
+	 * hwmon-related sensors the device supports.
+	 * Furthermore, it must be done after adding the device to the system.
+	 */
+	rc = hl_hwmon_init(hdev);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to initialize hwmon\n");
+		rc = 0;
+		goto out_disabled;
+	}
+
+	/* Scheduling the EQ heartbeat thread must come after driver is done with all
+	 * initializations, as we want to make sure the FW gets enough time to be prepared
+	 * to respond to heartbeat packets.
+	 */
+	device_heartbeat_schedule(hdev);
+
+	dev_notice(hdev->dev,
+		"Successfully added device %s to habanalabs driver\n",
+		dev_name(&(hdev)->pdev->dev));
+
+	/* After initialization is done, we are ready to receive events from
+	 * the F/W. We can't do it before because we will ignore events and if
+	 * those events are fatal, we won't know about it and the device will
+	 * be operational although it shouldn't be
+	 */
+	hdev->asic_funcs->enable_events_from_fw(hdev);
+
+	hdev->init_done = true;
+
+	return 0;
+
+cb_pool_fini:
+	hl_cb_pool_fini(hdev);
+release_ctx:
+	if (hl_ctx_put(hdev->kernel_ctx) != 1)
+		dev_err(hdev->dev,
+			"kernel ctx is still alive on initialization failure\n");
+debugfs_device_fini:
+	hl_debugfs_device_fini(hdev);
+mmu_fini:
+	hl_mmu_fini(hdev);
+eq_fini:
+	hl_eq_fini(hdev, &hdev->event_queue);
+free_shadow_cs_queue:
+	kfree(hdev->shadow_cs_queue);
+cq_fini:
+	for (i = 0 ; i < cq_ready_cnt ; i++)
+		hl_cq_fini(hdev, &hdev->completion_queue[i]);
+	kfree(hdev->completion_queue);
+hw_queues_destroy:
+	hl_hw_queues_destroy(hdev);
+sw_fini:
+	hdev->asic_funcs->sw_fini(hdev);
+free_common_usr_intr_mem:
+	vfree(hdev->common_user_cq_interrupt.ts_free_jobs_data.free_nodes_pool);
+free_usr_intr_mem:
+	if (user_interrupt_cnt) {
+		for (i = 0 ; i < user_interrupt_cnt ; i++) {
+			if (!hdev->user_interrupt[i].ts_free_jobs_data.free_nodes_pool)
+				break;
+			vfree(hdev->user_interrupt[i].ts_free_jobs_data.free_nodes_pool);
+		}
+		kfree(hdev->user_interrupt);
+	}
+early_fini:
+	device_early_fini(hdev);
+out_disabled:
+	hdev->disabled = true;
+	if (expose_interfaces_on_err) {
+		drm_dev_register(&hdev->drm, 0);
+		cdev_sysfs_debugfs_add(hdev);
+	}
+
+	pr_err("Failed to initialize accel%d. Device %s is NOT usable!\n",
+		hdev->cdev_idx, dev_name(&hdev->pdev->dev));
+
+	return rc;
+}
+
+/*
+ * hl_device_fini - main tear-down function for habanalabs device
+ *
+ * @hdev: pointer to habanalabs device structure
+ *
+ * Destroy the device, call ASIC fini functions and release the id
+ */
+void hl_device_fini(struct hl_device *hdev)
+{
+	u32 user_interrupt_cnt;
+	bool device_in_reset;
+	ktime_t timeout;
+	u64 reset_sec;
+	int i, rc;
+
+	dev_info(hdev->dev, "Removing device %s\n", dev_name(&(hdev)->pdev->dev));
+
+	hdev->device_fini_pending = 1;
+	flush_delayed_work(&hdev->device_reset_work.reset_work);
+
+	if (hdev->pldm)
+		reset_sec = HL_PLDM_HARD_RESET_MAX_TIMEOUT;
+	else
+		reset_sec = HL_HARD_RESET_MAX_TIMEOUT;
+
+	/*
+	 * This function is competing with the reset function, so try to
+	 * take the reset atomic and if we are already in middle of reset,
+	 * wait until reset function is finished. Reset function is designed
+	 * to always finish. However, in Gaudi, because of all the network
+	 * ports, the hard reset could take between 10-30 seconds
+	 */
+
+	timeout = ktime_add_us(ktime_get(), reset_sec * 1000 * 1000);
+
+	spin_lock(&hdev->reset_info.lock);
+	device_in_reset = !!hdev->reset_info.in_reset;
+	if (!device_in_reset)
+		hdev->reset_info.in_reset = 1;
+	spin_unlock(&hdev->reset_info.lock);
+
+	while (device_in_reset) {
+		usleep_range(50, 200);
+
+		spin_lock(&hdev->reset_info.lock);
+		device_in_reset = !!hdev->reset_info.in_reset;
+		if (!device_in_reset)
+			hdev->reset_info.in_reset = 1;
+		spin_unlock(&hdev->reset_info.lock);
+
+		if (ktime_compare(ktime_get(), timeout) > 0) {
+			dev_crit(hdev->dev,
+				"%s Failed to remove device because reset function did not finish\n",
+				dev_name(&(hdev)->pdev->dev));
+			return;
+		}
+	}
+
+	cancel_delayed_work_sync(&hdev->device_release_watchdog_work.reset_work);
+
+	/* Disable PCI access from device F/W so it won't send us additional
+	 * interrupts. We disable MSI/MSI-X at the halt_engines function and we
+	 * can't have the F/W sending us interrupts after that. We need to
+	 * disable the access here because if the device is marked disable, the
+	 * message won't be send. Also, in case of heartbeat, the device CPU is
+	 * marked as disable so this message won't be sent
+	 */
+	hl_fw_send_pci_access_msg(hdev,	CPUCP_PACKET_DISABLE_PCI_ACCESS, 0x0);
+
+	/* Mark device as disabled */
+	hdev->disabled = true;
+
+	take_release_locks(hdev);
+
+	hdev->reset_info.hard_reset_pending = true;
+
+	hl_hwmon_fini(hdev);
+
+	cleanup_resources(hdev, true, false, false);
+
+	/* Kill processes here after CS rollback. This is because the process
+	 * can't really exit until all its CSs are done, which is what we
+	 * do in cs rollback
+	 */
+	dev_info(hdev->dev,
+		"Waiting for all processes to exit (timeout of %u seconds)",
+		HL_WAIT_PROCESS_KILL_ON_DEVICE_FINI);
+
+	hdev->process_kill_trial_cnt = 0;
+	rc = device_kill_open_processes(hdev, HL_WAIT_PROCESS_KILL_ON_DEVICE_FINI, false);
+	if (rc) {
+		dev_crit(hdev->dev, "Failed to kill all open processes (%d)\n", rc);
+		device_disable_open_processes(hdev, false);
+	}
+
+	hdev->process_kill_trial_cnt = 0;
+	rc = device_kill_open_processes(hdev, 0, true);
+	if (rc) {
+		dev_crit(hdev->dev, "Failed to kill all control device open processes (%d)\n", rc);
+		device_disable_open_processes(hdev, true);
+	}
+
+	hl_cb_pool_fini(hdev);
+
+	/* Reset the H/W. It will be in idle state after this returns */
+	rc = hdev->asic_funcs->hw_fini(hdev, true, false);
+	if (rc)
+		dev_err(hdev->dev, "hw_fini failed in device fini while removing device %d\n", rc);
+
+	/* Reset the H/W (if it accessible). It will be in idle state after this returns */
+	if (!hdev->cpld_shutdown) {
+		rc = hdev->asic_funcs->hw_fini(hdev, true, false);
+		if (rc)
+			dev_err(hdev->dev,
+				"hw_fini failed in device fini while removing device %d\n", rc);
+	}
+
+	hdev->fw_loader.fw_comp_loaded = FW_TYPE_NONE;
+
+	/* Release kernel context */
+	if ((hdev->kernel_ctx) && (hl_ctx_put(hdev->kernel_ctx) != 1))
+		dev_err(hdev->dev, "kernel ctx is still alive\n");
+
+	hl_dec_fini(hdev);
+
+	hl_vm_fini(hdev);
+
+	hl_mmu_fini(hdev);
+
+	vfree(hdev->captured_err_info.page_fault_info.user_mappings);
+
+	hl_eq_fini(hdev, &hdev->event_queue);
+
+	kfree(hdev->shadow_cs_queue);
+
+	for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++)
+		hl_cq_fini(hdev, &hdev->completion_queue[i]);
+	kfree(hdev->completion_queue);
+
+	user_interrupt_cnt = hdev->asic_prop.user_dec_intr_count +
+					hdev->asic_prop.user_interrupt_count;
+
+	if (user_interrupt_cnt) {
+		if (hdev->asic_prop.first_available_cq[0] != USHRT_MAX) {
+			for (i = 0 ; i < user_interrupt_cnt ; i++)
+				vfree(hdev->user_interrupt[i].ts_free_jobs_data.free_nodes_pool);
+		}
+
+		kfree(hdev->user_interrupt);
+	}
+
+	vfree(hdev->common_user_cq_interrupt.ts_free_jobs_data.free_nodes_pool);
+
+	hl_hw_queues_destroy(hdev);
+
+	/* Call ASIC S/W finalize function */
+	hdev->asic_funcs->sw_fini(hdev);
+
+	device_early_fini(hdev);
+
+	/* Hide devices and sysfs/debugfs files from user */
+	cdev_sysfs_debugfs_remove(hdev);
+	drm_dev_unregister(&hdev->drm);
+
+	hl_debugfs_device_fini(hdev);
+
+	pr_info("removed device successfully\n");
+}
+
+/*
+ * MMIO register access helper functions.
+ */
+
+/*
+ * hl_rreg - Read an MMIO register
+ *
+ * @hdev: pointer to habanalabs device structure
+ * @reg: MMIO register offset (in bytes)
+ *
+ * Returns the value of the MMIO register we are asked to read
+ *
+ */
+inline u32 hl_rreg(struct hl_device *hdev, u32 reg)
+{
+	u32 val = readl(hdev->rmmio + reg);
+
+	if (unlikely(trace_habanalabs_rreg32_enabled()))
+		trace_habanalabs_rreg32(&(hdev)->pdev->dev, reg, val);
+
+	return val;
+}
+
+/*
+ * hl_wreg - Write to an MMIO register
+ *
+ * @hdev: pointer to habanalabs device structure
+ * @reg: MMIO register offset (in bytes)
+ * @val: 32-bit value
+ *
+ * Writes the 32-bit value into the MMIO register
+ *
+ */
+inline void hl_wreg(struct hl_device *hdev, u32 reg, u32 val)
+{
+	if (unlikely(trace_habanalabs_wreg32_enabled()))
+		trace_habanalabs_wreg32(&(hdev)->pdev->dev, reg, val);
+
+	writel(val, hdev->rmmio + reg);
+}
+
+void hl_capture_razwi(struct hl_device *hdev, u64 addr, u16 *engine_id, u16 num_of_engines,
+			u8 flags)
+{
+	struct razwi_info *razwi_info = &hdev->captured_err_info.razwi_info;
+
+	if (num_of_engines > HL_RAZWI_MAX_NUM_OF_ENGINES_PER_RTR) {
+		dev_err(hdev->dev,
+				"Number of possible razwi initiators (%u) exceeded limit (%u)\n",
+				num_of_engines, HL_RAZWI_MAX_NUM_OF_ENGINES_PER_RTR);
+		return;
+	}
+
+	/* In case it's the first razwi since the device was opened, capture its parameters */
+	if (atomic_cmpxchg(&hdev->captured_err_info.razwi_info.razwi_detected, 0, 1))
+		return;
+
+	razwi_info->razwi.timestamp = ktime_to_ns(ktime_get());
+	razwi_info->razwi.addr = addr;
+	razwi_info->razwi.num_of_possible_engines = num_of_engines;
+	memcpy(&razwi_info->razwi.engine_id[0], &engine_id[0],
+			num_of_engines * sizeof(u16));
+	razwi_info->razwi.flags = flags;
+
+	razwi_info->razwi_info_available = true;
+}
+
+void hl_handle_razwi(struct hl_device *hdev, u64 addr, u16 *engine_id, u16 num_of_engines,
+			u8 flags, u64 *event_mask)
+{
+	hl_capture_razwi(hdev, addr, engine_id, num_of_engines, flags);
+
+	if (event_mask)
+		*event_mask |= HL_NOTIFIER_EVENT_RAZWI;
+}
+
+static void hl_capture_user_mappings(struct hl_device *hdev, bool is_pmmu)
+{
+	struct page_fault_info *pgf_info = &hdev->captured_err_info.page_fault_info;
+	struct hl_vm_phys_pg_pack *phys_pg_pack = NULL;
+	struct hl_vm_hash_node *hnode;
+	struct hl_userptr *userptr;
+	enum vm_type *vm_type;
+	struct hl_ctx *ctx;
+	u32 map_idx = 0;
+	int i;
+
+	/* Reset previous session count*/
+	pgf_info->num_of_user_mappings = 0;
+
+	ctx = hl_get_compute_ctx(hdev);
+	if (!ctx) {
+		dev_err(hdev->dev, "Can't get user context for user mappings\n");
+		return;
+	}
+
+	mutex_lock(&ctx->mem_hash_lock);
+	hash_for_each(ctx->mem_hash, i, hnode, node) {
+		vm_type = hnode->ptr;
+		if (((*vm_type == VM_TYPE_USERPTR) && is_pmmu) ||
+				((*vm_type == VM_TYPE_PHYS_PACK) && !is_pmmu))
+			pgf_info->num_of_user_mappings++;
+
+	}
+
+	if (!pgf_info->num_of_user_mappings)
+		goto finish;
+
+	/* In case we already allocated in previous session, need to release it before
+	 * allocating new buffer.
+	 */
+	vfree(pgf_info->user_mappings);
+	pgf_info->user_mappings =
+			vzalloc(pgf_info->num_of_user_mappings * sizeof(struct hl_user_mapping));
+	if (!pgf_info->user_mappings) {
+		pgf_info->num_of_user_mappings = 0;
+		goto finish;
+	}
+
+	hash_for_each(ctx->mem_hash, i, hnode, node) {
+		vm_type = hnode->ptr;
+		if ((*vm_type == VM_TYPE_USERPTR) && (is_pmmu)) {
+			userptr = hnode->ptr;
+			pgf_info->user_mappings[map_idx].dev_va = hnode->vaddr;
+			pgf_info->user_mappings[map_idx].size = userptr->size;
+			map_idx++;
+		} else if ((*vm_type == VM_TYPE_PHYS_PACK) && (!is_pmmu)) {
+			phys_pg_pack = hnode->ptr;
+			pgf_info->user_mappings[map_idx].dev_va = hnode->vaddr;
+			pgf_info->user_mappings[map_idx].size = phys_pg_pack->total_size;
+			map_idx++;
+		}
+	}
+finish:
+	mutex_unlock(&ctx->mem_hash_lock);
+	hl_ctx_put(ctx);
+}
+
+void hl_capture_page_fault(struct hl_device *hdev, u64 addr, u16 eng_id, bool is_pmmu)
+{
+	struct page_fault_info *pgf_info = &hdev->captured_err_info.page_fault_info;
+
+	/* Capture only the first page fault */
+	if (atomic_cmpxchg(&pgf_info->page_fault_detected, 0, 1))
+		return;
+
+	pgf_info->page_fault.timestamp = ktime_to_ns(ktime_get());
+	pgf_info->page_fault.addr = addr;
+	pgf_info->page_fault.engine_id = eng_id;
+	hl_capture_user_mappings(hdev, is_pmmu);
+
+	pgf_info->page_fault_info_available = true;
+}
+
+void hl_handle_page_fault(struct hl_device *hdev, u64 addr, u16 eng_id, bool is_pmmu,
+				u64 *event_mask)
+{
+	hl_capture_page_fault(hdev, addr, eng_id, is_pmmu);
+
+	if (event_mask)
+		*event_mask |=  HL_NOTIFIER_EVENT_PAGE_FAULT;
+}
+
+static void hl_capture_hw_err(struct hl_device *hdev, u16 event_id)
+{
+	struct hw_err_info *info = &hdev->captured_err_info.hw_err;
+
+	/* Capture only the first HW err */
+	if (atomic_cmpxchg(&info->event_detected, 0, 1))
+		return;
+
+	info->event.timestamp = ktime_to_ns(ktime_get());
+	info->event.event_id = event_id;
+
+	info->event_info_available = true;
+}
+
+void hl_handle_critical_hw_err(struct hl_device *hdev, u16 event_id, u64 *event_mask)
+{
+	hl_capture_hw_err(hdev, event_id);
+
+	if (event_mask)
+		*event_mask |= HL_NOTIFIER_EVENT_CRITICL_HW_ERR;
+}
+
+static void hl_capture_fw_err(struct hl_device *hdev, struct hl_info_fw_err_info *fw_info)
+{
+	struct fw_err_info *info = &hdev->captured_err_info.fw_err;
+
+	/* Capture only the first FW error */
+	if (atomic_cmpxchg(&info->event_detected, 0, 1))
+		return;
+
+	info->event.timestamp = ktime_to_ns(ktime_get());
+	info->event.err_type = fw_info->err_type;
+	if (fw_info->err_type == HL_INFO_FW_REPORTED_ERR)
+		info->event.event_id = fw_info->event_id;
+
+	info->event_info_available = true;
+}
+
+void hl_handle_fw_err(struct hl_device *hdev, struct hl_info_fw_err_info *info)
+{
+	hl_capture_fw_err(hdev, info);
+
+	if (info->event_mask)
+		*info->event_mask |= HL_NOTIFIER_EVENT_CRITICL_FW_ERR;
+}
+
+void hl_capture_engine_err(struct hl_device *hdev, u16 engine_id, u16 error_count)
+{
+	struct engine_err_info *info = &hdev->captured_err_info.engine_err;
+
+	/* Capture only the first engine error */
+	if (atomic_cmpxchg(&info->event_detected, 0, 1))
+		return;
+
+	info->event.timestamp = ktime_to_ns(ktime_get());
+	info->event.engine_id = engine_id;
+	info->event.error_count = error_count;
+	info->event_info_available = true;
+}
+
+void hl_enable_err_info_capture(struct hl_error_info *captured_err_info)
+{
+	vfree(captured_err_info->page_fault_info.user_mappings);
+	memset(captured_err_info, 0, sizeof(struct hl_error_info));
+	atomic_set(&captured_err_info->cs_timeout.write_enable, 1);
+	captured_err_info->undef_opcode.write_enable = true;
+}
+
+void hl_init_cpu_for_irq(struct hl_device *hdev)
+{
+#ifdef CONFIG_NUMA
+	struct cpumask *available_mask = &hdev->irq_affinity_mask;
+	int numa_node = hdev->pdev->dev.numa_node, i;
+	static struct cpumask cpu_mask;
+
+	if (numa_node < 0)
+		return;
+
+	if (!cpumask_and(&cpu_mask, cpumask_of_node(numa_node), cpu_online_mask)) {
+		dev_err(hdev->dev, "No available affinities in current numa node\n");
+		return;
+	}
+
+	/* Remove HT siblings */
+	for_each_cpu(i, &cpu_mask)
+		cpumask_set_cpu(cpumask_first(topology_sibling_cpumask(i)), available_mask);
+#endif
+}
+
+void hl_set_irq_affinity(struct hl_device *hdev, int irq)
+{
+	if (cpumask_empty(&hdev->irq_affinity_mask)) {
+		dev_dbg(hdev->dev, "affinity mask is empty\n");
+		return;
+	}
+
+	if (irq_set_affinity_and_hint(irq, &hdev->irq_affinity_mask))
+		dev_err(hdev->dev, "Failed setting irq %d affinity\n", irq);
+}
+
+void hl_eq_heartbeat_event_handle(struct hl_device *hdev)
+{
+	hdev->heartbeat_debug_info.heartbeat_event_counter++;
+	hdev->heartbeat_debug_info.last_eq_heartbeat_ts = ktime_get_real_seconds();
+	hdev->eq_heartbeat_received = true;
+}
+
+void hl_handle_clk_change_event(struct hl_device *hdev, u16 event_type, u64 *event_mask)
+{
+	struct hl_clk_throttle *clk_throttle = &hdev->clk_throttling;
+	ktime_t zero_time = ktime_set(0, 0);
+
+	mutex_lock(&clk_throttle->lock);
+
+	switch (event_type) {
+	case EQ_EVENT_POWER_EVT_START:
+		clk_throttle->current_reason |= HL_CLK_THROTTLE_POWER;
+		clk_throttle->aggregated_reason |= HL_CLK_THROTTLE_POWER;
+		clk_throttle->timestamp[HL_CLK_THROTTLE_TYPE_POWER].start = ktime_get();
+		clk_throttle->timestamp[HL_CLK_THROTTLE_TYPE_POWER].end = zero_time;
+		dev_dbg_ratelimited(hdev->dev, "Clock throttling due to power consumption\n");
+		break;
+
+	case EQ_EVENT_POWER_EVT_END:
+		clk_throttle->current_reason &= ~HL_CLK_THROTTLE_POWER;
+		clk_throttle->timestamp[HL_CLK_THROTTLE_TYPE_POWER].end = ktime_get();
+		dev_dbg_ratelimited(hdev->dev, "Power envelop is safe, back to optimal clock\n");
+		break;
+
+	case EQ_EVENT_THERMAL_EVT_START:
+		clk_throttle->current_reason |= HL_CLK_THROTTLE_THERMAL;
+		clk_throttle->aggregated_reason |= HL_CLK_THROTTLE_THERMAL;
+		clk_throttle->timestamp[HL_CLK_THROTTLE_TYPE_THERMAL].start = ktime_get();
+		clk_throttle->timestamp[HL_CLK_THROTTLE_TYPE_THERMAL].end = zero_time;
+		*event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR;
+		dev_info_ratelimited(hdev->dev, "Clock throttling due to overheating\n");
+		break;
+
+	case EQ_EVENT_THERMAL_EVT_END:
+		clk_throttle->current_reason &= ~HL_CLK_THROTTLE_THERMAL;
+		clk_throttle->timestamp[HL_CLK_THROTTLE_TYPE_THERMAL].end = ktime_get();
+		*event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR;
+		dev_info_ratelimited(hdev->dev, "Thermal envelop is safe, back to optimal clock\n");
+		break;
+
+	default:
+		dev_err(hdev->dev, "Received invalid clock change event %d\n", event_type);
+		break;
+	}
+
+	mutex_unlock(&clk_throttle->lock);
+}
+
+void hl_eq_cpld_shutdown_event_handle(struct hl_device *hdev, u16 event_id, u64 *event_mask)
+{
+	hl_handle_critical_hw_err(hdev, event_id, event_mask);
+	*event_mask |= HL_NOTIFIER_EVENT_DEVICE_UNAVAILABLE;
+
+	/* Avoid any new accesses to the H/W */
+	hdev->disabled = true;
+	hdev->cpld_shutdown = true;
+}
diff --git a/drivers/accel/habanalabs/common/firmware_if.c b/drivers/accel/habanalabs/common/firmware_if.c
new file mode 100644
index 000000000000..eeb6b2a80fc7
--- /dev/null
+++ b/drivers/accel/habanalabs/common/firmware_if.c
@@ -0,0 +1,3337 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Copyright 2016-2022 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ */
+
+#include "habanalabs.h"
+#include <linux/habanalabs/hl_boot_if.h>
+
+#include <linux/pci.h>
+#include <linux/firmware.h>
+#include <linux/crc32.h>
+#include <linux/slab.h>
+#include <linux/ctype.h>
+#include <linux/vmalloc.h>
+
+#include <trace/events/habanalabs.h>
+
+#define FW_FILE_MAX_SIZE		0x1400000 /* maximum size of 20MB */
+
+static char *comms_cmd_str_arr[COMMS_INVLD_LAST] = {
+	[COMMS_NOOP] = __stringify(COMMS_NOOP),
+	[COMMS_CLR_STS] = __stringify(COMMS_CLR_STS),
+	[COMMS_RST_STATE] = __stringify(COMMS_RST_STATE),
+	[COMMS_PREP_DESC] = __stringify(COMMS_PREP_DESC),
+	[COMMS_DATA_RDY] = __stringify(COMMS_DATA_RDY),
+	[COMMS_EXEC] = __stringify(COMMS_EXEC),
+	[COMMS_RST_DEV] = __stringify(COMMS_RST_DEV),
+	[COMMS_GOTO_WFE] = __stringify(COMMS_GOTO_WFE),
+	[COMMS_SKIP_BMC] = __stringify(COMMS_SKIP_BMC),
+	[COMMS_PREP_DESC_ELBI] = __stringify(COMMS_PREP_DESC_ELBI),
+};
+
+static char *comms_sts_str_arr[COMMS_STS_INVLD_LAST] = {
+	[COMMS_STS_NOOP] = __stringify(COMMS_STS_NOOP),
+	[COMMS_STS_ACK] = __stringify(COMMS_STS_ACK),
+	[COMMS_STS_OK] = __stringify(COMMS_STS_OK),
+	[COMMS_STS_ERR] = __stringify(COMMS_STS_ERR),
+	[COMMS_STS_VALID_ERR] = __stringify(COMMS_STS_VALID_ERR),
+	[COMMS_STS_TIMEOUT_ERR] = __stringify(COMMS_STS_TIMEOUT_ERR),
+};
+
+/**
+ * hl_fw_version_cmp() - compares the FW version to a specific version
+ *
+ * @hdev: pointer to hl_device structure
+ * @major: major number of a reference version
+ * @minor: minor number of a reference version
+ * @subminor: sub-minor number of a reference version
+ *
+ * Return 1 if FW version greater than the reference version, -1 if it's
+ *         smaller and 0 if versions are identical.
+ */
+int hl_fw_version_cmp(struct hl_device *hdev, u32 major, u32 minor, u32 subminor)
+{
+	if (hdev->fw_sw_major_ver != major)
+		return (hdev->fw_sw_major_ver > major) ? 1 : -1;
+
+	if (hdev->fw_sw_minor_ver != minor)
+		return (hdev->fw_sw_minor_ver > minor) ? 1 : -1;
+
+	if (hdev->fw_sw_sub_minor_ver != subminor)
+		return (hdev->fw_sw_sub_minor_ver > subminor) ? 1 : -1;
+
+	return 0;
+}
+
+static char *extract_fw_ver_from_str(const char *fw_str)
+{
+	char *str, *fw_ver, *whitespace;
+	u32 ver_offset;
+
+	fw_ver = kmalloc(VERSION_MAX_LEN, GFP_KERNEL);
+	if (!fw_ver)
+		return NULL;
+
+	str = strnstr(fw_str, "fw-", VERSION_MAX_LEN);
+	if (!str)
+		goto free_fw_ver;
+
+	/* Skip the fw- part */
+	str += 3;
+	ver_offset = str - fw_str;
+
+	/* Copy until the next whitespace */
+	whitespace = strnstr(str, " ", VERSION_MAX_LEN - ver_offset);
+	if (!whitespace)
+		goto free_fw_ver;
+
+	strscpy(fw_ver, str, whitespace - str + 1);
+
+	return fw_ver;
+
+free_fw_ver:
+	kfree(fw_ver);
+	return NULL;
+}
+
+/**
+ * extract_u32_until_given_char() - given a string of the format "<u32><char>*", extract the u32.
+ * @str: the given string
+ * @ver_num: the pointer to the extracted u32 to be returned to the caller.
+ * @given_char: the given char at the end of the u32 in the string
+ *
+ * Return: Upon success, return a pointer to the given_char in the string. Upon failure, return NULL
+ */
+static char *extract_u32_until_given_char(char *str, u32 *ver_num, char given_char)
+{
+	char num_str[8] = {}, *ch;
+
+	ch = strchrnul(str, given_char);
+	if (*ch == '\0' || ch == str || ch - str >= sizeof(num_str))
+		return NULL;
+
+	memcpy(num_str, str, ch - str);
+	if (kstrtou32(num_str, 10, ver_num))
+		return NULL;
+	return ch;
+}
+
+/**
+ * hl_get_sw_major_minor_subminor() - extract the FW's SW version major, minor, sub-minor
+ *				      from the version string
+ * @hdev: pointer to the hl_device
+ * @fw_str: the FW's version string
+ *
+ * The extracted version is set in the hdev fields: fw_sw_{major/minor/sub_minor}_ver.
+ *
+ * fw_str is expected to have one of two possible formats, examples:
+ * 1) 'Preboot version hl-gaudi2-1.9.0-fw-42.0.1-sec-3'
+ * 2) 'Preboot version hl-gaudi2-1.9.0-rc-fw-42.0.1-sec-3'
+ * In those examples, the SW major,minor,subminor are correspondingly: 1,9,0.
+ *
+ * Return: 0 for success or a negative error code for failure.
+ */
+static int hl_get_sw_major_minor_subminor(struct hl_device *hdev, const char *fw_str)
+{
+	char *end, *start;
+
+	end = strnstr(fw_str, "-rc-", VERSION_MAX_LEN);
+	if (end == fw_str)
+		return -EINVAL;
+
+	if (!end)
+		end = strnstr(fw_str, "-fw-", VERSION_MAX_LEN);
+
+	if (end == fw_str)
+		return -EINVAL;
+
+	if (!end)
+		return -EINVAL;
+
+	for (start = end - 1; start != fw_str; start--) {
+		if (*start == '-')
+			break;
+	}
+
+	if (start == fw_str)
+		return -EINVAL;
+
+	/* start/end point each to the starting and ending hyphen of the sw version e.g. -1.9.0- */
+	start++;
+	start = extract_u32_until_given_char(start, &hdev->fw_sw_major_ver, '.');
+	if (!start)
+		goto err_zero_ver;
+
+	start++;
+	start = extract_u32_until_given_char(start, &hdev->fw_sw_minor_ver, '.');
+	if (!start)
+		goto err_zero_ver;
+
+	start++;
+	start = extract_u32_until_given_char(start, &hdev->fw_sw_sub_minor_ver, '-');
+	if (!start)
+		goto err_zero_ver;
+
+	return 0;
+
+err_zero_ver:
+	hdev->fw_sw_major_ver = 0;
+	hdev->fw_sw_minor_ver = 0;
+	hdev->fw_sw_sub_minor_ver = 0;
+	return -EINVAL;
+}
+
+/**
+ * hl_get_preboot_major_minor() - extract the FW's version major, minor from the version string.
+ * @hdev: pointer to the hl_device
+ * @preboot_ver: the FW's version string
+ *
+ * preboot_ver is expected to be the format of <major>.<minor>.<sub minor>*, e.g: 42.0.1-sec-3
+ * The extracted version is set in the hdev fields: fw_inner_{major/minor}_ver.
+ *
+ * Return: 0 on success, negative error code for failure.
+ */
+static int hl_get_preboot_major_minor(struct hl_device *hdev, char *preboot_ver)
+{
+	preboot_ver = extract_u32_until_given_char(preboot_ver, &hdev->fw_inner_major_ver, '.');
+	if (!preboot_ver) {
+		dev_err(hdev->dev, "Error parsing preboot major version\n");
+		goto err_zero_ver;
+	}
+
+	preboot_ver++;
+
+	preboot_ver = extract_u32_until_given_char(preboot_ver, &hdev->fw_inner_minor_ver, '.');
+	if (!preboot_ver) {
+		dev_err(hdev->dev, "Error parsing preboot minor version\n");
+		goto err_zero_ver;
+	}
+	return 0;
+
+err_zero_ver:
+	hdev->fw_inner_major_ver = 0;
+	hdev->fw_inner_minor_ver = 0;
+	return -EINVAL;
+}
+
+static int hl_request_fw(struct hl_device *hdev,
+				const struct firmware **firmware_p,
+				const char *fw_name)
+{
+	size_t fw_size;
+	int rc;
+
+	rc = request_firmware(firmware_p, fw_name, hdev->dev);
+	if (rc) {
+		dev_err(hdev->dev, "Firmware file %s is not found! (error %d)\n",
+				fw_name, rc);
+		goto out;
+	}
+
+	fw_size = (*firmware_p)->size;
+	if ((fw_size % 4) != 0) {
+		dev_err(hdev->dev, "Illegal %s firmware size %zu\n",
+				fw_name, fw_size);
+		rc = -EINVAL;
+		goto release_fw;
+	}
+
+	dev_dbg(hdev->dev, "%s firmware size == %zu\n", fw_name, fw_size);
+
+	if (fw_size > FW_FILE_MAX_SIZE) {
+		dev_err(hdev->dev,
+			"FW file size %zu exceeds maximum of %u bytes\n",
+			fw_size, FW_FILE_MAX_SIZE);
+		rc = -EINVAL;
+		goto release_fw;
+	}
+
+	return 0;
+
+release_fw:
+	release_firmware(*firmware_p);
+out:
+	return rc;
+}
+
+/**
+ * hl_release_firmware() - release FW
+ *
+ * @fw: fw descriptor
+ *
+ * note: this inline function added to serve as a comprehensive mirror for the
+ *       hl_request_fw function.
+ */
+static inline void hl_release_firmware(const struct firmware *fw)
+{
+	release_firmware(fw);
+}
+
+/**
+ * hl_fw_copy_fw_to_device() - copy FW to device
+ *
+ * @hdev: pointer to hl_device structure.
+ * @fw: fw descriptor
+ * @dst: IO memory mapped address space to copy firmware to
+ * @src_offset: offset in src FW to copy from
+ * @size: amount of bytes to copy (0 to copy the whole binary)
+ *
+ * actual copy of FW binary data to device, shared by static and dynamic loaders
+ */
+static int hl_fw_copy_fw_to_device(struct hl_device *hdev,
+				const struct firmware *fw, void __iomem *dst,
+				u32 src_offset, u32 size)
+{
+	const void *fw_data;
+
+	/* size 0 indicates to copy the whole file */
+	if (!size)
+		size = fw->size;
+
+	if (src_offset + size > fw->size) {
+		dev_err(hdev->dev,
+			"size to copy(%u) and offset(%u) are invalid\n",
+			size, src_offset);
+		return -EINVAL;
+	}
+
+	fw_data = (const void *) fw->data;
+
+	memcpy_toio(dst, fw_data + src_offset, size);
+	return 0;
+}
+
+/**
+ * hl_fw_copy_msg_to_device() - copy message to device
+ *
+ * @hdev: pointer to hl_device structure.
+ * @msg: message
+ * @dst: IO memory mapped address space to copy firmware to
+ * @src_offset: offset in src message to copy from
+ * @size: amount of bytes to copy (0 to copy the whole binary)
+ *
+ * actual copy of message data to device.
+ */
+static int hl_fw_copy_msg_to_device(struct hl_device *hdev,
+		struct lkd_msg_comms *msg, void __iomem *dst,
+		u32 src_offset, u32 size)
+{
+	void *msg_data;
+
+	/* size 0 indicates to copy the whole file */
+	if (!size)
+		size = sizeof(struct lkd_msg_comms);
+
+	if (src_offset + size > sizeof(struct lkd_msg_comms)) {
+		dev_err(hdev->dev,
+			"size to copy(%u) and offset(%u) are invalid\n",
+			size, src_offset);
+		return -EINVAL;
+	}
+
+	msg_data = (void *) msg;
+
+	memcpy_toio(dst, msg_data + src_offset, size);
+
+	return 0;
+}
+
+/**
+ * hl_fw_load_fw_to_device() - Load F/W code to device's memory.
+ *
+ * @hdev: pointer to hl_device structure.
+ * @fw_name: the firmware image name
+ * @dst: IO memory mapped address space to copy firmware to
+ * @src_offset: offset in src FW to copy from
+ * @size: amount of bytes to copy (0 to copy the whole binary)
+ *
+ * Copy fw code from firmware file to device memory.
+ *
+ * Return: 0 on success, non-zero for failure.
+ */
+int hl_fw_load_fw_to_device(struct hl_device *hdev, const char *fw_name,
+				void __iomem *dst, u32 src_offset, u32 size)
+{
+	const struct firmware *fw;
+	int rc;
+
+	rc = hl_request_fw(hdev, &fw, fw_name);
+	if (rc)
+		return rc;
+
+	rc = hl_fw_copy_fw_to_device(hdev, fw, dst, src_offset, size);
+
+	hl_release_firmware(fw);
+	return rc;
+}
+
+int hl_fw_send_pci_access_msg(struct hl_device *hdev, u32 opcode, u64 value)
+{
+	struct cpucp_packet pkt = {};
+	int rc;
+
+	pkt.ctl = cpu_to_le32(opcode << CPUCP_PKT_CTL_OPCODE_SHIFT);
+	pkt.value = cpu_to_le64(value);
+
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), 0, NULL);
+	if (rc)
+		dev_err(hdev->dev, "Failed to disable FW's PCI access\n");
+
+	return rc;
+}
+
+/**
+ * hl_fw_send_cpu_message() - send CPU message to the device.
+ *
+ * @hdev: pointer to hl_device structure.
+ * @hw_queue_id: HW queue ID
+ * @msg: raw data of the message/packet
+ * @size: size of @msg in bytes
+ * @timeout_us: timeout in usec to wait for CPU reply on the message
+ * @result: return code reported by FW
+ *
+ * send message to the device CPU.
+ *
+ * Return: 0 on success, non-zero for failure.
+ *     -ENOMEM: memory allocation failure
+ *     -EAGAIN: CPU is disabled (try again when enabled)
+ *     -ETIMEDOUT: timeout waiting for FW response
+ *     -EIO: protocol error
+ */
+int hl_fw_send_cpu_message(struct hl_device *hdev, u32 hw_queue_id, u32 *msg,
+				u16 size, u32 timeout_us, u64 *result)
+{
+	struct hl_hw_queue *queue = &hdev->kernel_queues[hw_queue_id];
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	u32 tmp, expected_ack_val, pi, opcode;
+	struct cpucp_packet *pkt;
+	dma_addr_t pkt_dma_addr;
+	struct hl_bd *sent_bd;
+	int rc = 0, fw_rc;
+
+	pkt = hl_cpu_accessible_dma_pool_alloc(hdev, size, &pkt_dma_addr);
+	if (!pkt) {
+		dev_err(hdev->dev, "Failed to allocate DMA memory for packet to CPU\n");
+		return -ENOMEM;
+	}
+
+	memcpy(pkt, msg, size);
+
+	mutex_lock(&hdev->send_cpu_message_lock);
+
+	/* CPU-CP messages can be sent during soft-reset */
+	if (hdev->disabled && !hdev->reset_info.in_compute_reset)
+		goto out;
+
+	if (hdev->device_cpu_disabled) {
+		rc = -EAGAIN;
+		goto out;
+	}
+
+	/* set fence to a non valid value */
+	pkt->fence = cpu_to_le32(UINT_MAX);
+	pi = queue->pi;
+
+	/*
+	 * The CPU queue is a synchronous queue with an effective depth of
+	 * a single entry (although it is allocated with room for multiple
+	 * entries). We lock on it using 'send_cpu_message_lock' which
+	 * serializes accesses to the CPU queue.
+	 * Which means that we don't need to lock the access to the entire H/W
+	 * queues module when submitting a JOB to the CPU queue.
+	 */
+	hl_hw_queue_submit_bd(hdev, queue, hl_queue_inc_ptr(queue->pi), size, pkt_dma_addr);
+
+	if (prop->fw_app_cpu_boot_dev_sts0 & CPU_BOOT_DEV_STS0_PKT_PI_ACK_EN)
+		expected_ack_val = queue->pi;
+	else
+		expected_ack_val = CPUCP_PACKET_FENCE_VAL;
+
+	rc = hl_poll_timeout_memory(hdev, &pkt->fence, tmp,
+				(tmp == expected_ack_val), 1000,
+				timeout_us, true);
+
+	hl_hw_queue_inc_ci_kernel(hdev, hw_queue_id);
+
+	if (rc == -ETIMEDOUT) {
+		/* If FW performed reset just before sending it a packet, we will get a timeout.
+		 * This is expected behavior, hence no need for error message.
+		 */
+		if (!hl_device_operational(hdev, NULL) && !hdev->reset_info.in_compute_reset) {
+			dev_dbg(hdev->dev, "Device CPU packet timeout (0x%x) due to FW reset\n",
+					tmp);
+		} else {
+			struct hl_bd *bd = queue->kernel_address;
+
+			bd += hl_pi_2_offset(pi);
+
+			dev_err(hdev->dev, "Device CPU packet timeout (status = 0x%x)\n"
+				"Pkt info[%u]: dma_addr: 0x%llx, kernel_addr: %p, len:0x%x, ctl: 0x%x, ptr:0x%llx, dram_bd:%u\n",
+				tmp, pi, pkt_dma_addr, (void *)pkt, bd->len, bd->ctl, bd->ptr,
+				queue->dram_bd);
+		}
+		hdev->device_cpu_disabled = true;
+		goto out;
+	}
+
+	tmp = le32_to_cpu(pkt->ctl);
+
+	fw_rc = (tmp & CPUCP_PKT_CTL_RC_MASK) >> CPUCP_PKT_CTL_RC_SHIFT;
+	if (fw_rc) {
+		opcode = (tmp & CPUCP_PKT_CTL_OPCODE_MASK) >> CPUCP_PKT_CTL_OPCODE_SHIFT;
+
+		if (!prop->supports_advanced_cpucp_rc) {
+			dev_dbg(hdev->dev, "F/W ERROR %d for CPU packet %d\n", rc, opcode);
+			rc = -EIO;
+			goto scrub_descriptor;
+		}
+
+		switch (fw_rc) {
+		case cpucp_packet_invalid:
+			dev_err(hdev->dev,
+				"CPU packet %d is not supported by F/W\n", opcode);
+			break;
+		case cpucp_packet_fault:
+			dev_err(hdev->dev,
+				"F/W failed processing CPU packet %d\n", opcode);
+			break;
+		case cpucp_packet_invalid_pkt:
+			dev_dbg(hdev->dev,
+				"CPU packet %d is not supported by F/W\n", opcode);
+			break;
+		case cpucp_packet_invalid_params:
+			dev_err(hdev->dev,
+				"F/W reports invalid parameters for CPU packet %d\n", opcode);
+			break;
+
+		default:
+			dev_err(hdev->dev,
+				"Unknown F/W ERROR %d for CPU packet %d\n", rc, opcode);
+		}
+
+		/* propagate the return code from the f/w to the callers who want to check it */
+		if (result)
+			*result = fw_rc;
+
+		rc = -EIO;
+
+	} else if (result) {
+		*result = le64_to_cpu(pkt->result);
+	}
+
+scrub_descriptor:
+	/* Scrub previous buffer descriptor 'ctl' field which contains the
+	 * previous PI value written during packet submission.
+	 * We must do this or else F/W can read an old value upon queue wraparound.
+	 */
+	sent_bd = queue->kernel_address;
+	sent_bd += hl_pi_2_offset(pi);
+	sent_bd->ctl = cpu_to_le32(UINT_MAX);
+
+out:
+	mutex_unlock(&hdev->send_cpu_message_lock);
+
+	hl_cpu_accessible_dma_pool_free(hdev, size, pkt);
+
+	return rc;
+}
+
+int hl_fw_unmask_irq(struct hl_device *hdev, u16 event_type)
+{
+	struct cpucp_packet pkt;
+	u64 result;
+	int rc;
+
+	memset(&pkt, 0, sizeof(pkt));
+
+	pkt.ctl = cpu_to_le32(CPUCP_PACKET_UNMASK_RAZWI_IRQ <<
+				CPUCP_PKT_CTL_OPCODE_SHIFT);
+	pkt.value = cpu_to_le64(event_type);
+
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
+						0, &result);
+
+	if (rc)
+		dev_err(hdev->dev, "failed to unmask event %d", event_type);
+
+	return rc;
+}
+
+int hl_fw_unmask_irq_arr(struct hl_device *hdev, const u32 *irq_arr,
+		size_t irq_arr_size)
+{
+	struct cpucp_unmask_irq_arr_packet *pkt;
+	size_t total_pkt_size;
+	u64 result;
+	int rc;
+
+	total_pkt_size = sizeof(struct cpucp_unmask_irq_arr_packet) +
+			irq_arr_size;
+
+	/* data should be aligned to 8 bytes in order to CPU-CP to copy it */
+	total_pkt_size = (total_pkt_size + 0x7) & ~0x7;
+
+	/* total_pkt_size is casted to u16 later on */
+	if (total_pkt_size > USHRT_MAX) {
+		dev_err(hdev->dev, "too many elements in IRQ array\n");
+		return -EINVAL;
+	}
+
+	pkt = kzalloc(total_pkt_size, GFP_KERNEL);
+	if (!pkt)
+		return -ENOMEM;
+
+	pkt->length = cpu_to_le32(irq_arr_size / sizeof(irq_arr[0]));
+	memcpy(&pkt->irqs, irq_arr, irq_arr_size);
+
+	pkt->cpucp_pkt.ctl = cpu_to_le32(CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY <<
+						CPUCP_PKT_CTL_OPCODE_SHIFT);
+
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) pkt,
+						total_pkt_size, 0, &result);
+
+	if (rc)
+		dev_err(hdev->dev, "failed to unmask event array\n");
+
+	kfree(pkt);
+
+	return rc;
+}
+
+int hl_fw_test_cpu_queue(struct hl_device *hdev)
+{
+	struct cpucp_packet test_pkt = {};
+	u64 result = 0;
+	int rc;
+
+	test_pkt.ctl = cpu_to_le32(CPUCP_PACKET_TEST <<
+					CPUCP_PKT_CTL_OPCODE_SHIFT);
+	test_pkt.value = cpu_to_le64(CPUCP_PACKET_FENCE_VAL);
+
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &test_pkt,
+						sizeof(test_pkt), 0, &result);
+
+	if (!rc) {
+		if (result != CPUCP_PACKET_FENCE_VAL)
+			dev_err(hdev->dev,
+				"CPU queue test failed (%#08llx)\n", result);
+	} else {
+		dev_err(hdev->dev, "CPU queue test failed, error %d\n", rc);
+	}
+
+	return rc;
+}
+
+void *hl_fw_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, size_t size,
+						dma_addr_t *dma_handle)
+{
+	u64 kernel_addr;
+
+	kernel_addr = gen_pool_alloc(hdev->cpu_accessible_dma_pool, size);
+
+	*dma_handle = hdev->cpu_accessible_dma_address +
+		(kernel_addr - (u64) (uintptr_t) hdev->cpu_accessible_dma_mem);
+
+	return (void *) (uintptr_t) kernel_addr;
+}
+
+void hl_fw_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size,
+					void *vaddr)
+{
+	gen_pool_free(hdev->cpu_accessible_dma_pool, (u64) (uintptr_t) vaddr,
+			size);
+}
+
+int hl_fw_send_soft_reset(struct hl_device *hdev)
+{
+	struct cpucp_packet pkt;
+	int rc;
+
+	memset(&pkt, 0, sizeof(pkt));
+	pkt.ctl = cpu_to_le32(CPUCP_PACKET_SOFT_RESET << CPUCP_PKT_CTL_OPCODE_SHIFT);
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), 0, NULL);
+	if (rc)
+		dev_err(hdev->dev, "failed to send soft-reset msg (err = %d)\n", rc);
+
+	return rc;
+}
+
+int hl_fw_send_device_activity(struct hl_device *hdev, bool open)
+{
+	struct cpucp_packet pkt;
+	int rc;
+
+	memset(&pkt, 0, sizeof(pkt));
+	pkt.ctl = cpu_to_le32(CPUCP_PACKET_ACTIVE_STATUS_SET <<	CPUCP_PKT_CTL_OPCODE_SHIFT);
+	pkt.value = cpu_to_le64(open);
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), 0, NULL);
+	if (rc)
+		dev_err(hdev->dev, "failed to send device activity msg(%u)\n", open);
+
+	return rc;
+}
+
+int hl_fw_send_heartbeat(struct hl_device *hdev)
+{
+	struct cpucp_packet hb_pkt;
+	u64 result = 0;
+	int rc;
+
+	memset(&hb_pkt, 0, sizeof(hb_pkt));
+	hb_pkt.ctl = cpu_to_le32(CPUCP_PACKET_TEST << CPUCP_PKT_CTL_OPCODE_SHIFT);
+	hb_pkt.value = cpu_to_le64(CPUCP_PACKET_FENCE_VAL);
+
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &hb_pkt, sizeof(hb_pkt), 0, &result);
+
+	if ((rc) || (result != CPUCP_PACKET_FENCE_VAL))
+		return -EIO;
+
+	if (le32_to_cpu(hb_pkt.status_mask) &
+					CPUCP_PKT_HB_STATUS_EQ_FAULT_MASK) {
+		dev_warn(hdev->dev, "FW reported EQ fault during heartbeat\n");
+		rc = -EIO;
+	}
+
+	hdev->heartbeat_debug_info.last_pq_heartbeat_ts = ktime_get_real_seconds();
+
+	return rc;
+}
+
+static bool fw_report_boot_dev0(struct hl_device *hdev, u32 err_val, u32 sts_val)
+{
+	bool err_exists = false;
+
+	if (!(err_val & CPU_BOOT_ERR0_ENABLED))
+		return false;
+
+	if (err_val & CPU_BOOT_ERR0_DRAM_INIT_FAIL)
+		dev_err(hdev->dev, "Device boot error - DRAM initialization failed\n");
+
+	if (err_val & CPU_BOOT_ERR0_FIT_CORRUPTED)
+		dev_err(hdev->dev, "Device boot error - FIT image corrupted\n");
+
+	if (err_val & CPU_BOOT_ERR0_TS_INIT_FAIL)
+		dev_err(hdev->dev, "Device boot error - Thermal Sensor initialization failed\n");
+
+	if (err_val & CPU_BOOT_ERR0_BMC_WAIT_SKIPPED) {
+		if (hdev->bmc_enable) {
+			dev_err(hdev->dev, "Device boot error - Skipped waiting for BMC\n");
+		} else {
+			dev_info(hdev->dev, "Device boot message - Skipped waiting for BMC\n");
+			/* This is an info so we don't want it to disable the
+			 * device
+			 */
+			err_val &= ~CPU_BOOT_ERR0_BMC_WAIT_SKIPPED;
+		}
+	}
+
+	if (err_val & CPU_BOOT_ERR0_NIC_DATA_NOT_RDY)
+		dev_err(hdev->dev, "Device boot error - Serdes data from BMC not available\n");
+
+	if (err_val & CPU_BOOT_ERR0_NIC_FW_FAIL)
+		dev_err(hdev->dev, "Device boot error - NIC F/W initialization failed\n");
+
+	if (err_val & CPU_BOOT_ERR0_SECURITY_NOT_RDY)
+		dev_err(hdev->dev, "Device boot warning - security not ready\n");
+
+	if (err_val & CPU_BOOT_ERR0_SECURITY_FAIL)
+		dev_err(hdev->dev, "Device boot error - security failure\n");
+
+	if (err_val & CPU_BOOT_ERR0_EFUSE_FAIL)
+		dev_err(hdev->dev, "Device boot error - eFuse failure\n");
+
+	if (err_val & CPU_BOOT_ERR0_SEC_IMG_VER_FAIL)
+		dev_err(hdev->dev, "Device boot error - Failed to load preboot secondary image\n");
+
+	if (err_val & CPU_BOOT_ERR0_PLL_FAIL)
+		dev_err(hdev->dev, "Device boot error - PLL failure\n");
+
+	if (err_val & CPU_BOOT_ERR0_TMP_THRESH_INIT_FAIL)
+		dev_err(hdev->dev, "Device boot error - Failed to set threshold for temperature sensor\n");
+
+	if (err_val & CPU_BOOT_ERR0_DEVICE_UNUSABLE_FAIL) {
+		/* Ignore this bit, don't prevent driver loading */
+		dev_dbg(hdev->dev, "device unusable status is set\n");
+		err_val &= ~CPU_BOOT_ERR0_DEVICE_UNUSABLE_FAIL;
+	}
+
+	if (err_val & CPU_BOOT_ERR0_BINNING_FAIL)
+		dev_err(hdev->dev, "Device boot error - binning failure\n");
+
+	if (sts_val & CPU_BOOT_DEV_STS0_ENABLED)
+		dev_dbg(hdev->dev, "Device status0 %#x\n", sts_val);
+
+	if (err_val & CPU_BOOT_ERR0_DRAM_SKIPPED)
+		dev_err(hdev->dev, "Device boot warning - Skipped DRAM initialization\n");
+
+	if (err_val & CPU_BOOT_ERR_ENG_ARC_MEM_SCRUB_FAIL)
+		dev_err(hdev->dev, "Device boot error - ARC memory scrub failed\n");
+
+	/* All warnings should go here in order not to reach the unknown error validation */
+	if (err_val & CPU_BOOT_ERR0_EEPROM_FAIL) {
+		dev_err(hdev->dev, "Device boot error - EEPROM failure detected\n");
+		err_exists = true;
+	}
+
+	if (err_val & CPU_BOOT_ERR0_PRI_IMG_VER_FAIL)
+		dev_warn(hdev->dev, "Device boot warning - Failed to load preboot primary image\n");
+
+	if (err_val & CPU_BOOT_ERR0_TPM_FAIL)
+		dev_warn(hdev->dev, "Device boot warning - TPM failure\n");
+
+	if (err_val & CPU_BOOT_ERR_FATAL_MASK)
+		err_exists = true;
+
+	/* return error only if it's in the predefined mask */
+	if (err_exists && ((err_val & ~CPU_BOOT_ERR0_ENABLED) &
+				lower_32_bits(hdev->boot_error_status_mask)))
+		return true;
+
+	return false;
+}
+
+/* placeholder for ERR1 as no errors defined there yet */
+static bool fw_report_boot_dev1(struct hl_device *hdev, u32 err_val,
+								u32 sts_val)
+{
+	/*
+	 * keep this variable to preserve the logic of the function.
+	 * this way it would require less modifications when error will be
+	 * added to DEV_ERR1
+	 */
+	bool err_exists = false;
+
+	if (!(err_val & CPU_BOOT_ERR1_ENABLED))
+		return false;
+
+	if (sts_val & CPU_BOOT_DEV_STS1_ENABLED)
+		dev_dbg(hdev->dev, "Device status1 %#x\n", sts_val);
+
+	if (!err_exists && (err_val & ~CPU_BOOT_ERR1_ENABLED)) {
+		dev_err(hdev->dev,
+			"Device boot error - unknown ERR1 error 0x%08x\n",
+								err_val);
+		err_exists = true;
+	}
+
+	/* return error only if it's in the predefined mask */
+	if (err_exists && ((err_val & ~CPU_BOOT_ERR1_ENABLED) &
+				upper_32_bits(hdev->boot_error_status_mask)))
+		return true;
+
+	return false;
+}
+
+static int fw_read_errors(struct hl_device *hdev, u32 boot_err0_reg,
+				u32 boot_err1_reg, u32 cpu_boot_dev_status0_reg,
+				u32 cpu_boot_dev_status1_reg)
+{
+	u32 err_val, status_val;
+	bool err_exists = false;
+
+	/* Some of the firmware status codes are deprecated in newer f/w
+	 * versions. In those versions, the errors are reported
+	 * in different registers. Therefore, we need to check those
+	 * registers and print the exact errors. Moreover, there
+	 * may be multiple errors, so we need to report on each error
+	 * separately. Some of the error codes might indicate a state
+	 * that is not an error per-se, but it is an error in production
+	 * environment
+	 */
+	err_val = RREG32(boot_err0_reg);
+	status_val = RREG32(cpu_boot_dev_status0_reg);
+	err_exists = fw_report_boot_dev0(hdev, err_val, status_val);
+
+	err_val = RREG32(boot_err1_reg);
+	status_val = RREG32(cpu_boot_dev_status1_reg);
+	err_exists |= fw_report_boot_dev1(hdev, err_val, status_val);
+
+	if (err_exists)
+		return -EIO;
+
+	return 0;
+}
+
+int hl_fw_cpucp_info_get(struct hl_device *hdev,
+				u32 sts_boot_dev_sts0_reg,
+				u32 sts_boot_dev_sts1_reg, u32 boot_err0_reg,
+				u32 boot_err1_reg)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct cpucp_packet pkt = {};
+	dma_addr_t cpucp_info_dma_addr;
+	void *cpucp_info_cpu_addr;
+	char *kernel_ver;
+	u64 result;
+	int rc;
+
+	cpucp_info_cpu_addr = hl_cpu_accessible_dma_pool_alloc(hdev, sizeof(struct cpucp_info),
+								&cpucp_info_dma_addr);
+	if (!cpucp_info_cpu_addr) {
+		dev_err(hdev->dev,
+			"Failed to allocate DMA memory for CPU-CP info packet\n");
+		return -ENOMEM;
+	}
+
+	memset(cpucp_info_cpu_addr, 0, sizeof(struct cpucp_info));
+
+	pkt.ctl = cpu_to_le32(CPUCP_PACKET_INFO_GET <<
+				CPUCP_PKT_CTL_OPCODE_SHIFT);
+	pkt.addr = cpu_to_le64(cpucp_info_dma_addr);
+	pkt.data_max_size = cpu_to_le32(sizeof(struct cpucp_info));
+
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
+					HL_CPUCP_INFO_TIMEOUT_USEC, &result);
+	if (rc) {
+		dev_err(hdev->dev,
+			"Failed to handle CPU-CP info pkt, error %d\n", rc);
+		goto out;
+	}
+
+	rc = fw_read_errors(hdev, boot_err0_reg, boot_err1_reg,
+				sts_boot_dev_sts0_reg, sts_boot_dev_sts1_reg);
+	if (rc) {
+		dev_err(hdev->dev, "Errors in device boot\n");
+		goto out;
+	}
+
+	memcpy(&prop->cpucp_info, cpucp_info_cpu_addr,
+			sizeof(prop->cpucp_info));
+
+	rc = hl_build_hwmon_channel_info(hdev, prop->cpucp_info.sensors);
+	if (rc) {
+		dev_err(hdev->dev,
+			"Failed to build hwmon channel info, error %d\n", rc);
+		rc = -EFAULT;
+		goto out;
+	}
+
+	kernel_ver = extract_fw_ver_from_str(prop->cpucp_info.kernel_version);
+	if (kernel_ver) {
+		dev_info(hdev->dev, "Linux version %s", kernel_ver);
+		kfree(kernel_ver);
+	}
+
+	/* assume EQ code doesn't need to check eqe index */
+	hdev->event_queue.check_eqe_index = false;
+
+	/* Read FW application security bits again */
+	if (prop->fw_cpu_boot_dev_sts0_valid) {
+		prop->fw_app_cpu_boot_dev_sts0 = RREG32(sts_boot_dev_sts0_reg);
+		if (prop->fw_app_cpu_boot_dev_sts0 &
+				CPU_BOOT_DEV_STS0_EQ_INDEX_EN)
+			hdev->event_queue.check_eqe_index = true;
+	}
+
+	if (prop->fw_cpu_boot_dev_sts1_valid)
+		prop->fw_app_cpu_boot_dev_sts1 = RREG32(sts_boot_dev_sts1_reg);
+
+out:
+	hl_cpu_accessible_dma_pool_free(hdev, sizeof(struct cpucp_info), cpucp_info_cpu_addr);
+
+	return rc;
+}
+
+static int hl_fw_send_msi_info_msg(struct hl_device *hdev)
+{
+	struct cpucp_array_data_packet *pkt;
+	size_t total_pkt_size, data_size;
+	u64 result = 0;
+	int rc;
+
+	/* skip sending this info for unsupported ASICs */
+	if (!hdev->asic_funcs->get_msi_info)
+		return 0;
+
+	data_size = CPUCP_NUM_OF_MSI_TYPES * sizeof(u32);
+	total_pkt_size = sizeof(struct cpucp_array_data_packet) + data_size;
+
+	/* data should be aligned to 8 bytes in order to CPU-CP to copy it */
+	total_pkt_size = (total_pkt_size + 0x7) & ~0x7;
+
+	/* total_pkt_size is casted to u16 later on */
+	if (total_pkt_size > USHRT_MAX) {
+		dev_err(hdev->dev, "CPUCP array data is too big\n");
+		return -EINVAL;
+	}
+
+	pkt = kzalloc(total_pkt_size, GFP_KERNEL);
+	if (!pkt)
+		return -ENOMEM;
+
+	pkt->length = cpu_to_le32(CPUCP_NUM_OF_MSI_TYPES);
+
+	memset((void *) &pkt->data, 0xFF, data_size);
+	hdev->asic_funcs->get_msi_info(pkt->data);
+
+	pkt->cpucp_pkt.ctl = cpu_to_le32(CPUCP_PACKET_MSI_INFO_SET <<
+						CPUCP_PKT_CTL_OPCODE_SHIFT);
+
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *)pkt,
+						total_pkt_size, 0, &result);
+
+	/*
+	 * in case packet result is invalid it means that FW does not support
+	 * this feature and will use default/hard coded MSI values. no reason
+	 * to stop the boot
+	 */
+	if (rc && result == cpucp_packet_invalid)
+		rc = 0;
+
+	if (rc)
+		dev_err(hdev->dev, "failed to send CPUCP array data\n");
+
+	kfree(pkt);
+
+	return rc;
+}
+
+int hl_fw_cpucp_handshake(struct hl_device *hdev,
+				u32 sts_boot_dev_sts0_reg,
+				u32 sts_boot_dev_sts1_reg, u32 boot_err0_reg,
+				u32 boot_err1_reg)
+{
+	int rc;
+
+	rc = hl_fw_cpucp_info_get(hdev, sts_boot_dev_sts0_reg,
+					sts_boot_dev_sts1_reg, boot_err0_reg,
+					boot_err1_reg);
+	if (rc)
+		return rc;
+
+	return hl_fw_send_msi_info_msg(hdev);
+}
+
+int hl_fw_get_eeprom_data(struct hl_device *hdev, void *data, size_t max_size)
+{
+	struct cpucp_packet pkt = {};
+	void *eeprom_info_cpu_addr;
+	dma_addr_t eeprom_info_dma_addr;
+	u64 result;
+	int rc;
+
+	eeprom_info_cpu_addr = hl_cpu_accessible_dma_pool_alloc(hdev, max_size,
+									&eeprom_info_dma_addr);
+	if (!eeprom_info_cpu_addr) {
+		dev_err(hdev->dev,
+			"Failed to allocate DMA memory for CPU-CP EEPROM packet\n");
+		return -ENOMEM;
+	}
+
+	memset(eeprom_info_cpu_addr, 0, max_size);
+
+	pkt.ctl = cpu_to_le32(CPUCP_PACKET_EEPROM_DATA_GET <<
+				CPUCP_PKT_CTL_OPCODE_SHIFT);
+	pkt.addr = cpu_to_le64(eeprom_info_dma_addr);
+	pkt.data_max_size = cpu_to_le32(max_size);
+
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
+			HL_CPUCP_EEPROM_TIMEOUT_USEC, &result);
+	if (rc) {
+		if (rc != -EAGAIN)
+			dev_err(hdev->dev,
+				"Failed to handle CPU-CP EEPROM packet, error %d\n", rc);
+		goto out;
+	}
+
+	/* result contains the actual size */
+	memcpy(data, eeprom_info_cpu_addr, min((size_t)result, max_size));
+
+out:
+	hl_cpu_accessible_dma_pool_free(hdev, max_size, eeprom_info_cpu_addr);
+
+	return rc;
+}
+
+int hl_fw_get_monitor_dump(struct hl_device *hdev, void *data)
+{
+	struct cpucp_monitor_dump *mon_dump_cpu_addr;
+	dma_addr_t mon_dump_dma_addr;
+	struct cpucp_packet pkt = {};
+	size_t data_size;
+	__le32 *src_ptr;
+	u32 *dst_ptr;
+	u64 result;
+	int i, rc;
+
+	data_size = sizeof(struct cpucp_monitor_dump);
+	mon_dump_cpu_addr = hl_cpu_accessible_dma_pool_alloc(hdev, data_size, &mon_dump_dma_addr);
+	if (!mon_dump_cpu_addr) {
+		dev_err(hdev->dev,
+			"Failed to allocate DMA memory for CPU-CP monitor-dump packet\n");
+		return -ENOMEM;
+	}
+
+	memset(mon_dump_cpu_addr, 0, data_size);
+
+	pkt.ctl = cpu_to_le32(CPUCP_PACKET_MONITOR_DUMP_GET << CPUCP_PKT_CTL_OPCODE_SHIFT);
+	pkt.addr = cpu_to_le64(mon_dump_dma_addr);
+	pkt.data_max_size = cpu_to_le32(data_size);
+
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
+							HL_CPUCP_MON_DUMP_TIMEOUT_USEC, &result);
+	if (rc) {
+		if (rc != -EAGAIN)
+			dev_err(hdev->dev,
+				"Failed to handle CPU-CP monitor-dump packet, error %d\n", rc);
+		goto out;
+	}
+
+	/* result contains the actual size */
+	src_ptr = (__le32 *) mon_dump_cpu_addr;
+	dst_ptr = data;
+	for (i = 0; i < (data_size / sizeof(u32)); i++) {
+		*dst_ptr = le32_to_cpu(*src_ptr);
+		src_ptr++;
+		dst_ptr++;
+	}
+
+out:
+	hl_cpu_accessible_dma_pool_free(hdev, data_size, mon_dump_cpu_addr);
+
+	return rc;
+}
+
+int hl_fw_cpucp_pci_counters_get(struct hl_device *hdev,
+		struct hl_info_pci_counters *counters)
+{
+	struct cpucp_packet pkt = {};
+	u64 result;
+	int rc;
+
+	pkt.ctl = cpu_to_le32(CPUCP_PACKET_PCIE_THROUGHPUT_GET <<
+			CPUCP_PKT_CTL_OPCODE_SHIFT);
+
+	/* Fetch PCI rx counter */
+	pkt.index = cpu_to_le32(cpucp_pcie_throughput_rx);
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
+					HL_CPUCP_INFO_TIMEOUT_USEC, &result);
+	if (rc) {
+		if (rc != -EAGAIN)
+			dev_err(hdev->dev,
+				"Failed to handle CPU-CP PCI info pkt, error %d\n", rc);
+		return rc;
+	}
+	counters->rx_throughput = result;
+
+	memset(&pkt, 0, sizeof(pkt));
+	pkt.ctl = cpu_to_le32(CPUCP_PACKET_PCIE_THROUGHPUT_GET <<
+			CPUCP_PKT_CTL_OPCODE_SHIFT);
+
+	/* Fetch PCI tx counter */
+	pkt.index = cpu_to_le32(cpucp_pcie_throughput_tx);
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
+					HL_CPUCP_INFO_TIMEOUT_USEC, &result);
+	if (rc) {
+		if (rc != -EAGAIN)
+			dev_err(hdev->dev,
+				"Failed to handle CPU-CP PCI info pkt, error %d\n", rc);
+		return rc;
+	}
+	counters->tx_throughput = result;
+
+	/* Fetch PCI replay counter */
+	memset(&pkt, 0, sizeof(pkt));
+	pkt.ctl = cpu_to_le32(CPUCP_PACKET_PCIE_REPLAY_CNT_GET <<
+			CPUCP_PKT_CTL_OPCODE_SHIFT);
+
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
+			HL_CPUCP_INFO_TIMEOUT_USEC, &result);
+	if (rc) {
+		if (rc != -EAGAIN)
+			dev_err(hdev->dev,
+				"Failed to handle CPU-CP PCI info pkt, error %d\n", rc);
+		return rc;
+	}
+	counters->replay_cnt = (u32) result;
+
+	return rc;
+}
+
+int hl_fw_cpucp_total_energy_get(struct hl_device *hdev, u64 *total_energy)
+{
+	struct cpucp_packet pkt = {};
+	u64 result;
+	int rc;
+
+	pkt.ctl = cpu_to_le32(CPUCP_PACKET_TOTAL_ENERGY_GET <<
+				CPUCP_PKT_CTL_OPCODE_SHIFT);
+
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
+					HL_CPUCP_INFO_TIMEOUT_USEC, &result);
+	if (rc) {
+		if (rc != -EAGAIN)
+			dev_err(hdev->dev,
+				"Failed to handle CpuCP total energy pkt, error %d\n", rc);
+		return rc;
+	}
+
+	*total_energy = result;
+
+	return rc;
+}
+
+int get_used_pll_index(struct hl_device *hdev, u32 input_pll_index,
+						enum pll_index *pll_index)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	u8 pll_byte, pll_bit_off;
+	bool dynamic_pll;
+	int fw_pll_idx;
+
+	dynamic_pll = !!(prop->fw_app_cpu_boot_dev_sts0 &
+						CPU_BOOT_DEV_STS0_DYN_PLL_EN);
+
+	if (!dynamic_pll) {
+		/*
+		 * in case we are working with legacy FW (each asic has unique
+		 * PLL numbering) use the driver based index as they are
+		 * aligned with fw legacy numbering
+		 */
+		*pll_index = input_pll_index;
+		return 0;
+	}
+
+	/* retrieve a FW compatible PLL index based on
+	 * ASIC specific user request
+	 */
+	fw_pll_idx = hdev->asic_funcs->map_pll_idx_to_fw_idx(input_pll_index);
+	if (fw_pll_idx < 0) {
+		dev_err(hdev->dev, "Invalid PLL index (%u) error %d\n",
+			input_pll_index, fw_pll_idx);
+		return -EINVAL;
+	}
+
+	/* PLL map is a u8 array */
+	pll_byte = prop->cpucp_info.pll_map[fw_pll_idx >> 3];
+	pll_bit_off = fw_pll_idx & 0x7;
+
+	if (!(pll_byte & BIT(pll_bit_off))) {
+		dev_err(hdev->dev, "PLL index %d is not supported\n",
+			fw_pll_idx);
+		return -EINVAL;
+	}
+
+	*pll_index = fw_pll_idx;
+
+	return 0;
+}
+
+int hl_fw_cpucp_pll_info_get(struct hl_device *hdev, u32 pll_index,
+		u16 *pll_freq_arr)
+{
+	struct cpucp_packet pkt;
+	enum pll_index used_pll_idx;
+	u64 result;
+	int rc;
+
+	rc = get_used_pll_index(hdev, pll_index, &used_pll_idx);
+	if (rc)
+		return rc;
+
+	memset(&pkt, 0, sizeof(pkt));
+
+	pkt.ctl = cpu_to_le32(CPUCP_PACKET_PLL_INFO_GET <<
+				CPUCP_PKT_CTL_OPCODE_SHIFT);
+	pkt.pll_type = __cpu_to_le16((u16)used_pll_idx);
+
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
+			HL_CPUCP_INFO_TIMEOUT_USEC, &result);
+	if (rc) {
+		if (rc != -EAGAIN)
+			dev_err(hdev->dev, "Failed to read PLL info, error %d\n", rc);
+		return rc;
+	}
+
+	pll_freq_arr[0] = FIELD_GET(CPUCP_PKT_RES_PLL_OUT0_MASK, result);
+	pll_freq_arr[1] = FIELD_GET(CPUCP_PKT_RES_PLL_OUT1_MASK, result);
+	pll_freq_arr[2] = FIELD_GET(CPUCP_PKT_RES_PLL_OUT2_MASK, result);
+	pll_freq_arr[3] = FIELD_GET(CPUCP_PKT_RES_PLL_OUT3_MASK, result);
+
+	return 0;
+}
+
+int hl_fw_cpucp_power_get(struct hl_device *hdev, u64 *power)
+{
+	struct cpucp_packet pkt;
+	u64 result;
+	int rc;
+
+	memset(&pkt, 0, sizeof(pkt));
+
+	pkt.ctl = cpu_to_le32(CPUCP_PACKET_POWER_GET <<
+				CPUCP_PKT_CTL_OPCODE_SHIFT);
+	pkt.type = cpu_to_le16(CPUCP_POWER_INPUT);
+
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
+			HL_CPUCP_INFO_TIMEOUT_USEC, &result);
+	if (rc) {
+		if (rc != -EAGAIN)
+			dev_err(hdev->dev, "Failed to read power, error %d\n", rc);
+		return rc;
+	}
+
+	*power = result;
+
+	return rc;
+}
+
+int hl_fw_dram_replaced_row_get(struct hl_device *hdev,
+				struct cpucp_hbm_row_info *info)
+{
+	struct cpucp_hbm_row_info *cpucp_repl_rows_info_cpu_addr;
+	dma_addr_t cpucp_repl_rows_info_dma_addr;
+	struct cpucp_packet pkt = {};
+	u64 result;
+	int rc;
+
+	cpucp_repl_rows_info_cpu_addr = hl_cpu_accessible_dma_pool_alloc(hdev,
+							sizeof(struct cpucp_hbm_row_info),
+							&cpucp_repl_rows_info_dma_addr);
+	if (!cpucp_repl_rows_info_cpu_addr) {
+		dev_err(hdev->dev,
+			"Failed to allocate DMA memory for CPU-CP replaced rows info packet\n");
+		return -ENOMEM;
+	}
+
+	memset(cpucp_repl_rows_info_cpu_addr, 0, sizeof(struct cpucp_hbm_row_info));
+
+	pkt.ctl = cpu_to_le32(CPUCP_PACKET_HBM_REPLACED_ROWS_INFO_GET <<
+					CPUCP_PKT_CTL_OPCODE_SHIFT);
+	pkt.addr = cpu_to_le64(cpucp_repl_rows_info_dma_addr);
+	pkt.data_max_size = cpu_to_le32(sizeof(struct cpucp_hbm_row_info));
+
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
+					HL_CPUCP_INFO_TIMEOUT_USEC, &result);
+	if (rc) {
+		if (rc != -EAGAIN)
+			dev_err(hdev->dev,
+				"Failed to handle CPU-CP replaced rows info pkt, error %d\n", rc);
+		goto out;
+	}
+
+	memcpy(info, cpucp_repl_rows_info_cpu_addr, sizeof(*info));
+
+out:
+	hl_cpu_accessible_dma_pool_free(hdev, sizeof(struct cpucp_hbm_row_info),
+						cpucp_repl_rows_info_cpu_addr);
+
+	return rc;
+}
+
+int hl_fw_dram_pending_row_get(struct hl_device *hdev, u32 *pend_rows_num)
+{
+	struct cpucp_packet pkt;
+	u64 result;
+	int rc;
+
+	memset(&pkt, 0, sizeof(pkt));
+
+	pkt.ctl = cpu_to_le32(CPUCP_PACKET_HBM_PENDING_ROWS_STATUS << CPUCP_PKT_CTL_OPCODE_SHIFT);
+
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), 0, &result);
+	if (rc) {
+		if (rc != -EAGAIN)
+			dev_err(hdev->dev,
+				"Failed to handle CPU-CP pending rows info pkt, error %d\n", rc);
+		goto out;
+	}
+
+	*pend_rows_num = (u32) result;
+out:
+	return rc;
+}
+
+int hl_fw_cpucp_engine_core_asid_set(struct hl_device *hdev, u32 asid)
+{
+	struct cpucp_packet pkt;
+	int rc;
+
+	memset(&pkt, 0, sizeof(pkt));
+
+	pkt.ctl = cpu_to_le32(CPUCP_PACKET_ENGINE_CORE_ASID_SET << CPUCP_PKT_CTL_OPCODE_SHIFT);
+	pkt.value = cpu_to_le64(asid);
+
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
+						HL_CPUCP_INFO_TIMEOUT_USEC, NULL);
+	if (rc)
+		dev_err(hdev->dev,
+			"Failed on ASID configuration request for engine core, error %d\n",
+			rc);
+
+	return rc;
+}
+
+void hl_fw_ask_hard_reset_without_linux(struct hl_device *hdev)
+{
+	struct static_fw_load_mgr *static_loader =
+			&hdev->fw_loader.static_loader;
+	int rc;
+
+	if (hdev->asic_prop.dynamic_fw_load) {
+		rc = hl_fw_dynamic_send_protocol_cmd(hdev, &hdev->fw_loader,
+				COMMS_RST_DEV, 0, false,
+				hdev->fw_loader.cpu_timeout);
+		if (rc)
+			dev_err(hdev->dev, "Failed sending COMMS_RST_DEV\n");
+	} else {
+		WREG32(static_loader->kmd_msg_to_cpu_reg, KMD_MSG_RST_DEV);
+	}
+}
+
+void hl_fw_ask_halt_machine_without_linux(struct hl_device *hdev)
+{
+	struct fw_load_mgr *fw_loader = &hdev->fw_loader;
+	u32 status, cpu_boot_status_reg, cpu_timeout;
+	struct static_fw_load_mgr *static_loader;
+	struct pre_fw_load_props *pre_fw_load;
+	int rc;
+
+	if (hdev->device_cpu_is_halted)
+		return;
+
+	/* Stop device CPU to make sure nothing bad happens */
+	if (hdev->asic_prop.dynamic_fw_load) {
+		pre_fw_load = &fw_loader->pre_fw_load;
+		cpu_timeout = fw_loader->cpu_timeout;
+		cpu_boot_status_reg = pre_fw_load->cpu_boot_status_reg;
+
+		rc = hl_fw_dynamic_send_protocol_cmd(hdev, &hdev->fw_loader,
+				COMMS_GOTO_WFE, 0, false, cpu_timeout);
+		if (rc) {
+			dev_err(hdev->dev, "Failed sending COMMS_GOTO_WFE\n");
+		} else {
+			rc = hl_poll_timeout(
+				hdev,
+				cpu_boot_status_reg,
+				status,
+				status == CPU_BOOT_STATUS_IN_WFE,
+				hdev->fw_poll_interval_usec,
+				cpu_timeout);
+			if (rc)
+				dev_err(hdev->dev, "Current status=%u. Timed-out updating to WFE\n",
+						status);
+		}
+	} else {
+		static_loader = &hdev->fw_loader.static_loader;
+		WREG32(static_loader->kmd_msg_to_cpu_reg, KMD_MSG_GOTO_WFE);
+		msleep(static_loader->cpu_reset_wait_msec);
+
+		/* Must clear this register in order to prevent preboot
+		 * from reading WFE after reboot
+		 */
+		WREG32(static_loader->kmd_msg_to_cpu_reg, KMD_MSG_NA);
+	}
+
+	hdev->device_cpu_is_halted = true;
+}
+
+static void detect_cpu_boot_status(struct hl_device *hdev, u32 status)
+{
+	/* Some of the status codes below are deprecated in newer f/w
+	 * versions but we keep them here for backward compatibility
+	 */
+	switch (status) {
+	case CPU_BOOT_STATUS_NA:
+		dev_err(hdev->dev,
+			"Device boot progress - BTL/ROM did NOT run\n");
+		break;
+	case CPU_BOOT_STATUS_IN_WFE:
+		dev_err(hdev->dev,
+			"Device boot progress - Stuck inside WFE loop\n");
+		break;
+	case CPU_BOOT_STATUS_IN_BTL:
+		dev_err(hdev->dev,
+			"Device boot progress - Stuck in BTL\n");
+		break;
+	case CPU_BOOT_STATUS_IN_PREBOOT:
+		dev_err(hdev->dev,
+			"Device boot progress - Stuck in Preboot\n");
+		break;
+	case CPU_BOOT_STATUS_IN_SPL:
+		dev_err(hdev->dev,
+			"Device boot progress - Stuck in SPL\n");
+		break;
+	case CPU_BOOT_STATUS_IN_UBOOT:
+		dev_err(hdev->dev,
+			"Device boot progress - Stuck in u-boot\n");
+		break;
+	case CPU_BOOT_STATUS_DRAM_INIT_FAIL:
+		dev_err(hdev->dev,
+			"Device boot progress - DRAM initialization failed\n");
+		break;
+	case CPU_BOOT_STATUS_UBOOT_NOT_READY:
+		dev_err(hdev->dev,
+			"Device boot progress - Cannot boot\n");
+		break;
+	case CPU_BOOT_STATUS_TS_INIT_FAIL:
+		dev_err(hdev->dev,
+			"Device boot progress - Thermal Sensor initialization failed\n");
+		break;
+	case CPU_BOOT_STATUS_SECURITY_READY:
+		dev_err(hdev->dev,
+			"Device boot progress - Stuck in preboot after security initialization\n");
+		break;
+	case CPU_BOOT_STATUS_FW_SHUTDOWN_PREP:
+		dev_err(hdev->dev,
+			"Device boot progress - Stuck in preparation for shutdown\n");
+		break;
+	default:
+		dev_err(hdev->dev,
+			"Device boot progress - Invalid or unexpected status code %d\n", status);
+		break;
+	}
+}
+
+int hl_fw_wait_preboot_ready(struct hl_device *hdev)
+{
+	struct pre_fw_load_props *pre_fw_load = &hdev->fw_loader.pre_fw_load;
+	u32 status = 0, timeout;
+	int rc, tries = 1, fw_err = 0;
+	bool preboot_still_runs;
+
+	/* Need to check two possible scenarios:
+	 *
+	 * CPU_BOOT_STATUS_WAITING_FOR_BOOT_FIT - for newer firmwares where
+	 * the preboot is waiting for the boot fit
+	 *
+	 * All other status values - for older firmwares where the uboot was
+	 * loaded from the FLASH
+	 */
+	timeout = pre_fw_load->wait_for_preboot_timeout;
+retry:
+	rc = hl_poll_timeout(
+		hdev,
+		pre_fw_load->cpu_boot_status_reg,
+		status,
+		(status == CPU_BOOT_STATUS_NIC_FW_RDY) ||
+		(status == CPU_BOOT_STATUS_READY_TO_BOOT) ||
+		(status == CPU_BOOT_STATUS_WAITING_FOR_BOOT_FIT),
+		hdev->fw_poll_interval_usec,
+		timeout);
+	/*
+	 * if F/W reports "security-ready" it means preboot might take longer.
+	 * If the field 'wait_for_preboot_extended_timeout' is non 0 we wait again
+	 * with that timeout
+	 */
+	preboot_still_runs = (status == CPU_BOOT_STATUS_SECURITY_READY ||
+				status == CPU_BOOT_STATUS_IN_PREBOOT ||
+				status == CPU_BOOT_STATUS_FW_SHUTDOWN_PREP ||
+				status == CPU_BOOT_STATUS_DRAM_RDY);
+
+	if (rc && tries && preboot_still_runs) {
+		tries--;
+		if (pre_fw_load->wait_for_preboot_extended_timeout) {
+			timeout = pre_fw_load->wait_for_preboot_extended_timeout;
+			goto retry;
+		}
+	}
+
+	/* If we read all FF, then something is totally wrong, no point
+	 * of reading specific errors
+	 */
+	if (status != -1)
+		fw_err = fw_read_errors(hdev, pre_fw_load->boot_err0_reg,
+					pre_fw_load->boot_err1_reg,
+					pre_fw_load->sts_boot_dev_sts0_reg,
+					pre_fw_load->sts_boot_dev_sts1_reg);
+	if (rc || fw_err) {
+		detect_cpu_boot_status(hdev, status);
+		dev_err(hdev->dev, "CPU boot %s (status = %d)\n",
+				fw_err ? "failed due to an error" : "ready timeout", status);
+		return -EIO;
+	}
+
+	hdev->fw_loader.fw_comp_loaded |= FW_TYPE_PREBOOT_CPU;
+
+	return 0;
+}
+
+static int hl_fw_read_preboot_caps(struct hl_device *hdev)
+{
+	struct pre_fw_load_props *pre_fw_load;
+	struct asic_fixed_properties *prop;
+	u32 reg_val;
+	int rc;
+
+	prop = &hdev->asic_prop;
+	pre_fw_load = &hdev->fw_loader.pre_fw_load;
+
+	rc = hl_fw_wait_preboot_ready(hdev);
+	if (rc)
+		return rc;
+
+	/*
+	 * the registers DEV_STS* contain FW capabilities/features.
+	 * We can rely on this registers only if bit CPU_BOOT_DEV_STS*_ENABLED
+	 * is set.
+	 * In the first read of this register we store the value of this
+	 * register ONLY if the register is enabled (which will be propagated
+	 * to next stages) and also mark the register as valid.
+	 * In case it is not enabled the stored value will be left 0- all
+	 * caps/features are off
+	 */
+	reg_val = RREG32(pre_fw_load->sts_boot_dev_sts0_reg);
+	if (reg_val & CPU_BOOT_DEV_STS0_ENABLED) {
+		prop->fw_cpu_boot_dev_sts0_valid = true;
+		prop->fw_preboot_cpu_boot_dev_sts0 = reg_val;
+	}
+
+	reg_val = RREG32(pre_fw_load->sts_boot_dev_sts1_reg);
+	if (reg_val & CPU_BOOT_DEV_STS1_ENABLED) {
+		prop->fw_cpu_boot_dev_sts1_valid = true;
+		prop->fw_preboot_cpu_boot_dev_sts1 = reg_val;
+	}
+
+	prop->dynamic_fw_load = !!(prop->fw_preboot_cpu_boot_dev_sts0 &
+						CPU_BOOT_DEV_STS0_FW_LD_COM_EN);
+
+	/* initialize FW loader once we know what load protocol is used */
+	hdev->asic_funcs->init_firmware_loader(hdev);
+
+	dev_dbg(hdev->dev, "Attempting %s FW load\n",
+			prop->dynamic_fw_load ? "dynamic" : "legacy");
+	return 0;
+}
+
+static int hl_fw_static_read_device_fw_version(struct hl_device *hdev,
+					enum hl_fw_component fwc)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct fw_load_mgr *fw_loader = &hdev->fw_loader;
+	struct static_fw_load_mgr *static_loader;
+	char *dest, *boot_ver, *preboot_ver;
+	u32 ver_off, limit;
+	const char *name;
+	char btl_ver[32];
+
+	static_loader = &hdev->fw_loader.static_loader;
+
+	switch (fwc) {
+	case FW_COMP_BOOT_FIT:
+		ver_off = RREG32(static_loader->boot_fit_version_offset_reg);
+		dest = prop->uboot_ver;
+		name = "Boot-fit";
+		limit = static_loader->boot_fit_version_max_off;
+		break;
+	case FW_COMP_PREBOOT:
+		ver_off = RREG32(static_loader->preboot_version_offset_reg);
+		dest = prop->preboot_ver;
+		name = "Preboot";
+		limit = static_loader->preboot_version_max_off;
+		break;
+	default:
+		dev_warn(hdev->dev, "Undefined FW component: %d\n", fwc);
+		return -EIO;
+	}
+
+	ver_off &= static_loader->sram_offset_mask;
+
+	if (ver_off < limit) {
+		memcpy_fromio(dest,
+			hdev->pcie_bar[fw_loader->sram_bar_id] + ver_off,
+			VERSION_MAX_LEN);
+	} else {
+		dev_err(hdev->dev, "%s version offset (0x%x) is above SRAM\n",
+								name, ver_off);
+		strscpy(dest, "unavailable", VERSION_MAX_LEN);
+		return -EIO;
+	}
+
+	if (fwc == FW_COMP_BOOT_FIT) {
+		boot_ver = extract_fw_ver_from_str(prop->uboot_ver);
+		if (boot_ver) {
+			dev_info(hdev->dev, "boot-fit version %s\n", boot_ver);
+			kfree(boot_ver);
+		}
+	} else if (fwc == FW_COMP_PREBOOT) {
+		preboot_ver = strnstr(prop->preboot_ver, "Preboot",
+						VERSION_MAX_LEN);
+		if (preboot_ver && preboot_ver != prop->preboot_ver) {
+			strscpy(btl_ver, prop->preboot_ver,
+				min((int) (preboot_ver - prop->preboot_ver),
+									31));
+			dev_info(hdev->dev, "%s\n", btl_ver);
+		}
+
+		preboot_ver = extract_fw_ver_from_str(prop->preboot_ver);
+		if (preboot_ver) {
+			dev_info(hdev->dev, "preboot version %s\n",
+								preboot_ver);
+			kfree(preboot_ver);
+		}
+	}
+
+	return 0;
+}
+
+/**
+ * hl_fw_preboot_update_state - update internal data structures during
+ *                              handshake with preboot
+ *
+ *
+ * @hdev: pointer to the habanalabs device structure
+ *
+ * @return 0 on success, otherwise non-zero error code
+ */
+static void hl_fw_preboot_update_state(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	u32 cpu_boot_dev_sts0, cpu_boot_dev_sts1;
+
+	cpu_boot_dev_sts0 = prop->fw_preboot_cpu_boot_dev_sts0;
+	cpu_boot_dev_sts1 = prop->fw_preboot_cpu_boot_dev_sts1;
+
+	/* We read boot_dev_sts registers multiple times during boot:
+	 * 1. preboot - a. Check whether the security status bits are valid
+	 *              b. Check whether fw security is enabled
+	 *              c. Check whether hard reset is done by preboot
+	 * 2. boot cpu - a. Fetch boot cpu security status
+	 *               b. Check whether hard reset is done by boot cpu
+	 * 3. FW application - a. Fetch fw application security status
+	 *                     b. Check whether hard reset is done by fw app
+	 */
+	prop->hard_reset_done_by_fw = !!(cpu_boot_dev_sts0 & CPU_BOOT_DEV_STS0_FW_HARD_RST_EN);
+
+	prop->fw_security_enabled = !!(cpu_boot_dev_sts0 & CPU_BOOT_DEV_STS0_SECURITY_EN);
+
+	dev_dbg(hdev->dev, "Firmware preboot boot device status0 %#x\n",
+							cpu_boot_dev_sts0);
+
+	dev_dbg(hdev->dev, "Firmware preboot boot device status1 %#x\n",
+							cpu_boot_dev_sts1);
+
+	dev_dbg(hdev->dev, "Firmware preboot hard-reset is %s\n",
+			prop->hard_reset_done_by_fw ? "enabled" : "disabled");
+
+	dev_dbg(hdev->dev, "firmware-level security is %s\n",
+			prop->fw_security_enabled ? "enabled" : "disabled");
+
+	dev_dbg(hdev->dev, "GIC controller is %s\n",
+			prop->gic_interrupts_enable ? "enabled" : "disabled");
+}
+
+static int hl_fw_static_read_preboot_status(struct hl_device *hdev)
+{
+	int rc;
+
+	rc = hl_fw_static_read_device_fw_version(hdev, FW_COMP_PREBOOT);
+	if (rc)
+		return rc;
+
+	return 0;
+}
+
+int hl_fw_read_preboot_status(struct hl_device *hdev)
+{
+	int rc;
+
+	if (!(hdev->fw_components & FW_TYPE_PREBOOT_CPU))
+		return 0;
+
+	/* get FW pre-load parameters  */
+	hdev->asic_funcs->init_firmware_preload_params(hdev);
+
+	/*
+	 * In order to determine boot method (static VS dynamic) we need to
+	 * read the boot caps register
+	 */
+	rc = hl_fw_read_preboot_caps(hdev);
+	if (rc)
+		return rc;
+
+	hl_fw_preboot_update_state(hdev);
+
+	/* no need to read preboot status in dynamic load */
+	if (hdev->asic_prop.dynamic_fw_load)
+		return 0;
+
+	return hl_fw_static_read_preboot_status(hdev);
+}
+
+/* associate string with COMM status */
+static char *hl_dynamic_fw_status_str[COMMS_STS_INVLD_LAST] = {
+	[COMMS_STS_NOOP] = "NOOP",
+	[COMMS_STS_ACK] = "ACK",
+	[COMMS_STS_OK] = "OK",
+	[COMMS_STS_ERR] = "ERR",
+	[COMMS_STS_VALID_ERR] = "VALID_ERR",
+	[COMMS_STS_TIMEOUT_ERR] = "TIMEOUT_ERR",
+};
+
+/**
+ * hl_fw_dynamic_report_error_status - report error status
+ *
+ * @hdev: pointer to the habanalabs device structure
+ * @status: value of FW status register
+ * @expected_status: the expected status
+ */
+static void hl_fw_dynamic_report_error_status(struct hl_device *hdev,
+						u32 status,
+						enum comms_sts expected_status)
+{
+	enum comms_sts comm_status =
+				FIELD_GET(COMMS_STATUS_STATUS_MASK, status);
+
+	if (comm_status < COMMS_STS_INVLD_LAST)
+		dev_err(hdev->dev, "Device status %s, expected status: %s\n",
+				hl_dynamic_fw_status_str[comm_status],
+				hl_dynamic_fw_status_str[expected_status]);
+	else
+		dev_err(hdev->dev, "Device status unknown %d, expected status: %s\n",
+				comm_status,
+				hl_dynamic_fw_status_str[expected_status]);
+}
+
+/**
+ * hl_fw_dynamic_send_cmd - send LKD to FW cmd
+ *
+ * @hdev: pointer to the habanalabs device structure
+ * @fw_loader: managing structure for loading device's FW
+ * @cmd: LKD to FW cmd code
+ * @size: size of next FW component to be loaded (0 if not necessary)
+ *
+ * LDK to FW exact command layout is defined at struct comms_command.
+ * note: the size argument is used only when the next FW component should be
+ *       loaded, otherwise it shall be 0. the size is used by the FW in later
+ *       protocol stages and when sending only indicating the amount of memory
+ *       to be allocated by the FW to receive the next boot component.
+ */
+static void hl_fw_dynamic_send_cmd(struct hl_device *hdev,
+				struct fw_load_mgr *fw_loader,
+				enum comms_cmd cmd, unsigned int size)
+{
+	struct cpu_dyn_regs *dyn_regs;
+	u32 val;
+
+	dyn_regs = &fw_loader->dynamic_loader.comm_desc.cpu_dyn_regs;
+
+	val = FIELD_PREP(COMMS_COMMAND_CMD_MASK, cmd);
+	val |= FIELD_PREP(COMMS_COMMAND_SIZE_MASK, size);
+
+	trace_habanalabs_comms_send_cmd(&hdev->pdev->dev, comms_cmd_str_arr[cmd]);
+	WREG32(le32_to_cpu(dyn_regs->kmd_msg_to_cpu), val);
+}
+
+/**
+ * hl_fw_dynamic_extract_fw_response - update the FW response
+ *
+ * @hdev: pointer to the habanalabs device structure
+ * @fw_loader: managing structure for loading device's FW
+ * @response: FW response
+ * @status: the status read from CPU status register
+ *
+ * @return 0 on success, otherwise non-zero error code
+ */
+static int hl_fw_dynamic_extract_fw_response(struct hl_device *hdev,
+						struct fw_load_mgr *fw_loader,
+						struct fw_response *response,
+						u32 status)
+{
+	response->status = FIELD_GET(COMMS_STATUS_STATUS_MASK, status);
+	response->ram_offset = FIELD_GET(COMMS_STATUS_OFFSET_MASK, status) <<
+						COMMS_STATUS_OFFSET_ALIGN_SHIFT;
+	response->ram_type = FIELD_GET(COMMS_STATUS_RAM_TYPE_MASK, status);
+
+	if ((response->ram_type != COMMS_SRAM) &&
+					(response->ram_type != COMMS_DRAM)) {
+		dev_err(hdev->dev, "FW status: invalid RAM type %u\n",
+							response->ram_type);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+/**
+ * hl_fw_dynamic_wait_for_status - wait for status in dynamic FW load
+ *
+ * @hdev: pointer to the habanalabs device structure
+ * @fw_loader: managing structure for loading device's FW
+ * @expected_status: expected status to wait for
+ * @timeout: timeout for status wait
+ *
+ * @return 0 on success, otherwise non-zero error code
+ *
+ * waiting for status from FW include polling the FW status register until
+ * expected status is received or timeout occurs (whatever occurs first).
+ */
+static int hl_fw_dynamic_wait_for_status(struct hl_device *hdev,
+						struct fw_load_mgr *fw_loader,
+						enum comms_sts expected_status,
+						u32 timeout)
+{
+	struct cpu_dyn_regs *dyn_regs;
+	u32 status;
+	int rc;
+
+	dyn_regs = &fw_loader->dynamic_loader.comm_desc.cpu_dyn_regs;
+
+	trace_habanalabs_comms_wait_status(&hdev->pdev->dev, comms_sts_str_arr[expected_status]);
+
+	/* Wait for expected status */
+	rc = hl_poll_timeout(
+		hdev,
+		le32_to_cpu(dyn_regs->cpu_cmd_status_to_host),
+		status,
+		FIELD_GET(COMMS_STATUS_STATUS_MASK, status) == expected_status,
+		hdev->fw_comms_poll_interval_usec,
+		timeout);
+
+	if (rc) {
+		hl_fw_dynamic_report_error_status(hdev, status,
+							expected_status);
+		return -EIO;
+	}
+
+	trace_habanalabs_comms_wait_status_done(&hdev->pdev->dev,
+						comms_sts_str_arr[expected_status]);
+
+	/*
+	 * skip storing FW response for NOOP to preserve the actual desired
+	 * FW status
+	 */
+	if (expected_status == COMMS_STS_NOOP)
+		return 0;
+
+	rc = hl_fw_dynamic_extract_fw_response(hdev, fw_loader,
+					&fw_loader->dynamic_loader.response,
+					status);
+	return rc;
+}
+
+/**
+ * hl_fw_dynamic_send_clear_cmd - send clear command to FW
+ *
+ * @hdev: pointer to the habanalabs device structure
+ * @fw_loader: managing structure for loading device's FW
+ *
+ * @return 0 on success, otherwise non-zero error code
+ *
+ * after command cycle between LKD to FW CPU (i.e. LKD got an expected status
+ * from FW) we need to clear the CPU status register in order to avoid garbage
+ * between command cycles.
+ * This is done by sending clear command and polling the CPU to LKD status
+ * register to hold the status NOOP
+ */
+static int hl_fw_dynamic_send_clear_cmd(struct hl_device *hdev,
+						struct fw_load_mgr *fw_loader)
+{
+	hl_fw_dynamic_send_cmd(hdev, fw_loader, COMMS_CLR_STS, 0);
+
+	return hl_fw_dynamic_wait_for_status(hdev, fw_loader, COMMS_STS_NOOP,
+							fw_loader->cpu_timeout);
+}
+
+/**
+ * hl_fw_dynamic_send_protocol_cmd - send LKD to FW cmd and wait for ACK
+ *
+ * @hdev: pointer to the habanalabs device structure
+ * @fw_loader: managing structure for loading device's FW
+ * @cmd: LKD to FW cmd code
+ * @size: size of next FW component to be loaded (0 if not necessary)
+ * @wait_ok: if true also wait for OK response from FW
+ * @timeout: timeout for status wait
+ *
+ * @return 0 on success, otherwise non-zero error code
+ *
+ * brief:
+ * when sending protocol command we have the following steps:
+ * - send clear (clear command and verify clear status register)
+ * - send the actual protocol command
+ * - wait for ACK on the protocol command
+ * - send clear
+ * - send NOOP
+ * if, in addition, the specific protocol command should wait for OK then:
+ * - wait for OK
+ * - send clear
+ * - send NOOP
+ *
+ * NOTES:
+ * send clear: this is necessary in order to clear the status register to avoid
+ *             leftovers between command
+ * NOOP command: necessary to avoid loop on the clear command by the FW
+ */
+int hl_fw_dynamic_send_protocol_cmd(struct hl_device *hdev,
+				struct fw_load_mgr *fw_loader,
+				enum comms_cmd cmd, unsigned int size,
+				bool wait_ok, u32 timeout)
+{
+	int rc;
+
+	trace_habanalabs_comms_protocol_cmd(&hdev->pdev->dev, comms_cmd_str_arr[cmd]);
+
+	/* first send clear command to clean former commands */
+	rc = hl_fw_dynamic_send_clear_cmd(hdev, fw_loader);
+	if (rc)
+		return rc;
+
+	/* send the actual command */
+	hl_fw_dynamic_send_cmd(hdev, fw_loader, cmd, size);
+
+	/* wait for ACK for the command */
+	rc = hl_fw_dynamic_wait_for_status(hdev, fw_loader, COMMS_STS_ACK,
+								timeout);
+	if (rc)
+		return rc;
+
+	/* clear command to prepare for NOOP command */
+	rc = hl_fw_dynamic_send_clear_cmd(hdev, fw_loader);
+	if (rc)
+		return rc;
+
+	/* send the actual NOOP command */
+	hl_fw_dynamic_send_cmd(hdev, fw_loader, COMMS_NOOP, 0);
+
+	if (!wait_ok)
+		return 0;
+
+	rc = hl_fw_dynamic_wait_for_status(hdev, fw_loader, COMMS_STS_OK,
+								timeout);
+	if (rc)
+		return rc;
+
+	/* clear command to prepare for NOOP command */
+	rc = hl_fw_dynamic_send_clear_cmd(hdev, fw_loader);
+	if (rc)
+		return rc;
+
+	/* send the actual NOOP command */
+	hl_fw_dynamic_send_cmd(hdev, fw_loader, COMMS_NOOP, 0);
+
+	return 0;
+}
+
+/**
+ * hl_fw_compat_crc32 - CRC compatible with FW
+ *
+ * @data: pointer to the data
+ * @size: size of the data
+ *
+ * @return the CRC32 result
+ *
+ * NOTE: kernel's CRC32 differs from standard CRC32 calculation.
+ *       in order to be aligned we need to flip the bits of both the input
+ *       initial CRC and kernel's CRC32 result.
+ *       in addition both sides use initial CRC of 0,
+ */
+static u32 hl_fw_compat_crc32(u8 *data, size_t size)
+{
+	return ~crc32_le(~((u32)0), data, size);
+}
+
+/**
+ * hl_fw_dynamic_validate_memory_bound - validate memory bounds for memory
+ *                                        transfer (image or descriptor) between
+ *                                        host and FW
+ *
+ * @hdev: pointer to the habanalabs device structure
+ * @addr: device address of memory transfer
+ * @size: memory transfer size
+ * @region: PCI memory region
+ *
+ * @return 0 on success, otherwise non-zero error code
+ */
+static int hl_fw_dynamic_validate_memory_bound(struct hl_device *hdev,
+						u64 addr, size_t size,
+						struct pci_mem_region *region)
+{
+	u64 end_addr;
+
+	/* now make sure that the memory transfer is within region's bounds */
+	end_addr = addr + size;
+	if (end_addr >= region->region_base + region->region_size) {
+		dev_err(hdev->dev,
+			"dynamic FW load: memory transfer end address out of memory region bounds. addr: %llx\n",
+							end_addr);
+		return -EIO;
+	}
+
+	/*
+	 * now make sure memory transfer is within predefined BAR bounds.
+	 * this is to make sure we do not need to set the bar (e.g. for DRAM
+	 * memory transfers)
+	 */
+	if (end_addr >= region->region_base - region->offset_in_bar +
+							region->bar_size) {
+		dev_err(hdev->dev,
+			"FW image beyond PCI BAR bounds\n");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+/**
+ * hl_fw_dynamic_validate_descriptor - validate FW descriptor
+ *
+ * @hdev: pointer to the habanalabs device structure
+ * @fw_loader: managing structure for loading device's FW
+ * @fw_desc: the descriptor from FW
+ *
+ * @return 0 on success, otherwise non-zero error code
+ */
+static int hl_fw_dynamic_validate_descriptor(struct hl_device *hdev,
+					struct fw_load_mgr *fw_loader,
+					struct lkd_fw_comms_desc *fw_desc)
+{
+	struct pci_mem_region *region;
+	enum pci_region region_id;
+	size_t data_size;
+	u32 data_crc32;
+	u8 *data_ptr;
+	u64 addr;
+	int rc;
+
+	if (le32_to_cpu(fw_desc->header.magic) != HL_COMMS_DESC_MAGIC)
+		dev_dbg(hdev->dev, "Invalid magic for dynamic FW descriptor (%x)\n",
+				fw_desc->header.magic);
+
+	if (fw_desc->header.version != HL_COMMS_DESC_VER)
+		dev_dbg(hdev->dev, "Invalid version for dynamic FW descriptor (%x)\n",
+				fw_desc->header.version);
+
+	/*
+	 * Calc CRC32 of data without header. use the size of the descriptor
+	 * reported by firmware, without calculating it ourself, to allow adding
+	 * more fields to the lkd_fw_comms_desc structure.
+	 * note that no alignment/stride address issues here as all structures
+	 * are 64 bit padded.
+	 */
+	data_ptr = (u8 *)fw_desc + sizeof(struct comms_msg_header);
+	data_size = le16_to_cpu(fw_desc->header.size);
+
+	data_crc32 = hl_fw_compat_crc32(data_ptr, data_size);
+	if (data_crc32 != le32_to_cpu(fw_desc->header.crc32)) {
+		dev_err(hdev->dev, "CRC32 mismatch for dynamic FW descriptor (%x:%x)\n",
+			data_crc32, fw_desc->header.crc32);
+		return -EIO;
+	}
+
+	/* find memory region to which to copy the image */
+	addr = le64_to_cpu(fw_desc->img_addr);
+	region_id = hl_get_pci_memory_region(hdev, addr);
+	if ((region_id != PCI_REGION_SRAM) && ((region_id != PCI_REGION_DRAM))) {
+		dev_err(hdev->dev, "Invalid region to copy FW image address=%llx\n", addr);
+		return -EIO;
+	}
+
+	region = &hdev->pci_mem_region[region_id];
+
+	/* store the region for the copy stage */
+	fw_loader->dynamic_loader.image_region = region;
+
+	/*
+	 * here we know that the start address is valid, now make sure that the
+	 * image is within region's bounds
+	 */
+	rc = hl_fw_dynamic_validate_memory_bound(hdev, addr,
+					fw_loader->dynamic_loader.fw_image_size,
+					region);
+	if (rc) {
+		dev_err(hdev->dev, "invalid mem transfer request for FW image\n");
+		return rc;
+	}
+
+	/* here we can mark the descriptor as valid as the content has been validated */
+	fw_loader->dynamic_loader.fw_desc_valid = true;
+
+	return 0;
+}
+
+static int hl_fw_dynamic_validate_response(struct hl_device *hdev,
+						struct fw_response *response,
+						struct pci_mem_region *region)
+{
+	u64 device_addr;
+	int rc;
+
+	device_addr = region->region_base + response->ram_offset;
+
+	/*
+	 * validate that the descriptor is within region's bounds
+	 * Note that as the start address was supplied according to the RAM
+	 * type- testing only the end address is enough
+	 */
+	rc = hl_fw_dynamic_validate_memory_bound(hdev, device_addr,
+					sizeof(struct lkd_fw_comms_desc),
+					region);
+	return rc;
+}
+
+/*
+ * hl_fw_dynamic_read_descriptor_msg - read and show the ascii msg that sent by fw
+ *
+ * @hdev: pointer to the habanalabs device structure
+ * @fw_desc: the descriptor from FW
+ */
+static void hl_fw_dynamic_read_descriptor_msg(struct hl_device *hdev,
+					struct lkd_fw_comms_desc *fw_desc)
+{
+	int i;
+	char *msg;
+
+	for (i = 0 ; i < LKD_FW_ASCII_MSG_MAX ; i++) {
+		if (!fw_desc->ascii_msg[i].valid)
+			return;
+
+		/* force NULL termination */
+		msg = fw_desc->ascii_msg[i].msg;
+		msg[LKD_FW_ASCII_MSG_MAX_LEN - 1] = '\0';
+
+		switch (fw_desc->ascii_msg[i].msg_lvl) {
+		case LKD_FW_ASCII_MSG_ERR:
+			dev_err(hdev->dev, "fw: %s", fw_desc->ascii_msg[i].msg);
+			break;
+		case LKD_FW_ASCII_MSG_WRN:
+			dev_warn(hdev->dev, "fw: %s", fw_desc->ascii_msg[i].msg);
+			break;
+		case LKD_FW_ASCII_MSG_INF:
+			dev_info(hdev->dev, "fw: %s", fw_desc->ascii_msg[i].msg);
+			break;
+		default:
+			dev_dbg(hdev->dev, "fw: %s", fw_desc->ascii_msg[i].msg);
+			break;
+		}
+	}
+}
+
+/**
+ * hl_fw_dynamic_read_and_validate_descriptor - read and validate FW descriptor
+ *
+ * @hdev: pointer to the habanalabs device structure
+ * @fw_loader: managing structure for loading device's FW
+ *
+ * @return 0 on success, otherwise non-zero error code
+ */
+static int hl_fw_dynamic_read_and_validate_descriptor(struct hl_device *hdev,
+						struct fw_load_mgr *fw_loader)
+{
+	struct lkd_fw_comms_desc *fw_desc;
+	struct pci_mem_region *region;
+	struct fw_response *response;
+	void *temp_fw_desc;
+	void __iomem *src;
+	u16 fw_data_size;
+	enum pci_region region_id;
+	int rc;
+
+	fw_desc = &fw_loader->dynamic_loader.comm_desc;
+	response = &fw_loader->dynamic_loader.response;
+
+	region_id = (response->ram_type == COMMS_SRAM) ?
+					PCI_REGION_SRAM : PCI_REGION_DRAM;
+
+	region = &hdev->pci_mem_region[region_id];
+
+	rc = hl_fw_dynamic_validate_response(hdev, response, region);
+	if (rc) {
+		dev_err(hdev->dev,
+			"invalid mem transfer request for FW descriptor\n");
+		return rc;
+	}
+
+	/*
+	 * extract address to copy the descriptor from
+	 * in addition, as the descriptor value is going to be over-ridden by new data- we mark it
+	 * as invalid.
+	 * it will be marked again as valid once validated
+	 */
+	fw_loader->dynamic_loader.fw_desc_valid = false;
+	src = hdev->pcie_bar[region->bar_id] + region->offset_in_bar +
+							response->ram_offset;
+
+	/*
+	 * We do the copy of the fw descriptor in 2 phases:
+	 * 1. copy the header + data info according to our lkd_fw_comms_desc definition.
+	 *    then we're able to read the actual data size provided by fw.
+	 *    this is needed for cases where data in descriptor was changed(add/remove)
+	 *    in embedded specs header file before updating lkd copy of the header file
+	 * 2. copy descriptor to temporary buffer with aligned size and send it to validation
+	 */
+	memcpy_fromio(fw_desc, src, sizeof(struct lkd_fw_comms_desc));
+	fw_data_size = le16_to_cpu(fw_desc->header.size);
+
+	temp_fw_desc = vzalloc(sizeof(struct comms_msg_header) + fw_data_size);
+	if (!temp_fw_desc)
+		return -ENOMEM;
+
+	memcpy_fromio(temp_fw_desc, src, sizeof(struct comms_msg_header) + fw_data_size);
+
+	rc = hl_fw_dynamic_validate_descriptor(hdev, fw_loader,
+					(struct lkd_fw_comms_desc *) temp_fw_desc);
+
+	if (!rc)
+		hl_fw_dynamic_read_descriptor_msg(hdev, temp_fw_desc);
+
+	vfree(temp_fw_desc);
+
+	return rc;
+}
+
+/**
+ * hl_fw_dynamic_request_descriptor - handshake with CPU to get FW descriptor
+ *
+ * @hdev: pointer to the habanalabs device structure
+ * @fw_loader: managing structure for loading device's FW
+ * @next_image_size: size to allocate for next FW component
+ *
+ * @return 0 on success, otherwise non-zero error code
+ */
+static int hl_fw_dynamic_request_descriptor(struct hl_device *hdev,
+						struct fw_load_mgr *fw_loader,
+						size_t next_image_size)
+{
+	int rc;
+
+	rc = hl_fw_dynamic_send_protocol_cmd(hdev, fw_loader, COMMS_PREP_DESC,
+						next_image_size, true,
+						fw_loader->cpu_timeout);
+	if (rc)
+		return rc;
+
+	return hl_fw_dynamic_read_and_validate_descriptor(hdev, fw_loader);
+}
+
+/**
+ * hl_fw_dynamic_read_device_fw_version - read FW version to exposed properties
+ *
+ * @hdev: pointer to the habanalabs device structure
+ * @fwc: the firmware component
+ * @fw_version: fw component's version string
+ */
+static int hl_fw_dynamic_read_device_fw_version(struct hl_device *hdev,
+					enum hl_fw_component fwc,
+					const char *fw_version)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	char *preboot_ver, *boot_ver;
+	char btl_ver[32];
+	int rc;
+
+	switch (fwc) {
+	case FW_COMP_BOOT_FIT:
+		strscpy(prop->uboot_ver, fw_version, VERSION_MAX_LEN);
+		boot_ver = extract_fw_ver_from_str(prop->uboot_ver);
+		if (boot_ver) {
+			dev_info(hdev->dev, "boot-fit version %s\n", boot_ver);
+			kfree(boot_ver);
+		}
+
+		break;
+	case FW_COMP_PREBOOT:
+		strscpy(prop->preboot_ver, fw_version, VERSION_MAX_LEN);
+		preboot_ver = strnstr(prop->preboot_ver, "Preboot", VERSION_MAX_LEN);
+		dev_info(hdev->dev, "preboot full version: '%s'\n", preboot_ver);
+
+		if (preboot_ver && preboot_ver != prop->preboot_ver) {
+			strscpy(btl_ver, prop->preboot_ver,
+				min((int) (preboot_ver - prop->preboot_ver), 31));
+			dev_info(hdev->dev, "%s\n", btl_ver);
+		}
+
+		rc = hl_get_sw_major_minor_subminor(hdev, preboot_ver);
+		if (rc)
+			return rc;
+		preboot_ver = extract_fw_ver_from_str(prop->preboot_ver);
+		if (preboot_ver) {
+			rc = hl_get_preboot_major_minor(hdev, preboot_ver);
+			kfree(preboot_ver);
+			if (rc)
+				return rc;
+		}
+
+		break;
+	default:
+		dev_warn(hdev->dev, "Undefined FW component: %d\n", fwc);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/**
+ * hl_fw_dynamic_copy_image - copy image to memory allocated by the FW
+ *
+ * @hdev: pointer to the habanalabs device structure
+ * @fw: fw descriptor
+ * @fw_loader: managing structure for loading device's FW
+ */
+static int hl_fw_dynamic_copy_image(struct hl_device *hdev,
+						const struct firmware *fw,
+						struct fw_load_mgr *fw_loader)
+{
+	struct lkd_fw_comms_desc *fw_desc;
+	struct pci_mem_region *region;
+	void __iomem *dest;
+	u64 addr;
+	int rc;
+
+	fw_desc = &fw_loader->dynamic_loader.comm_desc;
+	addr = le64_to_cpu(fw_desc->img_addr);
+
+	/* find memory region to which to copy the image */
+	region = fw_loader->dynamic_loader.image_region;
+
+	dest = hdev->pcie_bar[region->bar_id] + region->offset_in_bar +
+					(addr - region->region_base);
+
+	rc = hl_fw_copy_fw_to_device(hdev, fw, dest,
+					fw_loader->boot_fit_img.src_off,
+					fw_loader->boot_fit_img.copy_size);
+
+	return rc;
+}
+
+/**
+ * hl_fw_dynamic_copy_msg - copy msg to memory allocated by the FW
+ *
+ * @hdev: pointer to the habanalabs device structure
+ * @msg: message
+ * @fw_loader: managing structure for loading device's FW
+ */
+static int hl_fw_dynamic_copy_msg(struct hl_device *hdev,
+		struct lkd_msg_comms *msg, struct fw_load_mgr *fw_loader)
+{
+	struct lkd_fw_comms_desc *fw_desc;
+	struct pci_mem_region *region;
+	void __iomem *dest;
+	u64 addr;
+	int rc;
+
+	fw_desc = &fw_loader->dynamic_loader.comm_desc;
+	addr = le64_to_cpu(fw_desc->img_addr);
+
+	/* find memory region to which to copy the image */
+	region = fw_loader->dynamic_loader.image_region;
+
+	dest = hdev->pcie_bar[region->bar_id] + region->offset_in_bar +
+					(addr - region->region_base);
+
+	rc = hl_fw_copy_msg_to_device(hdev, msg, dest, 0, 0);
+
+	return rc;
+}
+
+/**
+ * hl_fw_boot_fit_update_state - update internal data structures after boot-fit
+ *                               is loaded
+ *
+ * @hdev: pointer to the habanalabs device structure
+ * @cpu_boot_dev_sts0_reg: register holding CPU boot dev status 0
+ * @cpu_boot_dev_sts1_reg: register holding CPU boot dev status 1
+ *
+ * @return 0 on success, otherwise non-zero error code
+ */
+static void hl_fw_boot_fit_update_state(struct hl_device *hdev,
+						u32 cpu_boot_dev_sts0_reg,
+						u32 cpu_boot_dev_sts1_reg)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+
+	hdev->fw_loader.fw_comp_loaded |= FW_TYPE_BOOT_CPU;
+
+	/* Read boot_cpu status bits */
+	if (prop->fw_preboot_cpu_boot_dev_sts0 & CPU_BOOT_DEV_STS0_ENABLED) {
+		prop->fw_bootfit_cpu_boot_dev_sts0 =
+				RREG32(cpu_boot_dev_sts0_reg);
+
+		prop->hard_reset_done_by_fw = !!(prop->fw_bootfit_cpu_boot_dev_sts0 &
+							CPU_BOOT_DEV_STS0_FW_HARD_RST_EN);
+
+		dev_dbg(hdev->dev, "Firmware boot CPU status0 %#x\n",
+					prop->fw_bootfit_cpu_boot_dev_sts0);
+	}
+
+	if (prop->fw_cpu_boot_dev_sts1_valid) {
+		prop->fw_bootfit_cpu_boot_dev_sts1 =
+				RREG32(cpu_boot_dev_sts1_reg);
+
+		dev_dbg(hdev->dev, "Firmware boot CPU status1 %#x\n",
+					prop->fw_bootfit_cpu_boot_dev_sts1);
+	}
+
+	dev_dbg(hdev->dev, "Firmware boot CPU hard-reset is %s\n",
+			prop->hard_reset_done_by_fw ? "enabled" : "disabled");
+}
+
+static void hl_fw_dynamic_update_linux_interrupt_if(struct hl_device *hdev)
+{
+	struct cpu_dyn_regs *dyn_regs =
+			&hdev->fw_loader.dynamic_loader.comm_desc.cpu_dyn_regs;
+
+	/* Check whether all 3 interrupt interfaces are set, if not use a
+	 * single interface
+	 */
+	if (!hdev->asic_prop.gic_interrupts_enable &&
+			!(hdev->asic_prop.fw_app_cpu_boot_dev_sts0 &
+				CPU_BOOT_DEV_STS0_MULTI_IRQ_POLL_EN)) {
+		dyn_regs->gic_host_halt_irq = dyn_regs->gic_host_pi_upd_irq;
+		dyn_regs->gic_host_ints_irq = dyn_regs->gic_host_pi_upd_irq;
+
+		dev_warn(hdev->dev,
+			"Using a single interrupt interface towards cpucp");
+	}
+}
+/**
+ * hl_fw_dynamic_load_image - load FW image using dynamic protocol
+ *
+ * @hdev: pointer to the habanalabs device structure
+ * @fw_loader: managing structure for loading device's FW
+ * @load_fwc: the FW component to be loaded
+ * @img_ld_timeout: image load timeout
+ *
+ * @return 0 on success, otherwise non-zero error code
+ */
+static int hl_fw_dynamic_load_image(struct hl_device *hdev,
+						struct fw_load_mgr *fw_loader,
+						enum hl_fw_component load_fwc,
+						u32 img_ld_timeout)
+{
+	enum hl_fw_component cur_fwc;
+	const struct firmware *fw;
+	char *fw_name;
+	int rc = 0;
+
+	/*
+	 * when loading image we have one of 2 scenarios:
+	 * 1. current FW component is preboot and we want to load boot-fit
+	 * 2. current FW component is boot-fit and we want to load linux
+	 */
+	if (load_fwc == FW_COMP_BOOT_FIT) {
+		cur_fwc = FW_COMP_PREBOOT;
+		fw_name = fw_loader->boot_fit_img.image_name;
+	} else {
+		cur_fwc = FW_COMP_BOOT_FIT;
+		fw_name = fw_loader->linux_img.image_name;
+	}
+
+	/* request FW in order to communicate to FW the size to be allocated */
+	rc = hl_request_fw(hdev, &fw, fw_name);
+	if (rc)
+		return rc;
+
+	/* store the image size for future validation */
+	fw_loader->dynamic_loader.fw_image_size = fw->size;
+
+	rc = hl_fw_dynamic_request_descriptor(hdev, fw_loader, fw->size);
+	if (rc)
+		goto release_fw;
+
+	/* read preboot version */
+	rc = hl_fw_dynamic_read_device_fw_version(hdev, cur_fwc,
+				fw_loader->dynamic_loader.comm_desc.cur_fw_ver);
+	if (rc)
+		goto release_fw;
+
+	/* copy boot fit to space allocated by FW */
+	rc = hl_fw_dynamic_copy_image(hdev, fw, fw_loader);
+	if (rc)
+		goto release_fw;
+
+	rc = hl_fw_dynamic_send_protocol_cmd(hdev, fw_loader, COMMS_DATA_RDY,
+						0, true,
+						fw_loader->cpu_timeout);
+	if (rc)
+		goto release_fw;
+
+	rc = hl_fw_dynamic_send_protocol_cmd(hdev, fw_loader, COMMS_EXEC,
+						0, false,
+						img_ld_timeout);
+
+release_fw:
+	hl_release_firmware(fw);
+	return rc;
+}
+
+static int hl_fw_dynamic_wait_for_boot_fit_active(struct hl_device *hdev,
+					struct fw_load_mgr *fw_loader)
+{
+	struct dynamic_fw_load_mgr *dyn_loader;
+	u32 status;
+	int rc;
+
+	dyn_loader = &fw_loader->dynamic_loader;
+
+	/*
+	 * Make sure CPU boot-loader is running
+	 * Note that the CPU_BOOT_STATUS_SRAM_AVAIL is generally set by Linux
+	 * yet there is a debug scenario in which we loading uboot (without Linux)
+	 * which at later stage is relocated to DRAM. In this case we expect
+	 * uboot to set the CPU_BOOT_STATUS_SRAM_AVAIL and so we add it to the
+	 * poll flags
+	 */
+	rc = hl_poll_timeout(
+		hdev,
+		le32_to_cpu(dyn_loader->comm_desc.cpu_dyn_regs.cpu_boot_status),
+		status,
+		(status == CPU_BOOT_STATUS_READY_TO_BOOT) ||
+		(status == CPU_BOOT_STATUS_SRAM_AVAIL),
+		hdev->fw_poll_interval_usec,
+		dyn_loader->wait_for_bl_timeout);
+	if (rc) {
+		dev_err(hdev->dev, "failed to wait for boot (status = %d)\n", status);
+		return rc;
+	}
+
+	dev_dbg(hdev->dev, "uboot status = %d\n", status);
+	return 0;
+}
+
+static int hl_fw_dynamic_wait_for_linux_active(struct hl_device *hdev,
+						struct fw_load_mgr *fw_loader)
+{
+	struct dynamic_fw_load_mgr *dyn_loader;
+	u32 status;
+	int rc;
+
+	dyn_loader = &fw_loader->dynamic_loader;
+
+	/* Make sure CPU linux is running */
+
+	rc = hl_poll_timeout(
+		hdev,
+		le32_to_cpu(dyn_loader->comm_desc.cpu_dyn_regs.cpu_boot_status),
+		status,
+		(status == CPU_BOOT_STATUS_SRAM_AVAIL),
+		hdev->fw_poll_interval_usec,
+		fw_loader->cpu_timeout);
+	if (rc) {
+		dev_err(hdev->dev, "failed to wait for Linux (status = %d)\n", status);
+		return rc;
+	}
+
+	dev_dbg(hdev->dev, "Boot status = %d\n", status);
+	return 0;
+}
+
+/**
+ * hl_fw_linux_update_state -	update internal data structures after Linux
+ *				is loaded.
+ *				Note: Linux initialization is comprised mainly
+ *				of two stages - loading kernel (SRAM_AVAIL)
+ *				& loading ARMCP.
+ *				Therefore reading boot device status in any of
+ *				these stages might result in different values.
+ *
+ * @hdev: pointer to the habanalabs device structure
+ * @cpu_boot_dev_sts0_reg: register holding CPU boot dev status 0
+ * @cpu_boot_dev_sts1_reg: register holding CPU boot dev status 1
+ *
+ * @return 0 on success, otherwise non-zero error code
+ */
+static void hl_fw_linux_update_state(struct hl_device *hdev,
+						u32 cpu_boot_dev_sts0_reg,
+						u32 cpu_boot_dev_sts1_reg)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+
+	hdev->fw_loader.fw_comp_loaded |= FW_TYPE_LINUX;
+
+	/* Read FW application security bits */
+	if (prop->fw_cpu_boot_dev_sts0_valid) {
+		prop->fw_app_cpu_boot_dev_sts0 = RREG32(cpu_boot_dev_sts0_reg);
+
+		prop->hard_reset_done_by_fw = !!(prop->fw_app_cpu_boot_dev_sts0 &
+							CPU_BOOT_DEV_STS0_FW_HARD_RST_EN);
+
+		if (prop->fw_app_cpu_boot_dev_sts0 &
+				CPU_BOOT_DEV_STS0_GIC_PRIVILEGED_EN)
+			prop->gic_interrupts_enable = false;
+
+		dev_dbg(hdev->dev,
+			"Firmware application CPU status0 %#x\n",
+			prop->fw_app_cpu_boot_dev_sts0);
+
+		dev_dbg(hdev->dev, "GIC controller is %s\n",
+				prop->gic_interrupts_enable ?
+						"enabled" : "disabled");
+	}
+
+	if (prop->fw_cpu_boot_dev_sts1_valid) {
+		prop->fw_app_cpu_boot_dev_sts1 = RREG32(cpu_boot_dev_sts1_reg);
+
+		dev_dbg(hdev->dev,
+			"Firmware application CPU status1 %#x\n",
+			prop->fw_app_cpu_boot_dev_sts1);
+	}
+
+	dev_dbg(hdev->dev, "Firmware application CPU hard-reset is %s\n",
+			prop->hard_reset_done_by_fw ? "enabled" : "disabled");
+
+	dev_info(hdev->dev, "Successfully loaded firmware to device\n");
+}
+
+/**
+ * hl_fw_dynamic_send_msg - send a COMMS message with attached data
+ *
+ * @hdev: pointer to the habanalabs device structure
+ * @fw_loader: managing structure for loading device's FW
+ * @msg_type: message type
+ * @data: data to be sent
+ *
+ * @return 0 on success, otherwise non-zero error code
+ */
+static int hl_fw_dynamic_send_msg(struct hl_device *hdev,
+		struct fw_load_mgr *fw_loader, u8 msg_type, void *data)
+{
+	struct lkd_msg_comms *msg;
+	int rc;
+
+	msg = kzalloc(sizeof(*msg), GFP_KERNEL);
+	if (!msg)
+		return -ENOMEM;
+
+	/* create message to be sent */
+	msg->header.type = msg_type;
+	msg->header.size = cpu_to_le16(sizeof(struct comms_msg_header));
+	msg->header.magic = cpu_to_le32(HL_COMMS_MSG_MAGIC);
+
+	switch (msg_type) {
+	case HL_COMMS_RESET_CAUSE_TYPE:
+		msg->reset_cause = *(__u8 *) data;
+		break;
+
+	default:
+		dev_err(hdev->dev,
+			"Send COMMS message - invalid message type %u\n",
+			msg_type);
+		rc = -EINVAL;
+		goto out;
+	}
+
+	rc = hl_fw_dynamic_request_descriptor(hdev, fw_loader,
+			sizeof(struct lkd_msg_comms));
+	if (rc)
+		goto out;
+
+	/* copy message to space allocated by FW */
+	rc = hl_fw_dynamic_copy_msg(hdev, msg, fw_loader);
+	if (rc)
+		goto out;
+
+	rc = hl_fw_dynamic_send_protocol_cmd(hdev, fw_loader, COMMS_DATA_RDY,
+						0, true,
+						fw_loader->cpu_timeout);
+	if (rc)
+		goto out;
+
+	rc = hl_fw_dynamic_send_protocol_cmd(hdev, fw_loader, COMMS_EXEC,
+						0, true,
+						fw_loader->cpu_timeout);
+
+out:
+	kfree(msg);
+	return rc;
+}
+
+/**
+ * hl_fw_dynamic_init_cpu - initialize the device CPU using dynamic protocol
+ *
+ * @hdev: pointer to the habanalabs device structure
+ * @fw_loader: managing structure for loading device's FW
+ *
+ * @return 0 on success, otherwise non-zero error code
+ *
+ * brief: the dynamic protocol is master (LKD) slave (FW CPU) protocol.
+ * the communication is done using registers:
+ * - LKD command register
+ * - FW status register
+ * the protocol is race free. this goal is achieved by splitting the requests
+ * and response to known synchronization points between the LKD and the FW.
+ * each response to LKD request is known and bound to a predefined timeout.
+ * in case of timeout expiration without the desired status from FW- the
+ * protocol (and hence the boot) will fail.
+ */
+static int hl_fw_dynamic_init_cpu(struct hl_device *hdev,
+					struct fw_load_mgr *fw_loader)
+{
+	struct cpu_dyn_regs *dyn_regs;
+	int rc, fw_error_rc;
+
+	dev_info(hdev->dev,
+		"Loading %sfirmware to device, may take some time...\n",
+		hdev->asic_prop.fw_security_enabled ? "secured " : "");
+
+	/* initialize FW descriptor as invalid */
+	fw_loader->dynamic_loader.fw_desc_valid = false;
+
+	/*
+	 * In this stage, "cpu_dyn_regs" contains only LKD's hard coded values!
+	 * It will be updated from FW after hl_fw_dynamic_request_descriptor().
+	 */
+	dyn_regs = &fw_loader->dynamic_loader.comm_desc.cpu_dyn_regs;
+
+	rc = hl_fw_dynamic_send_protocol_cmd(hdev, fw_loader, COMMS_RST_STATE,
+						0, true,
+						fw_loader->cpu_timeout);
+	if (rc)
+		goto protocol_err;
+
+	if (hdev->reset_info.curr_reset_cause) {
+		rc = hl_fw_dynamic_send_msg(hdev, fw_loader,
+				HL_COMMS_RESET_CAUSE_TYPE, &hdev->reset_info.curr_reset_cause);
+		if (rc)
+			goto protocol_err;
+
+		/* Clear current reset cause */
+		hdev->reset_info.curr_reset_cause = HL_RESET_CAUSE_UNKNOWN;
+	}
+
+	rc = hl_fw_dynamic_request_descriptor(hdev, fw_loader, sizeof(struct lkd_msg_comms));
+	if (rc)
+		goto protocol_err;
+
+	if (hdev->asic_prop.support_dynamic_resereved_fw_size)
+		hdev->asic_prop.reserved_fw_mem_size =
+			le32_to_cpu(fw_loader->dynamic_loader.comm_desc.rsvd_mem_size_mb) * SZ_1M;
+
+	if (!(hdev->fw_components & FW_TYPE_BOOT_CPU)) {
+		struct lkd_fw_binning_info *binning_info;
+
+		/* read preboot version */
+		rc = hl_fw_dynamic_read_device_fw_version(hdev, FW_COMP_PREBOOT,
+				fw_loader->dynamic_loader.comm_desc.cur_fw_ver);
+		if (rc)
+			return rc;
+
+		/* read binning info from preboot */
+		if (hdev->support_preboot_binning) {
+			binning_info = &fw_loader->dynamic_loader.comm_desc.binning_info;
+			hdev->tpc_binning = le64_to_cpu(binning_info->tpc_mask_l);
+			hdev->dram_binning = le32_to_cpu(binning_info->dram_mask);
+			hdev->edma_binning = le32_to_cpu(binning_info->edma_mask);
+			hdev->decoder_binning = le32_to_cpu(binning_info->dec_mask);
+			hdev->rotator_binning = le32_to_cpu(binning_info->rot_mask);
+
+			rc = hdev->asic_funcs->set_dram_properties(hdev);
+			if (rc)
+				return rc;
+
+			rc = hdev->asic_funcs->set_binning_masks(hdev);
+			if (rc)
+				return rc;
+
+			dev_dbg(hdev->dev,
+				"Read binning masks: tpc: 0x%llx, dram: 0x%llx, edma: 0x%x, dec: 0x%x, rot:0x%x\n",
+				hdev->tpc_binning, hdev->dram_binning, hdev->edma_binning,
+				hdev->decoder_binning, hdev->rotator_binning);
+		}
+
+		return 0;
+	}
+
+	/* load boot fit to FW */
+	rc = hl_fw_dynamic_load_image(hdev, fw_loader, FW_COMP_BOOT_FIT,
+						fw_loader->boot_fit_timeout);
+	if (rc) {
+		dev_err(hdev->dev, "failed to load boot fit\n");
+		goto protocol_err;
+	}
+
+	rc = hl_fw_dynamic_wait_for_boot_fit_active(hdev, fw_loader);
+	if (rc)
+		goto protocol_err;
+
+	hl_fw_boot_fit_update_state(hdev,
+			le32_to_cpu(dyn_regs->cpu_boot_dev_sts0),
+			le32_to_cpu(dyn_regs->cpu_boot_dev_sts1));
+
+	/*
+	 * when testing FW load (without Linux) on PLDM we don't want to
+	 * wait until boot fit is active as it may take several hours.
+	 * instead, we load the bootfit and let it do all initialization in
+	 * the background.
+	 */
+	if (hdev->pldm && !(hdev->fw_components & FW_TYPE_LINUX))
+		return 0;
+
+	/* Enable DRAM scrambling before Linux boot and after successful
+	 *  UBoot
+	 */
+	hdev->asic_funcs->init_cpu_scrambler_dram(hdev);
+
+	if (!(hdev->fw_components & FW_TYPE_LINUX)) {
+		dev_dbg(hdev->dev, "Skip loading Linux F/W\n");
+		return 0;
+	}
+
+	if (fw_loader->skip_bmc) {
+		rc = hl_fw_dynamic_send_protocol_cmd(hdev, fw_loader,
+							COMMS_SKIP_BMC, 0,
+							true,
+							fw_loader->cpu_timeout);
+		if (rc) {
+			dev_err(hdev->dev, "failed to load boot fit\n");
+			goto protocol_err;
+		}
+	}
+
+	/* load Linux image to FW */
+	rc = hl_fw_dynamic_load_image(hdev, fw_loader, FW_COMP_LINUX,
+							fw_loader->cpu_timeout);
+	if (rc) {
+		dev_err(hdev->dev, "failed to load Linux\n");
+		goto protocol_err;
+	}
+
+	rc = hl_fw_dynamic_wait_for_linux_active(hdev, fw_loader);
+	if (rc)
+		goto protocol_err;
+
+	hl_fw_linux_update_state(hdev,
+				le32_to_cpu(dyn_regs->cpu_boot_dev_sts0),
+				le32_to_cpu(dyn_regs->cpu_boot_dev_sts1));
+
+	hl_fw_dynamic_update_linux_interrupt_if(hdev);
+
+protocol_err:
+	if (fw_loader->dynamic_loader.fw_desc_valid) {
+		fw_error_rc = fw_read_errors(hdev, le32_to_cpu(dyn_regs->cpu_boot_err0),
+				le32_to_cpu(dyn_regs->cpu_boot_err1),
+				le32_to_cpu(dyn_regs->cpu_boot_dev_sts0),
+				le32_to_cpu(dyn_regs->cpu_boot_dev_sts1));
+
+		if (fw_error_rc)
+			return fw_error_rc;
+	}
+
+	return rc;
+}
+
+/**
+ * hl_fw_static_init_cpu - initialize the device CPU using static protocol
+ *
+ * @hdev: pointer to the habanalabs device structure
+ * @fw_loader: managing structure for loading device's FW
+ *
+ * @return 0 on success, otherwise non-zero error code
+ */
+static int hl_fw_static_init_cpu(struct hl_device *hdev,
+					struct fw_load_mgr *fw_loader)
+{
+	u32 cpu_msg_status_reg, cpu_timeout, msg_to_cpu_reg, status;
+	u32 cpu_boot_dev_status0_reg, cpu_boot_dev_status1_reg;
+	struct static_fw_load_mgr *static_loader;
+	u32 cpu_boot_status_reg;
+	int rc;
+
+	if (!(hdev->fw_components & FW_TYPE_BOOT_CPU))
+		return 0;
+
+	/* init common loader parameters */
+	cpu_timeout = fw_loader->cpu_timeout;
+
+	/* init static loader parameters */
+	static_loader = &fw_loader->static_loader;
+	cpu_msg_status_reg = static_loader->cpu_cmd_status_to_host_reg;
+	msg_to_cpu_reg = static_loader->kmd_msg_to_cpu_reg;
+	cpu_boot_dev_status0_reg = static_loader->cpu_boot_dev_status0_reg;
+	cpu_boot_dev_status1_reg = static_loader->cpu_boot_dev_status1_reg;
+	cpu_boot_status_reg = static_loader->cpu_boot_status_reg;
+
+	dev_info(hdev->dev, "Going to wait for device boot (up to %lds)\n",
+		cpu_timeout / USEC_PER_SEC);
+
+	/* Wait for boot FIT request */
+	rc = hl_poll_timeout(
+		hdev,
+		cpu_boot_status_reg,
+		status,
+		status == CPU_BOOT_STATUS_WAITING_FOR_BOOT_FIT,
+		hdev->fw_poll_interval_usec,
+		fw_loader->boot_fit_timeout);
+
+	if (rc) {
+		dev_dbg(hdev->dev,
+			"No boot fit request received (status = %d), resuming boot\n", status);
+	} else {
+		rc = hdev->asic_funcs->load_boot_fit_to_device(hdev);
+		if (rc)
+			goto out;
+
+		/* Clear device CPU message status */
+		WREG32(cpu_msg_status_reg, CPU_MSG_CLR);
+
+		/* Signal device CPU that boot loader is ready */
+		WREG32(msg_to_cpu_reg, KMD_MSG_FIT_RDY);
+
+		/* Poll for CPU device ack */
+		rc = hl_poll_timeout(
+			hdev,
+			cpu_msg_status_reg,
+			status,
+			status == CPU_MSG_OK,
+			hdev->fw_poll_interval_usec,
+			fw_loader->boot_fit_timeout);
+
+		if (rc) {
+			dev_err(hdev->dev,
+				"Timeout waiting for boot fit load ack (status = %d)\n", status);
+			goto out;
+		}
+
+		/* Clear message */
+		WREG32(msg_to_cpu_reg, KMD_MSG_NA);
+	}
+
+	/*
+	 * Make sure CPU boot-loader is running
+	 * Note that the CPU_BOOT_STATUS_SRAM_AVAIL is generally set by Linux
+	 * yet there is a debug scenario in which we loading uboot (without Linux)
+	 * which at later stage is relocated to DRAM. In this case we expect
+	 * uboot to set the CPU_BOOT_STATUS_SRAM_AVAIL and so we add it to the
+	 * poll flags
+	 */
+	rc = hl_poll_timeout(
+		hdev,
+		cpu_boot_status_reg,
+		status,
+		(status == CPU_BOOT_STATUS_DRAM_RDY) ||
+		(status == CPU_BOOT_STATUS_NIC_FW_RDY) ||
+		(status == CPU_BOOT_STATUS_READY_TO_BOOT) ||
+		(status == CPU_BOOT_STATUS_SRAM_AVAIL),
+		hdev->fw_poll_interval_usec,
+		cpu_timeout);
+
+	dev_dbg(hdev->dev, "uboot status = %d\n", status);
+
+	/* Read U-Boot version now in case we will later fail */
+	hl_fw_static_read_device_fw_version(hdev, FW_COMP_BOOT_FIT);
+
+	/* update state according to boot stage */
+	hl_fw_boot_fit_update_state(hdev, cpu_boot_dev_status0_reg,
+						cpu_boot_dev_status1_reg);
+
+	if (rc) {
+		detect_cpu_boot_status(hdev, status);
+		rc = -EIO;
+		goto out;
+	}
+
+	/* Enable DRAM scrambling before Linux boot and after successful
+	 *  UBoot
+	 */
+	hdev->asic_funcs->init_cpu_scrambler_dram(hdev);
+
+	if (!(hdev->fw_components & FW_TYPE_LINUX)) {
+		dev_info(hdev->dev, "Skip loading Linux F/W\n");
+		rc = 0;
+		goto out;
+	}
+
+	if (status == CPU_BOOT_STATUS_SRAM_AVAIL) {
+		rc = 0;
+		goto out;
+	}
+
+	dev_info(hdev->dev,
+		"Loading firmware to device, may take some time...\n");
+
+	rc = hdev->asic_funcs->load_firmware_to_device(hdev);
+	if (rc)
+		goto out;
+
+	if (fw_loader->skip_bmc) {
+		WREG32(msg_to_cpu_reg, KMD_MSG_SKIP_BMC);
+
+		rc = hl_poll_timeout(
+			hdev,
+			cpu_boot_status_reg,
+			status,
+			(status == CPU_BOOT_STATUS_BMC_WAITING_SKIPPED),
+			hdev->fw_poll_interval_usec,
+			cpu_timeout);
+
+		if (rc) {
+			dev_err(hdev->dev,
+				"Failed to get ACK on skipping BMC (status = %d)\n",
+				status);
+			WREG32(msg_to_cpu_reg, KMD_MSG_NA);
+			rc = -EIO;
+			goto out;
+		}
+	}
+
+	WREG32(msg_to_cpu_reg, KMD_MSG_FIT_RDY);
+
+	rc = hl_poll_timeout(
+		hdev,
+		cpu_boot_status_reg,
+		status,
+		(status == CPU_BOOT_STATUS_SRAM_AVAIL),
+		hdev->fw_poll_interval_usec,
+		cpu_timeout);
+
+	/* Clear message */
+	WREG32(msg_to_cpu_reg, KMD_MSG_NA);
+
+	if (rc) {
+		if (status == CPU_BOOT_STATUS_FIT_CORRUPTED)
+			dev_err(hdev->dev,
+				"Device reports FIT image is corrupted\n");
+		else
+			dev_err(hdev->dev,
+				"Failed to load firmware to device (status = %d)\n",
+				status);
+
+		rc = -EIO;
+		goto out;
+	}
+
+	rc = fw_read_errors(hdev, fw_loader->static_loader.boot_err0_reg,
+					fw_loader->static_loader.boot_err1_reg,
+					cpu_boot_dev_status0_reg,
+					cpu_boot_dev_status1_reg);
+	if (rc)
+		return rc;
+
+	hl_fw_linux_update_state(hdev, cpu_boot_dev_status0_reg,
+						cpu_boot_dev_status1_reg);
+
+	return 0;
+
+out:
+	fw_read_errors(hdev, fw_loader->static_loader.boot_err0_reg,
+					fw_loader->static_loader.boot_err1_reg,
+					cpu_boot_dev_status0_reg,
+					cpu_boot_dev_status1_reg);
+
+	return rc;
+}
+
+/**
+ * hl_fw_init_cpu - initialize the device CPU
+ *
+ * @hdev: pointer to the habanalabs device structure
+ *
+ * @return 0 on success, otherwise non-zero error code
+ *
+ * perform necessary initializations for device's CPU. takes into account if
+ * init protocol is static or dynamic.
+ */
+int hl_fw_init_cpu(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct fw_load_mgr *fw_loader = &hdev->fw_loader;
+
+	return  prop->dynamic_fw_load ?
+			hl_fw_dynamic_init_cpu(hdev, fw_loader) :
+			hl_fw_static_init_cpu(hdev, fw_loader);
+}
+
+void hl_fw_set_pll_profile(struct hl_device *hdev)
+{
+	hl_fw_set_frequency(hdev, hdev->asic_prop.clk_pll_index,
+				hdev->asic_prop.max_freq_value);
+}
+
+int hl_fw_get_clk_rate(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk)
+{
+	long value;
+
+	if (!hl_device_operational(hdev, NULL))
+		return -ENODEV;
+
+	if (!hdev->pdev) {
+		*cur_clk = 0;
+		*max_clk = 0;
+		return 0;
+	}
+
+	value = hl_fw_get_frequency(hdev, hdev->asic_prop.clk_pll_index, false);
+
+	if (value < 0) {
+		dev_err(hdev->dev, "Failed to retrieve device max clock %ld\n", value);
+		return value;
+	}
+
+	*max_clk = (value / 1000 / 1000);
+
+	value = hl_fw_get_frequency(hdev, hdev->asic_prop.clk_pll_index, true);
+
+	if (value < 0) {
+		dev_err(hdev->dev, "Failed to retrieve device current clock %ld\n", value);
+		return value;
+	}
+
+	*cur_clk = (value / 1000 / 1000);
+
+	return 0;
+}
+
+long hl_fw_get_frequency(struct hl_device *hdev, u32 pll_index, bool curr)
+{
+	struct cpucp_packet pkt;
+	u32 used_pll_idx;
+	u64 result;
+	int rc;
+
+	rc = get_used_pll_index(hdev, pll_index, &used_pll_idx);
+	if (rc)
+		return rc;
+
+	memset(&pkt, 0, sizeof(pkt));
+
+	if (curr)
+		pkt.ctl = cpu_to_le32(CPUCP_PACKET_FREQUENCY_CURR_GET <<
+						CPUCP_PKT_CTL_OPCODE_SHIFT);
+	else
+		pkt.ctl = cpu_to_le32(CPUCP_PACKET_FREQUENCY_GET << CPUCP_PKT_CTL_OPCODE_SHIFT);
+
+	pkt.pll_index = cpu_to_le32((u32)used_pll_idx);
+
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), 0, &result);
+	if (rc) {
+		if (rc != -EAGAIN)
+			dev_err(hdev->dev, "Failed to get frequency of PLL %d, error %d\n",
+				used_pll_idx, rc);
+		return rc;
+	}
+
+	return (long) result;
+}
+
+void hl_fw_set_frequency(struct hl_device *hdev, u32 pll_index, u64 freq)
+{
+	struct cpucp_packet pkt;
+	u32 used_pll_idx;
+	int rc;
+
+	rc = get_used_pll_index(hdev, pll_index, &used_pll_idx);
+	if (rc)
+		return;
+
+	memset(&pkt, 0, sizeof(pkt));
+
+	pkt.ctl = cpu_to_le32(CPUCP_PACKET_FREQUENCY_SET << CPUCP_PKT_CTL_OPCODE_SHIFT);
+	pkt.pll_index = cpu_to_le32((u32)used_pll_idx);
+	pkt.value = cpu_to_le64(freq);
+
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), 0, NULL);
+	if (rc && rc != -EAGAIN)
+		dev_err(hdev->dev, "Failed to set frequency to PLL %d, error %d\n",
+			used_pll_idx, rc);
+}
+
+long hl_fw_get_max_power(struct hl_device *hdev)
+{
+	struct cpucp_packet pkt;
+	u64 result;
+	int rc;
+
+	memset(&pkt, 0, sizeof(pkt));
+
+	pkt.ctl = cpu_to_le32(CPUCP_PACKET_MAX_POWER_GET << CPUCP_PKT_CTL_OPCODE_SHIFT);
+
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), 0, &result);
+	if (rc) {
+		if (rc != -EAGAIN)
+			dev_err(hdev->dev, "Failed to get max power, error %d\n", rc);
+		return rc;
+	}
+
+	return result;
+}
+
+void hl_fw_set_max_power(struct hl_device *hdev)
+{
+	struct cpucp_packet pkt;
+	int rc;
+
+	/* TODO: remove this after simulator supports this packet */
+	if (!hdev->pdev)
+		return;
+
+	memset(&pkt, 0, sizeof(pkt));
+
+	pkt.ctl = cpu_to_le32(CPUCP_PACKET_MAX_POWER_SET << CPUCP_PKT_CTL_OPCODE_SHIFT);
+	pkt.value = cpu_to_le64(hdev->max_power);
+
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), 0, NULL);
+	if (rc && rc != -EAGAIN)
+		dev_err(hdev->dev, "Failed to set max power, error %d\n", rc);
+}
+
+static int hl_fw_get_sec_attest_data(struct hl_device *hdev, u32 packet_id, void *data, u32 size,
+					u32 nonce, u32 timeout)
+{
+	struct cpucp_packet pkt = {};
+	dma_addr_t req_dma_addr;
+	void *req_cpu_addr;
+	int rc;
+
+	req_cpu_addr = hl_cpu_accessible_dma_pool_alloc(hdev, size, &req_dma_addr);
+	if (!req_cpu_addr) {
+		dev_err(hdev->dev,
+			"Failed to allocate DMA memory for CPU-CP packet %u\n", packet_id);
+		return -ENOMEM;
+	}
+
+	memset(data, 0, size);
+
+	pkt.ctl = cpu_to_le32(packet_id << CPUCP_PKT_CTL_OPCODE_SHIFT);
+	pkt.addr = cpu_to_le64(req_dma_addr);
+	pkt.data_max_size = cpu_to_le32(size);
+	pkt.nonce = cpu_to_le32(nonce);
+
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), timeout, NULL);
+	if (rc) {
+		if (rc != -EAGAIN)
+			dev_err(hdev->dev,
+				"Failed to handle CPU-CP pkt %u, error %d\n", packet_id, rc);
+		goto out;
+	}
+
+	memcpy(data, req_cpu_addr, size);
+
+out:
+	hl_cpu_accessible_dma_pool_free(hdev, size, req_cpu_addr);
+
+	return rc;
+}
+
+int hl_fw_get_sec_attest_info(struct hl_device *hdev, struct cpucp_sec_attest_info *sec_attest_info,
+				u32 nonce)
+{
+	return hl_fw_get_sec_attest_data(hdev, CPUCP_PACKET_SEC_ATTEST_GET, sec_attest_info,
+					sizeof(struct cpucp_sec_attest_info), nonce,
+					HL_CPUCP_SEC_ATTEST_INFO_TINEOUT_USEC);
+}
+
+int hl_fw_get_dev_info_signed(struct hl_device *hdev,
+			      struct cpucp_dev_info_signed *dev_info_signed, u32 nonce)
+{
+	return hl_fw_get_sec_attest_data(hdev, CPUCP_PACKET_INFO_SIGNED_GET, dev_info_signed,
+					 sizeof(struct cpucp_dev_info_signed), nonce,
+					 HL_CPUCP_SEC_ATTEST_INFO_TINEOUT_USEC);
+}
+
+int hl_fw_send_generic_request(struct hl_device *hdev, enum hl_passthrough_type sub_opcode,
+						dma_addr_t buff, u32 *size)
+{
+	struct cpucp_packet pkt = {};
+	u64 result;
+	int rc = 0;
+
+	pkt.ctl = cpu_to_le32(CPUCP_PACKET_GENERIC_PASSTHROUGH << CPUCP_PKT_CTL_OPCODE_SHIFT);
+	pkt.addr = cpu_to_le64(buff);
+	pkt.data_max_size = cpu_to_le32(*size);
+	pkt.pkt_subidx = cpu_to_le32(sub_opcode);
+
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *)&pkt, sizeof(pkt),
+						HL_CPUCP_INFO_TIMEOUT_USEC, &result);
+	if (rc) {
+		if (rc != -EAGAIN)
+			dev_err(hdev->dev, "failed to send CPUCP data of generic fw pkt\n");
+	} else {
+		dev_dbg(hdev->dev, "generic pkt was successful, result: 0x%llx\n", result);
+	}
+
+	*size = (u32)result;
+
+	return rc;
+}
diff --git a/drivers/accel/habanalabs/common/habanalabs.h b/drivers/accel/habanalabs/common/habanalabs.h
new file mode 100644
index 000000000000..d94c2ba22a6a
--- /dev/null
+++ b/drivers/accel/habanalabs/common/habanalabs.h
@@ -0,0 +1,4298 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2023 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+#ifndef HABANALABSP_H_
+#define HABANALABSP_H_
+
+#include <linux/habanalabs/cpucp_if.h>
+#include "../include/common/qman_if.h"
+#include "../include/hw_ip/mmu/mmu_general.h"
+#include <uapi/drm/habanalabs_accel.h>
+
+#include <linux/cdev.h>
+#include <linux/iopoll.h>
+#include <linux/irqreturn.h>
+#include <linux/dma-direction.h>
+#include <linux/scatterlist.h>
+#include <linux/hashtable.h>
+#include <linux/debugfs.h>
+#include <linux/rwsem.h>
+#include <linux/eventfd.h>
+#include <linux/bitfield.h>
+#include <linux/genalloc.h>
+#include <linux/sched/signal.h>
+#include <linux/io-64-nonatomic-lo-hi.h>
+#include <linux/coresight.h>
+#include <linux/dma-buf.h>
+
+#include <drm/drm_device.h>
+#include <drm/drm_file.h>
+
+#include "security.h"
+
+#define HL_NAME				"habanalabs"
+
+struct hl_device;
+struct hl_fpriv;
+
+#define PCI_VENDOR_ID_HABANALABS	0x1da3
+
+/* Use upper bits of mmap offset to store habana driver specific information.
+ * bits[63:59] - Encode mmap type
+ * bits[45:0]  - mmap offset value
+ *
+ * NOTE: struct vm_area_struct.vm_pgoff uses offset in pages. Hence, these
+ *  defines are w.r.t to PAGE_SIZE
+ */
+#define HL_MMAP_TYPE_SHIFT		(59 - PAGE_SHIFT)
+#define HL_MMAP_TYPE_MASK		(0x1full << HL_MMAP_TYPE_SHIFT)
+#define HL_MMAP_TYPE_TS_BUFF		(0x10ull << HL_MMAP_TYPE_SHIFT)
+#define HL_MMAP_TYPE_BLOCK		(0x4ull << HL_MMAP_TYPE_SHIFT)
+#define HL_MMAP_TYPE_CB			(0x2ull << HL_MMAP_TYPE_SHIFT)
+
+#define HL_MMAP_OFFSET_VALUE_MASK	(0x1FFFFFFFFFFFull >> PAGE_SHIFT)
+#define HL_MMAP_OFFSET_VALUE_GET(off)	(off & HL_MMAP_OFFSET_VALUE_MASK)
+
+#define HL_PENDING_RESET_PER_SEC		10
+#define HL_PENDING_RESET_MAX_TRIALS		60 /* 10 minutes */
+#define HL_PENDING_RESET_LONG_SEC		60
+/*
+ * In device fini, wait 10 minutes for user processes to be terminated after we kill them.
+ * This is needed to prevent situation of clearing resources while user processes are still alive.
+ */
+#define HL_WAIT_PROCESS_KILL_ON_DEVICE_FINI	600
+
+#define HL_HARD_RESET_MAX_TIMEOUT	120
+#define HL_PLDM_HARD_RESET_MAX_TIMEOUT	(HL_HARD_RESET_MAX_TIMEOUT * 3)
+
+#define HL_DEVICE_TIMEOUT_USEC		1000000 /* 1 s */
+
+#define HL_HEARTBEAT_PER_USEC		10000000 /* 10 s */
+
+#define HL_PLL_LOW_JOB_FREQ_USEC	5000000 /* 5 s */
+
+#define HL_CPUCP_INFO_TIMEOUT_USEC	10000000 /* 10s */
+#define HL_CPUCP_EEPROM_TIMEOUT_USEC	10000000 /* 10s */
+#define HL_CPUCP_MON_DUMP_TIMEOUT_USEC	10000000 /* 10s */
+#define HL_CPUCP_SEC_ATTEST_INFO_TINEOUT_USEC 10000000 /* 10s */
+
+#define HL_FW_STATUS_POLL_INTERVAL_USEC		10000 /* 10ms */
+#define HL_FW_COMMS_STATUS_PLDM_POLL_INTERVAL_USEC	1000000 /* 1s */
+
+#define HL_PCI_ELBI_TIMEOUT_MSEC	10 /* 10ms */
+
+#define HL_INVALID_QUEUE		UINT_MAX
+
+#define HL_COMMON_USER_CQ_INTERRUPT_ID	0xFFF
+#define HL_COMMON_DEC_INTERRUPT_ID	0xFFE
+
+#define HL_STATE_DUMP_HIST_LEN			5
+#define HL_DBGFS_CFG_ACCESS_HIST_LEN		20
+#define HL_DBGFS_CFG_ACCESS_HIST_TIMEOUT_SEC	2 /* 2s */
+
+/* Default value for device reset trigger , an invalid value */
+#define HL_RESET_TRIGGER_DEFAULT	0xFF
+
+#define OBJ_NAMES_HASH_TABLE_BITS	7 /* 1 << 7 buckets */
+#define SYNC_TO_ENGINE_HASH_TABLE_BITS	7 /* 1 << 7 buckets */
+
+/* Memory */
+#define MEM_HASH_TABLE_BITS		7 /* 1 << 7 buckets */
+
+/* MMU */
+#define MMU_HASH_TABLE_BITS		7 /* 1 << 7 buckets */
+
+#define TIMESTAMP_FREE_NODES_NUM	512
+
+/**
+ * enum hl_mmu_page_table_location - mmu page table location
+ * @MMU_DR_PGT: page-table is located on device DRAM.
+ * @MMU_HR_PGT: page-table is located on host memory.
+ * @MMU_NUM_PGT_LOCATIONS: number of page-table locations currently supported.
+ */
+enum hl_mmu_page_table_location {
+	MMU_DR_PGT = 0,		/* device-dram-resident MMU PGT */
+	MMU_HR_PGT,		/* host resident MMU PGT */
+	MMU_NUM_PGT_LOCATIONS	/* num of PGT locations */
+};
+
+/*
+ * HL_RSVD_SOBS 'sync stream' reserved sync objects per QMAN stream
+ * HL_RSVD_MONS 'sync stream' reserved monitors per QMAN stream
+ */
+#define HL_RSVD_SOBS			2
+#define HL_RSVD_MONS			1
+
+/*
+ * HL_COLLECTIVE_RSVD_MSTR_MONS 'collective' reserved monitors per QMAN stream
+ */
+#define HL_COLLECTIVE_RSVD_MSTR_MONS	2
+
+#define HL_MAX_SOB_VAL			(1 << 15)
+
+#define IS_POWER_OF_2(n)		(n != 0 && ((n & (n - 1)) == 0))
+#define IS_MAX_PENDING_CS_VALID(n)	(IS_POWER_OF_2(n) && (n > 1))
+
+#define HL_PCI_NUM_BARS			6
+
+/* Completion queue entry relates to completed job */
+#define HL_COMPLETION_MODE_JOB		0
+/* Completion queue entry relates to completed command submission */
+#define HL_COMPLETION_MODE_CS		1
+
+#define HL_MAX_DCORES			8
+
+/* DMA alloc/free wrappers */
+#define hl_asic_dma_alloc_coherent(hdev, size, dma_handle, flags) \
+	hl_asic_dma_alloc_coherent_caller(hdev, size, dma_handle, flags, __func__)
+
+#define hl_asic_dma_pool_zalloc(hdev, size, mem_flags, dma_handle) \
+	hl_asic_dma_pool_zalloc_caller(hdev, size, mem_flags, dma_handle, __func__)
+
+#define hl_asic_dma_free_coherent(hdev, size, cpu_addr, dma_handle) \
+	hl_asic_dma_free_coherent_caller(hdev, size, cpu_addr, dma_handle, __func__)
+
+#define hl_asic_dma_pool_free(hdev, vaddr, dma_addr) \
+	hl_asic_dma_pool_free_caller(hdev, vaddr, dma_addr, __func__)
+
+#define hl_dma_map_sgtable(hdev, sgt, dir) \
+	hl_dma_map_sgtable_caller(hdev, sgt, dir, __func__)
+#define hl_dma_unmap_sgtable(hdev, sgt, dir) \
+	hl_dma_unmap_sgtable_caller(hdev, sgt, dir, __func__)
+
+/*
+ * Reset Flags
+ *
+ * - HL_DRV_RESET_HARD
+ *       If set do hard reset to all engines. If not set reset just
+ *       compute/DMA engines.
+ *
+ * - HL_DRV_RESET_FROM_RESET_THR
+ *       Set if the caller is the hard-reset thread
+ *
+ * - HL_DRV_RESET_HEARTBEAT
+ *       Set if reset is due to heartbeat
+ *
+ * - HL_DRV_RESET_TDR
+ *       Set if reset is due to TDR
+ *
+ * - HL_DRV_RESET_DEV_RELEASE
+ *       Set if reset is due to device release
+ *
+ * - HL_DRV_RESET_BYPASS_REQ_TO_FW
+ *       F/W will perform the reset. No need to ask it to reset the device. This is relevant
+ *       only when running with secured f/w
+ *
+ * - HL_DRV_RESET_FW_FATAL_ERR
+ *       Set if reset is due to a fatal error from FW
+ *
+ * - HL_DRV_RESET_DELAY
+ *       Set if a delay should be added before the reset
+ *
+ * - HL_DRV_RESET_FROM_WD_THR
+ *       Set if the caller is the device release watchdog thread
+ */
+
+#define HL_DRV_RESET_HARD		(1 << 0)
+#define HL_DRV_RESET_FROM_RESET_THR	(1 << 1)
+#define HL_DRV_RESET_HEARTBEAT		(1 << 2)
+#define HL_DRV_RESET_TDR		(1 << 3)
+#define HL_DRV_RESET_DEV_RELEASE	(1 << 4)
+#define HL_DRV_RESET_BYPASS_REQ_TO_FW	(1 << 5)
+#define HL_DRV_RESET_FW_FATAL_ERR	(1 << 6)
+#define HL_DRV_RESET_DELAY		(1 << 7)
+#define HL_DRV_RESET_FROM_WD_THR	(1 << 8)
+
+/*
+ * Security
+ */
+
+#define HL_PB_SHARED		1
+#define HL_PB_NA		0
+#define HL_PB_SINGLE_INSTANCE	1
+#define HL_BLOCK_SIZE		0x1000
+#define HL_BLOCK_GLBL_ERR_MASK	0xF40
+#define HL_BLOCK_GLBL_ERR_ADDR	0xF44
+#define HL_BLOCK_GLBL_ERR_CAUSE	0xF48
+#define HL_BLOCK_GLBL_SEC_OFFS	0xF80
+#define HL_BLOCK_GLBL_SEC_SIZE	(HL_BLOCK_SIZE - HL_BLOCK_GLBL_SEC_OFFS)
+#define HL_BLOCK_GLBL_SEC_LEN	(HL_BLOCK_GLBL_SEC_SIZE / sizeof(u32))
+#define UNSET_GLBL_SEC_BIT(array, b) ((array)[((b) / 32)] |= (1 << ((b) % 32)))
+
+enum hl_protection_levels {
+	SECURED_LVL,
+	PRIVILEGED_LVL,
+	NON_SECURED_LVL
+};
+
+/**
+ * struct iterate_module_ctx - HW module iterator
+ * @fn: function to apply to each HW module instance
+ * @data: optional internal data to the function iterator
+ * @rc: return code for optional use of iterator/iterator-caller
+ */
+struct iterate_module_ctx {
+	/*
+	 * callback for the HW module iterator
+	 * @hdev: pointer to the habanalabs device structure
+	 * @block: block (ASIC specific definition can be dcore/hdcore)
+	 * @inst: HW module instance within the block
+	 * @offset: current HW module instance offset from the 1-st HW module instance
+	 *          in the 1-st block
+	 * @ctx: the iterator context.
+	 */
+	void (*fn)(struct hl_device *hdev, int block, int inst, u32 offset,
+			struct iterate_module_ctx *ctx);
+	void *data;
+	int rc;
+};
+
+struct hl_block_glbl_sec {
+	u32 sec_array[HL_BLOCK_GLBL_SEC_LEN];
+};
+
+#define HL_MAX_SOBS_PER_MONITOR	8
+
+/**
+ * struct hl_gen_wait_properties - properties for generating a wait CB
+ * @data: command buffer
+ * @q_idx: queue id is used to extract fence register address
+ * @size: offset in command buffer
+ * @sob_base: SOB base to use in this wait CB
+ * @sob_val: SOB value to wait for
+ * @mon_id: monitor to use in this wait CB
+ * @sob_mask: each bit represents a SOB offset from sob_base to be used
+ */
+struct hl_gen_wait_properties {
+	void	*data;
+	u32	q_idx;
+	u32	size;
+	u16	sob_base;
+	u16	sob_val;
+	u16	mon_id;
+	u8	sob_mask;
+};
+
+/**
+ * struct pgt_info - MMU hop page info.
+ * @node: hash linked-list node for the pgts on host (shadow pgts for device resident MMU and
+ *        actual pgts for host resident MMU).
+ * @phys_addr: physical address of the pgt.
+ * @virt_addr: host virtual address of the pgt (see above device/host resident).
+ * @shadow_addr: shadow hop in the host for device resident MMU.
+ * @ctx: pointer to the owner ctx.
+ * @num_of_ptes: indicates how many ptes are used in the pgt. used only for dynamically
+ *               allocated HOPs (all HOPs but HOP0)
+ *
+ * The MMU page tables hierarchy can be placed either on the device's DRAM (in which case shadow
+ * pgts will be stored on host memory) or on host memory (in which case no shadow is required).
+ *
+ * When a new level (hop) is needed during mapping this structure will be used to describe
+ * the newly allocated hop as well as to track number of PTEs in it.
+ * During unmapping, if no valid PTEs remained in the page of a newly allocated hop, it is
+ * freed with its pgt_info structure.
+ */
+struct pgt_info {
+	struct hlist_node	node;
+	u64			phys_addr;
+	u64			virt_addr;
+	u64			shadow_addr;
+	struct hl_ctx		*ctx;
+	int			num_of_ptes;
+};
+
+/**
+ * enum hl_pci_match_mode - pci match mode per region
+ * @PCI_ADDRESS_MATCH_MODE: address match mode
+ * @PCI_BAR_MATCH_MODE: bar match mode
+ */
+enum hl_pci_match_mode {
+	PCI_ADDRESS_MATCH_MODE,
+	PCI_BAR_MATCH_MODE
+};
+
+/**
+ * enum hl_fw_component - F/W components to read version through registers.
+ * @FW_COMP_BOOT_FIT: boot fit.
+ * @FW_COMP_PREBOOT: preboot.
+ * @FW_COMP_LINUX: linux.
+ */
+enum hl_fw_component {
+	FW_COMP_BOOT_FIT,
+	FW_COMP_PREBOOT,
+	FW_COMP_LINUX,
+};
+
+/**
+ * enum hl_fw_types - F/W types present in the system
+ * @FW_TYPE_NONE: no FW component indication
+ * @FW_TYPE_LINUX: Linux image for device CPU
+ * @FW_TYPE_BOOT_CPU: Boot image for device CPU
+ * @FW_TYPE_PREBOOT_CPU: Indicates pre-loaded CPUs are present in the system
+ *                       (preboot, ppboot etc...)
+ * @FW_TYPE_ALL_TYPES: Mask for all types
+ */
+enum hl_fw_types {
+	FW_TYPE_NONE = 0x0,
+	FW_TYPE_LINUX = 0x1,
+	FW_TYPE_BOOT_CPU = 0x2,
+	FW_TYPE_PREBOOT_CPU = 0x4,
+	FW_TYPE_ALL_TYPES =
+		(FW_TYPE_LINUX | FW_TYPE_BOOT_CPU | FW_TYPE_PREBOOT_CPU)
+};
+
+/**
+ * enum hl_queue_type - Supported QUEUE types.
+ * @QUEUE_TYPE_NA: queue is not available.
+ * @QUEUE_TYPE_EXT: external queue which is a DMA channel that may access the
+ *                  host.
+ * @QUEUE_TYPE_INT: internal queue that performs DMA inside the device's
+ *			memories and/or operates the compute engines.
+ * @QUEUE_TYPE_CPU: S/W queue for communication with the device's CPU.
+ * @QUEUE_TYPE_HW: queue of DMA and compute engines jobs, for which completion
+ *                 notifications are sent by H/W.
+ */
+enum hl_queue_type {
+	QUEUE_TYPE_NA,
+	QUEUE_TYPE_EXT,
+	QUEUE_TYPE_INT,
+	QUEUE_TYPE_CPU,
+	QUEUE_TYPE_HW
+};
+
+enum hl_cs_type {
+	CS_TYPE_DEFAULT,
+	CS_TYPE_SIGNAL,
+	CS_TYPE_WAIT,
+	CS_TYPE_COLLECTIVE_WAIT,
+	CS_RESERVE_SIGNALS,
+	CS_UNRESERVE_SIGNALS,
+	CS_TYPE_ENGINE_CORE,
+	CS_TYPE_ENGINES,
+	CS_TYPE_FLUSH_PCI_HBW_WRITES,
+};
+
+/*
+ * struct hl_inbound_pci_region - inbound region descriptor
+ * @mode: pci match mode for this region
+ * @addr: region target address
+ * @size: region size in bytes
+ * @offset_in_bar: offset within bar (address match mode)
+ * @bar: bar id
+ */
+struct hl_inbound_pci_region {
+	enum hl_pci_match_mode	mode;
+	u64			addr;
+	u64			size;
+	u64			offset_in_bar;
+	u8			bar;
+};
+
+/*
+ * struct hl_outbound_pci_region - outbound region descriptor
+ * @addr: region target address
+ * @size: region size in bytes
+ */
+struct hl_outbound_pci_region {
+	u64	addr;
+	u64	size;
+};
+
+/*
+ * enum queue_cb_alloc_flags - Indicates queue support for CBs that
+ * allocated by Kernel or by User
+ * @CB_ALLOC_KERNEL: support only CBs that allocated by Kernel
+ * @CB_ALLOC_USER: support only CBs that allocated by User
+ */
+enum queue_cb_alloc_flags {
+	CB_ALLOC_KERNEL = 0x1,
+	CB_ALLOC_USER   = 0x2
+};
+
+/*
+ * struct hl_hw_sob - H/W SOB info.
+ * @hdev: habanalabs device structure.
+ * @kref: refcount of this SOB. The SOB will reset once the refcount is zero.
+ * @sob_id: id of this SOB.
+ * @sob_addr: the sob offset from the base address.
+ * @q_idx: the H/W queue that uses this SOB.
+ * @need_reset: reset indication set when switching to the other sob.
+ */
+struct hl_hw_sob {
+	struct hl_device	*hdev;
+	struct kref		kref;
+	u32			sob_id;
+	u32			sob_addr;
+	u32			q_idx;
+	bool			need_reset;
+};
+
+enum hl_collective_mode {
+	HL_COLLECTIVE_NOT_SUPPORTED = 0x0,
+	HL_COLLECTIVE_MASTER = 0x1,
+	HL_COLLECTIVE_SLAVE = 0x2
+};
+
+/**
+ * struct hw_queue_properties - queue information.
+ * @type: queue type.
+ * @cb_alloc_flags: bitmap which indicates if the hw queue supports CB
+ *                  that allocated by the Kernel driver and therefore,
+ *                  a CB handle can be provided for jobs on this queue.
+ *                  Otherwise, a CB address must be provided.
+ * @collective_mode: collective mode of current queue
+ * @q_dram_bd_address: PQ dram address, used when PQ need to reside in DRAM.
+ * @driver_only: true if only the driver is allowed to send a job to this queue,
+ *               false otherwise.
+ * @binned: True if the queue is binned out and should not be used
+ * @supports_sync_stream: True if queue supports sync stream
+ * @dram_bd: True if the bd should be copied to dram, needed for PQ which has been allocated on dram
+ */
+struct hw_queue_properties {
+	enum hl_queue_type		type;
+	enum queue_cb_alloc_flags	cb_alloc_flags;
+	enum hl_collective_mode		collective_mode;
+	u64				q_dram_bd_address;
+	u8				driver_only;
+	u8				binned;
+	u8				supports_sync_stream;
+	u8				dram_bd;
+};
+
+/**
+ * enum vm_type - virtual memory mapping request information.
+ * @VM_TYPE_USERPTR: mapping of user memory to device virtual address.
+ * @VM_TYPE_PHYS_PACK: mapping of DRAM memory to device virtual address.
+ */
+enum vm_type {
+	VM_TYPE_USERPTR = 0x1,
+	VM_TYPE_PHYS_PACK = 0x2
+};
+
+/**
+ * enum mmu_op_flags - mmu operation relevant information.
+ * @MMU_OP_USERPTR: operation on user memory (host resident).
+ * @MMU_OP_PHYS_PACK: operation on DRAM (device resident).
+ * @MMU_OP_CLEAR_MEMCACHE: operation has to clear memcache.
+ * @MMU_OP_SKIP_LOW_CACHE_INV: operation is allowed to skip parts of cache invalidation.
+ */
+enum mmu_op_flags {
+	MMU_OP_USERPTR = 0x1,
+	MMU_OP_PHYS_PACK = 0x2,
+	MMU_OP_CLEAR_MEMCACHE = 0x4,
+	MMU_OP_SKIP_LOW_CACHE_INV = 0x8,
+};
+
+
+/**
+ * enum hl_device_hw_state - H/W device state. use this to understand whether
+ *                           to do reset before hw_init or not
+ * @HL_DEVICE_HW_STATE_CLEAN: H/W state is clean. i.e. after hard reset
+ * @HL_DEVICE_HW_STATE_DIRTY: H/W state is dirty. i.e. we started to execute
+ *                            hw_init
+ */
+enum hl_device_hw_state {
+	HL_DEVICE_HW_STATE_CLEAN = 0,
+	HL_DEVICE_HW_STATE_DIRTY
+};
+
+#define HL_MMU_VA_ALIGNMENT_NOT_NEEDED 0
+
+/**
+ * struct hl_mmu_properties - ASIC specific MMU address translation properties.
+ * @start_addr: virtual start address of the memory region.
+ * @end_addr: virtual end address of the memory region.
+ * @hop_shifts: array holds HOPs shifts.
+ * @hop_masks: array holds HOPs masks.
+ * @last_mask: mask to get the bit indicating this is the last hop.
+ * @pgt_size: size for page tables.
+ * @supported_pages_mask: bitmask for supported page size (relevant only for MMUs
+ *                        supporting multiple page size).
+ * @page_size: default page size used to allocate memory.
+ * @num_hops: The amount of hops supported by the translation table.
+ * @hop_table_size: HOP table size.
+ * @hop0_tables_total_size: total size for all HOP0 tables.
+ * @host_resident: Should the MMU page table reside in host memory or in the
+ *                 device DRAM.
+ */
+struct hl_mmu_properties {
+	u64	start_addr;
+	u64	end_addr;
+	u64	hop_shifts[MMU_HOP_MAX];
+	u64	hop_masks[MMU_HOP_MAX];
+	u64	last_mask;
+	u64	pgt_size;
+	u64	supported_pages_mask;
+	u32	page_size;
+	u32	num_hops;
+	u32	hop_table_size;
+	u32	hop0_tables_total_size;
+	u8	host_resident;
+};
+
+/**
+ * struct hl_hints_range - hint addresses reserved va range.
+ * @start_addr: start address of the va range.
+ * @end_addr: end address of the va range.
+ */
+struct hl_hints_range {
+	u64 start_addr;
+	u64 end_addr;
+};
+
+/**
+ * struct asic_fixed_properties - ASIC specific immutable properties.
+ * @hw_queues_props: H/W queues properties.
+ * @special_blocks: points to an array containing special blocks info.
+ * @skip_special_blocks_cfg: special blocks skip configs.
+ * @cpucp_info: received various information from CPU-CP regarding the H/W, e.g.
+ *		available sensors.
+ * @uboot_ver: F/W U-boot version.
+ * @preboot_ver: F/W Preboot version.
+ * @dmmu: DRAM MMU address translation properties.
+ * @pmmu: PCI (host) MMU address translation properties.
+ * @pmmu_huge: PCI (host) MMU address translation properties for memory
+ *              allocated with huge pages.
+ * @hints_dram_reserved_va_range: dram hint addresses reserved range.
+ * @hints_host_reserved_va_range: host hint addresses reserved range.
+ * @hints_host_hpage_reserved_va_range: host huge page hint addresses reserved range.
+ * @sram_base_address: SRAM physical start address.
+ * @sram_end_address: SRAM physical end address.
+ * @sram_user_base_address - SRAM physical start address for user access.
+ * @dram_base_address: DRAM physical start address.
+ * @dram_end_address: DRAM physical end address.
+ * @dram_user_base_address: DRAM physical start address for user access.
+ * @dram_size: DRAM total size.
+ * @dram_pci_bar_size: size of PCI bar towards DRAM.
+ * @max_power_default: max power of the device after reset.
+ * @dc_power_default: power consumed by the device in mode idle.
+ * @dram_size_for_default_page_mapping: DRAM size needed to map to avoid page
+ *                                      fault.
+ * @pcie_dbi_base_address: Base address of the PCIE_DBI block.
+ * @pcie_aux_dbi_reg_addr: Address of the PCIE_AUX DBI register.
+ * @mmu_pgt_addr: base physical address in DRAM of MMU page tables.
+ * @mmu_dram_default_page_addr: DRAM default page physical address.
+ * @tpc_enabled_mask: which TPCs are enabled.
+ * @tpc_binning_mask: which TPCs are binned. 0 means usable and 1 means binned.
+ * @dram_enabled_mask: which DRAMs are enabled.
+ * @dram_binning_mask: which DRAMs are binned. 0 means usable, 1 means binned.
+ * @dram_hints_align_mask: dram va hint addresses alignment mask which is used
+ *                  for hints validity check.
+ * @cfg_base_address: config space base address.
+ * @mmu_cache_mng_addr: address of the MMU cache.
+ * @mmu_cache_mng_size: size of the MMU cache.
+ * @device_dma_offset_for_host_access: the offset to add to host DMA addresses
+ *                                     to enable the device to access them.
+ * @host_base_address: host physical start address for host DMA from device
+ * @host_end_address: host physical end address for host DMA from device
+ * @max_freq_value: current max clk frequency.
+ * @engine_core_interrupt_reg_addr: interrupt register address for engine core to use
+ *                                  in order to raise events toward FW.
+ * @clk_pll_index: clock PLL index that specify which PLL determines the clock
+ *                 we display to the user
+ * @mmu_pgt_size: MMU page tables total size.
+ * @mmu_pte_size: PTE size in MMU page tables.
+ * @dram_page_size: The DRAM physical page size.
+ * @cfg_size: configuration space size on SRAM.
+ * @sram_size: total size of SRAM.
+ * @max_asid: maximum number of open contexts (ASIDs).
+ * @num_of_events: number of possible internal H/W IRQs.
+ * @psoc_pci_pll_nr: PCI PLL NR value.
+ * @psoc_pci_pll_nf: PCI PLL NF value.
+ * @psoc_pci_pll_od: PCI PLL OD value.
+ * @psoc_pci_pll_div_factor: PCI PLL DIV FACTOR 1 value.
+ * @psoc_timestamp_frequency: frequency of the psoc timestamp clock.
+ * @high_pll: high PLL frequency used by the device.
+ * @cb_pool_cb_cnt: number of CBs in the CB pool.
+ * @cb_pool_cb_size: size of each CB in the CB pool.
+ * @decoder_enabled_mask: which decoders are enabled.
+ * @decoder_binning_mask: which decoders are binned, 0 means usable and 1 means binned.
+ * @rotator_enabled_mask: which rotators are enabled.
+ * @edma_enabled_mask: which EDMAs are enabled.
+ * @edma_binning_mask: which EDMAs are binned, 0 means usable and 1 means
+ *                     binned (at most one binned DMA).
+ * @max_pending_cs: maximum of concurrent pending command submissions
+ * @max_queues: maximum amount of queues in the system
+ * @fw_preboot_cpu_boot_dev_sts0: bitmap representation of preboot cpu
+ *                                capabilities reported by FW, bit description
+ *                                can be found in CPU_BOOT_DEV_STS0
+ * @fw_preboot_cpu_boot_dev_sts1: bitmap representation of preboot cpu
+ *                                capabilities reported by FW, bit description
+ *                                can be found in CPU_BOOT_DEV_STS1
+ * @fw_bootfit_cpu_boot_dev_sts0: bitmap representation of boot cpu security
+ *                                status reported by FW, bit description can be
+ *                                found in CPU_BOOT_DEV_STS0
+ * @fw_bootfit_cpu_boot_dev_sts1: bitmap representation of boot cpu security
+ *                                status reported by FW, bit description can be
+ *                                found in CPU_BOOT_DEV_STS1
+ * @fw_app_cpu_boot_dev_sts0: bitmap representation of application security
+ *                            status reported by FW, bit description can be
+ *                            found in CPU_BOOT_DEV_STS0
+ * @fw_app_cpu_boot_dev_sts1: bitmap representation of application security
+ *                            status reported by FW, bit description can be
+ *                            found in CPU_BOOT_DEV_STS1
+ * @max_dec: maximum number of decoders
+ * @hmmu_hif_enabled_mask: mask of HMMUs/HIFs that are not isolated (enabled)
+ *                         1- enabled, 0- isolated.
+ * @faulty_dram_cluster_map: mask of faulty DRAM cluster.
+ *                         1- faulty cluster, 0- good cluster.
+ * @xbar_edge_enabled_mask: mask of XBAR_EDGEs that are not isolated (enabled)
+ *                          1- enabled, 0- isolated.
+ * @device_mem_alloc_default_page_size: may be different than dram_page_size only for ASICs for
+ *                                      which the property supports_user_set_page_size is true
+ *                                      (i.e. the DRAM supports multiple page sizes), otherwise
+ *                                      it will shall  be equal to dram_page_size.
+ * @num_engine_cores: number of engine cpu cores.
+ * @max_num_of_engines: maximum number of all engines in the ASIC.
+ * @num_of_special_blocks: special_blocks array size.
+ * @glbl_err_max_cause_num: global err max cause number.
+ * @hbw_flush_reg: register to read to generate HBW flush. value of 0 means HBW flush is
+ *                 not supported.
+ * @reserved_fw_mem_size: size of dram memory reserved for FW.
+ * @fw_event_queue_size: queue size for events from CPU-CP.
+ *                       A value of 0 means using the default HL_EQ_SIZE_IN_BYTES value.
+ * @collective_first_sob: first sync object available for collective use
+ * @collective_first_mon: first monitor available for collective use
+ * @sync_stream_first_sob: first sync object available for sync stream use
+ * @sync_stream_first_mon: first monitor available for sync stream use
+ * @first_available_user_sob: first sob available for the user
+ * @first_available_user_mon: first monitor available for the user
+ * @first_available_user_interrupt: first available interrupt reserved for the user
+ * @first_available_cq: first available CQ for the user.
+ * @user_interrupt_count: number of user interrupts.
+ * @user_dec_intr_count: number of decoder interrupts exposed to user.
+ * @tpc_interrupt_id: interrupt id for TPC to use in order to raise events towards the host.
+ * @eq_interrupt_id: interrupt id for EQ, uses to synchronize EQ interrupts in hard-reset.
+ * @cache_line_size: device cache line size.
+ * @server_type: Server type that the ASIC is currently installed in.
+ *               The value is according to enum hl_server_type in uapi file.
+ * @completion_queues_count: number of completion queues.
+ * @completion_mode: 0 - job based completion, 1 - cs based completion
+ * @mme_master_slave_mode: 0 - Each MME works independently, 1 - MME works
+ *                         in Master/Slave mode
+ * @fw_security_enabled: true if security measures are enabled in firmware,
+ *                       false otherwise
+ * @fw_cpu_boot_dev_sts0_valid: status bits are valid and can be fetched from
+ *                              BOOT_DEV_STS0
+ * @fw_cpu_boot_dev_sts1_valid: status bits are valid and can be fetched from
+ *                              BOOT_DEV_STS1
+ * @dram_supports_virtual_memory: is there an MMU towards the DRAM
+ * @hard_reset_done_by_fw: true if firmware is handling hard reset flow
+ * @num_functional_hbms: number of functional HBMs in each DCORE.
+ * @hints_range_reservation: device support hint addresses range reservation.
+ * @iatu_done_by_fw: true if iATU configuration is being done by FW.
+ * @dynamic_fw_load: is dynamic FW load is supported.
+ * @gic_interrupts_enable: true if FW is not blocking GIC controller,
+ *                         false otherwise.
+ * @use_get_power_for_reset_history: To support backward compatibility for Goya
+ *                                   and Gaudi
+ * @supports_compute_reset: is a reset which is not a hard-reset supported by this asic.
+ * @allow_inference_soft_reset: true if the ASIC supports soft reset that is
+ *                              initiated by user or TDR. This is only true
+ *                              in inference ASICs, as there is no real-world
+ *                              use-case of doing soft-reset in training (due
+ *                              to the fact that training runs on multiple
+ *                              devices)
+ * @configurable_stop_on_err: is stop-on-error option configurable via debugfs.
+ * @set_max_power_on_device_init: true if need to set max power in F/W on device init.
+ * @supports_user_set_page_size: true if user can set the allocation page size.
+ * @dma_mask: the dma mask to be set for this device.
+ * @supports_advanced_cpucp_rc: true if new cpucp opcodes are supported.
+ * @supports_engine_modes: true if changing engines/engine_cores modes is supported.
+ * @support_dynamic_resereved_fw_size: true if we support dynamic reserved size for fw.
+ * @supports_nvme: indicates whether the asic supports NVMe P2P DMA.
+ */
+struct asic_fixed_properties {
+	struct hw_queue_properties	*hw_queues_props;
+	struct hl_special_block_info	*special_blocks;
+	struct hl_skip_blocks_cfg	skip_special_blocks_cfg;
+	struct cpucp_info		cpucp_info;
+	char				uboot_ver[VERSION_MAX_LEN];
+	char				preboot_ver[VERSION_MAX_LEN];
+	struct hl_mmu_properties	dmmu;
+	struct hl_mmu_properties	pmmu;
+	struct hl_mmu_properties	pmmu_huge;
+	struct hl_hints_range		hints_dram_reserved_va_range;
+	struct hl_hints_range		hints_host_reserved_va_range;
+	struct hl_hints_range		hints_host_hpage_reserved_va_range;
+	u64				sram_base_address;
+	u64				sram_end_address;
+	u64				sram_user_base_address;
+	u64				dram_base_address;
+	u64				dram_end_address;
+	u64				dram_user_base_address;
+	u64				dram_size;
+	u64				dram_pci_bar_size;
+	u64				max_power_default;
+	u64				dc_power_default;
+	u64				dram_size_for_default_page_mapping;
+	u64				pcie_dbi_base_address;
+	u64				pcie_aux_dbi_reg_addr;
+	u64				mmu_pgt_addr;
+	u64				mmu_dram_default_page_addr;
+	u64				tpc_enabled_mask;
+	u64				tpc_binning_mask;
+	u64				dram_enabled_mask;
+	u64				dram_binning_mask;
+	u64				dram_hints_align_mask;
+	u64				cfg_base_address;
+	u64				mmu_cache_mng_addr;
+	u64				mmu_cache_mng_size;
+	u64				device_dma_offset_for_host_access;
+	u64				host_base_address;
+	u64				host_end_address;
+	u64				max_freq_value;
+	u64				engine_core_interrupt_reg_addr;
+	u32				clk_pll_index;
+	u32				mmu_pgt_size;
+	u32				mmu_pte_size;
+	u32				dram_page_size;
+	u32				cfg_size;
+	u32				sram_size;
+	u32				max_asid;
+	u32				num_of_events;
+	u32				psoc_pci_pll_nr;
+	u32				psoc_pci_pll_nf;
+	u32				psoc_pci_pll_od;
+	u32				psoc_pci_pll_div_factor;
+	u32				psoc_timestamp_frequency;
+	u32				high_pll;
+	u32				cb_pool_cb_cnt;
+	u32				cb_pool_cb_size;
+	u32				decoder_enabled_mask;
+	u32				decoder_binning_mask;
+	u32				rotator_enabled_mask;
+	u32				edma_enabled_mask;
+	u32				edma_binning_mask;
+	u32				max_pending_cs;
+	u32				max_queues;
+	u32				fw_preboot_cpu_boot_dev_sts0;
+	u32				fw_preboot_cpu_boot_dev_sts1;
+	u32				fw_bootfit_cpu_boot_dev_sts0;
+	u32				fw_bootfit_cpu_boot_dev_sts1;
+	u32				fw_app_cpu_boot_dev_sts0;
+	u32				fw_app_cpu_boot_dev_sts1;
+	u32				max_dec;
+	u32				hmmu_hif_enabled_mask;
+	u32				faulty_dram_cluster_map;
+	u32				xbar_edge_enabled_mask;
+	u32				device_mem_alloc_default_page_size;
+	u32				num_engine_cores;
+	u32				max_num_of_engines;
+	u32				num_of_special_blocks;
+	u32				glbl_err_max_cause_num;
+	u32				hbw_flush_reg;
+	u32				reserved_fw_mem_size;
+	u32				fw_event_queue_size;
+	u16				collective_first_sob;
+	u16				collective_first_mon;
+	u16				sync_stream_first_sob;
+	u16				sync_stream_first_mon;
+	u16				first_available_user_sob[HL_MAX_DCORES];
+	u16				first_available_user_mon[HL_MAX_DCORES];
+	u16				first_available_user_interrupt;
+	u16				first_available_cq[HL_MAX_DCORES];
+	u16				user_interrupt_count;
+	u16				user_dec_intr_count;
+	u16				tpc_interrupt_id;
+	u16				eq_interrupt_id;
+	u16				cache_line_size;
+	u16				server_type;
+	u8				completion_queues_count;
+	u8				completion_mode;
+	u8				mme_master_slave_mode;
+	u8				fw_security_enabled;
+	u8				fw_cpu_boot_dev_sts0_valid;
+	u8				fw_cpu_boot_dev_sts1_valid;
+	u8				dram_supports_virtual_memory;
+	u8				hard_reset_done_by_fw;
+	u8				num_functional_hbms;
+	u8				hints_range_reservation;
+	u8				iatu_done_by_fw;
+	u8				dynamic_fw_load;
+	u8				gic_interrupts_enable;
+	u8				use_get_power_for_reset_history;
+	u8				supports_compute_reset;
+	u8				allow_inference_soft_reset;
+	u8				configurable_stop_on_err;
+	u8				set_max_power_on_device_init;
+	u8				supports_user_set_page_size;
+	u8				dma_mask;
+	u8				supports_advanced_cpucp_rc;
+	u8				supports_engine_modes;
+	u8				support_dynamic_resereved_fw_size;
+	u8				supports_nvme;
+};
+
+/**
+ * struct hl_fence - software synchronization primitive
+ * @completion: fence is implemented using completion
+ * @refcount: refcount for this fence
+ * @cs_sequence: sequence of the corresponding command submission
+ * @stream_master_qid_map: streams masters QID bitmap to represent all streams
+ *                         masters QIDs that multi cs is waiting on
+ * @error: mark this fence with error
+ * @timestamp: timestamp upon completion
+ * @mcs_handling_done: indicates that corresponding command submission has
+ *                     finished msc handling, this does not mean it was part
+ *                     of the mcs
+ */
+struct hl_fence {
+	struct completion	completion;
+	struct kref		refcount;
+	u64			cs_sequence;
+	u32			stream_master_qid_map;
+	int			error;
+	ktime_t			timestamp;
+	u8			mcs_handling_done;
+};
+
+/**
+ * struct hl_cs_compl - command submission completion object.
+ * @base_fence: hl fence object.
+ * @lock: spinlock to protect fence.
+ * @hdev: habanalabs device structure.
+ * @hw_sob: the H/W SOB used in this signal/wait CS.
+ * @encaps_sig_hdl: encaps signals handler.
+ * @cs_seq: command submission sequence number.
+ * @type: type of the CS - signal/wait.
+ * @sob_val: the SOB value that is used in this signal/wait CS.
+ * @sob_group: the SOB group that is used in this collective wait CS.
+ * @encaps_signals: indication whether it's a completion object of cs with
+ * encaps signals or not.
+ */
+struct hl_cs_compl {
+	struct hl_fence		base_fence;
+	spinlock_t		lock;
+	struct hl_device	*hdev;
+	struct hl_hw_sob	*hw_sob;
+	struct hl_cs_encaps_sig_handle *encaps_sig_hdl;
+	u64			cs_seq;
+	enum hl_cs_type		type;
+	u16			sob_val;
+	u16			sob_group;
+	bool			encaps_signals;
+};
+
+/*
+ * Command Buffers
+ */
+
+/**
+ * struct hl_ts_buff - describes a timestamp buffer.
+ * @kernel_buff_address: Holds the internal buffer's kernel virtual address.
+ * @user_buff_address: Holds the user buffer's kernel virtual address.
+ * @kernel_buff_size: Holds the internal kernel buffer size.
+ */
+struct hl_ts_buff {
+	void			*kernel_buff_address;
+	void			*user_buff_address;
+	u32			kernel_buff_size;
+};
+
+struct hl_mmap_mem_buf;
+
+/**
+ * struct hl_mem_mgr - describes unified memory manager for mappable memory chunks.
+ * @dev: back pointer to the owning device
+ * @lock: protects handles
+ * @handles: an idr holding all active handles to the memory buffers in the system.
+ */
+struct hl_mem_mgr {
+	struct device *dev;
+	spinlock_t lock;
+	struct idr handles;
+};
+
+/**
+ * struct hl_mem_mgr_fini_stats - describes statistics returned during memory manager teardown.
+ * @n_busy_cb: the amount of CB handles that could not be removed
+ * @n_busy_ts: the amount of TS handles that could not be removed
+ * @n_busy_other: the amount of any other type of handles that could not be removed
+ */
+struct hl_mem_mgr_fini_stats {
+	u32 n_busy_cb;
+	u32 n_busy_ts;
+	u32 n_busy_other;
+};
+
+/**
+ * struct hl_mmap_mem_buf_behavior - describes unified memory manager buffer behavior
+ * @topic: string identifier used for logging
+ * @mem_id: memory type identifier, embedded in the handle and used to identify
+ *          the memory type by handle.
+ * @alloc: callback executed on buffer allocation, shall allocate the memory,
+ *         set it under buffer private, and set mappable size.
+ * @mmap: callback executed on mmap, must map the buffer to vma
+ * @release: callback executed on release, must free the resources used by the buffer
+ */
+struct hl_mmap_mem_buf_behavior {
+	const char *topic;
+	u64 mem_id;
+
+	int (*alloc)(struct hl_mmap_mem_buf *buf, gfp_t gfp, void *args);
+	int (*mmap)(struct hl_mmap_mem_buf *buf, struct vm_area_struct *vma, void *args);
+	void (*release)(struct hl_mmap_mem_buf *buf);
+};
+
+/**
+ * struct hl_mmap_mem_buf - describes a single unified memory buffer
+ * @behavior: buffer behavior
+ * @mmg: back pointer to the unified memory manager
+ * @refcount: reference counter for buffer users
+ * @private: pointer to buffer behavior private data
+ * @mmap: atomic boolean indicating whether or not the buffer is mapped right now
+ * @real_mapped_size: the actual size of buffer mapped, after part of it may be released,
+ *                   may change at runtime.
+ * @mappable_size: the original mappable size of the buffer, does not change after
+ *                 the allocation.
+ * @handle: the buffer id in mmg handles store
+ */
+struct hl_mmap_mem_buf {
+	struct hl_mmap_mem_buf_behavior *behavior;
+	struct hl_mem_mgr *mmg;
+	struct kref refcount;
+	void *private;
+	atomic_t mmap;
+	u64 real_mapped_size;
+	u64 mappable_size;
+	u64 handle;
+};
+
+/**
+ * struct hl_cb - describes a Command Buffer.
+ * @hdev: pointer to device this CB belongs to.
+ * @ctx: pointer to the CB owner's context.
+ * @buf: back pointer to the parent mappable memory buffer
+ * @debugfs_list: node in debugfs list of command buffers.
+ * @pool_list: node in pool list of command buffers.
+ * @kernel_address: Holds the CB's kernel virtual address.
+ * @virtual_addr: Holds the CB's virtual address.
+ * @bus_address: Holds the CB's DMA address.
+ * @size: holds the CB's size.
+ * @roundup_size: holds the cb size after roundup to page size.
+ * @cs_cnt: holds number of CS that this CB participates in.
+ * @is_handle_destroyed: atomic boolean indicating whether or not the CB handle was destroyed.
+ * @is_pool: true if CB was acquired from the pool, false otherwise.
+ * @is_internal: internally allocated
+ * @is_mmu_mapped: true if the CB is mapped to the device's MMU.
+ */
+struct hl_cb {
+	struct hl_device	*hdev;
+	struct hl_ctx		*ctx;
+	struct hl_mmap_mem_buf	*buf;
+	struct list_head	debugfs_list;
+	struct list_head	pool_list;
+	void			*kernel_address;
+	u64			virtual_addr;
+	dma_addr_t		bus_address;
+	u32			size;
+	u32			roundup_size;
+	atomic_t		cs_cnt;
+	atomic_t		is_handle_destroyed;
+	u8			is_pool;
+	u8			is_internal;
+	u8			is_mmu_mapped;
+};
+
+
+/*
+ * QUEUES
+ */
+
+struct hl_cs_job;
+
+/* Queue length of external and HW queues */
+#define HL_QUEUE_LENGTH			4096
+#define HL_QUEUE_SIZE_IN_BYTES		(HL_QUEUE_LENGTH * HL_BD_SIZE)
+
+#if (HL_MAX_JOBS_PER_CS > HL_QUEUE_LENGTH)
+#error "HL_QUEUE_LENGTH must be greater than HL_MAX_JOBS_PER_CS"
+#endif
+
+/* HL_CQ_LENGTH is in units of struct hl_cq_entry */
+#define HL_CQ_LENGTH			HL_QUEUE_LENGTH
+#define HL_CQ_SIZE_IN_BYTES		(HL_CQ_LENGTH * HL_CQ_ENTRY_SIZE)
+
+/* Must be power of 2 */
+#define HL_EQ_LENGTH			64
+#define HL_EQ_SIZE_IN_BYTES		(HL_EQ_LENGTH * HL_EQ_ENTRY_SIZE)
+
+/* Host <-> CPU-CP shared memory size */
+#define HL_CPU_ACCESSIBLE_MEM_SIZE	SZ_2M
+
+/**
+ * struct hl_sync_stream_properties -
+ *     describes a H/W queue sync stream properties
+ * @hw_sob: array of the used H/W SOBs by this H/W queue.
+ * @next_sob_val: the next value to use for the currently used SOB.
+ * @base_sob_id: the base SOB id of the SOBs used by this queue.
+ * @base_mon_id: the base MON id of the MONs used by this queue.
+ * @collective_mstr_mon_id: the MON ids of the MONs used by this master queue
+ *                          in order to sync with all slave queues.
+ * @collective_slave_mon_id: the MON id used by this slave queue in order to
+ *                           sync with its master queue.
+ * @collective_sob_id: current SOB id used by this collective slave queue
+ *                     to signal its collective master queue upon completion.
+ * @curr_sob_offset: the id offset to the currently used SOB from the
+ *                   HL_RSVD_SOBS that are being used by this queue.
+ */
+struct hl_sync_stream_properties {
+	struct hl_hw_sob hw_sob[HL_RSVD_SOBS];
+	u16		next_sob_val;
+	u16		base_sob_id;
+	u16		base_mon_id;
+	u16		collective_mstr_mon_id[HL_COLLECTIVE_RSVD_MSTR_MONS];
+	u16		collective_slave_mon_id;
+	u16		collective_sob_id;
+	u8		curr_sob_offset;
+};
+
+/**
+ * struct hl_encaps_signals_mgr - describes sync stream encapsulated signals
+ * handlers manager
+ * @lock: protects handles.
+ * @handles: an idr to hold all encapsulated signals handles.
+ */
+struct hl_encaps_signals_mgr {
+	spinlock_t		lock;
+	struct idr		handles;
+};
+
+/**
+ * struct hl_hw_queue - describes a H/W transport queue.
+ * @shadow_queue: pointer to a shadow queue that holds pointers to jobs.
+ * @sync_stream_prop: sync stream queue properties
+ * @queue_type: type of queue.
+ * @collective_mode: collective mode of current queue
+ * @kernel_address: holds the queue's kernel virtual address.
+ * @bus_address: holds the queue's DMA address.
+ * @pq_dram_address: hold the dram address when the PQ is allocated, used when dram_bd is true in
+ *                   queue properites.
+ * @pi: holds the queue's pi value.
+ * @ci: holds the queue's ci value, AS CALCULATED BY THE DRIVER (not real ci).
+ * @hw_queue_id: the id of the H/W queue.
+ * @cq_id: the id for the corresponding CQ for this H/W queue.
+ * @msi_vec: the IRQ number of the H/W queue.
+ * @int_queue_len: length of internal queue (number of entries).
+ * @valid: is the queue valid (we have array of 32 queues, not all of them
+ *         exist).
+ * @supports_sync_stream: True if queue supports sync stream
+ * @dram_bd: True if the bd should be copied to dram, needed for PQ which has been allocated on dram
+ */
+struct hl_hw_queue {
+	struct hl_cs_job			**shadow_queue;
+	struct hl_sync_stream_properties	sync_stream_prop;
+	enum hl_queue_type			queue_type;
+	enum hl_collective_mode			collective_mode;
+	void					*kernel_address;
+	dma_addr_t				bus_address;
+	u64					pq_dram_address;
+	u32					pi;
+	atomic_t				ci;
+	u32					hw_queue_id;
+	u32					cq_id;
+	u32					msi_vec;
+	u16					int_queue_len;
+	u8					valid;
+	u8					supports_sync_stream;
+	u8					dram_bd;
+};
+
+/**
+ * struct hl_cq - describes a completion queue
+ * @hdev: pointer to the device structure
+ * @kernel_address: holds the queue's kernel virtual address
+ * @bus_address: holds the queue's DMA address
+ * @cq_idx: completion queue index in array
+ * @hw_queue_id: the id of the matching H/W queue
+ * @ci: ci inside the queue
+ * @pi: pi inside the queue
+ * @free_slots_cnt: counter of free slots in queue
+ */
+struct hl_cq {
+	struct hl_device	*hdev;
+	void			*kernel_address;
+	dma_addr_t		bus_address;
+	u32			cq_idx;
+	u32			hw_queue_id;
+	u32			ci;
+	u32			pi;
+	atomic_t		free_slots_cnt;
+};
+
+enum hl_user_interrupt_type {
+	HL_USR_INTERRUPT_CQ = 0,
+	HL_USR_INTERRUPT_DECODER,
+	HL_USR_INTERRUPT_TPC,
+	HL_USR_INTERRUPT_UNEXPECTED
+};
+
+/**
+ * struct hl_ts_free_jobs - holds user interrupt ts free nodes related data
+ * @free_nodes_pool: pool of nodes to be used for free timestamp jobs
+ * @free_nodes_length: number of nodes in free_nodes_pool
+ * @next_avail_free_node_idx: index of the next free node in the pool
+ *
+ * the free nodes pool must be protected by the user interrupt lock
+ * to avoid race between different interrupts which are using the same
+ * ts buffer with different offsets.
+ */
+struct hl_ts_free_jobs {
+	struct timestamp_reg_free_node *free_nodes_pool;
+	u32				free_nodes_length;
+	u32				next_avail_free_node_idx;
+};
+
+/**
+ * struct hl_user_interrupt - holds user interrupt information
+ * @hdev: pointer to the device structure
+ * @ts_free_jobs_data: timestamp free jobs related data
+ * @type: user interrupt type
+ * @wait_list_head: head to the list of user threads pending on this interrupt
+ * @ts_list_head: head to the list of timestamp records
+ * @wait_list_lock: protects wait_list_head
+ * @ts_list_lock: protects ts_list_head
+ * @timestamp: last timestamp taken upon interrupt
+ * @interrupt_id: msix interrupt id
+ */
+struct hl_user_interrupt {
+	struct hl_device		*hdev;
+	struct hl_ts_free_jobs		ts_free_jobs_data;
+	enum hl_user_interrupt_type	type;
+	struct list_head		wait_list_head;
+	struct list_head		ts_list_head;
+	spinlock_t			wait_list_lock;
+	spinlock_t			ts_list_lock;
+	ktime_t				timestamp;
+	u32				interrupt_id;
+};
+
+/**
+ * struct timestamp_reg_free_node - holds the timestamp registration free objects node
+ * @free_objects_node: node in the list free_obj_jobs
+ * @cq_cb: pointer to cq command buffer to be freed
+ * @buf: pointer to timestamp buffer to be freed
+ * @in_use: indicates whether the node still in use in workqueue thread.
+ * @dynamic_alloc: indicates whether the node was allocated dynamically in the interrupt handler
+ */
+struct timestamp_reg_free_node {
+	struct list_head	free_objects_node;
+	struct hl_cb		*cq_cb;
+	struct hl_mmap_mem_buf	*buf;
+	atomic_t		in_use;
+	u8			dynamic_alloc;
+};
+
+/* struct timestamp_reg_work_obj - holds the timestamp registration free objects job
+ * the job will be to pass over the free_obj_jobs list and put refcount to objects
+ * in each node of the list
+ * @free_obj: workqueue object to free timestamp registration node objects
+ * @hdev: pointer to the device structure
+ * @free_obj_head: list of free jobs nodes (node type timestamp_reg_free_node)
+ * @dynamic_alloc_free_obj_head: list of free jobs nodes which were dynamically allocated in the
+ *                               interrupt handler.
+ */
+struct timestamp_reg_work_obj {
+	struct work_struct	free_obj;
+	struct hl_device	*hdev;
+	struct list_head	*free_obj_head;
+	struct list_head	*dynamic_alloc_free_obj_head;
+};
+
+/* struct timestamp_reg_info - holds the timestamp registration related data.
+ * @buf: pointer to the timestamp buffer which include both user/kernel buffers.
+ *       relevant only when doing timestamps records registration.
+ * @cq_cb: pointer to CQ counter CB.
+ * @interrupt: interrupt that the node hanged on it's wait list.
+ * @timestamp_kernel_addr: timestamp handle address, where to set timestamp
+ *                         relevant only when doing timestamps records
+ *                         registration.
+ * @in_use: indicates if the node already in use. relevant only when doing
+ *          timestamps records registration, since in this case the driver
+ *          will have it's own buffer which serve as a records pool instead of
+ *          allocating records dynamically.
+ */
+struct timestamp_reg_info {
+	struct hl_mmap_mem_buf		*buf;
+	struct hl_cb			*cq_cb;
+	struct hl_user_interrupt	*interrupt;
+	u64				*timestamp_kernel_addr;
+	bool				in_use;
+};
+
+/**
+ * struct hl_user_pending_interrupt - holds a context to a user thread
+ *                                    pending on an interrupt
+ * @ts_reg_info: holds the timestamps registration nodes info
+ * @list_node: node in the list of user threads pending on an interrupt or timestamp
+ * @fence: hl fence object for interrupt completion
+ * @cq_target_value: CQ target value
+ * @cq_kernel_addr: CQ kernel address, to be used in the cq interrupt
+ *                  handler for target value comparison
+ */
+struct hl_user_pending_interrupt {
+	struct timestamp_reg_info	ts_reg_info;
+	struct list_head		list_node;
+	struct hl_fence			fence;
+	u64				cq_target_value;
+	u64				*cq_kernel_addr;
+};
+
+/**
+ * struct hl_eq - describes the event queue (single one per device)
+ * @hdev: pointer to the device structure
+ * @kernel_address: holds the queue's kernel virtual address
+ * @bus_address: holds the queue's DMA address
+ * @size: the event queue size
+ * @ci: ci inside the queue
+ * @prev_eqe_index: the index of the previous event queue entry. The index of
+ *                  the current entry's index must be +1 of the previous one.
+ * @check_eqe_index: do we need to check the index of the current entry vs. the
+ *                   previous one. This is for backward compatibility with older
+ *                   firmwares
+ */
+struct hl_eq {
+	struct hl_device	*hdev;
+	void			*kernel_address;
+	dma_addr_t		bus_address;
+	u32			size;
+	u32			ci;
+	u32			prev_eqe_index;
+	bool			check_eqe_index;
+};
+
+/**
+ * struct hl_dec - describes a decoder sw instance.
+ * @hdev: pointer to the device structure.
+ * @abnrm_intr_work: workqueue work item to run when decoder generates an error interrupt.
+ * @core_id: ID of the decoder.
+ * @base_addr: base address of the decoder.
+ */
+struct hl_dec {
+	struct hl_device	*hdev;
+	struct work_struct	abnrm_intr_work;
+	u32			core_id;
+	u32			base_addr;
+};
+
+/**
+ * enum hl_asic_type - supported ASIC types.
+ * @ASIC_INVALID: Invalid ASIC type.
+ * @ASIC_GOYA: Goya device (HL-1000).
+ * @ASIC_GAUDI: Gaudi device (HL-2000).
+ * @ASIC_GAUDI_SEC: Gaudi secured device (HL-2000).
+ * @ASIC_GAUDI2: Gaudi2 device.
+ * @ASIC_GAUDI2B: Gaudi2B device.
+ * @ASIC_GAUDI2C: Gaudi2C device.
+ * @ASIC_GAUDI2D: Gaudi2D device.
+ */
+enum hl_asic_type {
+	ASIC_INVALID,
+
+	ASIC_GOYA,
+	ASIC_GAUDI,
+	ASIC_GAUDI_SEC,
+	ASIC_GAUDI2,
+	ASIC_GAUDI2B,
+	ASIC_GAUDI2C,
+	ASIC_GAUDI2D,
+};
+
+struct hl_cs_parser;
+
+/**
+ * enum hl_pm_mng_profile - power management profile.
+ * @PM_AUTO: internal clock is set by the Linux driver.
+ * @PM_MANUAL: internal clock is set by the user.
+ * @PM_LAST: last power management type.
+ */
+enum hl_pm_mng_profile {
+	PM_AUTO = 1,
+	PM_MANUAL,
+	PM_LAST
+};
+
+/**
+ * enum hl_pll_frequency - PLL frequency.
+ * @PLL_HIGH: high frequency.
+ * @PLL_LOW: low frequency.
+ * @PLL_LAST: last frequency values that were configured by the user.
+ */
+enum hl_pll_frequency {
+	PLL_HIGH = 1,
+	PLL_LOW,
+	PLL_LAST
+};
+
+#define PLL_REF_CLK 50
+
+enum div_select_defs {
+	DIV_SEL_REF_CLK = 0,
+	DIV_SEL_PLL_CLK = 1,
+	DIV_SEL_DIVIDED_REF = 2,
+	DIV_SEL_DIVIDED_PLL = 3,
+};
+
+enum debugfs_access_type {
+	DEBUGFS_READ8,
+	DEBUGFS_WRITE8,
+	DEBUGFS_READ32,
+	DEBUGFS_WRITE32,
+	DEBUGFS_READ64,
+	DEBUGFS_WRITE64,
+};
+
+enum pci_region {
+	PCI_REGION_CFG,
+	PCI_REGION_SRAM,
+	PCI_REGION_DRAM,
+	PCI_REGION_SP_SRAM,
+	PCI_REGION_NUMBER,
+};
+
+/**
+ * struct pci_mem_region - describe memory region in a PCI bar
+ * @region_base: region base address
+ * @region_size: region size
+ * @bar_size: size of the BAR
+ * @offset_in_bar: region offset into the bar
+ * @bar_id: bar ID of the region
+ * @used: if used 1, otherwise 0
+ */
+struct pci_mem_region {
+	u64 region_base;
+	u64 region_size;
+	u64 bar_size;
+	u64 offset_in_bar;
+	u8 bar_id;
+	u8 used;
+};
+
+/**
+ * struct static_fw_load_mgr - static FW load manager
+ * @preboot_version_max_off: max offset to preboot version
+ * @boot_fit_version_max_off: max offset to boot fit version
+ * @kmd_msg_to_cpu_reg: register address for KDM->CPU messages
+ * @cpu_cmd_status_to_host_reg: register address for CPU command status response
+ * @cpu_boot_status_reg: boot status register
+ * @cpu_boot_dev_status0_reg: boot device status register 0
+ * @cpu_boot_dev_status1_reg: boot device status register 1
+ * @boot_err0_reg: boot error register 0
+ * @boot_err1_reg: boot error register 1
+ * @preboot_version_offset_reg: SRAM offset to preboot version register
+ * @boot_fit_version_offset_reg: SRAM offset to boot fit version register
+ * @sram_offset_mask: mask for getting offset into the SRAM
+ * @cpu_reset_wait_msec: used when setting WFE via kmd_msg_to_cpu_reg
+ */
+struct static_fw_load_mgr {
+	u64 preboot_version_max_off;
+	u64 boot_fit_version_max_off;
+	u32 kmd_msg_to_cpu_reg;
+	u32 cpu_cmd_status_to_host_reg;
+	u32 cpu_boot_status_reg;
+	u32 cpu_boot_dev_status0_reg;
+	u32 cpu_boot_dev_status1_reg;
+	u32 boot_err0_reg;
+	u32 boot_err1_reg;
+	u32 preboot_version_offset_reg;
+	u32 boot_fit_version_offset_reg;
+	u32 sram_offset_mask;
+	u32 cpu_reset_wait_msec;
+};
+
+/**
+ * struct fw_response - FW response to LKD command
+ * @ram_offset: descriptor offset into the RAM
+ * @ram_type: RAM type containing the descriptor (SRAM/DRAM)
+ * @status: command status
+ */
+struct fw_response {
+	u32 ram_offset;
+	u8 ram_type;
+	u8 status;
+};
+
+/**
+ * struct dynamic_fw_load_mgr - dynamic FW load manager
+ * @response: FW to LKD response
+ * @comm_desc: the communication descriptor with FW
+ * @image_region: region to copy the FW image to
+ * @fw_image_size: size of FW image to load
+ * @wait_for_bl_timeout: timeout for waiting for boot loader to respond
+ * @fw_desc_valid: true if FW descriptor has been validated and hence the data can be used
+ */
+struct dynamic_fw_load_mgr {
+	struct fw_response response;
+	struct lkd_fw_comms_desc comm_desc;
+	struct pci_mem_region *image_region;
+	size_t fw_image_size;
+	u32 wait_for_bl_timeout;
+	bool fw_desc_valid;
+};
+
+/**
+ * struct pre_fw_load_props - needed properties for pre-FW load
+ * @cpu_boot_status_reg: cpu_boot_status register address
+ * @sts_boot_dev_sts0_reg: sts_boot_dev_sts0 register address
+ * @sts_boot_dev_sts1_reg: sts_boot_dev_sts1 register address
+ * @boot_err0_reg: boot_err0 register address
+ * @boot_err1_reg: boot_err1 register address
+ * @wait_for_preboot_timeout: timeout to poll for preboot ready
+ * @wait_for_preboot_extended_timeout: timeout to pull for preboot ready in case where we know
+ *		preboot needs longer time.
+ */
+struct pre_fw_load_props {
+	u32 cpu_boot_status_reg;
+	u32 sts_boot_dev_sts0_reg;
+	u32 sts_boot_dev_sts1_reg;
+	u32 boot_err0_reg;
+	u32 boot_err1_reg;
+	u32 wait_for_preboot_timeout;
+	u32 wait_for_preboot_extended_timeout;
+};
+
+/**
+ * struct fw_image_props - properties of FW image
+ * @image_name: name of the image
+ * @src_off: offset in src FW to copy from
+ * @copy_size: amount of bytes to copy (0 to copy the whole binary)
+ */
+struct fw_image_props {
+	char *image_name;
+	u32 src_off;
+	u32 copy_size;
+};
+
+/**
+ * struct fw_load_mgr - manager FW loading process
+ * @dynamic_loader: specific structure for dynamic load
+ * @static_loader: specific structure for static load
+ * @pre_fw_load_props: parameter for pre FW load
+ * @boot_fit_img: boot fit image properties
+ * @linux_img: linux image properties
+ * @cpu_timeout: CPU response timeout in usec
+ * @boot_fit_timeout: Boot fit load timeout in usec
+ * @skip_bmc: should BMC be skipped
+ * @sram_bar_id: SRAM bar ID
+ * @dram_bar_id: DRAM bar ID
+ * @fw_comp_loaded: bitmask of loaded FW components. set bit meaning loaded
+ *                  component. values are set according to enum hl_fw_types.
+ */
+struct fw_load_mgr {
+	union {
+		struct dynamic_fw_load_mgr dynamic_loader;
+		struct static_fw_load_mgr static_loader;
+	};
+	struct pre_fw_load_props pre_fw_load;
+	struct fw_image_props boot_fit_img;
+	struct fw_image_props linux_img;
+	u32 cpu_timeout;
+	u32 boot_fit_timeout;
+	u8 skip_bmc;
+	u8 sram_bar_id;
+	u8 dram_bar_id;
+	u8 fw_comp_loaded;
+};
+
+struct hl_cs;
+
+/**
+ * struct engines_data - asic engines data
+ * @buf: buffer for engines data in ascii
+ * @actual_size: actual size of data that was written by the driver to the allocated buffer
+ * @allocated_buf_size: total size of allocated buffer
+ */
+struct engines_data {
+	char *buf;
+	int actual_size;
+	u32 allocated_buf_size;
+};
+
+/**
+ * struct hl_asic_funcs - ASIC specific functions that are can be called from
+ *                        common code.
+ * @early_init: sets up early driver state (pre sw_init), doesn't configure H/W.
+ * @early_fini: tears down what was done in early_init.
+ * @late_init: sets up late driver/hw state (post hw_init) - Optional.
+ * @late_fini: tears down what was done in late_init (pre hw_fini) - Optional.
+ * @sw_init: sets up driver state, does not configure H/W.
+ * @sw_fini: tears down driver state, does not configure H/W.
+ * @hw_init: sets up the H/W state.
+ * @hw_fini: tears down the H/W state.
+ * @halt_engines: halt engines, needed for reset sequence. This also disables
+ *                interrupts from the device. Should be called before
+ *                hw_fini and before CS rollback.
+ * @suspend: handles IP specific H/W or SW changes for suspend.
+ * @resume: handles IP specific H/W or SW changes for resume.
+ * @mmap: maps a memory.
+ * @ring_doorbell: increment PI on a given QMAN.
+ * @pqe_write: Write the PQ entry to the PQ. This is ASIC-specific
+ *             function because the PQs are located in different memory areas
+ *             per ASIC (SRAM, DRAM, Host memory) and therefore, the method of
+ *             writing the PQE must match the destination memory area
+ *             properties.
+ * @asic_dma_alloc_coherent: Allocate coherent DMA memory by calling
+ *                           dma_alloc_coherent(). This is ASIC function because
+ *                           its implementation is not trivial when the driver
+ *                           is loaded in simulation mode (not upstreamed).
+ * @asic_dma_free_coherent:  Free coherent DMA memory by calling
+ *                           dma_free_coherent(). This is ASIC function because
+ *                           its implementation is not trivial when the driver
+ *                           is loaded in simulation mode (not upstreamed).
+ * @scrub_device_mem: Scrub the entire SRAM and DRAM.
+ * @scrub_device_dram: Scrub the dram memory of the device.
+ * @get_int_queue_base: get the internal queue base address.
+ * @test_queues: run simple test on all queues for sanity check.
+ * @asic_dma_pool_zalloc: small DMA allocation of coherent memory from DMA pool.
+ *                        size of allocation is HL_DMA_POOL_BLK_SIZE.
+ * @asic_dma_pool_free: free small DMA allocation from pool.
+ * @cpu_accessible_dma_pool_alloc: allocate CPU PQ packet from DMA pool.
+ * @cpu_accessible_dma_pool_free: free CPU PQ packet from DMA pool.
+ * @dma_unmap_sgtable: DMA unmap scatter-gather table.
+ * @dma_map_sgtable: DMA map scatter-gather table.
+ * @cs_parser: parse Command Submission.
+ * @add_end_of_cb_packets: Add packets to the end of CB, if device requires it.
+ * @update_eq_ci: update event queue CI.
+ * @context_switch: called upon ASID context switch.
+ * @restore_phase_topology: clear all SOBs amd MONs.
+ * @debugfs_read_dma: debug interface for reading up to 2MB from the device's
+ *                    internal memory via DMA engine.
+ * @add_device_attr: add ASIC specific device attributes.
+ * @handle_eqe: handle event queue entry (IRQ) from CPU-CP.
+ * @get_events_stat: retrieve event queue entries histogram.
+ * @read_pte: read MMU page table entry from DRAM.
+ * @write_pte: write MMU page table entry to DRAM.
+ * @mmu_invalidate_cache: flush MMU STLB host/DRAM cache, either with soft
+ *                        (L1 only) or hard (L0 & L1) flush.
+ * @mmu_invalidate_cache_range: flush specific MMU STLB cache lines with ASID-VA-size mask.
+ * @mmu_prefetch_cache_range: pre-fetch specific MMU STLB cache lines with ASID-VA-size mask.
+ * @send_heartbeat: send is-alive packet to CPU-CP and verify response.
+ * @debug_coresight: perform certain actions on Coresight for debugging.
+ * @is_device_idle: return true if device is idle, false otherwise.
+ * @compute_reset_late_init: perform certain actions needed after a compute reset
+ * @hw_queues_lock: acquire H/W queues lock.
+ * @hw_queues_unlock: release H/W queues lock.
+ * @get_pci_id: retrieve PCI ID.
+ * @get_eeprom_data: retrieve EEPROM data from F/W.
+ * @get_monitor_dump: retrieve monitor registers dump from F/W.
+ * @send_cpu_message: send message to F/W. If the message is timedout, the
+ *                    driver will eventually reset the device. The timeout can
+ *                    be determined by the calling function or it can be 0 and
+ *                    then the timeout is the default timeout for the specific
+ *                    ASIC
+ * @get_hw_state: retrieve the H/W state
+ * @pci_bars_map: Map PCI BARs.
+ * @init_iatu: Initialize the iATU unit inside the PCI controller.
+ * @rreg: Read a register. Needed for simulator support.
+ * @wreg: Write a register. Needed for simulator support.
+ * @halt_coresight: stop the ETF and ETR traces.
+ * @ctx_init: context dependent initialization.
+ * @ctx_fini: context dependent cleanup.
+ * @pre_schedule_cs: Perform pre-CS-scheduling operations.
+ * @get_queue_id_for_cq: Get the H/W queue id related to the given CQ index.
+ * @load_firmware_to_device: load the firmware to the device's memory
+ * @load_boot_fit_to_device: load boot fit to device's memory
+ * @get_signal_cb_size: Get signal CB size.
+ * @get_wait_cb_size: Get wait CB size.
+ * @gen_signal_cb: Generate a signal CB.
+ * @gen_wait_cb: Generate a wait CB.
+ * @reset_sob: Reset a SOB.
+ * @reset_sob_group: Reset SOB group
+ * @get_device_time: Get the device time.
+ * @pb_print_security_errors: print security errors according block and cause
+ * @collective_wait_init_cs: Generate collective master/slave packets
+ *                           and place them in the relevant cs jobs
+ * @collective_wait_create_jobs: allocate collective wait cs jobs
+ * @get_dec_base_addr: get the base address of a given decoder.
+ * @scramble_addr: Routine to scramble the address prior of mapping it
+ *                 in the MMU.
+ * @descramble_addr: Routine to de-scramble the address prior of
+ *                   showing it to users.
+ * @ack_protection_bits_errors: ack and dump all security violations
+ * @get_hw_block_id: retrieve a HW block id to be used by the user to mmap it.
+ *                   also returns the size of the block if caller supplies
+ *                   a valid pointer for it
+ * @hw_block_mmap: mmap a HW block with a given id.
+ * @enable_events_from_fw: send interrupt to firmware to notify them the
+ *                         driver is ready to receive asynchronous events. This
+ *                         function should be called during the first init and
+ *                         after every hard-reset of the device
+ * @ack_mmu_errors: check and ack mmu errors, page fault, access violation.
+ * @get_msi_info: Retrieve asic-specific MSI ID of the f/w async event
+ * @map_pll_idx_to_fw_idx: convert driver specific per asic PLL index to
+ *                         generic f/w compatible PLL Indexes
+ * @init_firmware_preload_params: initialize pre FW-load parameters.
+ * @init_firmware_loader: initialize data for FW loader.
+ * @init_cpu_scrambler_dram: Enable CPU specific DRAM scrambling
+ * @state_dump_init: initialize constants required for state dump
+ * @get_sob_addr: get SOB base address offset.
+ * @set_pci_memory_regions: setting properties of PCI memory regions
+ * @get_stream_master_qid_arr: get pointer to stream masters QID array
+ * @check_if_razwi_happened: check if there was a razwi due to RR violation.
+ * @access_dev_mem: access device memory
+ * @set_dram_bar_base: set the base of the DRAM BAR
+ * @set_engine_cores: set a config command to engine cores
+ * @set_engines: set a config command to user engines
+ * @send_device_activity: indication to FW about device availability
+ * @set_dram_properties: set DRAM related properties.
+ * @set_binning_masks: set binning/enable masks for all relevant components.
+ */
+struct hl_asic_funcs {
+	int (*early_init)(struct hl_device *hdev);
+	int (*early_fini)(struct hl_device *hdev);
+	int (*late_init)(struct hl_device *hdev);
+	void (*late_fini)(struct hl_device *hdev);
+	int (*sw_init)(struct hl_device *hdev);
+	int (*sw_fini)(struct hl_device *hdev);
+	int (*hw_init)(struct hl_device *hdev);
+	int (*hw_fini)(struct hl_device *hdev, bool hard_reset, bool fw_reset);
+	void (*halt_engines)(struct hl_device *hdev, bool hard_reset, bool fw_reset);
+	int (*suspend)(struct hl_device *hdev);
+	int (*resume)(struct hl_device *hdev);
+	int (*mmap)(struct hl_device *hdev, struct vm_area_struct *vma,
+			void *cpu_addr, dma_addr_t dma_addr, size_t size);
+	void (*ring_doorbell)(struct hl_device *hdev, u32 hw_queue_id, u32 pi);
+	void (*pqe_write)(struct hl_device *hdev, __le64 *pqe,
+			struct hl_bd *bd);
+	void* (*asic_dma_alloc_coherent)(struct hl_device *hdev, size_t size,
+					dma_addr_t *dma_handle, gfp_t flag);
+	void (*asic_dma_free_coherent)(struct hl_device *hdev, size_t size,
+					void *cpu_addr, dma_addr_t dma_handle);
+	int (*scrub_device_mem)(struct hl_device *hdev);
+	int (*scrub_device_dram)(struct hl_device *hdev, u64 val);
+	void* (*get_int_queue_base)(struct hl_device *hdev, u32 queue_id,
+				dma_addr_t *dma_handle, u16 *queue_len);
+	int (*test_queues)(struct hl_device *hdev);
+	void* (*asic_dma_pool_zalloc)(struct hl_device *hdev, size_t size,
+				gfp_t mem_flags, dma_addr_t *dma_handle);
+	void (*asic_dma_pool_free)(struct hl_device *hdev, void *vaddr,
+				dma_addr_t dma_addr);
+	void* (*cpu_accessible_dma_pool_alloc)(struct hl_device *hdev,
+				size_t size, dma_addr_t *dma_handle);
+	void (*cpu_accessible_dma_pool_free)(struct hl_device *hdev,
+				size_t size, void *vaddr);
+	void (*dma_unmap_sgtable)(struct hl_device *hdev, struct sg_table *sgt,
+				enum dma_data_direction dir);
+	int (*dma_map_sgtable)(struct hl_device *hdev, struct sg_table *sgt,
+				enum dma_data_direction dir);
+	int (*cs_parser)(struct hl_device *hdev, struct hl_cs_parser *parser);
+	void (*add_end_of_cb_packets)(struct hl_device *hdev,
+					void *kernel_address, u32 len,
+					u32 original_len,
+					u64 cq_addr, u32 cq_val, u32 msix_num,
+					bool eb);
+	void (*update_eq_ci)(struct hl_device *hdev, u32 val);
+	int (*context_switch)(struct hl_device *hdev, u32 asid);
+	void (*restore_phase_topology)(struct hl_device *hdev);
+	int (*debugfs_read_dma)(struct hl_device *hdev, u64 addr, u32 size,
+				void *blob_addr);
+	void (*add_device_attr)(struct hl_device *hdev, struct attribute_group *dev_clk_attr_grp,
+				struct attribute_group *dev_vrm_attr_grp);
+	void (*handle_eqe)(struct hl_device *hdev,
+				struct hl_eq_entry *eq_entry);
+	void* (*get_events_stat)(struct hl_device *hdev, bool aggregate,
+				u32 *size);
+	u64 (*read_pte)(struct hl_device *hdev, u64 addr);
+	void (*write_pte)(struct hl_device *hdev, u64 addr, u64 val);
+	int (*mmu_invalidate_cache)(struct hl_device *hdev, bool is_hard,
+					u32 flags);
+	int (*mmu_invalidate_cache_range)(struct hl_device *hdev, bool is_hard,
+				u32 flags, u32 asid, u64 va, u64 size);
+	int (*mmu_prefetch_cache_range)(struct hl_ctx *ctx, u32 flags, u32 asid, u64 va, u64 size);
+	int (*send_heartbeat)(struct hl_device *hdev);
+	int (*debug_coresight)(struct hl_device *hdev, struct hl_ctx *ctx, void *data);
+	bool (*is_device_idle)(struct hl_device *hdev, u64 *mask_arr, u8 mask_len,
+				struct engines_data *e);
+	int (*compute_reset_late_init)(struct hl_device *hdev);
+	void (*hw_queues_lock)(struct hl_device *hdev);
+	void (*hw_queues_unlock)(struct hl_device *hdev);
+	u32 (*get_pci_id)(struct hl_device *hdev);
+	int (*get_eeprom_data)(struct hl_device *hdev, void *data, size_t max_size);
+	int (*get_monitor_dump)(struct hl_device *hdev, void *data);
+	int (*send_cpu_message)(struct hl_device *hdev, u32 *msg,
+				u16 len, u32 timeout, u64 *result);
+	int (*pci_bars_map)(struct hl_device *hdev);
+	int (*init_iatu)(struct hl_device *hdev);
+	u32 (*rreg)(struct hl_device *hdev, u32 reg);
+	void (*wreg)(struct hl_device *hdev, u32 reg, u32 val);
+	void (*halt_coresight)(struct hl_device *hdev, struct hl_ctx *ctx);
+	int (*ctx_init)(struct hl_ctx *ctx);
+	void (*ctx_fini)(struct hl_ctx *ctx);
+	int (*pre_schedule_cs)(struct hl_cs *cs);
+	u32 (*get_queue_id_for_cq)(struct hl_device *hdev, u32 cq_idx);
+	int (*load_firmware_to_device)(struct hl_device *hdev);
+	int (*load_boot_fit_to_device)(struct hl_device *hdev);
+	u32 (*get_signal_cb_size)(struct hl_device *hdev);
+	u32 (*get_wait_cb_size)(struct hl_device *hdev);
+	u32 (*gen_signal_cb)(struct hl_device *hdev, void *data, u16 sob_id,
+			u32 size, bool eb);
+	u32 (*gen_wait_cb)(struct hl_device *hdev,
+			struct hl_gen_wait_properties *prop);
+	void (*reset_sob)(struct hl_device *hdev, void *data);
+	void (*reset_sob_group)(struct hl_device *hdev, u16 sob_group);
+	u64 (*get_device_time)(struct hl_device *hdev);
+	void (*pb_print_security_errors)(struct hl_device *hdev,
+			u32 block_addr, u32 cause, u32 offended_addr);
+	int (*collective_wait_init_cs)(struct hl_cs *cs);
+	int (*collective_wait_create_jobs)(struct hl_device *hdev,
+			struct hl_ctx *ctx, struct hl_cs *cs,
+			u32 wait_queue_id, u32 collective_engine_id,
+			u32 encaps_signal_offset);
+	u32 (*get_dec_base_addr)(struct hl_device *hdev, u32 core_id);
+	u64 (*scramble_addr)(struct hl_device *hdev, u64 addr);
+	u64 (*descramble_addr)(struct hl_device *hdev, u64 addr);
+	void (*ack_protection_bits_errors)(struct hl_device *hdev);
+	int (*get_hw_block_id)(struct hl_device *hdev, u64 block_addr,
+				u32 *block_size, u32 *block_id);
+	int (*hw_block_mmap)(struct hl_device *hdev, struct vm_area_struct *vma,
+			u32 block_id, u32 block_size);
+	void (*enable_events_from_fw)(struct hl_device *hdev);
+	int (*ack_mmu_errors)(struct hl_device *hdev, u64 mmu_cap_mask);
+	void (*get_msi_info)(__le32 *table);
+	int (*map_pll_idx_to_fw_idx)(u32 pll_idx);
+	void (*init_firmware_preload_params)(struct hl_device *hdev);
+	void (*init_firmware_loader)(struct hl_device *hdev);
+	void (*init_cpu_scrambler_dram)(struct hl_device *hdev);
+	void (*state_dump_init)(struct hl_device *hdev);
+	u32 (*get_sob_addr)(struct hl_device *hdev, u32 sob_id);
+	void (*set_pci_memory_regions)(struct hl_device *hdev);
+	u32* (*get_stream_master_qid_arr)(void);
+	void (*check_if_razwi_happened)(struct hl_device *hdev);
+	int (*mmu_get_real_page_size)(struct hl_device *hdev, struct hl_mmu_properties *mmu_prop,
+					u32 page_size, u32 *real_page_size, bool is_dram_addr);
+	int (*access_dev_mem)(struct hl_device *hdev, enum pci_region region_type,
+				u64 addr, u64 *val, enum debugfs_access_type acc_type);
+	u64 (*set_dram_bar_base)(struct hl_device *hdev, u64 addr);
+	int (*set_engine_cores)(struct hl_device *hdev, u32 *core_ids,
+					u32 num_cores, u32 core_command);
+	int (*set_engines)(struct hl_device *hdev, u32 *engine_ids,
+					u32 num_engines, u32 engine_command);
+	int (*send_device_activity)(struct hl_device *hdev, bool open);
+	int (*set_dram_properties)(struct hl_device *hdev);
+	int (*set_binning_masks)(struct hl_device *hdev);
+};
+
+
+/*
+ * CONTEXTS
+ */
+
+#define HL_KERNEL_ASID_ID	0
+
+/**
+ * enum hl_va_range_type - virtual address range type.
+ * @HL_VA_RANGE_TYPE_HOST: range type of host pages
+ * @HL_VA_RANGE_TYPE_HOST_HUGE: range type of host huge pages
+ * @HL_VA_RANGE_TYPE_DRAM: range type of dram pages
+ */
+enum hl_va_range_type {
+	HL_VA_RANGE_TYPE_HOST,
+	HL_VA_RANGE_TYPE_HOST_HUGE,
+	HL_VA_RANGE_TYPE_DRAM,
+	HL_VA_RANGE_TYPE_MAX
+};
+
+/**
+ * struct hl_va_range - virtual addresses range.
+ * @lock: protects the virtual addresses list.
+ * @list: list of virtual addresses blocks available for mappings.
+ * @start_addr: range start address.
+ * @end_addr: range end address.
+ * @page_size: page size of this va range.
+ */
+struct hl_va_range {
+	struct mutex		lock;
+	struct list_head	list;
+	u64			start_addr;
+	u64			end_addr;
+	u32			page_size;
+};
+
+/**
+ * struct hl_cs_counters_atomic - command submission counters
+ * @out_of_mem_drop_cnt: dropped due to memory allocation issue
+ * @parsing_drop_cnt: dropped due to error in packet parsing
+ * @queue_full_drop_cnt: dropped due to queue full
+ * @device_in_reset_drop_cnt: dropped due to device in reset
+ * @max_cs_in_flight_drop_cnt: dropped due to maximum CS in-flight
+ * @validation_drop_cnt: dropped due to error in validation
+ */
+struct hl_cs_counters_atomic {
+	atomic64_t out_of_mem_drop_cnt;
+	atomic64_t parsing_drop_cnt;
+	atomic64_t queue_full_drop_cnt;
+	atomic64_t device_in_reset_drop_cnt;
+	atomic64_t max_cs_in_flight_drop_cnt;
+	atomic64_t validation_drop_cnt;
+};
+
+/**
+ * struct hl_dmabuf_priv - a dma-buf private object.
+ * @dmabuf: pointer to dma-buf object.
+ * @ctx: pointer to the dma-buf owner's context.
+ * @phys_pg_pack: pointer to physical page pack if the dma-buf was exported
+ *                where virtual memory is supported.
+ * @memhash_hnode: pointer to the memhash node. this object holds the export count.
+ * @offset: the offset into the buffer from which the memory is exported.
+ *          Relevant only if virtual memory is supported and phys_pg_pack is being used.
+ * device_phys_addr: physical address of the device's memory. Relevant only
+ *                   if phys_pg_pack is NULL (dma-buf was exported from address).
+ *                   The total size can be taken from the dmabuf object.
+ */
+struct hl_dmabuf_priv {
+	struct dma_buf			*dmabuf;
+	struct hl_ctx			*ctx;
+	struct hl_vm_phys_pg_pack	*phys_pg_pack;
+	struct hl_vm_hash_node		*memhash_hnode;
+	u64				offset;
+	u64				device_phys_addr;
+};
+
+#define HL_CS_OUTCOME_HISTORY_LEN 256
+
+/**
+ * struct hl_cs_outcome - represents a single completed CS outcome
+ * @list_link: link to either container's used list or free list
+ * @map_link: list to the container hash map
+ * @ts: completion ts
+ * @seq: the original cs sequence
+ * @error: error code cs completed with, if any
+ */
+struct hl_cs_outcome {
+	struct list_head list_link;
+	struct hlist_node map_link;
+	ktime_t ts;
+	u64 seq;
+	int error;
+};
+
+/**
+ * struct hl_cs_outcome_store - represents a limited store of completed CS outcomes
+ * @outcome_map: index of completed CS searchable by sequence number
+ * @used_list: list of outcome objects currently in use
+ * @free_list: list of outcome objects currently not in use
+ * @nodes_pool: a static pool of pre-allocated outcome objects
+ * @db_lock: any operation on the store must take this lock
+ */
+struct hl_cs_outcome_store {
+	DECLARE_HASHTABLE(outcome_map, 8);
+	struct list_head used_list;
+	struct list_head free_list;
+	struct hl_cs_outcome nodes_pool[HL_CS_OUTCOME_HISTORY_LEN];
+	spinlock_t db_lock;
+};
+
+/**
+ * struct hl_ctx - user/kernel context.
+ * @mem_hash: holds mapping from virtual address to virtual memory area
+ *		descriptor (hl_vm_phys_pg_list or hl_userptr).
+ * @mmu_shadow_hash: holds a mapping from shadow address to pgt_info structure.
+ * @hr_mmu_phys_hash: if host-resident MMU is used, holds a mapping from
+ *                    MMU-hop-page physical address to its host-resident
+ *                    pgt_info structure.
+ * @hpriv: pointer to the private (Kernel Driver) data of the process (fd).
+ * @hdev: pointer to the device structure.
+ * @refcount: reference counter for the context. Context is released only when
+ *		this hits 0. It is incremented on CS and CS_WAIT.
+ * @cs_pending: array of hl fence objects representing pending CS.
+ * @outcome_store: storage data structure used to remember outcomes of completed
+ *                 command submissions for a long time after CS id wraparound.
+ * @va_range: holds available virtual addresses for host and dram mappings.
+ * @mem_hash_lock: protects the mem_hash.
+ * @hw_block_list_lock: protects the HW block memory list.
+ * @ts_reg_lock: timestamp registration ioctls lock.
+ * @debugfs_list: node in debugfs list of contexts.
+ * @hw_block_mem_list: list of HW block virtual mapped addresses.
+ * @cs_counters: context command submission counters.
+ * @cb_va_pool: device VA pool for command buffers which are mapped to the
+ *              device's MMU.
+ * @sig_mgr: encaps signals handle manager.
+ * @cb_va_pool_base: the base address for the device VA pool
+ * @cs_sequence: sequence number for CS. Value is assigned to a CS and passed
+ *			to user so user could inquire about CS. It is used as
+ *			index to cs_pending array.
+ * @dram_default_hops: array that holds all hops addresses needed for default
+ *                     DRAM mapping.
+ * @cs_lock: spinlock to protect cs_sequence.
+ * @dram_phys_mem: amount of used physical DRAM memory by this context.
+ * @thread_ctx_switch_token: token to prevent multiple threads of the same
+ *				context	from running the context switch phase.
+ *				Only a single thread should run it.
+ * @thread_ctx_switch_wait_token: token to prevent the threads that didn't run
+ *				the context switch phase from moving to their
+ *				execution phase before the context switch phase
+ *				has finished.
+ * @asid: context's unique address space ID in the device's MMU.
+ * @handle: context's opaque handle for user
+ */
+struct hl_ctx {
+	DECLARE_HASHTABLE(mem_hash, MEM_HASH_TABLE_BITS);
+	DECLARE_HASHTABLE(mmu_shadow_hash, MMU_HASH_TABLE_BITS);
+	DECLARE_HASHTABLE(hr_mmu_phys_hash, MMU_HASH_TABLE_BITS);
+	struct hl_fpriv			*hpriv;
+	struct hl_device		*hdev;
+	struct kref			refcount;
+	struct hl_fence			**cs_pending;
+	struct hl_cs_outcome_store	outcome_store;
+	struct hl_va_range		*va_range[HL_VA_RANGE_TYPE_MAX];
+	struct mutex			mem_hash_lock;
+	struct mutex			hw_block_list_lock;
+	struct mutex			ts_reg_lock;
+	struct list_head		debugfs_list;
+	struct list_head		hw_block_mem_list;
+	struct hl_cs_counters_atomic	cs_counters;
+	struct gen_pool			*cb_va_pool;
+	struct hl_encaps_signals_mgr	sig_mgr;
+	u64				cb_va_pool_base;
+	u64				cs_sequence;
+	u64				*dram_default_hops;
+	spinlock_t			cs_lock;
+	atomic64_t			dram_phys_mem;
+	atomic_t			thread_ctx_switch_token;
+	u32				thread_ctx_switch_wait_token;
+	u32				asid;
+	u32				handle;
+};
+
+/**
+ * struct hl_ctx_mgr - for handling multiple contexts.
+ * @lock: protects ctx_handles.
+ * @handles: idr to hold all ctx handles.
+ */
+struct hl_ctx_mgr {
+	struct mutex	lock;
+	struct idr	handles;
+};
+
+
+/*
+ * COMMAND SUBMISSIONS
+ */
+
+/**
+ * struct hl_userptr - memory mapping chunk information
+ * @vm_type: type of the VM.
+ * @job_node: linked-list node for hanging the object on the Job's list.
+ * @pages: pointer to struct page array
+ * @npages: size of @pages array
+ * @sgt: pointer to the scatter-gather table that holds the pages.
+ * @dir: for DMA unmapping, the direction must be supplied, so save it.
+ * @debugfs_list: node in debugfs list of command submissions.
+ * @pid: the pid of the user process owning the memory
+ * @addr: user-space virtual address of the start of the memory area.
+ * @size: size of the memory area to pin & map.
+ * @dma_mapped: true if the SG was mapped to DMA addresses, false otherwise.
+ */
+struct hl_userptr {
+	enum vm_type			vm_type; /* must be first */
+	struct list_head		job_node;
+	struct page			**pages;
+	unsigned int			npages;
+	struct sg_table			*sgt;
+	enum dma_data_direction		dir;
+	struct list_head		debugfs_list;
+	pid_t				pid;
+	u64				addr;
+	u64				size;
+	u8				dma_mapped;
+};
+
+/**
+ * struct hl_cs - command submission.
+ * @jobs_in_queue_cnt: per each queue, maintain counter of submitted jobs.
+ * @ctx: the context this CS belongs to.
+ * @job_list: list of the CS's jobs in the various queues.
+ * @job_lock: spinlock for the CS's jobs list. Needed for free_job.
+ * @refcount: reference counter for usage of the CS.
+ * @fence: pointer to the fence object of this CS.
+ * @signal_fence: pointer to the fence object of the signal CS (used by wait
+ *                CS only).
+ * @finish_work: workqueue object to run when CS is completed by H/W.
+ * @work_tdr: delayed work node for TDR.
+ * @mirror_node : node in device mirror list of command submissions.
+ * @staged_cs_node: node in the staged cs list.
+ * @debugfs_list: node in debugfs list of command submissions.
+ * @encaps_sig_hdl: holds the encaps signals handle.
+ * @sequence: the sequence number of this CS.
+ * @staged_sequence: the sequence of the staged submission this CS is part of,
+ *                   relevant only if staged_cs is set.
+ * @timeout_jiffies: cs timeout in jiffies.
+ * @submission_time_jiffies: submission time of the cs
+ * @type: CS_TYPE_*.
+ * @jobs_cnt: counter of submitted jobs on all queues.
+ * @encaps_sig_hdl_id: encaps signals handle id, set for the first staged cs.
+ * @completion_timestamp: timestamp of the last completed cs job.
+ * @sob_addr_offset: sob offset from the configuration base address.
+ * @initial_sob_count: count of completed signals in SOB before current submission of signal or
+ *                     cs with encaps signals.
+ * @submitted: true if CS was submitted to H/W.
+ * @completed: true if CS was completed by device.
+ * @timedout : true if CS was timedout.
+ * @tdr_active: true if TDR was activated for this CS (to prevent
+ *		double TDR activation).
+ * @aborted: true if CS was aborted due to some device error.
+ * @timestamp: true if a timestamp must be captured upon completion.
+ * @staged_last: true if this is the last staged CS and needs completion.
+ * @staged_first: true if this is the first staged CS and we need to receive
+ *                timeout for this CS.
+ * @staged_cs: true if this CS is part of a staged submission.
+ * @skip_reset_on_timeout: true if we shall not reset the device in case
+ *                         timeout occurs (debug scenario).
+ * @encaps_signals: true if this CS has encaps reserved signals.
+ */
+struct hl_cs {
+	u16			*jobs_in_queue_cnt;
+	struct hl_ctx		*ctx;
+	struct list_head	job_list;
+	spinlock_t		job_lock;
+	struct kref		refcount;
+	struct hl_fence		*fence;
+	struct hl_fence		*signal_fence;
+	struct work_struct	finish_work;
+	struct delayed_work	work_tdr;
+	struct list_head	mirror_node;
+	struct list_head	staged_cs_node;
+	struct list_head	debugfs_list;
+	struct hl_cs_encaps_sig_handle *encaps_sig_hdl;
+	ktime_t			completion_timestamp;
+	u64			sequence;
+	u64			staged_sequence;
+	u64			timeout_jiffies;
+	u64			submission_time_jiffies;
+	enum hl_cs_type		type;
+	u32			jobs_cnt;
+	u32			encaps_sig_hdl_id;
+	u32			sob_addr_offset;
+	u16			initial_sob_count;
+	u8			submitted;
+	u8			completed;
+	u8			timedout;
+	u8			tdr_active;
+	u8			aborted;
+	u8			timestamp;
+	u8			staged_last;
+	u8			staged_first;
+	u8			staged_cs;
+	u8			skip_reset_on_timeout;
+	u8			encaps_signals;
+};
+
+/**
+ * struct hl_cs_job - command submission job.
+ * @cs_node: the node to hang on the CS jobs list.
+ * @cs: the CS this job belongs to.
+ * @user_cb: the CB we got from the user.
+ * @patched_cb: in case of patching, this is internal CB which is submitted on
+ *		the queue instead of the CB we got from the IOCTL.
+ * @finish_work: workqueue object to run when job is completed.
+ * @userptr_list: linked-list of userptr mappings that belong to this job and
+ *			wait for completion.
+ * @debugfs_list: node in debugfs list of command submission jobs.
+ * @refcount: reference counter for usage of the CS job.
+ * @queue_type: the type of the H/W queue this job is submitted to.
+ * @timestamp: timestamp upon job completion
+ * @id: the id of this job inside a CS.
+ * @hw_queue_id: the id of the H/W queue this job is submitted to.
+ * @user_cb_size: the actual size of the CB we got from the user.
+ * @job_cb_size: the actual size of the CB that we put on the queue.
+ * @encaps_sig_wait_offset: encapsulated signals offset, which allow user
+ *                          to wait on part of the reserved signals.
+ * @is_kernel_allocated_cb: true if the CB handle we got from the user holds a
+ *                          handle to a kernel-allocated CB object, false
+ *                          otherwise (SRAM/DRAM/host address).
+ * @contains_dma_pkt: whether the JOB contains at least one DMA packet. This
+ *                    info is needed later, when adding the 2xMSG_PROT at the
+ *                    end of the JOB, to know which barriers to put in the
+ *                    MSG_PROT packets. Relevant only for GAUDI as GOYA doesn't
+ *                    have streams so the engine can't be busy by another
+ *                    stream.
+ */
+struct hl_cs_job {
+	struct list_head	cs_node;
+	struct hl_cs		*cs;
+	struct hl_cb		*user_cb;
+	struct hl_cb		*patched_cb;
+	struct work_struct	finish_work;
+	struct list_head	userptr_list;
+	struct list_head	debugfs_list;
+	struct kref		refcount;
+	enum hl_queue_type	queue_type;
+	ktime_t			timestamp;
+	u32			id;
+	u32			hw_queue_id;
+	u32			user_cb_size;
+	u32			job_cb_size;
+	u32			encaps_sig_wait_offset;
+	u8			is_kernel_allocated_cb;
+	u8			contains_dma_pkt;
+};
+
+/**
+ * struct hl_cs_parser - command submission parser properties.
+ * @user_cb: the CB we got from the user.
+ * @patched_cb: in case of patching, this is internal CB which is submitted on
+ *		the queue instead of the CB we got from the IOCTL.
+ * @job_userptr_list: linked-list of userptr mappings that belong to the related
+ *			job and wait for completion.
+ * @cs_sequence: the sequence number of the related CS.
+ * @queue_type: the type of the H/W queue this job is submitted to.
+ * @ctx_id: the ID of the context the related CS belongs to.
+ * @hw_queue_id: the id of the H/W queue this job is submitted to.
+ * @user_cb_size: the actual size of the CB we got from the user.
+ * @patched_cb_size: the size of the CB after parsing.
+ * @job_id: the id of the related job inside the related CS.
+ * @is_kernel_allocated_cb: true if the CB handle we got from the user holds a
+ *                          handle to a kernel-allocated CB object, false
+ *                          otherwise (SRAM/DRAM/host address).
+ * @contains_dma_pkt: whether the JOB contains at least one DMA packet. This
+ *                    info is needed later, when adding the 2xMSG_PROT at the
+ *                    end of the JOB, to know which barriers to put in the
+ *                    MSG_PROT packets. Relevant only for GAUDI as GOYA doesn't
+ *                    have streams so the engine can't be busy by another
+ *                    stream.
+ * @completion: true if we need completion for this CS.
+ */
+struct hl_cs_parser {
+	struct hl_cb		*user_cb;
+	struct hl_cb		*patched_cb;
+	struct list_head	*job_userptr_list;
+	u64			cs_sequence;
+	enum hl_queue_type	queue_type;
+	u32			ctx_id;
+	u32			hw_queue_id;
+	u32			user_cb_size;
+	u32			patched_cb_size;
+	u8			job_id;
+	u8			is_kernel_allocated_cb;
+	u8			contains_dma_pkt;
+	u8			completion;
+};
+
+/*
+ * MEMORY STRUCTURE
+ */
+
+/**
+ * struct hl_vm_hash_node - hash element from virtual address to virtual
+ *				memory area descriptor (hl_vm_phys_pg_list or
+ *				hl_userptr).
+ * @node: node to hang on the hash table in context object.
+ * @vaddr: key virtual address.
+ * @handle: memory handle for device memory allocation.
+ * @ptr: value pointer (hl_vm_phys_pg_list or hl_userptr).
+ * @export_cnt: number of exports from within the VA block.
+ */
+struct hl_vm_hash_node {
+	struct hlist_node	node;
+	u64			vaddr;
+	u64			handle;
+	void			*ptr;
+	int			export_cnt;
+};
+
+/**
+ * struct hl_vm_hw_block_list_node - list element from user virtual address to
+ *				HW block id.
+ * @node: node to hang on the list in context object.
+ * @ctx: the context this node belongs to.
+ * @vaddr: virtual address of the HW block.
+ * @block_size: size of the block.
+ * @mapped_size: size of the block which is mapped. May change if partial un-mappings are done.
+ * @id: HW block id (handle).
+ */
+struct hl_vm_hw_block_list_node {
+	struct list_head	node;
+	struct hl_ctx		*ctx;
+	unsigned long		vaddr;
+	u32			block_size;
+	u32			mapped_size;
+	u32			id;
+};
+
+/**
+ * struct hl_vm_phys_pg_pack - physical page pack.
+ * @vm_type: describes the type of the virtual area descriptor.
+ * @pages: the physical page array.
+ * @npages: num physical pages in the pack.
+ * @total_size: total size of all the pages in this list.
+ * @node: used to attach to deletion list that is used when all the allocations are cleared
+ *        at the teardown of the context.
+ * @mapping_cnt: number of shared mappings.
+ * @asid: the context related to this list.
+ * @page_size: size of each page in the pack.
+ * @flags: HL_MEM_* flags related to this list.
+ * @handle: the provided handle related to this list.
+ * @offset: offset from the first page.
+ * @contiguous: is contiguous physical memory.
+ * @created_from_userptr: is product of host virtual address.
+ */
+struct hl_vm_phys_pg_pack {
+	enum vm_type		vm_type; /* must be first */
+	u64			*pages;
+	u64			npages;
+	u64			total_size;
+	struct list_head	node;
+	atomic_t		mapping_cnt;
+	u32			asid;
+	u32			page_size;
+	u32			flags;
+	u32			handle;
+	u32			offset;
+	u8			contiguous;
+	u8			created_from_userptr;
+};
+
+/**
+ * struct hl_vm_va_block - virtual range block information.
+ * @node: node to hang on the virtual range list in context object.
+ * @start: virtual range start address.
+ * @end: virtual range end address.
+ * @size: virtual range size.
+ */
+struct hl_vm_va_block {
+	struct list_head	node;
+	u64			start;
+	u64			end;
+	u64			size;
+};
+
+/**
+ * struct hl_vm - virtual memory manager for MMU.
+ * @dram_pg_pool: pool for DRAM physical pages of 2MB.
+ * @dram_pg_pool_refcount: reference counter for the pool usage.
+ * @idr_lock: protects the phys_pg_list_handles.
+ * @phys_pg_pack_handles: idr to hold all device allocations handles.
+ * @init_done: whether initialization was done. We need this because VM
+ *		initialization might be skipped during device initialization.
+ */
+struct hl_vm {
+	struct gen_pool		*dram_pg_pool;
+	struct kref		dram_pg_pool_refcount;
+	spinlock_t		idr_lock;
+	struct idr		phys_pg_pack_handles;
+	u8			init_done;
+};
+
+#ifdef CONFIG_HL_HLDIO
+#include "hldio.h"
+#endif
+
+/*
+ * DEBUG, PROFILING STRUCTURE
+ */
+
+/**
+ * struct hl_debug_params - Coresight debug parameters.
+ * @input: pointer to component specific input parameters.
+ * @output: pointer to component specific output parameters.
+ * @output_size: size of output buffer.
+ * @reg_idx: relevant register ID.
+ * @op: component operation to execute.
+ * @enable: true if to enable component debugging, false otherwise.
+ */
+struct hl_debug_params {
+	void *input;
+	void *output;
+	u32 output_size;
+	u32 reg_idx;
+	u32 op;
+	bool enable;
+};
+
+/**
+ * struct hl_notifier_event - holds the notifier data structure
+ * @eventfd: the event file descriptor to raise the notifications
+ * @lock: mutex lock to protect the notifier data flows
+ * @events_mask: indicates the bitmap events
+ */
+struct hl_notifier_event {
+	struct eventfd_ctx	*eventfd;
+	struct mutex		lock;
+	u64			events_mask;
+};
+
+/*
+ * FILE PRIVATE STRUCTURE
+ */
+
+/**
+ * struct hl_fpriv - process information stored in FD private data.
+ * @hdev: habanalabs device structure.
+ * @file_priv: pointer to the DRM file private data structure.
+ * @taskpid: current process ID.
+ * @ctx: current executing context. TODO: remove for multiple ctx per process
+ * @ctx_mgr: context manager to handle multiple context for this FD.
+ * @mem_mgr: manager descriptor for memory exportable via mmap
+ * @notifier_event: notifier eventfd towards user process
+ * @debugfs_list: list of relevant ASIC debugfs.
+ * @dev_node: node in the device list of file private data
+ * @refcount: number of related contexts.
+ * @restore_phase_mutex: lock for context switch and restore phase.
+ * @ctx_lock: protects the pointer to current executing context pointer. TODO: remove for multiple
+ *            ctx per process.
+ */
+struct hl_fpriv {
+	struct hl_device		*hdev;
+	struct drm_file			*file_priv;
+	struct pid			*taskpid;
+	struct hl_ctx			*ctx;
+	struct hl_ctx_mgr		ctx_mgr;
+	struct hl_mem_mgr		mem_mgr;
+	struct hl_notifier_event	notifier_event;
+	struct list_head		debugfs_list;
+	struct list_head		dev_node;
+	struct kref			refcount;
+	struct mutex			restore_phase_mutex;
+	struct mutex			ctx_lock;
+};
+
+/*
+ * DebugFS
+ */
+
+/**
+ * struct hl_info_list - debugfs file ops.
+ * @name: file name.
+ * @show: function to output information.
+ * @write: function to write to the file.
+ */
+struct hl_info_list {
+	const char	*name;
+	int		(*show)(struct seq_file *s, void *data);
+	ssize_t		(*write)(struct file *file, const char __user *buf,
+				size_t count, loff_t *f_pos);
+};
+
+/**
+ * struct hl_debugfs_entry - debugfs dentry wrapper.
+ * @info_ent: dentry related ops.
+ * @dev_entry: ASIC specific debugfs manager.
+ */
+struct hl_debugfs_entry {
+	const struct hl_info_list	*info_ent;
+	struct hl_dbg_device_entry	*dev_entry;
+};
+
+
+/**
+ * struct hl_dbg_device_entry - ASIC specific debugfs manager.
+ * @root: root dentry.
+ * @hdev: habanalabs device structure.
+ * @entry_arr: array of available hl_debugfs_entry.
+ * @file_list: list of available debugfs files.
+ * @file_mutex: protects file_list.
+ * @cb_list: list of available CBs.
+ * @cb_spinlock: protects cb_list.
+ * @cs_list: list of available CSs.
+ * @cs_spinlock: protects cs_list.
+ * @cs_job_list: list of available CB jobs.
+ * @cs_job_spinlock: protects cs_job_list.
+ * @userptr_list: list of available userptrs (virtual memory chunk descriptor).
+ * @userptr_spinlock: protects userptr_list.
+ * @ctx_mem_hash_list: list of available contexts with MMU mappings.
+ * @ctx_mem_hash_mutex: protects list of available contexts with MMU mappings.
+ * @data_dma_blob_desc: data DMA descriptor of blob.
+ * @mon_dump_blob_desc: monitor dump descriptor of blob.
+ * @state_dump: data of the system states in case of a bad cs.
+ * @state_dump_sem: protects state_dump.
+ * @addr: next address to read/write from/to in read/write32.
+ * @mmu_addr: next virtual address to translate to physical address in mmu_show.
+ * @mmu_cap_mask: mmu hw capability mask, to be used in mmu_ack_error.
+ * @userptr_lookup: the target user ptr to look up for on demand.
+ * @mmu_asid: ASID to use while translating in mmu_show.
+ * @state_dump_head: index of the latest state dump
+ * @i2c_bus: generic u8 debugfs file for bus value to use in i2c_data_read.
+ * @i2c_addr: generic u8 debugfs file for address value to use in i2c_data_read.
+ * @i2c_reg: generic u8 debugfs file for register value to use in i2c_data_read.
+ * @i2c_len: generic u8 debugfs file for length value to use in i2c_data_read.
+ * @dio_stats: Direct I/O statistics
+ */
+struct hl_dbg_device_entry {
+	struct dentry			*root;
+	struct hl_device		*hdev;
+	struct hl_debugfs_entry		*entry_arr;
+	struct list_head		file_list;
+	struct mutex			file_mutex;
+	struct list_head		cb_list;
+	spinlock_t			cb_spinlock;
+	struct list_head		cs_list;
+	spinlock_t			cs_spinlock;
+	struct list_head		cs_job_list;
+	spinlock_t			cs_job_spinlock;
+	struct list_head		userptr_list;
+	spinlock_t			userptr_spinlock;
+	struct list_head		ctx_mem_hash_list;
+	struct mutex			ctx_mem_hash_mutex;
+	struct debugfs_blob_wrapper	data_dma_blob_desc;
+	struct debugfs_blob_wrapper	mon_dump_blob_desc;
+	char				*state_dump[HL_STATE_DUMP_HIST_LEN];
+	struct rw_semaphore		state_dump_sem;
+	u64				addr;
+	u64				mmu_addr;
+	u64				mmu_cap_mask;
+	u64				userptr_lookup;
+	u32				mmu_asid;
+	u32				state_dump_head;
+	u8				i2c_bus;
+	u8				i2c_addr;
+	u8				i2c_reg;
+	u8				i2c_len;
+#ifdef CONFIG_HL_HLDIO
+	struct hl_dio_stats	dio_stats;
+#endif
+};
+
+/**
+ * struct hl_debugfs_cfg_access_entry - single debugfs config access object, member of
+ * hl_debugfs_cfg_access.
+ * @seconds_since_epoch: seconds since January 1, 1970, used for time comparisons.
+ * @debugfs_type: the debugfs operation requested, can be READ32, WRITE32, READ64 or WRITE64.
+ * @addr: the requested address to access.
+ * @valid: if set, this entry has valid data for dumping at interrupt time.
+ */
+struct hl_debugfs_cfg_access_entry {
+	ktime_t				seconds_since_epoch;
+	enum debugfs_access_type	debugfs_type;
+	u64				addr;
+	bool				valid;
+};
+
+/**
+ * struct hl_debugfs_cfg_access - saves debugfs config region access requests history.
+ * @cfg_access_list: list of objects describing config region access requests.
+ * @head: next valid index to add new entry to in cfg_access_list.
+ */
+struct hl_debugfs_cfg_access {
+	struct hl_debugfs_cfg_access_entry	cfg_access_list[HL_DBGFS_CFG_ACCESS_HIST_LEN];
+	u32					head;
+	spinlock_t			lock; /* protects head and entries */
+};
+
+/**
+ * struct hl_hw_obj_name_entry - single hw object name, member of
+ * hl_state_dump_specs
+ * @node: link to the containing hash table
+ * @name: hw object name
+ * @id: object identifier
+ */
+struct hl_hw_obj_name_entry {
+	struct hlist_node	node;
+	const char		*name;
+	u32			id;
+};
+
+enum hl_state_dump_specs_props {
+	SP_SYNC_OBJ_BASE_ADDR,
+	SP_NEXT_SYNC_OBJ_ADDR,
+	SP_SYNC_OBJ_AMOUNT,
+	SP_MON_OBJ_WR_ADDR_LOW,
+	SP_MON_OBJ_WR_ADDR_HIGH,
+	SP_MON_OBJ_WR_DATA,
+	SP_MON_OBJ_ARM_DATA,
+	SP_MON_OBJ_STATUS,
+	SP_MONITORS_AMOUNT,
+	SP_TPC0_CMDQ,
+	SP_TPC0_CFG_SO,
+	SP_NEXT_TPC,
+	SP_MME_CMDQ,
+	SP_MME_CFG_SO,
+	SP_NEXT_MME,
+	SP_DMA_CMDQ,
+	SP_DMA_CFG_SO,
+	SP_DMA_QUEUES_OFFSET,
+	SP_NUM_OF_MME_ENGINES,
+	SP_SUB_MME_ENG_NUM,
+	SP_NUM_OF_DMA_ENGINES,
+	SP_NUM_OF_TPC_ENGINES,
+	SP_ENGINE_NUM_OF_QUEUES,
+	SP_ENGINE_NUM_OF_STREAMS,
+	SP_ENGINE_NUM_OF_FENCES,
+	SP_FENCE0_CNT_OFFSET,
+	SP_FENCE0_RDATA_OFFSET,
+	SP_CP_STS_OFFSET,
+	SP_NUM_CORES,
+
+	SP_MAX
+};
+
+enum hl_sync_engine_type {
+	ENGINE_TPC,
+	ENGINE_DMA,
+	ENGINE_MME,
+};
+
+/**
+ * struct hl_mon_state_dump - represents a state dump of a single monitor
+ * @id: monitor id
+ * @wr_addr_low: address monitor will write to, low bits
+ * @wr_addr_high: address monitor will write to, high bits
+ * @wr_data: data monitor will write
+ * @arm_data: register value containing monitor configuration
+ * @status: monitor status
+ */
+struct hl_mon_state_dump {
+	u32		id;
+	u32		wr_addr_low;
+	u32		wr_addr_high;
+	u32		wr_data;
+	u32		arm_data;
+	u32		status;
+};
+
+/**
+ * struct hl_sync_to_engine_map_entry - sync object id to engine mapping entry
+ * @engine_type: type of the engine
+ * @engine_id: id of the engine
+ * @sync_id: id of the sync object
+ */
+struct hl_sync_to_engine_map_entry {
+	struct hlist_node		node;
+	enum hl_sync_engine_type	engine_type;
+	u32				engine_id;
+	u32				sync_id;
+};
+
+/**
+ * struct hl_sync_to_engine_map - maps sync object id to associated engine id
+ * @tb: hash table containing the mapping, each element is of type
+ *      struct hl_sync_to_engine_map_entry
+ */
+struct hl_sync_to_engine_map {
+	DECLARE_HASHTABLE(tb, SYNC_TO_ENGINE_HASH_TABLE_BITS);
+};
+
+/**
+ * struct hl_state_dump_specs_funcs - virtual functions used by the state dump
+ * @gen_sync_to_engine_map: generate a hash map from sync obj id to its engine
+ * @print_single_monitor: format monitor data as string
+ * @monitor_valid: return true if given monitor dump is valid
+ * @print_fences_single_engine: format fences data as string
+ */
+struct hl_state_dump_specs_funcs {
+	int (*gen_sync_to_engine_map)(struct hl_device *hdev,
+				struct hl_sync_to_engine_map *map);
+	int (*print_single_monitor)(char **buf, size_t *size, size_t *offset,
+				    struct hl_device *hdev,
+				    struct hl_mon_state_dump *mon);
+	int (*monitor_valid)(struct hl_mon_state_dump *mon);
+	int (*print_fences_single_engine)(struct hl_device *hdev,
+					u64 base_offset,
+					u64 status_base_offset,
+					enum hl_sync_engine_type engine_type,
+					u32 engine_id, char **buf,
+					size_t *size, size_t *offset);
+};
+
+/**
+ * struct hl_state_dump_specs - defines ASIC known hw objects names
+ * @so_id_to_str_tb: sync objects names index table
+ * @monitor_id_to_str_tb: monitors names index table
+ * @funcs: virtual functions used for state dump
+ * @sync_namager_names: readable names for sync manager if available (ex: N_E)
+ * @props: pointer to a per asic const props array required for state dump
+ */
+struct hl_state_dump_specs {
+	DECLARE_HASHTABLE(so_id_to_str_tb, OBJ_NAMES_HASH_TABLE_BITS);
+	DECLARE_HASHTABLE(monitor_id_to_str_tb, OBJ_NAMES_HASH_TABLE_BITS);
+	struct hl_state_dump_specs_funcs	funcs;
+	const char * const			*sync_namager_names;
+	s64					*props;
+};
+
+
+/*
+ * DEVICES
+ */
+
+#define HL_STR_MAX	64
+
+#define HL_DEV_STS_MAX (HL_DEVICE_STATUS_LAST + 1)
+
+/* Theoretical limit only. A single host can only contain up to 4 or 8 PCIe
+ * x16 cards. In extreme cases, there are hosts that can accommodate 16 cards.
+ */
+#define HL_MAX_MINORS	256
+
+/*
+ * Registers read & write functions.
+ */
+
+u32 hl_rreg(struct hl_device *hdev, u32 reg);
+void hl_wreg(struct hl_device *hdev, u32 reg, u32 val);
+
+#define RREG32(reg) hdev->asic_funcs->rreg(hdev, (reg))
+#define WREG32(reg, v) hdev->asic_funcs->wreg(hdev, (reg), (v))
+#define DREG32(reg) pr_info("REGISTER: " #reg " : 0x%08X\n",	\
+			hdev->asic_funcs->rreg(hdev, (reg)))
+
+#define WREG32_P(reg, val, mask)				\
+	do {							\
+		u32 tmp_ = RREG32(reg);				\
+		tmp_ &= (mask);					\
+		tmp_ |= ((val) & ~(mask));			\
+		WREG32(reg, tmp_);				\
+	} while (0)
+#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
+#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
+
+#define RMWREG32_SHIFTED(reg, val, mask) WREG32_P(reg, val, ~(mask))
+
+#define RMWREG32(reg, val, mask) RMWREG32_SHIFTED(reg, (val) << __ffs(mask), mask)
+
+#define RREG32_MASK(reg, mask) ((RREG32(reg) & mask) >> __ffs(mask))
+
+#define REG_FIELD_SHIFT(reg, field) reg##_##field##_SHIFT
+#define REG_FIELD_MASK(reg, field) reg##_##field##_MASK
+#define WREG32_FIELD(reg, offset, field, val)	\
+	WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & \
+				~REG_FIELD_MASK(reg, field)) | \
+				(val) << REG_FIELD_SHIFT(reg, field))
+
+/* Timeout should be longer when working with simulator but cap the
+ * increased timeout to some maximum
+ */
+#define hl_poll_timeout_common(hdev, addr, val, cond, sleep_us, timeout_us, elbi) \
+({ \
+	ktime_t __timeout; \
+	u32 __elbi_read; \
+	int __rc = 0; \
+	__timeout = ktime_add_us(ktime_get(), timeout_us); \
+	might_sleep_if(sleep_us); \
+	for (;;) { \
+		if (elbi) { \
+			__rc = hl_pci_elbi_read(hdev, addr, &__elbi_read); \
+			if (__rc) \
+				break; \
+			(val) = __elbi_read; \
+		} else {\
+			(val) = RREG32(lower_32_bits(addr)); \
+		} \
+		if (cond) \
+			break; \
+		if (timeout_us && ktime_compare(ktime_get(), __timeout) > 0) { \
+			if (elbi) { \
+				__rc = hl_pci_elbi_read(hdev, addr, &__elbi_read); \
+				if (__rc) \
+					break; \
+				(val) = __elbi_read; \
+			} else {\
+				(val) = RREG32(lower_32_bits(addr)); \
+			} \
+			break; \
+		} \
+		if (sleep_us) \
+			usleep_range((sleep_us >> 2) + 1, sleep_us); \
+	} \
+	__rc ? __rc : ((cond) ? 0 : -ETIMEDOUT); \
+})
+
+#define hl_poll_timeout(hdev, addr, val, cond, sleep_us, timeout_us) \
+		hl_poll_timeout_common(hdev, addr, val, cond, sleep_us, timeout_us, false)
+
+#define hl_poll_timeout_elbi(hdev, addr, val, cond, sleep_us, timeout_us) \
+		hl_poll_timeout_common(hdev, addr, val, cond, sleep_us, timeout_us, true)
+
+/*
+ * poll array of register addresses.
+ * condition is satisfied if all registers values match the expected value.
+ * once some register in the array satisfies the condition it will not be polled again,
+ * this is done both for efficiency and due to some registers are "clear on read".
+ * TODO: use read from PCI bar in other places in the code (SW-91406)
+ */
+#define hl_poll_reg_array_timeout_common(hdev, addr_arr, arr_size, expected_val, sleep_us, \
+						timeout_us, elbi) \
+({ \
+	ktime_t __timeout; \
+	u64 __elem_bitmask; \
+	u32 __read_val;	\
+	u8 __arr_idx;	\
+	int __rc = 0; \
+	\
+	__timeout = ktime_add_us(ktime_get(), timeout_us); \
+	might_sleep_if(sleep_us); \
+	if (arr_size >= 64) \
+		__rc = -EINVAL; \
+	else \
+		__elem_bitmask = BIT_ULL(arr_size) - 1; \
+	for (;;) { \
+		if (__rc) \
+			break; \
+		for (__arr_idx = 0; __arr_idx < (arr_size); __arr_idx++) {	\
+			if (!(__elem_bitmask & BIT_ULL(__arr_idx)))	\
+				continue;	\
+			if (elbi) { \
+				__rc = hl_pci_elbi_read(hdev, (addr_arr)[__arr_idx], &__read_val); \
+				if (__rc) \
+					break; \
+			} else { \
+				__read_val = RREG32(lower_32_bits(addr_arr[__arr_idx])); \
+			} \
+			if (__read_val == (expected_val))	\
+				__elem_bitmask &= ~BIT_ULL(__arr_idx);	\
+		}	\
+		if (__rc || (__elem_bitmask == 0)) \
+			break; \
+		if (timeout_us && ktime_compare(ktime_get(), __timeout) > 0) \
+			break; \
+		if (sleep_us) \
+			usleep_range((sleep_us >> 2) + 1, sleep_us); \
+	} \
+	__rc ? __rc : ((__elem_bitmask == 0) ? 0 : -ETIMEDOUT); \
+})
+
+#define hl_poll_reg_array_timeout(hdev, addr_arr, arr_size, expected_val, sleep_us, \
+					timeout_us) \
+	hl_poll_reg_array_timeout_common(hdev, addr_arr, arr_size, expected_val, sleep_us, \
+						timeout_us, false)
+
+#define hl_poll_reg_array_timeout_elbi(hdev, addr_arr, arr_size, expected_val, sleep_us, \
+					timeout_us) \
+	hl_poll_reg_array_timeout_common(hdev, addr_arr, arr_size, expected_val, sleep_us, \
+						timeout_us, true)
+
+/*
+ * address in this macro points always to a memory location in the
+ * host's (server's) memory. That location is updated asynchronously
+ * either by the direct access of the device or by another core.
+ *
+ * To work both in LE and BE architectures, we need to distinguish between the
+ * two states (device or another core updates the memory location). Therefore,
+ * if mem_written_by_device is true, the host memory being polled will be
+ * updated directly by the device. If false, the host memory being polled will
+ * be updated by host CPU. Required so host knows whether or not the memory
+ * might need to be byte-swapped before returning value to caller.
+ *
+ * On the first 4 polling iterations the macro goes to sleep for short period of
+ * time that gradually increases and reaches sleep_us on the fifth iteration.
+ */
+#define hl_poll_timeout_memory(hdev, addr, val, cond, sleep_us, timeout_us, \
+				mem_written_by_device) \
+({ \
+	u64 __sleep_step_us; \
+	ktime_t __timeout; \
+	u8 __step = 8; \
+	\
+	__timeout = ktime_add_us(ktime_get(), timeout_us); \
+	might_sleep_if(sleep_us); \
+	for (;;) { \
+		/* Verify we read updates done by other cores or by device */ \
+		mb(); \
+		(val) = *((u32 *)(addr)); \
+		if (mem_written_by_device) \
+			(val) = le32_to_cpu(*(__le32 *) &(val)); \
+		if (cond) \
+			break; \
+		if (timeout_us && ktime_compare(ktime_get(), __timeout) > 0) { \
+			(val) = *((u32 *)(addr)); \
+			if (mem_written_by_device) \
+				(val) = le32_to_cpu(*(__le32 *) &(val)); \
+			break; \
+		} \
+		__sleep_step_us = sleep_us >> __step; \
+		if (__sleep_step_us) \
+			usleep_range((__sleep_step_us >> 2) + 1, __sleep_step_us); \
+		__step >>= 1; \
+	} \
+	(cond) ? 0 : -ETIMEDOUT; \
+})
+
+#define HL_USR_MAPPED_BLK_INIT(blk, base, sz) \
+({ \
+	struct user_mapped_block *p = blk; \
+\
+	p->address = base; \
+	p->size = sz; \
+})
+
+#define HL_USR_INTR_STRUCT_INIT(usr_intr, hdev, intr_id, intr_type) \
+({ \
+	usr_intr.hdev = hdev; \
+	usr_intr.interrupt_id = intr_id; \
+	usr_intr.type = intr_type; \
+	INIT_LIST_HEAD(&usr_intr.wait_list_head); \
+	spin_lock_init(&usr_intr.wait_list_lock); \
+	INIT_LIST_HEAD(&usr_intr.ts_list_head); \
+	spin_lock_init(&usr_intr.ts_list_lock); \
+})
+
+struct hwmon_chip_info;
+
+/**
+ * struct hl_device_reset_work - reset work wrapper.
+ * @reset_work: reset work to be done.
+ * @hdev: habanalabs device structure.
+ * @flags: reset flags.
+ */
+struct hl_device_reset_work {
+	struct delayed_work	reset_work;
+	struct hl_device	*hdev;
+	u32			flags;
+};
+
+/**
+ * struct hl_mmu_hr_pgt_priv - used for holding per-device mmu host-resident
+ * page-table internal information.
+ * @mmu_pgt_pool: pool of page tables used by a host-resident MMU for
+ *                allocating hops.
+ * @mmu_asid_hop0: per-ASID array of host-resident hop0 tables.
+ */
+struct hl_mmu_hr_priv {
+	struct gen_pool	*mmu_pgt_pool;
+	struct pgt_info	*mmu_asid_hop0;
+};
+
+/**
+ * struct hl_mmu_dr_pgt_priv - used for holding per-device mmu device-resident
+ * page-table internal information.
+ * @mmu_pgt_pool: pool of page tables used by MMU for allocating hops.
+ * @mmu_shadow_hop0: shadow array of hop0 tables.
+ */
+struct hl_mmu_dr_priv {
+	struct gen_pool *mmu_pgt_pool;
+	void *mmu_shadow_hop0;
+};
+
+/**
+ * struct hl_mmu_priv - used for holding per-device mmu internal information.
+ * @dr: information on the device-resident MMU, when exists.
+ * @hr: information on the host-resident MMU, when exists.
+ */
+struct hl_mmu_priv {
+	struct hl_mmu_dr_priv dr;
+	struct hl_mmu_hr_priv hr;
+};
+
+/**
+ * struct hl_mmu_per_hop_info - A structure describing one TLB HOP and its entry
+ *                that was created in order to translate a virtual address to a
+ *                physical one.
+ * @hop_addr: The address of the hop.
+ * @hop_pte_addr: The address of the hop entry.
+ * @hop_pte_val: The value in the hop entry.
+ */
+struct hl_mmu_per_hop_info {
+	u64 hop_addr;
+	u64 hop_pte_addr;
+	u64 hop_pte_val;
+};
+
+/**
+ * struct hl_mmu_hop_info - A structure describing the TLB hops and their
+ * hop-entries that were created in order to translate a virtual address to a
+ * physical one.
+ * @scrambled_vaddr: The value of the virtual address after scrambling. This
+ *                   address replaces the original virtual-address when mapped
+ *                   in the MMU tables.
+ * @unscrambled_paddr: The un-scrambled physical address.
+ * @hop_info: Array holding the per-hop information used for the translation.
+ * @used_hops: The number of hops used for the translation.
+ * @range_type: virtual address range type.
+ */
+struct hl_mmu_hop_info {
+	u64 scrambled_vaddr;
+	u64 unscrambled_paddr;
+	struct hl_mmu_per_hop_info hop_info[MMU_ARCH_6_HOPS];
+	u32 used_hops;
+	enum hl_va_range_type range_type;
+};
+
+/**
+ * struct hl_hr_mmu_funcs - Device related host resident MMU functions.
+ * @get_hop0_pgt_info: get page table info structure for HOP0.
+ * @get_pgt_info: get page table info structure for HOP other than HOP0.
+ * @add_pgt_info: add page table info structure to hash.
+ * @get_tlb_mapping_params: get mapping parameters needed for getting TLB info for specific mapping.
+ */
+struct hl_hr_mmu_funcs {
+	struct pgt_info *(*get_hop0_pgt_info)(struct hl_ctx *ctx);
+	struct pgt_info *(*get_pgt_info)(struct hl_ctx *ctx, u64 phys_hop_addr);
+	void (*add_pgt_info)(struct hl_ctx *ctx, struct pgt_info *pgt_info, dma_addr_t phys_addr);
+	int (*get_tlb_mapping_params)(struct hl_device *hdev, struct hl_mmu_properties **mmu_prop,
+								struct hl_mmu_hop_info *hops,
+								u64 virt_addr, bool *is_huge);
+};
+
+/**
+ * struct hl_mmu_funcs - Device related MMU functions.
+ * @init: initialize the MMU module.
+ * @fini: release the MMU module.
+ * @ctx_init: Initialize a context for using the MMU module.
+ * @ctx_fini: disable a ctx from using the mmu module.
+ * @map: maps a virtual address to physical address for a context.
+ * @unmap: unmap a virtual address of a context.
+ * @flush: flush all writes from all cores to reach device MMU.
+ * @swap_out: marks all mapping of the given context as swapped out.
+ * @swap_in: marks all mapping of the given context as swapped in.
+ * @get_tlb_info: returns the list of hops and hop-entries used that were
+ *                created in order to translate the giver virtual address to a
+ *                physical one.
+ * @hr_funcs: functions specific to host resident MMU.
+ */
+struct hl_mmu_funcs {
+	int (*init)(struct hl_device *hdev);
+	void (*fini)(struct hl_device *hdev);
+	int (*ctx_init)(struct hl_ctx *ctx);
+	void (*ctx_fini)(struct hl_ctx *ctx);
+	int (*map)(struct hl_ctx *ctx, u64 virt_addr, u64 phys_addr, u32 page_size,
+				bool is_dram_addr);
+	int (*unmap)(struct hl_ctx *ctx, u64 virt_addr, bool is_dram_addr);
+	void (*flush)(struct hl_ctx *ctx);
+	void (*swap_out)(struct hl_ctx *ctx);
+	void (*swap_in)(struct hl_ctx *ctx);
+	int (*get_tlb_info)(struct hl_ctx *ctx, u64 virt_addr, struct hl_mmu_hop_info *hops);
+	struct hl_hr_mmu_funcs hr_funcs;
+};
+
+/**
+ * struct hl_prefetch_work - prefetch work structure handler
+ * @prefetch_work: actual work struct.
+ * @ctx: compute context.
+ * @va: virtual address to pre-fetch.
+ * @size: pre-fetch size.
+ * @flags: operation flags.
+ * @asid: ASID for maintenance operation.
+ */
+struct hl_prefetch_work {
+	struct work_struct	prefetch_work;
+	struct hl_ctx		*ctx;
+	u64			va;
+	u64			size;
+	u32			flags;
+	u32			asid;
+};
+
+/*
+ * number of user contexts allowed to call wait_for_multi_cs ioctl in
+ * parallel
+ */
+#define MULTI_CS_MAX_USER_CTX	2
+
+/**
+ * struct multi_cs_completion - multi CS wait completion.
+ * @completion: completion of any of the CS in the list
+ * @lock: spinlock for the completion structure
+ * @timestamp: timestamp for the multi-CS completion
+ * @stream_master_qid_map: bitmap of all stream masters on which the multi-CS
+ *                        is waiting
+ * @used: 1 if in use, otherwise 0
+ */
+struct multi_cs_completion {
+	struct completion	completion;
+	spinlock_t		lock;
+	s64			timestamp;
+	u32			stream_master_qid_map;
+	u8			used;
+};
+
+/**
+ * struct multi_cs_data - internal data for multi CS call
+ * @ctx: pointer to the context structure
+ * @fence_arr: array of fences of all CSs
+ * @seq_arr: array of CS sequence numbers
+ * @timeout_jiffies: timeout in jiffies for waiting for CS to complete
+ * @timestamp: timestamp of first completed CS
+ * @wait_status: wait for CS status
+ * @completion_bitmap: bitmap of completed CSs (1- completed, otherwise 0)
+ * @arr_len: fence_arr and seq_arr array length
+ * @gone_cs: indication of gone CS (1- there was gone CS, otherwise 0)
+ * @update_ts: update timestamp. 1- update the timestamp, otherwise 0.
+ */
+struct multi_cs_data {
+	struct hl_ctx	*ctx;
+	struct hl_fence	**fence_arr;
+	u64		*seq_arr;
+	s64		timeout_jiffies;
+	s64		timestamp;
+	long		wait_status;
+	u32		completion_bitmap;
+	u8		arr_len;
+	u8		gone_cs;
+	u8		update_ts;
+};
+
+/**
+ * struct hl_clk_throttle_timestamp - current/last clock throttling timestamp
+ * @start: timestamp taken when 'start' event is received in driver
+ * @end: timestamp taken when 'end' event is received in driver
+ */
+struct hl_clk_throttle_timestamp {
+	ktime_t		start;
+	ktime_t		end;
+};
+
+/**
+ * struct hl_clk_throttle - keeps current/last clock throttling timestamps
+ * @timestamp: timestamp taken by driver and firmware, index 0 refers to POWER
+ *             index 1 refers to THERMAL
+ * @lock: protects this structure as it can be accessed from both event queue
+ *        context and info_ioctl context
+ * @current_reason: bitmask represents the current clk throttling reasons
+ * @aggregated_reason: bitmask represents aggregated clk throttling reasons since driver load
+ */
+struct hl_clk_throttle {
+	struct hl_clk_throttle_timestamp timestamp[HL_CLK_THROTTLE_TYPE_MAX];
+	struct mutex	lock;
+	u32		current_reason;
+	u32		aggregated_reason;
+};
+
+/**
+ * struct user_mapped_block - describes a hw block allowed to be mmapped by user
+ * @address: physical HW block address
+ * @size: allowed size for mmap
+ */
+struct user_mapped_block {
+	u32 address;
+	u32 size;
+};
+
+/**
+ * struct cs_timeout_info - info of last CS timeout occurred.
+ * @timestamp: CS timeout timestamp.
+ * @write_enable: if set writing to CS parameters in the structure is enabled. otherwise - disabled,
+ *                so the first (root cause) CS timeout will not be overwritten.
+ * @seq: CS timeout sequence number.
+ */
+struct cs_timeout_info {
+	ktime_t		timestamp;
+	atomic_t	write_enable;
+	u64		seq;
+};
+
+#define MAX_QMAN_STREAMS_INFO		4
+#define OPCODE_INFO_MAX_ADDR_SIZE	8
+/**
+ * struct undefined_opcode_info - info about last undefined opcode error
+ * @timestamp: timestamp of the undefined opcode error
+ * @cb_addr_streams: CB addresses (per stream) that are currently exists in the PQ
+ *                   entries. In case all streams array entries are
+ *                   filled with values, it means the execution was in Lower-CP.
+ * @cq_addr: the address of the current handled command buffer
+ * @cq_size: the size of the current handled command buffer
+ * @cb_addr_streams_len: num of streams - actual len of cb_addr_streams array.
+ *                       should be equal to 1 in case of undefined opcode
+ *                       in Upper-CP (specific stream) and equal to 4 in case
+ *                       of undefined opcode in Lower-CP.
+ * @engine_id: engine-id that the error occurred on
+ * @stream_id: the stream id the error occurred on. In case the stream equals to
+ *             MAX_QMAN_STREAMS_INFO it means the error occurred on a Lower-CP.
+ * @write_enable: if set, writing to undefined opcode parameters in the structure
+ *                 is enable so the first (root cause) undefined opcode will not be
+ *                 overwritten.
+ */
+struct undefined_opcode_info {
+	ktime_t timestamp;
+	u64 cb_addr_streams[MAX_QMAN_STREAMS_INFO][OPCODE_INFO_MAX_ADDR_SIZE];
+	u64 cq_addr;
+	u32 cq_size;
+	u32 cb_addr_streams_len;
+	u32 engine_id;
+	u32 stream_id;
+	bool write_enable;
+};
+
+/**
+ * struct page_fault_info - page fault information.
+ * @page_fault: holds information collected during a page fault.
+ * @user_mappings: buffer containing user mappings.
+ * @num_of_user_mappings: number of user mappings.
+ * @page_fault_detected: if set as 1, then a page-fault was discovered for the
+ *                       first time after the driver has finished booting-up.
+ *                       Since we're looking for the page-fault's root cause,
+ *                       we don't care of the others that might follow it-
+ *                       so once changed to 1, it will remain that way.
+ * @page_fault_info_available: indicates that a page fault info is now available.
+ */
+struct page_fault_info {
+	struct hl_page_fault_info	page_fault;
+	struct hl_user_mapping		*user_mappings;
+	u64				num_of_user_mappings;
+	atomic_t			page_fault_detected;
+	bool				page_fault_info_available;
+};
+
+/**
+ * struct razwi_info - RAZWI information.
+ * @razwi: holds information collected during a RAZWI
+ * @razwi_detected: if set as 1, then a RAZWI was discovered for the
+ *                  first time after the driver has finished booting-up.
+ *                  Since we're looking for the RAZWI's root cause,
+ *                  we don't care of the others that might follow it-
+ *                  so once changed to 1, it will remain that way.
+ * @razwi_info_available: indicates that a RAZWI info is now available.
+ */
+struct razwi_info {
+	struct hl_info_razwi_event	razwi;
+	atomic_t			razwi_detected;
+	bool				razwi_info_available;
+};
+
+/**
+ * struct hw_err_info - HW error information.
+ * @event: holds information on the event.
+ * @event_detected: if set as 1, then a HW event was discovered for the
+ *                  first time after the driver has finished booting-up.
+ *                  currently we assume that only fatal events (that require hard-reset) are
+ *                  reported so we don't care of the others that might follow it.
+ *                  so once changed to 1, it will remain that way.
+ *                  TODO: support multiple events.
+ * @event_info_available: indicates that a HW event info is now available.
+ */
+struct hw_err_info {
+	struct hl_info_hw_err_event	event;
+	atomic_t			event_detected;
+	bool				event_info_available;
+};
+
+/**
+ * struct fw_err_info - FW error information.
+ * @event: holds information on the event.
+ * @event_detected: if set as 1, then a FW event was discovered for the
+ *                  first time after the driver has finished booting-up.
+ *                  currently we assume that only fatal events (that require hard-reset) are
+ *                  reported so we don't care of the others that might follow it.
+ *                  so once changed to 1, it will remain that way.
+ *                  TODO: support multiple events.
+ * @event_info_available: indicates that a HW event info is now available.
+ */
+struct fw_err_info {
+	struct hl_info_fw_err_event	event;
+	atomic_t			event_detected;
+	bool				event_info_available;
+};
+
+/**
+ * struct engine_err_info - engine error information.
+ * @event: holds information on the event.
+ * @event_detected: if set as 1, then an engine event was discovered for the
+ *                  first time after the driver has finished booting-up.
+ * @event_info_available: indicates that an engine event info is now available.
+ */
+struct engine_err_info {
+	struct hl_info_engine_err_event	event;
+	atomic_t			event_detected;
+	bool				event_info_available;
+};
+
+
+/**
+ * struct hl_error_info - holds information collected during an error.
+ * @cs_timeout: CS timeout error information.
+ * @razwi_info: RAZWI information.
+ * @undef_opcode: undefined opcode information.
+ * @page_fault_info: page fault information.
+ * @hw_err: (fatal) hardware error information.
+ * @fw_err: firmware error information.
+ * @engine_err: engine error information.
+ */
+struct hl_error_info {
+	struct cs_timeout_info		cs_timeout;
+	struct razwi_info		razwi_info;
+	struct undefined_opcode_info	undef_opcode;
+	struct page_fault_info		page_fault_info;
+	struct hw_err_info		hw_err;
+	struct fw_err_info		fw_err;
+	struct engine_err_info		engine_err;
+};
+
+/**
+ * struct hl_reset_info - holds current device reset information.
+ * @lock: lock to protect critical reset flows.
+ * @compute_reset_cnt: number of compute resets since the driver was loaded.
+ * @hard_reset_cnt: number of hard resets since the driver was loaded.
+ * @hard_reset_schedule_flags: hard reset is scheduled to after current compute reset,
+ *                             here we hold the hard reset flags.
+ * @in_reset: is device in reset flow.
+ * @in_compute_reset: Device is currently in reset but not in hard-reset.
+ * @needs_reset: true if reset_on_lockup is false and device should be reset
+ *               due to lockup.
+ * @hard_reset_pending: is there a hard reset work pending.
+ * @curr_reset_cause: saves an enumerated reset cause when a hard reset is
+ *                    triggered, and cleared after it is shared with preboot.
+ * @prev_reset_trigger: saves the previous trigger which caused a reset, overridden
+ *                      with a new value on next reset
+ * @reset_trigger_repeated: set if device reset is triggered more than once with
+ *                          same cause.
+ * @skip_reset_on_timeout: Skip device reset if CS has timed out, wait for it to
+ *                         complete instead.
+ * @watchdog_active: true if a device release watchdog work is scheduled.
+ */
+struct hl_reset_info {
+	spinlock_t	lock;
+	u32		compute_reset_cnt;
+	u32		hard_reset_cnt;
+	u32		hard_reset_schedule_flags;
+	u8		in_reset;
+	u8		in_compute_reset;
+	u8		needs_reset;
+	u8		hard_reset_pending;
+	u8		curr_reset_cause;
+	u8		prev_reset_trigger;
+	u8		reset_trigger_repeated;
+	u8		skip_reset_on_timeout;
+	u8		watchdog_active;
+};
+
+/**
+ * struct eq_heartbeat_debug_info - stores debug info to be used upon heartbeat failure.
+ * @last_pq_heartbeat_ts: timestamp of the last test packet that was sent to FW.
+ *                        This packet is the trigger in FW to send the EQ heartbeat event.
+ * @last_eq_heartbeat_ts: timestamp of the last EQ heartbeat event that was received from FW.
+ * @heartbeat_event_counter: number of heartbeat events received.
+ * @cpu_queue_id: used to read the queue pi/ci
+ */
+struct eq_heartbeat_debug_info {
+	time64_t last_pq_heartbeat_ts;
+	time64_t last_eq_heartbeat_ts;
+	u32 heartbeat_event_counter;
+	u32 cpu_queue_id;
+};
+
+/**
+ * struct hl_device - habanalabs device structure.
+ * @pdev: pointer to PCI device, can be NULL in case of simulator device.
+ * @pcie_bar_phys: array of available PCIe bars physical addresses.
+ *		   (required only for PCI address match mode)
+ * @pcie_bar: array of available PCIe bars virtual addresses.
+ * @rmmio: configuration area address on SRAM.
+ * @drm: related DRM device.
+ * @cdev_ctrl: char device for control operations only (INFO IOCTL)
+ * @dev: related kernel basic device structure.
+ * @dev_ctrl: related kernel device structure for the control device
+ * @work_heartbeat: delayed work for CPU-CP is-alive check.
+ * @device_reset_work: delayed work which performs hard reset
+ * @device_release_watchdog_work: watchdog work that performs hard reset if user doesn't release
+ *                                device upon certain error cases.
+ * @asic_name: ASIC specific name.
+ * @asic_type: ASIC specific type.
+ * @completion_queue: array of hl_cq.
+ * @user_interrupt: array of hl_user_interrupt. upon the corresponding user
+ *                  interrupt, driver will monitor the list of fences
+ *                  registered to this interrupt.
+ * @tpc_interrupt: single TPC interrupt for all TPCs.
+ * @unexpected_error_interrupt: single interrupt for unexpected user error indication.
+ * @common_user_cq_interrupt: common user CQ interrupt for all user CQ interrupts.
+ *                         upon any user CQ interrupt, driver will monitor the
+ *                         list of fences registered to this common structure.
+ * @common_decoder_interrupt: common decoder interrupt for all user decoder interrupts.
+ * @shadow_cs_queue: pointer to a shadow queue that holds pointers to
+ *                   outstanding command submissions.
+ * @cq_wq: work queues of completion queues for executing work in process
+ *         context.
+ * @eq_wq: work queue of event queue for executing work in process context.
+ * @cs_cmplt_wq: work queue of CS completions for executing work in process
+ *               context.
+ * @ts_free_obj_wq: work queue for timestamp registration objects release.
+ * @prefetch_wq: work queue for MMU pre-fetch operations.
+ * @reset_wq: work queue for device reset procedure.
+ * @kernel_ctx: Kernel driver context structure.
+ * @kernel_queues: array of hl_hw_queue.
+ * @cs_mirror_list: CS mirror list for TDR.
+ * @cs_mirror_lock: protects cs_mirror_list.
+ * @kernel_mem_mgr: memory manager for memory buffers with lifespan of driver.
+ * @event_queue: event queue for IRQ from CPU-CP.
+ * @dma_pool: DMA pool for small allocations.
+ * @cpu_accessible_dma_mem: Host <-> CPU-CP shared memory CPU address.
+ * @cpu_accessible_dma_address: Host <-> CPU-CP shared memory DMA address.
+ * @cpu_accessible_dma_pool: Host <-> CPU-CP shared memory pool.
+ * @asid_bitmap: holds used/available ASIDs.
+ * @asid_mutex: protects asid_bitmap.
+ * @send_cpu_message_lock: enforces only one message in Host <-> CPU-CP queue.
+ * @debug_lock: protects critical section of setting debug mode for device
+ * @mmu_lock: protects the MMU page tables and invalidation h/w. Although the
+ *            page tables are per context, the invalidation h/w is per MMU.
+ *            Therefore, we can't allow multiple contexts (we only have two,
+ *            user and kernel) to access the invalidation h/w at the same time.
+ *            In addition, any change to the PGT, modifying the MMU hash or
+ *            walking the PGT requires talking this lock.
+ * @asic_prop: ASIC specific immutable properties.
+ * @asic_funcs: ASIC specific functions.
+ * @asic_specific: ASIC specific information to use only from ASIC files.
+ * @vm: virtual memory manager for MMU.
+ * @hwmon_dev: H/W monitor device.
+ * @hl_chip_info: ASIC's sensors information.
+ * @device_status_description: device status description.
+ * @hl_debugfs: device's debugfs manager.
+ * @debugfs_cfg_accesses: list of last debugfs config region accesses.
+ * @cb_pool: list of pre allocated CBs.
+ * @cb_pool_lock: protects the CB pool.
+ * @internal_cb_pool_virt_addr: internal command buffer pool virtual address.
+ * @internal_cb_pool_dma_addr: internal command buffer pool dma address.
+ * @internal_cb_pool: internal command buffer memory pool.
+ * @internal_cb_va_base: internal cb pool mmu virtual address base
+ * @fpriv_list: list of file private data structures. Each structure is created
+ *              when a user opens the device
+ * @fpriv_ctrl_list: list of file private data structures. Each structure is created
+ *              when a user opens the control device
+ * @fpriv_list_lock: protects the fpriv_list
+ * @fpriv_ctrl_list_lock: protects the fpriv_ctrl_list
+ * @aggregated_cs_counters: aggregated cs counters among all contexts
+ * @mmu_priv: device-specific MMU data.
+ * @mmu_func: device-related MMU functions.
+ * @dec: list of decoder sw instance
+ * @fw_loader: FW loader manager.
+ * @pci_mem_region: array of memory regions in the PCI
+ * @state_dump_specs: constants and dictionaries needed to dump system state.
+ * @multi_cs_completion: array of multi-CS completion.
+ * @clk_throttling: holds information about current/previous clock throttling events
+ * @captured_err_info: holds information about errors.
+ * @reset_info: holds current device reset information.
+ * @heartbeat_debug_info: counters used to debug heartbeat failures.
+ * @hldio: describes habanalabs direct storage interaction interface.
+ * @irq_affinity_mask: mask of available CPU cores for user and decoder interrupt handling.
+ * @stream_master_qid_arr: pointer to array with QIDs of master streams.
+ * @fw_inner_major_ver: the major of current loaded preboot inner version.
+ * @fw_inner_minor_ver: the minor of current loaded preboot inner version.
+ * @fw_sw_major_ver: the major of current loaded preboot SW version.
+ * @fw_sw_minor_ver: the minor of current loaded preboot SW version.
+ * @fw_sw_sub_minor_ver: the sub-minor of current loaded preboot SW version.
+ * @dram_used_mem: current DRAM memory consumption.
+ * @memory_scrub_val: the value to which the dram will be scrubbed to using cb scrub_device_dram
+ * @timeout_jiffies: device CS timeout value.
+ * @max_power: the max power of the device, as configured by the sysadmin. This
+ *             value is saved so in case of hard-reset, the driver will restore
+ *             this value and update the F/W after the re-initialization
+ * @boot_error_status_mask: contains a mask of the device boot error status.
+ *                          Each bit represents a different error, according to
+ *                          the defines in hl_boot_if.h. If the bit is cleared,
+ *                          the error will be ignored by the driver during
+ *                          device initialization. Mainly used to debug and
+ *                          workaround firmware bugs
+ * @dram_pci_bar_start: start bus address of PCIe bar towards DRAM.
+ * @last_successful_open_ktime: timestamp (ktime) of the last successful device open.
+ * @last_successful_open_jif: timestamp (jiffies) of the last successful
+ *                            device open.
+ * @last_open_session_duration_jif: duration (jiffies) of the last device open
+ *                                  session.
+ * @open_counter: number of successful device open operations.
+ * @fw_poll_interval_usec: FW status poll interval in usec.
+ *                         used for CPU boot status
+ * @fw_comms_poll_interval_usec: FW comms/protocol poll interval in usec.
+ *                                  used for COMMs protocols cmds(COMMS_STS_*)
+ * @dram_binning: contains mask of drams that is received from the f/w which indicates which
+ *                drams are binned-out
+ * @tpc_binning: contains mask of tpc engines that is received from the f/w which indicates which
+ *               tpc engines are binned-out
+ * @dmabuf_export_cnt: number of dma-buf exporting.
+ * @card_type: Various ASICs have several card types. This indicates the card
+ *             type of the current device.
+ * @major: habanalabs kernel driver major.
+ * @high_pll: high PLL profile frequency.
+ * @decoder_binning: contains mask of decoder engines that is received from the f/w which
+ *                   indicates which decoder engines are binned-out
+ * @edma_binning: contains mask of edma engines that is received from the f/w which
+ *                   indicates which edma engines are binned-out
+ * @device_release_watchdog_timeout_sec: device release watchdog timeout value in seconds.
+ * @rotator_binning: contains mask of rotators engines that is received from the f/w
+ *			which indicates which rotator engines are binned-out(Gaudi3 and above).
+ * @id: device minor.
+ * @cdev_idx: char device index.
+ * @cpu_pci_msb_addr: 50-bit extension bits for the device CPU's 40-bit
+ *                    addresses.
+ * @is_in_dram_scrub: true if dram scrub operation is on going.
+ * @disabled: is device disabled.
+ * @cpld_shutdown: is cpld shutdown.
+ * @late_init_done: is late init stage was done during initialization.
+ * @hwmon_initialized: is H/W monitor sensors was initialized.
+ * @reset_on_lockup: true if a reset should be done in case of stuck CS, false
+ *                   otherwise.
+ * @dram_default_page_mapping: is DRAM default page mapping enabled.
+ * @memory_scrub: true to perform device memory scrub in various locations,
+ *                such as context-switch, context close, page free, etc.
+ * @pmmu_huge_range: is a different virtual addresses range used for PMMU with
+ *                   huge pages.
+ * @init_done: is the initialization of the device done.
+ * @device_cpu_disabled: is the device CPU disabled (due to timeouts)
+ * @in_debug: whether the device is in a state where the profiling/tracing infrastructure
+ *            can be used. This indication is needed because in some ASICs we need to do
+ *            specific operations to enable that infrastructure.
+ * @cdev_sysfs_debugfs_created: were char devices and sysfs/debugfs files created.
+ * @stop_on_err: true if engines should stop on error.
+ * @supports_sync_stream: is sync stream supported.
+ * @sync_stream_queue_idx: helper index for sync stream queues initialization.
+ * @collective_mon_idx: helper index for collective initialization
+ * @supports_coresight: is CoreSight supported.
+ * @supports_cb_mapping: is mapping a CB to the device's MMU supported.
+ * @process_kill_trial_cnt: number of trials reset thread tried killing
+ *                          user processes
+ * @device_fini_pending: true if device_fini was called and might be
+ *                       waiting for the reset thread to finish
+ * @supports_staged_submission: true if staged submissions are supported
+ * @device_cpu_is_halted: Flag to indicate whether the device CPU was already
+ *                        halted. We can't halt it again because the COMMS
+ *                        protocol will throw an error. Relevant only for
+ *                        cases where Linux was not loaded to device CPU
+ * @supports_wait_for_multi_cs: true if wait for multi CS is supported
+ * @is_compute_ctx_active: Whether there is an active compute context executing.
+ * @compute_ctx_in_release: true if the current compute context is being released.
+ * @supports_mmu_prefetch: true if prefetch is supported, otherwise false.
+ * @reset_upon_device_release: reset the device when the user closes the file descriptor of the
+ *                             device.
+ * @supports_ctx_switch: true if a ctx switch is required upon first submission.
+ * @support_preboot_binning: true if we support read binning info from preboot.
+ * @eq_heartbeat_received: indication that eq heartbeat event has received from FW.
+ * @nic_ports_mask: Controls which NIC ports are enabled. Used only for testing.
+ * @fw_components: Controls which f/w components to load to the device. There are multiple f/w
+ *                 stages and sometimes we want to stop at a certain stage. Used only for testing.
+ * @mmu_disable: Disable the device MMU(s). Used only for testing.
+ * @cpu_queues_enable: Whether to enable queues communication vs. the f/w. Used only for testing.
+ * @pldm: Whether we are running in Palladium environment. Used only for testing.
+ * @hard_reset_on_fw_events: Whether to do device hard-reset when a fatal event is received from
+ *                           the f/w. Used only for testing.
+ * @bmc_enable: Whether we are running in a box with BMC. Used only for testing.
+ * @reset_on_preboot_fail: Whether to reset the device if preboot f/w fails to load.
+ *                         Used only for testing.
+ * @heartbeat: Controls if we want to enable the heartbeat mechanism vs. the f/w, which verifies
+ *             that the f/w is always alive. Used only for testing.
+ */
+struct hl_device {
+	struct pci_dev			*pdev;
+	u64				pcie_bar_phys[HL_PCI_NUM_BARS];
+	void __iomem			*pcie_bar[HL_PCI_NUM_BARS];
+	void __iomem			*rmmio;
+	struct drm_device		drm;
+	struct cdev			cdev_ctrl;
+	struct device			*dev;
+	struct device			*dev_ctrl;
+	struct delayed_work		work_heartbeat;
+	struct hl_device_reset_work	device_reset_work;
+	struct hl_device_reset_work	device_release_watchdog_work;
+	char				asic_name[HL_STR_MAX];
+	char				status[HL_DEV_STS_MAX][HL_STR_MAX];
+	enum hl_asic_type		asic_type;
+	struct hl_cq			*completion_queue;
+	struct hl_user_interrupt	*user_interrupt;
+	struct hl_user_interrupt	tpc_interrupt;
+	struct hl_user_interrupt	unexpected_error_interrupt;
+	struct hl_user_interrupt	common_user_cq_interrupt;
+	struct hl_user_interrupt	common_decoder_interrupt;
+	struct hl_cs			**shadow_cs_queue;
+	struct workqueue_struct		**cq_wq;
+	struct workqueue_struct		*eq_wq;
+	struct workqueue_struct		*cs_cmplt_wq;
+	struct workqueue_struct		*ts_free_obj_wq;
+	struct workqueue_struct		*prefetch_wq;
+	struct workqueue_struct		*reset_wq;
+	struct hl_ctx			*kernel_ctx;
+	struct hl_hw_queue		*kernel_queues;
+	struct list_head		cs_mirror_list;
+	spinlock_t			cs_mirror_lock;
+	struct hl_mem_mgr		kernel_mem_mgr;
+	struct hl_eq			event_queue;
+	struct dma_pool			*dma_pool;
+	void				*cpu_accessible_dma_mem;
+	dma_addr_t			cpu_accessible_dma_address;
+	struct gen_pool			*cpu_accessible_dma_pool;
+	unsigned long			*asid_bitmap;
+	struct mutex			asid_mutex;
+	struct mutex			send_cpu_message_lock;
+	struct mutex			debug_lock;
+	struct mutex			mmu_lock;
+	struct asic_fixed_properties	asic_prop;
+	const struct hl_asic_funcs	*asic_funcs;
+	void				*asic_specific;
+	struct hl_vm			vm;
+	struct device			*hwmon_dev;
+	struct hwmon_chip_info		*hl_chip_info;
+
+	struct hl_dbg_device_entry	hl_debugfs;
+	struct hl_debugfs_cfg_access	debugfs_cfg_accesses;
+
+	struct list_head		cb_pool;
+	spinlock_t			cb_pool_lock;
+
+	void				*internal_cb_pool_virt_addr;
+	dma_addr_t			internal_cb_pool_dma_addr;
+	struct gen_pool			*internal_cb_pool;
+	u64				internal_cb_va_base;
+
+	struct list_head		fpriv_list;
+	struct list_head		fpriv_ctrl_list;
+	struct mutex			fpriv_list_lock;
+	struct mutex			fpriv_ctrl_list_lock;
+
+	struct hl_cs_counters_atomic	aggregated_cs_counters;
+
+	struct hl_mmu_priv		mmu_priv;
+	struct hl_mmu_funcs		mmu_func[MMU_NUM_PGT_LOCATIONS];
+
+	struct hl_dec			*dec;
+
+	struct fw_load_mgr		fw_loader;
+
+	struct pci_mem_region		pci_mem_region[PCI_REGION_NUMBER];
+
+	struct hl_state_dump_specs	state_dump_specs;
+
+	struct multi_cs_completion	multi_cs_completion[
+							MULTI_CS_MAX_USER_CTX];
+	struct hl_clk_throttle		clk_throttling;
+	struct hl_error_info		captured_err_info;
+
+	struct hl_reset_info		reset_info;
+
+	struct eq_heartbeat_debug_info	heartbeat_debug_info;
+#ifdef CONFIG_HL_HLDIO
+	struct hl_dio			hldio;
+#endif
+	cpumask_t			irq_affinity_mask;
+
+	u32				*stream_master_qid_arr;
+	u32				fw_inner_major_ver;
+	u32				fw_inner_minor_ver;
+	u32				fw_sw_major_ver;
+	u32				fw_sw_minor_ver;
+	u32				fw_sw_sub_minor_ver;
+	atomic64_t			dram_used_mem;
+	u64				memory_scrub_val;
+	u64				timeout_jiffies;
+	u64				max_power;
+	u64				boot_error_status_mask;
+	u64				dram_pci_bar_start;
+	u64				last_successful_open_jif;
+	u64				last_open_session_duration_jif;
+	u64				open_counter;
+	u64				fw_poll_interval_usec;
+	ktime_t				last_successful_open_ktime;
+	u64				fw_comms_poll_interval_usec;
+	u64				dram_binning;
+	u64				tpc_binning;
+	atomic_t			dmabuf_export_cnt;
+	enum cpucp_card_types		card_type;
+	u32				major;
+	u32				high_pll;
+	u32				decoder_binning;
+	u32				edma_binning;
+	u32				device_release_watchdog_timeout_sec;
+	u32				rotator_binning;
+	u16				id;
+	u16				cdev_idx;
+	u16				cpu_pci_msb_addr;
+	u8				is_in_dram_scrub;
+	u8				disabled;
+	u8				cpld_shutdown;
+	u8				late_init_done;
+	u8				hwmon_initialized;
+	u8				reset_on_lockup;
+	u8				dram_default_page_mapping;
+	u8				memory_scrub;
+	u8				pmmu_huge_range;
+	u8				init_done;
+	u8				device_cpu_disabled;
+	u8				in_debug;
+	u8				cdev_sysfs_debugfs_created;
+	u8				stop_on_err;
+	u8				supports_sync_stream;
+	u8				sync_stream_queue_idx;
+	u8				collective_mon_idx;
+	u8				supports_coresight;
+	u8				supports_cb_mapping;
+	u8				process_kill_trial_cnt;
+	u8				device_fini_pending;
+	u8				supports_staged_submission;
+	u8				device_cpu_is_halted;
+	u8				supports_wait_for_multi_cs;
+	u8				stream_master_qid_arr_size;
+	u8				is_compute_ctx_active;
+	u8				compute_ctx_in_release;
+	u8				supports_mmu_prefetch;
+	u8				reset_upon_device_release;
+	u8				supports_ctx_switch;
+	u8				support_preboot_binning;
+	u8				eq_heartbeat_received;
+
+	/* Parameters for bring-up to be upstreamed */
+	u64				nic_ports_mask;
+	u64				fw_components;
+	u8				mmu_disable;
+	u8				cpu_queues_enable;
+	u8				pldm;
+	u8				hard_reset_on_fw_events;
+	u8				bmc_enable;
+	u8				reset_on_preboot_fail;
+	u8				heartbeat;
+};
+
+/* Retrieve PCI device name in case of a PCI device or dev name in simulator */
+#define HL_DEV_NAME(hdev)	\
+		((hdev)->pdev ? dev_name(&(hdev)->pdev->dev) : "NA-DEVICE")
+
+/**
+ * struct hl_cs_encaps_sig_handle - encapsulated signals handle structure
+ * @refcount: refcount used to protect removing this id when several
+ *            wait cs are used to wait of the reserved encaps signals.
+ * @hdev: pointer to habanalabs device structure.
+ * @hw_sob: pointer to  H/W SOB used in the reservation.
+ * @ctx: pointer to the user's context data structure
+ * @cs_seq: staged cs sequence which contains encapsulated signals
+ * @id: idr handler id to be used to fetch the handler info
+ * @q_idx: stream queue index
+ * @pre_sob_val: current SOB value before reservation
+ * @count: signals number
+ */
+struct hl_cs_encaps_sig_handle {
+	struct kref refcount;
+	struct hl_device *hdev;
+	struct hl_hw_sob *hw_sob;
+	struct hl_ctx *ctx;
+	u64  cs_seq;
+	u32  id;
+	u32  q_idx;
+	u32  pre_sob_val;
+	u32  count;
+};
+
+/**
+ * struct hl_info_fw_err_info - firmware error information structure
+ * @err_type: The type of error detected (or reported).
+ * @event_mask: Pointer to the event mask to be modified with the detected error flag
+ *              (can be NULL)
+ * @event_id: The id of the event that reported the error
+ *            (applicable when err_type is HL_INFO_FW_REPORTED_ERR).
+ */
+struct hl_info_fw_err_info {
+	enum hl_info_fw_err_type err_type;
+	u64 *event_mask;
+	u16 event_id;
+};
+
+/*
+ * IOCTLs
+ */
+
+/**
+ * typedef hl_ioctl_t - typedef for ioctl function in the driver
+ * @hpriv: pointer to the FD's private data, which contains state of
+ *		user process
+ * @data: pointer to the input/output arguments structure of the IOCTL
+ *
+ * Return: 0 for success, negative value for error
+ */
+typedef int hl_ioctl_t(struct hl_fpriv *hpriv, void *data);
+
+/**
+ * struct hl_ioctl_desc - describes an IOCTL entry of the driver.
+ * @cmd: the IOCTL code as created by the kernel macros.
+ * @func: pointer to the driver's function that should be called for this IOCTL.
+ */
+struct hl_ioctl_desc {
+	unsigned int cmd;
+	hl_ioctl_t *func;
+};
+
+/*
+ * Kernel module functions that can be accessed by entire module
+ */
+
+/**
+ * hl_get_sg_info() - get number of pages and the DMA address from SG list.
+ * @sg: the SG list.
+ * @dma_addr: pointer to DMA address to return.
+ *
+ * Calculate the number of consecutive pages described by the SG list. Take the
+ * offset of the address in the first page, add to it the length and round it up
+ * to the number of needed pages.
+ */
+static inline u32 hl_get_sg_info(struct scatterlist *sg, dma_addr_t *dma_addr)
+{
+	*dma_addr = sg_dma_address(sg);
+
+	return ((((*dma_addr) & (PAGE_SIZE - 1)) + sg_dma_len(sg)) +
+			(PAGE_SIZE - 1)) >> PAGE_SHIFT;
+}
+
+/**
+ * hl_mem_area_inside_range() - Checks whether address+size are inside a range.
+ * @address: The start address of the area we want to validate.
+ * @size: The size in bytes of the area we want to validate.
+ * @range_start_address: The start address of the valid range.
+ * @range_end_address: The end address of the valid range.
+ *
+ * Return: true if the area is inside the valid range, false otherwise.
+ */
+static inline bool hl_mem_area_inside_range(u64 address, u64 size,
+				u64 range_start_address, u64 range_end_address)
+{
+	u64 end_address = address + size;
+
+	if ((address >= range_start_address) &&
+			(end_address <= range_end_address) &&
+			(end_address > address))
+		return true;
+
+	return false;
+}
+
+static inline struct hl_device *to_hl_device(struct drm_device *ddev)
+{
+	return container_of(ddev, struct hl_device, drm);
+}
+
+/**
+ * hl_mem_area_crosses_range() - Checks whether address+size crossing a range.
+ * @address: The start address of the area we want to validate.
+ * @size: The size in bytes of the area we want to validate.
+ * @range_start_address: The start address of the valid range.
+ * @range_end_address: The end address of the valid range.
+ *
+ * Return: true if the area overlaps part or all of the valid range,
+ *		false otherwise.
+ */
+static inline bool hl_mem_area_crosses_range(u64 address, u32 size,
+				u64 range_start_address, u64 range_end_address)
+{
+	u64 end_address = address + size - 1;
+
+	return ((address <= range_end_address) && (range_start_address <= end_address));
+}
+
+uint64_t hl_set_dram_bar_default(struct hl_device *hdev, u64 addr);
+void *hl_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, size_t size, dma_addr_t *dma_handle);
+void hl_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size, void *vaddr);
+void *hl_asic_dma_alloc_coherent_caller(struct hl_device *hdev, size_t size, dma_addr_t *dma_handle,
+					gfp_t flag, const char *caller);
+void hl_asic_dma_free_coherent_caller(struct hl_device *hdev, size_t size, void *cpu_addr,
+					dma_addr_t dma_handle, const char *caller);
+void *hl_asic_dma_pool_zalloc_caller(struct hl_device *hdev, size_t size, gfp_t mem_flags,
+					dma_addr_t *dma_handle, const char *caller);
+void hl_asic_dma_pool_free_caller(struct hl_device *hdev, void *vaddr, dma_addr_t dma_addr,
+					const char *caller);
+int hl_dma_map_sgtable_caller(struct hl_device *hdev, struct sg_table *sgt,
+				enum dma_data_direction dir, const char *caller);
+void hl_dma_unmap_sgtable_caller(struct hl_device *hdev, struct sg_table *sgt,
+					enum dma_data_direction dir, const char *caller);
+int hl_asic_dma_map_sgtable(struct hl_device *hdev, struct sg_table *sgt,
+				enum dma_data_direction dir);
+void hl_asic_dma_unmap_sgtable(struct hl_device *hdev, struct sg_table *sgt,
+				enum dma_data_direction dir);
+int hl_access_sram_dram_region(struct hl_device *hdev, u64 addr, u64 *val,
+	enum debugfs_access_type acc_type, enum pci_region region_type, bool set_dram_bar);
+int hl_access_cfg_region(struct hl_device *hdev, u64 addr, u64 *val,
+	enum debugfs_access_type acc_type);
+int hl_access_dev_mem(struct hl_device *hdev, enum pci_region region_type,
+			u64 addr, u64 *val, enum debugfs_access_type acc_type);
+
+int hl_mmap(struct file *filp, struct vm_area_struct *vma);
+
+int hl_device_open(struct drm_device *drm, struct drm_file *file_priv);
+void hl_device_release(struct drm_device *ddev, struct drm_file *file_priv);
+
+int hl_device_open_ctrl(struct inode *inode, struct file *filp);
+bool hl_device_operational(struct hl_device *hdev,
+		enum hl_device_status *status);
+bool hl_ctrl_device_operational(struct hl_device *hdev,
+		enum hl_device_status *status);
+enum hl_device_status hl_device_status(struct hl_device *hdev);
+int hl_device_set_debug_mode(struct hl_device *hdev, struct hl_ctx *ctx, bool enable);
+int hl_hw_queues_create(struct hl_device *hdev);
+void hl_hw_queues_destroy(struct hl_device *hdev);
+int hl_hw_queue_send_cb_no_cmpl(struct hl_device *hdev, u32 hw_queue_id,
+		u32 cb_size, u64 cb_ptr);
+void hl_hw_queue_submit_bd(struct hl_device *hdev, struct hl_hw_queue *q,
+		u32 ctl, u32 len, u64 ptr);
+int hl_hw_queue_schedule_cs(struct hl_cs *cs);
+u32 hl_hw_queue_add_ptr(u32 ptr, u16 val);
+void hl_hw_queue_inc_ci_kernel(struct hl_device *hdev, u32 hw_queue_id);
+void hl_hw_queue_update_ci(struct hl_cs *cs);
+void hl_hw_queue_reset(struct hl_device *hdev, bool hard_reset);
+
+#define hl_queue_inc_ptr(p)		hl_hw_queue_add_ptr(p, 1)
+#define hl_pi_2_offset(pi)		((pi) & (HL_QUEUE_LENGTH - 1))
+
+int hl_cq_init(struct hl_device *hdev, struct hl_cq *q, u32 hw_queue_id);
+void hl_cq_fini(struct hl_device *hdev, struct hl_cq *q);
+int hl_eq_init(struct hl_device *hdev, struct hl_eq *q);
+void hl_eq_fini(struct hl_device *hdev, struct hl_eq *q);
+void hl_cq_reset(struct hl_device *hdev, struct hl_cq *q);
+void hl_eq_reset(struct hl_device *hdev, struct hl_eq *q);
+void hl_eq_dump(struct hl_device *hdev, struct hl_eq *q);
+irqreturn_t hl_irq_handler_cq(int irq, void *arg);
+irqreturn_t hl_irq_handler_eq(int irq, void *arg);
+irqreturn_t hl_irq_handler_dec_abnrm(int irq, void *arg);
+irqreturn_t hl_irq_user_interrupt_handler(int irq, void *arg);
+irqreturn_t hl_irq_user_interrupt_thread_handler(int irq, void *arg);
+irqreturn_t hl_irq_eq_error_interrupt_thread_handler(int irq, void *arg);
+u32 hl_cq_inc_ptr(u32 ptr);
+
+int hl_asid_init(struct hl_device *hdev);
+void hl_asid_fini(struct hl_device *hdev);
+unsigned long hl_asid_alloc(struct hl_device *hdev);
+void hl_asid_free(struct hl_device *hdev, unsigned long asid);
+
+int hl_ctx_create(struct hl_device *hdev, struct hl_fpriv *hpriv);
+void hl_ctx_free(struct hl_device *hdev, struct hl_ctx *ctx);
+int hl_ctx_init(struct hl_device *hdev, struct hl_ctx *ctx, bool is_kernel_ctx);
+void hl_ctx_do_release(struct kref *ref);
+void hl_ctx_get(struct hl_ctx *ctx);
+int hl_ctx_put(struct hl_ctx *ctx);
+struct hl_ctx *hl_get_compute_ctx(struct hl_device *hdev);
+struct hl_fence *hl_ctx_get_fence(struct hl_ctx *ctx, u64 seq);
+int hl_ctx_get_fences(struct hl_ctx *ctx, u64 *seq_arr,
+				struct hl_fence **fence, u32 arr_len);
+void hl_ctx_mgr_init(struct hl_ctx_mgr *mgr);
+void hl_ctx_mgr_fini(struct hl_device *hdev, struct hl_ctx_mgr *mgr);
+
+int hl_device_init(struct hl_device *hdev);
+void hl_device_fini(struct hl_device *hdev);
+int hl_device_suspend(struct hl_device *hdev);
+int hl_device_resume(struct hl_device *hdev);
+int hl_device_reset(struct hl_device *hdev, u32 flags);
+int hl_device_cond_reset(struct hl_device *hdev, u32 flags, u64 event_mask);
+void hl_hpriv_get(struct hl_fpriv *hpriv);
+int hl_hpriv_put(struct hl_fpriv *hpriv);
+int hl_device_utilization(struct hl_device *hdev, u32 *utilization);
+
+int hl_build_hwmon_channel_info(struct hl_device *hdev,
+		struct cpucp_sensor *sensors_arr);
+
+void hl_notifier_event_send_all(struct hl_device *hdev, u64 event_mask);
+
+int hl_sysfs_init(struct hl_device *hdev);
+void hl_sysfs_fini(struct hl_device *hdev);
+
+int hl_hwmon_init(struct hl_device *hdev);
+void hl_hwmon_fini(struct hl_device *hdev);
+void hl_hwmon_release_resources(struct hl_device *hdev);
+
+int hl_cb_create(struct hl_device *hdev, struct hl_mem_mgr *mmg,
+			struct hl_ctx *ctx, u32 cb_size, bool internal_cb,
+			bool map_cb, u64 *handle);
+int hl_cb_destroy(struct hl_mem_mgr *mmg, u64 cb_handle);
+int hl_hw_block_mmap(struct hl_fpriv *hpriv, struct vm_area_struct *vma);
+struct hl_cb *hl_cb_get(struct hl_mem_mgr *mmg, u64 handle);
+void hl_cb_put(struct hl_cb *cb);
+struct hl_cb *hl_cb_kernel_create(struct hl_device *hdev, u32 cb_size,
+					bool internal_cb);
+int hl_cb_pool_init(struct hl_device *hdev);
+int hl_cb_pool_fini(struct hl_device *hdev);
+int hl_cb_va_pool_init(struct hl_ctx *ctx);
+void hl_cb_va_pool_fini(struct hl_ctx *ctx);
+
+void hl_cs_rollback_all(struct hl_device *hdev, bool skip_wq_flush);
+struct hl_cs_job *hl_cs_allocate_job(struct hl_device *hdev,
+		enum hl_queue_type queue_type, bool is_kernel_allocated_cb);
+void hl_sob_reset_error(struct kref *ref);
+int hl_gen_sob_mask(u16 sob_base, u8 sob_mask, u8 *mask);
+void hl_fence_put(struct hl_fence *fence);
+void hl_fences_put(struct hl_fence **fence, int len);
+void hl_fence_get(struct hl_fence *fence);
+void cs_get(struct hl_cs *cs);
+bool cs_needs_completion(struct hl_cs *cs);
+bool cs_needs_timeout(struct hl_cs *cs);
+bool is_staged_cs_last_exists(struct hl_device *hdev, struct hl_cs *cs);
+struct hl_cs *hl_staged_cs_find_first(struct hl_device *hdev, u64 cs_seq);
+void hl_multi_cs_completion_init(struct hl_device *hdev);
+u32 hl_get_active_cs_num(struct hl_device *hdev);
+
+void goya_set_asic_funcs(struct hl_device *hdev);
+void gaudi_set_asic_funcs(struct hl_device *hdev);
+void gaudi2_set_asic_funcs(struct hl_device *hdev);
+
+int hl_vm_ctx_init(struct hl_ctx *ctx);
+void hl_vm_ctx_fini(struct hl_ctx *ctx);
+
+int hl_vm_init(struct hl_device *hdev);
+void hl_vm_fini(struct hl_device *hdev);
+
+void hl_hw_block_mem_init(struct hl_ctx *ctx);
+void hl_hw_block_mem_fini(struct hl_ctx *ctx);
+
+u64 hl_reserve_va_block(struct hl_device *hdev, struct hl_ctx *ctx,
+		enum hl_va_range_type type, u64 size, u32 alignment);
+int hl_unreserve_va_block(struct hl_device *hdev, struct hl_ctx *ctx,
+		u64 start_addr, u64 size);
+int hl_pin_host_memory(struct hl_device *hdev, u64 addr, u64 size,
+			struct hl_userptr *userptr);
+void hl_unpin_host_memory(struct hl_device *hdev, struct hl_userptr *userptr);
+void hl_userptr_delete_list(struct hl_device *hdev,
+				struct list_head *userptr_list);
+bool hl_userptr_is_pinned(struct hl_device *hdev, u64 addr, u32 size,
+				struct list_head *userptr_list,
+				struct hl_userptr **userptr);
+
+int hl_mmu_init(struct hl_device *hdev);
+void hl_mmu_fini(struct hl_device *hdev);
+int hl_mmu_ctx_init(struct hl_ctx *ctx);
+void hl_mmu_ctx_fini(struct hl_ctx *ctx);
+int hl_mmu_map_page(struct hl_ctx *ctx, u64 virt_addr, u64 phys_addr,
+		u32 page_size, bool flush_pte);
+int hl_mmu_get_real_page_size(struct hl_device *hdev, struct hl_mmu_properties *mmu_prop,
+				u32 page_size, u32 *real_page_size, bool is_dram_addr);
+int hl_mmu_unmap_page(struct hl_ctx *ctx, u64 virt_addr, u32 page_size,
+		bool flush_pte);
+int hl_mmu_map_contiguous(struct hl_ctx *ctx, u64 virt_addr,
+					u64 phys_addr, u32 size);
+int hl_mmu_unmap_contiguous(struct hl_ctx *ctx, u64 virt_addr, u32 size);
+int hl_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard, u32 flags);
+int hl_mmu_invalidate_cache_range(struct hl_device *hdev, bool is_hard,
+					u32 flags, u32 asid, u64 va, u64 size);
+int hl_mmu_prefetch_cache_range(struct hl_ctx *ctx, u32 flags, u32 asid, u64 va, u64 size);
+u64 hl_mmu_get_next_hop_addr(struct hl_ctx *ctx, u64 curr_pte);
+u64 hl_mmu_get_hop_pte_phys_addr(struct hl_ctx *ctx, struct hl_mmu_properties *mmu_prop,
+					u8 hop_idx, u64 hop_addr, u64 virt_addr);
+void hl_mmu_hr_flush(struct hl_ctx *ctx);
+int hl_mmu_hr_init(struct hl_device *hdev, struct hl_mmu_hr_priv *hr_priv, u32 hop_table_size,
+			u64 pgt_size);
+void hl_mmu_hr_fini(struct hl_device *hdev, struct hl_mmu_hr_priv *hr_priv, u32 hop_table_size);
+void hl_mmu_hr_free_hop_remove_pgt(struct pgt_info *pgt_info, struct hl_mmu_hr_priv *hr_priv,
+				u32 hop_table_size);
+u64 hl_mmu_hr_pte_phys_to_virt(struct hl_ctx *ctx, struct pgt_info *pgt, u64 phys_pte_addr,
+							u32 hop_table_size);
+void hl_mmu_hr_write_pte(struct hl_ctx *ctx, struct pgt_info *pgt_info, u64 phys_pte_addr,
+							u64 val, u32 hop_table_size);
+void hl_mmu_hr_clear_pte(struct hl_ctx *ctx, struct pgt_info *pgt_info, u64 phys_pte_addr,
+							u32 hop_table_size);
+int hl_mmu_hr_put_pte(struct hl_ctx *ctx, struct pgt_info *pgt_info, struct hl_mmu_hr_priv *hr_priv,
+							u32 hop_table_size);
+void hl_mmu_hr_get_pte(struct hl_ctx *ctx, struct hl_hr_mmu_funcs *hr_func, u64 phys_hop_addr);
+struct pgt_info *hl_mmu_hr_get_next_hop_pgt_info(struct hl_ctx *ctx,
+							struct hl_hr_mmu_funcs *hr_func,
+							u64 curr_pte);
+struct pgt_info *hl_mmu_hr_alloc_hop(struct hl_ctx *ctx, struct hl_mmu_hr_priv *hr_priv,
+							struct hl_hr_mmu_funcs *hr_func,
+							struct hl_mmu_properties *mmu_prop);
+struct pgt_info *hl_mmu_hr_get_alloc_next_hop(struct hl_ctx *ctx,
+							struct hl_mmu_hr_priv *hr_priv,
+							struct hl_hr_mmu_funcs *hr_func,
+							struct hl_mmu_properties *mmu_prop,
+							u64 curr_pte, bool *is_new_hop);
+int hl_mmu_hr_get_tlb_info(struct hl_ctx *ctx, u64 virt_addr, struct hl_mmu_hop_info *hops,
+							struct hl_hr_mmu_funcs *hr_func);
+int hl_mmu_if_set_funcs(struct hl_device *hdev);
+void hl_mmu_v1_set_funcs(struct hl_device *hdev, struct hl_mmu_funcs *mmu);
+void hl_mmu_v2_set_funcs(struct hl_device *hdev, struct hl_mmu_funcs *mmu);
+void hl_mmu_v2_hr_set_funcs(struct hl_device *hdev, struct hl_mmu_funcs *mmu);
+int hl_mmu_va_to_pa(struct hl_ctx *ctx, u64 virt_addr, u64 *phys_addr);
+int hl_mmu_get_tlb_info(struct hl_ctx *ctx, u64 virt_addr,
+			struct hl_mmu_hop_info *hops);
+u64 hl_mmu_scramble_addr(struct hl_device *hdev, u64 addr);
+u64 hl_mmu_descramble_addr(struct hl_device *hdev, u64 addr);
+bool hl_is_dram_va(struct hl_device *hdev, u64 virt_addr);
+struct pgt_info *hl_mmu_dr_get_pgt_info(struct hl_ctx *ctx, u64 hop_addr);
+void hl_mmu_dr_free_hop(struct hl_ctx *ctx, u64 hop_addr);
+void hl_mmu_dr_free_pgt_node(struct hl_ctx *ctx, struct pgt_info *pgt_info);
+u64 hl_mmu_dr_get_phys_hop0_addr(struct hl_ctx *ctx);
+u64 hl_mmu_dr_get_hop0_addr(struct hl_ctx *ctx);
+void hl_mmu_dr_write_pte(struct hl_ctx *ctx, u64 shadow_pte_addr, u64 val);
+void hl_mmu_dr_write_final_pte(struct hl_ctx *ctx, u64 shadow_pte_addr, u64 val);
+void hl_mmu_dr_clear_pte(struct hl_ctx *ctx, u64 pte_addr);
+u64 hl_mmu_dr_get_phys_addr(struct hl_ctx *ctx, u64 shadow_addr);
+void hl_mmu_dr_get_pte(struct hl_ctx *ctx, u64 hop_addr);
+int hl_mmu_dr_put_pte(struct hl_ctx *ctx, u64 hop_addr);
+u64 hl_mmu_dr_get_alloc_next_hop_addr(struct hl_ctx *ctx, u64 curr_pte, bool *is_new_hop);
+u64 hl_mmu_dr_alloc_hop(struct hl_ctx *ctx);
+void hl_mmu_dr_flush(struct hl_ctx *ctx);
+int hl_mmu_dr_init(struct hl_device *hdev);
+void hl_mmu_dr_fini(struct hl_device *hdev);
+
+int hl_fw_version_cmp(struct hl_device *hdev, u32 major, u32 minor, u32 subminor);
+int hl_fw_load_fw_to_device(struct hl_device *hdev, const char *fw_name,
+				void __iomem *dst, u32 src_offset, u32 size);
+int hl_fw_send_pci_access_msg(struct hl_device *hdev, u32 opcode, u64 value);
+int hl_fw_send_cpu_message(struct hl_device *hdev, u32 hw_queue_id, u32 *msg,
+				u16 len, u32 timeout, u64 *result);
+int hl_fw_unmask_irq(struct hl_device *hdev, u16 event_type);
+int hl_fw_unmask_irq_arr(struct hl_device *hdev, const u32 *irq_arr,
+		size_t irq_arr_size);
+int hl_fw_test_cpu_queue(struct hl_device *hdev);
+void *hl_fw_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, size_t size,
+						dma_addr_t *dma_handle);
+void hl_fw_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size,
+					void *vaddr);
+int hl_fw_send_heartbeat(struct hl_device *hdev);
+int hl_fw_cpucp_info_get(struct hl_device *hdev,
+				u32 sts_boot_dev_sts0_reg,
+				u32 sts_boot_dev_sts1_reg, u32 boot_err0_reg,
+				u32 boot_err1_reg);
+int hl_fw_cpucp_handshake(struct hl_device *hdev,
+				u32 sts_boot_dev_sts0_reg,
+				u32 sts_boot_dev_sts1_reg, u32 boot_err0_reg,
+				u32 boot_err1_reg);
+int hl_fw_get_eeprom_data(struct hl_device *hdev, void *data, size_t max_size);
+int hl_fw_get_monitor_dump(struct hl_device *hdev, void *data);
+int hl_fw_cpucp_pci_counters_get(struct hl_device *hdev,
+		struct hl_info_pci_counters *counters);
+int hl_fw_cpucp_total_energy_get(struct hl_device *hdev,
+			u64 *total_energy);
+int get_used_pll_index(struct hl_device *hdev, u32 input_pll_index,
+						enum pll_index *pll_index);
+int hl_fw_cpucp_pll_info_get(struct hl_device *hdev, u32 pll_index,
+		u16 *pll_freq_arr);
+int hl_fw_cpucp_power_get(struct hl_device *hdev, u64 *power);
+void hl_fw_ask_hard_reset_without_linux(struct hl_device *hdev);
+void hl_fw_ask_halt_machine_without_linux(struct hl_device *hdev);
+int hl_fw_init_cpu(struct hl_device *hdev);
+int hl_fw_wait_preboot_ready(struct hl_device *hdev);
+int hl_fw_read_preboot_status(struct hl_device *hdev);
+int hl_fw_dynamic_send_protocol_cmd(struct hl_device *hdev,
+				struct fw_load_mgr *fw_loader,
+				enum comms_cmd cmd, unsigned int size,
+				bool wait_ok, u32 timeout);
+int hl_fw_dram_replaced_row_get(struct hl_device *hdev,
+				struct cpucp_hbm_row_info *info);
+int hl_fw_dram_pending_row_get(struct hl_device *hdev, u32 *pend_rows_num);
+int hl_fw_cpucp_engine_core_asid_set(struct hl_device *hdev, u32 asid);
+int hl_fw_send_device_activity(struct hl_device *hdev, bool open);
+int hl_fw_send_soft_reset(struct hl_device *hdev);
+int hl_pci_bars_map(struct hl_device *hdev, const char * const name[3],
+			bool is_wc[3]);
+int hl_pci_elbi_read(struct hl_device *hdev, u64 addr, u32 *data);
+int hl_pci_iatu_write(struct hl_device *hdev, u32 addr, u32 data);
+int hl_pci_set_inbound_region(struct hl_device *hdev, u8 region,
+		struct hl_inbound_pci_region *pci_region);
+int hl_pci_set_outbound_region(struct hl_device *hdev,
+		struct hl_outbound_pci_region *pci_region);
+enum pci_region hl_get_pci_memory_region(struct hl_device *hdev, u64 addr);
+int hl_pci_init(struct hl_device *hdev);
+void hl_pci_fini(struct hl_device *hdev);
+
+long hl_fw_get_frequency(struct hl_device *hdev, u32 pll_index, bool curr);
+void hl_fw_set_frequency(struct hl_device *hdev, u32 pll_index, u64 freq);
+int hl_get_temperature(struct hl_device *hdev, int sensor_index, u32 attr, long *value);
+int hl_set_temperature(struct hl_device *hdev, int sensor_index, u32 attr, long value);
+int hl_get_voltage(struct hl_device *hdev, int sensor_index, u32 attr, long *value);
+int hl_get_current(struct hl_device *hdev, int sensor_index, u32 attr, long *value);
+int hl_get_fan_speed(struct hl_device *hdev, int sensor_index, u32 attr, long *value);
+int hl_get_pwm_info(struct hl_device *hdev, int sensor_index, u32 attr, long *value);
+void hl_set_pwm_info(struct hl_device *hdev, int sensor_index, u32 attr, long value);
+long hl_fw_get_max_power(struct hl_device *hdev);
+void hl_fw_set_max_power(struct hl_device *hdev);
+int hl_fw_get_sec_attest_info(struct hl_device *hdev, struct cpucp_sec_attest_info *sec_attest_info,
+				u32 nonce);
+int hl_fw_get_dev_info_signed(struct hl_device *hdev,
+			      struct cpucp_dev_info_signed *dev_info_signed, u32 nonce);
+int hl_set_voltage(struct hl_device *hdev, int sensor_index, u32 attr, long value);
+int hl_set_current(struct hl_device *hdev, int sensor_index, u32 attr, long value);
+int hl_set_power(struct hl_device *hdev, int sensor_index, u32 attr, long value);
+int hl_get_power(struct hl_device *hdev, int sensor_index, u32 attr, long *value);
+int hl_fw_get_clk_rate(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk);
+void hl_fw_set_pll_profile(struct hl_device *hdev);
+void hl_sysfs_add_dev_clk_attr(struct hl_device *hdev, struct attribute_group *dev_clk_attr_grp);
+void hl_sysfs_add_dev_vrm_attr(struct hl_device *hdev, struct attribute_group *dev_vrm_attr_grp);
+int hl_fw_send_generic_request(struct hl_device *hdev, enum hl_passthrough_type sub_opcode,
+						dma_addr_t buff, u32 *size);
+
+void hw_sob_get(struct hl_hw_sob *hw_sob);
+void hw_sob_put(struct hl_hw_sob *hw_sob);
+void hl_encaps_release_handle_and_put_ctx(struct kref *ref);
+void hl_encaps_release_handle_and_put_sob_ctx(struct kref *ref);
+void hl_hw_queue_encaps_sig_set_sob_info(struct hl_device *hdev,
+			struct hl_cs *cs, struct hl_cs_job *job,
+			struct hl_cs_compl *cs_cmpl);
+
+int hl_dec_init(struct hl_device *hdev);
+void hl_dec_fini(struct hl_device *hdev);
+void hl_dec_ctx_fini(struct hl_ctx *ctx);
+
+void hl_release_pending_user_interrupts(struct hl_device *hdev);
+void hl_abort_waiting_for_cs_completions(struct hl_device *hdev);
+int hl_cs_signal_sob_wraparound_handler(struct hl_device *hdev, u32 q_idx,
+			struct hl_hw_sob **hw_sob, u32 count, bool encaps_sig);
+
+int hl_state_dump(struct hl_device *hdev);
+const char *hl_state_dump_get_sync_name(struct hl_device *hdev, u32 sync_id);
+const char *hl_state_dump_get_monitor_name(struct hl_device *hdev,
+					struct hl_mon_state_dump *mon);
+void hl_state_dump_free_sync_to_engine_map(struct hl_sync_to_engine_map *map);
+__printf(4, 5) int hl_snprintf_resize(char **buf, size_t *size, size_t *offset,
+					const char *format, ...);
+char *hl_format_as_binary(char *buf, size_t buf_len, u32 n);
+const char *hl_sync_engine_to_string(enum hl_sync_engine_type engine_type);
+
+void hl_mem_mgr_init(struct device *dev, struct hl_mem_mgr *mmg);
+void hl_mem_mgr_fini(struct hl_mem_mgr *mmg, struct hl_mem_mgr_fini_stats *stats);
+void hl_mem_mgr_idr_destroy(struct hl_mem_mgr *mmg);
+int hl_mem_mgr_mmap(struct hl_mem_mgr *mmg, struct vm_area_struct *vma,
+		    void *args);
+struct hl_mmap_mem_buf *hl_mmap_mem_buf_get(struct hl_mem_mgr *mmg,
+						   u64 handle);
+int hl_mmap_mem_buf_put_handle(struct hl_mem_mgr *mmg, u64 handle);
+int hl_mmap_mem_buf_put(struct hl_mmap_mem_buf *buf);
+struct hl_mmap_mem_buf *
+hl_mmap_mem_buf_alloc(struct hl_mem_mgr *mmg,
+		      struct hl_mmap_mem_buf_behavior *behavior, gfp_t gfp,
+		      void *args);
+__printf(2, 3) void hl_engine_data_sprintf(struct engines_data *e, const char *fmt, ...);
+void hl_capture_razwi(struct hl_device *hdev, u64 addr, u16 *engine_id, u16 num_of_engines,
+			u8 flags);
+void hl_handle_razwi(struct hl_device *hdev, u64 addr, u16 *engine_id, u16 num_of_engines,
+			u8 flags, u64 *event_mask);
+void hl_capture_page_fault(struct hl_device *hdev, u64 addr, u16 eng_id, bool is_pmmu);
+void hl_handle_page_fault(struct hl_device *hdev, u64 addr, u16 eng_id, bool is_pmmu,
+				u64 *event_mask);
+void hl_handle_critical_hw_err(struct hl_device *hdev, u16 event_id, u64 *event_mask);
+void hl_handle_fw_err(struct hl_device *hdev, struct hl_info_fw_err_info *info);
+void hl_capture_engine_err(struct hl_device *hdev, u16 engine_id, u16 error_count);
+void hl_enable_err_info_capture(struct hl_error_info *captured_err_info);
+void hl_init_cpu_for_irq(struct hl_device *hdev);
+void hl_set_irq_affinity(struct hl_device *hdev, int irq);
+void hl_eq_heartbeat_event_handle(struct hl_device *hdev);
+void hl_handle_clk_change_event(struct hl_device *hdev, u16 event_type, u64 *event_mask);
+void hl_eq_cpld_shutdown_event_handle(struct hl_device *hdev, u16 event_id, u64 *event_mask);
+
+#ifdef CONFIG_DEBUG_FS
+
+int hl_debugfs_device_init(struct hl_device *hdev);
+void hl_debugfs_device_fini(struct hl_device *hdev);
+void hl_debugfs_add_device(struct hl_device *hdev);
+void hl_debugfs_add_file(struct hl_fpriv *hpriv);
+void hl_debugfs_remove_file(struct hl_fpriv *hpriv);
+void hl_debugfs_add_cb(struct hl_cb *cb);
+void hl_debugfs_remove_cb(struct hl_cb *cb);
+void hl_debugfs_add_cs(struct hl_cs *cs);
+void hl_debugfs_remove_cs(struct hl_cs *cs);
+void hl_debugfs_add_job(struct hl_device *hdev, struct hl_cs_job *job);
+void hl_debugfs_remove_job(struct hl_device *hdev, struct hl_cs_job *job);
+void hl_debugfs_add_userptr(struct hl_device *hdev, struct hl_userptr *userptr);
+void hl_debugfs_remove_userptr(struct hl_device *hdev,
+				struct hl_userptr *userptr);
+void hl_debugfs_add_ctx_mem_hash(struct hl_device *hdev, struct hl_ctx *ctx);
+void hl_debugfs_remove_ctx_mem_hash(struct hl_device *hdev, struct hl_ctx *ctx);
+void hl_debugfs_set_state_dump(struct hl_device *hdev, char *data,
+					unsigned long length);
+void hl_debugfs_cfg_access_history_dump(struct hl_device *hdev);
+
+#else
+
+static inline int hl_debugfs_device_init(struct hl_device *hdev)
+{
+	return 0;
+}
+
+static inline void hl_debugfs_device_fini(struct hl_device *hdev)
+{
+}
+
+static inline void hl_debugfs_add_device(struct hl_device *hdev)
+{
+}
+
+static inline void hl_debugfs_add_file(struct hl_fpriv *hpriv)
+{
+}
+
+static inline void hl_debugfs_remove_file(struct hl_fpriv *hpriv)
+{
+}
+
+static inline void hl_debugfs_add_cb(struct hl_cb *cb)
+{
+}
+
+static inline void hl_debugfs_remove_cb(struct hl_cb *cb)
+{
+}
+
+static inline void hl_debugfs_add_cs(struct hl_cs *cs)
+{
+}
+
+static inline void hl_debugfs_remove_cs(struct hl_cs *cs)
+{
+}
+
+static inline void hl_debugfs_add_job(struct hl_device *hdev,
+					struct hl_cs_job *job)
+{
+}
+
+static inline void hl_debugfs_remove_job(struct hl_device *hdev,
+					struct hl_cs_job *job)
+{
+}
+
+static inline void hl_debugfs_add_userptr(struct hl_device *hdev,
+					struct hl_userptr *userptr)
+{
+}
+
+static inline void hl_debugfs_remove_userptr(struct hl_device *hdev,
+					struct hl_userptr *userptr)
+{
+}
+
+static inline void hl_debugfs_add_ctx_mem_hash(struct hl_device *hdev,
+					struct hl_ctx *ctx)
+{
+}
+
+static inline void hl_debugfs_remove_ctx_mem_hash(struct hl_device *hdev,
+					struct hl_ctx *ctx)
+{
+}
+
+static inline void hl_debugfs_set_state_dump(struct hl_device *hdev,
+					char *data, unsigned long length)
+{
+}
+
+static inline void hl_debugfs_cfg_access_history_dump(struct hl_device *hdev)
+{
+}
+
+#endif
+
+/* Security */
+int hl_unsecure_register(struct hl_device *hdev, u32 mm_reg_addr, int offset,
+		const u32 pb_blocks[], struct hl_block_glbl_sec sgs_array[],
+		int array_size);
+int hl_unsecure_registers(struct hl_device *hdev, const u32 mm_reg_array[],
+		int mm_array_size, int offset, const u32 pb_blocks[],
+		struct hl_block_glbl_sec sgs_array[], int blocks_array_size);
+void hl_config_glbl_sec(struct hl_device *hdev, const u32 pb_blocks[],
+		struct hl_block_glbl_sec sgs_array[], u32 block_offset,
+		int array_size);
+void hl_secure_block(struct hl_device *hdev,
+		struct hl_block_glbl_sec sgs_array[], int array_size);
+int hl_init_pb_with_mask(struct hl_device *hdev, u32 num_dcores,
+		u32 dcore_offset, u32 num_instances, u32 instance_offset,
+		const u32 pb_blocks[], u32 blocks_array_size,
+		const u32 *regs_array, u32 regs_array_size, u64 mask);
+int hl_init_pb(struct hl_device *hdev, u32 num_dcores, u32 dcore_offset,
+		u32 num_instances, u32 instance_offset,
+		const u32 pb_blocks[], u32 blocks_array_size,
+		const u32 *regs_array, u32 regs_array_size);
+int hl_init_pb_ranges_with_mask(struct hl_device *hdev, u32 num_dcores,
+		u32 dcore_offset, u32 num_instances, u32 instance_offset,
+		const u32 pb_blocks[], u32 blocks_array_size,
+		const struct range *regs_range_array, u32 regs_range_array_size,
+		u64 mask);
+int hl_init_pb_ranges(struct hl_device *hdev, u32 num_dcores,
+		u32 dcore_offset, u32 num_instances, u32 instance_offset,
+		const u32 pb_blocks[], u32 blocks_array_size,
+		const struct range *regs_range_array,
+		u32 regs_range_array_size);
+int hl_init_pb_single_dcore(struct hl_device *hdev, u32 dcore_offset,
+		u32 num_instances, u32 instance_offset,
+		const u32 pb_blocks[], u32 blocks_array_size,
+		const u32 *regs_array, u32 regs_array_size);
+int hl_init_pb_ranges_single_dcore(struct hl_device *hdev, u32 dcore_offset,
+		u32 num_instances, u32 instance_offset,
+		const u32 pb_blocks[], u32 blocks_array_size,
+		const struct range *regs_range_array,
+		u32 regs_range_array_size);
+void hl_ack_pb(struct hl_device *hdev, u32 num_dcores, u32 dcore_offset,
+		u32 num_instances, u32 instance_offset,
+		const u32 pb_blocks[], u32 blocks_array_size);
+void hl_ack_pb_with_mask(struct hl_device *hdev, u32 num_dcores,
+		u32 dcore_offset, u32 num_instances, u32 instance_offset,
+		const u32 pb_blocks[], u32 blocks_array_size, u64 mask);
+void hl_ack_pb_single_dcore(struct hl_device *hdev, u32 dcore_offset,
+		u32 num_instances, u32 instance_offset,
+		const u32 pb_blocks[], u32 blocks_array_size);
+
+/* IOCTLs */
+long hl_ioctl_control(struct file *filep, unsigned int cmd, unsigned long arg);
+int hl_info_ioctl(struct drm_device *ddev, void *data, struct drm_file *file_priv);
+int hl_cb_ioctl(struct drm_device *ddev, void *data, struct drm_file *file_priv);
+int hl_cs_ioctl(struct drm_device *ddev, void *data, struct drm_file *file_priv);
+int hl_wait_ioctl(struct drm_device *ddev, void *data, struct drm_file *file_priv);
+int hl_mem_ioctl(struct drm_device *ddev, void *data, struct drm_file *file_priv);
+int hl_debug_ioctl(struct drm_device *ddev, void *data, struct drm_file *file_priv);
+
+#endif /* HABANALABSP_H_ */
diff --git a/drivers/accel/habanalabs/common/habanalabs_drv.c b/drivers/accel/habanalabs/common/habanalabs_drv.c
new file mode 100644
index 000000000000..0035748f3228
--- /dev/null
+++ b/drivers/accel/habanalabs/common/habanalabs_drv.c
@@ -0,0 +1,784 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Copyright 2016-2021 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+#define pr_fmt(fmt)		"habanalabs: " fmt
+
+#include "habanalabs.h"
+#include "../include/hw_ip/pci/pci_general.h"
+
+#include <linux/pci.h>
+#include <linux/module.h>
+#include <linux/vmalloc.h>
+#include <linux/version.h>
+
+#include <drm/drm_accel.h>
+#include <drm/drm_drv.h>
+#include <drm/drm_ioctl.h>
+
+#define CREATE_TRACE_POINTS
+#include <trace/events/habanalabs.h>
+
+#define HL_DRIVER_AUTHOR	"HabanaLabs Kernel Driver Team"
+
+#define HL_DRIVER_DESC		"Driver for HabanaLabs's AI Accelerators"
+
+MODULE_AUTHOR(HL_DRIVER_AUTHOR);
+MODULE_DESCRIPTION(HL_DRIVER_DESC);
+MODULE_LICENSE("GPL v2");
+
+static int hl_major;
+static DEFINE_IDR(hl_devs_idr);
+static DEFINE_MUTEX(hl_devs_idr_lock);
+
+#define HL_DEFAULT_TIMEOUT_LOCKED	30	/* 30 seconds */
+#define GAUDI_DEFAULT_TIMEOUT_LOCKED	600	/* 10 minutes */
+
+static int timeout_locked = HL_DEFAULT_TIMEOUT_LOCKED;
+static int reset_on_lockup = 1;
+static int memory_scrub;
+static ulong boot_error_status_mask = ULONG_MAX;
+
+module_param(timeout_locked, int, 0444);
+MODULE_PARM_DESC(timeout_locked,
+	"Device lockup timeout in seconds (0 = disabled, default 30s)");
+
+module_param(reset_on_lockup, int, 0444);
+MODULE_PARM_DESC(reset_on_lockup,
+	"Do device reset on lockup (0 = no, 1 = yes, default yes)");
+
+module_param(memory_scrub, int, 0444);
+MODULE_PARM_DESC(memory_scrub,
+	"Scrub device memory in various states (0 = no, 1 = yes, default no)");
+
+module_param(boot_error_status_mask, ulong, 0444);
+MODULE_PARM_DESC(boot_error_status_mask,
+	"Mask of the error status during device CPU boot (If bitX is cleared then error X is masked. Default all 1's)");
+
+#define PCI_IDS_GOYA			0x0001
+#define PCI_IDS_GAUDI			0x1000
+#define PCI_IDS_GAUDI_SEC		0x1010
+
+#define PCI_IDS_GAUDI2			0x1020
+
+static const struct pci_device_id ids[] = {
+	{ PCI_DEVICE(PCI_VENDOR_ID_HABANALABS, PCI_IDS_GOYA), },
+	{ PCI_DEVICE(PCI_VENDOR_ID_HABANALABS, PCI_IDS_GAUDI), },
+	{ PCI_DEVICE(PCI_VENDOR_ID_HABANALABS, PCI_IDS_GAUDI_SEC), },
+	{ PCI_DEVICE(PCI_VENDOR_ID_HABANALABS, PCI_IDS_GAUDI2), },
+	{ 0, }
+};
+MODULE_DEVICE_TABLE(pci, ids);
+
+static const struct drm_ioctl_desc hl_drm_ioctls[] = {
+	DRM_IOCTL_DEF_DRV(HL_INFO, hl_info_ioctl, 0),
+	DRM_IOCTL_DEF_DRV(HL_CB, hl_cb_ioctl, 0),
+	DRM_IOCTL_DEF_DRV(HL_CS, hl_cs_ioctl, 0),
+	DRM_IOCTL_DEF_DRV(HL_WAIT_CS, hl_wait_ioctl, 0),
+	DRM_IOCTL_DEF_DRV(HL_MEMORY, hl_mem_ioctl, 0),
+	DRM_IOCTL_DEF_DRV(HL_DEBUG, hl_debug_ioctl, 0),
+};
+
+static const struct file_operations hl_fops = {
+	.owner = THIS_MODULE,
+	.open = accel_open,
+	.release = drm_release,
+	.unlocked_ioctl = drm_ioctl,
+	.compat_ioctl = drm_compat_ioctl,
+	.llseek = noop_llseek,
+	.mmap = hl_mmap
+};
+
+static const struct drm_driver hl_driver = {
+	.driver_features = DRIVER_COMPUTE_ACCEL,
+
+	.name = HL_NAME,
+	.desc = HL_DRIVER_DESC,
+	.major = LINUX_VERSION_MAJOR,
+	.minor = LINUX_VERSION_PATCHLEVEL,
+	.patchlevel = LINUX_VERSION_SUBLEVEL,
+
+	.fops = &hl_fops,
+	.open = hl_device_open,
+	.postclose = hl_device_release,
+	.ioctls = hl_drm_ioctls,
+	.num_ioctls = ARRAY_SIZE(hl_drm_ioctls)
+};
+
+/*
+ * get_asic_type - translate device id to asic type
+ *
+ * @hdev: pointer to habanalabs device structure.
+ *
+ * Translate device id and revision id to asic type.
+ * In case of unidentified device, return -1
+ */
+static enum hl_asic_type get_asic_type(struct hl_device *hdev)
+{
+	struct pci_dev *pdev = hdev->pdev;
+	enum hl_asic_type asic_type = ASIC_INVALID;
+
+	switch (pdev->device) {
+	case PCI_IDS_GOYA:
+		asic_type = ASIC_GOYA;
+		break;
+	case PCI_IDS_GAUDI:
+		asic_type = ASIC_GAUDI;
+		break;
+	case PCI_IDS_GAUDI_SEC:
+		asic_type = ASIC_GAUDI_SEC;
+		break;
+	case PCI_IDS_GAUDI2:
+		switch (pdev->revision) {
+		case REV_ID_A:
+			asic_type = ASIC_GAUDI2;
+			break;
+		case REV_ID_B:
+			asic_type = ASIC_GAUDI2B;
+			break;
+		case REV_ID_C:
+			asic_type = ASIC_GAUDI2C;
+			break;
+		case REV_ID_D:
+			asic_type = ASIC_GAUDI2D;
+			break;
+		default:
+			break;
+		}
+		break;
+	default:
+		break;
+	}
+
+	return asic_type;
+}
+
+static bool is_asic_secured(enum hl_asic_type asic_type)
+{
+	switch (asic_type) {
+	case ASIC_GAUDI_SEC:
+		return true;
+	default:
+		return false;
+	}
+}
+
+/*
+ * hl_device_open() - open function for habanalabs device.
+ * @ddev: pointer to DRM device structure.
+ * @file: pointer to DRM file private data structure.
+ *
+ * Called when process opens an habanalabs device.
+ */
+int hl_device_open(struct drm_device *ddev, struct drm_file *file_priv)
+{
+	struct hl_device *hdev = to_hl_device(ddev);
+	enum hl_device_status status;
+	struct hl_fpriv *hpriv;
+	int rc;
+
+	hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL);
+	if (!hpriv)
+		return -ENOMEM;
+
+	hpriv->hdev = hdev;
+	mutex_init(&hpriv->notifier_event.lock);
+	mutex_init(&hpriv->restore_phase_mutex);
+	mutex_init(&hpriv->ctx_lock);
+	kref_init(&hpriv->refcount);
+
+	hl_ctx_mgr_init(&hpriv->ctx_mgr);
+	hl_mem_mgr_init(hpriv->hdev->dev, &hpriv->mem_mgr);
+
+	hpriv->taskpid = get_task_pid(current, PIDTYPE_PID);
+
+	mutex_lock(&hdev->fpriv_list_lock);
+
+	if (!hl_device_operational(hdev, &status)) {
+		dev_dbg_ratelimited(hdev->dev,
+			"Can't open %s because it is %s\n",
+			dev_name(hdev->dev), hdev->status[status]);
+
+		if (status == HL_DEVICE_STATUS_IN_RESET ||
+					status == HL_DEVICE_STATUS_IN_RESET_AFTER_DEVICE_RELEASE)
+			rc = -EAGAIN;
+		else
+			rc = -EPERM;
+
+		goto out_err;
+	}
+
+	if (hdev->is_in_dram_scrub) {
+		dev_dbg_ratelimited(hdev->dev,
+			"Can't open %s during dram scrub\n",
+			dev_name(hdev->dev));
+		rc = -EAGAIN;
+		goto out_err;
+	}
+
+	if (hdev->compute_ctx_in_release) {
+		dev_dbg_ratelimited(hdev->dev,
+			"Can't open %s because another user is still releasing it\n",
+			dev_name(hdev->dev));
+		rc = -EAGAIN;
+		goto out_err;
+	}
+
+	if (hdev->is_compute_ctx_active) {
+		dev_dbg_ratelimited(hdev->dev,
+			"Can't open %s because another user is working on it\n",
+			dev_name(hdev->dev));
+		rc = -EBUSY;
+		goto out_err;
+	}
+
+	rc = hl_ctx_create(hdev, hpriv);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to create context %d\n", rc);
+		goto out_err;
+	}
+
+	list_add(&hpriv->dev_node, &hdev->fpriv_list);
+	mutex_unlock(&hdev->fpriv_list_lock);
+
+	hdev->asic_funcs->send_device_activity(hdev, true);
+
+	hl_debugfs_add_file(hpriv);
+
+	hl_enable_err_info_capture(&hdev->captured_err_info);
+
+	hdev->open_counter++;
+	hdev->last_successful_open_jif = jiffies;
+	hdev->last_successful_open_ktime = ktime_get();
+
+	file_priv->driver_priv = hpriv;
+	hpriv->file_priv = file_priv;
+
+	return 0;
+
+out_err:
+	mutex_unlock(&hdev->fpriv_list_lock);
+	hl_mem_mgr_fini(&hpriv->mem_mgr, NULL);
+	hl_mem_mgr_idr_destroy(&hpriv->mem_mgr);
+	hl_ctx_mgr_fini(hpriv->hdev, &hpriv->ctx_mgr);
+	mutex_destroy(&hpriv->ctx_lock);
+	mutex_destroy(&hpriv->restore_phase_mutex);
+	mutex_destroy(&hpriv->notifier_event.lock);
+	put_pid(hpriv->taskpid);
+
+	kfree(hpriv);
+
+	return rc;
+}
+
+int hl_device_open_ctrl(struct inode *inode, struct file *filp)
+{
+	struct hl_device *hdev;
+	struct hl_fpriv *hpriv;
+	int rc;
+
+	mutex_lock(&hl_devs_idr_lock);
+	hdev = idr_find(&hl_devs_idr, iminor(inode));
+	mutex_unlock(&hl_devs_idr_lock);
+
+	if (!hdev) {
+		pr_err("Couldn't find device %d:%d\n",
+			imajor(inode), iminor(inode));
+		return -ENXIO;
+	}
+
+	hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL);
+	if (!hpriv)
+		return -ENOMEM;
+
+	/* Prevent other routines from reading partial hpriv data by
+	 * initializing hpriv fields before inserting it to the list
+	 */
+	hpriv->hdev = hdev;
+	filp->private_data = hpriv;
+
+	nonseekable_open(inode, filp);
+
+	hpriv->taskpid = get_task_pid(current, PIDTYPE_PID);
+
+	mutex_lock(&hdev->fpriv_ctrl_list_lock);
+
+	if (!hl_ctrl_device_operational(hdev, NULL)) {
+		dev_dbg_ratelimited(hdev->dev_ctrl,
+			"Can't open %s because it is disabled\n",
+			dev_name(hdev->dev_ctrl));
+		rc = -EPERM;
+		goto out_err;
+	}
+
+	list_add(&hpriv->dev_node, &hdev->fpriv_ctrl_list);
+	mutex_unlock(&hdev->fpriv_ctrl_list_lock);
+
+	return 0;
+
+out_err:
+	mutex_unlock(&hdev->fpriv_ctrl_list_lock);
+	filp->private_data = NULL;
+	put_pid(hpriv->taskpid);
+
+	kfree(hpriv);
+
+	return rc;
+}
+
+static void set_driver_behavior_per_device(struct hl_device *hdev)
+{
+	hdev->nic_ports_mask = 0;
+	hdev->fw_components = FW_TYPE_ALL_TYPES;
+	hdev->cpu_queues_enable = 1;
+	hdev->pldm = 0;
+	hdev->hard_reset_on_fw_events = 1;
+	hdev->bmc_enable = 1;
+	hdev->reset_on_preboot_fail = 1;
+	hdev->heartbeat = 1;
+}
+
+static void copy_kernel_module_params_to_device(struct hl_device *hdev)
+{
+	hdev->asic_prop.fw_security_enabled = is_asic_secured(hdev->asic_type);
+
+	hdev->major = hl_major;
+	hdev->memory_scrub = memory_scrub;
+	hdev->reset_on_lockup = reset_on_lockup;
+	hdev->boot_error_status_mask = boot_error_status_mask;
+}
+
+static void fixup_device_params_per_asic(struct hl_device *hdev, int timeout)
+{
+	switch (hdev->asic_type) {
+	case ASIC_GAUDI:
+	case ASIC_GAUDI_SEC:
+		/* If user didn't request a different timeout than the default one, we have
+		 * a different default timeout for Gaudi
+		 */
+		if (timeout == HL_DEFAULT_TIMEOUT_LOCKED)
+			hdev->timeout_jiffies = secs_to_jiffies(GAUDI_DEFAULT_TIMEOUT_LOCKED);
+
+		hdev->reset_upon_device_release = 0;
+		break;
+
+	case ASIC_GOYA:
+		hdev->reset_upon_device_release = 0;
+		break;
+
+	default:
+		hdev->reset_upon_device_release = 1;
+		break;
+	}
+}
+
+static int fixup_device_params(struct hl_device *hdev)
+{
+	int tmp_timeout;
+
+	tmp_timeout = timeout_locked;
+
+	hdev->fw_poll_interval_usec = HL_FW_STATUS_POLL_INTERVAL_USEC;
+	hdev->fw_comms_poll_interval_usec = HL_FW_STATUS_POLL_INTERVAL_USEC;
+
+	if (tmp_timeout)
+		hdev->timeout_jiffies = secs_to_jiffies(tmp_timeout);
+	else
+		hdev->timeout_jiffies = MAX_SCHEDULE_TIMEOUT;
+
+	hdev->stop_on_err = true;
+	hdev->reset_info.curr_reset_cause = HL_RESET_CAUSE_UNKNOWN;
+	hdev->reset_info.prev_reset_trigger = HL_RESET_TRIGGER_DEFAULT;
+
+	/* Enable only after the initialization of the device */
+	hdev->disabled = true;
+
+	if (!(hdev->fw_components & FW_TYPE_PREBOOT_CPU) &&
+			(hdev->fw_components & ~FW_TYPE_PREBOOT_CPU)) {
+		pr_err("Preboot must be set along with other components");
+		return -EINVAL;
+	}
+
+	/* If CPU queues not enabled, no way to do heartbeat */
+	if (!hdev->cpu_queues_enable)
+		hdev->heartbeat = 0;
+	fixup_device_params_per_asic(hdev, tmp_timeout);
+
+	return 0;
+}
+
+static int allocate_device_id(struct hl_device *hdev)
+{
+	int id;
+
+	mutex_lock(&hl_devs_idr_lock);
+	id = idr_alloc(&hl_devs_idr, hdev, 0, HL_MAX_MINORS, GFP_KERNEL);
+	mutex_unlock(&hl_devs_idr_lock);
+
+	if (id < 0) {
+		if (id == -ENOSPC)
+			pr_err("too many devices in the system\n");
+		return -EBUSY;
+	}
+
+	hdev->id = id;
+
+	/*
+	 * Firstly initialized with the internal device ID.
+	 * Will be updated later after the DRM device registration to hold the minor ID.
+	 */
+	hdev->cdev_idx = hdev->id;
+
+	return 0;
+}
+
+/**
+ * create_hdev - create habanalabs device instance
+ *
+ * @dev: will hold the pointer to the new habanalabs device structure
+ * @pdev: pointer to the pci device
+ *
+ * Allocate memory for habanalabs device and initialize basic fields
+ * Identify the ASIC type
+ * Allocate ID (minor) for the device (only for real devices)
+ */
+static int create_hdev(struct hl_device **dev, struct pci_dev *pdev)
+{
+	struct hl_device *hdev;
+	int rc;
+
+	*dev = NULL;
+
+	hdev = devm_drm_dev_alloc(&pdev->dev, &hl_driver, struct hl_device, drm);
+	if (IS_ERR(hdev))
+		return PTR_ERR(hdev);
+
+	hdev->dev = hdev->drm.dev;
+
+	/* Will be NULL in case of simulator device */
+	hdev->pdev = pdev;
+
+	/* Assign status description string */
+	strscpy(hdev->status[HL_DEVICE_STATUS_OPERATIONAL], "operational", HL_STR_MAX);
+	strscpy(hdev->status[HL_DEVICE_STATUS_IN_RESET], "in reset", HL_STR_MAX);
+	strscpy(hdev->status[HL_DEVICE_STATUS_MALFUNCTION], "disabled", HL_STR_MAX);
+	strscpy(hdev->status[HL_DEVICE_STATUS_NEEDS_RESET], "needs reset", HL_STR_MAX);
+	strscpy(hdev->status[HL_DEVICE_STATUS_IN_DEVICE_CREATION],
+				"in device creation", HL_STR_MAX);
+	strscpy(hdev->status[HL_DEVICE_STATUS_IN_RESET_AFTER_DEVICE_RELEASE],
+				"in reset after device release", HL_STR_MAX);
+
+
+	/* First, we must find out which ASIC are we handling. This is needed
+	 * to configure the behavior of the driver (kernel parameters)
+	 */
+	hdev->asic_type = get_asic_type(hdev);
+	if (hdev->asic_type == ASIC_INVALID) {
+		dev_err(&pdev->dev, "Unsupported ASIC\n");
+		rc = -ENODEV;
+		goto out_err;
+	}
+
+	copy_kernel_module_params_to_device(hdev);
+
+	set_driver_behavior_per_device(hdev);
+
+	fixup_device_params(hdev);
+
+	rc = allocate_device_id(hdev);
+	if (rc)
+		goto out_err;
+
+	*dev = hdev;
+
+	return 0;
+
+out_err:
+	return rc;
+}
+
+/*
+ * destroy_hdev - destroy habanalabs device instance
+ *
+ * @dev: pointer to the habanalabs device structure
+ *
+ */
+static void destroy_hdev(struct hl_device *hdev)
+{
+	/* Remove device from the device list */
+	mutex_lock(&hl_devs_idr_lock);
+	idr_remove(&hl_devs_idr, hdev->id);
+	mutex_unlock(&hl_devs_idr_lock);
+
+}
+
+static int hl_pmops_suspend(struct device *dev)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+
+	pr_debug("Going to suspend PCI device\n");
+
+	if (!hdev) {
+		pr_err("device pointer is NULL in suspend\n");
+		return 0;
+	}
+
+	return hl_device_suspend(hdev);
+}
+
+static int hl_pmops_resume(struct device *dev)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+
+	pr_debug("Going to resume PCI device\n");
+
+	if (!hdev) {
+		pr_err("device pointer is NULL in resume\n");
+		return 0;
+	}
+
+	return hl_device_resume(hdev);
+}
+
+/**
+ * hl_pci_probe - probe PCI habanalabs devices
+ *
+ * @pdev: pointer to pci device
+ * @id: pointer to pci device id structure
+ *
+ * Standard PCI probe function for habanalabs device.
+ * Create a new habanalabs device and initialize it according to the
+ * device's type
+ */
+static int hl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+{
+	struct hl_device *hdev;
+	int rc;
+
+	dev_info(&pdev->dev, HL_NAME
+		 " device found [%04x:%04x] (rev %x)\n",
+		 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
+
+	rc = create_hdev(&hdev, pdev);
+	if (rc)
+		return rc;
+
+	pci_set_drvdata(pdev, hdev);
+
+	rc = hl_device_init(hdev);
+	if (rc) {
+		dev_err(&pdev->dev, "Fatal error during habanalabs device init\n");
+		rc = -ENODEV;
+		goto disable_device;
+	}
+
+	return 0;
+
+disable_device:
+	pci_set_drvdata(pdev, NULL);
+	destroy_hdev(hdev);
+
+	return rc;
+}
+
+/*
+ * hl_pci_remove - remove PCI habanalabs devices
+ *
+ * @pdev: pointer to pci device
+ *
+ * Standard PCI remove function for habanalabs device
+ */
+static void hl_pci_remove(struct pci_dev *pdev)
+{
+	struct hl_device *hdev;
+
+	hdev = pci_get_drvdata(pdev);
+	if (!hdev)
+		return;
+
+	hl_device_fini(hdev);
+	pci_set_drvdata(pdev, NULL);
+	destroy_hdev(hdev);
+}
+
+/**
+ * hl_pci_err_detected - a PCI bus error detected on this device
+ *
+ * @pdev: pointer to pci device
+ * @state: PCI error type
+ *
+ * Called by the PCI subsystem whenever a non-correctable
+ * PCI bus error is detected
+ */
+static pci_ers_result_t
+hl_pci_err_detected(struct pci_dev *pdev, pci_channel_state_t state)
+{
+	struct hl_device *hdev = pci_get_drvdata(pdev);
+	enum pci_ers_result result;
+
+	switch (state) {
+	case pci_channel_io_normal:
+		dev_warn(hdev->dev, "PCI normal state error detected\n");
+		return PCI_ERS_RESULT_CAN_RECOVER;
+
+	case pci_channel_io_frozen:
+		dev_warn(hdev->dev, "PCI frozen state error detected\n");
+		result = PCI_ERS_RESULT_NEED_RESET;
+		break;
+
+	case pci_channel_io_perm_failure:
+		dev_warn(hdev->dev, "PCI failure state error detected\n");
+		result = PCI_ERS_RESULT_DISCONNECT;
+		break;
+
+	default:
+		result = PCI_ERS_RESULT_NONE;
+	}
+
+	hdev->asic_funcs->halt_engines(hdev, true, false);
+
+	return result;
+}
+
+/**
+ * hl_pci_err_resume - resume after a PCI slot reset
+ *
+ * @pdev: pointer to pci device
+ *
+ */
+static void hl_pci_err_resume(struct pci_dev *pdev)
+{
+	struct hl_device *hdev = pci_get_drvdata(pdev);
+
+	dev_warn(hdev->dev, "Resuming device after PCI slot reset\n");
+	hl_device_resume(hdev);
+}
+
+/**
+ * hl_pci_err_slot_reset - a PCI slot reset has just happened
+ *
+ * @pdev: pointer to pci device
+ *
+ * Determine if the driver can recover from the PCI slot reset
+ */
+static pci_ers_result_t hl_pci_err_slot_reset(struct pci_dev *pdev)
+{
+	struct hl_device *hdev = pci_get_drvdata(pdev);
+
+	dev_warn(hdev->dev, "PCI slot reset detected\n");
+
+	return PCI_ERS_RESULT_RECOVERED;
+}
+
+static void hl_pci_reset_prepare(struct pci_dev *pdev)
+{
+	struct hl_device *hdev;
+
+	hdev = pci_get_drvdata(pdev);
+	if (!hdev)
+		return;
+
+	hdev->disabled = true;
+}
+
+static void hl_pci_reset_done(struct pci_dev *pdev)
+{
+	struct hl_device *hdev;
+	u32 flags;
+
+	hdev = pci_get_drvdata(pdev);
+	if (!hdev)
+		return;
+
+	/*
+	 * Schedule a thread to trigger hard reset.
+	 * The reason for this handler, is for rare cases where the driver is up
+	 * and FLR occurs. This is valid only when working with no VM, so FW handles FLR
+	 * and resets the device. FW will go back preboot stage, so driver needs to perform
+	 * hard reset in order to load FW fit again.
+	 */
+	flags = HL_DRV_RESET_HARD | HL_DRV_RESET_BYPASS_REQ_TO_FW;
+
+	hl_device_reset(hdev, flags);
+}
+
+static const struct dev_pm_ops hl_pm_ops = {
+	.suspend = hl_pmops_suspend,
+	.resume = hl_pmops_resume,
+};
+
+static const struct pci_error_handlers hl_pci_err_handler = {
+	.error_detected = hl_pci_err_detected,
+	.slot_reset = hl_pci_err_slot_reset,
+	.resume = hl_pci_err_resume,
+	.reset_prepare = hl_pci_reset_prepare,
+	.reset_done = hl_pci_reset_done,
+};
+
+static struct pci_driver hl_pci_driver = {
+	.name = HL_NAME,
+	.id_table = ids,
+	.probe = hl_pci_probe,
+	.remove = hl_pci_remove,
+	.shutdown = hl_pci_remove,
+	.driver = {
+		.name = HL_NAME,
+		.pm = &hl_pm_ops,
+		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
+	},
+	.err_handler = &hl_pci_err_handler,
+};
+
+/*
+ * hl_init - Initialize the habanalabs kernel driver
+ */
+static int __init hl_init(void)
+{
+	int rc;
+	dev_t dev;
+
+	pr_info("loading driver\n");
+
+	rc = alloc_chrdev_region(&dev, 0, HL_MAX_MINORS, HL_NAME);
+	if (rc < 0) {
+		pr_err("unable to get major\n");
+		return rc;
+	}
+
+	hl_major = MAJOR(dev);
+
+	rc = pci_register_driver(&hl_pci_driver);
+	if (rc) {
+		pr_err("failed to register pci device\n");
+		goto remove_major;
+	}
+
+	pr_debug("driver loaded\n");
+
+	return 0;
+
+remove_major:
+	unregister_chrdev_region(MKDEV(hl_major, 0), HL_MAX_MINORS);
+	return rc;
+}
+
+/*
+ * hl_exit - Release all resources of the habanalabs kernel driver
+ */
+static void __exit hl_exit(void)
+{
+	pci_unregister_driver(&hl_pci_driver);
+
+	unregister_chrdev_region(MKDEV(hl_major, 0), HL_MAX_MINORS);
+
+	idr_destroy(&hl_devs_idr);
+
+	pr_debug("driver removed\n");
+}
+
+module_init(hl_init);
+module_exit(hl_exit);
diff --git a/drivers/accel/habanalabs/common/habanalabs_ioctl.c b/drivers/accel/habanalabs/common/habanalabs_ioctl.c
new file mode 100644
index 000000000000..fdfdabc85e54
--- /dev/null
+++ b/drivers/accel/habanalabs/common/habanalabs_ioctl.c
@@ -0,0 +1,1319 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Copyright 2016-2022 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ */
+
+#define pr_fmt(fmt)	"habanalabs: " fmt
+
+#include <uapi/drm/habanalabs_accel.h>
+#include "habanalabs.h"
+
+#include <linux/fs.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/slab.h>
+#include <linux/uaccess.h>
+#include <linux/vmalloc.h>
+
+/* make sure there is space for all the signed info */
+static_assert(sizeof(struct cpucp_info) <= SEC_DEV_INFO_BUF_SZ);
+
+static u32 hl_debug_struct_size[HL_DEBUG_OP_TIMESTAMP + 1] = {
+	[HL_DEBUG_OP_ETR] = sizeof(struct hl_debug_params_etr),
+	[HL_DEBUG_OP_ETF] = sizeof(struct hl_debug_params_etf),
+	[HL_DEBUG_OP_STM] = sizeof(struct hl_debug_params_stm),
+	[HL_DEBUG_OP_FUNNEL] = 0,
+	[HL_DEBUG_OP_BMON] = sizeof(struct hl_debug_params_bmon),
+	[HL_DEBUG_OP_SPMU] = sizeof(struct hl_debug_params_spmu),
+	[HL_DEBUG_OP_TIMESTAMP] = 0
+
+};
+
+static int device_status_info(struct hl_device *hdev, struct hl_info_args *args)
+{
+	struct hl_info_device_status dev_stat = {0};
+	u32 size = args->return_size;
+	void __user *out = (void __user *) (uintptr_t) args->return_pointer;
+
+	if ((!size) || (!out))
+		return -EINVAL;
+
+	dev_stat.status = hl_device_status(hdev);
+
+	return copy_to_user(out, &dev_stat,
+			min((size_t)size, sizeof(dev_stat))) ? -EFAULT : 0;
+}
+
+static int hw_ip_info(struct hl_device *hdev, struct hl_info_args *args)
+{
+	struct hl_info_hw_ip_info hw_ip = {0};
+	u32 size = args->return_size;
+	void __user *out = (void __user *) (uintptr_t) args->return_pointer;
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	u64 sram_kmd_size, dram_kmd_size, dram_available_size;
+
+	if ((!size) || (!out))
+		return -EINVAL;
+
+	sram_kmd_size = (prop->sram_user_base_address -
+				prop->sram_base_address);
+	dram_kmd_size = (prop->dram_user_base_address -
+				prop->dram_base_address);
+
+	hw_ip.device_id = hdev->asic_funcs->get_pci_id(hdev);
+	hw_ip.sram_base_address = prop->sram_user_base_address;
+	hw_ip.dram_base_address =
+			prop->dram_supports_virtual_memory ?
+			prop->dmmu.start_addr : prop->dram_user_base_address;
+	hw_ip.tpc_enabled_mask = prop->tpc_enabled_mask & 0xFF;
+	hw_ip.tpc_enabled_mask_ext = prop->tpc_enabled_mask;
+
+	hw_ip.sram_size = prop->sram_size - sram_kmd_size;
+
+	dram_available_size = prop->dram_size - dram_kmd_size;
+
+	hw_ip.dram_size = DIV_ROUND_DOWN_ULL(dram_available_size, prop->dram_page_size) *
+				prop->dram_page_size;
+
+	if (hw_ip.dram_size > PAGE_SIZE)
+		hw_ip.dram_enabled = 1;
+
+	hw_ip.dram_page_size = prop->dram_page_size;
+	hw_ip.device_mem_alloc_default_page_size = prop->device_mem_alloc_default_page_size;
+	hw_ip.num_of_events = prop->num_of_events;
+
+	memcpy(hw_ip.cpucp_version, prop->cpucp_info.cpucp_version,
+		min(VERSION_MAX_LEN, HL_INFO_VERSION_MAX_LEN));
+
+	memcpy(hw_ip.card_name, prop->cpucp_info.card_name,
+		min(CARD_NAME_MAX_LEN, HL_INFO_CARD_NAME_MAX_LEN));
+
+	hw_ip.cpld_version = le32_to_cpu(prop->cpucp_info.cpld_version);
+	hw_ip.module_id = le32_to_cpu(prop->cpucp_info.card_location);
+
+	hw_ip.psoc_pci_pll_nr = prop->psoc_pci_pll_nr;
+	hw_ip.psoc_pci_pll_nf = prop->psoc_pci_pll_nf;
+	hw_ip.psoc_pci_pll_od = prop->psoc_pci_pll_od;
+	hw_ip.psoc_pci_pll_div_factor = prop->psoc_pci_pll_div_factor;
+
+	hw_ip.decoder_enabled_mask = prop->decoder_enabled_mask;
+	hw_ip.mme_master_slave_mode = prop->mme_master_slave_mode;
+	hw_ip.first_available_interrupt_id = prop->first_available_user_interrupt;
+	hw_ip.number_of_user_interrupts = prop->user_interrupt_count;
+	hw_ip.tpc_interrupt_id = prop->tpc_interrupt_id;
+
+	hw_ip.edma_enabled_mask = prop->edma_enabled_mask;
+	hw_ip.server_type = prop->server_type;
+	hw_ip.security_enabled = prop->fw_security_enabled;
+	hw_ip.revision_id = hdev->pdev->revision;
+	hw_ip.rotator_enabled_mask = prop->rotator_enabled_mask;
+	hw_ip.engine_core_interrupt_reg_addr = prop->engine_core_interrupt_reg_addr;
+	hw_ip.reserved_dram_size = dram_kmd_size;
+
+	return copy_to_user(out, &hw_ip,
+		min((size_t) size, sizeof(hw_ip))) ? -EFAULT : 0;
+}
+
+static int hw_events_info(struct hl_device *hdev, bool aggregate,
+			struct hl_info_args *args)
+{
+	u32 size, max_size = args->return_size;
+	void __user *out = (void __user *) (uintptr_t) args->return_pointer;
+	void *arr;
+
+	if ((!max_size) || (!out))
+		return -EINVAL;
+
+	arr = hdev->asic_funcs->get_events_stat(hdev, aggregate, &size);
+	if (!arr) {
+		dev_err(hdev->dev, "Events info not supported\n");
+		return -EOPNOTSUPP;
+	}
+
+	return copy_to_user(out, arr, min(max_size, size)) ? -EFAULT : 0;
+}
+
+static int events_info(struct hl_fpriv *hpriv, struct hl_info_args *args)
+{
+	u32 max_size = args->return_size;
+	u64 events_mask;
+	void __user *out = (void __user *) (uintptr_t) args->return_pointer;
+
+	if ((max_size < sizeof(u64)) || (!out))
+		return -EINVAL;
+
+	mutex_lock(&hpriv->notifier_event.lock);
+	events_mask = hpriv->notifier_event.events_mask;
+	hpriv->notifier_event.events_mask = 0;
+	mutex_unlock(&hpriv->notifier_event.lock);
+
+	return copy_to_user(out, &events_mask, sizeof(u64)) ? -EFAULT : 0;
+}
+
+static int dram_usage_info(struct hl_fpriv *hpriv, struct hl_info_args *args)
+{
+	struct hl_device *hdev = hpriv->hdev;
+	struct hl_info_dram_usage dram_usage = {0};
+	u32 max_size = args->return_size;
+	void __user *out = (void __user *) (uintptr_t) args->return_pointer;
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	u64 dram_kmd_size;
+
+	if ((!max_size) || (!out))
+		return -EINVAL;
+
+	dram_kmd_size = (prop->dram_user_base_address -
+				prop->dram_base_address);
+	dram_usage.dram_free_mem = (prop->dram_size - dram_kmd_size) -
+					atomic64_read(&hdev->dram_used_mem);
+	if (hpriv->ctx)
+		dram_usage.ctx_dram_mem =
+			atomic64_read(&hpriv->ctx->dram_phys_mem);
+
+	return copy_to_user(out, &dram_usage,
+		min((size_t) max_size, sizeof(dram_usage))) ? -EFAULT : 0;
+}
+
+static int hw_idle(struct hl_device *hdev, struct hl_info_args *args)
+{
+	struct hl_info_hw_idle hw_idle = {0};
+	u32 max_size = args->return_size;
+	void __user *out = (void __user *) (uintptr_t) args->return_pointer;
+
+	if ((!max_size) || (!out))
+		return -EINVAL;
+
+	hw_idle.is_idle = hdev->asic_funcs->is_device_idle(hdev,
+					hw_idle.busy_engines_mask_ext,
+					HL_BUSY_ENGINES_MASK_EXT_SIZE, NULL);
+	hw_idle.busy_engines_mask =
+			lower_32_bits(hw_idle.busy_engines_mask_ext[0]);
+
+	return copy_to_user(out, &hw_idle,
+		min((size_t) max_size, sizeof(hw_idle))) ? -EFAULT : 0;
+}
+
+static int debug_coresight(struct hl_device *hdev, struct hl_ctx *ctx, struct hl_debug_args *args)
+{
+	struct hl_debug_params *params;
+	void *input = NULL, *output = NULL;
+	int rc;
+
+	params = kzalloc(sizeof(*params), GFP_KERNEL);
+	if (!params)
+		return -ENOMEM;
+
+	params->reg_idx = args->reg_idx;
+	params->enable = args->enable;
+	params->op = args->op;
+
+	if (args->input_ptr && args->input_size) {
+		input = kzalloc(hl_debug_struct_size[args->op], GFP_KERNEL);
+		if (!input) {
+			rc = -ENOMEM;
+			goto out;
+		}
+
+		if (copy_from_user(input, u64_to_user_ptr(args->input_ptr),
+					args->input_size)) {
+			rc = -EFAULT;
+			dev_err(hdev->dev, "failed to copy input debug data\n");
+			goto out;
+		}
+
+		params->input = input;
+	}
+
+	if (args->output_ptr && args->output_size) {
+		output = kzalloc(args->output_size, GFP_KERNEL);
+		if (!output) {
+			rc = -ENOMEM;
+			goto out;
+		}
+
+		params->output = output;
+		params->output_size = args->output_size;
+	}
+
+	rc = hdev->asic_funcs->debug_coresight(hdev, ctx, params);
+	if (rc) {
+		dev_err(hdev->dev,
+			"debug coresight operation failed %d\n", rc);
+		goto out;
+	}
+
+	if (output && copy_to_user((void __user *) (uintptr_t) args->output_ptr,
+					output, args->output_size)) {
+		dev_err(hdev->dev, "copy to user failed in debug ioctl\n");
+		rc = -EFAULT;
+		goto out;
+	}
+
+
+out:
+	kfree(params);
+	kfree(output);
+	kfree(input);
+
+	return rc;
+}
+
+static int device_utilization(struct hl_device *hdev, struct hl_info_args *args)
+{
+	struct hl_info_device_utilization device_util = {0};
+	u32 max_size = args->return_size;
+	void __user *out = (void __user *) (uintptr_t) args->return_pointer;
+	int rc;
+
+	if ((!max_size) || (!out))
+		return -EINVAL;
+
+	rc = hl_device_utilization(hdev, &device_util.utilization);
+	if (rc)
+		return -EINVAL;
+
+	return copy_to_user(out, &device_util,
+		min((size_t) max_size, sizeof(device_util))) ? -EFAULT : 0;
+}
+
+static int get_clk_rate(struct hl_device *hdev, struct hl_info_args *args)
+{
+	struct hl_info_clk_rate clk_rate = {0};
+	u32 max_size = args->return_size;
+	void __user *out = (void __user *) (uintptr_t) args->return_pointer;
+	int rc;
+
+	if ((!max_size) || (!out))
+		return -EINVAL;
+
+	rc = hl_fw_get_clk_rate(hdev, &clk_rate.cur_clk_rate_mhz, &clk_rate.max_clk_rate_mhz);
+	if (rc)
+		return rc;
+
+	return copy_to_user(out, &clk_rate, min_t(size_t, max_size, sizeof(clk_rate)))
+										? -EFAULT : 0;
+}
+
+static int get_reset_count(struct hl_device *hdev, struct hl_info_args *args)
+{
+	struct hl_info_reset_count reset_count = {0};
+	u32 max_size = args->return_size;
+	void __user *out = (void __user *) (uintptr_t) args->return_pointer;
+
+	if ((!max_size) || (!out))
+		return -EINVAL;
+
+	reset_count.hard_reset_cnt = hdev->reset_info.hard_reset_cnt;
+	reset_count.soft_reset_cnt = hdev->reset_info.compute_reset_cnt;
+
+	return copy_to_user(out, &reset_count,
+		min((size_t) max_size, sizeof(reset_count))) ? -EFAULT : 0;
+}
+
+static int time_sync_info(struct hl_device *hdev, struct hl_info_args *args)
+{
+	struct hl_info_time_sync time_sync = {0};
+	u32 max_size = args->return_size;
+	void __user *out = (void __user *) (uintptr_t) args->return_pointer;
+
+	if ((!max_size) || (!out))
+		return -EINVAL;
+
+	time_sync.device_time = hdev->asic_funcs->get_device_time(hdev);
+	time_sync.host_time = ktime_get_raw_ns();
+	time_sync.tsc_time = rdtsc();
+
+	return copy_to_user(out, &time_sync,
+		min((size_t) max_size, sizeof(time_sync))) ? -EFAULT : 0;
+}
+
+static int pci_counters_info(struct hl_fpriv *hpriv, struct hl_info_args *args)
+{
+	struct hl_device *hdev = hpriv->hdev;
+	struct hl_info_pci_counters pci_counters = {0};
+	u32 max_size = args->return_size;
+	void __user *out = (void __user *) (uintptr_t) args->return_pointer;
+	int rc;
+
+	if ((!max_size) || (!out))
+		return -EINVAL;
+
+	rc = hl_fw_cpucp_pci_counters_get(hdev, &pci_counters);
+	if (rc)
+		return rc;
+
+	return copy_to_user(out, &pci_counters,
+		min((size_t) max_size, sizeof(pci_counters))) ? -EFAULT : 0;
+}
+
+static int clk_throttle_info(struct hl_fpriv *hpriv, struct hl_info_args *args)
+{
+	void __user *out = (void __user *) (uintptr_t) args->return_pointer;
+	struct hl_device *hdev = hpriv->hdev;
+	struct hl_info_clk_throttle clk_throttle = {0};
+	ktime_t end_time, zero_time = ktime_set(0, 0);
+	u32 max_size = args->return_size;
+	int i;
+
+	if ((!max_size) || (!out))
+		return -EINVAL;
+
+	mutex_lock(&hdev->clk_throttling.lock);
+
+	clk_throttle.clk_throttling_reason = hdev->clk_throttling.current_reason;
+
+	for (i = 0 ; i < HL_CLK_THROTTLE_TYPE_MAX ; i++) {
+		if (!(hdev->clk_throttling.aggregated_reason & BIT(i)))
+			continue;
+
+		clk_throttle.clk_throttling_timestamp_us[i] =
+			ktime_to_us(hdev->clk_throttling.timestamp[i].start);
+
+		if (ktime_compare(hdev->clk_throttling.timestamp[i].end, zero_time))
+			end_time = hdev->clk_throttling.timestamp[i].end;
+		else
+			end_time = ktime_get();
+
+		clk_throttle.clk_throttling_duration_ns[i] =
+			ktime_to_ns(ktime_sub(end_time,
+				hdev->clk_throttling.timestamp[i].start));
+
+	}
+	mutex_unlock(&hdev->clk_throttling.lock);
+
+	return copy_to_user(out, &clk_throttle,
+		min((size_t) max_size, sizeof(clk_throttle))) ? -EFAULT : 0;
+}
+
+static int cs_counters_info(struct hl_fpriv *hpriv, struct hl_info_args *args)
+{
+	void __user *out = (void __user *) (uintptr_t) args->return_pointer;
+	struct hl_info_cs_counters cs_counters = {0};
+	struct hl_device *hdev = hpriv->hdev;
+	struct hl_cs_counters_atomic *cntr;
+	u32 max_size = args->return_size;
+
+	cntr = &hdev->aggregated_cs_counters;
+
+	if ((!max_size) || (!out))
+		return -EINVAL;
+
+	cs_counters.total_out_of_mem_drop_cnt =
+			atomic64_read(&cntr->out_of_mem_drop_cnt);
+	cs_counters.total_parsing_drop_cnt =
+			atomic64_read(&cntr->parsing_drop_cnt);
+	cs_counters.total_queue_full_drop_cnt =
+			atomic64_read(&cntr->queue_full_drop_cnt);
+	cs_counters.total_device_in_reset_drop_cnt =
+			atomic64_read(&cntr->device_in_reset_drop_cnt);
+	cs_counters.total_max_cs_in_flight_drop_cnt =
+			atomic64_read(&cntr->max_cs_in_flight_drop_cnt);
+	cs_counters.total_validation_drop_cnt =
+			atomic64_read(&cntr->validation_drop_cnt);
+
+	if (hpriv->ctx) {
+		cs_counters.ctx_out_of_mem_drop_cnt =
+				atomic64_read(
+				&hpriv->ctx->cs_counters.out_of_mem_drop_cnt);
+		cs_counters.ctx_parsing_drop_cnt =
+				atomic64_read(
+				&hpriv->ctx->cs_counters.parsing_drop_cnt);
+		cs_counters.ctx_queue_full_drop_cnt =
+				atomic64_read(
+				&hpriv->ctx->cs_counters.queue_full_drop_cnt);
+		cs_counters.ctx_device_in_reset_drop_cnt =
+				atomic64_read(
+			&hpriv->ctx->cs_counters.device_in_reset_drop_cnt);
+		cs_counters.ctx_max_cs_in_flight_drop_cnt =
+				atomic64_read(
+			&hpriv->ctx->cs_counters.max_cs_in_flight_drop_cnt);
+		cs_counters.ctx_validation_drop_cnt =
+				atomic64_read(
+				&hpriv->ctx->cs_counters.validation_drop_cnt);
+	}
+
+	return copy_to_user(out, &cs_counters,
+		min((size_t) max_size, sizeof(cs_counters))) ? -EFAULT : 0;
+}
+
+static int sync_manager_info(struct hl_fpriv *hpriv, struct hl_info_args *args)
+{
+	struct hl_device *hdev = hpriv->hdev;
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct hl_info_sync_manager sm_info = {0};
+	u32 max_size = args->return_size;
+	void __user *out = (void __user *) (uintptr_t) args->return_pointer;
+
+	if ((!max_size) || (!out))
+		return -EINVAL;
+
+	if (args->dcore_id >= HL_MAX_DCORES)
+		return -EINVAL;
+
+	sm_info.first_available_sync_object =
+			prop->first_available_user_sob[args->dcore_id];
+	sm_info.first_available_monitor =
+			prop->first_available_user_mon[args->dcore_id];
+	sm_info.first_available_cq =
+			prop->first_available_cq[args->dcore_id];
+
+	return copy_to_user(out, &sm_info, min_t(size_t, (size_t) max_size,
+			sizeof(sm_info))) ? -EFAULT : 0;
+}
+
+static int total_energy_consumption_info(struct hl_fpriv *hpriv,
+			struct hl_info_args *args)
+{
+	struct hl_device *hdev = hpriv->hdev;
+	struct hl_info_energy total_energy = {0};
+	u32 max_size = args->return_size;
+	void __user *out = (void __user *) (uintptr_t) args->return_pointer;
+	int rc;
+
+	if ((!max_size) || (!out))
+		return -EINVAL;
+
+	rc = hl_fw_cpucp_total_energy_get(hdev,
+			&total_energy.total_energy_consumption);
+	if (rc)
+		return rc;
+
+	return copy_to_user(out, &total_energy,
+		min((size_t) max_size, sizeof(total_energy))) ? -EFAULT : 0;
+}
+
+static int pll_frequency_info(struct hl_fpriv *hpriv, struct hl_info_args *args)
+{
+	struct hl_device *hdev = hpriv->hdev;
+	struct hl_pll_frequency_info freq_info = { {0} };
+	u32 max_size = args->return_size;
+	void __user *out = (void __user *) (uintptr_t) args->return_pointer;
+	int rc;
+
+	if ((!max_size) || (!out))
+		return -EINVAL;
+
+	rc = hl_fw_cpucp_pll_info_get(hdev, args->pll_index, freq_info.output);
+	if (rc)
+		return rc;
+
+	return copy_to_user(out, &freq_info,
+		min((size_t) max_size, sizeof(freq_info))) ? -EFAULT : 0;
+}
+
+static int power_info(struct hl_fpriv *hpriv, struct hl_info_args *args)
+{
+	struct hl_device *hdev = hpriv->hdev;
+	u32 max_size = args->return_size;
+	struct hl_power_info power_info = {0};
+	void __user *out = (void __user *) (uintptr_t) args->return_pointer;
+	int rc;
+
+	if ((!max_size) || (!out))
+		return -EINVAL;
+
+	rc = hl_fw_cpucp_power_get(hdev, &power_info.power);
+	if (rc)
+		return rc;
+
+	return copy_to_user(out, &power_info,
+		min((size_t) max_size, sizeof(power_info))) ? -EFAULT : 0;
+}
+
+static int open_stats_info(struct hl_fpriv *hpriv, struct hl_info_args *args)
+{
+	struct hl_device *hdev = hpriv->hdev;
+	u32 max_size = args->return_size;
+	struct hl_open_stats_info open_stats_info = {0};
+	void __user *out = (void __user *) (uintptr_t) args->return_pointer;
+
+	if ((!max_size) || (!out))
+		return -EINVAL;
+
+	open_stats_info.last_open_period_ms = jiffies64_to_msecs(
+		hdev->last_open_session_duration_jif);
+	open_stats_info.open_counter = hdev->open_counter;
+	open_stats_info.is_compute_ctx_active = hdev->is_compute_ctx_active;
+	open_stats_info.compute_ctx_in_release = hdev->compute_ctx_in_release;
+
+	return copy_to_user(out, &open_stats_info,
+		min((size_t) max_size, sizeof(open_stats_info))) ? -EFAULT : 0;
+}
+
+static int dram_pending_rows_info(struct hl_fpriv *hpriv, struct hl_info_args *args)
+{
+	struct hl_device *hdev = hpriv->hdev;
+	u32 max_size = args->return_size;
+	u32 pend_rows_num = 0;
+	void __user *out = (void __user *) (uintptr_t) args->return_pointer;
+	int rc;
+
+	if ((!max_size) || (!out))
+		return -EINVAL;
+
+	rc = hl_fw_dram_pending_row_get(hdev, &pend_rows_num);
+	if (rc)
+		return rc;
+
+	return copy_to_user(out, &pend_rows_num,
+			min_t(size_t, max_size, sizeof(pend_rows_num))) ? -EFAULT : 0;
+}
+
+static int dram_replaced_rows_info(struct hl_fpriv *hpriv, struct hl_info_args *args)
+{
+	struct hl_device *hdev = hpriv->hdev;
+	u32 max_size = args->return_size;
+	struct cpucp_hbm_row_info info = {0};
+	void __user *out = (void __user *) (uintptr_t) args->return_pointer;
+	int rc;
+
+	if ((!max_size) || (!out))
+		return -EINVAL;
+
+	rc = hl_fw_dram_replaced_row_get(hdev, &info);
+	if (rc)
+		return rc;
+
+	return copy_to_user(out, &info, min_t(size_t, max_size, sizeof(info))) ? -EFAULT : 0;
+}
+
+static int last_err_open_dev_info(struct hl_fpriv *hpriv, struct hl_info_args *args)
+{
+	struct hl_info_last_err_open_dev_time info = {0};
+	struct hl_device *hdev = hpriv->hdev;
+	u32 max_size = args->return_size;
+	void __user *out = (void __user *) (uintptr_t) args->return_pointer;
+
+	if ((!max_size) || (!out))
+		return -EINVAL;
+
+	info.timestamp = ktime_to_ns(hdev->last_successful_open_ktime);
+
+	return copy_to_user(out, &info, min_t(size_t, max_size, sizeof(info))) ? -EFAULT : 0;
+}
+
+static int cs_timeout_info(struct hl_fpriv *hpriv, struct hl_info_args *args)
+{
+	struct hl_info_cs_timeout_event info = {0};
+	struct hl_device *hdev = hpriv->hdev;
+	u32 max_size = args->return_size;
+	void __user *out = (void __user *) (uintptr_t) args->return_pointer;
+
+	if ((!max_size) || (!out))
+		return -EINVAL;
+
+	info.seq = hdev->captured_err_info.cs_timeout.seq;
+	info.timestamp = ktime_to_ns(hdev->captured_err_info.cs_timeout.timestamp);
+
+	return copy_to_user(out, &info, min_t(size_t, max_size, sizeof(info))) ? -EFAULT : 0;
+}
+
+static int razwi_info(struct hl_fpriv *hpriv, struct hl_info_args *args)
+{
+	void __user *out = (void __user *) (uintptr_t) args->return_pointer;
+	struct hl_device *hdev = hpriv->hdev;
+	u32 max_size = args->return_size;
+	struct razwi_info *razwi_info;
+
+	if ((!max_size) || (!out))
+		return -EINVAL;
+
+	razwi_info = &hdev->captured_err_info.razwi_info;
+	if (!razwi_info->razwi_info_available)
+		return 0;
+
+	return copy_to_user(out, &razwi_info->razwi,
+			min_t(size_t, max_size, sizeof(struct hl_info_razwi_event))) ? -EFAULT : 0;
+}
+
+static int undefined_opcode_info(struct hl_fpriv *hpriv, struct hl_info_args *args)
+{
+	struct hl_device *hdev = hpriv->hdev;
+	u32 max_size = args->return_size;
+	struct hl_info_undefined_opcode_event info = {0};
+	void __user *out = (void __user *) (uintptr_t) args->return_pointer;
+
+	if ((!max_size) || (!out))
+		return -EINVAL;
+
+	info.timestamp = ktime_to_ns(hdev->captured_err_info.undef_opcode.timestamp);
+	info.engine_id = hdev->captured_err_info.undef_opcode.engine_id;
+	info.cq_addr = hdev->captured_err_info.undef_opcode.cq_addr;
+	info.cq_size = hdev->captured_err_info.undef_opcode.cq_size;
+	info.stream_id = hdev->captured_err_info.undef_opcode.stream_id;
+	info.cb_addr_streams_len = hdev->captured_err_info.undef_opcode.cb_addr_streams_len;
+	memcpy(info.cb_addr_streams, hdev->captured_err_info.undef_opcode.cb_addr_streams,
+			sizeof(info.cb_addr_streams));
+
+	return copy_to_user(out, &info, min_t(size_t, max_size, sizeof(info))) ? -EFAULT : 0;
+}
+
+static int dev_mem_alloc_page_sizes_info(struct hl_fpriv *hpriv, struct hl_info_args *args)
+{
+	void __user *out = (void __user *) (uintptr_t) args->return_pointer;
+	struct hl_info_dev_memalloc_page_sizes info = {0};
+	struct hl_device *hdev = hpriv->hdev;
+	u32 max_size = args->return_size;
+
+	if ((!max_size) || (!out))
+		return -EINVAL;
+
+	/*
+	 * Future ASICs that will support multiple DRAM page sizes will support only "powers of 2"
+	 * pages (unlike some of the ASICs before supporting multiple page sizes).
+	 * For this reason for all ASICs that not support multiple page size the function will
+	 * return an empty bitmask indicating that multiple page sizes is not supported.
+	 */
+	info.page_order_bitmask = hdev->asic_prop.dmmu.supported_pages_mask;
+
+	return copy_to_user(out, &info, min_t(size_t, max_size, sizeof(info))) ? -EFAULT : 0;
+}
+
+static int sec_attest_info(struct hl_fpriv *hpriv, struct hl_info_args *args)
+{
+	void __user *out = (void __user *) (uintptr_t) args->return_pointer;
+	struct cpucp_sec_attest_info *sec_attest_info;
+	struct hl_info_sec_attest *info;
+	u32 max_size = args->return_size;
+	int rc;
+
+	if ((!max_size) || (!out))
+		return -EINVAL;
+
+	sec_attest_info = kmalloc(sizeof(*sec_attest_info), GFP_KERNEL);
+	if (!sec_attest_info)
+		return -ENOMEM;
+
+	info = kzalloc(sizeof(*info), GFP_KERNEL);
+	if (!info) {
+		rc = -ENOMEM;
+		goto free_sec_attest_info;
+	}
+
+	rc = hl_fw_get_sec_attest_info(hpriv->hdev, sec_attest_info, args->sec_attest_nonce);
+	if (rc)
+		goto free_info;
+
+	info->nonce = le32_to_cpu(sec_attest_info->nonce);
+	info->pcr_quote_len = le16_to_cpu(sec_attest_info->pcr_quote_len);
+	info->pub_data_len = le16_to_cpu(sec_attest_info->pub_data_len);
+	info->certificate_len = le16_to_cpu(sec_attest_info->certificate_len);
+	info->pcr_num_reg = sec_attest_info->pcr_num_reg;
+	info->pcr_reg_len = sec_attest_info->pcr_reg_len;
+	info->quote_sig_len = sec_attest_info->quote_sig_len;
+	memcpy(&info->pcr_data, &sec_attest_info->pcr_data, sizeof(info->pcr_data));
+	memcpy(&info->pcr_quote, &sec_attest_info->pcr_quote, sizeof(info->pcr_quote));
+	memcpy(&info->public_data, &sec_attest_info->public_data, sizeof(info->public_data));
+	memcpy(&info->certificate, &sec_attest_info->certificate, sizeof(info->certificate));
+	memcpy(&info->quote_sig, &sec_attest_info->quote_sig, sizeof(info->quote_sig));
+
+	rc = copy_to_user(out, info,
+				min_t(size_t, max_size, sizeof(*info))) ? -EFAULT : 0;
+
+free_info:
+	kfree(info);
+free_sec_attest_info:
+	kfree(sec_attest_info);
+
+	return rc;
+}
+
+static int dev_info_signed(struct hl_fpriv *hpriv, struct hl_info_args *args)
+{
+	void __user *out = (void __user *) (uintptr_t) args->return_pointer;
+	struct cpucp_dev_info_signed *dev_info_signed;
+	struct hl_info_signed *info;
+	u32 max_size = args->return_size;
+	int rc;
+
+	if ((!max_size) || (!out))
+		return -EINVAL;
+
+	dev_info_signed = kzalloc(sizeof(*dev_info_signed), GFP_KERNEL);
+	if (!dev_info_signed)
+		return -ENOMEM;
+
+	info = kzalloc(sizeof(*info), GFP_KERNEL);
+	if (!info) {
+		rc = -ENOMEM;
+		goto free_dev_info_signed;
+	}
+
+	rc = hl_fw_get_dev_info_signed(hpriv->hdev,
+					dev_info_signed, args->sec_attest_nonce);
+	if (rc)
+		goto free_info;
+
+	info->nonce = le32_to_cpu(dev_info_signed->nonce);
+	info->info_sig_len = dev_info_signed->info_sig_len;
+	info->pub_data_len = le16_to_cpu(dev_info_signed->pub_data_len);
+	info->certificate_len = le16_to_cpu(dev_info_signed->certificate_len);
+	info->dev_info_len = sizeof(struct cpucp_info);
+	memcpy(&info->info_sig, &dev_info_signed->info_sig, sizeof(info->info_sig));
+	memcpy(&info->public_data, &dev_info_signed->public_data, sizeof(info->public_data));
+	memcpy(&info->certificate, &dev_info_signed->certificate, sizeof(info->certificate));
+	memcpy(&info->dev_info, &dev_info_signed->info, info->dev_info_len);
+
+	rc = copy_to_user(out, info, min_t(size_t, max_size, sizeof(*info))) ? -EFAULT : 0;
+
+free_info:
+	kfree(info);
+free_dev_info_signed:
+	kfree(dev_info_signed);
+
+	return rc;
+}
+
+
+static int eventfd_register(struct hl_fpriv *hpriv, struct hl_info_args *args)
+{
+	int rc;
+
+	/* check if there is already a registered on that process */
+	mutex_lock(&hpriv->notifier_event.lock);
+	if (hpriv->notifier_event.eventfd) {
+		mutex_unlock(&hpriv->notifier_event.lock);
+		return -EINVAL;
+	}
+
+	hpriv->notifier_event.eventfd = eventfd_ctx_fdget(args->eventfd);
+	if (IS_ERR(hpriv->notifier_event.eventfd)) {
+		rc = PTR_ERR(hpriv->notifier_event.eventfd);
+		hpriv->notifier_event.eventfd = NULL;
+		mutex_unlock(&hpriv->notifier_event.lock);
+		return rc;
+	}
+
+	mutex_unlock(&hpriv->notifier_event.lock);
+	return 0;
+}
+
+static int eventfd_unregister(struct hl_fpriv *hpriv, struct hl_info_args *args)
+{
+	mutex_lock(&hpriv->notifier_event.lock);
+	if (!hpriv->notifier_event.eventfd) {
+		mutex_unlock(&hpriv->notifier_event.lock);
+		return -EINVAL;
+	}
+
+	eventfd_ctx_put(hpriv->notifier_event.eventfd);
+	hpriv->notifier_event.eventfd = NULL;
+	mutex_unlock(&hpriv->notifier_event.lock);
+	return 0;
+}
+
+static int engine_status_info(struct hl_fpriv *hpriv, struct hl_info_args *args)
+{
+	void __user *out = (void __user *) (uintptr_t) args->return_pointer;
+	u32 status_buf_size = args->return_size;
+	struct hl_device *hdev = hpriv->hdev;
+	struct engines_data eng_data;
+	int rc;
+
+	if ((status_buf_size < SZ_1K) || (status_buf_size > HL_ENGINES_DATA_MAX_SIZE) || (!out))
+		return -EINVAL;
+
+	eng_data.actual_size = 0;
+	eng_data.allocated_buf_size = status_buf_size;
+	eng_data.buf = vmalloc(status_buf_size);
+	if (!eng_data.buf)
+		return -ENOMEM;
+
+	hdev->asic_funcs->is_device_idle(hdev, NULL, 0, &eng_data);
+
+	if (eng_data.actual_size > eng_data.allocated_buf_size) {
+		dev_err(hdev->dev,
+			"Engines data size (%d Bytes) is bigger than allocated size (%u Bytes)\n",
+			eng_data.actual_size, status_buf_size);
+		vfree(eng_data.buf);
+		return -ENOMEM;
+	}
+
+	args->user_buffer_actual_size = eng_data.actual_size;
+	rc = copy_to_user(out, eng_data.buf, min_t(size_t, status_buf_size, eng_data.actual_size)) ?
+				-EFAULT : 0;
+
+	vfree(eng_data.buf);
+
+	return rc;
+}
+
+static int page_fault_info(struct hl_fpriv *hpriv, struct hl_info_args *args)
+{
+	void __user *out = (void __user *) (uintptr_t) args->return_pointer;
+	struct hl_device *hdev = hpriv->hdev;
+	u32 max_size = args->return_size;
+	struct page_fault_info *pgf_info;
+
+	if ((!max_size) || (!out))
+		return -EINVAL;
+
+	pgf_info = &hdev->captured_err_info.page_fault_info;
+	if (!pgf_info->page_fault_info_available)
+		return 0;
+
+	return copy_to_user(out, &pgf_info->page_fault,
+			min_t(size_t, max_size, sizeof(struct hl_page_fault_info))) ? -EFAULT : 0;
+}
+
+static int user_mappings_info(struct hl_fpriv *hpriv, struct hl_info_args *args)
+{
+	void __user *out = (void __user *) (uintptr_t) args->return_pointer;
+	u32 user_buf_size = args->return_size;
+	struct hl_device *hdev = hpriv->hdev;
+	struct page_fault_info *pgf_info;
+	u64 actual_size;
+
+	if (!out)
+		return -EINVAL;
+
+	pgf_info = &hdev->captured_err_info.page_fault_info;
+	if (!pgf_info->page_fault_info_available)
+		return 0;
+
+	args->array_size = pgf_info->num_of_user_mappings;
+
+	actual_size = pgf_info->num_of_user_mappings * sizeof(struct hl_user_mapping);
+	if (user_buf_size < actual_size)
+		return -ENOMEM;
+
+	return copy_to_user(out, pgf_info->user_mappings, actual_size) ? -EFAULT : 0;
+}
+
+static int hw_err_info(struct hl_fpriv *hpriv, struct hl_info_args *args)
+{
+	void __user *user_buf = (void __user *) (uintptr_t) args->return_pointer;
+	struct hl_device *hdev = hpriv->hdev;
+	u32 user_buf_size = args->return_size;
+	struct hw_err_info *info;
+	int rc;
+
+	if (!user_buf)
+		return -EINVAL;
+
+	info = &hdev->captured_err_info.hw_err;
+	if (!info->event_info_available)
+		return 0;
+
+	if (user_buf_size < sizeof(struct hl_info_hw_err_event))
+		return -ENOMEM;
+
+	rc = copy_to_user(user_buf, &info->event, sizeof(struct hl_info_hw_err_event));
+	return rc ? -EFAULT : 0;
+}
+
+static int fw_err_info(struct hl_fpriv *hpriv, struct hl_info_args *args)
+{
+	void __user *user_buf = (void __user *) (uintptr_t) args->return_pointer;
+	struct hl_device *hdev = hpriv->hdev;
+	u32 user_buf_size = args->return_size;
+	struct fw_err_info *info;
+	int rc;
+
+	if (!user_buf)
+		return -EINVAL;
+
+	info = &hdev->captured_err_info.fw_err;
+	if (!info->event_info_available)
+		return 0;
+
+	if (user_buf_size < sizeof(struct hl_info_fw_err_event))
+		return -ENOMEM;
+
+	rc = copy_to_user(user_buf, &info->event, sizeof(struct hl_info_fw_err_event));
+	return rc ? -EFAULT : 0;
+}
+
+static int engine_err_info(struct hl_fpriv *hpriv, struct hl_info_args *args)
+{
+	void __user *user_buf = (void __user *) (uintptr_t) args->return_pointer;
+	struct hl_device *hdev = hpriv->hdev;
+	u32 user_buf_size = args->return_size;
+	struct engine_err_info *info;
+	int rc;
+
+	if (!user_buf)
+		return -EINVAL;
+
+	info = &hdev->captured_err_info.engine_err;
+	if (!info->event_info_available)
+		return 0;
+
+	if (user_buf_size < sizeof(struct hl_info_engine_err_event))
+		return -ENOMEM;
+
+	rc = copy_to_user(user_buf, &info->event, sizeof(struct hl_info_engine_err_event));
+	return rc ? -EFAULT : 0;
+}
+
+static int send_fw_generic_request(struct hl_device *hdev, struct hl_info_args *info_args)
+{
+	void __user *buff = (void __user *) (uintptr_t) info_args->return_pointer;
+	u32 size = info_args->return_size;
+	dma_addr_t dma_handle;
+	bool need_input_buff;
+	void *fw_buff;
+	int rc = 0;
+
+	switch (info_args->fw_sub_opcode) {
+	case HL_PASSTHROUGH_VERSIONS:
+		need_input_buff = false;
+		break;
+	case  HL_GET_ERR_COUNTERS_CMD:
+		need_input_buff = true;
+		break;
+	case HL_GET_P_STATE:
+		need_input_buff = false;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	if (size > SZ_1M) {
+		dev_err(hdev->dev, "buffer size cannot exceed 1MB\n");
+		return -EINVAL;
+	}
+
+	fw_buff = hl_cpu_accessible_dma_pool_alloc(hdev, size, &dma_handle);
+	if (!fw_buff)
+		return -ENOMEM;
+
+
+	if (need_input_buff && copy_from_user(fw_buff, buff, size)) {
+		dev_dbg(hdev->dev, "Failed to copy from user FW buff\n");
+		rc = -EFAULT;
+		goto free_buff;
+	}
+
+	rc = hl_fw_send_generic_request(hdev, info_args->fw_sub_opcode, dma_handle, &size);
+	if (rc)
+		goto free_buff;
+
+	if (copy_to_user(buff, fw_buff, min(size, info_args->return_size))) {
+		dev_dbg(hdev->dev, "Failed to copy to user FW generic req output\n");
+		rc = -EFAULT;
+	}
+
+free_buff:
+	hl_cpu_accessible_dma_pool_free(hdev, info_args->return_size, fw_buff);
+
+	return rc;
+}
+
+static int _hl_info_ioctl(struct hl_fpriv *hpriv, void *data,
+				struct device *dev)
+{
+	enum hl_device_status status;
+	struct hl_info_args *args = data;
+	struct hl_device *hdev = hpriv->hdev;
+	int rc;
+
+	if (args->pad) {
+		dev_dbg(hdev->dev, "Padding bytes must be 0\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Information is returned for the following opcodes even if the device
+	 * is disabled or in reset.
+	 */
+	switch (args->op) {
+	case HL_INFO_HW_IP_INFO:
+		return hw_ip_info(hdev, args);
+
+	case HL_INFO_DEVICE_STATUS:
+		return device_status_info(hdev, args);
+
+	case HL_INFO_RESET_COUNT:
+		return get_reset_count(hdev, args);
+
+	case HL_INFO_HW_EVENTS:
+		return hw_events_info(hdev, false, args);
+
+	case HL_INFO_HW_EVENTS_AGGREGATE:
+		return hw_events_info(hdev, true, args);
+
+	case HL_INFO_CS_COUNTERS:
+		return cs_counters_info(hpriv, args);
+
+	case HL_INFO_CLK_THROTTLE_REASON:
+		return clk_throttle_info(hpriv, args);
+
+	case HL_INFO_SYNC_MANAGER:
+		return sync_manager_info(hpriv, args);
+
+	case HL_INFO_OPEN_STATS:
+		return open_stats_info(hpriv, args);
+
+	case HL_INFO_LAST_ERR_OPEN_DEV_TIME:
+		return last_err_open_dev_info(hpriv, args);
+
+	case HL_INFO_CS_TIMEOUT_EVENT:
+		return cs_timeout_info(hpriv, args);
+
+	case HL_INFO_RAZWI_EVENT:
+		return razwi_info(hpriv, args);
+
+	case HL_INFO_UNDEFINED_OPCODE_EVENT:
+		return undefined_opcode_info(hpriv, args);
+
+	case HL_INFO_DEV_MEM_ALLOC_PAGE_SIZES:
+		return dev_mem_alloc_page_sizes_info(hpriv, args);
+
+	case HL_INFO_GET_EVENTS:
+		return events_info(hpriv, args);
+
+	case HL_INFO_PAGE_FAULT_EVENT:
+		return page_fault_info(hpriv, args);
+
+	case HL_INFO_USER_MAPPINGS:
+		return user_mappings_info(hpriv, args);
+
+	case HL_INFO_UNREGISTER_EVENTFD:
+		return eventfd_unregister(hpriv, args);
+
+	case HL_INFO_HW_ERR_EVENT:
+		return hw_err_info(hpriv, args);
+
+	case HL_INFO_FW_ERR_EVENT:
+		return fw_err_info(hpriv, args);
+
+	case HL_INFO_USER_ENGINE_ERR_EVENT:
+		return engine_err_info(hpriv, args);
+
+	case HL_INFO_DRAM_USAGE:
+		return dram_usage_info(hpriv, args);
+	default:
+		break;
+	}
+
+	if (!hl_device_operational(hdev, &status)) {
+		dev_dbg_ratelimited(dev,
+			"Device is %s. Can't execute INFO IOCTL\n",
+			hdev->status[status]);
+		return -EBUSY;
+	}
+
+	switch (args->op) {
+	case HL_INFO_HW_IDLE:
+		rc = hw_idle(hdev, args);
+		break;
+
+	case HL_INFO_DEVICE_UTILIZATION:
+		rc = device_utilization(hdev, args);
+		break;
+
+	case HL_INFO_CLK_RATE:
+		rc = get_clk_rate(hdev, args);
+		break;
+
+	case HL_INFO_TIME_SYNC:
+		return time_sync_info(hdev, args);
+
+	case HL_INFO_PCI_COUNTERS:
+		return pci_counters_info(hpriv, args);
+
+	case HL_INFO_TOTAL_ENERGY:
+		return total_energy_consumption_info(hpriv, args);
+
+	case HL_INFO_PLL_FREQUENCY:
+		return pll_frequency_info(hpriv, args);
+
+	case HL_INFO_POWER:
+		return power_info(hpriv, args);
+
+
+	case HL_INFO_DRAM_REPLACED_ROWS:
+		return dram_replaced_rows_info(hpriv, args);
+
+	case HL_INFO_DRAM_PENDING_ROWS:
+		return dram_pending_rows_info(hpriv, args);
+
+	case HL_INFO_SECURED_ATTESTATION:
+		return sec_attest_info(hpriv, args);
+
+	case HL_INFO_REGISTER_EVENTFD:
+		return eventfd_register(hpriv, args);
+
+	case HL_INFO_ENGINE_STATUS:
+		return engine_status_info(hpriv, args);
+
+	case HL_INFO_FW_GENERIC_REQ:
+		return send_fw_generic_request(hdev, args);
+
+	case HL_INFO_DEV_SIGNED:
+		return dev_info_signed(hpriv, args);
+
+	default:
+		dev_err(dev, "Invalid request %d\n", args->op);
+		rc = -EINVAL;
+		break;
+	}
+
+	return rc;
+}
+
+int hl_info_ioctl(struct drm_device *ddev, void *data, struct drm_file *file_priv)
+{
+	struct hl_fpriv *hpriv = file_priv->driver_priv;
+
+	return _hl_info_ioctl(hpriv, data, hpriv->hdev->dev);
+}
+
+static int hl_info_ioctl_control(struct hl_fpriv *hpriv, void *data)
+{
+	struct hl_info_args *args = data;
+
+	switch (args->op) {
+	case HL_INFO_GET_EVENTS:
+	case HL_INFO_UNREGISTER_EVENTFD:
+	case HL_INFO_REGISTER_EVENTFD:
+		return -EOPNOTSUPP;
+	default:
+		break;
+	}
+
+	return _hl_info_ioctl(hpriv, data, hpriv->hdev->dev_ctrl);
+}
+
+int hl_debug_ioctl(struct drm_device *ddev, void *data, struct drm_file *file_priv)
+{
+	struct hl_fpriv *hpriv = file_priv->driver_priv;
+	struct hl_device *hdev = hpriv->hdev;
+	struct hl_debug_args *args = data;
+	enum hl_device_status status;
+
+	int rc = 0;
+
+	if (!hl_device_operational(hdev, &status)) {
+		dev_dbg_ratelimited(hdev->dev,
+			"Device is %s. Can't execute DEBUG IOCTL\n",
+			hdev->status[status]);
+		return -EBUSY;
+	}
+
+	switch (args->op) {
+	case HL_DEBUG_OP_ETR:
+	case HL_DEBUG_OP_ETF:
+	case HL_DEBUG_OP_STM:
+	case HL_DEBUG_OP_FUNNEL:
+	case HL_DEBUG_OP_BMON:
+	case HL_DEBUG_OP_SPMU:
+	case HL_DEBUG_OP_TIMESTAMP:
+		if (!hdev->in_debug) {
+			dev_err_ratelimited(hdev->dev,
+				"Rejecting debug configuration request because device not in debug mode\n");
+			return -EFAULT;
+		}
+		args->input_size = min(args->input_size, hl_debug_struct_size[args->op]);
+		rc = debug_coresight(hdev, hpriv->ctx, args);
+		break;
+
+	case HL_DEBUG_OP_SET_MODE:
+		rc = hl_device_set_debug_mode(hdev, hpriv->ctx, (bool) args->enable);
+		break;
+
+	default:
+		dev_err(hdev->dev, "Invalid request %d\n", args->op);
+		rc = -EINVAL;
+		break;
+	}
+
+	return rc;
+}
+
+#define HL_IOCTL_DEF(ioctl, _func) \
+	[_IOC_NR(ioctl) - HL_COMMAND_START] = {.cmd = ioctl, .func = _func}
+
+static const struct hl_ioctl_desc hl_ioctls_control[] = {
+	HL_IOCTL_DEF(DRM_IOCTL_HL_INFO, hl_info_ioctl_control)
+};
+
+static long _hl_ioctl(struct hl_fpriv *hpriv, unsigned int cmd, unsigned long arg,
+			const struct hl_ioctl_desc *ioctl, struct device *dev)
+{
+	unsigned int nr = _IOC_NR(cmd);
+	char stack_kdata[128] = {0};
+	char *kdata = NULL;
+	unsigned int usize, asize;
+	hl_ioctl_t *func;
+	u32 hl_size;
+	int retcode;
+
+	/* Do not trust userspace, use our own definition */
+	func = ioctl->func;
+
+	if (unlikely(!func)) {
+		dev_dbg(dev, "no function\n");
+		retcode = -ENOTTY;
+		goto out_err;
+	}
+
+	hl_size = _IOC_SIZE(ioctl->cmd);
+	usize = asize = _IOC_SIZE(cmd);
+	if (hl_size > asize)
+		asize = hl_size;
+
+	cmd = ioctl->cmd;
+
+	if (cmd & (IOC_IN | IOC_OUT)) {
+		if (asize <= sizeof(stack_kdata)) {
+			kdata = stack_kdata;
+		} else {
+			kdata = kzalloc(asize, GFP_KERNEL);
+			if (!kdata) {
+				retcode = -ENOMEM;
+				goto out_err;
+			}
+		}
+	}
+
+	if (cmd & IOC_IN) {
+		if (copy_from_user(kdata, (void __user *)arg, usize)) {
+			retcode = -EFAULT;
+			goto out_err;
+		}
+	}
+
+	retcode = func(hpriv, kdata);
+
+	if ((cmd & IOC_OUT) && copy_to_user((void __user *)arg, kdata, usize))
+		retcode = -EFAULT;
+
+out_err:
+	if (retcode)
+		dev_dbg_ratelimited(dev,
+				"error in ioctl: pid=%d, comm=\"%s\", cmd=%#010x, nr=%#04x\n",
+				task_pid_nr(current), current->comm, cmd, nr);
+
+	if (kdata != stack_kdata)
+		kfree(kdata);
+
+	return retcode;
+}
+
+long hl_ioctl_control(struct file *filep, unsigned int cmd, unsigned long arg)
+{
+	struct hl_fpriv *hpriv = filep->private_data;
+	struct hl_device *hdev = hpriv->hdev;
+	const struct hl_ioctl_desc *ioctl = NULL;
+	unsigned int nr = _IOC_NR(cmd);
+
+	if (!hdev) {
+		pr_err_ratelimited("Sending ioctl after device was removed! Please close FD\n");
+		return -ENODEV;
+	}
+
+	if (nr == _IOC_NR(DRM_IOCTL_HL_INFO)) {
+		ioctl = &hl_ioctls_control[nr - HL_COMMAND_START];
+	} else {
+		dev_dbg_ratelimited(hdev->dev_ctrl,
+				"invalid ioctl: pid=%d, comm=\"%s\", cmd=%#010x, nr=%#04x\n",
+				task_pid_nr(current), current->comm, cmd, nr);
+		return -ENOTTY;
+	}
+
+	return _hl_ioctl(hpriv, cmd, arg, ioctl, hdev->dev_ctrl);
+}
diff --git a/drivers/accel/habanalabs/common/hldio.c b/drivers/accel/habanalabs/common/hldio.c
new file mode 100644
index 000000000000..083ae5610875
--- /dev/null
+++ b/drivers/accel/habanalabs/common/hldio.c
@@ -0,0 +1,437 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Copyright 2024 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ */
+
+#include "habanalabs.h"
+#include "hldio.h"
+#include <generated/uapi/linux/version.h>
+#include <linux/pci-p2pdma.h>
+#include <linux/blkdev.h>
+#include <linux/vmalloc.h>
+
+/*
+ * NVMe Direct I/O implementation for habanalabs driver
+ *
+ * ASSUMPTIONS
+ * ===========
+ * 1. No IOMMU (well, technically it can work with IOMMU, but it is *almost useless).
+ * 2. Only READ operations (can extend in the future).
+ * 3. No sparse files (can overcome this in the future).
+ * 4. Kernel version >= 6.9
+ * 5. Requiring page alignment is OK (I don't see a solution to this one right,
+ *    now, how do we read partial pages?)
+ * 6. Kernel compiled with CONFIG_PCI_P2PDMA. This requires a CUSTOM kernel.
+ *    Theoretically I have a slight idea on how this could be solvable, but it
+ *    is probably inacceptable for the upstream. Also may not work in the end.
+ * 7. Either make sure our cards and disks are under the same PCI bridge, or
+ *    compile a custom kernel to hack around this.
+ */
+
+#define IO_STABILIZE_TIMEOUT 10000000 /* 10 seconds in microseconds */
+
+/*
+ * This struct contains all the useful data I could milk out of the file handle
+ * provided by the user.
+ * @TODO: right now it is retrieved on each IO, but can be done once with some
+ * dedicated IOCTL, call it for example HL_REGISTER_HANDLE.
+ */
+struct hl_dio_fd {
+	/* Back pointer in case we need it in async completion */
+	struct hl_ctx *ctx;
+	/* Associated fd struct */
+	struct file *filp;
+};
+
+/*
+ * This is a single IO descriptor
+ */
+struct hl_direct_io {
+	struct hl_dio_fd f;
+	struct kiocb kio;
+	struct bio_vec *bv;
+	struct iov_iter iter;
+	u64 device_va;
+	u64 off_bytes;
+	u64 len_bytes;
+	u32 type;
+};
+
+bool hl_device_supports_nvme(struct hl_device *hdev)
+{
+	return hdev->asic_prop.supports_nvme;
+}
+
+static int hl_dio_fd_register(struct hl_ctx *ctx, int fd, struct hl_dio_fd *f)
+{
+	struct hl_device *hdev = ctx->hdev;
+	struct block_device *bd;
+	struct super_block *sb;
+	struct inode *inode;
+	struct gendisk *gd;
+	struct device *disk_dev;
+	int rc;
+
+	f->filp = fget(fd);
+	if (!f->filp) {
+		rc = -ENOENT;
+		goto out;
+	}
+
+	if (!(f->filp->f_flags & O_DIRECT)) {
+		dev_err(hdev->dev, "file is not in the direct mode\n");
+		rc = -EINVAL;
+		goto fput;
+	}
+
+	if (!f->filp->f_op->read_iter) {
+		dev_err(hdev->dev, "read iter is not supported, need to fall back to legacy\n");
+		rc = -EINVAL;
+		goto fput;
+	}
+
+	inode = file_inode(f->filp);
+	sb = inode->i_sb;
+	bd = sb->s_bdev;
+	gd = bd->bd_disk;
+
+	if (inode->i_blocks << sb->s_blocksize_bits < i_size_read(inode)) {
+		dev_err(hdev->dev, "sparse files are not currently supported\n");
+		rc = -EINVAL;
+		goto fput;
+	}
+
+	if (!bd || !gd) {
+		dev_err(hdev->dev, "invalid block device\n");
+		rc = -ENODEV;
+		goto fput;
+	}
+	/* Get the underlying device from the block device */
+	disk_dev = disk_to_dev(gd);
+	if (!dma_pci_p2pdma_supported(disk_dev)) {
+		dev_err(hdev->dev, "device does not support PCI P2P DMA\n");
+		rc = -EOPNOTSUPP;
+		goto fput;
+	}
+
+	/*
+	 * @TODO: Maybe we need additional checks here
+	 */
+
+	f->ctx = ctx;
+	rc = 0;
+
+	goto out;
+fput:
+	fput(f->filp);
+out:
+	return rc;
+}
+
+static void hl_dio_fd_unregister(struct hl_dio_fd *f)
+{
+	fput(f->filp);
+}
+
+static long hl_dio_count_io(struct hl_device *hdev)
+{
+	s64 sum = 0;
+	int i;
+
+	for_each_possible_cpu(i)
+		sum += per_cpu(*hdev->hldio.inflight_ios, i);
+
+	return sum;
+}
+
+static bool hl_dio_get_iopath(struct hl_ctx *ctx)
+{
+	struct hl_device *hdev = ctx->hdev;
+
+	if (hdev->hldio.io_enabled) {
+		this_cpu_inc(*hdev->hldio.inflight_ios);
+
+		/* Avoid race conditions */
+		if (!hdev->hldio.io_enabled) {
+			this_cpu_dec(*hdev->hldio.inflight_ios);
+			return false;
+		}
+
+		hl_ctx_get(ctx);
+
+		return true;
+	}
+
+	return false;
+}
+
+static void hl_dio_put_iopath(struct hl_ctx *ctx)
+{
+	struct hl_device *hdev = ctx->hdev;
+
+	hl_ctx_put(ctx);
+	this_cpu_dec(*hdev->hldio.inflight_ios);
+}
+
+static void hl_dio_set_io_enabled(struct hl_device *hdev, bool enabled)
+{
+	hdev->hldio.io_enabled = enabled;
+}
+
+static bool hl_dio_validate_io(struct hl_device *hdev, struct hl_direct_io *io)
+{
+	if ((u64)io->device_va & ~PAGE_MASK) {
+		dev_dbg(hdev->dev, "device address must be 4K aligned\n");
+		return false;
+	}
+
+	if (io->len_bytes & ~PAGE_MASK) {
+		dev_dbg(hdev->dev, "IO length must be 4K aligned\n");
+		return false;
+	}
+
+	if (io->off_bytes & ~PAGE_MASK) {
+		dev_dbg(hdev->dev, "IO offset must be 4K aligned\n");
+		return false;
+	}
+
+	return true;
+}
+
+static struct page *hl_dio_va2page(struct hl_device *hdev, struct hl_ctx *ctx, u64 device_va)
+{
+	struct hl_dio *hldio = &hdev->hldio;
+	u64 device_pa;
+	int rc, i;
+
+	rc = hl_mmu_va_to_pa(ctx, device_va, &device_pa);
+	if (rc) {
+		dev_err(hdev->dev, "device virtual address translation error: %#llx (%d)",
+				device_va, rc);
+		return NULL;
+	}
+
+	for (i = 0 ; i < hldio->np2prs ; ++i) {
+		if (device_pa >= hldio->p2prs[i].device_pa &&
+		    device_pa < hldio->p2prs[i].device_pa + hldio->p2prs[i].size)
+			return hldio->p2prs[i].p2ppages[(device_pa - hldio->p2prs[i].device_pa) >>
+				PAGE_SHIFT];
+	}
+
+	return NULL;
+}
+
+static ssize_t hl_direct_io(struct hl_device *hdev, struct hl_direct_io *io)
+{
+	u64 npages, device_va;
+	ssize_t rc;
+	int i;
+
+	if (!hl_dio_validate_io(hdev, io))
+		return -EINVAL;
+
+	if (!hl_dio_get_iopath(io->f.ctx)) {
+		dev_info(hdev->dev, "can't schedule a new IO, IO is disabled\n");
+		return -ESHUTDOWN;
+	}
+
+	init_sync_kiocb(&io->kio, io->f.filp);
+	io->kio.ki_pos = io->off_bytes;
+
+	npages = (io->len_bytes >> PAGE_SHIFT);
+
+	/* @TODO: this can be implemented smarter, vmalloc in iopath is not
+	 * ideal. Maybe some variation of genpool. Number of pages may differ
+	 * greatly, so maybe even use pools of different sizes and chose the
+	 * closest one.
+	 */
+	io->bv = vzalloc(npages * sizeof(struct bio_vec));
+	if (!io->bv)
+		return -ENOMEM;
+
+	for (i = 0, device_va = io->device_va; i < npages ; ++i, device_va += PAGE_SIZE) {
+		io->bv[i].bv_page = hl_dio_va2page(hdev, io->f.ctx, device_va);
+		if (!io->bv[i].bv_page) {
+			dev_err(hdev->dev, "error getting page struct for device va %#llx",
+					device_va);
+			rc = -EFAULT;
+			goto cleanup;
+		}
+		io->bv[i].bv_offset = 0;
+		io->bv[i].bv_len = PAGE_SIZE;
+	}
+
+	iov_iter_bvec(&io->iter, io->type, io->bv, 1, io->len_bytes);
+	if (io->f.filp->f_op && io->f.filp->f_op->read_iter)
+		rc = io->f.filp->f_op->read_iter(&io->kio, &io->iter);
+	else
+		rc = -EINVAL;
+
+cleanup:
+	vfree(io->bv);
+	hl_dio_put_iopath(io->f.ctx);
+
+	dev_dbg(hdev->dev, "IO ended with %ld\n", rc);
+
+	return rc;
+}
+
+/*
+ * @TODO: This function can be used as a callback for io completion under
+ * kio->ki_complete in order to implement async IO.
+ * Note that on more recent kernels there is no ret2.
+ */
+__maybe_unused static void hl_direct_io_complete(struct kiocb *kio, long ret, long ret2)
+{
+	struct hl_direct_io *io = container_of(kio, struct hl_direct_io, kio);
+
+	dev_dbg(io->f.ctx->hdev->dev, "IO completed with %ld\n", ret);
+
+	/* Do something to copy result to user / notify completion */
+
+	hl_dio_put_iopath(io->f.ctx);
+
+	hl_dio_fd_unregister(&io->f);
+}
+
+/*
+ * DMA disk to ASIC, wait for results. Must be invoked from the user context
+ */
+int hl_dio_ssd2hl(struct hl_device *hdev, struct hl_ctx *ctx, int fd,
+		  u64 device_va, off_t off_bytes, size_t len_bytes,
+		  size_t *len_read)
+{
+	struct hl_direct_io *io;
+	ssize_t rc;
+
+	dev_dbg(hdev->dev, "SSD2HL fd=%d va=%#llx len=%#lx\n", fd, device_va, len_bytes);
+
+	io = kzalloc(sizeof(*io), GFP_KERNEL);
+	if (!io) {
+		rc = -ENOMEM;
+		goto out;
+	}
+
+	*io = (struct hl_direct_io){
+		.device_va = device_va,
+		.len_bytes = len_bytes,
+		.off_bytes = off_bytes,
+		.type = READ,
+	};
+
+	rc = hl_dio_fd_register(ctx, fd, &io->f);
+	if (rc)
+		goto kfree_io;
+
+	rc = hl_direct_io(hdev, io);
+	if (rc >= 0) {
+		*len_read = rc;
+		rc = 0;
+	}
+
+	/* This shall be called only in the case of a sync IO */
+	hl_dio_fd_unregister(&io->f);
+kfree_io:
+	kfree(io);
+out:
+	return rc;
+}
+
+static void hl_p2p_region_fini(struct hl_device *hdev, struct hl_p2p_region *p2pr)
+{
+	if (p2pr->p2ppages) {
+		vfree(p2pr->p2ppages);
+		p2pr->p2ppages = NULL;
+	}
+
+	if (p2pr->p2pmem) {
+		dev_dbg(hdev->dev, "freeing P2P mem from %p, size=%#llx\n",
+				p2pr->p2pmem, p2pr->size);
+		pci_free_p2pmem(hdev->pdev, p2pr->p2pmem, p2pr->size);
+		p2pr->p2pmem = NULL;
+	}
+}
+
+void hl_p2p_region_fini_all(struct hl_device *hdev)
+{
+	int i;
+
+	for (i = 0 ; i < hdev->hldio.np2prs ; ++i)
+		hl_p2p_region_fini(hdev, &hdev->hldio.p2prs[i]);
+
+	kvfree(hdev->hldio.p2prs);
+	hdev->hldio.p2prs = NULL;
+	hdev->hldio.np2prs = 0;
+}
+
+int hl_p2p_region_init(struct hl_device *hdev, struct hl_p2p_region *p2pr)
+{
+	void *addr;
+	int rc, i;
+
+	/* Start by publishing our p2p memory */
+	rc = pci_p2pdma_add_resource(hdev->pdev, p2pr->bar, p2pr->size, p2pr->bar_offset);
+	if (rc) {
+		dev_err(hdev->dev, "error adding p2p resource: %d\n", rc);
+		goto err;
+	}
+
+	/* Alloc all p2p mem */
+	p2pr->p2pmem = pci_alloc_p2pmem(hdev->pdev, p2pr->size);
+	if (!p2pr->p2pmem) {
+		dev_err(hdev->dev, "error allocating p2p memory\n");
+		rc = -ENOMEM;
+		goto err;
+	}
+
+	p2pr->p2ppages = vmalloc((p2pr->size >> PAGE_SHIFT) * sizeof(struct page *));
+	if (!p2pr->p2ppages) {
+		rc = -ENOMEM;
+		goto err;
+	}
+
+	for (i = 0, addr = p2pr->p2pmem ; i < (p2pr->size >> PAGE_SHIFT) ; ++i, addr += PAGE_SIZE) {
+		p2pr->p2ppages[i] = virt_to_page(addr);
+		if (!p2pr->p2ppages[i]) {
+			rc = -EFAULT;
+			goto err;
+		}
+	}
+
+	return 0;
+err:
+	hl_p2p_region_fini(hdev, p2pr);
+	return rc;
+}
+
+int hl_dio_start(struct hl_device *hdev)
+{
+	dev_dbg(hdev->dev, "initializing HLDIO\n");
+
+	/* Initialize the IO counter and enable IO */
+	hdev->hldio.inflight_ios = alloc_percpu(s64);
+	if (!hdev->hldio.inflight_ios)
+		return -ENOMEM;
+
+	hl_dio_set_io_enabled(hdev, true);
+
+	return 0;
+}
+
+void hl_dio_stop(struct hl_device *hdev)
+{
+	dev_dbg(hdev->dev, "deinitializing HLDIO\n");
+
+	if (hdev->hldio.io_enabled) {
+		/* Wait for all the IO to finish */
+		hl_dio_set_io_enabled(hdev, false);
+		hl_poll_timeout_condition(hdev, !hl_dio_count_io(hdev), 1000, IO_STABILIZE_TIMEOUT);
+	}
+
+	if (hdev->hldio.inflight_ios) {
+		free_percpu(hdev->hldio.inflight_ios);
+		hdev->hldio.inflight_ios = NULL;
+	}
+}
diff --git a/drivers/accel/habanalabs/common/hldio.h b/drivers/accel/habanalabs/common/hldio.h
new file mode 100644
index 000000000000..2874388f2851
--- /dev/null
+++ b/drivers/accel/habanalabs/common/hldio.h
@@ -0,0 +1,146 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * hldio.h - NVMe Direct I/O (HLDIO) infrastructure for Habana Labs Driver
+ *
+ * This feature requires specific hardware setup and must not be built
+ * under COMPILE_TEST.
+ */
+
+#ifndef __HL_HLDIO_H__
+#define __HL_HLDIO_H__
+
+#include <linux/types.h>
+#include <linux/fs.h>
+#include <linux/seq_file.h>
+#include <linux/ktime.h>     /* ktime functions */
+#include <linux/delay.h>     /* usleep_range */
+#include <linux/kernel.h>    /* might_sleep_if */
+#include <linux/errno.h>     /* error codes */
+
+/* Forward declarations */
+struct hl_device;
+struct file;
+
+/* Enable only if Kconfig selected */
+#ifdef CONFIG_HL_HLDIO
+/**
+ * struct hl_p2p_region - describes a single P2P memory region
+ * @p2ppages: array of page structs for the P2P memory
+ * @p2pmem: virtual address of the P2P memory region
+ * @device_pa: physical address on the device
+ * @bar_offset: offset within the BAR
+ * @size: size of the region in bytes
+ * @bar: BAR number containing this region
+ */
+struct hl_p2p_region {
+	struct page **p2ppages;
+	void *p2pmem;
+	u64 device_pa;
+	u64 bar_offset;
+	u64 size;
+	int bar;
+};
+
+/**
+ * struct hl_dio_stats - Direct I/O statistics
+ * @total_ops: total number of operations attempted
+ * @successful_ops: number of successful operations
+ * @failed_ops: number of failed operations
+ * @bytes_transferred: total bytes successfully transferred
+ * @last_len_read: length of the last read operation
+ */
+struct hl_dio_stats {
+	u64 total_ops;
+	u64 successful_ops;
+	u64 failed_ops;
+	u64 bytes_transferred;
+	size_t last_len_read;
+};
+
+/**
+ * struct hl_dio - describes habanalabs direct storage interaction interface
+ * @p2prs: array of p2p regions
+ * @inflight_ios: percpu counter for inflight ios
+ * @np2prs: number of elements in p2prs
+ * @io_enabled: 1 if io is enabled 0 otherwise
+ */
+struct hl_dio {
+	struct hl_p2p_region *p2prs;
+	s64 __percpu *inflight_ios;
+	u8 np2prs;
+	u8 io_enabled;
+};
+
+int hl_dio_ssd2hl(struct hl_device *hdev, struct hl_ctx *ctx, int fd,
+		  u64 device_va, off_t off_bytes, size_t len_bytes,
+		  size_t *len_read);
+void hl_p2p_region_fini_all(struct hl_device *hdev);
+int hl_p2p_region_init(struct hl_device *hdev, struct hl_p2p_region *p2pr);
+int hl_dio_start(struct hl_device *hdev);
+void hl_dio_stop(struct hl_device *hdev);
+
+/* Init/teardown */
+int hl_hldio_init(struct hl_device *hdev);
+void hl_hldio_fini(struct hl_device *hdev);
+
+/* File operations */
+long hl_hldio_ioctl(struct file *filep, unsigned int cmd, unsigned long arg);
+
+/* DebugFS hooks */
+#ifdef CONFIG_DEBUG_FS
+void hl_hldio_debugfs_init(struct hl_device *hdev);
+void hl_hldio_debugfs_fini(struct hl_device *hdev);
+#else
+static inline void hl_hldio_debugfs_init(struct hl_device *hdev) { }
+static inline void hl_hldio_debugfs_fini(struct hl_device *hdev) { }
+#endif
+
+#else /* !CONFIG_HL_HLDIO */
+
+struct hl_p2p_region;
+/* Stubs when HLDIO is disabled */
+static inline int hl_dio_ssd2hl(struct hl_device *hdev, struct hl_ctx *ctx, int fd,
+		  u64 device_va, off_t off_bytes, size_t len_bytes,
+		  size_t *len_read)
+{ return -EOPNOTSUPP; }
+static inline void hl_p2p_region_fini_all(struct hl_device *hdev) {}
+static inline int hl_p2p_region_init(struct hl_device *hdev, struct hl_p2p_region *p2pr)
+{ return -EOPNOTSUPP; }
+static inline int hl_dio_start(struct hl_device *hdev) { return -EOPNOTSUPP; }
+static inline void hl_dio_stop(struct hl_device *hdev) {}
+
+static inline int hl_hldio_init(struct hl_device *hdev) { return 0; }
+static inline void hl_hldio_fini(struct hl_device *hdev) { }
+static inline long hl_hldio_ioctl(struct file *f, unsigned int c,
+				  unsigned long a)
+{ return -ENOTTY; }
+static inline void hl_hldio_debugfs_init(struct hl_device *hdev) { }
+static inline void hl_hldio_debugfs_fini(struct hl_device *hdev) { }
+
+#endif /* CONFIG_HL_HLDIO */
+
+/* Simplified polling macro for HLDIO (no simulator support) */
+#define hl_poll_timeout_condition(hdev, cond, sleep_us, timeout_us) \
+({ \
+	ktime_t __timeout = ktime_add_us(ktime_get(), timeout_us); \
+	might_sleep_if(sleep_us); \
+	(void)(hdev); /* keep signature consistent, hdev unused */ \
+	for (;;) { \
+		mb(); /* ensure ordering of memory operations */ \
+		if (cond) \
+			break; \
+		if (timeout_us && ktime_compare(ktime_get(), __timeout) > 0) \
+			break; \
+		if (sleep_us) \
+			usleep_range((sleep_us >> 2) + 1, sleep_us); \
+	} \
+	(cond) ? 0 : -ETIMEDOUT; \
+})
+
+#ifdef CONFIG_HL_HLDIO
+bool hl_device_supports_nvme(struct hl_device *hdev);
+#else
+static inline bool hl_device_supports_nvme(struct hl_device *hdev) { return false; }
+#endif
+
+#endif /* __HL_HLDIO_H__ */
diff --git a/drivers/accel/habanalabs/common/hw_queue.c b/drivers/accel/habanalabs/common/hw_queue.c
new file mode 100644
index 000000000000..3d04a7507cce
--- /dev/null
+++ b/drivers/accel/habanalabs/common/hw_queue.c
@@ -0,0 +1,1154 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Copyright 2016-2019 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ */
+
+#include "habanalabs.h"
+
+#include <linux/slab.h>
+
+/*
+ * hl_queue_add_ptr - add to pi or ci and checks if it wraps around
+ *
+ * @ptr: the current pi/ci value
+ * @val: the amount to add
+ *
+ * Add val to ptr. It can go until twice the queue length.
+ */
+inline u32 hl_hw_queue_add_ptr(u32 ptr, u16 val)
+{
+	ptr += val;
+	ptr &= ((HL_QUEUE_LENGTH << 1) - 1);
+	return ptr;
+}
+static inline int queue_ci_get(atomic_t *ci, u32 queue_len)
+{
+	return atomic_read(ci) & ((queue_len << 1) - 1);
+}
+
+static inline int queue_free_slots(struct hl_hw_queue *q, u32 queue_len)
+{
+	int delta = (q->pi - queue_ci_get(&q->ci, queue_len));
+
+	if (delta >= 0)
+		return (queue_len - delta);
+	else
+		return (abs(delta) - queue_len);
+}
+
+void hl_hw_queue_update_ci(struct hl_cs *cs)
+{
+	struct hl_device *hdev = cs->ctx->hdev;
+	struct hl_hw_queue *q;
+	int i;
+
+	if (hdev->disabled)
+		return;
+
+	q = &hdev->kernel_queues[0];
+
+	/* There are no internal queues if H/W queues are being used */
+	if (!hdev->asic_prop.max_queues || q->queue_type == QUEUE_TYPE_HW)
+		return;
+
+	/* We must increment CI for every queue that will never get a
+	 * completion, there are 2 scenarios this can happen:
+	 * 1. All queues of a non completion CS will never get a completion.
+	 * 2. Internal queues never gets completion.
+	 */
+	for (i = 0 ; i < hdev->asic_prop.max_queues ; i++, q++) {
+		if (!cs_needs_completion(cs) || q->queue_type == QUEUE_TYPE_INT)
+			atomic_add(cs->jobs_in_queue_cnt[i], &q->ci);
+	}
+}
+
+/*
+ * hl_hw_queue_submit_bd() - Submit a buffer descriptor to an external or a
+ *                                H/W queue.
+ * @hdev: pointer to habanalabs device structure
+ * @q: pointer to habanalabs queue structure
+ * @ctl: BD's control word
+ * @len: BD's length
+ * @ptr: BD's pointer
+ *
+ * This function assumes there is enough space on the queue to submit a new
+ * BD to it. It initializes the next BD and calls the device specific
+ * function to set the pi (and doorbell)
+ *
+ * This function must be called when the scheduler mutex is taken
+ *
+ */
+void hl_hw_queue_submit_bd(struct hl_device *hdev, struct hl_hw_queue *q,
+		u32 ctl, u32 len, u64 ptr)
+{
+	struct hl_bd *bd;
+	u64 addr;
+	int i;
+
+	bd = q->kernel_address;
+	bd += hl_pi_2_offset(q->pi);
+	bd->ctl = cpu_to_le32(ctl);
+	bd->len = cpu_to_le32(len);
+	bd->ptr = cpu_to_le64(ptr);
+
+	if (q->dram_bd)
+		for (i = 0 ; i < 2 ; i++) {
+			addr = q->pq_dram_address +
+			((hl_pi_2_offset(q->pi) * sizeof(struct hl_bd))	+ (i * sizeof(u64)));
+			hdev->asic_funcs->access_dev_mem(hdev, PCI_REGION_DRAM,	addr,
+						(u64 *)(bd) + i, DEBUGFS_WRITE64);
+		}
+
+	q->pi = hl_queue_inc_ptr(q->pi);
+
+	hdev->asic_funcs->ring_doorbell(hdev, q->hw_queue_id, q->pi);
+}
+
+/*
+ * ext_queue_sanity_checks - perform some sanity checks on external queue
+ *
+ * @hdev              : pointer to hl_device structure
+ * @q                 :	pointer to hl_hw_queue structure
+ * @num_of_entries    : how many entries to check for space
+ * @reserve_cq_entry  :	whether to reserve an entry in the cq
+ *
+ * H/W queues spinlock should be taken before calling this function
+ *
+ * Perform the following:
+ * - Make sure we have enough space in the h/w queue
+ * - Make sure we have enough space in the completion queue
+ * - Reserve space in the completion queue (needs to be reversed if there
+ *   is a failure down the road before the actual submission of work). Only
+ *   do this action if reserve_cq_entry is true
+ *
+ */
+static int ext_queue_sanity_checks(struct hl_device *hdev,
+				struct hl_hw_queue *q, int num_of_entries,
+				bool reserve_cq_entry)
+{
+	atomic_t *free_slots =
+			&hdev->completion_queue[q->cq_id].free_slots_cnt;
+	int free_slots_cnt;
+
+	/* Check we have enough space in the queue */
+	free_slots_cnt = queue_free_slots(q, HL_QUEUE_LENGTH);
+
+	if (free_slots_cnt < num_of_entries) {
+		dev_dbg(hdev->dev, "Queue %d doesn't have room for %d CBs\n",
+			q->hw_queue_id, num_of_entries);
+		return -EAGAIN;
+	}
+
+	if (reserve_cq_entry) {
+		/*
+		 * Check we have enough space in the completion queue
+		 * Add -1 to counter (decrement) unless counter was already 0
+		 * In that case, CQ is full so we can't submit a new CB because
+		 * we won't get ack on its completion
+		 * atomic_add_unless will return 0 if counter was already 0
+		 */
+		if (atomic_add_negative(num_of_entries * -1, free_slots)) {
+			dev_dbg(hdev->dev, "No space for %d on CQ %d\n",
+				num_of_entries, q->hw_queue_id);
+			atomic_add(num_of_entries, free_slots);
+			return -EAGAIN;
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * int_queue_sanity_checks - perform some sanity checks on internal queue
+ *
+ * @hdev              : pointer to hl_device structure
+ * @q                 :	pointer to hl_hw_queue structure
+ * @num_of_entries    : how many entries to check for space
+ *
+ * H/W queues spinlock should be taken before calling this function
+ *
+ * Perform the following:
+ * - Make sure we have enough space in the h/w queue
+ *
+ */
+static int int_queue_sanity_checks(struct hl_device *hdev,
+					struct hl_hw_queue *q,
+					int num_of_entries)
+{
+	int free_slots_cnt;
+
+	if (num_of_entries > q->int_queue_len) {
+		dev_err(hdev->dev,
+			"Cannot populate queue %u with %u jobs\n",
+			q->hw_queue_id, num_of_entries);
+		return -ENOMEM;
+	}
+
+	/* Check we have enough space in the queue */
+	free_slots_cnt = queue_free_slots(q, q->int_queue_len);
+
+	if (free_slots_cnt < num_of_entries) {
+		dev_dbg(hdev->dev, "Queue %d doesn't have room for %d CBs\n",
+			q->hw_queue_id, num_of_entries);
+		return -EAGAIN;
+	}
+
+	return 0;
+}
+
+/*
+ * hw_queue_sanity_checks() - Make sure we have enough space in the h/w queue
+ * @hdev: Pointer to hl_device structure.
+ * @q: Pointer to hl_hw_queue structure.
+ * @num_of_entries: How many entries to check for space.
+ *
+ * Notice: We do not reserve queue entries so this function mustn't be called
+ *         more than once per CS for the same queue
+ *
+ */
+static int hw_queue_sanity_checks(struct hl_device *hdev, struct hl_hw_queue *q,
+					int num_of_entries)
+{
+	int free_slots_cnt;
+
+	/* Check we have enough space in the queue */
+	free_slots_cnt = queue_free_slots(q, HL_QUEUE_LENGTH);
+
+	if (free_slots_cnt < num_of_entries) {
+		dev_dbg(hdev->dev, "Queue %d doesn't have room for %d CBs\n",
+			q->hw_queue_id, num_of_entries);
+		return -EAGAIN;
+	}
+
+	return 0;
+}
+
+/*
+ * hl_hw_queue_send_cb_no_cmpl - send a single CB (not a JOB) without completion
+ *
+ * @hdev: pointer to hl_device structure
+ * @hw_queue_id: Queue's type
+ * @cb_size: size of CB
+ * @cb_ptr: pointer to CB location
+ *
+ * This function sends a single CB, that must NOT generate a completion entry.
+ * Sending CPU messages can be done instead via 'hl_hw_queue_submit_bd()'
+ */
+int hl_hw_queue_send_cb_no_cmpl(struct hl_device *hdev, u32 hw_queue_id,
+				u32 cb_size, u64 cb_ptr)
+{
+	struct hl_hw_queue *q = &hdev->kernel_queues[hw_queue_id];
+	int rc = 0;
+
+	hdev->asic_funcs->hw_queues_lock(hdev);
+
+	if (hdev->disabled) {
+		rc = -EPERM;
+		goto out;
+	}
+
+	/*
+	 * hl_hw_queue_send_cb_no_cmpl() is called for queues of a H/W queue
+	 * type only on init phase, when the queues are empty and being tested,
+	 * so there is no need for sanity checks.
+	 */
+	if (q->queue_type != QUEUE_TYPE_HW) {
+		rc = ext_queue_sanity_checks(hdev, q, 1, false);
+		if (rc)
+			goto out;
+	}
+
+	hl_hw_queue_submit_bd(hdev, q, 0, cb_size, cb_ptr);
+
+out:
+	hdev->asic_funcs->hw_queues_unlock(hdev);
+
+	return rc;
+}
+
+/*
+ * ext_queue_schedule_job - submit a JOB to an external queue
+ *
+ * @job: pointer to the job that needs to be submitted to the queue
+ *
+ * This function must be called when the scheduler mutex is taken
+ *
+ */
+static void ext_queue_schedule_job(struct hl_cs_job *job)
+{
+	struct hl_device *hdev = job->cs->ctx->hdev;
+	struct hl_hw_queue *q = &hdev->kernel_queues[job->hw_queue_id];
+	struct hl_cq_entry cq_pkt;
+	struct hl_cq *cq;
+	u64 cq_addr;
+	struct hl_cb *cb;
+	u32 ctl;
+	u32 len;
+	u64 ptr;
+
+	/*
+	 * Update the JOB ID inside the BD CTL so the device would know what
+	 * to write in the completion queue
+	 */
+	ctl = ((q->pi << BD_CTL_SHADOW_INDEX_SHIFT) & BD_CTL_SHADOW_INDEX_MASK);
+
+	cb = job->patched_cb;
+	len = job->job_cb_size;
+	ptr = cb->bus_address;
+
+	/* Skip completion flow in case this is a non completion CS */
+	if (!cs_needs_completion(job->cs))
+		goto submit_bd;
+
+	cq_pkt.data = cpu_to_le32(
+			((q->pi << CQ_ENTRY_SHADOW_INDEX_SHIFT)
+				& CQ_ENTRY_SHADOW_INDEX_MASK) |
+			FIELD_PREP(CQ_ENTRY_SHADOW_INDEX_VALID_MASK, 1) |
+			FIELD_PREP(CQ_ENTRY_READY_MASK, 1));
+
+	/*
+	 * No need to protect pi_offset because scheduling to the
+	 * H/W queues is done under the scheduler mutex
+	 *
+	 * No need to check if CQ is full because it was already
+	 * checked in ext_queue_sanity_checks
+	 */
+	cq = &hdev->completion_queue[q->cq_id];
+	cq_addr = cq->bus_address + cq->pi * sizeof(struct hl_cq_entry);
+
+	hdev->asic_funcs->add_end_of_cb_packets(hdev, cb->kernel_address, len,
+						job->user_cb_size,
+						cq_addr,
+						le32_to_cpu(cq_pkt.data),
+						q->msi_vec,
+						job->contains_dma_pkt);
+
+	q->shadow_queue[hl_pi_2_offset(q->pi)] = job;
+
+	cq->pi = hl_cq_inc_ptr(cq->pi);
+
+submit_bd:
+	hl_hw_queue_submit_bd(hdev, q, ctl, len, ptr);
+}
+
+/*
+ * int_queue_schedule_job - submit a JOB to an internal queue
+ *
+ * @job: pointer to the job that needs to be submitted to the queue
+ *
+ * This function must be called when the scheduler mutex is taken
+ *
+ */
+static void int_queue_schedule_job(struct hl_cs_job *job)
+{
+	struct hl_device *hdev = job->cs->ctx->hdev;
+	struct hl_hw_queue *q = &hdev->kernel_queues[job->hw_queue_id];
+	struct hl_bd bd;
+	__le64 *pi;
+
+	bd.ctl = 0;
+	bd.len = cpu_to_le32(job->job_cb_size);
+
+	if (job->is_kernel_allocated_cb)
+		/* bus_address is actually a mmu mapped address
+		 * allocated from an internal pool
+		 */
+		bd.ptr = cpu_to_le64(job->user_cb->bus_address);
+	else
+		bd.ptr = cpu_to_le64((u64) (uintptr_t) job->user_cb);
+
+	pi = q->kernel_address + (q->pi & (q->int_queue_len - 1)) * sizeof(bd);
+
+	q->pi++;
+	q->pi &= ((q->int_queue_len << 1) - 1);
+
+	hdev->asic_funcs->pqe_write(hdev, pi, &bd);
+
+	hdev->asic_funcs->ring_doorbell(hdev, q->hw_queue_id, q->pi);
+}
+
+/*
+ * hw_queue_schedule_job - submit a JOB to a H/W queue
+ *
+ * @job: pointer to the job that needs to be submitted to the queue
+ *
+ * This function must be called when the scheduler mutex is taken
+ *
+ */
+static void hw_queue_schedule_job(struct hl_cs_job *job)
+{
+	struct hl_device *hdev = job->cs->ctx->hdev;
+	struct hl_hw_queue *q = &hdev->kernel_queues[job->hw_queue_id];
+	u64 ptr;
+	u32 offset, ctl, len;
+
+	/*
+	 * Upon PQE completion, COMP_DATA is used as the write data to the
+	 * completion queue (QMAN HBW message), and COMP_OFFSET is used as the
+	 * write address offset in the SM block (QMAN LBW message).
+	 * The write address offset is calculated as "COMP_OFFSET << 2".
+	 */
+	offset = job->cs->sequence & (hdev->asic_prop.max_pending_cs - 1);
+	ctl = ((offset << BD_CTL_COMP_OFFSET_SHIFT) & BD_CTL_COMP_OFFSET_MASK) |
+		((q->pi << BD_CTL_COMP_DATA_SHIFT) & BD_CTL_COMP_DATA_MASK);
+
+	len = job->job_cb_size;
+
+	/*
+	 * A patched CB is created only if a user CB was allocated by driver and
+	 * MMU is disabled. If MMU is enabled, the user CB should be used
+	 * instead. If the user CB wasn't allocated by driver, assume that it
+	 * holds an address.
+	 */
+	if (job->patched_cb)
+		ptr = job->patched_cb->bus_address;
+	else if (job->is_kernel_allocated_cb)
+		ptr = job->user_cb->bus_address;
+	else
+		ptr = (u64) (uintptr_t) job->user_cb;
+
+	hl_hw_queue_submit_bd(hdev, q, ctl, len, ptr);
+}
+
+static int init_signal_cs(struct hl_device *hdev,
+		struct hl_cs_job *job, struct hl_cs_compl *cs_cmpl)
+{
+	struct hl_sync_stream_properties *prop;
+	struct hl_hw_sob *hw_sob;
+	u32 q_idx;
+	int rc = 0;
+
+	q_idx = job->hw_queue_id;
+	prop = &hdev->kernel_queues[q_idx].sync_stream_prop;
+	hw_sob = &prop->hw_sob[prop->curr_sob_offset];
+
+	cs_cmpl->hw_sob = hw_sob;
+	cs_cmpl->sob_val = prop->next_sob_val;
+
+	dev_dbg(hdev->dev,
+		"generate signal CB, sob_id: %d, sob val: %u, q_idx: %d, seq: %llu\n",
+		cs_cmpl->hw_sob->sob_id, cs_cmpl->sob_val, q_idx,
+		cs_cmpl->cs_seq);
+
+	/* we set an EB since we must make sure all oeprations are done
+	 * when sending the signal
+	 */
+	hdev->asic_funcs->gen_signal_cb(hdev, job->patched_cb,
+				cs_cmpl->hw_sob->sob_id, 0, true);
+
+	rc = hl_cs_signal_sob_wraparound_handler(hdev, q_idx, &hw_sob, 1,
+								false);
+
+	job->cs->sob_addr_offset = hw_sob->sob_addr;
+	job->cs->initial_sob_count = prop->next_sob_val - 1;
+
+	return rc;
+}
+
+void hl_hw_queue_encaps_sig_set_sob_info(struct hl_device *hdev,
+			struct hl_cs *cs, struct hl_cs_job *job,
+			struct hl_cs_compl *cs_cmpl)
+{
+	struct hl_cs_encaps_sig_handle *handle = cs->encaps_sig_hdl;
+	u32 offset = 0;
+
+	cs_cmpl->hw_sob = handle->hw_sob;
+
+	/* Note that encaps_sig_wait_offset was validated earlier in the flow
+	 * for offset value which exceeds the max reserved signal count.
+	 * always decrement 1 of the offset since when the user
+	 * set offset 1 for example he mean to wait only for the first
+	 * signal only, which will be pre_sob_val, and if he set offset 2
+	 * then the value required is (pre_sob_val + 1) and so on...
+	 * if user set wait offset to 0, then treat it as legacy wait cs,
+	 * wait for the next signal.
+	 */
+	if (job->encaps_sig_wait_offset)
+		offset = job->encaps_sig_wait_offset - 1;
+
+	cs_cmpl->sob_val = handle->pre_sob_val + offset;
+}
+
+static int init_wait_cs(struct hl_device *hdev, struct hl_cs *cs,
+		struct hl_cs_job *job, struct hl_cs_compl *cs_cmpl)
+{
+	struct hl_gen_wait_properties wait_prop;
+	struct hl_sync_stream_properties *prop;
+	struct hl_cs_compl *signal_cs_cmpl;
+	u32 q_idx;
+
+	q_idx = job->hw_queue_id;
+	prop = &hdev->kernel_queues[q_idx].sync_stream_prop;
+
+	signal_cs_cmpl = container_of(cs->signal_fence,
+					struct hl_cs_compl,
+					base_fence);
+
+	if (cs->encaps_signals) {
+		/* use the encaps signal handle stored earlier in the flow
+		 * and set the SOB information from the encaps
+		 * signals handle
+		 */
+		hl_hw_queue_encaps_sig_set_sob_info(hdev, cs, job, cs_cmpl);
+
+		dev_dbg(hdev->dev, "Wait for encaps signals handle, qidx(%u), CS sequence(%llu), sob val: 0x%x, offset: %u\n",
+				cs->encaps_sig_hdl->q_idx,
+				cs->encaps_sig_hdl->cs_seq,
+				cs_cmpl->sob_val,
+				job->encaps_sig_wait_offset);
+	} else {
+		/* Copy the SOB id and value of the signal CS */
+		cs_cmpl->hw_sob = signal_cs_cmpl->hw_sob;
+		cs_cmpl->sob_val = signal_cs_cmpl->sob_val;
+	}
+
+	/* check again if the signal cs already completed.
+	 * if yes then don't send any wait cs since the hw_sob
+	 * could be in reset already. if signal is not completed
+	 * then get refcount to hw_sob to prevent resetting the sob
+	 * while wait cs is not submitted.
+	 * note that this check is protected by two locks,
+	 * hw queue lock and completion object lock,
+	 * and the same completion object lock also protects
+	 * the hw_sob reset handler function.
+	 * The hw_queue lock prevent out of sync of hw_sob
+	 * refcount value, changed by signal/wait flows.
+	 */
+	spin_lock(&signal_cs_cmpl->lock);
+
+	if (completion_done(&cs->signal_fence->completion)) {
+		spin_unlock(&signal_cs_cmpl->lock);
+		return -EINVAL;
+	}
+
+	kref_get(&cs_cmpl->hw_sob->kref);
+
+	spin_unlock(&signal_cs_cmpl->lock);
+
+	dev_dbg(hdev->dev,
+		"generate wait CB, sob_id: %d, sob_val: 0x%x, mon_id: %d, q_idx: %d, seq: %llu\n",
+		cs_cmpl->hw_sob->sob_id, cs_cmpl->sob_val,
+		prop->base_mon_id, q_idx, cs->sequence);
+
+	wait_prop.data = (void *) job->patched_cb;
+	wait_prop.sob_base = cs_cmpl->hw_sob->sob_id;
+	wait_prop.sob_mask = 0x1;
+	wait_prop.sob_val = cs_cmpl->sob_val;
+	wait_prop.mon_id = prop->base_mon_id;
+	wait_prop.q_idx = q_idx;
+	wait_prop.size = 0;
+
+	hdev->asic_funcs->gen_wait_cb(hdev, &wait_prop);
+
+	mb();
+	hl_fence_put(cs->signal_fence);
+	cs->signal_fence = NULL;
+
+	return 0;
+}
+
+/*
+ * init_signal_wait_cs - initialize a signal/wait CS
+ * @cs: pointer to the signal/wait CS
+ *
+ * H/W queues spinlock should be taken before calling this function
+ */
+static int init_signal_wait_cs(struct hl_cs *cs)
+{
+	struct hl_ctx *ctx = cs->ctx;
+	struct hl_device *hdev = ctx->hdev;
+	struct hl_cs_job *job;
+	struct hl_cs_compl *cs_cmpl =
+			container_of(cs->fence, struct hl_cs_compl, base_fence);
+	int rc = 0;
+
+	/* There is only one job in a signal/wait CS */
+	job = list_first_entry(&cs->job_list, struct hl_cs_job,
+				cs_node);
+
+	if (cs->type & CS_TYPE_SIGNAL)
+		rc = init_signal_cs(hdev, job, cs_cmpl);
+	else if (cs->type & CS_TYPE_WAIT)
+		rc = init_wait_cs(hdev, cs, job, cs_cmpl);
+
+	return rc;
+}
+
+static int encaps_sig_first_staged_cs_handler
+			(struct hl_device *hdev, struct hl_cs *cs)
+{
+	struct hl_cs_compl *cs_cmpl =
+			container_of(cs->fence,
+					struct hl_cs_compl, base_fence);
+	struct hl_cs_encaps_sig_handle *encaps_sig_hdl;
+	struct hl_encaps_signals_mgr *mgr;
+	int rc = 0;
+
+	mgr = &cs->ctx->sig_mgr;
+
+	spin_lock(&mgr->lock);
+	encaps_sig_hdl = idr_find(&mgr->handles, cs->encaps_sig_hdl_id);
+	if (encaps_sig_hdl) {
+		/*
+		 * Set handler CS sequence,
+		 * the CS which contains the encapsulated signals.
+		 */
+		encaps_sig_hdl->cs_seq = cs->sequence;
+		/* store the handle and set encaps signal indication,
+		 * to be used later in cs_do_release to put the last
+		 * reference to encaps signals handlers.
+		 */
+		cs_cmpl->encaps_signals = true;
+		cs_cmpl->encaps_sig_hdl = encaps_sig_hdl;
+
+		/* set hw_sob pointer in completion object
+		 * since it's used in cs_do_release flow to put
+		 * refcount to sob
+		 */
+		cs_cmpl->hw_sob = encaps_sig_hdl->hw_sob;
+		cs_cmpl->sob_val = encaps_sig_hdl->pre_sob_val +
+						encaps_sig_hdl->count;
+
+		dev_dbg(hdev->dev, "CS seq (%llu) added to encaps signal handler id (%u), count(%u), qidx(%u), sob(%u), val(%u)\n",
+				cs->sequence, encaps_sig_hdl->id,
+				encaps_sig_hdl->count,
+				encaps_sig_hdl->q_idx,
+				cs_cmpl->hw_sob->sob_id,
+				cs_cmpl->sob_val);
+
+	} else {
+		dev_err(hdev->dev, "encaps handle id(%u) wasn't found!\n",
+				cs->encaps_sig_hdl_id);
+		rc = -EINVAL;
+	}
+
+	spin_unlock(&mgr->lock);
+
+	return rc;
+}
+
+/*
+ * hl_hw_queue_schedule_cs - schedule a command submission
+ * @cs: pointer to the CS
+ */
+int hl_hw_queue_schedule_cs(struct hl_cs *cs)
+{
+	enum hl_device_status status;
+	struct hl_cs_counters_atomic *cntr;
+	struct hl_ctx *ctx = cs->ctx;
+	struct hl_device *hdev = ctx->hdev;
+	struct hl_cs_job *job, *tmp;
+	struct hl_hw_queue *q;
+	int rc = 0, i, cq_cnt;
+	bool first_entry;
+	u32 max_queues;
+
+	cntr = &hdev->aggregated_cs_counters;
+
+	hdev->asic_funcs->hw_queues_lock(hdev);
+
+	if (!hl_device_operational(hdev, &status)) {
+		atomic64_inc(&cntr->device_in_reset_drop_cnt);
+		atomic64_inc(&ctx->cs_counters.device_in_reset_drop_cnt);
+		dev_err(hdev->dev,
+			"device is %s, CS rejected!\n", hdev->status[status]);
+		rc = -EPERM;
+		goto out;
+	}
+
+	max_queues = hdev->asic_prop.max_queues;
+
+	q = &hdev->kernel_queues[0];
+	for (i = 0, cq_cnt = 0 ; i < max_queues ; i++, q++) {
+		if (cs->jobs_in_queue_cnt[i]) {
+			switch (q->queue_type) {
+			case QUEUE_TYPE_EXT:
+				rc = ext_queue_sanity_checks(hdev, q,
+						cs->jobs_in_queue_cnt[i],
+						cs_needs_completion(cs) ?
+								true : false);
+				break;
+			case QUEUE_TYPE_INT:
+				rc = int_queue_sanity_checks(hdev, q,
+						cs->jobs_in_queue_cnt[i]);
+				break;
+			case QUEUE_TYPE_HW:
+				rc = hw_queue_sanity_checks(hdev, q,
+						cs->jobs_in_queue_cnt[i]);
+				break;
+			default:
+				dev_err(hdev->dev, "Queue type %d is invalid\n",
+					q->queue_type);
+				rc = -EINVAL;
+				break;
+			}
+
+			if (rc) {
+				atomic64_inc(
+					&ctx->cs_counters.queue_full_drop_cnt);
+				atomic64_inc(&cntr->queue_full_drop_cnt);
+				goto unroll_cq_resv;
+			}
+
+			if (q->queue_type == QUEUE_TYPE_EXT)
+				cq_cnt++;
+		}
+	}
+
+	if ((cs->type == CS_TYPE_SIGNAL) || (cs->type == CS_TYPE_WAIT)) {
+		rc = init_signal_wait_cs(cs);
+		if (rc)
+			goto unroll_cq_resv;
+	} else if (cs->type == CS_TYPE_COLLECTIVE_WAIT) {
+		rc = hdev->asic_funcs->collective_wait_init_cs(cs);
+		if (rc)
+			goto unroll_cq_resv;
+	}
+
+	rc = hdev->asic_funcs->pre_schedule_cs(cs);
+	if (rc) {
+		dev_err(hdev->dev,
+			"Failed in pre-submission operations of CS %d.%llu\n",
+			ctx->asid, cs->sequence);
+		goto unroll_cq_resv;
+	}
+
+	hdev->shadow_cs_queue[cs->sequence &
+				(hdev->asic_prop.max_pending_cs - 1)] = cs;
+
+	if (cs->encaps_signals && cs->staged_first) {
+		rc = encaps_sig_first_staged_cs_handler(hdev, cs);
+		if (rc)
+			goto unroll_cq_resv;
+	}
+
+	spin_lock(&hdev->cs_mirror_lock);
+
+	/* Verify staged CS exists and add to the staged list */
+	if (cs->staged_cs && !cs->staged_first) {
+		struct hl_cs *staged_cs;
+
+		staged_cs = hl_staged_cs_find_first(hdev, cs->staged_sequence);
+		if (!staged_cs) {
+			dev_err(hdev->dev,
+				"Cannot find staged submission sequence %llu",
+				cs->staged_sequence);
+			rc = -EINVAL;
+			goto unlock_cs_mirror;
+		}
+
+		if (is_staged_cs_last_exists(hdev, staged_cs)) {
+			dev_err(hdev->dev,
+				"Staged submission sequence %llu already submitted",
+				cs->staged_sequence);
+			rc = -EINVAL;
+			goto unlock_cs_mirror;
+		}
+
+		list_add_tail(&cs->staged_cs_node, &staged_cs->staged_cs_node);
+
+		/* update stream map of the first CS */
+		if (hdev->supports_wait_for_multi_cs)
+			staged_cs->fence->stream_master_qid_map |=
+					cs->fence->stream_master_qid_map;
+	}
+
+	list_add_tail(&cs->mirror_node, &hdev->cs_mirror_list);
+
+	/* Queue TDR if the CS is the first entry and if timeout is wanted */
+	first_entry = list_first_entry(&hdev->cs_mirror_list,
+					struct hl_cs, mirror_node) == cs;
+	if ((hdev->timeout_jiffies != MAX_SCHEDULE_TIMEOUT) &&
+				first_entry && cs_needs_timeout(cs)) {
+		cs->tdr_active = true;
+		schedule_delayed_work(&cs->work_tdr, cs->timeout_jiffies);
+
+	}
+
+	spin_unlock(&hdev->cs_mirror_lock);
+
+	list_for_each_entry_safe(job, tmp, &cs->job_list, cs_node)
+		switch (job->queue_type) {
+		case QUEUE_TYPE_EXT:
+			ext_queue_schedule_job(job);
+			break;
+		case QUEUE_TYPE_INT:
+			int_queue_schedule_job(job);
+			break;
+		case QUEUE_TYPE_HW:
+			hw_queue_schedule_job(job);
+			break;
+		default:
+			break;
+		}
+
+	cs->submitted = true;
+
+	goto out;
+
+unlock_cs_mirror:
+	spin_unlock(&hdev->cs_mirror_lock);
+unroll_cq_resv:
+	q = &hdev->kernel_queues[0];
+	for (i = 0 ; (i < max_queues) && (cq_cnt > 0) ; i++, q++) {
+		if ((q->queue_type == QUEUE_TYPE_EXT) &&
+						(cs->jobs_in_queue_cnt[i])) {
+			atomic_t *free_slots =
+				&hdev->completion_queue[i].free_slots_cnt;
+			atomic_add(cs->jobs_in_queue_cnt[i], free_slots);
+			cq_cnt--;
+		}
+	}
+
+out:
+	hdev->asic_funcs->hw_queues_unlock(hdev);
+
+	return rc;
+}
+
+/*
+ * hl_hw_queue_inc_ci_kernel - increment ci for kernel's queue
+ *
+ * @hdev: pointer to hl_device structure
+ * @hw_queue_id: which queue to increment its ci
+ */
+void hl_hw_queue_inc_ci_kernel(struct hl_device *hdev, u32 hw_queue_id)
+{
+	struct hl_hw_queue *q = &hdev->kernel_queues[hw_queue_id];
+
+	atomic_inc(&q->ci);
+}
+
+static int ext_and_cpu_queue_init(struct hl_device *hdev, struct hl_hw_queue *q,
+					bool is_cpu_queue)
+{
+	void *p;
+	int rc;
+
+	if (is_cpu_queue)
+		p = hl_cpu_accessible_dma_pool_alloc(hdev, HL_QUEUE_SIZE_IN_BYTES, &q->bus_address);
+	else
+		p = hl_asic_dma_alloc_coherent(hdev, HL_QUEUE_SIZE_IN_BYTES, &q->bus_address,
+						GFP_KERNEL | __GFP_ZERO);
+	if (!p)
+		return -ENOMEM;
+
+	q->kernel_address = p;
+
+	q->shadow_queue = kmalloc_array(HL_QUEUE_LENGTH, sizeof(struct hl_cs_job *), GFP_KERNEL);
+	if (!q->shadow_queue) {
+		dev_err(hdev->dev,
+			"Failed to allocate shadow queue for H/W queue %d\n",
+			q->hw_queue_id);
+		rc = -ENOMEM;
+		goto free_queue;
+	}
+
+	/* Make sure read/write pointers are initialized to start of queue */
+	atomic_set(&q->ci, 0);
+	q->pi = 0;
+
+	return 0;
+
+free_queue:
+	if (is_cpu_queue)
+		hl_cpu_accessible_dma_pool_free(hdev, HL_QUEUE_SIZE_IN_BYTES, q->kernel_address);
+	else
+		hl_asic_dma_free_coherent(hdev, HL_QUEUE_SIZE_IN_BYTES, q->kernel_address,
+						q->bus_address);
+
+	return rc;
+}
+
+static int int_queue_init(struct hl_device *hdev, struct hl_hw_queue *q)
+{
+	void *p;
+
+	p = hdev->asic_funcs->get_int_queue_base(hdev, q->hw_queue_id,
+					&q->bus_address, &q->int_queue_len);
+	if (!p) {
+		dev_err(hdev->dev,
+			"Failed to get base address for internal queue %d\n",
+			q->hw_queue_id);
+		return -EFAULT;
+	}
+
+	q->kernel_address = p;
+	q->pi = 0;
+	atomic_set(&q->ci, 0);
+
+	return 0;
+}
+
+static int cpu_queue_init(struct hl_device *hdev, struct hl_hw_queue *q)
+{
+	return ext_and_cpu_queue_init(hdev, q, true);
+}
+
+static int ext_queue_init(struct hl_device *hdev, struct hl_hw_queue *q)
+{
+	return ext_and_cpu_queue_init(hdev, q, false);
+}
+
+static int hw_queue_init(struct hl_device *hdev, struct hl_hw_queue *q)
+{
+	void *p;
+
+	p = hl_asic_dma_alloc_coherent(hdev, HL_QUEUE_SIZE_IN_BYTES, &q->bus_address,
+					GFP_KERNEL | __GFP_ZERO);
+	if (!p)
+		return -ENOMEM;
+
+	q->kernel_address = p;
+
+	/* Make sure read/write pointers are initialized to start of queue */
+	atomic_set(&q->ci, 0);
+	q->pi = 0;
+
+	return 0;
+}
+
+static void sync_stream_queue_init(struct hl_device *hdev, u32 q_idx)
+{
+	struct hl_sync_stream_properties *sync_stream_prop;
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct hl_hw_sob *hw_sob;
+	int sob, reserved_mon_idx, queue_idx;
+
+	sync_stream_prop = &hdev->kernel_queues[q_idx].sync_stream_prop;
+
+	/* We use 'collective_mon_idx' as a running index in order to reserve
+	 * monitors for collective master/slave queues.
+	 * collective master queue gets 2 reserved monitors
+	 * collective slave queue gets 1 reserved monitor
+	 */
+	if (hdev->kernel_queues[q_idx].collective_mode ==
+			HL_COLLECTIVE_MASTER) {
+		reserved_mon_idx = hdev->collective_mon_idx;
+
+		/* reserve the first monitor for collective master queue */
+		sync_stream_prop->collective_mstr_mon_id[0] =
+			prop->collective_first_mon + reserved_mon_idx;
+
+		/* reserve the second monitor for collective master queue */
+		sync_stream_prop->collective_mstr_mon_id[1] =
+			prop->collective_first_mon + reserved_mon_idx + 1;
+
+		hdev->collective_mon_idx += HL_COLLECTIVE_RSVD_MSTR_MONS;
+	} else if (hdev->kernel_queues[q_idx].collective_mode ==
+			HL_COLLECTIVE_SLAVE) {
+		reserved_mon_idx = hdev->collective_mon_idx++;
+
+		/* reserve a monitor for collective slave queue */
+		sync_stream_prop->collective_slave_mon_id =
+			prop->collective_first_mon + reserved_mon_idx;
+	}
+
+	if (!hdev->kernel_queues[q_idx].supports_sync_stream)
+		return;
+
+	queue_idx = hdev->sync_stream_queue_idx++;
+
+	sync_stream_prop->base_sob_id = prop->sync_stream_first_sob +
+			(queue_idx * HL_RSVD_SOBS);
+	sync_stream_prop->base_mon_id = prop->sync_stream_first_mon +
+			(queue_idx * HL_RSVD_MONS);
+	sync_stream_prop->next_sob_val = 1;
+	sync_stream_prop->curr_sob_offset = 0;
+
+	for (sob = 0 ; sob < HL_RSVD_SOBS ; sob++) {
+		hw_sob = &sync_stream_prop->hw_sob[sob];
+		hw_sob->hdev = hdev;
+		hw_sob->sob_id = sync_stream_prop->base_sob_id + sob;
+		hw_sob->sob_addr =
+			hdev->asic_funcs->get_sob_addr(hdev, hw_sob->sob_id);
+		hw_sob->q_idx = q_idx;
+		kref_init(&hw_sob->kref);
+	}
+}
+
+static void sync_stream_queue_reset(struct hl_device *hdev, u32 q_idx)
+{
+	struct hl_sync_stream_properties *prop =
+			&hdev->kernel_queues[q_idx].sync_stream_prop;
+
+	/*
+	 * In case we got here due to a stuck CS, the refcnt might be bigger
+	 * than 1 and therefore we reset it.
+	 */
+	kref_init(&prop->hw_sob[prop->curr_sob_offset].kref);
+	prop->curr_sob_offset = 0;
+	prop->next_sob_val = 1;
+}
+
+/*
+ * queue_init - main initialization function for H/W queue object
+ *
+ * @hdev: pointer to hl_device device structure
+ * @q: pointer to hl_hw_queue queue structure
+ * @hw_queue_id: The id of the H/W queue
+ *
+ * Allocate dma-able memory for the queue and initialize fields
+ * Returns 0 on success
+ */
+static int queue_init(struct hl_device *hdev, struct hl_hw_queue *q,
+			u32 hw_queue_id)
+{
+	int rc;
+
+	q->hw_queue_id = hw_queue_id;
+
+	switch (q->queue_type) {
+	case QUEUE_TYPE_EXT:
+		rc = ext_queue_init(hdev, q);
+		break;
+	case QUEUE_TYPE_INT:
+		rc = int_queue_init(hdev, q);
+		break;
+	case QUEUE_TYPE_CPU:
+		rc = cpu_queue_init(hdev, q);
+		break;
+	case QUEUE_TYPE_HW:
+		rc = hw_queue_init(hdev, q);
+		break;
+	case QUEUE_TYPE_NA:
+		q->valid = 0;
+		return 0;
+	default:
+		dev_crit(hdev->dev, "wrong queue type %d during init\n",
+			q->queue_type);
+		rc = -EINVAL;
+		break;
+	}
+
+	sync_stream_queue_init(hdev, q->hw_queue_id);
+
+	if (rc)
+		return rc;
+
+	q->valid = 1;
+
+	return 0;
+}
+
+/*
+ * hw_queue_fini - destroy queue
+ *
+ * @hdev: pointer to hl_device device structure
+ * @q: pointer to hl_hw_queue queue structure
+ *
+ * Free the queue memory
+ */
+static void queue_fini(struct hl_device *hdev, struct hl_hw_queue *q)
+{
+	if (!q->valid)
+		return;
+
+	/*
+	 * If we arrived here, there are no jobs waiting on this queue
+	 * so we can safely remove it.
+	 * This is because this function can only called when:
+	 * 1. Either a context is deleted, which only can occur if all its
+	 *    jobs were finished
+	 * 2. A context wasn't able to be created due to failure or timeout,
+	 *    which means there are no jobs on the queue yet
+	 *
+	 * The only exception are the queues of the kernel context, but
+	 * if they are being destroyed, it means that the entire module is
+	 * being removed. If the module is removed, it means there is no open
+	 * user context. It also means that if a job was submitted by
+	 * the kernel driver (e.g. context creation), the job itself was
+	 * released by the kernel driver when a timeout occurred on its
+	 * Completion. Thus, we don't need to release it again.
+	 */
+
+	if (q->queue_type == QUEUE_TYPE_INT)
+		return;
+
+	kfree(q->shadow_queue);
+
+	if (q->queue_type == QUEUE_TYPE_CPU)
+		hl_cpu_accessible_dma_pool_free(hdev, HL_QUEUE_SIZE_IN_BYTES, q->kernel_address);
+	else
+		hl_asic_dma_free_coherent(hdev, HL_QUEUE_SIZE_IN_BYTES, q->kernel_address,
+						q->bus_address);
+}
+
+int hl_hw_queues_create(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *asic = &hdev->asic_prop;
+	struct hl_hw_queue *q;
+	int i, rc, q_ready_cnt;
+
+	hdev->kernel_queues = kcalloc(asic->max_queues,
+				sizeof(*hdev->kernel_queues), GFP_KERNEL);
+
+	if (!hdev->kernel_queues) {
+		dev_err(hdev->dev, "Not enough memory for H/W queues\n");
+		return -ENOMEM;
+	}
+
+	/* Initialize the H/W queues */
+	for (i = 0, q_ready_cnt = 0, q = hdev->kernel_queues;
+			i < asic->max_queues ; i++, q_ready_cnt++, q++) {
+
+		q->queue_type = asic->hw_queues_props[i].type;
+		q->supports_sync_stream =
+				asic->hw_queues_props[i].supports_sync_stream;
+		q->collective_mode = asic->hw_queues_props[i].collective_mode;
+		q->dram_bd = asic->hw_queues_props[i].dram_bd;
+
+		rc = queue_init(hdev, q, i);
+		if (rc) {
+			dev_err(hdev->dev,
+				"failed to initialize queue %d\n", i);
+			goto release_queues;
+		}
+
+		/* Set DRAM PQ address for the queue if it should be at DRAM */
+		if (q->dram_bd)
+			q->pq_dram_address = asic->hw_queues_props[i].q_dram_bd_address;
+	}
+
+	return 0;
+
+release_queues:
+	for (i = 0, q = hdev->kernel_queues ; i < q_ready_cnt ; i++, q++)
+		queue_fini(hdev, q);
+
+	kfree(hdev->kernel_queues);
+
+	return rc;
+}
+
+void hl_hw_queues_destroy(struct hl_device *hdev)
+{
+	struct hl_hw_queue *q;
+	u32 max_queues = hdev->asic_prop.max_queues;
+	int i;
+
+	for (i = 0, q = hdev->kernel_queues ; i < max_queues ; i++, q++)
+		queue_fini(hdev, q);
+
+	kfree(hdev->kernel_queues);
+}
+
+void hl_hw_queue_reset(struct hl_device *hdev, bool hard_reset)
+{
+	struct hl_hw_queue *q;
+	u32 max_queues = hdev->asic_prop.max_queues;
+	int i;
+
+	for (i = 0, q = hdev->kernel_queues ; i < max_queues ; i++, q++) {
+		if ((!q->valid) ||
+			((!hard_reset) && (q->queue_type == QUEUE_TYPE_CPU)))
+			continue;
+		q->pi = 0;
+		atomic_set(&q->ci, 0);
+
+		if (q->supports_sync_stream)
+			sync_stream_queue_reset(hdev, q->hw_queue_id);
+	}
+}
diff --git a/drivers/accel/habanalabs/common/hwmon.c b/drivers/accel/habanalabs/common/hwmon.c
new file mode 100644
index 000000000000..52d1e6bf10dc
--- /dev/null
+++ b/drivers/accel/habanalabs/common/hwmon.c
@@ -0,0 +1,931 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Copyright 2016-2019 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ */
+
+#include "habanalabs.h"
+
+#include <linux/pci.h>
+#include <linux/hwmon.h>
+
+#define HWMON_NR_SENSOR_TYPES		(hwmon_max)
+
+#ifdef _HAS_HWMON_HWMON_T_ENABLE
+
+static u32 fixup_flags_legacy_fw(struct hl_device *hdev, enum hwmon_sensor_types type,
+					u32 cpucp_flags)
+{
+	u32 flags;
+
+	switch (type) {
+	case hwmon_temp:
+		flags = (cpucp_flags << 1) | HWMON_T_ENABLE;
+		break;
+
+	case hwmon_in:
+		flags = (cpucp_flags << 1) | HWMON_I_ENABLE;
+		break;
+
+	case hwmon_curr:
+		flags = (cpucp_flags << 1) | HWMON_C_ENABLE;
+		break;
+
+	case hwmon_fan:
+		flags = (cpucp_flags << 1) | HWMON_F_ENABLE;
+		break;
+
+	case hwmon_power:
+		flags = (cpucp_flags << 1) | HWMON_P_ENABLE;
+		break;
+
+	case hwmon_pwm:
+		/* enable bit was here from day 1, so no need to adjust */
+		flags = cpucp_flags;
+		break;
+
+	default:
+		dev_err_ratelimited(hdev->dev, "unsupported h/w sensor type %d\n", type);
+		flags = cpucp_flags;
+		break;
+	}
+
+	return flags;
+}
+
+static u32 fixup_attr_legacy_fw(u32 attr)
+{
+	return (attr - 1);
+}
+
+#else
+
+static u32 fixup_flags_legacy_fw(struct hl_device *hdev, enum hwmon_sensor_types type,
+						u32 cpucp_flags)
+{
+	return cpucp_flags;
+}
+
+static u32 fixup_attr_legacy_fw(u32 attr)
+{
+	return attr;
+}
+
+#endif /* !_HAS_HWMON_HWMON_T_ENABLE */
+
+static u32 adjust_hwmon_flags(struct hl_device *hdev, enum hwmon_sensor_types type, u32 cpucp_flags)
+{
+	u32 flags, cpucp_input_val;
+	bool use_cpucp_enum;
+
+	use_cpucp_enum = (hdev->asic_prop.fw_app_cpu_boot_dev_sts0 &
+					CPU_BOOT_DEV_STS0_MAP_HWMON_EN) ? true : false;
+
+	/* If f/w is using it's own enum, we need to check if the properties values are aligned.
+	 * If not, it means we need to adjust the values to the new format that is used in the
+	 * kernel since 5.6 (enum values were incremented by 1 by adding a new enable value).
+	 */
+	if (use_cpucp_enum) {
+		switch (type) {
+		case hwmon_temp:
+			cpucp_input_val = cpucp_temp_input;
+			if (cpucp_input_val == hwmon_temp_input)
+				flags = cpucp_flags;
+			else
+				flags = (cpucp_flags << 1) | HWMON_T_ENABLE;
+			break;
+
+		case hwmon_in:
+			cpucp_input_val = cpucp_in_input;
+			if (cpucp_input_val == hwmon_in_input)
+				flags = cpucp_flags;
+			else
+				flags = (cpucp_flags << 1) | HWMON_I_ENABLE;
+			break;
+
+		case hwmon_curr:
+			cpucp_input_val = cpucp_curr_input;
+			if (cpucp_input_val == hwmon_curr_input)
+				flags = cpucp_flags;
+			else
+				flags = (cpucp_flags << 1) | HWMON_C_ENABLE;
+			break;
+
+		case hwmon_fan:
+			cpucp_input_val = cpucp_fan_input;
+			if (cpucp_input_val == hwmon_fan_input)
+				flags = cpucp_flags;
+			else
+				flags = (cpucp_flags << 1) | HWMON_F_ENABLE;
+			break;
+
+		case hwmon_pwm:
+			/* enable bit was here from day 1, so no need to adjust */
+			flags = cpucp_flags;
+			break;
+
+		case hwmon_power:
+			cpucp_input_val = CPUCP_POWER_INPUT;
+			if (cpucp_input_val == hwmon_power_input)
+				flags = cpucp_flags;
+			else
+				flags = (cpucp_flags << 1) | HWMON_P_ENABLE;
+			break;
+
+		default:
+			dev_err_ratelimited(hdev->dev, "unsupported h/w sensor type %d\n", type);
+			flags = cpucp_flags;
+			break;
+		}
+	} else {
+		flags = fixup_flags_legacy_fw(hdev, type, cpucp_flags);
+	}
+
+	return flags;
+}
+
+int hl_build_hwmon_channel_info(struct hl_device *hdev, struct cpucp_sensor *sensors_arr)
+{
+	u32 num_sensors_for_type, flags, num_active_sensor_types = 0, arr_size = 0, *curr_arr;
+	u32 sensors_by_type_next_index[HWMON_NR_SENSOR_TYPES] = {0};
+	u32 *sensors_by_type[HWMON_NR_SENSOR_TYPES] = {NULL};
+	struct hwmon_channel_info **channels_info;
+	u32 counts[HWMON_NR_SENSOR_TYPES] = {0};
+	enum hwmon_sensor_types type;
+	int rc, i, j;
+
+	for (i = 0 ; i < CPUCP_MAX_SENSORS ; i++) {
+		type = le32_to_cpu(sensors_arr[i].type);
+
+		if ((type == 0) && (sensors_arr[i].flags == 0))
+			break;
+
+		if (type >= HWMON_NR_SENSOR_TYPES) {
+			dev_err_ratelimited(hdev->dev,
+				"Got wrong sensor type %d from device\n", type);
+			return -EINVAL;
+		}
+
+		counts[type]++;
+		arr_size++;
+	}
+
+	for (i = 0 ; i < HWMON_NR_SENSOR_TYPES ; i++) {
+		if (counts[i] == 0)
+			continue;
+
+		num_sensors_for_type = counts[i] + 1;
+		dev_dbg(hdev->dev, "num_sensors_for_type %d = %d\n", i, num_sensors_for_type);
+
+		curr_arr = kcalloc(num_sensors_for_type, sizeof(*curr_arr), GFP_KERNEL);
+		if (!curr_arr) {
+			rc = -ENOMEM;
+			goto sensors_type_err;
+		}
+
+		num_active_sensor_types++;
+		sensors_by_type[i] = curr_arr;
+	}
+
+	for (i = 0 ; i < arr_size ; i++) {
+		type = le32_to_cpu(sensors_arr[i].type);
+		curr_arr = sensors_by_type[type];
+		flags = adjust_hwmon_flags(hdev, type, le32_to_cpu(sensors_arr[i].flags));
+		curr_arr[sensors_by_type_next_index[type]++] = flags;
+	}
+
+	channels_info = kcalloc(num_active_sensor_types + 1, sizeof(struct hwmon_channel_info *),
+				GFP_KERNEL);
+	if (!channels_info) {
+		rc = -ENOMEM;
+		goto channels_info_array_err;
+	}
+
+	for (i = 0 ; i < num_active_sensor_types ; i++) {
+		channels_info[i] = kzalloc(sizeof(*channels_info[i]), GFP_KERNEL);
+		if (!channels_info[i]) {
+			rc = -ENOMEM;
+			goto channel_info_err;
+		}
+	}
+
+	for (i = 0, j = 0 ; i < HWMON_NR_SENSOR_TYPES ; i++) {
+		if (!sensors_by_type[i])
+			continue;
+
+		channels_info[j]->type = i;
+		channels_info[j]->config = sensors_by_type[i];
+		j++;
+	}
+
+	hdev->hl_chip_info->info = (const struct hwmon_channel_info **)channels_info;
+
+	return 0;
+
+channel_info_err:
+	for (i = 0 ; i < num_active_sensor_types ; i++) {
+		if (channels_info[i]) {
+			kfree(channels_info[i]->config);
+			kfree(channels_info[i]);
+		}
+	}
+	kfree(channels_info);
+
+channels_info_array_err:
+sensors_type_err:
+	for (i = 0 ; i < HWMON_NR_SENSOR_TYPES ; i++)
+		kfree(sensors_by_type[i]);
+
+	return rc;
+}
+
+static int hl_read(struct device *dev, enum hwmon_sensor_types type,
+			u32 attr, int channel, long *val)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+	bool use_cpucp_enum;
+	u32 cpucp_attr;
+	int rc;
+
+	if (!hl_device_operational(hdev, NULL))
+		return -ENODEV;
+
+	use_cpucp_enum = (hdev->asic_prop.fw_app_cpu_boot_dev_sts0 &
+					CPU_BOOT_DEV_STS0_MAP_HWMON_EN) ? true : false;
+
+	switch (type) {
+	case hwmon_temp:
+		switch (attr) {
+		case hwmon_temp_input:
+			cpucp_attr = cpucp_temp_input;
+			break;
+		case hwmon_temp_max:
+			cpucp_attr = cpucp_temp_max;
+			break;
+		case hwmon_temp_crit:
+			cpucp_attr = cpucp_temp_crit;
+			break;
+		case hwmon_temp_max_hyst:
+			cpucp_attr = cpucp_temp_max_hyst;
+			break;
+		case hwmon_temp_crit_hyst:
+			cpucp_attr = cpucp_temp_crit_hyst;
+			break;
+		case hwmon_temp_offset:
+			cpucp_attr = cpucp_temp_offset;
+			break;
+		case hwmon_temp_highest:
+			cpucp_attr = cpucp_temp_highest;
+			break;
+		default:
+			return -EINVAL;
+		}
+
+		if (use_cpucp_enum)
+			rc = hl_get_temperature(hdev, channel, cpucp_attr, val);
+		else
+			rc = hl_get_temperature(hdev, channel, fixup_attr_legacy_fw(attr), val);
+		break;
+	case hwmon_in:
+		switch (attr) {
+		case hwmon_in_input:
+			cpucp_attr = cpucp_in_input;
+			break;
+		case hwmon_in_min:
+			cpucp_attr = cpucp_in_min;
+			break;
+		case hwmon_in_max:
+			cpucp_attr = cpucp_in_max;
+			break;
+		case hwmon_in_highest:
+			cpucp_attr = cpucp_in_highest;
+			break;
+		default:
+			return -EINVAL;
+		}
+
+		if (use_cpucp_enum)
+			rc = hl_get_voltage(hdev, channel, cpucp_attr, val);
+		else
+			rc = hl_get_voltage(hdev, channel, fixup_attr_legacy_fw(attr), val);
+		break;
+	case hwmon_curr:
+		switch (attr) {
+		case hwmon_curr_input:
+			cpucp_attr = cpucp_curr_input;
+			break;
+		case hwmon_curr_min:
+			cpucp_attr = cpucp_curr_min;
+			break;
+		case hwmon_curr_max:
+			cpucp_attr = cpucp_curr_max;
+			break;
+		case hwmon_curr_highest:
+			cpucp_attr = cpucp_curr_highest;
+			break;
+		default:
+			return -EINVAL;
+		}
+
+		if (use_cpucp_enum)
+			rc = hl_get_current(hdev, channel, cpucp_attr, val);
+		else
+			rc = hl_get_current(hdev, channel, fixup_attr_legacy_fw(attr), val);
+		break;
+	case hwmon_fan:
+		switch (attr) {
+		case hwmon_fan_input:
+			cpucp_attr = cpucp_fan_input;
+			break;
+		case hwmon_fan_min:
+			cpucp_attr = cpucp_fan_min;
+			break;
+		case hwmon_fan_max:
+			cpucp_attr = cpucp_fan_max;
+			break;
+		default:
+			return -EINVAL;
+		}
+
+		if (use_cpucp_enum)
+			rc = hl_get_fan_speed(hdev, channel, cpucp_attr, val);
+		else
+			rc = hl_get_fan_speed(hdev, channel, fixup_attr_legacy_fw(attr), val);
+		break;
+	case hwmon_pwm:
+		switch (attr) {
+		case hwmon_pwm_input:
+			cpucp_attr = cpucp_pwm_input;
+			break;
+		case hwmon_pwm_enable:
+			cpucp_attr = cpucp_pwm_enable;
+			break;
+		default:
+			return -EINVAL;
+		}
+
+		if (use_cpucp_enum)
+			rc = hl_get_pwm_info(hdev, channel, cpucp_attr, val);
+		else
+			/* no need for fixup as pwm was aligned from day 1 */
+			rc = hl_get_pwm_info(hdev, channel, attr, val);
+		break;
+	case hwmon_power:
+		switch (attr) {
+		case hwmon_power_input:
+			cpucp_attr = CPUCP_POWER_INPUT;
+			break;
+		case hwmon_power_input_highest:
+			cpucp_attr = CPUCP_POWER_INPUT_HIGHEST;
+			break;
+		default:
+			return -EINVAL;
+		}
+
+		if (use_cpucp_enum)
+			rc = hl_get_power(hdev, channel, cpucp_attr, val);
+		else
+			rc = hl_get_power(hdev, channel, fixup_attr_legacy_fw(attr), val);
+		break;
+	default:
+		return -EINVAL;
+	}
+	return rc;
+}
+
+static int hl_write(struct device *dev, enum hwmon_sensor_types type,
+			u32 attr, int channel, long val)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+	u32 cpucp_attr;
+	bool use_cpucp_enum = (hdev->asic_prop.fw_app_cpu_boot_dev_sts0 &
+				CPU_BOOT_DEV_STS0_MAP_HWMON_EN) ? true : false;
+
+	if (!hl_device_operational(hdev, NULL))
+		return -ENODEV;
+
+	switch (type) {
+	case hwmon_temp:
+		switch (attr) {
+		case hwmon_temp_offset:
+			cpucp_attr = cpucp_temp_offset;
+			break;
+		case hwmon_temp_reset_history:
+			cpucp_attr = cpucp_temp_reset_history;
+			break;
+		default:
+			return -EINVAL;
+		}
+
+		if (use_cpucp_enum)
+			hl_set_temperature(hdev, channel, cpucp_attr, val);
+		else
+			hl_set_temperature(hdev, channel, fixup_attr_legacy_fw(attr), val);
+		break;
+	case hwmon_pwm:
+		switch (attr) {
+		case hwmon_pwm_input:
+			cpucp_attr = cpucp_pwm_input;
+			break;
+		case hwmon_pwm_enable:
+			cpucp_attr = cpucp_pwm_enable;
+			break;
+		default:
+			return -EINVAL;
+		}
+
+		if (use_cpucp_enum)
+			hl_set_pwm_info(hdev, channel, cpucp_attr, val);
+		else
+			/* no need for fixup as pwm was aligned from day 1 */
+			hl_set_pwm_info(hdev, channel, attr, val);
+		break;
+	case hwmon_in:
+		switch (attr) {
+		case hwmon_in_reset_history:
+			cpucp_attr = cpucp_in_reset_history;
+			break;
+		default:
+			return -EINVAL;
+		}
+
+		if (use_cpucp_enum)
+			hl_set_voltage(hdev, channel, cpucp_attr, val);
+		else
+			hl_set_voltage(hdev, channel, fixup_attr_legacy_fw(attr), val);
+		break;
+	case hwmon_curr:
+		switch (attr) {
+		case hwmon_curr_reset_history:
+			cpucp_attr = cpucp_curr_reset_history;
+			break;
+		default:
+			return -EINVAL;
+		}
+
+		if (use_cpucp_enum)
+			hl_set_current(hdev, channel, cpucp_attr, val);
+		else
+			hl_set_current(hdev, channel, fixup_attr_legacy_fw(attr), val);
+		break;
+	case hwmon_power:
+		switch (attr) {
+		case hwmon_power_reset_history:
+			cpucp_attr = CPUCP_POWER_RESET_INPUT_HISTORY;
+			break;
+		default:
+			return -EINVAL;
+		}
+
+		if (use_cpucp_enum)
+			hl_set_power(hdev, channel, cpucp_attr, val);
+		else
+			hl_set_power(hdev, channel, fixup_attr_legacy_fw(attr), val);
+		break;
+	default:
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static umode_t hl_is_visible(const void *data, enum hwmon_sensor_types type,
+				u32 attr, int channel)
+{
+	switch (type) {
+	case hwmon_temp:
+		switch (attr) {
+		case hwmon_temp_input:
+		case hwmon_temp_max:
+		case hwmon_temp_max_hyst:
+		case hwmon_temp_crit:
+		case hwmon_temp_crit_hyst:
+		case hwmon_temp_highest:
+			return 0444;
+		case hwmon_temp_offset:
+			return 0644;
+		case hwmon_temp_reset_history:
+			return 0200;
+		}
+		break;
+	case hwmon_in:
+		switch (attr) {
+		case hwmon_in_input:
+		case hwmon_in_min:
+		case hwmon_in_max:
+		case hwmon_in_highest:
+			return 0444;
+		case hwmon_in_reset_history:
+			return 0200;
+		}
+		break;
+	case hwmon_curr:
+		switch (attr) {
+		case hwmon_curr_input:
+		case hwmon_curr_min:
+		case hwmon_curr_max:
+		case hwmon_curr_highest:
+			return 0444;
+		case hwmon_curr_reset_history:
+			return 0200;
+		}
+		break;
+	case hwmon_fan:
+		switch (attr) {
+		case hwmon_fan_input:
+		case hwmon_fan_min:
+		case hwmon_fan_max:
+			return 0444;
+		}
+		break;
+	case hwmon_pwm:
+		switch (attr) {
+		case hwmon_pwm_input:
+		case hwmon_pwm_enable:
+			return 0644;
+		}
+		break;
+	case hwmon_power:
+		switch (attr) {
+		case hwmon_power_input:
+		case hwmon_power_input_highest:
+			return 0444;
+		case hwmon_power_reset_history:
+			return 0200;
+		}
+		break;
+	default:
+		break;
+	}
+	return 0;
+}
+
+static const struct hwmon_ops hl_hwmon_ops = {
+	.is_visible = hl_is_visible,
+	.read = hl_read,
+	.write = hl_write
+};
+
+int hl_get_temperature(struct hl_device *hdev,
+			int sensor_index, u32 attr, long *value)
+{
+	struct cpucp_packet pkt;
+	u64 result;
+	int rc;
+
+	memset(&pkt, 0, sizeof(pkt));
+
+	pkt.ctl = cpu_to_le32(CPUCP_PACKET_TEMPERATURE_GET <<
+				CPUCP_PKT_CTL_OPCODE_SHIFT);
+	pkt.sensor_index = __cpu_to_le16(sensor_index);
+	pkt.type = __cpu_to_le16(attr);
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
+						0, &result);
+
+	*value = (long) result;
+
+	if (rc) {
+		if (rc != -EAGAIN)
+			dev_err_ratelimited(hdev->dev,
+				"Failed to get temperature from sensor %d, error %d\n",
+				sensor_index, rc);
+		*value = 0;
+	}
+
+	return rc;
+}
+
+int hl_set_temperature(struct hl_device *hdev,
+			int sensor_index, u32 attr, long value)
+{
+	struct cpucp_packet pkt;
+	int rc;
+
+	memset(&pkt, 0, sizeof(pkt));
+
+	pkt.ctl = cpu_to_le32(CPUCP_PACKET_TEMPERATURE_SET <<
+				CPUCP_PKT_CTL_OPCODE_SHIFT);
+	pkt.sensor_index = __cpu_to_le16(sensor_index);
+	pkt.type = __cpu_to_le16(attr);
+	pkt.value = __cpu_to_le64(value);
+
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
+						0, NULL);
+	if (rc && rc != -EAGAIN)
+		dev_err_ratelimited(hdev->dev,
+			"Failed to set temperature of sensor %d, error %d\n",
+			sensor_index, rc);
+
+	return rc;
+}
+
+int hl_get_voltage(struct hl_device *hdev,
+			int sensor_index, u32 attr, long *value)
+{
+	struct cpucp_packet pkt;
+	u64 result;
+	int rc;
+
+	memset(&pkt, 0, sizeof(pkt));
+
+	pkt.ctl = cpu_to_le32(CPUCP_PACKET_VOLTAGE_GET <<
+				CPUCP_PKT_CTL_OPCODE_SHIFT);
+	pkt.sensor_index = __cpu_to_le16(sensor_index);
+	pkt.type = __cpu_to_le16(attr);
+
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
+						0, &result);
+
+	*value = (long) result;
+
+	if (rc) {
+		if (rc != -EAGAIN)
+			dev_err_ratelimited(hdev->dev,
+				"Failed to get voltage from sensor %d, error %d\n",
+				sensor_index, rc);
+		*value = 0;
+	}
+
+	return rc;
+}
+
+int hl_get_current(struct hl_device *hdev,
+			int sensor_index, u32 attr, long *value)
+{
+	struct cpucp_packet pkt;
+	u64 result;
+	int rc;
+
+	memset(&pkt, 0, sizeof(pkt));
+
+	pkt.ctl = cpu_to_le32(CPUCP_PACKET_CURRENT_GET <<
+				CPUCP_PKT_CTL_OPCODE_SHIFT);
+	pkt.sensor_index = __cpu_to_le16(sensor_index);
+	pkt.type = __cpu_to_le16(attr);
+
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
+						0, &result);
+
+	*value = (long) result;
+
+	if (rc) {
+		if (rc != -EAGAIN)
+			dev_err_ratelimited(hdev->dev,
+				"Failed to get current from sensor %d, error %d\n",
+				sensor_index, rc);
+		*value = 0;
+	}
+
+	return rc;
+}
+
+int hl_get_fan_speed(struct hl_device *hdev,
+			int sensor_index, u32 attr, long *value)
+{
+	struct cpucp_packet pkt;
+	u64 result;
+	int rc;
+
+	memset(&pkt, 0, sizeof(pkt));
+
+	pkt.ctl = cpu_to_le32(CPUCP_PACKET_FAN_SPEED_GET <<
+				CPUCP_PKT_CTL_OPCODE_SHIFT);
+	pkt.sensor_index = __cpu_to_le16(sensor_index);
+	pkt.type = __cpu_to_le16(attr);
+
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
+						0, &result);
+
+	*value = (long) result;
+
+	if (rc) {
+		if (rc != -EAGAIN)
+			dev_err_ratelimited(hdev->dev,
+				"Failed to get fan speed from sensor %d, error %d\n",
+				sensor_index, rc);
+		*value = 0;
+	}
+
+	return rc;
+}
+
+int hl_get_pwm_info(struct hl_device *hdev,
+			int sensor_index, u32 attr, long *value)
+{
+	struct cpucp_packet pkt;
+	u64 result;
+	int rc;
+
+	memset(&pkt, 0, sizeof(pkt));
+
+	pkt.ctl = cpu_to_le32(CPUCP_PACKET_PWM_GET <<
+				CPUCP_PKT_CTL_OPCODE_SHIFT);
+	pkt.sensor_index = __cpu_to_le16(sensor_index);
+	pkt.type = __cpu_to_le16(attr);
+
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
+						0, &result);
+
+	*value = (long) result;
+
+	if (rc) {
+		if (rc != -EAGAIN)
+			dev_err_ratelimited(hdev->dev,
+				"Failed to get pwm info from sensor %d, error %d\n",
+				sensor_index, rc);
+		*value = 0;
+	}
+
+	return rc;
+}
+
+void hl_set_pwm_info(struct hl_device *hdev, int sensor_index, u32 attr,
+			long value)
+{
+	struct cpucp_packet pkt;
+	int rc;
+
+	memset(&pkt, 0, sizeof(pkt));
+
+	pkt.ctl = cpu_to_le32(CPUCP_PACKET_PWM_SET <<
+				CPUCP_PKT_CTL_OPCODE_SHIFT);
+	pkt.sensor_index = __cpu_to_le16(sensor_index);
+	pkt.type = __cpu_to_le16(attr);
+	pkt.value = cpu_to_le64(value);
+
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
+						0, NULL);
+	if (rc && rc != -EAGAIN)
+		dev_err_ratelimited(hdev->dev,
+			"Failed to set pwm info to sensor %d, error %d\n",
+			sensor_index, rc);
+}
+
+int hl_set_voltage(struct hl_device *hdev,
+			int sensor_index, u32 attr, long value)
+{
+	struct cpucp_packet pkt;
+	int rc;
+
+	memset(&pkt, 0, sizeof(pkt));
+
+	pkt.ctl = cpu_to_le32(CPUCP_PACKET_VOLTAGE_SET <<
+				CPUCP_PKT_CTL_OPCODE_SHIFT);
+	pkt.sensor_index = __cpu_to_le16(sensor_index);
+	pkt.type = __cpu_to_le16(attr);
+	pkt.value = __cpu_to_le64(value);
+
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
+						0, NULL);
+	if (rc && rc != -EAGAIN)
+		dev_err_ratelimited(hdev->dev,
+			"Failed to set voltage of sensor %d, error %d\n",
+			sensor_index, rc);
+
+	return rc;
+}
+
+int hl_set_current(struct hl_device *hdev,
+			int sensor_index, u32 attr, long value)
+{
+	struct cpucp_packet pkt;
+	int rc;
+
+	memset(&pkt, 0, sizeof(pkt));
+
+	pkt.ctl = cpu_to_le32(CPUCP_PACKET_CURRENT_SET <<
+				CPUCP_PKT_CTL_OPCODE_SHIFT);
+	pkt.sensor_index = __cpu_to_le16(sensor_index);
+	pkt.type = __cpu_to_le16(attr);
+	pkt.value = __cpu_to_le64(value);
+
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), 0, NULL);
+	if (rc && rc != -EAGAIN)
+		dev_err_ratelimited(hdev->dev,
+			"Failed to set current of sensor %d, error %d\n",
+			sensor_index, rc);
+
+	return rc;
+}
+
+int hl_set_power(struct hl_device *hdev,
+			int sensor_index, u32 attr, long value)
+{
+	struct cpucp_packet pkt;
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	int rc;
+
+	memset(&pkt, 0, sizeof(pkt));
+
+	if (prop->use_get_power_for_reset_history)
+		pkt.ctl = cpu_to_le32(CPUCP_PACKET_POWER_GET <<
+				CPUCP_PKT_CTL_OPCODE_SHIFT);
+	else
+		pkt.ctl = cpu_to_le32(CPUCP_PACKET_POWER_SET <<
+				CPUCP_PKT_CTL_OPCODE_SHIFT);
+
+	pkt.sensor_index = __cpu_to_le16(sensor_index);
+	pkt.type = __cpu_to_le16(attr);
+	pkt.value = __cpu_to_le64(value);
+
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
+						0, NULL);
+	if (rc && rc != -EAGAIN)
+		dev_err_ratelimited(hdev->dev,
+			"Failed to set power of sensor %d, error %d\n",
+			sensor_index, rc);
+
+	return rc;
+}
+
+int hl_get_power(struct hl_device *hdev,
+			int sensor_index, u32 attr, long *value)
+{
+	struct cpucp_packet pkt;
+	u64 result;
+	int rc;
+
+	memset(&pkt, 0, sizeof(pkt));
+
+	pkt.ctl = cpu_to_le32(CPUCP_PACKET_POWER_GET <<
+				CPUCP_PKT_CTL_OPCODE_SHIFT);
+	pkt.sensor_index = __cpu_to_le16(sensor_index);
+	pkt.type = __cpu_to_le16(attr);
+
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
+						0, &result);
+
+	*value = (long) result;
+
+	if (rc) {
+		if (rc != -EAGAIN)
+			dev_err_ratelimited(hdev->dev,
+				"Failed to get power of sensor %d, error %d\n",
+				sensor_index, rc);
+		*value = 0;
+	}
+
+	return rc;
+}
+
+int hl_hwmon_init(struct hl_device *hdev)
+{
+	struct device *dev = hdev->pdev ? &hdev->pdev->dev : hdev->dev;
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	int rc;
+
+	if ((hdev->hwmon_initialized) || !(hdev->cpu_queues_enable))
+		return 0;
+
+	if (hdev->hl_chip_info->info) {
+		hdev->hl_chip_info->ops = &hl_hwmon_ops;
+
+		hdev->hwmon_dev = hwmon_device_register_with_info(dev,
+					prop->cpucp_info.card_name, hdev,
+					hdev->hl_chip_info, NULL);
+		if (IS_ERR(hdev->hwmon_dev)) {
+			rc = PTR_ERR(hdev->hwmon_dev);
+			dev_err(hdev->dev,
+				"Unable to register hwmon device: %d\n", rc);
+			return rc;
+		}
+
+		dev_info(hdev->dev, "%s: add sensors information\n",
+			dev_name(hdev->hwmon_dev));
+
+		hdev->hwmon_initialized = true;
+	} else {
+		dev_info(hdev->dev, "no available sensors\n");
+	}
+
+	return 0;
+}
+
+void hl_hwmon_fini(struct hl_device *hdev)
+{
+	if (!hdev->hwmon_initialized)
+		return;
+
+	hwmon_device_unregister(hdev->hwmon_dev);
+}
+
+void hl_hwmon_release_resources(struct hl_device *hdev)
+{
+	const struct hwmon_channel_info * const *channel_info_arr;
+	int i = 0;
+
+	if (!hdev->hl_chip_info->info)
+		return;
+
+	channel_info_arr = hdev->hl_chip_info->info;
+
+	while (channel_info_arr[i]) {
+		kfree(channel_info_arr[i]->config);
+		kfree(channel_info_arr[i]);
+		i++;
+	}
+
+	kfree(channel_info_arr);
+
+	hdev->hl_chip_info->info = NULL;
+}
diff --git a/drivers/accel/habanalabs/common/irq.c b/drivers/accel/habanalabs/common/irq.c
new file mode 100644
index 000000000000..7c9f2f6a2870
--- /dev/null
+++ b/drivers/accel/habanalabs/common/irq.c
@@ -0,0 +1,724 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Copyright 2016-2022 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ */
+
+#include "habanalabs.h"
+
+#include <linux/slab.h>
+
+/**
+ * struct hl_eqe_work - This structure is used to schedule work of EQ
+ *                      entry and cpucp_reset event
+ *
+ * @eq_work:          workqueue object to run when EQ entry is received
+ * @hdev:             pointer to device structure
+ * @eq_entry:         copy of the EQ entry
+ */
+struct hl_eqe_work {
+	struct work_struct	eq_work;
+	struct hl_device	*hdev;
+	struct hl_eq_entry	eq_entry;
+};
+
+/**
+ * hl_cq_inc_ptr - increment ci or pi of cq
+ *
+ * @ptr: the current ci or pi value of the completion queue
+ *
+ * Increment ptr by 1. If it reaches the number of completion queue
+ * entries, set it to 0
+ */
+inline u32 hl_cq_inc_ptr(u32 ptr)
+{
+	ptr++;
+	if (unlikely(ptr == HL_CQ_LENGTH))
+		ptr = 0;
+	return ptr;
+}
+
+/**
+ * hl_eq_inc_ptr - increment ci of eq
+ *
+ * @ptr: the current ci value of the event queue
+ *
+ * Increment ptr by 1. If it reaches the number of event queue
+ * entries, set it to 0
+ */
+static inline u32 hl_eq_inc_ptr(u32 ptr)
+{
+	ptr++;
+	if (unlikely(ptr == HL_EQ_LENGTH))
+		ptr = 0;
+	return ptr;
+}
+
+static void irq_handle_eqe(struct work_struct *work)
+{
+	struct hl_eqe_work *eqe_work = container_of(work, struct hl_eqe_work,
+							eq_work);
+	struct hl_device *hdev = eqe_work->hdev;
+
+	hdev->asic_funcs->handle_eqe(hdev, &eqe_work->eq_entry);
+
+	kfree(eqe_work);
+}
+
+/**
+ * job_finish - queue job finish work
+ *
+ * @hdev: pointer to device structure
+ * @cs_seq: command submission sequence
+ * @cq: completion queue
+ * @timestamp: interrupt timestamp
+ *
+ */
+static void job_finish(struct hl_device *hdev, u32 cs_seq, struct hl_cq *cq, ktime_t timestamp)
+{
+	struct hl_hw_queue *queue;
+	struct hl_cs_job *job;
+
+	queue = &hdev->kernel_queues[cq->hw_queue_id];
+	job = queue->shadow_queue[hl_pi_2_offset(cs_seq)];
+	job->timestamp = timestamp;
+	queue_work(hdev->cq_wq[cq->cq_idx], &job->finish_work);
+
+	atomic_inc(&queue->ci);
+}
+
+/**
+ * cs_finish - queue all cs jobs finish work
+ *
+ * @hdev: pointer to device structure
+ * @cs_seq: command submission sequence
+ * @timestamp: interrupt timestamp
+ *
+ */
+static void cs_finish(struct hl_device *hdev, u16 cs_seq, ktime_t timestamp)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct hl_hw_queue *queue;
+	struct hl_cs *cs;
+	struct hl_cs_job *job;
+
+	cs = hdev->shadow_cs_queue[cs_seq & (prop->max_pending_cs - 1)];
+	if (!cs) {
+		dev_warn(hdev->dev,
+			"No pointer to CS in shadow array at index %d\n",
+			cs_seq);
+		return;
+	}
+
+	list_for_each_entry(job, &cs->job_list, cs_node) {
+		queue = &hdev->kernel_queues[job->hw_queue_id];
+		atomic_inc(&queue->ci);
+	}
+
+	cs->completion_timestamp = timestamp;
+	queue_work(hdev->cs_cmplt_wq, &cs->finish_work);
+}
+
+/**
+ * hl_irq_handler_cq - irq handler for completion queue
+ *
+ * @irq: irq number
+ * @arg: pointer to completion queue structure
+ *
+ */
+irqreturn_t hl_irq_handler_cq(int irq, void *arg)
+{
+	struct hl_cq *cq = arg;
+	struct hl_device *hdev = cq->hdev;
+	bool shadow_index_valid, entry_ready;
+	u16 shadow_index;
+	struct hl_cq_entry *cq_entry, *cq_base;
+	ktime_t timestamp = ktime_get();
+
+	if (hdev->disabled) {
+		dev_dbg(hdev->dev,
+			"Device disabled but received IRQ %d for CQ %d\n",
+			irq, cq->hw_queue_id);
+		return IRQ_HANDLED;
+	}
+
+	cq_base = cq->kernel_address;
+
+	while (1) {
+		cq_entry = (struct hl_cq_entry *) &cq_base[cq->ci];
+
+		entry_ready = !!FIELD_GET(CQ_ENTRY_READY_MASK,
+				le32_to_cpu(cq_entry->data));
+		if (!entry_ready)
+			break;
+
+		/* Make sure we read CQ entry contents after we've
+		 * checked the ownership bit.
+		 */
+		dma_rmb();
+
+		shadow_index_valid =
+			!!FIELD_GET(CQ_ENTRY_SHADOW_INDEX_VALID_MASK,
+					le32_to_cpu(cq_entry->data));
+
+		shadow_index = FIELD_GET(CQ_ENTRY_SHADOW_INDEX_MASK,
+				le32_to_cpu(cq_entry->data));
+
+		/*
+		 * CQ interrupt handler has 2 modes of operation:
+		 * 1. Interrupt per CS completion: (Single CQ for all queues)
+		 *    CQ entry represents a completed CS
+		 *
+		 * 2. Interrupt per CS job completion in queue: (CQ per queue)
+		 *    CQ entry represents a completed job in a certain queue
+		 */
+		if (shadow_index_valid && !hdev->disabled) {
+			if (hdev->asic_prop.completion_mode ==
+					HL_COMPLETION_MODE_CS)
+				cs_finish(hdev, shadow_index, timestamp);
+			else
+				job_finish(hdev, shadow_index, cq, timestamp);
+		}
+
+		/* Clear CQ entry ready bit */
+		cq_entry->data = cpu_to_le32(le32_to_cpu(cq_entry->data) &
+						~CQ_ENTRY_READY_MASK);
+
+		cq->ci = hl_cq_inc_ptr(cq->ci);
+
+		/* Increment free slots */
+		atomic_inc(&cq->free_slots_cnt);
+	}
+
+	return IRQ_HANDLED;
+}
+
+/*
+ * hl_ts_free_objects - handler of the free objects workqueue.
+ * This function should put refcount to objects that the registration node
+ * took refcount to them.
+ * @work: workqueue object pointer
+ */
+static void hl_ts_free_objects(struct work_struct *work)
+{
+	struct timestamp_reg_work_obj *job =
+			container_of(work, struct timestamp_reg_work_obj, free_obj);
+	struct list_head *dynamic_alloc_free_list_head = job->dynamic_alloc_free_obj_head;
+	struct timestamp_reg_free_node *free_obj, *temp_free_obj;
+	struct list_head *free_list_head = job->free_obj_head;
+
+	struct hl_device *hdev = job->hdev;
+
+	list_for_each_entry_safe(free_obj, temp_free_obj, free_list_head, free_objects_node) {
+		dev_dbg(hdev->dev, "About to put refcount to buf (%p) cq_cb(%p)\n",
+					free_obj->buf,
+					free_obj->cq_cb);
+
+		hl_mmap_mem_buf_put(free_obj->buf);
+		hl_cb_put(free_obj->cq_cb);
+		atomic_set(&free_obj->in_use, 0);
+	}
+
+	kfree(free_list_head);
+
+	if (dynamic_alloc_free_list_head) {
+		list_for_each_entry_safe(free_obj, temp_free_obj, dynamic_alloc_free_list_head,
+								free_objects_node) {
+			dev_dbg(hdev->dev,
+				"Dynamic_Alloc list: About to put refcount to buf (%p) cq_cb(%p)\n",
+						free_obj->buf,
+						free_obj->cq_cb);
+
+			hl_mmap_mem_buf_put(free_obj->buf);
+			hl_cb_put(free_obj->cq_cb);
+			list_del(&free_obj->free_objects_node);
+			kfree(free_obj);
+		}
+
+		kfree(dynamic_alloc_free_list_head);
+	}
+
+	kfree(job);
+}
+
+/*
+ * This function called with spin_lock of wait_list_lock taken
+ * This function will set timestamp and delete the registration node from the
+ * wait_list_lock.
+ * and since we're protected with spin_lock here, so we cannot just put the refcount
+ * for the objects here, since the release function may be called and it's also a long
+ * logic (which might sleep also) that cannot be handled in irq context.
+ * so here we'll be filling a list with nodes of "put" jobs and then will send this
+ * list to a dedicated workqueue to do the actual put.
+ */
+static int handle_registration_node(struct hl_device *hdev, struct hl_user_pending_interrupt *pend,
+						struct list_head **free_list,
+						struct list_head **dynamic_alloc_list,
+						struct hl_user_interrupt *intr)
+{
+	struct hl_ts_free_jobs *ts_free_jobs_data;
+	struct timestamp_reg_free_node *free_node;
+	u32 free_node_index;
+	u64 timestamp;
+
+	ts_free_jobs_data = &intr->ts_free_jobs_data;
+	free_node_index = ts_free_jobs_data->next_avail_free_node_idx;
+
+	if (!(*free_list)) {
+		/* Alloc/Init the timestamp registration free objects list */
+		*free_list = kmalloc(sizeof(struct list_head), GFP_ATOMIC);
+		if (!(*free_list))
+			return -ENOMEM;
+
+		INIT_LIST_HEAD(*free_list);
+	}
+
+	free_node = &ts_free_jobs_data->free_nodes_pool[free_node_index];
+	if (atomic_cmpxchg(&free_node->in_use, 0, 1)) {
+		dev_dbg(hdev->dev,
+			"Timestamp free node pool is full, buff: %p, record: %p, irq: %u\n",
+				pend->ts_reg_info.buf,
+				pend,
+				intr->interrupt_id);
+
+		if (!(*dynamic_alloc_list)) {
+			*dynamic_alloc_list = kmalloc(sizeof(struct list_head), GFP_ATOMIC);
+			if (!(*dynamic_alloc_list))
+				return -ENOMEM;
+
+			INIT_LIST_HEAD(*dynamic_alloc_list);
+		}
+
+		free_node = kmalloc(sizeof(struct timestamp_reg_free_node), GFP_ATOMIC);
+		if (!free_node)
+			return -ENOMEM;
+
+		free_node->dynamic_alloc = 1;
+	}
+
+	timestamp = ktime_to_ns(intr->timestamp);
+
+	*pend->ts_reg_info.timestamp_kernel_addr = timestamp;
+
+	dev_dbg(hdev->dev, "Irq handle: Timestamp record (%p) ts cb address (%p), interrupt_id: %u\n",
+			pend, pend->ts_reg_info.timestamp_kernel_addr, intr->interrupt_id);
+
+	list_del(&pend->list_node);
+
+	/* Putting the refcount for ts_buff and cq_cb objects will be handled
+	 * in workqueue context, just add job to free_list.
+	 */
+	free_node->buf = pend->ts_reg_info.buf;
+	free_node->cq_cb = pend->ts_reg_info.cq_cb;
+
+	if (free_node->dynamic_alloc) {
+		list_add(&free_node->free_objects_node, *dynamic_alloc_list);
+	} else {
+		ts_free_jobs_data->next_avail_free_node_idx =
+				(++free_node_index) % ts_free_jobs_data->free_nodes_length;
+		list_add(&free_node->free_objects_node, *free_list);
+	}
+
+	/* Mark TS record as free */
+	pend->ts_reg_info.in_use = false;
+
+	return 0;
+}
+
+static void handle_user_interrupt_ts_list(struct hl_device *hdev, struct hl_user_interrupt *intr)
+{
+	struct list_head *ts_reg_free_list_head = NULL, *dynamic_alloc_list_head = NULL;
+	struct hl_user_pending_interrupt *pend, *temp_pend;
+	struct timestamp_reg_work_obj *job;
+	bool reg_node_handle_fail = false;
+	unsigned long flags;
+	int rc;
+
+	/* For registration nodes:
+	 * As part of handling the registration nodes, we should put refcount to
+	 * some objects. the problem is that we cannot do that under spinlock
+	 * or in irq handler context at all (since release functions are long and
+	 * might sleep), so we will need to handle that part in workqueue context.
+	 * To avoid handling kmalloc failure which compels us rolling back actions
+	 * and move nodes hanged on the free list back to the interrupt ts list
+	 * we always alloc the job of the WQ at the beginning.
+	 */
+	job = kmalloc(sizeof(*job), GFP_ATOMIC);
+	if (!job)
+		return;
+
+	spin_lock_irqsave(&intr->ts_list_lock, flags);
+	list_for_each_entry_safe(pend, temp_pend, &intr->ts_list_head, list_node) {
+		if ((pend->cq_kernel_addr && *(pend->cq_kernel_addr) >= pend->cq_target_value) ||
+				!pend->cq_kernel_addr) {
+			if (!reg_node_handle_fail) {
+				rc = handle_registration_node(hdev, pend,
+						&ts_reg_free_list_head,
+						&dynamic_alloc_list_head, intr);
+				if (rc)
+					reg_node_handle_fail = true;
+			}
+		}
+	}
+	spin_unlock_irqrestore(&intr->ts_list_lock, flags);
+
+	if (ts_reg_free_list_head) {
+		INIT_WORK(&job->free_obj, hl_ts_free_objects);
+		job->free_obj_head = ts_reg_free_list_head;
+		job->dynamic_alloc_free_obj_head = dynamic_alloc_list_head;
+		job->hdev = hdev;
+		queue_work(hdev->ts_free_obj_wq, &job->free_obj);
+	} else {
+		kfree(job);
+	}
+}
+
+static void handle_user_interrupt_wait_list(struct hl_device *hdev, struct hl_user_interrupt *intr)
+{
+	struct hl_user_pending_interrupt *pend, *temp_pend;
+	unsigned long flags;
+
+	spin_lock_irqsave(&intr->wait_list_lock, flags);
+	list_for_each_entry_safe(pend, temp_pend, &intr->wait_list_head, list_node) {
+		if ((pend->cq_kernel_addr && *(pend->cq_kernel_addr) >= pend->cq_target_value) ||
+				!pend->cq_kernel_addr) {
+			/* Handle wait target value node */
+			pend->fence.timestamp = intr->timestamp;
+			complete_all(&pend->fence.completion);
+		}
+	}
+	spin_unlock_irqrestore(&intr->wait_list_lock, flags);
+}
+
+static void handle_tpc_interrupt(struct hl_device *hdev)
+{
+	u64 event_mask;
+	u32 flags;
+
+	event_mask = HL_NOTIFIER_EVENT_TPC_ASSERT |
+		HL_NOTIFIER_EVENT_USER_ENGINE_ERR |
+		HL_NOTIFIER_EVENT_DEVICE_RESET;
+
+	flags = HL_DRV_RESET_DELAY;
+
+	dev_err_ratelimited(hdev->dev, "Received TPC assert\n");
+	hl_device_cond_reset(hdev, flags, event_mask);
+}
+
+static void handle_unexpected_user_interrupt(struct hl_device *hdev)
+{
+	dev_err_ratelimited(hdev->dev, "Received unexpected user error interrupt\n");
+}
+
+/**
+ * hl_irq_user_interrupt_handler - irq handler for user interrupts.
+ *
+ * @irq: irq number
+ * @arg: pointer to user interrupt structure
+ */
+irqreturn_t hl_irq_user_interrupt_handler(int irq, void *arg)
+{
+	struct hl_user_interrupt *user_int = arg;
+	struct hl_device *hdev = user_int->hdev;
+
+	user_int->timestamp = ktime_get();
+	switch (user_int->type) {
+	case HL_USR_INTERRUPT_CQ:
+		/* First handle user waiters threads */
+		handle_user_interrupt_wait_list(hdev, &hdev->common_user_cq_interrupt);
+		handle_user_interrupt_wait_list(hdev, user_int);
+
+		/* Second handle user timestamp registrations */
+		handle_user_interrupt_ts_list(hdev,  &hdev->common_user_cq_interrupt);
+		handle_user_interrupt_ts_list(hdev, user_int);
+		break;
+	case HL_USR_INTERRUPT_DECODER:
+		handle_user_interrupt_wait_list(hdev, &hdev->common_decoder_interrupt);
+
+		/* Handle decoder interrupt registered on this specific irq */
+		handle_user_interrupt_wait_list(hdev, user_int);
+		break;
+	default:
+		break;
+	}
+
+	return IRQ_HANDLED;
+}
+
+/**
+ * hl_irq_user_interrupt_thread_handler - irq thread handler for user interrupts.
+ * This function is invoked by threaded irq mechanism
+ *
+ * @irq: irq number
+ * @arg: pointer to user interrupt structure
+ *
+ */
+irqreturn_t hl_irq_user_interrupt_thread_handler(int irq, void *arg)
+{
+	struct hl_user_interrupt *user_int = arg;
+	struct hl_device *hdev = user_int->hdev;
+
+	user_int->timestamp = ktime_get();
+	switch (user_int->type) {
+	case HL_USR_INTERRUPT_TPC:
+		handle_tpc_interrupt(hdev);
+		break;
+	case HL_USR_INTERRUPT_UNEXPECTED:
+		handle_unexpected_user_interrupt(hdev);
+		break;
+	default:
+		break;
+	}
+
+	return IRQ_HANDLED;
+}
+
+irqreturn_t hl_irq_eq_error_interrupt_thread_handler(int irq, void *arg)
+{
+	u64 event_mask = HL_NOTIFIER_EVENT_DEVICE_RESET | HL_NOTIFIER_EVENT_DEVICE_UNAVAILABLE;
+	struct hl_device *hdev = arg;
+
+	dev_err(hdev->dev, "EQ error interrupt received\n");
+
+	hl_device_cond_reset(hdev, HL_DRV_RESET_HARD, event_mask);
+
+	return IRQ_HANDLED;
+}
+
+/**
+ * hl_irq_handler_eq - irq handler for event queue
+ *
+ * @irq: irq number
+ * @arg: pointer to event queue structure
+ *
+ */
+irqreturn_t hl_irq_handler_eq(int irq, void *arg)
+{
+	struct hl_eq *eq = arg;
+	struct hl_device *hdev = eq->hdev;
+	struct hl_eq_entry *eq_entry;
+	struct hl_eq_entry *eq_base;
+	struct hl_eqe_work *handle_eqe_work;
+	bool entry_ready;
+	u32 cur_eqe, ctl;
+	u16 cur_eqe_index, event_type;
+
+	eq_base = eq->kernel_address;
+
+	while (1) {
+		cur_eqe = le32_to_cpu(eq_base[eq->ci].hdr.ctl);
+		entry_ready = !!FIELD_GET(EQ_CTL_READY_MASK, cur_eqe);
+
+		if (!entry_ready)
+			break;
+
+		cur_eqe_index = FIELD_GET(EQ_CTL_INDEX_MASK, cur_eqe);
+		if ((hdev->event_queue.check_eqe_index) &&
+				(((eq->prev_eqe_index + 1) & EQ_CTL_INDEX_MASK) != cur_eqe_index)) {
+			dev_err(hdev->dev,
+				"EQE %#x in queue is ready but index does not match %d!=%d",
+				cur_eqe,
+				((eq->prev_eqe_index + 1) & EQ_CTL_INDEX_MASK),
+				cur_eqe_index);
+			break;
+		}
+
+		eq->prev_eqe_index++;
+
+		eq_entry = &eq_base[eq->ci];
+
+		/*
+		 * Make sure we read EQ entry contents after we've
+		 * checked the ownership bit.
+		 */
+		dma_rmb();
+
+		if (hdev->disabled && !hdev->reset_info.in_compute_reset) {
+			ctl = le32_to_cpu(eq_entry->hdr.ctl);
+			event_type = ((ctl & EQ_CTL_EVENT_TYPE_MASK) >> EQ_CTL_EVENT_TYPE_SHIFT);
+			dev_warn(hdev->dev,
+				"Device disabled but received an EQ event (%u)\n", event_type);
+			goto skip_irq;
+		}
+
+		handle_eqe_work = kmalloc(sizeof(*handle_eqe_work), GFP_ATOMIC);
+		if (handle_eqe_work) {
+			INIT_WORK(&handle_eqe_work->eq_work, irq_handle_eqe);
+			handle_eqe_work->hdev = hdev;
+
+			memcpy(&handle_eqe_work->eq_entry, eq_entry,
+					sizeof(*eq_entry));
+
+			queue_work(hdev->eq_wq, &handle_eqe_work->eq_work);
+		}
+skip_irq:
+		/* Clear EQ entry ready bit */
+		eq_entry->hdr.ctl =
+			cpu_to_le32(le32_to_cpu(eq_entry->hdr.ctl) &
+							~EQ_CTL_READY_MASK);
+
+		eq->ci = hl_eq_inc_ptr(eq->ci);
+
+		hdev->asic_funcs->update_eq_ci(hdev, eq->ci);
+	}
+
+	return IRQ_HANDLED;
+}
+
+/**
+ * hl_irq_handler_dec_abnrm - Decoder error interrupt handler
+ * @irq: IRQ number
+ * @arg: pointer to decoder structure.
+ */
+irqreturn_t hl_irq_handler_dec_abnrm(int irq, void *arg)
+{
+	struct hl_dec *dec = arg;
+
+	schedule_work(&dec->abnrm_intr_work);
+
+	return IRQ_HANDLED;
+}
+
+/**
+ * hl_cq_init - main initialization function for an cq object
+ *
+ * @hdev: pointer to device structure
+ * @q: pointer to cq structure
+ * @hw_queue_id: The H/W queue ID this completion queue belongs to
+ *               HL_INVALID_QUEUE if cq is not attached to any specific queue
+ *
+ * Allocate dma-able memory for the completion queue and initialize fields
+ * Returns 0 on success
+ */
+int hl_cq_init(struct hl_device *hdev, struct hl_cq *q, u32 hw_queue_id)
+{
+	void *p;
+
+	p = hl_asic_dma_alloc_coherent(hdev, HL_CQ_SIZE_IN_BYTES, &q->bus_address,
+					GFP_KERNEL | __GFP_ZERO);
+	if (!p)
+		return -ENOMEM;
+
+	q->hdev = hdev;
+	q->kernel_address = p;
+	q->hw_queue_id = hw_queue_id;
+	q->ci = 0;
+	q->pi = 0;
+
+	atomic_set(&q->free_slots_cnt, HL_CQ_LENGTH);
+
+	return 0;
+}
+
+/**
+ * hl_cq_fini - destroy completion queue
+ *
+ * @hdev: pointer to device structure
+ * @q: pointer to cq structure
+ *
+ * Free the completion queue memory
+ */
+void hl_cq_fini(struct hl_device *hdev, struct hl_cq *q)
+{
+	hl_asic_dma_free_coherent(hdev, HL_CQ_SIZE_IN_BYTES, q->kernel_address, q->bus_address);
+}
+
+void hl_cq_reset(struct hl_device *hdev, struct hl_cq *q)
+{
+	q->ci = 0;
+	q->pi = 0;
+
+	atomic_set(&q->free_slots_cnt, HL_CQ_LENGTH);
+
+	/*
+	 * It's not enough to just reset the PI/CI because the H/W may have
+	 * written valid completion entries before it was halted and therefore
+	 * we need to clean the actual queues so we won't process old entries
+	 * when the device is operational again
+	 */
+
+	memset(q->kernel_address, 0, HL_CQ_SIZE_IN_BYTES);
+}
+
+/**
+ * hl_eq_init - main initialization function for an event queue object
+ *
+ * @hdev: pointer to device structure
+ * @q: pointer to eq structure
+ *
+ * Allocate dma-able memory for the event queue and initialize fields
+ * Returns 0 on success
+ */
+int hl_eq_init(struct hl_device *hdev, struct hl_eq *q)
+{
+	u32 size = hdev->asic_prop.fw_event_queue_size ? : HL_EQ_SIZE_IN_BYTES;
+	void *p;
+
+	p = hl_cpu_accessible_dma_pool_alloc(hdev, size, &q->bus_address);
+	if (!p)
+		return -ENOMEM;
+
+	q->hdev = hdev;
+	q->kernel_address = p;
+	q->size = size;
+	q->ci = 0;
+	q->prev_eqe_index = 0;
+
+	return 0;
+}
+
+/**
+ * hl_eq_fini - destroy event queue
+ *
+ * @hdev: pointer to device structure
+ * @q: pointer to eq structure
+ *
+ * Free the event queue memory
+ */
+void hl_eq_fini(struct hl_device *hdev, struct hl_eq *q)
+{
+	flush_workqueue(hdev->eq_wq);
+
+	hl_cpu_accessible_dma_pool_free(hdev, q->size, q->kernel_address);
+}
+
+void hl_eq_reset(struct hl_device *hdev, struct hl_eq *q)
+{
+	q->ci = 0;
+	q->prev_eqe_index = 0;
+
+	/*
+	 * It's not enough to just reset the PI/CI because the H/W may have
+	 * written valid completion entries before it was halted and therefore
+	 * we need to clean the actual queues so we won't process old entries
+	 * when the device is operational again
+	 */
+
+	memset(q->kernel_address, 0, q->size);
+}
+
+void hl_eq_dump(struct hl_device *hdev, struct hl_eq *q)
+{
+	u32 eq_length, eqe_size, ctl, ready, mode, type, index;
+	struct hl_eq_header *hdr;
+	u8 *ptr;
+	int i;
+
+	eq_length = HL_EQ_LENGTH;
+	eqe_size = q->size / HL_EQ_LENGTH;
+
+	dev_info(hdev->dev, "Contents of EQ entries headers:\n");
+
+	for (i = 0, ptr = q->kernel_address ; i < eq_length ; ++i, ptr += eqe_size) {
+		hdr = (struct hl_eq_header *) ptr;
+		ctl = le32_to_cpu(hdr->ctl);
+		ready = FIELD_GET(EQ_CTL_READY_MASK, ctl);
+		mode = FIELD_GET(EQ_CTL_EVENT_MODE_MASK, ctl);
+		type = FIELD_GET(EQ_CTL_EVENT_TYPE_MASK, ctl);
+		index = FIELD_GET(EQ_CTL_INDEX_MASK, ctl);
+
+		dev_info(hdev->dev, "%02u: %#010x [ready: %u, mode %u, type %04u, index %05u]\n",
+				i, ctl, ready, mode, type, index);
+	}
+}
diff --git a/drivers/accel/habanalabs/common/memory.c b/drivers/accel/habanalabs/common/memory.c
new file mode 100644
index 000000000000..633db4bff46f
--- /dev/null
+++ b/drivers/accel/habanalabs/common/memory.c
@@ -0,0 +1,2938 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Copyright 2016-2022 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ */
+
+#include <uapi/drm/habanalabs_accel.h>
+#include "habanalabs.h"
+#include "../include/hw_ip/mmu/mmu_general.h"
+
+#include <linux/uaccess.h>
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+#include <linux/pci-p2pdma.h>
+
+MODULE_IMPORT_NS("DMA_BUF");
+
+#define HL_MMU_DEBUG	0
+
+/* use small pages for supporting non-pow2 (32M/40M/48M) DRAM phys page sizes */
+#define DRAM_POOL_PAGE_SIZE	SZ_8M
+
+#define MEM_HANDLE_INVALID	ULONG_MAX
+
+static int allocate_timestamps_buffers(struct hl_fpriv *hpriv,
+			struct hl_mem_in *args, u64 *handle);
+
+static int set_alloc_page_size(struct hl_device *hdev, struct hl_mem_in *args, u32 *page_size)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	u64 psize;
+
+	/*
+	 * for ASIC that supports setting the allocation page size by user we will address
+	 * user's choice only if it is not 0 (as 0 means taking the default page size)
+	 */
+	if (prop->supports_user_set_page_size && args->alloc.page_size) {
+		psize = args->alloc.page_size;
+
+		if (!is_power_of_2(psize)) {
+			dev_err(hdev->dev, "user page size (%#llx) is not power of 2\n", psize);
+			return -EINVAL;
+		}
+	} else {
+		psize = prop->device_mem_alloc_default_page_size;
+	}
+
+	*page_size = psize;
+
+	return 0;
+}
+
+/*
+ * The va ranges in context object contain a list with the available chunks of
+ * device virtual memory.
+ * There is one range for host allocations and one for DRAM allocations.
+ *
+ * On initialization each range contains one chunk of all of its available
+ * virtual range which is a half of the total device virtual range.
+ *
+ * On each mapping of physical pages, a suitable virtual range chunk (with a
+ * minimum size) is selected from the list. If the chunk size equals the
+ * requested size, the chunk is returned. Otherwise, the chunk is split into
+ * two chunks - one to return as result and a remainder to stay in the list.
+ *
+ * On each Unmapping of a virtual address, the relevant virtual chunk is
+ * returned to the list. The chunk is added to the list and if its edges match
+ * the edges of the adjacent chunks (means a contiguous chunk can be created),
+ * the chunks are merged.
+ *
+ * On finish, the list is checked to have only one chunk of all the relevant
+ * virtual range (which is a half of the device total virtual range).
+ * If not (means not all mappings were unmapped), a warning is printed.
+ */
+
+/*
+ * alloc_device_memory() - allocate device memory.
+ * @ctx: pointer to the context structure.
+ * @args: host parameters containing the requested size.
+ * @ret_handle: result handle.
+ *
+ * This function does the following:
+ * - Allocate the requested size rounded up to 'dram_page_size' pages.
+ * - Return unique handle for later map/unmap/free.
+ */
+static int alloc_device_memory(struct hl_ctx *ctx, struct hl_mem_in *args,
+				u32 *ret_handle)
+{
+	struct hl_device *hdev = ctx->hdev;
+	struct hl_vm *vm = &hdev->vm;
+	struct hl_vm_phys_pg_pack *phys_pg_pack;
+	u64 paddr = 0, total_size, num_pgs, i;
+	u32 num_curr_pgs, page_size;
+	bool contiguous;
+	int handle, rc;
+
+	num_curr_pgs = 0;
+
+	rc = set_alloc_page_size(hdev, args, &page_size);
+	if (rc)
+		return rc;
+
+	num_pgs = DIV_ROUND_UP_ULL(args->alloc.mem_size, page_size);
+	total_size = num_pgs * page_size;
+
+	if (!total_size) {
+		dev_err(hdev->dev, "Cannot allocate 0 bytes\n");
+		return -EINVAL;
+	}
+
+	contiguous = args->flags & HL_MEM_CONTIGUOUS;
+
+	if (contiguous) {
+		if (is_power_of_2(page_size))
+			paddr = (uintptr_t) gen_pool_dma_alloc_align(vm->dram_pg_pool,
+								     total_size, NULL, page_size);
+		else
+			paddr = gen_pool_alloc(vm->dram_pg_pool, total_size);
+		if (!paddr) {
+			dev_err(hdev->dev,
+				"Cannot allocate %llu contiguous pages with total size of %llu\n",
+				num_pgs, total_size);
+			return -ENOMEM;
+		}
+	}
+
+	phys_pg_pack = kzalloc(sizeof(*phys_pg_pack), GFP_KERNEL);
+	if (!phys_pg_pack) {
+		rc = -ENOMEM;
+		goto pages_pack_err;
+	}
+
+	phys_pg_pack->vm_type = VM_TYPE_PHYS_PACK;
+	phys_pg_pack->asid = ctx->asid;
+	phys_pg_pack->npages = num_pgs;
+	phys_pg_pack->page_size = page_size;
+	phys_pg_pack->total_size = total_size;
+	phys_pg_pack->flags = args->flags;
+	phys_pg_pack->contiguous = contiguous;
+
+	phys_pg_pack->pages = kvmalloc_array(num_pgs, sizeof(u64), GFP_KERNEL);
+	if (ZERO_OR_NULL_PTR(phys_pg_pack->pages)) {
+		rc = -ENOMEM;
+		goto pages_arr_err;
+	}
+
+	if (phys_pg_pack->contiguous) {
+		for (i = 0 ; i < num_pgs ; i++)
+			phys_pg_pack->pages[i] = paddr + i * page_size;
+	} else {
+		for (i = 0 ; i < num_pgs ; i++) {
+			if (is_power_of_2(page_size))
+				phys_pg_pack->pages[i] =
+					(uintptr_t)gen_pool_dma_alloc_align(vm->dram_pg_pool,
+									    page_size, NULL,
+									    page_size);
+			else
+				phys_pg_pack->pages[i] = gen_pool_alloc(vm->dram_pg_pool,
+									page_size);
+
+			if (!phys_pg_pack->pages[i]) {
+				dev_err(hdev->dev,
+					"Cannot allocate device memory (out of memory)\n");
+				rc = -ENOMEM;
+				goto page_err;
+			}
+
+			num_curr_pgs++;
+		}
+	}
+
+	spin_lock(&vm->idr_lock);
+	handle = idr_alloc(&vm->phys_pg_pack_handles, phys_pg_pack, 1, 0,
+				GFP_ATOMIC);
+	spin_unlock(&vm->idr_lock);
+
+	if (handle < 0) {
+		dev_err(hdev->dev, "Failed to get handle for page\n");
+		rc = -EFAULT;
+		goto idr_err;
+	}
+
+	for (i = 0 ; i < num_pgs ; i++)
+		kref_get(&vm->dram_pg_pool_refcount);
+
+	phys_pg_pack->handle = handle;
+
+	atomic64_add(phys_pg_pack->total_size, &ctx->dram_phys_mem);
+	atomic64_add(phys_pg_pack->total_size, &hdev->dram_used_mem);
+
+	*ret_handle = handle;
+
+	return 0;
+
+idr_err:
+page_err:
+	if (!phys_pg_pack->contiguous)
+		for (i = 0 ; i < num_curr_pgs ; i++)
+			gen_pool_free(vm->dram_pg_pool, phys_pg_pack->pages[i],
+					page_size);
+
+	kvfree(phys_pg_pack->pages);
+pages_arr_err:
+	kfree(phys_pg_pack);
+pages_pack_err:
+	if (contiguous)
+		gen_pool_free(vm->dram_pg_pool, paddr, total_size);
+
+	return rc;
+}
+
+/**
+ * dma_map_host_va() - DMA mapping of the given host virtual address.
+ * @hdev: habanalabs device structure.
+ * @addr: the host virtual address of the memory area.
+ * @size: the size of the memory area.
+ * @p_userptr: pointer to result userptr structure.
+ *
+ * This function does the following:
+ * - Allocate userptr structure.
+ * - Pin the given host memory using the userptr structure.
+ * - Perform DMA mapping to have the DMA addresses of the pages.
+ */
+static int dma_map_host_va(struct hl_device *hdev, u64 addr, u64 size,
+				struct hl_userptr **p_userptr)
+{
+	struct hl_userptr *userptr;
+	int rc;
+
+	userptr = kzalloc(sizeof(*userptr), GFP_KERNEL);
+	if (!userptr) {
+		rc = -ENOMEM;
+		goto userptr_err;
+	}
+
+	rc = hl_pin_host_memory(hdev, addr, size, userptr);
+	if (rc)
+		goto pin_err;
+
+	userptr->dma_mapped = true;
+	userptr->dir = DMA_BIDIRECTIONAL;
+	userptr->vm_type = VM_TYPE_USERPTR;
+
+	*p_userptr = userptr;
+
+	rc = hl_dma_map_sgtable(hdev, userptr->sgt, DMA_BIDIRECTIONAL);
+	if (rc) {
+		dev_err(hdev->dev, "failed to map sgt with DMA region\n");
+		goto dma_map_err;
+	}
+
+	return 0;
+
+dma_map_err:
+	hl_unpin_host_memory(hdev, userptr);
+pin_err:
+	kfree(userptr);
+userptr_err:
+
+	return rc;
+}
+
+/**
+ * dma_unmap_host_va() - DMA unmapping of the given host virtual address.
+ * @hdev: habanalabs device structure.
+ * @userptr: userptr to free.
+ *
+ * This function does the following:
+ * - Unpins the physical pages.
+ * - Frees the userptr structure.
+ */
+static void dma_unmap_host_va(struct hl_device *hdev,
+				struct hl_userptr *userptr)
+{
+	hl_unpin_host_memory(hdev, userptr);
+	kfree(userptr);
+}
+
+/**
+ * dram_pg_pool_do_release() - free DRAM pages pool
+ * @ref: pointer to reference object.
+ *
+ * This function does the following:
+ * - Frees the idr structure of physical pages handles.
+ * - Frees the generic pool of DRAM physical pages.
+ */
+static void dram_pg_pool_do_release(struct kref *ref)
+{
+	struct hl_vm *vm = container_of(ref, struct hl_vm,
+			dram_pg_pool_refcount);
+
+	/*
+	 * free the idr here as only here we know for sure that there are no
+	 * allocated physical pages and hence there are no handles in use
+	 */
+	idr_destroy(&vm->phys_pg_pack_handles);
+	gen_pool_destroy(vm->dram_pg_pool);
+}
+
+/**
+ * free_phys_pg_pack() - free physical page pack.
+ * @hdev: habanalabs device structure.
+ * @phys_pg_pack: physical page pack to free.
+ *
+ * This function does the following:
+ * - For DRAM memory only
+ *   - iterate over the pack, free each physical block structure by
+ *     returning it to the general pool.
+ * - Free the hl_vm_phys_pg_pack structure.
+ */
+static void free_phys_pg_pack(struct hl_device *hdev,
+				struct hl_vm_phys_pg_pack *phys_pg_pack)
+{
+	struct hl_vm *vm = &hdev->vm;
+	u64 i;
+
+	if (phys_pg_pack->created_from_userptr)
+		goto end;
+
+	if (phys_pg_pack->contiguous) {
+		gen_pool_free(vm->dram_pg_pool, phys_pg_pack->pages[0],
+			phys_pg_pack->total_size);
+
+		for (i = 0; i < phys_pg_pack->npages ; i++)
+			kref_put(&vm->dram_pg_pool_refcount,
+				dram_pg_pool_do_release);
+	} else {
+		for (i = 0 ; i < phys_pg_pack->npages ; i++) {
+			gen_pool_free(vm->dram_pg_pool,
+				phys_pg_pack->pages[i],
+				phys_pg_pack->page_size);
+			kref_put(&vm->dram_pg_pool_refcount,
+				dram_pg_pool_do_release);
+		}
+	}
+
+end:
+	kvfree(phys_pg_pack->pages);
+	kfree(phys_pg_pack);
+
+	return;
+}
+
+/**
+ * free_device_memory() - free device memory.
+ * @ctx: pointer to the context structure.
+ * @args: host parameters containing the requested size.
+ *
+ * This function does the following:
+ * - Free the device memory related to the given handle.
+ */
+static int free_device_memory(struct hl_ctx *ctx, struct hl_mem_in *args)
+{
+	struct hl_device *hdev = ctx->hdev;
+	struct hl_vm *vm = &hdev->vm;
+	struct hl_vm_phys_pg_pack *phys_pg_pack;
+	u32 handle = args->free.handle;
+
+	spin_lock(&vm->idr_lock);
+	phys_pg_pack = idr_find(&vm->phys_pg_pack_handles, handle);
+	if (!phys_pg_pack) {
+		spin_unlock(&vm->idr_lock);
+		dev_err(hdev->dev, "free device memory failed, no match for handle %u\n", handle);
+		return -EINVAL;
+	}
+
+	if (atomic_read(&phys_pg_pack->mapping_cnt) > 0) {
+		spin_unlock(&vm->idr_lock);
+		dev_err(hdev->dev, "handle %u is mapped, cannot free\n", handle);
+		return -EINVAL;
+	}
+
+	/* must remove from idr before the freeing of the physical pages as the refcount of the pool
+	 * is also the trigger of the idr destroy
+	 */
+	idr_remove(&vm->phys_pg_pack_handles, handle);
+	spin_unlock(&vm->idr_lock);
+
+	atomic64_sub(phys_pg_pack->total_size, &ctx->dram_phys_mem);
+	atomic64_sub(phys_pg_pack->total_size, &hdev->dram_used_mem);
+
+	free_phys_pg_pack(hdev, phys_pg_pack);
+
+	return 0;
+}
+
+/**
+ * clear_va_list_locked() - free virtual addresses list.
+ * @hdev: habanalabs device structure.
+ * @va_list: list of virtual addresses to free.
+ *
+ * This function does the following:
+ * - Iterate over the list and free each virtual addresses block.
+ *
+ * This function should be called only when va_list lock is taken.
+ */
+static void clear_va_list_locked(struct hl_device *hdev,
+		struct list_head *va_list)
+{
+	struct hl_vm_va_block *va_block, *tmp;
+
+	list_for_each_entry_safe(va_block, tmp, va_list, node) {
+		list_del(&va_block->node);
+		kfree(va_block);
+	}
+}
+
+/**
+ * print_va_list_locked() - print virtual addresses list.
+ * @hdev: habanalabs device structure.
+ * @va_list: list of virtual addresses to print.
+ *
+ * This function does the following:
+ * - Iterate over the list and print each virtual addresses block.
+ *
+ * This function should be called only when va_list lock is taken.
+ */
+static void print_va_list_locked(struct hl_device *hdev,
+		struct list_head *va_list)
+{
+#if HL_MMU_DEBUG
+	struct hl_vm_va_block *va_block;
+
+	dev_dbg(hdev->dev, "print va list:\n");
+
+	list_for_each_entry(va_block, va_list, node)
+		dev_dbg(hdev->dev,
+			"va block, start: 0x%llx, end: 0x%llx, size: %llu\n",
+			va_block->start, va_block->end, va_block->size);
+#endif
+}
+
+/**
+ * merge_va_blocks_locked() - merge a virtual block if possible.
+ * @hdev: pointer to the habanalabs device structure.
+ * @va_list: pointer to the virtual addresses block list.
+ * @va_block: virtual block to merge with adjacent blocks.
+ *
+ * This function does the following:
+ * - Merge the given blocks with the adjacent blocks if their virtual ranges
+ *   create a contiguous virtual range.
+ *
+ * This Function should be called only when va_list lock is taken.
+ */
+static void merge_va_blocks_locked(struct hl_device *hdev,
+		struct list_head *va_list, struct hl_vm_va_block *va_block)
+{
+	struct hl_vm_va_block *prev, *next;
+
+	prev = list_prev_entry(va_block, node);
+	if (&prev->node != va_list && prev->end + 1 == va_block->start) {
+		prev->end = va_block->end;
+		prev->size = prev->end - prev->start + 1;
+		list_del(&va_block->node);
+		kfree(va_block);
+		va_block = prev;
+	}
+
+	next = list_next_entry(va_block, node);
+	if (&next->node != va_list && va_block->end + 1 == next->start) {
+		next->start = va_block->start;
+		next->size = next->end - next->start + 1;
+		list_del(&va_block->node);
+		kfree(va_block);
+	}
+}
+
+/**
+ * add_va_block_locked() - add a virtual block to the virtual addresses list.
+ * @hdev: pointer to the habanalabs device structure.
+ * @va_list: pointer to the virtual addresses block list.
+ * @start: start virtual address.
+ * @end: end virtual address.
+ *
+ * This function does the following:
+ * - Add the given block to the virtual blocks list and merge with other blocks
+ *   if a contiguous virtual block can be created.
+ *
+ * This Function should be called only when va_list lock is taken.
+ */
+static int add_va_block_locked(struct hl_device *hdev,
+		struct list_head *va_list, u64 start, u64 end)
+{
+	struct hl_vm_va_block *va_block, *res = NULL;
+	u64 size = end - start + 1;
+
+	print_va_list_locked(hdev, va_list);
+
+	list_for_each_entry(va_block, va_list, node) {
+		/* TODO: remove upon matureness */
+		if (hl_mem_area_crosses_range(start, size, va_block->start,
+				va_block->end)) {
+			dev_err(hdev->dev,
+				"block crossing ranges at start 0x%llx, end 0x%llx\n",
+				va_block->start, va_block->end);
+			return -EINVAL;
+		}
+
+		if (va_block->end < start)
+			res = va_block;
+	}
+
+	va_block = kmalloc(sizeof(*va_block), GFP_KERNEL);
+	if (!va_block)
+		return -ENOMEM;
+
+	va_block->start = start;
+	va_block->end = end;
+	va_block->size = size;
+
+	if (!res)
+		list_add(&va_block->node, va_list);
+	else
+		list_add(&va_block->node, &res->node);
+
+	merge_va_blocks_locked(hdev, va_list, va_block);
+
+	print_va_list_locked(hdev, va_list);
+
+	return 0;
+}
+
+/**
+ * add_va_block() - wrapper for add_va_block_locked.
+ * @hdev: pointer to the habanalabs device structure.
+ * @va_range: pointer to the virtual addresses range object.
+ * @start: start virtual address.
+ * @end: end virtual address.
+ *
+ * This function does the following:
+ * - Takes the list lock and calls add_va_block_locked.
+ */
+static inline int add_va_block(struct hl_device *hdev,
+		struct hl_va_range *va_range, u64 start, u64 end)
+{
+	int rc;
+
+	mutex_lock(&va_range->lock);
+	rc = add_va_block_locked(hdev, &va_range->list, start, end);
+	mutex_unlock(&va_range->lock);
+
+	return rc;
+}
+
+/**
+ * is_hint_crossing_range() - check if hint address crossing specified reserved.
+ * @range_type: virtual space range type.
+ * @start_addr: start virtual address.
+ * @size: block size.
+ * @prop: asic properties structure to retrieve reserved ranges from.
+ */
+static inline bool is_hint_crossing_range(enum hl_va_range_type range_type,
+		u64 start_addr, u32 size, struct asic_fixed_properties *prop) {
+	bool range_cross;
+
+	if (range_type == HL_VA_RANGE_TYPE_DRAM)
+		range_cross =
+			hl_mem_area_crosses_range(start_addr, size,
+			prop->hints_dram_reserved_va_range.start_addr,
+			prop->hints_dram_reserved_va_range.end_addr);
+	else if (range_type == HL_VA_RANGE_TYPE_HOST)
+		range_cross =
+			hl_mem_area_crosses_range(start_addr,	size,
+			prop->hints_host_reserved_va_range.start_addr,
+			prop->hints_host_reserved_va_range.end_addr);
+	else
+		range_cross =
+			hl_mem_area_crosses_range(start_addr, size,
+			prop->hints_host_hpage_reserved_va_range.start_addr,
+			prop->hints_host_hpage_reserved_va_range.end_addr);
+
+	return range_cross;
+}
+
+/**
+ * get_va_block() - get a virtual block for the given size and alignment.
+ *
+ * @hdev: pointer to the habanalabs device structure.
+ * @va_range: pointer to the virtual addresses range.
+ * @size: requested block size.
+ * @hint_addr: hint for requested address by the user.
+ * @va_block_align: required alignment of the virtual block start address.
+ * @range_type: va range type (host, dram)
+ * @flags: additional memory flags, currently only uses HL_MEM_FORCE_HINT
+ *
+ * This function does the following:
+ * - Iterate on the virtual block list to find a suitable virtual block for the
+ *   given size, hint address and alignment.
+ * - Reserve the requested block and update the list.
+ * - Return the start address of the virtual block.
+ */
+static u64 get_va_block(struct hl_device *hdev,
+				struct hl_va_range *va_range,
+				u64 size, u64 hint_addr, u32 va_block_align,
+				enum hl_va_range_type range_type,
+				u32 flags)
+{
+	struct hl_vm_va_block *va_block, *new_va_block = NULL;
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	u64 tmp_hint_addr, valid_start, valid_size, prev_start, prev_end,
+		align_mask, reserved_valid_start = 0, reserved_valid_size = 0,
+		dram_hint_mask = prop->dram_hints_align_mask;
+	bool add_prev = false;
+	bool is_align_pow_2  = is_power_of_2(va_range->page_size);
+	bool is_hint_dram_addr = hl_is_dram_va(hdev, hint_addr);
+	bool force_hint = flags & HL_MEM_FORCE_HINT;
+	int rc;
+
+	if (is_align_pow_2)
+		align_mask = ~((u64)va_block_align - 1);
+	else
+		/*
+		 * with non-power-of-2 range we work only with page granularity
+		 * and the start address is page aligned,
+		 * so no need for alignment checking.
+		 */
+		size = DIV_ROUND_UP_ULL(size, va_range->page_size) *
+							va_range->page_size;
+
+	tmp_hint_addr = hint_addr & ~dram_hint_mask;
+
+	/* Check if we need to ignore hint address */
+	if ((is_align_pow_2 && (hint_addr & (va_block_align - 1))) ||
+			(!is_align_pow_2 && is_hint_dram_addr &&
+			do_div(tmp_hint_addr, va_range->page_size))) {
+
+		if (force_hint) {
+			/* Hint must be respected, so here we just fail */
+			dev_err(hdev->dev,
+				"Hint address 0x%llx is not page aligned - cannot be respected\n",
+				hint_addr);
+			return 0;
+		}
+
+		dev_dbg(hdev->dev,
+			"Hint address 0x%llx will be ignored because it is not aligned\n",
+			hint_addr);
+		hint_addr = 0;
+	}
+
+	mutex_lock(&va_range->lock);
+
+	print_va_list_locked(hdev, &va_range->list);
+
+	list_for_each_entry(va_block, &va_range->list, node) {
+		/* Calc the first possible aligned addr */
+		valid_start = va_block->start;
+
+		if (is_align_pow_2 && (valid_start & (va_block_align - 1))) {
+			valid_start &= align_mask;
+			valid_start += va_block_align;
+			if (valid_start > va_block->end)
+				continue;
+		}
+
+		valid_size = va_block->end - valid_start + 1;
+		if (valid_size < size)
+			continue;
+
+		/*
+		 * In case hint address is 0, and hints_range_reservation
+		 * property enabled, then avoid allocating va blocks from the
+		 * range reserved for hint addresses
+		 */
+		if (prop->hints_range_reservation && !hint_addr)
+			if (is_hint_crossing_range(range_type, valid_start,
+					size, prop))
+				continue;
+
+		/* Pick the minimal length block which has the required size */
+		if (!new_va_block || (valid_size < reserved_valid_size)) {
+			new_va_block = va_block;
+			reserved_valid_start = valid_start;
+			reserved_valid_size = valid_size;
+		}
+
+		if (hint_addr && hint_addr >= valid_start &&
+					(hint_addr + size) <= va_block->end) {
+			new_va_block = va_block;
+			reserved_valid_start = hint_addr;
+			reserved_valid_size = valid_size;
+			break;
+		}
+	}
+
+	if (!new_va_block) {
+		dev_err(hdev->dev, "no available va block for size %llu\n",
+								size);
+		goto out;
+	}
+
+	if (force_hint && reserved_valid_start != hint_addr) {
+		/* Hint address must be respected. If we are here - this means
+		 * we could not respect it.
+		 */
+		dev_err(hdev->dev,
+			"Hint address 0x%llx could not be respected\n",
+			hint_addr);
+		reserved_valid_start = 0;
+		goto out;
+	}
+
+	/*
+	 * Check if there is some leftover range due to reserving the new
+	 * va block, then return it to the main virtual addresses list.
+	 */
+	if (reserved_valid_start > new_va_block->start) {
+		prev_start = new_va_block->start;
+		prev_end = reserved_valid_start - 1;
+
+		new_va_block->start = reserved_valid_start;
+		new_va_block->size = reserved_valid_size;
+
+		add_prev = true;
+	}
+
+	if (new_va_block->size > size) {
+		new_va_block->start += size;
+		new_va_block->size = new_va_block->end - new_va_block->start + 1;
+	} else {
+		list_del(&new_va_block->node);
+		kfree(new_va_block);
+	}
+
+	if (add_prev) {
+		rc = add_va_block_locked(hdev, &va_range->list, prev_start, prev_end);
+		if (rc) {
+			reserved_valid_start = 0;
+			goto out;
+		}
+	}
+
+	print_va_list_locked(hdev, &va_range->list);
+out:
+	mutex_unlock(&va_range->lock);
+
+	return reserved_valid_start;
+}
+
+/*
+ * hl_reserve_va_block() - reserve a virtual block of a given size.
+ * @hdev: pointer to the habanalabs device structure.
+ * @ctx: current context
+ * @type: virtual addresses range type.
+ * @size: requested block size.
+ * @alignment: required alignment in bytes of the virtual block start address,
+ *             0 means no alignment.
+ *
+ * This function does the following:
+ * - Iterate on the virtual block list to find a suitable virtual block for the
+ *   given size and alignment.
+ * - Reserve the requested block and update the list.
+ * - Return the start address of the virtual block.
+ */
+u64 hl_reserve_va_block(struct hl_device *hdev, struct hl_ctx *ctx,
+		enum hl_va_range_type type, u64 size, u32 alignment)
+{
+	return get_va_block(hdev, ctx->va_range[type], size, 0,
+			max(alignment, ctx->va_range[type]->page_size),
+			type, 0);
+}
+
+/**
+ * hl_get_va_range_type() - get va_range type for the given address and size.
+ * @ctx: context to fetch va_range from.
+ * @address: the start address of the area we want to validate.
+ * @size: the size in bytes of the area we want to validate.
+ * @type: returned va_range type.
+ *
+ * Return: true if the area is inside a valid range, false otherwise.
+ */
+static int hl_get_va_range_type(struct hl_ctx *ctx, u64 address, u64 size,
+			enum hl_va_range_type *type)
+{
+	int i;
+
+	for (i = 0 ; i < HL_VA_RANGE_TYPE_MAX; i++) {
+		if (hl_mem_area_inside_range(address, size,
+				ctx->va_range[i]->start_addr,
+				ctx->va_range[i]->end_addr)) {
+			*type = i;
+			return 0;
+		}
+	}
+
+	return -EINVAL;
+}
+
+/**
+ * hl_unreserve_va_block() - wrapper for add_va_block to unreserve a va block.
+ * @hdev: pointer to the habanalabs device structure
+ * @ctx: pointer to the context structure.
+ * @start_addr: start virtual address.
+ * @size: number of bytes to unreserve.
+ *
+ * This function does the following:
+ * - Takes the list lock and calls add_va_block_locked.
+ */
+int hl_unreserve_va_block(struct hl_device *hdev, struct hl_ctx *ctx,
+		u64 start_addr, u64 size)
+{
+	enum hl_va_range_type type;
+	int rc;
+
+	rc = hl_get_va_range_type(ctx, start_addr, size, &type);
+	if (rc) {
+		dev_err(hdev->dev,
+			"cannot find va_range for va %#llx size %llu",
+			start_addr, size);
+		return rc;
+	}
+
+	rc = add_va_block(hdev, ctx->va_range[type], start_addr,
+						start_addr + size - 1);
+	if (rc)
+		dev_warn(hdev->dev,
+			"add va block failed for vaddr: 0x%llx\n", start_addr);
+
+	return rc;
+}
+
+/**
+ * init_phys_pg_pack_from_userptr() - initialize physical page pack from host
+ *                                    memory
+ * @ctx: pointer to the context structure.
+ * @userptr: userptr to initialize from.
+ * @pphys_pg_pack: result pointer.
+ * @force_regular_page: tell the function to ignore huge page optimization,
+ *                      even if possible. Needed for cases where the device VA
+ *                      is allocated before we know the composition of the
+ *                      physical pages
+ *
+ * This function does the following:
+ * - Create a physical page pack from the physical pages related to the given
+ *   virtual block.
+ */
+static int init_phys_pg_pack_from_userptr(struct hl_ctx *ctx,
+				struct hl_userptr *userptr,
+				struct hl_vm_phys_pg_pack **pphys_pg_pack,
+				bool force_regular_page)
+{
+	u32 npages, page_size = PAGE_SIZE,
+		huge_page_size = ctx->hdev->asic_prop.pmmu_huge.page_size;
+	u32 pgs_in_huge_page = huge_page_size >> __ffs(page_size);
+	struct hl_vm_phys_pg_pack *phys_pg_pack;
+	bool first = true, is_huge_page_opt;
+	u64 page_mask, total_npages;
+	struct scatterlist *sg;
+	dma_addr_t dma_addr;
+	int rc, i, j;
+
+	phys_pg_pack = kzalloc(sizeof(*phys_pg_pack), GFP_KERNEL);
+	if (!phys_pg_pack)
+		return -ENOMEM;
+
+	phys_pg_pack->vm_type = userptr->vm_type;
+	phys_pg_pack->created_from_userptr = true;
+	phys_pg_pack->asid = ctx->asid;
+	atomic_set(&phys_pg_pack->mapping_cnt, 1);
+
+	is_huge_page_opt = (force_regular_page ? false : true);
+
+	/* Only if all dma_addrs are aligned to 2MB and their
+	 * sizes is at least 2MB, we can use huge page mapping.
+	 * We limit the 2MB optimization to this condition,
+	 * since later on we acquire the related VA range as one
+	 * consecutive block.
+	 */
+	total_npages = 0;
+	for_each_sgtable_dma_sg(userptr->sgt, sg, i) {
+		npages = hl_get_sg_info(sg, &dma_addr);
+
+		total_npages += npages;
+
+		if ((npages % pgs_in_huge_page) ||
+					(dma_addr & (huge_page_size - 1)))
+			is_huge_page_opt = false;
+	}
+
+	if (is_huge_page_opt) {
+		page_size = huge_page_size;
+		do_div(total_npages, pgs_in_huge_page);
+	}
+
+	page_mask = ~(((u64) page_size) - 1);
+
+	phys_pg_pack->pages = kvmalloc_array(total_npages, sizeof(u64),
+						GFP_KERNEL);
+	if (ZERO_OR_NULL_PTR(phys_pg_pack->pages)) {
+		rc = -ENOMEM;
+		goto page_pack_arr_mem_err;
+	}
+
+	phys_pg_pack->npages = total_npages;
+	phys_pg_pack->page_size = page_size;
+	phys_pg_pack->total_size = total_npages * page_size;
+
+	j = 0;
+	for_each_sgtable_dma_sg(userptr->sgt, sg, i) {
+		npages = hl_get_sg_info(sg, &dma_addr);
+
+		/* align down to physical page size and save the offset */
+		if (first) {
+			first = false;
+			phys_pg_pack->offset = dma_addr & (page_size - 1);
+			dma_addr &= page_mask;
+		}
+
+		while (npages) {
+			phys_pg_pack->pages[j++] = dma_addr;
+			dma_addr += page_size;
+
+			if (is_huge_page_opt)
+				npages -= pgs_in_huge_page;
+			else
+				npages--;
+		}
+	}
+
+	*pphys_pg_pack = phys_pg_pack;
+
+	return 0;
+
+page_pack_arr_mem_err:
+	kfree(phys_pg_pack);
+
+	return rc;
+}
+
+/**
+ * map_phys_pg_pack() - maps the physical page pack..
+ * @ctx: pointer to the context structure.
+ * @vaddr: start address of the virtual area to map from.
+ * @phys_pg_pack: the pack of physical pages to map to.
+ *
+ * This function does the following:
+ * - Maps each chunk of virtual memory to matching physical chunk.
+ * - Stores number of successful mappings in the given argument.
+ * - Returns 0 on success, error code otherwise.
+ */
+static int map_phys_pg_pack(struct hl_ctx *ctx, u64 vaddr,
+				struct hl_vm_phys_pg_pack *phys_pg_pack)
+{
+	struct hl_device *hdev = ctx->hdev;
+	u64 next_vaddr = vaddr, paddr, mapped_pg_cnt = 0, i;
+	u32 page_size = phys_pg_pack->page_size;
+	int rc = 0;
+	bool is_host_addr;
+
+	for (i = 0 ; i < phys_pg_pack->npages ; i++) {
+		paddr = phys_pg_pack->pages[i];
+
+		rc = hl_mmu_map_page(ctx, next_vaddr, paddr, page_size,
+				(i + 1) == phys_pg_pack->npages);
+		if (rc) {
+			dev_err(hdev->dev,
+				"map failed (%d) for handle %u, npages: %llu, mapped: %llu\n",
+				rc, phys_pg_pack->handle, phys_pg_pack->npages,
+				mapped_pg_cnt);
+			goto err;
+		}
+
+		mapped_pg_cnt++;
+		next_vaddr += page_size;
+	}
+
+	return 0;
+
+err:
+	is_host_addr = !hl_is_dram_va(hdev, vaddr);
+
+	next_vaddr = vaddr;
+	for (i = 0 ; i < mapped_pg_cnt ; i++) {
+		if (hl_mmu_unmap_page(ctx, next_vaddr, page_size,
+					(i + 1) == mapped_pg_cnt))
+			dev_warn_ratelimited(hdev->dev,
+				"failed to unmap handle %u, va: 0x%llx, pa: 0x%llx, page size: %u\n",
+					phys_pg_pack->handle, next_vaddr,
+					phys_pg_pack->pages[i], page_size);
+
+		next_vaddr += page_size;
+
+		/*
+		 * unmapping on Palladium can be really long, so avoid a CPU
+		 * soft lockup bug by sleeping a little between unmapping pages
+		 *
+		 * In addition, on host num of pages could be huge,
+		 * because page size could be 4KB, so when unmapping host
+		 * pages sleep every 32K pages to avoid soft lockup
+		 */
+		if (hdev->pldm || (is_host_addr && (i & 0x7FFF) == 0))
+			usleep_range(50, 200);
+	}
+
+	return rc;
+}
+
+/**
+ * unmap_phys_pg_pack() - unmaps the physical page pack.
+ * @ctx: pointer to the context structure.
+ * @vaddr: start address of the virtual area to unmap.
+ * @phys_pg_pack: the pack of physical pages to unmap.
+ */
+static void unmap_phys_pg_pack(struct hl_ctx *ctx, u64 vaddr,
+				struct hl_vm_phys_pg_pack *phys_pg_pack)
+{
+	struct hl_device *hdev = ctx->hdev;
+	u64 next_vaddr, i;
+	bool is_host_addr;
+	u32 page_size;
+
+	is_host_addr = !hl_is_dram_va(hdev, vaddr);
+	page_size = phys_pg_pack->page_size;
+	next_vaddr = vaddr;
+
+	for (i = 0 ; i < phys_pg_pack->npages ; i++, next_vaddr += page_size) {
+		if (hl_mmu_unmap_page(ctx, next_vaddr, page_size,
+				       (i + 1) == phys_pg_pack->npages))
+			dev_warn_ratelimited(hdev->dev,
+			"unmap failed for vaddr: 0x%llx\n", next_vaddr);
+
+		/*
+		 * unmapping on Palladium can be really long, so avoid a CPU
+		 * soft lockup bug by sleeping a little between unmapping pages
+		 *
+		 * In addition, on host num of pages could be huge,
+		 * because page size could be 4KB, so when unmapping host
+		 * pages sleep every 32K pages to avoid soft lockup
+		 */
+		if (hdev->pldm || (is_host_addr && (i & 0x7FFF) == 0))
+			usleep_range(50, 200);
+	}
+}
+
+/**
+ * map_device_va() - map the given memory.
+ * @ctx: pointer to the context structure.
+ * @args: host parameters with handle/host virtual address.
+ * @device_addr: pointer to result device virtual address.
+ *
+ * This function does the following:
+ * - If given a physical device memory handle, map to a device virtual block
+ *   and return the start address of this block.
+ * - If given a host virtual address and size, find the related physical pages,
+ *   map a device virtual block to this pages and return the start address of
+ *   this block.
+ */
+static int map_device_va(struct hl_ctx *ctx, struct hl_mem_in *args, u64 *device_addr)
+{
+	struct hl_vm_phys_pg_pack *phys_pg_pack;
+	enum hl_va_range_type va_range_type = 0;
+	struct hl_device *hdev = ctx->hdev;
+	struct hl_userptr *userptr = NULL;
+	u32 handle = 0, va_block_align;
+	struct hl_vm_hash_node *hnode;
+	struct hl_vm *vm = &hdev->vm;
+	struct hl_va_range *va_range;
+	bool is_userptr, do_prefetch;
+	u64 ret_vaddr, hint_addr;
+	enum vm_type *vm_type;
+	int rc;
+
+	/* set map flags */
+	is_userptr = args->flags & HL_MEM_USERPTR;
+	do_prefetch = hdev->supports_mmu_prefetch && (args->flags & HL_MEM_PREFETCH);
+
+	/* Assume failure */
+	*device_addr = 0;
+
+	if (is_userptr) {
+		u64 addr = args->map_host.host_virt_addr,
+			size = args->map_host.mem_size;
+		u32 page_size = hdev->asic_prop.pmmu.page_size,
+			huge_page_size = hdev->asic_prop.pmmu_huge.page_size;
+
+		rc = dma_map_host_va(hdev, addr, size, &userptr);
+		if (rc)
+			return rc;
+
+		rc = init_phys_pg_pack_from_userptr(ctx, userptr,
+				&phys_pg_pack, false);
+		if (rc) {
+			dev_err(hdev->dev,
+				"unable to init page pack for vaddr 0x%llx\n",
+				addr);
+			goto init_page_pack_err;
+		}
+
+		vm_type = (enum vm_type *) userptr;
+		hint_addr = args->map_host.hint_addr;
+		handle = phys_pg_pack->handle;
+
+		/* get required alignment */
+		if (phys_pg_pack->page_size == page_size) {
+			va_range = ctx->va_range[HL_VA_RANGE_TYPE_HOST];
+			va_range_type = HL_VA_RANGE_TYPE_HOST;
+			/*
+			 * huge page alignment may be needed in case of regular
+			 * page mapping, depending on the host VA alignment
+			 */
+			if (addr & (huge_page_size - 1))
+				va_block_align = page_size;
+			else
+				va_block_align = huge_page_size;
+		} else {
+			/*
+			 * huge page alignment is needed in case of huge page
+			 * mapping
+			 */
+			va_range = ctx->va_range[HL_VA_RANGE_TYPE_HOST_HUGE];
+			va_range_type = HL_VA_RANGE_TYPE_HOST_HUGE;
+			va_block_align = huge_page_size;
+		}
+	} else {
+		handle = lower_32_bits(args->map_device.handle);
+
+		spin_lock(&vm->idr_lock);
+		phys_pg_pack = idr_find(&vm->phys_pg_pack_handles, handle);
+		if (!phys_pg_pack) {
+			spin_unlock(&vm->idr_lock);
+			dev_err(hdev->dev,
+				"no match for handle %u\n", handle);
+			return -EINVAL;
+		}
+
+		/* increment now to avoid freeing device memory while mapping */
+		atomic_inc(&phys_pg_pack->mapping_cnt);
+
+		spin_unlock(&vm->idr_lock);
+
+		vm_type = (enum vm_type *) phys_pg_pack;
+
+		hint_addr = args->map_device.hint_addr;
+
+		/* DRAM VA alignment is the same as the MMU page size */
+		va_range = ctx->va_range[HL_VA_RANGE_TYPE_DRAM];
+		va_range_type = HL_VA_RANGE_TYPE_DRAM;
+		va_block_align = hdev->asic_prop.dmmu.page_size;
+	}
+
+	/*
+	 * relevant for mapping device physical memory only, as host memory is
+	 * implicitly shared
+	 */
+	if (!is_userptr && !(phys_pg_pack->flags & HL_MEM_SHARED) &&
+			phys_pg_pack->asid != ctx->asid) {
+		dev_err(hdev->dev,
+			"Failed to map memory, handle %u is not shared\n",
+			handle);
+		rc = -EPERM;
+		goto shared_err;
+	}
+
+	hnode = kzalloc(sizeof(*hnode), GFP_KERNEL);
+	if (!hnode) {
+		rc = -ENOMEM;
+		goto hnode_err;
+	}
+
+	if (hint_addr && phys_pg_pack->offset) {
+		if (args->flags & HL_MEM_FORCE_HINT) {
+			/* Fail if hint must be respected but it can't be */
+			dev_err(hdev->dev,
+				"Hint address 0x%llx cannot be respected because source memory is not aligned 0x%x\n",
+				hint_addr, phys_pg_pack->offset);
+			rc = -EINVAL;
+			goto va_block_err;
+		}
+		dev_dbg(hdev->dev,
+			"Hint address 0x%llx will be ignored because source memory is not aligned 0x%x\n",
+			hint_addr, phys_pg_pack->offset);
+	}
+
+	ret_vaddr = get_va_block(hdev, va_range, phys_pg_pack->total_size,
+					hint_addr, va_block_align,
+					va_range_type, args->flags);
+	if (!ret_vaddr) {
+		dev_err(hdev->dev, "no available va block for handle %u\n",
+				handle);
+		rc = -ENOMEM;
+		goto va_block_err;
+	}
+
+	mutex_lock(&hdev->mmu_lock);
+
+	rc = map_phys_pg_pack(ctx, ret_vaddr, phys_pg_pack);
+	if (rc) {
+		dev_err(hdev->dev, "mapping page pack failed (%d) for handle %u\n",
+			rc, handle);
+		mutex_unlock(&hdev->mmu_lock);
+		goto map_err;
+	}
+
+	rc = hl_mmu_invalidate_cache_range(hdev, false, *vm_type | MMU_OP_SKIP_LOW_CACHE_INV,
+				ctx->asid, ret_vaddr, phys_pg_pack->total_size);
+	mutex_unlock(&hdev->mmu_lock);
+	if (rc)
+		goto map_err;
+
+	/*
+	 * prefetch is done upon user's request. it is performed in WQ as and so can
+	 * be outside the MMU lock. the operation itself is already protected by the mmu lock
+	 */
+	if (do_prefetch) {
+		rc = hl_mmu_prefetch_cache_range(ctx, *vm_type, ctx->asid, ret_vaddr,
+							phys_pg_pack->total_size);
+		if (rc)
+			goto map_err;
+	}
+
+	ret_vaddr += phys_pg_pack->offset;
+
+	hnode->ptr = vm_type;
+	hnode->vaddr = ret_vaddr;
+	hnode->handle = is_userptr ? MEM_HANDLE_INVALID : handle;
+
+	mutex_lock(&ctx->mem_hash_lock);
+	hash_add(ctx->mem_hash, &hnode->node, ret_vaddr);
+	mutex_unlock(&ctx->mem_hash_lock);
+
+	*device_addr = ret_vaddr;
+
+	if (is_userptr)
+		free_phys_pg_pack(hdev, phys_pg_pack);
+
+	return rc;
+
+map_err:
+	if (add_va_block(hdev, va_range, ret_vaddr,
+				ret_vaddr + phys_pg_pack->total_size - 1))
+		dev_warn(hdev->dev,
+			"release va block failed for handle 0x%x, vaddr: 0x%llx\n",
+				handle, ret_vaddr);
+
+va_block_err:
+	kfree(hnode);
+hnode_err:
+shared_err:
+	atomic_dec(&phys_pg_pack->mapping_cnt);
+	if (is_userptr)
+		free_phys_pg_pack(hdev, phys_pg_pack);
+init_page_pack_err:
+	if (is_userptr)
+		dma_unmap_host_va(hdev, userptr);
+
+	return rc;
+}
+
+/* Should be called while the context's mem_hash_lock is taken */
+static struct hl_vm_hash_node *get_vm_hash_node_locked(struct hl_ctx *ctx, u64 vaddr)
+{
+	struct hl_vm_hash_node *hnode;
+
+	hash_for_each_possible(ctx->mem_hash, hnode, node, vaddr)
+		if (vaddr == hnode->vaddr)
+			return hnode;
+
+	return NULL;
+}
+
+/**
+ * unmap_device_va() - unmap the given device virtual address.
+ * @ctx: pointer to the context structure.
+ * @args: host parameters with device virtual address to unmap.
+ * @ctx_free: true if in context free flow, false otherwise.
+ *
+ * This function does the following:
+ * - unmap the physical pages related to the given virtual address.
+ * - return the device virtual block to the virtual block list.
+ */
+static int unmap_device_va(struct hl_ctx *ctx, struct hl_mem_in *args,
+				bool ctx_free)
+{
+	struct hl_vm_phys_pg_pack *phys_pg_pack = NULL;
+	u64 vaddr = args->unmap.device_virt_addr;
+	struct asic_fixed_properties *prop;
+	struct hl_device *hdev = ctx->hdev;
+	struct hl_userptr *userptr = NULL;
+	struct hl_vm_hash_node *hnode;
+	struct hl_va_range *va_range;
+	enum vm_type *vm_type;
+	bool is_userptr;
+	int rc = 0;
+
+	prop = &hdev->asic_prop;
+
+	/* protect from double entrance */
+	mutex_lock(&ctx->mem_hash_lock);
+	hnode = get_vm_hash_node_locked(ctx, vaddr);
+	if (!hnode) {
+		mutex_unlock(&ctx->mem_hash_lock);
+		dev_err(hdev->dev, "unmap failed, no mem hnode for vaddr 0x%llx\n", vaddr);
+		return -EINVAL;
+	}
+
+	if (hnode->export_cnt) {
+		mutex_unlock(&ctx->mem_hash_lock);
+		dev_err(hdev->dev, "failed to unmap %#llx, memory is exported\n", vaddr);
+		return -EINVAL;
+	}
+
+	hash_del(&hnode->node);
+	mutex_unlock(&ctx->mem_hash_lock);
+
+	vm_type = hnode->ptr;
+
+	if (*vm_type == VM_TYPE_USERPTR) {
+		is_userptr = true;
+		userptr = hnode->ptr;
+
+		rc = init_phys_pg_pack_from_userptr(ctx, userptr, &phys_pg_pack,
+							false);
+		if (rc) {
+			dev_err(hdev->dev,
+				"unable to init page pack for vaddr 0x%llx\n",
+				vaddr);
+			goto vm_type_err;
+		}
+
+		if (phys_pg_pack->page_size ==
+					hdev->asic_prop.pmmu.page_size)
+			va_range = ctx->va_range[HL_VA_RANGE_TYPE_HOST];
+		else
+			va_range = ctx->va_range[HL_VA_RANGE_TYPE_HOST_HUGE];
+	} else if (*vm_type == VM_TYPE_PHYS_PACK) {
+		is_userptr = false;
+		va_range = ctx->va_range[HL_VA_RANGE_TYPE_DRAM];
+		phys_pg_pack = hnode->ptr;
+	} else {
+		dev_warn(hdev->dev,
+			"unmap failed, unknown vm desc for vaddr 0x%llx\n",
+				vaddr);
+		rc = -EFAULT;
+		goto vm_type_err;
+	}
+
+	if (atomic_read(&phys_pg_pack->mapping_cnt) == 0) {
+		dev_err(hdev->dev, "vaddr 0x%llx is not mapped\n", vaddr);
+		rc = -EINVAL;
+		goto mapping_cnt_err;
+	}
+
+	if (!is_userptr && !is_power_of_2(phys_pg_pack->page_size))
+		vaddr = prop->dram_base_address +
+			DIV_ROUND_DOWN_ULL(vaddr - prop->dram_base_address,
+						phys_pg_pack->page_size) *
+							phys_pg_pack->page_size;
+	else
+		vaddr &= ~(((u64) phys_pg_pack->page_size) - 1);
+
+	mutex_lock(&hdev->mmu_lock);
+
+	unmap_phys_pg_pack(ctx, vaddr, phys_pg_pack);
+
+	/*
+	 * During context free this function is called in a loop to clean all
+	 * the context mappings. Hence the cache invalidation can be called once
+	 * at the loop end rather than for each iteration
+	 */
+	if (!ctx_free)
+		rc = hl_mmu_invalidate_cache_range(hdev, true, *vm_type, ctx->asid, vaddr,
+							phys_pg_pack->total_size);
+
+	mutex_unlock(&hdev->mmu_lock);
+
+	/*
+	 * If the context is closing we don't need to check for the MMU cache
+	 * invalidation return code and update the VA free list as in this flow
+	 * we invalidate the MMU cache outside of this unmap function and the VA
+	 * free list will be freed anyway.
+	 */
+	if (!ctx_free) {
+		int tmp_rc;
+
+		tmp_rc = add_va_block(hdev, va_range, vaddr,
+					vaddr + phys_pg_pack->total_size - 1);
+		if (tmp_rc) {
+			dev_warn(hdev->dev,
+					"add va block failed for vaddr: 0x%llx\n",
+					vaddr);
+			if (!rc)
+				rc = tmp_rc;
+		}
+	}
+
+	atomic_dec(&phys_pg_pack->mapping_cnt);
+	kfree(hnode);
+
+	if (is_userptr) {
+		free_phys_pg_pack(hdev, phys_pg_pack);
+		dma_unmap_host_va(hdev, userptr);
+	}
+
+	return rc;
+
+mapping_cnt_err:
+	if (is_userptr)
+		free_phys_pg_pack(hdev, phys_pg_pack);
+vm_type_err:
+	mutex_lock(&ctx->mem_hash_lock);
+	hash_add(ctx->mem_hash, &hnode->node, vaddr);
+	mutex_unlock(&ctx->mem_hash_lock);
+
+	return rc;
+}
+
+static int map_block(struct hl_device *hdev, u64 address, u64 *handle, u32 *size)
+{
+	u32 block_id;
+	int rc;
+
+	*handle = 0;
+	if (size)
+		*size = 0;
+
+	rc = hdev->asic_funcs->get_hw_block_id(hdev, address, size, &block_id);
+	if (rc)
+		return rc;
+
+	*handle = block_id | HL_MMAP_TYPE_BLOCK;
+	*handle <<= PAGE_SHIFT;
+
+	return 0;
+}
+
+static void hw_block_vm_close(struct vm_area_struct *vma)
+{
+	struct hl_vm_hw_block_list_node *lnode =
+		(struct hl_vm_hw_block_list_node *) vma->vm_private_data;
+	struct hl_ctx *ctx = lnode->ctx;
+	long new_mmap_size;
+
+	new_mmap_size = lnode->mapped_size - (vma->vm_end - vma->vm_start);
+	if (new_mmap_size > 0) {
+		lnode->mapped_size = new_mmap_size;
+		return;
+	}
+
+	mutex_lock(&ctx->hw_block_list_lock);
+	list_del(&lnode->node);
+	mutex_unlock(&ctx->hw_block_list_lock);
+	hl_ctx_put(ctx);
+	kfree(lnode);
+	vma->vm_private_data = NULL;
+}
+
+static const struct vm_operations_struct hw_block_vm_ops = {
+	.close = hw_block_vm_close
+};
+
+/**
+ * hl_hw_block_mmap() - mmap a hw block to user.
+ * @hpriv: pointer to the private data of the fd
+ * @vma: pointer to vm_area_struct of the process
+ *
+ * Driver increments context reference for every HW block mapped in order
+ * to prevent user from closing FD without unmapping first
+ */
+int hl_hw_block_mmap(struct hl_fpriv *hpriv, struct vm_area_struct *vma)
+{
+	struct hl_vm_hw_block_list_node *lnode;
+	struct hl_device *hdev = hpriv->hdev;
+	struct hl_ctx *ctx = hpriv->ctx;
+	u32 block_id, block_size;
+	int rc;
+
+	/* We use the page offset to hold the block id and thus we need to clear
+	 * it before doing the mmap itself
+	 */
+	block_id = vma->vm_pgoff;
+	vma->vm_pgoff = 0;
+
+	/* Driver only allows mapping of a complete HW block */
+	block_size = vma->vm_end - vma->vm_start;
+
+	if (!access_ok((void __user *) (uintptr_t) vma->vm_start, block_size)) {
+		dev_err(hdev->dev,
+			"user pointer is invalid - 0x%lx\n",
+			vma->vm_start);
+
+		return -EINVAL;
+	}
+
+	lnode = kzalloc(sizeof(*lnode), GFP_KERNEL);
+	if (!lnode)
+		return -ENOMEM;
+
+	rc = hdev->asic_funcs->hw_block_mmap(hdev, vma, block_id, block_size);
+	if (rc) {
+		kfree(lnode);
+		return rc;
+	}
+
+	hl_ctx_get(ctx);
+
+	lnode->ctx = ctx;
+	lnode->vaddr = vma->vm_start;
+	lnode->block_size = block_size;
+	lnode->mapped_size = lnode->block_size;
+	lnode->id = block_id;
+
+	vma->vm_private_data = lnode;
+	vma->vm_ops = &hw_block_vm_ops;
+
+	mutex_lock(&ctx->hw_block_list_lock);
+	list_add_tail(&lnode->node, &ctx->hw_block_mem_list);
+	mutex_unlock(&ctx->hw_block_list_lock);
+
+	vma->vm_pgoff = block_id;
+
+	return 0;
+}
+
+static int set_dma_sg(struct scatterlist *sg, u64 bar_address, u64 chunk_size,
+			struct device *dev, enum dma_data_direction dir)
+{
+	dma_addr_t addr;
+	int rc;
+
+	addr = dma_map_resource(dev, bar_address, chunk_size, dir,
+				DMA_ATTR_SKIP_CPU_SYNC);
+	rc = dma_mapping_error(dev, addr);
+	if (rc)
+		return rc;
+
+	sg_set_page(sg, NULL, chunk_size, 0);
+	sg_dma_address(sg) = addr;
+	sg_dma_len(sg) = chunk_size;
+
+	return 0;
+}
+
+static struct sg_table *alloc_sgt_from_device_pages(struct hl_device *hdev, u64 *pages, u64 npages,
+						u64 page_size, u64 exported_size, u64 offset,
+						struct device *dev, enum dma_data_direction dir)
+{
+	u64 dma_max_seg_size, curr_page, size, chunk_size, left_size_to_export, left_size_in_page,
+		left_size_in_dma_seg, device_address, bar_address, start_page;
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct scatterlist *sg;
+	unsigned int nents, i;
+	struct sg_table *sgt;
+	bool next_sg_entry;
+	int rc;
+
+	/* Align max segment size to PAGE_SIZE to fit the minimal IOMMU mapping granularity */
+	dma_max_seg_size = ALIGN_DOWN(dma_get_max_seg_size(dev), PAGE_SIZE);
+	if (dma_max_seg_size < PAGE_SIZE) {
+		dev_err_ratelimited(hdev->dev,
+				"dma_max_seg_size %llu can't be smaller than PAGE_SIZE\n",
+				dma_max_seg_size);
+		return ERR_PTR(-EINVAL);
+	}
+
+	sgt = kzalloc(sizeof(*sgt), GFP_KERNEL);
+	if (!sgt)
+		return ERR_PTR(-ENOMEM);
+
+	/* Use the offset to move to the actual first page that is exported */
+	for (start_page = 0 ; start_page < npages ; ++start_page) {
+		if (offset < page_size)
+			break;
+
+		/* The offset value was validated so there can't be an underflow */
+		offset -= page_size;
+	}
+
+	/* Calculate the required number of entries for the SG table */
+	curr_page = start_page;
+	nents = 1;
+	left_size_to_export = exported_size;
+	left_size_in_page = page_size - offset;
+	left_size_in_dma_seg = dma_max_seg_size;
+	next_sg_entry = false;
+
+	while (true) {
+		size = min3(left_size_to_export, left_size_in_page, left_size_in_dma_seg);
+		left_size_to_export -= size;
+		left_size_in_page -= size;
+		left_size_in_dma_seg -= size;
+
+		if (!left_size_to_export)
+			break;
+
+		if (!left_size_in_page) {
+			/* left_size_to_export is not zero so there must be another page */
+			if (pages[curr_page] + page_size != pages[curr_page + 1])
+				next_sg_entry = true;
+
+			++curr_page;
+			left_size_in_page = page_size;
+		}
+
+		if (!left_size_in_dma_seg) {
+			next_sg_entry = true;
+			left_size_in_dma_seg = dma_max_seg_size;
+		}
+
+		if (next_sg_entry) {
+			++nents;
+			next_sg_entry = false;
+		}
+	}
+
+	rc = sg_alloc_table(sgt, nents, GFP_KERNEL | __GFP_ZERO);
+	if (rc)
+		goto err_free_sgt;
+
+	/* Prepare the SG table entries */
+	curr_page = start_page;
+	device_address = pages[curr_page] + offset;
+	left_size_to_export = exported_size;
+	left_size_in_page = page_size - offset;
+	left_size_in_dma_seg = dma_max_seg_size;
+	next_sg_entry = false;
+
+	for_each_sgtable_dma_sg(sgt, sg, i) {
+		bar_address = hdev->dram_pci_bar_start + (device_address - prop->dram_base_address);
+		chunk_size = 0;
+
+		for ( ; curr_page < npages ; ++curr_page) {
+			size = min3(left_size_to_export, left_size_in_page, left_size_in_dma_seg);
+			chunk_size += size;
+			left_size_to_export -= size;
+			left_size_in_page -= size;
+			left_size_in_dma_seg -= size;
+
+			if (!left_size_to_export)
+				break;
+
+			if (!left_size_in_page) {
+				/* left_size_to_export is not zero so there must be another page */
+				if (pages[curr_page] + page_size != pages[curr_page + 1]) {
+					device_address = pages[curr_page + 1];
+					next_sg_entry = true;
+				}
+
+				left_size_in_page = page_size;
+			}
+
+			if (!left_size_in_dma_seg) {
+				/*
+				 * Skip setting a new device address if already moving to a page
+				 * which is not contiguous with the current page.
+				 */
+				if (!next_sg_entry) {
+					device_address += chunk_size;
+					next_sg_entry = true;
+				}
+
+				left_size_in_dma_seg = dma_max_seg_size;
+			}
+
+			if (next_sg_entry) {
+				next_sg_entry = false;
+				break;
+			}
+		}
+
+		rc = set_dma_sg(sg, bar_address, chunk_size, dev, dir);
+		if (rc)
+			goto err_unmap;
+	}
+
+	/* There should be nothing left to export exactly after looping over all SG elements */
+	if (left_size_to_export) {
+		dev_err(hdev->dev,
+			"left size to export %#llx after initializing %u SG elements\n",
+			left_size_to_export, sgt->nents);
+		rc = -ENOMEM;
+		goto err_unmap;
+	}
+
+	/*
+	 * Because we are not going to include a CPU list, we want to have some chance that other
+	 * users will detect this when going over SG table, by setting the orig_nents to 0 and using
+	 * only nents (length of DMA list).
+	 */
+	sgt->orig_nents = 0;
+
+	dev_dbg(hdev->dev, "prepared SG table with %u entries for importer %s\n",
+		nents, dev_name(dev));
+	for_each_sgtable_dma_sg(sgt, sg, i)
+		dev_dbg(hdev->dev,
+			"SG entry %d: address %#llx, length %#x\n",
+			i, sg_dma_address(sg), sg_dma_len(sg));
+
+	return sgt;
+
+err_unmap:
+	for_each_sgtable_dma_sg(sgt, sg, i) {
+		if (!sg_dma_len(sg))
+			continue;
+
+		dma_unmap_resource(dev, sg_dma_address(sg), sg_dma_len(sg), dir,
+					DMA_ATTR_SKIP_CPU_SYNC);
+	}
+
+	sg_free_table(sgt);
+
+err_free_sgt:
+	kfree(sgt);
+	return ERR_PTR(rc);
+}
+
+static int hl_dmabuf_attach(struct dma_buf *dmabuf,
+				struct dma_buf_attachment *attachment)
+{
+	struct hl_dmabuf_priv *hl_dmabuf;
+	struct hl_device *hdev;
+	int rc;
+
+	hl_dmabuf = dmabuf->priv;
+	hdev = hl_dmabuf->ctx->hdev;
+
+	rc = pci_p2pdma_distance(hdev->pdev, attachment->dev, true);
+
+	if (rc < 0)
+		attachment->peer2peer = false;
+	return 0;
+}
+
+static struct sg_table *hl_map_dmabuf(struct dma_buf_attachment *attachment,
+					enum dma_data_direction dir)
+{
+	u64 *pages, npages, page_size, exported_size, offset;
+	struct dma_buf *dma_buf = attachment->dmabuf;
+	struct hl_vm_phys_pg_pack *phys_pg_pack;
+	struct hl_dmabuf_priv *hl_dmabuf;
+	struct hl_device *hdev;
+	struct sg_table *sgt;
+
+	hl_dmabuf = dma_buf->priv;
+	hdev = hl_dmabuf->ctx->hdev;
+
+	if (!attachment->peer2peer) {
+		dev_dbg(hdev->dev, "Failed to map dmabuf because p2p is disabled\n");
+		return ERR_PTR(-EPERM);
+	}
+
+	exported_size = hl_dmabuf->dmabuf->size;
+	offset = hl_dmabuf->offset;
+	phys_pg_pack = hl_dmabuf->phys_pg_pack;
+
+	if (phys_pg_pack) {
+		pages = phys_pg_pack->pages;
+		npages = phys_pg_pack->npages;
+		page_size = phys_pg_pack->page_size;
+	} else {
+		pages = &hl_dmabuf->device_phys_addr;
+		npages = 1;
+		page_size = hl_dmabuf->dmabuf->size;
+	}
+
+	sgt = alloc_sgt_from_device_pages(hdev, pages, npages, page_size, exported_size, offset,
+						attachment->dev, dir);
+	if (IS_ERR(sgt))
+		dev_err(hdev->dev, "failed (%ld) to initialize sgt for dmabuf\n", PTR_ERR(sgt));
+
+	return sgt;
+}
+
+static void hl_unmap_dmabuf(struct dma_buf_attachment *attachment,
+				  struct sg_table *sgt,
+				  enum dma_data_direction dir)
+{
+	struct scatterlist *sg;
+	int i;
+
+	/* The memory behind the dma-buf has *always* resided on the device itself, i.e. it lives
+	 * only in the 'device' domain (after all, it maps a PCI bar address which points to the
+	 * device memory).
+	 *
+	 * Therefore, it was never in the 'CPU' domain and hence, there is no need to perform
+	 * a sync of the memory to the CPU's cache, as it never resided inside that cache.
+	 */
+	for_each_sgtable_dma_sg(sgt, sg, i)
+		dma_unmap_resource(attachment->dev, sg_dma_address(sg),
+					sg_dma_len(sg), dir,
+					DMA_ATTR_SKIP_CPU_SYNC);
+
+	/* Need to restore orig_nents because sg_free_table use that field */
+	sgt->orig_nents = sgt->nents;
+	sg_free_table(sgt);
+	kfree(sgt);
+}
+
+static struct hl_vm_hash_node *memhash_node_export_get(struct hl_ctx *ctx, u64 addr)
+{
+	struct hl_device *hdev = ctx->hdev;
+	struct hl_vm_hash_node *hnode;
+
+	/* get the memory handle */
+	mutex_lock(&ctx->mem_hash_lock);
+	hnode = get_vm_hash_node_locked(ctx, addr);
+	if (!hnode) {
+		mutex_unlock(&ctx->mem_hash_lock);
+		dev_dbg(hdev->dev, "map address %#llx not found\n", addr);
+		return ERR_PTR(-EINVAL);
+	}
+
+	if (upper_32_bits(hnode->handle)) {
+		mutex_unlock(&ctx->mem_hash_lock);
+		dev_dbg(hdev->dev, "invalid handle %#llx for map address %#llx\n",
+				hnode->handle, addr);
+		return ERR_PTR(-EINVAL);
+	}
+
+	/*
+	 * node found, increase export count so this memory cannot be unmapped
+	 * and the hash node cannot be deleted.
+	 */
+	hnode->export_cnt++;
+	mutex_unlock(&ctx->mem_hash_lock);
+
+	return hnode;
+}
+
+static void memhash_node_export_put(struct hl_ctx *ctx, struct hl_vm_hash_node *hnode)
+{
+	mutex_lock(&ctx->mem_hash_lock);
+	hnode->export_cnt--;
+	mutex_unlock(&ctx->mem_hash_lock);
+}
+
+static void hl_release_dmabuf(struct dma_buf *dmabuf)
+{
+	struct hl_dmabuf_priv *hl_dmabuf = dmabuf->priv;
+	struct hl_ctx *ctx;
+
+	ctx = hl_dmabuf->ctx;
+
+	if (hl_dmabuf->memhash_hnode)
+		memhash_node_export_put(ctx, hl_dmabuf->memhash_hnode);
+
+	atomic_dec(&ctx->hdev->dmabuf_export_cnt);
+	hl_ctx_put(ctx);
+
+	/*
+	 * Paired with get_file() in export_dmabuf().
+	 * 'ctx' can be still used here to get the file pointer, even after hl_ctx_put() was called,
+	 * because releasing the compute device file involves another reference decrement, and it
+	 * would be possible only after calling fput().
+	 */
+	fput(ctx->hpriv->file_priv->filp);
+
+	kfree(hl_dmabuf);
+}
+
+static const struct dma_buf_ops habanalabs_dmabuf_ops = {
+	.attach = hl_dmabuf_attach,
+	.map_dma_buf = hl_map_dmabuf,
+	.unmap_dma_buf = hl_unmap_dmabuf,
+	.release = hl_release_dmabuf,
+};
+
+static int export_dmabuf(struct hl_ctx *ctx,
+				struct hl_dmabuf_priv *hl_dmabuf,
+				u64 total_size, int flags, int *dmabuf_fd)
+{
+	DEFINE_DMA_BUF_EXPORT_INFO(exp_info);
+	struct hl_device *hdev = ctx->hdev;
+	CLASS(get_unused_fd, fd)(flags);
+
+	if (fd < 0) {
+		dev_err(hdev->dev, "failed to get a file descriptor for a dma-buf, %d\n", fd);
+		return fd;
+	}
+
+	exp_info.ops = &habanalabs_dmabuf_ops;
+	exp_info.size = total_size;
+	exp_info.flags = flags;
+	exp_info.priv = hl_dmabuf;
+
+	hl_dmabuf->dmabuf = dma_buf_export(&exp_info);
+	if (IS_ERR(hl_dmabuf->dmabuf)) {
+		dev_err(hdev->dev, "failed to export dma-buf\n");
+		return PTR_ERR(hl_dmabuf->dmabuf);
+	}
+
+	hl_dmabuf->ctx = ctx;
+	hl_ctx_get(hl_dmabuf->ctx);
+	atomic_inc(&ctx->hdev->dmabuf_export_cnt);
+
+	/* Get compute device file to enforce release order, such that all exported dma-buf will be
+	 * released first and only then the compute device.
+	 * Paired with fput() in hl_release_dmabuf().
+	 */
+	get_file(ctx->hpriv->file_priv->filp);
+
+	*dmabuf_fd = fd;
+	fd_install(take_fd(fd), hl_dmabuf->dmabuf->file);
+
+	return 0;
+}
+
+static int validate_export_params_common(struct hl_device *hdev, u64 addr, u64 size, u64 offset)
+{
+	if (!PAGE_ALIGNED(addr)) {
+		dev_dbg(hdev->dev,
+			"exported device memory address 0x%llx should be aligned to PAGE_SIZE 0x%lx\n",
+			addr, PAGE_SIZE);
+		return -EINVAL;
+	}
+
+	if (!size || !PAGE_ALIGNED(size)) {
+		dev_dbg(hdev->dev,
+			"exported device memory size %llu should be a multiple of PAGE_SIZE %lu\n",
+			size, PAGE_SIZE);
+		return -EINVAL;
+	}
+
+	if (!PAGE_ALIGNED(offset)) {
+		dev_dbg(hdev->dev,
+			"exported device memory offset %llu should be a multiple of PAGE_SIZE %lu\n",
+			offset, PAGE_SIZE);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int validate_export_params_no_mmu(struct hl_device *hdev, u64 device_addr, u64 size)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	u64 bar_address;
+	int rc;
+
+	rc = validate_export_params_common(hdev, device_addr, size, 0);
+	if (rc)
+		return rc;
+
+	if (device_addr < prop->dram_user_base_address ||
+			(device_addr + size) > prop->dram_end_address ||
+			(device_addr + size) < device_addr) {
+		dev_dbg(hdev->dev,
+			"DRAM memory range 0x%llx (+0x%llx) is outside of DRAM boundaries\n",
+			device_addr, size);
+		return -EINVAL;
+	}
+
+	bar_address = hdev->dram_pci_bar_start + (device_addr - prop->dram_base_address);
+
+	if ((bar_address + size) > (hdev->dram_pci_bar_start + prop->dram_pci_bar_size) ||
+			(bar_address + size) < bar_address) {
+		dev_dbg(hdev->dev,
+			"DRAM memory range 0x%llx (+0x%llx) is outside of PCI BAR boundaries\n",
+			device_addr, size);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int validate_export_params(struct hl_device *hdev, u64 device_addr, u64 size, u64 offset,
+					struct hl_vm_phys_pg_pack *phys_pg_pack)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	u64 bar_address;
+	int i, rc;
+
+	rc = validate_export_params_common(hdev, device_addr, size, offset);
+	if (rc)
+		return rc;
+
+	if ((offset + size) > phys_pg_pack->total_size) {
+		dev_dbg(hdev->dev, "offset %#llx and size %#llx exceed total map size %#llx\n",
+			offset, size, phys_pg_pack->total_size);
+		return -EINVAL;
+	}
+
+	for (i = 0 ; i < phys_pg_pack->npages ; i++) {
+		bar_address = hdev->dram_pci_bar_start +
+				(phys_pg_pack->pages[i] - prop->dram_base_address);
+
+		if ((bar_address + phys_pg_pack->page_size) >
+				(hdev->dram_pci_bar_start + prop->dram_pci_bar_size) ||
+				(bar_address + phys_pg_pack->page_size) < bar_address) {
+			dev_dbg(hdev->dev,
+				"DRAM memory range 0x%llx (+0x%x) is outside of PCI BAR boundaries\n",
+				phys_pg_pack->pages[i], phys_pg_pack->page_size);
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
+static struct hl_vm_phys_pg_pack *get_phys_pg_pack_from_hash_node(struct hl_device *hdev,
+							struct hl_vm_hash_node *hnode)
+{
+	struct hl_vm_phys_pg_pack *phys_pg_pack;
+	struct hl_vm *vm = &hdev->vm;
+
+	spin_lock(&vm->idr_lock);
+	phys_pg_pack = idr_find(&vm->phys_pg_pack_handles, (u32) hnode->handle);
+	if (!phys_pg_pack) {
+		spin_unlock(&vm->idr_lock);
+		dev_dbg(hdev->dev, "no match for handle 0x%x\n", (u32) hnode->handle);
+		return ERR_PTR(-EINVAL);
+	}
+
+	spin_unlock(&vm->idr_lock);
+
+	if (phys_pg_pack->vm_type != VM_TYPE_PHYS_PACK) {
+		dev_dbg(hdev->dev, "handle 0x%llx does not represent DRAM memory\n", hnode->handle);
+		return ERR_PTR(-EINVAL);
+	}
+
+	return phys_pg_pack;
+}
+
+/**
+ * export_dmabuf_from_addr() - export a dma-buf object for the given memory
+ *                             address and size.
+ * @ctx: pointer to the context structure.
+ * @addr: device address.
+ * @size: size of device memory to export.
+ * @offset: the offset into the buffer from which to start exporting
+ * @flags: DMA-BUF file/FD flags.
+ * @dmabuf_fd: pointer to result FD that represents the dma-buf object.
+ *
+ * Create and export a dma-buf object for an existing memory allocation inside
+ * the device memory, and return a FD which is associated with the dma-buf
+ * object.
+ *
+ * Return: 0 on success, non-zero for failure.
+ */
+static int export_dmabuf_from_addr(struct hl_ctx *ctx, u64 addr, u64 size, u64 offset,
+					int flags, int *dmabuf_fd)
+{
+	struct hl_vm_phys_pg_pack *phys_pg_pack = NULL;
+	struct hl_vm_hash_node *hnode = NULL;
+	struct asic_fixed_properties *prop;
+	struct hl_dmabuf_priv *hl_dmabuf;
+	struct hl_device *hdev;
+	int rc;
+
+	hdev = ctx->hdev;
+	prop = &hdev->asic_prop;
+
+	/* offset must be 0 in devices without virtual memory support */
+	if (!prop->dram_supports_virtual_memory && offset) {
+		dev_dbg(hdev->dev, "offset is not allowed in device without virtual memory\n");
+		return -EINVAL;
+	}
+
+	hl_dmabuf = kzalloc(sizeof(*hl_dmabuf), GFP_KERNEL);
+	if (!hl_dmabuf)
+		return -ENOMEM;
+
+	if (prop->dram_supports_virtual_memory) {
+		hnode = memhash_node_export_get(ctx, addr);
+		if (IS_ERR(hnode)) {
+			rc = PTR_ERR(hnode);
+			goto err_free_dmabuf_wrapper;
+		}
+		phys_pg_pack = get_phys_pg_pack_from_hash_node(hdev, hnode);
+		if (IS_ERR(phys_pg_pack)) {
+			rc = PTR_ERR(phys_pg_pack);
+			goto dec_memhash_export_cnt;
+		}
+		rc = validate_export_params(hdev, addr, size, offset, phys_pg_pack);
+		if (rc)
+			goto dec_memhash_export_cnt;
+
+		hl_dmabuf->phys_pg_pack = phys_pg_pack;
+		hl_dmabuf->memhash_hnode = hnode;
+		hl_dmabuf->offset = offset;
+	} else {
+		rc = validate_export_params_no_mmu(hdev, addr, size);
+		if (rc)
+			goto err_free_dmabuf_wrapper;
+
+		hl_dmabuf->device_phys_addr = addr;
+	}
+
+	rc = export_dmabuf(ctx, hl_dmabuf, size, flags, dmabuf_fd);
+	if (rc)
+		goto dec_memhash_export_cnt;
+
+	return 0;
+
+dec_memhash_export_cnt:
+	if (prop->dram_supports_virtual_memory)
+		memhash_node_export_put(ctx, hnode);
+err_free_dmabuf_wrapper:
+	kfree(hl_dmabuf);
+	return rc;
+}
+
+static void ts_buff_release(struct hl_mmap_mem_buf *buf)
+{
+	struct hl_ts_buff *ts_buff = buf->private;
+
+	vfree(ts_buff->kernel_buff_address);
+	vfree(ts_buff->user_buff_address);
+	kfree(ts_buff);
+}
+
+static int hl_ts_mmap(struct hl_mmap_mem_buf *buf, struct vm_area_struct *vma, void *args)
+{
+	struct hl_ts_buff *ts_buff = buf->private;
+
+	vm_flags_set(vma, VM_DONTEXPAND | VM_DONTDUMP | VM_DONTCOPY | VM_NORESERVE);
+	return remap_vmalloc_range(vma, ts_buff->user_buff_address, 0);
+}
+
+static int hl_ts_alloc_buf(struct hl_mmap_mem_buf *buf, gfp_t gfp, void *args)
+{
+	struct hl_ts_buff *ts_buff = NULL;
+	u32 num_elements;
+	size_t size;
+	void *p;
+
+	num_elements = *(u32 *)args;
+
+	ts_buff = kzalloc(sizeof(*ts_buff), gfp);
+	if (!ts_buff)
+		return -ENOMEM;
+
+	/* Allocate the user buffer */
+	size = num_elements * sizeof(u64);
+	p = vmalloc_user(size);
+	if (!p)
+		goto free_mem;
+
+	ts_buff->user_buff_address = p;
+	buf->mappable_size = size;
+
+	/* Allocate the internal kernel buffer */
+	size = num_elements * sizeof(struct hl_user_pending_interrupt);
+	p = vzalloc(size);
+	if (!p)
+		goto free_user_buff;
+
+	ts_buff->kernel_buff_address = p;
+	ts_buff->kernel_buff_size = size;
+
+	buf->private = ts_buff;
+
+	return 0;
+
+free_user_buff:
+	vfree(ts_buff->user_buff_address);
+free_mem:
+	kfree(ts_buff);
+	return -ENOMEM;
+}
+
+static struct hl_mmap_mem_buf_behavior hl_ts_behavior = {
+	.topic = "TS",
+	.mem_id = HL_MMAP_TYPE_TS_BUFF,
+	.mmap = hl_ts_mmap,
+	.alloc = hl_ts_alloc_buf,
+	.release = ts_buff_release,
+};
+
+/**
+ * allocate_timestamps_buffers() - allocate timestamps buffers
+ * This function will allocate ts buffer that will later on be mapped to the user
+ * in order to be able to read the timestamp.
+ * in addition it'll allocate an extra buffer for registration management.
+ * since we cannot fail during registration for out-of-memory situation, so
+ * we'll prepare a pool which will be used as user interrupt nodes and instead
+ * of dynamically allocating nodes while registration we'll pick the node from
+ * this pool. in addition it'll add node to the mapping hash which will be used
+ * to map user ts buffer to the internal kernel ts buffer.
+ * @hpriv: pointer to the private data of the fd
+ * @args: ioctl input
+ * @handle: user timestamp buffer handle as an output
+ */
+static int allocate_timestamps_buffers(struct hl_fpriv *hpriv, struct hl_mem_in *args, u64 *handle)
+{
+	struct hl_mem_mgr *mmg = &hpriv->mem_mgr;
+	struct hl_mmap_mem_buf *buf;
+
+	if (args->num_of_elements > TS_MAX_ELEMENTS_NUM) {
+		dev_err(mmg->dev, "Num of elements exceeds Max allowed number (0x%x > 0x%x)\n",
+				args->num_of_elements, TS_MAX_ELEMENTS_NUM);
+		return -EINVAL;
+	}
+
+	buf = hl_mmap_mem_buf_alloc(mmg, &hl_ts_behavior, GFP_KERNEL, &args->num_of_elements);
+	if (!buf)
+		return -ENOMEM;
+
+	*handle = buf->handle;
+
+	return 0;
+}
+
+int hl_mem_ioctl(struct drm_device *ddev, void *data, struct drm_file *file_priv)
+{
+	struct hl_fpriv *hpriv = file_priv->driver_priv;
+	enum hl_device_status status;
+	union hl_mem_args *args = data;
+	struct hl_device *hdev = hpriv->hdev;
+	struct hl_ctx *ctx = hpriv->ctx;
+	u64 block_handle, device_addr = 0;
+	u32 handle = 0, block_size;
+	int rc, dmabuf_fd = -EBADF;
+
+	if (!hl_device_operational(hdev, &status)) {
+		dev_dbg_ratelimited(hdev->dev,
+			"Device is %s. Can't execute MEMORY IOCTL\n",
+			hdev->status[status]);
+		return -EBUSY;
+	}
+
+	switch (args->in.op) {
+	case HL_MEM_OP_ALLOC:
+		if (args->in.alloc.mem_size == 0) {
+			dev_err(hdev->dev,
+				"alloc size must be larger than 0\n");
+			rc = -EINVAL;
+			goto out;
+		}
+
+		/* If DRAM does not support virtual memory the driver won't
+		 * handle the allocation/freeing of that memory. However, for
+		 * system administration/monitoring purposes, the driver will
+		 * keep track of the amount of DRAM memory that is allocated
+		 * and freed by the user. Because this code totally relies on
+		 * the user's input, the driver can't ensure the validity
+		 * of this accounting.
+		 */
+		if (!hdev->asic_prop.dram_supports_virtual_memory) {
+			atomic64_add(args->in.alloc.mem_size,
+					&ctx->dram_phys_mem);
+			atomic64_add(args->in.alloc.mem_size,
+					&hdev->dram_used_mem);
+
+			dev_dbg(hdev->dev, "DRAM alloc is not supported\n");
+			rc = 0;
+
+			memset(args, 0, sizeof(*args));
+			args->out.handle = 0;
+			goto out;
+		}
+
+		rc = alloc_device_memory(ctx, &args->in, &handle);
+
+		memset(args, 0, sizeof(*args));
+		args->out.handle = (__u64) handle;
+		break;
+
+	case HL_MEM_OP_FREE:
+		/* If DRAM does not support virtual memory the driver won't
+		 * handle the allocation/freeing of that memory. However, for
+		 * system administration/monitoring purposes, the driver will
+		 * keep track of the amount of DRAM memory that is allocated
+		 * and freed by the user. Because this code totally relies on
+		 * the user's input, the driver can't ensure the validity
+		 * of this accounting.
+		 */
+		if (!hdev->asic_prop.dram_supports_virtual_memory) {
+			atomic64_sub(args->in.alloc.mem_size,
+					&ctx->dram_phys_mem);
+			atomic64_sub(args->in.alloc.mem_size,
+					&hdev->dram_used_mem);
+
+			dev_dbg(hdev->dev, "DRAM alloc is not supported\n");
+			rc = 0;
+
+			goto out;
+		}
+
+		rc = free_device_memory(ctx, &args->in);
+		break;
+
+	case HL_MEM_OP_MAP:
+		rc = map_device_va(ctx, &args->in, &device_addr);
+
+		memset(args, 0, sizeof(*args));
+		args->out.device_virt_addr = device_addr;
+		break;
+
+	case HL_MEM_OP_UNMAP:
+		rc = unmap_device_va(ctx, &args->in, false);
+		break;
+
+	case HL_MEM_OP_MAP_BLOCK:
+		rc = map_block(hdev, args->in.map_block.block_addr,
+				&block_handle, &block_size);
+		args->out.block_handle = block_handle;
+		args->out.block_size = block_size;
+		break;
+
+	case HL_MEM_OP_EXPORT_DMABUF_FD:
+		rc = export_dmabuf_from_addr(ctx,
+				args->in.export_dmabuf_fd.addr,
+				args->in.export_dmabuf_fd.mem_size,
+				args->in.export_dmabuf_fd.offset,
+				args->in.flags,
+				&dmabuf_fd);
+		memset(args, 0, sizeof(*args));
+		args->out.fd = dmabuf_fd;
+		break;
+
+	case HL_MEM_OP_TS_ALLOC:
+		rc = allocate_timestamps_buffers(hpriv, &args->in, &args->out.handle);
+		break;
+	default:
+		dev_err(hdev->dev, "Unknown opcode for memory IOCTL\n");
+		rc = -EINVAL;
+		break;
+	}
+
+out:
+	return rc;
+}
+
+static int get_user_memory(struct hl_device *hdev, u64 addr, u64 size,
+				u32 npages, u64 start, u32 offset,
+				struct hl_userptr *userptr)
+{
+	int rc;
+
+	if (!access_ok((void __user *) (uintptr_t) addr, size)) {
+		dev_err(hdev->dev, "user pointer is invalid - 0x%llx\n", addr);
+		return -EFAULT;
+	}
+
+	userptr->pages = kvmalloc_array(npages, sizeof(struct page *), GFP_KERNEL);
+	if (!userptr->pages)
+		return -ENOMEM;
+
+	rc = pin_user_pages_fast(start, npages, FOLL_WRITE | FOLL_LONGTERM,
+				 userptr->pages);
+
+	if (rc != npages) {
+		dev_err(hdev->dev,
+			"Failed (%d) to pin host memory with user ptr 0x%llx, size 0x%llx, npages %d\n",
+			rc, addr, size, npages);
+		if (rc < 0)
+			goto destroy_pages;
+		npages = rc;
+		rc = -ENOMEM;
+		goto put_pages;
+	}
+	userptr->npages = npages;
+
+	rc = sg_alloc_table_from_pages(userptr->sgt,
+				       userptr->pages,
+				       npages, offset, size, GFP_KERNEL);
+	if (rc < 0) {
+		dev_err(hdev->dev, "failed to create SG table from pages\n");
+		goto put_pages;
+	}
+
+	return 0;
+
+put_pages:
+	unpin_user_pages(userptr->pages, npages);
+destroy_pages:
+	kvfree(userptr->pages);
+	return rc;
+}
+
+/**
+ * hl_pin_host_memory() - pins a chunk of host memory.
+ * @hdev: pointer to the habanalabs device structure.
+ * @addr: the host virtual address of the memory area.
+ * @size: the size of the memory area.
+ * @userptr: pointer to hl_userptr structure.
+ *
+ * This function does the following:
+ * - Pins the physical pages.
+ * - Create an SG list from those pages.
+ */
+int hl_pin_host_memory(struct hl_device *hdev, u64 addr, u64 size,
+					struct hl_userptr *userptr)
+{
+	u64 start, end;
+	u32 npages, offset;
+	int rc;
+
+	if (!size) {
+		dev_err(hdev->dev, "size to pin is invalid - %llu\n", size);
+		return -EINVAL;
+	}
+
+	/*
+	 * If the combination of the address and size requested for this memory
+	 * region causes an integer overflow, return error.
+	 */
+	if (((addr + size) < addr) ||
+			PAGE_ALIGN(addr + size) < (addr + size)) {
+		dev_err(hdev->dev,
+			"user pointer 0x%llx + %llu causes integer overflow\n",
+			addr, size);
+		return -EINVAL;
+	}
+
+	userptr->pid = current->pid;
+	userptr->sgt = kzalloc(sizeof(*userptr->sgt), GFP_KERNEL);
+	if (!userptr->sgt)
+		return -ENOMEM;
+
+	start = addr & PAGE_MASK;
+	offset = addr & ~PAGE_MASK;
+	end = PAGE_ALIGN(addr + size);
+	npages = (end - start) >> PAGE_SHIFT;
+
+	userptr->size = size;
+	userptr->addr = addr;
+	userptr->dma_mapped = false;
+	INIT_LIST_HEAD(&userptr->job_node);
+
+	rc = get_user_memory(hdev, addr, size, npages, start, offset,
+				userptr);
+	if (rc) {
+		dev_err(hdev->dev,
+			"failed to get user memory for address 0x%llx\n",
+			addr);
+		goto free_sgt;
+	}
+
+	hl_debugfs_add_userptr(hdev, userptr);
+
+	return 0;
+
+free_sgt:
+	kfree(userptr->sgt);
+	return rc;
+}
+
+/*
+ * hl_unpin_host_memory - unpins a chunk of host memory.
+ * @hdev: pointer to the habanalabs device structure
+ * @userptr: pointer to hl_userptr structure
+ *
+ * This function does the following:
+ * - Unpins the physical pages related to the host memory
+ * - Free the SG list
+ */
+void hl_unpin_host_memory(struct hl_device *hdev, struct hl_userptr *userptr)
+{
+	hl_debugfs_remove_userptr(hdev, userptr);
+
+	if (userptr->dma_mapped)
+		hl_dma_unmap_sgtable(hdev, userptr->sgt, userptr->dir);
+
+	unpin_user_pages_dirty_lock(userptr->pages, userptr->npages, true);
+	kvfree(userptr->pages);
+
+	list_del(&userptr->job_node);
+
+	sg_free_table(userptr->sgt);
+	kfree(userptr->sgt);
+}
+
+/**
+ * hl_userptr_delete_list() - clear userptr list.
+ * @hdev: pointer to the habanalabs device structure.
+ * @userptr_list: pointer to the list to clear.
+ *
+ * This function does the following:
+ * - Iterates over the list and unpins the host memory and frees the userptr
+ *   structure.
+ */
+void hl_userptr_delete_list(struct hl_device *hdev,
+				struct list_head *userptr_list)
+{
+	struct hl_userptr *userptr, *tmp;
+
+	list_for_each_entry_safe(userptr, tmp, userptr_list, job_node) {
+		hl_unpin_host_memory(hdev, userptr);
+		kfree(userptr);
+	}
+
+	INIT_LIST_HEAD(userptr_list);
+}
+
+/**
+ * hl_userptr_is_pinned() - returns whether the given userptr is pinned.
+ * @hdev: pointer to the habanalabs device structure.
+ * @addr: user address to check.
+ * @size: user block size to check.
+ * @userptr_list: pointer to the list to clear.
+ * @userptr: pointer to userptr to check.
+ *
+ * This function does the following:
+ * - Iterates over the list and checks if the given userptr is in it, means is
+ *   pinned. If so, returns true, otherwise returns false.
+ */
+bool hl_userptr_is_pinned(struct hl_device *hdev, u64 addr,
+				u32 size, struct list_head *userptr_list,
+				struct hl_userptr **userptr)
+{
+	list_for_each_entry((*userptr), userptr_list, job_node) {
+		if ((addr == (*userptr)->addr) && (size == (*userptr)->size))
+			return true;
+	}
+
+	return false;
+}
+
+/**
+ * va_range_init() - initialize virtual addresses range.
+ * @hdev: pointer to the habanalabs device structure.
+ * @va_ranges: pointer to va_ranges array.
+ * @range_type: virtual address range type.
+ * @start: range start address, inclusive.
+ * @end: range end address, inclusive.
+ * @page_size: page size for this va_range.
+ *
+ * This function does the following:
+ * - Initializes the virtual addresses list of the given range with the given
+ *   addresses.
+ */
+static int va_range_init(struct hl_device *hdev, struct hl_va_range **va_ranges,
+				enum hl_va_range_type range_type, u64 start,
+				u64 end, u32 page_size)
+{
+	struct hl_va_range *va_range = va_ranges[range_type];
+	int rc;
+
+	INIT_LIST_HEAD(&va_range->list);
+
+	/*
+	 * PAGE_SIZE alignment
+	 * it is the caller's responsibility to align the addresses if the
+	 * page size is not a power of 2
+	 */
+
+	if (is_power_of_2(page_size)) {
+		start = round_up(start, page_size);
+
+		/*
+		 * The end of the range is inclusive, hence we need to align it
+		 * to the end of the last full page in the range. For example if
+		 * end = 0x3ff5 with page size 0x1000, we need to align it to
+		 * 0x2fff. The remaining 0xff5 bytes do not form a full page.
+		 */
+		end = round_down(end + 1, page_size) - 1;
+	}
+
+	if (start >= end) {
+		dev_err(hdev->dev, "too small vm range for va list\n");
+		return -EFAULT;
+	}
+
+	rc = add_va_block(hdev, va_range, start, end);
+
+	if (rc) {
+		dev_err(hdev->dev, "Failed to init host va list\n");
+		return rc;
+	}
+
+	va_range->start_addr = start;
+	va_range->end_addr = end;
+	va_range->page_size = page_size;
+
+	return 0;
+}
+
+/**
+ * va_range_fini() - clear a virtual addresses range.
+ * @hdev: pointer to the habanalabs structure.
+ * @va_range: pointer to virtual addresses range.
+ *
+ * This function does the following:
+ * - Frees the virtual addresses block list and its lock.
+ */
+static void va_range_fini(struct hl_device *hdev, struct hl_va_range *va_range)
+{
+	mutex_lock(&va_range->lock);
+	clear_va_list_locked(hdev, &va_range->list);
+	mutex_unlock(&va_range->lock);
+
+	mutex_destroy(&va_range->lock);
+	kfree(va_range);
+}
+
+/**
+ * vm_ctx_init_with_ranges() - initialize virtual memory for context.
+ * @ctx: pointer to the habanalabs context structure.
+ * @host_range_start: host virtual addresses range start.
+ * @host_range_end: host virtual addresses range end.
+ * @host_page_size: host page size.
+ * @host_huge_range_start: host virtual addresses range start for memory
+ *                         allocated with huge pages.
+ * @host_huge_range_end: host virtual addresses range end for memory allocated
+ *                        with huge pages.
+ * @host_huge_page_size: host huge page size.
+ * @dram_range_start: dram virtual addresses range start.
+ * @dram_range_end: dram virtual addresses range end.
+ * @dram_page_size: dram page size.
+ *
+ * This function initializes the following:
+ * - MMU for context.
+ * - Virtual address to area descriptor hashtable.
+ * - Virtual block list of available virtual memory.
+ */
+static int vm_ctx_init_with_ranges(struct hl_ctx *ctx,
+					u64 host_range_start,
+					u64 host_range_end,
+					u32 host_page_size,
+					u64 host_huge_range_start,
+					u64 host_huge_range_end,
+					u32 host_huge_page_size,
+					u64 dram_range_start,
+					u64 dram_range_end,
+					u32 dram_page_size)
+{
+	struct hl_device *hdev = ctx->hdev;
+	int i, rc;
+
+	for (i = 0 ; i < HL_VA_RANGE_TYPE_MAX ; i++) {
+		ctx->va_range[i] =
+			kzalloc(sizeof(struct hl_va_range), GFP_KERNEL);
+		if (!ctx->va_range[i]) {
+			rc = -ENOMEM;
+			goto free_va_range;
+		}
+	}
+
+	rc = hl_mmu_ctx_init(ctx);
+	if (rc) {
+		dev_err(hdev->dev, "failed to init context %d\n", ctx->asid);
+		goto free_va_range;
+	}
+
+	mutex_init(&ctx->mem_hash_lock);
+	hash_init(ctx->mem_hash);
+
+	mutex_init(&ctx->va_range[HL_VA_RANGE_TYPE_HOST]->lock);
+
+	rc = va_range_init(hdev, ctx->va_range, HL_VA_RANGE_TYPE_HOST,
+			host_range_start, host_range_end, host_page_size);
+	if (rc) {
+		dev_err(hdev->dev, "failed to init host vm range\n");
+		goto mmu_ctx_fini;
+	}
+
+	if (hdev->pmmu_huge_range) {
+		mutex_init(&ctx->va_range[HL_VA_RANGE_TYPE_HOST_HUGE]->lock);
+
+		rc = va_range_init(hdev,
+			ctx->va_range, HL_VA_RANGE_TYPE_HOST_HUGE,
+			host_huge_range_start, host_huge_range_end,
+			host_huge_page_size);
+		if (rc) {
+			dev_err(hdev->dev,
+				"failed to init host huge vm range\n");
+			goto clear_host_va_range;
+		}
+	} else {
+		kfree(ctx->va_range[HL_VA_RANGE_TYPE_HOST_HUGE]);
+		ctx->va_range[HL_VA_RANGE_TYPE_HOST_HUGE] =
+				ctx->va_range[HL_VA_RANGE_TYPE_HOST];
+	}
+
+	mutex_init(&ctx->va_range[HL_VA_RANGE_TYPE_DRAM]->lock);
+
+	rc = va_range_init(hdev, ctx->va_range, HL_VA_RANGE_TYPE_DRAM,
+			dram_range_start, dram_range_end, dram_page_size);
+	if (rc) {
+		dev_err(hdev->dev, "failed to init dram vm range\n");
+		goto clear_host_huge_va_range;
+	}
+
+	hl_debugfs_add_ctx_mem_hash(hdev, ctx);
+
+	return 0;
+
+clear_host_huge_va_range:
+	mutex_destroy(&ctx->va_range[HL_VA_RANGE_TYPE_DRAM]->lock);
+
+	if (hdev->pmmu_huge_range) {
+		mutex_lock(&ctx->va_range[HL_VA_RANGE_TYPE_HOST_HUGE]->lock);
+		clear_va_list_locked(hdev,
+			&ctx->va_range[HL_VA_RANGE_TYPE_HOST_HUGE]->list);
+		mutex_unlock(&ctx->va_range[HL_VA_RANGE_TYPE_HOST_HUGE]->lock);
+	}
+clear_host_va_range:
+	if (hdev->pmmu_huge_range)
+		mutex_destroy(&ctx->va_range[HL_VA_RANGE_TYPE_HOST_HUGE]->lock);
+	mutex_lock(&ctx->va_range[HL_VA_RANGE_TYPE_HOST]->lock);
+	clear_va_list_locked(hdev, &ctx->va_range[HL_VA_RANGE_TYPE_HOST]->list);
+	mutex_unlock(&ctx->va_range[HL_VA_RANGE_TYPE_HOST]->lock);
+mmu_ctx_fini:
+	mutex_destroy(&ctx->va_range[HL_VA_RANGE_TYPE_HOST]->lock);
+	mutex_destroy(&ctx->mem_hash_lock);
+	hl_mmu_ctx_fini(ctx);
+free_va_range:
+	for (i = 0 ; i < HL_VA_RANGE_TYPE_MAX ; i++)
+		kfree(ctx->va_range[i]);
+
+	return rc;
+}
+
+int hl_vm_ctx_init(struct hl_ctx *ctx)
+{
+	struct asic_fixed_properties *prop = &ctx->hdev->asic_prop;
+	u64 host_range_start, host_range_end, host_huge_range_start,
+		host_huge_range_end, dram_range_start, dram_range_end;
+	u32 host_page_size, host_huge_page_size, dram_page_size;
+
+	atomic64_set(&ctx->dram_phys_mem, 0);
+
+	/*
+	 *   In case of DRAM mapping, the returned address is the physical
+	 *   address of the memory related to the given handle.
+	 */
+	if (ctx->hdev->mmu_disable)
+		return 0;
+
+	dram_range_start = prop->dmmu.start_addr;
+	dram_range_end = prop->dmmu.end_addr - 1;
+	dram_page_size = prop->dram_page_size ?
+				prop->dram_page_size : prop->dmmu.page_size;
+	host_range_start = prop->pmmu.start_addr;
+	host_range_end = prop->pmmu.end_addr - 1;
+	host_page_size = prop->pmmu.page_size;
+	host_huge_range_start = prop->pmmu_huge.start_addr;
+	host_huge_range_end = prop->pmmu_huge.end_addr - 1;
+	host_huge_page_size = prop->pmmu_huge.page_size;
+
+	return vm_ctx_init_with_ranges(ctx, host_range_start, host_range_end,
+			host_page_size, host_huge_range_start,
+			host_huge_range_end, host_huge_page_size,
+			dram_range_start, dram_range_end, dram_page_size);
+}
+
+/**
+ * hl_vm_ctx_fini() - virtual memory teardown of context.
+ * @ctx: pointer to the habanalabs context structure.
+ *
+ * This function perform teardown the following:
+ * - Virtual block list of available virtual memory.
+ * - Virtual address to area descriptor hashtable.
+ * - MMU for context.
+ *
+ * In addition this function does the following:
+ * - Unmaps the existing hashtable nodes if the hashtable is not empty. The
+ *   hashtable should be empty as no valid mappings should exist at this
+ *   point.
+ * - Frees any existing physical page list from the idr which relates to the
+ *   current context asid.
+ * - This function checks the virtual block list for correctness. At this point
+ *   the list should contain one element which describes the whole virtual
+ *   memory range of the context. Otherwise, a warning is printed.
+ */
+void hl_vm_ctx_fini(struct hl_ctx *ctx)
+{
+	struct hl_vm_phys_pg_pack *phys_pg_list, *tmp_phys_node;
+	struct hl_device *hdev = ctx->hdev;
+	struct hl_vm_hash_node *hnode;
+	struct hl_vm *vm = &hdev->vm;
+	struct hlist_node *tmp_node;
+	struct list_head free_list;
+	struct hl_mem_in args;
+	int i;
+
+	if (hdev->mmu_disable)
+		return;
+
+	hl_debugfs_remove_ctx_mem_hash(hdev, ctx);
+
+	/*
+	 * Clearly something went wrong on hard reset so no point in printing
+	 * another side effect error
+	 */
+	if (!hdev->reset_info.hard_reset_pending && !hash_empty(ctx->mem_hash))
+		dev_dbg(hdev->dev,
+			"user released device without removing its memory mappings\n");
+
+	hash_for_each_safe(ctx->mem_hash, i, tmp_node, hnode, node) {
+		dev_dbg(hdev->dev,
+			"hl_mem_hash_node of vaddr 0x%llx of asid %d is still alive\n",
+			hnode->vaddr, ctx->asid);
+		args.unmap.device_virt_addr = hnode->vaddr;
+		unmap_device_va(ctx, &args, true);
+	}
+
+	mutex_lock(&hdev->mmu_lock);
+
+	/* invalidate the cache once after the unmapping loop */
+	hl_mmu_invalidate_cache(hdev, true, MMU_OP_USERPTR);
+	hl_mmu_invalidate_cache(hdev, true, MMU_OP_PHYS_PACK);
+
+	mutex_unlock(&hdev->mmu_lock);
+
+	INIT_LIST_HEAD(&free_list);
+
+	spin_lock(&vm->idr_lock);
+	idr_for_each_entry(&vm->phys_pg_pack_handles, phys_pg_list, i)
+		if (phys_pg_list->asid == ctx->asid) {
+			dev_dbg(hdev->dev,
+				"page list 0x%px of asid %d is still alive\n",
+				phys_pg_list, ctx->asid);
+
+			atomic64_sub(phys_pg_list->total_size, &hdev->dram_used_mem);
+			idr_remove(&vm->phys_pg_pack_handles, i);
+			list_add(&phys_pg_list->node, &free_list);
+		}
+	spin_unlock(&vm->idr_lock);
+
+	list_for_each_entry_safe(phys_pg_list, tmp_phys_node, &free_list, node)
+		free_phys_pg_pack(hdev, phys_pg_list);
+
+	va_range_fini(hdev, ctx->va_range[HL_VA_RANGE_TYPE_DRAM]);
+	va_range_fini(hdev, ctx->va_range[HL_VA_RANGE_TYPE_HOST]);
+
+	if (hdev->pmmu_huge_range)
+		va_range_fini(hdev, ctx->va_range[HL_VA_RANGE_TYPE_HOST_HUGE]);
+
+	mutex_destroy(&ctx->mem_hash_lock);
+	hl_mmu_ctx_fini(ctx);
+
+	/* In this case we need to clear the global accounting of DRAM usage
+	 * because the user notifies us on allocations. If the user is no more,
+	 * all DRAM is available
+	 */
+	if (ctx->asid != HL_KERNEL_ASID_ID &&
+			!hdev->asic_prop.dram_supports_virtual_memory)
+		atomic64_set(&hdev->dram_used_mem, 0);
+}
+
+/**
+ * hl_vm_init() - initialize virtual memory module.
+ * @hdev: pointer to the habanalabs device structure.
+ *
+ * This function initializes the following:
+ * - MMU module.
+ * - DRAM physical pages pool of 2MB.
+ * - Idr for device memory allocation handles.
+ */
+int hl_vm_init(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct hl_vm *vm = &hdev->vm;
+	int rc;
+
+	if (is_power_of_2(prop->dram_page_size))
+		vm->dram_pg_pool =
+			gen_pool_create(__ffs(prop->dram_page_size), -1);
+	else
+		vm->dram_pg_pool =
+			gen_pool_create(__ffs(DRAM_POOL_PAGE_SIZE), -1);
+
+	if (!vm->dram_pg_pool) {
+		dev_err(hdev->dev, "Failed to create dram page pool\n");
+		return -ENOMEM;
+	}
+
+	kref_init(&vm->dram_pg_pool_refcount);
+
+	rc = gen_pool_add(vm->dram_pg_pool, prop->dram_user_base_address,
+			prop->dram_end_address - prop->dram_user_base_address,
+			-1);
+
+	if (rc) {
+		dev_err(hdev->dev,
+			"Failed to add memory to dram page pool %d\n", rc);
+		goto pool_add_err;
+	}
+
+	spin_lock_init(&vm->idr_lock);
+	idr_init(&vm->phys_pg_pack_handles);
+
+	atomic64_set(&hdev->dram_used_mem, 0);
+
+	vm->init_done = true;
+
+	return 0;
+
+pool_add_err:
+	gen_pool_destroy(vm->dram_pg_pool);
+
+	return rc;
+}
+
+/**
+ * hl_vm_fini() - virtual memory module teardown.
+ * @hdev: pointer to the habanalabs device structure.
+ *
+ * This function perform teardown to the following:
+ * - Idr for device memory allocation handles.
+ * - DRAM physical pages pool of 2MB.
+ * - MMU module.
+ */
+void hl_vm_fini(struct hl_device *hdev)
+{
+	struct hl_vm *vm = &hdev->vm;
+
+	if (!vm->init_done)
+		return;
+
+	/*
+	 * At this point all the contexts should be freed and hence no DRAM
+	 * memory should be in use. Hence the DRAM pool should be freed here.
+	 */
+	if (kref_put(&vm->dram_pg_pool_refcount, dram_pg_pool_do_release) != 1)
+		dev_warn(hdev->dev, "dram_pg_pool was not destroyed on %s\n",
+				__func__);
+
+	vm->init_done = false;
+}
+
+/**
+ * hl_hw_block_mem_init() - HW block memory initialization.
+ * @ctx: pointer to the habanalabs context structure.
+ *
+ * This function initializes the HW block virtual mapped addresses list and
+ * it's lock.
+ */
+void hl_hw_block_mem_init(struct hl_ctx *ctx)
+{
+	mutex_init(&ctx->hw_block_list_lock);
+	INIT_LIST_HEAD(&ctx->hw_block_mem_list);
+}
+
+/**
+ * hl_hw_block_mem_fini() - HW block memory teardown.
+ * @ctx: pointer to the habanalabs context structure.
+ *
+ * This function clears the HW block virtual mapped addresses list and destroys
+ * it's lock.
+ */
+void hl_hw_block_mem_fini(struct hl_ctx *ctx)
+{
+	struct hl_vm_hw_block_list_node *lnode, *tmp;
+
+	if (!list_empty(&ctx->hw_block_mem_list))
+		dev_crit(ctx->hdev->dev, "HW block mem list isn't empty\n");
+
+	list_for_each_entry_safe(lnode, tmp, &ctx->hw_block_mem_list, node) {
+		list_del(&lnode->node);
+		kfree(lnode);
+	}
+
+	mutex_destroy(&ctx->hw_block_list_lock);
+}
diff --git a/drivers/accel/habanalabs/common/memory_mgr.c b/drivers/accel/habanalabs/common/memory_mgr.c
new file mode 100644
index 000000000000..4401beb99e42
--- /dev/null
+++ b/drivers/accel/habanalabs/common/memory_mgr.c
@@ -0,0 +1,387 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Copyright 2022 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ */
+
+#include "habanalabs.h"
+
+/**
+ * hl_mmap_mem_buf_get - increase the buffer refcount and return a pointer to
+ *                        the buffer descriptor.
+ *
+ * @mmg: parent unified memory manager
+ * @handle: requested buffer handle
+ *
+ * Find the buffer in the store and return a pointer to its descriptor.
+ * Increase buffer refcount. If not found - return NULL.
+ */
+struct hl_mmap_mem_buf *hl_mmap_mem_buf_get(struct hl_mem_mgr *mmg, u64 handle)
+{
+	struct hl_mmap_mem_buf *buf;
+
+	spin_lock(&mmg->lock);
+	buf = idr_find(&mmg->handles, lower_32_bits(handle >> PAGE_SHIFT));
+	if (!buf) {
+		spin_unlock(&mmg->lock);
+		dev_dbg(mmg->dev, "Buff get failed, no match to handle %#llx\n", handle);
+		return NULL;
+	}
+	kref_get(&buf->refcount);
+	spin_unlock(&mmg->lock);
+	return buf;
+}
+
+/**
+ * hl_mmap_mem_buf_destroy - destroy the unused buffer
+ *
+ * @buf: memory manager buffer descriptor
+ *
+ * Internal function, used as a final step of buffer release. Shall be invoked
+ * only when the buffer is no longer in use (removed from idr). Will call the
+ * release callback (if applicable), and free the memory.
+ */
+static void hl_mmap_mem_buf_destroy(struct hl_mmap_mem_buf *buf)
+{
+	if (buf->behavior->release)
+		buf->behavior->release(buf);
+
+	kfree(buf);
+}
+
+/**
+ * hl_mmap_mem_buf_release - release buffer
+ *
+ * @kref: kref that reached 0.
+ *
+ * Internal function, used as a kref release callback, when the last user of
+ * the buffer is released. Shall be called from an interrupt context.
+ */
+static void hl_mmap_mem_buf_release(struct kref *kref)
+{
+	struct hl_mmap_mem_buf *buf =
+		container_of(kref, struct hl_mmap_mem_buf, refcount);
+
+	spin_lock(&buf->mmg->lock);
+	idr_remove(&buf->mmg->handles, lower_32_bits(buf->handle >> PAGE_SHIFT));
+	spin_unlock(&buf->mmg->lock);
+
+	hl_mmap_mem_buf_destroy(buf);
+}
+
+/**
+ * hl_mmap_mem_buf_remove_idr_locked - remove handle from idr
+ *
+ * @kref: kref that reached 0.
+ *
+ * Internal function, used for kref put by handle. Assumes mmg lock is taken.
+ * Will remove the buffer from idr, without destroying it.
+ */
+static void hl_mmap_mem_buf_remove_idr_locked(struct kref *kref)
+{
+	struct hl_mmap_mem_buf *buf =
+		container_of(kref, struct hl_mmap_mem_buf, refcount);
+
+	idr_remove(&buf->mmg->handles, lower_32_bits(buf->handle >> PAGE_SHIFT));
+}
+
+/**
+ * hl_mmap_mem_buf_put - decrease the reference to the buffer
+ *
+ * @buf: memory manager buffer descriptor
+ *
+ * Decrease the reference to the buffer, and release it if it was the last one.
+ * Shall be called from an interrupt context.
+ */
+int hl_mmap_mem_buf_put(struct hl_mmap_mem_buf *buf)
+{
+	return kref_put(&buf->refcount, hl_mmap_mem_buf_release);
+}
+
+/**
+ * hl_mmap_mem_buf_put_handle - decrease the reference to the buffer with the
+ *                              given handle.
+ *
+ * @mmg: parent unified memory manager
+ * @handle: requested buffer handle
+ *
+ * Decrease the reference to the buffer, and release it if it was the last one.
+ * Shall not be called from an interrupt context. Return -EINVAL if handle was
+ * not found, else return the put outcome (0 or 1).
+ */
+int hl_mmap_mem_buf_put_handle(struct hl_mem_mgr *mmg, u64 handle)
+{
+	struct hl_mmap_mem_buf *buf;
+
+	spin_lock(&mmg->lock);
+	buf = idr_find(&mmg->handles, lower_32_bits(handle >> PAGE_SHIFT));
+	if (!buf) {
+		spin_unlock(&mmg->lock);
+		dev_dbg(mmg->dev,
+			 "Buff put failed, no match to handle %#llx\n", handle);
+		return -EINVAL;
+	}
+
+	if (kref_put(&buf->refcount, hl_mmap_mem_buf_remove_idr_locked)) {
+		spin_unlock(&mmg->lock);
+		hl_mmap_mem_buf_destroy(buf);
+		return 1;
+	}
+
+	spin_unlock(&mmg->lock);
+	return 0;
+}
+
+/**
+ * hl_mmap_mem_buf_alloc - allocate a new mappable buffer
+ *
+ * @mmg: parent unified memory manager
+ * @behavior: behavior object describing this buffer polymorphic behavior
+ * @gfp: gfp flags to use for the memory allocations
+ * @args: additional args passed to behavior->alloc
+ *
+ * Allocate and register a new memory buffer inside the give memory manager.
+ * Return the pointer to the new buffer on success or NULL on failure.
+ */
+struct hl_mmap_mem_buf *
+hl_mmap_mem_buf_alloc(struct hl_mem_mgr *mmg,
+		      struct hl_mmap_mem_buf_behavior *behavior, gfp_t gfp,
+		      void *args)
+{
+	struct hl_mmap_mem_buf *buf;
+	int rc;
+
+	buf = kzalloc(sizeof(*buf), gfp);
+	if (!buf)
+		return NULL;
+
+	spin_lock(&mmg->lock);
+	rc = idr_alloc(&mmg->handles, buf, 1, 0, GFP_ATOMIC);
+	spin_unlock(&mmg->lock);
+	if (rc < 0) {
+		dev_err(mmg->dev,
+			"%s: Failed to allocate IDR for a new buffer, rc=%d\n",
+			behavior->topic, rc);
+		goto free_buf;
+	}
+
+	buf->mmg = mmg;
+	buf->behavior = behavior;
+	buf->handle = (((u64)rc | buf->behavior->mem_id) << PAGE_SHIFT);
+	kref_init(&buf->refcount);
+
+	rc = buf->behavior->alloc(buf, gfp, args);
+	if (rc) {
+		dev_err(mmg->dev, "%s: Failure in buffer alloc callback %d\n",
+			behavior->topic, rc);
+		goto remove_idr;
+	}
+
+	return buf;
+
+remove_idr:
+	spin_lock(&mmg->lock);
+	idr_remove(&mmg->handles, lower_32_bits(buf->handle >> PAGE_SHIFT));
+	spin_unlock(&mmg->lock);
+free_buf:
+	kfree(buf);
+	return NULL;
+}
+
+/**
+ * hl_mmap_mem_buf_vm_close - handle mmap close
+ *
+ * @vma: the vma object for which mmap was closed.
+ *
+ * Put the memory buffer if it is no longer mapped.
+ */
+static void hl_mmap_mem_buf_vm_close(struct vm_area_struct *vma)
+{
+	struct hl_mmap_mem_buf *buf =
+		(struct hl_mmap_mem_buf *)vma->vm_private_data;
+	long new_mmap_size;
+
+	new_mmap_size = buf->real_mapped_size - (vma->vm_end - vma->vm_start);
+
+	if (new_mmap_size > 0) {
+		buf->real_mapped_size = new_mmap_size;
+		return;
+	}
+
+	atomic_set(&buf->mmap, 0);
+	hl_mmap_mem_buf_put(buf);
+	vma->vm_private_data = NULL;
+}
+
+static const struct vm_operations_struct hl_mmap_mem_buf_vm_ops = {
+	.close = hl_mmap_mem_buf_vm_close
+};
+
+/**
+ * hl_mem_mgr_mmap - map the given buffer to the user
+ *
+ * @mmg: unified memory manager
+ * @vma: the vma object for which mmap was closed.
+ * @args: additional args passed to behavior->mmap
+ *
+ * Map the buffer specified by the vma->vm_pgoff to the given vma.
+ */
+int hl_mem_mgr_mmap(struct hl_mem_mgr *mmg, struct vm_area_struct *vma,
+		    void *args)
+{
+	struct hl_mmap_mem_buf *buf;
+	u64 user_mem_size;
+	u64 handle;
+	int rc;
+
+	/* We use the page offset to hold the idr and thus we need to clear
+	 * it before doing the mmap itself
+	 */
+	handle = vma->vm_pgoff << PAGE_SHIFT;
+	vma->vm_pgoff = 0;
+
+	/* Reference was taken here */
+	buf = hl_mmap_mem_buf_get(mmg, handle);
+	if (!buf) {
+		dev_err(mmg->dev,
+			"Memory mmap failed, no match to handle %#llx\n", handle);
+		return -EINVAL;
+	}
+
+	/* Validation check */
+	user_mem_size = vma->vm_end - vma->vm_start;
+	if (user_mem_size != ALIGN(buf->mappable_size, PAGE_SIZE)) {
+		dev_err(mmg->dev,
+			"%s: Memory mmap failed, mmap VM size 0x%llx != 0x%llx allocated physical mem size\n",
+			buf->behavior->topic, user_mem_size, buf->mappable_size);
+		rc = -EINVAL;
+		goto put_mem;
+	}
+
+	if (!access_ok((void __user *)(uintptr_t)vma->vm_start,
+		       user_mem_size)) {
+		dev_err(mmg->dev, "%s: User pointer is invalid - 0x%lx\n",
+			buf->behavior->topic, vma->vm_start);
+
+		rc = -EINVAL;
+		goto put_mem;
+	}
+
+	if (atomic_cmpxchg(&buf->mmap, 0, 1)) {
+		dev_err(mmg->dev,
+			"%s, Memory mmap failed, already mapped to user\n",
+			buf->behavior->topic);
+		rc = -EINVAL;
+		goto put_mem;
+	}
+
+	vma->vm_ops = &hl_mmap_mem_buf_vm_ops;
+
+	/* Note: We're transferring the memory reference to vma->vm_private_data here. */
+
+	vma->vm_private_data = buf;
+
+	rc = buf->behavior->mmap(buf, vma, args);
+	if (rc) {
+		atomic_set(&buf->mmap, 0);
+		goto put_mem;
+	}
+
+	buf->real_mapped_size = buf->mappable_size;
+	vma->vm_pgoff = handle >> PAGE_SHIFT;
+
+	return 0;
+
+put_mem:
+	hl_mmap_mem_buf_put(buf);
+	return rc;
+}
+
+/**
+ * hl_mem_mgr_init - initialize unified memory manager
+ *
+ * @dev: owner device pointer
+ * @mmg: structure to initialize
+ *
+ * Initialize an instance of unified memory manager
+ */
+void hl_mem_mgr_init(struct device *dev, struct hl_mem_mgr *mmg)
+{
+	mmg->dev = dev;
+	spin_lock_init(&mmg->lock);
+	idr_init(&mmg->handles);
+}
+
+static void hl_mem_mgr_fini_stats_reset(struct hl_mem_mgr_fini_stats *stats)
+{
+	if (!stats)
+		return;
+
+	memset(stats, 0, sizeof(*stats));
+}
+
+static void hl_mem_mgr_fini_stats_inc(u64 mem_id, struct hl_mem_mgr_fini_stats *stats)
+{
+	if (!stats)
+		return;
+
+	switch (mem_id) {
+	case HL_MMAP_TYPE_CB:
+		++stats->n_busy_cb;
+		break;
+	case HL_MMAP_TYPE_TS_BUFF:
+		++stats->n_busy_ts;
+		break;
+	default:
+		/* we currently store only CB/TS so this shouldn't happen */
+		++stats->n_busy_other;
+	}
+}
+
+/**
+ * hl_mem_mgr_fini - release unified memory manager
+ *
+ * @mmg: parent unified memory manager
+ * @stats: if non-NULL, will return some counters for handles that could not be removed.
+ *
+ * Release the unified memory manager. Shall be called from an interrupt context.
+ */
+void hl_mem_mgr_fini(struct hl_mem_mgr *mmg, struct hl_mem_mgr_fini_stats *stats)
+{
+	struct hl_mmap_mem_buf *buf;
+	struct idr *idp;
+	const char *topic;
+	u64 mem_id;
+	u32 id;
+
+	hl_mem_mgr_fini_stats_reset(stats);
+
+	idp = &mmg->handles;
+
+	idr_for_each_entry(idp, buf, id) {
+		topic = buf->behavior->topic;
+		mem_id = buf->behavior->mem_id;
+		if (hl_mmap_mem_buf_put(buf) != 1) {
+			dev_err(mmg->dev,
+				"%s: Buff handle %u for CTX is still alive\n",
+				topic, id);
+			hl_mem_mgr_fini_stats_inc(mem_id, stats);
+		}
+	}
+}
+
+/**
+ * hl_mem_mgr_idr_destroy() - destroy memory manager IDR.
+ * @mmg: parent unified memory manager
+ *
+ * Destroy the memory manager IDR.
+ * Shall be called when IDR is empty and no memory buffers are in use.
+ */
+void hl_mem_mgr_idr_destroy(struct hl_mem_mgr *mmg)
+{
+	if (!idr_is_empty(&mmg->handles))
+		dev_crit(mmg->dev, "memory manager IDR is destroyed while it is not empty!\n");
+
+	idr_destroy(&mmg->handles);
+}
diff --git a/drivers/accel/habanalabs/common/mmu/Makefile b/drivers/accel/habanalabs/common/mmu/Makefile
new file mode 100644
index 000000000000..f4b815bf4f7d
--- /dev/null
+++ b/drivers/accel/habanalabs/common/mmu/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+HL_COMMON_MMU_FILES := common/mmu/mmu.o common/mmu/mmu_v1.o \
+			common/mmu/mmu_v2.o common/mmu/mmu_v2_hr.o
diff --git a/drivers/accel/habanalabs/common/mmu/mmu.c b/drivers/accel/habanalabs/common/mmu/mmu.c
new file mode 100644
index 000000000000..79823facce7f
--- /dev/null
+++ b/drivers/accel/habanalabs/common/mmu/mmu.c
@@ -0,0 +1,1434 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Copyright 2016-2022 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ */
+
+#include <linux/slab.h>
+#include <linux/pci.h>
+
+#include "../habanalabs.h"
+
+#include <trace/events/habanalabs.h>
+
+/**
+ * hl_mmu_get_funcs() - get MMU functions structure
+ * @hdev: habanalabs device structure.
+ * @pgt_residency: page table residency.
+ * @is_dram_addr: true if we need HMMU functions
+ *
+ * @return appropriate MMU functions structure
+ */
+static struct hl_mmu_funcs *hl_mmu_get_funcs(struct hl_device *hdev, int pgt_residency,
+									bool is_dram_addr)
+{
+	return &hdev->mmu_func[pgt_residency];
+}
+
+bool hl_is_dram_va(struct hl_device *hdev, u64 virt_addr)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+
+	return hl_mem_area_inside_range(virt_addr, prop->dmmu.page_size,
+					prop->dmmu.start_addr,
+					prop->dmmu.end_addr);
+}
+
+/**
+ * hl_mmu_init() - initialize the MMU module.
+ * @hdev: habanalabs device structure.
+ *
+ * Return: 0 for success, non-zero for failure.
+ */
+int hl_mmu_init(struct hl_device *hdev)
+{
+	int rc = -EOPNOTSUPP;
+
+	if (hdev->mmu_disable)
+		return 0;
+
+	mutex_init(&hdev->mmu_lock);
+
+	if (hdev->mmu_func[MMU_DR_PGT].init != NULL) {
+		rc = hdev->mmu_func[MMU_DR_PGT].init(hdev);
+		if (rc)
+			return rc;
+	}
+
+	if (hdev->mmu_func[MMU_HR_PGT].init != NULL) {
+		rc = hdev->mmu_func[MMU_HR_PGT].init(hdev);
+		if (rc)
+			goto fini_dr_mmu;
+	}
+
+	return 0;
+
+fini_dr_mmu:
+	if (hdev->mmu_func[MMU_DR_PGT].fini != NULL)
+		hdev->mmu_func[MMU_DR_PGT].fini(hdev);
+
+	return rc;
+}
+
+/**
+ * hl_mmu_fini() - release the MMU module.
+ * @hdev: habanalabs device structure.
+ *
+ * This function does the following:
+ * - Disable MMU in H/W.
+ * - Free the pgt_infos pool.
+ *
+ * All contexts should be freed before calling this function.
+ */
+void hl_mmu_fini(struct hl_device *hdev)
+{
+	if (hdev->mmu_disable)
+		return;
+
+	if (hdev->mmu_func[MMU_DR_PGT].fini != NULL)
+		hdev->mmu_func[MMU_DR_PGT].fini(hdev);
+
+	if (hdev->mmu_func[MMU_HR_PGT].fini != NULL)
+		hdev->mmu_func[MMU_HR_PGT].fini(hdev);
+
+	mutex_destroy(&hdev->mmu_lock);
+}
+
+/**
+ * hl_mmu_ctx_init() - initialize a context for using the MMU module.
+ * @ctx: pointer to the context structure to initialize.
+ *
+ * Initialize a mutex to protect the concurrent mapping flow, a hash to hold all
+ * page tables hops related to this context.
+ * Return: 0 on success, non-zero otherwise.
+ */
+int hl_mmu_ctx_init(struct hl_ctx *ctx)
+{
+	struct hl_device *hdev = ctx->hdev;
+	int rc = -EOPNOTSUPP;
+
+	if (hdev->mmu_disable)
+		return 0;
+
+	if (hdev->mmu_func[MMU_DR_PGT].ctx_init != NULL) {
+		rc = hdev->mmu_func[MMU_DR_PGT].ctx_init(ctx);
+		if (rc)
+			return rc;
+	}
+
+	if (hdev->mmu_func[MMU_HR_PGT].ctx_init != NULL) {
+		rc = hdev->mmu_func[MMU_HR_PGT].ctx_init(ctx);
+		if (rc)
+			goto fini_dr_ctx;
+	}
+
+	return 0;
+
+fini_dr_ctx:
+	if (hdev->mmu_func[MMU_DR_PGT].fini != NULL)
+		hdev->mmu_func[MMU_DR_PGT].fini(hdev);
+
+	return rc;
+}
+
+/*
+ * hl_mmu_ctx_fini - disable a ctx from using the mmu module
+ *
+ * @ctx: pointer to the context structure
+ *
+ * This function does the following:
+ * - Free any pgts which were not freed yet
+ * - Free the mutex
+ * - Free DRAM default page mapping hops
+ */
+void hl_mmu_ctx_fini(struct hl_ctx *ctx)
+{
+	struct hl_device *hdev = ctx->hdev;
+
+	if (hdev->mmu_disable)
+		return;
+
+	if (hdev->mmu_func[MMU_DR_PGT].ctx_fini != NULL)
+		hdev->mmu_func[MMU_DR_PGT].ctx_fini(ctx);
+
+	if (hdev->mmu_func[MMU_HR_PGT].ctx_fini != NULL)
+		hdev->mmu_func[MMU_HR_PGT].ctx_fini(ctx);
+}
+
+/*
+ * hl_mmu_get_real_page_size - get real page size to use in map/unmap operation
+ *
+ * @hdev: pointer to device data.
+ * @mmu_prop: MMU properties.
+ * @page_size: page size
+ * @real_page_size: set here the actual page size to use for the operation
+ * @is_dram_addr: true if DRAM address, otherwise false.
+ *
+ * @return 0 on success, otherwise non 0 error code
+ *
+ * note that this is general implementation that can fit most MMU arch. but as this is used as an
+ * MMU function:
+ * 1. it shall not be called directly- only from mmu_func structure instance
+ * 2. each MMU may modify the implementation internally
+ */
+int hl_mmu_get_real_page_size(struct hl_device *hdev, struct hl_mmu_properties *mmu_prop,
+				u32 page_size, u32 *real_page_size, bool is_dram_addr)
+{
+	/*
+	 * The H/W handles mapping of specific page sizes. Hence if the page
+	 * size is bigger, we break it to sub-pages and map them separately.
+	 */
+	if ((page_size % mmu_prop->page_size) == 0) {
+		*real_page_size = mmu_prop->page_size;
+		return 0;
+	}
+
+	dev_err(hdev->dev, "page size of %u is not %uKB aligned, can't map\n",
+						page_size, mmu_prop->page_size >> 10);
+
+	return -EFAULT;
+}
+
+static struct hl_mmu_properties *hl_mmu_get_prop(struct hl_device *hdev, u32 page_size,
+							bool is_dram_addr)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+
+	if (is_dram_addr)
+		return &prop->dmmu;
+	else if ((page_size % prop->pmmu_huge.page_size) == 0)
+		return &prop->pmmu_huge;
+
+	return &prop->pmmu;
+}
+
+/*
+ * hl_mmu_unmap_page - unmaps a virtual addr
+ *
+ * @ctx: pointer to the context structure
+ * @virt_addr: virt addr to map from
+ * @page_size: size of the page to unmap
+ * @flush_pte: whether to do a PCI flush
+ *
+ * This function does the following:
+ * - Check that the virt addr is mapped
+ * - Unmap the virt addr and frees pgts if possible
+ * - Returns 0 on success, -EINVAL if the given addr is not mapped
+ *
+ * Because this function changes the page tables in the device and because it
+ * changes the MMU hash, it must be protected by a lock.
+ * However, because it maps only a single page, the lock should be implemented
+ * in a higher level in order to protect the entire mapping of the memory area
+ *
+ * For optimization reasons PCI flush may be requested once after unmapping of
+ * large area.
+ */
+int hl_mmu_unmap_page(struct hl_ctx *ctx, u64 virt_addr, u32 page_size, bool flush_pte)
+{
+	struct hl_device *hdev = ctx->hdev;
+	struct hl_mmu_properties *mmu_prop;
+	struct hl_mmu_funcs *mmu_funcs;
+	int i, pgt_residency, rc = 0;
+	u32 real_page_size, npages;
+	u64 real_virt_addr;
+	bool is_dram_addr;
+
+	if (hdev->mmu_disable)
+		return 0;
+
+	is_dram_addr = hl_is_dram_va(hdev, virt_addr);
+	mmu_prop = hl_mmu_get_prop(hdev, page_size, is_dram_addr);
+
+	pgt_residency = mmu_prop->host_resident ? MMU_HR_PGT : MMU_DR_PGT;
+	mmu_funcs = hl_mmu_get_funcs(hdev, pgt_residency, is_dram_addr);
+
+	rc = hdev->asic_funcs->mmu_get_real_page_size(hdev, mmu_prop, page_size, &real_page_size,
+							is_dram_addr);
+	if (rc)
+		return rc;
+
+	npages = page_size / real_page_size;
+	real_virt_addr = virt_addr;
+
+	for (i = 0 ; i < npages ; i++) {
+		rc = mmu_funcs->unmap(ctx, real_virt_addr, is_dram_addr);
+		if (rc)
+			break;
+
+		real_virt_addr += real_page_size;
+	}
+
+	if (flush_pte)
+		mmu_funcs->flush(ctx);
+
+	if (trace_habanalabs_mmu_unmap_enabled() && !rc)
+		trace_habanalabs_mmu_unmap(&hdev->pdev->dev, virt_addr, 0, page_size, flush_pte);
+
+	return rc;
+}
+
+/*
+ * hl_mmu_map_page - maps a virtual addr to physical addr
+ *
+ * @ctx: pointer to the context structure
+ * @virt_addr: virt addr to map from
+ * @phys_addr: phys addr to map to
+ * @page_size: physical page size
+ * @flush_pte: whether to do a PCI flush
+ *
+ * This function does the following:
+ * - Check that the virt addr is not mapped
+ * - Allocate pgts as necessary in order to map the virt addr to the phys
+ * - Returns 0 on success, -EINVAL if addr is already mapped, or -ENOMEM.
+ *
+ * Because this function changes the page tables in the device and because it
+ * changes the MMU hash, it must be protected by a lock.
+ * However, because it maps only a single page, the lock should be implemented
+ * in a higher level in order to protect the entire mapping of the memory area
+ *
+ * For optimization reasons PCI flush may be requested once after mapping of
+ * large area.
+ */
+int hl_mmu_map_page(struct hl_ctx *ctx, u64 virt_addr, u64 phys_addr, u32 page_size,
+			bool flush_pte)
+{
+	int i, rc, pgt_residency, mapped_cnt = 0;
+	struct hl_device *hdev = ctx->hdev;
+	struct hl_mmu_properties *mmu_prop;
+	u64 real_virt_addr, real_phys_addr;
+	struct hl_mmu_funcs *mmu_funcs;
+	u32 real_page_size, npages;
+	bool is_dram_addr;
+
+
+	if (hdev->mmu_disable)
+		return 0;
+
+	is_dram_addr = hl_is_dram_va(hdev, virt_addr);
+	mmu_prop = hl_mmu_get_prop(hdev, page_size, is_dram_addr);
+
+	pgt_residency = mmu_prop->host_resident ? MMU_HR_PGT : MMU_DR_PGT;
+	mmu_funcs = hl_mmu_get_funcs(hdev, pgt_residency, is_dram_addr);
+
+	rc = hdev->asic_funcs->mmu_get_real_page_size(hdev, mmu_prop, page_size, &real_page_size,
+							is_dram_addr);
+	if (rc)
+		return rc;
+
+	/*
+	 * Verify that the phys and virt addresses are aligned with the
+	 * MMU page size (in dram this means checking the address and MMU
+	 * after scrambling)
+	 */
+	if ((is_dram_addr &&
+			((hdev->asic_funcs->scramble_addr(hdev, phys_addr) &
+				(mmu_prop->page_size - 1)) ||
+			(hdev->asic_funcs->scramble_addr(hdev, virt_addr) &
+				(mmu_prop->page_size - 1)))) ||
+		(!is_dram_addr && ((phys_addr & (real_page_size - 1)) ||
+				(virt_addr & (real_page_size - 1)))))
+		dev_crit(hdev->dev,
+			"Mapping address 0x%llx with virtual address 0x%llx and page size of 0x%x is erroneous! Addresses must be divisible by page size",
+			phys_addr, virt_addr, real_page_size);
+
+	npages = page_size / real_page_size;
+	real_virt_addr = virt_addr;
+	real_phys_addr = phys_addr;
+
+	for (i = 0 ; i < npages ; i++) {
+		rc = mmu_funcs->map(ctx, real_virt_addr, real_phys_addr, real_page_size,
+										is_dram_addr);
+		if (rc)
+			goto err;
+
+		real_virt_addr += real_page_size;
+		real_phys_addr += real_page_size;
+		mapped_cnt++;
+	}
+
+	if (flush_pte)
+		mmu_funcs->flush(ctx);
+
+	trace_habanalabs_mmu_map(&hdev->pdev->dev, virt_addr, phys_addr, page_size, flush_pte);
+
+	return 0;
+
+err:
+	real_virt_addr = virt_addr;
+	for (i = 0 ; i < mapped_cnt ; i++) {
+		if (mmu_funcs->unmap(ctx, real_virt_addr, is_dram_addr))
+			dev_warn_ratelimited(hdev->dev,
+				"failed to unmap va: 0x%llx\n", real_virt_addr);
+
+		real_virt_addr += real_page_size;
+	}
+
+	mmu_funcs->flush(ctx);
+
+	return rc;
+}
+
+/*
+ * hl_mmu_map_contiguous - implements a wrapper for hl_mmu_map_page
+ *                         for mapping contiguous physical memory
+ *
+ * @ctx: pointer to the context structure
+ * @virt_addr: virt addr to map from
+ * @phys_addr: phys addr to map to
+ * @size: size to map
+ *
+ */
+int hl_mmu_map_contiguous(struct hl_ctx *ctx, u64 virt_addr,
+					u64 phys_addr, u32 size)
+{
+	struct hl_device *hdev = ctx->hdev;
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	u64 curr_va, curr_pa;
+	u32 page_size;
+	bool flush_pte;
+	int rc = 0, off;
+
+	if (hl_mem_area_inside_range(virt_addr, size,
+			prop->dmmu.start_addr, prop->dmmu.end_addr))
+		page_size = prop->dmmu.page_size;
+	else if (hl_mem_area_inside_range(virt_addr, size,
+			prop->pmmu.start_addr, prop->pmmu.end_addr))
+		page_size = prop->pmmu.page_size;
+	else if (hl_mem_area_inside_range(virt_addr, size,
+			prop->pmmu_huge.start_addr, prop->pmmu_huge.end_addr))
+		page_size = prop->pmmu_huge.page_size;
+	else
+		return -EINVAL;
+
+	for (off = 0 ; off < size ; off += page_size) {
+		curr_va = virt_addr + off;
+		curr_pa = phys_addr + off;
+		flush_pte = (off + page_size) >= size;
+		rc = hl_mmu_map_page(ctx, curr_va, curr_pa, page_size,
+								flush_pte);
+		if (rc) {
+			dev_err(hdev->dev,
+				"Map failed for va 0x%llx to pa 0x%llx\n",
+				curr_va, curr_pa);
+			/* last mapping failed so don't try to unmap it - reduce off by page_size */
+			off -= page_size;
+			goto unmap;
+		}
+	}
+
+	return rc;
+
+unmap:
+	for (; off >= 0 ; off -= page_size) {
+		curr_va = virt_addr + off;
+		flush_pte = (off - (s32) page_size) < 0;
+		if (hl_mmu_unmap_page(ctx, curr_va, page_size, flush_pte))
+			dev_warn_ratelimited(hdev->dev,
+				"failed to unmap va 0x%llx\n", curr_va);
+	}
+
+	return rc;
+}
+
+/*
+ * hl_mmu_unmap_contiguous - implements a wrapper for hl_mmu_unmap_page
+ *                           for unmapping contiguous physical memory
+ *
+ * @ctx: pointer to the context structure
+ * @virt_addr: virt addr to unmap
+ * @size: size to unmap
+ *
+ */
+int hl_mmu_unmap_contiguous(struct hl_ctx *ctx, u64 virt_addr, u32 size)
+{
+	struct hl_device *hdev = ctx->hdev;
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	u64 curr_va;
+	u32 page_size;
+	bool flush_pte;
+	int rc = 0, off;
+
+	if (hl_mem_area_inside_range(virt_addr, size,
+			prop->dmmu.start_addr, prop->dmmu.end_addr))
+		page_size = prop->dmmu.page_size;
+	else if (hl_mem_area_inside_range(virt_addr, size,
+			prop->pmmu.start_addr, prop->pmmu.end_addr))
+		page_size = prop->pmmu.page_size;
+	else if (hl_mem_area_inside_range(virt_addr, size,
+			prop->pmmu_huge.start_addr, prop->pmmu_huge.end_addr))
+		page_size = prop->pmmu_huge.page_size;
+	else
+		return -EINVAL;
+
+	for (off = 0 ; off < size ; off += page_size) {
+		curr_va = virt_addr + off;
+		flush_pte = (off + page_size) >= size;
+		rc = hl_mmu_unmap_page(ctx, curr_va, page_size, flush_pte);
+		if (rc)
+			dev_warn_ratelimited(hdev->dev,
+				"Unmap failed for va 0x%llx\n", curr_va);
+	}
+
+	return rc;
+}
+
+static void hl_mmu_pa_page_with_offset(struct hl_ctx *ctx, u64 virt_addr,
+						struct hl_mmu_hop_info *hops,
+						u64 *phys_addr)
+{
+	struct asic_fixed_properties *prop = &ctx->hdev->asic_prop;
+	u64 offset_mask, addr_mask, hop_shift, tmp_phys_addr;
+	struct hl_mmu_properties *mmu_prop;
+
+	/* last hop holds the phys address and flags */
+	if (hops->unscrambled_paddr)
+		tmp_phys_addr = hops->unscrambled_paddr;
+	else
+		tmp_phys_addr = hops->hop_info[hops->used_hops - 1].hop_pte_val;
+
+	if (hops->range_type == HL_VA_RANGE_TYPE_HOST_HUGE)
+		mmu_prop = &prop->pmmu_huge;
+	else if (hops->range_type == HL_VA_RANGE_TYPE_HOST)
+		mmu_prop = &prop->pmmu;
+	else /* HL_VA_RANGE_TYPE_DRAM */
+		mmu_prop = &prop->dmmu;
+
+	if ((hops->range_type == HL_VA_RANGE_TYPE_DRAM) &&
+			!is_power_of_2(prop->dram_page_size)) {
+		u64 dram_page_size, dram_base, abs_phys_addr, abs_virt_addr,
+			page_id, page_start;
+		u32 page_off;
+
+		/*
+		 * Bit arithmetic cannot be used for non power of two page
+		 * sizes. In addition, since bit arithmetic is not used,
+		 * we cannot ignore dram base. All that shall be considered.
+		 */
+
+		dram_page_size = prop->dram_page_size;
+		dram_base = prop->dram_base_address;
+		abs_phys_addr = tmp_phys_addr - dram_base;
+		abs_virt_addr = virt_addr - dram_base;
+		page_id = DIV_ROUND_DOWN_ULL(abs_phys_addr, dram_page_size);
+		page_start = page_id * dram_page_size;
+		div_u64_rem(abs_virt_addr, dram_page_size, &page_off);
+
+		*phys_addr = page_start + page_off + dram_base;
+	} else {
+		/*
+		 * find the correct hop shift field in hl_mmu_properties
+		 * structure in order to determine the right masks
+		 * for the page offset.
+		 */
+		hop_shift = mmu_prop->hop_shifts[hops->used_hops - 1];
+		offset_mask = (1ull << hop_shift) - 1;
+		addr_mask = ~(offset_mask);
+		*phys_addr = (tmp_phys_addr & addr_mask) |
+				(virt_addr & offset_mask);
+	}
+}
+
+int hl_mmu_va_to_pa(struct hl_ctx *ctx, u64 virt_addr, u64 *phys_addr)
+{
+	struct hl_mmu_hop_info hops;
+	int rc;
+
+	memset(&hops, 0, sizeof(hops));
+
+	rc = hl_mmu_get_tlb_info(ctx, virt_addr, &hops);
+	if (rc)
+		return rc;
+
+	hl_mmu_pa_page_with_offset(ctx, virt_addr, &hops,  phys_addr);
+
+	return 0;
+}
+
+int hl_mmu_get_tlb_info(struct hl_ctx *ctx, u64 virt_addr,
+			struct hl_mmu_hop_info *hops)
+{
+	struct hl_device *hdev = ctx->hdev;
+	struct asic_fixed_properties *prop;
+	struct hl_mmu_properties *mmu_prop;
+	struct hl_mmu_funcs *mmu_funcs;
+	int pgt_residency, rc;
+	bool is_dram_addr;
+
+	if (hdev->mmu_disable)
+		return -EOPNOTSUPP;
+
+	prop = &hdev->asic_prop;
+	hops->scrambled_vaddr = virt_addr;      /* assume no scrambling */
+
+	is_dram_addr = hl_mem_area_inside_range(virt_addr, prop->dmmu.page_size,
+								prop->dmmu.start_addr,
+								prop->dmmu.end_addr);
+
+	/* host-residency is the same in PMMU and PMMU huge, no need to distinguish here */
+	mmu_prop = is_dram_addr ? &prop->dmmu : &prop->pmmu;
+	pgt_residency = mmu_prop->host_resident ? MMU_HR_PGT : MMU_DR_PGT;
+	mmu_funcs = hl_mmu_get_funcs(hdev, pgt_residency, is_dram_addr);
+
+	mutex_lock(&hdev->mmu_lock);
+	rc = mmu_funcs->get_tlb_info(ctx, virt_addr, hops);
+	mutex_unlock(&hdev->mmu_lock);
+
+	if (rc)
+		return rc;
+
+	/* add page offset to physical address */
+	if (hops->unscrambled_paddr)
+		hl_mmu_pa_page_with_offset(ctx, virt_addr, hops, &hops->unscrambled_paddr);
+
+	return 0;
+}
+
+int hl_mmu_if_set_funcs(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+
+	if (hdev->mmu_disable)
+		return 0;
+
+	switch (hdev->asic_type) {
+	case ASIC_GOYA:
+	case ASIC_GAUDI:
+	case ASIC_GAUDI_SEC:
+		hl_mmu_v1_set_funcs(hdev, &hdev->mmu_func[MMU_DR_PGT]);
+		break;
+	case ASIC_GAUDI2:
+	case ASIC_GAUDI2B:
+	case ASIC_GAUDI2C:
+	case ASIC_GAUDI2D:
+		hl_mmu_v2_set_funcs(hdev, &hdev->mmu_func[MMU_DR_PGT]);
+		if (prop->pmmu.host_resident)
+			hl_mmu_v2_hr_set_funcs(hdev, &hdev->mmu_func[MMU_HR_PGT]);
+		break;
+	default:
+		dev_err(hdev->dev, "Unrecognized ASIC type %d\n",
+			hdev->asic_type);
+		return -EOPNOTSUPP;
+	}
+
+	return 0;
+}
+
+/**
+ * hl_mmu_scramble_addr() - The generic mmu address scrambling routine.
+ * @hdev: pointer to device data.
+ * @addr: The address to scramble.
+ *
+ * Return: The scrambled address.
+ */
+u64 hl_mmu_scramble_addr(struct hl_device *hdev, u64 addr)
+{
+	return addr;
+}
+
+/**
+ * hl_mmu_descramble_addr() - The generic mmu address descrambling
+ * routine.
+ * @hdev: pointer to device data.
+ * @addr: The address to descramble.
+ *
+ * Return: The un-scrambled address.
+ */
+u64 hl_mmu_descramble_addr(struct hl_device *hdev, u64 addr)
+{
+	return addr;
+}
+
+int hl_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard, u32 flags)
+{
+	int rc;
+
+	rc = hdev->asic_funcs->mmu_invalidate_cache(hdev, is_hard, flags);
+	if (rc)
+		dev_err_ratelimited(hdev->dev,
+				"%s: %s cache invalidation failed, rc=%d\n",
+				dev_name(&hdev->pdev->dev),
+				flags == VM_TYPE_USERPTR ? "PMMU" : "HMMU", rc);
+
+	return rc;
+}
+
+int hl_mmu_invalidate_cache_range(struct hl_device *hdev, bool is_hard,
+					u32 flags, u32 asid, u64 va, u64 size)
+{
+	int rc;
+
+	rc = hdev->asic_funcs->mmu_invalidate_cache_range(hdev, is_hard, flags,
+								asid, va, size);
+	if (rc)
+		dev_err_ratelimited(hdev->dev,
+			"%s: %s cache range invalidation failed: va=%#llx, size=%llu, rc=%d",
+			dev_name(&hdev->pdev->dev), flags == VM_TYPE_USERPTR ? "PMMU" : "HMMU",
+			va, size, rc);
+
+	return rc;
+}
+
+static void hl_mmu_prefetch_work_function(struct work_struct *work)
+{
+	struct hl_prefetch_work *pfw = container_of(work, struct hl_prefetch_work, prefetch_work);
+	struct hl_ctx *ctx = pfw->ctx;
+	struct hl_device *hdev = ctx->hdev;
+
+	if (!hl_device_operational(hdev, NULL))
+		goto put_ctx;
+
+	mutex_lock(&hdev->mmu_lock);
+
+	hdev->asic_funcs->mmu_prefetch_cache_range(ctx, pfw->flags, pfw->asid, pfw->va, pfw->size);
+
+	mutex_unlock(&hdev->mmu_lock);
+
+put_ctx:
+	/*
+	 * context was taken in the common mmu prefetch function- see comment there about
+	 * context handling.
+	 */
+	hl_ctx_put(ctx);
+	kfree(pfw);
+}
+
+int hl_mmu_prefetch_cache_range(struct hl_ctx *ctx, u32 flags, u32 asid, u64 va, u64 size)
+{
+	struct hl_prefetch_work *handle_prefetch_work;
+
+	handle_prefetch_work = kmalloc(sizeof(*handle_prefetch_work), GFP_KERNEL);
+	if (!handle_prefetch_work)
+		return -ENOMEM;
+
+	INIT_WORK(&handle_prefetch_work->prefetch_work, hl_mmu_prefetch_work_function);
+	handle_prefetch_work->ctx = ctx;
+	handle_prefetch_work->va = va;
+	handle_prefetch_work->size = size;
+	handle_prefetch_work->flags = flags;
+	handle_prefetch_work->asid = asid;
+
+	/*
+	 * as actual prefetch is done in a WQ we must get the context (and put it
+	 * at the end of the work function)
+	 */
+	hl_ctx_get(ctx);
+	queue_work(ctx->hdev->prefetch_wq, &handle_prefetch_work->prefetch_work);
+
+	return 0;
+}
+
+u64 hl_mmu_get_next_hop_addr(struct hl_ctx *ctx, u64 curr_pte)
+{
+	return (curr_pte & PAGE_PRESENT_MASK) ? (curr_pte & HOP_PHYS_ADDR_MASK) : ULLONG_MAX;
+}
+
+/**
+ * hl_mmu_get_hop_pte_phys_addr() - extract PTE address from HOP
+ * @ctx: pointer to the context structure to initialize.
+ * @mmu_prop: MMU properties.
+ * @hop_idx: HOP index.
+ * @hop_addr: HOP address.
+ * @virt_addr: virtual address for the translation.
+ *
+ * @return the matching PTE value on success, otherwise U64_MAX.
+ */
+u64 hl_mmu_get_hop_pte_phys_addr(struct hl_ctx *ctx, struct hl_mmu_properties *mmu_prop,
+					u8 hop_idx, u64 hop_addr, u64 virt_addr)
+{
+	u64 mask, shift;
+
+	if (hop_idx >= mmu_prop->num_hops) {
+		dev_err_ratelimited(ctx->hdev->dev, "Invalid hop index %d\n", hop_idx);
+		return U64_MAX;
+	}
+
+	shift = mmu_prop->hop_shifts[hop_idx];
+	mask = mmu_prop->hop_masks[hop_idx];
+
+	return hop_addr + ctx->hdev->asic_prop.mmu_pte_size * ((virt_addr & mask) >> shift);
+}
+
+static void mmu_dma_mem_free_from_chunk(struct gen_pool *pool,
+					struct gen_pool_chunk *chunk,
+					void *data)
+{
+	struct hl_device *hdev = data;
+
+	hl_asic_dma_free_coherent(hdev, (chunk->end_addr - chunk->start_addr) + 1,
+					(void *)chunk->start_addr, chunk->phys_addr);
+}
+
+void hl_mmu_hr_flush(struct hl_ctx *ctx)
+{
+	/* a flush operation requires memory barrier */
+	mb();
+}
+
+/**
+ * hl_mmu_hr_pool_destroy() - destroy genpool
+ * @hdev: habanalabs device structure.
+ * @hr_priv: MMU HR private data.
+ * @hop_table_size: HOP table size.
+ *
+ * This function does the following:
+ * - free entries allocated for shadow HOP0
+ * - free pool chunks
+ * - free pool
+ */
+static void hl_mmu_hr_pool_destroy(struct hl_device *hdev, struct hl_mmu_hr_priv *hr_priv,
+					u32 hop_table_size)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct gen_pool **pool = &hr_priv->mmu_pgt_pool;
+	struct pgt_info *hop0_pgt;
+	int asid;
+
+	if (ZERO_OR_NULL_PTR(*pool))
+		return;
+
+	/* Free the Fixed allocation of HOPs0 */
+	if (hr_priv->mmu_asid_hop0) {
+		for (asid = 0 ; asid < prop->max_asid ; asid++) {
+			hop0_pgt = &hr_priv->mmu_asid_hop0[asid];
+			if (ZERO_OR_NULL_PTR(hop0_pgt->virt_addr))
+				continue;
+
+			gen_pool_free(*pool, (uintptr_t) hop0_pgt->virt_addr, hop_table_size);
+		}
+	}
+
+	gen_pool_for_each_chunk(*pool, mmu_dma_mem_free_from_chunk, hdev);
+	gen_pool_destroy(*pool);
+
+	/* Make sure that if we arrive here again without init was called we
+	 * won't cause kernel panic. This can happen for example if we fail
+	 * during hard reset code at certain points
+	 */
+	*pool = NULL;
+}
+
+/**
+ * hl_mmu_hr_init() - initialize the MMU module.
+ * @hdev: habanalabs device structure.
+ * @hr_priv: MMU HR private data.
+ * @hop_table_size: HOP table size.
+ * @pgt_size: memory size allocated for the page table
+ *
+ * @return 0 on success otherwise non-zero error code
+ *
+ * This function does the following:
+ * - Create a pool of pages for pgt_infos.
+ * - Create a shadow table for pgt
+ */
+int hl_mmu_hr_init(struct hl_device *hdev, struct hl_mmu_hr_priv *hr_priv, u32 hop_table_size,
+			u64 pgt_size)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	size_t pool_chunk_size = SZ_4M;
+	struct pgt_info *hop0_pgt;
+	dma_addr_t dma_addr;
+	u64 virt_addr;
+	int i, rc;
+
+	/*
+	 * we set alloc size as PAGE_SIZE (sine dma_alloc_coherent allocation order/size is
+	 * PAGE_SHIFT/PAGE_SIZE) in order to be able to control the allocations alignment.
+	 * This way we can call "DMA alloc align" according to dma_alloc granularity and supply
+	 * allocations with higher-order alignment restrictions
+	 */
+	hr_priv->mmu_pgt_pool = gen_pool_create(PAGE_SHIFT, -1);
+	if (ZERO_OR_NULL_PTR(hr_priv->mmu_pgt_pool)) {
+		dev_err(hdev->dev, "Failed to create hr page pool\n");
+		return -ENOMEM;
+	}
+
+	hr_priv->mmu_asid_hop0 = kvcalloc(prop->max_asid, sizeof(struct pgt_info), GFP_KERNEL);
+	if (ZERO_OR_NULL_PTR(hr_priv->mmu_asid_hop0)) {
+		dev_err(hdev->dev, "Failed to allocate hr-mmu hop0 table\n");
+		rc = -ENOMEM;
+		goto destroy_mmu_pgt_pool;
+	}
+
+	for (i = 0 ; i < pgt_size ; i += pool_chunk_size) {
+		virt_addr = (uintptr_t) hl_asic_dma_alloc_coherent(hdev, pool_chunk_size,
+									&dma_addr,
+									GFP_KERNEL | __GFP_ZERO);
+		if (ZERO_OR_NULL_PTR(virt_addr)) {
+			dev_err(hdev->dev,
+				"Failed to allocate memory for host-resident page pool\n");
+			rc = -ENOMEM;
+			goto destroy_mmu_pgt_pool;
+		}
+
+		rc = gen_pool_add_virt(hr_priv->mmu_pgt_pool, virt_addr, (phys_addr_t) dma_addr,
+						pool_chunk_size, -1);
+		if (rc) {
+			dev_err(hdev->dev, "Failed to fill host-resident page pool\n");
+			goto destroy_mmu_pgt_pool;
+		}
+	}
+
+	for (i = 0 ; i < prop->max_asid ; i++) {
+		hop0_pgt = &hr_priv->mmu_asid_hop0[i];
+		hop0_pgt->virt_addr = (uintptr_t)
+					gen_pool_dma_zalloc_align(hr_priv->mmu_pgt_pool,
+								hop_table_size,
+								(dma_addr_t *) &hop0_pgt->phys_addr,
+								hop_table_size);
+		if (!hop0_pgt->virt_addr) {
+			dev_err(hdev->dev, "Failed to allocate HOP from pgt pool\n");
+			rc = -ENOMEM;
+			goto destroy_mmu_pgt_pool;
+		}
+	}
+
+	/* MMU H/W init will be done in device hw_init() */
+
+	return 0;
+
+destroy_mmu_pgt_pool:
+	hl_mmu_hr_pool_destroy(hdev, hr_priv, hop_table_size);
+	if (!ZERO_OR_NULL_PTR(hr_priv->mmu_asid_hop0))
+		kvfree(hr_priv->mmu_asid_hop0);
+
+	return rc;
+}
+
+/**
+ * hl_mmu_hr_fini() - release the MMU module.
+ * @hdev: habanalabs device structure.
+ * @hr_priv: MMU host resident private info.
+ * @hop_table_size: HOP table size
+ *
+ * This function does the following:
+ * - Disable MMU in H/W.
+ * - Free the pgt_infos pool.
+ *
+ * All contexts should be freed before calling this function.
+ */
+void hl_mmu_hr_fini(struct hl_device *hdev, struct hl_mmu_hr_priv *hr_priv, u32 hop_table_size)
+{
+	/* MMU H/W fini was already done in device hw_fini() */
+
+	hl_mmu_hr_pool_destroy(hdev, hr_priv, hop_table_size);
+
+	if (!ZERO_OR_NULL_PTR(hr_priv->mmu_asid_hop0)) {
+		kvfree(hr_priv->mmu_asid_hop0);
+
+		/* Make sure that if we arrive here again without init was
+		 * called we won't cause kernel panic. This can happen for
+		 * example if we fail during hard reset code at certain points
+		 */
+		hr_priv->mmu_asid_hop0 = NULL;
+	}
+}
+
+/**
+ * hl_mmu_hr_free_hop_remove_pgt() - free HOP and remove PGT from hash
+ * @pgt_info: page table info structure.
+ * @hr_priv: MMU HR private data.
+ * @hop_table_size: HOP table size.
+ */
+void hl_mmu_hr_free_hop_remove_pgt(struct pgt_info *pgt_info, struct hl_mmu_hr_priv *hr_priv,
+					u32 hop_table_size)
+{
+	gen_pool_free(hr_priv->mmu_pgt_pool, pgt_info->virt_addr, hop_table_size);
+	hash_del(&pgt_info->node);
+	kfree(pgt_info);
+}
+
+/**
+ * hl_mmu_hr_pte_phys_to_virt() - translate PTE phys addr to virt addr
+ * @ctx: pointer to the context structure
+ * @pgt: pgt_info for the HOP hosting the PTE
+ * @phys_pte_addr: phys address of the PTE
+ * @hop_table_size: HOP table size
+ *
+ * @return PTE virtual address
+ *
+ * The function use the pgt_info to get HOP base virt addr and obtain the PTE's virt addr
+ * by adding the PTE offset.
+ */
+u64 hl_mmu_hr_pte_phys_to_virt(struct hl_ctx *ctx, struct pgt_info *pgt,
+							u64 phys_pte_addr, u32 hop_table_size)
+{
+	u64 page_mask = (hop_table_size - 1);
+	u64 pte_offset = phys_pte_addr & page_mask;
+
+	return pgt->virt_addr + pte_offset;
+}
+
+/**
+ * hl_mmu_hr_write_pte() - write HR PTE
+ * @ctx: pointer to the context structure
+ * @pgt_info: HOP's page table info structure
+ * @phys_pte_addr: phys PTE address
+ * @val: raw PTE data
+ * @hop_table_size: HOP table size
+ */
+void hl_mmu_hr_write_pte(struct hl_ctx *ctx, struct pgt_info *pgt_info, u64 phys_pte_addr,
+								u64 val, u32 hop_table_size)
+{
+	/*
+	 * The value to write is the phys address of the next hop +
+	 * flags at the 12 LSBs.
+	 */
+	u64 virt_addr = hl_mmu_hr_pte_phys_to_virt(ctx, pgt_info, phys_pte_addr, hop_table_size);
+
+	*((u64 *) (uintptr_t) virt_addr) = val;
+}
+
+/**
+ * hl_mmu_hr_clear_pte() - clear HR PTE
+ * @ctx: pointer to the context structure
+ * @pgt_info: HOP's page table info structure
+ * @phys_pte_addr: phys PTE address
+ * @hop_table_size: HOP table size
+ */
+void hl_mmu_hr_clear_pte(struct hl_ctx *ctx, struct pgt_info *pgt_info, u64 phys_pte_addr,
+						u32 hop_table_size)
+{
+	/* no need to transform the value to physical address */
+	hl_mmu_hr_write_pte(ctx, pgt_info, phys_pte_addr, 0, hop_table_size);
+}
+
+/**
+ * hl_mmu_hr_put_pte() - put HR PTE and remove it if necessary (no more PTEs)
+ * @ctx: pointer to the context structure
+ * @pgt_info: HOP's page table info structure
+ * @hr_priv: HR MMU private info
+ * @hop_table_size: HOP table size
+ *
+ * @return number of PTEs still in the HOP
+ */
+int hl_mmu_hr_put_pte(struct hl_ctx *ctx, struct pgt_info *pgt_info,
+						struct hl_mmu_hr_priv *hr_priv,
+						u32 hop_table_size)
+{
+	int num_of_ptes_left;
+
+	pgt_info->num_of_ptes--;
+
+	/*
+	 * Need to save the number of ptes left because free_hop might free
+	 * the pgt_info
+	 */
+	num_of_ptes_left = pgt_info->num_of_ptes;
+	if (!num_of_ptes_left)
+		hl_mmu_hr_free_hop_remove_pgt(pgt_info, hr_priv, hop_table_size);
+
+	return num_of_ptes_left;
+}
+
+/**
+ * hl_mmu_hr_get_pte() - increase PGT PTE count
+ * @ctx: pointer to the context structure
+ * @hr_func: host resident functions
+ * @phys_hop_addr: HOP phys address
+ */
+void hl_mmu_hr_get_pte(struct hl_ctx *ctx, struct hl_hr_mmu_funcs *hr_func, u64 phys_hop_addr)
+{
+	hr_func->get_pgt_info(ctx, phys_hop_addr)->num_of_ptes++;
+}
+
+/**
+ * hl_mmu_hr_get_next_hop_pgt_info() - get pgt_info structure for the next HOP
+ * @ctx: pointer to the context structure.
+ * @hr_func: host resident functions.
+ * @curr_pte: current PTE value.
+ *
+ * @return pgt_info structure on success, otherwise NULL.
+ */
+struct pgt_info *hl_mmu_hr_get_next_hop_pgt_info(struct hl_ctx *ctx,
+							struct hl_hr_mmu_funcs *hr_func,
+							u64 curr_pte)
+{
+	u64 next_hop_phys_addr = hl_mmu_get_next_hop_addr(ctx, curr_pte);
+
+	if (next_hop_phys_addr == ULLONG_MAX)
+		return NULL;
+
+	return hr_func->get_pgt_info(ctx, next_hop_phys_addr);
+}
+
+/**
+ * hl_mmu_hr_alloc_hop() - allocate HOP
+ * @ctx: pointer to the context structure.
+ * @hr_priv: host resident private info structure.
+ * @hr_func: host resident functions.
+ * @mmu_prop: MMU properties.
+ *
+ * @return pgt_info structure associated with the allocated HOP on success, otherwise NULL.
+ */
+struct pgt_info *hl_mmu_hr_alloc_hop(struct hl_ctx *ctx, struct hl_mmu_hr_priv *hr_priv,
+							struct hl_hr_mmu_funcs *hr_func,
+							struct hl_mmu_properties *mmu_prop)
+{
+	struct hl_device *hdev = ctx->hdev;
+	struct pgt_info *pgt_info;
+	dma_addr_t phys_addr;
+	void *virt_addr;
+	int i, retry = 1;
+
+	pgt_info = kmalloc(sizeof(*pgt_info), GFP_KERNEL);
+	if (!pgt_info)
+		return NULL;
+
+	for (i = 0; i <= retry; i++) {
+		virt_addr = gen_pool_dma_zalloc_align(hr_priv->mmu_pgt_pool,
+							mmu_prop->hop_table_size,
+							&phys_addr,
+							mmu_prop->hop_table_size);
+		if (virt_addr)
+			break;
+
+		/* No memory in pool - get some and try again */
+		virt_addr = hl_asic_dma_alloc_coherent(hdev, SZ_2M, &phys_addr,
+							GFP_KERNEL | __GFP_ZERO);
+		if (ZERO_OR_NULL_PTR(virt_addr))
+			break;
+
+		if (gen_pool_add_virt(hr_priv->mmu_pgt_pool, (unsigned long)virt_addr,
+								phys_addr, SZ_2M, -1)) {
+			hl_asic_dma_free_coherent(hdev, SZ_2M, virt_addr, phys_addr);
+			virt_addr = NULL;
+			break;
+		}
+	}
+
+	if (ZERO_OR_NULL_PTR(virt_addr)) {
+		dev_err(hdev->dev, "failed to allocate page\n");
+		goto pool_alloc_err;
+	}
+
+	pgt_info->phys_addr = phys_addr;
+	pgt_info->shadow_addr = (unsigned long) NULL;
+	pgt_info->virt_addr = (unsigned long)virt_addr;
+	pgt_info->ctx = ctx;
+	pgt_info->num_of_ptes = 0;
+	hr_func->add_pgt_info(ctx, pgt_info, phys_addr);
+
+	return pgt_info;
+
+pool_alloc_err:
+	kfree(pgt_info);
+
+	return NULL;
+}
+
+/**
+ * hl_mmu_hr_get_alloc_next_hop() - get the next HOP, allocate it if it does not exist
+ * @ctx: pointer to the context structure.
+ * @hr_priv: host resident private info structure.
+ * @hr_func: host resident functions.
+ * @mmu_prop: MMU properties.
+ * @curr_pte: current PTE value.
+ * @is_new_hop: set to true if HOP is new (caller responsibility to set it to false).
+ *
+ * @return pgt_info structure associated with the allocated HOP on success, otherwise NULL.
+ */
+struct pgt_info *hl_mmu_hr_get_alloc_next_hop(struct hl_ctx *ctx,
+							struct hl_mmu_hr_priv *hr_priv,
+							struct hl_hr_mmu_funcs *hr_func,
+							struct hl_mmu_properties *mmu_prop,
+							u64 curr_pte, bool *is_new_hop)
+{
+	u64 hop_addr = hl_mmu_get_next_hop_addr(ctx, curr_pte);
+
+	if (hop_addr != ULLONG_MAX)
+		return hr_func->get_pgt_info(ctx, hop_addr);
+
+	*is_new_hop = true;
+	return hl_mmu_hr_alloc_hop(ctx, hr_priv, hr_func, mmu_prop);
+}
+
+/**
+ * hl_mmu_hr_get_tlb_info() - get the TLB info (info for a specific mapping)
+ * @ctx: pointer to the context structure.
+ * @virt_addr: the virt address for which to get info.
+ * @hops: HOPs info structure.
+ * @hr_func: host resident functions.
+ *
+ * @return 0 on success, otherwise non 0 error code..
+ */
+int hl_mmu_hr_get_tlb_info(struct hl_ctx *ctx, u64 virt_addr, struct hl_mmu_hop_info *hops,
+								struct hl_hr_mmu_funcs *hr_func)
+{
+	/* using 6 HOPs as this is the maximum number of HOPs */
+	struct pgt_info *hops_pgt_info[MMU_ARCH_6_HOPS] = { NULL };
+	struct hl_device *hdev = ctx->hdev;
+	struct hl_mmu_properties *mmu_prop;
+	int rc, i, used_hops;
+	bool is_huge;
+
+	rc = hr_func->get_tlb_mapping_params(hdev, &mmu_prop, hops, virt_addr, &is_huge);
+	if (rc)
+		return rc;
+
+	used_hops = mmu_prop->num_hops;
+
+	/* huge pages use one less hop */
+	if (is_huge)
+		used_hops--;
+
+	hops->scrambled_vaddr = hdev->asic_funcs->scramble_addr(hdev, virt_addr);
+
+	for (i = 0 ; i < used_hops ; i++) {
+		if (i == 0)
+			hops_pgt_info[i] = hr_func->get_hop0_pgt_info(ctx);
+		else
+			hops_pgt_info[i] = hl_mmu_hr_get_next_hop_pgt_info(ctx, hr_func,
+								hops->hop_info[i - 1].hop_pte_val);
+
+		if (!hops_pgt_info[i])
+			return -EFAULT;
+
+		hops->hop_info[i].hop_addr = hops_pgt_info[i]->phys_addr;
+		hops->hop_info[i].hop_pte_addr =
+				hl_mmu_get_hop_pte_phys_addr(ctx, mmu_prop, i,
+								hops->hop_info[i].hop_addr,
+								hops->scrambled_vaddr);
+		hops->hop_info[i].hop_pte_val = *(u64 *) (uintptr_t)
+						hl_mmu_hr_pte_phys_to_virt(ctx, hops_pgt_info[i],
+								hops->hop_info[i].hop_pte_addr,
+								mmu_prop->hop_table_size);
+
+		if (!(hops->hop_info[i].hop_pte_val & PAGE_PRESENT_MASK))
+			return -EFAULT;
+
+		if (hops->hop_info[i].hop_pte_val & mmu_prop->last_mask)
+			break;
+	}
+
+	/* if passed over all hops then no last hop was found */
+	if (i == mmu_prop->num_hops)
+		return -EFAULT;
+
+	if (hops->scrambled_vaddr != virt_addr)
+		hops->unscrambled_paddr = hdev->asic_funcs->descramble_addr
+				(hdev, hops->hop_info[i].hop_pte_val);
+	else
+		hops->unscrambled_paddr = hops->hop_info[i].hop_pte_val;
+
+	hops->used_hops = i + 1;
+
+	return 0;
+}
+
+struct pgt_info *hl_mmu_dr_get_pgt_info(struct hl_ctx *ctx, u64 hop_addr)
+{
+	struct pgt_info *pgt_info = NULL;
+
+	hash_for_each_possible(ctx->mmu_shadow_hash, pgt_info, node,
+			(unsigned long) hop_addr)
+		if (hop_addr == pgt_info->shadow_addr)
+			break;
+
+	return pgt_info;
+}
+
+void hl_mmu_dr_free_hop(struct hl_ctx *ctx, u64 hop_addr)
+{
+	struct pgt_info *pgt_info = hl_mmu_dr_get_pgt_info(ctx, hop_addr);
+
+	hl_mmu_dr_free_pgt_node(ctx, pgt_info);
+}
+
+void hl_mmu_dr_free_pgt_node(struct hl_ctx *ctx, struct pgt_info *pgt_info)
+{
+	struct hl_device *hdev = ctx->hdev;
+
+	gen_pool_free(hdev->mmu_priv.dr.mmu_pgt_pool, pgt_info->phys_addr,
+			hdev->asic_prop.dmmu.hop_table_size);
+	hash_del(&pgt_info->node);
+	kfree((u64 *) (uintptr_t) pgt_info->shadow_addr);
+	kfree(pgt_info);
+}
+
+u64 hl_mmu_dr_get_phys_hop0_addr(struct hl_ctx *ctx)
+{
+	return ctx->hdev->asic_prop.mmu_pgt_addr +
+			(ctx->asid * ctx->hdev->asic_prop.dmmu.hop_table_size);
+}
+
+u64 hl_mmu_dr_get_hop0_addr(struct hl_ctx *ctx)
+{
+	return (u64) (uintptr_t) ctx->hdev->mmu_priv.dr.mmu_shadow_hop0 +
+			(ctx->asid * ctx->hdev->asic_prop.dmmu.hop_table_size);
+}
+
+u64 hl_mmu_dr_get_phys_addr(struct hl_ctx *ctx, u64 shadow_addr)
+{
+	u64 page_mask = ctx->hdev->asic_prop.dmmu.hop_table_size - 1;
+	u64 shadow_hop_addr = shadow_addr & (~page_mask);
+	u64 pte_offset = shadow_addr & page_mask;
+	u64 phys_hop_addr;
+
+	if (shadow_hop_addr != hl_mmu_dr_get_hop0_addr(ctx))
+		phys_hop_addr = hl_mmu_dr_get_pgt_info(ctx, shadow_hop_addr)->phys_addr;
+	else
+		phys_hop_addr = hl_mmu_dr_get_phys_hop0_addr(ctx);
+
+	return phys_hop_addr + pte_offset;
+}
+
+void hl_mmu_dr_write_pte(struct hl_ctx *ctx, u64 shadow_pte_addr, u64 val)
+{
+	u64 phys_val = hl_mmu_dr_get_phys_addr(ctx, val);
+
+	ctx->hdev->asic_funcs->write_pte(ctx->hdev, hl_mmu_dr_get_phys_addr(ctx, shadow_pte_addr),
+					phys_val);
+
+	*(u64 *) (uintptr_t) shadow_pte_addr = val;
+}
+
+void hl_mmu_dr_write_final_pte(struct hl_ctx *ctx, u64 shadow_pte_addr, u64 val)
+{
+	ctx->hdev->asic_funcs->write_pte(ctx->hdev,
+				hl_mmu_dr_get_phys_addr(ctx, shadow_pte_addr), val);
+	*(u64 *) (uintptr_t) shadow_pte_addr = val;
+}
+
+void hl_mmu_dr_clear_pte(struct hl_ctx *ctx, u64 pte_addr)
+{
+	hl_mmu_dr_write_final_pte(ctx, pte_addr, 0);
+}
+
+void hl_mmu_dr_get_pte(struct hl_ctx *ctx, u64 hop_addr)
+{
+	hl_mmu_dr_get_pgt_info(ctx, hop_addr)->num_of_ptes++;
+}
+
+int hl_mmu_dr_put_pte(struct hl_ctx *ctx, u64 hop_addr)
+{
+	struct pgt_info *pgt_info = hl_mmu_dr_get_pgt_info(ctx, hop_addr);
+	int num_of_ptes_left;
+
+	pgt_info->num_of_ptes--;
+
+	/*
+	 * Need to save the number of ptes left because hl_mmu_free_hop might free
+	 * the pgt_info
+	 */
+	num_of_ptes_left = pgt_info->num_of_ptes;
+	if (!num_of_ptes_left)
+		hl_mmu_dr_free_pgt_node(ctx, pgt_info);
+
+	return num_of_ptes_left;
+}
+
+u64 hl_mmu_dr_alloc_hop(struct hl_ctx *ctx)
+{
+	struct hl_device *hdev = ctx->hdev;
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct pgt_info *pgt_info;
+	u64 phys_addr, shadow_addr;
+
+	pgt_info = kmalloc(sizeof(*pgt_info), GFP_KERNEL);
+	if (!pgt_info)
+		return ULLONG_MAX;
+
+	phys_addr = (u64) gen_pool_alloc(hdev->mmu_priv.dr.mmu_pgt_pool,
+					prop->dmmu.hop_table_size);
+	if (!phys_addr) {
+		dev_err(hdev->dev, "failed to allocate page\n");
+		goto pool_add_err;
+	}
+
+	shadow_addr = (u64) (uintptr_t) kzalloc(prop->dmmu.hop_table_size,
+						GFP_KERNEL);
+	if (!shadow_addr)
+		goto shadow_err;
+
+	pgt_info->phys_addr = phys_addr;
+	pgt_info->shadow_addr = shadow_addr;
+	pgt_info->ctx = ctx;
+	pgt_info->num_of_ptes = 0;
+	hash_add(ctx->mmu_shadow_hash, &pgt_info->node, shadow_addr);
+
+	return shadow_addr;
+
+shadow_err:
+	gen_pool_free(hdev->mmu_priv.dr.mmu_pgt_pool,
+			phys_addr, prop->dmmu.hop_table_size);
+pool_add_err:
+	kfree(pgt_info);
+
+	return ULLONG_MAX;
+}
+
+u64 hl_mmu_dr_get_alloc_next_hop_addr(struct hl_ctx *ctx, u64 curr_pte, bool *is_new_hop)
+{
+	u64 hop_addr = hl_mmu_get_next_hop_addr(ctx, curr_pte);
+
+	if (hop_addr == ULLONG_MAX) {
+		hop_addr = hl_mmu_dr_alloc_hop(ctx);
+		*is_new_hop = (hop_addr != ULLONG_MAX);
+	}
+
+	return hop_addr;
+}
+
+void hl_mmu_dr_flush(struct hl_ctx *ctx)
+{
+	/* flush all writes from all cores to reach PCI */
+	mb();
+	ctx->hdev->asic_funcs->read_pte(ctx->hdev, hl_mmu_dr_get_phys_hop0_addr(ctx));
+}
+
+int hl_mmu_dr_init(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	int rc;
+
+	hdev->mmu_priv.dr.mmu_pgt_pool =
+			gen_pool_create(__ffs(prop->dmmu.hop_table_size), -1);
+
+	if (!hdev->mmu_priv.dr.mmu_pgt_pool) {
+		dev_err(hdev->dev, "Failed to create page gen pool\n");
+		return -ENOMEM;
+	}
+
+	rc = gen_pool_add(hdev->mmu_priv.dr.mmu_pgt_pool, prop->mmu_pgt_addr +
+			prop->dmmu.hop0_tables_total_size,
+			prop->dmmu.pgt_size - prop->dmmu.hop0_tables_total_size,
+			-1);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to add memory to page gen pool\n");
+		goto err_pool_add;
+	}
+
+	hdev->mmu_priv.dr.mmu_shadow_hop0 = kvcalloc(prop->max_asid,
+						prop->dmmu.hop_table_size, GFP_KERNEL);
+	if (ZERO_OR_NULL_PTR(hdev->mmu_priv.dr.mmu_shadow_hop0)) {
+		rc = -ENOMEM;
+		goto err_pool_add;
+	}
+
+	/* MMU H/W init will be done in device hw_init() */
+
+	return 0;
+
+err_pool_add:
+	gen_pool_destroy(hdev->mmu_priv.dr.mmu_pgt_pool);
+
+	return rc;
+}
+
+void hl_mmu_dr_fini(struct hl_device *hdev)
+{
+	/* MMU H/W fini was already done in device hw_fini() */
+
+	if (ZERO_OR_NULL_PTR(hdev->mmu_priv.dr.mmu_shadow_hop0))
+		return;
+
+	kvfree(hdev->mmu_priv.dr.mmu_shadow_hop0);
+	gen_pool_destroy(hdev->mmu_priv.dr.mmu_pgt_pool);
+
+	/* Make sure that if we arrive here again without init was
+	 * called we won't cause kernel panic. This can happen for
+	 * example if we fail during hard reset code at certain points
+	 */
+	hdev->mmu_priv.dr.mmu_shadow_hop0 = NULL;
+}
diff --git a/drivers/accel/habanalabs/common/mmu/mmu_v1.c b/drivers/accel/habanalabs/common/mmu/mmu_v1.c
new file mode 100644
index 000000000000..845d16aaa637
--- /dev/null
+++ b/drivers/accel/habanalabs/common/mmu/mmu_v1.c
@@ -0,0 +1,550 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Copyright 2016-2019 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ */
+
+#include "../habanalabs.h"
+#include "../../include/hw_ip/mmu/mmu_general.h"
+
+#include <linux/slab.h>
+
+#define MMU_V1_MAX_HOPS	(MMU_HOP4 + 1)
+
+static inline u64 get_hop_pte_addr(struct hl_ctx *ctx, struct hl_mmu_properties *mmu_prop,
+					u64 *hop_addr_arr, u64 virt_addr, enum mmu_hop_num hop_idx)
+{
+	u64 mask, shift;
+
+	mask = mmu_prop->hop_masks[hop_idx];
+	shift = mmu_prop->hop_shifts[hop_idx];
+	return hop_addr_arr[hop_idx] +
+			ctx->hdev->asic_prop.mmu_pte_size * ((virt_addr & mask) >> shift);
+}
+
+static int dram_default_mapping_init(struct hl_ctx *ctx)
+{
+	struct hl_device *hdev = ctx->hdev;
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	u64 num_of_hop3, total_hops, hop0_addr, hop1_addr, hop2_addr,
+		hop2_pte_addr, hop3_pte_addr, pte_val;
+	int rc, i, j, hop3_allocated = 0;
+
+	if ((!prop->dram_supports_virtual_memory) ||
+			(!hdev->dram_default_page_mapping) ||
+			(ctx->asid == HL_KERNEL_ASID_ID))
+		return 0;
+
+	num_of_hop3 = prop->dram_size_for_default_page_mapping;
+	do_div(num_of_hop3, prop->dram_page_size);
+	do_div(num_of_hop3, HOP_PTE_ENTRIES_512);
+
+	/* add hop1 and hop2 */
+	total_hops = num_of_hop3 + 2;
+
+	ctx->dram_default_hops = kcalloc(total_hops, HL_PTE_SIZE,  GFP_KERNEL);
+	if (!ctx->dram_default_hops)
+		return -ENOMEM;
+
+	hop0_addr = hl_mmu_dr_get_hop0_addr(ctx);
+
+	hop1_addr = hl_mmu_dr_alloc_hop(ctx);
+	if (hop1_addr == ULLONG_MAX) {
+		dev_err(hdev->dev, "failed to alloc hop 1\n");
+		rc = -ENOMEM;
+		goto hop1_err;
+	}
+
+	ctx->dram_default_hops[total_hops - 1] = hop1_addr;
+
+	hop2_addr = hl_mmu_dr_alloc_hop(ctx);
+	if (hop2_addr == ULLONG_MAX) {
+		dev_err(hdev->dev, "failed to alloc hop 2\n");
+		rc = -ENOMEM;
+		goto hop2_err;
+	}
+
+	ctx->dram_default_hops[total_hops - 2] = hop2_addr;
+
+	for (i = 0 ; i < num_of_hop3 ; i++) {
+		ctx->dram_default_hops[i] = hl_mmu_dr_alloc_hop(ctx);
+		if (ctx->dram_default_hops[i] == ULLONG_MAX) {
+			dev_err(hdev->dev, "failed to alloc hop 3, i: %d\n", i);
+			rc = -ENOMEM;
+			goto hop3_err;
+		}
+		hop3_allocated++;
+	}
+
+	/* need only pte 0 in hops 0 and 1 */
+	pte_val = (hop1_addr & HOP_PHYS_ADDR_MASK) | PAGE_PRESENT_MASK;
+	hl_mmu_dr_write_pte(ctx, hop0_addr, pte_val);
+
+	pte_val = (hop2_addr & HOP_PHYS_ADDR_MASK) | PAGE_PRESENT_MASK;
+	hl_mmu_dr_write_pte(ctx, hop1_addr, pte_val);
+	hl_mmu_dr_get_pte(ctx, hop1_addr);
+
+	hop2_pte_addr = hop2_addr;
+	for (i = 0 ; i < num_of_hop3 ; i++) {
+		pte_val = (ctx->dram_default_hops[i] & HOP_PHYS_ADDR_MASK) |
+				PAGE_PRESENT_MASK;
+		hl_mmu_dr_write_pte(ctx, hop2_pte_addr, pte_val);
+		hl_mmu_dr_get_pte(ctx, hop2_addr);
+		hop2_pte_addr += HL_PTE_SIZE;
+	}
+
+	pte_val = (prop->mmu_dram_default_page_addr & HOP_PHYS_ADDR_MASK) |
+			LAST_MASK | PAGE_PRESENT_MASK;
+
+	for (i = 0 ; i < num_of_hop3 ; i++) {
+		hop3_pte_addr = ctx->dram_default_hops[i];
+		for (j = 0 ; j < HOP_PTE_ENTRIES_512 ; j++) {
+			hl_mmu_dr_write_final_pte(ctx, hop3_pte_addr, pte_val);
+			hl_mmu_dr_get_pte(ctx, ctx->dram_default_hops[i]);
+			hop3_pte_addr += HL_PTE_SIZE;
+		}
+	}
+
+	hl_mmu_dr_flush(ctx);
+
+	return 0;
+
+hop3_err:
+	for (i = 0 ; i < hop3_allocated ; i++)
+		hl_mmu_dr_free_hop(ctx, ctx->dram_default_hops[i]);
+
+	hl_mmu_dr_free_hop(ctx, hop2_addr);
+hop2_err:
+	hl_mmu_dr_free_hop(ctx, hop1_addr);
+hop1_err:
+	kfree(ctx->dram_default_hops);
+
+	return rc;
+}
+
+static void dram_default_mapping_fini(struct hl_ctx *ctx)
+{
+	struct hl_device *hdev = ctx->hdev;
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	u64 num_of_hop3, total_hops, hop0_addr, hop1_addr, hop2_addr,
+		hop2_pte_addr, hop3_pte_addr;
+	int i, j;
+
+	if ((!prop->dram_supports_virtual_memory) ||
+			(!hdev->dram_default_page_mapping) ||
+			(ctx->asid == HL_KERNEL_ASID_ID))
+		return;
+
+	num_of_hop3 = prop->dram_size_for_default_page_mapping;
+	do_div(num_of_hop3, prop->dram_page_size);
+	do_div(num_of_hop3, HOP_PTE_ENTRIES_512);
+
+	hop0_addr = hl_mmu_dr_get_hop0_addr(ctx);
+	/* add hop1 and hop2 */
+	total_hops = num_of_hop3 + 2;
+	hop1_addr = ctx->dram_default_hops[total_hops - 1];
+	hop2_addr = ctx->dram_default_hops[total_hops - 2];
+
+	for (i = 0 ; i < num_of_hop3 ; i++) {
+		hop3_pte_addr = ctx->dram_default_hops[i];
+		for (j = 0 ; j < HOP_PTE_ENTRIES_512 ; j++) {
+			hl_mmu_dr_clear_pte(ctx, hop3_pte_addr);
+			hl_mmu_dr_put_pte(ctx, ctx->dram_default_hops[i]);
+			hop3_pte_addr += HL_PTE_SIZE;
+		}
+	}
+
+	hop2_pte_addr = hop2_addr;
+	for (i = 0 ; i < num_of_hop3 ; i++) {
+		hl_mmu_dr_clear_pte(ctx, hop2_pte_addr);
+		hl_mmu_dr_put_pte(ctx, hop2_addr);
+		hop2_pte_addr += HL_PTE_SIZE;
+	}
+
+	hl_mmu_dr_clear_pte(ctx, hop1_addr);
+	hl_mmu_dr_put_pte(ctx, hop1_addr);
+	hl_mmu_dr_clear_pte(ctx, hop0_addr);
+
+	kfree(ctx->dram_default_hops);
+
+	hl_mmu_dr_flush(ctx);
+}
+
+/**
+ * hl_mmu_v1_ctx_init() - initialize a context for using the MMU module.
+ * @ctx: pointer to the context structure to initialize.
+ *
+ * Initialize a mutex to protect the concurrent mapping flow, a hash to hold all
+ * page tables hops related to this context.
+ * Return: 0 on success, non-zero otherwise.
+ */
+static int hl_mmu_v1_ctx_init(struct hl_ctx *ctx)
+{
+	hash_init(ctx->mmu_shadow_hash);
+	return dram_default_mapping_init(ctx);
+}
+
+/*
+ * hl_mmu_ctx_fini - disable a ctx from using the mmu module
+ *
+ * @ctx: pointer to the context structure
+ *
+ * This function does the following:
+ * - Free any pgts which were not freed yet
+ * - Free the mutex
+ * - Free DRAM default page mapping hops
+ */
+static void hl_mmu_v1_ctx_fini(struct hl_ctx *ctx)
+{
+	struct hl_device *hdev = ctx->hdev;
+	struct pgt_info *pgt_info;
+	struct hlist_node *tmp;
+	int i;
+
+	dram_default_mapping_fini(ctx);
+
+	if (!hash_empty(ctx->mmu_shadow_hash))
+		dev_err(hdev->dev, "ctx %d is freed while it has pgts in use\n",
+			ctx->asid);
+
+	hash_for_each_safe(ctx->mmu_shadow_hash, i, tmp, pgt_info, node) {
+		dev_err_ratelimited(hdev->dev,
+			"pgt_info of addr 0x%llx of asid %d was not destroyed, num_ptes: %d\n",
+			pgt_info->phys_addr, ctx->asid, pgt_info->num_of_ptes);
+		hl_mmu_dr_free_pgt_node(ctx, pgt_info);
+	}
+}
+
+static int hl_mmu_v1_unmap(struct hl_ctx *ctx,
+				u64 virt_addr, bool is_dram_addr)
+{
+	u64 hop_addr[MMU_V1_MAX_HOPS] = {0}, hop_pte_addr[MMU_V1_MAX_HOPS] = {0}, curr_pte = 0;
+	struct hl_device *hdev = ctx->hdev;
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct hl_mmu_properties *mmu_prop;
+	bool is_huge, clear_hop3 = true;
+	int hop_idx;
+
+	/* shifts and masks are the same in PMMU and HPMMU, use one of them */
+	mmu_prop = is_dram_addr ? &prop->dmmu : &prop->pmmu;
+
+	for (hop_idx = MMU_HOP0; hop_idx < MMU_HOP4; hop_idx++) {
+		if (hop_idx == MMU_HOP0) {
+			hop_addr[hop_idx] = hl_mmu_dr_get_hop0_addr(ctx);
+		} else {
+			hop_addr[hop_idx] = hl_mmu_get_next_hop_addr(ctx, curr_pte);
+			if (hop_addr[hop_idx] == ULLONG_MAX)
+				goto not_mapped;
+		}
+
+		hop_pte_addr[hop_idx] =
+				get_hop_pte_addr(ctx, mmu_prop, hop_addr, virt_addr, hop_idx);
+
+		curr_pte = *(u64 *) (uintptr_t) hop_pte_addr[hop_idx];
+	}
+
+	is_huge = curr_pte & mmu_prop->last_mask;
+
+	if (is_dram_addr && !is_huge) {
+		dev_err(hdev->dev, "DRAM unmapping should use huge pages only\n");
+		return -EFAULT;
+	}
+
+	if (!is_huge) {
+		hop_idx = MMU_HOP4;
+		hop_addr[hop_idx] = hl_mmu_get_next_hop_addr(ctx, curr_pte);
+		if (hop_addr[hop_idx] == ULLONG_MAX)
+			goto not_mapped;
+
+		hop_pte_addr[hop_idx] =
+				get_hop_pte_addr(ctx, mmu_prop, hop_addr, virt_addr, hop_idx);
+		curr_pte = *(u64 *) (uintptr_t) hop_pte_addr[hop_idx];
+		clear_hop3 = false;
+	}
+
+	if (hdev->dram_default_page_mapping && is_dram_addr) {
+		u64 default_pte = (prop->mmu_dram_default_page_addr &
+				HOP_PHYS_ADDR_MASK) | mmu_prop->last_mask |
+					PAGE_PRESENT_MASK;
+		if (curr_pte == default_pte) {
+			dev_err(hdev->dev,
+				"DRAM: hop3 PTE points to zero page, can't unmap, va: 0x%llx\n",
+					virt_addr);
+			goto not_mapped;
+		}
+
+		if (!(curr_pte & PAGE_PRESENT_MASK)) {
+			dev_err(hdev->dev,
+				"DRAM: hop3 PTE is cleared! can't unmap, va: 0x%llx\n",
+					virt_addr);
+			goto not_mapped;
+		}
+
+		hop_idx = MMU_HOP3;
+		hl_mmu_dr_write_final_pte(ctx, hop_pte_addr[hop_idx], default_pte);
+		hl_mmu_dr_put_pte(ctx, hop_addr[hop_idx]);
+	} else {
+		if (!(curr_pte & PAGE_PRESENT_MASK))
+			goto not_mapped;
+
+		if (hop_addr[MMU_HOP4])
+			hl_mmu_dr_clear_pte(ctx, hop_pte_addr[MMU_HOP4]);
+		else
+			hl_mmu_dr_clear_pte(ctx, hop_pte_addr[MMU_HOP3]);
+
+		if (hop_addr[MMU_HOP4] && !hl_mmu_dr_put_pte(ctx, hop_addr[MMU_HOP4]))
+			clear_hop3 = true;
+
+		if (!clear_hop3)
+			goto mapped;
+
+		for (hop_idx = MMU_HOP3; hop_idx >= 0; hop_idx--) {
+			hl_mmu_dr_clear_pte(ctx, hop_pte_addr[hop_idx]);
+
+			if (hop_idx == MMU_HOP0)
+				break;
+
+			if (hl_mmu_dr_put_pte(ctx, hop_addr[hop_idx]))
+				goto mapped;
+		}
+	}
+
+mapped:
+	return 0;
+
+not_mapped:
+	dev_err(hdev->dev, "virt addr 0x%llx is not mapped to phys addr\n",
+		virt_addr);
+
+	return -EINVAL;
+}
+
+static int hl_mmu_v1_map(struct hl_ctx *ctx, u64 virt_addr, u64 phys_addr,
+			u32 page_size, bool is_dram_addr)
+{
+	u64 hop_addr[MMU_V1_MAX_HOPS] = {0}, hop_pte_addr[MMU_V1_MAX_HOPS] = {0}, curr_pte = 0;
+	struct hl_device *hdev = ctx->hdev;
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct hl_mmu_properties *mmu_prop;
+	bool is_huge, hop_new[MMU_V1_MAX_HOPS] = {false};
+	int num_hops, hop_idx, prev_hop, rc = -ENOMEM;
+
+	/*
+	 * This mapping function can map a page or a huge page. For huge page
+	 * there are only 3 hops rather than 4. Currently the DRAM allocation
+	 * uses huge pages only but user memory could have been allocated with
+	 * one of the two page sizes. Since this is a common code for all the
+	 * three cases, we need this hugs page check.
+	 */
+	if (is_dram_addr) {
+		mmu_prop = &prop->dmmu;
+		is_huge = true;
+	} else if (page_size == prop->pmmu_huge.page_size) {
+		mmu_prop = &prop->pmmu_huge;
+		is_huge = true;
+	} else {
+		mmu_prop = &prop->pmmu;
+		is_huge = false;
+	}
+
+	num_hops = is_huge ? (MMU_V1_MAX_HOPS - 1) : MMU_V1_MAX_HOPS;
+
+	for (hop_idx = MMU_HOP0; hop_idx < num_hops; hop_idx++) {
+		if (hop_idx == MMU_HOP0) {
+			hop_addr[hop_idx] = hl_mmu_dr_get_hop0_addr(ctx);
+		} else {
+			hop_addr[hop_idx] =
+				hl_mmu_dr_get_alloc_next_hop_addr(ctx, curr_pte, &hop_new[hop_idx]);
+			if (hop_addr[hop_idx] == ULLONG_MAX)
+				goto err;
+		}
+
+		hop_pte_addr[hop_idx] =
+				get_hop_pte_addr(ctx, mmu_prop, hop_addr, virt_addr, hop_idx);
+		curr_pte = *(u64 *) (uintptr_t) hop_pte_addr[hop_idx];
+	}
+
+	if (hdev->dram_default_page_mapping && is_dram_addr) {
+		u64 default_pte = (prop->mmu_dram_default_page_addr &
+					HOP_PHYS_ADDR_MASK) | mmu_prop->last_mask |
+						PAGE_PRESENT_MASK;
+
+		if (curr_pte != default_pte) {
+			dev_err(hdev->dev,
+				"DRAM: mapping already exists for virt_addr 0x%llx\n",
+					virt_addr);
+			rc = -EINVAL;
+			goto err;
+		}
+
+		for (hop_idx = MMU_HOP1; hop_idx < num_hops; hop_idx++) {
+			if (hop_new[hop_idx]) {
+				dev_err(hdev->dev, "DRAM mapping should not allocate more hops\n");
+				rc = -EFAULT;
+				goto err;
+			}
+		}
+	} else if (curr_pte & PAGE_PRESENT_MASK) {
+		dev_err(hdev->dev,
+			"mapping already exists for virt_addr 0x%llx\n",
+				virt_addr);
+
+		for (hop_idx = MMU_HOP0; hop_idx < num_hops; hop_idx++)
+			dev_dbg(hdev->dev, "hop%d pte: 0x%llx (0x%llx)\n", hop_idx,
+					*(u64 *) (uintptr_t) hop_pte_addr[hop_idx],
+					hop_pte_addr[hop_idx]);
+
+		rc = -EINVAL;
+		goto err;
+	}
+
+	curr_pte = (phys_addr & HOP_PHYS_ADDR_MASK) | mmu_prop->last_mask
+			| PAGE_PRESENT_MASK;
+
+	hl_mmu_dr_write_final_pte(ctx, hop_pte_addr[num_hops - 1], curr_pte);
+
+	for (hop_idx = MMU_HOP1; hop_idx < num_hops; hop_idx++) {
+		prev_hop = hop_idx - 1;
+
+		if (hop_new[hop_idx]) {
+			curr_pte = (hop_addr[hop_idx] & HOP_PHYS_ADDR_MASK) | PAGE_PRESENT_MASK;
+			hl_mmu_dr_write_pte(ctx, hop_pte_addr[prev_hop], curr_pte);
+			if (hop_idx != MMU_HOP1)
+				hl_mmu_dr_get_pte(ctx, hop_addr[prev_hop]);
+		}
+	}
+
+	hl_mmu_dr_get_pte(ctx, hop_addr[num_hops - 1]);
+
+	return 0;
+
+err:
+	for (hop_idx = num_hops; hop_idx > MMU_HOP0; hop_idx--) {
+		if (hop_new[hop_idx])
+			hl_mmu_dr_free_hop(ctx, hop_addr[hop_idx]);
+	}
+
+	return rc;
+}
+
+/*
+ * hl_mmu_v1_swap_out - marks all mapping of the given ctx as swapped out
+ *
+ * @ctx: pointer to the context structure
+ *
+ */
+static void hl_mmu_v1_swap_out(struct hl_ctx *ctx)
+{
+
+}
+
+/*
+ * hl_mmu_v1_swap_in - marks all mapping of the given ctx as swapped in
+ *
+ * @ctx: pointer to the context structure
+ *
+ */
+static void hl_mmu_v1_swap_in(struct hl_ctx *ctx)
+{
+
+}
+
+static int hl_mmu_v1_get_tlb_info(struct hl_ctx *ctx, u64 virt_addr,
+				struct hl_mmu_hop_info *hops)
+{
+	struct hl_device *hdev = ctx->hdev;
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct hl_mmu_properties *mmu_prop;
+	bool is_dram_addr, is_pmmu_addr, is_pmmu_h_addr, is_huge;
+	int i, used_hops;
+
+	is_dram_addr = hl_mem_area_inside_range(virt_addr, prop->dmmu.page_size,
+						prop->dmmu.start_addr,
+						prop->dmmu.end_addr);
+	is_pmmu_addr = hl_mem_area_inside_range(virt_addr, prop->pmmu.page_size,
+						prop->pmmu.start_addr,
+						prop->pmmu.end_addr);
+	is_pmmu_h_addr = hl_mem_area_inside_range(virt_addr,
+						prop->pmmu_huge.page_size,
+						prop->pmmu_huge.start_addr,
+						prop->pmmu_huge.end_addr);
+	if (is_dram_addr) {
+		mmu_prop = &prop->dmmu;
+		is_huge = true;
+	} else if (is_pmmu_addr) {
+		mmu_prop = &prop->pmmu;
+		is_huge = false;
+	} else if (is_pmmu_h_addr) {
+		mmu_prop = &prop->pmmu_huge;
+		is_huge = true;
+	} else {
+		return -EINVAL;
+	}
+
+	used_hops = mmu_prop->num_hops;
+
+	/* huge pages use lesser hops */
+	if (is_huge)
+		used_hops--;
+
+	hops->hop_info[0].hop_addr = hl_mmu_dr_get_phys_hop0_addr(ctx);
+	hops->hop_info[0].hop_pte_addr =
+			hl_mmu_get_hop_pte_phys_addr(ctx, mmu_prop, 0,
+					hops->hop_info[0].hop_addr, virt_addr);
+	hops->hop_info[0].hop_pte_val =
+			hdev->asic_funcs->read_pte(hdev,
+						hops->hop_info[0].hop_pte_addr);
+
+	for (i = 1 ; i < used_hops ; i++) {
+		hops->hop_info[i].hop_addr =
+			hl_mmu_get_next_hop_addr(ctx,
+					hops->hop_info[i - 1].hop_pte_val);
+		if (hops->hop_info[i].hop_addr == ULLONG_MAX)
+			return -EFAULT;
+
+		hops->hop_info[i].hop_pte_addr =
+				hl_mmu_get_hop_pte_phys_addr(ctx, mmu_prop, i,
+						hops->hop_info[i].hop_addr,
+						virt_addr);
+		hops->hop_info[i].hop_pte_val =
+				hdev->asic_funcs->read_pte(hdev,
+						hops->hop_info[i].hop_pte_addr);
+
+		if (!(hops->hop_info[i].hop_pte_val & PAGE_PRESENT_MASK))
+			return -EFAULT;
+
+		if (hops->hop_info[i].hop_pte_val & mmu_prop->last_mask)
+			break;
+	}
+
+	/* if passed over all hops then no last hop was found */
+	if (i == mmu_prop->num_hops)
+		return -EFAULT;
+
+	if (!(hops->hop_info[i].hop_pte_val & PAGE_PRESENT_MASK))
+		return -EFAULT;
+
+	hops->used_hops = i + 1;
+
+	return 0;
+}
+
+/*
+ * hl_mmu_v1_prepare - prepare mmu  for working with mmu v1
+ *
+ * @hdev: pointer to the device structure
+ */
+void hl_mmu_v1_set_funcs(struct hl_device *hdev, struct hl_mmu_funcs *mmu)
+{
+	mmu->init = hl_mmu_dr_init;
+	mmu->fini = hl_mmu_dr_fini;
+	mmu->ctx_init = hl_mmu_v1_ctx_init;
+	mmu->ctx_fini = hl_mmu_v1_ctx_fini;
+	mmu->map = hl_mmu_v1_map;
+	mmu->unmap = hl_mmu_v1_unmap;
+	mmu->flush = hl_mmu_dr_flush;
+	mmu->swap_out = hl_mmu_v1_swap_out;
+	mmu->swap_in = hl_mmu_v1_swap_in;
+	mmu->get_tlb_info = hl_mmu_v1_get_tlb_info;
+}
diff --git a/drivers/accel/habanalabs/common/mmu/mmu_v2.c b/drivers/accel/habanalabs/common/mmu/mmu_v2.c
new file mode 100644
index 000000000000..4bc0268fff1c
--- /dev/null
+++ b/drivers/accel/habanalabs/common/mmu/mmu_v2.c
@@ -0,0 +1,338 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ */
+
+#include "../habanalabs.h"
+#include "../../include/hw_ip/mmu/mmu_general.h"
+#include "../../include/hw_ip/mmu/mmu_v2_0.h"
+
+#include <linux/slab.h>
+
+/**
+ * hl_mmu_v2_ctx_init() - initialize a context for using the MMU module.
+ * @ctx: pointer to the context structure to initialize.
+ *
+ * Initialize a mutex to protect the concurrent mapping flow, a hash to hold all
+ * page tables hops related to this context.
+ * Return: 0 on success, non-zero otherwise.
+ */
+static int hl_mmu_v2_ctx_init(struct hl_ctx *ctx)
+{
+	hash_init(ctx->mmu_shadow_hash);
+
+	return 0;
+}
+
+/*
+ * hl_mmu_v2_ctx_fini - disable a ctx from using the mmu module
+ *
+ * @ctx: pointer to the context structure
+ *
+ * This function does the following:
+ * - Free any pgts which were not freed yet
+ * - Free the mutex
+ * - Free DRAM default page mapping hops
+ */
+static void hl_mmu_v2_ctx_fini(struct hl_ctx *ctx)
+{
+	struct hl_device *hdev = ctx->hdev;
+	struct pgt_info *pgt_info;
+	struct hlist_node *tmp;
+	int i;
+
+	if (!hash_empty(ctx->mmu_shadow_hash))
+		dev_err(hdev->dev, "ctx %d is freed while it has pgts in use\n",
+			ctx->asid);
+
+	hash_for_each_safe(ctx->mmu_shadow_hash, i, tmp, pgt_info, node) {
+		dev_err_ratelimited(hdev->dev,
+			"pgt_info of addr 0x%llx of asid %d was not destroyed, num_ptes: %d\n",
+			pgt_info->phys_addr, ctx->asid, pgt_info->num_of_ptes);
+		hl_mmu_dr_free_pgt_node(ctx, pgt_info);
+	}
+}
+
+static int hl_mmu_v2_unmap(struct hl_ctx *ctx,	u64 virt_addr, bool is_dram_addr)
+{
+	u64 hop_addr[MMU_ARCH_6_HOPS] = { 0 }, hop_pte_addr[MMU_ARCH_6_HOPS] = { 0 }, curr_pte,
+							scrambled_virt_addr;
+	struct asic_fixed_properties *prop = &ctx->hdev->asic_prop;
+	struct hl_device *hdev = ctx->hdev;
+	struct hl_mmu_properties *mmu_prop;
+	bool is_huge = false;
+	int i, hop_last;
+
+	/* device resident in V2 are allowed only for HMMU */
+	if (!is_dram_addr)
+		return -EINVAL;
+
+	mmu_prop = &prop->dmmu;
+
+	hop_last = mmu_prop->num_hops - 1;
+
+	scrambled_virt_addr = hdev->asic_funcs->scramble_addr(hdev, virt_addr);
+
+	hop_addr[0] = hl_mmu_dr_get_hop0_addr(ctx);
+	hop_pte_addr[0] = hl_mmu_get_hop_pte_phys_addr(ctx, mmu_prop, 0,
+					hop_addr[0], scrambled_virt_addr);
+	if (hop_pte_addr[0] == U64_MAX)
+		return -EFAULT;
+
+	curr_pte = *(u64 *) (uintptr_t) hop_pte_addr[0];
+
+	for (i = 1 ; i < mmu_prop->num_hops ; i++) {
+		hop_addr[i] = hl_mmu_get_next_hop_addr(ctx, curr_pte);
+		if (hop_addr[i] == ULLONG_MAX)
+			goto not_mapped;
+
+		hop_pte_addr[i] = hl_mmu_get_hop_pte_phys_addr(ctx, mmu_prop, i,
+					hop_addr[i], scrambled_virt_addr);
+		if (hop_pte_addr[i] == U64_MAX)
+			return -EFAULT;
+
+		curr_pte = *(u64 *) (uintptr_t) hop_pte_addr[i];
+
+		if ((i <= hop_last) && (curr_pte & mmu_prop->last_mask)) {
+			hop_last = i;
+			is_huge = true;
+			break;
+		}
+	}
+
+	if (is_dram_addr && !is_huge) {
+		dev_err(hdev->dev, "DRAM unmapping should use huge pages only\n");
+		return -EFAULT;
+	}
+
+	if (!(curr_pte & PAGE_PRESENT_MASK))
+		goto not_mapped;
+
+	for (i = hop_last ; i > 0 ; i--) {
+		hl_mmu_dr_clear_pte(ctx, hop_pte_addr[i]);
+		if (hl_mmu_dr_put_pte(ctx, hop_addr[i]))
+			goto mapped;
+	}
+	hl_mmu_dr_clear_pte(ctx, hop_pte_addr[0]);
+
+mapped:
+	return 0;
+
+not_mapped:
+	dev_err(hdev->dev, "virt addr 0x%llx is not mapped to phys addr\n",
+		virt_addr);
+
+	return -EINVAL;
+}
+
+static int hl_mmu_v2_map(struct hl_ctx *ctx, u64 virt_addr, u64 phys_addr,
+							u32 page_size, bool is_dram_addr)
+{
+	u64 hop_addr[MMU_ARCH_6_HOPS] = { 0 }, hop_pte_addr[MMU_ARCH_6_HOPS] = { 0 },
+			curr_pte = 0, scrambled_virt_addr, scrambled_phys_addr;
+	struct asic_fixed_properties *prop = &ctx->hdev->asic_prop;
+	bool hop_new[MMU_ARCH_6_HOPS] = { false };
+	struct hl_device *hdev = ctx->hdev;
+	struct hl_mmu_properties *mmu_prop;
+	int rc, i, hop_last;
+
+	/* device resident in V2 are allowed only for HMMU */
+	if (!is_dram_addr)
+		return -EINVAL;
+
+	mmu_prop = &prop->dmmu;
+
+	hop_last = mmu_prop->num_hops - 1;
+
+	scrambled_virt_addr = hdev->asic_funcs->scramble_addr(hdev, virt_addr);
+	scrambled_phys_addr = hdev->asic_funcs->scramble_addr(hdev, phys_addr);
+
+	/* First hop is preallocated therefore it is treated differently  */
+	hop_addr[0] = hl_mmu_dr_get_hop0_addr(ctx);
+	hop_pte_addr[0] = hl_mmu_get_hop_pte_phys_addr(ctx, mmu_prop, 0,
+						hop_addr[0], scrambled_virt_addr);
+	curr_pte = *(u64 *) (uintptr_t) hop_pte_addr[0];
+
+	/* Handle hop1 to hop_last */
+	for (i = 1 ; i <= hop_last ; i++) {
+		hop_addr[i] = hl_mmu_dr_get_alloc_next_hop_addr(ctx, curr_pte, &hop_new[i]);
+		if (hop_addr[i] == ULLONG_MAX) {
+			rc = -ENOMEM;
+			goto err;
+		}
+
+		hop_pte_addr[i] = hl_mmu_get_hop_pte_phys_addr(ctx, mmu_prop, i,
+					hop_addr[i], scrambled_virt_addr);
+		if (hop_pte_addr[i] == U64_MAX) {
+			rc = -EINVAL;
+			goto err;
+		}
+
+		if (!hop_pte_addr[i]) {
+			rc = -EINVAL;
+			goto err;
+		}
+
+		curr_pte = *(u64 *) (uintptr_t) hop_pte_addr[i];
+	}
+
+	if (curr_pte & PAGE_PRESENT_MASK) {
+		dev_err(hdev->dev,
+			"mapping already exists for virt_addr 0x%llx\n",
+				virt_addr);
+
+		for (i = 0 ; i <= hop_last ; i++)
+			dev_dbg(hdev->dev, "hop%d pte: 0x%llx (0x%llx)\n",
+				i, *(u64 *) (uintptr_t) hop_pte_addr[i],
+				hop_pte_addr[i]);
+
+		rc = -EINVAL;
+		goto err;
+	}
+
+	curr_pte = (scrambled_phys_addr & HOP_PHYS_ADDR_MASK)
+					| mmu_prop->last_mask | PAGE_PRESENT_MASK;
+
+	/* Write the PTEs */
+	hl_mmu_dr_write_final_pte(ctx, hop_pte_addr[hop_last], curr_pte);
+
+	/* for each new hop, add its address to the table of previous-hop */
+	for (i = 1 ; i <= hop_last ; i++) {
+		if (hop_new[i]) {
+			curr_pte = (hop_addr[i] & HOP_PHYS_ADDR_MASK) | PAGE_PRESENT_MASK;
+			hl_mmu_dr_write_pte(ctx, hop_pte_addr[i - 1], curr_pte);
+
+			if (i - 1)
+				hl_mmu_dr_get_pte(ctx, hop_addr[i - 1]);
+		}
+	}
+	hl_mmu_dr_get_pte(ctx, hop_addr[hop_last]);
+
+	return 0;
+
+err:
+	for (i = 1 ; i <= hop_last ; i++)
+		if (hop_new[i] && (hop_addr[i] != U64_MAX))
+			hl_mmu_dr_free_hop(ctx, hop_addr[i]);
+
+	return rc;
+}
+
+/*
+ * hl_mmu_v2_swap_out - marks all mapping of the given ctx as swapped out
+ *
+ * @ctx: pointer to the context structure
+ *
+ */
+static void hl_mmu_v2_swap_out(struct hl_ctx *ctx)
+{
+
+}
+
+/*
+ * hl_mmu_v2_swap_in - marks all mapping of the given ctx as swapped in
+ *
+ * @ctx: pointer to the context structure
+ *
+ */
+static void hl_mmu_v2_swap_in(struct hl_ctx *ctx)
+{
+
+}
+
+static int hl_mmu_v2_get_tlb_info(struct hl_ctx *ctx, u64 virt_addr, struct hl_mmu_hop_info *hops)
+{
+	struct asic_fixed_properties *prop = &ctx->hdev->asic_prop;
+	struct hl_device *hdev = ctx->hdev;
+	struct hl_mmu_properties *mmu_prop;
+	bool is_dram_addr;
+	int i;
+
+	is_dram_addr = hl_mem_area_inside_range(virt_addr, prop->dmmu.page_size,
+						prop->dmmu.start_addr,
+						prop->dmmu.end_addr);
+
+	/* device resident in V2 are allowed only for HMMU */
+	if (!is_dram_addr)
+		return -EINVAL;
+
+	mmu_prop = &prop->dmmu;
+	hops->range_type = HL_VA_RANGE_TYPE_DRAM;
+
+	hops->scrambled_vaddr = hdev->asic_funcs->scramble_addr(hdev, virt_addr);
+
+	hops->hop_info[0].hop_addr = hl_mmu_dr_get_phys_hop0_addr(ctx);
+	hops->hop_info[0].hop_pte_addr = hl_mmu_get_hop_pte_phys_addr(ctx, mmu_prop, 0,
+						hops->hop_info[0].hop_addr,
+							hops->scrambled_vaddr);
+	if (hops->hop_info[0].hop_pte_addr == U64_MAX)
+		return -EFAULT;
+
+	hops->hop_info[0].hop_pte_val = hdev->asic_funcs->read_pte(hdev,
+						hops->hop_info[0].hop_pte_addr);
+	if (hops->hop_info[0].hop_pte_val == U64_MAX)
+		return -EFAULT;
+
+	for (i = 1 ; i < mmu_prop->num_hops ; i++) {
+		hops->hop_info[i].hop_addr =
+			hl_mmu_get_next_hop_addr(ctx, hops->hop_info[i - 1].hop_pte_val);
+		if (hops->hop_info[i].hop_addr == ULLONG_MAX)
+			return -EFAULT;
+
+		hops->hop_info[i].hop_pte_addr =
+				hl_mmu_get_hop_pte_phys_addr(ctx, mmu_prop, i,
+						hops->hop_info[i].hop_addr,
+						hops->scrambled_vaddr);
+		if (hops->hop_info[i].hop_pte_addr == U64_MAX)
+			return -EFAULT;
+
+		hops->hop_info[i].hop_pte_val =
+				hdev->asic_funcs->read_pte(hdev,
+					hops->hop_info[i].hop_pte_addr);
+
+		if (!(hops->hop_info[i].hop_pte_val & PAGE_PRESENT_MASK))
+			return -EFAULT;
+
+		if (hops->hop_info[i].hop_pte_val & mmu_prop->last_mask)
+			break;
+	}
+
+	/* if passed over all hops then no last hop was found */
+	if (i == mmu_prop->num_hops)
+		return -EFAULT;
+
+	if (!(hops->hop_info[i].hop_pte_val & PAGE_PRESENT_MASK))
+		return -EFAULT;
+
+	if (hops->scrambled_vaddr != virt_addr)
+		hops->unscrambled_paddr = hdev->asic_funcs->descramble_addr
+				(hdev, hops->hop_info[i].hop_pte_val);
+	else
+		hops->unscrambled_paddr = hops->hop_info[i].hop_pte_val;
+
+	hops->used_hops = i + 1;
+
+	return 0;
+}
+
+/*
+ * hl_mmu_v2_prepare - prepare mmu_if for working with mmu v2
+ *
+ * @hdev: pointer to the device structure
+ * @mmu_if: pointer to the mmu interface structure
+ */
+void hl_mmu_v2_set_funcs(struct hl_device *hdev, struct hl_mmu_funcs *mmu)
+{
+	mmu->init = hl_mmu_dr_init;
+	mmu->fini = hl_mmu_dr_fini;
+	mmu->ctx_init = hl_mmu_v2_ctx_init;
+	mmu->ctx_fini = hl_mmu_v2_ctx_fini;
+	mmu->map = hl_mmu_v2_map;
+	mmu->unmap = hl_mmu_v2_unmap;
+	mmu->flush = hl_mmu_dr_flush;
+	mmu->swap_out = hl_mmu_v2_swap_out;
+	mmu->swap_in = hl_mmu_v2_swap_in;
+	mmu->get_tlb_info = hl_mmu_v2_get_tlb_info;
+}
diff --git a/drivers/accel/habanalabs/common/mmu/mmu_v2_hr.c b/drivers/accel/habanalabs/common/mmu/mmu_v2_hr.c
new file mode 100644
index 000000000000..31507b2a431b
--- /dev/null
+++ b/drivers/accel/habanalabs/common/mmu/mmu_v2_hr.c
@@ -0,0 +1,399 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Copyright 2020-2022 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ */
+
+#include "../habanalabs.h"
+#include "../../include/hw_ip/mmu/mmu_general.h"
+
+#include <linux/slab.h>
+
+static struct pgt_info *hl_mmu_v2_hr_get_pgt_info(struct hl_ctx *ctx, u64 phys_hop_addr)
+{
+	struct pgt_info *pgt_info = NULL;
+
+	hash_for_each_possible(ctx->hr_mmu_phys_hash, pgt_info, node,
+				(unsigned long) phys_hop_addr)
+		if (phys_hop_addr == pgt_info->phys_addr)
+			break;
+
+	return pgt_info;
+}
+
+static void hl_mmu_v2_hr_add_pgt_info(struct hl_ctx *ctx, struct pgt_info *pgt_info,
+					dma_addr_t phys_addr)
+{
+	hash_add(ctx->hr_mmu_phys_hash, &pgt_info->node, phys_addr);
+}
+
+static struct pgt_info *hl_mmu_v2_hr_get_hop0_pgt_info(struct hl_ctx *ctx)
+{
+	return &ctx->hdev->mmu_priv.hr.mmu_asid_hop0[ctx->asid];
+}
+
+/**
+ * hl_mmu_v2_hr_init() - initialize the MMU module.
+ * @hdev: habanalabs device structure.
+ *
+ * This function does the following:
+ * - Create a pool of pages for pgt_infos.
+ * - Create a shadow table for pgt
+ *
+ * Return: 0 for success, non-zero for failure.
+ */
+static inline int hl_mmu_v2_hr_init(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+
+	return hl_mmu_hr_init(hdev, &hdev->mmu_priv.hr, prop->pmmu.hop_table_size,
+				prop->mmu_pgt_size);
+}
+
+/**
+ * hl_mmu_v2_hr_fini() - release the MMU module.
+ * @hdev: habanalabs device structure.
+ *
+ * This function does the following:
+ * - Disable MMU in H/W.
+ * - Free the pgt_infos pool.
+ *
+ * All contexts should be freed before calling this function.
+ */
+static inline void hl_mmu_v2_hr_fini(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+
+	hl_mmu_hr_fini(hdev, &hdev->mmu_priv.hr, prop->pmmu.hop_table_size);
+}
+
+/**
+ * hl_mmu_v2_hr_ctx_init() - initialize a context for using the MMU module.
+ * @ctx: pointer to the context structure to initialize.
+ *
+ * Initialize a mutex to protect the concurrent mapping flow, a hash to hold all
+ * page tables hops related to this context.
+ * Return: 0 on success, non-zero otherwise.
+ */
+static int hl_mmu_v2_hr_ctx_init(struct hl_ctx *ctx)
+{
+	hash_init(ctx->hr_mmu_phys_hash);
+	return 0;
+}
+
+/*
+ * hl_mmu_v2_hr_ctx_fini - disable a ctx from using the mmu module
+ *
+ * @ctx: pointer to the context structure
+ *
+ * This function does the following:
+ * - Free any pgts which were not freed yet
+ * - Free the mutex
+ * - Free DRAM default page mapping hops
+ */
+static void hl_mmu_v2_hr_ctx_fini(struct hl_ctx *ctx)
+{
+	struct hl_device *hdev = ctx->hdev;
+	struct pgt_info *pgt_info;
+	struct hlist_node *tmp;
+	int i;
+
+	if (!hash_empty(ctx->hr_mmu_phys_hash))
+		dev_err(hdev->dev, "ctx %d is freed while it has pgts in use\n",
+			ctx->asid);
+
+	hash_for_each_safe(ctx->hr_mmu_phys_hash, i, tmp, pgt_info, node) {
+		dev_err_ratelimited(hdev->dev,
+			"pgt_info of addr 0x%llx of asid %d was not destroyed, num_ptes: %d\n",
+			pgt_info->phys_addr, ctx->asid, pgt_info->num_of_ptes);
+		hl_mmu_hr_free_hop_remove_pgt(pgt_info, &ctx->hdev->mmu_priv.hr,
+							ctx->hdev->asic_prop.pmmu.hop_table_size);
+	}
+}
+
+static int _hl_mmu_v2_hr_unmap(struct hl_ctx *ctx,
+				u64 virt_addr, bool is_dram_addr)
+{
+	u64 curr_pte, scrambled_virt_addr, hop_pte_phys_addr[MMU_ARCH_6_HOPS] = { 0 };
+	struct pgt_info *hops_pgt_info[MMU_ARCH_6_HOPS] = { NULL };
+	struct hl_device *hdev = ctx->hdev;
+	struct asic_fixed_properties *prop;
+	struct hl_mmu_properties *mmu_prop;
+	bool is_huge = false;
+	int i, hop_last;
+
+	prop = &hdev->asic_prop;
+
+	/* shifts and masks are the same in PMMU and HMMU, use one of them */
+	mmu_prop = is_dram_addr ? &prop->dmmu : &prop->pmmu;
+	hop_last = mmu_prop->num_hops - 1;
+
+	scrambled_virt_addr = hdev->asic_funcs->scramble_addr(hdev, virt_addr);
+	curr_pte = 0;
+
+	for (i = 0 ; i < mmu_prop->num_hops ; i++) {
+		/* we get HOP0 differently, it doesn't need curr_pte */
+		if (i == 0)
+			hops_pgt_info[i] = hl_mmu_v2_hr_get_hop0_pgt_info(ctx);
+		else
+			hops_pgt_info[i] = hl_mmu_hr_get_next_hop_pgt_info(ctx,
+					&ctx->hdev->mmu_func[MMU_HR_PGT].hr_funcs, curr_pte);
+		if (!hops_pgt_info[i])
+			goto not_mapped;
+
+		hop_pte_phys_addr[i] = hl_mmu_get_hop_pte_phys_addr(ctx, mmu_prop, i,
+									hops_pgt_info[i]->phys_addr,
+									scrambled_virt_addr);
+		if (hop_pte_phys_addr[i] == U64_MAX)
+			return -EFAULT;
+
+		curr_pte = *(u64 *) (uintptr_t) hl_mmu_hr_pte_phys_to_virt(ctx, hops_pgt_info[i],
+							hop_pte_phys_addr[i],
+							ctx->hdev->asic_prop.pmmu.hop_table_size);
+
+		if ((i < hop_last) && (curr_pte & mmu_prop->last_mask)) {
+			hop_last = i;
+			is_huge = true;
+			break;
+		}
+	}
+
+	if (is_dram_addr && !is_huge) {
+		dev_err(hdev->dev, "DRAM unmapping should use huge pages only\n");
+		return -EFAULT;
+	}
+
+	if (!(curr_pte & PAGE_PRESENT_MASK))
+		goto not_mapped;
+
+	for (i = hop_last ; i > 0 ; i--) {
+		hl_mmu_hr_clear_pte(ctx, hops_pgt_info[i], hop_pte_phys_addr[i],
+						ctx->hdev->asic_prop.pmmu.hop_table_size);
+
+		if (hl_mmu_hr_put_pte(ctx, hops_pgt_info[i], &ctx->hdev->mmu_priv.hr,
+						ctx->hdev->asic_prop.pmmu.hop_table_size))
+			goto mapped;
+	}
+	hl_mmu_hr_clear_pte(ctx, hops_pgt_info[0], hop_pte_phys_addr[0],
+						ctx->hdev->asic_prop.pmmu.hop_table_size);
+
+mapped:
+	return 0;
+
+not_mapped:
+	dev_err(hdev->dev, "virt addr 0x%llx is not mapped to phys addr\n", virt_addr);
+
+	return -EINVAL;
+}
+
+static int hl_mmu_v2_get_last_hop(struct hl_mmu_properties *mmu_prop, u32 page_size)
+{
+	int hop;
+
+	for (hop = (mmu_prop->num_hops - 1); hop; hop--) {
+		if (mmu_prop->hop_shifts[hop] == 0)
+			continue;
+
+		if (page_size <= (1 << mmu_prop->hop_shifts[hop]))
+			break;
+	}
+
+	return hop;
+}
+
+static int _hl_mmu_v2_hr_map(struct hl_ctx *ctx,
+			u64 virt_addr, u64 phys_addr,
+			u32 page_size, bool is_dram_addr)
+{
+	u64 hop_pte_phys_addr[MMU_ARCH_6_HOPS] = { 0 },
+		curr_pte = 0, scrambled_virt_addr, scrambled_phys_addr;
+	struct pgt_info *hops_pgt_info[MMU_ARCH_6_HOPS] = { NULL };
+	bool hop_new[MMU_ARCH_6_HOPS] = { false };
+	struct hl_device *hdev = ctx->hdev;
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct hl_mmu_properties *mmu_prop;
+	int i, hop_last, rc = -ENOMEM;
+
+	/*
+	 * This mapping function can map a page or a huge page. For huge page
+	 * there are only 4 hops rather than 5. Currently the DRAM allocation
+	 * uses huge pages only but user memory could have been allocated with
+	 * one of the two page sizes. Since this is a common code for all the
+	 * three cases, we need this hugs page check.
+	 */
+	if (is_dram_addr)
+		mmu_prop = &prop->dmmu;
+	else if (page_size == prop->pmmu_huge.page_size)
+		mmu_prop = &prop->pmmu_huge;
+	else
+		mmu_prop = &prop->pmmu;
+
+	hop_last = hl_mmu_v2_get_last_hop(mmu_prop, page_size);
+	if (hop_last <= 0) {
+		dev_err(ctx->hdev->dev, "Invalid last HOP %d\n", hop_last);
+		return -EFAULT;
+	}
+
+	scrambled_virt_addr = hdev->asic_funcs->scramble_addr(hdev, virt_addr);
+	scrambled_phys_addr = hdev->asic_funcs->scramble_addr(hdev, phys_addr);
+
+	for (i = 0 ; i <= hop_last ; i++) {
+
+		if (i == 0)
+			hops_pgt_info[i] = hl_mmu_v2_hr_get_hop0_pgt_info(ctx);
+		else
+			hops_pgt_info[i] = hl_mmu_hr_get_alloc_next_hop(ctx,
+							&ctx->hdev->mmu_priv.hr,
+							&ctx->hdev->mmu_func[MMU_HR_PGT].hr_funcs,
+							mmu_prop, curr_pte, &hop_new[i]);
+		if (!hops_pgt_info[i])
+			goto err;
+
+		hop_pte_phys_addr[i] = hl_mmu_get_hop_pte_phys_addr(ctx, mmu_prop, i,
+									hops_pgt_info[i]->phys_addr,
+									scrambled_virt_addr);
+		curr_pte = *(u64 *) (uintptr_t) hl_mmu_hr_pte_phys_to_virt(ctx, hops_pgt_info[i],
+							hop_pte_phys_addr[i],
+							ctx->hdev->asic_prop.pmmu.hop_table_size);
+	}
+
+	if (curr_pte & PAGE_PRESENT_MASK) {
+		dev_err(hdev->dev, "mapping already exists for virt_addr 0x%llx\n",
+									scrambled_virt_addr);
+
+		for (i = 0 ; i <= hop_last ; i++)
+			dev_dbg(hdev->dev, "hop%d pte: 0x%llx (0x%llx)\n",
+					i,
+					*(u64 *) (uintptr_t)
+					hl_mmu_hr_pte_phys_to_virt(ctx, hops_pgt_info[i],
+							hop_pte_phys_addr[i],
+							ctx->hdev->asic_prop.pmmu.hop_table_size),
+					hop_pte_phys_addr[i]);
+		rc = -EINVAL;
+		goto err;
+	}
+
+	curr_pte = (scrambled_phys_addr & HOP_PHYS_ADDR_MASK) | mmu_prop->last_mask
+			| PAGE_PRESENT_MASK;
+
+	/* Write the PTEs */
+	hl_mmu_hr_write_pte(ctx, hops_pgt_info[hop_last], hop_pte_phys_addr[hop_last], curr_pte,
+							ctx->hdev->asic_prop.pmmu.hop_table_size);
+
+	/* for each new hop, add its address to the table of previous-hop */
+	for (i = 1 ; i <= hop_last ; i++) {
+		if (hop_new[i]) {
+			curr_pte = (hops_pgt_info[i]->phys_addr & HOP_PHYS_ADDR_MASK) |
+							PAGE_PRESENT_MASK;
+			hl_mmu_hr_write_pte(ctx, hops_pgt_info[i - 1], hop_pte_phys_addr[i - 1],
+						curr_pte, ctx->hdev->asic_prop.pmmu.hop_table_size);
+			if (i - 1)
+				hl_mmu_hr_get_pte(ctx, &ctx->hdev->mmu_func[MMU_HR_PGT].hr_funcs,
+								hops_pgt_info[i - 1]->phys_addr);
+		}
+	}
+
+	hl_mmu_hr_get_pte(ctx, &ctx->hdev->mmu_func[MMU_HR_PGT].hr_funcs,
+						hops_pgt_info[hop_last]->phys_addr);
+
+	return 0;
+
+err:
+	for (i = 1 ; i <= hop_last ; i++)
+		if (hop_new[i] && hops_pgt_info[i])
+			hl_mmu_hr_free_hop_remove_pgt(hops_pgt_info[i], &ctx->hdev->mmu_priv.hr,
+							ctx->hdev->asic_prop.pmmu.hop_table_size);
+
+	return rc;
+}
+
+/*
+ * hl_mmu_v2_swap_out - marks all mapping of the given ctx as swapped out
+ *
+ * @ctx: pointer to the context structure
+ *
+ */
+static void hl_mmu_v2_hr_swap_out(struct hl_ctx *ctx)
+{
+
+}
+
+/*
+ * hl_mmu_v2_swap_in - marks all mapping of the given ctx as swapped in
+ *
+ * @ctx: pointer to the context structure
+ *
+ */
+static void hl_mmu_v2_hr_swap_in(struct hl_ctx *ctx)
+{
+
+}
+
+static int hl_mmu_v2_hr_get_tlb_mapping_params(struct hl_device *hdev,
+							struct hl_mmu_properties **mmu_prop,
+							struct hl_mmu_hop_info *hops,
+							u64 virt_addr, bool *is_huge)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	bool is_dram_addr, is_pmmu_addr, is_pmmu_h_addr;
+
+	is_dram_addr = hl_mem_area_inside_range(virt_addr, prop->dmmu.page_size,
+						prop->dmmu.start_addr,
+						prop->dmmu.end_addr);
+	is_pmmu_addr = hl_mem_area_inside_range(virt_addr, prop->pmmu.page_size,
+						prop->pmmu.start_addr,
+						prop->pmmu.end_addr);
+	is_pmmu_h_addr = hl_mem_area_inside_range(virt_addr,
+						prop->pmmu_huge.page_size,
+						prop->pmmu_huge.start_addr,
+						prop->pmmu_huge.end_addr);
+	if (is_dram_addr) {
+		*mmu_prop = &prop->dmmu;
+		*is_huge = true;
+		hops->range_type = HL_VA_RANGE_TYPE_DRAM;
+	} else if (is_pmmu_addr) {
+		*mmu_prop = &prop->pmmu;
+		*is_huge = false;
+		hops->range_type = HL_VA_RANGE_TYPE_HOST;
+	} else if (is_pmmu_h_addr) {
+		*mmu_prop = &prop->pmmu_huge;
+		*is_huge = true;
+		hops->range_type = HL_VA_RANGE_TYPE_HOST_HUGE;
+	} else {
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int hl_mmu_v2_hr_get_tlb_info(struct hl_ctx *ctx, u64 virt_addr,
+					struct hl_mmu_hop_info *hops)
+{
+	return hl_mmu_hr_get_tlb_info(ctx, virt_addr, hops,
+					&ctx->hdev->mmu_func[MMU_HR_PGT].hr_funcs);
+}
+
+/*
+ * hl_mmu_v2_prepare - prepare mmu_if for working with mmu v2
+ *
+ * @hdev: pointer to the device structure
+ * @mmu_if: pointer to the mmu interface structure
+ */
+void hl_mmu_v2_hr_set_funcs(struct hl_device *hdev, struct hl_mmu_funcs *mmu)
+{
+	mmu->init = hl_mmu_v2_hr_init;
+	mmu->fini = hl_mmu_v2_hr_fini;
+	mmu->ctx_init = hl_mmu_v2_hr_ctx_init;
+	mmu->ctx_fini = hl_mmu_v2_hr_ctx_fini;
+	mmu->map = _hl_mmu_v2_hr_map;
+	mmu->unmap = _hl_mmu_v2_hr_unmap;
+	mmu->flush = hl_mmu_hr_flush;
+	mmu->swap_out = hl_mmu_v2_hr_swap_out;
+	mmu->swap_in = hl_mmu_v2_hr_swap_in;
+	mmu->get_tlb_info = hl_mmu_v2_hr_get_tlb_info;
+	mmu->hr_funcs.get_hop0_pgt_info = hl_mmu_v2_hr_get_hop0_pgt_info;
+	mmu->hr_funcs.get_pgt_info = hl_mmu_v2_hr_get_pgt_info;
+	mmu->hr_funcs.add_pgt_info = hl_mmu_v2_hr_add_pgt_info;
+	mmu->hr_funcs.get_tlb_mapping_params = hl_mmu_v2_hr_get_tlb_mapping_params;
+}
diff --git a/drivers/accel/habanalabs/common/pci/Makefile b/drivers/accel/habanalabs/common/pci/Makefile
new file mode 100644
index 000000000000..dc922a686683
--- /dev/null
+++ b/drivers/accel/habanalabs/common/pci/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
+HL_COMMON_PCI_FILES := common/pci/pci.o
diff --git a/drivers/accel/habanalabs/common/pci/pci.c b/drivers/accel/habanalabs/common/pci/pci.c
new file mode 100644
index 000000000000..81cbd8697d4c
--- /dev/null
+++ b/drivers/accel/habanalabs/common/pci/pci.c
@@ -0,0 +1,439 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Copyright 2016-2019 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ */
+
+#include "../habanalabs.h"
+#include "../../include/hw_ip/pci/pci_general.h"
+
+#include <linux/pci.h>
+
+#include <trace/events/habanalabs.h>
+
+#define HL_PLDM_PCI_ELBI_TIMEOUT_MSEC	(HL_PCI_ELBI_TIMEOUT_MSEC * 100)
+
+#define IATU_REGION_CTRL_REGION_EN_MASK		BIT(31)
+#define IATU_REGION_CTRL_MATCH_MODE_MASK	BIT(30)
+#define IATU_REGION_CTRL_NUM_MATCH_EN_MASK	BIT(19)
+#define IATU_REGION_CTRL_BAR_NUM_MASK		GENMASK(10, 8)
+
+/**
+ * hl_pci_bars_map() - Map PCI BARs.
+ * @hdev: Pointer to hl_device structure.
+ * @name: Array of BAR names.
+ * @is_wc: Array with flag per BAR whether a write-combined mapping is needed.
+ *
+ * Request PCI regions and map them to kernel virtual addresses.
+ *
+ * Return: 0 on success, non-zero for failure.
+ */
+int hl_pci_bars_map(struct hl_device *hdev, const char * const name[3],
+			bool is_wc[3])
+{
+	struct pci_dev *pdev = hdev->pdev;
+	int rc, i, bar;
+
+	rc = pci_request_regions(pdev, HL_NAME);
+	if (rc) {
+		dev_err(hdev->dev, "Cannot obtain PCI resources\n");
+		return rc;
+	}
+
+	for (i = 0 ; i < 3 ; i++) {
+		bar = i * 2; /* 64-bit BARs */
+		hdev->pcie_bar[bar] = is_wc[i] ?
+				pci_ioremap_wc_bar(pdev, bar) :
+				pci_ioremap_bar(pdev, bar);
+		if (!hdev->pcie_bar[bar]) {
+			dev_err(hdev->dev, "pci_ioremap%s_bar failed for %s\n",
+					is_wc[i] ? "_wc" : "", name[i]);
+			rc = -ENODEV;
+			goto err;
+		}
+	}
+
+	return 0;
+
+err:
+	for (i = 2 ; i >= 0 ; i--) {
+		bar = i * 2; /* 64-bit BARs */
+		if (hdev->pcie_bar[bar])
+			iounmap(hdev->pcie_bar[bar]);
+	}
+
+	pci_release_regions(pdev);
+
+	return rc;
+}
+
+/**
+ * hl_pci_bars_unmap() - Unmap PCI BARS.
+ * @hdev: Pointer to hl_device structure.
+ *
+ * Release all PCI BARs and unmap their virtual addresses.
+ */
+static void hl_pci_bars_unmap(struct hl_device *hdev)
+{
+	struct pci_dev *pdev = hdev->pdev;
+	int i, bar;
+
+	for (i = 2 ; i >= 0 ; i--) {
+		bar = i * 2; /* 64-bit BARs */
+		iounmap(hdev->pcie_bar[bar]);
+	}
+
+	pci_release_regions(pdev);
+}
+
+int hl_pci_elbi_read(struct hl_device *hdev, u64 addr, u32 *data)
+{
+	struct pci_dev *pdev = hdev->pdev;
+	ktime_t timeout;
+	u64 msec;
+	u32 val;
+
+	if (hdev->pldm)
+		msec = HL_PLDM_PCI_ELBI_TIMEOUT_MSEC;
+	else
+		msec = HL_PCI_ELBI_TIMEOUT_MSEC;
+
+	/* Clear previous status */
+	pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_STS, 0);
+
+	pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_ADDR, (u32) addr);
+	pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_CTRL, 0);
+
+	timeout = ktime_add_ms(ktime_get(), msec);
+	for (;;) {
+		pci_read_config_dword(pdev, mmPCI_CONFIG_ELBI_STS, &val);
+		if (val & PCI_CONFIG_ELBI_STS_MASK)
+			break;
+		if (ktime_compare(ktime_get(), timeout) > 0) {
+			pci_read_config_dword(pdev, mmPCI_CONFIG_ELBI_STS,
+						&val);
+			break;
+		}
+
+		usleep_range(300, 500);
+	}
+
+	if ((val & PCI_CONFIG_ELBI_STS_MASK) == PCI_CONFIG_ELBI_STS_DONE) {
+		pci_read_config_dword(pdev, mmPCI_CONFIG_ELBI_DATA, data);
+
+		if (unlikely(trace_habanalabs_elbi_read_enabled()))
+			trace_habanalabs_elbi_read(&hdev->pdev->dev, (u32) addr, val);
+
+		return 0;
+	}
+
+	if (val & PCI_CONFIG_ELBI_STS_ERR) {
+		dev_err(hdev->dev, "Error reading from ELBI\n");
+		return -EIO;
+	}
+
+	if (!(val & PCI_CONFIG_ELBI_STS_MASK)) {
+		dev_err(hdev->dev, "ELBI read didn't finish in time\n");
+		return -EIO;
+	}
+
+	dev_err(hdev->dev, "ELBI read has undefined bits in status\n");
+	return -EIO;
+}
+
+/**
+ * hl_pci_elbi_write() - Write through the ELBI interface.
+ * @hdev: Pointer to hl_device structure.
+ * @addr: Address to write to
+ * @data: Data to write
+ *
+ * Return: 0 on success, negative value for failure.
+ */
+static int hl_pci_elbi_write(struct hl_device *hdev, u64 addr, u32 data)
+{
+	struct pci_dev *pdev = hdev->pdev;
+	ktime_t timeout;
+	u64 msec;
+	u32 val;
+
+	if (hdev->pldm)
+		msec = HL_PLDM_PCI_ELBI_TIMEOUT_MSEC;
+	else
+		msec = HL_PCI_ELBI_TIMEOUT_MSEC;
+
+	/* Clear previous status */
+	pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_STS, 0);
+
+	pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_ADDR, (u32) addr);
+	pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_DATA, data);
+	pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_CTRL,
+				PCI_CONFIG_ELBI_CTRL_WRITE);
+
+	timeout = ktime_add_ms(ktime_get(), msec);
+	for (;;) {
+		pci_read_config_dword(pdev, mmPCI_CONFIG_ELBI_STS, &val);
+		if (val & PCI_CONFIG_ELBI_STS_MASK)
+			break;
+		if (ktime_compare(ktime_get(), timeout) > 0) {
+			pci_read_config_dword(pdev, mmPCI_CONFIG_ELBI_STS,
+						&val);
+			break;
+		}
+
+		usleep_range(300, 500);
+	}
+
+	if ((val & PCI_CONFIG_ELBI_STS_MASK) == PCI_CONFIG_ELBI_STS_DONE) {
+		if (unlikely(trace_habanalabs_elbi_write_enabled()))
+			trace_habanalabs_elbi_write(&hdev->pdev->dev, (u32) addr, val);
+		return 0;
+	}
+
+	if (val & PCI_CONFIG_ELBI_STS_ERR)
+		return -EIO;
+
+	if (!(val & PCI_CONFIG_ELBI_STS_MASK)) {
+		dev_err(hdev->dev, "ELBI write didn't finish in time\n");
+		return -EIO;
+	}
+
+	dev_err(hdev->dev, "ELBI write has undefined bits in status\n");
+	return -EIO;
+}
+
+/**
+ * hl_pci_iatu_write() - iatu write routine.
+ * @hdev: Pointer to hl_device structure.
+ * @addr: Address to write to
+ * @data: Data to write
+ *
+ * Return: 0 on success, negative value for failure.
+ */
+int hl_pci_iatu_write(struct hl_device *hdev, u32 addr, u32 data)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	u32 dbi_offset;
+	int rc;
+
+	dbi_offset = addr & 0xFFF;
+
+	/* Ignore result of writing to pcie_aux_dbi_reg_addr as it could fail
+	 * in case the firmware security is enabled
+	 */
+	hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr, 0x00300000);
+
+	rc = hl_pci_elbi_write(hdev, prop->pcie_dbi_base_address + dbi_offset,
+				data);
+
+	if (rc)
+		return -EIO;
+
+	return 0;
+}
+
+/**
+ * hl_pci_set_inbound_region() - Configure inbound region
+ * @hdev: Pointer to hl_device structure.
+ * @region: Inbound region number.
+ * @pci_region: Inbound region parameters.
+ *
+ * Configure the iATU inbound region.
+ *
+ * Return: 0 on success, negative value for failure.
+ */
+int hl_pci_set_inbound_region(struct hl_device *hdev, u8 region,
+		struct hl_inbound_pci_region *pci_region)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	u64 bar_phys_base, region_base, region_end_address;
+	u32 offset, ctrl_reg_val;
+	int rc = 0;
+
+	/* region offset */
+	offset = (0x200 * region) + 0x100;
+
+	if (pci_region->mode == PCI_ADDRESS_MATCH_MODE) {
+		bar_phys_base = hdev->pcie_bar_phys[pci_region->bar];
+		region_base = bar_phys_base + pci_region->offset_in_bar;
+		region_end_address = region_base + pci_region->size - 1;
+
+		rc |= hl_pci_iatu_write(hdev, offset + 0x8,
+				lower_32_bits(region_base));
+		rc |= hl_pci_iatu_write(hdev, offset + 0xC,
+				upper_32_bits(region_base));
+		rc |= hl_pci_iatu_write(hdev, offset + 0x10,
+				lower_32_bits(region_end_address));
+	}
+
+	/* Point to the specified address */
+	rc |= hl_pci_iatu_write(hdev, offset + 0x14, lower_32_bits(pci_region->addr));
+	rc |= hl_pci_iatu_write(hdev, offset + 0x18, upper_32_bits(pci_region->addr));
+
+	/* Set bar type as memory */
+	rc |= hl_pci_iatu_write(hdev, offset + 0x0, 0);
+
+	/* Enable + bar/address match + match enable + bar number */
+	ctrl_reg_val = FIELD_PREP(IATU_REGION_CTRL_REGION_EN_MASK, 1);
+	ctrl_reg_val |= FIELD_PREP(IATU_REGION_CTRL_MATCH_MODE_MASK, pci_region->mode);
+	ctrl_reg_val |= FIELD_PREP(IATU_REGION_CTRL_NUM_MATCH_EN_MASK, 1);
+
+	if (pci_region->mode == PCI_BAR_MATCH_MODE)
+		ctrl_reg_val |= FIELD_PREP(IATU_REGION_CTRL_BAR_NUM_MASK, pci_region->bar);
+
+	rc |= hl_pci_iatu_write(hdev, offset + 0x4, ctrl_reg_val);
+
+	/* Return the DBI window to the default location
+	 * Ignore result of writing to pcie_aux_dbi_reg_addr as it could fail
+	 * in case the firmware security is enabled
+	 */
+	hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr, 0);
+
+	if (rc)
+		dev_err(hdev->dev, "failed to map bar %u to 0x%08llx\n",
+				pci_region->bar, pci_region->addr);
+
+	return rc;
+}
+
+/**
+ * hl_pci_set_outbound_region() - Configure outbound region 0
+ * @hdev: Pointer to hl_device structure.
+ * @pci_region: Outbound region parameters.
+ *
+ * Configure the iATU outbound region 0.
+ *
+ * Return: 0 on success, negative value for failure.
+ */
+int hl_pci_set_outbound_region(struct hl_device *hdev,
+		struct hl_outbound_pci_region *pci_region)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	u64 outbound_region_end_address;
+	int rc = 0;
+
+	/* Outbound Region 0 */
+	outbound_region_end_address =
+			pci_region->addr + pci_region->size - 1;
+	rc |= hl_pci_iatu_write(hdev, 0x008,
+				lower_32_bits(pci_region->addr));
+	rc |= hl_pci_iatu_write(hdev, 0x00C,
+				upper_32_bits(pci_region->addr));
+	rc |= hl_pci_iatu_write(hdev, 0x010,
+				lower_32_bits(outbound_region_end_address));
+	rc |= hl_pci_iatu_write(hdev, 0x014, 0);
+
+	rc |= hl_pci_iatu_write(hdev, 0x018, 0);
+
+	rc |= hl_pci_iatu_write(hdev, 0x020,
+				upper_32_bits(outbound_region_end_address));
+	/* Increase region size */
+	rc |= hl_pci_iatu_write(hdev, 0x000, 0x00002000);
+	/* Enable */
+	rc |= hl_pci_iatu_write(hdev, 0x004, 0x80000000);
+
+	/* Return the DBI window to the default location
+	 * Ignore result of writing to pcie_aux_dbi_reg_addr as it could fail
+	 * in case the firmware security is enabled
+	 */
+	hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr, 0);
+
+	return rc;
+}
+
+/**
+ * hl_get_pci_memory_region() - get PCI region for given address
+ * @hdev: Pointer to hl_device structure.
+ * @addr: device address
+ *
+ * @return region index on success, otherwise PCI_REGION_NUMBER (invalid
+ *         region index)
+ */
+enum pci_region hl_get_pci_memory_region(struct hl_device *hdev, u64 addr)
+{
+	int i;
+
+	for  (i = 0 ; i < PCI_REGION_NUMBER ; i++) {
+		struct pci_mem_region *region = &hdev->pci_mem_region[i];
+
+		if (!region->used)
+			continue;
+
+		if ((addr >= region->region_base) &&
+			(addr < region->region_base + region->region_size))
+			return i;
+	}
+
+	return PCI_REGION_NUMBER;
+}
+
+/**
+ * hl_pci_init() - PCI initialization code.
+ * @hdev: Pointer to hl_device structure.
+ *
+ * Set DMA masks, initialize the PCI controller and map the PCI BARs.
+ *
+ * Return: 0 on success, non-zero for failure.
+ */
+int hl_pci_init(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct pci_dev *pdev = hdev->pdev;
+	int rc;
+
+	rc = pci_enable_device_mem(pdev);
+	if (rc) {
+		dev_err(hdev->dev, "can't enable PCI device\n");
+		return rc;
+	}
+
+	pci_set_master(pdev);
+
+	rc = hdev->asic_funcs->pci_bars_map(hdev);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to map PCI BAR addresses\n");
+		goto disable_device;
+	}
+
+	rc = hdev->asic_funcs->init_iatu(hdev);
+	if (rc) {
+		dev_err(hdev->dev, "PCI controller was not initialized successfully\n");
+		goto unmap_pci_bars;
+	}
+
+	/* Driver must sleep in order for FW to finish the iATU configuration */
+	if (hdev->asic_prop.iatu_done_by_fw)
+		usleep_range(2000, 3000);
+
+	rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(prop->dma_mask));
+	if (rc) {
+		dev_err(hdev->dev,
+			"Failed to set dma mask to %d bits, error %d\n",
+			prop->dma_mask, rc);
+		goto unmap_pci_bars;
+	}
+
+	dma_set_max_seg_size(&pdev->dev, U32_MAX);
+
+	return 0;
+
+unmap_pci_bars:
+	hl_pci_bars_unmap(hdev);
+disable_device:
+	pci_disable_device(pdev);
+
+	return rc;
+}
+
+/**
+ * hl_pci_fini() - PCI finalization code.
+ * @hdev: Pointer to hl_device structure
+ *
+ * Unmap PCI bars and disable PCI device.
+ */
+void hl_pci_fini(struct hl_device *hdev)
+{
+	hl_pci_bars_unmap(hdev);
+
+	pci_disable_device(hdev->pdev);
+}
diff --git a/drivers/accel/habanalabs/common/security.c b/drivers/accel/habanalabs/common/security.c
new file mode 100644
index 000000000000..5402a3cd0491
--- /dev/null
+++ b/drivers/accel/habanalabs/common/security.c
@@ -0,0 +1,792 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Copyright 2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ */
+
+#include "habanalabs.h"
+
+static const char * const hl_glbl_error_cause[] = {
+	"Error due to un-priv read",
+	"Error due to un-secure read",
+	"Error due to read from unmapped reg",
+	"Error due to un-priv write",
+	"Error due to un-secure write",
+	"Error due to write to unmapped reg",
+	"N/A",
+	"N/A",
+	"N/A",
+	"N/A",
+	"N/A",
+	"N/A",
+	"N/A",
+	"N/A",
+	"N/A",
+	"N/A",
+	"External I/F write sec violation",
+	"External I/F write to un-mapped reg",
+	"N/A",
+	"N/A",
+	"N/A",
+	"N/A",
+	"N/A",
+	"N/A",
+	"Read to write only",
+	"Write to read only"
+};
+
+/**
+ * hl_get_pb_block - return the relevant block within the block array
+ *
+ * @hdev: pointer to hl_device structure
+ * @mm_reg_addr: register address in the desired block
+ * @pb_blocks: blocks array
+ * @array_size: blocks array size
+ *
+ */
+static int hl_get_pb_block(struct hl_device *hdev, u32 mm_reg_addr,
+		const u32 pb_blocks[], int array_size)
+{
+	int i;
+	u32 start_addr, end_addr;
+
+	for (i = 0 ; i < array_size ; i++) {
+		start_addr = pb_blocks[i];
+		end_addr = start_addr + HL_BLOCK_SIZE;
+
+		if ((mm_reg_addr >= start_addr) && (mm_reg_addr < end_addr))
+			return i;
+	}
+
+	dev_err(hdev->dev, "No protection domain was found for 0x%x\n",
+			mm_reg_addr);
+	return -EDOM;
+}
+
+/**
+ * hl_unset_pb_in_block - clear a specific protection bit in a block
+ *
+ * @hdev: pointer to hl_device structure
+ * @reg_offset: register offset will be converted to bit offset in pb block
+ * @sgs_entry: pb array
+ *
+ */
+static int hl_unset_pb_in_block(struct hl_device *hdev, u32 reg_offset,
+				struct hl_block_glbl_sec *sgs_entry)
+{
+	if ((reg_offset >= HL_BLOCK_SIZE) || (reg_offset & 0x3)) {
+		dev_err(hdev->dev,
+			"Register offset(%d) is out of range(%d) or invalid\n",
+			reg_offset, HL_BLOCK_SIZE);
+		return -EINVAL;
+	}
+
+	UNSET_GLBL_SEC_BIT(sgs_entry->sec_array,
+			 (reg_offset & (HL_BLOCK_SIZE - 1)) >> 2);
+
+	return 0;
+}
+
+/**
+ * hl_unsecure_register - locate the relevant block for this register and
+ *                        remove corresponding protection bit
+ *
+ * @hdev: pointer to hl_device structure
+ * @mm_reg_addr: register address to unsecure
+ * @offset: additional offset to the register address
+ * @pb_blocks: blocks array
+ * @sgs_array: pb array
+ * @array_size: blocks array size
+ *
+ */
+int hl_unsecure_register(struct hl_device *hdev, u32 mm_reg_addr, int offset,
+		const u32 pb_blocks[], struct hl_block_glbl_sec sgs_array[],
+		int array_size)
+{
+	u32 reg_offset;
+	int block_num;
+
+	block_num = hl_get_pb_block(hdev, mm_reg_addr + offset, pb_blocks,
+			array_size);
+	if (block_num < 0)
+		return block_num;
+
+	reg_offset = (mm_reg_addr + offset) - pb_blocks[block_num];
+
+	return hl_unset_pb_in_block(hdev, reg_offset, &sgs_array[block_num]);
+}
+
+/**
+ * hl_unsecure_register_range - locate the relevant block for this register
+ *                              range and remove corresponding protection bit
+ *
+ * @hdev: pointer to hl_device structure
+ * @mm_reg_range: register address range to unsecure
+ * @offset: additional offset to the register address
+ * @pb_blocks: blocks array
+ * @sgs_array: pb array
+ * @array_size: blocks array size
+ *
+ */
+static int hl_unsecure_register_range(struct hl_device *hdev,
+		struct range mm_reg_range, int offset, const u32 pb_blocks[],
+		struct hl_block_glbl_sec sgs_array[],
+		int array_size)
+{
+	u32 reg_offset;
+	int i, block_num, rc = 0;
+
+	block_num = hl_get_pb_block(hdev,
+			mm_reg_range.start + offset, pb_blocks,
+			array_size);
+	if (block_num < 0)
+		return block_num;
+
+	for (i = mm_reg_range.start ; i <= mm_reg_range.end ; i += 4) {
+		reg_offset = (i + offset) - pb_blocks[block_num];
+		rc |= hl_unset_pb_in_block(hdev, reg_offset,
+					&sgs_array[block_num]);
+	}
+
+	return rc;
+}
+
+/**
+ * hl_unsecure_registers - locate the relevant block for all registers and
+ *                        remove corresponding protection bit
+ *
+ * @hdev: pointer to hl_device structure
+ * @mm_reg_array: register address array to unsecure
+ * @mm_array_size: register array size
+ * @offset: additional offset to the register address
+ * @pb_blocks: blocks array
+ * @sgs_array: pb array
+ * @blocks_array_size: blocks array size
+ *
+ */
+int hl_unsecure_registers(struct hl_device *hdev, const u32 mm_reg_array[],
+		int mm_array_size, int offset, const u32 pb_blocks[],
+		struct hl_block_glbl_sec sgs_array[], int blocks_array_size)
+{
+	int i, rc = 0;
+
+	for (i = 0 ; i < mm_array_size ; i++) {
+		rc = hl_unsecure_register(hdev, mm_reg_array[i], offset,
+				pb_blocks, sgs_array, blocks_array_size);
+
+		if (rc)
+			return rc;
+	}
+
+	return rc;
+}
+
+/**
+ * hl_unsecure_registers_range - locate the relevant block for all register
+ *                        ranges and remove corresponding protection bit
+ *
+ * @hdev: pointer to hl_device structure
+ * @mm_reg_range_array: register address range array to unsecure
+ * @mm_array_size: register array size
+ * @offset: additional offset to the register address
+ * @pb_blocks: blocks array
+ * @sgs_array: pb array
+ * @blocks_array_size: blocks array size
+ *
+ */
+static int hl_unsecure_registers_range(struct hl_device *hdev,
+		const struct range mm_reg_range_array[], int mm_array_size,
+		int offset, const u32 pb_blocks[],
+		struct hl_block_glbl_sec sgs_array[], int blocks_array_size)
+{
+	int i, rc = 0;
+
+	for (i = 0 ; i < mm_array_size ; i++) {
+		rc = hl_unsecure_register_range(hdev, mm_reg_range_array[i],
+			offset, pb_blocks, sgs_array, blocks_array_size);
+
+		if (rc)
+			return rc;
+	}
+
+	return rc;
+}
+
+/**
+ * hl_ack_pb_security_violations - Ack security violation
+ *
+ * @hdev: pointer to hl_device structure
+ * @pb_blocks: blocks array
+ * @block_offset: additional offset to the block
+ * @array_size: blocks array size
+ *
+ */
+static void hl_ack_pb_security_violations(struct hl_device *hdev,
+		const u32 pb_blocks[], u32 block_offset, int array_size)
+{
+	int i;
+	u32 cause, addr, block_base;
+
+	for (i = 0 ; i < array_size ; i++) {
+		block_base = pb_blocks[i] + block_offset;
+		cause = RREG32(block_base + HL_BLOCK_GLBL_ERR_CAUSE);
+		if (cause) {
+			addr = RREG32(block_base + HL_BLOCK_GLBL_ERR_ADDR);
+			hdev->asic_funcs->pb_print_security_errors(hdev,
+					block_base, cause, addr);
+			WREG32(block_base + HL_BLOCK_GLBL_ERR_CAUSE, cause);
+		}
+	}
+}
+
+/**
+ * hl_config_glbl_sec - set pb in HW according to given pb array
+ *
+ * @hdev: pointer to hl_device structure
+ * @pb_blocks: blocks array
+ * @sgs_array: pb array
+ * @block_offset: additional offset to the block
+ * @array_size: blocks array size
+ *
+ */
+void hl_config_glbl_sec(struct hl_device *hdev, const u32 pb_blocks[],
+		struct hl_block_glbl_sec sgs_array[], u32 block_offset,
+		int array_size)
+{
+	int i, j;
+	u32 sgs_base;
+
+	if (hdev->pldm)
+		usleep_range(100, 1000);
+
+	for (i = 0 ; i < array_size ; i++) {
+		sgs_base = block_offset + pb_blocks[i] +
+				HL_BLOCK_GLBL_SEC_OFFS;
+
+		for (j = 0 ; j < HL_BLOCK_GLBL_SEC_LEN ; j++)
+			WREG32(sgs_base + j * sizeof(u32),
+				sgs_array[i].sec_array[j]);
+	}
+}
+
+/**
+ * hl_secure_block - locally memsets a block to 0
+ *
+ * @hdev: pointer to hl_device structure
+ * @sgs_array: pb array to clear
+ * @array_size: blocks array size
+ *
+ */
+void hl_secure_block(struct hl_device *hdev,
+		struct hl_block_glbl_sec sgs_array[], int array_size)
+{
+	int i;
+
+	for (i = 0 ; i < array_size ; i++)
+		memset((char *)(sgs_array[i].sec_array), 0,
+			HL_BLOCK_GLBL_SEC_SIZE);
+}
+
+/**
+ * hl_init_pb_with_mask - set selected pb instances with mask in HW according
+ *                        to given configuration
+ *
+ * @hdev: pointer to hl_device structure
+ * @num_dcores: number of decores to apply configuration to
+ *              set to HL_PB_SHARED if need to apply only once
+ * @dcore_offset: offset between dcores
+ * @num_instances: number of instances to apply configuration to
+ * @instance_offset: offset between instances
+ * @pb_blocks: blocks array
+ * @blocks_array_size: blocks array size
+ * @user_regs_array: unsecured register array
+ * @user_regs_array_size: unsecured register array size
+ * @mask: enabled instances mask: 1- enabled, 0- disabled
+ */
+int hl_init_pb_with_mask(struct hl_device *hdev, u32 num_dcores,
+		u32 dcore_offset, u32 num_instances, u32 instance_offset,
+		const u32 pb_blocks[], u32 blocks_array_size,
+		const u32 *user_regs_array, u32 user_regs_array_size, u64 mask)
+{
+	int i, j;
+	struct hl_block_glbl_sec *glbl_sec;
+
+	glbl_sec = kcalloc(blocks_array_size,
+			sizeof(struct hl_block_glbl_sec),
+			GFP_KERNEL);
+	if (!glbl_sec)
+		return -ENOMEM;
+
+	hl_secure_block(hdev, glbl_sec, blocks_array_size);
+	hl_unsecure_registers(hdev, user_regs_array, user_regs_array_size, 0,
+			pb_blocks, glbl_sec, blocks_array_size);
+
+	/* Fill all blocks with the same configuration */
+	for (i = 0 ; i < num_dcores ; i++) {
+		for (j = 0 ; j < num_instances ; j++) {
+			int seq = i * num_instances + j;
+
+			if (!(mask & BIT_ULL(seq)))
+				continue;
+
+			hl_config_glbl_sec(hdev, pb_blocks, glbl_sec,
+					i * dcore_offset + j * instance_offset,
+					blocks_array_size);
+		}
+	}
+
+	kfree(glbl_sec);
+
+	return 0;
+}
+
+/**
+ * hl_init_pb - set pb in HW according to given configuration
+ *
+ * @hdev: pointer to hl_device structure
+ * @num_dcores: number of decores to apply configuration to
+ *              set to HL_PB_SHARED if need to apply only once
+ * @dcore_offset: offset between dcores
+ * @num_instances: number of instances to apply configuration to
+ * @instance_offset: offset between instances
+ * @pb_blocks: blocks array
+ * @blocks_array_size: blocks array size
+ * @user_regs_array: unsecured register array
+ * @user_regs_array_size: unsecured register array size
+ *
+ */
+int hl_init_pb(struct hl_device *hdev, u32 num_dcores, u32 dcore_offset,
+		u32 num_instances, u32 instance_offset,
+		const u32 pb_blocks[], u32 blocks_array_size,
+		const u32 *user_regs_array, u32 user_regs_array_size)
+{
+	return hl_init_pb_with_mask(hdev, num_dcores, dcore_offset,
+			num_instances, instance_offset, pb_blocks,
+			blocks_array_size, user_regs_array,
+			user_regs_array_size, ULLONG_MAX);
+}
+
+/**
+ * hl_init_pb_ranges_with_mask - set pb instances using mask in HW according to
+ *                               given configuration unsecurring registers
+ *                               ranges instead of specific registers
+ *
+ * @hdev: pointer to hl_device structure
+ * @num_dcores: number of decores to apply configuration to
+ *              set to HL_PB_SHARED if need to apply only once
+ * @dcore_offset: offset between dcores
+ * @num_instances: number of instances to apply configuration to
+ * @instance_offset: offset between instances
+ * @pb_blocks: blocks array
+ * @blocks_array_size: blocks array size
+ * @user_regs_range_array: unsecured register range array
+ * @user_regs_range_array_size: unsecured register range array size
+ * @mask: enabled instances mask: 1- enabled, 0- disabled
+ */
+int hl_init_pb_ranges_with_mask(struct hl_device *hdev, u32 num_dcores,
+		u32 dcore_offset, u32 num_instances, u32 instance_offset,
+		const u32 pb_blocks[], u32 blocks_array_size,
+		const struct range *user_regs_range_array,
+		u32 user_regs_range_array_size, u64 mask)
+{
+	int i, j, rc = 0;
+	struct hl_block_glbl_sec *glbl_sec;
+
+	glbl_sec = kcalloc(blocks_array_size,
+			sizeof(struct hl_block_glbl_sec),
+			GFP_KERNEL);
+	if (!glbl_sec)
+		return -ENOMEM;
+
+	hl_secure_block(hdev, glbl_sec, blocks_array_size);
+	rc = hl_unsecure_registers_range(hdev, user_regs_range_array,
+			user_regs_range_array_size, 0, pb_blocks, glbl_sec,
+			blocks_array_size);
+	if (rc)
+		goto free_glbl_sec;
+
+	/* Fill all blocks with the same configuration */
+	for (i = 0 ; i < num_dcores ; i++) {
+		for (j = 0 ; j < num_instances ; j++) {
+			int seq = i * num_instances + j;
+
+			if (!(mask & BIT_ULL(seq)))
+				continue;
+
+			hl_config_glbl_sec(hdev, pb_blocks, glbl_sec,
+					i * dcore_offset + j * instance_offset,
+					blocks_array_size);
+		}
+	}
+
+free_glbl_sec:
+	kfree(glbl_sec);
+
+	return rc;
+}
+
+/**
+ * hl_init_pb_ranges - set pb in HW according to given configuration unsecurring
+ *                     registers ranges instead of specific registers
+ *
+ * @hdev: pointer to hl_device structure
+ * @num_dcores: number of decores to apply configuration to
+ *              set to HL_PB_SHARED if need to apply only once
+ * @dcore_offset: offset between dcores
+ * @num_instances: number of instances to apply configuration to
+ * @instance_offset: offset between instances
+ * @pb_blocks: blocks array
+ * @blocks_array_size: blocks array size
+ * @user_regs_range_array: unsecured register range array
+ * @user_regs_range_array_size: unsecured register range array size
+ *
+ */
+int hl_init_pb_ranges(struct hl_device *hdev, u32 num_dcores,
+		u32 dcore_offset, u32 num_instances, u32 instance_offset,
+		const u32 pb_blocks[], u32 blocks_array_size,
+		const struct range *user_regs_range_array,
+		u32 user_regs_range_array_size)
+{
+	return hl_init_pb_ranges_with_mask(hdev, num_dcores, dcore_offset,
+			num_instances, instance_offset, pb_blocks,
+			blocks_array_size, user_regs_range_array,
+			user_regs_range_array_size, ULLONG_MAX);
+}
+
+/**
+ * hl_init_pb_single_dcore - set pb for a single docre in HW
+ * according to given configuration
+ *
+ * @hdev: pointer to hl_device structure
+ * @dcore_offset: offset from the dcore0
+ * @num_instances: number of instances to apply configuration to
+ * @instance_offset: offset between instances
+ * @pb_blocks: blocks array
+ * @blocks_array_size: blocks array size
+ * @user_regs_array: unsecured register array
+ * @user_regs_array_size: unsecured register array size
+ *
+ */
+int hl_init_pb_single_dcore(struct hl_device *hdev, u32 dcore_offset,
+		u32 num_instances, u32 instance_offset,
+		const u32 pb_blocks[], u32 blocks_array_size,
+		const u32 *user_regs_array, u32 user_regs_array_size)
+{
+	int i, rc = 0;
+	struct hl_block_glbl_sec *glbl_sec;
+
+	glbl_sec = kcalloc(blocks_array_size,
+			sizeof(struct hl_block_glbl_sec),
+			GFP_KERNEL);
+	if (!glbl_sec)
+		return -ENOMEM;
+
+	hl_secure_block(hdev, glbl_sec, blocks_array_size);
+	rc = hl_unsecure_registers(hdev, user_regs_array, user_regs_array_size,
+			0, pb_blocks, glbl_sec, blocks_array_size);
+	if (rc)
+		goto free_glbl_sec;
+
+	/* Fill all blocks with the same configuration */
+	for (i = 0 ; i < num_instances ; i++)
+		hl_config_glbl_sec(hdev, pb_blocks, glbl_sec,
+				dcore_offset + i * instance_offset,
+				blocks_array_size);
+
+free_glbl_sec:
+	kfree(glbl_sec);
+
+	return rc;
+}
+
+/**
+ * hl_init_pb_ranges_single_dcore - set pb for a single docre in HW according
+ *                                  to given configuration unsecurring
+ *                                  registers ranges instead of specific
+ *                                  registers
+ *
+ * @hdev: pointer to hl_device structure
+ * @dcore_offset: offset from the dcore0
+ * @num_instances: number of instances to apply configuration to
+ * @instance_offset: offset between instances
+ * @pb_blocks: blocks array
+ * @blocks_array_size: blocks array size
+ * @user_regs_range_array: unsecured register range array
+ * @user_regs_range_array_size: unsecured register range array size
+ *
+ */
+int hl_init_pb_ranges_single_dcore(struct hl_device *hdev, u32 dcore_offset,
+		u32 num_instances, u32 instance_offset,
+		const u32 pb_blocks[], u32 blocks_array_size,
+		const struct range *user_regs_range_array, u32 user_regs_range_array_size)
+{
+	int i;
+	struct hl_block_glbl_sec *glbl_sec;
+
+	glbl_sec = kcalloc(blocks_array_size,
+			sizeof(struct hl_block_glbl_sec),
+			GFP_KERNEL);
+	if (!glbl_sec)
+		return -ENOMEM;
+
+	hl_secure_block(hdev, glbl_sec, blocks_array_size);
+	hl_unsecure_registers_range(hdev, user_regs_range_array,
+			user_regs_range_array_size, 0, pb_blocks, glbl_sec,
+			blocks_array_size);
+
+	/* Fill all blocks with the same configuration */
+	for (i = 0 ; i < num_instances ; i++)
+		hl_config_glbl_sec(hdev, pb_blocks, glbl_sec,
+				dcore_offset + i * instance_offset,
+				blocks_array_size);
+
+	kfree(glbl_sec);
+
+	return 0;
+}
+
+/**
+ * hl_ack_pb_with_mask - ack pb with mask in HW according to given configuration
+ *
+ * @hdev: pointer to hl_device structure
+ * @num_dcores: number of decores to apply configuration to
+ *              set to HL_PB_SHARED if need to apply only once
+ * @dcore_offset: offset between dcores
+ * @num_instances: number of instances to apply configuration to
+ * @instance_offset: offset between instances
+ * @pb_blocks: blocks array
+ * @blocks_array_size: blocks array size
+ * @mask: enabled instances mask: 1- enabled, 0- disabled
+ *
+ */
+void hl_ack_pb_with_mask(struct hl_device *hdev, u32 num_dcores,
+		u32 dcore_offset, u32 num_instances, u32 instance_offset,
+		const u32 pb_blocks[], u32 blocks_array_size, u64 mask)
+{
+	int i, j;
+
+	/* ack all blocks */
+	for (i = 0 ; i < num_dcores ; i++) {
+		for (j = 0 ; j < num_instances ; j++) {
+			int seq = i * num_instances + j;
+
+			if (!(mask & BIT_ULL(seq)))
+				continue;
+
+			hl_ack_pb_security_violations(hdev, pb_blocks,
+					i * dcore_offset + j * instance_offset,
+					blocks_array_size);
+		}
+	}
+}
+
+/**
+ * hl_ack_pb - ack pb in HW according to given configuration
+ *
+ * @hdev: pointer to hl_device structure
+ * @num_dcores: number of decores to apply configuration to
+ *              set to HL_PB_SHARED if need to apply only once
+ * @dcore_offset: offset between dcores
+ * @num_instances: number of instances to apply configuration to
+ * @instance_offset: offset between instances
+ * @pb_blocks: blocks array
+ * @blocks_array_size: blocks array size
+ *
+ */
+void hl_ack_pb(struct hl_device *hdev, u32 num_dcores, u32 dcore_offset,
+		u32 num_instances, u32 instance_offset,
+		const u32 pb_blocks[], u32 blocks_array_size)
+{
+	hl_ack_pb_with_mask(hdev, num_dcores, dcore_offset, num_instances,
+			instance_offset, pb_blocks, blocks_array_size,
+			ULLONG_MAX);
+}
+
+/**
+ * hl_ack_pb_single_dcore - ack pb for single docre in HW
+ * according to given configuration
+ *
+ * @hdev: pointer to hl_device structure
+ * @dcore_offset: offset from dcore0
+ * @num_instances: number of instances to apply configuration to
+ * @instance_offset: offset between instances
+ * @pb_blocks: blocks array
+ * @blocks_array_size: blocks array size
+ *
+ */
+void hl_ack_pb_single_dcore(struct hl_device *hdev, u32 dcore_offset,
+		u32 num_instances, u32 instance_offset,
+		const u32 pb_blocks[], u32 blocks_array_size)
+{
+	int i;
+
+	/* ack all blocks */
+	for (i = 0 ; i < num_instances ; i++)
+		hl_ack_pb_security_violations(hdev, pb_blocks,
+				dcore_offset + i * instance_offset,
+				blocks_array_size);
+
+}
+
+static u32 hl_automated_get_block_base_addr(struct hl_device *hdev,
+		struct hl_special_block_info *block_info,
+		u32 major, u32 minor, u32 sub_minor)
+{
+	u32 fw_block_base_address = block_info->base_addr +
+			major * block_info->major_offset +
+			minor * block_info->minor_offset +
+			sub_minor * block_info->sub_minor_offset;
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+
+	/* Calculation above returns an address for FW use, and therefore should
+	 * be casted for driver use.
+	 */
+	return (fw_block_base_address - lower_32_bits(prop->cfg_base_address));
+}
+
+static bool hl_check_block_type_exclusion(struct hl_skip_blocks_cfg *skip_blocks_cfg,
+		int block_type)
+{
+	int i;
+
+	/* Check if block type is listed in the exclusion list of block types */
+	for (i = 0 ; i < skip_blocks_cfg->block_types_len ; i++)
+		if (block_type == skip_blocks_cfg->block_types[i])
+			return true;
+
+	return false;
+}
+
+static bool hl_check_block_range_exclusion(struct hl_device *hdev,
+		struct hl_skip_blocks_cfg *skip_blocks_cfg,
+		struct hl_special_block_info *block_info,
+		u32 major, u32 minor, u32 sub_minor)
+{
+	u32 blocks_in_range, block_base_addr_in_range, block_base_addr;
+	int i, j;
+
+	block_base_addr = hl_automated_get_block_base_addr(hdev, block_info,
+			major, minor, sub_minor);
+
+	for (i = 0 ; i < skip_blocks_cfg->block_ranges_len ; i++) {
+		blocks_in_range = (skip_blocks_cfg->block_ranges[i].end -
+				skip_blocks_cfg->block_ranges[i].start) /
+				HL_BLOCK_SIZE + 1;
+		for (j = 0 ; j < blocks_in_range ; j++) {
+			block_base_addr_in_range = skip_blocks_cfg->block_ranges[i].start +
+					j * HL_BLOCK_SIZE;
+			if (block_base_addr == block_base_addr_in_range)
+				return true;
+		}
+	}
+
+	return false;
+}
+
+static int hl_read_glbl_errors(struct hl_device *hdev,
+		u32 blk_idx, u32 major, u32 minor, u32 sub_minor, void *data)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct hl_special_block_info *special_blocks = prop->special_blocks;
+	struct hl_special_block_info *current_block = &special_blocks[blk_idx];
+	u32 glbl_err_addr, glbl_err_cause, addr_val, cause_val, block_base,
+		base = current_block->base_addr - lower_32_bits(prop->cfg_base_address);
+	int i;
+
+	block_base = base + major * current_block->major_offset +
+			minor * current_block->minor_offset +
+			sub_minor * current_block->sub_minor_offset;
+
+	glbl_err_cause = block_base + HL_GLBL_ERR_CAUSE_OFFSET;
+	cause_val = RREG32(glbl_err_cause);
+	if (!cause_val)
+		return 0;
+
+	glbl_err_addr = block_base + HL_GLBL_ERR_ADDR_OFFSET;
+	addr_val = RREG32(glbl_err_addr);
+
+	for (i = 0 ; i <= prop->glbl_err_max_cause_num ; i++) {
+		if (cause_val & BIT(i))
+			dev_err_ratelimited(hdev->dev,
+					"%s, addr %#llx\n",
+					hl_glbl_error_cause[i],
+					prop->cfg_base_address + block_base +
+						FIELD_GET(HL_GLBL_ERR_ADDRESS_MASK, addr_val));
+	}
+
+	WREG32(glbl_err_cause, cause_val);
+
+	return 0;
+}
+
+void hl_check_for_glbl_errors(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct hl_special_blocks_cfg special_blocks_cfg;
+	struct iterate_special_ctx glbl_err_iter;
+	int rc;
+
+	memset(&special_blocks_cfg, 0, sizeof(special_blocks_cfg));
+	special_blocks_cfg.skip_blocks_cfg = &prop->skip_special_blocks_cfg;
+
+	glbl_err_iter.fn = &hl_read_glbl_errors;
+	glbl_err_iter.data = &special_blocks_cfg;
+
+	rc = hl_iterate_special_blocks(hdev, &glbl_err_iter);
+	if (rc)
+		dev_err_ratelimited(hdev->dev,
+			"Could not iterate special blocks, glbl error check failed\n");
+}
+
+int hl_iterate_special_blocks(struct hl_device *hdev, struct iterate_special_ctx *ctx)
+{
+	struct hl_special_blocks_cfg *special_blocks_cfg =
+			(struct hl_special_blocks_cfg *)ctx->data;
+	struct hl_skip_blocks_cfg *skip_blocks_cfg =
+			special_blocks_cfg->skip_blocks_cfg;
+	u32 major, minor, sub_minor, blk_idx, num_blocks;
+	struct hl_special_block_info *block_info_arr;
+	int rc;
+
+	block_info_arr = hdev->asic_prop.special_blocks;
+	if (!block_info_arr)
+		return -EINVAL;
+
+	num_blocks = hdev->asic_prop.num_of_special_blocks;
+
+	for (blk_idx = 0 ; blk_idx < num_blocks ; blk_idx++, block_info_arr++) {
+		if (hl_check_block_type_exclusion(skip_blocks_cfg, block_info_arr->block_type))
+			continue;
+
+		for (major = 0 ; major < block_info_arr->major ; major++) {
+			minor = 0;
+			do {
+				sub_minor = 0;
+				do {
+					if ((hl_check_block_range_exclusion(hdev,
+							skip_blocks_cfg, block_info_arr,
+							major, minor, sub_minor)) ||
+						(skip_blocks_cfg->skip_block_hook &&
+						skip_blocks_cfg->skip_block_hook(hdev,
+							special_blocks_cfg,
+							blk_idx, major, minor, sub_minor))) {
+						sub_minor++;
+						continue;
+					}
+
+					rc = ctx->fn(hdev, blk_idx, major, minor,
+								sub_minor, ctx->data);
+					if (rc)
+						return rc;
+
+					sub_minor++;
+				} while (sub_minor < block_info_arr->sub_minor);
+
+				minor++;
+			} while (minor < block_info_arr->minor);
+		}
+	}
+
+	return 0;
+}
diff --git a/drivers/accel/habanalabs/common/security.h b/drivers/accel/habanalabs/common/security.h
new file mode 100644
index 000000000000..476f70687c09
--- /dev/null
+++ b/drivers/accel/habanalabs/common/security.h
@@ -0,0 +1,162 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2022 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+#ifndef SECURITY_H_
+#define SECURITY_H_
+
+#include <linux/io-64-nonatomic-lo-hi.h>
+
+struct hl_device;
+
+/* special blocks */
+#define HL_GLBL_ERR_ADDRESS_MASK	GENMASK(11, 0)
+/* GLBL_ERR_ADDR register offset from the start of the block */
+#define HL_GLBL_ERR_ADDR_OFFSET		0xF44
+/* GLBL_ERR_CAUSE register offset from the start of the block */
+#define HL_GLBL_ERR_CAUSE_OFFSET	0xF48
+
+/*
+ * struct hl_special_block_info - stores address details of a particular type of
+ * IP block which has a SPECIAL part.
+ *
+ * @block_type: block type as described in every ASIC's block_types enum.
+ * @base_addr: base address of the first block of particular type,
+ *             e.g., address of NIC0_UMR0_0 of 'NIC_UMR' block.
+ * @major: number of major blocks of particular type.
+ * @minor: number of minor blocks of particular type.
+ * @sub_minor: number of sub minor blocks of particular type.
+ * @major_offset: address gap between 2 consecutive major blocks of particular type,
+ *                e.g., offset between NIC0_UMR0_0 and NIC1_UMR0_0 is 0x80000.
+ * @minor_offset: address gap between 2 consecutive minor blocks of particular type,
+ *                e.g., offset between NIC0_UMR0_0 and NIC0_UMR1_0 is 0x20000.
+ * @sub_minor_offset: address gap between 2 consecutive sub_minor blocks of particular
+ *                    type, e.g., offset between NIC0_UMR0_0 and NIC0_UMR0_1 is 0x1000.
+ *
+ * e.g., in Gaudi2, NIC_UMR blocks can be interpreted as:
+ * NIC<major>_UMR<minor>_<sub_minor> where major=12, minor=2, sub_minor=15.
+ * In other words, for each of 12 major numbers (i.e 0 to 11) there are
+ * 2 blocks with different minor numbers (i.e. 0 to 1). Again, for each minor
+ * number there are 15 blocks with different sub_minor numbers (i.e. 0 to 14).
+ * So different blocks are NIC0_UMR0_0, NIC0_UMR0_1, ..., NIC0_UMR1_0, ....,
+ * NIC11_UMR1_14.
+ *
+ * Struct's formatted data is located in the SOL-based auto-generated protbits headers.
+ */
+struct hl_special_block_info {
+	int block_type;
+	u32 base_addr;
+	u32 major;
+	u32 minor;
+	u32 sub_minor;
+	u32 major_offset;
+	u32 minor_offset;
+	u32 sub_minor_offset;
+};
+
+/*
+ * struct hl_automated_pb_cfg - represents configurations of a particular type
+ * of IP block which has protection bits.
+ *
+ * @addr: address details as described in hl_automation_pb_addr struct.
+ * @prot_map: each bit corresponds to one among 32 protection configuration regs
+ *            (e.g., SPECIAL_GLBL_PRIV). '1' means 0xffffffff and '0' means 0x0
+ *            to be written into the corresponding protection configuration reg.
+ *            This bit is meaningful if same bit in data_map is 0, otherwise ignored.
+ * @data_map: each bit corresponds to one among 32 protection configuration regs
+ *            (e.g., SPECIAL_GLBL_PRIV). '1' means corresponding protection
+ *            configuration reg is to be written with a value in array pointed
+ *            by 'data', otherwise the value is decided by 'prot_map'.
+ * @data: pointer to data array which stores the config value(s) to be written
+ *            to corresponding protection configuration reg(s).
+ * @data_size: size of the data array.
+ *
+ * Each bit of 'data_map' and 'prot_map' fields corresponds to one among 32
+ * protection configuration registers e.g., SPECIAL GLBL PRIV regs (starting at
+ * offset 0xE80). '1' in 'data_map' means protection configuration to be done
+ * using configuration in data array. '0' in 'data_map" means protection
+ * configuration to be done as per the value of corresponding bit in 'prot_map'.
+ * '1' in 'prot_map' means the register to be programmed with 0xFFFFFFFF
+ * (all non-protected). '0' in 'prot_map' means the register to be programmed
+ * with 0x0 (all protected).
+ *
+ * e.g., prot_map = 0x00000001, data_map = 0xC0000000 , data = {0xff, 0x12}
+ * SPECIAL_GLBL_PRIV[0] = 0xFFFFFFFF
+ * SPECIAL_GLBL_PRIV[1..29] = 0x0
+ * SPECIAL_GLBL_PRIV[30] = 0xFF
+ * SPECIAL_GLBL_PRIV[31] = 0x12
+ */
+struct hl_automated_pb_cfg {
+	struct hl_special_block_info addr;
+	u32 prot_map;
+	u32 data_map;
+	const u32 *data;
+	u8 data_size;
+};
+
+/* struct hl_special_blocks_cfg - holds special blocks cfg data.
+ *
+ * @priv_automated_pb_cfg: points to the main privileged PB array.
+ * @sec_automated_pb_cfg: points to the main secured PB array.
+ * @skip_blocks_cfg: holds arrays of block types & block ranges to be excluded.
+ * @priv_cfg_size: size of the main privileged PB array.
+ * @sec_cfg_size: size of the main secured PB array.
+ * @prot_lvl_priv: indication if it's a privileged/secured PB configurations.
+ */
+struct hl_special_blocks_cfg {
+	struct hl_automated_pb_cfg *priv_automated_pb_cfg;
+	struct hl_automated_pb_cfg *sec_automated_pb_cfg;
+	struct hl_skip_blocks_cfg *skip_blocks_cfg;
+	u32 priv_cfg_size;
+	u32 sec_cfg_size;
+	u8 prot_lvl_priv;
+};
+
+/* Automated security */
+
+/* struct hl_skip_blocks_cfg - holds arrays of block types & block ranges to be
+ * excluded from special blocks configurations.
+ *
+ * @block_types: an array of block types NOT to be configured.
+ * @block_types_len: len of an array of block types not to be configured.
+ * @block_ranges: an array of block ranges not to be configured.
+ * @block_ranges_len: len of an array of block ranges not to be configured.
+ * @skip_block_hook: hook that will be called before initializing special blocks.
+ */
+struct hl_skip_blocks_cfg {
+	int *block_types;
+	size_t block_types_len;
+	struct range *block_ranges;
+	size_t block_ranges_len;
+	bool (*skip_block_hook)(struct hl_device *hdev,
+				struct hl_special_blocks_cfg *special_blocks_cfg,
+				u32 blk_idx, u32 major, u32 minor, u32 sub_minor);
+};
+
+/**
+ * struct iterate_special_ctx - HW module special block iterator
+ * @fn: function to apply to each HW module special block instance
+ * @data: optional internal data to the function iterator
+ */
+struct iterate_special_ctx {
+	/*
+	 * callback for the HW module special block iterator
+	 * @hdev: pointer to the habanalabs device structure
+	 * @block_id: block (ASIC specific definition can be dcore/hdcore)
+	 * @major: major block index within block_id
+	 * @minor: minor block index within the major block
+	 * @sub_minor: sub_minor block index within the minor block
+	 * @data: function specific data
+	 */
+	int (*fn)(struct hl_device *hdev, u32 block_id, u32 major, u32 minor,
+						u32 sub_minor, void *data);
+	void *data;
+};
+
+int hl_iterate_special_blocks(struct hl_device *hdev, struct iterate_special_ctx *ctx);
+void hl_check_for_glbl_errors(struct hl_device *hdev);
+
+#endif /* SECURITY_H_ */
diff --git a/drivers/accel/habanalabs/common/state_dump.c b/drivers/accel/habanalabs/common/state_dump.c
new file mode 100644
index 000000000000..3a9931f24259
--- /dev/null
+++ b/drivers/accel/habanalabs/common/state_dump.c
@@ -0,0 +1,718 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Copyright 2021 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ */
+
+#include <linux/vmalloc.h>
+#include <uapi/drm/habanalabs_accel.h>
+#include "habanalabs.h"
+
+/**
+ * hl_format_as_binary - helper function, format an integer as binary
+ *                       using supplied scratch buffer
+ * @buf: the buffer to use
+ * @buf_len: buffer capacity
+ * @n: number to format
+ *
+ * Returns pointer to buffer
+ */
+char *hl_format_as_binary(char *buf, size_t buf_len, u32 n)
+{
+	int i;
+	u32 bit;
+	bool leading0 = true;
+	char *wrptr = buf;
+
+	if (buf_len > 0 && buf_len < 3) {
+		*wrptr = '\0';
+		return buf;
+	}
+
+	wrptr[0] = '0';
+	wrptr[1] = 'b';
+	wrptr += 2;
+	/* Remove 3 characters from length for '0b' and '\0' termination */
+	buf_len -= 3;
+
+	for (i = 0; i < sizeof(n) * BITS_PER_BYTE && buf_len; ++i, n <<= 1) {
+		/* Writing bit calculation in one line would cause a false
+		 * positive static code analysis error, so splitting.
+		 */
+		bit = n & (1 << (sizeof(n) * BITS_PER_BYTE - 1));
+		bit = !!bit;
+		leading0 &= !bit;
+		if (!leading0) {
+			*wrptr = '0' + bit;
+			++wrptr;
+		}
+	}
+
+	*wrptr = '\0';
+
+	return buf;
+}
+
+/**
+ * resize_to_fit - helper function, resize buffer to fit given amount of data
+ * @buf: destination buffer double pointer
+ * @size: pointer to the size container
+ * @desired_size: size the buffer must contain
+ *
+ * Returns 0 on success or error code on failure.
+ * On success, the size of buffer is at least desired_size. Buffer is allocated
+ * via vmalloc and must be freed with vfree.
+ */
+static int resize_to_fit(char **buf, size_t *size, size_t desired_size)
+{
+	char *resized_buf;
+	size_t new_size;
+
+	if (*size >= desired_size)
+		return 0;
+
+	/* Not enough space to print all, have to resize */
+	new_size = max_t(size_t, PAGE_SIZE, round_up(desired_size, PAGE_SIZE));
+	resized_buf = vmalloc(new_size);
+	if (!resized_buf)
+		return -ENOMEM;
+	memcpy(resized_buf, *buf, *size);
+	vfree(*buf);
+	*buf = resized_buf;
+	*size = new_size;
+
+	return 1;
+}
+
+/**
+ * hl_snprintf_resize() - print formatted data to buffer, resize as needed
+ * @buf: buffer double pointer, to be written to and resized, must be either
+ *       NULL or allocated with vmalloc.
+ * @size: current size of the buffer
+ * @offset: current offset to write to
+ * @format: format of the data
+ *
+ * This function will write formatted data into the buffer. If buffer is not
+ * large enough, it will be resized using vmalloc. Size may be modified if the
+ * buffer was resized, offset will be advanced by the number of bytes written
+ * not including the terminating character
+ *
+ * Returns 0 on success or error code on failure
+ *
+ * Note that the buffer has to be manually released using vfree.
+ */
+int hl_snprintf_resize(char **buf, size_t *size, size_t *offset,
+			   const char *format, ...)
+{
+	va_list args;
+	size_t length;
+	int rc;
+
+	if (*buf == NULL && (*size != 0 || *offset != 0))
+		return -EINVAL;
+
+	va_start(args, format);
+	length = vsnprintf(*buf + *offset, *size - *offset, format, args);
+	va_end(args);
+
+	rc = resize_to_fit(buf, size, *offset + length + 1);
+	if (rc < 0)
+		return rc;
+	else if (rc > 0) {
+		/* Resize was needed, write again */
+		va_start(args, format);
+		length = vsnprintf(*buf + *offset, *size - *offset, format,
+				   args);
+		va_end(args);
+	}
+
+	*offset += length;
+
+	return 0;
+}
+
+/**
+ * hl_sync_engine_to_string - convert engine type enum to string literal
+ * @engine_type: engine type (TPC/MME/DMA)
+ *
+ * Return the resolved string literal
+ */
+const char *hl_sync_engine_to_string(enum hl_sync_engine_type engine_type)
+{
+	switch (engine_type) {
+	case ENGINE_DMA:
+		return "DMA";
+	case ENGINE_MME:
+		return "MME";
+	case ENGINE_TPC:
+		return "TPC";
+	}
+	return "Invalid Engine Type";
+}
+
+/**
+ * hl_print_resize_sync_engine - helper function, format engine name and ID
+ * using hl_snprintf_resize
+ * @buf: destination buffer double pointer to be used with hl_snprintf_resize
+ * @size: pointer to the size container
+ * @offset: pointer to the offset container
+ * @engine_type: engine type (TPC/MME/DMA)
+ * @engine_id: engine numerical id
+ *
+ * Returns 0 on success or error code on failure
+ */
+static int hl_print_resize_sync_engine(char **buf, size_t *size, size_t *offset,
+				enum hl_sync_engine_type engine_type,
+				u32 engine_id)
+{
+	return hl_snprintf_resize(buf, size, offset, "%s%u",
+			hl_sync_engine_to_string(engine_type), engine_id);
+}
+
+/**
+ * hl_state_dump_get_sync_name - transform sync object id to name if available
+ * @hdev: pointer to the device
+ * @sync_id: sync object id
+ *
+ * Returns a name literal or NULL if not resolved.
+ * Note: returning NULL shall not be considered as a failure, as not all
+ * sync objects are named.
+ */
+const char *hl_state_dump_get_sync_name(struct hl_device *hdev, u32 sync_id)
+{
+	struct hl_state_dump_specs *sds = &hdev->state_dump_specs;
+	struct hl_hw_obj_name_entry *entry;
+
+	hash_for_each_possible(sds->so_id_to_str_tb, entry,
+				node, sync_id)
+		if (sync_id == entry->id)
+			return entry->name;
+
+	return NULL;
+}
+
+/**
+ * hl_state_dump_get_monitor_name - transform monitor object dump to monitor
+ * name if available
+ * @hdev: pointer to the device
+ * @mon: monitor state dump
+ *
+ * Returns a name literal or NULL if not resolved.
+ * Note: returning NULL shall not be considered as a failure, as not all
+ * monitors are named.
+ */
+const char *hl_state_dump_get_monitor_name(struct hl_device *hdev,
+					struct hl_mon_state_dump *mon)
+{
+	struct hl_state_dump_specs *sds = &hdev->state_dump_specs;
+	struct hl_hw_obj_name_entry *entry;
+
+	hash_for_each_possible(sds->monitor_id_to_str_tb,
+				entry, node, mon->id)
+		if (mon->id == entry->id)
+			return entry->name;
+
+	return NULL;
+}
+
+/**
+ * hl_state_dump_free_sync_to_engine_map - free sync object to engine map
+ * @map: sync object to engine map
+ *
+ * Note: generic free implementation, the allocation is implemented per ASIC.
+ */
+void hl_state_dump_free_sync_to_engine_map(struct hl_sync_to_engine_map *map)
+{
+	struct hl_sync_to_engine_map_entry *entry;
+	struct hlist_node *tmp_node;
+	int i;
+
+	hash_for_each_safe(map->tb, i, tmp_node, entry, node) {
+		hash_del(&entry->node);
+		kfree(entry);
+	}
+}
+
+/**
+ * hl_state_dump_get_sync_to_engine - transform sync_id to
+ * hl_sync_to_engine_map_entry if available for current id
+ * @map: sync object to engine map
+ * @sync_id: sync object id
+ *
+ * Returns the translation entry if found or NULL if not.
+ * Note, returned NULL shall not be considered as a failure as the map
+ * does not cover all possible, it is a best effort sync ids.
+ */
+static struct hl_sync_to_engine_map_entry *
+hl_state_dump_get_sync_to_engine(struct hl_sync_to_engine_map *map, u32 sync_id)
+{
+	struct hl_sync_to_engine_map_entry *entry;
+
+	hash_for_each_possible(map->tb, entry, node, sync_id)
+		if (entry->sync_id == sync_id)
+			return entry;
+	return NULL;
+}
+
+/**
+ * hl_state_dump_read_sync_objects - read sync objects array
+ * @hdev: pointer to the device
+ * @index: sync manager block index starting with E_N
+ *
+ * Returns array of size SP_SYNC_OBJ_AMOUNT on success or NULL on failure
+ */
+static u32 *hl_state_dump_read_sync_objects(struct hl_device *hdev, u32 index)
+{
+	struct hl_state_dump_specs *sds = &hdev->state_dump_specs;
+	u32 *sync_objects;
+	s64 base_addr; /* Base addr can be negative */
+	int i;
+
+	base_addr = sds->props[SP_SYNC_OBJ_BASE_ADDR] +
+			sds->props[SP_NEXT_SYNC_OBJ_ADDR] * index;
+
+	sync_objects = vmalloc(sds->props[SP_SYNC_OBJ_AMOUNT] * sizeof(u32));
+	if (!sync_objects)
+		return NULL;
+
+	for (i = 0; i < sds->props[SP_SYNC_OBJ_AMOUNT]; ++i)
+		sync_objects[i] = RREG32(base_addr + i * sizeof(u32));
+
+	return sync_objects;
+}
+
+/**
+ * hl_state_dump_free_sync_objects - free sync objects array allocated by
+ * hl_state_dump_read_sync_objects
+ * @sync_objects: sync objects array
+ */
+static void hl_state_dump_free_sync_objects(u32 *sync_objects)
+{
+	vfree(sync_objects);
+}
+
+
+/**
+ * hl_state_dump_print_syncs_single_block - print active sync objects on a
+ * single block
+ * @hdev: pointer to the device
+ * @index: sync manager block index starting with E_N
+ * @buf: destination buffer double pointer to be used with hl_snprintf_resize
+ * @size: pointer to the size container
+ * @offset: pointer to the offset container
+ * @map: sync engines names map
+ *
+ * Returns 0 on success or error code on failure
+ */
+static int
+hl_state_dump_print_syncs_single_block(struct hl_device *hdev, u32 index,
+				char **buf, size_t *size, size_t *offset,
+				struct hl_sync_to_engine_map *map)
+{
+	struct hl_state_dump_specs *sds = &hdev->state_dump_specs;
+	const char *sync_name;
+	u32 *sync_objects = NULL;
+	int rc = 0, i;
+
+	if (sds->sync_namager_names) {
+		rc = hl_snprintf_resize(
+			buf, size, offset, "%s\n",
+			sds->sync_namager_names[index]);
+		if (rc)
+			goto out;
+	}
+
+	sync_objects = hl_state_dump_read_sync_objects(hdev, index);
+	if (!sync_objects) {
+		rc = -ENOMEM;
+		goto out;
+	}
+
+	for (i = 0; i < sds->props[SP_SYNC_OBJ_AMOUNT]; ++i) {
+		struct hl_sync_to_engine_map_entry *entry;
+		u64 sync_object_addr;
+
+		if (!sync_objects[i])
+			continue;
+
+		sync_object_addr = sds->props[SP_SYNC_OBJ_BASE_ADDR] +
+				sds->props[SP_NEXT_SYNC_OBJ_ADDR] * index +
+				i * sizeof(u32);
+
+		rc = hl_snprintf_resize(buf, size, offset, "sync id: %u", i);
+		if (rc)
+			goto free_sync_objects;
+		sync_name = hl_state_dump_get_sync_name(hdev, i);
+		if (sync_name) {
+			rc = hl_snprintf_resize(buf, size, offset, " %s",
+						sync_name);
+			if (rc)
+				goto free_sync_objects;
+		}
+		rc = hl_snprintf_resize(buf, size, offset, ", value: %u",
+					sync_objects[i]);
+		if (rc)
+			goto free_sync_objects;
+
+		/* Append engine string */
+		entry = hl_state_dump_get_sync_to_engine(map,
+			(u32)sync_object_addr);
+		if (entry) {
+			rc = hl_snprintf_resize(buf, size, offset,
+						", Engine: ");
+			if (rc)
+				goto free_sync_objects;
+			rc = hl_print_resize_sync_engine(buf, size, offset,
+						entry->engine_type,
+						entry->engine_id);
+			if (rc)
+				goto free_sync_objects;
+		}
+
+		rc = hl_snprintf_resize(buf, size, offset, "\n");
+		if (rc)
+			goto free_sync_objects;
+	}
+
+free_sync_objects:
+	hl_state_dump_free_sync_objects(sync_objects);
+out:
+	return rc;
+}
+
+/**
+ * hl_state_dump_print_syncs - print active sync objects
+ * @hdev: pointer to the device
+ * @buf: destination buffer double pointer to be used with hl_snprintf_resize
+ * @size: pointer to the size container
+ * @offset: pointer to the offset container
+ *
+ * Returns 0 on success or error code on failure
+ */
+static int hl_state_dump_print_syncs(struct hl_device *hdev,
+					char **buf, size_t *size,
+					size_t *offset)
+
+{
+	struct hl_state_dump_specs *sds = &hdev->state_dump_specs;
+	struct hl_sync_to_engine_map *map;
+	u32 index;
+	int rc = 0;
+
+	map = kzalloc(sizeof(*map), GFP_KERNEL);
+	if (!map)
+		return -ENOMEM;
+
+	rc = sds->funcs.gen_sync_to_engine_map(hdev, map);
+	if (rc)
+		goto free_map_mem;
+
+	rc = hl_snprintf_resize(buf, size, offset, "Non zero sync objects:\n");
+	if (rc)
+		goto out;
+
+	if (sds->sync_namager_names) {
+		for (index = 0; sds->sync_namager_names[index]; ++index) {
+			rc = hl_state_dump_print_syncs_single_block(
+				hdev, index, buf, size, offset, map);
+			if (rc)
+				goto out;
+		}
+	} else {
+		for (index = 0; index < sds->props[SP_NUM_CORES]; ++index) {
+			rc = hl_state_dump_print_syncs_single_block(
+				hdev, index, buf, size, offset, map);
+			if (rc)
+				goto out;
+		}
+	}
+
+out:
+	hl_state_dump_free_sync_to_engine_map(map);
+free_map_mem:
+	kfree(map);
+
+	return rc;
+}
+
+/**
+ * hl_state_dump_alloc_read_sm_block_monitors - read monitors for a specific
+ * block
+ * @hdev: pointer to the device
+ * @index: sync manager block index starting with E_N
+ *
+ * Returns an array of monitor data of size SP_MONITORS_AMOUNT or NULL
+ * on error
+ */
+static struct hl_mon_state_dump *
+hl_state_dump_alloc_read_sm_block_monitors(struct hl_device *hdev, u32 index)
+{
+	struct hl_state_dump_specs *sds = &hdev->state_dump_specs;
+	struct hl_mon_state_dump *monitors;
+	s64 base_addr; /* Base addr can be negative */
+	int i;
+
+	monitors = vmalloc(sds->props[SP_MONITORS_AMOUNT] *
+			   sizeof(struct hl_mon_state_dump));
+	if (!monitors)
+		return NULL;
+
+	base_addr = sds->props[SP_NEXT_SYNC_OBJ_ADDR] * index;
+
+	for (i = 0; i < sds->props[SP_MONITORS_AMOUNT]; ++i) {
+		monitors[i].id = i;
+		monitors[i].wr_addr_low =
+			RREG32(base_addr + sds->props[SP_MON_OBJ_WR_ADDR_LOW] +
+				i * sizeof(u32));
+
+		monitors[i].wr_addr_high =
+			RREG32(base_addr + sds->props[SP_MON_OBJ_WR_ADDR_HIGH] +
+				i * sizeof(u32));
+
+		monitors[i].wr_data =
+			RREG32(base_addr + sds->props[SP_MON_OBJ_WR_DATA] +
+				i * sizeof(u32));
+
+		monitors[i].arm_data =
+			RREG32(base_addr + sds->props[SP_MON_OBJ_ARM_DATA] +
+				i * sizeof(u32));
+
+		monitors[i].status =
+			RREG32(base_addr + sds->props[SP_MON_OBJ_STATUS] +
+				i * sizeof(u32));
+	}
+
+	return monitors;
+}
+
+/**
+ * hl_state_dump_free_monitors - free the monitors structure
+ * @monitors: monitors array created with
+ *            hl_state_dump_alloc_read_sm_block_monitors
+ */
+static void hl_state_dump_free_monitors(struct hl_mon_state_dump *monitors)
+{
+	vfree(monitors);
+}
+
+/**
+ * hl_state_dump_print_monitors_single_block - print active monitors on a
+ * single block
+ * @hdev: pointer to the device
+ * @index: sync manager block index starting with E_N
+ * @buf: destination buffer double pointer to be used with hl_snprintf_resize
+ * @size: pointer to the size container
+ * @offset: pointer to the offset container
+ *
+ * Returns 0 on success or error code on failure
+ */
+static int hl_state_dump_print_monitors_single_block(struct hl_device *hdev,
+						u32 index,
+						char **buf, size_t *size,
+						size_t *offset)
+{
+	struct hl_state_dump_specs *sds = &hdev->state_dump_specs;
+	struct hl_mon_state_dump *monitors = NULL;
+	int rc = 0, i;
+
+	if (sds->sync_namager_names) {
+		rc = hl_snprintf_resize(
+			buf, size, offset, "%s\n",
+			sds->sync_namager_names[index]);
+		if (rc)
+			goto out;
+	}
+
+	monitors = hl_state_dump_alloc_read_sm_block_monitors(hdev, index);
+	if (!monitors) {
+		rc = -ENOMEM;
+		goto out;
+	}
+
+	for (i = 0; i < sds->props[SP_MONITORS_AMOUNT]; ++i) {
+		if (!(sds->funcs.monitor_valid(&monitors[i])))
+			continue;
+
+		/* Monitor is valid, dump it */
+		rc = sds->funcs.print_single_monitor(buf, size, offset, hdev,
+							&monitors[i]);
+		if (rc)
+			goto free_monitors;
+
+		hl_snprintf_resize(buf, size, offset, "\n");
+	}
+
+free_monitors:
+	hl_state_dump_free_monitors(monitors);
+out:
+	return rc;
+}
+
+/**
+ * hl_state_dump_print_monitors - print active monitors
+ * @hdev: pointer to the device
+ * @buf: destination buffer double pointer to be used with hl_snprintf_resize
+ * @size: pointer to the size container
+ * @offset: pointer to the offset container
+ *
+ * Returns 0 on success or error code on failure
+ */
+static int hl_state_dump_print_monitors(struct hl_device *hdev,
+					char **buf, size_t *size,
+					size_t *offset)
+{
+	struct hl_state_dump_specs *sds = &hdev->state_dump_specs;
+	u32 index;
+	int rc = 0;
+
+	rc = hl_snprintf_resize(buf, size, offset,
+		"Valid (armed) monitor objects:\n");
+	if (rc)
+		goto out;
+
+	if (sds->sync_namager_names) {
+		for (index = 0; sds->sync_namager_names[index]; ++index) {
+			rc = hl_state_dump_print_monitors_single_block(
+				hdev, index, buf, size, offset);
+			if (rc)
+				goto out;
+		}
+	} else {
+		for (index = 0; index < sds->props[SP_NUM_CORES]; ++index) {
+			rc = hl_state_dump_print_monitors_single_block(
+				hdev, index, buf, size, offset);
+			if (rc)
+				goto out;
+		}
+	}
+
+out:
+	return rc;
+}
+
+/**
+ * hl_state_dump_print_engine_fences - print active fences for a specific
+ * engine
+ * @hdev: pointer to the device
+ * @engine_type: engine type to use
+ * @buf: destination buffer double pointer to be used with hl_snprintf_resize
+ * @size: pointer to the size container
+ * @offset: pointer to the offset container
+ */
+static int
+hl_state_dump_print_engine_fences(struct hl_device *hdev,
+				  enum hl_sync_engine_type engine_type,
+				  char **buf, size_t *size, size_t *offset)
+{
+	struct hl_state_dump_specs *sds = &hdev->state_dump_specs;
+	int rc = 0, i, n_fences;
+	u64 base_addr, next_fence;
+
+	switch (engine_type) {
+	case ENGINE_TPC:
+		n_fences = sds->props[SP_NUM_OF_TPC_ENGINES];
+		base_addr = sds->props[SP_TPC0_CMDQ];
+		next_fence = sds->props[SP_NEXT_TPC];
+		break;
+	case ENGINE_MME:
+		n_fences = sds->props[SP_NUM_OF_MME_ENGINES];
+		base_addr = sds->props[SP_MME_CMDQ];
+		next_fence = sds->props[SP_NEXT_MME];
+		break;
+	case ENGINE_DMA:
+		n_fences = sds->props[SP_NUM_OF_DMA_ENGINES];
+		base_addr = sds->props[SP_DMA_CMDQ];
+		next_fence = sds->props[SP_DMA_QUEUES_OFFSET];
+		break;
+	default:
+		return -EINVAL;
+	}
+	for (i = 0; i < n_fences; ++i) {
+		rc = sds->funcs.print_fences_single_engine(
+			hdev,
+			base_addr + next_fence * i +
+				sds->props[SP_FENCE0_CNT_OFFSET],
+			base_addr + next_fence * i +
+				sds->props[SP_CP_STS_OFFSET],
+			engine_type, i, buf, size, offset);
+		if (rc)
+			goto out;
+	}
+out:
+	return rc;
+}
+
+/**
+ * hl_state_dump_print_fences - print active fences
+ * @hdev: pointer to the device
+ * @buf: destination buffer double pointer to be used with hl_snprintf_resize
+ * @size: pointer to the size container
+ * @offset: pointer to the offset container
+ */
+static int hl_state_dump_print_fences(struct hl_device *hdev, char **buf,
+				      size_t *size, size_t *offset)
+{
+	int rc = 0;
+
+	rc = hl_snprintf_resize(buf, size, offset, "Valid (armed) fences:\n");
+	if (rc)
+		goto out;
+
+	rc = hl_state_dump_print_engine_fences(hdev, ENGINE_TPC, buf, size, offset);
+	if (rc)
+		goto out;
+
+	rc = hl_state_dump_print_engine_fences(hdev, ENGINE_MME, buf, size, offset);
+	if (rc)
+		goto out;
+
+	rc = hl_state_dump_print_engine_fences(hdev, ENGINE_DMA, buf, size, offset);
+	if (rc)
+		goto out;
+
+out:
+	return rc;
+}
+
+/**
+ * hl_state_dump() - dump system state
+ * @hdev: pointer to device structure
+ */
+int hl_state_dump(struct hl_device *hdev)
+{
+	char *buf = NULL;
+	size_t offset = 0, size = 0;
+	int rc;
+
+	rc = hl_snprintf_resize(&buf, &size, &offset,
+				"Timestamp taken on: %llu\n\n",
+				ktime_to_ns(ktime_get()));
+	if (rc)
+		goto err;
+
+	rc = hl_state_dump_print_syncs(hdev, &buf, &size, &offset);
+	if (rc)
+		goto err;
+
+	hl_snprintf_resize(&buf, &size, &offset, "\n");
+
+	rc = hl_state_dump_print_monitors(hdev, &buf, &size, &offset);
+	if (rc)
+		goto err;
+
+	hl_snprintf_resize(&buf, &size, &offset, "\n");
+
+	rc = hl_state_dump_print_fences(hdev, &buf, &size, &offset);
+	if (rc)
+		goto err;
+
+	hl_snprintf_resize(&buf, &size, &offset, "\n");
+
+	hl_debugfs_set_state_dump(hdev, buf, size);
+
+	return 0;
+err:
+	vfree(buf);
+	return rc;
+}
diff --git a/drivers/accel/habanalabs/common/sysfs.c b/drivers/accel/habanalabs/common/sysfs.c
new file mode 100644
index 000000000000..8f55ba3b4e73
--- /dev/null
+++ b/drivers/accel/habanalabs/common/sysfs.c
@@ -0,0 +1,567 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Copyright 2016-2022 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ */
+
+#include "habanalabs.h"
+
+#include <linux/pci.h>
+#include <linux/types.h>
+
+static ssize_t clk_max_freq_mhz_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+	long value;
+
+	if (!hl_device_operational(hdev, NULL))
+		return -ENODEV;
+
+	value = hl_fw_get_frequency(hdev, hdev->asic_prop.clk_pll_index, false);
+	if (value < 0)
+		return value;
+
+	hdev->asic_prop.max_freq_value = value;
+
+	return sprintf(buf, "%lu\n", (value / 1000 / 1000));
+}
+
+static ssize_t clk_max_freq_mhz_store(struct device *dev, struct device_attribute *attr,
+					const char *buf, size_t count)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+	int rc;
+	u64 value;
+
+	if (!hl_device_operational(hdev, NULL)) {
+		count = -ENODEV;
+		goto fail;
+	}
+
+	rc = kstrtoull(buf, 0, &value);
+	if (rc) {
+		count = -EINVAL;
+		goto fail;
+	}
+
+	hdev->asic_prop.max_freq_value = value * 1000 * 1000;
+
+	hl_fw_set_frequency(hdev, hdev->asic_prop.clk_pll_index, hdev->asic_prop.max_freq_value);
+
+fail:
+	return count;
+}
+
+static ssize_t clk_cur_freq_mhz_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+	long value;
+
+	if (!hl_device_operational(hdev, NULL))
+		return -ENODEV;
+
+	value = hl_fw_get_frequency(hdev, hdev->asic_prop.clk_pll_index, true);
+	if (value < 0)
+		return value;
+
+	return sprintf(buf, "%lu\n", (value / 1000 / 1000));
+}
+
+static DEVICE_ATTR_RW(clk_max_freq_mhz);
+static DEVICE_ATTR_RO(clk_cur_freq_mhz);
+
+static struct attribute *hl_dev_clk_attrs[] = {
+	&dev_attr_clk_max_freq_mhz.attr,
+	&dev_attr_clk_cur_freq_mhz.attr,
+	NULL,
+};
+
+static ssize_t vrm_ver_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+	struct cpucp_info *cpucp_info;
+	u32 infineon_second_stage_version;
+	u32 infineon_second_stage_first_instance;
+	u32 infineon_second_stage_second_instance;
+	u32 infineon_second_stage_third_instance;
+	u32 mask = 0xff;
+
+	cpucp_info = &hdev->asic_prop.cpucp_info;
+
+	infineon_second_stage_version = le32_to_cpu(cpucp_info->infineon_second_stage_version);
+	infineon_second_stage_first_instance = infineon_second_stage_version & mask;
+	infineon_second_stage_second_instance =
+					(infineon_second_stage_version >> 8) & mask;
+	infineon_second_stage_third_instance =
+					(infineon_second_stage_version >> 16) & mask;
+
+	if (cpucp_info->infineon_version && cpucp_info->infineon_second_stage_version)
+		return sprintf(buf, "%#04x %#04x:%#04x:%#04x\n",
+				le32_to_cpu(cpucp_info->infineon_version),
+				infineon_second_stage_first_instance,
+				infineon_second_stage_second_instance,
+				infineon_second_stage_third_instance);
+	else if (cpucp_info->infineon_second_stage_version)
+		return sprintf(buf, "%#04x:%#04x:%#04x\n",
+				infineon_second_stage_first_instance,
+				infineon_second_stage_second_instance,
+				infineon_second_stage_third_instance);
+	else if (cpucp_info->infineon_version)
+		return sprintf(buf, "%#04x\n", le32_to_cpu(cpucp_info->infineon_version));
+
+	return 0;
+}
+
+static DEVICE_ATTR_RO(vrm_ver);
+
+static struct attribute *hl_dev_vrm_attrs[] = {
+	&dev_attr_vrm_ver.attr,
+	NULL,
+};
+
+static ssize_t uboot_ver_show(struct device *dev, struct device_attribute *attr,
+				char *buf)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+
+	return sprintf(buf, "%s\n", hdev->asic_prop.uboot_ver);
+}
+
+static ssize_t armcp_kernel_ver_show(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+
+	return sprintf(buf, "%s", hdev->asic_prop.cpucp_info.kernel_version);
+}
+
+static ssize_t armcp_ver_show(struct device *dev, struct device_attribute *attr,
+				char *buf)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+
+	return sprintf(buf, "%s\n", hdev->asic_prop.cpucp_info.cpucp_version);
+}
+
+static ssize_t cpld_ver_show(struct device *dev, struct device_attribute *attr,
+				char *buf)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+
+	return sprintf(buf, "0x%08x%08x\n",
+		le32_to_cpu(hdev->asic_prop.cpucp_info.cpld_timestamp),
+		le32_to_cpu(hdev->asic_prop.cpucp_info.cpld_version));
+}
+
+static ssize_t cpucp_kernel_ver_show(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+
+	return sprintf(buf, "%s", hdev->asic_prop.cpucp_info.kernel_version);
+}
+
+static ssize_t cpucp_ver_show(struct device *dev, struct device_attribute *attr,
+				char *buf)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+
+	return sprintf(buf, "%s\n", hdev->asic_prop.cpucp_info.cpucp_version);
+}
+
+static ssize_t fuse_ver_show(struct device *dev, struct device_attribute *attr,
+				char *buf)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+
+	return sprintf(buf, "%s\n", hdev->asic_prop.cpucp_info.fuse_version);
+}
+
+static ssize_t thermal_ver_show(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+
+	return sprintf(buf, "%s", hdev->asic_prop.cpucp_info.thermal_version);
+}
+
+static ssize_t fw_os_ver_show(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+
+	return sprintf(buf, "%s", hdev->asic_prop.cpucp_info.fw_os_version);
+}
+
+static ssize_t preboot_btl_ver_show(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+
+	return sprintf(buf, "%s\n", hdev->asic_prop.preboot_ver);
+}
+
+static ssize_t soft_reset_store(struct device *dev,
+				struct device_attribute *attr, const char *buf,
+				size_t count)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+	long value;
+	int rc;
+
+	rc = kstrtoul(buf, 0, &value);
+
+	if (rc) {
+		count = -EINVAL;
+		goto out;
+	}
+
+	if (!hdev->asic_prop.allow_inference_soft_reset) {
+		dev_err(hdev->dev, "Device does not support inference soft-reset\n");
+		goto out;
+	}
+
+	dev_warn(hdev->dev, "Inference Soft-Reset requested through sysfs\n");
+
+	hl_device_reset(hdev, 0);
+
+out:
+	return count;
+}
+
+static ssize_t hard_reset_store(struct device *dev,
+				struct device_attribute *attr,
+				const char *buf, size_t count)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+	long value;
+	int rc;
+
+	rc = kstrtoul(buf, 0, &value);
+
+	if (rc) {
+		count = -EINVAL;
+		goto out;
+	}
+
+	dev_warn(hdev->dev, "Hard-Reset requested through sysfs\n");
+
+	hl_device_reset(hdev, HL_DRV_RESET_HARD);
+
+out:
+	return count;
+}
+
+static ssize_t device_type_show(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+	char *str;
+
+	switch (hdev->asic_type) {
+	case ASIC_GOYA:
+		str = "GOYA";
+		break;
+	case ASIC_GAUDI:
+		str = "GAUDI";
+		break;
+	case ASIC_GAUDI_SEC:
+		str = "GAUDI SEC";
+		break;
+	case ASIC_GAUDI2:
+		str = "GAUDI2";
+		break;
+	case ASIC_GAUDI2B:
+		str = "GAUDI2B";
+		break;
+	case ASIC_GAUDI2C:
+		str = "GAUDI2C";
+		break;
+	case ASIC_GAUDI2D:
+		str = "GAUDI2D";
+		break;
+	default:
+		dev_err(hdev->dev, "Unrecognized ASIC type %d\n",
+				hdev->asic_type);
+		return -EINVAL;
+	}
+
+	return sprintf(buf, "%s\n", str);
+}
+
+static ssize_t pci_addr_show(struct device *dev, struct device_attribute *attr,
+				char *buf)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+
+	return sprintf(buf, "%04x:%02x:%02x.%x\n",
+			pci_domain_nr(hdev->pdev->bus),
+			hdev->pdev->bus->number,
+			PCI_SLOT(hdev->pdev->devfn),
+			PCI_FUNC(hdev->pdev->devfn));
+}
+
+static ssize_t status_show(struct device *dev, struct device_attribute *attr,
+				char *buf)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+	char str[HL_STR_MAX];
+
+	strscpy(str, hdev->status[hl_device_status(hdev)], HL_STR_MAX);
+
+	/* use uppercase for backward compatibility */
+	str[0] = 'A' + (str[0] - 'a');
+
+	return sprintf(buf, "%s\n", str);
+}
+
+static ssize_t soft_reset_cnt_show(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+
+	return sprintf(buf, "%d\n", hdev->reset_info.compute_reset_cnt);
+}
+
+static ssize_t hard_reset_cnt_show(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+
+	return sprintf(buf, "%d\n", hdev->reset_info.hard_reset_cnt);
+}
+
+static ssize_t max_power_show(struct device *dev, struct device_attribute *attr,
+				char *buf)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+	long val;
+
+	if (!hl_device_operational(hdev, NULL))
+		return -ENODEV;
+
+	val = hl_fw_get_max_power(hdev);
+	if (val < 0)
+		return val;
+
+	return sprintf(buf, "%lu\n", val);
+}
+
+static ssize_t max_power_store(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t count)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+	unsigned long value;
+	int rc;
+
+	if (!hl_device_operational(hdev, NULL)) {
+		count = -ENODEV;
+		goto out;
+	}
+
+	rc = kstrtoul(buf, 0, &value);
+
+	if (rc) {
+		count = -EINVAL;
+		goto out;
+	}
+
+	hdev->max_power = value;
+	hl_fw_set_max_power(hdev);
+
+out:
+	return count;
+}
+
+static ssize_t eeprom_read_handler(struct file *filp, struct kobject *kobj,
+			const struct bin_attribute *attr, char *buf, loff_t offset,
+			size_t max_size)
+{
+	struct device *dev = kobj_to_dev(kobj);
+	struct hl_device *hdev = dev_get_drvdata(dev);
+	char *data;
+	int rc;
+
+	if (!hl_device_operational(hdev, NULL))
+		return -ENODEV;
+
+	if (!max_size)
+		return -EINVAL;
+
+	data = kzalloc(max_size, GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	rc = hdev->asic_funcs->get_eeprom_data(hdev, data, max_size);
+	if (rc)
+		goto out;
+
+	memcpy(buf, data, max_size);
+
+out:
+	kfree(data);
+
+	return max_size;
+}
+
+static ssize_t security_enabled_show(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+
+	return sprintf(buf, "%d\n", hdev->asic_prop.fw_security_enabled);
+}
+
+static ssize_t module_id_show(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+
+	return sprintf(buf, "%u\n", le32_to_cpu(hdev->asic_prop.cpucp_info.card_location));
+}
+
+static ssize_t parent_device_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+
+	return sprintf(buf, "%s\n", HL_DEV_NAME(hdev));
+}
+
+static DEVICE_ATTR_RO(armcp_kernel_ver);
+static DEVICE_ATTR_RO(armcp_ver);
+static DEVICE_ATTR_RO(cpld_ver);
+static DEVICE_ATTR_RO(cpucp_kernel_ver);
+static DEVICE_ATTR_RO(cpucp_ver);
+static DEVICE_ATTR_RO(device_type);
+static DEVICE_ATTR_RO(fuse_ver);
+static DEVICE_ATTR_WO(hard_reset);
+static DEVICE_ATTR_RO(hard_reset_cnt);
+static DEVICE_ATTR_RW(max_power);
+static DEVICE_ATTR_RO(pci_addr);
+static DEVICE_ATTR_RO(preboot_btl_ver);
+static DEVICE_ATTR_WO(soft_reset);
+static DEVICE_ATTR_RO(soft_reset_cnt);
+static DEVICE_ATTR_RO(status);
+static DEVICE_ATTR_RO(thermal_ver);
+static DEVICE_ATTR_RO(uboot_ver);
+static DEVICE_ATTR_RO(fw_os_ver);
+static DEVICE_ATTR_RO(security_enabled);
+static DEVICE_ATTR_RO(module_id);
+static DEVICE_ATTR_RO(parent_device);
+
+static const struct bin_attribute bin_attr_eeprom = {
+	.attr = {.name = "eeprom", .mode = (0444)},
+	.size = PAGE_SIZE,
+	.read = eeprom_read_handler
+};
+
+static struct attribute *hl_dev_attrs[] = {
+	&dev_attr_armcp_kernel_ver.attr,
+	&dev_attr_armcp_ver.attr,
+	&dev_attr_cpld_ver.attr,
+	&dev_attr_cpucp_kernel_ver.attr,
+	&dev_attr_cpucp_ver.attr,
+	&dev_attr_device_type.attr,
+	&dev_attr_fuse_ver.attr,
+	&dev_attr_hard_reset.attr,
+	&dev_attr_hard_reset_cnt.attr,
+	&dev_attr_max_power.attr,
+	&dev_attr_pci_addr.attr,
+	&dev_attr_preboot_btl_ver.attr,
+	&dev_attr_status.attr,
+	&dev_attr_thermal_ver.attr,
+	&dev_attr_uboot_ver.attr,
+	&dev_attr_fw_os_ver.attr,
+	&dev_attr_security_enabled.attr,
+	&dev_attr_module_id.attr,
+	&dev_attr_parent_device.attr,
+	NULL,
+};
+
+static const struct bin_attribute *const hl_dev_bin_attrs[] = {
+	&bin_attr_eeprom,
+	NULL
+};
+
+static struct attribute_group hl_dev_attr_group = {
+	.attrs = hl_dev_attrs,
+	.bin_attrs = hl_dev_bin_attrs,
+};
+
+static struct attribute_group hl_dev_clks_attr_group;
+static struct attribute_group hl_dev_vrm_attr_group;
+
+static const struct attribute_group *hl_dev_attr_groups[] = {
+	&hl_dev_attr_group,
+	&hl_dev_clks_attr_group,
+	&hl_dev_vrm_attr_group,
+	NULL,
+};
+
+static struct attribute *hl_dev_inference_attrs[] = {
+	&dev_attr_soft_reset.attr,
+	&dev_attr_soft_reset_cnt.attr,
+	NULL,
+};
+
+static struct attribute_group hl_dev_inference_attr_group = {
+	.attrs = hl_dev_inference_attrs,
+};
+
+static const struct attribute_group *hl_dev_inference_attr_groups[] = {
+	&hl_dev_inference_attr_group,
+	NULL,
+};
+
+void hl_sysfs_add_dev_clk_attr(struct hl_device *hdev, struct attribute_group *dev_clk_attr_grp)
+{
+	dev_clk_attr_grp->attrs = hl_dev_clk_attrs;
+}
+
+void hl_sysfs_add_dev_vrm_attr(struct hl_device *hdev, struct attribute_group *dev_vrm_attr_grp)
+{
+	dev_vrm_attr_grp->attrs = hl_dev_vrm_attrs;
+}
+
+int hl_sysfs_init(struct hl_device *hdev)
+{
+	int rc;
+
+	hdev->max_power = hdev->asic_prop.max_power_default;
+
+	hdev->asic_funcs->add_device_attr(hdev, &hl_dev_clks_attr_group, &hl_dev_vrm_attr_group);
+
+	rc = device_add_groups(hdev->dev, hl_dev_attr_groups);
+	if (rc) {
+		dev_err(hdev->dev,
+			"Failed to add groups to device, error %d\n", rc);
+		return rc;
+	}
+
+	if (!hdev->asic_prop.allow_inference_soft_reset)
+		return 0;
+
+	rc = device_add_groups(hdev->dev, hl_dev_inference_attr_groups);
+	if (rc) {
+		dev_err(hdev->dev,
+			"Failed to add groups to device, error %d\n", rc);
+		goto remove_groups;
+	}
+
+	return 0;
+
+remove_groups:
+	device_remove_groups(hdev->dev, hl_dev_attr_groups);
+	return rc;
+}
+
+void hl_sysfs_fini(struct hl_device *hdev)
+{
+	device_remove_groups(hdev->dev, hl_dev_attr_groups);
+
+	if (!hdev->asic_prop.allow_inference_soft_reset)
+		return;
+
+	device_remove_groups(hdev->dev, hl_dev_inference_attr_groups);
+}
diff --git a/drivers/accel/habanalabs/gaudi/Makefile b/drivers/accel/habanalabs/gaudi/Makefile
new file mode 100644
index 000000000000..10577c33a816
--- /dev/null
+++ b/drivers/accel/habanalabs/gaudi/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+HL_GAUDI_FILES := gaudi/gaudi.o gaudi/gaudi_security.o \
+	gaudi/gaudi_coresight.o
diff --git a/drivers/accel/habanalabs/gaudi/gaudi.c b/drivers/accel/habanalabs/gaudi/gaudi.c
new file mode 100644
index 000000000000..34771d75da9d
--- /dev/null
+++ b/drivers/accel/habanalabs/gaudi/gaudi.c
@@ -0,0 +1,9237 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Copyright 2016-2022 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ */
+
+#include "gaudiP.h"
+#include "../include/hw_ip/mmu/mmu_general.h"
+#include "../include/hw_ip/mmu/mmu_v1_1.h"
+#include "../include/gaudi/gaudi_masks.h"
+#include "../include/gaudi/gaudi_fw_if.h"
+#include "../include/gaudi/gaudi_reg_map.h"
+#include "../include/gaudi/gaudi_async_ids_map_extended.h"
+
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/firmware.h>
+#include <linux/hwmon.h>
+#include <linux/iommu.h>
+#include <linux/seq_file.h>
+
+/*
+ * Gaudi security scheme:
+ *
+ * 1. Host is protected by:
+ *        - Range registers
+ *        - MMU
+ *
+ * 2. DDR is protected by:
+ *        - Range registers (protect the first 512MB)
+ *
+ * 3. Configuration is protected by:
+ *        - Range registers
+ *        - Protection bits
+ *
+ * MMU is always enabled.
+ *
+ * QMAN DMA channels 0,1 (PCI DMAN):
+ *     - DMA is not secured.
+ *     - PQ and CQ are secured.
+ *     - CP is secured: The driver needs to parse CB but WREG should be allowed
+ *                      because of TDMA (tensor DMA). Hence, WREG is always not
+ *                      secured.
+ *
+ * When the driver needs to use DMA it will check that Gaudi is idle, set DMA
+ * channel 0 to be secured, execute the DMA and change it back to not secured.
+ * Currently, the driver doesn't use the DMA while there are compute jobs
+ * running.
+ *
+ * The current use cases for the driver to use the DMA are:
+ *     - Clear SRAM on context switch (happens on context switch when device is
+ *       idle)
+ *     - MMU page tables area clear (happens on init)
+ *
+ * QMAN DMA 2-7, TPC, MME, NIC:
+ * PQ is secured and is located on the Host (HBM CON TPC3 bug)
+ * CQ, CP and the engine are not secured
+ *
+ */
+
+#define GAUDI_BOOT_FIT_FILE	"habanalabs/gaudi/gaudi-boot-fit.itb"
+#define GAUDI_LINUX_FW_FILE	"habanalabs/gaudi/gaudi-fit.itb"
+#define GAUDI_TPC_FW_FILE	"habanalabs/gaudi/gaudi_tpc.bin"
+
+MODULE_FIRMWARE(GAUDI_BOOT_FIT_FILE);
+MODULE_FIRMWARE(GAUDI_LINUX_FW_FILE);
+MODULE_FIRMWARE(GAUDI_TPC_FW_FILE);
+
+#define GAUDI_DMA_POOL_BLK_SIZE		0x100 /* 256 bytes */
+
+#define GAUDI_RESET_TIMEOUT_MSEC	2000		/* 2000ms */
+#define GAUDI_RESET_WAIT_MSEC		1		/* 1ms */
+#define GAUDI_CPU_RESET_WAIT_MSEC	200		/* 200ms */
+#define GAUDI_TEST_QUEUE_WAIT_USEC	100000		/* 100ms */
+
+#define GAUDI_PLDM_RESET_WAIT_MSEC	1000		/* 1s */
+#define GAUDI_PLDM_HRESET_TIMEOUT_MSEC	20000		/* 20s */
+#define GAUDI_PLDM_TEST_QUEUE_WAIT_USEC	1000000		/* 1s */
+#define GAUDI_PLDM_MMU_TIMEOUT_USEC	(MMU_CONFIG_TIMEOUT_USEC * 100)
+#define GAUDI_PLDM_QMAN0_TIMEOUT_USEC	(HL_DEVICE_TIMEOUT_USEC * 30)
+#define GAUDI_PLDM_TPC_KERNEL_WAIT_USEC	(HL_DEVICE_TIMEOUT_USEC * 30)
+#define GAUDI_BOOT_FIT_REQ_TIMEOUT_USEC	4000000		/* 4s */
+#define GAUDI_MSG_TO_CPU_TIMEOUT_USEC	4000000		/* 4s */
+#define GAUDI_WAIT_FOR_BL_TIMEOUT_USEC	15000000	/* 15s */
+
+#define GAUDI_QMAN0_FENCE_VAL		0x72E91AB9
+
+#define GAUDI_MAX_STRING_LEN		20
+
+#define GAUDI_CB_POOL_CB_CNT		512
+#define GAUDI_CB_POOL_CB_SIZE		0x20000 /* 128KB */
+
+#define GAUDI_ALLOC_CPU_MEM_RETRY_CNT	3
+
+#define GAUDI_NUM_OF_TPC_INTR_CAUSE	20
+
+#define GAUDI_NUM_OF_QM_ERR_CAUSE	16
+
+#define GAUDI_NUM_OF_QM_ARB_ERR_CAUSE	3
+
+#define GAUDI_ARB_WDT_TIMEOUT		0xEE6b27FF /* 8 seconds */
+
+#define HBM_SCRUBBING_TIMEOUT_US	1000000 /* 1s */
+
+#define BIN_REG_STRING_SIZE	sizeof("0b10101010101010101010101010101010")
+
+#define MONITOR_SOB_STRING_SIZE		256
+
+static u32 gaudi_stream_master[GAUDI_STREAM_MASTER_ARR_SIZE] = {
+	GAUDI_QUEUE_ID_DMA_0_0,
+	GAUDI_QUEUE_ID_DMA_0_1,
+	GAUDI_QUEUE_ID_DMA_0_2,
+	GAUDI_QUEUE_ID_DMA_0_3,
+	GAUDI_QUEUE_ID_DMA_1_0,
+	GAUDI_QUEUE_ID_DMA_1_1,
+	GAUDI_QUEUE_ID_DMA_1_2,
+	GAUDI_QUEUE_ID_DMA_1_3
+};
+
+static const u8 gaudi_dma_assignment[GAUDI_DMA_MAX] = {
+	[GAUDI_PCI_DMA_1] = GAUDI_ENGINE_ID_DMA_0,
+	[GAUDI_PCI_DMA_2] = GAUDI_ENGINE_ID_DMA_1,
+	[GAUDI_HBM_DMA_1] = GAUDI_ENGINE_ID_DMA_2,
+	[GAUDI_HBM_DMA_2] = GAUDI_ENGINE_ID_DMA_3,
+	[GAUDI_HBM_DMA_3] = GAUDI_ENGINE_ID_DMA_4,
+	[GAUDI_HBM_DMA_4] = GAUDI_ENGINE_ID_DMA_5,
+	[GAUDI_HBM_DMA_5] = GAUDI_ENGINE_ID_DMA_6,
+	[GAUDI_HBM_DMA_6] = GAUDI_ENGINE_ID_DMA_7
+};
+
+static const u8 gaudi_cq_assignment[NUMBER_OF_CMPLT_QUEUES] = {
+	[0] = GAUDI_QUEUE_ID_DMA_0_0,
+	[1] = GAUDI_QUEUE_ID_DMA_0_1,
+	[2] = GAUDI_QUEUE_ID_DMA_0_2,
+	[3] = GAUDI_QUEUE_ID_DMA_0_3,
+	[4] = GAUDI_QUEUE_ID_DMA_1_0,
+	[5] = GAUDI_QUEUE_ID_DMA_1_1,
+	[6] = GAUDI_QUEUE_ID_DMA_1_2,
+	[7] = GAUDI_QUEUE_ID_DMA_1_3,
+};
+
+static const u16 gaudi_packet_sizes[MAX_PACKET_ID] = {
+	[PACKET_WREG_32]	= sizeof(struct packet_wreg32),
+	[PACKET_WREG_BULK]	= sizeof(struct packet_wreg_bulk),
+	[PACKET_MSG_LONG]	= sizeof(struct packet_msg_long),
+	[PACKET_MSG_SHORT]	= sizeof(struct packet_msg_short),
+	[PACKET_CP_DMA]		= sizeof(struct packet_cp_dma),
+	[PACKET_REPEAT]		= sizeof(struct packet_repeat),
+	[PACKET_MSG_PROT]	= sizeof(struct packet_msg_prot),
+	[PACKET_FENCE]		= sizeof(struct packet_fence),
+	[PACKET_LIN_DMA]	= sizeof(struct packet_lin_dma),
+	[PACKET_NOP]		= sizeof(struct packet_nop),
+	[PACKET_STOP]		= sizeof(struct packet_stop),
+	[PACKET_ARB_POINT]	= sizeof(struct packet_arb_point),
+	[PACKET_WAIT]		= sizeof(struct packet_wait),
+	[PACKET_LOAD_AND_EXE]	= sizeof(struct packet_load_and_exe)
+};
+
+static inline bool validate_packet_id(enum packet_id id)
+{
+	switch (id) {
+	case PACKET_WREG_32:
+	case PACKET_WREG_BULK:
+	case PACKET_MSG_LONG:
+	case PACKET_MSG_SHORT:
+	case PACKET_CP_DMA:
+	case PACKET_REPEAT:
+	case PACKET_MSG_PROT:
+	case PACKET_FENCE:
+	case PACKET_LIN_DMA:
+	case PACKET_NOP:
+	case PACKET_STOP:
+	case PACKET_ARB_POINT:
+	case PACKET_WAIT:
+	case PACKET_LOAD_AND_EXE:
+		return true;
+	default:
+		return false;
+	}
+}
+
+static const char * const
+gaudi_tpc_interrupts_cause[GAUDI_NUM_OF_TPC_INTR_CAUSE] = {
+	"tpc_address_exceed_slm",
+	"tpc_div_by_0",
+	"tpc_spu_mac_overflow",
+	"tpc_spu_addsub_overflow",
+	"tpc_spu_abs_overflow",
+	"tpc_spu_fp_dst_nan_inf",
+	"tpc_spu_fp_dst_denorm",
+	"tpc_vpu_mac_overflow",
+	"tpc_vpu_addsub_overflow",
+	"tpc_vpu_abs_overflow",
+	"tpc_vpu_fp_dst_nan_inf",
+	"tpc_vpu_fp_dst_denorm",
+	"tpc_assertions",
+	"tpc_illegal_instruction",
+	"tpc_pc_wrap_around",
+	"tpc_qm_sw_err",
+	"tpc_hbw_rresp_err",
+	"tpc_hbw_bresp_err",
+	"tpc_lbw_rresp_err",
+	"tpc_lbw_bresp_err"
+};
+
+static const char * const
+gaudi_qman_error_cause[GAUDI_NUM_OF_QM_ERR_CAUSE] = {
+	"PQ AXI HBW error",
+	"CQ AXI HBW error",
+	"CP AXI HBW error",
+	"CP error due to undefined OPCODE",
+	"CP encountered STOP OPCODE",
+	"CP AXI LBW error",
+	"CP WRREG32 or WRBULK returned error",
+	"N/A",
+	"FENCE 0 inc over max value and clipped",
+	"FENCE 1 inc over max value and clipped",
+	"FENCE 2 inc over max value and clipped",
+	"FENCE 3 inc over max value and clipped",
+	"FENCE 0 dec under min value and clipped",
+	"FENCE 1 dec under min value and clipped",
+	"FENCE 2 dec under min value and clipped",
+	"FENCE 3 dec under min value and clipped"
+};
+
+static const char * const
+gaudi_qman_arb_error_cause[GAUDI_NUM_OF_QM_ARB_ERR_CAUSE] = {
+	"Choice push while full error",
+	"Choice Q watchdog error",
+	"MSG AXI LBW returned with error"
+};
+
+static enum hl_queue_type gaudi_queue_type[GAUDI_QUEUE_ID_SIZE] = {
+	QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_0_0 */
+	QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_0_1 */
+	QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_0_2 */
+	QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_0_3 */
+	QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_1_0 */
+	QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_1_1 */
+	QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_1_2 */
+	QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_1_3 */
+	QUEUE_TYPE_CPU, /* GAUDI_QUEUE_ID_CPU_PQ */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_2_0 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_2_1 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_2_2 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_2_3 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_3_0 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_3_1 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_3_2 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_3_3 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_4_0 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_4_1 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_4_2 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_4_3 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_5_0 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_5_1 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_5_2 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_5_3 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_6_0 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_6_1 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_6_2 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_6_3 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_7_0 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_7_1 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_7_2 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_7_3 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_MME_0_0 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_MME_0_1 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_MME_0_2 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_MME_0_3 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_MME_1_0 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_MME_1_1 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_MME_1_2 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_MME_1_3 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_0_0 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_0_1 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_0_2 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_0_3 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_1_0 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_1_1 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_1_2 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_1_3 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_2_0 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_2_1 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_2_2 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_2_3 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_3_0 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_3_1 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_3_2 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_3_3 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_4_0 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_4_1 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_4_2 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_4_3 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_5_0 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_5_1 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_5_2 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_5_3 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_6_0 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_6_1 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_6_2 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_6_3 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_7_0 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_7_1 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_7_2 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_7_3 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_0_0 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_0_1 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_0_2 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_0_3 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_1_0 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_1_1 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_1_2 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_1_3 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_2_0 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_2_1 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_2_2 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_2_3 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_3_0 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_3_1 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_3_2 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_3_3 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_4_0 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_4_1 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_4_2 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_4_3 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_5_0 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_5_1 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_5_2 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_5_3 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_6_0 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_6_1 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_6_2 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_6_3 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_7_0 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_7_1 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_7_2 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_7_3 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_8_0 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_8_1 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_8_2 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_8_3 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_9_0 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_9_1 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_9_2 */
+	QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_9_3 */
+};
+
+static struct hl_hw_obj_name_entry gaudi_so_id_to_str[] = {
+	{ .id = 0,  .name = "SYNC_OBJ_DMA_DOWN_FEEDBACK" },
+	{ .id = 1,  .name = "SYNC_OBJ_DMA_UP_FEEDBACK" },
+	{ .id = 2,  .name = "SYNC_OBJ_DMA_STATIC_DRAM_SRAM_FEEDBACK" },
+	{ .id = 3,  .name = "SYNC_OBJ_DMA_SRAM_DRAM_FEEDBACK" },
+	{ .id = 4,  .name = "SYNC_OBJ_FIRST_COMPUTE_FINISH" },
+	{ .id = 5,  .name = "SYNC_OBJ_HOST_DRAM_DONE" },
+	{ .id = 6,  .name = "SYNC_OBJ_DBG_CTR_DEPRECATED" },
+	{ .id = 7,  .name = "SYNC_OBJ_DMA_ACTIVATIONS_DRAM_SRAM_FEEDBACK" },
+	{ .id = 8,  .name = "SYNC_OBJ_ENGINE_SEM_MME_0" },
+	{ .id = 9,  .name = "SYNC_OBJ_ENGINE_SEM_MME_1" },
+	{ .id = 10, .name = "SYNC_OBJ_ENGINE_SEM_TPC_0" },
+	{ .id = 11, .name = "SYNC_OBJ_ENGINE_SEM_TPC_1" },
+	{ .id = 12, .name = "SYNC_OBJ_ENGINE_SEM_TPC_2" },
+	{ .id = 13, .name = "SYNC_OBJ_ENGINE_SEM_TPC_3" },
+	{ .id = 14, .name = "SYNC_OBJ_ENGINE_SEM_TPC_4" },
+	{ .id = 15, .name = "SYNC_OBJ_ENGINE_SEM_TPC_5" },
+	{ .id = 16, .name = "SYNC_OBJ_ENGINE_SEM_TPC_6" },
+	{ .id = 17, .name = "SYNC_OBJ_ENGINE_SEM_TPC_7" },
+	{ .id = 18, .name = "SYNC_OBJ_ENGINE_SEM_DMA_1" },
+	{ .id = 19, .name = "SYNC_OBJ_ENGINE_SEM_DMA_2" },
+	{ .id = 20, .name = "SYNC_OBJ_ENGINE_SEM_DMA_3" },
+	{ .id = 21, .name = "SYNC_OBJ_ENGINE_SEM_DMA_4" },
+	{ .id = 22, .name = "SYNC_OBJ_ENGINE_SEM_DMA_5" },
+	{ .id = 23, .name = "SYNC_OBJ_ENGINE_SEM_DMA_6" },
+	{ .id = 24, .name = "SYNC_OBJ_ENGINE_SEM_DMA_7" },
+	{ .id = 25, .name = "SYNC_OBJ_DBG_CTR_0" },
+	{ .id = 26, .name = "SYNC_OBJ_DBG_CTR_1" },
+};
+
+static struct hl_hw_obj_name_entry gaudi_monitor_id_to_str[] = {
+	{ .id = 200, .name = "MON_OBJ_DMA_DOWN_FEEDBACK_RESET" },
+	{ .id = 201, .name = "MON_OBJ_DMA_UP_FEEDBACK_RESET" },
+	{ .id = 203, .name = "MON_OBJ_DRAM_TO_SRAM_QUEUE_FENCE" },
+	{ .id = 204, .name = "MON_OBJ_TPC_0_CLK_GATE" },
+	{ .id = 205, .name = "MON_OBJ_TPC_1_CLK_GATE" },
+	{ .id = 206, .name = "MON_OBJ_TPC_2_CLK_GATE" },
+	{ .id = 207, .name = "MON_OBJ_TPC_3_CLK_GATE" },
+	{ .id = 208, .name = "MON_OBJ_TPC_4_CLK_GATE" },
+	{ .id = 209, .name = "MON_OBJ_TPC_5_CLK_GATE" },
+	{ .id = 210, .name = "MON_OBJ_TPC_6_CLK_GATE" },
+	{ .id = 211, .name = "MON_OBJ_TPC_7_CLK_GATE" },
+};
+
+static s64 gaudi_state_dump_specs_props[] = {
+	[SP_SYNC_OBJ_BASE_ADDR] = mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0,
+	[SP_NEXT_SYNC_OBJ_ADDR] = NEXT_SYNC_OBJ_ADDR_INTERVAL,
+	[SP_SYNC_OBJ_AMOUNT] = NUM_OF_SOB_IN_BLOCK,
+	[SP_MON_OBJ_WR_ADDR_LOW] =
+		mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0,
+	[SP_MON_OBJ_WR_ADDR_HIGH] =
+		mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRH_0,
+	[SP_MON_OBJ_WR_DATA] = mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_DATA_0,
+	[SP_MON_OBJ_ARM_DATA] = mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_ARM_0,
+	[SP_MON_OBJ_STATUS] = mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_0,
+	[SP_MONITORS_AMOUNT] = NUM_OF_MONITORS_IN_BLOCK,
+	[SP_TPC0_CMDQ] = mmTPC0_QM_GLBL_CFG0,
+	[SP_TPC0_CFG_SO] = mmTPC0_CFG_QM_SYNC_OBJECT_ADDR,
+	[SP_NEXT_TPC] = mmTPC1_QM_GLBL_CFG0 - mmTPC0_QM_GLBL_CFG0,
+	[SP_MME_CMDQ] = mmMME0_QM_GLBL_CFG0,
+	[SP_MME_CFG_SO] = mmMME0_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL,
+	[SP_NEXT_MME] = mmMME2_QM_GLBL_CFG0 - mmMME0_QM_GLBL_CFG0,
+	[SP_DMA_CMDQ] = mmDMA0_QM_GLBL_CFG0,
+	[SP_DMA_CFG_SO] = mmDMA0_CORE_WR_COMP_ADDR_LO,
+	[SP_DMA_QUEUES_OFFSET] = mmDMA1_QM_GLBL_CFG0 - mmDMA0_QM_GLBL_CFG0,
+	[SP_NUM_OF_MME_ENGINES] = NUM_OF_MME_ENGINES,
+	[SP_SUB_MME_ENG_NUM] = NUM_OF_MME_SUB_ENGINES,
+	[SP_NUM_OF_DMA_ENGINES] = NUM_OF_DMA_ENGINES,
+	[SP_NUM_OF_TPC_ENGINES] = NUM_OF_TPC_ENGINES,
+	[SP_ENGINE_NUM_OF_QUEUES] = NUM_OF_QUEUES,
+	[SP_ENGINE_NUM_OF_STREAMS] = NUM_OF_STREAMS,
+	[SP_ENGINE_NUM_OF_FENCES] = NUM_OF_FENCES,
+	[SP_FENCE0_CNT_OFFSET] =
+		mmDMA0_QM_CP_FENCE0_CNT_0 - mmDMA0_QM_GLBL_CFG0,
+	[SP_FENCE0_RDATA_OFFSET] =
+		mmDMA0_QM_CP_FENCE0_RDATA_0 - mmDMA0_QM_GLBL_CFG0,
+	[SP_CP_STS_OFFSET] = mmDMA0_QM_CP_STS_0 - mmDMA0_QM_GLBL_CFG0,
+	[SP_NUM_CORES] = 1,
+};
+
+static const int gaudi_queue_id_to_engine_id[] = {
+	[GAUDI_QUEUE_ID_DMA_0_0...GAUDI_QUEUE_ID_DMA_0_3] = GAUDI_ENGINE_ID_DMA_0,
+	[GAUDI_QUEUE_ID_DMA_1_0...GAUDI_QUEUE_ID_DMA_1_3] = GAUDI_ENGINE_ID_DMA_1,
+	[GAUDI_QUEUE_ID_CPU_PQ] = GAUDI_ENGINE_ID_SIZE,
+	[GAUDI_QUEUE_ID_DMA_2_0...GAUDI_QUEUE_ID_DMA_2_3] = GAUDI_ENGINE_ID_DMA_2,
+	[GAUDI_QUEUE_ID_DMA_3_0...GAUDI_QUEUE_ID_DMA_3_3] = GAUDI_ENGINE_ID_DMA_3,
+	[GAUDI_QUEUE_ID_DMA_4_0...GAUDI_QUEUE_ID_DMA_4_3] = GAUDI_ENGINE_ID_DMA_4,
+	[GAUDI_QUEUE_ID_DMA_5_0...GAUDI_QUEUE_ID_DMA_5_3] = GAUDI_ENGINE_ID_DMA_5,
+	[GAUDI_QUEUE_ID_DMA_6_0...GAUDI_QUEUE_ID_DMA_6_3] = GAUDI_ENGINE_ID_DMA_6,
+	[GAUDI_QUEUE_ID_DMA_7_0...GAUDI_QUEUE_ID_DMA_7_3] = GAUDI_ENGINE_ID_DMA_7,
+	[GAUDI_QUEUE_ID_MME_0_0...GAUDI_QUEUE_ID_MME_0_3] = GAUDI_ENGINE_ID_MME_0,
+	[GAUDI_QUEUE_ID_MME_1_0...GAUDI_QUEUE_ID_MME_1_3] = GAUDI_ENGINE_ID_MME_2,
+	[GAUDI_QUEUE_ID_TPC_0_0...GAUDI_QUEUE_ID_TPC_0_3] = GAUDI_ENGINE_ID_TPC_0,
+	[GAUDI_QUEUE_ID_TPC_1_0...GAUDI_QUEUE_ID_TPC_1_3] = GAUDI_ENGINE_ID_TPC_1,
+	[GAUDI_QUEUE_ID_TPC_2_0...GAUDI_QUEUE_ID_TPC_2_3] = GAUDI_ENGINE_ID_TPC_2,
+	[GAUDI_QUEUE_ID_TPC_3_0...GAUDI_QUEUE_ID_TPC_3_3] = GAUDI_ENGINE_ID_TPC_3,
+	[GAUDI_QUEUE_ID_TPC_4_0...GAUDI_QUEUE_ID_TPC_4_3] = GAUDI_ENGINE_ID_TPC_4,
+	[GAUDI_QUEUE_ID_TPC_5_0...GAUDI_QUEUE_ID_TPC_5_3] = GAUDI_ENGINE_ID_TPC_5,
+	[GAUDI_QUEUE_ID_TPC_6_0...GAUDI_QUEUE_ID_TPC_6_3] = GAUDI_ENGINE_ID_TPC_6,
+	[GAUDI_QUEUE_ID_TPC_7_0...GAUDI_QUEUE_ID_TPC_7_3] = GAUDI_ENGINE_ID_TPC_7,
+	[GAUDI_QUEUE_ID_NIC_0_0...GAUDI_QUEUE_ID_NIC_0_3] = GAUDI_ENGINE_ID_NIC_0,
+	[GAUDI_QUEUE_ID_NIC_1_0...GAUDI_QUEUE_ID_NIC_1_3] = GAUDI_ENGINE_ID_NIC_1,
+	[GAUDI_QUEUE_ID_NIC_2_0...GAUDI_QUEUE_ID_NIC_2_3] = GAUDI_ENGINE_ID_NIC_2,
+	[GAUDI_QUEUE_ID_NIC_3_0...GAUDI_QUEUE_ID_NIC_3_3] = GAUDI_ENGINE_ID_NIC_3,
+	[GAUDI_QUEUE_ID_NIC_4_0...GAUDI_QUEUE_ID_NIC_4_3] = GAUDI_ENGINE_ID_NIC_4,
+	[GAUDI_QUEUE_ID_NIC_5_0...GAUDI_QUEUE_ID_NIC_5_3] = GAUDI_ENGINE_ID_NIC_5,
+	[GAUDI_QUEUE_ID_NIC_6_0...GAUDI_QUEUE_ID_NIC_6_3] = GAUDI_ENGINE_ID_NIC_6,
+	[GAUDI_QUEUE_ID_NIC_7_0...GAUDI_QUEUE_ID_NIC_7_3] = GAUDI_ENGINE_ID_NIC_7,
+	[GAUDI_QUEUE_ID_NIC_8_0...GAUDI_QUEUE_ID_NIC_8_3] = GAUDI_ENGINE_ID_NIC_8,
+	[GAUDI_QUEUE_ID_NIC_9_0...GAUDI_QUEUE_ID_NIC_9_3] = GAUDI_ENGINE_ID_NIC_9,
+};
+
+/* The order here is opposite to the order of the indexing in the h/w.
+ * i.e. SYNC_MGR_W_S is actually 0, SYNC_MGR_E_S is 1, etc.
+ */
+static const char * const gaudi_sync_manager_names[] = {
+	"SYNC_MGR_E_N",
+	"SYNC_MGR_W_N",
+	"SYNC_MGR_E_S",
+	"SYNC_MGR_W_S",
+	NULL
+};
+
+struct ecc_info_extract_params {
+	u64 block_address;
+	u32 num_memories;
+	bool derr;
+};
+
+static int gaudi_mmu_update_asid_hop0_addr(struct hl_device *hdev, u32 asid,
+								u64 phys_addr);
+static int gaudi_send_job_on_qman0(struct hl_device *hdev,
+					struct hl_cs_job *job);
+static int gaudi_memset_device_memory(struct hl_device *hdev, u64 addr,
+					u32 size, u64 val);
+static int gaudi_memset_registers(struct hl_device *hdev, u64 reg_base,
+					u32 num_regs, u32 val);
+static int gaudi_run_tpc_kernel(struct hl_device *hdev, u64 tpc_kernel,
+				u32 tpc_id);
+static int gaudi_mmu_clear_pgt_range(struct hl_device *hdev);
+static int gaudi_cpucp_info_get(struct hl_device *hdev);
+static void gaudi_disable_clock_gating(struct hl_device *hdev);
+static void gaudi_mmu_prepare(struct hl_device *hdev, u32 asid);
+static u32 gaudi_gen_signal_cb(struct hl_device *hdev, void *data, u16 sob_id,
+				u32 size, bool eb);
+static u32 gaudi_gen_wait_cb(struct hl_device *hdev,
+				struct hl_gen_wait_properties *prop);
+static inline enum hl_collective_mode
+get_collective_mode(struct hl_device *hdev, u32 queue_id)
+{
+	if (gaudi_queue_type[queue_id] == QUEUE_TYPE_EXT)
+		return HL_COLLECTIVE_MASTER;
+
+	if (queue_id >= GAUDI_QUEUE_ID_DMA_5_0 &&
+			queue_id <= GAUDI_QUEUE_ID_DMA_5_3)
+		return HL_COLLECTIVE_SLAVE;
+
+	if (queue_id >= GAUDI_QUEUE_ID_TPC_7_0 &&
+			queue_id <= GAUDI_QUEUE_ID_TPC_7_3)
+		return HL_COLLECTIVE_SLAVE;
+
+	if (queue_id >= GAUDI_QUEUE_ID_NIC_0_0 &&
+			queue_id <= GAUDI_QUEUE_ID_NIC_9_3)
+		return HL_COLLECTIVE_SLAVE;
+
+	return HL_COLLECTIVE_NOT_SUPPORTED;
+}
+
+static inline void set_default_power_values(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+
+	if (hdev->card_type == cpucp_card_type_pmc) {
+		prop->max_power_default = MAX_POWER_DEFAULT_PMC;
+
+		if (prop->fw_security_enabled)
+			prop->dc_power_default = DC_POWER_DEFAULT_PMC_SEC;
+		else
+			prop->dc_power_default = DC_POWER_DEFAULT_PMC;
+	} else {
+		prop->max_power_default = MAX_POWER_DEFAULT_PCI;
+		prop->dc_power_default = DC_POWER_DEFAULT_PCI;
+	}
+}
+
+static int gaudi_set_fixed_properties(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	u32 num_sync_stream_queues = 0;
+	int i;
+
+	prop->max_queues = GAUDI_QUEUE_ID_SIZE;
+	prop->hw_queues_props = kcalloc(prop->max_queues,
+			sizeof(struct hw_queue_properties),
+			GFP_KERNEL);
+
+	if (!prop->hw_queues_props)
+		return -ENOMEM;
+
+	for (i = 0 ; i < prop->max_queues ; i++) {
+		if (gaudi_queue_type[i] == QUEUE_TYPE_EXT) {
+			prop->hw_queues_props[i].type = QUEUE_TYPE_EXT;
+			prop->hw_queues_props[i].driver_only = 0;
+			prop->hw_queues_props[i].supports_sync_stream = 1;
+			prop->hw_queues_props[i].cb_alloc_flags =
+				CB_ALLOC_KERNEL;
+			num_sync_stream_queues++;
+		} else if (gaudi_queue_type[i] == QUEUE_TYPE_CPU) {
+			prop->hw_queues_props[i].type = QUEUE_TYPE_CPU;
+			prop->hw_queues_props[i].driver_only = 1;
+			prop->hw_queues_props[i].supports_sync_stream = 0;
+			prop->hw_queues_props[i].cb_alloc_flags =
+				CB_ALLOC_KERNEL;
+		} else if (gaudi_queue_type[i] == QUEUE_TYPE_INT) {
+			prop->hw_queues_props[i].type = QUEUE_TYPE_INT;
+			prop->hw_queues_props[i].driver_only = 0;
+			prop->hw_queues_props[i].supports_sync_stream = 0;
+			prop->hw_queues_props[i].cb_alloc_flags =
+				CB_ALLOC_USER;
+
+		}
+		prop->hw_queues_props[i].collective_mode =
+						get_collective_mode(hdev, i);
+	}
+
+	prop->cache_line_size = DEVICE_CACHE_LINE_SIZE;
+	prop->cfg_base_address = CFG_BASE;
+	prop->device_dma_offset_for_host_access = HOST_PHYS_BASE;
+	prop->host_base_address = HOST_PHYS_BASE;
+	prop->host_end_address = prop->host_base_address + HOST_PHYS_SIZE;
+	prop->completion_queues_count = NUMBER_OF_CMPLT_QUEUES;
+	prop->completion_mode = HL_COMPLETION_MODE_JOB;
+	prop->collective_first_sob = 0;
+	prop->collective_first_mon = 0;
+
+	/* 2 SOBs per internal queue stream are reserved for collective */
+	prop->sync_stream_first_sob =
+			ALIGN(NUMBER_OF_SOBS_IN_GRP, HL_MAX_SOBS_PER_MONITOR)
+			* QMAN_STREAMS * HL_RSVD_SOBS;
+
+	/* 1 monitor per internal queue stream are reserved for collective
+	 * 2 monitors per external queue stream are reserved for collective
+	 */
+	prop->sync_stream_first_mon =
+			(NUMBER_OF_COLLECTIVE_QUEUES * QMAN_STREAMS) +
+			(NUMBER_OF_EXT_HW_QUEUES * 2);
+
+	prop->dram_base_address = DRAM_PHYS_BASE;
+	prop->dram_size = GAUDI_HBM_SIZE_32GB;
+	prop->dram_end_address = prop->dram_base_address + prop->dram_size;
+	prop->dram_user_base_address = DRAM_BASE_ADDR_USER;
+
+	prop->sram_base_address = SRAM_BASE_ADDR;
+	prop->sram_size = SRAM_SIZE;
+	prop->sram_end_address = prop->sram_base_address + prop->sram_size;
+	prop->sram_user_base_address =
+			prop->sram_base_address + SRAM_USER_BASE_OFFSET;
+
+	prop->mmu_cache_mng_addr = MMU_CACHE_MNG_ADDR;
+	prop->mmu_cache_mng_size = MMU_CACHE_MNG_SIZE;
+
+	prop->mmu_pgt_addr = MMU_PAGE_TABLES_ADDR;
+	if (hdev->pldm)
+		prop->mmu_pgt_size = 0x800000; /* 8MB */
+	else
+		prop->mmu_pgt_size = MMU_PAGE_TABLES_SIZE;
+	prop->mmu_pte_size = HL_PTE_SIZE;
+	prop->dram_page_size = PAGE_SIZE_2MB;
+	prop->device_mem_alloc_default_page_size = prop->dram_page_size;
+	prop->dram_supports_virtual_memory = false;
+
+	prop->pmmu.hop_shifts[MMU_HOP0] = MMU_V1_1_HOP0_SHIFT;
+	prop->pmmu.hop_shifts[MMU_HOP1] = MMU_V1_1_HOP1_SHIFT;
+	prop->pmmu.hop_shifts[MMU_HOP2] = MMU_V1_1_HOP2_SHIFT;
+	prop->pmmu.hop_shifts[MMU_HOP3] = MMU_V1_1_HOP3_SHIFT;
+	prop->pmmu.hop_shifts[MMU_HOP4] = MMU_V1_1_HOP4_SHIFT;
+	prop->pmmu.hop_masks[MMU_HOP0] = MMU_V1_1_HOP0_MASK;
+	prop->pmmu.hop_masks[MMU_HOP1] = MMU_V1_1_HOP1_MASK;
+	prop->pmmu.hop_masks[MMU_HOP2] = MMU_V1_1_HOP2_MASK;
+	prop->pmmu.hop_masks[MMU_HOP3] = MMU_V1_1_HOP3_MASK;
+	prop->pmmu.hop_masks[MMU_HOP4] = MMU_V1_1_HOP4_MASK;
+	prop->pmmu.start_addr = VA_HOST_SPACE_START;
+	prop->pmmu.end_addr =
+			(VA_HOST_SPACE_START + VA_HOST_SPACE_SIZE / 2) - 1;
+	prop->pmmu.page_size = PAGE_SIZE_4KB;
+	prop->pmmu.num_hops = MMU_ARCH_5_HOPS;
+	prop->pmmu.last_mask = LAST_MASK;
+	/* TODO: will be duplicated until implementing per-MMU props */
+	prop->pmmu.hop_table_size = HOP_TABLE_SIZE_512_PTE;
+	prop->pmmu.hop0_tables_total_size = HOP0_512_PTE_TABLES_TOTAL_SIZE;
+
+	/* PMMU and HPMMU are the same except of page size */
+	memcpy(&prop->pmmu_huge, &prop->pmmu, sizeof(prop->pmmu));
+	prop->pmmu_huge.page_size = PAGE_SIZE_2MB;
+
+	/* shifts and masks are the same in PMMU and DMMU */
+	memcpy(&prop->dmmu, &prop->pmmu, sizeof(prop->pmmu));
+	prop->dmmu.start_addr = (VA_HOST_SPACE_START + VA_HOST_SPACE_SIZE / 2);
+	prop->dmmu.end_addr = VA_HOST_SPACE_END;
+	prop->dmmu.page_size = PAGE_SIZE_2MB;
+	prop->dmmu.pgt_size = prop->mmu_pgt_size;
+
+	prop->cfg_size = CFG_SIZE;
+	prop->max_asid = MAX_ASID;
+	prop->num_of_events = GAUDI_EVENT_SIZE;
+	prop->max_num_of_engines = GAUDI_ENGINE_ID_SIZE;
+	prop->tpc_enabled_mask = TPC_ENABLED_MASK;
+
+	set_default_power_values(hdev);
+
+	prop->cb_pool_cb_cnt = GAUDI_CB_POOL_CB_CNT;
+	prop->cb_pool_cb_size = GAUDI_CB_POOL_CB_SIZE;
+
+	prop->pcie_dbi_base_address = mmPCIE_DBI_BASE;
+	prop->pcie_aux_dbi_reg_addr = CFG_BASE + mmPCIE_AUX_DBI;
+
+	strscpy_pad(prop->cpucp_info.card_name, GAUDI_DEFAULT_CARD_NAME,
+					CARD_NAME_MAX_LEN);
+
+	prop->max_pending_cs = GAUDI_MAX_PENDING_CS;
+
+	prop->first_available_user_sob[HL_GAUDI_WS_DCORE] =
+			prop->sync_stream_first_sob +
+			(num_sync_stream_queues * HL_RSVD_SOBS);
+	prop->first_available_user_mon[HL_GAUDI_WS_DCORE] =
+			prop->sync_stream_first_mon +
+			(num_sync_stream_queues * HL_RSVD_MONS);
+
+	prop->first_available_user_interrupt = USHRT_MAX;
+	prop->tpc_interrupt_id = USHRT_MAX;
+
+	/* single msi */
+	prop->eq_interrupt_id = 0;
+
+	for (i = 0 ; i < HL_MAX_DCORES ; i++)
+		prop->first_available_cq[i] = USHRT_MAX;
+
+	prop->fw_cpu_boot_dev_sts0_valid = false;
+	prop->fw_cpu_boot_dev_sts1_valid = false;
+	prop->hard_reset_done_by_fw = false;
+	prop->gic_interrupts_enable = true;
+
+	prop->server_type = HL_SERVER_TYPE_UNKNOWN;
+
+	prop->clk_pll_index = HL_GAUDI_MME_PLL;
+	prop->max_freq_value = GAUDI_MAX_CLK_FREQ;
+
+	prop->use_get_power_for_reset_history = true;
+
+	prop->configurable_stop_on_err = true;
+
+	prop->set_max_power_on_device_init = true;
+
+	prop->dma_mask = 48;
+
+	prop->hbw_flush_reg = mmPCIE_WRAP_RR_ELBI_RD_SEC_REG_CTRL;
+
+	return 0;
+}
+
+static int gaudi_pci_bars_map(struct hl_device *hdev)
+{
+	static const char * const name[] = {"SRAM", "CFG", "HBM"};
+	bool is_wc[3] = {false, false, true};
+	int rc;
+
+	rc = hl_pci_bars_map(hdev, name, is_wc);
+	if (rc)
+		return rc;
+
+	hdev->rmmio = hdev->pcie_bar[CFG_BAR_ID] +
+			(CFG_BASE - SPI_FLASH_BASE_ADDR);
+
+	return 0;
+}
+
+static u64 gaudi_set_hbm_bar_base(struct hl_device *hdev, u64 addr)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+	struct hl_inbound_pci_region pci_region;
+	u64 old_addr = addr;
+	int rc;
+
+	if ((gaudi) && (gaudi->hbm_bar_cur_addr == addr))
+		return old_addr;
+
+	if (hdev->asic_prop.iatu_done_by_fw)
+		return U64_MAX;
+
+	/* Inbound Region 2 - Bar 4 - Point to HBM */
+	pci_region.mode = PCI_BAR_MATCH_MODE;
+	pci_region.bar = HBM_BAR_ID;
+	pci_region.addr = addr;
+	rc = hl_pci_set_inbound_region(hdev, 2, &pci_region);
+	if (rc)
+		return U64_MAX;
+
+	if (gaudi) {
+		old_addr = gaudi->hbm_bar_cur_addr;
+		gaudi->hbm_bar_cur_addr = addr;
+	}
+
+	return old_addr;
+}
+
+static int gaudi_init_iatu(struct hl_device *hdev)
+{
+	struct hl_inbound_pci_region inbound_region;
+	struct hl_outbound_pci_region outbound_region;
+	int rc;
+
+	if (hdev->asic_prop.iatu_done_by_fw)
+		return 0;
+
+	/* Inbound Region 0 - Bar 0 - Point to SRAM + CFG */
+	inbound_region.mode = PCI_BAR_MATCH_MODE;
+	inbound_region.bar = SRAM_BAR_ID;
+	inbound_region.addr = SRAM_BASE_ADDR;
+	rc = hl_pci_set_inbound_region(hdev, 0, &inbound_region);
+	if (rc)
+		goto done;
+
+	/* Inbound Region 1 - Bar 2 - Point to SPI FLASH */
+	inbound_region.mode = PCI_BAR_MATCH_MODE;
+	inbound_region.bar = CFG_BAR_ID;
+	inbound_region.addr = SPI_FLASH_BASE_ADDR;
+	rc = hl_pci_set_inbound_region(hdev, 1, &inbound_region);
+	if (rc)
+		goto done;
+
+	/* Inbound Region 2 - Bar 4 - Point to HBM */
+	inbound_region.mode = PCI_BAR_MATCH_MODE;
+	inbound_region.bar = HBM_BAR_ID;
+	inbound_region.addr = DRAM_PHYS_BASE;
+	rc = hl_pci_set_inbound_region(hdev, 2, &inbound_region);
+	if (rc)
+		goto done;
+
+	/* Outbound Region 0 - Point to Host */
+	outbound_region.addr = HOST_PHYS_BASE;
+	outbound_region.size = HOST_PHYS_SIZE;
+	rc = hl_pci_set_outbound_region(hdev, &outbound_region);
+
+done:
+	return rc;
+}
+
+static enum hl_device_hw_state gaudi_get_hw_state(struct hl_device *hdev)
+{
+	return RREG32(mmHW_STATE);
+}
+
+static int gaudi_early_init(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct pci_dev *pdev = hdev->pdev;
+	resource_size_t pci_bar_size;
+	u32 fw_boot_status;
+	int rc;
+
+	rc = gaudi_set_fixed_properties(hdev);
+	if (rc) {
+		dev_err(hdev->dev, "Failed setting fixed properties\n");
+		return rc;
+	}
+
+	/* Check BAR sizes */
+	pci_bar_size = pci_resource_len(pdev, SRAM_BAR_ID);
+
+	if (pci_bar_size != SRAM_BAR_SIZE) {
+		dev_err(hdev->dev, "Not " HL_NAME "? BAR %d size %pa, expecting %llu\n",
+			SRAM_BAR_ID, &pci_bar_size, SRAM_BAR_SIZE);
+		rc = -ENODEV;
+		goto free_queue_props;
+	}
+
+	pci_bar_size = pci_resource_len(pdev, CFG_BAR_ID);
+
+	if (pci_bar_size != CFG_BAR_SIZE) {
+		dev_err(hdev->dev, "Not " HL_NAME "? BAR %d size %pa, expecting %llu\n",
+			CFG_BAR_ID, &pci_bar_size, CFG_BAR_SIZE);
+		rc = -ENODEV;
+		goto free_queue_props;
+	}
+
+	prop->dram_pci_bar_size = pci_resource_len(pdev, HBM_BAR_ID);
+	hdev->dram_pci_bar_start = pci_resource_start(pdev, HBM_BAR_ID);
+
+	/* If FW security is enabled at this point it means no access to ELBI */
+	if (hdev->asic_prop.fw_security_enabled) {
+		hdev->asic_prop.iatu_done_by_fw = true;
+
+		/*
+		 * GIC-security-bit can ONLY be set by CPUCP, so in this stage
+		 * decision can only be taken based on PCI ID security.
+		 */
+		hdev->asic_prop.gic_interrupts_enable = false;
+		goto pci_init;
+	}
+
+	rc = hl_pci_elbi_read(hdev, CFG_BASE + mmCPU_BOOT_DEV_STS0,
+				&fw_boot_status);
+	if (rc)
+		goto free_queue_props;
+
+	/* Check whether FW is configuring iATU */
+	if ((fw_boot_status & CPU_BOOT_DEV_STS0_ENABLED) &&
+			(fw_boot_status & CPU_BOOT_DEV_STS0_FW_IATU_CONF_EN))
+		hdev->asic_prop.iatu_done_by_fw = true;
+
+pci_init:
+	rc = hl_pci_init(hdev);
+	if (rc)
+		goto free_queue_props;
+
+	/* Before continuing in the initialization, we need to read the preboot
+	 * version to determine whether we run with a security-enabled firmware
+	 */
+	rc = hl_fw_read_preboot_status(hdev);
+	if (rc) {
+		if (hdev->reset_on_preboot_fail)
+			/* we are already on failure flow, so don't check if hw_fini fails. */
+			hdev->asic_funcs->hw_fini(hdev, true, false);
+		goto pci_fini;
+	}
+
+	if (gaudi_get_hw_state(hdev) == HL_DEVICE_HW_STATE_DIRTY) {
+		dev_dbg(hdev->dev, "H/W state is dirty, must reset before initializing\n");
+		rc = hdev->asic_funcs->hw_fini(hdev, true, false);
+		if (rc) {
+			dev_err(hdev->dev, "failed to reset HW in dirty state (%d)\n", rc);
+			goto pci_fini;
+		}
+	}
+
+	return 0;
+
+pci_fini:
+	hl_pci_fini(hdev);
+free_queue_props:
+	kfree(hdev->asic_prop.hw_queues_props);
+	return rc;
+}
+
+static int gaudi_early_fini(struct hl_device *hdev)
+{
+	kfree(hdev->asic_prop.hw_queues_props);
+	hl_pci_fini(hdev);
+
+	return 0;
+}
+
+/**
+ * gaudi_fetch_psoc_frequency - Fetch PSOC frequency values
+ *
+ * @hdev: pointer to hl_device structure
+ *
+ */
+static int gaudi_fetch_psoc_frequency(struct hl_device *hdev)
+{
+	u32 nr = 0, nf = 0, od = 0, div_fctr = 0, pll_clk, div_sel;
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	u16 pll_freq_arr[HL_PLL_NUM_OUTPUTS], freq;
+	int rc;
+
+	if ((hdev->fw_components & FW_TYPE_LINUX) &&
+			(prop->fw_app_cpu_boot_dev_sts0 & CPU_BOOT_DEV_STS0_PLL_INFO_EN)) {
+		struct gaudi_device *gaudi = hdev->asic_specific;
+
+		if (!(gaudi->hw_cap_initialized & HW_CAP_CPU_Q))
+			return 0;
+
+		rc = hl_fw_cpucp_pll_info_get(hdev, HL_GAUDI_CPU_PLL, pll_freq_arr);
+
+		if (rc)
+			return rc;
+
+		freq = pll_freq_arr[2];
+	} else {
+		/* Backward compatibility */
+		div_fctr = RREG32(mmPSOC_CPU_PLL_DIV_FACTOR_2);
+		div_sel = RREG32(mmPSOC_CPU_PLL_DIV_SEL_2);
+		nr = RREG32(mmPSOC_CPU_PLL_NR);
+		nf = RREG32(mmPSOC_CPU_PLL_NF);
+		od = RREG32(mmPSOC_CPU_PLL_OD);
+
+		if (div_sel == DIV_SEL_REF_CLK ||
+				div_sel == DIV_SEL_DIVIDED_REF) {
+			if (div_sel == DIV_SEL_REF_CLK)
+				freq = PLL_REF_CLK;
+			else
+				freq = PLL_REF_CLK / (div_fctr + 1);
+		} else if (div_sel == DIV_SEL_PLL_CLK ||
+			div_sel == DIV_SEL_DIVIDED_PLL) {
+			pll_clk = PLL_REF_CLK * (nf + 1) /
+					((nr + 1) * (od + 1));
+			if (div_sel == DIV_SEL_PLL_CLK)
+				freq = pll_clk;
+			else
+				freq = pll_clk / (div_fctr + 1);
+		} else {
+			dev_warn(hdev->dev, "Received invalid div select value: %#x", div_sel);
+			freq = 0;
+		}
+	}
+
+	prop->psoc_timestamp_frequency = freq;
+	prop->psoc_pci_pll_nr = nr;
+	prop->psoc_pci_pll_nf = nf;
+	prop->psoc_pci_pll_od = od;
+	prop->psoc_pci_pll_div_factor = div_fctr;
+
+	return 0;
+}
+
+static int _gaudi_init_tpc_mem(struct hl_device *hdev,
+		dma_addr_t tpc_kernel_src_addr, u32 tpc_kernel_size)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct packet_lin_dma *init_tpc_mem_pkt;
+	struct hl_cs_job *job;
+	struct hl_cb *cb;
+	u64 dst_addr;
+	u32 cb_size, ctl;
+	u8 tpc_id;
+	int rc;
+
+	cb = hl_cb_kernel_create(hdev, PAGE_SIZE, false);
+	if (!cb)
+		return -EFAULT;
+
+	init_tpc_mem_pkt = cb->kernel_address;
+	cb_size = sizeof(*init_tpc_mem_pkt);
+	memset(init_tpc_mem_pkt, 0, cb_size);
+
+	init_tpc_mem_pkt->tsize = cpu_to_le32(tpc_kernel_size);
+
+	ctl = FIELD_PREP(GAUDI_PKT_CTL_OPCODE_MASK, PACKET_LIN_DMA);
+	ctl |= FIELD_PREP(GAUDI_PKT_LIN_DMA_CTL_LIN_MASK, 1);
+	ctl |= FIELD_PREP(GAUDI_PKT_CTL_RB_MASK, 1);
+	ctl |= FIELD_PREP(GAUDI_PKT_CTL_MB_MASK, 1);
+
+	init_tpc_mem_pkt->ctl = cpu_to_le32(ctl);
+
+	init_tpc_mem_pkt->src_addr = cpu_to_le64(tpc_kernel_src_addr);
+
+	/* TPC_CMD is configured with I$ prefetch enabled, so address should be aligned to 8KB */
+	dst_addr = FIELD_PREP(GAUDI_PKT_LIN_DMA_DST_ADDR_MASK,
+				round_up(prop->sram_user_base_address, SZ_8K));
+	init_tpc_mem_pkt->dst_addr |= cpu_to_le64(dst_addr);
+
+	job = hl_cs_allocate_job(hdev, QUEUE_TYPE_EXT, true);
+	if (!job) {
+		dev_err(hdev->dev, "Failed to allocate a new job\n");
+		rc = -ENOMEM;
+		goto release_cb;
+	}
+
+	job->id = 0;
+	job->user_cb = cb;
+	atomic_inc(&job->user_cb->cs_cnt);
+	job->user_cb_size = cb_size;
+	job->hw_queue_id = GAUDI_QUEUE_ID_DMA_0_0;
+	job->patched_cb = job->user_cb;
+	job->job_cb_size = job->user_cb_size + sizeof(struct packet_msg_prot);
+
+	hl_debugfs_add_job(hdev, job);
+
+	rc = gaudi_send_job_on_qman0(hdev, job);
+
+	if (rc)
+		goto free_job;
+
+	for (tpc_id = 0 ; tpc_id < TPC_NUMBER_OF_ENGINES ; tpc_id++) {
+		rc = gaudi_run_tpc_kernel(hdev, dst_addr, tpc_id);
+		if (rc)
+			break;
+	}
+
+free_job:
+	hl_userptr_delete_list(hdev, &job->userptr_list);
+	hl_debugfs_remove_job(hdev, job);
+	kfree(job);
+	atomic_dec(&cb->cs_cnt);
+
+release_cb:
+	hl_cb_put(cb);
+	hl_cb_destroy(&hdev->kernel_mem_mgr, cb->buf->handle);
+
+	return rc;
+}
+
+/*
+ * gaudi_init_tpc_mem() - Initialize TPC memories.
+ * @hdev: Pointer to hl_device structure.
+ *
+ * Copy TPC kernel fw from firmware file and run it to initialize TPC memories.
+ *
+ * Return: 0 for success, negative value for error.
+ */
+static int gaudi_init_tpc_mem(struct hl_device *hdev)
+{
+	const struct firmware *fw;
+	size_t fw_size;
+	void *cpu_addr;
+	dma_addr_t dma_handle;
+	int rc, count = 5;
+
+again:
+	rc = request_firmware(&fw, GAUDI_TPC_FW_FILE, hdev->dev);
+	if (rc == -EINTR && count-- > 0) {
+		msleep(50);
+		goto again;
+	}
+
+	if (rc) {
+		dev_err(hdev->dev, "Failed to load firmware file %s\n",
+				GAUDI_TPC_FW_FILE);
+		goto out;
+	}
+
+	fw_size = fw->size;
+	cpu_addr = hl_asic_dma_alloc_coherent(hdev, fw_size, &dma_handle, GFP_KERNEL | __GFP_ZERO);
+	if (!cpu_addr) {
+		dev_err(hdev->dev,
+			"Failed to allocate %zu of dma memory for TPC kernel\n",
+			fw_size);
+		rc = -ENOMEM;
+		goto out;
+	}
+
+	memcpy(cpu_addr, fw->data, fw_size);
+
+	rc = _gaudi_init_tpc_mem(hdev, dma_handle, fw_size);
+
+	hl_asic_dma_free_coherent(hdev, fw->size, cpu_addr, dma_handle);
+
+out:
+	release_firmware(fw);
+	return rc;
+}
+
+static void gaudi_collective_map_sobs(struct hl_device *hdev, u32 stream)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+	struct gaudi_collective_properties *prop = &gaudi->collective_props;
+	struct hl_hw_queue *q;
+	u32 i, sob_id, sob_group_id, queue_id;
+
+	/* Iterate through SOB groups and assign a SOB for each slave queue */
+	sob_group_id =
+		stream * HL_RSVD_SOBS + prop->curr_sob_group_idx[stream];
+	sob_id = prop->hw_sob_group[sob_group_id].base_sob_id;
+
+	queue_id = GAUDI_QUEUE_ID_NIC_0_0 + stream;
+	for (i = 0 ; i < NIC_NUMBER_OF_ENGINES ; i++) {
+		q = &hdev->kernel_queues[queue_id + (4 * i)];
+		q->sync_stream_prop.collective_sob_id = sob_id + i;
+	}
+
+	/* Both DMA5 and TPC7 use the same resources since only a single
+	 * engine need to participate in the reduction process
+	 */
+	queue_id = GAUDI_QUEUE_ID_DMA_5_0 + stream;
+	q = &hdev->kernel_queues[queue_id];
+	q->sync_stream_prop.collective_sob_id =
+			sob_id + NIC_NUMBER_OF_ENGINES;
+
+	queue_id = GAUDI_QUEUE_ID_TPC_7_0 + stream;
+	q = &hdev->kernel_queues[queue_id];
+	q->sync_stream_prop.collective_sob_id =
+			sob_id + NIC_NUMBER_OF_ENGINES;
+}
+
+static void gaudi_sob_group_hw_reset(struct kref *ref)
+{
+	struct gaudi_hw_sob_group *hw_sob_group =
+		container_of(ref, struct gaudi_hw_sob_group, kref);
+	struct hl_device *hdev = hw_sob_group->hdev;
+	int i;
+
+	for (i = 0 ; i < NUMBER_OF_SOBS_IN_GRP ; i++)
+		WREG32((mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0 +
+			(hw_sob_group->base_sob_id * 4) + (i * 4)), 0);
+
+	kref_init(&hw_sob_group->kref);
+}
+
+static void gaudi_sob_group_reset_error(struct kref *ref)
+{
+	struct gaudi_hw_sob_group *hw_sob_group =
+		container_of(ref, struct gaudi_hw_sob_group, kref);
+	struct hl_device *hdev = hw_sob_group->hdev;
+
+	dev_crit(hdev->dev,
+		"SOB release shouldn't be called here, base_sob_id: %d\n",
+		hw_sob_group->base_sob_id);
+}
+
+static void gaudi_collective_mstr_sob_mask_set(struct gaudi_device *gaudi)
+{
+	struct gaudi_collective_properties *prop;
+	int i;
+
+	prop = &gaudi->collective_props;
+
+	memset(prop->mstr_sob_mask, 0, sizeof(prop->mstr_sob_mask));
+
+	for (i = 0 ; i < NIC_NUMBER_OF_ENGINES ; i++)
+		if (gaudi->hw_cap_initialized & BIT(HW_CAP_NIC_SHIFT + i))
+			prop->mstr_sob_mask[i / HL_MAX_SOBS_PER_MONITOR] |=
+					BIT(i % HL_MAX_SOBS_PER_MONITOR);
+	/* Set collective engine bit */
+	prop->mstr_sob_mask[i / HL_MAX_SOBS_PER_MONITOR] |=
+				BIT(i % HL_MAX_SOBS_PER_MONITOR);
+}
+
+static int gaudi_collective_init(struct hl_device *hdev)
+{
+	u32 i, sob_id, reserved_sobs_per_group;
+	struct gaudi_collective_properties *prop;
+	struct gaudi_device *gaudi;
+
+	gaudi = hdev->asic_specific;
+	prop = &gaudi->collective_props;
+	sob_id = hdev->asic_prop.collective_first_sob;
+
+	/* First sob in group must be aligned to HL_MAX_SOBS_PER_MONITOR */
+	reserved_sobs_per_group =
+		ALIGN(NUMBER_OF_SOBS_IN_GRP, HL_MAX_SOBS_PER_MONITOR);
+
+	/* Init SOB groups */
+	for (i = 0 ; i < NUM_SOB_GROUPS; i++) {
+		prop->hw_sob_group[i].hdev = hdev;
+		prop->hw_sob_group[i].base_sob_id = sob_id;
+		sob_id += reserved_sobs_per_group;
+		gaudi_sob_group_hw_reset(&prop->hw_sob_group[i].kref);
+	}
+
+	for (i = 0 ; i < QMAN_STREAMS; i++) {
+		prop->next_sob_group_val[i] = 1;
+		prop->curr_sob_group_idx[i] = 0;
+		gaudi_collective_map_sobs(hdev, i);
+	}
+
+	gaudi_collective_mstr_sob_mask_set(gaudi);
+
+	return 0;
+}
+
+static void gaudi_reset_sob_group(struct hl_device *hdev, u16 sob_group)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+	struct gaudi_collective_properties *cprop = &gaudi->collective_props;
+
+	kref_put(&cprop->hw_sob_group[sob_group].kref,
+					gaudi_sob_group_hw_reset);
+}
+
+static void gaudi_collective_master_init_job(struct hl_device *hdev,
+		struct hl_cs_job *job, u32 stream, u32 sob_group_offset)
+{
+	u32 master_sob_base, master_monitor, queue_id, cb_size = 0;
+	struct gaudi_collective_properties *cprop;
+	struct hl_gen_wait_properties wait_prop;
+	struct hl_sync_stream_properties *prop;
+	struct gaudi_device *gaudi;
+
+	gaudi = hdev->asic_specific;
+	cprop = &gaudi->collective_props;
+	queue_id = job->hw_queue_id;
+	prop = &hdev->kernel_queues[queue_id].sync_stream_prop;
+
+	master_sob_base =
+		cprop->hw_sob_group[sob_group_offset].base_sob_id;
+	master_monitor = prop->collective_mstr_mon_id[0];
+
+	cprop->hw_sob_group[sob_group_offset].queue_id = queue_id;
+
+	dev_dbg(hdev->dev,
+		"Generate master wait CBs, sob %d (mask %#x), val:0x%x, mon %u, q %d\n",
+		master_sob_base, cprop->mstr_sob_mask[0],
+		cprop->next_sob_group_val[stream],
+		master_monitor, queue_id);
+
+	wait_prop.data = (void *) job->patched_cb;
+	wait_prop.sob_base = master_sob_base;
+	wait_prop.sob_mask = cprop->mstr_sob_mask[0];
+	wait_prop.sob_val = cprop->next_sob_group_val[stream];
+	wait_prop.mon_id = master_monitor;
+	wait_prop.q_idx = queue_id;
+	wait_prop.size = cb_size;
+	cb_size += gaudi_gen_wait_cb(hdev, &wait_prop);
+
+	master_sob_base += HL_MAX_SOBS_PER_MONITOR;
+	master_monitor = prop->collective_mstr_mon_id[1];
+
+	dev_dbg(hdev->dev,
+		"Generate master wait CBs, sob %d (mask %#x), val:0x%x, mon %u, q %d\n",
+		master_sob_base, cprop->mstr_sob_mask[1],
+		cprop->next_sob_group_val[stream],
+		master_monitor, queue_id);
+
+	wait_prop.sob_base = master_sob_base;
+	wait_prop.sob_mask = cprop->mstr_sob_mask[1];
+	wait_prop.mon_id = master_monitor;
+	wait_prop.size = cb_size;
+	cb_size += gaudi_gen_wait_cb(hdev, &wait_prop);
+}
+
+static void gaudi_collective_slave_init_job(struct hl_device *hdev,
+		struct hl_cs_job *job, struct hl_cs_compl *cs_cmpl)
+{
+	struct hl_gen_wait_properties wait_prop;
+	struct hl_sync_stream_properties *prop;
+	u32 queue_id, cb_size = 0;
+
+	queue_id = job->hw_queue_id;
+	prop = &hdev->kernel_queues[queue_id].sync_stream_prop;
+
+	if (job->cs->encaps_signals) {
+		/* use the encaps signal handle store earlier in the flow
+		 * and set the SOB information from the encaps
+		 * signals handle
+		 */
+		hl_hw_queue_encaps_sig_set_sob_info(hdev, job->cs, job,
+						cs_cmpl);
+
+		dev_dbg(hdev->dev, "collective wait: Sequence %llu found, sob_id: %u,  wait for sob_val: %u\n",
+				job->cs->sequence,
+				cs_cmpl->hw_sob->sob_id,
+				cs_cmpl->sob_val);
+	}
+
+	/* Add to wait CBs using slave monitor */
+	wait_prop.data = (void *) job->user_cb;
+	wait_prop.sob_base = cs_cmpl->hw_sob->sob_id;
+	wait_prop.sob_mask = 0x1;
+	wait_prop.sob_val = cs_cmpl->sob_val;
+	wait_prop.mon_id = prop->collective_slave_mon_id;
+	wait_prop.q_idx = queue_id;
+	wait_prop.size = cb_size;
+
+	dev_dbg(hdev->dev,
+		"Generate slave wait CB, sob %d, val:%x, mon %d, q %d\n",
+		cs_cmpl->hw_sob->sob_id, cs_cmpl->sob_val,
+		prop->collective_slave_mon_id, queue_id);
+
+	cb_size += gaudi_gen_wait_cb(hdev, &wait_prop);
+
+	dev_dbg(hdev->dev,
+		"generate signal CB, sob_id: %d, sob val: 1, q_idx: %d\n",
+		prop->collective_sob_id, queue_id);
+
+	cb_size += gaudi_gen_signal_cb(hdev, job->user_cb,
+			prop->collective_sob_id, cb_size, false);
+}
+
+static int gaudi_collective_wait_init_cs(struct hl_cs *cs)
+{
+	struct hl_cs_compl *signal_cs_cmpl =
+		container_of(cs->signal_fence, struct hl_cs_compl, base_fence);
+	struct hl_cs_compl *cs_cmpl =
+		container_of(cs->fence, struct hl_cs_compl, base_fence);
+	struct hl_cs_encaps_sig_handle *handle = cs->encaps_sig_hdl;
+	struct gaudi_collective_properties *cprop;
+	u32 stream, queue_id, sob_group_offset;
+	struct gaudi_device *gaudi;
+	struct hl_device *hdev;
+	struct hl_cs_job *job;
+	struct hl_ctx *ctx;
+
+	ctx = cs->ctx;
+	hdev = ctx->hdev;
+	gaudi = hdev->asic_specific;
+	cprop = &gaudi->collective_props;
+
+	if (cs->encaps_signals) {
+		cs_cmpl->hw_sob = handle->hw_sob;
+		/* at this checkpoint we only need the hw_sob pointer
+		 * for the completion check before start going over the jobs
+		 * of the master/slaves, the sob_value will be taken later on
+		 * in gaudi_collective_slave_init_job depends on each
+		 * job wait offset value.
+		 */
+		cs_cmpl->sob_val = 0;
+	} else {
+		/* copy the SOB id and value of the signal CS */
+		cs_cmpl->hw_sob = signal_cs_cmpl->hw_sob;
+		cs_cmpl->sob_val = signal_cs_cmpl->sob_val;
+	}
+
+	/* check again if the signal cs already completed.
+	 * if yes then don't send any wait cs since the hw_sob
+	 * could be in reset already. if signal is not completed
+	 * then get refcount to hw_sob to prevent resetting the sob
+	 * while wait cs is not submitted.
+	 * note that this check is protected by two locks,
+	 * hw queue lock and completion object lock,
+	 * and the same completion object lock also protects
+	 * the hw_sob reset handler function.
+	 * The hw_queue lock prevent out of sync of hw_sob
+	 * refcount value, changed by signal/wait flows.
+	 */
+	spin_lock(&signal_cs_cmpl->lock);
+
+	if (completion_done(&cs->signal_fence->completion)) {
+		spin_unlock(&signal_cs_cmpl->lock);
+		return -EINVAL;
+	}
+	/* Increment kref since all slave queues are now waiting on it */
+	kref_get(&cs_cmpl->hw_sob->kref);
+
+	spin_unlock(&signal_cs_cmpl->lock);
+
+	/* Calculate the stream from collective master queue (1st job) */
+	job = list_first_entry(&cs->job_list, struct hl_cs_job, cs_node);
+	stream = job->hw_queue_id % 4;
+	sob_group_offset =
+		stream * HL_RSVD_SOBS + cprop->curr_sob_group_idx[stream];
+
+	list_for_each_entry(job, &cs->job_list, cs_node) {
+		queue_id = job->hw_queue_id;
+
+		if (hdev->kernel_queues[queue_id].collective_mode ==
+				HL_COLLECTIVE_MASTER)
+			gaudi_collective_master_init_job(hdev, job, stream,
+						sob_group_offset);
+		else
+			gaudi_collective_slave_init_job(hdev, job, cs_cmpl);
+	}
+
+	cs_cmpl->sob_group = sob_group_offset;
+
+	/* Handle sob group kref and wraparound */
+	kref_get(&cprop->hw_sob_group[sob_group_offset].kref);
+	cprop->next_sob_group_val[stream]++;
+
+	if (cprop->next_sob_group_val[stream] == HL_MAX_SOB_VAL) {
+		/*
+		 * Decrement as we reached the max value.
+		 * The release function won't be called here as we've
+		 * just incremented the refcount.
+		 */
+		kref_put(&cprop->hw_sob_group[sob_group_offset].kref,
+				gaudi_sob_group_reset_error);
+		cprop->next_sob_group_val[stream] = 1;
+		/* only two SOBs are currently in use */
+		cprop->curr_sob_group_idx[stream] =
+			(cprop->curr_sob_group_idx[stream] + 1) &
+							(HL_RSVD_SOBS - 1);
+
+		gaudi_collective_map_sobs(hdev, stream);
+
+		dev_dbg(hdev->dev, "switched to SOB group %d, stream: %d\n",
+				cprop->curr_sob_group_idx[stream], stream);
+	}
+
+	mb();
+	hl_fence_put(cs->signal_fence);
+	cs->signal_fence = NULL;
+
+	return 0;
+}
+
+static u32 gaudi_get_patched_cb_extra_size(u32 user_cb_size)
+{
+	u32 cacheline_end, additional_commands;
+
+	cacheline_end = round_up(user_cb_size, DEVICE_CACHE_LINE_SIZE);
+	additional_commands = sizeof(struct packet_msg_prot) * 2;
+
+	if (user_cb_size + additional_commands > cacheline_end)
+		return cacheline_end - user_cb_size + additional_commands;
+	else
+		return additional_commands;
+}
+
+static int gaudi_collective_wait_create_job(struct hl_device *hdev,
+		struct hl_ctx *ctx, struct hl_cs *cs,
+		enum hl_collective_mode mode, u32 queue_id, u32 wait_queue_id,
+		u32 encaps_signal_offset)
+{
+	struct hw_queue_properties *hw_queue_prop;
+	struct hl_cs_counters_atomic *cntr;
+	struct hl_cs_job *job;
+	struct hl_cb *cb;
+	u32 cb_size;
+	bool patched_cb;
+
+	cntr = &hdev->aggregated_cs_counters;
+
+	if (mode == HL_COLLECTIVE_MASTER) {
+		/* CB size of collective master queue contains
+		 * 4 msg short packets for monitor 1 configuration
+		 * 1 fence packet
+		 * 4 msg short packets for monitor 2 configuration
+		 * 1 fence packet
+		 * 2 msg prot packets for completion and MSI
+		 */
+		cb_size = sizeof(struct packet_msg_short) * 8 +
+				sizeof(struct packet_fence) * 2 +
+				sizeof(struct packet_msg_prot) * 2;
+		patched_cb = true;
+	} else {
+		/* CB size of collective slave queues contains
+		 * 4 msg short packets for monitor configuration
+		 * 1 fence packet
+		 * 1 additional msg short packet for sob signal
+		 */
+		cb_size = sizeof(struct packet_msg_short) * 5 +
+				sizeof(struct packet_fence);
+		patched_cb = false;
+	}
+
+	hw_queue_prop = &hdev->asic_prop.hw_queues_props[queue_id];
+	job = hl_cs_allocate_job(hdev, hw_queue_prop->type, true);
+	if (!job) {
+		atomic64_inc(&ctx->cs_counters.out_of_mem_drop_cnt);
+		atomic64_inc(&cntr->out_of_mem_drop_cnt);
+		dev_err(hdev->dev, "Failed to allocate a new job\n");
+		return -ENOMEM;
+	}
+
+	/* Allocate internal mapped CB for non patched CBs */
+	cb = hl_cb_kernel_create(hdev, cb_size, !patched_cb);
+	if (!cb) {
+		atomic64_inc(&ctx->cs_counters.out_of_mem_drop_cnt);
+		atomic64_inc(&cntr->out_of_mem_drop_cnt);
+		kfree(job);
+		return -EFAULT;
+	}
+
+	job->id = 0;
+	job->cs = cs;
+	job->user_cb = cb;
+	atomic_inc(&job->user_cb->cs_cnt);
+	job->user_cb_size = cb_size;
+	job->hw_queue_id = queue_id;
+
+	/* since its guaranteed to have only one chunk in the collective wait
+	 * cs, we can use this chunk to set the encapsulated signal offset
+	 * in the jobs.
+	 */
+	if (cs->encaps_signals)
+		job->encaps_sig_wait_offset = encaps_signal_offset;
+
+	/*
+	 * No need in parsing, user CB is the patched CB.
+	 * We call hl_cb_destroy() out of two reasons - we don't need
+	 * the CB in the CB idr anymore and to decrement its refcount as
+	 * it was incremented inside hl_cb_kernel_create().
+	 */
+	if (patched_cb)
+		job->patched_cb = job->user_cb;
+	else
+		job->patched_cb = NULL;
+
+	job->job_cb_size = job->user_cb_size;
+	hl_cb_destroy(&hdev->kernel_mem_mgr, cb->buf->handle);
+
+	/* increment refcount as for external queues we get completion */
+	if (hw_queue_prop->type == QUEUE_TYPE_EXT)
+		cs_get(cs);
+
+	cs->jobs_in_queue_cnt[job->hw_queue_id]++;
+
+	list_add_tail(&job->cs_node, &cs->job_list);
+
+	hl_debugfs_add_job(hdev, job);
+
+	return 0;
+}
+
+static int gaudi_collective_wait_create_jobs(struct hl_device *hdev,
+		struct hl_ctx *ctx, struct hl_cs *cs,
+		u32 wait_queue_id, u32 collective_engine_id,
+		u32 encaps_signal_offset)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+	struct hw_queue_properties *hw_queue_prop;
+	u32 queue_id, collective_queue, num_jobs;
+	u32 stream, nic_queue, nic_idx = 0;
+	bool skip;
+	int i, rc = 0;
+
+	/* Verify wait queue id is configured as master */
+	hw_queue_prop = &hdev->asic_prop.hw_queues_props[wait_queue_id];
+	if (!(hw_queue_prop->collective_mode == HL_COLLECTIVE_MASTER)) {
+		dev_err(hdev->dev,
+			"Queue %d is not configured as collective master\n",
+			wait_queue_id);
+		return -EINVAL;
+	}
+
+	/* Verify engine id is supported */
+	if (collective_engine_id != GAUDI_ENGINE_ID_DMA_5 &&
+			collective_engine_id != GAUDI_ENGINE_ID_TPC_7) {
+		dev_err(hdev->dev,
+			"Collective wait does not support engine %u\n",
+			collective_engine_id);
+		return -EINVAL;
+	}
+
+	stream = wait_queue_id % 4;
+
+	if (collective_engine_id == GAUDI_ENGINE_ID_DMA_5)
+		collective_queue = GAUDI_QUEUE_ID_DMA_5_0 + stream;
+	else
+		collective_queue = GAUDI_QUEUE_ID_TPC_7_0 + stream;
+
+	num_jobs = NUMBER_OF_SOBS_IN_GRP + 1;
+	nic_queue = GAUDI_QUEUE_ID_NIC_0_0 + stream;
+
+	/* First job goes to the collective master queue, it will wait for
+	 * the collective slave queues to finish execution.
+	 * The synchronization is done using two monitors:
+	 * First monitor for NICs 0-7, second monitor for NICs 8-9 and the
+	 * reduction engine (DMA5/TPC7).
+	 *
+	 * Rest of the jobs goes to the collective slave queues which will
+	 * all wait for the user to signal sob 'cs_cmpl->sob_val'.
+	 */
+	for (i = 0 ; i < num_jobs ; i++) {
+		if (i == 0) {
+			queue_id = wait_queue_id;
+			rc = gaudi_collective_wait_create_job(hdev, ctx, cs,
+				HL_COLLECTIVE_MASTER, queue_id,
+				wait_queue_id, encaps_signal_offset);
+		} else {
+			if (nic_idx < NIC_NUMBER_OF_ENGINES) {
+				if (gaudi->hw_cap_initialized &
+					BIT(HW_CAP_NIC_SHIFT + nic_idx))
+					skip = false;
+				else
+					skip = true;
+
+				queue_id = nic_queue;
+				nic_queue += 4;
+				nic_idx++;
+
+				if (skip)
+					continue;
+			} else {
+				queue_id = collective_queue;
+			}
+
+			rc = gaudi_collective_wait_create_job(hdev, ctx, cs,
+				HL_COLLECTIVE_SLAVE, queue_id,
+				wait_queue_id, encaps_signal_offset);
+		}
+
+		if (rc)
+			return rc;
+	}
+
+	return rc;
+}
+
+static int gaudi_late_init(struct hl_device *hdev)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+	int rc;
+
+	rc = gaudi->cpucp_info_get(hdev);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to get cpucp info\n");
+		return rc;
+	}
+
+	if ((hdev->card_type == cpucp_card_type_pci) &&
+			(hdev->nic_ports_mask & 0x3)) {
+		dev_info(hdev->dev,
+			"PCI card detected, only 8 ports are enabled\n");
+		hdev->nic_ports_mask &= ~0x3;
+
+		/* Stop and disable unused NIC QMANs */
+		WREG32(mmNIC0_QM0_GLBL_CFG1, NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK |
+					NIC0_QM0_GLBL_CFG1_CQF_STOP_MASK |
+					NIC0_QM0_GLBL_CFG1_CP_STOP_MASK);
+
+		WREG32(mmNIC0_QM1_GLBL_CFG1, NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK |
+					NIC0_QM0_GLBL_CFG1_CQF_STOP_MASK |
+					NIC0_QM0_GLBL_CFG1_CP_STOP_MASK);
+
+		WREG32(mmNIC0_QM0_GLBL_CFG0, 0);
+		WREG32(mmNIC0_QM1_GLBL_CFG0, 0);
+
+		gaudi->hw_cap_initialized &= ~(HW_CAP_NIC0 | HW_CAP_NIC1);
+	}
+
+	rc = hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_ENABLE_PCI_ACCESS, 0x0);
+	if (rc)
+		return rc;
+
+	/* Scrub both SRAM and DRAM */
+	rc = hdev->asic_funcs->scrub_device_mem(hdev);
+	if (rc)
+		goto disable_pci_access;
+
+	rc = gaudi_fetch_psoc_frequency(hdev);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to fetch psoc frequency\n");
+		goto disable_pci_access;
+	}
+
+	rc = gaudi_mmu_clear_pgt_range(hdev);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to clear MMU page tables range\n");
+		goto disable_pci_access;
+	}
+
+	rc = gaudi_init_tpc_mem(hdev);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to initialize TPC memories\n");
+		goto disable_pci_access;
+	}
+
+	rc = gaudi_collective_init(hdev);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to init collective\n");
+		goto disable_pci_access;
+	}
+
+	/* We only support a single ASID for the user, so for the sake of optimization, just
+	 * initialize the ASID one time during device initialization with the fixed value of 1
+	 */
+	gaudi_mmu_prepare(hdev, 1);
+
+	hl_fw_set_pll_profile(hdev);
+
+	return 0;
+
+disable_pci_access:
+	hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_DISABLE_PCI_ACCESS, 0x0);
+
+	return rc;
+}
+
+static void gaudi_late_fini(struct hl_device *hdev)
+{
+	hl_hwmon_release_resources(hdev);
+}
+
+static int gaudi_alloc_cpu_accessible_dma_mem(struct hl_device *hdev)
+{
+	dma_addr_t dma_addr_arr[GAUDI_ALLOC_CPU_MEM_RETRY_CNT] = {}, end_addr;
+	void *virt_addr_arr[GAUDI_ALLOC_CPU_MEM_RETRY_CNT] = {};
+	int i, j, rc = 0;
+
+	/*
+	 * The device CPU works with 40-bits addresses, while bit 39 must be set
+	 * to '1' when accessing the host.
+	 * Bits 49:39 of the full host address are saved for a later
+	 * configuration of the HW to perform extension to 50 bits.
+	 * Because there is a single HW register that holds the extension bits,
+	 * these bits must be identical in all allocated range.
+	 */
+
+	for (i = 0 ; i < GAUDI_ALLOC_CPU_MEM_RETRY_CNT ; i++) {
+		virt_addr_arr[i] = hl_asic_dma_alloc_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE,
+								&dma_addr_arr[i],
+								GFP_KERNEL | __GFP_ZERO);
+		if (!virt_addr_arr[i]) {
+			rc = -ENOMEM;
+			goto free_dma_mem_arr;
+		}
+
+		end_addr = dma_addr_arr[i] + HL_CPU_ACCESSIBLE_MEM_SIZE - 1;
+		if (GAUDI_CPU_PCI_MSB_ADDR(dma_addr_arr[i]) ==
+				GAUDI_CPU_PCI_MSB_ADDR(end_addr))
+			break;
+	}
+
+	if (i == GAUDI_ALLOC_CPU_MEM_RETRY_CNT) {
+		dev_err(hdev->dev,
+			"MSB of CPU accessible DMA memory are not identical in all range\n");
+		rc = -EFAULT;
+		goto free_dma_mem_arr;
+	}
+
+	hdev->cpu_accessible_dma_mem = virt_addr_arr[i];
+	hdev->cpu_accessible_dma_address = dma_addr_arr[i];
+	hdev->cpu_pci_msb_addr =
+		GAUDI_CPU_PCI_MSB_ADDR(hdev->cpu_accessible_dma_address);
+
+	if (!hdev->asic_prop.fw_security_enabled)
+		GAUDI_PCI_TO_CPU_ADDR(hdev->cpu_accessible_dma_address);
+
+free_dma_mem_arr:
+	for (j = 0 ; j < i ; j++)
+		hl_asic_dma_free_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE, virt_addr_arr[j],
+						dma_addr_arr[j]);
+
+	return rc;
+}
+
+static void gaudi_free_internal_qmans_pq_mem(struct hl_device *hdev)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+	struct gaudi_internal_qman_info *q;
+	u32 i;
+
+	for (i = 0 ; i < GAUDI_QUEUE_ID_SIZE ; i++) {
+		q = &gaudi->internal_qmans[i];
+		if (!q->pq_kernel_addr)
+			continue;
+		hl_asic_dma_free_coherent(hdev, q->pq_size, q->pq_kernel_addr, q->pq_dma_addr);
+	}
+}
+
+static int gaudi_alloc_internal_qmans_pq_mem(struct hl_device *hdev)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+	struct gaudi_internal_qman_info *q;
+	int rc, i;
+
+	for (i = 0 ; i < GAUDI_QUEUE_ID_SIZE ; i++) {
+		if (gaudi_queue_type[i] != QUEUE_TYPE_INT)
+			continue;
+
+		q = &gaudi->internal_qmans[i];
+
+		switch (i) {
+		case GAUDI_QUEUE_ID_DMA_2_0 ... GAUDI_QUEUE_ID_DMA_7_3:
+			q->pq_size = HBM_DMA_QMAN_SIZE_IN_BYTES;
+			break;
+		case GAUDI_QUEUE_ID_MME_0_0 ... GAUDI_QUEUE_ID_MME_1_3:
+			q->pq_size = MME_QMAN_SIZE_IN_BYTES;
+			break;
+		case GAUDI_QUEUE_ID_TPC_0_0 ... GAUDI_QUEUE_ID_TPC_7_3:
+			q->pq_size = TPC_QMAN_SIZE_IN_BYTES;
+			break;
+		case GAUDI_QUEUE_ID_NIC_0_0 ... GAUDI_QUEUE_ID_NIC_9_3:
+			q->pq_size = NIC_QMAN_SIZE_IN_BYTES;
+			break;
+		default:
+			dev_err(hdev->dev, "Bad internal queue index %d", i);
+			rc = -EINVAL;
+			goto free_internal_qmans_pq_mem;
+		}
+
+		q->pq_kernel_addr = hl_asic_dma_alloc_coherent(hdev, q->pq_size, &q->pq_dma_addr,
+								GFP_KERNEL | __GFP_ZERO);
+		if (!q->pq_kernel_addr) {
+			rc = -ENOMEM;
+			goto free_internal_qmans_pq_mem;
+		}
+	}
+
+	return 0;
+
+free_internal_qmans_pq_mem:
+	gaudi_free_internal_qmans_pq_mem(hdev);
+	return rc;
+}
+
+static void gaudi_set_pci_memory_regions(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct pci_mem_region *region;
+
+	/* CFG */
+	region = &hdev->pci_mem_region[PCI_REGION_CFG];
+	region->region_base = CFG_BASE;
+	region->region_size = CFG_SIZE;
+	region->offset_in_bar = CFG_BASE - SPI_FLASH_BASE_ADDR;
+	region->bar_size = CFG_BAR_SIZE;
+	region->bar_id = CFG_BAR_ID;
+	region->used = 1;
+
+	/* SRAM */
+	region = &hdev->pci_mem_region[PCI_REGION_SRAM];
+	region->region_base = SRAM_BASE_ADDR;
+	region->region_size = SRAM_SIZE;
+	region->offset_in_bar = 0;
+	region->bar_size = SRAM_BAR_SIZE;
+	region->bar_id = SRAM_BAR_ID;
+	region->used = 1;
+
+	/* DRAM */
+	region = &hdev->pci_mem_region[PCI_REGION_DRAM];
+	region->region_base = DRAM_PHYS_BASE;
+	region->region_size = hdev->asic_prop.dram_size;
+	region->offset_in_bar = 0;
+	region->bar_size = prop->dram_pci_bar_size;
+	region->bar_id = HBM_BAR_ID;
+	region->used = 1;
+
+	/* SP SRAM */
+	region = &hdev->pci_mem_region[PCI_REGION_SP_SRAM];
+	region->region_base = PSOC_SCRATCHPAD_ADDR;
+	region->region_size = PSOC_SCRATCHPAD_SIZE;
+	region->offset_in_bar = PSOC_SCRATCHPAD_ADDR - SPI_FLASH_BASE_ADDR;
+	region->bar_size = CFG_BAR_SIZE;
+	region->bar_id = CFG_BAR_ID;
+	region->used = 1;
+}
+
+static int gaudi_sw_init(struct hl_device *hdev)
+{
+	struct gaudi_device *gaudi;
+	u32 i, event_id = 0;
+	int rc;
+
+	/* Allocate device structure */
+	gaudi = kzalloc(sizeof(*gaudi), GFP_KERNEL);
+	if (!gaudi)
+		return -ENOMEM;
+
+	for (i = 0 ; i < ARRAY_SIZE(gaudi_irq_map_table) ; i++) {
+		if (gaudi_irq_map_table[i].valid) {
+			if (event_id == GAUDI_EVENT_SIZE) {
+				dev_err(hdev->dev,
+					"Event array exceeds the limit of %u events\n",
+					GAUDI_EVENT_SIZE);
+				rc = -EINVAL;
+				goto free_gaudi_device;
+			}
+
+			gaudi->events[event_id++] =
+					gaudi_irq_map_table[i].fc_id;
+		}
+	}
+
+	gaudi->cpucp_info_get = gaudi_cpucp_info_get;
+
+	hdev->asic_specific = gaudi;
+
+	/* Create DMA pool for small allocations */
+	hdev->dma_pool = dma_pool_create(dev_name(hdev->dev),
+			&hdev->pdev->dev, GAUDI_DMA_POOL_BLK_SIZE, 8, 0);
+	if (!hdev->dma_pool) {
+		dev_err(hdev->dev, "failed to create DMA pool\n");
+		rc = -ENOMEM;
+		goto free_gaudi_device;
+	}
+
+	rc = gaudi_alloc_cpu_accessible_dma_mem(hdev);
+	if (rc)
+		goto free_dma_pool;
+
+	hdev->cpu_accessible_dma_pool = gen_pool_create(ilog2(32), -1);
+	if (!hdev->cpu_accessible_dma_pool) {
+		dev_err(hdev->dev,
+			"Failed to create CPU accessible DMA pool\n");
+		rc = -ENOMEM;
+		goto free_cpu_dma_mem;
+	}
+
+	rc = gen_pool_add(hdev->cpu_accessible_dma_pool,
+				(uintptr_t) hdev->cpu_accessible_dma_mem,
+				HL_CPU_ACCESSIBLE_MEM_SIZE, -1);
+	if (rc) {
+		dev_err(hdev->dev,
+			"Failed to add memory to CPU accessible DMA pool\n");
+		rc = -EFAULT;
+		goto free_cpu_accessible_dma_pool;
+	}
+
+	rc = gaudi_alloc_internal_qmans_pq_mem(hdev);
+	if (rc)
+		goto free_cpu_accessible_dma_pool;
+
+	spin_lock_init(&gaudi->hw_queues_lock);
+
+	hdev->supports_sync_stream = true;
+	hdev->supports_coresight = true;
+	hdev->supports_staged_submission = true;
+	hdev->supports_wait_for_multi_cs = true;
+
+	hdev->asic_funcs->set_pci_memory_regions(hdev);
+	hdev->stream_master_qid_arr =
+				hdev->asic_funcs->get_stream_master_qid_arr();
+	hdev->stream_master_qid_arr_size = GAUDI_STREAM_MASTER_ARR_SIZE;
+
+	return 0;
+
+free_cpu_accessible_dma_pool:
+	gen_pool_destroy(hdev->cpu_accessible_dma_pool);
+free_cpu_dma_mem:
+	if (!hdev->asic_prop.fw_security_enabled)
+		GAUDI_CPU_TO_PCI_ADDR(hdev->cpu_accessible_dma_address,
+					hdev->cpu_pci_msb_addr);
+	hl_asic_dma_free_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE, hdev->cpu_accessible_dma_mem,
+					hdev->cpu_accessible_dma_address);
+free_dma_pool:
+	dma_pool_destroy(hdev->dma_pool);
+free_gaudi_device:
+	kfree(gaudi);
+	return rc;
+}
+
+static int gaudi_sw_fini(struct hl_device *hdev)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+
+	gaudi_free_internal_qmans_pq_mem(hdev);
+
+	gen_pool_destroy(hdev->cpu_accessible_dma_pool);
+
+	if (!hdev->asic_prop.fw_security_enabled)
+		GAUDI_CPU_TO_PCI_ADDR(hdev->cpu_accessible_dma_address,
+					hdev->cpu_pci_msb_addr);
+
+	hl_asic_dma_free_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE, hdev->cpu_accessible_dma_mem,
+					hdev->cpu_accessible_dma_address);
+
+	dma_pool_destroy(hdev->dma_pool);
+
+	kfree(gaudi);
+
+	return 0;
+}
+
+static irqreturn_t gaudi_irq_handler_single(int irq, void *arg)
+{
+	struct hl_device *hdev = arg;
+	int i;
+
+	if (hdev->disabled)
+		return IRQ_HANDLED;
+
+	for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++)
+		hl_irq_handler_cq(irq, &hdev->completion_queue[i]);
+
+	hl_irq_handler_eq(irq, &hdev->event_queue);
+
+	return IRQ_HANDLED;
+}
+
+/*
+ * For backward compatibility, new MSI interrupts should be set after the
+ * existing CPU and NIC interrupts.
+ */
+static int gaudi_pci_irq_vector(struct hl_device *hdev, unsigned int nr,
+				bool cpu_eq)
+{
+	int msi_vec;
+
+	if ((nr != GAUDI_EVENT_QUEUE_MSI_IDX) && (cpu_eq))
+		dev_crit(hdev->dev, "CPU EQ must use IRQ %d\n",
+				GAUDI_EVENT_QUEUE_MSI_IDX);
+
+	msi_vec = ((nr < GAUDI_EVENT_QUEUE_MSI_IDX) || (cpu_eq)) ? nr :
+			(nr + NIC_NUMBER_OF_ENGINES + 1);
+
+	return pci_irq_vector(hdev->pdev, msi_vec);
+}
+
+static int gaudi_enable_msi_single(struct hl_device *hdev)
+{
+	int rc, irq;
+
+	dev_dbg(hdev->dev, "Working in single MSI IRQ mode\n");
+
+	irq = gaudi_pci_irq_vector(hdev, 0, false);
+	rc = request_irq(irq, gaudi_irq_handler_single, 0,
+			"gaudi single msi", hdev);
+	if (rc)
+		dev_err(hdev->dev,
+			"Failed to request single MSI IRQ\n");
+
+	return rc;
+}
+
+static int gaudi_enable_msi(struct hl_device *hdev)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+	int rc;
+
+	if (gaudi->hw_cap_initialized & HW_CAP_MSI)
+		return 0;
+
+	rc = pci_alloc_irq_vectors(hdev->pdev, 1, 1, PCI_IRQ_MSI);
+	if (rc < 0) {
+		dev_err(hdev->dev, "MSI: Failed to enable support %d\n", rc);
+		return rc;
+	}
+
+	rc = gaudi_enable_msi_single(hdev);
+	if (rc)
+		goto free_pci_irq_vectors;
+
+	gaudi->hw_cap_initialized |= HW_CAP_MSI;
+
+	return 0;
+
+free_pci_irq_vectors:
+	pci_free_irq_vectors(hdev->pdev);
+	return rc;
+}
+
+static void gaudi_sync_irqs(struct hl_device *hdev)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+
+	if (!(gaudi->hw_cap_initialized & HW_CAP_MSI))
+		return;
+
+	/* Wait for all pending IRQs to be finished */
+	synchronize_irq(gaudi_pci_irq_vector(hdev, 0, false));
+}
+
+static void gaudi_disable_msi(struct hl_device *hdev)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+
+	if (!(gaudi->hw_cap_initialized & HW_CAP_MSI))
+		return;
+
+	gaudi_sync_irqs(hdev);
+	free_irq(gaudi_pci_irq_vector(hdev, 0, false), hdev);
+	pci_free_irq_vectors(hdev->pdev);
+
+	gaudi->hw_cap_initialized &= ~HW_CAP_MSI;
+}
+
+static void gaudi_init_scrambler_sram(struct hl_device *hdev)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+
+	if (hdev->asic_prop.fw_security_enabled)
+		return;
+
+	if (hdev->asic_prop.fw_app_cpu_boot_dev_sts0 &
+						CPU_BOOT_DEV_STS0_SRAM_SCR_EN)
+		return;
+
+	if (gaudi->hw_cap_initialized & HW_CAP_SRAM_SCRAMBLER)
+		return;
+
+	WREG32(mmNIF_RTR_CTRL_0_SCRAM_SRAM_EN,
+			1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT);
+	WREG32(mmNIF_RTR_CTRL_1_SCRAM_SRAM_EN,
+			1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT);
+	WREG32(mmNIF_RTR_CTRL_2_SCRAM_SRAM_EN,
+			1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT);
+	WREG32(mmNIF_RTR_CTRL_3_SCRAM_SRAM_EN,
+			1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT);
+	WREG32(mmNIF_RTR_CTRL_4_SCRAM_SRAM_EN,
+			1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT);
+	WREG32(mmNIF_RTR_CTRL_5_SCRAM_SRAM_EN,
+			1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT);
+	WREG32(mmNIF_RTR_CTRL_6_SCRAM_SRAM_EN,
+			1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT);
+	WREG32(mmNIF_RTR_CTRL_7_SCRAM_SRAM_EN,
+			1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT);
+
+	WREG32(mmSIF_RTR_CTRL_0_SCRAM_SRAM_EN,
+			1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT);
+	WREG32(mmSIF_RTR_CTRL_1_SCRAM_SRAM_EN,
+			1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT);
+	WREG32(mmSIF_RTR_CTRL_2_SCRAM_SRAM_EN,
+			1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT);
+	WREG32(mmSIF_RTR_CTRL_3_SCRAM_SRAM_EN,
+			1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT);
+	WREG32(mmSIF_RTR_CTRL_4_SCRAM_SRAM_EN,
+			1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT);
+	WREG32(mmSIF_RTR_CTRL_5_SCRAM_SRAM_EN,
+			1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT);
+	WREG32(mmSIF_RTR_CTRL_6_SCRAM_SRAM_EN,
+			1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT);
+	WREG32(mmSIF_RTR_CTRL_7_SCRAM_SRAM_EN,
+			1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT);
+
+	WREG32(mmDMA_IF_E_N_DOWN_CH0_SCRAM_SRAM_EN,
+			1 << DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT);
+	WREG32(mmDMA_IF_E_N_DOWN_CH1_SCRAM_SRAM_EN,
+			1 << DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT);
+	WREG32(mmDMA_IF_E_S_DOWN_CH0_SCRAM_SRAM_EN,
+			1 << DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT);
+	WREG32(mmDMA_IF_E_S_DOWN_CH1_SCRAM_SRAM_EN,
+			1 << DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT);
+	WREG32(mmDMA_IF_W_N_DOWN_CH0_SCRAM_SRAM_EN,
+			1 << DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT);
+	WREG32(mmDMA_IF_W_N_DOWN_CH1_SCRAM_SRAM_EN,
+			1 << DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT);
+	WREG32(mmDMA_IF_W_S_DOWN_CH0_SCRAM_SRAM_EN,
+			1 << DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT);
+	WREG32(mmDMA_IF_W_S_DOWN_CH1_SCRAM_SRAM_EN,
+			1 << DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT);
+
+	gaudi->hw_cap_initialized |= HW_CAP_SRAM_SCRAMBLER;
+}
+
+static void gaudi_init_scrambler_hbm(struct hl_device *hdev)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+
+	if (hdev->asic_prop.fw_security_enabled)
+		return;
+
+	if (hdev->asic_prop.fw_bootfit_cpu_boot_dev_sts0 &
+					CPU_BOOT_DEV_STS0_DRAM_SCR_EN)
+		return;
+
+	if (gaudi->hw_cap_initialized & HW_CAP_HBM_SCRAMBLER)
+		return;
+
+	WREG32(mmNIF_RTR_CTRL_0_SCRAM_HBM_EN,
+			1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT);
+	WREG32(mmNIF_RTR_CTRL_1_SCRAM_HBM_EN,
+			1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT);
+	WREG32(mmNIF_RTR_CTRL_2_SCRAM_HBM_EN,
+			1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT);
+	WREG32(mmNIF_RTR_CTRL_3_SCRAM_HBM_EN,
+			1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT);
+	WREG32(mmNIF_RTR_CTRL_4_SCRAM_HBM_EN,
+			1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT);
+	WREG32(mmNIF_RTR_CTRL_5_SCRAM_HBM_EN,
+			1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT);
+	WREG32(mmNIF_RTR_CTRL_6_SCRAM_HBM_EN,
+			1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT);
+	WREG32(mmNIF_RTR_CTRL_7_SCRAM_HBM_EN,
+			1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT);
+
+	WREG32(mmSIF_RTR_CTRL_0_SCRAM_HBM_EN,
+			1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT);
+	WREG32(mmSIF_RTR_CTRL_1_SCRAM_HBM_EN,
+			1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT);
+	WREG32(mmSIF_RTR_CTRL_2_SCRAM_HBM_EN,
+			1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT);
+	WREG32(mmSIF_RTR_CTRL_3_SCRAM_HBM_EN,
+			1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT);
+	WREG32(mmSIF_RTR_CTRL_4_SCRAM_HBM_EN,
+			1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT);
+	WREG32(mmSIF_RTR_CTRL_5_SCRAM_HBM_EN,
+			1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT);
+	WREG32(mmSIF_RTR_CTRL_6_SCRAM_HBM_EN,
+			1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT);
+	WREG32(mmSIF_RTR_CTRL_7_SCRAM_HBM_EN,
+			1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT);
+
+	WREG32(mmDMA_IF_E_N_DOWN_CH0_SCRAM_HBM_EN,
+			1 << DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT);
+	WREG32(mmDMA_IF_E_N_DOWN_CH1_SCRAM_HBM_EN,
+			1 << DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT);
+	WREG32(mmDMA_IF_E_S_DOWN_CH0_SCRAM_HBM_EN,
+			1 << DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT);
+	WREG32(mmDMA_IF_E_S_DOWN_CH1_SCRAM_HBM_EN,
+			1 << DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT);
+	WREG32(mmDMA_IF_W_N_DOWN_CH0_SCRAM_HBM_EN,
+			1 << DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT);
+	WREG32(mmDMA_IF_W_N_DOWN_CH1_SCRAM_HBM_EN,
+			1 << DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT);
+	WREG32(mmDMA_IF_W_S_DOWN_CH0_SCRAM_HBM_EN,
+			1 << DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT);
+	WREG32(mmDMA_IF_W_S_DOWN_CH1_SCRAM_HBM_EN,
+			1 << DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT);
+
+	gaudi->hw_cap_initialized |= HW_CAP_HBM_SCRAMBLER;
+}
+
+static void gaudi_init_e2e(struct hl_device *hdev)
+{
+	if (hdev->asic_prop.fw_security_enabled)
+		return;
+
+	if (hdev->asic_prop.fw_bootfit_cpu_boot_dev_sts0 &
+					CPU_BOOT_DEV_STS0_E2E_CRED_EN)
+		return;
+
+	WREG32(mmSIF_RTR_CTRL_0_E2E_HBM_WR_SIZE, 247 >> 3);
+	WREG32(mmSIF_RTR_CTRL_0_E2E_HBM_RD_SIZE, 785 >> 3);
+	WREG32(mmSIF_RTR_CTRL_0_E2E_PCI_WR_SIZE, 49);
+	WREG32(mmSIF_RTR_CTRL_0_E2E_PCI_RD_SIZE, 101);
+
+	WREG32(mmSIF_RTR_CTRL_1_E2E_HBM_WR_SIZE, 275 >> 3);
+	WREG32(mmSIF_RTR_CTRL_1_E2E_HBM_RD_SIZE, 614 >> 3);
+	WREG32(mmSIF_RTR_CTRL_1_E2E_PCI_WR_SIZE, 1);
+	WREG32(mmSIF_RTR_CTRL_1_E2E_PCI_RD_SIZE, 39);
+
+	WREG32(mmSIF_RTR_CTRL_2_E2E_HBM_WR_SIZE, 1);
+	WREG32(mmSIF_RTR_CTRL_2_E2E_HBM_RD_SIZE, 1);
+	WREG32(mmSIF_RTR_CTRL_2_E2E_PCI_WR_SIZE, 1);
+	WREG32(mmSIF_RTR_CTRL_2_E2E_PCI_RD_SIZE, 32);
+
+	WREG32(mmSIF_RTR_CTRL_3_E2E_HBM_WR_SIZE, 176 >> 3);
+	WREG32(mmSIF_RTR_CTRL_3_E2E_HBM_RD_SIZE, 32 >> 3);
+	WREG32(mmSIF_RTR_CTRL_3_E2E_PCI_WR_SIZE, 19);
+	WREG32(mmSIF_RTR_CTRL_3_E2E_PCI_RD_SIZE, 32);
+
+	WREG32(mmSIF_RTR_CTRL_4_E2E_HBM_WR_SIZE, 176 >> 3);
+	WREG32(mmSIF_RTR_CTRL_4_E2E_HBM_RD_SIZE, 32 >> 3);
+	WREG32(mmSIF_RTR_CTRL_4_E2E_PCI_WR_SIZE, 19);
+	WREG32(mmSIF_RTR_CTRL_4_E2E_PCI_RD_SIZE, 32);
+
+	WREG32(mmSIF_RTR_CTRL_5_E2E_HBM_WR_SIZE, 1);
+	WREG32(mmSIF_RTR_CTRL_5_E2E_HBM_RD_SIZE, 1);
+	WREG32(mmSIF_RTR_CTRL_5_E2E_PCI_WR_SIZE, 1);
+	WREG32(mmSIF_RTR_CTRL_5_E2E_PCI_RD_SIZE, 32);
+
+	WREG32(mmSIF_RTR_CTRL_6_E2E_HBM_WR_SIZE, 275 >> 3);
+	WREG32(mmSIF_RTR_CTRL_6_E2E_HBM_RD_SIZE, 614 >> 3);
+	WREG32(mmSIF_RTR_CTRL_6_E2E_PCI_WR_SIZE, 1);
+	WREG32(mmSIF_RTR_CTRL_6_E2E_PCI_RD_SIZE, 39);
+
+	WREG32(mmSIF_RTR_CTRL_7_E2E_HBM_WR_SIZE, 297 >> 3);
+	WREG32(mmSIF_RTR_CTRL_7_E2E_HBM_RD_SIZE, 908 >> 3);
+	WREG32(mmSIF_RTR_CTRL_7_E2E_PCI_WR_SIZE, 19);
+	WREG32(mmSIF_RTR_CTRL_7_E2E_PCI_RD_SIZE, 19);
+
+	WREG32(mmNIF_RTR_CTRL_0_E2E_HBM_WR_SIZE, 318 >> 3);
+	WREG32(mmNIF_RTR_CTRL_0_E2E_HBM_RD_SIZE, 956 >> 3);
+	WREG32(mmNIF_RTR_CTRL_0_E2E_PCI_WR_SIZE, 79);
+	WREG32(mmNIF_RTR_CTRL_0_E2E_PCI_RD_SIZE, 163);
+
+	WREG32(mmNIF_RTR_CTRL_1_E2E_HBM_WR_SIZE, 275 >> 3);
+	WREG32(mmNIF_RTR_CTRL_1_E2E_HBM_RD_SIZE, 614 >> 3);
+	WREG32(mmNIF_RTR_CTRL_1_E2E_PCI_WR_SIZE, 1);
+	WREG32(mmNIF_RTR_CTRL_1_E2E_PCI_RD_SIZE, 39);
+
+	WREG32(mmNIF_RTR_CTRL_2_E2E_HBM_WR_SIZE, 1);
+	WREG32(mmNIF_RTR_CTRL_2_E2E_HBM_RD_SIZE, 1);
+	WREG32(mmNIF_RTR_CTRL_2_E2E_PCI_WR_SIZE, 1);
+	WREG32(mmNIF_RTR_CTRL_2_E2E_PCI_RD_SIZE, 32);
+
+	WREG32(mmNIF_RTR_CTRL_3_E2E_HBM_WR_SIZE, 176 >> 3);
+	WREG32(mmNIF_RTR_CTRL_3_E2E_HBM_RD_SIZE, 32 >> 3);
+	WREG32(mmNIF_RTR_CTRL_3_E2E_PCI_WR_SIZE, 19);
+	WREG32(mmNIF_RTR_CTRL_3_E2E_PCI_RD_SIZE, 32);
+
+	WREG32(mmNIF_RTR_CTRL_4_E2E_HBM_WR_SIZE, 176 >> 3);
+	WREG32(mmNIF_RTR_CTRL_4_E2E_HBM_RD_SIZE, 32 >> 3);
+	WREG32(mmNIF_RTR_CTRL_4_E2E_PCI_WR_SIZE, 19);
+	WREG32(mmNIF_RTR_CTRL_4_E2E_PCI_RD_SIZE, 32);
+
+	WREG32(mmNIF_RTR_CTRL_5_E2E_HBM_WR_SIZE, 1);
+	WREG32(mmNIF_RTR_CTRL_5_E2E_HBM_RD_SIZE, 1);
+	WREG32(mmNIF_RTR_CTRL_5_E2E_PCI_WR_SIZE, 1);
+	WREG32(mmNIF_RTR_CTRL_5_E2E_PCI_RD_SIZE, 32);
+
+	WREG32(mmNIF_RTR_CTRL_6_E2E_HBM_WR_SIZE, 275 >> 3);
+	WREG32(mmNIF_RTR_CTRL_6_E2E_HBM_RD_SIZE, 614 >> 3);
+	WREG32(mmNIF_RTR_CTRL_6_E2E_PCI_WR_SIZE, 1);
+	WREG32(mmNIF_RTR_CTRL_6_E2E_PCI_RD_SIZE, 39);
+
+	WREG32(mmNIF_RTR_CTRL_7_E2E_HBM_WR_SIZE, 318 >> 3);
+	WREG32(mmNIF_RTR_CTRL_7_E2E_HBM_RD_SIZE, 956 >> 3);
+	WREG32(mmNIF_RTR_CTRL_7_E2E_PCI_WR_SIZE, 79);
+	WREG32(mmNIF_RTR_CTRL_7_E2E_PCI_RD_SIZE, 79);
+
+	WREG32(mmDMA_IF_E_N_DOWN_CH0_E2E_HBM_WR_SIZE, 344 >> 3);
+	WREG32(mmDMA_IF_E_N_DOWN_CH0_E2E_HBM_RD_SIZE, 1000 >> 3);
+	WREG32(mmDMA_IF_E_N_DOWN_CH0_E2E_PCI_WR_SIZE, 162);
+	WREG32(mmDMA_IF_E_N_DOWN_CH0_E2E_PCI_RD_SIZE, 338);
+
+	WREG32(mmDMA_IF_E_N_DOWN_CH1_E2E_HBM_WR_SIZE, 344 >> 3);
+	WREG32(mmDMA_IF_E_N_DOWN_CH1_E2E_HBM_RD_SIZE, 1000 >> 3);
+	WREG32(mmDMA_IF_E_N_DOWN_CH1_E2E_PCI_WR_SIZE, 162);
+	WREG32(mmDMA_IF_E_N_DOWN_CH1_E2E_PCI_RD_SIZE, 338);
+
+	WREG32(mmDMA_IF_E_S_DOWN_CH0_E2E_HBM_WR_SIZE, 344 >> 3);
+	WREG32(mmDMA_IF_E_S_DOWN_CH0_E2E_HBM_RD_SIZE, 1000 >> 3);
+	WREG32(mmDMA_IF_E_S_DOWN_CH0_E2E_PCI_WR_SIZE, 162);
+	WREG32(mmDMA_IF_E_S_DOWN_CH0_E2E_PCI_RD_SIZE, 338);
+
+	WREG32(mmDMA_IF_E_S_DOWN_CH1_E2E_HBM_WR_SIZE, 344 >> 3);
+	WREG32(mmDMA_IF_E_S_DOWN_CH1_E2E_HBM_RD_SIZE, 1000 >> 3);
+	WREG32(mmDMA_IF_E_S_DOWN_CH1_E2E_PCI_WR_SIZE, 162);
+	WREG32(mmDMA_IF_E_S_DOWN_CH1_E2E_PCI_RD_SIZE, 338);
+
+	WREG32(mmDMA_IF_W_N_DOWN_CH0_E2E_HBM_WR_SIZE, 344 >> 3);
+	WREG32(mmDMA_IF_W_N_DOWN_CH0_E2E_HBM_RD_SIZE, 1000 >> 3);
+	WREG32(mmDMA_IF_W_N_DOWN_CH0_E2E_PCI_WR_SIZE, 162);
+	WREG32(mmDMA_IF_W_N_DOWN_CH0_E2E_PCI_RD_SIZE, 338);
+
+	WREG32(mmDMA_IF_W_N_DOWN_CH1_E2E_HBM_WR_SIZE, 344 >> 3);
+	WREG32(mmDMA_IF_W_N_DOWN_CH1_E2E_HBM_RD_SIZE, 1000 >> 3);
+	WREG32(mmDMA_IF_W_N_DOWN_CH1_E2E_PCI_WR_SIZE, 162);
+	WREG32(mmDMA_IF_W_N_DOWN_CH1_E2E_PCI_RD_SIZE, 338);
+
+	WREG32(mmDMA_IF_W_S_DOWN_CH0_E2E_HBM_WR_SIZE, 344 >> 3);
+	WREG32(mmDMA_IF_W_S_DOWN_CH0_E2E_HBM_RD_SIZE, 1000 >> 3);
+	WREG32(mmDMA_IF_W_S_DOWN_CH0_E2E_PCI_WR_SIZE, 162);
+	WREG32(mmDMA_IF_W_S_DOWN_CH0_E2E_PCI_RD_SIZE, 338);
+
+	WREG32(mmDMA_IF_W_S_DOWN_CH1_E2E_HBM_WR_SIZE, 344 >> 3);
+	WREG32(mmDMA_IF_W_S_DOWN_CH1_E2E_HBM_RD_SIZE, 1000 >> 3);
+	WREG32(mmDMA_IF_W_S_DOWN_CH1_E2E_PCI_WR_SIZE, 162);
+	WREG32(mmDMA_IF_W_S_DOWN_CH1_E2E_PCI_RD_SIZE, 338);
+
+	WREG32(mmSIF_RTR_CTRL_0_E2E_HBM_EN,
+			1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT);
+	WREG32(mmSIF_RTR_CTRL_0_E2E_PCI_EN,
+			1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT);
+
+	WREG32(mmSIF_RTR_CTRL_1_E2E_HBM_EN,
+			1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT);
+	WREG32(mmSIF_RTR_CTRL_1_E2E_PCI_EN,
+			1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT);
+
+	WREG32(mmSIF_RTR_CTRL_2_E2E_HBM_EN,
+			1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT);
+	WREG32(mmSIF_RTR_CTRL_2_E2E_PCI_EN,
+			1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT);
+
+	WREG32(mmSIF_RTR_CTRL_3_E2E_HBM_EN,
+			1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT);
+	WREG32(mmSIF_RTR_CTRL_3_E2E_PCI_EN,
+			1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT);
+
+	WREG32(mmSIF_RTR_CTRL_4_E2E_HBM_EN,
+			1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT);
+	WREG32(mmSIF_RTR_CTRL_4_E2E_PCI_EN,
+			1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT);
+
+	WREG32(mmSIF_RTR_CTRL_5_E2E_HBM_EN,
+			1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT);
+	WREG32(mmSIF_RTR_CTRL_5_E2E_PCI_EN,
+			1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT);
+
+	WREG32(mmSIF_RTR_CTRL_6_E2E_HBM_EN,
+			1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT);
+	WREG32(mmSIF_RTR_CTRL_6_E2E_PCI_EN,
+			1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT);
+
+	WREG32(mmSIF_RTR_CTRL_7_E2E_HBM_EN,
+			1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT);
+	WREG32(mmSIF_RTR_CTRL_7_E2E_PCI_EN,
+			1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT);
+
+	WREG32(mmNIF_RTR_CTRL_0_E2E_HBM_EN,
+			1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT);
+	WREG32(mmNIF_RTR_CTRL_0_E2E_PCI_EN,
+			1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT);
+
+	WREG32(mmNIF_RTR_CTRL_1_E2E_HBM_EN,
+			1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT);
+	WREG32(mmNIF_RTR_CTRL_1_E2E_PCI_EN,
+			1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT);
+
+	WREG32(mmNIF_RTR_CTRL_2_E2E_HBM_EN,
+			1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT);
+	WREG32(mmNIF_RTR_CTRL_2_E2E_PCI_EN,
+			1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT);
+
+	WREG32(mmNIF_RTR_CTRL_3_E2E_HBM_EN,
+			1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT);
+	WREG32(mmNIF_RTR_CTRL_3_E2E_PCI_EN,
+			1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT);
+
+	WREG32(mmNIF_RTR_CTRL_4_E2E_HBM_EN,
+			1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT);
+	WREG32(mmNIF_RTR_CTRL_4_E2E_PCI_EN,
+			1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT);
+
+	WREG32(mmNIF_RTR_CTRL_5_E2E_HBM_EN,
+			1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT);
+	WREG32(mmNIF_RTR_CTRL_5_E2E_PCI_EN,
+			1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT);
+
+	WREG32(mmNIF_RTR_CTRL_6_E2E_HBM_EN,
+			1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT);
+	WREG32(mmNIF_RTR_CTRL_6_E2E_PCI_EN,
+			1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT);
+
+	WREG32(mmNIF_RTR_CTRL_7_E2E_HBM_EN,
+			1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT);
+	WREG32(mmNIF_RTR_CTRL_7_E2E_PCI_EN,
+			1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT);
+
+	WREG32(mmDMA_IF_E_N_DOWN_CH0_E2E_HBM_EN,
+			1 << DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT);
+	WREG32(mmDMA_IF_E_N_DOWN_CH0_E2E_PCI_EN,
+			1 << DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT);
+
+	WREG32(mmDMA_IF_E_N_DOWN_CH1_E2E_HBM_EN,
+			1 << DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT);
+	WREG32(mmDMA_IF_E_N_DOWN_CH1_E2E_PCI_EN,
+			1 << DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT);
+
+	WREG32(mmDMA_IF_E_S_DOWN_CH0_E2E_HBM_EN,
+			1 << DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT);
+	WREG32(mmDMA_IF_E_S_DOWN_CH0_E2E_PCI_EN,
+			1 << DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT);
+
+	WREG32(mmDMA_IF_E_S_DOWN_CH1_E2E_HBM_EN,
+			1 << DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT);
+	WREG32(mmDMA_IF_E_S_DOWN_CH1_E2E_PCI_EN,
+			1 << DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT);
+
+	WREG32(mmDMA_IF_W_N_DOWN_CH0_E2E_HBM_EN,
+			1 << DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT);
+	WREG32(mmDMA_IF_W_N_DOWN_CH0_E2E_PCI_EN,
+			1 << DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT);
+
+	WREG32(mmDMA_IF_W_N_DOWN_CH1_E2E_HBM_EN,
+			1 << DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT);
+	WREG32(mmDMA_IF_W_N_DOWN_CH1_E2E_PCI_EN,
+			1 << DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT);
+
+	WREG32(mmDMA_IF_W_S_DOWN_CH0_E2E_HBM_EN,
+			1 << DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT);
+	WREG32(mmDMA_IF_W_S_DOWN_CH0_E2E_PCI_EN,
+			1 << DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT);
+
+	WREG32(mmDMA_IF_W_S_DOWN_CH1_E2E_HBM_EN,
+			1 << DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT);
+	WREG32(mmDMA_IF_W_S_DOWN_CH1_E2E_PCI_EN,
+			1 << DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT);
+}
+
+static void gaudi_init_hbm_cred(struct hl_device *hdev)
+{
+	u32 hbm0_wr, hbm1_wr, hbm0_rd, hbm1_rd;
+
+	if (hdev->asic_prop.fw_security_enabled)
+		return;
+
+	if (hdev->asic_prop.fw_bootfit_cpu_boot_dev_sts0 &
+						CPU_BOOT_DEV_STS0_HBM_CRED_EN)
+		return;
+
+	hbm0_wr = 0x33333333;
+	hbm0_rd = 0x77777777;
+	hbm1_wr = 0x55555555;
+	hbm1_rd = 0xDDDDDDDD;
+
+	WREG32(mmDMA_IF_E_N_HBM0_WR_CRED_CNT, hbm0_wr);
+	WREG32(mmDMA_IF_E_N_HBM1_WR_CRED_CNT, hbm1_wr);
+	WREG32(mmDMA_IF_E_N_HBM0_RD_CRED_CNT, hbm0_rd);
+	WREG32(mmDMA_IF_E_N_HBM1_RD_CRED_CNT, hbm1_rd);
+
+	WREG32(mmDMA_IF_E_S_HBM0_WR_CRED_CNT, hbm0_wr);
+	WREG32(mmDMA_IF_E_S_HBM1_WR_CRED_CNT, hbm1_wr);
+	WREG32(mmDMA_IF_E_S_HBM0_RD_CRED_CNT, hbm0_rd);
+	WREG32(mmDMA_IF_E_S_HBM1_RD_CRED_CNT, hbm1_rd);
+
+	WREG32(mmDMA_IF_W_N_HBM0_WR_CRED_CNT, hbm0_wr);
+	WREG32(mmDMA_IF_W_N_HBM1_WR_CRED_CNT, hbm1_wr);
+	WREG32(mmDMA_IF_W_N_HBM0_RD_CRED_CNT, hbm0_rd);
+	WREG32(mmDMA_IF_W_N_HBM1_RD_CRED_CNT, hbm1_rd);
+
+	WREG32(mmDMA_IF_W_S_HBM0_WR_CRED_CNT, hbm0_wr);
+	WREG32(mmDMA_IF_W_S_HBM1_WR_CRED_CNT, hbm1_wr);
+	WREG32(mmDMA_IF_W_S_HBM0_RD_CRED_CNT, hbm0_rd);
+	WREG32(mmDMA_IF_W_S_HBM1_RD_CRED_CNT, hbm1_rd);
+
+	WREG32(mmDMA_IF_E_N_HBM_CRED_EN_0,
+			(1 << DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT) |
+			(1 << DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT));
+	WREG32(mmDMA_IF_E_S_HBM_CRED_EN_0,
+			(1 << DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT) |
+			(1 << DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT));
+	WREG32(mmDMA_IF_W_N_HBM_CRED_EN_0,
+			(1 << DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT) |
+			(1 << DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT));
+	WREG32(mmDMA_IF_W_S_HBM_CRED_EN_0,
+			(1 << DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT) |
+			(1 << DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT));
+
+	WREG32(mmDMA_IF_E_N_HBM_CRED_EN_1,
+			(1 << DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT) |
+			(1 << DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT));
+	WREG32(mmDMA_IF_E_S_HBM_CRED_EN_1,
+			(1 << DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT) |
+			(1 << DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT));
+	WREG32(mmDMA_IF_W_N_HBM_CRED_EN_1,
+			(1 << DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT) |
+			(1 << DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT));
+	WREG32(mmDMA_IF_W_S_HBM_CRED_EN_1,
+			(1 << DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT) |
+			(1 << DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT));
+}
+
+static void gaudi_init_golden_registers(struct hl_device *hdev)
+{
+	u32 tpc_offset;
+	int tpc_id, i;
+
+	gaudi_init_e2e(hdev);
+	gaudi_init_hbm_cred(hdev);
+
+	for (tpc_id = 0, tpc_offset = 0;
+				tpc_id < TPC_NUMBER_OF_ENGINES;
+				tpc_id++, tpc_offset += TPC_CFG_OFFSET) {
+		/* Mask all arithmetic interrupts from TPC */
+		WREG32(mmTPC0_CFG_TPC_INTR_MASK + tpc_offset, 0x8FFE);
+		/* Set 16 cache lines */
+		WREG32_FIELD(TPC0_CFG_MSS_CONFIG, tpc_offset,
+				ICACHE_FETCH_LINE_NUM, 2);
+	}
+
+	/* Make sure 1st 128 bytes in SRAM are 0 for Tensor DMA */
+	for (i = 0 ; i < 128 ; i += 8)
+		writeq(0, hdev->pcie_bar[SRAM_BAR_ID] + i);
+
+	WREG32(mmMME0_CTRL_EUS_ROLLUP_CNT_ADD, 3);
+	WREG32(mmMME1_CTRL_EUS_ROLLUP_CNT_ADD, 3);
+	WREG32(mmMME2_CTRL_EUS_ROLLUP_CNT_ADD, 3);
+	WREG32(mmMME3_CTRL_EUS_ROLLUP_CNT_ADD, 3);
+}
+
+static void gaudi_init_pci_dma_qman(struct hl_device *hdev, int dma_id,
+					int qman_id, dma_addr_t qman_pq_addr)
+{
+	struct cpu_dyn_regs *dyn_regs =
+			&hdev->fw_loader.dynamic_loader.comm_desc.cpu_dyn_regs;
+	u32 mtr_base_en_lo, mtr_base_en_hi, mtr_base_ws_lo, mtr_base_ws_hi;
+	u32 so_base_en_lo, so_base_en_hi, so_base_ws_lo, so_base_ws_hi;
+	u32 q_off, dma_qm_offset;
+	u32 dma_qm_err_cfg, irq_handler_offset;
+
+	dma_qm_offset = dma_id * DMA_QMAN_OFFSET;
+
+	mtr_base_en_lo = lower_32_bits(CFG_BASE +
+				mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0);
+	mtr_base_en_hi = upper_32_bits(CFG_BASE +
+				mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0);
+	so_base_en_lo = lower_32_bits(CFG_BASE +
+				mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0);
+	so_base_en_hi = upper_32_bits(CFG_BASE +
+				mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0);
+	mtr_base_ws_lo = lower_32_bits(CFG_BASE +
+				mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0);
+	mtr_base_ws_hi = upper_32_bits(CFG_BASE +
+				mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0);
+	so_base_ws_lo = lower_32_bits(CFG_BASE +
+				mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0);
+	so_base_ws_hi = upper_32_bits(CFG_BASE +
+				mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0);
+
+	q_off = dma_qm_offset + qman_id * 4;
+
+	WREG32(mmDMA0_QM_PQ_BASE_LO_0 + q_off, lower_32_bits(qman_pq_addr));
+	WREG32(mmDMA0_QM_PQ_BASE_HI_0 + q_off, upper_32_bits(qman_pq_addr));
+
+	WREG32(mmDMA0_QM_PQ_SIZE_0 + q_off, ilog2(HL_QUEUE_LENGTH));
+	WREG32(mmDMA0_QM_PQ_PI_0 + q_off, 0);
+	WREG32(mmDMA0_QM_PQ_CI_0 + q_off, 0);
+
+	WREG32(mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off, QMAN_LDMA_SIZE_OFFSET);
+	WREG32(mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
+							QMAN_LDMA_SRC_OFFSET);
+	WREG32(mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
+							QMAN_LDMA_DST_OFFSET);
+
+	WREG32(mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 + q_off, mtr_base_en_lo);
+	WREG32(mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 + q_off, mtr_base_en_hi);
+	WREG32(mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 + q_off, so_base_en_lo);
+	WREG32(mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 + q_off, so_base_en_hi);
+	WREG32(mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_0 + q_off, mtr_base_ws_lo);
+	WREG32(mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_0 + q_off, mtr_base_ws_hi);
+	WREG32(mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_0 + q_off, so_base_ws_lo);
+	WREG32(mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_0 + q_off, so_base_ws_hi);
+
+	WREG32(mmDMA0_QM_CP_BARRIER_CFG_0 + q_off, 0x100);
+
+	/* The following configuration is needed only once per QMAN */
+	if (qman_id == 0) {
+		irq_handler_offset = hdev->asic_prop.gic_interrupts_enable ?
+				mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR :
+				le32_to_cpu(dyn_regs->gic_dma_qm_irq_ctrl);
+
+		/* Configure RAZWI IRQ */
+		dma_qm_err_cfg = PCI_DMA_QMAN_GLBL_ERR_CFG_MSG_EN_MASK;
+		if (hdev->stop_on_err)
+			dma_qm_err_cfg |=
+				PCI_DMA_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK;
+
+		WREG32(mmDMA0_QM_GLBL_ERR_CFG + dma_qm_offset, dma_qm_err_cfg);
+
+		WREG32(mmDMA0_QM_GLBL_ERR_ADDR_LO + dma_qm_offset,
+			lower_32_bits(CFG_BASE + irq_handler_offset));
+		WREG32(mmDMA0_QM_GLBL_ERR_ADDR_HI + dma_qm_offset,
+			upper_32_bits(CFG_BASE + irq_handler_offset));
+
+		WREG32(mmDMA0_QM_GLBL_ERR_WDATA + dma_qm_offset,
+			gaudi_irq_map_table[GAUDI_EVENT_DMA0_QM].cpu_id +
+									dma_id);
+
+		WREG32(mmDMA0_QM_ARB_ERR_MSG_EN + dma_qm_offset,
+				QM_ARB_ERR_MSG_EN_MASK);
+
+		/* Set timeout to maximum */
+		WREG32(mmDMA0_QM_ARB_SLV_CHOISE_WDT + dma_qm_offset, GAUDI_ARB_WDT_TIMEOUT);
+
+		WREG32(mmDMA0_QM_GLBL_PROT + dma_qm_offset,
+				QMAN_EXTERNAL_MAKE_TRUSTED);
+
+		WREG32(mmDMA0_QM_GLBL_CFG1 + dma_qm_offset, 0);
+	}
+}
+
+static void gaudi_init_dma_core(struct hl_device *hdev, int dma_id)
+{
+	struct cpu_dyn_regs *dyn_regs =
+			&hdev->fw_loader.dynamic_loader.comm_desc.cpu_dyn_regs;
+	u32 dma_err_cfg = 1 << DMA0_CORE_ERR_CFG_ERR_MSG_EN_SHIFT;
+	u32 dma_offset = dma_id * DMA_CORE_OFFSET;
+	u32 irq_handler_offset;
+
+	/* Set to maximum possible according to physical size */
+	WREG32(mmDMA0_CORE_RD_MAX_OUTSTAND + dma_offset, 0);
+	WREG32(mmDMA0_CORE_RD_MAX_SIZE + dma_offset, 0);
+
+	/* WA for H/W bug H3-2116 */
+	WREG32(mmDMA0_CORE_LBW_MAX_OUTSTAND + dma_offset, 15);
+
+	/* STOP_ON bit implies no completion to operation in case of RAZWI */
+	if (hdev->stop_on_err)
+		dma_err_cfg |= 1 << DMA0_CORE_ERR_CFG_STOP_ON_ERR_SHIFT;
+
+	WREG32(mmDMA0_CORE_ERR_CFG + dma_offset, dma_err_cfg);
+
+	irq_handler_offset = hdev->asic_prop.gic_interrupts_enable ?
+			mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR :
+			le32_to_cpu(dyn_regs->gic_dma_core_irq_ctrl);
+
+	WREG32(mmDMA0_CORE_ERRMSG_ADDR_LO + dma_offset,
+		lower_32_bits(CFG_BASE + irq_handler_offset));
+	WREG32(mmDMA0_CORE_ERRMSG_ADDR_HI + dma_offset,
+		upper_32_bits(CFG_BASE + irq_handler_offset));
+
+	WREG32(mmDMA0_CORE_ERRMSG_WDATA + dma_offset,
+		gaudi_irq_map_table[GAUDI_EVENT_DMA0_CORE].cpu_id + dma_id);
+	WREG32(mmDMA0_CORE_PROT + dma_offset,
+			1 << DMA0_CORE_PROT_ERR_VAL_SHIFT);
+	/* If the channel is secured, it should be in MMU bypass mode */
+	WREG32(mmDMA0_CORE_SECURE_PROPS + dma_offset,
+			1 << DMA0_CORE_SECURE_PROPS_MMBP_SHIFT);
+	WREG32(mmDMA0_CORE_CFG_0 + dma_offset, 1 << DMA0_CORE_CFG_0_EN_SHIFT);
+}
+
+static void gaudi_enable_qman(struct hl_device *hdev, int dma_id,
+				u32 enable_mask)
+{
+	u32 dma_qm_offset = dma_id * DMA_QMAN_OFFSET;
+
+	WREG32(mmDMA0_QM_GLBL_CFG0 + dma_qm_offset, enable_mask);
+}
+
+static void gaudi_init_pci_dma_qmans(struct hl_device *hdev)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+	struct hl_hw_queue *q;
+	int i, j, dma_id, cpu_skip, nic_skip, cq_id = 0, q_idx, msi_vec = 0;
+
+	if (gaudi->hw_cap_initialized & HW_CAP_PCI_DMA)
+		return;
+
+	for (i = 0 ; i < PCI_DMA_NUMBER_OF_CHNLS ; i++) {
+		dma_id = gaudi_dma_assignment[i];
+		/*
+		 * For queues after the CPU Q need to add 1 to get the correct
+		 * queue. In addition, need to add the CPU EQ and NIC IRQs in
+		 * order to get the correct MSI register.
+		 */
+		if (dma_id > 1) {
+			cpu_skip = 1;
+			nic_skip = NIC_NUMBER_OF_ENGINES;
+		} else {
+			cpu_skip = 0;
+			nic_skip = 0;
+		}
+
+		for (j = 0 ; j < QMAN_STREAMS ; j++) {
+			q_idx = 4 * dma_id + j + cpu_skip;
+			q = &hdev->kernel_queues[q_idx];
+			q->cq_id = cq_id++;
+			q->msi_vec = nic_skip + cpu_skip + msi_vec++;
+			gaudi_init_pci_dma_qman(hdev, dma_id, j,
+						q->bus_address);
+		}
+
+		gaudi_init_dma_core(hdev, dma_id);
+
+		gaudi_enable_qman(hdev, dma_id, PCI_DMA_QMAN_ENABLE);
+	}
+
+	gaudi->hw_cap_initialized |= HW_CAP_PCI_DMA;
+}
+
+static void gaudi_init_hbm_dma_qman(struct hl_device *hdev, int dma_id,
+					int qman_id, u64 qman_base_addr)
+{
+	struct cpu_dyn_regs *dyn_regs =
+			&hdev->fw_loader.dynamic_loader.comm_desc.cpu_dyn_regs;
+	u32 mtr_base_en_lo, mtr_base_en_hi, mtr_base_ws_lo, mtr_base_ws_hi;
+	u32 so_base_en_lo, so_base_en_hi, so_base_ws_lo, so_base_ws_hi;
+	u32 dma_qm_err_cfg, irq_handler_offset;
+	u32 q_off, dma_qm_offset;
+
+	dma_qm_offset = dma_id * DMA_QMAN_OFFSET;
+
+	mtr_base_en_lo = lower_32_bits(CFG_BASE +
+			mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0);
+	mtr_base_en_hi = upper_32_bits(CFG_BASE +
+				mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0);
+	so_base_en_lo = lower_32_bits(CFG_BASE +
+				mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0);
+	so_base_en_hi = upper_32_bits(CFG_BASE +
+				mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0);
+	mtr_base_ws_lo = lower_32_bits(CFG_BASE +
+				mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0);
+	mtr_base_ws_hi = upper_32_bits(CFG_BASE +
+				mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0);
+	so_base_ws_lo = lower_32_bits(CFG_BASE +
+				mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0);
+	so_base_ws_hi = upper_32_bits(CFG_BASE +
+				mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0);
+
+	q_off = dma_qm_offset + qman_id * 4;
+
+	if (qman_id < 4) {
+		WREG32(mmDMA0_QM_PQ_BASE_LO_0 + q_off,
+					lower_32_bits(qman_base_addr));
+		WREG32(mmDMA0_QM_PQ_BASE_HI_0 + q_off,
+					upper_32_bits(qman_base_addr));
+
+		WREG32(mmDMA0_QM_PQ_SIZE_0 + q_off, ilog2(HBM_DMA_QMAN_LENGTH));
+		WREG32(mmDMA0_QM_PQ_PI_0 + q_off, 0);
+		WREG32(mmDMA0_QM_PQ_CI_0 + q_off, 0);
+
+		WREG32(mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,
+							QMAN_CPDMA_SIZE_OFFSET);
+		WREG32(mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
+							QMAN_CPDMA_SRC_OFFSET);
+		WREG32(mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
+							QMAN_CPDMA_DST_OFFSET);
+	} else {
+		irq_handler_offset = hdev->asic_prop.gic_interrupts_enable ?
+				mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR :
+				le32_to_cpu(dyn_regs->gic_dma_qm_irq_ctrl);
+
+		WREG32(mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,
+							QMAN_LDMA_SIZE_OFFSET);
+		WREG32(mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
+							QMAN_LDMA_SRC_OFFSET);
+		WREG32(mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
+							QMAN_LDMA_DST_OFFSET);
+
+		/* Configure RAZWI IRQ */
+		dma_qm_err_cfg = HBM_DMA_QMAN_GLBL_ERR_CFG_MSG_EN_MASK;
+		if (hdev->stop_on_err)
+			dma_qm_err_cfg |=
+				HBM_DMA_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK;
+
+		WREG32(mmDMA0_QM_GLBL_ERR_CFG + dma_qm_offset, dma_qm_err_cfg);
+
+		WREG32(mmDMA0_QM_GLBL_ERR_ADDR_LO + dma_qm_offset,
+			lower_32_bits(CFG_BASE + irq_handler_offset));
+		WREG32(mmDMA0_QM_GLBL_ERR_ADDR_HI + dma_qm_offset,
+			upper_32_bits(CFG_BASE + irq_handler_offset));
+
+		WREG32(mmDMA0_QM_GLBL_ERR_WDATA + dma_qm_offset,
+			gaudi_irq_map_table[GAUDI_EVENT_DMA0_QM].cpu_id +
+									dma_id);
+
+		WREG32(mmDMA0_QM_ARB_ERR_MSG_EN + dma_qm_offset,
+				QM_ARB_ERR_MSG_EN_MASK);
+
+		/* Set timeout to maximum */
+		WREG32(mmDMA0_QM_ARB_SLV_CHOISE_WDT + dma_qm_offset, GAUDI_ARB_WDT_TIMEOUT);
+
+		WREG32(mmDMA0_QM_GLBL_CFG1 + dma_qm_offset, 0);
+		WREG32(mmDMA0_QM_GLBL_PROT + dma_qm_offset,
+				QMAN_INTERNAL_MAKE_TRUSTED);
+	}
+
+	WREG32(mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 + q_off, mtr_base_en_lo);
+	WREG32(mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 + q_off, mtr_base_en_hi);
+	WREG32(mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 + q_off, so_base_en_lo);
+	WREG32(mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 + q_off, so_base_en_hi);
+
+	/* Configure DMA5 CP_MSG_BASE 2/3 for sync stream collective */
+	if (gaudi_dma_assignment[dma_id] == GAUDI_ENGINE_ID_DMA_5) {
+		WREG32(mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_0 + q_off,
+				mtr_base_ws_lo);
+		WREG32(mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_0 + q_off,
+				mtr_base_ws_hi);
+		WREG32(mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_0 + q_off,
+				so_base_ws_lo);
+		WREG32(mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_0 + q_off,
+				so_base_ws_hi);
+	}
+}
+
+static void gaudi_init_hbm_dma_qmans(struct hl_device *hdev)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+	struct gaudi_internal_qman_info *q;
+	u64 qman_base_addr;
+	int i, j, dma_id, internal_q_index;
+
+	if (gaudi->hw_cap_initialized & HW_CAP_HBM_DMA)
+		return;
+
+	for (i = 0 ; i < HBM_DMA_NUMBER_OF_CHNLS ; i++) {
+		dma_id = gaudi_dma_assignment[GAUDI_HBM_DMA_1 + i];
+
+		for (j = 0 ; j < QMAN_STREAMS ; j++) {
+			 /*
+			  * Add the CPU queue in order to get the correct queue
+			  * number as all internal queue are placed after it
+			  */
+			internal_q_index = dma_id * QMAN_STREAMS + j + 1;
+
+			q = &gaudi->internal_qmans[internal_q_index];
+			qman_base_addr = (u64) q->pq_dma_addr;
+			gaudi_init_hbm_dma_qman(hdev, dma_id, j,
+						qman_base_addr);
+		}
+
+		/* Initializing lower CP for HBM DMA QMAN */
+		gaudi_init_hbm_dma_qman(hdev, dma_id, 4, 0);
+
+		gaudi_init_dma_core(hdev, dma_id);
+
+		gaudi_enable_qman(hdev, dma_id, HBM_DMA_QMAN_ENABLE);
+	}
+
+	gaudi->hw_cap_initialized |= HW_CAP_HBM_DMA;
+}
+
+static void gaudi_init_mme_qman(struct hl_device *hdev, u32 mme_offset,
+					int qman_id, u64 qman_base_addr)
+{
+	struct cpu_dyn_regs *dyn_regs =
+			&hdev->fw_loader.dynamic_loader.comm_desc.cpu_dyn_regs;
+	u32 mtr_base_lo, mtr_base_hi;
+	u32 so_base_lo, so_base_hi;
+	u32 irq_handler_offset;
+	u32 q_off, mme_id;
+	u32 mme_qm_err_cfg;
+
+	mtr_base_lo = lower_32_bits(CFG_BASE +
+				mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0);
+	mtr_base_hi = upper_32_bits(CFG_BASE +
+				mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0);
+	so_base_lo = lower_32_bits(CFG_BASE +
+				mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0);
+	so_base_hi = upper_32_bits(CFG_BASE +
+				mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0);
+
+	q_off = mme_offset + qman_id * 4;
+
+	if (qman_id < 4) {
+		WREG32(mmMME0_QM_PQ_BASE_LO_0 + q_off,
+					lower_32_bits(qman_base_addr));
+		WREG32(mmMME0_QM_PQ_BASE_HI_0 + q_off,
+					upper_32_bits(qman_base_addr));
+
+		WREG32(mmMME0_QM_PQ_SIZE_0 + q_off, ilog2(MME_QMAN_LENGTH));
+		WREG32(mmMME0_QM_PQ_PI_0 + q_off, 0);
+		WREG32(mmMME0_QM_PQ_CI_0 + q_off, 0);
+
+		WREG32(mmMME0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,
+							QMAN_CPDMA_SIZE_OFFSET);
+		WREG32(mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
+							QMAN_CPDMA_SRC_OFFSET);
+		WREG32(mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
+							QMAN_CPDMA_DST_OFFSET);
+	} else {
+		irq_handler_offset = hdev->asic_prop.gic_interrupts_enable ?
+				mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR :
+				le32_to_cpu(dyn_regs->gic_mme_qm_irq_ctrl);
+
+		WREG32(mmMME0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,
+							QMAN_LDMA_SIZE_OFFSET);
+		WREG32(mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
+							QMAN_LDMA_SRC_OFFSET);
+		WREG32(mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
+							QMAN_LDMA_DST_OFFSET);
+
+		/* Configure RAZWI IRQ */
+		mme_id = mme_offset /
+				(mmMME1_QM_GLBL_CFG0 - mmMME0_QM_GLBL_CFG0) / 2;
+
+		mme_qm_err_cfg = MME_QMAN_GLBL_ERR_CFG_MSG_EN_MASK;
+		if (hdev->stop_on_err)
+			mme_qm_err_cfg |=
+				MME_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK;
+
+		WREG32(mmMME0_QM_GLBL_ERR_CFG + mme_offset, mme_qm_err_cfg);
+
+		WREG32(mmMME0_QM_GLBL_ERR_ADDR_LO + mme_offset,
+			lower_32_bits(CFG_BASE + irq_handler_offset));
+		WREG32(mmMME0_QM_GLBL_ERR_ADDR_HI + mme_offset,
+			upper_32_bits(CFG_BASE + irq_handler_offset));
+
+		WREG32(mmMME0_QM_GLBL_ERR_WDATA + mme_offset,
+			gaudi_irq_map_table[GAUDI_EVENT_MME0_QM].cpu_id +
+									mme_id);
+
+		WREG32(mmMME0_QM_ARB_ERR_MSG_EN + mme_offset,
+				QM_ARB_ERR_MSG_EN_MASK);
+
+		/* Set timeout to maximum */
+		WREG32(mmMME0_QM_ARB_SLV_CHOISE_WDT + mme_offset, GAUDI_ARB_WDT_TIMEOUT);
+
+		WREG32(mmMME0_QM_GLBL_CFG1 + mme_offset, 0);
+		WREG32(mmMME0_QM_GLBL_PROT + mme_offset,
+				QMAN_INTERNAL_MAKE_TRUSTED);
+	}
+
+	WREG32(mmMME0_QM_CP_MSG_BASE0_ADDR_LO_0 + q_off, mtr_base_lo);
+	WREG32(mmMME0_QM_CP_MSG_BASE0_ADDR_HI_0 + q_off, mtr_base_hi);
+	WREG32(mmMME0_QM_CP_MSG_BASE1_ADDR_LO_0 + q_off, so_base_lo);
+	WREG32(mmMME0_QM_CP_MSG_BASE1_ADDR_HI_0 + q_off, so_base_hi);
+}
+
+static void gaudi_init_mme_qmans(struct hl_device *hdev)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+	struct gaudi_internal_qman_info *q;
+	u64 qman_base_addr;
+	u32 mme_offset;
+	int i, internal_q_index;
+
+	if (gaudi->hw_cap_initialized & HW_CAP_MME)
+		return;
+
+	/*
+	 * map GAUDI_QUEUE_ID_MME_0_X to the N_W_MME (mmMME2_QM_BASE)
+	 * and GAUDI_QUEUE_ID_MME_1_X to the S_W_MME (mmMME0_QM_BASE)
+	 */
+
+	mme_offset = mmMME2_QM_GLBL_CFG0 - mmMME0_QM_GLBL_CFG0;
+
+	for (i = 0 ; i < MME_NUMBER_OF_QMANS ; i++) {
+		internal_q_index = GAUDI_QUEUE_ID_MME_0_0 + i;
+		q = &gaudi->internal_qmans[internal_q_index];
+		qman_base_addr = (u64) q->pq_dma_addr;
+		gaudi_init_mme_qman(hdev, mme_offset, (i & 0x3),
+					qman_base_addr);
+		if (i == 3)
+			mme_offset = 0;
+	}
+
+	/* Initializing lower CP for MME QMANs */
+	mme_offset = mmMME2_QM_GLBL_CFG0 - mmMME0_QM_GLBL_CFG0;
+	gaudi_init_mme_qman(hdev, mme_offset, 4, 0);
+	gaudi_init_mme_qman(hdev, 0, 4, 0);
+
+	WREG32(mmMME2_QM_GLBL_CFG0, QMAN_MME_ENABLE);
+	WREG32(mmMME0_QM_GLBL_CFG0, QMAN_MME_ENABLE);
+
+	gaudi->hw_cap_initialized |= HW_CAP_MME;
+}
+
+static void gaudi_init_tpc_qman(struct hl_device *hdev, u32 tpc_offset,
+				int qman_id, u64 qman_base_addr)
+{
+	struct cpu_dyn_regs *dyn_regs =
+			&hdev->fw_loader.dynamic_loader.comm_desc.cpu_dyn_regs;
+	u32 mtr_base_en_lo, mtr_base_en_hi, mtr_base_ws_lo, mtr_base_ws_hi;
+	u32 so_base_en_lo, so_base_en_hi, so_base_ws_lo, so_base_ws_hi;
+	u32 tpc_qm_err_cfg, irq_handler_offset;
+	u32 q_off, tpc_id;
+
+	mtr_base_en_lo = lower_32_bits(CFG_BASE +
+			mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0);
+	mtr_base_en_hi = upper_32_bits(CFG_BASE +
+				mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0);
+	so_base_en_lo = lower_32_bits(CFG_BASE +
+				mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0);
+	so_base_en_hi = upper_32_bits(CFG_BASE +
+				mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0);
+	mtr_base_ws_lo = lower_32_bits(CFG_BASE +
+				mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0);
+	mtr_base_ws_hi = upper_32_bits(CFG_BASE +
+				mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0);
+	so_base_ws_lo = lower_32_bits(CFG_BASE +
+				mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0);
+	so_base_ws_hi = upper_32_bits(CFG_BASE +
+				mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0);
+
+	q_off = tpc_offset + qman_id * 4;
+
+	tpc_id = tpc_offset /
+			(mmTPC1_QM_GLBL_CFG0 - mmTPC0_QM_GLBL_CFG0);
+
+	if (qman_id < 4) {
+		WREG32(mmTPC0_QM_PQ_BASE_LO_0 + q_off,
+					lower_32_bits(qman_base_addr));
+		WREG32(mmTPC0_QM_PQ_BASE_HI_0 + q_off,
+					upper_32_bits(qman_base_addr));
+
+		WREG32(mmTPC0_QM_PQ_SIZE_0 + q_off, ilog2(TPC_QMAN_LENGTH));
+		WREG32(mmTPC0_QM_PQ_PI_0 + q_off, 0);
+		WREG32(mmTPC0_QM_PQ_CI_0 + q_off, 0);
+
+		WREG32(mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,
+							QMAN_CPDMA_SIZE_OFFSET);
+		WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
+							QMAN_CPDMA_SRC_OFFSET);
+		WREG32(mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
+							QMAN_CPDMA_DST_OFFSET);
+	} else {
+		irq_handler_offset = hdev->asic_prop.gic_interrupts_enable ?
+				mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR :
+				le32_to_cpu(dyn_regs->gic_tpc_qm_irq_ctrl);
+
+		WREG32(mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,
+							QMAN_LDMA_SIZE_OFFSET);
+		WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
+							QMAN_LDMA_SRC_OFFSET);
+		WREG32(mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
+							QMAN_LDMA_DST_OFFSET);
+
+		/* Configure RAZWI IRQ */
+		tpc_qm_err_cfg = TPC_QMAN_GLBL_ERR_CFG_MSG_EN_MASK;
+		if (hdev->stop_on_err)
+			tpc_qm_err_cfg |=
+				TPC_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK;
+
+		WREG32(mmTPC0_QM_GLBL_ERR_CFG + tpc_offset, tpc_qm_err_cfg);
+
+		WREG32(mmTPC0_QM_GLBL_ERR_ADDR_LO + tpc_offset,
+			lower_32_bits(CFG_BASE + irq_handler_offset));
+		WREG32(mmTPC0_QM_GLBL_ERR_ADDR_HI + tpc_offset,
+			upper_32_bits(CFG_BASE + irq_handler_offset));
+
+		WREG32(mmTPC0_QM_GLBL_ERR_WDATA + tpc_offset,
+			gaudi_irq_map_table[GAUDI_EVENT_TPC0_QM].cpu_id +
+									tpc_id);
+
+		WREG32(mmTPC0_QM_ARB_ERR_MSG_EN + tpc_offset,
+				QM_ARB_ERR_MSG_EN_MASK);
+
+		/* Set timeout to maximum */
+		WREG32(mmTPC0_QM_ARB_SLV_CHOISE_WDT + tpc_offset, GAUDI_ARB_WDT_TIMEOUT);
+
+		WREG32(mmTPC0_QM_GLBL_CFG1 + tpc_offset, 0);
+		WREG32(mmTPC0_QM_GLBL_PROT + tpc_offset,
+				QMAN_INTERNAL_MAKE_TRUSTED);
+	}
+
+	WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_0 + q_off, mtr_base_en_lo);
+	WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_0 + q_off, mtr_base_en_hi);
+	WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_0 + q_off, so_base_en_lo);
+	WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_0 + q_off, so_base_en_hi);
+
+	/* Configure TPC7 CP_MSG_BASE 2/3 for sync stream collective */
+	if (tpc_id == 6) {
+		WREG32(mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_0 + q_off,
+				mtr_base_ws_lo);
+		WREG32(mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_0 + q_off,
+				mtr_base_ws_hi);
+		WREG32(mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_0 + q_off,
+				so_base_ws_lo);
+		WREG32(mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_0 + q_off,
+				so_base_ws_hi);
+	}
+}
+
+static void gaudi_init_tpc_qmans(struct hl_device *hdev)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+	struct gaudi_internal_qman_info *q;
+	u64 qman_base_addr;
+	u32 so_base_hi, tpc_offset = 0;
+	u32 tpc_delta = mmTPC1_CFG_SM_BASE_ADDRESS_HIGH -
+			mmTPC0_CFG_SM_BASE_ADDRESS_HIGH;
+	int i, tpc_id, internal_q_index;
+
+	if (gaudi->hw_cap_initialized & HW_CAP_TPC_MASK)
+		return;
+
+	so_base_hi = upper_32_bits(CFG_BASE +
+				mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0);
+
+	for (tpc_id = 0 ; tpc_id < TPC_NUMBER_OF_ENGINES ; tpc_id++) {
+		for (i = 0 ; i < QMAN_STREAMS ; i++) {
+			internal_q_index = GAUDI_QUEUE_ID_TPC_0_0 +
+						tpc_id * QMAN_STREAMS + i;
+			q = &gaudi->internal_qmans[internal_q_index];
+			qman_base_addr = (u64) q->pq_dma_addr;
+			gaudi_init_tpc_qman(hdev, tpc_offset, i,
+						qman_base_addr);
+
+			if (i == 3) {
+				/* Initializing lower CP for TPC QMAN */
+				gaudi_init_tpc_qman(hdev, tpc_offset, 4, 0);
+
+				/* Enable the QMAN and TPC channel */
+				WREG32(mmTPC0_QM_GLBL_CFG0 + tpc_offset,
+						QMAN_TPC_ENABLE);
+			}
+		}
+
+		WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_HIGH + tpc_id * tpc_delta,
+				so_base_hi);
+
+		tpc_offset += mmTPC1_QM_GLBL_CFG0 - mmTPC0_QM_GLBL_CFG0;
+
+		gaudi->hw_cap_initialized |=
+				FIELD_PREP(HW_CAP_TPC_MASK, 1 << tpc_id);
+	}
+}
+
+static void gaudi_init_nic_qman(struct hl_device *hdev, u32 nic_offset,
+				int qman_id, u64 qman_base_addr, int nic_id)
+{
+	struct cpu_dyn_regs *dyn_regs =
+			&hdev->fw_loader.dynamic_loader.comm_desc.cpu_dyn_regs;
+	u32 mtr_base_en_lo, mtr_base_en_hi, mtr_base_ws_lo, mtr_base_ws_hi;
+	u32 so_base_en_lo, so_base_en_hi, so_base_ws_lo, so_base_ws_hi;
+	u32 nic_qm_err_cfg, irq_handler_offset;
+	u32 q_off;
+
+	mtr_base_en_lo = lower_32_bits((CFG_BASE & U32_MAX) +
+			mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0);
+	mtr_base_en_hi = upper_32_bits(CFG_BASE +
+				mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0);
+	so_base_en_lo = lower_32_bits((CFG_BASE & U32_MAX) +
+				mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0);
+	so_base_en_hi = upper_32_bits(CFG_BASE +
+				mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0);
+	mtr_base_ws_lo = lower_32_bits((CFG_BASE & U32_MAX) +
+				mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0);
+	mtr_base_ws_hi = upper_32_bits(CFG_BASE +
+				mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0);
+	so_base_ws_lo = lower_32_bits((CFG_BASE & U32_MAX) +
+				mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0);
+	so_base_ws_hi = upper_32_bits(CFG_BASE +
+				mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0);
+
+	q_off = nic_offset + qman_id * 4;
+
+	WREG32(mmNIC0_QM0_PQ_BASE_LO_0 + q_off, lower_32_bits(qman_base_addr));
+	WREG32(mmNIC0_QM0_PQ_BASE_HI_0 + q_off, upper_32_bits(qman_base_addr));
+
+	WREG32(mmNIC0_QM0_PQ_SIZE_0 + q_off, ilog2(NIC_QMAN_LENGTH));
+	WREG32(mmNIC0_QM0_PQ_PI_0 + q_off, 0);
+	WREG32(mmNIC0_QM0_PQ_CI_0 + q_off, 0);
+
+	WREG32(mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET_0 + q_off,
+							QMAN_LDMA_SIZE_OFFSET);
+	WREG32(mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
+							QMAN_LDMA_SRC_OFFSET);
+	WREG32(mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
+							QMAN_LDMA_DST_OFFSET);
+
+	WREG32(mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_0 + q_off, mtr_base_en_lo);
+	WREG32(mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_0 + q_off, mtr_base_en_hi);
+	WREG32(mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_0 + q_off, so_base_en_lo);
+	WREG32(mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_0 + q_off, so_base_en_hi);
+
+	/* Configure NIC CP_MSG_BASE 2/3 for sync stream collective */
+	WREG32(mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_0 + q_off, mtr_base_ws_lo);
+	WREG32(mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_0 + q_off, mtr_base_ws_hi);
+	WREG32(mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_0 + q_off, so_base_ws_lo);
+	WREG32(mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_0 + q_off, so_base_ws_hi);
+
+	if (qman_id == 0) {
+		irq_handler_offset = hdev->asic_prop.gic_interrupts_enable ?
+				mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR :
+				le32_to_cpu(dyn_regs->gic_nic_qm_irq_ctrl);
+
+		/* Configure RAZWI IRQ */
+		nic_qm_err_cfg = NIC_QMAN_GLBL_ERR_CFG_MSG_EN_MASK;
+		if (hdev->stop_on_err)
+			nic_qm_err_cfg |=
+				NIC_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK;
+
+		WREG32(mmNIC0_QM0_GLBL_ERR_CFG + nic_offset, nic_qm_err_cfg);
+
+		WREG32(mmNIC0_QM0_GLBL_ERR_ADDR_LO + nic_offset,
+			lower_32_bits(CFG_BASE + irq_handler_offset));
+		WREG32(mmNIC0_QM0_GLBL_ERR_ADDR_HI + nic_offset,
+			upper_32_bits(CFG_BASE + irq_handler_offset));
+
+		WREG32(mmNIC0_QM0_GLBL_ERR_WDATA + nic_offset,
+			gaudi_irq_map_table[GAUDI_EVENT_NIC0_QM0].cpu_id +
+									nic_id);
+
+		WREG32(mmNIC0_QM0_ARB_ERR_MSG_EN + nic_offset,
+				QM_ARB_ERR_MSG_EN_MASK);
+
+		/* Set timeout to maximum */
+		WREG32(mmNIC0_QM0_ARB_SLV_CHOISE_WDT + nic_offset, GAUDI_ARB_WDT_TIMEOUT);
+
+		WREG32(mmNIC0_QM0_GLBL_CFG1 + nic_offset, 0);
+		WREG32(mmNIC0_QM0_GLBL_PROT + nic_offset,
+				QMAN_INTERNAL_MAKE_TRUSTED);
+	}
+}
+
+static void gaudi_init_nic_qmans(struct hl_device *hdev)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+	struct gaudi_internal_qman_info *q;
+	u64 qman_base_addr;
+	u32 nic_offset = 0;
+	u32 nic_delta_between_qmans =
+			mmNIC0_QM1_GLBL_CFG0 - mmNIC0_QM0_GLBL_CFG0;
+	u32 nic_delta_between_nics =
+			mmNIC1_QM0_GLBL_CFG0 - mmNIC0_QM0_GLBL_CFG0;
+	int i, nic_id, internal_q_index;
+
+	if (!hdev->nic_ports_mask)
+		return;
+
+	if (gaudi->hw_cap_initialized & HW_CAP_NIC_MASK)
+		return;
+
+	dev_dbg(hdev->dev, "Initializing NIC QMANs\n");
+
+	for (nic_id = 0 ; nic_id < NIC_NUMBER_OF_ENGINES ; nic_id++) {
+		if (!(hdev->nic_ports_mask & (1 << nic_id))) {
+			nic_offset += nic_delta_between_qmans;
+			if (nic_id & 1) {
+				nic_offset -= (nic_delta_between_qmans * 2);
+				nic_offset += nic_delta_between_nics;
+			}
+			continue;
+		}
+
+		for (i = 0 ; i < QMAN_STREAMS ; i++) {
+			internal_q_index = GAUDI_QUEUE_ID_NIC_0_0 +
+						nic_id * QMAN_STREAMS + i;
+			q = &gaudi->internal_qmans[internal_q_index];
+			qman_base_addr = (u64) q->pq_dma_addr;
+			gaudi_init_nic_qman(hdev, nic_offset, (i & 0x3),
+						qman_base_addr, nic_id);
+		}
+
+		/* Enable the QMAN */
+		WREG32(mmNIC0_QM0_GLBL_CFG0 + nic_offset, NIC_QMAN_ENABLE);
+
+		nic_offset += nic_delta_between_qmans;
+		if (nic_id & 1) {
+			nic_offset -= (nic_delta_between_qmans * 2);
+			nic_offset += nic_delta_between_nics;
+		}
+
+		gaudi->hw_cap_initialized |= 1 << (HW_CAP_NIC_SHIFT + nic_id);
+	}
+}
+
+static void gaudi_disable_pci_dma_qmans(struct hl_device *hdev)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+
+	if (!(gaudi->hw_cap_initialized & HW_CAP_PCI_DMA))
+		return;
+
+	WREG32(mmDMA0_QM_GLBL_CFG0, 0);
+	WREG32(mmDMA1_QM_GLBL_CFG0, 0);
+	WREG32(mmDMA5_QM_GLBL_CFG0, 0);
+}
+
+static void gaudi_disable_hbm_dma_qmans(struct hl_device *hdev)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+
+	if (!(gaudi->hw_cap_initialized & HW_CAP_HBM_DMA))
+		return;
+
+	WREG32(mmDMA2_QM_GLBL_CFG0, 0);
+	WREG32(mmDMA3_QM_GLBL_CFG0, 0);
+	WREG32(mmDMA4_QM_GLBL_CFG0, 0);
+	WREG32(mmDMA6_QM_GLBL_CFG0, 0);
+	WREG32(mmDMA7_QM_GLBL_CFG0, 0);
+}
+
+static void gaudi_disable_mme_qmans(struct hl_device *hdev)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+
+	if (!(gaudi->hw_cap_initialized & HW_CAP_MME))
+		return;
+
+	WREG32(mmMME2_QM_GLBL_CFG0, 0);
+	WREG32(mmMME0_QM_GLBL_CFG0, 0);
+}
+
+static void gaudi_disable_tpc_qmans(struct hl_device *hdev)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+	u32 tpc_offset = 0;
+	int tpc_id;
+
+	if (!(gaudi->hw_cap_initialized & HW_CAP_TPC_MASK))
+		return;
+
+	for (tpc_id = 0 ; tpc_id < TPC_NUMBER_OF_ENGINES ; tpc_id++) {
+		WREG32(mmTPC0_QM_GLBL_CFG0 + tpc_offset, 0);
+		tpc_offset += mmTPC1_QM_GLBL_CFG0 - mmTPC0_QM_GLBL_CFG0;
+	}
+}
+
+static void gaudi_disable_nic_qmans(struct hl_device *hdev)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+	u32 nic_mask, nic_offset = 0;
+	u32 nic_delta_between_qmans =
+			mmNIC0_QM1_GLBL_CFG0 - mmNIC0_QM0_GLBL_CFG0;
+	u32 nic_delta_between_nics =
+			mmNIC1_QM0_GLBL_CFG0 - mmNIC0_QM0_GLBL_CFG0;
+	int nic_id;
+
+	for (nic_id = 0 ; nic_id < NIC_NUMBER_OF_ENGINES ; nic_id++) {
+		nic_mask = 1 << (HW_CAP_NIC_SHIFT + nic_id);
+
+		if (gaudi->hw_cap_initialized & nic_mask)
+			WREG32(mmNIC0_QM0_GLBL_CFG0 + nic_offset, 0);
+
+		nic_offset += nic_delta_between_qmans;
+		if (nic_id & 1) {
+			nic_offset -= (nic_delta_between_qmans * 2);
+			nic_offset += nic_delta_between_nics;
+		}
+	}
+}
+
+static void gaudi_stop_pci_dma_qmans(struct hl_device *hdev)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+
+	if (!(gaudi->hw_cap_initialized & HW_CAP_PCI_DMA))
+		return;
+
+	/* Stop upper CPs of QMANs 0.0 to 1.3 and 5.0 to 5.3 */
+	WREG32(mmDMA0_QM_GLBL_CFG1, 0xF << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT);
+	WREG32(mmDMA1_QM_GLBL_CFG1, 0xF << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT);
+	WREG32(mmDMA5_QM_GLBL_CFG1, 0xF << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT);
+}
+
+static void gaudi_stop_hbm_dma_qmans(struct hl_device *hdev)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+
+	if (!(gaudi->hw_cap_initialized & HW_CAP_HBM_DMA))
+		return;
+
+	/* Stop CPs of HBM DMA QMANs */
+
+	WREG32(mmDMA2_QM_GLBL_CFG1, 0x1F << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT);
+	WREG32(mmDMA3_QM_GLBL_CFG1, 0x1F << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT);
+	WREG32(mmDMA4_QM_GLBL_CFG1, 0x1F << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT);
+	WREG32(mmDMA6_QM_GLBL_CFG1, 0x1F << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT);
+	WREG32(mmDMA7_QM_GLBL_CFG1, 0x1F << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT);
+}
+
+static void gaudi_stop_mme_qmans(struct hl_device *hdev)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+
+	if (!(gaudi->hw_cap_initialized & HW_CAP_MME))
+		return;
+
+	/* Stop CPs of MME QMANs */
+	WREG32(mmMME2_QM_GLBL_CFG1, 0x1F << MME0_QM_GLBL_CFG1_CP_STOP_SHIFT);
+	WREG32(mmMME0_QM_GLBL_CFG1, 0x1F << MME0_QM_GLBL_CFG1_CP_STOP_SHIFT);
+}
+
+static void gaudi_stop_tpc_qmans(struct hl_device *hdev)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+
+	if (!(gaudi->hw_cap_initialized & HW_CAP_TPC_MASK))
+		return;
+
+	WREG32(mmTPC0_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
+	WREG32(mmTPC1_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
+	WREG32(mmTPC2_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
+	WREG32(mmTPC3_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
+	WREG32(mmTPC4_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
+	WREG32(mmTPC5_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
+	WREG32(mmTPC6_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
+	WREG32(mmTPC7_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
+}
+
+static void gaudi_stop_nic_qmans(struct hl_device *hdev)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+
+	/* Stop upper CPs of QMANs */
+
+	if (gaudi->hw_cap_initialized & HW_CAP_NIC0)
+		WREG32(mmNIC0_QM0_GLBL_CFG1,
+				NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK |
+				NIC0_QM0_GLBL_CFG1_CQF_STOP_MASK |
+				NIC0_QM0_GLBL_CFG1_CP_STOP_MASK);
+
+	if (gaudi->hw_cap_initialized & HW_CAP_NIC1)
+		WREG32(mmNIC0_QM1_GLBL_CFG1,
+				NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK |
+				NIC0_QM0_GLBL_CFG1_CQF_STOP_MASK |
+				NIC0_QM0_GLBL_CFG1_CP_STOP_MASK);
+
+	if (gaudi->hw_cap_initialized & HW_CAP_NIC2)
+		WREG32(mmNIC1_QM0_GLBL_CFG1,
+				NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK |
+				NIC0_QM0_GLBL_CFG1_CQF_STOP_MASK |
+				NIC0_QM0_GLBL_CFG1_CP_STOP_MASK);
+
+	if (gaudi->hw_cap_initialized & HW_CAP_NIC3)
+		WREG32(mmNIC1_QM1_GLBL_CFG1,
+				NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK |
+				NIC0_QM0_GLBL_CFG1_CQF_STOP_MASK |
+				NIC0_QM0_GLBL_CFG1_CP_STOP_MASK);
+
+	if (gaudi->hw_cap_initialized & HW_CAP_NIC4)
+		WREG32(mmNIC2_QM0_GLBL_CFG1,
+				NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK |
+				NIC0_QM0_GLBL_CFG1_CQF_STOP_MASK |
+				NIC0_QM0_GLBL_CFG1_CP_STOP_MASK);
+
+	if (gaudi->hw_cap_initialized & HW_CAP_NIC5)
+		WREG32(mmNIC2_QM1_GLBL_CFG1,
+				NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK |
+				NIC0_QM0_GLBL_CFG1_CQF_STOP_MASK |
+				NIC0_QM0_GLBL_CFG1_CP_STOP_MASK);
+
+	if (gaudi->hw_cap_initialized & HW_CAP_NIC6)
+		WREG32(mmNIC3_QM0_GLBL_CFG1,
+				NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK |
+				NIC0_QM0_GLBL_CFG1_CQF_STOP_MASK |
+				NIC0_QM0_GLBL_CFG1_CP_STOP_MASK);
+
+	if (gaudi->hw_cap_initialized & HW_CAP_NIC7)
+		WREG32(mmNIC3_QM1_GLBL_CFG1,
+				NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK |
+				NIC0_QM0_GLBL_CFG1_CQF_STOP_MASK |
+				NIC0_QM0_GLBL_CFG1_CP_STOP_MASK);
+
+	if (gaudi->hw_cap_initialized & HW_CAP_NIC8)
+		WREG32(mmNIC4_QM0_GLBL_CFG1,
+				NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK |
+				NIC0_QM0_GLBL_CFG1_CQF_STOP_MASK |
+				NIC0_QM0_GLBL_CFG1_CP_STOP_MASK);
+
+	if (gaudi->hw_cap_initialized & HW_CAP_NIC9)
+		WREG32(mmNIC4_QM1_GLBL_CFG1,
+				NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK |
+				NIC0_QM0_GLBL_CFG1_CQF_STOP_MASK |
+				NIC0_QM0_GLBL_CFG1_CP_STOP_MASK);
+}
+
+static void gaudi_pci_dma_stall(struct hl_device *hdev)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+
+	if (!(gaudi->hw_cap_initialized & HW_CAP_PCI_DMA))
+		return;
+
+	WREG32(mmDMA0_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT);
+	WREG32(mmDMA1_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT);
+	WREG32(mmDMA5_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT);
+}
+
+static void gaudi_hbm_dma_stall(struct hl_device *hdev)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+
+	if (!(gaudi->hw_cap_initialized & HW_CAP_HBM_DMA))
+		return;
+
+	WREG32(mmDMA2_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT);
+	WREG32(mmDMA3_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT);
+	WREG32(mmDMA4_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT);
+	WREG32(mmDMA6_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT);
+	WREG32(mmDMA7_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT);
+}
+
+static void gaudi_mme_stall(struct hl_device *hdev)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+
+	if (!(gaudi->hw_cap_initialized & HW_CAP_MME))
+		return;
+
+	/* WA for H3-1800 bug: do ACC and SBAB writes twice */
+	WREG32(mmMME0_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT);
+	WREG32(mmMME0_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT);
+	WREG32(mmMME0_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT);
+	WREG32(mmMME0_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT);
+	WREG32(mmMME1_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT);
+	WREG32(mmMME1_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT);
+	WREG32(mmMME1_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT);
+	WREG32(mmMME1_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT);
+	WREG32(mmMME2_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT);
+	WREG32(mmMME2_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT);
+	WREG32(mmMME2_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT);
+	WREG32(mmMME2_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT);
+	WREG32(mmMME3_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT);
+	WREG32(mmMME3_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT);
+	WREG32(mmMME3_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT);
+	WREG32(mmMME3_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT);
+}
+
+static void gaudi_tpc_stall(struct hl_device *hdev)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+
+	if (!(gaudi->hw_cap_initialized & HW_CAP_TPC_MASK))
+		return;
+
+	WREG32(mmTPC0_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
+	WREG32(mmTPC1_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
+	WREG32(mmTPC2_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
+	WREG32(mmTPC3_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
+	WREG32(mmTPC4_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
+	WREG32(mmTPC5_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
+	WREG32(mmTPC6_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
+	WREG32(mmTPC7_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
+}
+
+static void gaudi_disable_clock_gating(struct hl_device *hdev)
+{
+	u32 qman_offset;
+	int i;
+
+	if (hdev->asic_prop.fw_security_enabled)
+		return;
+
+	for (i = 0, qman_offset = 0 ; i < DMA_NUMBER_OF_CHANNELS ; i++) {
+		WREG32(mmDMA0_QM_CGM_CFG + qman_offset, 0);
+		WREG32(mmDMA0_QM_CGM_CFG1 + qman_offset, 0);
+
+		qman_offset += (mmDMA1_QM_CGM_CFG - mmDMA0_QM_CGM_CFG);
+	}
+
+	WREG32(mmMME0_QM_CGM_CFG, 0);
+	WREG32(mmMME0_QM_CGM_CFG1, 0);
+	WREG32(mmMME2_QM_CGM_CFG, 0);
+	WREG32(mmMME2_QM_CGM_CFG1, 0);
+
+	for (i = 0, qman_offset = 0 ; i < TPC_NUMBER_OF_ENGINES ; i++) {
+		WREG32(mmTPC0_QM_CGM_CFG + qman_offset, 0);
+		WREG32(mmTPC0_QM_CGM_CFG1 + qman_offset, 0);
+
+		qman_offset += (mmTPC1_QM_CGM_CFG - mmTPC0_QM_CGM_CFG);
+	}
+}
+
+static void gaudi_enable_timestamp(struct hl_device *hdev)
+{
+	/* Disable the timestamp counter */
+	WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0);
+
+	/* Zero the lower/upper parts of the 64-bit counter */
+	WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0xC, 0);
+	WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0x8, 0);
+
+	/* Enable the counter */
+	WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 1);
+}
+
+static void gaudi_disable_timestamp(struct hl_device *hdev)
+{
+	/* Disable the timestamp counter */
+	WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0);
+}
+
+static void gaudi_halt_engines(struct hl_device *hdev, bool hard_reset, bool fw_reset)
+{
+	u32 wait_timeout_ms;
+
+	if (hdev->pldm)
+		wait_timeout_ms = GAUDI_PLDM_RESET_WAIT_MSEC;
+	else
+		wait_timeout_ms = GAUDI_RESET_WAIT_MSEC;
+
+	if (fw_reset)
+		goto skip_engines;
+
+	gaudi_stop_nic_qmans(hdev);
+	gaudi_stop_mme_qmans(hdev);
+	gaudi_stop_tpc_qmans(hdev);
+	gaudi_stop_hbm_dma_qmans(hdev);
+	gaudi_stop_pci_dma_qmans(hdev);
+
+	msleep(wait_timeout_ms);
+
+	gaudi_pci_dma_stall(hdev);
+	gaudi_hbm_dma_stall(hdev);
+	gaudi_tpc_stall(hdev);
+	gaudi_mme_stall(hdev);
+
+	msleep(wait_timeout_ms);
+
+	gaudi_disable_nic_qmans(hdev);
+	gaudi_disable_mme_qmans(hdev);
+	gaudi_disable_tpc_qmans(hdev);
+	gaudi_disable_hbm_dma_qmans(hdev);
+	gaudi_disable_pci_dma_qmans(hdev);
+
+	gaudi_disable_timestamp(hdev);
+
+skip_engines:
+	gaudi_disable_msi(hdev);
+}
+
+static int gaudi_mmu_init(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct gaudi_device *gaudi = hdev->asic_specific;
+	u64 hop0_addr;
+	int rc, i;
+
+	if (gaudi->hw_cap_initialized & HW_CAP_MMU)
+		return 0;
+
+	for (i = 0 ; i < prop->max_asid ; i++) {
+		hop0_addr = prop->mmu_pgt_addr +
+				(i * prop->dmmu.hop_table_size);
+
+		rc = gaudi_mmu_update_asid_hop0_addr(hdev, i, hop0_addr);
+		if (rc) {
+			dev_err(hdev->dev,
+				"failed to set hop0 addr for asid %d\n", i);
+			return rc;
+		}
+	}
+
+	/* init MMU cache manage page */
+	WREG32(mmSTLB_CACHE_INV_BASE_39_8, prop->mmu_cache_mng_addr >> 8);
+	WREG32(mmSTLB_CACHE_INV_BASE_49_40, prop->mmu_cache_mng_addr >> 40);
+
+	/* mem cache invalidation */
+	WREG32(mmSTLB_MEM_CACHE_INVALIDATION, 1);
+
+	rc = hl_mmu_invalidate_cache(hdev, true, 0);
+	if (rc)
+		return rc;
+
+	WREG32(mmMMU_UP_MMU_ENABLE, 1);
+	WREG32(mmMMU_UP_SPI_MASK, 0xF);
+
+	WREG32(mmSTLB_HOP_CONFIGURATION, 0x30440);
+
+	/*
+	 * The H/W expects the first PI after init to be 1. After wraparound
+	 * we'll write 0.
+	 */
+	gaudi->mmu_cache_inv_pi = 1;
+
+	gaudi->hw_cap_initialized |= HW_CAP_MMU;
+
+	return 0;
+}
+
+static int gaudi_load_firmware_to_device(struct hl_device *hdev)
+{
+	void __iomem *dst;
+
+	dst = hdev->pcie_bar[HBM_BAR_ID] + LINUX_FW_OFFSET;
+
+	return hl_fw_load_fw_to_device(hdev, GAUDI_LINUX_FW_FILE, dst, 0, 0);
+}
+
+static int gaudi_load_boot_fit_to_device(struct hl_device *hdev)
+{
+	void __iomem *dst;
+
+	dst = hdev->pcie_bar[SRAM_BAR_ID] + BOOT_FIT_SRAM_OFFSET;
+
+	return hl_fw_load_fw_to_device(hdev, GAUDI_BOOT_FIT_FILE, dst, 0, 0);
+}
+
+static void gaudi_init_dynamic_firmware_loader(struct hl_device *hdev)
+{
+	struct dynamic_fw_load_mgr *dynamic_loader;
+	struct cpu_dyn_regs *dyn_regs;
+
+	dynamic_loader = &hdev->fw_loader.dynamic_loader;
+
+	/*
+	 * here we update initial values for few specific dynamic regs (as
+	 * before reading the first descriptor from FW those value has to be
+	 * hard-coded) in later stages of the protocol those values will be
+	 * updated automatically by reading the FW descriptor so data there
+	 * will always be up-to-date
+	 */
+	dyn_regs = &dynamic_loader->comm_desc.cpu_dyn_regs;
+	dyn_regs->kmd_msg_to_cpu =
+				cpu_to_le32(mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU);
+	dyn_regs->cpu_cmd_status_to_host =
+				cpu_to_le32(mmCPU_CMD_STATUS_TO_HOST);
+
+	dynamic_loader->wait_for_bl_timeout = GAUDI_WAIT_FOR_BL_TIMEOUT_USEC;
+}
+
+static void gaudi_init_static_firmware_loader(struct hl_device *hdev)
+{
+	struct static_fw_load_mgr *static_loader;
+
+	static_loader = &hdev->fw_loader.static_loader;
+
+	static_loader->preboot_version_max_off = SRAM_SIZE - VERSION_MAX_LEN;
+	static_loader->boot_fit_version_max_off = SRAM_SIZE - VERSION_MAX_LEN;
+	static_loader->kmd_msg_to_cpu_reg = mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU;
+	static_loader->cpu_cmd_status_to_host_reg = mmCPU_CMD_STATUS_TO_HOST;
+	static_loader->cpu_boot_status_reg = mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS;
+	static_loader->cpu_boot_dev_status0_reg = mmCPU_BOOT_DEV_STS0;
+	static_loader->cpu_boot_dev_status1_reg = mmCPU_BOOT_DEV_STS1;
+	static_loader->boot_err0_reg = mmCPU_BOOT_ERR0;
+	static_loader->boot_err1_reg = mmCPU_BOOT_ERR1;
+	static_loader->preboot_version_offset_reg = mmPREBOOT_VER_OFFSET;
+	static_loader->boot_fit_version_offset_reg = mmUBOOT_VER_OFFSET;
+	static_loader->sram_offset_mask = ~(lower_32_bits(SRAM_BASE_ADDR));
+	static_loader->cpu_reset_wait_msec = hdev->pldm ?
+			GAUDI_PLDM_RESET_WAIT_MSEC :
+			GAUDI_CPU_RESET_WAIT_MSEC;
+}
+
+static void gaudi_init_firmware_preload_params(struct hl_device *hdev)
+{
+	struct pre_fw_load_props *pre_fw_load = &hdev->fw_loader.pre_fw_load;
+
+	pre_fw_load->cpu_boot_status_reg = mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS;
+	pre_fw_load->sts_boot_dev_sts0_reg = mmCPU_BOOT_DEV_STS0;
+	pre_fw_load->sts_boot_dev_sts1_reg = mmCPU_BOOT_DEV_STS1;
+	pre_fw_load->boot_err0_reg = mmCPU_BOOT_ERR0;
+	pre_fw_load->boot_err1_reg = mmCPU_BOOT_ERR1;
+	pre_fw_load->wait_for_preboot_timeout = GAUDI_BOOT_FIT_REQ_TIMEOUT_USEC;
+}
+
+static void gaudi_init_firmware_loader(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct fw_load_mgr *fw_loader = &hdev->fw_loader;
+
+	/* fill common fields */
+	fw_loader->fw_comp_loaded = FW_TYPE_NONE;
+	fw_loader->boot_fit_img.image_name = GAUDI_BOOT_FIT_FILE;
+	fw_loader->linux_img.image_name = GAUDI_LINUX_FW_FILE;
+	fw_loader->cpu_timeout = GAUDI_CPU_TIMEOUT_USEC;
+	fw_loader->boot_fit_timeout = GAUDI_BOOT_FIT_REQ_TIMEOUT_USEC;
+	fw_loader->skip_bmc = !hdev->bmc_enable;
+	fw_loader->sram_bar_id = SRAM_BAR_ID;
+	fw_loader->dram_bar_id = HBM_BAR_ID;
+
+	if (prop->dynamic_fw_load)
+		gaudi_init_dynamic_firmware_loader(hdev);
+	else
+		gaudi_init_static_firmware_loader(hdev);
+}
+
+static int gaudi_init_cpu(struct hl_device *hdev)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+	int rc;
+
+	if (!(hdev->fw_components & FW_TYPE_PREBOOT_CPU))
+		return 0;
+
+	if (gaudi->hw_cap_initialized & HW_CAP_CPU)
+		return 0;
+
+	/*
+	 * The device CPU works with 40 bits addresses.
+	 * This register sets the extension to 50 bits.
+	 */
+	if (!hdev->asic_prop.fw_security_enabled)
+		WREG32(mmCPU_IF_CPU_MSB_ADDR, hdev->cpu_pci_msb_addr);
+
+	rc = hl_fw_init_cpu(hdev);
+
+	if (rc)
+		return rc;
+
+	gaudi->hw_cap_initialized |= HW_CAP_CPU;
+
+	return 0;
+}
+
+static int gaudi_init_cpu_queues(struct hl_device *hdev, u32 cpu_timeout)
+{
+	struct cpu_dyn_regs *dyn_regs =
+			&hdev->fw_loader.dynamic_loader.comm_desc.cpu_dyn_regs;
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct gaudi_device *gaudi = hdev->asic_specific;
+	u32 status, irq_handler_offset;
+	struct hl_eq *eq;
+	struct hl_hw_queue *cpu_pq =
+			&hdev->kernel_queues[GAUDI_QUEUE_ID_CPU_PQ];
+	int err;
+
+	if (!hdev->cpu_queues_enable)
+		return 0;
+
+	if (gaudi->hw_cap_initialized & HW_CAP_CPU_Q)
+		return 0;
+
+	eq = &hdev->event_queue;
+
+	WREG32(mmCPU_IF_PQ_BASE_ADDR_LOW, lower_32_bits(cpu_pq->bus_address));
+	WREG32(mmCPU_IF_PQ_BASE_ADDR_HIGH, upper_32_bits(cpu_pq->bus_address));
+
+	WREG32(mmCPU_IF_EQ_BASE_ADDR_LOW, lower_32_bits(eq->bus_address));
+	WREG32(mmCPU_IF_EQ_BASE_ADDR_HIGH, upper_32_bits(eq->bus_address));
+
+	WREG32(mmCPU_IF_CQ_BASE_ADDR_LOW,
+			lower_32_bits(hdev->cpu_accessible_dma_address));
+	WREG32(mmCPU_IF_CQ_BASE_ADDR_HIGH,
+			upper_32_bits(hdev->cpu_accessible_dma_address));
+
+	WREG32(mmCPU_IF_PQ_LENGTH, HL_QUEUE_SIZE_IN_BYTES);
+	WREG32(mmCPU_IF_EQ_LENGTH, HL_EQ_SIZE_IN_BYTES);
+	WREG32(mmCPU_IF_CQ_LENGTH, HL_CPU_ACCESSIBLE_MEM_SIZE);
+
+	/* Used for EQ CI */
+	WREG32(mmCPU_IF_EQ_RD_OFFS, 0);
+
+	WREG32(mmCPU_IF_PF_PQ_PI, 0);
+
+	WREG32(mmCPU_IF_QUEUE_INIT, PQ_INIT_STATUS_READY_FOR_CP_SINGLE_MSI);
+
+	irq_handler_offset = prop->gic_interrupts_enable ?
+			mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR :
+			le32_to_cpu(dyn_regs->gic_host_pi_upd_irq);
+
+	WREG32(irq_handler_offset,
+		gaudi_irq_map_table[GAUDI_EVENT_PI_UPDATE].cpu_id);
+
+	err = hl_poll_timeout(
+		hdev,
+		mmCPU_IF_QUEUE_INIT,
+		status,
+		(status == PQ_INIT_STATUS_READY_FOR_HOST),
+		1000,
+		cpu_timeout);
+
+	if (err) {
+		dev_err(hdev->dev,
+			"Failed to communicate with Device CPU (CPU-CP timeout)\n");
+		return -EIO;
+	}
+
+	/* update FW application security bits */
+	if (prop->fw_cpu_boot_dev_sts0_valid)
+		prop->fw_app_cpu_boot_dev_sts0 = RREG32(mmCPU_BOOT_DEV_STS0);
+	if (prop->fw_cpu_boot_dev_sts1_valid)
+		prop->fw_app_cpu_boot_dev_sts1 = RREG32(mmCPU_BOOT_DEV_STS1);
+
+	gaudi->hw_cap_initialized |= HW_CAP_CPU_Q;
+	return 0;
+}
+
+static void gaudi_pre_hw_init(struct hl_device *hdev)
+{
+	/* Perform read from the device to make sure device is up */
+	RREG32(mmHW_STATE);
+
+	if (!hdev->asic_prop.fw_security_enabled) {
+		/* Set the access through PCI bars (Linux driver only) as
+		 * secured
+		 */
+		WREG32(mmPCIE_WRAP_LBW_PROT_OVR,
+				(PCIE_WRAP_LBW_PROT_OVR_RD_EN_MASK |
+				PCIE_WRAP_LBW_PROT_OVR_WR_EN_MASK));
+
+		/* Perform read to flush the waiting writes to ensure
+		 * configuration was set in the device
+		 */
+		RREG32(mmPCIE_WRAP_LBW_PROT_OVR);
+	}
+
+	/*
+	 * Let's mark in the H/W that we have reached this point. We check
+	 * this value in the reset_before_init function to understand whether
+	 * we need to reset the chip before doing H/W init. This register is
+	 * cleared by the H/W upon H/W reset
+	 */
+	WREG32(mmHW_STATE, HL_DEVICE_HW_STATE_DIRTY);
+}
+
+static int gaudi_hw_init(struct hl_device *hdev)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+	int rc;
+
+	gaudi_pre_hw_init(hdev);
+
+	/* If iATU is done by FW, the HBM bar ALWAYS points to DRAM_PHYS_BASE.
+	 * So we set it here and if anyone tries to move it later to
+	 * a different address, there will be an error
+	 */
+	if (hdev->asic_prop.iatu_done_by_fw)
+		gaudi->hbm_bar_cur_addr = DRAM_PHYS_BASE;
+
+	/*
+	 * Before pushing u-boot/linux to device, need to set the hbm bar to
+	 * base address of dram
+	 */
+	if (gaudi_set_hbm_bar_base(hdev, DRAM_PHYS_BASE) == U64_MAX) {
+		dev_err(hdev->dev,
+			"failed to map HBM bar to DRAM base address\n");
+		return -EIO;
+	}
+
+	rc = gaudi_init_cpu(hdev);
+	if (rc) {
+		dev_err(hdev->dev, "failed to initialize CPU\n");
+		return rc;
+	}
+
+	/* In case the clock gating was enabled in preboot we need to disable
+	 * it here before touching the MME/TPC registers.
+	 */
+	gaudi_disable_clock_gating(hdev);
+
+	/* SRAM scrambler must be initialized after CPU is running from HBM */
+	gaudi_init_scrambler_sram(hdev);
+
+	/* This is here just in case we are working without CPU */
+	gaudi_init_scrambler_hbm(hdev);
+
+	gaudi_init_golden_registers(hdev);
+
+	rc = gaudi_mmu_init(hdev);
+	if (rc)
+		return rc;
+
+	gaudi_init_security(hdev);
+
+	gaudi_init_pci_dma_qmans(hdev);
+
+	gaudi_init_hbm_dma_qmans(hdev);
+
+	gaudi_init_mme_qmans(hdev);
+
+	gaudi_init_tpc_qmans(hdev);
+
+	gaudi_init_nic_qmans(hdev);
+
+	gaudi_enable_timestamp(hdev);
+
+	/* MSI must be enabled before CPU queues and NIC are initialized */
+	rc = gaudi_enable_msi(hdev);
+	if (rc)
+		goto disable_queues;
+
+	/* must be called after MSI was enabled */
+	rc = gaudi_init_cpu_queues(hdev, GAUDI_CPU_TIMEOUT_USEC);
+	if (rc) {
+		dev_err(hdev->dev, "failed to initialize CPU H/W queues %d\n",
+			rc);
+		goto disable_msi;
+	}
+
+	/* Perform read from the device to flush all configuration */
+	RREG32(mmHW_STATE);
+
+	return 0;
+
+disable_msi:
+	gaudi_disable_msi(hdev);
+disable_queues:
+	gaudi_disable_mme_qmans(hdev);
+	gaudi_disable_pci_dma_qmans(hdev);
+
+	return rc;
+}
+
+static int gaudi_hw_fini(struct hl_device *hdev, bool hard_reset, bool fw_reset)
+{
+	struct cpu_dyn_regs *dyn_regs =
+			&hdev->fw_loader.dynamic_loader.comm_desc.cpu_dyn_regs;
+	u32 status, reset_timeout_ms, cpu_timeout_ms, irq_handler_offset;
+	struct gaudi_device *gaudi = hdev->asic_specific;
+	bool driver_performs_reset;
+
+	if (!hard_reset) {
+		dev_err(hdev->dev, "GAUDI doesn't support soft-reset\n");
+		return 0;
+	}
+
+	if (hdev->pldm) {
+		reset_timeout_ms = GAUDI_PLDM_HRESET_TIMEOUT_MSEC;
+		cpu_timeout_ms = GAUDI_PLDM_RESET_WAIT_MSEC;
+	} else {
+		reset_timeout_ms = GAUDI_RESET_TIMEOUT_MSEC;
+		cpu_timeout_ms = GAUDI_CPU_RESET_WAIT_MSEC;
+	}
+
+	if (fw_reset) {
+		dev_dbg(hdev->dev,
+			"Firmware performs HARD reset, going to wait %dms\n",
+			reset_timeout_ms);
+
+		goto skip_reset;
+	}
+
+	driver_performs_reset = !!(!hdev->asic_prop.fw_security_enabled &&
+					!hdev->asic_prop.hard_reset_done_by_fw);
+
+	/* Set device to handle FLR by H/W as we will put the device CPU to
+	 * halt mode
+	 */
+	if (driver_performs_reset)
+		WREG32(mmPCIE_AUX_FLR_CTRL, (PCIE_AUX_FLR_CTRL_HW_CTRL_MASK |
+					PCIE_AUX_FLR_CTRL_INT_MASK_MASK));
+
+	/* If linux is loaded in the device CPU we need to communicate with it
+	 * via the GIC. Otherwise, we need to use COMMS or the MSG_TO_CPU
+	 * registers in case of old F/Ws
+	 */
+	if (hdev->fw_loader.fw_comp_loaded & FW_TYPE_LINUX) {
+		irq_handler_offset = hdev->asic_prop.gic_interrupts_enable ?
+				mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR :
+				le32_to_cpu(dyn_regs->gic_host_halt_irq);
+
+		WREG32(irq_handler_offset,
+			gaudi_irq_map_table[GAUDI_EVENT_HALT_MACHINE].cpu_id);
+
+		/* This is a hail-mary attempt to revive the card in the small chance that the
+		 * f/w has experienced a watchdog event, which caused it to return back to preboot.
+		 * In that case, triggering reset through GIC won't help. We need to trigger the
+		 * reset as if Linux wasn't loaded.
+		 *
+		 * We do it only if the reset cause was HB, because that would be the indication
+		 * of such an event.
+		 *
+		 * In case watchdog hasn't expired but we still got HB, then this won't do any
+		 * damage.
+		 */
+		if (hdev->reset_info.curr_reset_cause == HL_RESET_CAUSE_HEARTBEAT) {
+			if (hdev->asic_prop.hard_reset_done_by_fw)
+				hl_fw_ask_hard_reset_without_linux(hdev);
+			else
+				hl_fw_ask_halt_machine_without_linux(hdev);
+		}
+	} else {
+		if (hdev->asic_prop.hard_reset_done_by_fw)
+			hl_fw_ask_hard_reset_without_linux(hdev);
+		else
+			hl_fw_ask_halt_machine_without_linux(hdev);
+	}
+
+	if (driver_performs_reset) {
+
+		/* Configure the reset registers. Must be done as early as
+		 * possible in case we fail during H/W initialization
+		 */
+		WREG32(mmPSOC_GLOBAL_CONF_SOFT_RST_CFG_H,
+						(CFG_RST_H_DMA_MASK |
+						CFG_RST_H_MME_MASK |
+						CFG_RST_H_SM_MASK |
+						CFG_RST_H_TPC_7_MASK));
+
+		WREG32(mmPSOC_GLOBAL_CONF_SOFT_RST_CFG_L, CFG_RST_L_TPC_MASK);
+
+		WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG_H,
+						(CFG_RST_H_HBM_MASK |
+						CFG_RST_H_TPC_7_MASK |
+						CFG_RST_H_NIC_MASK |
+						CFG_RST_H_SM_MASK |
+						CFG_RST_H_DMA_MASK |
+						CFG_RST_H_MME_MASK |
+						CFG_RST_H_CPU_MASK |
+						CFG_RST_H_MMU_MASK));
+
+		WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG_L,
+						(CFG_RST_L_IF_MASK |
+						CFG_RST_L_PSOC_MASK |
+						CFG_RST_L_TPC_MASK));
+
+		msleep(cpu_timeout_ms);
+
+		/* Tell ASIC not to re-initialize PCIe */
+		WREG32(mmPREBOOT_PCIE_EN, LKD_HARD_RESET_MAGIC);
+
+		/* Restart BTL/BLR upon hard-reset */
+		WREG32(mmPSOC_GLOBAL_CONF_BOOT_SEQ_RE_START, 1);
+
+		WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST,
+			1 << PSOC_GLOBAL_CONF_SW_ALL_RST_IND_SHIFT);
+
+		dev_dbg(hdev->dev,
+			"Issued HARD reset command, going to wait %dms\n",
+			reset_timeout_ms);
+	} else {
+		dev_dbg(hdev->dev,
+			"Firmware performs HARD reset, going to wait %dms\n",
+			reset_timeout_ms);
+	}
+
+skip_reset:
+	/*
+	 * After hard reset, we can't poll the BTM_FSM register because the PSOC
+	 * itself is in reset. Need to wait until the reset is deasserted
+	 */
+	msleep(reset_timeout_ms);
+
+	status = RREG32(mmPSOC_GLOBAL_CONF_BTM_FSM);
+	if (status & PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK) {
+		dev_err(hdev->dev, "Timeout while waiting for device to reset 0x%x\n", status);
+		return -ETIMEDOUT;
+	}
+
+	if (gaudi) {
+		gaudi->hw_cap_initialized &= ~(HW_CAP_CPU | HW_CAP_CPU_Q | HW_CAP_HBM |
+						HW_CAP_PCI_DMA | HW_CAP_MME | HW_CAP_TPC_MASK |
+						HW_CAP_HBM_DMA | HW_CAP_PLL | HW_CAP_NIC_MASK |
+						HW_CAP_MMU | HW_CAP_SRAM_SCRAMBLER |
+						HW_CAP_HBM_SCRAMBLER);
+
+		memset(gaudi->events_stat, 0, sizeof(gaudi->events_stat));
+
+		hdev->device_cpu_is_halted = false;
+	}
+	return 0;
+}
+
+static int gaudi_suspend(struct hl_device *hdev)
+{
+	return hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_DISABLE_PCI_ACCESS, 0x0);
+}
+
+static int gaudi_resume(struct hl_device *hdev)
+{
+	return gaudi_init_iatu(hdev);
+}
+
+static int gaudi_mmap(struct hl_device *hdev, struct vm_area_struct *vma,
+			void *cpu_addr, dma_addr_t dma_addr, size_t size)
+{
+	int rc;
+
+	vm_flags_set(vma, VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP |
+			VM_DONTCOPY | VM_NORESERVE);
+
+#ifdef _HAS_DMA_MMAP_COHERENT
+	/*
+	 * If dma_alloc_coherent() returns a vmalloc address, set VM_MIXEDMAP
+	 * so vm_insert_page() can handle it safely. Without this, the kernel
+	 * may BUG_ON due to VM_PFNMAP.
+	 */
+	if (is_vmalloc_addr(cpu_addr))
+		vm_flags_set(vma, VM_MIXEDMAP);
+
+	rc = dma_mmap_coherent(hdev->dev, vma, cpu_addr,
+				(dma_addr - HOST_PHYS_BASE), size);
+	if (rc)
+		dev_err(hdev->dev, "dma_mmap_coherent error %d", rc);
+#else
+
+	rc = remap_pfn_range(vma, vma->vm_start,
+				virt_to_phys(cpu_addr) >> PAGE_SHIFT,
+				size, vma->vm_page_prot);
+	if (rc)
+		dev_err(hdev->dev, "remap_pfn_range error %d", rc);
+
+ #endif
+
+
+	return rc;
+}
+
+static void gaudi_ring_doorbell(struct hl_device *hdev, u32 hw_queue_id, u32 pi)
+{
+	struct cpu_dyn_regs *dyn_regs =
+			&hdev->fw_loader.dynamic_loader.comm_desc.cpu_dyn_regs;
+	u32 db_reg_offset, db_value, dma_qm_offset, q_off, irq_handler_offset;
+	struct gaudi_device *gaudi = hdev->asic_specific;
+	bool invalid_queue = false;
+	int dma_id;
+
+	switch (hw_queue_id) {
+	case GAUDI_QUEUE_ID_DMA_0_0...GAUDI_QUEUE_ID_DMA_0_3:
+		dma_id = gaudi_dma_assignment[GAUDI_PCI_DMA_1];
+		dma_qm_offset = dma_id * DMA_QMAN_OFFSET;
+		q_off = dma_qm_offset + (hw_queue_id & 0x3) * 4;
+		db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
+		break;
+
+	case GAUDI_QUEUE_ID_DMA_1_0...GAUDI_QUEUE_ID_DMA_1_3:
+		dma_id = gaudi_dma_assignment[GAUDI_PCI_DMA_2];
+		dma_qm_offset = dma_id * DMA_QMAN_OFFSET;
+		q_off = dma_qm_offset + (hw_queue_id & 0x3) * 4;
+		db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
+		break;
+
+	case GAUDI_QUEUE_ID_DMA_2_0...GAUDI_QUEUE_ID_DMA_2_3:
+		dma_id = gaudi_dma_assignment[GAUDI_HBM_DMA_1];
+		dma_qm_offset = dma_id * DMA_QMAN_OFFSET;
+		q_off = dma_qm_offset + ((hw_queue_id - 1) & 0x3) * 4;
+		db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
+		break;
+
+	case GAUDI_QUEUE_ID_DMA_3_0...GAUDI_QUEUE_ID_DMA_3_3:
+		dma_id = gaudi_dma_assignment[GAUDI_HBM_DMA_2];
+		dma_qm_offset = dma_id * DMA_QMAN_OFFSET;
+		q_off = dma_qm_offset + ((hw_queue_id - 1) & 0x3) * 4;
+		db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
+		break;
+
+	case GAUDI_QUEUE_ID_DMA_4_0...GAUDI_QUEUE_ID_DMA_4_3:
+		dma_id = gaudi_dma_assignment[GAUDI_HBM_DMA_3];
+		dma_qm_offset = dma_id * DMA_QMAN_OFFSET;
+		q_off = dma_qm_offset + ((hw_queue_id - 1) & 0x3) * 4;
+		db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
+		break;
+
+	case GAUDI_QUEUE_ID_DMA_5_0...GAUDI_QUEUE_ID_DMA_5_3:
+		dma_id = gaudi_dma_assignment[GAUDI_HBM_DMA_4];
+		dma_qm_offset = dma_id * DMA_QMAN_OFFSET;
+		q_off = dma_qm_offset + ((hw_queue_id - 1) & 0x3) * 4;
+		db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
+		break;
+
+	case GAUDI_QUEUE_ID_DMA_6_0...GAUDI_QUEUE_ID_DMA_6_3:
+		dma_id = gaudi_dma_assignment[GAUDI_HBM_DMA_5];
+		dma_qm_offset = dma_id * DMA_QMAN_OFFSET;
+		q_off = dma_qm_offset + ((hw_queue_id - 1) & 0x3) * 4;
+		db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
+		break;
+
+	case GAUDI_QUEUE_ID_DMA_7_0...GAUDI_QUEUE_ID_DMA_7_3:
+		dma_id = gaudi_dma_assignment[GAUDI_HBM_DMA_6];
+		dma_qm_offset = dma_id * DMA_QMAN_OFFSET;
+		q_off = dma_qm_offset + ((hw_queue_id - 1) & 0x3) * 4;
+		db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
+		break;
+
+	case GAUDI_QUEUE_ID_CPU_PQ:
+		if (gaudi->hw_cap_initialized & HW_CAP_CPU_Q)
+			db_reg_offset = mmCPU_IF_PF_PQ_PI;
+		else
+			invalid_queue = true;
+		break;
+
+	case GAUDI_QUEUE_ID_MME_0_0:
+		db_reg_offset = mmMME2_QM_PQ_PI_0;
+		break;
+
+	case GAUDI_QUEUE_ID_MME_0_1:
+		db_reg_offset = mmMME2_QM_PQ_PI_1;
+		break;
+
+	case GAUDI_QUEUE_ID_MME_0_2:
+		db_reg_offset = mmMME2_QM_PQ_PI_2;
+		break;
+
+	case GAUDI_QUEUE_ID_MME_0_3:
+		db_reg_offset = mmMME2_QM_PQ_PI_3;
+		break;
+
+	case GAUDI_QUEUE_ID_MME_1_0:
+		db_reg_offset = mmMME0_QM_PQ_PI_0;
+		break;
+
+	case GAUDI_QUEUE_ID_MME_1_1:
+		db_reg_offset = mmMME0_QM_PQ_PI_1;
+		break;
+
+	case GAUDI_QUEUE_ID_MME_1_2:
+		db_reg_offset = mmMME0_QM_PQ_PI_2;
+		break;
+
+	case GAUDI_QUEUE_ID_MME_1_3:
+		db_reg_offset = mmMME0_QM_PQ_PI_3;
+		break;
+
+	case GAUDI_QUEUE_ID_TPC_0_0:
+		db_reg_offset = mmTPC0_QM_PQ_PI_0;
+		break;
+
+	case GAUDI_QUEUE_ID_TPC_0_1:
+		db_reg_offset = mmTPC0_QM_PQ_PI_1;
+		break;
+
+	case GAUDI_QUEUE_ID_TPC_0_2:
+		db_reg_offset = mmTPC0_QM_PQ_PI_2;
+		break;
+
+	case GAUDI_QUEUE_ID_TPC_0_3:
+		db_reg_offset = mmTPC0_QM_PQ_PI_3;
+		break;
+
+	case GAUDI_QUEUE_ID_TPC_1_0:
+		db_reg_offset = mmTPC1_QM_PQ_PI_0;
+		break;
+
+	case GAUDI_QUEUE_ID_TPC_1_1:
+		db_reg_offset = mmTPC1_QM_PQ_PI_1;
+		break;
+
+	case GAUDI_QUEUE_ID_TPC_1_2:
+		db_reg_offset = mmTPC1_QM_PQ_PI_2;
+		break;
+
+	case GAUDI_QUEUE_ID_TPC_1_3:
+		db_reg_offset = mmTPC1_QM_PQ_PI_3;
+		break;
+
+	case GAUDI_QUEUE_ID_TPC_2_0:
+		db_reg_offset = mmTPC2_QM_PQ_PI_0;
+		break;
+
+	case GAUDI_QUEUE_ID_TPC_2_1:
+		db_reg_offset = mmTPC2_QM_PQ_PI_1;
+		break;
+
+	case GAUDI_QUEUE_ID_TPC_2_2:
+		db_reg_offset = mmTPC2_QM_PQ_PI_2;
+		break;
+
+	case GAUDI_QUEUE_ID_TPC_2_3:
+		db_reg_offset = mmTPC2_QM_PQ_PI_3;
+		break;
+
+	case GAUDI_QUEUE_ID_TPC_3_0:
+		db_reg_offset = mmTPC3_QM_PQ_PI_0;
+		break;
+
+	case GAUDI_QUEUE_ID_TPC_3_1:
+		db_reg_offset = mmTPC3_QM_PQ_PI_1;
+		break;
+
+	case GAUDI_QUEUE_ID_TPC_3_2:
+		db_reg_offset = mmTPC3_QM_PQ_PI_2;
+		break;
+
+	case GAUDI_QUEUE_ID_TPC_3_3:
+		db_reg_offset = mmTPC3_QM_PQ_PI_3;
+		break;
+
+	case GAUDI_QUEUE_ID_TPC_4_0:
+		db_reg_offset = mmTPC4_QM_PQ_PI_0;
+		break;
+
+	case GAUDI_QUEUE_ID_TPC_4_1:
+		db_reg_offset = mmTPC4_QM_PQ_PI_1;
+		break;
+
+	case GAUDI_QUEUE_ID_TPC_4_2:
+		db_reg_offset = mmTPC4_QM_PQ_PI_2;
+		break;
+
+	case GAUDI_QUEUE_ID_TPC_4_3:
+		db_reg_offset = mmTPC4_QM_PQ_PI_3;
+		break;
+
+	case GAUDI_QUEUE_ID_TPC_5_0:
+		db_reg_offset = mmTPC5_QM_PQ_PI_0;
+		break;
+
+	case GAUDI_QUEUE_ID_TPC_5_1:
+		db_reg_offset = mmTPC5_QM_PQ_PI_1;
+		break;
+
+	case GAUDI_QUEUE_ID_TPC_5_2:
+		db_reg_offset = mmTPC5_QM_PQ_PI_2;
+		break;
+
+	case GAUDI_QUEUE_ID_TPC_5_3:
+		db_reg_offset = mmTPC5_QM_PQ_PI_3;
+		break;
+
+	case GAUDI_QUEUE_ID_TPC_6_0:
+		db_reg_offset = mmTPC6_QM_PQ_PI_0;
+		break;
+
+	case GAUDI_QUEUE_ID_TPC_6_1:
+		db_reg_offset = mmTPC6_QM_PQ_PI_1;
+		break;
+
+	case GAUDI_QUEUE_ID_TPC_6_2:
+		db_reg_offset = mmTPC6_QM_PQ_PI_2;
+		break;
+
+	case GAUDI_QUEUE_ID_TPC_6_3:
+		db_reg_offset = mmTPC6_QM_PQ_PI_3;
+		break;
+
+	case GAUDI_QUEUE_ID_TPC_7_0:
+		db_reg_offset = mmTPC7_QM_PQ_PI_0;
+		break;
+
+	case GAUDI_QUEUE_ID_TPC_7_1:
+		db_reg_offset = mmTPC7_QM_PQ_PI_1;
+		break;
+
+	case GAUDI_QUEUE_ID_TPC_7_2:
+		db_reg_offset = mmTPC7_QM_PQ_PI_2;
+		break;
+
+	case GAUDI_QUEUE_ID_TPC_7_3:
+		db_reg_offset = mmTPC7_QM_PQ_PI_3;
+		break;
+
+	case GAUDI_QUEUE_ID_NIC_0_0...GAUDI_QUEUE_ID_NIC_0_3:
+		if (!(gaudi->hw_cap_initialized & HW_CAP_NIC0))
+			invalid_queue = true;
+
+		q_off = ((hw_queue_id - 1) & 0x3) * 4;
+		db_reg_offset = mmNIC0_QM0_PQ_PI_0 + q_off;
+		break;
+
+	case GAUDI_QUEUE_ID_NIC_1_0...GAUDI_QUEUE_ID_NIC_1_3:
+		if (!(gaudi->hw_cap_initialized & HW_CAP_NIC1))
+			invalid_queue = true;
+
+		q_off = ((hw_queue_id - 1) & 0x3) * 4;
+		db_reg_offset = mmNIC0_QM1_PQ_PI_0 + q_off;
+		break;
+
+	case GAUDI_QUEUE_ID_NIC_2_0...GAUDI_QUEUE_ID_NIC_2_3:
+		if (!(gaudi->hw_cap_initialized & HW_CAP_NIC2))
+			invalid_queue = true;
+
+		q_off = ((hw_queue_id - 1) & 0x3) * 4;
+		db_reg_offset = mmNIC1_QM0_PQ_PI_0 + q_off;
+		break;
+
+	case GAUDI_QUEUE_ID_NIC_3_0...GAUDI_QUEUE_ID_NIC_3_3:
+		if (!(gaudi->hw_cap_initialized & HW_CAP_NIC3))
+			invalid_queue = true;
+
+		q_off = ((hw_queue_id - 1) & 0x3) * 4;
+		db_reg_offset = mmNIC1_QM1_PQ_PI_0 + q_off;
+		break;
+
+	case GAUDI_QUEUE_ID_NIC_4_0...GAUDI_QUEUE_ID_NIC_4_3:
+		if (!(gaudi->hw_cap_initialized & HW_CAP_NIC4))
+			invalid_queue = true;
+
+		q_off = ((hw_queue_id - 1) & 0x3) * 4;
+		db_reg_offset = mmNIC2_QM0_PQ_PI_0 + q_off;
+		break;
+
+	case GAUDI_QUEUE_ID_NIC_5_0...GAUDI_QUEUE_ID_NIC_5_3:
+		if (!(gaudi->hw_cap_initialized & HW_CAP_NIC5))
+			invalid_queue = true;
+
+		q_off = ((hw_queue_id - 1) & 0x3) * 4;
+		db_reg_offset = mmNIC2_QM1_PQ_PI_0 + q_off;
+		break;
+
+	case GAUDI_QUEUE_ID_NIC_6_0...GAUDI_QUEUE_ID_NIC_6_3:
+		if (!(gaudi->hw_cap_initialized & HW_CAP_NIC6))
+			invalid_queue = true;
+
+		q_off = ((hw_queue_id - 1) & 0x3) * 4;
+		db_reg_offset = mmNIC3_QM0_PQ_PI_0 + q_off;
+		break;
+
+	case GAUDI_QUEUE_ID_NIC_7_0...GAUDI_QUEUE_ID_NIC_7_3:
+		if (!(gaudi->hw_cap_initialized & HW_CAP_NIC7))
+			invalid_queue = true;
+
+		q_off = ((hw_queue_id - 1) & 0x3) * 4;
+		db_reg_offset = mmNIC3_QM1_PQ_PI_0 + q_off;
+		break;
+
+	case GAUDI_QUEUE_ID_NIC_8_0...GAUDI_QUEUE_ID_NIC_8_3:
+		if (!(gaudi->hw_cap_initialized & HW_CAP_NIC8))
+			invalid_queue = true;
+
+		q_off = ((hw_queue_id - 1) & 0x3) * 4;
+		db_reg_offset = mmNIC4_QM0_PQ_PI_0 + q_off;
+		break;
+
+	case GAUDI_QUEUE_ID_NIC_9_0...GAUDI_QUEUE_ID_NIC_9_3:
+		if (!(gaudi->hw_cap_initialized & HW_CAP_NIC9))
+			invalid_queue = true;
+
+		q_off = ((hw_queue_id - 1) & 0x3) * 4;
+		db_reg_offset = mmNIC4_QM1_PQ_PI_0 + q_off;
+		break;
+
+	default:
+		invalid_queue = true;
+	}
+
+	if (invalid_queue) {
+		/* Should never get here */
+		dev_err(hdev->dev, "h/w queue %d is invalid. Can't set pi\n",
+			hw_queue_id);
+		return;
+	}
+
+	db_value = pi;
+
+	/* ring the doorbell */
+	WREG32(db_reg_offset, db_value);
+
+	if (hw_queue_id == GAUDI_QUEUE_ID_CPU_PQ) {
+		/* make sure device CPU will read latest data from host */
+		mb();
+
+		irq_handler_offset = hdev->asic_prop.gic_interrupts_enable ?
+				mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR :
+				le32_to_cpu(dyn_regs->gic_host_pi_upd_irq);
+
+		WREG32(irq_handler_offset,
+			gaudi_irq_map_table[GAUDI_EVENT_PI_UPDATE].cpu_id);
+	}
+}
+
+static void gaudi_pqe_write(struct hl_device *hdev, __le64 *pqe,
+				struct hl_bd *bd)
+{
+	__le64 *pbd = (__le64 *) bd;
+
+	/* The QMANs are on the host memory so a simple copy suffice */
+	pqe[0] = pbd[0];
+	pqe[1] = pbd[1];
+}
+
+static void *gaudi_dma_alloc_coherent(struct hl_device *hdev, size_t size,
+					dma_addr_t *dma_handle, gfp_t flags)
+{
+	void *kernel_addr = dma_alloc_coherent(&hdev->pdev->dev, size,
+						dma_handle, flags);
+
+	/* Shift to the device's base physical address of host memory */
+	if (kernel_addr)
+		*dma_handle += HOST_PHYS_BASE;
+
+	return kernel_addr;
+}
+
+static void gaudi_dma_free_coherent(struct hl_device *hdev, size_t size,
+		void *cpu_addr, dma_addr_t dma_handle)
+{
+	/* Cancel the device's base physical address of host memory */
+	dma_addr_t fixed_dma_handle = dma_handle - HOST_PHYS_BASE;
+
+	dma_free_coherent(&hdev->pdev->dev, size, cpu_addr, fixed_dma_handle);
+}
+
+static int gaudi_scrub_device_dram(struct hl_device *hdev, u64 val)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	u64 cur_addr = prop->dram_user_base_address;
+	u32 chunk_size, busy;
+	int rc, dma_id;
+
+	while (cur_addr < prop->dram_end_address) {
+		for (dma_id = 0 ; dma_id < DMA_NUMBER_OF_CHANNELS ; dma_id++) {
+			u32 dma_offset = dma_id * DMA_CORE_OFFSET;
+
+			chunk_size =
+			min((u64)SZ_2G, prop->dram_end_address - cur_addr);
+
+			dev_dbg(hdev->dev,
+				"Doing HBM scrubbing for 0x%09llx - 0x%09llx\n",
+				cur_addr, cur_addr + chunk_size);
+
+			WREG32(mmDMA0_CORE_SRC_BASE_LO + dma_offset,
+					lower_32_bits(val));
+			WREG32(mmDMA0_CORE_SRC_BASE_HI + dma_offset,
+					upper_32_bits(val));
+			WREG32(mmDMA0_CORE_DST_BASE_LO + dma_offset,
+						lower_32_bits(cur_addr));
+			WREG32(mmDMA0_CORE_DST_BASE_HI + dma_offset,
+						upper_32_bits(cur_addr));
+			WREG32(mmDMA0_CORE_DST_TSIZE_0 + dma_offset,
+					chunk_size);
+			WREG32(mmDMA0_CORE_COMMIT + dma_offset,
+					((1 << DMA0_CORE_COMMIT_LIN_SHIFT) |
+					(1 << DMA0_CORE_COMMIT_MEM_SET_SHIFT)));
+
+			cur_addr += chunk_size;
+
+			if (cur_addr == prop->dram_end_address)
+				break;
+		}
+
+		for (dma_id = 0 ; dma_id < DMA_NUMBER_OF_CHANNELS ; dma_id++) {
+			u32 dma_offset = dma_id * DMA_CORE_OFFSET;
+
+			rc = hl_poll_timeout(
+				hdev,
+				mmDMA0_CORE_STS0 + dma_offset,
+				busy,
+				((busy & DMA0_CORE_STS0_BUSY_MASK) == 0),
+				1000,
+				HBM_SCRUBBING_TIMEOUT_US);
+
+			if (rc) {
+				dev_err(hdev->dev,
+					"DMA Timeout during HBM scrubbing of DMA #%d\n",
+					dma_id);
+				return -EIO;
+			}
+		}
+	}
+
+	return 0;
+}
+
+static int gaudi_scrub_device_mem(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	u64 wait_to_idle_time = HBM_SCRUBBING_TIMEOUT_US;
+	u64 addr, size, val = hdev->memory_scrub_val;
+	ktime_t timeout;
+	int rc = 0;
+
+	if (!hdev->memory_scrub)
+		return 0;
+
+	timeout = ktime_add_us(ktime_get(), wait_to_idle_time);
+	while (!hdev->asic_funcs->is_device_idle(hdev, NULL, 0, NULL)) {
+		if (ktime_compare(ktime_get(), timeout) > 0) {
+			dev_err(hdev->dev, "waiting for idle timeout\n");
+			return -ETIMEDOUT;
+		}
+		usleep_range((1000 >> 2) + 1, 1000);
+	}
+
+	/* Scrub SRAM */
+	addr = prop->sram_user_base_address;
+	size = hdev->pldm ? 0x10000 : prop->sram_size - SRAM_USER_BASE_OFFSET;
+
+	dev_dbg(hdev->dev, "Scrubbing SRAM: 0x%09llx - 0x%09llx val: 0x%llx\n",
+			addr, addr + size, val);
+	rc = gaudi_memset_device_memory(hdev, addr, size, val);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to clear SRAM (%d)\n", rc);
+		return rc;
+	}
+
+	/* Scrub HBM using all DMA channels in parallel */
+	rc = gaudi_scrub_device_dram(hdev, val);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to clear HBM (%d)\n", rc);
+		return rc;
+	}
+
+	return 0;
+}
+
+static void *gaudi_get_int_queue_base(struct hl_device *hdev,
+				u32 queue_id, dma_addr_t *dma_handle,
+				u16 *queue_len)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+	struct gaudi_internal_qman_info *q;
+
+	if (queue_id >= GAUDI_QUEUE_ID_SIZE ||
+			gaudi_queue_type[queue_id] != QUEUE_TYPE_INT) {
+		dev_err(hdev->dev, "Got invalid queue id %d\n", queue_id);
+		return NULL;
+	}
+
+	q = &gaudi->internal_qmans[queue_id];
+	*dma_handle = q->pq_dma_addr;
+	*queue_len = q->pq_size / QMAN_PQ_ENTRY_SIZE;
+
+	return q->pq_kernel_addr;
+}
+
+static int gaudi_send_cpu_message(struct hl_device *hdev, u32 *msg,
+				u16 len, u32 timeout, u64 *result)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+
+	if (!(gaudi->hw_cap_initialized & HW_CAP_CPU_Q)) {
+		if (result)
+			*result = 0;
+		return 0;
+	}
+
+	if (!timeout)
+		timeout = GAUDI_MSG_TO_CPU_TIMEOUT_USEC;
+
+	return hl_fw_send_cpu_message(hdev, GAUDI_QUEUE_ID_CPU_PQ, msg, len,
+						timeout, result);
+}
+
+static int gaudi_test_queue(struct hl_device *hdev, u32 hw_queue_id)
+{
+	struct packet_msg_prot *fence_pkt;
+	dma_addr_t pkt_dma_addr;
+	u32 fence_val, tmp, timeout_usec;
+	dma_addr_t fence_dma_addr;
+	u32 *fence_ptr;
+	int rc;
+
+	if (hdev->pldm)
+		timeout_usec = GAUDI_PLDM_TEST_QUEUE_WAIT_USEC;
+	else
+		timeout_usec = GAUDI_TEST_QUEUE_WAIT_USEC;
+
+	fence_val = GAUDI_QMAN0_FENCE_VAL;
+
+	fence_ptr = hl_asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL, &fence_dma_addr);
+	if (!fence_ptr) {
+		dev_err(hdev->dev,
+			"Failed to allocate memory for H/W queue %d testing\n",
+			hw_queue_id);
+		return -ENOMEM;
+	}
+
+	*fence_ptr = 0;
+
+	fence_pkt = hl_asic_dma_pool_zalloc(hdev, sizeof(struct packet_msg_prot), GFP_KERNEL,
+						&pkt_dma_addr);
+	if (!fence_pkt) {
+		dev_err(hdev->dev,
+			"Failed to allocate packet for H/W queue %d testing\n",
+			hw_queue_id);
+		rc = -ENOMEM;
+		goto free_fence_ptr;
+	}
+
+	tmp = FIELD_PREP(GAUDI_PKT_CTL_OPCODE_MASK, PACKET_MSG_PROT);
+	tmp |= FIELD_PREP(GAUDI_PKT_CTL_EB_MASK, 1);
+	tmp |= FIELD_PREP(GAUDI_PKT_CTL_MB_MASK, 1);
+
+	fence_pkt->ctl = cpu_to_le32(tmp);
+	fence_pkt->value = cpu_to_le32(fence_val);
+	fence_pkt->addr = cpu_to_le64(fence_dma_addr);
+
+	rc = hl_hw_queue_send_cb_no_cmpl(hdev, hw_queue_id,
+					sizeof(struct packet_msg_prot),
+					pkt_dma_addr);
+	if (rc) {
+		dev_err(hdev->dev,
+			"Failed to send fence packet to H/W queue %d\n",
+			hw_queue_id);
+		goto free_pkt;
+	}
+
+	rc = hl_poll_timeout_memory(hdev, fence_ptr, tmp, (tmp == fence_val),
+					1000, timeout_usec, true);
+
+	hl_hw_queue_inc_ci_kernel(hdev, hw_queue_id);
+
+	if (rc == -ETIMEDOUT) {
+		dev_err(hdev->dev,
+			"H/W queue %d test failed (scratch(0x%08llX) == 0x%08X)\n",
+			hw_queue_id, (unsigned long long) fence_dma_addr, tmp);
+		rc = -EIO;
+	}
+
+free_pkt:
+	hl_asic_dma_pool_free(hdev, (void *) fence_pkt, pkt_dma_addr);
+free_fence_ptr:
+	hl_asic_dma_pool_free(hdev, (void *) fence_ptr, fence_dma_addr);
+	return rc;
+}
+
+static int gaudi_test_cpu_queue(struct hl_device *hdev)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+
+	/*
+	 * check capability here as send_cpu_message() won't update the result
+	 * value if no capability
+	 */
+	if (!(gaudi->hw_cap_initialized & HW_CAP_CPU_Q))
+		return 0;
+
+	return hl_fw_test_cpu_queue(hdev);
+}
+
+static int gaudi_test_queues(struct hl_device *hdev)
+{
+	int i, rc, ret_val = 0;
+
+	for (i = 0 ; i < hdev->asic_prop.max_queues ; i++) {
+		if (hdev->asic_prop.hw_queues_props[i].type == QUEUE_TYPE_EXT) {
+			rc = gaudi_test_queue(hdev, i);
+			if (rc)
+				ret_val = -EINVAL;
+		}
+	}
+
+	rc = gaudi_test_cpu_queue(hdev);
+	if (rc)
+		ret_val = -EINVAL;
+
+	return ret_val;
+}
+
+static void *gaudi_dma_pool_zalloc(struct hl_device *hdev, size_t size,
+		gfp_t mem_flags, dma_addr_t *dma_handle)
+{
+	void *kernel_addr;
+
+	if (size > GAUDI_DMA_POOL_BLK_SIZE)
+		return NULL;
+
+	kernel_addr = dma_pool_zalloc(hdev->dma_pool, mem_flags, dma_handle);
+
+	/* Shift to the device's base physical address of host memory */
+	if (kernel_addr)
+		*dma_handle += HOST_PHYS_BASE;
+
+	return kernel_addr;
+}
+
+static void gaudi_dma_pool_free(struct hl_device *hdev, void *vaddr,
+			dma_addr_t dma_addr)
+{
+	/* Cancel the device's base physical address of host memory */
+	dma_addr_t fixed_dma_addr = dma_addr - HOST_PHYS_BASE;
+
+	dma_pool_free(hdev->dma_pool, vaddr, fixed_dma_addr);
+}
+
+static void *gaudi_cpu_accessible_dma_pool_alloc(struct hl_device *hdev,
+					size_t size, dma_addr_t *dma_handle)
+{
+	return hl_fw_cpu_accessible_dma_pool_alloc(hdev, size, dma_handle);
+}
+
+static void gaudi_cpu_accessible_dma_pool_free(struct hl_device *hdev,
+						size_t size, void *vaddr)
+{
+	hl_fw_cpu_accessible_dma_pool_free(hdev, size, vaddr);
+}
+
+static u32 gaudi_get_dma_desc_list_size(struct hl_device *hdev, struct sg_table *sgt)
+{
+	struct scatterlist *sg, *sg_next_iter;
+	u32 count, dma_desc_cnt;
+	u64 len, len_next;
+	dma_addr_t addr, addr_next;
+
+	dma_desc_cnt = 0;
+
+	for_each_sgtable_dma_sg(sgt, sg, count) {
+		len = sg_dma_len(sg);
+		addr = sg_dma_address(sg);
+
+		if (len == 0)
+			break;
+
+		while ((count + 1) < sgt->nents) {
+			sg_next_iter = sg_next(sg);
+			len_next = sg_dma_len(sg_next_iter);
+			addr_next = sg_dma_address(sg_next_iter);
+
+			if (len_next == 0)
+				break;
+
+			if ((addr + len == addr_next) &&
+				(len + len_next <= DMA_MAX_TRANSFER_SIZE)) {
+				len += len_next;
+				count++;
+				sg = sg_next_iter;
+			} else {
+				break;
+			}
+		}
+
+		dma_desc_cnt++;
+	}
+
+	return dma_desc_cnt * sizeof(struct packet_lin_dma);
+}
+
+static int gaudi_pin_memory_before_cs(struct hl_device *hdev,
+				struct hl_cs_parser *parser,
+				struct packet_lin_dma *user_dma_pkt,
+				u64 addr, enum dma_data_direction dir)
+{
+	struct hl_userptr *userptr;
+	int rc;
+
+	if (hl_userptr_is_pinned(hdev, addr, le32_to_cpu(user_dma_pkt->tsize),
+			parser->job_userptr_list, &userptr))
+		goto already_pinned;
+
+	userptr = kzalloc(sizeof(*userptr), GFP_KERNEL);
+	if (!userptr)
+		return -ENOMEM;
+
+	rc = hl_pin_host_memory(hdev, addr, le32_to_cpu(user_dma_pkt->tsize),
+				userptr);
+	if (rc)
+		goto free_userptr;
+
+	list_add_tail(&userptr->job_node, parser->job_userptr_list);
+
+	rc = hl_dma_map_sgtable(hdev, userptr->sgt, dir);
+	if (rc) {
+		dev_err(hdev->dev, "failed to map sgt with DMA region\n");
+		goto unpin_memory;
+	}
+
+	userptr->dma_mapped = true;
+	userptr->dir = dir;
+
+already_pinned:
+	parser->patched_cb_size +=
+			gaudi_get_dma_desc_list_size(hdev, userptr->sgt);
+
+	return 0;
+
+unpin_memory:
+	list_del(&userptr->job_node);
+	hl_unpin_host_memory(hdev, userptr);
+free_userptr:
+	kfree(userptr);
+	return rc;
+}
+
+static int gaudi_validate_dma_pkt_host(struct hl_device *hdev,
+				struct hl_cs_parser *parser,
+				struct packet_lin_dma *user_dma_pkt,
+				bool src_in_host)
+{
+	enum dma_data_direction dir;
+	bool skip_host_mem_pin = false, user_memset;
+	u64 addr;
+	int rc = 0;
+
+	user_memset = (le32_to_cpu(user_dma_pkt->ctl) &
+			GAUDI_PKT_LIN_DMA_CTL_MEMSET_MASK) >>
+			GAUDI_PKT_LIN_DMA_CTL_MEMSET_SHIFT;
+
+	if (src_in_host) {
+		if (user_memset)
+			skip_host_mem_pin = true;
+
+		dev_dbg(hdev->dev, "DMA direction is HOST --> DEVICE\n");
+		dir = DMA_TO_DEVICE;
+		addr = le64_to_cpu(user_dma_pkt->src_addr);
+	} else {
+		dev_dbg(hdev->dev, "DMA direction is DEVICE --> HOST\n");
+		dir = DMA_FROM_DEVICE;
+		addr = (le64_to_cpu(user_dma_pkt->dst_addr) &
+				GAUDI_PKT_LIN_DMA_DST_ADDR_MASK) >>
+				GAUDI_PKT_LIN_DMA_DST_ADDR_SHIFT;
+	}
+
+	if (skip_host_mem_pin)
+		parser->patched_cb_size += sizeof(*user_dma_pkt);
+	else
+		rc = gaudi_pin_memory_before_cs(hdev, parser, user_dma_pkt,
+						addr, dir);
+
+	return rc;
+}
+
+static int gaudi_validate_dma_pkt_no_mmu(struct hl_device *hdev,
+				struct hl_cs_parser *parser,
+				struct packet_lin_dma *user_dma_pkt)
+{
+	bool src_in_host = false;
+	u64 dst_addr = (le64_to_cpu(user_dma_pkt->dst_addr) &
+			GAUDI_PKT_LIN_DMA_DST_ADDR_MASK) >>
+			GAUDI_PKT_LIN_DMA_DST_ADDR_SHIFT;
+
+	dev_dbg(hdev->dev, "DMA packet details:\n");
+	dev_dbg(hdev->dev, "source == 0x%llx\n",
+				le64_to_cpu(user_dma_pkt->src_addr));
+	dev_dbg(hdev->dev, "destination == 0x%llx\n", dst_addr);
+	dev_dbg(hdev->dev, "size == %u\n", le32_to_cpu(user_dma_pkt->tsize));
+
+	/*
+	 * Special handling for DMA with size 0. Bypass all validations
+	 * because no transactions will be done except for WR_COMP, which
+	 * is not a security issue
+	 */
+	if (!le32_to_cpu(user_dma_pkt->tsize)) {
+		parser->patched_cb_size += sizeof(*user_dma_pkt);
+		return 0;
+	}
+
+	if (parser->hw_queue_id <= GAUDI_QUEUE_ID_DMA_0_3)
+		src_in_host = true;
+
+	return gaudi_validate_dma_pkt_host(hdev, parser, user_dma_pkt,
+						src_in_host);
+}
+
+static int gaudi_validate_load_and_exe_pkt(struct hl_device *hdev,
+					struct hl_cs_parser *parser,
+					struct packet_load_and_exe *user_pkt)
+{
+	u32 cfg;
+
+	cfg = le32_to_cpu(user_pkt->cfg);
+
+	if (cfg & GAUDI_PKT_LOAD_AND_EXE_CFG_DST_MASK) {
+		dev_err(hdev->dev,
+			"User not allowed to use Load and Execute\n");
+		return -EPERM;
+	}
+
+	parser->patched_cb_size += sizeof(struct packet_load_and_exe);
+
+	return 0;
+}
+
+static int gaudi_validate_cb(struct hl_device *hdev,
+			struct hl_cs_parser *parser, bool is_mmu)
+{
+	u32 cb_parsed_length = 0;
+	int rc = 0;
+
+	parser->patched_cb_size = 0;
+
+	/* cb_user_size is more than 0 so loop will always be executed */
+	while (cb_parsed_length < parser->user_cb_size) {
+		enum packet_id pkt_id;
+		u16 pkt_size;
+		struct gaudi_packet *user_pkt;
+
+		user_pkt = parser->user_cb->kernel_address + cb_parsed_length;
+
+		pkt_id = (enum packet_id) (
+				(le64_to_cpu(user_pkt->header) &
+				PACKET_HEADER_PACKET_ID_MASK) >>
+					PACKET_HEADER_PACKET_ID_SHIFT);
+
+		if (!validate_packet_id(pkt_id)) {
+			dev_err(hdev->dev, "Invalid packet id %u\n", pkt_id);
+			rc = -EINVAL;
+			break;
+		}
+
+		pkt_size = gaudi_packet_sizes[pkt_id];
+		cb_parsed_length += pkt_size;
+		if (cb_parsed_length > parser->user_cb_size) {
+			dev_err(hdev->dev,
+				"packet 0x%x is out of CB boundary\n", pkt_id);
+			rc = -EINVAL;
+			break;
+		}
+
+		switch (pkt_id) {
+		case PACKET_MSG_PROT:
+			dev_err(hdev->dev,
+				"User not allowed to use MSG_PROT\n");
+			rc = -EPERM;
+			break;
+
+		case PACKET_CP_DMA:
+			dev_err(hdev->dev, "User not allowed to use CP_DMA\n");
+			rc = -EPERM;
+			break;
+
+		case PACKET_STOP:
+			dev_err(hdev->dev, "User not allowed to use STOP\n");
+			rc = -EPERM;
+			break;
+
+		case PACKET_WREG_BULK:
+			dev_err(hdev->dev,
+				"User not allowed to use WREG_BULK\n");
+			rc = -EPERM;
+			break;
+
+		case PACKET_LOAD_AND_EXE:
+			rc = gaudi_validate_load_and_exe_pkt(hdev, parser,
+				(struct packet_load_and_exe *) user_pkt);
+			break;
+
+		case PACKET_LIN_DMA:
+			parser->contains_dma_pkt = true;
+			if (is_mmu)
+				parser->patched_cb_size += pkt_size;
+			else
+				rc = gaudi_validate_dma_pkt_no_mmu(hdev, parser,
+					(struct packet_lin_dma *) user_pkt);
+			break;
+
+		case PACKET_WREG_32:
+		case PACKET_MSG_LONG:
+		case PACKET_MSG_SHORT:
+		case PACKET_REPEAT:
+		case PACKET_FENCE:
+		case PACKET_NOP:
+		case PACKET_ARB_POINT:
+			parser->patched_cb_size += pkt_size;
+			break;
+
+		default:
+			dev_err(hdev->dev, "Invalid packet header 0x%x\n",
+				pkt_id);
+			rc = -EINVAL;
+			break;
+		}
+
+		if (rc)
+			break;
+	}
+
+	/*
+	 * The new CB should have space at the end for two MSG_PROT packets:
+	 * 1. Optional NOP padding for cacheline alignment
+	 * 2. A packet that will act as a completion packet
+	 * 3. A packet that will generate MSI interrupt
+	 */
+	if (parser->completion)
+		parser->patched_cb_size += gaudi_get_patched_cb_extra_size(
+			parser->patched_cb_size);
+
+	return rc;
+}
+
+static int gaudi_patch_dma_packet(struct hl_device *hdev,
+				struct hl_cs_parser *parser,
+				struct packet_lin_dma *user_dma_pkt,
+				struct packet_lin_dma *new_dma_pkt,
+				u32 *new_dma_pkt_size)
+{
+	struct hl_userptr *userptr;
+	struct scatterlist *sg, *sg_next_iter;
+	u32 count, dma_desc_cnt, user_wrcomp_en_mask, ctl;
+	u64 len, len_next;
+	dma_addr_t dma_addr, dma_addr_next;
+	u64 device_memory_addr, addr;
+	enum dma_data_direction dir;
+	struct sg_table *sgt;
+	bool src_in_host = false;
+	bool skip_host_mem_pin = false;
+	bool user_memset;
+
+	ctl = le32_to_cpu(user_dma_pkt->ctl);
+
+	if (parser->hw_queue_id <= GAUDI_QUEUE_ID_DMA_0_3)
+		src_in_host = true;
+
+	user_memset = (ctl & GAUDI_PKT_LIN_DMA_CTL_MEMSET_MASK) >>
+			GAUDI_PKT_LIN_DMA_CTL_MEMSET_SHIFT;
+
+	if (src_in_host) {
+		addr = le64_to_cpu(user_dma_pkt->src_addr);
+		device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
+		dir = DMA_TO_DEVICE;
+		if (user_memset)
+			skip_host_mem_pin = true;
+	} else {
+		addr = le64_to_cpu(user_dma_pkt->dst_addr);
+		device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
+		dir = DMA_FROM_DEVICE;
+	}
+
+	if ((!skip_host_mem_pin) &&
+		(!hl_userptr_is_pinned(hdev, addr,
+					le32_to_cpu(user_dma_pkt->tsize),
+					parser->job_userptr_list, &userptr))) {
+		dev_err(hdev->dev, "Userptr 0x%llx + 0x%x NOT mapped\n",
+				addr, user_dma_pkt->tsize);
+		return -EFAULT;
+	}
+
+	if ((user_memset) && (dir == DMA_TO_DEVICE)) {
+		memcpy(new_dma_pkt, user_dma_pkt, sizeof(*user_dma_pkt));
+		*new_dma_pkt_size = sizeof(*user_dma_pkt);
+		return 0;
+	}
+
+	user_wrcomp_en_mask = ctl & GAUDI_PKT_LIN_DMA_CTL_WRCOMP_EN_MASK;
+
+	sgt = userptr->sgt;
+	dma_desc_cnt = 0;
+
+	for_each_sgtable_dma_sg(sgt, sg, count) {
+		len = sg_dma_len(sg);
+		dma_addr = sg_dma_address(sg);
+
+		if (len == 0)
+			break;
+
+		while ((count + 1) < sgt->nents) {
+			sg_next_iter = sg_next(sg);
+			len_next = sg_dma_len(sg_next_iter);
+			dma_addr_next = sg_dma_address(sg_next_iter);
+
+			if (len_next == 0)
+				break;
+
+			if ((dma_addr + len == dma_addr_next) &&
+				(len + len_next <= DMA_MAX_TRANSFER_SIZE)) {
+				len += len_next;
+				count++;
+				sg = sg_next_iter;
+			} else {
+				break;
+			}
+		}
+
+		ctl = le32_to_cpu(user_dma_pkt->ctl);
+		if (likely(dma_desc_cnt))
+			ctl &= ~GAUDI_PKT_CTL_EB_MASK;
+		ctl &= ~GAUDI_PKT_LIN_DMA_CTL_WRCOMP_EN_MASK;
+		new_dma_pkt->ctl = cpu_to_le32(ctl);
+		new_dma_pkt->tsize = cpu_to_le32(len);
+
+		if (dir == DMA_TO_DEVICE) {
+			new_dma_pkt->src_addr = cpu_to_le64(dma_addr);
+			new_dma_pkt->dst_addr = cpu_to_le64(device_memory_addr);
+		} else {
+			new_dma_pkt->src_addr = cpu_to_le64(device_memory_addr);
+			new_dma_pkt->dst_addr = cpu_to_le64(dma_addr);
+		}
+
+		if (!user_memset)
+			device_memory_addr += len;
+		dma_desc_cnt++;
+		new_dma_pkt++;
+	}
+
+	if (!dma_desc_cnt) {
+		dev_err(hdev->dev,
+			"Error of 0 SG entries when patching DMA packet\n");
+		return -EFAULT;
+	}
+
+	/* Fix the last dma packet - wrcomp must be as user set it */
+	new_dma_pkt--;
+	new_dma_pkt->ctl |= cpu_to_le32(user_wrcomp_en_mask);
+
+	*new_dma_pkt_size = dma_desc_cnt * sizeof(struct packet_lin_dma);
+
+	return 0;
+}
+
+static int gaudi_patch_cb(struct hl_device *hdev,
+				struct hl_cs_parser *parser)
+{
+	u32 cb_parsed_length = 0;
+	u32 cb_patched_cur_length = 0;
+	int rc = 0;
+
+	/* cb_user_size is more than 0 so loop will always be executed */
+	while (cb_parsed_length < parser->user_cb_size) {
+		enum packet_id pkt_id;
+		u16 pkt_size;
+		u32 new_pkt_size = 0;
+		struct gaudi_packet *user_pkt, *kernel_pkt;
+
+		user_pkt = parser->user_cb->kernel_address + cb_parsed_length;
+		kernel_pkt = parser->patched_cb->kernel_address +
+					cb_patched_cur_length;
+
+		pkt_id = (enum packet_id) (
+				(le64_to_cpu(user_pkt->header) &
+				PACKET_HEADER_PACKET_ID_MASK) >>
+					PACKET_HEADER_PACKET_ID_SHIFT);
+
+		if (!validate_packet_id(pkt_id)) {
+			dev_err(hdev->dev, "Invalid packet id %u\n", pkt_id);
+			rc = -EINVAL;
+			break;
+		}
+
+		pkt_size = gaudi_packet_sizes[pkt_id];
+		cb_parsed_length += pkt_size;
+		if (cb_parsed_length > parser->user_cb_size) {
+			dev_err(hdev->dev,
+				"packet 0x%x is out of CB boundary\n", pkt_id);
+			rc = -EINVAL;
+			break;
+		}
+
+		switch (pkt_id) {
+		case PACKET_LIN_DMA:
+			rc = gaudi_patch_dma_packet(hdev, parser,
+					(struct packet_lin_dma *) user_pkt,
+					(struct packet_lin_dma *) kernel_pkt,
+					&new_pkt_size);
+			cb_patched_cur_length += new_pkt_size;
+			break;
+
+		case PACKET_MSG_PROT:
+			dev_err(hdev->dev,
+				"User not allowed to use MSG_PROT\n");
+			rc = -EPERM;
+			break;
+
+		case PACKET_CP_DMA:
+			dev_err(hdev->dev, "User not allowed to use CP_DMA\n");
+			rc = -EPERM;
+			break;
+
+		case PACKET_STOP:
+			dev_err(hdev->dev, "User not allowed to use STOP\n");
+			rc = -EPERM;
+			break;
+
+		case PACKET_WREG_32:
+		case PACKET_WREG_BULK:
+		case PACKET_MSG_LONG:
+		case PACKET_MSG_SHORT:
+		case PACKET_REPEAT:
+		case PACKET_FENCE:
+		case PACKET_NOP:
+		case PACKET_ARB_POINT:
+		case PACKET_LOAD_AND_EXE:
+			memcpy(kernel_pkt, user_pkt, pkt_size);
+			cb_patched_cur_length += pkt_size;
+			break;
+
+		default:
+			dev_err(hdev->dev, "Invalid packet header 0x%x\n",
+				pkt_id);
+			rc = -EINVAL;
+			break;
+		}
+
+		if (rc)
+			break;
+	}
+
+	return rc;
+}
+
+static int gaudi_parse_cb_mmu(struct hl_device *hdev,
+		struct hl_cs_parser *parser)
+{
+	u64 handle;
+	u32 patched_cb_size;
+	struct hl_cb *user_cb;
+	int rc;
+
+	/*
+	 * The new CB should have space at the end for two MSG_PROT packets:
+	 * 1. Optional NOP padding for cacheline alignment
+	 * 2. A packet that will act as a completion packet
+	 * 3. A packet that will generate MSI interrupt
+	 */
+	if (parser->completion)
+		parser->patched_cb_size = parser->user_cb_size +
+				gaudi_get_patched_cb_extra_size(parser->user_cb_size);
+	else
+		parser->patched_cb_size = parser->user_cb_size;
+
+	rc = hl_cb_create(hdev, &hdev->kernel_mem_mgr, hdev->kernel_ctx,
+				parser->patched_cb_size, false, false,
+				&handle);
+
+	if (rc) {
+		dev_err(hdev->dev,
+			"Failed to allocate patched CB for DMA CS %d\n",
+			rc);
+		return rc;
+	}
+
+	parser->patched_cb = hl_cb_get(&hdev->kernel_mem_mgr, handle);
+	/* hl_cb_get should never fail */
+	if (!parser->patched_cb) {
+		dev_crit(hdev->dev, "DMA CB handle invalid 0x%llx\n", handle);
+		rc = -EFAULT;
+		goto out;
+	}
+
+	/*
+	 * We are protected from overflow because the check
+	 * "parser->user_cb_size <= parser->user_cb->size" was done in get_cb_from_cs_chunk()
+	 * in the common code. That check is done only if is_kernel_allocated_cb is true.
+	 *
+	 * There is no option to reach here without going through that check because:
+	 * 1. validate_queue_index() assigns true to is_kernel_allocated_cb for any submission to
+	 *    an external queue.
+	 * 2. For Gaudi, we only parse CBs that were submitted to the external queues.
+	 */
+	memcpy(parser->patched_cb->kernel_address,
+		parser->user_cb->kernel_address,
+		parser->user_cb_size);
+
+	patched_cb_size = parser->patched_cb_size;
+
+	/* Validate patched CB instead of user CB */
+	user_cb = parser->user_cb;
+	parser->user_cb = parser->patched_cb;
+	rc = gaudi_validate_cb(hdev, parser, true);
+	parser->user_cb = user_cb;
+
+	if (rc) {
+		hl_cb_put(parser->patched_cb);
+		goto out;
+	}
+
+	if (patched_cb_size != parser->patched_cb_size) {
+		dev_err(hdev->dev, "user CB size mismatch\n");
+		hl_cb_put(parser->patched_cb);
+		rc = -EINVAL;
+		goto out;
+	}
+
+out:
+	/*
+	 * Always call cb destroy here because we still have 1 reference
+	 * to it by calling cb_get earlier. After the job will be completed,
+	 * cb_put will release it, but here we want to remove it from the
+	 * idr
+	 */
+	hl_cb_destroy(&hdev->kernel_mem_mgr, handle);
+
+	return rc;
+}
+
+static int gaudi_parse_cb_no_mmu(struct hl_device *hdev,
+		struct hl_cs_parser *parser)
+{
+	u64 handle;
+	int rc;
+
+	rc = gaudi_validate_cb(hdev, parser, false);
+
+	if (rc)
+		goto free_userptr;
+
+	rc = hl_cb_create(hdev, &hdev->kernel_mem_mgr, hdev->kernel_ctx,
+				parser->patched_cb_size, false, false,
+				&handle);
+	if (rc) {
+		dev_err(hdev->dev,
+			"Failed to allocate patched CB for DMA CS %d\n", rc);
+		goto free_userptr;
+	}
+
+	parser->patched_cb = hl_cb_get(&hdev->kernel_mem_mgr, handle);
+	/* hl_cb_get should never fail here */
+	if (!parser->patched_cb) {
+		dev_crit(hdev->dev, "DMA CB handle invalid 0x%llx\n", handle);
+		rc = -EFAULT;
+		goto out;
+	}
+
+	rc = gaudi_patch_cb(hdev, parser);
+
+	if (rc)
+		hl_cb_put(parser->patched_cb);
+
+out:
+	/*
+	 * Always call cb destroy here because we still have 1 reference
+	 * to it by calling cb_get earlier. After the job will be completed,
+	 * cb_put will release it, but here we want to remove it from the
+	 * idr
+	 */
+	hl_cb_destroy(&hdev->kernel_mem_mgr, handle);
+
+free_userptr:
+	if (rc)
+		hl_userptr_delete_list(hdev, parser->job_userptr_list);
+	return rc;
+}
+
+static int gaudi_parse_cb_no_ext_queue(struct hl_device *hdev,
+					struct hl_cs_parser *parser)
+{
+	struct asic_fixed_properties *asic_prop = &hdev->asic_prop;
+	struct gaudi_device *gaudi = hdev->asic_specific;
+	u32 nic_queue_offset, nic_mask_q_id;
+
+	if ((parser->hw_queue_id >= GAUDI_QUEUE_ID_NIC_0_0) &&
+			(parser->hw_queue_id <= GAUDI_QUEUE_ID_NIC_9_3)) {
+		nic_queue_offset = parser->hw_queue_id - GAUDI_QUEUE_ID_NIC_0_0;
+		nic_mask_q_id = 1 << (HW_CAP_NIC_SHIFT + (nic_queue_offset >> 2));
+
+		if (!(gaudi->hw_cap_initialized & nic_mask_q_id)) {
+			dev_err(hdev->dev, "h/w queue %d is disabled\n", parser->hw_queue_id);
+			return -EINVAL;
+		}
+	}
+
+	/* For internal queue jobs just check if CB address is valid */
+	if (hl_mem_area_inside_range((u64) (uintptr_t) parser->user_cb,
+					parser->user_cb_size,
+					asic_prop->sram_user_base_address,
+					asic_prop->sram_end_address))
+		return 0;
+
+	if (hl_mem_area_inside_range((u64) (uintptr_t) parser->user_cb,
+					parser->user_cb_size,
+					asic_prop->dram_user_base_address,
+					asic_prop->dram_end_address))
+		return 0;
+
+	/* PMMU and HPMMU addresses are equal, check only one of them */
+	if (hl_mem_area_inside_range((u64) (uintptr_t) parser->user_cb,
+					parser->user_cb_size,
+					asic_prop->pmmu.start_addr,
+					asic_prop->pmmu.end_addr))
+		return 0;
+
+	dev_err(hdev->dev,
+		"CB address 0x%px + 0x%x for internal QMAN is not valid\n",
+		parser->user_cb, parser->user_cb_size);
+
+	return -EFAULT;
+}
+
+static int gaudi_cs_parser(struct hl_device *hdev, struct hl_cs_parser *parser)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+
+	if (parser->queue_type == QUEUE_TYPE_INT)
+		return gaudi_parse_cb_no_ext_queue(hdev, parser);
+
+	if (gaudi->hw_cap_initialized & HW_CAP_MMU)
+		return gaudi_parse_cb_mmu(hdev, parser);
+	else
+		return gaudi_parse_cb_no_mmu(hdev, parser);
+}
+
+static void gaudi_add_end_of_cb_packets(struct hl_device *hdev, void *kernel_address,
+				u32 len, u32 original_len, u64 cq_addr, u32 cq_val,
+				u32 msi_vec, bool eb)
+{
+	struct packet_msg_prot *cq_pkt;
+	struct packet_nop *cq_padding;
+	u64 msi_addr;
+	u32 tmp;
+
+	cq_padding = kernel_address + original_len;
+	cq_pkt = kernel_address + len - (sizeof(struct packet_msg_prot) * 2);
+
+	while ((void *)cq_padding < (void *)cq_pkt) {
+		cq_padding->ctl = cpu_to_le32(FIELD_PREP(GAUDI_PKT_CTL_OPCODE_MASK, PACKET_NOP));
+		cq_padding++;
+	}
+
+	tmp = FIELD_PREP(GAUDI_PKT_CTL_OPCODE_MASK, PACKET_MSG_PROT);
+	tmp |= FIELD_PREP(GAUDI_PKT_CTL_MB_MASK, 1);
+
+	if (eb)
+		tmp |= FIELD_PREP(GAUDI_PKT_CTL_EB_MASK, 1);
+
+	cq_pkt->ctl = cpu_to_le32(tmp);
+	cq_pkt->value = cpu_to_le32(cq_val);
+	cq_pkt->addr = cpu_to_le64(cq_addr);
+
+	cq_pkt++;
+
+	tmp = FIELD_PREP(GAUDI_PKT_CTL_OPCODE_MASK, PACKET_MSG_PROT);
+	tmp |= FIELD_PREP(GAUDI_PKT_CTL_MB_MASK, 1);
+	cq_pkt->ctl = cpu_to_le32(tmp);
+	cq_pkt->value = cpu_to_le32(1);
+	msi_addr = hdev->pdev ? mmPCIE_CORE_MSI_REQ : mmPCIE_MSI_INTR_0 + msi_vec * 4;
+	cq_pkt->addr = cpu_to_le64(CFG_BASE + msi_addr);
+}
+
+static void gaudi_update_eq_ci(struct hl_device *hdev, u32 val)
+{
+	WREG32(mmCPU_IF_EQ_RD_OFFS, val);
+}
+
+static int gaudi_memset_device_memory(struct hl_device *hdev, u64 addr,
+					u32 size, u64 val)
+{
+	struct packet_lin_dma *lin_dma_pkt;
+	struct hl_cs_job *job;
+	u32 cb_size, ctl, err_cause;
+	struct hl_cb *cb;
+	int rc;
+
+	cb = hl_cb_kernel_create(hdev, PAGE_SIZE, false);
+	if (!cb)
+		return -EFAULT;
+
+	lin_dma_pkt = cb->kernel_address;
+	memset(lin_dma_pkt, 0, sizeof(*lin_dma_pkt));
+	cb_size = sizeof(*lin_dma_pkt);
+
+	ctl = FIELD_PREP(GAUDI_PKT_CTL_OPCODE_MASK, PACKET_LIN_DMA);
+	ctl |= FIELD_PREP(GAUDI_PKT_LIN_DMA_CTL_MEMSET_MASK, 1);
+	ctl |= FIELD_PREP(GAUDI_PKT_LIN_DMA_CTL_LIN_MASK, 1);
+	ctl |= FIELD_PREP(GAUDI_PKT_CTL_MB_MASK, 1);
+	ctl |= FIELD_PREP(GAUDI_PKT_CTL_RB_MASK, 1);
+
+	lin_dma_pkt->ctl = cpu_to_le32(ctl);
+	lin_dma_pkt->src_addr = cpu_to_le64(val);
+	lin_dma_pkt->dst_addr |= cpu_to_le64(addr);
+	lin_dma_pkt->tsize = cpu_to_le32(size);
+
+	job = hl_cs_allocate_job(hdev, QUEUE_TYPE_EXT, true);
+	if (!job) {
+		dev_err(hdev->dev, "Failed to allocate a new job\n");
+		rc = -ENOMEM;
+		goto release_cb;
+	}
+
+	/* Verify DMA is OK */
+	err_cause = RREG32(mmDMA0_CORE_ERR_CAUSE);
+	if (err_cause && !hdev->init_done) {
+		dev_dbg(hdev->dev,
+			"Clearing DMA0 engine from errors (cause 0x%x)\n",
+			err_cause);
+		WREG32(mmDMA0_CORE_ERR_CAUSE, err_cause);
+	}
+
+	job->id = 0;
+	job->user_cb = cb;
+	atomic_inc(&job->user_cb->cs_cnt);
+	job->user_cb_size = cb_size;
+	job->hw_queue_id = GAUDI_QUEUE_ID_DMA_0_0;
+	job->patched_cb = job->user_cb;
+	job->job_cb_size = job->user_cb_size + sizeof(struct packet_msg_prot);
+
+	hl_debugfs_add_job(hdev, job);
+
+	rc = gaudi_send_job_on_qman0(hdev, job);
+	hl_debugfs_remove_job(hdev, job);
+	kfree(job);
+	atomic_dec(&cb->cs_cnt);
+
+	/* Verify DMA is OK */
+	err_cause = RREG32(mmDMA0_CORE_ERR_CAUSE);
+	if (err_cause) {
+		dev_err(hdev->dev, "DMA Failed, cause 0x%x\n", err_cause);
+		rc = -EIO;
+		if (!hdev->init_done) {
+			dev_dbg(hdev->dev,
+				"Clearing DMA0 engine from errors (cause 0x%x)\n",
+				err_cause);
+			WREG32(mmDMA0_CORE_ERR_CAUSE, err_cause);
+		}
+	}
+
+release_cb:
+	hl_cb_put(cb);
+	hl_cb_destroy(&hdev->kernel_mem_mgr, cb->buf->handle);
+
+	return rc;
+}
+
+static int gaudi_memset_registers(struct hl_device *hdev, u64 reg_base,
+					u32 num_regs, u32 val)
+{
+	struct packet_msg_long *pkt;
+	struct hl_cs_job *job;
+	u32 cb_size, ctl;
+	struct hl_cb *cb;
+	int i, rc;
+
+	cb_size = (sizeof(*pkt) * num_regs) + sizeof(struct packet_msg_prot);
+
+	if (cb_size > SZ_2M) {
+		dev_err(hdev->dev, "CB size must be smaller than %uMB", SZ_2M);
+		return -ENOMEM;
+	}
+
+	cb = hl_cb_kernel_create(hdev, cb_size, false);
+	if (!cb)
+		return -EFAULT;
+
+	pkt = cb->kernel_address;
+
+	ctl = FIELD_PREP(GAUDI_PKT_LONG_CTL_OP_MASK, 0); /* write the value */
+	ctl |= FIELD_PREP(GAUDI_PKT_CTL_OPCODE_MASK, PACKET_MSG_LONG);
+	ctl |= FIELD_PREP(GAUDI_PKT_CTL_EB_MASK, 1);
+	ctl |= FIELD_PREP(GAUDI_PKT_CTL_RB_MASK, 1);
+	ctl |= FIELD_PREP(GAUDI_PKT_CTL_MB_MASK, 1);
+
+	for (i = 0; i < num_regs ; i++, pkt++) {
+		pkt->ctl = cpu_to_le32(ctl);
+		pkt->value = cpu_to_le32(val);
+		pkt->addr = cpu_to_le64(reg_base + (i * 4));
+	}
+
+	job = hl_cs_allocate_job(hdev, QUEUE_TYPE_EXT, true);
+	if (!job) {
+		dev_err(hdev->dev, "Failed to allocate a new job\n");
+		rc = -ENOMEM;
+		goto release_cb;
+	}
+
+	job->id = 0;
+	job->user_cb = cb;
+	atomic_inc(&job->user_cb->cs_cnt);
+	job->user_cb_size = cb_size;
+	job->hw_queue_id = GAUDI_QUEUE_ID_DMA_0_0;
+	job->patched_cb = job->user_cb;
+	job->job_cb_size = cb_size;
+
+	hl_debugfs_add_job(hdev, job);
+
+	rc = gaudi_send_job_on_qman0(hdev, job);
+	hl_debugfs_remove_job(hdev, job);
+	kfree(job);
+	atomic_dec(&cb->cs_cnt);
+
+release_cb:
+	hl_cb_put(cb);
+	hl_cb_destroy(&hdev->kernel_mem_mgr, cb->buf->handle);
+
+	return rc;
+}
+
+static int gaudi_restore_sm_registers(struct hl_device *hdev)
+{
+	u64 base_addr;
+	u32 num_regs;
+	int rc;
+
+	base_addr = CFG_BASE + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0;
+	num_regs = NUM_OF_SOB_IN_BLOCK;
+	rc = gaudi_memset_registers(hdev, base_addr, num_regs, 0);
+	if (rc) {
+		dev_err(hdev->dev, "failed resetting SM registers");
+		return -ENOMEM;
+	}
+
+	base_addr = CFG_BASE +  mmSYNC_MNGR_E_S_SYNC_MNGR_OBJS_SOB_OBJ_0;
+	num_regs = NUM_OF_SOB_IN_BLOCK;
+	rc = gaudi_memset_registers(hdev, base_addr, num_regs, 0);
+	if (rc) {
+		dev_err(hdev->dev, "failed resetting SM registers");
+		return -ENOMEM;
+	}
+
+	base_addr = CFG_BASE +  mmSYNC_MNGR_W_N_SYNC_MNGR_OBJS_SOB_OBJ_0;
+	num_regs = NUM_OF_SOB_IN_BLOCK;
+	rc = gaudi_memset_registers(hdev, base_addr, num_regs, 0);
+	if (rc) {
+		dev_err(hdev->dev, "failed resetting SM registers");
+		return -ENOMEM;
+	}
+
+	base_addr = CFG_BASE +  mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_0;
+	num_regs = NUM_OF_MONITORS_IN_BLOCK;
+	rc = gaudi_memset_registers(hdev, base_addr, num_regs, 0);
+	if (rc) {
+		dev_err(hdev->dev, "failed resetting SM registers");
+		return -ENOMEM;
+	}
+
+	base_addr = CFG_BASE +  mmSYNC_MNGR_E_S_SYNC_MNGR_OBJS_MON_STATUS_0;
+	num_regs = NUM_OF_MONITORS_IN_BLOCK;
+	rc = gaudi_memset_registers(hdev, base_addr, num_regs, 0);
+	if (rc) {
+		dev_err(hdev->dev, "failed resetting SM registers");
+		return -ENOMEM;
+	}
+
+	base_addr = CFG_BASE +  mmSYNC_MNGR_W_N_SYNC_MNGR_OBJS_MON_STATUS_0;
+	num_regs = NUM_OF_MONITORS_IN_BLOCK;
+	rc = gaudi_memset_registers(hdev, base_addr, num_regs, 0);
+	if (rc) {
+		dev_err(hdev->dev, "failed resetting SM registers");
+		return -ENOMEM;
+	}
+
+	base_addr = CFG_BASE +  mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0 +
+			(GAUDI_FIRST_AVAILABLE_W_S_SYNC_OBJECT * 4);
+	num_regs = NUM_OF_SOB_IN_BLOCK - GAUDI_FIRST_AVAILABLE_W_S_SYNC_OBJECT;
+	rc = gaudi_memset_registers(hdev, base_addr, num_regs, 0);
+	if (rc) {
+		dev_err(hdev->dev, "failed resetting SM registers");
+		return -ENOMEM;
+	}
+
+	base_addr = CFG_BASE +  mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0 +
+			(GAUDI_FIRST_AVAILABLE_W_S_MONITOR * 4);
+	num_regs = NUM_OF_MONITORS_IN_BLOCK - GAUDI_FIRST_AVAILABLE_W_S_MONITOR;
+	rc = gaudi_memset_registers(hdev, base_addr, num_regs, 0);
+	if (rc) {
+		dev_err(hdev->dev, "failed resetting SM registers");
+		return -ENOMEM;
+	}
+
+	return 0;
+}
+
+static void gaudi_restore_dma_registers(struct hl_device *hdev)
+{
+	u32 sob_delta = mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_1 -
+			mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0;
+	int i;
+
+	for (i = 0 ; i < DMA_NUMBER_OF_CHANNELS ; i++) {
+		u64 sob_addr = CFG_BASE +
+				mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0 +
+				(i * sob_delta);
+		u32 dma_offset = i * DMA_CORE_OFFSET;
+
+		WREG32(mmDMA0_CORE_WR_COMP_ADDR_LO + dma_offset,
+				lower_32_bits(sob_addr));
+		WREG32(mmDMA0_CORE_WR_COMP_ADDR_HI + dma_offset,
+				upper_32_bits(sob_addr));
+		WREG32(mmDMA0_CORE_WR_COMP_WDATA + dma_offset, 0x80000001);
+
+		/* For DMAs 2-7, need to restore WR_AWUSER_31_11 as it can be
+		 * modified by the user for SRAM reduction
+		 */
+		if (i > 1)
+			WREG32(mmDMA0_CORE_WR_AWUSER_31_11 + dma_offset,
+								0x00000001);
+	}
+}
+
+static void gaudi_restore_qm_registers(struct hl_device *hdev)
+{
+	u32 qman_offset;
+	int i;
+
+	for (i = 0 ; i < DMA_NUMBER_OF_CHANNELS ; i++) {
+		qman_offset = i * DMA_QMAN_OFFSET;
+		WREG32(mmDMA0_QM_ARB_CFG_0 + qman_offset, 0);
+	}
+
+	for (i = 0 ; i < MME_NUMBER_OF_MASTER_ENGINES ; i++) {
+		qman_offset = i * (mmMME2_QM_BASE - mmMME0_QM_BASE);
+		WREG32(mmMME0_QM_ARB_CFG_0 + qman_offset, 0);
+	}
+
+	for (i = 0 ; i < TPC_NUMBER_OF_ENGINES ; i++) {
+		qman_offset = i * TPC_QMAN_OFFSET;
+		WREG32(mmTPC0_QM_ARB_CFG_0 + qman_offset, 0);
+	}
+
+	for (i = 0 ; i < NIC_NUMBER_OF_ENGINES ; i++) {
+		qman_offset = (i >> 1) * NIC_MACRO_QMAN_OFFSET +
+				(i & 0x1) * NIC_ENGINE_QMAN_OFFSET;
+		WREG32(mmNIC0_QM0_ARB_CFG_0 + qman_offset, 0);
+	}
+}
+
+static int gaudi_restore_user_registers(struct hl_device *hdev)
+{
+	int rc;
+
+	rc = gaudi_restore_sm_registers(hdev);
+	if (rc)
+		return rc;
+
+	gaudi_restore_dma_registers(hdev);
+	gaudi_restore_qm_registers(hdev);
+
+	return 0;
+}
+
+static int gaudi_context_switch(struct hl_device *hdev, u32 asid)
+{
+	return 0;
+}
+
+static int gaudi_mmu_clear_pgt_range(struct hl_device *hdev)
+{
+	u32 size = hdev->asic_prop.mmu_pgt_size +
+			hdev->asic_prop.mmu_cache_mng_size;
+	struct gaudi_device *gaudi = hdev->asic_specific;
+	u64 addr = hdev->asic_prop.mmu_pgt_addr;
+
+	if (!(gaudi->hw_cap_initialized & HW_CAP_MMU))
+		return 0;
+
+	return gaudi_memset_device_memory(hdev, addr, size, 0);
+}
+
+static void gaudi_restore_phase_topology(struct hl_device *hdev)
+{
+
+}
+
+static int gaudi_dma_core_transfer(struct hl_device *hdev, int dma_id, u64 addr,
+					u32 size_to_dma, dma_addr_t dma_addr)
+{
+	u32 err_cause, val;
+	u64 dma_offset;
+	int rc;
+
+	dma_offset = dma_id * DMA_CORE_OFFSET;
+
+	WREG32(mmDMA0_CORE_SRC_BASE_LO + dma_offset, lower_32_bits(addr));
+	WREG32(mmDMA0_CORE_SRC_BASE_HI + dma_offset, upper_32_bits(addr));
+	WREG32(mmDMA0_CORE_DST_BASE_LO + dma_offset, lower_32_bits(dma_addr));
+	WREG32(mmDMA0_CORE_DST_BASE_HI + dma_offset, upper_32_bits(dma_addr));
+	WREG32(mmDMA0_CORE_DST_TSIZE_0 + dma_offset, size_to_dma);
+	WREG32(mmDMA0_CORE_COMMIT + dma_offset,
+			(1 << DMA0_CORE_COMMIT_LIN_SHIFT));
+
+	rc = hl_poll_timeout(
+		hdev,
+		mmDMA0_CORE_STS0 + dma_offset,
+		val,
+		((val & DMA0_CORE_STS0_BUSY_MASK) == 0),
+		0,
+		1000000);
+
+	if (rc) {
+		dev_err(hdev->dev,
+			"DMA %d timed-out during reading of 0x%llx\n",
+			dma_id, addr);
+		return -EIO;
+	}
+
+	/* Verify DMA is OK */
+	err_cause = RREG32(mmDMA0_CORE_ERR_CAUSE + dma_offset);
+	if (err_cause) {
+		dev_err(hdev->dev, "DMA Failed, cause 0x%x\n", err_cause);
+		dev_dbg(hdev->dev,
+			"Clearing DMA0 engine from errors (cause 0x%x)\n",
+			err_cause);
+		WREG32(mmDMA0_CORE_ERR_CAUSE + dma_offset, err_cause);
+
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int gaudi_debugfs_read_dma(struct hl_device *hdev, u64 addr, u32 size,
+				void *blob_addr)
+{
+	u32 dma_core_sts0, err_cause, cfg1, size_left, pos, size_to_dma;
+	u32 qm_glbl_sts0, qm_cgm_sts;
+	u64 dma_offset, qm_offset;
+	dma_addr_t dma_addr;
+	void *kernel_addr;
+	bool is_eng_idle;
+	int rc = 0, dma_id;
+
+	kernel_addr = hl_asic_dma_alloc_coherent(hdev, SZ_2M, &dma_addr, GFP_KERNEL | __GFP_ZERO);
+
+	if (!kernel_addr)
+		return -ENOMEM;
+
+	hdev->asic_funcs->hw_queues_lock(hdev);
+
+	dma_id = gaudi_dma_assignment[GAUDI_PCI_DMA_1];
+	dma_offset = dma_id * DMA_CORE_OFFSET;
+	qm_offset = dma_id * DMA_QMAN_OFFSET;
+	dma_core_sts0 = RREG32(mmDMA0_CORE_STS0 + dma_offset);
+	qm_glbl_sts0 = RREG32(mmDMA0_QM_GLBL_STS0 + qm_offset);
+	qm_cgm_sts = RREG32(mmDMA0_QM_CGM_STS + qm_offset);
+	is_eng_idle = IS_QM_IDLE(qm_glbl_sts0, qm_cgm_sts) &&
+		      IS_DMA_IDLE(dma_core_sts0);
+
+	if (!is_eng_idle) {
+		dma_id = gaudi_dma_assignment[GAUDI_PCI_DMA_2];
+		dma_offset = dma_id * DMA_CORE_OFFSET;
+		qm_offset = dma_id * DMA_QMAN_OFFSET;
+		dma_core_sts0 = RREG32(mmDMA0_CORE_STS0 + dma_offset);
+		qm_glbl_sts0 = RREG32(mmDMA0_QM_GLBL_STS0 + qm_offset);
+		qm_cgm_sts = RREG32(mmDMA0_QM_CGM_STS + qm_offset);
+		is_eng_idle = IS_QM_IDLE(qm_glbl_sts0, qm_cgm_sts) &&
+			      IS_DMA_IDLE(dma_core_sts0);
+
+		if (!is_eng_idle) {
+			dev_err_ratelimited(hdev->dev,
+				"Can't read via DMA because it is BUSY\n");
+			rc = -EAGAIN;
+			goto out;
+		}
+	}
+
+	cfg1 = RREG32(mmDMA0_QM_GLBL_CFG1 + qm_offset);
+	WREG32(mmDMA0_QM_GLBL_CFG1 + qm_offset,
+			0xF << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT);
+
+	/* TODO: remove this by mapping the DMA temporary buffer to the MMU
+	 * using the compute ctx ASID, if exists. If not, use the kernel ctx
+	 * ASID
+	 */
+	WREG32_OR(mmDMA0_CORE_PROT + dma_offset, BIT(DMA0_CORE_PROT_VAL_SHIFT));
+
+	/* Verify DMA is OK */
+	err_cause = RREG32(mmDMA0_CORE_ERR_CAUSE + dma_offset);
+	if (err_cause) {
+		dev_dbg(hdev->dev,
+			"Clearing DMA0 engine from errors (cause 0x%x)\n",
+			err_cause);
+		WREG32(mmDMA0_CORE_ERR_CAUSE + dma_offset, err_cause);
+	}
+
+	pos = 0;
+	size_left = size;
+	size_to_dma = SZ_2M;
+
+	while (size_left > 0) {
+
+		if (size_left < SZ_2M)
+			size_to_dma = size_left;
+
+		rc = gaudi_dma_core_transfer(hdev, dma_id, addr, size_to_dma,
+						dma_addr);
+		if (rc)
+			break;
+
+		memcpy(blob_addr + pos, kernel_addr, size_to_dma);
+
+		if (size_left <= SZ_2M)
+			break;
+
+		pos += SZ_2M;
+		addr += SZ_2M;
+		size_left -= SZ_2M;
+	}
+
+	/* TODO: remove this by mapping the DMA temporary buffer to the MMU
+	 * using the compute ctx ASID, if exists. If not, use the kernel ctx
+	 * ASID
+	 */
+	WREG32_AND(mmDMA0_CORE_PROT + dma_offset,
+			~BIT(DMA0_CORE_PROT_VAL_SHIFT));
+
+	WREG32(mmDMA0_QM_GLBL_CFG1 + qm_offset, cfg1);
+
+out:
+	hdev->asic_funcs->hw_queues_unlock(hdev);
+
+	hl_asic_dma_free_coherent(hdev, SZ_2M, kernel_addr, dma_addr);
+
+	return rc;
+}
+
+static u64 gaudi_read_pte(struct hl_device *hdev, u64 addr)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+
+	if (hdev->reset_info.hard_reset_pending)
+		return U64_MAX;
+
+	return readq(hdev->pcie_bar[HBM_BAR_ID] +
+			(addr - gaudi->hbm_bar_cur_addr));
+}
+
+static void gaudi_write_pte(struct hl_device *hdev, u64 addr, u64 val)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+
+	if (hdev->reset_info.hard_reset_pending)
+		return;
+
+	writeq(val, hdev->pcie_bar[HBM_BAR_ID] +
+			(addr - gaudi->hbm_bar_cur_addr));
+}
+
+void gaudi_mmu_prepare_reg(struct hl_device *hdev, u64 reg, u32 asid)
+{
+	/* mask to zero the MMBP and ASID bits */
+	WREG32_AND(reg, ~0x7FF);
+	WREG32_OR(reg, asid);
+}
+
+static void gaudi_mmu_prepare(struct hl_device *hdev, u32 asid)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+
+	if (!(gaudi->hw_cap_initialized & HW_CAP_MMU))
+		return;
+
+	if (asid & ~DMA0_QM_GLBL_NON_SECURE_PROPS_0_ASID_MASK) {
+		dev_crit(hdev->dev, "asid %u is too big\n", asid);
+		return;
+	}
+
+	gaudi_mmu_prepare_reg(hdev, mmDMA0_QM_GLBL_NON_SECURE_PROPS_0, asid);
+	gaudi_mmu_prepare_reg(hdev, mmDMA0_QM_GLBL_NON_SECURE_PROPS_1, asid);
+	gaudi_mmu_prepare_reg(hdev, mmDMA0_QM_GLBL_NON_SECURE_PROPS_2, asid);
+	gaudi_mmu_prepare_reg(hdev, mmDMA0_QM_GLBL_NON_SECURE_PROPS_3, asid);
+	gaudi_mmu_prepare_reg(hdev, mmDMA0_QM_GLBL_NON_SECURE_PROPS_4, asid);
+
+	gaudi_mmu_prepare_reg(hdev, mmDMA1_QM_GLBL_NON_SECURE_PROPS_0, asid);
+	gaudi_mmu_prepare_reg(hdev, mmDMA1_QM_GLBL_NON_SECURE_PROPS_1, asid);
+	gaudi_mmu_prepare_reg(hdev, mmDMA1_QM_GLBL_NON_SECURE_PROPS_2, asid);
+	gaudi_mmu_prepare_reg(hdev, mmDMA1_QM_GLBL_NON_SECURE_PROPS_3, asid);
+	gaudi_mmu_prepare_reg(hdev, mmDMA1_QM_GLBL_NON_SECURE_PROPS_4, asid);
+
+	gaudi_mmu_prepare_reg(hdev, mmDMA2_QM_GLBL_NON_SECURE_PROPS_0, asid);
+	gaudi_mmu_prepare_reg(hdev, mmDMA2_QM_GLBL_NON_SECURE_PROPS_1, asid);
+	gaudi_mmu_prepare_reg(hdev, mmDMA2_QM_GLBL_NON_SECURE_PROPS_2, asid);
+	gaudi_mmu_prepare_reg(hdev, mmDMA2_QM_GLBL_NON_SECURE_PROPS_3, asid);
+	gaudi_mmu_prepare_reg(hdev, mmDMA2_QM_GLBL_NON_SECURE_PROPS_4, asid);
+
+	gaudi_mmu_prepare_reg(hdev, mmDMA3_QM_GLBL_NON_SECURE_PROPS_0, asid);
+	gaudi_mmu_prepare_reg(hdev, mmDMA3_QM_GLBL_NON_SECURE_PROPS_1, asid);
+	gaudi_mmu_prepare_reg(hdev, mmDMA3_QM_GLBL_NON_SECURE_PROPS_2, asid);
+	gaudi_mmu_prepare_reg(hdev, mmDMA3_QM_GLBL_NON_SECURE_PROPS_3, asid);
+	gaudi_mmu_prepare_reg(hdev, mmDMA3_QM_GLBL_NON_SECURE_PROPS_4, asid);
+
+	gaudi_mmu_prepare_reg(hdev, mmDMA4_QM_GLBL_NON_SECURE_PROPS_0, asid);
+	gaudi_mmu_prepare_reg(hdev, mmDMA4_QM_GLBL_NON_SECURE_PROPS_1, asid);
+	gaudi_mmu_prepare_reg(hdev, mmDMA4_QM_GLBL_NON_SECURE_PROPS_2, asid);
+	gaudi_mmu_prepare_reg(hdev, mmDMA4_QM_GLBL_NON_SECURE_PROPS_3, asid);
+	gaudi_mmu_prepare_reg(hdev, mmDMA4_QM_GLBL_NON_SECURE_PROPS_4, asid);
+
+	gaudi_mmu_prepare_reg(hdev, mmDMA5_QM_GLBL_NON_SECURE_PROPS_0, asid);
+	gaudi_mmu_prepare_reg(hdev, mmDMA5_QM_GLBL_NON_SECURE_PROPS_1, asid);
+	gaudi_mmu_prepare_reg(hdev, mmDMA5_QM_GLBL_NON_SECURE_PROPS_2, asid);
+	gaudi_mmu_prepare_reg(hdev, mmDMA5_QM_GLBL_NON_SECURE_PROPS_3, asid);
+	gaudi_mmu_prepare_reg(hdev, mmDMA5_QM_GLBL_NON_SECURE_PROPS_4, asid);
+
+	gaudi_mmu_prepare_reg(hdev, mmDMA6_QM_GLBL_NON_SECURE_PROPS_0, asid);
+	gaudi_mmu_prepare_reg(hdev, mmDMA6_QM_GLBL_NON_SECURE_PROPS_1, asid);
+	gaudi_mmu_prepare_reg(hdev, mmDMA6_QM_GLBL_NON_SECURE_PROPS_2, asid);
+	gaudi_mmu_prepare_reg(hdev, mmDMA6_QM_GLBL_NON_SECURE_PROPS_3, asid);
+	gaudi_mmu_prepare_reg(hdev, mmDMA6_QM_GLBL_NON_SECURE_PROPS_4, asid);
+
+	gaudi_mmu_prepare_reg(hdev, mmDMA7_QM_GLBL_NON_SECURE_PROPS_0, asid);
+	gaudi_mmu_prepare_reg(hdev, mmDMA7_QM_GLBL_NON_SECURE_PROPS_1, asid);
+	gaudi_mmu_prepare_reg(hdev, mmDMA7_QM_GLBL_NON_SECURE_PROPS_2, asid);
+	gaudi_mmu_prepare_reg(hdev, mmDMA7_QM_GLBL_NON_SECURE_PROPS_3, asid);
+	gaudi_mmu_prepare_reg(hdev, mmDMA7_QM_GLBL_NON_SECURE_PROPS_4, asid);
+
+	gaudi_mmu_prepare_reg(hdev, mmDMA0_CORE_NON_SECURE_PROPS, asid);
+	gaudi_mmu_prepare_reg(hdev, mmDMA1_CORE_NON_SECURE_PROPS, asid);
+	gaudi_mmu_prepare_reg(hdev, mmDMA2_CORE_NON_SECURE_PROPS, asid);
+	gaudi_mmu_prepare_reg(hdev, mmDMA3_CORE_NON_SECURE_PROPS, asid);
+	gaudi_mmu_prepare_reg(hdev, mmDMA4_CORE_NON_SECURE_PROPS, asid);
+	gaudi_mmu_prepare_reg(hdev, mmDMA5_CORE_NON_SECURE_PROPS, asid);
+	gaudi_mmu_prepare_reg(hdev, mmDMA6_CORE_NON_SECURE_PROPS, asid);
+	gaudi_mmu_prepare_reg(hdev, mmDMA7_CORE_NON_SECURE_PROPS, asid);
+
+	gaudi_mmu_prepare_reg(hdev, mmTPC0_QM_GLBL_NON_SECURE_PROPS_0, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC0_QM_GLBL_NON_SECURE_PROPS_1, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC0_QM_GLBL_NON_SECURE_PROPS_2, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC0_QM_GLBL_NON_SECURE_PROPS_3, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC0_QM_GLBL_NON_SECURE_PROPS_4, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC0_CFG_ARUSER_LO, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC0_CFG_AWUSER_LO, asid);
+
+	gaudi_mmu_prepare_reg(hdev, mmTPC1_QM_GLBL_NON_SECURE_PROPS_0, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC1_QM_GLBL_NON_SECURE_PROPS_1, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC1_QM_GLBL_NON_SECURE_PROPS_2, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC1_QM_GLBL_NON_SECURE_PROPS_3, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC1_QM_GLBL_NON_SECURE_PROPS_4, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC1_CFG_ARUSER_LO, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC1_CFG_AWUSER_LO, asid);
+
+	gaudi_mmu_prepare_reg(hdev, mmTPC2_QM_GLBL_NON_SECURE_PROPS_0, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC2_QM_GLBL_NON_SECURE_PROPS_1, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC2_QM_GLBL_NON_SECURE_PROPS_2, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC2_QM_GLBL_NON_SECURE_PROPS_3, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC2_QM_GLBL_NON_SECURE_PROPS_4, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC2_CFG_ARUSER_LO, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC2_CFG_AWUSER_LO, asid);
+
+	gaudi_mmu_prepare_reg(hdev, mmTPC3_QM_GLBL_NON_SECURE_PROPS_0, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC3_QM_GLBL_NON_SECURE_PROPS_1, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC3_QM_GLBL_NON_SECURE_PROPS_2, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC3_QM_GLBL_NON_SECURE_PROPS_3, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC3_QM_GLBL_NON_SECURE_PROPS_4, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC3_CFG_ARUSER_LO, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC3_CFG_AWUSER_LO, asid);
+
+	gaudi_mmu_prepare_reg(hdev, mmTPC4_QM_GLBL_NON_SECURE_PROPS_0, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC4_QM_GLBL_NON_SECURE_PROPS_1, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC4_QM_GLBL_NON_SECURE_PROPS_2, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC4_QM_GLBL_NON_SECURE_PROPS_3, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC4_QM_GLBL_NON_SECURE_PROPS_4, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC4_CFG_ARUSER_LO, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC4_CFG_AWUSER_LO, asid);
+
+	gaudi_mmu_prepare_reg(hdev, mmTPC5_QM_GLBL_NON_SECURE_PROPS_0, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC5_QM_GLBL_NON_SECURE_PROPS_1, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC5_QM_GLBL_NON_SECURE_PROPS_2, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC5_QM_GLBL_NON_SECURE_PROPS_3, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC5_QM_GLBL_NON_SECURE_PROPS_4, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC5_CFG_ARUSER_LO, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC5_CFG_AWUSER_LO, asid);
+
+	gaudi_mmu_prepare_reg(hdev, mmTPC6_QM_GLBL_NON_SECURE_PROPS_0, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC6_QM_GLBL_NON_SECURE_PROPS_1, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC6_QM_GLBL_NON_SECURE_PROPS_2, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC6_QM_GLBL_NON_SECURE_PROPS_3, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC6_QM_GLBL_NON_SECURE_PROPS_4, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC6_CFG_ARUSER_LO, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC6_CFG_AWUSER_LO, asid);
+
+	gaudi_mmu_prepare_reg(hdev, mmTPC7_QM_GLBL_NON_SECURE_PROPS_0, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC7_QM_GLBL_NON_SECURE_PROPS_1, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC7_QM_GLBL_NON_SECURE_PROPS_2, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC7_QM_GLBL_NON_SECURE_PROPS_3, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC7_QM_GLBL_NON_SECURE_PROPS_4, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC7_CFG_ARUSER_LO, asid);
+	gaudi_mmu_prepare_reg(hdev, mmTPC7_CFG_AWUSER_LO, asid);
+
+	gaudi_mmu_prepare_reg(hdev, mmMME0_QM_GLBL_NON_SECURE_PROPS_0, asid);
+	gaudi_mmu_prepare_reg(hdev, mmMME0_QM_GLBL_NON_SECURE_PROPS_1, asid);
+	gaudi_mmu_prepare_reg(hdev, mmMME0_QM_GLBL_NON_SECURE_PROPS_2, asid);
+	gaudi_mmu_prepare_reg(hdev, mmMME0_QM_GLBL_NON_SECURE_PROPS_3, asid);
+	gaudi_mmu_prepare_reg(hdev, mmMME0_QM_GLBL_NON_SECURE_PROPS_4, asid);
+	gaudi_mmu_prepare_reg(hdev, mmMME2_QM_GLBL_NON_SECURE_PROPS_0, asid);
+	gaudi_mmu_prepare_reg(hdev, mmMME2_QM_GLBL_NON_SECURE_PROPS_1, asid);
+	gaudi_mmu_prepare_reg(hdev, mmMME2_QM_GLBL_NON_SECURE_PROPS_2, asid);
+	gaudi_mmu_prepare_reg(hdev, mmMME2_QM_GLBL_NON_SECURE_PROPS_3, asid);
+	gaudi_mmu_prepare_reg(hdev, mmMME2_QM_GLBL_NON_SECURE_PROPS_4, asid);
+
+	gaudi_mmu_prepare_reg(hdev, mmMME0_SBAB_ARUSER0, asid);
+	gaudi_mmu_prepare_reg(hdev, mmMME0_SBAB_ARUSER1, asid);
+	gaudi_mmu_prepare_reg(hdev, mmMME1_SBAB_ARUSER0, asid);
+	gaudi_mmu_prepare_reg(hdev, mmMME1_SBAB_ARUSER1, asid);
+	gaudi_mmu_prepare_reg(hdev, mmMME2_SBAB_ARUSER0, asid);
+	gaudi_mmu_prepare_reg(hdev, mmMME2_SBAB_ARUSER1, asid);
+	gaudi_mmu_prepare_reg(hdev, mmMME3_SBAB_ARUSER0, asid);
+	gaudi_mmu_prepare_reg(hdev, mmMME3_SBAB_ARUSER1, asid);
+	gaudi_mmu_prepare_reg(hdev, mmMME0_ACC_WBC, asid);
+	gaudi_mmu_prepare_reg(hdev, mmMME1_ACC_WBC, asid);
+	gaudi_mmu_prepare_reg(hdev, mmMME2_ACC_WBC, asid);
+	gaudi_mmu_prepare_reg(hdev, mmMME3_ACC_WBC, asid);
+
+	if (gaudi->hw_cap_initialized & HW_CAP_NIC0) {
+		gaudi_mmu_prepare_reg(hdev, mmNIC0_QM0_GLBL_NON_SECURE_PROPS_0,
+				asid);
+		gaudi_mmu_prepare_reg(hdev, mmNIC0_QM0_GLBL_NON_SECURE_PROPS_1,
+				asid);
+		gaudi_mmu_prepare_reg(hdev, mmNIC0_QM0_GLBL_NON_SECURE_PROPS_2,
+				asid);
+		gaudi_mmu_prepare_reg(hdev, mmNIC0_QM0_GLBL_NON_SECURE_PROPS_3,
+				asid);
+		gaudi_mmu_prepare_reg(hdev, mmNIC0_QM0_GLBL_NON_SECURE_PROPS_4,
+				asid);
+	}
+
+	if (gaudi->hw_cap_initialized & HW_CAP_NIC1) {
+		gaudi_mmu_prepare_reg(hdev, mmNIC0_QM1_GLBL_NON_SECURE_PROPS_0,
+				asid);
+		gaudi_mmu_prepare_reg(hdev, mmNIC0_QM1_GLBL_NON_SECURE_PROPS_1,
+				asid);
+		gaudi_mmu_prepare_reg(hdev, mmNIC0_QM1_GLBL_NON_SECURE_PROPS_2,
+				asid);
+		gaudi_mmu_prepare_reg(hdev, mmNIC0_QM1_GLBL_NON_SECURE_PROPS_3,
+				asid);
+		gaudi_mmu_prepare_reg(hdev, mmNIC0_QM1_GLBL_NON_SECURE_PROPS_4,
+				asid);
+	}
+
+	if (gaudi->hw_cap_initialized & HW_CAP_NIC2) {
+		gaudi_mmu_prepare_reg(hdev, mmNIC1_QM0_GLBL_NON_SECURE_PROPS_0,
+				asid);
+		gaudi_mmu_prepare_reg(hdev, mmNIC1_QM0_GLBL_NON_SECURE_PROPS_1,
+				asid);
+		gaudi_mmu_prepare_reg(hdev, mmNIC1_QM0_GLBL_NON_SECURE_PROPS_2,
+				asid);
+		gaudi_mmu_prepare_reg(hdev, mmNIC1_QM0_GLBL_NON_SECURE_PROPS_3,
+				asid);
+		gaudi_mmu_prepare_reg(hdev, mmNIC1_QM0_GLBL_NON_SECURE_PROPS_4,
+				asid);
+	}
+
+	if (gaudi->hw_cap_initialized & HW_CAP_NIC3) {
+		gaudi_mmu_prepare_reg(hdev, mmNIC1_QM1_GLBL_NON_SECURE_PROPS_0,
+				asid);
+		gaudi_mmu_prepare_reg(hdev, mmNIC1_QM1_GLBL_NON_SECURE_PROPS_1,
+				asid);
+		gaudi_mmu_prepare_reg(hdev, mmNIC1_QM1_GLBL_NON_SECURE_PROPS_2,
+				asid);
+		gaudi_mmu_prepare_reg(hdev, mmNIC1_QM1_GLBL_NON_SECURE_PROPS_3,
+				asid);
+		gaudi_mmu_prepare_reg(hdev, mmNIC1_QM1_GLBL_NON_SECURE_PROPS_4,
+				asid);
+	}
+
+	if (gaudi->hw_cap_initialized & HW_CAP_NIC4) {
+		gaudi_mmu_prepare_reg(hdev, mmNIC2_QM0_GLBL_NON_SECURE_PROPS_0,
+				asid);
+		gaudi_mmu_prepare_reg(hdev, mmNIC2_QM0_GLBL_NON_SECURE_PROPS_1,
+				asid);
+		gaudi_mmu_prepare_reg(hdev, mmNIC2_QM0_GLBL_NON_SECURE_PROPS_2,
+				asid);
+		gaudi_mmu_prepare_reg(hdev, mmNIC2_QM0_GLBL_NON_SECURE_PROPS_3,
+				asid);
+		gaudi_mmu_prepare_reg(hdev, mmNIC2_QM0_GLBL_NON_SECURE_PROPS_4,
+				asid);
+	}
+
+	if (gaudi->hw_cap_initialized & HW_CAP_NIC5) {
+		gaudi_mmu_prepare_reg(hdev, mmNIC2_QM1_GLBL_NON_SECURE_PROPS_0,
+				asid);
+		gaudi_mmu_prepare_reg(hdev, mmNIC2_QM1_GLBL_NON_SECURE_PROPS_1,
+				asid);
+		gaudi_mmu_prepare_reg(hdev, mmNIC2_QM1_GLBL_NON_SECURE_PROPS_2,
+				asid);
+		gaudi_mmu_prepare_reg(hdev, mmNIC2_QM1_GLBL_NON_SECURE_PROPS_3,
+				asid);
+		gaudi_mmu_prepare_reg(hdev, mmNIC2_QM1_GLBL_NON_SECURE_PROPS_4,
+				asid);
+	}
+
+	if (gaudi->hw_cap_initialized & HW_CAP_NIC6) {
+		gaudi_mmu_prepare_reg(hdev, mmNIC3_QM0_GLBL_NON_SECURE_PROPS_0,
+				asid);
+		gaudi_mmu_prepare_reg(hdev, mmNIC3_QM0_GLBL_NON_SECURE_PROPS_1,
+				asid);
+		gaudi_mmu_prepare_reg(hdev, mmNIC3_QM0_GLBL_NON_SECURE_PROPS_2,
+				asid);
+		gaudi_mmu_prepare_reg(hdev, mmNIC3_QM0_GLBL_NON_SECURE_PROPS_3,
+				asid);
+		gaudi_mmu_prepare_reg(hdev, mmNIC3_QM0_GLBL_NON_SECURE_PROPS_4,
+				asid);
+	}
+
+	if (gaudi->hw_cap_initialized & HW_CAP_NIC7) {
+		gaudi_mmu_prepare_reg(hdev, mmNIC3_QM1_GLBL_NON_SECURE_PROPS_0,
+				asid);
+		gaudi_mmu_prepare_reg(hdev, mmNIC3_QM1_GLBL_NON_SECURE_PROPS_1,
+				asid);
+		gaudi_mmu_prepare_reg(hdev, mmNIC3_QM1_GLBL_NON_SECURE_PROPS_2,
+				asid);
+		gaudi_mmu_prepare_reg(hdev, mmNIC3_QM1_GLBL_NON_SECURE_PROPS_3,
+				asid);
+		gaudi_mmu_prepare_reg(hdev, mmNIC3_QM1_GLBL_NON_SECURE_PROPS_4,
+				asid);
+	}
+
+	if (gaudi->hw_cap_initialized & HW_CAP_NIC8) {
+		gaudi_mmu_prepare_reg(hdev, mmNIC4_QM0_GLBL_NON_SECURE_PROPS_0,
+				asid);
+		gaudi_mmu_prepare_reg(hdev, mmNIC4_QM0_GLBL_NON_SECURE_PROPS_1,
+				asid);
+		gaudi_mmu_prepare_reg(hdev, mmNIC4_QM0_GLBL_NON_SECURE_PROPS_2,
+				asid);
+		gaudi_mmu_prepare_reg(hdev, mmNIC4_QM0_GLBL_NON_SECURE_PROPS_3,
+				asid);
+		gaudi_mmu_prepare_reg(hdev, mmNIC4_QM0_GLBL_NON_SECURE_PROPS_4,
+				asid);
+	}
+
+	if (gaudi->hw_cap_initialized & HW_CAP_NIC9) {
+		gaudi_mmu_prepare_reg(hdev, mmNIC4_QM1_GLBL_NON_SECURE_PROPS_0,
+				asid);
+		gaudi_mmu_prepare_reg(hdev, mmNIC4_QM1_GLBL_NON_SECURE_PROPS_1,
+				asid);
+		gaudi_mmu_prepare_reg(hdev, mmNIC4_QM1_GLBL_NON_SECURE_PROPS_2,
+				asid);
+		gaudi_mmu_prepare_reg(hdev, mmNIC4_QM1_GLBL_NON_SECURE_PROPS_3,
+				asid);
+		gaudi_mmu_prepare_reg(hdev, mmNIC4_QM1_GLBL_NON_SECURE_PROPS_4,
+				asid);
+	}
+
+	gaudi_mmu_prepare_reg(hdev, mmPSOC_GLOBAL_CONF_TRACE_ARUSER, asid);
+	gaudi_mmu_prepare_reg(hdev, mmPSOC_GLOBAL_CONF_TRACE_AWUSER, asid);
+}
+
+static int gaudi_send_job_on_qman0(struct hl_device *hdev,
+		struct hl_cs_job *job)
+{
+	struct packet_msg_prot *fence_pkt;
+	u32 *fence_ptr;
+	dma_addr_t fence_dma_addr;
+	struct hl_cb *cb;
+	u32 tmp, timeout, dma_offset;
+	int rc;
+
+	if (hdev->pldm)
+		timeout = GAUDI_PLDM_QMAN0_TIMEOUT_USEC;
+	else
+		timeout = HL_DEVICE_TIMEOUT_USEC;
+
+	fence_ptr = hl_asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL, &fence_dma_addr);
+	if (!fence_ptr) {
+		dev_err(hdev->dev,
+			"Failed to allocate fence memory for QMAN0\n");
+		return -ENOMEM;
+	}
+
+	cb = job->patched_cb;
+
+	fence_pkt = cb->kernel_address +
+			job->job_cb_size - sizeof(struct packet_msg_prot);
+
+	tmp = FIELD_PREP(GAUDI_PKT_CTL_OPCODE_MASK, PACKET_MSG_PROT);
+	tmp |= FIELD_PREP(GAUDI_PKT_CTL_EB_MASK, 1);
+	tmp |= FIELD_PREP(GAUDI_PKT_CTL_MB_MASK, 1);
+
+	fence_pkt->ctl = cpu_to_le32(tmp);
+	fence_pkt->value = cpu_to_le32(GAUDI_QMAN0_FENCE_VAL);
+	fence_pkt->addr = cpu_to_le64(fence_dma_addr);
+
+	dma_offset = gaudi_dma_assignment[GAUDI_PCI_DMA_1] * DMA_CORE_OFFSET;
+
+	WREG32(mmDMA0_CORE_PROT + dma_offset,
+			BIT(DMA0_CORE_PROT_ERR_VAL_SHIFT) | BIT(DMA0_CORE_PROT_VAL_SHIFT));
+
+	rc = hl_hw_queue_send_cb_no_cmpl(hdev, GAUDI_QUEUE_ID_DMA_0_0,
+					job->job_cb_size, cb->bus_address);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to send CB on QMAN0, %d\n", rc);
+		goto free_fence_ptr;
+	}
+
+	rc = hl_poll_timeout_memory(hdev, fence_ptr, tmp,
+				(tmp == GAUDI_QMAN0_FENCE_VAL), 1000,
+				timeout, true);
+
+	hl_hw_queue_inc_ci_kernel(hdev, GAUDI_QUEUE_ID_DMA_0_0);
+
+	if (rc == -ETIMEDOUT) {
+		dev_err(hdev->dev, "QMAN0 Job timeout (0x%x)\n", tmp);
+		goto free_fence_ptr;
+	}
+
+free_fence_ptr:
+	WREG32(mmDMA0_CORE_PROT + dma_offset, BIT(DMA0_CORE_PROT_ERR_VAL_SHIFT));
+
+	hl_asic_dma_pool_free(hdev, (void *) fence_ptr, fence_dma_addr);
+	return rc;
+}
+
+static void gaudi_get_event_desc(u16 event_type, char *desc, size_t size)
+{
+	if (event_type >= GAUDI_EVENT_SIZE)
+		goto event_not_supported;
+
+	if (!gaudi_irq_map_table[event_type].valid)
+		goto event_not_supported;
+
+	snprintf(desc, size, gaudi_irq_map_table[event_type].name);
+
+	return;
+
+event_not_supported:
+	snprintf(desc, size, "N/A");
+}
+
+static const char *gaudi_get_razwi_initiator_dma_name(struct hl_device *hdev, u32 x_y,
+							bool is_write, u16 *engine_id_1,
+							u16 *engine_id_2)
+{
+	u32 dma_id[2], dma_offset, err_cause[2], mask, i;
+
+	mask = is_write ? DMA0_CORE_ERR_CAUSE_HBW_WR_ERR_MASK :
+				DMA0_CORE_ERR_CAUSE_HBW_RD_ERR_MASK;
+
+	switch (x_y) {
+	case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_0:
+	case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_1:
+		dma_id[0] = 0;
+		dma_id[1] = 2;
+		break;
+	case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_0:
+	case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_1:
+		dma_id[0] = 1;
+		dma_id[1] = 3;
+		break;
+	case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_0:
+	case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_1:
+		dma_id[0] = 4;
+		dma_id[1] = 6;
+		break;
+	case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_0:
+	case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_1:
+		dma_id[0] = 5;
+		dma_id[1] = 7;
+		break;
+	default:
+		goto unknown_initiator;
+	}
+
+	for (i = 0 ; i < 2 ; i++) {
+		dma_offset = dma_id[i] * DMA_CORE_OFFSET;
+		err_cause[i] = RREG32(mmDMA0_CORE_ERR_CAUSE + dma_offset);
+	}
+
+	switch (x_y) {
+	case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_0:
+	case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_1:
+		if ((err_cause[0] & mask) && !(err_cause[1] & mask)) {
+			*engine_id_1 = GAUDI_ENGINE_ID_DMA_0;
+			return "DMA0";
+		} else if (!(err_cause[0] & mask) && (err_cause[1] & mask)) {
+			*engine_id_1 = GAUDI_ENGINE_ID_DMA_2;
+			return "DMA2";
+		} else {
+			*engine_id_1 = GAUDI_ENGINE_ID_DMA_0;
+			*engine_id_2 = GAUDI_ENGINE_ID_DMA_2;
+			return "DMA0 or DMA2";
+		}
+	case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_0:
+	case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_1:
+		if ((err_cause[0] & mask) && !(err_cause[1] & mask)) {
+			*engine_id_1 = GAUDI_ENGINE_ID_DMA_1;
+			return "DMA1";
+		} else if (!(err_cause[0] & mask) && (err_cause[1] & mask)) {
+			*engine_id_1 = GAUDI_ENGINE_ID_DMA_3;
+			return "DMA3";
+		} else {
+			*engine_id_1 = GAUDI_ENGINE_ID_DMA_1;
+			*engine_id_2 = GAUDI_ENGINE_ID_DMA_3;
+			return "DMA1 or DMA3";
+		}
+	case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_0:
+	case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_1:
+		if ((err_cause[0] & mask) && !(err_cause[1] & mask)) {
+			*engine_id_1 = GAUDI_ENGINE_ID_DMA_4;
+			return "DMA4";
+		} else if (!(err_cause[0] & mask) && (err_cause[1] & mask)) {
+			*engine_id_1 = GAUDI_ENGINE_ID_DMA_6;
+			return "DMA6";
+		} else {
+			*engine_id_1 = GAUDI_ENGINE_ID_DMA_4;
+			*engine_id_2 = GAUDI_ENGINE_ID_DMA_6;
+			return "DMA4 or DMA6";
+		}
+	case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_0:
+	case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_1:
+		if ((err_cause[0] & mask) && !(err_cause[1] & mask)) {
+			*engine_id_1 = GAUDI_ENGINE_ID_DMA_5;
+			return "DMA5";
+		} else if (!(err_cause[0] & mask) && (err_cause[1] & mask)) {
+			*engine_id_1 = GAUDI_ENGINE_ID_DMA_7;
+			return "DMA7";
+		} else {
+			*engine_id_1 = GAUDI_ENGINE_ID_DMA_5;
+			*engine_id_2 = GAUDI_ENGINE_ID_DMA_7;
+			return "DMA5 or DMA7";
+		}
+	}
+
+unknown_initiator:
+	return "unknown initiator";
+}
+
+static const char *gaudi_get_razwi_initiator_name(struct hl_device *hdev, bool is_write,
+							u16 *engine_id_1, u16 *engine_id_2)
+{
+	u32 val, x_y, axi_id;
+
+	val = is_write ? RREG32(mmMMU_UP_RAZWI_WRITE_ID) :
+				RREG32(mmMMU_UP_RAZWI_READ_ID);
+	x_y = val & ((RAZWI_INITIATOR_Y_MASK << RAZWI_INITIATOR_Y_SHIFT) |
+			(RAZWI_INITIATOR_X_MASK << RAZWI_INITIATOR_X_SHIFT));
+	axi_id = val & (RAZWI_INITIATOR_AXI_ID_MASK <<
+			RAZWI_INITIATOR_AXI_ID_SHIFT);
+
+	switch (x_y) {
+	case RAZWI_INITIATOR_ID_X_Y_TPC0_NIC0:
+		if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_TPC)) {
+			*engine_id_1 = GAUDI_ENGINE_ID_TPC_0;
+			return "TPC0";
+		}
+		if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_NIC)) {
+			*engine_id_1 = GAUDI_ENGINE_ID_NIC_0;
+			return "NIC0";
+		}
+		break;
+	case RAZWI_INITIATOR_ID_X_Y_TPC1:
+		*engine_id_1 = GAUDI_ENGINE_ID_TPC_1;
+		return "TPC1";
+	case RAZWI_INITIATOR_ID_X_Y_MME0_0:
+	case RAZWI_INITIATOR_ID_X_Y_MME0_1:
+		*engine_id_1 = GAUDI_ENGINE_ID_MME_0;
+		return "MME0";
+	case RAZWI_INITIATOR_ID_X_Y_MME1_0:
+	case RAZWI_INITIATOR_ID_X_Y_MME1_1:
+		*engine_id_1 = GAUDI_ENGINE_ID_MME_1;
+		return "MME1";
+	case RAZWI_INITIATOR_ID_X_Y_TPC2:
+		*engine_id_1 = GAUDI_ENGINE_ID_TPC_2;
+		return "TPC2";
+	case RAZWI_INITIATOR_ID_X_Y_TPC3_PCI_CPU_PSOC:
+		if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_TPC)) {
+			*engine_id_1 = GAUDI_ENGINE_ID_TPC_3;
+			return "TPC3";
+		}
+		/* PCI, CPU or PSOC does not have engine id*/
+		if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_PCI))
+			return "PCI";
+		if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_CPU))
+			return "CPU";
+		if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_PSOC))
+			return "PSOC";
+		break;
+	case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_0:
+	case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_1:
+	case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_0:
+	case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_1:
+	case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_0:
+	case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_1:
+	case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_0:
+	case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_1:
+		return gaudi_get_razwi_initiator_dma_name(hdev, x_y, is_write,
+				engine_id_1, engine_id_2);
+	case RAZWI_INITIATOR_ID_X_Y_TPC4_NIC1_NIC2:
+		if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_TPC)) {
+			*engine_id_1 = GAUDI_ENGINE_ID_TPC_4;
+			return "TPC4";
+		}
+		if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_NIC)) {
+			*engine_id_1 = GAUDI_ENGINE_ID_NIC_1;
+			return "NIC1";
+		}
+		if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_NIC_FT)) {
+			*engine_id_1 = GAUDI_ENGINE_ID_NIC_2;
+			return "NIC2";
+		}
+		break;
+	case RAZWI_INITIATOR_ID_X_Y_TPC5:
+		*engine_id_1 = GAUDI_ENGINE_ID_TPC_5;
+		return "TPC5";
+	case RAZWI_INITIATOR_ID_X_Y_MME2_0:
+	case RAZWI_INITIATOR_ID_X_Y_MME2_1:
+		*engine_id_1 = GAUDI_ENGINE_ID_MME_2;
+		return "MME2";
+	case RAZWI_INITIATOR_ID_X_Y_MME3_0:
+	case RAZWI_INITIATOR_ID_X_Y_MME3_1:
+		*engine_id_1 = GAUDI_ENGINE_ID_MME_3;
+		return "MME3";
+	case RAZWI_INITIATOR_ID_X_Y_TPC6:
+		*engine_id_1 = GAUDI_ENGINE_ID_TPC_6;
+		return "TPC6";
+	case RAZWI_INITIATOR_ID_X_Y_TPC7_NIC4_NIC5:
+		if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_TPC)) {
+			*engine_id_1 = GAUDI_ENGINE_ID_TPC_7;
+			return "TPC7";
+		}
+		if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_NIC)) {
+			*engine_id_1 = GAUDI_ENGINE_ID_NIC_4;
+			return "NIC4";
+		}
+		if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_NIC_FT)) {
+			*engine_id_1 = GAUDI_ENGINE_ID_NIC_5;
+			return "NIC5";
+		}
+		break;
+	default:
+		break;
+	}
+
+	dev_err(hdev->dev,
+		"Unknown RAZWI initiator ID 0x%x [Y=%d, X=%d, AXI_ID=%d]\n",
+		val,
+		(val >> RAZWI_INITIATOR_Y_SHIFT) & RAZWI_INITIATOR_Y_MASK,
+		(val >> RAZWI_INITIATOR_X_SHIFT) & RAZWI_INITIATOR_X_MASK,
+		(val >> RAZWI_INITIATOR_AXI_ID_SHIFT) &
+			RAZWI_INITIATOR_AXI_ID_MASK);
+
+	return "unknown initiator";
+}
+
+static void gaudi_print_and_get_razwi_info(struct hl_device *hdev, u16 *engine_id_1,
+						u16 *engine_id_2, bool *is_read, bool *is_write)
+{
+
+	if (RREG32(mmMMU_UP_RAZWI_WRITE_VLD)) {
+		dev_err_ratelimited(hdev->dev,
+			"RAZWI event caused by illegal write of %s\n",
+			gaudi_get_razwi_initiator_name(hdev, true, engine_id_1, engine_id_2));
+		WREG32(mmMMU_UP_RAZWI_WRITE_VLD, 0);
+		*is_write = true;
+	}
+
+	if (RREG32(mmMMU_UP_RAZWI_READ_VLD)) {
+		dev_err_ratelimited(hdev->dev,
+			"RAZWI event caused by illegal read of %s\n",
+			gaudi_get_razwi_initiator_name(hdev, false, engine_id_1, engine_id_2));
+		WREG32(mmMMU_UP_RAZWI_READ_VLD, 0);
+		*is_read = true;
+	}
+}
+
+static void gaudi_print_and_get_mmu_error_info(struct hl_device *hdev, u64 *addr, u64 *event_mask)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+	u32 val;
+
+	if (!(gaudi->hw_cap_initialized & HW_CAP_MMU))
+		return;
+
+	val = RREG32(mmMMU_UP_PAGE_ERROR_CAPTURE);
+	if (val & MMU_UP_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK) {
+		*addr = val & MMU_UP_PAGE_ERROR_CAPTURE_VA_49_32_MASK;
+		*addr <<= 32;
+		*addr |= RREG32(mmMMU_UP_PAGE_ERROR_CAPTURE_VA);
+
+		dev_err_ratelimited(hdev->dev, "MMU page fault on va 0x%llx\n", *addr);
+		hl_handle_page_fault(hdev, *addr, 0, true, event_mask);
+
+		WREG32(mmMMU_UP_PAGE_ERROR_CAPTURE, 0);
+	}
+
+	val = RREG32(mmMMU_UP_ACCESS_ERROR_CAPTURE);
+	if (val & MMU_UP_ACCESS_ERROR_CAPTURE_ENTRY_VALID_MASK) {
+		*addr = val & MMU_UP_ACCESS_ERROR_CAPTURE_VA_49_32_MASK;
+		*addr <<= 32;
+		*addr |= RREG32(mmMMU_UP_ACCESS_ERROR_CAPTURE_VA);
+
+		dev_err_ratelimited(hdev->dev, "MMU access error on va 0x%llx\n", *addr);
+
+		WREG32(mmMMU_UP_ACCESS_ERROR_CAPTURE, 0);
+	}
+}
+
+/*
+ *  +-------------------+------------------------------------------------------+
+ *  | Configuration Reg |                     Description                      |
+ *  |      Address      |                                                      |
+ *  +-------------------+------------------------------------------------------+
+ *  |  0xF30 - 0xF3F    |ECC single error indication (1 bit per memory wrapper)|
+ *  |                   |0xF30 memory wrappers 31:0 (MSB to LSB)               |
+ *  |                   |0xF34 memory wrappers 63:32                           |
+ *  |                   |0xF38 memory wrappers 95:64                           |
+ *  |                   |0xF3C memory wrappers 127:96                          |
+ *  +-------------------+------------------------------------------------------+
+ *  |  0xF40 - 0xF4F    |ECC double error indication (1 bit per memory wrapper)|
+ *  |                   |0xF40 memory wrappers 31:0 (MSB to LSB)               |
+ *  |                   |0xF44 memory wrappers 63:32                           |
+ *  |                   |0xF48 memory wrappers 95:64                           |
+ *  |                   |0xF4C memory wrappers 127:96                          |
+ *  +-------------------+------------------------------------------------------+
+ */
+static int gaudi_extract_ecc_info(struct hl_device *hdev,
+		struct ecc_info_extract_params *params, u64 *ecc_address,
+		u64 *ecc_syndrom, u8 *memory_wrapper_idx)
+{
+	u32 i, num_mem_regs, reg, err_bit;
+	u64 err_addr, err_word = 0;
+
+	num_mem_regs = params->num_memories / 32 +
+			((params->num_memories % 32) ? 1 : 0);
+
+	if (params->block_address >= CFG_BASE)
+		params->block_address -= CFG_BASE;
+
+	if (params->derr)
+		err_addr = params->block_address + GAUDI_ECC_DERR0_OFFSET;
+	else
+		err_addr = params->block_address + GAUDI_ECC_SERR0_OFFSET;
+
+	/* Set invalid wrapper index */
+	*memory_wrapper_idx = 0xFF;
+
+	/* Iterate through memory wrappers, a single bit must be set */
+	for (i = 0 ; i < num_mem_regs ; i++) {
+		err_addr += i * 4;
+		err_word = RREG32(err_addr);
+		if (err_word) {
+			err_bit = __ffs(err_word);
+			*memory_wrapper_idx = err_bit + (32 * i);
+			break;
+		}
+	}
+
+	if (*memory_wrapper_idx == 0xFF) {
+		dev_err(hdev->dev, "ECC error information cannot be found\n");
+		return -EINVAL;
+	}
+
+	WREG32(params->block_address + GAUDI_ECC_MEM_SEL_OFFSET,
+			*memory_wrapper_idx);
+
+	*ecc_address =
+		RREG32(params->block_address + GAUDI_ECC_ADDRESS_OFFSET);
+	*ecc_syndrom =
+		RREG32(params->block_address + GAUDI_ECC_SYNDROME_OFFSET);
+
+	/* Clear error indication */
+	reg = RREG32(params->block_address + GAUDI_ECC_MEM_INFO_CLR_OFFSET);
+	if (params->derr)
+		reg |= FIELD_PREP(GAUDI_ECC_MEM_INFO_CLR_DERR_MASK, 1);
+	else
+		reg |= FIELD_PREP(GAUDI_ECC_MEM_INFO_CLR_SERR_MASK, 1);
+
+	WREG32(params->block_address + GAUDI_ECC_MEM_INFO_CLR_OFFSET, reg);
+
+	return 0;
+}
+
+/*
+ * gaudi_queue_idx_dec - decrement queue index (pi/ci) and handle wrap
+ *
+ * @idx: the current pi/ci value
+ * @q_len: the queue length (power of 2)
+ *
+ * @return the cyclically decremented index
+ */
+static inline u32 gaudi_queue_idx_dec(u32 idx, u32 q_len)
+{
+	u32 mask = q_len - 1;
+
+	/*
+	 * modular decrement is equivalent to adding (queue_size -1)
+	 * later we take LSBs to make sure the value is in the
+	 * range [0, queue_len - 1]
+	 */
+	return (idx + q_len - 1) & mask;
+}
+
+/**
+ * gaudi_handle_sw_config_stream_data - print SW config stream data
+ *
+ * @hdev: pointer to the habanalabs device structure
+ * @stream: the QMAN's stream
+ * @qman_base: base address of QMAN registers block
+ * @event_mask: mask of the last events occurred
+ */
+static void gaudi_handle_sw_config_stream_data(struct hl_device *hdev, u32 stream,
+						u64 qman_base, u64 event_mask)
+{
+	u64 cq_ptr_lo, cq_ptr_hi, cq_tsize, cq_ptr;
+	u32 cq_ptr_lo_off, size;
+
+	cq_ptr_lo_off = mmTPC0_QM_CQ_PTR_LO_1 - mmTPC0_QM_CQ_PTR_LO_0;
+
+	cq_ptr_lo = qman_base + (mmTPC0_QM_CQ_PTR_LO_0 - mmTPC0_QM_BASE) +
+						stream * cq_ptr_lo_off;
+	cq_ptr_hi = cq_ptr_lo +
+				(mmTPC0_QM_CQ_PTR_HI_0 - mmTPC0_QM_CQ_PTR_LO_0);
+	cq_tsize = cq_ptr_lo +
+				(mmTPC0_QM_CQ_TSIZE_0 - mmTPC0_QM_CQ_PTR_LO_0);
+
+	cq_ptr = (((u64) RREG32(cq_ptr_hi)) << 32) | RREG32(cq_ptr_lo);
+	size = RREG32(cq_tsize);
+	dev_info(hdev->dev, "stop on err: stream: %u, addr: %#llx, size: %u\n",
+							stream, cq_ptr, size);
+
+	if (event_mask & HL_NOTIFIER_EVENT_UNDEFINED_OPCODE) {
+		hdev->captured_err_info.undef_opcode.cq_addr = cq_ptr;
+		hdev->captured_err_info.undef_opcode.cq_size = size;
+		hdev->captured_err_info.undef_opcode.stream_id = stream;
+	}
+}
+
+/**
+ * gaudi_handle_last_pqes_on_err - print last PQEs on error
+ *
+ * @hdev: pointer to the habanalabs device structure
+ * @qid_base: first QID of the QMAN (out of 4 streams)
+ * @stream: the QMAN's stream
+ * @qman_base: base address of QMAN registers block
+ * @event_mask: mask of the last events occurred
+ * @pr_sw_conf: if true print the SW config stream data (CQ PTR and SIZE)
+ */
+static void gaudi_handle_last_pqes_on_err(struct hl_device *hdev, u32 qid_base,
+						u32 stream, u64 qman_base,
+						u64 event_mask,
+						bool pr_sw_conf)
+{
+	u32 ci, qm_ci_stream_off, queue_len;
+	struct hl_hw_queue *q;
+	u64 pq_ci, addr[PQ_FETCHER_CACHE_SIZE];
+	int i;
+
+	q = &hdev->kernel_queues[qid_base + stream];
+
+	qm_ci_stream_off = mmTPC0_QM_PQ_CI_1 - mmTPC0_QM_PQ_CI_0;
+	pq_ci = qman_base + (mmTPC0_QM_PQ_CI_0 - mmTPC0_QM_BASE) +
+						stream * qm_ci_stream_off;
+
+	queue_len = (q->queue_type == QUEUE_TYPE_INT) ?
+					q->int_queue_len : HL_QUEUE_LENGTH;
+
+	hdev->asic_funcs->hw_queues_lock(hdev);
+
+	if (pr_sw_conf)
+		gaudi_handle_sw_config_stream_data(hdev, stream, qman_base, event_mask);
+
+	ci = RREG32(pq_ci);
+
+	/* we should start printing form ci -1 */
+	ci = gaudi_queue_idx_dec(ci, queue_len);
+	memset(addr, 0, sizeof(addr));
+
+	for (i = 0; i < PQ_FETCHER_CACHE_SIZE; i++) {
+		struct hl_bd *bd;
+		u32 len;
+
+		bd = q->kernel_address;
+		bd += ci;
+
+		len = le32_to_cpu(bd->len);
+		/* len 0 means uninitialized entry- break */
+		if (!len)
+			break;
+
+		addr[i] = le64_to_cpu(bd->ptr);
+
+		dev_info(hdev->dev, "stop on err PQE(stream %u): ci: %u, addr: %#llx, size: %u\n",
+							stream, ci, addr[i], len);
+
+		/* get previous ci, wrap if needed */
+		ci = gaudi_queue_idx_dec(ci, queue_len);
+	}
+
+	if (event_mask & HL_NOTIFIER_EVENT_UNDEFINED_OPCODE) {
+		struct undefined_opcode_info *undef_opcode = &hdev->captured_err_info.undef_opcode;
+		u32 arr_idx = undef_opcode->cb_addr_streams_len;
+
+		if (arr_idx == 0) {
+			undef_opcode->timestamp = ktime_get();
+			undef_opcode->engine_id = gaudi_queue_id_to_engine_id[qid_base];
+		}
+
+		memcpy(undef_opcode->cb_addr_streams[arr_idx], addr, sizeof(addr));
+		undef_opcode->cb_addr_streams_len++;
+	}
+
+	hdev->asic_funcs->hw_queues_unlock(hdev);
+}
+
+/**
+ * handle_qman_data_on_err - extract QMAN data on error
+ *
+ * @hdev: pointer to the habanalabs device structure
+ * @qid_base: first QID of the QMAN (out of 4 streams)
+ * @stream: the QMAN's stream
+ * @qman_base: base address of QMAN registers block
+ * @event_mask: mask of the last events occurred
+ *
+ * This function attempt to exatract as much data as possible on QMAN error.
+ * On upper CP print the SW config stream data and last 8 PQEs.
+ * On lower CP print SW config data and last PQEs of ALL 4 upper CPs
+ */
+static void handle_qman_data_on_err(struct hl_device *hdev, u32 qid_base,
+				   u32 stream, u64 qman_base, u64 event_mask)
+{
+	u32 i;
+
+	if (stream != QMAN_STREAMS) {
+		gaudi_handle_last_pqes_on_err(hdev, qid_base, stream,
+			qman_base, event_mask, true);
+		return;
+	}
+
+	/* handle Lower-CP */
+	gaudi_handle_sw_config_stream_data(hdev, stream, qman_base, event_mask);
+
+	for (i = 0; i < QMAN_STREAMS; i++)
+		gaudi_handle_last_pqes_on_err(hdev, qid_base, i,
+			qman_base, event_mask, false);
+}
+
+static void gaudi_handle_qman_err_generic(struct hl_device *hdev,
+					  const char *qm_name,
+					  u64 qman_base,
+					  u32 qid_base,
+					  u64 *event_mask)
+{
+	u32 i, j, glbl_sts_val, arb_err_val, glbl_sts_clr_val;
+	u64 glbl_sts_addr, arb_err_addr;
+	char reg_desc[32];
+
+	glbl_sts_addr = qman_base + (mmTPC0_QM_GLBL_STS1_0 - mmTPC0_QM_BASE);
+	arb_err_addr = qman_base + (mmTPC0_QM_ARB_ERR_CAUSE - mmTPC0_QM_BASE);
+
+	/* Iterate through all stream GLBL_STS1 registers + Lower CP */
+	for (i = 0 ; i < QMAN_STREAMS + 1 ; i++) {
+		glbl_sts_clr_val = 0;
+		glbl_sts_val = RREG32(glbl_sts_addr + 4 * i);
+
+		if (!glbl_sts_val)
+			continue;
+
+		if (i == QMAN_STREAMS)
+			snprintf(reg_desc, ARRAY_SIZE(reg_desc), "LowerCP");
+		else
+			snprintf(reg_desc, ARRAY_SIZE(reg_desc), "stream%u", i);
+
+		for (j = 0 ; j < GAUDI_NUM_OF_QM_ERR_CAUSE ; j++) {
+			if (glbl_sts_val & BIT(j)) {
+				dev_err_ratelimited(hdev->dev,
+						"%s %s. err cause: %s\n",
+						qm_name, reg_desc,
+						gaudi_qman_error_cause[j]);
+				glbl_sts_clr_val |= BIT(j);
+			}
+		}
+		/* check for undefined opcode */
+		if (glbl_sts_val & TPC0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK &&
+				hdev->captured_err_info.undef_opcode.write_enable) {
+			memset(&hdev->captured_err_info.undef_opcode, 0,
+						sizeof(hdev->captured_err_info.undef_opcode));
+
+			hdev->captured_err_info.undef_opcode.write_enable = false;
+			*event_mask |= HL_NOTIFIER_EVENT_UNDEFINED_OPCODE;
+		}
+
+		/* Write 1 clear errors */
+		if (!hdev->stop_on_err)
+			WREG32(glbl_sts_addr + 4 * i, glbl_sts_clr_val);
+		else
+			handle_qman_data_on_err(hdev, qid_base, i, qman_base, *event_mask);
+	}
+
+	arb_err_val = RREG32(arb_err_addr);
+
+	if (!arb_err_val)
+		return;
+
+	for (j = 0 ; j < GAUDI_NUM_OF_QM_ARB_ERR_CAUSE ; j++) {
+		if (arb_err_val & BIT(j)) {
+			dev_err_ratelimited(hdev->dev,
+					"%s ARB_ERR. err cause: %s\n",
+					qm_name,
+					gaudi_qman_arb_error_cause[j]);
+		}
+	}
+}
+
+static void gaudi_print_sm_sei_info(struct hl_device *hdev, u16 event_type,
+		struct hl_eq_sm_sei_data *sei_data)
+{
+	u32 index = event_type - GAUDI_EVENT_DMA_IF_SEI_0;
+
+	/* Flip the bits as the enum is ordered in the opposite way */
+	index = (index ^ 0x3) & 0x3;
+
+	switch (sei_data->sei_cause) {
+	case SM_SEI_SO_OVERFLOW:
+		dev_err_ratelimited(hdev->dev,
+			"%s SEI Error: SOB Group %u overflow/underflow",
+			gaudi_sync_manager_names[index],
+			le32_to_cpu(sei_data->sei_log));
+		break;
+	case SM_SEI_LBW_4B_UNALIGNED:
+		dev_err_ratelimited(hdev->dev,
+			"%s SEI Error: Unaligned 4B LBW access, monitor agent address low - %#x",
+			gaudi_sync_manager_names[index],
+			le32_to_cpu(sei_data->sei_log));
+		break;
+	case SM_SEI_AXI_RESPONSE_ERR:
+		dev_err_ratelimited(hdev->dev,
+			"%s SEI Error: AXI ID %u response error",
+			gaudi_sync_manager_names[index],
+			le32_to_cpu(sei_data->sei_log));
+		break;
+	default:
+		dev_err_ratelimited(hdev->dev, "Unknown SM SEI cause %u",
+				le32_to_cpu(sei_data->sei_log));
+		break;
+	}
+}
+
+static void gaudi_handle_ecc_event(struct hl_device *hdev, u16 event_type,
+		struct hl_eq_ecc_data *ecc_data)
+{
+	struct ecc_info_extract_params params;
+	u64 ecc_address = 0, ecc_syndrom = 0;
+	u8 index, memory_wrapper_idx = 0;
+	bool extract_info_from_fw;
+	int rc;
+
+	if (hdev->asic_prop.fw_security_enabled) {
+		extract_info_from_fw = true;
+		goto extract_ecc_info;
+	}
+
+	switch (event_type) {
+	case GAUDI_EVENT_PCIE_CORE_SERR ... GAUDI_EVENT_PCIE_PHY_DERR:
+	case GAUDI_EVENT_DMA0_SERR_ECC ... GAUDI_EVENT_MMU_DERR:
+		extract_info_from_fw = true;
+		break;
+	case GAUDI_EVENT_TPC0_SERR ... GAUDI_EVENT_TPC7_SERR:
+		index = event_type - GAUDI_EVENT_TPC0_SERR;
+		params.block_address = mmTPC0_CFG_BASE + index * TPC_CFG_OFFSET;
+		params.num_memories = 90;
+		params.derr = false;
+		extract_info_from_fw = false;
+		break;
+	case GAUDI_EVENT_TPC0_DERR ... GAUDI_EVENT_TPC7_DERR:
+		index = event_type - GAUDI_EVENT_TPC0_DERR;
+		params.block_address =
+			mmTPC0_CFG_BASE + index * TPC_CFG_OFFSET;
+		params.num_memories = 90;
+		params.derr = true;
+		extract_info_from_fw = false;
+		break;
+	case GAUDI_EVENT_MME0_ACC_SERR:
+	case GAUDI_EVENT_MME1_ACC_SERR:
+	case GAUDI_EVENT_MME2_ACC_SERR:
+	case GAUDI_EVENT_MME3_ACC_SERR:
+		index = (event_type - GAUDI_EVENT_MME0_ACC_SERR) / 4;
+		params.block_address = mmMME0_ACC_BASE + index * MME_ACC_OFFSET;
+		params.num_memories = 128;
+		params.derr = false;
+		extract_info_from_fw = false;
+		break;
+	case GAUDI_EVENT_MME0_ACC_DERR:
+	case GAUDI_EVENT_MME1_ACC_DERR:
+	case GAUDI_EVENT_MME2_ACC_DERR:
+	case GAUDI_EVENT_MME3_ACC_DERR:
+		index = (event_type - GAUDI_EVENT_MME0_ACC_DERR) / 4;
+		params.block_address = mmMME0_ACC_BASE + index * MME_ACC_OFFSET;
+		params.num_memories = 128;
+		params.derr = true;
+		extract_info_from_fw = false;
+		break;
+	case GAUDI_EVENT_MME0_SBAB_SERR:
+	case GAUDI_EVENT_MME1_SBAB_SERR:
+	case GAUDI_EVENT_MME2_SBAB_SERR:
+	case GAUDI_EVENT_MME3_SBAB_SERR:
+		index = (event_type - GAUDI_EVENT_MME0_SBAB_SERR) / 4;
+		params.block_address =
+			mmMME0_SBAB_BASE + index * MME_ACC_OFFSET;
+		params.num_memories = 33;
+		params.derr = false;
+		extract_info_from_fw = false;
+		break;
+	case GAUDI_EVENT_MME0_SBAB_DERR:
+	case GAUDI_EVENT_MME1_SBAB_DERR:
+	case GAUDI_EVENT_MME2_SBAB_DERR:
+	case GAUDI_EVENT_MME3_SBAB_DERR:
+		index = (event_type - GAUDI_EVENT_MME0_SBAB_DERR) / 4;
+		params.block_address =
+			mmMME0_SBAB_BASE + index * MME_ACC_OFFSET;
+		params.num_memories = 33;
+		params.derr = true;
+		extract_info_from_fw = false;
+		break;
+	default:
+		return;
+	}
+
+extract_ecc_info:
+	if (extract_info_from_fw) {
+		ecc_address = le64_to_cpu(ecc_data->ecc_address);
+		ecc_syndrom = le64_to_cpu(ecc_data->ecc_syndrom);
+		memory_wrapper_idx = ecc_data->memory_wrapper_idx;
+	} else {
+		rc = gaudi_extract_ecc_info(hdev, &params, &ecc_address,
+				&ecc_syndrom, &memory_wrapper_idx);
+		if (rc)
+			return;
+	}
+
+	dev_err(hdev->dev,
+		"ECC error detected. address: %#llx. Syndrom: %#llx. block id %u\n",
+		ecc_address, ecc_syndrom, memory_wrapper_idx);
+}
+
+static void gaudi_handle_qman_err(struct hl_device *hdev, u16 event_type, u64 *event_mask)
+{
+	u64 qman_base;
+	char desc[32];
+	u32 qid_base;
+	u8 index;
+
+	switch (event_type) {
+	case GAUDI_EVENT_TPC0_QM ... GAUDI_EVENT_TPC7_QM:
+		index = event_type - GAUDI_EVENT_TPC0_QM;
+		qid_base = GAUDI_QUEUE_ID_TPC_0_0 + index * QMAN_STREAMS;
+		qman_base = mmTPC0_QM_BASE + index * TPC_QMAN_OFFSET;
+		snprintf(desc, ARRAY_SIZE(desc), "%s%d", "TPC_QM", index);
+		break;
+	case GAUDI_EVENT_MME0_QM ... GAUDI_EVENT_MME2_QM:
+		if (event_type == GAUDI_EVENT_MME0_QM) {
+			index = 0;
+			qid_base = GAUDI_QUEUE_ID_MME_0_0;
+		} else { /* event_type == GAUDI_EVENT_MME2_QM */
+			index = 2;
+			qid_base = GAUDI_QUEUE_ID_MME_1_0;
+		}
+		qman_base = mmMME0_QM_BASE + index * MME_QMAN_OFFSET;
+		snprintf(desc, ARRAY_SIZE(desc), "%s%d", "MME_QM", index);
+		break;
+	case GAUDI_EVENT_DMA0_QM ... GAUDI_EVENT_DMA7_QM:
+		index = event_type - GAUDI_EVENT_DMA0_QM;
+		qid_base = GAUDI_QUEUE_ID_DMA_0_0 + index * QMAN_STREAMS;
+		/* skip GAUDI_QUEUE_ID_CPU_PQ if necessary */
+		if (index > 1)
+			qid_base++;
+		qman_base = mmDMA0_QM_BASE + index * DMA_QMAN_OFFSET;
+		snprintf(desc, ARRAY_SIZE(desc), "%s%d", "DMA_QM", index);
+		break;
+	case GAUDI_EVENT_NIC0_QM0:
+		qid_base = GAUDI_QUEUE_ID_NIC_0_0;
+		qman_base = mmNIC0_QM0_BASE;
+		snprintf(desc, ARRAY_SIZE(desc), "NIC0_QM0");
+		break;
+	case GAUDI_EVENT_NIC0_QM1:
+		qid_base = GAUDI_QUEUE_ID_NIC_1_0;
+		qman_base = mmNIC0_QM1_BASE;
+		snprintf(desc, ARRAY_SIZE(desc), "NIC0_QM1");
+		break;
+	case GAUDI_EVENT_NIC1_QM0:
+		qid_base = GAUDI_QUEUE_ID_NIC_2_0;
+		qman_base = mmNIC1_QM0_BASE;
+		snprintf(desc, ARRAY_SIZE(desc), "NIC1_QM0");
+		break;
+	case GAUDI_EVENT_NIC1_QM1:
+		qid_base = GAUDI_QUEUE_ID_NIC_3_0;
+		qman_base = mmNIC1_QM1_BASE;
+		snprintf(desc, ARRAY_SIZE(desc), "NIC1_QM1");
+		break;
+	case GAUDI_EVENT_NIC2_QM0:
+		qid_base = GAUDI_QUEUE_ID_NIC_4_0;
+		qman_base = mmNIC2_QM0_BASE;
+		snprintf(desc, ARRAY_SIZE(desc), "NIC2_QM0");
+		break;
+	case GAUDI_EVENT_NIC2_QM1:
+		qid_base = GAUDI_QUEUE_ID_NIC_5_0;
+		qman_base = mmNIC2_QM1_BASE;
+		snprintf(desc, ARRAY_SIZE(desc), "NIC2_QM1");
+		break;
+	case GAUDI_EVENT_NIC3_QM0:
+		qid_base = GAUDI_QUEUE_ID_NIC_6_0;
+		qman_base = mmNIC3_QM0_BASE;
+		snprintf(desc, ARRAY_SIZE(desc), "NIC3_QM0");
+		break;
+	case GAUDI_EVENT_NIC3_QM1:
+		qid_base = GAUDI_QUEUE_ID_NIC_7_0;
+		qman_base = mmNIC3_QM1_BASE;
+		snprintf(desc, ARRAY_SIZE(desc), "NIC3_QM1");
+		break;
+	case GAUDI_EVENT_NIC4_QM0:
+		qid_base = GAUDI_QUEUE_ID_NIC_8_0;
+		qman_base = mmNIC4_QM0_BASE;
+		snprintf(desc, ARRAY_SIZE(desc), "NIC4_QM0");
+		break;
+	case GAUDI_EVENT_NIC4_QM1:
+		qid_base = GAUDI_QUEUE_ID_NIC_9_0;
+		qman_base = mmNIC4_QM1_BASE;
+		snprintf(desc, ARRAY_SIZE(desc), "NIC4_QM1");
+		break;
+	default:
+		return;
+	}
+
+	gaudi_handle_qman_err_generic(hdev, desc, qman_base, qid_base, event_mask);
+}
+
+static void gaudi_print_irq_info(struct hl_device *hdev, u16 event_type,
+					bool check_razwi, u64 *event_mask)
+{
+	bool is_read = false, is_write = false;
+	u16 engine_id[2], num_of_razwi_eng = 0;
+	char desc[64] = "";
+	u64 razwi_addr = 0;
+	u8 razwi_flags = 0;
+
+	/*
+	 * Init engine id by default as not valid and only if razwi initiated from engine with
+	 * engine id it will get valid value.
+	 */
+	engine_id[0] = HL_RAZWI_NA_ENG_ID;
+	engine_id[1] = HL_RAZWI_NA_ENG_ID;
+
+	gaudi_get_event_desc(event_type, desc, sizeof(desc));
+	dev_err_ratelimited(hdev->dev, "Received H/W interrupt %d [\"%s\"]\n",
+		event_type, desc);
+
+	if (check_razwi) {
+		gaudi_print_and_get_razwi_info(hdev, &engine_id[0], &engine_id[1], &is_read,
+						&is_write);
+		gaudi_print_and_get_mmu_error_info(hdev, &razwi_addr, event_mask);
+
+		if (is_read)
+			razwi_flags |= HL_RAZWI_READ;
+		if (is_write)
+			razwi_flags |= HL_RAZWI_WRITE;
+
+		if (engine_id[0] != HL_RAZWI_NA_ENG_ID) {
+			if (engine_id[1] != HL_RAZWI_NA_ENG_ID)
+				num_of_razwi_eng = 2;
+			else
+				num_of_razwi_eng = 1;
+		}
+
+		if (razwi_flags)
+			hl_handle_razwi(hdev, razwi_addr, engine_id, num_of_razwi_eng,
+					razwi_flags, event_mask);
+	}
+}
+
+static void gaudi_print_out_of_sync_info(struct hl_device *hdev,
+					struct cpucp_pkt_sync_err *sync_err)
+{
+	struct hl_hw_queue *q = &hdev->kernel_queues[GAUDI_QUEUE_ID_CPU_PQ];
+
+	dev_err(hdev->dev, "Out of sync with FW, FW: pi=%u, ci=%u, LKD: pi=%u, ci=%d\n",
+		le32_to_cpu(sync_err->pi), le32_to_cpu(sync_err->ci), q->pi, atomic_read(&q->ci));
+}
+
+static void gaudi_print_fw_alive_info(struct hl_device *hdev,
+					struct hl_eq_fw_alive *fw_alive)
+{
+	dev_err(hdev->dev,
+		"FW alive report: severity=%s, process_id=%u, thread_id=%u, uptime=%llu seconds\n",
+		(fw_alive->severity == FW_ALIVE_SEVERITY_MINOR) ? "Minor" : "Critical",
+		le32_to_cpu(fw_alive->process_id),
+		le32_to_cpu(fw_alive->thread_id),
+		le64_to_cpu(fw_alive->uptime_seconds));
+}
+
+static void gaudi_print_nic_axi_irq_info(struct hl_device *hdev, u16 event_type,
+						void *data)
+{
+	char desc[64] = "", *type;
+	struct eq_nic_sei_event *eq_nic_sei = data;
+	u16 nic_id = event_type - GAUDI_EVENT_NIC_SEI_0;
+
+	switch (eq_nic_sei->axi_error_cause) {
+	case RXB:
+		type = "RXB";
+		break;
+	case RXE:
+		type = "RXE";
+		break;
+	case TXS:
+		type = "TXS";
+		break;
+	case TXE:
+		type = "TXE";
+		break;
+	case QPC_RESP:
+		type = "QPC_RESP";
+		break;
+	case NON_AXI_ERR:
+		type = "NON_AXI_ERR";
+		break;
+	case TMR:
+		type = "TMR";
+		break;
+	default:
+		dev_err(hdev->dev, "unknown NIC AXI cause %d\n",
+			eq_nic_sei->axi_error_cause);
+		type = "N/A";
+		break;
+	}
+
+	snprintf(desc, sizeof(desc), "NIC%d_%s%d", nic_id, type,
+			eq_nic_sei->id);
+	dev_err_ratelimited(hdev->dev, "Received H/W interrupt %d [\"%s\"]\n",
+		event_type, desc);
+}
+
+static int gaudi_compute_reset_late_init(struct hl_device *hdev)
+{
+	/* GAUDI doesn't support any reset except hard-reset */
+	return -EPERM;
+}
+
+static int gaudi_hbm_read_interrupts(struct hl_device *hdev, int device,
+			struct hl_eq_hbm_ecc_data *hbm_ecc_data)
+{
+	u32 base, val, val2, wr_par, rd_par, ca_par, derr, serr, type, ch;
+	int rc = 0;
+
+	if (hdev->asic_prop.fw_app_cpu_boot_dev_sts0 &
+					CPU_BOOT_DEV_STS0_HBM_ECC_EN) {
+		if (!hbm_ecc_data) {
+			dev_err(hdev->dev, "No FW ECC data");
+			return 0;
+		}
+
+		wr_par = FIELD_GET(CPUCP_PKT_HBM_ECC_INFO_WR_PAR_MASK,
+				le32_to_cpu(hbm_ecc_data->hbm_ecc_info));
+		rd_par = FIELD_GET(CPUCP_PKT_HBM_ECC_INFO_RD_PAR_MASK,
+				le32_to_cpu(hbm_ecc_data->hbm_ecc_info));
+		ca_par = FIELD_GET(CPUCP_PKT_HBM_ECC_INFO_CA_PAR_MASK,
+				le32_to_cpu(hbm_ecc_data->hbm_ecc_info));
+		derr = FIELD_GET(CPUCP_PKT_HBM_ECC_INFO_DERR_MASK,
+				le32_to_cpu(hbm_ecc_data->hbm_ecc_info));
+		serr = FIELD_GET(CPUCP_PKT_HBM_ECC_INFO_SERR_MASK,
+				le32_to_cpu(hbm_ecc_data->hbm_ecc_info));
+		type = FIELD_GET(CPUCP_PKT_HBM_ECC_INFO_TYPE_MASK,
+				le32_to_cpu(hbm_ecc_data->hbm_ecc_info));
+		ch = FIELD_GET(CPUCP_PKT_HBM_ECC_INFO_HBM_CH_MASK,
+				le32_to_cpu(hbm_ecc_data->hbm_ecc_info));
+
+		dev_err(hdev->dev,
+			"HBM%d pc%d interrupts info: WR_PAR=%d, RD_PAR=%d, CA_PAR=%d, SERR=%d, DERR=%d\n",
+			device, ch, wr_par, rd_par, ca_par, serr, derr);
+		dev_err(hdev->dev,
+			"HBM%d pc%d ECC info: 1ST_ERR_ADDR=0x%x, 1ST_ERR_TYPE=%d, SEC_CONT_CNT=%u, SEC_CNT=%d, DEC_CNT=%d\n",
+			device, ch, hbm_ecc_data->first_addr, type,
+			hbm_ecc_data->sec_cont_cnt, hbm_ecc_data->sec_cnt,
+			hbm_ecc_data->dec_cnt);
+		return 0;
+	}
+
+	if (hdev->asic_prop.fw_security_enabled) {
+		dev_info(hdev->dev, "Cannot access MC regs for ECC data while security is enabled\n");
+		return 0;
+	}
+
+	base = GAUDI_HBM_CFG_BASE + device * GAUDI_HBM_CFG_OFFSET;
+	for (ch = 0 ; ch < GAUDI_HBM_CHANNELS ; ch++) {
+		val = RREG32_MASK(base + ch * 0x1000 + 0x06C, 0x0000FFFF);
+		val = (val & 0xFF) | ((val >> 8) & 0xFF);
+		if (val) {
+			rc = -EIO;
+			dev_err(hdev->dev,
+				"HBM%d pc%d interrupts info: WR_PAR=%d, RD_PAR=%d, CA_PAR=%d, SERR=%d, DERR=%d\n",
+				device, ch * 2, val & 0x1, (val >> 1) & 0x1,
+				(val >> 2) & 0x1, (val >> 3) & 0x1,
+				(val >> 4) & 0x1);
+
+			val2 = RREG32(base + ch * 0x1000 + 0x060);
+			dev_err(hdev->dev,
+				"HBM%d pc%d ECC info: 1ST_ERR_ADDR=0x%x, 1ST_ERR_TYPE=%d, SEC_CONT_CNT=%d, SEC_CNT=%d, DEC_CNT=%d\n",
+				device, ch * 2,
+				RREG32(base + ch * 0x1000 + 0x064),
+				(val2 & 0x200) >> 9, (val2 & 0xFC00) >> 10,
+				(val2 & 0xFF0000) >> 16,
+				(val2 & 0xFF000000) >> 24);
+		}
+
+		val = RREG32_MASK(base + ch * 0x1000 + 0x07C, 0x0000FFFF);
+		val = (val & 0xFF) | ((val >> 8) & 0xFF);
+		if (val) {
+			rc = -EIO;
+			dev_err(hdev->dev,
+				"HBM%d pc%d interrupts info: WR_PAR=%d, RD_PAR=%d, CA_PAR=%d, SERR=%d, DERR=%d\n",
+				device, ch * 2 + 1, val & 0x1, (val >> 1) & 0x1,
+				(val >> 2) & 0x1, (val >> 3) & 0x1,
+				(val >> 4) & 0x1);
+
+			val2 = RREG32(base + ch * 0x1000 + 0x070);
+			dev_err(hdev->dev,
+				"HBM%d pc%d ECC info: 1ST_ERR_ADDR=0x%x, 1ST_ERR_TYPE=%d, SEC_CONT_CNT=%d, SEC_CNT=%d, DEC_CNT=%d\n",
+				device, ch * 2 + 1,
+				RREG32(base + ch * 0x1000 + 0x074),
+				(val2 & 0x200) >> 9, (val2 & 0xFC00) >> 10,
+				(val2 & 0xFF0000) >> 16,
+				(val2 & 0xFF000000) >> 24);
+		}
+
+		/* Clear interrupts */
+		RMWREG32(base + (ch * 0x1000) + 0x060, 0x1C8, 0x1FF);
+		RMWREG32(base + (ch * 0x1000) + 0x070, 0x1C8, 0x1FF);
+		WREG32(base + (ch * 0x1000) + 0x06C, 0x1F1F);
+		WREG32(base + (ch * 0x1000) + 0x07C, 0x1F1F);
+		RMWREG32(base + (ch * 0x1000) + 0x060, 0x0, 0xF);
+		RMWREG32(base + (ch * 0x1000) + 0x070, 0x0, 0xF);
+	}
+
+	val  = RREG32(base + 0x8F30);
+	val2 = RREG32(base + 0x8F34);
+	if (val | val2) {
+		rc = -EIO;
+		dev_err(hdev->dev,
+			"HBM %d MC SRAM SERR info: Reg 0x8F30=0x%x, Reg 0x8F34=0x%x\n",
+			device, val, val2);
+	}
+	val  = RREG32(base + 0x8F40);
+	val2 = RREG32(base + 0x8F44);
+	if (val | val2) {
+		rc = -EIO;
+		dev_err(hdev->dev,
+			"HBM %d MC SRAM DERR info: Reg 0x8F40=0x%x, Reg 0x8F44=0x%x\n",
+			device, val, val2);
+	}
+
+	return rc;
+}
+
+static int gaudi_hbm_event_to_dev(u16 hbm_event_type)
+{
+	switch (hbm_event_type) {
+	case GAUDI_EVENT_HBM0_SPI_0:
+	case GAUDI_EVENT_HBM0_SPI_1:
+		return 0;
+	case GAUDI_EVENT_HBM1_SPI_0:
+	case GAUDI_EVENT_HBM1_SPI_1:
+		return 1;
+	case GAUDI_EVENT_HBM2_SPI_0:
+	case GAUDI_EVENT_HBM2_SPI_1:
+		return 2;
+	case GAUDI_EVENT_HBM3_SPI_0:
+	case GAUDI_EVENT_HBM3_SPI_1:
+		return 3;
+	default:
+		break;
+	}
+
+	/* Should never happen */
+	return 0;
+}
+
+static bool gaudi_tpc_read_interrupts(struct hl_device *hdev, u8 tpc_id,
+					char *interrupt_name)
+{
+	u32 tpc_offset = tpc_id * TPC_CFG_OFFSET, tpc_interrupts_cause, i;
+	bool soft_reset_required = false;
+
+	tpc_interrupts_cause = RREG32(mmTPC0_CFG_TPC_INTR_CAUSE + tpc_offset) &
+				TPC0_CFG_TPC_INTR_CAUSE_CAUSE_MASK;
+
+	for (i = 0 ; i < GAUDI_NUM_OF_TPC_INTR_CAUSE ; i++)
+		if (tpc_interrupts_cause & BIT(i)) {
+			dev_err_ratelimited(hdev->dev,
+					"TPC%d_%s interrupt cause: %s\n",
+					tpc_id, interrupt_name,
+					gaudi_tpc_interrupts_cause[i]);
+			/* If this is QM error, we need to soft-reset */
+			if (i == 15)
+				soft_reset_required = true;
+		}
+
+	/* Clear interrupts */
+	WREG32(mmTPC0_CFG_TPC_INTR_CAUSE + tpc_offset, 0);
+
+	return soft_reset_required;
+}
+
+static int tpc_dec_event_to_tpc_id(u16 tpc_dec_event_type)
+{
+	return (tpc_dec_event_type - GAUDI_EVENT_TPC0_DEC) >> 1;
+}
+
+static int tpc_krn_event_to_tpc_id(u16 tpc_dec_event_type)
+{
+	return (tpc_dec_event_type - GAUDI_EVENT_TPC0_KRN_ERR) / 6;
+}
+
+static void gaudi_print_clk_change_info(struct hl_device *hdev, u16 event_type, u64 *event_mask)
+{
+	ktime_t zero_time = ktime_set(0, 0);
+
+	mutex_lock(&hdev->clk_throttling.lock);
+
+	switch (event_type) {
+	case GAUDI_EVENT_FIX_POWER_ENV_S:
+		hdev->clk_throttling.current_reason |= HL_CLK_THROTTLE_POWER;
+		hdev->clk_throttling.aggregated_reason |= HL_CLK_THROTTLE_POWER;
+		hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_POWER].start = ktime_get();
+		hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_POWER].end = zero_time;
+		dev_info_ratelimited(hdev->dev,
+			"Clock throttling due to power consumption\n");
+		break;
+
+	case GAUDI_EVENT_FIX_POWER_ENV_E:
+		hdev->clk_throttling.current_reason &= ~HL_CLK_THROTTLE_POWER;
+		hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_POWER].end = ktime_get();
+		dev_info_ratelimited(hdev->dev,
+			"Power envelop is safe, back to optimal clock\n");
+		break;
+
+	case GAUDI_EVENT_FIX_THERMAL_ENV_S:
+		hdev->clk_throttling.current_reason |= HL_CLK_THROTTLE_THERMAL;
+		hdev->clk_throttling.aggregated_reason |= HL_CLK_THROTTLE_THERMAL;
+		hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_THERMAL].start = ktime_get();
+		hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_THERMAL].end = zero_time;
+		*event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR;
+		dev_info_ratelimited(hdev->dev,
+			"Clock throttling due to overheating\n");
+		break;
+
+	case GAUDI_EVENT_FIX_THERMAL_ENV_E:
+		hdev->clk_throttling.current_reason &= ~HL_CLK_THROTTLE_THERMAL;
+		hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_THERMAL].end = ktime_get();
+		*event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR;
+		dev_info_ratelimited(hdev->dev,
+			"Thermal envelop is safe, back to optimal clock\n");
+		break;
+
+	default:
+		dev_err(hdev->dev, "Received invalid clock change event %d\n",
+			event_type);
+		break;
+	}
+
+	mutex_unlock(&hdev->clk_throttling.lock);
+}
+
+static void gaudi_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_entry)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+	struct hl_info_fw_err_info fw_err_info;
+	u64 data = le64_to_cpu(eq_entry->data[0]), event_mask = 0;
+	u32 ctl = le32_to_cpu(eq_entry->hdr.ctl);
+	u32 fw_fatal_err_flag = 0, flags = 0;
+	u16 event_type = ((ctl & EQ_CTL_EVENT_TYPE_MASK)
+			>> EQ_CTL_EVENT_TYPE_SHIFT);
+	bool reset_required, reset_direct = false;
+	u8 cause;
+	int rc;
+
+	if (event_type >= GAUDI_EVENT_SIZE) {
+		dev_err(hdev->dev, "Event type %u exceeds maximum of %u",
+				event_type, GAUDI_EVENT_SIZE - 1);
+		return;
+	}
+
+	gaudi->events_stat[event_type]++;
+	gaudi->events_stat_aggregate[event_type]++;
+
+	switch (event_type) {
+	case GAUDI_EVENT_PCIE_CORE_DERR:
+	case GAUDI_EVENT_PCIE_IF_DERR:
+	case GAUDI_EVENT_PCIE_PHY_DERR:
+	case GAUDI_EVENT_TPC0_DERR ... GAUDI_EVENT_TPC7_DERR:
+	case GAUDI_EVENT_MME0_ACC_DERR:
+	case GAUDI_EVENT_MME0_SBAB_DERR:
+	case GAUDI_EVENT_MME1_ACC_DERR:
+	case GAUDI_EVENT_MME1_SBAB_DERR:
+	case GAUDI_EVENT_MME2_ACC_DERR:
+	case GAUDI_EVENT_MME2_SBAB_DERR:
+	case GAUDI_EVENT_MME3_ACC_DERR:
+	case GAUDI_EVENT_MME3_SBAB_DERR:
+	case GAUDI_EVENT_DMA0_DERR_ECC ... GAUDI_EVENT_DMA7_DERR_ECC:
+		fallthrough;
+	case GAUDI_EVENT_CPU_IF_ECC_DERR:
+	case GAUDI_EVENT_PSOC_MEM_DERR:
+	case GAUDI_EVENT_PSOC_CORESIGHT_DERR:
+	case GAUDI_EVENT_SRAM0_DERR ... GAUDI_EVENT_SRAM28_DERR:
+	case GAUDI_EVENT_NIC0_DERR ... GAUDI_EVENT_NIC4_DERR:
+	case GAUDI_EVENT_DMA_IF0_DERR ... GAUDI_EVENT_DMA_IF3_DERR:
+	case GAUDI_EVENT_HBM_0_DERR ... GAUDI_EVENT_HBM_3_DERR:
+	case GAUDI_EVENT_MMU_DERR:
+	case GAUDI_EVENT_NIC0_CS_DBG_DERR ... GAUDI_EVENT_NIC4_CS_DBG_DERR:
+		gaudi_print_irq_info(hdev, event_type, true, &event_mask);
+		gaudi_handle_ecc_event(hdev, event_type, &eq_entry->ecc_data);
+		event_mask |= HL_NOTIFIER_EVENT_GENERAL_HW_ERR;
+		fw_fatal_err_flag = HL_DRV_RESET_FW_FATAL_ERR;
+		goto reset_device;
+
+	case GAUDI_EVENT_GIC500:
+	case GAUDI_EVENT_AXI_ECC:
+	case GAUDI_EVENT_L2_RAM_ECC:
+	case GAUDI_EVENT_PLL0 ... GAUDI_EVENT_PLL17:
+		gaudi_print_irq_info(hdev, event_type, false, &event_mask);
+		fw_fatal_err_flag = HL_DRV_RESET_FW_FATAL_ERR;
+		event_mask |= HL_NOTIFIER_EVENT_GENERAL_HW_ERR;
+		goto reset_device;
+
+	case GAUDI_EVENT_HBM0_SPI_0:
+	case GAUDI_EVENT_HBM1_SPI_0:
+	case GAUDI_EVENT_HBM2_SPI_0:
+	case GAUDI_EVENT_HBM3_SPI_0:
+		gaudi_print_irq_info(hdev, event_type, false, &event_mask);
+		gaudi_hbm_read_interrupts(hdev,
+				gaudi_hbm_event_to_dev(event_type),
+				&eq_entry->hbm_ecc_data);
+		fw_fatal_err_flag = HL_DRV_RESET_FW_FATAL_ERR;
+		event_mask |= HL_NOTIFIER_EVENT_GENERAL_HW_ERR;
+		goto reset_device;
+
+	case GAUDI_EVENT_HBM0_SPI_1:
+	case GAUDI_EVENT_HBM1_SPI_1:
+	case GAUDI_EVENT_HBM2_SPI_1:
+	case GAUDI_EVENT_HBM3_SPI_1:
+		gaudi_print_irq_info(hdev, event_type, false, &event_mask);
+		gaudi_hbm_read_interrupts(hdev,
+				gaudi_hbm_event_to_dev(event_type),
+				&eq_entry->hbm_ecc_data);
+		hl_fw_unmask_irq(hdev, event_type);
+		event_mask |= HL_NOTIFIER_EVENT_GENERAL_HW_ERR;
+		break;
+
+	case GAUDI_EVENT_TPC0_DEC:
+	case GAUDI_EVENT_TPC1_DEC:
+	case GAUDI_EVENT_TPC2_DEC:
+	case GAUDI_EVENT_TPC3_DEC:
+	case GAUDI_EVENT_TPC4_DEC:
+	case GAUDI_EVENT_TPC5_DEC:
+	case GAUDI_EVENT_TPC6_DEC:
+	case GAUDI_EVENT_TPC7_DEC:
+		/* In TPC DEC event, notify on TPC assertion. While there isn't
+		 * a specific event for assertion yet, the FW generates TPC DEC event.
+		 * The SW upper layer will inspect an internal mapped area to indicate
+		 * if the event is a TPC Assertion or a "real" TPC DEC.
+		 */
+		event_mask |= HL_NOTIFIER_EVENT_TPC_ASSERT;
+		gaudi_print_irq_info(hdev, event_type, true, &event_mask);
+		reset_required = gaudi_tpc_read_interrupts(hdev,
+					tpc_dec_event_to_tpc_id(event_type),
+					"AXI_SLV_DEC_Error");
+		event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR;
+		if (reset_required) {
+			dev_err(hdev->dev, "reset required due to %s\n",
+				gaudi_irq_map_table[event_type].name);
+
+			reset_direct = true;
+			goto reset_device;
+		} else {
+			hl_fw_unmask_irq(hdev, event_type);
+			event_mask |= HL_NOTIFIER_EVENT_DEVICE_RESET;
+		}
+		break;
+
+	case GAUDI_EVENT_TPC0_KRN_ERR:
+	case GAUDI_EVENT_TPC1_KRN_ERR:
+	case GAUDI_EVENT_TPC2_KRN_ERR:
+	case GAUDI_EVENT_TPC3_KRN_ERR:
+	case GAUDI_EVENT_TPC4_KRN_ERR:
+	case GAUDI_EVENT_TPC5_KRN_ERR:
+	case GAUDI_EVENT_TPC6_KRN_ERR:
+	case GAUDI_EVENT_TPC7_KRN_ERR:
+		gaudi_print_irq_info(hdev, event_type, true, &event_mask);
+		reset_required = gaudi_tpc_read_interrupts(hdev,
+					tpc_krn_event_to_tpc_id(event_type),
+					"KRN_ERR");
+		event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR;
+		if (reset_required) {
+			dev_err(hdev->dev, "reset required due to %s\n",
+				gaudi_irq_map_table[event_type].name);
+
+			reset_direct = true;
+			goto reset_device;
+		} else {
+			hl_fw_unmask_irq(hdev, event_type);
+			event_mask |= HL_NOTIFIER_EVENT_DEVICE_RESET;
+		}
+		break;
+
+	case GAUDI_EVENT_PCIE_CORE_SERR:
+	case GAUDI_EVENT_PCIE_IF_SERR:
+	case GAUDI_EVENT_PCIE_PHY_SERR:
+	case GAUDI_EVENT_TPC0_SERR ... GAUDI_EVENT_TPC7_SERR:
+	case GAUDI_EVENT_MME0_ACC_SERR:
+	case GAUDI_EVENT_MME0_SBAB_SERR:
+	case GAUDI_EVENT_MME1_ACC_SERR:
+	case GAUDI_EVENT_MME1_SBAB_SERR:
+	case GAUDI_EVENT_MME2_ACC_SERR:
+	case GAUDI_EVENT_MME2_SBAB_SERR:
+	case GAUDI_EVENT_MME3_ACC_SERR:
+	case GAUDI_EVENT_MME3_SBAB_SERR:
+	case GAUDI_EVENT_DMA0_SERR_ECC ... GAUDI_EVENT_DMA7_SERR_ECC:
+	case GAUDI_EVENT_CPU_IF_ECC_SERR:
+	case GAUDI_EVENT_PSOC_MEM_SERR:
+	case GAUDI_EVENT_PSOC_CORESIGHT_SERR:
+	case GAUDI_EVENT_SRAM0_SERR ... GAUDI_EVENT_SRAM28_SERR:
+	case GAUDI_EVENT_NIC0_SERR ... GAUDI_EVENT_NIC4_SERR:
+	case GAUDI_EVENT_DMA_IF0_SERR ... GAUDI_EVENT_DMA_IF3_SERR:
+	case GAUDI_EVENT_HBM_0_SERR ... GAUDI_EVENT_HBM_3_SERR:
+		fallthrough;
+	case GAUDI_EVENT_MMU_SERR:
+		gaudi_print_irq_info(hdev, event_type, true, &event_mask);
+		gaudi_handle_ecc_event(hdev, event_type, &eq_entry->ecc_data);
+		hl_fw_unmask_irq(hdev, event_type);
+		event_mask |= HL_NOTIFIER_EVENT_GENERAL_HW_ERR;
+		break;
+
+	case GAUDI_EVENT_PCIE_DEC:
+	case GAUDI_EVENT_CPU_AXI_SPLITTER:
+	case GAUDI_EVENT_PSOC_AXI_DEC:
+	case GAUDI_EVENT_PSOC_PRSTN_FALL:
+		gaudi_print_irq_info(hdev, event_type, true, &event_mask);
+		hl_fw_unmask_irq(hdev, event_type);
+		event_mask |= HL_NOTIFIER_EVENT_GENERAL_HW_ERR;
+		break;
+
+	case GAUDI_EVENT_MMU_PAGE_FAULT:
+	case GAUDI_EVENT_MMU_WR_PERM:
+		gaudi_print_irq_info(hdev, event_type, true, &event_mask);
+		hl_fw_unmask_irq(hdev, event_type);
+		event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR;
+		break;
+
+	case GAUDI_EVENT_MME0_WBC_RSP:
+	case GAUDI_EVENT_MME0_SBAB0_RSP:
+	case GAUDI_EVENT_MME1_WBC_RSP:
+	case GAUDI_EVENT_MME1_SBAB0_RSP:
+	case GAUDI_EVENT_MME2_WBC_RSP:
+	case GAUDI_EVENT_MME2_SBAB0_RSP:
+	case GAUDI_EVENT_MME3_WBC_RSP:
+	case GAUDI_EVENT_MME3_SBAB0_RSP:
+	case GAUDI_EVENT_RAZWI_OR_ADC:
+	case GAUDI_EVENT_MME0_QM ... GAUDI_EVENT_MME2_QM:
+	case GAUDI_EVENT_DMA0_QM ... GAUDI_EVENT_DMA7_QM:
+		fallthrough;
+	case GAUDI_EVENT_NIC0_QM0:
+	case GAUDI_EVENT_NIC0_QM1:
+	case GAUDI_EVENT_NIC1_QM0:
+	case GAUDI_EVENT_NIC1_QM1:
+	case GAUDI_EVENT_NIC2_QM0:
+	case GAUDI_EVENT_NIC2_QM1:
+	case GAUDI_EVENT_NIC3_QM0:
+	case GAUDI_EVENT_NIC3_QM1:
+	case GAUDI_EVENT_NIC4_QM0:
+	case GAUDI_EVENT_NIC4_QM1:
+	case GAUDI_EVENT_DMA0_CORE ... GAUDI_EVENT_DMA7_CORE:
+	case GAUDI_EVENT_TPC0_QM ... GAUDI_EVENT_TPC7_QM:
+		gaudi_print_irq_info(hdev, event_type, true, &event_mask);
+		gaudi_handle_qman_err(hdev, event_type, &event_mask);
+		hl_fw_unmask_irq(hdev, event_type);
+		event_mask |= (HL_NOTIFIER_EVENT_USER_ENGINE_ERR | HL_NOTIFIER_EVENT_DEVICE_RESET);
+		break;
+
+	case GAUDI_EVENT_RAZWI_OR_ADC_SW:
+		gaudi_print_irq_info(hdev, event_type, true, &event_mask);
+		event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR;
+		goto reset_device;
+
+	case GAUDI_EVENT_TPC0_BMON_SPMU:
+	case GAUDI_EVENT_TPC1_BMON_SPMU:
+	case GAUDI_EVENT_TPC2_BMON_SPMU:
+	case GAUDI_EVENT_TPC3_BMON_SPMU:
+	case GAUDI_EVENT_TPC4_BMON_SPMU:
+	case GAUDI_EVENT_TPC5_BMON_SPMU:
+	case GAUDI_EVENT_TPC6_BMON_SPMU:
+	case GAUDI_EVENT_TPC7_BMON_SPMU:
+	case GAUDI_EVENT_DMA_BM_CH0 ... GAUDI_EVENT_DMA_BM_CH7:
+		gaudi_print_irq_info(hdev, event_type, false, &event_mask);
+		hl_fw_unmask_irq(hdev, event_type);
+		event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR;
+		break;
+
+	case GAUDI_EVENT_NIC_SEI_0 ... GAUDI_EVENT_NIC_SEI_4:
+		gaudi_print_nic_axi_irq_info(hdev, event_type, &data);
+		hl_fw_unmask_irq(hdev, event_type);
+		event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR;
+		break;
+
+	case GAUDI_EVENT_DMA_IF_SEI_0 ... GAUDI_EVENT_DMA_IF_SEI_3:
+		gaudi_print_irq_info(hdev, event_type, false, &event_mask);
+		gaudi_print_sm_sei_info(hdev, event_type,
+					&eq_entry->sm_sei_data);
+		rc = hl_state_dump(hdev);
+		event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR;
+		if (rc)
+			dev_err(hdev->dev,
+				"Error during system state dump %d\n", rc);
+		hl_fw_unmask_irq(hdev, event_type);
+		break;
+
+	case GAUDI_EVENT_STATUS_NIC0_ENG0 ... GAUDI_EVENT_STATUS_NIC4_ENG1:
+		break;
+
+	case GAUDI_EVENT_FIX_POWER_ENV_S ... GAUDI_EVENT_FIX_THERMAL_ENV_E:
+		gaudi_print_clk_change_info(hdev, event_type, &event_mask);
+		hl_fw_unmask_irq(hdev, event_type);
+		break;
+
+	case GAUDI_EVENT_PSOC_GPIO_U16_0:
+		cause = le64_to_cpu(eq_entry->data[0]) & 0xFF;
+		dev_err(hdev->dev,
+			"Received high temp H/W interrupt %d (cause %d)\n",
+			event_type, cause);
+		event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR;
+		break;
+
+	case GAUDI_EVENT_DEV_RESET_REQ:
+		gaudi_print_irq_info(hdev, event_type, false, &event_mask);
+		event_mask |= HL_NOTIFIER_EVENT_GENERAL_HW_ERR;
+		goto reset_device;
+
+	case GAUDI_EVENT_PKT_QUEUE_OUT_SYNC:
+		gaudi_print_irq_info(hdev, event_type, false, &event_mask);
+		gaudi_print_out_of_sync_info(hdev, &eq_entry->pkt_sync_err);
+		event_mask |= HL_NOTIFIER_EVENT_GENERAL_HW_ERR;
+		goto reset_device;
+
+	case GAUDI_EVENT_FW_ALIVE_S:
+		gaudi_print_irq_info(hdev, event_type, false, &event_mask);
+		gaudi_print_fw_alive_info(hdev, &eq_entry->fw_alive);
+		fw_err_info.err_type = HL_INFO_FW_REPORTED_ERR;
+		fw_err_info.event_id = event_type;
+		fw_err_info.event_mask = &event_mask;
+		hl_handle_fw_err(hdev, &fw_err_info);
+		goto reset_device;
+
+	default:
+		dev_err(hdev->dev, "Received invalid H/W interrupt %d\n",
+				event_type);
+		break;
+	}
+
+	if (event_mask)
+		hl_notifier_event_send_all(hdev, event_mask);
+
+	return;
+
+reset_device:
+	reset_required = true;
+
+	if (hdev->asic_prop.fw_security_enabled && !reset_direct) {
+		flags = HL_DRV_RESET_HARD | HL_DRV_RESET_BYPASS_REQ_TO_FW | fw_fatal_err_flag;
+
+		/* notify on device unavailable while the reset triggered by fw */
+		event_mask |= (HL_NOTIFIER_EVENT_DEVICE_RESET |
+					HL_NOTIFIER_EVENT_DEVICE_UNAVAILABLE);
+	} else if (hdev->hard_reset_on_fw_events) {
+		flags = HL_DRV_RESET_HARD | HL_DRV_RESET_DELAY | fw_fatal_err_flag;
+		event_mask |= HL_NOTIFIER_EVENT_DEVICE_RESET;
+	} else {
+		reset_required = false;
+	}
+
+	if (reset_required) {
+		/* escalate general hw errors to critical/fatal error */
+		if (event_mask & HL_NOTIFIER_EVENT_GENERAL_HW_ERR)
+			hl_handle_critical_hw_err(hdev, event_type, &event_mask);
+
+		hl_device_cond_reset(hdev, flags, event_mask);
+	} else {
+		hl_fw_unmask_irq(hdev, event_type);
+		/* Notification on occurred event needs to be sent although reset is not executed */
+		if (event_mask)
+			hl_notifier_event_send_all(hdev, event_mask);
+	}
+}
+
+static void *gaudi_get_events_stat(struct hl_device *hdev, bool aggregate, u32 *size)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+
+	if (aggregate) {
+		*size = (u32) sizeof(gaudi->events_stat_aggregate);
+		return gaudi->events_stat_aggregate;
+	}
+
+	*size = (u32) sizeof(gaudi->events_stat);
+	return gaudi->events_stat;
+}
+
+static int gaudi_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard, u32 flags)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+	u32 status, timeout_usec;
+	int rc;
+
+	if (!(gaudi->hw_cap_initialized & HW_CAP_MMU) ||
+		hdev->reset_info.hard_reset_pending)
+		return 0;
+
+	if (hdev->pldm)
+		timeout_usec = GAUDI_PLDM_MMU_TIMEOUT_USEC;
+	else
+		timeout_usec = MMU_CONFIG_TIMEOUT_USEC;
+
+	/* L0 & L1 invalidation */
+	WREG32(mmSTLB_INV_PS, 3);
+	WREG32(mmSTLB_CACHE_INV, gaudi->mmu_cache_inv_pi++);
+	WREG32(mmSTLB_INV_PS, 2);
+
+	rc = hl_poll_timeout(
+		hdev,
+		mmSTLB_INV_PS,
+		status,
+		!status,
+		1000,
+		timeout_usec);
+
+	WREG32(mmSTLB_INV_SET, 0);
+
+	return rc;
+}
+
+static int gaudi_mmu_invalidate_cache_range(struct hl_device *hdev,
+						bool is_hard, u32 flags,
+						u32 asid, u64 va, u64 size)
+{
+	/* Treat as invalidate all because there is no range invalidation
+	 * in Gaudi
+	 */
+	return hdev->asic_funcs->mmu_invalidate_cache(hdev, is_hard, flags);
+}
+
+static int gaudi_mmu_update_asid_hop0_addr(struct hl_device *hdev, u32 asid, u64 phys_addr)
+{
+	u32 status, timeout_usec;
+	int rc;
+
+	if (hdev->pldm)
+		timeout_usec = GAUDI_PLDM_MMU_TIMEOUT_USEC;
+	else
+		timeout_usec = MMU_CONFIG_TIMEOUT_USEC;
+
+	WREG32(MMU_ASID, asid);
+	WREG32(MMU_HOP0_PA43_12, phys_addr >> MMU_HOP0_PA43_12_SHIFT);
+	WREG32(MMU_HOP0_PA49_44, phys_addr >> MMU_HOP0_PA49_44_SHIFT);
+	WREG32(MMU_BUSY, 0x80000000);
+
+	rc = hl_poll_timeout(
+		hdev,
+		MMU_BUSY,
+		status,
+		!(status & 0x80000000),
+		1000,
+		timeout_usec);
+
+	if (rc) {
+		dev_err(hdev->dev,
+			"Timeout during MMU hop0 config of asid %d\n", asid);
+		return rc;
+	}
+
+	return 0;
+}
+
+static int gaudi_send_heartbeat(struct hl_device *hdev)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+
+	if (!(gaudi->hw_cap_initialized & HW_CAP_CPU_Q))
+		return 0;
+
+	return hl_fw_send_heartbeat(hdev);
+}
+
+static int gaudi_cpucp_info_get(struct hl_device *hdev)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	int rc;
+
+	if (!(gaudi->hw_cap_initialized & HW_CAP_CPU_Q))
+		return 0;
+
+	rc = hl_fw_cpucp_handshake(hdev, mmCPU_BOOT_DEV_STS0,
+					mmCPU_BOOT_DEV_STS1, mmCPU_BOOT_ERR0,
+					mmCPU_BOOT_ERR1);
+	if (rc)
+		return rc;
+
+	if (!strlen(prop->cpucp_info.card_name))
+		strscpy_pad(prop->cpucp_info.card_name, GAUDI_DEFAULT_CARD_NAME,
+				CARD_NAME_MAX_LEN);
+
+	hdev->card_type = le32_to_cpu(hdev->asic_prop.cpucp_info.card_type);
+
+	set_default_power_values(hdev);
+
+	return 0;
+}
+
+static bool gaudi_is_device_idle(struct hl_device *hdev, u64 *mask_arr, u8 mask_len,
+		struct engines_data *e)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+	const char *fmt = "%-5d%-9s%#-14x%#-12x%#x\n";
+	const char *mme_slave_fmt = "%-5d%-9s%-14s%-12s%#x\n";
+	const char *nic_fmt = "%-5d%-9s%#-14x%#x\n";
+	unsigned long *mask = (unsigned long *)mask_arr;
+	u32 qm_glbl_sts0, qm_cgm_sts, dma_core_sts0, tpc_cfg_sts, mme_arch_sts;
+	bool is_idle = true, is_eng_idle, is_slave;
+	u64 offset;
+	int i, dma_id, port;
+
+	if (e)
+		hl_engine_data_sprintf(e,
+			"\nDMA  is_idle  QM_GLBL_STS0  QM_CGM_STS  DMA_CORE_STS0\n"
+			"---  -------  ------------  ----------  -------------\n");
+
+	for (i = 0 ; i < DMA_NUMBER_OF_CHNLS ; i++) {
+		dma_id = gaudi_dma_assignment[i];
+		offset = dma_id * DMA_QMAN_OFFSET;
+
+		qm_glbl_sts0 = RREG32(mmDMA0_QM_GLBL_STS0 + offset);
+		qm_cgm_sts = RREG32(mmDMA0_QM_CGM_STS + offset);
+		dma_core_sts0 = RREG32(mmDMA0_CORE_STS0 + offset);
+		is_eng_idle = IS_QM_IDLE(qm_glbl_sts0, qm_cgm_sts) &&
+				IS_DMA_IDLE(dma_core_sts0);
+		is_idle &= is_eng_idle;
+
+		if (mask && !is_eng_idle)
+			set_bit(GAUDI_ENGINE_ID_DMA_0 + dma_id, mask);
+		if (e)
+			hl_engine_data_sprintf(e, fmt, dma_id,
+				is_eng_idle ? "Y" : "N", qm_glbl_sts0,
+				qm_cgm_sts, dma_core_sts0);
+	}
+
+	if (e)
+		hl_engine_data_sprintf(e,
+			"\nTPC  is_idle  QM_GLBL_STS0  QM_CGM_STS  CFG_STATUS\n"
+			"---  -------  ------------  ----------  ----------\n");
+
+	for (i = 0 ; i < TPC_NUMBER_OF_ENGINES ; i++) {
+		offset = i * TPC_QMAN_OFFSET;
+		qm_glbl_sts0 = RREG32(mmTPC0_QM_GLBL_STS0 + offset);
+		qm_cgm_sts = RREG32(mmTPC0_QM_CGM_STS + offset);
+		tpc_cfg_sts = RREG32(mmTPC0_CFG_STATUS + offset);
+		is_eng_idle = IS_QM_IDLE(qm_glbl_sts0, qm_cgm_sts) &&
+				IS_TPC_IDLE(tpc_cfg_sts);
+		is_idle &= is_eng_idle;
+
+		if (mask && !is_eng_idle)
+			set_bit(GAUDI_ENGINE_ID_TPC_0 + i, mask);
+		if (e)
+			hl_engine_data_sprintf(e, fmt, i,
+				is_eng_idle ? "Y" : "N",
+				qm_glbl_sts0, qm_cgm_sts, tpc_cfg_sts);
+	}
+
+	if (e)
+		hl_engine_data_sprintf(e,
+			"\nMME  is_idle  QM_GLBL_STS0  QM_CGM_STS  ARCH_STATUS\n"
+			"---  -------  ------------  ----------  -----------\n");
+
+	for (i = 0 ; i < MME_NUMBER_OF_ENGINES ; i++) {
+		offset = i * MME_QMAN_OFFSET;
+		mme_arch_sts = RREG32(mmMME0_CTRL_ARCH_STATUS + offset);
+		is_eng_idle = IS_MME_IDLE(mme_arch_sts);
+
+		/* MME 1 & 3 are slaves, no need to check their QMANs */
+		is_slave = i % 2;
+		if (!is_slave) {
+			qm_glbl_sts0 = RREG32(mmMME0_QM_GLBL_STS0 + offset);
+			qm_cgm_sts = RREG32(mmMME0_QM_CGM_STS + offset);
+			is_eng_idle &= IS_QM_IDLE(qm_glbl_sts0, qm_cgm_sts);
+		}
+
+		is_idle &= is_eng_idle;
+
+		if (mask && !is_eng_idle)
+			set_bit(GAUDI_ENGINE_ID_MME_0 + i, mask);
+		if (e) {
+			if (!is_slave)
+				hl_engine_data_sprintf(e, fmt, i,
+					is_eng_idle ? "Y" : "N",
+					qm_glbl_sts0, qm_cgm_sts, mme_arch_sts);
+			else
+				hl_engine_data_sprintf(e, mme_slave_fmt, i,
+					is_eng_idle ? "Y" : "N", "-",
+					"-", mme_arch_sts);
+		}
+	}
+
+	if (e)
+		hl_engine_data_sprintf(e,
+				"\nNIC  is_idle  QM_GLBL_STS0  QM_CGM_STS\n"
+				"---  -------  ------------  ----------\n");
+
+	for (i = 0 ; i < (NIC_NUMBER_OF_ENGINES / 2) ; i++) {
+		offset = i * NIC_MACRO_QMAN_OFFSET;
+		port = 2 * i;
+		if (gaudi->hw_cap_initialized & BIT(HW_CAP_NIC_SHIFT + port)) {
+			qm_glbl_sts0 = RREG32(mmNIC0_QM0_GLBL_STS0 + offset);
+			qm_cgm_sts = RREG32(mmNIC0_QM0_CGM_STS + offset);
+			is_eng_idle = IS_QM_IDLE(qm_glbl_sts0, qm_cgm_sts);
+			is_idle &= is_eng_idle;
+
+			if (mask && !is_eng_idle)
+				set_bit(GAUDI_ENGINE_ID_NIC_0 + port, mask);
+			if (e)
+				hl_engine_data_sprintf(e, nic_fmt, port,
+						is_eng_idle ? "Y" : "N",
+						qm_glbl_sts0, qm_cgm_sts);
+		}
+
+		port = 2 * i + 1;
+		if (gaudi->hw_cap_initialized & BIT(HW_CAP_NIC_SHIFT + port)) {
+			qm_glbl_sts0 = RREG32(mmNIC0_QM1_GLBL_STS0 + offset);
+			qm_cgm_sts = RREG32(mmNIC0_QM1_CGM_STS + offset);
+			is_eng_idle = IS_QM_IDLE(qm_glbl_sts0, qm_cgm_sts);
+			is_idle &= is_eng_idle;
+
+			if (mask && !is_eng_idle)
+				set_bit(GAUDI_ENGINE_ID_NIC_0 + port, mask);
+			if (e)
+				hl_engine_data_sprintf(e, nic_fmt, port,
+						is_eng_idle ? "Y" : "N",
+						qm_glbl_sts0, qm_cgm_sts);
+		}
+	}
+
+	if (e)
+		hl_engine_data_sprintf(e, "\n");
+
+	return is_idle;
+}
+
+static void gaudi_hw_queues_lock(struct hl_device *hdev)
+	__acquires(&gaudi->hw_queues_lock)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+
+	spin_lock(&gaudi->hw_queues_lock);
+}
+
+static void gaudi_hw_queues_unlock(struct hl_device *hdev)
+	__releases(&gaudi->hw_queues_lock)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+
+	spin_unlock(&gaudi->hw_queues_lock);
+}
+
+static u32 gaudi_get_pci_id(struct hl_device *hdev)
+{
+	return hdev->pdev->device;
+}
+
+static int gaudi_get_eeprom_data(struct hl_device *hdev, void *data,
+				size_t max_size)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+
+	if (!(gaudi->hw_cap_initialized & HW_CAP_CPU_Q))
+		return 0;
+
+	return hl_fw_get_eeprom_data(hdev, data, max_size);
+}
+
+static int gaudi_get_monitor_dump(struct hl_device *hdev, void *data)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+
+	if (!(gaudi->hw_cap_initialized & HW_CAP_CPU_Q))
+		return 0;
+
+	return hl_fw_get_monitor_dump(hdev, data);
+}
+
+/*
+ * this function should be used only during initialization and/or after reset,
+ * when there are no active users.
+ */
+static int gaudi_run_tpc_kernel(struct hl_device *hdev, u64 tpc_kernel,	u32 tpc_id)
+{
+	u64 kernel_timeout;
+	u32 status, offset;
+	int rc;
+
+	offset = tpc_id * (mmTPC1_CFG_STATUS - mmTPC0_CFG_STATUS);
+
+	if (hdev->pldm)
+		kernel_timeout = GAUDI_PLDM_TPC_KERNEL_WAIT_USEC;
+	else
+		kernel_timeout = HL_DEVICE_TIMEOUT_USEC;
+
+	WREG32(mmTPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW + offset,
+			lower_32_bits(tpc_kernel));
+	WREG32(mmTPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH + offset,
+			upper_32_bits(tpc_kernel));
+
+	WREG32(mmTPC0_CFG_ICACHE_BASE_ADDERESS_LOW + offset,
+			lower_32_bits(tpc_kernel));
+	WREG32(mmTPC0_CFG_ICACHE_BASE_ADDERESS_HIGH + offset,
+			upper_32_bits(tpc_kernel));
+	/* set a valid LUT pointer, content is of no significance */
+	WREG32(mmTPC0_CFG_LUT_FUNC256_BASE_ADDR_LO + offset,
+			lower_32_bits(tpc_kernel));
+	WREG32(mmTPC0_CFG_LUT_FUNC256_BASE_ADDR_HI + offset,
+			upper_32_bits(tpc_kernel));
+
+	WREG32(mmTPC0_CFG_QM_SYNC_OBJECT_ADDR + offset,
+			lower_32_bits(CFG_BASE +
+				mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0));
+
+	WREG32(mmTPC0_CFG_TPC_CMD + offset,
+			(1 << TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_SHIFT |
+			1 << TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_SHIFT));
+	/* wait a bit for the engine to start executing */
+	usleep_range(1000, 1500);
+
+	/* wait until engine has finished executing */
+	rc = hl_poll_timeout(
+		hdev,
+		mmTPC0_CFG_STATUS + offset,
+		status,
+		(status & TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK) ==
+				TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK,
+		1000,
+		kernel_timeout);
+
+	if (rc) {
+		dev_err(hdev->dev,
+			"Timeout while waiting for TPC%d icache prefetch\n",
+			tpc_id);
+		return -EIO;
+	}
+
+	WREG32(mmTPC0_CFG_TPC_EXECUTE + offset,
+			1 << TPC0_CFG_TPC_EXECUTE_V_SHIFT);
+
+	/* wait a bit for the engine to start executing */
+	usleep_range(1000, 1500);
+
+	/* wait until engine has finished executing */
+	rc = hl_poll_timeout(
+		hdev,
+		mmTPC0_CFG_STATUS + offset,
+		status,
+		(status & TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK) ==
+				TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK,
+		1000,
+		kernel_timeout);
+
+	if (rc) {
+		dev_err(hdev->dev,
+			"Timeout while waiting for TPC%d vector pipe\n",
+			tpc_id);
+		return -EIO;
+	}
+
+	rc = hl_poll_timeout(
+		hdev,
+		mmTPC0_CFG_WQ_INFLIGHT_CNTR + offset,
+		status,
+		(status == 0),
+		1000,
+		kernel_timeout);
+
+	if (rc) {
+		dev_err(hdev->dev,
+			"Timeout while waiting for TPC%d kernel to execute\n",
+			tpc_id);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int gaudi_internal_cb_pool_init(struct hl_device *hdev,
+		struct hl_ctx *ctx)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+	int min_alloc_order, rc, collective_cb_size;
+
+	if (!(gaudi->hw_cap_initialized & HW_CAP_MMU))
+		return 0;
+
+	hdev->internal_cb_pool_virt_addr = hl_asic_dma_alloc_coherent(hdev,
+							HOST_SPACE_INTERNAL_CB_SZ,
+							&hdev->internal_cb_pool_dma_addr,
+							GFP_KERNEL | __GFP_ZERO);
+
+	if (!hdev->internal_cb_pool_virt_addr)
+		return -ENOMEM;
+
+	collective_cb_size = sizeof(struct packet_msg_short) * 5 +
+			sizeof(struct packet_fence);
+	min_alloc_order = ilog2(collective_cb_size);
+
+	hdev->internal_cb_pool = gen_pool_create(min_alloc_order, -1);
+	if (!hdev->internal_cb_pool) {
+		dev_err(hdev->dev,
+			"Failed to create internal CB pool\n");
+		rc = -ENOMEM;
+		goto free_internal_cb_pool;
+	}
+
+	rc = gen_pool_add(hdev->internal_cb_pool,
+				(uintptr_t) hdev->internal_cb_pool_virt_addr,
+				HOST_SPACE_INTERNAL_CB_SZ, -1);
+	if (rc) {
+		dev_err(hdev->dev,
+			"Failed to add memory to internal CB pool\n");
+		rc = -EFAULT;
+		goto destroy_internal_cb_pool;
+	}
+
+	hdev->internal_cb_va_base = hl_reserve_va_block(hdev, ctx,
+			HL_VA_RANGE_TYPE_HOST, HOST_SPACE_INTERNAL_CB_SZ,
+			HL_MMU_VA_ALIGNMENT_NOT_NEEDED);
+
+	if (!hdev->internal_cb_va_base) {
+		rc = -ENOMEM;
+		goto destroy_internal_cb_pool;
+	}
+
+	mutex_lock(&hdev->mmu_lock);
+
+	rc = hl_mmu_map_contiguous(ctx, hdev->internal_cb_va_base,
+			hdev->internal_cb_pool_dma_addr,
+			HOST_SPACE_INTERNAL_CB_SZ);
+	if (rc)
+		goto unreserve_internal_cb_pool;
+
+	rc = hl_mmu_invalidate_cache(hdev, false, MMU_OP_USERPTR);
+	if (rc)
+		goto unmap_internal_cb_pool;
+
+	mutex_unlock(&hdev->mmu_lock);
+
+	return 0;
+
+unmap_internal_cb_pool:
+	hl_mmu_unmap_contiguous(ctx, hdev->internal_cb_va_base,
+			HOST_SPACE_INTERNAL_CB_SZ);
+unreserve_internal_cb_pool:
+	mutex_unlock(&hdev->mmu_lock);
+	hl_unreserve_va_block(hdev, ctx, hdev->internal_cb_va_base,
+			HOST_SPACE_INTERNAL_CB_SZ);
+destroy_internal_cb_pool:
+	gen_pool_destroy(hdev->internal_cb_pool);
+free_internal_cb_pool:
+	hl_asic_dma_free_coherent(hdev, HOST_SPACE_INTERNAL_CB_SZ, hdev->internal_cb_pool_virt_addr,
+					hdev->internal_cb_pool_dma_addr);
+
+	return rc;
+}
+
+static void gaudi_internal_cb_pool_fini(struct hl_device *hdev,
+		struct hl_ctx *ctx)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+
+	if (!(gaudi->hw_cap_initialized & HW_CAP_MMU))
+		return;
+
+	mutex_lock(&hdev->mmu_lock);
+	hl_mmu_unmap_contiguous(ctx, hdev->internal_cb_va_base,
+			HOST_SPACE_INTERNAL_CB_SZ);
+	hl_unreserve_va_block(hdev, ctx, hdev->internal_cb_va_base,
+			HOST_SPACE_INTERNAL_CB_SZ);
+	hl_mmu_invalidate_cache(hdev, true, MMU_OP_USERPTR);
+	mutex_unlock(&hdev->mmu_lock);
+
+	gen_pool_destroy(hdev->internal_cb_pool);
+
+	hl_asic_dma_free_coherent(hdev, HOST_SPACE_INTERNAL_CB_SZ, hdev->internal_cb_pool_virt_addr,
+					hdev->internal_cb_pool_dma_addr);
+}
+
+static int gaudi_ctx_init(struct hl_ctx *ctx)
+{
+	int rc;
+
+	if (ctx->asid == HL_KERNEL_ASID_ID)
+		return 0;
+
+	rc = gaudi_internal_cb_pool_init(ctx->hdev, ctx);
+	if (rc)
+		return rc;
+
+	rc = gaudi_restore_user_registers(ctx->hdev);
+	if (rc)
+		gaudi_internal_cb_pool_fini(ctx->hdev, ctx);
+
+	return rc;
+}
+
+static void gaudi_ctx_fini(struct hl_ctx *ctx)
+{
+	if (ctx->asid == HL_KERNEL_ASID_ID)
+		return;
+
+	gaudi_internal_cb_pool_fini(ctx->hdev, ctx);
+}
+
+static int gaudi_pre_schedule_cs(struct hl_cs *cs)
+{
+	return 0;
+}
+
+static u32 gaudi_get_queue_id_for_cq(struct hl_device *hdev, u32 cq_idx)
+{
+	return gaudi_cq_assignment[cq_idx];
+}
+
+static u32 gaudi_get_signal_cb_size(struct hl_device *hdev)
+{
+	return sizeof(struct packet_msg_short) +
+			sizeof(struct packet_msg_prot) * 2;
+}
+
+static u32 gaudi_get_wait_cb_size(struct hl_device *hdev)
+{
+	return sizeof(struct packet_msg_short) * 4 +
+			sizeof(struct packet_fence) +
+			sizeof(struct packet_msg_prot) * 2;
+}
+
+static u32 gaudi_get_sob_addr(struct hl_device *hdev, u32 sob_id)
+{
+	return mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0 + (sob_id * 4);
+}
+
+static u32 gaudi_gen_signal_cb(struct hl_device *hdev, void *data, u16 sob_id,
+				u32 size, bool eb)
+{
+	struct hl_cb *cb = (struct hl_cb *) data;
+	struct packet_msg_short *pkt;
+	u32 value, ctl, pkt_size = sizeof(*pkt);
+
+	pkt = cb->kernel_address + size;
+	memset(pkt, 0, pkt_size);
+
+	/* Inc by 1, Mode ADD */
+	value = FIELD_PREP(GAUDI_PKT_SHORT_VAL_SOB_SYNC_VAL_MASK, 1);
+	value |= FIELD_PREP(GAUDI_PKT_SHORT_VAL_SOB_MOD_MASK, 1);
+
+	ctl = FIELD_PREP(GAUDI_PKT_SHORT_CTL_ADDR_MASK, sob_id * 4);
+	ctl |= FIELD_PREP(GAUDI_PKT_SHORT_CTL_OP_MASK, 0); /* write the value */
+	ctl |= FIELD_PREP(GAUDI_PKT_SHORT_CTL_BASE_MASK, 3); /* W_S SOB base */
+	ctl |= FIELD_PREP(GAUDI_PKT_CTL_OPCODE_MASK, PACKET_MSG_SHORT);
+	ctl |= FIELD_PREP(GAUDI_PKT_CTL_EB_MASK, eb);
+	ctl |= FIELD_PREP(GAUDI_PKT_CTL_RB_MASK, 1);
+	ctl |= FIELD_PREP(GAUDI_PKT_CTL_MB_MASK, 1);
+
+	pkt->value = cpu_to_le32(value);
+	pkt->ctl = cpu_to_le32(ctl);
+
+	return size + pkt_size;
+}
+
+static u32 gaudi_add_mon_msg_short(struct packet_msg_short *pkt, u32 value,
+					u16 addr)
+{
+	u32 ctl, pkt_size = sizeof(*pkt);
+
+	memset(pkt, 0, pkt_size);
+
+	ctl = FIELD_PREP(GAUDI_PKT_SHORT_CTL_ADDR_MASK, addr);
+	ctl |= FIELD_PREP(GAUDI_PKT_SHORT_CTL_BASE_MASK, 2);  /* W_S MON base */
+	ctl |= FIELD_PREP(GAUDI_PKT_CTL_OPCODE_MASK, PACKET_MSG_SHORT);
+	ctl |= FIELD_PREP(GAUDI_PKT_CTL_EB_MASK, 0);
+	ctl |= FIELD_PREP(GAUDI_PKT_CTL_RB_MASK, 1);
+	ctl |= FIELD_PREP(GAUDI_PKT_CTL_MB_MASK, 0); /* last pkt MB */
+
+	pkt->value = cpu_to_le32(value);
+	pkt->ctl = cpu_to_le32(ctl);
+
+	return pkt_size;
+}
+
+static u32 gaudi_add_arm_monitor_pkt(struct hl_device *hdev,
+		struct packet_msg_short *pkt, u16 sob_base, u8 sob_mask,
+		u16 sob_val, u16 mon_id)
+{
+	u64 monitor_base;
+	u32 ctl, value, pkt_size = sizeof(*pkt);
+	u16 msg_addr_offset;
+	u8 mask;
+
+	if (hl_gen_sob_mask(sob_base, sob_mask, &mask)) {
+		dev_err(hdev->dev,
+			"sob_base %u (mask %#x) is not valid\n",
+			sob_base, sob_mask);
+		return 0;
+	}
+
+	/*
+	 * monitor_base should be the content of the base0 address registers,
+	 * so it will be added to the msg short offsets
+	 */
+	monitor_base = mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0;
+
+	msg_addr_offset =
+		(mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0 + mon_id * 4) -
+				monitor_base;
+
+	memset(pkt, 0, pkt_size);
+
+	/* Monitor config packet: bind the monitor to a sync object */
+	value = FIELD_PREP(GAUDI_PKT_SHORT_VAL_MON_SYNC_GID_MASK, sob_base / 8);
+	value |= FIELD_PREP(GAUDI_PKT_SHORT_VAL_MON_SYNC_VAL_MASK, sob_val);
+	value |= FIELD_PREP(GAUDI_PKT_SHORT_VAL_MON_MODE_MASK,
+			0); /* GREATER OR EQUAL*/
+	value |= FIELD_PREP(GAUDI_PKT_SHORT_VAL_MON_MASK_MASK, mask);
+
+	ctl = FIELD_PREP(GAUDI_PKT_SHORT_CTL_ADDR_MASK, msg_addr_offset);
+	ctl |= FIELD_PREP(GAUDI_PKT_SHORT_CTL_OP_MASK, 0); /* write the value */
+	ctl |= FIELD_PREP(GAUDI_PKT_SHORT_CTL_BASE_MASK, 2); /* W_S MON base */
+	ctl |= FIELD_PREP(GAUDI_PKT_CTL_OPCODE_MASK, PACKET_MSG_SHORT);
+	ctl |= FIELD_PREP(GAUDI_PKT_CTL_EB_MASK, 0);
+	ctl |= FIELD_PREP(GAUDI_PKT_CTL_RB_MASK, 1);
+	ctl |= FIELD_PREP(GAUDI_PKT_CTL_MB_MASK, 1);
+
+	pkt->value = cpu_to_le32(value);
+	pkt->ctl = cpu_to_le32(ctl);
+
+	return pkt_size;
+}
+
+static u32 gaudi_add_fence_pkt(struct packet_fence *pkt)
+{
+	u32 ctl, cfg, pkt_size = sizeof(*pkt);
+
+	memset(pkt, 0, pkt_size);
+
+	cfg = FIELD_PREP(GAUDI_PKT_FENCE_CFG_DEC_VAL_MASK, 1);
+	cfg |= FIELD_PREP(GAUDI_PKT_FENCE_CFG_TARGET_VAL_MASK, 1);
+	cfg |= FIELD_PREP(GAUDI_PKT_FENCE_CFG_ID_MASK, 2);
+
+	ctl = FIELD_PREP(GAUDI_PKT_CTL_OPCODE_MASK, PACKET_FENCE);
+	ctl |= FIELD_PREP(GAUDI_PKT_CTL_EB_MASK, 0);
+	ctl |= FIELD_PREP(GAUDI_PKT_CTL_RB_MASK, 1);
+	ctl |= FIELD_PREP(GAUDI_PKT_CTL_MB_MASK, 1);
+
+	pkt->cfg = cpu_to_le32(cfg);
+	pkt->ctl = cpu_to_le32(ctl);
+
+	return pkt_size;
+}
+
+static int gaudi_get_fence_addr(struct hl_device *hdev, u32 queue_id, u64 *addr)
+{
+	u32 offset, nic_index;
+
+	switch (queue_id) {
+	case GAUDI_QUEUE_ID_DMA_0_0:
+		offset = mmDMA0_QM_CP_FENCE2_RDATA_0;
+		break;
+	case GAUDI_QUEUE_ID_DMA_0_1:
+		offset = mmDMA0_QM_CP_FENCE2_RDATA_1;
+		break;
+	case GAUDI_QUEUE_ID_DMA_0_2:
+		offset = mmDMA0_QM_CP_FENCE2_RDATA_2;
+		break;
+	case GAUDI_QUEUE_ID_DMA_0_3:
+		offset = mmDMA0_QM_CP_FENCE2_RDATA_3;
+		break;
+	case GAUDI_QUEUE_ID_DMA_1_0:
+		offset = mmDMA1_QM_CP_FENCE2_RDATA_0;
+		break;
+	case GAUDI_QUEUE_ID_DMA_1_1:
+		offset = mmDMA1_QM_CP_FENCE2_RDATA_1;
+		break;
+	case GAUDI_QUEUE_ID_DMA_1_2:
+		offset = mmDMA1_QM_CP_FENCE2_RDATA_2;
+		break;
+	case GAUDI_QUEUE_ID_DMA_1_3:
+		offset = mmDMA1_QM_CP_FENCE2_RDATA_3;
+		break;
+	case GAUDI_QUEUE_ID_DMA_5_0:
+		offset = mmDMA5_QM_CP_FENCE2_RDATA_0;
+		break;
+	case GAUDI_QUEUE_ID_DMA_5_1:
+		offset = mmDMA5_QM_CP_FENCE2_RDATA_1;
+		break;
+	case GAUDI_QUEUE_ID_DMA_5_2:
+		offset = mmDMA5_QM_CP_FENCE2_RDATA_2;
+		break;
+	case GAUDI_QUEUE_ID_DMA_5_3:
+		offset = mmDMA5_QM_CP_FENCE2_RDATA_3;
+		break;
+	case GAUDI_QUEUE_ID_TPC_7_0:
+		offset = mmTPC7_QM_CP_FENCE2_RDATA_0;
+		break;
+	case GAUDI_QUEUE_ID_TPC_7_1:
+		offset = mmTPC7_QM_CP_FENCE2_RDATA_1;
+		break;
+	case GAUDI_QUEUE_ID_TPC_7_2:
+		offset = mmTPC7_QM_CP_FENCE2_RDATA_2;
+		break;
+	case GAUDI_QUEUE_ID_TPC_7_3:
+		offset = mmTPC7_QM_CP_FENCE2_RDATA_3;
+		break;
+	case GAUDI_QUEUE_ID_NIC_0_0:
+	case GAUDI_QUEUE_ID_NIC_1_0:
+	case GAUDI_QUEUE_ID_NIC_2_0:
+	case GAUDI_QUEUE_ID_NIC_3_0:
+	case GAUDI_QUEUE_ID_NIC_4_0:
+	case GAUDI_QUEUE_ID_NIC_5_0:
+	case GAUDI_QUEUE_ID_NIC_6_0:
+	case GAUDI_QUEUE_ID_NIC_7_0:
+	case GAUDI_QUEUE_ID_NIC_8_0:
+	case GAUDI_QUEUE_ID_NIC_9_0:
+		nic_index = (queue_id - GAUDI_QUEUE_ID_NIC_0_0) >> 2;
+		offset = mmNIC0_QM0_CP_FENCE2_RDATA_0 +
+				(nic_index >> 1) * NIC_MACRO_QMAN_OFFSET +
+				(nic_index & 0x1) * NIC_ENGINE_QMAN_OFFSET;
+		break;
+	case GAUDI_QUEUE_ID_NIC_0_1:
+	case GAUDI_QUEUE_ID_NIC_1_1:
+	case GAUDI_QUEUE_ID_NIC_2_1:
+	case GAUDI_QUEUE_ID_NIC_3_1:
+	case GAUDI_QUEUE_ID_NIC_4_1:
+	case GAUDI_QUEUE_ID_NIC_5_1:
+	case GAUDI_QUEUE_ID_NIC_6_1:
+	case GAUDI_QUEUE_ID_NIC_7_1:
+	case GAUDI_QUEUE_ID_NIC_8_1:
+	case GAUDI_QUEUE_ID_NIC_9_1:
+		nic_index = (queue_id - GAUDI_QUEUE_ID_NIC_0_1) >> 2;
+		offset = mmNIC0_QM0_CP_FENCE2_RDATA_1 +
+				(nic_index >> 1) * NIC_MACRO_QMAN_OFFSET +
+				(nic_index & 0x1) * NIC_ENGINE_QMAN_OFFSET;
+		break;
+	case GAUDI_QUEUE_ID_NIC_0_2:
+	case GAUDI_QUEUE_ID_NIC_1_2:
+	case GAUDI_QUEUE_ID_NIC_2_2:
+	case GAUDI_QUEUE_ID_NIC_3_2:
+	case GAUDI_QUEUE_ID_NIC_4_2:
+	case GAUDI_QUEUE_ID_NIC_5_2:
+	case GAUDI_QUEUE_ID_NIC_6_2:
+	case GAUDI_QUEUE_ID_NIC_7_2:
+	case GAUDI_QUEUE_ID_NIC_8_2:
+	case GAUDI_QUEUE_ID_NIC_9_2:
+		nic_index = (queue_id - GAUDI_QUEUE_ID_NIC_0_2) >> 2;
+		offset = mmNIC0_QM0_CP_FENCE2_RDATA_2 +
+				(nic_index >> 1) * NIC_MACRO_QMAN_OFFSET +
+				(nic_index & 0x1) * NIC_ENGINE_QMAN_OFFSET;
+		break;
+	case GAUDI_QUEUE_ID_NIC_0_3:
+	case GAUDI_QUEUE_ID_NIC_1_3:
+	case GAUDI_QUEUE_ID_NIC_2_3:
+	case GAUDI_QUEUE_ID_NIC_3_3:
+	case GAUDI_QUEUE_ID_NIC_4_3:
+	case GAUDI_QUEUE_ID_NIC_5_3:
+	case GAUDI_QUEUE_ID_NIC_6_3:
+	case GAUDI_QUEUE_ID_NIC_7_3:
+	case GAUDI_QUEUE_ID_NIC_8_3:
+	case GAUDI_QUEUE_ID_NIC_9_3:
+		nic_index = (queue_id - GAUDI_QUEUE_ID_NIC_0_3) >> 2;
+		offset = mmNIC0_QM0_CP_FENCE2_RDATA_3 +
+				(nic_index >> 1) * NIC_MACRO_QMAN_OFFSET +
+				(nic_index & 0x1) * NIC_ENGINE_QMAN_OFFSET;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	*addr = CFG_BASE + offset;
+
+	return 0;
+}
+
+static u32 gaudi_add_mon_pkts(void *buf, u16 mon_id, u64 fence_addr)
+{
+	u64 monitor_base;
+	u32 size = 0;
+	u16 msg_addr_offset;
+
+	/*
+	 * monitor_base should be the content of the base0 address registers,
+	 * so it will be added to the msg short offsets
+	 */
+	monitor_base = mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0;
+
+	/* First monitor config packet: low address of the sync */
+	msg_addr_offset =
+		(mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 + mon_id * 4) -
+				monitor_base;
+
+	size += gaudi_add_mon_msg_short(buf + size, (u32) fence_addr,
+					msg_addr_offset);
+
+	/* Second monitor config packet: high address of the sync */
+	msg_addr_offset =
+		(mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRH_0 + mon_id * 4) -
+				monitor_base;
+
+	size += gaudi_add_mon_msg_short(buf + size, (u32) (fence_addr >> 32),
+					msg_addr_offset);
+
+	/*
+	 * Third monitor config packet: the payload, i.e. what to write when the
+	 * sync triggers
+	 */
+	msg_addr_offset =
+		(mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_DATA_0 + mon_id * 4) -
+				monitor_base;
+
+	size += gaudi_add_mon_msg_short(buf + size, 1, msg_addr_offset);
+
+	return size;
+}
+
+static u32 gaudi_gen_wait_cb(struct hl_device *hdev,
+				struct hl_gen_wait_properties *prop)
+{
+	struct hl_cb *cb = (struct hl_cb *) prop->data;
+	void *buf = cb->kernel_address;
+	u64 fence_addr = 0;
+	u32 size = prop->size;
+
+	if (gaudi_get_fence_addr(hdev, prop->q_idx, &fence_addr)) {
+		dev_crit(hdev->dev, "wrong queue id %d for wait packet\n",
+				prop->q_idx);
+		return 0;
+	}
+
+	size += gaudi_add_mon_pkts(buf + size, prop->mon_id, fence_addr);
+	size += gaudi_add_arm_monitor_pkt(hdev, buf + size, prop->sob_base,
+			prop->sob_mask, prop->sob_val, prop->mon_id);
+	size += gaudi_add_fence_pkt(buf + size);
+
+	return size;
+}
+
+static void gaudi_reset_sob(struct hl_device *hdev, void *data)
+{
+	struct hl_hw_sob *hw_sob = (struct hl_hw_sob *) data;
+
+	dev_dbg(hdev->dev, "reset SOB, q_idx: %d, sob_id: %d\n", hw_sob->q_idx,
+		hw_sob->sob_id);
+
+	WREG32(mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0 +
+			hw_sob->sob_id * 4, 0);
+
+	kref_init(&hw_sob->kref);
+}
+
+static u64 gaudi_get_device_time(struct hl_device *hdev)
+{
+	u64 device_time = ((u64) RREG32(mmPSOC_TIMESTAMP_CNTCVU)) << 32;
+
+	return device_time | RREG32(mmPSOC_TIMESTAMP_CNTCVL);
+}
+
+static int gaudi_get_hw_block_id(struct hl_device *hdev, u64 block_addr,
+				u32 *block_size, u32 *block_id)
+{
+	return -EPERM;
+}
+
+static int gaudi_block_mmap(struct hl_device *hdev,
+				struct vm_area_struct *vma,
+				u32 block_id, u32 block_size)
+{
+	return -EPERM;
+}
+
+static void gaudi_enable_events_from_fw(struct hl_device *hdev)
+{
+	struct cpu_dyn_regs *dyn_regs =
+			&hdev->fw_loader.dynamic_loader.comm_desc.cpu_dyn_regs;
+	u32 irq_handler_offset = hdev->asic_prop.gic_interrupts_enable ?
+			mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR :
+			le32_to_cpu(dyn_regs->gic_host_ints_irq);
+
+	WREG32(irq_handler_offset,
+		gaudi_irq_map_table[GAUDI_EVENT_INTS_REGISTER].cpu_id);
+}
+
+static int gaudi_ack_mmu_page_fault_or_access_error(struct hl_device *hdev, u64 mmu_cap_mask)
+{
+	return -EINVAL;
+}
+
+static int gaudi_map_pll_idx_to_fw_idx(u32 pll_idx)
+{
+	switch (pll_idx) {
+	case HL_GAUDI_CPU_PLL: return CPU_PLL;
+	case HL_GAUDI_PCI_PLL: return PCI_PLL;
+	case HL_GAUDI_NIC_PLL: return NIC_PLL;
+	case HL_GAUDI_DMA_PLL: return DMA_PLL;
+	case HL_GAUDI_MESH_PLL: return MESH_PLL;
+	case HL_GAUDI_MME_PLL: return MME_PLL;
+	case HL_GAUDI_TPC_PLL: return TPC_PLL;
+	case HL_GAUDI_IF_PLL: return IF_PLL;
+	case HL_GAUDI_SRAM_PLL: return SRAM_PLL;
+	case HL_GAUDI_HBM_PLL: return HBM_PLL;
+	default: return -EINVAL;
+	}
+}
+
+static int gaudi_add_sync_to_engine_map_entry(
+	struct hl_sync_to_engine_map *map, u32 reg_value,
+	enum hl_sync_engine_type engine_type, u32 engine_id)
+{
+	struct hl_sync_to_engine_map_entry *entry;
+
+	/* Reg value represents a partial address of sync object,
+	 * it is used as unique identifier. For this we need to
+	 * clear the cutoff cfg base bits from the value.
+	 */
+	if (reg_value == 0 || reg_value == 0xffffffff)
+		return 0;
+	reg_value -= lower_32_bits(CFG_BASE);
+
+	/* create a new hash entry */
+	entry = kzalloc(sizeof(*entry), GFP_KERNEL);
+	if (!entry)
+		return -ENOMEM;
+	entry->engine_type = engine_type;
+	entry->engine_id = engine_id;
+	entry->sync_id = reg_value;
+	hash_add(map->tb, &entry->node, reg_value);
+
+	return 0;
+}
+
+static int gaudi_gen_sync_to_engine_map(struct hl_device *hdev,
+				struct hl_sync_to_engine_map *map)
+{
+	struct hl_state_dump_specs *sds = &hdev->state_dump_specs;
+	int i, j, rc;
+	u32 reg_value;
+
+	/* Iterate over TPC engines */
+	for (i = 0; i < sds->props[SP_NUM_OF_TPC_ENGINES]; ++i) {
+
+		reg_value = RREG32(sds->props[SP_TPC0_CFG_SO] +
+					sds->props[SP_NEXT_TPC] * i);
+
+		rc = gaudi_add_sync_to_engine_map_entry(map, reg_value,
+							ENGINE_TPC, i);
+		if (rc)
+			goto free_sync_to_engine_map;
+	}
+
+	/* Iterate over MME engines */
+	for (i = 0; i < sds->props[SP_NUM_OF_MME_ENGINES]; ++i) {
+		for (j = 0; j < sds->props[SP_SUB_MME_ENG_NUM]; ++j) {
+
+			reg_value = RREG32(sds->props[SP_MME_CFG_SO] +
+						sds->props[SP_NEXT_MME] * i +
+						j * sizeof(u32));
+
+			rc = gaudi_add_sync_to_engine_map_entry(
+				map, reg_value, ENGINE_MME,
+				i * sds->props[SP_SUB_MME_ENG_NUM] + j);
+			if (rc)
+				goto free_sync_to_engine_map;
+		}
+	}
+
+	/* Iterate over DMA engines */
+	for (i = 0; i < sds->props[SP_NUM_OF_DMA_ENGINES]; ++i) {
+		reg_value = RREG32(sds->props[SP_DMA_CFG_SO] +
+					sds->props[SP_DMA_QUEUES_OFFSET] * i);
+		rc = gaudi_add_sync_to_engine_map_entry(map, reg_value,
+							ENGINE_DMA, i);
+		if (rc)
+			goto free_sync_to_engine_map;
+	}
+
+	return 0;
+
+free_sync_to_engine_map:
+	hl_state_dump_free_sync_to_engine_map(map);
+
+	return rc;
+}
+
+static int gaudi_monitor_valid(struct hl_mon_state_dump *mon)
+{
+	return FIELD_GET(
+		SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0_VALID_MASK,
+		mon->status);
+}
+
+static void gaudi_fill_sobs_from_mon(char *sobs, struct hl_mon_state_dump *mon)
+{
+	const size_t max_write = 10;
+	u32 gid, mask, sob;
+	int i, offset;
+
+	/* Sync object ID is calculated as follows:
+	 * (8 * group_id + cleared bits in mask)
+	 */
+	gid = FIELD_GET(SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SID_MASK,
+			mon->arm_data);
+	mask = FIELD_GET(SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_MASK_MASK,
+			mon->arm_data);
+
+	for (i = 0, offset = 0; mask && offset < MONITOR_SOB_STRING_SIZE -
+		max_write; mask >>= 1, i++) {
+		if (!(mask & 1)) {
+			sob = gid * MONITOR_MAX_SOBS + i;
+
+			if (offset > 0)
+				offset += snprintf(sobs + offset, max_write,
+							", ");
+
+			offset += snprintf(sobs + offset, max_write, "%u", sob);
+		}
+	}
+}
+
+static int gaudi_print_single_monitor(char **buf, size_t *size, size_t *offset,
+				struct hl_device *hdev,
+				struct hl_mon_state_dump *mon)
+{
+	const char *name;
+	char scratch_buf1[BIN_REG_STRING_SIZE],
+		scratch_buf2[BIN_REG_STRING_SIZE];
+	char monitored_sobs[MONITOR_SOB_STRING_SIZE] = {0};
+
+	name = hl_state_dump_get_monitor_name(hdev, mon);
+	if (!name)
+		name = "";
+
+	gaudi_fill_sobs_from_mon(monitored_sobs, mon);
+
+	return hl_snprintf_resize(
+		buf, size, offset,
+		"Mon id: %u%s, wait for group id: %u mask %s to reach val: %u and write %u to address 0x%llx. Pending: %s. Means sync objects [%s] are being monitored.",
+		mon->id, name,
+		FIELD_GET(SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SID_MASK,
+				mon->arm_data),
+		hl_format_as_binary(
+			scratch_buf1, sizeof(scratch_buf1),
+			FIELD_GET(
+				SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_MASK_MASK,
+				mon->arm_data)),
+		FIELD_GET(SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SOD_MASK,
+				mon->arm_data),
+		mon->wr_data,
+		(((u64)mon->wr_addr_high) << 32) | mon->wr_addr_low,
+		hl_format_as_binary(
+			scratch_buf2, sizeof(scratch_buf2),
+			FIELD_GET(
+				SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0_PENDING_MASK,
+				mon->status)),
+		monitored_sobs);
+}
+
+
+static int gaudi_print_fences_single_engine(
+	struct hl_device *hdev, u64 base_offset, u64 status_base_offset,
+	enum hl_sync_engine_type engine_type, u32 engine_id, char **buf,
+	size_t *size, size_t *offset)
+{
+	struct hl_state_dump_specs *sds = &hdev->state_dump_specs;
+	int rc = -ENOMEM, i;
+	u32 *statuses, *fences;
+
+	statuses = kcalloc(sds->props[SP_ENGINE_NUM_OF_QUEUES],
+			sizeof(*statuses), GFP_KERNEL);
+	if (!statuses)
+		goto out;
+
+	fences = kcalloc(sds->props[SP_ENGINE_NUM_OF_FENCES] *
+				sds->props[SP_ENGINE_NUM_OF_QUEUES],
+			 sizeof(*fences), GFP_KERNEL);
+	if (!fences)
+		goto free_status;
+
+	for (i = 0; i < sds->props[SP_ENGINE_NUM_OF_FENCES]; ++i)
+		statuses[i] = RREG32(status_base_offset + i * sizeof(u32));
+
+	for (i = 0; i < sds->props[SP_ENGINE_NUM_OF_FENCES] *
+				sds->props[SP_ENGINE_NUM_OF_QUEUES]; ++i)
+		fences[i] = RREG32(base_offset + i * sizeof(u32));
+
+	/* The actual print */
+	for (i = 0; i < sds->props[SP_ENGINE_NUM_OF_QUEUES]; ++i) {
+		u32 fence_id;
+		u64 fence_cnt, fence_rdata;
+		const char *engine_name;
+
+		if (!FIELD_GET(TPC0_QM_CP_STS_0_FENCE_IN_PROGRESS_MASK,
+			statuses[i]))
+			continue;
+
+		fence_id =
+			FIELD_GET(TPC0_QM_CP_STS_0_FENCE_ID_MASK, statuses[i]);
+		fence_cnt = base_offset + CFG_BASE +
+			sizeof(u32) *
+			(i + fence_id * sds->props[SP_ENGINE_NUM_OF_QUEUES]);
+		fence_rdata = fence_cnt - sds->props[SP_FENCE0_CNT_OFFSET] +
+				sds->props[SP_FENCE0_RDATA_OFFSET];
+		engine_name = hl_sync_engine_to_string(engine_type);
+
+		rc = hl_snprintf_resize(
+			buf, size, offset,
+			"%s%u, stream %u: fence id %u cnt = 0x%llx (%s%u_QM.CP_FENCE%u_CNT_%u) rdata = 0x%llx (%s%u_QM.CP_FENCE%u_RDATA_%u) value = %u, cp_status = %u\n",
+			engine_name, engine_id,
+			i, fence_id,
+			fence_cnt, engine_name, engine_id, fence_id, i,
+			fence_rdata, engine_name, engine_id, fence_id, i,
+			fences[fence_id],
+			statuses[i]);
+		if (rc)
+			goto free_fences;
+	}
+
+	rc = 0;
+
+free_fences:
+	kfree(fences);
+free_status:
+	kfree(statuses);
+out:
+	return rc;
+}
+
+
+static struct hl_state_dump_specs_funcs gaudi_state_dump_funcs = {
+	.monitor_valid = gaudi_monitor_valid,
+	.print_single_monitor = gaudi_print_single_monitor,
+	.gen_sync_to_engine_map = gaudi_gen_sync_to_engine_map,
+	.print_fences_single_engine = gaudi_print_fences_single_engine,
+};
+
+static void gaudi_state_dump_init(struct hl_device *hdev)
+{
+	struct hl_state_dump_specs *sds = &hdev->state_dump_specs;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(gaudi_so_id_to_str); ++i)
+		hash_add(sds->so_id_to_str_tb,
+			&gaudi_so_id_to_str[i].node,
+			gaudi_so_id_to_str[i].id);
+
+	for (i = 0; i < ARRAY_SIZE(gaudi_monitor_id_to_str); ++i)
+		hash_add(sds->monitor_id_to_str_tb,
+			&gaudi_monitor_id_to_str[i].node,
+			gaudi_monitor_id_to_str[i].id);
+
+	sds->props = gaudi_state_dump_specs_props;
+
+	sds->sync_namager_names = gaudi_sync_manager_names;
+
+	sds->funcs = gaudi_state_dump_funcs;
+}
+
+static u32 *gaudi_get_stream_master_qid_arr(void)
+{
+	return gaudi_stream_master;
+}
+
+static int gaudi_set_dram_properties(struct hl_device *hdev)
+{
+	return 0;
+}
+
+static int gaudi_set_binning_masks(struct hl_device *hdev)
+{
+	return 0;
+}
+
+static void gaudi_check_if_razwi_happened(struct hl_device *hdev)
+{
+}
+
+static ssize_t infineon_ver_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+	struct cpucp_info *cpucp_info;
+
+	cpucp_info = &hdev->asic_prop.cpucp_info;
+
+	return sprintf(buf, "%#04x\n", le32_to_cpu(cpucp_info->infineon_version));
+}
+
+static DEVICE_ATTR_RO(infineon_ver);
+
+static struct attribute *gaudi_vrm_dev_attrs[] = {
+	&dev_attr_infineon_ver.attr,
+	NULL,
+};
+
+static void gaudi_add_device_attr(struct hl_device *hdev, struct attribute_group *dev_clk_attr_grp,
+					struct attribute_group *dev_vrm_attr_grp)
+{
+	hl_sysfs_add_dev_clk_attr(hdev, dev_clk_attr_grp);
+	dev_vrm_attr_grp->attrs = gaudi_vrm_dev_attrs;
+}
+
+static int gaudi_send_device_activity(struct hl_device *hdev, bool open)
+{
+	return 0;
+}
+
+static const struct hl_asic_funcs gaudi_funcs = {
+	.early_init = gaudi_early_init,
+	.early_fini = gaudi_early_fini,
+	.late_init = gaudi_late_init,
+	.late_fini = gaudi_late_fini,
+	.sw_init = gaudi_sw_init,
+	.sw_fini = gaudi_sw_fini,
+	.hw_init = gaudi_hw_init,
+	.hw_fini = gaudi_hw_fini,
+	.halt_engines = gaudi_halt_engines,
+	.suspend = gaudi_suspend,
+	.resume = gaudi_resume,
+	.mmap = gaudi_mmap,
+	.ring_doorbell = gaudi_ring_doorbell,
+	.pqe_write = gaudi_pqe_write,
+	.asic_dma_alloc_coherent = gaudi_dma_alloc_coherent,
+	.asic_dma_free_coherent = gaudi_dma_free_coherent,
+	.scrub_device_mem = gaudi_scrub_device_mem,
+	.scrub_device_dram = gaudi_scrub_device_dram,
+	.get_int_queue_base = gaudi_get_int_queue_base,
+	.test_queues = gaudi_test_queues,
+	.asic_dma_pool_zalloc = gaudi_dma_pool_zalloc,
+	.asic_dma_pool_free = gaudi_dma_pool_free,
+	.cpu_accessible_dma_pool_alloc = gaudi_cpu_accessible_dma_pool_alloc,
+	.cpu_accessible_dma_pool_free = gaudi_cpu_accessible_dma_pool_free,
+	.dma_unmap_sgtable = hl_asic_dma_unmap_sgtable,
+	.cs_parser = gaudi_cs_parser,
+	.dma_map_sgtable = hl_asic_dma_map_sgtable,
+	.add_end_of_cb_packets = gaudi_add_end_of_cb_packets,
+	.update_eq_ci = gaudi_update_eq_ci,
+	.context_switch = gaudi_context_switch,
+	.restore_phase_topology = gaudi_restore_phase_topology,
+	.debugfs_read_dma = gaudi_debugfs_read_dma,
+	.add_device_attr = gaudi_add_device_attr,
+	.handle_eqe = gaudi_handle_eqe,
+	.get_events_stat = gaudi_get_events_stat,
+	.read_pte = gaudi_read_pte,
+	.write_pte = gaudi_write_pte,
+	.mmu_invalidate_cache = gaudi_mmu_invalidate_cache,
+	.mmu_invalidate_cache_range = gaudi_mmu_invalidate_cache_range,
+	.mmu_prefetch_cache_range = NULL,
+	.send_heartbeat = gaudi_send_heartbeat,
+	.debug_coresight = gaudi_debug_coresight,
+	.is_device_idle = gaudi_is_device_idle,
+	.compute_reset_late_init = gaudi_compute_reset_late_init,
+	.hw_queues_lock = gaudi_hw_queues_lock,
+	.hw_queues_unlock = gaudi_hw_queues_unlock,
+	.get_pci_id = gaudi_get_pci_id,
+	.get_eeprom_data = gaudi_get_eeprom_data,
+	.get_monitor_dump = gaudi_get_monitor_dump,
+	.send_cpu_message = gaudi_send_cpu_message,
+	.pci_bars_map = gaudi_pci_bars_map,
+	.init_iatu = gaudi_init_iatu,
+	.rreg = hl_rreg,
+	.wreg = hl_wreg,
+	.halt_coresight = gaudi_halt_coresight,
+	.ctx_init = gaudi_ctx_init,
+	.ctx_fini = gaudi_ctx_fini,
+	.pre_schedule_cs = gaudi_pre_schedule_cs,
+	.get_queue_id_for_cq = gaudi_get_queue_id_for_cq,
+	.load_firmware_to_device = gaudi_load_firmware_to_device,
+	.load_boot_fit_to_device = gaudi_load_boot_fit_to_device,
+	.get_signal_cb_size = gaudi_get_signal_cb_size,
+	.get_wait_cb_size = gaudi_get_wait_cb_size,
+	.gen_signal_cb = gaudi_gen_signal_cb,
+	.gen_wait_cb = gaudi_gen_wait_cb,
+	.reset_sob = gaudi_reset_sob,
+	.reset_sob_group = gaudi_reset_sob_group,
+	.get_device_time = gaudi_get_device_time,
+	.pb_print_security_errors = NULL,
+	.collective_wait_init_cs = gaudi_collective_wait_init_cs,
+	.collective_wait_create_jobs = gaudi_collective_wait_create_jobs,
+	.get_dec_base_addr = NULL,
+	.scramble_addr = hl_mmu_scramble_addr,
+	.descramble_addr = hl_mmu_descramble_addr,
+	.ack_protection_bits_errors = gaudi_ack_protection_bits_errors,
+	.get_hw_block_id = gaudi_get_hw_block_id,
+	.hw_block_mmap = gaudi_block_mmap,
+	.enable_events_from_fw = gaudi_enable_events_from_fw,
+	.ack_mmu_errors = gaudi_ack_mmu_page_fault_or_access_error,
+	.map_pll_idx_to_fw_idx = gaudi_map_pll_idx_to_fw_idx,
+	.init_firmware_preload_params = gaudi_init_firmware_preload_params,
+	.init_firmware_loader = gaudi_init_firmware_loader,
+	.init_cpu_scrambler_dram = gaudi_init_scrambler_hbm,
+	.state_dump_init = gaudi_state_dump_init,
+	.get_sob_addr = gaudi_get_sob_addr,
+	.set_pci_memory_regions = gaudi_set_pci_memory_regions,
+	.get_stream_master_qid_arr = gaudi_get_stream_master_qid_arr,
+	.check_if_razwi_happened = gaudi_check_if_razwi_happened,
+	.mmu_get_real_page_size = hl_mmu_get_real_page_size,
+	.access_dev_mem = hl_access_dev_mem,
+	.set_dram_bar_base = gaudi_set_hbm_bar_base,
+	.send_device_activity = gaudi_send_device_activity,
+	.set_dram_properties = gaudi_set_dram_properties,
+	.set_binning_masks = gaudi_set_binning_masks,
+};
+
+/**
+ * gaudi_set_asic_funcs - set GAUDI function pointers
+ *
+ * @hdev: pointer to hl_device structure
+ *
+ */
+void gaudi_set_asic_funcs(struct hl_device *hdev)
+{
+	hdev->asic_funcs = &gaudi_funcs;
+}
diff --git a/drivers/accel/habanalabs/gaudi/gaudiP.h b/drivers/accel/habanalabs/gaudi/gaudiP.h
new file mode 100644
index 000000000000..831be53bb9d7
--- /dev/null
+++ b/drivers/accel/habanalabs/gaudi/gaudiP.h
@@ -0,0 +1,343 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2019-2022 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+#ifndef GAUDIP_H_
+#define GAUDIP_H_
+
+#include <uapi/drm/habanalabs_accel.h>
+#include "../common/habanalabs.h"
+#include <linux/habanalabs/hl_boot_if.h>
+#include "../include/gaudi/gaudi_packets.h"
+#include "../include/gaudi/gaudi.h"
+#include "../include/gaudi/gaudi_async_events.h"
+#include "../include/gaudi/gaudi_fw_if.h"
+
+#define NUMBER_OF_EXT_HW_QUEUES		8
+#define NUMBER_OF_CMPLT_QUEUES		NUMBER_OF_EXT_HW_QUEUES
+#define NUMBER_OF_CPU_HW_QUEUES		1
+#define NUMBER_OF_INT_HW_QUEUES		100
+#define NUMBER_OF_HW_QUEUES		(NUMBER_OF_EXT_HW_QUEUES + \
+					NUMBER_OF_CPU_HW_QUEUES + \
+					NUMBER_OF_INT_HW_QUEUES)
+
+/* 10 NIC QMANs, DMA5 QMAN, TPC7 QMAN */
+#define NUMBER_OF_COLLECTIVE_QUEUES	12
+#define NUMBER_OF_SOBS_IN_GRP		11
+
+#define GAUDI_STREAM_MASTER_ARR_SIZE	8
+
+#define CORESIGHT_TIMEOUT_USEC		100000		/* 100 ms */
+
+#define GAUDI_MAX_CLK_FREQ		2200000000ull	/* 2200 MHz */
+
+#define MAX_POWER_DEFAULT_PCI		200000		/* 200W */
+#define MAX_POWER_DEFAULT_PMC		350000		/* 350W */
+
+#define DC_POWER_DEFAULT_PCI		60000		/* 60W */
+#define DC_POWER_DEFAULT_PMC		60000		/* 60W */
+
+#define DC_POWER_DEFAULT_PMC_SEC	97000		/* 97W */
+
+#define GAUDI_CPU_TIMEOUT_USEC		30000000	/* 30s */
+
+#define TPC_ENABLED_MASK		0xFF
+
+#define GAUDI_HBM_SIZE_32GB		0x800000000ull
+#define GAUDI_HBM_DEVICES		4
+#define GAUDI_HBM_CHANNELS		8
+#define GAUDI_HBM_CFG_BASE		(mmHBM0_BASE - CFG_BASE)
+#define GAUDI_HBM_CFG_OFFSET		(mmHBM1_BASE - mmHBM0_BASE)
+
+#define DMA_MAX_TRANSFER_SIZE		U32_MAX
+
+#define GAUDI_DEFAULT_CARD_NAME		"HL205"
+
+#define GAUDI_MAX_PENDING_CS		SZ_16K
+
+#if !IS_MAX_PENDING_CS_VALID(GAUDI_MAX_PENDING_CS)
+#error "GAUDI_MAX_PENDING_CS must be power of 2 and greater than 1"
+#endif
+
+#define PCI_DMA_NUMBER_OF_CHNLS		2
+#define HBM_DMA_NUMBER_OF_CHNLS		6
+#define DMA_NUMBER_OF_CHNLS		(PCI_DMA_NUMBER_OF_CHNLS + \
+						HBM_DMA_NUMBER_OF_CHNLS)
+
+#define MME_NUMBER_OF_SLAVE_ENGINES	2
+#define MME_NUMBER_OF_ENGINES		(MME_NUMBER_OF_MASTER_ENGINES + \
+					MME_NUMBER_OF_SLAVE_ENGINES)
+#define MME_NUMBER_OF_QMANS		(MME_NUMBER_OF_MASTER_ENGINES * \
+					QMAN_STREAMS)
+
+#define QMAN_STREAMS		4
+#define PQ_FETCHER_CACHE_SIZE	8
+
+#define DMA_QMAN_OFFSET		(mmDMA1_QM_BASE - mmDMA0_QM_BASE)
+#define TPC_QMAN_OFFSET		(mmTPC1_QM_BASE - mmTPC0_QM_BASE)
+#define MME_QMAN_OFFSET		(mmMME1_QM_BASE - mmMME0_QM_BASE)
+#define NIC_MACRO_QMAN_OFFSET	(mmNIC1_QM0_BASE - mmNIC0_QM0_BASE)
+#define NIC_ENGINE_QMAN_OFFSET	(mmNIC0_QM1_BASE - mmNIC0_QM0_BASE)
+
+#define TPC_CFG_OFFSET		(mmTPC1_CFG_BASE - mmTPC0_CFG_BASE)
+
+#define DMA_CORE_OFFSET		(mmDMA1_CORE_BASE - mmDMA0_CORE_BASE)
+
+#define QMAN_LDMA_SRC_OFFSET	(mmDMA0_CORE_SRC_BASE_LO - mmDMA0_CORE_CFG_0)
+#define QMAN_LDMA_DST_OFFSET	(mmDMA0_CORE_DST_BASE_LO - mmDMA0_CORE_CFG_0)
+#define QMAN_LDMA_SIZE_OFFSET	(mmDMA0_CORE_DST_TSIZE_0 - mmDMA0_CORE_CFG_0)
+
+#define QMAN_CPDMA_SRC_OFFSET	(mmDMA0_QM_CQ_PTR_LO_4 - mmDMA0_CORE_CFG_0)
+#define QMAN_CPDMA_DST_OFFSET	(mmDMA0_CORE_DST_BASE_LO - mmDMA0_CORE_CFG_0)
+#define QMAN_CPDMA_SIZE_OFFSET	(mmDMA0_QM_CQ_TSIZE_4 - mmDMA0_CORE_CFG_0)
+
+#define SIF_RTR_CTRL_OFFSET	(mmSIF_RTR_CTRL_1_BASE - mmSIF_RTR_CTRL_0_BASE)
+
+#define NIF_RTR_CTRL_OFFSET	(mmNIF_RTR_CTRL_1_BASE - mmNIF_RTR_CTRL_0_BASE)
+
+#define MME_ACC_OFFSET		(mmMME1_ACC_BASE - mmMME0_ACC_BASE)
+#define SRAM_BANK_OFFSET	(mmSRAM_Y0_X1_RTR_BASE - mmSRAM_Y0_X0_RTR_BASE)
+
+#define NUM_OF_SOB_IN_BLOCK		\
+	(((mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_2047 - \
+	mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0) + 4) >> 2)
+
+#define NUM_OF_MONITORS_IN_BLOCK	\
+	(((mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_511 - \
+	mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_0) + 4) >> 2)
+
+#define MONITOR_MAX_SOBS	8
+
+/* DRAM Memory Map */
+
+#define CPU_FW_IMAGE_SIZE	0x10000000	/* 256MB */
+#define MMU_PAGE_TABLES_SIZE	0x0BF00000	/* 191MB */
+#define MMU_CACHE_MNG_SIZE	0x00100000	/* 1MB */
+#define RESERVED		0x04000000	/* 64MB */
+
+#define CPU_FW_IMAGE_ADDR	DRAM_PHYS_BASE
+#define MMU_PAGE_TABLES_ADDR	(CPU_FW_IMAGE_ADDR + CPU_FW_IMAGE_SIZE)
+#define MMU_CACHE_MNG_ADDR	(MMU_PAGE_TABLES_ADDR + MMU_PAGE_TABLES_SIZE)
+
+#define DRAM_DRIVER_END_ADDR	(MMU_CACHE_MNG_ADDR + MMU_CACHE_MNG_SIZE +\
+								RESERVED)
+
+#define DRAM_BASE_ADDR_USER	0x20000000
+
+#if (DRAM_DRIVER_END_ADDR > DRAM_BASE_ADDR_USER)
+#error "Driver must reserve no more than 512MB"
+#endif
+
+/* Internal QMANs PQ sizes */
+
+#define MME_QMAN_LENGTH			1024
+#define MME_QMAN_SIZE_IN_BYTES		(MME_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE)
+
+#define HBM_DMA_QMAN_LENGTH		4096
+#define HBM_DMA_QMAN_SIZE_IN_BYTES	\
+				(HBM_DMA_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE)
+
+#define TPC_QMAN_LENGTH			1024
+#define TPC_QMAN_SIZE_IN_BYTES		(TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE)
+
+#define NIC_QMAN_LENGTH			4096
+#define NIC_QMAN_SIZE_IN_BYTES		(NIC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE)
+
+
+#define SRAM_USER_BASE_OFFSET  GAUDI_DRIVER_SRAM_RESERVED_SIZE_FROM_START
+
+/* Virtual address space */
+#define VA_HOST_SPACE_START	0x1000000000000ull	/* 256TB */
+#define VA_HOST_SPACE_END	0x3FF8000000000ull	/* 1PB - 512GB */
+#define VA_HOST_SPACE_SIZE	(VA_HOST_SPACE_END - \
+					VA_HOST_SPACE_START) /* 767TB */
+#define HOST_SPACE_INTERNAL_CB_SZ	SZ_2M
+
+#define HW_CAP_PLL		BIT(0)
+#define HW_CAP_HBM		BIT(1)
+#define HW_CAP_MMU		BIT(2)
+#define HW_CAP_MME		BIT(3)
+#define HW_CAP_CPU		BIT(4)
+#define HW_CAP_PCI_DMA		BIT(5)
+#define HW_CAP_MSI		BIT(6)
+#define HW_CAP_CPU_Q		BIT(7)
+#define HW_CAP_HBM_DMA		BIT(8)
+#define HW_CAP_SRAM_SCRAMBLER	BIT(10)
+#define HW_CAP_HBM_SCRAMBLER	BIT(11)
+
+#define HW_CAP_NIC0		BIT(14)
+#define HW_CAP_NIC1		BIT(15)
+#define HW_CAP_NIC2		BIT(16)
+#define HW_CAP_NIC3		BIT(17)
+#define HW_CAP_NIC4		BIT(18)
+#define HW_CAP_NIC5		BIT(19)
+#define HW_CAP_NIC6		BIT(20)
+#define HW_CAP_NIC7		BIT(21)
+#define HW_CAP_NIC8		BIT(22)
+#define HW_CAP_NIC9		BIT(23)
+#define HW_CAP_NIC_MASK		GENMASK(23, 14)
+#define HW_CAP_NIC_SHIFT	14
+
+#define HW_CAP_TPC0		BIT(24)
+#define HW_CAP_TPC1		BIT(25)
+#define HW_CAP_TPC2		BIT(26)
+#define HW_CAP_TPC3		BIT(27)
+#define HW_CAP_TPC4		BIT(28)
+#define HW_CAP_TPC5		BIT(29)
+#define HW_CAP_TPC6		BIT(30)
+#define HW_CAP_TPC7		BIT(31)
+#define HW_CAP_TPC_MASK		GENMASK(31, 24)
+#define HW_CAP_TPC_SHIFT	24
+
+#define NEXT_SYNC_OBJ_ADDR_INTERVAL \
+	(mmSYNC_MNGR_W_N_SYNC_MNGR_OBJS_SOB_OBJ_0 - \
+	 mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0)
+#define NUM_OF_MME_ENGINES			2
+#define NUM_OF_MME_SUB_ENGINES		2
+#define NUM_OF_TPC_ENGINES			8
+#define NUM_OF_DMA_ENGINES			8
+#define NUM_OF_QUEUES				5
+#define NUM_OF_STREAMS				4
+#define NUM_OF_FENCES				4
+
+
+#define GAUDI_CPU_PCI_MSB_ADDR(addr)	(((addr) & GENMASK_ULL(49, 39)) >> 39)
+#define GAUDI_PCI_TO_CPU_ADDR(addr)			\
+	do {						\
+		(addr) &= ~GENMASK_ULL(49, 39);		\
+		(addr) |= BIT_ULL(39);			\
+	} while (0)
+#define GAUDI_CPU_TO_PCI_ADDR(addr, extension)		\
+	do {						\
+		(addr) &= ~GENMASK_ULL(49, 39);		\
+		(addr) |= (u64) (extension) << 39;	\
+	} while (0)
+
+enum gaudi_dma_channels {
+	GAUDI_PCI_DMA_1,
+	GAUDI_PCI_DMA_2,
+	GAUDI_HBM_DMA_1,
+	GAUDI_HBM_DMA_2,
+	GAUDI_HBM_DMA_3,
+	GAUDI_HBM_DMA_4,
+	GAUDI_HBM_DMA_5,
+	GAUDI_HBM_DMA_6,
+	GAUDI_DMA_MAX
+};
+
+enum gaudi_tpc_mask {
+	GAUDI_TPC_MASK_TPC0 = 0x01,
+	GAUDI_TPC_MASK_TPC1 = 0x02,
+	GAUDI_TPC_MASK_TPC2 = 0x04,
+	GAUDI_TPC_MASK_TPC3 = 0x08,
+	GAUDI_TPC_MASK_TPC4 = 0x10,
+	GAUDI_TPC_MASK_TPC5 = 0x20,
+	GAUDI_TPC_MASK_TPC6 = 0x40,
+	GAUDI_TPC_MASK_TPC7 = 0x80,
+	GAUDI_TPC_MASK_ALL = 0xFF
+};
+
+enum gaudi_nic_mask {
+	GAUDI_NIC_MASK_NIC0 = 0x01,
+	GAUDI_NIC_MASK_NIC1 = 0x02,
+	GAUDI_NIC_MASK_NIC2 = 0x04,
+	GAUDI_NIC_MASK_NIC3 = 0x08,
+	GAUDI_NIC_MASK_NIC4 = 0x10,
+	GAUDI_NIC_MASK_NIC5 = 0x20,
+	GAUDI_NIC_MASK_NIC6 = 0x40,
+	GAUDI_NIC_MASK_NIC7 = 0x80,
+	GAUDI_NIC_MASK_NIC8 = 0x100,
+	GAUDI_NIC_MASK_NIC9 = 0x200,
+	GAUDI_NIC_MASK_ALL = 0x3FF
+};
+
+/*
+ * struct gaudi_hw_sob_group - H/W SOB group info.
+ * @hdev: habanalabs device structure.
+ * @kref: refcount of this SOB group. group will reset once refcount is zero.
+ * @base_sob_id: base sob id of this SOB group.
+ * @queue_id: id of the queue that waits on this sob group
+ */
+struct gaudi_hw_sob_group {
+	struct hl_device	*hdev;
+	struct kref		kref;
+	u32			base_sob_id;
+	u32			queue_id;
+};
+
+#define NUM_SOB_GROUPS (HL_RSVD_SOBS * QMAN_STREAMS)
+/**
+ * struct gaudi_collective_properties -
+ *     holds all SOB groups and queues info reserved for the collective
+ * @hw_sob_group: H/W SOB groups.
+ * @next_sob_group_val: the next value to use for the currently used SOB group.
+ * @curr_sob_group_idx: the index of the currently used SOB group.
+ * @mstr_sob_mask: pre-defined masks for collective master monitors
+ */
+struct gaudi_collective_properties {
+	struct gaudi_hw_sob_group hw_sob_group[NUM_SOB_GROUPS];
+	u16			next_sob_group_val[QMAN_STREAMS];
+	u8			curr_sob_group_idx[QMAN_STREAMS];
+	u8			mstr_sob_mask[HL_COLLECTIVE_RSVD_MSTR_MONS];
+};
+
+/**
+ * struct gaudi_internal_qman_info - Internal QMAN information.
+ * @pq_kernel_addr: Kernel address of the PQ memory area in the host.
+ * @pq_dma_addr: DMA address of the PQ memory area in the host.
+ * @pq_size: Size of allocated host memory for PQ.
+ */
+struct gaudi_internal_qman_info {
+	void		*pq_kernel_addr;
+	dma_addr_t	pq_dma_addr;
+	size_t		pq_size;
+};
+
+/**
+ * struct gaudi_device - ASIC specific manage structure.
+ * @cpucp_info_get: get information on device from CPU-CP
+ * @hw_queues_lock: protects the H/W queues from concurrent access.
+ * @internal_qmans: Internal QMANs information. The array size is larger than
+ *                  the actual number of internal queues because they are not in
+ *                  consecutive order.
+ * @hbm_bar_cur_addr: current address of HBM PCI bar.
+ * @events: array that holds all event id's
+ * @events_stat: array that holds histogram of all received events.
+ * @events_stat_aggregate: same as events_stat but doesn't get cleared on reset
+ * @hw_cap_initialized: This field contains a bit per H/W engine. When that
+ *                      engine is initialized, that bit is set by the driver to
+ *                      signal we can use this engine in later code paths.
+ *                      Each bit is cleared upon reset of its corresponding H/W
+ *                      engine.
+ * @mmu_cache_inv_pi: PI for MMU cache invalidation flow. The H/W expects an
+ *                    8-bit value so use u8.
+ */
+struct gaudi_device {
+	int (*cpucp_info_get)(struct hl_device *hdev);
+
+	/* TODO: remove hw_queues_lock after moving to scheduler code */
+	spinlock_t			hw_queues_lock;
+
+	struct gaudi_internal_qman_info	internal_qmans[GAUDI_QUEUE_ID_SIZE];
+
+	struct gaudi_collective_properties collective_props;
+
+	u64				hbm_bar_cur_addr;
+
+	u32				events[GAUDI_EVENT_SIZE];
+	u32				events_stat[GAUDI_EVENT_SIZE];
+	u32				events_stat_aggregate[GAUDI_EVENT_SIZE];
+	u32				hw_cap_initialized;
+	u8				mmu_cache_inv_pi;
+};
+
+void gaudi_init_security(struct hl_device *hdev);
+void gaudi_ack_protection_bits_errors(struct hl_device *hdev);
+int gaudi_debug_coresight(struct hl_device *hdev, struct hl_ctx *ctx, void *data);
+void gaudi_halt_coresight(struct hl_device *hdev, struct hl_ctx *ctx);
+void gaudi_mmu_prepare_reg(struct hl_device *hdev, u64 reg, u32 asid);
+
+#endif /* GAUDIP_H_ */
diff --git a/drivers/accel/habanalabs/gaudi/gaudi_coresight.c b/drivers/accel/habanalabs/gaudi/gaudi_coresight.c
new file mode 100644
index 000000000000..1168fefa33f4
--- /dev/null
+++ b/drivers/accel/habanalabs/gaudi/gaudi_coresight.c
@@ -0,0 +1,918 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ */
+
+#include "gaudiP.h"
+#include "../include/gaudi/gaudi_coresight.h"
+#include "../include/gaudi/asic_reg/gaudi_regs.h"
+#include "../include/gaudi/gaudi_masks.h"
+#include "../include/gaudi/gaudi_reg_map.h"
+
+#include <uapi/drm/habanalabs_accel.h>
+
+#define SPMU_SECTION_SIZE		MME0_ACC_SPMU_MAX_OFFSET
+#define SPMU_EVENT_TYPES_OFFSET		0x400
+#define SPMU_MAX_COUNTERS		6
+
+static u64 debug_stm_regs[GAUDI_STM_LAST + 1] = {
+	[GAUDI_STM_MME0_ACC]	= mmMME0_ACC_STM_BASE,
+	[GAUDI_STM_MME0_SBAB]	= mmMME0_SBAB_STM_BASE,
+	[GAUDI_STM_MME0_CTRL]	= mmMME0_CTRL_STM_BASE,
+	[GAUDI_STM_MME1_ACC]	= mmMME1_ACC_STM_BASE,
+	[GAUDI_STM_MME1_SBAB]	= mmMME1_SBAB_STM_BASE,
+	[GAUDI_STM_MME1_CTRL]	= mmMME1_CTRL_STM_BASE,
+	[GAUDI_STM_MME2_ACC]	= mmMME2_ACC_STM_BASE,
+	[GAUDI_STM_MME2_SBAB]	= mmMME2_SBAB_STM_BASE,
+	[GAUDI_STM_MME2_CTRL]	= mmMME2_CTRL_STM_BASE,
+	[GAUDI_STM_MME3_ACC]	= mmMME3_ACC_STM_BASE,
+	[GAUDI_STM_MME3_SBAB]	= mmMME3_SBAB_STM_BASE,
+	[GAUDI_STM_MME3_CTRL]	= mmMME3_CTRL_STM_BASE,
+	[GAUDI_STM_DMA_IF_W_S]	= mmDMA_IF_W_S_STM_BASE,
+	[GAUDI_STM_DMA_IF_E_S]	= mmDMA_IF_E_S_STM_BASE,
+	[GAUDI_STM_DMA_IF_W_N]	= mmDMA_IF_W_N_STM_BASE,
+	[GAUDI_STM_DMA_IF_E_N]	= mmDMA_IF_E_N_STM_BASE,
+	[GAUDI_STM_CPU]		= mmCPU_STM_BASE,
+	[GAUDI_STM_DMA_CH_0_CS]	= mmDMA_CH_0_CS_STM_BASE,
+	[GAUDI_STM_DMA_CH_1_CS]	= mmDMA_CH_1_CS_STM_BASE,
+	[GAUDI_STM_DMA_CH_2_CS]	= mmDMA_CH_2_CS_STM_BASE,
+	[GAUDI_STM_DMA_CH_3_CS]	= mmDMA_CH_3_CS_STM_BASE,
+	[GAUDI_STM_DMA_CH_4_CS]	= mmDMA_CH_4_CS_STM_BASE,
+	[GAUDI_STM_DMA_CH_5_CS]	= mmDMA_CH_5_CS_STM_BASE,
+	[GAUDI_STM_DMA_CH_6_CS]	= mmDMA_CH_6_CS_STM_BASE,
+	[GAUDI_STM_DMA_CH_7_CS]	= mmDMA_CH_7_CS_STM_BASE,
+	[GAUDI_STM_PCIE]	= mmPCIE_STM_BASE,
+	[GAUDI_STM_MMU_CS]	= mmMMU_CS_STM_BASE,
+	[GAUDI_STM_PSOC]	= mmPSOC_STM_BASE,
+	[GAUDI_STM_NIC0_0]	= mmSTM_0_NIC0_DBG_BASE,
+	[GAUDI_STM_NIC0_1]	= mmSTM_1_NIC0_DBG_BASE,
+	[GAUDI_STM_NIC1_0]	= mmSTM_0_NIC1_DBG_BASE,
+	[GAUDI_STM_NIC1_1]	= mmSTM_1_NIC1_DBG_BASE,
+	[GAUDI_STM_NIC2_0]	= mmSTM_0_NIC2_DBG_BASE,
+	[GAUDI_STM_NIC2_1]	= mmSTM_1_NIC2_DBG_BASE,
+	[GAUDI_STM_NIC3_0]	= mmSTM_0_NIC3_DBG_BASE,
+	[GAUDI_STM_NIC3_1]	= mmSTM_1_NIC3_DBG_BASE,
+	[GAUDI_STM_NIC4_0]	= mmSTM_0_NIC4_DBG_BASE,
+	[GAUDI_STM_NIC4_1]	= mmSTM_1_NIC4_DBG_BASE,
+	[GAUDI_STM_TPC0_EML]	= mmTPC0_EML_STM_BASE,
+	[GAUDI_STM_TPC1_EML]	= mmTPC1_EML_STM_BASE,
+	[GAUDI_STM_TPC2_EML]	= mmTPC2_EML_STM_BASE,
+	[GAUDI_STM_TPC3_EML]	= mmTPC3_EML_STM_BASE,
+	[GAUDI_STM_TPC4_EML]	= mmTPC4_EML_STM_BASE,
+	[GAUDI_STM_TPC5_EML]	= mmTPC5_EML_STM_BASE,
+	[GAUDI_STM_TPC6_EML]	= mmTPC6_EML_STM_BASE,
+	[GAUDI_STM_TPC7_EML]	= mmTPC7_EML_STM_BASE
+};
+
+static u64 debug_etf_regs[GAUDI_ETF_LAST + 1] = {
+	[GAUDI_ETF_MME0_ACC]		= mmMME0_ACC_ETF_BASE,
+	[GAUDI_ETF_MME0_SBAB]		= mmMME0_SBAB_ETF_BASE,
+	[GAUDI_ETF_MME0_CTRL]		= mmMME0_CTRL_ETF_BASE,
+	[GAUDI_ETF_MME1_ACC]		= mmMME1_ACC_ETF_BASE,
+	[GAUDI_ETF_MME1_SBAB]		= mmMME1_SBAB_ETF_BASE,
+	[GAUDI_ETF_MME1_CTRL]		= mmMME1_CTRL_ETF_BASE,
+	[GAUDI_ETF_MME2_ACC]		= mmMME2_MME2_ACC_ETF_BASE,
+	[GAUDI_ETF_MME2_SBAB]		= mmMME2_SBAB_ETF_BASE,
+	[GAUDI_ETF_MME2_CTRL]		= mmMME2_CTRL_ETF_BASE,
+	[GAUDI_ETF_MME3_ACC]		= mmMME3_ACC_ETF_BASE,
+	[GAUDI_ETF_MME3_SBAB]		= mmMME3_SBAB_ETF_BASE,
+	[GAUDI_ETF_MME3_CTRL]		= mmMME3_CTRL_ETF_BASE,
+	[GAUDI_ETF_DMA_IF_W_S]		= mmDMA_IF_W_S_ETF_BASE,
+	[GAUDI_ETF_DMA_IF_E_S]		= mmDMA_IF_E_S_ETF_BASE,
+	[GAUDI_ETF_DMA_IF_W_N]		= mmDMA_IF_W_N_ETF_BASE,
+	[GAUDI_ETF_DMA_IF_E_N]		= mmDMA_IF_E_N_ETF_BASE,
+	[GAUDI_ETF_CPU_0]		= mmCPU_ETF_0_BASE,
+	[GAUDI_ETF_CPU_1]		= mmCPU_ETF_1_BASE,
+	[GAUDI_ETF_CPU_TRACE]		= mmCPU_ETF_TRACE_BASE,
+	[GAUDI_ETF_DMA_CH_0_CS]		= mmDMA_CH_0_CS_ETF_BASE,
+	[GAUDI_ETF_DMA_CH_1_CS]		= mmDMA_CH_1_CS_ETF_BASE,
+	[GAUDI_ETF_DMA_CH_2_CS]		= mmDMA_CH_2_CS_ETF_BASE,
+	[GAUDI_ETF_DMA_CH_3_CS]		= mmDMA_CH_3_CS_ETF_BASE,
+	[GAUDI_ETF_DMA_CH_4_CS]		= mmDMA_CH_4_CS_ETF_BASE,
+	[GAUDI_ETF_DMA_CH_5_CS]		= mmDMA_CH_5_CS_ETF_BASE,
+	[GAUDI_ETF_DMA_CH_6_CS]		= mmDMA_CH_6_CS_ETF_BASE,
+	[GAUDI_ETF_DMA_CH_7_CS]		= mmDMA_CH_7_CS_ETF_BASE,
+	[GAUDI_ETF_PCIE]		= mmPCIE_ETF_BASE,
+	[GAUDI_ETF_MMU_CS]		= mmMMU_CS_ETF_BASE,
+	[GAUDI_ETF_PSOC]		= mmPSOC_ETF_BASE,
+	[GAUDI_ETF_NIC0_0]		= mmETF_0_NIC0_DBG_BASE,
+	[GAUDI_ETF_NIC0_1]		= mmETF_1_NIC0_DBG_BASE,
+	[GAUDI_ETF_NIC1_0]		= mmETF_0_NIC1_DBG_BASE,
+	[GAUDI_ETF_NIC1_1]		= mmETF_1_NIC1_DBG_BASE,
+	[GAUDI_ETF_NIC2_0]		= mmETF_0_NIC2_DBG_BASE,
+	[GAUDI_ETF_NIC2_1]		= mmETF_1_NIC2_DBG_BASE,
+	[GAUDI_ETF_NIC3_0]		= mmETF_0_NIC3_DBG_BASE,
+	[GAUDI_ETF_NIC3_1]		= mmETF_1_NIC3_DBG_BASE,
+	[GAUDI_ETF_NIC4_0]		= mmETF_0_NIC4_DBG_BASE,
+	[GAUDI_ETF_NIC4_1]		= mmETF_1_NIC4_DBG_BASE,
+	[GAUDI_ETF_TPC0_EML]		= mmTPC0_EML_ETF_BASE,
+	[GAUDI_ETF_TPC1_EML]		= mmTPC1_EML_ETF_BASE,
+	[GAUDI_ETF_TPC2_EML]		= mmTPC2_EML_ETF_BASE,
+	[GAUDI_ETF_TPC3_EML]		= mmTPC3_EML_ETF_BASE,
+	[GAUDI_ETF_TPC4_EML]		= mmTPC4_EML_ETF_BASE,
+	[GAUDI_ETF_TPC5_EML]		= mmTPC5_EML_ETF_BASE,
+	[GAUDI_ETF_TPC6_EML]		= mmTPC6_EML_ETF_BASE,
+	[GAUDI_ETF_TPC7_EML]		= mmTPC7_EML_ETF_BASE
+};
+
+static u64 debug_funnel_regs[GAUDI_FUNNEL_LAST + 1] = {
+	[GAUDI_FUNNEL_MME0_ACC]		= mmMME0_ACC_FUNNEL_BASE,
+	[GAUDI_FUNNEL_MME1_ACC]		= mmMME1_ACC_FUNNEL_BASE,
+	[GAUDI_FUNNEL_MME2_ACC]		= mmMME2_ACC_FUNNEL_BASE,
+	[GAUDI_FUNNEL_MME3_ACC]		= mmMME3_ACC_FUNNEL_BASE,
+	[GAUDI_FUNNEL_SRAM_Y0_X0]	= mmSRAM_Y0_X0_FUNNEL_BASE,
+	[GAUDI_FUNNEL_SRAM_Y0_X1]	= mmSRAM_Y0_X1_FUNNEL_BASE,
+	[GAUDI_FUNNEL_SRAM_Y0_X2]	= mmSRAM_Y0_X2_FUNNEL_BASE,
+	[GAUDI_FUNNEL_SRAM_Y0_X3]	= mmSRAM_Y0_X3_FUNNEL_BASE,
+	[GAUDI_FUNNEL_SRAM_Y0_X4]	= mmSRAM_Y0_X4_FUNNEL_BASE,
+	[GAUDI_FUNNEL_SRAM_Y0_X5]	= mmSRAM_Y0_X5_FUNNEL_BASE,
+	[GAUDI_FUNNEL_SRAM_Y0_X6]	= mmSRAM_Y0_X6_FUNNEL_BASE,
+	[GAUDI_FUNNEL_SRAM_Y0_X7]	= mmSRAM_Y0_X7_FUNNEL_BASE,
+	[GAUDI_FUNNEL_SRAM_Y1_X0]	= mmSRAM_Y1_X0_FUNNEL_BASE,
+	[GAUDI_FUNNEL_SRAM_Y1_X1]	= mmSRAM_Y1_X1_FUNNEL_BASE,
+	[GAUDI_FUNNEL_SRAM_Y1_X2]	= mmSRAM_Y1_X2_FUNNEL_BASE,
+	[GAUDI_FUNNEL_SRAM_Y1_X3]	= mmSRAM_Y1_X3_FUNNEL_BASE,
+	[GAUDI_FUNNEL_SRAM_Y1_X4]	= mmSRAM_Y1_X4_FUNNEL_BASE,
+	[GAUDI_FUNNEL_SRAM_Y1_X5]	= mmSRAM_Y1_X5_FUNNEL_BASE,
+	[GAUDI_FUNNEL_SRAM_Y1_X6]	= mmSRAM_Y1_X6_FUNNEL_BASE,
+	[GAUDI_FUNNEL_SRAM_Y1_X7]	= mmSRAM_Y1_X7_FUNNEL_BASE,
+	[GAUDI_FUNNEL_SRAM_Y2_X0]	= mmSRAM_Y2_X0_FUNNEL_BASE,
+	[GAUDI_FUNNEL_SRAM_Y2_X1]	= mmSRAM_Y2_X1_FUNNEL_BASE,
+	[GAUDI_FUNNEL_SRAM_Y2_X2]	= mmSRAM_Y2_X2_FUNNEL_BASE,
+	[GAUDI_FUNNEL_SRAM_Y2_X3]	= mmSRAM_Y2_X3_FUNNEL_BASE,
+	[GAUDI_FUNNEL_SRAM_Y2_X4]	= mmSRAM_Y2_X4_FUNNEL_BASE,
+	[GAUDI_FUNNEL_SRAM_Y2_X5]	= mmSRAM_Y2_X5_FUNNEL_BASE,
+	[GAUDI_FUNNEL_SRAM_Y2_X6]	= mmSRAM_Y2_X6_FUNNEL_BASE,
+	[GAUDI_FUNNEL_SRAM_Y2_X7]	= mmSRAM_Y2_X7_FUNNEL_BASE,
+	[GAUDI_FUNNEL_SRAM_Y3_X0]	= mmSRAM_Y3_X0_FUNNEL_BASE,
+	[GAUDI_FUNNEL_SRAM_Y3_X1]	= mmSRAM_Y3_X1_FUNNEL_BASE,
+	[GAUDI_FUNNEL_SRAM_Y3_X2]	= mmSRAM_Y3_X2_FUNNEL_BASE,
+	[GAUDI_FUNNEL_SRAM_Y3_X4]	= mmSRAM_Y3_X4_FUNNEL_BASE,
+	[GAUDI_FUNNEL_SRAM_Y3_X3]	= mmSRAM_Y3_X3_FUNNEL_BASE,
+	[GAUDI_FUNNEL_SRAM_Y3_X5]	= mmSRAM_Y3_X5_FUNNEL_BASE,
+	[GAUDI_FUNNEL_SRAM_Y3_X6]	= mmSRAM_Y3_X6_FUNNEL_BASE,
+	[GAUDI_FUNNEL_SRAM_Y3_X7]	= mmSRAM_Y3_X7_FUNNEL_BASE,
+	[GAUDI_FUNNEL_SIF_0]		= mmSIF_FUNNEL_0_BASE,
+	[GAUDI_FUNNEL_SIF_1]		= mmSIF_FUNNEL_1_BASE,
+	[GAUDI_FUNNEL_SIF_2]		= mmSIF_FUNNEL_2_BASE,
+	[GAUDI_FUNNEL_SIF_3]		= mmSIF_FUNNEL_3_BASE,
+	[GAUDI_FUNNEL_SIF_4]		= mmSIF_FUNNEL_4_BASE,
+	[GAUDI_FUNNEL_SIF_5]		= mmSIF_FUNNEL_5_BASE,
+	[GAUDI_FUNNEL_SIF_6]		= mmSIF_FUNNEL_6_BASE,
+	[GAUDI_FUNNEL_SIF_7]		= mmSIF_FUNNEL_7_BASE,
+	[GAUDI_FUNNEL_NIF_0]		= mmNIF_FUNNEL_0_BASE,
+	[GAUDI_FUNNEL_NIF_1]		= mmNIF_FUNNEL_1_BASE,
+	[GAUDI_FUNNEL_NIF_2]		= mmNIF_FUNNEL_2_BASE,
+	[GAUDI_FUNNEL_NIF_3]		= mmNIF_FUNNEL_3_BASE,
+	[GAUDI_FUNNEL_NIF_4]		= mmNIF_FUNNEL_4_BASE,
+	[GAUDI_FUNNEL_NIF_5]		= mmNIF_FUNNEL_5_BASE,
+	[GAUDI_FUNNEL_NIF_6]		= mmNIF_FUNNEL_6_BASE,
+	[GAUDI_FUNNEL_NIF_7]		= mmNIF_FUNNEL_7_BASE,
+	[GAUDI_FUNNEL_DMA_IF_W_S]	= mmDMA_IF_W_S_FUNNEL_BASE,
+	[GAUDI_FUNNEL_DMA_IF_E_S]	= mmDMA_IF_E_S_FUNNEL_BASE,
+	[GAUDI_FUNNEL_DMA_IF_W_N]	= mmDMA_IF_W_N_FUNNEL_BASE,
+	[GAUDI_FUNNEL_DMA_IF_E_N]	= mmDMA_IF_E_N_FUNNEL_BASE,
+	[GAUDI_FUNNEL_CPU]		= mmCPU_FUNNEL_BASE,
+	[GAUDI_FUNNEL_NIC_TPC_W_S]	= mmNIC_TPC_FUNNEL_W_S_BASE,
+	[GAUDI_FUNNEL_NIC_TPC_E_S]	= mmNIC_TPC_FUNNEL_E_S_BASE,
+	[GAUDI_FUNNEL_NIC_TPC_W_N]	= mmNIC_TPC_FUNNEL_W_N_BASE,
+	[GAUDI_FUNNEL_NIC_TPC_E_N]	= mmNIC_TPC_FUNNEL_E_N_BASE,
+	[GAUDI_FUNNEL_PCIE]		= mmPCIE_FUNNEL_BASE,
+	[GAUDI_FUNNEL_PSOC]		= mmPSOC_FUNNEL_BASE,
+	[GAUDI_FUNNEL_NIC0]		= mmFUNNEL_NIC0_DBG_BASE,
+	[GAUDI_FUNNEL_NIC1]		= mmFUNNEL_NIC1_DBG_BASE,
+	[GAUDI_FUNNEL_NIC2]		= mmFUNNEL_NIC2_DBG_BASE,
+	[GAUDI_FUNNEL_NIC3]		= mmFUNNEL_NIC3_DBG_BASE,
+	[GAUDI_FUNNEL_NIC4]		= mmFUNNEL_NIC4_DBG_BASE,
+	[GAUDI_FUNNEL_TPC0_EML]		= mmTPC0_EML_FUNNEL_BASE,
+	[GAUDI_FUNNEL_TPC1_EML]		= mmTPC1_EML_FUNNEL_BASE,
+	[GAUDI_FUNNEL_TPC2_EML]		= mmTPC2_EML_FUNNEL_BASE,
+	[GAUDI_FUNNEL_TPC3_EML]		= mmTPC3_EML_FUNNEL_BASE,
+	[GAUDI_FUNNEL_TPC4_EML]		= mmTPC4_EML_FUNNEL_BASE,
+	[GAUDI_FUNNEL_TPC5_EML]		= mmTPC5_EML_FUNNEL_BASE,
+	[GAUDI_FUNNEL_TPC6_EML]		= mmTPC6_EML_FUNNEL_BASE,
+	[GAUDI_FUNNEL_TPC7_EML]		= mmTPC7_EML_FUNNEL_BASE
+};
+
+static u64 debug_bmon_regs[GAUDI_BMON_LAST + 1] = {
+	[GAUDI_BMON_MME0_ACC_0]		= mmMME0_ACC_BMON0_BASE,
+	[GAUDI_BMON_MME0_SBAB_0]	= mmMME0_SBAB_BMON0_BASE,
+	[GAUDI_BMON_MME0_SBAB_1]	= mmMME0_SBAB_BMON1_BASE,
+	[GAUDI_BMON_MME0_CTRL_0]	= mmMME0_CTRL_BMON0_BASE,
+	[GAUDI_BMON_MME0_CTRL_1]	= mmMME0_CTRL_BMON1_BASE,
+	[GAUDI_BMON_MME1_ACC_0]		= mmMME1_ACC_BMON0_BASE,
+	[GAUDI_BMON_MME1_SBAB_0]	= mmMME1_SBAB_BMON0_BASE,
+	[GAUDI_BMON_MME1_SBAB_1]	= mmMME1_SBAB_BMON1_BASE,
+	[GAUDI_BMON_MME1_CTRL_0]	= mmMME1_CTRL_BMON0_BASE,
+	[GAUDI_BMON_MME1_CTRL_1]	= mmMME1_CTRL_BMON1_BASE,
+	[GAUDI_BMON_MME2_ACC_0]		= mmMME2_ACC_BMON0_BASE,
+	[GAUDI_BMON_MME2_SBAB_0]	= mmMME2_SBAB_BMON0_BASE,
+	[GAUDI_BMON_MME2_SBAB_1]	= mmMME2_SBAB_BMON1_BASE,
+	[GAUDI_BMON_MME2_CTRL_0]	= mmMME2_CTRL_BMON0_BASE,
+	[GAUDI_BMON_MME2_CTRL_1]	= mmMME2_CTRL_BMON1_BASE,
+	[GAUDI_BMON_MME3_ACC_0]		= mmMME3_ACC_BMON0_BASE,
+	[GAUDI_BMON_MME3_SBAB_0]	= mmMME3_SBAB_BMON0_BASE,
+	[GAUDI_BMON_MME3_SBAB_1]	= mmMME3_SBAB_BMON1_BASE,
+	[GAUDI_BMON_MME3_CTRL_0]	= mmMME3_CTRL_BMON0_BASE,
+	[GAUDI_BMON_MME3_CTRL_1]	= mmMME3_CTRL_BMON1_BASE,
+	[GAUDI_BMON_DMA_IF_W_S_SOB_WR]	= mmDMA_IF_W_S_SOB_WR_BMON_BASE,
+	[GAUDI_BMON_DMA_IF_W_S_0_WR]	= mmDMA_IF_W_S_HBM0_WR_BMON_BASE,
+	[GAUDI_BMON_DMA_IF_W_S_0_RD]	= mmDMA_IF_W_S_HBM0_RD_BMON_BASE,
+	[GAUDI_BMON_DMA_IF_W_S_1_WR]	= mmDMA_IF_W_S_HBM1_WR_BMON_BASE,
+	[GAUDI_BMON_DMA_IF_W_S_1_RD]	= mmDMA_IF_W_S_HBM1_RD_BMON_BASE,
+	[GAUDI_BMON_DMA_IF_E_S_SOB_WR]	= mmDMA_IF_E_S_SOB_WR_BMON_BASE,
+	[GAUDI_BMON_DMA_IF_E_S_0_WR]	= mmDMA_IF_E_S_HBM0_WR_BMON_BASE,
+	[GAUDI_BMON_DMA_IF_E_S_0_RD]	= mmDMA_IF_E_S_HBM0_RD_BMON_BASE,
+	[GAUDI_BMON_DMA_IF_E_S_1_WR]	= mmDMA_IF_E_S_HBM1_WR_BMON_BASE,
+	[GAUDI_BMON_DMA_IF_E_S_1_RD]	= mmDMA_IF_E_S_HBM1_RD_BMON_BASE,
+	[GAUDI_BMON_DMA_IF_W_N_SOB_WR]	= mmDMA_IF_W_N_SOB_WR_BMON_BASE,
+	[GAUDI_BMON_DMA_IF_W_N_HBM0_WR]	= mmDMA_IF_W_N_HBM0_WR_BMON_BASE,
+	[GAUDI_BMON_DMA_IF_W_N_HBM0_RD]	= mmDMA_IF_W_N_HBM0_RD_BMON_BASE,
+	[GAUDI_BMON_DMA_IF_W_N_HBM1_WR]	= mmDMA_IF_W_N_HBM1_WR_BMON_BASE,
+	[GAUDI_BMON_DMA_IF_W_N_HBM1_RD]	= mmDMA_IF_W_N_HBM1_RD_BMON_BASE,
+	[GAUDI_BMON_DMA_IF_E_N_SOB_WR]	= mmDMA_IF_E_N_SOB_WR_BMON_BASE,
+	[GAUDI_BMON_DMA_IF_E_N_HBM0_WR]	= mmDMA_IF_E_N_HBM0_WR_BMON_BASE,
+	[GAUDI_BMON_DMA_IF_E_N_HBM0_RD]	= mmDMA_IF_E_N_HBM0_RD_BMON_BASE,
+	[GAUDI_BMON_DMA_IF_E_N_HBM1_WR]	= mmDMA_IF_E_N_HBM1_WR_BMON_BASE,
+	[GAUDI_BMON_DMA_IF_E_N_HBM1_RD]	= mmDMA_IF_E_N_HBM1_RD_BMON_BASE,
+	[GAUDI_BMON_CPU_WR]		= mmCPU_WR_BMON_BASE,
+	[GAUDI_BMON_CPU_RD]		= mmCPU_RD_BMON_BASE,
+	[GAUDI_BMON_DMA_CH_0_0]		= mmDMA_CH_0_BMON_0_BASE,
+	[GAUDI_BMON_DMA_CH_0_1]		= mmDMA_CH_0_BMON_1_BASE,
+	[GAUDI_BMON_DMA_CH_1_0]		= mmDMA_CH_1_BMON_0_BASE,
+	[GAUDI_BMON_DMA_CH_1_1]		= mmDMA_CH_1_BMON_1_BASE,
+	[GAUDI_BMON_DMA_CH_2_0]		= mmDMA_CH_2_BMON_0_BASE,
+	[GAUDI_BMON_DMA_CH_2_1]		= mmDMA_CH_2_BMON_1_BASE,
+	[GAUDI_BMON_DMA_CH_3_0]		= mmDMA_CH_3_BMON_0_BASE,
+	[GAUDI_BMON_DMA_CH_3_1]		= mmDMA_CH_3_BMON_1_BASE,
+	[GAUDI_BMON_DMA_CH_4_0]		= mmDMA_CH_4_BMON_0_BASE,
+	[GAUDI_BMON_DMA_CH_4_1]		= mmDMA_CH_4_BMON_1_BASE,
+	[GAUDI_BMON_DMA_CH_5_0]		= mmDMA_CH_5_BMON_0_BASE,
+	[GAUDI_BMON_DMA_CH_5_1]		= mmDMA_CH_5_BMON_1_BASE,
+	[GAUDI_BMON_DMA_CH_6_0]		= mmDMA_CH_6_BMON_0_BASE,
+	[GAUDI_BMON_DMA_CH_6_1]		= mmDMA_CH_6_BMON_1_BASE,
+	[GAUDI_BMON_DMA_CH_7_0]		= mmDMA_CH_7_BMON_0_BASE,
+	[GAUDI_BMON_DMA_CH_7_1]		= mmDMA_CH_7_BMON_1_BASE,
+	[GAUDI_BMON_PCIE_MSTR_WR]	= mmPCIE_BMON_MSTR_WR_BASE,
+	[GAUDI_BMON_PCIE_MSTR_RD]	= mmPCIE_BMON_MSTR_RD_BASE,
+	[GAUDI_BMON_PCIE_SLV_WR]	= mmPCIE_BMON_SLV_WR_BASE,
+	[GAUDI_BMON_PCIE_SLV_RD]	= mmPCIE_BMON_SLV_RD_BASE,
+	[GAUDI_BMON_MMU_0]		= mmMMU_BMON_0_BASE,
+	[GAUDI_BMON_MMU_1]		= mmMMU_BMON_1_BASE,
+	[GAUDI_BMON_NIC0_0]		= mmBMON0_NIC0_DBG_BASE,
+	[GAUDI_BMON_NIC0_1]		= mmBMON1_NIC0_DBG_BASE,
+	[GAUDI_BMON_NIC0_2]		= mmBMON2_NIC0_DBG_BASE,
+	[GAUDI_BMON_NIC0_3]		= mmBMON3_NIC0_DBG_BASE,
+	[GAUDI_BMON_NIC0_4]		= mmBMON4_NIC0_DBG_BASE,
+	[GAUDI_BMON_NIC1_0]		= mmBMON0_NIC1_DBG_BASE,
+	[GAUDI_BMON_NIC1_1]		= mmBMON1_NIC1_DBG_BASE,
+	[GAUDI_BMON_NIC1_2]		= mmBMON2_NIC1_DBG_BASE,
+	[GAUDI_BMON_NIC1_3]		= mmBMON3_NIC1_DBG_BASE,
+	[GAUDI_BMON_NIC1_4]		= mmBMON4_NIC1_DBG_BASE,
+	[GAUDI_BMON_NIC2_0]		= mmBMON0_NIC2_DBG_BASE,
+	[GAUDI_BMON_NIC2_1]		= mmBMON1_NIC2_DBG_BASE,
+	[GAUDI_BMON_NIC2_2]		= mmBMON2_NIC2_DBG_BASE,
+	[GAUDI_BMON_NIC2_3]		= mmBMON3_NIC2_DBG_BASE,
+	[GAUDI_BMON_NIC2_4]		= mmBMON4_NIC2_DBG_BASE,
+	[GAUDI_BMON_NIC3_0]		= mmBMON0_NIC3_DBG_BASE,
+	[GAUDI_BMON_NIC3_1]		= mmBMON1_NIC3_DBG_BASE,
+	[GAUDI_BMON_NIC3_2]		= mmBMON2_NIC3_DBG_BASE,
+	[GAUDI_BMON_NIC3_3]		= mmBMON3_NIC3_DBG_BASE,
+	[GAUDI_BMON_NIC3_4]		= mmBMON4_NIC3_DBG_BASE,
+	[GAUDI_BMON_NIC4_0]		= mmBMON0_NIC4_DBG_BASE,
+	[GAUDI_BMON_NIC4_1]		= mmBMON1_NIC4_DBG_BASE,
+	[GAUDI_BMON_NIC4_2]		= mmBMON2_NIC4_DBG_BASE,
+	[GAUDI_BMON_NIC4_3]		= mmBMON3_NIC4_DBG_BASE,
+	[GAUDI_BMON_NIC4_4]		= mmBMON4_NIC4_DBG_BASE,
+	[GAUDI_BMON_TPC0_EML_0]		= mmTPC0_EML_BUSMON_0_BASE,
+	[GAUDI_BMON_TPC0_EML_1]		= mmTPC0_EML_BUSMON_1_BASE,
+	[GAUDI_BMON_TPC0_EML_2]		= mmTPC0_EML_BUSMON_2_BASE,
+	[GAUDI_BMON_TPC0_EML_3]		= mmTPC0_EML_BUSMON_3_BASE,
+	[GAUDI_BMON_TPC1_EML_0]		= mmTPC1_EML_BUSMON_0_BASE,
+	[GAUDI_BMON_TPC1_EML_1]		= mmTPC1_EML_BUSMON_1_BASE,
+	[GAUDI_BMON_TPC1_EML_2]		= mmTPC1_EML_BUSMON_2_BASE,
+	[GAUDI_BMON_TPC1_EML_3]		= mmTPC1_EML_BUSMON_3_BASE,
+	[GAUDI_BMON_TPC2_EML_0]		= mmTPC2_EML_BUSMON_0_BASE,
+	[GAUDI_BMON_TPC2_EML_1]		= mmTPC2_EML_BUSMON_1_BASE,
+	[GAUDI_BMON_TPC2_EML_2]		= mmTPC2_EML_BUSMON_2_BASE,
+	[GAUDI_BMON_TPC2_EML_3]		= mmTPC2_EML_BUSMON_3_BASE,
+	[GAUDI_BMON_TPC3_EML_0]		= mmTPC3_EML_BUSMON_0_BASE,
+	[GAUDI_BMON_TPC3_EML_1]		= mmTPC3_EML_BUSMON_1_BASE,
+	[GAUDI_BMON_TPC3_EML_2]		= mmTPC3_EML_BUSMON_2_BASE,
+	[GAUDI_BMON_TPC3_EML_3]		= mmTPC3_EML_BUSMON_3_BASE,
+	[GAUDI_BMON_TPC4_EML_0]		= mmTPC4_EML_BUSMON_0_BASE,
+	[GAUDI_BMON_TPC4_EML_1]		= mmTPC4_EML_BUSMON_1_BASE,
+	[GAUDI_BMON_TPC4_EML_2]		= mmTPC4_EML_BUSMON_2_BASE,
+	[GAUDI_BMON_TPC4_EML_3]		= mmTPC4_EML_BUSMON_3_BASE,
+	[GAUDI_BMON_TPC5_EML_0]		= mmTPC5_EML_BUSMON_0_BASE,
+	[GAUDI_BMON_TPC5_EML_1]		= mmTPC5_EML_BUSMON_1_BASE,
+	[GAUDI_BMON_TPC5_EML_2]		= mmTPC5_EML_BUSMON_2_BASE,
+	[GAUDI_BMON_TPC5_EML_3]		= mmTPC5_EML_BUSMON_3_BASE,
+	[GAUDI_BMON_TPC6_EML_0]		= mmTPC6_EML_BUSMON_0_BASE,
+	[GAUDI_BMON_TPC6_EML_1]		= mmTPC6_EML_BUSMON_1_BASE,
+	[GAUDI_BMON_TPC6_EML_2]		= mmTPC6_EML_BUSMON_2_BASE,
+	[GAUDI_BMON_TPC6_EML_3]		= mmTPC6_EML_BUSMON_3_BASE,
+	[GAUDI_BMON_TPC7_EML_0]		= mmTPC7_EML_BUSMON_0_BASE,
+	[GAUDI_BMON_TPC7_EML_1]		= mmTPC7_EML_BUSMON_1_BASE,
+	[GAUDI_BMON_TPC7_EML_2]		= mmTPC7_EML_BUSMON_2_BASE,
+	[GAUDI_BMON_TPC7_EML_3]		= mmTPC7_EML_BUSMON_3_BASE
+};
+
+static u64 debug_spmu_regs[GAUDI_SPMU_LAST + 1] = {
+	[GAUDI_SPMU_MME0_ACC]		= mmMME0_ACC_SPMU_BASE,
+	[GAUDI_SPMU_MME0_SBAB]		= mmMME0_SBAB_SPMU_BASE,
+	[GAUDI_SPMU_MME0_CTRL]		= mmMME0_CTRL_SPMU_BASE,
+	[GAUDI_SPMU_MME1_ACC]		= mmMME1_ACC_SPMU_BASE,
+	[GAUDI_SPMU_MME1_SBAB]		= mmMME1_SBAB_SPMU_BASE,
+	[GAUDI_SPMU_MME1_CTRL]		= mmMME1_CTRL_SPMU_BASE,
+	[GAUDI_SPMU_MME2_MME2_ACC]	= mmMME2_ACC_SPMU_BASE,
+	[GAUDI_SPMU_MME2_SBAB]		= mmMME2_SBAB_SPMU_BASE,
+	[GAUDI_SPMU_MME2_CTRL]		= mmMME2_CTRL_SPMU_BASE,
+	[GAUDI_SPMU_MME3_ACC]		= mmMME3_ACC_SPMU_BASE,
+	[GAUDI_SPMU_MME3_SBAB]		= mmMME3_SBAB_SPMU_BASE,
+	[GAUDI_SPMU_MME3_CTRL]		= mmMME3_CTRL_SPMU_BASE,
+	[GAUDI_SPMU_DMA_CH_0_CS]	= mmDMA_CH_0_CS_SPMU_BASE,
+	[GAUDI_SPMU_DMA_CH_1_CS]	= mmDMA_CH_1_CS_SPMU_BASE,
+	[GAUDI_SPMU_DMA_CH_2_CS]	= mmDMA_CH_2_CS_SPMU_BASE,
+	[GAUDI_SPMU_DMA_CH_3_CS]	= mmDMA_CH_3_CS_SPMU_BASE,
+	[GAUDI_SPMU_DMA_CH_4_CS]	= mmDMA_CH_4_CS_SPMU_BASE,
+	[GAUDI_SPMU_DMA_CH_5_CS]	= mmDMA_CH_5_CS_SPMU_BASE,
+	[GAUDI_SPMU_DMA_CH_6_CS]	= mmDMA_CH_6_CS_SPMU_BASE,
+	[GAUDI_SPMU_DMA_CH_7_CS]	= mmDMA_CH_7_CS_SPMU_BASE,
+	[GAUDI_SPMU_PCIE]		= mmPCIE_SPMU_BASE,
+	[GAUDI_SPMU_MMU_CS]		= mmMMU_CS_SPMU_BASE,
+	[GAUDI_SPMU_NIC0_0]		= mmSPMU_0_NIC0_DBG_BASE,
+	[GAUDI_SPMU_NIC0_1]		= mmSPMU_1_NIC0_DBG_BASE,
+	[GAUDI_SPMU_NIC1_0]		= mmSPMU_0_NIC1_DBG_BASE,
+	[GAUDI_SPMU_NIC1_1]		= mmSPMU_1_NIC1_DBG_BASE,
+	[GAUDI_SPMU_NIC2_0]		= mmSPMU_0_NIC2_DBG_BASE,
+	[GAUDI_SPMU_NIC2_1]		= mmSPMU_1_NIC2_DBG_BASE,
+	[GAUDI_SPMU_NIC3_0]		= mmSPMU_0_NIC3_DBG_BASE,
+	[GAUDI_SPMU_NIC3_1]		= mmSPMU_1_NIC3_DBG_BASE,
+	[GAUDI_SPMU_NIC4_0]		= mmSPMU_0_NIC4_DBG_BASE,
+	[GAUDI_SPMU_NIC4_1]		= mmSPMU_1_NIC4_DBG_BASE,
+	[GAUDI_SPMU_TPC0_EML]		= mmTPC0_EML_SPMU_BASE,
+	[GAUDI_SPMU_TPC1_EML]		= mmTPC1_EML_SPMU_BASE,
+	[GAUDI_SPMU_TPC2_EML]		= mmTPC2_EML_SPMU_BASE,
+	[GAUDI_SPMU_TPC3_EML]		= mmTPC3_EML_SPMU_BASE,
+	[GAUDI_SPMU_TPC4_EML]		= mmTPC4_EML_SPMU_BASE,
+	[GAUDI_SPMU_TPC5_EML]		= mmTPC5_EML_SPMU_BASE,
+	[GAUDI_SPMU_TPC6_EML]		= mmTPC6_EML_SPMU_BASE,
+	[GAUDI_SPMU_TPC7_EML]		= mmTPC7_EML_SPMU_BASE
+};
+
+static int gaudi_coresight_timeout(struct hl_device *hdev, u64 addr,
+		int position, bool up)
+{
+	int rc;
+	u32 val;
+
+	rc = hl_poll_timeout(
+		hdev,
+		addr,
+		val,
+		up ? val & BIT(position) : !(val & BIT(position)),
+		1000,
+		CORESIGHT_TIMEOUT_USEC);
+
+	if (rc) {
+		dev_err(hdev->dev,
+			"Timeout while waiting for coresight, addr: 0x%llx, position: %d, up: %d\n",
+				addr, position, up);
+		return -EFAULT;
+	}
+
+	return 0;
+}
+
+static int gaudi_config_stm(struct hl_device *hdev,
+		struct hl_debug_params *params)
+{
+	struct hl_debug_params_stm *input;
+	u64 base_reg;
+	u32 frequency;
+	int rc;
+
+	if (params->reg_idx >= ARRAY_SIZE(debug_stm_regs)) {
+		dev_err(hdev->dev, "Invalid register index in STM\n");
+		return -EINVAL;
+	}
+
+	base_reg = debug_stm_regs[params->reg_idx] - CFG_BASE;
+
+	WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);
+
+	if (params->enable) {
+		input = params->input;
+
+		if (!input)
+			return -EINVAL;
+
+		WREG32(base_reg + 0xE80, 0x80004);
+		WREG32(base_reg + 0xD64, 7);
+		WREG32(base_reg + 0xD60, 0);
+		WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask));
+		WREG32(base_reg + 0xD60, 1);
+		WREG32(base_reg + 0xD00, upper_32_bits(input->he_mask));
+		WREG32(base_reg + 0xE70, 0x10);
+		WREG32(base_reg + 0xE60, 0);
+		WREG32(base_reg + 0xE00, lower_32_bits(input->sp_mask));
+		WREG32(base_reg + 0xEF4, input->id);
+		WREG32(base_reg + 0xDF4, 0x80);
+		frequency = hdev->asic_prop.psoc_timestamp_frequency;
+		if (frequency == 0)
+			frequency = input->frequency;
+		WREG32(base_reg + 0xE8C, frequency);
+		WREG32(base_reg + 0xE90, 0x1F00);
+
+		/* SW-2176 - SW WA for HW bug */
+		if ((CFG_BASE + base_reg) >= mmDMA_CH_0_CS_STM_BASE &&
+			(CFG_BASE + base_reg) <= mmDMA_CH_7_CS_STM_BASE) {
+
+			WREG32(base_reg + 0xE68, 0xffff8005);
+			WREG32(base_reg + 0xE6C, 0x0);
+		}
+
+		WREG32(base_reg + 0xE80, 0x23 | (input->id << 16));
+	} else {
+		WREG32(base_reg + 0xE80, 4);
+		WREG32(base_reg + 0xD64, 0);
+		WREG32(base_reg + 0xD60, 1);
+		WREG32(base_reg + 0xD00, 0);
+		WREG32(base_reg + 0xD20, 0);
+		WREG32(base_reg + 0xD60, 0);
+		WREG32(base_reg + 0xE20, 0);
+		WREG32(base_reg + 0xE00, 0);
+		WREG32(base_reg + 0xDF4, 0x80);
+		WREG32(base_reg + 0xE70, 0);
+		WREG32(base_reg + 0xE60, 0);
+		WREG32(base_reg + 0xE64, 0);
+		WREG32(base_reg + 0xE8C, 0);
+
+		rc = gaudi_coresight_timeout(hdev, base_reg + 0xE80, 23, false);
+		if (rc) {
+			dev_err(hdev->dev,
+				"Failed to disable STM on timeout, error %d\n",
+				rc);
+			return rc;
+		}
+
+		WREG32(base_reg + 0xE80, 4);
+	}
+
+	return 0;
+}
+
+static int gaudi_config_etf(struct hl_device *hdev,
+		struct hl_debug_params *params)
+{
+	struct hl_debug_params_etf *input;
+	u64 base_reg;
+	u32 val;
+	int rc;
+
+	if (params->reg_idx >= ARRAY_SIZE(debug_etf_regs)) {
+		dev_err(hdev->dev, "Invalid register index in ETF\n");
+		return -EINVAL;
+	}
+
+	base_reg = debug_etf_regs[params->reg_idx] - CFG_BASE;
+
+	WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);
+
+	val = RREG32(base_reg + 0x20);
+
+	if ((!params->enable && val == 0x0) || (params->enable && val != 0x0))
+		return 0;
+
+	val = RREG32(base_reg + 0x304);
+	val |= 0x1000;
+	WREG32(base_reg + 0x304, val);
+	val |= 0x40;
+	WREG32(base_reg + 0x304, val);
+
+	rc = gaudi_coresight_timeout(hdev, base_reg + 0x304, 6, false);
+	if (rc) {
+		dev_err(hdev->dev,
+			"Failed to %s ETF on timeout, error %d\n",
+				params->enable ? "enable" : "disable", rc);
+		return rc;
+	}
+
+	rc = gaudi_coresight_timeout(hdev, base_reg + 0xC, 2, true);
+	if (rc) {
+		dev_err(hdev->dev,
+			"Failed to %s ETF on timeout, error %d\n",
+				params->enable ? "enable" : "disable", rc);
+		return rc;
+	}
+
+	WREG32(base_reg + 0x20, 0);
+
+	if (params->enable) {
+		input = params->input;
+
+		if (!input)
+			return -EINVAL;
+
+		WREG32(base_reg + 0x34, 0x3FFC);
+		WREG32(base_reg + 0x28, input->sink_mode);
+		WREG32(base_reg + 0x304, 0x4001);
+		WREG32(base_reg + 0x308, 0xA);
+		WREG32(base_reg + 0x20, 1);
+	} else {
+		WREG32(base_reg + 0x34, 0);
+		WREG32(base_reg + 0x28, 0);
+		WREG32(base_reg + 0x304, 0);
+	}
+
+	return 0;
+}
+
+static bool gaudi_etr_validate_address(struct hl_device *hdev, u64 addr,
+					u64 size, bool *is_host)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct gaudi_device *gaudi = hdev->asic_specific;
+
+	/* maximum address length is 50 bits */
+	if (addr >> 50) {
+		dev_err(hdev->dev,
+			"ETR buffer address shouldn't exceed 50 bits\n");
+		return false;
+	}
+
+	if (addr > (addr + size)) {
+		dev_err(hdev->dev,
+			"ETR buffer size %llu overflow\n", size);
+		return false;
+	}
+
+	/* PMMU and HPMMU addresses are equal, check only one of them */
+	if ((gaudi->hw_cap_initialized & HW_CAP_MMU) &&
+		hl_mem_area_inside_range(addr, size,
+				prop->pmmu.start_addr,
+				prop->pmmu.end_addr)) {
+		*is_host = true;
+		return true;
+	}
+
+	if (hl_mem_area_inside_range(addr, size,
+			prop->dram_user_base_address,
+			prop->dram_end_address))
+		return true;
+
+	if (hl_mem_area_inside_range(addr, size,
+			prop->sram_user_base_address,
+			prop->sram_end_address))
+		return true;
+
+	if (!(gaudi->hw_cap_initialized & HW_CAP_MMU))
+		dev_err(hdev->dev, "ETR buffer should be in SRAM/DRAM\n");
+
+	return false;
+}
+
+static int gaudi_config_etr(struct hl_device *hdev,
+		struct hl_debug_params *params)
+{
+	struct hl_debug_params_etr *input;
+	u64 msb;
+	u32 val;
+	int rc;
+
+	WREG32(mmPSOC_ETR_LAR, CORESIGHT_UNLOCK);
+
+	val = RREG32(mmPSOC_ETR_CTL);
+
+	if ((!params->enable && val == 0x0) || (params->enable && val != 0x0))
+		return 0;
+
+
+
+	val = RREG32(mmPSOC_ETR_FFCR);
+	val |= 0x1000;
+	WREG32(mmPSOC_ETR_FFCR, val);
+	val |= 0x40;
+	WREG32(mmPSOC_ETR_FFCR, val);
+
+	rc = gaudi_coresight_timeout(hdev, mmPSOC_ETR_FFCR, 6, false);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n",
+				params->enable ? "enable" : "disable", rc);
+		return rc;
+	}
+
+	rc = gaudi_coresight_timeout(hdev, mmPSOC_ETR_STS, 2, true);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n",
+				params->enable ? "enable" : "disable", rc);
+		return rc;
+	}
+
+	WREG32(mmPSOC_ETR_CTL, 0);
+
+	if (params->enable) {
+		bool is_host = false;
+
+		input = params->input;
+
+		if (!input)
+			return -EINVAL;
+
+		if (input->buffer_size == 0) {
+			dev_err(hdev->dev,
+				"ETR buffer size should be bigger than 0\n");
+			return -EINVAL;
+		}
+
+		if (!gaudi_etr_validate_address(hdev,
+				input->buffer_address, input->buffer_size,
+				&is_host)) {
+			dev_err(hdev->dev, "ETR buffer address is invalid\n");
+			return -EINVAL;
+		}
+
+		msb = upper_32_bits(input->buffer_address) >> 8;
+		msb &= PSOC_GLOBAL_CONF_TRACE_ADDR_MSB_MASK;
+		WREG32(mmPSOC_GLOBAL_CONF_TRACE_ADDR, msb);
+
+		WREG32(mmPSOC_ETR_BUFWM, 0x3FFC);
+		WREG32(mmPSOC_ETR_RSZ, input->buffer_size);
+		WREG32(mmPSOC_ETR_MODE, input->sink_mode);
+		if (!hdev->asic_prop.fw_security_enabled) {
+			/* make ETR not privileged */
+			val = FIELD_PREP(
+					PSOC_ETR_AXICTL_PROTCTRLBIT0_MASK, 0);
+			/* make ETR non-secured (inverted logic) */
+			val |= FIELD_PREP(
+					PSOC_ETR_AXICTL_PROTCTRLBIT1_MASK, 1);
+			/*
+			 * Workaround for H3 #HW-2075 bug: use small data
+			 * chunks
+			 */
+			val |= FIELD_PREP(PSOC_ETR_AXICTL_WRBURSTLEN_MASK,
+							is_host ? 0 : 7);
+			WREG32(mmPSOC_ETR_AXICTL, val);
+		}
+		WREG32(mmPSOC_ETR_DBALO,
+				lower_32_bits(input->buffer_address));
+		WREG32(mmPSOC_ETR_DBAHI,
+				upper_32_bits(input->buffer_address));
+		WREG32(mmPSOC_ETR_FFCR, 3);
+		WREG32(mmPSOC_ETR_PSCR, 0xA);
+		WREG32(mmPSOC_ETR_CTL, 1);
+	} else {
+		WREG32(mmPSOC_ETR_BUFWM, 0);
+		WREG32(mmPSOC_ETR_RSZ, 0x400);
+		WREG32(mmPSOC_ETR_DBALO, 0);
+		WREG32(mmPSOC_ETR_DBAHI, 0);
+		WREG32(mmPSOC_ETR_PSCR, 0);
+		WREG32(mmPSOC_ETR_MODE, 0);
+		WREG32(mmPSOC_ETR_FFCR, 0);
+
+		if (params->output_size >= sizeof(u64)) {
+			u32 rwp, rwphi;
+
+			/*
+			 * The trace buffer address is 50 bits wide. The end of
+			 * the buffer is set in the RWP register (lower 32
+			 * bits), and in the RWPHI register (upper 8 bits).
+			 * The 10 msb of the 50-bit address are stored in a
+			 * global configuration register.
+			 */
+			rwp = RREG32(mmPSOC_ETR_RWP);
+			rwphi = RREG32(mmPSOC_ETR_RWPHI) & 0xff;
+			msb = RREG32(mmPSOC_GLOBAL_CONF_TRACE_ADDR) &
+					PSOC_GLOBAL_CONF_TRACE_ADDR_MSB_MASK;
+			*(u64 *) params->output = ((u64) msb << 40) |
+						((u64) rwphi << 32) | rwp;
+		}
+	}
+
+	return 0;
+}
+
+static int gaudi_config_funnel(struct hl_device *hdev,
+		struct hl_debug_params *params)
+{
+	u64 base_reg;
+
+	if (params->reg_idx >= ARRAY_SIZE(debug_funnel_regs)) {
+		dev_err(hdev->dev, "Invalid register index in FUNNEL\n");
+		return -EINVAL;
+	}
+
+	base_reg = debug_funnel_regs[params->reg_idx] - CFG_BASE;
+
+	WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);
+
+	WREG32(base_reg, params->enable ? 0x33F : 0);
+
+	return 0;
+}
+
+static int gaudi_config_bmon(struct hl_device *hdev,
+		struct hl_debug_params *params)
+{
+	struct hl_debug_params_bmon *input;
+	u64 base_reg;
+
+	if (params->reg_idx >= ARRAY_SIZE(debug_bmon_regs)) {
+		dev_err(hdev->dev, "Invalid register index in BMON\n");
+		return -EINVAL;
+	}
+
+	base_reg = debug_bmon_regs[params->reg_idx] - CFG_BASE;
+
+	WREG32(base_reg + 0x104, 1);
+
+	if (params->enable) {
+		input = params->input;
+
+		if (!input)
+			return -EINVAL;
+
+		WREG32(base_reg + 0x200, lower_32_bits(input->start_addr0));
+		WREG32(base_reg + 0x204, upper_32_bits(input->start_addr0));
+		WREG32(base_reg + 0x208, lower_32_bits(input->addr_mask0));
+		WREG32(base_reg + 0x20C, upper_32_bits(input->addr_mask0));
+		WREG32(base_reg + 0x240, lower_32_bits(input->start_addr1));
+		WREG32(base_reg + 0x244, upper_32_bits(input->start_addr1));
+		WREG32(base_reg + 0x248, lower_32_bits(input->addr_mask1));
+		WREG32(base_reg + 0x24C, upper_32_bits(input->addr_mask1));
+		WREG32(base_reg + 0x224, 0);
+		WREG32(base_reg + 0x234, 0);
+		WREG32(base_reg + 0x30C, input->bw_win);
+		WREG32(base_reg + 0x308, input->win_capture);
+		WREG32(base_reg + 0x700, 0xA000B00 | (input->id << 12));
+		WREG32(base_reg + 0x708, 0xA000A00 | (input->id << 12));
+		WREG32(base_reg + 0x70C, 0xA000C00 | (input->id << 12));
+		WREG32(base_reg + 0x100, 0x11);
+		WREG32(base_reg + 0x304, 0x1);
+	} else {
+		WREG32(base_reg + 0x200, 0);
+		WREG32(base_reg + 0x204, 0);
+		WREG32(base_reg + 0x208, 0xFFFFFFFF);
+		WREG32(base_reg + 0x20C, 0xFFFFFFFF);
+		WREG32(base_reg + 0x240, 0);
+		WREG32(base_reg + 0x244, 0);
+		WREG32(base_reg + 0x248, 0xFFFFFFFF);
+		WREG32(base_reg + 0x24C, 0xFFFFFFFF);
+		WREG32(base_reg + 0x224, 0xFFFFFFFF);
+		WREG32(base_reg + 0x234, 0x1070F);
+		WREG32(base_reg + 0x30C, 0);
+		WREG32(base_reg + 0x308, 0xFFFF);
+		WREG32(base_reg + 0x700, 0xA000B00);
+		WREG32(base_reg + 0x708, 0xA000A00);
+		WREG32(base_reg + 0x70C, 0xA000C00);
+		WREG32(base_reg + 0x100, 1);
+		WREG32(base_reg + 0x304, 0);
+		WREG32(base_reg + 0x104, 0);
+	}
+
+	return 0;
+}
+
+static int gaudi_config_spmu(struct hl_device *hdev,
+		struct hl_debug_params *params)
+{
+	u64 base_reg;
+	struct hl_debug_params_spmu *input = params->input;
+	u64 *output;
+	u32 output_arr_len;
+	u32 events_num;
+	u32 overflow_idx;
+	u32 cycle_cnt_idx;
+	int i;
+
+	if (params->reg_idx >= ARRAY_SIZE(debug_spmu_regs)) {
+		dev_err(hdev->dev, "Invalid register index in SPMU\n");
+		return -EINVAL;
+	}
+
+	base_reg = debug_spmu_regs[params->reg_idx] - CFG_BASE;
+
+	if (params->enable) {
+		input = params->input;
+
+		if (!input)
+			return -EINVAL;
+
+		if (input->event_types_num < 3) {
+			dev_err(hdev->dev,
+				"not enough event types values for SPMU enable\n");
+			return -EINVAL;
+		}
+
+		if (input->event_types_num > SPMU_MAX_COUNTERS) {
+			dev_err(hdev->dev,
+				"too many event types values for SPMU enable\n");
+			return -EINVAL;
+		}
+
+		WREG32(base_reg + 0xE04, 0x41013046);
+		WREG32(base_reg + 0xE04, 0x41013040);
+
+		for (i = 0 ; i < input->event_types_num ; i++)
+			WREG32(base_reg + SPMU_EVENT_TYPES_OFFSET + i * 4,
+				input->event_types[i]);
+
+		WREG32(base_reg + 0xE04, 0x41013041);
+		WREG32(base_reg + 0xC00, 0x8000003F);
+	} else {
+		output = params->output;
+		output_arr_len = params->output_size / 8;
+		events_num = output_arr_len - 2;
+		overflow_idx = output_arr_len - 2;
+		cycle_cnt_idx = output_arr_len - 1;
+
+		if (!output)
+			return -EINVAL;
+
+		if (output_arr_len < 3) {
+			dev_err(hdev->dev,
+				"not enough values for SPMU disable\n");
+			return -EINVAL;
+		}
+
+		if (events_num > SPMU_MAX_COUNTERS) {
+			dev_err(hdev->dev,
+				"too many events values for SPMU disable\n");
+			return -EINVAL;
+		}
+
+		WREG32(base_reg + 0xE04, 0x41013040);
+
+		for (i = 0 ; i < events_num ; i++)
+			output[i] = RREG32(base_reg + i * 8);
+
+		output[overflow_idx] = RREG32(base_reg + 0xCC0);
+
+		output[cycle_cnt_idx] = RREG32(base_reg + 0xFC);
+		output[cycle_cnt_idx] <<= 32;
+		output[cycle_cnt_idx] |= RREG32(base_reg + 0xF8);
+
+		WREG32(base_reg + 0xCC0, 0);
+	}
+
+	return 0;
+}
+
+int gaudi_debug_coresight(struct hl_device *hdev, struct hl_ctx *ctx, void *data)
+{
+	struct hl_debug_params *params = data;
+	int rc = 0;
+
+	switch (params->op) {
+	case HL_DEBUG_OP_STM:
+		rc = gaudi_config_stm(hdev, params);
+		break;
+	case HL_DEBUG_OP_ETF:
+		rc = gaudi_config_etf(hdev, params);
+		break;
+	case HL_DEBUG_OP_ETR:
+		rc = gaudi_config_etr(hdev, params);
+		break;
+	case HL_DEBUG_OP_FUNNEL:
+		rc = gaudi_config_funnel(hdev, params);
+		break;
+	case HL_DEBUG_OP_BMON:
+		rc = gaudi_config_bmon(hdev, params);
+		break;
+	case HL_DEBUG_OP_SPMU:
+		rc = gaudi_config_spmu(hdev, params);
+		break;
+	case HL_DEBUG_OP_TIMESTAMP:
+		/* Do nothing as this opcode is deprecated */
+		break;
+
+	default:
+		dev_err(hdev->dev, "Unknown coresight id %d\n", params->op);
+		return -EINVAL;
+	}
+
+	/* Perform read from the device to flush all configuration */
+	RREG32(mmHW_STATE);
+
+	return rc;
+}
+
+void gaudi_halt_coresight(struct hl_device *hdev, struct hl_ctx *ctx)
+{
+	struct hl_debug_params params = {};
+	int i, rc;
+
+	for (i = GAUDI_ETF_FIRST ; i <= GAUDI_ETF_LAST ; i++) {
+		params.reg_idx = i;
+		rc = gaudi_config_etf(hdev, &params);
+		if (rc)
+			dev_err(hdev->dev, "halt ETF failed, %d/%d\n", rc, i);
+	}
+
+	rc = gaudi_config_etr(hdev, &params);
+	if (rc)
+		dev_err(hdev->dev, "halt ETR failed, %d\n", rc);
+}
diff --git a/drivers/accel/habanalabs/gaudi/gaudi_security.c b/drivers/accel/habanalabs/gaudi/gaudi_security.c
new file mode 100644
index 000000000000..81a3c79a8bc6
--- /dev/null
+++ b/drivers/accel/habanalabs/gaudi/gaudi_security.c
@@ -0,0 +1,13079 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ */
+
+#include "gaudiP.h"
+#include "../include/gaudi/asic_reg/gaudi_regs.h"
+
+#define GAUDI_NUMBER_OF_LBW_RR_REGS	28
+#define GAUDI_NUMBER_OF_HBW_RR_REGS	24
+#define GAUDI_NUMBER_OF_LBW_RANGES	10
+
+static u64 gaudi_rr_lbw_hit_aw_regs[GAUDI_NUMBER_OF_LBW_RR_REGS] = {
+	mmDMA_IF_W_S_SOB_HIT_WPROT,
+	mmDMA_IF_W_S_DMA0_HIT_WPROT,
+	mmDMA_IF_W_S_DMA1_HIT_WPROT,
+	mmDMA_IF_E_S_SOB_HIT_WPROT,
+	mmDMA_IF_E_S_DMA0_HIT_WPROT,
+	mmDMA_IF_E_S_DMA1_HIT_WPROT,
+	mmDMA_IF_W_N_SOB_HIT_WPROT,
+	mmDMA_IF_W_N_DMA0_HIT_WPROT,
+	mmDMA_IF_W_N_DMA1_HIT_WPROT,
+	mmDMA_IF_E_N_SOB_HIT_WPROT,
+	mmDMA_IF_E_N_DMA0_HIT_WPROT,
+	mmDMA_IF_E_N_DMA1_HIT_WPROT,
+	mmSIF_RTR_0_LBW_RANGE_PROT_HIT_AW,
+	mmSIF_RTR_1_LBW_RANGE_PROT_HIT_AW,
+	mmSIF_RTR_2_LBW_RANGE_PROT_HIT_AW,
+	mmSIF_RTR_3_LBW_RANGE_PROT_HIT_AW,
+	mmSIF_RTR_4_LBW_RANGE_PROT_HIT_AW,
+	mmSIF_RTR_5_LBW_RANGE_PROT_HIT_AW,
+	mmSIF_RTR_6_LBW_RANGE_PROT_HIT_AW,
+	mmSIF_RTR_7_LBW_RANGE_PROT_HIT_AW,
+	mmNIF_RTR_0_LBW_RANGE_PROT_HIT_AW,
+	mmNIF_RTR_1_LBW_RANGE_PROT_HIT_AW,
+	mmNIF_RTR_2_LBW_RANGE_PROT_HIT_AW,
+	mmNIF_RTR_3_LBW_RANGE_PROT_HIT_AW,
+	mmNIF_RTR_4_LBW_RANGE_PROT_HIT_AW,
+	mmNIF_RTR_5_LBW_RANGE_PROT_HIT_AW,
+	mmNIF_RTR_6_LBW_RANGE_PROT_HIT_AW,
+	mmNIF_RTR_7_LBW_RANGE_PROT_HIT_AW,
+};
+
+static u64 gaudi_rr_lbw_hit_ar_regs[GAUDI_NUMBER_OF_LBW_RR_REGS] = {
+	mmDMA_IF_W_S_SOB_HIT_RPROT,
+	mmDMA_IF_W_S_DMA0_HIT_RPROT,
+	mmDMA_IF_W_S_DMA1_HIT_RPROT,
+	mmDMA_IF_E_S_SOB_HIT_RPROT,
+	mmDMA_IF_E_S_DMA0_HIT_RPROT,
+	mmDMA_IF_E_S_DMA1_HIT_RPROT,
+	mmDMA_IF_W_N_SOB_HIT_RPROT,
+	mmDMA_IF_W_N_DMA0_HIT_RPROT,
+	mmDMA_IF_W_N_DMA1_HIT_RPROT,
+	mmDMA_IF_E_N_SOB_HIT_RPROT,
+	mmDMA_IF_E_N_DMA0_HIT_RPROT,
+	mmDMA_IF_E_N_DMA1_HIT_RPROT,
+	mmSIF_RTR_0_LBW_RANGE_PROT_HIT_AR,
+	mmSIF_RTR_1_LBW_RANGE_PROT_HIT_AR,
+	mmSIF_RTR_2_LBW_RANGE_PROT_HIT_AR,
+	mmSIF_RTR_3_LBW_RANGE_PROT_HIT_AR,
+	mmSIF_RTR_4_LBW_RANGE_PROT_HIT_AR,
+	mmSIF_RTR_5_LBW_RANGE_PROT_HIT_AR,
+	mmSIF_RTR_6_LBW_RANGE_PROT_HIT_AR,
+	mmSIF_RTR_7_LBW_RANGE_PROT_HIT_AR,
+	mmNIF_RTR_0_LBW_RANGE_PROT_HIT_AR,
+	mmNIF_RTR_1_LBW_RANGE_PROT_HIT_AR,
+	mmNIF_RTR_2_LBW_RANGE_PROT_HIT_AR,
+	mmNIF_RTR_3_LBW_RANGE_PROT_HIT_AR,
+	mmNIF_RTR_4_LBW_RANGE_PROT_HIT_AR,
+	mmNIF_RTR_5_LBW_RANGE_PROT_HIT_AR,
+	mmNIF_RTR_6_LBW_RANGE_PROT_HIT_AR,
+	mmNIF_RTR_7_LBW_RANGE_PROT_HIT_AR,
+};
+
+static u64 gaudi_rr_lbw_min_aw_regs[GAUDI_NUMBER_OF_LBW_RR_REGS] = {
+	mmDMA_IF_W_S_SOB_MIN_WPROT_0,
+	mmDMA_IF_W_S_DMA0_MIN_WPROT_0,
+	mmDMA_IF_W_S_DMA1_MIN_WPROT_0,
+	mmDMA_IF_E_S_SOB_MIN_WPROT_0,
+	mmDMA_IF_E_S_DMA0_MIN_WPROT_0,
+	mmDMA_IF_E_S_DMA1_MIN_WPROT_0,
+	mmDMA_IF_W_N_SOB_MIN_WPROT_0,
+	mmDMA_IF_W_N_DMA0_MIN_WPROT_0,
+	mmDMA_IF_W_N_DMA1_MIN_WPROT_0,
+	mmDMA_IF_E_N_SOB_MIN_WPROT_0,
+	mmDMA_IF_E_N_DMA0_MIN_WPROT_0,
+	mmDMA_IF_E_N_DMA1_MIN_WPROT_0,
+	mmSIF_RTR_0_LBW_RANGE_PROT_MIN_AW_0,
+	mmSIF_RTR_1_LBW_RANGE_PROT_MIN_AW_0,
+	mmSIF_RTR_2_LBW_RANGE_PROT_MIN_AW_0,
+	mmSIF_RTR_3_LBW_RANGE_PROT_MIN_AW_0,
+	mmSIF_RTR_4_LBW_RANGE_PROT_MIN_AW_0,
+	mmSIF_RTR_5_LBW_RANGE_PROT_MIN_AW_0,
+	mmSIF_RTR_6_LBW_RANGE_PROT_MIN_AW_0,
+	mmSIF_RTR_7_LBW_RANGE_PROT_MIN_AW_0,
+	mmNIF_RTR_0_LBW_RANGE_PROT_MIN_AW_0,
+	mmNIF_RTR_1_LBW_RANGE_PROT_MIN_AW_0,
+	mmNIF_RTR_2_LBW_RANGE_PROT_MIN_AW_0,
+	mmNIF_RTR_3_LBW_RANGE_PROT_MIN_AW_0,
+	mmNIF_RTR_4_LBW_RANGE_PROT_MIN_AW_0,
+	mmNIF_RTR_5_LBW_RANGE_PROT_MIN_AW_0,
+	mmNIF_RTR_6_LBW_RANGE_PROT_MIN_AW_0,
+	mmNIF_RTR_7_LBW_RANGE_PROT_MIN_AW_0,
+};
+
+static u64 gaudi_rr_lbw_max_aw_regs[GAUDI_NUMBER_OF_LBW_RR_REGS] = {
+	mmDMA_IF_W_S_SOB_MAX_WPROT_0,
+	mmDMA_IF_W_S_DMA0_MAX_WPROT_0,
+	mmDMA_IF_W_S_DMA1_MAX_WPROT_0,
+	mmDMA_IF_E_S_SOB_MAX_WPROT_0,
+	mmDMA_IF_E_S_DMA0_MAX_WPROT_0,
+	mmDMA_IF_E_S_DMA1_MAX_WPROT_0,
+	mmDMA_IF_W_N_SOB_MAX_WPROT_0,
+	mmDMA_IF_W_N_DMA0_MAX_WPROT_0,
+	mmDMA_IF_W_N_DMA1_MAX_WPROT_0,
+	mmDMA_IF_E_N_SOB_MAX_WPROT_0,
+	mmDMA_IF_E_N_DMA0_MAX_WPROT_0,
+	mmDMA_IF_E_N_DMA1_MAX_WPROT_0,
+	mmSIF_RTR_0_LBW_RANGE_PROT_MAX_AW_0,
+	mmSIF_RTR_1_LBW_RANGE_PROT_MAX_AW_0,
+	mmSIF_RTR_2_LBW_RANGE_PROT_MAX_AW_0,
+	mmSIF_RTR_3_LBW_RANGE_PROT_MAX_AW_0,
+	mmSIF_RTR_4_LBW_RANGE_PROT_MAX_AW_0,
+	mmSIF_RTR_5_LBW_RANGE_PROT_MAX_AW_0,
+	mmSIF_RTR_6_LBW_RANGE_PROT_MAX_AW_0,
+	mmSIF_RTR_7_LBW_RANGE_PROT_MAX_AW_0,
+	mmNIF_RTR_0_LBW_RANGE_PROT_MAX_AW_0,
+	mmNIF_RTR_1_LBW_RANGE_PROT_MAX_AW_0,
+	mmNIF_RTR_2_LBW_RANGE_PROT_MAX_AW_0,
+	mmNIF_RTR_3_LBW_RANGE_PROT_MAX_AW_0,
+	mmNIF_RTR_4_LBW_RANGE_PROT_MAX_AW_0,
+	mmNIF_RTR_5_LBW_RANGE_PROT_MAX_AW_0,
+	mmNIF_RTR_6_LBW_RANGE_PROT_MAX_AW_0,
+	mmNIF_RTR_7_LBW_RANGE_PROT_MAX_AW_0,
+};
+
+static u64 gaudi_rr_lbw_min_ar_regs[GAUDI_NUMBER_OF_LBW_RR_REGS] = {
+	mmDMA_IF_W_S_SOB_MIN_RPROT_0,
+	mmDMA_IF_W_S_DMA0_MIN_RPROT_0,
+	mmDMA_IF_W_S_DMA1_MIN_RPROT_0,
+	mmDMA_IF_E_S_SOB_MIN_RPROT_0,
+	mmDMA_IF_E_S_DMA0_MIN_RPROT_0,
+	mmDMA_IF_E_S_DMA1_MIN_RPROT_0,
+	mmDMA_IF_W_N_SOB_MIN_RPROT_0,
+	mmDMA_IF_W_N_DMA0_MIN_RPROT_0,
+	mmDMA_IF_W_N_DMA1_MIN_RPROT_0,
+	mmDMA_IF_E_N_SOB_MIN_RPROT_0,
+	mmDMA_IF_E_N_DMA0_MIN_RPROT_0,
+	mmDMA_IF_E_N_DMA1_MIN_RPROT_0,
+	mmSIF_RTR_0_LBW_RANGE_PROT_MIN_AR_0,
+	mmSIF_RTR_1_LBW_RANGE_PROT_MIN_AR_0,
+	mmSIF_RTR_2_LBW_RANGE_PROT_MIN_AR_0,
+	mmSIF_RTR_3_LBW_RANGE_PROT_MIN_AR_0,
+	mmSIF_RTR_4_LBW_RANGE_PROT_MIN_AR_0,
+	mmSIF_RTR_5_LBW_RANGE_PROT_MIN_AR_0,
+	mmSIF_RTR_6_LBW_RANGE_PROT_MIN_AR_0,
+	mmSIF_RTR_7_LBW_RANGE_PROT_MIN_AR_0,
+	mmNIF_RTR_0_LBW_RANGE_PROT_MIN_AR_0,
+	mmNIF_RTR_1_LBW_RANGE_PROT_MIN_AR_0,
+	mmNIF_RTR_2_LBW_RANGE_PROT_MIN_AR_0,
+	mmNIF_RTR_3_LBW_RANGE_PROT_MIN_AR_0,
+	mmNIF_RTR_4_LBW_RANGE_PROT_MIN_AR_0,
+	mmNIF_RTR_5_LBW_RANGE_PROT_MIN_AR_0,
+	mmNIF_RTR_6_LBW_RANGE_PROT_MIN_AR_0,
+	mmNIF_RTR_7_LBW_RANGE_PROT_MIN_AR_0,
+};
+
+static u64 gaudi_rr_lbw_max_ar_regs[GAUDI_NUMBER_OF_LBW_RR_REGS] = {
+	mmDMA_IF_W_S_SOB_MAX_RPROT_0,
+	mmDMA_IF_W_S_DMA0_MAX_RPROT_0,
+	mmDMA_IF_W_S_DMA1_MAX_RPROT_0,
+	mmDMA_IF_E_S_SOB_MAX_RPROT_0,
+	mmDMA_IF_E_S_DMA0_MAX_RPROT_0,
+	mmDMA_IF_E_S_DMA1_MAX_RPROT_0,
+	mmDMA_IF_W_N_SOB_MAX_RPROT_0,
+	mmDMA_IF_W_N_DMA0_MAX_RPROT_0,
+	mmDMA_IF_W_N_DMA1_MAX_RPROT_0,
+	mmDMA_IF_E_N_SOB_MAX_RPROT_0,
+	mmDMA_IF_E_N_DMA0_MAX_RPROT_0,
+	mmDMA_IF_E_N_DMA1_MAX_RPROT_0,
+	mmSIF_RTR_0_LBW_RANGE_PROT_MAX_AR_0,
+	mmSIF_RTR_1_LBW_RANGE_PROT_MAX_AR_0,
+	mmSIF_RTR_2_LBW_RANGE_PROT_MAX_AR_0,
+	mmSIF_RTR_3_LBW_RANGE_PROT_MAX_AR_0,
+	mmSIF_RTR_4_LBW_RANGE_PROT_MAX_AR_0,
+	mmSIF_RTR_5_LBW_RANGE_PROT_MAX_AR_0,
+	mmSIF_RTR_6_LBW_RANGE_PROT_MAX_AR_0,
+	mmSIF_RTR_7_LBW_RANGE_PROT_MAX_AR_0,
+	mmNIF_RTR_0_LBW_RANGE_PROT_MAX_AR_0,
+	mmNIF_RTR_1_LBW_RANGE_PROT_MAX_AR_0,
+	mmNIF_RTR_2_LBW_RANGE_PROT_MAX_AR_0,
+	mmNIF_RTR_3_LBW_RANGE_PROT_MAX_AR_0,
+	mmNIF_RTR_4_LBW_RANGE_PROT_MAX_AR_0,
+	mmNIF_RTR_5_LBW_RANGE_PROT_MAX_AR_0,
+	mmNIF_RTR_6_LBW_RANGE_PROT_MAX_AR_0,
+	mmNIF_RTR_7_LBW_RANGE_PROT_MAX_AR_0,
+};
+
+static u64 gaudi_rr_hbw_hit_aw_regs[GAUDI_NUMBER_OF_HBW_RR_REGS] = {
+	mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_HIT_AW,
+	mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_HIT_AW,
+	mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_HIT_AW,
+	mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_HIT_AW,
+	mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_HIT_AW,
+	mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_HIT_AW,
+	mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_HIT_AW,
+	mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_HIT_AW,
+	mmSIF_RTR_CTRL_0_RANGE_SEC_HIT_AW,
+	mmSIF_RTR_CTRL_1_RANGE_SEC_HIT_AW,
+	mmSIF_RTR_CTRL_2_RANGE_SEC_HIT_AW,
+	mmSIF_RTR_CTRL_3_RANGE_SEC_HIT_AW,
+	mmSIF_RTR_CTRL_4_RANGE_SEC_HIT_AW,
+	mmSIF_RTR_CTRL_5_RANGE_SEC_HIT_AW,
+	mmSIF_RTR_CTRL_6_RANGE_SEC_HIT_AW,
+	mmSIF_RTR_CTRL_7_RANGE_SEC_HIT_AW,
+	mmNIF_RTR_CTRL_0_RANGE_SEC_HIT_AW,
+	mmNIF_RTR_CTRL_1_RANGE_SEC_HIT_AW,
+	mmNIF_RTR_CTRL_2_RANGE_SEC_HIT_AW,
+	mmNIF_RTR_CTRL_3_RANGE_SEC_HIT_AW,
+	mmNIF_RTR_CTRL_4_RANGE_SEC_HIT_AW,
+	mmNIF_RTR_CTRL_5_RANGE_SEC_HIT_AW,
+	mmNIF_RTR_CTRL_6_RANGE_SEC_HIT_AW,
+	mmNIF_RTR_CTRL_7_RANGE_SEC_HIT_AW
+};
+
+static u64 gaudi_rr_hbw_hit_ar_regs[GAUDI_NUMBER_OF_HBW_RR_REGS] = {
+	mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_HIT_AR,
+	mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_HIT_AR,
+	mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_HIT_AR,
+	mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_HIT_AR,
+	mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_HIT_AR,
+	mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_HIT_AR,
+	mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_HIT_AR,
+	mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_HIT_AR,
+	mmSIF_RTR_CTRL_0_RANGE_SEC_HIT_AR,
+	mmSIF_RTR_CTRL_1_RANGE_SEC_HIT_AR,
+	mmSIF_RTR_CTRL_2_RANGE_SEC_HIT_AR,
+	mmSIF_RTR_CTRL_3_RANGE_SEC_HIT_AR,
+	mmSIF_RTR_CTRL_4_RANGE_SEC_HIT_AR,
+	mmSIF_RTR_CTRL_5_RANGE_SEC_HIT_AR,
+	mmSIF_RTR_CTRL_6_RANGE_SEC_HIT_AR,
+	mmSIF_RTR_CTRL_7_RANGE_SEC_HIT_AR,
+	mmNIF_RTR_CTRL_0_RANGE_SEC_HIT_AR,
+	mmNIF_RTR_CTRL_1_RANGE_SEC_HIT_AR,
+	mmNIF_RTR_CTRL_2_RANGE_SEC_HIT_AR,
+	mmNIF_RTR_CTRL_3_RANGE_SEC_HIT_AR,
+	mmNIF_RTR_CTRL_4_RANGE_SEC_HIT_AR,
+	mmNIF_RTR_CTRL_5_RANGE_SEC_HIT_AR,
+	mmNIF_RTR_CTRL_6_RANGE_SEC_HIT_AR,
+	mmNIF_RTR_CTRL_7_RANGE_SEC_HIT_AR
+};
+
+static u64 gaudi_rr_hbw_base_low_aw_regs[GAUDI_NUMBER_OF_HBW_RR_REGS] = {
+	mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_0,
+	mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0,
+	mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_0,
+	mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0,
+	mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_0,
+	mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0,
+	mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_0,
+	mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0,
+	mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_0,
+	mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_0,
+	mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_0,
+	mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_0,
+	mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_0,
+	mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_0,
+	mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_0,
+	mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_0,
+	mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_0,
+	mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_0,
+	mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_0,
+	mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_0,
+	mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_0,
+	mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_0,
+	mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_0,
+	mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_0
+};
+
+static u64 gaudi_rr_hbw_base_high_aw_regs[GAUDI_NUMBER_OF_HBW_RR_REGS] = {
+	mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_0,
+	mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0,
+	mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_0,
+	mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0,
+	mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_0,
+	mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0,
+	mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_0,
+	mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0,
+	mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_0,
+	mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_0,
+	mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_0,
+	mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_0,
+	mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_0,
+	mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_0,
+	mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_0,
+	mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_0,
+	mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_0,
+	mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_0,
+	mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_0,
+	mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_0,
+	mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_0,
+	mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_0,
+	mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_0,
+	mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_0
+};
+
+static u64 gaudi_rr_hbw_mask_low_aw_regs[GAUDI_NUMBER_OF_HBW_RR_REGS] = {
+	mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_0,
+	mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0,
+	mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_0,
+	mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0,
+	mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_0,
+	mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0,
+	mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_0,
+	mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0,
+	mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_0,
+	mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_0,
+	mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_0,
+	mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_0,
+	mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_0,
+	mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_0,
+	mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_0,
+	mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_0,
+	mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_0,
+	mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_0,
+	mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_0,
+	mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_0,
+	mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_0,
+	mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_0,
+	mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_0,
+	mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_0
+};
+
+static u64 gaudi_rr_hbw_mask_high_aw_regs[GAUDI_NUMBER_OF_HBW_RR_REGS] = {
+	mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_0,
+	mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0,
+	mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_0,
+	mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0,
+	mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_0,
+	mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0,
+	mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_0,
+	mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0,
+	mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_0,
+	mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_0,
+	mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_0,
+	mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_0,
+	mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_0,
+	mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_0,
+	mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_0,
+	mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_0,
+	mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_0,
+	mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_0,
+	mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_0,
+	mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_0,
+	mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_0,
+	mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_0,
+	mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_0,
+	mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_0
+};
+
+static u64 gaudi_rr_hbw_base_low_ar_regs[GAUDI_NUMBER_OF_HBW_RR_REGS] = {
+	mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_0,
+	mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0,
+	mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_0,
+	mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0,
+	mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_0,
+	mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0,
+	mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_0,
+	mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0,
+	mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_0,
+	mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_0,
+	mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_0,
+	mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_0,
+	mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_0,
+	mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_0,
+	mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_0,
+	mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_0,
+	mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_0,
+	mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_0,
+	mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_0,
+	mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_0,
+	mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_0,
+	mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_0,
+	mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_0,
+	mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_0
+};
+
+static u64 gaudi_rr_hbw_base_high_ar_regs[GAUDI_NUMBER_OF_HBW_RR_REGS] = {
+	mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_0,
+	mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0,
+	mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_0,
+	mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0,
+	mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_0,
+	mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0,
+	mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_0,
+	mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0,
+	mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_0,
+	mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_0,
+	mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_0,
+	mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_0,
+	mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_0,
+	mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_0,
+	mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_0,
+	mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_0,
+	mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_0,
+	mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_0,
+	mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_0,
+	mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_0,
+	mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_0,
+	mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_0,
+	mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_0,
+	mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_0
+};
+
+static u64 gaudi_rr_hbw_mask_low_ar_regs[GAUDI_NUMBER_OF_HBW_RR_REGS] = {
+	mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_0,
+	mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0,
+	mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_0,
+	mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0,
+	mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_0,
+	mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0,
+	mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_0,
+	mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0,
+	mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_0,
+	mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_0,
+	mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_0,
+	mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_0,
+	mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_0,
+	mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_0,
+	mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_0,
+	mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_0,
+	mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_0,
+	mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_0,
+	mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_0,
+	mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_0,
+	mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_0,
+	mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_0,
+	mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_0,
+	mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_0
+};
+
+static u64 gaudi_rr_hbw_mask_high_ar_regs[GAUDI_NUMBER_OF_HBW_RR_REGS] = {
+	mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_0,
+	mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0,
+	mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_0,
+	mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0,
+	mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_0,
+	mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0,
+	mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_0,
+	mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0,
+	mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_0,
+	mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_0,
+	mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_0,
+	mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_0,
+	mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_0,
+	mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_0,
+	mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_0,
+	mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_0,
+	mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_0,
+	mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_0,
+	mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_0,
+	mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_0,
+	mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_0,
+	mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_0,
+	mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_0,
+	mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_0
+};
+
+/**
+ * gaudi_pb_set_block - set the given block as protected
+ *
+ * @hdev: pointer to hl_device structure
+ * @base: block base address
+ */
+static void gaudi_pb_set_block(struct hl_device *hdev, u64 base)
+{
+	u32 pb_addr = base - CFG_BASE + PROT_BITS_OFFS;
+
+	while (pb_addr & 0xFFF) {
+		WREG32(pb_addr, 0);
+		pb_addr += 4;
+	}
+}
+
+static void gaudi_init_mme_protection_bits(struct hl_device *hdev)
+{
+	u32 pb_addr, mask;
+	u8 word_offset;
+
+	gaudi_pb_set_block(hdev, mmMME0_ACC_BASE);
+	gaudi_pb_set_block(hdev, mmMME0_SBAB_BASE);
+	gaudi_pb_set_block(hdev, mmMME0_PRTN_BASE);
+	gaudi_pb_set_block(hdev, mmMME1_ACC_BASE);
+	gaudi_pb_set_block(hdev, mmMME1_SBAB_BASE);
+	gaudi_pb_set_block(hdev, mmMME1_PRTN_BASE);
+	gaudi_pb_set_block(hdev, mmMME2_ACC_BASE);
+	gaudi_pb_set_block(hdev, mmMME2_SBAB_BASE);
+	gaudi_pb_set_block(hdev, mmMME2_PRTN_BASE);
+	gaudi_pb_set_block(hdev, mmMME3_ACC_BASE);
+	gaudi_pb_set_block(hdev, mmMME3_SBAB_BASE);
+	gaudi_pb_set_block(hdev, mmMME3_PRTN_BASE);
+
+	WREG32(mmMME0_CTRL_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+	WREG32(mmMME1_CTRL_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+	WREG32(mmMME2_CTRL_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+	WREG32(mmMME3_CTRL_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+
+	WREG32(mmMME0_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+	WREG32(mmMME2_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+
+	pb_addr = (mmMME0_CTRL_RESET & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmMME0_CTRL_RESET & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmMME0_CTRL_RESET & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_CTRL_QM_STALL & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_CTRL_SYNC_OBJECT_FIFO_TH & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_CTRL_EUS_ROLLUP_CNT_ADD & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_CTRL_INTR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_CTRL_INTR_MASK & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_CTRL_LOG_SHADOW & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_CTRL_PCU_RL_DESC0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_CTRL_PCU_RL_TOKEN_UPDATE & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_CTRL_PCU_RL_TH & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_CTRL_PCU_RL_MIN & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_CTRL_PCU_RL_CTRL_EN & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_CTRL_PCU_RL_HISTORY_LOG_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_CTRL_PCU_DUMMY_A_BF16 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_CTRL_PCU_DUMMY_B_BF16 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_CTRL_PCU_DUMMY_A_FP32_ODD & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_CTRL_PCU_DUMMY_A_FP32_EVEN & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_CTRL_PCU_DUMMY_B_FP32_ODD & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_CTRL_PCU_DUMMY_B_FP32_EVEN & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_CTRL_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_CTRL_EU_POWER_SAVE_DISABLE & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_CTRL_CS_DBG_BLOCK_ID & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_CTRL_CS_DBG_STATUS_DROP_CNT & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_CTRL_TE_CLOSE_CGATE & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_CTRL_AGU_SM_INFLIGHT_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_CTRL_AGU_SM_TOTAL_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_CTRL_EZSYNC_OUT_CREDIT & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_CTRL_PCU_RL_SAT_SEC & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_CTRL_AGU_SYNC_MSG_AXI_USER & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_CTRL_QM_SLV_LBW_CLK_EN & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmMME0_CTRL_SHADOW_0_STATUS & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmMME0_CTRL_SHADOW_0_STATUS & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmMME0_CTRL_SHADOW_0_STATUS & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmMME0_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmMME0_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmMME0_QM_GLBL_CFG0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_GLBL_CFG1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_GLBL_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_GLBL_ERR_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_GLBL_STS0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_GLBL_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_GLBL_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_GLBL_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_GLBL_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_GLBL_STS1_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_GLBL_MSG_EN_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_GLBL_MSG_EN_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_GLBL_MSG_EN_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_GLBL_MSG_EN_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_GLBL_MSG_EN_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_PQ_BASE_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_PQ_BASE_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_PQ_BASE_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_PQ_BASE_LO_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmMME0_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmMME0_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmMME0_QM_PQ_BASE_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_PQ_BASE_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_PQ_BASE_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_PQ_BASE_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_PQ_SIZE_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_PQ_SIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_PQ_SIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_PQ_SIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_PQ_PI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_PQ_PI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_PQ_PI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_PQ_PI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_PQ_CI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_PQ_CI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_PQ_CI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_PQ_CI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_PQ_CFG0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_PQ_CFG0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_PQ_CFG0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_PQ_CFG0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_PQ_CFG1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_PQ_CFG1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_PQ_CFG1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_PQ_CFG1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_PQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_PQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_PQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_PQ_STS0_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmMME0_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmMME0_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmMME0_QM_PQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_PQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_PQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_PQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_STS0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_PTR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_PTR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_TSIZE_0 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmMME0_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmMME0_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmMME0_QM_CQ_CTL_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_PTR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_PTR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_TSIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_CTL_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_PTR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_PTR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_TSIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_CTL_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_PTR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_PTR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_TSIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_CTL_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmMME0_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmMME0_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmMME0_QM_CQ_CTL_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_CTL_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_CTL_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_CTL_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_CTL_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmMME0_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmMME0_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmMME0_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) +
+			PROT_BITS_OFFS;
+	word_offset = ((mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmMME0_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmMME0_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmMME0_QM_CP_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmMME0_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmMME0_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmMME0_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_DBG_0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_DBG_0_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmMME0_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmMME0_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmMME0_QM_CP_DBG_0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_DBG_0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_DBG_0_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmMME0_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmMME0_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmMME0_QM_ARB_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmMME0_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmMME0_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2);
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) +
+			PROT_BITS_OFFS;
+	word_offset = ((mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_23 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmMME0_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmMME0_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmMME0_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmMME0_QM_ARB_STATE_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MSG_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_ERR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_ERR_MSG_EN & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_ERR_STS_DRP & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmMME0_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmMME0_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmMME0_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CGM_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CGM_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CGM_CFG1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmMME0_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmMME0_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmMME0_QM_LOCAL_RANGE_BASE & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_GLBL_AXCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_IND_GW_APB_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_IND_GW_APB_WDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_IND_GW_APB_RDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_IND_GW_APB_STATUS & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmMME0_QM_GLBL_ERR_WDATA & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmMME0_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmMME0_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmMME0_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmMME1_CTRL_RESET & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmMME1_CTRL_RESET & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmMME1_CTRL_RESET & 0x7F) >> 2);
+	mask |= 1U << ((mmMME1_CTRL_QM_STALL & 0x7F) >> 2);
+	mask |= 1U << ((mmMME1_CTRL_SYNC_OBJECT_FIFO_TH & 0x7F) >> 2);
+	mask |= 1U << ((mmMME1_CTRL_EUS_ROLLUP_CNT_ADD & 0x7F) >> 2);
+	mask |= 1U << ((mmMME1_CTRL_INTR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmMME1_CTRL_INTR_MASK & 0x7F) >> 2);
+	mask |= 1U << ((mmMME1_CTRL_LOG_SHADOW & 0x7F) >> 2);
+	mask |= 1U << ((mmMME1_CTRL_PCU_RL_DESC0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME1_CTRL_PCU_RL_TOKEN_UPDATE & 0x7F) >> 2);
+	mask |= 1U << ((mmMME1_CTRL_PCU_RL_TH & 0x7F) >> 2);
+	mask |= 1U << ((mmMME1_CTRL_PCU_RL_MIN & 0x7F) >> 2);
+	mask |= 1U << ((mmMME1_CTRL_PCU_RL_CTRL_EN & 0x7F) >> 2);
+	mask |= 1U << ((mmMME1_CTRL_PCU_RL_HISTORY_LOG_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmMME1_CTRL_PCU_DUMMY_A_BF16 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME1_CTRL_PCU_DUMMY_B_BF16 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME1_CTRL_PCU_DUMMY_A_FP32_ODD & 0x7F) >> 2);
+	mask |= 1U << ((mmMME1_CTRL_PCU_DUMMY_A_FP32_EVEN & 0x7F) >> 2);
+	mask |= 1U << ((mmMME1_CTRL_PCU_DUMMY_B_FP32_ODD & 0x7F) >> 2);
+	mask |= 1U << ((mmMME1_CTRL_PCU_DUMMY_B_FP32_EVEN & 0x7F) >> 2);
+	mask |= 1U << ((mmMME1_CTRL_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmMME1_CTRL_EU_POWER_SAVE_DISABLE & 0x7F) >> 2);
+	mask |= 1U << ((mmMME1_CTRL_CS_DBG_BLOCK_ID & 0x7F) >> 2);
+	mask |= 1U << ((mmMME1_CTRL_CS_DBG_STATUS_DROP_CNT & 0x7F) >> 2);
+	mask |= 1U << ((mmMME1_CTRL_TE_CLOSE_CGATE & 0x7F) >> 2);
+	mask |= 1U << ((mmMME1_CTRL_AGU_SM_INFLIGHT_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmMME1_CTRL_AGU_SM_TOTAL_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmMME1_CTRL_EZSYNC_OUT_CREDIT & 0x7F) >> 2);
+	mask |= 1U << ((mmMME1_CTRL_PCU_RL_SAT_SEC & 0x7F) >> 2);
+	mask |= 1U << ((mmMME1_CTRL_AGU_SYNC_MSG_AXI_USER & 0x7F) >> 2);
+	mask |= 1U << ((mmMME1_CTRL_QM_SLV_LBW_CLK_EN & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmMME1_CTRL_SHADOW_0_STATUS & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmMME1_CTRL_SHADOW_0_STATUS & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmMME1_CTRL_SHADOW_0_STATUS & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	/* MME 1 is slave, hence its whole QM block is protected (with RR) */
+
+	pb_addr = (mmMME2_CTRL_RESET & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmMME2_CTRL_RESET & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmMME2_CTRL_RESET & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_CTRL_QM_STALL & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_CTRL_SYNC_OBJECT_FIFO_TH & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_CTRL_EUS_ROLLUP_CNT_ADD & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_CTRL_INTR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_CTRL_INTR_MASK & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_CTRL_LOG_SHADOW & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_CTRL_PCU_RL_DESC0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_CTRL_PCU_RL_TOKEN_UPDATE & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_CTRL_PCU_RL_TH & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_CTRL_PCU_RL_MIN & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_CTRL_PCU_RL_CTRL_EN & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_CTRL_PCU_RL_HISTORY_LOG_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_CTRL_PCU_DUMMY_A_BF16 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_CTRL_PCU_DUMMY_B_BF16 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_CTRL_PCU_DUMMY_A_FP32_ODD & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_CTRL_PCU_DUMMY_A_FP32_EVEN & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_CTRL_PCU_DUMMY_B_FP32_ODD & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_CTRL_PCU_DUMMY_B_FP32_EVEN & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_CTRL_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_CTRL_EU_POWER_SAVE_DISABLE & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_CTRL_CS_DBG_BLOCK_ID & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_CTRL_CS_DBG_STATUS_DROP_CNT & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_CTRL_TE_CLOSE_CGATE & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_CTRL_AGU_SM_INFLIGHT_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_CTRL_AGU_SM_TOTAL_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_CTRL_EZSYNC_OUT_CREDIT & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_CTRL_PCU_RL_SAT_SEC & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_CTRL_AGU_SYNC_MSG_AXI_USER & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_CTRL_QM_SLV_LBW_CLK_EN & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmMME2_CTRL_SHADOW_0_STATUS & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmMME2_CTRL_SHADOW_0_STATUS & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmMME2_CTRL_SHADOW_0_STATUS & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmMME2_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmMME2_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmMME2_QM_GLBL_CFG0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_GLBL_CFG1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_GLBL_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_GLBL_ERR_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_GLBL_STS0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_GLBL_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_GLBL_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_GLBL_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_GLBL_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_GLBL_STS1_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_GLBL_MSG_EN_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_GLBL_MSG_EN_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_GLBL_MSG_EN_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_GLBL_MSG_EN_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_GLBL_MSG_EN_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_PQ_BASE_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_PQ_BASE_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_PQ_BASE_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_PQ_BASE_LO_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmMME2_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmMME2_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmMME2_QM_PQ_BASE_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_PQ_BASE_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_PQ_BASE_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_PQ_BASE_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_PQ_SIZE_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_PQ_SIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_PQ_SIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_PQ_SIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_PQ_PI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_PQ_PI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_PQ_PI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_PQ_PI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_PQ_CI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_PQ_CI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_PQ_CI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_PQ_CI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_PQ_CFG0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_PQ_CFG0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_PQ_CFG0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_PQ_CFG0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_PQ_CFG1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_PQ_CFG1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_PQ_CFG1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_PQ_CFG1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_PQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_PQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_PQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_PQ_STS0_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmMME2_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmMME2_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmMME2_QM_PQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_PQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_PQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_PQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_STS0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_PTR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_PTR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_TSIZE_0 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmMME2_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmMME2_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmMME2_QM_CQ_CTL_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_PTR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_PTR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_TSIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_CTL_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_PTR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_PTR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_TSIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_CTL_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_PTR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_PTR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_TSIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_CTL_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmMME2_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmMME2_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmMME2_QM_CQ_CTL_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_CTL_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_CTL_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_CTL_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_CTL_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmMME2_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmMME2_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmMME2_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) +
+			PROT_BITS_OFFS;
+	word_offset = ((mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS)
+			>> 7) << 2;
+	mask = 1U << ((mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmMME2_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmMME2_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmMME2_QM_CP_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmMME2_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmMME2_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmMME2_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_DBG_0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_DBG_0_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmMME2_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmMME2_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmMME2_QM_CP_DBG_0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_DBG_0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_DBG_0_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmMME2_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmMME2_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmMME2_QM_ARB_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmMME2_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmMME2_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) +
+			PROT_BITS_OFFS;
+	word_offset = ((mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_23 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmMME2_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmMME2_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmMME2_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmMME2_QM_ARB_STATE_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MSG_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_ERR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_ERR_MSG_EN & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_ERR_STS_DRP & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmMME2_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmMME2_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmMME2_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CGM_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CGM_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CGM_CFG1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmMME2_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmMME2_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmMME2_QM_LOCAL_RANGE_BASE & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_GLBL_AXCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_IND_GW_APB_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_IND_GW_APB_WDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_IND_GW_APB_RDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_IND_GW_APB_STATUS & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmMME2_QM_GLBL_ERR_WDATA & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmMME2_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmMME2_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmMME2_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmMME3_CTRL_RESET & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmMME3_CTRL_RESET & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmMME3_CTRL_RESET & 0x7F) >> 2);
+	mask |= 1U << ((mmMME3_CTRL_QM_STALL & 0x7F) >> 2);
+	mask |= 1U << ((mmMME3_CTRL_SYNC_OBJECT_FIFO_TH & 0x7F) >> 2);
+	mask |= 1U << ((mmMME3_CTRL_EUS_ROLLUP_CNT_ADD & 0x7F) >> 2);
+	mask |= 1U << ((mmMME3_CTRL_INTR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmMME3_CTRL_INTR_MASK & 0x7F) >> 2);
+	mask |= 1U << ((mmMME3_CTRL_LOG_SHADOW & 0x7F) >> 2);
+	mask |= 1U << ((mmMME3_CTRL_PCU_RL_DESC0 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME3_CTRL_PCU_RL_TOKEN_UPDATE & 0x7F) >> 2);
+	mask |= 1U << ((mmMME3_CTRL_PCU_RL_TH & 0x7F) >> 2);
+	mask |= 1U << ((mmMME3_CTRL_PCU_RL_MIN & 0x7F) >> 2);
+	mask |= 1U << ((mmMME3_CTRL_PCU_RL_CTRL_EN & 0x7F) >> 2);
+	mask |= 1U << ((mmMME3_CTRL_PCU_RL_HISTORY_LOG_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmMME3_CTRL_PCU_DUMMY_A_BF16 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME3_CTRL_PCU_DUMMY_B_BF16 & 0x7F) >> 2);
+	mask |= 1U << ((mmMME3_CTRL_PCU_DUMMY_A_FP32_ODD & 0x7F) >> 2);
+	mask |= 1U << ((mmMME3_CTRL_PCU_DUMMY_A_FP32_EVEN & 0x7F) >> 2);
+	mask |= 1U << ((mmMME3_CTRL_PCU_DUMMY_B_FP32_ODD & 0x7F) >> 2);
+	mask |= 1U << ((mmMME3_CTRL_PCU_DUMMY_B_FP32_EVEN & 0x7F) >> 2);
+	mask |= 1U << ((mmMME3_CTRL_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmMME3_CTRL_EU_POWER_SAVE_DISABLE & 0x7F) >> 2);
+	mask |= 1U << ((mmMME3_CTRL_CS_DBG_BLOCK_ID & 0x7F) >> 2);
+	mask |= 1U << ((mmMME3_CTRL_CS_DBG_STATUS_DROP_CNT & 0x7F) >> 2);
+	mask |= 1U << ((mmMME3_CTRL_TE_CLOSE_CGATE & 0x7F) >> 2);
+	mask |= 1U << ((mmMME3_CTRL_AGU_SM_INFLIGHT_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmMME3_CTRL_AGU_SM_TOTAL_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmMME3_CTRL_EZSYNC_OUT_CREDIT & 0x7F) >> 2);
+	mask |= 1U << ((mmMME3_CTRL_PCU_RL_SAT_SEC & 0x7F) >> 2);
+	mask |= 1U << ((mmMME3_CTRL_AGU_SYNC_MSG_AXI_USER & 0x7F) >> 2);
+	mask |= 1U << ((mmMME3_CTRL_QM_SLV_LBW_CLK_EN & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmMME3_CTRL_SHADOW_0_STATUS & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmMME3_CTRL_SHADOW_0_STATUS & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmMME3_CTRL_SHADOW_0_STATUS & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	/* MME 3 is slave, hence its whole QM block is protected (with RR) */
+}
+
+static void gaudi_init_dma_protection_bits(struct hl_device *hdev)
+{
+	u32 pb_addr, mask;
+	u8 word_offset;
+
+	if (!hdev->asic_prop.fw_security_enabled) {
+		gaudi_pb_set_block(hdev, mmDMA_IF_E_S_BASE);
+		gaudi_pb_set_block(hdev, mmDMA_IF_E_S_DOWN_CH0_BASE);
+		gaudi_pb_set_block(hdev, mmDMA_IF_E_S_DOWN_CH1_BASE);
+		gaudi_pb_set_block(hdev, mmDMA_E_PLL_BASE);
+		gaudi_pb_set_block(hdev, mmDMA_IF_E_S_DOWN_BASE);
+
+		gaudi_pb_set_block(hdev, mmDMA_IF_W_N_BASE);
+		gaudi_pb_set_block(hdev, mmDMA_IF_W_N_DOWN_CH0_BASE);
+		gaudi_pb_set_block(hdev, mmDMA_IF_W_N_DOWN_CH1_BASE);
+		gaudi_pb_set_block(hdev, mmDMA_IF_W_N_DOWN_BASE);
+
+		gaudi_pb_set_block(hdev, mmDMA_IF_E_N_BASE);
+		gaudi_pb_set_block(hdev, mmDMA_IF_E_N_DOWN_CH0_BASE);
+		gaudi_pb_set_block(hdev, mmDMA_IF_E_N_DOWN_CH1_BASE);
+		gaudi_pb_set_block(hdev, mmDMA_IF_E_N_DOWN_BASE);
+	}
+
+	WREG32(mmDMA0_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+	WREG32(mmDMA1_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+	WREG32(mmDMA2_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+	WREG32(mmDMA3_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+	WREG32(mmDMA4_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+	WREG32(mmDMA5_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+	WREG32(mmDMA6_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+	WREG32(mmDMA7_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+
+	WREG32(mmDMA0_CORE_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+	WREG32(mmDMA1_CORE_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+	WREG32(mmDMA2_CORE_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+	WREG32(mmDMA3_CORE_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+	WREG32(mmDMA4_CORE_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+	WREG32(mmDMA5_CORE_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+	WREG32(mmDMA6_CORE_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+	WREG32(mmDMA7_CORE_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+
+	pb_addr = (mmDMA0_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA0_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA0_QM_GLBL_CFG0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_GLBL_CFG1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_GLBL_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_GLBL_ERR_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_GLBL_STS0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_GLBL_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_GLBL_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_GLBL_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_GLBL_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_GLBL_STS1_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_GLBL_MSG_EN_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_GLBL_MSG_EN_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_GLBL_MSG_EN_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_GLBL_MSG_EN_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_GLBL_MSG_EN_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_PQ_BASE_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_PQ_BASE_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_PQ_BASE_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_PQ_BASE_LO_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA0_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA0_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA0_QM_PQ_BASE_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_PQ_BASE_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_PQ_BASE_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_PQ_BASE_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_PQ_SIZE_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_PQ_SIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_PQ_SIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_PQ_SIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_PQ_PI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_PQ_PI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_PQ_PI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_PQ_PI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_PQ_CI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_PQ_CI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_PQ_CI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_PQ_CI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_PQ_CFG0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_PQ_CFG0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_PQ_CFG0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_PQ_CFG0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_PQ_CFG1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_PQ_CFG1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_PQ_CFG1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_PQ_CFG1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_PQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_PQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_PQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_PQ_STS0_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA0_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA0_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA0_QM_PQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_PQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_PQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_PQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_STS0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_PTR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_PTR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_TSIZE_0 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA0_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA0_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA0_QM_CQ_CTL_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_PTR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_PTR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_TSIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_CTL_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_PTR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_PTR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_TSIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_CTL_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_PTR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_PTR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_TSIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_CTL_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA0_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA0_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA0_QM_CQ_CTL_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_CTL_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_CTL_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_CTL_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_CTL_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) +
+			PROT_BITS_OFFS;
+	word_offset =
+		((mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7)
+		<< 2;
+	mask = 1U << ((mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA0_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA0_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA0_QM_CP_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA0_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA0_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA0_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_DBG_0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_DBG_0_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA0_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA0_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA0_QM_CP_DBG_0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_DBG_0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_DBG_0_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA0_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA0_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA0_QM_ARB_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA0_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA0_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2);
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) +
+			PROT_BITS_OFFS;
+	word_offset =
+		((mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7)
+		<< 2;
+	mask = 1U << ((mmDMA0_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA0_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA0_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA0_QM_ARB_STATE_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MSG_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_ERR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_ERR_MSG_EN & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_ERR_STS_DRP & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA0_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA0_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CGM_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CGM_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CGM_CFG1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA0_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA0_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA0_QM_LOCAL_RANGE_BASE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_GLBL_AXCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_IND_GW_APB_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_IND_GW_APB_WDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_IND_GW_APB_RDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_IND_GW_APB_STATUS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_QM_GLBL_ERR_WDATA & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA0_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA0_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmDMA0_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA1_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA1_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA1_QM_GLBL_CFG0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_GLBL_CFG1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_GLBL_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_GLBL_ERR_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_GLBL_STS0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_GLBL_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_GLBL_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_GLBL_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_GLBL_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_GLBL_STS1_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_GLBL_MSG_EN_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_GLBL_MSG_EN_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_GLBL_MSG_EN_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_GLBL_MSG_EN_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_GLBL_MSG_EN_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_PQ_BASE_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_PQ_BASE_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_PQ_BASE_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_PQ_BASE_LO_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA1_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA1_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA1_QM_PQ_BASE_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_PQ_BASE_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_PQ_BASE_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_PQ_BASE_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_PQ_SIZE_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_PQ_SIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_PQ_SIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_PQ_SIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_PQ_PI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_PQ_PI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_PQ_PI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_PQ_PI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_PQ_CI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_PQ_CI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_PQ_CI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_PQ_CI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_PQ_CFG0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_PQ_CFG0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_PQ_CFG0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_PQ_CFG0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_PQ_CFG1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_PQ_CFG1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_PQ_CFG1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_PQ_CFG1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_PQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_PQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_PQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_PQ_STS0_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA1_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA1_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA1_QM_PQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_PQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_PQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_PQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_STS0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_PTR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_PTR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_TSIZE_0 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA1_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA1_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA1_QM_CQ_CTL_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_PTR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_PTR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_TSIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_CTL_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_PTR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_PTR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_TSIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_CTL_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_PTR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_PTR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_TSIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_CTL_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA1_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA1_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA1_QM_CQ_CTL_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_CTL_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_CTL_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_CTL_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_CTL_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) +
+			PROT_BITS_OFFS;
+	word_offset =
+		((mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7)
+		<< 2;
+	mask = 1U << ((mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA1_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA1_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA1_QM_CP_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA1_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA1_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA1_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_DBG_0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_DBG_0_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA1_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA1_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA1_QM_CP_DBG_0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_DBG_0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_DBG_0_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA1_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA1_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA1_QM_ARB_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA1_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA1_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) +
+			PROT_BITS_OFFS;
+	word_offset =
+		((mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7)
+		<< 2;
+	mask = 1U << ((mmDMA1_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA1_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA1_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA1_QM_ARB_STATE_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MSG_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_ERR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_ERR_MSG_EN & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_ERR_STS_DRP & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA1_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA1_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CGM_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CGM_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CGM_CFG1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA1_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA1_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA1_QM_LOCAL_RANGE_BASE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_GLBL_AXCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_IND_GW_APB_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_IND_GW_APB_WDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_IND_GW_APB_RDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_IND_GW_APB_STATUS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_QM_GLBL_ERR_WDATA & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA1_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA1_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmDMA1_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA2_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA2_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA2_QM_GLBL_CFG0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_GLBL_CFG1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_GLBL_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_GLBL_ERR_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_GLBL_STS0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_GLBL_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_GLBL_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_GLBL_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_GLBL_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_GLBL_STS1_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_GLBL_MSG_EN_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_GLBL_MSG_EN_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_GLBL_MSG_EN_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_GLBL_MSG_EN_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_GLBL_MSG_EN_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_PQ_BASE_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_PQ_BASE_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_PQ_BASE_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_PQ_BASE_LO_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA2_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA2_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA2_QM_PQ_BASE_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_PQ_BASE_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_PQ_BASE_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_PQ_BASE_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_PQ_SIZE_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_PQ_SIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_PQ_SIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_PQ_SIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_PQ_PI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_PQ_PI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_PQ_PI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_PQ_PI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_PQ_CI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_PQ_CI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_PQ_CI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_PQ_CI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_PQ_CFG0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_PQ_CFG0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_PQ_CFG0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_PQ_CFG0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_PQ_CFG1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_PQ_CFG1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_PQ_CFG1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_PQ_CFG1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_PQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_PQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_PQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_PQ_STS0_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA2_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA2_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA2_QM_PQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_PQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_PQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_PQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_STS0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_PTR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_PTR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_TSIZE_0 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA2_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA2_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA2_QM_CQ_CTL_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_PTR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_PTR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_TSIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_CTL_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_PTR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_PTR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_TSIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_CTL_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_PTR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_PTR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_TSIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_CTL_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA2_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA2_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA2_QM_CQ_CTL_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_CTL_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_CTL_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_CTL_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_CTL_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) +
+			PROT_BITS_OFFS;
+	word_offset =
+		((mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7)
+		<< 2;
+	mask = 1U << ((mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA2_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA2_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA2_QM_CP_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA2_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA2_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA2_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_DBG_0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_DBG_0_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA2_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA2_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA2_QM_CP_DBG_0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_DBG_0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_DBG_0_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA2_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA2_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA2_QM_ARB_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA2_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA2_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) +
+			PROT_BITS_OFFS;
+	word_offset =
+		((mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7)
+		<< 2;
+	mask = 1U << ((mmDMA2_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA2_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA2_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA2_QM_ARB_STATE_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MSG_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_ERR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_ERR_MSG_EN & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_ERR_STS_DRP & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA2_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA2_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CGM_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CGM_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CGM_CFG1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA2_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA2_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA2_QM_LOCAL_RANGE_BASE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_GLBL_AXCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_IND_GW_APB_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_IND_GW_APB_WDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_IND_GW_APB_RDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_IND_GW_APB_STATUS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_QM_GLBL_ERR_WDATA & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA2_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA2_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmDMA2_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA3_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA3_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA3_QM_GLBL_CFG0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_GLBL_CFG1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_GLBL_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_GLBL_ERR_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_GLBL_STS0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_GLBL_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_GLBL_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_GLBL_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_GLBL_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_GLBL_STS1_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_GLBL_MSG_EN_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_GLBL_MSG_EN_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_GLBL_MSG_EN_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_GLBL_MSG_EN_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_GLBL_MSG_EN_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_PQ_BASE_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_PQ_BASE_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_PQ_BASE_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_PQ_BASE_LO_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA3_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA3_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA3_QM_PQ_BASE_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_PQ_BASE_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_PQ_BASE_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_PQ_BASE_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_PQ_SIZE_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_PQ_SIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_PQ_SIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_PQ_SIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_PQ_PI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_PQ_PI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_PQ_PI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_PQ_PI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_PQ_CI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_PQ_CI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_PQ_CI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_PQ_CI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_PQ_CFG0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_PQ_CFG0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_PQ_CFG0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_PQ_CFG0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_PQ_CFG1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_PQ_CFG1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_PQ_CFG1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_PQ_CFG1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_PQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_PQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_PQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_PQ_STS0_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA3_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA3_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA3_QM_PQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_PQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_PQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_PQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_STS0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_PTR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_PTR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_TSIZE_0 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA3_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA3_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA3_QM_CQ_CTL_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_PTR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_PTR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_TSIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_CTL_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_PTR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_PTR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_TSIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_CTL_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_PTR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_PTR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_TSIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_CTL_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA3_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA3_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA3_QM_CQ_CTL_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_CTL_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_CTL_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_CTL_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_CTL_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) +
+			PROT_BITS_OFFS;
+	word_offset =
+		((mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7)
+		<< 2;
+	mask = 1U << ((mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA3_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA3_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA3_QM_CP_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA3_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA3_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA3_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_DBG_0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_DBG_0_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA3_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA3_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA3_QM_CP_DBG_0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_DBG_0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_DBG_0_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA3_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA3_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA3_QM_ARB_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA3_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA3_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) +
+			PROT_BITS_OFFS;
+	word_offset =
+		((mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7)
+		<< 2;
+	mask = 1U << ((mmDMA3_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA3_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA3_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA3_QM_ARB_STATE_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MSG_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_ERR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_ERR_MSG_EN & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_ERR_STS_DRP & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA3_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA3_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CGM_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CGM_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CGM_CFG1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA3_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA3_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA3_QM_LOCAL_RANGE_BASE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_GLBL_AXCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_IND_GW_APB_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_IND_GW_APB_WDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_IND_GW_APB_RDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_IND_GW_APB_STATUS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_QM_GLBL_ERR_WDATA & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA3_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA3_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmDMA3_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA4_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA4_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA4_QM_GLBL_CFG0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_GLBL_CFG1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_GLBL_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_GLBL_ERR_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_GLBL_STS0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_GLBL_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_GLBL_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_GLBL_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_GLBL_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_GLBL_STS1_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_GLBL_MSG_EN_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_GLBL_MSG_EN_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_GLBL_MSG_EN_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_GLBL_MSG_EN_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_GLBL_MSG_EN_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_PQ_BASE_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_PQ_BASE_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_PQ_BASE_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_PQ_BASE_LO_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA4_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA4_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA4_QM_PQ_BASE_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_PQ_BASE_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_PQ_BASE_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_PQ_BASE_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_PQ_SIZE_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_PQ_SIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_PQ_SIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_PQ_SIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_PQ_PI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_PQ_PI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_PQ_PI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_PQ_PI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_PQ_CI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_PQ_CI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_PQ_CI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_PQ_CI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_PQ_CFG0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_PQ_CFG0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_PQ_CFG0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_PQ_CFG0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_PQ_CFG1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_PQ_CFG1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_PQ_CFG1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_PQ_CFG1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_PQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_PQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_PQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_PQ_STS0_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA4_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA4_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA4_QM_PQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_PQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_PQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_PQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_STS0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_PTR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_PTR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_TSIZE_0 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA4_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA4_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA4_QM_CQ_CTL_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_PTR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_PTR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_TSIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_CTL_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_PTR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_PTR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_TSIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_CTL_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_PTR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_PTR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_TSIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_CTL_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA4_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA4_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA4_QM_CQ_CTL_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_CTL_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_CTL_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_CTL_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_CTL_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) +
+			PROT_BITS_OFFS;
+	word_offset =
+		((mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7)
+		<< 2;
+	mask = 1U << ((mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA4_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA4_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA4_QM_CP_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA4_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA4_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA4_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_DBG_0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_DBG_0_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA4_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA4_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA4_QM_CP_DBG_0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_DBG_0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_DBG_0_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA4_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA4_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA4_QM_ARB_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA4_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA4_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) +
+			PROT_BITS_OFFS;
+	word_offset =
+		((mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7)
+		<< 2;
+	mask = 1U << ((mmDMA4_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA4_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA4_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA4_QM_ARB_STATE_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MSG_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_ERR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_ERR_MSG_EN & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_ERR_STS_DRP & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA4_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA4_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CGM_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CGM_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CGM_CFG1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA4_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA4_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA4_QM_LOCAL_RANGE_BASE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_GLBL_AXCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_IND_GW_APB_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_IND_GW_APB_WDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_IND_GW_APB_RDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_IND_GW_APB_STATUS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_QM_GLBL_ERR_WDATA & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA4_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA4_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmDMA4_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA5_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA5_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA5_QM_GLBL_CFG0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_GLBL_CFG1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_GLBL_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_GLBL_ERR_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_GLBL_STS0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_GLBL_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_GLBL_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_GLBL_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_GLBL_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_GLBL_STS1_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_GLBL_MSG_EN_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_GLBL_MSG_EN_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_GLBL_MSG_EN_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_GLBL_MSG_EN_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_GLBL_MSG_EN_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_PQ_BASE_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_PQ_BASE_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_PQ_BASE_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_PQ_BASE_LO_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA5_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA5_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA5_QM_PQ_BASE_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_PQ_BASE_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_PQ_BASE_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_PQ_BASE_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_PQ_SIZE_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_PQ_SIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_PQ_SIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_PQ_SIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_PQ_PI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_PQ_PI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_PQ_PI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_PQ_PI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_PQ_CI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_PQ_CI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_PQ_CI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_PQ_CI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_PQ_CFG0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_PQ_CFG0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_PQ_CFG0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_PQ_CFG0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_PQ_CFG1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_PQ_CFG1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_PQ_CFG1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_PQ_CFG1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_PQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_PQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_PQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_PQ_STS0_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA5_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA5_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA5_QM_PQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_PQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_PQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_PQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_STS0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_PTR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_PTR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_TSIZE_0 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA5_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA5_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA5_QM_CQ_CTL_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_PTR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_PTR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_TSIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_CTL_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_PTR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_PTR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_TSIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_CTL_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_PTR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_PTR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_TSIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_CTL_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA5_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA5_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA5_QM_CQ_CTL_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_CTL_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_CTL_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_CTL_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_CTL_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) +
+			PROT_BITS_OFFS;
+	word_offset =
+		((mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7)
+		<< 2;
+	mask = 1U << ((mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA5_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA5_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA5_QM_CP_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA5_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA5_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA5_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_DBG_0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_DBG_0_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA5_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA5_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA5_QM_CP_DBG_0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_DBG_0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_DBG_0_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA5_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA5_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA5_QM_ARB_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA5_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA5_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) +
+			PROT_BITS_OFFS;
+	word_offset =
+		((mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7)
+		<< 2;
+	mask = 1U << ((mmDMA5_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA5_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA5_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA5_QM_ARB_STATE_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MSG_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_ERR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_ERR_MSG_EN & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_ERR_STS_DRP & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA5_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA5_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CGM_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CGM_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CGM_CFG1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA5_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA5_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA5_QM_LOCAL_RANGE_BASE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_GLBL_AXCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_IND_GW_APB_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_IND_GW_APB_WDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_IND_GW_APB_RDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_IND_GW_APB_STATUS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_QM_GLBL_ERR_WDATA & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA5_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA5_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmDMA5_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA6_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA6_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA6_QM_GLBL_CFG0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_GLBL_CFG1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_GLBL_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_GLBL_ERR_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_GLBL_STS0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_GLBL_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_GLBL_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_GLBL_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_GLBL_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_GLBL_STS1_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_GLBL_MSG_EN_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_GLBL_MSG_EN_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_GLBL_MSG_EN_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_GLBL_MSG_EN_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_GLBL_MSG_EN_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_PQ_BASE_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_PQ_BASE_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_PQ_BASE_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_PQ_BASE_LO_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA6_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA6_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA6_QM_PQ_BASE_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_PQ_BASE_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_PQ_BASE_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_PQ_BASE_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_PQ_SIZE_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_PQ_SIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_PQ_SIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_PQ_SIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_PQ_PI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_PQ_PI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_PQ_PI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_PQ_PI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_PQ_CI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_PQ_CI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_PQ_CI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_PQ_CI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_PQ_CFG0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_PQ_CFG0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_PQ_CFG0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_PQ_CFG0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_PQ_CFG1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_PQ_CFG1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_PQ_CFG1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_PQ_CFG1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_PQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_PQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_PQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_PQ_STS0_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA6_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA6_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA6_QM_PQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_PQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_PQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_PQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_STS0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_PTR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_PTR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_TSIZE_0 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA6_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA6_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA6_QM_CQ_CTL_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_PTR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_PTR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_TSIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_CTL_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_PTR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_PTR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_TSIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_CTL_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_PTR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_PTR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_TSIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_CTL_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA6_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA6_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA6_QM_CQ_CTL_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_CTL_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_CTL_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_CTL_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_CTL_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) +
+			PROT_BITS_OFFS;
+	word_offset =
+		((mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7)
+		<< 2;
+	mask = 1U << ((mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA6_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA6_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA6_QM_CP_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA6_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA6_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA6_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_DBG_0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_DBG_0_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA6_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA6_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA6_QM_CP_DBG_0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_DBG_0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_DBG_0_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA6_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA6_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA6_QM_ARB_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA6_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA6_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) +
+			PROT_BITS_OFFS;
+	word_offset =
+		((mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7)
+		<< 2;
+
+	mask = 1U << ((mmDMA6_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA6_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA6_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA6_QM_ARB_STATE_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MSG_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_ERR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_ERR_MSG_EN & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_ERR_STS_DRP & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA6_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA6_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CGM_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CGM_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CGM_CFG1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA6_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA6_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA6_QM_LOCAL_RANGE_BASE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_GLBL_AXCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_IND_GW_APB_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_IND_GW_APB_WDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_IND_GW_APB_RDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_IND_GW_APB_STATUS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_QM_GLBL_ERR_WDATA & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA6_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA6_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmDMA6_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA7_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA7_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA7_QM_GLBL_CFG0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_GLBL_CFG1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_GLBL_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_GLBL_ERR_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_GLBL_STS0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_GLBL_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_GLBL_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_GLBL_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_GLBL_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_GLBL_STS1_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_GLBL_MSG_EN_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_GLBL_MSG_EN_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_GLBL_MSG_EN_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_GLBL_MSG_EN_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_GLBL_MSG_EN_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_PQ_BASE_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_PQ_BASE_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_PQ_BASE_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_PQ_BASE_LO_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA7_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA7_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA7_QM_PQ_BASE_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_PQ_BASE_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_PQ_BASE_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_PQ_BASE_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_PQ_SIZE_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_PQ_SIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_PQ_SIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_PQ_SIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_PQ_PI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_PQ_PI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_PQ_PI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_PQ_PI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_PQ_CI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_PQ_CI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_PQ_CI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_PQ_CI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_PQ_CFG0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_PQ_CFG0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_PQ_CFG0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_PQ_CFG0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_PQ_CFG1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_PQ_CFG1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_PQ_CFG1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_PQ_CFG1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_PQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_PQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_PQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_PQ_STS0_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA7_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA7_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA7_QM_PQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_PQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_PQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_PQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_STS0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_PTR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_PTR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_TSIZE_0 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA7_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA7_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA7_QM_CQ_CTL_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_PTR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_PTR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_TSIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_CTL_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_PTR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_PTR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_TSIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_CTL_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_PTR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_PTR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_TSIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_CTL_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA7_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA7_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA7_QM_CQ_CTL_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_CTL_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_CTL_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_CTL_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_CTL_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) +
+			PROT_BITS_OFFS;
+	word_offset =
+		((mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7)
+		<< 2;
+	mask = 1U << ((mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA7_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA7_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA7_QM_CP_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA7_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA7_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA7_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_DBG_0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_DBG_0_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA7_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA7_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA7_QM_CP_DBG_0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_DBG_0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_DBG_0_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA7_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA7_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA7_QM_ARB_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA7_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA7_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) +
+			PROT_BITS_OFFS;
+	word_offset =
+		((mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7)
+		<< 2;
+	mask = 1U << ((mmDMA7_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA7_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA7_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA7_QM_ARB_STATE_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MSG_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_ERR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_ERR_MSG_EN & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_ERR_STS_DRP & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA7_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA7_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CGM_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CGM_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CGM_CFG1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA7_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA7_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA7_QM_LOCAL_RANGE_BASE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_GLBL_AXCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_IND_GW_APB_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_IND_GW_APB_WDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_IND_GW_APB_RDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_IND_GW_APB_STATUS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_QM_GLBL_ERR_WDATA & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA7_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA7_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmDMA7_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA0_CORE_CFG_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA0_CORE_CFG_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA0_CORE_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_CORE_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA0_CORE_PROT & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA0_CORE_PROT & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA0_CORE_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_CORE_SECURE_PROPS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_CORE_NON_SECURE_PROPS & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA0_CORE_RD_MAX_OUTSTAND & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA0_CORE_RD_MAX_OUTSTAND & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmDMA0_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_CORE_RD_MAX_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_CORE_RD_ARCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_CORE_RD_ARUSER_31_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_CORE_RD_INFLIGHTS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_CORE_WR_MAX_AWID & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_CORE_WR_AWCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_CORE_WR_AWUSER_31_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_CORE_WR_INFLIGHTS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_CORE_ERR_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_CORE_ERR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_CORE_ERRMSG_WDATA & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA0_CORE_STS0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA0_CORE_STS0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA0_CORE_STS0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_CORE_STS1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA0_CORE_RD_DBGMEM_ADD & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA0_CORE_RD_DBGMEM_ADD & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA0_CORE_RD_DBGMEM_ADD & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_CORE_RD_DBGMEM_RC & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_CORE_DBG_DESC_CNT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_CORE_DBG_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_CORE_DBG_RD_DESC_ID & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA0_CORE_DBG_WR_DESC_ID & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA1_CORE_CFG_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA1_CORE_CFG_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA1_CORE_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_CORE_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA1_CORE_PROT & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA1_CORE_PROT & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA1_CORE_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_CORE_SECURE_PROPS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_CORE_NON_SECURE_PROPS & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA1_CORE_RD_MAX_OUTSTAND & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA1_CORE_RD_MAX_OUTSTAND & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmDMA1_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_CORE_RD_MAX_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_CORE_RD_ARCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_CORE_RD_ARUSER_31_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_CORE_RD_INFLIGHTS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_CORE_WR_MAX_AWID & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_CORE_WR_AWCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_CORE_WR_AWUSER_31_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_CORE_WR_INFLIGHTS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_CORE_ERR_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_CORE_ERR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_CORE_ERRMSG_WDATA & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA1_CORE_STS0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA1_CORE_STS0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA1_CORE_STS0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_CORE_STS1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA1_CORE_RD_DBGMEM_ADD & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA1_CORE_RD_DBGMEM_ADD & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA1_CORE_RD_DBGMEM_ADD & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_CORE_RD_DBGMEM_RC & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_CORE_DBG_DESC_CNT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_CORE_DBG_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_CORE_DBG_RD_DESC_ID & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA1_CORE_DBG_WR_DESC_ID & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA2_CORE_CFG_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA2_CORE_CFG_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA2_CORE_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_CORE_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA2_CORE_PROT & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA2_CORE_PROT & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA2_CORE_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_CORE_SECURE_PROPS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_CORE_NON_SECURE_PROPS & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA2_CORE_RD_MAX_OUTSTAND & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA2_CORE_RD_MAX_OUTSTAND & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmDMA2_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_CORE_RD_MAX_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_CORE_RD_ARCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_CORE_RD_ARUSER_31_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_CORE_RD_INFLIGHTS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_CORE_WR_MAX_AWID & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_CORE_WR_AWCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_CORE_WR_INFLIGHTS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_CORE_ERR_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_CORE_ERR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_CORE_ERRMSG_WDATA & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA2_CORE_STS0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA2_CORE_STS0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA2_CORE_STS0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_CORE_STS1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA2_CORE_RD_DBGMEM_ADD & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA2_CORE_RD_DBGMEM_ADD & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA2_CORE_RD_DBGMEM_ADD & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_CORE_RD_DBGMEM_RC & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_CORE_DBG_DESC_CNT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_CORE_DBG_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_CORE_DBG_RD_DESC_ID & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA2_CORE_DBG_WR_DESC_ID & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA3_CORE_CFG_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA3_CORE_CFG_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA3_CORE_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_CORE_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA3_CORE_PROT & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA3_CORE_PROT & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA3_CORE_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_CORE_SECURE_PROPS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_CORE_NON_SECURE_PROPS & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA3_CORE_RD_MAX_OUTSTAND & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA3_CORE_RD_MAX_OUTSTAND & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmDMA3_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_CORE_RD_MAX_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_CORE_RD_ARCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_CORE_RD_ARUSER_31_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_CORE_RD_INFLIGHTS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_CORE_WR_MAX_AWID & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_CORE_WR_AWCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_CORE_WR_INFLIGHTS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_CORE_ERR_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_CORE_ERR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_CORE_ERRMSG_WDATA & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA3_CORE_STS0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA3_CORE_STS0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA3_CORE_STS0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_CORE_STS1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA3_CORE_RD_DBGMEM_ADD & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA3_CORE_RD_DBGMEM_ADD & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA3_CORE_RD_DBGMEM_ADD & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_CORE_RD_DBGMEM_RC & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_CORE_DBG_DESC_CNT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_CORE_DBG_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_CORE_DBG_RD_DESC_ID & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA3_CORE_DBG_WR_DESC_ID & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA4_CORE_CFG_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA4_CORE_CFG_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA4_CORE_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_CORE_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA4_CORE_PROT & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA4_CORE_PROT & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA4_CORE_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_CORE_SECURE_PROPS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_CORE_NON_SECURE_PROPS & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA4_CORE_RD_MAX_OUTSTAND & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA4_CORE_RD_MAX_OUTSTAND & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmDMA4_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_CORE_RD_MAX_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_CORE_RD_ARCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_CORE_RD_ARUSER_31_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_CORE_RD_INFLIGHTS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_CORE_WR_MAX_AWID & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_CORE_WR_AWCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_CORE_WR_INFLIGHTS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_CORE_ERR_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_CORE_ERR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_CORE_ERRMSG_WDATA & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA4_CORE_STS0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA4_CORE_STS0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA4_CORE_STS0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_CORE_STS1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA4_CORE_RD_DBGMEM_ADD & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA4_CORE_RD_DBGMEM_ADD & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA4_CORE_RD_DBGMEM_ADD & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_CORE_RD_DBGMEM_RC & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_CORE_DBG_DESC_CNT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_CORE_DBG_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_CORE_DBG_RD_DESC_ID & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA4_CORE_DBG_WR_DESC_ID & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA5_CORE_CFG_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA5_CORE_CFG_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA5_CORE_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_CORE_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA5_CORE_PROT & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA5_CORE_PROT & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA5_CORE_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_CORE_SECURE_PROPS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_CORE_NON_SECURE_PROPS & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA5_CORE_RD_MAX_OUTSTAND & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA5_CORE_RD_MAX_OUTSTAND & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmDMA5_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_CORE_RD_MAX_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_CORE_RD_ARCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_CORE_RD_ARUSER_31_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_CORE_RD_INFLIGHTS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_CORE_WR_MAX_AWID & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_CORE_WR_AWCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_CORE_WR_INFLIGHTS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_CORE_ERR_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_CORE_ERR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_CORE_ERRMSG_WDATA & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA5_CORE_STS0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA5_CORE_STS0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA5_CORE_STS0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_CORE_STS1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA5_CORE_RD_DBGMEM_ADD & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA5_CORE_RD_DBGMEM_ADD & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA5_CORE_RD_DBGMEM_ADD & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_CORE_RD_DBGMEM_RC & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_CORE_DBG_DESC_CNT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_CORE_DBG_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_CORE_DBG_RD_DESC_ID & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA5_CORE_DBG_WR_DESC_ID & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA6_CORE_CFG_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA6_CORE_CFG_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA6_CORE_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_CORE_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA6_CORE_PROT & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA6_CORE_PROT & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA6_CORE_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_CORE_SECURE_PROPS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_CORE_NON_SECURE_PROPS & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA6_CORE_RD_MAX_OUTSTAND & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA6_CORE_RD_MAX_OUTSTAND & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmDMA6_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_CORE_RD_MAX_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_CORE_RD_ARCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_CORE_RD_ARUSER_31_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_CORE_RD_INFLIGHTS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_CORE_WR_MAX_AWID & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_CORE_WR_AWCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_CORE_WR_INFLIGHTS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_CORE_ERR_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_CORE_ERR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_CORE_ERRMSG_WDATA & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA6_CORE_STS0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA6_CORE_STS0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA6_CORE_STS0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_CORE_STS1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA6_CORE_RD_DBGMEM_ADD & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA6_CORE_RD_DBGMEM_ADD & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA6_CORE_RD_DBGMEM_ADD & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_CORE_RD_DBGMEM_RC & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_CORE_DBG_DESC_CNT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_CORE_DBG_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_CORE_DBG_RD_DESC_ID & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA6_CORE_DBG_WR_DESC_ID & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA7_CORE_CFG_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA7_CORE_CFG_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA7_CORE_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_CORE_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA7_CORE_PROT & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA7_CORE_PROT & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA7_CORE_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_CORE_SECURE_PROPS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_CORE_NON_SECURE_PROPS & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA7_CORE_RD_MAX_OUTSTAND & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA7_CORE_RD_MAX_OUTSTAND & PROT_BITS_OFFS) >> 7)
+			<< 2;
+	mask = 1U << ((mmDMA7_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_CORE_RD_MAX_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_CORE_RD_ARCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_CORE_RD_ARUSER_31_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_CORE_RD_INFLIGHTS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_CORE_WR_MAX_AWID & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_CORE_WR_AWCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_CORE_WR_INFLIGHTS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_CORE_ERR_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_CORE_ERR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_CORE_ERRMSG_WDATA & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA7_CORE_STS0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA7_CORE_STS0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA7_CORE_STS0 & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_CORE_STS1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmDMA7_CORE_RD_DBGMEM_ADD & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmDMA7_CORE_RD_DBGMEM_ADD & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmDMA7_CORE_RD_DBGMEM_ADD & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_CORE_RD_DBGMEM_RC & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_CORE_DBG_DESC_CNT & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_CORE_DBG_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_CORE_DBG_RD_DESC_ID & 0x7F) >> 2);
+	mask |= 1U << ((mmDMA7_CORE_DBG_WR_DESC_ID & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+}
+
+static void gaudi_init_nic_protection_bits(struct hl_device *hdev)
+{
+	u32 pb_addr, mask;
+	u8 word_offset;
+
+	WREG32(mmNIC0_QM0_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+	WREG32(mmNIC0_QM1_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+
+	pb_addr = (mmNIC0_QM0_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC0_QM0_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC0_QM0_GLBL_CFG0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_GLBL_CFG1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_GLBL_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_GLBL_ERR_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_GLBL_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_GLBL_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_GLBL_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_GLBL_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_GLBL_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_GLBL_STS0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_GLBL_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_GLBL_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_GLBL_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_GLBL_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_GLBL_STS1_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_GLBL_MSG_EN_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_GLBL_MSG_EN_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_GLBL_MSG_EN_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_GLBL_MSG_EN_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_GLBL_MSG_EN_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_PQ_BASE_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_PQ_BASE_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_PQ_BASE_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_PQ_BASE_LO_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC0_QM0_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC0_QM0_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC0_QM0_PQ_BASE_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_PQ_BASE_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_PQ_BASE_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_PQ_BASE_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_PQ_SIZE_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_PQ_SIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_PQ_SIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_PQ_SIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_PQ_PI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_PQ_PI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_PQ_PI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_PQ_PI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_PQ_CI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_PQ_CI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_PQ_CI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_PQ_CI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_PQ_CFG0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_PQ_CFG0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_PQ_CFG0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_PQ_CFG0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_PQ_CFG1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_PQ_CFG1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_PQ_CFG1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_PQ_CFG1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_PQ_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_PQ_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_PQ_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_PQ_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_PQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_PQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_PQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_PQ_STS0_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC0_QM0_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC0_QM0_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC0_QM0_PQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_PQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_PQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_PQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_STS0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_PTR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_PTR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_TSIZE_0 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC0_QM0_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC0_QM0_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC0_QM0_CQ_CTL_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_PTR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_PTR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_TSIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_CTL_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_PTR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_PTR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_TSIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_CTL_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_PTR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_PTR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_TSIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_CTL_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_PTR_LO_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_PTR_LO_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_PTR_LO_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_PTR_LO_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_PTR_LO_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_PTR_HI_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_PTR_HI_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_PTR_HI_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_PTR_HI_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_PTR_HI_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_TSIZE_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_TSIZE_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_TSIZE_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_TSIZE_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_TSIZE_STS_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC0_QM0_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC0_QM0_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC0_QM0_CQ_CTL_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_CTL_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_CTL_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_CTL_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_CTL_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_IFIFO_CNT_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_IFIFO_CNT_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_IFIFO_CNT_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_IFIFO_CNT_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CQ_IFIFO_CNT_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_2 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) +
+				PROT_BITS_OFFS;
+	word_offset = ((mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC0_QM0_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC0_QM0_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC0_QM0_CP_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_CURRENT_INST_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_CURRENT_INST_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_CURRENT_INST_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_CURRENT_INST_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_CURRENT_INST_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_CURRENT_INST_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_CURRENT_INST_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_CURRENT_INST_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_CURRENT_INST_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_CURRENT_INST_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_BARRIER_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_BARRIER_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_BARRIER_CFG_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC0_QM0_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC0_QM0_CP_BARRIER_CFG_3 & PROT_BITS_OFFS)
+			>> 7) << 2;
+	mask = 1U << ((mmNIC0_QM0_CP_BARRIER_CFG_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_BARRIER_CFG_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_DBG_0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_DBG_0_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC0_QM0_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC0_QM0_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC0_QM0_CP_DBG_0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_DBG_0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_DBG_0_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_ARUSER_31_11_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_AWUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_AWUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_AWUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_AWUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CP_AWUSER_31_11_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC0_QM0_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC0_QM0_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC0_QM0_ARB_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC0_QM0_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_24 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) +
+			PROT_BITS_OFFS;
+	word_offset = ((mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_23 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC0_QM0_ARB_SLV_CHOISE_WDT & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC0_QM0_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC0_QM0_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC0_QM0_ARB_STATE_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MSG_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_ERR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_ERR_MSG_EN & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_ERR_STS_DRP & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_19 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC0_QM0_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC0_QM0_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS)
+			>> 7) << 2;
+	mask = 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_23 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_31 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CGM_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CGM_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CGM_CFG1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC0_QM0_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC0_QM0_LOCAL_RANGE_BASE & PROT_BITS_OFFS)
+			>> 7) << 2;
+	mask = 1U << ((mmNIC0_QM0_LOCAL_RANGE_BASE & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_LOCAL_RANGE_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_GLBL_AXCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_IND_GW_APB_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_IND_GW_APB_WDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_IND_GW_APB_RDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_IND_GW_APB_STATUS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM0_GLBL_ERR_WDATA & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC0_QM0_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC0_QM0_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS)
+			>> 7) << 2;
+	mask = 1U << ((mmNIC0_QM0_GLBL_MEM_INIT_BUSY & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC0_QM1_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC0_QM1_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC0_QM1_GLBL_CFG0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_GLBL_CFG1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_GLBL_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_GLBL_ERR_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_GLBL_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_GLBL_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_GLBL_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_GLBL_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_GLBL_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_GLBL_STS0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_GLBL_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_GLBL_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_GLBL_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_GLBL_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_GLBL_STS1_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_GLBL_MSG_EN_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_GLBL_MSG_EN_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_GLBL_MSG_EN_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_GLBL_MSG_EN_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_GLBL_MSG_EN_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_PQ_BASE_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_PQ_BASE_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_PQ_BASE_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_PQ_BASE_LO_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC0_QM1_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC0_QM1_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC0_QM1_PQ_BASE_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_PQ_BASE_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_PQ_BASE_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_PQ_BASE_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_PQ_SIZE_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_PQ_SIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_PQ_SIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_PQ_SIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_PQ_PI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_PQ_PI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_PQ_PI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_PQ_PI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_PQ_CI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_PQ_CI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_PQ_CI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_PQ_CI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_PQ_CFG0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_PQ_CFG0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_PQ_CFG0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_PQ_CFG0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_PQ_CFG1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_PQ_CFG1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_PQ_CFG1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_PQ_CFG1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_PQ_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_PQ_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_PQ_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_PQ_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_PQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_PQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_PQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_PQ_STS0_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC0_QM1_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC0_QM1_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC0_QM1_PQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_PQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_PQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_PQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_STS0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_PTR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_PTR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_TSIZE_0 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC0_QM1_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC0_QM1_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC0_QM1_CQ_CTL_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_PTR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_PTR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_TSIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_CTL_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_PTR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_PTR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_TSIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_CTL_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_PTR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_PTR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_TSIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_CTL_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_PTR_LO_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_PTR_LO_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_PTR_LO_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_PTR_LO_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_PTR_LO_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_PTR_HI_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_PTR_HI_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_PTR_HI_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_PTR_HI_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_PTR_HI_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_TSIZE_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_TSIZE_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_TSIZE_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_TSIZE_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_TSIZE_STS_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC0_QM1_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC0_QM1_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC0_QM1_CQ_CTL_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_CTL_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_CTL_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_CTL_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_CTL_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_IFIFO_CNT_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_IFIFO_CNT_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_IFIFO_CNT_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_IFIFO_CNT_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CQ_IFIFO_CNT_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC0_QM1_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC0_QM1_CP_MSG_BASE2_ADDR_LO_2 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC0_QM1_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC0_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) +
+			PROT_BITS_OFFS;
+	word_offset = ((mmNIC0_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC0_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC0_QM1_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC0_QM1_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC0_QM1_CP_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_CURRENT_INST_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_CURRENT_INST_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_CURRENT_INST_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_CURRENT_INST_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_CURRENT_INST_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_CURRENT_INST_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_CURRENT_INST_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_CURRENT_INST_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_CURRENT_INST_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_CURRENT_INST_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_BARRIER_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_BARRIER_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_BARRIER_CFG_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC0_QM1_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC0_QM1_CP_BARRIER_CFG_3 & PROT_BITS_OFFS)
+			>> 7) << 2;
+	mask = 1U << ((mmNIC0_QM1_CP_BARRIER_CFG_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_BARRIER_CFG_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_DBG_0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_DBG_0_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC0_QM1_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC0_QM1_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC0_QM1_CP_DBG_0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_DBG_0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_DBG_0_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_ARUSER_31_11_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_AWUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_AWUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_AWUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_AWUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CP_AWUSER_31_11_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC0_QM1_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC0_QM1_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC0_QM1_ARB_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC0_QM1_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_24 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) +
+			PROT_BITS_OFFS;
+	word_offset = ((mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_23 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC0_QM1_ARB_SLV_CHOISE_WDT & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC0_QM1_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC0_QM1_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC0_QM1_ARB_STATE_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MSG_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_ERR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_ERR_MSG_EN & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_ERR_STS_DRP & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_19 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC0_QM1_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC0_QM1_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS)
+			>> 7) << 2;
+	mask = 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_23 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_31 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CGM_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CGM_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CGM_CFG1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC0_QM1_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC0_QM1_LOCAL_RANGE_BASE & PROT_BITS_OFFS)
+			>> 7) << 2;
+	mask = 1U << ((mmNIC0_QM1_LOCAL_RANGE_BASE & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_LOCAL_RANGE_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_GLBL_AXCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_IND_GW_APB_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_IND_GW_APB_WDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_IND_GW_APB_RDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_IND_GW_APB_STATUS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC0_QM1_GLBL_ERR_WDATA & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC0_QM1_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC0_QM1_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS)
+			>> 7) << 2;
+	mask = 1U << ((mmNIC0_QM1_GLBL_MEM_INIT_BUSY & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	WREG32(mmNIC1_QM0_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+	WREG32(mmNIC1_QM1_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+
+	pb_addr = (mmNIC1_QM0_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC1_QM0_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC1_QM0_GLBL_CFG0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_GLBL_CFG1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_GLBL_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_GLBL_ERR_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_GLBL_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_GLBL_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_GLBL_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_GLBL_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_GLBL_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_GLBL_STS0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_GLBL_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_GLBL_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_GLBL_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_GLBL_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_GLBL_STS1_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_GLBL_MSG_EN_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_GLBL_MSG_EN_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_GLBL_MSG_EN_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_GLBL_MSG_EN_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_GLBL_MSG_EN_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_PQ_BASE_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_PQ_BASE_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_PQ_BASE_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_PQ_BASE_LO_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC1_QM0_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC1_QM0_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC1_QM0_PQ_BASE_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_PQ_BASE_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_PQ_BASE_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_PQ_BASE_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_PQ_SIZE_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_PQ_SIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_PQ_SIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_PQ_SIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_PQ_PI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_PQ_PI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_PQ_PI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_PQ_PI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_PQ_CI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_PQ_CI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_PQ_CI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_PQ_CI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_PQ_CFG0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_PQ_CFG0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_PQ_CFG0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_PQ_CFG0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_PQ_CFG1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_PQ_CFG1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_PQ_CFG1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_PQ_CFG1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_PQ_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_PQ_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_PQ_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_PQ_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_PQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_PQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_PQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_PQ_STS0_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC1_QM0_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC1_QM0_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC1_QM0_PQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_PQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_PQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_PQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_STS0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_PTR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_PTR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_TSIZE_0 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC1_QM0_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC1_QM0_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC1_QM0_CQ_CTL_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_PTR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_PTR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_TSIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_CTL_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_PTR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_PTR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_TSIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_CTL_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_PTR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_PTR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_TSIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_CTL_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_PTR_LO_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_PTR_LO_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_PTR_LO_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_PTR_LO_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_PTR_LO_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_PTR_HI_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_PTR_HI_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_PTR_HI_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_PTR_HI_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_PTR_HI_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_TSIZE_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_TSIZE_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_TSIZE_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_TSIZE_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_TSIZE_STS_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC1_QM0_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC1_QM0_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC1_QM0_CQ_CTL_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_CTL_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_CTL_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_CTL_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_CTL_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_IFIFO_CNT_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_IFIFO_CNT_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_IFIFO_CNT_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_IFIFO_CNT_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CQ_IFIFO_CNT_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC1_QM0_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC1_QM0_CP_MSG_BASE2_ADDR_LO_2 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC1_QM0_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC1_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) +
+			PROT_BITS_OFFS;
+	word_offset = ((mmNIC1_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC1_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC1_QM0_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC1_QM0_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC1_QM0_CP_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_CURRENT_INST_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_CURRENT_INST_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_CURRENT_INST_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_CURRENT_INST_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_CURRENT_INST_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_CURRENT_INST_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_CURRENT_INST_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_CURRENT_INST_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_CURRENT_INST_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_CURRENT_INST_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_BARRIER_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_BARRIER_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_BARRIER_CFG_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC1_QM0_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC1_QM0_CP_BARRIER_CFG_3 & PROT_BITS_OFFS)
+			>> 7) << 2;
+	mask = 1U << ((mmNIC1_QM0_CP_BARRIER_CFG_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_BARRIER_CFG_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_DBG_0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_DBG_0_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC1_QM0_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC1_QM0_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC1_QM0_CP_DBG_0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_DBG_0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_DBG_0_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_ARUSER_31_11_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_AWUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_AWUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_AWUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_AWUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CP_AWUSER_31_11_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC1_QM0_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC1_QM0_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC1_QM0_ARB_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC1_QM0_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_24 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) +
+			PROT_BITS_OFFS;
+	word_offset = ((mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_23 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC1_QM0_ARB_SLV_CHOISE_WDT & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2);
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC1_QM0_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC1_QM0_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC1_QM0_ARB_STATE_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MSG_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_ERR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_ERR_MSG_EN & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_ERR_STS_DRP & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_19 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC1_QM0_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC1_QM0_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS)
+			>> 7) << 2;
+	mask = 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_23 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_31 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CGM_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CGM_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CGM_CFG1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC1_QM0_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC1_QM0_LOCAL_RANGE_BASE & PROT_BITS_OFFS)
+			>> 7) << 2;
+	mask = 1U << ((mmNIC1_QM0_LOCAL_RANGE_BASE & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_LOCAL_RANGE_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_GLBL_AXCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_IND_GW_APB_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_IND_GW_APB_WDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_IND_GW_APB_RDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_IND_GW_APB_STATUS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM0_GLBL_ERR_WDATA & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC1_QM0_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC1_QM0_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS)
+			>> 7) << 2;
+	mask = 1U << ((mmNIC1_QM0_GLBL_MEM_INIT_BUSY & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC1_QM1_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC1_QM1_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC1_QM1_GLBL_CFG0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_GLBL_CFG1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_GLBL_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_GLBL_ERR_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_GLBL_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_GLBL_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_GLBL_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_GLBL_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_GLBL_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_GLBL_STS0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_GLBL_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_GLBL_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_GLBL_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_GLBL_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_GLBL_STS1_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_GLBL_MSG_EN_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_GLBL_MSG_EN_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_GLBL_MSG_EN_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_GLBL_MSG_EN_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_GLBL_MSG_EN_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_PQ_BASE_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_PQ_BASE_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_PQ_BASE_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_PQ_BASE_LO_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC1_QM1_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC1_QM1_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC1_QM1_PQ_BASE_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_PQ_BASE_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_PQ_BASE_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_PQ_BASE_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_PQ_SIZE_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_PQ_SIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_PQ_SIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_PQ_SIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_PQ_PI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_PQ_PI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_PQ_PI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_PQ_PI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_PQ_CI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_PQ_CI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_PQ_CI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_PQ_CI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_PQ_CFG0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_PQ_CFG0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_PQ_CFG0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_PQ_CFG0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_PQ_CFG1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_PQ_CFG1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_PQ_CFG1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_PQ_CFG1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_PQ_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_PQ_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_PQ_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_PQ_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_PQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_PQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_PQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_PQ_STS0_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC1_QM1_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC1_QM1_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC1_QM1_PQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_PQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_PQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_PQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_STS0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_PTR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_PTR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_TSIZE_0 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC1_QM1_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC1_QM1_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC1_QM1_CQ_CTL_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_PTR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_PTR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_TSIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_CTL_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_PTR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_PTR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_TSIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_CTL_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_PTR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_PTR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_TSIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_CTL_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_PTR_LO_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_PTR_LO_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_PTR_LO_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_PTR_LO_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_PTR_LO_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_PTR_HI_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_PTR_HI_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_PTR_HI_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_PTR_HI_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_PTR_HI_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_TSIZE_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_TSIZE_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_TSIZE_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_TSIZE_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_TSIZE_STS_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC1_QM1_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC1_QM1_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC1_QM1_CQ_CTL_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_CTL_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_CTL_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_CTL_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_CTL_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_IFIFO_CNT_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_IFIFO_CNT_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_IFIFO_CNT_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_IFIFO_CNT_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CQ_IFIFO_CNT_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC1_QM1_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC1_QM1_CP_MSG_BASE2_ADDR_LO_2 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC1_QM1_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC1_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) +
+			PROT_BITS_OFFS;
+	word_offset = ((mmNIC1_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC1_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC1_QM1_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC1_QM1_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC1_QM1_CP_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_CURRENT_INST_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_CURRENT_INST_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_CURRENT_INST_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_CURRENT_INST_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_CURRENT_INST_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_CURRENT_INST_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_CURRENT_INST_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_CURRENT_INST_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_CURRENT_INST_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_CURRENT_INST_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_BARRIER_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_BARRIER_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_BARRIER_CFG_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC1_QM1_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC1_QM1_CP_BARRIER_CFG_3 & PROT_BITS_OFFS)
+			>> 7) << 2;
+	mask = 1U << ((mmNIC1_QM1_CP_BARRIER_CFG_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_BARRIER_CFG_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_DBG_0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_DBG_0_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC1_QM1_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC1_QM1_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC1_QM1_CP_DBG_0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_DBG_0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_DBG_0_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_ARUSER_31_11_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_AWUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_AWUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_AWUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_AWUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CP_AWUSER_31_11_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC1_QM1_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC1_QM1_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC1_QM1_ARB_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC1_QM1_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_24 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) +
+			PROT_BITS_OFFS;
+	word_offset = ((mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_23 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC1_QM1_ARB_SLV_CHOISE_WDT & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC1_QM1_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC1_QM1_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC1_QM1_ARB_STATE_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MSG_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_ERR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_ERR_MSG_EN & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_ERR_STS_DRP & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_19 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC1_QM1_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC1_QM1_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS)
+			>> 7) << 2;
+	mask = 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_23 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_31 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CGM_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CGM_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CGM_CFG1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC1_QM1_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC1_QM1_LOCAL_RANGE_BASE & PROT_BITS_OFFS)
+			>> 7) << 2;
+	mask = 1U << ((mmNIC1_QM1_LOCAL_RANGE_BASE & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_LOCAL_RANGE_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_GLBL_AXCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_IND_GW_APB_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_IND_GW_APB_WDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_IND_GW_APB_RDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_IND_GW_APB_STATUS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC1_QM1_GLBL_ERR_WDATA & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC1_QM1_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC1_QM1_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS)
+			>> 7) << 2;
+	mask = 1U << ((mmNIC1_QM1_GLBL_MEM_INIT_BUSY & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	WREG32(mmNIC2_QM0_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+	WREG32(mmNIC2_QM1_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+
+	pb_addr = (mmNIC2_QM0_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC2_QM0_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC2_QM0_GLBL_CFG0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_GLBL_CFG1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_GLBL_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_GLBL_ERR_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_GLBL_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_GLBL_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_GLBL_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_GLBL_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_GLBL_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_GLBL_STS0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_GLBL_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_GLBL_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_GLBL_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_GLBL_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_GLBL_STS1_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_GLBL_MSG_EN_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_GLBL_MSG_EN_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_GLBL_MSG_EN_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_GLBL_MSG_EN_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_GLBL_MSG_EN_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_PQ_BASE_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_PQ_BASE_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_PQ_BASE_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_PQ_BASE_LO_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC2_QM0_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC2_QM0_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC2_QM0_PQ_BASE_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_PQ_BASE_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_PQ_BASE_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_PQ_BASE_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_PQ_SIZE_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_PQ_SIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_PQ_SIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_PQ_SIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_PQ_PI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_PQ_PI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_PQ_PI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_PQ_PI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_PQ_CI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_PQ_CI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_PQ_CI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_PQ_CI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_PQ_CFG0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_PQ_CFG0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_PQ_CFG0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_PQ_CFG0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_PQ_CFG1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_PQ_CFG1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_PQ_CFG1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_PQ_CFG1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_PQ_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_PQ_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_PQ_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_PQ_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_PQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_PQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_PQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_PQ_STS0_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC2_QM0_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC2_QM0_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC2_QM0_PQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_PQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_PQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_PQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_STS0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_PTR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_PTR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_TSIZE_0 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC2_QM0_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC2_QM0_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC2_QM0_CQ_CTL_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_PTR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_PTR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_TSIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_CTL_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_PTR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_PTR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_TSIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_CTL_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_PTR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_PTR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_TSIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_CTL_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_PTR_LO_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_PTR_LO_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_PTR_LO_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_PTR_LO_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_PTR_LO_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_PTR_HI_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_PTR_HI_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_PTR_HI_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_PTR_HI_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_PTR_HI_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_TSIZE_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_TSIZE_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_TSIZE_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_TSIZE_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_TSIZE_STS_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC2_QM0_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC2_QM0_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC2_QM0_CQ_CTL_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_CTL_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_CTL_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_CTL_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_CTL_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_IFIFO_CNT_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_IFIFO_CNT_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_IFIFO_CNT_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_IFIFO_CNT_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CQ_IFIFO_CNT_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC2_QM0_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) +
+			PROT_BITS_OFFS;
+	word_offset = ((mmNIC2_QM0_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS)
+				>> 7) << 2;
+	mask = 1U << ((mmNIC2_QM0_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC2_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) +
+			PROT_BITS_OFFS;
+	word_offset = ((mmNIC2_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC2_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC2_QM0_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC2_QM0_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC2_QM0_CP_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_CURRENT_INST_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_CURRENT_INST_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_CURRENT_INST_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_CURRENT_INST_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_CURRENT_INST_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_CURRENT_INST_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_CURRENT_INST_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_CURRENT_INST_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_CURRENT_INST_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_CURRENT_INST_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_BARRIER_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_BARRIER_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_BARRIER_CFG_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC2_QM0_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC2_QM0_CP_BARRIER_CFG_3 & PROT_BITS_OFFS)
+			>> 7) << 2;
+	mask = 1U << ((mmNIC2_QM0_CP_BARRIER_CFG_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_BARRIER_CFG_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_DBG_0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_DBG_0_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC2_QM0_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC2_QM0_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC2_QM0_CP_DBG_0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_DBG_0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_DBG_0_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_ARUSER_31_11_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_AWUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_AWUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_AWUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_AWUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CP_AWUSER_31_11_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC2_QM0_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC2_QM0_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC2_QM0_ARB_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC2_QM0_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_24 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) +
+			PROT_BITS_OFFS;
+	word_offset = ((mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_23 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC2_QM0_ARB_SLV_CHOISE_WDT & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC2_QM0_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC2_QM0_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC2_QM0_ARB_STATE_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MSG_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_ERR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_ERR_MSG_EN & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_ERR_STS_DRP & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_19 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC2_QM0_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC2_QM0_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS)
+			>> 7) << 2;
+	mask = 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_23 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_31 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CGM_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CGM_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CGM_CFG1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC2_QM0_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC2_QM0_LOCAL_RANGE_BASE & PROT_BITS_OFFS)
+			>> 7) << 2;
+	mask = 1U << ((mmNIC2_QM0_LOCAL_RANGE_BASE & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_LOCAL_RANGE_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_GLBL_AXCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_IND_GW_APB_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_IND_GW_APB_WDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_IND_GW_APB_RDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_IND_GW_APB_STATUS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM0_GLBL_ERR_WDATA & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC2_QM0_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC2_QM0_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS)
+			>> 7) << 2;
+	mask = 1U << ((mmNIC2_QM0_GLBL_MEM_INIT_BUSY & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC2_QM1_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC2_QM1_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC2_QM1_GLBL_CFG0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_GLBL_CFG1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_GLBL_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_GLBL_ERR_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_GLBL_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_GLBL_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_GLBL_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_GLBL_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_GLBL_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_GLBL_STS0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_GLBL_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_GLBL_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_GLBL_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_GLBL_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_GLBL_STS1_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_GLBL_MSG_EN_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_GLBL_MSG_EN_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_GLBL_MSG_EN_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_GLBL_MSG_EN_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_GLBL_MSG_EN_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_PQ_BASE_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_PQ_BASE_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_PQ_BASE_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_PQ_BASE_LO_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC2_QM1_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC2_QM1_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC2_QM1_PQ_BASE_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_PQ_BASE_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_PQ_BASE_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_PQ_BASE_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_PQ_SIZE_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_PQ_SIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_PQ_SIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_PQ_SIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_PQ_PI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_PQ_PI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_PQ_PI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_PQ_PI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_PQ_CI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_PQ_CI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_PQ_CI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_PQ_CI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_PQ_CFG0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_PQ_CFG0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_PQ_CFG0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_PQ_CFG0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_PQ_CFG1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_PQ_CFG1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_PQ_CFG1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_PQ_CFG1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_PQ_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_PQ_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_PQ_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_PQ_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_PQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_PQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_PQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_PQ_STS0_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC2_QM1_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC2_QM1_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC2_QM1_PQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_PQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_PQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_PQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_STS0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_PTR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_PTR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_TSIZE_0 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC2_QM1_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC2_QM1_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC2_QM1_CQ_CTL_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_PTR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_PTR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_TSIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_CTL_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_PTR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_PTR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_TSIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_CTL_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_PTR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_PTR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_TSIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_CTL_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_PTR_LO_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_PTR_LO_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_PTR_LO_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_PTR_LO_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_PTR_LO_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_PTR_HI_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_PTR_HI_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_PTR_HI_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_PTR_HI_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_PTR_HI_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_TSIZE_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_TSIZE_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_TSIZE_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_TSIZE_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_TSIZE_STS_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC2_QM1_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC2_QM1_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC2_QM1_CQ_CTL_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_CTL_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_CTL_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_CTL_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_CTL_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_IFIFO_CNT_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_IFIFO_CNT_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_IFIFO_CNT_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_IFIFO_CNT_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CQ_IFIFO_CNT_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC2_QM1_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC2_QM1_CP_MSG_BASE2_ADDR_LO_2 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC2_QM1_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC2_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) +
+			PROT_BITS_OFFS;
+	word_offset = ((mmNIC2_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC2_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC2_QM1_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC2_QM1_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC2_QM1_CP_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_CURRENT_INST_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_CURRENT_INST_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_CURRENT_INST_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_CURRENT_INST_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_CURRENT_INST_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_CURRENT_INST_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_CURRENT_INST_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_CURRENT_INST_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_CURRENT_INST_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_CURRENT_INST_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_BARRIER_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_BARRIER_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_BARRIER_CFG_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC2_QM1_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC2_QM1_CP_BARRIER_CFG_3 & PROT_BITS_OFFS)
+			>> 7) << 2;
+	mask = 1U << ((mmNIC2_QM1_CP_BARRIER_CFG_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_BARRIER_CFG_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_DBG_0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_DBG_0_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC2_QM1_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC2_QM1_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC2_QM1_CP_DBG_0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_DBG_0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_DBG_0_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_ARUSER_31_11_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_AWUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_AWUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_AWUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_AWUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CP_AWUSER_31_11_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC2_QM1_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC2_QM1_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC2_QM1_ARB_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC2_QM1_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_24 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) +
+			PROT_BITS_OFFS;
+	word_offset = ((mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_23 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC2_QM1_ARB_SLV_CHOISE_WDT & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC2_QM1_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC2_QM1_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC2_QM1_ARB_STATE_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MSG_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_ERR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_ERR_MSG_EN & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_ERR_STS_DRP & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_19 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC2_QM1_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC2_QM1_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS)
+			>> 7) << 2;
+	mask = 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_23 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_31 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CGM_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CGM_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CGM_CFG1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC2_QM1_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC2_QM1_LOCAL_RANGE_BASE & PROT_BITS_OFFS)
+			>> 7) << 2;
+	mask = 1U << ((mmNIC2_QM1_LOCAL_RANGE_BASE & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_LOCAL_RANGE_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_GLBL_AXCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_IND_GW_APB_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_IND_GW_APB_WDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_IND_GW_APB_RDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_IND_GW_APB_STATUS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC2_QM1_GLBL_ERR_WDATA & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC2_QM1_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC2_QM1_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS)
+			>> 7) << 2;
+	mask = 1U << ((mmNIC2_QM1_GLBL_MEM_INIT_BUSY & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	WREG32(mmNIC3_QM0_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+	WREG32(mmNIC3_QM1_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+
+	pb_addr = (mmNIC3_QM0_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC3_QM0_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC3_QM0_GLBL_CFG0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_GLBL_CFG1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_GLBL_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_GLBL_ERR_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_GLBL_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_GLBL_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_GLBL_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_GLBL_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_GLBL_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_GLBL_STS0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_GLBL_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_GLBL_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_GLBL_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_GLBL_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_GLBL_STS1_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_GLBL_MSG_EN_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_GLBL_MSG_EN_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_GLBL_MSG_EN_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_GLBL_MSG_EN_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_GLBL_MSG_EN_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_PQ_BASE_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_PQ_BASE_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_PQ_BASE_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_PQ_BASE_LO_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC3_QM0_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC3_QM0_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC3_QM0_PQ_BASE_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_PQ_BASE_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_PQ_BASE_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_PQ_BASE_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_PQ_SIZE_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_PQ_SIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_PQ_SIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_PQ_SIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_PQ_PI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_PQ_PI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_PQ_PI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_PQ_PI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_PQ_CI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_PQ_CI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_PQ_CI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_PQ_CI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_PQ_CFG0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_PQ_CFG0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_PQ_CFG0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_PQ_CFG0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_PQ_CFG1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_PQ_CFG1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_PQ_CFG1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_PQ_CFG1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_PQ_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_PQ_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_PQ_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_PQ_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_PQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_PQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_PQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_PQ_STS0_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC3_QM0_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC3_QM0_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC3_QM0_PQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_PQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_PQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_PQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_STS0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_PTR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_PTR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_TSIZE_0 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC3_QM0_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC3_QM0_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC3_QM0_CQ_CTL_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_PTR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_PTR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_TSIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_CTL_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_PTR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_PTR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_TSIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_CTL_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_PTR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_PTR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_TSIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_CTL_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_PTR_LO_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_PTR_LO_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_PTR_LO_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_PTR_LO_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_PTR_LO_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_PTR_HI_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_PTR_HI_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_PTR_HI_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_PTR_HI_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_PTR_HI_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_TSIZE_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_TSIZE_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_TSIZE_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_TSIZE_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_TSIZE_STS_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC3_QM0_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC3_QM0_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC3_QM0_CQ_CTL_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_CTL_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_CTL_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_CTL_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_CTL_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_IFIFO_CNT_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_IFIFO_CNT_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_IFIFO_CNT_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_IFIFO_CNT_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CQ_IFIFO_CNT_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC3_QM0_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC3_QM0_CP_MSG_BASE2_ADDR_LO_2 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC3_QM0_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC3_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) +
+			PROT_BITS_OFFS;
+	word_offset = ((mmNIC3_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC3_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC3_QM0_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC3_QM0_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC3_QM0_CP_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_CURRENT_INST_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_CURRENT_INST_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_CURRENT_INST_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_CURRENT_INST_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_CURRENT_INST_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_CURRENT_INST_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_CURRENT_INST_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_CURRENT_INST_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_CURRENT_INST_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_CURRENT_INST_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_BARRIER_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_BARRIER_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_BARRIER_CFG_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC3_QM0_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC3_QM0_CP_BARRIER_CFG_3 & PROT_BITS_OFFS)
+			>> 7) << 2;
+	mask = 1U << ((mmNIC3_QM0_CP_BARRIER_CFG_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_BARRIER_CFG_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_DBG_0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_DBG_0_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC3_QM0_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC3_QM0_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC3_QM0_CP_DBG_0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_DBG_0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_DBG_0_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_ARUSER_31_11_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_AWUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_AWUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_AWUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_AWUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CP_AWUSER_31_11_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC3_QM0_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC3_QM0_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC3_QM0_ARB_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC3_QM0_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_24 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) +
+			PROT_BITS_OFFS;
+	word_offset = ((mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_23 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC3_QM0_ARB_SLV_CHOISE_WDT & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC3_QM0_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC3_QM0_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC3_QM0_ARB_STATE_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MSG_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_ERR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_ERR_MSG_EN & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_ERR_STS_DRP & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_19 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC3_QM0_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC3_QM0_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS)
+			>> 7) << 2;
+	mask = 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_23 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_31 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CGM_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CGM_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CGM_CFG1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC3_QM0_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC3_QM0_LOCAL_RANGE_BASE & PROT_BITS_OFFS)
+			>> 7) << 2;
+	mask = 1U << ((mmNIC3_QM0_LOCAL_RANGE_BASE & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_LOCAL_RANGE_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_GLBL_AXCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_IND_GW_APB_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_IND_GW_APB_WDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_IND_GW_APB_RDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_IND_GW_APB_STATUS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM0_GLBL_ERR_WDATA & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC3_QM0_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC3_QM0_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS)
+			>> 7) << 2;
+	mask = 1U << ((mmNIC3_QM0_GLBL_MEM_INIT_BUSY & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC3_QM1_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC3_QM1_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC3_QM1_GLBL_CFG0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_GLBL_CFG1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_GLBL_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_GLBL_ERR_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_GLBL_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_GLBL_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_GLBL_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_GLBL_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_GLBL_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_GLBL_STS0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_GLBL_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_GLBL_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_GLBL_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_GLBL_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_GLBL_STS1_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_GLBL_MSG_EN_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_GLBL_MSG_EN_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_GLBL_MSG_EN_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_GLBL_MSG_EN_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_GLBL_MSG_EN_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_PQ_BASE_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_PQ_BASE_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_PQ_BASE_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_PQ_BASE_LO_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC3_QM1_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC3_QM1_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC3_QM1_PQ_BASE_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_PQ_BASE_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_PQ_BASE_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_PQ_BASE_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_PQ_SIZE_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_PQ_SIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_PQ_SIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_PQ_SIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_PQ_PI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_PQ_PI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_PQ_PI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_PQ_PI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_PQ_CI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_PQ_CI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_PQ_CI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_PQ_CI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_PQ_CFG0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_PQ_CFG0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_PQ_CFG0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_PQ_CFG0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_PQ_CFG1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_PQ_CFG1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_PQ_CFG1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_PQ_CFG1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_PQ_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_PQ_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_PQ_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_PQ_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_PQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_PQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_PQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_PQ_STS0_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC3_QM1_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC3_QM1_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC3_QM1_PQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_PQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_PQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_PQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_STS0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_PTR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_PTR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_TSIZE_0 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC3_QM1_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC3_QM1_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC3_QM1_CQ_CTL_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_PTR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_PTR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_TSIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_CTL_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_PTR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_PTR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_TSIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_CTL_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_PTR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_PTR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_TSIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_CTL_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_PTR_LO_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_PTR_LO_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_PTR_LO_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_PTR_LO_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_PTR_LO_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_PTR_HI_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_PTR_HI_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_PTR_HI_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_PTR_HI_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_PTR_HI_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_TSIZE_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_TSIZE_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_TSIZE_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_TSIZE_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_TSIZE_STS_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC3_QM1_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC3_QM1_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC3_QM1_CQ_CTL_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_CTL_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_CTL_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_CTL_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_CTL_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_IFIFO_CNT_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_IFIFO_CNT_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_IFIFO_CNT_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_IFIFO_CNT_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CQ_IFIFO_CNT_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC3_QM1_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC3_QM1_CP_MSG_BASE2_ADDR_LO_2 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC3_QM1_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC3_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) +
+			PROT_BITS_OFFS;
+	word_offset = ((mmNIC3_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC3_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC3_QM1_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC3_QM1_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC3_QM1_CP_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_CURRENT_INST_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_CURRENT_INST_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_CURRENT_INST_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_CURRENT_INST_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_CURRENT_INST_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_CURRENT_INST_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_CURRENT_INST_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_CURRENT_INST_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_CURRENT_INST_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_CURRENT_INST_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_BARRIER_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_BARRIER_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_BARRIER_CFG_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC3_QM1_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC3_QM1_CP_BARRIER_CFG_3 & PROT_BITS_OFFS)
+			>> 7) << 2;
+	mask = 1U << ((mmNIC3_QM1_CP_BARRIER_CFG_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_BARRIER_CFG_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_DBG_0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_DBG_0_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC3_QM1_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC3_QM1_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC3_QM1_CP_DBG_0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_DBG_0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_DBG_0_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_ARUSER_31_11_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_AWUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_AWUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_AWUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_AWUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CP_AWUSER_31_11_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC3_QM1_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC3_QM1_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC3_QM1_ARB_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC3_QM1_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_24 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) +
+			PROT_BITS_OFFS;
+	word_offset = ((mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_23 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC3_QM1_ARB_SLV_CHOISE_WDT & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC3_QM1_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC3_QM1_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC3_QM1_ARB_STATE_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MSG_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_ERR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_ERR_MSG_EN & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_ERR_STS_DRP & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_19 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC3_QM1_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC3_QM1_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS)
+			>> 7) << 2;
+	mask = 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_23 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_31 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CGM_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CGM_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CGM_CFG1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC3_QM1_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC3_QM1_LOCAL_RANGE_BASE & PROT_BITS_OFFS)
+			>> 7) << 2;
+	mask = 1U << ((mmNIC3_QM1_LOCAL_RANGE_BASE & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_LOCAL_RANGE_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_GLBL_AXCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_IND_GW_APB_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_IND_GW_APB_WDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_IND_GW_APB_RDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_IND_GW_APB_STATUS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC3_QM1_GLBL_ERR_WDATA & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC3_QM1_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC3_QM1_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS)
+			>> 7) << 2;
+	mask = 1U << ((mmNIC3_QM1_GLBL_MEM_INIT_BUSY & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	WREG32(mmNIC4_QM0_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+	WREG32(mmNIC4_QM1_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+
+	pb_addr = (mmNIC4_QM0_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC4_QM0_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC4_QM0_GLBL_CFG0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_GLBL_CFG1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_GLBL_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_GLBL_ERR_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_GLBL_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_GLBL_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_GLBL_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_GLBL_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_GLBL_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_GLBL_STS0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_GLBL_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_GLBL_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_GLBL_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_GLBL_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_GLBL_STS1_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_GLBL_MSG_EN_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_GLBL_MSG_EN_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_GLBL_MSG_EN_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_GLBL_MSG_EN_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_GLBL_MSG_EN_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_PQ_BASE_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_PQ_BASE_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_PQ_BASE_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_PQ_BASE_LO_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC4_QM0_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC4_QM0_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC4_QM0_PQ_BASE_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_PQ_BASE_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_PQ_BASE_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_PQ_BASE_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_PQ_SIZE_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_PQ_SIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_PQ_SIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_PQ_SIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_PQ_PI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_PQ_PI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_PQ_PI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_PQ_PI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_PQ_CI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_PQ_CI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_PQ_CI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_PQ_CI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_PQ_CFG0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_PQ_CFG0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_PQ_CFG0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_PQ_CFG0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_PQ_CFG1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_PQ_CFG1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_PQ_CFG1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_PQ_CFG1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_PQ_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_PQ_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_PQ_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_PQ_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_PQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_PQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_PQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_PQ_STS0_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC4_QM0_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC4_QM0_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC4_QM0_PQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_PQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_PQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_PQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_STS0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_PTR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_PTR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_TSIZE_0 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC4_QM0_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC4_QM0_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC4_QM0_CQ_CTL_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_PTR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_PTR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_TSIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_CTL_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_PTR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_PTR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_TSIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_CTL_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_PTR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_PTR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_TSIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_CTL_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_PTR_LO_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_PTR_LO_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_PTR_LO_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_PTR_LO_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_PTR_LO_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_PTR_HI_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_PTR_HI_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_PTR_HI_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_PTR_HI_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_PTR_HI_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_TSIZE_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_TSIZE_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_TSIZE_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_TSIZE_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_TSIZE_STS_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC4_QM0_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC4_QM0_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC4_QM0_CQ_CTL_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_CTL_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_CTL_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_CTL_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_CTL_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_IFIFO_CNT_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_IFIFO_CNT_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_IFIFO_CNT_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_IFIFO_CNT_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CQ_IFIFO_CNT_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC4_QM0_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC4_QM0_CP_MSG_BASE2_ADDR_LO_2 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC4_QM0_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC4_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) +
+			PROT_BITS_OFFS;
+	word_offset = ((mmNIC4_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC4_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC4_QM0_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC4_QM0_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC4_QM0_CP_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_CURRENT_INST_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_CURRENT_INST_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_CURRENT_INST_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_CURRENT_INST_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_CURRENT_INST_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_CURRENT_INST_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_CURRENT_INST_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_CURRENT_INST_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_CURRENT_INST_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_CURRENT_INST_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_BARRIER_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_BARRIER_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_BARRIER_CFG_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC4_QM0_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC4_QM0_CP_BARRIER_CFG_3 & PROT_BITS_OFFS)
+			>> 7) << 2;
+	mask = 1U << ((mmNIC4_QM0_CP_BARRIER_CFG_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_BARRIER_CFG_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_DBG_0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_DBG_0_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC4_QM0_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC4_QM0_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC4_QM0_CP_DBG_0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_DBG_0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_DBG_0_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_ARUSER_31_11_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_AWUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_AWUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_AWUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_AWUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CP_AWUSER_31_11_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC4_QM0_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC4_QM0_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC4_QM0_ARB_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC4_QM0_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_24 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) +
+			PROT_BITS_OFFS;
+	word_offset = ((mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_23 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC4_QM0_ARB_SLV_CHOISE_WDT & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC4_QM0_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC4_QM0_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC4_QM0_ARB_STATE_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MSG_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_ERR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_ERR_MSG_EN & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_ERR_STS_DRP & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_19 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC4_QM0_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC4_QM0_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS)
+			>> 7) << 2;
+	mask = 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_23 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_31 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CGM_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CGM_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CGM_CFG1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC4_QM0_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC4_QM0_LOCAL_RANGE_BASE & PROT_BITS_OFFS)
+			>> 7) << 2;
+	mask = 1U << ((mmNIC4_QM0_LOCAL_RANGE_BASE & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_LOCAL_RANGE_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_GLBL_AXCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_IND_GW_APB_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_IND_GW_APB_WDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_IND_GW_APB_RDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_IND_GW_APB_STATUS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM0_GLBL_ERR_WDATA & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC4_QM0_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC4_QM0_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS)
+			>> 7) << 2;
+	mask = 1U << ((mmNIC4_QM0_GLBL_MEM_INIT_BUSY & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC4_QM1_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC4_QM1_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC4_QM1_GLBL_CFG0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_GLBL_CFG1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_GLBL_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_GLBL_ERR_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_GLBL_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_GLBL_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_GLBL_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_GLBL_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_GLBL_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_GLBL_STS0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_GLBL_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_GLBL_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_GLBL_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_GLBL_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_GLBL_STS1_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_GLBL_MSG_EN_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_GLBL_MSG_EN_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_GLBL_MSG_EN_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_GLBL_MSG_EN_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_GLBL_MSG_EN_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_PQ_BASE_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_PQ_BASE_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_PQ_BASE_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_PQ_BASE_LO_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC4_QM1_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC4_QM1_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC4_QM1_PQ_BASE_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_PQ_BASE_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_PQ_BASE_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_PQ_BASE_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_PQ_SIZE_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_PQ_SIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_PQ_SIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_PQ_SIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_PQ_PI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_PQ_PI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_PQ_PI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_PQ_PI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_PQ_CI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_PQ_CI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_PQ_CI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_PQ_CI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_PQ_CFG0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_PQ_CFG0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_PQ_CFG0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_PQ_CFG0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_PQ_CFG1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_PQ_CFG1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_PQ_CFG1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_PQ_CFG1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_PQ_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_PQ_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_PQ_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_PQ_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_PQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_PQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_PQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_PQ_STS0_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC4_QM1_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC4_QM1_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC4_QM1_PQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_PQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_PQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_PQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_STS0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_PTR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_PTR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_TSIZE_0 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC4_QM1_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC4_QM1_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC4_QM1_CQ_CTL_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_PTR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_PTR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_TSIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_CTL_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_PTR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_PTR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_TSIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_CTL_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_PTR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_PTR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_TSIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_CTL_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_PTR_LO_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_PTR_LO_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_PTR_LO_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_PTR_LO_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_PTR_LO_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_PTR_HI_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_PTR_HI_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_PTR_HI_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_PTR_HI_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_PTR_HI_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_TSIZE_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_TSIZE_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_TSIZE_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_TSIZE_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_TSIZE_STS_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC4_QM1_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC4_QM1_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC4_QM1_CQ_CTL_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_CTL_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_CTL_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_CTL_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_CTL_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_IFIFO_CNT_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_IFIFO_CNT_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_IFIFO_CNT_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_IFIFO_CNT_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CQ_IFIFO_CNT_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC4_QM1_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC4_QM1_CP_MSG_BASE2_ADDR_LO_2 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC4_QM1_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC4_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) +
+			PROT_BITS_OFFS;
+	word_offset = ((mmNIC4_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC4_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC4_QM1_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC4_QM1_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC4_QM1_CP_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_CURRENT_INST_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_CURRENT_INST_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_CURRENT_INST_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_CURRENT_INST_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_CURRENT_INST_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_CURRENT_INST_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_CURRENT_INST_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_CURRENT_INST_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_CURRENT_INST_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_CURRENT_INST_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_BARRIER_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_BARRIER_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_BARRIER_CFG_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC4_QM1_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC4_QM1_CP_BARRIER_CFG_3 & PROT_BITS_OFFS)
+			>> 7) << 2;
+	mask = 1U << ((mmNIC4_QM1_CP_BARRIER_CFG_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_BARRIER_CFG_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_DBG_0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_DBG_0_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC4_QM1_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC4_QM1_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC4_QM1_CP_DBG_0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_DBG_0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_DBG_0_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_ARUSER_31_11_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_AWUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_AWUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_AWUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_AWUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CP_AWUSER_31_11_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC4_QM1_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC4_QM1_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC4_QM1_ARB_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC4_QM1_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_24 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) +
+			PROT_BITS_OFFS;
+	word_offset = ((mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_23 &
+			PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC4_QM1_ARB_SLV_CHOISE_WDT & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC4_QM1_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC4_QM1_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmNIC4_QM1_ARB_STATE_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MSG_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_ERR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_ERR_MSG_EN & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_ERR_STS_DRP & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_19 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC4_QM1_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC4_QM1_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS)
+			>> 7) << 2;
+	mask = 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_23 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_31 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CGM_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CGM_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CGM_CFG1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC4_QM1_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC4_QM1_LOCAL_RANGE_BASE & PROT_BITS_OFFS)
+			>> 7) << 2;
+	mask = 1U << ((mmNIC4_QM1_LOCAL_RANGE_BASE & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_LOCAL_RANGE_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_GLBL_AXCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_IND_GW_APB_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_IND_GW_APB_WDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_IND_GW_APB_RDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_IND_GW_APB_STATUS & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmNIC4_QM1_GLBL_ERR_WDATA & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmNIC4_QM1_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmNIC4_QM1_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS)
+			>> 7) << 2;
+	mask = 1U << ((mmNIC4_QM1_GLBL_MEM_INIT_BUSY & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+}
+
+static void gaudi_init_tpc_protection_bits(struct hl_device *hdev)
+{
+	u32 pb_addr, mask;
+	u8 word_offset;
+
+	if (!hdev->asic_prop.fw_security_enabled) {
+		gaudi_pb_set_block(hdev, mmTPC0_E2E_CRED_BASE);
+		gaudi_pb_set_block(hdev, mmTPC1_E2E_CRED_BASE);
+		gaudi_pb_set_block(hdev, mmTPC2_E2E_CRED_BASE);
+		gaudi_pb_set_block(hdev, mmTPC3_E2E_CRED_BASE);
+		gaudi_pb_set_block(hdev, mmTPC4_E2E_CRED_BASE);
+		gaudi_pb_set_block(hdev, mmTPC5_E2E_CRED_BASE);
+		gaudi_pb_set_block(hdev, mmTPC6_E2E_CRED_BASE);
+		gaudi_pb_set_block(hdev, mmTPC7_E2E_CRED_BASE);
+	}
+
+	WREG32(mmTPC0_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+	WREG32(mmTPC0_CFG_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+
+	pb_addr = (mmTPC0_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC0_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC0_QM_GLBL_CFG0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_GLBL_CFG1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_GLBL_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_GLBL_ERR_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_GLBL_STS0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_GLBL_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_GLBL_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_GLBL_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_GLBL_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_GLBL_STS1_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_GLBL_MSG_EN_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_GLBL_MSG_EN_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_GLBL_MSG_EN_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_GLBL_MSG_EN_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_GLBL_MSG_EN_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_PQ_BASE_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_PQ_BASE_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_PQ_BASE_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_PQ_BASE_LO_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC0_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC0_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC0_QM_PQ_BASE_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_PQ_BASE_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_PQ_BASE_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_PQ_BASE_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_PQ_SIZE_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_PQ_SIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_PQ_SIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_PQ_SIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_PQ_PI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_PQ_PI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_PQ_PI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_PQ_PI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_PQ_CI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_PQ_CI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_PQ_CI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_PQ_CI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_PQ_CFG0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_PQ_CFG0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_PQ_CFG0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_PQ_CFG0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_PQ_CFG1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_PQ_CFG1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_PQ_CFG1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_PQ_CFG1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_PQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_PQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_PQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_PQ_STS0_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC0_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC0_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC0_QM_PQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_PQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_PQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_PQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_STS0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_PTR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_PTR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_TSIZE_0 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC0_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC0_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC0_QM_CQ_CTL_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_PTR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_PTR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_TSIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_CTL_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_PTR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_PTR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_TSIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_CTL_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_PTR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_PTR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_TSIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_CTL_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC0_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC0_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC0_QM_CQ_CTL_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_CTL_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_CTL_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_CTL_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_CTL_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7)
+									<< 2;
+	mask = 1U << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) +
+								PROT_BITS_OFFS;
+
+	word_offset = ((mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS)
+								>> 7) << 2;
+
+	mask = 1U << ((mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC0_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC0_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC0_QM_CP_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC0_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC0_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC0_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_DBG_0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_DBG_0_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC0_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC0_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC0_QM_CP_DBG_0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_DBG_0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_DBG_0_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC0_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC0_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC0_QM_ARB_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC0_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC0_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7)
+									<< 2;
+	mask = 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) +
+								PROT_BITS_OFFS;
+
+	word_offset = ((mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS)
+								>> 7) << 2;
+	mask = 1U << ((mmTPC0_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC0_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC0_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC0_QM_ARB_STATE_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MSG_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_ERR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_ERR_MSG_EN & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_ERR_STS_DRP & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC0_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC0_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7)
+									<< 2;
+	mask = 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CGM_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CGM_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CGM_CFG1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC0_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC0_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC0_QM_LOCAL_RANGE_BASE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_GLBL_AXCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_IND_GW_APB_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_IND_GW_APB_WDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_IND_GW_APB_RDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_IND_GW_APB_STATUS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_QM_GLBL_ERR_WDATA & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC0_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC0_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7)
+									<< 2;
+	mask = 1U << ((mmTPC0_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC0_CFG_ROUND_CSR & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC0_CFG_ROUND_CSR & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC0_CFG_ROUND_CSR & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC0_CFG_PROT & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC0_CFG_PROT & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC0_CFG_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_CFG_VFLAGS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_CFG_SFLAGS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_CFG_TPC_STALL & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_CFG_ICACHE_BASE_ADDERESS_HIGH & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_CFG_RD_RATE_LIMIT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_CFG_WR_RATE_LIMIT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_CFG_MSS_CONFIG & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_CFG_TPC_INTR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_CFG_TPC_INTR_MASK & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_CFG_WQ_CREDITS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_CFG_ARUSER_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_CFG_ARUSER_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_CFG_AWUSER_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_CFG_AWUSER_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_CFG_OPCODE_EXEC & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC0_CFG_TSB_CFG_MAX_SIZE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC0_CFG_TSB_CFG_MAX_SIZE & PROT_BITS_OFFS) >> 7)
+									<< 2;
+	mask = 1U << ((mmTPC0_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_CFG_DBGMEM_ADD & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_CFG_DBGMEM_DATA_WR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_CFG_DBGMEM_DATA_RD & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_CFG_DBGMEM_CTRL & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_CFG_DBGMEM_RC & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_CFG_FUNC_MBIST_PAT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC0_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	WREG32(mmTPC1_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+	WREG32(mmTPC1_CFG_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+
+	pb_addr = (mmTPC1_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC1_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC1_QM_GLBL_CFG0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_GLBL_CFG1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_GLBL_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_GLBL_ERR_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_GLBL_STS0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_GLBL_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_GLBL_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_GLBL_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_GLBL_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_GLBL_STS1_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_GLBL_MSG_EN_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_GLBL_MSG_EN_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_GLBL_MSG_EN_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_GLBL_MSG_EN_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_GLBL_MSG_EN_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_PQ_BASE_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_PQ_BASE_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_PQ_BASE_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_PQ_BASE_LO_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC1_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC1_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC1_QM_PQ_BASE_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_PQ_BASE_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_PQ_BASE_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_PQ_BASE_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_PQ_SIZE_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_PQ_SIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_PQ_SIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_PQ_SIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_PQ_PI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_PQ_PI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_PQ_PI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_PQ_PI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_PQ_CI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_PQ_CI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_PQ_CI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_PQ_CI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_PQ_CFG0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_PQ_CFG0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_PQ_CFG0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_PQ_CFG0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_PQ_CFG1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_PQ_CFG1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_PQ_CFG1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_PQ_CFG1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_PQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_PQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_PQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_PQ_STS0_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC1_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC1_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC1_QM_PQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_PQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_PQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_PQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_STS0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_PTR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_PTR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_TSIZE_0 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC1_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC1_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC1_QM_CQ_CTL_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_PTR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_PTR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_TSIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_CTL_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_PTR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_PTR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_TSIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_CTL_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_PTR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_PTR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_TSIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_CTL_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC1_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC1_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC1_QM_CQ_CTL_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_CTL_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_CTL_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_CTL_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_CTL_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7)
+									<< 2;
+	mask = 1U << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) +
+								PROT_BITS_OFFS;
+	word_offset = ((mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS)
+								>> 7) << 2;
+	mask = 1U << ((mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC1_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC1_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC1_QM_CP_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC1_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC1_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC1_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_DBG_0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_DBG_0_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC1_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC1_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC1_QM_CP_DBG_0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_DBG_0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_DBG_0_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC1_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC1_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC1_QM_ARB_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC1_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC1_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7)
+									<< 2;
+	mask = 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) +
+								PROT_BITS_OFFS;
+
+	word_offset = ((mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS)
+								>> 7) << 2;
+	mask = 1U << ((mmTPC1_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC1_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC1_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC1_QM_ARB_STATE_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MSG_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_ERR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_ERR_MSG_EN & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_ERR_STS_DRP & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC1_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC1_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7)
+									<< 2;
+	mask = 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CGM_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CGM_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CGM_CFG1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC1_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC1_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC1_QM_LOCAL_RANGE_BASE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_GLBL_AXCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_IND_GW_APB_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_IND_GW_APB_WDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_IND_GW_APB_RDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_IND_GW_APB_STATUS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_QM_GLBL_ERR_WDATA & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC1_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC1_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7)
+									<< 2;
+	mask = 1U << ((mmTPC1_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC1_CFG_ROUND_CSR & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC1_CFG_ROUND_CSR & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC1_CFG_ROUND_CSR & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC1_CFG_PROT & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC1_CFG_PROT & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC1_CFG_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_CFG_VFLAGS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_CFG_SFLAGS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_CFG_TPC_STALL & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_CFG_ICACHE_BASE_ADDERESS_HIGH & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_CFG_RD_RATE_LIMIT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_CFG_WR_RATE_LIMIT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_CFG_MSS_CONFIG & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_CFG_TPC_INTR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_CFG_TPC_INTR_MASK & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_CFG_WQ_CREDITS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_CFG_ARUSER_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_CFG_ARUSER_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_CFG_AWUSER_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_CFG_AWUSER_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_CFG_OPCODE_EXEC & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC1_CFG_TSB_CFG_MAX_SIZE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC1_CFG_TSB_CFG_MAX_SIZE & PROT_BITS_OFFS) >> 7)
+									<< 2;
+	mask = 1U << ((mmTPC1_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_CFG_DBGMEM_ADD & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_CFG_DBGMEM_DATA_WR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_CFG_DBGMEM_DATA_RD & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_CFG_DBGMEM_CTRL & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_CFG_DBGMEM_RC & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_CFG_FUNC_MBIST_PAT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC1_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	WREG32(mmTPC2_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+	WREG32(mmTPC2_CFG_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+
+	pb_addr = (mmTPC2_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC2_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC2_QM_GLBL_CFG0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_GLBL_CFG1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_GLBL_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_GLBL_ERR_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_GLBL_STS0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_GLBL_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_GLBL_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_GLBL_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_GLBL_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_GLBL_STS1_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_GLBL_MSG_EN_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_GLBL_MSG_EN_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_GLBL_MSG_EN_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_GLBL_MSG_EN_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_GLBL_MSG_EN_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_PQ_BASE_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_PQ_BASE_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_PQ_BASE_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_PQ_BASE_LO_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC2_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC2_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC2_QM_PQ_BASE_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_PQ_BASE_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_PQ_BASE_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_PQ_BASE_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_PQ_SIZE_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_PQ_SIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_PQ_SIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_PQ_SIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_PQ_PI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_PQ_PI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_PQ_PI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_PQ_PI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_PQ_CI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_PQ_CI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_PQ_CI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_PQ_CI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_PQ_CFG0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_PQ_CFG0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_PQ_CFG0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_PQ_CFG0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_PQ_CFG1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_PQ_CFG1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_PQ_CFG1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_PQ_CFG1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_PQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_PQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_PQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_PQ_STS0_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC2_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC2_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC2_QM_PQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_PQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_PQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_PQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_STS0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_PTR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_PTR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_TSIZE_0 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC2_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC2_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC2_QM_CQ_CTL_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_PTR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_PTR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_TSIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_CTL_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_PTR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_PTR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_TSIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_CTL_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_PTR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_PTR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_TSIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_CTL_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC2_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC2_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC2_QM_CQ_CTL_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_CTL_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_CTL_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_CTL_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_CTL_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7)
+									<< 2;
+	mask = 1U << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) +
+								PROT_BITS_OFFS;
+	word_offset = ((mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS)
+								>> 7) << 2;
+	mask = 1U << ((mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC2_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC2_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC2_QM_CP_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC2_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC2_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC2_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_DBG_0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_DBG_0_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC2_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC2_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC2_QM_CP_DBG_0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_DBG_0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_DBG_0_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC2_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC2_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC2_QM_ARB_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC2_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC2_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7)
+									<< 2;
+	mask = 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) +
+								PROT_BITS_OFFS;
+	word_offset = ((mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS)
+								>> 7) << 2;
+	mask = 1U << ((mmTPC2_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC2_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC2_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC2_QM_ARB_STATE_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MSG_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_ERR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_ERR_MSG_EN & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_ERR_STS_DRP & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC2_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC2_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7)
+									<< 2;
+	mask = 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CGM_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CGM_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CGM_CFG1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC2_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC2_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC2_QM_LOCAL_RANGE_BASE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_GLBL_AXCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_IND_GW_APB_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_IND_GW_APB_WDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_IND_GW_APB_RDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_IND_GW_APB_STATUS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_QM_GLBL_ERR_WDATA & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC2_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC2_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7)
+									<< 2;
+	mask = 1U << ((mmTPC2_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC2_CFG_ROUND_CSR & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC2_CFG_ROUND_CSR & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC2_CFG_ROUND_CSR & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC2_CFG_PROT & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC2_CFG_PROT & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC2_CFG_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_CFG_VFLAGS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_CFG_SFLAGS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_CFG_TPC_STALL & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_CFG_ICACHE_BASE_ADDERESS_HIGH & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_CFG_RD_RATE_LIMIT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_CFG_WR_RATE_LIMIT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_CFG_MSS_CONFIG & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_CFG_TPC_INTR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_CFG_TPC_INTR_MASK & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_CFG_WQ_CREDITS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_CFG_ARUSER_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_CFG_ARUSER_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_CFG_AWUSER_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_CFG_AWUSER_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_CFG_OPCODE_EXEC & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC2_CFG_TSB_CFG_MAX_SIZE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC2_CFG_TSB_CFG_MAX_SIZE & PROT_BITS_OFFS) >> 7)
+								<< 2;
+	mask = 1U << ((mmTPC2_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_CFG_DBGMEM_ADD & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_CFG_DBGMEM_DATA_WR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_CFG_DBGMEM_DATA_RD & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_CFG_DBGMEM_CTRL & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_CFG_DBGMEM_RC & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_CFG_FUNC_MBIST_PAT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC2_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	WREG32(mmTPC3_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+	WREG32(mmTPC3_CFG_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+
+	pb_addr = (mmTPC3_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC3_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC3_QM_GLBL_CFG0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_GLBL_CFG1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_GLBL_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_GLBL_ERR_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_GLBL_STS0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_GLBL_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_GLBL_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_GLBL_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_GLBL_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_GLBL_STS1_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_GLBL_MSG_EN_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_GLBL_MSG_EN_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_GLBL_MSG_EN_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_GLBL_MSG_EN_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_GLBL_MSG_EN_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_PQ_BASE_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_PQ_BASE_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_PQ_BASE_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_PQ_BASE_LO_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC3_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC3_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC3_QM_PQ_BASE_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_PQ_BASE_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_PQ_BASE_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_PQ_BASE_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_PQ_SIZE_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_PQ_SIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_PQ_SIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_PQ_SIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_PQ_PI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_PQ_PI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_PQ_PI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_PQ_PI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_PQ_CI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_PQ_CI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_PQ_CI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_PQ_CI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_PQ_CFG0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_PQ_CFG0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_PQ_CFG0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_PQ_CFG0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_PQ_CFG1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_PQ_CFG1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_PQ_CFG1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_PQ_CFG1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_PQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_PQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_PQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_PQ_STS0_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC3_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC3_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC3_QM_PQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_PQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_PQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_PQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_STS0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_PTR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_PTR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_TSIZE_0 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC3_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC3_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC3_QM_CQ_CTL_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_PTR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_PTR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_TSIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_CTL_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_PTR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_PTR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_TSIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_CTL_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_PTR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_PTR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_TSIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_CTL_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC3_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC3_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC3_QM_CQ_CTL_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_CTL_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_CTL_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_CTL_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_CTL_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7)
+									<< 2;
+	mask = 1U << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) +
+								PROT_BITS_OFFS;
+	word_offset = ((mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS)
+								>> 7) << 2;
+	mask = 1U << ((mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC3_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC3_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC3_QM_CP_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC3_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC3_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC3_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_DBG_0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_DBG_0_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC3_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC3_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC3_QM_CP_DBG_0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_DBG_0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_DBG_0_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC3_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC3_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC3_QM_ARB_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC3_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC3_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7)
+									<< 2;
+	mask = 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) +
+								PROT_BITS_OFFS;
+	word_offset = ((mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS)
+								>> 7) << 2;
+	mask = 1U << ((mmTPC3_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC3_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC3_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC3_QM_ARB_STATE_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MSG_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_ERR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_ERR_MSG_EN & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_ERR_STS_DRP & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC3_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC3_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7)
+									<< 2;
+	mask = 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CGM_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CGM_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CGM_CFG1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC3_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC3_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC3_QM_LOCAL_RANGE_BASE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_GLBL_AXCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_IND_GW_APB_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_IND_GW_APB_WDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_IND_GW_APB_RDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_IND_GW_APB_STATUS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_QM_GLBL_ERR_WDATA & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC3_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC3_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7)
+									<< 2;
+	mask = 1U << ((mmTPC3_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC3_CFG_ROUND_CSR & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC3_CFG_ROUND_CSR & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC3_CFG_ROUND_CSR & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC3_CFG_PROT & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC3_CFG_PROT & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC3_CFG_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_CFG_VFLAGS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_CFG_SFLAGS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_CFG_TPC_STALL & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_CFG_ICACHE_BASE_ADDERESS_HIGH & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_CFG_RD_RATE_LIMIT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_CFG_WR_RATE_LIMIT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_CFG_MSS_CONFIG & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_CFG_TPC_INTR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_CFG_TPC_INTR_MASK & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_CFG_WQ_CREDITS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_CFG_ARUSER_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_CFG_ARUSER_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_CFG_AWUSER_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_CFG_AWUSER_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_CFG_OPCODE_EXEC & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC3_CFG_TSB_CFG_MAX_SIZE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC3_CFG_TSB_CFG_MAX_SIZE & PROT_BITS_OFFS) >> 7)
+									<< 2;
+	mask = 1U << ((mmTPC3_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_CFG_DBGMEM_ADD & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_CFG_DBGMEM_DATA_WR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_CFG_DBGMEM_DATA_RD & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_CFG_DBGMEM_CTRL & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_CFG_DBGMEM_RC & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_CFG_FUNC_MBIST_PAT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC3_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	WREG32(mmTPC4_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+	WREG32(mmTPC4_CFG_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+
+	pb_addr = (mmTPC4_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC4_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC4_QM_GLBL_CFG0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_GLBL_CFG1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_GLBL_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_GLBL_ERR_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_GLBL_STS0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_GLBL_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_GLBL_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_GLBL_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_GLBL_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_GLBL_STS1_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_GLBL_MSG_EN_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_GLBL_MSG_EN_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_GLBL_MSG_EN_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_GLBL_MSG_EN_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_GLBL_MSG_EN_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_PQ_BASE_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_PQ_BASE_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_PQ_BASE_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_PQ_BASE_LO_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC4_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC4_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC4_QM_PQ_BASE_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_PQ_BASE_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_PQ_BASE_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_PQ_BASE_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_PQ_SIZE_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_PQ_SIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_PQ_SIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_PQ_SIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_PQ_PI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_PQ_PI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_PQ_PI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_PQ_PI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_PQ_CI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_PQ_CI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_PQ_CI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_PQ_CI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_PQ_CFG0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_PQ_CFG0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_PQ_CFG0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_PQ_CFG0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_PQ_CFG1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_PQ_CFG1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_PQ_CFG1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_PQ_CFG1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_PQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_PQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_PQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_PQ_STS0_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC4_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC4_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC4_QM_PQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_PQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_PQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_PQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_STS0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_PTR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_PTR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_TSIZE_0 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC4_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC4_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC4_QM_CQ_CTL_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_PTR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_PTR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_TSIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_CTL_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_PTR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_PTR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_TSIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_CTL_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_PTR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_PTR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_TSIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_CTL_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC4_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC4_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC4_QM_CQ_CTL_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_CTL_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_CTL_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_CTL_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_CTL_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7)
+									<< 2;
+	mask = 1U << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) +
+								PROT_BITS_OFFS;
+	word_offset = ((mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS)
+								>> 7) << 2;
+	mask = 1U << ((mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC4_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC4_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC4_QM_CP_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC4_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC4_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC4_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_DBG_0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_DBG_0_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC4_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC4_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC4_QM_CP_DBG_0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_DBG_0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_DBG_0_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC4_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC4_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC4_QM_ARB_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC4_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC4_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7)
+									<< 2;
+	mask = 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) +
+								PROT_BITS_OFFS;
+	word_offset = ((mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS)
+								>> 7) << 2;
+	mask = 1U << ((mmTPC4_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC4_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC4_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC4_QM_ARB_STATE_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MSG_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_ERR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_ERR_MSG_EN & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_ERR_STS_DRP & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC4_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC4_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7)
+									<< 2;
+	mask = 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CGM_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CGM_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CGM_CFG1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC4_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC4_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC4_QM_LOCAL_RANGE_BASE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_GLBL_AXCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_IND_GW_APB_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_IND_GW_APB_WDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_IND_GW_APB_RDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_IND_GW_APB_STATUS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_QM_GLBL_ERR_WDATA & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC4_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC4_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7)
+									<< 2;
+	mask = 1U << ((mmTPC4_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC4_CFG_ROUND_CSR & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC4_CFG_ROUND_CSR & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC4_CFG_ROUND_CSR & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC4_CFG_PROT & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC4_CFG_PROT & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC4_CFG_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_CFG_VFLAGS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_CFG_SFLAGS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_CFG_TPC_STALL & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_CFG_ICACHE_BASE_ADDERESS_HIGH & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_CFG_RD_RATE_LIMIT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_CFG_WR_RATE_LIMIT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_CFG_MSS_CONFIG & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_CFG_TPC_INTR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_CFG_TPC_INTR_MASK & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_CFG_WQ_CREDITS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_CFG_ARUSER_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_CFG_ARUSER_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_CFG_AWUSER_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_CFG_AWUSER_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_CFG_OPCODE_EXEC & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC4_CFG_TSB_CFG_MAX_SIZE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC4_CFG_TSB_CFG_MAX_SIZE & PROT_BITS_OFFS) >> 7)
+									<< 2;
+	mask = 1U << ((mmTPC4_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_CFG_DBGMEM_ADD & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_CFG_DBGMEM_DATA_WR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_CFG_DBGMEM_DATA_RD & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_CFG_DBGMEM_CTRL & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_CFG_DBGMEM_RC & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_CFG_FUNC_MBIST_PAT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC4_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	WREG32(mmTPC5_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+	WREG32(mmTPC5_CFG_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+
+	pb_addr = (mmTPC5_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC5_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC5_QM_GLBL_CFG0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_GLBL_CFG1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_GLBL_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_GLBL_ERR_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_GLBL_STS0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_GLBL_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_GLBL_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_GLBL_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_GLBL_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_GLBL_STS1_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_GLBL_MSG_EN_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_GLBL_MSG_EN_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_GLBL_MSG_EN_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_GLBL_MSG_EN_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_GLBL_MSG_EN_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_PQ_BASE_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_PQ_BASE_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_PQ_BASE_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_PQ_BASE_LO_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC5_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC5_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC5_QM_PQ_BASE_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_PQ_BASE_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_PQ_BASE_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_PQ_BASE_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_PQ_SIZE_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_PQ_SIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_PQ_SIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_PQ_SIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_PQ_PI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_PQ_PI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_PQ_PI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_PQ_PI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_PQ_CI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_PQ_CI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_PQ_CI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_PQ_CI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_PQ_CFG0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_PQ_CFG0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_PQ_CFG0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_PQ_CFG0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_PQ_CFG1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_PQ_CFG1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_PQ_CFG1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_PQ_CFG1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_PQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_PQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_PQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_PQ_STS0_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC5_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC5_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC5_QM_PQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_PQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_PQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_PQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_STS0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_PTR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_PTR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_TSIZE_0 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC5_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC5_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC5_QM_CQ_CTL_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_PTR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_PTR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_TSIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_CTL_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_PTR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_PTR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_TSIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_CTL_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_PTR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_PTR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_TSIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_CTL_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC5_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC5_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC5_QM_CQ_CTL_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_CTL_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_CTL_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_CTL_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_CTL_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7)
+									<< 2;
+	mask = 1U << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) +
+								PROT_BITS_OFFS;
+	word_offset = ((mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS)
+								>> 7) << 2;
+	mask = 1U << ((mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC5_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC5_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC5_QM_CP_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC5_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC5_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC5_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_DBG_0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_DBG_0_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC5_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC5_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC5_QM_CP_DBG_0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_DBG_0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_DBG_0_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC5_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC5_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC5_QM_ARB_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC5_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC5_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7)
+									<< 2;
+	mask = 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) +
+								PROT_BITS_OFFS;
+	word_offset = ((mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS)
+								>> 7) << 2;
+	mask = 1U << ((mmTPC5_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC5_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC5_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC5_QM_ARB_STATE_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MSG_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_ERR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_ERR_MSG_EN & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_ERR_STS_DRP & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC5_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC5_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7)
+									<< 2;
+	mask = 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CGM_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CGM_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CGM_CFG1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC5_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC5_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC5_QM_LOCAL_RANGE_BASE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_GLBL_AXCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_IND_GW_APB_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_IND_GW_APB_WDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_IND_GW_APB_RDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_IND_GW_APB_STATUS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_QM_GLBL_ERR_WDATA & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC5_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC5_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7)
+									<< 2;
+	mask = 1U << ((mmTPC5_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC5_CFG_ROUND_CSR & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC5_CFG_ROUND_CSR & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC5_CFG_ROUND_CSR & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC5_CFG_PROT & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC5_CFG_PROT & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC5_CFG_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_CFG_VFLAGS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_CFG_SFLAGS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_CFG_TPC_STALL & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_CFG_ICACHE_BASE_ADDERESS_HIGH & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_CFG_RD_RATE_LIMIT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_CFG_WR_RATE_LIMIT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_CFG_MSS_CONFIG & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_CFG_TPC_INTR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_CFG_TPC_INTR_MASK & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_CFG_WQ_CREDITS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_CFG_ARUSER_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_CFG_ARUSER_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_CFG_AWUSER_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_CFG_AWUSER_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_CFG_OPCODE_EXEC & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC5_CFG_TSB_CFG_MAX_SIZE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC5_CFG_TSB_CFG_MAX_SIZE & PROT_BITS_OFFS) >> 7)
+									<< 2;
+	mask = 1U << ((mmTPC5_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_CFG_DBGMEM_ADD & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_CFG_DBGMEM_DATA_WR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_CFG_DBGMEM_DATA_RD & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_CFG_DBGMEM_CTRL & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_CFG_DBGMEM_RC & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_CFG_FUNC_MBIST_PAT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC5_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	WREG32(mmTPC6_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+	WREG32(mmTPC6_CFG_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+
+	pb_addr = (mmTPC6_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC6_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC6_QM_GLBL_CFG0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_GLBL_CFG1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_GLBL_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_GLBL_ERR_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_GLBL_STS0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_GLBL_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_GLBL_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_GLBL_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_GLBL_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_GLBL_STS1_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_GLBL_MSG_EN_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_GLBL_MSG_EN_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_GLBL_MSG_EN_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_GLBL_MSG_EN_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_GLBL_MSG_EN_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_PQ_BASE_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_PQ_BASE_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_PQ_BASE_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_PQ_BASE_LO_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC6_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC6_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC6_QM_PQ_BASE_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_PQ_BASE_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_PQ_BASE_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_PQ_BASE_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_PQ_SIZE_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_PQ_SIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_PQ_SIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_PQ_SIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_PQ_PI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_PQ_PI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_PQ_PI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_PQ_PI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_PQ_CI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_PQ_CI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_PQ_CI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_PQ_CI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_PQ_CFG0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_PQ_CFG0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_PQ_CFG0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_PQ_CFG0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_PQ_CFG1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_PQ_CFG1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_PQ_CFG1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_PQ_CFG1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_PQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_PQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_PQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_PQ_STS0_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC6_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC6_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC6_QM_PQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_PQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_PQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_PQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_STS0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_PTR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_PTR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_TSIZE_0 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC6_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC6_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC6_QM_CQ_CTL_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_PTR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_PTR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_TSIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_CTL_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_PTR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_PTR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_TSIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_CTL_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_PTR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_PTR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_TSIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_CTL_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC6_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC6_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC6_QM_CQ_CTL_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_CTL_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_CTL_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_CTL_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_CTL_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7)
+									<< 2;
+	mask = 1U << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) +
+								PROT_BITS_OFFS;
+	word_offset = ((mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS)
+								>> 7) << 2;
+	mask = 1U << ((mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC6_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC6_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC6_QM_CP_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC6_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC6_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC6_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_DBG_0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_DBG_0_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC6_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC6_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC6_QM_CP_DBG_0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_DBG_0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_DBG_0_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC6_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC6_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC6_QM_ARB_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC6_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC6_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7)
+									<< 2;
+	mask = 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) +
+								PROT_BITS_OFFS;
+
+	word_offset = ((mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS)
+								>> 7) << 2;
+	mask = 1U << ((mmTPC6_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC6_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC6_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC6_QM_ARB_STATE_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MSG_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_ERR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_ERR_MSG_EN & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_ERR_STS_DRP & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC6_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC6_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7)
+									<< 2;
+	mask = 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CGM_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CGM_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CGM_CFG1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC6_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC6_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC6_QM_LOCAL_RANGE_BASE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_GLBL_AXCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_IND_GW_APB_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_IND_GW_APB_WDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_IND_GW_APB_RDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_IND_GW_APB_STATUS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_QM_GLBL_ERR_WDATA & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC6_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC6_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7)
+									<< 2;
+
+	mask = 1U << ((mmTPC6_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC6_CFG_ROUND_CSR & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC6_CFG_ROUND_CSR & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC6_CFG_ROUND_CSR & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC6_CFG_PROT & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC6_CFG_PROT & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC6_CFG_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_CFG_VFLAGS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_CFG_SFLAGS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_CFG_TPC_STALL & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_CFG_ICACHE_BASE_ADDERESS_HIGH & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_CFG_RD_RATE_LIMIT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_CFG_WR_RATE_LIMIT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_CFG_MSS_CONFIG & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_CFG_TPC_INTR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_CFG_TPC_INTR_MASK & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_CFG_WQ_CREDITS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_CFG_ARUSER_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_CFG_ARUSER_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_CFG_AWUSER_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_CFG_AWUSER_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_CFG_OPCODE_EXEC & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC6_CFG_TSB_CFG_MAX_SIZE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC6_CFG_TSB_CFG_MAX_SIZE & PROT_BITS_OFFS) >> 7)
+									<< 2;
+	mask = 1U << ((mmTPC6_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_CFG_DBGMEM_ADD & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_CFG_DBGMEM_DATA_WR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_CFG_DBGMEM_DATA_RD & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_CFG_DBGMEM_CTRL & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_CFG_DBGMEM_RC & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_CFG_FUNC_MBIST_PAT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC6_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	WREG32(mmTPC7_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+	WREG32(mmTPC7_CFG_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
+
+	pb_addr = (mmTPC7_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC7_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC7_QM_GLBL_CFG0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_GLBL_CFG1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_GLBL_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_GLBL_ERR_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_GLBL_STS0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_GLBL_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_GLBL_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_GLBL_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_GLBL_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_GLBL_STS1_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_GLBL_MSG_EN_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_GLBL_MSG_EN_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_GLBL_MSG_EN_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_GLBL_MSG_EN_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_GLBL_MSG_EN_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_PQ_BASE_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_PQ_BASE_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_PQ_BASE_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_PQ_BASE_LO_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC7_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC7_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC7_QM_PQ_BASE_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_PQ_BASE_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_PQ_BASE_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_PQ_BASE_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_PQ_SIZE_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_PQ_SIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_PQ_SIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_PQ_SIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_PQ_PI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_PQ_PI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_PQ_PI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_PQ_PI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_PQ_CI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_PQ_CI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_PQ_CI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_PQ_CI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_PQ_CFG0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_PQ_CFG0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_PQ_CFG0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_PQ_CFG0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_PQ_CFG1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_PQ_CFG1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_PQ_CFG1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_PQ_CFG1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_PQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_PQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_PQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_PQ_STS0_3 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC7_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC7_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC7_QM_PQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_PQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_PQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_PQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_STS0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_STS0_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_STS0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_STS0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_STS1_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_STS1_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_STS1_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_STS1_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_PTR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_PTR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_TSIZE_0 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC7_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC7_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC7_QM_CQ_CTL_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_PTR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_PTR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_TSIZE_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_CTL_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_PTR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_PTR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_TSIZE_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_CTL_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_PTR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_PTR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_TSIZE_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_CTL_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC7_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC7_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC7_QM_CQ_CTL_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_CTL_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_CTL_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_CTL_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_CTL_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7)
+									<< 2;
+	mask = 1U << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) +
+								PROT_BITS_OFFS;
+
+	word_offset = ((mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS)
+								>> 7) << 2;
+
+	mask = 1U << ((mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC7_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC7_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC7_QM_CP_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC7_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC7_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC7_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_DBG_0_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_DBG_0_1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC7_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC7_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC7_QM_CP_DBG_0_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_DBG_0_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_DBG_0_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC7_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC7_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC7_QM_ARB_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC7_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC7_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7)
+									<< 2;
+	mask = 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) +
+			PROT_BITS_OFFS;
+	word_offset = ((mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS)
+								>> 7) << 2;
+	mask = 1U << ((mmTPC7_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC7_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC7_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7)	<< 2;
+	mask = 1U << ((mmTPC7_QM_ARB_STATE_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MSG_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_ERR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_ERR_MSG_EN & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_ERR_STS_DRP & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC7_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC7_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS)	>> 7)
+									<< 2;
+	mask = 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CGM_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CGM_STS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CGM_CFG1 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC7_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC7_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC7_QM_LOCAL_RANGE_BASE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_GLBL_AXCACHE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_IND_GW_APB_CFG & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_IND_GW_APB_WDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_IND_GW_APB_RDATA & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_IND_GW_APB_STATUS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_QM_GLBL_ERR_WDATA & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC7_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC7_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7)
+									<< 2;
+	mask = 1U << ((mmTPC7_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC7_CFG_ROUND_CSR & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC7_CFG_ROUND_CSR & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC7_CFG_ROUND_CSR & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC7_CFG_PROT & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC7_CFG_PROT & PROT_BITS_OFFS) >> 7) << 2;
+	mask = 1U << ((mmTPC7_CFG_PROT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_CFG_VFLAGS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_CFG_SFLAGS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_CFG_TPC_STALL & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_CFG_ICACHE_BASE_ADDERESS_HIGH & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_CFG_RD_RATE_LIMIT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_CFG_WR_RATE_LIMIT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_CFG_MSS_CONFIG & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_CFG_TPC_INTR_CAUSE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_CFG_TPC_INTR_MASK & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_CFG_WQ_CREDITS & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_CFG_ARUSER_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_CFG_ARUSER_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_CFG_AWUSER_LO & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_CFG_AWUSER_HI & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_CFG_OPCODE_EXEC & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
+	pb_addr = (mmTPC7_CFG_TSB_CFG_MAX_SIZE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC7_CFG_TSB_CFG_MAX_SIZE & PROT_BITS_OFFS) >> 7)
+									<< 2;
+	mask = 1U << ((mmTPC7_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_CFG_DBGMEM_ADD & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_CFG_DBGMEM_DATA_WR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_CFG_DBGMEM_DATA_RD & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_CFG_DBGMEM_CTRL & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_CFG_DBGMEM_RC & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_CFG_FUNC_MBIST_PAT & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2);
+	mask |= 1U << ((mmTPC7_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+}
+
+/**
+ * gaudi_init_protection_bits - Initialize protection bits of specific registers
+ *
+ * @hdev: pointer to hl_device structure
+ *
+ * All protection bits are 1 by default, means not protected. Need to set to 0
+ * each bit that belongs to a protected register.
+ *
+ */
+static void gaudi_init_protection_bits(struct hl_device *hdev)
+{
+	/*
+	 * In each 4K block of registers, the last 128 bytes are protection
+	 * bits - total of 1024 bits, one for each register. Each bit is related
+	 * to a specific register, by the order of the registers.
+	 * So in order to calculate the bit that is related to a given register,
+	 * we need to calculate its word offset and then the exact bit inside
+	 * the word (which is 4 bytes).
+	 *
+	 * Register address:
+	 *
+	 * 31                 12 11           7   6             2  1      0
+	 * -----------------------------------------------------------------
+	 * |      Don't         |    word       |  bit location  |    0    |
+	 * |      care          |   offset      |  inside word   |         |
+	 * -----------------------------------------------------------------
+	 *
+	 * Bits 7-11 represents the word offset inside the 128 bytes.
+	 * Bits 2-6 represents the bit location inside the word.
+	 *
+	 * When a bit is cleared, it means the register it represents can only
+	 * be accessed by a secured entity. When the bit is set, any entity can
+	 * access the register.
+	 *
+	 * The last 4 bytes in the block of the PBs control the security of
+	 * the PBs themselves, so they always need to be configured to be
+	 * secured
+	 */
+
+	if (!hdev->asic_prop.fw_security_enabled) {
+		gaudi_pb_set_block(hdev, mmIF_E_PLL_BASE);
+		gaudi_pb_set_block(hdev, mmMESH_W_PLL_BASE);
+		gaudi_pb_set_block(hdev, mmSRAM_W_PLL_BASE);
+		gaudi_pb_set_block(hdev, mmMESH_E_PLL_BASE);
+		gaudi_pb_set_block(hdev, mmSRAM_E_PLL_BASE);
+	}
+
+	gaudi_init_dma_protection_bits(hdev);
+
+	gaudi_init_mme_protection_bits(hdev);
+
+	gaudi_init_nic_protection_bits(hdev);
+
+	gaudi_init_tpc_protection_bits(hdev);
+}
+
+static void gaudi_init_range_registers_lbw(struct hl_device *hdev)
+{
+	u32 lbw_rng_start[GAUDI_NUMBER_OF_LBW_RANGES];
+	u32 lbw_rng_end[GAUDI_NUMBER_OF_LBW_RANGES];
+	int i, j;
+
+	lbw_rng_start[0]  = (0xFC0E8000 & 0x3FFFFFF) - 1; /* 0x000E7FFF */
+	lbw_rng_end[0]    = (0xFC11FFFF & 0x3FFFFFF) + 1; /* 0x00120000 */
+
+	lbw_rng_start[1]  = (0xFC1E8000 & 0x3FFFFFF) - 1; /* 0x001E7FFF */
+	lbw_rng_end[1]    = (0xFC48FFFF & 0x3FFFFFF) + 1; /* 0x00490000 */
+
+	lbw_rng_start[2]  = (0xFC600000 & 0x3FFFFFF) - 1; /* 0x005FFFFF */
+	lbw_rng_end[2]    = (0xFCC48FFF & 0x3FFFFFF) + 1; /* 0x00C49000 */
+
+	lbw_rng_start[3]  = (0xFCC4A000 & 0x3FFFFFF) - 1; /* 0x00C49FFF */
+	lbw_rng_end[3]    = (0xFCCDFFFF & 0x3FFFFFF) + 1; /* 0x00CE0000 */
+
+	lbw_rng_start[4]  = (0xFCCE4000 & 0x3FFFFFF) - 1; /* 0x00CE3FFF */
+	lbw_rng_end[4]    = (0xFCD1FFFF & 0x3FFFFFF) + 1; /* 0x00D20000 */
+
+	lbw_rng_start[5]  = (0xFCD24000 & 0x3FFFFFF) - 1; /* 0x00D23FFF */
+	lbw_rng_end[5]    = (0xFCD5FFFF & 0x3FFFFFF) + 1; /* 0x00D60000 */
+
+	lbw_rng_start[6]  = (0xFCD64000 & 0x3FFFFFF) - 1; /* 0x00D63FFF */
+	lbw_rng_end[6]    = (0xFCD9FFFF & 0x3FFFFFF) + 1; /* 0x00DA0000 */
+
+	lbw_rng_start[7]  = (0xFCDA4000 & 0x3FFFFFF) - 1; /* 0x00DA3FFF */
+	lbw_rng_end[7]    = (0xFCDDFFFF & 0x3FFFFFF) + 1; /* 0x00DE0000 */
+
+	lbw_rng_start[8]  = (0xFCDE4000 & 0x3FFFFFF) - 1; /* 0x00DE3FFF */
+	lbw_rng_end[8]    = (0xFCE05FFF & 0x3FFFFFF) + 1; /* 0x00E06000 */
+
+	lbw_rng_start[9]  = (0xFCFC9000 & 0x3FFFFFF) - 1; /* 0x00FC8FFF */
+	lbw_rng_end[9]    = (0xFFFFFFFE & 0x3FFFFFF) + 1; /* 0x03FFFFFF */
+
+	for (i = 0 ; i < GAUDI_NUMBER_OF_LBW_RR_REGS ; i++) {
+		WREG32(gaudi_rr_lbw_hit_aw_regs[i],
+				(1 << GAUDI_NUMBER_OF_LBW_RANGES) - 1);
+		WREG32(gaudi_rr_lbw_hit_ar_regs[i],
+				(1 << GAUDI_NUMBER_OF_LBW_RANGES) - 1);
+	}
+
+	for (i = 0 ; i < GAUDI_NUMBER_OF_LBW_RR_REGS ; i++)
+		for (j = 0 ; j < GAUDI_NUMBER_OF_LBW_RANGES ; j++) {
+			WREG32(gaudi_rr_lbw_min_aw_regs[i] + (j << 2),
+							lbw_rng_start[j]);
+
+			WREG32(gaudi_rr_lbw_min_ar_regs[i] + (j << 2),
+							lbw_rng_start[j]);
+
+			WREG32(gaudi_rr_lbw_max_aw_regs[i] + (j << 2),
+							lbw_rng_end[j]);
+
+			WREG32(gaudi_rr_lbw_max_ar_regs[i] + (j << 2),
+							lbw_rng_end[j]);
+		}
+}
+
+static void gaudi_init_range_registers_hbw(struct hl_device *hdev)
+{
+	struct gaudi_device *gaudi = hdev->asic_specific;
+
+	u32 dram_addr_lo = lower_32_bits(DRAM_PHYS_BASE);
+	u32 dram_addr_hi = upper_32_bits(DRAM_PHYS_BASE);
+
+	u32 sram_addr_lo = lower_32_bits(SRAM_BASE_ADDR);
+	u32 sram_addr_hi = upper_32_bits(SRAM_BASE_ADDR);
+
+	u32 scratch_addr_lo = lower_32_bits(PSOC_SCRATCHPAD_ADDR);
+	u32 scratch_addr_hi = upper_32_bits(PSOC_SCRATCHPAD_ADDR);
+
+	u32 pcie_fw_addr_lo = lower_32_bits(PCIE_FW_SRAM_ADDR);
+	u32 pcie_fw_addr_hi = upper_32_bits(PCIE_FW_SRAM_ADDR);
+
+	u32 spi_addr_lo = lower_32_bits(SPI_FLASH_BASE_ADDR);
+	u32 spi_addr_hi = upper_32_bits(SPI_FLASH_BASE_ADDR);
+
+	int i;
+
+	/* Configure HBW RR:
+	 * 1st range is the DRAM (first 512MB)
+	 * 2nd range is the 1st 128 bytes in SRAM (for tensor DMA). This area
+	 * is defined as read-only for user
+	 * 3rd range is the PSOC scratch-pad
+	 * 4th range is the PCIe F/W SRAM area
+	 * 5th range is the SPI FLASH area
+	 * 6th range is the host
+	 */
+
+	for (i = 0 ; i < GAUDI_NUMBER_OF_HBW_RR_REGS ; i++) {
+		WREG32(gaudi_rr_hbw_hit_aw_regs[i], 0x1F);
+		WREG32(gaudi_rr_hbw_hit_ar_regs[i], 0x1D);
+	}
+
+	for (i = 0 ; i < GAUDI_NUMBER_OF_HBW_RR_REGS ; i++) {
+		WREG32(gaudi_rr_hbw_base_low_aw_regs[i], dram_addr_lo);
+		WREG32(gaudi_rr_hbw_base_low_ar_regs[i], dram_addr_lo);
+
+		WREG32(gaudi_rr_hbw_base_high_aw_regs[i], dram_addr_hi);
+		WREG32(gaudi_rr_hbw_base_high_ar_regs[i], dram_addr_hi);
+
+		WREG32(gaudi_rr_hbw_mask_low_aw_regs[i], 0xE0000000);
+		WREG32(gaudi_rr_hbw_mask_low_ar_regs[i], 0xE0000000);
+
+		WREG32(gaudi_rr_hbw_mask_high_aw_regs[i], 0x3FFFF);
+		WREG32(gaudi_rr_hbw_mask_high_ar_regs[i], 0x3FFFF);
+
+		WREG32(gaudi_rr_hbw_base_low_aw_regs[i] + 4, sram_addr_lo);
+		WREG32(gaudi_rr_hbw_base_high_aw_regs[i] + 4, sram_addr_hi);
+		WREG32(gaudi_rr_hbw_mask_low_aw_regs[i] + 4, 0xFFFFFF80);
+		WREG32(gaudi_rr_hbw_mask_high_aw_regs[i] + 4, 0x3FFFF);
+
+		WREG32(gaudi_rr_hbw_base_low_aw_regs[i] + 8, scratch_addr_lo);
+		WREG32(gaudi_rr_hbw_base_low_ar_regs[i] + 8, scratch_addr_lo);
+
+		WREG32(gaudi_rr_hbw_base_high_aw_regs[i] + 8, scratch_addr_hi);
+		WREG32(gaudi_rr_hbw_base_high_ar_regs[i] + 8, scratch_addr_hi);
+
+		WREG32(gaudi_rr_hbw_mask_low_aw_regs[i] + 8, 0xFFFF0000);
+		WREG32(gaudi_rr_hbw_mask_low_ar_regs[i] + 8, 0xFFFF0000);
+
+		WREG32(gaudi_rr_hbw_mask_high_aw_regs[i] + 8, 0x3FFFF);
+		WREG32(gaudi_rr_hbw_mask_high_ar_regs[i] + 8, 0x3FFFF);
+
+		WREG32(gaudi_rr_hbw_base_low_aw_regs[i] + 12, pcie_fw_addr_lo);
+		WREG32(gaudi_rr_hbw_base_low_ar_regs[i] + 12, pcie_fw_addr_lo);
+
+		WREG32(gaudi_rr_hbw_base_high_aw_regs[i] + 12, pcie_fw_addr_hi);
+		WREG32(gaudi_rr_hbw_base_high_ar_regs[i] + 12, pcie_fw_addr_hi);
+
+		WREG32(gaudi_rr_hbw_mask_low_aw_regs[i] + 12, 0xFFFF8000);
+		WREG32(gaudi_rr_hbw_mask_low_ar_regs[i] + 12, 0xFFFF8000);
+
+		WREG32(gaudi_rr_hbw_mask_high_aw_regs[i] + 12, 0x3FFFF);
+		WREG32(gaudi_rr_hbw_mask_high_ar_regs[i] + 12, 0x3FFFF);
+
+		WREG32(gaudi_rr_hbw_base_low_aw_regs[i] + 16, spi_addr_lo);
+		WREG32(gaudi_rr_hbw_base_low_ar_regs[i] + 16, spi_addr_lo);
+
+		WREG32(gaudi_rr_hbw_base_high_aw_regs[i] + 16, spi_addr_hi);
+		WREG32(gaudi_rr_hbw_base_high_ar_regs[i] + 16, spi_addr_hi);
+
+		WREG32(gaudi_rr_hbw_mask_low_aw_regs[i] + 16, 0xFE000000);
+		WREG32(gaudi_rr_hbw_mask_low_ar_regs[i] + 16, 0xFE000000);
+
+		WREG32(gaudi_rr_hbw_mask_high_aw_regs[i] + 16, 0x3FFFF);
+		WREG32(gaudi_rr_hbw_mask_high_ar_regs[i] + 16, 0x3FFFF);
+
+		if (gaudi->hw_cap_initialized & HW_CAP_MMU)
+			continue;
+
+		/* Protect HOST */
+		WREG32(gaudi_rr_hbw_base_low_aw_regs[i] + 20, 0);
+		WREG32(gaudi_rr_hbw_base_low_ar_regs[i] + 20, 0);
+
+		WREG32(gaudi_rr_hbw_base_high_aw_regs[i] + 20, 0);
+		WREG32(gaudi_rr_hbw_base_high_ar_regs[i] + 20, 0);
+
+		WREG32(gaudi_rr_hbw_mask_low_aw_regs[i] + 20, 0);
+		WREG32(gaudi_rr_hbw_mask_low_ar_regs[i] + 20, 0);
+
+		WREG32(gaudi_rr_hbw_mask_high_aw_regs[i] + 20, 0xFFF80);
+		WREG32(gaudi_rr_hbw_mask_high_ar_regs[i] + 20, 0xFFF80);
+	}
+}
+
+/**
+ * gaudi_init_security - Initialize security model
+ *
+ * @hdev: pointer to hl_device structure
+ *
+ * Initialize the security model of the device
+ * That includes range registers and protection bit per register
+ *
+ */
+void gaudi_init_security(struct hl_device *hdev)
+{
+	/* Due to H/W errata GAUDI0500, need to override default security
+	 * property configuration of MME SBAB and ACC to be non-privileged and
+	 * non-secured
+	 */
+	if (!hdev->asic_prop.fw_security_enabled) {
+		WREG32(mmMME0_SBAB_PROT, 0x2);
+		WREG32(mmMME0_ACC_PROT, 0x2);
+		WREG32(mmMME1_SBAB_PROT, 0x2);
+		WREG32(mmMME1_ACC_PROT, 0x2);
+		WREG32(mmMME2_SBAB_PROT, 0x2);
+		WREG32(mmMME2_ACC_PROT, 0x2);
+		WREG32(mmMME3_SBAB_PROT, 0x2);
+		WREG32(mmMME3_ACC_PROT, 0x2);
+
+		/*
+		 * On RAZWI, 0 will be returned from RR and 0xBABA0BAD from PB
+		 */
+		WREG32(0xC01B28, 0x1);
+	}
+
+	gaudi_init_range_registers_lbw(hdev);
+
+	gaudi_init_range_registers_hbw(hdev);
+
+	gaudi_init_protection_bits(hdev);
+}
+
+void gaudi_ack_protection_bits_errors(struct hl_device *hdev)
+{
+
+}
diff --git a/drivers/accel/habanalabs/gaudi2/Makefile b/drivers/accel/habanalabs/gaudi2/Makefile
new file mode 100644
index 000000000000..1e047883ba74
--- /dev/null
+++ b/drivers/accel/habanalabs/gaudi2/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+HL_GAUDI2_FILES := gaudi2/gaudi2.o gaudi2/gaudi2_security.o \
+		gaudi2/gaudi2_coresight.o
diff --git a/drivers/accel/habanalabs/gaudi2/gaudi2.c b/drivers/accel/habanalabs/gaudi2/gaudi2.c
new file mode 100644
index 000000000000..b8c0689dba64
--- /dev/null
+++ b/drivers/accel/habanalabs/gaudi2/gaudi2.c
@@ -0,0 +1,12008 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Copyright 2020-2022 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ */
+
+#include "gaudi2P.h"
+#include "gaudi2_masks.h"
+#include "../include/gaudi2/gaudi2_special_blocks.h"
+#include "../include/hw_ip/mmu/mmu_general.h"
+#include "../include/hw_ip/mmu/mmu_v2_0.h"
+#include "../include/gaudi2/gaudi2_packets.h"
+#include "../include/gaudi2/gaudi2_reg_map.h"
+#include "../include/gaudi2/gaudi2_async_ids_map_extended.h"
+#include "../include/gaudi2/arc/gaudi2_arc_common_packets.h"
+
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/hwmon.h>
+#include <linux/iommu.h>
+
+#define GAUDI2_DMA_POOL_BLK_SIZE		SZ_256		/* 256 bytes */
+
+#define GAUDI2_RESET_TIMEOUT_MSEC		2000		/* 2000ms */
+
+#define GAUDI2_RESET_POLL_TIMEOUT_USEC		500000		/* 500ms */
+#define GAUDI2_PLDM_HRESET_TIMEOUT_MSEC		25000		/* 25s */
+#define GAUDI2_PLDM_SRESET_TIMEOUT_MSEC		25000		/* 25s */
+#define GAUDI2_PLDM_RESET_POLL_TIMEOUT_USEC	3000000		/* 3s */
+#define GAUDI2_RESET_POLL_CNT			3
+#define GAUDI2_RESET_WAIT_MSEC			1		/* 1ms */
+#define GAUDI2_CPU_RESET_WAIT_MSEC		100		/* 100ms */
+#define GAUDI2_PLDM_RESET_WAIT_MSEC		1000		/* 1s */
+#define GAUDI2_CB_POOL_CB_CNT			512
+#define GAUDI2_CB_POOL_CB_SIZE			SZ_128K		/* 128KB */
+#define GAUDI2_MSG_TO_CPU_TIMEOUT_USEC		4000000		/* 4s */
+#define GAUDI2_WAIT_FOR_BL_TIMEOUT_USEC		25000000	/* 25s */
+#define GAUDI2_TEST_QUEUE_WAIT_USEC		100000		/* 100ms */
+#define GAUDI2_PLDM_TEST_QUEUE_WAIT_USEC	1000000		/* 1s */
+
+#define GAUDI2_ALLOC_CPU_MEM_RETRY_CNT		3
+
+/*
+ * since the code already has built-in support for binning of up to MAX_FAULTY_TPCS TPCs
+ * and the code relies on that value (for array size etc..) we define another value
+ * for MAX faulty TPCs which reflects the cluster binning requirements
+ */
+#define MAX_CLUSTER_BINNING_FAULTY_TPCS		1
+#define MAX_FAULTY_XBARS			1
+#define MAX_FAULTY_EDMAS			1
+#define MAX_FAULTY_DECODERS			1
+
+#define GAUDI2_TPC_FULL_MASK			0x1FFFFFF
+#define GAUDI2_HIF_HMMU_FULL_MASK		0xFFFF
+#define GAUDI2_DECODER_FULL_MASK		0x3FF
+
+#define GAUDI2_NA_EVENT_CAUSE			0xFF
+#define GAUDI2_NUM_OF_QM_ERR_CAUSE		18
+#define GAUDI2_NUM_OF_LOWER_QM_ERR_CAUSE	25
+#define GAUDI2_NUM_OF_QM_ARB_ERR_CAUSE		3
+#define GAUDI2_NUM_OF_ARC_SEI_ERR_CAUSE		14
+#define GAUDI2_NUM_OF_CPU_SEI_ERR_CAUSE		3
+#define GAUDI2_NUM_OF_QM_SEI_ERR_CAUSE		2
+#define GAUDI2_NUM_OF_ROT_ERR_CAUSE		22
+#define GAUDI2_NUM_OF_TPC_INTR_CAUSE		31
+#define GAUDI2_NUM_OF_DEC_ERR_CAUSE		25
+#define GAUDI2_NUM_OF_MME_ERR_CAUSE		16
+#define GAUDI2_NUM_OF_MME_WAP_ERR_CAUSE		7
+#define GAUDI2_NUM_OF_DMA_CORE_INTR_CAUSE	8
+#define GAUDI2_NUM_OF_MMU_SPI_SEI_CAUSE		19
+#define GAUDI2_NUM_OF_HBM_SEI_CAUSE		9
+#define GAUDI2_NUM_OF_SM_SEI_ERR_CAUSE		3
+#define GAUDI2_NUM_OF_PCIE_ADDR_DEC_ERR_CAUSE	3
+#define GAUDI2_NUM_OF_PMMU_FATAL_ERR_CAUSE	2
+#define GAUDI2_NUM_OF_HIF_FATAL_ERR_CAUSE	2
+#define GAUDI2_NUM_OF_AXI_DRAIN_ERR_CAUSE	2
+#define GAUDI2_NUM_OF_HBM_MC_SPI_CAUSE		5
+
+#define GAUDI2_MMU_CACHE_INV_TIMEOUT_USEC	(MMU_CONFIG_TIMEOUT_USEC * 10)
+#define GAUDI2_PLDM_MMU_TIMEOUT_USEC		(MMU_CONFIG_TIMEOUT_USEC * 200)
+#define GAUDI2_ARB_WDT_TIMEOUT			(0x1000000)
+
+#define GAUDI2_VDEC_TIMEOUT_USEC		10000		/* 10ms */
+#define GAUDI2_PLDM_VDEC_TIMEOUT_USEC		(GAUDI2_VDEC_TIMEOUT_USEC * 100)
+
+#define KDMA_TIMEOUT_USEC			USEC_PER_SEC
+
+#define IS_DMA_IDLE(dma_core_sts0)	\
+	(!((dma_core_sts0) & (DCORE0_EDMA0_CORE_STS0_BUSY_MASK)))
+
+#define IS_DMA_HALTED(dma_core_sts1)	\
+	((dma_core_sts1) & (DCORE0_EDMA0_CORE_STS1_IS_HALT_MASK))
+
+#define IS_MME_IDLE(mme_arch_sts) (((mme_arch_sts) & MME_ARCH_IDLE_MASK) == MME_ARCH_IDLE_MASK)
+
+#define IS_TPC_IDLE(tpc_cfg_sts) (((tpc_cfg_sts) & (TPC_IDLE_MASK)) == (TPC_IDLE_MASK))
+
+#define IS_QM_IDLE(qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts) \
+	((((qm_glbl_sts0) & (QM_IDLE_MASK)) == (QM_IDLE_MASK)) && \
+	(((qm_glbl_sts1) & (QM_ARC_IDLE_MASK)) == (QM_ARC_IDLE_MASK)) && \
+	(((qm_cgm_sts) & (CGM_IDLE_MASK)) == (CGM_IDLE_MASK)))
+
+#define PCIE_DEC_EN_MASK			0x300
+#define DEC_WORK_STATE_IDLE			0
+#define DEC_WORK_STATE_PEND			3
+#define IS_DEC_IDLE(dec_swreg15) \
+	(((dec_swreg15) & DCORE0_DEC0_CMD_SWREG15_SW_WORK_STATE_MASK) == DEC_WORK_STATE_IDLE || \
+	((dec_swreg15) & DCORE0_DEC0_CMD_SWREG15_SW_WORK_STATE_MASK) ==  DEC_WORK_STATE_PEND)
+
+/* HBM MMU address scrambling parameters */
+#define GAUDI2_HBM_MMU_SCRM_MEM_SIZE		SZ_8M
+#define GAUDI2_HBM_MMU_SCRM_DIV_SHIFT		26
+#define GAUDI2_HBM_MMU_SCRM_MOD_SHIFT		0
+#define GAUDI2_HBM_MMU_SCRM_ADDRESS_MASK	DRAM_VA_HINT_MASK
+#define GAUDI2_COMPENSATE_TLB_PAGE_SIZE_FACTOR	16
+#define MMU_RANGE_INV_VA_LSB_SHIFT		12
+#define MMU_RANGE_INV_VA_MSB_SHIFT		44
+#define MMU_RANGE_INV_EN_SHIFT			0
+#define MMU_RANGE_INV_ASID_EN_SHIFT		1
+#define MMU_RANGE_INV_ASID_SHIFT		2
+
+/* The last SPI_SEI cause bit, "burst_fifo_full", is expected to be triggered in PMMU because it has
+ * a 2 entries FIFO, and hence it is not enabled for it.
+ */
+#define GAUDI2_PMMU_SPI_SEI_ENABLE_MASK		GENMASK(GAUDI2_NUM_OF_MMU_SPI_SEI_CAUSE - 2, 0)
+#define GAUDI2_HMMU_SPI_SEI_ENABLE_MASK		GENMASK(GAUDI2_NUM_OF_MMU_SPI_SEI_CAUSE - 1, 0)
+
+#define GAUDI2_MAX_STRING_LEN			64
+
+#define GAUDI2_VDEC_MSIX_ENTRIES		(GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM - \
+							GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM + 1)
+
+#define ENGINE_ID_DCORE_OFFSET (GAUDI2_DCORE1_ENGINE_ID_EDMA_0 - GAUDI2_DCORE0_ENGINE_ID_EDMA_0)
+
+/* RAZWI initiator coordinates */
+#define RAZWI_GET_AXUSER_XY(x) \
+	((x & 0xF8001FF0) >> 4)
+
+#define RAZWI_GET_AXUSER_LOW_XY(x) \
+	((x & 0x00001FF0) >> 4)
+
+#define RAZWI_INITIATOR_AXUER_L_X_SHIFT		0
+#define RAZWI_INITIATOR_AXUER_L_X_MASK		0x1F
+#define RAZWI_INITIATOR_AXUER_L_Y_SHIFT		5
+#define RAZWI_INITIATOR_AXUER_L_Y_MASK		0xF
+
+#define RAZWI_INITIATOR_AXUER_H_X_SHIFT		23
+#define RAZWI_INITIATOR_AXUER_H_X_MASK		0x1F
+
+#define RAZWI_INITIATOR_ID_X_Y_LOW(x, y) \
+	((((y) & RAZWI_INITIATOR_AXUER_L_Y_MASK) << RAZWI_INITIATOR_AXUER_L_Y_SHIFT) | \
+		(((x) & RAZWI_INITIATOR_AXUER_L_X_MASK) << RAZWI_INITIATOR_AXUER_L_X_SHIFT))
+
+#define RAZWI_INITIATOR_ID_X_HIGH(x) \
+		(((x) & RAZWI_INITIATOR_AXUER_H_X_MASK) << RAZWI_INITIATOR_AXUER_H_X_SHIFT)
+
+#define RAZWI_INITIATOR_ID_X_Y(xl, yl, xh) \
+	(RAZWI_INITIATOR_ID_X_Y_LOW(xl, yl) | RAZWI_INITIATOR_ID_X_HIGH(xh))
+
+#define PSOC_RAZWI_ENG_STR_SIZE			128
+#define PSOC_RAZWI_MAX_ENG_PER_RTR		5
+
+/* HW scrambles only bits 0-25 */
+#define HW_UNSCRAMBLED_BITS_MASK		GENMASK_ULL(63, 26)
+
+#define GAUDI2_GLBL_ERR_MAX_CAUSE_NUM		17
+
+struct gaudi2_razwi_info {
+	u32 axuser_xy;
+	u32 rtr_ctrl;
+	u16 eng_id;
+	char *eng_name;
+};
+
+static struct gaudi2_razwi_info common_razwi_info[] = {
+		{RAZWI_INITIATOR_ID_X_Y(2, 4, 0), mmDCORE0_RTR0_CTRL_BASE,
+				GAUDI2_DCORE0_ENGINE_ID_DEC_0, "DEC0"},
+		{RAZWI_INITIATOR_ID_X_Y(2, 4, 4), mmDCORE0_RTR0_CTRL_BASE,
+				GAUDI2_DCORE0_ENGINE_ID_DEC_1, "DEC1"},
+		{RAZWI_INITIATOR_ID_X_Y(17, 4, 18), mmDCORE1_RTR7_CTRL_BASE,
+				GAUDI2_DCORE1_ENGINE_ID_DEC_0, "DEC2"},
+		{RAZWI_INITIATOR_ID_X_Y(17, 4, 14), mmDCORE1_RTR7_CTRL_BASE,
+				GAUDI2_DCORE1_ENGINE_ID_DEC_1, "DEC3"},
+		{RAZWI_INITIATOR_ID_X_Y(2, 11, 0), mmDCORE2_RTR0_CTRL_BASE,
+				GAUDI2_DCORE2_ENGINE_ID_DEC_0, "DEC4"},
+		{RAZWI_INITIATOR_ID_X_Y(2, 11, 4), mmDCORE2_RTR0_CTRL_BASE,
+				GAUDI2_DCORE2_ENGINE_ID_DEC_1, "DEC5"},
+		{RAZWI_INITIATOR_ID_X_Y(17, 11, 18), mmDCORE3_RTR7_CTRL_BASE,
+				GAUDI2_DCORE3_ENGINE_ID_DEC_0, "DEC6"},
+		{RAZWI_INITIATOR_ID_X_Y(17, 11, 14), mmDCORE3_RTR7_CTRL_BASE,
+				GAUDI2_DCORE3_ENGINE_ID_DEC_1, "DEC7"},
+		{RAZWI_INITIATOR_ID_X_Y(2, 4, 6), mmDCORE0_RTR0_CTRL_BASE,
+				GAUDI2_PCIE_ENGINE_ID_DEC_0, "DEC8"},
+		{RAZWI_INITIATOR_ID_X_Y(2, 4, 7), mmDCORE0_RTR0_CTRL_BASE,
+				GAUDI2_PCIE_ENGINE_ID_DEC_0, "DEC9"},
+		{RAZWI_INITIATOR_ID_X_Y(3, 4, 2), mmDCORE0_RTR1_CTRL_BASE,
+				GAUDI2_DCORE0_ENGINE_ID_TPC_0, "TPC0"},
+		{RAZWI_INITIATOR_ID_X_Y(3, 4, 4), mmDCORE0_RTR1_CTRL_BASE,
+				GAUDI2_DCORE0_ENGINE_ID_TPC_1, "TPC1"},
+		{RAZWI_INITIATOR_ID_X_Y(4, 4, 2), mmDCORE0_RTR2_CTRL_BASE,
+				GAUDI2_DCORE0_ENGINE_ID_TPC_2, "TPC2"},
+		{RAZWI_INITIATOR_ID_X_Y(4, 4, 4), mmDCORE0_RTR2_CTRL_BASE,
+				GAUDI2_DCORE0_ENGINE_ID_TPC_3, "TPC3"},
+		{RAZWI_INITIATOR_ID_X_Y(5, 4, 2), mmDCORE0_RTR3_CTRL_BASE,
+				GAUDI2_DCORE0_ENGINE_ID_TPC_4, "TPC4"},
+		{RAZWI_INITIATOR_ID_X_Y(5, 4, 4), mmDCORE0_RTR3_CTRL_BASE,
+				GAUDI2_DCORE0_ENGINE_ID_TPC_5, "TPC5"},
+		{RAZWI_INITIATOR_ID_X_Y(16, 4, 14), mmDCORE1_RTR6_CTRL_BASE,
+				GAUDI2_DCORE1_ENGINE_ID_TPC_0, "TPC6"},
+		{RAZWI_INITIATOR_ID_X_Y(16, 4, 16), mmDCORE1_RTR6_CTRL_BASE,
+				GAUDI2_DCORE1_ENGINE_ID_TPC_1, "TPC7"},
+		{RAZWI_INITIATOR_ID_X_Y(15, 4, 14), mmDCORE1_RTR5_CTRL_BASE,
+				GAUDI2_DCORE1_ENGINE_ID_TPC_2, "TPC8"},
+		{RAZWI_INITIATOR_ID_X_Y(15, 4, 16), mmDCORE1_RTR5_CTRL_BASE,
+				GAUDI2_DCORE1_ENGINE_ID_TPC_3, "TPC9"},
+		{RAZWI_INITIATOR_ID_X_Y(14, 4, 14), mmDCORE1_RTR4_CTRL_BASE,
+				GAUDI2_DCORE1_ENGINE_ID_TPC_4, "TPC10"},
+		{RAZWI_INITIATOR_ID_X_Y(14, 4, 16), mmDCORE1_RTR4_CTRL_BASE,
+				GAUDI2_DCORE1_ENGINE_ID_TPC_5, "TPC11"},
+		{RAZWI_INITIATOR_ID_X_Y(5, 11, 2), mmDCORE2_RTR3_CTRL_BASE,
+				GAUDI2_DCORE2_ENGINE_ID_TPC_0, "TPC12"},
+		{RAZWI_INITIATOR_ID_X_Y(5, 11, 4), mmDCORE2_RTR3_CTRL_BASE,
+				GAUDI2_DCORE2_ENGINE_ID_TPC_1, "TPC13"},
+		{RAZWI_INITIATOR_ID_X_Y(4, 11, 2), mmDCORE2_RTR2_CTRL_BASE,
+				GAUDI2_DCORE2_ENGINE_ID_TPC_2, "TPC14"},
+		{RAZWI_INITIATOR_ID_X_Y(4, 11, 4), mmDCORE2_RTR2_CTRL_BASE,
+				GAUDI2_DCORE2_ENGINE_ID_TPC_3, "TPC15"},
+		{RAZWI_INITIATOR_ID_X_Y(3, 11, 2), mmDCORE2_RTR1_CTRL_BASE,
+				GAUDI2_DCORE2_ENGINE_ID_TPC_4, "TPC16"},
+		{RAZWI_INITIATOR_ID_X_Y(3, 11, 4), mmDCORE2_RTR1_CTRL_BASE,
+				GAUDI2_DCORE2_ENGINE_ID_TPC_5, "TPC17"},
+		{RAZWI_INITIATOR_ID_X_Y(14, 11, 14), mmDCORE3_RTR4_CTRL_BASE,
+				GAUDI2_DCORE3_ENGINE_ID_TPC_0, "TPC18"},
+		{RAZWI_INITIATOR_ID_X_Y(14, 11, 16), mmDCORE3_RTR4_CTRL_BASE,
+				GAUDI2_DCORE3_ENGINE_ID_TPC_1, "TPC19"},
+		{RAZWI_INITIATOR_ID_X_Y(15, 11, 14), mmDCORE3_RTR5_CTRL_BASE,
+				GAUDI2_DCORE3_ENGINE_ID_TPC_2, "TPC20"},
+		{RAZWI_INITIATOR_ID_X_Y(15, 11, 16), mmDCORE3_RTR5_CTRL_BASE,
+				GAUDI2_DCORE3_ENGINE_ID_TPC_3, "TPC21"},
+		{RAZWI_INITIATOR_ID_X_Y(16, 11, 14), mmDCORE3_RTR6_CTRL_BASE,
+				GAUDI2_DCORE3_ENGINE_ID_TPC_4, "TPC22"},
+		{RAZWI_INITIATOR_ID_X_Y(16, 11, 16), mmDCORE3_RTR6_CTRL_BASE,
+				GAUDI2_DCORE3_ENGINE_ID_TPC_5, "TPC23"},
+		{RAZWI_INITIATOR_ID_X_Y(2, 4, 2), mmDCORE0_RTR0_CTRL_BASE,
+				GAUDI2_DCORE3_ENGINE_ID_TPC_5, "TPC24"},
+		{RAZWI_INITIATOR_ID_X_Y(17, 4, 8), mmDCORE1_RTR7_CTRL_BASE,
+				GAUDI2_ENGINE_ID_NIC0_0, "NIC0"},
+		{RAZWI_INITIATOR_ID_X_Y(17, 4, 10), mmDCORE1_RTR7_CTRL_BASE,
+				GAUDI2_ENGINE_ID_NIC0_1, "NIC1"},
+		{RAZWI_INITIATOR_ID_X_Y(17, 4, 12), mmDCORE1_RTR7_CTRL_BASE,
+				GAUDI2_ENGINE_ID_NIC1_0, "NIC2"},
+		{RAZWI_INITIATOR_ID_X_Y(17, 4, 14), mmDCORE1_RTR7_CTRL_BASE,
+				GAUDI2_ENGINE_ID_NIC1_1, "NIC3"},
+		{RAZWI_INITIATOR_ID_X_Y(17, 4, 15), mmDCORE1_RTR7_CTRL_BASE,
+				GAUDI2_ENGINE_ID_NIC2_0, "NIC4"},
+		{RAZWI_INITIATOR_ID_X_Y(2, 11, 2), mmDCORE2_RTR0_CTRL_BASE,
+				GAUDI2_ENGINE_ID_NIC2_1, "NIC5"},
+		{RAZWI_INITIATOR_ID_X_Y(2, 11, 4), mmDCORE2_RTR0_CTRL_BASE,
+				GAUDI2_ENGINE_ID_NIC3_0, "NIC6"},
+		{RAZWI_INITIATOR_ID_X_Y(2, 11, 6), mmDCORE2_RTR0_CTRL_BASE,
+				GAUDI2_ENGINE_ID_NIC3_1, "NIC7"},
+		{RAZWI_INITIATOR_ID_X_Y(2, 11, 8), mmDCORE2_RTR0_CTRL_BASE,
+				GAUDI2_ENGINE_ID_NIC4_0, "NIC8"},
+		{RAZWI_INITIATOR_ID_X_Y(17, 11, 12), mmDCORE3_RTR7_CTRL_BASE,
+				GAUDI2_ENGINE_ID_NIC4_1, "NIC9"},
+		{RAZWI_INITIATOR_ID_X_Y(17, 11, 14), mmDCORE3_RTR7_CTRL_BASE,
+				GAUDI2_ENGINE_ID_NIC5_0, "NIC10"},
+		{RAZWI_INITIATOR_ID_X_Y(17, 11, 16), mmDCORE3_RTR7_CTRL_BASE,
+				GAUDI2_ENGINE_ID_NIC5_1, "NIC11"},
+		{RAZWI_INITIATOR_ID_X_Y(2, 4, 2), mmDCORE0_RTR0_CTRL_BASE,
+				GAUDI2_ENGINE_ID_PDMA_0, "PDMA0"},
+		{RAZWI_INITIATOR_ID_X_Y(2, 4, 3), mmDCORE0_RTR0_CTRL_BASE,
+				GAUDI2_ENGINE_ID_PDMA_1, "PDMA1"},
+		{RAZWI_INITIATOR_ID_X_Y(2, 4, 4), mmDCORE0_RTR0_CTRL_BASE,
+				GAUDI2_ENGINE_ID_SIZE, "PMMU"},
+		{RAZWI_INITIATOR_ID_X_Y(2, 4, 5), mmDCORE0_RTR0_CTRL_BASE,
+				GAUDI2_ENGINE_ID_SIZE, "PCIE"},
+		{RAZWI_INITIATOR_ID_X_Y(17, 4, 16), mmDCORE1_RTR7_CTRL_BASE,
+				GAUDI2_ENGINE_ID_ARC_FARM, "ARC_FARM"},
+		{RAZWI_INITIATOR_ID_X_Y(17, 4, 17), mmDCORE1_RTR7_CTRL_BASE,
+				GAUDI2_ENGINE_ID_KDMA, "KDMA"},
+		{RAZWI_INITIATOR_ID_X_Y(1, 5, 1), mmSFT0_HBW_RTR_IF1_RTR_CTRL_BASE,
+				GAUDI2_DCORE0_ENGINE_ID_EDMA_0, "EDMA0"},
+		{RAZWI_INITIATOR_ID_X_Y(1, 5, 1), mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE,
+				GAUDI2_DCORE0_ENGINE_ID_EDMA_1, "EDMA1"},
+		{RAZWI_INITIATOR_ID_X_Y(18, 5, 18), mmSFT1_HBW_RTR_IF1_RTR_CTRL_BASE,
+				GAUDI2_DCORE1_ENGINE_ID_EDMA_0, "EDMA2"},
+		{RAZWI_INITIATOR_ID_X_Y(18, 5, 18), mmSFT1_HBW_RTR_IF0_RTR_CTRL_BASE,
+				GAUDI2_DCORE1_ENGINE_ID_EDMA_1, "EDMA3"},
+		{RAZWI_INITIATOR_ID_X_Y(1, 10, 1), mmSFT2_HBW_RTR_IF0_RTR_CTRL_BASE,
+				GAUDI2_DCORE2_ENGINE_ID_EDMA_0, "EDMA4"},
+		{RAZWI_INITIATOR_ID_X_Y(1, 10, 1), mmSFT2_HBW_RTR_IF1_RTR_CTRL_BASE,
+				GAUDI2_DCORE2_ENGINE_ID_EDMA_1, "EDMA5"},
+		{RAZWI_INITIATOR_ID_X_Y(18, 10, 18), mmSFT2_HBW_RTR_IF0_RTR_CTRL_BASE,
+				GAUDI2_DCORE3_ENGINE_ID_EDMA_0, "EDMA6"},
+		{RAZWI_INITIATOR_ID_X_Y(18, 10, 18), mmSFT2_HBW_RTR_IF1_RTR_CTRL_BASE,
+				GAUDI2_DCORE3_ENGINE_ID_EDMA_1, "EDMA7"},
+		{RAZWI_INITIATOR_ID_X_Y(1, 5, 0), mmDCORE0_RTR0_CTRL_BASE,
+				GAUDI2_ENGINE_ID_SIZE, "HMMU0"},
+		{RAZWI_INITIATOR_ID_X_Y(18, 5, 19), mmDCORE1_RTR7_CTRL_BASE,
+				GAUDI2_ENGINE_ID_SIZE, "HMMU1"},
+		{RAZWI_INITIATOR_ID_X_Y(1, 5, 0), mmDCORE0_RTR0_CTRL_BASE,
+				GAUDI2_ENGINE_ID_SIZE, "HMMU2"},
+		{RAZWI_INITIATOR_ID_X_Y(18, 5, 19), mmDCORE1_RTR7_CTRL_BASE,
+				GAUDI2_ENGINE_ID_SIZE, "HMMU3"},
+		{RAZWI_INITIATOR_ID_X_Y(1, 5, 0), mmDCORE0_RTR0_CTRL_BASE,
+				GAUDI2_ENGINE_ID_SIZE, "HMMU4"},
+		{RAZWI_INITIATOR_ID_X_Y(18, 5, 19), mmDCORE1_RTR7_CTRL_BASE,
+				GAUDI2_ENGINE_ID_SIZE, "HMMU5"},
+		{RAZWI_INITIATOR_ID_X_Y(1, 5, 0), mmDCORE0_RTR0_CTRL_BASE,
+				GAUDI2_ENGINE_ID_SIZE, "HMMU6"},
+		{RAZWI_INITIATOR_ID_X_Y(18, 5, 19), mmDCORE1_RTR7_CTRL_BASE,
+				GAUDI2_ENGINE_ID_SIZE, "HMMU7"},
+		{RAZWI_INITIATOR_ID_X_Y(1, 10, 0), mmDCORE2_RTR0_CTRL_BASE,
+				GAUDI2_ENGINE_ID_SIZE, "HMMU8"},
+		{RAZWI_INITIATOR_ID_X_Y(18, 10, 19), mmDCORE3_RTR7_CTRL_BASE,
+				GAUDI2_ENGINE_ID_SIZE, "HMMU9"},
+		{RAZWI_INITIATOR_ID_X_Y(1, 10, 0), mmDCORE2_RTR0_CTRL_BASE,
+				GAUDI2_ENGINE_ID_SIZE, "HMMU10"},
+		{RAZWI_INITIATOR_ID_X_Y(18, 10, 19), mmDCORE3_RTR7_CTRL_BASE,
+				GAUDI2_ENGINE_ID_SIZE, "HMMU11"},
+		{RAZWI_INITIATOR_ID_X_Y(1, 10, 0), mmDCORE2_RTR0_CTRL_BASE,
+				GAUDI2_ENGINE_ID_SIZE, "HMMU12"},
+		{RAZWI_INITIATOR_ID_X_Y(18, 10, 19), mmDCORE3_RTR7_CTRL_BASE,
+				GAUDI2_ENGINE_ID_SIZE, "HMMU13"},
+		{RAZWI_INITIATOR_ID_X_Y(1, 10, 0), mmDCORE2_RTR0_CTRL_BASE,
+				GAUDI2_ENGINE_ID_SIZE, "HMMU14"},
+		{RAZWI_INITIATOR_ID_X_Y(18, 10, 19), mmDCORE3_RTR7_CTRL_BASE,
+				GAUDI2_ENGINE_ID_SIZE, "HMMU15"},
+		{RAZWI_INITIATOR_ID_X_Y(2, 11, 2), mmDCORE2_RTR0_CTRL_BASE,
+				GAUDI2_ENGINE_ID_ROT_0, "ROT0"},
+		{RAZWI_INITIATOR_ID_X_Y(17, 11, 16), mmDCORE3_RTR7_CTRL_BASE,
+				GAUDI2_ENGINE_ID_ROT_1, "ROT1"},
+		{RAZWI_INITIATOR_ID_X_Y(2, 11, 2), mmDCORE2_RTR0_CTRL_BASE,
+				GAUDI2_ENGINE_ID_PSOC, "CPU"},
+		{RAZWI_INITIATOR_ID_X_Y(17, 11, 11), mmDCORE3_RTR7_CTRL_BASE,
+				GAUDI2_ENGINE_ID_PSOC, "PSOC"}
+};
+
+static struct gaudi2_razwi_info mme_razwi_info[] = {
+		/* MME X high coordinate is N/A, hence using only low coordinates */
+		{RAZWI_INITIATOR_ID_X_Y_LOW(7, 4), mmDCORE0_RTR5_CTRL_BASE,
+				GAUDI2_DCORE0_ENGINE_ID_MME, "MME0_WAP0"},
+		{RAZWI_INITIATOR_ID_X_Y_LOW(9, 4), mmDCORE0_RTR7_CTRL_BASE,
+				GAUDI2_DCORE0_ENGINE_ID_MME, "MME0_WAP1"},
+		{RAZWI_INITIATOR_ID_X_Y_LOW(8, 4), mmDCORE0_RTR6_CTRL_BASE,
+				GAUDI2_DCORE0_ENGINE_ID_MME, "MME0_CTRL_WR"},
+		{RAZWI_INITIATOR_ID_X_Y_LOW(9, 4), mmDCORE0_RTR7_CTRL_BASE,
+				GAUDI2_DCORE0_ENGINE_ID_MME, "MME0_CTRL_RD"},
+		{RAZWI_INITIATOR_ID_X_Y_LOW(6, 4), mmDCORE0_RTR4_CTRL_BASE,
+				GAUDI2_DCORE0_ENGINE_ID_MME, "MME0_SBTE0"},
+		{RAZWI_INITIATOR_ID_X_Y_LOW(6, 4), mmDCORE0_RTR4_CTRL_BASE,
+				GAUDI2_DCORE0_ENGINE_ID_MME, "MME0_SBTE1"},
+		{RAZWI_INITIATOR_ID_X_Y_LOW(7, 4), mmDCORE0_RTR5_CTRL_BASE,
+				GAUDI2_DCORE0_ENGINE_ID_MME, "MME0_SBTE2"},
+		{RAZWI_INITIATOR_ID_X_Y_LOW(8, 4), mmDCORE0_RTR6_CTRL_BASE,
+				GAUDI2_DCORE0_ENGINE_ID_MME, "MME0_SBTE3"},
+		{RAZWI_INITIATOR_ID_X_Y_LOW(9, 4), mmDCORE0_RTR7_CTRL_BASE,
+				GAUDI2_DCORE0_ENGINE_ID_MME, "MME0_SBTE4"},
+		{RAZWI_INITIATOR_ID_X_Y_LOW(12, 4), mmDCORE1_RTR2_CTRL_BASE,
+				GAUDI2_DCORE1_ENGINE_ID_MME, "MME1_WAP0"},
+		{RAZWI_INITIATOR_ID_X_Y_LOW(10, 4), mmDCORE1_RTR0_CTRL_BASE,
+				GAUDI2_DCORE1_ENGINE_ID_MME, "MME1_WAP1"},
+		{RAZWI_INITIATOR_ID_X_Y_LOW(11, 4), mmDCORE1_RTR1_CTRL_BASE,
+				GAUDI2_DCORE1_ENGINE_ID_MME, "MME1_CTRL_WR"},
+		{RAZWI_INITIATOR_ID_X_Y_LOW(10, 4), mmDCORE1_RTR0_CTRL_BASE,
+				GAUDI2_DCORE1_ENGINE_ID_MME, "MME1_CTRL_RD"},
+		{RAZWI_INITIATOR_ID_X_Y_LOW(13, 4), mmDCORE1_RTR3_CTRL_BASE,
+				GAUDI2_DCORE1_ENGINE_ID_MME, "MME1_SBTE0"},
+		{RAZWI_INITIATOR_ID_X_Y_LOW(13, 4), mmDCORE1_RTR3_CTRL_BASE,
+				GAUDI2_DCORE1_ENGINE_ID_MME, "MME1_SBTE1"},
+		{RAZWI_INITIATOR_ID_X_Y_LOW(12, 4), mmDCORE1_RTR2_CTRL_BASE,
+				GAUDI2_DCORE1_ENGINE_ID_MME, "MME1_SBTE2"},
+		{RAZWI_INITIATOR_ID_X_Y_LOW(11, 4), mmDCORE1_RTR1_CTRL_BASE,
+				GAUDI2_DCORE1_ENGINE_ID_MME, "MME1_SBTE3"},
+		{RAZWI_INITIATOR_ID_X_Y_LOW(10, 4), mmDCORE1_RTR0_CTRL_BASE,
+				GAUDI2_DCORE1_ENGINE_ID_MME, "MME1_SBTE4"},
+		{RAZWI_INITIATOR_ID_X_Y_LOW(7, 11), mmDCORE2_RTR5_CTRL_BASE,
+				GAUDI2_DCORE2_ENGINE_ID_MME, "MME2_WAP0"},
+		{RAZWI_INITIATOR_ID_X_Y_LOW(9, 11), mmDCORE2_RTR7_CTRL_BASE,
+				GAUDI2_DCORE2_ENGINE_ID_MME, "MME2_WAP1"},
+		{RAZWI_INITIATOR_ID_X_Y_LOW(8, 11), mmDCORE2_RTR6_CTRL_BASE,
+				GAUDI2_DCORE2_ENGINE_ID_MME, "MME2_CTRL_WR"},
+		{RAZWI_INITIATOR_ID_X_Y_LOW(9, 11), mmDCORE2_RTR7_CTRL_BASE,
+				GAUDI2_DCORE2_ENGINE_ID_MME, "MME2_CTRL_RD"},
+		{RAZWI_INITIATOR_ID_X_Y_LOW(6, 11), mmDCORE2_RTR4_CTRL_BASE,
+				GAUDI2_DCORE2_ENGINE_ID_MME, "MME2_SBTE0"},
+		{RAZWI_INITIATOR_ID_X_Y_LOW(6, 11), mmDCORE2_RTR4_CTRL_BASE,
+				GAUDI2_DCORE2_ENGINE_ID_MME, "MME2_SBTE1"},
+		{RAZWI_INITIATOR_ID_X_Y_LOW(7, 11), mmDCORE2_RTR5_CTRL_BASE,
+				GAUDI2_DCORE2_ENGINE_ID_MME, "MME2_SBTE2"},
+		{RAZWI_INITIATOR_ID_X_Y_LOW(8, 11), mmDCORE2_RTR6_CTRL_BASE,
+				GAUDI2_DCORE2_ENGINE_ID_MME, "MME2_SBTE3"},
+		{RAZWI_INITIATOR_ID_X_Y_LOW(9, 11), mmDCORE2_RTR7_CTRL_BASE,
+				GAUDI2_DCORE2_ENGINE_ID_MME, "MME2_SBTE4"},
+		{RAZWI_INITIATOR_ID_X_Y_LOW(12, 11), mmDCORE3_RTR2_CTRL_BASE,
+				GAUDI2_DCORE3_ENGINE_ID_MME, "MME3_WAP0"},
+		{RAZWI_INITIATOR_ID_X_Y_LOW(10, 11), mmDCORE3_RTR0_CTRL_BASE,
+				GAUDI2_DCORE3_ENGINE_ID_MME, "MME3_WAP1"},
+		{RAZWI_INITIATOR_ID_X_Y_LOW(11, 11), mmDCORE3_RTR1_CTRL_BASE,
+				GAUDI2_DCORE3_ENGINE_ID_MME, "MME3_CTRL_WR"},
+		{RAZWI_INITIATOR_ID_X_Y_LOW(10, 11), mmDCORE3_RTR0_CTRL_BASE,
+				GAUDI2_DCORE3_ENGINE_ID_MME, "MME3_CTRL_RD"},
+		{RAZWI_INITIATOR_ID_X_Y_LOW(13, 11), mmDCORE3_RTR3_CTRL_BASE,
+				GAUDI2_DCORE3_ENGINE_ID_MME, "MME3_SBTE0"},
+		{RAZWI_INITIATOR_ID_X_Y_LOW(13, 11), mmDCORE3_RTR3_CTRL_BASE,
+				GAUDI2_DCORE3_ENGINE_ID_MME, "MME3_SBTE1"},
+		{RAZWI_INITIATOR_ID_X_Y_LOW(12, 11), mmDCORE3_RTR2_CTRL_BASE,
+				GAUDI2_DCORE3_ENGINE_ID_MME, "MME3_SBTE2"},
+		{RAZWI_INITIATOR_ID_X_Y_LOW(11, 11), mmDCORE3_RTR1_CTRL_BASE,
+				GAUDI2_DCORE3_ENGINE_ID_MME, "MME3_SBTE3"},
+		{RAZWI_INITIATOR_ID_X_Y_LOW(10, 11), mmDCORE3_RTR0_CTRL_BASE,
+				GAUDI2_DCORE3_ENGINE_ID_MME, "MME3_SBTE4"}
+};
+
+enum hl_pmmu_fatal_cause {
+	LATENCY_RD_OUT_FIFO_OVERRUN,
+	LATENCY_WR_OUT_FIFO_OVERRUN,
+};
+
+enum hl_pcie_drain_ind_cause {
+	LBW_AXI_DRAIN_IND,
+	HBW_AXI_DRAIN_IND
+};
+
+static const u32 cluster_hmmu_hif_enabled_mask[GAUDI2_HBM_NUM] = {
+	[HBM_ID0] = 0xFFFC,
+	[HBM_ID1] = 0xFFCF,
+	[HBM_ID2] = 0xF7F7,
+	[HBM_ID3] = 0x7F7F,
+	[HBM_ID4] = 0xFCFF,
+	[HBM_ID5] = 0xCFFF,
+};
+
+static const u8 xbar_edge_to_hbm_cluster[EDMA_ID_SIZE] = {
+	[0] = HBM_ID0,
+	[1] = HBM_ID1,
+	[2] = HBM_ID4,
+	[3] = HBM_ID5,
+};
+
+static const u8 edma_to_hbm_cluster[EDMA_ID_SIZE] = {
+	[EDMA_ID_DCORE0_INSTANCE0] = HBM_ID0,
+	[EDMA_ID_DCORE0_INSTANCE1] = HBM_ID2,
+	[EDMA_ID_DCORE1_INSTANCE0] = HBM_ID1,
+	[EDMA_ID_DCORE1_INSTANCE1] = HBM_ID3,
+	[EDMA_ID_DCORE2_INSTANCE0] = HBM_ID2,
+	[EDMA_ID_DCORE2_INSTANCE1] = HBM_ID4,
+	[EDMA_ID_DCORE3_INSTANCE0] = HBM_ID3,
+	[EDMA_ID_DCORE3_INSTANCE1] = HBM_ID5,
+};
+
+static const int gaudi2_qman_async_event_id[] = {
+	[GAUDI2_QUEUE_ID_PDMA_0_0] = GAUDI2_EVENT_PDMA0_QM,
+	[GAUDI2_QUEUE_ID_PDMA_0_1] = GAUDI2_EVENT_PDMA0_QM,
+	[GAUDI2_QUEUE_ID_PDMA_0_2] = GAUDI2_EVENT_PDMA0_QM,
+	[GAUDI2_QUEUE_ID_PDMA_0_3] = GAUDI2_EVENT_PDMA0_QM,
+	[GAUDI2_QUEUE_ID_PDMA_1_0] = GAUDI2_EVENT_PDMA1_QM,
+	[GAUDI2_QUEUE_ID_PDMA_1_1] = GAUDI2_EVENT_PDMA1_QM,
+	[GAUDI2_QUEUE_ID_PDMA_1_2] = GAUDI2_EVENT_PDMA1_QM,
+	[GAUDI2_QUEUE_ID_PDMA_1_3] = GAUDI2_EVENT_PDMA1_QM,
+	[GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0] = GAUDI2_EVENT_HDMA0_QM,
+	[GAUDI2_QUEUE_ID_DCORE0_EDMA_0_1] = GAUDI2_EVENT_HDMA0_QM,
+	[GAUDI2_QUEUE_ID_DCORE0_EDMA_0_2] = GAUDI2_EVENT_HDMA0_QM,
+	[GAUDI2_QUEUE_ID_DCORE0_EDMA_0_3] = GAUDI2_EVENT_HDMA0_QM,
+	[GAUDI2_QUEUE_ID_DCORE0_EDMA_1_0] = GAUDI2_EVENT_HDMA1_QM,
+	[GAUDI2_QUEUE_ID_DCORE0_EDMA_1_1] = GAUDI2_EVENT_HDMA1_QM,
+	[GAUDI2_QUEUE_ID_DCORE0_EDMA_1_2] = GAUDI2_EVENT_HDMA1_QM,
+	[GAUDI2_QUEUE_ID_DCORE0_EDMA_1_3] = GAUDI2_EVENT_HDMA1_QM,
+	[GAUDI2_QUEUE_ID_DCORE0_MME_0_0] = GAUDI2_EVENT_MME0_QM,
+	[GAUDI2_QUEUE_ID_DCORE0_MME_0_1] = GAUDI2_EVENT_MME0_QM,
+	[GAUDI2_QUEUE_ID_DCORE0_MME_0_2] = GAUDI2_EVENT_MME0_QM,
+	[GAUDI2_QUEUE_ID_DCORE0_MME_0_3] = GAUDI2_EVENT_MME0_QM,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_0_0] = GAUDI2_EVENT_TPC0_QM,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_0_1] = GAUDI2_EVENT_TPC0_QM,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_0_2] = GAUDI2_EVENT_TPC0_QM,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_0_3] = GAUDI2_EVENT_TPC0_QM,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_1_0] = GAUDI2_EVENT_TPC1_QM,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_1_1] = GAUDI2_EVENT_TPC1_QM,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_1_2] = GAUDI2_EVENT_TPC1_QM,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_1_3] = GAUDI2_EVENT_TPC1_QM,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_2_0] = GAUDI2_EVENT_TPC2_QM,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_2_1] = GAUDI2_EVENT_TPC2_QM,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_2_2] = GAUDI2_EVENT_TPC2_QM,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_2_3] = GAUDI2_EVENT_TPC2_QM,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_3_0] = GAUDI2_EVENT_TPC3_QM,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_3_1] = GAUDI2_EVENT_TPC3_QM,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_3_2] = GAUDI2_EVENT_TPC3_QM,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_3_3] = GAUDI2_EVENT_TPC3_QM,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_4_0] = GAUDI2_EVENT_TPC4_QM,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_4_1] = GAUDI2_EVENT_TPC4_QM,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_4_2] = GAUDI2_EVENT_TPC4_QM,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_4_3] = GAUDI2_EVENT_TPC4_QM,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_5_0] = GAUDI2_EVENT_TPC5_QM,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_5_1] = GAUDI2_EVENT_TPC5_QM,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_5_2] = GAUDI2_EVENT_TPC5_QM,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_5_3] = GAUDI2_EVENT_TPC5_QM,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_6_0] = GAUDI2_EVENT_TPC24_QM,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_6_1] = GAUDI2_EVENT_TPC24_QM,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_6_2] = GAUDI2_EVENT_TPC24_QM,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_6_3] = GAUDI2_EVENT_TPC24_QM,
+	[GAUDI2_QUEUE_ID_DCORE1_EDMA_0_0] = GAUDI2_EVENT_HDMA2_QM,
+	[GAUDI2_QUEUE_ID_DCORE1_EDMA_0_1] = GAUDI2_EVENT_HDMA2_QM,
+	[GAUDI2_QUEUE_ID_DCORE1_EDMA_0_2] = GAUDI2_EVENT_HDMA2_QM,
+	[GAUDI2_QUEUE_ID_DCORE1_EDMA_0_3] = GAUDI2_EVENT_HDMA2_QM,
+	[GAUDI2_QUEUE_ID_DCORE1_EDMA_1_0] = GAUDI2_EVENT_HDMA3_QM,
+	[GAUDI2_QUEUE_ID_DCORE1_EDMA_1_1] = GAUDI2_EVENT_HDMA3_QM,
+	[GAUDI2_QUEUE_ID_DCORE1_EDMA_1_2] = GAUDI2_EVENT_HDMA3_QM,
+	[GAUDI2_QUEUE_ID_DCORE1_EDMA_1_3] = GAUDI2_EVENT_HDMA3_QM,
+	[GAUDI2_QUEUE_ID_DCORE1_MME_0_0] = GAUDI2_EVENT_MME1_QM,
+	[GAUDI2_QUEUE_ID_DCORE1_MME_0_1] = GAUDI2_EVENT_MME1_QM,
+	[GAUDI2_QUEUE_ID_DCORE1_MME_0_2] = GAUDI2_EVENT_MME1_QM,
+	[GAUDI2_QUEUE_ID_DCORE1_MME_0_3] = GAUDI2_EVENT_MME1_QM,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_0_0] = GAUDI2_EVENT_TPC6_QM,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_0_1] = GAUDI2_EVENT_TPC6_QM,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_0_2] = GAUDI2_EVENT_TPC6_QM,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_0_3] = GAUDI2_EVENT_TPC6_QM,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_1_0] = GAUDI2_EVENT_TPC7_QM,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_1_1] = GAUDI2_EVENT_TPC7_QM,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_1_2] = GAUDI2_EVENT_TPC7_QM,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_1_3] = GAUDI2_EVENT_TPC7_QM,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_2_0] = GAUDI2_EVENT_TPC8_QM,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_2_1] = GAUDI2_EVENT_TPC8_QM,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_2_2] = GAUDI2_EVENT_TPC8_QM,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_2_3] = GAUDI2_EVENT_TPC8_QM,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_3_0] = GAUDI2_EVENT_TPC9_QM,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_3_1] = GAUDI2_EVENT_TPC9_QM,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_3_2] = GAUDI2_EVENT_TPC9_QM,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_3_3] = GAUDI2_EVENT_TPC9_QM,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_4_0] = GAUDI2_EVENT_TPC10_QM,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_4_1] = GAUDI2_EVENT_TPC10_QM,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_4_2] = GAUDI2_EVENT_TPC10_QM,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_4_3] = GAUDI2_EVENT_TPC10_QM,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_5_0] = GAUDI2_EVENT_TPC11_QM,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_5_1] = GAUDI2_EVENT_TPC11_QM,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_5_2] = GAUDI2_EVENT_TPC11_QM,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_5_3] = GAUDI2_EVENT_TPC11_QM,
+	[GAUDI2_QUEUE_ID_DCORE2_EDMA_0_0] = GAUDI2_EVENT_HDMA4_QM,
+	[GAUDI2_QUEUE_ID_DCORE2_EDMA_0_1] = GAUDI2_EVENT_HDMA4_QM,
+	[GAUDI2_QUEUE_ID_DCORE2_EDMA_0_2] = GAUDI2_EVENT_HDMA4_QM,
+	[GAUDI2_QUEUE_ID_DCORE2_EDMA_0_3] = GAUDI2_EVENT_HDMA4_QM,
+	[GAUDI2_QUEUE_ID_DCORE2_EDMA_1_0] = GAUDI2_EVENT_HDMA5_QM,
+	[GAUDI2_QUEUE_ID_DCORE2_EDMA_1_1] = GAUDI2_EVENT_HDMA5_QM,
+	[GAUDI2_QUEUE_ID_DCORE2_EDMA_1_2] = GAUDI2_EVENT_HDMA5_QM,
+	[GAUDI2_QUEUE_ID_DCORE2_EDMA_1_3] = GAUDI2_EVENT_HDMA5_QM,
+	[GAUDI2_QUEUE_ID_DCORE2_MME_0_0] = GAUDI2_EVENT_MME2_QM,
+	[GAUDI2_QUEUE_ID_DCORE2_MME_0_1] = GAUDI2_EVENT_MME2_QM,
+	[GAUDI2_QUEUE_ID_DCORE2_MME_0_2] = GAUDI2_EVENT_MME2_QM,
+	[GAUDI2_QUEUE_ID_DCORE2_MME_0_3] = GAUDI2_EVENT_MME2_QM,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_0_0] = GAUDI2_EVENT_TPC12_QM,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_0_1] = GAUDI2_EVENT_TPC12_QM,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_0_2] = GAUDI2_EVENT_TPC12_QM,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_0_3] = GAUDI2_EVENT_TPC12_QM,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_1_0] = GAUDI2_EVENT_TPC13_QM,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_1_1] = GAUDI2_EVENT_TPC13_QM,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_1_2] = GAUDI2_EVENT_TPC13_QM,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_1_3] = GAUDI2_EVENT_TPC13_QM,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_2_0] = GAUDI2_EVENT_TPC14_QM,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_2_1] = GAUDI2_EVENT_TPC14_QM,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_2_2] = GAUDI2_EVENT_TPC14_QM,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_2_3] = GAUDI2_EVENT_TPC14_QM,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_3_0] = GAUDI2_EVENT_TPC15_QM,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_3_1] = GAUDI2_EVENT_TPC15_QM,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_3_2] = GAUDI2_EVENT_TPC15_QM,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_3_3] = GAUDI2_EVENT_TPC15_QM,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_4_0] = GAUDI2_EVENT_TPC16_QM,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_4_1] = GAUDI2_EVENT_TPC16_QM,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_4_2] = GAUDI2_EVENT_TPC16_QM,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_4_3] = GAUDI2_EVENT_TPC16_QM,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_5_0] = GAUDI2_EVENT_TPC17_QM,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_5_1] = GAUDI2_EVENT_TPC17_QM,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_5_2] = GAUDI2_EVENT_TPC17_QM,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_5_3] = GAUDI2_EVENT_TPC17_QM,
+	[GAUDI2_QUEUE_ID_DCORE3_EDMA_0_0] = GAUDI2_EVENT_HDMA6_QM,
+	[GAUDI2_QUEUE_ID_DCORE3_EDMA_0_1] = GAUDI2_EVENT_HDMA6_QM,
+	[GAUDI2_QUEUE_ID_DCORE3_EDMA_0_2] = GAUDI2_EVENT_HDMA6_QM,
+	[GAUDI2_QUEUE_ID_DCORE3_EDMA_0_3] = GAUDI2_EVENT_HDMA6_QM,
+	[GAUDI2_QUEUE_ID_DCORE3_EDMA_1_0] = GAUDI2_EVENT_HDMA7_QM,
+	[GAUDI2_QUEUE_ID_DCORE3_EDMA_1_1] = GAUDI2_EVENT_HDMA7_QM,
+	[GAUDI2_QUEUE_ID_DCORE3_EDMA_1_2] = GAUDI2_EVENT_HDMA7_QM,
+	[GAUDI2_QUEUE_ID_DCORE3_EDMA_1_3] = GAUDI2_EVENT_HDMA7_QM,
+	[GAUDI2_QUEUE_ID_DCORE3_MME_0_0] = GAUDI2_EVENT_MME3_QM,
+	[GAUDI2_QUEUE_ID_DCORE3_MME_0_1] = GAUDI2_EVENT_MME3_QM,
+	[GAUDI2_QUEUE_ID_DCORE3_MME_0_2] = GAUDI2_EVENT_MME3_QM,
+	[GAUDI2_QUEUE_ID_DCORE3_MME_0_3] = GAUDI2_EVENT_MME3_QM,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_0_0] = GAUDI2_EVENT_TPC18_QM,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_0_1] = GAUDI2_EVENT_TPC18_QM,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_0_2] = GAUDI2_EVENT_TPC18_QM,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_0_3] = GAUDI2_EVENT_TPC18_QM,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_1_0] = GAUDI2_EVENT_TPC19_QM,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_1_1] = GAUDI2_EVENT_TPC19_QM,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_1_2] = GAUDI2_EVENT_TPC19_QM,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_1_3] = GAUDI2_EVENT_TPC19_QM,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_2_0] = GAUDI2_EVENT_TPC20_QM,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_2_1] = GAUDI2_EVENT_TPC20_QM,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_2_2] = GAUDI2_EVENT_TPC20_QM,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_2_3] = GAUDI2_EVENT_TPC20_QM,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_3_0] = GAUDI2_EVENT_TPC21_QM,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_3_1] = GAUDI2_EVENT_TPC21_QM,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_3_2] = GAUDI2_EVENT_TPC21_QM,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_3_3] = GAUDI2_EVENT_TPC21_QM,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_4_0] = GAUDI2_EVENT_TPC22_QM,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_4_1] = GAUDI2_EVENT_TPC22_QM,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_4_2] = GAUDI2_EVENT_TPC22_QM,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_4_3] = GAUDI2_EVENT_TPC22_QM,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_5_0] = GAUDI2_EVENT_TPC23_QM,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_5_1] = GAUDI2_EVENT_TPC23_QM,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_5_2] = GAUDI2_EVENT_TPC23_QM,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_5_3] = GAUDI2_EVENT_TPC23_QM,
+	[GAUDI2_QUEUE_ID_NIC_0_0] = GAUDI2_EVENT_NIC0_QM0,
+	[GAUDI2_QUEUE_ID_NIC_0_1] = GAUDI2_EVENT_NIC0_QM0,
+	[GAUDI2_QUEUE_ID_NIC_0_2] = GAUDI2_EVENT_NIC0_QM0,
+	[GAUDI2_QUEUE_ID_NIC_0_3] = GAUDI2_EVENT_NIC0_QM0,
+	[GAUDI2_QUEUE_ID_NIC_1_0] = GAUDI2_EVENT_NIC0_QM1,
+	[GAUDI2_QUEUE_ID_NIC_1_1] = GAUDI2_EVENT_NIC0_QM1,
+	[GAUDI2_QUEUE_ID_NIC_1_2] = GAUDI2_EVENT_NIC0_QM1,
+	[GAUDI2_QUEUE_ID_NIC_1_3] = GAUDI2_EVENT_NIC0_QM1,
+	[GAUDI2_QUEUE_ID_NIC_2_0] = GAUDI2_EVENT_NIC1_QM0,
+	[GAUDI2_QUEUE_ID_NIC_2_1] = GAUDI2_EVENT_NIC1_QM0,
+	[GAUDI2_QUEUE_ID_NIC_2_2] = GAUDI2_EVENT_NIC1_QM0,
+	[GAUDI2_QUEUE_ID_NIC_2_3] = GAUDI2_EVENT_NIC1_QM0,
+	[GAUDI2_QUEUE_ID_NIC_3_0] = GAUDI2_EVENT_NIC1_QM1,
+	[GAUDI2_QUEUE_ID_NIC_3_1] = GAUDI2_EVENT_NIC1_QM1,
+	[GAUDI2_QUEUE_ID_NIC_3_2] = GAUDI2_EVENT_NIC1_QM1,
+	[GAUDI2_QUEUE_ID_NIC_3_3] = GAUDI2_EVENT_NIC1_QM1,
+	[GAUDI2_QUEUE_ID_NIC_4_0] = GAUDI2_EVENT_NIC2_QM0,
+	[GAUDI2_QUEUE_ID_NIC_4_1] = GAUDI2_EVENT_NIC2_QM0,
+	[GAUDI2_QUEUE_ID_NIC_4_2] = GAUDI2_EVENT_NIC2_QM0,
+	[GAUDI2_QUEUE_ID_NIC_4_3] = GAUDI2_EVENT_NIC2_QM0,
+	[GAUDI2_QUEUE_ID_NIC_5_0] = GAUDI2_EVENT_NIC2_QM1,
+	[GAUDI2_QUEUE_ID_NIC_5_1] = GAUDI2_EVENT_NIC2_QM1,
+	[GAUDI2_QUEUE_ID_NIC_5_2] = GAUDI2_EVENT_NIC2_QM1,
+	[GAUDI2_QUEUE_ID_NIC_5_3] = GAUDI2_EVENT_NIC2_QM1,
+	[GAUDI2_QUEUE_ID_NIC_6_0] = GAUDI2_EVENT_NIC3_QM0,
+	[GAUDI2_QUEUE_ID_NIC_6_1] = GAUDI2_EVENT_NIC3_QM0,
+	[GAUDI2_QUEUE_ID_NIC_6_2] = GAUDI2_EVENT_NIC3_QM0,
+	[GAUDI2_QUEUE_ID_NIC_6_3] = GAUDI2_EVENT_NIC3_QM0,
+	[GAUDI2_QUEUE_ID_NIC_7_0] = GAUDI2_EVENT_NIC3_QM1,
+	[GAUDI2_QUEUE_ID_NIC_7_1] = GAUDI2_EVENT_NIC3_QM1,
+	[GAUDI2_QUEUE_ID_NIC_7_2] = GAUDI2_EVENT_NIC3_QM1,
+	[GAUDI2_QUEUE_ID_NIC_7_3] = GAUDI2_EVENT_NIC3_QM1,
+	[GAUDI2_QUEUE_ID_NIC_8_0] = GAUDI2_EVENT_NIC4_QM0,
+	[GAUDI2_QUEUE_ID_NIC_8_1] = GAUDI2_EVENT_NIC4_QM0,
+	[GAUDI2_QUEUE_ID_NIC_8_2] = GAUDI2_EVENT_NIC4_QM0,
+	[GAUDI2_QUEUE_ID_NIC_8_3] = GAUDI2_EVENT_NIC4_QM0,
+	[GAUDI2_QUEUE_ID_NIC_9_0] = GAUDI2_EVENT_NIC4_QM1,
+	[GAUDI2_QUEUE_ID_NIC_9_1] = GAUDI2_EVENT_NIC4_QM1,
+	[GAUDI2_QUEUE_ID_NIC_9_2] = GAUDI2_EVENT_NIC4_QM1,
+	[GAUDI2_QUEUE_ID_NIC_9_3] = GAUDI2_EVENT_NIC4_QM1,
+	[GAUDI2_QUEUE_ID_NIC_10_0] = GAUDI2_EVENT_NIC5_QM0,
+	[GAUDI2_QUEUE_ID_NIC_10_1] = GAUDI2_EVENT_NIC5_QM0,
+	[GAUDI2_QUEUE_ID_NIC_10_2] = GAUDI2_EVENT_NIC5_QM0,
+	[GAUDI2_QUEUE_ID_NIC_10_3] = GAUDI2_EVENT_NIC5_QM0,
+	[GAUDI2_QUEUE_ID_NIC_11_0] = GAUDI2_EVENT_NIC5_QM1,
+	[GAUDI2_QUEUE_ID_NIC_11_1] = GAUDI2_EVENT_NIC5_QM1,
+	[GAUDI2_QUEUE_ID_NIC_11_2] = GAUDI2_EVENT_NIC5_QM1,
+	[GAUDI2_QUEUE_ID_NIC_11_3] = GAUDI2_EVENT_NIC5_QM1,
+	[GAUDI2_QUEUE_ID_NIC_12_0] = GAUDI2_EVENT_NIC6_QM0,
+	[GAUDI2_QUEUE_ID_NIC_12_1] = GAUDI2_EVENT_NIC6_QM0,
+	[GAUDI2_QUEUE_ID_NIC_12_2] = GAUDI2_EVENT_NIC6_QM0,
+	[GAUDI2_QUEUE_ID_NIC_12_3] = GAUDI2_EVENT_NIC6_QM0,
+	[GAUDI2_QUEUE_ID_NIC_13_0] = GAUDI2_EVENT_NIC6_QM1,
+	[GAUDI2_QUEUE_ID_NIC_13_1] = GAUDI2_EVENT_NIC6_QM1,
+	[GAUDI2_QUEUE_ID_NIC_13_2] = GAUDI2_EVENT_NIC6_QM1,
+	[GAUDI2_QUEUE_ID_NIC_13_3] = GAUDI2_EVENT_NIC6_QM1,
+	[GAUDI2_QUEUE_ID_NIC_14_0] = GAUDI2_EVENT_NIC7_QM0,
+	[GAUDI2_QUEUE_ID_NIC_14_1] = GAUDI2_EVENT_NIC7_QM0,
+	[GAUDI2_QUEUE_ID_NIC_14_2] = GAUDI2_EVENT_NIC7_QM0,
+	[GAUDI2_QUEUE_ID_NIC_14_3] = GAUDI2_EVENT_NIC7_QM0,
+	[GAUDI2_QUEUE_ID_NIC_15_0] = GAUDI2_EVENT_NIC7_QM1,
+	[GAUDI2_QUEUE_ID_NIC_15_1] = GAUDI2_EVENT_NIC7_QM1,
+	[GAUDI2_QUEUE_ID_NIC_15_2] = GAUDI2_EVENT_NIC7_QM1,
+	[GAUDI2_QUEUE_ID_NIC_15_3] = GAUDI2_EVENT_NIC7_QM1,
+	[GAUDI2_QUEUE_ID_NIC_16_0] = GAUDI2_EVENT_NIC8_QM0,
+	[GAUDI2_QUEUE_ID_NIC_16_1] = GAUDI2_EVENT_NIC8_QM0,
+	[GAUDI2_QUEUE_ID_NIC_16_2] = GAUDI2_EVENT_NIC8_QM0,
+	[GAUDI2_QUEUE_ID_NIC_16_3] = GAUDI2_EVENT_NIC8_QM0,
+	[GAUDI2_QUEUE_ID_NIC_17_0] = GAUDI2_EVENT_NIC8_QM1,
+	[GAUDI2_QUEUE_ID_NIC_17_1] = GAUDI2_EVENT_NIC8_QM1,
+	[GAUDI2_QUEUE_ID_NIC_17_2] = GAUDI2_EVENT_NIC8_QM1,
+	[GAUDI2_QUEUE_ID_NIC_17_3] = GAUDI2_EVENT_NIC8_QM1,
+	[GAUDI2_QUEUE_ID_NIC_18_0] = GAUDI2_EVENT_NIC9_QM0,
+	[GAUDI2_QUEUE_ID_NIC_18_1] = GAUDI2_EVENT_NIC9_QM0,
+	[GAUDI2_QUEUE_ID_NIC_18_2] = GAUDI2_EVENT_NIC9_QM0,
+	[GAUDI2_QUEUE_ID_NIC_18_3] = GAUDI2_EVENT_NIC9_QM0,
+	[GAUDI2_QUEUE_ID_NIC_19_0] = GAUDI2_EVENT_NIC9_QM1,
+	[GAUDI2_QUEUE_ID_NIC_19_1] = GAUDI2_EVENT_NIC9_QM1,
+	[GAUDI2_QUEUE_ID_NIC_19_2] = GAUDI2_EVENT_NIC9_QM1,
+	[GAUDI2_QUEUE_ID_NIC_19_3] = GAUDI2_EVENT_NIC9_QM1,
+	[GAUDI2_QUEUE_ID_NIC_20_0] = GAUDI2_EVENT_NIC10_QM0,
+	[GAUDI2_QUEUE_ID_NIC_20_1] = GAUDI2_EVENT_NIC10_QM0,
+	[GAUDI2_QUEUE_ID_NIC_20_2] = GAUDI2_EVENT_NIC10_QM0,
+	[GAUDI2_QUEUE_ID_NIC_20_3] = GAUDI2_EVENT_NIC10_QM0,
+	[GAUDI2_QUEUE_ID_NIC_21_0] = GAUDI2_EVENT_NIC10_QM1,
+	[GAUDI2_QUEUE_ID_NIC_21_1] = GAUDI2_EVENT_NIC10_QM1,
+	[GAUDI2_QUEUE_ID_NIC_21_2] = GAUDI2_EVENT_NIC10_QM1,
+	[GAUDI2_QUEUE_ID_NIC_21_3] = GAUDI2_EVENT_NIC10_QM1,
+	[GAUDI2_QUEUE_ID_NIC_22_0] = GAUDI2_EVENT_NIC11_QM0,
+	[GAUDI2_QUEUE_ID_NIC_22_1] = GAUDI2_EVENT_NIC11_QM0,
+	[GAUDI2_QUEUE_ID_NIC_22_2] = GAUDI2_EVENT_NIC11_QM0,
+	[GAUDI2_QUEUE_ID_NIC_22_3] = GAUDI2_EVENT_NIC11_QM0,
+	[GAUDI2_QUEUE_ID_NIC_23_0] = GAUDI2_EVENT_NIC11_QM1,
+	[GAUDI2_QUEUE_ID_NIC_23_1] = GAUDI2_EVENT_NIC11_QM1,
+	[GAUDI2_QUEUE_ID_NIC_23_2] = GAUDI2_EVENT_NIC11_QM1,
+	[GAUDI2_QUEUE_ID_NIC_23_3] = GAUDI2_EVENT_NIC11_QM1,
+	[GAUDI2_QUEUE_ID_ROT_0_0] = GAUDI2_EVENT_ROTATOR0_ROT0_QM,
+	[GAUDI2_QUEUE_ID_ROT_0_1] = GAUDI2_EVENT_ROTATOR0_ROT0_QM,
+	[GAUDI2_QUEUE_ID_ROT_0_2] = GAUDI2_EVENT_ROTATOR0_ROT0_QM,
+	[GAUDI2_QUEUE_ID_ROT_0_3] = GAUDI2_EVENT_ROTATOR0_ROT0_QM,
+	[GAUDI2_QUEUE_ID_ROT_1_0] = GAUDI2_EVENT_ROTATOR1_ROT1_QM,
+	[GAUDI2_QUEUE_ID_ROT_1_1] = GAUDI2_EVENT_ROTATOR1_ROT1_QM,
+	[GAUDI2_QUEUE_ID_ROT_1_2] = GAUDI2_EVENT_ROTATOR1_ROT1_QM,
+	[GAUDI2_QUEUE_ID_ROT_1_3] = GAUDI2_EVENT_ROTATOR1_ROT1_QM
+};
+
+static const int gaudi2_dma_core_async_event_id[] = {
+	[DMA_CORE_ID_EDMA0] = GAUDI2_EVENT_HDMA0_CORE,
+	[DMA_CORE_ID_EDMA1] = GAUDI2_EVENT_HDMA1_CORE,
+	[DMA_CORE_ID_EDMA2] = GAUDI2_EVENT_HDMA2_CORE,
+	[DMA_CORE_ID_EDMA3] = GAUDI2_EVENT_HDMA3_CORE,
+	[DMA_CORE_ID_EDMA4] = GAUDI2_EVENT_HDMA4_CORE,
+	[DMA_CORE_ID_EDMA5] = GAUDI2_EVENT_HDMA5_CORE,
+	[DMA_CORE_ID_EDMA6] = GAUDI2_EVENT_HDMA6_CORE,
+	[DMA_CORE_ID_EDMA7] = GAUDI2_EVENT_HDMA7_CORE,
+	[DMA_CORE_ID_PDMA0] = GAUDI2_EVENT_PDMA0_CORE,
+	[DMA_CORE_ID_PDMA1] = GAUDI2_EVENT_PDMA1_CORE,
+	[DMA_CORE_ID_KDMA] = GAUDI2_EVENT_KDMA0_CORE,
+};
+
+const char *gaudi2_engine_id_str[] = {
+	__stringify(GAUDI2_DCORE0_ENGINE_ID_EDMA_0),
+	__stringify(GAUDI2_DCORE0_ENGINE_ID_EDMA_1),
+	__stringify(GAUDI2_DCORE0_ENGINE_ID_MME),
+	__stringify(GAUDI2_DCORE0_ENGINE_ID_TPC_0),
+	__stringify(GAUDI2_DCORE0_ENGINE_ID_TPC_1),
+	__stringify(GAUDI2_DCORE0_ENGINE_ID_TPC_2),
+	__stringify(GAUDI2_DCORE0_ENGINE_ID_TPC_3),
+	__stringify(GAUDI2_DCORE0_ENGINE_ID_TPC_4),
+	__stringify(GAUDI2_DCORE0_ENGINE_ID_TPC_5),
+	__stringify(GAUDI2_DCORE0_ENGINE_ID_DEC_0),
+	__stringify(GAUDI2_DCORE0_ENGINE_ID_DEC_1),
+	__stringify(GAUDI2_DCORE1_ENGINE_ID_EDMA_0),
+	__stringify(GAUDI2_DCORE1_ENGINE_ID_EDMA_1),
+	__stringify(GAUDI2_DCORE1_ENGINE_ID_MME),
+	__stringify(GAUDI2_DCORE1_ENGINE_ID_TPC_0),
+	__stringify(GAUDI2_DCORE1_ENGINE_ID_TPC_1),
+	__stringify(GAUDI2_DCORE1_ENGINE_ID_TPC_2),
+	__stringify(GAUDI2_DCORE1_ENGINE_ID_TPC_3),
+	__stringify(GAUDI2_DCORE1_ENGINE_ID_TPC_4),
+	__stringify(GAUDI2_DCORE1_ENGINE_ID_TPC_5),
+	__stringify(GAUDI2_DCORE1_ENGINE_ID_DEC_0),
+	__stringify(GAUDI2_DCORE1_ENGINE_ID_DEC_1),
+	__stringify(GAUDI2_DCORE2_ENGINE_ID_EDMA_0),
+	__stringify(GAUDI2_DCORE2_ENGINE_ID_EDMA_1),
+	__stringify(GAUDI2_DCORE2_ENGINE_ID_MME),
+	__stringify(GAUDI2_DCORE2_ENGINE_ID_TPC_0),
+	__stringify(GAUDI2_DCORE2_ENGINE_ID_TPC_1),
+	__stringify(GAUDI2_DCORE2_ENGINE_ID_TPC_2),
+	__stringify(GAUDI2_DCORE2_ENGINE_ID_TPC_3),
+	__stringify(GAUDI2_DCORE2_ENGINE_ID_TPC_4),
+	__stringify(GAUDI2_DCORE2_ENGINE_ID_TPC_5),
+	__stringify(GAUDI2_DCORE2_ENGINE_ID_DEC_0),
+	__stringify(GAUDI2_DCORE2_ENGINE_ID_DEC_1),
+	__stringify(GAUDI2_DCORE3_ENGINE_ID_EDMA_0),
+	__stringify(GAUDI2_DCORE3_ENGINE_ID_EDMA_1),
+	__stringify(GAUDI2_DCORE3_ENGINE_ID_MME),
+	__stringify(GAUDI2_DCORE3_ENGINE_ID_TPC_0),
+	__stringify(GAUDI2_DCORE3_ENGINE_ID_TPC_1),
+	__stringify(GAUDI2_DCORE3_ENGINE_ID_TPC_2),
+	__stringify(GAUDI2_DCORE3_ENGINE_ID_TPC_3),
+	__stringify(GAUDI2_DCORE3_ENGINE_ID_TPC_4),
+	__stringify(GAUDI2_DCORE3_ENGINE_ID_TPC_5),
+	__stringify(GAUDI2_DCORE3_ENGINE_ID_DEC_0),
+	__stringify(GAUDI2_DCORE3_ENGINE_ID_DEC_1),
+	__stringify(GAUDI2_DCORE0_ENGINE_ID_TPC_6),
+	__stringify(GAUDI2_ENGINE_ID_PDMA_0),
+	__stringify(GAUDI2_ENGINE_ID_PDMA_1),
+	__stringify(GAUDI2_ENGINE_ID_ROT_0),
+	__stringify(GAUDI2_ENGINE_ID_ROT_1),
+	__stringify(GAUDI2_PCIE_ENGINE_ID_DEC_0),
+	__stringify(GAUDI2_PCIE_ENGINE_ID_DEC_1),
+	__stringify(GAUDI2_ENGINE_ID_NIC0_0),
+	__stringify(GAUDI2_ENGINE_ID_NIC0_1),
+	__stringify(GAUDI2_ENGINE_ID_NIC1_0),
+	__stringify(GAUDI2_ENGINE_ID_NIC1_1),
+	__stringify(GAUDI2_ENGINE_ID_NIC2_0),
+	__stringify(GAUDI2_ENGINE_ID_NIC2_1),
+	__stringify(GAUDI2_ENGINE_ID_NIC3_0),
+	__stringify(GAUDI2_ENGINE_ID_NIC3_1),
+	__stringify(GAUDI2_ENGINE_ID_NIC4_0),
+	__stringify(GAUDI2_ENGINE_ID_NIC4_1),
+	__stringify(GAUDI2_ENGINE_ID_NIC5_0),
+	__stringify(GAUDI2_ENGINE_ID_NIC5_1),
+	__stringify(GAUDI2_ENGINE_ID_NIC6_0),
+	__stringify(GAUDI2_ENGINE_ID_NIC6_1),
+	__stringify(GAUDI2_ENGINE_ID_NIC7_0),
+	__stringify(GAUDI2_ENGINE_ID_NIC7_1),
+	__stringify(GAUDI2_ENGINE_ID_NIC8_0),
+	__stringify(GAUDI2_ENGINE_ID_NIC8_1),
+	__stringify(GAUDI2_ENGINE_ID_NIC9_0),
+	__stringify(GAUDI2_ENGINE_ID_NIC9_1),
+	__stringify(GAUDI2_ENGINE_ID_NIC10_0),
+	__stringify(GAUDI2_ENGINE_ID_NIC10_1),
+	__stringify(GAUDI2_ENGINE_ID_NIC11_0),
+	__stringify(GAUDI2_ENGINE_ID_NIC11_1),
+	__stringify(GAUDI2_ENGINE_ID_PCIE),
+	__stringify(GAUDI2_ENGINE_ID_PSOC),
+	__stringify(GAUDI2_ENGINE_ID_ARC_FARM),
+	__stringify(GAUDI2_ENGINE_ID_KDMA),
+	__stringify(GAUDI2_ENGINE_ID_SIZE),
+};
+
+const char *gaudi2_queue_id_str[] = {
+	__stringify(GAUDI2_QUEUE_ID_PDMA_0_0),
+	__stringify(GAUDI2_QUEUE_ID_PDMA_0_1),
+	__stringify(GAUDI2_QUEUE_ID_PDMA_0_2),
+	__stringify(GAUDI2_QUEUE_ID_PDMA_0_3),
+	__stringify(GAUDI2_QUEUE_ID_PDMA_1_0),
+	__stringify(GAUDI2_QUEUE_ID_PDMA_1_1),
+	__stringify(GAUDI2_QUEUE_ID_PDMA_1_2),
+	__stringify(GAUDI2_QUEUE_ID_PDMA_1_3),
+	__stringify(GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0),
+	__stringify(GAUDI2_QUEUE_ID_DCORE0_EDMA_0_1),
+	__stringify(GAUDI2_QUEUE_ID_DCORE0_EDMA_0_2),
+	__stringify(GAUDI2_QUEUE_ID_DCORE0_EDMA_0_3),
+	__stringify(GAUDI2_QUEUE_ID_DCORE0_EDMA_1_0),
+	__stringify(GAUDI2_QUEUE_ID_DCORE0_EDMA_1_1),
+	__stringify(GAUDI2_QUEUE_ID_DCORE0_EDMA_1_2),
+	__stringify(GAUDI2_QUEUE_ID_DCORE0_EDMA_1_3),
+	__stringify(GAUDI2_QUEUE_ID_DCORE0_MME_0_0),
+	__stringify(GAUDI2_QUEUE_ID_DCORE0_MME_0_1),
+	__stringify(GAUDI2_QUEUE_ID_DCORE0_MME_0_2),
+	__stringify(GAUDI2_QUEUE_ID_DCORE0_MME_0_3),
+	__stringify(GAUDI2_QUEUE_ID_DCORE0_TPC_0_0),
+	__stringify(GAUDI2_QUEUE_ID_DCORE0_TPC_0_1),
+	__stringify(GAUDI2_QUEUE_ID_DCORE0_TPC_0_2),
+	__stringify(GAUDI2_QUEUE_ID_DCORE0_TPC_0_3),
+	__stringify(GAUDI2_QUEUE_ID_DCORE0_TPC_1_0),
+	__stringify(GAUDI2_QUEUE_ID_DCORE0_TPC_1_1),
+	__stringify(GAUDI2_QUEUE_ID_DCORE0_TPC_1_2),
+	__stringify(GAUDI2_QUEUE_ID_DCORE0_TPC_1_3),
+	__stringify(GAUDI2_QUEUE_ID_DCORE0_TPC_2_0),
+	__stringify(GAUDI2_QUEUE_ID_DCORE0_TPC_2_1),
+	__stringify(GAUDI2_QUEUE_ID_DCORE0_TPC_2_2),
+	__stringify(GAUDI2_QUEUE_ID_DCORE0_TPC_2_3),
+	__stringify(GAUDI2_QUEUE_ID_DCORE0_TPC_3_0),
+	__stringify(GAUDI2_QUEUE_ID_DCORE0_TPC_3_1),
+	__stringify(GAUDI2_QUEUE_ID_DCORE0_TPC_3_2),
+	__stringify(GAUDI2_QUEUE_ID_DCORE0_TPC_3_3),
+	__stringify(GAUDI2_QUEUE_ID_DCORE0_TPC_4_0),
+	__stringify(GAUDI2_QUEUE_ID_DCORE0_TPC_4_1),
+	__stringify(GAUDI2_QUEUE_ID_DCORE0_TPC_4_2),
+	__stringify(GAUDI2_QUEUE_ID_DCORE0_TPC_4_3),
+	__stringify(GAUDI2_QUEUE_ID_DCORE0_TPC_5_0),
+	__stringify(GAUDI2_QUEUE_ID_DCORE0_TPC_5_1),
+	__stringify(GAUDI2_QUEUE_ID_DCORE0_TPC_5_2),
+	__stringify(GAUDI2_QUEUE_ID_DCORE0_TPC_5_3),
+	__stringify(GAUDI2_QUEUE_ID_DCORE0_TPC_6_0),
+	__stringify(GAUDI2_QUEUE_ID_DCORE0_TPC_6_1),
+	__stringify(GAUDI2_QUEUE_ID_DCORE0_TPC_6_2),
+	__stringify(GAUDI2_QUEUE_ID_DCORE0_TPC_6_3),
+	__stringify(GAUDI2_QUEUE_ID_DCORE1_EDMA_0_0),
+	__stringify(GAUDI2_QUEUE_ID_DCORE1_EDMA_0_1),
+	__stringify(GAUDI2_QUEUE_ID_DCORE1_EDMA_0_2),
+	__stringify(GAUDI2_QUEUE_ID_DCORE1_EDMA_0_3),
+	__stringify(GAUDI2_QUEUE_ID_DCORE1_EDMA_1_0),
+	__stringify(GAUDI2_QUEUE_ID_DCORE1_EDMA_1_1),
+	__stringify(GAUDI2_QUEUE_ID_DCORE1_EDMA_1_2),
+	__stringify(GAUDI2_QUEUE_ID_DCORE1_EDMA_1_3),
+	__stringify(GAUDI2_QUEUE_ID_DCORE1_MME_0_0),
+	__stringify(GAUDI2_QUEUE_ID_DCORE1_MME_0_1),
+	__stringify(GAUDI2_QUEUE_ID_DCORE1_MME_0_2),
+	__stringify(GAUDI2_QUEUE_ID_DCORE1_MME_0_3),
+	__stringify(GAUDI2_QUEUE_ID_DCORE1_TPC_0_0),
+	__stringify(GAUDI2_QUEUE_ID_DCORE1_TPC_0_1),
+	__stringify(GAUDI2_QUEUE_ID_DCORE1_TPC_0_2),
+	__stringify(GAUDI2_QUEUE_ID_DCORE1_TPC_0_3),
+	__stringify(GAUDI2_QUEUE_ID_DCORE1_TPC_1_0),
+	__stringify(GAUDI2_QUEUE_ID_DCORE1_TPC_1_1),
+	__stringify(GAUDI2_QUEUE_ID_DCORE1_TPC_1_2),
+	__stringify(GAUDI2_QUEUE_ID_DCORE1_TPC_1_3),
+	__stringify(GAUDI2_QUEUE_ID_DCORE1_TPC_2_0),
+	__stringify(GAUDI2_QUEUE_ID_DCORE1_TPC_2_1),
+	__stringify(GAUDI2_QUEUE_ID_DCORE1_TPC_2_2),
+	__stringify(GAUDI2_QUEUE_ID_DCORE1_TPC_2_3),
+	__stringify(GAUDI2_QUEUE_ID_DCORE1_TPC_3_0),
+	__stringify(GAUDI2_QUEUE_ID_DCORE1_TPC_3_1),
+	__stringify(GAUDI2_QUEUE_ID_DCORE1_TPC_3_2),
+	__stringify(GAUDI2_QUEUE_ID_DCORE1_TPC_3_3),
+	__stringify(GAUDI2_QUEUE_ID_DCORE1_TPC_4_0),
+	__stringify(GAUDI2_QUEUE_ID_DCORE1_TPC_4_1),
+	__stringify(GAUDI2_QUEUE_ID_DCORE1_TPC_4_2),
+	__stringify(GAUDI2_QUEUE_ID_DCORE1_TPC_4_3),
+	__stringify(GAUDI2_QUEUE_ID_DCORE1_TPC_5_0),
+	__stringify(GAUDI2_QUEUE_ID_DCORE1_TPC_5_1),
+	__stringify(GAUDI2_QUEUE_ID_DCORE1_TPC_5_2),
+	__stringify(GAUDI2_QUEUE_ID_DCORE1_TPC_5_3),
+	__stringify(GAUDI2_QUEUE_ID_DCORE2_EDMA_0_0),
+	__stringify(GAUDI2_QUEUE_ID_DCORE2_EDMA_0_1),
+	__stringify(GAUDI2_QUEUE_ID_DCORE2_EDMA_0_2),
+	__stringify(GAUDI2_QUEUE_ID_DCORE2_EDMA_0_3),
+	__stringify(GAUDI2_QUEUE_ID_DCORE2_EDMA_1_0),
+	__stringify(GAUDI2_QUEUE_ID_DCORE2_EDMA_1_1),
+	__stringify(GAUDI2_QUEUE_ID_DCORE2_EDMA_1_2),
+	__stringify(GAUDI2_QUEUE_ID_DCORE2_EDMA_1_3),
+	__stringify(GAUDI2_QUEUE_ID_DCORE2_MME_0_0),
+	__stringify(GAUDI2_QUEUE_ID_DCORE2_MME_0_1),
+	__stringify(GAUDI2_QUEUE_ID_DCORE2_MME_0_2),
+	__stringify(GAUDI2_QUEUE_ID_DCORE2_MME_0_3),
+	__stringify(GAUDI2_QUEUE_ID_DCORE2_TPC_0_0),
+	__stringify(GAUDI2_QUEUE_ID_DCORE2_TPC_0_1),
+	__stringify(GAUDI2_QUEUE_ID_DCORE2_TPC_0_2),
+	__stringify(GAUDI2_QUEUE_ID_DCORE2_TPC_0_3),
+	__stringify(GAUDI2_QUEUE_ID_DCORE2_TPC_1_0),
+	__stringify(GAUDI2_QUEUE_ID_DCORE2_TPC_1_1),
+	__stringify(GAUDI2_QUEUE_ID_DCORE2_TPC_1_2),
+	__stringify(GAUDI2_QUEUE_ID_DCORE2_TPC_1_3),
+	__stringify(GAUDI2_QUEUE_ID_DCORE2_TPC_2_0),
+	__stringify(GAUDI2_QUEUE_ID_DCORE2_TPC_2_1),
+	__stringify(GAUDI2_QUEUE_ID_DCORE2_TPC_2_2),
+	__stringify(GAUDI2_QUEUE_ID_DCORE2_TPC_2_3),
+	__stringify(GAUDI2_QUEUE_ID_DCORE2_TPC_3_0),
+	__stringify(GAUDI2_QUEUE_ID_DCORE2_TPC_3_1),
+	__stringify(GAUDI2_QUEUE_ID_DCORE2_TPC_3_2),
+	__stringify(GAUDI2_QUEUE_ID_DCORE2_TPC_3_3),
+	__stringify(GAUDI2_QUEUE_ID_DCORE2_TPC_4_0),
+	__stringify(GAUDI2_QUEUE_ID_DCORE2_TPC_4_1),
+	__stringify(GAUDI2_QUEUE_ID_DCORE2_TPC_4_2),
+	__stringify(GAUDI2_QUEUE_ID_DCORE2_TPC_4_3),
+	__stringify(GAUDI2_QUEUE_ID_DCORE2_TPC_5_0),
+	__stringify(GAUDI2_QUEUE_ID_DCORE2_TPC_5_1),
+	__stringify(GAUDI2_QUEUE_ID_DCORE2_TPC_5_2),
+	__stringify(GAUDI2_QUEUE_ID_DCORE2_TPC_5_3),
+	__stringify(GAUDI2_QUEUE_ID_DCORE3_EDMA_0_0),
+	__stringify(GAUDI2_QUEUE_ID_DCORE3_EDMA_0_1),
+	__stringify(GAUDI2_QUEUE_ID_DCORE3_EDMA_0_2),
+	__stringify(GAUDI2_QUEUE_ID_DCORE3_EDMA_0_3),
+	__stringify(GAUDI2_QUEUE_ID_DCORE3_EDMA_1_0),
+	__stringify(GAUDI2_QUEUE_ID_DCORE3_EDMA_1_1),
+	__stringify(GAUDI2_QUEUE_ID_DCORE3_EDMA_1_2),
+	__stringify(GAUDI2_QUEUE_ID_DCORE3_EDMA_1_3),
+	__stringify(GAUDI2_QUEUE_ID_DCORE3_MME_0_0),
+	__stringify(GAUDI2_QUEUE_ID_DCORE3_MME_0_1),
+	__stringify(GAUDI2_QUEUE_ID_DCORE3_MME_0_2),
+	__stringify(GAUDI2_QUEUE_ID_DCORE3_MME_0_3),
+	__stringify(GAUDI2_QUEUE_ID_DCORE3_TPC_0_0),
+	__stringify(GAUDI2_QUEUE_ID_DCORE3_TPC_0_1),
+	__stringify(GAUDI2_QUEUE_ID_DCORE3_TPC_0_2),
+	__stringify(GAUDI2_QUEUE_ID_DCORE3_TPC_0_3),
+	__stringify(GAUDI2_QUEUE_ID_DCORE3_TPC_1_0),
+	__stringify(GAUDI2_QUEUE_ID_DCORE3_TPC_1_1),
+	__stringify(GAUDI2_QUEUE_ID_DCORE3_TPC_1_2),
+	__stringify(GAUDI2_QUEUE_ID_DCORE3_TPC_1_3),
+	__stringify(GAUDI2_QUEUE_ID_DCORE3_TPC_2_0),
+	__stringify(GAUDI2_QUEUE_ID_DCORE3_TPC_2_1),
+	__stringify(GAUDI2_QUEUE_ID_DCORE3_TPC_2_2),
+	__stringify(GAUDI2_QUEUE_ID_DCORE3_TPC_2_3),
+	__stringify(GAUDI2_QUEUE_ID_DCORE3_TPC_3_0),
+	__stringify(GAUDI2_QUEUE_ID_DCORE3_TPC_3_1),
+	__stringify(GAUDI2_QUEUE_ID_DCORE3_TPC_3_2),
+	__stringify(GAUDI2_QUEUE_ID_DCORE3_TPC_3_3),
+	__stringify(GAUDI2_QUEUE_ID_DCORE3_TPC_4_0),
+	__stringify(GAUDI2_QUEUE_ID_DCORE3_TPC_4_1),
+	__stringify(GAUDI2_QUEUE_ID_DCORE3_TPC_4_2),
+	__stringify(GAUDI2_QUEUE_ID_DCORE3_TPC_4_3),
+	__stringify(GAUDI2_QUEUE_ID_DCORE3_TPC_5_0),
+	__stringify(GAUDI2_QUEUE_ID_DCORE3_TPC_5_1),
+	__stringify(GAUDI2_QUEUE_ID_DCORE3_TPC_5_2),
+	__stringify(GAUDI2_QUEUE_ID_DCORE3_TPC_5_3),
+	__stringify(GAUDI2_QUEUE_ID_NIC_0_0),
+	__stringify(GAUDI2_QUEUE_ID_NIC_0_1),
+	__stringify(GAUDI2_QUEUE_ID_NIC_0_2),
+	__stringify(GAUDI2_QUEUE_ID_NIC_0_3),
+	__stringify(GAUDI2_QUEUE_ID_NIC_1_0),
+	__stringify(GAUDI2_QUEUE_ID_NIC_1_1),
+	__stringify(GAUDI2_QUEUE_ID_NIC_1_2),
+	__stringify(GAUDI2_QUEUE_ID_NIC_1_3),
+	__stringify(GAUDI2_QUEUE_ID_NIC_2_0),
+	__stringify(GAUDI2_QUEUE_ID_NIC_2_1),
+	__stringify(GAUDI2_QUEUE_ID_NIC_2_2),
+	__stringify(GAUDI2_QUEUE_ID_NIC_2_3),
+	__stringify(GAUDI2_QUEUE_ID_NIC_3_0),
+	__stringify(GAUDI2_QUEUE_ID_NIC_3_1),
+	__stringify(GAUDI2_QUEUE_ID_NIC_3_2),
+	__stringify(GAUDI2_QUEUE_ID_NIC_3_3),
+	__stringify(GAUDI2_QUEUE_ID_NIC_4_0),
+	__stringify(GAUDI2_QUEUE_ID_NIC_4_1),
+	__stringify(GAUDI2_QUEUE_ID_NIC_4_2),
+	__stringify(GAUDI2_QUEUE_ID_NIC_4_3),
+	__stringify(GAUDI2_QUEUE_ID_NIC_5_0),
+	__stringify(GAUDI2_QUEUE_ID_NIC_5_1),
+	__stringify(GAUDI2_QUEUE_ID_NIC_5_2),
+	__stringify(GAUDI2_QUEUE_ID_NIC_5_3),
+	__stringify(GAUDI2_QUEUE_ID_NIC_6_0),
+	__stringify(GAUDI2_QUEUE_ID_NIC_6_1),
+	__stringify(GAUDI2_QUEUE_ID_NIC_6_2),
+	__stringify(GAUDI2_QUEUE_ID_NIC_6_3),
+	__stringify(GAUDI2_QUEUE_ID_NIC_7_0),
+	__stringify(GAUDI2_QUEUE_ID_NIC_7_1),
+	__stringify(GAUDI2_QUEUE_ID_NIC_7_2),
+	__stringify(GAUDI2_QUEUE_ID_NIC_7_3),
+	__stringify(GAUDI2_QUEUE_ID_NIC_8_0),
+	__stringify(GAUDI2_QUEUE_ID_NIC_8_1),
+	__stringify(GAUDI2_QUEUE_ID_NIC_8_2),
+	__stringify(GAUDI2_QUEUE_ID_NIC_8_3),
+	__stringify(GAUDI2_QUEUE_ID_NIC_9_0),
+	__stringify(GAUDI2_QUEUE_ID_NIC_9_1),
+	__stringify(GAUDI2_QUEUE_ID_NIC_9_2),
+	__stringify(GAUDI2_QUEUE_ID_NIC_9_3),
+	__stringify(GAUDI2_QUEUE_ID_NIC_10_0),
+	__stringify(GAUDI2_QUEUE_ID_NIC_10_1),
+	__stringify(GAUDI2_QUEUE_ID_NIC_10_2),
+	__stringify(GAUDI2_QUEUE_ID_NIC_10_3),
+	__stringify(GAUDI2_QUEUE_ID_NIC_11_0),
+	__stringify(GAUDI2_QUEUE_ID_NIC_11_1),
+	__stringify(GAUDI2_QUEUE_ID_NIC_11_2),
+	__stringify(GAUDI2_QUEUE_ID_NIC_11_3),
+	__stringify(GAUDI2_QUEUE_ID_NIC_12_0),
+	__stringify(GAUDI2_QUEUE_ID_NIC_12_1),
+	__stringify(GAUDI2_QUEUE_ID_NIC_12_2),
+	__stringify(GAUDI2_QUEUE_ID_NIC_12_3),
+	__stringify(GAUDI2_QUEUE_ID_NIC_13_0),
+	__stringify(GAUDI2_QUEUE_ID_NIC_13_1),
+	__stringify(GAUDI2_QUEUE_ID_NIC_13_2),
+	__stringify(GAUDI2_QUEUE_ID_NIC_13_3),
+	__stringify(GAUDI2_QUEUE_ID_NIC_14_0),
+	__stringify(GAUDI2_QUEUE_ID_NIC_14_1),
+	__stringify(GAUDI2_QUEUE_ID_NIC_14_2),
+	__stringify(GAUDI2_QUEUE_ID_NIC_14_3),
+	__stringify(GAUDI2_QUEUE_ID_NIC_15_0),
+	__stringify(GAUDI2_QUEUE_ID_NIC_15_1),
+	__stringify(GAUDI2_QUEUE_ID_NIC_15_2),
+	__stringify(GAUDI2_QUEUE_ID_NIC_15_3),
+	__stringify(GAUDI2_QUEUE_ID_NIC_16_0),
+	__stringify(GAUDI2_QUEUE_ID_NIC_16_1),
+	__stringify(GAUDI2_QUEUE_ID_NIC_16_2),
+	__stringify(GAUDI2_QUEUE_ID_NIC_16_3),
+	__stringify(GAUDI2_QUEUE_ID_NIC_17_0),
+	__stringify(GAUDI2_QUEUE_ID_NIC_17_1),
+	__stringify(GAUDI2_QUEUE_ID_NIC_17_2),
+	__stringify(GAUDI2_QUEUE_ID_NIC_17_3),
+	__stringify(GAUDI2_QUEUE_ID_NIC_18_0),
+	__stringify(GAUDI2_QUEUE_ID_NIC_18_1),
+	__stringify(GAUDI2_QUEUE_ID_NIC_18_2),
+	__stringify(GAUDI2_QUEUE_ID_NIC_18_3),
+	__stringify(GAUDI2_QUEUE_ID_NIC_19_0),
+	__stringify(GAUDI2_QUEUE_ID_NIC_19_1),
+	__stringify(GAUDI2_QUEUE_ID_NIC_19_2),
+	__stringify(GAUDI2_QUEUE_ID_NIC_19_3),
+	__stringify(GAUDI2_QUEUE_ID_NIC_20_0),
+	__stringify(GAUDI2_QUEUE_ID_NIC_20_1),
+	__stringify(GAUDI2_QUEUE_ID_NIC_20_2),
+	__stringify(GAUDI2_QUEUE_ID_NIC_20_3),
+	__stringify(GAUDI2_QUEUE_ID_NIC_21_0),
+	__stringify(GAUDI2_QUEUE_ID_NIC_21_1),
+	__stringify(GAUDI2_QUEUE_ID_NIC_21_2),
+	__stringify(GAUDI2_QUEUE_ID_NIC_21_3),
+	__stringify(GAUDI2_QUEUE_ID_NIC_22_0),
+	__stringify(GAUDI2_QUEUE_ID_NIC_22_1),
+	__stringify(GAUDI2_QUEUE_ID_NIC_22_2),
+	__stringify(GAUDI2_QUEUE_ID_NIC_22_3),
+	__stringify(GAUDI2_QUEUE_ID_NIC_23_0),
+	__stringify(GAUDI2_QUEUE_ID_NIC_23_1),
+	__stringify(GAUDI2_QUEUE_ID_NIC_23_2),
+	__stringify(GAUDI2_QUEUE_ID_NIC_23_3),
+	__stringify(GAUDI2_QUEUE_ID_ROT_0_0),
+	__stringify(GAUDI2_QUEUE_ID_ROT_0_1),
+	__stringify(GAUDI2_QUEUE_ID_ROT_0_2),
+	__stringify(GAUDI2_QUEUE_ID_ROT_0_3),
+	__stringify(GAUDI2_QUEUE_ID_ROT_1_0),
+	__stringify(GAUDI2_QUEUE_ID_ROT_1_1),
+	__stringify(GAUDI2_QUEUE_ID_ROT_1_2),
+	__stringify(GAUDI2_QUEUE_ID_ROT_1_3),
+	__stringify(GAUDI2_QUEUE_ID_CPU_PQ),
+	__stringify(GAUDI2_QUEUE_ID_SIZE),
+};
+
+static const char * const gaudi2_qm_sei_error_cause[GAUDI2_NUM_OF_QM_SEI_ERR_CAUSE] = {
+	"qman sei intr",
+	"arc sei intr"
+};
+
+static const char * const gaudi2_cpu_sei_error_cause[GAUDI2_NUM_OF_CPU_SEI_ERR_CAUSE] = {
+	"AXI_TERMINATOR WR",
+	"AXI_TERMINATOR RD",
+	"AXI SPLIT SEI Status"
+};
+
+static const char * const gaudi2_arc_sei_error_cause[GAUDI2_NUM_OF_ARC_SEI_ERR_CAUSE] = {
+	"cbu_bresp_sei_intr_cause",
+	"cbu_rresp_sei_intr_cause",
+	"lbu_bresp_sei_intr_cause",
+	"lbu_rresp_sei_intr_cause",
+	"cbu_axi_split_intr_cause",
+	"lbu_axi_split_intr_cause",
+	"arc_ip_excptn_sei_intr_cause",
+	"dmi_bresp_sei_intr_cause",
+	"aux2apb_err_sei_intr_cause",
+	"cfg_lbw_wr_terminated_intr_cause",
+	"cfg_lbw_rd_terminated_intr_cause",
+	"cfg_dccm_wr_terminated_intr_cause",
+	"cfg_dccm_rd_terminated_intr_cause",
+	"cfg_hbw_rd_terminated_intr_cause"
+};
+
+static const char * const gaudi2_dec_error_cause[GAUDI2_NUM_OF_DEC_ERR_CAUSE] = {
+	"msix_vcd_hbw_sei",
+	"msix_l2c_hbw_sei",
+	"msix_nrm_hbw_sei",
+	"msix_abnrm_hbw_sei",
+	"msix_vcd_lbw_sei",
+	"msix_l2c_lbw_sei",
+	"msix_nrm_lbw_sei",
+	"msix_abnrm_lbw_sei",
+	"apb_vcd_lbw_sei",
+	"apb_l2c_lbw_sei",
+	"apb_nrm_lbw_sei",
+	"apb_abnrm_lbw_sei",
+	"dec_sei",
+	"dec_apb_sei",
+	"trc_apb_sei",
+	"lbw_mstr_if_sei",
+	"axi_split_bresp_err_sei",
+	"hbw_axi_wr_viol_sei",
+	"hbw_axi_rd_viol_sei",
+	"lbw_axi_wr_viol_sei",
+	"lbw_axi_rd_viol_sei",
+	"vcd_spi",
+	"l2c_spi",
+	"nrm_spi",
+	"abnrm_spi",
+};
+
+static const char * const gaudi2_qman_error_cause[GAUDI2_NUM_OF_QM_ERR_CAUSE] = {
+	"PQ AXI HBW error",
+	"CQ AXI HBW error",
+	"CP AXI HBW error",
+	"CP error due to undefined OPCODE",
+	"CP encountered STOP OPCODE",
+	"CP AXI LBW error",
+	"CP WRREG32 or WRBULK returned error",
+	"N/A",
+	"FENCE 0 inc over max value and clipped",
+	"FENCE 1 inc over max value and clipped",
+	"FENCE 2 inc over max value and clipped",
+	"FENCE 3 inc over max value and clipped",
+	"FENCE 0 dec under min value and clipped",
+	"FENCE 1 dec under min value and clipped",
+	"FENCE 2 dec under min value and clipped",
+	"FENCE 3 dec under min value and clipped",
+	"CPDMA Up overflow",
+	"PQC L2H error"
+};
+
+static const char * const gaudi2_lower_qman_error_cause[GAUDI2_NUM_OF_LOWER_QM_ERR_CAUSE] = {
+	"RSVD0",
+	"CQ AXI HBW error",
+	"CP AXI HBW error",
+	"CP error due to undefined OPCODE",
+	"CP encountered STOP OPCODE",
+	"CP AXI LBW error",
+	"CP WRREG32 or WRBULK returned error",
+	"N/A",
+	"FENCE 0 inc over max value and clipped",
+	"FENCE 1 inc over max value and clipped",
+	"FENCE 2 inc over max value and clipped",
+	"FENCE 3 inc over max value and clipped",
+	"FENCE 0 dec under min value and clipped",
+	"FENCE 1 dec under min value and clipped",
+	"FENCE 2 dec under min value and clipped",
+	"FENCE 3 dec under min value and clipped",
+	"CPDMA Up overflow",
+	"RSVD17",
+	"CQ_WR_IFIFO_CI_ERR",
+	"CQ_WR_CTL_CI_ERR",
+	"ARC_CQF_RD_ERR",
+	"ARC_CQ_WR_IFIFO_CI_ERR",
+	"ARC_CQ_WR_CTL_CI_ERR",
+	"ARC_AXI_ERR",
+	"CP_SWITCH_WDT_ERR"
+};
+
+static const char * const gaudi2_qman_arb_error_cause[GAUDI2_NUM_OF_QM_ARB_ERR_CAUSE] = {
+	"Choice push while full error",
+	"Choice Q watchdog error",
+	"MSG AXI LBW returned with error"
+};
+
+static const char * const guadi2_rot_error_cause[GAUDI2_NUM_OF_ROT_ERR_CAUSE] = {
+	"qm_axi_err",
+	"qm_trace_fence_events",
+	"qm_sw_err",
+	"qm_cp_sw_stop",
+	"lbw_mstr_rresp_err",
+	"lbw_mstr_bresp_err",
+	"lbw_msg_slverr",
+	"hbw_msg_slverr",
+	"wbc_slverr",
+	"hbw_mstr_rresp_err",
+	"hbw_mstr_bresp_err",
+	"sb_resp_intr",
+	"mrsb_resp_intr",
+	"core_dw_status_0",
+	"core_dw_status_1",
+	"core_dw_status_2",
+	"core_dw_status_3",
+	"core_dw_status_4",
+	"core_dw_status_5",
+	"core_dw_status_6",
+	"core_dw_status_7",
+	"async_arc2cpu_sei_intr",
+};
+
+static const char * const gaudi2_tpc_interrupts_cause[GAUDI2_NUM_OF_TPC_INTR_CAUSE] = {
+	"tpc_address_exceed_slm",
+	"tpc_div_by_0",
+	"tpc_spu_mac_overflow",
+	"tpc_spu_addsub_overflow",
+	"tpc_spu_abs_overflow",
+	"tpc_spu_fma_fp_dst_nan",
+	"tpc_spu_fma_fp_dst_inf",
+	"tpc_spu_convert_fp_dst_nan",
+	"tpc_spu_convert_fp_dst_inf",
+	"tpc_spu_fp_dst_denorm",
+	"tpc_vpu_mac_overflow",
+	"tpc_vpu_addsub_overflow",
+	"tpc_vpu_abs_overflow",
+	"tpc_vpu_convert_fp_dst_nan",
+	"tpc_vpu_convert_fp_dst_inf",
+	"tpc_vpu_fma_fp_dst_nan",
+	"tpc_vpu_fma_fp_dst_inf",
+	"tpc_vpu_fp_dst_denorm",
+	"tpc_assertions",
+	"tpc_illegal_instruction",
+	"tpc_pc_wrap_around",
+	"tpc_qm_sw_err",
+	"tpc_hbw_rresp_err",
+	"tpc_hbw_bresp_err",
+	"tpc_lbw_rresp_err",
+	"tpc_lbw_bresp_err",
+	"st_unlock_already_locked",
+	"invalid_lock_access",
+	"LD_L protection violation",
+	"ST_L protection violation",
+	"D$ L0CS mismatch",
+};
+
+static const char * const guadi2_mme_error_cause[GAUDI2_NUM_OF_MME_ERR_CAUSE] = {
+	"agu_resp_intr",
+	"qman_axi_err",
+	"wap sei (wbc axi err)",
+	"arc sei",
+	"cfg access error",
+	"qm_sw_err",
+	"sbte_dbg_intr_0",
+	"sbte_dbg_intr_1",
+	"sbte_dbg_intr_2",
+	"sbte_dbg_intr_3",
+	"sbte_dbg_intr_4",
+	"sbte_prtn_intr_0",
+	"sbte_prtn_intr_1",
+	"sbte_prtn_intr_2",
+	"sbte_prtn_intr_3",
+	"sbte_prtn_intr_4",
+};
+
+static const char * const guadi2_mme_wap_error_cause[GAUDI2_NUM_OF_MME_WAP_ERR_CAUSE] = {
+	"WBC ERR RESP_0",
+	"WBC ERR RESP_1",
+	"AP SOURCE POS INF",
+	"AP SOURCE NEG INF",
+	"AP SOURCE NAN",
+	"AP RESULT POS INF",
+	"AP RESULT NEG INF",
+};
+
+static const char * const gaudi2_dma_core_interrupts_cause[GAUDI2_NUM_OF_DMA_CORE_INTR_CAUSE] = {
+	"HBW Read returned with error RRESP",
+	"HBW write returned with error BRESP",
+	"LBW write returned with error BRESP",
+	"descriptor_fifo_overflow",
+	"KDMA SB LBW Read returned with error",
+	"KDMA WBC LBW Write returned with error",
+	"TRANSPOSE ENGINE DESC FIFO OVERFLOW",
+	"WRONG CFG FOR COMMIT IN LIN DMA"
+};
+
+static const char * const gaudi2_kdma_core_interrupts_cause[GAUDI2_NUM_OF_DMA_CORE_INTR_CAUSE] = {
+	"HBW/LBW Read returned with error RRESP",
+	"HBW/LBW write returned with error BRESP",
+	"LBW write returned with error BRESP",
+	"descriptor_fifo_overflow",
+	"KDMA SB LBW Read returned with error",
+	"KDMA WBC LBW Write returned with error",
+	"TRANSPOSE ENGINE DESC FIFO OVERFLOW",
+	"WRONG CFG FOR COMMIT IN LIN DMA"
+};
+
+struct gaudi2_sm_sei_cause_data {
+	const char *cause_name;
+	const char *log_name;
+};
+
+static const struct gaudi2_sm_sei_cause_data
+gaudi2_sm_sei_cause[GAUDI2_NUM_OF_SM_SEI_ERR_CAUSE] = {
+	{"calculated SO value overflow/underflow", "SOB ID"},
+	{"payload address of monitor is not aligned to 4B", "monitor addr"},
+	{"armed monitor write got BRESP (SLVERR or DECERR)", "AXI id"},
+};
+
+static const char * const
+gaudi2_pmmu_fatal_interrupts_cause[GAUDI2_NUM_OF_PMMU_FATAL_ERR_CAUSE] = {
+	"LATENCY_RD_OUT_FIFO_OVERRUN",
+	"LATENCY_WR_OUT_FIFO_OVERRUN",
+};
+
+static const char * const
+gaudi2_hif_fatal_interrupts_cause[GAUDI2_NUM_OF_HIF_FATAL_ERR_CAUSE] = {
+	"LATENCY_RD_OUT_FIFO_OVERRUN",
+	"LATENCY_WR_OUT_FIFO_OVERRUN",
+};
+
+static const char * const
+gaudi2_psoc_axi_drain_interrupts_cause[GAUDI2_NUM_OF_AXI_DRAIN_ERR_CAUSE] = {
+	"AXI drain HBW",
+	"AXI drain LBW",
+};
+
+static const char * const
+gaudi2_pcie_addr_dec_error_cause[GAUDI2_NUM_OF_PCIE_ADDR_DEC_ERR_CAUSE] = {
+	"HBW error response",
+	"LBW error response",
+	"TLP is blocked by RR"
+};
+
+static const int gaudi2_queue_id_to_engine_id[] = {
+	[GAUDI2_QUEUE_ID_PDMA_0_0...GAUDI2_QUEUE_ID_PDMA_0_3] = GAUDI2_ENGINE_ID_PDMA_0,
+	[GAUDI2_QUEUE_ID_PDMA_1_0...GAUDI2_QUEUE_ID_PDMA_1_3] = GAUDI2_ENGINE_ID_PDMA_1,
+	[GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0...GAUDI2_QUEUE_ID_DCORE0_EDMA_0_3] =
+							GAUDI2_DCORE0_ENGINE_ID_EDMA_0,
+	[GAUDI2_QUEUE_ID_DCORE0_EDMA_1_0...GAUDI2_QUEUE_ID_DCORE0_EDMA_1_3] =
+							GAUDI2_DCORE0_ENGINE_ID_EDMA_1,
+	[GAUDI2_QUEUE_ID_DCORE1_EDMA_0_0...GAUDI2_QUEUE_ID_DCORE1_EDMA_0_3] =
+							GAUDI2_DCORE1_ENGINE_ID_EDMA_0,
+	[GAUDI2_QUEUE_ID_DCORE1_EDMA_1_0...GAUDI2_QUEUE_ID_DCORE1_EDMA_1_3] =
+							GAUDI2_DCORE1_ENGINE_ID_EDMA_1,
+	[GAUDI2_QUEUE_ID_DCORE2_EDMA_0_0...GAUDI2_QUEUE_ID_DCORE2_EDMA_0_3] =
+							GAUDI2_DCORE2_ENGINE_ID_EDMA_0,
+	[GAUDI2_QUEUE_ID_DCORE2_EDMA_1_0...GAUDI2_QUEUE_ID_DCORE2_EDMA_1_3] =
+							GAUDI2_DCORE2_ENGINE_ID_EDMA_1,
+	[GAUDI2_QUEUE_ID_DCORE3_EDMA_0_0...GAUDI2_QUEUE_ID_DCORE3_EDMA_0_3] =
+							GAUDI2_DCORE3_ENGINE_ID_EDMA_0,
+	[GAUDI2_QUEUE_ID_DCORE3_EDMA_1_0...GAUDI2_QUEUE_ID_DCORE3_EDMA_1_3] =
+							GAUDI2_DCORE3_ENGINE_ID_EDMA_1,
+	[GAUDI2_QUEUE_ID_DCORE0_MME_0_0...GAUDI2_QUEUE_ID_DCORE0_MME_0_3] =
+							GAUDI2_DCORE0_ENGINE_ID_MME,
+	[GAUDI2_QUEUE_ID_DCORE1_MME_0_0...GAUDI2_QUEUE_ID_DCORE1_MME_0_3] =
+							GAUDI2_DCORE1_ENGINE_ID_MME,
+	[GAUDI2_QUEUE_ID_DCORE2_MME_0_0...GAUDI2_QUEUE_ID_DCORE2_MME_0_3] =
+							GAUDI2_DCORE2_ENGINE_ID_MME,
+	[GAUDI2_QUEUE_ID_DCORE3_MME_0_0...GAUDI2_QUEUE_ID_DCORE3_MME_0_3] =
+							GAUDI2_DCORE3_ENGINE_ID_MME,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_0_0...GAUDI2_QUEUE_ID_DCORE0_TPC_0_3] =
+							GAUDI2_DCORE0_ENGINE_ID_TPC_0,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_1_0...GAUDI2_QUEUE_ID_DCORE0_TPC_1_3] =
+							GAUDI2_DCORE0_ENGINE_ID_TPC_1,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_2_0...GAUDI2_QUEUE_ID_DCORE0_TPC_2_3] =
+							GAUDI2_DCORE0_ENGINE_ID_TPC_2,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_3_0...GAUDI2_QUEUE_ID_DCORE0_TPC_3_3] =
+							GAUDI2_DCORE0_ENGINE_ID_TPC_3,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_4_0...GAUDI2_QUEUE_ID_DCORE0_TPC_4_3] =
+							GAUDI2_DCORE0_ENGINE_ID_TPC_4,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_5_0...GAUDI2_QUEUE_ID_DCORE0_TPC_5_3] =
+							GAUDI2_DCORE0_ENGINE_ID_TPC_5,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_6_0...GAUDI2_QUEUE_ID_DCORE0_TPC_6_3] =
+							GAUDI2_DCORE0_ENGINE_ID_TPC_6,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_0_0...GAUDI2_QUEUE_ID_DCORE1_TPC_0_3] =
+							GAUDI2_DCORE1_ENGINE_ID_TPC_0,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_1_0...GAUDI2_QUEUE_ID_DCORE1_TPC_1_3] =
+							GAUDI2_DCORE1_ENGINE_ID_TPC_1,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_2_0...GAUDI2_QUEUE_ID_DCORE1_TPC_2_3] =
+							GAUDI2_DCORE1_ENGINE_ID_TPC_2,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_3_0...GAUDI2_QUEUE_ID_DCORE1_TPC_3_3] =
+							GAUDI2_DCORE1_ENGINE_ID_TPC_3,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_4_0...GAUDI2_QUEUE_ID_DCORE1_TPC_4_3] =
+							GAUDI2_DCORE1_ENGINE_ID_TPC_4,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_5_0...GAUDI2_QUEUE_ID_DCORE1_TPC_5_3] =
+							GAUDI2_DCORE1_ENGINE_ID_TPC_5,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_0_0...GAUDI2_QUEUE_ID_DCORE2_TPC_0_3] =
+							GAUDI2_DCORE2_ENGINE_ID_TPC_0,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_1_0...GAUDI2_QUEUE_ID_DCORE2_TPC_1_3] =
+							GAUDI2_DCORE2_ENGINE_ID_TPC_1,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_2_0...GAUDI2_QUEUE_ID_DCORE2_TPC_2_3] =
+							GAUDI2_DCORE2_ENGINE_ID_TPC_2,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_3_0...GAUDI2_QUEUE_ID_DCORE2_TPC_3_3] =
+							GAUDI2_DCORE2_ENGINE_ID_TPC_3,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_4_0...GAUDI2_QUEUE_ID_DCORE2_TPC_4_3] =
+							GAUDI2_DCORE2_ENGINE_ID_TPC_4,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_5_0...GAUDI2_QUEUE_ID_DCORE2_TPC_5_3] =
+							GAUDI2_DCORE2_ENGINE_ID_TPC_5,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_0_0...GAUDI2_QUEUE_ID_DCORE3_TPC_0_3] =
+							GAUDI2_DCORE3_ENGINE_ID_TPC_0,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_1_0...GAUDI2_QUEUE_ID_DCORE3_TPC_1_3] =
+							GAUDI2_DCORE3_ENGINE_ID_TPC_1,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_2_0...GAUDI2_QUEUE_ID_DCORE3_TPC_2_3] =
+							GAUDI2_DCORE3_ENGINE_ID_TPC_2,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_3_0...GAUDI2_QUEUE_ID_DCORE3_TPC_3_3] =
+							GAUDI2_DCORE3_ENGINE_ID_TPC_3,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_4_0...GAUDI2_QUEUE_ID_DCORE3_TPC_4_3] =
+							GAUDI2_DCORE3_ENGINE_ID_TPC_4,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_5_0...GAUDI2_QUEUE_ID_DCORE3_TPC_5_3] =
+							GAUDI2_DCORE3_ENGINE_ID_TPC_5,
+	[GAUDI2_QUEUE_ID_NIC_0_0...GAUDI2_QUEUE_ID_NIC_0_3] = GAUDI2_ENGINE_ID_NIC0_0,
+	[GAUDI2_QUEUE_ID_NIC_1_0...GAUDI2_QUEUE_ID_NIC_1_3] = GAUDI2_ENGINE_ID_NIC0_1,
+	[GAUDI2_QUEUE_ID_NIC_2_0...GAUDI2_QUEUE_ID_NIC_2_3] = GAUDI2_ENGINE_ID_NIC1_0,
+	[GAUDI2_QUEUE_ID_NIC_3_0...GAUDI2_QUEUE_ID_NIC_3_3] = GAUDI2_ENGINE_ID_NIC1_1,
+	[GAUDI2_QUEUE_ID_NIC_4_0...GAUDI2_QUEUE_ID_NIC_4_3] = GAUDI2_ENGINE_ID_NIC2_0,
+	[GAUDI2_QUEUE_ID_NIC_5_0...GAUDI2_QUEUE_ID_NIC_5_3] = GAUDI2_ENGINE_ID_NIC2_1,
+	[GAUDI2_QUEUE_ID_NIC_6_0...GAUDI2_QUEUE_ID_NIC_6_3] = GAUDI2_ENGINE_ID_NIC3_0,
+	[GAUDI2_QUEUE_ID_NIC_7_0...GAUDI2_QUEUE_ID_NIC_7_3] = GAUDI2_ENGINE_ID_NIC3_1,
+	[GAUDI2_QUEUE_ID_NIC_8_0...GAUDI2_QUEUE_ID_NIC_8_3] = GAUDI2_ENGINE_ID_NIC4_0,
+	[GAUDI2_QUEUE_ID_NIC_9_0...GAUDI2_QUEUE_ID_NIC_9_3] = GAUDI2_ENGINE_ID_NIC4_1,
+	[GAUDI2_QUEUE_ID_NIC_10_0...GAUDI2_QUEUE_ID_NIC_10_3] = GAUDI2_ENGINE_ID_NIC5_0,
+	[GAUDI2_QUEUE_ID_NIC_11_0...GAUDI2_QUEUE_ID_NIC_11_3] = GAUDI2_ENGINE_ID_NIC5_1,
+	[GAUDI2_QUEUE_ID_NIC_12_0...GAUDI2_QUEUE_ID_NIC_12_3] = GAUDI2_ENGINE_ID_NIC6_0,
+	[GAUDI2_QUEUE_ID_NIC_13_0...GAUDI2_QUEUE_ID_NIC_13_3] = GAUDI2_ENGINE_ID_NIC6_1,
+	[GAUDI2_QUEUE_ID_NIC_14_0...GAUDI2_QUEUE_ID_NIC_14_3] = GAUDI2_ENGINE_ID_NIC7_0,
+	[GAUDI2_QUEUE_ID_NIC_15_0...GAUDI2_QUEUE_ID_NIC_15_3] = GAUDI2_ENGINE_ID_NIC7_1,
+	[GAUDI2_QUEUE_ID_NIC_16_0...GAUDI2_QUEUE_ID_NIC_16_3] = GAUDI2_ENGINE_ID_NIC8_0,
+	[GAUDI2_QUEUE_ID_NIC_17_0...GAUDI2_QUEUE_ID_NIC_17_3] = GAUDI2_ENGINE_ID_NIC8_1,
+	[GAUDI2_QUEUE_ID_NIC_18_0...GAUDI2_QUEUE_ID_NIC_18_3] = GAUDI2_ENGINE_ID_NIC9_0,
+	[GAUDI2_QUEUE_ID_NIC_19_0...GAUDI2_QUEUE_ID_NIC_19_3] = GAUDI2_ENGINE_ID_NIC9_1,
+	[GAUDI2_QUEUE_ID_NIC_20_0...GAUDI2_QUEUE_ID_NIC_20_3] = GAUDI2_ENGINE_ID_NIC10_0,
+	[GAUDI2_QUEUE_ID_NIC_21_0...GAUDI2_QUEUE_ID_NIC_21_3] = GAUDI2_ENGINE_ID_NIC10_1,
+	[GAUDI2_QUEUE_ID_NIC_22_0...GAUDI2_QUEUE_ID_NIC_22_3] = GAUDI2_ENGINE_ID_NIC11_0,
+	[GAUDI2_QUEUE_ID_NIC_23_0...GAUDI2_QUEUE_ID_NIC_23_3] = GAUDI2_ENGINE_ID_NIC11_1,
+	[GAUDI2_QUEUE_ID_ROT_0_0...GAUDI2_QUEUE_ID_ROT_0_3] = GAUDI2_ENGINE_ID_ROT_0,
+	[GAUDI2_QUEUE_ID_ROT_1_0...GAUDI2_QUEUE_ID_ROT_1_3] = GAUDI2_ENGINE_ID_ROT_1,
+};
+
+const u32 gaudi2_qm_blocks_bases[GAUDI2_QUEUE_ID_SIZE] = {
+	[GAUDI2_QUEUE_ID_PDMA_0_0] = mmPDMA0_QM_BASE,
+	[GAUDI2_QUEUE_ID_PDMA_0_1] = mmPDMA0_QM_BASE,
+	[GAUDI2_QUEUE_ID_PDMA_0_2] = mmPDMA0_QM_BASE,
+	[GAUDI2_QUEUE_ID_PDMA_0_3] = mmPDMA0_QM_BASE,
+	[GAUDI2_QUEUE_ID_PDMA_1_0] = mmPDMA1_QM_BASE,
+	[GAUDI2_QUEUE_ID_PDMA_1_1] = mmPDMA1_QM_BASE,
+	[GAUDI2_QUEUE_ID_PDMA_1_2] = mmPDMA1_QM_BASE,
+	[GAUDI2_QUEUE_ID_PDMA_1_3] = mmPDMA1_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0] = mmDCORE0_EDMA0_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE0_EDMA_0_1] = mmDCORE0_EDMA0_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE0_EDMA_0_2] = mmDCORE0_EDMA0_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE0_EDMA_0_3] = mmDCORE0_EDMA0_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE0_EDMA_1_0] = mmDCORE0_EDMA1_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE0_EDMA_1_1] = mmDCORE0_EDMA1_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE0_EDMA_1_2] = mmDCORE0_EDMA1_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE0_EDMA_1_3] = mmDCORE0_EDMA1_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE0_MME_0_0] = mmDCORE0_MME_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE0_MME_0_1] = mmDCORE0_MME_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE0_MME_0_2] = mmDCORE0_MME_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE0_MME_0_3] = mmDCORE0_MME_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_0_0] = mmDCORE0_TPC0_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_0_1] = mmDCORE0_TPC0_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_0_2] = mmDCORE0_TPC0_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_0_3] = mmDCORE0_TPC0_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_1_0] = mmDCORE0_TPC1_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_1_1] = mmDCORE0_TPC1_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_1_2] = mmDCORE0_TPC1_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_1_3] = mmDCORE0_TPC1_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_2_0] = mmDCORE0_TPC2_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_2_1] = mmDCORE0_TPC2_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_2_2] = mmDCORE0_TPC2_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_2_3] = mmDCORE0_TPC2_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_3_0] = mmDCORE0_TPC3_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_3_1] = mmDCORE0_TPC3_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_3_2] = mmDCORE0_TPC3_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_3_3] = mmDCORE0_TPC3_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_4_0] = mmDCORE0_TPC4_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_4_1] = mmDCORE0_TPC4_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_4_2] = mmDCORE0_TPC4_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_4_3] = mmDCORE0_TPC4_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_5_0] = mmDCORE0_TPC5_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_5_1] = mmDCORE0_TPC5_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_5_2] = mmDCORE0_TPC5_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_5_3] = mmDCORE0_TPC5_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_6_0] = mmDCORE0_TPC6_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_6_1] = mmDCORE0_TPC6_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_6_2] = mmDCORE0_TPC6_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_6_3] = mmDCORE0_TPC6_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE1_EDMA_0_0] = mmDCORE1_EDMA0_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE1_EDMA_0_1] = mmDCORE1_EDMA0_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE1_EDMA_0_2] = mmDCORE1_EDMA0_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE1_EDMA_0_3] = mmDCORE1_EDMA0_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE1_EDMA_1_0] = mmDCORE1_EDMA1_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE1_EDMA_1_1] = mmDCORE1_EDMA1_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE1_EDMA_1_2] = mmDCORE1_EDMA1_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE1_EDMA_1_3] = mmDCORE1_EDMA1_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE1_MME_0_0] = mmDCORE1_MME_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE1_MME_0_1] = mmDCORE1_MME_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE1_MME_0_2] = mmDCORE1_MME_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE1_MME_0_3] = mmDCORE1_MME_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_0_0] = mmDCORE1_TPC0_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_0_1] = mmDCORE1_TPC0_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_0_2] = mmDCORE1_TPC0_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_0_3] = mmDCORE1_TPC0_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_1_0] = mmDCORE1_TPC1_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_1_1] = mmDCORE1_TPC1_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_1_2] = mmDCORE1_TPC1_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_1_3] = mmDCORE1_TPC1_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_2_0] = mmDCORE1_TPC2_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_2_1] = mmDCORE1_TPC2_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_2_2] = mmDCORE1_TPC2_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_2_3] = mmDCORE1_TPC2_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_3_0] = mmDCORE1_TPC3_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_3_1] = mmDCORE1_TPC3_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_3_2] = mmDCORE1_TPC3_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_3_3] = mmDCORE1_TPC3_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_4_0] = mmDCORE1_TPC4_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_4_1] = mmDCORE1_TPC4_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_4_2] = mmDCORE1_TPC4_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_4_3] = mmDCORE1_TPC4_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_5_0] = mmDCORE1_TPC5_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_5_1] = mmDCORE1_TPC5_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_5_2] = mmDCORE1_TPC5_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_5_3] = mmDCORE1_TPC5_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE2_EDMA_0_0] = mmDCORE2_EDMA0_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE2_EDMA_0_1] = mmDCORE2_EDMA0_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE2_EDMA_0_2] = mmDCORE2_EDMA0_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE2_EDMA_0_3] = mmDCORE2_EDMA0_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE2_EDMA_1_0] = mmDCORE2_EDMA1_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE2_EDMA_1_1] = mmDCORE2_EDMA1_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE2_EDMA_1_2] = mmDCORE2_EDMA1_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE2_EDMA_1_3] = mmDCORE2_EDMA1_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE2_MME_0_0] = mmDCORE2_MME_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE2_MME_0_1] = mmDCORE2_MME_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE2_MME_0_2] = mmDCORE2_MME_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE2_MME_0_3] = mmDCORE2_MME_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_0_0] = mmDCORE2_TPC0_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_0_1] = mmDCORE2_TPC0_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_0_2] = mmDCORE2_TPC0_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_0_3] = mmDCORE2_TPC0_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_1_0] = mmDCORE2_TPC1_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_1_1] = mmDCORE2_TPC1_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_1_2] = mmDCORE2_TPC1_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_1_3] = mmDCORE2_TPC1_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_2_0] = mmDCORE2_TPC2_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_2_1] = mmDCORE2_TPC2_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_2_2] = mmDCORE2_TPC2_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_2_3] = mmDCORE2_TPC2_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_3_0] = mmDCORE2_TPC3_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_3_1] = mmDCORE2_TPC3_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_3_2] = mmDCORE2_TPC3_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_3_3] = mmDCORE2_TPC3_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_4_0] = mmDCORE2_TPC4_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_4_1] = mmDCORE2_TPC4_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_4_2] = mmDCORE2_TPC4_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_4_3] = mmDCORE2_TPC4_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_5_0] = mmDCORE2_TPC5_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_5_1] = mmDCORE2_TPC5_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_5_2] = mmDCORE2_TPC5_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_5_3] = mmDCORE2_TPC5_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE3_EDMA_0_0] = mmDCORE3_EDMA0_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE3_EDMA_0_1] = mmDCORE3_EDMA0_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE3_EDMA_0_2] = mmDCORE3_EDMA0_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE3_EDMA_0_3] = mmDCORE3_EDMA0_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE3_EDMA_1_0] = mmDCORE3_EDMA1_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE3_EDMA_1_1] = mmDCORE3_EDMA1_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE3_EDMA_1_2] = mmDCORE3_EDMA1_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE3_EDMA_1_3] = mmDCORE3_EDMA1_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE3_MME_0_0] = mmDCORE3_MME_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE3_MME_0_1] = mmDCORE3_MME_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE3_MME_0_2] = mmDCORE3_MME_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE3_MME_0_3] = mmDCORE3_MME_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_0_0] = mmDCORE3_TPC0_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_0_1] = mmDCORE3_TPC0_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_0_2] = mmDCORE3_TPC0_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_0_3] = mmDCORE3_TPC0_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_1_0] = mmDCORE3_TPC1_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_1_1] = mmDCORE3_TPC1_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_1_2] = mmDCORE3_TPC1_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_1_3] = mmDCORE3_TPC1_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_2_0] = mmDCORE3_TPC2_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_2_1] = mmDCORE3_TPC2_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_2_2] = mmDCORE3_TPC2_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_2_3] = mmDCORE3_TPC2_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_3_0] = mmDCORE3_TPC3_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_3_1] = mmDCORE3_TPC3_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_3_2] = mmDCORE3_TPC3_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_3_3] = mmDCORE3_TPC3_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_4_0] = mmDCORE3_TPC4_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_4_1] = mmDCORE3_TPC4_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_4_2] = mmDCORE3_TPC4_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_4_3] = mmDCORE3_TPC4_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_5_0] = mmDCORE3_TPC5_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_5_1] = mmDCORE3_TPC5_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_5_2] = mmDCORE3_TPC5_QM_BASE,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_5_3] = mmDCORE3_TPC5_QM_BASE,
+	[GAUDI2_QUEUE_ID_NIC_0_0] = mmNIC0_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_0_1] = mmNIC0_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_0_2] = mmNIC0_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_0_3] = mmNIC0_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_1_0] = mmNIC0_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_1_1] = mmNIC0_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_1_2] = mmNIC0_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_1_3] = mmNIC0_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_2_0] = mmNIC1_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_2_1] = mmNIC1_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_2_2] = mmNIC1_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_2_3] = mmNIC1_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_3_0] = mmNIC1_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_3_1] = mmNIC1_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_3_2] = mmNIC1_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_3_3] = mmNIC1_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_4_0] = mmNIC2_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_4_1] = mmNIC2_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_4_2] = mmNIC2_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_4_3] = mmNIC2_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_5_0] = mmNIC2_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_5_1] = mmNIC2_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_5_2] = mmNIC2_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_5_3] = mmNIC2_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_6_0] = mmNIC3_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_6_1] = mmNIC3_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_6_2] = mmNIC3_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_6_3] = mmNIC3_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_7_0] = mmNIC3_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_7_1] = mmNIC3_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_7_2] = mmNIC3_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_7_3] = mmNIC3_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_8_0] = mmNIC4_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_8_1] = mmNIC4_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_8_2] = mmNIC4_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_8_3] = mmNIC4_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_9_0] = mmNIC4_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_9_1] = mmNIC4_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_9_2] = mmNIC4_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_9_3] = mmNIC4_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_10_0] = mmNIC5_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_10_1] = mmNIC5_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_10_2] = mmNIC5_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_10_3] = mmNIC5_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_11_0] = mmNIC5_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_11_1] = mmNIC5_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_11_2] = mmNIC5_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_11_3] = mmNIC5_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_12_0] = mmNIC6_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_12_1] = mmNIC6_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_12_2] = mmNIC6_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_12_3] = mmNIC6_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_13_0] = mmNIC6_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_13_1] = mmNIC6_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_13_2] = mmNIC6_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_13_3] = mmNIC6_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_14_0] = mmNIC7_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_14_1] = mmNIC7_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_14_2] = mmNIC7_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_14_3] = mmNIC7_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_15_0] = mmNIC7_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_15_1] = mmNIC7_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_15_2] = mmNIC7_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_15_3] = mmNIC7_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_16_0] = mmNIC8_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_16_1] = mmNIC8_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_16_2] = mmNIC8_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_16_3] = mmNIC8_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_17_0] = mmNIC8_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_17_1] = mmNIC8_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_17_2] = mmNIC8_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_17_3] = mmNIC8_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_18_0] = mmNIC9_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_18_1] = mmNIC9_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_18_2] = mmNIC9_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_18_3] = mmNIC9_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_19_0] = mmNIC9_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_19_1] = mmNIC9_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_19_2] = mmNIC9_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_19_3] = mmNIC9_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_20_0] = mmNIC10_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_20_1] = mmNIC10_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_20_2] = mmNIC10_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_20_3] = mmNIC10_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_21_0] = mmNIC10_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_21_1] = mmNIC10_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_21_2] = mmNIC10_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_21_3] = mmNIC10_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_22_0] = mmNIC11_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_22_1] = mmNIC11_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_22_2] = mmNIC11_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_22_3] = mmNIC11_QM0_BASE,
+	[GAUDI2_QUEUE_ID_NIC_23_0] = mmNIC11_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_23_1] = mmNIC11_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_23_2] = mmNIC11_QM1_BASE,
+	[GAUDI2_QUEUE_ID_NIC_23_3] = mmNIC11_QM1_BASE,
+	[GAUDI2_QUEUE_ID_ROT_0_0] = mmROT0_QM_BASE,
+	[GAUDI2_QUEUE_ID_ROT_0_1] = mmROT0_QM_BASE,
+	[GAUDI2_QUEUE_ID_ROT_0_2] = mmROT0_QM_BASE,
+	[GAUDI2_QUEUE_ID_ROT_0_3] = mmROT0_QM_BASE,
+	[GAUDI2_QUEUE_ID_ROT_1_0] = mmROT1_QM_BASE,
+	[GAUDI2_QUEUE_ID_ROT_1_1] = mmROT1_QM_BASE,
+	[GAUDI2_QUEUE_ID_ROT_1_2] = mmROT1_QM_BASE,
+	[GAUDI2_QUEUE_ID_ROT_1_3] = mmROT1_QM_BASE
+};
+
+static const u32 gaudi2_arc_blocks_bases[NUM_ARC_CPUS] = {
+	[CPU_ID_SCHED_ARC0] = mmARC_FARM_ARC0_AUX_BASE,
+	[CPU_ID_SCHED_ARC1] = mmARC_FARM_ARC1_AUX_BASE,
+	[CPU_ID_SCHED_ARC2] = mmARC_FARM_ARC2_AUX_BASE,
+	[CPU_ID_SCHED_ARC3] = mmARC_FARM_ARC3_AUX_BASE,
+	[CPU_ID_SCHED_ARC4] = mmDCORE1_MME_QM_ARC_AUX_BASE,
+	[CPU_ID_SCHED_ARC5] = mmDCORE3_MME_QM_ARC_AUX_BASE,
+	[CPU_ID_TPC_QMAN_ARC0] = mmDCORE0_TPC0_QM_ARC_AUX_BASE,
+	[CPU_ID_TPC_QMAN_ARC1] = mmDCORE0_TPC1_QM_ARC_AUX_BASE,
+	[CPU_ID_TPC_QMAN_ARC2] = mmDCORE0_TPC2_QM_ARC_AUX_BASE,
+	[CPU_ID_TPC_QMAN_ARC3] = mmDCORE0_TPC3_QM_ARC_AUX_BASE,
+	[CPU_ID_TPC_QMAN_ARC4] = mmDCORE0_TPC4_QM_ARC_AUX_BASE,
+	[CPU_ID_TPC_QMAN_ARC5] = mmDCORE0_TPC5_QM_ARC_AUX_BASE,
+	[CPU_ID_TPC_QMAN_ARC6] = mmDCORE1_TPC0_QM_ARC_AUX_BASE,
+	[CPU_ID_TPC_QMAN_ARC7] = mmDCORE1_TPC1_QM_ARC_AUX_BASE,
+	[CPU_ID_TPC_QMAN_ARC8] = mmDCORE1_TPC2_QM_ARC_AUX_BASE,
+	[CPU_ID_TPC_QMAN_ARC9] = mmDCORE1_TPC3_QM_ARC_AUX_BASE,
+	[CPU_ID_TPC_QMAN_ARC10] = mmDCORE1_TPC4_QM_ARC_AUX_BASE,
+	[CPU_ID_TPC_QMAN_ARC11] = mmDCORE1_TPC5_QM_ARC_AUX_BASE,
+	[CPU_ID_TPC_QMAN_ARC12] = mmDCORE2_TPC0_QM_ARC_AUX_BASE,
+	[CPU_ID_TPC_QMAN_ARC13] = mmDCORE2_TPC1_QM_ARC_AUX_BASE,
+	[CPU_ID_TPC_QMAN_ARC14] = mmDCORE2_TPC2_QM_ARC_AUX_BASE,
+	[CPU_ID_TPC_QMAN_ARC15] = mmDCORE2_TPC3_QM_ARC_AUX_BASE,
+	[CPU_ID_TPC_QMAN_ARC16] = mmDCORE2_TPC4_QM_ARC_AUX_BASE,
+	[CPU_ID_TPC_QMAN_ARC17] = mmDCORE2_TPC5_QM_ARC_AUX_BASE,
+	[CPU_ID_TPC_QMAN_ARC18] = mmDCORE3_TPC0_QM_ARC_AUX_BASE,
+	[CPU_ID_TPC_QMAN_ARC19] = mmDCORE3_TPC1_QM_ARC_AUX_BASE,
+	[CPU_ID_TPC_QMAN_ARC20] = mmDCORE3_TPC2_QM_ARC_AUX_BASE,
+	[CPU_ID_TPC_QMAN_ARC21] = mmDCORE3_TPC3_QM_ARC_AUX_BASE,
+	[CPU_ID_TPC_QMAN_ARC22] = mmDCORE3_TPC4_QM_ARC_AUX_BASE,
+	[CPU_ID_TPC_QMAN_ARC23] = mmDCORE3_TPC5_QM_ARC_AUX_BASE,
+	[CPU_ID_TPC_QMAN_ARC24] = mmDCORE0_TPC6_QM_ARC_AUX_BASE,
+	[CPU_ID_MME_QMAN_ARC0] = mmDCORE0_MME_QM_ARC_AUX_BASE,
+	[CPU_ID_MME_QMAN_ARC1] = mmDCORE2_MME_QM_ARC_AUX_BASE,
+	[CPU_ID_EDMA_QMAN_ARC0] = mmDCORE0_EDMA0_QM_ARC_AUX_BASE,
+	[CPU_ID_EDMA_QMAN_ARC1] = mmDCORE0_EDMA1_QM_ARC_AUX_BASE,
+	[CPU_ID_EDMA_QMAN_ARC2] = mmDCORE1_EDMA0_QM_ARC_AUX_BASE,
+	[CPU_ID_EDMA_QMAN_ARC3] = mmDCORE1_EDMA1_QM_ARC_AUX_BASE,
+	[CPU_ID_EDMA_QMAN_ARC4] = mmDCORE2_EDMA0_QM_ARC_AUX_BASE,
+	[CPU_ID_EDMA_QMAN_ARC5] = mmDCORE2_EDMA1_QM_ARC_AUX_BASE,
+	[CPU_ID_EDMA_QMAN_ARC6] = mmDCORE3_EDMA0_QM_ARC_AUX_BASE,
+	[CPU_ID_EDMA_QMAN_ARC7] = mmDCORE3_EDMA1_QM_ARC_AUX_BASE,
+	[CPU_ID_PDMA_QMAN_ARC0] = mmPDMA0_QM_ARC_AUX_BASE,
+	[CPU_ID_PDMA_QMAN_ARC1] = mmPDMA1_QM_ARC_AUX_BASE,
+	[CPU_ID_ROT_QMAN_ARC0] = mmROT0_QM_ARC_AUX_BASE,
+	[CPU_ID_ROT_QMAN_ARC1] = mmROT1_QM_ARC_AUX_BASE,
+	[CPU_ID_NIC_QMAN_ARC0] = mmNIC0_QM_ARC_AUX0_BASE,
+	[CPU_ID_NIC_QMAN_ARC1] = mmNIC0_QM_ARC_AUX1_BASE,
+	[CPU_ID_NIC_QMAN_ARC2] = mmNIC1_QM_ARC_AUX0_BASE,
+	[CPU_ID_NIC_QMAN_ARC3] = mmNIC1_QM_ARC_AUX1_BASE,
+	[CPU_ID_NIC_QMAN_ARC4] = mmNIC2_QM_ARC_AUX0_BASE,
+	[CPU_ID_NIC_QMAN_ARC5] = mmNIC2_QM_ARC_AUX1_BASE,
+	[CPU_ID_NIC_QMAN_ARC6] = mmNIC3_QM_ARC_AUX0_BASE,
+	[CPU_ID_NIC_QMAN_ARC7] = mmNIC3_QM_ARC_AUX1_BASE,
+	[CPU_ID_NIC_QMAN_ARC8] = mmNIC4_QM_ARC_AUX0_BASE,
+	[CPU_ID_NIC_QMAN_ARC9] = mmNIC4_QM_ARC_AUX1_BASE,
+	[CPU_ID_NIC_QMAN_ARC10] = mmNIC5_QM_ARC_AUX0_BASE,
+	[CPU_ID_NIC_QMAN_ARC11] = mmNIC5_QM_ARC_AUX1_BASE,
+	[CPU_ID_NIC_QMAN_ARC12] = mmNIC6_QM_ARC_AUX0_BASE,
+	[CPU_ID_NIC_QMAN_ARC13] = mmNIC6_QM_ARC_AUX1_BASE,
+	[CPU_ID_NIC_QMAN_ARC14] = mmNIC7_QM_ARC_AUX0_BASE,
+	[CPU_ID_NIC_QMAN_ARC15] = mmNIC7_QM_ARC_AUX1_BASE,
+	[CPU_ID_NIC_QMAN_ARC16] = mmNIC8_QM_ARC_AUX0_BASE,
+	[CPU_ID_NIC_QMAN_ARC17] = mmNIC8_QM_ARC_AUX1_BASE,
+	[CPU_ID_NIC_QMAN_ARC18] = mmNIC9_QM_ARC_AUX0_BASE,
+	[CPU_ID_NIC_QMAN_ARC19] = mmNIC9_QM_ARC_AUX1_BASE,
+	[CPU_ID_NIC_QMAN_ARC20] = mmNIC10_QM_ARC_AUX0_BASE,
+	[CPU_ID_NIC_QMAN_ARC21] = mmNIC10_QM_ARC_AUX1_BASE,
+	[CPU_ID_NIC_QMAN_ARC22] = mmNIC11_QM_ARC_AUX0_BASE,
+	[CPU_ID_NIC_QMAN_ARC23] = mmNIC11_QM_ARC_AUX1_BASE,
+};
+
+static const u32 gaudi2_arc_dccm_bases[NUM_ARC_CPUS] = {
+	[CPU_ID_SCHED_ARC0] = mmARC_FARM_ARC0_DCCM0_BASE,
+	[CPU_ID_SCHED_ARC1] = mmARC_FARM_ARC1_DCCM0_BASE,
+	[CPU_ID_SCHED_ARC2] = mmARC_FARM_ARC2_DCCM0_BASE,
+	[CPU_ID_SCHED_ARC3] = mmARC_FARM_ARC3_DCCM0_BASE,
+	[CPU_ID_SCHED_ARC4] = mmDCORE1_MME_QM_ARC_DCCM_BASE,
+	[CPU_ID_SCHED_ARC5] = mmDCORE3_MME_QM_ARC_DCCM_BASE,
+	[CPU_ID_TPC_QMAN_ARC0] = mmDCORE0_TPC0_QM_DCCM_BASE,
+	[CPU_ID_TPC_QMAN_ARC1] = mmDCORE0_TPC1_QM_DCCM_BASE,
+	[CPU_ID_TPC_QMAN_ARC2] = mmDCORE0_TPC2_QM_DCCM_BASE,
+	[CPU_ID_TPC_QMAN_ARC3] = mmDCORE0_TPC3_QM_DCCM_BASE,
+	[CPU_ID_TPC_QMAN_ARC4] = mmDCORE0_TPC4_QM_DCCM_BASE,
+	[CPU_ID_TPC_QMAN_ARC5] = mmDCORE0_TPC5_QM_DCCM_BASE,
+	[CPU_ID_TPC_QMAN_ARC6] = mmDCORE1_TPC0_QM_DCCM_BASE,
+	[CPU_ID_TPC_QMAN_ARC7] = mmDCORE1_TPC1_QM_DCCM_BASE,
+	[CPU_ID_TPC_QMAN_ARC8] = mmDCORE1_TPC2_QM_DCCM_BASE,
+	[CPU_ID_TPC_QMAN_ARC9] = mmDCORE1_TPC3_QM_DCCM_BASE,
+	[CPU_ID_TPC_QMAN_ARC10] = mmDCORE1_TPC4_QM_DCCM_BASE,
+	[CPU_ID_TPC_QMAN_ARC11] = mmDCORE1_TPC5_QM_DCCM_BASE,
+	[CPU_ID_TPC_QMAN_ARC12] = mmDCORE2_TPC0_QM_DCCM_BASE,
+	[CPU_ID_TPC_QMAN_ARC13] = mmDCORE2_TPC1_QM_DCCM_BASE,
+	[CPU_ID_TPC_QMAN_ARC14] = mmDCORE2_TPC2_QM_DCCM_BASE,
+	[CPU_ID_TPC_QMAN_ARC15] = mmDCORE2_TPC3_QM_DCCM_BASE,
+	[CPU_ID_TPC_QMAN_ARC16] = mmDCORE2_TPC4_QM_DCCM_BASE,
+	[CPU_ID_TPC_QMAN_ARC17] = mmDCORE2_TPC5_QM_DCCM_BASE,
+	[CPU_ID_TPC_QMAN_ARC18] = mmDCORE3_TPC0_QM_DCCM_BASE,
+	[CPU_ID_TPC_QMAN_ARC19] = mmDCORE3_TPC1_QM_DCCM_BASE,
+	[CPU_ID_TPC_QMAN_ARC20] = mmDCORE3_TPC2_QM_DCCM_BASE,
+	[CPU_ID_TPC_QMAN_ARC21] = mmDCORE3_TPC3_QM_DCCM_BASE,
+	[CPU_ID_TPC_QMAN_ARC22] = mmDCORE3_TPC4_QM_DCCM_BASE,
+	[CPU_ID_TPC_QMAN_ARC23] = mmDCORE3_TPC5_QM_DCCM_BASE,
+	[CPU_ID_TPC_QMAN_ARC24] = mmDCORE0_TPC6_QM_DCCM_BASE,
+	[CPU_ID_MME_QMAN_ARC0] = mmDCORE0_MME_QM_ARC_DCCM_BASE,
+	[CPU_ID_MME_QMAN_ARC1] = mmDCORE2_MME_QM_ARC_DCCM_BASE,
+	[CPU_ID_EDMA_QMAN_ARC0] = mmDCORE0_EDMA0_QM_DCCM_BASE,
+	[CPU_ID_EDMA_QMAN_ARC1] = mmDCORE0_EDMA1_QM_DCCM_BASE,
+	[CPU_ID_EDMA_QMAN_ARC2] = mmDCORE1_EDMA0_QM_DCCM_BASE,
+	[CPU_ID_EDMA_QMAN_ARC3] = mmDCORE1_EDMA1_QM_DCCM_BASE,
+	[CPU_ID_EDMA_QMAN_ARC4] = mmDCORE2_EDMA0_QM_DCCM_BASE,
+	[CPU_ID_EDMA_QMAN_ARC5] = mmDCORE2_EDMA1_QM_DCCM_BASE,
+	[CPU_ID_EDMA_QMAN_ARC6] = mmDCORE3_EDMA0_QM_DCCM_BASE,
+	[CPU_ID_EDMA_QMAN_ARC7] = mmDCORE3_EDMA1_QM_DCCM_BASE,
+	[CPU_ID_PDMA_QMAN_ARC0] = mmPDMA0_QM_ARC_DCCM_BASE,
+	[CPU_ID_PDMA_QMAN_ARC1] = mmPDMA1_QM_ARC_DCCM_BASE,
+	[CPU_ID_ROT_QMAN_ARC0] = mmROT0_QM_ARC_DCCM_BASE,
+	[CPU_ID_ROT_QMAN_ARC1] = mmROT1_QM_ARC_DCCM_BASE,
+	[CPU_ID_NIC_QMAN_ARC0] = mmNIC0_QM_DCCM0_BASE,
+	[CPU_ID_NIC_QMAN_ARC1] = mmNIC0_QM_DCCM1_BASE,
+	[CPU_ID_NIC_QMAN_ARC2] = mmNIC1_QM_DCCM0_BASE,
+	[CPU_ID_NIC_QMAN_ARC3] = mmNIC1_QM_DCCM1_BASE,
+	[CPU_ID_NIC_QMAN_ARC4] = mmNIC2_QM_DCCM0_BASE,
+	[CPU_ID_NIC_QMAN_ARC5] = mmNIC2_QM_DCCM1_BASE,
+	[CPU_ID_NIC_QMAN_ARC6] = mmNIC3_QM_DCCM0_BASE,
+	[CPU_ID_NIC_QMAN_ARC7] = mmNIC3_QM_DCCM1_BASE,
+	[CPU_ID_NIC_QMAN_ARC8] = mmNIC4_QM_DCCM0_BASE,
+	[CPU_ID_NIC_QMAN_ARC9] = mmNIC4_QM_DCCM1_BASE,
+	[CPU_ID_NIC_QMAN_ARC10] = mmNIC5_QM_DCCM0_BASE,
+	[CPU_ID_NIC_QMAN_ARC11] = mmNIC5_QM_DCCM1_BASE,
+	[CPU_ID_NIC_QMAN_ARC12] = mmNIC6_QM_DCCM0_BASE,
+	[CPU_ID_NIC_QMAN_ARC13] = mmNIC6_QM_DCCM1_BASE,
+	[CPU_ID_NIC_QMAN_ARC14] = mmNIC7_QM_DCCM0_BASE,
+	[CPU_ID_NIC_QMAN_ARC15] = mmNIC7_QM_DCCM1_BASE,
+	[CPU_ID_NIC_QMAN_ARC16] = mmNIC8_QM_DCCM0_BASE,
+	[CPU_ID_NIC_QMAN_ARC17] = mmNIC8_QM_DCCM1_BASE,
+	[CPU_ID_NIC_QMAN_ARC18] = mmNIC9_QM_DCCM0_BASE,
+	[CPU_ID_NIC_QMAN_ARC19] = mmNIC9_QM_DCCM1_BASE,
+	[CPU_ID_NIC_QMAN_ARC20] = mmNIC10_QM_DCCM0_BASE,
+	[CPU_ID_NIC_QMAN_ARC21] = mmNIC10_QM_DCCM1_BASE,
+	[CPU_ID_NIC_QMAN_ARC22] = mmNIC11_QM_DCCM0_BASE,
+	[CPU_ID_NIC_QMAN_ARC23] = mmNIC11_QM_DCCM1_BASE,
+};
+
+const u32 gaudi2_mme_ctrl_lo_blocks_bases[MME_ID_SIZE] = {
+	[MME_ID_DCORE0] = mmDCORE0_MME_CTRL_LO_BASE,
+	[MME_ID_DCORE1] = mmDCORE1_MME_CTRL_LO_BASE,
+	[MME_ID_DCORE2] = mmDCORE2_MME_CTRL_LO_BASE,
+	[MME_ID_DCORE3] = mmDCORE3_MME_CTRL_LO_BASE,
+};
+
+static const u32 gaudi2_queue_id_to_arc_id[GAUDI2_QUEUE_ID_SIZE] = {
+	[GAUDI2_QUEUE_ID_PDMA_0_0] = CPU_ID_PDMA_QMAN_ARC0,
+	[GAUDI2_QUEUE_ID_PDMA_0_1] = CPU_ID_PDMA_QMAN_ARC0,
+	[GAUDI2_QUEUE_ID_PDMA_0_2] = CPU_ID_PDMA_QMAN_ARC0,
+	[GAUDI2_QUEUE_ID_PDMA_0_3] = CPU_ID_PDMA_QMAN_ARC0,
+	[GAUDI2_QUEUE_ID_PDMA_1_0] = CPU_ID_PDMA_QMAN_ARC1,
+	[GAUDI2_QUEUE_ID_PDMA_1_1] = CPU_ID_PDMA_QMAN_ARC1,
+	[GAUDI2_QUEUE_ID_PDMA_1_2] = CPU_ID_PDMA_QMAN_ARC1,
+	[GAUDI2_QUEUE_ID_PDMA_1_3] = CPU_ID_PDMA_QMAN_ARC1,
+	[GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0] = CPU_ID_EDMA_QMAN_ARC0,
+	[GAUDI2_QUEUE_ID_DCORE0_EDMA_0_1] = CPU_ID_EDMA_QMAN_ARC0,
+	[GAUDI2_QUEUE_ID_DCORE0_EDMA_0_2] = CPU_ID_EDMA_QMAN_ARC0,
+	[GAUDI2_QUEUE_ID_DCORE0_EDMA_0_3] = CPU_ID_EDMA_QMAN_ARC0,
+	[GAUDI2_QUEUE_ID_DCORE0_EDMA_1_0] = CPU_ID_EDMA_QMAN_ARC1,
+	[GAUDI2_QUEUE_ID_DCORE0_EDMA_1_1] = CPU_ID_EDMA_QMAN_ARC1,
+	[GAUDI2_QUEUE_ID_DCORE0_EDMA_1_2] = CPU_ID_EDMA_QMAN_ARC1,
+	[GAUDI2_QUEUE_ID_DCORE0_EDMA_1_3] = CPU_ID_EDMA_QMAN_ARC1,
+	[GAUDI2_QUEUE_ID_DCORE0_MME_0_0] = CPU_ID_MME_QMAN_ARC0,
+	[GAUDI2_QUEUE_ID_DCORE0_MME_0_1] = CPU_ID_MME_QMAN_ARC0,
+	[GAUDI2_QUEUE_ID_DCORE0_MME_0_2] = CPU_ID_MME_QMAN_ARC0,
+	[GAUDI2_QUEUE_ID_DCORE0_MME_0_3] = CPU_ID_MME_QMAN_ARC0,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_0_0] = CPU_ID_TPC_QMAN_ARC0,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_0_1] = CPU_ID_TPC_QMAN_ARC0,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_0_2] = CPU_ID_TPC_QMAN_ARC0,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_0_3] = CPU_ID_TPC_QMAN_ARC0,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_1_0] = CPU_ID_TPC_QMAN_ARC1,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_1_1] = CPU_ID_TPC_QMAN_ARC1,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_1_2] = CPU_ID_TPC_QMAN_ARC1,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_1_3] = CPU_ID_TPC_QMAN_ARC1,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_2_0] = CPU_ID_TPC_QMAN_ARC2,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_2_1] = CPU_ID_TPC_QMAN_ARC2,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_2_2] = CPU_ID_TPC_QMAN_ARC2,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_2_3] = CPU_ID_TPC_QMAN_ARC2,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_3_0] = CPU_ID_TPC_QMAN_ARC3,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_3_1] = CPU_ID_TPC_QMAN_ARC3,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_3_2] = CPU_ID_TPC_QMAN_ARC3,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_3_3] = CPU_ID_TPC_QMAN_ARC3,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_4_0] = CPU_ID_TPC_QMAN_ARC4,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_4_1] = CPU_ID_TPC_QMAN_ARC4,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_4_2] = CPU_ID_TPC_QMAN_ARC4,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_4_3] = CPU_ID_TPC_QMAN_ARC4,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_5_0] = CPU_ID_TPC_QMAN_ARC5,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_5_1] = CPU_ID_TPC_QMAN_ARC5,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_5_2] = CPU_ID_TPC_QMAN_ARC5,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_5_3] = CPU_ID_TPC_QMAN_ARC5,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_6_0] = CPU_ID_TPC_QMAN_ARC24,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_6_1] = CPU_ID_TPC_QMAN_ARC24,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_6_2] = CPU_ID_TPC_QMAN_ARC24,
+	[GAUDI2_QUEUE_ID_DCORE0_TPC_6_3] = CPU_ID_TPC_QMAN_ARC24,
+	[GAUDI2_QUEUE_ID_DCORE1_EDMA_0_0] = CPU_ID_EDMA_QMAN_ARC2,
+	[GAUDI2_QUEUE_ID_DCORE1_EDMA_0_1] = CPU_ID_EDMA_QMAN_ARC2,
+	[GAUDI2_QUEUE_ID_DCORE1_EDMA_0_2] = CPU_ID_EDMA_QMAN_ARC2,
+	[GAUDI2_QUEUE_ID_DCORE1_EDMA_0_3] = CPU_ID_EDMA_QMAN_ARC2,
+	[GAUDI2_QUEUE_ID_DCORE1_EDMA_1_0] = CPU_ID_EDMA_QMAN_ARC3,
+	[GAUDI2_QUEUE_ID_DCORE1_EDMA_1_1] = CPU_ID_EDMA_QMAN_ARC3,
+	[GAUDI2_QUEUE_ID_DCORE1_EDMA_1_2] = CPU_ID_EDMA_QMAN_ARC3,
+	[GAUDI2_QUEUE_ID_DCORE1_EDMA_1_3] = CPU_ID_EDMA_QMAN_ARC3,
+	[GAUDI2_QUEUE_ID_DCORE1_MME_0_0] = CPU_ID_SCHED_ARC4,
+	[GAUDI2_QUEUE_ID_DCORE1_MME_0_1] = CPU_ID_SCHED_ARC4,
+	[GAUDI2_QUEUE_ID_DCORE1_MME_0_2] = CPU_ID_SCHED_ARC4,
+	[GAUDI2_QUEUE_ID_DCORE1_MME_0_3] = CPU_ID_SCHED_ARC4,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_0_0] = CPU_ID_TPC_QMAN_ARC6,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_0_1] = CPU_ID_TPC_QMAN_ARC6,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_0_2] = CPU_ID_TPC_QMAN_ARC6,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_0_3] = CPU_ID_TPC_QMAN_ARC6,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_1_0] = CPU_ID_TPC_QMAN_ARC7,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_1_1] = CPU_ID_TPC_QMAN_ARC7,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_1_2] = CPU_ID_TPC_QMAN_ARC7,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_1_3] = CPU_ID_TPC_QMAN_ARC7,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_2_0] = CPU_ID_TPC_QMAN_ARC8,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_2_1] = CPU_ID_TPC_QMAN_ARC8,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_2_2] = CPU_ID_TPC_QMAN_ARC8,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_2_3] = CPU_ID_TPC_QMAN_ARC8,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_3_0] = CPU_ID_TPC_QMAN_ARC9,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_3_1] = CPU_ID_TPC_QMAN_ARC9,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_3_2] = CPU_ID_TPC_QMAN_ARC9,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_3_3] = CPU_ID_TPC_QMAN_ARC9,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_4_0] = CPU_ID_TPC_QMAN_ARC10,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_4_1] = CPU_ID_TPC_QMAN_ARC10,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_4_2] = CPU_ID_TPC_QMAN_ARC10,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_4_3] = CPU_ID_TPC_QMAN_ARC10,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_5_0] = CPU_ID_TPC_QMAN_ARC11,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_5_1] = CPU_ID_TPC_QMAN_ARC11,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_5_2] = CPU_ID_TPC_QMAN_ARC11,
+	[GAUDI2_QUEUE_ID_DCORE1_TPC_5_3] = CPU_ID_TPC_QMAN_ARC11,
+	[GAUDI2_QUEUE_ID_DCORE2_EDMA_0_0] = CPU_ID_EDMA_QMAN_ARC4,
+	[GAUDI2_QUEUE_ID_DCORE2_EDMA_0_1] = CPU_ID_EDMA_QMAN_ARC4,
+	[GAUDI2_QUEUE_ID_DCORE2_EDMA_0_2] = CPU_ID_EDMA_QMAN_ARC4,
+	[GAUDI2_QUEUE_ID_DCORE2_EDMA_0_3] = CPU_ID_EDMA_QMAN_ARC4,
+	[GAUDI2_QUEUE_ID_DCORE2_EDMA_1_0] = CPU_ID_EDMA_QMAN_ARC5,
+	[GAUDI2_QUEUE_ID_DCORE2_EDMA_1_1] = CPU_ID_EDMA_QMAN_ARC5,
+	[GAUDI2_QUEUE_ID_DCORE2_EDMA_1_2] = CPU_ID_EDMA_QMAN_ARC5,
+	[GAUDI2_QUEUE_ID_DCORE2_EDMA_1_3] = CPU_ID_EDMA_QMAN_ARC5,
+	[GAUDI2_QUEUE_ID_DCORE2_MME_0_0] = CPU_ID_MME_QMAN_ARC1,
+	[GAUDI2_QUEUE_ID_DCORE2_MME_0_1] = CPU_ID_MME_QMAN_ARC1,
+	[GAUDI2_QUEUE_ID_DCORE2_MME_0_2] = CPU_ID_MME_QMAN_ARC1,
+	[GAUDI2_QUEUE_ID_DCORE2_MME_0_3] = CPU_ID_MME_QMAN_ARC1,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_0_0] = CPU_ID_TPC_QMAN_ARC12,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_0_1] = CPU_ID_TPC_QMAN_ARC12,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_0_2] = CPU_ID_TPC_QMAN_ARC12,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_0_3] = CPU_ID_TPC_QMAN_ARC12,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_1_0] = CPU_ID_TPC_QMAN_ARC13,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_1_1] = CPU_ID_TPC_QMAN_ARC13,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_1_2] = CPU_ID_TPC_QMAN_ARC13,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_1_3] = CPU_ID_TPC_QMAN_ARC13,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_2_0] = CPU_ID_TPC_QMAN_ARC14,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_2_1] = CPU_ID_TPC_QMAN_ARC14,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_2_2] = CPU_ID_TPC_QMAN_ARC14,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_2_3] = CPU_ID_TPC_QMAN_ARC14,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_3_0] = CPU_ID_TPC_QMAN_ARC15,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_3_1] = CPU_ID_TPC_QMAN_ARC15,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_3_2] = CPU_ID_TPC_QMAN_ARC15,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_3_3] = CPU_ID_TPC_QMAN_ARC15,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_4_0] = CPU_ID_TPC_QMAN_ARC16,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_4_1] = CPU_ID_TPC_QMAN_ARC16,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_4_2] = CPU_ID_TPC_QMAN_ARC16,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_4_3] = CPU_ID_TPC_QMAN_ARC16,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_5_0] = CPU_ID_TPC_QMAN_ARC17,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_5_1] = CPU_ID_TPC_QMAN_ARC17,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_5_2] = CPU_ID_TPC_QMAN_ARC17,
+	[GAUDI2_QUEUE_ID_DCORE2_TPC_5_3] = CPU_ID_TPC_QMAN_ARC17,
+	[GAUDI2_QUEUE_ID_DCORE3_EDMA_0_0] = CPU_ID_EDMA_QMAN_ARC6,
+	[GAUDI2_QUEUE_ID_DCORE3_EDMA_0_1] = CPU_ID_EDMA_QMAN_ARC6,
+	[GAUDI2_QUEUE_ID_DCORE3_EDMA_0_2] = CPU_ID_EDMA_QMAN_ARC6,
+	[GAUDI2_QUEUE_ID_DCORE3_EDMA_0_3] = CPU_ID_EDMA_QMAN_ARC6,
+	[GAUDI2_QUEUE_ID_DCORE3_EDMA_1_0] = CPU_ID_EDMA_QMAN_ARC7,
+	[GAUDI2_QUEUE_ID_DCORE3_EDMA_1_1] = CPU_ID_EDMA_QMAN_ARC7,
+	[GAUDI2_QUEUE_ID_DCORE3_EDMA_1_2] = CPU_ID_EDMA_QMAN_ARC7,
+	[GAUDI2_QUEUE_ID_DCORE3_EDMA_1_3] = CPU_ID_EDMA_QMAN_ARC7,
+	[GAUDI2_QUEUE_ID_DCORE3_MME_0_0] = CPU_ID_SCHED_ARC5,
+	[GAUDI2_QUEUE_ID_DCORE3_MME_0_1] = CPU_ID_SCHED_ARC5,
+	[GAUDI2_QUEUE_ID_DCORE3_MME_0_2] = CPU_ID_SCHED_ARC5,
+	[GAUDI2_QUEUE_ID_DCORE3_MME_0_3] = CPU_ID_SCHED_ARC5,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_0_0] = CPU_ID_TPC_QMAN_ARC18,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_0_1] = CPU_ID_TPC_QMAN_ARC18,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_0_2] = CPU_ID_TPC_QMAN_ARC18,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_0_3] = CPU_ID_TPC_QMAN_ARC18,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_1_0] = CPU_ID_TPC_QMAN_ARC19,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_1_1] = CPU_ID_TPC_QMAN_ARC19,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_1_2] = CPU_ID_TPC_QMAN_ARC19,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_1_3] = CPU_ID_TPC_QMAN_ARC19,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_2_0] = CPU_ID_TPC_QMAN_ARC20,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_2_1] = CPU_ID_TPC_QMAN_ARC20,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_2_2] = CPU_ID_TPC_QMAN_ARC20,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_2_3] = CPU_ID_TPC_QMAN_ARC20,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_3_0] = CPU_ID_TPC_QMAN_ARC21,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_3_1] = CPU_ID_TPC_QMAN_ARC21,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_3_2] = CPU_ID_TPC_QMAN_ARC21,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_3_3] = CPU_ID_TPC_QMAN_ARC21,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_4_0] = CPU_ID_TPC_QMAN_ARC22,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_4_1] = CPU_ID_TPC_QMAN_ARC22,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_4_2] = CPU_ID_TPC_QMAN_ARC22,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_4_3] = CPU_ID_TPC_QMAN_ARC22,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_5_0] = CPU_ID_TPC_QMAN_ARC23,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_5_1] = CPU_ID_TPC_QMAN_ARC23,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_5_2] = CPU_ID_TPC_QMAN_ARC23,
+	[GAUDI2_QUEUE_ID_DCORE3_TPC_5_3] = CPU_ID_TPC_QMAN_ARC23,
+	[GAUDI2_QUEUE_ID_NIC_0_0] = CPU_ID_NIC_QMAN_ARC0,
+	[GAUDI2_QUEUE_ID_NIC_0_1] = CPU_ID_NIC_QMAN_ARC0,
+	[GAUDI2_QUEUE_ID_NIC_0_2] = CPU_ID_NIC_QMAN_ARC0,
+	[GAUDI2_QUEUE_ID_NIC_0_3] = CPU_ID_NIC_QMAN_ARC0,
+	[GAUDI2_QUEUE_ID_NIC_1_0] = CPU_ID_NIC_QMAN_ARC1,
+	[GAUDI2_QUEUE_ID_NIC_1_1] = CPU_ID_NIC_QMAN_ARC1,
+	[GAUDI2_QUEUE_ID_NIC_1_2] = CPU_ID_NIC_QMAN_ARC1,
+	[GAUDI2_QUEUE_ID_NIC_1_3] = CPU_ID_NIC_QMAN_ARC1,
+	[GAUDI2_QUEUE_ID_NIC_2_0] = CPU_ID_NIC_QMAN_ARC2,
+	[GAUDI2_QUEUE_ID_NIC_2_1] = CPU_ID_NIC_QMAN_ARC2,
+	[GAUDI2_QUEUE_ID_NIC_2_2] = CPU_ID_NIC_QMAN_ARC2,
+	[GAUDI2_QUEUE_ID_NIC_2_3] = CPU_ID_NIC_QMAN_ARC2,
+	[GAUDI2_QUEUE_ID_NIC_3_0] = CPU_ID_NIC_QMAN_ARC3,
+	[GAUDI2_QUEUE_ID_NIC_3_1] = CPU_ID_NIC_QMAN_ARC3,
+	[GAUDI2_QUEUE_ID_NIC_3_2] = CPU_ID_NIC_QMAN_ARC3,
+	[GAUDI2_QUEUE_ID_NIC_3_3] = CPU_ID_NIC_QMAN_ARC3,
+	[GAUDI2_QUEUE_ID_NIC_4_0] = CPU_ID_NIC_QMAN_ARC4,
+	[GAUDI2_QUEUE_ID_NIC_4_1] = CPU_ID_NIC_QMAN_ARC4,
+	[GAUDI2_QUEUE_ID_NIC_4_2] = CPU_ID_NIC_QMAN_ARC4,
+	[GAUDI2_QUEUE_ID_NIC_4_3] = CPU_ID_NIC_QMAN_ARC4,
+	[GAUDI2_QUEUE_ID_NIC_5_0] = CPU_ID_NIC_QMAN_ARC5,
+	[GAUDI2_QUEUE_ID_NIC_5_1] = CPU_ID_NIC_QMAN_ARC5,
+	[GAUDI2_QUEUE_ID_NIC_5_2] = CPU_ID_NIC_QMAN_ARC5,
+	[GAUDI2_QUEUE_ID_NIC_5_3] = CPU_ID_NIC_QMAN_ARC5,
+	[GAUDI2_QUEUE_ID_NIC_6_0] = CPU_ID_NIC_QMAN_ARC6,
+	[GAUDI2_QUEUE_ID_NIC_6_1] = CPU_ID_NIC_QMAN_ARC6,
+	[GAUDI2_QUEUE_ID_NIC_6_2] = CPU_ID_NIC_QMAN_ARC6,
+	[GAUDI2_QUEUE_ID_NIC_6_3] = CPU_ID_NIC_QMAN_ARC6,
+	[GAUDI2_QUEUE_ID_NIC_7_0] = CPU_ID_NIC_QMAN_ARC7,
+	[GAUDI2_QUEUE_ID_NIC_7_1] = CPU_ID_NIC_QMAN_ARC7,
+	[GAUDI2_QUEUE_ID_NIC_7_2] = CPU_ID_NIC_QMAN_ARC7,
+	[GAUDI2_QUEUE_ID_NIC_7_3] = CPU_ID_NIC_QMAN_ARC7,
+	[GAUDI2_QUEUE_ID_NIC_8_0] = CPU_ID_NIC_QMAN_ARC8,
+	[GAUDI2_QUEUE_ID_NIC_8_1] = CPU_ID_NIC_QMAN_ARC8,
+	[GAUDI2_QUEUE_ID_NIC_8_2] = CPU_ID_NIC_QMAN_ARC8,
+	[GAUDI2_QUEUE_ID_NIC_8_3] = CPU_ID_NIC_QMAN_ARC8,
+	[GAUDI2_QUEUE_ID_NIC_9_0] = CPU_ID_NIC_QMAN_ARC9,
+	[GAUDI2_QUEUE_ID_NIC_9_1] = CPU_ID_NIC_QMAN_ARC9,
+	[GAUDI2_QUEUE_ID_NIC_9_2] = CPU_ID_NIC_QMAN_ARC9,
+	[GAUDI2_QUEUE_ID_NIC_9_3] = CPU_ID_NIC_QMAN_ARC9,
+	[GAUDI2_QUEUE_ID_NIC_10_0] = CPU_ID_NIC_QMAN_ARC10,
+	[GAUDI2_QUEUE_ID_NIC_10_1] = CPU_ID_NIC_QMAN_ARC10,
+	[GAUDI2_QUEUE_ID_NIC_10_2] = CPU_ID_NIC_QMAN_ARC10,
+	[GAUDI2_QUEUE_ID_NIC_10_3] = CPU_ID_NIC_QMAN_ARC10,
+	[GAUDI2_QUEUE_ID_NIC_11_0] = CPU_ID_NIC_QMAN_ARC11,
+	[GAUDI2_QUEUE_ID_NIC_11_1] = CPU_ID_NIC_QMAN_ARC11,
+	[GAUDI2_QUEUE_ID_NIC_11_2] = CPU_ID_NIC_QMAN_ARC11,
+	[GAUDI2_QUEUE_ID_NIC_11_3] = CPU_ID_NIC_QMAN_ARC11,
+	[GAUDI2_QUEUE_ID_NIC_12_0] = CPU_ID_NIC_QMAN_ARC12,
+	[GAUDI2_QUEUE_ID_NIC_12_1] = CPU_ID_NIC_QMAN_ARC12,
+	[GAUDI2_QUEUE_ID_NIC_12_2] = CPU_ID_NIC_QMAN_ARC12,
+	[GAUDI2_QUEUE_ID_NIC_12_3] = CPU_ID_NIC_QMAN_ARC12,
+	[GAUDI2_QUEUE_ID_NIC_13_0] = CPU_ID_NIC_QMAN_ARC13,
+	[GAUDI2_QUEUE_ID_NIC_13_1] = CPU_ID_NIC_QMAN_ARC13,
+	[GAUDI2_QUEUE_ID_NIC_13_2] = CPU_ID_NIC_QMAN_ARC13,
+	[GAUDI2_QUEUE_ID_NIC_13_3] = CPU_ID_NIC_QMAN_ARC13,
+	[GAUDI2_QUEUE_ID_NIC_14_0] = CPU_ID_NIC_QMAN_ARC14,
+	[GAUDI2_QUEUE_ID_NIC_14_1] = CPU_ID_NIC_QMAN_ARC14,
+	[GAUDI2_QUEUE_ID_NIC_14_2] = CPU_ID_NIC_QMAN_ARC14,
+	[GAUDI2_QUEUE_ID_NIC_14_3] = CPU_ID_NIC_QMAN_ARC14,
+	[GAUDI2_QUEUE_ID_NIC_15_0] = CPU_ID_NIC_QMAN_ARC15,
+	[GAUDI2_QUEUE_ID_NIC_15_1] = CPU_ID_NIC_QMAN_ARC15,
+	[GAUDI2_QUEUE_ID_NIC_15_2] = CPU_ID_NIC_QMAN_ARC15,
+	[GAUDI2_QUEUE_ID_NIC_15_3] = CPU_ID_NIC_QMAN_ARC15,
+	[GAUDI2_QUEUE_ID_NIC_16_0] = CPU_ID_NIC_QMAN_ARC16,
+	[GAUDI2_QUEUE_ID_NIC_16_1] = CPU_ID_NIC_QMAN_ARC16,
+	[GAUDI2_QUEUE_ID_NIC_16_2] = CPU_ID_NIC_QMAN_ARC16,
+	[GAUDI2_QUEUE_ID_NIC_16_3] = CPU_ID_NIC_QMAN_ARC16,
+	[GAUDI2_QUEUE_ID_NIC_17_0] = CPU_ID_NIC_QMAN_ARC17,
+	[GAUDI2_QUEUE_ID_NIC_17_1] = CPU_ID_NIC_QMAN_ARC17,
+	[GAUDI2_QUEUE_ID_NIC_17_2] = CPU_ID_NIC_QMAN_ARC17,
+	[GAUDI2_QUEUE_ID_NIC_17_3] = CPU_ID_NIC_QMAN_ARC17,
+	[GAUDI2_QUEUE_ID_NIC_18_0] = CPU_ID_NIC_QMAN_ARC18,
+	[GAUDI2_QUEUE_ID_NIC_18_1] = CPU_ID_NIC_QMAN_ARC18,
+	[GAUDI2_QUEUE_ID_NIC_18_2] = CPU_ID_NIC_QMAN_ARC18,
+	[GAUDI2_QUEUE_ID_NIC_18_3] = CPU_ID_NIC_QMAN_ARC18,
+	[GAUDI2_QUEUE_ID_NIC_19_0] = CPU_ID_NIC_QMAN_ARC19,
+	[GAUDI2_QUEUE_ID_NIC_19_1] = CPU_ID_NIC_QMAN_ARC19,
+	[GAUDI2_QUEUE_ID_NIC_19_2] = CPU_ID_NIC_QMAN_ARC19,
+	[GAUDI2_QUEUE_ID_NIC_19_3] = CPU_ID_NIC_QMAN_ARC19,
+	[GAUDI2_QUEUE_ID_NIC_20_0] = CPU_ID_NIC_QMAN_ARC20,
+	[GAUDI2_QUEUE_ID_NIC_20_1] = CPU_ID_NIC_QMAN_ARC20,
+	[GAUDI2_QUEUE_ID_NIC_20_2] = CPU_ID_NIC_QMAN_ARC20,
+	[GAUDI2_QUEUE_ID_NIC_20_3] = CPU_ID_NIC_QMAN_ARC20,
+	[GAUDI2_QUEUE_ID_NIC_21_0] = CPU_ID_NIC_QMAN_ARC21,
+	[GAUDI2_QUEUE_ID_NIC_21_1] = CPU_ID_NIC_QMAN_ARC21,
+	[GAUDI2_QUEUE_ID_NIC_21_2] = CPU_ID_NIC_QMAN_ARC21,
+	[GAUDI2_QUEUE_ID_NIC_21_3] = CPU_ID_NIC_QMAN_ARC21,
+	[GAUDI2_QUEUE_ID_NIC_22_0] = CPU_ID_NIC_QMAN_ARC22,
+	[GAUDI2_QUEUE_ID_NIC_22_1] = CPU_ID_NIC_QMAN_ARC22,
+	[GAUDI2_QUEUE_ID_NIC_22_2] = CPU_ID_NIC_QMAN_ARC22,
+	[GAUDI2_QUEUE_ID_NIC_22_3] = CPU_ID_NIC_QMAN_ARC22,
+	[GAUDI2_QUEUE_ID_NIC_23_0] = CPU_ID_NIC_QMAN_ARC23,
+	[GAUDI2_QUEUE_ID_NIC_23_1] = CPU_ID_NIC_QMAN_ARC23,
+	[GAUDI2_QUEUE_ID_NIC_23_2] = CPU_ID_NIC_QMAN_ARC23,
+	[GAUDI2_QUEUE_ID_NIC_23_3] = CPU_ID_NIC_QMAN_ARC23,
+	[GAUDI2_QUEUE_ID_ROT_0_0] = CPU_ID_ROT_QMAN_ARC0,
+	[GAUDI2_QUEUE_ID_ROT_0_1] = CPU_ID_ROT_QMAN_ARC0,
+	[GAUDI2_QUEUE_ID_ROT_0_2] = CPU_ID_ROT_QMAN_ARC0,
+	[GAUDI2_QUEUE_ID_ROT_0_3] = CPU_ID_ROT_QMAN_ARC0,
+	[GAUDI2_QUEUE_ID_ROT_1_0] = CPU_ID_ROT_QMAN_ARC1,
+	[GAUDI2_QUEUE_ID_ROT_1_1] = CPU_ID_ROT_QMAN_ARC1,
+	[GAUDI2_QUEUE_ID_ROT_1_2] = CPU_ID_ROT_QMAN_ARC1,
+	[GAUDI2_QUEUE_ID_ROT_1_3] = CPU_ID_ROT_QMAN_ARC1
+};
+
+const u32 gaudi2_dma_core_blocks_bases[DMA_CORE_ID_SIZE] = {
+	[DMA_CORE_ID_PDMA0] = mmPDMA0_CORE_BASE,
+	[DMA_CORE_ID_PDMA1] = mmPDMA1_CORE_BASE,
+	[DMA_CORE_ID_EDMA0] = mmDCORE0_EDMA0_CORE_BASE,
+	[DMA_CORE_ID_EDMA1] = mmDCORE0_EDMA1_CORE_BASE,
+	[DMA_CORE_ID_EDMA2] = mmDCORE1_EDMA0_CORE_BASE,
+	[DMA_CORE_ID_EDMA3] = mmDCORE1_EDMA1_CORE_BASE,
+	[DMA_CORE_ID_EDMA4] = mmDCORE2_EDMA0_CORE_BASE,
+	[DMA_CORE_ID_EDMA5] = mmDCORE2_EDMA1_CORE_BASE,
+	[DMA_CORE_ID_EDMA6] = mmDCORE3_EDMA0_CORE_BASE,
+	[DMA_CORE_ID_EDMA7] = mmDCORE3_EDMA1_CORE_BASE,
+	[DMA_CORE_ID_KDMA] = mmARC_FARM_KDMA_BASE
+};
+
+const u32 gaudi2_mme_acc_blocks_bases[MME_ID_SIZE] = {
+	[MME_ID_DCORE0] = mmDCORE0_MME_ACC_BASE,
+	[MME_ID_DCORE1] = mmDCORE1_MME_ACC_BASE,
+	[MME_ID_DCORE2] = mmDCORE2_MME_ACC_BASE,
+	[MME_ID_DCORE3] = mmDCORE3_MME_ACC_BASE
+};
+
+static const u32 gaudi2_tpc_cfg_blocks_bases[TPC_ID_SIZE] = {
+	[TPC_ID_DCORE0_TPC0] = mmDCORE0_TPC0_CFG_BASE,
+	[TPC_ID_DCORE0_TPC1] = mmDCORE0_TPC1_CFG_BASE,
+	[TPC_ID_DCORE0_TPC2] = mmDCORE0_TPC2_CFG_BASE,
+	[TPC_ID_DCORE0_TPC3] = mmDCORE0_TPC3_CFG_BASE,
+	[TPC_ID_DCORE0_TPC4] = mmDCORE0_TPC4_CFG_BASE,
+	[TPC_ID_DCORE0_TPC5] = mmDCORE0_TPC5_CFG_BASE,
+	[TPC_ID_DCORE1_TPC0] = mmDCORE1_TPC0_CFG_BASE,
+	[TPC_ID_DCORE1_TPC1] = mmDCORE1_TPC1_CFG_BASE,
+	[TPC_ID_DCORE1_TPC2] = mmDCORE1_TPC2_CFG_BASE,
+	[TPC_ID_DCORE1_TPC3] = mmDCORE1_TPC3_CFG_BASE,
+	[TPC_ID_DCORE1_TPC4] = mmDCORE1_TPC4_CFG_BASE,
+	[TPC_ID_DCORE1_TPC5] = mmDCORE1_TPC5_CFG_BASE,
+	[TPC_ID_DCORE2_TPC0] = mmDCORE2_TPC0_CFG_BASE,
+	[TPC_ID_DCORE2_TPC1] = mmDCORE2_TPC1_CFG_BASE,
+	[TPC_ID_DCORE2_TPC2] = mmDCORE2_TPC2_CFG_BASE,
+	[TPC_ID_DCORE2_TPC3] = mmDCORE2_TPC3_CFG_BASE,
+	[TPC_ID_DCORE2_TPC4] = mmDCORE2_TPC4_CFG_BASE,
+	[TPC_ID_DCORE2_TPC5] = mmDCORE2_TPC5_CFG_BASE,
+	[TPC_ID_DCORE3_TPC0] = mmDCORE3_TPC0_CFG_BASE,
+	[TPC_ID_DCORE3_TPC1] = mmDCORE3_TPC1_CFG_BASE,
+	[TPC_ID_DCORE3_TPC2] = mmDCORE3_TPC2_CFG_BASE,
+	[TPC_ID_DCORE3_TPC3] = mmDCORE3_TPC3_CFG_BASE,
+	[TPC_ID_DCORE3_TPC4] = mmDCORE3_TPC4_CFG_BASE,
+	[TPC_ID_DCORE3_TPC5] = mmDCORE3_TPC5_CFG_BASE,
+	[TPC_ID_DCORE0_TPC6] = mmDCORE0_TPC6_CFG_BASE,
+};
+
+static const u32 gaudi2_tpc_eml_cfg_blocks_bases[TPC_ID_SIZE] = {
+	[TPC_ID_DCORE0_TPC0] = mmDCORE0_TPC0_EML_CFG_BASE,
+	[TPC_ID_DCORE0_TPC1] = mmDCORE0_TPC1_EML_CFG_BASE,
+	[TPC_ID_DCORE0_TPC2] = mmDCORE0_TPC2_EML_CFG_BASE,
+	[TPC_ID_DCORE0_TPC3] = mmDCORE0_TPC3_EML_CFG_BASE,
+	[TPC_ID_DCORE0_TPC4] = mmDCORE0_TPC4_EML_CFG_BASE,
+	[TPC_ID_DCORE0_TPC5] = mmDCORE0_TPC5_EML_CFG_BASE,
+	[TPC_ID_DCORE1_TPC0] = mmDCORE1_TPC0_EML_CFG_BASE,
+	[TPC_ID_DCORE1_TPC1] = mmDCORE1_TPC1_EML_CFG_BASE,
+	[TPC_ID_DCORE1_TPC2] = mmDCORE1_TPC2_EML_CFG_BASE,
+	[TPC_ID_DCORE1_TPC3] = mmDCORE1_TPC3_EML_CFG_BASE,
+	[TPC_ID_DCORE1_TPC4] = mmDCORE1_TPC4_EML_CFG_BASE,
+	[TPC_ID_DCORE1_TPC5] = mmDCORE1_TPC5_EML_CFG_BASE,
+	[TPC_ID_DCORE2_TPC0] = mmDCORE2_TPC0_EML_CFG_BASE,
+	[TPC_ID_DCORE2_TPC1] = mmDCORE2_TPC1_EML_CFG_BASE,
+	[TPC_ID_DCORE2_TPC2] = mmDCORE2_TPC2_EML_CFG_BASE,
+	[TPC_ID_DCORE2_TPC3] = mmDCORE2_TPC3_EML_CFG_BASE,
+	[TPC_ID_DCORE2_TPC4] = mmDCORE2_TPC4_EML_CFG_BASE,
+	[TPC_ID_DCORE2_TPC5] = mmDCORE2_TPC5_EML_CFG_BASE,
+	[TPC_ID_DCORE3_TPC0] = mmDCORE3_TPC0_EML_CFG_BASE,
+	[TPC_ID_DCORE3_TPC1] = mmDCORE3_TPC1_EML_CFG_BASE,
+	[TPC_ID_DCORE3_TPC2] = mmDCORE3_TPC2_EML_CFG_BASE,
+	[TPC_ID_DCORE3_TPC3] = mmDCORE3_TPC3_EML_CFG_BASE,
+	[TPC_ID_DCORE3_TPC4] = mmDCORE3_TPC4_EML_CFG_BASE,
+	[TPC_ID_DCORE3_TPC5] = mmDCORE3_TPC5_EML_CFG_BASE,
+	[TPC_ID_DCORE0_TPC6] = mmDCORE0_TPC6_EML_CFG_BASE,
+};
+
+const u32 gaudi2_rot_blocks_bases[ROTATOR_ID_SIZE] = {
+	[ROTATOR_ID_0] = mmROT0_BASE,
+	[ROTATOR_ID_1] = mmROT1_BASE
+};
+
+static const u32 gaudi2_tpc_id_to_queue_id[TPC_ID_SIZE] = {
+	[TPC_ID_DCORE0_TPC0] = GAUDI2_QUEUE_ID_DCORE0_TPC_0_0,
+	[TPC_ID_DCORE0_TPC1] = GAUDI2_QUEUE_ID_DCORE0_TPC_1_0,
+	[TPC_ID_DCORE0_TPC2] = GAUDI2_QUEUE_ID_DCORE0_TPC_2_0,
+	[TPC_ID_DCORE0_TPC3] = GAUDI2_QUEUE_ID_DCORE0_TPC_3_0,
+	[TPC_ID_DCORE0_TPC4] = GAUDI2_QUEUE_ID_DCORE0_TPC_4_0,
+	[TPC_ID_DCORE0_TPC5] = GAUDI2_QUEUE_ID_DCORE0_TPC_5_0,
+	[TPC_ID_DCORE1_TPC0] = GAUDI2_QUEUE_ID_DCORE1_TPC_0_0,
+	[TPC_ID_DCORE1_TPC1] = GAUDI2_QUEUE_ID_DCORE1_TPC_1_0,
+	[TPC_ID_DCORE1_TPC2] = GAUDI2_QUEUE_ID_DCORE1_TPC_2_0,
+	[TPC_ID_DCORE1_TPC3] = GAUDI2_QUEUE_ID_DCORE1_TPC_3_0,
+	[TPC_ID_DCORE1_TPC4] = GAUDI2_QUEUE_ID_DCORE1_TPC_4_0,
+	[TPC_ID_DCORE1_TPC5] = GAUDI2_QUEUE_ID_DCORE1_TPC_5_0,
+	[TPC_ID_DCORE2_TPC0] = GAUDI2_QUEUE_ID_DCORE2_TPC_0_0,
+	[TPC_ID_DCORE2_TPC1] = GAUDI2_QUEUE_ID_DCORE2_TPC_1_0,
+	[TPC_ID_DCORE2_TPC2] = GAUDI2_QUEUE_ID_DCORE2_TPC_2_0,
+	[TPC_ID_DCORE2_TPC3] = GAUDI2_QUEUE_ID_DCORE2_TPC_3_0,
+	[TPC_ID_DCORE2_TPC4] = GAUDI2_QUEUE_ID_DCORE2_TPC_4_0,
+	[TPC_ID_DCORE2_TPC5] = GAUDI2_QUEUE_ID_DCORE2_TPC_5_0,
+	[TPC_ID_DCORE3_TPC0] = GAUDI2_QUEUE_ID_DCORE3_TPC_0_0,
+	[TPC_ID_DCORE3_TPC1] = GAUDI2_QUEUE_ID_DCORE3_TPC_1_0,
+	[TPC_ID_DCORE3_TPC2] = GAUDI2_QUEUE_ID_DCORE3_TPC_2_0,
+	[TPC_ID_DCORE3_TPC3] = GAUDI2_QUEUE_ID_DCORE3_TPC_3_0,
+	[TPC_ID_DCORE3_TPC4] = GAUDI2_QUEUE_ID_DCORE3_TPC_4_0,
+	[TPC_ID_DCORE3_TPC5] = GAUDI2_QUEUE_ID_DCORE3_TPC_5_0,
+	[TPC_ID_DCORE0_TPC6] = GAUDI2_QUEUE_ID_DCORE0_TPC_6_0,
+};
+
+static const u32 gaudi2_rot_id_to_queue_id[ROTATOR_ID_SIZE] = {
+	[ROTATOR_ID_0] = GAUDI2_QUEUE_ID_ROT_0_0,
+	[ROTATOR_ID_1] = GAUDI2_QUEUE_ID_ROT_1_0,
+};
+
+static const u32 gaudi2_tpc_engine_id_to_tpc_id[] = {
+	[GAUDI2_DCORE0_ENGINE_ID_TPC_0] = TPC_ID_DCORE0_TPC0,
+	[GAUDI2_DCORE0_ENGINE_ID_TPC_1] = TPC_ID_DCORE0_TPC1,
+	[GAUDI2_DCORE0_ENGINE_ID_TPC_2] = TPC_ID_DCORE0_TPC2,
+	[GAUDI2_DCORE0_ENGINE_ID_TPC_3] = TPC_ID_DCORE0_TPC3,
+	[GAUDI2_DCORE0_ENGINE_ID_TPC_4] = TPC_ID_DCORE0_TPC4,
+	[GAUDI2_DCORE0_ENGINE_ID_TPC_5] = TPC_ID_DCORE0_TPC5,
+	[GAUDI2_DCORE1_ENGINE_ID_TPC_0] = TPC_ID_DCORE1_TPC0,
+	[GAUDI2_DCORE1_ENGINE_ID_TPC_1] = TPC_ID_DCORE1_TPC1,
+	[GAUDI2_DCORE1_ENGINE_ID_TPC_2] = TPC_ID_DCORE1_TPC2,
+	[GAUDI2_DCORE1_ENGINE_ID_TPC_3] = TPC_ID_DCORE1_TPC3,
+	[GAUDI2_DCORE1_ENGINE_ID_TPC_4] = TPC_ID_DCORE1_TPC4,
+	[GAUDI2_DCORE1_ENGINE_ID_TPC_5] = TPC_ID_DCORE1_TPC5,
+	[GAUDI2_DCORE2_ENGINE_ID_TPC_0] = TPC_ID_DCORE2_TPC0,
+	[GAUDI2_DCORE2_ENGINE_ID_TPC_1] = TPC_ID_DCORE2_TPC1,
+	[GAUDI2_DCORE2_ENGINE_ID_TPC_2] = TPC_ID_DCORE2_TPC2,
+	[GAUDI2_DCORE2_ENGINE_ID_TPC_3] = TPC_ID_DCORE2_TPC3,
+	[GAUDI2_DCORE2_ENGINE_ID_TPC_4] = TPC_ID_DCORE2_TPC4,
+	[GAUDI2_DCORE2_ENGINE_ID_TPC_5] = TPC_ID_DCORE2_TPC5,
+	[GAUDI2_DCORE3_ENGINE_ID_TPC_0] = TPC_ID_DCORE3_TPC0,
+	[GAUDI2_DCORE3_ENGINE_ID_TPC_1] = TPC_ID_DCORE3_TPC1,
+	[GAUDI2_DCORE3_ENGINE_ID_TPC_2] = TPC_ID_DCORE3_TPC2,
+	[GAUDI2_DCORE3_ENGINE_ID_TPC_3] = TPC_ID_DCORE3_TPC3,
+	[GAUDI2_DCORE3_ENGINE_ID_TPC_4] = TPC_ID_DCORE3_TPC4,
+	[GAUDI2_DCORE3_ENGINE_ID_TPC_5] = TPC_ID_DCORE3_TPC5,
+	/* the PCI TPC is placed last (mapped liked HW) */
+	[GAUDI2_DCORE0_ENGINE_ID_TPC_6] = TPC_ID_DCORE0_TPC6,
+};
+
+static const u32 gaudi2_mme_engine_id_to_mme_id[] = {
+	[GAUDI2_DCORE0_ENGINE_ID_MME] = MME_ID_DCORE0,
+	[GAUDI2_DCORE1_ENGINE_ID_MME] = MME_ID_DCORE1,
+	[GAUDI2_DCORE2_ENGINE_ID_MME] = MME_ID_DCORE2,
+	[GAUDI2_DCORE3_ENGINE_ID_MME] = MME_ID_DCORE3,
+};
+
+static const u32 gaudi2_edma_engine_id_to_edma_id[] = {
+	[GAUDI2_ENGINE_ID_PDMA_0] = DMA_CORE_ID_PDMA0,
+	[GAUDI2_ENGINE_ID_PDMA_1] = DMA_CORE_ID_PDMA1,
+	[GAUDI2_DCORE0_ENGINE_ID_EDMA_0] = DMA_CORE_ID_EDMA0,
+	[GAUDI2_DCORE0_ENGINE_ID_EDMA_1] = DMA_CORE_ID_EDMA1,
+	[GAUDI2_DCORE1_ENGINE_ID_EDMA_0] = DMA_CORE_ID_EDMA2,
+	[GAUDI2_DCORE1_ENGINE_ID_EDMA_1] = DMA_CORE_ID_EDMA3,
+	[GAUDI2_DCORE2_ENGINE_ID_EDMA_0] = DMA_CORE_ID_EDMA4,
+	[GAUDI2_DCORE2_ENGINE_ID_EDMA_1] = DMA_CORE_ID_EDMA5,
+	[GAUDI2_DCORE3_ENGINE_ID_EDMA_0] = DMA_CORE_ID_EDMA6,
+	[GAUDI2_DCORE3_ENGINE_ID_EDMA_1] = DMA_CORE_ID_EDMA7,
+	[GAUDI2_ENGINE_ID_KDMA] = DMA_CORE_ID_KDMA,
+};
+
+const u32 edma_stream_base[NUM_OF_EDMA_PER_DCORE * NUM_OF_DCORES] = {
+	GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0,
+	GAUDI2_QUEUE_ID_DCORE0_EDMA_1_0,
+	GAUDI2_QUEUE_ID_DCORE1_EDMA_0_0,
+	GAUDI2_QUEUE_ID_DCORE1_EDMA_1_0,
+	GAUDI2_QUEUE_ID_DCORE2_EDMA_0_0,
+	GAUDI2_QUEUE_ID_DCORE2_EDMA_1_0,
+	GAUDI2_QUEUE_ID_DCORE3_EDMA_0_0,
+	GAUDI2_QUEUE_ID_DCORE3_EDMA_1_0,
+};
+
+static const char gaudi2_vdec_irq_name[GAUDI2_VDEC_MSIX_ENTRIES][GAUDI2_MAX_STRING_LEN] = {
+	"gaudi2 vdec 0_0", "gaudi2 vdec 0_0 abnormal",
+	"gaudi2 vdec 0_1", "gaudi2 vdec 0_1 abnormal",
+	"gaudi2 vdec 1_0", "gaudi2 vdec 1_0 abnormal",
+	"gaudi2 vdec 1_1", "gaudi2 vdec 1_1 abnormal",
+	"gaudi2 vdec 2_0", "gaudi2 vdec 2_0 abnormal",
+	"gaudi2 vdec 2_1", "gaudi2 vdec 2_1 abnormal",
+	"gaudi2 vdec 3_0", "gaudi2 vdec 3_0 abnormal",
+	"gaudi2 vdec 3_1", "gaudi2 vdec 3_1 abnormal",
+	"gaudi2 vdec s_0", "gaudi2 vdec s_0 abnormal",
+	"gaudi2 vdec s_1", "gaudi2 vdec s_1 abnormal"
+};
+
+enum rtr_id {
+	DCORE0_RTR0,
+	DCORE0_RTR1,
+	DCORE0_RTR2,
+	DCORE0_RTR3,
+	DCORE0_RTR4,
+	DCORE0_RTR5,
+	DCORE0_RTR6,
+	DCORE0_RTR7,
+	DCORE1_RTR0,
+	DCORE1_RTR1,
+	DCORE1_RTR2,
+	DCORE1_RTR3,
+	DCORE1_RTR4,
+	DCORE1_RTR5,
+	DCORE1_RTR6,
+	DCORE1_RTR7,
+	DCORE2_RTR0,
+	DCORE2_RTR1,
+	DCORE2_RTR2,
+	DCORE2_RTR3,
+	DCORE2_RTR4,
+	DCORE2_RTR5,
+	DCORE2_RTR6,
+	DCORE2_RTR7,
+	DCORE3_RTR0,
+	DCORE3_RTR1,
+	DCORE3_RTR2,
+	DCORE3_RTR3,
+	DCORE3_RTR4,
+	DCORE3_RTR5,
+	DCORE3_RTR6,
+	DCORE3_RTR7,
+};
+
+static const u32 gaudi2_tpc_initiator_hbw_rtr_id[NUM_OF_TPC_PER_DCORE * NUM_OF_DCORES + 1] = {
+	DCORE0_RTR1, DCORE0_RTR1, DCORE0_RTR2, DCORE0_RTR2, DCORE0_RTR3, DCORE0_RTR3,
+	DCORE1_RTR6, DCORE1_RTR6, DCORE1_RTR5, DCORE1_RTR5, DCORE1_RTR4, DCORE1_RTR4,
+	DCORE2_RTR3, DCORE2_RTR3, DCORE2_RTR2, DCORE2_RTR2, DCORE2_RTR1, DCORE2_RTR1,
+	DCORE3_RTR4, DCORE3_RTR4, DCORE3_RTR5, DCORE3_RTR5, DCORE3_RTR6, DCORE3_RTR6,
+	DCORE0_RTR0
+};
+
+static const u32 gaudi2_tpc_initiator_lbw_rtr_id[NUM_OF_TPC_PER_DCORE * NUM_OF_DCORES + 1] = {
+	DCORE0_RTR1, DCORE0_RTR1, DCORE0_RTR1, DCORE0_RTR1, DCORE0_RTR2, DCORE0_RTR2,
+	DCORE1_RTR7, DCORE1_RTR7, DCORE1_RTR6, DCORE1_RTR6, DCORE1_RTR5, DCORE1_RTR5,
+	DCORE2_RTR2, DCORE2_RTR2, DCORE2_RTR1, DCORE2_RTR1, DCORE2_RTR0, DCORE2_RTR0,
+	DCORE3_RTR5, DCORE3_RTR5, DCORE3_RTR6, DCORE3_RTR6, DCORE3_RTR7, DCORE3_RTR7,
+	DCORE0_RTR0
+};
+
+static const u32 gaudi2_dec_initiator_hbw_rtr_id[NUMBER_OF_DEC] = {
+	DCORE0_RTR0, DCORE0_RTR0, DCORE1_RTR7, DCORE1_RTR7, DCORE2_RTR0, DCORE2_RTR0,
+	DCORE3_RTR7, DCORE3_RTR7, DCORE0_RTR0, DCORE0_RTR0
+};
+
+static const u32 gaudi2_dec_initiator_lbw_rtr_id[NUMBER_OF_DEC] = {
+	DCORE0_RTR1, DCORE0_RTR1, DCORE1_RTR6, DCORE1_RTR6, DCORE2_RTR1, DCORE2_RTR1,
+	DCORE3_RTR6, DCORE3_RTR6, DCORE0_RTR0, DCORE0_RTR0
+};
+
+static const u32 gaudi2_nic_initiator_hbw_rtr_id[NIC_NUMBER_OF_MACROS] = {
+	DCORE1_RTR7, DCORE1_RTR7, DCORE1_RTR7, DCORE1_RTR7, DCORE1_RTR7, DCORE2_RTR0,
+	DCORE2_RTR0, DCORE2_RTR0, DCORE2_RTR0, DCORE3_RTR7, DCORE3_RTR7, DCORE3_RTR7
+};
+
+static const u32 gaudi2_nic_initiator_lbw_rtr_id[NIC_NUMBER_OF_MACROS] = {
+	DCORE1_RTR7, DCORE1_RTR7, DCORE1_RTR7, DCORE1_RTR7, DCORE1_RTR7, DCORE2_RTR0,
+	DCORE2_RTR0, DCORE2_RTR0, DCORE2_RTR0, DCORE3_RTR7, DCORE3_RTR7, DCORE3_RTR7
+};
+
+static const u32 gaudi2_edma_initiator_hbw_sft[NUM_OF_EDMA_PER_DCORE * NUM_OF_DCORES] = {
+	mmSFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE,
+	mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE,
+	mmSFT1_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE,
+	mmSFT1_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE,
+	mmSFT2_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE,
+	mmSFT2_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE,
+	mmSFT3_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE,
+	mmSFT3_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE
+};
+
+static const u32 gaudi2_pdma_initiator_hbw_rtr_id[NUM_OF_PDMA] = {
+	DCORE0_RTR0, DCORE0_RTR0
+};
+
+static const u32 gaudi2_pdma_initiator_lbw_rtr_id[NUM_OF_PDMA] = {
+	DCORE0_RTR2, DCORE0_RTR2
+};
+
+static const u32 gaudi2_rot_initiator_hbw_rtr_id[NUM_OF_ROT] = {
+	DCORE2_RTR0, DCORE3_RTR7
+};
+
+static const u32 gaudi2_rot_initiator_lbw_rtr_id[NUM_OF_ROT] = {
+	DCORE2_RTR2, DCORE3_RTR5
+};
+
+struct mme_initiators_rtr_id {
+	u32 wap0;
+	u32 wap1;
+	u32 write;
+	u32 read;
+	u32 sbte0;
+	u32 sbte1;
+	u32 sbte2;
+	u32 sbte3;
+	u32 sbte4;
+};
+
+enum mme_initiators {
+	MME_WAP0 = 0,
+	MME_WAP1,
+	MME_WRITE,
+	MME_READ,
+	MME_SBTE0,
+	MME_SBTE1,
+	MME_SBTE2,
+	MME_SBTE3,
+	MME_SBTE4,
+	MME_INITIATORS_MAX
+};
+
+static const struct mme_initiators_rtr_id
+gaudi2_mme_initiator_rtr_id[NUM_OF_MME_PER_DCORE * NUM_OF_DCORES] = {
+	{ .wap0 = 5, .wap1 = 7, .write = 6, .read = 7,
+	.sbte0 = 7, .sbte1 = 4, .sbte2 = 4, .sbte3 = 5, .sbte4 = 6},
+	{ .wap0 = 10, .wap1 = 8, .write = 9, .read = 8,
+	.sbte0 = 11, .sbte1 = 11, .sbte2 = 10, .sbte3 = 9, .sbte4 = 8},
+	{ .wap0 = 21, .wap1 = 23, .write = 22, .read = 23,
+	.sbte0 = 20, .sbte1 = 20, .sbte2 = 21, .sbte3 = 22, .sbte4 = 23},
+	{ .wap0 = 30, .wap1 = 28, .write = 29, .read = 30,
+	.sbte0 = 31, .sbte1 = 31, .sbte2 = 30, .sbte3 = 29, .sbte4 = 28},
+};
+
+enum razwi_event_sources {
+	RAZWI_TPC,
+	RAZWI_MME,
+	RAZWI_EDMA,
+	RAZWI_PDMA,
+	RAZWI_NIC,
+	RAZWI_DEC,
+	RAZWI_ROT,
+	RAZWI_ARC_FARM
+};
+
+struct hbm_mc_error_causes {
+	u32 mask;
+	char cause[50];
+};
+
+static struct hl_special_block_info gaudi2_special_blocks[] = GAUDI2_SPECIAL_BLOCKS;
+
+/* Special blocks iterator is currently used to configure security protection bits,
+ * and read global errors. Most HW blocks are addressable and those who aren't (N/A)-
+ * must be skipped. Following configurations are commonly used for both PB config
+ * and global error reading, since currently they both share the same settings.
+ * Once it changes, we must remember to use separate configurations for either one.
+ */
+static int gaudi2_iterator_skip_block_types[] = {
+		GAUDI2_BLOCK_TYPE_PLL,
+		GAUDI2_BLOCK_TYPE_EU_BIST,
+		GAUDI2_BLOCK_TYPE_HBM,
+		GAUDI2_BLOCK_TYPE_XFT
+};
+
+static struct range gaudi2_iterator_skip_block_ranges[] = {
+		/* Skip all PSOC blocks except for PSOC_GLOBAL_CONF */
+		{mmPSOC_I2C_M0_BASE, mmPSOC_EFUSE_BASE},
+		{mmPSOC_BTL_BASE, mmPSOC_MSTR_IF_RR_SHRD_HBW_BASE},
+		/* Skip all CPU blocks except for CPU_IF */
+		{mmCPU_CA53_CFG_BASE, mmCPU_CA53_CFG_BASE},
+		{mmCPU_TIMESTAMP_BASE, mmCPU_MSTR_IF_RR_SHRD_HBW_BASE}
+};
+
+static struct hbm_mc_error_causes hbm_mc_spi[GAUDI2_NUM_OF_HBM_MC_SPI_CAUSE] = {
+	{HBM_MC_SPI_TEMP_PIN_CHG_MASK, "temperature pins changed"},
+	{HBM_MC_SPI_THR_ENG_MASK, "temperature-based throttling engaged"},
+	{HBM_MC_SPI_THR_DIS_ENG_MASK, "temperature-based throttling disengaged"},
+	{HBM_MC_SPI_IEEE1500_COMP_MASK, "IEEE1500 op comp"},
+	{HBM_MC_SPI_IEEE1500_PAUSED_MASK, "IEEE1500 op paused"},
+};
+
+static const char * const hbm_mc_sei_cause[GAUDI2_NUM_OF_HBM_SEI_CAUSE] = {
+	[HBM_SEI_CMD_PARITY_EVEN] = "SEI C/A parity even",
+	[HBM_SEI_CMD_PARITY_ODD] = "SEI C/A parity odd",
+	[HBM_SEI_READ_ERR] = "SEI read data error",
+	[HBM_SEI_WRITE_DATA_PARITY_ERR] = "SEI write data parity error",
+	[HBM_SEI_CATTRIP] = "SEI CATTRIP asserted",
+	[HBM_SEI_MEM_BIST_FAIL] = "SEI memory BIST fail",
+	[HBM_SEI_DFI] = "SEI DFI error",
+	[HBM_SEI_INV_TEMP_READ_OUT] = "SEI invalid temp read",
+	[HBM_SEI_BIST_FAIL] = "SEI BIST fail"
+};
+
+struct mmu_spi_sei_cause {
+	char cause[50];
+	int clear_bit;
+};
+
+static const struct mmu_spi_sei_cause gaudi2_mmu_spi_sei[GAUDI2_NUM_OF_MMU_SPI_SEI_CAUSE] = {
+	{"page fault", 1},		/* INTERRUPT_CLR[1] */
+	{"page access", 1},		/* INTERRUPT_CLR[1] */
+	{"bypass ddr", 2},		/* INTERRUPT_CLR[2] */
+	{"multi hit", 2},		/* INTERRUPT_CLR[2] */
+	{"mmu rei0", -1},		/* no clear register bit */
+	{"mmu rei1", -1},		/* no clear register bit */
+	{"stlb rei0", -1},		/* no clear register bit */
+	{"stlb rei1", -1},		/* no clear register bit */
+	{"rr privileged write hit", 2},	/* INTERRUPT_CLR[2] */
+	{"rr privileged read hit", 2},	/* INTERRUPT_CLR[2] */
+	{"rr secure write hit", 2},	/* INTERRUPT_CLR[2] */
+	{"rr secure read hit", 2},	/* INTERRUPT_CLR[2] */
+	{"bist_fail no use", 2},	/* INTERRUPT_CLR[2] */
+	{"bist_fail no use", 2},	/* INTERRUPT_CLR[2] */
+	{"bist_fail no use", 2},	/* INTERRUPT_CLR[2] */
+	{"bist_fail no use", 2},	/* INTERRUPT_CLR[2] */
+	{"slave error", 16},		/* INTERRUPT_CLR[16] */
+	{"dec error", 17},		/* INTERRUPT_CLR[17] */
+	{"burst fifo full", 2}		/* INTERRUPT_CLR[2] */
+};
+
+struct gaudi2_cache_invld_params {
+	u64 start_va;
+	u64 end_va;
+	u32 inv_start_val;
+	u32 flags;
+	bool range_invalidation;
+};
+
+struct gaudi2_tpc_idle_data {
+	struct engines_data *e;
+	unsigned long *mask;
+	bool *is_idle;
+	const char *tpc_fmt;
+};
+
+struct gaudi2_tpc_mmu_data {
+	u32 rw_asid;
+};
+
+static s64 gaudi2_state_dump_specs_props[SP_MAX] = {0};
+
+static int gaudi2_memset_device_memory(struct hl_device *hdev, u64 addr, u64 size, u64 val);
+static bool gaudi2_is_queue_enabled(struct hl_device *hdev, u32 hw_queue_id);
+static bool gaudi2_is_arc_enabled(struct hl_device *hdev, u64 arc_id);
+static void gaudi2_clr_arc_id_cap(struct hl_device *hdev, u64 arc_id);
+static void gaudi2_set_arc_id_cap(struct hl_device *hdev, u64 arc_id);
+static void gaudi2_memset_device_lbw(struct hl_device *hdev, u32 addr, u32 size, u32 val);
+static int gaudi2_send_job_to_kdma(struct hl_device *hdev, u64 src_addr, u64 dst_addr, u32 size,
+										bool is_memset);
+static bool gaudi2_get_tpc_idle_status(struct hl_device *hdev, u64 *mask_arr, u8 mask_len,
+		struct engines_data *e);
+static bool gaudi2_get_mme_idle_status(struct hl_device *hdev, u64 *mask_arr, u8 mask_len,
+		struct engines_data *e);
+static bool gaudi2_get_edma_idle_status(struct hl_device *hdev, u64 *mask_arr, u8 mask_len,
+		struct engines_data *e);
+static u64 gaudi2_mmu_scramble_addr(struct hl_device *hdev, u64 raw_addr);
+static u64 gaudi2_mmu_descramble_addr(struct hl_device *hdev, u64 scrambled_addr);
+
+static void gaudi2_init_scrambler_hbm(struct hl_device *hdev)
+{
+
+}
+
+static u32 gaudi2_get_signal_cb_size(struct hl_device *hdev)
+{
+	return sizeof(struct packet_msg_short);
+}
+
+static u32 gaudi2_get_wait_cb_size(struct hl_device *hdev)
+{
+	return sizeof(struct packet_msg_short) * 4 + sizeof(struct packet_fence);
+}
+
+void gaudi2_iterate_tpcs(struct hl_device *hdev, struct iterate_module_ctx *ctx)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	int dcore, inst, tpc_seq;
+	u32 offset;
+
+	/* init the return code */
+	ctx->rc = 0;
+
+	for (dcore = 0; dcore < NUM_OF_DCORES; dcore++) {
+		for (inst = 0; inst < NUM_OF_TPC_PER_DCORE; inst++) {
+			tpc_seq = dcore * NUM_OF_TPC_PER_DCORE + inst;
+
+			if (!(prop->tpc_enabled_mask & BIT(tpc_seq)))
+				continue;
+
+			offset = (DCORE_OFFSET * dcore) + (DCORE_TPC_OFFSET * inst);
+
+			ctx->fn(hdev, dcore, inst, offset, ctx);
+			if (ctx->rc) {
+				dev_err(hdev->dev, "TPC iterator failed for DCORE%d TPC%d\n",
+							dcore, inst);
+				return;
+			}
+		}
+	}
+
+	if (!(prop->tpc_enabled_mask & BIT(TPC_ID_DCORE0_TPC6)))
+		return;
+
+	/* special check for PCI TPC (DCORE0_TPC6) */
+	offset = DCORE_TPC_OFFSET * (NUM_DCORE0_TPC - 1);
+	ctx->fn(hdev, 0, NUM_DCORE0_TPC - 1, offset, ctx);
+	if (ctx->rc)
+		dev_err(hdev->dev, "TPC iterator failed for DCORE0 TPC6\n");
+}
+
+static bool gaudi2_host_phys_addr_valid(u64 addr)
+{
+	if ((addr < HOST_PHYS_BASE_0 + HOST_PHYS_SIZE_0) || (addr >= HOST_PHYS_BASE_1))
+		return true;
+
+	return false;
+}
+
+static int set_number_of_functional_hbms(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	u8 faulty_hbms = hweight64(hdev->dram_binning);
+
+	/* check if all HBMs should be used */
+	if (!faulty_hbms) {
+		dev_dbg(hdev->dev, "All HBM are in use (no binning)\n");
+		prop->num_functional_hbms = GAUDI2_HBM_NUM;
+		return 0;
+	}
+
+	/*
+	 * check for error condition in which number of binning
+	 * candidates is higher than the maximum supported by the
+	 * driver (in which case binning mask shall be ignored and driver will
+	 * set the default)
+	 */
+	if (faulty_hbms > MAX_FAULTY_HBMS) {
+		dev_err(hdev->dev,
+			"HBM binning supports max of %d faulty HBMs, supplied mask 0x%llx.\n",
+			MAX_FAULTY_HBMS, hdev->dram_binning);
+		return -EINVAL;
+	}
+
+	/*
+	 * by default, number of functional HBMs in Gaudi2 is always
+	 * GAUDI2_HBM_NUM - 1.
+	 */
+	prop->num_functional_hbms = GAUDI2_HBM_NUM - faulty_hbms;
+	return 0;
+}
+
+static bool gaudi2_is_edma_queue_id(u32 queue_id)
+{
+
+	switch (queue_id) {
+	case GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0...GAUDI2_QUEUE_ID_DCORE0_EDMA_1_3:
+	case GAUDI2_QUEUE_ID_DCORE1_EDMA_0_0...GAUDI2_QUEUE_ID_DCORE1_EDMA_1_3:
+	case GAUDI2_QUEUE_ID_DCORE2_EDMA_0_0...GAUDI2_QUEUE_ID_DCORE2_EDMA_1_3:
+	case GAUDI2_QUEUE_ID_DCORE3_EDMA_0_0...GAUDI2_QUEUE_ID_DCORE3_EDMA_1_3:
+		return true;
+	default:
+		return false;
+	}
+}
+
+static int gaudi2_set_dram_properties(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	u64 hbm_drv_base_offset = 0, edma_pq_base_addr;
+	u32 basic_hbm_page_size, edma_idx = 0;
+	int rc, i;
+
+	rc = set_number_of_functional_hbms(hdev);
+	if (rc)
+		return -EINVAL;
+
+	/*
+	 * Due to HW bug in which TLB size is x16 smaller than expected we use a workaround
+	 * in which we are using x16 bigger page size to be able to populate the entire
+	 * HBM mappings in the TLB
+	 */
+	basic_hbm_page_size = prop->num_functional_hbms * SZ_8M;
+	prop->dram_page_size = GAUDI2_COMPENSATE_TLB_PAGE_SIZE_FACTOR * basic_hbm_page_size;
+	prop->device_mem_alloc_default_page_size = prop->dram_page_size;
+	prop->dram_size = prop->num_functional_hbms * SZ_16G;
+	prop->dram_base_address = DRAM_PHYS_BASE;
+	prop->dram_end_address = prop->dram_base_address + prop->dram_size;
+	prop->dram_supports_virtual_memory = true;
+
+	prop->dram_user_base_address = DRAM_PHYS_BASE + prop->dram_page_size;
+	prop->dram_hints_align_mask = ~GAUDI2_HBM_MMU_SCRM_ADDRESS_MASK;
+	prop->hints_dram_reserved_va_range.start_addr = RESERVED_VA_RANGE_FOR_ARC_ON_HBM_START;
+	prop->hints_dram_reserved_va_range.end_addr = RESERVED_VA_RANGE_FOR_ARC_ON_HBM_END;
+
+	/* since DRAM page size differs from DMMU page size we need to allocate
+	 * DRAM memory in units of dram_page size and mapping this memory in
+	 * units of DMMU page size. we overcome this size mismatch using a
+	 * scrambling routine which takes a DRAM page and converts it to a DMMU
+	 * page.
+	 * We therefore:
+	 * 1. partition the virtual address space to DRAM-page (whole) pages.
+	 *    (suppose we get n such pages)
+	 * 2. limit the amount of virtual address space we got from 1 above to
+	 *    a multiple of 64M as we don't want the scrambled address to cross
+	 *    the DRAM virtual address space.
+	 *    ( m = (n * DRAM_page_size) / DMMU_page_size).
+	 * 3. determine the and address accordingly
+	 *    end_addr = start_addr + m * 48M
+	 *
+	 *    the DRAM address MSBs (63:48) are not part of the roundup calculation
+	 */
+	prop->dmmu.start_addr = prop->dram_base_address +
+			(prop->dram_page_size *
+				DIV_ROUND_UP_SECTOR_T(prop->dram_size, prop->dram_page_size));
+	prop->dmmu.end_addr = prop->dmmu.start_addr + prop->dram_page_size *
+			div_u64((VA_HBM_SPACE_END - prop->dmmu.start_addr), prop->dmmu.page_size);
+	/*
+	 * Driver can't share an (48MB) HBM page with the F/W in order to prevent FW to block
+	 * the driver part by range register, so it must start at the next (48MB) page
+	 */
+	hbm_drv_base_offset = roundup(CPU_FW_IMAGE_SIZE, prop->num_functional_hbms * SZ_8M);
+
+	/*
+	 * The NIC driver section size and the HMMU page tables section in the HBM needs
+	 * to be the remaining size in the first dram page after taking into
+	 * account the F/W image size
+	 */
+
+	/* Reserve region in HBM for HMMU page tables */
+	prop->mmu_pgt_addr = DRAM_PHYS_BASE + hbm_drv_base_offset +
+				((prop->dram_page_size - hbm_drv_base_offset) -
+				(HMMU_PAGE_TABLES_SIZE + EDMA_PQS_SIZE + EDMA_SCRATCHPAD_SIZE));
+
+	/* Set EDMA PQs HBM addresses */
+	edma_pq_base_addr = prop->mmu_pgt_addr + HMMU_PAGE_TABLES_SIZE;
+
+	for (i = 0 ; i < GAUDI2_QUEUE_ID_CPU_PQ ; i++) {
+		if (gaudi2_is_edma_queue_id(i)) {
+			prop->hw_queues_props[i].q_dram_bd_address = edma_pq_base_addr +
+							(edma_idx * HL_QUEUE_SIZE_IN_BYTES);
+			edma_idx++;
+		}
+	}
+
+	return 0;
+}
+
+static int gaudi2_set_fixed_properties(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct hw_queue_properties *q_props;
+	u32 num_sync_stream_queues = 0;
+	int i, rc;
+
+	prop->max_queues = GAUDI2_QUEUE_ID_SIZE;
+	prop->hw_queues_props = kcalloc(prop->max_queues, sizeof(struct hw_queue_properties),
+					GFP_KERNEL);
+
+	if (!prop->hw_queues_props)
+		return -ENOMEM;
+
+	q_props = prop->hw_queues_props;
+
+	for (i = 0 ; i < GAUDI2_QUEUE_ID_CPU_PQ ; i++) {
+		q_props[i].type = QUEUE_TYPE_HW;
+		q_props[i].driver_only = 0;
+
+		if (i >= GAUDI2_QUEUE_ID_NIC_0_0 && i <= GAUDI2_QUEUE_ID_NIC_23_3) {
+			q_props[i].supports_sync_stream = 0;
+		} else {
+			q_props[i].supports_sync_stream = 1;
+			num_sync_stream_queues++;
+		}
+
+		q_props[i].cb_alloc_flags = CB_ALLOC_USER;
+
+		if (gaudi2_is_edma_queue_id(i))
+			q_props[i].dram_bd = 1;
+	}
+
+	q_props[GAUDI2_QUEUE_ID_CPU_PQ].type = QUEUE_TYPE_CPU;
+	q_props[GAUDI2_QUEUE_ID_CPU_PQ].driver_only = 1;
+	q_props[GAUDI2_QUEUE_ID_CPU_PQ].cb_alloc_flags = CB_ALLOC_KERNEL;
+
+	prop->cache_line_size = DEVICE_CACHE_LINE_SIZE;
+	prop->cfg_base_address = CFG_BASE;
+	prop->device_dma_offset_for_host_access = HOST_PHYS_BASE_0;
+	prop->host_base_address = HOST_PHYS_BASE_0;
+	prop->host_end_address = prop->host_base_address + HOST_PHYS_SIZE_0;
+	prop->max_pending_cs = GAUDI2_MAX_PENDING_CS;
+	prop->completion_queues_count = GAUDI2_RESERVED_CQ_NUMBER;
+	prop->user_dec_intr_count = NUMBER_OF_DEC;
+	prop->user_interrupt_count = GAUDI2_IRQ_NUM_USER_LAST - GAUDI2_IRQ_NUM_USER_FIRST + 1;
+	prop->completion_mode = HL_COMPLETION_MODE_CS;
+	prop->sync_stream_first_sob = GAUDI2_RESERVED_SOB_NUMBER;
+	prop->sync_stream_first_mon = GAUDI2_RESERVED_MON_NUMBER;
+
+	prop->sram_base_address = SRAM_BASE_ADDR;
+	prop->sram_size = SRAM_SIZE;
+	prop->sram_end_address = prop->sram_base_address + prop->sram_size;
+	prop->sram_user_base_address = prop->sram_base_address + SRAM_USER_BASE_OFFSET;
+
+	prop->hints_range_reservation = true;
+
+	prop->rotator_enabled_mask = BIT(NUM_OF_ROT) - 1;
+
+	prop->max_asid = 2;
+
+	prop->dmmu.pgt_size = HMMU_PAGE_TABLES_SIZE;
+	prop->mmu_pte_size = HL_PTE_SIZE;
+
+	prop->dmmu.hop_shifts[MMU_HOP0] = DHOP0_SHIFT;
+	prop->dmmu.hop_shifts[MMU_HOP1] = DHOP1_SHIFT;
+	prop->dmmu.hop_shifts[MMU_HOP2] = DHOP2_SHIFT;
+	prop->dmmu.hop_shifts[MMU_HOP3] = DHOP3_SHIFT;
+	prop->dmmu.hop_masks[MMU_HOP0] = DHOP0_MASK;
+	prop->dmmu.hop_masks[MMU_HOP1] = DHOP1_MASK;
+	prop->dmmu.hop_masks[MMU_HOP2] = DHOP2_MASK;
+	prop->dmmu.hop_masks[MMU_HOP3] = DHOP3_MASK;
+	prop->dmmu.page_size = PAGE_SIZE_1GB;
+	prop->dmmu.num_hops = MMU_ARCH_4_HOPS;
+	prop->dmmu.last_mask = LAST_MASK;
+	prop->dmmu.host_resident = 0;
+	prop->dmmu.hop_table_size = HOP_TABLE_SIZE_512_PTE;
+	prop->dmmu.hop0_tables_total_size = HOP_TABLE_SIZE_512_PTE * prop->max_asid;
+
+	/* As we need to set the pgt address in dram for HMMU init so we cannot
+	 * wait to the fw cpucp info to set the dram props as mmu init comes before
+	 * hw init
+	 */
+	rc = hdev->asic_funcs->set_dram_properties(hdev);
+	if (rc)
+		goto free_qprops;
+
+	prop->mmu_pgt_size = PMMU_PAGE_TABLES_SIZE;
+
+	prop->pmmu.pgt_size = prop->mmu_pgt_size;
+	hdev->pmmu_huge_range = true;
+	prop->pmmu.host_resident = 1;
+	prop->pmmu.num_hops = MMU_ARCH_6_HOPS;
+	prop->pmmu.last_mask = LAST_MASK;
+	prop->pmmu.hop_table_size = HOP_TABLE_SIZE_512_PTE;
+	prop->pmmu.hop0_tables_total_size = HOP_TABLE_SIZE_512_PTE * prop->max_asid;
+
+	prop->hints_host_reserved_va_range.start_addr = RESERVED_VA_FOR_VIRTUAL_MSIX_DOORBELL_START;
+	prop->hints_host_reserved_va_range.end_addr = RESERVED_VA_RANGE_FOR_ARC_ON_HOST_END;
+	prop->hints_host_hpage_reserved_va_range.start_addr =
+			RESERVED_VA_RANGE_FOR_ARC_ON_HOST_HPAGE_START;
+	prop->hints_host_hpage_reserved_va_range.end_addr =
+			RESERVED_VA_RANGE_FOR_ARC_ON_HOST_HPAGE_END;
+
+	if (PAGE_SIZE == SZ_64K) {
+		prop->pmmu.hop_shifts[MMU_HOP0] = HOP0_SHIFT_64K;
+		prop->pmmu.hop_shifts[MMU_HOP1] = HOP1_SHIFT_64K;
+		prop->pmmu.hop_shifts[MMU_HOP2] = HOP2_SHIFT_64K;
+		prop->pmmu.hop_shifts[MMU_HOP3] = HOP3_SHIFT_64K;
+		prop->pmmu.hop_shifts[MMU_HOP4] = HOP4_SHIFT_64K;
+		prop->pmmu.hop_shifts[MMU_HOP5] = HOP5_SHIFT_64K;
+		prop->pmmu.hop_masks[MMU_HOP0] = HOP0_MASK_64K;
+		prop->pmmu.hop_masks[MMU_HOP1] = HOP1_MASK_64K;
+		prop->pmmu.hop_masks[MMU_HOP2] = HOP2_MASK_64K;
+		prop->pmmu.hop_masks[MMU_HOP3] = HOP3_MASK_64K;
+		prop->pmmu.hop_masks[MMU_HOP4] = HOP4_MASK_64K;
+		prop->pmmu.hop_masks[MMU_HOP5] = HOP5_MASK_64K;
+		prop->pmmu.start_addr = VA_HOST_SPACE_PAGE_START;
+		prop->pmmu.end_addr = VA_HOST_SPACE_PAGE_END;
+		prop->pmmu.page_size = PAGE_SIZE_64KB;
+
+		/* shifts and masks are the same in PMMU and HPMMU */
+		memcpy(&prop->pmmu_huge, &prop->pmmu, sizeof(prop->pmmu));
+		prop->pmmu_huge.page_size = PAGE_SIZE_16MB;
+		prop->pmmu_huge.start_addr = VA_HOST_SPACE_HPAGE_START;
+		prop->pmmu_huge.end_addr = VA_HOST_SPACE_HPAGE_END;
+	} else {
+		prop->pmmu.hop_shifts[MMU_HOP0] = HOP0_SHIFT_4K;
+		prop->pmmu.hop_shifts[MMU_HOP1] = HOP1_SHIFT_4K;
+		prop->pmmu.hop_shifts[MMU_HOP2] = HOP2_SHIFT_4K;
+		prop->pmmu.hop_shifts[MMU_HOP3] = HOP3_SHIFT_4K;
+		prop->pmmu.hop_shifts[MMU_HOP4] = HOP4_SHIFT_4K;
+		prop->pmmu.hop_shifts[MMU_HOP5] = HOP5_SHIFT_4K;
+		prop->pmmu.hop_masks[MMU_HOP0] = HOP0_MASK_4K;
+		prop->pmmu.hop_masks[MMU_HOP1] = HOP1_MASK_4K;
+		prop->pmmu.hop_masks[MMU_HOP2] = HOP2_MASK_4K;
+		prop->pmmu.hop_masks[MMU_HOP3] = HOP3_MASK_4K;
+		prop->pmmu.hop_masks[MMU_HOP4] = HOP4_MASK_4K;
+		prop->pmmu.hop_masks[MMU_HOP5] = HOP5_MASK_4K;
+		prop->pmmu.start_addr = VA_HOST_SPACE_PAGE_START;
+		prop->pmmu.end_addr = VA_HOST_SPACE_PAGE_END;
+		prop->pmmu.page_size = PAGE_SIZE_4KB;
+
+		/* shifts and masks are the same in PMMU and HPMMU */
+		memcpy(&prop->pmmu_huge, &prop->pmmu, sizeof(prop->pmmu));
+		prop->pmmu_huge.page_size = PAGE_SIZE_2MB;
+		prop->pmmu_huge.start_addr = VA_HOST_SPACE_HPAGE_START;
+		prop->pmmu_huge.end_addr = VA_HOST_SPACE_HPAGE_END;
+	}
+
+	prop->max_num_of_engines = GAUDI2_ENGINE_ID_SIZE;
+	prop->num_engine_cores = CPU_ID_MAX;
+	prop->cfg_size = CFG_SIZE;
+	prop->num_of_events = GAUDI2_EVENT_SIZE;
+
+	prop->supports_engine_modes = true;
+
+	prop->dc_power_default = DC_POWER_DEFAULT;
+
+	prop->cb_pool_cb_cnt = GAUDI2_CB_POOL_CB_CNT;
+	prop->cb_pool_cb_size = GAUDI2_CB_POOL_CB_SIZE;
+	prop->pcie_dbi_base_address = CFG_BASE + mmPCIE_DBI_BASE;
+	prop->pcie_aux_dbi_reg_addr = CFG_BASE + mmPCIE_AUX_DBI;
+
+	strscpy_pad(prop->cpucp_info.card_name, GAUDI2_DEFAULT_CARD_NAME, CARD_NAME_MAX_LEN);
+
+	prop->mme_master_slave_mode = 1;
+
+	prop->first_available_user_sob[0] = GAUDI2_RESERVED_SOB_NUMBER +
+					(num_sync_stream_queues * HL_RSVD_SOBS);
+
+	prop->first_available_user_mon[0] = GAUDI2_RESERVED_MON_NUMBER +
+					(num_sync_stream_queues * HL_RSVD_MONS);
+
+	prop->first_available_user_interrupt = GAUDI2_IRQ_NUM_USER_FIRST;
+	prop->tpc_interrupt_id = GAUDI2_IRQ_NUM_TPC_ASSERT;
+	prop->eq_interrupt_id = GAUDI2_IRQ_NUM_EVENT_QUEUE;
+
+	prop->first_available_cq[0] = GAUDI2_RESERVED_CQ_NUMBER;
+
+	prop->fw_cpu_boot_dev_sts0_valid = false;
+	prop->fw_cpu_boot_dev_sts1_valid = false;
+	prop->hard_reset_done_by_fw = false;
+	prop->gic_interrupts_enable = true;
+
+	prop->server_type = HL_SERVER_TYPE_UNKNOWN;
+
+	prop->max_dec = NUMBER_OF_DEC;
+
+	prop->clk_pll_index = HL_GAUDI2_MME_PLL;
+
+	prop->dma_mask = 64;
+
+	prop->hbw_flush_reg = mmPCIE_WRAP_SPECIAL_GLBL_SPARE_0;
+
+	prop->supports_advanced_cpucp_rc = true;
+
+	return 0;
+
+free_qprops:
+	kfree(prop->hw_queues_props);
+	return rc;
+}
+
+static int gaudi2_pci_bars_map(struct hl_device *hdev)
+{
+	static const char * const name[] = {"CFG_SRAM", "MSIX", "DRAM"};
+	bool is_wc[3] = {false, false, true};
+	int rc;
+
+	rc = hl_pci_bars_map(hdev, name, is_wc);
+	if (rc)
+		return rc;
+
+	hdev->rmmio = hdev->pcie_bar[SRAM_CFG_BAR_ID] + (CFG_BASE - STM_FLASH_BASE_ADDR);
+
+	return 0;
+}
+
+static u64 gaudi2_set_hbm_bar_base(struct hl_device *hdev, u64 addr)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	struct hl_inbound_pci_region pci_region;
+	u64 old_addr = addr;
+	int rc;
+
+	if ((gaudi2) && (gaudi2->dram_bar_cur_addr == addr))
+		return old_addr;
+
+	if (hdev->asic_prop.iatu_done_by_fw)
+		return U64_MAX;
+
+	/* Inbound Region 2 - Bar 4 - Point to DRAM */
+	pci_region.mode = PCI_BAR_MATCH_MODE;
+	pci_region.bar = DRAM_BAR_ID;
+	pci_region.addr = addr;
+	rc = hl_pci_set_inbound_region(hdev, 2, &pci_region);
+	if (rc)
+		return U64_MAX;
+
+	if (gaudi2) {
+		old_addr = gaudi2->dram_bar_cur_addr;
+		gaudi2->dram_bar_cur_addr = addr;
+	}
+
+	return old_addr;
+}
+
+static int gaudi2_init_iatu(struct hl_device *hdev)
+{
+	struct hl_inbound_pci_region inbound_region;
+	struct hl_outbound_pci_region outbound_region;
+	u32 bar_addr_low, bar_addr_high;
+	int rc;
+
+	if (hdev->asic_prop.iatu_done_by_fw)
+		return 0;
+
+	/* Temporary inbound Region 0 - Bar 0 - Point to CFG
+	 * We must map this region in BAR match mode in order to
+	 * fetch BAR physical base address
+	 */
+	inbound_region.mode = PCI_BAR_MATCH_MODE;
+	inbound_region.bar = SRAM_CFG_BAR_ID;
+	/* Base address must be aligned to Bar size which is 256 MB */
+	inbound_region.addr = STM_FLASH_BASE_ADDR - STM_FLASH_ALIGNED_OFF;
+	rc = hl_pci_set_inbound_region(hdev, 0, &inbound_region);
+	if (rc)
+		return rc;
+
+	/* Fetch physical BAR address */
+	bar_addr_high = RREG32(mmPCIE_DBI_BAR1_REG + STM_FLASH_ALIGNED_OFF);
+	bar_addr_low = RREG32(mmPCIE_DBI_BAR0_REG + STM_FLASH_ALIGNED_OFF) & ~0xF;
+
+	hdev->pcie_bar_phys[SRAM_CFG_BAR_ID] = (u64)bar_addr_high << 32 | bar_addr_low;
+
+	/* Inbound Region 0 - Bar 0 - Point to CFG */
+	inbound_region.mode = PCI_ADDRESS_MATCH_MODE;
+	inbound_region.bar = SRAM_CFG_BAR_ID;
+	inbound_region.offset_in_bar = 0;
+	inbound_region.addr = STM_FLASH_BASE_ADDR;
+	inbound_region.size = CFG_REGION_SIZE;
+	rc = hl_pci_set_inbound_region(hdev, 0, &inbound_region);
+	if (rc)
+		return rc;
+
+	/* Inbound Region 1 - Bar 0 - Point to BAR0_RESERVED + SRAM */
+	inbound_region.mode = PCI_ADDRESS_MATCH_MODE;
+	inbound_region.bar = SRAM_CFG_BAR_ID;
+	inbound_region.offset_in_bar = CFG_REGION_SIZE;
+	inbound_region.addr = BAR0_RSRVD_BASE_ADDR;
+	inbound_region.size = BAR0_RSRVD_SIZE + SRAM_SIZE;
+	rc = hl_pci_set_inbound_region(hdev, 1, &inbound_region);
+	if (rc)
+		return rc;
+
+	/* Inbound Region 2 - Bar 4 - Point to DRAM */
+	inbound_region.mode = PCI_BAR_MATCH_MODE;
+	inbound_region.bar = DRAM_BAR_ID;
+	inbound_region.addr = DRAM_PHYS_BASE;
+	rc = hl_pci_set_inbound_region(hdev, 2, &inbound_region);
+	if (rc)
+		return rc;
+
+	/* Outbound Region 0 - Point to Host */
+	outbound_region.addr = HOST_PHYS_BASE_0;
+	outbound_region.size = HOST_PHYS_SIZE_0;
+	rc = hl_pci_set_outbound_region(hdev, &outbound_region);
+
+	return rc;
+}
+
+static enum hl_device_hw_state gaudi2_get_hw_state(struct hl_device *hdev)
+{
+	return RREG32(mmHW_STATE);
+}
+
+static int gaudi2_tpc_binning_init_prop(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+
+	/*
+	 * check for error condition in which number of binning candidates
+	 * is higher than the maximum supported by the driver
+	 */
+	if (hweight64(hdev->tpc_binning) > MAX_CLUSTER_BINNING_FAULTY_TPCS) {
+		dev_err(hdev->dev, "TPC binning is supported for max of %d faulty TPCs, provided mask 0x%llx\n",
+					MAX_CLUSTER_BINNING_FAULTY_TPCS,
+					hdev->tpc_binning);
+		return -EINVAL;
+	}
+
+	prop->tpc_binning_mask = hdev->tpc_binning;
+	prop->tpc_enabled_mask = GAUDI2_TPC_FULL_MASK;
+
+	return 0;
+}
+
+static int gaudi2_set_tpc_binning_masks(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct hw_queue_properties *q_props = prop->hw_queues_props;
+	u64 tpc_binning_mask;
+	u8 subst_idx = 0;
+	int i, rc;
+
+	rc = gaudi2_tpc_binning_init_prop(hdev);
+	if (rc)
+		return rc;
+
+	tpc_binning_mask = prop->tpc_binning_mask;
+
+	for (i = 0 ; i < MAX_FAULTY_TPCS ; i++) {
+		u8 subst_seq, binned, qid_base;
+
+		if (tpc_binning_mask == 0)
+			break;
+
+		if (subst_idx == 0) {
+			subst_seq = TPC_ID_DCORE0_TPC6;
+			qid_base = GAUDI2_QUEUE_ID_DCORE0_TPC_6_0;
+		} else {
+			subst_seq = TPC_ID_DCORE3_TPC5;
+			qid_base = GAUDI2_QUEUE_ID_DCORE3_TPC_5_0;
+		}
+
+
+		/* clear bit from mask */
+		binned = __ffs(tpc_binning_mask);
+		/*
+		 * Coverity complains about possible out-of-bound access in
+		 * clear_bit
+		 */
+		if (binned >= TPC_ID_SIZE) {
+			dev_err(hdev->dev,
+				"Invalid binned TPC (binning mask: %llx)\n",
+				tpc_binning_mask);
+			return -EINVAL;
+		}
+		clear_bit(binned, (unsigned long *)&tpc_binning_mask);
+
+		/* also clear replacing TPC bit from enabled mask */
+		clear_bit(subst_seq, (unsigned long *)&prop->tpc_enabled_mask);
+
+		/* bin substite TPC's Qs */
+		q_props[qid_base].binned = 1;
+		q_props[qid_base + 1].binned = 1;
+		q_props[qid_base + 2].binned = 1;
+		q_props[qid_base + 3].binned = 1;
+
+		subst_idx++;
+	}
+
+	return 0;
+}
+
+static int gaudi2_set_dec_binning_masks(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	u8 num_faulty;
+
+	num_faulty = hweight32(hdev->decoder_binning);
+
+	/*
+	 * check for error condition in which number of binning candidates
+	 * is higher than the maximum supported by the driver
+	 */
+	if (num_faulty > MAX_FAULTY_DECODERS) {
+		dev_err(hdev->dev, "decoder binning is supported for max of single faulty decoder, provided mask 0x%x\n",
+						hdev->decoder_binning);
+		return -EINVAL;
+	}
+
+	prop->decoder_binning_mask = (hdev->decoder_binning & GAUDI2_DECODER_FULL_MASK);
+
+	if (prop->decoder_binning_mask)
+		prop->decoder_enabled_mask = (GAUDI2_DECODER_FULL_MASK & ~BIT(DEC_ID_PCIE_VDEC1));
+	else
+		prop->decoder_enabled_mask = GAUDI2_DECODER_FULL_MASK;
+
+	return 0;
+}
+
+static void gaudi2_set_dram_binning_masks(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+
+	/* check if we should override default binning */
+	if (!hdev->dram_binning) {
+		prop->dram_binning_mask = 0;
+		prop->dram_enabled_mask = GAUDI2_DRAM_FULL_MASK;
+		return;
+	}
+
+	/* set DRAM binning constraints */
+	prop->faulty_dram_cluster_map |= hdev->dram_binning;
+	prop->dram_binning_mask = hdev->dram_binning;
+	prop->dram_enabled_mask = GAUDI2_DRAM_FULL_MASK & ~BIT(HBM_ID5);
+}
+
+static int gaudi2_set_edma_binning_masks(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct hw_queue_properties *q_props;
+	u8 seq, num_faulty;
+
+	num_faulty = hweight32(hdev->edma_binning);
+
+	/*
+	 * check for error condition in which number of binning candidates
+	 * is higher than the maximum supported by the driver
+	 */
+	if (num_faulty > MAX_FAULTY_EDMAS) {
+		dev_err(hdev->dev,
+			"EDMA binning is supported for max of single faulty EDMA, provided mask 0x%x\n",
+			hdev->edma_binning);
+		return -EINVAL;
+	}
+
+	if (!hdev->edma_binning) {
+		prop->edma_binning_mask = 0;
+		prop->edma_enabled_mask = GAUDI2_EDMA_FULL_MASK;
+		return 0;
+	}
+
+	seq = __ffs((unsigned long)hdev->edma_binning);
+
+	/* set binning constraints */
+	prop->faulty_dram_cluster_map |= BIT(edma_to_hbm_cluster[seq]);
+	prop->edma_binning_mask = hdev->edma_binning;
+	prop->edma_enabled_mask = GAUDI2_EDMA_FULL_MASK & ~BIT(EDMA_ID_DCORE3_INSTANCE1);
+
+	/* bin substitute EDMA's queue */
+	q_props = prop->hw_queues_props;
+	q_props[GAUDI2_QUEUE_ID_DCORE3_EDMA_1_0].binned = 1;
+	q_props[GAUDI2_QUEUE_ID_DCORE3_EDMA_1_1].binned = 1;
+	q_props[GAUDI2_QUEUE_ID_DCORE3_EDMA_1_2].binned = 1;
+	q_props[GAUDI2_QUEUE_ID_DCORE3_EDMA_1_3].binned = 1;
+
+	return 0;
+}
+
+static int gaudi2_set_xbar_edge_enable_mask(struct hl_device *hdev, u32 xbar_edge_iso_mask)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	u8 num_faulty, seq;
+
+	/* check if we should override default binning */
+	if (!xbar_edge_iso_mask) {
+		prop->xbar_edge_enabled_mask = GAUDI2_XBAR_EDGE_FULL_MASK;
+		return 0;
+	}
+
+	/*
+	 * note that it can be set to value other than 0 only after cpucp packet (i.e.
+	 * only the FW can set a redundancy value). for user it'll always be 0.
+	 */
+	num_faulty = hweight32(xbar_edge_iso_mask);
+
+	/*
+	 * check for error condition in which number of binning candidates
+	 * is higher than the maximum supported by the driver
+	 */
+	if (num_faulty > MAX_FAULTY_XBARS) {
+		dev_err(hdev->dev, "we cannot have more than %d faulty XBAR EDGE\n",
+									MAX_FAULTY_XBARS);
+		return -EINVAL;
+	}
+
+	seq = __ffs((unsigned long)xbar_edge_iso_mask);
+
+	/* set binning constraints */
+	prop->faulty_dram_cluster_map |= BIT(xbar_edge_to_hbm_cluster[seq]);
+	prop->xbar_edge_enabled_mask = (~xbar_edge_iso_mask) & GAUDI2_XBAR_EDGE_FULL_MASK;
+
+	return 0;
+}
+
+static int gaudi2_set_cluster_binning_masks_common(struct hl_device *hdev, u8 xbar_edge_iso_mask)
+{
+	int rc;
+
+	/*
+	 * mark all clusters as good, each component will "fail" cluster
+	 * based on eFuse/user values.
+	 * If more than single cluster is faulty- the chip is unusable
+	 */
+	hdev->asic_prop.faulty_dram_cluster_map = 0;
+
+	gaudi2_set_dram_binning_masks(hdev);
+
+	rc = gaudi2_set_edma_binning_masks(hdev);
+	if (rc)
+		return rc;
+
+	rc = gaudi2_set_xbar_edge_enable_mask(hdev, xbar_edge_iso_mask);
+	if (rc)
+		return rc;
+
+
+	/* always initially set to full mask */
+	hdev->asic_prop.hmmu_hif_enabled_mask = GAUDI2_HIF_HMMU_FULL_MASK;
+
+	return 0;
+}
+
+static int gaudi2_set_cluster_binning_masks(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	int rc;
+
+	rc = gaudi2_set_cluster_binning_masks_common(hdev, prop->cpucp_info.xbar_binning_mask);
+	if (rc)
+		return rc;
+
+	/* if we have DRAM binning reported by FW we should perform cluster config  */
+	if (prop->faulty_dram_cluster_map) {
+		u8 cluster_seq = __ffs((unsigned long)prop->faulty_dram_cluster_map);
+
+		prop->hmmu_hif_enabled_mask = cluster_hmmu_hif_enabled_mask[cluster_seq];
+	}
+
+	return 0;
+}
+
+static int gaudi2_set_binning_masks(struct hl_device *hdev)
+{
+	int rc;
+
+	rc = gaudi2_set_cluster_binning_masks(hdev);
+	if (rc)
+		return rc;
+
+	rc = gaudi2_set_tpc_binning_masks(hdev);
+	if (rc)
+		return rc;
+
+	rc = gaudi2_set_dec_binning_masks(hdev);
+	if (rc)
+		return rc;
+
+	return 0;
+}
+
+static int gaudi2_cpucp_info_get(struct hl_device *hdev)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	long max_power;
+	u64 dram_size;
+	int rc;
+
+	if (!(gaudi2->hw_cap_initialized & HW_CAP_CPU_Q))
+		return 0;
+
+	/* No point of asking this information again when not doing hard reset, as the device
+	 * CPU hasn't been reset
+	 */
+	if (hdev->reset_info.in_compute_reset)
+		return 0;
+
+	rc = hl_fw_cpucp_handshake(hdev, mmCPU_BOOT_DEV_STS0, mmCPU_BOOT_DEV_STS1, mmCPU_BOOT_ERR0,
+										mmCPU_BOOT_ERR1);
+	if (rc)
+		return rc;
+
+	dram_size = le64_to_cpu(prop->cpucp_info.dram_size);
+	if (dram_size) {
+		/* we can have wither 5 or 6 HBMs. other values are invalid */
+
+		if ((dram_size != ((GAUDI2_HBM_NUM - 1) * SZ_16G)) &&
+					(dram_size != (GAUDI2_HBM_NUM * SZ_16G))) {
+			dev_err(hdev->dev,
+				"F/W reported invalid DRAM size %llu. Trying to use default size %llu\n",
+				dram_size, prop->dram_size);
+			dram_size = prop->dram_size;
+		}
+
+		prop->dram_size = dram_size;
+		prop->dram_end_address = prop->dram_base_address + dram_size;
+	}
+
+	if (!strlen(prop->cpucp_info.card_name))
+		strscpy_pad(prop->cpucp_info.card_name, GAUDI2_DEFAULT_CARD_NAME,
+				CARD_NAME_MAX_LEN);
+
+	/* Overwrite binning masks with the actual binning values from F/W */
+	hdev->dram_binning = prop->cpucp_info.dram_binning_mask;
+	hdev->edma_binning = prop->cpucp_info.edma_binning_mask;
+	hdev->tpc_binning = le64_to_cpu(prop->cpucp_info.tpc_binning_mask);
+	hdev->decoder_binning = lower_32_bits(le64_to_cpu(prop->cpucp_info.decoder_binning_mask));
+
+	dev_dbg(hdev->dev, "Read binning masks: tpc: 0x%llx, dram: 0x%llx, edma: 0x%x, dec: 0x%x\n",
+			hdev->tpc_binning, hdev->dram_binning, hdev->edma_binning,
+			hdev->decoder_binning);
+
+	/*
+	 * at this point the DRAM parameters need to be updated according to data obtained
+	 * from the FW
+	 */
+	rc = hdev->asic_funcs->set_dram_properties(hdev);
+	if (rc)
+		return rc;
+
+	rc = hdev->asic_funcs->set_binning_masks(hdev);
+	if (rc)
+		return rc;
+
+	max_power = hl_fw_get_max_power(hdev);
+	if (max_power < 0)
+		return max_power;
+
+	prop->max_power_default = (u64) max_power;
+
+	return 0;
+}
+
+static int gaudi2_fetch_psoc_frequency(struct hl_device *hdev)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	u16 pll_freq_arr[HL_PLL_NUM_OUTPUTS];
+	int rc;
+
+	if (!(gaudi2->hw_cap_initialized & HW_CAP_CPU_Q))
+		return 0;
+
+	rc = hl_fw_cpucp_pll_info_get(hdev, HL_GAUDI2_CPU_PLL, pll_freq_arr);
+	if (rc)
+		return rc;
+
+	hdev->asic_prop.psoc_timestamp_frequency = pll_freq_arr[3];
+
+	return 0;
+}
+
+static int gaudi2_mmu_clear_pgt_range(struct hl_device *hdev)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	int rc;
+
+	if (!(gaudi2->hw_cap_initialized & HW_CAP_MMU_MASK))
+		return 0;
+
+	if (prop->dmmu.host_resident)
+		return 0;
+
+	rc = gaudi2_memset_device_memory(hdev, prop->mmu_pgt_addr, prop->dmmu.pgt_size, 0);
+	if (rc)
+		dev_err(hdev->dev, "Failed to clear mmu pgt");
+
+	return rc;
+}
+
+static int gaudi2_early_init(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct pci_dev *pdev = hdev->pdev;
+	resource_size_t pci_bar_size;
+	int rc;
+
+	rc = gaudi2_set_fixed_properties(hdev);
+	if (rc)
+		return rc;
+
+	/* Check BAR sizes */
+	pci_bar_size = pci_resource_len(pdev, SRAM_CFG_BAR_ID);
+
+	if (pci_bar_size != CFG_BAR_SIZE) {
+		dev_err(hdev->dev, "Not " HL_NAME "? BAR %d size %pa, expecting %llu\n",
+			SRAM_CFG_BAR_ID, &pci_bar_size, CFG_BAR_SIZE);
+		rc = -ENODEV;
+		goto free_queue_props;
+	}
+
+	pci_bar_size = pci_resource_len(pdev, MSIX_BAR_ID);
+	if (pci_bar_size != MSIX_BAR_SIZE) {
+		dev_err(hdev->dev, "Not " HL_NAME "? BAR %d size %pa, expecting %llu\n",
+			MSIX_BAR_ID, &pci_bar_size, MSIX_BAR_SIZE);
+		rc = -ENODEV;
+		goto free_queue_props;
+	}
+
+	prop->dram_pci_bar_size = pci_resource_len(pdev, DRAM_BAR_ID);
+	hdev->dram_pci_bar_start = pci_resource_start(pdev, DRAM_BAR_ID);
+
+	/*
+	 * Only in pldm driver config iATU
+	 */
+	if (hdev->pldm)
+		hdev->asic_prop.iatu_done_by_fw = false;
+	else
+		hdev->asic_prop.iatu_done_by_fw = true;
+
+	rc = hl_pci_init(hdev);
+	if (rc)
+		goto free_queue_props;
+
+	/* Before continuing in the initialization, we need to read the preboot
+	 * version to determine whether we run with a security-enabled firmware
+	 */
+	rc = hl_fw_read_preboot_status(hdev);
+	if (rc) {
+		if (hdev->reset_on_preboot_fail)
+			hdev->asic_funcs->hw_fini(hdev, true, false);
+		goto pci_fini;
+	}
+
+	if (gaudi2_get_hw_state(hdev) == HL_DEVICE_HW_STATE_DIRTY) {
+		dev_dbg(hdev->dev, "H/W state is dirty, must reset before initializing\n");
+		rc = hdev->asic_funcs->hw_fini(hdev, true, false);
+		if (rc) {
+			dev_err(hdev->dev, "failed to reset HW in dirty state (%d)\n", rc);
+			goto pci_fini;
+		}
+
+		rc = hl_fw_read_preboot_status(hdev);
+		if (rc) {
+			if (hdev->reset_on_preboot_fail)
+				hdev->asic_funcs->hw_fini(hdev, true, false);
+			goto pci_fini;
+		}
+	}
+
+	return 0;
+
+pci_fini:
+	hl_pci_fini(hdev);
+free_queue_props:
+	kfree(hdev->asic_prop.hw_queues_props);
+	return rc;
+}
+
+static int gaudi2_early_fini(struct hl_device *hdev)
+{
+	kfree(hdev->asic_prop.hw_queues_props);
+	hl_pci_fini(hdev);
+
+	return 0;
+}
+
+static bool gaudi2_is_arc_nic_owned(u64 arc_id)
+{
+	switch (arc_id) {
+	case CPU_ID_NIC_QMAN_ARC0...CPU_ID_NIC_QMAN_ARC23:
+		return true;
+	default:
+		return false;
+	}
+}
+
+static bool gaudi2_is_arc_tpc_owned(u64 arc_id)
+{
+	switch (arc_id) {
+	case CPU_ID_TPC_QMAN_ARC0...CPU_ID_TPC_QMAN_ARC24:
+		return true;
+	default:
+		return false;
+	}
+}
+
+static void gaudi2_init_arcs(struct hl_device *hdev)
+{
+	struct cpu_dyn_regs *dyn_regs = &hdev->fw_loader.dynamic_loader.comm_desc.cpu_dyn_regs;
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	u64 arc_id;
+	u32 i;
+
+	for (i = CPU_ID_SCHED_ARC0 ; i <= CPU_ID_SCHED_ARC3 ; i++) {
+		if (gaudi2_is_arc_enabled(hdev, i))
+			continue;
+
+		gaudi2_set_arc_id_cap(hdev, i);
+	}
+
+	for (i = GAUDI2_QUEUE_ID_PDMA_0_0 ; i < GAUDI2_QUEUE_ID_CPU_PQ ; i += 4) {
+		if (!gaudi2_is_queue_enabled(hdev, i))
+			continue;
+
+		arc_id = gaudi2_queue_id_to_arc_id[i];
+		if (gaudi2_is_arc_enabled(hdev, arc_id))
+			continue;
+
+		if (gaudi2_is_arc_nic_owned(arc_id) &&
+				!(hdev->nic_ports_mask & BIT_ULL(arc_id - CPU_ID_NIC_QMAN_ARC0)))
+			continue;
+
+		if (gaudi2_is_arc_tpc_owned(arc_id) && !(gaudi2->tpc_hw_cap_initialized &
+							BIT_ULL(arc_id - CPU_ID_TPC_QMAN_ARC0)))
+			continue;
+
+		gaudi2_set_arc_id_cap(hdev, arc_id);
+	}
+
+	/* Fetch ARC scratchpad address */
+	hdev->asic_prop.engine_core_interrupt_reg_addr =
+		CFG_BASE + le32_to_cpu(dyn_regs->eng_arc_irq_ctrl);
+}
+
+static int gaudi2_scrub_arc_dccm(struct hl_device *hdev, u32 cpu_id)
+{
+	u32 reg_base, reg_val;
+	int rc;
+
+	switch (cpu_id) {
+	case CPU_ID_SCHED_ARC0 ... CPU_ID_SCHED_ARC3:
+		/* Each ARC scheduler has 2 consecutive DCCM blocks */
+		rc = gaudi2_send_job_to_kdma(hdev, 0, CFG_BASE + gaudi2_arc_dccm_bases[cpu_id],
+						ARC_DCCM_BLOCK_SIZE * 2, true);
+		if (rc)
+			return rc;
+		break;
+	case CPU_ID_SCHED_ARC4:
+	case CPU_ID_SCHED_ARC5:
+	case CPU_ID_MME_QMAN_ARC0:
+	case CPU_ID_MME_QMAN_ARC1:
+		reg_base = gaudi2_arc_blocks_bases[cpu_id];
+
+		/* Scrub lower DCCM block */
+		rc = gaudi2_send_job_to_kdma(hdev, 0, CFG_BASE + gaudi2_arc_dccm_bases[cpu_id],
+						ARC_DCCM_BLOCK_SIZE, true);
+		if (rc)
+			return rc;
+
+		/* Switch to upper DCCM block */
+		reg_val = FIELD_PREP(ARC_FARM_ARC0_AUX_MME_ARC_UPPER_DCCM_EN_VAL_MASK, 1);
+		WREG32(reg_base + ARC_DCCM_UPPER_EN_OFFSET, reg_val);
+
+		/* Scrub upper DCCM block */
+		rc = gaudi2_send_job_to_kdma(hdev, 0, CFG_BASE + gaudi2_arc_dccm_bases[cpu_id],
+						ARC_DCCM_BLOCK_SIZE, true);
+		if (rc)
+			return rc;
+
+		/* Switch to lower DCCM block */
+		reg_val = FIELD_PREP(ARC_FARM_ARC0_AUX_MME_ARC_UPPER_DCCM_EN_VAL_MASK, 0);
+		WREG32(reg_base + ARC_DCCM_UPPER_EN_OFFSET, reg_val);
+		break;
+	default:
+		rc = gaudi2_send_job_to_kdma(hdev, 0, CFG_BASE + gaudi2_arc_dccm_bases[cpu_id],
+						ARC_DCCM_BLOCK_SIZE, true);
+		if (rc)
+			return rc;
+	}
+
+	return 0;
+}
+
+static int gaudi2_scrub_arcs_dccm(struct hl_device *hdev)
+{
+	u16 arc_id;
+	int rc;
+
+	for (arc_id = CPU_ID_SCHED_ARC0 ; arc_id < CPU_ID_MAX ; arc_id++) {
+		if (!gaudi2_is_arc_enabled(hdev, arc_id))
+			continue;
+
+		rc = gaudi2_scrub_arc_dccm(hdev, arc_id);
+		if (rc)
+			return rc;
+	}
+
+	return 0;
+}
+
+static int gaudi2_late_init(struct hl_device *hdev)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	int rc;
+
+	rc = hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_ENABLE_PCI_ACCESS,
+					gaudi2->virt_msix_db_dma_addr);
+	if (rc)
+		return rc;
+
+	rc = gaudi2_fetch_psoc_frequency(hdev);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to fetch psoc frequency\n");
+		goto disable_pci_access;
+	}
+
+	rc = gaudi2_mmu_clear_pgt_range(hdev);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to clear MMU page tables range\n");
+		goto disable_pci_access;
+	}
+
+	gaudi2_init_arcs(hdev);
+
+	rc = gaudi2_scrub_arcs_dccm(hdev);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to scrub arcs DCCM\n");
+		goto disable_pci_access;
+	}
+
+	gaudi2_init_security(hdev);
+
+	return 0;
+
+disable_pci_access:
+	hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_DISABLE_PCI_ACCESS, 0x0);
+
+	return rc;
+}
+
+static void gaudi2_late_fini(struct hl_device *hdev)
+{
+	hl_hwmon_release_resources(hdev);
+}
+
+static void gaudi2_user_mapped_dec_init(struct gaudi2_device *gaudi2, u32 start_idx)
+{
+	struct user_mapped_block *blocks = gaudi2->mapped_blocks;
+
+	HL_USR_MAPPED_BLK_INIT(&blocks[start_idx++], mmDCORE0_DEC0_CMD_BASE, HL_BLOCK_SIZE);
+	HL_USR_MAPPED_BLK_INIT(&blocks[start_idx++], mmDCORE0_DEC1_CMD_BASE, HL_BLOCK_SIZE);
+	HL_USR_MAPPED_BLK_INIT(&blocks[start_idx++], mmDCORE1_DEC0_CMD_BASE, HL_BLOCK_SIZE);
+	HL_USR_MAPPED_BLK_INIT(&blocks[start_idx++], mmDCORE1_DEC1_CMD_BASE, HL_BLOCK_SIZE);
+	HL_USR_MAPPED_BLK_INIT(&blocks[start_idx++], mmDCORE2_DEC0_CMD_BASE, HL_BLOCK_SIZE);
+	HL_USR_MAPPED_BLK_INIT(&blocks[start_idx++], mmDCORE2_DEC1_CMD_BASE, HL_BLOCK_SIZE);
+	HL_USR_MAPPED_BLK_INIT(&blocks[start_idx++], mmDCORE3_DEC0_CMD_BASE, HL_BLOCK_SIZE);
+	HL_USR_MAPPED_BLK_INIT(&blocks[start_idx++], mmDCORE3_DEC1_CMD_BASE, HL_BLOCK_SIZE);
+	HL_USR_MAPPED_BLK_INIT(&blocks[start_idx++], mmPCIE_DEC0_CMD_BASE, HL_BLOCK_SIZE);
+	HL_USR_MAPPED_BLK_INIT(&blocks[start_idx], mmPCIE_DEC1_CMD_BASE, HL_BLOCK_SIZE);
+}
+
+static void gaudi2_user_mapped_blocks_init(struct hl_device *hdev)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	struct user_mapped_block *blocks = gaudi2->mapped_blocks;
+	u32 block_size, umr_start_idx, num_umr_blocks;
+	int i;
+
+	for (i = 0 ; i < NUM_ARC_CPUS ; i++) {
+		if (i >= CPU_ID_SCHED_ARC0 && i <= CPU_ID_SCHED_ARC3)
+			block_size = ARC_DCCM_BLOCK_SIZE * 2;
+		else
+			block_size = ARC_DCCM_BLOCK_SIZE;
+
+		blocks[i].address = gaudi2_arc_dccm_bases[i];
+		blocks[i].size = block_size;
+	}
+
+	blocks[NUM_ARC_CPUS].address = mmARC_FARM_ARC0_ACP_ENG_BASE;
+	blocks[NUM_ARC_CPUS].size = HL_BLOCK_SIZE;
+
+	blocks[NUM_ARC_CPUS + 1].address = mmARC_FARM_ARC1_ACP_ENG_BASE;
+	blocks[NUM_ARC_CPUS + 1].size = HL_BLOCK_SIZE;
+
+	blocks[NUM_ARC_CPUS + 2].address = mmARC_FARM_ARC2_ACP_ENG_BASE;
+	blocks[NUM_ARC_CPUS + 2].size = HL_BLOCK_SIZE;
+
+	blocks[NUM_ARC_CPUS + 3].address = mmARC_FARM_ARC3_ACP_ENG_BASE;
+	blocks[NUM_ARC_CPUS + 3].size = HL_BLOCK_SIZE;
+
+	blocks[NUM_ARC_CPUS + 4].address = mmDCORE0_MME_QM_ARC_ACP_ENG_BASE;
+	blocks[NUM_ARC_CPUS + 4].size = HL_BLOCK_SIZE;
+
+	blocks[NUM_ARC_CPUS + 5].address = mmDCORE1_MME_QM_ARC_ACP_ENG_BASE;
+	blocks[NUM_ARC_CPUS + 5].size = HL_BLOCK_SIZE;
+
+	blocks[NUM_ARC_CPUS + 6].address = mmDCORE2_MME_QM_ARC_ACP_ENG_BASE;
+	blocks[NUM_ARC_CPUS + 6].size = HL_BLOCK_SIZE;
+
+	blocks[NUM_ARC_CPUS + 7].address = mmDCORE3_MME_QM_ARC_ACP_ENG_BASE;
+	blocks[NUM_ARC_CPUS + 7].size = HL_BLOCK_SIZE;
+
+	umr_start_idx = NUM_ARC_CPUS + NUM_OF_USER_ACP_BLOCKS;
+	num_umr_blocks = NIC_NUMBER_OF_ENGINES * NUM_OF_USER_NIC_UMR_BLOCKS;
+	for (i = 0 ; i < num_umr_blocks ; i++) {
+		u8 nic_id, umr_block_id;
+
+		nic_id = i / NUM_OF_USER_NIC_UMR_BLOCKS;
+		umr_block_id = i % NUM_OF_USER_NIC_UMR_BLOCKS;
+
+		blocks[umr_start_idx + i].address =
+			mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE +
+			(nic_id / NIC_NUMBER_OF_QM_PER_MACRO) * NIC_OFFSET +
+			(nic_id % NIC_NUMBER_OF_QM_PER_MACRO) * NIC_QM_OFFSET +
+			umr_block_id * NIC_UMR_OFFSET;
+		blocks[umr_start_idx + i].size = HL_BLOCK_SIZE;
+	}
+
+	/* Expose decoder HW configuration block to user */
+	gaudi2_user_mapped_dec_init(gaudi2, USR_MAPPED_BLK_DEC_START_IDX);
+
+	for (i = 1; i < NUM_OF_DCORES; ++i) {
+		blocks[USR_MAPPED_BLK_SM_START_IDX + 2 * (i - 1)].size = SM_OBJS_BLOCK_SIZE;
+		blocks[USR_MAPPED_BLK_SM_START_IDX + 2 * (i - 1) + 1].size = HL_BLOCK_SIZE;
+
+		blocks[USR_MAPPED_BLK_SM_START_IDX + 2 * (i - 1)].address =
+						mmDCORE0_SYNC_MNGR_OBJS_BASE + i * DCORE_OFFSET;
+
+		blocks[USR_MAPPED_BLK_SM_START_IDX + 2 * (i - 1) + 1].address =
+						mmDCORE0_SYNC_MNGR_GLBL_BASE + i * DCORE_OFFSET;
+	}
+}
+
+static int gaudi2_alloc_cpu_accessible_dma_mem(struct hl_device *hdev)
+{
+	dma_addr_t dma_addr_arr[GAUDI2_ALLOC_CPU_MEM_RETRY_CNT] = {}, end_addr;
+	void *virt_addr_arr[GAUDI2_ALLOC_CPU_MEM_RETRY_CNT] = {};
+	int i, j, rc = 0;
+
+	/* The device ARC works with 32-bits addresses, and because there is a single HW register
+	 * that holds the extension bits (49..28), these bits must be identical in all the allocated
+	 * range.
+	 */
+
+	for (i = 0 ; i < GAUDI2_ALLOC_CPU_MEM_RETRY_CNT ; i++) {
+		virt_addr_arr[i] = hl_asic_dma_alloc_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE,
+							&dma_addr_arr[i], GFP_KERNEL | __GFP_ZERO);
+		if (!virt_addr_arr[i]) {
+			rc = -ENOMEM;
+			goto free_dma_mem_arr;
+		}
+
+		end_addr = dma_addr_arr[i] + HL_CPU_ACCESSIBLE_MEM_SIZE - 1;
+		if (GAUDI2_ARC_PCI_MSB_ADDR(dma_addr_arr[i]) == GAUDI2_ARC_PCI_MSB_ADDR(end_addr))
+			break;
+	}
+
+	if (i == GAUDI2_ALLOC_CPU_MEM_RETRY_CNT) {
+		dev_err(hdev->dev,
+			"MSB of ARC accessible DMA memory are not identical in all range\n");
+		rc = -EFAULT;
+		goto free_dma_mem_arr;
+	}
+
+	hdev->cpu_accessible_dma_mem = virt_addr_arr[i];
+	hdev->cpu_accessible_dma_address = dma_addr_arr[i];
+
+free_dma_mem_arr:
+	for (j = 0 ; j < i ; j++)
+		hl_asic_dma_free_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE, virt_addr_arr[j],
+						dma_addr_arr[j]);
+
+	return rc;
+}
+
+static void gaudi2_set_pci_memory_regions(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct pci_mem_region *region;
+
+	/* CFG */
+	region = &hdev->pci_mem_region[PCI_REGION_CFG];
+	region->region_base = CFG_BASE;
+	region->region_size = CFG_SIZE;
+	region->offset_in_bar = CFG_BASE - STM_FLASH_BASE_ADDR;
+	region->bar_size = CFG_BAR_SIZE;
+	region->bar_id = SRAM_CFG_BAR_ID;
+	region->used = 1;
+
+	/* SRAM */
+	region = &hdev->pci_mem_region[PCI_REGION_SRAM];
+	region->region_base = SRAM_BASE_ADDR;
+	region->region_size = SRAM_SIZE;
+	region->offset_in_bar = CFG_REGION_SIZE + BAR0_RSRVD_SIZE;
+	region->bar_size = CFG_BAR_SIZE;
+	region->bar_id = SRAM_CFG_BAR_ID;
+	region->used = 1;
+
+	/* DRAM */
+	region = &hdev->pci_mem_region[PCI_REGION_DRAM];
+	region->region_base = DRAM_PHYS_BASE;
+	region->region_size = hdev->asic_prop.dram_size;
+	region->offset_in_bar = 0;
+	region->bar_size = prop->dram_pci_bar_size;
+	region->bar_id = DRAM_BAR_ID;
+	region->used = 1;
+}
+
+static void gaudi2_user_interrupt_setup(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	int i, j, k;
+
+	/* Initialize TPC interrupt */
+	HL_USR_INTR_STRUCT_INIT(hdev->tpc_interrupt, hdev, 0, HL_USR_INTERRUPT_TPC);
+
+	/* Initialize unexpected error interrupt */
+	HL_USR_INTR_STRUCT_INIT(hdev->unexpected_error_interrupt, hdev, 0,
+						HL_USR_INTERRUPT_UNEXPECTED);
+
+	/* Initialize common user CQ interrupt */
+	HL_USR_INTR_STRUCT_INIT(hdev->common_user_cq_interrupt, hdev,
+				HL_COMMON_USER_CQ_INTERRUPT_ID, HL_USR_INTERRUPT_CQ);
+
+	/* Initialize common decoder interrupt */
+	HL_USR_INTR_STRUCT_INIT(hdev->common_decoder_interrupt, hdev,
+				HL_COMMON_DEC_INTERRUPT_ID, HL_USR_INTERRUPT_DECODER);
+
+	/* User interrupts structure holds both decoder and user interrupts from various engines.
+	 * We first initialize the decoder interrupts and then we add the user interrupts.
+	 * The only limitation is that the last decoder interrupt id must be smaller
+	 * then GAUDI2_IRQ_NUM_USER_FIRST. This is checked at compilation time.
+	 */
+
+	/* Initialize decoder interrupts, expose only normal interrupts,
+	 * error interrupts to be handled by driver
+	 */
+	for (i = GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM, j = 0 ; i <= GAUDI2_IRQ_NUM_SHARED_DEC1_NRM;
+										i += 2, j++)
+		HL_USR_INTR_STRUCT_INIT(hdev->user_interrupt[j], hdev, i,
+						HL_USR_INTERRUPT_DECODER);
+
+	for (i = GAUDI2_IRQ_NUM_USER_FIRST, k = 0 ; k < prop->user_interrupt_count; i++, j++, k++)
+		HL_USR_INTR_STRUCT_INIT(hdev->user_interrupt[j], hdev, i, HL_USR_INTERRUPT_CQ);
+}
+
+static inline int gaudi2_get_non_zero_random_int(void)
+{
+	int rand = get_random_u32();
+
+	return rand ? rand : 1;
+}
+
+static void gaudi2_special_blocks_free(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct hl_skip_blocks_cfg *skip_special_blocks_cfg =
+			&prop->skip_special_blocks_cfg;
+
+	kfree(prop->special_blocks);
+	kfree(skip_special_blocks_cfg->block_types);
+	kfree(skip_special_blocks_cfg->block_ranges);
+}
+
+static void gaudi2_special_blocks_iterator_free(struct hl_device *hdev)
+{
+	gaudi2_special_blocks_free(hdev);
+}
+
+static bool gaudi2_special_block_skip(struct hl_device *hdev,
+		struct hl_special_blocks_cfg *special_blocks_cfg,
+		u32 blk_idx, u32 major, u32 minor, u32 sub_minor)
+{
+	return false;
+}
+
+static int gaudi2_special_blocks_config(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	int i, rc;
+
+	/* Configure Special blocks */
+	prop->glbl_err_max_cause_num = GAUDI2_GLBL_ERR_MAX_CAUSE_NUM;
+	prop->num_of_special_blocks = ARRAY_SIZE(gaudi2_special_blocks);
+	prop->special_blocks = kmalloc_array(prop->num_of_special_blocks,
+			sizeof(*prop->special_blocks), GFP_KERNEL);
+	if (!prop->special_blocks)
+		return -ENOMEM;
+
+	for (i = 0 ; i < prop->num_of_special_blocks ; i++)
+		memcpy(&prop->special_blocks[i], &gaudi2_special_blocks[i],
+				sizeof(*prop->special_blocks));
+
+	/* Configure when to skip Special blocks */
+	memset(&prop->skip_special_blocks_cfg, 0, sizeof(prop->skip_special_blocks_cfg));
+	prop->skip_special_blocks_cfg.skip_block_hook = gaudi2_special_block_skip;
+
+	if (ARRAY_SIZE(gaudi2_iterator_skip_block_types)) {
+		prop->skip_special_blocks_cfg.block_types =
+				kmalloc_array(ARRAY_SIZE(gaudi2_iterator_skip_block_types),
+					sizeof(gaudi2_iterator_skip_block_types[0]), GFP_KERNEL);
+		if (!prop->skip_special_blocks_cfg.block_types) {
+			rc = -ENOMEM;
+			goto free_special_blocks;
+		}
+
+		memcpy(prop->skip_special_blocks_cfg.block_types, gaudi2_iterator_skip_block_types,
+				sizeof(gaudi2_iterator_skip_block_types));
+
+		prop->skip_special_blocks_cfg.block_types_len =
+					ARRAY_SIZE(gaudi2_iterator_skip_block_types);
+	}
+
+	if (ARRAY_SIZE(gaudi2_iterator_skip_block_ranges)) {
+		prop->skip_special_blocks_cfg.block_ranges =
+				kmalloc_array(ARRAY_SIZE(gaudi2_iterator_skip_block_ranges),
+					sizeof(gaudi2_iterator_skip_block_ranges[0]), GFP_KERNEL);
+		if (!prop->skip_special_blocks_cfg.block_ranges) {
+			rc = -ENOMEM;
+			goto free_skip_special_blocks_types;
+		}
+
+		for (i = 0 ; i < ARRAY_SIZE(gaudi2_iterator_skip_block_ranges) ; i++)
+			memcpy(&prop->skip_special_blocks_cfg.block_ranges[i],
+					&gaudi2_iterator_skip_block_ranges[i],
+					sizeof(struct range));
+
+		prop->skip_special_blocks_cfg.block_ranges_len =
+					ARRAY_SIZE(gaudi2_iterator_skip_block_ranges);
+	}
+
+	return 0;
+
+free_skip_special_blocks_types:
+	kfree(prop->skip_special_blocks_cfg.block_types);
+free_special_blocks:
+	kfree(prop->special_blocks);
+
+	return rc;
+}
+
+static int gaudi2_special_blocks_iterator_config(struct hl_device *hdev)
+{
+	return gaudi2_special_blocks_config(hdev);
+}
+
+static void gaudi2_test_queues_msgs_free(struct hl_device *hdev)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	struct gaudi2_queues_test_info *msg_info = gaudi2->queues_test_info;
+	int i;
+
+	for (i = 0 ; i < GAUDI2_NUM_TESTED_QS ; i++) {
+		/* bail-out if this is an allocation failure point */
+		if (!msg_info[i].kern_addr)
+			break;
+
+		hl_asic_dma_pool_free(hdev, msg_info[i].kern_addr, msg_info[i].dma_addr);
+		msg_info[i].kern_addr = NULL;
+	}
+}
+
+static int gaudi2_test_queues_msgs_alloc(struct hl_device *hdev)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	struct gaudi2_queues_test_info *msg_info = gaudi2->queues_test_info;
+	int i, rc;
+
+	/* allocate a message-short buf for each Q we intend to test */
+	for (i = 0 ; i < GAUDI2_NUM_TESTED_QS ; i++) {
+		msg_info[i].kern_addr =
+			(void *)hl_asic_dma_pool_zalloc(hdev, sizeof(struct packet_msg_short),
+							GFP_KERNEL, &msg_info[i].dma_addr);
+		if (!msg_info[i].kern_addr) {
+			dev_err(hdev->dev,
+				"Failed to allocate dma memory for H/W queue %d testing\n", i);
+			rc = -ENOMEM;
+			goto err_exit;
+		}
+	}
+
+	return 0;
+
+err_exit:
+	gaudi2_test_queues_msgs_free(hdev);
+	return rc;
+}
+
+static int gaudi2_sw_init(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct gaudi2_device *gaudi2;
+	int i, rc;
+
+	/* Allocate device structure */
+	gaudi2 = kzalloc(sizeof(*gaudi2), GFP_KERNEL);
+	if (!gaudi2)
+		return -ENOMEM;
+
+	for (i = 0 ; i < ARRAY_SIZE(gaudi2_irq_map_table) ; i++) {
+		if (gaudi2_irq_map_table[i].msg || !gaudi2_irq_map_table[i].valid)
+			continue;
+
+		if (gaudi2->num_of_valid_hw_events == GAUDI2_EVENT_SIZE) {
+			dev_err(hdev->dev, "H/W events array exceeds the limit of %u events\n",
+				GAUDI2_EVENT_SIZE);
+			rc = -EINVAL;
+			goto free_gaudi2_device;
+		}
+
+		gaudi2->hw_events[gaudi2->num_of_valid_hw_events++] = gaudi2_irq_map_table[i].fc_id;
+	}
+
+	for (i = 0 ; i < MME_NUM_OF_LFSR_SEEDS ; i++)
+		gaudi2->lfsr_rand_seeds[i] = gaudi2_get_non_zero_random_int();
+
+	gaudi2->cpucp_info_get = gaudi2_cpucp_info_get;
+
+	hdev->asic_specific = gaudi2;
+
+	/* Create DMA pool for small allocations.
+	 * Use DEVICE_CACHE_LINE_SIZE for alignment since the NIC memory-mapped
+	 * PI/CI registers allocated from this pool have this restriction
+	 */
+	hdev->dma_pool = dma_pool_create(dev_name(hdev->dev), &hdev->pdev->dev,
+					GAUDI2_DMA_POOL_BLK_SIZE, DEVICE_CACHE_LINE_SIZE, 0);
+	if (!hdev->dma_pool) {
+		dev_err(hdev->dev, "failed to create DMA pool\n");
+		rc = -ENOMEM;
+		goto free_gaudi2_device;
+	}
+
+	rc = gaudi2_alloc_cpu_accessible_dma_mem(hdev);
+	if (rc)
+		goto free_dma_pool;
+
+	hdev->cpu_accessible_dma_pool = gen_pool_create(ilog2(32), -1);
+	if (!hdev->cpu_accessible_dma_pool) {
+		dev_err(hdev->dev, "Failed to create CPU accessible DMA pool\n");
+		rc = -ENOMEM;
+		goto free_cpu_dma_mem;
+	}
+
+	rc = gen_pool_add(hdev->cpu_accessible_dma_pool, (uintptr_t) hdev->cpu_accessible_dma_mem,
+				HL_CPU_ACCESSIBLE_MEM_SIZE, -1);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to add memory to CPU accessible DMA pool\n");
+		rc = -EFAULT;
+		goto free_cpu_accessible_dma_pool;
+	}
+
+	gaudi2->virt_msix_db_cpu_addr = hl_cpu_accessible_dma_pool_alloc(hdev, prop->pmmu.page_size,
+								&gaudi2->virt_msix_db_dma_addr);
+	if (!gaudi2->virt_msix_db_cpu_addr) {
+		dev_err(hdev->dev, "Failed to allocate DMA memory for virtual MSI-X doorbell\n");
+		rc = -ENOMEM;
+		goto free_cpu_accessible_dma_pool;
+	}
+
+	spin_lock_init(&gaudi2->hw_queues_lock);
+
+	gaudi2->scratchpad_bus_address = prop->mmu_pgt_addr + HMMU_PAGE_TABLES_SIZE + EDMA_PQS_SIZE;
+
+	gaudi2_user_mapped_blocks_init(hdev);
+
+	/* Initialize user interrupts */
+	gaudi2_user_interrupt_setup(hdev);
+
+	hdev->supports_coresight = true;
+	hdev->supports_sync_stream = true;
+	hdev->supports_cb_mapping = true;
+	hdev->supports_wait_for_multi_cs = false;
+
+	prop->supports_compute_reset = true;
+
+	/* Event queue sanity check added in FW version 1.11 */
+	if (hl_fw_version_cmp(hdev, 1, 11, 0) < 0)
+		hdev->event_queue.check_eqe_index = false;
+	else
+		hdev->event_queue.check_eqe_index = true;
+
+	hdev->asic_funcs->set_pci_memory_regions(hdev);
+
+	rc = gaudi2_special_blocks_iterator_config(hdev);
+	if (rc)
+		goto free_virt_msix_db_mem;
+
+	rc = gaudi2_test_queues_msgs_alloc(hdev);
+	if (rc)
+		goto special_blocks_free;
+
+	hdev->heartbeat_debug_info.cpu_queue_id = GAUDI2_QUEUE_ID_CPU_PQ;
+
+	return 0;
+
+special_blocks_free:
+	gaudi2_special_blocks_iterator_free(hdev);
+free_virt_msix_db_mem:
+	hl_cpu_accessible_dma_pool_free(hdev, prop->pmmu.page_size, gaudi2->virt_msix_db_cpu_addr);
+free_cpu_accessible_dma_pool:
+	gen_pool_destroy(hdev->cpu_accessible_dma_pool);
+free_cpu_dma_mem:
+	hl_asic_dma_free_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE, hdev->cpu_accessible_dma_mem,
+					hdev->cpu_accessible_dma_address);
+free_dma_pool:
+	dma_pool_destroy(hdev->dma_pool);
+free_gaudi2_device:
+	kfree(gaudi2);
+	return rc;
+}
+
+static int gaudi2_sw_fini(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+
+	gaudi2_test_queues_msgs_free(hdev);
+
+	gaudi2_special_blocks_iterator_free(hdev);
+
+	hl_cpu_accessible_dma_pool_free(hdev, prop->pmmu.page_size, gaudi2->virt_msix_db_cpu_addr);
+
+	gen_pool_destroy(hdev->cpu_accessible_dma_pool);
+
+	hl_asic_dma_free_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE, hdev->cpu_accessible_dma_mem,
+						hdev->cpu_accessible_dma_address);
+
+	dma_pool_destroy(hdev->dma_pool);
+
+	kfree(gaudi2);
+
+	return 0;
+}
+
+static void gaudi2_stop_qman_common(struct hl_device *hdev, u32 reg_base)
+{
+	WREG32(reg_base + QM_GLBL_CFG1_OFFSET, QM_GLBL_CFG1_PQF_STOP |
+						QM_GLBL_CFG1_CQF_STOP |
+						QM_GLBL_CFG1_CP_STOP);
+
+	/* stop also the ARC */
+	WREG32(reg_base + QM_GLBL_CFG2_OFFSET, QM_GLBL_CFG2_ARC_CQF_STOP);
+}
+
+static void gaudi2_flush_qman_common(struct hl_device *hdev, u32 reg_base)
+{
+	WREG32(reg_base + QM_GLBL_CFG1_OFFSET, QM_GLBL_CFG1_PQF_FLUSH |
+						QM_GLBL_CFG1_CQF_FLUSH |
+						QM_GLBL_CFG1_CP_FLUSH);
+}
+
+static void gaudi2_flush_qman_arc_common(struct hl_device *hdev, u32 reg_base)
+{
+	WREG32(reg_base + QM_GLBL_CFG2_OFFSET, QM_GLBL_CFG2_ARC_CQF_FLUSH);
+}
+
+/**
+ * gaudi2_clear_qm_fence_counters_common - clear QM's fence counters
+ *
+ * @hdev: pointer to the habanalabs device structure
+ * @queue_id: queue to clear fence counters to
+ * @skip_fence: if true set maximum fence value to all fence counters to avoid
+ *              getting stuck on any fence value. otherwise set all fence
+ *              counters to 0 (standard clear of fence counters)
+ */
+static void gaudi2_clear_qm_fence_counters_common(struct hl_device *hdev, u32 queue_id,
+						bool skip_fence)
+{
+	u32 size, reg_base;
+	u32 addr, val;
+
+	reg_base = gaudi2_qm_blocks_bases[queue_id];
+
+	addr = reg_base + QM_CP_FENCE0_CNT_0_OFFSET;
+	size = mmPDMA0_QM_CP_BARRIER_CFG - mmPDMA0_QM_CP_FENCE0_CNT_0;
+
+	/*
+	 * in case we want to make sure that QM that is stuck on a fence will
+	 * be released we should set the fence counter to a higher value that
+	 * the value the QM waiting for. to comply with any fence counter of
+	 * any value we set maximum fence value to all counters
+	 */
+	val = skip_fence ? U32_MAX : 0;
+	gaudi2_memset_device_lbw(hdev, addr, size, val);
+}
+
+static void gaudi2_qman_manual_flush_common(struct hl_device *hdev, u32 queue_id)
+{
+	u32 reg_base = gaudi2_qm_blocks_bases[queue_id];
+
+	gaudi2_clear_qm_fence_counters_common(hdev, queue_id, true);
+	gaudi2_flush_qman_common(hdev, reg_base);
+	gaudi2_flush_qman_arc_common(hdev, reg_base);
+}
+
+static void gaudi2_stop_dma_qmans(struct hl_device *hdev)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	int dcore, inst;
+
+	if (!(gaudi2->hw_cap_initialized & HW_CAP_PDMA_MASK))
+		goto stop_edma_qmans;
+
+	/* Stop CPs of PDMA QMANs */
+	gaudi2_stop_qman_common(hdev, mmPDMA0_QM_BASE);
+	gaudi2_stop_qman_common(hdev, mmPDMA1_QM_BASE);
+
+stop_edma_qmans:
+	if (!(gaudi2->hw_cap_initialized & HW_CAP_EDMA_MASK))
+		return;
+
+	for (dcore = 0 ; dcore < NUM_OF_DCORES ; dcore++) {
+		for (inst = 0 ; inst < NUM_OF_EDMA_PER_DCORE ; inst++) {
+			u8 seq = dcore * NUM_OF_EDMA_PER_DCORE + inst;
+			u32 qm_base;
+
+			if (!(gaudi2->hw_cap_initialized & BIT_ULL(HW_CAP_EDMA_SHIFT + seq)))
+				continue;
+
+			qm_base = mmDCORE0_EDMA0_QM_BASE + dcore * DCORE_OFFSET +
+					inst * DCORE_EDMA_OFFSET;
+
+			/* Stop CPs of EDMA QMANs */
+			gaudi2_stop_qman_common(hdev, qm_base);
+		}
+	}
+}
+
+static void gaudi2_stop_mme_qmans(struct hl_device *hdev)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	u32 offset, i;
+
+	offset = mmDCORE1_MME_QM_BASE - mmDCORE0_MME_QM_BASE;
+
+	for (i = 0 ; i < NUM_OF_DCORES ; i++) {
+		if (!(gaudi2->hw_cap_initialized & BIT_ULL(HW_CAP_MME_SHIFT + i)))
+			continue;
+
+		gaudi2_stop_qman_common(hdev, mmDCORE0_MME_QM_BASE + (i * offset));
+	}
+}
+
+static void gaudi2_stop_tpc_qmans(struct hl_device *hdev)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	u32 reg_base;
+	int i;
+
+	if (!(gaudi2->tpc_hw_cap_initialized & HW_CAP_TPC_MASK))
+		return;
+
+	for (i = 0 ; i < TPC_ID_SIZE ; i++) {
+		if (!(gaudi2->tpc_hw_cap_initialized & BIT_ULL(HW_CAP_TPC_SHIFT + i)))
+			continue;
+
+		reg_base = gaudi2_qm_blocks_bases[gaudi2_tpc_id_to_queue_id[i]];
+		gaudi2_stop_qman_common(hdev, reg_base);
+	}
+}
+
+static void gaudi2_stop_rot_qmans(struct hl_device *hdev)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	u32 reg_base;
+	int i;
+
+	if (!(gaudi2->hw_cap_initialized & HW_CAP_ROT_MASK))
+		return;
+
+	for (i = 0 ; i < ROTATOR_ID_SIZE ; i++) {
+		if (!(gaudi2->hw_cap_initialized & BIT_ULL(HW_CAP_ROT_SHIFT + i)))
+			continue;
+
+		reg_base = gaudi2_qm_blocks_bases[gaudi2_rot_id_to_queue_id[i]];
+		gaudi2_stop_qman_common(hdev, reg_base);
+	}
+}
+
+static void gaudi2_stop_nic_qmans(struct hl_device *hdev)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	u32 reg_base, queue_id;
+	int i;
+
+	if (!(gaudi2->nic_hw_cap_initialized & HW_CAP_NIC_MASK))
+		return;
+
+	queue_id = GAUDI2_QUEUE_ID_NIC_0_0;
+
+	for (i = 0 ; i < NIC_NUMBER_OF_ENGINES ; i++, queue_id += NUM_OF_PQ_PER_QMAN) {
+		if (!(hdev->nic_ports_mask & BIT(i)))
+			continue;
+
+		reg_base = gaudi2_qm_blocks_bases[queue_id];
+		gaudi2_stop_qman_common(hdev, reg_base);
+	}
+}
+
+static void gaudi2_stall_dma_common(struct hl_device *hdev, u32 reg_base)
+{
+	u32 reg_val;
+
+	reg_val = FIELD_PREP(PDMA0_CORE_CFG_1_HALT_MASK, 0x1);
+	WREG32(reg_base + DMA_CORE_CFG_1_OFFSET, reg_val);
+}
+
+static void gaudi2_dma_stall(struct hl_device *hdev)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	int dcore, inst;
+
+	if (!(gaudi2->hw_cap_initialized & HW_CAP_PDMA_MASK))
+		goto stall_edma;
+
+	gaudi2_stall_dma_common(hdev, mmPDMA0_CORE_BASE);
+	gaudi2_stall_dma_common(hdev, mmPDMA1_CORE_BASE);
+
+stall_edma:
+	if (!(gaudi2->hw_cap_initialized & HW_CAP_EDMA_MASK))
+		return;
+
+	for (dcore = 0 ; dcore < NUM_OF_DCORES ; dcore++) {
+		for (inst = 0 ; inst < NUM_OF_EDMA_PER_DCORE ; inst++) {
+			u8 seq = dcore * NUM_OF_EDMA_PER_DCORE + inst;
+			u32 core_base;
+
+			if (!(gaudi2->hw_cap_initialized & BIT_ULL(HW_CAP_EDMA_SHIFT + seq)))
+				continue;
+
+			core_base = mmDCORE0_EDMA0_CORE_BASE + dcore * DCORE_OFFSET +
+					inst * DCORE_EDMA_OFFSET;
+
+			/* Stall CPs of EDMA QMANs */
+			gaudi2_stall_dma_common(hdev, core_base);
+		}
+	}
+}
+
+static void gaudi2_mme_stall(struct hl_device *hdev)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	u32 offset, i;
+
+	offset = mmDCORE1_MME_CTRL_LO_QM_STALL - mmDCORE0_MME_CTRL_LO_QM_STALL;
+
+	for (i = 0 ; i < NUM_OF_DCORES ; i++)
+		if (gaudi2->hw_cap_initialized & BIT_ULL(HW_CAP_MME_SHIFT + i))
+			WREG32(mmDCORE0_MME_CTRL_LO_QM_STALL + (i * offset), 1);
+}
+
+static void gaudi2_tpc_stall(struct hl_device *hdev)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	u32 reg_base;
+	int i;
+
+	if (!(gaudi2->tpc_hw_cap_initialized & HW_CAP_TPC_MASK))
+		return;
+
+	for (i = 0 ; i < TPC_ID_SIZE ; i++) {
+		if (!(gaudi2->tpc_hw_cap_initialized & BIT_ULL(HW_CAP_TPC_SHIFT + i)))
+			continue;
+
+		reg_base = gaudi2_tpc_cfg_blocks_bases[i];
+		WREG32(reg_base + TPC_CFG_STALL_OFFSET, 1);
+	}
+}
+
+static void gaudi2_rotator_stall(struct hl_device *hdev)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	u32 reg_val;
+	int i;
+
+	if (!(gaudi2->hw_cap_initialized & HW_CAP_ROT_MASK))
+		return;
+
+	reg_val = FIELD_PREP(ROT_MSS_HALT_WBC_MASK, 0x1) |
+			FIELD_PREP(ROT_MSS_HALT_RSB_MASK, 0x1) |
+			FIELD_PREP(ROT_MSS_HALT_MRSB_MASK, 0x1);
+
+	for (i = 0 ; i < ROTATOR_ID_SIZE ; i++) {
+		if (!(gaudi2->hw_cap_initialized & BIT_ULL(HW_CAP_ROT_SHIFT + i)))
+			continue;
+
+		WREG32(mmROT0_MSS_HALT + i * ROT_OFFSET, reg_val);
+	}
+}
+
+static void gaudi2_disable_qman_common(struct hl_device *hdev, u32 reg_base)
+{
+	WREG32(reg_base + QM_GLBL_CFG0_OFFSET, 0);
+}
+
+static void gaudi2_disable_dma_qmans(struct hl_device *hdev)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	int dcore, inst;
+
+	if (!(gaudi2->hw_cap_initialized & HW_CAP_PDMA_MASK))
+		goto stop_edma_qmans;
+
+	gaudi2_disable_qman_common(hdev, mmPDMA0_QM_BASE);
+	gaudi2_disable_qman_common(hdev, mmPDMA1_QM_BASE);
+
+stop_edma_qmans:
+	if (!(gaudi2->hw_cap_initialized & HW_CAP_EDMA_MASK))
+		return;
+
+	for (dcore = 0 ; dcore < NUM_OF_DCORES ; dcore++) {
+		for (inst = 0 ; inst < NUM_OF_EDMA_PER_DCORE ; inst++) {
+			u8 seq = dcore * NUM_OF_EDMA_PER_DCORE + inst;
+			u32 qm_base;
+
+			if (!(gaudi2->hw_cap_initialized & BIT_ULL(HW_CAP_EDMA_SHIFT + seq)))
+				continue;
+
+			qm_base = mmDCORE0_EDMA0_QM_BASE + dcore * DCORE_OFFSET +
+					inst * DCORE_EDMA_OFFSET;
+
+			/* Disable CPs of EDMA QMANs */
+			gaudi2_disable_qman_common(hdev, qm_base);
+		}
+	}
+}
+
+static void gaudi2_disable_mme_qmans(struct hl_device *hdev)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	u32 offset, i;
+
+	offset = mmDCORE1_MME_QM_BASE - mmDCORE0_MME_QM_BASE;
+
+	for (i = 0 ; i < NUM_OF_DCORES ; i++)
+		if (gaudi2->hw_cap_initialized & BIT_ULL(HW_CAP_MME_SHIFT + i))
+			gaudi2_disable_qman_common(hdev, mmDCORE0_MME_QM_BASE + (i * offset));
+}
+
+static void gaudi2_disable_tpc_qmans(struct hl_device *hdev)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	u32 reg_base;
+	int i;
+
+	if (!(gaudi2->tpc_hw_cap_initialized & HW_CAP_TPC_MASK))
+		return;
+
+	for (i = 0 ; i < TPC_ID_SIZE ; i++) {
+		if (!(gaudi2->tpc_hw_cap_initialized & BIT_ULL(HW_CAP_TPC_SHIFT + i)))
+			continue;
+
+		reg_base = gaudi2_qm_blocks_bases[gaudi2_tpc_id_to_queue_id[i]];
+		gaudi2_disable_qman_common(hdev, reg_base);
+	}
+}
+
+static void gaudi2_disable_rot_qmans(struct hl_device *hdev)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	u32 reg_base;
+	int i;
+
+	if (!(gaudi2->hw_cap_initialized & HW_CAP_ROT_MASK))
+		return;
+
+	for (i = 0 ; i < ROTATOR_ID_SIZE ; i++) {
+		if (!(gaudi2->hw_cap_initialized & BIT_ULL(HW_CAP_ROT_SHIFT + i)))
+			continue;
+
+		reg_base = gaudi2_qm_blocks_bases[gaudi2_rot_id_to_queue_id[i]];
+		gaudi2_disable_qman_common(hdev, reg_base);
+	}
+}
+
+static void gaudi2_disable_nic_qmans(struct hl_device *hdev)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	u32 reg_base, queue_id;
+	int i;
+
+	if (!(gaudi2->nic_hw_cap_initialized & HW_CAP_NIC_MASK))
+		return;
+
+	queue_id = GAUDI2_QUEUE_ID_NIC_0_0;
+
+	for (i = 0 ; i < NIC_NUMBER_OF_ENGINES ; i++, queue_id += NUM_OF_PQ_PER_QMAN) {
+		if (!(hdev->nic_ports_mask & BIT(i)))
+			continue;
+
+		reg_base = gaudi2_qm_blocks_bases[queue_id];
+		gaudi2_disable_qman_common(hdev, reg_base);
+	}
+}
+
+static void gaudi2_enable_timestamp(struct hl_device *hdev)
+{
+	/* Disable the timestamp counter */
+	WREG32(mmPSOC_TIMESTAMP_BASE, 0);
+
+	/* Zero the lower/upper parts of the 64-bit counter */
+	WREG32(mmPSOC_TIMESTAMP_BASE + 0xC, 0);
+	WREG32(mmPSOC_TIMESTAMP_BASE + 0x8, 0);
+
+	/* Enable the counter */
+	WREG32(mmPSOC_TIMESTAMP_BASE, 1);
+}
+
+static void gaudi2_disable_timestamp(struct hl_device *hdev)
+{
+	/* Disable the timestamp counter */
+	WREG32(mmPSOC_TIMESTAMP_BASE, 0);
+}
+
+static const char *gaudi2_irq_name(u16 irq_number)
+{
+	switch (irq_number) {
+	case GAUDI2_IRQ_NUM_EVENT_QUEUE:
+		return "gaudi2 cpu eq";
+	case GAUDI2_IRQ_NUM_COMPLETION:
+		return "gaudi2 completion";
+	case GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM ... GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM:
+		return gaudi2_vdec_irq_name[irq_number - GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM];
+	case GAUDI2_IRQ_NUM_TPC_ASSERT:
+		return "gaudi2 tpc assert";
+	case GAUDI2_IRQ_NUM_UNEXPECTED_ERROR:
+		return "gaudi2 unexpected error";
+	case GAUDI2_IRQ_NUM_USER_FIRST ... GAUDI2_IRQ_NUM_USER_LAST:
+		return "gaudi2 user completion";
+	case GAUDI2_IRQ_NUM_EQ_ERROR:
+		return "gaudi2 eq error";
+	default:
+		return "invalid";
+	}
+}
+
+static void gaudi2_dec_disable_msix(struct hl_device *hdev, u32 max_irq_num)
+{
+	int i, irq, relative_idx;
+	struct hl_dec *dec;
+
+	for (i = GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM ; i < max_irq_num ; i++) {
+		irq = pci_irq_vector(hdev->pdev, i);
+		relative_idx = i - GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM;
+
+		dec = hdev->dec + relative_idx / 2;
+
+		/* We pass different structures depending on the irq handler. For the abnormal
+		 * interrupt we pass hl_dec and for the regular interrupt we pass the relevant
+		 * user_interrupt entry
+		 */
+		free_irq(irq, ((relative_idx % 2) ?
+				(void *) dec :
+				(void *) &hdev->user_interrupt[dec->core_id]));
+	}
+}
+
+static int gaudi2_dec_enable_msix(struct hl_device *hdev)
+{
+	int rc, i, irq_init_cnt, irq, relative_idx;
+	struct hl_dec *dec;
+
+	for (i = GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM, irq_init_cnt = 0;
+			i <= GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM;
+			i++, irq_init_cnt++) {
+
+		irq = pci_irq_vector(hdev->pdev, i);
+		relative_idx = i - GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM;
+
+		/* We pass different structures depending on the irq handler. For the abnormal
+		 * interrupt we pass hl_dec and for the regular interrupt we pass the relevant
+		 * user_interrupt entry
+		 *
+		 * TODO: change the dec abnrm to threaded irq
+		 */
+
+		dec = hdev->dec + relative_idx / 2;
+		if (relative_idx % 2) {
+			rc = request_irq(irq, hl_irq_handler_dec_abnrm, 0,
+						gaudi2_irq_name(i), (void *) dec);
+		} else {
+			rc = request_irq(irq, hl_irq_user_interrupt_handler, 0, gaudi2_irq_name(i),
+					(void *) &hdev->user_interrupt[dec->core_id]);
+		}
+
+		if (rc) {
+			dev_err(hdev->dev, "Failed to request IRQ %d", irq);
+			goto free_dec_irqs;
+		}
+	}
+
+	return 0;
+
+free_dec_irqs:
+	gaudi2_dec_disable_msix(hdev, (GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM + irq_init_cnt));
+	return rc;
+}
+
+static int gaudi2_enable_msix(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	int rc, irq, i, j, user_irq_init_cnt;
+	struct hl_cq *cq;
+
+	if (gaudi2->hw_cap_initialized & HW_CAP_MSIX)
+		return 0;
+
+	hl_init_cpu_for_irq(hdev);
+
+	rc = pci_alloc_irq_vectors(hdev->pdev, GAUDI2_MSIX_ENTRIES, GAUDI2_MSIX_ENTRIES,
+					PCI_IRQ_MSIX);
+	if (rc < 0) {
+		dev_err(hdev->dev, "MSI-X: Failed to enable support -- %d/%d\n",
+			GAUDI2_MSIX_ENTRIES, rc);
+		return rc;
+	}
+
+	irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_COMPLETION);
+	cq = &hdev->completion_queue[GAUDI2_RESERVED_CQ_CS_COMPLETION];
+	rc = request_irq(irq, hl_irq_handler_cq, 0, gaudi2_irq_name(GAUDI2_IRQ_NUM_COMPLETION), cq);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to request IRQ %d", irq);
+		goto free_irq_vectors;
+	}
+
+	irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_EVENT_QUEUE);
+	rc = request_irq(irq, hl_irq_handler_eq, 0, gaudi2_irq_name(GAUDI2_IRQ_NUM_EVENT_QUEUE),
+			&hdev->event_queue);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to request IRQ %d", irq);
+		goto free_completion_irq;
+	}
+
+	rc = gaudi2_dec_enable_msix(hdev);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to enable decoder IRQ");
+		goto free_event_irq;
+	}
+
+	irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_TPC_ASSERT);
+	rc = request_threaded_irq(irq, NULL, hl_irq_user_interrupt_thread_handler, IRQF_ONESHOT,
+					gaudi2_irq_name(GAUDI2_IRQ_NUM_TPC_ASSERT),
+					&hdev->tpc_interrupt);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to request IRQ %d", irq);
+		goto free_dec_irq;
+	}
+
+	irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_UNEXPECTED_ERROR);
+	rc = request_threaded_irq(irq, NULL, hl_irq_user_interrupt_thread_handler, IRQF_ONESHOT,
+					gaudi2_irq_name(GAUDI2_IRQ_NUM_UNEXPECTED_ERROR),
+					&hdev->unexpected_error_interrupt);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to request IRQ %d", irq);
+		goto free_tpc_irq;
+	}
+
+	for (i = GAUDI2_IRQ_NUM_USER_FIRST, j = prop->user_dec_intr_count, user_irq_init_cnt = 0;
+			user_irq_init_cnt < prop->user_interrupt_count;
+			i++, j++, user_irq_init_cnt++) {
+
+		irq = pci_irq_vector(hdev->pdev, i);
+		hl_set_irq_affinity(hdev, irq);
+		rc = request_irq(irq, hl_irq_user_interrupt_handler, 0, gaudi2_irq_name(i),
+				&hdev->user_interrupt[j]);
+		if (rc) {
+			dev_err(hdev->dev, "Failed to request IRQ %d", irq);
+			goto free_user_irq;
+		}
+	}
+
+	irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_EQ_ERROR);
+	rc = request_threaded_irq(irq, NULL, hl_irq_eq_error_interrupt_thread_handler,
+					IRQF_ONESHOT, gaudi2_irq_name(GAUDI2_IRQ_NUM_EQ_ERROR),
+					hdev);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to request IRQ %d", irq);
+		goto free_user_irq;
+	}
+
+	gaudi2->hw_cap_initialized |= HW_CAP_MSIX;
+
+	return 0;
+
+free_user_irq:
+	for (i = GAUDI2_IRQ_NUM_USER_FIRST, j = prop->user_dec_intr_count;
+			i < GAUDI2_IRQ_NUM_USER_FIRST + user_irq_init_cnt ; i++, j++) {
+
+		irq = pci_irq_vector(hdev->pdev, i);
+		irq_set_affinity_and_hint(irq, NULL);
+		free_irq(irq, &hdev->user_interrupt[j]);
+	}
+	irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_UNEXPECTED_ERROR);
+	free_irq(irq, &hdev->unexpected_error_interrupt);
+free_tpc_irq:
+	irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_TPC_ASSERT);
+	free_irq(irq, &hdev->tpc_interrupt);
+free_dec_irq:
+	gaudi2_dec_disable_msix(hdev, GAUDI2_IRQ_NUM_DEC_LAST + 1);
+free_event_irq:
+	irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_EVENT_QUEUE);
+	free_irq(irq, cq);
+
+free_completion_irq:
+	irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_COMPLETION);
+	free_irq(irq, cq);
+
+free_irq_vectors:
+	pci_free_irq_vectors(hdev->pdev);
+
+	return rc;
+}
+
+static void gaudi2_sync_irqs(struct hl_device *hdev)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	int i, j;
+	int irq;
+
+	if (!(gaudi2->hw_cap_initialized & HW_CAP_MSIX))
+		return;
+
+	/* Wait for all pending IRQs to be finished */
+	synchronize_irq(pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_COMPLETION));
+
+	for (i = GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM ; i <= GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM ; i++) {
+		irq = pci_irq_vector(hdev->pdev, i);
+		synchronize_irq(irq);
+	}
+
+	synchronize_irq(pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_TPC_ASSERT));
+	synchronize_irq(pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_UNEXPECTED_ERROR));
+
+	for (i = GAUDI2_IRQ_NUM_USER_FIRST, j = 0 ; j < hdev->asic_prop.user_interrupt_count;
+										i++, j++) {
+		irq = pci_irq_vector(hdev->pdev, i);
+		synchronize_irq(irq);
+	}
+
+	synchronize_irq(pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_EVENT_QUEUE));
+	synchronize_irq(pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_EQ_ERROR));
+}
+
+static void gaudi2_disable_msix(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	struct hl_cq *cq;
+	int irq, i, j, k;
+
+	if (!(gaudi2->hw_cap_initialized & HW_CAP_MSIX))
+		return;
+
+	gaudi2_sync_irqs(hdev);
+
+	irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_EVENT_QUEUE);
+	free_irq(irq, &hdev->event_queue);
+
+	gaudi2_dec_disable_msix(hdev, GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM + 1);
+
+	irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_TPC_ASSERT);
+	free_irq(irq, &hdev->tpc_interrupt);
+
+	irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_UNEXPECTED_ERROR);
+	free_irq(irq, &hdev->unexpected_error_interrupt);
+
+	for (i = GAUDI2_IRQ_NUM_USER_FIRST, j = prop->user_dec_intr_count, k = 0;
+			k < hdev->asic_prop.user_interrupt_count ; i++, j++, k++) {
+
+		irq = pci_irq_vector(hdev->pdev, i);
+		irq_set_affinity_and_hint(irq, NULL);
+		free_irq(irq, &hdev->user_interrupt[j]);
+	}
+
+	irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_COMPLETION);
+	cq = &hdev->completion_queue[GAUDI2_RESERVED_CQ_CS_COMPLETION];
+	free_irq(irq, cq);
+
+	irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_EQ_ERROR);
+	free_irq(irq, hdev);
+
+	pci_free_irq_vectors(hdev->pdev);
+
+	gaudi2->hw_cap_initialized &= ~HW_CAP_MSIX;
+}
+
+static void gaudi2_stop_dcore_dec(struct hl_device *hdev, int dcore_id)
+{
+	u32 reg_val = FIELD_PREP(DCORE0_VDEC0_BRDG_CTRL_GRACEFUL_STOP_MASK, 0x1);
+	u32 graceful_pend_mask = DCORE0_VDEC0_BRDG_CTRL_GRACEFUL_PEND_MASK;
+	u32 timeout_usec, dec_id, dec_bit, offset, graceful;
+	int rc;
+
+	if (hdev->pldm)
+		timeout_usec = GAUDI2_PLDM_VDEC_TIMEOUT_USEC;
+	else
+		timeout_usec = GAUDI2_VDEC_TIMEOUT_USEC;
+
+	for (dec_id = 0 ; dec_id < NUM_OF_DEC_PER_DCORE ; dec_id++) {
+		dec_bit = dcore_id * NUM_OF_DEC_PER_DCORE + dec_id;
+		if (!(hdev->asic_prop.decoder_enabled_mask & BIT(dec_bit)))
+			continue;
+
+		offset = dcore_id * DCORE_OFFSET + dec_id * DCORE_VDEC_OFFSET;
+
+		WREG32(mmDCORE0_DEC0_CMD_SWREG16 + offset, 0);
+
+		WREG32(mmDCORE0_VDEC0_BRDG_CTRL_GRACEFUL + offset, reg_val);
+
+		/* Wait till all traffic from decoder stops
+		 * before apply core reset.
+		 */
+		rc = hl_poll_timeout(
+				hdev,
+				mmDCORE0_VDEC0_BRDG_CTRL_GRACEFUL + offset,
+				graceful,
+				(graceful & graceful_pend_mask),
+				100,
+				timeout_usec);
+		if (rc)
+			dev_err(hdev->dev,
+				"Failed to stop traffic from DCORE%d Decoder %d\n",
+				dcore_id, dec_id);
+	}
+}
+
+static void gaudi2_stop_pcie_dec(struct hl_device *hdev)
+{
+	u32 reg_val = FIELD_PREP(DCORE0_VDEC0_BRDG_CTRL_GRACEFUL_STOP_MASK, 0x1);
+	u32 graceful_pend_mask = PCIE_VDEC0_BRDG_CTRL_GRACEFUL_PEND_MASK;
+	u32 timeout_usec, dec_id, dec_bit, offset, graceful;
+	int rc;
+
+	if (hdev->pldm)
+		timeout_usec = GAUDI2_PLDM_VDEC_TIMEOUT_USEC;
+	else
+		timeout_usec = GAUDI2_VDEC_TIMEOUT_USEC;
+
+	for (dec_id = 0 ; dec_id < NUM_OF_DEC_PER_DCORE ; dec_id++) {
+		dec_bit = PCIE_DEC_SHIFT + dec_id;
+		if (!(hdev->asic_prop.decoder_enabled_mask & BIT(dec_bit)))
+			continue;
+
+		offset = dec_id * PCIE_VDEC_OFFSET;
+
+		WREG32(mmPCIE_DEC0_CMD_SWREG16 + offset, 0);
+
+		WREG32(mmPCIE_VDEC0_BRDG_CTRL_GRACEFUL + offset, reg_val);
+
+		/* Wait till all traffic from decoder stops
+		 * before apply core reset.
+		 */
+		rc = hl_poll_timeout(
+				hdev,
+				mmPCIE_VDEC0_BRDG_CTRL_GRACEFUL + offset,
+				graceful,
+				(graceful & graceful_pend_mask),
+				100,
+				timeout_usec);
+		if (rc)
+			dev_err(hdev->dev,
+				"Failed to stop traffic from PCIe Decoder %d\n",
+				dec_id);
+	}
+}
+
+static void gaudi2_stop_dec(struct hl_device *hdev)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	int dcore_id;
+
+	if ((gaudi2->dec_hw_cap_initialized & HW_CAP_DEC_MASK) == 0)
+		return;
+
+	for (dcore_id = 0 ; dcore_id < NUM_OF_DCORES ; dcore_id++)
+		gaudi2_stop_dcore_dec(hdev, dcore_id);
+
+	gaudi2_stop_pcie_dec(hdev);
+}
+
+static void gaudi2_set_arc_running_mode(struct hl_device *hdev, u32 cpu_id, u32 run_mode)
+{
+	u32 reg_base, reg_val;
+
+	reg_base = gaudi2_arc_blocks_bases[cpu_id];
+	if (run_mode == HL_ENGINE_CORE_RUN)
+		reg_val = FIELD_PREP(ARC_FARM_ARC0_AUX_RUN_HALT_REQ_RUN_REQ_MASK, 1);
+	else
+		reg_val = FIELD_PREP(ARC_FARM_ARC0_AUX_RUN_HALT_REQ_HALT_REQ_MASK, 1);
+
+	WREG32(reg_base + ARC_HALT_REQ_OFFSET, reg_val);
+}
+
+static void gaudi2_halt_arcs(struct hl_device *hdev)
+{
+	u16 arc_id;
+
+	for (arc_id = CPU_ID_SCHED_ARC0; arc_id < CPU_ID_MAX; arc_id++) {
+		if (gaudi2_is_arc_enabled(hdev, arc_id))
+			gaudi2_set_arc_running_mode(hdev, arc_id, HL_ENGINE_CORE_HALT);
+	}
+}
+
+static int gaudi2_verify_arc_running_mode(struct hl_device *hdev, u32 cpu_id, u32 run_mode)
+{
+	int rc;
+	u32 reg_base, val, ack_mask, timeout_usec = 100000;
+
+	if (hdev->pldm)
+		timeout_usec *= 100;
+
+	reg_base = gaudi2_arc_blocks_bases[cpu_id];
+	if (run_mode == HL_ENGINE_CORE_RUN)
+		ack_mask = ARC_FARM_ARC0_AUX_RUN_HALT_ACK_RUN_ACK_MASK;
+	else
+		ack_mask = ARC_FARM_ARC0_AUX_RUN_HALT_ACK_HALT_ACK_MASK;
+
+	rc = hl_poll_timeout(hdev, reg_base + ARC_HALT_ACK_OFFSET,
+				val, ((val & ack_mask) == ack_mask),
+				1000, timeout_usec);
+
+	if (!rc) {
+		/* Clear */
+		val = FIELD_PREP(ARC_FARM_ARC0_AUX_RUN_HALT_REQ_RUN_REQ_MASK, 0);
+		WREG32(reg_base + ARC_HALT_REQ_OFFSET, val);
+	}
+
+	return rc;
+}
+
+static void gaudi2_reset_arcs(struct hl_device *hdev)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	u16 arc_id;
+
+	if (!gaudi2)
+		return;
+
+	for (arc_id = CPU_ID_SCHED_ARC0; arc_id < CPU_ID_MAX; arc_id++)
+		if (gaudi2_is_arc_enabled(hdev, arc_id))
+			gaudi2_clr_arc_id_cap(hdev, arc_id);
+}
+
+static void gaudi2_nic_qmans_manual_flush(struct hl_device *hdev)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	u32 queue_id;
+	int i;
+
+	if (!(gaudi2->nic_hw_cap_initialized & HW_CAP_NIC_MASK))
+		return;
+
+	queue_id = GAUDI2_QUEUE_ID_NIC_0_0;
+
+	for (i = 0 ; i < NIC_NUMBER_OF_ENGINES ; i++, queue_id += NUM_OF_PQ_PER_QMAN) {
+		if (!(hdev->nic_ports_mask & BIT(i)))
+			continue;
+
+		gaudi2_qman_manual_flush_common(hdev, queue_id);
+	}
+}
+
+static int gaudi2_set_engine_cores(struct hl_device *hdev, u32 *core_ids,
+					u32 num_cores, u32 core_command)
+{
+	int i, rc;
+
+	for (i = 0 ; i < num_cores ; i++) {
+		if (gaudi2_is_arc_enabled(hdev, core_ids[i]))
+			gaudi2_set_arc_running_mode(hdev, core_ids[i], core_command);
+	}
+
+	for (i = 0 ; i < num_cores ; i++) {
+		if (gaudi2_is_arc_enabled(hdev, core_ids[i])) {
+			rc = gaudi2_verify_arc_running_mode(hdev, core_ids[i], core_command);
+
+			if (rc) {
+				dev_err(hdev->dev, "failed to %s arc: %d\n",
+					(core_command == HL_ENGINE_CORE_HALT) ?
+					"HALT" : "RUN", core_ids[i]);
+				return -1;
+			}
+		}
+	}
+
+	return 0;
+}
+
+static int gaudi2_set_tpc_engine_mode(struct hl_device *hdev, u32 engine_id, u32 engine_command)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	u32 reg_base, reg_addr, reg_val, tpc_id;
+
+	if (!(gaudi2->tpc_hw_cap_initialized & HW_CAP_TPC_MASK))
+		return 0;
+
+	tpc_id = gaudi2_tpc_engine_id_to_tpc_id[engine_id];
+	if (!(gaudi2->tpc_hw_cap_initialized & BIT_ULL(HW_CAP_TPC_SHIFT + tpc_id)))
+		return 0;
+
+	reg_base = gaudi2_tpc_cfg_blocks_bases[tpc_id];
+	reg_addr = reg_base + TPC_CFG_STALL_OFFSET;
+	reg_val = FIELD_PREP(DCORE0_TPC0_CFG_TPC_STALL_V_MASK,
+			(engine_command == HL_ENGINE_STALL) ? 1 : 0);
+	WREG32(reg_addr, reg_val);
+
+	if (engine_command == HL_ENGINE_RESUME) {
+		reg_base = gaudi2_tpc_eml_cfg_blocks_bases[tpc_id];
+		reg_addr = reg_base + TPC_EML_CFG_DBG_CNT_OFFSET;
+		RMWREG32(reg_addr, 0x1, DCORE0_TPC0_EML_CFG_DBG_CNT_DBG_EXIT_MASK);
+	}
+
+	return 0;
+}
+
+static int gaudi2_set_mme_engine_mode(struct hl_device *hdev, u32 engine_id, u32 engine_command)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	u32 reg_base, reg_addr, reg_val, mme_id;
+
+	mme_id = gaudi2_mme_engine_id_to_mme_id[engine_id];
+	if (!(gaudi2->hw_cap_initialized & BIT_ULL(HW_CAP_MME_SHIFT + mme_id)))
+		return 0;
+
+	reg_base = gaudi2_mme_ctrl_lo_blocks_bases[mme_id];
+	reg_addr = reg_base + MME_CTRL_LO_QM_STALL_OFFSET;
+	reg_val = FIELD_PREP(DCORE0_MME_CTRL_LO_QM_STALL_V_MASK,
+			(engine_command == HL_ENGINE_STALL) ? 1 : 0);
+	WREG32(reg_addr, reg_val);
+
+	return 0;
+}
+
+static int gaudi2_set_edma_engine_mode(struct hl_device *hdev, u32 engine_id, u32 engine_command)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	u32 reg_base, reg_addr, reg_val, edma_id;
+
+	if (!(gaudi2->hw_cap_initialized & HW_CAP_EDMA_MASK))
+		return 0;
+
+	edma_id = gaudi2_edma_engine_id_to_edma_id[engine_id];
+	if (!(gaudi2->hw_cap_initialized & BIT_ULL(HW_CAP_EDMA_SHIFT + edma_id)))
+		return 0;
+
+	reg_base = gaudi2_dma_core_blocks_bases[edma_id];
+	reg_addr = reg_base + EDMA_CORE_CFG_STALL_OFFSET;
+	reg_val = FIELD_PREP(DCORE0_EDMA0_CORE_CFG_1_HALT_MASK,
+			(engine_command == HL_ENGINE_STALL) ? 1 : 0);
+	WREG32(reg_addr, reg_val);
+
+	if (engine_command == HL_ENGINE_STALL) {
+		reg_val = FIELD_PREP(DCORE0_EDMA0_CORE_CFG_1_HALT_MASK, 0x1) |
+				FIELD_PREP(DCORE0_EDMA0_CORE_CFG_1_FLUSH_MASK, 0x1);
+		WREG32(reg_addr, reg_val);
+	}
+
+	return 0;
+}
+
+static int gaudi2_set_engine_modes(struct hl_device *hdev,
+		u32 *engine_ids, u32 num_engines, u32 engine_command)
+{
+	int i, rc;
+
+	for (i = 0 ; i < num_engines ; ++i) {
+		switch (engine_ids[i]) {
+		case GAUDI2_DCORE0_ENGINE_ID_TPC_0 ... GAUDI2_DCORE0_ENGINE_ID_TPC_5:
+		case GAUDI2_DCORE1_ENGINE_ID_TPC_0 ... GAUDI2_DCORE1_ENGINE_ID_TPC_5:
+		case GAUDI2_DCORE2_ENGINE_ID_TPC_0 ... GAUDI2_DCORE2_ENGINE_ID_TPC_5:
+		case GAUDI2_DCORE3_ENGINE_ID_TPC_0 ... GAUDI2_DCORE3_ENGINE_ID_TPC_5:
+			rc = gaudi2_set_tpc_engine_mode(hdev, engine_ids[i], engine_command);
+			if (rc)
+				return rc;
+
+			break;
+		case GAUDI2_DCORE0_ENGINE_ID_MME:
+		case GAUDI2_DCORE1_ENGINE_ID_MME:
+		case GAUDI2_DCORE2_ENGINE_ID_MME:
+		case GAUDI2_DCORE3_ENGINE_ID_MME:
+			rc = gaudi2_set_mme_engine_mode(hdev, engine_ids[i], engine_command);
+			if (rc)
+				return rc;
+
+			break;
+		case GAUDI2_DCORE0_ENGINE_ID_EDMA_0 ... GAUDI2_DCORE0_ENGINE_ID_EDMA_1:
+		case GAUDI2_DCORE1_ENGINE_ID_EDMA_0 ... GAUDI2_DCORE1_ENGINE_ID_EDMA_1:
+		case GAUDI2_DCORE2_ENGINE_ID_EDMA_0 ... GAUDI2_DCORE2_ENGINE_ID_EDMA_1:
+		case GAUDI2_DCORE3_ENGINE_ID_EDMA_0 ... GAUDI2_DCORE3_ENGINE_ID_EDMA_1:
+			rc = gaudi2_set_edma_engine_mode(hdev, engine_ids[i], engine_command);
+			if (rc)
+				return rc;
+
+			break;
+		default:
+			dev_err(hdev->dev, "Invalid engine ID %u\n", engine_ids[i]);
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
+static int gaudi2_set_engines(struct hl_device *hdev, u32 *engine_ids,
+					u32 num_engines, u32 engine_command)
+{
+	switch (engine_command) {
+	case HL_ENGINE_CORE_HALT:
+	case HL_ENGINE_CORE_RUN:
+		return gaudi2_set_engine_cores(hdev, engine_ids, num_engines, engine_command);
+
+	case HL_ENGINE_STALL:
+	case HL_ENGINE_RESUME:
+		return gaudi2_set_engine_modes(hdev, engine_ids, num_engines, engine_command);
+
+	default:
+		dev_err(hdev->dev, "failed to execute command id %u\n", engine_command);
+		return -EINVAL;
+	}
+}
+
+static void gaudi2_halt_engines(struct hl_device *hdev, bool hard_reset, bool fw_reset)
+{
+	u32 wait_timeout_ms;
+
+	if (hdev->pldm)
+		wait_timeout_ms = GAUDI2_PLDM_RESET_WAIT_MSEC;
+	else
+		wait_timeout_ms = GAUDI2_RESET_WAIT_MSEC;
+
+	if (fw_reset || hdev->cpld_shutdown)
+		goto skip_engines;
+
+	gaudi2_stop_dma_qmans(hdev);
+	gaudi2_stop_mme_qmans(hdev);
+	gaudi2_stop_tpc_qmans(hdev);
+	gaudi2_stop_rot_qmans(hdev);
+	gaudi2_stop_nic_qmans(hdev);
+	msleep(wait_timeout_ms);
+
+	gaudi2_halt_arcs(hdev);
+	gaudi2_dma_stall(hdev);
+	gaudi2_mme_stall(hdev);
+	gaudi2_tpc_stall(hdev);
+	gaudi2_rotator_stall(hdev);
+
+	msleep(wait_timeout_ms);
+
+	gaudi2_stop_dec(hdev);
+
+	/*
+	 * in case of soft reset do a manual flush for QMANs (currently called
+	 * only for NIC QMANs
+	 */
+	if (!hard_reset)
+		gaudi2_nic_qmans_manual_flush(hdev);
+
+	gaudi2_disable_dma_qmans(hdev);
+	gaudi2_disable_mme_qmans(hdev);
+	gaudi2_disable_tpc_qmans(hdev);
+	gaudi2_disable_rot_qmans(hdev);
+	gaudi2_disable_nic_qmans(hdev);
+	gaudi2_disable_timestamp(hdev);
+
+skip_engines:
+	if (hard_reset) {
+		gaudi2_disable_msix(hdev);
+		return;
+	}
+
+	gaudi2_sync_irqs(hdev);
+}
+
+static void gaudi2_init_firmware_preload_params(struct hl_device *hdev)
+{
+	struct pre_fw_load_props *pre_fw_load = &hdev->fw_loader.pre_fw_load;
+
+	pre_fw_load->cpu_boot_status_reg = mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS;
+	pre_fw_load->sts_boot_dev_sts0_reg = mmCPU_BOOT_DEV_STS0;
+	pre_fw_load->sts_boot_dev_sts1_reg = mmCPU_BOOT_DEV_STS1;
+	pre_fw_load->boot_err0_reg = mmCPU_BOOT_ERR0;
+	pre_fw_load->boot_err1_reg = mmCPU_BOOT_ERR1;
+	pre_fw_load->wait_for_preboot_timeout = GAUDI2_PREBOOT_REQ_TIMEOUT_USEC;
+	pre_fw_load->wait_for_preboot_extended_timeout =
+		GAUDI2_PREBOOT_EXTENDED_REQ_TIMEOUT_USEC;
+}
+
+static void gaudi2_init_firmware_loader(struct hl_device *hdev)
+{
+	struct fw_load_mgr *fw_loader = &hdev->fw_loader;
+	struct dynamic_fw_load_mgr *dynamic_loader;
+	struct cpu_dyn_regs *dyn_regs;
+
+	/* fill common fields */
+	fw_loader->fw_comp_loaded = FW_TYPE_NONE;
+	fw_loader->boot_fit_img.image_name = GAUDI2_BOOT_FIT_FILE;
+	fw_loader->linux_img.image_name = GAUDI2_LINUX_FW_FILE;
+	fw_loader->boot_fit_timeout = GAUDI2_BOOT_FIT_REQ_TIMEOUT_USEC;
+	fw_loader->skip_bmc = false;
+	fw_loader->sram_bar_id = SRAM_CFG_BAR_ID;
+	fw_loader->dram_bar_id = DRAM_BAR_ID;
+	fw_loader->cpu_timeout = GAUDI2_CPU_TIMEOUT_USEC;
+
+	/* here we update initial values for few specific dynamic regs (as
+	 * before reading the first descriptor from FW those value has to be
+	 * hard-coded). in later stages of the protocol those values will be
+	 * updated automatically by reading the FW descriptor so data there
+	 * will always be up-to-date
+	 */
+	dynamic_loader = &hdev->fw_loader.dynamic_loader;
+	dyn_regs = &dynamic_loader->comm_desc.cpu_dyn_regs;
+	dyn_regs->kmd_msg_to_cpu = cpu_to_le32(mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU);
+	dyn_regs->cpu_cmd_status_to_host = cpu_to_le32(mmCPU_CMD_STATUS_TO_HOST);
+	dynamic_loader->wait_for_bl_timeout = GAUDI2_WAIT_FOR_BL_TIMEOUT_USEC;
+}
+
+static int gaudi2_init_cpu(struct hl_device *hdev)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	int rc;
+
+	if (!(hdev->fw_components & FW_TYPE_PREBOOT_CPU))
+		return 0;
+
+	if (gaudi2->hw_cap_initialized & HW_CAP_CPU)
+		return 0;
+
+	rc = hl_fw_init_cpu(hdev);
+	if (rc)
+		return rc;
+
+	gaudi2->hw_cap_initialized |= HW_CAP_CPU;
+
+	return 0;
+}
+
+static int gaudi2_init_cpu_queues(struct hl_device *hdev, u32 cpu_timeout)
+{
+	struct hl_hw_queue *cpu_pq = &hdev->kernel_queues[GAUDI2_QUEUE_ID_CPU_PQ];
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	struct cpu_dyn_regs *dyn_regs;
+	struct hl_eq *eq;
+	u32 status;
+	int err;
+
+	if (!hdev->cpu_queues_enable)
+		return 0;
+
+	if (gaudi2->hw_cap_initialized & HW_CAP_CPU_Q)
+		return 0;
+
+	eq = &hdev->event_queue;
+
+	dyn_regs = &hdev->fw_loader.dynamic_loader.comm_desc.cpu_dyn_regs;
+
+	WREG32(mmCPU_IF_PQ_BASE_ADDR_LOW, lower_32_bits(cpu_pq->bus_address));
+	WREG32(mmCPU_IF_PQ_BASE_ADDR_HIGH, upper_32_bits(cpu_pq->bus_address));
+
+	WREG32(mmCPU_IF_EQ_BASE_ADDR_LOW, lower_32_bits(eq->bus_address));
+	WREG32(mmCPU_IF_EQ_BASE_ADDR_HIGH, upper_32_bits(eq->bus_address));
+
+	WREG32(mmCPU_IF_CQ_BASE_ADDR_LOW, lower_32_bits(hdev->cpu_accessible_dma_address));
+	WREG32(mmCPU_IF_CQ_BASE_ADDR_HIGH, upper_32_bits(hdev->cpu_accessible_dma_address));
+
+	WREG32(mmCPU_IF_PQ_LENGTH, HL_QUEUE_SIZE_IN_BYTES);
+	WREG32(mmCPU_IF_EQ_LENGTH, HL_EQ_SIZE_IN_BYTES);
+	WREG32(mmCPU_IF_CQ_LENGTH, HL_CPU_ACCESSIBLE_MEM_SIZE);
+
+	/* Used for EQ CI */
+	WREG32(mmCPU_IF_EQ_RD_OFFS, 0);
+
+	WREG32(mmCPU_IF_PF_PQ_PI, 0);
+
+	WREG32(mmCPU_IF_QUEUE_INIT, PQ_INIT_STATUS_READY_FOR_CP);
+
+	/* Let the ARC know we are ready as it is now handling those queues  */
+
+	WREG32(le32_to_cpu(dyn_regs->gic_host_pi_upd_irq),
+		gaudi2_irq_map_table[GAUDI2_EVENT_CPU_PI_UPDATE].cpu_id);
+
+	err = hl_poll_timeout(
+		hdev,
+		mmCPU_IF_QUEUE_INIT,
+		status,
+		(status == PQ_INIT_STATUS_READY_FOR_HOST),
+		1000,
+		cpu_timeout);
+
+	if (err) {
+		dev_err(hdev->dev, "Failed to communicate with device CPU (timeout)\n");
+		return -EIO;
+	}
+
+	/* update FW application security bits */
+	if (prop->fw_cpu_boot_dev_sts0_valid)
+		prop->fw_app_cpu_boot_dev_sts0 = RREG32(mmCPU_BOOT_DEV_STS0);
+
+	if (prop->fw_cpu_boot_dev_sts1_valid)
+		prop->fw_app_cpu_boot_dev_sts1 = RREG32(mmCPU_BOOT_DEV_STS1);
+
+	gaudi2->hw_cap_initialized |= HW_CAP_CPU_Q;
+	return 0;
+}
+
+static void gaudi2_init_qman_pq(struct hl_device *hdev, u32 reg_base,
+				u32 queue_id_base)
+{
+	struct hl_hw_queue *q;
+	u32 pq_id, pq_offset;
+
+	for (pq_id = 0 ; pq_id < NUM_OF_PQ_PER_QMAN ; pq_id++) {
+		q = &hdev->kernel_queues[queue_id_base + pq_id];
+		pq_offset = pq_id * 4;
+
+		if (q->dram_bd) {
+			WREG32(reg_base + QM_PQ_BASE_LO_0_OFFSET + pq_offset,
+					lower_32_bits(q->pq_dram_address));
+			WREG32(reg_base + QM_PQ_BASE_HI_0_OFFSET + pq_offset,
+					upper_32_bits(q->pq_dram_address));
+		} else {
+			WREG32(reg_base + QM_PQ_BASE_LO_0_OFFSET + pq_offset,
+					lower_32_bits(q->bus_address));
+			WREG32(reg_base + QM_PQ_BASE_HI_0_OFFSET + pq_offset,
+					upper_32_bits(q->bus_address));
+		}
+		WREG32(reg_base + QM_PQ_SIZE_0_OFFSET + pq_offset, ilog2(HL_QUEUE_LENGTH));
+		WREG32(reg_base + QM_PQ_PI_0_OFFSET + pq_offset, 0);
+		WREG32(reg_base + QM_PQ_CI_0_OFFSET + pq_offset, 0);
+	}
+}
+
+static void gaudi2_init_qman_cp(struct hl_device *hdev, u32 reg_base)
+{
+	u32 cp_id, cp_offset, mtr_base_lo, mtr_base_hi, so_base_lo, so_base_hi;
+
+	mtr_base_lo = lower_32_bits(CFG_BASE + mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0);
+	mtr_base_hi = upper_32_bits(CFG_BASE + mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0);
+	so_base_lo = lower_32_bits(CFG_BASE + mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0);
+	so_base_hi = upper_32_bits(CFG_BASE + mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0);
+
+	for (cp_id = 0 ; cp_id < NUM_OF_CP_PER_QMAN; cp_id++) {
+		cp_offset = cp_id * 4;
+
+		WREG32(reg_base + QM_CP_MSG_BASE0_ADDR_LO_0_OFFSET + cp_offset, mtr_base_lo);
+		WREG32(reg_base + QM_CP_MSG_BASE0_ADDR_HI_0_OFFSET + cp_offset,	mtr_base_hi);
+		WREG32(reg_base + QM_CP_MSG_BASE1_ADDR_LO_0_OFFSET + cp_offset,	so_base_lo);
+		WREG32(reg_base + QM_CP_MSG_BASE1_ADDR_HI_0_OFFSET + cp_offset,	so_base_hi);
+	}
+
+	/* allow QMANs to accept work from ARC CQF */
+	WREG32(reg_base + QM_CP_CFG_OFFSET, FIELD_PREP(PDMA0_QM_CP_CFG_SWITCH_EN_MASK, 0x1));
+}
+
+static void gaudi2_init_qman_pqc(struct hl_device *hdev, u32 reg_base,
+				u32 queue_id_base)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	u32 pq_id, pq_offset, so_base_lo, so_base_hi;
+
+	so_base_lo = lower_32_bits(CFG_BASE + mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0);
+	so_base_hi = upper_32_bits(CFG_BASE + mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0);
+
+	for (pq_id = 0 ; pq_id < NUM_OF_PQ_PER_QMAN ; pq_id++) {
+		pq_offset = pq_id * 4;
+
+		/* Configure QMAN HBW to scratchpad as it is not needed */
+		WREG32(reg_base + QM_PQC_HBW_BASE_LO_0_OFFSET + pq_offset,
+				lower_32_bits(gaudi2->scratchpad_bus_address));
+		WREG32(reg_base + QM_PQC_HBW_BASE_HI_0_OFFSET + pq_offset,
+				upper_32_bits(gaudi2->scratchpad_bus_address));
+		WREG32(reg_base + QM_PQC_SIZE_0_OFFSET + pq_offset,
+				ilog2(PAGE_SIZE / sizeof(struct hl_cq_entry)));
+
+		WREG32(reg_base + QM_PQC_PI_0_OFFSET + pq_offset, 0);
+		WREG32(reg_base + QM_PQC_LBW_WDATA_0_OFFSET + pq_offset, QM_PQC_LBW_WDATA);
+		WREG32(reg_base + QM_PQC_LBW_BASE_LO_0_OFFSET + pq_offset, so_base_lo);
+		WREG32(reg_base + QM_PQC_LBW_BASE_HI_0_OFFSET + pq_offset, so_base_hi);
+	}
+
+	/* Enable QMAN H/W completion */
+	WREG32(reg_base + QM_PQC_CFG_OFFSET, 1 << PDMA0_QM_PQC_CFG_EN_SHIFT);
+}
+
+static u32 gaudi2_get_dyn_sp_reg(struct hl_device *hdev, u32 queue_id_base)
+{
+	struct cpu_dyn_regs *dyn_regs = &hdev->fw_loader.dynamic_loader.comm_desc.cpu_dyn_regs;
+	u32 sp_reg_addr;
+
+	switch (queue_id_base) {
+	case GAUDI2_QUEUE_ID_PDMA_0_0...GAUDI2_QUEUE_ID_PDMA_1_3:
+		fallthrough;
+	case GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0...GAUDI2_QUEUE_ID_DCORE0_EDMA_1_3:
+		fallthrough;
+	case GAUDI2_QUEUE_ID_DCORE1_EDMA_0_0...GAUDI2_QUEUE_ID_DCORE1_EDMA_1_3:
+		fallthrough;
+	case GAUDI2_QUEUE_ID_DCORE2_EDMA_0_0...GAUDI2_QUEUE_ID_DCORE2_EDMA_1_3:
+		fallthrough;
+	case GAUDI2_QUEUE_ID_DCORE3_EDMA_0_0...GAUDI2_QUEUE_ID_DCORE3_EDMA_1_3:
+		sp_reg_addr = le32_to_cpu(dyn_regs->gic_dma_qm_irq_ctrl);
+		break;
+	case GAUDI2_QUEUE_ID_DCORE0_MME_0_0...GAUDI2_QUEUE_ID_DCORE0_MME_0_3:
+		fallthrough;
+	case GAUDI2_QUEUE_ID_DCORE1_MME_0_0...GAUDI2_QUEUE_ID_DCORE1_MME_0_3:
+		fallthrough;
+	case GAUDI2_QUEUE_ID_DCORE2_MME_0_0...GAUDI2_QUEUE_ID_DCORE2_MME_0_3:
+		fallthrough;
+	case GAUDI2_QUEUE_ID_DCORE3_MME_0_0...GAUDI2_QUEUE_ID_DCORE3_MME_0_3:
+		sp_reg_addr = le32_to_cpu(dyn_regs->gic_mme_qm_irq_ctrl);
+		break;
+	case GAUDI2_QUEUE_ID_DCORE0_TPC_0_0 ... GAUDI2_QUEUE_ID_DCORE0_TPC_6_3:
+		fallthrough;
+	case GAUDI2_QUEUE_ID_DCORE1_TPC_0_0 ... GAUDI2_QUEUE_ID_DCORE1_TPC_5_3:
+		fallthrough;
+	case GAUDI2_QUEUE_ID_DCORE2_TPC_0_0 ... GAUDI2_QUEUE_ID_DCORE2_TPC_5_3:
+		fallthrough;
+	case GAUDI2_QUEUE_ID_DCORE3_TPC_0_0 ... GAUDI2_QUEUE_ID_DCORE3_TPC_5_3:
+		sp_reg_addr = le32_to_cpu(dyn_regs->gic_tpc_qm_irq_ctrl);
+		break;
+	case GAUDI2_QUEUE_ID_ROT_0_0...GAUDI2_QUEUE_ID_ROT_1_3:
+		sp_reg_addr = le32_to_cpu(dyn_regs->gic_rot_qm_irq_ctrl);
+		break;
+	case GAUDI2_QUEUE_ID_NIC_0_0...GAUDI2_QUEUE_ID_NIC_23_3:
+		sp_reg_addr = le32_to_cpu(dyn_regs->gic_nic_qm_irq_ctrl);
+		break;
+	default:
+		dev_err(hdev->dev, "Unexpected h/w queue %d\n", queue_id_base);
+		return 0;
+	}
+
+	return sp_reg_addr;
+}
+
+static void gaudi2_init_qman_common(struct hl_device *hdev, u32 reg_base,
+					u32 queue_id_base)
+{
+	u32 glbl_prot = QMAN_MAKE_TRUSTED, irq_handler_offset;
+	int map_table_entry;
+
+	WREG32(reg_base + QM_GLBL_PROT_OFFSET, glbl_prot);
+
+	irq_handler_offset = gaudi2_get_dyn_sp_reg(hdev, queue_id_base);
+	WREG32(reg_base + QM_GLBL_ERR_ADDR_LO_OFFSET, lower_32_bits(CFG_BASE + irq_handler_offset));
+	WREG32(reg_base + QM_GLBL_ERR_ADDR_HI_OFFSET, upper_32_bits(CFG_BASE + irq_handler_offset));
+
+	map_table_entry = gaudi2_qman_async_event_id[queue_id_base];
+	WREG32(reg_base + QM_GLBL_ERR_WDATA_OFFSET,
+		gaudi2_irq_map_table[map_table_entry].cpu_id);
+
+	WREG32(reg_base + QM_ARB_ERR_MSG_EN_OFFSET, QM_ARB_ERR_MSG_EN_MASK);
+
+	WREG32(reg_base + QM_ARB_SLV_CHOISE_WDT_OFFSET, GAUDI2_ARB_WDT_TIMEOUT);
+	WREG32(reg_base + QM_GLBL_CFG1_OFFSET, 0);
+	WREG32(reg_base + QM_GLBL_CFG2_OFFSET, 0);
+
+	/* Enable the QMAN channel.
+	 * PDMA QMAN configuration is different, as we do not allow user to
+	 * access some of the CPs.
+	 * PDMA0: CP2/3 are reserved for the ARC usage.
+	 * PDMA1: CP1/2/3 are reserved for the ARC usage.
+	 */
+	if (reg_base == gaudi2_qm_blocks_bases[GAUDI2_QUEUE_ID_PDMA_1_0])
+		WREG32(reg_base + QM_GLBL_CFG0_OFFSET, PDMA1_QMAN_ENABLE);
+	else if (reg_base == gaudi2_qm_blocks_bases[GAUDI2_QUEUE_ID_PDMA_0_0])
+		WREG32(reg_base + QM_GLBL_CFG0_OFFSET, PDMA0_QMAN_ENABLE);
+	else
+		WREG32(reg_base + QM_GLBL_CFG0_OFFSET, QMAN_ENABLE);
+}
+
+static void gaudi2_init_qman(struct hl_device *hdev, u32 reg_base,
+		u32 queue_id_base)
+{
+	u32 pq_id;
+
+	for (pq_id = 0 ; pq_id < NUM_OF_PQ_PER_QMAN ; pq_id++)
+		hdev->kernel_queues[queue_id_base + pq_id].cq_id = GAUDI2_RESERVED_CQ_CS_COMPLETION;
+
+	gaudi2_init_qman_pq(hdev, reg_base, queue_id_base);
+	gaudi2_init_qman_cp(hdev, reg_base);
+	gaudi2_init_qman_pqc(hdev, reg_base, queue_id_base);
+	gaudi2_init_qman_common(hdev, reg_base, queue_id_base);
+}
+
+static void gaudi2_init_dma_core(struct hl_device *hdev, u32 reg_base,
+				u32 dma_core_id, bool is_secure)
+{
+	u32 prot, irq_handler_offset;
+	struct cpu_dyn_regs *dyn_regs;
+	int map_table_entry;
+
+	prot = 1 << ARC_FARM_KDMA_PROT_ERR_VAL_SHIFT;
+	if (is_secure)
+		prot |= 1 << ARC_FARM_KDMA_PROT_VAL_SHIFT;
+
+	WREG32(reg_base + DMA_CORE_PROT_OFFSET, prot);
+
+	dyn_regs = &hdev->fw_loader.dynamic_loader.comm_desc.cpu_dyn_regs;
+	irq_handler_offset = le32_to_cpu(dyn_regs->gic_dma_core_irq_ctrl);
+
+	WREG32(reg_base + DMA_CORE_ERRMSG_ADDR_LO_OFFSET,
+			lower_32_bits(CFG_BASE + irq_handler_offset));
+
+	WREG32(reg_base + DMA_CORE_ERRMSG_ADDR_HI_OFFSET,
+			upper_32_bits(CFG_BASE + irq_handler_offset));
+
+	map_table_entry = gaudi2_dma_core_async_event_id[dma_core_id];
+	WREG32(reg_base + DMA_CORE_ERRMSG_WDATA_OFFSET,
+		gaudi2_irq_map_table[map_table_entry].cpu_id);
+
+	/* Enable the DMA channel */
+	WREG32(reg_base + DMA_CORE_CFG_0_OFFSET, 1 << ARC_FARM_KDMA_CFG_0_EN_SHIFT);
+}
+
+static void gaudi2_init_kdma(struct hl_device *hdev)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	u32 reg_base;
+
+	if ((gaudi2->hw_cap_initialized & HW_CAP_KDMA) == HW_CAP_KDMA)
+		return;
+
+	reg_base = gaudi2_dma_core_blocks_bases[DMA_CORE_ID_KDMA];
+
+	gaudi2_init_dma_core(hdev, reg_base, DMA_CORE_ID_KDMA, true);
+
+	gaudi2->hw_cap_initialized |= HW_CAP_KDMA;
+}
+
+static void gaudi2_init_pdma(struct hl_device *hdev)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	u32 reg_base;
+
+	if ((gaudi2->hw_cap_initialized & HW_CAP_PDMA_MASK) == HW_CAP_PDMA_MASK)
+		return;
+
+	reg_base = gaudi2_dma_core_blocks_bases[DMA_CORE_ID_PDMA0];
+	gaudi2_init_dma_core(hdev, reg_base, DMA_CORE_ID_PDMA0, false);
+
+	reg_base = gaudi2_qm_blocks_bases[GAUDI2_QUEUE_ID_PDMA_0_0];
+	gaudi2_init_qman(hdev, reg_base, GAUDI2_QUEUE_ID_PDMA_0_0);
+
+	reg_base = gaudi2_dma_core_blocks_bases[DMA_CORE_ID_PDMA1];
+	gaudi2_init_dma_core(hdev, reg_base, DMA_CORE_ID_PDMA1, false);
+
+	reg_base = gaudi2_qm_blocks_bases[GAUDI2_QUEUE_ID_PDMA_1_0];
+	gaudi2_init_qman(hdev, reg_base, GAUDI2_QUEUE_ID_PDMA_1_0);
+
+	gaudi2->hw_cap_initialized |= HW_CAP_PDMA_MASK;
+}
+
+static void gaudi2_init_edma_instance(struct hl_device *hdev, u8 seq)
+{
+	u32 reg_base, base_edma_core_id, base_edma_qman_id;
+
+	base_edma_core_id = DMA_CORE_ID_EDMA0 + seq;
+	base_edma_qman_id = edma_stream_base[seq];
+
+	reg_base = gaudi2_dma_core_blocks_bases[base_edma_core_id];
+	gaudi2_init_dma_core(hdev, reg_base, base_edma_core_id, false);
+
+	reg_base = gaudi2_qm_blocks_bases[base_edma_qman_id];
+	gaudi2_init_qman(hdev, reg_base, base_edma_qman_id);
+}
+
+static void gaudi2_init_edma(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	int dcore, inst;
+
+	if ((gaudi2->hw_cap_initialized & HW_CAP_EDMA_MASK) == HW_CAP_EDMA_MASK)
+		return;
+
+	for (dcore = 0 ; dcore < NUM_OF_DCORES ; dcore++) {
+		for (inst = 0 ; inst < NUM_OF_EDMA_PER_DCORE ; inst++) {
+			u8 seq = dcore * NUM_OF_EDMA_PER_DCORE + inst;
+
+			if (!(prop->edma_enabled_mask & BIT(seq)))
+				continue;
+
+			gaudi2_init_edma_instance(hdev, seq);
+
+			gaudi2->hw_cap_initialized |= BIT_ULL(HW_CAP_EDMA_SHIFT + seq);
+		}
+	}
+}
+
+/*
+ * gaudi2_arm_monitors_for_virt_msix_db() - Arm monitors for writing to the virtual MSI-X doorbell.
+ * @hdev: pointer to habanalabs device structure.
+ * @sob_id: sync object ID.
+ * @first_mon_id: ID of first monitor out of 3 consecutive monitors.
+ * @interrupt_id: interrupt ID.
+ *
+ * Some initiators cannot have HBW address in their completion address registers, and thus cannot
+ * write directly to the HBW host memory of the virtual MSI-X doorbell.
+ * Instead, they are configured to LBW write to a sync object, and a monitor will do the HBW write.
+ *
+ * The mechanism in the sync manager block is composed of a master monitor with 3 messages.
+ * In addition to the HBW write, the other 2 messages are for preparing the monitor to next
+ * completion, by decrementing the sync object value and re-arming the monitor.
+ */
+static void gaudi2_arm_monitors_for_virt_msix_db(struct hl_device *hdev, u32 sob_id,
+							u32 first_mon_id, u32 interrupt_id)
+{
+	u32 sob_offset, first_mon_offset, mon_offset, payload, sob_group, mode, arm, config;
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	u64 addr;
+	u8 mask;
+
+	/* Reset the SOB value */
+	sob_offset = sob_id * sizeof(u32);
+	WREG32(mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 + sob_offset, 0);
+
+	/* Configure 3 monitors:
+	 * 1. Write interrupt ID to the virtual MSI-X doorbell (master monitor)
+	 * 2. Decrement SOB value by 1.
+	 * 3. Re-arm the master monitor.
+	 */
+
+	first_mon_offset = first_mon_id * sizeof(u32);
+
+	/* 2nd monitor: Decrement SOB value by 1 */
+	mon_offset = first_mon_offset + sizeof(u32);
+
+	addr = CFG_BASE + mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 + sob_offset;
+	WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 + mon_offset, lower_32_bits(addr));
+	WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_0 + mon_offset, upper_32_bits(addr));
+
+	payload = FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_VAL_MASK, 0x7FFF) | /* "-1" */
+			FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_SIGN_MASK, 1) |
+			FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_INC_MASK, 1);
+	WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_0 + mon_offset, payload);
+
+	/* 3rd monitor: Re-arm the master monitor */
+	mon_offset = first_mon_offset + 2 * sizeof(u32);
+
+	addr = CFG_BASE + mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_0 + first_mon_offset;
+	WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 + mon_offset, lower_32_bits(addr));
+	WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_0 + mon_offset, upper_32_bits(addr));
+
+	sob_group = sob_id / 8;
+	mask = ~BIT(sob_id & 0x7);
+	mode = 0; /* comparison mode is "greater than or equal to" */
+	arm = FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_MON_ARM_SID_MASK, sob_group) |
+			FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_MON_ARM_MASK_MASK, mask) |
+			FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_MON_ARM_SOP_MASK, mode) |
+			FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_MON_ARM_SOD_MASK, 1);
+
+	payload = arm;
+	WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_0 + mon_offset, payload);
+
+	/* 1st monitor (master): Write interrupt ID to the virtual MSI-X doorbell */
+	mon_offset = first_mon_offset;
+
+	config = FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_WR_NUM_MASK, 2); /* "2": 3 writes */
+	WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_0 + mon_offset, config);
+
+	addr = gaudi2->virt_msix_db_dma_addr;
+	WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 + mon_offset, lower_32_bits(addr));
+	WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_0 + mon_offset, upper_32_bits(addr));
+
+	payload = interrupt_id;
+	WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_0 + mon_offset, payload);
+
+	WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_0 + mon_offset, arm);
+}
+
+static void gaudi2_prepare_sm_for_virt_msix_db(struct hl_device *hdev)
+{
+	u32 decoder_id, sob_id, first_mon_id, interrupt_id;
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+
+	/* Decoder normal/abnormal interrupts */
+	for (decoder_id = 0 ; decoder_id < NUMBER_OF_DEC ; ++decoder_id) {
+		if (!(prop->decoder_enabled_mask & BIT(decoder_id)))
+			continue;
+
+		sob_id = GAUDI2_RESERVED_SOB_DEC_NRM_FIRST + decoder_id;
+		first_mon_id = GAUDI2_RESERVED_MON_DEC_NRM_FIRST + 3 * decoder_id;
+		interrupt_id = GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM + 2 * decoder_id;
+		gaudi2_arm_monitors_for_virt_msix_db(hdev, sob_id, first_mon_id, interrupt_id);
+
+		sob_id = GAUDI2_RESERVED_SOB_DEC_ABNRM_FIRST + decoder_id;
+		first_mon_id = GAUDI2_RESERVED_MON_DEC_ABNRM_FIRST + 3 * decoder_id;
+		interrupt_id += 1;
+		gaudi2_arm_monitors_for_virt_msix_db(hdev, sob_id, first_mon_id, interrupt_id);
+	}
+}
+
+static void gaudi2_init_sm(struct hl_device *hdev)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	u64 cq_address;
+	u32 reg_val;
+	int i;
+
+	/* Enable HBW/LBW CQ for completion monitors */
+	reg_val = FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_CQ_EN_MASK, 1);
+	reg_val |= FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_LBW_EN_MASK, 1);
+
+	for (i = 0 ; i < GAUDI2_MAX_PENDING_CS ; i++)
+		WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_0 + (4 * i), reg_val);
+
+	/* Enable only HBW CQ for KDMA completion monitor */
+	reg_val = FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_CQ_EN_MASK, 1);
+	WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_0 + (4 * i), reg_val);
+
+	/* Init CQ0 DB - configure the monitor to trigger MSI-X interrupt */
+	WREG32(mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_0, lower_32_bits(gaudi2->virt_msix_db_dma_addr));
+	WREG32(mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_0, upper_32_bits(gaudi2->virt_msix_db_dma_addr));
+	WREG32(mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_0, GAUDI2_IRQ_NUM_COMPLETION);
+
+	for (i = 0 ; i < GAUDI2_RESERVED_CQ_NUMBER ; i++) {
+		cq_address =
+			hdev->completion_queue[i].bus_address;
+
+		WREG32(mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_0 + (4 * i),
+							lower_32_bits(cq_address));
+		WREG32(mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_0 + (4 * i),
+							upper_32_bits(cq_address));
+		WREG32(mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_0 + (4 * i),
+							ilog2(HL_CQ_SIZE_IN_BYTES));
+	}
+
+	/* Configure kernel ASID and MMU BP*/
+	WREG32(mmDCORE0_SYNC_MNGR_GLBL_ASID_SEC, 0x10000);
+	WREG32(mmDCORE0_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV, 0);
+
+	/* Initialize sync objects and monitors which are used for the virtual MSI-X doorbell */
+	gaudi2_prepare_sm_for_virt_msix_db(hdev);
+}
+
+static void gaudi2_init_mme_acc(struct hl_device *hdev, u32 reg_base)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	u32 reg_val;
+	int i;
+
+	reg_val = FIELD_PREP(MME_ACC_INTR_MASK_WBC_ERR_RESP_MASK, 0);
+	reg_val |= FIELD_PREP(MME_ACC_INTR_MASK_AP_SRC_POS_INF_MASK, 1);
+	reg_val |= FIELD_PREP(MME_ACC_INTR_MASK_AP_SRC_NEG_INF_MASK, 1);
+	reg_val |= FIELD_PREP(MME_ACC_INTR_MASK_AP_SRC_NAN_MASK, 1);
+	reg_val |= FIELD_PREP(MME_ACC_INTR_MASK_AP_RESULT_POS_INF_MASK, 1);
+	reg_val |= FIELD_PREP(MME_ACC_INTR_MASK_AP_RESULT_NEG_INF_MASK, 1);
+
+	WREG32(reg_base + MME_ACC_INTR_MASK_OFFSET, reg_val);
+	WREG32(reg_base + MME_ACC_AP_LFSR_POLY_OFFSET, 0x80DEADAF);
+
+	for (i = 0 ; i < MME_NUM_OF_LFSR_SEEDS ; i++) {
+		WREG32(reg_base + MME_ACC_AP_LFSR_SEED_SEL_OFFSET, i);
+		WREG32(reg_base + MME_ACC_AP_LFSR_SEED_WDATA_OFFSET, gaudi2->lfsr_rand_seeds[i]);
+	}
+}
+
+static void gaudi2_init_dcore_mme(struct hl_device *hdev, int dcore_id,
+							bool config_qman_only)
+{
+	u32 queue_id_base, reg_base;
+
+	switch (dcore_id) {
+	case 0:
+		queue_id_base = GAUDI2_QUEUE_ID_DCORE0_MME_0_0;
+		break;
+	case 1:
+		queue_id_base = GAUDI2_QUEUE_ID_DCORE1_MME_0_0;
+		break;
+	case 2:
+		queue_id_base = GAUDI2_QUEUE_ID_DCORE2_MME_0_0;
+		break;
+	case 3:
+		queue_id_base = GAUDI2_QUEUE_ID_DCORE3_MME_0_0;
+		break;
+	default:
+		dev_err(hdev->dev, "Invalid dcore id %u\n", dcore_id);
+		return;
+	}
+
+	if (!config_qman_only) {
+		reg_base = gaudi2_mme_acc_blocks_bases[dcore_id];
+		gaudi2_init_mme_acc(hdev, reg_base);
+	}
+
+	reg_base = gaudi2_qm_blocks_bases[queue_id_base];
+	gaudi2_init_qman(hdev, reg_base, queue_id_base);
+}
+
+static void gaudi2_init_mme(struct hl_device *hdev)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	int i;
+
+	if ((gaudi2->hw_cap_initialized & HW_CAP_MME_MASK) == HW_CAP_MME_MASK)
+		return;
+
+	for (i = 0 ; i < NUM_OF_DCORES ; i++) {
+		gaudi2_init_dcore_mme(hdev, i, false);
+
+		gaudi2->hw_cap_initialized |= BIT_ULL(HW_CAP_MME_SHIFT + i);
+	}
+}
+
+static void gaudi2_init_tpc_cfg(struct hl_device *hdev, u32 reg_base)
+{
+	/* Mask arithmetic and QM interrupts in TPC */
+	WREG32(reg_base + TPC_CFG_TPC_INTR_MASK_OFFSET, 0x23FFFE);
+
+	/* Set 16 cache lines */
+	WREG32(reg_base + TPC_CFG_MSS_CONFIG_OFFSET,
+			2 << DCORE0_TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_SHIFT);
+}
+
+struct gaudi2_tpc_init_cfg_data {
+	enum gaudi2_queue_id dcore_tpc_qid_base[NUM_OF_DCORES];
+};
+
+static void gaudi2_init_tpc_config(struct hl_device *hdev, int dcore, int inst,
+					u32 offset, struct iterate_module_ctx *ctx)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	struct gaudi2_tpc_init_cfg_data *cfg_data = ctx->data;
+	u32 queue_id_base;
+	u8 seq;
+
+	queue_id_base = cfg_data->dcore_tpc_qid_base[dcore] + (inst * NUM_OF_PQ_PER_QMAN);
+
+	if (dcore == 0 && inst == (NUM_DCORE0_TPC - 1))
+		/* gets last sequence number */
+		seq = NUM_OF_DCORES * NUM_OF_TPC_PER_DCORE;
+	else
+		seq = dcore * NUM_OF_TPC_PER_DCORE + inst;
+
+	gaudi2_init_tpc_cfg(hdev, mmDCORE0_TPC0_CFG_BASE + offset);
+	gaudi2_init_qman(hdev, mmDCORE0_TPC0_QM_BASE + offset, queue_id_base);
+
+	gaudi2->tpc_hw_cap_initialized |= BIT_ULL(HW_CAP_TPC_SHIFT + seq);
+}
+
+static void gaudi2_init_tpc(struct hl_device *hdev)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	struct gaudi2_tpc_init_cfg_data init_cfg_data;
+	struct iterate_module_ctx tpc_iter;
+
+	if (!hdev->asic_prop.tpc_enabled_mask)
+		return;
+
+	if ((gaudi2->tpc_hw_cap_initialized & HW_CAP_TPC_MASK) == HW_CAP_TPC_MASK)
+		return;
+
+	init_cfg_data.dcore_tpc_qid_base[0] = GAUDI2_QUEUE_ID_DCORE0_TPC_0_0;
+	init_cfg_data.dcore_tpc_qid_base[1] = GAUDI2_QUEUE_ID_DCORE1_TPC_0_0;
+	init_cfg_data.dcore_tpc_qid_base[2] = GAUDI2_QUEUE_ID_DCORE2_TPC_0_0;
+	init_cfg_data.dcore_tpc_qid_base[3] = GAUDI2_QUEUE_ID_DCORE3_TPC_0_0;
+	tpc_iter.fn = &gaudi2_init_tpc_config;
+	tpc_iter.data = &init_cfg_data;
+	gaudi2_iterate_tpcs(hdev, &tpc_iter);
+}
+
+static void gaudi2_init_rotator(struct hl_device *hdev)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	u32 i, reg_base, queue_id;
+
+	queue_id = GAUDI2_QUEUE_ID_ROT_0_0;
+
+	for (i = 0 ; i < NUM_OF_ROT ; i++, queue_id += NUM_OF_PQ_PER_QMAN) {
+		reg_base = gaudi2_qm_blocks_bases[queue_id];
+		gaudi2_init_qman(hdev, reg_base, queue_id);
+
+		gaudi2->hw_cap_initialized |= BIT_ULL(HW_CAP_ROT_SHIFT + i);
+	}
+}
+
+static void gaudi2_init_vdec_brdg_ctrl(struct hl_device *hdev, u64 base_addr, u32 decoder_id)
+{
+	u32 sob_id;
+
+	/* VCMD normal interrupt */
+	sob_id = GAUDI2_RESERVED_SOB_DEC_NRM_FIRST + decoder_id;
+	WREG32(base_addr + BRDG_CTRL_NRM_MSIX_LBW_AWADDR,
+			mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 + sob_id * sizeof(u32));
+	WREG32(base_addr + BRDG_CTRL_NRM_MSIX_LBW_WDATA, GAUDI2_SOB_INCREMENT_BY_ONE);
+
+	/* VCMD abnormal interrupt */
+	sob_id = GAUDI2_RESERVED_SOB_DEC_ABNRM_FIRST + decoder_id;
+	WREG32(base_addr + BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR,
+			mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 + sob_id * sizeof(u32));
+	WREG32(base_addr + BRDG_CTRL_ABNRM_MSIX_LBW_WDATA, GAUDI2_SOB_INCREMENT_BY_ONE);
+}
+
+static void gaudi2_init_dec(struct hl_device *hdev)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	u32 dcore_id, dec_id, dec_bit;
+	u64 base_addr;
+
+	if (!hdev->asic_prop.decoder_enabled_mask)
+		return;
+
+	if ((gaudi2->dec_hw_cap_initialized & HW_CAP_DEC_MASK) == HW_CAP_DEC_MASK)
+		return;
+
+	for (dcore_id = 0 ; dcore_id < NUM_OF_DCORES ; dcore_id++)
+		for (dec_id = 0 ; dec_id < NUM_OF_DEC_PER_DCORE ; dec_id++) {
+			dec_bit = dcore_id * NUM_OF_DEC_PER_DCORE + dec_id;
+
+			if (!(hdev->asic_prop.decoder_enabled_mask & BIT(dec_bit)))
+				continue;
+
+			base_addr =  mmDCORE0_DEC0_CMD_BASE +
+					BRDG_CTRL_BLOCK_OFFSET +
+					dcore_id * DCORE_OFFSET +
+					dec_id * DCORE_VDEC_OFFSET;
+
+			gaudi2_init_vdec_brdg_ctrl(hdev, base_addr, dec_bit);
+
+			gaudi2->dec_hw_cap_initialized |= BIT_ULL(HW_CAP_DEC_SHIFT + dec_bit);
+		}
+
+	for (dec_id = 0 ; dec_id < NUM_OF_PCIE_VDEC ; dec_id++) {
+		dec_bit = PCIE_DEC_SHIFT + dec_id;
+		if (!(hdev->asic_prop.decoder_enabled_mask & BIT(dec_bit)))
+			continue;
+
+		base_addr = mmPCIE_DEC0_CMD_BASE + BRDG_CTRL_BLOCK_OFFSET +
+				dec_id * DCORE_VDEC_OFFSET;
+
+		gaudi2_init_vdec_brdg_ctrl(hdev, base_addr, dec_bit);
+
+		gaudi2->dec_hw_cap_initialized |= BIT_ULL(HW_CAP_DEC_SHIFT + dec_bit);
+	}
+}
+
+static int gaudi2_mmu_update_asid_hop0_addr(struct hl_device *hdev,
+					u32 stlb_base, u32 asid, u64 phys_addr)
+{
+	u32 status, timeout_usec;
+	int rc;
+
+	if (hdev->pldm || !hdev->pdev)
+		timeout_usec = GAUDI2_PLDM_MMU_TIMEOUT_USEC;
+	else
+		timeout_usec = MMU_CONFIG_TIMEOUT_USEC;
+
+	WREG32(stlb_base + STLB_ASID_OFFSET, asid);
+	WREG32(stlb_base + STLB_HOP0_PA43_12_OFFSET, phys_addr >> MMU_HOP0_PA43_12_SHIFT);
+	WREG32(stlb_base + STLB_HOP0_PA63_44_OFFSET, phys_addr >> MMU_HOP0_PA63_44_SHIFT);
+	WREG32(stlb_base + STLB_BUSY_OFFSET, 0x80000000);
+
+	rc = hl_poll_timeout(
+		hdev,
+		stlb_base + STLB_BUSY_OFFSET,
+		status,
+		!(status & 0x80000000),
+		1000,
+		timeout_usec);
+
+	if (rc) {
+		dev_err(hdev->dev, "Timeout during MMU hop0 config of asid %d\n", asid);
+		return rc;
+	}
+
+	return 0;
+}
+
+static void gaudi2_mmu_send_invalidate_cache_cmd(struct hl_device *hdev, u32 stlb_base,
+					u32 start_offset, u32 inv_start_val,
+					u32 flags)
+{
+	/* clear PMMU mem line cache (only needed in mmu range invalidation) */
+	if (flags & MMU_OP_CLEAR_MEMCACHE)
+		WREG32(mmPMMU_HBW_STLB_MEM_CACHE_INVALIDATION, 0x1);
+
+	if (flags & MMU_OP_SKIP_LOW_CACHE_INV)
+		return;
+
+	WREG32(stlb_base + start_offset, inv_start_val);
+}
+
+static int gaudi2_mmu_invalidate_cache_status_poll(struct hl_device *hdev, u32 stlb_base,
+						struct gaudi2_cache_invld_params *inv_params)
+{
+	u32 status, timeout_usec, start_offset;
+	int rc;
+
+	timeout_usec = (hdev->pldm) ? GAUDI2_PLDM_MMU_TIMEOUT_USEC :
+					GAUDI2_MMU_CACHE_INV_TIMEOUT_USEC;
+
+	/* poll PMMU mem line cache (only needed in mmu range invalidation) */
+	if (inv_params->flags & MMU_OP_CLEAR_MEMCACHE) {
+		rc = hl_poll_timeout(
+			hdev,
+			mmPMMU_HBW_STLB_MEM_CACHE_INV_STATUS,
+			status,
+			status & 0x1,
+			1000,
+			timeout_usec);
+
+		if (rc)
+			return rc;
+
+		/* Need to manually reset the status to 0 */
+		WREG32(mmPMMU_HBW_STLB_MEM_CACHE_INV_STATUS, 0x0);
+	}
+
+	/* Lower cache does not work with cache lines, hence we can skip its
+	 * invalidation upon map and invalidate only upon unmap
+	 */
+	if (inv_params->flags & MMU_OP_SKIP_LOW_CACHE_INV)
+		return 0;
+
+	start_offset = inv_params->range_invalidation ?
+			STLB_RANGE_CACHE_INVALIDATION_OFFSET : STLB_INV_ALL_START_OFFSET;
+
+	rc = hl_poll_timeout(
+		hdev,
+		stlb_base + start_offset,
+		status,
+		!(status & 0x1),
+		1000,
+		timeout_usec);
+
+	return rc;
+}
+
+bool gaudi2_is_hmmu_enabled(struct hl_device *hdev, int dcore_id, int hmmu_id)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	u32 hw_cap;
+
+	hw_cap = HW_CAP_DCORE0_DMMU0 << (NUM_OF_HMMU_PER_DCORE * dcore_id + hmmu_id);
+
+	if (gaudi2->hw_cap_initialized & hw_cap)
+		return true;
+
+	return false;
+}
+
+/* this function shall be called only for HMMUs for which capability bit is set */
+static inline u32 get_hmmu_stlb_base(int dcore_id, int hmmu_id)
+{
+	u32 offset;
+
+	offset =  (u32) (dcore_id * DCORE_OFFSET + hmmu_id * DCORE_HMMU_OFFSET);
+	return (u32)(mmDCORE0_HMMU0_STLB_BASE + offset);
+}
+
+static void gaudi2_mmu_invalidate_cache_trigger(struct hl_device *hdev, u32 stlb_base,
+						struct gaudi2_cache_invld_params *inv_params)
+{
+	u32 start_offset;
+
+	if (inv_params->range_invalidation) {
+		/* Set the addresses range
+		 * Note: that the start address we set in register, is not included in
+		 * the range of the invalidation, by design.
+		 * that's why we need to set lower address than the one we actually
+		 * want to be included in the range invalidation.
+		 */
+		u64 start = inv_params->start_va - 1;
+
+		start_offset = STLB_RANGE_CACHE_INVALIDATION_OFFSET;
+
+		WREG32(stlb_base + STLB_RANGE_INV_START_LSB_OFFSET,
+				start >> MMU_RANGE_INV_VA_LSB_SHIFT);
+
+		WREG32(stlb_base + STLB_RANGE_INV_START_MSB_OFFSET,
+				start >> MMU_RANGE_INV_VA_MSB_SHIFT);
+
+		WREG32(stlb_base + STLB_RANGE_INV_END_LSB_OFFSET,
+				inv_params->end_va >> MMU_RANGE_INV_VA_LSB_SHIFT);
+
+		WREG32(stlb_base + STLB_RANGE_INV_END_MSB_OFFSET,
+				inv_params->end_va >> MMU_RANGE_INV_VA_MSB_SHIFT);
+	} else {
+		start_offset = STLB_INV_ALL_START_OFFSET;
+	}
+
+	gaudi2_mmu_send_invalidate_cache_cmd(hdev, stlb_base, start_offset,
+						inv_params->inv_start_val, inv_params->flags);
+}
+
+static inline void gaudi2_hmmu_invalidate_cache_trigger(struct hl_device *hdev,
+						int dcore_id, int hmmu_id,
+						struct gaudi2_cache_invld_params *inv_params)
+{
+	u32 stlb_base = get_hmmu_stlb_base(dcore_id, hmmu_id);
+
+	gaudi2_mmu_invalidate_cache_trigger(hdev, stlb_base, inv_params);
+}
+
+static inline int gaudi2_hmmu_invalidate_cache_status_poll(struct hl_device *hdev,
+						int dcore_id, int hmmu_id,
+						struct gaudi2_cache_invld_params *inv_params)
+{
+	u32 stlb_base = get_hmmu_stlb_base(dcore_id, hmmu_id);
+
+	return gaudi2_mmu_invalidate_cache_status_poll(hdev, stlb_base, inv_params);
+}
+
+static int gaudi2_hmmus_invalidate_cache(struct hl_device *hdev,
+						struct gaudi2_cache_invld_params *inv_params)
+{
+	int dcore_id, hmmu_id;
+
+	/* first send all invalidation commands */
+	for (dcore_id = 0 ; dcore_id < NUM_OF_DCORES ; dcore_id++) {
+		for (hmmu_id = 0 ; hmmu_id < NUM_OF_HMMU_PER_DCORE ; hmmu_id++) {
+			if (!gaudi2_is_hmmu_enabled(hdev, dcore_id, hmmu_id))
+				continue;
+
+			gaudi2_hmmu_invalidate_cache_trigger(hdev, dcore_id, hmmu_id, inv_params);
+		}
+	}
+
+	/* next, poll all invalidations status */
+	for (dcore_id = 0 ; dcore_id < NUM_OF_DCORES ; dcore_id++) {
+		for (hmmu_id = 0 ; hmmu_id < NUM_OF_HMMU_PER_DCORE ; hmmu_id++) {
+			int rc;
+
+			if (!gaudi2_is_hmmu_enabled(hdev, dcore_id, hmmu_id))
+				continue;
+
+			rc = gaudi2_hmmu_invalidate_cache_status_poll(hdev, dcore_id, hmmu_id,
+										inv_params);
+			if (rc)
+				return rc;
+		}
+	}
+
+	return 0;
+}
+
+static int gaudi2_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard, u32 flags)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	struct gaudi2_cache_invld_params invld_params;
+	int rc = 0;
+
+	if (hdev->reset_info.hard_reset_pending)
+		return rc;
+
+	invld_params.range_invalidation = false;
+	invld_params.inv_start_val = 1;
+
+	if ((flags & MMU_OP_USERPTR) && (gaudi2->hw_cap_initialized & HW_CAP_PMMU)) {
+		invld_params.flags = flags;
+		gaudi2_mmu_invalidate_cache_trigger(hdev, mmPMMU_HBW_STLB_BASE, &invld_params);
+		rc = gaudi2_mmu_invalidate_cache_status_poll(hdev, mmPMMU_HBW_STLB_BASE,
+										&invld_params);
+	} else if (flags & MMU_OP_PHYS_PACK) {
+		invld_params.flags = 0;
+		rc = gaudi2_hmmus_invalidate_cache(hdev, &invld_params);
+	}
+
+	return rc;
+}
+
+static int gaudi2_mmu_invalidate_cache_range(struct hl_device *hdev, bool is_hard,
+				u32 flags, u32 asid, u64 va, u64 size)
+{
+	struct gaudi2_cache_invld_params invld_params = {0};
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	u64 start_va, end_va;
+	u32 inv_start_val;
+	int rc = 0;
+
+	if (hdev->reset_info.hard_reset_pending)
+		return 0;
+
+	inv_start_val = (1 << MMU_RANGE_INV_EN_SHIFT |
+			1 << MMU_RANGE_INV_ASID_EN_SHIFT |
+			asid << MMU_RANGE_INV_ASID_SHIFT);
+	start_va = va;
+	end_va = start_va + size;
+
+	if ((flags & MMU_OP_USERPTR) && (gaudi2->hw_cap_initialized & HW_CAP_PMMU)) {
+		/* As range invalidation does not support zero address we will
+		 * do full invalidation in this case
+		 */
+		if (start_va) {
+			invld_params.range_invalidation = true;
+			invld_params.start_va = start_va;
+			invld_params.end_va = end_va;
+			invld_params.inv_start_val = inv_start_val;
+			invld_params.flags = flags | MMU_OP_CLEAR_MEMCACHE;
+		} else {
+			invld_params.range_invalidation = false;
+			invld_params.inv_start_val = 1;
+			invld_params.flags = flags;
+		}
+
+
+		gaudi2_mmu_invalidate_cache_trigger(hdev, mmPMMU_HBW_STLB_BASE, &invld_params);
+		rc = gaudi2_mmu_invalidate_cache_status_poll(hdev, mmPMMU_HBW_STLB_BASE,
+										&invld_params);
+		if (rc)
+			return rc;
+
+	} else if (flags & MMU_OP_PHYS_PACK) {
+		invld_params.start_va = gaudi2_mmu_scramble_addr(hdev, start_va);
+		invld_params.end_va = gaudi2_mmu_scramble_addr(hdev, end_va);
+		invld_params.inv_start_val = inv_start_val;
+		invld_params.flags = flags;
+		rc = gaudi2_hmmus_invalidate_cache(hdev, &invld_params);
+	}
+
+	return rc;
+}
+
+static int gaudi2_mmu_update_hop0_addr(struct hl_device *hdev, u32 stlb_base,
+									bool host_resident_pgt)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	u64 hop0_addr;
+	u32 asid, max_asid = prop->max_asid;
+	int rc;
+
+	/* it takes too much time to init all of the ASIDs on palladium */
+	if (hdev->pldm)
+		max_asid = min((u32) 8, max_asid);
+
+	for (asid = 0 ; asid < max_asid ; asid++) {
+		if (host_resident_pgt)
+			hop0_addr = hdev->mmu_priv.hr.mmu_asid_hop0[asid].phys_addr;
+		else
+			hop0_addr = prop->mmu_pgt_addr + (asid * prop->dmmu.hop_table_size);
+
+		rc = gaudi2_mmu_update_asid_hop0_addr(hdev, stlb_base, asid, hop0_addr);
+		if (rc) {
+			dev_err(hdev->dev, "failed to set hop0 addr for asid %d\n", asid);
+			return rc;
+		}
+	}
+
+	return 0;
+}
+
+static int gaudi2_mmu_init_common(struct hl_device *hdev, u32 mmu_base, u32 stlb_base,
+								bool host_resident_pgt)
+{
+	u32 status, timeout_usec;
+	int rc;
+
+	if (hdev->pldm || !hdev->pdev)
+		timeout_usec = GAUDI2_PLDM_MMU_TIMEOUT_USEC;
+	else
+		timeout_usec = GAUDI2_MMU_CACHE_INV_TIMEOUT_USEC;
+
+	WREG32(stlb_base + STLB_INV_ALL_START_OFFSET, 1);
+
+	rc = hl_poll_timeout(
+		hdev,
+		stlb_base + STLB_SRAM_INIT_OFFSET,
+		status,
+		!status,
+		1000,
+		timeout_usec);
+
+	if (rc)
+		dev_notice_ratelimited(hdev->dev, "Timeout when waiting for MMU SRAM init\n");
+
+	rc = gaudi2_mmu_update_hop0_addr(hdev, stlb_base, host_resident_pgt);
+	if (rc)
+		return rc;
+
+	WREG32(mmu_base + MMU_BYPASS_OFFSET, 0);
+
+	rc = hl_poll_timeout(
+		hdev,
+		stlb_base + STLB_INV_ALL_START_OFFSET,
+		status,
+		!status,
+		1000,
+		timeout_usec);
+
+	if (rc)
+		dev_notice_ratelimited(hdev->dev, "Timeout when waiting for MMU invalidate all\n");
+
+	WREG32(mmu_base + MMU_ENABLE_OFFSET, 1);
+
+	return rc;
+}
+
+static int gaudi2_pci_mmu_init(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	u32 mmu_base, stlb_base;
+	int rc;
+
+	if (gaudi2->hw_cap_initialized & HW_CAP_PMMU)
+		return 0;
+
+	mmu_base = mmPMMU_HBW_MMU_BASE;
+	stlb_base = mmPMMU_HBW_STLB_BASE;
+
+	RMWREG32_SHIFTED(stlb_base + STLB_HOP_CONFIGURATION_OFFSET,
+		(0 << PMMU_HBW_STLB_HOP_CONFIGURATION_FIRST_HOP_SHIFT) |
+		(5 << PMMU_HBW_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_SMALL_P_SHIFT) |
+		(4 << PMMU_HBW_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_LARGE_P_SHIFT) |
+		(5 << PMMU_HBW_STLB_HOP_CONFIGURATION_LAST_HOP_SHIFT) |
+		(5 << PMMU_HBW_STLB_HOP_CONFIGURATION_FOLLOWER_HOP_SHIFT),
+		PMMU_HBW_STLB_HOP_CONFIGURATION_FIRST_HOP_MASK |
+		PMMU_HBW_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_SMALL_P_MASK |
+		PMMU_HBW_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_LARGE_P_MASK |
+		PMMU_HBW_STLB_HOP_CONFIGURATION_LAST_HOP_MASK |
+		PMMU_HBW_STLB_HOP_CONFIGURATION_FOLLOWER_HOP_MASK);
+
+	WREG32(stlb_base + STLB_LL_LOOKUP_MASK_63_32_OFFSET, 0);
+
+	if (PAGE_SIZE == SZ_64K) {
+		/* Set page sizes to 64K on hop5 and 16M on hop4 + enable 8 bit hops */
+		RMWREG32_SHIFTED(mmu_base + MMU_STATIC_MULTI_PAGE_SIZE_OFFSET,
+			FIELD_PREP(DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP5_PAGE_SIZE_MASK, 4) |
+			FIELD_PREP(DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP4_PAGE_SIZE_MASK, 3) |
+			FIELD_PREP(
+				DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_CFG_8_BITS_HOP_MODE_EN_MASK,
+				1),
+			DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP5_PAGE_SIZE_MASK |
+			DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP4_PAGE_SIZE_MASK |
+			DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_CFG_8_BITS_HOP_MODE_EN_MASK);
+	}
+
+	WREG32(mmu_base + MMU_SPI_SEI_MASK_OFFSET, GAUDI2_PMMU_SPI_SEI_ENABLE_MASK);
+
+	rc = gaudi2_mmu_init_common(hdev, mmu_base, stlb_base, prop->pmmu.host_resident);
+	if (rc)
+		return rc;
+
+	gaudi2->hw_cap_initialized |= HW_CAP_PMMU;
+
+	return 0;
+}
+
+static int gaudi2_dcore_hmmu_init(struct hl_device *hdev, int dcore_id,
+				int hmmu_id)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	u32 offset, mmu_base, stlb_base, hw_cap;
+	u8 dmmu_seq;
+	int rc;
+
+	dmmu_seq = NUM_OF_HMMU_PER_DCORE * dcore_id + hmmu_id;
+	hw_cap = HW_CAP_DCORE0_DMMU0 << dmmu_seq;
+
+	/*
+	 * return if DMMU is already initialized or if it's not out of
+	 * isolation (due to cluster binning)
+	 */
+	if ((gaudi2->hw_cap_initialized & hw_cap) || !(prop->hmmu_hif_enabled_mask & BIT(dmmu_seq)))
+		return 0;
+
+	offset = (u32) (dcore_id * DCORE_OFFSET + hmmu_id * DCORE_HMMU_OFFSET);
+	mmu_base = mmDCORE0_HMMU0_MMU_BASE + offset;
+	stlb_base = mmDCORE0_HMMU0_STLB_BASE + offset;
+
+	RMWREG32(mmu_base + MMU_STATIC_MULTI_PAGE_SIZE_OFFSET, 5 /* 64MB */,
+			MMU_STATIC_MULTI_PAGE_SIZE_HOP4_PAGE_SIZE_MASK);
+
+	RMWREG32_SHIFTED(stlb_base + STLB_HOP_CONFIGURATION_OFFSET,
+		FIELD_PREP(DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_HOP_MASK, 0) |
+		FIELD_PREP(DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_SMALL_P_MASK, 3) |
+		FIELD_PREP(DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_LARGE_P_MASK, 3) |
+		FIELD_PREP(DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LAST_HOP_MASK, 3) |
+		FIELD_PREP(DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FOLLOWER_HOP_MASK, 3),
+			DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_HOP_MASK |
+			DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_SMALL_P_MASK |
+			DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_LARGE_P_MASK |
+			DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LAST_HOP_MASK |
+			DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FOLLOWER_HOP_MASK);
+
+	RMWREG32(stlb_base + STLB_HOP_CONFIGURATION_OFFSET, 1,
+			STLB_HOP_CONFIGURATION_ONLY_LARGE_PAGE_MASK);
+
+	WREG32(mmu_base + MMU_SPI_SEI_MASK_OFFSET, GAUDI2_HMMU_SPI_SEI_ENABLE_MASK);
+
+	rc = gaudi2_mmu_init_common(hdev, mmu_base, stlb_base, prop->dmmu.host_resident);
+	if (rc)
+		return rc;
+
+	gaudi2->hw_cap_initialized |= hw_cap;
+
+	return 0;
+}
+
+static int gaudi2_hbm_mmu_init(struct hl_device *hdev)
+{
+	int rc, dcore_id, hmmu_id;
+
+	for (dcore_id = 0 ; dcore_id < NUM_OF_DCORES ; dcore_id++)
+		for (hmmu_id = 0 ; hmmu_id < NUM_OF_HMMU_PER_DCORE; hmmu_id++) {
+			rc = gaudi2_dcore_hmmu_init(hdev, dcore_id, hmmu_id);
+			if (rc)
+				return rc;
+		}
+
+	return 0;
+}
+
+static int gaudi2_mmu_init(struct hl_device *hdev)
+{
+	int rc;
+
+	rc = gaudi2_pci_mmu_init(hdev);
+	if (rc)
+		return rc;
+
+	rc = gaudi2_hbm_mmu_init(hdev);
+	if (rc)
+		return rc;
+
+	return 0;
+}
+
+static int gaudi2_hw_init(struct hl_device *hdev)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	int rc;
+
+	/* Let's mark in the H/W that we have reached this point. We check
+	 * this value in the reset_before_init function to understand whether
+	 * we need to reset the chip before doing H/W init. This register is
+	 * cleared by the H/W upon H/W reset
+	 */
+	WREG32(mmHW_STATE, HL_DEVICE_HW_STATE_DIRTY);
+
+	/* Perform read from the device to make sure device is up */
+	RREG32(mmHW_STATE);
+
+	/* If iATU is done by FW, the HBM bar ALWAYS points to DRAM_PHYS_BASE.
+	 * So we set it here and if anyone tries to move it later to
+	 * a different address, there will be an error
+	 */
+	if (hdev->asic_prop.iatu_done_by_fw)
+		gaudi2->dram_bar_cur_addr = DRAM_PHYS_BASE;
+
+	/*
+	 * Before pushing u-boot/linux to device, need to set the hbm bar to
+	 * base address of dram
+	 */
+	if (gaudi2_set_hbm_bar_base(hdev, DRAM_PHYS_BASE) == U64_MAX) {
+		dev_err(hdev->dev, "failed to map HBM bar to DRAM base address\n");
+		return -EIO;
+	}
+
+	rc = gaudi2_init_cpu(hdev);
+	if (rc) {
+		dev_err(hdev->dev, "failed to initialize CPU\n");
+		return rc;
+	}
+
+	gaudi2_init_scrambler_hbm(hdev);
+	gaudi2_init_kdma(hdev);
+
+	rc = gaudi2_init_cpu_queues(hdev, GAUDI2_CPU_TIMEOUT_USEC);
+	if (rc) {
+		dev_err(hdev->dev, "failed to initialize CPU H/W queues %d\n", rc);
+		return rc;
+	}
+
+	rc = gaudi2->cpucp_info_get(hdev);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to get cpucp info\n");
+		return rc;
+	}
+
+	rc = gaudi2_mmu_init(hdev);
+	if (rc)
+		return rc;
+
+	gaudi2_init_pdma(hdev);
+	gaudi2_init_edma(hdev);
+	gaudi2_init_sm(hdev);
+	gaudi2_init_tpc(hdev);
+	gaudi2_init_mme(hdev);
+	gaudi2_init_rotator(hdev);
+	gaudi2_init_dec(hdev);
+	gaudi2_enable_timestamp(hdev);
+
+	rc = gaudi2_coresight_init(hdev);
+	if (rc)
+		goto disable_queues;
+
+	rc = gaudi2_enable_msix(hdev);
+	if (rc)
+		goto disable_queues;
+
+	/* Perform read from the device to flush all configuration */
+	RREG32(mmHW_STATE);
+
+	return 0;
+
+disable_queues:
+	gaudi2_disable_dma_qmans(hdev);
+	gaudi2_disable_mme_qmans(hdev);
+	gaudi2_disable_tpc_qmans(hdev);
+	gaudi2_disable_rot_qmans(hdev);
+	gaudi2_disable_nic_qmans(hdev);
+
+	gaudi2_disable_timestamp(hdev);
+
+	return rc;
+}
+
+/**
+ * gaudi2_send_hard_reset_cmd - common function to handle reset
+ *
+ * @hdev: pointer to the habanalabs device structure
+ *
+ * This function handles the various possible scenarios for reset.
+ * It considers if reset is handled by driver\FW and what FW components are loaded
+ */
+static void gaudi2_send_hard_reset_cmd(struct hl_device *hdev)
+{
+	struct cpu_dyn_regs *dyn_regs = &hdev->fw_loader.dynamic_loader.comm_desc.cpu_dyn_regs;
+	bool heartbeat_reset, preboot_only, cpu_initialized = false;
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	u32 cpu_boot_status;
+
+	preboot_only = (hdev->fw_loader.fw_comp_loaded == FW_TYPE_PREBOOT_CPU);
+	heartbeat_reset = (hdev->reset_info.curr_reset_cause == HL_RESET_CAUSE_HEARTBEAT);
+
+	/*
+	 * Handle corner case where failure was at cpu management app load,
+	 * and driver didn't detect any failure while loading the FW,
+	 * then at such scenario driver will send only HALT_MACHINE
+	 * and no one will respond to this request since FW already back to preboot
+	 * and it cannot handle such cmd.
+	 * In this case next time the management app loads it'll check on events register
+	 * which will still have the halt indication, and will reboot the device.
+	 * The solution is to let preboot clear all relevant registers before next boot
+	 * once driver send COMMS_RST_DEV.
+	 */
+	cpu_boot_status = RREG32(mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS);
+
+	if (gaudi2 && (gaudi2->hw_cap_initialized & HW_CAP_CPU) &&
+			(cpu_boot_status == CPU_BOOT_STATUS_SRAM_AVAIL))
+		cpu_initialized = true;
+
+	/*
+	 * when Linux/Bootfit exist this write to the SP can be interpreted in 2 ways:
+	 * 1. FW reset: FW initiate the reset sequence
+	 * 2. driver reset: FW will start HALT sequence (the preparations for the
+	 *                  reset but not the reset itself as it is not implemented
+	 *                  on their part) and LKD will wait to let FW complete the
+	 *                  sequence before issuing the reset
+	 */
+	if (!preboot_only && cpu_initialized) {
+		WREG32(le32_to_cpu(dyn_regs->gic_host_halt_irq),
+			gaudi2_irq_map_table[GAUDI2_EVENT_CPU_HALT_MACHINE].cpu_id);
+
+		msleep(GAUDI2_CPU_RESET_WAIT_MSEC);
+	}
+
+	/*
+	 * When working with preboot (without Linux/Boot fit) we can
+	 * communicate only using the COMMS commands to issue halt/reset.
+	 *
+	 * For the case in which we are working with Linux/Bootfit this is a hail-mary
+	 * attempt to revive the card in the small chance that the f/w has
+	 * experienced a watchdog event, which caused it to return back to preboot.
+	 * In that case, triggering reset through GIC won't help. We need to
+	 * trigger the reset as if Linux wasn't loaded.
+	 *
+	 * We do it only if the reset cause was HB, because that would be the
+	 * indication of such an event.
+	 *
+	 * In case watchdog hasn't expired but we still got HB, then this won't
+	 * do any damage.
+	 */
+
+	if (heartbeat_reset || preboot_only || !cpu_initialized) {
+		if (hdev->asic_prop.hard_reset_done_by_fw)
+			hl_fw_ask_hard_reset_without_linux(hdev);
+		else
+			hl_fw_ask_halt_machine_without_linux(hdev);
+	}
+}
+
+/**
+ * gaudi2_execute_hard_reset - execute hard reset by driver/FW
+ *
+ * @hdev: pointer to the habanalabs device structure
+ *
+ * This function executes hard reset based on if driver/FW should do the reset
+ */
+static void gaudi2_execute_hard_reset(struct hl_device *hdev)
+{
+	if (hdev->asic_prop.hard_reset_done_by_fw) {
+		gaudi2_send_hard_reset_cmd(hdev);
+		return;
+	}
+
+	/* Set device to handle FLR by H/W as we will put the device
+	 * CPU to halt mode
+	 */
+	WREG32(mmPCIE_AUX_FLR_CTRL,
+			(PCIE_AUX_FLR_CTRL_HW_CTRL_MASK | PCIE_AUX_FLR_CTRL_INT_MASK_MASK));
+
+	gaudi2_send_hard_reset_cmd(hdev);
+
+	WREG32(mmPSOC_RESET_CONF_SW_ALL_RST, 1);
+}
+
+/**
+ * gaudi2_execute_soft_reset - execute soft reset by driver/FW
+ *
+ * @hdev: pointer to the habanalabs device structure
+ * @driver_performs_reset: true if driver should perform reset instead of f/w.
+ * @poll_timeout_us: time to wait for response from f/w.
+ *
+ * This function executes soft reset based on if driver/FW should do the reset
+ */
+static int gaudi2_execute_soft_reset(struct hl_device *hdev, bool driver_performs_reset,
+						u32 poll_timeout_us)
+{
+	if (!driver_performs_reset)
+		return hl_fw_send_soft_reset(hdev);
+
+	/* Block access to engines, QMANs and SM during reset, these
+	 * RRs will be reconfigured after soft reset.
+	 * PCIE_MSIX is left unsecured to allow NIC packets processing during the reset.
+	 */
+	gaudi2_write_rr_to_all_lbw_rtrs(hdev, RR_TYPE_LONG, NUM_LONG_LBW_RR - 1,
+					mmDCORE0_TPC0_QM_DCCM_BASE, mmPCIE_MSIX_BASE);
+
+	gaudi2_write_rr_to_all_lbw_rtrs(hdev, RR_TYPE_LONG, NUM_LONG_LBW_RR - 2,
+				mmPCIE_MSIX_BASE + HL_BLOCK_SIZE,
+				mmPCIE_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE + HL_BLOCK_SIZE);
+
+	WREG32(mmPSOC_RESET_CONF_SOFT_RST, 1);
+	return 0;
+}
+
+static void gaudi2_poll_btm_indication(struct hl_device *hdev, u32 poll_timeout_us)
+{
+	int i, rc = 0;
+	u32 reg_val;
+
+	/* We poll the BTM done indication multiple times after reset due to
+	 * a HW errata 'GAUDI2_0300'
+	 */
+	for (i = 0 ; i < GAUDI2_RESET_POLL_CNT ; i++)
+		rc = hl_poll_timeout(
+			hdev,
+			mmPSOC_GLOBAL_CONF_BTM_FSM,
+			reg_val,
+			reg_val == 0,
+			1000,
+			poll_timeout_us);
+
+	if (rc)
+		dev_err(hdev->dev, "Timeout while waiting for device to reset 0x%x\n", reg_val);
+}
+
+static int gaudi2_hw_fini(struct hl_device *hdev, bool hard_reset, bool fw_reset)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	u32 poll_timeout_us, reset_sleep_ms;
+	bool driver_performs_reset = false;
+	int rc;
+
+	if (hdev->pldm) {
+		reset_sleep_ms = hard_reset ? GAUDI2_PLDM_HRESET_TIMEOUT_MSEC :
+						GAUDI2_PLDM_SRESET_TIMEOUT_MSEC;
+		poll_timeout_us = GAUDI2_PLDM_RESET_POLL_TIMEOUT_USEC;
+	} else {
+		reset_sleep_ms = GAUDI2_RESET_TIMEOUT_MSEC;
+		poll_timeout_us = GAUDI2_RESET_POLL_TIMEOUT_USEC;
+	}
+
+	if (fw_reset)
+		goto skip_reset;
+
+	gaudi2_reset_arcs(hdev);
+
+	if (hard_reset) {
+		driver_performs_reset = !hdev->asic_prop.hard_reset_done_by_fw;
+		gaudi2_execute_hard_reset(hdev);
+	} else {
+		/*
+		 * As we have to support also work with preboot only (which does not supports
+		 * soft reset) we have to make sure that security is disabled before letting driver
+		 * do the reset. user shall control the BFE flags to avoid asking soft reset in
+		 * secured device with preboot only.
+		 */
+		driver_performs_reset = (hdev->fw_components == FW_TYPE_PREBOOT_CPU &&
+							!hdev->asic_prop.fw_security_enabled);
+		rc = gaudi2_execute_soft_reset(hdev, driver_performs_reset, poll_timeout_us);
+		if (rc)
+			return rc;
+	}
+
+skip_reset:
+	if (driver_performs_reset || hard_reset) {
+		/*
+		 * Instead of waiting for BTM indication we should wait for preboot ready:
+		 * Consider the below scenario:
+		 * 1. FW update is being triggered
+		 *        - setting the dirty bit
+		 * 2. hard reset will be triggered due to the dirty bit
+		 * 3. FW initiates the reset:
+		 *        - dirty bit cleared
+		 *        - BTM indication cleared
+		 *        - preboot ready indication cleared
+		 * 4. during hard reset:
+		 *        - BTM indication will be set
+		 *        - BIST test performed and another reset triggered
+		 * 5. only after this reset the preboot will set the preboot ready
+		 *
+		 * when polling on BTM indication alone we can lose sync with FW while trying to
+		 * communicate with FW that is during reset.
+		 * to overcome this we will always wait to preboot ready indication
+		 */
+
+		/* without this sleep reset will not work */
+		msleep(reset_sleep_ms);
+
+		if (hdev->fw_components & FW_TYPE_PREBOOT_CPU)
+			hl_fw_wait_preboot_ready(hdev);
+		else
+			gaudi2_poll_btm_indication(hdev, poll_timeout_us);
+	}
+
+	if (!gaudi2)
+		return 0;
+
+	gaudi2->dec_hw_cap_initialized &= ~(HW_CAP_DEC_MASK);
+	gaudi2->tpc_hw_cap_initialized &= ~(HW_CAP_TPC_MASK);
+
+	/*
+	 * Clear NIC capability mask in order for driver to re-configure
+	 * NIC QMANs. NIC ports will not be re-configured during soft
+	 * reset as we call gaudi2_nic_init only during hard reset
+	 */
+	gaudi2->nic_hw_cap_initialized &= ~(HW_CAP_NIC_MASK);
+
+	if (hard_reset) {
+		gaudi2->hw_cap_initialized &=
+			~(HW_CAP_DRAM | HW_CAP_CLK_GATE | HW_CAP_HBM_SCRAMBLER_MASK |
+			HW_CAP_PMMU | HW_CAP_CPU | HW_CAP_CPU_Q |
+			HW_CAP_SRAM_SCRAMBLER | HW_CAP_DMMU_MASK |
+			HW_CAP_PDMA_MASK | HW_CAP_EDMA_MASK | HW_CAP_KDMA |
+			HW_CAP_MME_MASK | HW_CAP_ROT_MASK);
+
+		memset(gaudi2->events_stat, 0, sizeof(gaudi2->events_stat));
+	} else {
+		gaudi2->hw_cap_initialized &=
+			~(HW_CAP_CLK_GATE | HW_CAP_HBM_SCRAMBLER_SW_RESET |
+			HW_CAP_PDMA_MASK | HW_CAP_EDMA_MASK | HW_CAP_MME_MASK |
+			HW_CAP_ROT_MASK);
+	}
+	return 0;
+}
+
+static int gaudi2_suspend(struct hl_device *hdev)
+{
+	return hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_DISABLE_PCI_ACCESS, 0x0);
+}
+
+static int gaudi2_resume(struct hl_device *hdev)
+{
+	return gaudi2_init_iatu(hdev);
+}
+
+static int gaudi2_mmap(struct hl_device *hdev, struct vm_area_struct *vma,
+		void *cpu_addr, dma_addr_t dma_addr, size_t size)
+{
+	int rc;
+
+	vm_flags_set(vma, VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP |
+			VM_DONTCOPY | VM_NORESERVE);
+
+#ifdef _HAS_DMA_MMAP_COHERENT
+	/*
+	 * If dma_alloc_coherent() returns a vmalloc address, set VM_MIXEDMAP
+	 * so vm_insert_page() can handle it safely. Without this, the kernel
+	 * may BUG_ON due to VM_PFNMAP.
+	 */
+	if (is_vmalloc_addr(cpu_addr))
+		vm_flags_set(vma, VM_MIXEDMAP);
+
+	rc = dma_mmap_coherent(hdev->dev, vma, cpu_addr, dma_addr, size);
+	if (rc)
+		dev_err(hdev->dev, "dma_mmap_coherent error %d", rc);
+
+#else
+
+	rc = remap_pfn_range(vma, vma->vm_start,
+				virt_to_phys(cpu_addr) >> PAGE_SHIFT,
+				size, vma->vm_page_prot);
+	if (rc)
+		dev_err(hdev->dev, "remap_pfn_range error %d", rc);
+
+#endif
+
+	return rc;
+}
+
+static bool gaudi2_is_queue_enabled(struct hl_device *hdev, u32 hw_queue_id)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	u64 hw_cap_mask = 0;
+	u64 hw_tpc_cap_bit = 0;
+	u64 hw_nic_cap_bit = 0;
+	u64 hw_test_cap_bit = 0;
+
+	switch (hw_queue_id) {
+	case GAUDI2_QUEUE_ID_PDMA_0_0:
+	case GAUDI2_QUEUE_ID_PDMA_0_1:
+	case GAUDI2_QUEUE_ID_PDMA_1_0:
+		hw_cap_mask = HW_CAP_PDMA_MASK;
+		break;
+	case GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0...GAUDI2_QUEUE_ID_DCORE0_EDMA_1_3:
+		hw_test_cap_bit = HW_CAP_EDMA_SHIFT +
+			((hw_queue_id - GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0) >> 2);
+		break;
+	case GAUDI2_QUEUE_ID_DCORE1_EDMA_0_0...GAUDI2_QUEUE_ID_DCORE1_EDMA_1_3:
+		hw_test_cap_bit = HW_CAP_EDMA_SHIFT + NUM_OF_EDMA_PER_DCORE +
+			((hw_queue_id - GAUDI2_QUEUE_ID_DCORE1_EDMA_0_0) >> 2);
+		break;
+	case GAUDI2_QUEUE_ID_DCORE2_EDMA_0_0...GAUDI2_QUEUE_ID_DCORE2_EDMA_1_3:
+		hw_test_cap_bit = HW_CAP_EDMA_SHIFT + 2 * NUM_OF_EDMA_PER_DCORE +
+			((hw_queue_id - GAUDI2_QUEUE_ID_DCORE2_EDMA_0_0) >> 2);
+		break;
+	case GAUDI2_QUEUE_ID_DCORE3_EDMA_0_0...GAUDI2_QUEUE_ID_DCORE3_EDMA_1_3:
+		hw_test_cap_bit = HW_CAP_EDMA_SHIFT + 3 * NUM_OF_EDMA_PER_DCORE +
+			((hw_queue_id - GAUDI2_QUEUE_ID_DCORE3_EDMA_0_0) >> 2);
+		break;
+
+	case GAUDI2_QUEUE_ID_DCORE0_MME_0_0 ... GAUDI2_QUEUE_ID_DCORE0_MME_0_3:
+		hw_test_cap_bit = HW_CAP_MME_SHIFT;
+		break;
+
+	case GAUDI2_QUEUE_ID_DCORE1_MME_0_0 ... GAUDI2_QUEUE_ID_DCORE1_MME_0_3:
+		hw_test_cap_bit = HW_CAP_MME_SHIFT + 1;
+		break;
+
+	case GAUDI2_QUEUE_ID_DCORE2_MME_0_0 ... GAUDI2_QUEUE_ID_DCORE2_MME_0_3:
+		hw_test_cap_bit = HW_CAP_MME_SHIFT + 2;
+		break;
+
+	case GAUDI2_QUEUE_ID_DCORE3_MME_0_0 ... GAUDI2_QUEUE_ID_DCORE3_MME_0_3:
+		hw_test_cap_bit = HW_CAP_MME_SHIFT + 3;
+		break;
+
+	case GAUDI2_QUEUE_ID_DCORE0_TPC_0_0 ... GAUDI2_QUEUE_ID_DCORE0_TPC_5_3:
+		hw_tpc_cap_bit = HW_CAP_TPC_SHIFT +
+			((hw_queue_id - GAUDI2_QUEUE_ID_DCORE0_TPC_0_0) >> 2);
+
+		/* special case where cap bit refers to the first queue id */
+		if (!hw_tpc_cap_bit)
+			return !!(gaudi2->tpc_hw_cap_initialized & BIT_ULL(0));
+		break;
+
+	case GAUDI2_QUEUE_ID_DCORE1_TPC_0_0 ... GAUDI2_QUEUE_ID_DCORE1_TPC_5_3:
+		hw_tpc_cap_bit = HW_CAP_TPC_SHIFT + NUM_OF_TPC_PER_DCORE +
+			((hw_queue_id - GAUDI2_QUEUE_ID_DCORE1_TPC_0_0) >> 2);
+		break;
+
+	case GAUDI2_QUEUE_ID_DCORE2_TPC_0_0 ... GAUDI2_QUEUE_ID_DCORE2_TPC_5_3:
+		hw_tpc_cap_bit = HW_CAP_TPC_SHIFT + (2 * NUM_OF_TPC_PER_DCORE) +
+			((hw_queue_id - GAUDI2_QUEUE_ID_DCORE2_TPC_0_0) >> 2);
+		break;
+
+	case GAUDI2_QUEUE_ID_DCORE3_TPC_0_0 ... GAUDI2_QUEUE_ID_DCORE3_TPC_5_3:
+		hw_tpc_cap_bit = HW_CAP_TPC_SHIFT + (3 * NUM_OF_TPC_PER_DCORE) +
+			((hw_queue_id - GAUDI2_QUEUE_ID_DCORE3_TPC_0_0) >> 2);
+		break;
+
+	case GAUDI2_QUEUE_ID_DCORE0_TPC_6_0 ... GAUDI2_QUEUE_ID_DCORE0_TPC_6_3:
+		hw_tpc_cap_bit = HW_CAP_TPC_SHIFT + (4 * NUM_OF_TPC_PER_DCORE);
+		break;
+
+	case GAUDI2_QUEUE_ID_ROT_0_0 ... GAUDI2_QUEUE_ID_ROT_1_3:
+		hw_test_cap_bit = HW_CAP_ROT_SHIFT + ((hw_queue_id - GAUDI2_QUEUE_ID_ROT_0_0) >> 2);
+		break;
+
+	case GAUDI2_QUEUE_ID_NIC_0_0 ... GAUDI2_QUEUE_ID_NIC_23_3:
+		hw_nic_cap_bit = HW_CAP_NIC_SHIFT + ((hw_queue_id - GAUDI2_QUEUE_ID_NIC_0_0) >> 2);
+
+		/* special case where cap bit refers to the first queue id */
+		if (!hw_nic_cap_bit)
+			return !!(gaudi2->nic_hw_cap_initialized & BIT_ULL(0));
+		break;
+
+	case GAUDI2_QUEUE_ID_CPU_PQ:
+		return !!(gaudi2->hw_cap_initialized & HW_CAP_CPU_Q);
+
+	default:
+		return false;
+	}
+
+	if (hw_tpc_cap_bit)
+		return  !!(gaudi2->tpc_hw_cap_initialized & BIT_ULL(hw_tpc_cap_bit));
+
+	if (hw_nic_cap_bit)
+		return  !!(gaudi2->nic_hw_cap_initialized & BIT_ULL(hw_nic_cap_bit));
+
+	if (hw_test_cap_bit)
+		hw_cap_mask = BIT_ULL(hw_test_cap_bit);
+
+	return !!(gaudi2->hw_cap_initialized & hw_cap_mask);
+}
+
+static bool gaudi2_is_arc_enabled(struct hl_device *hdev, u64 arc_id)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+
+	switch (arc_id) {
+	case CPU_ID_SCHED_ARC0 ... CPU_ID_SCHED_ARC5:
+	case CPU_ID_MME_QMAN_ARC0...CPU_ID_ROT_QMAN_ARC1:
+		return !!(gaudi2->active_hw_arc & BIT_ULL(arc_id));
+
+	case CPU_ID_TPC_QMAN_ARC0...CPU_ID_TPC_QMAN_ARC24:
+		return !!(gaudi2->active_tpc_arc & BIT_ULL(arc_id - CPU_ID_TPC_QMAN_ARC0));
+
+	case CPU_ID_NIC_QMAN_ARC0...CPU_ID_NIC_QMAN_ARC23:
+		return !!(gaudi2->active_nic_arc & BIT_ULL(arc_id - CPU_ID_NIC_QMAN_ARC0));
+
+	default:
+		return false;
+	}
+}
+
+static void gaudi2_clr_arc_id_cap(struct hl_device *hdev, u64 arc_id)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+
+	switch (arc_id) {
+	case CPU_ID_SCHED_ARC0 ... CPU_ID_SCHED_ARC5:
+	case CPU_ID_MME_QMAN_ARC0...CPU_ID_ROT_QMAN_ARC1:
+		gaudi2->active_hw_arc &= ~(BIT_ULL(arc_id));
+		break;
+
+	case CPU_ID_TPC_QMAN_ARC0...CPU_ID_TPC_QMAN_ARC24:
+		gaudi2->active_tpc_arc &= ~(BIT_ULL(arc_id - CPU_ID_TPC_QMAN_ARC0));
+		break;
+
+	case CPU_ID_NIC_QMAN_ARC0...CPU_ID_NIC_QMAN_ARC23:
+		gaudi2->active_nic_arc &= ~(BIT_ULL(arc_id - CPU_ID_NIC_QMAN_ARC0));
+		break;
+
+	default:
+		return;
+	}
+}
+
+static void gaudi2_set_arc_id_cap(struct hl_device *hdev, u64 arc_id)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+
+	switch (arc_id) {
+	case CPU_ID_SCHED_ARC0 ... CPU_ID_SCHED_ARC5:
+	case CPU_ID_MME_QMAN_ARC0...CPU_ID_ROT_QMAN_ARC1:
+		gaudi2->active_hw_arc |= BIT_ULL(arc_id);
+		break;
+
+	case CPU_ID_TPC_QMAN_ARC0...CPU_ID_TPC_QMAN_ARC24:
+		gaudi2->active_tpc_arc |= BIT_ULL(arc_id - CPU_ID_TPC_QMAN_ARC0);
+		break;
+
+	case CPU_ID_NIC_QMAN_ARC0...CPU_ID_NIC_QMAN_ARC23:
+		gaudi2->active_nic_arc |= BIT_ULL(arc_id - CPU_ID_NIC_QMAN_ARC0);
+		break;
+
+	default:
+		return;
+	}
+}
+
+static void gaudi2_ring_doorbell(struct hl_device *hdev, u32 hw_queue_id, u32 pi)
+{
+	struct cpu_dyn_regs *dyn_regs = &hdev->fw_loader.dynamic_loader.comm_desc.cpu_dyn_regs;
+	u32 pq_offset, reg_base, db_reg_offset, db_value;
+
+	if (hw_queue_id != GAUDI2_QUEUE_ID_CPU_PQ) {
+		/*
+		 * QMAN has 4 successive PQ_PI registers, 1 for each of the QMAN PQs.
+		 * Masking the H/W queue ID with 0x3 extracts the QMAN internal PQ
+		 * number.
+		 */
+		pq_offset = (hw_queue_id & 0x3) * 4;
+		reg_base = gaudi2_qm_blocks_bases[hw_queue_id];
+		db_reg_offset = reg_base + QM_PQ_PI_0_OFFSET + pq_offset;
+	} else {
+		db_reg_offset = mmCPU_IF_PF_PQ_PI;
+	}
+
+	db_value = pi;
+
+	/* ring the doorbell */
+	WREG32(db_reg_offset, db_value);
+
+	if (hw_queue_id == GAUDI2_QUEUE_ID_CPU_PQ) {
+		/* make sure device CPU will read latest data from host */
+		mb();
+		WREG32(le32_to_cpu(dyn_regs->gic_host_pi_upd_irq),
+			gaudi2_irq_map_table[GAUDI2_EVENT_CPU_PI_UPDATE].cpu_id);
+	}
+}
+
+static void gaudi2_pqe_write(struct hl_device *hdev, __le64 *pqe, struct hl_bd *bd)
+{
+	__le64 *pbd = (__le64 *) bd;
+
+	/* The QMANs are on the host memory so a simple copy suffice */
+	pqe[0] = pbd[0];
+	pqe[1] = pbd[1];
+}
+
+static void *gaudi2_dma_alloc_coherent(struct hl_device *hdev, size_t size,
+				dma_addr_t *dma_handle, gfp_t flags)
+{
+	return dma_alloc_coherent(&hdev->pdev->dev, size, dma_handle, flags);
+}
+
+static void gaudi2_dma_free_coherent(struct hl_device *hdev, size_t size,
+				void *cpu_addr, dma_addr_t dma_handle)
+{
+	dma_free_coherent(&hdev->pdev->dev, size, cpu_addr, dma_handle);
+}
+
+static int gaudi2_send_cpu_message(struct hl_device *hdev, u32 *msg, u16 len,
+				u32 timeout, u64 *result)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+
+	if (!(gaudi2->hw_cap_initialized & HW_CAP_CPU_Q)) {
+		if (result)
+			*result = 0;
+		return 0;
+	}
+
+	if (!timeout)
+		timeout = GAUDI2_MSG_TO_CPU_TIMEOUT_USEC;
+
+	return hl_fw_send_cpu_message(hdev, GAUDI2_QUEUE_ID_CPU_PQ, msg, len, timeout, result);
+}
+
+static void *gaudi2_dma_pool_zalloc(struct hl_device *hdev, size_t size,
+				gfp_t mem_flags, dma_addr_t *dma_handle)
+{
+	if (size > GAUDI2_DMA_POOL_BLK_SIZE)
+		return NULL;
+
+	return dma_pool_zalloc(hdev->dma_pool, mem_flags, dma_handle);
+}
+
+static void gaudi2_dma_pool_free(struct hl_device *hdev, void *vaddr, dma_addr_t dma_addr)
+{
+	dma_pool_free(hdev->dma_pool, vaddr, dma_addr);
+}
+
+static void *gaudi2_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, size_t size,
+						dma_addr_t *dma_handle)
+{
+	return hl_fw_cpu_accessible_dma_pool_alloc(hdev, size, dma_handle);
+}
+
+static void gaudi2_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size, void *vaddr)
+{
+	hl_fw_cpu_accessible_dma_pool_free(hdev, size, vaddr);
+}
+
+static int gaudi2_validate_cb_address(struct hl_device *hdev, struct hl_cs_parser *parser)
+{
+	struct asic_fixed_properties *asic_prop = &hdev->asic_prop;
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+
+	if (!gaudi2_is_queue_enabled(hdev, parser->hw_queue_id)) {
+		dev_err(hdev->dev, "h/w queue %s is disabled\n",
+		GAUDI2_QUEUE_ID_TO_STR(parser->hw_queue_id));
+		return -EINVAL;
+	}
+
+	/* Just check if CB address is valid */
+
+	if (hl_mem_area_inside_range((u64) (uintptr_t) parser->user_cb,
+					parser->user_cb_size,
+					asic_prop->sram_user_base_address,
+					asic_prop->sram_end_address))
+		return 0;
+
+	if (hl_mem_area_inside_range((u64) (uintptr_t) parser->user_cb,
+					parser->user_cb_size,
+					asic_prop->dram_user_base_address,
+					asic_prop->dram_end_address))
+		return 0;
+
+	if ((gaudi2->hw_cap_initialized & HW_CAP_DMMU_MASK) &&
+		hl_mem_area_inside_range((u64) (uintptr_t) parser->user_cb,
+						parser->user_cb_size,
+						asic_prop->dmmu.start_addr,
+						asic_prop->dmmu.end_addr))
+		return 0;
+
+	if (gaudi2->hw_cap_initialized & HW_CAP_PMMU) {
+		if (hl_mem_area_inside_range((u64) (uintptr_t) parser->user_cb,
+					parser->user_cb_size,
+					asic_prop->pmmu.start_addr,
+					asic_prop->pmmu.end_addr) ||
+			hl_mem_area_inside_range(
+					(u64) (uintptr_t) parser->user_cb,
+					parser->user_cb_size,
+					asic_prop->pmmu_huge.start_addr,
+					asic_prop->pmmu_huge.end_addr))
+			return 0;
+
+	} else if (gaudi2_host_phys_addr_valid((u64) (uintptr_t) parser->user_cb)) {
+		if (!hdev->pdev)
+			return 0;
+
+		if (!device_iommu_mapped(&hdev->pdev->dev))
+			return 0;
+	}
+
+	dev_err(hdev->dev, "CB address %p + 0x%x for internal QMAN is not valid\n",
+		parser->user_cb, parser->user_cb_size);
+
+	return -EFAULT;
+}
+
+static int gaudi2_cs_parser(struct hl_device *hdev, struct hl_cs_parser *parser)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+
+	if (!parser->is_kernel_allocated_cb)
+		return gaudi2_validate_cb_address(hdev, parser);
+
+	if (!(gaudi2->hw_cap_initialized & HW_CAP_PMMU)) {
+		dev_err(hdev->dev, "PMMU not initialized - Unsupported mode in Gaudi2\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int gaudi2_send_heartbeat(struct hl_device *hdev)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+
+	if (!(gaudi2->hw_cap_initialized & HW_CAP_CPU_Q))
+		return 0;
+
+	return hl_fw_send_heartbeat(hdev);
+}
+
+/* This is an internal helper function, used to update the KDMA mmu props.
+ * Should be called with a proper kdma lock.
+ */
+static void gaudi2_kdma_set_mmbp_asid(struct hl_device *hdev,
+					   bool mmu_bypass, u32 asid)
+{
+	u32 rw_asid, rw_mmu_bp;
+
+	rw_asid = (asid << ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_RD_SHIFT) |
+		      (asid << ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_WR_SHIFT);
+
+	rw_mmu_bp = (!!mmu_bypass << ARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP_RD_SHIFT) |
+			(!!mmu_bypass << ARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP_WR_SHIFT);
+
+	WREG32(mmARC_FARM_KDMA_CTX_AXUSER_HB_ASID, rw_asid);
+	WREG32(mmARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP, rw_mmu_bp);
+}
+
+static void gaudi2_arm_cq_monitor(struct hl_device *hdev, u32 sob_id, u32 mon_id, u32 cq_id,
+						u32 mon_payload, u32 sync_value)
+{
+	u32 sob_offset, mon_offset, sync_group_id, mode, mon_arm;
+	u8 mask;
+
+	sob_offset = sob_id * 4;
+	mon_offset = mon_id * 4;
+
+	/* Reset the SOB value */
+	WREG32(mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 + sob_offset, 0);
+
+	/* Configure this address with CQ_ID 0 because CQ_EN is set */
+	WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 + mon_offset, cq_id);
+
+	/* Configure this address with CS index because CQ_EN is set */
+	WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_0 + mon_offset, mon_payload);
+
+	sync_group_id = sob_id / 8;
+	mask = ~(1 << (sob_id & 0x7));
+	mode = 1; /* comparison mode is "equal to" */
+
+	mon_arm = FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_MON_ARM_SOD_MASK, sync_value);
+	mon_arm |= FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_MON_ARM_SOP_MASK, mode);
+	mon_arm |= FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_MON_ARM_MASK_MASK, mask);
+	mon_arm |= FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_MON_ARM_SID_MASK, sync_group_id);
+	WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_0 + mon_offset, mon_arm);
+}
+
+/* This is an internal helper function used by gaudi2_send_job_to_kdma only */
+static int gaudi2_send_job_to_kdma(struct hl_device *hdev,
+					u64 src_addr, u64 dst_addr,
+					u32 size, bool is_memset)
+{
+	u32 comp_val, commit_mask, *polling_addr, timeout, status = 0;
+	struct hl_cq_entry *cq_base;
+	struct hl_cq *cq;
+	u64 comp_addr;
+	int rc;
+
+	gaudi2_arm_cq_monitor(hdev, GAUDI2_RESERVED_SOB_KDMA_COMPLETION,
+				GAUDI2_RESERVED_MON_KDMA_COMPLETION,
+				GAUDI2_RESERVED_CQ_KDMA_COMPLETION, 1, 1);
+
+	comp_addr = CFG_BASE + mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 +
+			(GAUDI2_RESERVED_SOB_KDMA_COMPLETION * sizeof(u32));
+
+	comp_val = FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_INC_MASK, 1) |
+			FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_VAL_MASK, 1);
+
+	WREG32(mmARC_FARM_KDMA_CTX_SRC_BASE_LO, lower_32_bits(src_addr));
+	WREG32(mmARC_FARM_KDMA_CTX_SRC_BASE_HI, upper_32_bits(src_addr));
+	WREG32(mmARC_FARM_KDMA_CTX_DST_BASE_LO, lower_32_bits(dst_addr));
+	WREG32(mmARC_FARM_KDMA_CTX_DST_BASE_HI, upper_32_bits(dst_addr));
+	WREG32(mmARC_FARM_KDMA_CTX_WR_COMP_ADDR_LO, lower_32_bits(comp_addr));
+	WREG32(mmARC_FARM_KDMA_CTX_WR_COMP_ADDR_HI, upper_32_bits(comp_addr));
+	WREG32(mmARC_FARM_KDMA_CTX_WR_COMP_WDATA, comp_val);
+	WREG32(mmARC_FARM_KDMA_CTX_DST_TSIZE_0, size);
+
+	commit_mask = FIELD_PREP(ARC_FARM_KDMA_CTX_COMMIT_LIN_MASK, 1) |
+				FIELD_PREP(ARC_FARM_KDMA_CTX_COMMIT_WR_COMP_EN_MASK, 1);
+
+	if (is_memset)
+		commit_mask |= FIELD_PREP(ARC_FARM_KDMA_CTX_COMMIT_MEM_SET_MASK, 1);
+
+	WREG32(mmARC_FARM_KDMA_CTX_COMMIT, commit_mask);
+
+	/* Wait for completion */
+	cq = &hdev->completion_queue[GAUDI2_RESERVED_CQ_KDMA_COMPLETION];
+	cq_base = cq->kernel_address;
+	polling_addr = (u32 *)&cq_base[cq->ci];
+
+	if (hdev->pldm)
+		/* for each 1MB 20 second of timeout */
+		timeout = ((size / SZ_1M) + 1) * USEC_PER_SEC * 20;
+	else
+		timeout = KDMA_TIMEOUT_USEC;
+
+	/* Polling */
+	rc = hl_poll_timeout_memory(
+			hdev,
+			polling_addr,
+			status,
+			(status == 1),
+			1000,
+			timeout,
+			true);
+
+	*polling_addr = 0;
+
+	if (rc) {
+		dev_err(hdev->dev, "Timeout while waiting for KDMA to be idle\n");
+		WREG32(mmARC_FARM_KDMA_CFG_1, 1 << ARC_FARM_KDMA_CFG_1_HALT_SHIFT);
+		return rc;
+	}
+
+	cq->ci = hl_cq_inc_ptr(cq->ci);
+
+	return 0;
+}
+
+static void gaudi2_memset_device_lbw(struct hl_device *hdev, u32 addr, u32 size, u32 val)
+{
+	u32 i;
+
+	for (i = 0 ; i < size ; i += sizeof(u32))
+		WREG32(addr + i, val);
+}
+
+static void gaudi2_qman_set_test_mode(struct hl_device *hdev, u32 hw_queue_id, bool enable)
+{
+	u32 reg_base = gaudi2_qm_blocks_bases[hw_queue_id];
+
+	if (enable) {
+		WREG32(reg_base + QM_GLBL_PROT_OFFSET, QMAN_MAKE_TRUSTED_TEST_MODE);
+		WREG32(reg_base + QM_PQC_CFG_OFFSET, 0);
+	} else {
+		WREG32(reg_base + QM_GLBL_PROT_OFFSET, QMAN_MAKE_TRUSTED);
+		WREG32(reg_base + QM_PQC_CFG_OFFSET, 1 << PDMA0_QM_PQC_CFG_EN_SHIFT);
+	}
+}
+
+static inline u32 gaudi2_test_queue_hw_queue_id_to_sob_id(struct hl_device *hdev, u32 hw_queue_id)
+{
+	return hdev->asic_prop.first_available_user_sob[0] +
+				hw_queue_id - GAUDI2_QUEUE_ID_PDMA_0_0;
+}
+
+static void gaudi2_test_queue_clear(struct hl_device *hdev, u32 hw_queue_id)
+{
+	u32 sob_offset = gaudi2_test_queue_hw_queue_id_to_sob_id(hdev, hw_queue_id) * 4;
+	u32 sob_addr = mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 + sob_offset;
+
+	/* Reset the SOB value */
+	WREG32(sob_addr, 0);
+}
+
+static int gaudi2_test_queue_send_msg_short(struct hl_device *hdev, u32 hw_queue_id, u32 sob_val,
+					    struct gaudi2_queues_test_info *msg_info)
+{
+	u32 sob_offset =  gaudi2_test_queue_hw_queue_id_to_sob_id(hdev, hw_queue_id) * 4;
+	u32 tmp, sob_base = 1;
+	struct packet_msg_short *msg_short_pkt = msg_info->kern_addr;
+	size_t pkt_size = sizeof(struct packet_msg_short);
+	int rc;
+
+	tmp = (PACKET_MSG_SHORT << GAUDI2_PKT_CTL_OPCODE_SHIFT) |
+		(1 << GAUDI2_PKT_CTL_EB_SHIFT) |
+		(1 << GAUDI2_PKT_CTL_MB_SHIFT) |
+		(sob_base << GAUDI2_PKT_SHORT_CTL_BASE_SHIFT) |
+		(sob_offset << GAUDI2_PKT_SHORT_CTL_ADDR_SHIFT);
+
+	msg_short_pkt->value = cpu_to_le32(sob_val);
+	msg_short_pkt->ctl = cpu_to_le32(tmp);
+
+	rc = hl_hw_queue_send_cb_no_cmpl(hdev, hw_queue_id, pkt_size, msg_info->dma_addr);
+	if (rc)
+		dev_err(hdev->dev,
+			"Failed to send msg_short packet to H/W queue %s\n",
+			GAUDI2_QUEUE_ID_TO_STR(hw_queue_id));
+
+	return rc;
+}
+
+static int gaudi2_test_queue_wait_completion(struct hl_device *hdev, u32 hw_queue_id, u32 sob_val)
+{
+	u32 sob_offset = gaudi2_test_queue_hw_queue_id_to_sob_id(hdev, hw_queue_id) * 4;
+	u32 sob_addr = mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 + sob_offset;
+	u32 timeout_usec, tmp;
+	int rc;
+
+	if (hdev->pldm)
+		timeout_usec = GAUDI2_PLDM_TEST_QUEUE_WAIT_USEC;
+	else
+		timeout_usec = GAUDI2_TEST_QUEUE_WAIT_USEC;
+
+	rc = hl_poll_timeout(
+			hdev,
+			sob_addr,
+			tmp,
+			(tmp == sob_val),
+			1000,
+			timeout_usec);
+
+	if (rc == -ETIMEDOUT) {
+		dev_err(hdev->dev, "H/W queue %s test failed (SOB_OBJ_0 == 0x%x)\n",
+			GAUDI2_QUEUE_ID_TO_STR(hw_queue_id), tmp);
+		rc = -EIO;
+	}
+
+	return rc;
+}
+
+static int gaudi2_test_cpu_queue(struct hl_device *hdev)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+
+	/*
+	 * check capability here as send_cpu_message() won't update the result
+	 * value if no capability
+	 */
+	if (!(gaudi2->hw_cap_initialized & HW_CAP_CPU_Q))
+		return 0;
+
+	return hl_fw_test_cpu_queue(hdev);
+}
+
+static int gaudi2_test_queues(struct hl_device *hdev)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	struct gaudi2_queues_test_info *msg_info;
+	u32 sob_val = 0x5a5a;
+	int i, rc;
+
+	/* send test message on all enabled Qs */
+	for (i = GAUDI2_QUEUE_ID_PDMA_0_0 ; i < GAUDI2_QUEUE_ID_CPU_PQ; i++) {
+		if (!gaudi2_is_queue_enabled(hdev, i) || gaudi2_is_edma_queue_id(i))
+			continue;
+
+		msg_info = &gaudi2->queues_test_info[i - GAUDI2_QUEUE_ID_PDMA_0_0];
+		gaudi2_qman_set_test_mode(hdev, i, true);
+		gaudi2_test_queue_clear(hdev, i);
+		rc = gaudi2_test_queue_send_msg_short(hdev, i, sob_val, msg_info);
+		if (rc)
+			goto done;
+	}
+
+	rc = gaudi2_test_cpu_queue(hdev);
+	if (rc)
+		goto done;
+
+	/* verify that all messages were processed */
+	for (i = GAUDI2_QUEUE_ID_PDMA_0_0 ; i < GAUDI2_QUEUE_ID_CPU_PQ; i++) {
+		if (!gaudi2_is_queue_enabled(hdev, i) || gaudi2_is_edma_queue_id(i))
+			continue;
+
+		rc = gaudi2_test_queue_wait_completion(hdev, i, sob_val);
+		if (rc)
+			/* chip is not usable, no need for cleanups, just bail-out with error */
+			goto done;
+
+		gaudi2_test_queue_clear(hdev, i);
+		gaudi2_qman_set_test_mode(hdev, i, false);
+	}
+
+done:
+	return rc;
+}
+
+static int gaudi2_compute_reset_late_init(struct hl_device *hdev)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	size_t irq_arr_size;
+	int rc;
+
+	gaudi2_init_arcs(hdev);
+
+	rc = gaudi2_scrub_arcs_dccm(hdev);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to scrub arcs DCCM\n");
+		return rc;
+	}
+
+	gaudi2_init_security(hdev);
+
+	/* Unmask all IRQs since some could have been received during the soft reset */
+	irq_arr_size = gaudi2->num_of_valid_hw_events * sizeof(gaudi2->hw_events[0]);
+	return hl_fw_unmask_irq_arr(hdev, gaudi2->hw_events, irq_arr_size);
+}
+
+static bool gaudi2_get_edma_idle_status(struct hl_device *hdev, u64 *mask_arr, u8 mask_len,
+		struct engines_data *e)
+{
+	u32 qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts, dma_core_sts0, dma_core_sts1;
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	unsigned long *mask = (unsigned long *) mask_arr;
+	const char *edma_fmt = "%-6d%-6d%-9s%#-14x%#-15x%#x\n";
+	bool is_idle = true, is_eng_idle;
+	int engine_idx, i, j;
+	u64 offset;
+
+	if (e)
+		hl_engine_data_sprintf(e,
+			"\nCORE  EDMA  is_idle  QM_GLBL_STS0  DMA_CORE_STS0  DMA_CORE_STS1\n"
+			"----  ----  -------  ------------  -------------  -------------\n");
+
+	for (i = 0; i < NUM_OF_DCORES; i++) {
+		for (j = 0 ; j < NUM_OF_EDMA_PER_DCORE ; j++) {
+			int seq = i * NUM_OF_EDMA_PER_DCORE + j;
+
+			if (!(prop->edma_enabled_mask & BIT(seq)))
+				continue;
+
+			engine_idx = GAUDI2_DCORE0_ENGINE_ID_EDMA_0 +
+					i * GAUDI2_ENGINE_ID_DCORE_OFFSET + j;
+			offset = i * DCORE_OFFSET + j * DCORE_EDMA_OFFSET;
+
+			dma_core_sts0 = RREG32(mmDCORE0_EDMA0_CORE_STS0 + offset);
+			dma_core_sts1 = RREG32(mmDCORE0_EDMA0_CORE_STS1 + offset);
+
+			qm_glbl_sts0 = RREG32(mmDCORE0_EDMA0_QM_GLBL_STS0 + offset);
+			qm_glbl_sts1 = RREG32(mmDCORE0_EDMA0_QM_GLBL_STS1 + offset);
+			qm_cgm_sts = RREG32(mmDCORE0_EDMA0_QM_CGM_STS + offset);
+
+			is_eng_idle = IS_QM_IDLE(qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts) &&
+					IS_DMA_IDLE(dma_core_sts0) && !IS_DMA_HALTED(dma_core_sts1);
+			is_idle &= is_eng_idle;
+
+			if (mask && !is_eng_idle)
+				set_bit(engine_idx, mask);
+
+			if (e)
+				hl_engine_data_sprintf(e, edma_fmt, i, j, is_eng_idle ? "Y" : "N",
+							qm_glbl_sts0, dma_core_sts0, dma_core_sts1);
+		}
+	}
+
+	return is_idle;
+}
+
+static bool gaudi2_get_pdma_idle_status(struct hl_device *hdev, u64 *mask_arr, u8 mask_len,
+		struct engines_data *e)
+{
+	u32 qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts, dma_core_sts0, dma_core_sts1;
+	unsigned long *mask = (unsigned long *) mask_arr;
+	const char *pdma_fmt = "%-6d%-9s%#-14x%#-15x%#x\n";
+	bool is_idle = true, is_eng_idle;
+	int engine_idx, i;
+	u64 offset;
+
+	if (e)
+		hl_engine_data_sprintf(e,
+					"\nPDMA  is_idle  QM_GLBL_STS0  DMA_CORE_STS0  DMA_CORE_STS1\n"
+					"----  -------  ------------  -------------  -------------\n");
+
+	for (i = 0 ; i < NUM_OF_PDMA ; i++) {
+		engine_idx = GAUDI2_ENGINE_ID_PDMA_0 + i;
+		offset = i * PDMA_OFFSET;
+		dma_core_sts0 = RREG32(mmPDMA0_CORE_STS0 + offset);
+		dma_core_sts1 = RREG32(mmPDMA0_CORE_STS1 + offset);
+
+		qm_glbl_sts0 = RREG32(mmPDMA0_QM_GLBL_STS0 + offset);
+		qm_glbl_sts1 = RREG32(mmPDMA0_QM_GLBL_STS1 + offset);
+		qm_cgm_sts = RREG32(mmPDMA0_QM_CGM_STS + offset);
+
+		is_eng_idle = IS_QM_IDLE(qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts) &&
+				IS_DMA_IDLE(dma_core_sts0) && !IS_DMA_HALTED(dma_core_sts1);
+		is_idle &= is_eng_idle;
+
+		if (mask && !is_eng_idle)
+			set_bit(engine_idx, mask);
+
+		if (e)
+			hl_engine_data_sprintf(e, pdma_fmt, i, is_eng_idle ? "Y" : "N",
+						qm_glbl_sts0, dma_core_sts0, dma_core_sts1);
+	}
+
+	return is_idle;
+}
+
+static bool gaudi2_get_nic_idle_status(struct hl_device *hdev, u64 *mask_arr, u8 mask_len,
+		struct engines_data *e)
+{
+	unsigned long *mask = (unsigned long *) mask_arr;
+	const char *nic_fmt = "%-5d%-9s%#-14x%#-12x\n";
+	u32 qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts;
+	bool is_idle = true, is_eng_idle;
+	int engine_idx, i;
+	u64 offset = 0;
+
+	/* NIC, twelve macros in Full chip */
+	if (e && hdev->nic_ports_mask)
+		hl_engine_data_sprintf(e,
+					"\nNIC  is_idle  QM_GLBL_STS0  QM_CGM_STS\n"
+					"---  -------  ------------  ----------\n");
+
+	for (i = 0 ; i < NIC_NUMBER_OF_ENGINES ; i++) {
+		if (!(i & 1))
+			offset = i / 2 * NIC_OFFSET;
+		else
+			offset += NIC_QM_OFFSET;
+
+		if (!(hdev->nic_ports_mask & BIT(i)))
+			continue;
+
+		engine_idx = GAUDI2_ENGINE_ID_NIC0_0 + i;
+
+
+		qm_glbl_sts0 = RREG32(mmNIC0_QM0_GLBL_STS0 + offset);
+		qm_glbl_sts1 = RREG32(mmNIC0_QM0_GLBL_STS1 + offset);
+		qm_cgm_sts = RREG32(mmNIC0_QM0_CGM_STS + offset);
+
+		is_eng_idle = IS_QM_IDLE(qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts);
+		is_idle &= is_eng_idle;
+
+		if (mask && !is_eng_idle)
+			set_bit(engine_idx, mask);
+
+		if (e)
+			hl_engine_data_sprintf(e, nic_fmt, i, is_eng_idle ? "Y" : "N",
+						qm_glbl_sts0, qm_cgm_sts);
+	}
+
+	return is_idle;
+}
+
+static bool gaudi2_get_mme_idle_status(struct hl_device *hdev, u64 *mask_arr, u8 mask_len,
+		struct engines_data *e)
+{
+	u32 qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts, mme_arch_sts;
+	unsigned long *mask = (unsigned long *) mask_arr;
+	const char *mme_fmt = "%-5d%-6s%-9s%#-14x%#x\n";
+	bool is_idle = true, is_eng_idle;
+	int engine_idx, i;
+	u64 offset;
+
+	if (e)
+		hl_engine_data_sprintf(e,
+					"\nMME  Stub  is_idle  QM_GLBL_STS0  MME_ARCH_STATUS\n"
+					"---  ----  -------  ------------  ---------------\n");
+	/* MME, one per Dcore */
+	for (i = 0 ; i < NUM_OF_DCORES ; i++) {
+		engine_idx = GAUDI2_DCORE0_ENGINE_ID_MME + i * GAUDI2_ENGINE_ID_DCORE_OFFSET;
+		offset = i * DCORE_OFFSET;
+
+		qm_glbl_sts0 = RREG32(mmDCORE0_MME_QM_GLBL_STS0 + offset);
+		qm_glbl_sts1 = RREG32(mmDCORE0_MME_QM_GLBL_STS1 + offset);
+		qm_cgm_sts = RREG32(mmDCORE0_MME_QM_CGM_STS + offset);
+
+		is_eng_idle = IS_QM_IDLE(qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts);
+		is_idle &= is_eng_idle;
+
+		mme_arch_sts = RREG32(mmDCORE0_MME_CTRL_LO_ARCH_STATUS + offset);
+		is_eng_idle &= IS_MME_IDLE(mme_arch_sts);
+		is_idle &= is_eng_idle;
+
+		if (e)
+			hl_engine_data_sprintf(e, mme_fmt, i, "N",
+				is_eng_idle ? "Y" : "N",
+				qm_glbl_sts0,
+				mme_arch_sts);
+
+		if (mask && !is_eng_idle)
+			set_bit(engine_idx, mask);
+	}
+
+	return is_idle;
+}
+
+static void gaudi2_is_tpc_engine_idle(struct hl_device *hdev, int dcore, int inst, u32 offset,
+					struct iterate_module_ctx *ctx)
+{
+	struct gaudi2_tpc_idle_data *idle_data = ctx->data;
+	u32 tpc_cfg_sts, qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts;
+	bool is_eng_idle;
+	int engine_idx;
+
+	if ((dcore == 0) && (inst == (NUM_DCORE0_TPC - 1)))
+		engine_idx = GAUDI2_DCORE0_ENGINE_ID_TPC_6;
+	else
+		engine_idx = GAUDI2_DCORE0_ENGINE_ID_TPC_0 +
+				dcore * GAUDI2_ENGINE_ID_DCORE_OFFSET + inst;
+
+	tpc_cfg_sts = RREG32(mmDCORE0_TPC0_CFG_STATUS + offset);
+	qm_glbl_sts0 = RREG32(mmDCORE0_TPC0_QM_GLBL_STS0 + offset);
+	qm_glbl_sts1 = RREG32(mmDCORE0_TPC0_QM_GLBL_STS1 + offset);
+	qm_cgm_sts = RREG32(mmDCORE0_TPC0_QM_CGM_STS + offset);
+
+	is_eng_idle = IS_QM_IDLE(qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts) &&
+						IS_TPC_IDLE(tpc_cfg_sts);
+	*(idle_data->is_idle) &= is_eng_idle;
+
+	if (idle_data->mask && !is_eng_idle)
+		set_bit(engine_idx, idle_data->mask);
+
+	if (idle_data->e)
+		hl_engine_data_sprintf(idle_data->e,
+					idle_data->tpc_fmt, dcore, inst,
+					is_eng_idle ? "Y" : "N",
+					qm_glbl_sts0, qm_cgm_sts, tpc_cfg_sts);
+}
+
+static bool gaudi2_get_tpc_idle_status(struct hl_device *hdev, u64 *mask_arr, u8 mask_len,
+		struct engines_data *e)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	unsigned long *mask = (unsigned long *) mask_arr;
+	bool is_idle = true;
+
+	struct gaudi2_tpc_idle_data tpc_idle_data = {
+		.tpc_fmt = "%-6d%-5d%-9s%#-14x%#-12x%#x\n",
+		.e = e,
+		.mask = mask,
+		.is_idle = &is_idle,
+	};
+	struct iterate_module_ctx tpc_iter = {
+		.fn = &gaudi2_is_tpc_engine_idle,
+		.data = &tpc_idle_data,
+	};
+
+	if (e && prop->tpc_enabled_mask)
+		hl_engine_data_sprintf(e,
+			"\nCORE  TPC  is_idle  QM_GLBL_STS0  QM_CGM_STS  STATUS\n"
+			"----  ---  -------  ------------  ----------  ------\n");
+
+	gaudi2_iterate_tpcs(hdev, &tpc_iter);
+
+	return *tpc_idle_data.is_idle;
+}
+
+static bool gaudi2_get_decoder_idle_status(struct hl_device *hdev, u64 *mask_arr, u8 mask_len,
+		struct engines_data *e)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	unsigned long *mask = (unsigned long *) mask_arr;
+	const char *pcie_dec_fmt = "%-10d%-9s%#x\n";
+	const char *dec_fmt = "%-6d%-5d%-9s%#x\n";
+	bool is_idle = true, is_eng_idle;
+	u32 dec_swreg15, dec_enabled_bit;
+	int engine_idx, i, j;
+	u64 offset;
+
+	/* Decoders, two each Dcore and two shared PCIe decoders */
+	if (e && (prop->decoder_enabled_mask & (~PCIE_DEC_EN_MASK)))
+		hl_engine_data_sprintf(e,
+			"\nCORE  DEC  is_idle  VSI_CMD_SWREG15\n"
+			"----  ---  -------  ---------------\n");
+
+	for (i = 0 ; i < NUM_OF_DCORES ; i++) {
+		for (j = 0 ; j < NUM_OF_DEC_PER_DCORE ; j++) {
+			dec_enabled_bit = 1 << (i * NUM_OF_DEC_PER_DCORE + j);
+			if (!(prop->decoder_enabled_mask & dec_enabled_bit))
+				continue;
+
+			engine_idx = GAUDI2_DCORE0_ENGINE_ID_DEC_0 +
+					i * GAUDI2_ENGINE_ID_DCORE_OFFSET + j;
+			offset = i * DCORE_OFFSET + j * DCORE_DEC_OFFSET;
+
+			dec_swreg15 = RREG32(mmDCORE0_DEC0_CMD_SWREG15 + offset);
+			is_eng_idle = IS_DEC_IDLE(dec_swreg15);
+			is_idle &= is_eng_idle;
+
+			if (mask && !is_eng_idle)
+				set_bit(engine_idx, mask);
+
+			if (e)
+				hl_engine_data_sprintf(e, dec_fmt, i, j,
+							is_eng_idle ? "Y" : "N", dec_swreg15);
+		}
+	}
+
+	if (e && (prop->decoder_enabled_mask & PCIE_DEC_EN_MASK))
+		hl_engine_data_sprintf(e,
+			"\nPCIe DEC  is_idle  VSI_CMD_SWREG15\n"
+			"--------  -------  ---------------\n");
+
+	/* Check shared(PCIe) decoders */
+	for (i = 0 ; i < NUM_OF_DEC_PER_DCORE ; i++) {
+		dec_enabled_bit = PCIE_DEC_SHIFT + i;
+		if (!(prop->decoder_enabled_mask & BIT(dec_enabled_bit)))
+			continue;
+
+		engine_idx = GAUDI2_PCIE_ENGINE_ID_DEC_0 + i;
+		offset = i * DCORE_DEC_OFFSET;
+		dec_swreg15 = RREG32(mmPCIE_DEC0_CMD_SWREG15 + offset);
+		is_eng_idle = IS_DEC_IDLE(dec_swreg15);
+		is_idle &= is_eng_idle;
+
+		if (mask && !is_eng_idle)
+			set_bit(engine_idx, mask);
+
+		if (e)
+			hl_engine_data_sprintf(e, pcie_dec_fmt, i,
+						is_eng_idle ? "Y" : "N", dec_swreg15);
+	}
+
+	return is_idle;
+}
+
+static bool gaudi2_get_rotator_idle_status(struct hl_device *hdev, u64 *mask_arr, u8 mask_len,
+		struct engines_data *e)
+{
+	const char *rot_fmt = "%-6d%-5d%-9s%#-14x%#-14x%#x\n";
+	unsigned long *mask = (unsigned long *) mask_arr;
+	u32 qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts;
+	bool is_idle = true, is_eng_idle;
+	int engine_idx, i;
+	u64 offset;
+
+	if (e)
+		hl_engine_data_sprintf(e,
+			"\nCORE  ROT  is_idle  QM_GLBL_STS0  QM_GLBL_STS1  QM_CGM_STS\n"
+			"----  ---  -------  ------------  ------------  ----------\n");
+
+	for (i = 0 ; i < NUM_OF_ROT ; i++) {
+		engine_idx = GAUDI2_ENGINE_ID_ROT_0 + i;
+
+		offset = i * ROT_OFFSET;
+
+		qm_glbl_sts0 = RREG32(mmROT0_QM_GLBL_STS0 + offset);
+		qm_glbl_sts1 = RREG32(mmROT0_QM_GLBL_STS1 + offset);
+		qm_cgm_sts = RREG32(mmROT0_QM_CGM_STS + offset);
+
+		is_eng_idle = IS_QM_IDLE(qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts);
+		is_idle &= is_eng_idle;
+
+		if (mask && !is_eng_idle)
+			set_bit(engine_idx, mask);
+
+		if (e)
+			hl_engine_data_sprintf(e, rot_fmt, i, 0, is_eng_idle ? "Y" : "N",
+						qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts);
+	}
+
+	return is_idle;
+}
+
+static bool gaudi2_is_device_idle(struct hl_device *hdev, u64 *mask_arr, u8 mask_len,
+					struct engines_data *e)
+{
+	bool is_idle = true;
+
+	is_idle &= gaudi2_get_edma_idle_status(hdev, mask_arr, mask_len, e);
+	is_idle &= gaudi2_get_pdma_idle_status(hdev, mask_arr, mask_len, e);
+	is_idle &= gaudi2_get_nic_idle_status(hdev, mask_arr, mask_len, e);
+	is_idle &= gaudi2_get_mme_idle_status(hdev, mask_arr, mask_len, e);
+	is_idle &= gaudi2_get_tpc_idle_status(hdev, mask_arr, mask_len, e);
+	is_idle &= gaudi2_get_decoder_idle_status(hdev, mask_arr, mask_len, e);
+	is_idle &= gaudi2_get_rotator_idle_status(hdev, mask_arr, mask_len, e);
+
+	return is_idle;
+}
+
+static void gaudi2_hw_queues_lock(struct hl_device *hdev)
+	__acquires(&gaudi2->hw_queues_lock)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+
+	spin_lock(&gaudi2->hw_queues_lock);
+}
+
+static void gaudi2_hw_queues_unlock(struct hl_device *hdev)
+	__releases(&gaudi2->hw_queues_lock)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+
+	spin_unlock(&gaudi2->hw_queues_lock);
+}
+
+static u32 gaudi2_get_pci_id(struct hl_device *hdev)
+{
+	return hdev->pdev->device;
+}
+
+static int gaudi2_get_eeprom_data(struct hl_device *hdev, void *data, size_t max_size)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+
+	if (!(gaudi2->hw_cap_initialized & HW_CAP_CPU_Q))
+		return 0;
+
+	return hl_fw_get_eeprom_data(hdev, data, max_size);
+}
+
+static void gaudi2_update_eq_ci(struct hl_device *hdev, u32 val)
+{
+	WREG32(mmCPU_IF_EQ_RD_OFFS, val);
+}
+
+static void *gaudi2_get_events_stat(struct hl_device *hdev, bool aggregate, u32 *size)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+
+	if (aggregate) {
+		*size = (u32) sizeof(gaudi2->events_stat_aggregate);
+		return gaudi2->events_stat_aggregate;
+	}
+
+	*size = (u32) sizeof(gaudi2->events_stat);
+	return gaudi2->events_stat;
+}
+
+static void gaudi2_mmu_vdec_dcore_prepare(struct hl_device *hdev, int dcore_id,
+				int dcore_vdec_id, u32 rw_asid, u32 rw_mmu_bp)
+{
+	u32 offset = (mmDCORE0_VDEC1_BRDG_CTRL_BASE - mmDCORE0_VDEC0_BRDG_CTRL_BASE) *
+			dcore_vdec_id + DCORE_OFFSET * dcore_id;
+
+	WREG32(mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_MMU_BP + offset, rw_mmu_bp);
+	WREG32(mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_ASID + offset, rw_asid);
+
+	WREG32(mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_MMU_BP + offset, rw_mmu_bp);
+	WREG32(mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_ASID + offset, rw_asid);
+
+	WREG32(mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_MMU_BP + offset, rw_mmu_bp);
+	WREG32(mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_ASID + offset, rw_asid);
+
+	WREG32(mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_MMU_BP + offset, rw_mmu_bp);
+	WREG32(mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_ASID + offset, rw_asid);
+
+	WREG32(mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_MMU_BP + offset, rw_mmu_bp);
+	WREG32(mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_ASID + offset, rw_asid);
+}
+
+static void gaudi2_mmu_dcore_prepare(struct hl_device *hdev, int dcore_id, u32 asid)
+{
+	u32 rw_asid = (asid << ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_RD_SHIFT) |
+			(asid << ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_WR_SHIFT);
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	u32 dcore_offset = dcore_id * DCORE_OFFSET;
+	u32 vdec_id, i, ports_offset, reg_val;
+	u8 edma_seq_base;
+
+	/* EDMA */
+	edma_seq_base = dcore_id * NUM_OF_EDMA_PER_DCORE;
+	if (prop->edma_enabled_mask & BIT(edma_seq_base)) {
+		WREG32(mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_MMU_BP + dcore_offset, 0);
+		WREG32(mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_ASID + dcore_offset, rw_asid);
+		WREG32(mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_MMU_BP + dcore_offset, 0);
+		WREG32(mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_ASID + dcore_offset, rw_asid);
+	}
+
+	if (prop->edma_enabled_mask & BIT(edma_seq_base + 1)) {
+		WREG32(mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_MMU_BP + dcore_offset, 0);
+		WREG32(mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_ASID + dcore_offset, rw_asid);
+		WREG32(mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_ASID + dcore_offset, rw_asid);
+		WREG32(mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_MMU_BP + dcore_offset, 0);
+	}
+
+	/* Sync Mngr */
+	WREG32(mmDCORE0_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV + dcore_offset, asid);
+	/*
+	 * Sync Mngrs on dcores 1 - 3 are exposed to user, so must use user ASID
+	 * for any access type
+	 */
+	if (dcore_id > 0) {
+		reg_val = (asid << DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_ASID_RD_SHIFT) |
+			  (asid << DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_ASID_WR_SHIFT);
+		WREG32(mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_ASID + dcore_offset, reg_val);
+		WREG32(mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_MMU_BP + dcore_offset, 0);
+	}
+
+	WREG32(mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_MMU_BP + dcore_offset, 0);
+	WREG32(mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_ASID + dcore_offset, rw_asid);
+
+	for (i = 0 ; i < NUM_OF_MME_SBTE_PORTS ; i++) {
+		ports_offset = i * DCORE_MME_SBTE_OFFSET;
+		WREG32(mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_MMU_BP +
+				dcore_offset + ports_offset, 0);
+		WREG32(mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_ASID +
+				dcore_offset + ports_offset, rw_asid);
+	}
+
+	for (i = 0 ; i < NUM_OF_MME_WB_PORTS ; i++) {
+		ports_offset = i * DCORE_MME_WB_OFFSET;
+		WREG32(mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_MMU_BP +
+				dcore_offset + ports_offset, 0);
+		WREG32(mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_ASID +
+				dcore_offset + ports_offset, rw_asid);
+	}
+
+	WREG32(mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_MMU_BP + dcore_offset, 0);
+	WREG32(mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_ASID + dcore_offset, rw_asid);
+
+	/*
+	 * Decoders
+	 */
+	for (vdec_id = 0 ; vdec_id < NUM_OF_DEC_PER_DCORE ; vdec_id++) {
+		if (prop->decoder_enabled_mask & BIT(dcore_id * NUM_OF_DEC_PER_DCORE + vdec_id))
+			gaudi2_mmu_vdec_dcore_prepare(hdev, dcore_id, vdec_id, rw_asid, 0);
+	}
+}
+
+static void gudi2_mmu_vdec_shared_prepare(struct hl_device *hdev,
+				int shared_vdec_id, u32 rw_asid, u32 rw_mmu_bp)
+{
+	u32 offset = (mmPCIE_VDEC1_BRDG_CTRL_BASE - mmPCIE_VDEC0_BRDG_CTRL_BASE) * shared_vdec_id;
+
+	WREG32(mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_MMU_BP + offset, rw_mmu_bp);
+	WREG32(mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_ASID + offset, rw_asid);
+
+	WREG32(mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_MMU_BP + offset, rw_mmu_bp);
+	WREG32(mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_ASID + offset, rw_asid);
+
+	WREG32(mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_MMU_BP + offset, rw_mmu_bp);
+	WREG32(mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_ASID + offset, rw_asid);
+
+	WREG32(mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_MMU_BP + offset, rw_mmu_bp);
+	WREG32(mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_ASID + offset, rw_asid);
+
+	WREG32(mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_MMU_BP + offset, rw_mmu_bp);
+	WREG32(mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_ASID + offset, rw_asid);
+}
+
+static void gudi2_mmu_arc_farm_arc_dup_eng_prepare(struct hl_device *hdev, int arc_farm_id,
+							u32 rw_asid, u32 rw_mmu_bp)
+{
+	u32 offset = (mmARC_FARM_ARC1_DUP_ENG_BASE - mmARC_FARM_ARC0_DUP_ENG_BASE) * arc_farm_id;
+
+	WREG32(mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_MMU_BP + offset, rw_mmu_bp);
+	WREG32(mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_ASID + offset, rw_asid);
+}
+
+static void gaudi2_arc_mmu_prepare(struct hl_device *hdev, u32 cpu_id, u32 asid)
+{
+	u32 reg_base, reg_offset, reg_val = 0;
+
+	reg_base = gaudi2_arc_blocks_bases[cpu_id];
+
+	/* Enable MMU and configure asid for all relevant ARC regions */
+	reg_val = FIELD_PREP(ARC_FARM_ARC0_AUX_ARC_REGION_CFG_MMU_BP_MASK, 0);
+	reg_val |= FIELD_PREP(ARC_FARM_ARC0_AUX_ARC_REGION_CFG_0_ASID_MASK, asid);
+
+	reg_offset = ARC_REGION_CFG_OFFSET(ARC_REGION3_GENERAL);
+	WREG32(reg_base + reg_offset, reg_val);
+
+	reg_offset = ARC_REGION_CFG_OFFSET(ARC_REGION4_HBM0_FW);
+	WREG32(reg_base + reg_offset, reg_val);
+
+	reg_offset = ARC_REGION_CFG_OFFSET(ARC_REGION5_HBM1_GC_DATA);
+	WREG32(reg_base + reg_offset, reg_val);
+
+	reg_offset = ARC_REGION_CFG_OFFSET(ARC_REGION6_HBM2_GC_DATA);
+	WREG32(reg_base + reg_offset, reg_val);
+
+	reg_offset = ARC_REGION_CFG_OFFSET(ARC_REGION7_HBM3_GC_DATA);
+	WREG32(reg_base + reg_offset, reg_val);
+
+	reg_offset = ARC_REGION_CFG_OFFSET(ARC_REGION9_PCIE);
+	WREG32(reg_base + reg_offset, reg_val);
+
+	reg_offset = ARC_REGION_CFG_OFFSET(ARC_REGION10_GENERAL);
+	WREG32(reg_base + reg_offset, reg_val);
+
+	reg_offset = ARC_REGION_CFG_OFFSET(ARC_REGION11_GENERAL);
+	WREG32(reg_base + reg_offset, reg_val);
+
+	reg_offset = ARC_REGION_CFG_OFFSET(ARC_REGION12_GENERAL);
+	WREG32(reg_base + reg_offset, reg_val);
+
+	reg_offset = ARC_REGION_CFG_OFFSET(ARC_REGION13_GENERAL);
+	WREG32(reg_base + reg_offset, reg_val);
+
+	reg_offset = ARC_REGION_CFG_OFFSET(ARC_REGION14_GENERAL);
+	WREG32(reg_base + reg_offset, reg_val);
+}
+
+static int gaudi2_arc_mmu_prepare_all(struct hl_device *hdev, u32 asid)
+{
+	int i;
+
+	if (hdev->fw_components & FW_TYPE_BOOT_CPU)
+		return hl_fw_cpucp_engine_core_asid_set(hdev, asid);
+
+	for (i = CPU_ID_SCHED_ARC0 ; i < NUM_OF_ARC_FARMS_ARC ; i++)
+		gaudi2_arc_mmu_prepare(hdev, i, asid);
+
+	for (i = GAUDI2_QUEUE_ID_PDMA_0_0 ; i < GAUDI2_QUEUE_ID_CPU_PQ ; i += 4) {
+		if (!gaudi2_is_queue_enabled(hdev, i))
+			continue;
+
+		gaudi2_arc_mmu_prepare(hdev, gaudi2_queue_id_to_arc_id[i], asid);
+	}
+
+	return 0;
+}
+
+static int gaudi2_mmu_shared_prepare(struct hl_device *hdev, u32 asid)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	u32 rw_asid, offset;
+	int rc, i;
+
+	rw_asid = FIELD_PREP(ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_RD_MASK, asid) |
+			FIELD_PREP(ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_WR_MASK, asid);
+
+	WREG32(mmPDMA0_QM_AXUSER_NONSECURED_HB_ASID, rw_asid);
+	WREG32(mmPDMA0_QM_AXUSER_NONSECURED_HB_MMU_BP, 0);
+	WREG32(mmPDMA0_CORE_CTX_AXUSER_HB_ASID, rw_asid);
+	WREG32(mmPDMA0_CORE_CTX_AXUSER_HB_MMU_BP, 0);
+
+	WREG32(mmPDMA1_QM_AXUSER_NONSECURED_HB_ASID, rw_asid);
+	WREG32(mmPDMA1_QM_AXUSER_NONSECURED_HB_MMU_BP, 0);
+	WREG32(mmPDMA1_CORE_CTX_AXUSER_HB_ASID, rw_asid);
+	WREG32(mmPDMA1_CORE_CTX_AXUSER_HB_MMU_BP, 0);
+
+	/* ROT */
+	for (i = 0 ; i < NUM_OF_ROT ; i++) {
+		offset = i * ROT_OFFSET;
+		WREG32(mmROT0_QM_AXUSER_NONSECURED_HB_ASID + offset, rw_asid);
+		WREG32(mmROT0_QM_AXUSER_NONSECURED_HB_MMU_BP + offset, 0);
+		RMWREG32(mmROT0_CPL_QUEUE_AWUSER + offset, asid, MMUBP_ASID_MASK);
+		RMWREG32(mmROT0_DESC_HBW_ARUSER_LO + offset, asid, MMUBP_ASID_MASK);
+		RMWREG32(mmROT0_DESC_HBW_AWUSER_LO + offset, asid, MMUBP_ASID_MASK);
+	}
+
+	/* Shared Decoders are the last bits in the decoders mask */
+	if (prop->decoder_enabled_mask & BIT(NUM_OF_DCORES * NUM_OF_DEC_PER_DCORE + 0))
+		gudi2_mmu_vdec_shared_prepare(hdev, 0, rw_asid, 0);
+
+	if (prop->decoder_enabled_mask & BIT(NUM_OF_DCORES * NUM_OF_DEC_PER_DCORE + 1))
+		gudi2_mmu_vdec_shared_prepare(hdev, 1, rw_asid, 0);
+
+	/* arc farm arc dup eng */
+	for (i = 0 ; i < NUM_OF_ARC_FARMS_ARC ; i++)
+		gudi2_mmu_arc_farm_arc_dup_eng_prepare(hdev, i, rw_asid, 0);
+
+	rc = gaudi2_arc_mmu_prepare_all(hdev, asid);
+	if (rc)
+		return rc;
+
+	return 0;
+}
+
+static void gaudi2_tpc_mmu_prepare(struct hl_device *hdev, int dcore, int inst,	u32 offset,
+					struct iterate_module_ctx *ctx)
+{
+	struct gaudi2_tpc_mmu_data *mmu_data = ctx->data;
+
+	WREG32(mmDCORE0_TPC0_CFG_AXUSER_HB_MMU_BP + offset, 0);
+	WREG32(mmDCORE0_TPC0_CFG_AXUSER_HB_ASID + offset, mmu_data->rw_asid);
+	WREG32(mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_MMU_BP + offset, 0);
+	WREG32(mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_ASID + offset, mmu_data->rw_asid);
+}
+
+/* zero the MMUBP and set the ASID */
+static int gaudi2_mmu_prepare(struct hl_device *hdev, u32 asid)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	struct gaudi2_tpc_mmu_data tpc_mmu_data;
+	struct iterate_module_ctx tpc_iter = {
+		.fn = &gaudi2_tpc_mmu_prepare,
+		.data = &tpc_mmu_data,
+	};
+	int rc, i;
+
+	if (asid & ~DCORE0_HMMU0_STLB_ASID_ASID_MASK) {
+		dev_crit(hdev->dev, "asid %u is too big\n", asid);
+		return -EINVAL;
+	}
+
+	if (!(gaudi2->hw_cap_initialized & HW_CAP_MMU_MASK))
+		return 0;
+
+	rc = gaudi2_mmu_shared_prepare(hdev, asid);
+	if (rc)
+		return rc;
+
+	/* configure DCORE MMUs */
+	tpc_mmu_data.rw_asid = (asid << ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_RD_SHIFT) |
+				(asid << ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_WR_SHIFT);
+	gaudi2_iterate_tpcs(hdev, &tpc_iter);
+	for (i = 0 ; i < NUM_OF_DCORES ; i++)
+		gaudi2_mmu_dcore_prepare(hdev, i, asid);
+
+	return 0;
+}
+
+static inline bool is_info_event(u32 event)
+{
+	switch (event) {
+	case GAUDI2_EVENT_CPU_CPLD_SHUTDOWN_CAUSE:
+	case GAUDI2_EVENT_CPU_FIX_POWER_ENV_S ... GAUDI2_EVENT_CPU_FIX_THERMAL_ENV_E:
+	case GAUDI2_EVENT_ARC_PWR_BRK_ENTRY ... GAUDI2_EVENT_ARC_PWR_RD_MODE3:
+
+	/* return in case of NIC status event - these events are received periodically and not as
+	 * an indication to an error.
+	 */
+	case GAUDI2_EVENT_CPU0_STATUS_NIC0_ENG0 ... GAUDI2_EVENT_CPU11_STATUS_NIC11_ENG1:
+	case GAUDI2_EVENT_ARC_EQ_HEARTBEAT:
+		return true;
+	default:
+		return false;
+	}
+}
+
+static void gaudi2_print_event(struct hl_device *hdev, u16 event_type,
+			bool ratelimited, const char *fmt, ...)
+{
+	struct va_format vaf;
+	va_list args;
+
+	va_start(args, fmt);
+	vaf.fmt = fmt;
+	vaf.va = &args;
+
+	if (ratelimited)
+		dev_err_ratelimited(hdev->dev, "%s: %pV\n",
+			gaudi2_irq_map_table[event_type].valid ?
+			gaudi2_irq_map_table[event_type].name : "N/A Event", &vaf);
+	else
+		dev_err(hdev->dev, "%s: %pV\n",
+			gaudi2_irq_map_table[event_type].valid ?
+			gaudi2_irq_map_table[event_type].name : "N/A Event", &vaf);
+
+	va_end(args);
+}
+
+static bool gaudi2_handle_ecc_event(struct hl_device *hdev, u16 event_type,
+		struct hl_eq_ecc_data *ecc_data)
+{
+	u64 ecc_address = 0, ecc_syndrome = 0;
+	u8 memory_wrapper_idx = 0;
+	bool has_block_id = false;
+	u16 block_id;
+
+	if (hl_fw_version_cmp(hdev, 1, 12, 0) >= 0)
+		has_block_id = true;
+
+	ecc_address = le64_to_cpu(ecc_data->ecc_address);
+	ecc_syndrome = le64_to_cpu(ecc_data->ecc_syndrom);
+	memory_wrapper_idx = ecc_data->memory_wrapper_idx;
+
+	if (has_block_id) {
+		block_id = le16_to_cpu(ecc_data->block_id);
+		gaudi2_print_event(hdev, event_type, !ecc_data->is_critical,
+			"ECC error detected. address: %#llx. Syndrome: %#llx. wrapper id %u. block id %#x. critical %u.",
+			ecc_address, ecc_syndrome, memory_wrapper_idx, block_id,
+			ecc_data->is_critical);
+	} else {
+		gaudi2_print_event(hdev, event_type, !ecc_data->is_critical,
+			"ECC error detected. address: %#llx. Syndrome: %#llx. wrapper id %u. critical %u.",
+			ecc_address, ecc_syndrome, memory_wrapper_idx, ecc_data->is_critical);
+	}
+
+	return !!ecc_data->is_critical;
+}
+
+static void handle_lower_qman_data_on_err(struct hl_device *hdev, u64 qman_base, u32 engine_id)
+{
+	struct undefined_opcode_info *undef_opcode = &hdev->captured_err_info.undef_opcode;
+	u64 cq_ptr, cp_current_inst;
+	u32 lo, hi, cq_size, cp_sts;
+	bool is_arc_cq;
+
+	cp_sts = RREG32(qman_base + QM_CP_STS_4_OFFSET);
+	is_arc_cq = FIELD_GET(PDMA0_QM_CP_STS_CUR_CQ_MASK, cp_sts); /* 0 - legacy CQ, 1 - ARC_CQ */
+
+	if (is_arc_cq) {
+		lo = RREG32(qman_base + QM_ARC_CQ_PTR_LO_STS_OFFSET);
+		hi = RREG32(qman_base + QM_ARC_CQ_PTR_HI_STS_OFFSET);
+		cq_ptr = ((u64) hi) << 32 | lo;
+		cq_size = RREG32(qman_base + QM_ARC_CQ_TSIZE_STS_OFFSET);
+	} else {
+		lo = RREG32(qman_base + QM_CQ_PTR_LO_STS_4_OFFSET);
+		hi = RREG32(qman_base + QM_CQ_PTR_HI_STS_4_OFFSET);
+		cq_ptr = ((u64) hi) << 32 | lo;
+		cq_size = RREG32(qman_base + QM_CQ_TSIZE_STS_4_OFFSET);
+	}
+
+	lo = RREG32(qman_base + QM_CP_CURRENT_INST_LO_4_OFFSET);
+	hi = RREG32(qman_base + QM_CP_CURRENT_INST_HI_4_OFFSET);
+	cp_current_inst = ((u64) hi) << 32 | lo;
+
+	dev_info(hdev->dev,
+		"LowerQM. %sCQ: {ptr %#llx, size %u}, CP: {instruction %#018llx}\n",
+		is_arc_cq ? "ARC_" : "", cq_ptr, cq_size, cp_current_inst);
+
+	if (undef_opcode->write_enable) {
+		memset(undef_opcode, 0, sizeof(*undef_opcode));
+		undef_opcode->timestamp = ktime_get();
+		undef_opcode->cq_addr = cq_ptr;
+		undef_opcode->cq_size = cq_size;
+		undef_opcode->engine_id = engine_id;
+		undef_opcode->stream_id = QMAN_STREAMS;
+		undef_opcode->write_enable = 0;
+	}
+}
+
+static int gaudi2_handle_qman_err_generic(struct hl_device *hdev, u16 event_type,
+						u64 qman_base, u32 qid_base, u64 *event_mask)
+{
+	u32 i, j, glbl_sts_val, arb_err_val, num_error_causes, error_count = 0;
+	u64 glbl_sts_addr, arb_err_addr;
+	char reg_desc[32];
+
+	glbl_sts_addr = qman_base + (mmDCORE0_TPC0_QM_GLBL_ERR_STS_0 - mmDCORE0_TPC0_QM_BASE);
+	arb_err_addr = qman_base + (mmDCORE0_TPC0_QM_ARB_ERR_CAUSE - mmDCORE0_TPC0_QM_BASE);
+
+	/* Iterate through all stream GLBL_ERR_STS registers + Lower CP */
+	for (i = 0 ; i < QMAN_STREAMS + 1 ; i++) {
+		glbl_sts_val = RREG32(glbl_sts_addr + 4 * i);
+
+		if (!glbl_sts_val)
+			continue;
+
+		if (i == QMAN_STREAMS) {
+			snprintf(reg_desc, ARRAY_SIZE(reg_desc), "LowerQM");
+			num_error_causes = GAUDI2_NUM_OF_LOWER_QM_ERR_CAUSE;
+		} else {
+			snprintf(reg_desc, ARRAY_SIZE(reg_desc), "stream%u", i);
+			num_error_causes = GAUDI2_NUM_OF_QM_ERR_CAUSE;
+		}
+
+		for (j = 0 ; j < num_error_causes ; j++)
+			if (glbl_sts_val & BIT(j)) {
+				gaudi2_print_event(hdev, event_type, true,
+					"%s. err cause: %s", reg_desc,
+					i == QMAN_STREAMS ?
+					gaudi2_lower_qman_error_cause[j] :
+					gaudi2_qman_error_cause[j]);
+				error_count++;
+			}
+
+		/* Check for undefined opcode error in lower QM */
+		if ((i == QMAN_STREAMS) &&
+				(glbl_sts_val & PDMA0_QM_GLBL_ERR_STS_CP_UNDEF_CMD_ERR_MASK)) {
+			handle_lower_qman_data_on_err(hdev, qman_base,
+							gaudi2_queue_id_to_engine_id[qid_base]);
+			*event_mask |= HL_NOTIFIER_EVENT_UNDEFINED_OPCODE;
+		}
+	}
+
+	arb_err_val = RREG32(arb_err_addr);
+
+	if (!arb_err_val)
+		goto out;
+
+	for (j = 0 ; j < GAUDI2_NUM_OF_QM_ARB_ERR_CAUSE ; j++) {
+		if (arb_err_val & BIT(j)) {
+			gaudi2_print_event(hdev, event_type, true,
+				"ARB_ERR. err cause: %s",
+				gaudi2_qman_arb_error_cause[j]);
+			error_count++;
+		}
+	}
+
+out:
+	return error_count;
+}
+
+static void gaudi2_razwi_rr_hbw_shared_printf_info(struct hl_device *hdev,
+			u64 rtr_mstr_if_base_addr, bool is_write, char *name,
+			enum gaudi2_engine_id id, u64 *event_mask)
+{
+	u32 razwi_hi, razwi_lo, razwi_xy;
+	u16 eng_id = id;
+	u8 rd_wr_flag;
+
+	if (is_write) {
+		razwi_hi = RREG32(rtr_mstr_if_base_addr + RR_SHRD_HBW_AW_RAZWI_HI);
+		razwi_lo = RREG32(rtr_mstr_if_base_addr + RR_SHRD_HBW_AW_RAZWI_LO);
+		razwi_xy = RREG32(rtr_mstr_if_base_addr + RR_SHRD_HBW_AW_RAZWI_XY);
+		rd_wr_flag = HL_RAZWI_WRITE;
+	} else {
+		razwi_hi = RREG32(rtr_mstr_if_base_addr + RR_SHRD_HBW_AR_RAZWI_HI);
+		razwi_lo = RREG32(rtr_mstr_if_base_addr + RR_SHRD_HBW_AR_RAZWI_LO);
+		razwi_xy = RREG32(rtr_mstr_if_base_addr + RR_SHRD_HBW_AR_RAZWI_XY);
+		rd_wr_flag = HL_RAZWI_READ;
+	}
+
+	hl_handle_razwi(hdev, (u64)razwi_hi << 32 | razwi_lo, &eng_id, 1,
+				rd_wr_flag | HL_RAZWI_HBW, event_mask);
+
+	dev_err_ratelimited(hdev->dev,
+		"%s-RAZWI SHARED RR HBW %s error, address %#llx, Initiator coordinates 0x%x\n",
+		name, is_write ? "WR" : "RD", (u64)razwi_hi << 32 | razwi_lo, razwi_xy);
+}
+
+static void gaudi2_razwi_rr_lbw_shared_printf_info(struct hl_device *hdev,
+			u64 rtr_mstr_if_base_addr, bool is_write, char *name,
+			enum gaudi2_engine_id id, u64 *event_mask)
+{
+	u64 razwi_addr = CFG_BASE;
+	u32 razwi_xy;
+	u16 eng_id = id;
+	u8 rd_wr_flag;
+
+	if (is_write) {
+		razwi_addr += RREG32(rtr_mstr_if_base_addr + RR_SHRD_LBW_AW_RAZWI);
+		razwi_xy = RREG32(rtr_mstr_if_base_addr + RR_SHRD_LBW_AW_RAZWI_XY);
+		rd_wr_flag = HL_RAZWI_WRITE;
+	} else {
+		razwi_addr += RREG32(rtr_mstr_if_base_addr + RR_SHRD_LBW_AR_RAZWI);
+		razwi_xy = RREG32(rtr_mstr_if_base_addr + RR_SHRD_LBW_AR_RAZWI_XY);
+		rd_wr_flag = HL_RAZWI_READ;
+	}
+
+	hl_handle_razwi(hdev, razwi_addr, &eng_id, 1, rd_wr_flag | HL_RAZWI_LBW, event_mask);
+	dev_err_ratelimited(hdev->dev,
+				"%s-RAZWI SHARED RR LBW %s error, mstr_if 0x%llx, captured address 0x%llX Initiator coordinates 0x%x\n",
+				name, is_write ? "WR" : "RD", rtr_mstr_if_base_addr, razwi_addr,
+						razwi_xy);
+}
+
+static enum gaudi2_engine_id gaudi2_razwi_calc_engine_id(struct hl_device *hdev,
+						enum razwi_event_sources module, u8 module_idx)
+{
+	switch (module) {
+	case RAZWI_TPC:
+		if (module_idx == (NUM_OF_TPC_PER_DCORE * NUM_OF_DCORES))
+			return GAUDI2_DCORE0_ENGINE_ID_TPC_6;
+		return (((module_idx / NUM_OF_TPC_PER_DCORE) * ENGINE_ID_DCORE_OFFSET) +
+				(module_idx % NUM_OF_TPC_PER_DCORE) +
+				(GAUDI2_DCORE0_ENGINE_ID_TPC_0 - GAUDI2_DCORE0_ENGINE_ID_EDMA_0));
+
+	case RAZWI_MME:
+		return ((GAUDI2_DCORE0_ENGINE_ID_MME - GAUDI2_DCORE0_ENGINE_ID_EDMA_0) +
+			(module_idx * ENGINE_ID_DCORE_OFFSET));
+
+	case RAZWI_EDMA:
+		return (((module_idx / NUM_OF_EDMA_PER_DCORE) * ENGINE_ID_DCORE_OFFSET) +
+			(module_idx % NUM_OF_EDMA_PER_DCORE));
+
+	case RAZWI_PDMA:
+		return (GAUDI2_ENGINE_ID_PDMA_0 + module_idx);
+
+	case RAZWI_NIC:
+		return (GAUDI2_ENGINE_ID_NIC0_0 + (NIC_NUMBER_OF_QM_PER_MACRO * module_idx));
+
+	case RAZWI_DEC:
+		if (module_idx == 8)
+			return GAUDI2_PCIE_ENGINE_ID_DEC_0;
+
+		if (module_idx == 9)
+			return GAUDI2_PCIE_ENGINE_ID_DEC_1;
+					;
+		return (((module_idx / NUM_OF_DEC_PER_DCORE) * ENGINE_ID_DCORE_OFFSET) +
+				(module_idx % NUM_OF_DEC_PER_DCORE) +
+				(GAUDI2_DCORE0_ENGINE_ID_DEC_0 - GAUDI2_DCORE0_ENGINE_ID_EDMA_0));
+
+	case RAZWI_ROT:
+		return GAUDI2_ENGINE_ID_ROT_0 + module_idx;
+
+	case RAZWI_ARC_FARM:
+		return GAUDI2_ENGINE_ID_ARC_FARM;
+
+	default:
+		return GAUDI2_ENGINE_ID_SIZE;
+	}
+}
+
+/*
+ * This function handles RR(Range register) hit events.
+ * raised be initiators not PSOC RAZWI.
+ */
+static void gaudi2_ack_module_razwi_event_handler(struct hl_device *hdev,
+				enum razwi_event_sources module, u8 module_idx,
+				u8 module_sub_idx, u64 *event_mask)
+{
+	bool via_sft = false;
+	u32 hbw_rtr_id, lbw_rtr_id, dcore_id, dcore_rtr_id, eng_id, binned_idx;
+	u64 hbw_rtr_mstr_if_base_addr, lbw_rtr_mstr_if_base_addr;
+	u32 hbw_shrd_aw = 0, hbw_shrd_ar = 0;
+	u32 lbw_shrd_aw = 0, lbw_shrd_ar = 0;
+	char initiator_name[64];
+
+	switch (module) {
+	case RAZWI_TPC:
+		sprintf(initiator_name, "TPC_%u", module_idx);
+		if (hdev->tpc_binning) {
+			binned_idx = __ffs(hdev->tpc_binning);
+			if (binned_idx == module_idx)
+				module_idx = TPC_ID_DCORE0_TPC6;
+		}
+
+		hbw_rtr_id = gaudi2_tpc_initiator_hbw_rtr_id[module_idx];
+		lbw_rtr_id = gaudi2_tpc_initiator_lbw_rtr_id[module_idx];
+		break;
+	case RAZWI_MME:
+		sprintf(initiator_name, "MME_%u", module_idx);
+		switch (module_sub_idx) {
+		case MME_WAP0:
+			hbw_rtr_id = gaudi2_mme_initiator_rtr_id[module_idx].wap0;
+			break;
+		case MME_WAP1:
+			hbw_rtr_id = gaudi2_mme_initiator_rtr_id[module_idx].wap1;
+			break;
+		case MME_WRITE:
+			hbw_rtr_id = gaudi2_mme_initiator_rtr_id[module_idx].write;
+			break;
+		case MME_READ:
+			hbw_rtr_id = gaudi2_mme_initiator_rtr_id[module_idx].read;
+			break;
+		case MME_SBTE0:
+			hbw_rtr_id = gaudi2_mme_initiator_rtr_id[module_idx].sbte0;
+			break;
+		case MME_SBTE1:
+			hbw_rtr_id = gaudi2_mme_initiator_rtr_id[module_idx].sbte1;
+			break;
+		case MME_SBTE2:
+			hbw_rtr_id = gaudi2_mme_initiator_rtr_id[module_idx].sbte2;
+			break;
+		case MME_SBTE3:
+			hbw_rtr_id = gaudi2_mme_initiator_rtr_id[module_idx].sbte3;
+			break;
+		case MME_SBTE4:
+			hbw_rtr_id = gaudi2_mme_initiator_rtr_id[module_idx].sbte4;
+			break;
+		default:
+			return;
+		}
+		lbw_rtr_id = hbw_rtr_id;
+		break;
+	case RAZWI_EDMA:
+		hbw_rtr_mstr_if_base_addr = gaudi2_edma_initiator_hbw_sft[module_idx];
+		dcore_id = module_idx / NUM_OF_EDMA_PER_DCORE;
+		/* SFT has separate MSTR_IF for LBW, only there we can
+		 * read the LBW razwi related registers
+		 */
+		lbw_rtr_mstr_if_base_addr = mmSFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE +
+								dcore_id * SFT_DCORE_OFFSET;
+		via_sft = true;
+		sprintf(initiator_name, "EDMA_%u", module_idx);
+		break;
+	case RAZWI_PDMA:
+		hbw_rtr_id = gaudi2_pdma_initiator_hbw_rtr_id[module_idx];
+		lbw_rtr_id = gaudi2_pdma_initiator_lbw_rtr_id[module_idx];
+		sprintf(initiator_name, "PDMA_%u", module_idx);
+		break;
+	case RAZWI_NIC:
+		hbw_rtr_id = gaudi2_nic_initiator_hbw_rtr_id[module_idx];
+		lbw_rtr_id = gaudi2_nic_initiator_lbw_rtr_id[module_idx];
+		sprintf(initiator_name, "NIC_%u", module_idx);
+		break;
+	case RAZWI_DEC:
+		sprintf(initiator_name, "DEC_%u", module_idx);
+		if (hdev->decoder_binning) {
+			binned_idx = __ffs(hdev->decoder_binning);
+			if (binned_idx == module_idx)
+				module_idx = DEC_ID_PCIE_VDEC1;
+		}
+		hbw_rtr_id = gaudi2_dec_initiator_hbw_rtr_id[module_idx];
+		lbw_rtr_id = gaudi2_dec_initiator_lbw_rtr_id[module_idx];
+		break;
+	case RAZWI_ROT:
+		hbw_rtr_id = gaudi2_rot_initiator_hbw_rtr_id[module_idx];
+		lbw_rtr_id = gaudi2_rot_initiator_lbw_rtr_id[module_idx];
+		sprintf(initiator_name, "ROT_%u", module_idx);
+		break;
+	case RAZWI_ARC_FARM:
+		lbw_rtr_id = DCORE1_RTR5;
+		hbw_rtr_id = DCORE1_RTR7;
+		sprintf(initiator_name, "ARC_FARM_%u", module_idx);
+		break;
+	default:
+		return;
+	}
+
+	/* Find router mstr_if register base */
+	if (!via_sft) {
+		dcore_id = hbw_rtr_id / NUM_OF_RTR_PER_DCORE;
+		dcore_rtr_id = hbw_rtr_id % NUM_OF_RTR_PER_DCORE;
+		hbw_rtr_mstr_if_base_addr = mmDCORE0_RTR0_CTRL_BASE +
+				dcore_id * DCORE_OFFSET +
+				dcore_rtr_id * DCORE_RTR_OFFSET +
+				RTR_MSTR_IF_OFFSET;
+		lbw_rtr_mstr_if_base_addr = hbw_rtr_mstr_if_base_addr +
+				(((s32)lbw_rtr_id - hbw_rtr_id) * DCORE_RTR_OFFSET);
+	}
+
+	/* Find out event cause by reading "RAZWI_HAPPENED" registers */
+	hbw_shrd_aw = RREG32(hbw_rtr_mstr_if_base_addr + RR_SHRD_HBW_AW_RAZWI_HAPPENED);
+	hbw_shrd_ar = RREG32(hbw_rtr_mstr_if_base_addr + RR_SHRD_HBW_AR_RAZWI_HAPPENED);
+	lbw_shrd_aw = RREG32(lbw_rtr_mstr_if_base_addr + RR_SHRD_LBW_AW_RAZWI_HAPPENED);
+	lbw_shrd_ar = RREG32(lbw_rtr_mstr_if_base_addr + RR_SHRD_LBW_AR_RAZWI_HAPPENED);
+
+	eng_id = gaudi2_razwi_calc_engine_id(hdev, module, module_idx);
+	if (hbw_shrd_aw) {
+		gaudi2_razwi_rr_hbw_shared_printf_info(hdev, hbw_rtr_mstr_if_base_addr, true,
+						initiator_name, eng_id, event_mask);
+
+		/* Clear event indication */
+		WREG32(hbw_rtr_mstr_if_base_addr + RR_SHRD_HBW_AW_RAZWI_HAPPENED, hbw_shrd_aw);
+	}
+
+	if (hbw_shrd_ar) {
+		gaudi2_razwi_rr_hbw_shared_printf_info(hdev, hbw_rtr_mstr_if_base_addr, false,
+						initiator_name, eng_id, event_mask);
+
+		/* Clear event indication */
+		WREG32(hbw_rtr_mstr_if_base_addr + RR_SHRD_HBW_AR_RAZWI_HAPPENED, hbw_shrd_ar);
+	}
+
+	if (lbw_shrd_aw) {
+		gaudi2_razwi_rr_lbw_shared_printf_info(hdev, lbw_rtr_mstr_if_base_addr, true,
+						initiator_name, eng_id, event_mask);
+
+		/* Clear event indication */
+		WREG32(lbw_rtr_mstr_if_base_addr + RR_SHRD_LBW_AW_RAZWI_HAPPENED, lbw_shrd_aw);
+	}
+
+	if (lbw_shrd_ar) {
+		gaudi2_razwi_rr_lbw_shared_printf_info(hdev, lbw_rtr_mstr_if_base_addr, false,
+						initiator_name, eng_id, event_mask);
+
+		/* Clear event indication */
+		WREG32(lbw_rtr_mstr_if_base_addr + RR_SHRD_LBW_AR_RAZWI_HAPPENED, lbw_shrd_ar);
+	}
+}
+
+static void gaudi2_check_if_razwi_happened(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	u8 mod_idx, sub_mod;
+
+	/* check all TPCs */
+	for (mod_idx = 0 ; mod_idx < (NUM_OF_TPC_PER_DCORE * NUM_OF_DCORES + 1) ; mod_idx++) {
+		if (prop->tpc_enabled_mask & BIT(mod_idx))
+			gaudi2_ack_module_razwi_event_handler(hdev, RAZWI_TPC, mod_idx, 0, NULL);
+	}
+
+	/* check all MMEs */
+	for (mod_idx = 0 ; mod_idx < (NUM_OF_MME_PER_DCORE * NUM_OF_DCORES) ; mod_idx++)
+		for (sub_mod = MME_WAP0 ; sub_mod < MME_INITIATORS_MAX ; sub_mod++)
+			gaudi2_ack_module_razwi_event_handler(hdev, RAZWI_MME, mod_idx,
+									sub_mod, NULL);
+
+	/* check all EDMAs */
+	for (mod_idx = 0 ; mod_idx < (NUM_OF_EDMA_PER_DCORE * NUM_OF_DCORES) ; mod_idx++)
+		if (prop->edma_enabled_mask & BIT(mod_idx))
+			gaudi2_ack_module_razwi_event_handler(hdev, RAZWI_EDMA, mod_idx, 0, NULL);
+
+	/* check all PDMAs */
+	for (mod_idx = 0 ; mod_idx < NUM_OF_PDMA ; mod_idx++)
+		gaudi2_ack_module_razwi_event_handler(hdev, RAZWI_PDMA, mod_idx, 0, NULL);
+
+	/* check all NICs */
+	for (mod_idx = 0 ; mod_idx < NIC_NUMBER_OF_PORTS ; mod_idx++)
+		if (hdev->nic_ports_mask & BIT(mod_idx))
+			gaudi2_ack_module_razwi_event_handler(hdev, RAZWI_NIC, mod_idx >> 1, 0,
+								NULL);
+
+	/* check all DECs */
+	for (mod_idx = 0 ; mod_idx < NUMBER_OF_DEC ; mod_idx++)
+		if (prop->decoder_enabled_mask & BIT(mod_idx))
+			gaudi2_ack_module_razwi_event_handler(hdev, RAZWI_DEC, mod_idx, 0, NULL);
+
+	/* check all ROTs */
+	for (mod_idx = 0 ; mod_idx < NUM_OF_ROT ; mod_idx++)
+		gaudi2_ack_module_razwi_event_handler(hdev, RAZWI_ROT, mod_idx, 0, NULL);
+}
+
+static int gaudi2_psoc_razwi_get_engines(struct gaudi2_razwi_info *razwi_info, u32 array_size,
+						u32 axuser_xy, u32 *base, u16 *eng_id,
+						char *eng_name)
+{
+
+	int i, num_of_eng = 0;
+	u16 str_size = 0;
+
+	for (i = 0 ; i < array_size ; i++) {
+		if (axuser_xy != razwi_info[i].axuser_xy)
+			continue;
+
+		eng_id[num_of_eng] = razwi_info[i].eng_id;
+		base[num_of_eng] = razwi_info[i].rtr_ctrl;
+		if (!num_of_eng)
+			str_size += scnprintf(eng_name + str_size,
+						PSOC_RAZWI_ENG_STR_SIZE - str_size, "%s",
+						razwi_info[i].eng_name);
+		else
+			str_size += scnprintf(eng_name + str_size,
+						PSOC_RAZWI_ENG_STR_SIZE - str_size, " or %s",
+						razwi_info[i].eng_name);
+		num_of_eng++;
+	}
+
+	return num_of_eng;
+}
+
+static bool gaudi2_handle_psoc_razwi_happened(struct hl_device *hdev, u32 razwi_reg,
+						u64 *event_mask)
+{
+	u32 axuser_xy = RAZWI_GET_AXUSER_XY(razwi_reg), addr_hi = 0, addr_lo = 0;
+	u32 base[PSOC_RAZWI_MAX_ENG_PER_RTR];
+	u16 num_of_eng, eng_id[PSOC_RAZWI_MAX_ENG_PER_RTR];
+	char eng_name_str[PSOC_RAZWI_ENG_STR_SIZE];
+	bool razwi_happened = false;
+	u64 addr;
+	int i;
+
+	num_of_eng = gaudi2_psoc_razwi_get_engines(common_razwi_info, ARRAY_SIZE(common_razwi_info),
+							axuser_xy, base, eng_id, eng_name_str);
+
+	/* If no match for XY coordinates, try to find it in MME razwi table */
+	if (!num_of_eng) {
+		axuser_xy = RAZWI_GET_AXUSER_LOW_XY(razwi_reg);
+		num_of_eng = gaudi2_psoc_razwi_get_engines(mme_razwi_info,
+								ARRAY_SIZE(mme_razwi_info),
+								axuser_xy, base, eng_id,
+								eng_name_str);
+	}
+
+	for  (i = 0 ; i < num_of_eng ; i++) {
+		if (RREG32(base[i] + DEC_RAZWI_HBW_AW_SET)) {
+			addr_hi = RREG32(base[i] + DEC_RAZWI_HBW_AW_ADDR_HI);
+			addr_lo = RREG32(base[i] + DEC_RAZWI_HBW_AW_ADDR_LO);
+			addr = ((u64)addr_hi << 32) + addr_lo;
+			if (addr) {
+				dev_err(hdev->dev,
+					"PSOC HBW AW RAZWI: %s, address (aligned to 128 byte): 0x%llX\n",
+					eng_name_str, addr);
+				hl_handle_razwi(hdev, addr, &eng_id[0],
+					num_of_eng, HL_RAZWI_HBW | HL_RAZWI_WRITE, event_mask);
+				razwi_happened = true;
+			}
+		}
+
+		if (RREG32(base[i] + DEC_RAZWI_HBW_AR_SET)) {
+			addr_hi = RREG32(base[i] + DEC_RAZWI_HBW_AR_ADDR_HI);
+			addr_lo = RREG32(base[i] + DEC_RAZWI_HBW_AR_ADDR_LO);
+			addr = ((u64)addr_hi << 32) + addr_lo;
+			if (addr) {
+				dev_err(hdev->dev,
+					"PSOC HBW AR RAZWI: %s, address (aligned to 128 byte): 0x%llX\n",
+					eng_name_str, addr);
+				hl_handle_razwi(hdev, addr, &eng_id[0],
+					num_of_eng, HL_RAZWI_HBW | HL_RAZWI_READ, event_mask);
+				razwi_happened = true;
+			}
+		}
+
+		if (RREG32(base[i] + DEC_RAZWI_LBW_AW_SET)) {
+			addr_lo = RREG32(base[i] + DEC_RAZWI_LBW_AW_ADDR);
+			if (addr_lo) {
+				dev_err(hdev->dev,
+					"PSOC LBW AW RAZWI: %s, address (aligned to 128 byte): 0x%X\n",
+					eng_name_str, addr_lo);
+				hl_handle_razwi(hdev, addr_lo, &eng_id[0],
+					num_of_eng, HL_RAZWI_LBW | HL_RAZWI_WRITE, event_mask);
+				razwi_happened = true;
+			}
+		}
+
+		if (RREG32(base[i] + DEC_RAZWI_LBW_AR_SET)) {
+			addr_lo = RREG32(base[i] + DEC_RAZWI_LBW_AR_ADDR);
+			if (addr_lo) {
+				dev_err(hdev->dev,
+						"PSOC LBW AR RAZWI: %s, address (aligned to 128 byte): 0x%X\n",
+						eng_name_str, addr_lo);
+				hl_handle_razwi(hdev, addr_lo, &eng_id[0],
+					num_of_eng, HL_RAZWI_LBW | HL_RAZWI_READ, event_mask);
+				razwi_happened = true;
+			}
+		}
+		/* In common case the loop will break, when there is only one engine id, or
+		 * several engines with the same router. The exceptional case is with psoc razwi
+		 * from EDMA, where it's possible to get axuser id which fits 2 routers (2
+		 * interfaces of sft router). In this case, maybe the first router won't hold info
+		 * and we will need to iterate on the other router.
+		 */
+		if (razwi_happened)
+			break;
+	}
+
+	return razwi_happened;
+}
+
+/* PSOC RAZWI interrupt occurs only when trying to access a bad address */
+static int gaudi2_ack_psoc_razwi_event_handler(struct hl_device *hdev, u64 *event_mask)
+{
+	u32 razwi_mask_info, razwi_intr = 0, error_count = 0;
+
+	if (hdev->pldm || !(hdev->fw_components & FW_TYPE_LINUX)) {
+		razwi_intr = RREG32(mmPSOC_GLOBAL_CONF_RAZWI_INTERRUPT);
+		if (!razwi_intr)
+			return 0;
+	}
+
+	razwi_mask_info = RREG32(mmPSOC_GLOBAL_CONF_RAZWI_MASK_INFO);
+
+	dev_err_ratelimited(hdev->dev,
+		"PSOC RAZWI interrupt: Mask %d, AR %d, AW %d, AXUSER_L 0x%x AXUSER_H 0x%x\n",
+		FIELD_GET(PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_MASK_MASK, razwi_mask_info),
+		FIELD_GET(PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_WAS_AR_MASK, razwi_mask_info),
+		FIELD_GET(PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_WAS_AW_MASK, razwi_mask_info),
+		FIELD_GET(PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_AXUSER_L_MASK, razwi_mask_info),
+		FIELD_GET(PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_AXUSER_H_MASK, razwi_mask_info));
+
+	if (gaudi2_handle_psoc_razwi_happened(hdev, razwi_mask_info, event_mask))
+		error_count++;
+	else
+		dev_err_ratelimited(hdev->dev,
+				"PSOC RAZWI interrupt: invalid razwi info (0x%x)\n",
+				razwi_mask_info);
+
+	/* Clear Interrupts only on pldm or if f/w doesn't handle interrupts */
+	if (hdev->pldm || !(hdev->fw_components & FW_TYPE_LINUX))
+		WREG32(mmPSOC_GLOBAL_CONF_RAZWI_INTERRUPT, razwi_intr);
+
+	return error_count;
+}
+
+static int _gaudi2_handle_qm_sei_err(struct hl_device *hdev, u64 qman_base, u16 event_type)
+{
+	u32 i, sts_val, sts_clr_val = 0, error_count = 0;
+
+	sts_val = RREG32(qman_base + QM_SEI_STATUS_OFFSET);
+
+	for (i = 0 ; i < GAUDI2_NUM_OF_QM_SEI_ERR_CAUSE ; i++) {
+		if (sts_val & BIT(i)) {
+			gaudi2_print_event(hdev, event_type, true,
+				"err cause: %s", gaudi2_qm_sei_error_cause[i]);
+			sts_clr_val |= BIT(i);
+			error_count++;
+		}
+	}
+
+	WREG32(qman_base + QM_SEI_STATUS_OFFSET, sts_clr_val);
+
+	return error_count;
+}
+
+static int gaudi2_handle_qm_sei_err(struct hl_device *hdev, u16 event_type,
+					bool extended_err_check, u64 *event_mask)
+{
+	enum razwi_event_sources module;
+	u32 error_count = 0;
+	u64 qman_base;
+	u8 index;
+
+	switch (event_type) {
+	case GAUDI2_EVENT_TPC0_AXI_ERR_RSP ... GAUDI2_EVENT_TPC23_AXI_ERR_RSP:
+		index = event_type - GAUDI2_EVENT_TPC0_AXI_ERR_RSP;
+		qman_base = mmDCORE0_TPC0_QM_BASE +
+				(index / NUM_OF_TPC_PER_DCORE) * DCORE_OFFSET +
+				(index % NUM_OF_TPC_PER_DCORE) * DCORE_TPC_OFFSET;
+		module = RAZWI_TPC;
+		break;
+	case GAUDI2_EVENT_TPC24_AXI_ERR_RSP:
+		qman_base = mmDCORE0_TPC6_QM_BASE;
+		module = RAZWI_TPC;
+		break;
+	case GAUDI2_EVENT_MME0_CTRL_AXI_ERROR_RESPONSE:
+	case GAUDI2_EVENT_MME1_CTRL_AXI_ERROR_RESPONSE:
+	case GAUDI2_EVENT_MME2_CTRL_AXI_ERROR_RESPONSE:
+	case GAUDI2_EVENT_MME3_CTRL_AXI_ERROR_RESPONSE:
+		index = (event_type - GAUDI2_EVENT_MME0_CTRL_AXI_ERROR_RESPONSE) /
+				(GAUDI2_EVENT_MME1_CTRL_AXI_ERROR_RESPONSE -
+						GAUDI2_EVENT_MME0_CTRL_AXI_ERROR_RESPONSE);
+		qman_base = mmDCORE0_MME_QM_BASE + index * DCORE_OFFSET;
+		module = RAZWI_MME;
+		break;
+	case GAUDI2_EVENT_PDMA_CH0_AXI_ERR_RSP:
+	case GAUDI2_EVENT_PDMA_CH1_AXI_ERR_RSP:
+		index = event_type - GAUDI2_EVENT_PDMA_CH0_AXI_ERR_RSP;
+		qman_base = mmPDMA0_QM_BASE + index * PDMA_OFFSET;
+		module = RAZWI_PDMA;
+		break;
+	case GAUDI2_EVENT_ROTATOR0_AXI_ERROR_RESPONSE:
+	case GAUDI2_EVENT_ROTATOR1_AXI_ERROR_RESPONSE:
+		index = event_type - GAUDI2_EVENT_ROTATOR0_AXI_ERROR_RESPONSE;
+		qman_base = mmROT0_QM_BASE + index * ROT_OFFSET;
+		module = RAZWI_ROT;
+		break;
+	default:
+		return 0;
+	}
+
+	error_count = _gaudi2_handle_qm_sei_err(hdev, qman_base, event_type);
+
+	/* There is a single event per NIC macro, so should check its both QMAN blocks */
+	if (event_type >= GAUDI2_EVENT_NIC0_AXI_ERROR_RESPONSE &&
+			event_type <= GAUDI2_EVENT_NIC11_AXI_ERROR_RESPONSE)
+		error_count += _gaudi2_handle_qm_sei_err(hdev,
+					qman_base + NIC_QM_OFFSET, event_type);
+
+	if (extended_err_check) {
+		/* check if RAZWI happened */
+		gaudi2_ack_module_razwi_event_handler(hdev, module, 0, 0, event_mask);
+		hl_check_for_glbl_errors(hdev);
+	}
+
+	return error_count;
+}
+
+static int gaudi2_handle_qman_err(struct hl_device *hdev, u16 event_type, u64 *event_mask)
+{
+	u32 qid_base, error_count = 0;
+	u64 qman_base;
+	u8 index = 0;
+
+	switch (event_type) {
+	case GAUDI2_EVENT_TPC0_QM ... GAUDI2_EVENT_TPC5_QM:
+		index = event_type - GAUDI2_EVENT_TPC0_QM;
+		qid_base = GAUDI2_QUEUE_ID_DCORE0_TPC_0_0 + index * QMAN_STREAMS;
+		qman_base = mmDCORE0_TPC0_QM_BASE + index * DCORE_TPC_OFFSET;
+		break;
+	case GAUDI2_EVENT_TPC6_QM ... GAUDI2_EVENT_TPC11_QM:
+		index = event_type - GAUDI2_EVENT_TPC6_QM;
+		qid_base = GAUDI2_QUEUE_ID_DCORE1_TPC_0_0 + index * QMAN_STREAMS;
+		qman_base = mmDCORE1_TPC0_QM_BASE + index * DCORE_TPC_OFFSET;
+		break;
+	case GAUDI2_EVENT_TPC12_QM ... GAUDI2_EVENT_TPC17_QM:
+		index = event_type - GAUDI2_EVENT_TPC12_QM;
+		qid_base = GAUDI2_QUEUE_ID_DCORE2_TPC_0_0 + index * QMAN_STREAMS;
+		qman_base = mmDCORE2_TPC0_QM_BASE + index * DCORE_TPC_OFFSET;
+		break;
+	case GAUDI2_EVENT_TPC18_QM ... GAUDI2_EVENT_TPC23_QM:
+		index = event_type - GAUDI2_EVENT_TPC18_QM;
+		qid_base = GAUDI2_QUEUE_ID_DCORE3_TPC_0_0 + index * QMAN_STREAMS;
+		qman_base = mmDCORE3_TPC0_QM_BASE + index * DCORE_TPC_OFFSET;
+		break;
+	case GAUDI2_EVENT_TPC24_QM:
+		qid_base = GAUDI2_QUEUE_ID_DCORE0_TPC_6_0;
+		qman_base = mmDCORE0_TPC6_QM_BASE;
+		break;
+	case GAUDI2_EVENT_MME0_QM:
+		qid_base = GAUDI2_QUEUE_ID_DCORE0_MME_0_0;
+		qman_base = mmDCORE0_MME_QM_BASE;
+		break;
+	case GAUDI2_EVENT_MME1_QM:
+		qid_base = GAUDI2_QUEUE_ID_DCORE1_MME_0_0;
+		qman_base = mmDCORE1_MME_QM_BASE;
+		break;
+	case GAUDI2_EVENT_MME2_QM:
+		qid_base = GAUDI2_QUEUE_ID_DCORE2_MME_0_0;
+		qman_base = mmDCORE2_MME_QM_BASE;
+		break;
+	case GAUDI2_EVENT_MME3_QM:
+		qid_base = GAUDI2_QUEUE_ID_DCORE3_MME_0_0;
+		qman_base = mmDCORE3_MME_QM_BASE;
+		break;
+	case GAUDI2_EVENT_HDMA0_QM:
+		index = 0;
+		qid_base = GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0;
+		qman_base = mmDCORE0_EDMA0_QM_BASE;
+		break;
+	case GAUDI2_EVENT_HDMA1_QM:
+		index = 1;
+		qid_base = GAUDI2_QUEUE_ID_DCORE0_EDMA_1_0;
+		qman_base = mmDCORE0_EDMA1_QM_BASE;
+		break;
+	case GAUDI2_EVENT_HDMA2_QM:
+		index = 2;
+		qid_base = GAUDI2_QUEUE_ID_DCORE1_EDMA_0_0;
+		qman_base = mmDCORE1_EDMA0_QM_BASE;
+		break;
+	case GAUDI2_EVENT_HDMA3_QM:
+		index = 3;
+		qid_base = GAUDI2_QUEUE_ID_DCORE1_EDMA_1_0;
+		qman_base = mmDCORE1_EDMA1_QM_BASE;
+		break;
+	case GAUDI2_EVENT_HDMA4_QM:
+		index = 4;
+		qid_base = GAUDI2_QUEUE_ID_DCORE2_EDMA_0_0;
+		qman_base = mmDCORE2_EDMA0_QM_BASE;
+		break;
+	case GAUDI2_EVENT_HDMA5_QM:
+		index = 5;
+		qid_base = GAUDI2_QUEUE_ID_DCORE2_EDMA_1_0;
+		qman_base = mmDCORE2_EDMA1_QM_BASE;
+		break;
+	case GAUDI2_EVENT_HDMA6_QM:
+		index = 6;
+		qid_base = GAUDI2_QUEUE_ID_DCORE3_EDMA_0_0;
+		qman_base = mmDCORE3_EDMA0_QM_BASE;
+		break;
+	case GAUDI2_EVENT_HDMA7_QM:
+		index = 7;
+		qid_base = GAUDI2_QUEUE_ID_DCORE3_EDMA_1_0;
+		qman_base = mmDCORE3_EDMA1_QM_BASE;
+		break;
+	case GAUDI2_EVENT_PDMA0_QM:
+		qid_base = GAUDI2_QUEUE_ID_PDMA_0_0;
+		qman_base = mmPDMA0_QM_BASE;
+		break;
+	case GAUDI2_EVENT_PDMA1_QM:
+		qid_base = GAUDI2_QUEUE_ID_PDMA_1_0;
+		qman_base = mmPDMA1_QM_BASE;
+		break;
+	case GAUDI2_EVENT_ROTATOR0_ROT0_QM:
+		qid_base = GAUDI2_QUEUE_ID_ROT_0_0;
+		qman_base = mmROT0_QM_BASE;
+		break;
+	case GAUDI2_EVENT_ROTATOR1_ROT1_QM:
+		qid_base = GAUDI2_QUEUE_ID_ROT_1_0;
+		qman_base = mmROT1_QM_BASE;
+		break;
+	default:
+		return 0;
+	}
+
+	error_count = gaudi2_handle_qman_err_generic(hdev, event_type, qman_base,
+								qid_base, event_mask);
+
+	/* Handle EDMA QM SEI here because there is no AXI error response event for EDMA */
+	if (event_type >= GAUDI2_EVENT_HDMA2_QM && event_type <= GAUDI2_EVENT_HDMA5_QM) {
+		error_count += _gaudi2_handle_qm_sei_err(hdev, qman_base, event_type);
+		gaudi2_ack_module_razwi_event_handler(hdev, RAZWI_EDMA, index, 0, event_mask);
+	}
+
+	hl_check_for_glbl_errors(hdev);
+
+	return error_count;
+}
+
+static int gaudi2_handle_arc_farm_sei_err(struct hl_device *hdev, u16 event_type, u64 *event_mask)
+{
+	u32 i, sts_val, sts_clr_val, error_count = 0, arc_farm;
+
+	for (arc_farm = 0 ; arc_farm < NUM_OF_ARC_FARMS_ARC ; arc_farm++) {
+		sts_clr_val = 0;
+		sts_val = RREG32(mmARC_FARM_ARC0_AUX_ARC_SEI_INTR_STS +
+				(arc_farm * ARC_FARM_OFFSET));
+
+		for (i = 0 ; i < GAUDI2_NUM_OF_ARC_SEI_ERR_CAUSE ; i++) {
+			if (sts_val & BIT(i)) {
+				gaudi2_print_event(hdev, event_type, true,
+						"ARC FARM ARC %u err cause: %s",
+						arc_farm, gaudi2_arc_sei_error_cause[i]);
+				sts_clr_val |= BIT(i);
+				error_count++;
+			}
+		}
+		WREG32(mmARC_FARM_ARC0_AUX_ARC_SEI_INTR_CLR + (arc_farm * ARC_FARM_OFFSET),
+				sts_clr_val);
+	}
+
+	gaudi2_ack_module_razwi_event_handler(hdev, RAZWI_ARC_FARM, 0, 0, event_mask);
+	hl_check_for_glbl_errors(hdev);
+
+	return error_count;
+}
+
+static int gaudi2_handle_cpu_sei_err(struct hl_device *hdev, u16 event_type)
+{
+	u32 i, sts_val, sts_clr_val = 0, error_count = 0;
+
+	sts_val = RREG32(mmCPU_IF_CPU_SEI_INTR_STS);
+
+	for (i = 0 ; i < GAUDI2_NUM_OF_CPU_SEI_ERR_CAUSE ; i++) {
+		if (sts_val & BIT(i)) {
+			gaudi2_print_event(hdev, event_type, true,
+				"err cause: %s", gaudi2_cpu_sei_error_cause[i]);
+			sts_clr_val |= BIT(i);
+			error_count++;
+		}
+	}
+
+	hl_check_for_glbl_errors(hdev);
+
+	WREG32(mmCPU_IF_CPU_SEI_INTR_CLR, sts_clr_val);
+
+	return error_count;
+}
+
+static int gaudi2_handle_rot_err(struct hl_device *hdev, u8 rot_index, u16 event_type,
+					struct hl_eq_razwi_with_intr_cause *razwi_with_intr_cause,
+					u64 *event_mask)
+{
+	u64 intr_cause_data = le64_to_cpu(razwi_with_intr_cause->intr_cause.intr_cause_data);
+	u32 error_count = 0;
+	int i;
+
+	for (i = 0 ; i < GAUDI2_NUM_OF_ROT_ERR_CAUSE ; i++)
+		if (intr_cause_data & BIT(i)) {
+			gaudi2_print_event(hdev, event_type, true,
+				"err cause: %s", guadi2_rot_error_cause[i]);
+			error_count++;
+		}
+
+	/* check if RAZWI happened */
+	gaudi2_ack_module_razwi_event_handler(hdev, RAZWI_ROT, rot_index, 0, event_mask);
+	hl_check_for_glbl_errors(hdev);
+
+	return error_count;
+}
+
+static int gaudi2_tpc_ack_interrupts(struct hl_device *hdev,  u8 tpc_index, u16 event_type,
+					struct hl_eq_razwi_with_intr_cause *razwi_with_intr_cause,
+					u64 *event_mask)
+{
+	u64 intr_cause_data = le64_to_cpu(razwi_with_intr_cause->intr_cause.intr_cause_data);
+	u32 error_count = 0;
+	int i;
+
+	for (i = 0 ; i < GAUDI2_NUM_OF_TPC_INTR_CAUSE ; i++)
+		if (intr_cause_data & BIT(i)) {
+			gaudi2_print_event(hdev, event_type, true,
+				"interrupt cause: %s",  gaudi2_tpc_interrupts_cause[i]);
+			error_count++;
+		}
+
+	/* check if RAZWI happened */
+	gaudi2_ack_module_razwi_event_handler(hdev, RAZWI_TPC, tpc_index, 0, event_mask);
+	hl_check_for_glbl_errors(hdev);
+
+	return error_count;
+}
+
+static int gaudi2_handle_dec_err(struct hl_device *hdev, u8 dec_index, u16 event_type,
+					u64 *event_mask)
+{
+	u32 sts_addr, sts_val, sts_clr_val = 0, error_count = 0;
+	int i;
+
+	if (dec_index < NUM_OF_VDEC_PER_DCORE * NUM_OF_DCORES)
+		/* DCORE DEC */
+		sts_addr = mmDCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR +
+				DCORE_OFFSET * (dec_index / NUM_OF_DEC_PER_DCORE) +
+				DCORE_VDEC_OFFSET * (dec_index % NUM_OF_DEC_PER_DCORE);
+	else
+		/* PCIE DEC */
+		sts_addr = mmPCIE_VDEC0_BRDG_CTRL_CAUSE_INTR + PCIE_VDEC_OFFSET *
+				(dec_index - NUM_OF_VDEC_PER_DCORE * NUM_OF_DCORES);
+
+	sts_val = RREG32(sts_addr);
+
+	for (i = 0 ; i < GAUDI2_NUM_OF_DEC_ERR_CAUSE ; i++) {
+		if (sts_val & BIT(i)) {
+			gaudi2_print_event(hdev, event_type, true,
+				"err cause: %s", gaudi2_dec_error_cause[i]);
+			sts_clr_val |= BIT(i);
+			error_count++;
+		}
+	}
+
+	/* check if RAZWI happened */
+	gaudi2_ack_module_razwi_event_handler(hdev, RAZWI_DEC, dec_index, 0, event_mask);
+	hl_check_for_glbl_errors(hdev);
+
+	/* Write 1 clear errors */
+	WREG32(sts_addr, sts_clr_val);
+
+	return error_count;
+}
+
+static int gaudi2_handle_mme_err(struct hl_device *hdev, u8 mme_index, u16 event_type,
+					u64 *event_mask)
+{
+	u32 sts_addr, sts_val, sts_clr_addr, sts_clr_val = 0, error_count = 0;
+	int i;
+
+	sts_addr = mmDCORE0_MME_CTRL_LO_INTR_CAUSE + DCORE_OFFSET * mme_index;
+	sts_clr_addr = mmDCORE0_MME_CTRL_LO_INTR_CLEAR + DCORE_OFFSET * mme_index;
+
+	sts_val = RREG32(sts_addr);
+
+	for (i = 0 ; i < GAUDI2_NUM_OF_MME_ERR_CAUSE ; i++) {
+		if (sts_val & BIT(i)) {
+			gaudi2_print_event(hdev, event_type, true,
+				"err cause: %s", guadi2_mme_error_cause[i]);
+			sts_clr_val |= BIT(i);
+			error_count++;
+		}
+	}
+
+	/* check if RAZWI happened */
+	for (i = MME_WRITE ; i < MME_INITIATORS_MAX ; i++)
+		gaudi2_ack_module_razwi_event_handler(hdev, RAZWI_MME, mme_index, i, event_mask);
+
+	hl_check_for_glbl_errors(hdev);
+
+	WREG32(sts_clr_addr, sts_clr_val);
+
+	return error_count;
+}
+
+static int gaudi2_handle_mme_sbte_err(struct hl_device *hdev, u16 event_type)
+{
+	/*
+	 * We have a single error cause here but the report mechanism is
+	 * buggy. Hence there is no good reason to fetch the cause so we
+	 * just check for glbl_errors and exit.
+	 */
+	hl_check_for_glbl_errors(hdev);
+
+	return GAUDI2_NA_EVENT_CAUSE;
+}
+
+static int gaudi2_handle_mme_wap_err(struct hl_device *hdev, u8 mme_index, u16 event_type,
+					u64 *event_mask)
+{
+	u32 sts_addr, sts_val, sts_clr_addr, sts_clr_val = 0, error_count = 0;
+	int i;
+
+	sts_addr = mmDCORE0_MME_ACC_INTR_CAUSE + DCORE_OFFSET * mme_index;
+	sts_clr_addr = mmDCORE0_MME_ACC_INTR_CLEAR + DCORE_OFFSET * mme_index;
+
+	sts_val = RREG32(sts_addr);
+
+	for (i = 0 ; i < GAUDI2_NUM_OF_MME_WAP_ERR_CAUSE ; i++) {
+		if (sts_val & BIT(i)) {
+			gaudi2_print_event(hdev, event_type, true,
+				"err cause: %s", guadi2_mme_wap_error_cause[i]);
+			sts_clr_val |= BIT(i);
+			error_count++;
+		}
+	}
+
+	/* check if RAZWI happened on WAP0/1 */
+	gaudi2_ack_module_razwi_event_handler(hdev, RAZWI_MME, mme_index, MME_WAP0, event_mask);
+	gaudi2_ack_module_razwi_event_handler(hdev, RAZWI_MME, mme_index, MME_WAP1, event_mask);
+	hl_check_for_glbl_errors(hdev);
+
+	WREG32(sts_clr_addr, sts_clr_val);
+
+	return error_count;
+}
+
+static int gaudi2_handle_kdma_core_event(struct hl_device *hdev, u16 event_type,
+					u64 intr_cause_data)
+{
+	u32 error_count = 0;
+	int i;
+
+	/* If an AXI read or write error is received, an error is reported and
+	 * interrupt message is sent. Due to an HW errata, when reading the cause
+	 * register of the KDMA engine, the reported error is always HBW even if
+	 * the actual error caused by a LBW KDMA transaction.
+	 */
+	for (i = 0 ; i < GAUDI2_NUM_OF_DMA_CORE_INTR_CAUSE ; i++)
+		if (intr_cause_data & BIT(i)) {
+			gaudi2_print_event(hdev, event_type, true,
+				"err cause: %s", gaudi2_kdma_core_interrupts_cause[i]);
+			error_count++;
+		}
+
+	hl_check_for_glbl_errors(hdev);
+
+	return error_count;
+}
+
+static int gaudi2_handle_dma_core_event(struct hl_device *hdev, u16 event_type, u64 intr_cause)
+{
+	u32 error_count = 0;
+	int i;
+
+	for (i = 0 ; i < GAUDI2_NUM_OF_DMA_CORE_INTR_CAUSE ; i++)
+		if (intr_cause & BIT(i)) {
+			gaudi2_print_event(hdev, event_type, true,
+				"err cause: %s", gaudi2_dma_core_interrupts_cause[i]);
+			error_count++;
+		}
+
+	hl_check_for_glbl_errors(hdev);
+
+	return error_count;
+}
+
+static void gaudi2_print_pcie_mstr_rr_mstr_if_razwi_info(struct hl_device *hdev, u64 *event_mask)
+{
+	u32 mstr_if_base_addr = mmPCIE_MSTR_RR_MSTR_IF_RR_SHRD_HBW_BASE, razwi_happened_addr;
+
+	razwi_happened_addr = mstr_if_base_addr + RR_SHRD_HBW_AW_RAZWI_HAPPENED;
+	if (RREG32(razwi_happened_addr)) {
+		gaudi2_razwi_rr_hbw_shared_printf_info(hdev, mstr_if_base_addr, true, "PCIE",
+							GAUDI2_ENGINE_ID_PCIE, event_mask);
+		WREG32(razwi_happened_addr, 0x1);
+	}
+
+	razwi_happened_addr = mstr_if_base_addr + RR_SHRD_HBW_AR_RAZWI_HAPPENED;
+	if (RREG32(razwi_happened_addr)) {
+		gaudi2_razwi_rr_hbw_shared_printf_info(hdev, mstr_if_base_addr, false, "PCIE",
+							GAUDI2_ENGINE_ID_PCIE, event_mask);
+		WREG32(razwi_happened_addr, 0x1);
+	}
+
+	razwi_happened_addr = mstr_if_base_addr + RR_SHRD_LBW_AW_RAZWI_HAPPENED;
+	if (RREG32(razwi_happened_addr)) {
+		gaudi2_razwi_rr_lbw_shared_printf_info(hdev, mstr_if_base_addr, true, "PCIE",
+							GAUDI2_ENGINE_ID_PCIE, event_mask);
+		WREG32(razwi_happened_addr, 0x1);
+	}
+
+	razwi_happened_addr = mstr_if_base_addr + RR_SHRD_LBW_AR_RAZWI_HAPPENED;
+	if (RREG32(razwi_happened_addr)) {
+		gaudi2_razwi_rr_lbw_shared_printf_info(hdev, mstr_if_base_addr, false, "PCIE",
+							GAUDI2_ENGINE_ID_PCIE, event_mask);
+		WREG32(razwi_happened_addr, 0x1);
+	}
+}
+
+static int gaudi2_print_pcie_addr_dec_info(struct hl_device *hdev, u16 event_type,
+					u64 intr_cause_data, u64 *event_mask)
+{
+	u32 error_count = 0;
+	int i;
+
+	for (i = 0 ; i < GAUDI2_NUM_OF_PCIE_ADDR_DEC_ERR_CAUSE ; i++) {
+		if (!(intr_cause_data & BIT_ULL(i)))
+			continue;
+
+		gaudi2_print_event(hdev, event_type, true,
+			"err cause: %s", gaudi2_pcie_addr_dec_error_cause[i]);
+		error_count++;
+
+		switch (intr_cause_data & BIT_ULL(i)) {
+		case PCIE_WRAP_PCIE_IC_SEI_INTR_IND_AXI_LBW_ERR_INTR_MASK:
+			hl_check_for_glbl_errors(hdev);
+			break;
+		case PCIE_WRAP_PCIE_IC_SEI_INTR_IND_BAD_ACCESS_INTR_MASK:
+			gaudi2_print_pcie_mstr_rr_mstr_if_razwi_info(hdev, event_mask);
+			break;
+		}
+	}
+
+	return error_count;
+}
+
+static int gaudi2_handle_pif_fatal(struct hl_device *hdev, u16 event_type,
+				u64 intr_cause_data)
+
+{
+	u32 error_count = 0;
+	int i;
+
+	for (i = 0 ; i < GAUDI2_NUM_OF_PMMU_FATAL_ERR_CAUSE ; i++) {
+		if (intr_cause_data & BIT_ULL(i)) {
+			gaudi2_print_event(hdev, event_type, true,
+				"err cause: %s", gaudi2_pmmu_fatal_interrupts_cause[i]);
+			error_count++;
+		}
+	}
+
+	return error_count;
+}
+
+static int gaudi2_handle_hif_fatal(struct hl_device *hdev, u16 event_type, u64 intr_cause_data)
+{
+	u32 error_count = 0;
+	int i;
+
+	for (i = 0 ; i < GAUDI2_NUM_OF_HIF_FATAL_ERR_CAUSE ; i++) {
+		if (intr_cause_data & BIT_ULL(i)) {
+			gaudi2_print_event(hdev, event_type, true,
+				"err cause: %s", gaudi2_hif_fatal_interrupts_cause[i]);
+			error_count++;
+		}
+	}
+
+	return error_count;
+}
+
+static void gaudi2_handle_page_error(struct hl_device *hdev, u64 mmu_base, bool is_pmmu,
+					u64 *event_mask)
+{
+	u32 valid, val;
+	u64 addr;
+
+	valid = RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID));
+
+	if (!(valid & DCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID_PAGE_ERR_VALID_ENTRY_MASK))
+		return;
+
+	val = RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE));
+	addr = val & DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA_63_32_MASK;
+	addr <<= 32;
+	addr |= RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA));
+
+	if (is_pmmu) {
+		dev_err_ratelimited(hdev->dev, "PMMU page fault on va 0x%llx\n", addr);
+	} else {
+		addr = gaudi2_mmu_descramble_addr(hdev, addr);
+		addr &= HW_UNSCRAMBLED_BITS_MASK;
+		dev_err_ratelimited(hdev->dev, "HMMU page fault on va range 0x%llx - 0x%llx\n",
+				addr, addr + ~HW_UNSCRAMBLED_BITS_MASK);
+	}
+
+	hl_handle_page_fault(hdev, addr, 0, is_pmmu, event_mask);
+
+	WREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID), 0);
+}
+
+static void gaudi2_handle_access_error(struct hl_device *hdev, u64 mmu_base, bool is_pmmu)
+{
+	u32 valid, val;
+	u64 addr;
+
+	valid = RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID));
+
+	if (!(valid & DCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID_ACCESS_ERR_VALID_ENTRY_MASK))
+		return;
+
+	val = RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE));
+	addr = val & DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA_63_32_MASK;
+	addr <<= 32;
+	addr |= RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA));
+
+	if (!is_pmmu)
+		addr = gaudi2_mmu_descramble_addr(hdev, addr);
+
+	dev_err_ratelimited(hdev->dev, "%s access error on va 0x%llx\n",
+				is_pmmu ? "PMMU" : "HMMU", addr);
+	WREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID), 0);
+}
+
+static int gaudi2_handle_mmu_spi_sei_generic(struct hl_device *hdev, u16 event_type,
+						u64 mmu_base, bool is_pmmu, u64 *event_mask)
+{
+	u32 spi_sei_cause, interrupt_clr = 0x0, error_count = 0;
+	int i;
+
+	spi_sei_cause = RREG32(mmu_base + MMU_SPI_SEI_CAUSE_OFFSET);
+
+	for (i = 0 ; i < GAUDI2_NUM_OF_MMU_SPI_SEI_CAUSE ; i++) {
+		if (spi_sei_cause & BIT(i)) {
+			gaudi2_print_event(hdev, event_type, true,
+				"err cause: %s", gaudi2_mmu_spi_sei[i].cause);
+
+			if (i == 0)
+				gaudi2_handle_page_error(hdev, mmu_base, is_pmmu, event_mask);
+			else if (i == 1)
+				gaudi2_handle_access_error(hdev, mmu_base, is_pmmu);
+
+			if (gaudi2_mmu_spi_sei[i].clear_bit >= 0)
+				interrupt_clr |= BIT(gaudi2_mmu_spi_sei[i].clear_bit);
+
+			error_count++;
+		}
+	}
+
+	/* Clear cause */
+	WREG32_AND(mmu_base + MMU_SPI_SEI_CAUSE_OFFSET, ~spi_sei_cause);
+
+	/* Clear interrupt */
+	WREG32(mmu_base + MMU_INTERRUPT_CLR_OFFSET, interrupt_clr);
+
+	return error_count;
+}
+
+static int gaudi2_handle_sm_err(struct hl_device *hdev, u16 event_type, u8 sm_index)
+{
+	u32 sei_cause_addr, sei_cause_val, sei_cause_cause, sei_cause_log,
+		cq_intr_addr, cq_intr_val, cq_intr_queue_index, error_count = 0;
+	int i;
+
+	sei_cause_addr = mmDCORE0_SYNC_MNGR_GLBL_SM_SEI_CAUSE + DCORE_OFFSET * sm_index;
+	cq_intr_addr = mmDCORE0_SYNC_MNGR_GLBL_CQ_INTR + DCORE_OFFSET * sm_index;
+
+	sei_cause_val = RREG32(sei_cause_addr);
+	sei_cause_cause = FIELD_GET(DCORE0_SYNC_MNGR_GLBL_SM_SEI_CAUSE_CAUSE_MASK, sei_cause_val);
+	cq_intr_val = RREG32(cq_intr_addr);
+
+	/* SEI interrupt */
+	if (sei_cause_cause) {
+		/* There are corresponding SEI_CAUSE_log bits for every SEI_CAUSE_cause bit */
+		sei_cause_log = FIELD_GET(DCORE0_SYNC_MNGR_GLBL_SM_SEI_CAUSE_LOG_MASK,
+					sei_cause_val);
+
+		for (i = 0 ; i < GAUDI2_NUM_OF_SM_SEI_ERR_CAUSE ; i++) {
+			if (!(sei_cause_cause & BIT(i)))
+				continue;
+
+			gaudi2_print_event(hdev, event_type, true,
+				"err cause: %s. %s: 0x%X",
+				gaudi2_sm_sei_cause[i].cause_name,
+				gaudi2_sm_sei_cause[i].log_name,
+				sei_cause_log);
+			error_count++;
+			break;
+		}
+
+		/* Clear SM_SEI_CAUSE */
+		WREG32(sei_cause_addr, 0);
+	}
+
+	/* CQ interrupt */
+	if (cq_intr_val & DCORE0_SYNC_MNGR_GLBL_CQ_INTR_CQ_SEC_INTR_MASK) {
+		cq_intr_queue_index =
+				FIELD_GET(DCORE0_SYNC_MNGR_GLBL_CQ_INTR_CQ_INTR_QUEUE_INDEX_MASK,
+					cq_intr_val);
+
+		dev_err_ratelimited(hdev->dev, "SM%u err. err cause: CQ_INTR. queue index: %u\n",
+				sm_index, cq_intr_queue_index);
+		error_count++;
+
+		/* Clear CQ_INTR */
+		WREG32(cq_intr_addr, 0);
+	}
+
+	hl_check_for_glbl_errors(hdev);
+
+	return error_count;
+}
+
+static u64 get_hmmu_base(u16 event_type)
+{
+	u8 dcore, index_in_dcore;
+
+	switch (event_type) {
+	case GAUDI2_EVENT_HMMU_0_AXI_ERR_RSP:
+	case GAUDI2_EVENT_HMMU0_SPI_BASE ... GAUDI2_EVENT_HMMU0_SECURITY_ERROR:
+		dcore = 0;
+		index_in_dcore = 0;
+	break;
+	case GAUDI2_EVENT_HMMU_1_AXI_ERR_RSP:
+	case GAUDI2_EVENT_HMMU1_SPI_BASE ... GAUDI2_EVENT_HMMU1_SECURITY_ERROR:
+		dcore = 1;
+		index_in_dcore = 0;
+	break;
+	case GAUDI2_EVENT_HMMU_2_AXI_ERR_RSP:
+	case GAUDI2_EVENT_HMMU2_SPI_BASE ... GAUDI2_EVENT_HMMU2_SECURITY_ERROR:
+		dcore = 0;
+		index_in_dcore = 1;
+	break;
+	case GAUDI2_EVENT_HMMU_3_AXI_ERR_RSP:
+	case GAUDI2_EVENT_HMMU3_SPI_BASE ... GAUDI2_EVENT_HMMU3_SECURITY_ERROR:
+		dcore = 1;
+		index_in_dcore = 1;
+	break;
+	case GAUDI2_EVENT_HMMU_4_AXI_ERR_RSP:
+	case GAUDI2_EVENT_HMMU4_SPI_BASE ... GAUDI2_EVENT_HMMU4_SECURITY_ERROR:
+		dcore = 3;
+		index_in_dcore = 2;
+	break;
+	case GAUDI2_EVENT_HMMU_5_AXI_ERR_RSP:
+	case GAUDI2_EVENT_HMMU5_SPI_BASE ... GAUDI2_EVENT_HMMU5_SECURITY_ERROR:
+		dcore = 2;
+		index_in_dcore = 2;
+	break;
+	case GAUDI2_EVENT_HMMU_6_AXI_ERR_RSP:
+	case GAUDI2_EVENT_HMMU6_SPI_BASE ... GAUDI2_EVENT_HMMU6_SECURITY_ERROR:
+		dcore = 3;
+		index_in_dcore = 3;
+	break;
+	case GAUDI2_EVENT_HMMU_7_AXI_ERR_RSP:
+	case GAUDI2_EVENT_HMMU7_SPI_BASE ... GAUDI2_EVENT_HMMU7_SECURITY_ERROR:
+		dcore = 2;
+		index_in_dcore = 3;
+	break;
+	case GAUDI2_EVENT_HMMU_8_AXI_ERR_RSP:
+	case GAUDI2_EVENT_HMMU8_SPI_BASE ... GAUDI2_EVENT_HMMU8_SECURITY_ERROR:
+		dcore = 0;
+		index_in_dcore = 2;
+	break;
+	case GAUDI2_EVENT_HMMU_9_AXI_ERR_RSP:
+	case GAUDI2_EVENT_HMMU9_SPI_BASE ... GAUDI2_EVENT_HMMU9_SECURITY_ERROR:
+		dcore = 1;
+		index_in_dcore = 2;
+	break;
+	case GAUDI2_EVENT_HMMU_10_AXI_ERR_RSP:
+	case GAUDI2_EVENT_HMMU10_SPI_BASE ... GAUDI2_EVENT_HMMU10_SECURITY_ERROR:
+		dcore = 0;
+		index_in_dcore = 3;
+	break;
+	case GAUDI2_EVENT_HMMU_11_AXI_ERR_RSP:
+	case GAUDI2_EVENT_HMMU11_SPI_BASE ... GAUDI2_EVENT_HMMU11_SECURITY_ERROR:
+		dcore = 1;
+		index_in_dcore = 3;
+	break;
+	case GAUDI2_EVENT_HMMU_12_AXI_ERR_RSP:
+	case GAUDI2_EVENT_HMMU12_SPI_BASE ... GAUDI2_EVENT_HMMU12_SECURITY_ERROR:
+		dcore = 3;
+		index_in_dcore = 0;
+	break;
+	case GAUDI2_EVENT_HMMU_13_AXI_ERR_RSP:
+	case GAUDI2_EVENT_HMMU13_SPI_BASE ... GAUDI2_EVENT_HMMU13_SECURITY_ERROR:
+		dcore = 2;
+		index_in_dcore = 0;
+	break;
+	case GAUDI2_EVENT_HMMU_14_AXI_ERR_RSP:
+	case GAUDI2_EVENT_HMMU14_SPI_BASE ... GAUDI2_EVENT_HMMU14_SECURITY_ERROR:
+		dcore = 3;
+		index_in_dcore = 1;
+	break;
+	case GAUDI2_EVENT_HMMU_15_AXI_ERR_RSP:
+	case GAUDI2_EVENT_HMMU15_SPI_BASE ... GAUDI2_EVENT_HMMU15_SECURITY_ERROR:
+		dcore = 2;
+		index_in_dcore = 1;
+	break;
+	default:
+		return ULONG_MAX;
+	}
+
+	return mmDCORE0_HMMU0_MMU_BASE + dcore * DCORE_OFFSET + index_in_dcore * DCORE_HMMU_OFFSET;
+}
+
+static int gaudi2_handle_mmu_spi_sei_err(struct hl_device *hdev, u16 event_type, u64 *event_mask)
+{
+	bool is_pmmu = false;
+	u32 error_count = 0;
+	u64 mmu_base;
+
+	switch (event_type) {
+	case GAUDI2_EVENT_HMMU_0_AXI_ERR_RSP ... GAUDI2_EVENT_HMMU_12_AXI_ERR_RSP:
+	case GAUDI2_EVENT_HMMU0_SPI_BASE ... GAUDI2_EVENT_HMMU12_SECURITY_ERROR:
+		mmu_base = get_hmmu_base(event_type);
+		break;
+
+	case GAUDI2_EVENT_PMMU0_PAGE_FAULT_WR_PERM ... GAUDI2_EVENT_PMMU0_SECURITY_ERROR:
+	case GAUDI2_EVENT_PMMU_AXI_ERR_RSP_0:
+		is_pmmu = true;
+		mmu_base = mmPMMU_HBW_MMU_BASE;
+		break;
+	default:
+		return 0;
+	}
+
+	if (mmu_base == ULONG_MAX)
+		return 0;
+
+	error_count = gaudi2_handle_mmu_spi_sei_generic(hdev, event_type, mmu_base,
+							is_pmmu, event_mask);
+	hl_check_for_glbl_errors(hdev);
+
+	return error_count;
+}
+
+
+/* returns true if hard reset is required (ECC DERR or Read parity), false otherwise (ECC SERR) */
+static bool gaudi2_hbm_sei_handle_read_err(struct hl_device *hdev,
+			struct hl_eq_hbm_sei_read_err_intr_info *rd_err_data, u32 err_cnt)
+{
+	bool require_hard_reset = false;
+	u32 addr, beat, beat_shift;
+
+	dev_err_ratelimited(hdev->dev,
+			"READ ERROR count: ECC SERR: %d, ECC DERR: %d, RD_PARITY: %d\n",
+			FIELD_GET(HBM_ECC_SERR_CNTR_MASK, err_cnt),
+			FIELD_GET(HBM_ECC_DERR_CNTR_MASK, err_cnt),
+			FIELD_GET(HBM_RD_PARITY_CNTR_MASK, err_cnt));
+
+	addr = le32_to_cpu(rd_err_data->dbg_rd_err_addr.rd_addr_val);
+	dev_err_ratelimited(hdev->dev,
+			"READ ERROR address: sid(%u), bg(%u), ba(%u), col(%u), row(%u)\n",
+			FIELD_GET(HBM_RD_ADDR_SID_MASK, addr),
+			FIELD_GET(HBM_RD_ADDR_BG_MASK, addr),
+			FIELD_GET(HBM_RD_ADDR_BA_MASK, addr),
+			FIELD_GET(HBM_RD_ADDR_COL_MASK, addr),
+			FIELD_GET(HBM_RD_ADDR_ROW_MASK, addr));
+
+	/* For each beat (RDQS edge), look for possible errors and print relevant info */
+	for (beat = 0 ; beat < 4 ; beat++) {
+		if (le32_to_cpu(rd_err_data->dbg_rd_err_misc) &
+			(HBM_RD_ERR_SERR_BEAT0_MASK << beat))
+			dev_err_ratelimited(hdev->dev, "Beat%d ECC SERR: DM: %#x, Syndrome: %#x\n",
+						beat,
+						le32_to_cpu(rd_err_data->dbg_rd_err_dm),
+						le32_to_cpu(rd_err_data->dbg_rd_err_syndrome));
+
+		if (le32_to_cpu(rd_err_data->dbg_rd_err_misc) &
+			(HBM_RD_ERR_DERR_BEAT0_MASK << beat)) {
+			dev_err_ratelimited(hdev->dev, "Beat%d ECC DERR: DM: %#x, Syndrome: %#x\n",
+						beat,
+						le32_to_cpu(rd_err_data->dbg_rd_err_dm),
+						le32_to_cpu(rd_err_data->dbg_rd_err_syndrome));
+			require_hard_reset = true;
+		}
+
+		beat_shift = beat * HBM_RD_ERR_BEAT_SHIFT;
+		if (le32_to_cpu(rd_err_data->dbg_rd_err_misc) &
+			(HBM_RD_ERR_PAR_ERR_BEAT0_MASK << beat_shift)) {
+			dev_err_ratelimited(hdev->dev,
+					"Beat%d read PARITY: DM: %#x, PAR data: %#x\n",
+					beat,
+					le32_to_cpu(rd_err_data->dbg_rd_err_dm),
+					(le32_to_cpu(rd_err_data->dbg_rd_err_misc) &
+						(HBM_RD_ERR_PAR_DATA_BEAT0_MASK << beat_shift)) >>
+						(HBM_RD_ERR_PAR_DATA_BEAT0_SHIFT + beat_shift));
+			require_hard_reset = true;
+		}
+
+		dev_err_ratelimited(hdev->dev, "Beat%d DQ data:\n", beat);
+		dev_err_ratelimited(hdev->dev, "\t0x%08x\n",
+					le32_to_cpu(rd_err_data->dbg_rd_err_data[beat * 2]));
+		dev_err_ratelimited(hdev->dev, "\t0x%08x\n",
+					le32_to_cpu(rd_err_data->dbg_rd_err_data[beat * 2 + 1]));
+	}
+
+	return require_hard_reset;
+}
+
+static void gaudi2_hbm_sei_print_wr_par_info(struct hl_device *hdev,
+			struct hl_eq_hbm_sei_wr_par_intr_info *wr_par_err_data, u32 err_cnt)
+{
+	struct hbm_sei_wr_cmd_address *wr_cmd_addr = wr_par_err_data->dbg_last_wr_cmds;
+	u32 i, curr_addr, derr = wr_par_err_data->dbg_derr;
+
+	dev_err_ratelimited(hdev->dev, "WRITE PARITY ERROR count: %d\n", err_cnt);
+
+	dev_err_ratelimited(hdev->dev, "CK-0 DERR: 0x%02x, CK-1 DERR: 0x%02x\n",
+				derr & 0x3, derr & 0xc);
+
+	/* JIRA H6-3286 - the following prints may not be valid */
+	dev_err_ratelimited(hdev->dev, "Last latched write commands addresses:\n");
+	for (i = 0 ; i < HBM_WR_PAR_CMD_LIFO_LEN ; i++) {
+		curr_addr = le32_to_cpu(wr_cmd_addr[i].dbg_wr_cmd_addr);
+		dev_err_ratelimited(hdev->dev,
+				"\twrite cmd[%u]: Address: SID(%u) BG(%u) BA(%u) COL(%u).\n",
+				i,
+				FIELD_GET(WR_PAR_LAST_CMD_SID_MASK, curr_addr),
+				FIELD_GET(WR_PAR_LAST_CMD_BG_MASK, curr_addr),
+				FIELD_GET(WR_PAR_LAST_CMD_BA_MASK, curr_addr),
+				FIELD_GET(WR_PAR_LAST_CMD_COL_MASK, curr_addr));
+	}
+}
+
+static void gaudi2_hbm_sei_print_ca_par_info(struct hl_device *hdev,
+		struct hl_eq_hbm_sei_ca_par_intr_info *ca_par_err_data, u32 err_cnt)
+{
+	__le32 *col_cmd = ca_par_err_data->dbg_col;
+	__le16 *row_cmd = ca_par_err_data->dbg_row;
+	u32 i;
+
+	dev_err_ratelimited(hdev->dev, "CA ERROR count: %d\n", err_cnt);
+
+	dev_err_ratelimited(hdev->dev, "Last latched C&R bus commands:\n");
+	for (i = 0 ; i < HBM_CA_ERR_CMD_LIFO_LEN ; i++)
+		dev_err_ratelimited(hdev->dev, "cmd%u: ROW(0x%04x) COL(0x%05x)\n", i,
+			le16_to_cpu(row_cmd[i]) & (u16)GENMASK(13, 0),
+			le32_to_cpu(col_cmd[i]) & (u32)GENMASK(17, 0));
+}
+
+/* Returns true if hard reset is needed or false otherwise */
+static bool gaudi2_handle_hbm_mc_sei_err(struct hl_device *hdev, u16 event_type,
+					struct hl_eq_hbm_sei_data *sei_data)
+{
+	bool require_hard_reset = false;
+	u32 hbm_id, mc_id, cause_idx;
+
+	hbm_id = (event_type - GAUDI2_EVENT_HBM0_MC0_SEI_SEVERE) / 4;
+	mc_id = ((event_type - GAUDI2_EVENT_HBM0_MC0_SEI_SEVERE) / 2) % 2;
+
+	cause_idx = sei_data->hdr.sei_cause;
+	if (cause_idx > GAUDI2_NUM_OF_HBM_SEI_CAUSE - 1) {
+		gaudi2_print_event(hdev, event_type, true,
+			"err cause: %s",
+			"Invalid HBM SEI event cause (%d) provided by FW", cause_idx);
+		return true;
+	}
+
+	gaudi2_print_event(hdev, event_type, !sei_data->hdr.is_critical,
+		"System %s Error Interrupt - HBM(%u) MC(%u) MC_CH(%u) MC_PC(%u). Error cause: %s",
+		sei_data->hdr.is_critical ? "Critical" : "Non-critical",
+		hbm_id, mc_id, sei_data->hdr.mc_channel, sei_data->hdr.mc_pseudo_channel,
+		hbm_mc_sei_cause[cause_idx]);
+
+	/* Print error-specific info */
+	switch (cause_idx) {
+	case HBM_SEI_CATTRIP:
+		require_hard_reset = true;
+		break;
+
+	case  HBM_SEI_CMD_PARITY_EVEN:
+		gaudi2_hbm_sei_print_ca_par_info(hdev, &sei_data->ca_parity_even_info,
+						le32_to_cpu(sei_data->hdr.cnt));
+		require_hard_reset = true;
+		break;
+
+	case  HBM_SEI_CMD_PARITY_ODD:
+		gaudi2_hbm_sei_print_ca_par_info(hdev, &sei_data->ca_parity_odd_info,
+						le32_to_cpu(sei_data->hdr.cnt));
+		require_hard_reset = true;
+		break;
+
+	case HBM_SEI_WRITE_DATA_PARITY_ERR:
+		gaudi2_hbm_sei_print_wr_par_info(hdev, &sei_data->wr_parity_info,
+						le32_to_cpu(sei_data->hdr.cnt));
+		require_hard_reset = true;
+		break;
+
+	case HBM_SEI_READ_ERR:
+		/* Unlike other SEI events, read error requires further processing of the
+		 * raw data in order to determine the root cause.
+		 */
+		require_hard_reset = gaudi2_hbm_sei_handle_read_err(hdev,
+								&sei_data->read_err_info,
+								le32_to_cpu(sei_data->hdr.cnt));
+		break;
+
+	default:
+		break;
+	}
+
+	require_hard_reset |= !!sei_data->hdr.is_critical;
+
+	return require_hard_reset;
+}
+
+static int gaudi2_handle_hbm_cattrip(struct hl_device *hdev, u16 event_type,
+				u64 intr_cause_data)
+{
+	if (intr_cause_data) {
+		gaudi2_print_event(hdev, event_type, true,
+			"temperature error cause: %#llx", intr_cause_data);
+		return 1;
+	}
+
+	return 0;
+}
+
+static int gaudi2_handle_hbm_mc_spi(struct hl_device *hdev, u64 intr_cause_data)
+{
+	u32 i, error_count = 0;
+
+	for (i = 0 ; i < GAUDI2_NUM_OF_HBM_MC_SPI_CAUSE ; i++)
+		if (intr_cause_data & hbm_mc_spi[i].mask) {
+			dev_dbg(hdev->dev, "HBM spi event: notification cause(%s)\n",
+				hbm_mc_spi[i].cause);
+			error_count++;
+		}
+
+	return error_count;
+}
+
+static void gaudi2_print_clk_change_info(struct hl_device *hdev, u16 event_type, u64 *event_mask)
+{
+	ktime_t zero_time = ktime_set(0, 0);
+
+	mutex_lock(&hdev->clk_throttling.lock);
+
+	switch (event_type) {
+	case GAUDI2_EVENT_CPU_FIX_POWER_ENV_S:
+		hdev->clk_throttling.current_reason |= HL_CLK_THROTTLE_POWER;
+		hdev->clk_throttling.aggregated_reason |= HL_CLK_THROTTLE_POWER;
+		hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_POWER].start = ktime_get();
+		hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_POWER].end = zero_time;
+		dev_dbg_ratelimited(hdev->dev, "Clock throttling due to power consumption\n");
+		break;
+
+	case GAUDI2_EVENT_CPU_FIX_POWER_ENV_E:
+		hdev->clk_throttling.current_reason &= ~HL_CLK_THROTTLE_POWER;
+		hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_POWER].end = ktime_get();
+		dev_dbg_ratelimited(hdev->dev, "Power envelop is safe, back to optimal clock\n");
+		break;
+
+	case GAUDI2_EVENT_CPU_FIX_THERMAL_ENV_S:
+		hdev->clk_throttling.current_reason |= HL_CLK_THROTTLE_THERMAL;
+		hdev->clk_throttling.aggregated_reason |= HL_CLK_THROTTLE_THERMAL;
+		hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_THERMAL].start = ktime_get();
+		hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_THERMAL].end = zero_time;
+		*event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR;
+		dev_info_ratelimited(hdev->dev, "Clock throttling due to overheating\n");
+		break;
+
+	case GAUDI2_EVENT_CPU_FIX_THERMAL_ENV_E:
+		hdev->clk_throttling.current_reason &= ~HL_CLK_THROTTLE_THERMAL;
+		hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_THERMAL].end = ktime_get();
+		*event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR;
+		dev_info_ratelimited(hdev->dev, "Thermal envelop is safe, back to optimal clock\n");
+		break;
+
+	default:
+		dev_err(hdev->dev, "Received invalid clock change event %d\n", event_type);
+		break;
+	}
+
+	mutex_unlock(&hdev->clk_throttling.lock);
+}
+
+static void gaudi2_print_out_of_sync_info(struct hl_device *hdev, u16 event_type,
+					struct cpucp_pkt_sync_err *sync_err)
+{
+	struct hl_hw_queue *q = &hdev->kernel_queues[GAUDI2_QUEUE_ID_CPU_PQ];
+
+	gaudi2_print_event(hdev, event_type, false,
+		"FW: pi=%u, ci=%u, LKD: pi=%u, ci=%d",
+		le32_to_cpu(sync_err->pi), le32_to_cpu(sync_err->ci),
+		q->pi, atomic_read(&q->ci));
+}
+
+static int gaudi2_handle_pcie_p2p_msix(struct hl_device *hdev, u16 event_type)
+{
+	u32 p2p_intr, msix_gw_intr, error_count = 0;
+
+	p2p_intr = RREG32(mmPCIE_WRAP_P2P_INTR);
+	msix_gw_intr = RREG32(mmPCIE_WRAP_MSIX_GW_INTR);
+
+	if (p2p_intr) {
+		gaudi2_print_event(hdev, event_type, true,
+			"pcie p2p transaction terminated due to security, req_id(0x%x)",
+			RREG32(mmPCIE_WRAP_P2P_REQ_ID));
+
+		WREG32(mmPCIE_WRAP_P2P_INTR, 0x1);
+		error_count++;
+	}
+
+	if (msix_gw_intr) {
+		gaudi2_print_event(hdev, event_type, true,
+			"pcie msi-x gen denied due to vector num check failure, vec(0x%X)",
+			RREG32(mmPCIE_WRAP_MSIX_GW_VEC));
+
+		WREG32(mmPCIE_WRAP_MSIX_GW_INTR, 0x1);
+		error_count++;
+	}
+
+	return error_count;
+}
+
+static int gaudi2_handle_pcie_drain(struct hl_device *hdev,
+			struct hl_eq_pcie_drain_ind_data *drain_data)
+{
+	u64 cause, error_count = 0;
+
+	cause = le64_to_cpu(drain_data->intr_cause.intr_cause_data);
+
+	if (cause & BIT_ULL(0)) {
+		dev_err_ratelimited(hdev->dev, "PCIE AXI drain LBW completed\n");
+		error_count++;
+	}
+
+	if (cause & BIT_ULL(1)) {
+		dev_err_ratelimited(hdev->dev, "PCIE AXI drain HBW completed\n");
+		error_count++;
+	}
+
+	return error_count;
+}
+
+static int gaudi2_handle_psoc_drain(struct hl_device *hdev, u64 intr_cause_data)
+{
+	u32 error_count = 0;
+	int i;
+
+	for (i = 0 ; i < GAUDI2_NUM_OF_AXI_DRAIN_ERR_CAUSE ; i++) {
+		if (intr_cause_data & BIT_ULL(i)) {
+			dev_err_ratelimited(hdev->dev, "PSOC %s completed\n",
+				gaudi2_psoc_axi_drain_interrupts_cause[i]);
+			error_count++;
+		}
+	}
+
+	hl_check_for_glbl_errors(hdev);
+
+	return error_count;
+}
+
+static void gaudi2_print_cpu_pkt_failure_info(struct hl_device *hdev, u16 event_type,
+					struct cpucp_pkt_sync_err *sync_err)
+{
+	struct hl_hw_queue *q = &hdev->kernel_queues[GAUDI2_QUEUE_ID_CPU_PQ];
+
+	gaudi2_print_event(hdev, event_type, false,
+		"FW reported sanity check failure, FW: pi=%u, ci=%u, LKD: pi=%u, ci=%d",
+		le32_to_cpu(sync_err->pi), le32_to_cpu(sync_err->ci), q->pi, atomic_read(&q->ci));
+}
+
+static int hl_arc_event_handle(struct hl_device *hdev, u16 event_type,
+					struct hl_eq_engine_arc_intr_data *data)
+{
+	struct hl_engine_arc_dccm_queue_full_irq *q;
+	u32 intr_type, engine_id;
+	u64 payload;
+
+	intr_type = le32_to_cpu(data->intr_type);
+	engine_id = le32_to_cpu(data->engine_id);
+	payload = le64_to_cpu(data->payload);
+
+	switch (intr_type) {
+	case ENGINE_ARC_DCCM_QUEUE_FULL_IRQ:
+		q = (struct hl_engine_arc_dccm_queue_full_irq *) &payload;
+
+		gaudi2_print_event(hdev, event_type, true,
+				"ARC DCCM Full event: Eng: %s, Intr_type: %u, Qidx: %u",
+				GAUDI2_ENG_ID_TO_STR(engine_id), intr_type, q->queue_index);
+		return 1;
+	default:
+		gaudi2_print_event(hdev, event_type, true, "Unknown ARC event type");
+		return 0;
+	}
+}
+
+static u16 event_id_to_engine_id(struct hl_device *hdev, u16 event_type)
+{
+	enum gaudi2_block_types type = GAUDI2_BLOCK_TYPE_MAX;
+	u16 index;
+
+	switch (event_type) {
+	case GAUDI2_EVENT_TPC0_AXI_ERR_RSP ... GAUDI2_EVENT_TPC24_AXI_ERR_RSP:
+		index = event_type - GAUDI2_EVENT_TPC0_AXI_ERR_RSP;
+		type = GAUDI2_BLOCK_TYPE_TPC;
+		break;
+	case GAUDI2_EVENT_TPC0_QM ... GAUDI2_EVENT_TPC24_QM:
+		index = event_type - GAUDI2_EVENT_TPC0_QM;
+		type = GAUDI2_BLOCK_TYPE_TPC;
+		break;
+	case GAUDI2_EVENT_MME0_SBTE0_AXI_ERR_RSP ... GAUDI2_EVENT_MME0_CTRL_AXI_ERROR_RESPONSE:
+	case GAUDI2_EVENT_MME0_SPI_BASE ... GAUDI2_EVENT_MME0_WAP_SOURCE_RESULT_INVALID:
+	case GAUDI2_EVENT_MME0_QM:
+		index = 0;
+		type = GAUDI2_BLOCK_TYPE_MME;
+		break;
+	case GAUDI2_EVENT_MME1_SBTE0_AXI_ERR_RSP ... GAUDI2_EVENT_MME1_CTRL_AXI_ERROR_RESPONSE:
+	case GAUDI2_EVENT_MME1_SPI_BASE ... GAUDI2_EVENT_MME1_WAP_SOURCE_RESULT_INVALID:
+	case GAUDI2_EVENT_MME1_QM:
+		index = 1;
+		type = GAUDI2_BLOCK_TYPE_MME;
+		break;
+	case GAUDI2_EVENT_MME2_SBTE0_AXI_ERR_RSP ... GAUDI2_EVENT_MME2_CTRL_AXI_ERROR_RESPONSE:
+	case GAUDI2_EVENT_MME2_SPI_BASE ... GAUDI2_EVENT_MME2_WAP_SOURCE_RESULT_INVALID:
+	case GAUDI2_EVENT_MME2_QM:
+		index = 2;
+		type = GAUDI2_BLOCK_TYPE_MME;
+		break;
+	case GAUDI2_EVENT_MME3_SBTE0_AXI_ERR_RSP ... GAUDI2_EVENT_MME3_CTRL_AXI_ERROR_RESPONSE:
+	case GAUDI2_EVENT_MME3_SPI_BASE ... GAUDI2_EVENT_MME3_WAP_SOURCE_RESULT_INVALID:
+	case GAUDI2_EVENT_MME3_QM:
+		index = 3;
+		type = GAUDI2_BLOCK_TYPE_MME;
+		break;
+	case GAUDI2_EVENT_KDMA_CH0_AXI_ERR_RSP:
+	case GAUDI2_EVENT_KDMA_BM_SPMU:
+	case GAUDI2_EVENT_KDMA0_CORE:
+		return GAUDI2_ENGINE_ID_KDMA;
+	case GAUDI2_EVENT_PDMA_CH0_AXI_ERR_RSP:
+	case GAUDI2_EVENT_PDMA0_CORE:
+	case GAUDI2_EVENT_PDMA0_BM_SPMU:
+	case GAUDI2_EVENT_PDMA0_QM:
+		return GAUDI2_ENGINE_ID_PDMA_0;
+	case GAUDI2_EVENT_PDMA_CH1_AXI_ERR_RSP:
+	case GAUDI2_EVENT_PDMA1_CORE:
+	case GAUDI2_EVENT_PDMA1_BM_SPMU:
+	case GAUDI2_EVENT_PDMA1_QM:
+		return GAUDI2_ENGINE_ID_PDMA_1;
+	case GAUDI2_EVENT_DEC0_AXI_ERR_RSPONSE ... GAUDI2_EVENT_DEC9_AXI_ERR_RSPONSE:
+		index = event_type - GAUDI2_EVENT_DEC0_AXI_ERR_RSPONSE;
+		type = GAUDI2_BLOCK_TYPE_DEC;
+		break;
+	case GAUDI2_EVENT_DEC0_SPI ... GAUDI2_EVENT_DEC9_BMON_SPMU:
+		index = (event_type - GAUDI2_EVENT_DEC0_SPI) >> 1;
+		type = GAUDI2_BLOCK_TYPE_DEC;
+		break;
+	case GAUDI2_EVENT_NIC0_AXI_ERROR_RESPONSE ... GAUDI2_EVENT_NIC11_AXI_ERROR_RESPONSE:
+		index = event_type - GAUDI2_EVENT_NIC0_AXI_ERROR_RESPONSE;
+		return GAUDI2_ENGINE_ID_NIC0_0 + (index * 2);
+	case GAUDI2_EVENT_NIC0_QM0 ... GAUDI2_EVENT_NIC11_QM1:
+		index = event_type - GAUDI2_EVENT_NIC0_QM0;
+		return GAUDI2_ENGINE_ID_NIC0_0 + index;
+	case GAUDI2_EVENT_NIC0_BMON_SPMU ... GAUDI2_EVENT_NIC11_SW_ERROR:
+		index = event_type - GAUDI2_EVENT_NIC0_BMON_SPMU;
+		return GAUDI2_ENGINE_ID_NIC0_0 + (index * 2);
+	case GAUDI2_EVENT_TPC0_BMON_SPMU ... GAUDI2_EVENT_TPC24_KERNEL_ERR:
+		index = (event_type - GAUDI2_EVENT_TPC0_BMON_SPMU) >> 1;
+		type = GAUDI2_BLOCK_TYPE_TPC;
+		break;
+	case GAUDI2_EVENT_ROTATOR0_AXI_ERROR_RESPONSE:
+	case GAUDI2_EVENT_ROTATOR0_BMON_SPMU:
+	case GAUDI2_EVENT_ROTATOR0_ROT0_QM:
+		return GAUDI2_ENGINE_ID_ROT_0;
+	case GAUDI2_EVENT_ROTATOR1_AXI_ERROR_RESPONSE:
+	case GAUDI2_EVENT_ROTATOR1_BMON_SPMU:
+	case GAUDI2_EVENT_ROTATOR1_ROT1_QM:
+		return GAUDI2_ENGINE_ID_ROT_1;
+	case GAUDI2_EVENT_HDMA0_BM_SPMU:
+	case GAUDI2_EVENT_HDMA0_QM:
+	case GAUDI2_EVENT_HDMA0_CORE:
+		return GAUDI2_DCORE0_ENGINE_ID_EDMA_0;
+	case GAUDI2_EVENT_HDMA1_BM_SPMU:
+	case GAUDI2_EVENT_HDMA1_QM:
+	case GAUDI2_EVENT_HDMA1_CORE:
+		return GAUDI2_DCORE0_ENGINE_ID_EDMA_1;
+	case GAUDI2_EVENT_HDMA2_BM_SPMU:
+	case GAUDI2_EVENT_HDMA2_QM:
+	case GAUDI2_EVENT_HDMA2_CORE:
+		return GAUDI2_DCORE1_ENGINE_ID_EDMA_0;
+	case GAUDI2_EVENT_HDMA3_BM_SPMU:
+	case GAUDI2_EVENT_HDMA3_QM:
+	case GAUDI2_EVENT_HDMA3_CORE:
+		return GAUDI2_DCORE1_ENGINE_ID_EDMA_1;
+	case GAUDI2_EVENT_HDMA4_BM_SPMU:
+	case GAUDI2_EVENT_HDMA4_QM:
+	case GAUDI2_EVENT_HDMA4_CORE:
+		return GAUDI2_DCORE2_ENGINE_ID_EDMA_0;
+	case GAUDI2_EVENT_HDMA5_BM_SPMU:
+	case GAUDI2_EVENT_HDMA5_QM:
+	case GAUDI2_EVENT_HDMA5_CORE:
+		return GAUDI2_DCORE2_ENGINE_ID_EDMA_1;
+	case GAUDI2_EVENT_HDMA6_BM_SPMU:
+	case GAUDI2_EVENT_HDMA6_QM:
+	case GAUDI2_EVENT_HDMA6_CORE:
+		return GAUDI2_DCORE3_ENGINE_ID_EDMA_0;
+	case GAUDI2_EVENT_HDMA7_BM_SPMU:
+	case GAUDI2_EVENT_HDMA7_QM:
+	case GAUDI2_EVENT_HDMA7_CORE:
+		return GAUDI2_DCORE3_ENGINE_ID_EDMA_1;
+	default:
+		break;
+	}
+
+	switch (type) {
+	case GAUDI2_BLOCK_TYPE_TPC:
+		switch (index) {
+		case TPC_ID_DCORE0_TPC0 ... TPC_ID_DCORE0_TPC5:
+			return GAUDI2_DCORE0_ENGINE_ID_TPC_0 + index;
+		case TPC_ID_DCORE1_TPC0 ... TPC_ID_DCORE1_TPC5:
+			return GAUDI2_DCORE1_ENGINE_ID_TPC_0 + index - TPC_ID_DCORE1_TPC0;
+		case TPC_ID_DCORE2_TPC0 ... TPC_ID_DCORE2_TPC5:
+			return GAUDI2_DCORE2_ENGINE_ID_TPC_0 + index - TPC_ID_DCORE2_TPC0;
+		case TPC_ID_DCORE3_TPC0 ... TPC_ID_DCORE3_TPC5:
+			return GAUDI2_DCORE3_ENGINE_ID_TPC_0 + index - TPC_ID_DCORE3_TPC0;
+		default:
+			break;
+		}
+		break;
+	case GAUDI2_BLOCK_TYPE_MME:
+		switch (index) {
+		case MME_ID_DCORE0: return GAUDI2_DCORE0_ENGINE_ID_MME;
+		case MME_ID_DCORE1: return GAUDI2_DCORE1_ENGINE_ID_MME;
+		case MME_ID_DCORE2: return GAUDI2_DCORE2_ENGINE_ID_MME;
+		case MME_ID_DCORE3: return GAUDI2_DCORE3_ENGINE_ID_MME;
+		default:
+			break;
+		}
+		break;
+	case GAUDI2_BLOCK_TYPE_DEC:
+		switch (index) {
+		case DEC_ID_DCORE0_DEC0: return GAUDI2_DCORE0_ENGINE_ID_DEC_0;
+		case DEC_ID_DCORE0_DEC1: return GAUDI2_DCORE0_ENGINE_ID_DEC_1;
+		case DEC_ID_DCORE1_DEC0: return GAUDI2_DCORE1_ENGINE_ID_DEC_0;
+		case DEC_ID_DCORE1_DEC1: return GAUDI2_DCORE1_ENGINE_ID_DEC_1;
+		case DEC_ID_DCORE2_DEC0: return GAUDI2_DCORE2_ENGINE_ID_DEC_0;
+		case DEC_ID_DCORE2_DEC1: return GAUDI2_DCORE2_ENGINE_ID_DEC_1;
+		case DEC_ID_DCORE3_DEC0: return GAUDI2_DCORE3_ENGINE_ID_DEC_0;
+		case DEC_ID_DCORE3_DEC1: return GAUDI2_DCORE3_ENGINE_ID_DEC_1;
+		case DEC_ID_PCIE_VDEC0: return GAUDI2_PCIE_ENGINE_ID_DEC_0;
+		case DEC_ID_PCIE_VDEC1: return GAUDI2_PCIE_ENGINE_ID_DEC_1;
+		default:
+			break;
+		}
+		break;
+	default:
+		break;
+	}
+
+	return U16_MAX;
+}
+
+static void gaudi2_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_entry)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	bool reset_required = false, is_critical = false;
+	u32 index, ctl, reset_flags = 0, error_count = 0;
+	u64 event_mask = 0;
+	u16 event_type;
+
+	ctl = le32_to_cpu(eq_entry->hdr.ctl);
+	event_type = ((ctl & EQ_CTL_EVENT_TYPE_MASK) >> EQ_CTL_EVENT_TYPE_SHIFT);
+
+	if (event_type >= GAUDI2_EVENT_SIZE) {
+		dev_err(hdev->dev, "Event type %u exceeds maximum of %u",
+				event_type, GAUDI2_EVENT_SIZE - 1);
+		return;
+	}
+
+	gaudi2->events_stat[event_type]++;
+	gaudi2->events_stat_aggregate[event_type]++;
+
+	switch (event_type) {
+	case GAUDI2_EVENT_PCIE_CORE_SERR ... GAUDI2_EVENT_ARC0_ECC_DERR:
+		fallthrough;
+	case GAUDI2_EVENT_ROTATOR0_SERR ... GAUDI2_EVENT_ROTATOR1_DERR:
+		reset_flags |= HL_DRV_RESET_FW_FATAL_ERR;
+		event_mask |= HL_NOTIFIER_EVENT_GENERAL_HW_ERR;
+		reset_required = gaudi2_handle_ecc_event(hdev, event_type, &eq_entry->ecc_data);
+		is_critical = eq_entry->ecc_data.is_critical;
+		error_count++;
+		break;
+
+	case GAUDI2_EVENT_TPC0_QM ... GAUDI2_EVENT_PDMA1_QM:
+		fallthrough;
+	case GAUDI2_EVENT_ROTATOR0_ROT0_QM ... GAUDI2_EVENT_ROTATOR1_ROT1_QM:
+		fallthrough;
+	case GAUDI2_EVENT_NIC0_QM0 ... GAUDI2_EVENT_NIC11_QM1:
+		error_count = gaudi2_handle_qman_err(hdev, event_type, &event_mask);
+		event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR;
+		break;
+
+	case GAUDI2_EVENT_ARC_AXI_ERROR_RESPONSE_0:
+		error_count = gaudi2_handle_arc_farm_sei_err(hdev, event_type, &event_mask);
+		event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR;
+		break;
+
+	case GAUDI2_EVENT_CPU_AXI_ERR_RSP:
+		error_count = gaudi2_handle_cpu_sei_err(hdev, event_type);
+		reset_flags |= HL_DRV_RESET_FW_FATAL_ERR;
+		event_mask |= HL_NOTIFIER_EVENT_CRITICL_FW_ERR;
+		break;
+
+	case GAUDI2_EVENT_PDMA_CH0_AXI_ERR_RSP:
+	case GAUDI2_EVENT_PDMA_CH1_AXI_ERR_RSP:
+		error_count = gaudi2_handle_qm_sei_err(hdev, event_type, true, &event_mask);
+		event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR;
+		break;
+
+	case GAUDI2_EVENT_ROTATOR0_AXI_ERROR_RESPONSE:
+	case GAUDI2_EVENT_ROTATOR1_AXI_ERROR_RESPONSE:
+		index = event_type - GAUDI2_EVENT_ROTATOR0_AXI_ERROR_RESPONSE;
+		error_count = gaudi2_handle_rot_err(hdev, index, event_type,
+					&eq_entry->razwi_with_intr_cause, &event_mask);
+		error_count += gaudi2_handle_qm_sei_err(hdev, event_type, false, &event_mask);
+		event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR;
+		break;
+
+	case GAUDI2_EVENT_TPC0_AXI_ERR_RSP ... GAUDI2_EVENT_TPC24_AXI_ERR_RSP:
+		index = event_type - GAUDI2_EVENT_TPC0_AXI_ERR_RSP;
+		error_count = gaudi2_tpc_ack_interrupts(hdev, index, event_type,
+						&eq_entry->razwi_with_intr_cause, &event_mask);
+		error_count += gaudi2_handle_qm_sei_err(hdev, event_type, false, &event_mask);
+		event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR;
+		break;
+
+	case GAUDI2_EVENT_DEC0_AXI_ERR_RSPONSE ... GAUDI2_EVENT_DEC9_AXI_ERR_RSPONSE:
+		index = event_type - GAUDI2_EVENT_DEC0_AXI_ERR_RSPONSE;
+		error_count = gaudi2_handle_dec_err(hdev, index, event_type, &event_mask);
+		event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR;
+		break;
+
+	case GAUDI2_EVENT_TPC0_KERNEL_ERR:
+	case GAUDI2_EVENT_TPC1_KERNEL_ERR:
+	case GAUDI2_EVENT_TPC2_KERNEL_ERR:
+	case GAUDI2_EVENT_TPC3_KERNEL_ERR:
+	case GAUDI2_EVENT_TPC4_KERNEL_ERR:
+	case GAUDI2_EVENT_TPC5_KERNEL_ERR:
+	case GAUDI2_EVENT_TPC6_KERNEL_ERR:
+	case GAUDI2_EVENT_TPC7_KERNEL_ERR:
+	case GAUDI2_EVENT_TPC8_KERNEL_ERR:
+	case GAUDI2_EVENT_TPC9_KERNEL_ERR:
+	case GAUDI2_EVENT_TPC10_KERNEL_ERR:
+	case GAUDI2_EVENT_TPC11_KERNEL_ERR:
+	case GAUDI2_EVENT_TPC12_KERNEL_ERR:
+	case GAUDI2_EVENT_TPC13_KERNEL_ERR:
+	case GAUDI2_EVENT_TPC14_KERNEL_ERR:
+	case GAUDI2_EVENT_TPC15_KERNEL_ERR:
+	case GAUDI2_EVENT_TPC16_KERNEL_ERR:
+	case GAUDI2_EVENT_TPC17_KERNEL_ERR:
+	case GAUDI2_EVENT_TPC18_KERNEL_ERR:
+	case GAUDI2_EVENT_TPC19_KERNEL_ERR:
+	case GAUDI2_EVENT_TPC20_KERNEL_ERR:
+	case GAUDI2_EVENT_TPC21_KERNEL_ERR:
+	case GAUDI2_EVENT_TPC22_KERNEL_ERR:
+	case GAUDI2_EVENT_TPC23_KERNEL_ERR:
+	case GAUDI2_EVENT_TPC24_KERNEL_ERR:
+		index = (event_type - GAUDI2_EVENT_TPC0_KERNEL_ERR) /
+			(GAUDI2_EVENT_TPC1_KERNEL_ERR - GAUDI2_EVENT_TPC0_KERNEL_ERR);
+		error_count = gaudi2_tpc_ack_interrupts(hdev, index, event_type,
+					&eq_entry->razwi_with_intr_cause, &event_mask);
+		event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR;
+		break;
+
+	case GAUDI2_EVENT_DEC0_SPI:
+	case GAUDI2_EVENT_DEC1_SPI:
+	case GAUDI2_EVENT_DEC2_SPI:
+	case GAUDI2_EVENT_DEC3_SPI:
+	case GAUDI2_EVENT_DEC4_SPI:
+	case GAUDI2_EVENT_DEC5_SPI:
+	case GAUDI2_EVENT_DEC6_SPI:
+	case GAUDI2_EVENT_DEC7_SPI:
+	case GAUDI2_EVENT_DEC8_SPI:
+	case GAUDI2_EVENT_DEC9_SPI:
+		index = (event_type - GAUDI2_EVENT_DEC0_SPI) /
+				(GAUDI2_EVENT_DEC1_SPI - GAUDI2_EVENT_DEC0_SPI);
+		error_count = gaudi2_handle_dec_err(hdev, index, event_type, &event_mask);
+		event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR;
+		break;
+
+	case GAUDI2_EVENT_MME0_CTRL_AXI_ERROR_RESPONSE:
+	case GAUDI2_EVENT_MME1_CTRL_AXI_ERROR_RESPONSE:
+	case GAUDI2_EVENT_MME2_CTRL_AXI_ERROR_RESPONSE:
+	case GAUDI2_EVENT_MME3_CTRL_AXI_ERROR_RESPONSE:
+		index = (event_type - GAUDI2_EVENT_MME0_CTRL_AXI_ERROR_RESPONSE) /
+				(GAUDI2_EVENT_MME1_CTRL_AXI_ERROR_RESPONSE -
+						GAUDI2_EVENT_MME0_CTRL_AXI_ERROR_RESPONSE);
+		error_count = gaudi2_handle_mme_err(hdev, index, event_type, &event_mask);
+		error_count += gaudi2_handle_qm_sei_err(hdev, event_type, false, &event_mask);
+		event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR;
+		break;
+
+	case GAUDI2_EVENT_MME0_QMAN_SW_ERROR:
+	case GAUDI2_EVENT_MME1_QMAN_SW_ERROR:
+	case GAUDI2_EVENT_MME2_QMAN_SW_ERROR:
+	case GAUDI2_EVENT_MME3_QMAN_SW_ERROR:
+		index = (event_type - GAUDI2_EVENT_MME0_QMAN_SW_ERROR) /
+				(GAUDI2_EVENT_MME1_QMAN_SW_ERROR -
+					GAUDI2_EVENT_MME0_QMAN_SW_ERROR);
+		error_count = gaudi2_handle_mme_err(hdev, index, event_type, &event_mask);
+		event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR;
+		break;
+
+	case GAUDI2_EVENT_MME0_WAP_SOURCE_RESULT_INVALID:
+	case GAUDI2_EVENT_MME1_WAP_SOURCE_RESULT_INVALID:
+	case GAUDI2_EVENT_MME2_WAP_SOURCE_RESULT_INVALID:
+	case GAUDI2_EVENT_MME3_WAP_SOURCE_RESULT_INVALID:
+		index = (event_type - GAUDI2_EVENT_MME0_WAP_SOURCE_RESULT_INVALID) /
+				(GAUDI2_EVENT_MME1_WAP_SOURCE_RESULT_INVALID -
+					GAUDI2_EVENT_MME0_WAP_SOURCE_RESULT_INVALID);
+		error_count = gaudi2_handle_mme_wap_err(hdev, index, event_type, &event_mask);
+		event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR;
+		break;
+
+	case GAUDI2_EVENT_KDMA_CH0_AXI_ERR_RSP:
+	case GAUDI2_EVENT_KDMA0_CORE:
+		error_count = gaudi2_handle_kdma_core_event(hdev, event_type,
+				le64_to_cpu(eq_entry->intr_cause.intr_cause_data));
+		event_mask |= HL_NOTIFIER_EVENT_GENERAL_HW_ERR;
+		break;
+
+	case GAUDI2_EVENT_HDMA2_CORE ... GAUDI2_EVENT_HDMA5_CORE:
+		error_count = gaudi2_handle_dma_core_event(hdev, event_type,
+				le64_to_cpu(eq_entry->intr_cause.intr_cause_data));
+		event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR;
+		break;
+
+	case GAUDI2_EVENT_PDMA0_CORE ... GAUDI2_EVENT_PDMA1_CORE:
+		error_count = gaudi2_handle_dma_core_event(hdev, event_type,
+				le64_to_cpu(eq_entry->intr_cause.intr_cause_data));
+		event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR;
+		break;
+
+	case GAUDI2_EVENT_PCIE_ADDR_DEC_ERR:
+		error_count = gaudi2_print_pcie_addr_dec_info(hdev, event_type,
+				le64_to_cpu(eq_entry->intr_cause.intr_cause_data), &event_mask);
+		reset_flags |= HL_DRV_RESET_FW_FATAL_ERR;
+		event_mask |= HL_NOTIFIER_EVENT_GENERAL_HW_ERR;
+		break;
+
+	case GAUDI2_EVENT_HMMU0_PAGE_FAULT_OR_WR_PERM ... GAUDI2_EVENT_HMMU12_SECURITY_ERROR:
+	case GAUDI2_EVENT_HMMU_0_AXI_ERR_RSP ... GAUDI2_EVENT_HMMU_12_AXI_ERR_RSP:
+	case GAUDI2_EVENT_PMMU0_PAGE_FAULT_WR_PERM ... GAUDI2_EVENT_PMMU0_SECURITY_ERROR:
+	case GAUDI2_EVENT_PMMU_AXI_ERR_RSP_0:
+		error_count = gaudi2_handle_mmu_spi_sei_err(hdev, event_type, &event_mask);
+		reset_flags |= HL_DRV_RESET_FW_FATAL_ERR;
+		event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR;
+		break;
+
+	case GAUDI2_EVENT_HIF0_FATAL ... GAUDI2_EVENT_HIF12_FATAL:
+		error_count = gaudi2_handle_hif_fatal(hdev, event_type,
+				le64_to_cpu(eq_entry->intr_cause.intr_cause_data));
+		reset_flags |= HL_DRV_RESET_FW_FATAL_ERR;
+		event_mask |= HL_NOTIFIER_EVENT_GENERAL_HW_ERR;
+		break;
+
+	case GAUDI2_EVENT_PMMU_FATAL_0:
+		error_count = gaudi2_handle_pif_fatal(hdev, event_type,
+				le64_to_cpu(eq_entry->intr_cause.intr_cause_data));
+		reset_flags |= HL_DRV_RESET_FW_FATAL_ERR;
+		event_mask |= HL_NOTIFIER_EVENT_GENERAL_HW_ERR;
+		break;
+
+	case GAUDI2_EVENT_PSOC63_RAZWI_OR_PID_MIN_MAX_INTERRUPT:
+		error_count = gaudi2_ack_psoc_razwi_event_handler(hdev, &event_mask);
+		event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR;
+		break;
+
+	case GAUDI2_EVENT_HBM0_MC0_SEI_SEVERE ... GAUDI2_EVENT_HBM5_MC1_SEI_NON_SEVERE:
+		event_mask |= HL_NOTIFIER_EVENT_GENERAL_HW_ERR;
+		if (gaudi2_handle_hbm_mc_sei_err(hdev, event_type, &eq_entry->sei_data)) {
+			reset_flags |= HL_DRV_RESET_FW_FATAL_ERR;
+			reset_required = true;
+			is_critical = eq_entry->sei_data.hdr.is_critical;
+		}
+		error_count++;
+		break;
+
+	case GAUDI2_EVENT_HBM_CATTRIP_0 ... GAUDI2_EVENT_HBM_CATTRIP_5:
+		error_count = gaudi2_handle_hbm_cattrip(hdev, event_type,
+				le64_to_cpu(eq_entry->intr_cause.intr_cause_data));
+		event_mask |= HL_NOTIFIER_EVENT_GENERAL_HW_ERR;
+		break;
+
+	case GAUDI2_EVENT_HBM0_MC0_SPI ... GAUDI2_EVENT_HBM5_MC1_SPI:
+		error_count = gaudi2_handle_hbm_mc_spi(hdev,
+				le64_to_cpu(eq_entry->intr_cause.intr_cause_data));
+		event_mask |= HL_NOTIFIER_EVENT_GENERAL_HW_ERR;
+		break;
+
+	case GAUDI2_EVENT_PCIE_DRAIN_COMPLETE:
+		error_count = gaudi2_handle_pcie_drain(hdev, &eq_entry->pcie_drain_ind_data);
+		reset_flags |= HL_DRV_RESET_FW_FATAL_ERR;
+		event_mask |= HL_NOTIFIER_EVENT_GENERAL_HW_ERR;
+		if (hl_fw_version_cmp(hdev, 1, 13, 0) >= 0)
+			is_critical = true;
+		break;
+
+	case GAUDI2_EVENT_PSOC59_RPM_ERROR_OR_DRAIN:
+		error_count = gaudi2_handle_psoc_drain(hdev,
+				le64_to_cpu(eq_entry->intr_cause.intr_cause_data));
+		reset_flags |= HL_DRV_RESET_FW_FATAL_ERR;
+		event_mask |= HL_NOTIFIER_EVENT_GENERAL_HW_ERR;
+		break;
+
+	case GAUDI2_EVENT_CPU_AXI_ECC:
+		error_count = GAUDI2_NA_EVENT_CAUSE;
+		reset_flags |= HL_DRV_RESET_FW_FATAL_ERR;
+		event_mask |= HL_NOTIFIER_EVENT_GENERAL_HW_ERR;
+		break;
+	case GAUDI2_EVENT_CPU_L2_RAM_ECC:
+		error_count = GAUDI2_NA_EVENT_CAUSE;
+		reset_flags |= HL_DRV_RESET_FW_FATAL_ERR;
+		event_mask |= HL_NOTIFIER_EVENT_GENERAL_HW_ERR;
+		break;
+	case GAUDI2_EVENT_MME0_SBTE0_AXI_ERR_RSP ... GAUDI2_EVENT_MME0_SBTE4_AXI_ERR_RSP:
+	case GAUDI2_EVENT_MME1_SBTE0_AXI_ERR_RSP ... GAUDI2_EVENT_MME1_SBTE4_AXI_ERR_RSP:
+	case GAUDI2_EVENT_MME2_SBTE0_AXI_ERR_RSP ... GAUDI2_EVENT_MME2_SBTE4_AXI_ERR_RSP:
+	case GAUDI2_EVENT_MME3_SBTE0_AXI_ERR_RSP ... GAUDI2_EVENT_MME3_SBTE4_AXI_ERR_RSP:
+		error_count = gaudi2_handle_mme_sbte_err(hdev, event_type);
+		event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR;
+		break;
+	case GAUDI2_EVENT_VM0_ALARM_A ... GAUDI2_EVENT_VM3_ALARM_B:
+		error_count = GAUDI2_NA_EVENT_CAUSE;
+		reset_flags |= HL_DRV_RESET_FW_FATAL_ERR;
+		event_mask |= HL_NOTIFIER_EVENT_GENERAL_HW_ERR;
+		break;
+	case GAUDI2_EVENT_PSOC_AXI_ERR_RSP:
+		error_count = GAUDI2_NA_EVENT_CAUSE;
+		reset_flags |= HL_DRV_RESET_FW_FATAL_ERR;
+		event_mask |= HL_NOTIFIER_EVENT_GENERAL_HW_ERR;
+		break;
+	case GAUDI2_EVENT_PSOC_PRSTN_FALL:
+		error_count = GAUDI2_NA_EVENT_CAUSE;
+		event_mask |= HL_NOTIFIER_EVENT_GENERAL_HW_ERR;
+		break;
+	case GAUDI2_EVENT_PCIE_APB_TIMEOUT:
+		error_count = GAUDI2_NA_EVENT_CAUSE;
+		reset_flags |= HL_DRV_RESET_FW_FATAL_ERR;
+		event_mask |= HL_NOTIFIER_EVENT_GENERAL_HW_ERR;
+		break;
+	case GAUDI2_EVENT_PCIE_FATAL_ERR:
+		error_count = GAUDI2_NA_EVENT_CAUSE;
+		reset_flags |= HL_DRV_RESET_FW_FATAL_ERR;
+		event_mask |= HL_NOTIFIER_EVENT_GENERAL_HW_ERR;
+		break;
+	case GAUDI2_EVENT_TPC0_BMON_SPMU:
+	case GAUDI2_EVENT_TPC1_BMON_SPMU:
+	case GAUDI2_EVENT_TPC2_BMON_SPMU:
+	case GAUDI2_EVENT_TPC3_BMON_SPMU:
+	case GAUDI2_EVENT_TPC4_BMON_SPMU:
+	case GAUDI2_EVENT_TPC5_BMON_SPMU:
+	case GAUDI2_EVENT_TPC6_BMON_SPMU:
+	case GAUDI2_EVENT_TPC7_BMON_SPMU:
+	case GAUDI2_EVENT_TPC8_BMON_SPMU:
+	case GAUDI2_EVENT_TPC9_BMON_SPMU:
+	case GAUDI2_EVENT_TPC10_BMON_SPMU:
+	case GAUDI2_EVENT_TPC11_BMON_SPMU:
+	case GAUDI2_EVENT_TPC12_BMON_SPMU:
+	case GAUDI2_EVENT_TPC13_BMON_SPMU:
+	case GAUDI2_EVENT_TPC14_BMON_SPMU:
+	case GAUDI2_EVENT_TPC15_BMON_SPMU:
+	case GAUDI2_EVENT_TPC16_BMON_SPMU:
+	case GAUDI2_EVENT_TPC17_BMON_SPMU:
+	case GAUDI2_EVENT_TPC18_BMON_SPMU:
+	case GAUDI2_EVENT_TPC19_BMON_SPMU:
+	case GAUDI2_EVENT_TPC20_BMON_SPMU:
+	case GAUDI2_EVENT_TPC21_BMON_SPMU:
+	case GAUDI2_EVENT_TPC22_BMON_SPMU:
+	case GAUDI2_EVENT_TPC23_BMON_SPMU:
+	case GAUDI2_EVENT_TPC24_BMON_SPMU:
+	case GAUDI2_EVENT_MME0_CTRL_BMON_SPMU:
+	case GAUDI2_EVENT_MME0_SBTE_BMON_SPMU:
+	case GAUDI2_EVENT_MME0_WAP_BMON_SPMU:
+	case GAUDI2_EVENT_MME1_CTRL_BMON_SPMU:
+	case GAUDI2_EVENT_MME1_SBTE_BMON_SPMU:
+	case GAUDI2_EVENT_MME1_WAP_BMON_SPMU:
+	case GAUDI2_EVENT_MME2_CTRL_BMON_SPMU:
+	case GAUDI2_EVENT_MME2_SBTE_BMON_SPMU:
+	case GAUDI2_EVENT_MME2_WAP_BMON_SPMU:
+	case GAUDI2_EVENT_MME3_CTRL_BMON_SPMU:
+	case GAUDI2_EVENT_MME3_SBTE_BMON_SPMU:
+	case GAUDI2_EVENT_MME3_WAP_BMON_SPMU:
+	case GAUDI2_EVENT_HDMA2_BM_SPMU ... GAUDI2_EVENT_PDMA1_BM_SPMU:
+		fallthrough;
+	case GAUDI2_EVENT_DEC0_BMON_SPMU:
+	case GAUDI2_EVENT_DEC1_BMON_SPMU:
+	case GAUDI2_EVENT_DEC2_BMON_SPMU:
+	case GAUDI2_EVENT_DEC3_BMON_SPMU:
+	case GAUDI2_EVENT_DEC4_BMON_SPMU:
+	case GAUDI2_EVENT_DEC5_BMON_SPMU:
+	case GAUDI2_EVENT_DEC6_BMON_SPMU:
+	case GAUDI2_EVENT_DEC7_BMON_SPMU:
+	case GAUDI2_EVENT_DEC8_BMON_SPMU:
+	case GAUDI2_EVENT_DEC9_BMON_SPMU:
+	case GAUDI2_EVENT_ROTATOR0_BMON_SPMU ... GAUDI2_EVENT_SM3_BMON_SPMU:
+		error_count = GAUDI2_NA_EVENT_CAUSE;
+		event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR;
+		break;
+
+	case GAUDI2_EVENT_CPU_FIX_POWER_ENV_S:
+	case GAUDI2_EVENT_CPU_FIX_POWER_ENV_E:
+	case GAUDI2_EVENT_CPU_FIX_THERMAL_ENV_S:
+	case GAUDI2_EVENT_CPU_FIX_THERMAL_ENV_E:
+		gaudi2_print_clk_change_info(hdev, event_type, &event_mask);
+		error_count = GAUDI2_NA_EVENT_CAUSE;
+		break;
+
+	case GAUDI2_EVENT_CPU_PKT_QUEUE_OUT_SYNC:
+		gaudi2_print_out_of_sync_info(hdev, event_type, &eq_entry->pkt_sync_err);
+		error_count = GAUDI2_NA_EVENT_CAUSE;
+		reset_flags |= HL_DRV_RESET_FW_FATAL_ERR;
+		event_mask |= HL_NOTIFIER_EVENT_GENERAL_HW_ERR;
+		break;
+
+	case GAUDI2_EVENT_PCIE_FLR_REQUESTED:
+		event_mask |= HL_NOTIFIER_EVENT_GENERAL_HW_ERR;
+		error_count = GAUDI2_NA_EVENT_CAUSE;
+		/* Do nothing- FW will handle it */
+		break;
+
+	case GAUDI2_EVENT_PCIE_P2P_MSIX:
+		error_count = gaudi2_handle_pcie_p2p_msix(hdev, event_type);
+		event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR;
+		break;
+
+	case GAUDI2_EVENT_SM0_AXI_ERROR_RESPONSE ... GAUDI2_EVENT_SM3_AXI_ERROR_RESPONSE:
+		index = event_type - GAUDI2_EVENT_SM0_AXI_ERROR_RESPONSE;
+		error_count = gaudi2_handle_sm_err(hdev, event_type, index);
+		event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR;
+		break;
+
+	case GAUDI2_EVENT_PSOC_MME_PLL_LOCK_ERR ... GAUDI2_EVENT_DCORE2_HBM_PLL_LOCK_ERR:
+		error_count = GAUDI2_NA_EVENT_CAUSE;
+		event_mask |= HL_NOTIFIER_EVENT_GENERAL_HW_ERR;
+		break;
+
+	case GAUDI2_EVENT_CPU_CPLD_SHUTDOWN_CAUSE:
+		dev_info(hdev->dev, "CPLD shutdown cause, reset reason: 0x%llx\n",
+						le64_to_cpu(eq_entry->data[0]));
+		error_count = GAUDI2_NA_EVENT_CAUSE;
+		event_mask |= HL_NOTIFIER_EVENT_GENERAL_HW_ERR;
+		break;
+	case GAUDI2_EVENT_CPU_CPLD_SHUTDOWN_EVENT:
+		dev_err(hdev->dev, "CPLD shutdown event, reset reason: 0x%llx\n",
+						le64_to_cpu(eq_entry->data[0]));
+		error_count = GAUDI2_NA_EVENT_CAUSE;
+		hl_eq_cpld_shutdown_event_handle(hdev, event_type, &event_mask);
+		break;
+
+	case GAUDI2_EVENT_CPU_PKT_SANITY_FAILED:
+		gaudi2_print_cpu_pkt_failure_info(hdev, event_type, &eq_entry->pkt_sync_err);
+		error_count = GAUDI2_NA_EVENT_CAUSE;
+		reset_flags |= HL_DRV_RESET_FW_FATAL_ERR;
+		event_mask |= HL_NOTIFIER_EVENT_GENERAL_HW_ERR;
+		break;
+
+	case GAUDI2_EVENT_ARC_DCCM_FULL:
+		error_count = hl_arc_event_handle(hdev, event_type, &eq_entry->arc_data);
+		event_mask |= HL_NOTIFIER_EVENT_USER_ENGINE_ERR;
+		break;
+
+	case GAUDI2_EVENT_CPU_FP32_NOT_SUPPORTED:
+	case GAUDI2_EVENT_CPU_DEV_RESET_REQ:
+		event_mask |= HL_NOTIFIER_EVENT_GENERAL_HW_ERR;
+		error_count = GAUDI2_NA_EVENT_CAUSE;
+		is_critical = true;
+		break;
+
+	case GAUDI2_EVENT_ARC_PWR_BRK_ENTRY:
+	case GAUDI2_EVENT_ARC_PWR_BRK_EXT:
+	case GAUDI2_EVENT_ARC_PWR_RD_MODE0:
+	case GAUDI2_EVENT_ARC_PWR_RD_MODE1:
+	case GAUDI2_EVENT_ARC_PWR_RD_MODE2:
+	case GAUDI2_EVENT_ARC_PWR_RD_MODE3:
+		error_count = GAUDI2_NA_EVENT_CAUSE;
+		dev_info_ratelimited(hdev->dev, "%s event received\n",
+					gaudi2_irq_map_table[event_type].name);
+		break;
+
+	case GAUDI2_EVENT_ARC_EQ_HEARTBEAT:
+		hl_eq_heartbeat_event_handle(hdev);
+		error_count = GAUDI2_NA_EVENT_CAUSE;
+		break;
+	default:
+		if (gaudi2_irq_map_table[event_type].valid) {
+			dev_err_ratelimited(hdev->dev, "Cannot find handler for event %d\n",
+						event_type);
+			error_count = GAUDI2_NA_EVENT_CAUSE;
+		}
+	}
+
+	if (event_mask & HL_NOTIFIER_EVENT_USER_ENGINE_ERR)
+		hl_capture_engine_err(hdev, event_id_to_engine_id(hdev, event_type), error_count);
+
+	/* Make sure to dump an error in case no error cause was printed so far.
+	 * Note that although we have counted the errors, we use this number as
+	 * a boolean.
+	 */
+	if (error_count == GAUDI2_NA_EVENT_CAUSE && !is_info_event(event_type))
+		gaudi2_print_event(hdev, event_type, true, "%d", event_type);
+	else if (error_count == 0)
+		gaudi2_print_event(hdev, event_type, true,
+				"No error cause for H/W event %u", event_type);
+
+	if ((gaudi2_irq_map_table[event_type].reset != EVENT_RESET_TYPE_NONE) || reset_required) {
+		if (reset_required ||
+				(gaudi2_irq_map_table[event_type].reset == EVENT_RESET_TYPE_HARD))
+			reset_flags |= HL_DRV_RESET_HARD;
+
+		if (hdev->hard_reset_on_fw_events ||
+				(hdev->asic_prop.fw_security_enabled && is_critical))
+			goto reset_device;
+	}
+
+	/* Send unmask irq only for interrupts not classified as MSG */
+	if (!gaudi2_irq_map_table[event_type].msg)
+		hl_fw_unmask_irq(hdev, event_type);
+
+	if (event_mask)
+		hl_notifier_event_send_all(hdev, event_mask);
+
+	return;
+
+reset_device:
+	if (hdev->asic_prop.fw_security_enabled && is_critical) {
+		reset_flags |= HL_DRV_RESET_BYPASS_REQ_TO_FW;
+		event_mask |= HL_NOTIFIER_EVENT_DEVICE_UNAVAILABLE;
+	} else {
+		reset_flags |= HL_DRV_RESET_DELAY;
+	}
+	/* escalate general hw errors to critical/fatal error */
+	if (event_mask & HL_NOTIFIER_EVENT_GENERAL_HW_ERR)
+		hl_handle_critical_hw_err(hdev, event_type, &event_mask);
+
+	hl_debugfs_cfg_access_history_dump(hdev);
+	event_mask |= HL_NOTIFIER_EVENT_DEVICE_RESET;
+	hl_device_cond_reset(hdev, reset_flags, event_mask);
+}
+
+static int gaudi2_memset_memory_chunk_using_edma_qm(struct hl_device *hdev,
+			struct packet_lin_dma *lin_dma_pkt,
+			u64 phys_addr, u32 hw_queue_id, u32 size, u64 addr, u32 val)
+{
+	u32 ctl, pkt_size;
+	int rc = 0, i;
+
+	ctl = FIELD_PREP(GAUDI2_PKT_CTL_OPCODE_MASK, PACKET_LIN_DMA);
+	ctl |= FIELD_PREP(GAUDI2_PKT_LIN_DMA_CTL_MEMSET_MASK, 1);
+	ctl |= FIELD_PREP(GAUDI2_PKT_LIN_DMA_CTL_WRCOMP_MASK, 1);
+	ctl |= FIELD_PREP(GAUDI2_PKT_CTL_EB_MASK, 1);
+
+	lin_dma_pkt->ctl = cpu_to_le32(ctl);
+	lin_dma_pkt->src_addr = cpu_to_le64(val);
+	lin_dma_pkt->dst_addr = cpu_to_le64(addr);
+	lin_dma_pkt->tsize = cpu_to_le32(size);
+
+	pkt_size = sizeof(struct packet_lin_dma);
+
+	for (i = 0; i < 3; i++) {
+		rc = hdev->asic_funcs->access_dev_mem(hdev, PCI_REGION_DRAM,
+				phys_addr + (i * sizeof(u64)),
+				((u64 *)(lin_dma_pkt)) + i, DEBUGFS_WRITE64);
+		if (rc) {
+			dev_err(hdev->dev, "Failed to copy lin_dma packet to HBM (%#llx)\n",
+				phys_addr);
+			return rc;
+		}
+	}
+
+	rc = hl_hw_queue_send_cb_no_cmpl(hdev, hw_queue_id, pkt_size, phys_addr);
+	if (rc)
+		dev_err(hdev->dev, "Failed to send lin_dma packet to H/W queue %s\n",
+				GAUDI2_QUEUE_ID_TO_STR(hw_queue_id));
+
+	return rc;
+}
+
+static int gaudi2_memset_device_memory(struct hl_device *hdev, u64 addr, u64 size, u64 val)
+{
+	u32 edma_queues_id[] = {GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0,
+					GAUDI2_QUEUE_ID_DCORE1_EDMA_0_0,
+					GAUDI2_QUEUE_ID_DCORE2_EDMA_0_0,
+					GAUDI2_QUEUE_ID_DCORE3_EDMA_0_0};
+	u32 chunk_size, dcore, edma_idx, sob_offset, sob_addr, comp_val,
+		old_mmubp, mmubp, num_of_pkts, busy, pkt_size, cb_len;
+	u64 comp_addr, cur_addr = addr, end_addr = addr + size;
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	int rc = 0, dma_num = 0, i;
+	void *lin_dma_pkts_arr;
+
+	if (prop->edma_enabled_mask == 0) {
+		dev_info(hdev->dev, "non of the EDMA engines is enabled - skip dram scrubbing\n");
+		return -EIO;
+	}
+
+	sob_offset = hdev->asic_prop.first_available_user_sob[0] * 4;
+	sob_addr = mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 + sob_offset;
+	comp_addr = CFG_BASE + sob_addr;
+	comp_val = FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_INC_MASK, 1) |
+		FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_VAL_MASK, 1);
+	mmubp = FIELD_PREP(ARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP_WR_MASK, 1) |
+		FIELD_PREP(ARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP_RD_MASK, 1);
+
+	/* Calculate how many lin dma pkts we'll need */
+	num_of_pkts = div64_u64(round_up(size, SZ_2G), SZ_2G);
+	pkt_size = sizeof(struct packet_lin_dma);
+	cb_len = pkt_size * num_of_pkts;
+
+	/*
+	 * if we're not scrubing HMMU or NIC reserved sections in hbm,
+	 * then it the scrubing of the user section, as we use the start of the user section
+	 * to store the CB of the EDMA QM, so shift the start address of the scrubbing accordingly
+	 * and scrub the CB section before leaving this function.
+	 */
+	if ((addr >= prop->dram_user_base_address) &&
+				(addr < prop->dram_user_base_address + cb_len))
+		cur_addr += (prop->dram_user_base_address + cb_len) - addr;
+
+	lin_dma_pkts_arr = kvcalloc(num_of_pkts, pkt_size, GFP_KERNEL);
+	if (!lin_dma_pkts_arr)
+		return -ENOMEM;
+
+	/*
+	 * set mmu bypass for the scrubbing - all ddmas are configured the same so save
+	 * only the first one to restore later
+	 * also set the sob addr for all edma cores for completion.
+	 * set QM as trusted to allow it to access physical address with MMU bp.
+	 */
+	old_mmubp = RREG32(mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_MMU_BP);
+	for (dcore = 0 ; dcore < NUM_OF_DCORES ; dcore++) {
+		for (edma_idx = 0 ; edma_idx < NUM_OF_EDMA_PER_DCORE ; edma_idx++) {
+			u32 edma_offset = dcore * DCORE_OFFSET + edma_idx * DCORE_EDMA_OFFSET;
+			u32 edma_bit = dcore * NUM_OF_EDMA_PER_DCORE + edma_idx;
+
+			if (!(prop->edma_enabled_mask & BIT(edma_bit)))
+				continue;
+
+			WREG32(mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_MMU_BP +
+					edma_offset, mmubp);
+			WREG32(mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_LO + edma_offset,
+					lower_32_bits(comp_addr));
+			WREG32(mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_HI + edma_offset,
+					upper_32_bits(comp_addr));
+			WREG32(mmDCORE0_EDMA0_CORE_CTX_WR_COMP_WDATA + edma_offset,
+					comp_val);
+			gaudi2_qman_set_test_mode(hdev,
+					edma_queues_id[dcore] + 4 * edma_idx, true);
+		}
+	}
+
+	WREG32(sob_addr, 0);
+
+	while (cur_addr < end_addr) {
+		for (dcore = 0 ; dcore < NUM_OF_DCORES ; dcore++) {
+			for (edma_idx = 0 ; edma_idx < NUM_OF_EDMA_PER_DCORE ; edma_idx++) {
+				u32 edma_bit = dcore * NUM_OF_EDMA_PER_DCORE + edma_idx;
+
+				if (!(prop->edma_enabled_mask & BIT(edma_bit)))
+					continue;
+
+				chunk_size = min_t(u64, SZ_2G, end_addr - cur_addr);
+
+				rc = gaudi2_memset_memory_chunk_using_edma_qm(hdev,
+					(struct packet_lin_dma *)lin_dma_pkts_arr + dma_num,
+					prop->dram_user_base_address + (dma_num * pkt_size),
+					edma_queues_id[dcore] + edma_idx * 4,
+					chunk_size, cur_addr, val);
+				if (rc)
+					goto end;
+
+				dma_num++;
+				cur_addr += chunk_size;
+				if (cur_addr == end_addr)
+					goto edma_wait;
+			}
+		}
+	}
+
+edma_wait:
+	rc = hl_poll_timeout(hdev, sob_addr, busy, (busy == dma_num), 1000, 1000000);
+	if (rc) {
+		dev_err(hdev->dev, "DMA Timeout during HBM scrubbing(sob: 0x%x, dma_num: 0x%x)\n",
+						busy, dma_num);
+		goto end;
+	}
+end:
+	for (dcore = 0 ; dcore < NUM_OF_DCORES ; dcore++) {
+		for (edma_idx = 0 ; edma_idx < NUM_OF_EDMA_PER_DCORE ; edma_idx++) {
+			u32 edma_offset = dcore * DCORE_OFFSET + edma_idx * DCORE_EDMA_OFFSET;
+			u32 edma_bit = dcore * NUM_OF_EDMA_PER_DCORE + edma_idx;
+
+			if (!(prop->edma_enabled_mask & BIT(edma_bit)))
+				continue;
+
+			WREG32(mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_MMU_BP + edma_offset, old_mmubp);
+			WREG32(mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_LO + edma_offset, 0);
+			WREG32(mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_HI + edma_offset, 0);
+			WREG32(mmDCORE0_EDMA0_CORE_CTX_WR_COMP_WDATA + edma_offset, 0);
+			gaudi2_qman_set_test_mode(hdev,
+					edma_queues_id[dcore] + 4 * edma_idx, false);
+		}
+	}
+
+	memset(lin_dma_pkts_arr, 0, sizeof(u64));
+
+	/* Zero the HBM area where we copied the CB */
+	for (i = 0; i < cb_len / sizeof(u64); i += sizeof(u64))
+		rc = hdev->asic_funcs->access_dev_mem(hdev, PCI_REGION_DRAM,
+			prop->dram_user_base_address + i,
+				(u64 *)(lin_dma_pkts_arr), DEBUGFS_WRITE64);
+	WREG32(sob_addr, 0);
+
+	kvfree(lin_dma_pkts_arr);
+
+	return rc;
+}
+
+static int gaudi2_scrub_device_dram(struct hl_device *hdev, u64 val)
+{
+	int rc;
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	u64 size = prop->dram_end_address - prop->dram_user_base_address;
+
+	rc = gaudi2_memset_device_memory(hdev, prop->dram_user_base_address, size, val);
+
+	if (rc)
+		dev_err(hdev->dev, "Failed to scrub dram, address: 0x%llx size: %llu\n",
+				prop->dram_user_base_address, size);
+	return rc;
+}
+
+static int gaudi2_scrub_device_mem(struct hl_device *hdev)
+{
+	int rc;
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	u64 val = hdev->memory_scrub_val;
+	u64 addr, size;
+
+	if (!hdev->memory_scrub)
+		return 0;
+
+	/* scrub SRAM */
+	addr = prop->sram_user_base_address;
+	size = hdev->pldm ? 0x10000 : (prop->sram_size - SRAM_USER_BASE_OFFSET);
+	dev_dbg(hdev->dev, "Scrubbing SRAM: 0x%09llx - 0x%09llx, val: 0x%llx\n",
+			addr, addr + size, val);
+	rc = gaudi2_memset_device_memory(hdev, addr, size, val);
+	if (rc) {
+		dev_err(hdev->dev, "scrubbing SRAM failed (%d)\n", rc);
+		return rc;
+	}
+
+	/* scrub DRAM */
+	rc = gaudi2_scrub_device_dram(hdev, val);
+	if (rc) {
+		dev_err(hdev->dev, "scrubbing DRAM failed (%d)\n", rc);
+		return rc;
+	}
+	return 0;
+}
+
+static void gaudi2_restore_user_sm_registers(struct hl_device *hdev)
+{
+	u64 addr, mon_sts_addr, mon_cfg_addr, cq_lbw_l_addr, cq_lbw_h_addr,
+		cq_lbw_data_addr, cq_base_l_addr, cq_base_h_addr, cq_size_addr;
+	u32 val, size, offset;
+	int dcore_id;
+
+	offset = hdev->asic_prop.first_available_cq[0] * 4;
+	cq_lbw_l_addr = mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_0 + offset;
+	cq_lbw_h_addr = mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_0 + offset;
+	cq_lbw_data_addr = mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_0 + offset;
+	cq_base_l_addr = mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_0 + offset;
+	cq_base_h_addr = mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_0 + offset;
+	cq_size_addr = mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_0 + offset;
+	size = mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_0 -
+			(mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_0 + offset);
+
+	/* memset dcore0 CQ registers */
+	gaudi2_memset_device_lbw(hdev, cq_lbw_l_addr, size, 0);
+	gaudi2_memset_device_lbw(hdev, cq_lbw_h_addr, size, 0);
+	gaudi2_memset_device_lbw(hdev, cq_lbw_data_addr, size, 0);
+	gaudi2_memset_device_lbw(hdev, cq_base_l_addr, size, 0);
+	gaudi2_memset_device_lbw(hdev, cq_base_h_addr, size, 0);
+	gaudi2_memset_device_lbw(hdev, cq_size_addr, size, 0);
+
+	cq_lbw_l_addr = mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_0 + DCORE_OFFSET;
+	cq_lbw_h_addr = mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_0 + DCORE_OFFSET;
+	cq_lbw_data_addr = mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_0 + DCORE_OFFSET;
+	cq_base_l_addr = mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_0 + DCORE_OFFSET;
+	cq_base_h_addr = mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_0 + DCORE_OFFSET;
+	cq_size_addr = mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_0 + DCORE_OFFSET;
+	size = mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_0 - mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_0;
+
+	for (dcore_id = 1 ; dcore_id < NUM_OF_DCORES ; dcore_id++) {
+		gaudi2_memset_device_lbw(hdev, cq_lbw_l_addr, size, 0);
+		gaudi2_memset_device_lbw(hdev, cq_lbw_h_addr, size, 0);
+		gaudi2_memset_device_lbw(hdev, cq_lbw_data_addr, size, 0);
+		gaudi2_memset_device_lbw(hdev, cq_base_l_addr, size, 0);
+		gaudi2_memset_device_lbw(hdev, cq_base_h_addr, size, 0);
+		gaudi2_memset_device_lbw(hdev, cq_size_addr, size, 0);
+
+		cq_lbw_l_addr += DCORE_OFFSET;
+		cq_lbw_h_addr += DCORE_OFFSET;
+		cq_lbw_data_addr += DCORE_OFFSET;
+		cq_base_l_addr += DCORE_OFFSET;
+		cq_base_h_addr += DCORE_OFFSET;
+		cq_size_addr += DCORE_OFFSET;
+	}
+
+	offset = hdev->asic_prop.first_available_user_mon[0] * 4;
+	addr = mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_0 + offset;
+	val = 1 << DCORE0_SYNC_MNGR_OBJS_MON_STATUS_PROT_SHIFT;
+	size = mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_0 - (mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_0 + offset);
+
+	/* memset dcore0 monitors */
+	gaudi2_memset_device_lbw(hdev, addr, size, val);
+
+	addr = mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_0 + offset;
+	gaudi2_memset_device_lbw(hdev, addr, size, 0);
+
+	mon_sts_addr = mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_0 + DCORE_OFFSET;
+	mon_cfg_addr = mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_0 + DCORE_OFFSET;
+	size = mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_0 - mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_0;
+
+	for (dcore_id = 1 ; dcore_id < NUM_OF_DCORES ; dcore_id++) {
+		gaudi2_memset_device_lbw(hdev, mon_sts_addr, size, val);
+		gaudi2_memset_device_lbw(hdev, mon_cfg_addr, size, 0);
+		mon_sts_addr += DCORE_OFFSET;
+		mon_cfg_addr += DCORE_OFFSET;
+	}
+
+	offset = hdev->asic_prop.first_available_user_sob[0] * 4;
+	addr = mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 + offset;
+	val = 0;
+	size = mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 -
+			(mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 + offset);
+
+	/* memset dcore0 sobs */
+	gaudi2_memset_device_lbw(hdev, addr, size, val);
+
+	addr = mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 + DCORE_OFFSET;
+	size = mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 - mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0;
+
+	for (dcore_id = 1 ; dcore_id < NUM_OF_DCORES ; dcore_id++) {
+		gaudi2_memset_device_lbw(hdev, addr, size, val);
+		addr += DCORE_OFFSET;
+	}
+
+	/* Flush all WREG to prevent race */
+	val = RREG32(mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 + offset);
+}
+
+static void gaudi2_restore_user_qm_registers(struct hl_device *hdev)
+{
+	u32 reg_base, hw_queue_id;
+
+	for (hw_queue_id = GAUDI2_QUEUE_ID_PDMA_0_0 ; hw_queue_id <= GAUDI2_QUEUE_ID_ROT_1_0;
+							hw_queue_id += NUM_OF_PQ_PER_QMAN) {
+		if (!gaudi2_is_queue_enabled(hdev, hw_queue_id))
+			continue;
+
+		gaudi2_clear_qm_fence_counters_common(hdev, hw_queue_id, false);
+
+		reg_base = gaudi2_qm_blocks_bases[hw_queue_id];
+		WREG32(reg_base + QM_ARB_CFG_0_OFFSET, 0);
+	}
+
+	/* Flush all WREG to prevent race */
+	RREG32(mmPDMA0_QM_ARB_CFG_0);
+}
+
+static void gaudi2_restore_nic_qm_registers(struct hl_device *hdev)
+{
+	u32 reg_base, hw_queue_id;
+
+	for (hw_queue_id = GAUDI2_QUEUE_ID_NIC_0_0 ; hw_queue_id <= GAUDI2_QUEUE_ID_NIC_23_3;
+							hw_queue_id += NUM_OF_PQ_PER_QMAN) {
+		if (!gaudi2_is_queue_enabled(hdev, hw_queue_id))
+			continue;
+
+		gaudi2_clear_qm_fence_counters_common(hdev, hw_queue_id, false);
+
+		reg_base = gaudi2_qm_blocks_bases[hw_queue_id];
+		WREG32(reg_base + QM_ARB_CFG_0_OFFSET, 0);
+	}
+
+	/* Flush all WREG to prevent race */
+	RREG32(mmPDMA0_QM_ARB_CFG_0);
+}
+
+static int gaudi2_context_switch(struct hl_device *hdev, u32 asid)
+{
+	return 0;
+}
+
+static void gaudi2_restore_phase_topology(struct hl_device *hdev)
+{
+}
+
+static void gaudi2_init_block_instances(struct hl_device *hdev, u32 block_idx,
+						struct dup_block_ctx *cfg_ctx)
+{
+	u64 block_base = cfg_ctx->base + block_idx * cfg_ctx->block_off;
+	u8 seq;
+	int i;
+
+	for (i = 0 ; i < cfg_ctx->instances ; i++) {
+		seq = block_idx * cfg_ctx->instances + i;
+
+		/* skip disabled instance */
+		if (!(cfg_ctx->enabled_mask & BIT_ULL(seq)))
+			continue;
+
+		cfg_ctx->instance_cfg_fn(hdev, block_base + i * cfg_ctx->instance_off,
+					cfg_ctx->data);
+	}
+}
+
+static void gaudi2_init_blocks_with_mask(struct hl_device *hdev, struct dup_block_ctx *cfg_ctx,
+						u64 mask)
+{
+	int i;
+
+	cfg_ctx->enabled_mask = mask;
+
+	for (i = 0 ; i < cfg_ctx->blocks ; i++)
+		gaudi2_init_block_instances(hdev, i, cfg_ctx);
+}
+
+void gaudi2_init_blocks(struct hl_device *hdev, struct dup_block_ctx *cfg_ctx)
+{
+	gaudi2_init_blocks_with_mask(hdev, cfg_ctx, U64_MAX);
+}
+
+static int gaudi2_debugfs_read_dma(struct hl_device *hdev, u64 addr, u32 size, void *blob_addr)
+{
+	void *host_mem_virtual_addr;
+	dma_addr_t host_mem_dma_addr;
+	u64 reserved_va_base;
+	u32 pos, size_left, size_to_dma;
+	struct hl_ctx *ctx;
+	int rc = 0;
+
+	/* Fetch the ctx */
+	ctx = hl_get_compute_ctx(hdev);
+	if (!ctx) {
+		dev_err(hdev->dev, "No ctx available\n");
+		return -EINVAL;
+	}
+
+	/* Allocate buffers for read and for poll */
+	host_mem_virtual_addr = hl_asic_dma_alloc_coherent(hdev, SZ_2M, &host_mem_dma_addr,
+								GFP_KERNEL | __GFP_ZERO);
+	if (host_mem_virtual_addr == NULL) {
+		dev_err(hdev->dev, "Failed to allocate memory for KDMA read\n");
+		rc = -ENOMEM;
+		goto put_ctx;
+	}
+
+	/* Reserve VM region on asic side */
+	reserved_va_base = hl_reserve_va_block(hdev, ctx, HL_VA_RANGE_TYPE_HOST, SZ_2M,
+						HL_MMU_VA_ALIGNMENT_NOT_NEEDED);
+	if (!reserved_va_base) {
+		dev_err(hdev->dev, "Failed to reserve vmem on asic\n");
+		rc = -ENOMEM;
+		goto free_data_buffer;
+	}
+
+	/* Create mapping on asic side */
+	mutex_lock(&hdev->mmu_lock);
+
+	rc = hl_mmu_map_contiguous(ctx, reserved_va_base, host_mem_dma_addr, SZ_2M);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to create mapping on asic mmu\n");
+		goto unreserve_va;
+	}
+
+	rc = hl_mmu_invalidate_cache_range(hdev, false,
+				      MMU_OP_USERPTR | MMU_OP_SKIP_LOW_CACHE_INV,
+				      ctx->asid, reserved_va_base, SZ_2M);
+	if (rc) {
+		hl_mmu_unmap_contiguous(ctx, reserved_va_base, SZ_2M);
+		goto unreserve_va;
+	}
+
+	mutex_unlock(&hdev->mmu_lock);
+
+	/* Enable MMU on KDMA */
+	gaudi2_kdma_set_mmbp_asid(hdev, false, ctx->asid);
+
+	pos = 0;
+	size_left = size;
+	size_to_dma = SZ_2M;
+
+	while (size_left > 0) {
+		if (size_left < SZ_2M)
+			size_to_dma = size_left;
+
+		rc = gaudi2_send_job_to_kdma(hdev, addr, reserved_va_base, size_to_dma, false);
+		if (rc)
+			break;
+
+		memcpy(blob_addr + pos, host_mem_virtual_addr, size_to_dma);
+
+		if (size_left <= SZ_2M)
+			break;
+
+		pos += SZ_2M;
+		addr += SZ_2M;
+		size_left -= SZ_2M;
+	}
+
+	gaudi2_kdma_set_mmbp_asid(hdev, true, HL_KERNEL_ASID_ID);
+
+	mutex_lock(&hdev->mmu_lock);
+
+	rc = hl_mmu_unmap_contiguous(ctx, reserved_va_base, SZ_2M);
+	if (rc)
+		goto unreserve_va;
+
+	rc = hl_mmu_invalidate_cache_range(hdev, false, MMU_OP_USERPTR,
+				      ctx->asid, reserved_va_base, SZ_2M);
+
+unreserve_va:
+	mutex_unlock(&hdev->mmu_lock);
+	hl_unreserve_va_block(hdev, ctx, reserved_va_base, SZ_2M);
+free_data_buffer:
+	hl_asic_dma_free_coherent(hdev, SZ_2M, host_mem_virtual_addr, host_mem_dma_addr);
+put_ctx:
+	hl_ctx_put(ctx);
+
+	return rc;
+}
+
+static int gaudi2_internal_cb_pool_init(struct hl_device *hdev, struct hl_ctx *ctx)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	int min_alloc_order, rc;
+
+	if (!(gaudi2->hw_cap_initialized & HW_CAP_PMMU))
+		return 0;
+
+	hdev->internal_cb_pool_virt_addr = hl_asic_dma_alloc_coherent(hdev,
+								HOST_SPACE_INTERNAL_CB_SZ,
+								&hdev->internal_cb_pool_dma_addr,
+								GFP_KERNEL | __GFP_ZERO);
+
+	if (!hdev->internal_cb_pool_virt_addr)
+		return -ENOMEM;
+
+	min_alloc_order = ilog2(min(gaudi2_get_signal_cb_size(hdev),
+					gaudi2_get_wait_cb_size(hdev)));
+
+	hdev->internal_cb_pool = gen_pool_create(min_alloc_order, -1);
+	if (!hdev->internal_cb_pool) {
+		dev_err(hdev->dev, "Failed to create internal CB pool\n");
+		rc = -ENOMEM;
+		goto free_internal_cb_pool;
+	}
+
+	rc = gen_pool_add(hdev->internal_cb_pool, (uintptr_t) hdev->internal_cb_pool_virt_addr,
+				HOST_SPACE_INTERNAL_CB_SZ, -1);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to add memory to internal CB pool\n");
+		rc = -EFAULT;
+		goto destroy_internal_cb_pool;
+	}
+
+	hdev->internal_cb_va_base = hl_reserve_va_block(hdev, ctx, HL_VA_RANGE_TYPE_HOST,
+					HOST_SPACE_INTERNAL_CB_SZ, HL_MMU_VA_ALIGNMENT_NOT_NEEDED);
+
+	if (!hdev->internal_cb_va_base) {
+		rc = -ENOMEM;
+		goto destroy_internal_cb_pool;
+	}
+
+	mutex_lock(&hdev->mmu_lock);
+
+	rc = hl_mmu_map_contiguous(ctx, hdev->internal_cb_va_base, hdev->internal_cb_pool_dma_addr,
+					HOST_SPACE_INTERNAL_CB_SZ);
+	if (rc)
+		goto unreserve_internal_cb_pool;
+
+	rc = hl_mmu_invalidate_cache(hdev, false, MMU_OP_USERPTR);
+	if (rc)
+		goto unmap_internal_cb_pool;
+
+	mutex_unlock(&hdev->mmu_lock);
+
+	return 0;
+
+unmap_internal_cb_pool:
+	hl_mmu_unmap_contiguous(ctx, hdev->internal_cb_va_base, HOST_SPACE_INTERNAL_CB_SZ);
+unreserve_internal_cb_pool:
+	mutex_unlock(&hdev->mmu_lock);
+	hl_unreserve_va_block(hdev, ctx, hdev->internal_cb_va_base, HOST_SPACE_INTERNAL_CB_SZ);
+destroy_internal_cb_pool:
+	gen_pool_destroy(hdev->internal_cb_pool);
+free_internal_cb_pool:
+	hl_asic_dma_free_coherent(hdev, HOST_SPACE_INTERNAL_CB_SZ, hdev->internal_cb_pool_virt_addr,
+					hdev->internal_cb_pool_dma_addr);
+
+	return rc;
+}
+
+static void gaudi2_internal_cb_pool_fini(struct hl_device *hdev, struct hl_ctx *ctx)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+
+	if (!(gaudi2->hw_cap_initialized & HW_CAP_PMMU))
+		return;
+
+	mutex_lock(&hdev->mmu_lock);
+	hl_mmu_unmap_contiguous(ctx, hdev->internal_cb_va_base, HOST_SPACE_INTERNAL_CB_SZ);
+	hl_unreserve_va_block(hdev, ctx, hdev->internal_cb_va_base, HOST_SPACE_INTERNAL_CB_SZ);
+	hl_mmu_invalidate_cache(hdev, true, MMU_OP_USERPTR);
+	mutex_unlock(&hdev->mmu_lock);
+
+	gen_pool_destroy(hdev->internal_cb_pool);
+
+	hl_asic_dma_free_coherent(hdev, HOST_SPACE_INTERNAL_CB_SZ, hdev->internal_cb_pool_virt_addr,
+					hdev->internal_cb_pool_dma_addr);
+}
+
+static void gaudi2_restore_user_registers(struct hl_device *hdev)
+{
+	gaudi2_restore_user_sm_registers(hdev);
+	gaudi2_restore_user_qm_registers(hdev);
+}
+
+static int gaudi2_map_virtual_msix_doorbell_memory(struct hl_ctx *ctx)
+{
+	struct hl_device *hdev = ctx->hdev;
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	int rc;
+
+	rc = hl_mmu_map_page(ctx, RESERVED_VA_FOR_VIRTUAL_MSIX_DOORBELL_START,
+				gaudi2->virt_msix_db_dma_addr, prop->pmmu.page_size, true);
+	if (rc)
+		dev_err(hdev->dev, "Failed to map VA %#llx for virtual MSI-X doorbell memory\n",
+			RESERVED_VA_FOR_VIRTUAL_MSIX_DOORBELL_START);
+
+	return rc;
+}
+
+static void gaudi2_unmap_virtual_msix_doorbell_memory(struct hl_ctx *ctx)
+{
+	struct hl_device *hdev = ctx->hdev;
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	int rc;
+
+	rc = hl_mmu_unmap_page(ctx, RESERVED_VA_FOR_VIRTUAL_MSIX_DOORBELL_START,
+				prop->pmmu.page_size, true);
+	if (rc)
+		dev_err(hdev->dev, "Failed to unmap VA %#llx of virtual MSI-X doorbell memory\n",
+			RESERVED_VA_FOR_VIRTUAL_MSIX_DOORBELL_START);
+}
+
+static int gaudi2_ctx_init(struct hl_ctx *ctx)
+{
+	int rc;
+
+	if (ctx->asid == HL_KERNEL_ASID_ID)
+		return 0;
+
+	rc = gaudi2_mmu_prepare(ctx->hdev, ctx->asid);
+	if (rc)
+		return rc;
+
+	/* No need to clear user registers if the device has just
+	 * performed reset, we restore only nic qm registers
+	 */
+	if (ctx->hdev->reset_upon_device_release)
+		gaudi2_restore_nic_qm_registers(ctx->hdev);
+	else
+		gaudi2_restore_user_registers(ctx->hdev);
+
+	rc = gaudi2_internal_cb_pool_init(ctx->hdev, ctx);
+	if (rc)
+		return rc;
+
+	rc = gaudi2_map_virtual_msix_doorbell_memory(ctx);
+	if (rc)
+		gaudi2_internal_cb_pool_fini(ctx->hdev, ctx);
+
+	return rc;
+}
+
+static void gaudi2_ctx_fini(struct hl_ctx *ctx)
+{
+	if (ctx->asid == HL_KERNEL_ASID_ID)
+		return;
+
+	gaudi2_internal_cb_pool_fini(ctx->hdev, ctx);
+
+	gaudi2_unmap_virtual_msix_doorbell_memory(ctx);
+}
+
+static int gaudi2_pre_schedule_cs(struct hl_cs *cs)
+{
+	struct hl_device *hdev = cs->ctx->hdev;
+	int index = cs->sequence & (hdev->asic_prop.max_pending_cs - 1);
+	u32 mon_payload, sob_id, mon_id;
+
+	if (!cs_needs_completion(cs))
+		return 0;
+
+	/*
+	 * First 64 SOB/MON are reserved for driver for QMAN auto completion
+	 * mechanism. Each SOB/MON pair are used for a pending CS with the same
+	 * cyclic index. The SOB value is increased when each of the CS jobs is
+	 * completed. When the SOB reaches the number of CS jobs, the monitor
+	 * generates MSI-X interrupt.
+	 */
+
+	sob_id = mon_id = index;
+	mon_payload = (1 << CQ_ENTRY_SHADOW_INDEX_VALID_SHIFT) |
+				(1 << CQ_ENTRY_READY_SHIFT) | index;
+
+	gaudi2_arm_cq_monitor(hdev, sob_id, mon_id, GAUDI2_RESERVED_CQ_CS_COMPLETION, mon_payload,
+				cs->jobs_cnt);
+
+	return 0;
+}
+
+static u32 gaudi2_get_queue_id_for_cq(struct hl_device *hdev, u32 cq_idx)
+{
+	return HL_INVALID_QUEUE;
+}
+
+static u32 gaudi2_gen_signal_cb(struct hl_device *hdev, void *data, u16 sob_id, u32 size, bool eb)
+{
+	struct hl_cb *cb = data;
+	struct packet_msg_short *pkt;
+	u32 value, ctl, pkt_size = sizeof(*pkt);
+
+	pkt = (struct packet_msg_short *) (uintptr_t) (cb->kernel_address + size);
+	memset(pkt, 0, pkt_size);
+
+	/* Inc by 1, Mode ADD */
+	value = FIELD_PREP(GAUDI2_PKT_SHORT_VAL_SOB_SYNC_VAL_MASK, 1);
+	value |= FIELD_PREP(GAUDI2_PKT_SHORT_VAL_SOB_MOD_MASK, 1);
+
+	ctl = FIELD_PREP(GAUDI2_PKT_SHORT_CTL_ADDR_MASK, sob_id * 4);
+	ctl |= FIELD_PREP(GAUDI2_PKT_SHORT_CTL_BASE_MASK, 1); /* SOB base */
+	ctl |= FIELD_PREP(GAUDI2_PKT_CTL_OPCODE_MASK, PACKET_MSG_SHORT);
+	ctl |= FIELD_PREP(GAUDI2_PKT_CTL_EB_MASK, eb);
+	ctl |= FIELD_PREP(GAUDI2_PKT_CTL_MB_MASK, 1);
+
+	pkt->value = cpu_to_le32(value);
+	pkt->ctl = cpu_to_le32(ctl);
+
+	return size + pkt_size;
+}
+
+static u32 gaudi2_add_mon_msg_short(struct packet_msg_short *pkt, u32 value, u16 addr)
+{
+	u32 ctl, pkt_size = sizeof(*pkt);
+
+	memset(pkt, 0, pkt_size);
+
+	ctl = FIELD_PREP(GAUDI2_PKT_SHORT_CTL_ADDR_MASK, addr);
+	ctl |= FIELD_PREP(GAUDI2_PKT_SHORT_CTL_BASE_MASK, 0);  /* MON base */
+	ctl |= FIELD_PREP(GAUDI2_PKT_CTL_OPCODE_MASK, PACKET_MSG_SHORT);
+	ctl |= FIELD_PREP(GAUDI2_PKT_CTL_EB_MASK, 0);
+	ctl |= FIELD_PREP(GAUDI2_PKT_CTL_MB_MASK, 0);
+
+	pkt->value = cpu_to_le32(value);
+	pkt->ctl = cpu_to_le32(ctl);
+
+	return pkt_size;
+}
+
+static u32 gaudi2_add_arm_monitor_pkt(struct hl_device *hdev, struct packet_msg_short *pkt,
+					u16 sob_base, u8 sob_mask, u16 sob_val, u16 addr)
+{
+	u32 ctl, value, pkt_size = sizeof(*pkt);
+	u8 mask;
+
+	if (hl_gen_sob_mask(sob_base, sob_mask, &mask)) {
+		dev_err(hdev->dev, "sob_base %u (mask %#x) is not valid\n", sob_base, sob_mask);
+		return 0;
+	}
+
+	memset(pkt, 0, pkt_size);
+
+	value = FIELD_PREP(GAUDI2_PKT_SHORT_VAL_MON_SYNC_GID_MASK, sob_base / 8);
+	value |= FIELD_PREP(GAUDI2_PKT_SHORT_VAL_MON_SYNC_VAL_MASK, sob_val);
+	value |= FIELD_PREP(GAUDI2_PKT_SHORT_VAL_MON_MODE_MASK, 0); /* GREATER OR EQUAL*/
+	value |= FIELD_PREP(GAUDI2_PKT_SHORT_VAL_MON_MASK_MASK, mask);
+
+	ctl = FIELD_PREP(GAUDI2_PKT_SHORT_CTL_ADDR_MASK, addr);
+	ctl |= FIELD_PREP(GAUDI2_PKT_SHORT_CTL_BASE_MASK, 0); /* MON base */
+	ctl |= FIELD_PREP(GAUDI2_PKT_CTL_OPCODE_MASK, PACKET_MSG_SHORT);
+	ctl |= FIELD_PREP(GAUDI2_PKT_CTL_EB_MASK, 0);
+	ctl |= FIELD_PREP(GAUDI2_PKT_CTL_MB_MASK, 1);
+
+	pkt->value = cpu_to_le32(value);
+	pkt->ctl = cpu_to_le32(ctl);
+
+	return pkt_size;
+}
+
+static u32 gaudi2_add_fence_pkt(struct packet_fence *pkt)
+{
+	u32 ctl, cfg, pkt_size = sizeof(*pkt);
+
+	memset(pkt, 0, pkt_size);
+
+	cfg = FIELD_PREP(GAUDI2_PKT_FENCE_CFG_DEC_VAL_MASK, 1);
+	cfg |= FIELD_PREP(GAUDI2_PKT_FENCE_CFG_TARGET_VAL_MASK, 1);
+	cfg |= FIELD_PREP(GAUDI2_PKT_FENCE_CFG_ID_MASK, 2);
+
+	ctl = FIELD_PREP(GAUDI2_PKT_CTL_OPCODE_MASK, PACKET_FENCE);
+	ctl |= FIELD_PREP(GAUDI2_PKT_CTL_EB_MASK, 0);
+	ctl |= FIELD_PREP(GAUDI2_PKT_CTL_MB_MASK, 1);
+
+	pkt->cfg = cpu_to_le32(cfg);
+	pkt->ctl = cpu_to_le32(ctl);
+
+	return pkt_size;
+}
+
+static u32 gaudi2_gen_wait_cb(struct hl_device *hdev, struct hl_gen_wait_properties *prop)
+{
+	struct hl_cb *cb = prop->data;
+	void *buf = (void *) (uintptr_t) (cb->kernel_address);
+
+	u64 monitor_base, fence_addr = 0;
+	u32 stream_index, size = prop->size;
+	u16 msg_addr_offset;
+
+	stream_index = prop->q_idx % 4;
+	fence_addr = CFG_BASE + gaudi2_qm_blocks_bases[prop->q_idx] +
+			QM_FENCE2_OFFSET + stream_index * 4;
+
+	/*
+	 * monitor_base should be the content of the base0 address registers,
+	 * so it will be added to the msg short offsets
+	 */
+	monitor_base = mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0;
+
+	/* First monitor config packet: low address of the sync */
+	msg_addr_offset = (mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 + prop->mon_id * 4) -
+				monitor_base;
+
+	size += gaudi2_add_mon_msg_short(buf + size, (u32) fence_addr, msg_addr_offset);
+
+	/* Second monitor config packet: high address of the sync */
+	msg_addr_offset = (mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_0 + prop->mon_id * 4) -
+				monitor_base;
+
+	size += gaudi2_add_mon_msg_short(buf + size, (u32) (fence_addr >> 32), msg_addr_offset);
+
+	/*
+	 * Third monitor config packet: the payload, i.e. what to write when the
+	 * sync triggers
+	 */
+	msg_addr_offset = (mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_0 + prop->mon_id * 4) -
+				monitor_base;
+
+	size += gaudi2_add_mon_msg_short(buf + size, 1, msg_addr_offset);
+
+	/* Fourth monitor config packet: bind the monitor to a sync object */
+	msg_addr_offset = (mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_0 + prop->mon_id * 4) - monitor_base;
+
+	size += gaudi2_add_arm_monitor_pkt(hdev, buf + size, prop->sob_base, prop->sob_mask,
+						prop->sob_val, msg_addr_offset);
+
+	/* Fence packet */
+	size += gaudi2_add_fence_pkt(buf + size);
+
+	return size;
+}
+
+static void gaudi2_reset_sob(struct hl_device *hdev, void *data)
+{
+	struct hl_hw_sob *hw_sob = data;
+
+	dev_dbg(hdev->dev, "reset SOB, q_idx: %d, sob_id: %d\n", hw_sob->q_idx, hw_sob->sob_id);
+
+	WREG32(mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 + hw_sob->sob_id * 4, 0);
+
+	kref_init(&hw_sob->kref);
+}
+
+static void gaudi2_reset_sob_group(struct hl_device *hdev, u16 sob_group)
+{
+}
+
+static u64 gaudi2_get_device_time(struct hl_device *hdev)
+{
+	u64 device_time = ((u64) RREG32(mmPSOC_TIMESTAMP_CNTCVU)) << 32;
+
+	return device_time | RREG32(mmPSOC_TIMESTAMP_CNTCVL);
+}
+
+static int gaudi2_collective_wait_init_cs(struct hl_cs *cs)
+{
+	return 0;
+}
+
+static int gaudi2_collective_wait_create_jobs(struct hl_device *hdev, struct hl_ctx *ctx,
+					struct hl_cs *cs, u32 wait_queue_id,
+					u32 collective_engine_id, u32 encaps_signal_offset)
+{
+	return -EINVAL;
+}
+
+/*
+ * hl_mmu_scramble - converts a dram (non power of 2) page-size aligned address
+ *                   to DMMU page-size address (64MB) before mapping it in
+ *                   the MMU.
+ * The operation is performed on both the virtual and physical addresses.
+ * for device with 6 HBMs the scramble is:
+ * (addr[47:0] / 48M) * 64M + addr % 48M + addr[63:48]
+ *
+ * Example:
+ * =============================================================================
+ * Allocated DRAM  Reserved VA      scrambled VA for MMU mapping    Scrambled PA
+ * Phys address                                                     in MMU last
+ *                                                                    HOP
+ * =============================================================================
+ * PA1 0x3000000  VA1 0x9C000000  SVA1= (VA1/48M)*64M 0xD0000000  <- PA1/48M 0x1
+ * PA2 0x9000000  VA2 0x9F000000  SVA2= (VA2/48M)*64M 0xD4000000  <- PA2/48M 0x3
+ * =============================================================================
+ */
+static u64 gaudi2_mmu_scramble_addr(struct hl_device *hdev, u64 raw_addr)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	u32 divisor, mod_va;
+	u64 div_va;
+
+	/* accept any address in the DRAM address space */
+	if (hl_mem_area_inside_range(raw_addr, sizeof(raw_addr), DRAM_PHYS_BASE,
+									VA_HBM_SPACE_END)) {
+
+		divisor = prop->num_functional_hbms * GAUDI2_HBM_MMU_SCRM_MEM_SIZE;
+		div_va = div_u64_rem(raw_addr & GAUDI2_HBM_MMU_SCRM_ADDRESS_MASK, divisor, &mod_va);
+		return (raw_addr & ~GAUDI2_HBM_MMU_SCRM_ADDRESS_MASK) |
+			(div_va << GAUDI2_HBM_MMU_SCRM_DIV_SHIFT) |
+			(mod_va << GAUDI2_HBM_MMU_SCRM_MOD_SHIFT);
+	}
+
+	return raw_addr;
+}
+
+static u64 gaudi2_mmu_descramble_addr(struct hl_device *hdev, u64 scrambled_addr)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	u32 divisor, mod_va;
+	u64 div_va;
+
+	/* accept any address in the DRAM address space */
+	if (hl_mem_area_inside_range(scrambled_addr, sizeof(scrambled_addr), DRAM_PHYS_BASE,
+									VA_HBM_SPACE_END)) {
+
+		divisor = prop->num_functional_hbms * GAUDI2_HBM_MMU_SCRM_MEM_SIZE;
+		div_va = div_u64_rem(scrambled_addr & GAUDI2_HBM_MMU_SCRM_ADDRESS_MASK,
+					PAGE_SIZE_64MB, &mod_va);
+
+		return ((scrambled_addr & ~GAUDI2_HBM_MMU_SCRM_ADDRESS_MASK) +
+					(div_va * divisor + mod_va));
+	}
+
+	return scrambled_addr;
+}
+
+static u32 gaudi2_get_dec_base_addr(struct hl_device *hdev, u32 core_id)
+{
+	u32 base = 0, dcore_id, dec_id;
+
+	if (core_id >= NUMBER_OF_DEC) {
+		dev_err(hdev->dev, "Unexpected core number %d for DEC\n", core_id);
+		goto out;
+	}
+
+	if (core_id < 8) {
+		dcore_id = core_id / NUM_OF_DEC_PER_DCORE;
+		dec_id = core_id % NUM_OF_DEC_PER_DCORE;
+
+		base = mmDCORE0_DEC0_CMD_BASE + dcore_id * DCORE_OFFSET +
+				dec_id * DCORE_VDEC_OFFSET;
+	} else {
+		/* PCIe Shared Decoder */
+		base = mmPCIE_DEC0_CMD_BASE + ((core_id % 8) * PCIE_VDEC_OFFSET);
+	}
+out:
+	return base;
+}
+
+static int gaudi2_get_hw_block_id(struct hl_device *hdev, u64 block_addr,
+				u32 *block_size, u32 *block_id)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	int i;
+
+	for (i = 0 ; i < NUM_USER_MAPPED_BLOCKS ; i++) {
+		if (block_addr == CFG_BASE + gaudi2->mapped_blocks[i].address) {
+			*block_id = i;
+			if (block_size)
+				*block_size = gaudi2->mapped_blocks[i].size;
+			return 0;
+		}
+	}
+
+	dev_err(hdev->dev, "Invalid block address %#llx", block_addr);
+
+	return -EINVAL;
+}
+
+static int gaudi2_block_mmap(struct hl_device *hdev, struct vm_area_struct *vma,
+			u32 block_id, u32 block_size)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	u64 offset_in_bar;
+	u64 address;
+	int rc;
+
+	if (block_id >= NUM_USER_MAPPED_BLOCKS) {
+		dev_err(hdev->dev, "Invalid block id %u", block_id);
+		return -EINVAL;
+	}
+
+	/* we allow mapping only an entire block */
+	if (block_size != gaudi2->mapped_blocks[block_id].size) {
+		dev_err(hdev->dev, "Invalid block size %u", block_size);
+		return -EINVAL;
+	}
+
+	offset_in_bar = CFG_BASE + gaudi2->mapped_blocks[block_id].address - STM_FLASH_BASE_ADDR;
+
+	address = pci_resource_start(hdev->pdev, SRAM_CFG_BAR_ID) + offset_in_bar;
+
+	vm_flags_set(vma, VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP |
+			VM_DONTCOPY | VM_NORESERVE);
+
+	rc = remap_pfn_range(vma, vma->vm_start, address >> PAGE_SHIFT,
+			block_size, vma->vm_page_prot);
+	if (rc)
+		dev_err(hdev->dev, "remap_pfn_range error %d", rc);
+
+	return rc;
+}
+
+static void gaudi2_enable_events_from_fw(struct hl_device *hdev)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+
+	struct cpu_dyn_regs *dyn_regs = &hdev->fw_loader.dynamic_loader.comm_desc.cpu_dyn_regs;
+	u32 irq_handler_offset = le32_to_cpu(dyn_regs->gic_host_ints_irq);
+
+	if (gaudi2->hw_cap_initialized & HW_CAP_CPU_Q)
+		WREG32(irq_handler_offset,
+			gaudi2_irq_map_table[GAUDI2_EVENT_CPU_INTS_REGISTER].cpu_id);
+}
+
+static int gaudi2_get_mmu_base(struct hl_device *hdev, u64 mmu_id, u32 *mmu_base)
+{
+	switch (mmu_id) {
+	case HW_CAP_DCORE0_DMMU0:
+		*mmu_base = mmDCORE0_HMMU0_MMU_BASE;
+		break;
+	case HW_CAP_DCORE0_DMMU1:
+		*mmu_base = mmDCORE0_HMMU1_MMU_BASE;
+		break;
+	case HW_CAP_DCORE0_DMMU2:
+		*mmu_base = mmDCORE0_HMMU2_MMU_BASE;
+		break;
+	case HW_CAP_DCORE0_DMMU3:
+		*mmu_base = mmDCORE0_HMMU3_MMU_BASE;
+		break;
+	case HW_CAP_DCORE1_DMMU0:
+		*mmu_base = mmDCORE1_HMMU0_MMU_BASE;
+		break;
+	case HW_CAP_DCORE1_DMMU1:
+		*mmu_base = mmDCORE1_HMMU1_MMU_BASE;
+		break;
+	case HW_CAP_DCORE1_DMMU2:
+		*mmu_base = mmDCORE1_HMMU2_MMU_BASE;
+		break;
+	case HW_CAP_DCORE1_DMMU3:
+		*mmu_base = mmDCORE1_HMMU3_MMU_BASE;
+		break;
+	case HW_CAP_DCORE2_DMMU0:
+		*mmu_base = mmDCORE2_HMMU0_MMU_BASE;
+		break;
+	case HW_CAP_DCORE2_DMMU1:
+		*mmu_base = mmDCORE2_HMMU1_MMU_BASE;
+		break;
+	case HW_CAP_DCORE2_DMMU2:
+		*mmu_base = mmDCORE2_HMMU2_MMU_BASE;
+		break;
+	case HW_CAP_DCORE2_DMMU3:
+		*mmu_base = mmDCORE2_HMMU3_MMU_BASE;
+		break;
+	case HW_CAP_DCORE3_DMMU0:
+		*mmu_base = mmDCORE3_HMMU0_MMU_BASE;
+		break;
+	case HW_CAP_DCORE3_DMMU1:
+		*mmu_base = mmDCORE3_HMMU1_MMU_BASE;
+		break;
+	case HW_CAP_DCORE3_DMMU2:
+		*mmu_base = mmDCORE3_HMMU2_MMU_BASE;
+		break;
+	case HW_CAP_DCORE3_DMMU3:
+		*mmu_base = mmDCORE3_HMMU3_MMU_BASE;
+		break;
+	case HW_CAP_PMMU:
+		*mmu_base = mmPMMU_HBW_MMU_BASE;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static void gaudi2_ack_mmu_error(struct hl_device *hdev, u64 mmu_id)
+{
+	bool is_pmmu = (mmu_id == HW_CAP_PMMU);
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	u32 mmu_base;
+
+	if (!(gaudi2->hw_cap_initialized & mmu_id))
+		return;
+
+	if (gaudi2_get_mmu_base(hdev, mmu_id, &mmu_base))
+		return;
+
+	gaudi2_handle_page_error(hdev, mmu_base, is_pmmu, NULL);
+	gaudi2_handle_access_error(hdev, mmu_base, is_pmmu);
+}
+
+static int gaudi2_ack_mmu_page_fault_or_access_error(struct hl_device *hdev, u64 mmu_cap_mask)
+{
+	u32 i, mmu_id, num_of_hmmus = NUM_OF_HMMU_PER_DCORE * NUM_OF_DCORES;
+
+	/* check all HMMUs */
+	for (i = 0 ; i < num_of_hmmus ; i++) {
+		mmu_id = HW_CAP_DCORE0_DMMU0 << i;
+
+		if (mmu_cap_mask & mmu_id)
+			gaudi2_ack_mmu_error(hdev, mmu_id);
+	}
+
+	/* check PMMU */
+	if (mmu_cap_mask & HW_CAP_PMMU)
+		gaudi2_ack_mmu_error(hdev, HW_CAP_PMMU);
+
+	return 0;
+}
+
+static void gaudi2_get_msi_info(__le32 *table)
+{
+	table[CPUCP_EVENT_QUEUE_MSI_TYPE] = cpu_to_le32(GAUDI2_EVENT_QUEUE_MSIX_IDX);
+	table[CPUCP_EVENT_QUEUE_ERR_MSI_TYPE] = cpu_to_le32(GAUDI2_IRQ_NUM_EQ_ERROR);
+}
+
+static int gaudi2_map_pll_idx_to_fw_idx(u32 pll_idx)
+{
+	switch (pll_idx) {
+	case HL_GAUDI2_CPU_PLL: return CPU_PLL;
+	case HL_GAUDI2_PCI_PLL: return PCI_PLL;
+	case HL_GAUDI2_NIC_PLL: return NIC_PLL;
+	case HL_GAUDI2_DMA_PLL: return DMA_PLL;
+	case HL_GAUDI2_MESH_PLL: return MESH_PLL;
+	case HL_GAUDI2_MME_PLL: return MME_PLL;
+	case HL_GAUDI2_TPC_PLL: return TPC_PLL;
+	case HL_GAUDI2_IF_PLL: return IF_PLL;
+	case HL_GAUDI2_SRAM_PLL: return SRAM_PLL;
+	case HL_GAUDI2_HBM_PLL: return HBM_PLL;
+	case HL_GAUDI2_VID_PLL: return VID_PLL;
+	case HL_GAUDI2_MSS_PLL: return MSS_PLL;
+	default: return -EINVAL;
+	}
+}
+
+static int gaudi2_gen_sync_to_engine_map(struct hl_device *hdev, struct hl_sync_to_engine_map *map)
+{
+	/* Not implemented */
+	return 0;
+}
+
+static int gaudi2_monitor_valid(struct hl_mon_state_dump *mon)
+{
+	/* Not implemented */
+	return 0;
+}
+
+static int gaudi2_print_single_monitor(char **buf, size_t *size, size_t *offset,
+				struct hl_device *hdev, struct hl_mon_state_dump *mon)
+{
+	/* Not implemented */
+	return 0;
+}
+
+
+static int gaudi2_print_fences_single_engine(struct hl_device *hdev, u64 base_offset,
+				u64 status_base_offset, enum hl_sync_engine_type engine_type,
+				u32 engine_id, char **buf, size_t *size, size_t *offset)
+{
+	/* Not implemented */
+	return 0;
+}
+
+
+static struct hl_state_dump_specs_funcs gaudi2_state_dump_funcs = {
+	.monitor_valid = gaudi2_monitor_valid,
+	.print_single_monitor = gaudi2_print_single_monitor,
+	.gen_sync_to_engine_map = gaudi2_gen_sync_to_engine_map,
+	.print_fences_single_engine = gaudi2_print_fences_single_engine,
+};
+
+static void gaudi2_state_dump_init(struct hl_device *hdev)
+{
+	/* Not implemented */
+	hdev->state_dump_specs.props = gaudi2_state_dump_specs_props;
+	hdev->state_dump_specs.funcs = gaudi2_state_dump_funcs;
+}
+
+static u32 gaudi2_get_sob_addr(struct hl_device *hdev, u32 sob_id)
+{
+	return 0;
+}
+
+static u32 *gaudi2_get_stream_master_qid_arr(void)
+{
+	return NULL;
+}
+
+static void gaudi2_add_device_attr(struct hl_device *hdev, struct attribute_group *dev_clk_attr_grp,
+				struct attribute_group *dev_vrm_attr_grp)
+{
+	hl_sysfs_add_dev_clk_attr(hdev, dev_clk_attr_grp);
+	hl_sysfs_add_dev_vrm_attr(hdev, dev_vrm_attr_grp);
+}
+
+static int gaudi2_mmu_get_real_page_size(struct hl_device *hdev, struct hl_mmu_properties *mmu_prop,
+					u32 page_size, u32 *real_page_size, bool is_dram_addr)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+
+	/* for host pages the page size must be  */
+	if (!is_dram_addr) {
+		if (page_size % mmu_prop->page_size)
+			goto page_size_err;
+
+		*real_page_size = mmu_prop->page_size;
+		return 0;
+	}
+
+	if ((page_size % prop->dram_page_size) || (prop->dram_page_size > mmu_prop->page_size))
+		goto page_size_err;
+
+	/*
+	 * MMU page size is different from DRAM page size (more precisely, DMMU page is greater
+	 * than DRAM page size).
+	 * for this reason work with the DRAM page size and let the MMU scrambling routine handle
+	 * this mismatch when calculating the address to place in the MMU page table.
+	 * (in that case also make sure that the dram_page_size is not greater than the
+	 * mmu page size)
+	 */
+	*real_page_size = prop->dram_page_size;
+
+	return 0;
+
+page_size_err:
+	dev_err(hdev->dev, "page size of 0x%X is not 0x%X aligned, can't map\n",
+							page_size, mmu_prop->page_size >> 10);
+	return -EFAULT;
+}
+
+static int gaudi2_get_monitor_dump(struct hl_device *hdev, void *data)
+{
+	return -EOPNOTSUPP;
+}
+
+int gaudi2_send_device_activity(struct hl_device *hdev, bool open)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+
+	if (!(gaudi2->hw_cap_initialized & HW_CAP_CPU_Q))
+		return 0;
+
+	return hl_fw_send_device_activity(hdev, open);
+}
+
+static u64 gaudi2_read_pte(struct hl_device *hdev, u64 addr)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+	u64 val;
+
+	if (hdev->reset_info.hard_reset_pending)
+		return U64_MAX;
+
+	val = readq(hdev->pcie_bar[DRAM_BAR_ID] + (addr - gaudi2->dram_bar_cur_addr));
+
+	return val;
+}
+
+static void gaudi2_write_pte(struct hl_device *hdev, u64 addr, u64 val)
+{
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+
+	if (hdev->reset_info.hard_reset_pending)
+		return;
+
+	writeq(val, hdev->pcie_bar[DRAM_BAR_ID] + (addr - gaudi2->dram_bar_cur_addr));
+}
+
+static const struct hl_asic_funcs gaudi2_funcs = {
+	.early_init = gaudi2_early_init,
+	.early_fini = gaudi2_early_fini,
+	.late_init = gaudi2_late_init,
+	.late_fini = gaudi2_late_fini,
+	.sw_init = gaudi2_sw_init,
+	.sw_fini = gaudi2_sw_fini,
+	.hw_init = gaudi2_hw_init,
+	.hw_fini = gaudi2_hw_fini,
+	.halt_engines = gaudi2_halt_engines,
+	.suspend = gaudi2_suspend,
+	.resume = gaudi2_resume,
+	.mmap = gaudi2_mmap,
+	.ring_doorbell = gaudi2_ring_doorbell,
+	.pqe_write = gaudi2_pqe_write,
+	.asic_dma_alloc_coherent = gaudi2_dma_alloc_coherent,
+	.asic_dma_free_coherent = gaudi2_dma_free_coherent,
+	.scrub_device_mem = gaudi2_scrub_device_mem,
+	.scrub_device_dram = gaudi2_scrub_device_dram,
+	.get_int_queue_base = NULL,
+	.test_queues = gaudi2_test_queues,
+	.asic_dma_pool_zalloc = gaudi2_dma_pool_zalloc,
+	.asic_dma_pool_free = gaudi2_dma_pool_free,
+	.cpu_accessible_dma_pool_alloc = gaudi2_cpu_accessible_dma_pool_alloc,
+	.cpu_accessible_dma_pool_free = gaudi2_cpu_accessible_dma_pool_free,
+	.dma_unmap_sgtable = hl_asic_dma_unmap_sgtable,
+	.cs_parser = gaudi2_cs_parser,
+	.dma_map_sgtable = hl_asic_dma_map_sgtable,
+	.add_end_of_cb_packets = NULL,
+	.update_eq_ci = gaudi2_update_eq_ci,
+	.context_switch = gaudi2_context_switch,
+	.restore_phase_topology = gaudi2_restore_phase_topology,
+	.debugfs_read_dma = gaudi2_debugfs_read_dma,
+	.add_device_attr = gaudi2_add_device_attr,
+	.handle_eqe = gaudi2_handle_eqe,
+	.get_events_stat = gaudi2_get_events_stat,
+	.read_pte = gaudi2_read_pte,
+	.write_pte = gaudi2_write_pte,
+	.mmu_invalidate_cache = gaudi2_mmu_invalidate_cache,
+	.mmu_invalidate_cache_range = gaudi2_mmu_invalidate_cache_range,
+	.mmu_prefetch_cache_range = NULL,
+	.send_heartbeat = gaudi2_send_heartbeat,
+	.debug_coresight = gaudi2_debug_coresight,
+	.is_device_idle = gaudi2_is_device_idle,
+	.compute_reset_late_init = gaudi2_compute_reset_late_init,
+	.hw_queues_lock = gaudi2_hw_queues_lock,
+	.hw_queues_unlock = gaudi2_hw_queues_unlock,
+	.get_pci_id = gaudi2_get_pci_id,
+	.get_eeprom_data = gaudi2_get_eeprom_data,
+	.get_monitor_dump = gaudi2_get_monitor_dump,
+	.send_cpu_message = gaudi2_send_cpu_message,
+	.pci_bars_map = gaudi2_pci_bars_map,
+	.init_iatu = gaudi2_init_iatu,
+	.rreg = hl_rreg,
+	.wreg = hl_wreg,
+	.halt_coresight = gaudi2_halt_coresight,
+	.ctx_init = gaudi2_ctx_init,
+	.ctx_fini = gaudi2_ctx_fini,
+	.pre_schedule_cs = gaudi2_pre_schedule_cs,
+	.get_queue_id_for_cq = gaudi2_get_queue_id_for_cq,
+	.load_firmware_to_device = NULL,
+	.load_boot_fit_to_device = NULL,
+	.get_signal_cb_size = gaudi2_get_signal_cb_size,
+	.get_wait_cb_size = gaudi2_get_wait_cb_size,
+	.gen_signal_cb = gaudi2_gen_signal_cb,
+	.gen_wait_cb = gaudi2_gen_wait_cb,
+	.reset_sob = gaudi2_reset_sob,
+	.reset_sob_group = gaudi2_reset_sob_group,
+	.get_device_time = gaudi2_get_device_time,
+	.pb_print_security_errors = gaudi2_pb_print_security_errors,
+	.collective_wait_init_cs = gaudi2_collective_wait_init_cs,
+	.collective_wait_create_jobs = gaudi2_collective_wait_create_jobs,
+	.get_dec_base_addr = gaudi2_get_dec_base_addr,
+	.scramble_addr = gaudi2_mmu_scramble_addr,
+	.descramble_addr = gaudi2_mmu_descramble_addr,
+	.ack_protection_bits_errors = gaudi2_ack_protection_bits_errors,
+	.get_hw_block_id = gaudi2_get_hw_block_id,
+	.hw_block_mmap = gaudi2_block_mmap,
+	.enable_events_from_fw = gaudi2_enable_events_from_fw,
+	.ack_mmu_errors = gaudi2_ack_mmu_page_fault_or_access_error,
+	.get_msi_info = gaudi2_get_msi_info,
+	.map_pll_idx_to_fw_idx = gaudi2_map_pll_idx_to_fw_idx,
+	.init_firmware_preload_params = gaudi2_init_firmware_preload_params,
+	.init_firmware_loader = gaudi2_init_firmware_loader,
+	.init_cpu_scrambler_dram = gaudi2_init_scrambler_hbm,
+	.state_dump_init = gaudi2_state_dump_init,
+	.get_sob_addr = &gaudi2_get_sob_addr,
+	.set_pci_memory_regions = gaudi2_set_pci_memory_regions,
+	.get_stream_master_qid_arr = gaudi2_get_stream_master_qid_arr,
+	.check_if_razwi_happened = gaudi2_check_if_razwi_happened,
+	.mmu_get_real_page_size = gaudi2_mmu_get_real_page_size,
+	.access_dev_mem = hl_access_dev_mem,
+	.set_dram_bar_base = gaudi2_set_hbm_bar_base,
+	.set_engine_cores = gaudi2_set_engine_cores,
+	.set_engines = gaudi2_set_engines,
+	.send_device_activity = gaudi2_send_device_activity,
+	.set_dram_properties = gaudi2_set_dram_properties,
+	.set_binning_masks = gaudi2_set_binning_masks,
+};
+
+void gaudi2_set_asic_funcs(struct hl_device *hdev)
+{
+	hdev->asic_funcs = &gaudi2_funcs;
+}
diff --git a/drivers/accel/habanalabs/gaudi2/gaudi2P.h b/drivers/accel/habanalabs/gaudi2/gaudi2P.h
new file mode 100644
index 000000000000..bdf5c1bd2d63
--- /dev/null
+++ b/drivers/accel/habanalabs/gaudi2/gaudi2P.h
@@ -0,0 +1,621 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2022 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+#ifndef GAUDI2P_H_
+#define GAUDI2P_H_
+
+#include <uapi/drm/habanalabs_accel.h>
+#include "../common/habanalabs.h"
+#include <linux/habanalabs/hl_boot_if.h>
+#include "../include/gaudi2/gaudi2.h"
+#include "../include/gaudi2/gaudi2_packets.h"
+#include "../include/gaudi2/gaudi2_fw_if.h"
+#include "../include/gaudi2/gaudi2_async_events.h"
+
+#define GAUDI2_LINUX_FW_FILE	"habanalabs/gaudi2/gaudi2-fit.itb"
+#define GAUDI2_BOOT_FIT_FILE	"habanalabs/gaudi2/gaudi2-boot-fit.itb"
+
+#define GAUDI2_CPU_TIMEOUT_USEC		30000000	/* 30s */
+
+#define NUMBER_OF_PDMA_QUEUES		2
+#define NUMBER_OF_EDMA_QUEUES		8
+#define NUMBER_OF_MME_QUEUES		4
+#define NUMBER_OF_TPC_QUEUES		25
+#define NUMBER_OF_NIC_QUEUES		24
+#define NUMBER_OF_ROT_QUEUES		2
+#define NUMBER_OF_CPU_QUEUES		1
+
+#define NUMBER_OF_HW_QUEUES		((NUMBER_OF_PDMA_QUEUES + \
+					NUMBER_OF_EDMA_QUEUES + \
+					NUMBER_OF_MME_QUEUES + \
+					NUMBER_OF_TPC_QUEUES + \
+					NUMBER_OF_NIC_QUEUES + \
+					NUMBER_OF_ROT_QUEUES + \
+					NUMBER_OF_CPU_QUEUES) * \
+					NUM_OF_PQ_PER_QMAN)
+
+#define NUMBER_OF_QUEUES		(NUMBER_OF_CPU_QUEUES + NUMBER_OF_HW_QUEUES)
+
+#define DCORE_NUM_OF_SOB		\
+	(((mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8191 - \
+	mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0) + 4) >> 2)
+
+#define DCORE_NUM_OF_MONITORS		\
+	(((mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2047 - \
+	mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_0) + 4) >> 2)
+
+#define NUMBER_OF_DEC		((NUM_OF_DEC_PER_DCORE * NUM_OF_DCORES) + NUMBER_OF_PCIE_DEC)
+
+/* Map all arcs dccm + arc schedulers acp blocks */
+#define NUM_OF_USER_ACP_BLOCKS		(NUM_OF_SCHEDULER_ARC + 2)
+#define NUM_OF_USER_NIC_UMR_BLOCKS	15
+#define NUM_OF_EXPOSED_SM_BLOCKS	((NUM_OF_DCORES - 1) * 2)
+#define NUM_USER_MAPPED_BLOCKS \
+	(NUM_ARC_CPUS + NUM_OF_USER_ACP_BLOCKS + NUMBER_OF_DEC + \
+	NUM_OF_EXPOSED_SM_BLOCKS + \
+	(NIC_NUMBER_OF_ENGINES * NUM_OF_USER_NIC_UMR_BLOCKS))
+
+/* Within the user mapped array, decoder entries start post all the ARC related
+ * entries
+ */
+#define USR_MAPPED_BLK_DEC_START_IDX \
+	(NUM_ARC_CPUS + NUM_OF_USER_ACP_BLOCKS + \
+	(NIC_NUMBER_OF_ENGINES * NUM_OF_USER_NIC_UMR_BLOCKS))
+
+#define USR_MAPPED_BLK_SM_START_IDX \
+	(NUM_ARC_CPUS + NUM_OF_USER_ACP_BLOCKS + NUMBER_OF_DEC + \
+	(NIC_NUMBER_OF_ENGINES * NUM_OF_USER_NIC_UMR_BLOCKS))
+
+#define SM_OBJS_BLOCK_SIZE		(mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_0 - \
+					 mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0)
+
+#define GAUDI2_MAX_PENDING_CS		64
+
+#if !IS_MAX_PENDING_CS_VALID(GAUDI2_MAX_PENDING_CS)
+#error "GAUDI2_MAX_PENDING_CS must be power of 2 and greater than 1"
+#endif
+
+#define CORESIGHT_TIMEOUT_USEC			100000		/* 100 ms */
+
+#define GAUDI2_PREBOOT_REQ_TIMEOUT_USEC		25000000	/* 25s */
+#define GAUDI2_PREBOOT_EXTENDED_REQ_TIMEOUT_USEC 85000000	/* 85s */
+
+#define GAUDI2_BOOT_FIT_REQ_TIMEOUT_USEC	10000000	/* 10s */
+
+#define GAUDI2_NIC_CLK_FREQ			450000000ull	/* 450 MHz */
+
+#define DC_POWER_DEFAULT			60000		/* 60W */
+
+#define GAUDI2_HBM_NUM				6
+
+#define DMA_MAX_TRANSFER_SIZE			U32_MAX
+
+#define GAUDI2_DEFAULT_CARD_NAME		"HL225"
+
+#define QMAN_STREAMS				4
+
+#define NUM_OF_MME_SBTE_PORTS			5
+#define NUM_OF_MME_WB_PORTS			2
+
+#define GAUDI2_ENGINE_ID_DCORE_OFFSET \
+	(GAUDI2_DCORE1_ENGINE_ID_EDMA_0 - GAUDI2_DCORE0_ENGINE_ID_EDMA_0)
+
+/* DRAM Memory Map */
+
+#define CPU_FW_IMAGE_SIZE			0x10000000	/* 256MB */
+#define CPU_FW_IMAGE_ADDR			DRAM_PHYS_BASE
+#define PMMU_PAGE_TABLES_SIZE			0x10000000      /* 256MB */
+#define EDMA_PQS_SIZE				SZ_2M
+#define EDMA_SCRATCHPAD_SIZE			SZ_1M
+#define HMMU_PAGE_TABLES_SIZE			SZ_1M
+
+#define NIC_NUMBER_OF_PORTS			NIC_NUMBER_OF_ENGINES
+
+#define NUMBER_OF_PCIE_DEC			2
+#define PCIE_DEC_SHIFT				8
+
+#define SRAM_USER_BASE_OFFSET			0
+
+/* cluster binning */
+#define MAX_FAULTY_HBMS				1
+#define GAUDI2_XBAR_EDGE_FULL_MASK		0xF
+#define GAUDI2_EDMA_FULL_MASK			0xFF
+#define GAUDI2_DRAM_FULL_MASK			0x3F
+
+/* Host virtual address space. */
+
+#define VA_HOST_SPACE_PAGE_START		0xFFF0000000000000ull
+#define VA_HOST_SPACE_PAGE_END			0xFFF0800000000000ull /* 140TB */
+
+#define VA_HOST_SPACE_HPAGE_START		0xFFF0800000000000ull
+#define VA_HOST_SPACE_HPAGE_END			0xFFF1000000000000ull /* 140TB */
+
+/* 140TB */
+#define VA_HOST_SPACE_PAGE_SIZE		(VA_HOST_SPACE_PAGE_END - VA_HOST_SPACE_PAGE_START)
+
+/* 140TB */
+#define VA_HOST_SPACE_HPAGE_SIZE	(VA_HOST_SPACE_HPAGE_END - VA_HOST_SPACE_HPAGE_START)
+
+#define VA_HOST_SPACE_SIZE		(VA_HOST_SPACE_PAGE_SIZE + VA_HOST_SPACE_HPAGE_SIZE)
+
+#define HOST_SPACE_INTERNAL_CB_SZ		SZ_2M
+
+/*
+ * HBM virtual address space
+ * Gaudi2 has 6 HBM devices, each supporting 16GB total of 96GB at most.
+ * No core separation is supported so we can have one chunk of virtual address
+ * space just above the physical ones.
+ * The virtual address space starts immediately after the end of the physical
+ * address space which is determined at run-time.
+ */
+#define VA_HBM_SPACE_END		0x1002000000000000ull
+
+#define HW_CAP_PLL			BIT_ULL(0)
+#define HW_CAP_DRAM			BIT_ULL(1)
+#define HW_CAP_PMMU			BIT_ULL(2)
+#define HW_CAP_CPU			BIT_ULL(3)
+#define HW_CAP_MSIX			BIT_ULL(4)
+
+#define HW_CAP_CPU_Q			BIT_ULL(5)
+#define HW_CAP_CPU_Q_SHIFT		5
+
+#define HW_CAP_CLK_GATE			BIT_ULL(6)
+#define HW_CAP_KDMA			BIT_ULL(7)
+#define HW_CAP_SRAM_SCRAMBLER		BIT_ULL(8)
+
+#define HW_CAP_DCORE0_DMMU0		BIT_ULL(9)
+#define HW_CAP_DCORE0_DMMU1		BIT_ULL(10)
+#define HW_CAP_DCORE0_DMMU2		BIT_ULL(11)
+#define HW_CAP_DCORE0_DMMU3		BIT_ULL(12)
+#define HW_CAP_DCORE1_DMMU0		BIT_ULL(13)
+#define HW_CAP_DCORE1_DMMU1		BIT_ULL(14)
+#define HW_CAP_DCORE1_DMMU2		BIT_ULL(15)
+#define HW_CAP_DCORE1_DMMU3		BIT_ULL(16)
+#define HW_CAP_DCORE2_DMMU0		BIT_ULL(17)
+#define HW_CAP_DCORE2_DMMU1		BIT_ULL(18)
+#define HW_CAP_DCORE2_DMMU2		BIT_ULL(19)
+#define HW_CAP_DCORE2_DMMU3		BIT_ULL(20)
+#define HW_CAP_DCORE3_DMMU0		BIT_ULL(21)
+#define HW_CAP_DCORE3_DMMU1		BIT_ULL(22)
+#define HW_CAP_DCORE3_DMMU2		BIT_ULL(23)
+#define HW_CAP_DCORE3_DMMU3		BIT_ULL(24)
+#define HW_CAP_DMMU_MASK		GENMASK_ULL(24, 9)
+#define HW_CAP_DMMU_SHIFT		9
+#define HW_CAP_PDMA_MASK		BIT_ULL(26)
+#define HW_CAP_EDMA_MASK		GENMASK_ULL(34, 27)
+#define HW_CAP_EDMA_SHIFT		27
+#define HW_CAP_MME_MASK			GENMASK_ULL(38, 35)
+#define HW_CAP_MME_SHIFT		35
+#define HW_CAP_ROT_MASK			GENMASK_ULL(40, 39)
+#define HW_CAP_ROT_SHIFT		39
+#define HW_CAP_HBM_SCRAMBLER_HW_RESET	BIT_ULL(41)
+#define HW_CAP_HBM_SCRAMBLER_SW_RESET	BIT_ULL(42)
+#define HW_CAP_HBM_SCRAMBLER_MASK	(HW_CAP_HBM_SCRAMBLER_HW_RESET | \
+						HW_CAP_HBM_SCRAMBLER_SW_RESET)
+#define HW_CAP_HBM_SCRAMBLER_SHIFT	41
+#define HW_CAP_RESERVED			BIT(43)
+#define HW_CAP_MMU_MASK			(HW_CAP_PMMU | HW_CAP_DMMU_MASK)
+
+/* Range Registers */
+#define RR_TYPE_SHORT			0
+#define RR_TYPE_LONG			1
+#define RR_TYPE_SHORT_PRIV		2
+#define RR_TYPE_LONG_PRIV		3
+#define NUM_SHORT_LBW_RR		14
+#define NUM_LONG_LBW_RR			4
+#define NUM_SHORT_HBW_RR		6
+#define NUM_LONG_HBW_RR			4
+
+/* RAZWI initiator coordinates- X- 5 bits, Y- 4 bits */
+#define RAZWI_INITIATOR_X_SHIFT		0
+#define RAZWI_INITIATOR_X_MASK		0x1F
+#define RAZWI_INITIATOR_Y_SHIFT		5
+#define RAZWI_INITIATOR_Y_MASK		0xF
+
+#define RTR_ID_X_Y(x, y) \
+	((((y) & RAZWI_INITIATOR_Y_MASK) << RAZWI_INITIATOR_Y_SHIFT) | \
+		(((x) & RAZWI_INITIATOR_X_MASK) << RAZWI_INITIATOR_X_SHIFT))
+
+/* decoders have separate mask */
+#define HW_CAP_DEC_SHIFT		0
+#define HW_CAP_DEC_MASK			GENMASK_ULL(9, 0)
+
+/* TPCs have separate mask */
+#define HW_CAP_TPC_SHIFT		0
+#define HW_CAP_TPC_MASK			GENMASK_ULL(24, 0)
+
+/* nics have separate mask */
+#define HW_CAP_NIC_SHIFT		0
+#define HW_CAP_NIC_MASK			GENMASK_ULL(NIC_NUMBER_OF_ENGINES - 1, 0)
+
+#define GAUDI2_ARC_PCI_MSB_ADDR(addr)	(((addr) & GENMASK_ULL(49, 28)) >> 28)
+
+#define GAUDI2_SOB_INCREMENT_BY_ONE	(FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_VAL_MASK, 1) | \
+					FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_INC_MASK, 1))
+
+#define GAUDI2_NUM_TESTED_QS		(GAUDI2_QUEUE_ID_CPU_PQ - GAUDI2_QUEUE_ID_PDMA_0_0)
+
+
+extern const char *gaudi2_engine_id_str[];
+extern const char *gaudi2_queue_id_str[];
+
+#define GAUDI2_ENG_ID_TO_STR(initiator) ((initiator) >= GAUDI2_ENGINE_ID_SIZE ? "not found" :	\
+						gaudi2_engine_id_str[initiator])
+
+#define GAUDI2_QUEUE_ID_TO_STR(initiator) ((initiator) >= GAUDI2_QUEUE_ID_SIZE ? "not found" :	\
+						gaudi2_queue_id_str[initiator])
+
+enum gaudi2_reserved_sob_id {
+	GAUDI2_RESERVED_SOB_CS_COMPLETION_FIRST,
+	GAUDI2_RESERVED_SOB_CS_COMPLETION_LAST =
+			GAUDI2_RESERVED_SOB_CS_COMPLETION_FIRST + GAUDI2_MAX_PENDING_CS - 1,
+	GAUDI2_RESERVED_SOB_KDMA_COMPLETION,
+	GAUDI2_RESERVED_SOB_DEC_NRM_FIRST,
+	GAUDI2_RESERVED_SOB_DEC_NRM_LAST =
+			GAUDI2_RESERVED_SOB_DEC_NRM_FIRST + NUMBER_OF_DEC - 1,
+	GAUDI2_RESERVED_SOB_DEC_ABNRM_FIRST,
+	GAUDI2_RESERVED_SOB_DEC_ABNRM_LAST =
+			GAUDI2_RESERVED_SOB_DEC_ABNRM_FIRST + NUMBER_OF_DEC - 1,
+	GAUDI2_RESERVED_SOB_NUMBER
+};
+
+enum gaudi2_reserved_mon_id {
+	GAUDI2_RESERVED_MON_CS_COMPLETION_FIRST,
+	GAUDI2_RESERVED_MON_CS_COMPLETION_LAST =
+			GAUDI2_RESERVED_MON_CS_COMPLETION_FIRST + GAUDI2_MAX_PENDING_CS - 1,
+	GAUDI2_RESERVED_MON_KDMA_COMPLETION,
+	GAUDI2_RESERVED_MON_DEC_NRM_FIRST,
+	GAUDI2_RESERVED_MON_DEC_NRM_LAST =
+			GAUDI2_RESERVED_MON_DEC_NRM_FIRST + 3 * NUMBER_OF_DEC - 1,
+	GAUDI2_RESERVED_MON_DEC_ABNRM_FIRST,
+	GAUDI2_RESERVED_MON_DEC_ABNRM_LAST =
+			GAUDI2_RESERVED_MON_DEC_ABNRM_FIRST + 3 * NUMBER_OF_DEC - 1,
+	GAUDI2_RESERVED_MON_NUMBER
+};
+
+enum gaudi2_reserved_cq_id {
+	GAUDI2_RESERVED_CQ_CS_COMPLETION,
+	GAUDI2_RESERVED_CQ_KDMA_COMPLETION,
+	GAUDI2_RESERVED_CQ_NUMBER
+};
+
+/*
+ * Gaudi2 subtitute TPCs Numbering
+ * At most- two faulty TPCs are allowed
+ * First replacement to a faulty TPC will be TPC24, second- TPC23
+ */
+enum substitude_tpc {
+	FAULTY_TPC_SUBTS_1_TPC_24,
+	FAULTY_TPC_SUBTS_2_TPC_23,
+	MAX_FAULTY_TPCS
+};
+
+enum gaudi2_dma_core_id {
+	DMA_CORE_ID_PDMA0, /* Dcore 0 */
+	DMA_CORE_ID_PDMA1, /* Dcore 0 */
+	DMA_CORE_ID_EDMA0, /* Dcore 0 */
+	DMA_CORE_ID_EDMA1, /* Dcore 0 */
+	DMA_CORE_ID_EDMA2, /* Dcore 1 */
+	DMA_CORE_ID_EDMA3, /* Dcore 1 */
+	DMA_CORE_ID_EDMA4, /* Dcore 2 */
+	DMA_CORE_ID_EDMA5, /* Dcore 2 */
+	DMA_CORE_ID_EDMA6, /* Dcore 3 */
+	DMA_CORE_ID_EDMA7, /* Dcore 3 */
+	DMA_CORE_ID_KDMA, /* Dcore 0 */
+	DMA_CORE_ID_SIZE
+};
+
+enum gaudi2_rotator_id {
+	ROTATOR_ID_0,
+	ROTATOR_ID_1,
+	ROTATOR_ID_SIZE,
+};
+
+enum gaudi2_mme_id {
+	MME_ID_DCORE0,
+	MME_ID_DCORE1,
+	MME_ID_DCORE2,
+	MME_ID_DCORE3,
+	MME_ID_SIZE,
+};
+
+enum gaudi2_tpc_id {
+	TPC_ID_DCORE0_TPC0,
+	TPC_ID_DCORE0_TPC1,
+	TPC_ID_DCORE0_TPC2,
+	TPC_ID_DCORE0_TPC3,
+	TPC_ID_DCORE0_TPC4,
+	TPC_ID_DCORE0_TPC5,
+	TPC_ID_DCORE1_TPC0,
+	TPC_ID_DCORE1_TPC1,
+	TPC_ID_DCORE1_TPC2,
+	TPC_ID_DCORE1_TPC3,
+	TPC_ID_DCORE1_TPC4,
+	TPC_ID_DCORE1_TPC5,
+	TPC_ID_DCORE2_TPC0,
+	TPC_ID_DCORE2_TPC1,
+	TPC_ID_DCORE2_TPC2,
+	TPC_ID_DCORE2_TPC3,
+	TPC_ID_DCORE2_TPC4,
+	TPC_ID_DCORE2_TPC5,
+	TPC_ID_DCORE3_TPC0,
+	TPC_ID_DCORE3_TPC1,
+	TPC_ID_DCORE3_TPC2,
+	TPC_ID_DCORE3_TPC3,
+	TPC_ID_DCORE3_TPC4,
+	TPC_ID_DCORE3_TPC5,
+	/* the PCI TPC is placed last (mapped liked HW) */
+	TPC_ID_DCORE0_TPC6,
+	TPC_ID_SIZE,
+};
+
+enum gaudi2_dec_id {
+	DEC_ID_DCORE0_DEC0,
+	DEC_ID_DCORE0_DEC1,
+	DEC_ID_DCORE1_DEC0,
+	DEC_ID_DCORE1_DEC1,
+	DEC_ID_DCORE2_DEC0,
+	DEC_ID_DCORE2_DEC1,
+	DEC_ID_DCORE3_DEC0,
+	DEC_ID_DCORE3_DEC1,
+	DEC_ID_PCIE_VDEC0,
+	DEC_ID_PCIE_VDEC1,
+	DEC_ID_SIZE,
+};
+
+enum gaudi2_hbm_id {
+	HBM_ID0,
+	HBM_ID1,
+	HBM_ID2,
+	HBM_ID3,
+	HBM_ID4,
+	HBM_ID5,
+	HBM_ID_SIZE,
+};
+
+/* specific EDMA enumeration */
+enum gaudi2_edma_id {
+	EDMA_ID_DCORE0_INSTANCE0,
+	EDMA_ID_DCORE0_INSTANCE1,
+	EDMA_ID_DCORE1_INSTANCE0,
+	EDMA_ID_DCORE1_INSTANCE1,
+	EDMA_ID_DCORE2_INSTANCE0,
+	EDMA_ID_DCORE2_INSTANCE1,
+	EDMA_ID_DCORE3_INSTANCE0,
+	EDMA_ID_DCORE3_INSTANCE1,
+	EDMA_ID_SIZE,
+};
+
+/* User interrupt count is aligned with HW CQ count.
+ * We have 64 CQ's per dcore, CQ0 in dcore 0 is reserved for legacy mode
+ */
+#define GAUDI2_NUM_USER_INTERRUPTS 64
+#define GAUDI2_NUM_RESERVED_INTERRUPTS 1
+#define GAUDI2_TOTAL_USER_INTERRUPTS (GAUDI2_NUM_USER_INTERRUPTS + GAUDI2_NUM_RESERVED_INTERRUPTS)
+
+enum gaudi2_irq_num {
+	GAUDI2_IRQ_NUM_EVENT_QUEUE = GAUDI2_EVENT_QUEUE_MSIX_IDX,
+	GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM,
+	GAUDI2_IRQ_NUM_DCORE0_DEC0_ABNRM,
+	GAUDI2_IRQ_NUM_DCORE0_DEC1_NRM,
+	GAUDI2_IRQ_NUM_DCORE0_DEC1_ABNRM,
+	GAUDI2_IRQ_NUM_DCORE1_DEC0_NRM,
+	GAUDI2_IRQ_NUM_DCORE1_DEC0_ABNRM,
+	GAUDI2_IRQ_NUM_DCORE1_DEC1_NRM,
+	GAUDI2_IRQ_NUM_DCORE1_DEC1_ABNRM,
+	GAUDI2_IRQ_NUM_DCORE2_DEC0_NRM,
+	GAUDI2_IRQ_NUM_DCORE2_DEC0_ABNRM,
+	GAUDI2_IRQ_NUM_DCORE2_DEC1_NRM,
+	GAUDI2_IRQ_NUM_DCORE2_DEC1_ABNRM,
+	GAUDI2_IRQ_NUM_DCORE3_DEC0_NRM,
+	GAUDI2_IRQ_NUM_DCORE3_DEC0_ABNRM,
+	GAUDI2_IRQ_NUM_DCORE3_DEC1_NRM,
+	GAUDI2_IRQ_NUM_DCORE3_DEC1_ABNRM,
+	GAUDI2_IRQ_NUM_SHARED_DEC0_NRM,
+	GAUDI2_IRQ_NUM_SHARED_DEC0_ABNRM,
+	GAUDI2_IRQ_NUM_SHARED_DEC1_NRM,
+	GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM,
+	GAUDI2_IRQ_NUM_DEC_LAST = GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM,
+	GAUDI2_IRQ_NUM_COMPLETION,
+	GAUDI2_IRQ_NUM_NIC_PORT_FIRST,
+	GAUDI2_IRQ_NUM_NIC_PORT_LAST = (GAUDI2_IRQ_NUM_NIC_PORT_FIRST + NIC_NUMBER_OF_PORTS - 1),
+	GAUDI2_IRQ_NUM_TPC_ASSERT,
+	GAUDI2_IRQ_NUM_EQ_ERROR,
+	GAUDI2_IRQ_NUM_USER_FIRST,
+	GAUDI2_IRQ_NUM_USER_LAST = (GAUDI2_IRQ_NUM_USER_FIRST + GAUDI2_NUM_USER_INTERRUPTS - 1),
+	GAUDI2_IRQ_NUM_RESERVED_FIRST,
+	GAUDI2_IRQ_NUM_RESERVED_LAST = (GAUDI2_MSIX_ENTRIES - GAUDI2_NUM_RESERVED_INTERRUPTS - 1),
+	GAUDI2_IRQ_NUM_UNEXPECTED_ERROR = RESERVED_MSIX_UNEXPECTED_USER_ERROR_INTERRUPT,
+	GAUDI2_IRQ_NUM_LAST = (GAUDI2_MSIX_ENTRIES - 1)
+};
+
+static_assert(GAUDI2_IRQ_NUM_USER_FIRST > GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM);
+
+/**
+ * struct dup_block_ctx - context to initialize unit instances across multiple
+ *                        blocks where block can be either a dcore of duplicated
+ *                        common module. this code relies on constant offsets
+ *                        of blocks and unit instances in a block.
+ * @instance_cfg_fn: instance specific configuration function.
+ * @data: private configuration data.
+ * @base: base address of the first instance in the first block.
+ * @block_off: subsequent blocks address spacing.
+ * @instance_off: subsequent block's instances address spacing.
+ * @enabled_mask: mask of enabled instances (1- enabled, 0- disabled).
+ * @blocks: number of blocks.
+ * @instances: unit instances per block.
+ */
+struct dup_block_ctx {
+	void (*instance_cfg_fn)(struct hl_device *hdev, u64 base, void *data);
+	void *data;
+	u64 base;
+	u64 block_off;
+	u64 instance_off;
+	u64 enabled_mask;
+	unsigned int blocks;
+	unsigned int instances;
+};
+
+/**
+ * struct gaudi2_queues_test_info - Holds the address of a the messages used for testing the
+ *                                  device queues.
+ * @dma_addr: the address used by the HW for accessing the message.
+ * @kern_addr: The address used by the driver for accessing the message.
+ */
+struct gaudi2_queues_test_info {
+	dma_addr_t dma_addr;
+	void *kern_addr;
+};
+
+/**
+ * struct gaudi2_device - ASIC specific manage structure.
+ * @cpucp_info_get: get information on device from CPU-CP
+ * @mapped_blocks: array that holds the base address and size of all blocks
+ *                 the user can map.
+ * @lfsr_rand_seeds: array of MME ACC random seeds to set.
+ * @hw_queues_lock: protects the H/W queues from concurrent access.
+ * @scratchpad_kernel_address: general purpose PAGE_SIZE contiguous memory,
+ *                             this memory region should be write-only.
+ *                             currently used for HBW QMAN writes which is
+ *                             redundant.
+ * @scratchpad_bus_address: scratchpad bus address
+ * @virt_msix_db_cpu_addr: host memory page for the virtual MSI-X doorbell.
+ * @virt_msix_db_dma_addr: bus address of the page for the virtual MSI-X doorbell.
+ * @dram_bar_cur_addr: current address of DRAM PCI bar.
+ * @hw_cap_initialized: This field contains a bit per H/W engine. When that
+ *                      engine is initialized, that bit is set by the driver to
+ *                      signal we can use this engine in later code paths.
+ *                      Each bit is cleared upon reset of its corresponding H/W
+ *                      engine.
+ * @active_hw_arc: This field contains a bit per ARC of an H/W engine with
+ *                 exception of TPC and NIC engines. Once an engine arc is
+ *                 initialized, its respective bit is set. Driver can uniquely
+ *                 identify each initialized ARC and use this information in
+ *                 later code paths. Each respective bit is cleared upon reset
+ *                 of its corresponding ARC of the H/W engine.
+ * @dec_hw_cap_initialized: This field contains a bit per decoder H/W engine.
+ *                      When that engine is initialized, that bit is set by
+ *                      the driver to signal we can use this engine in later
+ *                      code paths.
+ *                      Each bit is cleared upon reset of its corresponding H/W
+ *                      engine.
+ * @tpc_hw_cap_initialized: This field contains a bit per TPC H/W engine.
+ *                      When that engine is initialized, that bit is set by
+ *                      the driver to signal we can use this engine in later
+ *                      code paths.
+ *                      Each bit is cleared upon reset of its corresponding H/W
+ *                      engine.
+ * @active_tpc_arc: This field contains a bit per ARC of the TPC engines.
+ *                  Once an engine arc is initialized, its respective bit is
+ *                  set. Each respective bit is cleared upon reset of its
+ *                  corresponding ARC of the TPC engine.
+ * @nic_hw_cap_initialized: This field contains a bit per nic H/W engine.
+ * @active_nic_arc: This field contains a bit per ARC of the NIC engines.
+ *                  Once an engine arc is initialized, its respective bit is
+ *                  set. Each respective bit is cleared upon reset of its
+ *                  corresponding ARC of the NIC engine.
+ * @hw_events: array that holds all H/W events that are defined valid.
+ * @events_stat: array that holds histogram of all received events.
+ * @events_stat_aggregate: same as events_stat but doesn't get cleared on reset.
+ * @num_of_valid_hw_events: used to hold the number of valid H/W events.
+ * @nic_ports: array that holds all NIC ports manage structures.
+ * @nic_macros: array that holds all NIC macro manage structures.
+ * @core_info: core info to be used by the Ethernet driver.
+ * @aux_ops: functions for core <-> aux drivers communication.
+ * @flush_db_fifo: flag to force flush DB FIFO after a write.
+ * @hbm_cfg: HBM subsystem settings
+ * @hw_queues_lock_mutex: used by simulator instead of hw_queues_lock.
+ * @queues_test_info: information used by the driver when testing the HW queues.
+ */
+struct gaudi2_device {
+	int (*cpucp_info_get)(struct hl_device *hdev);
+
+	struct user_mapped_block	mapped_blocks[NUM_USER_MAPPED_BLOCKS];
+	int				lfsr_rand_seeds[MME_NUM_OF_LFSR_SEEDS];
+
+	spinlock_t			hw_queues_lock;
+
+	void				*scratchpad_kernel_address;
+	dma_addr_t			scratchpad_bus_address;
+
+	void				*virt_msix_db_cpu_addr;
+	dma_addr_t			virt_msix_db_dma_addr;
+
+	u64				dram_bar_cur_addr;
+	u64				hw_cap_initialized;
+	u64				active_hw_arc;
+	u64				dec_hw_cap_initialized;
+	u64				tpc_hw_cap_initialized;
+	u64				active_tpc_arc;
+	u64				nic_hw_cap_initialized;
+	u64				active_nic_arc;
+	u32				hw_events[GAUDI2_EVENT_SIZE];
+	u32				events_stat[GAUDI2_EVENT_SIZE];
+	u32				events_stat_aggregate[GAUDI2_EVENT_SIZE];
+	u32				num_of_valid_hw_events;
+
+	/* Queue testing */
+	struct gaudi2_queues_test_info	queues_test_info[GAUDI2_NUM_TESTED_QS];
+};
+
+/*
+ * Types of the Gaudi2 IP blocks, used by special blocks iterator.
+ * Required for scenarios where only particular block types can be
+ * addressed (e.g., special PLDM images).
+ */
+enum gaudi2_block_types {
+	GAUDI2_BLOCK_TYPE_PLL,
+	GAUDI2_BLOCK_TYPE_RTR,
+	GAUDI2_BLOCK_TYPE_CPU,
+	GAUDI2_BLOCK_TYPE_HIF,
+	GAUDI2_BLOCK_TYPE_HBM,
+	GAUDI2_BLOCK_TYPE_NIC,
+	GAUDI2_BLOCK_TYPE_PCIE,
+	GAUDI2_BLOCK_TYPE_PCIE_PMA,
+	GAUDI2_BLOCK_TYPE_PDMA,
+	GAUDI2_BLOCK_TYPE_EDMA,
+	GAUDI2_BLOCK_TYPE_PMMU,
+	GAUDI2_BLOCK_TYPE_PSOC,
+	GAUDI2_BLOCK_TYPE_ROT,
+	GAUDI2_BLOCK_TYPE_ARC_FARM,
+	GAUDI2_BLOCK_TYPE_DEC,
+	GAUDI2_BLOCK_TYPE_MME,
+	GAUDI2_BLOCK_TYPE_EU_BIST,
+	GAUDI2_BLOCK_TYPE_SYNC_MNGR,
+	GAUDI2_BLOCK_TYPE_STLB,
+	GAUDI2_BLOCK_TYPE_TPC,
+	GAUDI2_BLOCK_TYPE_HMMU,
+	GAUDI2_BLOCK_TYPE_SRAM,
+	GAUDI2_BLOCK_TYPE_XBAR,
+	GAUDI2_BLOCK_TYPE_KDMA,
+	GAUDI2_BLOCK_TYPE_XDMA,
+	GAUDI2_BLOCK_TYPE_XFT,
+	GAUDI2_BLOCK_TYPE_MAX
+};
+
+extern const u32 gaudi2_dma_core_blocks_bases[DMA_CORE_ID_SIZE];
+extern const u32 gaudi2_qm_blocks_bases[GAUDI2_QUEUE_ID_SIZE];
+extern const u32 gaudi2_mme_acc_blocks_bases[MME_ID_SIZE];
+extern const u32 gaudi2_mme_ctrl_lo_blocks_bases[MME_ID_SIZE];
+extern const u32 edma_stream_base[NUM_OF_EDMA_PER_DCORE * NUM_OF_DCORES];
+extern const u32 gaudi2_rot_blocks_bases[ROTATOR_ID_SIZE];
+
+void gaudi2_iterate_tpcs(struct hl_device *hdev, struct iterate_module_ctx *ctx);
+int gaudi2_coresight_init(struct hl_device *hdev);
+int gaudi2_debug_coresight(struct hl_device *hdev, struct hl_ctx *ctx, void *data);
+void gaudi2_halt_coresight(struct hl_device *hdev, struct hl_ctx *ctx);
+void gaudi2_init_blocks(struct hl_device *hdev, struct dup_block_ctx *cfg_ctx);
+bool gaudi2_is_hmmu_enabled(struct hl_device *hdev, int dcore_id, int hmmu_id);
+void gaudi2_write_rr_to_all_lbw_rtrs(struct hl_device *hdev, u8 rr_type, u32 rr_index, u64 min_val,
+					u64 max_val);
+void gaudi2_pb_print_security_errors(struct hl_device *hdev, u32 block_addr, u32 cause,
+					u32 offended_addr);
+int gaudi2_init_security(struct hl_device *hdev);
+void gaudi2_ack_protection_bits_errors(struct hl_device *hdev);
+int gaudi2_send_device_activity(struct hl_device *hdev, bool open);
+
+#endif /* GAUDI2P_H_ */
diff --git a/drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c b/drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c
new file mode 100644
index 000000000000..bc3c57bda5cd
--- /dev/null
+++ b/drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c
@@ -0,0 +1,2738 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Copyright 2019-2022 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ */
+#include "gaudi2_coresight_regs.h"
+#include <uapi/drm/habanalabs_accel.h>
+
+#define GAUDI2_PLDM_CORESIGHT_TIMEOUT_USEC	(CORESIGHT_TIMEOUT_USEC * 2000)
+#define SPMU_MAX_COUNTERS			6
+
+#define COMPONENT_ID_INVALID ((u32)(-1))
+#define MAX_BMONS_PER_UNIT 8
+
+enum gaudi2_hif_hmmu_id {
+	HMMU_ID_DCORE0_HMMU0,
+	HMMU_ID_DCORE0_HMMU1,
+	HMMU_ID_DCORE0_HMMU2,
+	HMMU_ID_DCORE0_HMMU3,
+	HMMU_ID_DCORE1_HMMU0,
+	HMMU_ID_DCORE1_HMMU1,
+	HMMU_ID_DCORE1_HMMU2,
+	HMMU_ID_DCORE1_HMMU3,
+	HMMU_ID_DCORE2_HMMU0,
+	HMMU_ID_DCORE2_HMMU1,
+	HMMU_ID_DCORE2_HMMU2,
+	HMMU_ID_DCORE2_HMMU3,
+	HMMU_ID_DCORE3_HMMU0,
+	HMMU_ID_DCORE3_HMMU1,
+	HMMU_ID_DCORE3_HMMU2,
+	HMMU_ID_DCORE3_HMMU3,
+	HMMU_ID_SIZE,
+};
+
+enum gaudi2_xbar_edge_id {
+	XBAR_EDGE_ID_DCORE0,
+	XBAR_EDGE_ID_DCORE1,
+	XBAR_EDGE_ID_DCORE2,
+	XBAR_EDGE_ID_DCORE3,
+	XBAR_EDGE_ID_SIZE
+};
+
+/**
+ * struct component_config_offsets - per cs_dbg unit - view off all related components indices
+ * @funnel_id: funnel id - index in debug_funnel_regs
+ * @etf_id: etf id - index in debug_etf_regs
+ * @stm_id: stm id - index in debug_stm_regs
+ * @spmu_id: spmu_id - index in debug_spmu_regs
+ * @bmon_count: number of bmons per unit
+ * @bmon_ids: array of bmon id (max size - MAX_BMONS_PER_UNIT) index in debug_bmon_regs
+ */
+struct component_config_offsets {
+	u32 funnel_id;
+	u32 etf_id;
+	u32 stm_id;
+	u32 spmu_id;
+	u32 bmon_count;
+	u32 bmon_ids[MAX_BMONS_PER_UNIT];
+};
+
+static u64 debug_stm_regs[GAUDI2_STM_LAST + 1] = {
+	[GAUDI2_STM_DCORE0_TPC0_EML] = mmDCORE0_TPC0_EML_STM_BASE,
+	[GAUDI2_STM_DCORE0_TPC1_EML] = mmDCORE0_TPC1_EML_STM_BASE,
+	[GAUDI2_STM_DCORE0_TPC2_EML] = mmDCORE0_TPC2_EML_STM_BASE,
+	[GAUDI2_STM_DCORE0_TPC3_EML] = mmDCORE0_TPC3_EML_STM_BASE,
+	[GAUDI2_STM_DCORE0_TPC4_EML] = mmDCORE0_TPC4_EML_STM_BASE,
+	[GAUDI2_STM_DCORE0_TPC5_EML] = mmDCORE0_TPC5_EML_STM_BASE,
+	[GAUDI2_STM_DCORE0_TPC6_EML] = mmDCORE0_TPC6_EML_STM_BASE,
+	[GAUDI2_STM_DCORE1_TPC0_EML] = mmDCORE1_TPC0_EML_STM_BASE,
+	[GAUDI2_STM_DCORE1_TPC1_EML] = mmDCORE1_TPC1_EML_STM_BASE,
+	[GAUDI2_STM_DCORE1_TPC2_EML] = mmDCORE1_TPC2_EML_STM_BASE,
+	[GAUDI2_STM_DCORE1_TPC3_EML] = mmDCORE1_TPC3_EML_STM_BASE,
+	[GAUDI2_STM_DCORE1_TPC4_EML] = mmDCORE1_TPC4_EML_STM_BASE,
+	[GAUDI2_STM_DCORE1_TPC5_EML] = mmDCORE1_TPC5_EML_STM_BASE,
+	[GAUDI2_STM_DCORE2_TPC0_EML] = mmDCORE2_TPC0_EML_STM_BASE,
+	[GAUDI2_STM_DCORE2_TPC1_EML] = mmDCORE2_TPC1_EML_STM_BASE,
+	[GAUDI2_STM_DCORE2_TPC2_EML] = mmDCORE2_TPC2_EML_STM_BASE,
+	[GAUDI2_STM_DCORE2_TPC3_EML] = mmDCORE2_TPC3_EML_STM_BASE,
+	[GAUDI2_STM_DCORE2_TPC4_EML] = mmDCORE2_TPC4_EML_STM_BASE,
+	[GAUDI2_STM_DCORE2_TPC5_EML] = mmDCORE2_TPC5_EML_STM_BASE,
+	[GAUDI2_STM_DCORE3_TPC0_EML] = mmDCORE3_TPC0_EML_STM_BASE,
+	[GAUDI2_STM_DCORE3_TPC1_EML] = mmDCORE3_TPC1_EML_STM_BASE,
+	[GAUDI2_STM_DCORE3_TPC2_EML] = mmDCORE3_TPC2_EML_STM_BASE,
+	[GAUDI2_STM_DCORE3_TPC3_EML] = mmDCORE3_TPC3_EML_STM_BASE,
+	[GAUDI2_STM_DCORE3_TPC4_EML] = mmDCORE3_TPC4_EML_STM_BASE,
+	[GAUDI2_STM_DCORE3_TPC5_EML] = mmDCORE3_TPC5_EML_STM_BASE,
+	[GAUDI2_STM_DCORE0_HMMU0_CS] = mmDCORE0_HMMU0_CS_STM_BASE,
+	[GAUDI2_STM_DCORE0_HMMU1_CS] = mmDCORE0_HMMU1_CS_STM_BASE,
+	[GAUDI2_STM_DCORE0_HMMU2_CS] = mmDCORE0_HMMU2_CS_STM_BASE,
+	[GAUDI2_STM_DCORE0_HMMU3_CS] = mmDCORE0_HMMU3_CS_STM_BASE,
+	[GAUDI2_STM_DCORE0_MME_CTRL] = mmDCORE0_MME_CTRL_STM_BASE,
+	[GAUDI2_STM_DCORE0_MME_SBTE0] = mmDCORE0_MME_SBTE0_STM_BASE,
+	[GAUDI2_STM_DCORE0_MME_SBTE1] = mmDCORE0_MME_SBTE1_STM_BASE,
+	[GAUDI2_STM_DCORE0_MME_SBTE2] = mmDCORE0_MME_SBTE2_STM_BASE,
+	[GAUDI2_STM_DCORE0_MME_SBTE3] = mmDCORE0_MME_SBTE3_STM_BASE,
+	[GAUDI2_STM_DCORE0_MME_SBTE4] = mmDCORE0_MME_SBTE4_STM_BASE,
+	[GAUDI2_STM_DCORE0_MME_ACC] = mmDCORE0_MME_ACC_STM_BASE,
+	[GAUDI2_STM_DCORE0_SM] = mmDCORE0_SM_STM_BASE,
+	[GAUDI2_STM_DCORE0_EDMA0_CS] = mmDCORE0_EDMA0_CS_STM_BASE,
+	[GAUDI2_STM_DCORE0_EDMA1_CS] = mmDCORE0_EDMA1_CS_STM_BASE,
+	[GAUDI2_STM_DCORE0_VDEC0_CS] = mmDCORE0_VDEC0_CS_STM_BASE,
+	[GAUDI2_STM_DCORE0_VDEC1_CS] = mmDCORE0_VDEC1_CS_STM_BASE,
+	[GAUDI2_STM_DCORE1_HMMU0_CS] = mmDCORE1_HMMU0_CS_STM_BASE,
+	[GAUDI2_STM_DCORE1_HMMU1_CS] = mmDCORE1_HMMU1_CS_STM_BASE,
+	[GAUDI2_STM_DCORE1_HMMU2_CS] = mmDCORE1_HMMU2_CS_STM_BASE,
+	[GAUDI2_STM_DCORE1_HMMU3_CS] = mmDCORE1_HMMU3_CS_STM_BASE,
+	[GAUDI2_STM_DCORE1_MME_CTRL] = mmDCORE1_MME_CTRL_STM_BASE,
+	[GAUDI2_STM_DCORE1_MME_SBTE0] = mmDCORE1_MME_SBTE0_STM_BASE,
+	[GAUDI2_STM_DCORE1_MME_SBTE1] = mmDCORE1_MME_SBTE1_STM_BASE,
+	[GAUDI2_STM_DCORE1_MME_SBTE2] = mmDCORE1_MME_SBTE2_STM_BASE,
+	[GAUDI2_STM_DCORE1_MME_SBTE3] = mmDCORE1_MME_SBTE3_STM_BASE,
+	[GAUDI2_STM_DCORE1_MME_SBTE4] = mmDCORE1_MME_SBTE4_STM_BASE,
+	[GAUDI2_STM_DCORE1_MME_ACC] = mmDCORE1_MME_ACC_STM_BASE,
+	[GAUDI2_STM_DCORE1_SM] = mmDCORE1_SM_STM_BASE,
+	[GAUDI2_STM_DCORE1_EDMA0_CS] = mmDCORE1_EDMA0_CS_STM_BASE,
+	[GAUDI2_STM_DCORE1_EDMA1_CS] = mmDCORE1_EDMA1_CS_STM_BASE,
+	[GAUDI2_STM_DCORE1_VDEC0_CS] = mmDCORE1_VDEC0_CS_STM_BASE,
+	[GAUDI2_STM_DCORE1_VDEC1_CS] = mmDCORE1_VDEC1_CS_STM_BASE,
+	[GAUDI2_STM_DCORE2_HMMU0_CS] = mmDCORE2_HMMU0_CS_STM_BASE,
+	[GAUDI2_STM_DCORE2_HMMU1_CS] = mmDCORE2_HMMU1_CS_STM_BASE,
+	[GAUDI2_STM_DCORE2_HMMU2_CS] = mmDCORE2_HMMU2_CS_STM_BASE,
+	[GAUDI2_STM_DCORE2_HMMU3_CS] = mmDCORE2_HMMU3_CS_STM_BASE,
+	[GAUDI2_STM_DCORE2_MME_CTRL] = mmDCORE2_MME_CTRL_STM_BASE,
+	[GAUDI2_STM_DCORE2_MME_SBTE0] = mmDCORE2_MME_SBTE0_STM_BASE,
+	[GAUDI2_STM_DCORE2_MME_SBTE1] = mmDCORE2_MME_SBTE1_STM_BASE,
+	[GAUDI2_STM_DCORE2_MME_SBTE2] = mmDCORE2_MME_SBTE2_STM_BASE,
+	[GAUDI2_STM_DCORE2_MME_SBTE3] = mmDCORE2_MME_SBTE3_STM_BASE,
+	[GAUDI2_STM_DCORE2_MME_SBTE4] = mmDCORE2_MME_SBTE4_STM_BASE,
+	[GAUDI2_STM_DCORE2_MME_ACC] = mmDCORE2_MME_ACC_STM_BASE,
+	[GAUDI2_STM_DCORE2_SM] = mmDCORE2_SM_STM_BASE,
+	[GAUDI2_STM_DCORE2_EDMA0_CS] = mmDCORE2_EDMA0_CS_STM_BASE,
+	[GAUDI2_STM_DCORE2_EDMA1_CS] = mmDCORE2_EDMA1_CS_STM_BASE,
+	[GAUDI2_STM_DCORE2_VDEC0_CS] = mmDCORE2_VDEC0_CS_STM_BASE,
+	[GAUDI2_STM_DCORE2_VDEC1_CS] = mmDCORE2_VDEC1_CS_STM_BASE,
+	[GAUDI2_STM_DCORE3_HMMU0_CS] = mmDCORE3_HMMU0_CS_STM_BASE,
+	[GAUDI2_STM_DCORE3_HMMU1_CS] = mmDCORE3_HMMU1_CS_STM_BASE,
+	[GAUDI2_STM_DCORE3_HMMU2_CS] = mmDCORE3_HMMU2_CS_STM_BASE,
+	[GAUDI2_STM_DCORE3_HMMU3_CS] = mmDCORE3_HMMU3_CS_STM_BASE,
+	[GAUDI2_STM_DCORE3_MME_CTRL] = mmDCORE3_MME_CTRL_STM_BASE,
+	[GAUDI2_STM_DCORE3_MME_SBTE0] = mmDCORE3_MME_SBTE0_STM_BASE,
+	[GAUDI2_STM_DCORE3_MME_SBTE1] = mmDCORE3_MME_SBTE1_STM_BASE,
+	[GAUDI2_STM_DCORE3_MME_SBTE2] = mmDCORE3_MME_SBTE2_STM_BASE,
+	[GAUDI2_STM_DCORE3_MME_SBTE3] = mmDCORE3_MME_SBTE3_STM_BASE,
+	[GAUDI2_STM_DCORE3_MME_SBTE4] = mmDCORE3_MME_SBTE4_STM_BASE,
+	[GAUDI2_STM_DCORE3_MME_ACC] = mmDCORE3_MME_ACC_STM_BASE,
+	[GAUDI2_STM_DCORE3_SM] = mmDCORE3_SM_STM_BASE,
+	[GAUDI2_STM_DCORE3_EDMA0_CS] = mmDCORE3_EDMA0_CS_STM_BASE,
+	[GAUDI2_STM_DCORE3_EDMA1_CS] = mmDCORE3_EDMA1_CS_STM_BASE,
+	[GAUDI2_STM_DCORE3_VDEC0_CS] = mmDCORE3_VDEC0_CS_STM_BASE,
+	[GAUDI2_STM_DCORE3_VDEC1_CS] = mmDCORE3_VDEC1_CS_STM_BASE,
+	[GAUDI2_STM_PCIE] = mmPCIE_STM_BASE,
+	[GAUDI2_STM_PSOC] = mmPSOC_STM_BASE,
+	[GAUDI2_STM_PSOC_ARC0_CS] = 0,
+	[GAUDI2_STM_PSOC_ARC1_CS] = 0,
+	[GAUDI2_STM_PDMA0_CS] = mmPDMA0_CS_STM_BASE,
+	[GAUDI2_STM_PDMA1_CS] = mmPDMA1_CS_STM_BASE,
+	[GAUDI2_STM_CPU] = mmCPU_STM_BASE,
+	[GAUDI2_STM_PMMU_CS] = mmPMMU_CS_STM_BASE,
+	[GAUDI2_STM_ROT0_CS] = mmROT0_CS_STM_BASE,
+	[GAUDI2_STM_ROT1_CS] = mmROT1_CS_STM_BASE,
+	[GAUDI2_STM_ARC_FARM_CS] = mmARC_FARM_CS_STM_BASE,
+	[GAUDI2_STM_KDMA_CS] = mmKDMA_CS_STM_BASE,
+	[GAUDI2_STM_PCIE_VDEC0_CS] = mmPCIE_VDEC0_CS_STM_BASE,
+	[GAUDI2_STM_PCIE_VDEC1_CS] = mmPCIE_VDEC1_CS_STM_BASE,
+	[GAUDI2_STM_HBM0_MC0_CS] = mmHBM0_MC0_CS_STM_BASE,
+	[GAUDI2_STM_HBM0_MC1_CS] = mmHBM0_MC1_CS_STM_BASE,
+	[GAUDI2_STM_HBM1_MC0_CS] = mmHBM1_MC0_CS_STM_BASE,
+	[GAUDI2_STM_HBM1_MC1_CS] = mmHBM1_MC1_CS_STM_BASE,
+	[GAUDI2_STM_HBM2_MC0_CS] = mmHBM2_MC0_CS_STM_BASE,
+	[GAUDI2_STM_HBM2_MC1_CS] = mmHBM2_MC1_CS_STM_BASE,
+	[GAUDI2_STM_HBM3_MC0_CS] = mmHBM3_MC0_CS_STM_BASE,
+	[GAUDI2_STM_HBM3_MC1_CS] = mmHBM3_MC1_CS_STM_BASE,
+	[GAUDI2_STM_HBM4_MC0_CS] = mmHBM4_MC0_CS_STM_BASE,
+	[GAUDI2_STM_HBM4_MC1_CS] = mmHBM4_MC1_CS_STM_BASE,
+	[GAUDI2_STM_HBM5_MC0_CS] = mmHBM5_MC0_CS_STM_BASE,
+	[GAUDI2_STM_HBM5_MC1_CS] = mmHBM5_MC1_CS_STM_BASE,
+	[GAUDI2_STM_NIC0_DBG_0] = mmNIC0_DBG_STM_0_BASE,
+	[GAUDI2_STM_NIC0_DBG_1] = mmNIC0_DBG_STM_1_BASE,
+	[GAUDI2_STM_NIC1_DBG_0] = mmNIC1_DBG_STM_0_BASE,
+	[GAUDI2_STM_NIC1_DBG_1] = mmNIC1_DBG_STM_1_BASE,
+	[GAUDI2_STM_NIC2_DBG_0] = mmNIC2_DBG_STM_0_BASE,
+	[GAUDI2_STM_NIC2_DBG_1] = mmNIC2_DBG_STM_1_BASE,
+	[GAUDI2_STM_NIC3_DBG_0] = mmNIC3_DBG_STM_0_BASE,
+	[GAUDI2_STM_NIC3_DBG_1] = mmNIC3_DBG_STM_1_BASE,
+	[GAUDI2_STM_NIC4_DBG_0] = mmNIC4_DBG_STM_0_BASE,
+	[GAUDI2_STM_NIC4_DBG_1] = mmNIC4_DBG_STM_1_BASE,
+	[GAUDI2_STM_NIC5_DBG_0] = mmNIC5_DBG_STM_0_BASE,
+	[GAUDI2_STM_NIC5_DBG_1] = mmNIC5_DBG_STM_1_BASE,
+	[GAUDI2_STM_NIC6_DBG_0] = mmNIC6_DBG_STM_0_BASE,
+	[GAUDI2_STM_NIC6_DBG_1] = mmNIC6_DBG_STM_1_BASE,
+	[GAUDI2_STM_NIC7_DBG_0] = mmNIC7_DBG_STM_0_BASE,
+	[GAUDI2_STM_NIC7_DBG_1] = mmNIC7_DBG_STM_1_BASE,
+	[GAUDI2_STM_NIC8_DBG_0] = mmNIC8_DBG_STM_0_BASE,
+	[GAUDI2_STM_NIC8_DBG_1] = mmNIC8_DBG_STM_1_BASE,
+	[GAUDI2_STM_NIC9_DBG_0] = mmNIC9_DBG_STM_0_BASE,
+	[GAUDI2_STM_NIC9_DBG_1] = mmNIC9_DBG_STM_1_BASE,
+	[GAUDI2_STM_NIC10_DBG_0] = mmNIC10_DBG_STM_0_BASE,
+	[GAUDI2_STM_NIC10_DBG_1] = mmNIC10_DBG_STM_1_BASE,
+	[GAUDI2_STM_NIC11_DBG_0] = mmNIC11_DBG_STM_0_BASE,
+	[GAUDI2_STM_NIC11_DBG_1] = mmNIC11_DBG_STM_1_BASE
+};
+
+static u64 debug_etf_regs[GAUDI2_ETF_LAST + 1] = {
+	[GAUDI2_ETF_DCORE0_TPC0_EML] = mmDCORE0_TPC0_EML_ETF_BASE,
+	[GAUDI2_ETF_DCORE0_TPC1_EML] = mmDCORE0_TPC1_EML_ETF_BASE,
+	[GAUDI2_ETF_DCORE0_TPC2_EML] = mmDCORE0_TPC2_EML_ETF_BASE,
+	[GAUDI2_ETF_DCORE0_TPC3_EML] = mmDCORE0_TPC3_EML_ETF_BASE,
+	[GAUDI2_ETF_DCORE0_TPC4_EML] = mmDCORE0_TPC4_EML_ETF_BASE,
+	[GAUDI2_ETF_DCORE0_TPC5_EML] = mmDCORE0_TPC5_EML_ETF_BASE,
+	[GAUDI2_ETF_DCORE0_TPC6_EML] = mmDCORE0_TPC6_EML_ETF_BASE,
+	[GAUDI2_ETF_DCORE1_TPC0_EML] = mmDCORE1_TPC0_EML_ETF_BASE,
+	[GAUDI2_ETF_DCORE1_TPC1_EML] = mmDCORE1_TPC1_EML_ETF_BASE,
+	[GAUDI2_ETF_DCORE1_TPC2_EML] = mmDCORE1_TPC2_EML_ETF_BASE,
+	[GAUDI2_ETF_DCORE1_TPC3_EML] = mmDCORE1_TPC3_EML_ETF_BASE,
+	[GAUDI2_ETF_DCORE1_TPC4_EML] = mmDCORE1_TPC4_EML_ETF_BASE,
+	[GAUDI2_ETF_DCORE1_TPC5_EML] = mmDCORE1_TPC5_EML_ETF_BASE,
+	[GAUDI2_ETF_DCORE2_TPC0_EML] = mmDCORE2_TPC0_EML_ETF_BASE,
+	[GAUDI2_ETF_DCORE2_TPC1_EML] = mmDCORE2_TPC1_EML_ETF_BASE,
+	[GAUDI2_ETF_DCORE2_TPC2_EML] = mmDCORE2_TPC2_EML_ETF_BASE,
+	[GAUDI2_ETF_DCORE2_TPC3_EML] = mmDCORE2_TPC3_EML_ETF_BASE,
+	[GAUDI2_ETF_DCORE2_TPC4_EML] = mmDCORE2_TPC4_EML_ETF_BASE,
+	[GAUDI2_ETF_DCORE2_TPC5_EML] = mmDCORE2_TPC5_EML_ETF_BASE,
+	[GAUDI2_ETF_DCORE3_TPC0_EML] = mmDCORE3_TPC0_EML_ETF_BASE,
+	[GAUDI2_ETF_DCORE3_TPC1_EML] = mmDCORE3_TPC1_EML_ETF_BASE,
+	[GAUDI2_ETF_DCORE3_TPC2_EML] = mmDCORE3_TPC2_EML_ETF_BASE,
+	[GAUDI2_ETF_DCORE3_TPC3_EML] = mmDCORE3_TPC3_EML_ETF_BASE,
+	[GAUDI2_ETF_DCORE3_TPC4_EML] = mmDCORE3_TPC4_EML_ETF_BASE,
+	[GAUDI2_ETF_DCORE3_TPC5_EML] = mmDCORE3_TPC5_EML_ETF_BASE,
+	[GAUDI2_ETF_DCORE0_HMMU0_CS] = mmDCORE0_HMMU0_CS_ETF_BASE,
+	[GAUDI2_ETF_DCORE0_HMMU1_CS] = mmDCORE0_HMMU1_CS_ETF_BASE,
+	[GAUDI2_ETF_DCORE0_HMMU2_CS] = mmDCORE0_HMMU2_CS_ETF_BASE,
+	[GAUDI2_ETF_DCORE0_HMMU3_CS] = mmDCORE0_HMMU3_CS_ETF_BASE,
+	[GAUDI2_ETF_DCORE0_MME_CTRL] = mmDCORE0_MME_CTRL_ETF_BASE,
+	[GAUDI2_ETF_DCORE0_MME_SBTE0] = mmDCORE0_MME_SBTE0_ETF_BASE,
+	[GAUDI2_ETF_DCORE0_MME_SBTE1] = mmDCORE0_MME_SBTE1_ETF_BASE,
+	[GAUDI2_ETF_DCORE0_MME_SBTE2] = mmDCORE0_MME_SBTE2_ETF_BASE,
+	[GAUDI2_ETF_DCORE0_MME_SBTE3] = mmDCORE0_MME_SBTE3_ETF_BASE,
+	[GAUDI2_ETF_DCORE0_MME_SBTE4] = mmDCORE0_MME_SBTE4_ETF_BASE,
+	[GAUDI2_ETF_DCORE0_MME_ACC] = mmDCORE0_MME_ACC_ETF_BASE,
+	[GAUDI2_ETF_DCORE0_SM] = mmDCORE0_SM_ETF_BASE,
+	[GAUDI2_ETF_DCORE0_EDMA0_CS] = mmDCORE0_EDMA0_CS_ETF_BASE,
+	[GAUDI2_ETF_DCORE0_EDMA1_CS] = mmDCORE0_EDMA1_CS_ETF_BASE,
+	[GAUDI2_ETF_DCORE0_VDEC0_CS] = mmDCORE0_VDEC0_CS_ETF_BASE,
+	[GAUDI2_ETF_DCORE0_VDEC1_CS] = mmDCORE0_VDEC1_CS_ETF_BASE,
+	[GAUDI2_ETF_DCORE1_HMMU0_CS] = mmDCORE1_HMMU0_CS_ETF_BASE,
+	[GAUDI2_ETF_DCORE1_HMMU1_CS] = mmDCORE1_HMMU1_CS_ETF_BASE,
+	[GAUDI2_ETF_DCORE1_HMMU2_CS] = mmDCORE1_HMMU2_CS_ETF_BASE,
+	[GAUDI2_ETF_DCORE1_HMMU3_CS] = mmDCORE1_HMMU3_CS_ETF_BASE,
+	[GAUDI2_ETF_DCORE1_MME_CTRL] = mmDCORE1_MME_CTRL_ETF_BASE,
+	[GAUDI2_ETF_DCORE1_MME_SBTE0] = mmDCORE1_MME_SBTE0_ETF_BASE,
+	[GAUDI2_ETF_DCORE1_MME_SBTE1] = mmDCORE1_MME_SBTE1_ETF_BASE,
+	[GAUDI2_ETF_DCORE1_MME_SBTE2] = mmDCORE1_MME_SBTE2_ETF_BASE,
+	[GAUDI2_ETF_DCORE1_MME_SBTE3] = mmDCORE1_MME_SBTE3_ETF_BASE,
+	[GAUDI2_ETF_DCORE1_MME_SBTE4] = mmDCORE1_MME_SBTE4_ETF_BASE,
+	[GAUDI2_ETF_DCORE1_MME_ACC] = mmDCORE1_MME_ACC_ETF_BASE,
+	[GAUDI2_ETF_DCORE1_SM] = mmDCORE1_SM_ETF_BASE,
+	[GAUDI2_ETF_DCORE1_EDMA0_CS] = mmDCORE1_EDMA0_CS_ETF_BASE,
+	[GAUDI2_ETF_DCORE1_EDMA1_CS] = mmDCORE1_EDMA1_CS_ETF_BASE,
+	[GAUDI2_ETF_DCORE1_VDEC0_CS] = mmDCORE1_VDEC0_CS_ETF_BASE,
+	[GAUDI2_ETF_DCORE1_VDEC1_CS] = mmDCORE1_VDEC1_CS_ETF_BASE,
+	[GAUDI2_ETF_DCORE2_HMMU0_CS] = mmDCORE2_HMMU0_CS_ETF_BASE,
+	[GAUDI2_ETF_DCORE2_HMMU1_CS] = mmDCORE2_HMMU1_CS_ETF_BASE,
+	[GAUDI2_ETF_DCORE2_HMMU2_CS] = mmDCORE2_HMMU2_CS_ETF_BASE,
+	[GAUDI2_ETF_DCORE2_HMMU3_CS] = mmDCORE2_HMMU3_CS_ETF_BASE,
+	[GAUDI2_ETF_DCORE2_MME_CTRL] = mmDCORE2_MME_CTRL_ETF_BASE,
+	[GAUDI2_ETF_DCORE2_MME_SBTE0] = mmDCORE2_MME_SBTE0_ETF_BASE,
+	[GAUDI2_ETF_DCORE2_MME_SBTE1] = mmDCORE2_MME_SBTE1_ETF_BASE,
+	[GAUDI2_ETF_DCORE2_MME_SBTE2] = mmDCORE2_MME_SBTE2_ETF_BASE,
+	[GAUDI2_ETF_DCORE2_MME_SBTE3] = mmDCORE2_MME_SBTE3_ETF_BASE,
+	[GAUDI2_ETF_DCORE2_MME_SBTE4] = mmDCORE2_MME_SBTE4_ETF_BASE,
+	[GAUDI2_ETF_DCORE2_MME_ACC] = mmDCORE2_MME_ACC_ETF_BASE,
+	[GAUDI2_ETF_DCORE2_SM] = mmDCORE2_SM_ETF_BASE,
+	[GAUDI2_ETF_DCORE2_EDMA0_CS] = mmDCORE2_EDMA0_CS_ETF_BASE,
+	[GAUDI2_ETF_DCORE2_EDMA1_CS] = mmDCORE2_EDMA1_CS_ETF_BASE,
+	[GAUDI2_ETF_DCORE2_VDEC0_CS] = mmDCORE2_VDEC0_CS_ETF_BASE,
+	[GAUDI2_ETF_DCORE2_VDEC1_CS] = mmDCORE2_VDEC1_CS_ETF_BASE,
+	[GAUDI2_ETF_DCORE3_HMMU0_CS] = mmDCORE3_HMMU0_CS_ETF_BASE,
+	[GAUDI2_ETF_DCORE3_HMMU1_CS] = mmDCORE3_HMMU1_CS_ETF_BASE,
+	[GAUDI2_ETF_DCORE3_HMMU2_CS] = mmDCORE3_HMMU2_CS_ETF_BASE,
+	[GAUDI2_ETF_DCORE3_HMMU3_CS] = mmDCORE3_HMMU3_CS_ETF_BASE,
+	[GAUDI2_ETF_DCORE3_MME_CTRL] = mmDCORE3_MME_CTRL_ETF_BASE,
+	[GAUDI2_ETF_DCORE3_MME_SBTE0] = mmDCORE3_MME_SBTE0_ETF_BASE,
+	[GAUDI2_ETF_DCORE3_MME_SBTE1] = mmDCORE3_MME_SBTE1_ETF_BASE,
+	[GAUDI2_ETF_DCORE3_MME_SBTE2] = mmDCORE3_MME_SBTE2_ETF_BASE,
+	[GAUDI2_ETF_DCORE3_MME_SBTE3] = mmDCORE3_MME_SBTE3_ETF_BASE,
+	[GAUDI2_ETF_DCORE3_MME_SBTE4] = mmDCORE3_MME_SBTE4_ETF_BASE,
+	[GAUDI2_ETF_DCORE3_MME_ACC] = mmDCORE3_MME_ACC_ETF_BASE,
+	[GAUDI2_ETF_DCORE3_SM] = mmDCORE3_SM_ETF_BASE,
+	[GAUDI2_ETF_DCORE3_EDMA0_CS] = mmDCORE3_EDMA0_CS_ETF_BASE,
+	[GAUDI2_ETF_DCORE3_EDMA1_CS] = mmDCORE3_EDMA1_CS_ETF_BASE,
+	[GAUDI2_ETF_DCORE3_VDEC0_CS] = mmDCORE3_VDEC0_CS_ETF_BASE,
+	[GAUDI2_ETF_DCORE3_VDEC1_CS] = mmDCORE3_VDEC1_CS_ETF_BASE,
+	[GAUDI2_ETF_PCIE] = mmPCIE_ETF_BASE,
+	[GAUDI2_ETF_PSOC] = mmPSOC_ETF_BASE,
+	[GAUDI2_ETF_PSOC_ARC0_CS] = 0,
+	[GAUDI2_ETF_PSOC_ARC1_CS] = 0,
+	[GAUDI2_ETF_PDMA0_CS] = mmPDMA0_CS_ETF_BASE,
+	[GAUDI2_ETF_PDMA1_CS] = mmPDMA1_CS_ETF_BASE,
+	[GAUDI2_ETF_CPU_0] = mmCPU_ETF_0_BASE,
+	[GAUDI2_ETF_CPU_1] = mmCPU_ETF_1_BASE,
+	[GAUDI2_ETF_CPU_TRACE] = mmCPU_ETF_TRACE_BASE,
+	[GAUDI2_ETF_PMMU_CS] = mmPMMU_CS_ETF_BASE,
+	[GAUDI2_ETF_ROT0_CS] = mmROT0_CS_ETF_BASE,
+	[GAUDI2_ETF_ROT1_CS] = mmROT1_CS_ETF_BASE,
+	[GAUDI2_ETF_ARC_FARM_CS] = mmARC_FARM_CS_ETF_BASE,
+	[GAUDI2_ETF_KDMA_CS] = mmKDMA_CS_ETF_BASE,
+	[GAUDI2_ETF_PCIE_VDEC0_CS] = mmPCIE_VDEC0_CS_ETF_BASE,
+	[GAUDI2_ETF_PCIE_VDEC1_CS] = mmPCIE_VDEC1_CS_ETF_BASE,
+	[GAUDI2_ETF_HBM0_MC0_CS] = mmHBM0_MC0_CS_ETF_BASE,
+	[GAUDI2_ETF_HBM0_MC1_CS] = mmHBM0_MC1_CS_ETF_BASE,
+	[GAUDI2_ETF_HBM1_MC0_CS] = mmHBM1_MC0_CS_ETF_BASE,
+	[GAUDI2_ETF_HBM1_MC1_CS] = mmHBM1_MC1_CS_ETF_BASE,
+	[GAUDI2_ETF_HBM2_MC0_CS] = mmHBM2_MC0_CS_ETF_BASE,
+	[GAUDI2_ETF_HBM2_MC1_CS] = mmHBM2_MC1_CS_ETF_BASE,
+	[GAUDI2_ETF_HBM3_MC0_CS] = mmHBM3_MC0_CS_ETF_BASE,
+	[GAUDI2_ETF_HBM3_MC1_CS] = mmHBM3_MC1_CS_ETF_BASE,
+	[GAUDI2_ETF_HBM4_MC0_CS] = mmHBM4_MC0_CS_ETF_BASE,
+	[GAUDI2_ETF_HBM4_MC1_CS] = mmHBM4_MC1_CS_ETF_BASE,
+	[GAUDI2_ETF_HBM5_MC0_CS] = mmHBM5_MC0_CS_ETF_BASE,
+	[GAUDI2_ETF_HBM5_MC1_CS] = mmHBM5_MC1_CS_ETF_BASE,
+	[GAUDI2_ETF_NIC0_DBG_0] = mmNIC0_DBG_ETF_0_BASE,
+	[GAUDI2_ETF_NIC0_DBG_1] = mmNIC0_DBG_ETF_1_BASE,
+	[GAUDI2_ETF_NIC1_DBG_0] = mmNIC1_DBG_ETF_0_BASE,
+	[GAUDI2_ETF_NIC1_DBG_1] = mmNIC1_DBG_ETF_1_BASE,
+	[GAUDI2_ETF_NIC2_DBG_0] = mmNIC2_DBG_ETF_0_BASE,
+	[GAUDI2_ETF_NIC2_DBG_1] = mmNIC2_DBG_ETF_1_BASE,
+	[GAUDI2_ETF_NIC3_DBG_0] = mmNIC3_DBG_ETF_0_BASE,
+	[GAUDI2_ETF_NIC3_DBG_1] = mmNIC3_DBG_ETF_1_BASE,
+	[GAUDI2_ETF_NIC4_DBG_0] = mmNIC4_DBG_ETF_0_BASE,
+	[GAUDI2_ETF_NIC4_DBG_1] = mmNIC4_DBG_ETF_1_BASE,
+	[GAUDI2_ETF_NIC5_DBG_0] = mmNIC5_DBG_ETF_0_BASE,
+	[GAUDI2_ETF_NIC5_DBG_1] = mmNIC5_DBG_ETF_1_BASE,
+	[GAUDI2_ETF_NIC6_DBG_0] = mmNIC6_DBG_ETF_0_BASE,
+	[GAUDI2_ETF_NIC6_DBG_1] = mmNIC6_DBG_ETF_1_BASE,
+	[GAUDI2_ETF_NIC7_DBG_0] = mmNIC7_DBG_ETF_0_BASE,
+	[GAUDI2_ETF_NIC7_DBG_1] = mmNIC7_DBG_ETF_1_BASE,
+	[GAUDI2_ETF_NIC8_DBG_0] = mmNIC8_DBG_ETF_0_BASE,
+	[GAUDI2_ETF_NIC8_DBG_1] = mmNIC8_DBG_ETF_1_BASE,
+	[GAUDI2_ETF_NIC9_DBG_0] = mmNIC9_DBG_ETF_0_BASE,
+	[GAUDI2_ETF_NIC9_DBG_1] = mmNIC9_DBG_ETF_1_BASE,
+	[GAUDI2_ETF_NIC10_DBG_0] = mmNIC10_DBG_ETF_0_BASE,
+	[GAUDI2_ETF_NIC10_DBG_1] = mmNIC10_DBG_ETF_1_BASE,
+	[GAUDI2_ETF_NIC11_DBG_0] = mmNIC11_DBG_ETF_0_BASE,
+	[GAUDI2_ETF_NIC11_DBG_1] = mmNIC11_DBG_ETF_1_BASE
+};
+
+static u64 debug_funnel_regs[GAUDI2_FUNNEL_LAST + 1] = {
+	[GAUDI2_FUNNEL_DCORE0_TPC0_EML] = mmDCORE0_TPC0_EML_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE0_TPC1_EML] = mmDCORE0_TPC1_EML_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE0_TPC2_EML] = mmDCORE0_TPC2_EML_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE0_TPC3_EML] = mmDCORE0_TPC3_EML_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE0_TPC4_EML] = mmDCORE0_TPC4_EML_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE0_TPC5_EML] = mmDCORE0_TPC5_EML_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE0_TPC6_EML] = mmDCORE0_TPC6_EML_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE1_TPC0_EML] = mmDCORE1_TPC0_EML_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE1_TPC1_EML] = mmDCORE1_TPC1_EML_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE1_TPC2_EML] = mmDCORE1_TPC2_EML_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE1_TPC3_EML] = mmDCORE1_TPC3_EML_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE1_TPC4_EML] = mmDCORE1_TPC4_EML_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE1_TPC5_EML] = mmDCORE1_TPC5_EML_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE2_TPC0_EML] = mmDCORE2_TPC0_EML_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE2_TPC1_EML] = mmDCORE2_TPC1_EML_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE2_TPC2_EML] = mmDCORE2_TPC2_EML_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE2_TPC3_EML] = mmDCORE2_TPC3_EML_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE2_TPC4_EML] = mmDCORE2_TPC4_EML_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE2_TPC5_EML] = mmDCORE2_TPC5_EML_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE3_TPC0_EML] = mmDCORE3_TPC0_EML_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE3_TPC1_EML] = mmDCORE3_TPC1_EML_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE3_TPC2_EML] = mmDCORE3_TPC2_EML_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE3_TPC3_EML] = mmDCORE3_TPC3_EML_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE3_TPC4_EML] = mmDCORE3_TPC4_EML_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE3_TPC5_EML] = mmDCORE3_TPC5_EML_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE0_XFT] = mmDCORE0_XFT_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE0_TFT0] = mmDCORE0_TFT0_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE0_TFT1] = mmDCORE0_TFT1_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE0_TFT2] = mmDCORE0_TFT2_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE0_RTR0] = mmDCORE0_RTR0_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE0_RTR1] = mmDCORE0_RTR1_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE0_RTR2] = mmDCORE0_RTR2_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE0_RTR3] = mmDCORE0_RTR3_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE0_RTR4] = mmDCORE0_RTR4_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE0_MIF0] = mmDCORE0_MIF0_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE0_RTR5] = mmDCORE0_RTR5_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE0_MIF1] = mmDCORE0_MIF1_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE0_RTR6] = mmDCORE0_RTR6_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE0_MIF2] = mmDCORE0_MIF2_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE0_RTR7] = mmDCORE0_RTR7_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE0_MIF3] = mmDCORE0_MIF3_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE1_XFT] = mmDCORE1_XFT_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE1_TFT0] = mmDCORE1_TFT0_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE1_TFT1] = mmDCORE1_TFT1_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE1_TFT2] = mmDCORE1_TFT2_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE1_RTR0] = mmDCORE1_RTR0_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE1_MIF0] = mmDCORE1_MIF0_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE1_RTR1] = mmDCORE1_RTR1_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE1_MIF1] = mmDCORE1_MIF1_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE1_RTR2] = mmDCORE1_RTR2_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE1_MIF2] = mmDCORE1_MIF2_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE1_RTR3] = mmDCORE1_RTR3_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE1_MIF3] = mmDCORE1_MIF3_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE1_RTR4] = mmDCORE1_RTR4_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE1_RTR5] = mmDCORE1_RTR5_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE1_RTR6] = mmDCORE1_RTR6_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE1_RTR7] = mmDCORE1_RTR7_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE2_XFT] = mmDCORE2_XFT_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE2_TFT0] = mmDCORE2_TFT0_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE2_TFT1] = mmDCORE2_TFT1_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE2_TFT2] = mmDCORE2_TFT2_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE2_RTR0] = mmDCORE2_RTR0_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE2_RTR1] = mmDCORE2_RTR1_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE2_RTR2] = mmDCORE2_RTR2_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE2_RTR3] = mmDCORE2_RTR3_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE2_RTR4] = mmDCORE2_RTR4_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE2_MIF0] = mmDCORE2_MIF0_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE2_RTR5] = mmDCORE2_RTR5_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE2_MIF1] = mmDCORE2_MIF1_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE2_RTR6] = mmDCORE2_RTR6_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE2_MIF2] = mmDCORE2_MIF2_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE2_RTR7] = mmDCORE2_RTR7_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE2_MIF3] = mmDCORE2_MIF3_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE3_XFT] = mmDCORE3_XFT_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE3_TFT0] = mmDCORE3_TFT0_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE3_TFT1] = mmDCORE3_TFT1_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE3_TFT2] = mmDCORE3_TFT2_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE3_RTR0] = mmDCORE3_RTR0_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE3_MIF0] = mmDCORE3_MIF0_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE3_RTR1] = mmDCORE3_RTR1_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE3_MIF1] = mmDCORE3_MIF1_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE3_RTR2] = mmDCORE3_RTR2_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE3_MIF2] = mmDCORE3_MIF2_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE3_RTR3] = mmDCORE3_RTR3_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE3_MIF3] = mmDCORE3_MIF3_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE3_RTR4] = mmDCORE3_RTR4_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE3_RTR5] = mmDCORE3_RTR5_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE3_RTR6] = mmDCORE3_RTR6_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE3_RTR7] = mmDCORE3_RTR7_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_PSOC] = mmPSOC_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_PSOC_ARC0] = 0,
+	[GAUDI2_FUNNEL_PSOC_ARC1] = 0,
+	[GAUDI2_FUNNEL_XDMA] = mmXDMA_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_CPU] = mmCPU_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_PMMU] = mmPMMU_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_PMMU_DEC] = mmPMMU_FUNNEL_DEC_BASE,
+	[GAUDI2_FUNNEL_DCORE0_XBAR_MID] = mmDCORE0_XBAR_MID_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE0_XBAR_EDGE] = mmDCORE0_XBAR_EDGE_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE1_XBAR_MID] = mmDCORE1_XBAR_MID_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE1_XBAR_EDGE] = mmDCORE1_XBAR_EDGE_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE2_XBAR_MID] = mmDCORE2_XBAR_MID_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE2_XBAR_EDGE] = mmDCORE2_XBAR_EDGE_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE3_XBAR_MID] = mmDCORE3_XBAR_MID_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_DCORE3_XBAR_EDGE] = mmDCORE3_XBAR_EDGE_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_ARC_FARM] = mmARC_FARM_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_HBM0_MC0] = mmHBM0_MC0_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_HBM0_MC1] = mmHBM0_MC1_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_HBM1_MC0] = mmHBM1_MC0_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_HBM1_MC1] = mmHBM1_MC1_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_HBM2_MC0] = mmHBM2_MC0_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_HBM2_MC1] = mmHBM2_MC1_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_HBM3_MC0] = mmHBM3_MC0_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_HBM3_MC1] = mmHBM3_MC1_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_HBM4_MC0] = mmHBM4_MC0_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_HBM4_MC1] = mmHBM4_MC1_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_HBM5_MC0] = mmHBM5_MC0_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_HBM5_MC1] = mmHBM5_MC1_FUNNEL_BASE,
+	[GAUDI2_FUNNEL_NIC0_DBG_TX] = mmNIC0_DBG_FUNNEL_TX_BASE,
+	[GAUDI2_FUNNEL_NIC0_DBG_NCH] = mmNIC0_DBG_FUNNEL_NCH_BASE,
+	[GAUDI2_FUNNEL_NIC1_DBG_TX] = mmNIC1_DBG_FUNNEL_TX_BASE,
+	[GAUDI2_FUNNEL_NIC1_DBG_NCH] = mmNIC1_DBG_FUNNEL_NCH_BASE,
+	[GAUDI2_FUNNEL_NIC2_DBG_TX] = mmNIC2_DBG_FUNNEL_TX_BASE,
+	[GAUDI2_FUNNEL_NIC2_DBG_NCH] = mmNIC2_DBG_FUNNEL_NCH_BASE,
+	[GAUDI2_FUNNEL_NIC3_DBG_TX] = mmNIC3_DBG_FUNNEL_TX_BASE,
+	[GAUDI2_FUNNEL_NIC3_DBG_NCH] = mmNIC3_DBG_FUNNEL_NCH_BASE,
+	[GAUDI2_FUNNEL_NIC4_DBG_TX] = mmNIC4_DBG_FUNNEL_TX_BASE,
+	[GAUDI2_FUNNEL_NIC4_DBG_NCH] = mmNIC4_DBG_FUNNEL_NCH_BASE,
+	[GAUDI2_FUNNEL_NIC5_DBG_TX] = mmNIC5_DBG_FUNNEL_TX_BASE,
+	[GAUDI2_FUNNEL_NIC5_DBG_NCH] = mmNIC5_DBG_FUNNEL_NCH_BASE,
+	[GAUDI2_FUNNEL_NIC6_DBG_TX] = mmNIC6_DBG_FUNNEL_TX_BASE,
+	[GAUDI2_FUNNEL_NIC6_DBG_NCH] = mmNIC6_DBG_FUNNEL_NCH_BASE,
+	[GAUDI2_FUNNEL_NIC7_DBG_TX] = mmNIC7_DBG_FUNNEL_TX_BASE,
+	[GAUDI2_FUNNEL_NIC7_DBG_NCH] = mmNIC7_DBG_FUNNEL_NCH_BASE,
+	[GAUDI2_FUNNEL_NIC8_DBG_TX] = mmNIC8_DBG_FUNNEL_TX_BASE,
+	[GAUDI2_FUNNEL_NIC8_DBG_NCH] = mmNIC8_DBG_FUNNEL_NCH_BASE,
+	[GAUDI2_FUNNEL_NIC9_DBG_TX] = mmNIC9_DBG_FUNNEL_TX_BASE,
+	[GAUDI2_FUNNEL_NIC9_DBG_NCH] = mmNIC9_DBG_FUNNEL_NCH_BASE,
+	[GAUDI2_FUNNEL_NIC10_DBG_TX] = mmNIC10_DBG_FUNNEL_TX_BASE,
+	[GAUDI2_FUNNEL_NIC10_DBG_NCH] = mmNIC10_DBG_FUNNEL_NCH_BASE,
+	[GAUDI2_FUNNEL_NIC11_DBG_TX] = mmNIC11_DBG_FUNNEL_TX_BASE,
+	[GAUDI2_FUNNEL_NIC11_DBG_NCH] = mmNIC11_DBG_FUNNEL_NCH_BASE
+};
+
+static u64 debug_bmon_regs[GAUDI2_BMON_LAST + 1] = {
+	[GAUDI2_BMON_DCORE0_TPC0_EML_0] = mmDCORE0_TPC0_EML_BUSMON_0_BASE,
+	[GAUDI2_BMON_DCORE0_TPC0_EML_1] = mmDCORE0_TPC0_EML_BUSMON_1_BASE,
+	[GAUDI2_BMON_DCORE0_TPC0_EML_2] = mmDCORE0_TPC0_EML_BUSMON_2_BASE,
+	[GAUDI2_BMON_DCORE0_TPC0_EML_3] = mmDCORE0_TPC0_EML_BUSMON_3_BASE,
+	[GAUDI2_BMON_DCORE0_TPC1_EML_0] = mmDCORE0_TPC1_EML_BUSMON_0_BASE,
+	[GAUDI2_BMON_DCORE0_TPC1_EML_1] = mmDCORE0_TPC1_EML_BUSMON_1_BASE,
+	[GAUDI2_BMON_DCORE0_TPC1_EML_2] = mmDCORE0_TPC1_EML_BUSMON_2_BASE,
+	[GAUDI2_BMON_DCORE0_TPC1_EML_3] = mmDCORE0_TPC1_EML_BUSMON_3_BASE,
+	[GAUDI2_BMON_DCORE0_TPC2_EML_0] = mmDCORE0_TPC2_EML_BUSMON_0_BASE,
+	[GAUDI2_BMON_DCORE0_TPC2_EML_1] = mmDCORE0_TPC2_EML_BUSMON_1_BASE,
+	[GAUDI2_BMON_DCORE0_TPC2_EML_2] = mmDCORE0_TPC2_EML_BUSMON_2_BASE,
+	[GAUDI2_BMON_DCORE0_TPC2_EML_3] = mmDCORE0_TPC2_EML_BUSMON_3_BASE,
+	[GAUDI2_BMON_DCORE0_TPC3_EML_0] = mmDCORE0_TPC3_EML_BUSMON_0_BASE,
+	[GAUDI2_BMON_DCORE0_TPC3_EML_1] = mmDCORE0_TPC3_EML_BUSMON_1_BASE,
+	[GAUDI2_BMON_DCORE0_TPC3_EML_2] = mmDCORE0_TPC3_EML_BUSMON_2_BASE,
+	[GAUDI2_BMON_DCORE0_TPC3_EML_3] = mmDCORE0_TPC3_EML_BUSMON_3_BASE,
+	[GAUDI2_BMON_DCORE0_TPC4_EML_0] = mmDCORE0_TPC4_EML_BUSMON_0_BASE,
+	[GAUDI2_BMON_DCORE0_TPC4_EML_1] = mmDCORE0_TPC4_EML_BUSMON_1_BASE,
+	[GAUDI2_BMON_DCORE0_TPC4_EML_2] = mmDCORE0_TPC4_EML_BUSMON_2_BASE,
+	[GAUDI2_BMON_DCORE0_TPC4_EML_3] = mmDCORE0_TPC4_EML_BUSMON_3_BASE,
+	[GAUDI2_BMON_DCORE0_TPC5_EML_0] = mmDCORE0_TPC5_EML_BUSMON_0_BASE,
+	[GAUDI2_BMON_DCORE0_TPC5_EML_1] = mmDCORE0_TPC5_EML_BUSMON_1_BASE,
+	[GAUDI2_BMON_DCORE0_TPC5_EML_2] = mmDCORE0_TPC5_EML_BUSMON_2_BASE,
+	[GAUDI2_BMON_DCORE0_TPC5_EML_3] = mmDCORE0_TPC5_EML_BUSMON_3_BASE,
+	[GAUDI2_BMON_DCORE0_TPC6_EML_0] = mmDCORE0_TPC6_EML_BUSMON_0_BASE,
+	[GAUDI2_BMON_DCORE0_TPC6_EML_1] = mmDCORE0_TPC6_EML_BUSMON_1_BASE,
+	[GAUDI2_BMON_DCORE0_TPC6_EML_2] = mmDCORE0_TPC6_EML_BUSMON_2_BASE,
+	[GAUDI2_BMON_DCORE0_TPC6_EML_3] = mmDCORE0_TPC6_EML_BUSMON_3_BASE,
+	[GAUDI2_BMON_DCORE1_TPC0_EML_0] = mmDCORE1_TPC0_EML_BUSMON_0_BASE,
+	[GAUDI2_BMON_DCORE1_TPC0_EML_1] = mmDCORE1_TPC0_EML_BUSMON_1_BASE,
+	[GAUDI2_BMON_DCORE1_TPC0_EML_2] = mmDCORE1_TPC0_EML_BUSMON_2_BASE,
+	[GAUDI2_BMON_DCORE1_TPC0_EML_3] = mmDCORE1_TPC0_EML_BUSMON_3_BASE,
+	[GAUDI2_BMON_DCORE1_TPC1_EML_0] = mmDCORE1_TPC1_EML_BUSMON_0_BASE,
+	[GAUDI2_BMON_DCORE1_TPC1_EML_1] = mmDCORE1_TPC1_EML_BUSMON_1_BASE,
+	[GAUDI2_BMON_DCORE1_TPC1_EML_2] = mmDCORE1_TPC1_EML_BUSMON_2_BASE,
+	[GAUDI2_BMON_DCORE1_TPC1_EML_3] = mmDCORE1_TPC1_EML_BUSMON_3_BASE,
+	[GAUDI2_BMON_DCORE1_TPC2_EML_0] = mmDCORE1_TPC2_EML_BUSMON_0_BASE,
+	[GAUDI2_BMON_DCORE1_TPC2_EML_1] = mmDCORE1_TPC2_EML_BUSMON_1_BASE,
+	[GAUDI2_BMON_DCORE1_TPC2_EML_2] = mmDCORE1_TPC2_EML_BUSMON_2_BASE,
+	[GAUDI2_BMON_DCORE1_TPC2_EML_3] = mmDCORE1_TPC2_EML_BUSMON_3_BASE,
+	[GAUDI2_BMON_DCORE1_TPC3_EML_0] = mmDCORE1_TPC3_EML_BUSMON_0_BASE,
+	[GAUDI2_BMON_DCORE1_TPC3_EML_1] = mmDCORE1_TPC3_EML_BUSMON_1_BASE,
+	[GAUDI2_BMON_DCORE1_TPC3_EML_2] = mmDCORE1_TPC3_EML_BUSMON_2_BASE,
+	[GAUDI2_BMON_DCORE1_TPC3_EML_3] = mmDCORE1_TPC3_EML_BUSMON_3_BASE,
+	[GAUDI2_BMON_DCORE1_TPC4_EML_0] = mmDCORE1_TPC4_EML_BUSMON_0_BASE,
+	[GAUDI2_BMON_DCORE1_TPC4_EML_1] = mmDCORE1_TPC4_EML_BUSMON_1_BASE,
+	[GAUDI2_BMON_DCORE1_TPC4_EML_2] = mmDCORE1_TPC4_EML_BUSMON_2_BASE,
+	[GAUDI2_BMON_DCORE1_TPC4_EML_3] = mmDCORE1_TPC4_EML_BUSMON_3_BASE,
+	[GAUDI2_BMON_DCORE1_TPC5_EML_0] = mmDCORE1_TPC5_EML_BUSMON_0_BASE,
+	[GAUDI2_BMON_DCORE1_TPC5_EML_1] = mmDCORE1_TPC5_EML_BUSMON_1_BASE,
+	[GAUDI2_BMON_DCORE1_TPC5_EML_2] = mmDCORE1_TPC5_EML_BUSMON_2_BASE,
+	[GAUDI2_BMON_DCORE1_TPC5_EML_3] = mmDCORE1_TPC5_EML_BUSMON_3_BASE,
+	[GAUDI2_BMON_DCORE2_TPC0_EML_0] = mmDCORE2_TPC0_EML_BUSMON_0_BASE,
+	[GAUDI2_BMON_DCORE2_TPC0_EML_1] = mmDCORE2_TPC0_EML_BUSMON_1_BASE,
+	[GAUDI2_BMON_DCORE2_TPC0_EML_2] = mmDCORE2_TPC0_EML_BUSMON_2_BASE,
+	[GAUDI2_BMON_DCORE2_TPC0_EML_3] = mmDCORE2_TPC0_EML_BUSMON_3_BASE,
+	[GAUDI2_BMON_DCORE2_TPC1_EML_0] = mmDCORE2_TPC1_EML_BUSMON_0_BASE,
+	[GAUDI2_BMON_DCORE2_TPC1_EML_1] = mmDCORE2_TPC1_EML_BUSMON_1_BASE,
+	[GAUDI2_BMON_DCORE2_TPC1_EML_2] = mmDCORE2_TPC1_EML_BUSMON_2_BASE,
+	[GAUDI2_BMON_DCORE2_TPC1_EML_3] = mmDCORE2_TPC1_EML_BUSMON_3_BASE,
+	[GAUDI2_BMON_DCORE2_TPC2_EML_0] = mmDCORE2_TPC2_EML_BUSMON_0_BASE,
+	[GAUDI2_BMON_DCORE2_TPC2_EML_1] = mmDCORE2_TPC2_EML_BUSMON_1_BASE,
+	[GAUDI2_BMON_DCORE2_TPC2_EML_2] = mmDCORE2_TPC2_EML_BUSMON_2_BASE,
+	[GAUDI2_BMON_DCORE2_TPC2_EML_3] = mmDCORE2_TPC2_EML_BUSMON_3_BASE,
+	[GAUDI2_BMON_DCORE2_TPC3_EML_0] = mmDCORE2_TPC3_EML_BUSMON_0_BASE,
+	[GAUDI2_BMON_DCORE2_TPC3_EML_1] = mmDCORE2_TPC3_EML_BUSMON_1_BASE,
+	[GAUDI2_BMON_DCORE2_TPC3_EML_2] = mmDCORE2_TPC3_EML_BUSMON_2_BASE,
+	[GAUDI2_BMON_DCORE2_TPC3_EML_3] = mmDCORE2_TPC3_EML_BUSMON_3_BASE,
+	[GAUDI2_BMON_DCORE2_TPC4_EML_0] = mmDCORE2_TPC4_EML_BUSMON_0_BASE,
+	[GAUDI2_BMON_DCORE2_TPC4_EML_1] = mmDCORE2_TPC4_EML_BUSMON_1_BASE,
+	[GAUDI2_BMON_DCORE2_TPC4_EML_2] = mmDCORE2_TPC4_EML_BUSMON_2_BASE,
+	[GAUDI2_BMON_DCORE2_TPC4_EML_3] = mmDCORE2_TPC4_EML_BUSMON_3_BASE,
+	[GAUDI2_BMON_DCORE2_TPC5_EML_0] = mmDCORE2_TPC5_EML_BUSMON_0_BASE,
+	[GAUDI2_BMON_DCORE2_TPC5_EML_1] = mmDCORE2_TPC5_EML_BUSMON_1_BASE,
+	[GAUDI2_BMON_DCORE2_TPC5_EML_2] = mmDCORE2_TPC5_EML_BUSMON_2_BASE,
+	[GAUDI2_BMON_DCORE2_TPC5_EML_3] = mmDCORE2_TPC5_EML_BUSMON_3_BASE,
+	[GAUDI2_BMON_DCORE3_TPC0_EML_0] = mmDCORE3_TPC0_EML_BUSMON_0_BASE,
+	[GAUDI2_BMON_DCORE3_TPC0_EML_1] = mmDCORE3_TPC0_EML_BUSMON_1_BASE,
+	[GAUDI2_BMON_DCORE3_TPC0_EML_2] = mmDCORE3_TPC0_EML_BUSMON_2_BASE,
+	[GAUDI2_BMON_DCORE3_TPC0_EML_3] = mmDCORE3_TPC0_EML_BUSMON_3_BASE,
+	[GAUDI2_BMON_DCORE3_TPC1_EML_0] = mmDCORE3_TPC1_EML_BUSMON_0_BASE,
+	[GAUDI2_BMON_DCORE3_TPC1_EML_1] = mmDCORE3_TPC1_EML_BUSMON_1_BASE,
+	[GAUDI2_BMON_DCORE3_TPC1_EML_2] = mmDCORE3_TPC1_EML_BUSMON_2_BASE,
+	[GAUDI2_BMON_DCORE3_TPC1_EML_3] = mmDCORE3_TPC1_EML_BUSMON_3_BASE,
+	[GAUDI2_BMON_DCORE3_TPC2_EML_0] = mmDCORE3_TPC2_EML_BUSMON_0_BASE,
+	[GAUDI2_BMON_DCORE3_TPC2_EML_1] = mmDCORE3_TPC2_EML_BUSMON_1_BASE,
+	[GAUDI2_BMON_DCORE3_TPC2_EML_2] = mmDCORE3_TPC2_EML_BUSMON_2_BASE,
+	[GAUDI2_BMON_DCORE3_TPC2_EML_3] = mmDCORE3_TPC2_EML_BUSMON_3_BASE,
+	[GAUDI2_BMON_DCORE3_TPC3_EML_0] = mmDCORE3_TPC3_EML_BUSMON_0_BASE,
+	[GAUDI2_BMON_DCORE3_TPC3_EML_1] = mmDCORE3_TPC3_EML_BUSMON_1_BASE,
+	[GAUDI2_BMON_DCORE3_TPC3_EML_2] = mmDCORE3_TPC3_EML_BUSMON_2_BASE,
+	[GAUDI2_BMON_DCORE3_TPC3_EML_3] = mmDCORE3_TPC3_EML_BUSMON_3_BASE,
+	[GAUDI2_BMON_DCORE3_TPC4_EML_0] = mmDCORE3_TPC4_EML_BUSMON_0_BASE,
+	[GAUDI2_BMON_DCORE3_TPC4_EML_1] = mmDCORE3_TPC4_EML_BUSMON_1_BASE,
+	[GAUDI2_BMON_DCORE3_TPC4_EML_2] = mmDCORE3_TPC4_EML_BUSMON_2_BASE,
+	[GAUDI2_BMON_DCORE3_TPC4_EML_3] = mmDCORE3_TPC4_EML_BUSMON_3_BASE,
+	[GAUDI2_BMON_DCORE3_TPC5_EML_0] = mmDCORE3_TPC5_EML_BUSMON_0_BASE,
+	[GAUDI2_BMON_DCORE3_TPC5_EML_1] = mmDCORE3_TPC5_EML_BUSMON_1_BASE,
+	[GAUDI2_BMON_DCORE3_TPC5_EML_2] = mmDCORE3_TPC5_EML_BUSMON_2_BASE,
+	[GAUDI2_BMON_DCORE3_TPC5_EML_3] = mmDCORE3_TPC5_EML_BUSMON_3_BASE,
+	[GAUDI2_BMON_DCORE0_HMMU0_0] = mmDCORE0_HMMU0_BMON_0_BASE,
+	[GAUDI2_BMON_DCORE0_HMMU0_1] = mmDCORE0_HMMU0_BMON_1_BASE,
+	[GAUDI2_BMON_DCORE0_HMMU0_3] = mmDCORE0_HMMU0_BMON_3_BASE,
+	[GAUDI2_BMON_DCORE0_HMMU0_2] = mmDCORE0_HMMU0_BMON_2_BASE,
+	[GAUDI2_BMON_DCORE0_HMMU0_4] = mmDCORE0_HMMU0_BMON_4_BASE,
+	[GAUDI2_BMON_DCORE0_HMMU1_0] = mmDCORE0_HMMU1_BMON_0_BASE,
+	[GAUDI2_BMON_DCORE0_HMMU1_1] = mmDCORE0_HMMU1_BMON_1_BASE,
+	[GAUDI2_BMON_DCORE0_HMMU1_3] = mmDCORE0_HMMU1_BMON_3_BASE,
+	[GAUDI2_BMON_DCORE0_HMMU1_2] = mmDCORE0_HMMU1_BMON_2_BASE,
+	[GAUDI2_BMON_DCORE0_HMMU1_4] = mmDCORE0_HMMU1_BMON_4_BASE,
+	[GAUDI2_BMON_DCORE0_HMMU2_0] = mmDCORE0_HMMU2_BMON_0_BASE,
+	[GAUDI2_BMON_DCORE0_HMMU2_1] = mmDCORE0_HMMU2_BMON_1_BASE,
+	[GAUDI2_BMON_DCORE0_HMMU2_3] = mmDCORE0_HMMU2_BMON_3_BASE,
+	[GAUDI2_BMON_DCORE0_HMMU2_2] = mmDCORE0_HMMU2_BMON_2_BASE,
+	[GAUDI2_BMON_DCORE0_HMMU2_4] = mmDCORE0_HMMU2_BMON_4_BASE,
+	[GAUDI2_BMON_DCORE0_HMMU3_0] = mmDCORE0_HMMU3_BMON_0_BASE,
+	[GAUDI2_BMON_DCORE0_HMMU3_1] = mmDCORE0_HMMU3_BMON_1_BASE,
+	[GAUDI2_BMON_DCORE0_HMMU3_3] = mmDCORE0_HMMU3_BMON_3_BASE,
+	[GAUDI2_BMON_DCORE0_HMMU3_2] = mmDCORE0_HMMU3_BMON_2_BASE,
+	[GAUDI2_BMON_DCORE0_HMMU3_4] = mmDCORE0_HMMU3_BMON_4_BASE,
+	[GAUDI2_BMON_DCORE0_MME_CTRL_0] = mmDCORE0_MME_CTRL_BMON0_BASE,
+	[GAUDI2_BMON_DCORE0_MME_CTRL_1] = mmDCORE0_MME_CTRL_BMON1_BASE,
+	[GAUDI2_BMON_DCORE0_MME_CTRL_2] = mmDCORE0_MME_CTRL_BMON2_BASE,
+	[GAUDI2_BMON_DCORE0_MME_CTRL_3] = mmDCORE0_MME_CTRL_BMON3_BASE,
+	[GAUDI2_BMON_DCORE0_MME_SBTE0_0] = mmDCORE0_MME_SBTE0_BMON0_BASE,
+	[GAUDI2_BMON_DCORE0_MME_SBTE1_0] = mmDCORE0_MME_SBTE1_BMON0_BASE,
+	[GAUDI2_BMON_DCORE0_MME_SBTE2_0] = mmDCORE0_MME_SBTE2_BMON0_BASE,
+	[GAUDI2_BMON_DCORE0_MME_SBTE3_0] = mmDCORE0_MME_SBTE3_BMON0_BASE,
+	[GAUDI2_BMON_DCORE0_MME_SBTE4_0] = mmDCORE0_MME_SBTE4_BMON0_BASE,
+	[GAUDI2_BMON_DCORE0_MME_ACC_0] = mmDCORE0_MME_ACC_BMON0_BASE,
+	[GAUDI2_BMON_DCORE0_MME_ACC_1] = mmDCORE0_MME_ACC_BMON1_BASE,
+	[GAUDI2_BMON_DCORE0_SM] = mmDCORE0_SM_BMON_BASE,
+	[GAUDI2_BMON_DCORE0_SM_1] = mmDCORE0_SM_BMON1_BASE,
+	[GAUDI2_BMON_DCORE0_EDMA0_0] = mmDCORE0_EDMA0_BMON_0_BASE,
+	[GAUDI2_BMON_DCORE0_EDMA0_1] = mmDCORE0_EDMA0_BMON_1_BASE,
+	[GAUDI2_BMON_DCORE0_EDMA1_0] = mmDCORE0_EDMA1_BMON_0_BASE,
+	[GAUDI2_BMON_DCORE0_EDMA1_1] = mmDCORE0_EDMA1_BMON_1_BASE,
+	[GAUDI2_BMON_DCORE0_VDEC0_0] = mmDCORE0_VDEC0_BMON_0_BASE,
+	[GAUDI2_BMON_DCORE0_VDEC0_1] = mmDCORE0_VDEC0_BMON_1_BASE,
+	[GAUDI2_BMON_DCORE0_VDEC0_2] = mmDCORE0_VDEC0_BMON_2_BASE,
+	[GAUDI2_BMON_DCORE0_VDEC1_0] = mmDCORE0_VDEC1_BMON_0_BASE,
+	[GAUDI2_BMON_DCORE0_VDEC1_1] = mmDCORE0_VDEC1_BMON_1_BASE,
+	[GAUDI2_BMON_DCORE0_VDEC1_2] = mmDCORE0_VDEC1_BMON_2_BASE,
+	[GAUDI2_BMON_DCORE1_HMMU0_0] = mmDCORE1_HMMU0_BMON_0_BASE,
+	[GAUDI2_BMON_DCORE1_HMMU0_1] = mmDCORE1_HMMU0_BMON_1_BASE,
+	[GAUDI2_BMON_DCORE1_HMMU0_3] = mmDCORE1_HMMU0_BMON_3_BASE,
+	[GAUDI2_BMON_DCORE1_HMMU0_2] = mmDCORE1_HMMU0_BMON_2_BASE,
+	[GAUDI2_BMON_DCORE1_HMMU0_4] = mmDCORE1_HMMU0_BMON_4_BASE,
+	[GAUDI2_BMON_DCORE1_HMMU1_0] = mmDCORE1_HMMU1_BMON_0_BASE,
+	[GAUDI2_BMON_DCORE1_HMMU1_1] = mmDCORE1_HMMU1_BMON_1_BASE,
+	[GAUDI2_BMON_DCORE1_HMMU1_3] = mmDCORE1_HMMU1_BMON_3_BASE,
+	[GAUDI2_BMON_DCORE1_HMMU1_2] = mmDCORE1_HMMU1_BMON_2_BASE,
+	[GAUDI2_BMON_DCORE1_HMMU1_4] = mmDCORE1_HMMU1_BMON_4_BASE,
+	[GAUDI2_BMON_DCORE1_HMMU2_0] = mmDCORE1_HMMU2_BMON_0_BASE,
+	[GAUDI2_BMON_DCORE1_HMMU2_1] = mmDCORE1_HMMU2_BMON_1_BASE,
+	[GAUDI2_BMON_DCORE1_HMMU2_3] = mmDCORE1_HMMU2_BMON_3_BASE,
+	[GAUDI2_BMON_DCORE1_HMMU2_2] = mmDCORE1_HMMU2_BMON_2_BASE,
+	[GAUDI2_BMON_DCORE1_HMMU2_4] = mmDCORE1_HMMU2_BMON_4_BASE,
+	[GAUDI2_BMON_DCORE1_HMMU3_0] = mmDCORE1_HMMU3_BMON_0_BASE,
+	[GAUDI2_BMON_DCORE1_HMMU3_1] = mmDCORE1_HMMU3_BMON_1_BASE,
+	[GAUDI2_BMON_DCORE1_HMMU3_3] = mmDCORE1_HMMU3_BMON_3_BASE,
+	[GAUDI2_BMON_DCORE1_HMMU3_2] = mmDCORE1_HMMU3_BMON_2_BASE,
+	[GAUDI2_BMON_DCORE1_HMMU3_4] = mmDCORE1_HMMU3_BMON_4_BASE,
+	[GAUDI2_BMON_DCORE1_MME_CTRL_0] = mmDCORE1_MME_CTRL_BMON0_BASE,
+	[GAUDI2_BMON_DCORE1_MME_CTRL_1] = mmDCORE1_MME_CTRL_BMON1_BASE,
+	[GAUDI2_BMON_DCORE1_MME_CTRL_2] = mmDCORE1_MME_CTRL_BMON2_BASE,
+	[GAUDI2_BMON_DCORE1_MME_CTRL_3] = mmDCORE1_MME_CTRL_BMON3_BASE,
+	[GAUDI2_BMON_DCORE1_MME_SBTE0_0] = mmDCORE1_MME_SBTE0_BMON0_BASE,
+	[GAUDI2_BMON_DCORE1_MME_SBTE1_0] = mmDCORE1_MME_SBTE1_BMON0_BASE,
+	[GAUDI2_BMON_DCORE1_MME_SBTE2_0] = mmDCORE1_MME_SBTE2_BMON0_BASE,
+	[GAUDI2_BMON_DCORE1_MME_SBTE3_0] = mmDCORE1_MME_SBTE3_BMON0_BASE,
+	[GAUDI2_BMON_DCORE1_MME_SBTE4_0] = mmDCORE1_MME_SBTE4_BMON0_BASE,
+	[GAUDI2_BMON_DCORE1_MME_ACC_0] = mmDCORE1_MME_ACC_BMON0_BASE,
+	[GAUDI2_BMON_DCORE1_MME_ACC_1] = mmDCORE1_MME_ACC_BMON1_BASE,
+	[GAUDI2_BMON_DCORE1_SM] = mmDCORE1_SM_BMON_BASE,
+	[GAUDI2_BMON_DCORE1_SM_1] = mmDCORE1_SM_BMON1_BASE,
+	[GAUDI2_BMON_DCORE1_EDMA0_0] = mmDCORE1_EDMA0_BMON_0_BASE,
+	[GAUDI2_BMON_DCORE1_EDMA0_1] = mmDCORE1_EDMA0_BMON_1_BASE,
+	[GAUDI2_BMON_DCORE1_EDMA1_0] = mmDCORE1_EDMA1_BMON_0_BASE,
+	[GAUDI2_BMON_DCORE1_EDMA1_1] = mmDCORE1_EDMA1_BMON_1_BASE,
+	[GAUDI2_BMON_DCORE1_VDEC0_0] = mmDCORE1_VDEC0_BMON_0_BASE,
+	[GAUDI2_BMON_DCORE1_VDEC0_1] = mmDCORE1_VDEC0_BMON_1_BASE,
+	[GAUDI2_BMON_DCORE1_VDEC0_2] = mmDCORE1_VDEC0_BMON_2_BASE,
+	[GAUDI2_BMON_DCORE1_VDEC1_0] = mmDCORE1_VDEC1_BMON_0_BASE,
+	[GAUDI2_BMON_DCORE1_VDEC1_1] = mmDCORE1_VDEC1_BMON_1_BASE,
+	[GAUDI2_BMON_DCORE1_VDEC1_2] = mmDCORE1_VDEC1_BMON_2_BASE,
+	[GAUDI2_BMON_DCORE2_HMMU0_0] = mmDCORE2_HMMU0_BMON_0_BASE,
+	[GAUDI2_BMON_DCORE2_HMMU0_1] = mmDCORE2_HMMU0_BMON_1_BASE,
+	[GAUDI2_BMON_DCORE2_HMMU0_3] = mmDCORE2_HMMU0_BMON_3_BASE,
+	[GAUDI2_BMON_DCORE2_HMMU0_2] = mmDCORE2_HMMU0_BMON_2_BASE,
+	[GAUDI2_BMON_DCORE2_HMMU0_4] = mmDCORE2_HMMU0_BMON_4_BASE,
+	[GAUDI2_BMON_DCORE2_HMMU1_0] = mmDCORE2_HMMU1_BMON_0_BASE,
+	[GAUDI2_BMON_DCORE2_HMMU1_1] = mmDCORE2_HMMU1_BMON_1_BASE,
+	[GAUDI2_BMON_DCORE2_HMMU1_3] = mmDCORE2_HMMU1_BMON_3_BASE,
+	[GAUDI2_BMON_DCORE2_HMMU1_2] = mmDCORE2_HMMU1_BMON_2_BASE,
+	[GAUDI2_BMON_DCORE2_HMMU1_4] = mmDCORE2_HMMU1_BMON_4_BASE,
+	[GAUDI2_BMON_DCORE2_HMMU2_0] = mmDCORE2_HMMU2_BMON_0_BASE,
+	[GAUDI2_BMON_DCORE2_HMMU2_1] = mmDCORE2_HMMU2_BMON_1_BASE,
+	[GAUDI2_BMON_DCORE2_HMMU2_3] = mmDCORE2_HMMU2_BMON_3_BASE,
+	[GAUDI2_BMON_DCORE2_HMMU2_2] = mmDCORE2_HMMU2_BMON_2_BASE,
+	[GAUDI2_BMON_DCORE2_HMMU2_4] = mmDCORE2_HMMU2_BMON_4_BASE,
+	[GAUDI2_BMON_DCORE2_HMMU3_0] = mmDCORE2_HMMU3_BMON_0_BASE,
+	[GAUDI2_BMON_DCORE2_HMMU3_1] = mmDCORE2_HMMU3_BMON_1_BASE,
+	[GAUDI2_BMON_DCORE2_HMMU3_3] = mmDCORE2_HMMU3_BMON_3_BASE,
+	[GAUDI2_BMON_DCORE2_HMMU3_2] = mmDCORE2_HMMU3_BMON_2_BASE,
+	[GAUDI2_BMON_DCORE2_HMMU3_4] = mmDCORE2_HMMU3_BMON_4_BASE,
+	[GAUDI2_BMON_DCORE2_MME_CTRL_0] = mmDCORE2_MME_CTRL_BMON0_BASE,
+	[GAUDI2_BMON_DCORE2_MME_CTRL_1] = mmDCORE2_MME_CTRL_BMON1_BASE,
+	[GAUDI2_BMON_DCORE2_MME_CTRL_2] = mmDCORE2_MME_CTRL_BMON2_BASE,
+	[GAUDI2_BMON_DCORE2_MME_CTRL_3] = mmDCORE2_MME_CTRL_BMON3_BASE,
+	[GAUDI2_BMON_DCORE2_MME_SBTE0_0] = mmDCORE2_MME_SBTE0_BMON0_BASE,
+	[GAUDI2_BMON_DCORE2_MME_SBTE1_0] = mmDCORE2_MME_SBTE1_BMON0_BASE,
+	[GAUDI2_BMON_DCORE2_MME_SBTE2_0] = mmDCORE2_MME_SBTE2_BMON0_BASE,
+	[GAUDI2_BMON_DCORE2_MME_SBTE3_0] = mmDCORE2_MME_SBTE3_BMON0_BASE,
+	[GAUDI2_BMON_DCORE2_MME_SBTE4_0] = mmDCORE2_MME_SBTE4_BMON0_BASE,
+	[GAUDI2_BMON_DCORE2_MME_ACC_0] = mmDCORE2_MME_ACC_BMON0_BASE,
+	[GAUDI2_BMON_DCORE2_MME_ACC_1] = mmDCORE2_MME_ACC_BMON1_BASE,
+	[GAUDI2_BMON_DCORE2_SM] = mmDCORE2_SM_BMON_BASE,
+	[GAUDI2_BMON_DCORE2_SM_1] = mmDCORE2_SM_BMON1_BASE,
+	[GAUDI2_BMON_DCORE2_EDMA0_0] = mmDCORE2_EDMA0_BMON_0_BASE,
+	[GAUDI2_BMON_DCORE2_EDMA0_1] = mmDCORE2_EDMA0_BMON_1_BASE,
+	[GAUDI2_BMON_DCORE2_EDMA1_0] = mmDCORE2_EDMA1_BMON_0_BASE,
+	[GAUDI2_BMON_DCORE2_EDMA1_1] = mmDCORE2_EDMA1_BMON_1_BASE,
+	[GAUDI2_BMON_DCORE2_VDEC0_0] = mmDCORE2_VDEC0_BMON_0_BASE,
+	[GAUDI2_BMON_DCORE2_VDEC0_1] = mmDCORE2_VDEC0_BMON_1_BASE,
+	[GAUDI2_BMON_DCORE2_VDEC0_2] = mmDCORE2_VDEC0_BMON_2_BASE,
+	[GAUDI2_BMON_DCORE2_VDEC1_0] = mmDCORE2_VDEC1_BMON_0_BASE,
+	[GAUDI2_BMON_DCORE2_VDEC1_1] = mmDCORE2_VDEC1_BMON_1_BASE,
+	[GAUDI2_BMON_DCORE2_VDEC1_2] = mmDCORE2_VDEC1_BMON_2_BASE,
+	[GAUDI2_BMON_DCORE3_HMMU0_0] = mmDCORE3_HMMU0_BMON_0_BASE,
+	[GAUDI2_BMON_DCORE3_HMMU0_1] = mmDCORE3_HMMU0_BMON_1_BASE,
+	[GAUDI2_BMON_DCORE3_HMMU0_3] = mmDCORE3_HMMU0_BMON_3_BASE,
+	[GAUDI2_BMON_DCORE3_HMMU0_2] = mmDCORE3_HMMU0_BMON_2_BASE,
+	[GAUDI2_BMON_DCORE3_HMMU0_4] = mmDCORE3_HMMU0_BMON_4_BASE,
+	[GAUDI2_BMON_DCORE3_HMMU1_0] = mmDCORE3_HMMU1_BMON_0_BASE,
+	[GAUDI2_BMON_DCORE3_HMMU1_1] = mmDCORE3_HMMU1_BMON_1_BASE,
+	[GAUDI2_BMON_DCORE3_HMMU1_3] = mmDCORE3_HMMU1_BMON_3_BASE,
+	[GAUDI2_BMON_DCORE3_HMMU1_2] = mmDCORE3_HMMU1_BMON_2_BASE,
+	[GAUDI2_BMON_DCORE3_HMMU1_4] = mmDCORE3_HMMU1_BMON_4_BASE,
+	[GAUDI2_BMON_DCORE3_HMMU2_0] = mmDCORE3_HMMU2_BMON_0_BASE,
+	[GAUDI2_BMON_DCORE3_HMMU2_1] = mmDCORE3_HMMU2_BMON_1_BASE,
+	[GAUDI2_BMON_DCORE3_HMMU2_3] = mmDCORE3_HMMU2_BMON_3_BASE,
+	[GAUDI2_BMON_DCORE3_HMMU2_2] = mmDCORE3_HMMU2_BMON_2_BASE,
+	[GAUDI2_BMON_DCORE3_HMMU2_4] = mmDCORE3_HMMU2_BMON_4_BASE,
+	[GAUDI2_BMON_DCORE3_HMMU3_0] = mmDCORE3_HMMU3_BMON_0_BASE,
+	[GAUDI2_BMON_DCORE3_HMMU3_1] = mmDCORE3_HMMU3_BMON_1_BASE,
+	[GAUDI2_BMON_DCORE3_HMMU3_3] = mmDCORE3_HMMU3_BMON_3_BASE,
+	[GAUDI2_BMON_DCORE3_HMMU3_2] = mmDCORE3_HMMU3_BMON_2_BASE,
+	[GAUDI2_BMON_DCORE3_HMMU3_4] = mmDCORE3_HMMU3_BMON_4_BASE,
+	[GAUDI2_BMON_DCORE3_MME_CTRL_0] = mmDCORE3_MME_CTRL_BMON0_BASE,
+	[GAUDI2_BMON_DCORE3_MME_CTRL_1] = mmDCORE3_MME_CTRL_BMON1_BASE,
+	[GAUDI2_BMON_DCORE3_MME_CTRL_2] = mmDCORE3_MME_CTRL_BMON2_BASE,
+	[GAUDI2_BMON_DCORE3_MME_CTRL_3] = mmDCORE3_MME_CTRL_BMON3_BASE,
+	[GAUDI2_BMON_DCORE3_MME_SBTE0_0] = mmDCORE3_MME_SBTE0_BMON0_BASE,
+	[GAUDI2_BMON_DCORE3_MME_SBTE1_0] = mmDCORE3_MME_SBTE1_BMON0_BASE,
+	[GAUDI2_BMON_DCORE3_MME_SBTE2_0] = mmDCORE3_MME_SBTE2_BMON0_BASE,
+	[GAUDI2_BMON_DCORE3_MME_SBTE3_0] = mmDCORE3_MME_SBTE3_BMON0_BASE,
+	[GAUDI2_BMON_DCORE3_MME_SBTE4_0] = mmDCORE3_MME_SBTE4_BMON0_BASE,
+	[GAUDI2_BMON_DCORE3_MME_ACC_0] = mmDCORE3_MME_ACC_BMON0_BASE,
+	[GAUDI2_BMON_DCORE3_MME_ACC_1] = mmDCORE3_MME_ACC_BMON1_BASE,
+	[GAUDI2_BMON_DCORE3_SM] = mmDCORE3_SM_BMON_BASE,
+	[GAUDI2_BMON_DCORE3_SM_1] = mmDCORE3_SM_BMON1_BASE,
+	[GAUDI2_BMON_DCORE3_EDMA0_0] = mmDCORE3_EDMA0_BMON_0_BASE,
+	[GAUDI2_BMON_DCORE3_EDMA0_1] = mmDCORE3_EDMA0_BMON_1_BASE,
+	[GAUDI2_BMON_DCORE3_EDMA1_0] = mmDCORE3_EDMA1_BMON_0_BASE,
+	[GAUDI2_BMON_DCORE3_EDMA1_1] = mmDCORE3_EDMA1_BMON_1_BASE,
+	[GAUDI2_BMON_DCORE3_VDEC0_0] = mmDCORE3_VDEC0_BMON_0_BASE,
+	[GAUDI2_BMON_DCORE3_VDEC0_1] = mmDCORE3_VDEC0_BMON_1_BASE,
+	[GAUDI2_BMON_DCORE3_VDEC0_2] = mmDCORE3_VDEC0_BMON_2_BASE,
+	[GAUDI2_BMON_DCORE3_VDEC1_0] = mmDCORE3_VDEC1_BMON_0_BASE,
+	[GAUDI2_BMON_DCORE3_VDEC1_1] = mmDCORE3_VDEC1_BMON_1_BASE,
+	[GAUDI2_BMON_DCORE3_VDEC1_2] = mmDCORE3_VDEC1_BMON_2_BASE,
+	[GAUDI2_BMON_PCIE_MSTR_WR] = mmPCIE_BMON_MSTR_WR_BASE,
+	[GAUDI2_BMON_PCIE_MSTR_RD] = mmPCIE_BMON_MSTR_RD_BASE,
+	[GAUDI2_BMON_PCIE_SLV_WR] = mmPCIE_BMON_SLV_WR_BASE,
+	[GAUDI2_BMON_PCIE_SLV_RD] = mmPCIE_BMON_SLV_RD_BASE,
+	[GAUDI2_BMON_PSOC_ARC0_0] = 0,
+	[GAUDI2_BMON_PSOC_ARC0_1] = 0,
+	[GAUDI2_BMON_PSOC_ARC1_0] = 0,
+	[GAUDI2_BMON_PSOC_ARC1_1] = 0,
+	[GAUDI2_BMON_PDMA0_0] = mmPDMA0_BMON_0_BASE,
+	[GAUDI2_BMON_PDMA0_1] = mmPDMA0_BMON_1_BASE,
+	[GAUDI2_BMON_PDMA1_0] = mmPDMA1_BMON_0_BASE,
+	[GAUDI2_BMON_PDMA1_1] = mmPDMA1_BMON_1_BASE,
+	[GAUDI2_BMON_CPU_WR] = mmCPU_WR_BMON_BASE,
+	[GAUDI2_BMON_CPU_RD] = mmCPU_RD_BMON_BASE,
+	[GAUDI2_BMON_PMMU_0] = mmPMMU_BMON_0_BASE,
+	[GAUDI2_BMON_PMMU_1] = mmPMMU_BMON_1_BASE,
+	[GAUDI2_BMON_PMMU_2] = mmPMMU_BMON_2_BASE,
+	[GAUDI2_BMON_PMMU_3] = mmPMMU_BMON_3_BASE,
+	[GAUDI2_BMON_PMMU_4] = mmPMMU_BMON_4_BASE,
+	[GAUDI2_BMON_ROT0_0] = mmROT0_BMON_0_BASE,
+	[GAUDI2_BMON_ROT0_1] = mmROT0_BMON_1_BASE,
+	[GAUDI2_BMON_ROT0_2] = mmROT0_BMON_2_BASE,
+	[GAUDI2_BMON_ROT0_3] = mmROT0_BMON_3_BASE,
+	[GAUDI2_BMON_ROT1_0] = mmROT1_BMON_0_BASE,
+	[GAUDI2_BMON_ROT1_1] = mmROT1_BMON_1_BASE,
+	[GAUDI2_BMON_ROT1_2] = mmROT1_BMON_2_BASE,
+	[GAUDI2_BMON_ROT1_3] = mmROT1_BMON_3_BASE,
+	[GAUDI2_BMON_ARC_FARM_0] = mmARC_FARM_BMON_0_BASE,
+	[GAUDI2_BMON_ARC_FARM_1] = mmARC_FARM_BMON_1_BASE,
+	[GAUDI2_BMON_ARC_FARM_2] = mmARC_FARM_BMON_2_BASE,
+	[GAUDI2_BMON_ARC_FARM_3] = mmARC_FARM_BMON_3_BASE,
+	[GAUDI2_BMON_KDMA_0] = mmKDMA_BMON_0_BASE,
+	[GAUDI2_BMON_KDMA_1] = mmKDMA_BMON_1_BASE,
+	[GAUDI2_BMON_KDMA_2] = mmKDMA_BMON_2_BASE,
+	[GAUDI2_BMON_KDMA_3] = mmKDMA_BMON_3_BASE,
+	[GAUDI2_BMON_PCIE_VDEC0_0] = mmPCIE_VDEC0_BMON_0_BASE,
+	[GAUDI2_BMON_PCIE_VDEC0_1] = mmPCIE_VDEC0_BMON_1_BASE,
+	[GAUDI2_BMON_PCIE_VDEC0_2] = mmPCIE_VDEC0_BMON_2_BASE,
+	[GAUDI2_BMON_PCIE_VDEC1_0] = mmPCIE_VDEC1_BMON_0_BASE,
+	[GAUDI2_BMON_PCIE_VDEC1_1] = mmPCIE_VDEC1_BMON_1_BASE,
+	[GAUDI2_BMON_PCIE_VDEC1_2] = mmPCIE_VDEC1_BMON_2_BASE,
+	[GAUDI2_BMON_NIC0_DBG_0_0] = mmNIC0_DBG_BMON0_0_BASE,
+	[GAUDI2_BMON_NIC0_DBG_1_0] = mmNIC0_DBG_BMON1_0_BASE,
+	[GAUDI2_BMON_NIC0_DBG_2_0] = mmNIC0_DBG_BMON2_0_BASE,
+	[GAUDI2_BMON_NIC0_DBG_0_1] = mmNIC0_DBG_BMON0_1_BASE,
+	[GAUDI2_BMON_NIC0_DBG_1_1] = mmNIC0_DBG_BMON1_1_BASE,
+	[GAUDI2_BMON_NIC0_DBG_2_1] = mmNIC0_DBG_BMON2_1_BASE,
+	[GAUDI2_BMON_NIC1_DBG_0_0] = mmNIC1_DBG_BMON0_0_BASE,
+	[GAUDI2_BMON_NIC1_DBG_1_0] = mmNIC1_DBG_BMON1_0_BASE,
+	[GAUDI2_BMON_NIC1_DBG_2_0] = mmNIC1_DBG_BMON2_0_BASE,
+	[GAUDI2_BMON_NIC1_DBG_0_1] = mmNIC1_DBG_BMON0_1_BASE,
+	[GAUDI2_BMON_NIC1_DBG_1_1] = mmNIC1_DBG_BMON1_1_BASE,
+	[GAUDI2_BMON_NIC1_DBG_2_1] = mmNIC1_DBG_BMON2_1_BASE,
+	[GAUDI2_BMON_NIC2_DBG_0_0] = mmNIC2_DBG_BMON0_0_BASE,
+	[GAUDI2_BMON_NIC2_DBG_1_0] = mmNIC2_DBG_BMON1_0_BASE,
+	[GAUDI2_BMON_NIC2_DBG_2_0] = mmNIC2_DBG_BMON2_0_BASE,
+	[GAUDI2_BMON_NIC2_DBG_0_1] = mmNIC2_DBG_BMON0_1_BASE,
+	[GAUDI2_BMON_NIC2_DBG_1_1] = mmNIC2_DBG_BMON1_1_BASE,
+	[GAUDI2_BMON_NIC2_DBG_2_1] = mmNIC2_DBG_BMON2_1_BASE,
+	[GAUDI2_BMON_NIC3_DBG_0_0] = mmNIC3_DBG_BMON0_0_BASE,
+	[GAUDI2_BMON_NIC3_DBG_1_0] = mmNIC3_DBG_BMON1_0_BASE,
+	[GAUDI2_BMON_NIC3_DBG_2_0] = mmNIC3_DBG_BMON2_0_BASE,
+	[GAUDI2_BMON_NIC3_DBG_0_1] = mmNIC3_DBG_BMON0_1_BASE,
+	[GAUDI2_BMON_NIC3_DBG_1_1] = mmNIC3_DBG_BMON1_1_BASE,
+	[GAUDI2_BMON_NIC3_DBG_2_1] = mmNIC3_DBG_BMON2_1_BASE,
+	[GAUDI2_BMON_NIC4_DBG_0_0] = mmNIC4_DBG_BMON0_0_BASE,
+	[GAUDI2_BMON_NIC4_DBG_1_0] = mmNIC4_DBG_BMON1_0_BASE,
+	[GAUDI2_BMON_NIC4_DBG_2_0] = mmNIC4_DBG_BMON2_0_BASE,
+	[GAUDI2_BMON_NIC4_DBG_0_1] = mmNIC4_DBG_BMON0_1_BASE,
+	[GAUDI2_BMON_NIC4_DBG_1_1] = mmNIC4_DBG_BMON1_1_BASE,
+	[GAUDI2_BMON_NIC4_DBG_2_1] = mmNIC4_DBG_BMON2_1_BASE,
+	[GAUDI2_BMON_NIC5_DBG_0_0] = mmNIC5_DBG_BMON0_0_BASE,
+	[GAUDI2_BMON_NIC5_DBG_1_0] = mmNIC5_DBG_BMON1_0_BASE,
+	[GAUDI2_BMON_NIC5_DBG_2_0] = mmNIC5_DBG_BMON2_0_BASE,
+	[GAUDI2_BMON_NIC5_DBG_0_1] = mmNIC5_DBG_BMON0_1_BASE,
+	[GAUDI2_BMON_NIC5_DBG_1_1] = mmNIC5_DBG_BMON1_1_BASE,
+	[GAUDI2_BMON_NIC5_DBG_2_1] = mmNIC5_DBG_BMON2_1_BASE,
+	[GAUDI2_BMON_NIC6_DBG_0_0] = mmNIC6_DBG_BMON0_0_BASE,
+	[GAUDI2_BMON_NIC6_DBG_1_0] = mmNIC6_DBG_BMON1_0_BASE,
+	[GAUDI2_BMON_NIC6_DBG_2_0] = mmNIC6_DBG_BMON2_0_BASE,
+	[GAUDI2_BMON_NIC6_DBG_0_1] = mmNIC6_DBG_BMON0_1_BASE,
+	[GAUDI2_BMON_NIC6_DBG_1_1] = mmNIC6_DBG_BMON1_1_BASE,
+	[GAUDI2_BMON_NIC6_DBG_2_1] = mmNIC6_DBG_BMON2_1_BASE,
+	[GAUDI2_BMON_NIC7_DBG_0_0] = mmNIC7_DBG_BMON0_0_BASE,
+	[GAUDI2_BMON_NIC7_DBG_1_0] = mmNIC7_DBG_BMON1_0_BASE,
+	[GAUDI2_BMON_NIC7_DBG_2_0] = mmNIC7_DBG_BMON2_0_BASE,
+	[GAUDI2_BMON_NIC7_DBG_0_1] = mmNIC7_DBG_BMON0_1_BASE,
+	[GAUDI2_BMON_NIC7_DBG_1_1] = mmNIC7_DBG_BMON1_1_BASE,
+	[GAUDI2_BMON_NIC7_DBG_2_1] = mmNIC7_DBG_BMON2_1_BASE,
+	[GAUDI2_BMON_NIC8_DBG_0_0] = mmNIC8_DBG_BMON0_0_BASE,
+	[GAUDI2_BMON_NIC8_DBG_1_0] = mmNIC8_DBG_BMON1_0_BASE,
+	[GAUDI2_BMON_NIC8_DBG_2_0] = mmNIC8_DBG_BMON2_0_BASE,
+	[GAUDI2_BMON_NIC8_DBG_0_1] = mmNIC8_DBG_BMON0_1_BASE,
+	[GAUDI2_BMON_NIC8_DBG_1_1] = mmNIC8_DBG_BMON1_1_BASE,
+	[GAUDI2_BMON_NIC8_DBG_2_1] = mmNIC8_DBG_BMON2_1_BASE,
+	[GAUDI2_BMON_NIC9_DBG_0_0] = mmNIC9_DBG_BMON0_0_BASE,
+	[GAUDI2_BMON_NIC9_DBG_1_0] = mmNIC9_DBG_BMON1_0_BASE,
+	[GAUDI2_BMON_NIC9_DBG_2_0] = mmNIC9_DBG_BMON2_0_BASE,
+	[GAUDI2_BMON_NIC9_DBG_0_1] = mmNIC9_DBG_BMON0_1_BASE,
+	[GAUDI2_BMON_NIC9_DBG_1_1] = mmNIC9_DBG_BMON1_1_BASE,
+	[GAUDI2_BMON_NIC9_DBG_2_1] = mmNIC9_DBG_BMON2_1_BASE,
+	[GAUDI2_BMON_NIC10_DBG_0_0] = mmNIC10_DBG_BMON0_0_BASE,
+	[GAUDI2_BMON_NIC10_DBG_1_0] = mmNIC10_DBG_BMON1_0_BASE,
+	[GAUDI2_BMON_NIC10_DBG_2_0] = mmNIC10_DBG_BMON2_0_BASE,
+	[GAUDI2_BMON_NIC10_DBG_0_1] = mmNIC10_DBG_BMON0_1_BASE,
+	[GAUDI2_BMON_NIC10_DBG_1_1] = mmNIC10_DBG_BMON1_1_BASE,
+	[GAUDI2_BMON_NIC10_DBG_2_1] = mmNIC10_DBG_BMON2_1_BASE,
+	[GAUDI2_BMON_NIC11_DBG_0_0] = mmNIC11_DBG_BMON0_0_BASE,
+	[GAUDI2_BMON_NIC11_DBG_1_0] = mmNIC11_DBG_BMON1_0_BASE,
+	[GAUDI2_BMON_NIC11_DBG_2_0] = mmNIC11_DBG_BMON2_0_BASE,
+	[GAUDI2_BMON_NIC11_DBG_0_1] = mmNIC11_DBG_BMON0_1_BASE,
+	[GAUDI2_BMON_NIC11_DBG_1_1] = mmNIC11_DBG_BMON1_1_BASE,
+	[GAUDI2_BMON_NIC11_DBG_2_1] = mmNIC11_DBG_BMON2_1_BASE
+};
+
+static u64 debug_spmu_regs[GAUDI2_SPMU_LAST + 1] = {
+	[GAUDI2_SPMU_DCORE0_TPC0_EML] = mmDCORE0_TPC0_EML_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE0_TPC1_EML] = mmDCORE0_TPC1_EML_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE0_TPC2_EML] = mmDCORE0_TPC2_EML_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE0_TPC3_EML] = mmDCORE0_TPC3_EML_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE0_TPC4_EML] = mmDCORE0_TPC4_EML_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE0_TPC5_EML] = mmDCORE0_TPC5_EML_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE0_TPC6_EML] = mmDCORE0_TPC6_EML_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE1_TPC0_EML] = mmDCORE1_TPC0_EML_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE1_TPC1_EML] = mmDCORE1_TPC1_EML_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE1_TPC2_EML] = mmDCORE1_TPC2_EML_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE1_TPC3_EML] = mmDCORE1_TPC3_EML_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE1_TPC4_EML] = mmDCORE1_TPC4_EML_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE1_TPC5_EML] = mmDCORE1_TPC5_EML_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE2_TPC0_EML] = mmDCORE2_TPC0_EML_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE2_TPC1_EML] = mmDCORE2_TPC1_EML_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE2_TPC2_EML] = mmDCORE2_TPC2_EML_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE2_TPC3_EML] = mmDCORE2_TPC3_EML_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE2_TPC4_EML] = mmDCORE2_TPC4_EML_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE2_TPC5_EML] = mmDCORE2_TPC5_EML_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE3_TPC0_EML] = mmDCORE3_TPC0_EML_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE3_TPC1_EML] = mmDCORE3_TPC1_EML_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE3_TPC2_EML] = mmDCORE3_TPC2_EML_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE3_TPC3_EML] = mmDCORE3_TPC3_EML_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE3_TPC4_EML] = mmDCORE3_TPC4_EML_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE3_TPC5_EML] = mmDCORE3_TPC5_EML_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE0_HMMU0_CS] = mmDCORE0_HMMU0_CS_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE0_HMMU1_CS] = mmDCORE0_HMMU1_CS_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE0_HMMU2_CS] = mmDCORE0_HMMU2_CS_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE0_HMMU3_CS] = mmDCORE0_HMMU3_CS_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE0_MME_CTRL] = mmDCORE0_MME_CTRL_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE0_MME_SBTE0] = mmDCORE0_MME_SBTE0_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE0_MME_SBTE1] = mmDCORE0_MME_SBTE1_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE0_MME_SBTE2] = mmDCORE0_MME_SBTE2_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE0_MME_SBTE3] = mmDCORE0_MME_SBTE3_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE0_MME_SBTE4] = mmDCORE0_MME_SBTE4_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE0_MME_ACC] = mmDCORE0_MME_ACC_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE0_SM] = mmDCORE0_SM_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE0_EDMA0_CS] = mmDCORE0_EDMA0_CS_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE0_EDMA1_CS] = mmDCORE0_EDMA1_CS_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE0_VDEC0_CS] = mmDCORE0_VDEC0_CS_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE0_VDEC1_CS] = mmDCORE0_VDEC1_CS_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE1_HMMU0_CS] = mmDCORE1_HMMU0_CS_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE1_HMMU1_CS] = mmDCORE1_HMMU1_CS_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE1_HMMU2_CS] = mmDCORE1_HMMU2_CS_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE1_HMMU3_CS] = mmDCORE1_HMMU3_CS_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE1_MME_CTRL] = mmDCORE1_MME_CTRL_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE1_MME_SBTE0] = mmDCORE1_MME_SBTE0_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE1_MME_SBTE1] = mmDCORE1_MME_SBTE1_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE1_MME_SBTE2] = mmDCORE1_MME_SBTE2_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE1_MME_SBTE3] = mmDCORE1_MME_SBTE3_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE1_MME_SBTE4] = mmDCORE1_MME_SBTE4_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE1_MME_ACC] = mmDCORE1_MME_ACC_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE1_SM] = mmDCORE1_SM_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE1_EDMA0_CS] = mmDCORE1_EDMA0_CS_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE1_EDMA1_CS] = mmDCORE1_EDMA1_CS_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE1_VDEC0_CS] = mmDCORE1_VDEC0_CS_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE1_VDEC1_CS] = mmDCORE1_VDEC1_CS_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE2_HMMU0_CS] = mmDCORE2_HMMU0_CS_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE2_HMMU1_CS] = mmDCORE2_HMMU1_CS_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE2_HMMU2_CS] = mmDCORE2_HMMU2_CS_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE2_HMMU3_CS] = mmDCORE2_HMMU3_CS_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE2_MME_CTRL] = mmDCORE2_MME_CTRL_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE2_MME_SBTE0] = mmDCORE2_MME_SBTE0_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE2_MME_SBTE1] = mmDCORE2_MME_SBTE1_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE2_MME_SBTE2] = mmDCORE2_MME_SBTE2_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE2_MME_SBTE3] = mmDCORE2_MME_SBTE3_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE2_MME_SBTE4] = mmDCORE2_MME_SBTE4_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE2_MME_ACC] = mmDCORE2_MME_ACC_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE2_SM] = mmDCORE2_SM_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE2_EDMA0_CS] = mmDCORE2_EDMA0_CS_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE2_EDMA1_CS] = mmDCORE2_EDMA1_CS_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE2_VDEC0_CS] = mmDCORE2_VDEC0_CS_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE2_VDEC1_CS] = mmDCORE2_VDEC1_CS_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE3_HMMU0_CS] = mmDCORE3_HMMU0_CS_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE3_HMMU1_CS] = mmDCORE3_HMMU1_CS_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE3_HMMU2_CS] = mmDCORE3_HMMU2_CS_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE3_HMMU3_CS] = mmDCORE3_HMMU3_CS_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE3_MME_CTRL] = mmDCORE3_MME_CTRL_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE3_MME_SBTE0] = mmDCORE3_MME_SBTE0_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE3_MME_SBTE1] = mmDCORE3_MME_SBTE1_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE3_MME_SBTE2] = mmDCORE3_MME_SBTE2_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE3_MME_SBTE3] = mmDCORE3_MME_SBTE3_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE3_MME_SBTE4] = mmDCORE3_MME_SBTE4_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE3_MME_ACC] = mmDCORE3_MME_ACC_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE3_SM] = mmDCORE3_SM_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE3_EDMA0_CS] = mmDCORE3_EDMA0_CS_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE3_EDMA1_CS] = mmDCORE3_EDMA1_CS_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE3_VDEC0_CS] = mmDCORE3_VDEC0_CS_SPMU_BASE,
+	[GAUDI2_SPMU_DCORE3_VDEC1_CS] = mmDCORE3_VDEC1_CS_SPMU_BASE,
+	[GAUDI2_SPMU_PCIE] = mmPCIE_SPMU_BASE,
+	[GAUDI2_SPMU_PSOC_ARC0_CS] = 0,
+	[GAUDI2_SPMU_PSOC_ARC1_CS] = 0,
+	[GAUDI2_SPMU_PDMA0_CS] = mmPDMA0_CS_SPMU_BASE,
+	[GAUDI2_SPMU_PDMA1_CS] = mmPDMA1_CS_SPMU_BASE,
+	[GAUDI2_SPMU_PMMU_CS] = mmPMMU_CS_SPMU_BASE,
+	[GAUDI2_SPMU_ROT0_CS] = mmROT0_CS_SPMU_BASE,
+	[GAUDI2_SPMU_ROT1_CS] = mmROT1_CS_SPMU_BASE,
+	[GAUDI2_SPMU_ARC_FARM_CS] = mmARC_FARM_CS_SPMU_BASE,
+	[GAUDI2_SPMU_KDMA_CS] = mmKDMA_CS_SPMU_BASE,
+	[GAUDI2_SPMU_PCIE_VDEC0_CS] = mmPCIE_VDEC0_CS_SPMU_BASE,
+	[GAUDI2_SPMU_PCIE_VDEC1_CS] = mmPCIE_VDEC1_CS_SPMU_BASE,
+	[GAUDI2_SPMU_HBM0_MC0_CS] = mmHBM0_MC0_CS_SPMU_BASE,
+	[GAUDI2_SPMU_HBM0_MC1_CS] = mmHBM0_MC1_CS_SPMU_BASE,
+	[GAUDI2_SPMU_HBM1_MC0_CS] = mmHBM1_MC0_CS_SPMU_BASE,
+	[GAUDI2_SPMU_HBM1_MC1_CS] = mmHBM1_MC1_CS_SPMU_BASE,
+	[GAUDI2_SPMU_HBM2_MC0_CS] = mmHBM2_MC0_CS_SPMU_BASE,
+	[GAUDI2_SPMU_HBM2_MC1_CS] = mmHBM2_MC1_CS_SPMU_BASE,
+	[GAUDI2_SPMU_HBM3_MC0_CS] = mmHBM3_MC0_CS_SPMU_BASE,
+	[GAUDI2_SPMU_HBM3_MC1_CS] = mmHBM3_MC1_CS_SPMU_BASE,
+	[GAUDI2_SPMU_HBM4_MC0_CS] = mmHBM4_MC0_CS_SPMU_BASE,
+	[GAUDI2_SPMU_HBM4_MC1_CS] = mmHBM4_MC1_CS_SPMU_BASE,
+	[GAUDI2_SPMU_HBM5_MC0_CS] = mmHBM5_MC0_CS_SPMU_BASE,
+	[GAUDI2_SPMU_HBM5_MC1_CS] = mmHBM5_MC1_CS_SPMU_BASE,
+	[GAUDI2_SPMU_NIC0_DBG_0] = mmNIC0_DBG_SPMU_0_BASE,
+	[GAUDI2_SPMU_NIC0_DBG_1] = mmNIC0_DBG_SPMU_1_BASE,
+	[GAUDI2_SPMU_NIC1_DBG_0] = mmNIC1_DBG_SPMU_0_BASE,
+	[GAUDI2_SPMU_NIC1_DBG_1] = mmNIC1_DBG_SPMU_1_BASE,
+	[GAUDI2_SPMU_NIC2_DBG_0] = mmNIC2_DBG_SPMU_0_BASE,
+	[GAUDI2_SPMU_NIC2_DBG_1] = mmNIC2_DBG_SPMU_1_BASE,
+	[GAUDI2_SPMU_NIC3_DBG_0] = mmNIC3_DBG_SPMU_0_BASE,
+	[GAUDI2_SPMU_NIC3_DBG_1] = mmNIC3_DBG_SPMU_1_BASE,
+	[GAUDI2_SPMU_NIC4_DBG_0] = mmNIC4_DBG_SPMU_0_BASE,
+	[GAUDI2_SPMU_NIC4_DBG_1] = mmNIC4_DBG_SPMU_1_BASE,
+	[GAUDI2_SPMU_NIC5_DBG_0] = mmNIC5_DBG_SPMU_0_BASE,
+	[GAUDI2_SPMU_NIC5_DBG_1] = mmNIC5_DBG_SPMU_1_BASE,
+	[GAUDI2_SPMU_NIC6_DBG_0] = mmNIC6_DBG_SPMU_0_BASE,
+	[GAUDI2_SPMU_NIC6_DBG_1] = mmNIC6_DBG_SPMU_1_BASE,
+	[GAUDI2_SPMU_NIC7_DBG_0] = mmNIC7_DBG_SPMU_0_BASE,
+	[GAUDI2_SPMU_NIC7_DBG_1] = mmNIC7_DBG_SPMU_1_BASE,
+	[GAUDI2_SPMU_NIC8_DBG_0] = mmNIC8_DBG_SPMU_0_BASE,
+	[GAUDI2_SPMU_NIC8_DBG_1] = mmNIC8_DBG_SPMU_1_BASE,
+	[GAUDI2_SPMU_NIC9_DBG_0] = mmNIC9_DBG_SPMU_0_BASE,
+	[GAUDI2_SPMU_NIC9_DBG_1] = mmNIC9_DBG_SPMU_1_BASE,
+	[GAUDI2_SPMU_NIC10_DBG_0] = mmNIC10_DBG_SPMU_0_BASE,
+	[GAUDI2_SPMU_NIC10_DBG_1] = mmNIC10_DBG_SPMU_1_BASE,
+	[GAUDI2_SPMU_NIC11_DBG_0] = mmNIC11_DBG_SPMU_0_BASE,
+	[GAUDI2_SPMU_NIC11_DBG_1] = mmNIC11_DBG_SPMU_1_BASE
+};
+
+static struct component_config_offsets xbar_edge_binning_cfg_table[XBAR_EDGE_ID_SIZE] = {
+	[XBAR_EDGE_ID_DCORE0] = {
+		.funnel_id = GAUDI2_FUNNEL_DCORE0_XBAR_EDGE,
+		.etf_id = COMPONENT_ID_INVALID,
+		.stm_id = COMPONENT_ID_INVALID,
+		.spmu_id = COMPONENT_ID_INVALID,
+		.bmon_count = 0,
+		.bmon_ids = {COMPONENT_ID_INVALID}
+	},
+	[XBAR_EDGE_ID_DCORE1] = {
+		.funnel_id = GAUDI2_FUNNEL_DCORE1_XBAR_EDGE,
+		.etf_id = COMPONENT_ID_INVALID,
+		.stm_id = COMPONENT_ID_INVALID,
+		.spmu_id = COMPONENT_ID_INVALID,
+		.bmon_count = 0,
+		.bmon_ids = {COMPONENT_ID_INVALID}
+	},
+	[XBAR_EDGE_ID_DCORE2] = {
+		.funnel_id = GAUDI2_FUNNEL_DCORE2_XBAR_EDGE,
+		.etf_id = COMPONENT_ID_INVALID,
+		.stm_id = COMPONENT_ID_INVALID,
+		.spmu_id = COMPONENT_ID_INVALID,
+		.bmon_count = 0,
+		.bmon_ids = {COMPONENT_ID_INVALID}
+	},
+	[XBAR_EDGE_ID_DCORE3] = {
+		.funnel_id = GAUDI2_FUNNEL_DCORE3_XBAR_EDGE,
+		.etf_id = COMPONENT_ID_INVALID,
+		.stm_id = COMPONENT_ID_INVALID,
+		.spmu_id = COMPONENT_ID_INVALID,
+		.bmon_count = 0,
+		.bmon_ids = {COMPONENT_ID_INVALID}
+	},
+};
+
+
+static struct component_config_offsets hmmu_binning_cfg_table[HMMU_ID_SIZE] = {
+	[HMMU_ID_DCORE0_HMMU0] = {
+		.funnel_id = COMPONENT_ID_INVALID,
+		.etf_id = GAUDI2_ETF_DCORE0_HMMU0_CS,
+		.stm_id = GAUDI2_STM_DCORE0_HMMU0_CS,
+		.spmu_id = GAUDI2_SPMU_DCORE0_HMMU0_CS,
+		.bmon_count = 5,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE0_HMMU0_0,
+			GAUDI2_BMON_DCORE0_HMMU0_1,
+			GAUDI2_BMON_DCORE0_HMMU0_2,
+			GAUDI2_BMON_DCORE0_HMMU0_3,
+			GAUDI2_BMON_DCORE0_HMMU0_4,
+		}
+	},
+	[HMMU_ID_DCORE0_HMMU1] = {
+		.funnel_id = COMPONENT_ID_INVALID,
+		.etf_id = GAUDI2_ETF_DCORE0_HMMU1_CS,
+		.stm_id = GAUDI2_STM_DCORE0_HMMU1_CS,
+		.spmu_id = GAUDI2_SPMU_DCORE0_HMMU1_CS,
+		.bmon_count = 5,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE0_HMMU1_0,
+			GAUDI2_BMON_DCORE0_HMMU1_1,
+			GAUDI2_BMON_DCORE0_HMMU1_2,
+			GAUDI2_BMON_DCORE0_HMMU1_3,
+			GAUDI2_BMON_DCORE0_HMMU1_4,
+		}
+	},
+	[HMMU_ID_DCORE0_HMMU2] = {
+		.funnel_id = COMPONENT_ID_INVALID,
+		.etf_id = GAUDI2_ETF_DCORE0_HMMU2_CS,
+		.stm_id = GAUDI2_STM_DCORE0_HMMU2_CS,
+		.spmu_id = GAUDI2_SPMU_DCORE0_HMMU2_CS,
+		.bmon_count = 5,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE0_HMMU2_0,
+			GAUDI2_BMON_DCORE0_HMMU2_1,
+			GAUDI2_BMON_DCORE0_HMMU2_2,
+			GAUDI2_BMON_DCORE0_HMMU2_3,
+			GAUDI2_BMON_DCORE0_HMMU2_4,
+		}
+	},
+	[HMMU_ID_DCORE0_HMMU3] = {
+		.funnel_id = COMPONENT_ID_INVALID,
+		.etf_id = GAUDI2_ETF_DCORE0_HMMU3_CS,
+		.stm_id = GAUDI2_STM_DCORE0_HMMU3_CS,
+		.spmu_id = GAUDI2_SPMU_DCORE0_HMMU3_CS,
+		.bmon_count = 5,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE0_HMMU3_0,
+			GAUDI2_BMON_DCORE0_HMMU3_1,
+			GAUDI2_BMON_DCORE0_HMMU3_2,
+			GAUDI2_BMON_DCORE0_HMMU3_3,
+			GAUDI2_BMON_DCORE0_HMMU3_4,
+		}
+	},
+	[HMMU_ID_DCORE1_HMMU0] = {
+		.funnel_id = COMPONENT_ID_INVALID,
+		.etf_id = GAUDI2_ETF_DCORE1_HMMU0_CS,
+		.stm_id = GAUDI2_STM_DCORE1_HMMU0_CS,
+		.spmu_id = GAUDI2_SPMU_DCORE1_HMMU0_CS,
+		.bmon_count = 5,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE1_HMMU0_0,
+			GAUDI2_BMON_DCORE1_HMMU0_1,
+			GAUDI2_BMON_DCORE1_HMMU0_2,
+			GAUDI2_BMON_DCORE1_HMMU0_3,
+			GAUDI2_BMON_DCORE1_HMMU0_4,
+		}
+	},
+	[HMMU_ID_DCORE1_HMMU1] = {
+		.funnel_id = COMPONENT_ID_INVALID,
+		.etf_id = GAUDI2_ETF_DCORE1_HMMU1_CS,
+		.stm_id = GAUDI2_STM_DCORE1_HMMU1_CS,
+		.spmu_id = GAUDI2_SPMU_DCORE1_HMMU1_CS,
+		.bmon_count = 5,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE1_HMMU1_0,
+			GAUDI2_BMON_DCORE1_HMMU1_1,
+			GAUDI2_BMON_DCORE1_HMMU1_2,
+			GAUDI2_BMON_DCORE1_HMMU1_3,
+			GAUDI2_BMON_DCORE1_HMMU1_4,
+		}
+	},
+	[HMMU_ID_DCORE1_HMMU2] = {
+		.funnel_id = COMPONENT_ID_INVALID,
+		.etf_id = GAUDI2_ETF_DCORE1_HMMU2_CS,
+		.stm_id = GAUDI2_STM_DCORE1_HMMU2_CS,
+		.spmu_id = GAUDI2_SPMU_DCORE1_HMMU2_CS,
+		.bmon_count = 5,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE1_HMMU2_0,
+			GAUDI2_BMON_DCORE1_HMMU2_1,
+			GAUDI2_BMON_DCORE1_HMMU2_2,
+			GAUDI2_BMON_DCORE1_HMMU2_3,
+			GAUDI2_BMON_DCORE1_HMMU2_4,
+		}
+	},
+	[HMMU_ID_DCORE1_HMMU3] = {
+		.funnel_id = COMPONENT_ID_INVALID,
+		.etf_id = GAUDI2_ETF_DCORE1_HMMU3_CS,
+		.stm_id = GAUDI2_STM_DCORE1_HMMU3_CS,
+		.spmu_id = GAUDI2_SPMU_DCORE1_HMMU3_CS,
+		.bmon_count = 5,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE1_HMMU3_0,
+			GAUDI2_BMON_DCORE1_HMMU3_1,
+			GAUDI2_BMON_DCORE1_HMMU3_2,
+			GAUDI2_BMON_DCORE1_HMMU3_3,
+			GAUDI2_BMON_DCORE1_HMMU3_4,
+		}
+	},
+	[HMMU_ID_DCORE2_HMMU0] = {
+		.funnel_id = COMPONENT_ID_INVALID,
+		.etf_id = GAUDI2_ETF_DCORE2_HMMU0_CS,
+		.stm_id = GAUDI2_STM_DCORE2_HMMU0_CS,
+		.spmu_id = GAUDI2_SPMU_DCORE2_HMMU0_CS,
+		.bmon_count = 5,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE2_HMMU0_0,
+			GAUDI2_BMON_DCORE2_HMMU0_1,
+			GAUDI2_BMON_DCORE2_HMMU0_2,
+			GAUDI2_BMON_DCORE2_HMMU0_3,
+			GAUDI2_BMON_DCORE2_HMMU0_4,
+		}
+	},
+	[HMMU_ID_DCORE2_HMMU1] = {
+		.funnel_id = COMPONENT_ID_INVALID,
+		.etf_id = GAUDI2_ETF_DCORE2_HMMU1_CS,
+		.stm_id = GAUDI2_STM_DCORE2_HMMU1_CS,
+		.spmu_id = GAUDI2_SPMU_DCORE2_HMMU1_CS,
+		.bmon_count = 5,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE2_HMMU1_0,
+			GAUDI2_BMON_DCORE2_HMMU1_1,
+			GAUDI2_BMON_DCORE2_HMMU1_2,
+			GAUDI2_BMON_DCORE2_HMMU1_3,
+			GAUDI2_BMON_DCORE2_HMMU1_4,
+		}
+	},
+	[HMMU_ID_DCORE2_HMMU2] = {
+		.funnel_id = COMPONENT_ID_INVALID,
+		.etf_id = GAUDI2_ETF_DCORE2_HMMU2_CS,
+		.stm_id = GAUDI2_STM_DCORE2_HMMU2_CS,
+		.spmu_id = GAUDI2_SPMU_DCORE2_HMMU2_CS,
+		.bmon_count = 5,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE2_HMMU2_0,
+			GAUDI2_BMON_DCORE2_HMMU2_1,
+			GAUDI2_BMON_DCORE2_HMMU2_2,
+			GAUDI2_BMON_DCORE2_HMMU2_3,
+			GAUDI2_BMON_DCORE2_HMMU2_4,
+		}
+	},
+	[HMMU_ID_DCORE2_HMMU3] = {
+		.funnel_id = COMPONENT_ID_INVALID,
+		.etf_id = GAUDI2_ETF_DCORE2_HMMU3_CS,
+		.stm_id = GAUDI2_STM_DCORE2_HMMU3_CS,
+		.spmu_id = GAUDI2_SPMU_DCORE2_HMMU3_CS,
+		.bmon_count = 5,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE2_HMMU3_0,
+			GAUDI2_BMON_DCORE2_HMMU3_1,
+			GAUDI2_BMON_DCORE2_HMMU3_2,
+			GAUDI2_BMON_DCORE2_HMMU3_3,
+			GAUDI2_BMON_DCORE2_HMMU3_4,
+		}
+	},
+	[HMMU_ID_DCORE3_HMMU0] = {
+		.funnel_id = COMPONENT_ID_INVALID,
+		.etf_id = GAUDI2_ETF_DCORE3_HMMU0_CS,
+		.stm_id = GAUDI2_STM_DCORE3_HMMU0_CS,
+		.spmu_id = GAUDI2_SPMU_DCORE3_HMMU0_CS,
+		.bmon_count = 5,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE3_HMMU0_0,
+			GAUDI2_BMON_DCORE3_HMMU0_1,
+			GAUDI2_BMON_DCORE3_HMMU0_2,
+			GAUDI2_BMON_DCORE3_HMMU0_3,
+			GAUDI2_BMON_DCORE3_HMMU0_4,
+		}
+	},
+	[HMMU_ID_DCORE3_HMMU1] = {
+		.funnel_id = COMPONENT_ID_INVALID,
+		.etf_id = GAUDI2_ETF_DCORE3_HMMU1_CS,
+		.stm_id = GAUDI2_STM_DCORE3_HMMU1_CS,
+		.spmu_id = GAUDI2_SPMU_DCORE3_HMMU1_CS,
+		.bmon_count = 5,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE3_HMMU1_0,
+			GAUDI2_BMON_DCORE3_HMMU1_1,
+			GAUDI2_BMON_DCORE3_HMMU1_2,
+			GAUDI2_BMON_DCORE3_HMMU1_3,
+			GAUDI2_BMON_DCORE3_HMMU1_4,
+		}
+	},
+	[HMMU_ID_DCORE3_HMMU2] = {
+		.funnel_id = COMPONENT_ID_INVALID,
+		.etf_id = GAUDI2_ETF_DCORE3_HMMU2_CS,
+		.stm_id = GAUDI2_STM_DCORE3_HMMU2_CS,
+		.spmu_id = GAUDI2_SPMU_DCORE3_HMMU2_CS,
+		.bmon_count = 5,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE3_HMMU2_0,
+			GAUDI2_BMON_DCORE3_HMMU2_1,
+			GAUDI2_BMON_DCORE3_HMMU2_2,
+			GAUDI2_BMON_DCORE3_HMMU2_3,
+			GAUDI2_BMON_DCORE3_HMMU2_4,
+		}
+	},
+	[HMMU_ID_DCORE3_HMMU3] = {
+		.funnel_id = COMPONENT_ID_INVALID,
+		.etf_id = GAUDI2_ETF_DCORE3_HMMU3_CS,
+		.stm_id = GAUDI2_STM_DCORE3_HMMU3_CS,
+		.spmu_id = GAUDI2_SPMU_DCORE3_HMMU3_CS,
+		.bmon_count = 5,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE3_HMMU3_0,
+			GAUDI2_BMON_DCORE3_HMMU3_1,
+			GAUDI2_BMON_DCORE3_HMMU3_2,
+			GAUDI2_BMON_DCORE3_HMMU3_3,
+			GAUDI2_BMON_DCORE3_HMMU3_4,
+		}
+	},
+};
+
+static struct component_config_offsets hbm_mc0_binning_cfg_table[HBM_ID_SIZE] = {
+	[HBM_ID0] = {
+		.funnel_id = GAUDI2_FUNNEL_HBM0_MC0,
+		.etf_id = GAUDI2_ETF_HBM0_MC0_CS,
+		.stm_id = GAUDI2_STM_HBM0_MC0_CS,
+		.spmu_id = GAUDI2_SPMU_HBM0_MC0_CS,
+		.bmon_count = 0,
+		.bmon_ids = {COMPONENT_ID_INVALID}
+	},
+	[HBM_ID1] = {
+		.funnel_id = GAUDI2_FUNNEL_HBM1_MC0,
+		.etf_id = GAUDI2_ETF_HBM1_MC0_CS,
+		.stm_id = GAUDI2_STM_HBM1_MC0_CS,
+		.spmu_id = GAUDI2_SPMU_HBM1_MC0_CS,
+		.bmon_count = 0,
+		.bmon_ids = {COMPONENT_ID_INVALID}
+	},
+	[HBM_ID2] = {
+		.funnel_id = GAUDI2_FUNNEL_HBM2_MC0,
+		.etf_id = GAUDI2_ETF_HBM2_MC0_CS,
+		.stm_id = GAUDI2_STM_HBM2_MC0_CS,
+		.spmu_id = GAUDI2_SPMU_HBM2_MC0_CS,
+		.bmon_count = 0,
+		.bmon_ids = {COMPONENT_ID_INVALID}
+	},
+	[HBM_ID3] = {
+		.funnel_id = GAUDI2_FUNNEL_HBM3_MC0,
+		.etf_id = GAUDI2_ETF_HBM3_MC0_CS,
+		.stm_id = GAUDI2_STM_HBM3_MC0_CS,
+		.spmu_id = GAUDI2_SPMU_HBM3_MC0_CS,
+		.bmon_count = 0,
+		.bmon_ids = {COMPONENT_ID_INVALID}
+	},
+	[HBM_ID4] = {
+		.funnel_id = GAUDI2_FUNNEL_HBM4_MC0,
+		.etf_id = GAUDI2_ETF_HBM4_MC0_CS,
+		.stm_id = GAUDI2_STM_HBM4_MC0_CS,
+		.spmu_id = GAUDI2_SPMU_HBM4_MC0_CS,
+		.bmon_count = 0,
+		.bmon_ids = {COMPONENT_ID_INVALID}
+	},
+	[HBM_ID5] = {
+		.funnel_id = GAUDI2_FUNNEL_HBM5_MC0,
+		.etf_id = GAUDI2_ETF_HBM5_MC0_CS,
+		.stm_id = GAUDI2_STM_HBM5_MC0_CS,
+		.spmu_id = GAUDI2_SPMU_HBM5_MC0_CS,
+		.bmon_count = 0,
+		.bmon_ids = {COMPONENT_ID_INVALID}
+	},
+};
+
+static struct component_config_offsets hbm_mc1_binning_cfg_table[HBM_ID_SIZE] = {
+	[HBM_ID0] = {
+		.funnel_id = GAUDI2_FUNNEL_HBM0_MC1,
+		.etf_id = GAUDI2_ETF_HBM0_MC1_CS,
+		.stm_id = GAUDI2_STM_HBM0_MC1_CS,
+		.spmu_id = GAUDI2_SPMU_HBM0_MC1_CS,
+		.bmon_count = 0,
+		.bmon_ids = {COMPONENT_ID_INVALID}
+	},
+	[HBM_ID1] = {
+		.funnel_id = GAUDI2_FUNNEL_HBM1_MC1,
+		.etf_id = GAUDI2_ETF_HBM1_MC1_CS,
+		.stm_id = GAUDI2_STM_HBM1_MC1_CS,
+		.spmu_id = GAUDI2_SPMU_HBM1_MC1_CS,
+		.bmon_count = 0,
+		.bmon_ids = {COMPONENT_ID_INVALID}
+	},
+	[HBM_ID2] = {
+		.funnel_id = GAUDI2_FUNNEL_HBM2_MC1,
+		.etf_id = GAUDI2_ETF_HBM2_MC1_CS,
+		.stm_id = GAUDI2_STM_HBM2_MC1_CS,
+		.spmu_id = GAUDI2_SPMU_HBM2_MC1_CS,
+		.bmon_count = 0,
+		.bmon_ids = {COMPONENT_ID_INVALID}
+	},
+	[HBM_ID3] = {
+		.funnel_id = GAUDI2_FUNNEL_HBM3_MC1,
+		.etf_id = GAUDI2_ETF_HBM3_MC1_CS,
+		.stm_id = GAUDI2_STM_HBM3_MC1_CS,
+		.spmu_id = GAUDI2_SPMU_HBM3_MC1_CS,
+		.bmon_count = 0,
+		.bmon_ids = {COMPONENT_ID_INVALID}
+	},
+	[HBM_ID4] = {
+		.funnel_id = GAUDI2_FUNNEL_HBM4_MC1,
+		.etf_id = GAUDI2_ETF_HBM4_MC1_CS,
+		.stm_id = GAUDI2_STM_HBM4_MC1_CS,
+		.spmu_id = GAUDI2_SPMU_HBM4_MC1_CS,
+		.bmon_count = 0,
+		.bmon_ids = {COMPONENT_ID_INVALID}
+	},
+	[HBM_ID5] = {
+		.funnel_id = GAUDI2_FUNNEL_HBM5_MC1,
+		.etf_id = GAUDI2_ETF_HBM5_MC1_CS,
+		.stm_id = GAUDI2_STM_HBM5_MC1_CS,
+		.spmu_id = GAUDI2_SPMU_HBM5_MC1_CS,
+		.bmon_count = 0,
+		.bmon_ids = {COMPONENT_ID_INVALID}
+	},
+};
+
+static struct component_config_offsets decoder_binning_cfg_table[DEC_ID_SIZE] = {
+	[DEC_ID_DCORE0_DEC0] = {
+		.funnel_id = COMPONENT_ID_INVALID,
+		.etf_id = GAUDI2_ETF_DCORE0_VDEC0_CS,
+		.stm_id = GAUDI2_STM_DCORE0_VDEC0_CS,
+		.spmu_id = GAUDI2_SPMU_DCORE0_VDEC0_CS,
+		.bmon_count = 3,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE0_VDEC0_0,
+			GAUDI2_BMON_DCORE0_VDEC0_1,
+			GAUDI2_BMON_DCORE0_VDEC0_2,
+		}
+	},
+	[DEC_ID_DCORE0_DEC1] = {
+		.funnel_id = COMPONENT_ID_INVALID,
+		.etf_id = GAUDI2_ETF_DCORE0_VDEC1_CS,
+		.stm_id = GAUDI2_STM_DCORE0_VDEC1_CS,
+		.spmu_id = GAUDI2_SPMU_DCORE0_VDEC1_CS,
+		.bmon_count = 3,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE0_VDEC1_0,
+			GAUDI2_BMON_DCORE0_VDEC1_1,
+			GAUDI2_BMON_DCORE0_VDEC1_2,
+		}
+	},
+	[DEC_ID_DCORE1_DEC0] = {
+		.funnel_id = COMPONENT_ID_INVALID,
+		.etf_id = GAUDI2_ETF_DCORE1_VDEC0_CS,
+		.stm_id = GAUDI2_STM_DCORE1_VDEC0_CS,
+		.spmu_id = GAUDI2_SPMU_DCORE1_VDEC0_CS,
+		.bmon_count = 3,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE1_VDEC0_0,
+			GAUDI2_BMON_DCORE1_VDEC0_1,
+			GAUDI2_BMON_DCORE1_VDEC0_2,
+		}
+	},
+	[DEC_ID_DCORE1_DEC1] = {
+		.funnel_id = COMPONENT_ID_INVALID,
+		.etf_id = GAUDI2_ETF_DCORE1_VDEC1_CS,
+		.stm_id = GAUDI2_STM_DCORE1_VDEC1_CS,
+		.spmu_id = GAUDI2_SPMU_DCORE1_VDEC1_CS,
+		.bmon_count = 3,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE1_VDEC1_0,
+			GAUDI2_BMON_DCORE1_VDEC1_1,
+			GAUDI2_BMON_DCORE1_VDEC1_2,
+		}
+	},
+	[DEC_ID_DCORE2_DEC0] = {
+		.funnel_id = COMPONENT_ID_INVALID,
+		.etf_id = GAUDI2_ETF_DCORE2_VDEC0_CS,
+		.stm_id = GAUDI2_STM_DCORE2_VDEC0_CS,
+		.spmu_id = GAUDI2_SPMU_DCORE2_VDEC0_CS,
+		.bmon_count = 3,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE2_VDEC0_0,
+			GAUDI2_BMON_DCORE2_VDEC0_1,
+			GAUDI2_BMON_DCORE2_VDEC0_2,
+		}
+	},
+	[DEC_ID_DCORE2_DEC1] = {
+		.funnel_id = COMPONENT_ID_INVALID,
+		.etf_id = GAUDI2_ETF_DCORE2_VDEC1_CS,
+		.stm_id = GAUDI2_STM_DCORE2_VDEC1_CS,
+		.spmu_id = GAUDI2_SPMU_DCORE2_VDEC1_CS,
+		.bmon_count = 3,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE2_VDEC1_0,
+			GAUDI2_BMON_DCORE2_VDEC1_1,
+			GAUDI2_BMON_DCORE2_VDEC1_2,
+		}
+	},
+	[DEC_ID_DCORE3_DEC0] = {
+		.funnel_id = COMPONENT_ID_INVALID,
+		.etf_id = GAUDI2_ETF_DCORE3_VDEC0_CS,
+		.stm_id = GAUDI2_STM_DCORE3_VDEC0_CS,
+		.spmu_id = GAUDI2_SPMU_DCORE3_VDEC0_CS,
+		.bmon_count = 3,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE3_VDEC0_0,
+			GAUDI2_BMON_DCORE3_VDEC0_1,
+			GAUDI2_BMON_DCORE3_VDEC0_2,
+		}
+	},
+	[DEC_ID_DCORE3_DEC1] = {
+		.funnel_id = COMPONENT_ID_INVALID,
+		.etf_id = GAUDI2_ETF_DCORE3_VDEC1_CS,
+		.stm_id = GAUDI2_STM_DCORE3_VDEC1_CS,
+		.spmu_id = GAUDI2_SPMU_DCORE3_VDEC1_CS,
+		.bmon_count = 3,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE3_VDEC1_0,
+			GAUDI2_BMON_DCORE3_VDEC1_1,
+			GAUDI2_BMON_DCORE3_VDEC1_2,
+		}
+	},
+	[DEC_ID_PCIE_VDEC0] = {
+		.funnel_id = COMPONENT_ID_INVALID,
+		.etf_id = GAUDI2_ETF_PCIE_VDEC0_CS,
+		.stm_id = GAUDI2_STM_PCIE_VDEC0_CS,
+		.spmu_id = GAUDI2_SPMU_PCIE_VDEC0_CS,
+		.bmon_count = 3,
+		.bmon_ids = {
+			GAUDI2_BMON_PCIE_VDEC0_0,
+			GAUDI2_BMON_PCIE_VDEC0_1,
+			GAUDI2_BMON_PCIE_VDEC0_2,
+		}
+	},
+	[DEC_ID_PCIE_VDEC1] = {
+		.funnel_id = COMPONENT_ID_INVALID,
+		.etf_id = GAUDI2_ETF_PCIE_VDEC1_CS,
+		.stm_id = GAUDI2_STM_PCIE_VDEC1_CS,
+		.spmu_id = GAUDI2_SPMU_PCIE_VDEC1_CS,
+		.bmon_count = 3,
+		.bmon_ids = {
+			GAUDI2_BMON_PCIE_VDEC1_0,
+			GAUDI2_BMON_PCIE_VDEC1_1,
+			GAUDI2_BMON_PCIE_VDEC1_2,
+		}
+	},
+};
+
+static struct component_config_offsets edma_binning_cfg_table[EDMA_ID_SIZE] = {
+	[EDMA_ID_DCORE0_INSTANCE0] = {
+		.funnel_id = COMPONENT_ID_INVALID,
+		.etf_id = GAUDI2_ETF_DCORE0_EDMA0_CS,
+		.stm_id = GAUDI2_STM_DCORE0_EDMA0_CS,
+		.spmu_id = GAUDI2_SPMU_DCORE0_EDMA0_CS,
+		.bmon_count = 2,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE0_EDMA0_0,
+			GAUDI2_BMON_DCORE0_EDMA0_1,
+		}
+	},
+	[EDMA_ID_DCORE0_INSTANCE1] = {
+		.funnel_id = COMPONENT_ID_INVALID,
+		.etf_id = GAUDI2_ETF_DCORE0_EDMA1_CS,
+		.stm_id = GAUDI2_STM_DCORE0_EDMA1_CS,
+		.spmu_id = GAUDI2_SPMU_DCORE0_EDMA1_CS,
+		.bmon_count = 2,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE0_EDMA1_0,
+			GAUDI2_BMON_DCORE0_EDMA1_1,
+		}
+	},
+	[EDMA_ID_DCORE1_INSTANCE0] = {
+		.funnel_id = COMPONENT_ID_INVALID,
+		.etf_id = GAUDI2_ETF_DCORE1_EDMA0_CS,
+		.stm_id = GAUDI2_STM_DCORE1_EDMA0_CS,
+		.spmu_id = GAUDI2_SPMU_DCORE1_EDMA0_CS,
+		.bmon_count = 2,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE1_EDMA0_0,
+			GAUDI2_BMON_DCORE1_EDMA0_1,
+		}
+	},
+	[EDMA_ID_DCORE1_INSTANCE1] = {
+		.funnel_id = COMPONENT_ID_INVALID,
+		.etf_id = GAUDI2_ETF_DCORE1_EDMA1_CS,
+		.stm_id = GAUDI2_STM_DCORE1_EDMA1_CS,
+		.spmu_id = GAUDI2_SPMU_DCORE1_EDMA1_CS,
+		.bmon_count = 2,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE1_EDMA1_0,
+			GAUDI2_BMON_DCORE1_EDMA1_1,
+		}
+	},
+	[EDMA_ID_DCORE2_INSTANCE0] = {
+		.funnel_id = COMPONENT_ID_INVALID,
+		.etf_id = GAUDI2_ETF_DCORE2_EDMA0_CS,
+		.stm_id = GAUDI2_STM_DCORE2_EDMA0_CS,
+		.spmu_id = GAUDI2_SPMU_DCORE2_EDMA0_CS,
+		.bmon_count = 2,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE2_EDMA0_0,
+			GAUDI2_BMON_DCORE2_EDMA0_1,
+		}
+	},
+	[EDMA_ID_DCORE2_INSTANCE1] = {
+		.funnel_id = COMPONENT_ID_INVALID,
+		.etf_id = GAUDI2_ETF_DCORE2_EDMA1_CS,
+		.stm_id = GAUDI2_STM_DCORE2_EDMA1_CS,
+		.spmu_id = GAUDI2_SPMU_DCORE2_EDMA1_CS,
+		.bmon_count = 2,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE2_EDMA1_0,
+			GAUDI2_BMON_DCORE2_EDMA1_1,
+		}
+	},
+	[EDMA_ID_DCORE3_INSTANCE0] = {
+		.funnel_id = COMPONENT_ID_INVALID,
+		.etf_id = GAUDI2_ETF_DCORE3_EDMA0_CS,
+		.stm_id = GAUDI2_STM_DCORE3_EDMA0_CS,
+		.spmu_id = GAUDI2_SPMU_DCORE3_EDMA0_CS,
+		.bmon_count = 2,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE3_EDMA0_0,
+			GAUDI2_BMON_DCORE3_EDMA0_1,
+		}
+	},
+	[EDMA_ID_DCORE3_INSTANCE1] = {
+		.funnel_id = COMPONENT_ID_INVALID,
+		.etf_id = GAUDI2_ETF_DCORE3_EDMA1_CS,
+		.stm_id = GAUDI2_STM_DCORE3_EDMA1_CS,
+		.spmu_id = GAUDI2_SPMU_DCORE3_EDMA1_CS,
+		.bmon_count = 2,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE3_EDMA1_0,
+			GAUDI2_BMON_DCORE3_EDMA1_1,
+		}
+	},
+};
+
+static struct component_config_offsets tpc_binning_cfg_table[TPC_ID_SIZE] = {
+	[TPC_ID_DCORE0_TPC0] = {
+		.funnel_id = GAUDI2_FUNNEL_DCORE0_TPC0_EML,
+		.etf_id = GAUDI2_ETF_DCORE0_TPC0_EML,
+		.stm_id = GAUDI2_STM_DCORE0_TPC0_EML,
+		.spmu_id = GAUDI2_SPMU_DCORE0_TPC0_EML,
+		.bmon_count = 4,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE0_TPC0_EML_0,
+			GAUDI2_BMON_DCORE0_TPC0_EML_1,
+			GAUDI2_BMON_DCORE0_TPC0_EML_2,
+			GAUDI2_BMON_DCORE0_TPC0_EML_3,
+		}
+	},
+	[TPC_ID_DCORE0_TPC1] = {
+		.funnel_id = GAUDI2_FUNNEL_DCORE0_TPC1_EML,
+		.etf_id = GAUDI2_ETF_DCORE0_TPC1_EML,
+		.stm_id = GAUDI2_STM_DCORE0_TPC1_EML,
+		.spmu_id = GAUDI2_SPMU_DCORE0_TPC1_EML,
+		.bmon_count = 4,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE0_TPC1_EML_0,
+			GAUDI2_BMON_DCORE0_TPC1_EML_1,
+			GAUDI2_BMON_DCORE0_TPC1_EML_2,
+			GAUDI2_BMON_DCORE0_TPC1_EML_3,
+		}
+	},
+	[TPC_ID_DCORE0_TPC2] = {
+		.funnel_id = GAUDI2_FUNNEL_DCORE0_TPC2_EML,
+		.etf_id = GAUDI2_ETF_DCORE0_TPC2_EML,
+		.stm_id = GAUDI2_STM_DCORE0_TPC2_EML,
+		.spmu_id = GAUDI2_SPMU_DCORE0_TPC2_EML,
+		.bmon_count = 4,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE0_TPC2_EML_0,
+			GAUDI2_BMON_DCORE0_TPC2_EML_1,
+			GAUDI2_BMON_DCORE0_TPC2_EML_2,
+			GAUDI2_BMON_DCORE0_TPC2_EML_3,
+		}
+	},
+	[TPC_ID_DCORE0_TPC3] = {
+		.funnel_id = GAUDI2_FUNNEL_DCORE0_TPC3_EML,
+		.etf_id = GAUDI2_ETF_DCORE0_TPC3_EML,
+		.stm_id = GAUDI2_STM_DCORE0_TPC3_EML,
+		.spmu_id = GAUDI2_SPMU_DCORE0_TPC3_EML,
+		.bmon_count = 4,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE0_TPC3_EML_0,
+			GAUDI2_BMON_DCORE0_TPC3_EML_1,
+			GAUDI2_BMON_DCORE0_TPC3_EML_2,
+			GAUDI2_BMON_DCORE0_TPC3_EML_3,
+		}
+	},
+	[TPC_ID_DCORE0_TPC4] = {
+		.funnel_id = GAUDI2_FUNNEL_DCORE0_TPC4_EML,
+		.etf_id = GAUDI2_ETF_DCORE0_TPC4_EML,
+		.stm_id = GAUDI2_STM_DCORE0_TPC4_EML,
+		.spmu_id = GAUDI2_SPMU_DCORE0_TPC4_EML,
+		.bmon_count = 4,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE0_TPC4_EML_0,
+			GAUDI2_BMON_DCORE0_TPC4_EML_1,
+			GAUDI2_BMON_DCORE0_TPC4_EML_2,
+			GAUDI2_BMON_DCORE0_TPC4_EML_3,
+		}
+	},
+	[TPC_ID_DCORE0_TPC5] = {
+		.funnel_id = GAUDI2_FUNNEL_DCORE0_TPC5_EML,
+		.etf_id = GAUDI2_ETF_DCORE0_TPC5_EML,
+		.stm_id = GAUDI2_STM_DCORE0_TPC5_EML,
+		.spmu_id = GAUDI2_SPMU_DCORE0_TPC5_EML,
+		.bmon_count = 4,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE0_TPC5_EML_0,
+			GAUDI2_BMON_DCORE0_TPC5_EML_1,
+			GAUDI2_BMON_DCORE0_TPC5_EML_2,
+			GAUDI2_BMON_DCORE0_TPC5_EML_3,
+		}
+	},
+	[TPC_ID_DCORE1_TPC0] = {
+		.funnel_id = GAUDI2_FUNNEL_DCORE1_TPC0_EML,
+		.etf_id = GAUDI2_ETF_DCORE1_TPC0_EML,
+		.stm_id = GAUDI2_STM_DCORE1_TPC0_EML,
+		.spmu_id = GAUDI2_SPMU_DCORE1_TPC0_EML,
+		.bmon_count = 4,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE1_TPC0_EML_0,
+			GAUDI2_BMON_DCORE1_TPC0_EML_1,
+			GAUDI2_BMON_DCORE1_TPC0_EML_2,
+			GAUDI2_BMON_DCORE1_TPC0_EML_3,
+		}
+	},
+	[TPC_ID_DCORE1_TPC1] = {
+		.funnel_id = GAUDI2_FUNNEL_DCORE1_TPC1_EML,
+		.etf_id = GAUDI2_ETF_DCORE1_TPC1_EML,
+		.stm_id = GAUDI2_STM_DCORE1_TPC1_EML,
+		.spmu_id = GAUDI2_SPMU_DCORE1_TPC1_EML,
+		.bmon_count = 4,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE1_TPC1_EML_0,
+			GAUDI2_BMON_DCORE1_TPC1_EML_1,
+			GAUDI2_BMON_DCORE1_TPC1_EML_2,
+			GAUDI2_BMON_DCORE1_TPC1_EML_3,
+		}
+	},
+	[TPC_ID_DCORE1_TPC2] = {
+		.funnel_id = GAUDI2_FUNNEL_DCORE1_TPC2_EML,
+		.etf_id = GAUDI2_ETF_DCORE1_TPC2_EML,
+		.stm_id = GAUDI2_STM_DCORE1_TPC2_EML,
+		.spmu_id = GAUDI2_SPMU_DCORE1_TPC2_EML,
+		.bmon_count = 4,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE1_TPC2_EML_0,
+			GAUDI2_BMON_DCORE1_TPC2_EML_1,
+			GAUDI2_BMON_DCORE1_TPC2_EML_2,
+			GAUDI2_BMON_DCORE1_TPC2_EML_3,
+		}
+	},
+	[TPC_ID_DCORE1_TPC3] = {
+		.funnel_id = GAUDI2_FUNNEL_DCORE1_TPC3_EML,
+		.etf_id = GAUDI2_ETF_DCORE1_TPC3_EML,
+		.stm_id = GAUDI2_STM_DCORE1_TPC3_EML,
+		.spmu_id = GAUDI2_SPMU_DCORE1_TPC3_EML,
+		.bmon_count = 4,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE1_TPC3_EML_0,
+			GAUDI2_BMON_DCORE1_TPC3_EML_1,
+			GAUDI2_BMON_DCORE1_TPC3_EML_2,
+			GAUDI2_BMON_DCORE1_TPC3_EML_3,
+		}
+	},
+	[TPC_ID_DCORE1_TPC4] = {
+		.funnel_id = GAUDI2_FUNNEL_DCORE1_TPC4_EML,
+		.etf_id = GAUDI2_ETF_DCORE1_TPC4_EML,
+		.stm_id = GAUDI2_STM_DCORE1_TPC4_EML,
+		.spmu_id = GAUDI2_SPMU_DCORE1_TPC4_EML,
+		.bmon_count = 4,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE1_TPC4_EML_0,
+			GAUDI2_BMON_DCORE1_TPC4_EML_1,
+			GAUDI2_BMON_DCORE1_TPC4_EML_2,
+			GAUDI2_BMON_DCORE1_TPC4_EML_3,
+		}
+	},
+	[TPC_ID_DCORE1_TPC5] = {
+		.funnel_id = GAUDI2_FUNNEL_DCORE1_TPC5_EML,
+		.etf_id = GAUDI2_ETF_DCORE1_TPC5_EML,
+		.stm_id = GAUDI2_STM_DCORE1_TPC5_EML,
+		.spmu_id = GAUDI2_SPMU_DCORE1_TPC5_EML,
+		.bmon_count = 4,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE1_TPC5_EML_0,
+			GAUDI2_BMON_DCORE1_TPC5_EML_1,
+			GAUDI2_BMON_DCORE1_TPC5_EML_2,
+			GAUDI2_BMON_DCORE1_TPC5_EML_3,
+		}
+	},
+	[TPC_ID_DCORE2_TPC0] = {
+		.funnel_id = GAUDI2_FUNNEL_DCORE2_TPC0_EML,
+		.etf_id = GAUDI2_ETF_DCORE2_TPC0_EML,
+		.stm_id = GAUDI2_STM_DCORE2_TPC0_EML,
+		.spmu_id = GAUDI2_SPMU_DCORE2_TPC0_EML,
+		.bmon_count = 4,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE2_TPC0_EML_0,
+			GAUDI2_BMON_DCORE2_TPC0_EML_1,
+			GAUDI2_BMON_DCORE2_TPC0_EML_2,
+			GAUDI2_BMON_DCORE2_TPC0_EML_3,
+		}
+	},
+	[TPC_ID_DCORE2_TPC1] = {
+		.funnel_id = GAUDI2_FUNNEL_DCORE2_TPC1_EML,
+		.etf_id = GAUDI2_ETF_DCORE2_TPC1_EML,
+		.stm_id = GAUDI2_STM_DCORE2_TPC1_EML,
+		.spmu_id = GAUDI2_SPMU_DCORE2_TPC1_EML,
+		.bmon_count = 4,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE2_TPC1_EML_0,
+			GAUDI2_BMON_DCORE2_TPC1_EML_1,
+			GAUDI2_BMON_DCORE2_TPC1_EML_2,
+			GAUDI2_BMON_DCORE2_TPC1_EML_3,
+		}
+	},
+	[TPC_ID_DCORE2_TPC2] = {
+		.funnel_id = GAUDI2_FUNNEL_DCORE2_TPC2_EML,
+		.etf_id = GAUDI2_ETF_DCORE2_TPC2_EML,
+		.stm_id = GAUDI2_STM_DCORE2_TPC2_EML,
+		.spmu_id = GAUDI2_SPMU_DCORE2_TPC2_EML,
+		.bmon_count = 4,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE2_TPC2_EML_0,
+			GAUDI2_BMON_DCORE2_TPC2_EML_1,
+			GAUDI2_BMON_DCORE2_TPC2_EML_2,
+			GAUDI2_BMON_DCORE2_TPC2_EML_3,
+		}
+	},
+	[TPC_ID_DCORE2_TPC3] = {
+		.funnel_id = GAUDI2_FUNNEL_DCORE2_TPC3_EML,
+		.etf_id = GAUDI2_ETF_DCORE2_TPC3_EML,
+		.stm_id = GAUDI2_STM_DCORE2_TPC3_EML,
+		.spmu_id = GAUDI2_SPMU_DCORE2_TPC3_EML,
+		.bmon_count = 4,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE2_TPC3_EML_0,
+			GAUDI2_BMON_DCORE2_TPC3_EML_1,
+			GAUDI2_BMON_DCORE2_TPC3_EML_2,
+			GAUDI2_BMON_DCORE2_TPC3_EML_3,
+		}
+	},
+	[TPC_ID_DCORE2_TPC4] = {
+		.funnel_id = GAUDI2_FUNNEL_DCORE2_TPC4_EML,
+		.etf_id = GAUDI2_ETF_DCORE2_TPC4_EML,
+		.stm_id = GAUDI2_STM_DCORE2_TPC4_EML,
+		.spmu_id = GAUDI2_SPMU_DCORE2_TPC4_EML,
+		.bmon_count = 4,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE2_TPC4_EML_0,
+			GAUDI2_BMON_DCORE2_TPC4_EML_1,
+			GAUDI2_BMON_DCORE2_TPC4_EML_2,
+			GAUDI2_BMON_DCORE2_TPC4_EML_3,
+		}
+	},
+	[TPC_ID_DCORE2_TPC5] = {
+		.funnel_id = GAUDI2_FUNNEL_DCORE2_TPC5_EML,
+		.etf_id = GAUDI2_ETF_DCORE2_TPC5_EML,
+		.stm_id = GAUDI2_STM_DCORE2_TPC5_EML,
+		.spmu_id = GAUDI2_SPMU_DCORE2_TPC5_EML,
+		.bmon_count = 4,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE2_TPC5_EML_0,
+			GAUDI2_BMON_DCORE2_TPC5_EML_1,
+			GAUDI2_BMON_DCORE2_TPC5_EML_2,
+			GAUDI2_BMON_DCORE2_TPC5_EML_3,
+		}
+	},
+	[TPC_ID_DCORE3_TPC0] = {
+		.funnel_id = GAUDI2_FUNNEL_DCORE3_TPC0_EML,
+		.etf_id = GAUDI2_ETF_DCORE3_TPC0_EML,
+		.stm_id = GAUDI2_STM_DCORE3_TPC0_EML,
+		.spmu_id = GAUDI2_SPMU_DCORE3_TPC0_EML,
+		.bmon_count = 4,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE3_TPC0_EML_0,
+			GAUDI2_BMON_DCORE3_TPC0_EML_1,
+			GAUDI2_BMON_DCORE3_TPC0_EML_2,
+			GAUDI2_BMON_DCORE3_TPC0_EML_3,
+		}
+	},
+	[TPC_ID_DCORE3_TPC1] = {
+		.funnel_id = GAUDI2_FUNNEL_DCORE3_TPC1_EML,
+		.etf_id = GAUDI2_ETF_DCORE3_TPC1_EML,
+		.stm_id = GAUDI2_STM_DCORE3_TPC1_EML,
+		.spmu_id = GAUDI2_SPMU_DCORE3_TPC1_EML,
+		.bmon_count = 4,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE3_TPC1_EML_0,
+			GAUDI2_BMON_DCORE3_TPC1_EML_1,
+			GAUDI2_BMON_DCORE3_TPC1_EML_2,
+			GAUDI2_BMON_DCORE3_TPC1_EML_3,
+		}
+	},
+	[TPC_ID_DCORE3_TPC2] = {
+		.funnel_id = GAUDI2_FUNNEL_DCORE3_TPC2_EML,
+		.etf_id = GAUDI2_ETF_DCORE3_TPC2_EML,
+		.stm_id = GAUDI2_STM_DCORE3_TPC2_EML,
+		.spmu_id = GAUDI2_SPMU_DCORE3_TPC2_EML,
+		.bmon_count = 4,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE3_TPC2_EML_0,
+			GAUDI2_BMON_DCORE3_TPC2_EML_1,
+			GAUDI2_BMON_DCORE3_TPC2_EML_2,
+			GAUDI2_BMON_DCORE3_TPC2_EML_3,
+		}
+	},
+	[TPC_ID_DCORE3_TPC3] = {
+		.funnel_id = GAUDI2_FUNNEL_DCORE3_TPC3_EML,
+		.etf_id = GAUDI2_ETF_DCORE3_TPC3_EML,
+		.stm_id = GAUDI2_STM_DCORE3_TPC3_EML,
+		.spmu_id = GAUDI2_SPMU_DCORE3_TPC3_EML,
+		.bmon_count = 4,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE3_TPC3_EML_0,
+			GAUDI2_BMON_DCORE3_TPC3_EML_1,
+			GAUDI2_BMON_DCORE3_TPC3_EML_2,
+			GAUDI2_BMON_DCORE3_TPC3_EML_3,
+		}
+	},
+	[TPC_ID_DCORE3_TPC4] = {
+		.funnel_id = GAUDI2_FUNNEL_DCORE3_TPC4_EML,
+		.etf_id = GAUDI2_ETF_DCORE3_TPC4_EML,
+		.stm_id = GAUDI2_STM_DCORE3_TPC4_EML,
+		.spmu_id = GAUDI2_SPMU_DCORE3_TPC4_EML,
+		.bmon_count = 4,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE3_TPC4_EML_0,
+			GAUDI2_BMON_DCORE3_TPC4_EML_1,
+			GAUDI2_BMON_DCORE3_TPC4_EML_2,
+			GAUDI2_BMON_DCORE3_TPC4_EML_3,
+		}
+	},
+	[TPC_ID_DCORE3_TPC5] = {
+		.funnel_id = GAUDI2_FUNNEL_DCORE3_TPC5_EML,
+		.etf_id = GAUDI2_ETF_DCORE3_TPC5_EML,
+		.stm_id = GAUDI2_STM_DCORE3_TPC5_EML,
+		.spmu_id = GAUDI2_SPMU_DCORE3_TPC5_EML,
+		.bmon_count = 4,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE3_TPC5_EML_0,
+			GAUDI2_BMON_DCORE3_TPC5_EML_1,
+			GAUDI2_BMON_DCORE3_TPC5_EML_2,
+			GAUDI2_BMON_DCORE3_TPC5_EML_3,
+		}
+	},
+	[TPC_ID_DCORE0_TPC6] = {
+		.funnel_id = GAUDI2_FUNNEL_DCORE0_TPC6_EML,
+		.etf_id = GAUDI2_ETF_DCORE0_TPC6_EML,
+		.stm_id = GAUDI2_STM_DCORE0_TPC6_EML,
+		.spmu_id = GAUDI2_SPMU_DCORE0_TPC6_EML,
+		.bmon_count = 4,
+		.bmon_ids = {
+			GAUDI2_BMON_DCORE0_TPC6_EML_0,
+			GAUDI2_BMON_DCORE0_TPC6_EML_1,
+			GAUDI2_BMON_DCORE0_TPC6_EML_2,
+			GAUDI2_BMON_DCORE0_TPC6_EML_3,
+		}
+	}
+};
+
+static int gaudi2_coresight_timeout(struct hl_device *hdev, u64 addr,
+					int position, bool up)
+{
+	int rc;
+	u32 val, timeout_usec;
+
+	if (hdev->pldm)
+		timeout_usec = GAUDI2_PLDM_CORESIGHT_TIMEOUT_USEC;
+	else
+		timeout_usec = CORESIGHT_TIMEOUT_USEC;
+
+	rc = hl_poll_timeout(
+		hdev,
+		addr,
+		val,
+		up ? val & BIT(position) : !(val & BIT(position)),
+		1000,
+		timeout_usec);
+
+	if (rc)
+		dev_err(hdev->dev,
+			"Timeout while waiting for coresight, addr: 0x%llx, position: %d, up: %d\n",
+			addr, position, up);
+
+	return rc;
+}
+
+static int gaudi2_unlock_coresight_unit(struct hl_device *hdev,
+	const u64 base_reg)
+{
+	int rc = 0;
+
+	WREG32(base_reg + mmCORESIGHT_UNLOCK_REGISTER_OFFSET, CORESIGHT_UNLOCK);
+
+	rc = gaudi2_coresight_timeout(hdev, base_reg + mmCORESIGHT_UNLOCK_STATUS_REGISTER_OFFSET,
+					1, 0);
+
+	if (rc)
+		dev_err(hdev->dev,
+			"Failed to unlock register base addr: 0x%llx , position: 1, up: 0\n",
+			base_reg);
+
+	return rc;
+}
+
+static int gaudi2_config_stm(struct hl_device *hdev, struct hl_debug_params *params)
+{
+	struct hl_debug_params_stm *input;
+	u64 base_reg;
+	u32 frequency;
+	u32 read_reg;
+	int rc;
+
+	if (params->reg_idx >= ARRAY_SIZE(debug_stm_regs)) {
+		dev_err(hdev->dev, "Invalid register index in STM\n");
+		return -EINVAL;
+	}
+
+	base_reg = debug_stm_regs[params->reg_idx];
+
+	/*
+	 * in case base reg is 0x0 we ignore this configuration
+	 */
+	if (!base_reg)
+		return 0;
+
+	/* check if stub component on pldm
+	 * we check offset 0xCFC STMDMAIDR in case
+	 * return value is 0x0 - hence stub component
+	 */
+	read_reg = RREG32(base_reg + mmSTM_STMDMAIDR_OFFSET);
+	if (hdev->pldm &&  read_reg == 0x0)
+		return 0;
+
+	rc = gaudi2_unlock_coresight_unit(hdev, base_reg);
+	if (rc)
+		return -EIO;
+
+	if (params->enable) {
+		input = params->input;
+
+		if (!input)
+			return -EINVAL;
+
+		WREG32(base_reg + mmSTM_STMTCSR_OFFSET, 0x80004);
+		/* dummy read for pldm to flush outstanding writes */
+		if (hdev->pldm)
+			RREG32(base_reg + mmSTM_STMTCSR_OFFSET);
+
+		WREG32(base_reg + mmSTM_STMHEMCR_OFFSET, 7);
+		WREG32(base_reg + mmSTM_STMHEBSR_OFFSET, 0);
+		WREG32(base_reg + mmSTM_STMHEER_OFFSET, lower_32_bits(input->he_mask));
+		WREG32(base_reg + mmSTM_STMHEBSR_OFFSET, 1);
+		WREG32(base_reg + mmSTM_STMHEER_OFFSET, upper_32_bits(input->he_mask));
+		WREG32(base_reg + mmSTM_STMSPTRIGCSR_OFFSET, 0x10);
+		WREG32(base_reg + mmSTM_STMSPSCR_OFFSET, 0);
+		WREG32(base_reg + mmSTM_STMSPER_OFFSET, lower_32_bits(input->sp_mask));
+		WREG32(base_reg + mmSTM_STMITATBID_OFFSET, input->id);
+		WREG32(base_reg + mmSTM_STMHEMASTR_OFFSET, 0x80);
+		frequency = hdev->asic_prop.psoc_timestamp_frequency;
+		if (frequency == 0)
+			frequency = input->frequency;
+		WREG32(base_reg + mmSTM_STMTSFREQR_OFFSET, frequency);
+		WREG32(base_reg + mmSTM_STMSYNCR_OFFSET, 0x7FF);
+		WREG32(base_reg + mmSTM_STMTCSR_OFFSET, 0x27 | (input->id << 16));
+	} else {
+		WREG32(base_reg + mmSTM_STMTCSR_OFFSET, 4);
+		WREG32(base_reg + mmSTM_STMHEMCR_OFFSET, 0);
+		WREG32(base_reg + mmSTM_STMHEBSR_OFFSET, 1);
+		WREG32(base_reg + mmSTM_STMHEER_OFFSET, 0);
+		WREG32(base_reg + mmSTM_STMHETER_OFFSET, 0);
+		WREG32(base_reg + mmSTM_STMHEBSR_OFFSET, 0);
+		WREG32(base_reg + mmSTM_STMSPTER_OFFSET, 0);
+		WREG32(base_reg + mmSTM_STMSPER_OFFSET, 0);
+		WREG32(base_reg + mmSTM_STMHEMASTR_OFFSET, 0x80);
+		WREG32(base_reg + mmSTM_STMSPTRIGCSR_OFFSET, 0);
+		WREG32(base_reg + mmSTM_STMSPSCR_OFFSET, 0);
+		WREG32(base_reg + mmSTM_STMSPMSCR_OFFSET, 0);
+		WREG32(base_reg + mmSTM_STMTSFREQR_OFFSET, 0);
+
+		rc = gaudi2_coresight_timeout(hdev, base_reg + mmSTM_STMTCSR_OFFSET, 23, false);
+		if (rc) {
+			dev_err(hdev->dev, "Failed to disable STM on timeout, error %d\n", rc);
+			return rc;
+		}
+
+		WREG32(base_reg + mmSTM_STMTCSR_OFFSET, 4);
+	}
+
+	return 0;
+}
+
+static int gaudi2_config_etf(struct hl_device *hdev, struct hl_debug_params *params)
+{
+	struct hl_debug_params_etf *input;
+	u64 base_reg;
+	u32 read_reg;
+	u32 val;
+	int rc;
+
+	if (params->reg_idx >= ARRAY_SIZE(debug_etf_regs)) {
+		dev_err(hdev->dev, "Invalid register index in ETF\n");
+		return -EINVAL;
+	}
+
+	base_reg = debug_etf_regs[params->reg_idx];
+
+	/*
+	 * in case base reg is 0x0 we ignore this configuration
+	 */
+	if (!base_reg)
+		return 0;
+
+
+	/* in pldm we need to check if unit is not stub
+	 * for doing do need to read ETF STS register and check
+	 * it is not return 0x0 - in case it does
+	 * it means that this is stub, we ignore this and return 0
+	 * means success
+	 */
+	read_reg = RREG32(base_reg + mmETF_STS_OFFSET);
+	if (hdev->pldm &&  read_reg == 0x0)
+		return 0;
+
+	rc = gaudi2_unlock_coresight_unit(hdev, base_reg);
+	if (rc)
+		return -EIO;
+
+	val = RREG32(base_reg + mmETF_CTL_OFFSET);
+
+	if ((!params->enable && val == 0x0) || (params->enable && val != 0x0))
+		return 0;
+
+	val = RREG32(base_reg + mmETF_FFCR_OFFSET);
+	val |= 0x1000;
+	WREG32(base_reg + mmETF_FFCR_OFFSET, val);
+	val |= 0x40;
+	WREG32(base_reg + mmETF_FFCR_OFFSET, val);
+
+	rc = gaudi2_coresight_timeout(hdev, base_reg + mmETF_FFCR_OFFSET, 6, false);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to %s ETF on timeout, error %d\n",
+			params->enable ? "enable" : "disable", rc);
+		return rc;
+	}
+
+	rc = gaudi2_coresight_timeout(hdev, base_reg + mmETF_STS_OFFSET, 2, true);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to %s ETF on timeout, error %d\n",
+			params->enable ? "enable" : "disable", rc);
+		return rc;
+	}
+
+	WREG32(base_reg + mmETF_CTL_OFFSET, 0);
+
+	if (params->enable) {
+		input = params->input;
+
+		if (!input)
+			return -EINVAL;
+
+		val = RREG32(base_reg + mmETF_RSZ_OFFSET) << 2;
+		if (val) {
+			val = ffs(val);
+			WREG32(base_reg + mmETF_PSCR_OFFSET, val);
+		} else {
+			WREG32(base_reg + mmETF_PSCR_OFFSET, 0x10);
+		}
+
+		WREG32(base_reg + mmETF_BUFWM_OFFSET, 0x3FFC);
+		WREG32(base_reg + mmETF_MODE_OFFSET, input->sink_mode);
+		WREG32(base_reg + mmETF_FFCR_OFFSET, 0x4001);
+		WREG32(base_reg + mmETF_CTL_OFFSET, 1);
+	} else {
+		WREG32(base_reg + mmETF_BUFWM_OFFSET, 0);
+		WREG32(base_reg + mmETF_MODE_OFFSET, 0);
+		WREG32(base_reg + mmETF_FFCR_OFFSET, 0);
+	}
+
+	return 0;
+}
+
+static int gaudi2_etr_validate_address(struct hl_device *hdev, u64 addr, u64 size)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct gaudi2_device *gaudi2 = hdev->asic_specific;
+
+	if (addr > (addr + size)) {
+		dev_err(hdev->dev, "ETR buffer size %llu overflow\n", size);
+		return false;
+	}
+
+	if (gaudi2->hw_cap_initialized & HW_CAP_PMMU) {
+		if (hl_mem_area_inside_range(addr, size,
+				prop->pmmu.start_addr,
+				prop->pmmu.end_addr))
+			return true;
+
+		if (hl_mem_area_inside_range(addr, size,
+				prop->pmmu_huge.start_addr,
+				prop->pmmu_huge.end_addr))
+			return true;
+
+		if (hl_mem_area_inside_range(addr, size,
+				prop->dmmu.start_addr,
+				prop->dmmu.end_addr))
+			return true;
+	} else {
+		if (hl_mem_area_inside_range(addr, size,
+				prop->dram_user_base_address,
+				prop->dram_end_address))
+			return true;
+	}
+
+	if (hl_mem_area_inside_range(addr, size,
+			prop->sram_user_base_address,
+			prop->sram_end_address))
+		return true;
+
+	if (!(gaudi2->hw_cap_initialized & HW_CAP_PMMU))
+		dev_err(hdev->dev, "ETR buffer should be in SRAM/DRAM\n");
+
+	return false;
+}
+
+static int gaudi2_config_etr(struct hl_device *hdev, struct hl_ctx *ctx,
+				struct hl_debug_params *params)
+{
+	struct hl_debug_params_etr *input;
+	u64 msb;
+	u32 val;
+	int rc;
+
+	rc = gaudi2_unlock_coresight_unit(hdev, mmPSOC_ETR_BASE);
+	if (rc)
+		return -EIO;
+
+	val = RREG32(mmPSOC_ETR_CTL);
+
+	if ((!params->enable && val == 0x0) || (params->enable && val != 0x0))
+		return 0;
+
+	val = RREG32(mmPSOC_ETR_FFCR);
+	val |= 0x1000;
+	WREG32(mmPSOC_ETR_FFCR, val);
+	val |= 0x40;
+	WREG32(mmPSOC_ETR_FFCR, val);
+
+	rc = gaudi2_coresight_timeout(hdev, mmPSOC_ETR_FFCR, 6, false);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n",
+				params->enable ? "enable" : "disable", rc);
+		return rc;
+	}
+
+	rc = gaudi2_coresight_timeout(hdev, mmPSOC_ETR_STS, 2, true);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n",
+				params->enable ? "enable" : "disable", rc);
+		return rc;
+	}
+
+	WREG32(mmPSOC_ETR_CTL, 0);
+
+	if (params->enable) {
+		input = params->input;
+
+		if (!input)
+			return -EINVAL;
+
+		if (input->buffer_size == 0) {
+			dev_err(hdev->dev, "ETR buffer size should be bigger than 0\n");
+			return -EINVAL;
+		}
+
+		if (!gaudi2_etr_validate_address(hdev, input->buffer_address, input->buffer_size)) {
+			dev_err(hdev->dev, "ETR buffer address is invalid\n");
+			return -EINVAL;
+		}
+
+		RMWREG32(mmPSOC_GLOBAL_CONF_TRACE_AWUSER, ctx->asid, MMUBP_ASID_MASK);
+		RMWREG32(mmPSOC_GLOBAL_CONF_TRACE_ARUSER, ctx->asid, MMUBP_ASID_MASK);
+
+		msb = upper_32_bits(input->buffer_address) >> 8;
+		WREG32(mmPSOC_GLOBAL_CONF_TRACE_ADDR, msb);
+
+		WREG32(mmPSOC_ETR_BUFWM, 0x3FFC);
+		WREG32(mmPSOC_ETR_RSZ, input->buffer_size);
+		WREG32(mmPSOC_ETR_MODE, input->sink_mode);
+		/* write the protection bits only if security is disable */
+		if (!(hdev->fw_components & FW_TYPE_BOOT_CPU)) {
+			/* make ETR not privileged */
+			val = FIELD_PREP(PSOC_ETR_AXICTL_PROTCTRLBIT0_MASK, 0);
+			/* make ETR non-secured (inverted logic) */
+			val |= FIELD_PREP(PSOC_ETR_AXICTL_PROTCTRLBIT1_MASK, 1);
+			/* burst size 16 */
+			val |= FIELD_PREP(PSOC_ETR_AXICTL_WRBURSTLEN_MASK, 0xF);
+			WREG32(mmPSOC_ETR_AXICTL, val);
+		}
+		WREG32(mmPSOC_ETR_DBALO, lower_32_bits(input->buffer_address));
+		WREG32(mmPSOC_ETR_DBAHI, upper_32_bits(input->buffer_address));
+		WREG32(mmPSOC_ETR_FFCR, 3);
+		WREG32(mmPSOC_ETR_PSCR, 0x10);
+		WREG32(mmPSOC_ETR_CTL, 1);
+	} else {
+		WREG32(mmPSOC_ETR_BUFWM, 0);
+		WREG32(mmPSOC_ETR_RSZ, 0x400);
+		WREG32(mmPSOC_ETR_DBALO, 0);
+		WREG32(mmPSOC_ETR_DBAHI, 0);
+		WREG32(mmPSOC_ETR_PSCR, 0);
+		WREG32(mmPSOC_ETR_MODE, 0);
+		WREG32(mmPSOC_ETR_FFCR, 0);
+
+		if (params->output_size >= sizeof(u64)) {
+			u32 rwp, rwphi;
+
+			/*
+			 * The trace buffer address is 64 bits wide. The end of
+			 * the buffer is set in the RWP register (lower 32
+			 * bits), and in the RWPHI register (upper 8 bits).
+			 * The 24 msb of the 64-bit address are stored in a
+			 * global configuration register.
+			 */
+			rwp = RREG32(mmPSOC_ETR_RWP);
+			rwphi = RREG32(mmPSOC_ETR_RWPHI) & 0xff;
+			msb = RREG32(mmPSOC_GLOBAL_CONF_TRACE_ADDR);
+			*(u64 *) params->output = ((u64) msb << 40) | ((u64) rwphi << 32) | rwp;
+		}
+	}
+
+	return 0;
+}
+
+static int gaudi2_config_funnel(struct hl_device *hdev, struct hl_debug_params *params)
+{
+	u64 base_reg;
+	u32 val = params->enable ? 0xFFF : 0;
+	u32 read_reg;
+	int rc = 0;
+
+	if (params->reg_idx >= ARRAY_SIZE(debug_funnel_regs)) {
+		dev_err(hdev->dev, "Invalid register index in FUNNEL\n");
+		return -EINVAL;
+	}
+
+	base_reg = debug_funnel_regs[params->reg_idx];
+
+	/*
+	 * in case base reg is 0x0 we ignore this configuration
+	 */
+	if (!base_reg)
+		return 0;
+
+
+	/* in pldm we need to check if unit is not stub
+	 * for doing so, need to read DEVID value.
+	 * in case return 0x0 - it means that this is stub,
+	 * we ignore this and return 0 - means success
+	 */
+	read_reg = RREG32(base_reg + mmFUNNEL_DEVID_OFFSET);
+	if (hdev->pldm && read_reg == 0x0)
+		return 0;
+
+	rc = gaudi2_unlock_coresight_unit(hdev, base_reg);
+	if (rc)
+		return -EIO;
+
+	WREG32(base_reg, val);
+
+	return 0;
+}
+
+static int gaudi2_config_bmon(struct hl_device *hdev, struct hl_debug_params *params)
+{
+	struct hl_debug_params_bmon *input;
+	u64 base_reg;
+	u32 read_reg;
+
+	if (params->reg_idx >= ARRAY_SIZE(debug_bmon_regs)) {
+		dev_err(hdev->dev, "Invalid register index in BMON\n");
+		return -EINVAL;
+	}
+
+	base_reg = debug_bmon_regs[params->reg_idx];
+
+	/*
+	 * in case base reg is 0x0 we ignore this configuration
+	 */
+	if (!base_reg)
+		return 0;
+
+
+	/* in pldm we need to check if unit is not stub
+	 * for doing do need to read Control Register (offset 0x0) and check
+	 * it is not return 0x0 - in case it does
+	 * it means that this is stub, we ignore this and return 0
+	 * means success
+	 */
+	read_reg = RREG32(base_reg + mmBMON_CR_OFFSET);
+	if (hdev->pldm &&  read_reg == 0x0)
+		return 0;
+
+	WREG32(base_reg + mmBMON_ATTREN_OFFSET, 1);
+	/* dummy read for pldm to flush outstanding writes */
+	if (hdev->pldm)
+		RREG32(base_reg + mmBMON_ATTREN_OFFSET);
+
+	/* Write Only	Reset AXIMON */
+
+	WREG32(base_reg + mmBMON_RESET_OFFSET, 0x1);
+
+	if (params->enable) {
+		input = params->input;
+
+		if (!input)
+			return -EINVAL;
+
+		WREG32(base_reg + mmBMON_ADDRL_S0_OFFSET, lower_32_bits(input->start_addr0));
+		WREG32(base_reg + mmBMON_ADDRH_S0_OFFSET, upper_32_bits(input->start_addr0));
+		WREG32(base_reg + mmBMON_ADDRL_E0_OFFSET, lower_32_bits(input->addr_mask0));
+		WREG32(base_reg + mmBMON_ADDRH_E0_OFFSET, upper_32_bits(input->addr_mask0));
+		WREG32(base_reg + mmBMON_ADDRL_S1_OFFSET, lower_32_bits(input->start_addr1));
+		WREG32(base_reg + mmBMON_ADDRH_S1_OFFSET, upper_32_bits(input->start_addr1));
+		WREG32(base_reg + mmBMON_ADDRL_E1_OFFSET, lower_32_bits(input->addr_mask1));
+		WREG32(base_reg + mmBMON_ADDRH_E1_OFFSET, upper_32_bits(input->addr_mask1));
+		WREG32(base_reg + mmBMON_ADDRL_S2_OFFSET, lower_32_bits(input->start_addr2));
+		WREG32(base_reg + mmBMON_ADDRH_S2_OFFSET, upper_32_bits(input->start_addr2));
+		WREG32(base_reg + mmBMON_ADDRL_E2_OFFSET, lower_32_bits(input->end_addr2));
+		WREG32(base_reg + mmBMON_ADDRH_E2_OFFSET, upper_32_bits(input->end_addr2));
+		WREG32(base_reg + mmBMON_ADDRL_S3_OFFSET, lower_32_bits(input->start_addr3));
+		WREG32(base_reg + mmBMON_ADDRH_S3_OFFSET, upper_32_bits(input->start_addr3));
+		WREG32(base_reg + mmBMON_ADDRL_E3_OFFSET, lower_32_bits(input->end_addr3));
+		WREG32(base_reg + mmBMON_ADDRH_E3_OFFSET, upper_32_bits(input->end_addr3));
+
+		WREG32(base_reg + mmBMON_IDL_OFFSET, 0x0);
+		WREG32(base_reg + mmBMON_IDH_OFFSET, 0x0);
+
+		WREG32(base_reg + mmBMON_ATTREN_OFFSET, 0);
+		WREG32(base_reg + mmBMON_BW_WIN_OFFSET, input->bw_win);
+		WREG32(base_reg + mmBMON_WIN_CAPTURE_OFFSET, input->win_capture);
+		WREG32(base_reg + mmBMON_REDUCTION_OFFSET, 0x1 | (13 << 8));
+		WREG32(base_reg + mmBMON_STM_TRC_OFFSET, 0x7 | (input->id << 8));
+		WREG32(base_reg + mmBMON_CR_OFFSET, input->control);
+	} else {
+		WREG32(base_reg + mmBMON_ADDRL_S0_OFFSET, 0);
+		WREG32(base_reg + mmBMON_ADDRH_S0_OFFSET, 0);
+		WREG32(base_reg + mmBMON_ADDRL_E0_OFFSET, 0);
+		WREG32(base_reg + mmBMON_ADDRH_E0_OFFSET, 0);
+		WREG32(base_reg + mmBMON_ADDRL_S1_OFFSET, 0);
+		WREG32(base_reg + mmBMON_ADDRH_S1_OFFSET, 0);
+		WREG32(base_reg + mmBMON_ADDRL_E1_OFFSET, 0);
+		WREG32(base_reg + mmBMON_ADDRH_E1_OFFSET, 0);
+		WREG32(base_reg + mmBMON_ADDRL_S2_OFFSET, 0);
+		WREG32(base_reg + mmBMON_ADDRH_S2_OFFSET, 0);
+		WREG32(base_reg + mmBMON_ADDRL_E2_OFFSET, 0);
+		WREG32(base_reg + mmBMON_ADDRH_E2_OFFSET, 0);
+		WREG32(base_reg + mmBMON_ADDRL_S3_OFFSET, 0);
+		WREG32(base_reg + mmBMON_ADDRH_S3_OFFSET, 0);
+		WREG32(base_reg + mmBMON_ADDRL_E3_OFFSET, 0);
+		WREG32(base_reg + mmBMON_ADDRH_E3_OFFSET, 0);
+		WREG32(base_reg + mmBMON_REDUCTION_OFFSET, 0);
+		WREG32(base_reg + mmBMON_STM_TRC_OFFSET, 0x7 | (0xA << 8));
+		WREG32(base_reg + mmBMON_CR_OFFSET, 0x41);
+	}
+
+	return 0;
+}
+
+static int gaudi2_config_spmu(struct hl_device *hdev, struct hl_debug_params *params)
+{
+	struct hl_debug_params_spmu *input = params->input;
+	u32 output_arr_len;
+	u32 cycle_cnt_idx;
+	u32 overflow_idx;
+	u32 events_num;
+	u32 event_mask;
+	u64 base_reg;
+	u32 read_reg;
+	u64 *output;
+	int i;
+
+	if (params->reg_idx >= ARRAY_SIZE(debug_spmu_regs)) {
+		dev_err(hdev->dev, "Invalid register index in SPMU\n");
+		return -EINVAL;
+	}
+
+	base_reg = debug_spmu_regs[params->reg_idx];
+
+	/*
+	 * in case base reg is 0x0 we ignore this configuration
+	 */
+	if (!base_reg)
+		return 0;
+
+	/* in pldm we need to check if unit is not stub
+	 * for doing do need to read  PMTRC (at offset 0x200)
+	 * address and check if return value is 0x0 - in case it does
+	 * it means that this is stub, we ignore this and return 0
+	 * means success
+	 */
+	read_reg = RREG32(base_reg + mmSPMU_PMCR_EL0_OFFSET);
+	if (hdev->pldm && read_reg == 0x0)
+		return 0;
+
+	if (params->enable) {
+		input = params->input;
+
+		if (!input)
+			return -EINVAL;
+
+		if (input->event_types_num > SPMU_MAX_COUNTERS) {
+			dev_err(hdev->dev, "too many event types values for SPMU enable\n");
+			return -EINVAL;
+		}
+
+		WREG32(base_reg + mmSPMU_PMCR_EL0_OFFSET, 0x41013046);
+		WREG32(base_reg + mmSPMU_PMCR_EL0_OFFSET, 0x41013040);
+
+		/* dummy read for pldm to flush outstanding writes */
+		if (hdev->pldm)
+			RREG32(base_reg);
+
+		for (i = 0 ; i < input->event_types_num ; i++)
+			WREG32(base_reg + mmSPMU_PMEVTYPER0_EL0_OFFSET + i * 4,
+				input->event_types[i]);
+
+		WREG32(base_reg + mmSPMU_PMTRC_OFFSET, input->pmtrc_val);
+		WREG32(base_reg + mmSPMU_TRC_CTRL_HOST_OFFSET, input->trc_ctrl_host_val);
+		WREG32(base_reg + mmSPMU_TRC_EN_HOST_OFFSET, input->trc_en_host_val);
+
+		WREG32(base_reg + mmSPMU_PMCR_EL0_OFFSET, 0x41013041);
+
+		/*
+		 * set enabled events mask based on input->event_types_num
+		 */
+		event_mask = 0x80000000;
+		if (input->event_types_num)
+			event_mask |= GENMASK(input->event_types_num - 1, 0);
+
+		WREG32(base_reg + mmSPMU_PMCNTENSET_EL0_OFFSET, event_mask);
+	} else {
+		output = params->output;
+		output_arr_len = params->output_size / 8;
+		events_num = output_arr_len - 2;
+		overflow_idx = output_arr_len - 2;
+		cycle_cnt_idx = output_arr_len - 1;
+
+		WREG32(base_reg + mmSPMU_PMCR_EL0_OFFSET, 0x41013040);
+
+		if (output && output_arr_len > 2) {
+
+			if (events_num > SPMU_MAX_COUNTERS) {
+				dev_err(hdev->dev, "too many events values for SPMU disable\n");
+				return -EINVAL;
+			}
+
+			for (i = 0 ; i < events_num ; i++) {
+				const u64 performance_counter_offset =
+					base_reg + mmSPMU_PMEVCNTR0_EL0_OFFSET + (i * 8);
+
+				output[i] = RREG32(performance_counter_offset);
+			}
+
+			output[overflow_idx] = RREG32(base_reg + mmSPMU_PMOVSSET_EL0_OFFSET);
+			output[cycle_cnt_idx] = RREG32(base_reg + mmSPMU_PMCCNTR_H_EL0_OFFSET);
+			output[cycle_cnt_idx] <<= 32;
+			output[cycle_cnt_idx] |= RREG32(base_reg + mmSPMU_PMCCNTR_L_EL0_OFFSET);
+		}
+
+		WREG32(base_reg + mmSPMU_PMOVSSET_EL0_OFFSET, 0);
+
+		/* clean pmtrc to reset value */
+		WREG32(base_reg + mmSPMU_PMTRC_OFFSET, 0x100400);
+	}
+
+	return 0;
+}
+
+int gaudi2_debug_coresight(struct hl_device *hdev, struct hl_ctx *ctx, void *data)
+{
+	struct hl_debug_params *params = data;
+	int rc = 0;
+
+	switch (params->op) {
+	case HL_DEBUG_OP_STM:
+		rc = gaudi2_config_stm(hdev, params);
+		break;
+	case HL_DEBUG_OP_ETF:
+		rc = gaudi2_config_etf(hdev, params);
+		break;
+	case HL_DEBUG_OP_ETR:
+		rc = gaudi2_config_etr(hdev, ctx, params);
+		break;
+	case HL_DEBUG_OP_FUNNEL:
+		rc = gaudi2_config_funnel(hdev, params);
+		break;
+	case HL_DEBUG_OP_BMON:
+		rc = gaudi2_config_bmon(hdev, params);
+		break;
+	case HL_DEBUG_OP_SPMU:
+		rc = gaudi2_config_spmu(hdev, params);
+		break;
+	case HL_DEBUG_OP_TIMESTAMP:
+		/* Do nothing as this opcode is deprecated */
+		break;
+	default:
+		dev_err(hdev->dev, "Unknown coresight id %d\n", params->op);
+		return -EINVAL;
+	}
+
+	return rc;
+}
+
+void gaudi2_halt_coresight(struct hl_device *hdev, struct hl_ctx *ctx)
+{
+	struct hl_debug_params params = {};
+	int i, rc;
+
+	/* in pldm attempting to access stubbed etfs can cause problems */
+	if (!hdev->pldm)
+		for (i = GAUDI2_ETF_FIRST ; i <= GAUDI2_ETF_LAST ; i++) {
+			params.reg_idx = i;
+			rc = gaudi2_config_etf(hdev, &params);
+			if (rc)
+				dev_err(hdev->dev, "halt ETF failed, %d/%d\n", rc, i);
+		}
+
+	rc = gaudi2_config_etr(hdev, ctx, &params);
+	if (rc)
+		dev_err(hdev->dev, "halt ETR failed, %d\n", rc);
+}
+
+
+static int gaudi2_coresight_set_disabled_components(struct hl_device *hdev, u32 unit_count,
+					u32 enabled_mask,
+					const struct component_config_offsets *binning_table)
+{
+	u32 component_idx = 0;
+	u32 disabled_mask;
+	u32 full_mask;
+
+	/* in case no unit - no need to do work */
+	if (!unit_count)
+		return 0;
+
+	full_mask = GENMASK(unit_count - 1, 0);
+
+	/* set the disable bits on disabled mask */
+	disabled_mask = (~enabled_mask) & full_mask;
+
+	while (disabled_mask) {
+		u32 component_mask = 1 << component_idx;
+
+		if (component_idx >= unit_count) {
+			dev_err(hdev->dev, "index is out of range index(%u) >= units_count(%u)\n",
+				component_idx, unit_count);
+			return -EINVAL;
+		}
+
+		/*
+		 * in case mask is set, driver need to set to 0x0
+		 * all offsets for the following structures in the appropriate indices:
+		 * debug_funnel_regs - offsets for all cs_dbg FUNNELs
+		 * debug_etf_regs - offsets for all cs_dbg ETFs
+		 * debug_stm_regs - offsets for all cs_dbg STMs
+		 * debug_spmu_regs - offsets for all cs_dbg SPMUs
+		 * debug_bmon_regs - offsets for all cs_dbg BMONs
+		 * when value is set to COMPONENT_ID_INVALID -
+		 * it means there is no such register for current component.
+		 */
+
+		if (disabled_mask & component_mask) {
+			u32 bmon_idx;
+			const struct component_config_offsets *binned_component =
+				&(binning_table[component_idx]);
+
+			if (binned_component->funnel_id != COMPONENT_ID_INVALID)
+				debug_funnel_regs[binned_component->funnel_id] = 0x0;
+
+			if (binned_component->etf_id != COMPONENT_ID_INVALID)
+				debug_etf_regs[binned_component->etf_id] = 0x0;
+
+			if (binned_component->stm_id != COMPONENT_ID_INVALID)
+				debug_stm_regs[binned_component->stm_id] = 0x0;
+
+			if (binned_component->spmu_id != COMPONENT_ID_INVALID)
+				debug_spmu_regs[binned_component->spmu_id] = 0x0;
+
+			for (bmon_idx = 0; bmon_idx < binned_component->bmon_count; bmon_idx++)
+				debug_bmon_regs[binned_component->bmon_ids[bmon_idx]] = 0x0;
+
+			/*
+			 * reset enabled bit
+			 */
+			disabled_mask &= ~component_mask;
+		}
+
+		component_idx++;
+	}
+
+	return 0;
+}
+
+int gaudi2_coresight_init(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	int ret;
+
+	/*
+	 * Mask out all the disabled binned offsets.
+	 * so when user request to configure a binned or masked out component,
+	 * driver will ignore programming it ( happens when offset value is set to 0x0 )
+	 * this is being set in gaudi2_coresight_set_disabled_components
+	 */
+
+	/* Set TPC disable components */
+	ret = gaudi2_coresight_set_disabled_components(hdev, TPC_ID_SIZE, prop->tpc_enabled_mask,
+							tpc_binning_cfg_table);
+	if (ret) {
+		dev_err(hdev->dev, "Failed to set disabled cs_dbg units for tpc coresight\n");
+		return ret;
+	}
+
+	/* Set decoder disable components */
+	ret = gaudi2_coresight_set_disabled_components(hdev, DEC_ID_SIZE,
+					prop->decoder_enabled_mask, decoder_binning_cfg_table);
+	if (ret) {
+		dev_err(hdev->dev, "Failed to set disabled cs_dbg units for decoder coresight\n");
+		return ret;
+	}
+
+	/* Set HBM (MC0 and MC1) disable components */
+	ret = gaudi2_coresight_set_disabled_components(hdev, HBM_ID_SIZE, prop->dram_enabled_mask,
+							hbm_mc0_binning_cfg_table);
+	if (ret) {
+		dev_err(hdev->dev, "Failed to set disabled cs_dbg units for hbm mc0 coresight\n");
+		return ret;
+	}
+
+	ret = gaudi2_coresight_set_disabled_components(hdev, HBM_ID_SIZE, prop->dram_enabled_mask,
+							hbm_mc1_binning_cfg_table);
+	if (ret) {
+		dev_err(hdev->dev, "Failed to set disabled cs_dbg units for hbm mc1 coresight\n");
+		return ret;
+	}
+
+	/* Set HIF_HMMU disable components */
+	ret = gaudi2_coresight_set_disabled_components(hdev, HMMU_ID_SIZE,
+					prop->hmmu_hif_enabled_mask, hmmu_binning_cfg_table);
+	if (ret) {
+		dev_err(hdev->dev, "Failed to set disabled cs_dbg units for hmmu coresight\n");
+		return ret;
+	}
+
+	/* Set XBAR_EDGE disable components */
+	ret = gaudi2_coresight_set_disabled_components(hdev, XBAR_EDGE_ID_SIZE,
+					prop->xbar_edge_enabled_mask, xbar_edge_binning_cfg_table);
+	if (ret) {
+		dev_err(hdev->dev, "Failed to set disabled cs_dbg units for xbar_edge coresight\n");
+		return ret;
+	}
+
+	/* Set EDMA disable components */
+	ret = gaudi2_coresight_set_disabled_components(hdev, EDMA_ID_SIZE, prop->edma_enabled_mask,
+							edma_binning_cfg_table);
+	if (ret) {
+		dev_err(hdev->dev, "Failed to set disabled cs_dbg units for edma coresight\n");
+		return ret;
+	}
+
+	return 0;
+}
diff --git a/drivers/accel/habanalabs/gaudi2/gaudi2_coresight_regs.h b/drivers/accel/habanalabs/gaudi2/gaudi2_coresight_regs.h
new file mode 100644
index 000000000000..df8729286e06
--- /dev/null
+++ b/drivers/accel/habanalabs/gaudi2/gaudi2_coresight_regs.h
@@ -0,0 +1,1063 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+#ifndef GAUDI2_CORESIGHT_REGS_DRV_H_
+#define GAUDI2_CORESIGHT_REGS_DRV_H_
+
+#include "gaudi2_masks.h"
+#include "../include/gaudi2/gaudi2_coresight.h"
+#include "gaudi2P.h"
+
+/* FUNNEL Offsets - same offsets for all funnels*/
+#define mmFUNNEL_CTRL_REG_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_CTRL_REG -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_PRIORITY_CTRL_REG_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_PRIORITY_CTRL_REG -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_ITATBDATA0_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_ITATBDATA0 -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_ITATBCTR2_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_ITATBCTR2 -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_ITATBCTR1_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_ITATBCTR1 -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_ITATBCTR0_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_ITATBCTR0 -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_ITCTRL_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_ITCTRL -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_CLAIMSET_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_CLAIMSET -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_CLAIMCLR_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_CLAIMCLR -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_LOCKACCESS_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_LOCKACCESS -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_LOCKSTATUS_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_LOCKSTATUS -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_AUTHSTATUS_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_AUTHSTATUS -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_DEVID_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_DEVID -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_DEVTYPE_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_DEVTYPE -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_PIDR4_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_PIDR4 -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_PERIPHID5_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_PERIPHID5 -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_PERIPHID6_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_PERIPHID6 -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_PERIPHID7_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_PERIPHID7 -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_PIDR0_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_PIDR0 -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_PIDR1_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_PIDR1 -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_PIDR2_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_PIDR2 -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_PIDR3_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_PIDR3 -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_CID0_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_CID0 -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_CID1_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_CID1 -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_CID2_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_CID2 -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+#define mmFUNNEL_CID3_OFFSET	\
+			(mmDCORE0_TPC0_EML_FUNNEL_CID3 -	\
+				mmDCORE0_TPC0_EML_FUNNEL_BASE)
+
+/* ETF Offsets - same offsets for all etfs */
+#define mmETF_RSZ_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_RSZ -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_STS_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_STS -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_RRD_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_RRD -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_RRP_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_RRP -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_RWP_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_RWP -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_TRG_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_TRG -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_CTL_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_CTL -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_RWD_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_RWD -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_MODE_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_MODE -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_LBUFLEVEL_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_LBUFLEVEL -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_CBUFLEVEL_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_CBUFLEVEL -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_BUFWM_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_BUFWM -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_FFSR_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_FFSR -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_FFCR_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_FFCR -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_PSCR_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_PSCR -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_ITATBMDATA0_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_ITATBMDATA0 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_ITATBMCTR2_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_ITATBMCTR2 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_ITATBMCTR1_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_ITATBMCTR1 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_ITATBMCTR0_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_ITATBMCTR0 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_ITMISCOP0_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_ITMISCOP0 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_ITTRFLIN_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_ITTRFLIN -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_ITATBDATA0_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_ITATBDATA0 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_ITATBCTR2_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_ITATBCTR2 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_ITATBCTR1_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_ITATBCTR1 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_ITATBCTR0_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_ITATBCTR0 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_ITCTRL_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_ITCTRL -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_CLAIMSET_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_CLAIMSET -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_CLAIMCLR_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_CLAIMCLR -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_LAR_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_LAR -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_LSR_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_LSR -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_AUTHSTATUS_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_AUTHSTATUS -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_DEVID_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_DEVID -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_DEVTYPE_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_DEVTYPE -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_PERIPHID4_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_PERIPHID4 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_PERIPHID5_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_PERIPHID5 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_PERIPHID6_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_PERIPHID6 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_PERIPHID7_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_PERIPHID7 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_PERIPHID0_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_PERIPHID0 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_PERIPHID1_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_PERIPHID1 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_PERIPHID2_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_PERIPHID2 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_PERIPHID3_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_PERIPHID3 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_COMPID0_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_COMPID0 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_COMPID1_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_COMPID1 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_COMPID2_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_COMPID2 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+#define mmETF_COMPID3_OFFSET	\
+			(mmDCORE0_TPC0_EML_ETF_COMPID3 -	\
+				mmDCORE0_TPC0_EML_ETF_BASE)
+
+
+/* STM OFFSETS - same offsets for all stms */
+#define mmSTM_STMDMASTARTR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMDMASTARTR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMDMASTOPR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMDMASTOPR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMDMASTATR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMDMASTATR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMDMACTLR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMDMACTLR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMDMAIDR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMDMAIDR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMHEER_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMHEER -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMHETER_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMHETER -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMHEBSR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMHEBSR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMHEMCR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMHEMCR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMHEEXTMUXR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMHEEXTMUXR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMHEMASTR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMHEMASTR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMHEFEAT1R_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMHEFEAT1R -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMHEIDR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMHEIDR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMSPER_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMSPER -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMSPTER_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMSPTER -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMSPSCR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMSPSCR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMSPMSCR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMSPMSCR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMSPOVERRIDER_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMSPOVERRIDER -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMSPMOVERRIDER_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMSPMOVERRIDER -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMSPTRIGCSR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMSPTRIGCSR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMTCSR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMTCSR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMTSSTIMR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMTSSTIMR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMTSFREQR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMTSFREQR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMSYNCR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMSYNCR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMAUXCR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMAUXCR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMFEAT1R_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMFEAT1R -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMFEAT2R_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMFEAT2R -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMFEAT3R_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMFEAT3R -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMITTRIGGER_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMITTRIGGER -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMITATBDATA0_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMITATBDATA0 -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMITATBCTR2_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMITATBCTR2 -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMITATBID_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMITATBID -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMITATBCTR0_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMITATBCTR0 -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMITCTRL_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMITCTRL -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMCLAIMSET_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMCLAIMSET -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMCLAIMCLR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMCLAIMCLR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMLAR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMLAR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMLSR_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMLSR -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMAUTHSTATUS_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMAUTHSTATUS -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMDEVARCH_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMDEVARCH -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMDEVID_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMDEVID -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMDEVTYPE_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMDEVTYPE -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMPIDR4_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMPIDR4 -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMPIDR5_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMPIDR5 -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMPIDR6_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMPIDR6 -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMPIDR7_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMPIDR7 -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMPIDR0_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMPIDR0 -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMPIDR1_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMPIDR1 -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMPIDR2_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMPIDR2 -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMPIDR3_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMPIDR3 -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMCIDR0_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMCIDR0 -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMCIDR1_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMCIDR1 -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMCIDR2_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMCIDR2 -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+#define mmSTM_STMCIDR3_OFFSET	\
+			(mmDCORE0_TPC0_EML_STM_STMCIDR3 -	\
+				mmDCORE0_TPC0_EML_STM_BASE)
+
+
+/* SPMU OFFSETS - same offsets for all SPMUs */
+#define mmSPMU_PMEVCNTR0_EL0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMEVCNTR0_EL0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMEVCNTR1_EL0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMEVCNTR1_EL0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMEVCNTR2_EL0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMEVCNTR2_EL0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMEVCNTR3_EL0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMEVCNTR3_EL0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMEVCNTR4_EL0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMEVCNTR4_EL0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMEVCNTR5_EL0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMEVCNTR5_EL0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMCCNTR_L_EL0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMCCNTR_L_EL0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMCCNTR_H_EL0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMCCNTR_H_EL0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMTRC_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMTRC -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_TRC_CTRL_HOST_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_TRC_CTRL_HOST -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_TRC_STAT_HOST_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_TRC_STAT_HOST -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_TRC_EN_HOST_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_TRC_EN_HOST -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMEVTYPER0_EL0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMEVTYPER0_EL0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMEVTYPER1_EL0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMEVTYPER1_EL0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMEVTYPER2_EL0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMEVTYPER2_EL0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMEVTYPER3_EL0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMEVTYPER3_EL0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMEVTYPER4_EL0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMEVTYPER4_EL0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMEVTYPER5_EL0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMEVTYPER5_EL0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMSSR_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMSSR -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMOVSSR_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMOVSSR -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMCCNTSR_L_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMCCNTSR_L -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMCCNTSR_H_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMCCNTSR_H -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMEVCNTSR0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMEVCNTSR1_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR1 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMEVCNTSR2_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR2 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMEVCNTSR3_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR3 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMEVCNTSR4_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR4 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMEVCNTSR5_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR5 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMSCR_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMSCR -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMSRR_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMSRR -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMCNTENSET_EL0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMCNTENSET_EL0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMCNTENCLR_EL0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMCNTENCLR_EL0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMINTENSET_EL1_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMINTENSET_EL1 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMINTENCLR_EL1_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMINTENCLR_EL1 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMOVSCLR_EL0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMOVSCLR_EL0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMSWINC_EL0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMSWINC_EL0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMOVSSET_EL0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMOVSSET_EL0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMCFGR_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMCFGR -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMCR_EL0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMCR_EL0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMITCTRL_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMITCTRL -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMCLAIMSET_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMCLAIMSET -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMCLAIMCLR_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMCLAIMCLR -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMDEVAFF0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMDEVAFF0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMDEVAFF1_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMDEVAFF1 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMLAR_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMLAR -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMLSR_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMLSR -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMAUTHSTATUS_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMAUTHSTATUS -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMDEVARCH_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMDEVARCH -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMDEVID2_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMDEVID2 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMDEVID1_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMDEVID1 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMDEVID_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMDEVID -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMDEVTYPE_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMDEVTYPE -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMPIDR4_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMPIDR4 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMPIDR5_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMPIDR5 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMPIDR6_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMPIDR6 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMPIDR7_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMPIDR7 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMPIDR0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMPIDR0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMPIDR1_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMPIDR1 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMPIDR2_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMPIDR2 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMPIDR3_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMPIDR3 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMCIDR0_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMCIDR0 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMCIDR1_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMCIDR1 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMCIDR2_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMCIDR2 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+#define mmSPMU_PMCIDR3_OFFSET	\
+			(mmDCORE0_TPC0_EML_SPMU_PMCIDR3 -	\
+				mmDCORE0_TPC0_EML_SPMU_BASE)
+
+
+/* BMON OFFSETS - same offsets for all BMONs*/
+#define mmBMON_CR_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_CR -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_RESET_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_REG_RESET -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_INT_CLR_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_INT_CLR -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_TRIG_TH_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_TRIG_TH -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ADDRL_S0_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S0 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ADDRH_S0_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S0 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ADDRL_E0_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_E0 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ADDRH_E0_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_E0 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ADDRL_S1_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S1 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ADDRH_S1_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S1 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ADDRL_E1_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_E1 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ADDRH_E1_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_E1 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ADDRL_S2_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S2 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ADDRH_S2_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S2 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ADDRL_E2_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_E2 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ADDRH_E2_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_E2 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ADDRL_S3_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S3 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ADDRH_S3_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S3 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ADDRL_E3_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_E3 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ADDRH_E3_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_E3 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_REDUCTION_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_REDUCTION -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_IDL_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_IDL -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_IDH_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_IDH -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_IDENL_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_IDENL -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_IDENH_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_IDENH -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_LATENCY_SMP_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_LATENCY_SMP -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ATTR_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ATTR -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ATTREN_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ATTREN -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_USRENL_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_USRENL -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_USRL_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_USRL -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_USRENH_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_USRENH -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_USRH_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_USRH -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_CAPTURE_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_CAPTURE -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_RELEASE_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_RELEASE -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_WIN_CAPTURE_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_WIN_CAPTURE -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_BW_WIN_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_BW_WIN -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_MATCH_CNT_SOD_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_MATCH_CNT_SOD -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_MATCH_CNT_WIN_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_MATCH_CNT_WIN -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_CYCCNT_L_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_CYCCNT_L -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_CYCCNT_H_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_CYCCNT_H -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_MAXLAT_SOD_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_MAXLAT_SOD -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_MINLAT_SOD_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_MINLAT_SOD -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_MAXBW_SOD_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_MAXBW_SOD -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_MINBW_SOD_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_MINBW_SOD -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_MAXOS_SOD_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_MAXOS_SOD -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_MINOS_SOD_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_MINOS_SOD -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ADDRL_SNAPSHOT_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_SNAPSHOT -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ADDRH_SNAPSHOT_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_SNAPSHOT -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_IDL_SNAPSHOT_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_IDL_SNAPSHOT -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_IDH_SNAPSHOT_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_IDH_SNAPSHOT -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_ATTR_SNAPSHOT_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_ATTR_SNAPSHOT -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_STM_TRC_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_STM_TRC -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_STM_TRC_DROP_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_STM_TRC_DROP -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_DEVARCH_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_DEVARCH -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_PMDEVID2_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_PMDEVID2 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_PMDEVID1_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_PMDEVID1 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_PMDEVID_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_PMDEVID -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_DEVTYPE_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_DEVTYPE -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_PIDR4_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_PIDR4 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_PIDR5_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_PIDR5 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_PIDR6_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_PIDR6 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_PIDR7_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_PIDR7 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_PIDR0_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_PIDR0 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_PIDR1_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_PIDR1 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_PIDR2_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_PIDR2 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_PIDR3_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_PIDR3 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_CIDR0_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_CIDR0 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_CIDR1_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_CIDR1 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_CIDR2_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_CIDR2 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+#define mmBMON_CIDR3_OFFSET	\
+			(mmDCORE0_TPC0_EML_BUSMON_0_CIDR3 -	\
+				mmDCORE0_TPC0_EML_BUSMON_0_BASE)
+
+
+/* Coresight unlock offset */
+#define  mmCORESIGHT_UNLOCK_REGISTER_OFFSET mmSTM_STMLAR_OFFSET
+#define  mmCORESIGHT_UNLOCK_STATUS_REGISTER_OFFSET mmSTM_STMLSR_OFFSET
+
+#endif /* GAUDI2_CORESIGHT_REGS_DRV_H_ */
diff --git a/drivers/accel/habanalabs/gaudi2/gaudi2_masks.h b/drivers/accel/habanalabs/gaudi2/gaudi2_masks.h
new file mode 100644
index 000000000000..e6664c4a2cf5
--- /dev/null
+++ b/drivers/accel/habanalabs/gaudi2/gaudi2_masks.h
@@ -0,0 +1,161 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2022 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+#ifndef GAUDI2_MASKS_H_
+#define GAUDI2_MASKS_H_
+
+#include "../include/gaudi2/asic_reg/gaudi2_regs.h"
+
+/* Useful masks for bits in various registers */
+#define QMAN_GLBL_ERR_CFG_MSG_EN_MASK	\
+	((0xF << PDMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \
+	(0x1F << PDMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \
+	(0x1F << PDMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT))
+
+#define QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK	\
+	((0xF << PDMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \
+	(0x1F << PDMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \
+	(0x1F << PDMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT) | \
+	(0x1 << PDMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT))
+
+#define QMAN_GLBL_ERR_CFG1_MSG_EN_MASK	\
+	(0x1 << PDMA0_QM_GLBL_ERR_CFG1_CQF_ERR_MSG_EN_SHIFT)
+
+#define QMAN_GLBL_ERR_CFG1_STOP_ON_ERR_EN_MASK	\
+	((0x1 << PDMA0_QM_GLBL_ERR_CFG1_CQF_STOP_ON_ERR_SHIFT) | \
+	(0x1 << PDMA0_QM_GLBL_ERR_CFG1_ARC_STOP_ON_ERR_SHIFT))
+
+#define QM_PQC_LBW_WDATA	\
+	((1 << DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_VAL_SHIFT) | \
+	(1 << DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_INC_SHIFT))
+
+#define QMAN_MAKE_TRUSTED	\
+	((0xF << PDMA0_QM_GLBL_PROT_PQF_SHIFT) | \
+	(0x1 << PDMA0_QM_GLBL_PROT_ERR_SHIFT) | \
+	(0x1 << PDMA0_QM_GLBL_PROT_PQC_SHIFT))
+
+#define QMAN_MAKE_TRUSTED_TEST_MODE	\
+	((0xF << PDMA0_QM_GLBL_PROT_PQF_SHIFT) | \
+	(0xF << PDMA0_QM_GLBL_PROT_CQF_SHIFT) | \
+	(0xF << PDMA0_QM_GLBL_PROT_CP_SHIFT) | \
+	(0x1 << PDMA0_QM_GLBL_PROT_ERR_SHIFT) | \
+	(0x1 << PDMA0_QM_GLBL_PROT_PQC_SHIFT))
+
+#define QMAN_ENABLE		\
+	((0xF << PDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \
+	(0x1F << PDMA0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \
+	(0x1F << PDMA0_QM_GLBL_CFG0_CP_EN_SHIFT)  | \
+	(0x1 << PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_SHIFT))
+
+#define PDMA0_QMAN_ENABLE	\
+	((0x3 << PDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \
+	(0x1F << PDMA0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \
+	(0x1F << PDMA0_QM_GLBL_CFG0_CP_EN_SHIFT)  | \
+	(0x1 << PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_SHIFT))
+
+#define PDMA1_QMAN_ENABLE	\
+	((0x1 << PDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \
+	(0x1F << PDMA0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \
+	(0x1F << PDMA0_QM_GLBL_CFG0_CP_EN_SHIFT)  | \
+	(0x1 << PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_SHIFT))
+
+/* QM_IDLE_MASK is valid for all engines QM idle check */
+#define QM_IDLE_MASK	(DCORE0_EDMA0_QM_GLBL_STS0_PQF_IDLE_MASK | \
+			DCORE0_EDMA0_QM_GLBL_STS0_CQF_IDLE_MASK | \
+			DCORE0_EDMA0_QM_GLBL_STS0_CP_IDLE_MASK)
+
+#define QM_ARC_IDLE_MASK	DCORE0_EDMA0_QM_GLBL_STS1_ARC_CQF_IDLE_MASK
+
+#define MME_ARCH_IDLE_MASK	\
+			(DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_EMPTY_MASK | \
+			DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_SM_IDLE_MASK | \
+			DCORE0_MME_CTRL_LO_ARCH_STATUS_WBC_AXI_IDLE_MASK | \
+			DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_AXI_IDLE_MASK | \
+			DCORE0_MME_CTRL_LO_ARCH_STATUS_QM_IDLE_MASK | \
+			DCORE0_MME_CTRL_LO_ARCH_STATUS_QM_RDY_MASK)
+
+#define TPC_IDLE_MASK	(DCORE0_TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_MASK | \
+			DCORE0_TPC0_CFG_STATUS_IQ_EMPTY_MASK | \
+			DCORE0_TPC0_CFG_STATUS_SB_EMPTY_MASK | \
+			DCORE0_TPC0_CFG_STATUS_QM_IDLE_MASK | \
+			DCORE0_TPC0_CFG_STATUS_QM_RDY_MASK)
+
+#define DCORE0_TPC0_QM_CGM_STS_AGENT_IDLE_MASK 0x100
+
+#define DCORE0_TPC0_EML_CFG_DBG_CNT_DBG_EXIT_MASK 0x40
+
+/* CGM_IDLE_MASK is valid for all engines CGM idle check */
+#define CGM_IDLE_MASK	DCORE0_TPC0_QM_CGM_STS_AGENT_IDLE_MASK
+
+#define QM_GLBL_CFG1_PQF_STOP		PDMA0_QM_GLBL_CFG1_PQF_STOP_MASK
+#define QM_GLBL_CFG1_CQF_STOP		PDMA0_QM_GLBL_CFG1_CQF_STOP_MASK
+#define QM_GLBL_CFG1_CP_STOP		PDMA0_QM_GLBL_CFG1_CP_STOP_MASK
+#define QM_GLBL_CFG1_PQF_FLUSH		PDMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK
+#define QM_GLBL_CFG1_CQF_FLUSH		PDMA0_QM_GLBL_CFG1_CQF_FLUSH_MASK
+#define QM_GLBL_CFG1_CP_FLUSH		PDMA0_QM_GLBL_CFG1_CP_FLUSH_MASK
+
+#define QM_GLBL_CFG2_ARC_CQF_STOP	PDMA0_QM_GLBL_CFG2_ARC_CQF_STOP_MASK
+#define QM_GLBL_CFG2_ARC_CQF_FLUSH	PDMA0_QM_GLBL_CFG2_ARC_CQF_FLUSH_MASK
+
+#define QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK                            0x1
+#define QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK                            0x2
+#define QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK                           0x4
+
+#define QM_ARB_ERR_MSG_EN_MASK		(\
+					QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK |\
+					QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK |\
+					QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK)
+
+#define PCIE_AUX_FLR_CTRL_HW_CTRL_MASK		0x1
+#define PCIE_AUX_FLR_CTRL_INT_MASK_MASK		0x2
+
+#define MME_ACC_INTR_MASK_WBC_ERR_RESP_MASK		GENMASK(1, 0)
+#define MME_ACC_INTR_MASK_AP_SRC_POS_INF_MASK		BIT(2)
+#define MME_ACC_INTR_MASK_AP_SRC_NEG_INF_MASK		BIT(3)
+#define MME_ACC_INTR_MASK_AP_SRC_NAN_MASK		BIT(4)
+#define MME_ACC_INTR_MASK_AP_RESULT_POS_INF_MASK	BIT(5)
+#define MME_ACC_INTR_MASK_AP_RESULT_NEG_INF_MASK	BIT(6)
+
+#define SM_CQ_L2H_MASK_VAL		0xFFFFFFFFFC000000ull
+#define SM_CQ_L2H_CMPR_VAL		0x1000007FFC000000ull
+#define SM_CQ_L2H_LOW_MASK		GENMASK(31, 20)
+#define SM_CQ_L2H_LOW_SHIFT		20
+
+#define MMU_STATIC_MULTI_PAGE_SIZE_HOP4_PAGE_SIZE_MASK \
+	REG_FIELD_MASK(DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE, HOP4_PAGE_SIZE)
+#define STLB_HOP_CONFIGURATION_ONLY_LARGE_PAGE_MASK \
+	REG_FIELD_MASK(DCORE0_HMMU0_STLB_HOP_CONFIGURATION, ONLY_LARGE_PAGE)
+
+#define AXUSER_HB_SEC_ASID_MASK                0x3FF
+#define AXUSER_HB_SEC_MMBP_MASK                0x400
+
+#define MMUBP_ASID_MASK	(AXUSER_HB_SEC_ASID_MASK | AXUSER_HB_SEC_MMBP_MASK)
+
+#define ROT_MSS_HALT_WBC_MASK	BIT(0)
+#define ROT_MSS_HALT_RSB_MASK	BIT(1)
+#define ROT_MSS_HALT_MRSB_MASK	BIT(2)
+
+#define PCIE_DBI_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_SHIFT	0
+#define PCIE_DBI_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_MASK	0x1
+
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_SIGN_SHIFT	15
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_SIGN_MASK		0x8000
+
+#define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_AXI_ERR_INTR_SHIFT		0
+#define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_AXI_ERR_INTR_MASK		0x1
+#define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_AXI_LBW_ERR_INTR_SHIFT		1
+#define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_AXI_LBW_ERR_INTR_MASK		0x2
+#define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_BAD_ACCESS_INTR_SHIFT		2
+#define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_BAD_ACCESS_INTR_MASK		0x4
+#define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_AXI_ERR_INTR_MASK_SHIFT		3
+#define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_AXI_ERR_INTR_MASK_MASK		0x8
+#define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_AXI_LBW_ERR_INTR_MASK_SHIFT	4
+#define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_AXI_LBW_ERR_INTR_MASK_MASK	0x10
+#define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_BAD_ACCESS_INTR_MASK_SHIFT	5
+#define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_BAD_ACCESS_INTR_MASK_MASK	0x20
+
+#endif /* GAUDI2_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/gaudi2/gaudi2_security.c b/drivers/accel/habanalabs/gaudi2/gaudi2_security.c
new file mode 100644
index 000000000000..307ccb912ccd
--- /dev/null
+++ b/drivers/accel/habanalabs/gaudi2/gaudi2_security.c
@@ -0,0 +1,3873 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Copyright 2020-2022 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ */
+
+#include "gaudi2P.h"
+#include "../include/gaudi2/asic_reg/gaudi2_regs.h"
+
+#define UNSET_GLBL_SEC_BIT(array, b) ((array)[((b) / 32)] |= (1 << ((b) % 32)))
+
+#define SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD_MASK
+#define SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD_MASK
+#define SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR_MASK
+#define SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR_MASK
+#define SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR_MASK
+#define SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD \
+		PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD_MASK
+#define SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR \
+		PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR_MASK
+#define SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR \
+		PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR_MASK
+
+/* LBW RR */
+#define SFT_NUM_OF_LBW_RTR		1
+#define SFT_LBW_RTR_OFFSET		0
+#define RR_LBW_LONG_MASK		0x7FFFFFFull
+#define RR_LBW_SHORT_MASK		0x7FFF000ull
+
+/* HBW RR */
+#define SFT_NUM_OF_HBW_RTR		2
+#define RR_HBW_SHORT_LO_MASK		0xFFFFFFFF000ull
+#define RR_HBW_SHORT_HI_MASK		0xF00000000000ull
+#define RR_HBW_LONG_LO_MASK		0xFFFFFFFF000ull
+#define RR_HBW_LONG_HI_MASK		0xFFFFF00000000000ull
+
+struct rr_config {
+	u64 min;
+	u64 max;
+	u32 index;
+	u8 type;
+};
+
+struct gaudi2_atypical_bp_blocks {
+	u32 mm_block_base_addr;
+	u32 block_size;
+	u32 glbl_sec_offset;
+	u32 glbl_sec_length;
+};
+
+static const struct gaudi2_atypical_bp_blocks gaudi2_pb_dcr0_sm_objs = {
+	mmDCORE0_SYNC_MNGR_OBJS_BASE,
+	128 * 1024,
+	SM_OBJS_PROT_BITS_OFFS,
+	640
+};
+
+static const u32 gaudi2_pb_sft0[] = {
+	mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE,
+	mmSFT0_HBW_RTR_IF0_RTR_H3_BASE,
+	mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE,
+	mmSFT0_HBW_RTR_IF0_ADDR_DEC_HBW_BASE,
+	mmSFT0_HBW_RTR_IF1_RTR_CTRL_BASE,
+	mmSFT0_HBW_RTR_IF1_RTR_H3_BASE,
+	mmSFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE,
+	mmSFT0_HBW_RTR_IF1_ADDR_DEC_HBW_BASE,
+	mmSFT0_LBW_RTR_IF_RTR_CTRL_BASE,
+	mmSFT0_LBW_RTR_IF_RTR_H3_BASE,
+	mmSFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE,
+	mmSFT0_LBW_RTR_IF_ADDR_DEC_HBW_BASE,
+	mmSFT0_BASE,
+};
+
+static const u32 gaudi2_pb_dcr0_hif[] = {
+	mmDCORE0_HIF0_BASE,
+};
+
+static const u32 gaudi2_pb_dcr0_rtr0[] = {
+	mmDCORE0_RTR0_CTRL_BASE,
+	mmDCORE0_RTR0_H3_BASE,
+	mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE,
+	mmDCORE0_RTR0_ADD_DEC_HBW_BASE,
+	mmDCORE0_RTR0_BASE,
+	mmDCORE0_RTR0_DBG_ADDR_BASE,
+};
+
+static const u32 gaudi2_pb_dcr0_hmmu0[] = {
+	mmDCORE0_HMMU0_MMU_BASE,
+	mmDCORE0_HMMU0_MSTR_IF_RR_SHRD_HBW_BASE,
+	mmDCORE0_HMMU0_SCRAMB_OUT_BASE,
+	mmDCORE0_HMMU0_STLB_BASE,
+};
+
+static const u32 gaudi2_pb_cpu_if[] = {
+	mmCPU_IF_BASE,
+};
+
+static const u32 gaudi2_pb_cpu[] = {
+	mmCPU_CA53_CFG_BASE,
+	mmCPU_MSTR_IF_RR_SHRD_HBW_BASE,
+};
+
+static const u32 gaudi2_pb_kdma[] = {
+	mmARC_FARM_KDMA_BASE,
+	mmARC_FARM_KDMA_MSTR_IF_RR_SHRD_HBW_BASE,
+};
+
+static const u32 gaudi2_pb_pdma0[] = {
+	mmPDMA0_CORE_BASE,
+	mmPDMA0_MSTR_IF_RR_SHRD_HBW_BASE,
+	mmPDMA0_QM_BASE,
+};
+
+static const u32 gaudi2_pb_pdma0_arc[] = {
+	mmPDMA0_QM_ARC_AUX_BASE,
+};
+
+static const struct range gaudi2_pb_pdma0_arc_unsecured_regs[] = {
+	{mmPDMA0_QM_ARC_AUX_RUN_HALT_REQ, mmPDMA0_QM_ARC_AUX_RUN_HALT_ACK},
+	{mmPDMA0_QM_ARC_AUX_CLUSTER_NUM, mmPDMA0_QM_ARC_AUX_WAKE_UP_EVENT},
+	{mmPDMA0_QM_ARC_AUX_ARC_RST_REQ, mmPDMA0_QM_ARC_AUX_CID_OFFSET_7},
+	{mmPDMA0_QM_ARC_AUX_SCRATCHPAD_0, mmPDMA0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT},
+	{mmPDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN, mmPDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN},
+	{mmPDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN, mmPDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN},
+	{mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0, mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG},
+	{mmPDMA0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT, mmPDMA0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI},
+	{mmPDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT, mmPDMA0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN},
+};
+
+static const u32 gaudi2_pb_pdma0_unsecured_regs[] = {
+	mmPDMA0_CORE_CTX_AXUSER_HB_WR_REDUCTION,
+	mmPDMA0_CORE_CTX_WR_COMP_ADDR_HI,
+	mmPDMA0_CORE_CTX_WR_COMP_ADDR_LO,
+	mmPDMA0_CORE_CTX_WR_COMP_WDATA,
+	mmPDMA0_CORE_CTX_SRC_BASE_LO,
+	mmPDMA0_CORE_CTX_SRC_BASE_HI,
+	mmPDMA0_CORE_CTX_DST_BASE_LO,
+	mmPDMA0_CORE_CTX_DST_BASE_HI,
+	mmPDMA0_CORE_CTX_SRC_TSIZE_0,
+	mmPDMA0_CORE_CTX_SRC_TSIZE_1,
+	mmPDMA0_CORE_CTX_SRC_TSIZE_2,
+	mmPDMA0_CORE_CTX_SRC_TSIZE_3,
+	mmPDMA0_CORE_CTX_SRC_TSIZE_4,
+	mmPDMA0_CORE_CTX_SRC_STRIDE_1,
+	mmPDMA0_CORE_CTX_SRC_STRIDE_2,
+	mmPDMA0_CORE_CTX_SRC_STRIDE_3,
+	mmPDMA0_CORE_CTX_SRC_STRIDE_4,
+	mmPDMA0_CORE_CTX_SRC_OFFSET_LO,
+	mmPDMA0_CORE_CTX_SRC_OFFSET_HI,
+	mmPDMA0_CORE_CTX_DST_TSIZE_0,
+	mmPDMA0_CORE_CTX_DST_TSIZE_1,
+	mmPDMA0_CORE_CTX_DST_TSIZE_2,
+	mmPDMA0_CORE_CTX_DST_TSIZE_3,
+	mmPDMA0_CORE_CTX_DST_TSIZE_4,
+	mmPDMA0_CORE_CTX_DST_STRIDE_1,
+	mmPDMA0_CORE_CTX_DST_STRIDE_2,
+	mmPDMA0_CORE_CTX_DST_STRIDE_3,
+	mmPDMA0_CORE_CTX_DST_STRIDE_4,
+	mmPDMA0_CORE_CTX_DST_OFFSET_LO,
+	mmPDMA0_CORE_CTX_DST_OFFSET_HI,
+	mmPDMA0_CORE_CTX_COMMIT,
+	mmPDMA0_CORE_CTX_CTRL,
+	mmPDMA0_CORE_CTX_TE_NUMROWS,
+	mmPDMA0_CORE_CTX_IDX,
+	mmPDMA0_CORE_CTX_IDX_INC,
+	mmPDMA0_QM_CQ_CFG0_0,
+	mmPDMA0_QM_CQ_CFG0_1,
+	mmPDMA0_QM_CQ_CFG0_2,
+	mmPDMA0_QM_CQ_CFG0_3,
+	mmPDMA0_QM_CQ_CFG0_4,
+	mmPDMA0_QM_CP_FENCE0_RDATA_0,
+	mmPDMA0_QM_CP_FENCE0_RDATA_1,
+	mmPDMA0_QM_CP_FENCE0_RDATA_2,
+	mmPDMA0_QM_CP_FENCE0_RDATA_3,
+	mmPDMA0_QM_CP_FENCE0_RDATA_4,
+	mmPDMA0_QM_CP_FENCE1_RDATA_0,
+	mmPDMA0_QM_CP_FENCE1_RDATA_1,
+	mmPDMA0_QM_CP_FENCE1_RDATA_2,
+	mmPDMA0_QM_CP_FENCE1_RDATA_3,
+	mmPDMA0_QM_CP_FENCE1_RDATA_4,
+	mmPDMA0_QM_CP_FENCE2_RDATA_0,
+	mmPDMA0_QM_CP_FENCE2_RDATA_1,
+	mmPDMA0_QM_CP_FENCE2_RDATA_2,
+	mmPDMA0_QM_CP_FENCE2_RDATA_3,
+	mmPDMA0_QM_CP_FENCE2_RDATA_4,
+	mmPDMA0_QM_CP_FENCE3_RDATA_0,
+	mmPDMA0_QM_CP_FENCE3_RDATA_1,
+	mmPDMA0_QM_CP_FENCE3_RDATA_2,
+	mmPDMA0_QM_CP_FENCE3_RDATA_3,
+	mmPDMA0_QM_CP_FENCE3_RDATA_4,
+	mmPDMA0_QM_CP_FENCE0_CNT_0,
+	mmPDMA0_QM_CP_FENCE0_CNT_1,
+	mmPDMA0_QM_CP_FENCE0_CNT_2,
+	mmPDMA0_QM_CP_FENCE0_CNT_3,
+	mmPDMA0_QM_CP_FENCE0_CNT_4,
+	mmPDMA0_QM_CP_FENCE1_CNT_0,
+	mmPDMA0_QM_CP_FENCE1_CNT_1,
+	mmPDMA0_QM_CP_FENCE1_CNT_2,
+	mmPDMA0_QM_CP_FENCE1_CNT_3,
+	mmPDMA0_QM_CP_FENCE1_CNT_4,
+	mmPDMA0_QM_CP_FENCE2_CNT_0,
+	mmPDMA0_QM_CP_FENCE2_CNT_1,
+	mmPDMA0_QM_CP_FENCE2_CNT_2,
+	mmPDMA0_QM_CP_FENCE2_CNT_3,
+	mmPDMA0_QM_CP_FENCE2_CNT_4,
+	mmPDMA0_QM_CP_FENCE3_CNT_0,
+	mmPDMA0_QM_CP_FENCE3_CNT_1,
+	mmPDMA0_QM_CP_FENCE3_CNT_2,
+	mmPDMA0_QM_CP_FENCE3_CNT_3,
+	mmPDMA0_QM_CP_FENCE3_CNT_4,
+	mmPDMA0_QM_CQ_PTR_LO_0,
+	mmPDMA0_QM_CQ_PTR_HI_0,
+	mmPDMA0_QM_CQ_TSIZE_0,
+	mmPDMA0_QM_CQ_CTL_0,
+	mmPDMA0_QM_CQ_PTR_LO_1,
+	mmPDMA0_QM_CQ_PTR_HI_1,
+	mmPDMA0_QM_CQ_TSIZE_1,
+	mmPDMA0_QM_CQ_CTL_1,
+	mmPDMA0_QM_CQ_PTR_LO_2,
+	mmPDMA0_QM_CQ_PTR_HI_2,
+	mmPDMA0_QM_CQ_TSIZE_2,
+	mmPDMA0_QM_CQ_CTL_2,
+	mmPDMA0_QM_CQ_PTR_LO_3,
+	mmPDMA0_QM_CQ_PTR_HI_3,
+	mmPDMA0_QM_CQ_TSIZE_3,
+	mmPDMA0_QM_CQ_CTL_3,
+	mmPDMA0_QM_CQ_PTR_LO_4,
+	mmPDMA0_QM_CQ_PTR_HI_4,
+	mmPDMA0_QM_CQ_TSIZE_4,
+	mmPDMA0_QM_CQ_CTL_4,
+	mmPDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE,
+	mmPDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE + 4,
+	mmPDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE,
+	mmPDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE + 4,
+	mmPDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE,
+	mmPDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE + 4,
+	mmPDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE,
+	mmPDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE + 4,
+	mmPDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE,
+	mmPDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE + 4,
+	mmPDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE,
+	mmPDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE + 4,
+	mmPDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE,
+	mmPDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE + 4,
+	mmPDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE,
+	mmPDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE + 4,
+	mmPDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE,
+	mmPDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE + 4,
+	mmPDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE,
+	mmPDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE + 4,
+	mmPDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE,
+	mmPDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE + 4,
+	mmPDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE,
+	mmPDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE + 4,
+	mmPDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE,
+	mmPDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE + 4,
+	mmPDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE,
+	mmPDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE + 4,
+	mmPDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE,
+	mmPDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE + 4,
+	mmPDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE,
+	mmPDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE + 4,
+	mmPDMA0_QM_ARC_CQ_PTR_LO,
+	mmPDMA0_QM_ARC_CQ_PTR_LO_STS,
+	mmPDMA0_QM_ARC_CQ_PTR_HI,
+	mmPDMA0_QM_ARC_CQ_PTR_HI_STS,
+	mmPDMA0_QM_ARB_CFG_0,
+	mmPDMA0_QM_ARB_MST_QUIET_PER,
+	mmPDMA0_QM_ARB_CHOICE_Q_PUSH,
+	mmPDMA0_QM_ARB_WRR_WEIGHT_0,
+	mmPDMA0_QM_ARB_WRR_WEIGHT_1,
+	mmPDMA0_QM_ARB_WRR_WEIGHT_2,
+	mmPDMA0_QM_ARB_WRR_WEIGHT_3,
+	mmPDMA0_QM_ARB_BASE_LO,
+	mmPDMA0_QM_ARB_BASE_HI,
+	mmPDMA0_QM_ARB_MST_SLAVE_EN,
+	mmPDMA0_QM_ARB_MST_SLAVE_EN_1,
+	mmPDMA0_QM_ARB_MST_CRED_INC,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_0,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_1,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_2,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_3,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_4,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_5,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_6,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_7,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_8,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_9,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_10,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_11,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_12,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_13,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_14,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_15,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_16,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_17,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_18,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_19,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_20,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_21,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_22,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_23,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_24,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_25,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_26,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_27,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_28,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_29,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_30,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_31,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_32,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_33,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_34,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_35,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_36,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_37,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_38,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_39,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_40,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_41,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_42,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_43,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_44,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_45,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_46,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_47,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_48,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_49,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_50,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_51,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_52,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_53,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_54,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_55,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_56,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_57,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_58,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_59,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_60,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_61,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_62,
+	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_63,
+	mmPDMA0_QM_ARB_SLV_ID,
+	mmPDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST,
+	mmPDMA0_QM_ARC_CQ_CFG0,
+	mmPDMA0_QM_CQ_IFIFO_CI_0,
+	mmPDMA0_QM_CQ_IFIFO_CI_1,
+	mmPDMA0_QM_CQ_IFIFO_CI_2,
+	mmPDMA0_QM_CQ_IFIFO_CI_3,
+	mmPDMA0_QM_CQ_IFIFO_CI_4,
+	mmPDMA0_QM_ARC_CQ_IFIFO_CI,
+	mmPDMA0_QM_CQ_CTL_CI_0,
+	mmPDMA0_QM_CQ_CTL_CI_1,
+	mmPDMA0_QM_CQ_CTL_CI_2,
+	mmPDMA0_QM_CQ_CTL_CI_3,
+	mmPDMA0_QM_CQ_CTL_CI_4,
+	mmPDMA0_QM_ARC_CQ_CTL_CI,
+	mmPDMA0_QM_ARC_CQ_TSIZE,
+	mmPDMA0_QM_ARC_CQ_CTL,
+	mmPDMA0_QM_CP_SWITCH_WD_SET,
+	mmPDMA0_QM_CP_EXT_SWITCH,
+	mmPDMA0_QM_CP_PRED_0,
+	mmPDMA0_QM_CP_PRED_1,
+	mmPDMA0_QM_CP_PRED_2,
+	mmPDMA0_QM_CP_PRED_3,
+	mmPDMA0_QM_CP_PRED_4,
+	mmPDMA0_QM_CP_PRED_UPEN_0,
+	mmPDMA0_QM_CP_PRED_UPEN_1,
+	mmPDMA0_QM_CP_PRED_UPEN_2,
+	mmPDMA0_QM_CP_PRED_UPEN_3,
+	mmPDMA0_QM_CP_PRED_UPEN_4,
+	mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_0,
+	mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_1,
+	mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_2,
+	mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_3,
+	mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_4,
+	mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_0,
+	mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_1,
+	mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_2,
+	mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_3,
+	mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_4,
+	mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_0,
+	mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_1,
+	mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_2,
+	mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_3,
+	mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_4,
+	mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_0,
+	mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_1,
+	mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_2,
+	mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_3,
+	mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_4,
+	mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_0,
+	mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_1,
+	mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_2,
+	mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_3,
+	mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_4,
+	mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_0,
+	mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_1,
+	mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_2,
+	mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_3,
+	mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_4,
+	mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_0,
+	mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_1,
+	mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_2,
+	mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_3,
+	mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_4,
+	mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_0,
+	mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_1,
+	mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_2,
+	mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_3,
+	mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_4,
+	mmPDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO,
+	mmPDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO,
+	mmPDMA0_QM_CQ_IFIFO_MSG_BASE_LO,
+	mmPDMA0_QM_CQ_CTL_MSG_BASE_LO
+};
+
+static const u32 gaudi2_pb_dcr0_edma0[] = {
+	mmDCORE0_EDMA0_CORE_BASE,
+	mmDCORE0_EDMA0_MSTR_IF_RR_SHRD_HBW_BASE,
+	mmDCORE0_EDMA0_QM_BASE,
+};
+
+static const u32 gaudi2_pb_dcr0_edma0_arc[] = {
+	mmDCORE0_EDMA0_QM_ARC_AUX_BASE,
+};
+
+static const struct range gaudi2_pb_dcr0_edma0_arc_unsecured_regs[] = {
+	{mmDCORE0_EDMA0_QM_ARC_AUX_RUN_HALT_REQ, mmDCORE0_EDMA0_QM_ARC_AUX_RUN_HALT_ACK},
+	{mmDCORE0_EDMA0_QM_ARC_AUX_CLUSTER_NUM, mmDCORE0_EDMA0_QM_ARC_AUX_WAKE_UP_EVENT},
+	{mmDCORE0_EDMA0_QM_ARC_AUX_ARC_RST_REQ, mmDCORE0_EDMA0_QM_ARC_AUX_CID_OFFSET_7},
+	{mmDCORE0_EDMA0_QM_ARC_AUX_SCRATCHPAD_0, mmDCORE0_EDMA0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT},
+	{mmDCORE0_EDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN,
+		mmDCORE0_EDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN},
+	{mmDCORE0_EDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN,
+		mmDCORE0_EDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN},
+	{mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0,
+		mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG},
+	{mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT,
+		mmDCORE0_EDMA0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI},
+	{mmDCORE0_EDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT,
+		mmDCORE0_EDMA0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN},
+};
+
+static const u32 gaudi2_pb_dcr0_edma0_unsecured_regs[] = {
+	mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_WR_REDUCTION,
+	mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_HI,
+	mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_LO,
+	mmDCORE0_EDMA0_CORE_CTX_WR_COMP_WDATA,
+	mmDCORE0_EDMA0_CORE_CTX_SRC_BASE_LO,
+	mmDCORE0_EDMA0_CORE_CTX_SRC_BASE_HI,
+	mmDCORE0_EDMA0_CORE_CTX_DST_BASE_LO,
+	mmDCORE0_EDMA0_CORE_CTX_DST_BASE_HI,
+	mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_0,
+	mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_1,
+	mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_2,
+	mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_3,
+	mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_4,
+	mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_1,
+	mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_2,
+	mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_3,
+	mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_4,
+	mmDCORE0_EDMA0_CORE_CTX_SRC_OFFSET_LO,
+	mmDCORE0_EDMA0_CORE_CTX_SRC_OFFSET_HI,
+	mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_0,
+	mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_1,
+	mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_2,
+	mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_3,
+	mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_4,
+	mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_1,
+	mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_2,
+	mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_3,
+	mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_4,
+	mmDCORE0_EDMA0_CORE_CTX_DST_OFFSET_LO,
+	mmDCORE0_EDMA0_CORE_CTX_DST_OFFSET_HI,
+	mmDCORE0_EDMA0_CORE_CTX_COMMIT,
+	mmDCORE0_EDMA0_CORE_CTX_CTRL,
+	mmDCORE0_EDMA0_CORE_CTX_TE_NUMROWS,
+	mmDCORE0_EDMA0_CORE_CTX_IDX,
+	mmDCORE0_EDMA0_CORE_CTX_IDX_INC,
+	mmDCORE0_EDMA0_CORE_WR_COMP_MAX_OUTSTAND,
+	mmDCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG,
+	mmDCORE0_EDMA0_QM_CQ_CFG0_0,
+	mmDCORE0_EDMA0_QM_CQ_CFG0_1,
+	mmDCORE0_EDMA0_QM_CQ_CFG0_2,
+	mmDCORE0_EDMA0_QM_CQ_CFG0_3,
+	mmDCORE0_EDMA0_QM_CQ_CFG0_4,
+	mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_0,
+	mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_1,
+	mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_2,
+	mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_3,
+	mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_4,
+	mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_0,
+	mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_1,
+	mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_2,
+	mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_3,
+	mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_4,
+	mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_0,
+	mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_1,
+	mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_2,
+	mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_3,
+	mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_4,
+	mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_0,
+	mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_1,
+	mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_2,
+	mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_3,
+	mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_4,
+	mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_0,
+	mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_1,
+	mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_2,
+	mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_3,
+	mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_4,
+	mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_0,
+	mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_1,
+	mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_2,
+	mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_3,
+	mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_4,
+	mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_0,
+	mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_1,
+	mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_2,
+	mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_3,
+	mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_4,
+	mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_0,
+	mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_1,
+	mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_2,
+	mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_3,
+	mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_4,
+	mmDCORE0_EDMA0_QM_CQ_PTR_LO_0,
+	mmDCORE0_EDMA0_QM_CQ_PTR_HI_0,
+	mmDCORE0_EDMA0_QM_CQ_TSIZE_0,
+	mmDCORE0_EDMA0_QM_CQ_CTL_0,
+	mmDCORE0_EDMA0_QM_CQ_PTR_LO_1,
+	mmDCORE0_EDMA0_QM_CQ_PTR_HI_1,
+	mmDCORE0_EDMA0_QM_CQ_TSIZE_1,
+	mmDCORE0_EDMA0_QM_CQ_CTL_1,
+	mmDCORE0_EDMA0_QM_CQ_PTR_LO_2,
+	mmDCORE0_EDMA0_QM_CQ_PTR_HI_2,
+	mmDCORE0_EDMA0_QM_CQ_TSIZE_2,
+	mmDCORE0_EDMA0_QM_CQ_CTL_2,
+	mmDCORE0_EDMA0_QM_CQ_PTR_LO_3,
+	mmDCORE0_EDMA0_QM_CQ_PTR_HI_3,
+	mmDCORE0_EDMA0_QM_CQ_TSIZE_3,
+	mmDCORE0_EDMA0_QM_CQ_CTL_3,
+	mmDCORE0_EDMA0_QM_CQ_PTR_LO_4,
+	mmDCORE0_EDMA0_QM_CQ_PTR_HI_4,
+	mmDCORE0_EDMA0_QM_CQ_TSIZE_4,
+	mmDCORE0_EDMA0_QM_CQ_CTL_4,
+	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE,
+	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE + 4,
+	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE,
+	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE + 4,
+	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE,
+	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE + 4,
+	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE,
+	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE + 4,
+	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE,
+	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE + 4,
+	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE,
+	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE + 4,
+	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE,
+	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE + 4,
+	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE,
+	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE + 4,
+	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE,
+	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE + 4,
+	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE,
+	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE + 4,
+	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE,
+	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE + 4,
+	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE,
+	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE + 4,
+	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE,
+	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE + 4,
+	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE,
+	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE + 4,
+	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE,
+	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE + 4,
+	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE,
+	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE + 4,
+	mmDCORE0_EDMA0_QM_ARC_CQ_PTR_LO,
+	mmDCORE0_EDMA0_QM_ARC_CQ_PTR_LO_STS,
+	mmDCORE0_EDMA0_QM_ARC_CQ_PTR_HI,
+	mmDCORE0_EDMA0_QM_ARC_CQ_PTR_HI_STS,
+	mmDCORE0_EDMA0_QM_ARB_CFG_0,
+	mmDCORE0_EDMA0_QM_ARB_MST_QUIET_PER,
+	mmDCORE0_EDMA0_QM_ARB_CHOICE_Q_PUSH,
+	mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_0,
+	mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_1,
+	mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_2,
+	mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_3,
+	mmDCORE0_EDMA0_QM_ARB_BASE_LO,
+	mmDCORE0_EDMA0_QM_ARB_BASE_HI,
+	mmDCORE0_EDMA0_QM_ARB_MST_SLAVE_EN,
+	mmDCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_1,
+	mmDCORE0_EDMA0_QM_ARB_MST_CRED_INC,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_0,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_1,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_2,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_3,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_4,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_5,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_6,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_7,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_8,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_9,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_10,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_11,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_12,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_13,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_14,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_15,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_16,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_17,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_18,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_19,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_20,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_21,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_22,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_23,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_24,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_25,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_26,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_27,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_28,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_29,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_30,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_31,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_32,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_33,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_34,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_35,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_36,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_37,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_38,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_39,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_40,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_41,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_42,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_43,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_44,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_45,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_46,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_47,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_48,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_49,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_50,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_51,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_52,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_53,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_54,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_55,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_56,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_57,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_58,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_59,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_60,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_61,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_62,
+	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_63,
+	mmDCORE0_EDMA0_QM_ARB_SLV_ID,
+	mmDCORE0_EDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST,
+	mmDCORE0_EDMA0_QM_ARC_CQ_CFG0,
+	mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_0,
+	mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_1,
+	mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_2,
+	mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_3,
+	mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_4,
+	mmDCORE0_EDMA0_QM_ARC_CQ_IFIFO_CI,
+	mmDCORE0_EDMA0_QM_CQ_CTL_CI_0,
+	mmDCORE0_EDMA0_QM_CQ_CTL_CI_1,
+	mmDCORE0_EDMA0_QM_CQ_CTL_CI_2,
+	mmDCORE0_EDMA0_QM_CQ_CTL_CI_3,
+	mmDCORE0_EDMA0_QM_CQ_CTL_CI_4,
+	mmDCORE0_EDMA0_QM_ARC_CQ_CTL_CI,
+	mmDCORE0_EDMA0_QM_ARC_CQ_TSIZE,
+	mmDCORE0_EDMA0_QM_ARC_CQ_CTL,
+	mmDCORE0_EDMA0_QM_CP_SWITCH_WD_SET,
+	mmDCORE0_EDMA0_QM_CP_EXT_SWITCH,
+	mmDCORE0_EDMA0_QM_CP_PRED_0,
+	mmDCORE0_EDMA0_QM_CP_PRED_1,
+	mmDCORE0_EDMA0_QM_CP_PRED_2,
+	mmDCORE0_EDMA0_QM_CP_PRED_3,
+	mmDCORE0_EDMA0_QM_CP_PRED_4,
+	mmDCORE0_EDMA0_QM_CP_PRED_UPEN_0,
+	mmDCORE0_EDMA0_QM_CP_PRED_UPEN_1,
+	mmDCORE0_EDMA0_QM_CP_PRED_UPEN_2,
+	mmDCORE0_EDMA0_QM_CP_PRED_UPEN_3,
+	mmDCORE0_EDMA0_QM_CP_PRED_UPEN_4,
+	mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_0,
+	mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_1,
+	mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_2,
+	mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_3,
+	mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_4,
+	mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_0,
+	mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_1,
+	mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_2,
+	mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_3,
+	mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_4,
+	mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_0,
+	mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_1,
+	mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_2,
+	mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_3,
+	mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_4,
+	mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_0,
+	mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_1,
+	mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_2,
+	mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_3,
+	mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_4,
+	mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_0,
+	mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_1,
+	mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_2,
+	mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_3,
+	mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_4,
+	mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_0,
+	mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_1,
+	mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_2,
+	mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_3,
+	mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_4,
+	mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_0,
+	mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_1,
+	mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_2,
+	mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_3,
+	mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_4,
+	mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_0,
+	mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_1,
+	mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_2,
+	mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_3,
+	mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_4,
+	mmDCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO,
+	mmDCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO,
+	mmDCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_LO,
+	mmDCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_LO
+};
+
+static const u32 gaudi2_pb_dcr0_mme_sbte[] = {
+	mmDCORE0_MME_SBTE0_BASE,
+	mmDCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_BASE,
+};
+
+static const u32 gaudi2_pb_dcr0_mme_qm[] = {
+	mmDCORE0_MME_QM_BASE,
+};
+
+static const u32 gaudi2_pb_dcr0_mme_eng[] = {
+	mmDCORE0_MME_ACC_BASE,
+	mmDCORE0_MME_CTRL_HI_BASE,
+	mmDCORE0_MME_CTRL_LO_BASE,
+	mmDCORE0_MME_CTRL_MSTR_IF_RR_SHRD_HBW_BASE,
+	mmDCORE0_MME_WB0_MSTR_IF_RR_SHRD_HBW_BASE,
+	mmDCORE0_MME_WB1_MSTR_IF_RR_SHRD_HBW_BASE,
+};
+
+static const u32 gaudi2_pb_dcr0_mme_arc[] = {
+	mmDCORE0_MME_QM_ARC_AUX_BASE,
+	mmDCORE0_MME_QM_ARC_DUP_ENG_BASE,
+};
+
+static const struct range gaudi2_pb_dcr0_mme_arc_unsecured_regs[] = {
+	{mmDCORE0_MME_QM_ARC_AUX_RUN_HALT_REQ, mmDCORE0_MME_QM_ARC_AUX_RUN_HALT_ACK},
+	{mmDCORE0_MME_QM_ARC_AUX_CLUSTER_NUM, mmDCORE0_MME_QM_ARC_AUX_WAKE_UP_EVENT},
+	{mmDCORE0_MME_QM_ARC_AUX_ARC_RST_REQ, mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_7},
+	{mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_0, mmDCORE0_MME_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT},
+	{mmDCORE0_MME_QM_ARC_AUX_CBU_EARLY_BRESP_EN, mmDCORE0_MME_QM_ARC_AUX_CBU_EARLY_BRESP_EN},
+	{mmDCORE0_MME_QM_ARC_AUX_LBU_EARLY_BRESP_EN, mmDCORE0_MME_QM_ARC_AUX_LBU_EARLY_BRESP_EN},
+	{mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0,
+		mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG},
+	{mmDCORE0_MME_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT,
+		mmDCORE0_MME_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI},
+	{mmDCORE0_MME_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT,
+		mmDCORE0_MME_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN},
+	{mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_0,
+		mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_63},
+	{mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_STRONG_ORDER,
+		mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_LB_OVRD},
+};
+
+static const u32 gaudi2_pb_dcr0_mme_qm_unsecured_regs[] = {
+	mmDCORE0_MME_QM_CQ_CFG0_0,
+	mmDCORE0_MME_QM_CQ_CFG0_1,
+	mmDCORE0_MME_QM_CQ_CFG0_2,
+	mmDCORE0_MME_QM_CQ_CFG0_3,
+	mmDCORE0_MME_QM_CQ_CFG0_4,
+	mmDCORE0_MME_QM_CP_FENCE0_RDATA_0,
+	mmDCORE0_MME_QM_CP_FENCE0_RDATA_1,
+	mmDCORE0_MME_QM_CP_FENCE0_RDATA_2,
+	mmDCORE0_MME_QM_CP_FENCE0_RDATA_3,
+	mmDCORE0_MME_QM_CP_FENCE0_RDATA_4,
+	mmDCORE0_MME_QM_CP_FENCE1_RDATA_0,
+	mmDCORE0_MME_QM_CP_FENCE1_RDATA_1,
+	mmDCORE0_MME_QM_CP_FENCE1_RDATA_2,
+	mmDCORE0_MME_QM_CP_FENCE1_RDATA_3,
+	mmDCORE0_MME_QM_CP_FENCE1_RDATA_4,
+	mmDCORE0_MME_QM_CP_FENCE2_RDATA_0,
+	mmDCORE0_MME_QM_CP_FENCE2_RDATA_1,
+	mmDCORE0_MME_QM_CP_FENCE2_RDATA_2,
+	mmDCORE0_MME_QM_CP_FENCE2_RDATA_3,
+	mmDCORE0_MME_QM_CP_FENCE2_RDATA_4,
+	mmDCORE0_MME_QM_CP_FENCE3_RDATA_0,
+	mmDCORE0_MME_QM_CP_FENCE3_RDATA_1,
+	mmDCORE0_MME_QM_CP_FENCE3_RDATA_2,
+	mmDCORE0_MME_QM_CP_FENCE3_RDATA_3,
+	mmDCORE0_MME_QM_CP_FENCE3_RDATA_4,
+	mmDCORE0_MME_QM_CP_FENCE0_CNT_0,
+	mmDCORE0_MME_QM_CP_FENCE0_CNT_1,
+	mmDCORE0_MME_QM_CP_FENCE0_CNT_2,
+	mmDCORE0_MME_QM_CP_FENCE0_CNT_3,
+	mmDCORE0_MME_QM_CP_FENCE0_CNT_4,
+	mmDCORE0_MME_QM_CP_FENCE1_CNT_0,
+	mmDCORE0_MME_QM_CP_FENCE1_CNT_1,
+	mmDCORE0_MME_QM_CP_FENCE1_CNT_2,
+	mmDCORE0_MME_QM_CP_FENCE1_CNT_3,
+	mmDCORE0_MME_QM_CP_FENCE1_CNT_4,
+	mmDCORE0_MME_QM_CP_FENCE2_CNT_0,
+	mmDCORE0_MME_QM_CP_FENCE2_CNT_1,
+	mmDCORE0_MME_QM_CP_FENCE2_CNT_2,
+	mmDCORE0_MME_QM_CP_FENCE2_CNT_3,
+	mmDCORE0_MME_QM_CP_FENCE2_CNT_4,
+	mmDCORE0_MME_QM_CP_FENCE3_CNT_0,
+	mmDCORE0_MME_QM_CP_FENCE3_CNT_1,
+	mmDCORE0_MME_QM_CP_FENCE3_CNT_2,
+	mmDCORE0_MME_QM_CP_FENCE3_CNT_3,
+	mmDCORE0_MME_QM_CP_FENCE3_CNT_4,
+	mmDCORE0_MME_QM_CQ_PTR_LO_0,
+	mmDCORE0_MME_QM_CQ_PTR_HI_0,
+	mmDCORE0_MME_QM_CQ_TSIZE_0,
+	mmDCORE0_MME_QM_CQ_CTL_0,
+	mmDCORE0_MME_QM_CQ_PTR_LO_1,
+	mmDCORE0_MME_QM_CQ_PTR_HI_1,
+	mmDCORE0_MME_QM_CQ_TSIZE_1,
+	mmDCORE0_MME_QM_CQ_CTL_1,
+	mmDCORE0_MME_QM_CQ_PTR_LO_2,
+	mmDCORE0_MME_QM_CQ_PTR_HI_2,
+	mmDCORE0_MME_QM_CQ_TSIZE_2,
+	mmDCORE0_MME_QM_CQ_CTL_2,
+	mmDCORE0_MME_QM_CQ_PTR_LO_3,
+	mmDCORE0_MME_QM_CQ_PTR_HI_3,
+	mmDCORE0_MME_QM_CQ_TSIZE_3,
+	mmDCORE0_MME_QM_CQ_CTL_3,
+	mmDCORE0_MME_QM_CQ_PTR_LO_4,
+	mmDCORE0_MME_QM_CQ_PTR_HI_4,
+	mmDCORE0_MME_QM_CQ_TSIZE_4,
+	mmDCORE0_MME_QM_CQ_CTL_4,
+	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR0_BASE,
+	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR0_BASE + 4,
+	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR1_BASE,
+	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR1_BASE + 4,
+	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR2_BASE,
+	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR2_BASE + 4,
+	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR3_BASE,
+	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR3_BASE + 4,
+	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR4_BASE,
+	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR4_BASE + 4,
+	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR5_BASE,
+	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR5_BASE + 4,
+	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR6_BASE,
+	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR6_BASE + 4,
+	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR7_BASE,
+	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR7_BASE + 4,
+	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR8_BASE,
+	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR8_BASE + 4,
+	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR9_BASE,
+	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR9_BASE + 4,
+	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR10_BASE,
+	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR10_BASE + 4,
+	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR11_BASE,
+	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR11_BASE + 4,
+	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR12_BASE,
+	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR12_BASE + 4,
+	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR13_BASE,
+	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR13_BASE + 4,
+	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR14_BASE,
+	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR14_BASE + 4,
+	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR15_BASE,
+	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR15_BASE + 4,
+	mmDCORE0_MME_QM_ARC_CQ_PTR_LO,
+	mmDCORE0_MME_QM_ARC_CQ_PTR_LO_STS,
+	mmDCORE0_MME_QM_ARC_CQ_PTR_HI,
+	mmDCORE0_MME_QM_ARC_CQ_PTR_HI_STS,
+	mmDCORE0_MME_QM_ARB_CFG_0,
+	mmDCORE0_MME_QM_ARB_MST_QUIET_PER,
+	mmDCORE0_MME_QM_ARB_CHOICE_Q_PUSH,
+	mmDCORE0_MME_QM_ARB_WRR_WEIGHT_0,
+	mmDCORE0_MME_QM_ARB_WRR_WEIGHT_1,
+	mmDCORE0_MME_QM_ARB_WRR_WEIGHT_2,
+	mmDCORE0_MME_QM_ARB_WRR_WEIGHT_3,
+	mmDCORE0_MME_QM_ARB_BASE_LO,
+	mmDCORE0_MME_QM_ARB_BASE_HI,
+	mmDCORE0_MME_QM_ARB_MST_SLAVE_EN,
+	mmDCORE0_MME_QM_ARB_MST_SLAVE_EN_1,
+	mmDCORE0_MME_QM_ARB_MST_CRED_INC,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_0,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_1,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_2,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_3,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_4,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_5,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_6,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_7,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_8,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_9,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_10,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_11,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_12,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_13,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_14,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_15,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_16,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_17,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_18,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_19,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_20,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_21,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_22,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_23,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_24,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_25,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_26,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_27,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_28,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_29,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_30,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_31,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_32,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_33,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_34,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_35,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_36,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_37,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_38,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_39,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_40,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_41,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_42,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_43,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_44,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_45,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_46,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_47,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_48,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_49,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_50,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_51,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_52,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_53,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_54,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_55,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_56,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_57,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_58,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_59,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_60,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_61,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_62,
+	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_63,
+	mmDCORE0_MME_QM_ARB_SLV_ID,
+	mmDCORE0_MME_QM_ARB_SLV_MASTER_INC_CRED_OFST,
+	mmDCORE0_MME_QM_ARC_CQ_CFG0,
+	mmDCORE0_MME_QM_CQ_IFIFO_CI_0,
+	mmDCORE0_MME_QM_CQ_IFIFO_CI_1,
+	mmDCORE0_MME_QM_CQ_IFIFO_CI_2,
+	mmDCORE0_MME_QM_CQ_IFIFO_CI_3,
+	mmDCORE0_MME_QM_CQ_IFIFO_CI_4,
+	mmDCORE0_MME_QM_ARC_CQ_IFIFO_CI,
+	mmDCORE0_MME_QM_CQ_CTL_CI_0,
+	mmDCORE0_MME_QM_CQ_CTL_CI_1,
+	mmDCORE0_MME_QM_CQ_CTL_CI_2,
+	mmDCORE0_MME_QM_CQ_CTL_CI_3,
+	mmDCORE0_MME_QM_CQ_CTL_CI_4,
+	mmDCORE0_MME_QM_ARC_CQ_CTL_CI,
+	mmDCORE0_MME_QM_ARC_CQ_TSIZE,
+	mmDCORE0_MME_QM_ARC_CQ_CTL,
+	mmDCORE0_MME_QM_CP_SWITCH_WD_SET,
+	mmDCORE0_MME_QM_CP_EXT_SWITCH,
+	mmDCORE0_MME_QM_CP_PRED_0,
+	mmDCORE0_MME_QM_CP_PRED_1,
+	mmDCORE0_MME_QM_CP_PRED_2,
+	mmDCORE0_MME_QM_CP_PRED_3,
+	mmDCORE0_MME_QM_CP_PRED_4,
+	mmDCORE0_MME_QM_CP_PRED_UPEN_0,
+	mmDCORE0_MME_QM_CP_PRED_UPEN_1,
+	mmDCORE0_MME_QM_CP_PRED_UPEN_2,
+	mmDCORE0_MME_QM_CP_PRED_UPEN_3,
+	mmDCORE0_MME_QM_CP_PRED_UPEN_4,
+	mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_0,
+	mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_1,
+	mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_2,
+	mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_3,
+	mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_4,
+	mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_0,
+	mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_1,
+	mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_2,
+	mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_3,
+	mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_4,
+	mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_0,
+	mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_1,
+	mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_2,
+	mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_3,
+	mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_4,
+	mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_0,
+	mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_1,
+	mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_2,
+	mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_3,
+	mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_4,
+	mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_0,
+	mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_1,
+	mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_2,
+	mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_3,
+	mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_4,
+	mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_0,
+	mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_1,
+	mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_2,
+	mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_3,
+	mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_4,
+	mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_0,
+	mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_1,
+	mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_2,
+	mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_3,
+	mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_4,
+	mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_0,
+	mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_1,
+	mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_2,
+	mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_3,
+	mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_4,
+	mmDCORE0_MME_QM_ARC_CQ_IFIFO_MSG_BASE_LO,
+	mmDCORE0_MME_QM_ARC_CQ_CTL_MSG_BASE_LO,
+	mmDCORE0_MME_QM_CQ_IFIFO_MSG_BASE_LO,
+	mmDCORE0_MME_QM_CQ_CTL_MSG_BASE_LO
+};
+
+static const u32 gaudi2_pb_dcr0_mme_eng_unsecured_regs[] = {
+	mmDCORE0_MME_CTRL_LO_CMD,
+	mmDCORE0_MME_CTRL_LO_AGU,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_0,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_1,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_2,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_3,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_4,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_0,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_1,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_2,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_3,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_4,
+	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BRAINS_LOW,
+	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BRAINS_HIGH,
+	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_HEADER_LOW,
+	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_HEADER_HIGH,
+	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_EUS_MASTER,
+	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_EUS_SLAVE,
+	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_KERNEL_SIZE_MINUS_1,
+	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_LOW,
+	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_HIGH,
+	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_OUTER_LOOP,
+	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_NUM_ITERATIONS_MINUS_1,
+	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SB_REPEAT,
+	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_FP8_BIAS,
+	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_RATE_LIMITER,
+	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_USER_DATA,
+	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PERF_EVT_IN,
+	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PERF_EVT_OUT,
+	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PCU,
+	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SLAVE_SYNC_OBJ0_ADDR,
+	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SLAVE_SYNC_OBJ1_ADDR,
+	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_POWER_LOOP,
+	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE0_MASTER,
+	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE1_MASTER,
+	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE2_MASTER,
+	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE3_MASTER,
+	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE0_SLAVE,
+	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE1_SLAVE,
+	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE2_SLAVE,
+	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE3_SLAVE,
+	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_WKL_ID,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_0,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_1,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_2,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_3,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_4,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_0,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_1,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_2,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_3,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_4,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_0,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_1,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_2,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_3,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_4,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_0,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_1,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_2,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_3,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_4,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_0,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_1,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_2,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_3,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_4,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_0,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_1,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_2,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_3,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_4,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_0,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_1,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_2,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_3,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_4,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_0,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_1,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_2,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_3,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_4,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_0,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_1,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_2,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_3,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_0,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_1,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_2,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_3,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_0,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_1,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_2,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_3,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_0,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_1,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_2,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_3,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_4,
+	mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT1_LOW,
+	mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT1_HIGH,
+	mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT0_LOW,
+	mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT0_HIGH,
+	mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_A_LOW,
+	mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_A_HIGH,
+	mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_B_LOW,
+	mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_B_HIGH,
+	mmDCORE0_MME_CTRL_LO_ARCH_STATUS,
+	mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0,
+	mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0,
+	mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0,
+	mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1,
+	mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1,
+	mmDCORE0_MME_CTRL_LO_ARCH_A_SS,
+	mmDCORE0_MME_CTRL_LO_ARCH_B_SS,
+	mmDCORE0_MME_CTRL_LO_ARCH_COUT_SS,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_0,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_1,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_2,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_3,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_4,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_0,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_1,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_2,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_3,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_4,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_0,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_1,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_2,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_3,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_4,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_0,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_1,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_2,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_3,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_4,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_0,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_1,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_2,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_3,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_0,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_1,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_2,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_3,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_0,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_1,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_2,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_3,
+	mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_BASE,
+	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BASE,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_BASE,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_BASE,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_BASE,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_BASE,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_BASE,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_BASE,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_BASE,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_BASE,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_BASE,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_BASE,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_BASE,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_BASE,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_BASE,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_BASE,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_BASE,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_BASE,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_BASE,
+	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_BASE,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_0,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_1,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_2,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_3,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_4,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_0,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_1,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_2,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_3,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_4,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_0,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_1,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_2,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_3,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_4,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_0,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_1,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_2,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_3,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_4,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_0,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_1,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_2,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_3,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_0,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_1,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_2,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_3,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_0,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_1,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_2,
+	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_3,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_0,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_1,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_2,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_3,
+	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_4,
+	mmDCORE0_MME_ACC_AP_LFSR_POLY,
+	mmDCORE0_MME_ACC_AP_LFSR_SEED_WDATA,
+	mmDCORE0_MME_ACC_AP_LFSR_SEED_SEL,
+	mmDCORE0_MME_ACC_AP_LFSR_SEED_RDATA,
+	mmDCORE0_MME_ACC_AP_LFSR_CLOSE_CGATE_DLY,
+	mmDCORE0_MME_ACC_WBC_SRC_BP,
+};
+
+static const u32 gaudi2_pb_dcr0_tpc0[] = {
+	mmDCORE0_TPC0_QM_BASE,
+	mmDCORE0_TPC0_CFG_BASE,
+	mmDCORE0_TPC0_MSTR_IF_RR_SHRD_HBW_BASE,
+};
+
+static const u32 gaudi2_pb_dcr0_tpc0_arc[] = {
+	mmDCORE0_TPC0_QM_ARC_AUX_BASE,
+};
+
+static const struct range gaudi2_pb_dcr0_tpc0_arc_unsecured_regs[] = {
+	{mmDCORE0_TPC0_QM_ARC_AUX_RUN_HALT_REQ, mmDCORE0_TPC0_QM_ARC_AUX_RUN_HALT_ACK},
+	{mmDCORE0_TPC0_QM_ARC_AUX_CLUSTER_NUM, mmDCORE0_TPC0_QM_ARC_AUX_WAKE_UP_EVENT},
+	{mmDCORE0_TPC0_QM_ARC_AUX_ARC_RST_REQ, mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_7},
+	{mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_0, mmDCORE0_TPC0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT},
+	{mmDCORE0_TPC0_QM_ARC_AUX_CBU_EARLY_BRESP_EN, mmDCORE0_TPC0_QM_ARC_AUX_CBU_EARLY_BRESP_EN},
+	{mmDCORE0_TPC0_QM_ARC_AUX_LBU_EARLY_BRESP_EN, mmDCORE0_TPC0_QM_ARC_AUX_LBU_EARLY_BRESP_EN},
+	{mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0,
+		mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG},
+	{mmDCORE0_TPC0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT,
+		mmDCORE0_TPC0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI},
+	{mmDCORE0_TPC0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT,
+		mmDCORE0_TPC0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN},
+};
+
+static const u32 gaudi2_pb_dcr0_tpc0_unsecured_regs[] = {
+	mmDCORE0_TPC0_QM_CQ_CFG0_0,
+	mmDCORE0_TPC0_QM_CQ_CFG0_1,
+	mmDCORE0_TPC0_QM_CQ_CFG0_2,
+	mmDCORE0_TPC0_QM_CQ_CFG0_3,
+	mmDCORE0_TPC0_QM_CQ_CFG0_4,
+	mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_0,
+	mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_1,
+	mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_2,
+	mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_3,
+	mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_4,
+	mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_0,
+	mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_1,
+	mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_2,
+	mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_3,
+	mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_4,
+	mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_0,
+	mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_1,
+	mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_2,
+	mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_3,
+	mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_4,
+	mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_0,
+	mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_1,
+	mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_2,
+	mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_3,
+	mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_4,
+	mmDCORE0_TPC0_QM_CP_FENCE0_CNT_0,
+	mmDCORE0_TPC0_QM_CP_FENCE0_CNT_1,
+	mmDCORE0_TPC0_QM_CP_FENCE0_CNT_2,
+	mmDCORE0_TPC0_QM_CP_FENCE0_CNT_3,
+	mmDCORE0_TPC0_QM_CP_FENCE0_CNT_4,
+	mmDCORE0_TPC0_QM_CP_FENCE1_CNT_0,
+	mmDCORE0_TPC0_QM_CP_FENCE1_CNT_1,
+	mmDCORE0_TPC0_QM_CP_FENCE1_CNT_2,
+	mmDCORE0_TPC0_QM_CP_FENCE1_CNT_3,
+	mmDCORE0_TPC0_QM_CP_FENCE1_CNT_4,
+	mmDCORE0_TPC0_QM_CP_FENCE2_CNT_0,
+	mmDCORE0_TPC0_QM_CP_FENCE2_CNT_1,
+	mmDCORE0_TPC0_QM_CP_FENCE2_CNT_2,
+	mmDCORE0_TPC0_QM_CP_FENCE2_CNT_3,
+	mmDCORE0_TPC0_QM_CP_FENCE2_CNT_4,
+	mmDCORE0_TPC0_QM_CP_FENCE3_CNT_0,
+	mmDCORE0_TPC0_QM_CP_FENCE3_CNT_1,
+	mmDCORE0_TPC0_QM_CP_FENCE3_CNT_2,
+	mmDCORE0_TPC0_QM_CP_FENCE3_CNT_3,
+	mmDCORE0_TPC0_QM_CP_FENCE3_CNT_4,
+	mmDCORE0_TPC0_QM_CQ_PTR_LO_0,
+	mmDCORE0_TPC0_QM_CQ_PTR_HI_0,
+	mmDCORE0_TPC0_QM_CQ_TSIZE_0,
+	mmDCORE0_TPC0_QM_CQ_CTL_0,
+	mmDCORE0_TPC0_QM_CQ_PTR_LO_1,
+	mmDCORE0_TPC0_QM_CQ_PTR_HI_1,
+	mmDCORE0_TPC0_QM_CQ_TSIZE_1,
+	mmDCORE0_TPC0_QM_CQ_CTL_1,
+	mmDCORE0_TPC0_QM_CQ_PTR_LO_2,
+	mmDCORE0_TPC0_QM_CQ_PTR_HI_2,
+	mmDCORE0_TPC0_QM_CQ_TSIZE_2,
+	mmDCORE0_TPC0_QM_CQ_CTL_2,
+	mmDCORE0_TPC0_QM_CQ_PTR_LO_3,
+	mmDCORE0_TPC0_QM_CQ_PTR_HI_3,
+	mmDCORE0_TPC0_QM_CQ_TSIZE_3,
+	mmDCORE0_TPC0_QM_CQ_CTL_3,
+	mmDCORE0_TPC0_QM_CQ_PTR_LO_4,
+	mmDCORE0_TPC0_QM_CQ_PTR_HI_4,
+	mmDCORE0_TPC0_QM_CQ_TSIZE_4,
+	mmDCORE0_TPC0_QM_CQ_CTL_4,
+	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE,
+	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE + 4,
+	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE,
+	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE + 4,
+	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE,
+	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE + 4,
+	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE,
+	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE + 4,
+	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE,
+	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE + 4,
+	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE,
+	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE + 4,
+	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE,
+	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE + 4,
+	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE,
+	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE + 4,
+	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE,
+	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE + 4,
+	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE,
+	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE + 4,
+	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE,
+	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE + 4,
+	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE,
+	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE + 4,
+	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE,
+	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE + 4,
+	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE,
+	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE + 4,
+	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE,
+	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE + 4,
+	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE,
+	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE + 4,
+	mmDCORE0_TPC0_QM_ARC_CQ_PTR_LO,
+	mmDCORE0_TPC0_QM_ARC_CQ_PTR_LO_STS,
+	mmDCORE0_TPC0_QM_ARC_CQ_PTR_HI,
+	mmDCORE0_TPC0_QM_ARC_CQ_PTR_HI_STS,
+	mmDCORE0_TPC0_QM_ARB_CFG_0,
+	mmDCORE0_TPC0_QM_ARB_MST_QUIET_PER,
+	mmDCORE0_TPC0_QM_ARB_CHOICE_Q_PUSH,
+	mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_0,
+	mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_1,
+	mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_2,
+	mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_3,
+	mmDCORE0_TPC0_QM_ARB_BASE_LO,
+	mmDCORE0_TPC0_QM_ARB_BASE_HI,
+	mmDCORE0_TPC0_QM_ARB_MST_SLAVE_EN,
+	mmDCORE0_TPC0_QM_ARB_MST_SLAVE_EN_1,
+	mmDCORE0_TPC0_QM_ARB_MST_CRED_INC,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_0,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_1,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_2,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_3,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_4,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_5,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_6,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_7,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_8,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_9,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_10,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_11,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_12,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_13,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_14,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_15,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_16,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_17,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_18,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_19,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_20,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_21,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_22,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_23,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_24,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_25,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_26,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_27,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_28,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_29,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_30,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_31,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_32,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_33,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_34,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_35,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_36,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_37,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_38,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_39,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_40,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_41,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_42,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_43,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_44,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_45,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_46,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_47,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_48,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_49,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_50,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_51,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_52,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_53,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_54,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_55,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_56,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_57,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_58,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_59,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_60,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_61,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_62,
+	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_63,
+	mmDCORE0_TPC0_QM_ARB_SLV_ID,
+	mmDCORE0_TPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST,
+	mmDCORE0_TPC0_QM_ARC_CQ_CFG0,
+	mmDCORE0_TPC0_QM_CQ_IFIFO_CI_0,
+	mmDCORE0_TPC0_QM_CQ_IFIFO_CI_1,
+	mmDCORE0_TPC0_QM_CQ_IFIFO_CI_2,
+	mmDCORE0_TPC0_QM_CQ_IFIFO_CI_3,
+	mmDCORE0_TPC0_QM_CQ_IFIFO_CI_4,
+	mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_CI,
+	mmDCORE0_TPC0_QM_CQ_CTL_CI_0,
+	mmDCORE0_TPC0_QM_CQ_CTL_CI_1,
+	mmDCORE0_TPC0_QM_CQ_CTL_CI_2,
+	mmDCORE0_TPC0_QM_CQ_CTL_CI_3,
+	mmDCORE0_TPC0_QM_CQ_CTL_CI_4,
+	mmDCORE0_TPC0_QM_ARC_CQ_CTL_CI,
+	mmDCORE0_TPC0_QM_ARC_CQ_TSIZE,
+	mmDCORE0_TPC0_QM_ARC_CQ_CTL,
+	mmDCORE0_TPC0_QM_CP_SWITCH_WD_SET,
+	mmDCORE0_TPC0_QM_CP_EXT_SWITCH,
+	mmDCORE0_TPC0_QM_CP_PRED_0,
+	mmDCORE0_TPC0_QM_CP_PRED_1,
+	mmDCORE0_TPC0_QM_CP_PRED_2,
+	mmDCORE0_TPC0_QM_CP_PRED_3,
+	mmDCORE0_TPC0_QM_CP_PRED_4,
+	mmDCORE0_TPC0_QM_CP_PRED_UPEN_0,
+	mmDCORE0_TPC0_QM_CP_PRED_UPEN_1,
+	mmDCORE0_TPC0_QM_CP_PRED_UPEN_2,
+	mmDCORE0_TPC0_QM_CP_PRED_UPEN_3,
+	mmDCORE0_TPC0_QM_CP_PRED_UPEN_4,
+	mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_0,
+	mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_1,
+	mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_2,
+	mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_3,
+	mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_4,
+	mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_0,
+	mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_1,
+	mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_2,
+	mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_3,
+	mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_4,
+	mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_0,
+	mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_1,
+	mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_2,
+	mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_3,
+	mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_4,
+	mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_0,
+	mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_1,
+	mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_2,
+	mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_3,
+	mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_4,
+	mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_0,
+	mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_1,
+	mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_2,
+	mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_3,
+	mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_4,
+	mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_0,
+	mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_1,
+	mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_2,
+	mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_3,
+	mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_4,
+	mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_0,
+	mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_1,
+	mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_2,
+	mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_3,
+	mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_4,
+	mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_0,
+	mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_1,
+	mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_2,
+	mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_3,
+	mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_4,
+	mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_MSG_BASE_LO,
+	mmDCORE0_TPC0_QM_ARC_CQ_CTL_MSG_BASE_LO,
+	mmDCORE0_TPC0_QM_CQ_IFIFO_MSG_BASE_LO,
+	mmDCORE0_TPC0_QM_CQ_CTL_MSG_BASE_LO,
+	mmDCORE0_TPC0_CFG_QM_SYNC_OBJECT_MESSAGE,
+	mmDCORE0_TPC0_CFG_QM_SYNC_OBJECT_ADDR,
+	mmDCORE0_TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW,
+	mmDCORE0_TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH,
+	mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_0,
+	mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_0,
+	mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_1,
+	mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_1,
+	mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_2,
+	mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_2,
+	mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_3,
+	mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_3,
+	mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_4,
+	mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_4,
+	mmDCORE0_TPC0_CFG_QM_KERNEL_CONFIG,
+	mmDCORE0_TPC0_CFG_QM_KERNEL_ID,
+	mmDCORE0_TPC0_CFG_QM_POWER_LOOP,
+	mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_0,
+	mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_1,
+	mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_2,
+	mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_3,
+	mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_LO,
+	mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_HI,
+	mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_LO,
+	mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_HI,
+	mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_LO,
+	mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_HI,
+	mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_LO,
+	mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_HI,
+	mmDCORE0_TPC0_CFG_FP8_143_BIAS,
+	mmDCORE0_TPC0_CFG_ROUND_CSR,
+	mmDCORE0_TPC0_CFG_CONV_ROUND_CSR,
+	mmDCORE0_TPC0_CFG_SEMAPHORE,
+	mmDCORE0_TPC0_CFG_LFSR_POLYNOM,
+	mmDCORE0_TPC0_CFG_STATUS,
+	mmDCORE0_TPC0_CFG_TPC_CMD,
+	mmDCORE0_TPC0_CFG_TPC_EXECUTE,
+	mmDCORE0_TPC0_CFG_TPC_DCACHE_L0CD,
+	mmDCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_LOW,
+	mmDCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH,
+	mmDCORE0_TPC0_CFG_RD_RATE_LIMIT,
+	mmDCORE0_TPC0_CFG_WR_RATE_LIMIT,
+	mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO,
+	mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI,
+	mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO,
+	mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI,
+	mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO,
+	mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI,
+	mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO,
+	mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI,
+	mmDCORE0_TPC0_CFG_KERNEL_KERNEL_CONFIG,
+	mmDCORE0_TPC0_CFG_KERNEL_SRF_0,
+	mmDCORE0_TPC0_CFG_KERNEL_SRF_1,
+	mmDCORE0_TPC0_CFG_KERNEL_SRF_2,
+	mmDCORE0_TPC0_CFG_KERNEL_SRF_3,
+	mmDCORE0_TPC0_CFG_KERNEL_SRF_4,
+	mmDCORE0_TPC0_CFG_KERNEL_SRF_5,
+	mmDCORE0_TPC0_CFG_KERNEL_SRF_6,
+	mmDCORE0_TPC0_CFG_KERNEL_SRF_7,
+	mmDCORE0_TPC0_CFG_KERNEL_SRF_8,
+	mmDCORE0_TPC0_CFG_KERNEL_SRF_9,
+	mmDCORE0_TPC0_CFG_KERNEL_SRF_10,
+	mmDCORE0_TPC0_CFG_KERNEL_SRF_11,
+	mmDCORE0_TPC0_CFG_KERNEL_SRF_12,
+	mmDCORE0_TPC0_CFG_KERNEL_SRF_13,
+	mmDCORE0_TPC0_CFG_KERNEL_SRF_14,
+	mmDCORE0_TPC0_CFG_KERNEL_SRF_15,
+	mmDCORE0_TPC0_CFG_KERNEL_SRF_16,
+	mmDCORE0_TPC0_CFG_KERNEL_SRF_17,
+	mmDCORE0_TPC0_CFG_KERNEL_SRF_18,
+	mmDCORE0_TPC0_CFG_KERNEL_SRF_19,
+	mmDCORE0_TPC0_CFG_KERNEL_SRF_20,
+	mmDCORE0_TPC0_CFG_KERNEL_SRF_21,
+	mmDCORE0_TPC0_CFG_KERNEL_SRF_22,
+	mmDCORE0_TPC0_CFG_KERNEL_SRF_23,
+	mmDCORE0_TPC0_CFG_KERNEL_SRF_24,
+	mmDCORE0_TPC0_CFG_KERNEL_SRF_25,
+	mmDCORE0_TPC0_CFG_KERNEL_SRF_26,
+	mmDCORE0_TPC0_CFG_KERNEL_SRF_27,
+	mmDCORE0_TPC0_CFG_KERNEL_SRF_28,
+	mmDCORE0_TPC0_CFG_KERNEL_SRF_29,
+	mmDCORE0_TPC0_CFG_KERNEL_SRF_30,
+	mmDCORE0_TPC0_CFG_KERNEL_SRF_31,
+	mmDCORE0_TPC0_CFG_TPC_SB_L0CD,
+	mmDCORE0_TPC0_CFG_TPC_COUNT,
+	mmDCORE0_TPC0_CFG_TPC_ID,
+	mmDCORE0_TPC0_CFG_QM_KERNEL_ID_INC,
+	mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_0,
+	mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_1,
+	mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_2,
+	mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_3,
+	mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_4,
+	mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_0,
+	mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_1,
+	mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_2,
+	mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_3
+};
+
+static const u32 gaudi2_pb_dcr0_tpc0_ktensor_unsecured_regs[] = {
+	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW,
+	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH,
+	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE,
+	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG,
+	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE,
+	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE,
+	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE,
+	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE,
+	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE,
+	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE,
+	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE,
+	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE,
+	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE,
+	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE,
+	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_PREF_STRIDE,
+	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_STRIDE_HIGH,
+	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_STRIDE_HIGH,
+	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_STRIDE_HIGH,
+	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_STRIDE_HIGH,
+	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_STRIDE_HIGH,
+};
+
+static const u32 gaudi2_pb_dcr0_tpc0_qtensor_unsecured_regs[] = {
+	mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW,
+	mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH,
+	mmDCORE0_TPC0_CFG_QM_TENSOR_0_PADDING_VALUE,
+	mmDCORE0_TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG,
+	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE,
+	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE,
+	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE,
+	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE,
+	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE,
+	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE,
+	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE,
+	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE,
+	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE,
+	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE,
+	mmDCORE0_TPC0_CFG_QM_TENSOR_0_PREF_STRIDE,
+	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_STRIDE_HIGH,
+	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_STRIDE_HIGH,
+	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_STRIDE_HIGH,
+	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_STRIDE_HIGH,
+	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_STRIDE_HIGH,
+};
+
+static const u32 gaudi2_pb_dcr0_sram0[] = {
+	mmDCORE0_SRAM0_BANK_BASE,
+	mmDCORE0_SRAM0_DBG_CNT_N_HBW_DBG_CNT_BASE,
+	mmDCORE0_SRAM0_RTR_BASE,
+};
+
+static const u32 gaudi2_pb_dcr0_sm_mstr_if[] = {
+	mmDCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_BASE,
+};
+
+static const u32 gaudi2_pb_dcr0_sm_glbl[] = {
+	mmDCORE0_SYNC_MNGR_GLBL_BASE,
+};
+
+static const u32 gaudi2_pb_dcr1_sm_glbl[] = {
+	mmDCORE1_SYNC_MNGR_GLBL_BASE,
+};
+
+static const struct range gaudi2_pb_dcr0_sm_glbl_unsecured_regs[] = {
+	{mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_63},
+	{mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_63},
+	{mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_63},
+	{mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_63},
+	{mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_1, mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_63},
+	{mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_1, mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_63},
+	{mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_1, mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_63},
+	{mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_63},
+};
+
+static const struct range gaudi2_pb_dcr_x_sm_glbl_unsecured_regs[] = {
+	{mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_0, mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_63},
+	{mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_0, mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_63},
+	{mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_0, mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_63},
+	{mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_0, mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_63},
+	{mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_0, mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_63},
+	{mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_0, mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_63},
+	{mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_0, mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_63},
+	{mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_0, mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_63},
+};
+
+static const u32 gaudi2_pb_arc_sched[] = {
+	mmARC_FARM_ARC0_AUX_BASE,
+	mmARC_FARM_ARC0_DUP_ENG_BASE,
+	mmARC_FARM_ARC0_ACP_ENG_BASE,
+};
+
+static const struct range gaudi2_pb_arc_sched_unsecured_regs[] = {
+	{mmARC_FARM_ARC0_AUX_RUN_HALT_REQ, mmARC_FARM_ARC0_AUX_RUN_HALT_ACK},
+	{mmARC_FARM_ARC0_AUX_CLUSTER_NUM, mmARC_FARM_ARC0_AUX_WAKE_UP_EVENT},
+	{mmARC_FARM_ARC0_AUX_ARC_RST_REQ, mmARC_FARM_ARC0_AUX_CID_OFFSET_7},
+	{mmARC_FARM_ARC0_AUX_SCRATCHPAD_0, mmARC_FARM_ARC0_AUX_INFLIGHT_LBU_RD_CNT},
+	{mmARC_FARM_ARC0_AUX_CBU_EARLY_BRESP_EN, mmARC_FARM_ARC0_AUX_CBU_EARLY_BRESP_EN},
+	{mmARC_FARM_ARC0_AUX_LBU_EARLY_BRESP_EN, mmARC_FARM_ARC0_AUX_LBU_EARLY_BRESP_EN},
+	{mmARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR_0, mmARC_FARM_ARC0_AUX_DCCM_QUEUE_ALERT_MSG},
+	{mmARC_FARM_ARC0_AUX_DCCM_Q_PUSH_FIFO_CNT, mmARC_FARM_ARC0_AUX_QMAN_ARC_CQ_SHADOW_CI},
+	{mmARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_WR_IF_CNT, mmARC_FARM_ARC0_AUX_MME_ARC_UPPER_DCCM_EN},
+	{mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_0, mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_63},
+	{mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_STRONG_ORDER, mmARC_FARM_ARC0_DUP_ENG_AXUSER_LB_OVRD},
+	{mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_0, mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_REG},
+};
+
+static const u32 gaudi2_pb_xbar_mid[] = {
+	mmXBAR_MID_0_BASE,
+};
+
+static const u32 gaudi2_pb_xbar_mid_unsecured_regs[] = {
+	mmXBAR_MID_0_UPSCALE,
+	mmXBAR_MID_0_DOWN_CONV,
+	mmXBAR_MID_0_DOWN_CONV_LFSR_EN,
+	mmXBAR_MID_0_DOWN_CONV_LFSR_SET_VLD,
+	mmXBAR_MID_0_DOWN_CONV_LFSR_SET_VALUE,
+	mmXBAR_MID_0_DOWN_CONV_LFSR_CFG_POLY,
+};
+
+static const u32 gaudi2_pb_xbar_edge[] = {
+	mmXBAR_EDGE_0_BASE,
+};
+
+static const u32 gaudi2_pb_xbar_edge_unsecured_regs[] = {
+	mmXBAR_EDGE_0_UPSCALE,
+	mmXBAR_EDGE_0_DOWN_CONV,
+	mmXBAR_EDGE_0_DOWN_CONV_LFSR_EN,
+	mmXBAR_EDGE_0_DOWN_CONV_LFSR_SET_VLD,
+	mmXBAR_EDGE_0_DOWN_CONV_LFSR_SET_VALUE,
+	mmXBAR_EDGE_0_DOWN_CONV_LFSR_CFG_POLY,
+};
+
+static const u32 gaudi2_pb_nic0[] = {
+	mmNIC0_TMR_BASE,
+	mmNIC0_RXB_CORE_BASE,
+	mmNIC0_RXE0_BASE,
+	mmNIC0_RXE1_BASE,
+	mmNIC0_RXE0_AXUSER_AXUSER_CQ0_BASE,
+	mmNIC0_RXE1_AXUSER_AXUSER_CQ0_BASE,
+	mmNIC0_TXS0_BASE,
+	mmNIC0_TXS1_BASE,
+	mmNIC0_TXE0_BASE,
+	mmNIC0_TXE1_BASE,
+	mmNIC0_TXB_BASE,
+	mmNIC0_MSTR_IF_RR_SHRD_HBW_BASE,
+};
+
+static const u32 gaudi2_pb_nic0_qm_qpc[] = {
+	mmNIC0_QM0_BASE,
+	mmNIC0_QPC0_BASE,
+};
+
+static const u32 gaudi2_pb_nic0_qm_arc_aux0[] = {
+	mmNIC0_QM_ARC_AUX0_BASE,
+};
+
+static const struct range gaudi2_pb_nic0_qm_arc_aux0_unsecured_regs[] = {
+	{mmNIC0_QM_ARC_AUX0_RUN_HALT_REQ, mmNIC0_QM_ARC_AUX0_RUN_HALT_ACK},
+	{mmNIC0_QM_ARC_AUX0_CLUSTER_NUM, mmNIC0_QM_ARC_AUX0_WAKE_UP_EVENT},
+	{mmNIC0_QM_ARC_AUX0_ARC_RST_REQ, mmNIC0_QM_ARC_AUX0_CID_OFFSET_7},
+	{mmNIC0_QM_ARC_AUX0_SCRATCHPAD_0, mmNIC0_QM_ARC_AUX0_INFLIGHT_LBU_RD_CNT},
+	{mmNIC0_QM_ARC_AUX0_CBU_EARLY_BRESP_EN, mmNIC0_QM_ARC_AUX0_CBU_EARLY_BRESP_EN},
+	{mmNIC0_QM_ARC_AUX0_LBU_EARLY_BRESP_EN, mmNIC0_QM_ARC_AUX0_LBU_EARLY_BRESP_EN},
+	{mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_0, mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_ALERT_MSG},
+	{mmNIC0_QM_ARC_AUX0_DCCM_Q_PUSH_FIFO_CNT, mmNIC0_QM_ARC_AUX0_QMAN_ARC_CQ_SHADOW_CI},
+	{mmNIC0_QM_ARC_AUX0_ARC_AXI_ORDERING_WR_IF_CNT, mmNIC0_QM_ARC_AUX0_MME_ARC_UPPER_DCCM_EN},
+};
+
+static const u32 gaudi2_pb_nic0_umr[] = {
+	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE,
+	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 1, /* UMR0_1 */
+	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 2, /* UMR0_2 */
+	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 3, /* UMR0_3 */
+	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 4, /* UMR0_4 */
+	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 5, /* UMR0_5 */
+	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 6, /* UMR0_6 */
+	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 7, /* UMR0_7 */
+	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 8, /* UMR0_8 */
+	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 9, /* UMR0_9 */
+	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 10, /* UMR0_10 */
+	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 11, /* UMR0_11 */
+	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 12, /* UMR0_12 */
+	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 13, /* UMR0_13 */
+	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 14, /* UMR0_14 */
+};
+
+static const struct range gaudi2_pb_nic0_umr_unsecured_regs[] = {
+	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32,
+		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX},
+	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 1, /* UMR0_1 */
+		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 1},
+	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 2, /* UMR0_2 */
+		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 2},
+	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 3, /* UMR0_3 */
+		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 3},
+	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 4, /* UMR0_4 */
+		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 4},
+	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 5, /* UMR0_5 */
+		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 5},
+	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 6, /* UMR0_6 */
+		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 6},
+	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 7, /* UMR0_7 */
+		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 7},
+	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 8, /* UMR0_8 */
+		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 8},
+	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 9, /* UMR0_9 */
+		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 9},
+	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 10, /* UMR0_10 */
+		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 10},
+	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 11, /* UMR0_11 */
+		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 11},
+	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 12, /* UMR0_12 */
+		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 12},
+	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 13, /* UMR0_13 */
+		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 13},
+	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 14, /* UMR0_14 */
+		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 14},
+};
+
+/*
+ * mmNIC0_QPC0_LINEAR_WQE_QPN and mmNIC0_QPC0_MULTI_STRIDE_WQE_QPN are 32-bit
+ * registers and since the user writes in bulks of 64 bits we need to un-secure
+ * also the following 32 bits (that's why we added also the next 4 bytes to the
+ * table). In the RTL, as part of ECO (2874), writing to the next 4 bytes
+ * triggers a write to the SPECIAL_GLBL_SPARE register, hence it's must be
+ * unsecured as well.
+ */
+#define mmNIC0_QPC0_LINEAR_WQE_RSV (mmNIC0_QPC0_LINEAR_WQE_QPN + 4)
+#define mmNIC0_QPC0_MULTI_STRIDE_WQE_RSV (mmNIC0_QPC0_MULTI_STRIDE_WQE_QPN + 4)
+#define mmNIC0_QPC0_SPECIAL_GLBL_SPARE 0x541FF60
+
+static const u32 gaudi2_pb_nic0_qm_qpc_unsecured_regs[] = {
+	mmNIC0_QPC0_LINEAR_WQE_STATIC_0,
+	mmNIC0_QPC0_LINEAR_WQE_STATIC_1,
+	mmNIC0_QPC0_LINEAR_WQE_STATIC_2,
+	mmNIC0_QPC0_LINEAR_WQE_STATIC_3,
+	mmNIC0_QPC0_LINEAR_WQE_STATIC_4,
+	mmNIC0_QPC0_LINEAR_WQE_STATIC_5,
+	mmNIC0_QPC0_LINEAR_WQE_STATIC_6,
+	mmNIC0_QPC0_LINEAR_WQE_STATIC_7,
+	mmNIC0_QPC0_LINEAR_WQE_STATIC_8,
+	mmNIC0_QPC0_LINEAR_WQE_STATIC_9,
+	mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_0,
+	mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_1,
+	mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_2,
+	mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_3,
+	mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_4,
+	mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_5,
+	mmNIC0_QPC0_LINEAR_WQE_QPN,
+	mmNIC0_QPC0_LINEAR_WQE_RSV,
+	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_0,
+	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_1,
+	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_2,
+	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_3,
+	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_4,
+	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_5,
+	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_6,
+	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_7,
+	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_8,
+	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_9,
+	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_10,
+	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_11,
+	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_12,
+	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_13,
+	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_14,
+	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_15,
+	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_16,
+	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_17,
+	mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_0,
+	mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_1,
+	mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_2,
+	mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_3,
+	mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_4,
+	mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_5,
+	mmNIC0_QPC0_MULTI_STRIDE_WQE_QPN,
+	mmNIC0_QPC0_MULTI_STRIDE_WQE_RSV,
+	mmNIC0_QPC0_QMAN_DOORBELL,
+	mmNIC0_QPC0_QMAN_DOORBELL_QPN,
+	mmNIC0_QPC0_SPECIAL_GLBL_SPARE,
+	mmNIC0_QM0_CQ_CFG0_0,
+	mmNIC0_QM0_CQ_CFG0_1,
+	mmNIC0_QM0_CQ_CFG0_2,
+	mmNIC0_QM0_CQ_CFG0_3,
+	mmNIC0_QM0_CQ_CFG0_4,
+	mmNIC0_QM0_CP_FENCE0_RDATA_0,
+	mmNIC0_QM0_CP_FENCE0_RDATA_1,
+	mmNIC0_QM0_CP_FENCE0_RDATA_2,
+	mmNIC0_QM0_CP_FENCE0_RDATA_3,
+	mmNIC0_QM0_CP_FENCE0_RDATA_4,
+	mmNIC0_QM0_CP_FENCE1_RDATA_0,
+	mmNIC0_QM0_CP_FENCE1_RDATA_1,
+	mmNIC0_QM0_CP_FENCE1_RDATA_2,
+	mmNIC0_QM0_CP_FENCE1_RDATA_3,
+	mmNIC0_QM0_CP_FENCE1_RDATA_4,
+	mmNIC0_QM0_CP_FENCE2_RDATA_0,
+	mmNIC0_QM0_CP_FENCE2_RDATA_1,
+	mmNIC0_QM0_CP_FENCE2_RDATA_2,
+	mmNIC0_QM0_CP_FENCE2_RDATA_3,
+	mmNIC0_QM0_CP_FENCE2_RDATA_4,
+	mmNIC0_QM0_CP_FENCE3_RDATA_0,
+	mmNIC0_QM0_CP_FENCE3_RDATA_1,
+	mmNIC0_QM0_CP_FENCE3_RDATA_2,
+	mmNIC0_QM0_CP_FENCE3_RDATA_3,
+	mmNIC0_QM0_CP_FENCE3_RDATA_4,
+	mmNIC0_QM0_CP_FENCE0_CNT_0,
+	mmNIC0_QM0_CP_FENCE0_CNT_1,
+	mmNIC0_QM0_CP_FENCE0_CNT_2,
+	mmNIC0_QM0_CP_FENCE0_CNT_3,
+	mmNIC0_QM0_CP_FENCE0_CNT_4,
+	mmNIC0_QM0_CP_FENCE1_CNT_0,
+	mmNIC0_QM0_CP_FENCE1_CNT_1,
+	mmNIC0_QM0_CP_FENCE1_CNT_2,
+	mmNIC0_QM0_CP_FENCE1_CNT_3,
+	mmNIC0_QM0_CP_FENCE1_CNT_4,
+	mmNIC0_QM0_CP_FENCE2_CNT_0,
+	mmNIC0_QM0_CP_FENCE2_CNT_1,
+	mmNIC0_QM0_CP_FENCE2_CNT_2,
+	mmNIC0_QM0_CP_FENCE2_CNT_3,
+	mmNIC0_QM0_CP_FENCE2_CNT_4,
+	mmNIC0_QM0_CP_FENCE3_CNT_0,
+	mmNIC0_QM0_CP_FENCE3_CNT_1,
+	mmNIC0_QM0_CP_FENCE3_CNT_2,
+	mmNIC0_QM0_CP_FENCE3_CNT_3,
+	mmNIC0_QM0_CP_FENCE3_CNT_4,
+	mmNIC0_QM0_CQ_PTR_LO_0,
+	mmNIC0_QM0_CQ_PTR_HI_0,
+	mmNIC0_QM0_CQ_TSIZE_0,
+	mmNIC0_QM0_CQ_CTL_0,
+	mmNIC0_QM0_CQ_PTR_LO_1,
+	mmNIC0_QM0_CQ_PTR_HI_1,
+	mmNIC0_QM0_CQ_TSIZE_1,
+	mmNIC0_QM0_CQ_CTL_1,
+	mmNIC0_QM0_CQ_PTR_LO_2,
+	mmNIC0_QM0_CQ_PTR_HI_2,
+	mmNIC0_QM0_CQ_TSIZE_2,
+	mmNIC0_QM0_CQ_CTL_2,
+	mmNIC0_QM0_CQ_PTR_LO_3,
+	mmNIC0_QM0_CQ_PTR_HI_3,
+	mmNIC0_QM0_CQ_TSIZE_3,
+	mmNIC0_QM0_CQ_CTL_3,
+	mmNIC0_QM0_CQ_PTR_LO_4,
+	mmNIC0_QM0_CQ_PTR_HI_4,
+	mmNIC0_QM0_CQ_TSIZE_4,
+	mmNIC0_QM0_CQ_CTL_4,
+	mmNIC0_QM0_QMAN_WR64_BASE_ADDR0_BASE,
+	mmNIC0_QM0_QMAN_WR64_BASE_ADDR0_BASE + 4,
+	mmNIC0_QM0_QMAN_WR64_BASE_ADDR1_BASE,
+	mmNIC0_QM0_QMAN_WR64_BASE_ADDR1_BASE + 4,
+	mmNIC0_QM0_QMAN_WR64_BASE_ADDR2_BASE,
+	mmNIC0_QM0_QMAN_WR64_BASE_ADDR2_BASE + 4,
+	mmNIC0_QM0_QMAN_WR64_BASE_ADDR3_BASE,
+	mmNIC0_QM0_QMAN_WR64_BASE_ADDR3_BASE + 4,
+	mmNIC0_QM0_QMAN_WR64_BASE_ADDR4_BASE,
+	mmNIC0_QM0_QMAN_WR64_BASE_ADDR4_BASE + 4,
+	mmNIC0_QM0_QMAN_WR64_BASE_ADDR5_BASE,
+	mmNIC0_QM0_QMAN_WR64_BASE_ADDR5_BASE + 4,
+	mmNIC0_QM0_QMAN_WR64_BASE_ADDR6_BASE,
+	mmNIC0_QM0_QMAN_WR64_BASE_ADDR6_BASE + 4,
+	mmNIC0_QM0_QMAN_WR64_BASE_ADDR7_BASE,
+	mmNIC0_QM0_QMAN_WR64_BASE_ADDR7_BASE + 4,
+	mmNIC0_QM0_QMAN_WR64_BASE_ADDR8_BASE,
+	mmNIC0_QM0_QMAN_WR64_BASE_ADDR8_BASE + 4,
+	mmNIC0_QM0_QMAN_WR64_BASE_ADDR9_BASE,
+	mmNIC0_QM0_QMAN_WR64_BASE_ADDR9_BASE + 4,
+	mmNIC0_QM0_QMAN_WR64_BASE_ADDR10_BASE,
+	mmNIC0_QM0_QMAN_WR64_BASE_ADDR10_BASE + 4,
+	mmNIC0_QM0_QMAN_WR64_BASE_ADDR11_BASE,
+	mmNIC0_QM0_QMAN_WR64_BASE_ADDR11_BASE + 4,
+	mmNIC0_QM0_QMAN_WR64_BASE_ADDR12_BASE,
+	mmNIC0_QM0_QMAN_WR64_BASE_ADDR12_BASE + 4,
+	mmNIC0_QM0_QMAN_WR64_BASE_ADDR13_BASE,
+	mmNIC0_QM0_QMAN_WR64_BASE_ADDR13_BASE + 4,
+	mmNIC0_QM0_QMAN_WR64_BASE_ADDR14_BASE,
+	mmNIC0_QM0_QMAN_WR64_BASE_ADDR14_BASE + 4,
+	mmNIC0_QM0_QMAN_WR64_BASE_ADDR15_BASE,
+	mmNIC0_QM0_QMAN_WR64_BASE_ADDR15_BASE + 4,
+	mmNIC0_QM0_ARC_CQ_PTR_LO,
+	mmNIC0_QM0_ARC_CQ_PTR_LO_STS,
+	mmNIC0_QM0_ARC_CQ_PTR_HI,
+	mmNIC0_QM0_ARC_CQ_PTR_HI_STS,
+	mmNIC0_QM0_ARB_CFG_0,
+	mmNIC0_QM0_ARB_MST_QUIET_PER,
+	mmNIC0_QM0_ARB_CHOICE_Q_PUSH,
+	mmNIC0_QM0_ARB_WRR_WEIGHT_0,
+	mmNIC0_QM0_ARB_WRR_WEIGHT_1,
+	mmNIC0_QM0_ARB_WRR_WEIGHT_2,
+	mmNIC0_QM0_ARB_WRR_WEIGHT_3,
+	mmNIC0_QM0_ARB_BASE_LO,
+	mmNIC0_QM0_ARB_BASE_HI,
+	mmNIC0_QM0_ARB_MST_SLAVE_EN,
+	mmNIC0_QM0_ARB_MST_SLAVE_EN_1,
+	mmNIC0_QM0_ARB_MST_CRED_INC,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_0,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_1,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_2,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_3,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_4,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_5,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_6,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_7,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_8,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_9,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_10,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_11,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_12,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_13,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_14,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_15,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_16,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_17,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_18,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_19,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_20,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_21,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_22,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_23,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_24,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_25,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_26,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_27,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_28,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_29,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_30,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_31,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_32,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_33,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_34,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_35,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_36,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_37,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_38,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_39,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_40,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_41,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_42,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_43,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_44,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_45,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_46,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_47,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_48,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_49,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_50,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_51,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_52,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_53,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_54,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_55,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_56,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_57,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_58,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_59,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_60,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_61,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_62,
+	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_63,
+	mmNIC0_QM0_ARB_SLV_ID,
+	mmNIC0_QM0_ARB_SLV_MASTER_INC_CRED_OFST,
+	mmNIC0_QM0_ARC_CQ_CFG0,
+	mmNIC0_QM0_CQ_IFIFO_CI_0,
+	mmNIC0_QM0_CQ_IFIFO_CI_1,
+	mmNIC0_QM0_CQ_IFIFO_CI_2,
+	mmNIC0_QM0_CQ_IFIFO_CI_3,
+	mmNIC0_QM0_CQ_IFIFO_CI_4,
+	mmNIC0_QM0_ARC_CQ_IFIFO_CI,
+	mmNIC0_QM0_CQ_CTL_CI_0,
+	mmNIC0_QM0_CQ_CTL_CI_1,
+	mmNIC0_QM0_CQ_CTL_CI_2,
+	mmNIC0_QM0_CQ_CTL_CI_3,
+	mmNIC0_QM0_CQ_CTL_CI_4,
+	mmNIC0_QM0_ARC_CQ_CTL_CI,
+	mmNIC0_QM0_ARC_CQ_TSIZE,
+	mmNIC0_QM0_ARC_CQ_CTL,
+	mmNIC0_QM0_CP_SWITCH_WD_SET,
+	mmNIC0_QM0_CP_EXT_SWITCH,
+	mmNIC0_QM0_CP_PRED_0,
+	mmNIC0_QM0_CP_PRED_1,
+	mmNIC0_QM0_CP_PRED_2,
+	mmNIC0_QM0_CP_PRED_3,
+	mmNIC0_QM0_CP_PRED_4,
+	mmNIC0_QM0_CP_PRED_UPEN_0,
+	mmNIC0_QM0_CP_PRED_UPEN_1,
+	mmNIC0_QM0_CP_PRED_UPEN_2,
+	mmNIC0_QM0_CP_PRED_UPEN_3,
+	mmNIC0_QM0_CP_PRED_UPEN_4,
+	mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_0,
+	mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_1,
+	mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_2,
+	mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_3,
+	mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_4,
+	mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_0,
+	mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_1,
+	mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_2,
+	mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_3,
+	mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_4,
+	mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_0,
+	mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_1,
+	mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_2,
+	mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_3,
+	mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_4,
+	mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_0,
+	mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_1,
+	mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_2,
+	mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_3,
+	mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_4,
+	mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_0,
+	mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_1,
+	mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_2,
+	mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_3,
+	mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_4,
+	mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_0,
+	mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_1,
+	mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_2,
+	mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_3,
+	mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_4,
+	mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_0,
+	mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_1,
+	mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_2,
+	mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_3,
+	mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_4,
+	mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_0,
+	mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_1,
+	mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_2,
+	mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_3,
+	mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_4,
+	mmNIC0_QM0_ARC_CQ_IFIFO_MSG_BASE_LO,
+	mmNIC0_QM0_ARC_CQ_CTL_MSG_BASE_LO,
+	mmNIC0_QM0_CQ_IFIFO_MSG_BASE_LO,
+	mmNIC0_QM0_CQ_CTL_MSG_BASE_LO
+};
+
+static const u32 gaudi2_pb_rot0[] = {
+	mmROT0_BASE,
+	mmROT0_MSTR_IF_RR_SHRD_HBW_BASE,
+	mmROT0_QM_BASE,
+};
+
+static const u32 gaudi2_pb_rot0_arc[] = {
+	mmROT0_QM_ARC_AUX_BASE
+};
+
+static const struct range gaudi2_pb_rot0_arc_unsecured_regs[] = {
+	{mmROT0_QM_ARC_AUX_RUN_HALT_REQ, mmROT0_QM_ARC_AUX_RUN_HALT_ACK},
+	{mmROT0_QM_ARC_AUX_CLUSTER_NUM, mmROT0_QM_ARC_AUX_WAKE_UP_EVENT},
+	{mmROT0_QM_ARC_AUX_ARC_RST_REQ, mmROT0_QM_ARC_AUX_CID_OFFSET_7},
+	{mmROT0_QM_ARC_AUX_SCRATCHPAD_0, mmROT0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT},
+	{mmROT0_QM_ARC_AUX_CBU_EARLY_BRESP_EN, mmROT0_QM_ARC_AUX_CBU_EARLY_BRESP_EN},
+	{mmROT0_QM_ARC_AUX_LBU_EARLY_BRESP_EN, mmROT0_QM_ARC_AUX_LBU_EARLY_BRESP_EN},
+	{mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0, mmROT0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG},
+	{mmROT0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT, mmROT0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI},
+	{mmROT0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT, mmROT0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN},
+};
+
+static const u32 gaudi2_pb_rot0_unsecured_regs[] = {
+	mmROT0_QM_CQ_CFG0_0,
+	mmROT0_QM_CQ_CFG0_1,
+	mmROT0_QM_CQ_CFG0_2,
+	mmROT0_QM_CQ_CFG0_3,
+	mmROT0_QM_CQ_CFG0_4,
+	mmROT0_QM_CP_FENCE0_RDATA_0,
+	mmROT0_QM_CP_FENCE0_RDATA_1,
+	mmROT0_QM_CP_FENCE0_RDATA_2,
+	mmROT0_QM_CP_FENCE0_RDATA_3,
+	mmROT0_QM_CP_FENCE0_RDATA_4,
+	mmROT0_QM_CP_FENCE1_RDATA_0,
+	mmROT0_QM_CP_FENCE1_RDATA_1,
+	mmROT0_QM_CP_FENCE1_RDATA_2,
+	mmROT0_QM_CP_FENCE1_RDATA_3,
+	mmROT0_QM_CP_FENCE1_RDATA_4,
+	mmROT0_QM_CP_FENCE2_RDATA_0,
+	mmROT0_QM_CP_FENCE2_RDATA_1,
+	mmROT0_QM_CP_FENCE2_RDATA_2,
+	mmROT0_QM_CP_FENCE2_RDATA_3,
+	mmROT0_QM_CP_FENCE2_RDATA_4,
+	mmROT0_QM_CP_FENCE3_RDATA_0,
+	mmROT0_QM_CP_FENCE3_RDATA_1,
+	mmROT0_QM_CP_FENCE3_RDATA_2,
+	mmROT0_QM_CP_FENCE3_RDATA_3,
+	mmROT0_QM_CP_FENCE3_RDATA_4,
+	mmROT0_QM_CP_FENCE0_CNT_0,
+	mmROT0_QM_CP_FENCE0_CNT_1,
+	mmROT0_QM_CP_FENCE0_CNT_2,
+	mmROT0_QM_CP_FENCE0_CNT_3,
+	mmROT0_QM_CP_FENCE0_CNT_4,
+	mmROT0_QM_CP_FENCE1_CNT_0,
+	mmROT0_QM_CP_FENCE1_CNT_1,
+	mmROT0_QM_CP_FENCE1_CNT_2,
+	mmROT0_QM_CP_FENCE1_CNT_3,
+	mmROT0_QM_CP_FENCE1_CNT_4,
+	mmROT0_QM_CP_FENCE2_CNT_0,
+	mmROT0_QM_CP_FENCE2_CNT_1,
+	mmROT0_QM_CP_FENCE2_CNT_2,
+	mmROT0_QM_CP_FENCE2_CNT_3,
+	mmROT0_QM_CP_FENCE2_CNT_4,
+	mmROT0_QM_CP_FENCE3_CNT_0,
+	mmROT0_QM_CP_FENCE3_CNT_1,
+	mmROT0_QM_CP_FENCE3_CNT_2,
+	mmROT0_QM_CP_FENCE3_CNT_3,
+	mmROT0_QM_CP_FENCE3_CNT_4,
+	mmROT0_QM_CQ_PTR_LO_0,
+	mmROT0_QM_CQ_PTR_HI_0,
+	mmROT0_QM_CQ_TSIZE_0,
+	mmROT0_QM_CQ_CTL_0,
+	mmROT0_QM_CQ_PTR_LO_1,
+	mmROT0_QM_CQ_PTR_HI_1,
+	mmROT0_QM_CQ_TSIZE_1,
+	mmROT0_QM_CQ_CTL_1,
+	mmROT0_QM_CQ_PTR_LO_2,
+	mmROT0_QM_CQ_PTR_HI_2,
+	mmROT0_QM_CQ_TSIZE_2,
+	mmROT0_QM_CQ_CTL_2,
+	mmROT0_QM_CQ_PTR_LO_3,
+	mmROT0_QM_CQ_PTR_HI_3,
+	mmROT0_QM_CQ_TSIZE_3,
+	mmROT0_QM_CQ_CTL_3,
+	mmROT0_QM_CQ_PTR_LO_4,
+	mmROT0_QM_CQ_PTR_HI_4,
+	mmROT0_QM_CQ_TSIZE_4,
+	mmROT0_QM_CQ_CTL_4,
+	mmROT0_QM_QMAN_WR64_BASE_ADDR0_BASE,
+	mmROT0_QM_QMAN_WR64_BASE_ADDR0_BASE + 4,
+	mmROT0_QM_QMAN_WR64_BASE_ADDR1_BASE,
+	mmROT0_QM_QMAN_WR64_BASE_ADDR1_BASE + 4,
+	mmROT0_QM_QMAN_WR64_BASE_ADDR2_BASE,
+	mmROT0_QM_QMAN_WR64_BASE_ADDR2_BASE + 4,
+	mmROT0_QM_QMAN_WR64_BASE_ADDR3_BASE,
+	mmROT0_QM_QMAN_WR64_BASE_ADDR3_BASE + 4,
+	mmROT0_QM_QMAN_WR64_BASE_ADDR4_BASE,
+	mmROT0_QM_QMAN_WR64_BASE_ADDR4_BASE + 4,
+	mmROT0_QM_QMAN_WR64_BASE_ADDR5_BASE,
+	mmROT0_QM_QMAN_WR64_BASE_ADDR5_BASE + 4,
+	mmROT0_QM_QMAN_WR64_BASE_ADDR6_BASE,
+	mmROT0_QM_QMAN_WR64_BASE_ADDR6_BASE + 4,
+	mmROT0_QM_QMAN_WR64_BASE_ADDR7_BASE,
+	mmROT0_QM_QMAN_WR64_BASE_ADDR7_BASE + 4,
+	mmROT0_QM_QMAN_WR64_BASE_ADDR8_BASE,
+	mmROT0_QM_QMAN_WR64_BASE_ADDR8_BASE + 4,
+	mmROT0_QM_QMAN_WR64_BASE_ADDR9_BASE,
+	mmROT0_QM_QMAN_WR64_BASE_ADDR9_BASE + 4,
+	mmROT0_QM_QMAN_WR64_BASE_ADDR10_BASE,
+	mmROT0_QM_QMAN_WR64_BASE_ADDR10_BASE + 4,
+	mmROT0_QM_QMAN_WR64_BASE_ADDR11_BASE,
+	mmROT0_QM_QMAN_WR64_BASE_ADDR11_BASE + 4,
+	mmROT0_QM_QMAN_WR64_BASE_ADDR12_BASE,
+	mmROT0_QM_QMAN_WR64_BASE_ADDR12_BASE + 4,
+	mmROT0_QM_QMAN_WR64_BASE_ADDR13_BASE,
+	mmROT0_QM_QMAN_WR64_BASE_ADDR13_BASE + 4,
+	mmROT0_QM_QMAN_WR64_BASE_ADDR14_BASE,
+	mmROT0_QM_QMAN_WR64_BASE_ADDR14_BASE + 4,
+	mmROT0_QM_QMAN_WR64_BASE_ADDR15_BASE,
+	mmROT0_QM_QMAN_WR64_BASE_ADDR15_BASE + 4,
+	mmROT0_QM_ARC_CQ_PTR_LO,
+	mmROT0_QM_ARC_CQ_PTR_LO_STS,
+	mmROT0_QM_ARC_CQ_PTR_HI,
+	mmROT0_QM_ARC_CQ_PTR_HI_STS,
+	mmROT0_QM_ARB_CFG_0,
+	mmROT0_QM_ARB_MST_QUIET_PER,
+	mmROT0_QM_ARB_CHOICE_Q_PUSH,
+	mmROT0_QM_ARB_WRR_WEIGHT_0,
+	mmROT0_QM_ARB_WRR_WEIGHT_1,
+	mmROT0_QM_ARB_WRR_WEIGHT_2,
+	mmROT0_QM_ARB_WRR_WEIGHT_3,
+	mmROT0_QM_ARB_BASE_LO,
+	mmROT0_QM_ARB_BASE_HI,
+	mmROT0_QM_ARB_MST_SLAVE_EN,
+	mmROT0_QM_ARB_MST_SLAVE_EN_1,
+	mmROT0_QM_ARB_MST_CRED_INC,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_0,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_1,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_2,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_3,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_4,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_5,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_6,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_7,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_8,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_9,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_10,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_11,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_12,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_13,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_14,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_15,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_16,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_17,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_18,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_19,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_20,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_21,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_22,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_23,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_24,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_25,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_26,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_27,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_28,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_29,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_30,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_31,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_32,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_33,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_34,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_35,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_36,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_37,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_38,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_39,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_40,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_41,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_42,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_43,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_44,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_45,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_46,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_47,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_48,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_49,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_50,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_51,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_52,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_53,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_54,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_55,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_56,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_57,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_58,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_59,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_60,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_61,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_62,
+	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_63,
+	mmROT0_QM_ARB_SLV_ID,
+	mmROT0_QM_ARB_SLV_MASTER_INC_CRED_OFST,
+	mmROT0_QM_ARC_CQ_CFG0,
+	mmROT0_QM_CQ_IFIFO_CI_0,
+	mmROT0_QM_CQ_IFIFO_CI_1,
+	mmROT0_QM_CQ_IFIFO_CI_2,
+	mmROT0_QM_CQ_IFIFO_CI_3,
+	mmROT0_QM_CQ_IFIFO_CI_4,
+	mmROT0_QM_ARC_CQ_IFIFO_CI,
+	mmROT0_QM_CQ_CTL_CI_0,
+	mmROT0_QM_CQ_CTL_CI_1,
+	mmROT0_QM_CQ_CTL_CI_2,
+	mmROT0_QM_CQ_CTL_CI_3,
+	mmROT0_QM_CQ_CTL_CI_4,
+	mmROT0_QM_ARC_CQ_CTL_CI,
+	mmROT0_QM_ARC_CQ_TSIZE,
+	mmROT0_QM_ARC_CQ_CTL,
+	mmROT0_QM_CP_SWITCH_WD_SET,
+	mmROT0_QM_CP_EXT_SWITCH,
+	mmROT0_QM_CP_PRED_0,
+	mmROT0_QM_CP_PRED_1,
+	mmROT0_QM_CP_PRED_2,
+	mmROT0_QM_CP_PRED_3,
+	mmROT0_QM_CP_PRED_4,
+	mmROT0_QM_CP_PRED_UPEN_0,
+	mmROT0_QM_CP_PRED_UPEN_1,
+	mmROT0_QM_CP_PRED_UPEN_2,
+	mmROT0_QM_CP_PRED_UPEN_3,
+	mmROT0_QM_CP_PRED_UPEN_4,
+	mmROT0_QM_CP_MSG_BASE0_ADDR_LO_0,
+	mmROT0_QM_CP_MSG_BASE0_ADDR_LO_1,
+	mmROT0_QM_CP_MSG_BASE0_ADDR_LO_2,
+	mmROT0_QM_CP_MSG_BASE0_ADDR_LO_3,
+	mmROT0_QM_CP_MSG_BASE0_ADDR_LO_4,
+	mmROT0_QM_CP_MSG_BASE0_ADDR_HI_0,
+	mmROT0_QM_CP_MSG_BASE0_ADDR_HI_1,
+	mmROT0_QM_CP_MSG_BASE0_ADDR_HI_2,
+	mmROT0_QM_CP_MSG_BASE0_ADDR_HI_3,
+	mmROT0_QM_CP_MSG_BASE0_ADDR_HI_4,
+	mmROT0_QM_CP_MSG_BASE1_ADDR_LO_0,
+	mmROT0_QM_CP_MSG_BASE1_ADDR_LO_1,
+	mmROT0_QM_CP_MSG_BASE1_ADDR_LO_2,
+	mmROT0_QM_CP_MSG_BASE1_ADDR_LO_3,
+	mmROT0_QM_CP_MSG_BASE1_ADDR_LO_4,
+	mmROT0_QM_CP_MSG_BASE1_ADDR_HI_0,
+	mmROT0_QM_CP_MSG_BASE1_ADDR_HI_1,
+	mmROT0_QM_CP_MSG_BASE1_ADDR_HI_2,
+	mmROT0_QM_CP_MSG_BASE1_ADDR_HI_3,
+	mmROT0_QM_CP_MSG_BASE1_ADDR_HI_4,
+	mmROT0_QM_CP_MSG_BASE2_ADDR_LO_0,
+	mmROT0_QM_CP_MSG_BASE2_ADDR_LO_1,
+	mmROT0_QM_CP_MSG_BASE2_ADDR_LO_2,
+	mmROT0_QM_CP_MSG_BASE2_ADDR_LO_3,
+	mmROT0_QM_CP_MSG_BASE2_ADDR_LO_4,
+	mmROT0_QM_CP_MSG_BASE2_ADDR_HI_0,
+	mmROT0_QM_CP_MSG_BASE2_ADDR_HI_1,
+	mmROT0_QM_CP_MSG_BASE2_ADDR_HI_2,
+	mmROT0_QM_CP_MSG_BASE2_ADDR_HI_3,
+	mmROT0_QM_CP_MSG_BASE2_ADDR_HI_4,
+	mmROT0_QM_CP_MSG_BASE3_ADDR_LO_0,
+	mmROT0_QM_CP_MSG_BASE3_ADDR_LO_1,
+	mmROT0_QM_CP_MSG_BASE3_ADDR_LO_2,
+	mmROT0_QM_CP_MSG_BASE3_ADDR_LO_3,
+	mmROT0_QM_CP_MSG_BASE3_ADDR_LO_4,
+	mmROT0_QM_CP_MSG_BASE3_ADDR_HI_0,
+	mmROT0_QM_CP_MSG_BASE3_ADDR_HI_1,
+	mmROT0_QM_CP_MSG_BASE3_ADDR_HI_2,
+	mmROT0_QM_CP_MSG_BASE3_ADDR_HI_3,
+	mmROT0_QM_CP_MSG_BASE3_ADDR_HI_4,
+	mmROT0_QM_ARC_CQ_IFIFO_MSG_BASE_LO,
+	mmROT0_QM_ARC_CQ_CTL_MSG_BASE_LO,
+	mmROT0_QM_CQ_IFIFO_MSG_BASE_LO,
+	mmROT0_QM_CQ_CTL_MSG_BASE_LO,
+	mmROT0_DESC_CONTEXT_ID,
+	mmROT0_DESC_IN_IMG_START_ADDR_L,
+	mmROT0_DESC_IN_IMG_START_ADDR_H,
+	mmROT0_DESC_OUT_IMG_START_ADDR_L,
+	mmROT0_DESC_OUT_IMG_START_ADDR_H,
+	mmROT0_DESC_CFG,
+	mmROT0_DESC_IM_READ_SLOPE,
+	mmROT0_DESC_SIN_D,
+	mmROT0_DESC_COS_D,
+	mmROT0_DESC_IN_IMG,
+	mmROT0_DESC_IN_STRIDE,
+	mmROT0_DESC_IN_STRIPE,
+	mmROT0_DESC_IN_CENTER,
+	mmROT0_DESC_OUT_IMG,
+	mmROT0_DESC_OUT_STRIDE,
+	mmROT0_DESC_OUT_STRIPE,
+	mmROT0_DESC_OUT_CENTER,
+	mmROT0_DESC_BACKGROUND,
+	mmROT0_DESC_CPL_MSG_EN,
+	mmROT0_DESC_IDLE_STATE,
+	mmROT0_DESC_CPL_MSG_ADDR,
+	mmROT0_DESC_CPL_MSG_DATA,
+	mmROT0_DESC_X_I_START_OFFSET,
+	mmROT0_DESC_X_I_START_OFFSET_FLIP,
+	mmROT0_DESC_X_I_FIRST,
+	mmROT0_DESC_Y_I_FIRST,
+	mmROT0_DESC_Y_I,
+	mmROT0_DESC_OUT_STRIPE_SIZE,
+	mmROT0_DESC_RSB_CFG_0,
+	mmROT0_DESC_RSB_PAD_VAL,
+	mmROT0_DESC_OWM_CFG,
+	mmROT0_DESC_CTRL_CFG,
+	mmROT0_DESC_PIXEL_PAD,
+	mmROT0_DESC_PREC_SHIFT,
+	mmROT0_DESC_MAX_VAL,
+	mmROT0_DESC_A0_M11,
+	mmROT0_DESC_A1_M12,
+	mmROT0_DESC_A2,
+	mmROT0_DESC_B0_M21,
+	mmROT0_DESC_B1_M22,
+	mmROT0_DESC_B2,
+	mmROT0_DESC_C0,
+	mmROT0_DESC_C1,
+	mmROT0_DESC_C2,
+	mmROT0_DESC_D0,
+	mmROT0_DESC_D1,
+	mmROT0_DESC_D2,
+	mmROT0_DESC_INV_PROC_SIZE_M_1,
+	mmROT0_DESC_MESH_IMG_START_ADDR_L,
+	mmROT0_DESC_MESH_IMG_START_ADDR_H,
+	mmROT0_DESC_MESH_IMG,
+	mmROT0_DESC_MESH_STRIDE,
+	mmROT0_DESC_MESH_STRIPE,
+	mmROT0_DESC_MESH_CTRL,
+	mmROT0_DESC_MESH_GH,
+	mmROT0_DESC_MESH_GV,
+	mmROT0_DESC_MRSB_CFG_0,
+	mmROT0_DESC_MRSB_PAD_VAL,
+	mmROT0_DESC_BUF_CFG,
+	mmROT0_DESC_CID_OFFSET,
+	mmROT0_DESC_PUSH_DESC
+};
+
+static const u32 gaudi2_pb_psoc_global_conf[] = {
+	mmPSOC_GLOBAL_CONF_BASE
+};
+
+static const u32 gaudi2_pb_psoc[] = {
+	mmPSOC_EFUSE_BASE,
+	mmPSOC_BTL_BASE,
+	mmPSOC_CS_TRACE_BASE,
+	mmPSOC_DFT_EFUSE_BASE,
+	mmPSOC_PID_BASE,
+	mmPSOC_ARC0_CFG_BASE,
+	mmPSOC_ARC0_MSTR_IF_RR_SHRD_HBW_BASE,
+	mmPSOC_ARC0_AUX_BASE,
+	mmPSOC_ARC1_CFG_BASE,
+	mmPSOC_ARC1_MSTR_IF_RR_SHRD_HBW_BASE,
+	mmPSOC_ARC1_AUX_BASE,
+	mmJT_MSTR_IF_RR_SHRD_HBW_BASE,
+	mmSMI_MSTR_IF_RR_SHRD_HBW_BASE,
+	mmI2C_S_MSTR_IF_RR_SHRD_HBW_BASE,
+	mmPSOC_SVID0_BASE,
+	mmPSOC_SVID1_BASE,
+	mmPSOC_SVID2_BASE,
+	mmPSOC_AVS0_BASE,
+	mmPSOC_AVS1_BASE,
+	mmPSOC_AVS2_BASE,
+	mmPSOC_PWM0_BASE,
+	mmPSOC_PWM1_BASE,
+	mmPSOC_MSTR_IF_RR_SHRD_HBW_BASE,
+};
+
+static const u32 gaudi2_pb_pmmu[] = {
+	mmPMMU_HBW_MMU_BASE,
+	mmPMMU_HBW_STLB_BASE,
+	mmPMMU_HBW_MSTR_IF_RR_SHRD_HBW_BASE,
+	mmPMMU_PIF_BASE,
+};
+
+static const u32 gaudi2_pb_psoc_pll[] = {
+	mmPSOC_MME_PLL_CTRL_BASE,
+	mmPSOC_CPU_PLL_CTRL_BASE,
+	mmPSOC_VID_PLL_CTRL_BASE
+};
+
+static const u32 gaudi2_pb_pmmu_pll[] = {
+	mmPMMU_MME_PLL_CTRL_BASE,
+	mmPMMU_VID_PLL_CTRL_BASE
+};
+
+static const u32 gaudi2_pb_xbar_pll[] = {
+	mmDCORE0_XBAR_DMA_PLL_CTRL_BASE,
+	mmDCORE0_XBAR_MMU_PLL_CTRL_BASE,
+	mmDCORE0_XBAR_IF_PLL_CTRL_BASE,
+	mmDCORE0_XBAR_MESH_PLL_CTRL_BASE,
+	mmDCORE1_XBAR_DMA_PLL_CTRL_BASE,
+	mmDCORE1_XBAR_MMU_PLL_CTRL_BASE,
+	mmDCORE1_XBAR_IF_PLL_CTRL_BASE,
+	mmDCORE1_XBAR_MESH_PLL_CTRL_BASE,
+	mmDCORE1_XBAR_HBM_PLL_CTRL_BASE,
+	mmDCORE2_XBAR_DMA_PLL_CTRL_BASE,
+	mmDCORE2_XBAR_MMU_PLL_CTRL_BASE,
+	mmDCORE2_XBAR_IF_PLL_CTRL_BASE,
+	mmDCORE2_XBAR_BANK_PLL_CTRL_BASE,
+	mmDCORE2_XBAR_HBM_PLL_CTRL_BASE,
+	mmDCORE3_XBAR_DMA_PLL_CTRL_BASE,
+	mmDCORE3_XBAR_MMU_PLL_CTRL_BASE,
+	mmDCORE3_XBAR_IF_PLL_CTRL_BASE,
+	mmDCORE3_XBAR_BANK_PLL_CTRL_BASE
+};
+
+static const u32 gaudi2_pb_xft_pll[] = {
+	mmDCORE0_HBM_PLL_CTRL_BASE,
+	mmDCORE0_TPC_PLL_CTRL_BASE,
+	mmDCORE0_PCI_PLL_CTRL_BASE,
+	mmDCORE1_HBM_PLL_CTRL_BASE,
+	mmDCORE1_TPC_PLL_CTRL_BASE,
+	mmDCORE1_NIC_PLL_CTRL_BASE,
+	mmDCORE2_HBM_PLL_CTRL_BASE,
+	mmDCORE2_TPC_PLL_CTRL_BASE,
+	mmDCORE3_HBM_PLL_CTRL_BASE,
+	mmDCORE3_TPC_PLL_CTRL_BASE,
+	mmDCORE3_NIC_PLL_CTRL_BASE,
+};
+
+static const u32 gaudi2_pb_pcie[] = {
+	mmPCIE_ELBI_RR_MSTR_IF_RR_SHRD_HBW_BASE,
+	mmPCIE_LBW_RR_MSTR_IF_RR_SHRD_HBW_BASE,
+	mmPCIE_MSTR_RR_MSTR_IF_RR_SHRD_HBW_BASE,
+	mmPCIE_WRAP_BASE,
+};
+
+static const u32 gaudi2_pb_pcie_unsecured_regs[] = {
+	mmPCIE_WRAP_SPECIAL_GLBL_SPARE_0,
+};
+
+static const u32 gaudi2_pb_thermal_sensor0[] = {
+	mmDCORE0_XFT_BASE,
+	mmDCORE0_TSTDVS_BASE,
+};
+
+static const u32 gaudi2_pb_hbm[] = {
+	mmHBM0_MC0_BASE,
+	mmHBM0_MC1_BASE,
+};
+
+static const u32 gaudi2_pb_mme_qm_arc_acp_eng[] = {
+	mmDCORE0_MME_QM_ARC_ACP_ENG_BASE,
+};
+
+static const struct range gaudi2_pb_mme_qm_arc_acp_eng_unsecured_regs[] = {
+	{mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_0, mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_REG},
+};
+
+struct gaudi2_tpc_pb_data {
+	struct hl_block_glbl_sec *glbl_sec;
+	u32 block_array_size;
+};
+
+static void gaudi2_config_tpcs_glbl_sec(struct hl_device *hdev, int dcore, int inst, u32 offset,
+						struct iterate_module_ctx *ctx)
+{
+	struct gaudi2_tpc_pb_data *pb_data = ctx->data;
+
+	hl_config_glbl_sec(hdev, gaudi2_pb_dcr0_tpc0, pb_data->glbl_sec,
+					offset, pb_data->block_array_size);
+}
+
+static int gaudi2_init_pb_tpc(struct hl_device *hdev)
+{
+	u32 stride, kernel_tensor_stride, qm_tensor_stride, block_array_size;
+	struct gaudi2_tpc_pb_data tpc_pb_data;
+	struct hl_block_glbl_sec *glbl_sec;
+	struct iterate_module_ctx tpc_iter;
+	int i;
+
+	block_array_size = ARRAY_SIZE(gaudi2_pb_dcr0_tpc0);
+
+	glbl_sec = kcalloc(block_array_size, sizeof(struct hl_block_glbl_sec), GFP_KERNEL);
+	if (!glbl_sec)
+		return -ENOMEM;
+
+	kernel_tensor_stride = mmDCORE0_TPC0_CFG_KERNEL_TENSOR_1_BASE -
+				mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE;
+	qm_tensor_stride = mmDCORE0_TPC0_CFG_QM_TENSOR_1_BASE - mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE;
+
+	hl_secure_block(hdev, glbl_sec, block_array_size);
+	hl_unsecure_registers(hdev, gaudi2_pb_dcr0_tpc0_unsecured_regs,
+			ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_unsecured_regs),
+			0, gaudi2_pb_dcr0_tpc0, glbl_sec,
+			block_array_size);
+
+	/* Unsecure all TPC kernel tensors */
+	for (i = 0 ; i < TPC_NUM_OF_KERNEL_TENSORS ; i++)
+		hl_unsecure_registers(hdev,
+			gaudi2_pb_dcr0_tpc0_ktensor_unsecured_regs,
+			ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_ktensor_unsecured_regs),
+			i * kernel_tensor_stride, gaudi2_pb_dcr0_tpc0,
+			glbl_sec, block_array_size);
+
+	/* Unsecure all TPC QM tensors */
+	for (i = 0 ; i < TPC_NUM_OF_QM_TENSORS ; i++)
+		hl_unsecure_registers(hdev,
+			gaudi2_pb_dcr0_tpc0_qtensor_unsecured_regs,
+			ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_qtensor_unsecured_regs),
+			i * qm_tensor_stride,
+			gaudi2_pb_dcr0_tpc0, glbl_sec, block_array_size);
+
+	/* unsecure all 32 TPC QM SRF regs */
+	stride = mmDCORE0_TPC0_CFG_QM_SRF_1 - mmDCORE0_TPC0_CFG_QM_SRF_0;
+	for (i = 0 ; i < 32 ; i++)
+		hl_unsecure_register(hdev, mmDCORE0_TPC0_CFG_QM_SRF_0,
+				i * stride, gaudi2_pb_dcr0_tpc0, glbl_sec,
+				block_array_size);
+
+	/* unsecure the 4 TPC LOCK VALUE regs */
+	stride = mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_1 - mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_0;
+	for (i = 0 ; i < 4 ; i++)
+		hl_unsecure_register(hdev, mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_0,
+				i * stride, gaudi2_pb_dcr0_tpc0, glbl_sec,
+				block_array_size);
+
+	/* prepare data for TPC iterator */
+	tpc_pb_data.glbl_sec = glbl_sec;
+	tpc_pb_data.block_array_size = block_array_size;
+	tpc_iter.fn = &gaudi2_config_tpcs_glbl_sec;
+	tpc_iter.data = &tpc_pb_data;
+	gaudi2_iterate_tpcs(hdev, &tpc_iter);
+
+	kfree(glbl_sec);
+
+	return 0;
+}
+
+struct gaudi2_tpc_arc_pb_data {
+	u32 unsecured_regs_arr_size;
+	u32 arc_regs_arr_size;
+};
+
+static void gaudi2_config_tpcs_pb_ranges(struct hl_device *hdev, int dcore, int inst, u32 offset,
+						struct iterate_module_ctx *ctx)
+{
+	struct gaudi2_tpc_arc_pb_data *pb_data = ctx->data;
+
+	ctx->rc = hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA, 1,
+					offset, gaudi2_pb_dcr0_tpc0_arc,
+					pb_data->arc_regs_arr_size,
+					gaudi2_pb_dcr0_tpc0_arc_unsecured_regs,
+					pb_data->unsecured_regs_arr_size);
+}
+
+static int gaudi2_init_pb_tpc_arc(struct hl_device *hdev)
+{
+	struct gaudi2_tpc_arc_pb_data tpc_arc_pb_data;
+	struct iterate_module_ctx tpc_iter;
+
+	tpc_arc_pb_data.arc_regs_arr_size = ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_arc);
+	tpc_arc_pb_data.unsecured_regs_arr_size =
+			ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_arc_unsecured_regs);
+
+	tpc_iter.fn = &gaudi2_config_tpcs_pb_ranges;
+	tpc_iter.data = &tpc_arc_pb_data;
+	gaudi2_iterate_tpcs(hdev, &tpc_iter);
+
+	return tpc_iter.rc;
+}
+
+static int gaudi2_init_pb_sm_objs(struct hl_device *hdev)
+{
+	int i, j, glbl_sec_array_len = gaudi2_pb_dcr0_sm_objs.glbl_sec_length;
+	u32 sec_entry, *sec_array, array_base, first_sob, first_mon;
+
+	array_base = gaudi2_pb_dcr0_sm_objs.mm_block_base_addr +
+				gaudi2_pb_dcr0_sm_objs.glbl_sec_offset;
+
+	sec_array = kcalloc(glbl_sec_array_len, sizeof(u32), GFP_KERNEL);
+	if (!sec_array)
+		return -ENOMEM;
+
+	first_sob = GAUDI2_RESERVED_SOB_NUMBER;
+	first_mon = GAUDI2_RESERVED_MON_NUMBER;
+
+	/* 8192 SOB_OBJs skipping first GAUDI2_MAX_PENDING_CS of them */
+	for (j = i = first_sob ; i < DCORE_NUM_OF_SOB ; i++, j++)
+		UNSET_GLBL_SEC_BIT(sec_array, j);
+
+	/* 2048 MON_PAY ADDR_L skipping first GAUDI2_MAX_PENDING_CS of them */
+	for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)
+		UNSET_GLBL_SEC_BIT(sec_array, j);
+
+	/* 2048 MON_PAY ADDR_H skipping first GAUDI2_MAX_PENDING_CS of them */
+	for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)
+		UNSET_GLBL_SEC_BIT(sec_array, j);
+
+	/* 2048 MON_PAY DATA skipping first GAUDI2_MAX_PENDING_CS of them */
+	for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)
+		UNSET_GLBL_SEC_BIT(sec_array, j);
+
+	/* 2048 MON_ARM skipping first GAUDI2_MAX_PENDING_CS of them */
+	for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)
+		UNSET_GLBL_SEC_BIT(sec_array, j);
+
+	/* 2048 MON_CONFIG skipping first GAUDI2_MAX_PENDING_CS of them */
+	for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)
+		UNSET_GLBL_SEC_BIT(sec_array, j);
+
+	/* 2048 MON_STATUS skipping first GAUDI2_MAX_PENDING_CS of them */
+	for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)
+		UNSET_GLBL_SEC_BIT(sec_array, j);
+
+	/* Unsecure selected Dcore0 registers */
+	for (i = 0 ; i < glbl_sec_array_len ; i++) {
+		sec_entry = array_base + i * sizeof(u32);
+		WREG32(sec_entry, sec_array[i]);
+	}
+
+	/* Unsecure Dcore1 - Dcore3 registers */
+	memset(sec_array, -1, glbl_sec_array_len * sizeof(u32));
+
+	for (i = 1 ; i < NUM_OF_DCORES ; i++) {
+		for (j = 0 ; j < glbl_sec_array_len ; j++) {
+			sec_entry = DCORE_OFFSET * i + array_base + j * sizeof(u32);
+			WREG32(sec_entry, sec_array[j]);
+		}
+	}
+
+	kfree(sec_array);
+
+	return 0;
+}
+
+static void gaudi2_write_lbw_range_register(struct hl_device *hdev, u64 base, void *data)
+{
+	u32 reg_min_offset, reg_max_offset, write_min, write_max;
+	struct rr_config *rr_cfg = (struct rr_config *) data;
+
+	switch (rr_cfg->type) {
+	case RR_TYPE_SHORT:
+		reg_min_offset = RR_LBW_SEC_RANGE_MIN_SHORT_0_OFFSET;
+		reg_max_offset = RR_LBW_SEC_RANGE_MAX_SHORT_0_OFFSET;
+		break;
+
+	case RR_TYPE_LONG:
+		reg_min_offset = RR_LBW_SEC_RANGE_MIN_0_OFFSET;
+		reg_max_offset = RR_LBW_SEC_RANGE_MAX_0_OFFSET;
+		break;
+
+	case RR_TYPE_SHORT_PRIV:
+		reg_min_offset = RR_LBW_PRIV_RANGE_MIN_SHORT_0_OFFSET;
+		reg_max_offset = RR_LBW_PRIV_RANGE_MAX_SHORT_0_OFFSET;
+		break;
+
+	case RR_TYPE_LONG_PRIV:
+		reg_min_offset = RR_LBW_PRIV_RANGE_MIN_0_OFFSET;
+		reg_max_offset = RR_LBW_PRIV_RANGE_MAX_0_OFFSET;
+		break;
+
+	default:
+		dev_err(hdev->dev, "Invalid LBW RR type %u\n", rr_cfg->type);
+		return;
+	}
+
+	reg_min_offset += rr_cfg->index * sizeof(u32);
+	reg_max_offset += rr_cfg->index * sizeof(u32);
+
+	if (rr_cfg->type == RR_TYPE_SHORT || rr_cfg->type == RR_TYPE_SHORT_PRIV) {
+		write_min = FIELD_GET(RR_LBW_SHORT_MASK, lower_32_bits(rr_cfg->min));
+		write_max = FIELD_GET(RR_LBW_SHORT_MASK, lower_32_bits(rr_cfg->max));
+
+	} else {
+		write_min = FIELD_GET(RR_LBW_LONG_MASK, lower_32_bits(rr_cfg->min));
+		write_max = FIELD_GET(RR_LBW_LONG_MASK, lower_32_bits(rr_cfg->max));
+	}
+
+	/* Configure LBW RR:
+	 * Both RR types start blocking from base address 0x1000007FF8000000
+	 * SHORT RRs address bits [26:12]
+	 * LONG RRs address bits [26:0]
+	 */
+	WREG32(base + reg_min_offset, write_min);
+	WREG32(base + reg_max_offset, write_max);
+}
+
+void gaudi2_write_rr_to_all_lbw_rtrs(struct hl_device *hdev, u8 rr_type, u32 rr_index, u64 min_val,
+					u64 max_val)
+{
+	struct dup_block_ctx block_ctx;
+	struct rr_config rr_cfg;
+
+	if ((rr_type == RR_TYPE_SHORT || rr_type == RR_TYPE_SHORT_PRIV) &&
+								rr_index >= NUM_SHORT_LBW_RR) {
+
+		dev_err(hdev->dev, "invalid short LBW %s range register index: %u",
+			rr_type == RR_TYPE_SHORT ? "secure" : "privileged", rr_index);
+		return;
+	}
+
+	if ((rr_type == RR_TYPE_LONG || rr_type == RR_TYPE_LONG_PRIV) &&
+								rr_index >= NUM_LONG_LBW_RR) {
+
+		dev_err(hdev->dev, "invalid long LBW %s range register index: %u",
+			rr_type == RR_TYPE_LONG ? "secure" : "privileged", rr_index);
+		return;
+	}
+
+	rr_cfg.type = rr_type;
+	rr_cfg.index = rr_index;
+	rr_cfg.min = min_val;
+	rr_cfg.max = max_val;
+
+	block_ctx.instance_cfg_fn = &gaudi2_write_lbw_range_register;
+	block_ctx.data = &rr_cfg;
+
+	/* SFT */
+	block_ctx.base = mmSFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_BASE;
+	block_ctx.blocks = NUM_OF_SFT;
+	block_ctx.block_off = SFT_OFFSET;
+	block_ctx.instances = SFT_NUM_OF_LBW_RTR;
+	block_ctx.instance_off = SFT_LBW_RTR_OFFSET;
+	gaudi2_init_blocks(hdev, &block_ctx);
+
+	/* SIF */
+	block_ctx.base = mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE;
+	block_ctx.blocks = NUM_OF_DCORES;
+	block_ctx.block_off = DCORE_OFFSET;
+	block_ctx.instances = NUM_OF_RTR_PER_DCORE;
+	block_ctx.instance_off = DCORE_RTR_OFFSET;
+	gaudi2_init_blocks(hdev, &block_ctx);
+
+	block_ctx.blocks = 1;
+	block_ctx.block_off = 0;
+	block_ctx.instances = 1;
+	block_ctx.instance_off = 0;
+
+	/* PCIE ELBI */
+	block_ctx.base = mmPCIE_ELBI_RR_MSTR_IF_RR_SHRD_LBW_BASE;
+	gaudi2_init_blocks(hdev, &block_ctx);
+
+	/* PCIE MSTR */
+	block_ctx.base = mmPCIE_MSTR_RR_MSTR_IF_RR_SHRD_LBW_BASE;
+	gaudi2_init_blocks(hdev, &block_ctx);
+
+	/* PCIE LBW */
+	block_ctx.base = mmPCIE_LBW_RR_MSTR_IF_RR_SHRD_LBW_BASE;
+	gaudi2_init_blocks(hdev, &block_ctx);
+}
+
+static void gaudi2_init_lbw_range_registers_secure(struct hl_device *hdev)
+{
+	int i;
+
+	/* Up to 14 14bit-address regs.
+	 *
+	 * - range 0: NIC0_CFG
+	 * - range 1: NIC1_CFG
+	 * - range 2: NIC2_CFG
+	 * - range 3: NIC3_CFG
+	 * - range 4: NIC4_CFG
+	 * - range 5: NIC5_CFG
+	 * - range 6: NIC6_CFG
+	 * - range 7: NIC7_CFG
+	 * - range 8: NIC8_CFG
+	 * - range 9: NIC9_CFG
+	 * - range 10: NIC10_CFG
+	 * - range 11: NIC11_CFG + *_DBG (not including TPC_DBG)
+	 *
+	 * If F/W security is not enabled:
+	 * - ranges 12,13: PSOC_CFG (excluding PSOC_TIMESTAMP, PSOC_EFUSE and PSOC_GLOBAL_CONF)
+	 */
+	u64 lbw_range_min_short[] = {
+		mmNIC0_TX_AXUSER_BASE,
+		mmNIC1_TX_AXUSER_BASE,
+		mmNIC2_TX_AXUSER_BASE,
+		mmNIC3_TX_AXUSER_BASE,
+		mmNIC4_TX_AXUSER_BASE,
+		mmNIC5_TX_AXUSER_BASE,
+		mmNIC6_TX_AXUSER_BASE,
+		mmNIC7_TX_AXUSER_BASE,
+		mmNIC8_TX_AXUSER_BASE,
+		mmNIC9_TX_AXUSER_BASE,
+		mmNIC10_TX_AXUSER_BASE,
+		mmNIC11_TX_AXUSER_BASE,
+		mmPSOC_I2C_M0_BASE,
+		mmPSOC_GPIO0_BASE
+	};
+	u64 lbw_range_max_short[] = {
+		mmNIC0_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
+		mmNIC1_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
+		mmNIC2_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
+		mmNIC3_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
+		mmNIC4_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
+		mmNIC5_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
+		mmNIC6_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
+		mmNIC7_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
+		mmNIC8_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
+		mmNIC9_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
+		mmNIC10_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
+		mmNIC11_DBG_FUNNEL_NCH_BASE + HL_BLOCK_SIZE,
+		mmPSOC_WDOG_BASE + HL_BLOCK_SIZE,
+		mmSVID2_AC_BASE + HL_BLOCK_SIZE
+	};
+
+	/* Up to 4 26bit-address regs.
+	 *
+	 * - range 0: TPC_DBG
+	 * - range 1: PCIE_DBI.MSIX_DOORBELL_OFF
+	 * - range 2/3: used in soft reset to block access to several blocks and are cleared here
+	 */
+	u64 lbw_range_min_long[] = {
+		mmDCORE0_TPC0_ROM_TABLE_BASE,
+		mmPCIE_DBI_MSIX_DOORBELL_OFF,
+		0x0,
+		0x0
+	};
+	u64 lbw_range_max_long[] = {
+		mmDCORE3_TPC5_EML_CS_BASE + HL_BLOCK_SIZE,
+		mmPCIE_DBI_MSIX_DOORBELL_OFF + 0x4,
+		0x0,
+		0x0
+	};
+
+	/* write short range registers to all lbw rtrs */
+	for (i = 0 ; i < ARRAY_SIZE(lbw_range_min_short) ; i++) {
+		if ((lbw_range_min_short[i] == mmPSOC_I2C_M0_BASE ||
+				lbw_range_min_short[i] == mmPSOC_EFUSE_BASE) &&
+				hdev->asic_prop.fw_security_enabled)
+			continue;
+
+		gaudi2_write_rr_to_all_lbw_rtrs(hdev, RR_TYPE_SHORT, i,
+				lbw_range_min_short[i], lbw_range_max_short[i]);
+	}
+
+	/* write long range registers to all lbw rtrs */
+	for (i = 0 ; i < ARRAY_SIZE(lbw_range_min_long) ; i++) {
+		gaudi2_write_rr_to_all_lbw_rtrs(hdev, RR_TYPE_LONG, i,
+				lbw_range_min_long[i], lbw_range_max_long[i]);
+	}
+}
+
+static void gaudi2_init_lbw_range_registers(struct hl_device *hdev)
+{
+	gaudi2_init_lbw_range_registers_secure(hdev);
+}
+
+static void gaudi2_write_hbw_range_register(struct hl_device *hdev, u64 base, void *data)
+{
+	u32 min_lo_reg_offset, min_hi_reg_offset, max_lo_reg_offset, max_hi_reg_offset;
+	struct rr_config *rr_cfg = (struct rr_config *) data;
+	u64 val_min, val_max;
+
+	switch (rr_cfg->type) {
+	case RR_TYPE_SHORT:
+		min_lo_reg_offset = RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_0_OFFSET;
+		min_hi_reg_offset = RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_0_OFFSET;
+		max_lo_reg_offset = RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_0_OFFSET;
+		max_hi_reg_offset = RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_0_OFFSET;
+		break;
+
+	case RR_TYPE_LONG:
+		min_lo_reg_offset = RR_SHRD_HBW_SEC_RANGE_MIN_LO_0_OFFSET;
+		min_hi_reg_offset = RR_SHRD_HBW_SEC_RANGE_MIN_HI_0_OFFSET;
+		max_lo_reg_offset = RR_SHRD_HBW_SEC_RANGE_MAX_LO_0_OFFSET;
+		max_hi_reg_offset = RR_SHRD_HBW_SEC_RANGE_MAX_HI_0_OFFSET;
+		break;
+
+	case RR_TYPE_SHORT_PRIV:
+		min_lo_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_0_OFFSET;
+		min_hi_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_0_OFFSET;
+		max_lo_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_0_OFFSET;
+		max_hi_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_0_OFFSET;
+		break;
+
+	case RR_TYPE_LONG_PRIV:
+		min_lo_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MIN_LO_0_OFFSET;
+		min_hi_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MIN_HI_0_OFFSET;
+		max_lo_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MAX_LO_0_OFFSET;
+		max_hi_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MAX_HI_0_OFFSET;
+		break;
+
+	default:
+		dev_err(hdev->dev, "Invalid HBW RR type %u\n", rr_cfg->type);
+		return;
+	}
+
+	min_lo_reg_offset += rr_cfg->index * sizeof(u32);
+	min_hi_reg_offset += rr_cfg->index * sizeof(u32);
+	max_lo_reg_offset += rr_cfg->index * sizeof(u32);
+	max_hi_reg_offset += rr_cfg->index * sizeof(u32);
+
+	if (rr_cfg->type == RR_TYPE_SHORT || rr_cfg->type == RR_TYPE_SHORT_PRIV) {
+		val_min = FIELD_GET(RR_HBW_SHORT_HI_MASK, rr_cfg->min) |
+				FIELD_GET(RR_HBW_SHORT_LO_MASK, rr_cfg->min);
+		val_max = FIELD_GET(RR_HBW_SHORT_HI_MASK, rr_cfg->max) |
+				FIELD_GET(RR_HBW_SHORT_LO_MASK, rr_cfg->max);
+	} else {
+		val_min = FIELD_GET(RR_HBW_LONG_HI_MASK, rr_cfg->min) |
+				FIELD_GET(RR_HBW_LONG_LO_MASK, rr_cfg->min);
+		val_max = FIELD_GET(RR_HBW_LONG_HI_MASK, rr_cfg->max) |
+				FIELD_GET(RR_HBW_LONG_LO_MASK, rr_cfg->max);
+	}
+
+	/* Configure HBW RR:
+	 * SHORT RRs (0x1000_<36bits>000) - HI: address bits [47:44], LO: address bits [43:12]
+	 * LONG  RRs (0x<52bits>000)      - HI: address bits [63:44], LO: address bits [43:12]
+	 */
+	WREG32(base + min_lo_reg_offset, lower_32_bits(val_min));
+	WREG32(base + min_hi_reg_offset, upper_32_bits(val_min));
+	WREG32(base + max_lo_reg_offset, lower_32_bits(val_max));
+	WREG32(base + max_hi_reg_offset, upper_32_bits(val_max));
+}
+
+static void gaudi2_write_hbw_rr_to_all_mstr_if(struct hl_device *hdev, u8 rr_type, u32 rr_index,
+						u64 min_val, u64 max_val)
+{
+	struct dup_block_ctx block_ctx;
+	struct rr_config rr_cfg;
+
+	if ((rr_type == RR_TYPE_SHORT || rr_type == RR_TYPE_SHORT_PRIV) &&
+								rr_index >= NUM_SHORT_HBW_RR) {
+
+		dev_err(hdev->dev, "invalid short HBW %s range register index: %u",
+			rr_type == RR_TYPE_SHORT ? "secure" : "privileged", rr_index);
+		return;
+	}
+
+	if ((rr_type == RR_TYPE_LONG || rr_type == RR_TYPE_LONG_PRIV) &&
+								rr_index >= NUM_LONG_HBW_RR) {
+
+		dev_err(hdev->dev, "invalid long HBW %s range register index: %u",
+			rr_type == RR_TYPE_LONG ? "secure" : "privileged", rr_index);
+		return;
+	}
+
+	rr_cfg.type = rr_type;
+	rr_cfg.index = rr_index;
+	rr_cfg.min = min_val;
+	rr_cfg.max = max_val;
+
+	block_ctx.instance_cfg_fn = &gaudi2_write_hbw_range_register;
+	block_ctx.data = &rr_cfg;
+
+	/* SFT */
+	block_ctx.base = mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE;
+	block_ctx.blocks = NUM_OF_SFT;
+	block_ctx.block_off = SFT_OFFSET;
+	block_ctx.instances = SFT_NUM_OF_HBW_RTR;
+	block_ctx.instance_off = SFT_IF_RTR_OFFSET;
+	gaudi2_init_blocks(hdev, &block_ctx);
+
+	/* SIF */
+	block_ctx.base = mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE;
+	block_ctx.blocks = NUM_OF_DCORES;
+	block_ctx.block_off = DCORE_OFFSET;
+	block_ctx.instances = NUM_OF_RTR_PER_DCORE;
+	block_ctx.instance_off = DCORE_RTR_OFFSET;
+	gaudi2_init_blocks(hdev, &block_ctx);
+
+	/* PCIE MSTR */
+	block_ctx.base = mmPCIE_MSTR_RR_MSTR_IF_RR_SHRD_HBW_BASE;
+	block_ctx.blocks = 1;
+	block_ctx.block_off = 0;
+	block_ctx.instances = 1;
+	block_ctx.instance_off = 0;
+	gaudi2_init_blocks(hdev, &block_ctx);
+}
+
+static void gaudi2_init_hbw_range_registers(struct hl_device *hdev)
+{
+	int i;
+
+	/* Up to 6 short RR (0x1000_<36bits>000) and 4 long RR (0x<52bits>000).
+	 *
+	 * - short range 0:
+	 *	SPI Flash, ARC0/1 ICCM/DCCM, Secure Boot ROM, PSOC_FW/Scratchpad/PCIE_FW SRAM
+	 */
+	u64 hbw_range_min_short[] = {
+		SPI_FLASH_BASE_ADDR
+	};
+	u64 hbw_range_max_short[] = {
+		PCIE_FW_SRAM_ADDR + PCIE_FW_SRAM_SIZE
+	};
+
+	for (i = 0 ; i < ARRAY_SIZE(hbw_range_min_short) ; i++) {
+		gaudi2_write_hbw_rr_to_all_mstr_if(hdev, RR_TYPE_SHORT, i, hbw_range_min_short[i],
+							hbw_range_max_short[i]);
+	}
+}
+
+static void gaudi2_write_mmu_range_register(struct hl_device *hdev, u64 base,
+						struct rr_config *rr_cfg)
+{
+	u32 min_lo_reg_offset, min_hi_reg_offset, max_lo_reg_offset, max_hi_reg_offset;
+
+	switch (rr_cfg->type) {
+	case RR_TYPE_LONG:
+		min_lo_reg_offset = MMU_RR_SEC_MIN_31_0_0_OFFSET;
+		min_hi_reg_offset = MMU_RR_SEC_MIN_63_32_0_OFFSET;
+		max_lo_reg_offset = MMU_RR_SEC_MAX_31_0_0_OFFSET;
+		max_hi_reg_offset = MMU_RR_SEC_MAX_63_32_0_OFFSET;
+		break;
+
+	case RR_TYPE_LONG_PRIV:
+		min_lo_reg_offset = MMU_RR_PRIV_MIN_31_0_0_OFFSET;
+		min_hi_reg_offset = MMU_RR_PRIV_MIN_63_32_0_OFFSET;
+		max_lo_reg_offset = MMU_RR_PRIV_MAX_31_0_0_OFFSET;
+		max_hi_reg_offset = MMU_RR_PRIV_MAX_63_32_0_OFFSET;
+		break;
+
+	default:
+		dev_err(hdev->dev, "Invalid MMU RR type %u\n", rr_cfg->type);
+		return;
+	}
+
+	min_lo_reg_offset += rr_cfg->index * sizeof(u32);
+	min_hi_reg_offset += rr_cfg->index * sizeof(u32);
+	max_lo_reg_offset += rr_cfg->index * sizeof(u32);
+	max_hi_reg_offset += rr_cfg->index * sizeof(u32);
+
+	/* Configure MMU RR (address bits [63:0]) */
+	WREG32(base + min_lo_reg_offset, lower_32_bits(rr_cfg->min));
+	WREG32(base + min_hi_reg_offset, upper_32_bits(rr_cfg->min));
+	WREG32(base + max_lo_reg_offset, lower_32_bits(rr_cfg->max));
+	WREG32(base + max_hi_reg_offset, upper_32_bits(rr_cfg->max));
+}
+
+static void gaudi2_init_mmu_range_registers(struct hl_device *hdev)
+{
+	u32 dcore_id, hmmu_id, hmmu_base;
+	struct rr_config rr_cfg;
+
+	/* Up to 8 ranges [63:0].
+	 *
+	 * - range 0: Reserved HBM area for F/W and driver
+	 */
+
+	/* The RRs are located after the HMMU so need to use the scrambled addresses */
+	rr_cfg.min = hdev->asic_funcs->scramble_addr(hdev, DRAM_PHYS_BASE);
+	rr_cfg.max = hdev->asic_funcs->scramble_addr(hdev, hdev->asic_prop.dram_user_base_address);
+	rr_cfg.index = 0;
+	rr_cfg.type = RR_TYPE_LONG;
+
+	for (dcore_id = 0 ; dcore_id < NUM_OF_DCORES ; dcore_id++) {
+		for (hmmu_id = 0 ; hmmu_id < NUM_OF_HMMU_PER_DCORE; hmmu_id++) {
+			if (!gaudi2_is_hmmu_enabled(hdev, dcore_id, hmmu_id))
+				continue;
+
+			hmmu_base = mmDCORE0_HMMU0_MMU_BASE + dcore_id * DCORE_OFFSET +
+					hmmu_id * DCORE_HMMU_OFFSET;
+
+			gaudi2_write_mmu_range_register(hdev, hmmu_base, &rr_cfg);
+		}
+	}
+}
+
+/**
+ * gaudi2_init_range_registers -
+ * Initialize range registers of all initiators
+ *
+ * @hdev: pointer to hl_device structure
+ */
+static void gaudi2_init_range_registers(struct hl_device *hdev)
+{
+	gaudi2_init_lbw_range_registers(hdev);
+	gaudi2_init_hbw_range_registers(hdev);
+	gaudi2_init_mmu_range_registers(hdev);
+}
+
+/**
+ * gaudi2_init_protection_bits -
+ * Initialize protection bits of specific registers
+ *
+ * @hdev: pointer to hl_device structure
+ *
+ * All protection bits are 1 by default, means not protected. Need to set to 0
+ * each bit that belongs to a protected register.
+ *
+ */
+static int gaudi2_init_protection_bits(struct hl_device *hdev)
+{
+	u32 *user_regs_array = NULL, user_regs_array_size = 0, engine_core_intr_reg;
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	u32 instance_offset;
+	int rc = 0;
+	u8 i;
+
+	/* SFT */
+	instance_offset = mmSFT1_HBW_RTR_IF0_RTR_CTRL_BASE - mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE;
+	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,
+			gaudi2_pb_sft0, ARRAY_SIZE(gaudi2_pb_sft0),
+			NULL, HL_PB_NA);
+
+	/* HIF */
+	instance_offset = mmDCORE0_HIF1_BASE - mmDCORE0_HIF0_BASE;
+	rc |= hl_init_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
+			NUM_OF_HIF_PER_DCORE, instance_offset,
+			gaudi2_pb_dcr0_hif, ARRAY_SIZE(gaudi2_pb_dcr0_hif),
+			NULL, HL_PB_NA, prop->hmmu_hif_enabled_mask);
+
+	/* RTR */
+	instance_offset = mmDCORE0_RTR1_CTRL_BASE - mmDCORE0_RTR0_CTRL_BASE;
+	rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,
+			gaudi2_pb_dcr0_rtr0, ARRAY_SIZE(gaudi2_pb_dcr0_rtr0),
+			NULL, HL_PB_NA);
+
+	/* HMMU */
+	rc |= hl_init_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
+			NUM_OF_HMMU_PER_DCORE, DCORE_HMMU_OFFSET,
+			gaudi2_pb_dcr0_hmmu0, ARRAY_SIZE(gaudi2_pb_dcr0_hmmu0),
+			NULL, HL_PB_NA, prop->hmmu_hif_enabled_mask);
+
+	/* CPU.
+	 * Except for CPU_IF, skip when security is enabled in F/W, because the blocks are protected
+	 * by privileged RR.
+	 */
+	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
+			HL_PB_SINGLE_INSTANCE, HL_PB_NA,
+			gaudi2_pb_cpu_if, ARRAY_SIZE(gaudi2_pb_cpu_if),
+			NULL, HL_PB_NA);
+
+	if (!hdev->asic_prop.fw_security_enabled)
+		rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
+				HL_PB_SINGLE_INSTANCE, HL_PB_NA,
+				gaudi2_pb_cpu, ARRAY_SIZE(gaudi2_pb_cpu),
+				NULL, HL_PB_NA);
+
+	/* KDMA */
+	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
+			HL_PB_SINGLE_INSTANCE, HL_PB_NA,
+			gaudi2_pb_kdma, ARRAY_SIZE(gaudi2_pb_kdma),
+			NULL, HL_PB_NA);
+
+	/* PDMA */
+	instance_offset = mmPDMA1_CORE_BASE - mmPDMA0_CORE_BASE;
+	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 2, instance_offset,
+			gaudi2_pb_pdma0, ARRAY_SIZE(gaudi2_pb_pdma0),
+			gaudi2_pb_pdma0_unsecured_regs,
+			ARRAY_SIZE(gaudi2_pb_pdma0_unsecured_regs));
+
+	/* ARC PDMA */
+	rc |= hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA, 2,
+			instance_offset, gaudi2_pb_pdma0_arc,
+			ARRAY_SIZE(gaudi2_pb_pdma0_arc),
+			gaudi2_pb_pdma0_arc_unsecured_regs,
+			ARRAY_SIZE(gaudi2_pb_pdma0_arc_unsecured_regs));
+
+	/* EDMA */
+	instance_offset = mmDCORE0_EDMA1_CORE_BASE - mmDCORE0_EDMA0_CORE_BASE;
+	rc |= hl_init_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,
+			instance_offset, gaudi2_pb_dcr0_edma0,
+			ARRAY_SIZE(gaudi2_pb_dcr0_edma0),
+			gaudi2_pb_dcr0_edma0_unsecured_regs,
+			ARRAY_SIZE(gaudi2_pb_dcr0_edma0_unsecured_regs),
+			prop->edma_enabled_mask);
+
+	/* ARC EDMA */
+	rc |= hl_init_pb_ranges_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,
+			instance_offset, gaudi2_pb_dcr0_edma0_arc,
+			ARRAY_SIZE(gaudi2_pb_dcr0_edma0_arc),
+			gaudi2_pb_dcr0_edma0_arc_unsecured_regs,
+			ARRAY_SIZE(gaudi2_pb_dcr0_edma0_arc_unsecured_regs),
+			prop->edma_enabled_mask);
+
+	/* MME */
+	instance_offset = mmDCORE0_MME_SBTE1_BASE - mmDCORE0_MME_SBTE0_BASE;
+
+	for (i = 0 ; i < NUM_OF_DCORES * NUM_OF_MME_PER_DCORE ; i++) {
+		/* MME SBTE */
+		rc |= hl_init_pb_single_dcore(hdev, (DCORE_OFFSET * i), 5,
+				instance_offset, gaudi2_pb_dcr0_mme_sbte,
+				ARRAY_SIZE(gaudi2_pb_dcr0_mme_sbte), NULL,
+				HL_PB_NA);
+
+		/* MME */
+		rc |= hl_init_pb_single_dcore(hdev, (DCORE_OFFSET * i),
+				HL_PB_SINGLE_INSTANCE, HL_PB_NA,
+				gaudi2_pb_dcr0_mme_eng,
+				ARRAY_SIZE(gaudi2_pb_dcr0_mme_eng),
+				gaudi2_pb_dcr0_mme_eng_unsecured_regs,
+				ARRAY_SIZE(gaudi2_pb_dcr0_mme_eng_unsecured_regs));
+	}
+
+	/*
+	 * we have special iteration for case in which we would like to
+	 * configure stubbed MME's ARC/QMAN
+	 */
+	for (i = 0 ; i < NUM_OF_DCORES * NUM_OF_MME_PER_DCORE ; i++) {
+		/* MME QM */
+		rc |= hl_init_pb_single_dcore(hdev, (DCORE_OFFSET * i),
+				HL_PB_SINGLE_INSTANCE, HL_PB_NA,
+				gaudi2_pb_dcr0_mme_qm,
+				ARRAY_SIZE(gaudi2_pb_dcr0_mme_qm),
+				gaudi2_pb_dcr0_mme_qm_unsecured_regs,
+				ARRAY_SIZE(gaudi2_pb_dcr0_mme_qm_unsecured_regs));
+
+		/* ARC MME */
+		rc |= hl_init_pb_ranges_single_dcore(hdev, (DCORE_OFFSET * i),
+			HL_PB_SINGLE_INSTANCE, HL_PB_NA,
+			gaudi2_pb_dcr0_mme_arc,
+			ARRAY_SIZE(gaudi2_pb_dcr0_mme_arc),
+			gaudi2_pb_dcr0_mme_arc_unsecured_regs,
+			ARRAY_SIZE(gaudi2_pb_dcr0_mme_arc_unsecured_regs));
+	}
+
+	/* MME QM ARC ACP ENG */
+	rc |= hl_init_pb_ranges_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
+			HL_PB_SINGLE_INSTANCE, HL_PB_NA,
+			gaudi2_pb_mme_qm_arc_acp_eng,
+			ARRAY_SIZE(gaudi2_pb_mme_qm_arc_acp_eng),
+			gaudi2_pb_mme_qm_arc_acp_eng_unsecured_regs,
+			ARRAY_SIZE(gaudi2_pb_mme_qm_arc_acp_eng_unsecured_regs),
+			(BIT(NUM_OF_DCORES * NUM_OF_MME_PER_DCORE) - 1));
+
+	/* TPC */
+	rc |= gaudi2_init_pb_tpc(hdev);
+	rc |= gaudi2_init_pb_tpc_arc(hdev);
+
+	/* SRAM */
+	instance_offset = mmDCORE0_SRAM1_BANK_BASE - mmDCORE0_SRAM0_BANK_BASE;
+	rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,
+			gaudi2_pb_dcr0_sram0, ARRAY_SIZE(gaudi2_pb_dcr0_sram0),
+			NULL, HL_PB_NA);
+
+	/* Sync Manager MSTR IF */
+	rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET,
+			HL_PB_SINGLE_INSTANCE, HL_PB_NA,
+			gaudi2_pb_dcr0_sm_mstr_if,
+			ARRAY_SIZE(gaudi2_pb_dcr0_sm_mstr_if),
+			NULL, HL_PB_NA);
+
+	/* Sync Manager GLBL */
+
+	/* Secure Dcore0 CQ0 registers */
+	rc |= hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA,
+			HL_PB_SINGLE_INSTANCE, HL_PB_NA,
+			gaudi2_pb_dcr0_sm_glbl,
+			ARRAY_SIZE(gaudi2_pb_dcr0_sm_glbl),
+			gaudi2_pb_dcr0_sm_glbl_unsecured_regs,
+			ARRAY_SIZE(gaudi2_pb_dcr0_sm_glbl_unsecured_regs));
+
+	/* Unsecure all other CQ registers */
+	rc |= hl_init_pb_ranges(hdev, NUM_OF_DCORES - 1, DCORE_OFFSET,
+			HL_PB_SINGLE_INSTANCE, HL_PB_NA,
+			gaudi2_pb_dcr1_sm_glbl,
+			ARRAY_SIZE(gaudi2_pb_dcr1_sm_glbl),
+			gaudi2_pb_dcr_x_sm_glbl_unsecured_regs,
+			ARRAY_SIZE(gaudi2_pb_dcr_x_sm_glbl_unsecured_regs));
+
+	/* PSOC.
+	 * Except for PSOC_GLOBAL_CONF, skip when security is enabled in F/W, because the blocks are
+	 * protected by privileged RR.
+	 * For PSOC_GLOBAL_CONF, need to un-secure the scratchpad register which is used for engine
+	 * cores to raise events towards F/W.
+	 */
+	engine_core_intr_reg = (u32) (hdev->asic_prop.engine_core_interrupt_reg_addr - CFG_BASE);
+	if (engine_core_intr_reg >= mmPSOC_GLOBAL_CONF_SCRATCHPAD_0 &&
+			engine_core_intr_reg <= mmPSOC_GLOBAL_CONF_SCRATCHPAD_31) {
+		user_regs_array = &engine_core_intr_reg;
+		user_regs_array_size = 1;
+	} else {
+		dev_err(hdev->dev,
+			"Engine cores register for interrupts (%#x) is not a PSOC scratchpad register\n",
+			engine_core_intr_reg);
+	}
+
+	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
+			HL_PB_SINGLE_INSTANCE, HL_PB_NA,
+			gaudi2_pb_psoc_global_conf, ARRAY_SIZE(gaudi2_pb_psoc_global_conf),
+			user_regs_array, user_regs_array_size);
+
+	if (!hdev->asic_prop.fw_security_enabled)
+		rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
+				HL_PB_SINGLE_INSTANCE, HL_PB_NA,
+				gaudi2_pb_psoc, ARRAY_SIZE(gaudi2_pb_psoc),
+				NULL, HL_PB_NA);
+
+	/* PMMU */
+	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
+			HL_PB_SINGLE_INSTANCE, HL_PB_NA,
+			gaudi2_pb_pmmu, ARRAY_SIZE(gaudi2_pb_pmmu),
+			NULL, HL_PB_NA);
+
+	/* PLL.
+	 * Skip PSOC/XFT PLL when security is enabled in F/W, because these blocks are protected by
+	 * privileged RR.
+	 */
+	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
+			HL_PB_SINGLE_INSTANCE, HL_PB_NA,
+			gaudi2_pb_pmmu_pll, ARRAY_SIZE(gaudi2_pb_pmmu_pll),
+			NULL, HL_PB_NA);
+	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
+			HL_PB_SINGLE_INSTANCE, HL_PB_NA,
+			gaudi2_pb_xbar_pll, ARRAY_SIZE(gaudi2_pb_xbar_pll),
+			NULL, HL_PB_NA);
+
+	if (!hdev->asic_prop.fw_security_enabled) {
+		rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
+				HL_PB_SINGLE_INSTANCE, HL_PB_NA,
+				gaudi2_pb_psoc_pll, ARRAY_SIZE(gaudi2_pb_psoc_pll),
+				NULL, HL_PB_NA);
+		rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
+				HL_PB_SINGLE_INSTANCE, HL_PB_NA,
+				gaudi2_pb_xft_pll, ARRAY_SIZE(gaudi2_pb_xft_pll),
+				NULL, HL_PB_NA);
+	}
+
+	/* PCIE */
+	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
+			HL_PB_SINGLE_INSTANCE, HL_PB_NA,
+			gaudi2_pb_pcie, ARRAY_SIZE(gaudi2_pb_pcie),
+			gaudi2_pb_pcie_unsecured_regs,
+			ARRAY_SIZE(gaudi2_pb_pcie_unsecured_regs));
+
+	/* Thermal Sensor.
+	 * Skip when security is enabled in F/W, because the blocks are protected by privileged RR.
+	 */
+	if (!hdev->asic_prop.fw_security_enabled) {
+		instance_offset = mmDCORE1_XFT_BASE - mmDCORE0_XFT_BASE;
+		rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,
+				gaudi2_pb_thermal_sensor0,
+				ARRAY_SIZE(gaudi2_pb_thermal_sensor0), NULL, HL_PB_NA);
+	}
+
+	/* Scheduler ARCs */
+	instance_offset = mmARC_FARM_ARC1_AUX_BASE - mmARC_FARM_ARC0_AUX_BASE;
+	rc |= hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA,
+			NUM_OF_ARC_FARMS_ARC,
+			instance_offset, gaudi2_pb_arc_sched,
+			ARRAY_SIZE(gaudi2_pb_arc_sched),
+			gaudi2_pb_arc_sched_unsecured_regs,
+			ARRAY_SIZE(gaudi2_pb_arc_sched_unsecured_regs));
+
+	/* XBAR MIDs */
+	instance_offset = mmXBAR_MID_1_BASE - mmXBAR_MID_0_BASE;
+	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR,
+			instance_offset, gaudi2_pb_xbar_mid,
+			ARRAY_SIZE(gaudi2_pb_xbar_mid),
+			gaudi2_pb_xbar_mid_unsecured_regs,
+			ARRAY_SIZE(gaudi2_pb_xbar_mid_unsecured_regs));
+
+	/* XBAR EDGEs */
+	instance_offset = mmXBAR_EDGE_1_BASE - mmXBAR_EDGE_0_BASE;
+	rc |= hl_init_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR,
+			instance_offset, gaudi2_pb_xbar_edge,
+			ARRAY_SIZE(gaudi2_pb_xbar_edge),
+			gaudi2_pb_xbar_edge_unsecured_regs,
+			ARRAY_SIZE(gaudi2_pb_xbar_edge_unsecured_regs),
+			prop->xbar_edge_enabled_mask);
+
+	/* NIC */
+	rc |= hl_init_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET,
+			HL_PB_SINGLE_INSTANCE, HL_PB_NA,
+			gaudi2_pb_nic0, ARRAY_SIZE(gaudi2_pb_nic0),
+			NULL, HL_PB_NA, hdev->nic_ports_mask);
+
+	/* NIC QM and QPC */
+	rc |= hl_init_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET,
+			NIC_NUMBER_OF_QM_PER_MACRO, NIC_QM_OFFSET,
+			gaudi2_pb_nic0_qm_qpc, ARRAY_SIZE(gaudi2_pb_nic0_qm_qpc),
+			gaudi2_pb_nic0_qm_qpc_unsecured_regs,
+			ARRAY_SIZE(gaudi2_pb_nic0_qm_qpc_unsecured_regs),
+			hdev->nic_ports_mask);
+
+	/* NIC QM ARC */
+	rc |= hl_init_pb_ranges_with_mask(hdev, NIC_NUMBER_OF_MACROS,
+			NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO, NIC_QM_OFFSET,
+			gaudi2_pb_nic0_qm_arc_aux0,
+			ARRAY_SIZE(gaudi2_pb_nic0_qm_arc_aux0),
+			gaudi2_pb_nic0_qm_arc_aux0_unsecured_regs,
+			ARRAY_SIZE(gaudi2_pb_nic0_qm_arc_aux0_unsecured_regs),
+			hdev->nic_ports_mask);
+
+	/* NIC UMR */
+	rc |= hl_init_pb_ranges_with_mask(hdev, NIC_NUMBER_OF_MACROS,
+			NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO, NIC_QM_OFFSET,
+			gaudi2_pb_nic0_umr,
+			ARRAY_SIZE(gaudi2_pb_nic0_umr),
+			gaudi2_pb_nic0_umr_unsecured_regs,
+			ARRAY_SIZE(gaudi2_pb_nic0_umr_unsecured_regs),
+			hdev->nic_ports_mask);
+
+	/* Rotators */
+	instance_offset = mmROT1_BASE - mmROT0_BASE;
+	rc |= hl_init_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ROT,
+			instance_offset, gaudi2_pb_rot0,
+			ARRAY_SIZE(gaudi2_pb_rot0),
+			gaudi2_pb_rot0_unsecured_regs,
+			ARRAY_SIZE(gaudi2_pb_rot0_unsecured_regs),
+			(BIT(NUM_OF_ROT) - 1));
+
+	/* Rotators ARCS */
+	rc |= hl_init_pb_ranges_with_mask(hdev, HL_PB_SHARED,
+			HL_PB_NA, NUM_OF_ROT, instance_offset,
+			gaudi2_pb_rot0_arc, ARRAY_SIZE(gaudi2_pb_rot0_arc),
+			gaudi2_pb_rot0_arc_unsecured_regs,
+			ARRAY_SIZE(gaudi2_pb_rot0_arc_unsecured_regs),
+			(BIT(NUM_OF_ROT) - 1));
+
+	rc |= gaudi2_init_pb_sm_objs(hdev);
+
+	return rc;
+}
+
+/**
+ * gaudi2_init_security - Initialize security model
+ *
+ * @hdev: pointer to hl_device structure
+ *
+ * Initialize the security model of the device
+ * That includes range registers and protection bit per register.
+ */
+int gaudi2_init_security(struct hl_device *hdev)
+{
+	int rc;
+
+	rc = gaudi2_init_protection_bits(hdev);
+	if (rc)
+		return rc;
+
+	gaudi2_init_range_registers(hdev);
+
+	return 0;
+}
+
+struct gaudi2_ack_pb_tpc_data {
+	u32 tpc_regs_array_size;
+	u32 arc_tpc_regs_array_size;
+};
+
+static void gaudi2_ack_pb_tpc_config(struct hl_device *hdev, int dcore, int inst, u32 offset,
+					struct iterate_module_ctx *ctx)
+{
+	struct gaudi2_ack_pb_tpc_data *pb_data = ctx->data;
+
+	hl_ack_pb_single_dcore(hdev, offset, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
+				gaudi2_pb_dcr0_tpc0, pb_data->tpc_regs_array_size);
+
+	hl_ack_pb_single_dcore(hdev, offset, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
+				gaudi2_pb_dcr0_tpc0_arc, pb_data->arc_tpc_regs_array_size);
+}
+
+static void gaudi2_ack_pb_tpc(struct hl_device *hdev)
+{
+	struct iterate_module_ctx tpc_iter = {
+		.fn = &gaudi2_ack_pb_tpc_config,
+	};
+	struct gaudi2_ack_pb_tpc_data data;
+
+	data.tpc_regs_array_size = ARRAY_SIZE(gaudi2_pb_dcr0_tpc0);
+	data.arc_tpc_regs_array_size = ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_arc);
+	tpc_iter.data = &data;
+
+	gaudi2_iterate_tpcs(hdev, &tpc_iter);
+}
+
+/**
+ * gaudi2_ack_protection_bits_errors - scan all blocks having protection bits
+ * and for every protection error found, display the appropriate error message
+ * and clear the error.
+ *
+ * @hdev: pointer to hl_device structure
+ *
+ * All protection bits are 1 by default, means not protected. Need to set to 0
+ * each bit that belongs to a protected register.
+ *
+ */
+void gaudi2_ack_protection_bits_errors(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	u32 instance_offset;
+	u8 i;
+
+	/* SFT */
+	instance_offset = mmSFT1_HBW_RTR_IF0_RTR_CTRL_BASE - mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE;
+	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,
+			gaudi2_pb_sft0, ARRAY_SIZE(gaudi2_pb_sft0));
+
+	/* HIF */
+	instance_offset = mmDCORE0_HIF1_BASE - mmDCORE0_HIF0_BASE;
+	hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
+			NUM_OF_HIF_PER_DCORE, instance_offset,
+			gaudi2_pb_dcr0_hif, ARRAY_SIZE(gaudi2_pb_dcr0_hif),
+			prop->hmmu_hif_enabled_mask);
+
+	/* RTR */
+	instance_offset = mmDCORE0_RTR1_CTRL_BASE - mmDCORE0_RTR0_CTRL_BASE;
+	hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,
+			gaudi2_pb_dcr0_rtr0, ARRAY_SIZE(gaudi2_pb_dcr0_rtr0));
+
+	/* HMMU */
+	hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
+			NUM_OF_HMMU_PER_DCORE, DCORE_HMMU_OFFSET,
+			gaudi2_pb_dcr0_hmmu0, ARRAY_SIZE(gaudi2_pb_dcr0_hmmu0),
+			prop->hmmu_hif_enabled_mask);
+
+	/* CPU.
+	 * Except for CPU_IF, skip when security is enabled in F/W, because the blocks are protected
+	 * by privileged RR.
+	 */
+	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
+			gaudi2_pb_cpu_if, ARRAY_SIZE(gaudi2_pb_cpu_if));
+	if (!hdev->asic_prop.fw_security_enabled)
+		hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
+				gaudi2_pb_cpu, ARRAY_SIZE(gaudi2_pb_cpu));
+
+	/* KDMA */
+	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
+			gaudi2_pb_kdma, ARRAY_SIZE(gaudi2_pb_kdma));
+
+	/* PDMA */
+	instance_offset = mmPDMA1_CORE_BASE - mmPDMA0_CORE_BASE;
+	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 2, instance_offset,
+			gaudi2_pb_pdma0, ARRAY_SIZE(gaudi2_pb_pdma0));
+
+	/* ARC PDMA */
+	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 2, instance_offset,
+			gaudi2_pb_pdma0_arc, ARRAY_SIZE(gaudi2_pb_pdma0_arc));
+
+	/* EDMA */
+	instance_offset = mmDCORE0_EDMA1_CORE_BASE - mmDCORE0_EDMA0_CORE_BASE;
+	hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,
+			instance_offset, gaudi2_pb_dcr0_edma0,
+			ARRAY_SIZE(gaudi2_pb_dcr0_edma0),
+			prop->edma_enabled_mask);
+
+	/* ARC EDMA */
+	hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,
+			instance_offset, gaudi2_pb_dcr0_edma0_arc,
+			ARRAY_SIZE(gaudi2_pb_dcr0_edma0_arc),
+			prop->edma_enabled_mask);
+
+	/* MME */
+	instance_offset = mmDCORE0_MME_SBTE1_BASE - mmDCORE0_MME_SBTE0_BASE;
+
+	for (i = 0 ; i < NUM_OF_DCORES * NUM_OF_MME_PER_DCORE ; i++) {
+		/* MME SBTE */
+		hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i), 5,
+				instance_offset, gaudi2_pb_dcr0_mme_sbte,
+				ARRAY_SIZE(gaudi2_pb_dcr0_mme_sbte));
+
+		/* MME */
+		hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i),
+				HL_PB_SINGLE_INSTANCE, HL_PB_NA,
+				gaudi2_pb_dcr0_mme_eng,
+				ARRAY_SIZE(gaudi2_pb_dcr0_mme_eng));
+	}
+
+	/*
+	 * we have special iteration for case in which we would like to
+	 * configure stubbed MME's ARC/QMAN
+	 */
+	for (i = 0 ; i < NUM_OF_DCORES * NUM_OF_MME_PER_DCORE ; i++) {
+		/* MME QM */
+		hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i),
+				HL_PB_SINGLE_INSTANCE, HL_PB_NA,
+				gaudi2_pb_dcr0_mme_qm,
+				ARRAY_SIZE(gaudi2_pb_dcr0_mme_qm));
+
+		/* ARC MME */
+		hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i),
+				HL_PB_SINGLE_INSTANCE, HL_PB_NA,
+				gaudi2_pb_dcr0_mme_arc,
+				ARRAY_SIZE(gaudi2_pb_dcr0_mme_arc));
+	}
+
+	/* MME QM ARC ACP ENG */
+	hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
+			HL_PB_SINGLE_INSTANCE, HL_PB_NA,
+			gaudi2_pb_mme_qm_arc_acp_eng,
+			ARRAY_SIZE(gaudi2_pb_mme_qm_arc_acp_eng),
+			(BIT(NUM_OF_DCORES * NUM_OF_MME_PER_DCORE) - 1));
+
+	/* TPC */
+	gaudi2_ack_pb_tpc(hdev);
+
+	/* SRAM */
+	instance_offset = mmDCORE0_SRAM1_BANK_BASE - mmDCORE0_SRAM0_BANK_BASE;
+	hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,
+			gaudi2_pb_dcr0_sram0, ARRAY_SIZE(gaudi2_pb_dcr0_sram0));
+
+	/* Sync Manager MSTR IF */
+	hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
+			gaudi2_pb_dcr0_sm_mstr_if, ARRAY_SIZE(gaudi2_pb_dcr0_sm_mstr_if));
+
+	/* Sync Manager */
+	hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
+			gaudi2_pb_dcr0_sm_glbl, ARRAY_SIZE(gaudi2_pb_dcr0_sm_glbl));
+
+	hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
+			gaudi2_pb_dcr0_sm_mstr_if, ARRAY_SIZE(gaudi2_pb_dcr0_sm_mstr_if));
+
+	/* PSOC.
+	 * Except for PSOC_GLOBAL_CONF, skip when security is enabled in F/W, because the blocks are
+	 * protected by privileged RR.
+	 */
+	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
+			gaudi2_pb_psoc_global_conf, ARRAY_SIZE(gaudi2_pb_psoc_global_conf));
+	if (!hdev->asic_prop.fw_security_enabled)
+		hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
+				gaudi2_pb_psoc, ARRAY_SIZE(gaudi2_pb_psoc));
+
+	/* PMMU */
+	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
+			gaudi2_pb_pmmu, ARRAY_SIZE(gaudi2_pb_pmmu));
+
+	/* PLL.
+	 * Skip PSOC/XFT PLL when security is enabled in F/W, because these blocks are protected by
+	 * privileged RR.
+	 */
+	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
+			gaudi2_pb_pmmu_pll, ARRAY_SIZE(gaudi2_pb_pmmu_pll));
+	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
+			gaudi2_pb_xbar_pll, ARRAY_SIZE(gaudi2_pb_xbar_pll));
+	if (!hdev->asic_prop.fw_security_enabled) {
+		hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
+				gaudi2_pb_psoc_pll, ARRAY_SIZE(gaudi2_pb_psoc_pll));
+		hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
+				gaudi2_pb_xft_pll, ARRAY_SIZE(gaudi2_pb_xft_pll));
+	}
+
+	/* PCIE */
+	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
+			gaudi2_pb_pcie, ARRAY_SIZE(gaudi2_pb_pcie));
+
+	/* Thermal Sensor.
+	 * Skip when security is enabled in F/W, because the blocks are protected by privileged RR.
+	 */
+	if (!hdev->asic_prop.fw_security_enabled) {
+		instance_offset = mmDCORE1_XFT_BASE - mmDCORE0_XFT_BASE;
+		hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,
+				gaudi2_pb_thermal_sensor0, ARRAY_SIZE(gaudi2_pb_thermal_sensor0));
+	}
+
+	/* HBM */
+	instance_offset = mmHBM1_MC0_BASE - mmHBM0_MC0_BASE;
+	hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, GAUDI2_HBM_NUM,
+			instance_offset, gaudi2_pb_hbm,
+			ARRAY_SIZE(gaudi2_pb_hbm), prop->dram_enabled_mask);
+
+	/* Scheduler ARCs */
+	instance_offset = mmARC_FARM_ARC1_AUX_BASE - mmARC_FARM_ARC0_AUX_BASE;
+	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ARC_FARMS_ARC,
+			instance_offset, gaudi2_pb_arc_sched,
+			ARRAY_SIZE(gaudi2_pb_arc_sched));
+
+	/* XBAR MIDs */
+	instance_offset = mmXBAR_MID_1_BASE - mmXBAR_MID_0_BASE;
+	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR,
+			instance_offset, gaudi2_pb_xbar_mid,
+			ARRAY_SIZE(gaudi2_pb_xbar_mid));
+
+	/* XBAR EDGEs */
+	instance_offset = mmXBAR_EDGE_1_BASE - mmXBAR_EDGE_0_BASE;
+	hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR,
+			instance_offset, gaudi2_pb_xbar_edge,
+			ARRAY_SIZE(gaudi2_pb_xbar_edge), prop->xbar_edge_enabled_mask);
+
+	/* NIC */
+	hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
+			gaudi2_pb_nic0, ARRAY_SIZE(gaudi2_pb_nic0), hdev->nic_ports_mask);
+
+	/* NIC QM and QPC */
+	hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO,
+			NIC_QM_OFFSET, gaudi2_pb_nic0_qm_qpc, ARRAY_SIZE(gaudi2_pb_nic0_qm_qpc),
+			hdev->nic_ports_mask);
+
+	/* NIC QM ARC */
+	hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO,
+			NIC_QM_OFFSET, gaudi2_pb_nic0_qm_arc_aux0,
+			ARRAY_SIZE(gaudi2_pb_nic0_qm_arc_aux0), hdev->nic_ports_mask);
+
+	/* NIC UMR */
+	hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO,
+			NIC_QM_OFFSET, gaudi2_pb_nic0_umr, ARRAY_SIZE(gaudi2_pb_nic0_umr),
+			hdev->nic_ports_mask);
+
+	/* Rotators */
+	instance_offset = mmROT1_BASE - mmROT0_BASE;
+	hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ROT, instance_offset,
+			gaudi2_pb_rot0, ARRAY_SIZE(gaudi2_pb_rot0), (BIT(NUM_OF_ROT) - 1));
+
+	/* Rotators ARCS */
+	hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ROT, instance_offset,
+			gaudi2_pb_rot0_arc, ARRAY_SIZE(gaudi2_pb_rot0_arc), (BIT(NUM_OF_ROT) - 1));
+}
+
+/*
+ * Print PB security errors
+ */
+
+void gaudi2_pb_print_security_errors(struct hl_device *hdev, u32 block_addr, u32 cause,
+					u32 offended_addr)
+{
+	int i = 0;
+	const char *error_format =
+		"Security error at block 0x%x, offending address 0x%x\n"
+		"Cause 0x%x: %s %s %s %s %s %s %s %s\n";
+	char *mcause[8] = {"Unknown", "", "", "", "", "", "", "" };
+
+	if (!cause)
+		return;
+
+	if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD)
+		mcause[i++] = "APB_PRIV_RD";
+
+	if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD)
+		mcause[i++] = "APB_SEC_RD";
+
+	if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD)
+		mcause[i++] = "APB_UNMAPPED_RD";
+
+	if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR)
+		mcause[i++] = "APB_PRIV_WR";
+
+	if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR)
+		mcause[i++] = "APB_SEC_WR";
+
+	if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR)
+		mcause[i++] = "APB_UNMAPPED_WR";
+
+	if (cause & SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR)
+		mcause[i++] = "EXT_SEC_WR";
+
+	if (cause & SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR)
+		mcause[i++] = "APB_EXT_UNMAPPED_WR";
+
+	dev_err_ratelimited(hdev->dev, error_format, block_addr, offended_addr,
+			cause, mcause[0], mcause[1], mcause[2], mcause[3],
+			mcause[4], mcause[5], mcause[6], mcause[7]);
+}
diff --git a/drivers/accel/habanalabs/goya/Makefile b/drivers/accel/habanalabs/goya/Makefile
new file mode 100644
index 000000000000..b3f3b7b96683
--- /dev/null
+++ b/drivers/accel/habanalabs/goya/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+HL_GOYA_FILES :=  goya/goya.o goya/goya_security.o goya/goya_hwmgr.o \
+	goya/goya_coresight.o
diff --git a/drivers/misc/habanalabs/goya/goya.c b/drivers/accel/habanalabs/goya/goya.c
index 68f065607544..84768e306269 100644
--- a/drivers/misc/habanalabs/goya/goya.c
+++ b/drivers/accel/habanalabs/goya/goya.c
@@ -1,20 +1,18 @@
 // SPDX-License-Identifier: GPL-2.0
 
 /*
- * Copyright 2016-2019 HabanaLabs, Ltd.
+ * Copyright 2016-2022 HabanaLabs, Ltd.
  * All Rights Reserved.
  */
 
 #include "goyaP.h"
-#include "include/hw_ip/mmu/mmu_general.h"
-#include "include/hw_ip/mmu/mmu_v1_0.h"
-#include "include/goya/asic_reg/goya_masks.h"
-#include "include/goya/goya_reg_map.h"
+#include "../include/hw_ip/mmu/mmu_general.h"
+#include "../include/hw_ip/mmu/mmu_v1_0.h"
+#include "../include/goya/asic_reg/goya_masks.h"
+#include "../include/goya/goya_reg_map.h"
 
 #include <linux/pci.h>
-#include <linux/genalloc.h>
 #include <linux/hwmon.h>
-#include <linux/io-64-nonatomic-lo-hi.h>
 #include <linux/iommu.h>
 #include <linux/seq_file.h>
 
@@ -72,7 +70,7 @@
  *
  */
 
-#define GOYA_UBOOT_FW_FILE	"habanalabs/goya/goya-u-boot.bin"
+#define GOYA_BOOT_FIT_FILE	"habanalabs/goya/goya-boot-fit.itb"
 #define GOYA_LINUX_FW_FILE	"habanalabs/goya/goya-fit.itb"
 
 #define GOYA_MMU_REGS_NUM		63
@@ -87,6 +85,9 @@
 #define GOYA_TEST_QUEUE_WAIT_USEC	100000		/* 100ms */
 #define GOYA_PLDM_MMU_TIMEOUT_USEC	(MMU_CONFIG_TIMEOUT_USEC * 100)
 #define GOYA_PLDM_QMAN0_TIMEOUT_USEC	(HL_DEVICE_TIMEOUT_USEC * 30)
+#define GOYA_BOOT_FIT_REQ_TIMEOUT_USEC	1000000		/* 1s */
+#define GOYA_MSG_TO_CPU_TIMEOUT_USEC	4000000		/* 4s */
+#define GOYA_WAIT_FOR_BL_TIMEOUT_USEC	15000000	/* 15s */
 
 #define GOYA_QMAN0_FENCE_VAL		0xD169B243
 
@@ -118,7 +119,6 @@
 #define IS_MME_IDLE(mme_arch_sts) \
 	(((mme_arch_sts) & MME_ARCH_IDLE_MASK) == MME_ARCH_IDLE_MASK)
 
-
 static const char goya_irq_name[GOYA_MSIX_ENTRIES][GOYA_MAX_STRING_LEN] = {
 		"goya cq 0", "goya cq 1", "goya cq 2", "goya cq 3",
 		"goya cq 4", "goya cpu eq"
@@ -137,6 +137,25 @@ static u16 goya_packet_sizes[MAX_PACKET_ID] = {
 	[PACKET_STOP]		= sizeof(struct packet_stop)
 };
 
+static inline bool validate_packet_id(enum packet_id id)
+{
+	switch (id) {
+	case PACKET_WREG_32:
+	case PACKET_WREG_BULK:
+	case PACKET_MSG_LONG:
+	case PACKET_MSG_SHORT:
+	case PACKET_CP_DMA:
+	case PACKET_MSG_PROT:
+	case PACKET_FENCE:
+	case PACKET_LIN_DMA:
+	case PACKET_NOP:
+	case PACKET_STOP:
+		return true;
+	default:
+		return false;
+	}
+}
+
 static u64 goya_mmu_regs[GOYA_MMU_REGS_NUM] = {
 	mmDMA_QM_0_GLBL_NON_SECURE_PROPS,
 	mmDMA_QM_1_GLBL_NON_SECURE_PROPS,
@@ -331,40 +350,51 @@ static u32 goya_all_events[] = {
 	GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_E
 };
 
+static s64 goya_state_dump_specs_props[SP_MAX] = {0};
+
 static int goya_mmu_clear_pgt_range(struct hl_device *hdev);
 static int goya_mmu_set_dram_default_page(struct hl_device *hdev);
 static int goya_mmu_add_mappings_for_device_cpu(struct hl_device *hdev);
 static void goya_mmu_prepare(struct hl_device *hdev, u32 asid);
 
-void goya_get_fixed_properties(struct hl_device *hdev)
+int goya_set_fixed_properties(struct hl_device *hdev)
 {
 	struct asic_fixed_properties *prop = &hdev->asic_prop;
 	int i;
 
+	prop->max_queues = GOYA_QUEUE_ID_SIZE;
+	prop->hw_queues_props = kcalloc(prop->max_queues,
+			sizeof(struct hw_queue_properties),
+			GFP_KERNEL);
+
+	if (!prop->hw_queues_props)
+		return -ENOMEM;
+
 	for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++) {
 		prop->hw_queues_props[i].type = QUEUE_TYPE_EXT;
 		prop->hw_queues_props[i].driver_only = 0;
-		prop->hw_queues_props[i].requires_kernel_cb = 1;
+		prop->hw_queues_props[i].cb_alloc_flags = CB_ALLOC_KERNEL;
 	}
 
 	for (; i < NUMBER_OF_EXT_HW_QUEUES + NUMBER_OF_CPU_HW_QUEUES ; i++) {
 		prop->hw_queues_props[i].type = QUEUE_TYPE_CPU;
 		prop->hw_queues_props[i].driver_only = 1;
-		prop->hw_queues_props[i].requires_kernel_cb = 0;
+		prop->hw_queues_props[i].cb_alloc_flags = CB_ALLOC_KERNEL;
 	}
 
 	for (; i < NUMBER_OF_EXT_HW_QUEUES + NUMBER_OF_CPU_HW_QUEUES +
 			NUMBER_OF_INT_HW_QUEUES; i++) {
 		prop->hw_queues_props[i].type = QUEUE_TYPE_INT;
 		prop->hw_queues_props[i].driver_only = 0;
-		prop->hw_queues_props[i].requires_kernel_cb = 0;
+		prop->hw_queues_props[i].cb_alloc_flags = CB_ALLOC_USER;
 	}
 
-	for (; i < HL_MAX_QUEUES; i++)
-		prop->hw_queues_props[i].type = QUEUE_TYPE_NA;
-
+	prop->cfg_base_address = CFG_BASE;
+	prop->device_dma_offset_for_host_access = HOST_PHYS_BASE;
+	prop->host_base_address = HOST_PHYS_BASE;
+	prop->host_end_address = prop->host_base_address + HOST_PHYS_SIZE;
 	prop->completion_queues_count = NUMBER_OF_CMPLT_QUEUES;
-
+	prop->completion_mode = HL_COMPLETION_MODE_JOB;
 	prop->dram_base_address = DRAM_PHYS_BASE;
 	prop->dram_size = DRAM_PHYS_DEFAULT_SIZE;
 	prop->dram_end_address = prop->dram_base_address + prop->dram_size;
@@ -383,29 +413,39 @@ void goya_get_fixed_properties(struct hl_device *hdev)
 	else
 		prop->mmu_pgt_size = MMU_PAGE_TABLES_SIZE;
 	prop->mmu_pte_size = HL_PTE_SIZE;
-	prop->mmu_hop_table_size = HOP_TABLE_SIZE;
-	prop->mmu_hop0_tables_total_size = HOP0_TABLES_TOTAL_SIZE;
 	prop->dram_page_size = PAGE_SIZE_2MB;
-
-	prop->dmmu.hop0_shift = HOP0_SHIFT;
-	prop->dmmu.hop1_shift = HOP1_SHIFT;
-	prop->dmmu.hop2_shift = HOP2_SHIFT;
-	prop->dmmu.hop3_shift = HOP3_SHIFT;
-	prop->dmmu.hop4_shift = HOP4_SHIFT;
-	prop->dmmu.hop0_mask = HOP0_MASK;
-	prop->dmmu.hop1_mask = HOP1_MASK;
-	prop->dmmu.hop2_mask = HOP2_MASK;
-	prop->dmmu.hop3_mask = HOP3_MASK;
-	prop->dmmu.hop4_mask = HOP4_MASK;
+	prop->device_mem_alloc_default_page_size = prop->dram_page_size;
+	prop->dram_supports_virtual_memory = true;
+
+	prop->dmmu.hop_shifts[MMU_HOP0] = MMU_V1_0_HOP0_SHIFT;
+	prop->dmmu.hop_shifts[MMU_HOP1] = MMU_V1_0_HOP1_SHIFT;
+	prop->dmmu.hop_shifts[MMU_HOP2] = MMU_V1_0_HOP2_SHIFT;
+	prop->dmmu.hop_shifts[MMU_HOP3] = MMU_V1_0_HOP3_SHIFT;
+	prop->dmmu.hop_shifts[MMU_HOP4] = MMU_V1_0_HOP4_SHIFT;
+	prop->dmmu.hop_masks[MMU_HOP0] = MMU_V1_0_HOP0_MASK;
+	prop->dmmu.hop_masks[MMU_HOP1] = MMU_V1_0_HOP1_MASK;
+	prop->dmmu.hop_masks[MMU_HOP2] = MMU_V1_0_HOP2_MASK;
+	prop->dmmu.hop_masks[MMU_HOP3] = MMU_V1_0_HOP3_MASK;
+	prop->dmmu.hop_masks[MMU_HOP4] = MMU_V1_0_HOP4_MASK;
 	prop->dmmu.start_addr = VA_DDR_SPACE_START;
 	prop->dmmu.end_addr = VA_DDR_SPACE_END;
 	prop->dmmu.page_size = PAGE_SIZE_2MB;
+	prop->dmmu.num_hops = MMU_ARCH_5_HOPS;
+	prop->dmmu.last_mask = LAST_MASK;
+	/* TODO: will be duplicated until implementing per-MMU props */
+	prop->dmmu.hop_table_size = HOP_TABLE_SIZE_512_PTE;
+	prop->dmmu.hop0_tables_total_size = HOP0_512_PTE_TABLES_TOTAL_SIZE;
 
 	/* shifts and masks are the same in PMMU and DMMU */
 	memcpy(&prop->pmmu, &prop->dmmu, sizeof(prop->dmmu));
 	prop->pmmu.start_addr = VA_HOST_SPACE_START;
 	prop->pmmu.end_addr = VA_HOST_SPACE_END;
 	prop->pmmu.page_size = PAGE_SIZE_4KB;
+	prop->pmmu.num_hops = MMU_ARCH_5_HOPS;
+	prop->pmmu.last_mask = LAST_MASK;
+	/* TODO: will be duplicated until implementing per-MMU props */
+	prop->pmmu.hop_table_size = HOP_TABLE_SIZE_512_PTE;
+	prop->pmmu.hop0_tables_total_size = HOP0_512_PTE_TABLES_TOTAL_SIZE;
 
 	/* PMMU and HPMMU are the same except of page size */
 	memcpy(&prop->pmmu_huge, &prop->pmmu, sizeof(prop->pmmu));
@@ -419,12 +459,41 @@ void goya_get_fixed_properties(struct hl_device *hdev)
 	prop->cb_pool_cb_cnt = GOYA_CB_POOL_CB_CNT;
 	prop->cb_pool_cb_size = GOYA_CB_POOL_CB_SIZE;
 	prop->max_power_default = MAX_POWER_DEFAULT;
+	prop->dc_power_default = DC_POWER_DEFAULT;
 	prop->tpc_enabled_mask = TPC_ENABLED_MASK;
 	prop->pcie_dbi_base_address = mmPCIE_DBI_BASE;
 	prop->pcie_aux_dbi_reg_addr = CFG_BASE + mmPCIE_AUX_DBI;
 
-	strncpy(prop->armcp_info.card_name, GOYA_DEFAULT_CARD_NAME,
+	strscpy_pad(prop->cpucp_info.card_name, GOYA_DEFAULT_CARD_NAME,
 		CARD_NAME_MAX_LEN);
+
+	prop->max_pending_cs = GOYA_MAX_PENDING_CS;
+
+	prop->first_available_user_interrupt = USHRT_MAX;
+	prop->tpc_interrupt_id = USHRT_MAX;
+	prop->eq_interrupt_id = GOYA_EVENT_QUEUE_MSIX_IDX;
+
+	for (i = 0 ; i < HL_MAX_DCORES ; i++)
+		prop->first_available_cq[i] = USHRT_MAX;
+
+	prop->fw_cpu_boot_dev_sts0_valid = false;
+	prop->fw_cpu_boot_dev_sts1_valid = false;
+	prop->hard_reset_done_by_fw = false;
+	prop->gic_interrupts_enable = true;
+
+	prop->server_type = HL_SERVER_TYPE_UNKNOWN;
+
+	prop->clk_pll_index = HL_GOYA_MME_PLL;
+
+	prop->use_get_power_for_reset_history = true;
+
+	prop->configurable_stop_on_err = true;
+
+	prop->set_max_power_on_device_init = true;
+
+	prop->dma_mask = 48;
+
+	return 0;
 }
 
 /*
@@ -455,6 +524,7 @@ static int goya_pci_bars_map(struct hl_device *hdev)
 static u64 goya_set_ddr_bar_base(struct hl_device *hdev, u64 addr)
 {
 	struct goya_device *goya = hdev->asic_specific;
+	struct hl_inbound_pci_region pci_region;
 	u64 old_addr = addr;
 	int rc;
 
@@ -462,7 +532,10 @@ static u64 goya_set_ddr_bar_base(struct hl_device *hdev, u64 addr)
 		return old_addr;
 
 	/* Inbound Region 1 - Bar 4 - Point to DDR */
-	rc = hl_pci_set_dram_bar_base(hdev, 1, 4, addr);
+	pci_region.mode = PCI_BAR_MATCH_MODE;
+	pci_region.bar = DDR_BAR_ID;
+	pci_region.addr = addr;
+	rc = hl_pci_set_inbound_region(hdev, 1, &pci_region);
 	if (rc)
 		return U64_MAX;
 
@@ -484,8 +557,41 @@ static u64 goya_set_ddr_bar_base(struct hl_device *hdev, u64 addr)
  */
 static int goya_init_iatu(struct hl_device *hdev)
 {
-	return hl_pci_init_iatu(hdev, SRAM_BASE_ADDR, DRAM_PHYS_BASE,
-				HOST_PHYS_BASE, HOST_PHYS_SIZE);
+	struct hl_inbound_pci_region inbound_region;
+	struct hl_outbound_pci_region outbound_region;
+	int rc;
+
+	if (hdev->asic_prop.iatu_done_by_fw)
+		return 0;
+
+	/* Inbound Region 0 - Bar 0 - Point to SRAM and CFG */
+	inbound_region.mode = PCI_BAR_MATCH_MODE;
+	inbound_region.bar = SRAM_CFG_BAR_ID;
+	inbound_region.addr = SRAM_BASE_ADDR;
+	rc = hl_pci_set_inbound_region(hdev, 0, &inbound_region);
+	if (rc)
+		goto done;
+
+	/* Inbound Region 1 - Bar 4 - Point to DDR */
+	inbound_region.mode = PCI_BAR_MATCH_MODE;
+	inbound_region.bar = DDR_BAR_ID;
+	inbound_region.addr = DRAM_PHYS_BASE;
+	rc = hl_pci_set_inbound_region(hdev, 1, &inbound_region);
+	if (rc)
+		goto done;
+
+	/* Outbound Region 0 - Point to Host  */
+	outbound_region.addr = HOST_PHYS_BASE;
+	outbound_region.size = HOST_PHYS_SIZE;
+	rc = hl_pci_set_outbound_region(hdev, &outbound_region);
+
+done:
+	return rc;
+}
+
+static enum hl_device_hw_state goya_get_hw_state(struct hl_device *hdev)
+{
+	return RREG32(mmHW_STATE);
 }
 
 /*
@@ -503,37 +609,78 @@ static int goya_early_init(struct hl_device *hdev)
 {
 	struct asic_fixed_properties *prop = &hdev->asic_prop;
 	struct pci_dev *pdev = hdev->pdev;
-	u32 val;
+	resource_size_t pci_bar_size;
+	u32 fw_boot_status, val;
 	int rc;
 
-	goya_get_fixed_properties(hdev);
+	rc = goya_set_fixed_properties(hdev);
+	if (rc) {
+		dev_err(hdev->dev, "Failed to get fixed properties\n");
+		return rc;
+	}
 
 	/* Check BAR sizes */
-	if (pci_resource_len(pdev, SRAM_CFG_BAR_ID) != CFG_BAR_SIZE) {
-		dev_err(hdev->dev,
-			"Not " HL_NAME "? BAR %d size %llu, expecting %llu\n",
-			SRAM_CFG_BAR_ID,
-			(unsigned long long) pci_resource_len(pdev,
-							SRAM_CFG_BAR_ID),
-			CFG_BAR_SIZE);
-		return -ENODEV;
+	pci_bar_size = pci_resource_len(pdev, SRAM_CFG_BAR_ID);
+
+	if (pci_bar_size != CFG_BAR_SIZE) {
+		dev_err(hdev->dev, "Not " HL_NAME "? BAR %d size %pa, expecting %llu\n",
+			SRAM_CFG_BAR_ID, &pci_bar_size, CFG_BAR_SIZE);
+		rc = -ENODEV;
+		goto free_queue_props;
 	}
 
-	if (pci_resource_len(pdev, MSIX_BAR_ID) != MSIX_BAR_SIZE) {
-		dev_err(hdev->dev,
-			"Not " HL_NAME "? BAR %d size %llu, expecting %llu\n",
-			MSIX_BAR_ID,
-			(unsigned long long) pci_resource_len(pdev,
-								MSIX_BAR_ID),
-			MSIX_BAR_SIZE);
-		return -ENODEV;
+	pci_bar_size = pci_resource_len(pdev, MSIX_BAR_ID);
+
+	if (pci_bar_size != MSIX_BAR_SIZE) {
+		dev_err(hdev->dev, "Not " HL_NAME "? BAR %d size %pa, expecting %llu\n",
+			MSIX_BAR_ID, &pci_bar_size, MSIX_BAR_SIZE);
+		rc = -ENODEV;
+		goto free_queue_props;
 	}
 
 	prop->dram_pci_bar_size = pci_resource_len(pdev, DDR_BAR_ID);
+	hdev->dram_pci_bar_start = pci_resource_start(pdev, DDR_BAR_ID);
 
-	rc = hl_pci_init(hdev, 48);
+	/* If FW security is enabled at this point it means no access to ELBI */
+	if (hdev->asic_prop.fw_security_enabled) {
+		hdev->asic_prop.iatu_done_by_fw = true;
+		goto pci_init;
+	}
+
+	rc = hl_pci_elbi_read(hdev, CFG_BASE + mmCPU_BOOT_DEV_STS0,
+				&fw_boot_status);
 	if (rc)
-		return rc;
+		goto free_queue_props;
+
+	/* Check whether FW is configuring iATU */
+	if ((fw_boot_status & CPU_BOOT_DEV_STS0_ENABLED) &&
+			(fw_boot_status & CPU_BOOT_DEV_STS0_FW_IATU_CONF_EN))
+		hdev->asic_prop.iatu_done_by_fw = true;
+
+pci_init:
+	rc = hl_pci_init(hdev);
+	if (rc)
+		goto free_queue_props;
+
+	/* Before continuing in the initialization, we need to read the preboot
+	 * version to determine whether we run with a security-enabled firmware
+	 */
+	rc = hl_fw_read_preboot_status(hdev);
+	if (rc) {
+		if (hdev->reset_on_preboot_fail)
+			/* we are already on failure flow, so don't check if hw_fini fails. */
+			hdev->asic_funcs->hw_fini(hdev, true, false);
+		goto pci_fini;
+	}
+
+	if (goya_get_hw_state(hdev) == HL_DEVICE_HW_STATE_DIRTY) {
+		dev_dbg(hdev->dev, "H/W state is dirty, must reset before initializing\n");
+		rc = hdev->asic_funcs->hw_fini(hdev, true, false);
+		if (rc) {
+			dev_err(hdev->dev, "failed to reset HW in dirty state (%d)\n", rc);
+			goto pci_fini;
+		}
+	}
 
 	if (!hdev->pldm) {
 		val = RREG32(mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS);
@@ -543,6 +690,12 @@ static int goya_early_init(struct hl_device *hdev)
 	}
 
 	return 0;
+
+pci_fini:
+	hl_pci_fini(hdev);
+free_queue_props:
+	kfree(hdev->asic_prop.hw_queues_props);
+	return rc;
 }
 
 /*
@@ -555,6 +708,7 @@ static int goya_early_init(struct hl_device *hdev)
  */
 static int goya_early_fini(struct hl_device *hdev)
 {
+	kfree(hdev->asic_prop.hw_queues_props);
 	hl_pci_fini(hdev);
 
 	return 0;
@@ -591,16 +745,112 @@ static void goya_qman0_set_security(struct hl_device *hdev, bool secure)
 static void goya_fetch_psoc_frequency(struct hl_device *hdev)
 {
 	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	u32 nr = 0, nf = 0, od = 0, div_fctr = 0, pll_clk, div_sel;
+	u16 pll_freq_arr[HL_PLL_NUM_OUTPUTS], freq;
+	int rc;
+
+	if (hdev->asic_prop.fw_security_enabled) {
+		struct goya_device *goya = hdev->asic_specific;
+
+		if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
+			return;
+
+		rc = hl_fw_cpucp_pll_info_get(hdev, HL_GOYA_PCI_PLL,
+				pll_freq_arr);
+
+		if (rc)
+			return;
+
+		freq = pll_freq_arr[1];
+	} else {
+		div_fctr = RREG32(mmPSOC_PCI_PLL_DIV_FACTOR_1);
+		div_sel = RREG32(mmPSOC_PCI_PLL_DIV_SEL_1);
+		nr = RREG32(mmPSOC_PCI_PLL_NR);
+		nf = RREG32(mmPSOC_PCI_PLL_NF);
+		od = RREG32(mmPSOC_PCI_PLL_OD);
+
+		if (div_sel == DIV_SEL_REF_CLK ||
+				div_sel == DIV_SEL_DIVIDED_REF) {
+			if (div_sel == DIV_SEL_REF_CLK)
+				freq = PLL_REF_CLK;
+			else
+				freq = PLL_REF_CLK / (div_fctr + 1);
+		} else if (div_sel == DIV_SEL_PLL_CLK ||
+				div_sel == DIV_SEL_DIVIDED_PLL) {
+			pll_clk = PLL_REF_CLK * (nf + 1) /
+					((nr + 1) * (od + 1));
+			if (div_sel == DIV_SEL_PLL_CLK)
+				freq = pll_clk;
+			else
+				freq = pll_clk / (div_fctr + 1);
+		} else {
+			dev_warn(hdev->dev,
+				"Received invalid div select value: %d",
+				div_sel);
+			freq = 0;
+		}
+	}
 
-	prop->psoc_pci_pll_nr = RREG32(mmPSOC_PCI_PLL_NR);
-	prop->psoc_pci_pll_nf = RREG32(mmPSOC_PCI_PLL_NF);
-	prop->psoc_pci_pll_od = RREG32(mmPSOC_PCI_PLL_OD);
-	prop->psoc_pci_pll_div_factor = RREG32(mmPSOC_PCI_PLL_DIV_FACTOR_1);
+	prop->psoc_timestamp_frequency = freq;
+	prop->psoc_pci_pll_nr = nr;
+	prop->psoc_pci_pll_nf = nf;
+	prop->psoc_pci_pll_od = od;
+	prop->psoc_pci_pll_div_factor = div_fctr;
+}
+
+/*
+ * goya_set_frequency - set the frequency of the device
+ *
+ * @hdev: pointer to habanalabs device structure
+ * @freq: the new frequency value
+ *
+ * Change the frequency if needed. This function has no protection against
+ * concurrency, therefore it is assumed that the calling function has protected
+ * itself against the case of calling this function from multiple threads with
+ * different values
+ *
+ * Returns 0 if no change was done, otherwise returns 1
+ */
+int goya_set_frequency(struct hl_device *hdev, enum hl_pll_frequency freq)
+{
+	struct goya_device *goya = hdev->asic_specific;
+
+	if ((goya->pm_mng_profile == PM_MANUAL) ||
+			(goya->curr_pll_profile == freq))
+		return 0;
+
+	dev_dbg(hdev->dev, "Changing device frequency to %s\n",
+		freq == PLL_HIGH ? "high" : "low");
+
+	goya_set_pll_profile(hdev, freq);
+
+	goya->curr_pll_profile = freq;
+
+	return 1;
+}
+
+static void goya_set_freq_to_low_job(struct work_struct *work)
+{
+	struct goya_work_freq *goya_work = container_of(work,
+						struct goya_work_freq,
+						work_freq.work);
+	struct hl_device *hdev = goya_work->hdev;
+
+	mutex_lock(&hdev->fpriv_list_lock);
+
+	if (!hdev->is_compute_ctx_active)
+		goya_set_frequency(hdev, PLL_LOW);
+
+	mutex_unlock(&hdev->fpriv_list_lock);
+
+	schedule_delayed_work(&goya_work->work_freq,
+			usecs_to_jiffies(HL_PLL_LOW_JOB_FREQ_USEC));
 }
 
 int goya_late_init(struct hl_device *hdev)
 {
 	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct goya_device *goya = hdev->asic_specific;
 	int rc;
 
 	goya_fetch_psoc_frequency(hdev);
@@ -630,9 +880,9 @@ int goya_late_init(struct hl_device *hdev)
 	if (rc)
 		return rc;
 
-	rc = goya_armcp_info_get(hdev);
+	rc = goya_cpucp_info_get(hdev);
 	if (rc) {
-		dev_err(hdev->dev, "Failed to get armcp info %d\n", rc);
+		dev_err(hdev->dev, "Failed to get cpucp info %d\n", rc);
 		return rc;
 	}
 
@@ -642,15 +892,19 @@ int goya_late_init(struct hl_device *hdev)
 	 */
 	WREG32(mmMMU_LOG2_DDR_SIZE, ilog2(prop->dram_size));
 
-	rc = hl_fw_send_pci_access_msg(hdev, ARMCP_PACKET_ENABLE_PCI_ACCESS);
-	if (rc) {
-		dev_err(hdev->dev,
-			"Failed to enable PCI access from CPU %d\n", rc);
+	rc = hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_ENABLE_PCI_ACCESS, 0x0);
+	if (rc)
 		return rc;
-	}
 
-	WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
-			GOYA_ASYNC_EVENT_ID_INTS_REGISTER);
+	/* force setting to low frequency */
+	goya->curr_pll_profile = PLL_LOW;
+
+	goya->pm_mng_profile = PM_AUTO;
+
+	goya_set_pll_profile(hdev, PLL_LOW);
+
+	schedule_delayed_work(&goya->goya_work->work_freq,
+		usecs_to_jiffies(HL_PLL_LOW_JOB_FREQ_USEC));
 
 	return 0;
 }
@@ -664,23 +918,44 @@ int goya_late_init(struct hl_device *hdev)
  */
 void goya_late_fini(struct hl_device *hdev)
 {
-	const struct hwmon_channel_info **channel_info_arr;
-	int i = 0;
-
-	if (!hdev->hl_chip_info->info)
-		return;
-
-	channel_info_arr = hdev->hl_chip_info->info;
+	struct goya_device *goya = hdev->asic_specific;
 
-	while (channel_info_arr[i]) {
-		kfree(channel_info_arr[i]->config);
-		kfree(channel_info_arr[i]);
-		i++;
-	}
+	cancel_delayed_work_sync(&goya->goya_work->work_freq);
 
-	kfree(channel_info_arr);
+	hl_hwmon_release_resources(hdev);
+}
 
-	hdev->hl_chip_info->info = NULL;
+static void goya_set_pci_memory_regions(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct pci_mem_region *region;
+
+	/* CFG */
+	region = &hdev->pci_mem_region[PCI_REGION_CFG];
+	region->region_base = CFG_BASE;
+	region->region_size = CFG_SIZE;
+	region->offset_in_bar = CFG_BASE - SRAM_BASE_ADDR;
+	region->bar_size = CFG_BAR_SIZE;
+	region->bar_id = SRAM_CFG_BAR_ID;
+	region->used = 1;
+
+	/* SRAM */
+	region = &hdev->pci_mem_region[PCI_REGION_SRAM];
+	region->region_base = SRAM_BASE_ADDR;
+	region->region_size = SRAM_SIZE;
+	region->offset_in_bar = 0;
+	region->bar_size = CFG_BAR_SIZE;
+	region->bar_id = SRAM_CFG_BAR_ID;
+	region->used = 1;
+
+	/* DRAM */
+	region = &hdev->pci_mem_region[PCI_REGION_DRAM];
+	region->region_base = DRAM_PHYS_BASE;
+	region->region_size = hdev->asic_prop.dram_size;
+	region->offset_in_bar = 0;
+	region->bar_size = prop->dram_pci_bar_size;
+	region->bar_id = DDR_BAR_ID;
+	region->used = 1;
 }
 
 /*
@@ -717,11 +992,9 @@ static int goya_sw_init(struct hl_device *hdev)
 		goto free_goya_device;
 	}
 
-	hdev->cpu_accessible_dma_mem =
-			hdev->asic_funcs->asic_dma_alloc_coherent(hdev,
-					HL_CPU_ACCESSIBLE_MEM_SIZE,
-					&hdev->cpu_accessible_dma_address,
-					GFP_KERNEL | __GFP_ZERO);
+	hdev->cpu_accessible_dma_mem = hl_asic_dma_alloc_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE,
+							&hdev->cpu_accessible_dma_address,
+							GFP_KERNEL | __GFP_ZERO);
 
 	if (!hdev->cpu_accessible_dma_mem) {
 		rc = -ENOMEM;
@@ -750,16 +1023,30 @@ static int goya_sw_init(struct hl_device *hdev)
 	}
 
 	spin_lock_init(&goya->hw_queues_lock);
+	hdev->supports_coresight = true;
+	hdev->asic_prop.supports_compute_reset = true;
+	hdev->asic_prop.allow_inference_soft_reset = true;
+	hdev->supports_wait_for_multi_cs = false;
+	hdev->supports_ctx_switch = true;
+
+	hdev->asic_funcs->set_pci_memory_regions(hdev);
+
+	goya->goya_work = kmalloc(sizeof(struct goya_work_freq), GFP_KERNEL);
+	if (!goya->goya_work) {
+		rc = -ENOMEM;
+		goto free_cpu_accessible_dma_pool;
+	}
+
+	goya->goya_work->hdev = hdev;
+	INIT_DELAYED_WORK(&goya->goya_work->work_freq, goya_set_freq_to_low_job);
 
 	return 0;
 
 free_cpu_accessible_dma_pool:
 	gen_pool_destroy(hdev->cpu_accessible_dma_pool);
 free_cpu_dma_mem:
-	hdev->asic_funcs->asic_dma_free_coherent(hdev,
-			HL_CPU_ACCESSIBLE_MEM_SIZE,
-			hdev->cpu_accessible_dma_mem,
-			hdev->cpu_accessible_dma_address);
+	hl_asic_dma_free_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE, hdev->cpu_accessible_dma_mem,
+					hdev->cpu_accessible_dma_address);
 free_dma_pool:
 	dma_pool_destroy(hdev->dma_pool);
 free_goya_device:
@@ -780,13 +1067,12 @@ static int goya_sw_fini(struct hl_device *hdev)
 
 	gen_pool_destroy(hdev->cpu_accessible_dma_pool);
 
-	hdev->asic_funcs->asic_dma_free_coherent(hdev,
-			HL_CPU_ACCESSIBLE_MEM_SIZE,
-			hdev->cpu_accessible_dma_mem,
-			hdev->cpu_accessible_dma_address);
+	hl_asic_dma_free_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE, hdev->cpu_accessible_dma_mem,
+					hdev->cpu_accessible_dma_address);
 
 	dma_pool_destroy(hdev->dma_pool);
 
+	kfree(goya->goya_work);
 	kfree(goya);
 
 	return 0;
@@ -800,6 +1086,7 @@ static void goya_init_dma_qman(struct hl_device *hdev, int dma_id,
 	u32 so_base_lo, so_base_hi;
 	u32 gic_base_lo, gic_base_hi;
 	u32 reg_off = dma_id * (mmDMA_QM_1_PQ_PI - mmDMA_QM_0_PQ_PI);
+	u32 dma_err_cfg = QMAN_DMA_ERR_MSG_EN;
 
 	mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
 	mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
@@ -836,7 +1123,10 @@ static void goya_init_dma_qman(struct hl_device *hdev, int dma_id,
 	else
 		WREG32(mmDMA_QM_0_GLBL_PROT + reg_off, QMAN_DMA_FULLY_TRUSTED);
 
-	WREG32(mmDMA_QM_0_GLBL_ERR_CFG + reg_off, QMAN_DMA_ERR_MSG_EN);
+	if (hdev->stop_on_err)
+		dma_err_cfg |= 1 << DMA_QM_0_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT;
+
+	WREG32(mmDMA_QM_0_GLBL_ERR_CFG + reg_off, dma_err_cfg);
 	WREG32(mmDMA_QM_0_GLBL_CFG0 + reg_off, QMAN_DMA_ENABLE);
 }
 
@@ -886,6 +1176,7 @@ void goya_init_dma_qmans(struct hl_device *hdev)
 	q = &hdev->kernel_queues[0];
 
 	for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++, q++) {
+		q->cq_id = q->msi_vec = i;
 		goya_init_dma_qman(hdev, i, q->bus_address);
 		goya_init_dma_ch(hdev, i);
 	}
@@ -1036,6 +1327,7 @@ static int goya_stop_external_queues(struct hl_device *hdev)
 int goya_init_cpu_queues(struct hl_device *hdev)
 {
 	struct goya_device *goya = hdev->asic_specific;
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
 	struct hl_eq *eq;
 	u32 status;
 	struct hl_hw_queue *cpu_pq = &hdev->kernel_queues[GOYA_QUEUE_ID_CPU_PQ];
@@ -1088,6 +1380,13 @@ int goya_init_cpu_queues(struct hl_device *hdev)
 		return -EIO;
 	}
 
+	/* update FW application security bits */
+	if (prop->fw_cpu_boot_dev_sts0_valid)
+		prop->fw_app_cpu_boot_dev_sts0 = RREG32(mmCPU_BOOT_DEV_STS0);
+
+	if (prop->fw_cpu_boot_dev_sts1_valid)
+		prop->fw_app_cpu_boot_dev_sts1 = RREG32(mmCPU_BOOT_DEV_STS1);
+
 	goya->hw_cap_initialized |= HW_CAP_CPU_Q;
 	return 0;
 }
@@ -2154,31 +2453,14 @@ static void goya_disable_timestamp(struct hl_device *hdev)
 	WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0);
 }
 
-static void goya_halt_engines(struct hl_device *hdev, bool hard_reset)
+static void goya_halt_engines(struct hl_device *hdev, bool hard_reset, bool fw_reset)
 {
-	u32 wait_timeout_ms, cpu_timeout_ms;
+	u32 wait_timeout_ms;
 
-	dev_info(hdev->dev,
-		"Halting compute engines and disabling interrupts\n");
-
-	if (hdev->pldm) {
+	if (hdev->pldm)
 		wait_timeout_ms = GOYA_PLDM_RESET_WAIT_MSEC;
-		cpu_timeout_ms = GOYA_PLDM_RESET_WAIT_MSEC;
-	} else {
+	else
 		wait_timeout_ms = GOYA_RESET_WAIT_MSEC;
-		cpu_timeout_ms = GOYA_CPU_RESET_WAIT_MSEC;
-	}
-
-	if (hard_reset) {
-		/*
-		 * I don't know what is the state of the CPU so make sure it is
-		 * stopped in any means necessary
-		 */
-		WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_GOTO_WFE);
-		WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
-			GOYA_ASYNC_EVENT_ID_HALT_MACHINE);
-		msleep(cpu_timeout_ms);
-	}
 
 	goya_stop_external_queues(hdev);
 	goya_stop_internal_queues(hdev);
@@ -2205,128 +2487,121 @@ static void goya_halt_engines(struct hl_device *hdev, bool hard_reset)
 }
 
 /*
- * goya_push_uboot_to_device() - Push u-boot FW code to device.
+ * goya_load_firmware_to_device() - Load LINUX FW code to device.
  * @hdev: Pointer to hl_device structure.
  *
- * Copy u-boot fw code from firmware file to SRAM BAR.
+ * Copy LINUX fw code from firmware file to HBM BAR.
  *
  * Return: 0 on success, non-zero for failure.
  */
-static int goya_push_uboot_to_device(struct hl_device *hdev)
+static int goya_load_firmware_to_device(struct hl_device *hdev)
 {
 	void __iomem *dst;
 
-	dst = hdev->pcie_bar[SRAM_CFG_BAR_ID] + UBOOT_FW_OFFSET;
+	dst = hdev->pcie_bar[DDR_BAR_ID] + LINUX_FW_OFFSET;
 
-	return hl_fw_push_fw_to_device(hdev, GOYA_UBOOT_FW_FILE, dst);
+	return hl_fw_load_fw_to_device(hdev, GOYA_LINUX_FW_FILE, dst, 0, 0);
 }
 
 /*
- * goya_push_linux_to_device() - Push LINUX FW code to device.
+ * goya_load_boot_fit_to_device() - Load boot fit to device.
  * @hdev: Pointer to hl_device structure.
  *
- * Copy LINUX fw code from firmware file to HBM BAR.
+ * Copy boot fit file to SRAM BAR.
  *
  * Return: 0 on success, non-zero for failure.
  */
-static int goya_push_linux_to_device(struct hl_device *hdev)
+static int goya_load_boot_fit_to_device(struct hl_device *hdev)
 {
 	void __iomem *dst;
 
-	dst = hdev->pcie_bar[DDR_BAR_ID] + LINUX_FW_OFFSET;
+	dst = hdev->pcie_bar[SRAM_CFG_BAR_ID] + BOOT_FIT_SRAM_OFFSET;
 
-	return hl_fw_push_fw_to_device(hdev, GOYA_LINUX_FW_FILE, dst);
+	return hl_fw_load_fw_to_device(hdev, GOYA_BOOT_FIT_FILE, dst, 0, 0);
 }
 
-static int goya_pldm_init_cpu(struct hl_device *hdev)
+static void goya_init_dynamic_firmware_loader(struct hl_device *hdev)
 {
-	u32 unit_rst_val;
-	int rc;
+	struct dynamic_fw_load_mgr *dynamic_loader;
+	struct cpu_dyn_regs *dyn_regs;
 
-	/* Must initialize SRAM scrambler before pushing u-boot to SRAM */
-	goya_init_golden_registers(hdev);
-
-	/* Put ARM cores into reset */
-	WREG32(mmCPU_CA53_CFG_ARM_RST_CONTROL, CPU_RESET_ASSERT);
-	RREG32(mmCPU_CA53_CFG_ARM_RST_CONTROL);
-
-	/* Reset the CA53 MACRO */
-	unit_rst_val = RREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N);
-	WREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N, CA53_RESET);
-	RREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N);
-	WREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N, unit_rst_val);
-	RREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N);
+	dynamic_loader = &hdev->fw_loader.dynamic_loader;
 
-	rc = goya_push_uboot_to_device(hdev);
-	if (rc)
-		return rc;
-
-	rc = goya_push_linux_to_device(hdev);
-	if (rc)
-		return rc;
-
-	WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_FIT_RDY);
-	WREG32(mmPSOC_GLOBAL_CONF_WARM_REBOOT, CPU_BOOT_STATUS_NA);
-
-	WREG32(mmCPU_CA53_CFG_RST_ADDR_LSB_0,
-		lower_32_bits(SRAM_BASE_ADDR + UBOOT_FW_OFFSET));
-	WREG32(mmCPU_CA53_CFG_RST_ADDR_MSB_0,
-		upper_32_bits(SRAM_BASE_ADDR + UBOOT_FW_OFFSET));
-
-	/* Release ARM core 0 from reset */
-	WREG32(mmCPU_CA53_CFG_ARM_RST_CONTROL,
-					CPU_RESET_CORE0_DEASSERT);
-	RREG32(mmCPU_CA53_CFG_ARM_RST_CONTROL);
+	/*
+	 * here we update initial values for few specific dynamic regs (as
+	 * before reading the first descriptor from FW those value has to be
+	 * hard-coded) in later stages of the protocol those values will be
+	 * updated automatically by reading the FW descriptor so data there
+	 * will always be up-to-date
+	 */
+	dyn_regs = &dynamic_loader->comm_desc.cpu_dyn_regs;
+	dyn_regs->kmd_msg_to_cpu =
+				cpu_to_le32(mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU);
+	dyn_regs->cpu_cmd_status_to_host =
+				cpu_to_le32(mmCPU_CMD_STATUS_TO_HOST);
 
-	return 0;
+	dynamic_loader->wait_for_bl_timeout = GOYA_WAIT_FOR_BL_TIMEOUT_USEC;
 }
 
-/*
- * FW component passes an offset from SRAM_BASE_ADDR in SCRATCHPAD_xx.
- * The version string should be located by that offset.
- */
-static void goya_read_device_fw_version(struct hl_device *hdev,
-					enum goya_fw_component fwc)
-{
-	const char *name;
-	u32 ver_off;
-	char *dest;
-
-	switch (fwc) {
-	case FW_COMP_UBOOT:
-		ver_off = RREG32(mmUBOOT_VER_OFFSET);
-		dest = hdev->asic_prop.uboot_ver;
-		name = "U-Boot";
-		break;
-	case FW_COMP_PREBOOT:
-		ver_off = RREG32(mmPREBOOT_VER_OFFSET);
-		dest = hdev->asic_prop.preboot_ver;
-		name = "Preboot";
-		break;
-	default:
-		dev_warn(hdev->dev, "Undefined FW component: %d\n", fwc);
-		return;
-	}
+static void goya_init_static_firmware_loader(struct hl_device *hdev)
+{
+	struct static_fw_load_mgr *static_loader;
+
+	static_loader = &hdev->fw_loader.static_loader;
+
+	static_loader->preboot_version_max_off = SRAM_SIZE - VERSION_MAX_LEN;
+	static_loader->boot_fit_version_max_off = SRAM_SIZE - VERSION_MAX_LEN;
+	static_loader->kmd_msg_to_cpu_reg = mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU;
+	static_loader->cpu_cmd_status_to_host_reg = mmCPU_CMD_STATUS_TO_HOST;
+	static_loader->cpu_boot_status_reg = mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS;
+	static_loader->cpu_boot_dev_status0_reg = mmCPU_BOOT_DEV_STS0;
+	static_loader->cpu_boot_dev_status1_reg = mmCPU_BOOT_DEV_STS1;
+	static_loader->boot_err0_reg = mmCPU_BOOT_ERR0;
+	static_loader->boot_err1_reg = mmCPU_BOOT_ERR1;
+	static_loader->preboot_version_offset_reg = mmPREBOOT_VER_OFFSET;
+	static_loader->boot_fit_version_offset_reg = mmUBOOT_VER_OFFSET;
+	static_loader->sram_offset_mask = ~(lower_32_bits(SRAM_BASE_ADDR));
+}
 
-	ver_off &= ~((u32)SRAM_BASE_ADDR);
+static void goya_init_firmware_preload_params(struct hl_device *hdev)
+{
+	struct pre_fw_load_props *pre_fw_load = &hdev->fw_loader.pre_fw_load;
+
+	pre_fw_load->cpu_boot_status_reg = mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS;
+	pre_fw_load->sts_boot_dev_sts0_reg = mmCPU_BOOT_DEV_STS0;
+	pre_fw_load->sts_boot_dev_sts1_reg = mmCPU_BOOT_DEV_STS1;
+	pre_fw_load->boot_err0_reg = mmCPU_BOOT_ERR0;
+	pre_fw_load->boot_err1_reg = mmCPU_BOOT_ERR1;
+	pre_fw_load->wait_for_preboot_timeout = GOYA_BOOT_FIT_REQ_TIMEOUT_USEC;
+}
 
-	if (ver_off < SRAM_SIZE - VERSION_MAX_LEN) {
-		memcpy_fromio(dest, hdev->pcie_bar[SRAM_CFG_BAR_ID] + ver_off,
-							VERSION_MAX_LEN);
-	} else {
-		dev_err(hdev->dev, "%s version offset (0x%x) is above SRAM\n",
-								name, ver_off);
-		strcpy(dest, "unavailable");
-	}
+static void goya_init_firmware_loader(struct hl_device *hdev)
+{
+	struct asic_fixed_properties *prop = &hdev->asic_prop;
+	struct fw_load_mgr *fw_loader = &hdev->fw_loader;
+
+	/* fill common fields */
+	fw_loader->fw_comp_loaded = FW_TYPE_NONE;
+	fw_loader->boot_fit_img.image_name = GOYA_BOOT_FIT_FILE;
+	fw_loader->linux_img.image_name = GOYA_LINUX_FW_FILE;
+	fw_loader->cpu_timeout = GOYA_CPU_TIMEOUT_USEC;
+	fw_loader->boot_fit_timeout = GOYA_BOOT_FIT_REQ_TIMEOUT_USEC;
+	fw_loader->skip_bmc = false;
+	fw_loader->sram_bar_id = SRAM_CFG_BAR_ID;
+	fw_loader->dram_bar_id = DDR_BAR_ID;
+
+	if (prop->dynamic_fw_load)
+		goya_init_dynamic_firmware_loader(hdev);
+	else
+		goya_init_static_firmware_loader(hdev);
 }
 
-static int goya_init_cpu(struct hl_device *hdev, u32 cpu_timeout)
+static int goya_init_cpu(struct hl_device *hdev)
 {
 	struct goya_device *goya = hdev->asic_specific;
-	u32 status;
 	int rc;
 
-	if (!hdev->cpu_enable)
+	if (!(hdev->fw_components & FW_TYPE_PREBOOT_CPU))
 		return 0;
 
 	if (goya->hw_cap_initialized & HW_CAP_CPU)
@@ -2342,115 +2617,11 @@ static int goya_init_cpu(struct hl_device *hdev, u32 cpu_timeout)
 		return -EIO;
 	}
 
-	if (hdev->pldm) {
-		rc = goya_pldm_init_cpu(hdev);
-		if (rc)
-			return rc;
-
-		goto out;
-	}
-
-	/* Make sure CPU boot-loader is running */
-	rc = hl_poll_timeout(
-		hdev,
-		mmPSOC_GLOBAL_CONF_WARM_REBOOT,
-		status,
-		(status == CPU_BOOT_STATUS_DRAM_RDY) ||
-		(status == CPU_BOOT_STATUS_SRAM_AVAIL),
-		10000,
-		cpu_timeout);
-
-	/* Read U-Boot version now in case we will later fail */
-	goya_read_device_fw_version(hdev, FW_COMP_UBOOT);
-	goya_read_device_fw_version(hdev, FW_COMP_PREBOOT);
-
-	if (rc) {
-		dev_err(hdev->dev, "Error in ARM u-boot!");
-		switch (status) {
-		case CPU_BOOT_STATUS_NA:
-			dev_err(hdev->dev,
-				"ARM status %d - BTL did NOT run\n", status);
-			break;
-		case CPU_BOOT_STATUS_IN_WFE:
-			dev_err(hdev->dev,
-				"ARM status %d - Inside WFE loop\n", status);
-			break;
-		case CPU_BOOT_STATUS_IN_BTL:
-			dev_err(hdev->dev,
-				"ARM status %d - Stuck in BTL\n", status);
-			break;
-		case CPU_BOOT_STATUS_IN_PREBOOT:
-			dev_err(hdev->dev,
-				"ARM status %d - Stuck in Preboot\n", status);
-			break;
-		case CPU_BOOT_STATUS_IN_SPL:
-			dev_err(hdev->dev,
-				"ARM status %d - Stuck in SPL\n", status);
-			break;
-		case CPU_BOOT_STATUS_IN_UBOOT:
-			dev_err(hdev->dev,
-				"ARM status %d - Stuck in u-boot\n", status);
-			break;
-		case CPU_BOOT_STATUS_DRAM_INIT_FAIL:
-			dev_err(hdev->dev,
-				"ARM status %d - DDR initialization failed\n",
-				status);
-			break;
-		case CPU_BOOT_STATUS_UBOOT_NOT_READY:
-			dev_err(hdev->dev,
-				"ARM status %d - u-boot stopped by user\n",
-				status);
-			break;
-		case CPU_BOOT_STATUS_TS_INIT_FAIL:
-			dev_err(hdev->dev,
-				"ARM status %d - Thermal Sensor initialization failed\n",
-				status);
-			break;
-		default:
-			dev_err(hdev->dev,
-				"ARM status %d - Invalid status code\n",
-				status);
-			break;
-		}
-		return -EIO;
-	}
-
-	if (!hdev->fw_loading) {
-		dev_info(hdev->dev, "Skip loading FW\n");
-		goto out;
-	}
-
-	if (status == CPU_BOOT_STATUS_SRAM_AVAIL)
-		goto out;
+	rc = hl_fw_init_cpu(hdev);
 
-	rc = goya_push_linux_to_device(hdev);
 	if (rc)
 		return rc;
 
-	WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_FIT_RDY);
-
-	rc = hl_poll_timeout(
-		hdev,
-		mmPSOC_GLOBAL_CONF_WARM_REBOOT,
-		status,
-		(status == CPU_BOOT_STATUS_SRAM_AVAIL),
-		10000,
-		cpu_timeout);
-
-	if (rc) {
-		if (status == CPU_BOOT_STATUS_FIT_CORRUPTED)
-			dev_err(hdev->dev,
-				"ARM u-boot reports FIT image is corrupted\n");
-		else
-			dev_err(hdev->dev,
-				"ARM Linux failed to load, %d\n", status);
-		WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_NA);
-		return -EIO;
-	}
-
-	dev_info(hdev->dev, "Successfully loaded firmware to device\n");
-
-out:
 	goya->hw_cap_initialized |= HW_CAP_CPU;
 
 	return 0;
@@ -2495,18 +2666,14 @@ int goya_mmu_init(struct hl_device *hdev)
 	u64 hop0_addr;
 	int rc, i;
 
-	if (!hdev->mmu_enable)
-		return 0;
-
 	if (goya->hw_cap_initialized & HW_CAP_MMU)
 		return 0;
 
-	hdev->dram_supports_virtual_memory = true;
 	hdev->dram_default_page_mapping = true;
 
 	for (i = 0 ; i < prop->max_asid ; i++) {
 		hop0_addr = prop->mmu_pgt_addr +
-				(i * prop->mmu_hop_table_size);
+				(i * prop->dmmu.hop_table_size);
 
 		rc = goya_mmu_update_asid_hop0_addr(hdev, i, hop0_addr);
 		if (rc) {
@@ -2527,8 +2694,7 @@ int goya_mmu_init(struct hl_device *hdev)
 	WREG32_AND(mmSTLB_STLB_FEATURE_EN,
 			(~STLB_STLB_FEATURE_EN_FOLLOWER_EN_MASK));
 
-	hdev->asic_funcs->mmu_invalidate_cache(hdev, true,
-					VM_TYPE_USERPTR | VM_TYPE_PHYS_PACK);
+	hl_mmu_invalidate_cache(hdev, true, MMU_OP_USERPTR | MMU_OP_PHYS_PACK);
 
 	WREG32(mmMMU_MMU_ENABLE, 1);
 	WREG32(mmMMU_SPI_MASK, 0xF);
@@ -2552,8 +2718,6 @@ static int goya_hw_init(struct hl_device *hdev)
 	struct asic_fixed_properties *prop = &hdev->asic_prop;
 	int rc;
 
-	dev_info(hdev->dev, "Starting initialization of H/W\n");
-
 	/* Perform read from the device to make sure device is up */
 	RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG);
 
@@ -2565,7 +2729,7 @@ static int goya_hw_init(struct hl_device *hdev)
 	 */
 	WREG32(mmHW_STATE, HL_DEVICE_HW_STATE_DIRTY);
 
-	rc = goya_init_cpu(hdev, GOYA_CPU_TIMEOUT_USEC);
+	rc = goya_init_cpu(hdev);
 	if (rc) {
 		dev_err(hdev->dev, "failed to initialize CPU\n");
 		return rc;
@@ -2617,35 +2781,40 @@ disable_queues:
 	return rc;
 }
 
-/*
- * goya_hw_fini - Goya hardware tear-down code
- *
- * @hdev: pointer to hl_device structure
- * @hard_reset: should we do hard reset to all engines or just reset the
- *              compute/dma engines
- */
-static void goya_hw_fini(struct hl_device *hdev, bool hard_reset)
+static int goya_hw_fini(struct hl_device *hdev, bool hard_reset, bool fw_reset)
 {
 	struct goya_device *goya = hdev->asic_specific;
-	u32 reset_timeout_ms, status;
+	u32 reset_timeout_ms, cpu_timeout_ms, status;
 
-	if (hdev->pldm)
+	if (hdev->pldm) {
 		reset_timeout_ms = GOYA_PLDM_RESET_TIMEOUT_MSEC;
-	else
+		cpu_timeout_ms = GOYA_PLDM_RESET_WAIT_MSEC;
+	} else {
 		reset_timeout_ms = GOYA_RESET_TIMEOUT_MSEC;
+		cpu_timeout_ms = GOYA_CPU_RESET_WAIT_MSEC;
+	}
 
 	if (hard_reset) {
+		/* I don't know what is the state of the CPU so make sure it is
+		 * stopped in any means necessary
+		 */
+		WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_GOTO_WFE);
+		WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
+			GOYA_ASYNC_EVENT_ID_HALT_MACHINE);
+
+		msleep(cpu_timeout_ms);
+
 		goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE);
 		goya_disable_clk_rlx(hdev);
 		goya_set_pll_refclk(hdev);
 
 		WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG, RESET_ALL);
-		dev_info(hdev->dev,
+		dev_dbg(hdev->dev,
 			"Issued HARD reset command, going to wait %dms\n",
 			reset_timeout_ms);
 	} else {
 		WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG, DMA_MME_TPC_RESET);
-		dev_info(hdev->dev,
+		dev_dbg(hdev->dev,
 			"Issued SOFT reset command, going to wait %dms\n",
 			reset_timeout_ms);
 	}
@@ -2658,17 +2827,17 @@ static void goya_hw_fini(struct hl_device *hdev, bool hard_reset)
 	msleep(reset_timeout_ms);
 
 	status = RREG32(mmPSOC_GLOBAL_CONF_BTM_FSM);
-	if (status & PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK)
-		dev_err(hdev->dev,
-			"Timeout while waiting for device to reset 0x%x\n",
-			status);
+	if (status & PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK) {
+		dev_err(hdev->dev, "Timeout while waiting for device to reset 0x%x\n", status);
+		return -ETIMEDOUT;
+	}
 
-	if (!hard_reset) {
+	if (!hard_reset && goya) {
 		goya->hw_cap_initialized &= ~(HW_CAP_DMA | HW_CAP_MME |
 						HW_CAP_GOLDEN | HW_CAP_TPC);
 		WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
 				GOYA_ASYNC_EVENT_ID_SOFT_RESET);
-		return;
+		return 0;
 	}
 
 	/* Chicken bit to re-initiate boot sequencer flow */
@@ -2678,47 +2847,21 @@ static void goya_hw_fini(struct hl_device *hdev, bool hard_reset)
 	WREG32(mmPSOC_GLOBAL_CONF_SW_BTM_FSM,
 			0xA << PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_SHIFT);
 
-	goya->hw_cap_initialized &= ~(HW_CAP_CPU | HW_CAP_CPU_Q |
-					HW_CAP_DDR_0 | HW_CAP_DDR_1 |
-					HW_CAP_DMA | HW_CAP_MME |
-					HW_CAP_MMU | HW_CAP_TPC_MBIST |
-					HW_CAP_GOLDEN | HW_CAP_TPC);
-	memset(goya->events_stat, 0, sizeof(goya->events_stat));
-
-	if (!hdev->pldm) {
-		int rc;
-		/* In case we are running inside VM and the VM is
-		 * shutting down, we need to make sure CPU boot-loader
-		 * is running before we can continue the VM shutdown.
-		 * That is because the VM will send an FLR signal that
-		 * we must answer
-		 */
-		dev_info(hdev->dev,
-			"Going to wait up to %ds for CPU boot loader\n",
-			GOYA_CPU_TIMEOUT_USEC / 1000 / 1000);
+	if (goya) {
+		goya->hw_cap_initialized &= ~(HW_CAP_CPU | HW_CAP_CPU_Q |
+				HW_CAP_DDR_0 | HW_CAP_DDR_1 |
+				HW_CAP_DMA | HW_CAP_MME |
+				HW_CAP_MMU | HW_CAP_TPC_MBIST |
+				HW_CAP_GOLDEN | HW_CAP_TPC);
 
-		rc = hl_poll_timeout(
-			hdev,
-			mmPSOC_GLOBAL_CONF_WARM_REBOOT,
-			status,
-			(status == CPU_BOOT_STATUS_DRAM_RDY),
-			10000,
-			GOYA_CPU_TIMEOUT_USEC);
-		if (rc)
-			dev_err(hdev->dev,
-				"failed to wait for CPU boot loader\n");
+		memset(goya->events_stat, 0, sizeof(goya->events_stat));
 	}
+	return 0;
 }
 
 int goya_suspend(struct hl_device *hdev)
 {
-	int rc;
-
-	rc = hl_fw_send_pci_access_msg(hdev, ARMCP_PACKET_DISABLE_PCI_ACCESS);
-	if (rc)
-		dev_err(hdev->dev, "Failed to disable PCI access from CPU\n");
-
-	return rc;
+	return hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_DISABLE_PCI_ACCESS, 0x0);
 }
 
 int goya_resume(struct hl_device *hdev)
@@ -2726,18 +2869,18 @@ int goya_resume(struct hl_device *hdev)
 	return goya_init_iatu(hdev);
 }
 
-static int goya_cb_mmap(struct hl_device *hdev, struct vm_area_struct *vma,
-		u64 kaddress, phys_addr_t paddress, u32 size)
+static int goya_mmap(struct hl_device *hdev, struct vm_area_struct *vma,
+			void *cpu_addr, dma_addr_t dma_addr, size_t size)
 {
 	int rc;
 
-	vma->vm_flags |= VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP |
-			VM_DONTCOPY | VM_NORESERVE;
+	vm_flags_set(vma, VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP |
+			VM_DONTCOPY | VM_NORESERVE);
 
-	rc = remap_pfn_range(vma, vma->vm_start, paddress >> PAGE_SHIFT,
-				size, vma->vm_page_prot);
+	rc = dma_mmap_coherent(hdev->dev, vma, cpu_addr,
+				(dma_addr - HOST_PHYS_BASE), size);
 	if (rc)
-		dev_err(hdev->dev, "remap_pfn_range error %d", rc);
+		dev_err(hdev->dev, "dma_mmap_coherent error %d", rc);
 
 	return rc;
 }
@@ -2819,9 +2962,12 @@ void goya_ring_doorbell(struct hl_device *hdev, u32 hw_queue_id, u32 pi)
 	/* ring the doorbell */
 	WREG32(db_reg_offset, db_value);
 
-	if (hw_queue_id == GOYA_QUEUE_ID_CPU_PQ)
+	if (hw_queue_id == GOYA_QUEUE_ID_CPU_PQ) {
+		/* make sure device CPU will read latest data from host */
+		mb();
 		WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
 				GOYA_ASYNC_EVENT_ID_PI_UPDATE);
+	}
 }
 
 void goya_pqe_write(struct hl_device *hdev, __le64 *pqe, struct hl_bd *bd)
@@ -2852,6 +2998,11 @@ static void goya_dma_free_coherent(struct hl_device *hdev, size_t size,
 	dma_free_coherent(&hdev->pdev->dev, size, cpu_addr, fixed_dma_handle);
 }
 
+int goya_scrub_device_mem(struct hl_device *hdev)
+{
+	return 0;
+}
+
 void *goya_get_int_queue_base(struct hl_device *hdev, u32 queue_id,
 				dma_addr_t *dma_handle,	u16 *queue_len)
 {
@@ -2860,7 +3011,7 @@ void *goya_get_int_queue_base(struct hl_device *hdev, u32 queue_id,
 
 	*dma_handle = hdev->asic_prop.sram_base_address;
 
-	base = (void *) hdev->pcie_bar[SRAM_CFG_BAR_ID];
+	base = (__force void *) hdev->pcie_bar[SRAM_CFG_BAR_ID];
 
 	switch (queue_id) {
 	case GOYA_QUEUE_ID_MME:
@@ -2924,14 +3075,13 @@ static int goya_send_job_on_qman0(struct hl_device *hdev, struct hl_cs_job *job)
 	else
 		timeout = HL_DEVICE_TIMEOUT_USEC;
 
-	if (!hdev->asic_funcs->is_device_idle(hdev, NULL, NULL)) {
+	if (!hdev->asic_funcs->is_device_idle(hdev, NULL, 0, NULL)) {
 		dev_err_ratelimited(hdev->dev,
 			"Can't send driver job on QMAN0 because the device is not idle\n");
 		return -EBUSY;
 	}
 
-	fence_ptr = hdev->asic_funcs->asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL,
-							&fence_dma_addr);
+	fence_ptr = hl_asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL, &fence_dma_addr);
 	if (!fence_ptr) {
 		dev_err(hdev->dev,
 			"Failed to allocate fence memory for QMAN0\n");
@@ -2942,8 +3092,8 @@ static int goya_send_job_on_qman0(struct hl_device *hdev, struct hl_cs_job *job)
 
 	cb = job->patched_cb;
 
-	fence_pkt = (struct packet_msg_prot *) (uintptr_t) (cb->kernel_address +
-			job->job_cb_size - sizeof(struct packet_msg_prot));
+	fence_pkt = cb->kernel_address +
+			job->job_cb_size - sizeof(struct packet_msg_prot);
 
 	tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
 			(1 << GOYA_PKT_CTL_EB_SHIFT) |
@@ -2971,8 +3121,7 @@ static int goya_send_job_on_qman0(struct hl_device *hdev, struct hl_cs_job *job)
 	}
 
 free_fence_ptr:
-	hdev->asic_funcs->asic_dma_pool_free(hdev, (void *) fence_ptr,
-					fence_dma_addr);
+	hl_asic_dma_pool_free(hdev, (void *) fence_ptr, fence_dma_addr);
 
 	goya_qman0_set_security(hdev, false);
 
@@ -2980,7 +3129,7 @@ free_fence_ptr:
 }
 
 int goya_send_cpu_message(struct hl_device *hdev, u32 *msg, u16 len,
-				u32 timeout, long *result)
+				u32 timeout, u64 *result)
 {
 	struct goya_device *goya = hdev->asic_specific;
 
@@ -2990,6 +3139,9 @@ int goya_send_cpu_message(struct hl_device *hdev, u32 *msg, u16 len,
 		return 0;
 	}
 
+	if (!timeout)
+		timeout = GOYA_MSG_TO_CPU_TIMEOUT_USEC;
+
 	return hl_fw_send_cpu_message(hdev, GOYA_QUEUE_ID_CPU_PQ, msg, len,
 					timeout, result);
 }
@@ -3005,22 +3157,22 @@ int goya_test_queue(struct hl_device *hdev, u32 hw_queue_id)
 
 	fence_val = GOYA_QMAN0_FENCE_VAL;
 
-	fence_ptr = hdev->asic_funcs->asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL,
-							&fence_dma_addr);
+	fence_ptr = hl_asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL, &fence_dma_addr);
 	if (!fence_ptr) {
 		dev_err(hdev->dev,
-			"Failed to allocate memory for queue testing\n");
+			"Failed to allocate memory for H/W queue %d testing\n",
+			hw_queue_id);
 		return -ENOMEM;
 	}
 
 	*fence_ptr = 0;
 
-	fence_pkt = hdev->asic_funcs->asic_dma_pool_zalloc(hdev,
-					sizeof(struct packet_msg_prot),
-					GFP_KERNEL, &pkt_dma_addr);
+	fence_pkt = hl_asic_dma_pool_zalloc(hdev, sizeof(struct packet_msg_prot), GFP_KERNEL,
+						&pkt_dma_addr);
 	if (!fence_pkt) {
 		dev_err(hdev->dev,
-			"Failed to allocate packet for queue testing\n");
+			"Failed to allocate packet for H/W queue %d testing\n",
+			hw_queue_id);
 		rc = -ENOMEM;
 		goto free_fence_ptr;
 	}
@@ -3037,7 +3189,8 @@ int goya_test_queue(struct hl_device *hdev, u32 hw_queue_id)
 					pkt_dma_addr);
 	if (rc) {
 		dev_err(hdev->dev,
-			"Failed to send fence packet\n");
+			"Failed to send fence packet to H/W queue %d\n",
+			hw_queue_id);
 		goto free_pkt;
 	}
 
@@ -3054,11 +3207,9 @@ int goya_test_queue(struct hl_device *hdev, u32 hw_queue_id)
 	}
 
 free_pkt:
-	hdev->asic_funcs->asic_dma_pool_free(hdev, (void *) fence_pkt,
-					pkt_dma_addr);
+	hl_asic_dma_pool_free(hdev, (void *) fence_pkt, pkt_dma_addr);
 free_fence_ptr:
-	hdev->asic_funcs->asic_dma_pool_free(hdev, (void *) fence_ptr,
-					fence_dma_addr);
+	hl_asic_dma_pool_free(hdev, (void *) fence_ptr, fence_dma_addr);
 	return rc;
 }
 
@@ -3133,35 +3284,6 @@ void goya_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size,
 	hl_fw_cpu_accessible_dma_pool_free(hdev, size, vaddr);
 }
 
-static int goya_dma_map_sg(struct hl_device *hdev, struct scatterlist *sgl,
-				int nents, enum dma_data_direction dir)
-{
-	struct scatterlist *sg;
-	int i;
-
-	if (!dma_map_sg(&hdev->pdev->dev, sgl, nents, dir))
-		return -ENOMEM;
-
-	/* Shift to the device's base physical address of host memory */
-	for_each_sg(sgl, sg, nents, i)
-		sg->dma_address += HOST_PHYS_BASE;
-
-	return 0;
-}
-
-static void goya_dma_unmap_sg(struct hl_device *hdev, struct scatterlist *sgl,
-				int nents, enum dma_data_direction dir)
-{
-	struct scatterlist *sg;
-	int i;
-
-	/* Cancel the device's base physical address of host memory */
-	for_each_sg(sgl, sg, nents, i)
-		sg->dma_address -= HOST_PHYS_BASE;
-
-	dma_unmap_sg(&hdev->pdev->dev, sgl, nents, dir);
-}
-
 u32 goya_get_dma_desc_list_size(struct hl_device *hdev, struct sg_table *sgt)
 {
 	struct scatterlist *sg, *sg_next_iter;
@@ -3171,8 +3293,7 @@ u32 goya_get_dma_desc_list_size(struct hl_device *hdev, struct sg_table *sgt)
 
 	dma_desc_cnt = 0;
 
-	for_each_sg(sgt->sgl, sg, sgt->nents, count) {
-
+	for_each_sgtable_dma_sg(sgt, sg, count) {
 		len = sg_dma_len(sg);
 		addr = sg_dma_address(sg);
 
@@ -3215,7 +3336,7 @@ static int goya_pin_memory_before_cs(struct hl_device *hdev,
 			parser->job_userptr_list, &userptr))
 		goto already_pinned;
 
-	userptr = kzalloc(sizeof(*userptr), GFP_ATOMIC);
+	userptr = kzalloc(sizeof(*userptr), GFP_KERNEL);
 	if (!userptr)
 		return -ENOMEM;
 
@@ -3226,8 +3347,7 @@ static int goya_pin_memory_before_cs(struct hl_device *hdev,
 
 	list_add_tail(&userptr->job_node, parser->job_userptr_list);
 
-	rc = hdev->asic_funcs->asic_dma_map_sg(hdev, userptr->sgt->sgl,
-					userptr->sgt->nents, dir);
+	rc = hl_dma_map_sgtable(hdev, userptr->sgt, dir);
 	if (rc) {
 		dev_err(hdev->dev, "failed to map sgt with DMA region\n");
 		goto unpin_memory;
@@ -3243,6 +3363,7 @@ already_pinned:
 	return 0;
 
 unpin_memory:
+	list_del(&userptr->job_node);
 	hl_unpin_host_memory(hdev, userptr);
 free_userptr:
 	kfree(userptr);
@@ -3255,7 +3376,7 @@ static int goya_validate_dma_pkt_host(struct hl_device *hdev,
 {
 	u64 device_memory_addr, addr;
 	enum dma_data_direction dir;
-	enum goya_dma_direction user_dir;
+	enum hl_goya_dma_direction user_dir;
 	bool sram_addr = true;
 	bool skip_host_mem_pin = false;
 	bool user_memset;
@@ -3271,7 +3392,7 @@ static int goya_validate_dma_pkt_host(struct hl_device *hdev,
 			GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT;
 
 	switch (user_dir) {
-	case DMA_HOST_TO_DRAM:
+	case HL_DMA_HOST_TO_DRAM:
 		dev_dbg(hdev->dev, "DMA direction is HOST --> DRAM\n");
 		dir = DMA_TO_DEVICE;
 		sram_addr = false;
@@ -3281,7 +3402,7 @@ static int goya_validate_dma_pkt_host(struct hl_device *hdev,
 			skip_host_mem_pin = true;
 		break;
 
-	case DMA_DRAM_TO_HOST:
+	case HL_DMA_DRAM_TO_HOST:
 		dev_dbg(hdev->dev, "DMA direction is DRAM --> HOST\n");
 		dir = DMA_FROM_DEVICE;
 		sram_addr = false;
@@ -3289,7 +3410,7 @@ static int goya_validate_dma_pkt_host(struct hl_device *hdev,
 		device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
 		break;
 
-	case DMA_HOST_TO_SRAM:
+	case HL_DMA_HOST_TO_SRAM:
 		dev_dbg(hdev->dev, "DMA direction is HOST --> SRAM\n");
 		dir = DMA_TO_DEVICE;
 		addr = le64_to_cpu(user_dma_pkt->src_addr);
@@ -3298,14 +3419,14 @@ static int goya_validate_dma_pkt_host(struct hl_device *hdev,
 			skip_host_mem_pin = true;
 		break;
 
-	case DMA_SRAM_TO_HOST:
+	case HL_DMA_SRAM_TO_HOST:
 		dev_dbg(hdev->dev, "DMA direction is SRAM --> HOST\n");
 		dir = DMA_FROM_DEVICE;
 		addr = le64_to_cpu(user_dma_pkt->dst_addr);
 		device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
 		break;
 	default:
-		dev_err(hdev->dev, "DMA direction is undefined\n");
+		dev_err(hdev->dev, "DMA direction %d is unsupported/undefined\n", user_dir);
 		return -EFAULT;
 	}
 
@@ -3357,14 +3478,14 @@ static int goya_validate_dma_pkt_no_host(struct hl_device *hdev,
 				struct packet_lin_dma *user_dma_pkt)
 {
 	u64 sram_memory_addr, dram_memory_addr;
-	enum goya_dma_direction user_dir;
+	enum hl_goya_dma_direction user_dir;
 	u32 ctl;
 
 	ctl = le32_to_cpu(user_dma_pkt->ctl);
 	user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
 			GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
 
-	if (user_dir == DMA_DRAM_TO_SRAM) {
+	if (user_dir == HL_DMA_DRAM_TO_SRAM) {
 		dev_dbg(hdev->dev, "DMA direction is DRAM --> SRAM\n");
 		dram_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
 		sram_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
@@ -3401,7 +3522,7 @@ static int goya_validate_dma_pkt_no_mmu(struct hl_device *hdev,
 				struct hl_cs_parser *parser,
 				struct packet_lin_dma *user_dma_pkt)
 {
-	enum goya_dma_direction user_dir;
+	enum hl_goya_dma_direction user_dir;
 	u32 ctl;
 	int rc;
 
@@ -3426,7 +3547,7 @@ static int goya_validate_dma_pkt_no_mmu(struct hl_device *hdev,
 		return -EINVAL;
 	}
 
-	if ((user_dir == DMA_DRAM_TO_SRAM) || (user_dir == DMA_SRAM_TO_DRAM))
+	if ((user_dir == HL_DMA_DRAM_TO_SRAM) || (user_dir == HL_DMA_SRAM_TO_DRAM))
 		rc = goya_validate_dma_pkt_no_host(hdev, parser, user_dma_pkt);
 	else
 		rc = goya_validate_dma_pkt_host(hdev, parser, user_dma_pkt);
@@ -3529,14 +3650,19 @@ static int goya_validate_cb(struct hl_device *hdev,
 		u16 pkt_size;
 		struct goya_packet *user_pkt;
 
-		user_pkt = (struct goya_packet *) (uintptr_t)
-			(parser->user_cb->kernel_address + cb_parsed_length);
+		user_pkt = parser->user_cb->kernel_address + cb_parsed_length;
 
 		pkt_id = (enum packet_id) (
 				(le64_to_cpu(user_pkt->header) &
 				PACKET_HEADER_PACKET_ID_MASK) >>
 					PACKET_HEADER_PACKET_ID_SHIFT);
 
+		if (!validate_packet_id(pkt_id)) {
+			dev_err(hdev->dev, "Invalid packet id %u\n", pkt_id);
+			rc = -EINVAL;
+			break;
+		}
+
 		pkt_size = goya_packet_sizes[pkt_id];
 		cb_parsed_length += pkt_size;
 		if (cb_parsed_length > parser->user_cb_size) {
@@ -3555,6 +3681,7 @@ static int goya_validate_cb(struct hl_device *hdev,
 			 */
 			rc = goya_validate_wreg32(hdev,
 				parser, (struct packet_wreg32 *) user_pkt);
+			parser->patched_cb_size += pkt_size;
 			break;
 
 		case PACKET_WREG_BULK:
@@ -3627,7 +3754,7 @@ static int goya_patch_dma_packet(struct hl_device *hdev,
 	u32 count, dma_desc_cnt;
 	u64 len, len_next;
 	dma_addr_t dma_addr, dma_addr_next;
-	enum goya_dma_direction user_dir;
+	enum hl_goya_dma_direction user_dir;
 	u64 device_memory_addr, addr;
 	enum dma_data_direction dir;
 	struct sg_table *sgt;
@@ -3643,14 +3770,14 @@ static int goya_patch_dma_packet(struct hl_device *hdev,
 	user_memset = (ctl & GOYA_PKT_LIN_DMA_CTL_MEMSET_MASK) >>
 			GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT;
 
-	if ((user_dir == DMA_DRAM_TO_SRAM) || (user_dir == DMA_SRAM_TO_DRAM) ||
+	if ((user_dir == HL_DMA_DRAM_TO_SRAM) || (user_dir == HL_DMA_SRAM_TO_DRAM) ||
 			(user_dma_pkt->tsize == 0)) {
 		memcpy(new_dma_pkt, user_dma_pkt, sizeof(*new_dma_pkt));
 		*new_dma_pkt_size = sizeof(*new_dma_pkt);
 		return 0;
 	}
 
-	if ((user_dir == DMA_HOST_TO_DRAM) || (user_dir == DMA_HOST_TO_SRAM)) {
+	if ((user_dir == HL_DMA_HOST_TO_DRAM) || (user_dir == HL_DMA_HOST_TO_SRAM)) {
 		addr = le64_to_cpu(user_dma_pkt->src_addr);
 		device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
 		dir = DMA_TO_DEVICE;
@@ -3684,7 +3811,7 @@ static int goya_patch_dma_packet(struct hl_device *hdev,
 	sgt = userptr->sgt;
 	dma_desc_cnt = 0;
 
-	for_each_sg(sgt->sgl, sg, sgt->nents, count) {
+	for_each_sgtable_dma_sg(sgt, sg, count) {
 		len = sg_dma_len(sg);
 		dma_addr = sg_dma_address(sg);
 
@@ -3760,17 +3887,21 @@ static int goya_patch_cb(struct hl_device *hdev,
 		u32 new_pkt_size = 0;
 		struct goya_packet *user_pkt, *kernel_pkt;
 
-		user_pkt = (struct goya_packet *) (uintptr_t)
-			(parser->user_cb->kernel_address + cb_parsed_length);
-		kernel_pkt = (struct goya_packet *) (uintptr_t)
-			(parser->patched_cb->kernel_address +
-					cb_patched_cur_length);
+		user_pkt = parser->user_cb->kernel_address + cb_parsed_length;
+		kernel_pkt = parser->patched_cb->kernel_address +
+					cb_patched_cur_length;
 
 		pkt_id = (enum packet_id) (
 				(le64_to_cpu(user_pkt->header) &
 				PACKET_HEADER_PACKET_ID_MASK) >>
 					PACKET_HEADER_PACKET_ID_SHIFT);
 
+		if (!validate_packet_id(pkt_id)) {
+			dev_err(hdev->dev, "Invalid packet id %u\n", pkt_id);
+			rc = -EINVAL;
+			break;
+		}
+
 		pkt_size = goya_packet_sizes[pkt_id];
 		cb_parsed_length += pkt_size;
 		if (cb_parsed_length > parser->user_cb_size) {
@@ -3843,7 +3974,7 @@ static int goya_patch_cb(struct hl_device *hdev,
 static int goya_parse_cb_mmu(struct hl_device *hdev,
 		struct hl_cs_parser *parser)
 {
-	u64 patched_cb_handle;
+	u64 handle;
 	u32 patched_cb_size;
 	struct hl_cb *user_cb;
 	int rc;
@@ -3856,9 +3987,9 @@ static int goya_parse_cb_mmu(struct hl_device *hdev,
 	parser->patched_cb_size = parser->user_cb_size +
 			sizeof(struct packet_msg_prot) * 2;
 
-	rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr,
-				parser->patched_cb_size,
-				&patched_cb_handle, HL_KERNEL_ASID_ID);
+	rc = hl_cb_create(hdev, &hdev->kernel_mem_mgr, hdev->kernel_ctx,
+				parser->patched_cb_size, false, false,
+				&handle);
 
 	if (rc) {
 		dev_err(hdev->dev,
@@ -3867,13 +3998,10 @@ static int goya_parse_cb_mmu(struct hl_device *hdev,
 		return rc;
 	}
 
-	patched_cb_handle >>= PAGE_SHIFT;
-	parser->patched_cb = hl_cb_get(hdev, &hdev->kernel_cb_mgr,
-				(u32) patched_cb_handle);
-	/* hl_cb_get should never fail here so use kernel WARN */
-	WARN(!parser->patched_cb, "DMA CB handle invalid 0x%x\n",
-			(u32) patched_cb_handle);
+	parser->patched_cb = hl_cb_get(&hdev->kernel_mem_mgr, handle);
+	/* hl_cb_get should never fail here */
 	if (!parser->patched_cb) {
+		dev_crit(hdev->dev, "DMA CB handle invalid 0x%llx\n", handle);
 		rc = -EFAULT;
 		goto out;
 	}
@@ -3882,8 +4010,8 @@ static int goya_parse_cb_mmu(struct hl_device *hdev,
 	 * The check that parser->user_cb_size <= parser->user_cb->size was done
 	 * in validate_queue_index().
 	 */
-	memcpy((void *) (uintptr_t) parser->patched_cb->kernel_address,
-		(void *) (uintptr_t) parser->user_cb->kernel_address,
+	memcpy(parser->patched_cb->kernel_address,
+		parser->user_cb->kernel_address,
 		parser->user_cb_size);
 
 	patched_cb_size = parser->patched_cb_size;
@@ -3913,8 +4041,7 @@ out:
 	 * cb_put will release it, but here we want to remove it from the
 	 * idr
 	 */
-	hl_cb_destroy(hdev, &hdev->kernel_cb_mgr,
-					patched_cb_handle << PAGE_SHIFT);
+	hl_cb_destroy(&hdev->kernel_mem_mgr, handle);
 
 	return rc;
 }
@@ -3922,7 +4049,7 @@ out:
 static int goya_parse_cb_no_mmu(struct hl_device *hdev,
 				struct hl_cs_parser *parser)
 {
-	u64 patched_cb_handle;
+	u64 handle;
 	int rc;
 
 	rc = goya_validate_cb(hdev, parser, false);
@@ -3930,22 +4057,19 @@ static int goya_parse_cb_no_mmu(struct hl_device *hdev,
 	if (rc)
 		goto free_userptr;
 
-	rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr,
-				parser->patched_cb_size,
-				&patched_cb_handle, HL_KERNEL_ASID_ID);
+	rc = hl_cb_create(hdev, &hdev->kernel_mem_mgr, hdev->kernel_ctx,
+				parser->patched_cb_size, false, false,
+				&handle);
 	if (rc) {
 		dev_err(hdev->dev,
 			"Failed to allocate patched CB for DMA CS %d\n", rc);
 		goto free_userptr;
 	}
 
-	patched_cb_handle >>= PAGE_SHIFT;
-	parser->patched_cb = hl_cb_get(hdev, &hdev->kernel_cb_mgr,
-				(u32) patched_cb_handle);
-	/* hl_cb_get should never fail here so use kernel WARN */
-	WARN(!parser->patched_cb, "DMA CB handle invalid 0x%x\n",
-			(u32) patched_cb_handle);
+	parser->patched_cb = hl_cb_get(&hdev->kernel_mem_mgr, handle);
+	/* hl_cb_get should never fail here */
 	if (!parser->patched_cb) {
+		dev_crit(hdev->dev, "DMA CB handle invalid 0x%llx\n", handle);
 		rc = -EFAULT;
 		goto out;
 	}
@@ -3962,8 +4086,7 @@ out:
 	 * cb_put will release it, but here we want to remove it from the
 	 * idr
 	 */
-	hl_cb_destroy(hdev, &hdev->kernel_cb_mgr,
-				patched_cb_handle << PAGE_SHIFT);
+	hl_cb_destroy(&hdev->kernel_mem_mgr, handle);
 
 free_userptr:
 	if (rc)
@@ -4015,14 +4138,14 @@ int goya_cs_parser(struct hl_device *hdev, struct hl_cs_parser *parser)
 		return goya_parse_cb_no_mmu(hdev, parser);
 }
 
-void goya_add_end_of_cb_packets(struct hl_device *hdev, u64 kernel_address,
-				u32 len, u64 cq_addr, u32 cq_val, u32 msix_vec)
+void goya_add_end_of_cb_packets(struct hl_device *hdev, void *kernel_address,
+				u32 len, u32 original_len, u64 cq_addr, u32 cq_val,
+				u32 msix_vec, bool eb)
 {
 	struct packet_msg_prot *cq_pkt;
 	u32 tmp;
 
-	cq_pkt = (struct packet_msg_prot *) (uintptr_t)
-		(kernel_address + len - (sizeof(struct packet_msg_prot) * 2));
+	cq_pkt = kernel_address + len - (sizeof(struct packet_msg_prot) * 2);
 
 	tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
 			(1 << GOYA_PKT_CTL_EB_SHIFT) |
@@ -4070,215 +4193,17 @@ static void goya_clear_sm_regs(struct hl_device *hdev)
 	i = RREG32(mmSYNC_MNGR_SOB_OBJ_0);
 }
 
-/*
- * goya_debugfs_read32 - read a 32bit value from a given device or a host mapped
- *                       address.
- *
- * @hdev:	pointer to hl_device structure
- * @addr:	device or host mapped address
- * @val:	returned value
- *
- * In case of DDR address that is not mapped into the default aperture that
- * the DDR bar exposes, the function will configure the iATU so that the DDR
- * bar will be positioned at a base address that allows reading from the
- * required address. Configuring the iATU during normal operation can
- * lead to undefined behavior and therefore, should be done with extreme care
- *
- */
-static int goya_debugfs_read32(struct hl_device *hdev, u64 addr, u32 *val)
-{
-	struct asic_fixed_properties *prop = &hdev->asic_prop;
-	u64 ddr_bar_addr;
-	int rc = 0;
-
-	if ((addr >= CFG_BASE) && (addr < CFG_BASE + CFG_SIZE)) {
-		*val = RREG32(addr - CFG_BASE);
-
-	} else if ((addr >= SRAM_BASE_ADDR) &&
-			(addr < SRAM_BASE_ADDR + SRAM_SIZE)) {
-
-		*val = readl(hdev->pcie_bar[SRAM_CFG_BAR_ID] +
-				(addr - SRAM_BASE_ADDR));
-
-	} else if ((addr >= DRAM_PHYS_BASE) &&
-			(addr < DRAM_PHYS_BASE + hdev->asic_prop.dram_size)) {
-
-		u64 bar_base_addr = DRAM_PHYS_BASE +
-				(addr & ~(prop->dram_pci_bar_size - 0x1ull));
-
-		ddr_bar_addr = goya_set_ddr_bar_base(hdev, bar_base_addr);
-		if (ddr_bar_addr != U64_MAX) {
-			*val = readl(hdev->pcie_bar[DDR_BAR_ID] +
-						(addr - bar_base_addr));
-
-			ddr_bar_addr = goya_set_ddr_bar_base(hdev,
-							ddr_bar_addr);
-		}
-		if (ddr_bar_addr == U64_MAX)
-			rc = -EIO;
-
-	} else if (addr >= HOST_PHYS_BASE && !iommu_present(&pci_bus_type)) {
-		*val = *(u32 *) phys_to_virt(addr - HOST_PHYS_BASE);
-
-	} else {
-		rc = -EFAULT;
-	}
-
-	return rc;
-}
-
-/*
- * goya_debugfs_write32 - write a 32bit value to a given device or a host mapped
- *                        address.
- *
- * @hdev:	pointer to hl_device structure
- * @addr:	device or host mapped address
- * @val:	returned value
- *
- * In case of DDR address that is not mapped into the default aperture that
- * the DDR bar exposes, the function will configure the iATU so that the DDR
- * bar will be positioned at a base address that allows writing to the
- * required address. Configuring the iATU during normal operation can
- * lead to undefined behavior and therefore, should be done with extreme care
- *
- */
-static int goya_debugfs_write32(struct hl_device *hdev, u64 addr, u32 val)
-{
-	struct asic_fixed_properties *prop = &hdev->asic_prop;
-	u64 ddr_bar_addr;
-	int rc = 0;
-
-	if ((addr >= CFG_BASE) && (addr < CFG_BASE + CFG_SIZE)) {
-		WREG32(addr - CFG_BASE, val);
-
-	} else if ((addr >= SRAM_BASE_ADDR) &&
-			(addr < SRAM_BASE_ADDR + SRAM_SIZE)) {
-
-		writel(val, hdev->pcie_bar[SRAM_CFG_BAR_ID] +
-					(addr - SRAM_BASE_ADDR));
-
-	} else if ((addr >= DRAM_PHYS_BASE) &&
-			(addr < DRAM_PHYS_BASE + hdev->asic_prop.dram_size)) {
-
-		u64 bar_base_addr = DRAM_PHYS_BASE +
-				(addr & ~(prop->dram_pci_bar_size - 0x1ull));
-
-		ddr_bar_addr = goya_set_ddr_bar_base(hdev, bar_base_addr);
-		if (ddr_bar_addr != U64_MAX) {
-			writel(val, hdev->pcie_bar[DDR_BAR_ID] +
-						(addr - bar_base_addr));
-
-			ddr_bar_addr = goya_set_ddr_bar_base(hdev,
-							ddr_bar_addr);
-		}
-		if (ddr_bar_addr == U64_MAX)
-			rc = -EIO;
-
-	} else if (addr >= HOST_PHYS_BASE && !iommu_present(&pci_bus_type)) {
-		*(u32 *) phys_to_virt(addr - HOST_PHYS_BASE) = val;
-
-	} else {
-		rc = -EFAULT;
-	}
-
-	return rc;
-}
-
-static int goya_debugfs_read64(struct hl_device *hdev, u64 addr, u64 *val)
-{
-	struct asic_fixed_properties *prop = &hdev->asic_prop;
-	u64 ddr_bar_addr;
-	int rc = 0;
-
-	if ((addr >= CFG_BASE) && (addr <= CFG_BASE + CFG_SIZE - sizeof(u64))) {
-		u32 val_l = RREG32(addr - CFG_BASE);
-		u32 val_h = RREG32(addr + sizeof(u32) - CFG_BASE);
-
-		*val = (((u64) val_h) << 32) | val_l;
-
-	} else if ((addr >= SRAM_BASE_ADDR) &&
-			(addr <= SRAM_BASE_ADDR + SRAM_SIZE - sizeof(u64))) {
-
-		*val = readq(hdev->pcie_bar[SRAM_CFG_BAR_ID] +
-				(addr - SRAM_BASE_ADDR));
-
-	} else if ((addr >= DRAM_PHYS_BASE) &&
-		   (addr <=
-		    DRAM_PHYS_BASE + hdev->asic_prop.dram_size - sizeof(u64))) {
-
-		u64 bar_base_addr = DRAM_PHYS_BASE +
-				(addr & ~(prop->dram_pci_bar_size - 0x1ull));
-
-		ddr_bar_addr = goya_set_ddr_bar_base(hdev, bar_base_addr);
-		if (ddr_bar_addr != U64_MAX) {
-			*val = readq(hdev->pcie_bar[DDR_BAR_ID] +
-						(addr - bar_base_addr));
-
-			ddr_bar_addr = goya_set_ddr_bar_base(hdev,
-							ddr_bar_addr);
-		}
-		if (ddr_bar_addr == U64_MAX)
-			rc = -EIO;
-
-	} else if (addr >= HOST_PHYS_BASE && !iommu_present(&pci_bus_type)) {
-		*val = *(u64 *) phys_to_virt(addr - HOST_PHYS_BASE);
-
-	} else {
-		rc = -EFAULT;
-	}
-
-	return rc;
-}
-
-static int goya_debugfs_write64(struct hl_device *hdev, u64 addr, u64 val)
+static int goya_debugfs_read_dma(struct hl_device *hdev, u64 addr, u32 size, void *blob_addr)
 {
-	struct asic_fixed_properties *prop = &hdev->asic_prop;
-	u64 ddr_bar_addr;
-	int rc = 0;
-
-	if ((addr >= CFG_BASE) && (addr <= CFG_BASE + CFG_SIZE - sizeof(u64))) {
-		WREG32(addr - CFG_BASE, lower_32_bits(val));
-		WREG32(addr + sizeof(u32) - CFG_BASE, upper_32_bits(val));
-
-	} else if ((addr >= SRAM_BASE_ADDR) &&
-			(addr <= SRAM_BASE_ADDR + SRAM_SIZE - sizeof(u64))) {
-
-		writeq(val, hdev->pcie_bar[SRAM_CFG_BAR_ID] +
-					(addr - SRAM_BASE_ADDR));
-
-	} else if ((addr >= DRAM_PHYS_BASE) &&
-		   (addr <=
-		    DRAM_PHYS_BASE + hdev->asic_prop.dram_size - sizeof(u64))) {
-
-		u64 bar_base_addr = DRAM_PHYS_BASE +
-				(addr & ~(prop->dram_pci_bar_size - 0x1ull));
-
-		ddr_bar_addr = goya_set_ddr_bar_base(hdev, bar_base_addr);
-		if (ddr_bar_addr != U64_MAX) {
-			writeq(val, hdev->pcie_bar[DDR_BAR_ID] +
-						(addr - bar_base_addr));
-
-			ddr_bar_addr = goya_set_ddr_bar_base(hdev,
-							ddr_bar_addr);
-		}
-		if (ddr_bar_addr == U64_MAX)
-			rc = -EIO;
-
-	} else if (addr >= HOST_PHYS_BASE && !iommu_present(&pci_bus_type)) {
-		*(u64 *) phys_to_virt(addr - HOST_PHYS_BASE) = val;
-
-	} else {
-		rc = -EFAULT;
-	}
-
-	return rc;
+	dev_err(hdev->dev, "Reading via DMA is unimplemented yet\n");
+	return -EPERM;
 }
 
 static u64 goya_read_pte(struct hl_device *hdev, u64 addr)
 {
 	struct goya_device *goya = hdev->asic_specific;
 
-	if (hdev->hard_reset_pending)
+	if (hdev->reset_info.hard_reset_pending)
 		return U64_MAX;
 
 	return readq(hdev->pcie_bar[DDR_BAR_ID] +
@@ -4289,7 +4214,7 @@ static void goya_write_pte(struct hl_device *hdev, u64 addr, u64 val)
 {
 	struct goya_device *goya = hdev->asic_specific;
 
-	if (hdev->hard_reset_pending)
+	if (hdev->reset_info.hard_reset_pending)
 		return;
 
 	writeq(val, hdev->pcie_bar[DDR_BAR_ID] +
@@ -4401,6 +4326,8 @@ static const char *_goya_get_event_desc(u16 event_type)
 		return "THERMAL_ENV_S";
 	case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_E:
 		return "THERMAL_ENV_E";
+	case GOYA_ASYNC_EVENT_PKT_QUEUE_OUT_SYNC:
+		return "QUEUE_OUT_OF_SYNC";
 	default:
 		return "N/A";
 	}
@@ -4483,6 +4410,9 @@ static void goya_get_event_desc(u16 event_type, char *desc, size_t size)
 		index = event_type - GOYA_ASYNC_EVENT_ID_DMA_BM_CH0;
 		snprintf(desc, size, _goya_get_event_desc(event_type), index);
 		break;
+	case GOYA_ASYNC_EVENT_PKT_QUEUE_OUT_SYNC:
+		snprintf(desc, size, _goya_get_event_desc(event_type));
+		break;
 	default:
 		snprintf(desc, size, _goya_get_event_desc(event_type));
 		break;
@@ -4534,6 +4464,15 @@ static void goya_print_mmu_error_info(struct hl_device *hdev)
 	}
 }
 
+static void goya_print_out_of_sync_info(struct hl_device *hdev,
+					struct cpucp_pkt_sync_err *sync_err)
+{
+	struct hl_hw_queue *q = &hdev->kernel_queues[GOYA_QUEUE_ID_CPU_PQ];
+
+	dev_err(hdev->dev, "Out of sync with FW, FW: pi=%u, ci=%u, LKD: pi=%u, ci=%d\n",
+		le32_to_cpu(sync_err->pi), le32_to_cpu(sync_err->ci), q->pi, atomic_read(&q->ci));
+}
+
 static void goya_print_irq_info(struct hl_device *hdev, u16 event_type,
 				bool razwi)
 {
@@ -4552,17 +4491,17 @@ static void goya_print_irq_info(struct hl_device *hdev, u16 event_type,
 static int goya_unmask_irq_arr(struct hl_device *hdev, u32 *irq_arr,
 		size_t irq_arr_size)
 {
-	struct armcp_unmask_irq_arr_packet *pkt;
+	struct cpucp_unmask_irq_arr_packet *pkt;
 	size_t total_pkt_size;
-	long result;
+	u64 result;
 	int rc;
 	int irq_num_entries, irq_arr_index;
 	__le32 *goya_irq_arr;
 
-	total_pkt_size = sizeof(struct armcp_unmask_irq_arr_packet) +
+	total_pkt_size = sizeof(struct cpucp_unmask_irq_arr_packet) +
 			irq_arr_size;
 
-	/* data should be aligned to 8 bytes in order to ArmCP to copy it */
+	/* data should be aligned to 8 bytes in order to CPU-CP to copy it */
 	total_pkt_size = (total_pkt_size + 0x7) & ~0x7;
 
 	/* total_pkt_size is casted to u16 later on */
@@ -4586,11 +4525,11 @@ static int goya_unmask_irq_arr(struct hl_device *hdev, u32 *irq_arr,
 		goya_irq_arr[irq_arr_index] =
 				cpu_to_le32(irq_arr[irq_arr_index]);
 
-	pkt->armcp_pkt.ctl = cpu_to_le32(ARMCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY <<
-						ARMCP_PKT_CTL_OPCODE_SHIFT);
+	pkt->cpucp_pkt.ctl = cpu_to_le32(CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY <<
+						CPUCP_PKT_CTL_OPCODE_SHIFT);
 
-	rc = goya_send_cpu_message(hdev, (u32 *) pkt, total_pkt_size,
-			HL_DEVICE_TIMEOUT_USEC, &result);
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) pkt,
+						total_pkt_size,	0, &result);
 
 	if (rc)
 		dev_err(hdev->dev, "failed to unmask IRQ array\n");
@@ -4600,7 +4539,7 @@ static int goya_unmask_irq_arr(struct hl_device *hdev, u32 *irq_arr,
 	return rc;
 }
 
-static int goya_soft_reset_late_init(struct hl_device *hdev)
+static int goya_compute_reset_late_init(struct hl_device *hdev)
 {
 	/*
 	 * Unmask all IRQs since some could have been received
@@ -4612,18 +4551,18 @@ static int goya_soft_reset_late_init(struct hl_device *hdev)
 
 static int goya_unmask_irq(struct hl_device *hdev, u16 event_type)
 {
-	struct armcp_packet pkt;
-	long result;
+	struct cpucp_packet pkt;
+	u64 result;
 	int rc;
 
 	memset(&pkt, 0, sizeof(pkt));
 
-	pkt.ctl = cpu_to_le32(ARMCP_PACKET_UNMASK_RAZWI_IRQ <<
-				ARMCP_PKT_CTL_OPCODE_SHIFT);
+	pkt.ctl = cpu_to_le32(CPUCP_PACKET_UNMASK_RAZWI_IRQ <<
+				CPUCP_PKT_CTL_OPCODE_SHIFT);
 	pkt.value = cpu_to_le64(event_type);
 
-	rc = goya_send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
-			HL_DEVICE_TIMEOUT_USEC, &result);
+	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
+						0, &result);
 
 	if (rc)
 		dev_err(hdev->dev, "failed to unmask RAZWI IRQ %d", event_type);
@@ -4633,20 +4572,39 @@ static int goya_unmask_irq(struct hl_device *hdev, u16 event_type)
 
 static void goya_print_clk_change_info(struct hl_device *hdev, u16 event_type)
 {
+	ktime_t zero_time = ktime_set(0, 0);
+
+	mutex_lock(&hdev->clk_throttling.lock);
+
 	switch (event_type) {
 	case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_S:
+		hdev->clk_throttling.current_reason |= HL_CLK_THROTTLE_POWER;
+		hdev->clk_throttling.aggregated_reason |= HL_CLK_THROTTLE_POWER;
+		hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_POWER].start = ktime_get();
+		hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_POWER].end = zero_time;
 		dev_info_ratelimited(hdev->dev,
 			"Clock throttling due to power consumption\n");
 		break;
+
 	case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_E:
+		hdev->clk_throttling.current_reason &= ~HL_CLK_THROTTLE_POWER;
+		hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_POWER].end = ktime_get();
 		dev_info_ratelimited(hdev->dev,
 			"Power envelop is safe, back to optimal clock\n");
 		break;
+
 	case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_S:
+		hdev->clk_throttling.current_reason |= HL_CLK_THROTTLE_THERMAL;
+		hdev->clk_throttling.aggregated_reason |= HL_CLK_THROTTLE_THERMAL;
+		hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_THERMAL].start = ktime_get();
+		hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_THERMAL].end = zero_time;
 		dev_info_ratelimited(hdev->dev,
 			"Clock throttling due to overheating\n");
 		break;
+
 	case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_E:
+		hdev->clk_throttling.current_reason &= ~HL_CLK_THROTTLE_THERMAL;
+		hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_THERMAL].end = ktime_get();
 		dev_info_ratelimited(hdev->dev,
 			"Thermal envelop is safe, back to optimal clock\n");
 		break;
@@ -4656,6 +4614,8 @@ static void goya_print_clk_change_info(struct hl_device *hdev, u16 event_type)
 			event_type);
 		break;
 	}
+
+	mutex_unlock(&hdev->clk_throttling.lock);
 }
 
 void goya_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_entry)
@@ -4665,6 +4625,12 @@ void goya_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_entry)
 				>> EQ_CTL_EVENT_TYPE_SHIFT);
 	struct goya_device *goya = hdev->asic_specific;
 
+	if (event_type >= GOYA_ASYNC_EVENT_ID_SIZE) {
+		dev_err(hdev->dev, "Event type %u exceeds maximum of %u",
+				event_type, GOYA_ASYNC_EVENT_ID_SIZE - 1);
+		return;
+	}
+
 	goya->events_stat[event_type]++;
 	goya->events_stat_aggregate[event_type]++;
 
@@ -4691,9 +4657,16 @@ void goya_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_entry)
 	case GOYA_ASYNC_EVENT_ID_PLL0 ... GOYA_ASYNC_EVENT_ID_PLL6:
 	case GOYA_ASYNC_EVENT_ID_AXI_ECC:
 	case GOYA_ASYNC_EVENT_ID_L2_RAM_ECC:
+		goya_print_irq_info(hdev, event_type, false);
+		if (hdev->hard_reset_on_fw_events)
+			hl_device_reset(hdev, (HL_DRV_RESET_HARD |
+						HL_DRV_RESET_FW_FATAL_ERR));
+		break;
+
 	case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_05_SW_RESET:
 		goya_print_irq_info(hdev, event_type, false);
-		hl_device_reset(hdev, true, false);
+		if (hdev->hard_reset_on_fw_events)
+			hl_device_reset(hdev, HL_DRV_RESET_HARD);
 		break;
 
 	case GOYA_ASYNC_EVENT_ID_PCIE_DEC:
@@ -4749,6 +4722,15 @@ void goya_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_entry)
 		goya_unmask_irq(hdev, event_type);
 		break;
 
+	case GOYA_ASYNC_EVENT_PKT_QUEUE_OUT_SYNC:
+		goya_print_irq_info(hdev, event_type, false);
+		goya_print_out_of_sync_info(hdev, &eq_entry->pkt_sync_err);
+		if (hdev->hard_reset_on_fw_events)
+			hl_device_reset(hdev, HL_DRV_RESET_HARD);
+		else
+			hl_fw_unmask_irq(hdev, event_type);
+		break;
+
 	default:
 		dev_err(hdev->dev, "Received invalid H/W interrupt %d\n",
 				event_type);
@@ -4781,11 +4763,11 @@ static int goya_memset_device_memory(struct hl_device *hdev, u64 addr, u64 size,
 	lin_dma_pkts_cnt = DIV_ROUND_UP_ULL(size, SZ_2G);
 	cb_size = lin_dma_pkts_cnt * sizeof(struct packet_lin_dma) +
 						sizeof(struct packet_msg_prot);
-	cb = hl_cb_kernel_create(hdev, cb_size);
+	cb = hl_cb_kernel_create(hdev, cb_size, false);
 	if (!cb)
 		return -ENOMEM;
 
-	lin_dma_pkt = (struct packet_lin_dma *) (uintptr_t) cb->kernel_address;
+	lin_dma_pkt = cb->kernel_address;
 
 	do {
 		memset(lin_dma_pkt, 0, sizeof(*lin_dma_pkt));
@@ -4795,7 +4777,7 @@ static int goya_memset_device_memory(struct hl_device *hdev, u64 addr, u64 size,
 				(1 << GOYA_PKT_LIN_DMA_CTL_WO_SHIFT) |
 				(1 << GOYA_PKT_CTL_RB_SHIFT) |
 				(1 << GOYA_PKT_CTL_MB_SHIFT));
-		ctl |= (is_dram ? DMA_HOST_TO_DRAM : DMA_HOST_TO_SRAM) <<
+		ctl |= (is_dram ? HL_DMA_HOST_TO_DRAM : HL_DMA_HOST_TO_SRAM) <<
 				GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
 		lin_dma_pkt->ctl = cpu_to_le32(ctl);
 
@@ -4820,7 +4802,7 @@ static int goya_memset_device_memory(struct hl_device *hdev, u64 addr, u64 size,
 
 	job->id = 0;
 	job->user_cb = cb;
-	job->user_cb->cs_cnt++;
+	atomic_inc(&job->user_cb->cs_cnt);
 	job->user_cb_size = cb_size;
 	job->hw_queue_id = GOYA_QUEUE_ID_DMA_0;
 	job->patched_cb = job->user_cb;
@@ -4832,11 +4814,11 @@ static int goya_memset_device_memory(struct hl_device *hdev, u64 addr, u64 size,
 
 	hl_debugfs_remove_job(hdev, job);
 	kfree(job);
-	cb->cs_cnt--;
+	atomic_dec(&cb->cs_cnt);
 
 release_cb:
 	hl_cb_put(cb);
-	hl_cb_destroy(hdev, &hdev->kernel_cb_mgr, cb->id << PAGE_SHIFT);
+	hl_cb_destroy(&hdev->kernel_mem_mgr, cb->buf->handle);
 
 	return rc;
 }
@@ -4870,8 +4852,6 @@ int goya_context_switch(struct hl_device *hdev, u32 asid)
 
 	WREG32(mmTPC_PLL_CLK_RLX_0, 0x200020);
 
-	goya_mmu_prepare(hdev, asid);
-
 	goya_clear_sm_regs(hdev);
 
 	return 0;
@@ -4915,9 +4895,10 @@ static int goya_mmu_add_mappings_for_device_cpu(struct hl_device *hdev)
 		return 0;
 
 	for (off = 0 ; off < CPU_FW_IMAGE_SIZE ; off += PAGE_SIZE_2MB) {
-		rc = hl_mmu_map(hdev->kernel_ctx, prop->dram_base_address + off,
-				prop->dram_base_address + off, PAGE_SIZE_2MB,
-				(off + PAGE_SIZE_2MB) == CPU_FW_IMAGE_SIZE);
+		rc = hl_mmu_map_page(hdev->kernel_ctx,
+			prop->dram_base_address + off,
+			prop->dram_base_address + off, PAGE_SIZE_2MB,
+			(off + PAGE_SIZE_2MB) == CPU_FW_IMAGE_SIZE);
 		if (rc) {
 			dev_err(hdev->dev, "Map failed for address 0x%llx\n",
 				prop->dram_base_address + off);
@@ -4926,8 +4907,10 @@ static int goya_mmu_add_mappings_for_device_cpu(struct hl_device *hdev)
 	}
 
 	if (!(hdev->cpu_accessible_dma_address & (PAGE_SIZE_2MB - 1))) {
-		rc = hl_mmu_map(hdev->kernel_ctx, VA_CPU_ACCESSIBLE_MEM_ADDR,
-			hdev->cpu_accessible_dma_address, PAGE_SIZE_2MB, true);
+		rc = hl_mmu_map_page(hdev->kernel_ctx,
+			VA_CPU_ACCESSIBLE_MEM_ADDR,
+			hdev->cpu_accessible_dma_address,
+			PAGE_SIZE_2MB, true);
 
 		if (rc) {
 			dev_err(hdev->dev,
@@ -4937,7 +4920,7 @@ static int goya_mmu_add_mappings_for_device_cpu(struct hl_device *hdev)
 		}
 	} else {
 		for (cpu_off = 0 ; cpu_off < SZ_2M ; cpu_off += PAGE_SIZE_4KB) {
-			rc = hl_mmu_map(hdev->kernel_ctx,
+			rc = hl_mmu_map_page(hdev->kernel_ctx,
 				VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off,
 				hdev->cpu_accessible_dma_address + cpu_off,
 				PAGE_SIZE_4KB, true);
@@ -4964,7 +4947,7 @@ static int goya_mmu_add_mappings_for_device_cpu(struct hl_device *hdev)
 
 unmap_cpu:
 	for (; cpu_off >= 0 ; cpu_off -= PAGE_SIZE_4KB)
-		if (hl_mmu_unmap(hdev->kernel_ctx,
+		if (hl_mmu_unmap_page(hdev->kernel_ctx,
 				VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off,
 				PAGE_SIZE_4KB, true))
 			dev_warn_ratelimited(hdev->dev,
@@ -4972,7 +4955,7 @@ unmap_cpu:
 				VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off);
 unmap:
 	for (; off >= 0 ; off -= PAGE_SIZE_2MB)
-		if (hl_mmu_unmap(hdev->kernel_ctx,
+		if (hl_mmu_unmap_page(hdev->kernel_ctx,
 				prop->dram_base_address + off, PAGE_SIZE_2MB,
 				true))
 			dev_warn_ratelimited(hdev->dev,
@@ -4998,13 +4981,14 @@ void goya_mmu_remove_device_cpu_mappings(struct hl_device *hdev)
 	WREG32(mmCPU_IF_AWUSER_OVR_EN, 0);
 
 	if (!(hdev->cpu_accessible_dma_address & (PAGE_SIZE_2MB - 1))) {
-		if (hl_mmu_unmap(hdev->kernel_ctx, VA_CPU_ACCESSIBLE_MEM_ADDR,
+		if (hl_mmu_unmap_page(hdev->kernel_ctx,
+				VA_CPU_ACCESSIBLE_MEM_ADDR,
 				PAGE_SIZE_2MB, true))
 			dev_warn(hdev->dev,
 				"Failed to unmap CPU accessible memory\n");
 	} else {
 		for (cpu_off = 0 ; cpu_off < SZ_2M ; cpu_off += PAGE_SIZE_4KB)
-			if (hl_mmu_unmap(hdev->kernel_ctx,
+			if (hl_mmu_unmap_page(hdev->kernel_ctx,
 					VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off,
 					PAGE_SIZE_4KB,
 					(cpu_off + PAGE_SIZE_4KB) >= SZ_2M))
@@ -5014,7 +4998,7 @@ void goya_mmu_remove_device_cpu_mappings(struct hl_device *hdev)
 	}
 
 	for (off = 0 ; off < CPU_FW_IMAGE_SIZE ; off += PAGE_SIZE_2MB)
-		if (hl_mmu_unmap(hdev->kernel_ctx,
+		if (hl_mmu_unmap_page(hdev->kernel_ctx,
 				prop->dram_base_address + off, PAGE_SIZE_2MB,
 				(off + PAGE_SIZE_2MB) >= CPU_FW_IMAGE_SIZE))
 			dev_warn_ratelimited(hdev->dev,
@@ -5033,7 +5017,7 @@ static void goya_mmu_prepare(struct hl_device *hdev, u32 asid)
 		return;
 
 	if (asid & ~MME_QM_GLBL_SECURE_PROPS_ASID_MASK) {
-		WARN(1, "asid %u is too big\n", asid);
+		dev_crit(hdev->dev, "asid %u is too big\n", asid);
 		return;
 	}
 
@@ -5042,7 +5026,7 @@ static void goya_mmu_prepare(struct hl_device *hdev, u32 asid)
 		goya_mmu_prepare_reg(hdev, goya_mmu_regs[i], asid);
 }
 
-static void goya_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard,
+static int goya_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard,
 					u32 flags)
 {
 	struct goya_device *goya = hdev->asic_specific;
@@ -5050,20 +5034,18 @@ static void goya_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard,
 	int rc;
 
 	if (!(goya->hw_cap_initialized & HW_CAP_MMU) ||
-		hdev->hard_reset_pending)
-		return;
+		hdev->reset_info.hard_reset_pending)
+		return 0;
 
 	/* no need in L1 only invalidation in Goya */
 	if (!is_hard)
-		return;
+		return 0;
 
 	if (hdev->pldm)
 		timeout_usec = GOYA_PLDM_MMU_TIMEOUT_USEC;
 	else
 		timeout_usec = MMU_CONFIG_TIMEOUT_USEC;
 
-	mutex_lock(&hdev->mmu_cache_lock);
-
 	/* L0 & L1 invalidation */
 	WREG32(mmSTLB_INV_ALL_START, 1);
 
@@ -5075,62 +5057,17 @@ static void goya_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard,
 		1000,
 		timeout_usec);
 
-	mutex_unlock(&hdev->mmu_cache_lock);
-
-	if (rc)
-		dev_notice_ratelimited(hdev->dev,
-			"Timeout when waiting for MMU cache invalidation\n");
+	return rc;
 }
 
-static void goya_mmu_invalidate_cache_range(struct hl_device *hdev,
-		bool is_hard, u32 asid, u64 va, u64 size)
+static int goya_mmu_invalidate_cache_range(struct hl_device *hdev,
+						bool is_hard, u32 flags,
+						u32 asid, u64 va, u64 size)
 {
-	struct goya_device *goya = hdev->asic_specific;
-	u32 status, timeout_usec, inv_data, pi;
-	int rc;
-
-	if (!(goya->hw_cap_initialized & HW_CAP_MMU) ||
-		hdev->hard_reset_pending)
-		return;
-
-	/* no need in L1 only invalidation in Goya */
-	if (!is_hard)
-		return;
-
-	if (hdev->pldm)
-		timeout_usec = GOYA_PLDM_MMU_TIMEOUT_USEC;
-	else
-		timeout_usec = MMU_CONFIG_TIMEOUT_USEC;
-
-	mutex_lock(&hdev->mmu_cache_lock);
-
-	/*
-	 * TODO: currently invalidate entire L0 & L1 as in regular hard
-	 * invalidation. Need to apply invalidation of specific cache lines with
-	 * mask of ASID & VA & size.
-	 * Note that L1 with be flushed entirely in any case.
+	/* Treat as invalidate all because there is no range invalidation
+	 * in Goya
 	 */
-
-	/* L0 & L1 invalidation */
-	inv_data = RREG32(mmSTLB_CACHE_INV);
-	/* PI is 8 bit */
-	pi = ((inv_data & STLB_CACHE_INV_PRODUCER_INDEX_MASK) + 1) & 0xFF;
-	WREG32(mmSTLB_CACHE_INV,
-			(inv_data & STLB_CACHE_INV_INDEX_MASK_MASK) | pi);
-
-	rc = hl_poll_timeout(
-		hdev,
-		mmSTLB_INV_CONSUMER_INDEX,
-		status,
-		status == pi,
-		1000,
-		timeout_usec);
-
-	mutex_unlock(&hdev->mmu_cache_lock);
-
-	if (rc)
-		dev_notice_ratelimited(hdev->dev,
-			"Timeout when waiting for MMU cache invalidation\n");
+	return hl_mmu_invalidate_cache(hdev, is_hard, flags);
 }
 
 int goya_send_heartbeat(struct hl_device *hdev)
@@ -5143,7 +5080,7 @@ int goya_send_heartbeat(struct hl_device *hdev)
 	return hl_fw_send_heartbeat(hdev);
 }
 
-int goya_armcp_info_get(struct hl_device *hdev)
+int goya_cpucp_info_get(struct hl_device *hdev)
 {
 	struct goya_device *goya = hdev->asic_specific;
 	struct asic_fixed_properties *prop = &hdev->asic_prop;
@@ -5153,11 +5090,13 @@ int goya_armcp_info_get(struct hl_device *hdev)
 	if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
 		return 0;
 
-	rc = hl_fw_armcp_info_get(hdev);
+	rc = hl_fw_cpucp_handshake(hdev, mmCPU_BOOT_DEV_STS0,
+					mmCPU_BOOT_DEV_STS1, mmCPU_BOOT_ERR0,
+					mmCPU_BOOT_ERR1);
 	if (rc)
 		return rc;
 
-	dram_size = le64_to_cpu(prop->armcp_info.dram_size);
+	dram_size = le64_to_cpu(prop->cpucp_info.dram_size);
 	if (dram_size) {
 		if ((!is_power_of_2(dram_size)) ||
 				(dram_size < DRAM_PHYS_DEFAULT_SIZE)) {
@@ -5171,27 +5110,28 @@ int goya_armcp_info_get(struct hl_device *hdev)
 		prop->dram_end_address = prop->dram_base_address + dram_size;
 	}
 
-	if (!strlen(prop->armcp_info.card_name))
-		strncpy(prop->armcp_info.card_name, GOYA_DEFAULT_CARD_NAME,
+	if (!strlen(prop->cpucp_info.card_name))
+		strscpy_pad(prop->cpucp_info.card_name, GOYA_DEFAULT_CARD_NAME,
 				CARD_NAME_MAX_LEN);
 
 	return 0;
 }
 
-static bool goya_is_device_idle(struct hl_device *hdev, u32 *mask,
-				struct seq_file *s)
+static bool goya_is_device_idle(struct hl_device *hdev, u64 *mask_arr, u8 mask_len,
+				struct engines_data *e)
 {
 	const char *fmt = "%-5d%-9s%#-14x%#-16x%#x\n";
 	const char *dma_fmt = "%-5d%-9s%#-14x%#x\n";
+	unsigned long *mask = (unsigned long *)mask_arr;
 	u32 qm_glbl_sts0, cmdq_glbl_sts0, dma_core_sts0, tpc_cfg_sts,
 		mme_arch_sts;
 	bool is_idle = true, is_eng_idle;
 	u64 offset;
 	int i;
 
-	if (s)
-		seq_puts(s, "\nDMA  is_idle  QM_GLBL_STS0  DMA_CORE_STS0\n"
-				"---  -------  ------------  -------------\n");
+	if (e)
+		hl_engine_data_sprintf(e, "\nDMA  is_idle  QM_GLBL_STS0  DMA_CORE_STS0\n"
+					"---  -------  ------------  -------------\n");
 
 	offset = mmDMA_QM_1_GLBL_STS0 - mmDMA_QM_0_GLBL_STS0;
 
@@ -5202,15 +5142,15 @@ static bool goya_is_device_idle(struct hl_device *hdev, u32 *mask,
 				IS_DMA_IDLE(dma_core_sts0);
 		is_idle &= is_eng_idle;
 
-		if (mask)
-			*mask |= !is_eng_idle << (GOYA_ENGINE_ID_DMA_0 + i);
-		if (s)
-			seq_printf(s, dma_fmt, i, is_eng_idle ? "Y" : "N",
+		if (mask && !is_eng_idle)
+			set_bit(GOYA_ENGINE_ID_DMA_0 + i, mask);
+		if (e)
+			hl_engine_data_sprintf(e, dma_fmt, i, is_eng_idle ? "Y" : "N",
 					qm_glbl_sts0, dma_core_sts0);
 	}
 
-	if (s)
-		seq_puts(s,
+	if (e)
+		hl_engine_data_sprintf(e,
 			"\nTPC  is_idle  QM_GLBL_STS0  CMDQ_GLBL_STS0  CFG_STATUS\n"
 			"---  -------  ------------  --------------  ----------\n");
 
@@ -5225,15 +5165,15 @@ static bool goya_is_device_idle(struct hl_device *hdev, u32 *mask,
 				IS_TPC_IDLE(tpc_cfg_sts);
 		is_idle &= is_eng_idle;
 
-		if (mask)
-			*mask |= !is_eng_idle << (GOYA_ENGINE_ID_TPC_0 + i);
-		if (s)
-			seq_printf(s, fmt, i, is_eng_idle ? "Y" : "N",
+		if (mask && !is_eng_idle)
+			set_bit(GOYA_ENGINE_ID_TPC_0 + i, mask);
+		if (e)
+			hl_engine_data_sprintf(e, fmt, i, is_eng_idle ? "Y" : "N",
 				qm_glbl_sts0, cmdq_glbl_sts0, tpc_cfg_sts);
 	}
 
-	if (s)
-		seq_puts(s,
+	if (e)
+		hl_engine_data_sprintf(e,
 			"\nMME  is_idle  QM_GLBL_STS0  CMDQ_GLBL_STS0  ARCH_STATUS\n"
 			"---  -------  ------------  --------------  -----------\n");
 
@@ -5245,12 +5185,12 @@ static bool goya_is_device_idle(struct hl_device *hdev, u32 *mask,
 			IS_MME_IDLE(mme_arch_sts);
 	is_idle &= is_eng_idle;
 
-	if (mask)
-		*mask |= !is_eng_idle << GOYA_ENGINE_ID_MME_0;
-	if (s) {
-		seq_printf(s, fmt, 0, is_eng_idle ? "Y" : "N", qm_glbl_sts0,
+	if (mask && !is_eng_idle)
+		set_bit(GOYA_ENGINE_ID_MME_0, mask);
+	if (e) {
+		hl_engine_data_sprintf(e, fmt, 0, is_eng_idle ? "Y" : "N", qm_glbl_sts0,
 				cmdq_glbl_sts0, mme_arch_sts);
-		seq_puts(s, "\n");
+		hl_engine_data_sprintf(e, "\n");
 	}
 
 	return is_idle;
@@ -5288,9 +5228,205 @@ static int goya_get_eeprom_data(struct hl_device *hdev, void *data,
 	return hl_fw_get_eeprom_data(hdev, data, max_size);
 }
 
-static enum hl_device_hw_state goya_get_hw_state(struct hl_device *hdev)
+static void goya_cpu_init_scrambler_dram(struct hl_device *hdev)
 {
-	return RREG32(mmHW_STATE);
+
+}
+
+static int goya_ctx_init(struct hl_ctx *ctx)
+{
+	if (ctx->asid != HL_KERNEL_ASID_ID)
+		goya_mmu_prepare(ctx->hdev, ctx->asid);
+
+	return 0;
+}
+
+static int goya_pre_schedule_cs(struct hl_cs *cs)
+{
+	return 0;
+}
+
+u32 goya_get_queue_id_for_cq(struct hl_device *hdev, u32 cq_idx)
+{
+	return cq_idx;
+}
+
+static u32 goya_get_signal_cb_size(struct hl_device *hdev)
+{
+	return 0;
+}
+
+static u32 goya_get_wait_cb_size(struct hl_device *hdev)
+{
+	return 0;
+}
+
+static u32 goya_gen_signal_cb(struct hl_device *hdev, void *data, u16 sob_id,
+				u32 size, bool eb)
+{
+	return 0;
+}
+
+static u32 goya_gen_wait_cb(struct hl_device *hdev,
+		struct hl_gen_wait_properties *prop)
+{
+	return 0;
+}
+
+static void goya_reset_sob(struct hl_device *hdev, void *data)
+{
+
+}
+
+static void goya_reset_sob_group(struct hl_device *hdev, u16 sob_group)
+{
+
+}
+
+u64 goya_get_device_time(struct hl_device *hdev)
+{
+	u64 device_time = ((u64) RREG32(mmPSOC_TIMESTAMP_CNTCVU)) << 32;
+
+	return device_time | RREG32(mmPSOC_TIMESTAMP_CNTCVL);
+}
+
+static int goya_collective_wait_init_cs(struct hl_cs *cs)
+{
+	return 0;
+}
+
+static int goya_collective_wait_create_jobs(struct hl_device *hdev,
+		struct hl_ctx *ctx, struct hl_cs *cs, u32 wait_queue_id,
+		u32 collective_engine_id, u32 encaps_signal_offset)
+{
+	return -EINVAL;
+}
+
+static void goya_ctx_fini(struct hl_ctx *ctx)
+{
+
+}
+
+static int goya_get_hw_block_id(struct hl_device *hdev, u64 block_addr,
+			u32 *block_size, u32 *block_id)
+{
+	return -EPERM;
+}
+
+static int goya_block_mmap(struct hl_device *hdev, struct vm_area_struct *vma,
+				u32 block_id, u32 block_size)
+{
+	return -EPERM;
+}
+
+static void goya_enable_events_from_fw(struct hl_device *hdev)
+{
+	WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
+			GOYA_ASYNC_EVENT_ID_INTS_REGISTER);
+}
+
+static int goya_ack_mmu_page_fault_or_access_error(struct hl_device *hdev, u64 mmu_cap_mask)
+{
+	return -EINVAL;
+}
+
+static int goya_map_pll_idx_to_fw_idx(u32 pll_idx)
+{
+	switch (pll_idx) {
+	case HL_GOYA_CPU_PLL: return CPU_PLL;
+	case HL_GOYA_PCI_PLL: return PCI_PLL;
+	case HL_GOYA_MME_PLL: return MME_PLL;
+	case HL_GOYA_TPC_PLL: return TPC_PLL;
+	case HL_GOYA_IC_PLL: return IC_PLL;
+	case HL_GOYA_MC_PLL: return MC_PLL;
+	case HL_GOYA_EMMC_PLL: return EMMC_PLL;
+	default: return -EINVAL;
+	}
+}
+
+static int goya_gen_sync_to_engine_map(struct hl_device *hdev,
+				struct hl_sync_to_engine_map *map)
+{
+	/* Not implemented */
+	return 0;
+}
+
+static int goya_monitor_valid(struct hl_mon_state_dump *mon)
+{
+	/* Not implemented */
+	return 0;
+}
+
+static int goya_print_single_monitor(char **buf, size_t *size, size_t *offset,
+				struct hl_device *hdev,
+				struct hl_mon_state_dump *mon)
+{
+	/* Not implemented */
+	return 0;
+}
+
+
+static int goya_print_fences_single_engine(
+	struct hl_device *hdev, u64 base_offset, u64 status_base_offset,
+	enum hl_sync_engine_type engine_type, u32 engine_id, char **buf,
+	size_t *size, size_t *offset)
+{
+	/* Not implemented */
+	return 0;
+}
+
+
+static struct hl_state_dump_specs_funcs goya_state_dump_funcs = {
+	.monitor_valid = goya_monitor_valid,
+	.print_single_monitor = goya_print_single_monitor,
+	.gen_sync_to_engine_map = goya_gen_sync_to_engine_map,
+	.print_fences_single_engine = goya_print_fences_single_engine,
+};
+
+static void goya_state_dump_init(struct hl_device *hdev)
+{
+	/* Not implemented */
+	hdev->state_dump_specs.props = goya_state_dump_specs_props;
+	hdev->state_dump_specs.funcs = goya_state_dump_funcs;
+}
+
+static u32 goya_get_sob_addr(struct hl_device *hdev, u32 sob_id)
+{
+	return 0;
+}
+
+static u32 *goya_get_stream_master_qid_arr(void)
+{
+	return NULL;
+}
+
+static int goya_get_monitor_dump(struct hl_device *hdev, void *data)
+{
+	return -EOPNOTSUPP;
+}
+
+static void goya_check_if_razwi_happened(struct hl_device *hdev)
+{
+}
+
+static int goya_scrub_device_dram(struct hl_device *hdev, u64 val)
+{
+	return -EOPNOTSUPP;
+}
+
+static int goya_set_dram_properties(struct hl_device *hdev)
+{
+	return 0;
+}
+
+static int goya_set_binning_masks(struct hl_device *hdev)
+{
+	return 0;
+}
+
+static int goya_send_device_activity(struct hl_device *hdev, bool open)
+{
+	return 0;
 }
 
 static const struct hl_asic_funcs goya_funcs = {
@@ -5305,54 +5441,89 @@ static const struct hl_asic_funcs goya_funcs = {
 	.halt_engines = goya_halt_engines,
 	.suspend = goya_suspend,
 	.resume = goya_resume,
-	.cb_mmap = goya_cb_mmap,
+	.mmap = goya_mmap,
 	.ring_doorbell = goya_ring_doorbell,
 	.pqe_write = goya_pqe_write,
 	.asic_dma_alloc_coherent = goya_dma_alloc_coherent,
 	.asic_dma_free_coherent = goya_dma_free_coherent,
+	.scrub_device_mem = goya_scrub_device_mem,
+	.scrub_device_dram = goya_scrub_device_dram,
 	.get_int_queue_base = goya_get_int_queue_base,
 	.test_queues = goya_test_queues,
 	.asic_dma_pool_zalloc = goya_dma_pool_zalloc,
 	.asic_dma_pool_free = goya_dma_pool_free,
 	.cpu_accessible_dma_pool_alloc = goya_cpu_accessible_dma_pool_alloc,
 	.cpu_accessible_dma_pool_free = goya_cpu_accessible_dma_pool_free,
-	.hl_dma_unmap_sg = goya_dma_unmap_sg,
+	.dma_unmap_sgtable = hl_asic_dma_unmap_sgtable,
 	.cs_parser = goya_cs_parser,
-	.asic_dma_map_sg = goya_dma_map_sg,
-	.get_dma_desc_list_size = goya_get_dma_desc_list_size,
+	.dma_map_sgtable = hl_asic_dma_map_sgtable,
 	.add_end_of_cb_packets = goya_add_end_of_cb_packets,
 	.update_eq_ci = goya_update_eq_ci,
 	.context_switch = goya_context_switch,
 	.restore_phase_topology = goya_restore_phase_topology,
-	.debugfs_read32 = goya_debugfs_read32,
-	.debugfs_write32 = goya_debugfs_write32,
-	.debugfs_read64 = goya_debugfs_read64,
-	.debugfs_write64 = goya_debugfs_write64,
+	.debugfs_read_dma = goya_debugfs_read_dma,
 	.add_device_attr = goya_add_device_attr,
 	.handle_eqe = goya_handle_eqe,
-	.set_pll_profile = goya_set_pll_profile,
 	.get_events_stat = goya_get_events_stat,
 	.read_pte = goya_read_pte,
 	.write_pte = goya_write_pte,
 	.mmu_invalidate_cache = goya_mmu_invalidate_cache,
 	.mmu_invalidate_cache_range = goya_mmu_invalidate_cache_range,
+	.mmu_prefetch_cache_range = NULL,
 	.send_heartbeat = goya_send_heartbeat,
 	.debug_coresight = goya_debug_coresight,
 	.is_device_idle = goya_is_device_idle,
-	.soft_reset_late_init = goya_soft_reset_late_init,
+	.compute_reset_late_init = goya_compute_reset_late_init,
 	.hw_queues_lock = goya_hw_queues_lock,
 	.hw_queues_unlock = goya_hw_queues_unlock,
 	.get_pci_id = goya_get_pci_id,
 	.get_eeprom_data = goya_get_eeprom_data,
+	.get_monitor_dump = goya_get_monitor_dump,
 	.send_cpu_message = goya_send_cpu_message,
-	.get_hw_state = goya_get_hw_state,
 	.pci_bars_map = goya_pci_bars_map,
-	.set_dram_bar_base = goya_set_ddr_bar_base,
 	.init_iatu = goya_init_iatu,
 	.rreg = hl_rreg,
 	.wreg = hl_wreg,
 	.halt_coresight = goya_halt_coresight,
-	.get_clk_rate = goya_get_clk_rate
+	.ctx_init = goya_ctx_init,
+	.ctx_fini = goya_ctx_fini,
+	.pre_schedule_cs = goya_pre_schedule_cs,
+	.get_queue_id_for_cq = goya_get_queue_id_for_cq,
+	.load_firmware_to_device = goya_load_firmware_to_device,
+	.load_boot_fit_to_device = goya_load_boot_fit_to_device,
+	.get_signal_cb_size = goya_get_signal_cb_size,
+	.get_wait_cb_size = goya_get_wait_cb_size,
+	.gen_signal_cb = goya_gen_signal_cb,
+	.gen_wait_cb = goya_gen_wait_cb,
+	.reset_sob = goya_reset_sob,
+	.reset_sob_group = goya_reset_sob_group,
+	.get_device_time = goya_get_device_time,
+	.pb_print_security_errors = NULL,
+	.collective_wait_init_cs = goya_collective_wait_init_cs,
+	.collective_wait_create_jobs = goya_collective_wait_create_jobs,
+	.get_dec_base_addr = NULL,
+	.scramble_addr = hl_mmu_scramble_addr,
+	.descramble_addr = hl_mmu_descramble_addr,
+	.ack_protection_bits_errors = goya_ack_protection_bits_errors,
+	.get_hw_block_id = goya_get_hw_block_id,
+	.hw_block_mmap = goya_block_mmap,
+	.enable_events_from_fw = goya_enable_events_from_fw,
+	.ack_mmu_errors = goya_ack_mmu_page_fault_or_access_error,
+	.map_pll_idx_to_fw_idx = goya_map_pll_idx_to_fw_idx,
+	.init_firmware_preload_params = goya_init_firmware_preload_params,
+	.init_firmware_loader = goya_init_firmware_loader,
+	.init_cpu_scrambler_dram = goya_cpu_init_scrambler_dram,
+	.state_dump_init = goya_state_dump_init,
+	.get_sob_addr = &goya_get_sob_addr,
+	.set_pci_memory_regions = goya_set_pci_memory_regions,
+	.get_stream_master_qid_arr = goya_get_stream_master_qid_arr,
+	.check_if_razwi_happened = goya_check_if_razwi_happened,
+	.mmu_get_real_page_size = hl_mmu_get_real_page_size,
+	.access_dev_mem = hl_access_dev_mem,
+	.set_dram_bar_base = goya_set_ddr_bar_base,
+	.send_device_activity = goya_send_device_activity,
+	.set_dram_properties = goya_set_dram_properties,
+	.set_binning_masks = goya_set_binning_masks,
 };
 
 /*
diff --git a/drivers/misc/habanalabs/goya/goyaP.h b/drivers/accel/habanalabs/goya/goyaP.h
index c3230cb6e25c..194c2ae157cd 100644
--- a/drivers/misc/habanalabs/goya/goyaP.h
+++ b/drivers/accel/habanalabs/goya/goyaP.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0
  *
- * Copyright 2016-2019 HabanaLabs, Ltd.
+ * Copyright 2016-2022 HabanaLabs, Ltd.
  * All Rights Reserved.
  *
  */
@@ -8,13 +8,13 @@
 #ifndef GOYAP_H_
 #define GOYAP_H_
 
-#include <uapi/misc/habanalabs.h>
-#include "habanalabs.h"
-#include "include/hl_boot_if.h"
-#include "include/goya/goya_packets.h"
-#include "include/goya/goya.h"
-#include "include/goya/goya_async_events.h"
-#include "include/goya/goya_fw_if.h"
+#include <uapi/drm/habanalabs_accel.h>
+#include <linux/habanalabs/hl_boot_if.h>
+#include "../common/habanalabs.h"
+#include "../include/goya/goya_packets.h"
+#include "../include/goya/goya.h"
+#include "../include/goya/goya_async_events.h"
+#include "../include/goya/goya_fw_if.h"
 
 #define NUMBER_OF_CMPLT_QUEUES		5
 #define NUMBER_OF_EXT_HW_QUEUES		5
@@ -31,10 +31,6 @@
  */
 #define NUMBER_OF_INTERRUPTS		(NUMBER_OF_CMPLT_QUEUES + 1)
 
-#if (NUMBER_OF_HW_QUEUES >= HL_MAX_QUEUES)
-#error "Number of H/W queues must be smaller than HL_MAX_QUEUES"
-#endif
-
 #if (NUMBER_OF_INTERRUPTS > GOYA_MSIX_ENTRIES)
 #error "Number of MSIX interrupts must be smaller or equal to GOYA_MSIX_ENTRIES"
 #endif
@@ -45,7 +41,7 @@
 
 #define CORESIGHT_TIMEOUT_USEC		100000		/* 100 ms */
 
-#define GOYA_CPU_TIMEOUT_USEC		10000000	/* 10s */
+#define GOYA_CPU_TIMEOUT_USEC		15000000	/* 15s */
 
 #define TPC_ENABLED_MASK		0xFF
 
@@ -53,10 +49,18 @@
 
 #define MAX_POWER_DEFAULT		200000		/* 200W */
 
+#define DC_POWER_DEFAULT		20000		/* 20W */
+
 #define DRAM_PHYS_DEFAULT_SIZE		0x100000000ull	/* 4GB */
 
 #define GOYA_DEFAULT_CARD_NAME		"HL1000"
 
+#define GOYA_MAX_PENDING_CS		64
+
+#if !IS_MAX_PENDING_CS_VALID(GOYA_MAX_PENDING_CS)
+#error "GOYA_MAX_PENDING_CS must be power of 2 and greater than 1"
+#endif
+
 /* DRAM Memory Map */
 
 #define CPU_FW_IMAGE_SIZE		0x10000000	/* 256MB */
@@ -149,14 +153,15 @@
 #define HW_CAP_GOLDEN		0x00000400
 #define HW_CAP_TPC		0x00000800
 
-enum goya_fw_component {
-	FW_COMP_UBOOT,
-	FW_COMP_PREBOOT
+struct goya_work_freq {
+	struct hl_device *hdev;
+	struct delayed_work work_freq;
 };
 
 struct goya_device {
 	/* TODO: remove hw_queues_lock after moving to scheduler code */
 	spinlock_t	hw_queues_lock;
+	struct goya_work_freq	*goya_work;
 
 	u64		mme_clk;
 	u64		tpc_clk;
@@ -167,15 +172,19 @@ struct goya_device {
 	u32		events_stat_aggregate[GOYA_ASYNC_EVENT_ID_SIZE];
 	u32		hw_cap_initialized;
 	u8		device_cpu_mmu_mappings_done;
+
+	enum hl_pll_frequency		curr_pll_profile;
+	enum hl_pm_mng_profile		pm_mng_profile;
 };
 
-void goya_get_fixed_properties(struct hl_device *hdev);
+int goya_set_fixed_properties(struct hl_device *hdev);
 int goya_mmu_init(struct hl_device *hdev);
 void goya_init_dma_qmans(struct hl_device *hdev);
 void goya_init_mme_qmans(struct hl_device *hdev);
 void goya_init_tpc_qmans(struct hl_device *hdev);
 int goya_init_cpu_queues(struct hl_device *hdev);
 void goya_init_security(struct hl_device *hdev);
+void goya_ack_protection_bits_errors(struct hl_device *hdev);
 int goya_late_init(struct hl_device *hdev);
 void goya_late_fini(struct hl_device *hdev);
 
@@ -195,7 +204,7 @@ int goya_test_queue(struct hl_device *hdev, u32 hw_queue_id);
 int goya_test_queues(struct hl_device *hdev);
 int goya_test_cpu_queue(struct hl_device *hdev);
 int goya_send_cpu_message(struct hl_device *hdev, u32 *msg, u16 len,
-				u32 timeout, long *result);
+				u32 timeout, u64 *result);
 
 long goya_get_temperature(struct hl_device *hdev, int sensor_index, u32 attr);
 long goya_get_voltage(struct hl_device *hdev, int sensor_index, u32 attr);
@@ -208,11 +217,11 @@ u64 goya_get_max_power(struct hl_device *hdev);
 void goya_set_max_power(struct hl_device *hdev, u64 value);
 
 void goya_set_pll_profile(struct hl_device *hdev, enum hl_pll_frequency freq);
-void goya_add_device_attr(struct hl_device *hdev,
-			struct attribute_group *dev_attr_grp);
-int goya_armcp_info_get(struct hl_device *hdev);
-int goya_debug_coresight(struct hl_device *hdev, void *data);
-void goya_halt_coresight(struct hl_device *hdev);
+void goya_add_device_attr(struct hl_device *hdev, struct attribute_group *dev_clk_attr_grp,
+				struct attribute_group *dev_vrm_attr_grp);
+int goya_cpucp_info_get(struct hl_device *hdev);
+int goya_debug_coresight(struct hl_device *hdev, struct hl_ctx *ctx, void *data);
+void goya_halt_coresight(struct hl_device *hdev, struct hl_ctx *ctx);
 
 int goya_suspend(struct hl_device *hdev);
 int goya_resume(struct hl_device *hdev);
@@ -220,9 +229,11 @@ int goya_resume(struct hl_device *hdev);
 void goya_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_entry);
 void *goya_get_events_stat(struct hl_device *hdev, bool aggregate, u32 *size);
 
-void goya_add_end_of_cb_packets(struct hl_device *hdev, u64 kernel_address,
-				u32 len, u64 cq_addr, u32 cq_val, u32 msix_vec);
+void goya_add_end_of_cb_packets(struct hl_device *hdev, void *kernel_address,
+				u32 len, u32 original_len, u64 cq_addr, u32 cq_val,
+				u32 msix_vec, bool eb);
 int goya_cs_parser(struct hl_device *hdev, struct hl_cs_parser *parser);
+int goya_scrub_device_mem(struct hl_device *hdev);
 void *goya_get_int_queue_base(struct hl_device *hdev, u32 queue_id,
 				dma_addr_t *dma_handle,	u16 *queue_len);
 u32 goya_get_dma_desc_list_size(struct hl_device *hdev, struct sg_table *sgt);
@@ -233,6 +244,8 @@ void goya_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size,
 					void *vaddr);
 void goya_mmu_remove_device_cpu_mappings(struct hl_device *hdev);
 
-int goya_get_clk_rate(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk);
+u32 goya_get_queue_id_for_cq(struct hl_device *hdev, u32 cq_idx);
+u64 goya_get_device_time(struct hl_device *hdev);
+int goya_set_frequency(struct hl_device *hdev, enum hl_pll_frequency freq);
 
 #endif /* GOYAP_H_ */
diff --git a/drivers/misc/habanalabs/goya/goya_coresight.c b/drivers/accel/habanalabs/goya/goya_coresight.c
index a1bc930d904f..3827ea4c02f7 100644
--- a/drivers/misc/habanalabs/goya/goya_coresight.c
+++ b/drivers/accel/habanalabs/goya/goya_coresight.c
@@ -6,13 +6,11 @@
  */
 
 #include "goyaP.h"
-#include "include/goya/goya_coresight.h"
-#include "include/goya/asic_reg/goya_regs.h"
-#include "include/goya/asic_reg/goya_masks.h"
+#include "../include/goya/goya_coresight.h"
+#include "../include/goya/asic_reg/goya_regs.h"
+#include "../include/goya/asic_reg/goya_masks.h"
 
-#include <uapi/misc/habanalabs.h>
-
-#include <linux/coresight.h>
+#include <uapi/drm/habanalabs_accel.h>
 
 #define GOYA_PLDM_CORESIGHT_TIMEOUT_USEC	(CORESIGHT_TIMEOUT_USEC * 100)
 
@@ -232,6 +230,7 @@ static int goya_config_stm(struct hl_device *hdev,
 {
 	struct hl_debug_params_stm *input;
 	u64 base_reg;
+	u32 frequency;
 	int rc;
 
 	if (params->reg_idx >= ARRAY_SIZE(debug_stm_regs)) {
@@ -264,9 +263,12 @@ static int goya_config_stm(struct hl_device *hdev,
 		WREG32(base_reg + 0xE20, 0xFFFFFFFF);
 		WREG32(base_reg + 0xEF4, input->id);
 		WREG32(base_reg + 0xDF4, 0x80);
-		WREG32(base_reg + 0xE8C, input->frequency);
+		frequency = hdev->asic_prop.psoc_timestamp_frequency;
+		if (frequency == 0)
+			frequency = input->frequency;
+		WREG32(base_reg + 0xE8C, frequency);
 		WREG32(base_reg + 0xE90, 0x7FF);
-		WREG32(base_reg + 0xE80, 0x7 | (input->id << 16));
+		WREG32(base_reg + 0xE80, 0x27 | (input->id << 16));
 	} else {
 		WREG32(base_reg + 0xE80, 4);
 		WREG32(base_reg + 0xD64, 0);
@@ -313,6 +315,11 @@ static int goya_config_etf(struct hl_device *hdev,
 
 	WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);
 
+	val = RREG32(base_reg + 0x20);
+
+	if ((!params->enable && val == 0x0) || (params->enable && val != 0x0))
+		return 0;
+
 	val = RREG32(base_reg + 0x304);
 	val |= 0x1000;
 	WREG32(base_reg + 0x304, val);
@@ -358,19 +365,20 @@ static int goya_config_etf(struct hl_device *hdev,
 }
 
 static int goya_etr_validate_address(struct hl_device *hdev, u64 addr,
-		u32 size)
+		u64 size)
 {
 	struct asic_fixed_properties *prop = &hdev->asic_prop;
 	u64 range_start, range_end;
 
-	if (hdev->mmu_enable) {
-		range_start = prop->dmmu.start_addr;
-		range_end = prop->dmmu.end_addr;
-	} else {
-		range_start = prop->dram_user_base_address;
-		range_end = prop->dram_end_address;
+	if (addr > (addr + size)) {
+		dev_err(hdev->dev,
+			"ETR buffer size %llu overflow\n", size);
+		return false;
 	}
 
+	range_start = prop->dmmu.start_addr;
+	range_end = prop->dmmu.end_addr;
+
 	return hl_mem_area_inside_range(addr, size, range_start, range_end);
 }
 
@@ -383,6 +391,11 @@ static int goya_config_etr(struct hl_device *hdev,
 
 	WREG32(mmPSOC_ETR_LAR, CORESIGHT_UNLOCK);
 
+	val = RREG32(mmPSOC_ETR_CTL);
+
+	if ((!params->enable && val == 0x0) || (params->enable && val != 0x0))
+		return 0;
+
 	val = RREG32(mmPSOC_ETR_FFCR);
 	val |= 0x1000;
 	WREG32(mmPSOC_ETR_FFCR, val);
@@ -426,8 +439,15 @@ static int goya_config_etr(struct hl_device *hdev,
 		WREG32(mmPSOC_ETR_BUFWM, 0x3FFC);
 		WREG32(mmPSOC_ETR_RSZ, input->buffer_size);
 		WREG32(mmPSOC_ETR_MODE, input->sink_mode);
-		WREG32(mmPSOC_ETR_AXICTL,
-				0x700 | PSOC_ETR_AXICTL_PROTCTRLBIT1_SHIFT);
+		if (!hdev->asic_prop.fw_security_enabled) {
+			/* make ETR not privileged */
+			val = FIELD_PREP(PSOC_ETR_AXICTL_PROTCTRLBIT0_MASK, 0);
+			/* make ETR non-secured (inverted logic) */
+			val |= FIELD_PREP(PSOC_ETR_AXICTL_PROTCTRLBIT1_MASK, 1);
+			/* burst size 8 */
+			val |= FIELD_PREP(PSOC_ETR_AXICTL_WRBURSTLEN_MASK, 7);
+			WREG32(mmPSOC_ETR_AXICTL, val);
+		}
 		WREG32(mmPSOC_ETR_DBALO,
 				lower_32_bits(input->buffer_address));
 		WREG32(mmPSOC_ETR_DBAHI,
@@ -556,7 +576,6 @@ static int goya_config_spmu(struct hl_device *hdev,
 		struct hl_debug_params *params)
 {
 	u64 base_reg;
-	struct hl_debug_params_spmu *input = params->input;
 	u64 *output;
 	u32 output_arr_len;
 	u32 events_num;
@@ -572,7 +591,7 @@ static int goya_config_spmu(struct hl_device *hdev,
 	base_reg = debug_spmu_regs[params->reg_idx] - CFG_BASE;
 
 	if (params->enable) {
-		input = params->input;
+		struct hl_debug_params_spmu *input = params->input;
 
 		if (!input)
 			return -EINVAL;
@@ -637,10 +656,9 @@ static int goya_config_spmu(struct hl_device *hdev,
 	return 0;
 }
 
-int goya_debug_coresight(struct hl_device *hdev, void *data)
+int goya_debug_coresight(struct hl_device *hdev, struct hl_ctx *ctx, void *data)
 {
 	struct hl_debug_params *params = data;
-	u32 val;
 	int rc = 0;
 
 	switch (params->op) {
@@ -672,12 +690,12 @@ int goya_debug_coresight(struct hl_device *hdev, void *data)
 	}
 
 	/* Perform read from the device to flush all configuration */
-	val = RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG);
+	RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG);
 
 	return rc;
 }
 
-void goya_halt_coresight(struct hl_device *hdev)
+void goya_halt_coresight(struct hl_device *hdev, struct hl_ctx *ctx)
 {
 	struct hl_debug_params params = {};
 	int i, rc;
diff --git a/drivers/accel/habanalabs/goya/goya_hwmgr.c b/drivers/accel/habanalabs/goya/goya_hwmgr.c
new file mode 100644
index 000000000000..b595721751c1
--- /dev/null
+++ b/drivers/accel/habanalabs/goya/goya_hwmgr.c
@@ -0,0 +1,387 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Copyright 2016-2022 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ */
+
+#include "goyaP.h"
+
+void goya_set_pll_profile(struct hl_device *hdev, enum hl_pll_frequency freq)
+{
+	struct goya_device *goya = hdev->asic_specific;
+
+	if (!hdev->pdev)
+		return;
+
+	switch (freq) {
+	case PLL_HIGH:
+		hl_fw_set_frequency(hdev, HL_GOYA_MME_PLL, hdev->high_pll);
+		hl_fw_set_frequency(hdev, HL_GOYA_TPC_PLL, hdev->high_pll);
+		hl_fw_set_frequency(hdev, HL_GOYA_IC_PLL, hdev->high_pll);
+		break;
+	case PLL_LOW:
+		hl_fw_set_frequency(hdev, HL_GOYA_MME_PLL, GOYA_PLL_FREQ_LOW);
+		hl_fw_set_frequency(hdev, HL_GOYA_TPC_PLL, GOYA_PLL_FREQ_LOW);
+		hl_fw_set_frequency(hdev, HL_GOYA_IC_PLL, GOYA_PLL_FREQ_LOW);
+		break;
+	case PLL_LAST:
+		hl_fw_set_frequency(hdev, HL_GOYA_MME_PLL, goya->mme_clk);
+		hl_fw_set_frequency(hdev, HL_GOYA_TPC_PLL, goya->tpc_clk);
+		hl_fw_set_frequency(hdev, HL_GOYA_IC_PLL, goya->ic_clk);
+		break;
+	default:
+		dev_err(hdev->dev, "unknown frequency setting\n");
+	}
+}
+
+static ssize_t mme_clk_show(struct device *dev, struct device_attribute *attr,
+				char *buf)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+	long value;
+
+	if (!hl_device_operational(hdev, NULL))
+		return -ENODEV;
+
+	value = hl_fw_get_frequency(hdev, HL_GOYA_MME_PLL, false);
+
+	if (value < 0)
+		return value;
+
+	return sprintf(buf, "%lu\n", value);
+}
+
+static ssize_t mme_clk_store(struct device *dev, struct device_attribute *attr,
+				const char *buf, size_t count)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+	struct goya_device *goya = hdev->asic_specific;
+	int rc;
+	long value;
+
+	if (!hl_device_operational(hdev, NULL)) {
+		count = -ENODEV;
+		goto fail;
+	}
+
+	if (goya->pm_mng_profile == PM_AUTO) {
+		count = -EPERM;
+		goto fail;
+	}
+
+	rc = kstrtoul(buf, 0, &value);
+
+	if (rc) {
+		count = -EINVAL;
+		goto fail;
+	}
+
+	hl_fw_set_frequency(hdev, HL_GOYA_MME_PLL, value);
+	goya->mme_clk = value;
+
+fail:
+	return count;
+}
+
+static ssize_t tpc_clk_show(struct device *dev, struct device_attribute *attr,
+				char *buf)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+	long value;
+
+	if (!hl_device_operational(hdev, NULL))
+		return -ENODEV;
+
+	value = hl_fw_get_frequency(hdev, HL_GOYA_TPC_PLL, false);
+
+	if (value < 0)
+		return value;
+
+	return sprintf(buf, "%lu\n", value);
+}
+
+static ssize_t tpc_clk_store(struct device *dev, struct device_attribute *attr,
+				const char *buf, size_t count)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+	struct goya_device *goya = hdev->asic_specific;
+	int rc;
+	long value;
+
+	if (!hl_device_operational(hdev, NULL)) {
+		count = -ENODEV;
+		goto fail;
+	}
+
+	if (goya->pm_mng_profile == PM_AUTO) {
+		count = -EPERM;
+		goto fail;
+	}
+
+	rc = kstrtoul(buf, 0, &value);
+
+	if (rc) {
+		count = -EINVAL;
+		goto fail;
+	}
+
+	hl_fw_set_frequency(hdev, HL_GOYA_TPC_PLL, value);
+	goya->tpc_clk = value;
+
+fail:
+	return count;
+}
+
+static ssize_t ic_clk_show(struct device *dev, struct device_attribute *attr,
+				char *buf)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+	long value;
+
+	if (!hl_device_operational(hdev, NULL))
+		return -ENODEV;
+
+	value = hl_fw_get_frequency(hdev, HL_GOYA_IC_PLL, false);
+
+	if (value < 0)
+		return value;
+
+	return sprintf(buf, "%lu\n", value);
+}
+
+static ssize_t ic_clk_store(struct device *dev, struct device_attribute *attr,
+				const char *buf, size_t count)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+	struct goya_device *goya = hdev->asic_specific;
+	int rc;
+	long value;
+
+	if (!hl_device_operational(hdev, NULL)) {
+		count = -ENODEV;
+		goto fail;
+	}
+
+	if (goya->pm_mng_profile == PM_AUTO) {
+		count = -EPERM;
+		goto fail;
+	}
+
+	rc = kstrtoul(buf, 0, &value);
+
+	if (rc) {
+		count = -EINVAL;
+		goto fail;
+	}
+
+	hl_fw_set_frequency(hdev, HL_GOYA_IC_PLL, value);
+	goya->ic_clk = value;
+
+fail:
+	return count;
+}
+
+static ssize_t mme_clk_curr_show(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+	long value;
+
+	if (!hl_device_operational(hdev, NULL))
+		return -ENODEV;
+
+	value = hl_fw_get_frequency(hdev, HL_GOYA_MME_PLL, true);
+
+	if (value < 0)
+		return value;
+
+	return sprintf(buf, "%lu\n", value);
+}
+
+static ssize_t tpc_clk_curr_show(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+	long value;
+
+	if (!hl_device_operational(hdev, NULL))
+		return -ENODEV;
+
+	value = hl_fw_get_frequency(hdev, HL_GOYA_TPC_PLL, true);
+
+	if (value < 0)
+		return value;
+
+	return sprintf(buf, "%lu\n", value);
+}
+
+static ssize_t ic_clk_curr_show(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+	long value;
+
+	if (!hl_device_operational(hdev, NULL))
+		return -ENODEV;
+
+	value = hl_fw_get_frequency(hdev, HL_GOYA_IC_PLL, true);
+
+	if (value < 0)
+		return value;
+
+	return sprintf(buf, "%lu\n", value);
+}
+
+static ssize_t pm_mng_profile_show(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+	struct goya_device *goya = hdev->asic_specific;
+
+	if (!hl_device_operational(hdev, NULL))
+		return -ENODEV;
+
+	return sprintf(buf, "%s\n",
+			(goya->pm_mng_profile == PM_AUTO) ? "auto" :
+			(goya->pm_mng_profile == PM_MANUAL) ? "manual" :
+			"unknown");
+}
+
+static ssize_t pm_mng_profile_store(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t count)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+	struct goya_device *goya = hdev->asic_specific;
+
+	if (!hl_device_operational(hdev, NULL)) {
+		count = -ENODEV;
+		goto out;
+	}
+
+	mutex_lock(&hdev->fpriv_list_lock);
+
+	if (hdev->is_compute_ctx_active) {
+		dev_err(hdev->dev,
+			"Can't change PM profile while compute context is opened on the device\n");
+		count = -EPERM;
+		goto unlock_mutex;
+	}
+
+	if (strncmp("auto", buf, strlen("auto")) == 0) {
+		/* Make sure we are in LOW PLL when changing modes */
+		if (goya->pm_mng_profile == PM_MANUAL) {
+			goya->curr_pll_profile = PLL_HIGH;
+			goya->pm_mng_profile = PM_AUTO;
+			goya_set_frequency(hdev, PLL_LOW);
+		}
+	} else if (strncmp("manual", buf, strlen("manual")) == 0) {
+		if (goya->pm_mng_profile == PM_AUTO) {
+			/* Must release the lock because the work thread also
+			 * takes this lock. But before we release it, set
+			 * the mode to manual so nothing will change if a user
+			 * suddenly opens the device
+			 */
+			goya->pm_mng_profile = PM_MANUAL;
+
+			mutex_unlock(&hdev->fpriv_list_lock);
+
+			/* Flush the current work so we can return to the user
+			 * knowing that he is the only one changing frequencies
+			 */
+			if (goya->goya_work)
+				flush_delayed_work(&goya->goya_work->work_freq);
+
+			return count;
+		}
+	} else {
+		dev_err(hdev->dev, "value should be auto or manual\n");
+		count = -EINVAL;
+	}
+
+unlock_mutex:
+	mutex_unlock(&hdev->fpriv_list_lock);
+out:
+	return count;
+}
+
+static ssize_t high_pll_show(struct device *dev, struct device_attribute *attr,
+				char *buf)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+
+	if (!hl_device_operational(hdev, NULL))
+		return -ENODEV;
+
+	return sprintf(buf, "%u\n", hdev->high_pll);
+}
+
+static ssize_t high_pll_store(struct device *dev, struct device_attribute *attr,
+				const char *buf, size_t count)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+	long value;
+	int rc;
+
+	if (!hl_device_operational(hdev, NULL)) {
+		count = -ENODEV;
+		goto out;
+	}
+
+	rc = kstrtoul(buf, 0, &value);
+
+	if (rc) {
+		count = -EINVAL;
+		goto out;
+	}
+
+	hdev->high_pll = value;
+
+out:
+	return count;
+}
+
+static DEVICE_ATTR_RW(high_pll);
+static DEVICE_ATTR_RW(ic_clk);
+static DEVICE_ATTR_RO(ic_clk_curr);
+static DEVICE_ATTR_RW(mme_clk);
+static DEVICE_ATTR_RO(mme_clk_curr);
+static DEVICE_ATTR_RW(pm_mng_profile);
+static DEVICE_ATTR_RW(tpc_clk);
+static DEVICE_ATTR_RO(tpc_clk_curr);
+
+static struct attribute *goya_clk_dev_attrs[] = {
+	&dev_attr_high_pll.attr,
+	&dev_attr_ic_clk.attr,
+	&dev_attr_ic_clk_curr.attr,
+	&dev_attr_mme_clk.attr,
+	&dev_attr_mme_clk_curr.attr,
+	&dev_attr_pm_mng_profile.attr,
+	&dev_attr_tpc_clk.attr,
+	&dev_attr_tpc_clk_curr.attr,
+	NULL,
+};
+
+static ssize_t infineon_ver_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+	struct hl_device *hdev = dev_get_drvdata(dev);
+	struct cpucp_info *cpucp_info;
+
+	cpucp_info = &hdev->asic_prop.cpucp_info;
+
+	return sprintf(buf, "%#04x\n", le32_to_cpu(cpucp_info->infineon_version));
+}
+
+static DEVICE_ATTR_RO(infineon_ver);
+
+static struct attribute *goya_vrm_dev_attrs[] = {
+	&dev_attr_infineon_ver.attr,
+	NULL,
+};
+
+void goya_add_device_attr(struct hl_device *hdev, struct attribute_group *dev_clk_attr_grp,
+				struct attribute_group *dev_vrm_attr_grp)
+{
+	dev_clk_attr_grp->attrs = goya_clk_dev_attrs;
+	dev_vrm_attr_grp->attrs = goya_vrm_dev_attrs;
+}
diff --git a/drivers/misc/habanalabs/goya/goya_security.c b/drivers/accel/habanalabs/goya/goya_security.c
index d6ec12b3e692..14c3bae3ccdc 100644
--- a/drivers/misc/habanalabs/goya/goya_security.c
+++ b/drivers/accel/habanalabs/goya/goya_security.c
@@ -6,7 +6,7 @@
  */
 
 #include "goyaP.h"
-#include "include/goya/asic_reg/goya_regs.h"
+#include "../include/goya/asic_reg/goya_regs.h"
 
 /*
  * goya_set_block_as_protected - set the given block as protected
@@ -683,7 +683,6 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev)
 	mask = 1 << ((mmTPC0_CFG_SEMAPHORE & 0x7F) >> 2);
 	mask |= 1 << ((mmTPC0_CFG_VFLAGS & 0x7F) >> 2);
 	mask |= 1 << ((mmTPC0_CFG_SFLAGS & 0x7F) >> 2);
-	mask |= 1 << ((mmTPC0_CFG_LFSR_POLYNOM & 0x7F) >> 2);
 	mask |= 1 << ((mmTPC0_CFG_STATUS & 0x7F) >> 2);
 
 	WREG32(pb_addr + word_offset, ~mask);
@@ -695,7 +694,6 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev)
 	mask |= 1 << ((mmTPC0_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2);
 	mask |= 1 << ((mmTPC0_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2);
 	mask |= 1 << ((mmTPC0_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2);
-	mask |= 1 << ((mmTPC0_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2);
 	mask |= 1 << ((mmTPC0_CFG_TPC_STALL & 0x7F) >> 2);
 	mask |= 1 << ((mmTPC0_CFG_MSS_CONFIG & 0x7F) >> 2);
 	mask |= 1 << ((mmTPC0_CFG_TPC_INTR_CAUSE & 0x7F) >> 2);
@@ -875,6 +873,16 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev)
 	goya_pb_set_block(hdev, mmTPC1_RD_REGULATOR_BASE);
 	goya_pb_set_block(hdev, mmTPC1_WR_REGULATOR_BASE);
 
+	pb_addr = (mmTPC1_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC1_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2;
+
+	mask = 1 << ((mmTPC1_CFG_SEMAPHORE & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC1_CFG_VFLAGS & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC1_CFG_SFLAGS & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC1_CFG_STATUS & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
 	pb_addr = (mmTPC1_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS;
 	word_offset = ((mmTPC1_CFG_CFG_BASE_ADDRESS_HIGH &
 			PROT_BITS_OFFS) >> 7) << 2;
@@ -882,6 +890,10 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev)
 	mask |= 1 << ((mmTPC1_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2);
 	mask |= 1 << ((mmTPC1_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2);
 	mask |= 1 << ((mmTPC1_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC1_CFG_TPC_STALL & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC1_CFG_MSS_CONFIG & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC1_CFG_TPC_INTR_CAUSE & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC1_CFG_TPC_INTR_MASK & 0x7F) >> 2);
 
 	WREG32(pb_addr + word_offset, ~mask);
 
@@ -1057,6 +1069,16 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev)
 	goya_pb_set_block(hdev, mmTPC2_RD_REGULATOR_BASE);
 	goya_pb_set_block(hdev, mmTPC2_WR_REGULATOR_BASE);
 
+	pb_addr = (mmTPC2_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC2_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2;
+
+	mask = 1 << ((mmTPC2_CFG_SEMAPHORE & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC2_CFG_VFLAGS & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC2_CFG_SFLAGS & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC2_CFG_STATUS & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
 	pb_addr = (mmTPC2_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS;
 	word_offset = ((mmTPC2_CFG_CFG_BASE_ADDRESS_HIGH &
 			PROT_BITS_OFFS) >> 7) << 2;
@@ -1064,6 +1086,10 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev)
 	mask |= 1 << ((mmTPC2_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2);
 	mask |= 1 << ((mmTPC2_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2);
 	mask |= 1 << ((mmTPC2_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC2_CFG_TPC_STALL & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC2_CFG_MSS_CONFIG & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC2_CFG_TPC_INTR_CAUSE & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC2_CFG_TPC_INTR_MASK & 0x7F) >> 2);
 
 	WREG32(pb_addr + word_offset, ~mask);
 
@@ -1239,6 +1265,16 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev)
 	goya_pb_set_block(hdev, mmTPC3_RD_REGULATOR_BASE);
 	goya_pb_set_block(hdev, mmTPC3_WR_REGULATOR_BASE);
 
+	pb_addr = (mmTPC3_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC3_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2;
+
+	mask = 1 << ((mmTPC3_CFG_SEMAPHORE & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC3_CFG_VFLAGS & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC3_CFG_SFLAGS & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC3_CFG_STATUS & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
 	pb_addr = (mmTPC3_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS;
 	word_offset = ((mmTPC3_CFG_CFG_BASE_ADDRESS_HIGH
 			& PROT_BITS_OFFS) >> 7) << 2;
@@ -1246,6 +1282,10 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev)
 	mask |= 1 << ((mmTPC3_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2);
 	mask |= 1 << ((mmTPC3_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2);
 	mask |= 1 << ((mmTPC3_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC3_CFG_TPC_STALL & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC3_CFG_MSS_CONFIG & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC3_CFG_TPC_INTR_CAUSE & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC3_CFG_TPC_INTR_MASK & 0x7F) >> 2);
 
 	WREG32(pb_addr + word_offset, ~mask);
 
@@ -1421,6 +1461,16 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev)
 	goya_pb_set_block(hdev, mmTPC4_RD_REGULATOR_BASE);
 	goya_pb_set_block(hdev, mmTPC4_WR_REGULATOR_BASE);
 
+	pb_addr = (mmTPC4_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC4_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2;
+
+	mask = 1 << ((mmTPC4_CFG_SEMAPHORE & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC4_CFG_VFLAGS & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC4_CFG_SFLAGS & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC4_CFG_STATUS & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
 	pb_addr = (mmTPC4_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS;
 	word_offset = ((mmTPC4_CFG_CFG_BASE_ADDRESS_HIGH &
 			PROT_BITS_OFFS) >> 7) << 2;
@@ -1428,6 +1478,10 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev)
 	mask |= 1 << ((mmTPC4_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2);
 	mask |= 1 << ((mmTPC4_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2);
 	mask |= 1 << ((mmTPC4_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC4_CFG_TPC_STALL & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC4_CFG_MSS_CONFIG & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC4_CFG_TPC_INTR_CAUSE & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC4_CFG_TPC_INTR_MASK & 0x7F) >> 2);
 
 	WREG32(pb_addr + word_offset, ~mask);
 
@@ -1603,6 +1657,16 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev)
 	goya_pb_set_block(hdev, mmTPC5_RD_REGULATOR_BASE);
 	goya_pb_set_block(hdev, mmTPC5_WR_REGULATOR_BASE);
 
+	pb_addr = (mmTPC5_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC5_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2;
+
+	mask = 1 << ((mmTPC5_CFG_SEMAPHORE & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC5_CFG_VFLAGS & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC5_CFG_SFLAGS & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC5_CFG_STATUS & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
 	pb_addr = (mmTPC5_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS;
 	word_offset = ((mmTPC5_CFG_CFG_BASE_ADDRESS_HIGH &
 			PROT_BITS_OFFS) >> 7) << 2;
@@ -1610,6 +1674,10 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev)
 	mask |= 1 << ((mmTPC5_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2);
 	mask |= 1 << ((mmTPC5_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2);
 	mask |= 1 << ((mmTPC5_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC5_CFG_TPC_STALL & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC5_CFG_MSS_CONFIG & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC5_CFG_TPC_INTR_CAUSE & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC5_CFG_TPC_INTR_MASK & 0x7F) >> 2);
 
 	WREG32(pb_addr + word_offset, ~mask);
 
@@ -1785,6 +1853,16 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev)
 	goya_pb_set_block(hdev, mmTPC6_RD_REGULATOR_BASE);
 	goya_pb_set_block(hdev, mmTPC6_WR_REGULATOR_BASE);
 
+	pb_addr = (mmTPC6_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC6_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2;
+
+	mask = 1 << ((mmTPC6_CFG_SEMAPHORE & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC6_CFG_VFLAGS & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC6_CFG_SFLAGS & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC6_CFG_STATUS & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
 	pb_addr = (mmTPC6_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS;
 	word_offset = ((mmTPC6_CFG_CFG_BASE_ADDRESS_HIGH &
 			PROT_BITS_OFFS) >> 7) << 2;
@@ -1792,6 +1870,10 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev)
 	mask |= 1 << ((mmTPC6_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2);
 	mask |= 1 << ((mmTPC6_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2);
 	mask |= 1 << ((mmTPC6_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC6_CFG_TPC_STALL & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC6_CFG_MSS_CONFIG & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC6_CFG_TPC_INTR_CAUSE & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC6_CFG_TPC_INTR_MASK & 0x7F) >> 2);
 
 	WREG32(pb_addr + word_offset, ~mask);
 
@@ -1967,6 +2049,16 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev)
 	goya_pb_set_block(hdev, mmTPC7_RD_REGULATOR_BASE);
 	goya_pb_set_block(hdev, mmTPC7_WR_REGULATOR_BASE);
 
+	pb_addr = (mmTPC7_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS;
+	word_offset = ((mmTPC7_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2;
+
+	mask = 1 << ((mmTPC7_CFG_SEMAPHORE & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC7_CFG_VFLAGS & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC7_CFG_SFLAGS & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC7_CFG_STATUS & 0x7F) >> 2);
+
+	WREG32(pb_addr + word_offset, ~mask);
+
 	pb_addr = (mmTPC7_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) +	PROT_BITS_OFFS;
 	word_offset = ((mmTPC7_CFG_CFG_BASE_ADDRESS_HIGH &
 			PROT_BITS_OFFS) >> 7) << 2;
@@ -1974,6 +2066,10 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev)
 	mask |= 1 << ((mmTPC7_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2);
 	mask |= 1 << ((mmTPC7_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2);
 	mask |= 1 << ((mmTPC7_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC7_CFG_TPC_STALL & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC7_CFG_MSS_CONFIG & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC7_CFG_TPC_INTR_CAUSE & 0x7F) >> 2);
+	mask |= 1 << ((mmTPC7_CFG_TPC_INTR_MASK & 0x7F) >> 2);
 
 	WREG32(pb_addr + word_offset, ~mask);
 
@@ -3024,3 +3120,8 @@ void goya_init_security(struct hl_device *hdev)
 
 	goya_init_protection_bits(hdev);
 }
+
+void goya_ack_protection_bits_errors(struct hl_device *hdev)
+{
+
+}
diff --git a/drivers/misc/habanalabs/include/qman_if.h b/drivers/accel/habanalabs/include/common/qman_if.h
index 0fdb49188ed7..7ed7739575ee 100644
--- a/drivers/misc/habanalabs/include/qman_if.h
+++ b/drivers/accel/habanalabs/include/common/qman_if.h
@@ -40,7 +40,7 @@ struct hl_bd {
  */
 
 #define BD_CTL_COMP_OFFSET_SHIFT	16
-#define BD_CTL_COMP_OFFSET_MASK		0x00FF0000
+#define BD_CTL_COMP_OFFSET_MASK		0x0FFF0000
 
 #define BD_CTL_COMP_DATA_SHIFT		0
 #define BD_CTL_COMP_DATA_MASK		0x0000FFFF
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/cpu_if_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/cpu_if_regs.h
new file mode 100644
index 000000000000..cf80e31317ad
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/cpu_if_regs.h
@@ -0,0 +1,174 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_CPU_IF_REGS_H_
+#define ASIC_REG_CPU_IF_REGS_H_
+
+/*
+ *****************************************
+ *   CPU_IF (Prototype: CPU_IF)
+ *****************************************
+ */
+
+#define mmCPU_IF_ARUSER_OVR                                          0x442104
+
+#define mmCPU_IF_ARUSER_OVR_EN                                       0x442108
+
+#define mmCPU_IF_AWUSER_OVR                                          0x44210C
+
+#define mmCPU_IF_AWUSER_OVR_EN                                       0x442110
+
+#define mmCPU_IF_AXCACHE_OVR                                         0x442114
+
+#define mmCPU_IF_LOCK_OVR                                            0x442118
+
+#define mmCPU_IF_PROT_OVR                                            0x44211C
+
+#define mmCPU_IF_MAX_OUTSTANDING                                     0x442120
+
+#define mmCPU_IF_EARLY_BRESP_EN                                      0x442124
+
+#define mmCPU_IF_FORCE_RSP_OK                                        0x442128
+
+#define mmCPU_IF_CPU_MSB_ADDR                                        0x44212C
+
+#define mmCPU_IF_AXI_SPLIT_INTR                                      0x442130
+
+#define mmCPU_IF_TOTAL_WR_CNT                                        0x442140
+
+#define mmCPU_IF_INFLIGHT_WR_CNT                                     0x442144
+
+#define mmCPU_IF_TOTAL_RD_CNT                                        0x442150
+
+#define mmCPU_IF_INFLIGHT_RD_CNT                                     0x442154
+
+#define mmCPU_IF_PF_PQ_PI                                            0x442200
+
+#define mmCPU_IF_PQ_BASE_ADDR_LOW                                    0x442204
+
+#define mmCPU_IF_PQ_BASE_ADDR_HIGH                                   0x442208
+
+#define mmCPU_IF_PQ_LENGTH                                           0x44220C
+
+#define mmCPU_IF_CQ_BASE_ADDR_LOW                                    0x442210
+
+#define mmCPU_IF_CQ_BASE_ADDR_HIGH                                   0x442214
+
+#define mmCPU_IF_CQ_LENGTH                                           0x442218
+
+#define mmCPU_IF_EQ_BASE_ADDR_LOW                                    0x442220
+
+#define mmCPU_IF_EQ_BASE_ADDR_HIGH                                   0x442224
+
+#define mmCPU_IF_EQ_LENGTH                                           0x442228
+
+#define mmCPU_IF_EQ_RD_OFFS                                          0x44222C
+
+#define mmCPU_IF_QUEUE_INIT                                          0x442230
+
+#define mmCPU_IF_TPC_SERR_INTR_STS                                   0x442300
+
+#define mmCPU_IF_TPC_SERR_INTR_CLR                                   0x442304
+
+#define mmCPU_IF_TPC_SERR_INTR_MASK                                  0x442308
+
+#define mmCPU_IF_TPC_DERR_INTR_STS                                   0x442310
+
+#define mmCPU_IF_TPC_DERR_INTR_CLR                                   0x442314
+
+#define mmCPU_IF_TPC_DERR_INTR_MASK                                  0x442318
+
+#define mmCPU_IF_DMA_SERR_INTR_STS                                   0x442320
+
+#define mmCPU_IF_DMA_SERR_INTR_CLR                                   0x442324
+
+#define mmCPU_IF_DMA_SERR_INTR_MASK                                  0x442328
+
+#define mmCPU_IF_DMA_DERR_INTR_STS                                   0x442330
+
+#define mmCPU_IF_DMA_DERR_INTR_CLR                                   0x442334
+
+#define mmCPU_IF_DMA_DERR_INTR_MASK                                  0x442338
+
+#define mmCPU_IF_SRAM_SERR_INTR_STS                                  0x442340
+
+#define mmCPU_IF_SRAM_SERR_INTR_CLR                                  0x442344
+
+#define mmCPU_IF_SRAM_SERR_INTR_MASK                                 0x442348
+
+#define mmCPU_IF_SRAM_DERR_INTR_STS                                  0x442350
+
+#define mmCPU_IF_SRAM_DERR_INTR_CLR                                  0x442354
+
+#define mmCPU_IF_SRAM_DERR_INTR_MASK                                 0x442358
+
+#define mmCPU_IF_NIC_SERR_INTR_STS                                   0x442360
+
+#define mmCPU_IF_NIC_SERR_INTR_CLR                                   0x442364
+
+#define mmCPU_IF_NIC_SERR_INTR_MASK                                  0x442368
+
+#define mmCPU_IF_NIC_DERR_INTR_STS                                   0x442370
+
+#define mmCPU_IF_NIC_DERR_INTR_CLR                                   0x442374
+
+#define mmCPU_IF_NIC_DERR_INTR_MASK                                  0x442378
+
+#define mmCPU_IF_DMA_IF_SERR_INTR_STS                                0x442380
+
+#define mmCPU_IF_DMA_IF_SERR_INTR_CLR                                0x442384
+
+#define mmCPU_IF_DMA_IF_SERR_INTR_MASK                               0x442388
+
+#define mmCPU_IF_DMA_IF_DERR_INTR_STS                                0x442390
+
+#define mmCPU_IF_DMA_IF_DERR_INTR_CLR                                0x442394
+
+#define mmCPU_IF_DMA_IF_DERR_INTR_MASK                               0x442398
+
+#define mmCPU_IF_HBM_SERR_INTR_STS                                   0x4423A0
+
+#define mmCPU_IF_HBM_SERR_INTR_CLR                                   0x4423A4
+
+#define mmCPU_IF_HBM_SERR_INTR_MASK                                  0x4423A8
+
+#define mmCPU_IF_HBM_DERR_INTR_STS                                   0x4423B0
+
+#define mmCPU_IF_HBM_DERR_INTR_CLR                                   0x4423B4
+
+#define mmCPU_IF_HBM_DERR_INTR_MASK                                  0x4423B8
+
+#define mmCPU_IF_PLL_SEI_INTR_STS                                    0x442400
+
+#define mmCPU_IF_PLL_SEI_INTR_CLR                                    0x442404
+
+#define mmCPU_IF_PLL_SEI_INTR_MASK                                   0x442408
+
+#define mmCPU_IF_NIC_SEI_INTR_STS                                    0x442410
+
+#define mmCPU_IF_NIC_SEI_INTR_CLR                                    0x442414
+
+#define mmCPU_IF_NIC_SEI_INTR_MASK                                   0x442418
+
+#define mmCPU_IF_DMA_SEI_INTR_STS                                    0x442420
+
+#define mmCPU_IF_DMA_SEI_INTR_CLR                                    0x442424
+
+#define mmCPU_IF_DMA_SEI_INTR_MASK                                   0x442428
+
+#define mmCPU_IF_DMA_IF_SEI_INTR_STS                                 0x442430
+
+#define mmCPU_IF_DMA_IF_SEI_INTR_CLR                                 0x442434
+
+#define mmCPU_IF_DMA_IF_SEI_INTR_MASK                                0x442438
+
+#endif /* ASIC_REG_CPU_IF_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma0_core_masks.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma0_core_masks.h
new file mode 100644
index 000000000000..d079a37acab8
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma0_core_masks.h
@@ -0,0 +1,348 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DMA0_CORE_MASKS_H_
+#define ASIC_REG_DMA0_CORE_MASKS_H_
+
+/*
+ *****************************************
+ *   DMA0_CORE (Prototype: DMA_CORE)
+ *****************************************
+ */
+
+/* DMA0_CORE_CFG_0 */
+#define DMA0_CORE_CFG_0_EN_SHIFT                                     0
+#define DMA0_CORE_CFG_0_EN_MASK                                      0x1
+
+/* DMA0_CORE_CFG_1 */
+#define DMA0_CORE_CFG_1_HALT_SHIFT                                   0
+#define DMA0_CORE_CFG_1_HALT_MASK                                    0x1
+#define DMA0_CORE_CFG_1_FLUSH_SHIFT                                  1
+#define DMA0_CORE_CFG_1_FLUSH_MASK                                   0x2
+#define DMA0_CORE_CFG_1_SB_FORCE_MISS_SHIFT                          2
+#define DMA0_CORE_CFG_1_SB_FORCE_MISS_MASK                           0x4
+
+/* DMA0_CORE_LBW_MAX_OUTSTAND */
+#define DMA0_CORE_LBW_MAX_OUTSTAND_VAL_SHIFT                         0
+#define DMA0_CORE_LBW_MAX_OUTSTAND_VAL_MASK                          0x1F
+
+/* DMA0_CORE_SRC_BASE_LO */
+#define DMA0_CORE_SRC_BASE_LO_VAL_SHIFT                              0
+#define DMA0_CORE_SRC_BASE_LO_VAL_MASK                               0xFFFFFFFF
+
+/* DMA0_CORE_SRC_BASE_HI */
+#define DMA0_CORE_SRC_BASE_HI_VAL_SHIFT                              0
+#define DMA0_CORE_SRC_BASE_HI_VAL_MASK                               0xFFFFFFFF
+
+/* DMA0_CORE_DST_BASE_LO */
+#define DMA0_CORE_DST_BASE_LO_VAL_SHIFT                              0
+#define DMA0_CORE_DST_BASE_LO_VAL_MASK                               0xFFFFFFFF
+
+/* DMA0_CORE_DST_BASE_HI */
+#define DMA0_CORE_DST_BASE_HI_VAL_SHIFT                              0
+#define DMA0_CORE_DST_BASE_HI_VAL_MASK                               0xFFFFFF
+#define DMA0_CORE_DST_BASE_HI_CTX_ID_HI_SHIFT                        24
+#define DMA0_CORE_DST_BASE_HI_CTX_ID_HI_MASK                         0xFF000000
+
+/* DMA0_CORE_SRC_TSIZE_1 */
+#define DMA0_CORE_SRC_TSIZE_1_VAL_SHIFT                              0
+#define DMA0_CORE_SRC_TSIZE_1_VAL_MASK                               0xFFFFFFFF
+
+/* DMA0_CORE_SRC_STRIDE_1 */
+#define DMA0_CORE_SRC_STRIDE_1_VAL_SHIFT                             0
+#define DMA0_CORE_SRC_STRIDE_1_VAL_MASK                              0xFFFFFFFF
+
+/* DMA0_CORE_SRC_TSIZE_2 */
+#define DMA0_CORE_SRC_TSIZE_2_VAL_SHIFT                              0
+#define DMA0_CORE_SRC_TSIZE_2_VAL_MASK                               0xFFFFFFFF
+
+/* DMA0_CORE_SRC_STRIDE_2 */
+#define DMA0_CORE_SRC_STRIDE_2_VAL_SHIFT                             0
+#define DMA0_CORE_SRC_STRIDE_2_VAL_MASK                              0xFFFFFFFF
+
+/* DMA0_CORE_SRC_TSIZE_3 */
+#define DMA0_CORE_SRC_TSIZE_3_VAL_SHIFT                              0
+#define DMA0_CORE_SRC_TSIZE_3_VAL_MASK                               0xFFFFFFFF
+
+/* DMA0_CORE_SRC_STRIDE_3 */
+#define DMA0_CORE_SRC_STRIDE_3_VAL_SHIFT                             0
+#define DMA0_CORE_SRC_STRIDE_3_VAL_MASK                              0xFFFFFFFF
+
+/* DMA0_CORE_SRC_TSIZE_4 */
+#define DMA0_CORE_SRC_TSIZE_4_VAL_SHIFT                              0
+#define DMA0_CORE_SRC_TSIZE_4_VAL_MASK                               0xFFFFFFFF
+
+/* DMA0_CORE_SRC_STRIDE_4 */
+#define DMA0_CORE_SRC_STRIDE_4_VAL_SHIFT                             0
+#define DMA0_CORE_SRC_STRIDE_4_VAL_MASK                              0xFFFFFFFF
+
+/* DMA0_CORE_SRC_TSIZE_0 */
+#define DMA0_CORE_SRC_TSIZE_0_VAL_SHIFT                              0
+#define DMA0_CORE_SRC_TSIZE_0_VAL_MASK                               0xFFFFFFFF
+
+/* DMA0_CORE_DST_TSIZE_1 */
+#define DMA0_CORE_DST_TSIZE_1_VAL_SHIFT                              0
+#define DMA0_CORE_DST_TSIZE_1_VAL_MASK                               0xFFFFFFFF
+
+/* DMA0_CORE_DST_STRIDE_1 */
+#define DMA0_CORE_DST_STRIDE_1_VAL_SHIFT                             0
+#define DMA0_CORE_DST_STRIDE_1_VAL_MASK                              0xFFFFFFFF
+
+/* DMA0_CORE_DST_TSIZE_2 */
+#define DMA0_CORE_DST_TSIZE_2_VAL_SHIFT                              0
+#define DMA0_CORE_DST_TSIZE_2_VAL_MASK                               0xFFFFFFFF
+
+/* DMA0_CORE_DST_STRIDE_2 */
+#define DMA0_CORE_DST_STRIDE_2_VAL_SHIFT                             0
+#define DMA0_CORE_DST_STRIDE_2_VAL_MASK                              0xFFFFFFFF
+
+/* DMA0_CORE_DST_TSIZE_3 */
+#define DMA0_CORE_DST_TSIZE_3_VAL_SHIFT                              0
+#define DMA0_CORE_DST_TSIZE_3_VAL_MASK                               0xFFFFFFFF
+
+/* DMA0_CORE_DST_STRIDE_3 */
+#define DMA0_CORE_DST_STRIDE_3_VAL_SHIFT                             0
+#define DMA0_CORE_DST_STRIDE_3_VAL_MASK                              0xFFFFFFFF
+
+/* DMA0_CORE_DST_TSIZE_4 */
+#define DMA0_CORE_DST_TSIZE_4_VAL_SHIFT                              0
+#define DMA0_CORE_DST_TSIZE_4_VAL_MASK                               0xFFFFFFFF
+
+/* DMA0_CORE_DST_STRIDE_4 */
+#define DMA0_CORE_DST_STRIDE_4_VAL_SHIFT                             0
+#define DMA0_CORE_DST_STRIDE_4_VAL_MASK                              0xFFFFFFFF
+
+/* DMA0_CORE_DST_TSIZE_0 */
+#define DMA0_CORE_DST_TSIZE_0_VAL_SHIFT                              0
+#define DMA0_CORE_DST_TSIZE_0_VAL_MASK                               0xFFFFFFFF
+
+/* DMA0_CORE_COMMIT */
+#define DMA0_CORE_COMMIT_WR_COMP_EN_SHIFT                            0
+#define DMA0_CORE_COMMIT_WR_COMP_EN_MASK                             0x1
+#define DMA0_CORE_COMMIT_TRANSPOSE_SHIFT                             1
+#define DMA0_CORE_COMMIT_TRANSPOSE_MASK                              0x2
+#define DMA0_CORE_COMMIT_DTYPE_SHIFT                                 2
+#define DMA0_CORE_COMMIT_DTYPE_MASK                                  0x4
+#define DMA0_CORE_COMMIT_LIN_SHIFT                                   3
+#define DMA0_CORE_COMMIT_LIN_MASK                                    0x8
+#define DMA0_CORE_COMMIT_MEM_SET_SHIFT                               4
+#define DMA0_CORE_COMMIT_MEM_SET_MASK                                0x10
+#define DMA0_CORE_COMMIT_COMPRESS_SHIFT                              5
+#define DMA0_CORE_COMMIT_COMPRESS_MASK                               0x20
+#define DMA0_CORE_COMMIT_DECOMPRESS_SHIFT                            6
+#define DMA0_CORE_COMMIT_DECOMPRESS_MASK                             0x40
+#define DMA0_CORE_COMMIT_CTX_ID_SHIFT                                16
+#define DMA0_CORE_COMMIT_CTX_ID_MASK                                 0xFF0000
+
+/* DMA0_CORE_WR_COMP_WDATA */
+#define DMA0_CORE_WR_COMP_WDATA_VAL_SHIFT                            0
+#define DMA0_CORE_WR_COMP_WDATA_VAL_MASK                             0xFFFFFFFF
+
+/* DMA0_CORE_WR_COMP_ADDR_LO */
+#define DMA0_CORE_WR_COMP_ADDR_LO_VAL_SHIFT                          0
+#define DMA0_CORE_WR_COMP_ADDR_LO_VAL_MASK                           0xFFFFFFFF
+
+/* DMA0_CORE_WR_COMP_ADDR_HI */
+#define DMA0_CORE_WR_COMP_ADDR_HI_VAL_SHIFT                          0
+#define DMA0_CORE_WR_COMP_ADDR_HI_VAL_MASK                           0xFFFFFFFF
+
+/* DMA0_CORE_WR_COMP_AWUSER_31_11 */
+#define DMA0_CORE_WR_COMP_AWUSER_31_11_VAL_SHIFT                     0
+#define DMA0_CORE_WR_COMP_AWUSER_31_11_VAL_MASK                      0x1FFFFF
+
+/* DMA0_CORE_TE_NUMROWS */
+#define DMA0_CORE_TE_NUMROWS_VAL_SHIFT                               0
+#define DMA0_CORE_TE_NUMROWS_VAL_MASK                                0xFFFFFFFF
+
+/* DMA0_CORE_PROT */
+#define DMA0_CORE_PROT_VAL_SHIFT                                     0
+#define DMA0_CORE_PROT_VAL_MASK                                      0x1
+#define DMA0_CORE_PROT_ERR_VAL_SHIFT                                 1
+#define DMA0_CORE_PROT_ERR_VAL_MASK                                  0x2
+
+/* DMA0_CORE_SECURE_PROPS */
+#define DMA0_CORE_SECURE_PROPS_ASID_SHIFT                            0
+#define DMA0_CORE_SECURE_PROPS_ASID_MASK                             0x3FF
+#define DMA0_CORE_SECURE_PROPS_MMBP_SHIFT                            10
+#define DMA0_CORE_SECURE_PROPS_MMBP_MASK                             0x400
+
+/* DMA0_CORE_NON_SECURE_PROPS */
+#define DMA0_CORE_NON_SECURE_PROPS_ASID_SHIFT                        0
+#define DMA0_CORE_NON_SECURE_PROPS_ASID_MASK                         0x3FF
+#define DMA0_CORE_NON_SECURE_PROPS_MMBP_SHIFT                        10
+#define DMA0_CORE_NON_SECURE_PROPS_MMBP_MASK                         0x400
+
+/* DMA0_CORE_RD_MAX_OUTSTAND */
+#define DMA0_CORE_RD_MAX_OUTSTAND_VAL_SHIFT                          0
+#define DMA0_CORE_RD_MAX_OUTSTAND_VAL_MASK                           0xFFF
+
+/* DMA0_CORE_RD_MAX_SIZE */
+#define DMA0_CORE_RD_MAX_SIZE_DATA_SHIFT                             0
+#define DMA0_CORE_RD_MAX_SIZE_DATA_MASK                              0x7FF
+#define DMA0_CORE_RD_MAX_SIZE_MD_SHIFT                               16
+#define DMA0_CORE_RD_MAX_SIZE_MD_MASK                                0x7FF0000
+
+/* DMA0_CORE_RD_ARCACHE */
+#define DMA0_CORE_RD_ARCACHE_VAL_SHIFT                               0
+#define DMA0_CORE_RD_ARCACHE_VAL_MASK                                0xF
+
+/* DMA0_CORE_RD_ARUSER_31_11 */
+#define DMA0_CORE_RD_ARUSER_31_11_VAL_SHIFT                          0
+#define DMA0_CORE_RD_ARUSER_31_11_VAL_MASK                           0x1FFFFF
+
+/* DMA0_CORE_RD_INFLIGHTS */
+#define DMA0_CORE_RD_INFLIGHTS_VAL_SHIFT                             0
+#define DMA0_CORE_RD_INFLIGHTS_VAL_MASK                              0xFFFFFFFF
+
+/* DMA0_CORE_WR_MAX_OUTSTAND */
+#define DMA0_CORE_WR_MAX_OUTSTAND_VAL_SHIFT                          0
+#define DMA0_CORE_WR_MAX_OUTSTAND_VAL_MASK                           0xFFF
+
+/* DMA0_CORE_WR_MAX_AWID */
+#define DMA0_CORE_WR_MAX_AWID_VAL_SHIFT                              0
+#define DMA0_CORE_WR_MAX_AWID_VAL_MASK                               0xFFFF
+
+/* DMA0_CORE_WR_AWCACHE */
+#define DMA0_CORE_WR_AWCACHE_VAL_SHIFT                               0
+#define DMA0_CORE_WR_AWCACHE_VAL_MASK                                0xF
+
+/* DMA0_CORE_WR_AWUSER_31_11 */
+#define DMA0_CORE_WR_AWUSER_31_11_VAL_SHIFT                          0
+#define DMA0_CORE_WR_AWUSER_31_11_VAL_MASK                           0x1FFFFF
+
+/* DMA0_CORE_WR_INFLIGHTS */
+#define DMA0_CORE_WR_INFLIGHTS_VAL_SHIFT                             0
+#define DMA0_CORE_WR_INFLIGHTS_VAL_MASK                              0xFFFF
+
+/* DMA0_CORE_RD_RATE_LIM_CFG_0 */
+#define DMA0_CORE_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT                  0
+#define DMA0_CORE_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK                   0xFF
+#define DMA0_CORE_RD_RATE_LIM_CFG_0_SAT_SHIFT                        16
+#define DMA0_CORE_RD_RATE_LIM_CFG_0_SAT_MASK                         0xFF0000
+
+/* DMA0_CORE_RD_RATE_LIM_CFG_1 */
+#define DMA0_CORE_RD_RATE_LIM_CFG_1_TOUT_SHIFT                       0
+#define DMA0_CORE_RD_RATE_LIM_CFG_1_TOUT_MASK                        0xFF
+#define DMA0_CORE_RD_RATE_LIM_CFG_1_EN_SHIFT                         31
+#define DMA0_CORE_RD_RATE_LIM_CFG_1_EN_MASK                          0x80000000
+
+/* DMA0_CORE_WR_RATE_LIM_CFG_0 */
+#define DMA0_CORE_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT                  0
+#define DMA0_CORE_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK                   0xFF
+#define DMA0_CORE_WR_RATE_LIM_CFG_0_SAT_SHIFT                        16
+#define DMA0_CORE_WR_RATE_LIM_CFG_0_SAT_MASK                         0xFF0000
+
+/* DMA0_CORE_WR_RATE_LIM_CFG_1 */
+#define DMA0_CORE_WR_RATE_LIM_CFG_1_TOUT_SHIFT                       0
+#define DMA0_CORE_WR_RATE_LIM_CFG_1_TOUT_MASK                        0xFF
+#define DMA0_CORE_WR_RATE_LIM_CFG_1_EN_SHIFT                         31
+#define DMA0_CORE_WR_RATE_LIM_CFG_1_EN_MASK                          0x80000000
+
+/* DMA0_CORE_ERR_CFG */
+#define DMA0_CORE_ERR_CFG_ERR_MSG_EN_SHIFT                           0
+#define DMA0_CORE_ERR_CFG_ERR_MSG_EN_MASK                            0x1
+#define DMA0_CORE_ERR_CFG_STOP_ON_ERR_SHIFT                          1
+#define DMA0_CORE_ERR_CFG_STOP_ON_ERR_MASK                           0x2
+
+/* DMA0_CORE_ERR_CAUSE */
+#define DMA0_CORE_ERR_CAUSE_HBW_RD_ERR_SHIFT                         0
+#define DMA0_CORE_ERR_CAUSE_HBW_RD_ERR_MASK                          0x1
+#define DMA0_CORE_ERR_CAUSE_HBW_WR_ERR_SHIFT                         1
+#define DMA0_CORE_ERR_CAUSE_HBW_WR_ERR_MASK                          0x2
+#define DMA0_CORE_ERR_CAUSE_LBW_WR_ERR_SHIFT                         2
+#define DMA0_CORE_ERR_CAUSE_LBW_WR_ERR_MASK                          0x4
+#define DMA0_CORE_ERR_CAUSE_DESC_OVF_SHIFT                           3
+#define DMA0_CORE_ERR_CAUSE_DESC_OVF_MASK                            0x8
+
+/* DMA0_CORE_ERRMSG_ADDR_LO */
+#define DMA0_CORE_ERRMSG_ADDR_LO_VAL_SHIFT                           0
+#define DMA0_CORE_ERRMSG_ADDR_LO_VAL_MASK                            0xFFFFFFFF
+
+/* DMA0_CORE_ERRMSG_ADDR_HI */
+#define DMA0_CORE_ERRMSG_ADDR_HI_VAL_SHIFT                           0
+#define DMA0_CORE_ERRMSG_ADDR_HI_VAL_MASK                            0xFFFFFFFF
+
+/* DMA0_CORE_ERRMSG_WDATA */
+#define DMA0_CORE_ERRMSG_WDATA_VAL_SHIFT                             0
+#define DMA0_CORE_ERRMSG_WDATA_VAL_MASK                              0xFFFFFFFF
+
+/* DMA0_CORE_STS0 */
+#define DMA0_CORE_STS0_RD_REQ_CNT_SHIFT                              0
+#define DMA0_CORE_STS0_RD_REQ_CNT_MASK                               0x7FFF
+#define DMA0_CORE_STS0_WR_REQ_CNT_SHIFT                              16
+#define DMA0_CORE_STS0_WR_REQ_CNT_MASK                               0x7FFF0000
+#define DMA0_CORE_STS0_BUSY_SHIFT                                    31
+#define DMA0_CORE_STS0_BUSY_MASK                                     0x80000000
+
+/* DMA0_CORE_STS1 */
+#define DMA0_CORE_STS1_IS_HALT_SHIFT                                 0
+#define DMA0_CORE_STS1_IS_HALT_MASK                                  0x1
+
+/* DMA0_CORE_RD_DBGMEM_ADD */
+#define DMA0_CORE_RD_DBGMEM_ADD_VAL_SHIFT                            0
+#define DMA0_CORE_RD_DBGMEM_ADD_VAL_MASK                             0xFFFFFFFF
+
+/* DMA0_CORE_RD_DBGMEM_DATA_WR */
+#define DMA0_CORE_RD_DBGMEM_DATA_WR_VAL_SHIFT                        0
+#define DMA0_CORE_RD_DBGMEM_DATA_WR_VAL_MASK                         0xFFFFFFFF
+
+/* DMA0_CORE_RD_DBGMEM_DATA_RD */
+#define DMA0_CORE_RD_DBGMEM_DATA_RD_VAL_SHIFT                        0
+#define DMA0_CORE_RD_DBGMEM_DATA_RD_VAL_MASK                         0xFFFFFFFF
+
+/* DMA0_CORE_RD_DBGMEM_CTRL */
+#define DMA0_CORE_RD_DBGMEM_CTRL_WR_NRD_SHIFT                        0
+#define DMA0_CORE_RD_DBGMEM_CTRL_WR_NRD_MASK                         0x1
+
+/* DMA0_CORE_RD_DBGMEM_RC */
+#define DMA0_CORE_RD_DBGMEM_RC_VALID_SHIFT                           0
+#define DMA0_CORE_RD_DBGMEM_RC_VALID_MASK                            0x1
+
+/* DMA0_CORE_DBG_HBW_AXI_AR_CNT */
+
+/* DMA0_CORE_DBG_HBW_AXI_AW_CNT */
+
+/* DMA0_CORE_DBG_LBW_AXI_AW_CNT */
+
+/* DMA0_CORE_DBG_DESC_CNT */
+#define DMA0_CORE_DBG_DESC_CNT_RD_STS_CTX_CNT_SHIFT                  0
+#define DMA0_CORE_DBG_DESC_CNT_RD_STS_CTX_CNT_MASK                   0xFFFFFFFF
+
+/* DMA0_CORE_DBG_STS */
+#define DMA0_CORE_DBG_STS_RD_CTX_FULL_SHIFT                          0
+#define DMA0_CORE_DBG_STS_RD_CTX_FULL_MASK                           0x1
+#define DMA0_CORE_DBG_STS_WR_CTX_FULL_SHIFT                          1
+#define DMA0_CORE_DBG_STS_WR_CTX_FULL_MASK                           0x2
+#define DMA0_CORE_DBG_STS_WR_COMP_FULL_SHIFT                         2
+#define DMA0_CORE_DBG_STS_WR_COMP_FULL_MASK                          0x4
+#define DMA0_CORE_DBG_STS_RD_CTX_EMPTY_SHIFT                         3
+#define DMA0_CORE_DBG_STS_RD_CTX_EMPTY_MASK                          0x8
+#define DMA0_CORE_DBG_STS_WR_CTX_EMPTY_SHIFT                         4
+#define DMA0_CORE_DBG_STS_WR_CTX_EMPTY_MASK                          0x10
+#define DMA0_CORE_DBG_STS_WR_COMP_EMPTY_SHIFT                        5
+#define DMA0_CORE_DBG_STS_WR_COMP_EMPTY_MASK                         0x20
+#define DMA0_CORE_DBG_STS_TE_EMPTY_SHIFT                             6
+#define DMA0_CORE_DBG_STS_TE_EMPTY_MASK                              0x40
+#define DMA0_CORE_DBG_STS_TE_BUSY_SHIFT                              7
+#define DMA0_CORE_DBG_STS_TE_BUSY_MASK                               0x80
+#define DMA0_CORE_DBG_STS_GSKT_EMPTY_SHIFT                           8
+#define DMA0_CORE_DBG_STS_GSKT_EMPTY_MASK                            0x100
+#define DMA0_CORE_DBG_STS_GSKT_FULL_SHIFT                            9
+#define DMA0_CORE_DBG_STS_GSKT_FULL_MASK                             0x200
+#define DMA0_CORE_DBG_STS_RDBUF_FULLNESS_SHIFT                       20
+#define DMA0_CORE_DBG_STS_RDBUF_FULLNESS_MASK                        0x7FF00000
+
+/* DMA0_CORE_DBG_RD_DESC_ID */
+
+/* DMA0_CORE_DBG_WR_DESC_ID */
+
+#endif /* ASIC_REG_DMA0_CORE_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma0_core_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma0_core_regs.h
new file mode 100644
index 000000000000..1fdd5d5fc6d2
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma0_core_regs.h
@@ -0,0 +1,156 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DMA0_CORE_REGS_H_
+#define ASIC_REG_DMA0_CORE_REGS_H_
+
+/*
+ *****************************************
+ *   DMA0_CORE (Prototype: DMA_CORE)
+ *****************************************
+ */
+
+#define mmDMA0_CORE_CFG_0                                            0x500000
+
+#define mmDMA0_CORE_CFG_1                                            0x500004
+
+#define mmDMA0_CORE_LBW_MAX_OUTSTAND                                 0x500008
+
+#define mmDMA0_CORE_SRC_BASE_LO                                      0x500014
+
+#define mmDMA0_CORE_SRC_BASE_HI                                      0x500018
+
+#define mmDMA0_CORE_DST_BASE_LO                                      0x50001C
+
+#define mmDMA0_CORE_DST_BASE_HI                                      0x500020
+
+#define mmDMA0_CORE_SRC_TSIZE_1                                      0x50002C
+
+#define mmDMA0_CORE_SRC_STRIDE_1                                     0x500030
+
+#define mmDMA0_CORE_SRC_TSIZE_2                                      0x500034
+
+#define mmDMA0_CORE_SRC_STRIDE_2                                     0x500038
+
+#define mmDMA0_CORE_SRC_TSIZE_3                                      0x50003C
+
+#define mmDMA0_CORE_SRC_STRIDE_3                                     0x500040
+
+#define mmDMA0_CORE_SRC_TSIZE_4                                      0x500044
+
+#define mmDMA0_CORE_SRC_STRIDE_4                                     0x500048
+
+#define mmDMA0_CORE_SRC_TSIZE_0                                      0x50004C
+
+#define mmDMA0_CORE_DST_TSIZE_1                                      0x500054
+
+#define mmDMA0_CORE_DST_STRIDE_1                                     0x500058
+
+#define mmDMA0_CORE_DST_TSIZE_2                                      0x50005C
+
+#define mmDMA0_CORE_DST_STRIDE_2                                     0x500060
+
+#define mmDMA0_CORE_DST_TSIZE_3                                      0x500064
+
+#define mmDMA0_CORE_DST_STRIDE_3                                     0x500068
+
+#define mmDMA0_CORE_DST_TSIZE_4                                      0x50006C
+
+#define mmDMA0_CORE_DST_STRIDE_4                                     0x500070
+
+#define mmDMA0_CORE_DST_TSIZE_0                                      0x500074
+
+#define mmDMA0_CORE_COMMIT                                           0x500078
+
+#define mmDMA0_CORE_WR_COMP_WDATA                                    0x50007C
+
+#define mmDMA0_CORE_WR_COMP_ADDR_LO                                  0x500080
+
+#define mmDMA0_CORE_WR_COMP_ADDR_HI                                  0x500084
+
+#define mmDMA0_CORE_WR_COMP_AWUSER_31_11                             0x500088
+
+#define mmDMA0_CORE_TE_NUMROWS                                       0x500094
+
+#define mmDMA0_CORE_PROT                                             0x5000B8
+
+#define mmDMA0_CORE_SECURE_PROPS                                     0x5000F0
+
+#define mmDMA0_CORE_NON_SECURE_PROPS                                 0x5000F4
+
+#define mmDMA0_CORE_RD_MAX_OUTSTAND                                  0x500100
+
+#define mmDMA0_CORE_RD_MAX_SIZE                                      0x500104
+
+#define mmDMA0_CORE_RD_ARCACHE                                       0x500108
+
+#define mmDMA0_CORE_RD_ARUSER_31_11                                  0x500110
+
+#define mmDMA0_CORE_RD_INFLIGHTS                                     0x500114
+
+#define mmDMA0_CORE_WR_MAX_OUTSTAND                                  0x500120
+
+#define mmDMA0_CORE_WR_MAX_AWID                                      0x500124
+
+#define mmDMA0_CORE_WR_AWCACHE                                       0x500128
+
+#define mmDMA0_CORE_WR_AWUSER_31_11                                  0x500130
+
+#define mmDMA0_CORE_WR_INFLIGHTS                                     0x500134
+
+#define mmDMA0_CORE_RD_RATE_LIM_CFG_0                                0x500150
+
+#define mmDMA0_CORE_RD_RATE_LIM_CFG_1                                0x500154
+
+#define mmDMA0_CORE_WR_RATE_LIM_CFG_0                                0x500158
+
+#define mmDMA0_CORE_WR_RATE_LIM_CFG_1                                0x50015C
+
+#define mmDMA0_CORE_ERR_CFG                                          0x500160
+
+#define mmDMA0_CORE_ERR_CAUSE                                        0x500164
+
+#define mmDMA0_CORE_ERRMSG_ADDR_LO                                   0x500170
+
+#define mmDMA0_CORE_ERRMSG_ADDR_HI                                   0x500174
+
+#define mmDMA0_CORE_ERRMSG_WDATA                                     0x500178
+
+#define mmDMA0_CORE_STS0                                             0x500190
+
+#define mmDMA0_CORE_STS1                                             0x500194
+
+#define mmDMA0_CORE_RD_DBGMEM_ADD                                    0x500200
+
+#define mmDMA0_CORE_RD_DBGMEM_DATA_WR                                0x500204
+
+#define mmDMA0_CORE_RD_DBGMEM_DATA_RD                                0x500208
+
+#define mmDMA0_CORE_RD_DBGMEM_CTRL                                   0x50020C
+
+#define mmDMA0_CORE_RD_DBGMEM_RC                                     0x500210
+
+#define mmDMA0_CORE_DBG_HBW_AXI_AR_CNT                               0x500220
+
+#define mmDMA0_CORE_DBG_HBW_AXI_AW_CNT                               0x500224
+
+#define mmDMA0_CORE_DBG_LBW_AXI_AW_CNT                               0x500228
+
+#define mmDMA0_CORE_DBG_DESC_CNT                                     0x50022C
+
+#define mmDMA0_CORE_DBG_STS                                          0x500230
+
+#define mmDMA0_CORE_DBG_RD_DESC_ID                                   0x500234
+
+#define mmDMA0_CORE_DBG_WR_DESC_ID                                   0x500238
+
+#endif /* ASIC_REG_DMA0_CORE_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma0_qm_masks.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma0_qm_masks.h
new file mode 100644
index 000000000000..48376aabc3ba
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma0_qm_masks.h
@@ -0,0 +1,800 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DMA0_QM_MASKS_H_
+#define ASIC_REG_DMA0_QM_MASKS_H_
+
+/*
+ *****************************************
+ *   DMA0_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+/* DMA0_QM_GLBL_CFG0 */
+#define DMA0_QM_GLBL_CFG0_PQF_EN_SHIFT                               0
+#define DMA0_QM_GLBL_CFG0_PQF_EN_MASK                                0xF
+#define DMA0_QM_GLBL_CFG0_CQF_EN_SHIFT                               4
+#define DMA0_QM_GLBL_CFG0_CQF_EN_MASK                                0x1F0
+#define DMA0_QM_GLBL_CFG0_CP_EN_SHIFT                                9
+#define DMA0_QM_GLBL_CFG0_CP_EN_MASK                                 0x3E00
+
+/* DMA0_QM_GLBL_CFG1 */
+#define DMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT                             0
+#define DMA0_QM_GLBL_CFG1_PQF_STOP_MASK                              0xF
+#define DMA0_QM_GLBL_CFG1_CQF_STOP_SHIFT                             4
+#define DMA0_QM_GLBL_CFG1_CQF_STOP_MASK                              0x1F0
+#define DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT                              9
+#define DMA0_QM_GLBL_CFG1_CP_STOP_MASK                               0x3E00
+#define DMA0_QM_GLBL_CFG1_PQF_FLUSH_SHIFT                            16
+#define DMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK                             0xF0000
+#define DMA0_QM_GLBL_CFG1_CQF_FLUSH_SHIFT                            20
+#define DMA0_QM_GLBL_CFG1_CQF_FLUSH_MASK                             0x1F00000
+#define DMA0_QM_GLBL_CFG1_CP_FLUSH_SHIFT                             25
+#define DMA0_QM_GLBL_CFG1_CP_FLUSH_MASK                              0x3E000000
+
+/* DMA0_QM_GLBL_PROT */
+#define DMA0_QM_GLBL_PROT_PQF_SHIFT                                  0
+#define DMA0_QM_GLBL_PROT_PQF_MASK                                   0xF
+#define DMA0_QM_GLBL_PROT_CQF_SHIFT                                  4
+#define DMA0_QM_GLBL_PROT_CQF_MASK                                   0x1F0
+#define DMA0_QM_GLBL_PROT_CP_SHIFT                                   9
+#define DMA0_QM_GLBL_PROT_CP_MASK                                    0x3E00
+#define DMA0_QM_GLBL_PROT_ERR_SHIFT                                  14
+#define DMA0_QM_GLBL_PROT_ERR_MASK                                   0x4000
+#define DMA0_QM_GLBL_PROT_ARB_SHIFT                                  15
+#define DMA0_QM_GLBL_PROT_ARB_MASK                                   0x8000
+
+/* DMA0_QM_GLBL_ERR_CFG */
+#define DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT                    0
+#define DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK                     0xF
+#define DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT                    4
+#define DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK                     0x1F0
+#define DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT                     9
+#define DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK                      0x3E00
+#define DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT                   16
+#define DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK                    0xF0000
+#define DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT                   20
+#define DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK                    0x1F00000
+#define DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT                    25
+#define DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK                     0x3E000000
+#define DMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT                   31
+#define DMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK                    0x80000000
+
+/* DMA0_QM_GLBL_SECURE_PROPS */
+#define DMA0_QM_GLBL_SECURE_PROPS_0_ASID_SHIFT                       0
+#define DMA0_QM_GLBL_SECURE_PROPS_0_ASID_MASK                        0x3FF
+#define DMA0_QM_GLBL_SECURE_PROPS_1_ASID_SHIFT                       0
+#define DMA0_QM_GLBL_SECURE_PROPS_1_ASID_MASK                        0x3FF
+#define DMA0_QM_GLBL_SECURE_PROPS_2_ASID_SHIFT                       0
+#define DMA0_QM_GLBL_SECURE_PROPS_2_ASID_MASK                        0x3FF
+#define DMA0_QM_GLBL_SECURE_PROPS_3_ASID_SHIFT                       0
+#define DMA0_QM_GLBL_SECURE_PROPS_3_ASID_MASK                        0x3FF
+#define DMA0_QM_GLBL_SECURE_PROPS_4_ASID_SHIFT                       0
+#define DMA0_QM_GLBL_SECURE_PROPS_4_ASID_MASK                        0x3FF
+#define DMA0_QM_GLBL_SECURE_PROPS_0_MMBP_SHIFT                       10
+#define DMA0_QM_GLBL_SECURE_PROPS_0_MMBP_MASK                        0x400
+#define DMA0_QM_GLBL_SECURE_PROPS_1_MMBP_SHIFT                       10
+#define DMA0_QM_GLBL_SECURE_PROPS_1_MMBP_MASK                        0x400
+#define DMA0_QM_GLBL_SECURE_PROPS_2_MMBP_SHIFT                       10
+#define DMA0_QM_GLBL_SECURE_PROPS_2_MMBP_MASK                        0x400
+#define DMA0_QM_GLBL_SECURE_PROPS_3_MMBP_SHIFT                       10
+#define DMA0_QM_GLBL_SECURE_PROPS_3_MMBP_MASK                        0x400
+#define DMA0_QM_GLBL_SECURE_PROPS_4_MMBP_SHIFT                       10
+#define DMA0_QM_GLBL_SECURE_PROPS_4_MMBP_MASK                        0x400
+
+/* DMA0_QM_GLBL_NON_SECURE_PROPS */
+#define DMA0_QM_GLBL_NON_SECURE_PROPS_0_ASID_SHIFT                   0
+#define DMA0_QM_GLBL_NON_SECURE_PROPS_0_ASID_MASK                    0x3FF
+#define DMA0_QM_GLBL_NON_SECURE_PROPS_1_ASID_SHIFT                   0
+#define DMA0_QM_GLBL_NON_SECURE_PROPS_1_ASID_MASK                    0x3FF
+#define DMA0_QM_GLBL_NON_SECURE_PROPS_2_ASID_SHIFT                   0
+#define DMA0_QM_GLBL_NON_SECURE_PROPS_2_ASID_MASK                    0x3FF
+#define DMA0_QM_GLBL_NON_SECURE_PROPS_3_ASID_SHIFT                   0
+#define DMA0_QM_GLBL_NON_SECURE_PROPS_3_ASID_MASK                    0x3FF
+#define DMA0_QM_GLBL_NON_SECURE_PROPS_4_ASID_SHIFT                   0
+#define DMA0_QM_GLBL_NON_SECURE_PROPS_4_ASID_MASK                    0x3FF
+#define DMA0_QM_GLBL_NON_SECURE_PROPS_0_MMBP_SHIFT                   10
+#define DMA0_QM_GLBL_NON_SECURE_PROPS_0_MMBP_MASK                    0x400
+#define DMA0_QM_GLBL_NON_SECURE_PROPS_1_MMBP_SHIFT                   10
+#define DMA0_QM_GLBL_NON_SECURE_PROPS_1_MMBP_MASK                    0x400
+#define DMA0_QM_GLBL_NON_SECURE_PROPS_2_MMBP_SHIFT                   10
+#define DMA0_QM_GLBL_NON_SECURE_PROPS_2_MMBP_MASK                    0x400
+#define DMA0_QM_GLBL_NON_SECURE_PROPS_3_MMBP_SHIFT                   10
+#define DMA0_QM_GLBL_NON_SECURE_PROPS_3_MMBP_MASK                    0x400
+#define DMA0_QM_GLBL_NON_SECURE_PROPS_4_MMBP_SHIFT                   10
+#define DMA0_QM_GLBL_NON_SECURE_PROPS_4_MMBP_MASK                    0x400
+
+/* DMA0_QM_GLBL_STS0 */
+#define DMA0_QM_GLBL_STS0_PQF_IDLE_SHIFT                             0
+#define DMA0_QM_GLBL_STS0_PQF_IDLE_MASK                              0xF
+#define DMA0_QM_GLBL_STS0_CQF_IDLE_SHIFT                             4
+#define DMA0_QM_GLBL_STS0_CQF_IDLE_MASK                              0x1F0
+#define DMA0_QM_GLBL_STS0_CP_IDLE_SHIFT                              9
+#define DMA0_QM_GLBL_STS0_CP_IDLE_MASK                               0x3E00
+#define DMA0_QM_GLBL_STS0_PQF_IS_STOP_SHIFT                          16
+#define DMA0_QM_GLBL_STS0_PQF_IS_STOP_MASK                           0xF0000
+#define DMA0_QM_GLBL_STS0_CQF_IS_STOP_SHIFT                          20
+#define DMA0_QM_GLBL_STS0_CQF_IS_STOP_MASK                           0x1F00000
+#define DMA0_QM_GLBL_STS0_CP_IS_STOP_SHIFT                           25
+#define DMA0_QM_GLBL_STS0_CP_IS_STOP_MASK                            0x3E000000
+#define DMA0_QM_GLBL_STS0_ARB_IS_STOP_SHIFT                          31
+#define DMA0_QM_GLBL_STS0_ARB_IS_STOP_MASK                           0x80000000
+
+/* DMA0_QM_GLBL_STS1 */
+#define DMA0_QM_GLBL_STS1_PQF_RD_ERR_SHIFT                           0
+#define DMA0_QM_GLBL_STS1_PQF_RD_ERR_MASK                            0x1
+#define DMA0_QM_GLBL_STS1_CQF_RD_ERR_SHIFT                           1
+#define DMA0_QM_GLBL_STS1_CQF_RD_ERR_MASK                            0x2
+#define DMA0_QM_GLBL_STS1_CP_RD_ERR_SHIFT                            2
+#define DMA0_QM_GLBL_STS1_CP_RD_ERR_MASK                             0x4
+#define DMA0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT                     3
+#define DMA0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK                      0x8
+#define DMA0_QM_GLBL_STS1_CP_STOP_OP_SHIFT                           4
+#define DMA0_QM_GLBL_STS1_CP_STOP_OP_MASK                            0x10
+#define DMA0_QM_GLBL_STS1_CP_MSG_WR_ERR_SHIFT                        5
+#define DMA0_QM_GLBL_STS1_CP_MSG_WR_ERR_MASK                         0x20
+#define DMA0_QM_GLBL_STS1_CP_WREG_ERR_SHIFT                          6
+#define DMA0_QM_GLBL_STS1_CP_WREG_ERR_MASK                           0x40
+#define DMA0_QM_GLBL_STS1_CP_FENCE0_OVF_ERR_SHIFT                    8
+#define DMA0_QM_GLBL_STS1_CP_FENCE0_OVF_ERR_MASK                     0x100
+#define DMA0_QM_GLBL_STS1_CP_FENCE1_OVF_ERR_SHIFT                    9
+#define DMA0_QM_GLBL_STS1_CP_FENCE1_OVF_ERR_MASK                     0x200
+#define DMA0_QM_GLBL_STS1_CP_FENCE2_OVF_ERR_SHIFT                    10
+#define DMA0_QM_GLBL_STS1_CP_FENCE2_OVF_ERR_MASK                     0x400
+#define DMA0_QM_GLBL_STS1_CP_FENCE3_OVF_ERR_SHIFT                    11
+#define DMA0_QM_GLBL_STS1_CP_FENCE3_OVF_ERR_MASK                     0x800
+#define DMA0_QM_GLBL_STS1_CP_FENCE0_UDF_ERR_SHIFT                    12
+#define DMA0_QM_GLBL_STS1_CP_FENCE0_UDF_ERR_MASK                     0x1000
+#define DMA0_QM_GLBL_STS1_CP_FENCE1_UDF_ERR_SHIFT                    13
+#define DMA0_QM_GLBL_STS1_CP_FENCE1_UDF_ERR_MASK                     0x2000
+#define DMA0_QM_GLBL_STS1_CP_FENCE2_UDF_ERR_SHIFT                    14
+#define DMA0_QM_GLBL_STS1_CP_FENCE2_UDF_ERR_MASK                     0x4000
+#define DMA0_QM_GLBL_STS1_CP_FENCE3_UDF_ERR_SHIFT                    15
+#define DMA0_QM_GLBL_STS1_CP_FENCE3_UDF_ERR_MASK                     0x8000
+
+/* DMA0_QM_GLBL_STS1_4 */
+#define DMA0_QM_GLBL_STS1_4_CQF_RD_ERR_SHIFT                         1
+#define DMA0_QM_GLBL_STS1_4_CQF_RD_ERR_MASK                          0x2
+#define DMA0_QM_GLBL_STS1_4_CP_RD_ERR_SHIFT                          2
+#define DMA0_QM_GLBL_STS1_4_CP_RD_ERR_MASK                           0x4
+#define DMA0_QM_GLBL_STS1_4_CP_UNDEF_CMD_ERR_SHIFT                   3
+#define DMA0_QM_GLBL_STS1_4_CP_UNDEF_CMD_ERR_MASK                    0x8
+#define DMA0_QM_GLBL_STS1_4_CP_STOP_OP_SHIFT                         4
+#define DMA0_QM_GLBL_STS1_4_CP_STOP_OP_MASK                          0x10
+#define DMA0_QM_GLBL_STS1_4_CP_MSG_WR_ERR_SHIFT                      5
+#define DMA0_QM_GLBL_STS1_4_CP_MSG_WR_ERR_MASK                       0x20
+#define DMA0_QM_GLBL_STS1_4_CP_WREG_ERR_SHIFT                        6
+#define DMA0_QM_GLBL_STS1_4_CP_WREG_ERR_MASK                         0x40
+#define DMA0_QM_GLBL_STS1_4_CP_FENCE0_OVF_ERR_SHIFT                  8
+#define DMA0_QM_GLBL_STS1_4_CP_FENCE0_OVF_ERR_MASK                   0x100
+#define DMA0_QM_GLBL_STS1_4_CP_FENCE1_OVF_ERR_SHIFT                  9
+#define DMA0_QM_GLBL_STS1_4_CP_FENCE1_OVF_ERR_MASK                   0x200
+#define DMA0_QM_GLBL_STS1_4_CP_FENCE2_OVF_ERR_SHIFT                  10
+#define DMA0_QM_GLBL_STS1_4_CP_FENCE2_OVF_ERR_MASK                   0x400
+#define DMA0_QM_GLBL_STS1_4_CP_FENCE3_OVF_ERR_SHIFT                  11
+#define DMA0_QM_GLBL_STS1_4_CP_FENCE3_OVF_ERR_MASK                   0x800
+#define DMA0_QM_GLBL_STS1_4_CP_FENCE0_UDF_ERR_SHIFT                  12
+#define DMA0_QM_GLBL_STS1_4_CP_FENCE0_UDF_ERR_MASK                   0x1000
+#define DMA0_QM_GLBL_STS1_4_CP_FENCE1_UDF_ERR_SHIFT                  13
+#define DMA0_QM_GLBL_STS1_4_CP_FENCE1_UDF_ERR_MASK                   0x2000
+#define DMA0_QM_GLBL_STS1_4_CP_FENCE2_UDF_ERR_SHIFT                  14
+#define DMA0_QM_GLBL_STS1_4_CP_FENCE2_UDF_ERR_MASK                   0x4000
+#define DMA0_QM_GLBL_STS1_4_CP_FENCE3_UDF_ERR_SHIFT                  15
+#define DMA0_QM_GLBL_STS1_4_CP_FENCE3_UDF_ERR_MASK                   0x8000
+
+/* DMA0_QM_GLBL_MSG_EN */
+#define DMA0_QM_GLBL_MSG_EN_PQF_RD_ERR_SHIFT                         0
+#define DMA0_QM_GLBL_MSG_EN_PQF_RD_ERR_MASK                          0x1
+#define DMA0_QM_GLBL_MSG_EN_CQF_RD_ERR_SHIFT                         1
+#define DMA0_QM_GLBL_MSG_EN_CQF_RD_ERR_MASK                          0x2
+#define DMA0_QM_GLBL_MSG_EN_CP_RD_ERR_SHIFT                          2
+#define DMA0_QM_GLBL_MSG_EN_CP_RD_ERR_MASK                           0x4
+#define DMA0_QM_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_SHIFT                   3
+#define DMA0_QM_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_MASK                    0x8
+#define DMA0_QM_GLBL_MSG_EN_CP_STOP_OP_SHIFT                         4
+#define DMA0_QM_GLBL_MSG_EN_CP_STOP_OP_MASK                          0x10
+#define DMA0_QM_GLBL_MSG_EN_CP_MSG_WR_ERR_SHIFT                      5
+#define DMA0_QM_GLBL_MSG_EN_CP_MSG_WR_ERR_MASK                       0x20
+#define DMA0_QM_GLBL_MSG_EN_CP_WREG_ERR_SHIFT                        6
+#define DMA0_QM_GLBL_MSG_EN_CP_WREG_ERR_MASK                         0x40
+#define DMA0_QM_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_SHIFT                  8
+#define DMA0_QM_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_MASK                   0x100
+#define DMA0_QM_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_SHIFT                  9
+#define DMA0_QM_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_MASK                   0x200
+#define DMA0_QM_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_SHIFT                  10
+#define DMA0_QM_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_MASK                   0x400
+#define DMA0_QM_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_SHIFT                  11
+#define DMA0_QM_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_MASK                   0x800
+#define DMA0_QM_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_SHIFT                  12
+#define DMA0_QM_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_MASK                   0x1000
+#define DMA0_QM_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_SHIFT                  13
+#define DMA0_QM_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_MASK                   0x2000
+#define DMA0_QM_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_SHIFT                  14
+#define DMA0_QM_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_MASK                   0x4000
+#define DMA0_QM_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_SHIFT                  15
+#define DMA0_QM_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_MASK                   0x8000
+
+/* DMA0_QM_GLBL_MSG_EN_4 */
+#define DMA0_QM_GLBL_MSG_EN_4_CQF_RD_ERR_SHIFT                       1
+#define DMA0_QM_GLBL_MSG_EN_4_CQF_RD_ERR_MASK                        0x2
+#define DMA0_QM_GLBL_MSG_EN_4_CP_RD_ERR_SHIFT                        2
+#define DMA0_QM_GLBL_MSG_EN_4_CP_RD_ERR_MASK                         0x4
+#define DMA0_QM_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_SHIFT                 3
+#define DMA0_QM_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_MASK                  0x8
+#define DMA0_QM_GLBL_MSG_EN_4_CP_STOP_OP_SHIFT                       4
+#define DMA0_QM_GLBL_MSG_EN_4_CP_STOP_OP_MASK                        0x10
+#define DMA0_QM_GLBL_MSG_EN_4_CP_MSG_WR_ERR_SHIFT                    5
+#define DMA0_QM_GLBL_MSG_EN_4_CP_MSG_WR_ERR_MASK                     0x20
+#define DMA0_QM_GLBL_MSG_EN_4_CP_WREG_ERR_SHIFT                      6
+#define DMA0_QM_GLBL_MSG_EN_4_CP_WREG_ERR_MASK                       0x40
+#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_SHIFT                8
+#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_MASK                 0x100
+#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_SHIFT                9
+#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_MASK                 0x200
+#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_SHIFT                10
+#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_MASK                 0x400
+#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_SHIFT                11
+#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_MASK                 0x800
+#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_SHIFT                12
+#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_MASK                 0x1000
+#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_SHIFT                13
+#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_MASK                 0x2000
+#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_SHIFT                14
+#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_MASK                 0x4000
+#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_SHIFT                15
+#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_MASK                 0x8000
+
+/* DMA0_QM_PQ_BASE_LO */
+#define DMA0_QM_PQ_BASE_LO_VAL_SHIFT                                 0
+#define DMA0_QM_PQ_BASE_LO_VAL_MASK                                  0xFFFFFFFF
+
+/* DMA0_QM_PQ_BASE_HI */
+#define DMA0_QM_PQ_BASE_HI_VAL_SHIFT                                 0
+#define DMA0_QM_PQ_BASE_HI_VAL_MASK                                  0xFFFFFFFF
+
+/* DMA0_QM_PQ_SIZE */
+#define DMA0_QM_PQ_SIZE_VAL_SHIFT                                    0
+#define DMA0_QM_PQ_SIZE_VAL_MASK                                     0xFFFFFFFF
+
+/* DMA0_QM_PQ_PI */
+#define DMA0_QM_PQ_PI_VAL_SHIFT                                      0
+#define DMA0_QM_PQ_PI_VAL_MASK                                       0xFFFFFFFF
+
+/* DMA0_QM_PQ_CI */
+#define DMA0_QM_PQ_CI_VAL_SHIFT                                      0
+#define DMA0_QM_PQ_CI_VAL_MASK                                       0xFFFFFFFF
+
+/* DMA0_QM_PQ_CFG0 */
+#define DMA0_QM_PQ_CFG0_RESERVED_SHIFT                               0
+#define DMA0_QM_PQ_CFG0_RESERVED_MASK                                0x1
+
+/* DMA0_QM_PQ_CFG1 */
+#define DMA0_QM_PQ_CFG1_CREDIT_LIM_SHIFT                             0
+#define DMA0_QM_PQ_CFG1_CREDIT_LIM_MASK                              0xFFFF
+#define DMA0_QM_PQ_CFG1_MAX_INFLIGHT_SHIFT                           16
+#define DMA0_QM_PQ_CFG1_MAX_INFLIGHT_MASK                            0xFFFF0000
+
+/* DMA0_QM_PQ_ARUSER_31_11 */
+#define DMA0_QM_PQ_ARUSER_31_11_VAL_SHIFT                            0
+#define DMA0_QM_PQ_ARUSER_31_11_VAL_MASK                             0x1FFFFF
+
+/* DMA0_QM_PQ_STS0 */
+#define DMA0_QM_PQ_STS0_PQ_CREDIT_CNT_SHIFT                          0
+#define DMA0_QM_PQ_STS0_PQ_CREDIT_CNT_MASK                           0xFFFF
+#define DMA0_QM_PQ_STS0_PQ_FREE_CNT_SHIFT                            16
+#define DMA0_QM_PQ_STS0_PQ_FREE_CNT_MASK                             0xFFFF0000
+
+/* DMA0_QM_PQ_STS1 */
+#define DMA0_QM_PQ_STS1_PQ_INFLIGHT_CNT_SHIFT                        0
+#define DMA0_QM_PQ_STS1_PQ_INFLIGHT_CNT_MASK                         0xFFFF
+#define DMA0_QM_PQ_STS1_PQ_BUF_EMPTY_SHIFT                           30
+#define DMA0_QM_PQ_STS1_PQ_BUF_EMPTY_MASK                            0x40000000
+#define DMA0_QM_PQ_STS1_PQ_BUSY_SHIFT                                31
+#define DMA0_QM_PQ_STS1_PQ_BUSY_MASK                                 0x80000000
+
+/* DMA0_QM_CQ_CFG0 */
+#define DMA0_QM_CQ_CFG0_RESERVED_SHIFT                               0
+#define DMA0_QM_CQ_CFG0_RESERVED_MASK                                0x1
+
+/* DMA0_QM_CQ_CFG1 */
+#define DMA0_QM_CQ_CFG1_CREDIT_LIM_SHIFT                             0
+#define DMA0_QM_CQ_CFG1_CREDIT_LIM_MASK                              0xFFFF
+#define DMA0_QM_CQ_CFG1_MAX_INFLIGHT_SHIFT                           16
+#define DMA0_QM_CQ_CFG1_MAX_INFLIGHT_MASK                            0xFFFF0000
+
+/* DMA0_QM_CQ_ARUSER_31_11 */
+#define DMA0_QM_CQ_ARUSER_31_11_VAL_SHIFT                            0
+#define DMA0_QM_CQ_ARUSER_31_11_VAL_MASK                             0x1FFFFF
+
+/* DMA0_QM_CQ_STS0 */
+#define DMA0_QM_CQ_STS0_CQ_CREDIT_CNT_SHIFT                          0
+#define DMA0_QM_CQ_STS0_CQ_CREDIT_CNT_MASK                           0xFFFF
+#define DMA0_QM_CQ_STS0_CQ_FREE_CNT_SHIFT                            16
+#define DMA0_QM_CQ_STS0_CQ_FREE_CNT_MASK                             0xFFFF0000
+
+/* DMA0_QM_CQ_STS1 */
+#define DMA0_QM_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT                        0
+#define DMA0_QM_CQ_STS1_CQ_INFLIGHT_CNT_MASK                         0xFFFF
+#define DMA0_QM_CQ_STS1_CQ_BUF_EMPTY_SHIFT                           30
+#define DMA0_QM_CQ_STS1_CQ_BUF_EMPTY_MASK                            0x40000000
+#define DMA0_QM_CQ_STS1_CQ_BUSY_SHIFT                                31
+#define DMA0_QM_CQ_STS1_CQ_BUSY_MASK                                 0x80000000
+
+/* DMA0_QM_CQ_PTR_LO_0 */
+#define DMA0_QM_CQ_PTR_LO_0_VAL_SHIFT                                0
+#define DMA0_QM_CQ_PTR_LO_0_VAL_MASK                                 0xFFFFFFFF
+
+/* DMA0_QM_CQ_PTR_HI_0 */
+#define DMA0_QM_CQ_PTR_HI_0_VAL_SHIFT                                0
+#define DMA0_QM_CQ_PTR_HI_0_VAL_MASK                                 0xFFFFFFFF
+
+/* DMA0_QM_CQ_TSIZE_0 */
+#define DMA0_QM_CQ_TSIZE_0_VAL_SHIFT                                 0
+#define DMA0_QM_CQ_TSIZE_0_VAL_MASK                                  0xFFFFFFFF
+
+/* DMA0_QM_CQ_CTL_0 */
+#define DMA0_QM_CQ_CTL_0_RPT_SHIFT                                   0
+#define DMA0_QM_CQ_CTL_0_RPT_MASK                                    0xFFFF
+#define DMA0_QM_CQ_CTL_0_CTL_SHIFT                                   16
+#define DMA0_QM_CQ_CTL_0_CTL_MASK                                    0xFFFF0000
+
+/* DMA0_QM_CQ_PTR_LO_1 */
+#define DMA0_QM_CQ_PTR_LO_1_VAL_SHIFT                                0
+#define DMA0_QM_CQ_PTR_LO_1_VAL_MASK                                 0xFFFFFFFF
+
+/* DMA0_QM_CQ_PTR_HI_1 */
+#define DMA0_QM_CQ_PTR_HI_1_VAL_SHIFT                                0
+#define DMA0_QM_CQ_PTR_HI_1_VAL_MASK                                 0xFFFFFFFF
+
+/* DMA0_QM_CQ_TSIZE_1 */
+#define DMA0_QM_CQ_TSIZE_1_VAL_SHIFT                                 0
+#define DMA0_QM_CQ_TSIZE_1_VAL_MASK                                  0xFFFFFFFF
+
+/* DMA0_QM_CQ_CTL_1 */
+#define DMA0_QM_CQ_CTL_1_RPT_SHIFT                                   0
+#define DMA0_QM_CQ_CTL_1_RPT_MASK                                    0xFFFF
+#define DMA0_QM_CQ_CTL_1_CTL_SHIFT                                   16
+#define DMA0_QM_CQ_CTL_1_CTL_MASK                                    0xFFFF0000
+
+/* DMA0_QM_CQ_PTR_LO_2 */
+#define DMA0_QM_CQ_PTR_LO_2_VAL_SHIFT                                0
+#define DMA0_QM_CQ_PTR_LO_2_VAL_MASK                                 0xFFFFFFFF
+
+/* DMA0_QM_CQ_PTR_HI_2 */
+#define DMA0_QM_CQ_PTR_HI_2_VAL_SHIFT                                0
+#define DMA0_QM_CQ_PTR_HI_2_VAL_MASK                                 0xFFFFFFFF
+
+/* DMA0_QM_CQ_TSIZE_2 */
+#define DMA0_QM_CQ_TSIZE_2_VAL_SHIFT                                 0
+#define DMA0_QM_CQ_TSIZE_2_VAL_MASK                                  0xFFFFFFFF
+
+/* DMA0_QM_CQ_CTL_2 */
+#define DMA0_QM_CQ_CTL_2_RPT_SHIFT                                   0
+#define DMA0_QM_CQ_CTL_2_RPT_MASK                                    0xFFFF
+#define DMA0_QM_CQ_CTL_2_CTL_SHIFT                                   16
+#define DMA0_QM_CQ_CTL_2_CTL_MASK                                    0xFFFF0000
+
+/* DMA0_QM_CQ_PTR_LO_3 */
+#define DMA0_QM_CQ_PTR_LO_3_VAL_SHIFT                                0
+#define DMA0_QM_CQ_PTR_LO_3_VAL_MASK                                 0xFFFFFFFF
+
+/* DMA0_QM_CQ_PTR_HI_3 */
+#define DMA0_QM_CQ_PTR_HI_3_VAL_SHIFT                                0
+#define DMA0_QM_CQ_PTR_HI_3_VAL_MASK                                 0xFFFFFFFF
+
+/* DMA0_QM_CQ_TSIZE_3 */
+#define DMA0_QM_CQ_TSIZE_3_VAL_SHIFT                                 0
+#define DMA0_QM_CQ_TSIZE_3_VAL_MASK                                  0xFFFFFFFF
+
+/* DMA0_QM_CQ_CTL_3 */
+#define DMA0_QM_CQ_CTL_3_RPT_SHIFT                                   0
+#define DMA0_QM_CQ_CTL_3_RPT_MASK                                    0xFFFF
+#define DMA0_QM_CQ_CTL_3_CTL_SHIFT                                   16
+#define DMA0_QM_CQ_CTL_3_CTL_MASK                                    0xFFFF0000
+
+/* DMA0_QM_CQ_PTR_LO_4 */
+#define DMA0_QM_CQ_PTR_LO_4_VAL_SHIFT                                0
+#define DMA0_QM_CQ_PTR_LO_4_VAL_MASK                                 0xFFFFFFFF
+
+/* DMA0_QM_CQ_PTR_HI_4 */
+#define DMA0_QM_CQ_PTR_HI_4_VAL_SHIFT                                0
+#define DMA0_QM_CQ_PTR_HI_4_VAL_MASK                                 0xFFFFFFFF
+
+/* DMA0_QM_CQ_TSIZE_4 */
+#define DMA0_QM_CQ_TSIZE_4_VAL_SHIFT                                 0
+#define DMA0_QM_CQ_TSIZE_4_VAL_MASK                                  0xFFFFFFFF
+
+/* DMA0_QM_CQ_CTL_4 */
+#define DMA0_QM_CQ_CTL_4_RPT_SHIFT                                   0
+#define DMA0_QM_CQ_CTL_4_RPT_MASK                                    0xFFFF
+#define DMA0_QM_CQ_CTL_4_CTL_SHIFT                                   16
+#define DMA0_QM_CQ_CTL_4_CTL_MASK                                    0xFFFF0000
+
+/* DMA0_QM_CQ_PTR_LO_STS */
+#define DMA0_QM_CQ_PTR_LO_STS_VAL_SHIFT                              0
+#define DMA0_QM_CQ_PTR_LO_STS_VAL_MASK                               0xFFFFFFFF
+
+/* DMA0_QM_CQ_PTR_HI_STS */
+#define DMA0_QM_CQ_PTR_HI_STS_VAL_SHIFT                              0
+#define DMA0_QM_CQ_PTR_HI_STS_VAL_MASK                               0xFFFFFFFF
+
+/* DMA0_QM_CQ_TSIZE_STS */
+#define DMA0_QM_CQ_TSIZE_STS_VAL_SHIFT                               0
+#define DMA0_QM_CQ_TSIZE_STS_VAL_MASK                                0xFFFFFFFF
+
+/* DMA0_QM_CQ_CTL_STS */
+#define DMA0_QM_CQ_CTL_STS_RPT_SHIFT                                 0
+#define DMA0_QM_CQ_CTL_STS_RPT_MASK                                  0xFFFF
+#define DMA0_QM_CQ_CTL_STS_CTL_SHIFT                                 16
+#define DMA0_QM_CQ_CTL_STS_CTL_MASK                                  0xFFFF0000
+
+/* DMA0_QM_CQ_IFIFO_CNT */
+#define DMA0_QM_CQ_IFIFO_CNT_VAL_SHIFT                               0
+#define DMA0_QM_CQ_IFIFO_CNT_VAL_MASK                                0x3
+
+/* DMA0_QM_CP_MSG_BASE0_ADDR_LO */
+#define DMA0_QM_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT                       0
+#define DMA0_QM_CP_MSG_BASE0_ADDR_LO_VAL_MASK                        0xFFFFFFFF
+
+/* DMA0_QM_CP_MSG_BASE0_ADDR_HI */
+#define DMA0_QM_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT                       0
+#define DMA0_QM_CP_MSG_BASE0_ADDR_HI_VAL_MASK                        0xFFFFFFFF
+
+/* DMA0_QM_CP_MSG_BASE1_ADDR_LO */
+#define DMA0_QM_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT                       0
+#define DMA0_QM_CP_MSG_BASE1_ADDR_LO_VAL_MASK                        0xFFFFFFFF
+
+/* DMA0_QM_CP_MSG_BASE1_ADDR_HI */
+#define DMA0_QM_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT                       0
+#define DMA0_QM_CP_MSG_BASE1_ADDR_HI_VAL_MASK                        0xFFFFFFFF
+
+/* DMA0_QM_CP_MSG_BASE2_ADDR_LO */
+#define DMA0_QM_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT                       0
+#define DMA0_QM_CP_MSG_BASE2_ADDR_LO_VAL_MASK                        0xFFFFFFFF
+
+/* DMA0_QM_CP_MSG_BASE2_ADDR_HI */
+#define DMA0_QM_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT                       0
+#define DMA0_QM_CP_MSG_BASE2_ADDR_HI_VAL_MASK                        0xFFFFFFFF
+
+/* DMA0_QM_CP_MSG_BASE3_ADDR_LO */
+#define DMA0_QM_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT                       0
+#define DMA0_QM_CP_MSG_BASE3_ADDR_LO_VAL_MASK                        0xFFFFFFFF
+
+/* DMA0_QM_CP_MSG_BASE3_ADDR_HI */
+#define DMA0_QM_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT                       0
+#define DMA0_QM_CP_MSG_BASE3_ADDR_HI_VAL_MASK                        0xFFFFFFFF
+
+/* DMA0_QM_CP_LDMA_TSIZE_OFFSET */
+#define DMA0_QM_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT                       0
+#define DMA0_QM_CP_LDMA_TSIZE_OFFSET_VAL_MASK                        0xFFFFFFFF
+
+/* DMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET */
+#define DMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT                 0
+#define DMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK                  0xFFFFFFFF
+
+/* DMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET */
+#define DMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT                 0
+#define DMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK                  0xFFFFFFFF
+
+/* DMA0_QM_CP_FENCE0_RDATA */
+#define DMA0_QM_CP_FENCE0_RDATA_INC_VAL_SHIFT                        0
+#define DMA0_QM_CP_FENCE0_RDATA_INC_VAL_MASK                         0xF
+
+/* DMA0_QM_CP_FENCE1_RDATA */
+#define DMA0_QM_CP_FENCE1_RDATA_INC_VAL_SHIFT                        0
+#define DMA0_QM_CP_FENCE1_RDATA_INC_VAL_MASK                         0xF
+
+/* DMA0_QM_CP_FENCE2_RDATA */
+#define DMA0_QM_CP_FENCE2_RDATA_INC_VAL_SHIFT                        0
+#define DMA0_QM_CP_FENCE2_RDATA_INC_VAL_MASK                         0xF
+
+/* DMA0_QM_CP_FENCE3_RDATA */
+#define DMA0_QM_CP_FENCE3_RDATA_INC_VAL_SHIFT                        0
+#define DMA0_QM_CP_FENCE3_RDATA_INC_VAL_MASK                         0xF
+
+/* DMA0_QM_CP_FENCE0_CNT */
+#define DMA0_QM_CP_FENCE0_CNT_VAL_SHIFT                              0
+#define DMA0_QM_CP_FENCE0_CNT_VAL_MASK                               0x3FFF
+
+/* DMA0_QM_CP_FENCE1_CNT */
+#define DMA0_QM_CP_FENCE1_CNT_VAL_SHIFT                              0
+#define DMA0_QM_CP_FENCE1_CNT_VAL_MASK                               0x3FFF
+
+/* DMA0_QM_CP_FENCE2_CNT */
+#define DMA0_QM_CP_FENCE2_CNT_VAL_SHIFT                              0
+#define DMA0_QM_CP_FENCE2_CNT_VAL_MASK                               0x3FFF
+
+/* DMA0_QM_CP_FENCE3_CNT */
+#define DMA0_QM_CP_FENCE3_CNT_VAL_SHIFT                              0
+#define DMA0_QM_CP_FENCE3_CNT_VAL_MASK                               0x3FFF
+
+/* DMA0_QM_CP_STS */
+#define DMA0_QM_CP_STS_MSG_INFLIGHT_CNT_SHIFT                        0
+#define DMA0_QM_CP_STS_MSG_INFLIGHT_CNT_MASK                         0xFFFF
+#define DMA0_QM_CP_STS_ERDY_SHIFT                                    16
+#define DMA0_QM_CP_STS_ERDY_MASK                                     0x10000
+#define DMA0_QM_CP_STS_RRDY_SHIFT                                    17
+#define DMA0_QM_CP_STS_RRDY_MASK                                     0x20000
+#define DMA0_QM_CP_STS_MRDY_SHIFT                                    18
+#define DMA0_QM_CP_STS_MRDY_MASK                                     0x40000
+#define DMA0_QM_CP_STS_SW_STOP_SHIFT                                 19
+#define DMA0_QM_CP_STS_SW_STOP_MASK                                  0x80000
+#define DMA0_QM_CP_STS_FENCE_ID_SHIFT                                20
+#define DMA0_QM_CP_STS_FENCE_ID_MASK                                 0x300000
+#define DMA0_QM_CP_STS_FENCE_IN_PROGRESS_SHIFT                       22
+#define DMA0_QM_CP_STS_FENCE_IN_PROGRESS_MASK                        0x400000
+
+/* DMA0_QM_CP_CURRENT_INST_LO */
+#define DMA0_QM_CP_CURRENT_INST_LO_VAL_SHIFT                         0
+#define DMA0_QM_CP_CURRENT_INST_LO_VAL_MASK                          0xFFFFFFFF
+
+/* DMA0_QM_CP_CURRENT_INST_HI */
+#define DMA0_QM_CP_CURRENT_INST_HI_VAL_SHIFT                         0
+#define DMA0_QM_CP_CURRENT_INST_HI_VAL_MASK                          0xFFFFFFFF
+
+/* DMA0_QM_CP_BARRIER_CFG */
+#define DMA0_QM_CP_BARRIER_CFG_EBGUARD_SHIFT                         0
+#define DMA0_QM_CP_BARRIER_CFG_EBGUARD_MASK                          0xFFF
+#define DMA0_QM_CP_BARRIER_CFG_RBGUARD_SHIFT                         16
+#define DMA0_QM_CP_BARRIER_CFG_RBGUARD_MASK                          0xF0000
+
+/* DMA0_QM_CP_DBG_0 */
+#define DMA0_QM_CP_DBG_0_CS_SHIFT                                    0
+#define DMA0_QM_CP_DBG_0_CS_MASK                                     0xF
+#define DMA0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_SHIFT                       4
+#define DMA0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_MASK                        0x10
+#define DMA0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_SHIFT                     5
+#define DMA0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_MASK                      0x20
+#define DMA0_QM_CP_DBG_0_MREB_STALL_SHIFT                            6
+#define DMA0_QM_CP_DBG_0_MREB_STALL_MASK                             0x40
+#define DMA0_QM_CP_DBG_0_STALL_SHIFT                                 7
+#define DMA0_QM_CP_DBG_0_STALL_MASK                                  0x80
+
+/* DMA0_QM_CP_ARUSER_31_11 */
+#define DMA0_QM_CP_ARUSER_31_11_VAL_SHIFT                            0
+#define DMA0_QM_CP_ARUSER_31_11_VAL_MASK                             0x1FFFFF
+
+/* DMA0_QM_CP_AWUSER_31_11 */
+#define DMA0_QM_CP_AWUSER_31_11_VAL_SHIFT                            0
+#define DMA0_QM_CP_AWUSER_31_11_VAL_MASK                             0x1FFFFF
+
+/* DMA0_QM_ARB_CFG_0 */
+#define DMA0_QM_ARB_CFG_0_TYPE_SHIFT                                 0
+#define DMA0_QM_ARB_CFG_0_TYPE_MASK                                  0x1
+#define DMA0_QM_ARB_CFG_0_IS_MASTER_SHIFT                            4
+#define DMA0_QM_ARB_CFG_0_IS_MASTER_MASK                             0x10
+#define DMA0_QM_ARB_CFG_0_EN_SHIFT                                   8
+#define DMA0_QM_ARB_CFG_0_EN_MASK                                    0x100
+#define DMA0_QM_ARB_CFG_0_MASK_SHIFT                                 12
+#define DMA0_QM_ARB_CFG_0_MASK_MASK                                  0xF000
+#define DMA0_QM_ARB_CFG_0_MST_MSG_NOSTALL_SHIFT                      16
+#define DMA0_QM_ARB_CFG_0_MST_MSG_NOSTALL_MASK                       0x10000
+
+/* DMA0_QM_ARB_CHOISE_Q_PUSH */
+#define DMA0_QM_ARB_CHOISE_Q_PUSH_VAL_SHIFT                          0
+#define DMA0_QM_ARB_CHOISE_Q_PUSH_VAL_MASK                           0x3
+
+/* DMA0_QM_ARB_WRR_WEIGHT */
+#define DMA0_QM_ARB_WRR_WEIGHT_VAL_SHIFT                             0
+#define DMA0_QM_ARB_WRR_WEIGHT_VAL_MASK                              0xFFFFFFFF
+
+/* DMA0_QM_ARB_CFG_1 */
+#define DMA0_QM_ARB_CFG_1_CLR_SHIFT                                  0
+#define DMA0_QM_ARB_CFG_1_CLR_MASK                                   0x1
+
+/* DMA0_QM_ARB_MST_AVAIL_CRED */
+#define DMA0_QM_ARB_MST_AVAIL_CRED_VAL_SHIFT                         0
+#define DMA0_QM_ARB_MST_AVAIL_CRED_VAL_MASK                          0x7F
+
+/* DMA0_QM_ARB_MST_CRED_INC */
+#define DMA0_QM_ARB_MST_CRED_INC_VAL_SHIFT                           0
+#define DMA0_QM_ARB_MST_CRED_INC_VAL_MASK                            0xFFFFFFFF
+
+/* DMA0_QM_ARB_MST_CHOISE_PUSH_OFST */
+#define DMA0_QM_ARB_MST_CHOISE_PUSH_OFST_VAL_SHIFT                   0
+#define DMA0_QM_ARB_MST_CHOISE_PUSH_OFST_VAL_MASK                    0xFFFFFFFF
+
+/* DMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST */
+#define DMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_SHIFT               0
+#define DMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_MASK                0xFFFFFFFF
+
+/* DMA0_QM_ARB_MST_SLAVE_EN */
+#define DMA0_QM_ARB_MST_SLAVE_EN_VAL_SHIFT                           0
+#define DMA0_QM_ARB_MST_SLAVE_EN_VAL_MASK                            0xFFFFFFFF
+
+/* DMA0_QM_ARB_MST_QUIET_PER */
+#define DMA0_QM_ARB_MST_QUIET_PER_VAL_SHIFT                          0
+#define DMA0_QM_ARB_MST_QUIET_PER_VAL_MASK                           0xFFFFFFFF
+
+/* DMA0_QM_ARB_SLV_CHOISE_WDT */
+#define DMA0_QM_ARB_SLV_CHOISE_WDT_VAL_SHIFT                         0
+#define DMA0_QM_ARB_SLV_CHOISE_WDT_VAL_MASK                          0xFFFFFFFF
+
+/* DMA0_QM_ARB_SLV_ID */
+#define DMA0_QM_ARB_SLV_ID_VAL_SHIFT                                 0
+#define DMA0_QM_ARB_SLV_ID_VAL_MASK                                  0x1F
+
+/* DMA0_QM_ARB_MSG_MAX_INFLIGHT */
+#define DMA0_QM_ARB_MSG_MAX_INFLIGHT_VAL_SHIFT                       0
+#define DMA0_QM_ARB_MSG_MAX_INFLIGHT_VAL_MASK                        0x3F
+
+/* DMA0_QM_ARB_MSG_AWUSER_31_11 */
+#define DMA0_QM_ARB_MSG_AWUSER_31_11_VAL_SHIFT                       0
+#define DMA0_QM_ARB_MSG_AWUSER_31_11_VAL_MASK                        0x1FFFFF
+
+/* DMA0_QM_ARB_MSG_AWUSER_SEC_PROP */
+#define DMA0_QM_ARB_MSG_AWUSER_SEC_PROP_ASID_SHIFT                   0
+#define DMA0_QM_ARB_MSG_AWUSER_SEC_PROP_ASID_MASK                    0x3FF
+#define DMA0_QM_ARB_MSG_AWUSER_SEC_PROP_MMBP_SHIFT                   10
+#define DMA0_QM_ARB_MSG_AWUSER_SEC_PROP_MMBP_MASK                    0x400
+
+/* DMA0_QM_ARB_MSG_AWUSER_NON_SEC_PROP */
+#define DMA0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_SHIFT               0
+#define DMA0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_MASK                0x3FF
+#define DMA0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_SHIFT               10
+#define DMA0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_MASK                0x400
+
+/* DMA0_QM_ARB_BASE_LO */
+#define DMA0_QM_ARB_BASE_LO_VAL_SHIFT                                0
+#define DMA0_QM_ARB_BASE_LO_VAL_MASK                                 0xFFFFFFFF
+
+/* DMA0_QM_ARB_BASE_HI */
+#define DMA0_QM_ARB_BASE_HI_VAL_SHIFT                                0
+#define DMA0_QM_ARB_BASE_HI_VAL_MASK                                 0xFFFFFFFF
+
+/* DMA0_QM_ARB_STATE_STS */
+#define DMA0_QM_ARB_STATE_STS_VAL_SHIFT                              0
+#define DMA0_QM_ARB_STATE_STS_VAL_MASK                               0xFFFFFFFF
+
+/* DMA0_QM_ARB_CHOISE_FULLNESS_STS */
+#define DMA0_QM_ARB_CHOISE_FULLNESS_STS_VAL_SHIFT                    0
+#define DMA0_QM_ARB_CHOISE_FULLNESS_STS_VAL_MASK                     0x7F
+
+/* DMA0_QM_ARB_MSG_STS */
+#define DMA0_QM_ARB_MSG_STS_FULL_SHIFT                               0
+#define DMA0_QM_ARB_MSG_STS_FULL_MASK                                0x1
+#define DMA0_QM_ARB_MSG_STS_NO_INFLIGHT_SHIFT                        1
+#define DMA0_QM_ARB_MSG_STS_NO_INFLIGHT_MASK                         0x2
+
+/* DMA0_QM_ARB_SLV_CHOISE_Q_HEAD */
+#define DMA0_QM_ARB_SLV_CHOISE_Q_HEAD_VAL_SHIFT                      0
+#define DMA0_QM_ARB_SLV_CHOISE_Q_HEAD_VAL_MASK                       0x3
+
+/* DMA0_QM_ARB_ERR_CAUSE */
+#define DMA0_QM_ARB_ERR_CAUSE_CHOISE_OVF_SHIFT                       0
+#define DMA0_QM_ARB_ERR_CAUSE_CHOISE_OVF_MASK                        0x1
+#define DMA0_QM_ARB_ERR_CAUSE_CHOISE_WDT_SHIFT                       1
+#define DMA0_QM_ARB_ERR_CAUSE_CHOISE_WDT_MASK                        0x2
+#define DMA0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_SHIFT                      2
+#define DMA0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_MASK                       0x4
+
+/* DMA0_QM_ARB_ERR_MSG_EN */
+#define DMA0_QM_ARB_ERR_MSG_EN_CHOISE_OVF_SHIFT                      0
+#define DMA0_QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK                       0x1
+#define DMA0_QM_ARB_ERR_MSG_EN_CHOISE_WDT_SHIFT                      1
+#define DMA0_QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK                       0x2
+#define DMA0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_SHIFT                     2
+#define DMA0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK                      0x4
+
+/* DMA0_QM_ARB_ERR_STS_DRP */
+#define DMA0_QM_ARB_ERR_STS_DRP_VAL_SHIFT                            0
+#define DMA0_QM_ARB_ERR_STS_DRP_VAL_MASK                             0x3
+
+/* DMA0_QM_ARB_MST_CRED_STS */
+#define DMA0_QM_ARB_MST_CRED_STS_VAL_SHIFT                           0
+#define DMA0_QM_ARB_MST_CRED_STS_VAL_MASK                            0x7F
+
+/* DMA0_QM_CGM_CFG */
+#define DMA0_QM_CGM_CFG_IDLE_TH_SHIFT                                0
+#define DMA0_QM_CGM_CFG_IDLE_TH_MASK                                 0xFFF
+#define DMA0_QM_CGM_CFG_G2F_TH_SHIFT                                 16
+#define DMA0_QM_CGM_CFG_G2F_TH_MASK                                  0xFF0000
+#define DMA0_QM_CGM_CFG_CP_IDLE_MASK_SHIFT                           24
+#define DMA0_QM_CGM_CFG_CP_IDLE_MASK_MASK                            0x1F000000
+#define DMA0_QM_CGM_CFG_EN_SHIFT                                     31
+#define DMA0_QM_CGM_CFG_EN_MASK                                      0x80000000
+
+/* DMA0_QM_CGM_STS */
+#define DMA0_QM_CGM_STS_ST_SHIFT                                     0
+#define DMA0_QM_CGM_STS_ST_MASK                                      0x3
+#define DMA0_QM_CGM_STS_CG_SHIFT                                     4
+#define DMA0_QM_CGM_STS_CG_MASK                                      0x10
+#define DMA0_QM_CGM_STS_AGENT_IDLE_SHIFT                             8
+#define DMA0_QM_CGM_STS_AGENT_IDLE_MASK                              0x100
+#define DMA0_QM_CGM_STS_AXI_IDLE_SHIFT                               9
+#define DMA0_QM_CGM_STS_AXI_IDLE_MASK                                0x200
+#define DMA0_QM_CGM_STS_CP_IDLE_SHIFT                                10
+#define DMA0_QM_CGM_STS_CP_IDLE_MASK                                 0x400
+
+/* DMA0_QM_CGM_CFG1 */
+#define DMA0_QM_CGM_CFG1_MASK_TH_SHIFT                               0
+#define DMA0_QM_CGM_CFG1_MASK_TH_MASK                                0xFF
+
+/* DMA0_QM_LOCAL_RANGE_BASE */
+#define DMA0_QM_LOCAL_RANGE_BASE_VAL_SHIFT                           0
+#define DMA0_QM_LOCAL_RANGE_BASE_VAL_MASK                            0xFFFF
+
+/* DMA0_QM_LOCAL_RANGE_SIZE */
+#define DMA0_QM_LOCAL_RANGE_SIZE_VAL_SHIFT                           0
+#define DMA0_QM_LOCAL_RANGE_SIZE_VAL_MASK                            0xFFFF
+
+/* DMA0_QM_CSMR_STRICT_PRIO_CFG */
+#define DMA0_QM_CSMR_STRICT_PRIO_CFG_TYPE_SHIFT                      0
+#define DMA0_QM_CSMR_STRICT_PRIO_CFG_TYPE_MASK                       0x1
+
+/* DMA0_QM_HBW_RD_RATE_LIM_CFG_1 */
+#define DMA0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_SHIFT                     0
+#define DMA0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_MASK                      0xFF
+#define DMA0_QM_HBW_RD_RATE_LIM_CFG_1_EN_SHIFT                       31
+#define DMA0_QM_HBW_RD_RATE_LIM_CFG_1_EN_MASK                        0x80000000
+
+/* DMA0_QM_LBW_WR_RATE_LIM_CFG_0 */
+#define DMA0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT                0
+#define DMA0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK                 0xFF
+#define DMA0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_SHIFT                      16
+#define DMA0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_MASK                       0xFF0000
+
+/* DMA0_QM_LBW_WR_RATE_LIM_CFG_1 */
+#define DMA0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_SHIFT                     0
+#define DMA0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_MASK                      0xFF
+#define DMA0_QM_LBW_WR_RATE_LIM_CFG_1_EN_SHIFT                       31
+#define DMA0_QM_LBW_WR_RATE_LIM_CFG_1_EN_MASK                        0x80000000
+
+/* DMA0_QM_HBW_RD_RATE_LIM_CFG_0 */
+#define DMA0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT                0
+#define DMA0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK                 0xFF
+#define DMA0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_SHIFT                      16
+#define DMA0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_MASK                       0xFF0000
+
+/* DMA0_QM_GLBL_AXCACHE */
+#define DMA0_QM_GLBL_AXCACHE_AR_SHIFT                                0
+#define DMA0_QM_GLBL_AXCACHE_AR_MASK                                 0xF
+#define DMA0_QM_GLBL_AXCACHE_AW_SHIFT                                16
+#define DMA0_QM_GLBL_AXCACHE_AW_MASK                                 0xF0000
+
+/* DMA0_QM_IND_GW_APB_CFG */
+#define DMA0_QM_IND_GW_APB_CFG_ADDR_SHIFT                            0
+#define DMA0_QM_IND_GW_APB_CFG_ADDR_MASK                             0x7FFFFFFF
+#define DMA0_QM_IND_GW_APB_CFG_CMD_SHIFT                             31
+#define DMA0_QM_IND_GW_APB_CFG_CMD_MASK                              0x80000000
+
+/* DMA0_QM_IND_GW_APB_WDATA */
+#define DMA0_QM_IND_GW_APB_WDATA_VAL_SHIFT                           0
+#define DMA0_QM_IND_GW_APB_WDATA_VAL_MASK                            0xFFFFFFFF
+
+/* DMA0_QM_IND_GW_APB_RDATA */
+#define DMA0_QM_IND_GW_APB_RDATA_VAL_SHIFT                           0
+#define DMA0_QM_IND_GW_APB_RDATA_VAL_MASK                            0xFFFFFFFF
+
+/* DMA0_QM_IND_GW_APB_STATUS */
+#define DMA0_QM_IND_GW_APB_STATUS_RDY_SHIFT                          0
+#define DMA0_QM_IND_GW_APB_STATUS_RDY_MASK                           0x1
+#define DMA0_QM_IND_GW_APB_STATUS_ERR_SHIFT                          1
+#define DMA0_QM_IND_GW_APB_STATUS_ERR_MASK                           0x2
+
+/* DMA0_QM_GLBL_ERR_ADDR_LO */
+#define DMA0_QM_GLBL_ERR_ADDR_LO_VAL_SHIFT                           0
+#define DMA0_QM_GLBL_ERR_ADDR_LO_VAL_MASK                            0xFFFFFFFF
+
+/* DMA0_QM_GLBL_ERR_ADDR_HI */
+#define DMA0_QM_GLBL_ERR_ADDR_HI_VAL_SHIFT                           0
+#define DMA0_QM_GLBL_ERR_ADDR_HI_VAL_MASK                            0xFFFFFFFF
+
+/* DMA0_QM_GLBL_ERR_WDATA */
+#define DMA0_QM_GLBL_ERR_WDATA_VAL_SHIFT                             0
+#define DMA0_QM_GLBL_ERR_WDATA_VAL_MASK                              0xFFFFFFFF
+
+/* DMA0_QM_GLBL_MEM_INIT_BUSY */
+#define DMA0_QM_GLBL_MEM_INIT_BUSY_RBUF_SHIFT                        0
+#define DMA0_QM_GLBL_MEM_INIT_BUSY_RBUF_MASK                         0xF
+
+#endif /* ASIC_REG_DMA0_QM_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma0_qm_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma0_qm_regs.h
new file mode 100644
index 000000000000..8e56a93d88a1
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma0_qm_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DMA0_QM_REGS_H_
+#define ASIC_REG_DMA0_QM_REGS_H_
+
+/*
+ *****************************************
+ *   DMA0_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmDMA0_QM_GLBL_CFG0                                          0x508000
+
+#define mmDMA0_QM_GLBL_CFG1                                          0x508004
+
+#define mmDMA0_QM_GLBL_PROT                                          0x508008
+
+#define mmDMA0_QM_GLBL_ERR_CFG                                       0x50800C
+
+#define mmDMA0_QM_GLBL_SECURE_PROPS_0                                0x508010
+
+#define mmDMA0_QM_GLBL_SECURE_PROPS_1                                0x508014
+
+#define mmDMA0_QM_GLBL_SECURE_PROPS_2                                0x508018
+
+#define mmDMA0_QM_GLBL_SECURE_PROPS_3                                0x50801C
+
+#define mmDMA0_QM_GLBL_SECURE_PROPS_4                                0x508020
+
+#define mmDMA0_QM_GLBL_NON_SECURE_PROPS_0                            0x508024
+
+#define mmDMA0_QM_GLBL_NON_SECURE_PROPS_1                            0x508028
+
+#define mmDMA0_QM_GLBL_NON_SECURE_PROPS_2                            0x50802C
+
+#define mmDMA0_QM_GLBL_NON_SECURE_PROPS_3                            0x508030
+
+#define mmDMA0_QM_GLBL_NON_SECURE_PROPS_4                            0x508034
+
+#define mmDMA0_QM_GLBL_STS0                                          0x508038
+
+#define mmDMA0_QM_GLBL_STS1_0                                        0x508040
+
+#define mmDMA0_QM_GLBL_STS1_1                                        0x508044
+
+#define mmDMA0_QM_GLBL_STS1_2                                        0x508048
+
+#define mmDMA0_QM_GLBL_STS1_3                                        0x50804C
+
+#define mmDMA0_QM_GLBL_STS1_4                                        0x508050
+
+#define mmDMA0_QM_GLBL_MSG_EN_0                                      0x508054
+
+#define mmDMA0_QM_GLBL_MSG_EN_1                                      0x508058
+
+#define mmDMA0_QM_GLBL_MSG_EN_2                                      0x50805C
+
+#define mmDMA0_QM_GLBL_MSG_EN_3                                      0x508060
+
+#define mmDMA0_QM_GLBL_MSG_EN_4                                      0x508068
+
+#define mmDMA0_QM_PQ_BASE_LO_0                                       0x508070
+
+#define mmDMA0_QM_PQ_BASE_LO_1                                       0x508074
+
+#define mmDMA0_QM_PQ_BASE_LO_2                                       0x508078
+
+#define mmDMA0_QM_PQ_BASE_LO_3                                       0x50807C
+
+#define mmDMA0_QM_PQ_BASE_HI_0                                       0x508080
+
+#define mmDMA0_QM_PQ_BASE_HI_1                                       0x508084
+
+#define mmDMA0_QM_PQ_BASE_HI_2                                       0x508088
+
+#define mmDMA0_QM_PQ_BASE_HI_3                                       0x50808C
+
+#define mmDMA0_QM_PQ_SIZE_0                                          0x508090
+
+#define mmDMA0_QM_PQ_SIZE_1                                          0x508094
+
+#define mmDMA0_QM_PQ_SIZE_2                                          0x508098
+
+#define mmDMA0_QM_PQ_SIZE_3                                          0x50809C
+
+#define mmDMA0_QM_PQ_PI_0                                            0x5080A0
+
+#define mmDMA0_QM_PQ_PI_1                                            0x5080A4
+
+#define mmDMA0_QM_PQ_PI_2                                            0x5080A8
+
+#define mmDMA0_QM_PQ_PI_3                                            0x5080AC
+
+#define mmDMA0_QM_PQ_CI_0                                            0x5080B0
+
+#define mmDMA0_QM_PQ_CI_1                                            0x5080B4
+
+#define mmDMA0_QM_PQ_CI_2                                            0x5080B8
+
+#define mmDMA0_QM_PQ_CI_3                                            0x5080BC
+
+#define mmDMA0_QM_PQ_CFG0_0                                          0x5080C0
+
+#define mmDMA0_QM_PQ_CFG0_1                                          0x5080C4
+
+#define mmDMA0_QM_PQ_CFG0_2                                          0x5080C8
+
+#define mmDMA0_QM_PQ_CFG0_3                                          0x5080CC
+
+#define mmDMA0_QM_PQ_CFG1_0                                          0x5080D0
+
+#define mmDMA0_QM_PQ_CFG1_1                                          0x5080D4
+
+#define mmDMA0_QM_PQ_CFG1_2                                          0x5080D8
+
+#define mmDMA0_QM_PQ_CFG1_3                                          0x5080DC
+
+#define mmDMA0_QM_PQ_ARUSER_31_11_0                                  0x5080E0
+
+#define mmDMA0_QM_PQ_ARUSER_31_11_1                                  0x5080E4
+
+#define mmDMA0_QM_PQ_ARUSER_31_11_2                                  0x5080E8
+
+#define mmDMA0_QM_PQ_ARUSER_31_11_3                                  0x5080EC
+
+#define mmDMA0_QM_PQ_STS0_0                                          0x5080F0
+
+#define mmDMA0_QM_PQ_STS0_1                                          0x5080F4
+
+#define mmDMA0_QM_PQ_STS0_2                                          0x5080F8
+
+#define mmDMA0_QM_PQ_STS0_3                                          0x5080FC
+
+#define mmDMA0_QM_PQ_STS1_0                                          0x508100
+
+#define mmDMA0_QM_PQ_STS1_1                                          0x508104
+
+#define mmDMA0_QM_PQ_STS1_2                                          0x508108
+
+#define mmDMA0_QM_PQ_STS1_3                                          0x50810C
+
+#define mmDMA0_QM_CQ_CFG0_0                                          0x508110
+
+#define mmDMA0_QM_CQ_CFG0_1                                          0x508114
+
+#define mmDMA0_QM_CQ_CFG0_2                                          0x508118
+
+#define mmDMA0_QM_CQ_CFG0_3                                          0x50811C
+
+#define mmDMA0_QM_CQ_CFG0_4                                          0x508120
+
+#define mmDMA0_QM_CQ_CFG1_0                                          0x508124
+
+#define mmDMA0_QM_CQ_CFG1_1                                          0x508128
+
+#define mmDMA0_QM_CQ_CFG1_2                                          0x50812C
+
+#define mmDMA0_QM_CQ_CFG1_3                                          0x508130
+
+#define mmDMA0_QM_CQ_CFG1_4                                          0x508134
+
+#define mmDMA0_QM_CQ_ARUSER_31_11_0                                  0x508138
+
+#define mmDMA0_QM_CQ_ARUSER_31_11_1                                  0x50813C
+
+#define mmDMA0_QM_CQ_ARUSER_31_11_2                                  0x508140
+
+#define mmDMA0_QM_CQ_ARUSER_31_11_3                                  0x508144
+
+#define mmDMA0_QM_CQ_ARUSER_31_11_4                                  0x508148
+
+#define mmDMA0_QM_CQ_STS0_0                                          0x50814C
+
+#define mmDMA0_QM_CQ_STS0_1                                          0x508150
+
+#define mmDMA0_QM_CQ_STS0_2                                          0x508154
+
+#define mmDMA0_QM_CQ_STS0_3                                          0x508158
+
+#define mmDMA0_QM_CQ_STS0_4                                          0x50815C
+
+#define mmDMA0_QM_CQ_STS1_0                                          0x508160
+
+#define mmDMA0_QM_CQ_STS1_1                                          0x508164
+
+#define mmDMA0_QM_CQ_STS1_2                                          0x508168
+
+#define mmDMA0_QM_CQ_STS1_3                                          0x50816C
+
+#define mmDMA0_QM_CQ_STS1_4                                          0x508170
+
+#define mmDMA0_QM_CQ_PTR_LO_0                                        0x508174
+
+#define mmDMA0_QM_CQ_PTR_HI_0                                        0x508178
+
+#define mmDMA0_QM_CQ_TSIZE_0                                         0x50817C
+
+#define mmDMA0_QM_CQ_CTL_0                                           0x508180
+
+#define mmDMA0_QM_CQ_PTR_LO_1                                        0x508184
+
+#define mmDMA0_QM_CQ_PTR_HI_1                                        0x508188
+
+#define mmDMA0_QM_CQ_TSIZE_1                                         0x50818C
+
+#define mmDMA0_QM_CQ_CTL_1                                           0x508190
+
+#define mmDMA0_QM_CQ_PTR_LO_2                                        0x508194
+
+#define mmDMA0_QM_CQ_PTR_HI_2                                        0x508198
+
+#define mmDMA0_QM_CQ_TSIZE_2                                         0x50819C
+
+#define mmDMA0_QM_CQ_CTL_2                                           0x5081A0
+
+#define mmDMA0_QM_CQ_PTR_LO_3                                        0x5081A4
+
+#define mmDMA0_QM_CQ_PTR_HI_3                                        0x5081A8
+
+#define mmDMA0_QM_CQ_TSIZE_3                                         0x5081AC
+
+#define mmDMA0_QM_CQ_CTL_3                                           0x5081B0
+
+#define mmDMA0_QM_CQ_PTR_LO_4                                        0x5081B4
+
+#define mmDMA0_QM_CQ_PTR_HI_4                                        0x5081B8
+
+#define mmDMA0_QM_CQ_TSIZE_4                                         0x5081BC
+
+#define mmDMA0_QM_CQ_CTL_4                                           0x5081C0
+
+#define mmDMA0_QM_CQ_PTR_LO_STS_0                                    0x5081C4
+
+#define mmDMA0_QM_CQ_PTR_LO_STS_1                                    0x5081C8
+
+#define mmDMA0_QM_CQ_PTR_LO_STS_2                                    0x5081CC
+
+#define mmDMA0_QM_CQ_PTR_LO_STS_3                                    0x5081D0
+
+#define mmDMA0_QM_CQ_PTR_LO_STS_4                                    0x5081D4
+
+#define mmDMA0_QM_CQ_PTR_HI_STS_0                                    0x5081D8
+
+#define mmDMA0_QM_CQ_PTR_HI_STS_1                                    0x5081DC
+
+#define mmDMA0_QM_CQ_PTR_HI_STS_2                                    0x5081E0
+
+#define mmDMA0_QM_CQ_PTR_HI_STS_3                                    0x5081E4
+
+#define mmDMA0_QM_CQ_PTR_HI_STS_4                                    0x5081E8
+
+#define mmDMA0_QM_CQ_TSIZE_STS_0                                     0x5081EC
+
+#define mmDMA0_QM_CQ_TSIZE_STS_1                                     0x5081F0
+
+#define mmDMA0_QM_CQ_TSIZE_STS_2                                     0x5081F4
+
+#define mmDMA0_QM_CQ_TSIZE_STS_3                                     0x5081F8
+
+#define mmDMA0_QM_CQ_TSIZE_STS_4                                     0x5081FC
+
+#define mmDMA0_QM_CQ_CTL_STS_0                                       0x508200
+
+#define mmDMA0_QM_CQ_CTL_STS_1                                       0x508204
+
+#define mmDMA0_QM_CQ_CTL_STS_2                                       0x508208
+
+#define mmDMA0_QM_CQ_CTL_STS_3                                       0x50820C
+
+#define mmDMA0_QM_CQ_CTL_STS_4                                       0x508210
+
+#define mmDMA0_QM_CQ_IFIFO_CNT_0                                     0x508214
+
+#define mmDMA0_QM_CQ_IFIFO_CNT_1                                     0x508218
+
+#define mmDMA0_QM_CQ_IFIFO_CNT_2                                     0x50821C
+
+#define mmDMA0_QM_CQ_IFIFO_CNT_3                                     0x508220
+
+#define mmDMA0_QM_CQ_IFIFO_CNT_4                                     0x508224
+
+#define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_0                             0x508228
+
+#define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_1                             0x50822C
+
+#define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_2                             0x508230
+
+#define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_3                             0x508234
+
+#define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_4                             0x508238
+
+#define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_0                             0x50823C
+
+#define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_1                             0x508240
+
+#define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_2                             0x508244
+
+#define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_3                             0x508248
+
+#define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_4                             0x50824C
+
+#define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_0                             0x508250
+
+#define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_1                             0x508254
+
+#define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_2                             0x508258
+
+#define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_3                             0x50825C
+
+#define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_4                             0x508260
+
+#define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_0                             0x508264
+
+#define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_1                             0x508268
+
+#define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_2                             0x50826C
+
+#define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_3                             0x508270
+
+#define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_4                             0x508274
+
+#define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_0                             0x508278
+
+#define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_1                             0x50827C
+
+#define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_2                             0x508280
+
+#define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_3                             0x508284
+
+#define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_4                             0x508288
+
+#define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_0                             0x50828C
+
+#define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_1                             0x508290
+
+#define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_2                             0x508294
+
+#define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_3                             0x508298
+
+#define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_4                             0x50829C
+
+#define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_0                             0x5082A0
+
+#define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_1                             0x5082A4
+
+#define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_2                             0x5082A8
+
+#define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_3                             0x5082AC
+
+#define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_4                             0x5082B0
+
+#define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_0                             0x5082B4
+
+#define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_1                             0x5082B8
+
+#define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_2                             0x5082BC
+
+#define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_3                             0x5082C0
+
+#define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_4                             0x5082C4
+
+#define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0                             0x5082C8
+
+#define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_1                             0x5082CC
+
+#define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_2                             0x5082D0
+
+#define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_3                             0x5082D4
+
+#define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_4                             0x5082D8
+
+#define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0                       0x5082E0
+
+#define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1                       0x5082E4
+
+#define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2                       0x5082E8
+
+#define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3                       0x5082EC
+
+#define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4                       0x5082F0
+
+#define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0                       0x5082F4
+
+#define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1                       0x5082F8
+
+#define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2                       0x5082FC
+
+#define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3                       0x508300
+
+#define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4                       0x508304
+
+#define mmDMA0_QM_CP_FENCE0_RDATA_0                                  0x508308
+
+#define mmDMA0_QM_CP_FENCE0_RDATA_1                                  0x50830C
+
+#define mmDMA0_QM_CP_FENCE0_RDATA_2                                  0x508310
+
+#define mmDMA0_QM_CP_FENCE0_RDATA_3                                  0x508314
+
+#define mmDMA0_QM_CP_FENCE0_RDATA_4                                  0x508318
+
+#define mmDMA0_QM_CP_FENCE1_RDATA_0                                  0x50831C
+
+#define mmDMA0_QM_CP_FENCE1_RDATA_1                                  0x508320
+
+#define mmDMA0_QM_CP_FENCE1_RDATA_2                                  0x508324
+
+#define mmDMA0_QM_CP_FENCE1_RDATA_3                                  0x508328
+
+#define mmDMA0_QM_CP_FENCE1_RDATA_4                                  0x50832C
+
+#define mmDMA0_QM_CP_FENCE2_RDATA_0                                  0x508330
+
+#define mmDMA0_QM_CP_FENCE2_RDATA_1                                  0x508334
+
+#define mmDMA0_QM_CP_FENCE2_RDATA_2                                  0x508338
+
+#define mmDMA0_QM_CP_FENCE2_RDATA_3                                  0x50833C
+
+#define mmDMA0_QM_CP_FENCE2_RDATA_4                                  0x508340
+
+#define mmDMA0_QM_CP_FENCE3_RDATA_0                                  0x508344
+
+#define mmDMA0_QM_CP_FENCE3_RDATA_1                                  0x508348
+
+#define mmDMA0_QM_CP_FENCE3_RDATA_2                                  0x50834C
+
+#define mmDMA0_QM_CP_FENCE3_RDATA_3                                  0x508350
+
+#define mmDMA0_QM_CP_FENCE3_RDATA_4                                  0x508354
+
+#define mmDMA0_QM_CP_FENCE0_CNT_0                                    0x508358
+
+#define mmDMA0_QM_CP_FENCE0_CNT_1                                    0x50835C
+
+#define mmDMA0_QM_CP_FENCE0_CNT_2                                    0x508360
+
+#define mmDMA0_QM_CP_FENCE0_CNT_3                                    0x508364
+
+#define mmDMA0_QM_CP_FENCE0_CNT_4                                    0x508368
+
+#define mmDMA0_QM_CP_FENCE1_CNT_0                                    0x50836C
+
+#define mmDMA0_QM_CP_FENCE1_CNT_1                                    0x508370
+
+#define mmDMA0_QM_CP_FENCE1_CNT_2                                    0x508374
+
+#define mmDMA0_QM_CP_FENCE1_CNT_3                                    0x508378
+
+#define mmDMA0_QM_CP_FENCE1_CNT_4                                    0x50837C
+
+#define mmDMA0_QM_CP_FENCE2_CNT_0                                    0x508380
+
+#define mmDMA0_QM_CP_FENCE2_CNT_1                                    0x508384
+
+#define mmDMA0_QM_CP_FENCE2_CNT_2                                    0x508388
+
+#define mmDMA0_QM_CP_FENCE2_CNT_3                                    0x50838C
+
+#define mmDMA0_QM_CP_FENCE2_CNT_4                                    0x508390
+
+#define mmDMA0_QM_CP_FENCE3_CNT_0                                    0x508394
+
+#define mmDMA0_QM_CP_FENCE3_CNT_1                                    0x508398
+
+#define mmDMA0_QM_CP_FENCE3_CNT_2                                    0x50839C
+
+#define mmDMA0_QM_CP_FENCE3_CNT_3                                    0x5083A0
+
+#define mmDMA0_QM_CP_FENCE3_CNT_4                                    0x5083A4
+
+#define mmDMA0_QM_CP_STS_0                                           0x5083A8
+
+#define mmDMA0_QM_CP_STS_1                                           0x5083AC
+
+#define mmDMA0_QM_CP_STS_2                                           0x5083B0
+
+#define mmDMA0_QM_CP_STS_3                                           0x5083B4
+
+#define mmDMA0_QM_CP_STS_4                                           0x5083B8
+
+#define mmDMA0_QM_CP_CURRENT_INST_LO_0                               0x5083BC
+
+#define mmDMA0_QM_CP_CURRENT_INST_LO_1                               0x5083C0
+
+#define mmDMA0_QM_CP_CURRENT_INST_LO_2                               0x5083C4
+
+#define mmDMA0_QM_CP_CURRENT_INST_LO_3                               0x5083C8
+
+#define mmDMA0_QM_CP_CURRENT_INST_LO_4                               0x5083CC
+
+#define mmDMA0_QM_CP_CURRENT_INST_HI_0                               0x5083D0
+
+#define mmDMA0_QM_CP_CURRENT_INST_HI_1                               0x5083D4
+
+#define mmDMA0_QM_CP_CURRENT_INST_HI_2                               0x5083D8
+
+#define mmDMA0_QM_CP_CURRENT_INST_HI_3                               0x5083DC
+
+#define mmDMA0_QM_CP_CURRENT_INST_HI_4                               0x5083E0
+
+#define mmDMA0_QM_CP_BARRIER_CFG_0                                   0x5083F4
+
+#define mmDMA0_QM_CP_BARRIER_CFG_1                                   0x5083F8
+
+#define mmDMA0_QM_CP_BARRIER_CFG_2                                   0x5083FC
+
+#define mmDMA0_QM_CP_BARRIER_CFG_3                                   0x508400
+
+#define mmDMA0_QM_CP_BARRIER_CFG_4                                   0x508404
+
+#define mmDMA0_QM_CP_DBG_0_0                                         0x508408
+
+#define mmDMA0_QM_CP_DBG_0_1                                         0x50840C
+
+#define mmDMA0_QM_CP_DBG_0_2                                         0x508410
+
+#define mmDMA0_QM_CP_DBG_0_3                                         0x508414
+
+#define mmDMA0_QM_CP_DBG_0_4                                         0x508418
+
+#define mmDMA0_QM_CP_ARUSER_31_11_0                                  0x50841C
+
+#define mmDMA0_QM_CP_ARUSER_31_11_1                                  0x508420
+
+#define mmDMA0_QM_CP_ARUSER_31_11_2                                  0x508424
+
+#define mmDMA0_QM_CP_ARUSER_31_11_3                                  0x508428
+
+#define mmDMA0_QM_CP_ARUSER_31_11_4                                  0x50842C
+
+#define mmDMA0_QM_CP_AWUSER_31_11_0                                  0x508430
+
+#define mmDMA0_QM_CP_AWUSER_31_11_1                                  0x508434
+
+#define mmDMA0_QM_CP_AWUSER_31_11_2                                  0x508438
+
+#define mmDMA0_QM_CP_AWUSER_31_11_3                                  0x50843C
+
+#define mmDMA0_QM_CP_AWUSER_31_11_4                                  0x508440
+
+#define mmDMA0_QM_ARB_CFG_0                                          0x508A00
+
+#define mmDMA0_QM_ARB_CHOISE_Q_PUSH                                  0x508A04
+
+#define mmDMA0_QM_ARB_WRR_WEIGHT_0                                   0x508A08
+
+#define mmDMA0_QM_ARB_WRR_WEIGHT_1                                   0x508A0C
+
+#define mmDMA0_QM_ARB_WRR_WEIGHT_2                                   0x508A10
+
+#define mmDMA0_QM_ARB_WRR_WEIGHT_3                                   0x508A14
+
+#define mmDMA0_QM_ARB_CFG_1                                          0x508A18
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_0                               0x508A20
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_1                               0x508A24
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_2                               0x508A28
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_3                               0x508A2C
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_4                               0x508A30
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_5                               0x508A34
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_6                               0x508A38
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_7                               0x508A3C
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_8                               0x508A40
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_9                               0x508A44
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_10                              0x508A48
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_11                              0x508A4C
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_12                              0x508A50
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_13                              0x508A54
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_14                              0x508A58
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_15                              0x508A5C
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_16                              0x508A60
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_17                              0x508A64
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_18                              0x508A68
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_19                              0x508A6C
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_20                              0x508A70
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_21                              0x508A74
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_22                              0x508A78
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_23                              0x508A7C
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_24                              0x508A80
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_25                              0x508A84
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_26                              0x508A88
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_27                              0x508A8C
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_28                              0x508A90
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_29                              0x508A94
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_30                              0x508A98
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_31                              0x508A9C
+
+#define mmDMA0_QM_ARB_MST_CRED_INC                                   0x508AA0
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_0                         0x508AA4
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_1                         0x508AA8
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_2                         0x508AAC
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_3                         0x508AB0
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_4                         0x508AB4
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_5                         0x508AB8
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_6                         0x508ABC
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_7                         0x508AC0
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_8                         0x508AC4
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_9                         0x508AC8
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_10                        0x508ACC
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_11                        0x508AD0
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_12                        0x508AD4
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_13                        0x508AD8
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_14                        0x508ADC
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_15                        0x508AE0
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_16                        0x508AE4
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_17                        0x508AE8
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_18                        0x508AEC
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_19                        0x508AF0
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_20                        0x508AF4
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_21                        0x508AF8
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_22                        0x508AFC
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_23                        0x508B00
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_24                        0x508B04
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_25                        0x508B08
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_26                        0x508B0C
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_27                        0x508B10
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_28                        0x508B14
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_29                        0x508B18
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_30                        0x508B1C
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_31                        0x508B20
+
+#define mmDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST                       0x508B28
+
+#define mmDMA0_QM_ARB_MST_SLAVE_EN                                   0x508B2C
+
+#define mmDMA0_QM_ARB_MST_QUIET_PER                                  0x508B34
+
+#define mmDMA0_QM_ARB_SLV_CHOISE_WDT                                 0x508B38
+
+#define mmDMA0_QM_ARB_SLV_ID                                         0x508B3C
+
+#define mmDMA0_QM_ARB_MSG_MAX_INFLIGHT                               0x508B44
+
+#define mmDMA0_QM_ARB_MSG_AWUSER_31_11                               0x508B48
+
+#define mmDMA0_QM_ARB_MSG_AWUSER_SEC_PROP                            0x508B4C
+
+#define mmDMA0_QM_ARB_MSG_AWUSER_NON_SEC_PROP                        0x508B50
+
+#define mmDMA0_QM_ARB_BASE_LO                                        0x508B54
+
+#define mmDMA0_QM_ARB_BASE_HI                                        0x508B58
+
+#define mmDMA0_QM_ARB_STATE_STS                                      0x508B80
+
+#define mmDMA0_QM_ARB_CHOISE_FULLNESS_STS                            0x508B84
+
+#define mmDMA0_QM_ARB_MSG_STS                                        0x508B88
+
+#define mmDMA0_QM_ARB_SLV_CHOISE_Q_HEAD                              0x508B8C
+
+#define mmDMA0_QM_ARB_ERR_CAUSE                                      0x508B9C
+
+#define mmDMA0_QM_ARB_ERR_MSG_EN                                     0x508BA0
+
+#define mmDMA0_QM_ARB_ERR_STS_DRP                                    0x508BA8
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_0                                 0x508BB0
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_1                                 0x508BB4
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_2                                 0x508BB8
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_3                                 0x508BBC
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_4                                 0x508BC0
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_5                                 0x508BC4
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_6                                 0x508BC8
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_7                                 0x508BCC
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_8                                 0x508BD0
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_9                                 0x508BD4
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_10                                0x508BD8
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_11                                0x508BDC
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_12                                0x508BE0
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_13                                0x508BE4
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_14                                0x508BE8
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_15                                0x508BEC
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_16                                0x508BF0
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_17                                0x508BF4
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_18                                0x508BF8
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_19                                0x508BFC
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_20                                0x508C00
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_21                                0x508C04
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_22                                0x508C08
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_23                                0x508C0C
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_24                                0x508C10
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_25                                0x508C14
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_26                                0x508C18
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_27                                0x508C1C
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_28                                0x508C20
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_29                                0x508C24
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_30                                0x508C28
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_31                                0x508C2C
+
+#define mmDMA0_QM_CGM_CFG                                            0x508C70
+
+#define mmDMA0_QM_CGM_STS                                            0x508C74
+
+#define mmDMA0_QM_CGM_CFG1                                           0x508C78
+
+#define mmDMA0_QM_LOCAL_RANGE_BASE                                   0x508C80
+
+#define mmDMA0_QM_LOCAL_RANGE_SIZE                                   0x508C84
+
+#define mmDMA0_QM_CSMR_STRICT_PRIO_CFG                               0x508C90
+
+#define mmDMA0_QM_HBW_RD_RATE_LIM_CFG_1                              0x508C94
+
+#define mmDMA0_QM_LBW_WR_RATE_LIM_CFG_0                              0x508C98
+
+#define mmDMA0_QM_LBW_WR_RATE_LIM_CFG_1                              0x508C9C
+
+#define mmDMA0_QM_HBW_RD_RATE_LIM_CFG_0                              0x508CA0
+
+#define mmDMA0_QM_GLBL_AXCACHE                                       0x508CA4
+
+#define mmDMA0_QM_IND_GW_APB_CFG                                     0x508CB0
+
+#define mmDMA0_QM_IND_GW_APB_WDATA                                   0x508CB4
+
+#define mmDMA0_QM_IND_GW_APB_RDATA                                   0x508CB8
+
+#define mmDMA0_QM_IND_GW_APB_STATUS                                  0x508CBC
+
+#define mmDMA0_QM_GLBL_ERR_ADDR_LO                                   0x508CD0
+
+#define mmDMA0_QM_GLBL_ERR_ADDR_HI                                   0x508CD4
+
+#define mmDMA0_QM_GLBL_ERR_WDATA                                     0x508CD8
+
+#define mmDMA0_QM_GLBL_MEM_INIT_BUSY                                 0x508D00
+
+#endif /* ASIC_REG_DMA0_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma1_core_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma1_core_regs.h
new file mode 100644
index 000000000000..4d8d8f26c5d4
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma1_core_regs.h
@@ -0,0 +1,156 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DMA1_CORE_REGS_H_
+#define ASIC_REG_DMA1_CORE_REGS_H_
+
+/*
+ *****************************************
+ *   DMA1_CORE (Prototype: DMA_CORE)
+ *****************************************
+ */
+
+#define mmDMA1_CORE_CFG_0                                            0x520000
+
+#define mmDMA1_CORE_CFG_1                                            0x520004
+
+#define mmDMA1_CORE_LBW_MAX_OUTSTAND                                 0x520008
+
+#define mmDMA1_CORE_SRC_BASE_LO                                      0x520014
+
+#define mmDMA1_CORE_SRC_BASE_HI                                      0x520018
+
+#define mmDMA1_CORE_DST_BASE_LO                                      0x52001C
+
+#define mmDMA1_CORE_DST_BASE_HI                                      0x520020
+
+#define mmDMA1_CORE_SRC_TSIZE_1                                      0x52002C
+
+#define mmDMA1_CORE_SRC_STRIDE_1                                     0x520030
+
+#define mmDMA1_CORE_SRC_TSIZE_2                                      0x520034
+
+#define mmDMA1_CORE_SRC_STRIDE_2                                     0x520038
+
+#define mmDMA1_CORE_SRC_TSIZE_3                                      0x52003C
+
+#define mmDMA1_CORE_SRC_STRIDE_3                                     0x520040
+
+#define mmDMA1_CORE_SRC_TSIZE_4                                      0x520044
+
+#define mmDMA1_CORE_SRC_STRIDE_4                                     0x520048
+
+#define mmDMA1_CORE_SRC_TSIZE_0                                      0x52004C
+
+#define mmDMA1_CORE_DST_TSIZE_1                                      0x520054
+
+#define mmDMA1_CORE_DST_STRIDE_1                                     0x520058
+
+#define mmDMA1_CORE_DST_TSIZE_2                                      0x52005C
+
+#define mmDMA1_CORE_DST_STRIDE_2                                     0x520060
+
+#define mmDMA1_CORE_DST_TSIZE_3                                      0x520064
+
+#define mmDMA1_CORE_DST_STRIDE_3                                     0x520068
+
+#define mmDMA1_CORE_DST_TSIZE_4                                      0x52006C
+
+#define mmDMA1_CORE_DST_STRIDE_4                                     0x520070
+
+#define mmDMA1_CORE_DST_TSIZE_0                                      0x520074
+
+#define mmDMA1_CORE_COMMIT                                           0x520078
+
+#define mmDMA1_CORE_WR_COMP_WDATA                                    0x52007C
+
+#define mmDMA1_CORE_WR_COMP_ADDR_LO                                  0x520080
+
+#define mmDMA1_CORE_WR_COMP_ADDR_HI                                  0x520084
+
+#define mmDMA1_CORE_WR_COMP_AWUSER_31_11                             0x520088
+
+#define mmDMA1_CORE_TE_NUMROWS                                       0x520094
+
+#define mmDMA1_CORE_PROT                                             0x5200B8
+
+#define mmDMA1_CORE_SECURE_PROPS                                     0x5200F0
+
+#define mmDMA1_CORE_NON_SECURE_PROPS                                 0x5200F4
+
+#define mmDMA1_CORE_RD_MAX_OUTSTAND                                  0x520100
+
+#define mmDMA1_CORE_RD_MAX_SIZE                                      0x520104
+
+#define mmDMA1_CORE_RD_ARCACHE                                       0x520108
+
+#define mmDMA1_CORE_RD_ARUSER_31_11                                  0x520110
+
+#define mmDMA1_CORE_RD_INFLIGHTS                                     0x520114
+
+#define mmDMA1_CORE_WR_MAX_OUTSTAND                                  0x520120
+
+#define mmDMA1_CORE_WR_MAX_AWID                                      0x520124
+
+#define mmDMA1_CORE_WR_AWCACHE                                       0x520128
+
+#define mmDMA1_CORE_WR_AWUSER_31_11                                  0x520130
+
+#define mmDMA1_CORE_WR_INFLIGHTS                                     0x520134
+
+#define mmDMA1_CORE_RD_RATE_LIM_CFG_0                                0x520150
+
+#define mmDMA1_CORE_RD_RATE_LIM_CFG_1                                0x520154
+
+#define mmDMA1_CORE_WR_RATE_LIM_CFG_0                                0x520158
+
+#define mmDMA1_CORE_WR_RATE_LIM_CFG_1                                0x52015C
+
+#define mmDMA1_CORE_ERR_CFG                                          0x520160
+
+#define mmDMA1_CORE_ERR_CAUSE                                        0x520164
+
+#define mmDMA1_CORE_ERRMSG_ADDR_LO                                   0x520170
+
+#define mmDMA1_CORE_ERRMSG_ADDR_HI                                   0x520174
+
+#define mmDMA1_CORE_ERRMSG_WDATA                                     0x520178
+
+#define mmDMA1_CORE_STS0                                             0x520190
+
+#define mmDMA1_CORE_STS1                                             0x520194
+
+#define mmDMA1_CORE_RD_DBGMEM_ADD                                    0x520200
+
+#define mmDMA1_CORE_RD_DBGMEM_DATA_WR                                0x520204
+
+#define mmDMA1_CORE_RD_DBGMEM_DATA_RD                                0x520208
+
+#define mmDMA1_CORE_RD_DBGMEM_CTRL                                   0x52020C
+
+#define mmDMA1_CORE_RD_DBGMEM_RC                                     0x520210
+
+#define mmDMA1_CORE_DBG_HBW_AXI_AR_CNT                               0x520220
+
+#define mmDMA1_CORE_DBG_HBW_AXI_AW_CNT                               0x520224
+
+#define mmDMA1_CORE_DBG_LBW_AXI_AW_CNT                               0x520228
+
+#define mmDMA1_CORE_DBG_DESC_CNT                                     0x52022C
+
+#define mmDMA1_CORE_DBG_STS                                          0x520230
+
+#define mmDMA1_CORE_DBG_RD_DESC_ID                                   0x520234
+
+#define mmDMA1_CORE_DBG_WR_DESC_ID                                   0x520238
+
+#endif /* ASIC_REG_DMA1_CORE_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma1_qm_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma1_qm_regs.h
new file mode 100644
index 000000000000..c3ef300849be
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma1_qm_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DMA1_QM_REGS_H_
+#define ASIC_REG_DMA1_QM_REGS_H_
+
+/*
+ *****************************************
+ *   DMA1_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmDMA1_QM_GLBL_CFG0                                          0x528000
+
+#define mmDMA1_QM_GLBL_CFG1                                          0x528004
+
+#define mmDMA1_QM_GLBL_PROT                                          0x528008
+
+#define mmDMA1_QM_GLBL_ERR_CFG                                       0x52800C
+
+#define mmDMA1_QM_GLBL_SECURE_PROPS_0                                0x528010
+
+#define mmDMA1_QM_GLBL_SECURE_PROPS_1                                0x528014
+
+#define mmDMA1_QM_GLBL_SECURE_PROPS_2                                0x528018
+
+#define mmDMA1_QM_GLBL_SECURE_PROPS_3                                0x52801C
+
+#define mmDMA1_QM_GLBL_SECURE_PROPS_4                                0x528020
+
+#define mmDMA1_QM_GLBL_NON_SECURE_PROPS_0                            0x528024
+
+#define mmDMA1_QM_GLBL_NON_SECURE_PROPS_1                            0x528028
+
+#define mmDMA1_QM_GLBL_NON_SECURE_PROPS_2                            0x52802C
+
+#define mmDMA1_QM_GLBL_NON_SECURE_PROPS_3                            0x528030
+
+#define mmDMA1_QM_GLBL_NON_SECURE_PROPS_4                            0x528034
+
+#define mmDMA1_QM_GLBL_STS0                                          0x528038
+
+#define mmDMA1_QM_GLBL_STS1_0                                        0x528040
+
+#define mmDMA1_QM_GLBL_STS1_1                                        0x528044
+
+#define mmDMA1_QM_GLBL_STS1_2                                        0x528048
+
+#define mmDMA1_QM_GLBL_STS1_3                                        0x52804C
+
+#define mmDMA1_QM_GLBL_STS1_4                                        0x528050
+
+#define mmDMA1_QM_GLBL_MSG_EN_0                                      0x528054
+
+#define mmDMA1_QM_GLBL_MSG_EN_1                                      0x528058
+
+#define mmDMA1_QM_GLBL_MSG_EN_2                                      0x52805C
+
+#define mmDMA1_QM_GLBL_MSG_EN_3                                      0x528060
+
+#define mmDMA1_QM_GLBL_MSG_EN_4                                      0x528068
+
+#define mmDMA1_QM_PQ_BASE_LO_0                                       0x528070
+
+#define mmDMA1_QM_PQ_BASE_LO_1                                       0x528074
+
+#define mmDMA1_QM_PQ_BASE_LO_2                                       0x528078
+
+#define mmDMA1_QM_PQ_BASE_LO_3                                       0x52807C
+
+#define mmDMA1_QM_PQ_BASE_HI_0                                       0x528080
+
+#define mmDMA1_QM_PQ_BASE_HI_1                                       0x528084
+
+#define mmDMA1_QM_PQ_BASE_HI_2                                       0x528088
+
+#define mmDMA1_QM_PQ_BASE_HI_3                                       0x52808C
+
+#define mmDMA1_QM_PQ_SIZE_0                                          0x528090
+
+#define mmDMA1_QM_PQ_SIZE_1                                          0x528094
+
+#define mmDMA1_QM_PQ_SIZE_2                                          0x528098
+
+#define mmDMA1_QM_PQ_SIZE_3                                          0x52809C
+
+#define mmDMA1_QM_PQ_PI_0                                            0x5280A0
+
+#define mmDMA1_QM_PQ_PI_1                                            0x5280A4
+
+#define mmDMA1_QM_PQ_PI_2                                            0x5280A8
+
+#define mmDMA1_QM_PQ_PI_3                                            0x5280AC
+
+#define mmDMA1_QM_PQ_CI_0                                            0x5280B0
+
+#define mmDMA1_QM_PQ_CI_1                                            0x5280B4
+
+#define mmDMA1_QM_PQ_CI_2                                            0x5280B8
+
+#define mmDMA1_QM_PQ_CI_3                                            0x5280BC
+
+#define mmDMA1_QM_PQ_CFG0_0                                          0x5280C0
+
+#define mmDMA1_QM_PQ_CFG0_1                                          0x5280C4
+
+#define mmDMA1_QM_PQ_CFG0_2                                          0x5280C8
+
+#define mmDMA1_QM_PQ_CFG0_3                                          0x5280CC
+
+#define mmDMA1_QM_PQ_CFG1_0                                          0x5280D0
+
+#define mmDMA1_QM_PQ_CFG1_1                                          0x5280D4
+
+#define mmDMA1_QM_PQ_CFG1_2                                          0x5280D8
+
+#define mmDMA1_QM_PQ_CFG1_3                                          0x5280DC
+
+#define mmDMA1_QM_PQ_ARUSER_31_11_0                                  0x5280E0
+
+#define mmDMA1_QM_PQ_ARUSER_31_11_1                                  0x5280E4
+
+#define mmDMA1_QM_PQ_ARUSER_31_11_2                                  0x5280E8
+
+#define mmDMA1_QM_PQ_ARUSER_31_11_3                                  0x5280EC
+
+#define mmDMA1_QM_PQ_STS0_0                                          0x5280F0
+
+#define mmDMA1_QM_PQ_STS0_1                                          0x5280F4
+
+#define mmDMA1_QM_PQ_STS0_2                                          0x5280F8
+
+#define mmDMA1_QM_PQ_STS0_3                                          0x5280FC
+
+#define mmDMA1_QM_PQ_STS1_0                                          0x528100
+
+#define mmDMA1_QM_PQ_STS1_1                                          0x528104
+
+#define mmDMA1_QM_PQ_STS1_2                                          0x528108
+
+#define mmDMA1_QM_PQ_STS1_3                                          0x52810C
+
+#define mmDMA1_QM_CQ_CFG0_0                                          0x528110
+
+#define mmDMA1_QM_CQ_CFG0_1                                          0x528114
+
+#define mmDMA1_QM_CQ_CFG0_2                                          0x528118
+
+#define mmDMA1_QM_CQ_CFG0_3                                          0x52811C
+
+#define mmDMA1_QM_CQ_CFG0_4                                          0x528120
+
+#define mmDMA1_QM_CQ_CFG1_0                                          0x528124
+
+#define mmDMA1_QM_CQ_CFG1_1                                          0x528128
+
+#define mmDMA1_QM_CQ_CFG1_2                                          0x52812C
+
+#define mmDMA1_QM_CQ_CFG1_3                                          0x528130
+
+#define mmDMA1_QM_CQ_CFG1_4                                          0x528134
+
+#define mmDMA1_QM_CQ_ARUSER_31_11_0                                  0x528138
+
+#define mmDMA1_QM_CQ_ARUSER_31_11_1                                  0x52813C
+
+#define mmDMA1_QM_CQ_ARUSER_31_11_2                                  0x528140
+
+#define mmDMA1_QM_CQ_ARUSER_31_11_3                                  0x528144
+
+#define mmDMA1_QM_CQ_ARUSER_31_11_4                                  0x528148
+
+#define mmDMA1_QM_CQ_STS0_0                                          0x52814C
+
+#define mmDMA1_QM_CQ_STS0_1                                          0x528150
+
+#define mmDMA1_QM_CQ_STS0_2                                          0x528154
+
+#define mmDMA1_QM_CQ_STS0_3                                          0x528158
+
+#define mmDMA1_QM_CQ_STS0_4                                          0x52815C
+
+#define mmDMA1_QM_CQ_STS1_0                                          0x528160
+
+#define mmDMA1_QM_CQ_STS1_1                                          0x528164
+
+#define mmDMA1_QM_CQ_STS1_2                                          0x528168
+
+#define mmDMA1_QM_CQ_STS1_3                                          0x52816C
+
+#define mmDMA1_QM_CQ_STS1_4                                          0x528170
+
+#define mmDMA1_QM_CQ_PTR_LO_0                                        0x528174
+
+#define mmDMA1_QM_CQ_PTR_HI_0                                        0x528178
+
+#define mmDMA1_QM_CQ_TSIZE_0                                         0x52817C
+
+#define mmDMA1_QM_CQ_CTL_0                                           0x528180
+
+#define mmDMA1_QM_CQ_PTR_LO_1                                        0x528184
+
+#define mmDMA1_QM_CQ_PTR_HI_1                                        0x528188
+
+#define mmDMA1_QM_CQ_TSIZE_1                                         0x52818C
+
+#define mmDMA1_QM_CQ_CTL_1                                           0x528190
+
+#define mmDMA1_QM_CQ_PTR_LO_2                                        0x528194
+
+#define mmDMA1_QM_CQ_PTR_HI_2                                        0x528198
+
+#define mmDMA1_QM_CQ_TSIZE_2                                         0x52819C
+
+#define mmDMA1_QM_CQ_CTL_2                                           0x5281A0
+
+#define mmDMA1_QM_CQ_PTR_LO_3                                        0x5281A4
+
+#define mmDMA1_QM_CQ_PTR_HI_3                                        0x5281A8
+
+#define mmDMA1_QM_CQ_TSIZE_3                                         0x5281AC
+
+#define mmDMA1_QM_CQ_CTL_3                                           0x5281B0
+
+#define mmDMA1_QM_CQ_PTR_LO_4                                        0x5281B4
+
+#define mmDMA1_QM_CQ_PTR_HI_4                                        0x5281B8
+
+#define mmDMA1_QM_CQ_TSIZE_4                                         0x5281BC
+
+#define mmDMA1_QM_CQ_CTL_4                                           0x5281C0
+
+#define mmDMA1_QM_CQ_PTR_LO_STS_0                                    0x5281C4
+
+#define mmDMA1_QM_CQ_PTR_LO_STS_1                                    0x5281C8
+
+#define mmDMA1_QM_CQ_PTR_LO_STS_2                                    0x5281CC
+
+#define mmDMA1_QM_CQ_PTR_LO_STS_3                                    0x5281D0
+
+#define mmDMA1_QM_CQ_PTR_LO_STS_4                                    0x5281D4
+
+#define mmDMA1_QM_CQ_PTR_HI_STS_0                                    0x5281D8
+
+#define mmDMA1_QM_CQ_PTR_HI_STS_1                                    0x5281DC
+
+#define mmDMA1_QM_CQ_PTR_HI_STS_2                                    0x5281E0
+
+#define mmDMA1_QM_CQ_PTR_HI_STS_3                                    0x5281E4
+
+#define mmDMA1_QM_CQ_PTR_HI_STS_4                                    0x5281E8
+
+#define mmDMA1_QM_CQ_TSIZE_STS_0                                     0x5281EC
+
+#define mmDMA1_QM_CQ_TSIZE_STS_1                                     0x5281F0
+
+#define mmDMA1_QM_CQ_TSIZE_STS_2                                     0x5281F4
+
+#define mmDMA1_QM_CQ_TSIZE_STS_3                                     0x5281F8
+
+#define mmDMA1_QM_CQ_TSIZE_STS_4                                     0x5281FC
+
+#define mmDMA1_QM_CQ_CTL_STS_0                                       0x528200
+
+#define mmDMA1_QM_CQ_CTL_STS_1                                       0x528204
+
+#define mmDMA1_QM_CQ_CTL_STS_2                                       0x528208
+
+#define mmDMA1_QM_CQ_CTL_STS_3                                       0x52820C
+
+#define mmDMA1_QM_CQ_CTL_STS_4                                       0x528210
+
+#define mmDMA1_QM_CQ_IFIFO_CNT_0                                     0x528214
+
+#define mmDMA1_QM_CQ_IFIFO_CNT_1                                     0x528218
+
+#define mmDMA1_QM_CQ_IFIFO_CNT_2                                     0x52821C
+
+#define mmDMA1_QM_CQ_IFIFO_CNT_3                                     0x528220
+
+#define mmDMA1_QM_CQ_IFIFO_CNT_4                                     0x528224
+
+#define mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_0                             0x528228
+
+#define mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_1                             0x52822C
+
+#define mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_2                             0x528230
+
+#define mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_3                             0x528234
+
+#define mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_4                             0x528238
+
+#define mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_0                             0x52823C
+
+#define mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_1                             0x528240
+
+#define mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_2                             0x528244
+
+#define mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_3                             0x528248
+
+#define mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_4                             0x52824C
+
+#define mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_0                             0x528250
+
+#define mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_1                             0x528254
+
+#define mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_2                             0x528258
+
+#define mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_3                             0x52825C
+
+#define mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_4                             0x528260
+
+#define mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_0                             0x528264
+
+#define mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_1                             0x528268
+
+#define mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_2                             0x52826C
+
+#define mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_3                             0x528270
+
+#define mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_4                             0x528274
+
+#define mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_0                             0x528278
+
+#define mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_1                             0x52827C
+
+#define mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_2                             0x528280
+
+#define mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_3                             0x528284
+
+#define mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_4                             0x528288
+
+#define mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_0                             0x52828C
+
+#define mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_1                             0x528290
+
+#define mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_2                             0x528294
+
+#define mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_3                             0x528298
+
+#define mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_4                             0x52829C
+
+#define mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_0                             0x5282A0
+
+#define mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_1                             0x5282A4
+
+#define mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_2                             0x5282A8
+
+#define mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_3                             0x5282AC
+
+#define mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_4                             0x5282B0
+
+#define mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_0                             0x5282B4
+
+#define mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_1                             0x5282B8
+
+#define mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_2                             0x5282BC
+
+#define mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_3                             0x5282C0
+
+#define mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_4                             0x5282C4
+
+#define mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_0                             0x5282C8
+
+#define mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_1                             0x5282CC
+
+#define mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_2                             0x5282D0
+
+#define mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_3                             0x5282D4
+
+#define mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_4                             0x5282D8
+
+#define mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0                       0x5282E0
+
+#define mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1                       0x5282E4
+
+#define mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2                       0x5282E8
+
+#define mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3                       0x5282EC
+
+#define mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4                       0x5282F0
+
+#define mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_0                       0x5282F4
+
+#define mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_1                       0x5282F8
+
+#define mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_2                       0x5282FC
+
+#define mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3                       0x528300
+
+#define mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_4                       0x528304
+
+#define mmDMA1_QM_CP_FENCE0_RDATA_0                                  0x528308
+
+#define mmDMA1_QM_CP_FENCE0_RDATA_1                                  0x52830C
+
+#define mmDMA1_QM_CP_FENCE0_RDATA_2                                  0x528310
+
+#define mmDMA1_QM_CP_FENCE0_RDATA_3                                  0x528314
+
+#define mmDMA1_QM_CP_FENCE0_RDATA_4                                  0x528318
+
+#define mmDMA1_QM_CP_FENCE1_RDATA_0                                  0x52831C
+
+#define mmDMA1_QM_CP_FENCE1_RDATA_1                                  0x528320
+
+#define mmDMA1_QM_CP_FENCE1_RDATA_2                                  0x528324
+
+#define mmDMA1_QM_CP_FENCE1_RDATA_3                                  0x528328
+
+#define mmDMA1_QM_CP_FENCE1_RDATA_4                                  0x52832C
+
+#define mmDMA1_QM_CP_FENCE2_RDATA_0                                  0x528330
+
+#define mmDMA1_QM_CP_FENCE2_RDATA_1                                  0x528334
+
+#define mmDMA1_QM_CP_FENCE2_RDATA_2                                  0x528338
+
+#define mmDMA1_QM_CP_FENCE2_RDATA_3                                  0x52833C
+
+#define mmDMA1_QM_CP_FENCE2_RDATA_4                                  0x528340
+
+#define mmDMA1_QM_CP_FENCE3_RDATA_0                                  0x528344
+
+#define mmDMA1_QM_CP_FENCE3_RDATA_1                                  0x528348
+
+#define mmDMA1_QM_CP_FENCE3_RDATA_2                                  0x52834C
+
+#define mmDMA1_QM_CP_FENCE3_RDATA_3                                  0x528350
+
+#define mmDMA1_QM_CP_FENCE3_RDATA_4                                  0x528354
+
+#define mmDMA1_QM_CP_FENCE0_CNT_0                                    0x528358
+
+#define mmDMA1_QM_CP_FENCE0_CNT_1                                    0x52835C
+
+#define mmDMA1_QM_CP_FENCE0_CNT_2                                    0x528360
+
+#define mmDMA1_QM_CP_FENCE0_CNT_3                                    0x528364
+
+#define mmDMA1_QM_CP_FENCE0_CNT_4                                    0x528368
+
+#define mmDMA1_QM_CP_FENCE1_CNT_0                                    0x52836C
+
+#define mmDMA1_QM_CP_FENCE1_CNT_1                                    0x528370
+
+#define mmDMA1_QM_CP_FENCE1_CNT_2                                    0x528374
+
+#define mmDMA1_QM_CP_FENCE1_CNT_3                                    0x528378
+
+#define mmDMA1_QM_CP_FENCE1_CNT_4                                    0x52837C
+
+#define mmDMA1_QM_CP_FENCE2_CNT_0                                    0x528380
+
+#define mmDMA1_QM_CP_FENCE2_CNT_1                                    0x528384
+
+#define mmDMA1_QM_CP_FENCE2_CNT_2                                    0x528388
+
+#define mmDMA1_QM_CP_FENCE2_CNT_3                                    0x52838C
+
+#define mmDMA1_QM_CP_FENCE2_CNT_4                                    0x528390
+
+#define mmDMA1_QM_CP_FENCE3_CNT_0                                    0x528394
+
+#define mmDMA1_QM_CP_FENCE3_CNT_1                                    0x528398
+
+#define mmDMA1_QM_CP_FENCE3_CNT_2                                    0x52839C
+
+#define mmDMA1_QM_CP_FENCE3_CNT_3                                    0x5283A0
+
+#define mmDMA1_QM_CP_FENCE3_CNT_4                                    0x5283A4
+
+#define mmDMA1_QM_CP_STS_0                                           0x5283A8
+
+#define mmDMA1_QM_CP_STS_1                                           0x5283AC
+
+#define mmDMA1_QM_CP_STS_2                                           0x5283B0
+
+#define mmDMA1_QM_CP_STS_3                                           0x5283B4
+
+#define mmDMA1_QM_CP_STS_4                                           0x5283B8
+
+#define mmDMA1_QM_CP_CURRENT_INST_LO_0                               0x5283BC
+
+#define mmDMA1_QM_CP_CURRENT_INST_LO_1                               0x5283C0
+
+#define mmDMA1_QM_CP_CURRENT_INST_LO_2                               0x5283C4
+
+#define mmDMA1_QM_CP_CURRENT_INST_LO_3                               0x5283C8
+
+#define mmDMA1_QM_CP_CURRENT_INST_LO_4                               0x5283CC
+
+#define mmDMA1_QM_CP_CURRENT_INST_HI_0                               0x5283D0
+
+#define mmDMA1_QM_CP_CURRENT_INST_HI_1                               0x5283D4
+
+#define mmDMA1_QM_CP_CURRENT_INST_HI_2                               0x5283D8
+
+#define mmDMA1_QM_CP_CURRENT_INST_HI_3                               0x5283DC
+
+#define mmDMA1_QM_CP_CURRENT_INST_HI_4                               0x5283E0
+
+#define mmDMA1_QM_CP_BARRIER_CFG_0                                   0x5283F4
+
+#define mmDMA1_QM_CP_BARRIER_CFG_1                                   0x5283F8
+
+#define mmDMA1_QM_CP_BARRIER_CFG_2                                   0x5283FC
+
+#define mmDMA1_QM_CP_BARRIER_CFG_3                                   0x528400
+
+#define mmDMA1_QM_CP_BARRIER_CFG_4                                   0x528404
+
+#define mmDMA1_QM_CP_DBG_0_0                                         0x528408
+
+#define mmDMA1_QM_CP_DBG_0_1                                         0x52840C
+
+#define mmDMA1_QM_CP_DBG_0_2                                         0x528410
+
+#define mmDMA1_QM_CP_DBG_0_3                                         0x528414
+
+#define mmDMA1_QM_CP_DBG_0_4                                         0x528418
+
+#define mmDMA1_QM_CP_ARUSER_31_11_0                                  0x52841C
+
+#define mmDMA1_QM_CP_ARUSER_31_11_1                                  0x528420
+
+#define mmDMA1_QM_CP_ARUSER_31_11_2                                  0x528424
+
+#define mmDMA1_QM_CP_ARUSER_31_11_3                                  0x528428
+
+#define mmDMA1_QM_CP_ARUSER_31_11_4                                  0x52842C
+
+#define mmDMA1_QM_CP_AWUSER_31_11_0                                  0x528430
+
+#define mmDMA1_QM_CP_AWUSER_31_11_1                                  0x528434
+
+#define mmDMA1_QM_CP_AWUSER_31_11_2                                  0x528438
+
+#define mmDMA1_QM_CP_AWUSER_31_11_3                                  0x52843C
+
+#define mmDMA1_QM_CP_AWUSER_31_11_4                                  0x528440
+
+#define mmDMA1_QM_ARB_CFG_0                                          0x528A00
+
+#define mmDMA1_QM_ARB_CHOISE_Q_PUSH                                  0x528A04
+
+#define mmDMA1_QM_ARB_WRR_WEIGHT_0                                   0x528A08
+
+#define mmDMA1_QM_ARB_WRR_WEIGHT_1                                   0x528A0C
+
+#define mmDMA1_QM_ARB_WRR_WEIGHT_2                                   0x528A10
+
+#define mmDMA1_QM_ARB_WRR_WEIGHT_3                                   0x528A14
+
+#define mmDMA1_QM_ARB_CFG_1                                          0x528A18
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_0                               0x528A20
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_1                               0x528A24
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_2                               0x528A28
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_3                               0x528A2C
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_4                               0x528A30
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_5                               0x528A34
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_6                               0x528A38
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_7                               0x528A3C
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_8                               0x528A40
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_9                               0x528A44
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_10                              0x528A48
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_11                              0x528A4C
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_12                              0x528A50
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_13                              0x528A54
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_14                              0x528A58
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_15                              0x528A5C
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_16                              0x528A60
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_17                              0x528A64
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_18                              0x528A68
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_19                              0x528A6C
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_20                              0x528A70
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_21                              0x528A74
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_22                              0x528A78
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_23                              0x528A7C
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_24                              0x528A80
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_25                              0x528A84
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_26                              0x528A88
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_27                              0x528A8C
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_28                              0x528A90
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_29                              0x528A94
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_30                              0x528A98
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_31                              0x528A9C
+
+#define mmDMA1_QM_ARB_MST_CRED_INC                                   0x528AA0
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_0                         0x528AA4
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_1                         0x528AA8
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_2                         0x528AAC
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_3                         0x528AB0
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_4                         0x528AB4
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_5                         0x528AB8
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_6                         0x528ABC
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_7                         0x528AC0
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_8                         0x528AC4
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_9                         0x528AC8
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_10                        0x528ACC
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_11                        0x528AD0
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_12                        0x528AD4
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_13                        0x528AD8
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_14                        0x528ADC
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_15                        0x528AE0
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_16                        0x528AE4
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_17                        0x528AE8
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_18                        0x528AEC
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_19                        0x528AF0
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_20                        0x528AF4
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_21                        0x528AF8
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_22                        0x528AFC
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_23                        0x528B00
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_24                        0x528B04
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_25                        0x528B08
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_26                        0x528B0C
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_27                        0x528B10
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_28                        0x528B14
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_29                        0x528B18
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_30                        0x528B1C
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_31                        0x528B20
+
+#define mmDMA1_QM_ARB_SLV_MASTER_INC_CRED_OFST                       0x528B28
+
+#define mmDMA1_QM_ARB_MST_SLAVE_EN                                   0x528B2C
+
+#define mmDMA1_QM_ARB_MST_QUIET_PER                                  0x528B34
+
+#define mmDMA1_QM_ARB_SLV_CHOISE_WDT                                 0x528B38
+
+#define mmDMA1_QM_ARB_SLV_ID                                         0x528B3C
+
+#define mmDMA1_QM_ARB_MSG_MAX_INFLIGHT                               0x528B44
+
+#define mmDMA1_QM_ARB_MSG_AWUSER_31_11                               0x528B48
+
+#define mmDMA1_QM_ARB_MSG_AWUSER_SEC_PROP                            0x528B4C
+
+#define mmDMA1_QM_ARB_MSG_AWUSER_NON_SEC_PROP                        0x528B50
+
+#define mmDMA1_QM_ARB_BASE_LO                                        0x528B54
+
+#define mmDMA1_QM_ARB_BASE_HI                                        0x528B58
+
+#define mmDMA1_QM_ARB_STATE_STS                                      0x528B80
+
+#define mmDMA1_QM_ARB_CHOISE_FULLNESS_STS                            0x528B84
+
+#define mmDMA1_QM_ARB_MSG_STS                                        0x528B88
+
+#define mmDMA1_QM_ARB_SLV_CHOISE_Q_HEAD                              0x528B8C
+
+#define mmDMA1_QM_ARB_ERR_CAUSE                                      0x528B9C
+
+#define mmDMA1_QM_ARB_ERR_MSG_EN                                     0x528BA0
+
+#define mmDMA1_QM_ARB_ERR_STS_DRP                                    0x528BA8
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_0                                 0x528BB0
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_1                                 0x528BB4
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_2                                 0x528BB8
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_3                                 0x528BBC
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_4                                 0x528BC0
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_5                                 0x528BC4
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_6                                 0x528BC8
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_7                                 0x528BCC
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_8                                 0x528BD0
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_9                                 0x528BD4
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_10                                0x528BD8
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_11                                0x528BDC
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_12                                0x528BE0
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_13                                0x528BE4
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_14                                0x528BE8
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_15                                0x528BEC
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_16                                0x528BF0
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_17                                0x528BF4
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_18                                0x528BF8
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_19                                0x528BFC
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_20                                0x528C00
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_21                                0x528C04
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_22                                0x528C08
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_23                                0x528C0C
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_24                                0x528C10
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_25                                0x528C14
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_26                                0x528C18
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_27                                0x528C1C
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_28                                0x528C20
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_29                                0x528C24
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_30                                0x528C28
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_31                                0x528C2C
+
+#define mmDMA1_QM_CGM_CFG                                            0x528C70
+
+#define mmDMA1_QM_CGM_STS                                            0x528C74
+
+#define mmDMA1_QM_CGM_CFG1                                           0x528C78
+
+#define mmDMA1_QM_LOCAL_RANGE_BASE                                   0x528C80
+
+#define mmDMA1_QM_LOCAL_RANGE_SIZE                                   0x528C84
+
+#define mmDMA1_QM_CSMR_STRICT_PRIO_CFG                               0x528C90
+
+#define mmDMA1_QM_HBW_RD_RATE_LIM_CFG_1                              0x528C94
+
+#define mmDMA1_QM_LBW_WR_RATE_LIM_CFG_0                              0x528C98
+
+#define mmDMA1_QM_LBW_WR_RATE_LIM_CFG_1                              0x528C9C
+
+#define mmDMA1_QM_HBW_RD_RATE_LIM_CFG_0                              0x528CA0
+
+#define mmDMA1_QM_GLBL_AXCACHE                                       0x528CA4
+
+#define mmDMA1_QM_IND_GW_APB_CFG                                     0x528CB0
+
+#define mmDMA1_QM_IND_GW_APB_WDATA                                   0x528CB4
+
+#define mmDMA1_QM_IND_GW_APB_RDATA                                   0x528CB8
+
+#define mmDMA1_QM_IND_GW_APB_STATUS                                  0x528CBC
+
+#define mmDMA1_QM_GLBL_ERR_ADDR_LO                                   0x528CD0
+
+#define mmDMA1_QM_GLBL_ERR_ADDR_HI                                   0x528CD4
+
+#define mmDMA1_QM_GLBL_ERR_WDATA                                     0x528CD8
+
+#define mmDMA1_QM_GLBL_MEM_INIT_BUSY                                 0x528D00
+
+#endif /* ASIC_REG_DMA1_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma2_core_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma2_core_regs.h
new file mode 100644
index 000000000000..a42862cd5ae0
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma2_core_regs.h
@@ -0,0 +1,156 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DMA2_CORE_REGS_H_
+#define ASIC_REG_DMA2_CORE_REGS_H_
+
+/*
+ *****************************************
+ *   DMA2_CORE (Prototype: DMA_CORE)
+ *****************************************
+ */
+
+#define mmDMA2_CORE_CFG_0                                            0x540000
+
+#define mmDMA2_CORE_CFG_1                                            0x540004
+
+#define mmDMA2_CORE_LBW_MAX_OUTSTAND                                 0x540008
+
+#define mmDMA2_CORE_SRC_BASE_LO                                      0x540014
+
+#define mmDMA2_CORE_SRC_BASE_HI                                      0x540018
+
+#define mmDMA2_CORE_DST_BASE_LO                                      0x54001C
+
+#define mmDMA2_CORE_DST_BASE_HI                                      0x540020
+
+#define mmDMA2_CORE_SRC_TSIZE_1                                      0x54002C
+
+#define mmDMA2_CORE_SRC_STRIDE_1                                     0x540030
+
+#define mmDMA2_CORE_SRC_TSIZE_2                                      0x540034
+
+#define mmDMA2_CORE_SRC_STRIDE_2                                     0x540038
+
+#define mmDMA2_CORE_SRC_TSIZE_3                                      0x54003C
+
+#define mmDMA2_CORE_SRC_STRIDE_3                                     0x540040
+
+#define mmDMA2_CORE_SRC_TSIZE_4                                      0x540044
+
+#define mmDMA2_CORE_SRC_STRIDE_4                                     0x540048
+
+#define mmDMA2_CORE_SRC_TSIZE_0                                      0x54004C
+
+#define mmDMA2_CORE_DST_TSIZE_1                                      0x540054
+
+#define mmDMA2_CORE_DST_STRIDE_1                                     0x540058
+
+#define mmDMA2_CORE_DST_TSIZE_2                                      0x54005C
+
+#define mmDMA2_CORE_DST_STRIDE_2                                     0x540060
+
+#define mmDMA2_CORE_DST_TSIZE_3                                      0x540064
+
+#define mmDMA2_CORE_DST_STRIDE_3                                     0x540068
+
+#define mmDMA2_CORE_DST_TSIZE_4                                      0x54006C
+
+#define mmDMA2_CORE_DST_STRIDE_4                                     0x540070
+
+#define mmDMA2_CORE_DST_TSIZE_0                                      0x540074
+
+#define mmDMA2_CORE_COMMIT                                           0x540078
+
+#define mmDMA2_CORE_WR_COMP_WDATA                                    0x54007C
+
+#define mmDMA2_CORE_WR_COMP_ADDR_LO                                  0x540080
+
+#define mmDMA2_CORE_WR_COMP_ADDR_HI                                  0x540084
+
+#define mmDMA2_CORE_WR_COMP_AWUSER_31_11                             0x540088
+
+#define mmDMA2_CORE_TE_NUMROWS                                       0x540094
+
+#define mmDMA2_CORE_PROT                                             0x5400B8
+
+#define mmDMA2_CORE_SECURE_PROPS                                     0x5400F0
+
+#define mmDMA2_CORE_NON_SECURE_PROPS                                 0x5400F4
+
+#define mmDMA2_CORE_RD_MAX_OUTSTAND                                  0x540100
+
+#define mmDMA2_CORE_RD_MAX_SIZE                                      0x540104
+
+#define mmDMA2_CORE_RD_ARCACHE                                       0x540108
+
+#define mmDMA2_CORE_RD_ARUSER_31_11                                  0x540110
+
+#define mmDMA2_CORE_RD_INFLIGHTS                                     0x540114
+
+#define mmDMA2_CORE_WR_MAX_OUTSTAND                                  0x540120
+
+#define mmDMA2_CORE_WR_MAX_AWID                                      0x540124
+
+#define mmDMA2_CORE_WR_AWCACHE                                       0x540128
+
+#define mmDMA2_CORE_WR_AWUSER_31_11                                  0x540130
+
+#define mmDMA2_CORE_WR_INFLIGHTS                                     0x540134
+
+#define mmDMA2_CORE_RD_RATE_LIM_CFG_0                                0x540150
+
+#define mmDMA2_CORE_RD_RATE_LIM_CFG_1                                0x540154
+
+#define mmDMA2_CORE_WR_RATE_LIM_CFG_0                                0x540158
+
+#define mmDMA2_CORE_WR_RATE_LIM_CFG_1                                0x54015C
+
+#define mmDMA2_CORE_ERR_CFG                                          0x540160
+
+#define mmDMA2_CORE_ERR_CAUSE                                        0x540164
+
+#define mmDMA2_CORE_ERRMSG_ADDR_LO                                   0x540170
+
+#define mmDMA2_CORE_ERRMSG_ADDR_HI                                   0x540174
+
+#define mmDMA2_CORE_ERRMSG_WDATA                                     0x540178
+
+#define mmDMA2_CORE_STS0                                             0x540190
+
+#define mmDMA2_CORE_STS1                                             0x540194
+
+#define mmDMA2_CORE_RD_DBGMEM_ADD                                    0x540200
+
+#define mmDMA2_CORE_RD_DBGMEM_DATA_WR                                0x540204
+
+#define mmDMA2_CORE_RD_DBGMEM_DATA_RD                                0x540208
+
+#define mmDMA2_CORE_RD_DBGMEM_CTRL                                   0x54020C
+
+#define mmDMA2_CORE_RD_DBGMEM_RC                                     0x540210
+
+#define mmDMA2_CORE_DBG_HBW_AXI_AR_CNT                               0x540220
+
+#define mmDMA2_CORE_DBG_HBW_AXI_AW_CNT                               0x540224
+
+#define mmDMA2_CORE_DBG_LBW_AXI_AW_CNT                               0x540228
+
+#define mmDMA2_CORE_DBG_DESC_CNT                                     0x54022C
+
+#define mmDMA2_CORE_DBG_STS                                          0x540230
+
+#define mmDMA2_CORE_DBG_RD_DESC_ID                                   0x540234
+
+#define mmDMA2_CORE_DBG_WR_DESC_ID                                   0x540238
+
+#endif /* ASIC_REG_DMA2_CORE_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma2_qm_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma2_qm_regs.h
new file mode 100644
index 000000000000..8c4d4e016852
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma2_qm_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DMA2_QM_REGS_H_
+#define ASIC_REG_DMA2_QM_REGS_H_
+
+/*
+ *****************************************
+ *   DMA2_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmDMA2_QM_GLBL_CFG0                                          0x548000
+
+#define mmDMA2_QM_GLBL_CFG1                                          0x548004
+
+#define mmDMA2_QM_GLBL_PROT                                          0x548008
+
+#define mmDMA2_QM_GLBL_ERR_CFG                                       0x54800C
+
+#define mmDMA2_QM_GLBL_SECURE_PROPS_0                                0x548010
+
+#define mmDMA2_QM_GLBL_SECURE_PROPS_1                                0x548014
+
+#define mmDMA2_QM_GLBL_SECURE_PROPS_2                                0x548018
+
+#define mmDMA2_QM_GLBL_SECURE_PROPS_3                                0x54801C
+
+#define mmDMA2_QM_GLBL_SECURE_PROPS_4                                0x548020
+
+#define mmDMA2_QM_GLBL_NON_SECURE_PROPS_0                            0x548024
+
+#define mmDMA2_QM_GLBL_NON_SECURE_PROPS_1                            0x548028
+
+#define mmDMA2_QM_GLBL_NON_SECURE_PROPS_2                            0x54802C
+
+#define mmDMA2_QM_GLBL_NON_SECURE_PROPS_3                            0x548030
+
+#define mmDMA2_QM_GLBL_NON_SECURE_PROPS_4                            0x548034
+
+#define mmDMA2_QM_GLBL_STS0                                          0x548038
+
+#define mmDMA2_QM_GLBL_STS1_0                                        0x548040
+
+#define mmDMA2_QM_GLBL_STS1_1                                        0x548044
+
+#define mmDMA2_QM_GLBL_STS1_2                                        0x548048
+
+#define mmDMA2_QM_GLBL_STS1_3                                        0x54804C
+
+#define mmDMA2_QM_GLBL_STS1_4                                        0x548050
+
+#define mmDMA2_QM_GLBL_MSG_EN_0                                      0x548054
+
+#define mmDMA2_QM_GLBL_MSG_EN_1                                      0x548058
+
+#define mmDMA2_QM_GLBL_MSG_EN_2                                      0x54805C
+
+#define mmDMA2_QM_GLBL_MSG_EN_3                                      0x548060
+
+#define mmDMA2_QM_GLBL_MSG_EN_4                                      0x548068
+
+#define mmDMA2_QM_PQ_BASE_LO_0                                       0x548070
+
+#define mmDMA2_QM_PQ_BASE_LO_1                                       0x548074
+
+#define mmDMA2_QM_PQ_BASE_LO_2                                       0x548078
+
+#define mmDMA2_QM_PQ_BASE_LO_3                                       0x54807C
+
+#define mmDMA2_QM_PQ_BASE_HI_0                                       0x548080
+
+#define mmDMA2_QM_PQ_BASE_HI_1                                       0x548084
+
+#define mmDMA2_QM_PQ_BASE_HI_2                                       0x548088
+
+#define mmDMA2_QM_PQ_BASE_HI_3                                       0x54808C
+
+#define mmDMA2_QM_PQ_SIZE_0                                          0x548090
+
+#define mmDMA2_QM_PQ_SIZE_1                                          0x548094
+
+#define mmDMA2_QM_PQ_SIZE_2                                          0x548098
+
+#define mmDMA2_QM_PQ_SIZE_3                                          0x54809C
+
+#define mmDMA2_QM_PQ_PI_0                                            0x5480A0
+
+#define mmDMA2_QM_PQ_PI_1                                            0x5480A4
+
+#define mmDMA2_QM_PQ_PI_2                                            0x5480A8
+
+#define mmDMA2_QM_PQ_PI_3                                            0x5480AC
+
+#define mmDMA2_QM_PQ_CI_0                                            0x5480B0
+
+#define mmDMA2_QM_PQ_CI_1                                            0x5480B4
+
+#define mmDMA2_QM_PQ_CI_2                                            0x5480B8
+
+#define mmDMA2_QM_PQ_CI_3                                            0x5480BC
+
+#define mmDMA2_QM_PQ_CFG0_0                                          0x5480C0
+
+#define mmDMA2_QM_PQ_CFG0_1                                          0x5480C4
+
+#define mmDMA2_QM_PQ_CFG0_2                                          0x5480C8
+
+#define mmDMA2_QM_PQ_CFG0_3                                          0x5480CC
+
+#define mmDMA2_QM_PQ_CFG1_0                                          0x5480D0
+
+#define mmDMA2_QM_PQ_CFG1_1                                          0x5480D4
+
+#define mmDMA2_QM_PQ_CFG1_2                                          0x5480D8
+
+#define mmDMA2_QM_PQ_CFG1_3                                          0x5480DC
+
+#define mmDMA2_QM_PQ_ARUSER_31_11_0                                  0x5480E0
+
+#define mmDMA2_QM_PQ_ARUSER_31_11_1                                  0x5480E4
+
+#define mmDMA2_QM_PQ_ARUSER_31_11_2                                  0x5480E8
+
+#define mmDMA2_QM_PQ_ARUSER_31_11_3                                  0x5480EC
+
+#define mmDMA2_QM_PQ_STS0_0                                          0x5480F0
+
+#define mmDMA2_QM_PQ_STS0_1                                          0x5480F4
+
+#define mmDMA2_QM_PQ_STS0_2                                          0x5480F8
+
+#define mmDMA2_QM_PQ_STS0_3                                          0x5480FC
+
+#define mmDMA2_QM_PQ_STS1_0                                          0x548100
+
+#define mmDMA2_QM_PQ_STS1_1                                          0x548104
+
+#define mmDMA2_QM_PQ_STS1_2                                          0x548108
+
+#define mmDMA2_QM_PQ_STS1_3                                          0x54810C
+
+#define mmDMA2_QM_CQ_CFG0_0                                          0x548110
+
+#define mmDMA2_QM_CQ_CFG0_1                                          0x548114
+
+#define mmDMA2_QM_CQ_CFG0_2                                          0x548118
+
+#define mmDMA2_QM_CQ_CFG0_3                                          0x54811C
+
+#define mmDMA2_QM_CQ_CFG0_4                                          0x548120
+
+#define mmDMA2_QM_CQ_CFG1_0                                          0x548124
+
+#define mmDMA2_QM_CQ_CFG1_1                                          0x548128
+
+#define mmDMA2_QM_CQ_CFG1_2                                          0x54812C
+
+#define mmDMA2_QM_CQ_CFG1_3                                          0x548130
+
+#define mmDMA2_QM_CQ_CFG1_4                                          0x548134
+
+#define mmDMA2_QM_CQ_ARUSER_31_11_0                                  0x548138
+
+#define mmDMA2_QM_CQ_ARUSER_31_11_1                                  0x54813C
+
+#define mmDMA2_QM_CQ_ARUSER_31_11_2                                  0x548140
+
+#define mmDMA2_QM_CQ_ARUSER_31_11_3                                  0x548144
+
+#define mmDMA2_QM_CQ_ARUSER_31_11_4                                  0x548148
+
+#define mmDMA2_QM_CQ_STS0_0                                          0x54814C
+
+#define mmDMA2_QM_CQ_STS0_1                                          0x548150
+
+#define mmDMA2_QM_CQ_STS0_2                                          0x548154
+
+#define mmDMA2_QM_CQ_STS0_3                                          0x548158
+
+#define mmDMA2_QM_CQ_STS0_4                                          0x54815C
+
+#define mmDMA2_QM_CQ_STS1_0                                          0x548160
+
+#define mmDMA2_QM_CQ_STS1_1                                          0x548164
+
+#define mmDMA2_QM_CQ_STS1_2                                          0x548168
+
+#define mmDMA2_QM_CQ_STS1_3                                          0x54816C
+
+#define mmDMA2_QM_CQ_STS1_4                                          0x548170
+
+#define mmDMA2_QM_CQ_PTR_LO_0                                        0x548174
+
+#define mmDMA2_QM_CQ_PTR_HI_0                                        0x548178
+
+#define mmDMA2_QM_CQ_TSIZE_0                                         0x54817C
+
+#define mmDMA2_QM_CQ_CTL_0                                           0x548180
+
+#define mmDMA2_QM_CQ_PTR_LO_1                                        0x548184
+
+#define mmDMA2_QM_CQ_PTR_HI_1                                        0x548188
+
+#define mmDMA2_QM_CQ_TSIZE_1                                         0x54818C
+
+#define mmDMA2_QM_CQ_CTL_1                                           0x548190
+
+#define mmDMA2_QM_CQ_PTR_LO_2                                        0x548194
+
+#define mmDMA2_QM_CQ_PTR_HI_2                                        0x548198
+
+#define mmDMA2_QM_CQ_TSIZE_2                                         0x54819C
+
+#define mmDMA2_QM_CQ_CTL_2                                           0x5481A0
+
+#define mmDMA2_QM_CQ_PTR_LO_3                                        0x5481A4
+
+#define mmDMA2_QM_CQ_PTR_HI_3                                        0x5481A8
+
+#define mmDMA2_QM_CQ_TSIZE_3                                         0x5481AC
+
+#define mmDMA2_QM_CQ_CTL_3                                           0x5481B0
+
+#define mmDMA2_QM_CQ_PTR_LO_4                                        0x5481B4
+
+#define mmDMA2_QM_CQ_PTR_HI_4                                        0x5481B8
+
+#define mmDMA2_QM_CQ_TSIZE_4                                         0x5481BC
+
+#define mmDMA2_QM_CQ_CTL_4                                           0x5481C0
+
+#define mmDMA2_QM_CQ_PTR_LO_STS_0                                    0x5481C4
+
+#define mmDMA2_QM_CQ_PTR_LO_STS_1                                    0x5481C8
+
+#define mmDMA2_QM_CQ_PTR_LO_STS_2                                    0x5481CC
+
+#define mmDMA2_QM_CQ_PTR_LO_STS_3                                    0x5481D0
+
+#define mmDMA2_QM_CQ_PTR_LO_STS_4                                    0x5481D4
+
+#define mmDMA2_QM_CQ_PTR_HI_STS_0                                    0x5481D8
+
+#define mmDMA2_QM_CQ_PTR_HI_STS_1                                    0x5481DC
+
+#define mmDMA2_QM_CQ_PTR_HI_STS_2                                    0x5481E0
+
+#define mmDMA2_QM_CQ_PTR_HI_STS_3                                    0x5481E4
+
+#define mmDMA2_QM_CQ_PTR_HI_STS_4                                    0x5481E8
+
+#define mmDMA2_QM_CQ_TSIZE_STS_0                                     0x5481EC
+
+#define mmDMA2_QM_CQ_TSIZE_STS_1                                     0x5481F0
+
+#define mmDMA2_QM_CQ_TSIZE_STS_2                                     0x5481F4
+
+#define mmDMA2_QM_CQ_TSIZE_STS_3                                     0x5481F8
+
+#define mmDMA2_QM_CQ_TSIZE_STS_4                                     0x5481FC
+
+#define mmDMA2_QM_CQ_CTL_STS_0                                       0x548200
+
+#define mmDMA2_QM_CQ_CTL_STS_1                                       0x548204
+
+#define mmDMA2_QM_CQ_CTL_STS_2                                       0x548208
+
+#define mmDMA2_QM_CQ_CTL_STS_3                                       0x54820C
+
+#define mmDMA2_QM_CQ_CTL_STS_4                                       0x548210
+
+#define mmDMA2_QM_CQ_IFIFO_CNT_0                                     0x548214
+
+#define mmDMA2_QM_CQ_IFIFO_CNT_1                                     0x548218
+
+#define mmDMA2_QM_CQ_IFIFO_CNT_2                                     0x54821C
+
+#define mmDMA2_QM_CQ_IFIFO_CNT_3                                     0x548220
+
+#define mmDMA2_QM_CQ_IFIFO_CNT_4                                     0x548224
+
+#define mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_0                             0x548228
+
+#define mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_1                             0x54822C
+
+#define mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_2                             0x548230
+
+#define mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_3                             0x548234
+
+#define mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_4                             0x548238
+
+#define mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_0                             0x54823C
+
+#define mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_1                             0x548240
+
+#define mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_2                             0x548244
+
+#define mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_3                             0x548248
+
+#define mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_4                             0x54824C
+
+#define mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_0                             0x548250
+
+#define mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_1                             0x548254
+
+#define mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_2                             0x548258
+
+#define mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_3                             0x54825C
+
+#define mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_4                             0x548260
+
+#define mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_0                             0x548264
+
+#define mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_1                             0x548268
+
+#define mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_2                             0x54826C
+
+#define mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_3                             0x548270
+
+#define mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_4                             0x548274
+
+#define mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_0                             0x548278
+
+#define mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_1                             0x54827C
+
+#define mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_2                             0x548280
+
+#define mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_3                             0x548284
+
+#define mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_4                             0x548288
+
+#define mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_0                             0x54828C
+
+#define mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_1                             0x548290
+
+#define mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_2                             0x548294
+
+#define mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_3                             0x548298
+
+#define mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_4                             0x54829C
+
+#define mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_0                             0x5482A0
+
+#define mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_1                             0x5482A4
+
+#define mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_2                             0x5482A8
+
+#define mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_3                             0x5482AC
+
+#define mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_4                             0x5482B0
+
+#define mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_0                             0x5482B4
+
+#define mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_1                             0x5482B8
+
+#define mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_2                             0x5482BC
+
+#define mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_3                             0x5482C0
+
+#define mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_4                             0x5482C4
+
+#define mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_0                             0x5482C8
+
+#define mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_1                             0x5482CC
+
+#define mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_2                             0x5482D0
+
+#define mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_3                             0x5482D4
+
+#define mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_4                             0x5482D8
+
+#define mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0                       0x5482E0
+
+#define mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1                       0x5482E4
+
+#define mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2                       0x5482E8
+
+#define mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3                       0x5482EC
+
+#define mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4                       0x5482F0
+
+#define mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_0                       0x5482F4
+
+#define mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_1                       0x5482F8
+
+#define mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_2                       0x5482FC
+
+#define mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3                       0x548300
+
+#define mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_4                       0x548304
+
+#define mmDMA2_QM_CP_FENCE0_RDATA_0                                  0x548308
+
+#define mmDMA2_QM_CP_FENCE0_RDATA_1                                  0x54830C
+
+#define mmDMA2_QM_CP_FENCE0_RDATA_2                                  0x548310
+
+#define mmDMA2_QM_CP_FENCE0_RDATA_3                                  0x548314
+
+#define mmDMA2_QM_CP_FENCE0_RDATA_4                                  0x548318
+
+#define mmDMA2_QM_CP_FENCE1_RDATA_0                                  0x54831C
+
+#define mmDMA2_QM_CP_FENCE1_RDATA_1                                  0x548320
+
+#define mmDMA2_QM_CP_FENCE1_RDATA_2                                  0x548324
+
+#define mmDMA2_QM_CP_FENCE1_RDATA_3                                  0x548328
+
+#define mmDMA2_QM_CP_FENCE1_RDATA_4                                  0x54832C
+
+#define mmDMA2_QM_CP_FENCE2_RDATA_0                                  0x548330
+
+#define mmDMA2_QM_CP_FENCE2_RDATA_1                                  0x548334
+
+#define mmDMA2_QM_CP_FENCE2_RDATA_2                                  0x548338
+
+#define mmDMA2_QM_CP_FENCE2_RDATA_3                                  0x54833C
+
+#define mmDMA2_QM_CP_FENCE2_RDATA_4                                  0x548340
+
+#define mmDMA2_QM_CP_FENCE3_RDATA_0                                  0x548344
+
+#define mmDMA2_QM_CP_FENCE3_RDATA_1                                  0x548348
+
+#define mmDMA2_QM_CP_FENCE3_RDATA_2                                  0x54834C
+
+#define mmDMA2_QM_CP_FENCE3_RDATA_3                                  0x548350
+
+#define mmDMA2_QM_CP_FENCE3_RDATA_4                                  0x548354
+
+#define mmDMA2_QM_CP_FENCE0_CNT_0                                    0x548358
+
+#define mmDMA2_QM_CP_FENCE0_CNT_1                                    0x54835C
+
+#define mmDMA2_QM_CP_FENCE0_CNT_2                                    0x548360
+
+#define mmDMA2_QM_CP_FENCE0_CNT_3                                    0x548364
+
+#define mmDMA2_QM_CP_FENCE0_CNT_4                                    0x548368
+
+#define mmDMA2_QM_CP_FENCE1_CNT_0                                    0x54836C
+
+#define mmDMA2_QM_CP_FENCE1_CNT_1                                    0x548370
+
+#define mmDMA2_QM_CP_FENCE1_CNT_2                                    0x548374
+
+#define mmDMA2_QM_CP_FENCE1_CNT_3                                    0x548378
+
+#define mmDMA2_QM_CP_FENCE1_CNT_4                                    0x54837C
+
+#define mmDMA2_QM_CP_FENCE2_CNT_0                                    0x548380
+
+#define mmDMA2_QM_CP_FENCE2_CNT_1                                    0x548384
+
+#define mmDMA2_QM_CP_FENCE2_CNT_2                                    0x548388
+
+#define mmDMA2_QM_CP_FENCE2_CNT_3                                    0x54838C
+
+#define mmDMA2_QM_CP_FENCE2_CNT_4                                    0x548390
+
+#define mmDMA2_QM_CP_FENCE3_CNT_0                                    0x548394
+
+#define mmDMA2_QM_CP_FENCE3_CNT_1                                    0x548398
+
+#define mmDMA2_QM_CP_FENCE3_CNT_2                                    0x54839C
+
+#define mmDMA2_QM_CP_FENCE3_CNT_3                                    0x5483A0
+
+#define mmDMA2_QM_CP_FENCE3_CNT_4                                    0x5483A4
+
+#define mmDMA2_QM_CP_STS_0                                           0x5483A8
+
+#define mmDMA2_QM_CP_STS_1                                           0x5483AC
+
+#define mmDMA2_QM_CP_STS_2                                           0x5483B0
+
+#define mmDMA2_QM_CP_STS_3                                           0x5483B4
+
+#define mmDMA2_QM_CP_STS_4                                           0x5483B8
+
+#define mmDMA2_QM_CP_CURRENT_INST_LO_0                               0x5483BC
+
+#define mmDMA2_QM_CP_CURRENT_INST_LO_1                               0x5483C0
+
+#define mmDMA2_QM_CP_CURRENT_INST_LO_2                               0x5483C4
+
+#define mmDMA2_QM_CP_CURRENT_INST_LO_3                               0x5483C8
+
+#define mmDMA2_QM_CP_CURRENT_INST_LO_4                               0x5483CC
+
+#define mmDMA2_QM_CP_CURRENT_INST_HI_0                               0x5483D0
+
+#define mmDMA2_QM_CP_CURRENT_INST_HI_1                               0x5483D4
+
+#define mmDMA2_QM_CP_CURRENT_INST_HI_2                               0x5483D8
+
+#define mmDMA2_QM_CP_CURRENT_INST_HI_3                               0x5483DC
+
+#define mmDMA2_QM_CP_CURRENT_INST_HI_4                               0x5483E0
+
+#define mmDMA2_QM_CP_BARRIER_CFG_0                                   0x5483F4
+
+#define mmDMA2_QM_CP_BARRIER_CFG_1                                   0x5483F8
+
+#define mmDMA2_QM_CP_BARRIER_CFG_2                                   0x5483FC
+
+#define mmDMA2_QM_CP_BARRIER_CFG_3                                   0x548400
+
+#define mmDMA2_QM_CP_BARRIER_CFG_4                                   0x548404
+
+#define mmDMA2_QM_CP_DBG_0_0                                         0x548408
+
+#define mmDMA2_QM_CP_DBG_0_1                                         0x54840C
+
+#define mmDMA2_QM_CP_DBG_0_2                                         0x548410
+
+#define mmDMA2_QM_CP_DBG_0_3                                         0x548414
+
+#define mmDMA2_QM_CP_DBG_0_4                                         0x548418
+
+#define mmDMA2_QM_CP_ARUSER_31_11_0                                  0x54841C
+
+#define mmDMA2_QM_CP_ARUSER_31_11_1                                  0x548420
+
+#define mmDMA2_QM_CP_ARUSER_31_11_2                                  0x548424
+
+#define mmDMA2_QM_CP_ARUSER_31_11_3                                  0x548428
+
+#define mmDMA2_QM_CP_ARUSER_31_11_4                                  0x54842C
+
+#define mmDMA2_QM_CP_AWUSER_31_11_0                                  0x548430
+
+#define mmDMA2_QM_CP_AWUSER_31_11_1                                  0x548434
+
+#define mmDMA2_QM_CP_AWUSER_31_11_2                                  0x548438
+
+#define mmDMA2_QM_CP_AWUSER_31_11_3                                  0x54843C
+
+#define mmDMA2_QM_CP_AWUSER_31_11_4                                  0x548440
+
+#define mmDMA2_QM_ARB_CFG_0                                          0x548A00
+
+#define mmDMA2_QM_ARB_CHOISE_Q_PUSH                                  0x548A04
+
+#define mmDMA2_QM_ARB_WRR_WEIGHT_0                                   0x548A08
+
+#define mmDMA2_QM_ARB_WRR_WEIGHT_1                                   0x548A0C
+
+#define mmDMA2_QM_ARB_WRR_WEIGHT_2                                   0x548A10
+
+#define mmDMA2_QM_ARB_WRR_WEIGHT_3                                   0x548A14
+
+#define mmDMA2_QM_ARB_CFG_1                                          0x548A18
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_0                               0x548A20
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_1                               0x548A24
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_2                               0x548A28
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_3                               0x548A2C
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_4                               0x548A30
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_5                               0x548A34
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_6                               0x548A38
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_7                               0x548A3C
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_8                               0x548A40
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_9                               0x548A44
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_10                              0x548A48
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_11                              0x548A4C
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_12                              0x548A50
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_13                              0x548A54
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_14                              0x548A58
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_15                              0x548A5C
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_16                              0x548A60
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_17                              0x548A64
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_18                              0x548A68
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_19                              0x548A6C
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_20                              0x548A70
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_21                              0x548A74
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_22                              0x548A78
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_23                              0x548A7C
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_24                              0x548A80
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_25                              0x548A84
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_26                              0x548A88
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_27                              0x548A8C
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_28                              0x548A90
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_29                              0x548A94
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_30                              0x548A98
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_31                              0x548A9C
+
+#define mmDMA2_QM_ARB_MST_CRED_INC                                   0x548AA0
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_0                         0x548AA4
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_1                         0x548AA8
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_2                         0x548AAC
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_3                         0x548AB0
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_4                         0x548AB4
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_5                         0x548AB8
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_6                         0x548ABC
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_7                         0x548AC0
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_8                         0x548AC4
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_9                         0x548AC8
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_10                        0x548ACC
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_11                        0x548AD0
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_12                        0x548AD4
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_13                        0x548AD8
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_14                        0x548ADC
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_15                        0x548AE0
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_16                        0x548AE4
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_17                        0x548AE8
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_18                        0x548AEC
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_19                        0x548AF0
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_20                        0x548AF4
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_21                        0x548AF8
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_22                        0x548AFC
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_23                        0x548B00
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_24                        0x548B04
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_25                        0x548B08
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_26                        0x548B0C
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_27                        0x548B10
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_28                        0x548B14
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_29                        0x548B18
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_30                        0x548B1C
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_31                        0x548B20
+
+#define mmDMA2_QM_ARB_SLV_MASTER_INC_CRED_OFST                       0x548B28
+
+#define mmDMA2_QM_ARB_MST_SLAVE_EN                                   0x548B2C
+
+#define mmDMA2_QM_ARB_MST_QUIET_PER                                  0x548B34
+
+#define mmDMA2_QM_ARB_SLV_CHOISE_WDT                                 0x548B38
+
+#define mmDMA2_QM_ARB_SLV_ID                                         0x548B3C
+
+#define mmDMA2_QM_ARB_MSG_MAX_INFLIGHT                               0x548B44
+
+#define mmDMA2_QM_ARB_MSG_AWUSER_31_11                               0x548B48
+
+#define mmDMA2_QM_ARB_MSG_AWUSER_SEC_PROP                            0x548B4C
+
+#define mmDMA2_QM_ARB_MSG_AWUSER_NON_SEC_PROP                        0x548B50
+
+#define mmDMA2_QM_ARB_BASE_LO                                        0x548B54
+
+#define mmDMA2_QM_ARB_BASE_HI                                        0x548B58
+
+#define mmDMA2_QM_ARB_STATE_STS                                      0x548B80
+
+#define mmDMA2_QM_ARB_CHOISE_FULLNESS_STS                            0x548B84
+
+#define mmDMA2_QM_ARB_MSG_STS                                        0x548B88
+
+#define mmDMA2_QM_ARB_SLV_CHOISE_Q_HEAD                              0x548B8C
+
+#define mmDMA2_QM_ARB_ERR_CAUSE                                      0x548B9C
+
+#define mmDMA2_QM_ARB_ERR_MSG_EN                                     0x548BA0
+
+#define mmDMA2_QM_ARB_ERR_STS_DRP                                    0x548BA8
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_0                                 0x548BB0
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_1                                 0x548BB4
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_2                                 0x548BB8
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_3                                 0x548BBC
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_4                                 0x548BC0
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_5                                 0x548BC4
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_6                                 0x548BC8
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_7                                 0x548BCC
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_8                                 0x548BD0
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_9                                 0x548BD4
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_10                                0x548BD8
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_11                                0x548BDC
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_12                                0x548BE0
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_13                                0x548BE4
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_14                                0x548BE8
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_15                                0x548BEC
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_16                                0x548BF0
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_17                                0x548BF4
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_18                                0x548BF8
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_19                                0x548BFC
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_20                                0x548C00
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_21                                0x548C04
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_22                                0x548C08
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_23                                0x548C0C
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_24                                0x548C10
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_25                                0x548C14
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_26                                0x548C18
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_27                                0x548C1C
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_28                                0x548C20
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_29                                0x548C24
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_30                                0x548C28
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_31                                0x548C2C
+
+#define mmDMA2_QM_CGM_CFG                                            0x548C70
+
+#define mmDMA2_QM_CGM_STS                                            0x548C74
+
+#define mmDMA2_QM_CGM_CFG1                                           0x548C78
+
+#define mmDMA2_QM_LOCAL_RANGE_BASE                                   0x548C80
+
+#define mmDMA2_QM_LOCAL_RANGE_SIZE                                   0x548C84
+
+#define mmDMA2_QM_CSMR_STRICT_PRIO_CFG                               0x548C90
+
+#define mmDMA2_QM_HBW_RD_RATE_LIM_CFG_1                              0x548C94
+
+#define mmDMA2_QM_LBW_WR_RATE_LIM_CFG_0                              0x548C98
+
+#define mmDMA2_QM_LBW_WR_RATE_LIM_CFG_1                              0x548C9C
+
+#define mmDMA2_QM_HBW_RD_RATE_LIM_CFG_0                              0x548CA0
+
+#define mmDMA2_QM_GLBL_AXCACHE                                       0x548CA4
+
+#define mmDMA2_QM_IND_GW_APB_CFG                                     0x548CB0
+
+#define mmDMA2_QM_IND_GW_APB_WDATA                                   0x548CB4
+
+#define mmDMA2_QM_IND_GW_APB_RDATA                                   0x548CB8
+
+#define mmDMA2_QM_IND_GW_APB_STATUS                                  0x548CBC
+
+#define mmDMA2_QM_GLBL_ERR_ADDR_LO                                   0x548CD0
+
+#define mmDMA2_QM_GLBL_ERR_ADDR_HI                                   0x548CD4
+
+#define mmDMA2_QM_GLBL_ERR_WDATA                                     0x548CD8
+
+#define mmDMA2_QM_GLBL_MEM_INIT_BUSY                                 0x548D00
+
+#endif /* ASIC_REG_DMA2_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma3_core_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma3_core_regs.h
new file mode 100644
index 000000000000..fb145f416fe6
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma3_core_regs.h
@@ -0,0 +1,156 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DMA3_CORE_REGS_H_
+#define ASIC_REG_DMA3_CORE_REGS_H_
+
+/*
+ *****************************************
+ *   DMA3_CORE (Prototype: DMA_CORE)
+ *****************************************
+ */
+
+#define mmDMA3_CORE_CFG_0                                            0x560000
+
+#define mmDMA3_CORE_CFG_1                                            0x560004
+
+#define mmDMA3_CORE_LBW_MAX_OUTSTAND                                 0x560008
+
+#define mmDMA3_CORE_SRC_BASE_LO                                      0x560014
+
+#define mmDMA3_CORE_SRC_BASE_HI                                      0x560018
+
+#define mmDMA3_CORE_DST_BASE_LO                                      0x56001C
+
+#define mmDMA3_CORE_DST_BASE_HI                                      0x560020
+
+#define mmDMA3_CORE_SRC_TSIZE_1                                      0x56002C
+
+#define mmDMA3_CORE_SRC_STRIDE_1                                     0x560030
+
+#define mmDMA3_CORE_SRC_TSIZE_2                                      0x560034
+
+#define mmDMA3_CORE_SRC_STRIDE_2                                     0x560038
+
+#define mmDMA3_CORE_SRC_TSIZE_3                                      0x56003C
+
+#define mmDMA3_CORE_SRC_STRIDE_3                                     0x560040
+
+#define mmDMA3_CORE_SRC_TSIZE_4                                      0x560044
+
+#define mmDMA3_CORE_SRC_STRIDE_4                                     0x560048
+
+#define mmDMA3_CORE_SRC_TSIZE_0                                      0x56004C
+
+#define mmDMA3_CORE_DST_TSIZE_1                                      0x560054
+
+#define mmDMA3_CORE_DST_STRIDE_1                                     0x560058
+
+#define mmDMA3_CORE_DST_TSIZE_2                                      0x56005C
+
+#define mmDMA3_CORE_DST_STRIDE_2                                     0x560060
+
+#define mmDMA3_CORE_DST_TSIZE_3                                      0x560064
+
+#define mmDMA3_CORE_DST_STRIDE_3                                     0x560068
+
+#define mmDMA3_CORE_DST_TSIZE_4                                      0x56006C
+
+#define mmDMA3_CORE_DST_STRIDE_4                                     0x560070
+
+#define mmDMA3_CORE_DST_TSIZE_0                                      0x560074
+
+#define mmDMA3_CORE_COMMIT                                           0x560078
+
+#define mmDMA3_CORE_WR_COMP_WDATA                                    0x56007C
+
+#define mmDMA3_CORE_WR_COMP_ADDR_LO                                  0x560080
+
+#define mmDMA3_CORE_WR_COMP_ADDR_HI                                  0x560084
+
+#define mmDMA3_CORE_WR_COMP_AWUSER_31_11                             0x560088
+
+#define mmDMA3_CORE_TE_NUMROWS                                       0x560094
+
+#define mmDMA3_CORE_PROT                                             0x5600B8
+
+#define mmDMA3_CORE_SECURE_PROPS                                     0x5600F0
+
+#define mmDMA3_CORE_NON_SECURE_PROPS                                 0x5600F4
+
+#define mmDMA3_CORE_RD_MAX_OUTSTAND                                  0x560100
+
+#define mmDMA3_CORE_RD_MAX_SIZE                                      0x560104
+
+#define mmDMA3_CORE_RD_ARCACHE                                       0x560108
+
+#define mmDMA3_CORE_RD_ARUSER_31_11                                  0x560110
+
+#define mmDMA3_CORE_RD_INFLIGHTS                                     0x560114
+
+#define mmDMA3_CORE_WR_MAX_OUTSTAND                                  0x560120
+
+#define mmDMA3_CORE_WR_MAX_AWID                                      0x560124
+
+#define mmDMA3_CORE_WR_AWCACHE                                       0x560128
+
+#define mmDMA3_CORE_WR_AWUSER_31_11                                  0x560130
+
+#define mmDMA3_CORE_WR_INFLIGHTS                                     0x560134
+
+#define mmDMA3_CORE_RD_RATE_LIM_CFG_0                                0x560150
+
+#define mmDMA3_CORE_RD_RATE_LIM_CFG_1                                0x560154
+
+#define mmDMA3_CORE_WR_RATE_LIM_CFG_0                                0x560158
+
+#define mmDMA3_CORE_WR_RATE_LIM_CFG_1                                0x56015C
+
+#define mmDMA3_CORE_ERR_CFG                                          0x560160
+
+#define mmDMA3_CORE_ERR_CAUSE                                        0x560164
+
+#define mmDMA3_CORE_ERRMSG_ADDR_LO                                   0x560170
+
+#define mmDMA3_CORE_ERRMSG_ADDR_HI                                   0x560174
+
+#define mmDMA3_CORE_ERRMSG_WDATA                                     0x560178
+
+#define mmDMA3_CORE_STS0                                             0x560190
+
+#define mmDMA3_CORE_STS1                                             0x560194
+
+#define mmDMA3_CORE_RD_DBGMEM_ADD                                    0x560200
+
+#define mmDMA3_CORE_RD_DBGMEM_DATA_WR                                0x560204
+
+#define mmDMA3_CORE_RD_DBGMEM_DATA_RD                                0x560208
+
+#define mmDMA3_CORE_RD_DBGMEM_CTRL                                   0x56020C
+
+#define mmDMA3_CORE_RD_DBGMEM_RC                                     0x560210
+
+#define mmDMA3_CORE_DBG_HBW_AXI_AR_CNT                               0x560220
+
+#define mmDMA3_CORE_DBG_HBW_AXI_AW_CNT                               0x560224
+
+#define mmDMA3_CORE_DBG_LBW_AXI_AW_CNT                               0x560228
+
+#define mmDMA3_CORE_DBG_DESC_CNT                                     0x56022C
+
+#define mmDMA3_CORE_DBG_STS                                          0x560230
+
+#define mmDMA3_CORE_DBG_RD_DESC_ID                                   0x560234
+
+#define mmDMA3_CORE_DBG_WR_DESC_ID                                   0x560238
+
+#endif /* ASIC_REG_DMA3_CORE_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma3_qm_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma3_qm_regs.h
new file mode 100644
index 000000000000..a4b461ca3d94
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma3_qm_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DMA3_QM_REGS_H_
+#define ASIC_REG_DMA3_QM_REGS_H_
+
+/*
+ *****************************************
+ *   DMA3_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmDMA3_QM_GLBL_CFG0                                          0x568000
+
+#define mmDMA3_QM_GLBL_CFG1                                          0x568004
+
+#define mmDMA3_QM_GLBL_PROT                                          0x568008
+
+#define mmDMA3_QM_GLBL_ERR_CFG                                       0x56800C
+
+#define mmDMA3_QM_GLBL_SECURE_PROPS_0                                0x568010
+
+#define mmDMA3_QM_GLBL_SECURE_PROPS_1                                0x568014
+
+#define mmDMA3_QM_GLBL_SECURE_PROPS_2                                0x568018
+
+#define mmDMA3_QM_GLBL_SECURE_PROPS_3                                0x56801C
+
+#define mmDMA3_QM_GLBL_SECURE_PROPS_4                                0x568020
+
+#define mmDMA3_QM_GLBL_NON_SECURE_PROPS_0                            0x568024
+
+#define mmDMA3_QM_GLBL_NON_SECURE_PROPS_1                            0x568028
+
+#define mmDMA3_QM_GLBL_NON_SECURE_PROPS_2                            0x56802C
+
+#define mmDMA3_QM_GLBL_NON_SECURE_PROPS_3                            0x568030
+
+#define mmDMA3_QM_GLBL_NON_SECURE_PROPS_4                            0x568034
+
+#define mmDMA3_QM_GLBL_STS0                                          0x568038
+
+#define mmDMA3_QM_GLBL_STS1_0                                        0x568040
+
+#define mmDMA3_QM_GLBL_STS1_1                                        0x568044
+
+#define mmDMA3_QM_GLBL_STS1_2                                        0x568048
+
+#define mmDMA3_QM_GLBL_STS1_3                                        0x56804C
+
+#define mmDMA3_QM_GLBL_STS1_4                                        0x568050
+
+#define mmDMA3_QM_GLBL_MSG_EN_0                                      0x568054
+
+#define mmDMA3_QM_GLBL_MSG_EN_1                                      0x568058
+
+#define mmDMA3_QM_GLBL_MSG_EN_2                                      0x56805C
+
+#define mmDMA3_QM_GLBL_MSG_EN_3                                      0x568060
+
+#define mmDMA3_QM_GLBL_MSG_EN_4                                      0x568068
+
+#define mmDMA3_QM_PQ_BASE_LO_0                                       0x568070
+
+#define mmDMA3_QM_PQ_BASE_LO_1                                       0x568074
+
+#define mmDMA3_QM_PQ_BASE_LO_2                                       0x568078
+
+#define mmDMA3_QM_PQ_BASE_LO_3                                       0x56807C
+
+#define mmDMA3_QM_PQ_BASE_HI_0                                       0x568080
+
+#define mmDMA3_QM_PQ_BASE_HI_1                                       0x568084
+
+#define mmDMA3_QM_PQ_BASE_HI_2                                       0x568088
+
+#define mmDMA3_QM_PQ_BASE_HI_3                                       0x56808C
+
+#define mmDMA3_QM_PQ_SIZE_0                                          0x568090
+
+#define mmDMA3_QM_PQ_SIZE_1                                          0x568094
+
+#define mmDMA3_QM_PQ_SIZE_2                                          0x568098
+
+#define mmDMA3_QM_PQ_SIZE_3                                          0x56809C
+
+#define mmDMA3_QM_PQ_PI_0                                            0x5680A0
+
+#define mmDMA3_QM_PQ_PI_1                                            0x5680A4
+
+#define mmDMA3_QM_PQ_PI_2                                            0x5680A8
+
+#define mmDMA3_QM_PQ_PI_3                                            0x5680AC
+
+#define mmDMA3_QM_PQ_CI_0                                            0x5680B0
+
+#define mmDMA3_QM_PQ_CI_1                                            0x5680B4
+
+#define mmDMA3_QM_PQ_CI_2                                            0x5680B8
+
+#define mmDMA3_QM_PQ_CI_3                                            0x5680BC
+
+#define mmDMA3_QM_PQ_CFG0_0                                          0x5680C0
+
+#define mmDMA3_QM_PQ_CFG0_1                                          0x5680C4
+
+#define mmDMA3_QM_PQ_CFG0_2                                          0x5680C8
+
+#define mmDMA3_QM_PQ_CFG0_3                                          0x5680CC
+
+#define mmDMA3_QM_PQ_CFG1_0                                          0x5680D0
+
+#define mmDMA3_QM_PQ_CFG1_1                                          0x5680D4
+
+#define mmDMA3_QM_PQ_CFG1_2                                          0x5680D8
+
+#define mmDMA3_QM_PQ_CFG1_3                                          0x5680DC
+
+#define mmDMA3_QM_PQ_ARUSER_31_11_0                                  0x5680E0
+
+#define mmDMA3_QM_PQ_ARUSER_31_11_1                                  0x5680E4
+
+#define mmDMA3_QM_PQ_ARUSER_31_11_2                                  0x5680E8
+
+#define mmDMA3_QM_PQ_ARUSER_31_11_3                                  0x5680EC
+
+#define mmDMA3_QM_PQ_STS0_0                                          0x5680F0
+
+#define mmDMA3_QM_PQ_STS0_1                                          0x5680F4
+
+#define mmDMA3_QM_PQ_STS0_2                                          0x5680F8
+
+#define mmDMA3_QM_PQ_STS0_3                                          0x5680FC
+
+#define mmDMA3_QM_PQ_STS1_0                                          0x568100
+
+#define mmDMA3_QM_PQ_STS1_1                                          0x568104
+
+#define mmDMA3_QM_PQ_STS1_2                                          0x568108
+
+#define mmDMA3_QM_PQ_STS1_3                                          0x56810C
+
+#define mmDMA3_QM_CQ_CFG0_0                                          0x568110
+
+#define mmDMA3_QM_CQ_CFG0_1                                          0x568114
+
+#define mmDMA3_QM_CQ_CFG0_2                                          0x568118
+
+#define mmDMA3_QM_CQ_CFG0_3                                          0x56811C
+
+#define mmDMA3_QM_CQ_CFG0_4                                          0x568120
+
+#define mmDMA3_QM_CQ_CFG1_0                                          0x568124
+
+#define mmDMA3_QM_CQ_CFG1_1                                          0x568128
+
+#define mmDMA3_QM_CQ_CFG1_2                                          0x56812C
+
+#define mmDMA3_QM_CQ_CFG1_3                                          0x568130
+
+#define mmDMA3_QM_CQ_CFG1_4                                          0x568134
+
+#define mmDMA3_QM_CQ_ARUSER_31_11_0                                  0x568138
+
+#define mmDMA3_QM_CQ_ARUSER_31_11_1                                  0x56813C
+
+#define mmDMA3_QM_CQ_ARUSER_31_11_2                                  0x568140
+
+#define mmDMA3_QM_CQ_ARUSER_31_11_3                                  0x568144
+
+#define mmDMA3_QM_CQ_ARUSER_31_11_4                                  0x568148
+
+#define mmDMA3_QM_CQ_STS0_0                                          0x56814C
+
+#define mmDMA3_QM_CQ_STS0_1                                          0x568150
+
+#define mmDMA3_QM_CQ_STS0_2                                          0x568154
+
+#define mmDMA3_QM_CQ_STS0_3                                          0x568158
+
+#define mmDMA3_QM_CQ_STS0_4                                          0x56815C
+
+#define mmDMA3_QM_CQ_STS1_0                                          0x568160
+
+#define mmDMA3_QM_CQ_STS1_1                                          0x568164
+
+#define mmDMA3_QM_CQ_STS1_2                                          0x568168
+
+#define mmDMA3_QM_CQ_STS1_3                                          0x56816C
+
+#define mmDMA3_QM_CQ_STS1_4                                          0x568170
+
+#define mmDMA3_QM_CQ_PTR_LO_0                                        0x568174
+
+#define mmDMA3_QM_CQ_PTR_HI_0                                        0x568178
+
+#define mmDMA3_QM_CQ_TSIZE_0                                         0x56817C
+
+#define mmDMA3_QM_CQ_CTL_0                                           0x568180
+
+#define mmDMA3_QM_CQ_PTR_LO_1                                        0x568184
+
+#define mmDMA3_QM_CQ_PTR_HI_1                                        0x568188
+
+#define mmDMA3_QM_CQ_TSIZE_1                                         0x56818C
+
+#define mmDMA3_QM_CQ_CTL_1                                           0x568190
+
+#define mmDMA3_QM_CQ_PTR_LO_2                                        0x568194
+
+#define mmDMA3_QM_CQ_PTR_HI_2                                        0x568198
+
+#define mmDMA3_QM_CQ_TSIZE_2                                         0x56819C
+
+#define mmDMA3_QM_CQ_CTL_2                                           0x5681A0
+
+#define mmDMA3_QM_CQ_PTR_LO_3                                        0x5681A4
+
+#define mmDMA3_QM_CQ_PTR_HI_3                                        0x5681A8
+
+#define mmDMA3_QM_CQ_TSIZE_3                                         0x5681AC
+
+#define mmDMA3_QM_CQ_CTL_3                                           0x5681B0
+
+#define mmDMA3_QM_CQ_PTR_LO_4                                        0x5681B4
+
+#define mmDMA3_QM_CQ_PTR_HI_4                                        0x5681B8
+
+#define mmDMA3_QM_CQ_TSIZE_4                                         0x5681BC
+
+#define mmDMA3_QM_CQ_CTL_4                                           0x5681C0
+
+#define mmDMA3_QM_CQ_PTR_LO_STS_0                                    0x5681C4
+
+#define mmDMA3_QM_CQ_PTR_LO_STS_1                                    0x5681C8
+
+#define mmDMA3_QM_CQ_PTR_LO_STS_2                                    0x5681CC
+
+#define mmDMA3_QM_CQ_PTR_LO_STS_3                                    0x5681D0
+
+#define mmDMA3_QM_CQ_PTR_LO_STS_4                                    0x5681D4
+
+#define mmDMA3_QM_CQ_PTR_HI_STS_0                                    0x5681D8
+
+#define mmDMA3_QM_CQ_PTR_HI_STS_1                                    0x5681DC
+
+#define mmDMA3_QM_CQ_PTR_HI_STS_2                                    0x5681E0
+
+#define mmDMA3_QM_CQ_PTR_HI_STS_3                                    0x5681E4
+
+#define mmDMA3_QM_CQ_PTR_HI_STS_4                                    0x5681E8
+
+#define mmDMA3_QM_CQ_TSIZE_STS_0                                     0x5681EC
+
+#define mmDMA3_QM_CQ_TSIZE_STS_1                                     0x5681F0
+
+#define mmDMA3_QM_CQ_TSIZE_STS_2                                     0x5681F4
+
+#define mmDMA3_QM_CQ_TSIZE_STS_3                                     0x5681F8
+
+#define mmDMA3_QM_CQ_TSIZE_STS_4                                     0x5681FC
+
+#define mmDMA3_QM_CQ_CTL_STS_0                                       0x568200
+
+#define mmDMA3_QM_CQ_CTL_STS_1                                       0x568204
+
+#define mmDMA3_QM_CQ_CTL_STS_2                                       0x568208
+
+#define mmDMA3_QM_CQ_CTL_STS_3                                       0x56820C
+
+#define mmDMA3_QM_CQ_CTL_STS_4                                       0x568210
+
+#define mmDMA3_QM_CQ_IFIFO_CNT_0                                     0x568214
+
+#define mmDMA3_QM_CQ_IFIFO_CNT_1                                     0x568218
+
+#define mmDMA3_QM_CQ_IFIFO_CNT_2                                     0x56821C
+
+#define mmDMA3_QM_CQ_IFIFO_CNT_3                                     0x568220
+
+#define mmDMA3_QM_CQ_IFIFO_CNT_4                                     0x568224
+
+#define mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_0                             0x568228
+
+#define mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_1                             0x56822C
+
+#define mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_2                             0x568230
+
+#define mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_3                             0x568234
+
+#define mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_4                             0x568238
+
+#define mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_0                             0x56823C
+
+#define mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_1                             0x568240
+
+#define mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_2                             0x568244
+
+#define mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_3                             0x568248
+
+#define mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_4                             0x56824C
+
+#define mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_0                             0x568250
+
+#define mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_1                             0x568254
+
+#define mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_2                             0x568258
+
+#define mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_3                             0x56825C
+
+#define mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_4                             0x568260
+
+#define mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_0                             0x568264
+
+#define mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_1                             0x568268
+
+#define mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_2                             0x56826C
+
+#define mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_3                             0x568270
+
+#define mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_4                             0x568274
+
+#define mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_0                             0x568278
+
+#define mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_1                             0x56827C
+
+#define mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_2                             0x568280
+
+#define mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_3                             0x568284
+
+#define mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_4                             0x568288
+
+#define mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_0                             0x56828C
+
+#define mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_1                             0x568290
+
+#define mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_2                             0x568294
+
+#define mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_3                             0x568298
+
+#define mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_4                             0x56829C
+
+#define mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_0                             0x5682A0
+
+#define mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_1                             0x5682A4
+
+#define mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_2                             0x5682A8
+
+#define mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_3                             0x5682AC
+
+#define mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_4                             0x5682B0
+
+#define mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_0                             0x5682B4
+
+#define mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_1                             0x5682B8
+
+#define mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_2                             0x5682BC
+
+#define mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_3                             0x5682C0
+
+#define mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_4                             0x5682C4
+
+#define mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_0                             0x5682C8
+
+#define mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_1                             0x5682CC
+
+#define mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_2                             0x5682D0
+
+#define mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_3                             0x5682D4
+
+#define mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_4                             0x5682D8
+
+#define mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0                       0x5682E0
+
+#define mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1                       0x5682E4
+
+#define mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2                       0x5682E8
+
+#define mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3                       0x5682EC
+
+#define mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4                       0x5682F0
+
+#define mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_0                       0x5682F4
+
+#define mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_1                       0x5682F8
+
+#define mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_2                       0x5682FC
+
+#define mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3                       0x568300
+
+#define mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_4                       0x568304
+
+#define mmDMA3_QM_CP_FENCE0_RDATA_0                                  0x568308
+
+#define mmDMA3_QM_CP_FENCE0_RDATA_1                                  0x56830C
+
+#define mmDMA3_QM_CP_FENCE0_RDATA_2                                  0x568310
+
+#define mmDMA3_QM_CP_FENCE0_RDATA_3                                  0x568314
+
+#define mmDMA3_QM_CP_FENCE0_RDATA_4                                  0x568318
+
+#define mmDMA3_QM_CP_FENCE1_RDATA_0                                  0x56831C
+
+#define mmDMA3_QM_CP_FENCE1_RDATA_1                                  0x568320
+
+#define mmDMA3_QM_CP_FENCE1_RDATA_2                                  0x568324
+
+#define mmDMA3_QM_CP_FENCE1_RDATA_3                                  0x568328
+
+#define mmDMA3_QM_CP_FENCE1_RDATA_4                                  0x56832C
+
+#define mmDMA3_QM_CP_FENCE2_RDATA_0                                  0x568330
+
+#define mmDMA3_QM_CP_FENCE2_RDATA_1                                  0x568334
+
+#define mmDMA3_QM_CP_FENCE2_RDATA_2                                  0x568338
+
+#define mmDMA3_QM_CP_FENCE2_RDATA_3                                  0x56833C
+
+#define mmDMA3_QM_CP_FENCE2_RDATA_4                                  0x568340
+
+#define mmDMA3_QM_CP_FENCE3_RDATA_0                                  0x568344
+
+#define mmDMA3_QM_CP_FENCE3_RDATA_1                                  0x568348
+
+#define mmDMA3_QM_CP_FENCE3_RDATA_2                                  0x56834C
+
+#define mmDMA3_QM_CP_FENCE3_RDATA_3                                  0x568350
+
+#define mmDMA3_QM_CP_FENCE3_RDATA_4                                  0x568354
+
+#define mmDMA3_QM_CP_FENCE0_CNT_0                                    0x568358
+
+#define mmDMA3_QM_CP_FENCE0_CNT_1                                    0x56835C
+
+#define mmDMA3_QM_CP_FENCE0_CNT_2                                    0x568360
+
+#define mmDMA3_QM_CP_FENCE0_CNT_3                                    0x568364
+
+#define mmDMA3_QM_CP_FENCE0_CNT_4                                    0x568368
+
+#define mmDMA3_QM_CP_FENCE1_CNT_0                                    0x56836C
+
+#define mmDMA3_QM_CP_FENCE1_CNT_1                                    0x568370
+
+#define mmDMA3_QM_CP_FENCE1_CNT_2                                    0x568374
+
+#define mmDMA3_QM_CP_FENCE1_CNT_3                                    0x568378
+
+#define mmDMA3_QM_CP_FENCE1_CNT_4                                    0x56837C
+
+#define mmDMA3_QM_CP_FENCE2_CNT_0                                    0x568380
+
+#define mmDMA3_QM_CP_FENCE2_CNT_1                                    0x568384
+
+#define mmDMA3_QM_CP_FENCE2_CNT_2                                    0x568388
+
+#define mmDMA3_QM_CP_FENCE2_CNT_3                                    0x56838C
+
+#define mmDMA3_QM_CP_FENCE2_CNT_4                                    0x568390
+
+#define mmDMA3_QM_CP_FENCE3_CNT_0                                    0x568394
+
+#define mmDMA3_QM_CP_FENCE3_CNT_1                                    0x568398
+
+#define mmDMA3_QM_CP_FENCE3_CNT_2                                    0x56839C
+
+#define mmDMA3_QM_CP_FENCE3_CNT_3                                    0x5683A0
+
+#define mmDMA3_QM_CP_FENCE3_CNT_4                                    0x5683A4
+
+#define mmDMA3_QM_CP_STS_0                                           0x5683A8
+
+#define mmDMA3_QM_CP_STS_1                                           0x5683AC
+
+#define mmDMA3_QM_CP_STS_2                                           0x5683B0
+
+#define mmDMA3_QM_CP_STS_3                                           0x5683B4
+
+#define mmDMA3_QM_CP_STS_4                                           0x5683B8
+
+#define mmDMA3_QM_CP_CURRENT_INST_LO_0                               0x5683BC
+
+#define mmDMA3_QM_CP_CURRENT_INST_LO_1                               0x5683C0
+
+#define mmDMA3_QM_CP_CURRENT_INST_LO_2                               0x5683C4
+
+#define mmDMA3_QM_CP_CURRENT_INST_LO_3                               0x5683C8
+
+#define mmDMA3_QM_CP_CURRENT_INST_LO_4                               0x5683CC
+
+#define mmDMA3_QM_CP_CURRENT_INST_HI_0                               0x5683D0
+
+#define mmDMA3_QM_CP_CURRENT_INST_HI_1                               0x5683D4
+
+#define mmDMA3_QM_CP_CURRENT_INST_HI_2                               0x5683D8
+
+#define mmDMA3_QM_CP_CURRENT_INST_HI_3                               0x5683DC
+
+#define mmDMA3_QM_CP_CURRENT_INST_HI_4                               0x5683E0
+
+#define mmDMA3_QM_CP_BARRIER_CFG_0                                   0x5683F4
+
+#define mmDMA3_QM_CP_BARRIER_CFG_1                                   0x5683F8
+
+#define mmDMA3_QM_CP_BARRIER_CFG_2                                   0x5683FC
+
+#define mmDMA3_QM_CP_BARRIER_CFG_3                                   0x568400
+
+#define mmDMA3_QM_CP_BARRIER_CFG_4                                   0x568404
+
+#define mmDMA3_QM_CP_DBG_0_0                                         0x568408
+
+#define mmDMA3_QM_CP_DBG_0_1                                         0x56840C
+
+#define mmDMA3_QM_CP_DBG_0_2                                         0x568410
+
+#define mmDMA3_QM_CP_DBG_0_3                                         0x568414
+
+#define mmDMA3_QM_CP_DBG_0_4                                         0x568418
+
+#define mmDMA3_QM_CP_ARUSER_31_11_0                                  0x56841C
+
+#define mmDMA3_QM_CP_ARUSER_31_11_1                                  0x568420
+
+#define mmDMA3_QM_CP_ARUSER_31_11_2                                  0x568424
+
+#define mmDMA3_QM_CP_ARUSER_31_11_3                                  0x568428
+
+#define mmDMA3_QM_CP_ARUSER_31_11_4                                  0x56842C
+
+#define mmDMA3_QM_CP_AWUSER_31_11_0                                  0x568430
+
+#define mmDMA3_QM_CP_AWUSER_31_11_1                                  0x568434
+
+#define mmDMA3_QM_CP_AWUSER_31_11_2                                  0x568438
+
+#define mmDMA3_QM_CP_AWUSER_31_11_3                                  0x56843C
+
+#define mmDMA3_QM_CP_AWUSER_31_11_4                                  0x568440
+
+#define mmDMA3_QM_ARB_CFG_0                                          0x568A00
+
+#define mmDMA3_QM_ARB_CHOISE_Q_PUSH                                  0x568A04
+
+#define mmDMA3_QM_ARB_WRR_WEIGHT_0                                   0x568A08
+
+#define mmDMA3_QM_ARB_WRR_WEIGHT_1                                   0x568A0C
+
+#define mmDMA3_QM_ARB_WRR_WEIGHT_2                                   0x568A10
+
+#define mmDMA3_QM_ARB_WRR_WEIGHT_3                                   0x568A14
+
+#define mmDMA3_QM_ARB_CFG_1                                          0x568A18
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_0                               0x568A20
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_1                               0x568A24
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_2                               0x568A28
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_3                               0x568A2C
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_4                               0x568A30
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_5                               0x568A34
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_6                               0x568A38
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_7                               0x568A3C
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_8                               0x568A40
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_9                               0x568A44
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_10                              0x568A48
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_11                              0x568A4C
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_12                              0x568A50
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_13                              0x568A54
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_14                              0x568A58
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_15                              0x568A5C
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_16                              0x568A60
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_17                              0x568A64
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_18                              0x568A68
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_19                              0x568A6C
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_20                              0x568A70
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_21                              0x568A74
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_22                              0x568A78
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_23                              0x568A7C
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_24                              0x568A80
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_25                              0x568A84
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_26                              0x568A88
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_27                              0x568A8C
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_28                              0x568A90
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_29                              0x568A94
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_30                              0x568A98
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_31                              0x568A9C
+
+#define mmDMA3_QM_ARB_MST_CRED_INC                                   0x568AA0
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_0                         0x568AA4
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_1                         0x568AA8
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_2                         0x568AAC
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_3                         0x568AB0
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_4                         0x568AB4
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_5                         0x568AB8
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_6                         0x568ABC
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_7                         0x568AC0
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_8                         0x568AC4
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_9                         0x568AC8
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_10                        0x568ACC
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_11                        0x568AD0
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_12                        0x568AD4
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_13                        0x568AD8
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_14                        0x568ADC
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_15                        0x568AE0
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_16                        0x568AE4
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_17                        0x568AE8
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_18                        0x568AEC
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_19                        0x568AF0
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_20                        0x568AF4
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_21                        0x568AF8
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_22                        0x568AFC
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_23                        0x568B00
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_24                        0x568B04
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_25                        0x568B08
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_26                        0x568B0C
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_27                        0x568B10
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_28                        0x568B14
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_29                        0x568B18
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_30                        0x568B1C
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_31                        0x568B20
+
+#define mmDMA3_QM_ARB_SLV_MASTER_INC_CRED_OFST                       0x568B28
+
+#define mmDMA3_QM_ARB_MST_SLAVE_EN                                   0x568B2C
+
+#define mmDMA3_QM_ARB_MST_QUIET_PER                                  0x568B34
+
+#define mmDMA3_QM_ARB_SLV_CHOISE_WDT                                 0x568B38
+
+#define mmDMA3_QM_ARB_SLV_ID                                         0x568B3C
+
+#define mmDMA3_QM_ARB_MSG_MAX_INFLIGHT                               0x568B44
+
+#define mmDMA3_QM_ARB_MSG_AWUSER_31_11                               0x568B48
+
+#define mmDMA3_QM_ARB_MSG_AWUSER_SEC_PROP                            0x568B4C
+
+#define mmDMA3_QM_ARB_MSG_AWUSER_NON_SEC_PROP                        0x568B50
+
+#define mmDMA3_QM_ARB_BASE_LO                                        0x568B54
+
+#define mmDMA3_QM_ARB_BASE_HI                                        0x568B58
+
+#define mmDMA3_QM_ARB_STATE_STS                                      0x568B80
+
+#define mmDMA3_QM_ARB_CHOISE_FULLNESS_STS                            0x568B84
+
+#define mmDMA3_QM_ARB_MSG_STS                                        0x568B88
+
+#define mmDMA3_QM_ARB_SLV_CHOISE_Q_HEAD                              0x568B8C
+
+#define mmDMA3_QM_ARB_ERR_CAUSE                                      0x568B9C
+
+#define mmDMA3_QM_ARB_ERR_MSG_EN                                     0x568BA0
+
+#define mmDMA3_QM_ARB_ERR_STS_DRP                                    0x568BA8
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_0                                 0x568BB0
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_1                                 0x568BB4
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_2                                 0x568BB8
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_3                                 0x568BBC
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_4                                 0x568BC0
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_5                                 0x568BC4
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_6                                 0x568BC8
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_7                                 0x568BCC
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_8                                 0x568BD0
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_9                                 0x568BD4
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_10                                0x568BD8
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_11                                0x568BDC
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_12                                0x568BE0
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_13                                0x568BE4
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_14                                0x568BE8
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_15                                0x568BEC
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_16                                0x568BF0
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_17                                0x568BF4
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_18                                0x568BF8
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_19                                0x568BFC
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_20                                0x568C00
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_21                                0x568C04
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_22                                0x568C08
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_23                                0x568C0C
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_24                                0x568C10
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_25                                0x568C14
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_26                                0x568C18
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_27                                0x568C1C
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_28                                0x568C20
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_29                                0x568C24
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_30                                0x568C28
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_31                                0x568C2C
+
+#define mmDMA3_QM_CGM_CFG                                            0x568C70
+
+#define mmDMA3_QM_CGM_STS                                            0x568C74
+
+#define mmDMA3_QM_CGM_CFG1                                           0x568C78
+
+#define mmDMA3_QM_LOCAL_RANGE_BASE                                   0x568C80
+
+#define mmDMA3_QM_LOCAL_RANGE_SIZE                                   0x568C84
+
+#define mmDMA3_QM_CSMR_STRICT_PRIO_CFG                               0x568C90
+
+#define mmDMA3_QM_HBW_RD_RATE_LIM_CFG_1                              0x568C94
+
+#define mmDMA3_QM_LBW_WR_RATE_LIM_CFG_0                              0x568C98
+
+#define mmDMA3_QM_LBW_WR_RATE_LIM_CFG_1                              0x568C9C
+
+#define mmDMA3_QM_HBW_RD_RATE_LIM_CFG_0                              0x568CA0
+
+#define mmDMA3_QM_GLBL_AXCACHE                                       0x568CA4
+
+#define mmDMA3_QM_IND_GW_APB_CFG                                     0x568CB0
+
+#define mmDMA3_QM_IND_GW_APB_WDATA                                   0x568CB4
+
+#define mmDMA3_QM_IND_GW_APB_RDATA                                   0x568CB8
+
+#define mmDMA3_QM_IND_GW_APB_STATUS                                  0x568CBC
+
+#define mmDMA3_QM_GLBL_ERR_ADDR_LO                                   0x568CD0
+
+#define mmDMA3_QM_GLBL_ERR_ADDR_HI                                   0x568CD4
+
+#define mmDMA3_QM_GLBL_ERR_WDATA                                     0x568CD8
+
+#define mmDMA3_QM_GLBL_MEM_INIT_BUSY                                 0x568D00
+
+#endif /* ASIC_REG_DMA3_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma4_core_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma4_core_regs.h
new file mode 100644
index 000000000000..192d11404b1c
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma4_core_regs.h
@@ -0,0 +1,156 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DMA4_CORE_REGS_H_
+#define ASIC_REG_DMA4_CORE_REGS_H_
+
+/*
+ *****************************************
+ *   DMA4_CORE (Prototype: DMA_CORE)
+ *****************************************
+ */
+
+#define mmDMA4_CORE_CFG_0                                            0x580000
+
+#define mmDMA4_CORE_CFG_1                                            0x580004
+
+#define mmDMA4_CORE_LBW_MAX_OUTSTAND                                 0x580008
+
+#define mmDMA4_CORE_SRC_BASE_LO                                      0x580014
+
+#define mmDMA4_CORE_SRC_BASE_HI                                      0x580018
+
+#define mmDMA4_CORE_DST_BASE_LO                                      0x58001C
+
+#define mmDMA4_CORE_DST_BASE_HI                                      0x580020
+
+#define mmDMA4_CORE_SRC_TSIZE_1                                      0x58002C
+
+#define mmDMA4_CORE_SRC_STRIDE_1                                     0x580030
+
+#define mmDMA4_CORE_SRC_TSIZE_2                                      0x580034
+
+#define mmDMA4_CORE_SRC_STRIDE_2                                     0x580038
+
+#define mmDMA4_CORE_SRC_TSIZE_3                                      0x58003C
+
+#define mmDMA4_CORE_SRC_STRIDE_3                                     0x580040
+
+#define mmDMA4_CORE_SRC_TSIZE_4                                      0x580044
+
+#define mmDMA4_CORE_SRC_STRIDE_4                                     0x580048
+
+#define mmDMA4_CORE_SRC_TSIZE_0                                      0x58004C
+
+#define mmDMA4_CORE_DST_TSIZE_1                                      0x580054
+
+#define mmDMA4_CORE_DST_STRIDE_1                                     0x580058
+
+#define mmDMA4_CORE_DST_TSIZE_2                                      0x58005C
+
+#define mmDMA4_CORE_DST_STRIDE_2                                     0x580060
+
+#define mmDMA4_CORE_DST_TSIZE_3                                      0x580064
+
+#define mmDMA4_CORE_DST_STRIDE_3                                     0x580068
+
+#define mmDMA4_CORE_DST_TSIZE_4                                      0x58006C
+
+#define mmDMA4_CORE_DST_STRIDE_4                                     0x580070
+
+#define mmDMA4_CORE_DST_TSIZE_0                                      0x580074
+
+#define mmDMA4_CORE_COMMIT                                           0x580078
+
+#define mmDMA4_CORE_WR_COMP_WDATA                                    0x58007C
+
+#define mmDMA4_CORE_WR_COMP_ADDR_LO                                  0x580080
+
+#define mmDMA4_CORE_WR_COMP_ADDR_HI                                  0x580084
+
+#define mmDMA4_CORE_WR_COMP_AWUSER_31_11                             0x580088
+
+#define mmDMA4_CORE_TE_NUMROWS                                       0x580094
+
+#define mmDMA4_CORE_PROT                                             0x5800B8
+
+#define mmDMA4_CORE_SECURE_PROPS                                     0x5800F0
+
+#define mmDMA4_CORE_NON_SECURE_PROPS                                 0x5800F4
+
+#define mmDMA4_CORE_RD_MAX_OUTSTAND                                  0x580100
+
+#define mmDMA4_CORE_RD_MAX_SIZE                                      0x580104
+
+#define mmDMA4_CORE_RD_ARCACHE                                       0x580108
+
+#define mmDMA4_CORE_RD_ARUSER_31_11                                  0x580110
+
+#define mmDMA4_CORE_RD_INFLIGHTS                                     0x580114
+
+#define mmDMA4_CORE_WR_MAX_OUTSTAND                                  0x580120
+
+#define mmDMA4_CORE_WR_MAX_AWID                                      0x580124
+
+#define mmDMA4_CORE_WR_AWCACHE                                       0x580128
+
+#define mmDMA4_CORE_WR_AWUSER_31_11                                  0x580130
+
+#define mmDMA4_CORE_WR_INFLIGHTS                                     0x580134
+
+#define mmDMA4_CORE_RD_RATE_LIM_CFG_0                                0x580150
+
+#define mmDMA4_CORE_RD_RATE_LIM_CFG_1                                0x580154
+
+#define mmDMA4_CORE_WR_RATE_LIM_CFG_0                                0x580158
+
+#define mmDMA4_CORE_WR_RATE_LIM_CFG_1                                0x58015C
+
+#define mmDMA4_CORE_ERR_CFG                                          0x580160
+
+#define mmDMA4_CORE_ERR_CAUSE                                        0x580164
+
+#define mmDMA4_CORE_ERRMSG_ADDR_LO                                   0x580170
+
+#define mmDMA4_CORE_ERRMSG_ADDR_HI                                   0x580174
+
+#define mmDMA4_CORE_ERRMSG_WDATA                                     0x580178
+
+#define mmDMA4_CORE_STS0                                             0x580190
+
+#define mmDMA4_CORE_STS1                                             0x580194
+
+#define mmDMA4_CORE_RD_DBGMEM_ADD                                    0x580200
+
+#define mmDMA4_CORE_RD_DBGMEM_DATA_WR                                0x580204
+
+#define mmDMA4_CORE_RD_DBGMEM_DATA_RD                                0x580208
+
+#define mmDMA4_CORE_RD_DBGMEM_CTRL                                   0x58020C
+
+#define mmDMA4_CORE_RD_DBGMEM_RC                                     0x580210
+
+#define mmDMA4_CORE_DBG_HBW_AXI_AR_CNT                               0x580220
+
+#define mmDMA4_CORE_DBG_HBW_AXI_AW_CNT                               0x580224
+
+#define mmDMA4_CORE_DBG_LBW_AXI_AW_CNT                               0x580228
+
+#define mmDMA4_CORE_DBG_DESC_CNT                                     0x58022C
+
+#define mmDMA4_CORE_DBG_STS                                          0x580230
+
+#define mmDMA4_CORE_DBG_RD_DESC_ID                                   0x580234
+
+#define mmDMA4_CORE_DBG_WR_DESC_ID                                   0x580238
+
+#endif /* ASIC_REG_DMA4_CORE_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma4_qm_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma4_qm_regs.h
new file mode 100644
index 000000000000..f0cbda0d1e4d
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma4_qm_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DMA4_QM_REGS_H_
+#define ASIC_REG_DMA4_QM_REGS_H_
+
+/*
+ *****************************************
+ *   DMA4_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmDMA4_QM_GLBL_CFG0                                          0x588000
+
+#define mmDMA4_QM_GLBL_CFG1                                          0x588004
+
+#define mmDMA4_QM_GLBL_PROT                                          0x588008
+
+#define mmDMA4_QM_GLBL_ERR_CFG                                       0x58800C
+
+#define mmDMA4_QM_GLBL_SECURE_PROPS_0                                0x588010
+
+#define mmDMA4_QM_GLBL_SECURE_PROPS_1                                0x588014
+
+#define mmDMA4_QM_GLBL_SECURE_PROPS_2                                0x588018
+
+#define mmDMA4_QM_GLBL_SECURE_PROPS_3                                0x58801C
+
+#define mmDMA4_QM_GLBL_SECURE_PROPS_4                                0x588020
+
+#define mmDMA4_QM_GLBL_NON_SECURE_PROPS_0                            0x588024
+
+#define mmDMA4_QM_GLBL_NON_SECURE_PROPS_1                            0x588028
+
+#define mmDMA4_QM_GLBL_NON_SECURE_PROPS_2                            0x58802C
+
+#define mmDMA4_QM_GLBL_NON_SECURE_PROPS_3                            0x588030
+
+#define mmDMA4_QM_GLBL_NON_SECURE_PROPS_4                            0x588034
+
+#define mmDMA4_QM_GLBL_STS0                                          0x588038
+
+#define mmDMA4_QM_GLBL_STS1_0                                        0x588040
+
+#define mmDMA4_QM_GLBL_STS1_1                                        0x588044
+
+#define mmDMA4_QM_GLBL_STS1_2                                        0x588048
+
+#define mmDMA4_QM_GLBL_STS1_3                                        0x58804C
+
+#define mmDMA4_QM_GLBL_STS1_4                                        0x588050
+
+#define mmDMA4_QM_GLBL_MSG_EN_0                                      0x588054
+
+#define mmDMA4_QM_GLBL_MSG_EN_1                                      0x588058
+
+#define mmDMA4_QM_GLBL_MSG_EN_2                                      0x58805C
+
+#define mmDMA4_QM_GLBL_MSG_EN_3                                      0x588060
+
+#define mmDMA4_QM_GLBL_MSG_EN_4                                      0x588068
+
+#define mmDMA4_QM_PQ_BASE_LO_0                                       0x588070
+
+#define mmDMA4_QM_PQ_BASE_LO_1                                       0x588074
+
+#define mmDMA4_QM_PQ_BASE_LO_2                                       0x588078
+
+#define mmDMA4_QM_PQ_BASE_LO_3                                       0x58807C
+
+#define mmDMA4_QM_PQ_BASE_HI_0                                       0x588080
+
+#define mmDMA4_QM_PQ_BASE_HI_1                                       0x588084
+
+#define mmDMA4_QM_PQ_BASE_HI_2                                       0x588088
+
+#define mmDMA4_QM_PQ_BASE_HI_3                                       0x58808C
+
+#define mmDMA4_QM_PQ_SIZE_0                                          0x588090
+
+#define mmDMA4_QM_PQ_SIZE_1                                          0x588094
+
+#define mmDMA4_QM_PQ_SIZE_2                                          0x588098
+
+#define mmDMA4_QM_PQ_SIZE_3                                          0x58809C
+
+#define mmDMA4_QM_PQ_PI_0                                            0x5880A0
+
+#define mmDMA4_QM_PQ_PI_1                                            0x5880A4
+
+#define mmDMA4_QM_PQ_PI_2                                            0x5880A8
+
+#define mmDMA4_QM_PQ_PI_3                                            0x5880AC
+
+#define mmDMA4_QM_PQ_CI_0                                            0x5880B0
+
+#define mmDMA4_QM_PQ_CI_1                                            0x5880B4
+
+#define mmDMA4_QM_PQ_CI_2                                            0x5880B8
+
+#define mmDMA4_QM_PQ_CI_3                                            0x5880BC
+
+#define mmDMA4_QM_PQ_CFG0_0                                          0x5880C0
+
+#define mmDMA4_QM_PQ_CFG0_1                                          0x5880C4
+
+#define mmDMA4_QM_PQ_CFG0_2                                          0x5880C8
+
+#define mmDMA4_QM_PQ_CFG0_3                                          0x5880CC
+
+#define mmDMA4_QM_PQ_CFG1_0                                          0x5880D0
+
+#define mmDMA4_QM_PQ_CFG1_1                                          0x5880D4
+
+#define mmDMA4_QM_PQ_CFG1_2                                          0x5880D8
+
+#define mmDMA4_QM_PQ_CFG1_3                                          0x5880DC
+
+#define mmDMA4_QM_PQ_ARUSER_31_11_0                                  0x5880E0
+
+#define mmDMA4_QM_PQ_ARUSER_31_11_1                                  0x5880E4
+
+#define mmDMA4_QM_PQ_ARUSER_31_11_2                                  0x5880E8
+
+#define mmDMA4_QM_PQ_ARUSER_31_11_3                                  0x5880EC
+
+#define mmDMA4_QM_PQ_STS0_0                                          0x5880F0
+
+#define mmDMA4_QM_PQ_STS0_1                                          0x5880F4
+
+#define mmDMA4_QM_PQ_STS0_2                                          0x5880F8
+
+#define mmDMA4_QM_PQ_STS0_3                                          0x5880FC
+
+#define mmDMA4_QM_PQ_STS1_0                                          0x588100
+
+#define mmDMA4_QM_PQ_STS1_1                                          0x588104
+
+#define mmDMA4_QM_PQ_STS1_2                                          0x588108
+
+#define mmDMA4_QM_PQ_STS1_3                                          0x58810C
+
+#define mmDMA4_QM_CQ_CFG0_0                                          0x588110
+
+#define mmDMA4_QM_CQ_CFG0_1                                          0x588114
+
+#define mmDMA4_QM_CQ_CFG0_2                                          0x588118
+
+#define mmDMA4_QM_CQ_CFG0_3                                          0x58811C
+
+#define mmDMA4_QM_CQ_CFG0_4                                          0x588120
+
+#define mmDMA4_QM_CQ_CFG1_0                                          0x588124
+
+#define mmDMA4_QM_CQ_CFG1_1                                          0x588128
+
+#define mmDMA4_QM_CQ_CFG1_2                                          0x58812C
+
+#define mmDMA4_QM_CQ_CFG1_3                                          0x588130
+
+#define mmDMA4_QM_CQ_CFG1_4                                          0x588134
+
+#define mmDMA4_QM_CQ_ARUSER_31_11_0                                  0x588138
+
+#define mmDMA4_QM_CQ_ARUSER_31_11_1                                  0x58813C
+
+#define mmDMA4_QM_CQ_ARUSER_31_11_2                                  0x588140
+
+#define mmDMA4_QM_CQ_ARUSER_31_11_3                                  0x588144
+
+#define mmDMA4_QM_CQ_ARUSER_31_11_4                                  0x588148
+
+#define mmDMA4_QM_CQ_STS0_0                                          0x58814C
+
+#define mmDMA4_QM_CQ_STS0_1                                          0x588150
+
+#define mmDMA4_QM_CQ_STS0_2                                          0x588154
+
+#define mmDMA4_QM_CQ_STS0_3                                          0x588158
+
+#define mmDMA4_QM_CQ_STS0_4                                          0x58815C
+
+#define mmDMA4_QM_CQ_STS1_0                                          0x588160
+
+#define mmDMA4_QM_CQ_STS1_1                                          0x588164
+
+#define mmDMA4_QM_CQ_STS1_2                                          0x588168
+
+#define mmDMA4_QM_CQ_STS1_3                                          0x58816C
+
+#define mmDMA4_QM_CQ_STS1_4                                          0x588170
+
+#define mmDMA4_QM_CQ_PTR_LO_0                                        0x588174
+
+#define mmDMA4_QM_CQ_PTR_HI_0                                        0x588178
+
+#define mmDMA4_QM_CQ_TSIZE_0                                         0x58817C
+
+#define mmDMA4_QM_CQ_CTL_0                                           0x588180
+
+#define mmDMA4_QM_CQ_PTR_LO_1                                        0x588184
+
+#define mmDMA4_QM_CQ_PTR_HI_1                                        0x588188
+
+#define mmDMA4_QM_CQ_TSIZE_1                                         0x58818C
+
+#define mmDMA4_QM_CQ_CTL_1                                           0x588190
+
+#define mmDMA4_QM_CQ_PTR_LO_2                                        0x588194
+
+#define mmDMA4_QM_CQ_PTR_HI_2                                        0x588198
+
+#define mmDMA4_QM_CQ_TSIZE_2                                         0x58819C
+
+#define mmDMA4_QM_CQ_CTL_2                                           0x5881A0
+
+#define mmDMA4_QM_CQ_PTR_LO_3                                        0x5881A4
+
+#define mmDMA4_QM_CQ_PTR_HI_3                                        0x5881A8
+
+#define mmDMA4_QM_CQ_TSIZE_3                                         0x5881AC
+
+#define mmDMA4_QM_CQ_CTL_3                                           0x5881B0
+
+#define mmDMA4_QM_CQ_PTR_LO_4                                        0x5881B4
+
+#define mmDMA4_QM_CQ_PTR_HI_4                                        0x5881B8
+
+#define mmDMA4_QM_CQ_TSIZE_4                                         0x5881BC
+
+#define mmDMA4_QM_CQ_CTL_4                                           0x5881C0
+
+#define mmDMA4_QM_CQ_PTR_LO_STS_0                                    0x5881C4
+
+#define mmDMA4_QM_CQ_PTR_LO_STS_1                                    0x5881C8
+
+#define mmDMA4_QM_CQ_PTR_LO_STS_2                                    0x5881CC
+
+#define mmDMA4_QM_CQ_PTR_LO_STS_3                                    0x5881D0
+
+#define mmDMA4_QM_CQ_PTR_LO_STS_4                                    0x5881D4
+
+#define mmDMA4_QM_CQ_PTR_HI_STS_0                                    0x5881D8
+
+#define mmDMA4_QM_CQ_PTR_HI_STS_1                                    0x5881DC
+
+#define mmDMA4_QM_CQ_PTR_HI_STS_2                                    0x5881E0
+
+#define mmDMA4_QM_CQ_PTR_HI_STS_3                                    0x5881E4
+
+#define mmDMA4_QM_CQ_PTR_HI_STS_4                                    0x5881E8
+
+#define mmDMA4_QM_CQ_TSIZE_STS_0                                     0x5881EC
+
+#define mmDMA4_QM_CQ_TSIZE_STS_1                                     0x5881F0
+
+#define mmDMA4_QM_CQ_TSIZE_STS_2                                     0x5881F4
+
+#define mmDMA4_QM_CQ_TSIZE_STS_3                                     0x5881F8
+
+#define mmDMA4_QM_CQ_TSIZE_STS_4                                     0x5881FC
+
+#define mmDMA4_QM_CQ_CTL_STS_0                                       0x588200
+
+#define mmDMA4_QM_CQ_CTL_STS_1                                       0x588204
+
+#define mmDMA4_QM_CQ_CTL_STS_2                                       0x588208
+
+#define mmDMA4_QM_CQ_CTL_STS_3                                       0x58820C
+
+#define mmDMA4_QM_CQ_CTL_STS_4                                       0x588210
+
+#define mmDMA4_QM_CQ_IFIFO_CNT_0                                     0x588214
+
+#define mmDMA4_QM_CQ_IFIFO_CNT_1                                     0x588218
+
+#define mmDMA4_QM_CQ_IFIFO_CNT_2                                     0x58821C
+
+#define mmDMA4_QM_CQ_IFIFO_CNT_3                                     0x588220
+
+#define mmDMA4_QM_CQ_IFIFO_CNT_4                                     0x588224
+
+#define mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_0                             0x588228
+
+#define mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_1                             0x58822C
+
+#define mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_2                             0x588230
+
+#define mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_3                             0x588234
+
+#define mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_4                             0x588238
+
+#define mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_0                             0x58823C
+
+#define mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_1                             0x588240
+
+#define mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_2                             0x588244
+
+#define mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_3                             0x588248
+
+#define mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_4                             0x58824C
+
+#define mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_0                             0x588250
+
+#define mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_1                             0x588254
+
+#define mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_2                             0x588258
+
+#define mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_3                             0x58825C
+
+#define mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_4                             0x588260
+
+#define mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_0                             0x588264
+
+#define mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_1                             0x588268
+
+#define mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_2                             0x58826C
+
+#define mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_3                             0x588270
+
+#define mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_4                             0x588274
+
+#define mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_0                             0x588278
+
+#define mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_1                             0x58827C
+
+#define mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_2                             0x588280
+
+#define mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_3                             0x588284
+
+#define mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_4                             0x588288
+
+#define mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_0                             0x58828C
+
+#define mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_1                             0x588290
+
+#define mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_2                             0x588294
+
+#define mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_3                             0x588298
+
+#define mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_4                             0x58829C
+
+#define mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_0                             0x5882A0
+
+#define mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_1                             0x5882A4
+
+#define mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_2                             0x5882A8
+
+#define mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_3                             0x5882AC
+
+#define mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_4                             0x5882B0
+
+#define mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_0                             0x5882B4
+
+#define mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_1                             0x5882B8
+
+#define mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_2                             0x5882BC
+
+#define mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_3                             0x5882C0
+
+#define mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_4                             0x5882C4
+
+#define mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_0                             0x5882C8
+
+#define mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_1                             0x5882CC
+
+#define mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_2                             0x5882D0
+
+#define mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_3                             0x5882D4
+
+#define mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_4                             0x5882D8
+
+#define mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0                       0x5882E0
+
+#define mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1                       0x5882E4
+
+#define mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2                       0x5882E8
+
+#define mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3                       0x5882EC
+
+#define mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4                       0x5882F0
+
+#define mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_0                       0x5882F4
+
+#define mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_1                       0x5882F8
+
+#define mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_2                       0x5882FC
+
+#define mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3                       0x588300
+
+#define mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_4                       0x588304
+
+#define mmDMA4_QM_CP_FENCE0_RDATA_0                                  0x588308
+
+#define mmDMA4_QM_CP_FENCE0_RDATA_1                                  0x58830C
+
+#define mmDMA4_QM_CP_FENCE0_RDATA_2                                  0x588310
+
+#define mmDMA4_QM_CP_FENCE0_RDATA_3                                  0x588314
+
+#define mmDMA4_QM_CP_FENCE0_RDATA_4                                  0x588318
+
+#define mmDMA4_QM_CP_FENCE1_RDATA_0                                  0x58831C
+
+#define mmDMA4_QM_CP_FENCE1_RDATA_1                                  0x588320
+
+#define mmDMA4_QM_CP_FENCE1_RDATA_2                                  0x588324
+
+#define mmDMA4_QM_CP_FENCE1_RDATA_3                                  0x588328
+
+#define mmDMA4_QM_CP_FENCE1_RDATA_4                                  0x58832C
+
+#define mmDMA4_QM_CP_FENCE2_RDATA_0                                  0x588330
+
+#define mmDMA4_QM_CP_FENCE2_RDATA_1                                  0x588334
+
+#define mmDMA4_QM_CP_FENCE2_RDATA_2                                  0x588338
+
+#define mmDMA4_QM_CP_FENCE2_RDATA_3                                  0x58833C
+
+#define mmDMA4_QM_CP_FENCE2_RDATA_4                                  0x588340
+
+#define mmDMA4_QM_CP_FENCE3_RDATA_0                                  0x588344
+
+#define mmDMA4_QM_CP_FENCE3_RDATA_1                                  0x588348
+
+#define mmDMA4_QM_CP_FENCE3_RDATA_2                                  0x58834C
+
+#define mmDMA4_QM_CP_FENCE3_RDATA_3                                  0x588350
+
+#define mmDMA4_QM_CP_FENCE3_RDATA_4                                  0x588354
+
+#define mmDMA4_QM_CP_FENCE0_CNT_0                                    0x588358
+
+#define mmDMA4_QM_CP_FENCE0_CNT_1                                    0x58835C
+
+#define mmDMA4_QM_CP_FENCE0_CNT_2                                    0x588360
+
+#define mmDMA4_QM_CP_FENCE0_CNT_3                                    0x588364
+
+#define mmDMA4_QM_CP_FENCE0_CNT_4                                    0x588368
+
+#define mmDMA4_QM_CP_FENCE1_CNT_0                                    0x58836C
+
+#define mmDMA4_QM_CP_FENCE1_CNT_1                                    0x588370
+
+#define mmDMA4_QM_CP_FENCE1_CNT_2                                    0x588374
+
+#define mmDMA4_QM_CP_FENCE1_CNT_3                                    0x588378
+
+#define mmDMA4_QM_CP_FENCE1_CNT_4                                    0x58837C
+
+#define mmDMA4_QM_CP_FENCE2_CNT_0                                    0x588380
+
+#define mmDMA4_QM_CP_FENCE2_CNT_1                                    0x588384
+
+#define mmDMA4_QM_CP_FENCE2_CNT_2                                    0x588388
+
+#define mmDMA4_QM_CP_FENCE2_CNT_3                                    0x58838C
+
+#define mmDMA4_QM_CP_FENCE2_CNT_4                                    0x588390
+
+#define mmDMA4_QM_CP_FENCE3_CNT_0                                    0x588394
+
+#define mmDMA4_QM_CP_FENCE3_CNT_1                                    0x588398
+
+#define mmDMA4_QM_CP_FENCE3_CNT_2                                    0x58839C
+
+#define mmDMA4_QM_CP_FENCE3_CNT_3                                    0x5883A0
+
+#define mmDMA4_QM_CP_FENCE3_CNT_4                                    0x5883A4
+
+#define mmDMA4_QM_CP_STS_0                                           0x5883A8
+
+#define mmDMA4_QM_CP_STS_1                                           0x5883AC
+
+#define mmDMA4_QM_CP_STS_2                                           0x5883B0
+
+#define mmDMA4_QM_CP_STS_3                                           0x5883B4
+
+#define mmDMA4_QM_CP_STS_4                                           0x5883B8
+
+#define mmDMA4_QM_CP_CURRENT_INST_LO_0                               0x5883BC
+
+#define mmDMA4_QM_CP_CURRENT_INST_LO_1                               0x5883C0
+
+#define mmDMA4_QM_CP_CURRENT_INST_LO_2                               0x5883C4
+
+#define mmDMA4_QM_CP_CURRENT_INST_LO_3                               0x5883C8
+
+#define mmDMA4_QM_CP_CURRENT_INST_LO_4                               0x5883CC
+
+#define mmDMA4_QM_CP_CURRENT_INST_HI_0                               0x5883D0
+
+#define mmDMA4_QM_CP_CURRENT_INST_HI_1                               0x5883D4
+
+#define mmDMA4_QM_CP_CURRENT_INST_HI_2                               0x5883D8
+
+#define mmDMA4_QM_CP_CURRENT_INST_HI_3                               0x5883DC
+
+#define mmDMA4_QM_CP_CURRENT_INST_HI_4                               0x5883E0
+
+#define mmDMA4_QM_CP_BARRIER_CFG_0                                   0x5883F4
+
+#define mmDMA4_QM_CP_BARRIER_CFG_1                                   0x5883F8
+
+#define mmDMA4_QM_CP_BARRIER_CFG_2                                   0x5883FC
+
+#define mmDMA4_QM_CP_BARRIER_CFG_3                                   0x588400
+
+#define mmDMA4_QM_CP_BARRIER_CFG_4                                   0x588404
+
+#define mmDMA4_QM_CP_DBG_0_0                                         0x588408
+
+#define mmDMA4_QM_CP_DBG_0_1                                         0x58840C
+
+#define mmDMA4_QM_CP_DBG_0_2                                         0x588410
+
+#define mmDMA4_QM_CP_DBG_0_3                                         0x588414
+
+#define mmDMA4_QM_CP_DBG_0_4                                         0x588418
+
+#define mmDMA4_QM_CP_ARUSER_31_11_0                                  0x58841C
+
+#define mmDMA4_QM_CP_ARUSER_31_11_1                                  0x588420
+
+#define mmDMA4_QM_CP_ARUSER_31_11_2                                  0x588424
+
+#define mmDMA4_QM_CP_ARUSER_31_11_3                                  0x588428
+
+#define mmDMA4_QM_CP_ARUSER_31_11_4                                  0x58842C
+
+#define mmDMA4_QM_CP_AWUSER_31_11_0                                  0x588430
+
+#define mmDMA4_QM_CP_AWUSER_31_11_1                                  0x588434
+
+#define mmDMA4_QM_CP_AWUSER_31_11_2                                  0x588438
+
+#define mmDMA4_QM_CP_AWUSER_31_11_3                                  0x58843C
+
+#define mmDMA4_QM_CP_AWUSER_31_11_4                                  0x588440
+
+#define mmDMA4_QM_ARB_CFG_0                                          0x588A00
+
+#define mmDMA4_QM_ARB_CHOISE_Q_PUSH                                  0x588A04
+
+#define mmDMA4_QM_ARB_WRR_WEIGHT_0                                   0x588A08
+
+#define mmDMA4_QM_ARB_WRR_WEIGHT_1                                   0x588A0C
+
+#define mmDMA4_QM_ARB_WRR_WEIGHT_2                                   0x588A10
+
+#define mmDMA4_QM_ARB_WRR_WEIGHT_3                                   0x588A14
+
+#define mmDMA4_QM_ARB_CFG_1                                          0x588A18
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_0                               0x588A20
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_1                               0x588A24
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_2                               0x588A28
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_3                               0x588A2C
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_4                               0x588A30
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_5                               0x588A34
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_6                               0x588A38
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_7                               0x588A3C
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_8                               0x588A40
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_9                               0x588A44
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_10                              0x588A48
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_11                              0x588A4C
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_12                              0x588A50
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_13                              0x588A54
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_14                              0x588A58
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_15                              0x588A5C
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_16                              0x588A60
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_17                              0x588A64
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_18                              0x588A68
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_19                              0x588A6C
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_20                              0x588A70
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_21                              0x588A74
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_22                              0x588A78
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_23                              0x588A7C
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_24                              0x588A80
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_25                              0x588A84
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_26                              0x588A88
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_27                              0x588A8C
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_28                              0x588A90
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_29                              0x588A94
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_30                              0x588A98
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_31                              0x588A9C
+
+#define mmDMA4_QM_ARB_MST_CRED_INC                                   0x588AA0
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_0                         0x588AA4
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_1                         0x588AA8
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_2                         0x588AAC
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_3                         0x588AB0
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_4                         0x588AB4
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_5                         0x588AB8
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_6                         0x588ABC
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_7                         0x588AC0
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_8                         0x588AC4
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_9                         0x588AC8
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_10                        0x588ACC
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_11                        0x588AD0
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_12                        0x588AD4
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_13                        0x588AD8
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_14                        0x588ADC
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_15                        0x588AE0
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_16                        0x588AE4
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_17                        0x588AE8
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_18                        0x588AEC
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_19                        0x588AF0
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_20                        0x588AF4
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_21                        0x588AF8
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_22                        0x588AFC
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_23                        0x588B00
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_24                        0x588B04
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_25                        0x588B08
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_26                        0x588B0C
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_27                        0x588B10
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_28                        0x588B14
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_29                        0x588B18
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_30                        0x588B1C
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_31                        0x588B20
+
+#define mmDMA4_QM_ARB_SLV_MASTER_INC_CRED_OFST                       0x588B28
+
+#define mmDMA4_QM_ARB_MST_SLAVE_EN                                   0x588B2C
+
+#define mmDMA4_QM_ARB_MST_QUIET_PER                                  0x588B34
+
+#define mmDMA4_QM_ARB_SLV_CHOISE_WDT                                 0x588B38
+
+#define mmDMA4_QM_ARB_SLV_ID                                         0x588B3C
+
+#define mmDMA4_QM_ARB_MSG_MAX_INFLIGHT                               0x588B44
+
+#define mmDMA4_QM_ARB_MSG_AWUSER_31_11                               0x588B48
+
+#define mmDMA4_QM_ARB_MSG_AWUSER_SEC_PROP                            0x588B4C
+
+#define mmDMA4_QM_ARB_MSG_AWUSER_NON_SEC_PROP                        0x588B50
+
+#define mmDMA4_QM_ARB_BASE_LO                                        0x588B54
+
+#define mmDMA4_QM_ARB_BASE_HI                                        0x588B58
+
+#define mmDMA4_QM_ARB_STATE_STS                                      0x588B80
+
+#define mmDMA4_QM_ARB_CHOISE_FULLNESS_STS                            0x588B84
+
+#define mmDMA4_QM_ARB_MSG_STS                                        0x588B88
+
+#define mmDMA4_QM_ARB_SLV_CHOISE_Q_HEAD                              0x588B8C
+
+#define mmDMA4_QM_ARB_ERR_CAUSE                                      0x588B9C
+
+#define mmDMA4_QM_ARB_ERR_MSG_EN                                     0x588BA0
+
+#define mmDMA4_QM_ARB_ERR_STS_DRP                                    0x588BA8
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_0                                 0x588BB0
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_1                                 0x588BB4
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_2                                 0x588BB8
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_3                                 0x588BBC
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_4                                 0x588BC0
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_5                                 0x588BC4
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_6                                 0x588BC8
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_7                                 0x588BCC
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_8                                 0x588BD0
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_9                                 0x588BD4
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_10                                0x588BD8
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_11                                0x588BDC
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_12                                0x588BE0
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_13                                0x588BE4
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_14                                0x588BE8
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_15                                0x588BEC
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_16                                0x588BF0
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_17                                0x588BF4
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_18                                0x588BF8
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_19                                0x588BFC
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_20                                0x588C00
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_21                                0x588C04
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_22                                0x588C08
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_23                                0x588C0C
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_24                                0x588C10
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_25                                0x588C14
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_26                                0x588C18
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_27                                0x588C1C
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_28                                0x588C20
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_29                                0x588C24
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_30                                0x588C28
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_31                                0x588C2C
+
+#define mmDMA4_QM_CGM_CFG                                            0x588C70
+
+#define mmDMA4_QM_CGM_STS                                            0x588C74
+
+#define mmDMA4_QM_CGM_CFG1                                           0x588C78
+
+#define mmDMA4_QM_LOCAL_RANGE_BASE                                   0x588C80
+
+#define mmDMA4_QM_LOCAL_RANGE_SIZE                                   0x588C84
+
+#define mmDMA4_QM_CSMR_STRICT_PRIO_CFG                               0x588C90
+
+#define mmDMA4_QM_HBW_RD_RATE_LIM_CFG_1                              0x588C94
+
+#define mmDMA4_QM_LBW_WR_RATE_LIM_CFG_0                              0x588C98
+
+#define mmDMA4_QM_LBW_WR_RATE_LIM_CFG_1                              0x588C9C
+
+#define mmDMA4_QM_HBW_RD_RATE_LIM_CFG_0                              0x588CA0
+
+#define mmDMA4_QM_GLBL_AXCACHE                                       0x588CA4
+
+#define mmDMA4_QM_IND_GW_APB_CFG                                     0x588CB0
+
+#define mmDMA4_QM_IND_GW_APB_WDATA                                   0x588CB4
+
+#define mmDMA4_QM_IND_GW_APB_RDATA                                   0x588CB8
+
+#define mmDMA4_QM_IND_GW_APB_STATUS                                  0x588CBC
+
+#define mmDMA4_QM_GLBL_ERR_ADDR_LO                                   0x588CD0
+
+#define mmDMA4_QM_GLBL_ERR_ADDR_HI                                   0x588CD4
+
+#define mmDMA4_QM_GLBL_ERR_WDATA                                     0x588CD8
+
+#define mmDMA4_QM_GLBL_MEM_INIT_BUSY                                 0x588D00
+
+#endif /* ASIC_REG_DMA4_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma5_core_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma5_core_regs.h
new file mode 100644
index 000000000000..6e07c6fb6fc9
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma5_core_regs.h
@@ -0,0 +1,156 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DMA5_CORE_REGS_H_
+#define ASIC_REG_DMA5_CORE_REGS_H_
+
+/*
+ *****************************************
+ *   DMA5_CORE (Prototype: DMA_CORE)
+ *****************************************
+ */
+
+#define mmDMA5_CORE_CFG_0                                            0x5A0000
+
+#define mmDMA5_CORE_CFG_1                                            0x5A0004
+
+#define mmDMA5_CORE_LBW_MAX_OUTSTAND                                 0x5A0008
+
+#define mmDMA5_CORE_SRC_BASE_LO                                      0x5A0014
+
+#define mmDMA5_CORE_SRC_BASE_HI                                      0x5A0018
+
+#define mmDMA5_CORE_DST_BASE_LO                                      0x5A001C
+
+#define mmDMA5_CORE_DST_BASE_HI                                      0x5A0020
+
+#define mmDMA5_CORE_SRC_TSIZE_1                                      0x5A002C
+
+#define mmDMA5_CORE_SRC_STRIDE_1                                     0x5A0030
+
+#define mmDMA5_CORE_SRC_TSIZE_2                                      0x5A0034
+
+#define mmDMA5_CORE_SRC_STRIDE_2                                     0x5A0038
+
+#define mmDMA5_CORE_SRC_TSIZE_3                                      0x5A003C
+
+#define mmDMA5_CORE_SRC_STRIDE_3                                     0x5A0040
+
+#define mmDMA5_CORE_SRC_TSIZE_4                                      0x5A0044
+
+#define mmDMA5_CORE_SRC_STRIDE_4                                     0x5A0048
+
+#define mmDMA5_CORE_SRC_TSIZE_0                                      0x5A004C
+
+#define mmDMA5_CORE_DST_TSIZE_1                                      0x5A0054
+
+#define mmDMA5_CORE_DST_STRIDE_1                                     0x5A0058
+
+#define mmDMA5_CORE_DST_TSIZE_2                                      0x5A005C
+
+#define mmDMA5_CORE_DST_STRIDE_2                                     0x5A0060
+
+#define mmDMA5_CORE_DST_TSIZE_3                                      0x5A0064
+
+#define mmDMA5_CORE_DST_STRIDE_3                                     0x5A0068
+
+#define mmDMA5_CORE_DST_TSIZE_4                                      0x5A006C
+
+#define mmDMA5_CORE_DST_STRIDE_4                                     0x5A0070
+
+#define mmDMA5_CORE_DST_TSIZE_0                                      0x5A0074
+
+#define mmDMA5_CORE_COMMIT                                           0x5A0078
+
+#define mmDMA5_CORE_WR_COMP_WDATA                                    0x5A007C
+
+#define mmDMA5_CORE_WR_COMP_ADDR_LO                                  0x5A0080
+
+#define mmDMA5_CORE_WR_COMP_ADDR_HI                                  0x5A0084
+
+#define mmDMA5_CORE_WR_COMP_AWUSER_31_11                             0x5A0088
+
+#define mmDMA5_CORE_TE_NUMROWS                                       0x5A0094
+
+#define mmDMA5_CORE_PROT                                             0x5A00B8
+
+#define mmDMA5_CORE_SECURE_PROPS                                     0x5A00F0
+
+#define mmDMA5_CORE_NON_SECURE_PROPS                                 0x5A00F4
+
+#define mmDMA5_CORE_RD_MAX_OUTSTAND                                  0x5A0100
+
+#define mmDMA5_CORE_RD_MAX_SIZE                                      0x5A0104
+
+#define mmDMA5_CORE_RD_ARCACHE                                       0x5A0108
+
+#define mmDMA5_CORE_RD_ARUSER_31_11                                  0x5A0110
+
+#define mmDMA5_CORE_RD_INFLIGHTS                                     0x5A0114
+
+#define mmDMA5_CORE_WR_MAX_OUTSTAND                                  0x5A0120
+
+#define mmDMA5_CORE_WR_MAX_AWID                                      0x5A0124
+
+#define mmDMA5_CORE_WR_AWCACHE                                       0x5A0128
+
+#define mmDMA5_CORE_WR_AWUSER_31_11                                  0x5A0130
+
+#define mmDMA5_CORE_WR_INFLIGHTS                                     0x5A0134
+
+#define mmDMA5_CORE_RD_RATE_LIM_CFG_0                                0x5A0150
+
+#define mmDMA5_CORE_RD_RATE_LIM_CFG_1                                0x5A0154
+
+#define mmDMA5_CORE_WR_RATE_LIM_CFG_0                                0x5A0158
+
+#define mmDMA5_CORE_WR_RATE_LIM_CFG_1                                0x5A015C
+
+#define mmDMA5_CORE_ERR_CFG                                          0x5A0160
+
+#define mmDMA5_CORE_ERR_CAUSE                                        0x5A0164
+
+#define mmDMA5_CORE_ERRMSG_ADDR_LO                                   0x5A0170
+
+#define mmDMA5_CORE_ERRMSG_ADDR_HI                                   0x5A0174
+
+#define mmDMA5_CORE_ERRMSG_WDATA                                     0x5A0178
+
+#define mmDMA5_CORE_STS0                                             0x5A0190
+
+#define mmDMA5_CORE_STS1                                             0x5A0194
+
+#define mmDMA5_CORE_RD_DBGMEM_ADD                                    0x5A0200
+
+#define mmDMA5_CORE_RD_DBGMEM_DATA_WR                                0x5A0204
+
+#define mmDMA5_CORE_RD_DBGMEM_DATA_RD                                0x5A0208
+
+#define mmDMA5_CORE_RD_DBGMEM_CTRL                                   0x5A020C
+
+#define mmDMA5_CORE_RD_DBGMEM_RC                                     0x5A0210
+
+#define mmDMA5_CORE_DBG_HBW_AXI_AR_CNT                               0x5A0220
+
+#define mmDMA5_CORE_DBG_HBW_AXI_AW_CNT                               0x5A0224
+
+#define mmDMA5_CORE_DBG_LBW_AXI_AW_CNT                               0x5A0228
+
+#define mmDMA5_CORE_DBG_DESC_CNT                                     0x5A022C
+
+#define mmDMA5_CORE_DBG_STS                                          0x5A0230
+
+#define mmDMA5_CORE_DBG_RD_DESC_ID                                   0x5A0234
+
+#define mmDMA5_CORE_DBG_WR_DESC_ID                                   0x5A0238
+
+#endif /* ASIC_REG_DMA5_CORE_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma5_qm_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma5_qm_regs.h
new file mode 100644
index 000000000000..0faea21756c5
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma5_qm_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DMA5_QM_REGS_H_
+#define ASIC_REG_DMA5_QM_REGS_H_
+
+/*
+ *****************************************
+ *   DMA5_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmDMA5_QM_GLBL_CFG0                                          0x5A8000
+
+#define mmDMA5_QM_GLBL_CFG1                                          0x5A8004
+
+#define mmDMA5_QM_GLBL_PROT                                          0x5A8008
+
+#define mmDMA5_QM_GLBL_ERR_CFG                                       0x5A800C
+
+#define mmDMA5_QM_GLBL_SECURE_PROPS_0                                0x5A8010
+
+#define mmDMA5_QM_GLBL_SECURE_PROPS_1                                0x5A8014
+
+#define mmDMA5_QM_GLBL_SECURE_PROPS_2                                0x5A8018
+
+#define mmDMA5_QM_GLBL_SECURE_PROPS_3                                0x5A801C
+
+#define mmDMA5_QM_GLBL_SECURE_PROPS_4                                0x5A8020
+
+#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_0                            0x5A8024
+
+#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_1                            0x5A8028
+
+#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_2                            0x5A802C
+
+#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_3                            0x5A8030
+
+#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_4                            0x5A8034
+
+#define mmDMA5_QM_GLBL_STS0                                          0x5A8038
+
+#define mmDMA5_QM_GLBL_STS1_0                                        0x5A8040
+
+#define mmDMA5_QM_GLBL_STS1_1                                        0x5A8044
+
+#define mmDMA5_QM_GLBL_STS1_2                                        0x5A8048
+
+#define mmDMA5_QM_GLBL_STS1_3                                        0x5A804C
+
+#define mmDMA5_QM_GLBL_STS1_4                                        0x5A8050
+
+#define mmDMA5_QM_GLBL_MSG_EN_0                                      0x5A8054
+
+#define mmDMA5_QM_GLBL_MSG_EN_1                                      0x5A8058
+
+#define mmDMA5_QM_GLBL_MSG_EN_2                                      0x5A805C
+
+#define mmDMA5_QM_GLBL_MSG_EN_3                                      0x5A8060
+
+#define mmDMA5_QM_GLBL_MSG_EN_4                                      0x5A8068
+
+#define mmDMA5_QM_PQ_BASE_LO_0                                       0x5A8070
+
+#define mmDMA5_QM_PQ_BASE_LO_1                                       0x5A8074
+
+#define mmDMA5_QM_PQ_BASE_LO_2                                       0x5A8078
+
+#define mmDMA5_QM_PQ_BASE_LO_3                                       0x5A807C
+
+#define mmDMA5_QM_PQ_BASE_HI_0                                       0x5A8080
+
+#define mmDMA5_QM_PQ_BASE_HI_1                                       0x5A8084
+
+#define mmDMA5_QM_PQ_BASE_HI_2                                       0x5A8088
+
+#define mmDMA5_QM_PQ_BASE_HI_3                                       0x5A808C
+
+#define mmDMA5_QM_PQ_SIZE_0                                          0x5A8090
+
+#define mmDMA5_QM_PQ_SIZE_1                                          0x5A8094
+
+#define mmDMA5_QM_PQ_SIZE_2                                          0x5A8098
+
+#define mmDMA5_QM_PQ_SIZE_3                                          0x5A809C
+
+#define mmDMA5_QM_PQ_PI_0                                            0x5A80A0
+
+#define mmDMA5_QM_PQ_PI_1                                            0x5A80A4
+
+#define mmDMA5_QM_PQ_PI_2                                            0x5A80A8
+
+#define mmDMA5_QM_PQ_PI_3                                            0x5A80AC
+
+#define mmDMA5_QM_PQ_CI_0                                            0x5A80B0
+
+#define mmDMA5_QM_PQ_CI_1                                            0x5A80B4
+
+#define mmDMA5_QM_PQ_CI_2                                            0x5A80B8
+
+#define mmDMA5_QM_PQ_CI_3                                            0x5A80BC
+
+#define mmDMA5_QM_PQ_CFG0_0                                          0x5A80C0
+
+#define mmDMA5_QM_PQ_CFG0_1                                          0x5A80C4
+
+#define mmDMA5_QM_PQ_CFG0_2                                          0x5A80C8
+
+#define mmDMA5_QM_PQ_CFG0_3                                          0x5A80CC
+
+#define mmDMA5_QM_PQ_CFG1_0                                          0x5A80D0
+
+#define mmDMA5_QM_PQ_CFG1_1                                          0x5A80D4
+
+#define mmDMA5_QM_PQ_CFG1_2                                          0x5A80D8
+
+#define mmDMA5_QM_PQ_CFG1_3                                          0x5A80DC
+
+#define mmDMA5_QM_PQ_ARUSER_31_11_0                                  0x5A80E0
+
+#define mmDMA5_QM_PQ_ARUSER_31_11_1                                  0x5A80E4
+
+#define mmDMA5_QM_PQ_ARUSER_31_11_2                                  0x5A80E8
+
+#define mmDMA5_QM_PQ_ARUSER_31_11_3                                  0x5A80EC
+
+#define mmDMA5_QM_PQ_STS0_0                                          0x5A80F0
+
+#define mmDMA5_QM_PQ_STS0_1                                          0x5A80F4
+
+#define mmDMA5_QM_PQ_STS0_2                                          0x5A80F8
+
+#define mmDMA5_QM_PQ_STS0_3                                          0x5A80FC
+
+#define mmDMA5_QM_PQ_STS1_0                                          0x5A8100
+
+#define mmDMA5_QM_PQ_STS1_1                                          0x5A8104
+
+#define mmDMA5_QM_PQ_STS1_2                                          0x5A8108
+
+#define mmDMA5_QM_PQ_STS1_3                                          0x5A810C
+
+#define mmDMA5_QM_CQ_CFG0_0                                          0x5A8110
+
+#define mmDMA5_QM_CQ_CFG0_1                                          0x5A8114
+
+#define mmDMA5_QM_CQ_CFG0_2                                          0x5A8118
+
+#define mmDMA5_QM_CQ_CFG0_3                                          0x5A811C
+
+#define mmDMA5_QM_CQ_CFG0_4                                          0x5A8120
+
+#define mmDMA5_QM_CQ_CFG1_0                                          0x5A8124
+
+#define mmDMA5_QM_CQ_CFG1_1                                          0x5A8128
+
+#define mmDMA5_QM_CQ_CFG1_2                                          0x5A812C
+
+#define mmDMA5_QM_CQ_CFG1_3                                          0x5A8130
+
+#define mmDMA5_QM_CQ_CFG1_4                                          0x5A8134
+
+#define mmDMA5_QM_CQ_ARUSER_31_11_0                                  0x5A8138
+
+#define mmDMA5_QM_CQ_ARUSER_31_11_1                                  0x5A813C
+
+#define mmDMA5_QM_CQ_ARUSER_31_11_2                                  0x5A8140
+
+#define mmDMA5_QM_CQ_ARUSER_31_11_3                                  0x5A8144
+
+#define mmDMA5_QM_CQ_ARUSER_31_11_4                                  0x5A8148
+
+#define mmDMA5_QM_CQ_STS0_0                                          0x5A814C
+
+#define mmDMA5_QM_CQ_STS0_1                                          0x5A8150
+
+#define mmDMA5_QM_CQ_STS0_2                                          0x5A8154
+
+#define mmDMA5_QM_CQ_STS0_3                                          0x5A8158
+
+#define mmDMA5_QM_CQ_STS0_4                                          0x5A815C
+
+#define mmDMA5_QM_CQ_STS1_0                                          0x5A8160
+
+#define mmDMA5_QM_CQ_STS1_1                                          0x5A8164
+
+#define mmDMA5_QM_CQ_STS1_2                                          0x5A8168
+
+#define mmDMA5_QM_CQ_STS1_3                                          0x5A816C
+
+#define mmDMA5_QM_CQ_STS1_4                                          0x5A8170
+
+#define mmDMA5_QM_CQ_PTR_LO_0                                        0x5A8174
+
+#define mmDMA5_QM_CQ_PTR_HI_0                                        0x5A8178
+
+#define mmDMA5_QM_CQ_TSIZE_0                                         0x5A817C
+
+#define mmDMA5_QM_CQ_CTL_0                                           0x5A8180
+
+#define mmDMA5_QM_CQ_PTR_LO_1                                        0x5A8184
+
+#define mmDMA5_QM_CQ_PTR_HI_1                                        0x5A8188
+
+#define mmDMA5_QM_CQ_TSIZE_1                                         0x5A818C
+
+#define mmDMA5_QM_CQ_CTL_1                                           0x5A8190
+
+#define mmDMA5_QM_CQ_PTR_LO_2                                        0x5A8194
+
+#define mmDMA5_QM_CQ_PTR_HI_2                                        0x5A8198
+
+#define mmDMA5_QM_CQ_TSIZE_2                                         0x5A819C
+
+#define mmDMA5_QM_CQ_CTL_2                                           0x5A81A0
+
+#define mmDMA5_QM_CQ_PTR_LO_3                                        0x5A81A4
+
+#define mmDMA5_QM_CQ_PTR_HI_3                                        0x5A81A8
+
+#define mmDMA5_QM_CQ_TSIZE_3                                         0x5A81AC
+
+#define mmDMA5_QM_CQ_CTL_3                                           0x5A81B0
+
+#define mmDMA5_QM_CQ_PTR_LO_4                                        0x5A81B4
+
+#define mmDMA5_QM_CQ_PTR_HI_4                                        0x5A81B8
+
+#define mmDMA5_QM_CQ_TSIZE_4                                         0x5A81BC
+
+#define mmDMA5_QM_CQ_CTL_4                                           0x5A81C0
+
+#define mmDMA5_QM_CQ_PTR_LO_STS_0                                    0x5A81C4
+
+#define mmDMA5_QM_CQ_PTR_LO_STS_1                                    0x5A81C8
+
+#define mmDMA5_QM_CQ_PTR_LO_STS_2                                    0x5A81CC
+
+#define mmDMA5_QM_CQ_PTR_LO_STS_3                                    0x5A81D0
+
+#define mmDMA5_QM_CQ_PTR_LO_STS_4                                    0x5A81D4
+
+#define mmDMA5_QM_CQ_PTR_HI_STS_0                                    0x5A81D8
+
+#define mmDMA5_QM_CQ_PTR_HI_STS_1                                    0x5A81DC
+
+#define mmDMA5_QM_CQ_PTR_HI_STS_2                                    0x5A81E0
+
+#define mmDMA5_QM_CQ_PTR_HI_STS_3                                    0x5A81E4
+
+#define mmDMA5_QM_CQ_PTR_HI_STS_4                                    0x5A81E8
+
+#define mmDMA5_QM_CQ_TSIZE_STS_0                                     0x5A81EC
+
+#define mmDMA5_QM_CQ_TSIZE_STS_1                                     0x5A81F0
+
+#define mmDMA5_QM_CQ_TSIZE_STS_2                                     0x5A81F4
+
+#define mmDMA5_QM_CQ_TSIZE_STS_3                                     0x5A81F8
+
+#define mmDMA5_QM_CQ_TSIZE_STS_4                                     0x5A81FC
+
+#define mmDMA5_QM_CQ_CTL_STS_0                                       0x5A8200
+
+#define mmDMA5_QM_CQ_CTL_STS_1                                       0x5A8204
+
+#define mmDMA5_QM_CQ_CTL_STS_2                                       0x5A8208
+
+#define mmDMA5_QM_CQ_CTL_STS_3                                       0x5A820C
+
+#define mmDMA5_QM_CQ_CTL_STS_4                                       0x5A8210
+
+#define mmDMA5_QM_CQ_IFIFO_CNT_0                                     0x5A8214
+
+#define mmDMA5_QM_CQ_IFIFO_CNT_1                                     0x5A8218
+
+#define mmDMA5_QM_CQ_IFIFO_CNT_2                                     0x5A821C
+
+#define mmDMA5_QM_CQ_IFIFO_CNT_3                                     0x5A8220
+
+#define mmDMA5_QM_CQ_IFIFO_CNT_4                                     0x5A8224
+
+#define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_0                             0x5A8228
+
+#define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_1                             0x5A822C
+
+#define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_2                             0x5A8230
+
+#define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_3                             0x5A8234
+
+#define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_4                             0x5A8238
+
+#define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_0                             0x5A823C
+
+#define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_1                             0x5A8240
+
+#define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_2                             0x5A8244
+
+#define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_3                             0x5A8248
+
+#define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_4                             0x5A824C
+
+#define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_0                             0x5A8250
+
+#define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_1                             0x5A8254
+
+#define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_2                             0x5A8258
+
+#define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_3                             0x5A825C
+
+#define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_4                             0x5A8260
+
+#define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_0                             0x5A8264
+
+#define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_1                             0x5A8268
+
+#define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_2                             0x5A826C
+
+#define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_3                             0x5A8270
+
+#define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_4                             0x5A8274
+
+#define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_0                             0x5A8278
+
+#define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_1                             0x5A827C
+
+#define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_2                             0x5A8280
+
+#define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_3                             0x5A8284
+
+#define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_4                             0x5A8288
+
+#define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_0                             0x5A828C
+
+#define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_1                             0x5A8290
+
+#define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_2                             0x5A8294
+
+#define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_3                             0x5A8298
+
+#define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_4                             0x5A829C
+
+#define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_0                             0x5A82A0
+
+#define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_1                             0x5A82A4
+
+#define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_2                             0x5A82A8
+
+#define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_3                             0x5A82AC
+
+#define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_4                             0x5A82B0
+
+#define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_0                             0x5A82B4
+
+#define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_1                             0x5A82B8
+
+#define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_2                             0x5A82BC
+
+#define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_3                             0x5A82C0
+
+#define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_4                             0x5A82C4
+
+#define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_0                             0x5A82C8
+
+#define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_1                             0x5A82CC
+
+#define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_2                             0x5A82D0
+
+#define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_3                             0x5A82D4
+
+#define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_4                             0x5A82D8
+
+#define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0                       0x5A82E0
+
+#define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1                       0x5A82E4
+
+#define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2                       0x5A82E8
+
+#define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3                       0x5A82EC
+
+#define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4                       0x5A82F0
+
+#define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_0                       0x5A82F4
+
+#define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_1                       0x5A82F8
+
+#define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_2                       0x5A82FC
+
+#define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3                       0x5A8300
+
+#define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_4                       0x5A8304
+
+#define mmDMA5_QM_CP_FENCE0_RDATA_0                                  0x5A8308
+
+#define mmDMA5_QM_CP_FENCE0_RDATA_1                                  0x5A830C
+
+#define mmDMA5_QM_CP_FENCE0_RDATA_2                                  0x5A8310
+
+#define mmDMA5_QM_CP_FENCE0_RDATA_3                                  0x5A8314
+
+#define mmDMA5_QM_CP_FENCE0_RDATA_4                                  0x5A8318
+
+#define mmDMA5_QM_CP_FENCE1_RDATA_0                                  0x5A831C
+
+#define mmDMA5_QM_CP_FENCE1_RDATA_1                                  0x5A8320
+
+#define mmDMA5_QM_CP_FENCE1_RDATA_2                                  0x5A8324
+
+#define mmDMA5_QM_CP_FENCE1_RDATA_3                                  0x5A8328
+
+#define mmDMA5_QM_CP_FENCE1_RDATA_4                                  0x5A832C
+
+#define mmDMA5_QM_CP_FENCE2_RDATA_0                                  0x5A8330
+
+#define mmDMA5_QM_CP_FENCE2_RDATA_1                                  0x5A8334
+
+#define mmDMA5_QM_CP_FENCE2_RDATA_2                                  0x5A8338
+
+#define mmDMA5_QM_CP_FENCE2_RDATA_3                                  0x5A833C
+
+#define mmDMA5_QM_CP_FENCE2_RDATA_4                                  0x5A8340
+
+#define mmDMA5_QM_CP_FENCE3_RDATA_0                                  0x5A8344
+
+#define mmDMA5_QM_CP_FENCE3_RDATA_1                                  0x5A8348
+
+#define mmDMA5_QM_CP_FENCE3_RDATA_2                                  0x5A834C
+
+#define mmDMA5_QM_CP_FENCE3_RDATA_3                                  0x5A8350
+
+#define mmDMA5_QM_CP_FENCE3_RDATA_4                                  0x5A8354
+
+#define mmDMA5_QM_CP_FENCE0_CNT_0                                    0x5A8358
+
+#define mmDMA5_QM_CP_FENCE0_CNT_1                                    0x5A835C
+
+#define mmDMA5_QM_CP_FENCE0_CNT_2                                    0x5A8360
+
+#define mmDMA5_QM_CP_FENCE0_CNT_3                                    0x5A8364
+
+#define mmDMA5_QM_CP_FENCE0_CNT_4                                    0x5A8368
+
+#define mmDMA5_QM_CP_FENCE1_CNT_0                                    0x5A836C
+
+#define mmDMA5_QM_CP_FENCE1_CNT_1                                    0x5A8370
+
+#define mmDMA5_QM_CP_FENCE1_CNT_2                                    0x5A8374
+
+#define mmDMA5_QM_CP_FENCE1_CNT_3                                    0x5A8378
+
+#define mmDMA5_QM_CP_FENCE1_CNT_4                                    0x5A837C
+
+#define mmDMA5_QM_CP_FENCE2_CNT_0                                    0x5A8380
+
+#define mmDMA5_QM_CP_FENCE2_CNT_1                                    0x5A8384
+
+#define mmDMA5_QM_CP_FENCE2_CNT_2                                    0x5A8388
+
+#define mmDMA5_QM_CP_FENCE2_CNT_3                                    0x5A838C
+
+#define mmDMA5_QM_CP_FENCE2_CNT_4                                    0x5A8390
+
+#define mmDMA5_QM_CP_FENCE3_CNT_0                                    0x5A8394
+
+#define mmDMA5_QM_CP_FENCE3_CNT_1                                    0x5A8398
+
+#define mmDMA5_QM_CP_FENCE3_CNT_2                                    0x5A839C
+
+#define mmDMA5_QM_CP_FENCE3_CNT_3                                    0x5A83A0
+
+#define mmDMA5_QM_CP_FENCE3_CNT_4                                    0x5A83A4
+
+#define mmDMA5_QM_CP_STS_0                                           0x5A83A8
+
+#define mmDMA5_QM_CP_STS_1                                           0x5A83AC
+
+#define mmDMA5_QM_CP_STS_2                                           0x5A83B0
+
+#define mmDMA5_QM_CP_STS_3                                           0x5A83B4
+
+#define mmDMA5_QM_CP_STS_4                                           0x5A83B8
+
+#define mmDMA5_QM_CP_CURRENT_INST_LO_0                               0x5A83BC
+
+#define mmDMA5_QM_CP_CURRENT_INST_LO_1                               0x5A83C0
+
+#define mmDMA5_QM_CP_CURRENT_INST_LO_2                               0x5A83C4
+
+#define mmDMA5_QM_CP_CURRENT_INST_LO_3                               0x5A83C8
+
+#define mmDMA5_QM_CP_CURRENT_INST_LO_4                               0x5A83CC
+
+#define mmDMA5_QM_CP_CURRENT_INST_HI_0                               0x5A83D0
+
+#define mmDMA5_QM_CP_CURRENT_INST_HI_1                               0x5A83D4
+
+#define mmDMA5_QM_CP_CURRENT_INST_HI_2                               0x5A83D8
+
+#define mmDMA5_QM_CP_CURRENT_INST_HI_3                               0x5A83DC
+
+#define mmDMA5_QM_CP_CURRENT_INST_HI_4                               0x5A83E0
+
+#define mmDMA5_QM_CP_BARRIER_CFG_0                                   0x5A83F4
+
+#define mmDMA5_QM_CP_BARRIER_CFG_1                                   0x5A83F8
+
+#define mmDMA5_QM_CP_BARRIER_CFG_2                                   0x5A83FC
+
+#define mmDMA5_QM_CP_BARRIER_CFG_3                                   0x5A8400
+
+#define mmDMA5_QM_CP_BARRIER_CFG_4                                   0x5A8404
+
+#define mmDMA5_QM_CP_DBG_0_0                                         0x5A8408
+
+#define mmDMA5_QM_CP_DBG_0_1                                         0x5A840C
+
+#define mmDMA5_QM_CP_DBG_0_2                                         0x5A8410
+
+#define mmDMA5_QM_CP_DBG_0_3                                         0x5A8414
+
+#define mmDMA5_QM_CP_DBG_0_4                                         0x5A8418
+
+#define mmDMA5_QM_CP_ARUSER_31_11_0                                  0x5A841C
+
+#define mmDMA5_QM_CP_ARUSER_31_11_1                                  0x5A8420
+
+#define mmDMA5_QM_CP_ARUSER_31_11_2                                  0x5A8424
+
+#define mmDMA5_QM_CP_ARUSER_31_11_3                                  0x5A8428
+
+#define mmDMA5_QM_CP_ARUSER_31_11_4                                  0x5A842C
+
+#define mmDMA5_QM_CP_AWUSER_31_11_0                                  0x5A8430
+
+#define mmDMA5_QM_CP_AWUSER_31_11_1                                  0x5A8434
+
+#define mmDMA5_QM_CP_AWUSER_31_11_2                                  0x5A8438
+
+#define mmDMA5_QM_CP_AWUSER_31_11_3                                  0x5A843C
+
+#define mmDMA5_QM_CP_AWUSER_31_11_4                                  0x5A8440
+
+#define mmDMA5_QM_ARB_CFG_0                                          0x5A8A00
+
+#define mmDMA5_QM_ARB_CHOISE_Q_PUSH                                  0x5A8A04
+
+#define mmDMA5_QM_ARB_WRR_WEIGHT_0                                   0x5A8A08
+
+#define mmDMA5_QM_ARB_WRR_WEIGHT_1                                   0x5A8A0C
+
+#define mmDMA5_QM_ARB_WRR_WEIGHT_2                                   0x5A8A10
+
+#define mmDMA5_QM_ARB_WRR_WEIGHT_3                                   0x5A8A14
+
+#define mmDMA5_QM_ARB_CFG_1                                          0x5A8A18
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_0                               0x5A8A20
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_1                               0x5A8A24
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_2                               0x5A8A28
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_3                               0x5A8A2C
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_4                               0x5A8A30
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_5                               0x5A8A34
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_6                               0x5A8A38
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_7                               0x5A8A3C
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_8                               0x5A8A40
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_9                               0x5A8A44
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_10                              0x5A8A48
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_11                              0x5A8A4C
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_12                              0x5A8A50
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_13                              0x5A8A54
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_14                              0x5A8A58
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_15                              0x5A8A5C
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_16                              0x5A8A60
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_17                              0x5A8A64
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_18                              0x5A8A68
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_19                              0x5A8A6C
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_20                              0x5A8A70
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_21                              0x5A8A74
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_22                              0x5A8A78
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_23                              0x5A8A7C
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_24                              0x5A8A80
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_25                              0x5A8A84
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_26                              0x5A8A88
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_27                              0x5A8A8C
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_28                              0x5A8A90
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_29                              0x5A8A94
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_30                              0x5A8A98
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_31                              0x5A8A9C
+
+#define mmDMA5_QM_ARB_MST_CRED_INC                                   0x5A8AA0
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_0                         0x5A8AA4
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_1                         0x5A8AA8
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_2                         0x5A8AAC
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_3                         0x5A8AB0
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_4                         0x5A8AB4
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_5                         0x5A8AB8
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_6                         0x5A8ABC
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_7                         0x5A8AC0
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_8                         0x5A8AC4
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_9                         0x5A8AC8
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_10                        0x5A8ACC
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_11                        0x5A8AD0
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_12                        0x5A8AD4
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_13                        0x5A8AD8
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_14                        0x5A8ADC
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_15                        0x5A8AE0
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_16                        0x5A8AE4
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_17                        0x5A8AE8
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_18                        0x5A8AEC
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_19                        0x5A8AF0
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_20                        0x5A8AF4
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_21                        0x5A8AF8
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_22                        0x5A8AFC
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_23                        0x5A8B00
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_24                        0x5A8B04
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_25                        0x5A8B08
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_26                        0x5A8B0C
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_27                        0x5A8B10
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_28                        0x5A8B14
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_29                        0x5A8B18
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_30                        0x5A8B1C
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_31                        0x5A8B20
+
+#define mmDMA5_QM_ARB_SLV_MASTER_INC_CRED_OFST                       0x5A8B28
+
+#define mmDMA5_QM_ARB_MST_SLAVE_EN                                   0x5A8B2C
+
+#define mmDMA5_QM_ARB_MST_QUIET_PER                                  0x5A8B34
+
+#define mmDMA5_QM_ARB_SLV_CHOISE_WDT                                 0x5A8B38
+
+#define mmDMA5_QM_ARB_SLV_ID                                         0x5A8B3C
+
+#define mmDMA5_QM_ARB_MSG_MAX_INFLIGHT                               0x5A8B44
+
+#define mmDMA5_QM_ARB_MSG_AWUSER_31_11                               0x5A8B48
+
+#define mmDMA5_QM_ARB_MSG_AWUSER_SEC_PROP                            0x5A8B4C
+
+#define mmDMA5_QM_ARB_MSG_AWUSER_NON_SEC_PROP                        0x5A8B50
+
+#define mmDMA5_QM_ARB_BASE_LO                                        0x5A8B54
+
+#define mmDMA5_QM_ARB_BASE_HI                                        0x5A8B58
+
+#define mmDMA5_QM_ARB_STATE_STS                                      0x5A8B80
+
+#define mmDMA5_QM_ARB_CHOISE_FULLNESS_STS                            0x5A8B84
+
+#define mmDMA5_QM_ARB_MSG_STS                                        0x5A8B88
+
+#define mmDMA5_QM_ARB_SLV_CHOISE_Q_HEAD                              0x5A8B8C
+
+#define mmDMA5_QM_ARB_ERR_CAUSE                                      0x5A8B9C
+
+#define mmDMA5_QM_ARB_ERR_MSG_EN                                     0x5A8BA0
+
+#define mmDMA5_QM_ARB_ERR_STS_DRP                                    0x5A8BA8
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_0                                 0x5A8BB0
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_1                                 0x5A8BB4
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_2                                 0x5A8BB8
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_3                                 0x5A8BBC
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_4                                 0x5A8BC0
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_5                                 0x5A8BC4
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_6                                 0x5A8BC8
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_7                                 0x5A8BCC
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_8                                 0x5A8BD0
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_9                                 0x5A8BD4
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_10                                0x5A8BD8
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_11                                0x5A8BDC
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_12                                0x5A8BE0
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_13                                0x5A8BE4
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_14                                0x5A8BE8
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_15                                0x5A8BEC
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_16                                0x5A8BF0
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_17                                0x5A8BF4
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_18                                0x5A8BF8
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_19                                0x5A8BFC
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_20                                0x5A8C00
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_21                                0x5A8C04
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_22                                0x5A8C08
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_23                                0x5A8C0C
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_24                                0x5A8C10
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_25                                0x5A8C14
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_26                                0x5A8C18
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_27                                0x5A8C1C
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_28                                0x5A8C20
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_29                                0x5A8C24
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_30                                0x5A8C28
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_31                                0x5A8C2C
+
+#define mmDMA5_QM_CGM_CFG                                            0x5A8C70
+
+#define mmDMA5_QM_CGM_STS                                            0x5A8C74
+
+#define mmDMA5_QM_CGM_CFG1                                           0x5A8C78
+
+#define mmDMA5_QM_LOCAL_RANGE_BASE                                   0x5A8C80
+
+#define mmDMA5_QM_LOCAL_RANGE_SIZE                                   0x5A8C84
+
+#define mmDMA5_QM_CSMR_STRICT_PRIO_CFG                               0x5A8C90
+
+#define mmDMA5_QM_HBW_RD_RATE_LIM_CFG_1                              0x5A8C94
+
+#define mmDMA5_QM_LBW_WR_RATE_LIM_CFG_0                              0x5A8C98
+
+#define mmDMA5_QM_LBW_WR_RATE_LIM_CFG_1                              0x5A8C9C
+
+#define mmDMA5_QM_HBW_RD_RATE_LIM_CFG_0                              0x5A8CA0
+
+#define mmDMA5_QM_GLBL_AXCACHE                                       0x5A8CA4
+
+#define mmDMA5_QM_IND_GW_APB_CFG                                     0x5A8CB0
+
+#define mmDMA5_QM_IND_GW_APB_WDATA                                   0x5A8CB4
+
+#define mmDMA5_QM_IND_GW_APB_RDATA                                   0x5A8CB8
+
+#define mmDMA5_QM_IND_GW_APB_STATUS                                  0x5A8CBC
+
+#define mmDMA5_QM_GLBL_ERR_ADDR_LO                                   0x5A8CD0
+
+#define mmDMA5_QM_GLBL_ERR_ADDR_HI                                   0x5A8CD4
+
+#define mmDMA5_QM_GLBL_ERR_WDATA                                     0x5A8CD8
+
+#define mmDMA5_QM_GLBL_MEM_INIT_BUSY                                 0x5A8D00
+
+#endif /* ASIC_REG_DMA5_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma6_core_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma6_core_regs.h
new file mode 100644
index 000000000000..4962c13e2e2e
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma6_core_regs.h
@@ -0,0 +1,156 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DMA6_CORE_REGS_H_
+#define ASIC_REG_DMA6_CORE_REGS_H_
+
+/*
+ *****************************************
+ *   DMA6_CORE (Prototype: DMA_CORE)
+ *****************************************
+ */
+
+#define mmDMA6_CORE_CFG_0                                            0x5C0000
+
+#define mmDMA6_CORE_CFG_1                                            0x5C0004
+
+#define mmDMA6_CORE_LBW_MAX_OUTSTAND                                 0x5C0008
+
+#define mmDMA6_CORE_SRC_BASE_LO                                      0x5C0014
+
+#define mmDMA6_CORE_SRC_BASE_HI                                      0x5C0018
+
+#define mmDMA6_CORE_DST_BASE_LO                                      0x5C001C
+
+#define mmDMA6_CORE_DST_BASE_HI                                      0x5C0020
+
+#define mmDMA6_CORE_SRC_TSIZE_1                                      0x5C002C
+
+#define mmDMA6_CORE_SRC_STRIDE_1                                     0x5C0030
+
+#define mmDMA6_CORE_SRC_TSIZE_2                                      0x5C0034
+
+#define mmDMA6_CORE_SRC_STRIDE_2                                     0x5C0038
+
+#define mmDMA6_CORE_SRC_TSIZE_3                                      0x5C003C
+
+#define mmDMA6_CORE_SRC_STRIDE_3                                     0x5C0040
+
+#define mmDMA6_CORE_SRC_TSIZE_4                                      0x5C0044
+
+#define mmDMA6_CORE_SRC_STRIDE_4                                     0x5C0048
+
+#define mmDMA6_CORE_SRC_TSIZE_0                                      0x5C004C
+
+#define mmDMA6_CORE_DST_TSIZE_1                                      0x5C0054
+
+#define mmDMA6_CORE_DST_STRIDE_1                                     0x5C0058
+
+#define mmDMA6_CORE_DST_TSIZE_2                                      0x5C005C
+
+#define mmDMA6_CORE_DST_STRIDE_2                                     0x5C0060
+
+#define mmDMA6_CORE_DST_TSIZE_3                                      0x5C0064
+
+#define mmDMA6_CORE_DST_STRIDE_3                                     0x5C0068
+
+#define mmDMA6_CORE_DST_TSIZE_4                                      0x5C006C
+
+#define mmDMA6_CORE_DST_STRIDE_4                                     0x5C0070
+
+#define mmDMA6_CORE_DST_TSIZE_0                                      0x5C0074
+
+#define mmDMA6_CORE_COMMIT                                           0x5C0078
+
+#define mmDMA6_CORE_WR_COMP_WDATA                                    0x5C007C
+
+#define mmDMA6_CORE_WR_COMP_ADDR_LO                                  0x5C0080
+
+#define mmDMA6_CORE_WR_COMP_ADDR_HI                                  0x5C0084
+
+#define mmDMA6_CORE_WR_COMP_AWUSER_31_11                             0x5C0088
+
+#define mmDMA6_CORE_TE_NUMROWS                                       0x5C0094
+
+#define mmDMA6_CORE_PROT                                             0x5C00B8
+
+#define mmDMA6_CORE_SECURE_PROPS                                     0x5C00F0
+
+#define mmDMA6_CORE_NON_SECURE_PROPS                                 0x5C00F4
+
+#define mmDMA6_CORE_RD_MAX_OUTSTAND                                  0x5C0100
+
+#define mmDMA6_CORE_RD_MAX_SIZE                                      0x5C0104
+
+#define mmDMA6_CORE_RD_ARCACHE                                       0x5C0108
+
+#define mmDMA6_CORE_RD_ARUSER_31_11                                  0x5C0110
+
+#define mmDMA6_CORE_RD_INFLIGHTS                                     0x5C0114
+
+#define mmDMA6_CORE_WR_MAX_OUTSTAND                                  0x5C0120
+
+#define mmDMA6_CORE_WR_MAX_AWID                                      0x5C0124
+
+#define mmDMA6_CORE_WR_AWCACHE                                       0x5C0128
+
+#define mmDMA6_CORE_WR_AWUSER_31_11                                  0x5C0130
+
+#define mmDMA6_CORE_WR_INFLIGHTS                                     0x5C0134
+
+#define mmDMA6_CORE_RD_RATE_LIM_CFG_0                                0x5C0150
+
+#define mmDMA6_CORE_RD_RATE_LIM_CFG_1                                0x5C0154
+
+#define mmDMA6_CORE_WR_RATE_LIM_CFG_0                                0x5C0158
+
+#define mmDMA6_CORE_WR_RATE_LIM_CFG_1                                0x5C015C
+
+#define mmDMA6_CORE_ERR_CFG                                          0x5C0160
+
+#define mmDMA6_CORE_ERR_CAUSE                                        0x5C0164
+
+#define mmDMA6_CORE_ERRMSG_ADDR_LO                                   0x5C0170
+
+#define mmDMA6_CORE_ERRMSG_ADDR_HI                                   0x5C0174
+
+#define mmDMA6_CORE_ERRMSG_WDATA                                     0x5C0178
+
+#define mmDMA6_CORE_STS0                                             0x5C0190
+
+#define mmDMA6_CORE_STS1                                             0x5C0194
+
+#define mmDMA6_CORE_RD_DBGMEM_ADD                                    0x5C0200
+
+#define mmDMA6_CORE_RD_DBGMEM_DATA_WR                                0x5C0204
+
+#define mmDMA6_CORE_RD_DBGMEM_DATA_RD                                0x5C0208
+
+#define mmDMA6_CORE_RD_DBGMEM_CTRL                                   0x5C020C
+
+#define mmDMA6_CORE_RD_DBGMEM_RC                                     0x5C0210
+
+#define mmDMA6_CORE_DBG_HBW_AXI_AR_CNT                               0x5C0220
+
+#define mmDMA6_CORE_DBG_HBW_AXI_AW_CNT                               0x5C0224
+
+#define mmDMA6_CORE_DBG_LBW_AXI_AW_CNT                               0x5C0228
+
+#define mmDMA6_CORE_DBG_DESC_CNT                                     0x5C022C
+
+#define mmDMA6_CORE_DBG_STS                                          0x5C0230
+
+#define mmDMA6_CORE_DBG_RD_DESC_ID                                   0x5C0234
+
+#define mmDMA6_CORE_DBG_WR_DESC_ID                                   0x5C0238
+
+#endif /* ASIC_REG_DMA6_CORE_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma6_qm_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma6_qm_regs.h
new file mode 100644
index 000000000000..af87adb94c94
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma6_qm_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DMA6_QM_REGS_H_
+#define ASIC_REG_DMA6_QM_REGS_H_
+
+/*
+ *****************************************
+ *   DMA6_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmDMA6_QM_GLBL_CFG0                                          0x5C8000
+
+#define mmDMA6_QM_GLBL_CFG1                                          0x5C8004
+
+#define mmDMA6_QM_GLBL_PROT                                          0x5C8008
+
+#define mmDMA6_QM_GLBL_ERR_CFG                                       0x5C800C
+
+#define mmDMA6_QM_GLBL_SECURE_PROPS_0                                0x5C8010
+
+#define mmDMA6_QM_GLBL_SECURE_PROPS_1                                0x5C8014
+
+#define mmDMA6_QM_GLBL_SECURE_PROPS_2                                0x5C8018
+
+#define mmDMA6_QM_GLBL_SECURE_PROPS_3                                0x5C801C
+
+#define mmDMA6_QM_GLBL_SECURE_PROPS_4                                0x5C8020
+
+#define mmDMA6_QM_GLBL_NON_SECURE_PROPS_0                            0x5C8024
+
+#define mmDMA6_QM_GLBL_NON_SECURE_PROPS_1                            0x5C8028
+
+#define mmDMA6_QM_GLBL_NON_SECURE_PROPS_2                            0x5C802C
+
+#define mmDMA6_QM_GLBL_NON_SECURE_PROPS_3                            0x5C8030
+
+#define mmDMA6_QM_GLBL_NON_SECURE_PROPS_4                            0x5C8034
+
+#define mmDMA6_QM_GLBL_STS0                                          0x5C8038
+
+#define mmDMA6_QM_GLBL_STS1_0                                        0x5C8040
+
+#define mmDMA6_QM_GLBL_STS1_1                                        0x5C8044
+
+#define mmDMA6_QM_GLBL_STS1_2                                        0x5C8048
+
+#define mmDMA6_QM_GLBL_STS1_3                                        0x5C804C
+
+#define mmDMA6_QM_GLBL_STS1_4                                        0x5C8050
+
+#define mmDMA6_QM_GLBL_MSG_EN_0                                      0x5C8054
+
+#define mmDMA6_QM_GLBL_MSG_EN_1                                      0x5C8058
+
+#define mmDMA6_QM_GLBL_MSG_EN_2                                      0x5C805C
+
+#define mmDMA6_QM_GLBL_MSG_EN_3                                      0x5C8060
+
+#define mmDMA6_QM_GLBL_MSG_EN_4                                      0x5C8068
+
+#define mmDMA6_QM_PQ_BASE_LO_0                                       0x5C8070
+
+#define mmDMA6_QM_PQ_BASE_LO_1                                       0x5C8074
+
+#define mmDMA6_QM_PQ_BASE_LO_2                                       0x5C8078
+
+#define mmDMA6_QM_PQ_BASE_LO_3                                       0x5C807C
+
+#define mmDMA6_QM_PQ_BASE_HI_0                                       0x5C8080
+
+#define mmDMA6_QM_PQ_BASE_HI_1                                       0x5C8084
+
+#define mmDMA6_QM_PQ_BASE_HI_2                                       0x5C8088
+
+#define mmDMA6_QM_PQ_BASE_HI_3                                       0x5C808C
+
+#define mmDMA6_QM_PQ_SIZE_0                                          0x5C8090
+
+#define mmDMA6_QM_PQ_SIZE_1                                          0x5C8094
+
+#define mmDMA6_QM_PQ_SIZE_2                                          0x5C8098
+
+#define mmDMA6_QM_PQ_SIZE_3                                          0x5C809C
+
+#define mmDMA6_QM_PQ_PI_0                                            0x5C80A0
+
+#define mmDMA6_QM_PQ_PI_1                                            0x5C80A4
+
+#define mmDMA6_QM_PQ_PI_2                                            0x5C80A8
+
+#define mmDMA6_QM_PQ_PI_3                                            0x5C80AC
+
+#define mmDMA6_QM_PQ_CI_0                                            0x5C80B0
+
+#define mmDMA6_QM_PQ_CI_1                                            0x5C80B4
+
+#define mmDMA6_QM_PQ_CI_2                                            0x5C80B8
+
+#define mmDMA6_QM_PQ_CI_3                                            0x5C80BC
+
+#define mmDMA6_QM_PQ_CFG0_0                                          0x5C80C0
+
+#define mmDMA6_QM_PQ_CFG0_1                                          0x5C80C4
+
+#define mmDMA6_QM_PQ_CFG0_2                                          0x5C80C8
+
+#define mmDMA6_QM_PQ_CFG0_3                                          0x5C80CC
+
+#define mmDMA6_QM_PQ_CFG1_0                                          0x5C80D0
+
+#define mmDMA6_QM_PQ_CFG1_1                                          0x5C80D4
+
+#define mmDMA6_QM_PQ_CFG1_2                                          0x5C80D8
+
+#define mmDMA6_QM_PQ_CFG1_3                                          0x5C80DC
+
+#define mmDMA6_QM_PQ_ARUSER_31_11_0                                  0x5C80E0
+
+#define mmDMA6_QM_PQ_ARUSER_31_11_1                                  0x5C80E4
+
+#define mmDMA6_QM_PQ_ARUSER_31_11_2                                  0x5C80E8
+
+#define mmDMA6_QM_PQ_ARUSER_31_11_3                                  0x5C80EC
+
+#define mmDMA6_QM_PQ_STS0_0                                          0x5C80F0
+
+#define mmDMA6_QM_PQ_STS0_1                                          0x5C80F4
+
+#define mmDMA6_QM_PQ_STS0_2                                          0x5C80F8
+
+#define mmDMA6_QM_PQ_STS0_3                                          0x5C80FC
+
+#define mmDMA6_QM_PQ_STS1_0                                          0x5C8100
+
+#define mmDMA6_QM_PQ_STS1_1                                          0x5C8104
+
+#define mmDMA6_QM_PQ_STS1_2                                          0x5C8108
+
+#define mmDMA6_QM_PQ_STS1_3                                          0x5C810C
+
+#define mmDMA6_QM_CQ_CFG0_0                                          0x5C8110
+
+#define mmDMA6_QM_CQ_CFG0_1                                          0x5C8114
+
+#define mmDMA6_QM_CQ_CFG0_2                                          0x5C8118
+
+#define mmDMA6_QM_CQ_CFG0_3                                          0x5C811C
+
+#define mmDMA6_QM_CQ_CFG0_4                                          0x5C8120
+
+#define mmDMA6_QM_CQ_CFG1_0                                          0x5C8124
+
+#define mmDMA6_QM_CQ_CFG1_1                                          0x5C8128
+
+#define mmDMA6_QM_CQ_CFG1_2                                          0x5C812C
+
+#define mmDMA6_QM_CQ_CFG1_3                                          0x5C8130
+
+#define mmDMA6_QM_CQ_CFG1_4                                          0x5C8134
+
+#define mmDMA6_QM_CQ_ARUSER_31_11_0                                  0x5C8138
+
+#define mmDMA6_QM_CQ_ARUSER_31_11_1                                  0x5C813C
+
+#define mmDMA6_QM_CQ_ARUSER_31_11_2                                  0x5C8140
+
+#define mmDMA6_QM_CQ_ARUSER_31_11_3                                  0x5C8144
+
+#define mmDMA6_QM_CQ_ARUSER_31_11_4                                  0x5C8148
+
+#define mmDMA6_QM_CQ_STS0_0                                          0x5C814C
+
+#define mmDMA6_QM_CQ_STS0_1                                          0x5C8150
+
+#define mmDMA6_QM_CQ_STS0_2                                          0x5C8154
+
+#define mmDMA6_QM_CQ_STS0_3                                          0x5C8158
+
+#define mmDMA6_QM_CQ_STS0_4                                          0x5C815C
+
+#define mmDMA6_QM_CQ_STS1_0                                          0x5C8160
+
+#define mmDMA6_QM_CQ_STS1_1                                          0x5C8164
+
+#define mmDMA6_QM_CQ_STS1_2                                          0x5C8168
+
+#define mmDMA6_QM_CQ_STS1_3                                          0x5C816C
+
+#define mmDMA6_QM_CQ_STS1_4                                          0x5C8170
+
+#define mmDMA6_QM_CQ_PTR_LO_0                                        0x5C8174
+
+#define mmDMA6_QM_CQ_PTR_HI_0                                        0x5C8178
+
+#define mmDMA6_QM_CQ_TSIZE_0                                         0x5C817C
+
+#define mmDMA6_QM_CQ_CTL_0                                           0x5C8180
+
+#define mmDMA6_QM_CQ_PTR_LO_1                                        0x5C8184
+
+#define mmDMA6_QM_CQ_PTR_HI_1                                        0x5C8188
+
+#define mmDMA6_QM_CQ_TSIZE_1                                         0x5C818C
+
+#define mmDMA6_QM_CQ_CTL_1                                           0x5C8190
+
+#define mmDMA6_QM_CQ_PTR_LO_2                                        0x5C8194
+
+#define mmDMA6_QM_CQ_PTR_HI_2                                        0x5C8198
+
+#define mmDMA6_QM_CQ_TSIZE_2                                         0x5C819C
+
+#define mmDMA6_QM_CQ_CTL_2                                           0x5C81A0
+
+#define mmDMA6_QM_CQ_PTR_LO_3                                        0x5C81A4
+
+#define mmDMA6_QM_CQ_PTR_HI_3                                        0x5C81A8
+
+#define mmDMA6_QM_CQ_TSIZE_3                                         0x5C81AC
+
+#define mmDMA6_QM_CQ_CTL_3                                           0x5C81B0
+
+#define mmDMA6_QM_CQ_PTR_LO_4                                        0x5C81B4
+
+#define mmDMA6_QM_CQ_PTR_HI_4                                        0x5C81B8
+
+#define mmDMA6_QM_CQ_TSIZE_4                                         0x5C81BC
+
+#define mmDMA6_QM_CQ_CTL_4                                           0x5C81C0
+
+#define mmDMA6_QM_CQ_PTR_LO_STS_0                                    0x5C81C4
+
+#define mmDMA6_QM_CQ_PTR_LO_STS_1                                    0x5C81C8
+
+#define mmDMA6_QM_CQ_PTR_LO_STS_2                                    0x5C81CC
+
+#define mmDMA6_QM_CQ_PTR_LO_STS_3                                    0x5C81D0
+
+#define mmDMA6_QM_CQ_PTR_LO_STS_4                                    0x5C81D4
+
+#define mmDMA6_QM_CQ_PTR_HI_STS_0                                    0x5C81D8
+
+#define mmDMA6_QM_CQ_PTR_HI_STS_1                                    0x5C81DC
+
+#define mmDMA6_QM_CQ_PTR_HI_STS_2                                    0x5C81E0
+
+#define mmDMA6_QM_CQ_PTR_HI_STS_3                                    0x5C81E4
+
+#define mmDMA6_QM_CQ_PTR_HI_STS_4                                    0x5C81E8
+
+#define mmDMA6_QM_CQ_TSIZE_STS_0                                     0x5C81EC
+
+#define mmDMA6_QM_CQ_TSIZE_STS_1                                     0x5C81F0
+
+#define mmDMA6_QM_CQ_TSIZE_STS_2                                     0x5C81F4
+
+#define mmDMA6_QM_CQ_TSIZE_STS_3                                     0x5C81F8
+
+#define mmDMA6_QM_CQ_TSIZE_STS_4                                     0x5C81FC
+
+#define mmDMA6_QM_CQ_CTL_STS_0                                       0x5C8200
+
+#define mmDMA6_QM_CQ_CTL_STS_1                                       0x5C8204
+
+#define mmDMA6_QM_CQ_CTL_STS_2                                       0x5C8208
+
+#define mmDMA6_QM_CQ_CTL_STS_3                                       0x5C820C
+
+#define mmDMA6_QM_CQ_CTL_STS_4                                       0x5C8210
+
+#define mmDMA6_QM_CQ_IFIFO_CNT_0                                     0x5C8214
+
+#define mmDMA6_QM_CQ_IFIFO_CNT_1                                     0x5C8218
+
+#define mmDMA6_QM_CQ_IFIFO_CNT_2                                     0x5C821C
+
+#define mmDMA6_QM_CQ_IFIFO_CNT_3                                     0x5C8220
+
+#define mmDMA6_QM_CQ_IFIFO_CNT_4                                     0x5C8224
+
+#define mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_0                             0x5C8228
+
+#define mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_1                             0x5C822C
+
+#define mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_2                             0x5C8230
+
+#define mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_3                             0x5C8234
+
+#define mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_4                             0x5C8238
+
+#define mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_0                             0x5C823C
+
+#define mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_1                             0x5C8240
+
+#define mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_2                             0x5C8244
+
+#define mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_3                             0x5C8248
+
+#define mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_4                             0x5C824C
+
+#define mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_0                             0x5C8250
+
+#define mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_1                             0x5C8254
+
+#define mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_2                             0x5C8258
+
+#define mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_3                             0x5C825C
+
+#define mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_4                             0x5C8260
+
+#define mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_0                             0x5C8264
+
+#define mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_1                             0x5C8268
+
+#define mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_2                             0x5C826C
+
+#define mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_3                             0x5C8270
+
+#define mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_4                             0x5C8274
+
+#define mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_0                             0x5C8278
+
+#define mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_1                             0x5C827C
+
+#define mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_2                             0x5C8280
+
+#define mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_3                             0x5C8284
+
+#define mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_4                             0x5C8288
+
+#define mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_0                             0x5C828C
+
+#define mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_1                             0x5C8290
+
+#define mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_2                             0x5C8294
+
+#define mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_3                             0x5C8298
+
+#define mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_4                             0x5C829C
+
+#define mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_0                             0x5C82A0
+
+#define mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_1                             0x5C82A4
+
+#define mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_2                             0x5C82A8
+
+#define mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_3                             0x5C82AC
+
+#define mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_4                             0x5C82B0
+
+#define mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_0                             0x5C82B4
+
+#define mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_1                             0x5C82B8
+
+#define mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_2                             0x5C82BC
+
+#define mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_3                             0x5C82C0
+
+#define mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_4                             0x5C82C4
+
+#define mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_0                             0x5C82C8
+
+#define mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_1                             0x5C82CC
+
+#define mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_2                             0x5C82D0
+
+#define mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_3                             0x5C82D4
+
+#define mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_4                             0x5C82D8
+
+#define mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0                       0x5C82E0
+
+#define mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1                       0x5C82E4
+
+#define mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2                       0x5C82E8
+
+#define mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3                       0x5C82EC
+
+#define mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4                       0x5C82F0
+
+#define mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_0                       0x5C82F4
+
+#define mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_1                       0x5C82F8
+
+#define mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_2                       0x5C82FC
+
+#define mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3                       0x5C8300
+
+#define mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_4                       0x5C8304
+
+#define mmDMA6_QM_CP_FENCE0_RDATA_0                                  0x5C8308
+
+#define mmDMA6_QM_CP_FENCE0_RDATA_1                                  0x5C830C
+
+#define mmDMA6_QM_CP_FENCE0_RDATA_2                                  0x5C8310
+
+#define mmDMA6_QM_CP_FENCE0_RDATA_3                                  0x5C8314
+
+#define mmDMA6_QM_CP_FENCE0_RDATA_4                                  0x5C8318
+
+#define mmDMA6_QM_CP_FENCE1_RDATA_0                                  0x5C831C
+
+#define mmDMA6_QM_CP_FENCE1_RDATA_1                                  0x5C8320
+
+#define mmDMA6_QM_CP_FENCE1_RDATA_2                                  0x5C8324
+
+#define mmDMA6_QM_CP_FENCE1_RDATA_3                                  0x5C8328
+
+#define mmDMA6_QM_CP_FENCE1_RDATA_4                                  0x5C832C
+
+#define mmDMA6_QM_CP_FENCE2_RDATA_0                                  0x5C8330
+
+#define mmDMA6_QM_CP_FENCE2_RDATA_1                                  0x5C8334
+
+#define mmDMA6_QM_CP_FENCE2_RDATA_2                                  0x5C8338
+
+#define mmDMA6_QM_CP_FENCE2_RDATA_3                                  0x5C833C
+
+#define mmDMA6_QM_CP_FENCE2_RDATA_4                                  0x5C8340
+
+#define mmDMA6_QM_CP_FENCE3_RDATA_0                                  0x5C8344
+
+#define mmDMA6_QM_CP_FENCE3_RDATA_1                                  0x5C8348
+
+#define mmDMA6_QM_CP_FENCE3_RDATA_2                                  0x5C834C
+
+#define mmDMA6_QM_CP_FENCE3_RDATA_3                                  0x5C8350
+
+#define mmDMA6_QM_CP_FENCE3_RDATA_4                                  0x5C8354
+
+#define mmDMA6_QM_CP_FENCE0_CNT_0                                    0x5C8358
+
+#define mmDMA6_QM_CP_FENCE0_CNT_1                                    0x5C835C
+
+#define mmDMA6_QM_CP_FENCE0_CNT_2                                    0x5C8360
+
+#define mmDMA6_QM_CP_FENCE0_CNT_3                                    0x5C8364
+
+#define mmDMA6_QM_CP_FENCE0_CNT_4                                    0x5C8368
+
+#define mmDMA6_QM_CP_FENCE1_CNT_0                                    0x5C836C
+
+#define mmDMA6_QM_CP_FENCE1_CNT_1                                    0x5C8370
+
+#define mmDMA6_QM_CP_FENCE1_CNT_2                                    0x5C8374
+
+#define mmDMA6_QM_CP_FENCE1_CNT_3                                    0x5C8378
+
+#define mmDMA6_QM_CP_FENCE1_CNT_4                                    0x5C837C
+
+#define mmDMA6_QM_CP_FENCE2_CNT_0                                    0x5C8380
+
+#define mmDMA6_QM_CP_FENCE2_CNT_1                                    0x5C8384
+
+#define mmDMA6_QM_CP_FENCE2_CNT_2                                    0x5C8388
+
+#define mmDMA6_QM_CP_FENCE2_CNT_3                                    0x5C838C
+
+#define mmDMA6_QM_CP_FENCE2_CNT_4                                    0x5C8390
+
+#define mmDMA6_QM_CP_FENCE3_CNT_0                                    0x5C8394
+
+#define mmDMA6_QM_CP_FENCE3_CNT_1                                    0x5C8398
+
+#define mmDMA6_QM_CP_FENCE3_CNT_2                                    0x5C839C
+
+#define mmDMA6_QM_CP_FENCE3_CNT_3                                    0x5C83A0
+
+#define mmDMA6_QM_CP_FENCE3_CNT_4                                    0x5C83A4
+
+#define mmDMA6_QM_CP_STS_0                                           0x5C83A8
+
+#define mmDMA6_QM_CP_STS_1                                           0x5C83AC
+
+#define mmDMA6_QM_CP_STS_2                                           0x5C83B0
+
+#define mmDMA6_QM_CP_STS_3                                           0x5C83B4
+
+#define mmDMA6_QM_CP_STS_4                                           0x5C83B8
+
+#define mmDMA6_QM_CP_CURRENT_INST_LO_0                               0x5C83BC
+
+#define mmDMA6_QM_CP_CURRENT_INST_LO_1                               0x5C83C0
+
+#define mmDMA6_QM_CP_CURRENT_INST_LO_2                               0x5C83C4
+
+#define mmDMA6_QM_CP_CURRENT_INST_LO_3                               0x5C83C8
+
+#define mmDMA6_QM_CP_CURRENT_INST_LO_4                               0x5C83CC
+
+#define mmDMA6_QM_CP_CURRENT_INST_HI_0                               0x5C83D0
+
+#define mmDMA6_QM_CP_CURRENT_INST_HI_1                               0x5C83D4
+
+#define mmDMA6_QM_CP_CURRENT_INST_HI_2                               0x5C83D8
+
+#define mmDMA6_QM_CP_CURRENT_INST_HI_3                               0x5C83DC
+
+#define mmDMA6_QM_CP_CURRENT_INST_HI_4                               0x5C83E0
+
+#define mmDMA6_QM_CP_BARRIER_CFG_0                                   0x5C83F4
+
+#define mmDMA6_QM_CP_BARRIER_CFG_1                                   0x5C83F8
+
+#define mmDMA6_QM_CP_BARRIER_CFG_2                                   0x5C83FC
+
+#define mmDMA6_QM_CP_BARRIER_CFG_3                                   0x5C8400
+
+#define mmDMA6_QM_CP_BARRIER_CFG_4                                   0x5C8404
+
+#define mmDMA6_QM_CP_DBG_0_0                                         0x5C8408
+
+#define mmDMA6_QM_CP_DBG_0_1                                         0x5C840C
+
+#define mmDMA6_QM_CP_DBG_0_2                                         0x5C8410
+
+#define mmDMA6_QM_CP_DBG_0_3                                         0x5C8414
+
+#define mmDMA6_QM_CP_DBG_0_4                                         0x5C8418
+
+#define mmDMA6_QM_CP_ARUSER_31_11_0                                  0x5C841C
+
+#define mmDMA6_QM_CP_ARUSER_31_11_1                                  0x5C8420
+
+#define mmDMA6_QM_CP_ARUSER_31_11_2                                  0x5C8424
+
+#define mmDMA6_QM_CP_ARUSER_31_11_3                                  0x5C8428
+
+#define mmDMA6_QM_CP_ARUSER_31_11_4                                  0x5C842C
+
+#define mmDMA6_QM_CP_AWUSER_31_11_0                                  0x5C8430
+
+#define mmDMA6_QM_CP_AWUSER_31_11_1                                  0x5C8434
+
+#define mmDMA6_QM_CP_AWUSER_31_11_2                                  0x5C8438
+
+#define mmDMA6_QM_CP_AWUSER_31_11_3                                  0x5C843C
+
+#define mmDMA6_QM_CP_AWUSER_31_11_4                                  0x5C8440
+
+#define mmDMA6_QM_ARB_CFG_0                                          0x5C8A00
+
+#define mmDMA6_QM_ARB_CHOISE_Q_PUSH                                  0x5C8A04
+
+#define mmDMA6_QM_ARB_WRR_WEIGHT_0                                   0x5C8A08
+
+#define mmDMA6_QM_ARB_WRR_WEIGHT_1                                   0x5C8A0C
+
+#define mmDMA6_QM_ARB_WRR_WEIGHT_2                                   0x5C8A10
+
+#define mmDMA6_QM_ARB_WRR_WEIGHT_3                                   0x5C8A14
+
+#define mmDMA6_QM_ARB_CFG_1                                          0x5C8A18
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_0                               0x5C8A20
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_1                               0x5C8A24
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_2                               0x5C8A28
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_3                               0x5C8A2C
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_4                               0x5C8A30
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_5                               0x5C8A34
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_6                               0x5C8A38
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_7                               0x5C8A3C
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_8                               0x5C8A40
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_9                               0x5C8A44
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_10                              0x5C8A48
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_11                              0x5C8A4C
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_12                              0x5C8A50
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_13                              0x5C8A54
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_14                              0x5C8A58
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_15                              0x5C8A5C
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_16                              0x5C8A60
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_17                              0x5C8A64
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_18                              0x5C8A68
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_19                              0x5C8A6C
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_20                              0x5C8A70
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_21                              0x5C8A74
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_22                              0x5C8A78
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_23                              0x5C8A7C
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_24                              0x5C8A80
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_25                              0x5C8A84
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_26                              0x5C8A88
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_27                              0x5C8A8C
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_28                              0x5C8A90
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_29                              0x5C8A94
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_30                              0x5C8A98
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_31                              0x5C8A9C
+
+#define mmDMA6_QM_ARB_MST_CRED_INC                                   0x5C8AA0
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_0                         0x5C8AA4
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_1                         0x5C8AA8
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_2                         0x5C8AAC
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_3                         0x5C8AB0
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_4                         0x5C8AB4
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_5                         0x5C8AB8
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_6                         0x5C8ABC
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_7                         0x5C8AC0
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_8                         0x5C8AC4
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_9                         0x5C8AC8
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_10                        0x5C8ACC
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_11                        0x5C8AD0
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_12                        0x5C8AD4
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_13                        0x5C8AD8
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_14                        0x5C8ADC
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_15                        0x5C8AE0
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_16                        0x5C8AE4
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_17                        0x5C8AE8
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_18                        0x5C8AEC
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_19                        0x5C8AF0
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_20                        0x5C8AF4
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_21                        0x5C8AF8
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_22                        0x5C8AFC
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_23                        0x5C8B00
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_24                        0x5C8B04
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_25                        0x5C8B08
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_26                        0x5C8B0C
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_27                        0x5C8B10
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_28                        0x5C8B14
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_29                        0x5C8B18
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_30                        0x5C8B1C
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_31                        0x5C8B20
+
+#define mmDMA6_QM_ARB_SLV_MASTER_INC_CRED_OFST                       0x5C8B28
+
+#define mmDMA6_QM_ARB_MST_SLAVE_EN                                   0x5C8B2C
+
+#define mmDMA6_QM_ARB_MST_QUIET_PER                                  0x5C8B34
+
+#define mmDMA6_QM_ARB_SLV_CHOISE_WDT                                 0x5C8B38
+
+#define mmDMA6_QM_ARB_SLV_ID                                         0x5C8B3C
+
+#define mmDMA6_QM_ARB_MSG_MAX_INFLIGHT                               0x5C8B44
+
+#define mmDMA6_QM_ARB_MSG_AWUSER_31_11                               0x5C8B48
+
+#define mmDMA6_QM_ARB_MSG_AWUSER_SEC_PROP                            0x5C8B4C
+
+#define mmDMA6_QM_ARB_MSG_AWUSER_NON_SEC_PROP                        0x5C8B50
+
+#define mmDMA6_QM_ARB_BASE_LO                                        0x5C8B54
+
+#define mmDMA6_QM_ARB_BASE_HI                                        0x5C8B58
+
+#define mmDMA6_QM_ARB_STATE_STS                                      0x5C8B80
+
+#define mmDMA6_QM_ARB_CHOISE_FULLNESS_STS                            0x5C8B84
+
+#define mmDMA6_QM_ARB_MSG_STS                                        0x5C8B88
+
+#define mmDMA6_QM_ARB_SLV_CHOISE_Q_HEAD                              0x5C8B8C
+
+#define mmDMA6_QM_ARB_ERR_CAUSE                                      0x5C8B9C
+
+#define mmDMA6_QM_ARB_ERR_MSG_EN                                     0x5C8BA0
+
+#define mmDMA6_QM_ARB_ERR_STS_DRP                                    0x5C8BA8
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_0                                 0x5C8BB0
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_1                                 0x5C8BB4
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_2                                 0x5C8BB8
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_3                                 0x5C8BBC
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_4                                 0x5C8BC0
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_5                                 0x5C8BC4
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_6                                 0x5C8BC8
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_7                                 0x5C8BCC
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_8                                 0x5C8BD0
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_9                                 0x5C8BD4
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_10                                0x5C8BD8
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_11                                0x5C8BDC
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_12                                0x5C8BE0
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_13                                0x5C8BE4
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_14                                0x5C8BE8
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_15                                0x5C8BEC
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_16                                0x5C8BF0
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_17                                0x5C8BF4
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_18                                0x5C8BF8
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_19                                0x5C8BFC
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_20                                0x5C8C00
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_21                                0x5C8C04
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_22                                0x5C8C08
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_23                                0x5C8C0C
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_24                                0x5C8C10
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_25                                0x5C8C14
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_26                                0x5C8C18
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_27                                0x5C8C1C
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_28                                0x5C8C20
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_29                                0x5C8C24
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_30                                0x5C8C28
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_31                                0x5C8C2C
+
+#define mmDMA6_QM_CGM_CFG                                            0x5C8C70
+
+#define mmDMA6_QM_CGM_STS                                            0x5C8C74
+
+#define mmDMA6_QM_CGM_CFG1                                           0x5C8C78
+
+#define mmDMA6_QM_LOCAL_RANGE_BASE                                   0x5C8C80
+
+#define mmDMA6_QM_LOCAL_RANGE_SIZE                                   0x5C8C84
+
+#define mmDMA6_QM_CSMR_STRICT_PRIO_CFG                               0x5C8C90
+
+#define mmDMA6_QM_HBW_RD_RATE_LIM_CFG_1                              0x5C8C94
+
+#define mmDMA6_QM_LBW_WR_RATE_LIM_CFG_0                              0x5C8C98
+
+#define mmDMA6_QM_LBW_WR_RATE_LIM_CFG_1                              0x5C8C9C
+
+#define mmDMA6_QM_HBW_RD_RATE_LIM_CFG_0                              0x5C8CA0
+
+#define mmDMA6_QM_GLBL_AXCACHE                                       0x5C8CA4
+
+#define mmDMA6_QM_IND_GW_APB_CFG                                     0x5C8CB0
+
+#define mmDMA6_QM_IND_GW_APB_WDATA                                   0x5C8CB4
+
+#define mmDMA6_QM_IND_GW_APB_RDATA                                   0x5C8CB8
+
+#define mmDMA6_QM_IND_GW_APB_STATUS                                  0x5C8CBC
+
+#define mmDMA6_QM_GLBL_ERR_ADDR_LO                                   0x5C8CD0
+
+#define mmDMA6_QM_GLBL_ERR_ADDR_HI                                   0x5C8CD4
+
+#define mmDMA6_QM_GLBL_ERR_WDATA                                     0x5C8CD8
+
+#define mmDMA6_QM_GLBL_MEM_INIT_BUSY                                 0x5C8D00
+
+#endif /* ASIC_REG_DMA6_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma7_core_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma7_core_regs.h
new file mode 100644
index 000000000000..8dd705d20195
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma7_core_regs.h
@@ -0,0 +1,156 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DMA7_CORE_REGS_H_
+#define ASIC_REG_DMA7_CORE_REGS_H_
+
+/*
+ *****************************************
+ *   DMA7_CORE (Prototype: DMA_CORE)
+ *****************************************
+ */
+
+#define mmDMA7_CORE_CFG_0                                            0x5E0000
+
+#define mmDMA7_CORE_CFG_1                                            0x5E0004
+
+#define mmDMA7_CORE_LBW_MAX_OUTSTAND                                 0x5E0008
+
+#define mmDMA7_CORE_SRC_BASE_LO                                      0x5E0014
+
+#define mmDMA7_CORE_SRC_BASE_HI                                      0x5E0018
+
+#define mmDMA7_CORE_DST_BASE_LO                                      0x5E001C
+
+#define mmDMA7_CORE_DST_BASE_HI                                      0x5E0020
+
+#define mmDMA7_CORE_SRC_TSIZE_1                                      0x5E002C
+
+#define mmDMA7_CORE_SRC_STRIDE_1                                     0x5E0030
+
+#define mmDMA7_CORE_SRC_TSIZE_2                                      0x5E0034
+
+#define mmDMA7_CORE_SRC_STRIDE_2                                     0x5E0038
+
+#define mmDMA7_CORE_SRC_TSIZE_3                                      0x5E003C
+
+#define mmDMA7_CORE_SRC_STRIDE_3                                     0x5E0040
+
+#define mmDMA7_CORE_SRC_TSIZE_4                                      0x5E0044
+
+#define mmDMA7_CORE_SRC_STRIDE_4                                     0x5E0048
+
+#define mmDMA7_CORE_SRC_TSIZE_0                                      0x5E004C
+
+#define mmDMA7_CORE_DST_TSIZE_1                                      0x5E0054
+
+#define mmDMA7_CORE_DST_STRIDE_1                                     0x5E0058
+
+#define mmDMA7_CORE_DST_TSIZE_2                                      0x5E005C
+
+#define mmDMA7_CORE_DST_STRIDE_2                                     0x5E0060
+
+#define mmDMA7_CORE_DST_TSIZE_3                                      0x5E0064
+
+#define mmDMA7_CORE_DST_STRIDE_3                                     0x5E0068
+
+#define mmDMA7_CORE_DST_TSIZE_4                                      0x5E006C
+
+#define mmDMA7_CORE_DST_STRIDE_4                                     0x5E0070
+
+#define mmDMA7_CORE_DST_TSIZE_0                                      0x5E0074
+
+#define mmDMA7_CORE_COMMIT                                           0x5E0078
+
+#define mmDMA7_CORE_WR_COMP_WDATA                                    0x5E007C
+
+#define mmDMA7_CORE_WR_COMP_ADDR_LO                                  0x5E0080
+
+#define mmDMA7_CORE_WR_COMP_ADDR_HI                                  0x5E0084
+
+#define mmDMA7_CORE_WR_COMP_AWUSER_31_11                             0x5E0088
+
+#define mmDMA7_CORE_TE_NUMROWS                                       0x5E0094
+
+#define mmDMA7_CORE_PROT                                             0x5E00B8
+
+#define mmDMA7_CORE_SECURE_PROPS                                     0x5E00F0
+
+#define mmDMA7_CORE_NON_SECURE_PROPS                                 0x5E00F4
+
+#define mmDMA7_CORE_RD_MAX_OUTSTAND                                  0x5E0100
+
+#define mmDMA7_CORE_RD_MAX_SIZE                                      0x5E0104
+
+#define mmDMA7_CORE_RD_ARCACHE                                       0x5E0108
+
+#define mmDMA7_CORE_RD_ARUSER_31_11                                  0x5E0110
+
+#define mmDMA7_CORE_RD_INFLIGHTS                                     0x5E0114
+
+#define mmDMA7_CORE_WR_MAX_OUTSTAND                                  0x5E0120
+
+#define mmDMA7_CORE_WR_MAX_AWID                                      0x5E0124
+
+#define mmDMA7_CORE_WR_AWCACHE                                       0x5E0128
+
+#define mmDMA7_CORE_WR_AWUSER_31_11                                  0x5E0130
+
+#define mmDMA7_CORE_WR_INFLIGHTS                                     0x5E0134
+
+#define mmDMA7_CORE_RD_RATE_LIM_CFG_0                                0x5E0150
+
+#define mmDMA7_CORE_RD_RATE_LIM_CFG_1                                0x5E0154
+
+#define mmDMA7_CORE_WR_RATE_LIM_CFG_0                                0x5E0158
+
+#define mmDMA7_CORE_WR_RATE_LIM_CFG_1                                0x5E015C
+
+#define mmDMA7_CORE_ERR_CFG                                          0x5E0160
+
+#define mmDMA7_CORE_ERR_CAUSE                                        0x5E0164
+
+#define mmDMA7_CORE_ERRMSG_ADDR_LO                                   0x5E0170
+
+#define mmDMA7_CORE_ERRMSG_ADDR_HI                                   0x5E0174
+
+#define mmDMA7_CORE_ERRMSG_WDATA                                     0x5E0178
+
+#define mmDMA7_CORE_STS0                                             0x5E0190
+
+#define mmDMA7_CORE_STS1                                             0x5E0194
+
+#define mmDMA7_CORE_RD_DBGMEM_ADD                                    0x5E0200
+
+#define mmDMA7_CORE_RD_DBGMEM_DATA_WR                                0x5E0204
+
+#define mmDMA7_CORE_RD_DBGMEM_DATA_RD                                0x5E0208
+
+#define mmDMA7_CORE_RD_DBGMEM_CTRL                                   0x5E020C
+
+#define mmDMA7_CORE_RD_DBGMEM_RC                                     0x5E0210
+
+#define mmDMA7_CORE_DBG_HBW_AXI_AR_CNT                               0x5E0220
+
+#define mmDMA7_CORE_DBG_HBW_AXI_AW_CNT                               0x5E0224
+
+#define mmDMA7_CORE_DBG_LBW_AXI_AW_CNT                               0x5E0228
+
+#define mmDMA7_CORE_DBG_DESC_CNT                                     0x5E022C
+
+#define mmDMA7_CORE_DBG_STS                                          0x5E0230
+
+#define mmDMA7_CORE_DBG_RD_DESC_ID                                   0x5E0234
+
+#define mmDMA7_CORE_DBG_WR_DESC_ID                                   0x5E0238
+
+#endif /* ASIC_REG_DMA7_CORE_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma7_qm_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma7_qm_regs.h
new file mode 100644
index 000000000000..d6c631f63e3e
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma7_qm_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DMA7_QM_REGS_H_
+#define ASIC_REG_DMA7_QM_REGS_H_
+
+/*
+ *****************************************
+ *   DMA7_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmDMA7_QM_GLBL_CFG0                                          0x5E8000
+
+#define mmDMA7_QM_GLBL_CFG1                                          0x5E8004
+
+#define mmDMA7_QM_GLBL_PROT                                          0x5E8008
+
+#define mmDMA7_QM_GLBL_ERR_CFG                                       0x5E800C
+
+#define mmDMA7_QM_GLBL_SECURE_PROPS_0                                0x5E8010
+
+#define mmDMA7_QM_GLBL_SECURE_PROPS_1                                0x5E8014
+
+#define mmDMA7_QM_GLBL_SECURE_PROPS_2                                0x5E8018
+
+#define mmDMA7_QM_GLBL_SECURE_PROPS_3                                0x5E801C
+
+#define mmDMA7_QM_GLBL_SECURE_PROPS_4                                0x5E8020
+
+#define mmDMA7_QM_GLBL_NON_SECURE_PROPS_0                            0x5E8024
+
+#define mmDMA7_QM_GLBL_NON_SECURE_PROPS_1                            0x5E8028
+
+#define mmDMA7_QM_GLBL_NON_SECURE_PROPS_2                            0x5E802C
+
+#define mmDMA7_QM_GLBL_NON_SECURE_PROPS_3                            0x5E8030
+
+#define mmDMA7_QM_GLBL_NON_SECURE_PROPS_4                            0x5E8034
+
+#define mmDMA7_QM_GLBL_STS0                                          0x5E8038
+
+#define mmDMA7_QM_GLBL_STS1_0                                        0x5E8040
+
+#define mmDMA7_QM_GLBL_STS1_1                                        0x5E8044
+
+#define mmDMA7_QM_GLBL_STS1_2                                        0x5E8048
+
+#define mmDMA7_QM_GLBL_STS1_3                                        0x5E804C
+
+#define mmDMA7_QM_GLBL_STS1_4                                        0x5E8050
+
+#define mmDMA7_QM_GLBL_MSG_EN_0                                      0x5E8054
+
+#define mmDMA7_QM_GLBL_MSG_EN_1                                      0x5E8058
+
+#define mmDMA7_QM_GLBL_MSG_EN_2                                      0x5E805C
+
+#define mmDMA7_QM_GLBL_MSG_EN_3                                      0x5E8060
+
+#define mmDMA7_QM_GLBL_MSG_EN_4                                      0x5E8068
+
+#define mmDMA7_QM_PQ_BASE_LO_0                                       0x5E8070
+
+#define mmDMA7_QM_PQ_BASE_LO_1                                       0x5E8074
+
+#define mmDMA7_QM_PQ_BASE_LO_2                                       0x5E8078
+
+#define mmDMA7_QM_PQ_BASE_LO_3                                       0x5E807C
+
+#define mmDMA7_QM_PQ_BASE_HI_0                                       0x5E8080
+
+#define mmDMA7_QM_PQ_BASE_HI_1                                       0x5E8084
+
+#define mmDMA7_QM_PQ_BASE_HI_2                                       0x5E8088
+
+#define mmDMA7_QM_PQ_BASE_HI_3                                       0x5E808C
+
+#define mmDMA7_QM_PQ_SIZE_0                                          0x5E8090
+
+#define mmDMA7_QM_PQ_SIZE_1                                          0x5E8094
+
+#define mmDMA7_QM_PQ_SIZE_2                                          0x5E8098
+
+#define mmDMA7_QM_PQ_SIZE_3                                          0x5E809C
+
+#define mmDMA7_QM_PQ_PI_0                                            0x5E80A0
+
+#define mmDMA7_QM_PQ_PI_1                                            0x5E80A4
+
+#define mmDMA7_QM_PQ_PI_2                                            0x5E80A8
+
+#define mmDMA7_QM_PQ_PI_3                                            0x5E80AC
+
+#define mmDMA7_QM_PQ_CI_0                                            0x5E80B0
+
+#define mmDMA7_QM_PQ_CI_1                                            0x5E80B4
+
+#define mmDMA7_QM_PQ_CI_2                                            0x5E80B8
+
+#define mmDMA7_QM_PQ_CI_3                                            0x5E80BC
+
+#define mmDMA7_QM_PQ_CFG0_0                                          0x5E80C0
+
+#define mmDMA7_QM_PQ_CFG0_1                                          0x5E80C4
+
+#define mmDMA7_QM_PQ_CFG0_2                                          0x5E80C8
+
+#define mmDMA7_QM_PQ_CFG0_3                                          0x5E80CC
+
+#define mmDMA7_QM_PQ_CFG1_0                                          0x5E80D0
+
+#define mmDMA7_QM_PQ_CFG1_1                                          0x5E80D4
+
+#define mmDMA7_QM_PQ_CFG1_2                                          0x5E80D8
+
+#define mmDMA7_QM_PQ_CFG1_3                                          0x5E80DC
+
+#define mmDMA7_QM_PQ_ARUSER_31_11_0                                  0x5E80E0
+
+#define mmDMA7_QM_PQ_ARUSER_31_11_1                                  0x5E80E4
+
+#define mmDMA7_QM_PQ_ARUSER_31_11_2                                  0x5E80E8
+
+#define mmDMA7_QM_PQ_ARUSER_31_11_3                                  0x5E80EC
+
+#define mmDMA7_QM_PQ_STS0_0                                          0x5E80F0
+
+#define mmDMA7_QM_PQ_STS0_1                                          0x5E80F4
+
+#define mmDMA7_QM_PQ_STS0_2                                          0x5E80F8
+
+#define mmDMA7_QM_PQ_STS0_3                                          0x5E80FC
+
+#define mmDMA7_QM_PQ_STS1_0                                          0x5E8100
+
+#define mmDMA7_QM_PQ_STS1_1                                          0x5E8104
+
+#define mmDMA7_QM_PQ_STS1_2                                          0x5E8108
+
+#define mmDMA7_QM_PQ_STS1_3                                          0x5E810C
+
+#define mmDMA7_QM_CQ_CFG0_0                                          0x5E8110
+
+#define mmDMA7_QM_CQ_CFG0_1                                          0x5E8114
+
+#define mmDMA7_QM_CQ_CFG0_2                                          0x5E8118
+
+#define mmDMA7_QM_CQ_CFG0_3                                          0x5E811C
+
+#define mmDMA7_QM_CQ_CFG0_4                                          0x5E8120
+
+#define mmDMA7_QM_CQ_CFG1_0                                          0x5E8124
+
+#define mmDMA7_QM_CQ_CFG1_1                                          0x5E8128
+
+#define mmDMA7_QM_CQ_CFG1_2                                          0x5E812C
+
+#define mmDMA7_QM_CQ_CFG1_3                                          0x5E8130
+
+#define mmDMA7_QM_CQ_CFG1_4                                          0x5E8134
+
+#define mmDMA7_QM_CQ_ARUSER_31_11_0                                  0x5E8138
+
+#define mmDMA7_QM_CQ_ARUSER_31_11_1                                  0x5E813C
+
+#define mmDMA7_QM_CQ_ARUSER_31_11_2                                  0x5E8140
+
+#define mmDMA7_QM_CQ_ARUSER_31_11_3                                  0x5E8144
+
+#define mmDMA7_QM_CQ_ARUSER_31_11_4                                  0x5E8148
+
+#define mmDMA7_QM_CQ_STS0_0                                          0x5E814C
+
+#define mmDMA7_QM_CQ_STS0_1                                          0x5E8150
+
+#define mmDMA7_QM_CQ_STS0_2                                          0x5E8154
+
+#define mmDMA7_QM_CQ_STS0_3                                          0x5E8158
+
+#define mmDMA7_QM_CQ_STS0_4                                          0x5E815C
+
+#define mmDMA7_QM_CQ_STS1_0                                          0x5E8160
+
+#define mmDMA7_QM_CQ_STS1_1                                          0x5E8164
+
+#define mmDMA7_QM_CQ_STS1_2                                          0x5E8168
+
+#define mmDMA7_QM_CQ_STS1_3                                          0x5E816C
+
+#define mmDMA7_QM_CQ_STS1_4                                          0x5E8170
+
+#define mmDMA7_QM_CQ_PTR_LO_0                                        0x5E8174
+
+#define mmDMA7_QM_CQ_PTR_HI_0                                        0x5E8178
+
+#define mmDMA7_QM_CQ_TSIZE_0                                         0x5E817C
+
+#define mmDMA7_QM_CQ_CTL_0                                           0x5E8180
+
+#define mmDMA7_QM_CQ_PTR_LO_1                                        0x5E8184
+
+#define mmDMA7_QM_CQ_PTR_HI_1                                        0x5E8188
+
+#define mmDMA7_QM_CQ_TSIZE_1                                         0x5E818C
+
+#define mmDMA7_QM_CQ_CTL_1                                           0x5E8190
+
+#define mmDMA7_QM_CQ_PTR_LO_2                                        0x5E8194
+
+#define mmDMA7_QM_CQ_PTR_HI_2                                        0x5E8198
+
+#define mmDMA7_QM_CQ_TSIZE_2                                         0x5E819C
+
+#define mmDMA7_QM_CQ_CTL_2                                           0x5E81A0
+
+#define mmDMA7_QM_CQ_PTR_LO_3                                        0x5E81A4
+
+#define mmDMA7_QM_CQ_PTR_HI_3                                        0x5E81A8
+
+#define mmDMA7_QM_CQ_TSIZE_3                                         0x5E81AC
+
+#define mmDMA7_QM_CQ_CTL_3                                           0x5E81B0
+
+#define mmDMA7_QM_CQ_PTR_LO_4                                        0x5E81B4
+
+#define mmDMA7_QM_CQ_PTR_HI_4                                        0x5E81B8
+
+#define mmDMA7_QM_CQ_TSIZE_4                                         0x5E81BC
+
+#define mmDMA7_QM_CQ_CTL_4                                           0x5E81C0
+
+#define mmDMA7_QM_CQ_PTR_LO_STS_0                                    0x5E81C4
+
+#define mmDMA7_QM_CQ_PTR_LO_STS_1                                    0x5E81C8
+
+#define mmDMA7_QM_CQ_PTR_LO_STS_2                                    0x5E81CC
+
+#define mmDMA7_QM_CQ_PTR_LO_STS_3                                    0x5E81D0
+
+#define mmDMA7_QM_CQ_PTR_LO_STS_4                                    0x5E81D4
+
+#define mmDMA7_QM_CQ_PTR_HI_STS_0                                    0x5E81D8
+
+#define mmDMA7_QM_CQ_PTR_HI_STS_1                                    0x5E81DC
+
+#define mmDMA7_QM_CQ_PTR_HI_STS_2                                    0x5E81E0
+
+#define mmDMA7_QM_CQ_PTR_HI_STS_3                                    0x5E81E4
+
+#define mmDMA7_QM_CQ_PTR_HI_STS_4                                    0x5E81E8
+
+#define mmDMA7_QM_CQ_TSIZE_STS_0                                     0x5E81EC
+
+#define mmDMA7_QM_CQ_TSIZE_STS_1                                     0x5E81F0
+
+#define mmDMA7_QM_CQ_TSIZE_STS_2                                     0x5E81F4
+
+#define mmDMA7_QM_CQ_TSIZE_STS_3                                     0x5E81F8
+
+#define mmDMA7_QM_CQ_TSIZE_STS_4                                     0x5E81FC
+
+#define mmDMA7_QM_CQ_CTL_STS_0                                       0x5E8200
+
+#define mmDMA7_QM_CQ_CTL_STS_1                                       0x5E8204
+
+#define mmDMA7_QM_CQ_CTL_STS_2                                       0x5E8208
+
+#define mmDMA7_QM_CQ_CTL_STS_3                                       0x5E820C
+
+#define mmDMA7_QM_CQ_CTL_STS_4                                       0x5E8210
+
+#define mmDMA7_QM_CQ_IFIFO_CNT_0                                     0x5E8214
+
+#define mmDMA7_QM_CQ_IFIFO_CNT_1                                     0x5E8218
+
+#define mmDMA7_QM_CQ_IFIFO_CNT_2                                     0x5E821C
+
+#define mmDMA7_QM_CQ_IFIFO_CNT_3                                     0x5E8220
+
+#define mmDMA7_QM_CQ_IFIFO_CNT_4                                     0x5E8224
+
+#define mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_0                             0x5E8228
+
+#define mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_1                             0x5E822C
+
+#define mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_2                             0x5E8230
+
+#define mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_3                             0x5E8234
+
+#define mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_4                             0x5E8238
+
+#define mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_0                             0x5E823C
+
+#define mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_1                             0x5E8240
+
+#define mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_2                             0x5E8244
+
+#define mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_3                             0x5E8248
+
+#define mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_4                             0x5E824C
+
+#define mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_0                             0x5E8250
+
+#define mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_1                             0x5E8254
+
+#define mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_2                             0x5E8258
+
+#define mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_3                             0x5E825C
+
+#define mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_4                             0x5E8260
+
+#define mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_0                             0x5E8264
+
+#define mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_1                             0x5E8268
+
+#define mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_2                             0x5E826C
+
+#define mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_3                             0x5E8270
+
+#define mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_4                             0x5E8274
+
+#define mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_0                             0x5E8278
+
+#define mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_1                             0x5E827C
+
+#define mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_2                             0x5E8280
+
+#define mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_3                             0x5E8284
+
+#define mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_4                             0x5E8288
+
+#define mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_0                             0x5E828C
+
+#define mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_1                             0x5E8290
+
+#define mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_2                             0x5E8294
+
+#define mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_3                             0x5E8298
+
+#define mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_4                             0x5E829C
+
+#define mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_0                             0x5E82A0
+
+#define mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_1                             0x5E82A4
+
+#define mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_2                             0x5E82A8
+
+#define mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_3                             0x5E82AC
+
+#define mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_4                             0x5E82B0
+
+#define mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_0                             0x5E82B4
+
+#define mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_1                             0x5E82B8
+
+#define mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_2                             0x5E82BC
+
+#define mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_3                             0x5E82C0
+
+#define mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_4                             0x5E82C4
+
+#define mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_0                             0x5E82C8
+
+#define mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_1                             0x5E82CC
+
+#define mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_2                             0x5E82D0
+
+#define mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_3                             0x5E82D4
+
+#define mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_4                             0x5E82D8
+
+#define mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0                       0x5E82E0
+
+#define mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1                       0x5E82E4
+
+#define mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2                       0x5E82E8
+
+#define mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3                       0x5E82EC
+
+#define mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4                       0x5E82F0
+
+#define mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_0                       0x5E82F4
+
+#define mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_1                       0x5E82F8
+
+#define mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_2                       0x5E82FC
+
+#define mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3                       0x5E8300
+
+#define mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_4                       0x5E8304
+
+#define mmDMA7_QM_CP_FENCE0_RDATA_0                                  0x5E8308
+
+#define mmDMA7_QM_CP_FENCE0_RDATA_1                                  0x5E830C
+
+#define mmDMA7_QM_CP_FENCE0_RDATA_2                                  0x5E8310
+
+#define mmDMA7_QM_CP_FENCE0_RDATA_3                                  0x5E8314
+
+#define mmDMA7_QM_CP_FENCE0_RDATA_4                                  0x5E8318
+
+#define mmDMA7_QM_CP_FENCE1_RDATA_0                                  0x5E831C
+
+#define mmDMA7_QM_CP_FENCE1_RDATA_1                                  0x5E8320
+
+#define mmDMA7_QM_CP_FENCE1_RDATA_2                                  0x5E8324
+
+#define mmDMA7_QM_CP_FENCE1_RDATA_3                                  0x5E8328
+
+#define mmDMA7_QM_CP_FENCE1_RDATA_4                                  0x5E832C
+
+#define mmDMA7_QM_CP_FENCE2_RDATA_0                                  0x5E8330
+
+#define mmDMA7_QM_CP_FENCE2_RDATA_1                                  0x5E8334
+
+#define mmDMA7_QM_CP_FENCE2_RDATA_2                                  0x5E8338
+
+#define mmDMA7_QM_CP_FENCE2_RDATA_3                                  0x5E833C
+
+#define mmDMA7_QM_CP_FENCE2_RDATA_4                                  0x5E8340
+
+#define mmDMA7_QM_CP_FENCE3_RDATA_0                                  0x5E8344
+
+#define mmDMA7_QM_CP_FENCE3_RDATA_1                                  0x5E8348
+
+#define mmDMA7_QM_CP_FENCE3_RDATA_2                                  0x5E834C
+
+#define mmDMA7_QM_CP_FENCE3_RDATA_3                                  0x5E8350
+
+#define mmDMA7_QM_CP_FENCE3_RDATA_4                                  0x5E8354
+
+#define mmDMA7_QM_CP_FENCE0_CNT_0                                    0x5E8358
+
+#define mmDMA7_QM_CP_FENCE0_CNT_1                                    0x5E835C
+
+#define mmDMA7_QM_CP_FENCE0_CNT_2                                    0x5E8360
+
+#define mmDMA7_QM_CP_FENCE0_CNT_3                                    0x5E8364
+
+#define mmDMA7_QM_CP_FENCE0_CNT_4                                    0x5E8368
+
+#define mmDMA7_QM_CP_FENCE1_CNT_0                                    0x5E836C
+
+#define mmDMA7_QM_CP_FENCE1_CNT_1                                    0x5E8370
+
+#define mmDMA7_QM_CP_FENCE1_CNT_2                                    0x5E8374
+
+#define mmDMA7_QM_CP_FENCE1_CNT_3                                    0x5E8378
+
+#define mmDMA7_QM_CP_FENCE1_CNT_4                                    0x5E837C
+
+#define mmDMA7_QM_CP_FENCE2_CNT_0                                    0x5E8380
+
+#define mmDMA7_QM_CP_FENCE2_CNT_1                                    0x5E8384
+
+#define mmDMA7_QM_CP_FENCE2_CNT_2                                    0x5E8388
+
+#define mmDMA7_QM_CP_FENCE2_CNT_3                                    0x5E838C
+
+#define mmDMA7_QM_CP_FENCE2_CNT_4                                    0x5E8390
+
+#define mmDMA7_QM_CP_FENCE3_CNT_0                                    0x5E8394
+
+#define mmDMA7_QM_CP_FENCE3_CNT_1                                    0x5E8398
+
+#define mmDMA7_QM_CP_FENCE3_CNT_2                                    0x5E839C
+
+#define mmDMA7_QM_CP_FENCE3_CNT_3                                    0x5E83A0
+
+#define mmDMA7_QM_CP_FENCE3_CNT_4                                    0x5E83A4
+
+#define mmDMA7_QM_CP_STS_0                                           0x5E83A8
+
+#define mmDMA7_QM_CP_STS_1                                           0x5E83AC
+
+#define mmDMA7_QM_CP_STS_2                                           0x5E83B0
+
+#define mmDMA7_QM_CP_STS_3                                           0x5E83B4
+
+#define mmDMA7_QM_CP_STS_4                                           0x5E83B8
+
+#define mmDMA7_QM_CP_CURRENT_INST_LO_0                               0x5E83BC
+
+#define mmDMA7_QM_CP_CURRENT_INST_LO_1                               0x5E83C0
+
+#define mmDMA7_QM_CP_CURRENT_INST_LO_2                               0x5E83C4
+
+#define mmDMA7_QM_CP_CURRENT_INST_LO_3                               0x5E83C8
+
+#define mmDMA7_QM_CP_CURRENT_INST_LO_4                               0x5E83CC
+
+#define mmDMA7_QM_CP_CURRENT_INST_HI_0                               0x5E83D0
+
+#define mmDMA7_QM_CP_CURRENT_INST_HI_1                               0x5E83D4
+
+#define mmDMA7_QM_CP_CURRENT_INST_HI_2                               0x5E83D8
+
+#define mmDMA7_QM_CP_CURRENT_INST_HI_3                               0x5E83DC
+
+#define mmDMA7_QM_CP_CURRENT_INST_HI_4                               0x5E83E0
+
+#define mmDMA7_QM_CP_BARRIER_CFG_0                                   0x5E83F4
+
+#define mmDMA7_QM_CP_BARRIER_CFG_1                                   0x5E83F8
+
+#define mmDMA7_QM_CP_BARRIER_CFG_2                                   0x5E83FC
+
+#define mmDMA7_QM_CP_BARRIER_CFG_3                                   0x5E8400
+
+#define mmDMA7_QM_CP_BARRIER_CFG_4                                   0x5E8404
+
+#define mmDMA7_QM_CP_DBG_0_0                                         0x5E8408
+
+#define mmDMA7_QM_CP_DBG_0_1                                         0x5E840C
+
+#define mmDMA7_QM_CP_DBG_0_2                                         0x5E8410
+
+#define mmDMA7_QM_CP_DBG_0_3                                         0x5E8414
+
+#define mmDMA7_QM_CP_DBG_0_4                                         0x5E8418
+
+#define mmDMA7_QM_CP_ARUSER_31_11_0                                  0x5E841C
+
+#define mmDMA7_QM_CP_ARUSER_31_11_1                                  0x5E8420
+
+#define mmDMA7_QM_CP_ARUSER_31_11_2                                  0x5E8424
+
+#define mmDMA7_QM_CP_ARUSER_31_11_3                                  0x5E8428
+
+#define mmDMA7_QM_CP_ARUSER_31_11_4                                  0x5E842C
+
+#define mmDMA7_QM_CP_AWUSER_31_11_0                                  0x5E8430
+
+#define mmDMA7_QM_CP_AWUSER_31_11_1                                  0x5E8434
+
+#define mmDMA7_QM_CP_AWUSER_31_11_2                                  0x5E8438
+
+#define mmDMA7_QM_CP_AWUSER_31_11_3                                  0x5E843C
+
+#define mmDMA7_QM_CP_AWUSER_31_11_4                                  0x5E8440
+
+#define mmDMA7_QM_ARB_CFG_0                                          0x5E8A00
+
+#define mmDMA7_QM_ARB_CHOISE_Q_PUSH                                  0x5E8A04
+
+#define mmDMA7_QM_ARB_WRR_WEIGHT_0                                   0x5E8A08
+
+#define mmDMA7_QM_ARB_WRR_WEIGHT_1                                   0x5E8A0C
+
+#define mmDMA7_QM_ARB_WRR_WEIGHT_2                                   0x5E8A10
+
+#define mmDMA7_QM_ARB_WRR_WEIGHT_3                                   0x5E8A14
+
+#define mmDMA7_QM_ARB_CFG_1                                          0x5E8A18
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_0                               0x5E8A20
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_1                               0x5E8A24
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_2                               0x5E8A28
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_3                               0x5E8A2C
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_4                               0x5E8A30
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_5                               0x5E8A34
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_6                               0x5E8A38
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_7                               0x5E8A3C
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_8                               0x5E8A40
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_9                               0x5E8A44
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_10                              0x5E8A48
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_11                              0x5E8A4C
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_12                              0x5E8A50
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_13                              0x5E8A54
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_14                              0x5E8A58
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_15                              0x5E8A5C
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_16                              0x5E8A60
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_17                              0x5E8A64
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_18                              0x5E8A68
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_19                              0x5E8A6C
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_20                              0x5E8A70
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_21                              0x5E8A74
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_22                              0x5E8A78
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_23                              0x5E8A7C
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_24                              0x5E8A80
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_25                              0x5E8A84
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_26                              0x5E8A88
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_27                              0x5E8A8C
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_28                              0x5E8A90
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_29                              0x5E8A94
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_30                              0x5E8A98
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_31                              0x5E8A9C
+
+#define mmDMA7_QM_ARB_MST_CRED_INC                                   0x5E8AA0
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_0                         0x5E8AA4
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_1                         0x5E8AA8
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_2                         0x5E8AAC
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_3                         0x5E8AB0
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_4                         0x5E8AB4
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_5                         0x5E8AB8
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_6                         0x5E8ABC
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_7                         0x5E8AC0
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_8                         0x5E8AC4
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_9                         0x5E8AC8
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_10                        0x5E8ACC
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_11                        0x5E8AD0
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_12                        0x5E8AD4
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_13                        0x5E8AD8
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_14                        0x5E8ADC
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_15                        0x5E8AE0
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_16                        0x5E8AE4
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_17                        0x5E8AE8
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_18                        0x5E8AEC
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_19                        0x5E8AF0
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_20                        0x5E8AF4
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_21                        0x5E8AF8
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_22                        0x5E8AFC
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_23                        0x5E8B00
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_24                        0x5E8B04
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_25                        0x5E8B08
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_26                        0x5E8B0C
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_27                        0x5E8B10
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_28                        0x5E8B14
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_29                        0x5E8B18
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_30                        0x5E8B1C
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_31                        0x5E8B20
+
+#define mmDMA7_QM_ARB_SLV_MASTER_INC_CRED_OFST                       0x5E8B28
+
+#define mmDMA7_QM_ARB_MST_SLAVE_EN                                   0x5E8B2C
+
+#define mmDMA7_QM_ARB_MST_QUIET_PER                                  0x5E8B34
+
+#define mmDMA7_QM_ARB_SLV_CHOISE_WDT                                 0x5E8B38
+
+#define mmDMA7_QM_ARB_SLV_ID                                         0x5E8B3C
+
+#define mmDMA7_QM_ARB_MSG_MAX_INFLIGHT                               0x5E8B44
+
+#define mmDMA7_QM_ARB_MSG_AWUSER_31_11                               0x5E8B48
+
+#define mmDMA7_QM_ARB_MSG_AWUSER_SEC_PROP                            0x5E8B4C
+
+#define mmDMA7_QM_ARB_MSG_AWUSER_NON_SEC_PROP                        0x5E8B50
+
+#define mmDMA7_QM_ARB_BASE_LO                                        0x5E8B54
+
+#define mmDMA7_QM_ARB_BASE_HI                                        0x5E8B58
+
+#define mmDMA7_QM_ARB_STATE_STS                                      0x5E8B80
+
+#define mmDMA7_QM_ARB_CHOISE_FULLNESS_STS                            0x5E8B84
+
+#define mmDMA7_QM_ARB_MSG_STS                                        0x5E8B88
+
+#define mmDMA7_QM_ARB_SLV_CHOISE_Q_HEAD                              0x5E8B8C
+
+#define mmDMA7_QM_ARB_ERR_CAUSE                                      0x5E8B9C
+
+#define mmDMA7_QM_ARB_ERR_MSG_EN                                     0x5E8BA0
+
+#define mmDMA7_QM_ARB_ERR_STS_DRP                                    0x5E8BA8
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_0                                 0x5E8BB0
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_1                                 0x5E8BB4
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_2                                 0x5E8BB8
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_3                                 0x5E8BBC
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_4                                 0x5E8BC0
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_5                                 0x5E8BC4
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_6                                 0x5E8BC8
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_7                                 0x5E8BCC
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_8                                 0x5E8BD0
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_9                                 0x5E8BD4
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_10                                0x5E8BD8
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_11                                0x5E8BDC
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_12                                0x5E8BE0
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_13                                0x5E8BE4
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_14                                0x5E8BE8
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_15                                0x5E8BEC
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_16                                0x5E8BF0
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_17                                0x5E8BF4
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_18                                0x5E8BF8
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_19                                0x5E8BFC
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_20                                0x5E8C00
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_21                                0x5E8C04
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_22                                0x5E8C08
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_23                                0x5E8C0C
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_24                                0x5E8C10
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_25                                0x5E8C14
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_26                                0x5E8C18
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_27                                0x5E8C1C
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_28                                0x5E8C20
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_29                                0x5E8C24
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_30                                0x5E8C28
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_31                                0x5E8C2C
+
+#define mmDMA7_QM_CGM_CFG                                            0x5E8C70
+
+#define mmDMA7_QM_CGM_STS                                            0x5E8C74
+
+#define mmDMA7_QM_CGM_CFG1                                           0x5E8C78
+
+#define mmDMA7_QM_LOCAL_RANGE_BASE                                   0x5E8C80
+
+#define mmDMA7_QM_LOCAL_RANGE_SIZE                                   0x5E8C84
+
+#define mmDMA7_QM_CSMR_STRICT_PRIO_CFG                               0x5E8C90
+
+#define mmDMA7_QM_HBW_RD_RATE_LIM_CFG_1                              0x5E8C94
+
+#define mmDMA7_QM_LBW_WR_RATE_LIM_CFG_0                              0x5E8C98
+
+#define mmDMA7_QM_LBW_WR_RATE_LIM_CFG_1                              0x5E8C9C
+
+#define mmDMA7_QM_HBW_RD_RATE_LIM_CFG_0                              0x5E8CA0
+
+#define mmDMA7_QM_GLBL_AXCACHE                                       0x5E8CA4
+
+#define mmDMA7_QM_IND_GW_APB_CFG                                     0x5E8CB0
+
+#define mmDMA7_QM_IND_GW_APB_WDATA                                   0x5E8CB4
+
+#define mmDMA7_QM_IND_GW_APB_RDATA                                   0x5E8CB8
+
+#define mmDMA7_QM_IND_GW_APB_STATUS                                  0x5E8CBC
+
+#define mmDMA7_QM_GLBL_ERR_ADDR_LO                                   0x5E8CD0
+
+#define mmDMA7_QM_GLBL_ERR_ADDR_HI                                   0x5E8CD4
+
+#define mmDMA7_QM_GLBL_ERR_WDATA                                     0x5E8CD8
+
+#define mmDMA7_QM_GLBL_MEM_INIT_BUSY                                 0x5E8D00
+
+#endif /* ASIC_REG_DMA7_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_n_down_ch0_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_n_down_ch0_regs.h
new file mode 100644
index 000000000000..8c1c72df4469
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_n_down_ch0_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DMA_IF_E_N_DOWN_CH0_REGS_H_
+#define ASIC_REG_DMA_IF_E_N_DOWN_CH0_REGS_H_
+
+/*
+ *****************************************
+ *   DMA_IF_E_N_DOWN_CH0 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmDMA_IF_E_N_DOWN_CH0_PERM_SEL                               0x4E1108
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_0                          0x4E1114
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_1                          0x4E1118
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_2                          0x4E111C
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_3                          0x4E1120
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_4                          0x4E1124
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_5                          0x4E1128
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_6                          0x4E112C
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_7                          0x4E1130
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_8                          0x4E1134
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_9                          0x4E1138
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_10                         0x4E113C
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_11                         0x4E1140
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_12                         0x4E1144
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_13                         0x4E1148
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_14                         0x4E114C
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_15                         0x4E1150
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_16                         0x4E1154
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_17                         0x4E1158
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_18                         0x4E115C
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_19                         0x4E1160
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_20                         0x4E1164
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_21                         0x4E1168
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_22                         0x4E116C
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_23                         0x4E1170
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_24                         0x4E1174
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_25                         0x4E1178
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_26                         0x4E117C
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_27                         0x4E1180
+
+#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_0                         0x4E1184
+
+#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_1                         0x4E1188
+
+#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_2                         0x4E118C
+
+#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_3                         0x4E1190
+
+#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_4                         0x4E1194
+
+#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_5                         0x4E1198
+
+#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_6                         0x4E119C
+
+#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_7                         0x4E11A0
+
+#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_8                         0x4E11A4
+
+#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_9                         0x4E11A8
+
+#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_10                        0x4E11AC
+
+#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_11                        0x4E11B0
+
+#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_12                        0x4E11B4
+
+#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_13                        0x4E11B8
+
+#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_14                        0x4E11BC
+
+#define mmDMA_IF_E_N_DOWN_CH0_SCRAM_SRAM_EN                          0x4E126C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RL_HBM_EN                              0x4E1274
+
+#define mmDMA_IF_E_N_DOWN_CH0_RL_HBM_SAT                             0x4E1278
+
+#define mmDMA_IF_E_N_DOWN_CH0_RL_HBM_RST                             0x4E127C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RL_HBM_TIMEOUT                         0x4E1280
+
+#define mmDMA_IF_E_N_DOWN_CH0_SCRAM_HBM_EN                           0x4E1284
+
+#define mmDMA_IF_E_N_DOWN_CH0_RL_PCI_EN                              0x4E1288
+
+#define mmDMA_IF_E_N_DOWN_CH0_RL_PCI_SAT                             0x4E128C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RL_PCI_RST                             0x4E1290
+
+#define mmDMA_IF_E_N_DOWN_CH0_RL_PCI_TIMEOUT                         0x4E1294
+
+#define mmDMA_IF_E_N_DOWN_CH0_RL_SRAM_EN                             0x4E129C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RL_SRAM_SAT                            0x4E12A0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RL_SRAM_RST                            0x4E12A4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RL_SRAM_TIMEOUT                        0x4E12AC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RL_SRAM_RED                            0x4E12B4
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_HBM_EN                             0x4E12EC
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_PCI_EN                             0x4E12F0
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_HBM_WR_SIZE                        0x4E12F4
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_PCI_WR_SIZE                        0x4E12F8
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_PCI_CTR_SET_EN                  0x4E1404
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_PCI_CTR_SET                     0x4E1408
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_PCI_CTR_WRAP                    0x4E140C
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_PCI_CTR_CNT                     0x4E1410
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM_CTR_SET_EN                  0x4E1414
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM_CTR_SET                     0x4E1418
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_HBM_RD_SIZE                        0x4E141C
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_PCI_RD_SIZE                        0x4E1420
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_PCI_CTR_SET_EN                  0x4E1424
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_PCI_CTR_SET                     0x4E1428
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_PCI_CTR_WRAP                    0x4E142C
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_PCI_CTR_CNT                     0x4E1430
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM_CTR_SET_EN                  0x4E1434
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM_CTR_SET                     0x4E1438
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_SEL_0                           0x4E1450
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_SEL_1                           0x4E1454
+
+#define mmDMA_IF_E_N_DOWN_CH0_NON_LIN_EN                             0x4E1480
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_BANK_0                         0x4E1500
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_BANK_1                         0x4E1504
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_BANK_2                         0x4E1508
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_BANK_3                         0x4E150C
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_BANK_4                         0x4E1510
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_0                       0x4E1514
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_1                       0x4E1520
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_2                       0x4E1524
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_3                       0x4E1528
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_4                       0x4E152C
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_5                       0x4E1530
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_6                       0x4E1534
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_7                       0x4E1538
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_8                       0x4E153C
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_9                       0x4E1540
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_0                        0x4E1550
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_1                        0x4E1554
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_2                        0x4E1558
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_3                        0x4E155C
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_4                        0x4E1560
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_5                        0x4E1564
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_6                        0x4E1568
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_7                        0x4E156C
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_8                        0x4E1570
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_9                        0x4E1574
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_10                       0x4E1578
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_11                       0x4E157C
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_12                       0x4E1580
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_13                       0x4E1584
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_14                       0x4E1588
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_15                       0x4E158C
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_16                       0x4E1590
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_17                       0x4E1594
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_18                       0x4E1598
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_0                0x4E15E4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_1                0x4E15E8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_2                0x4E15EC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_3                0x4E15F0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_4                0x4E15F4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_5                0x4E15F8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_6                0x4E15FC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_7                0x4E1600
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_8                0x4E1604
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_9                0x4E1608
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_10               0x4E160C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_11               0x4E1610
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_12               0x4E1614
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_13               0x4E1618
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_14               0x4E161C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_15               0x4E1620
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_0               0x4E1624
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_1               0x4E1628
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_2               0x4E162C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_3               0x4E1630
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_4               0x4E1634
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_5               0x4E1638
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_6               0x4E163C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_7               0x4E1640
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_8               0x4E1644
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_9               0x4E1648
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_10              0x4E164C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_11              0x4E1650
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_12              0x4E1654
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_13              0x4E1658
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_14              0x4E165C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_15              0x4E1660
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_0                0x4E1664
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_1                0x4E1668
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_2                0x4E166C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_3                0x4E1670
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_4                0x4E1674
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_5                0x4E1678
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_6                0x4E167C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_7                0x4E1680
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_8                0x4E1684
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_9                0x4E1688
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_10               0x4E168C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_11               0x4E1690
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_12               0x4E1694
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_13               0x4E1698
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_14               0x4E169C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_15               0x4E16A0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_0               0x4E16A4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_1               0x4E16A8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_2               0x4E16AC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_3               0x4E16B0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_4               0x4E16B4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_5               0x4E16B8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_6               0x4E16BC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_7               0x4E16C0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_8               0x4E16C4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_9               0x4E16C8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_10              0x4E16CC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_11              0x4E16D0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_12              0x4E16D4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_13              0x4E16D8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_14              0x4E16DC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_15              0x4E16E0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_0               0x4E16E4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_1               0x4E16E8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_2               0x4E16EC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_3               0x4E16F0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_4               0x4E16F4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_5               0x4E16F8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_6               0x4E16FC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_7               0x4E1700
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_8               0x4E1704
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_9               0x4E1708
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_10              0x4E170C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_11              0x4E1710
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_12              0x4E1714
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_13              0x4E1718
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_14              0x4E171C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_15              0x4E1720
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_0              0x4E1724
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_1              0x4E1728
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_2              0x4E172C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_3              0x4E1730
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_4              0x4E1734
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_5              0x4E1738
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_6              0x4E173C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_7              0x4E1740
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_8              0x4E1744
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_9              0x4E1748
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_10             0x4E174C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_11             0x4E1750
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_12             0x4E1754
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_13             0x4E1758
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_14             0x4E175C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_15             0x4E1760
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_0               0x4E1764
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_1               0x4E1768
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_2               0x4E176C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_3               0x4E1770
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_4               0x4E1774
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_5               0x4E1778
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_6               0x4E177C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_7               0x4E1780
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_8               0x4E1784
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_9               0x4E1788
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_10              0x4E178C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_11              0x4E1790
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_12              0x4E1794
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_13              0x4E1798
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_14              0x4E179C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_15              0x4E17A0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_0              0x4E17A4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_1              0x4E17A8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_2              0x4E17AC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_3              0x4E17B0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_4              0x4E17B4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_5              0x4E17B8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_6              0x4E17BC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_7              0x4E17C0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_8              0x4E17C4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_9              0x4E17C8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_10             0x4E17CC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_11             0x4E17D0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_12             0x4E17D4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_13             0x4E17D8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_14             0x4E17DC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_15             0x4E17E0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_0                0x4E1824
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_1                0x4E1828
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_2                0x4E182C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_3                0x4E1830
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_4                0x4E1834
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_5                0x4E1838
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_6                0x4E183C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_7                0x4E1840
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_8                0x4E1844
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_9                0x4E1848
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_10               0x4E184C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_11               0x4E1850
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_12               0x4E1854
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_13               0x4E1858
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_14               0x4E185C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_15               0x4E1860
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_0               0x4E1864
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_1               0x4E1868
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_2               0x4E186C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_3               0x4E1870
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_4               0x4E1874
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_5               0x4E1878
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_6               0x4E187C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_7               0x4E1880
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_8               0x4E1884
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_9               0x4E1888
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_10              0x4E188C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_11              0x4E1890
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_12              0x4E1894
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_13              0x4E1898
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_14              0x4E189C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_15              0x4E18A0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_0                0x4E18A4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_1                0x4E18A8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_2                0x4E18AC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_3                0x4E18B0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_4                0x4E18B4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_5                0x4E18B8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_6                0x4E18BC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_7                0x4E18C0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_8                0x4E18C4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_9                0x4E18C8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_10               0x4E18CC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_11               0x4E18D0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_12               0x4E18D4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_13               0x4E18D8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_14               0x4E18DC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_15               0x4E18E0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_0               0x4E18E4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_1               0x4E18E8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_2               0x4E18EC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_3               0x4E18F0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_4               0x4E18F4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_5               0x4E18F8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_6               0x4E18FC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_7               0x4E1900
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_8               0x4E1904
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_9               0x4E1908
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_10              0x4E190C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_11              0x4E1910
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_12              0x4E1914
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_13              0x4E1918
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_14              0x4E191C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_15              0x4E1920
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_0               0x4E1924
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_1               0x4E1928
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_2               0x4E192C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_3               0x4E1930
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_4               0x4E1934
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_5               0x4E1938
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_6               0x4E193C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_7               0x4E1940
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_8               0x4E1944
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_9               0x4E1948
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_10              0x4E194C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_11              0x4E1950
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_12              0x4E1954
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_13              0x4E1958
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_14              0x4E195C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_15              0x4E1960
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_0              0x4E1964
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_1              0x4E1968
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_2              0x4E196C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_3              0x4E1970
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_4              0x4E1974
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_5              0x4E1978
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_6              0x4E197C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_7              0x4E1980
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_8              0x4E1984
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_9              0x4E1988
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_10             0x4E198C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_11             0x4E1990
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_12             0x4E1994
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_13             0x4E1998
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_14             0x4E199C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_15             0x4E19A0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_0               0x4E19A4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_1               0x4E19A8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_2               0x4E19AC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_3               0x4E19B0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_4               0x4E19B4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_5               0x4E19B8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_6               0x4E19BC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_7               0x4E19C0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_8               0x4E19C4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_9               0x4E19C8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_10              0x4E19CC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_11              0x4E19D0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_12              0x4E19D4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_13              0x4E19D8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_14              0x4E19DC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_15              0x4E19E0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_0              0x4E19E4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_1              0x4E19E8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_2              0x4E19EC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_3              0x4E19F0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_4              0x4E19F4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_5              0x4E19F8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_6              0x4E19FC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_7              0x4E1A00
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_8              0x4E1A04
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_9              0x4E1A08
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_10             0x4E1A0C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_11             0x4E1A10
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_12             0x4E1A14
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_13             0x4E1A18
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_14             0x4E1A1C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_15             0x4E1A20
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_HIT_AW                       0x4E1A64
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_HIT_AR                       0x4E1A68
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_HIT_AW                      0x4E1A6C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_HIT_AR                      0x4E1A70
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_CFG                                0x4E1B64
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_SHIFT                              0x4E1B68
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_EXPECTED_LAT_0                     0x4E1B6C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_EXPECTED_LAT_1                     0x4E1B70
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_EXPECTED_LAT_2                     0x4E1B74
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_EXPECTED_LAT_3                     0x4E1B78
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_EXPECTED_LAT_4                     0x4E1B7C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_EXPECTED_LAT_5                     0x4E1B80
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_EXPECTED_LAT_6                     0x4E1B84
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_EXPECTED_LAT_7                     0x4E1B88
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_TOKEN_0                            0x4E1BAC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_TOKEN_1                            0x4E1BB0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_TOKEN_2                            0x4E1BB4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_TOKEN_3                            0x4E1BB8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_TOKEN_4                            0x4E1BBC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_TOKEN_5                            0x4E1BC0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_TOKEN_6                            0x4E1BC4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_TOKEN_7                            0x4E1BC8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_BANK_ID_0                          0x4E1BEC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_BANK_ID_1                          0x4E1BF0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_BANK_ID_2                          0x4E1BF4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_BANK_ID_3                          0x4E1BF8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_BANK_ID_4                          0x4E1BFC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_BANK_ID_5                          0x4E1C00
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_BANK_ID_6                          0x4E1C04
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_BANK_ID_7                          0x4E1C08
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_WDT                                0x4E1C2C
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_WRAP               0x4E1C30
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_WRAP               0x4E1C34
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_WRAP               0x4E1C38
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_WRAP               0x4E1C3C
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_WRAP               0x4E1C40
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_WRAP               0x4E1C44
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_WRAP               0x4E1C48
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_WRAP               0x4E1C4C
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_CNT                0x4E1C50
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_CNT                0x4E1C54
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_CNT                0x4E1C58
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_CNT                0x4E1C5C
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_CNT                0x4E1C60
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_CNT                0x4E1C64
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_CNT                0x4E1C68
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_CNT                0x4E1C6C
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_WRAP               0x4E1C70
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_WRAP               0x4E1C74
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_WRAP               0x4E1C78
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_WRAP               0x4E1C7C
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_WRAP               0x4E1C80
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_WRAP               0x4E1C84
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_WRAP               0x4E1C88
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_WRAP               0x4E1C8C
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_CNT                0x4E1C90
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_CNT                0x4E1C94
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_CNT                0x4E1C98
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_CNT                0x4E1C9C
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_CNT                0x4E1CA0
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_CNT                0x4E1CA4
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_CNT                0x4E1CA8
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_CNT                0x4E1CAC
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_PC_SEL_0                        0x4E1CB0
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_PC_SEL_1                        0x4E1CB4
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_PC_SEL_2                        0x4E1CB8
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_PC_SEL_3                        0x4E1CBC
+
+#endif /* ASIC_REG_DMA_IF_E_N_DOWN_CH0_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_n_down_ch1_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_n_down_ch1_regs.h
new file mode 100644
index 000000000000..b2b593fcec30
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_n_down_ch1_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DMA_IF_E_N_DOWN_CH1_REGS_H_
+#define ASIC_REG_DMA_IF_E_N_DOWN_CH1_REGS_H_
+
+/*
+ *****************************************
+ *   DMA_IF_E_N_DOWN_CH1 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmDMA_IF_E_N_DOWN_CH1_PERM_SEL                               0x4E2108
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_0                          0x4E2114
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_1                          0x4E2118
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_2                          0x4E211C
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_3                          0x4E2120
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_4                          0x4E2124
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_5                          0x4E2128
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_6                          0x4E212C
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_7                          0x4E2130
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_8                          0x4E2134
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_9                          0x4E2138
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_10                         0x4E213C
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_11                         0x4E2140
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_12                         0x4E2144
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_13                         0x4E2148
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_14                         0x4E214C
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_15                         0x4E2150
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_16                         0x4E2154
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_17                         0x4E2158
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_18                         0x4E215C
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_19                         0x4E2160
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_20                         0x4E2164
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_21                         0x4E2168
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_22                         0x4E216C
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_23                         0x4E2170
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_24                         0x4E2174
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_25                         0x4E2178
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_26                         0x4E217C
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_27                         0x4E2180
+
+#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_0                         0x4E2184
+
+#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_1                         0x4E2188
+
+#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_2                         0x4E218C
+
+#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_3                         0x4E2190
+
+#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_4                         0x4E2194
+
+#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_5                         0x4E2198
+
+#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_6                         0x4E219C
+
+#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_7                         0x4E21A0
+
+#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_8                         0x4E21A4
+
+#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_9                         0x4E21A8
+
+#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_10                        0x4E21AC
+
+#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_11                        0x4E21B0
+
+#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_12                        0x4E21B4
+
+#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_13                        0x4E21B8
+
+#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_14                        0x4E21BC
+
+#define mmDMA_IF_E_N_DOWN_CH1_SCRAM_SRAM_EN                          0x4E226C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RL_HBM_EN                              0x4E2274
+
+#define mmDMA_IF_E_N_DOWN_CH1_RL_HBM_SAT                             0x4E2278
+
+#define mmDMA_IF_E_N_DOWN_CH1_RL_HBM_RST                             0x4E227C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RL_HBM_TIMEOUT                         0x4E2280
+
+#define mmDMA_IF_E_N_DOWN_CH1_SCRAM_HBM_EN                           0x4E2284
+
+#define mmDMA_IF_E_N_DOWN_CH1_RL_PCI_EN                              0x4E2288
+
+#define mmDMA_IF_E_N_DOWN_CH1_RL_PCI_SAT                             0x4E228C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RL_PCI_RST                             0x4E2290
+
+#define mmDMA_IF_E_N_DOWN_CH1_RL_PCI_TIMEOUT                         0x4E2294
+
+#define mmDMA_IF_E_N_DOWN_CH1_RL_SRAM_EN                             0x4E229C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RL_SRAM_SAT                            0x4E22A0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RL_SRAM_RST                            0x4E22A4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RL_SRAM_TIMEOUT                        0x4E22AC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RL_SRAM_RED                            0x4E22B4
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_HBM_EN                             0x4E22EC
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_PCI_EN                             0x4E22F0
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_HBM_WR_SIZE                        0x4E22F4
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_PCI_WR_SIZE                        0x4E22F8
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_PCI_CTR_SET_EN                  0x4E2404
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_PCI_CTR_SET                     0x4E2408
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_PCI_CTR_WRAP                    0x4E240C
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_PCI_CTR_CNT                     0x4E2410
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM_CTR_SET_EN                  0x4E2414
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM_CTR_SET                     0x4E2418
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_HBM_RD_SIZE                        0x4E241C
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_PCI_RD_SIZE                        0x4E2420
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_PCI_CTR_SET_EN                  0x4E2424
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_PCI_CTR_SET                     0x4E2428
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_PCI_CTR_WRAP                    0x4E242C
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_PCI_CTR_CNT                     0x4E2430
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM_CTR_SET_EN                  0x4E2434
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM_CTR_SET                     0x4E2438
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_SEL_0                           0x4E2450
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_SEL_1                           0x4E2454
+
+#define mmDMA_IF_E_N_DOWN_CH1_NON_LIN_EN                             0x4E2480
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_BANK_0                         0x4E2500
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_BANK_1                         0x4E2504
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_BANK_2                         0x4E2508
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_BANK_3                         0x4E250C
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_BANK_4                         0x4E2510
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_0                       0x4E2514
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_1                       0x4E2520
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_2                       0x4E2524
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_3                       0x4E2528
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_4                       0x4E252C
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_5                       0x4E2530
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_6                       0x4E2534
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_7                       0x4E2538
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_8                       0x4E253C
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_9                       0x4E2540
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_0                        0x4E2550
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_1                        0x4E2554
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_2                        0x4E2558
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_3                        0x4E255C
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_4                        0x4E2560
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_5                        0x4E2564
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_6                        0x4E2568
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_7                        0x4E256C
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_8                        0x4E2570
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_9                        0x4E2574
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_10                       0x4E2578
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_11                       0x4E257C
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_12                       0x4E2580
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_13                       0x4E2584
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_14                       0x4E2588
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_15                       0x4E258C
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_16                       0x4E2590
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_17                       0x4E2594
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_18                       0x4E2598
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0                0x4E25E4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_1                0x4E25E8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_2                0x4E25EC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_3                0x4E25F0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_4                0x4E25F4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_5                0x4E25F8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_6                0x4E25FC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_7                0x4E2600
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_8                0x4E2604
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_9                0x4E2608
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_10               0x4E260C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_11               0x4E2610
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_12               0x4E2614
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_13               0x4E2618
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_14               0x4E261C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_15               0x4E2620
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0               0x4E2624
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_1               0x4E2628
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_2               0x4E262C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_3               0x4E2630
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_4               0x4E2634
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_5               0x4E2638
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_6               0x4E263C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_7               0x4E2640
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_8               0x4E2644
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_9               0x4E2648
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_10              0x4E264C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_11              0x4E2650
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_12              0x4E2654
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_13              0x4E2658
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_14              0x4E265C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_15              0x4E2660
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0                0x4E2664
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_1                0x4E2668
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_2                0x4E266C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_3                0x4E2670
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_4                0x4E2674
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_5                0x4E2678
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_6                0x4E267C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_7                0x4E2680
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_8                0x4E2684
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_9                0x4E2688
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_10               0x4E268C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_11               0x4E2690
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_12               0x4E2694
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_13               0x4E2698
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_14               0x4E269C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_15               0x4E26A0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0               0x4E26A4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_1               0x4E26A8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_2               0x4E26AC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_3               0x4E26B0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_4               0x4E26B4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_5               0x4E26B8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_6               0x4E26BC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_7               0x4E26C0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_8               0x4E26C4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_9               0x4E26C8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_10              0x4E26CC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_11              0x4E26D0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_12              0x4E26D4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_13              0x4E26D8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_14              0x4E26DC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_15              0x4E26E0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_0               0x4E26E4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_1               0x4E26E8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_2               0x4E26EC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_3               0x4E26F0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_4               0x4E26F4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_5               0x4E26F8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_6               0x4E26FC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_7               0x4E2700
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_8               0x4E2704
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_9               0x4E2708
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_10              0x4E270C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_11              0x4E2710
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_12              0x4E2714
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_13              0x4E2718
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_14              0x4E271C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_15              0x4E2720
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_0              0x4E2724
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_1              0x4E2728
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_2              0x4E272C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_3              0x4E2730
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_4              0x4E2734
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_5              0x4E2738
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_6              0x4E273C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_7              0x4E2740
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_8              0x4E2744
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_9              0x4E2748
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_10             0x4E274C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_11             0x4E2750
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_12             0x4E2754
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_13             0x4E2758
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_14             0x4E275C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_15             0x4E2760
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_0               0x4E2764
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_1               0x4E2768
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_2               0x4E276C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_3               0x4E2770
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_4               0x4E2774
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_5               0x4E2778
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_6               0x4E277C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_7               0x4E2780
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_8               0x4E2784
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_9               0x4E2788
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_10              0x4E278C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_11              0x4E2790
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_12              0x4E2794
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_13              0x4E2798
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_14              0x4E279C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_15              0x4E27A0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_0              0x4E27A4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_1              0x4E27A8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_2              0x4E27AC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_3              0x4E27B0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_4              0x4E27B4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_5              0x4E27B8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_6              0x4E27BC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_7              0x4E27C0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_8              0x4E27C4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_9              0x4E27C8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_10             0x4E27CC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_11             0x4E27D0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_12             0x4E27D4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_13             0x4E27D8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_14             0x4E27DC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_15             0x4E27E0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0                0x4E2824
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_1                0x4E2828
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_2                0x4E282C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_3                0x4E2830
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_4                0x4E2834
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_5                0x4E2838
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_6                0x4E283C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_7                0x4E2840
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_8                0x4E2844
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_9                0x4E2848
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_10               0x4E284C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_11               0x4E2850
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_12               0x4E2854
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_13               0x4E2858
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_14               0x4E285C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_15               0x4E2860
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0               0x4E2864
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_1               0x4E2868
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_2               0x4E286C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_3               0x4E2870
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_4               0x4E2874
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_5               0x4E2878
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_6               0x4E287C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_7               0x4E2880
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_8               0x4E2884
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_9               0x4E2888
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_10              0x4E288C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_11              0x4E2890
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_12              0x4E2894
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_13              0x4E2898
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_14              0x4E289C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_15              0x4E28A0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0                0x4E28A4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_1                0x4E28A8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_2                0x4E28AC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_3                0x4E28B0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_4                0x4E28B4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_5                0x4E28B8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_6                0x4E28BC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_7                0x4E28C0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_8                0x4E28C4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_9                0x4E28C8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_10               0x4E28CC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_11               0x4E28D0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_12               0x4E28D4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_13               0x4E28D8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_14               0x4E28DC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_15               0x4E28E0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0               0x4E28E4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_1               0x4E28E8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_2               0x4E28EC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_3               0x4E28F0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_4               0x4E28F4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_5               0x4E28F8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_6               0x4E28FC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_7               0x4E2900
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_8               0x4E2904
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_9               0x4E2908
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_10              0x4E290C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_11              0x4E2910
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_12              0x4E2914
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_13              0x4E2918
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_14              0x4E291C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_15              0x4E2920
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_0               0x4E2924
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_1               0x4E2928
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_2               0x4E292C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_3               0x4E2930
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_4               0x4E2934
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_5               0x4E2938
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_6               0x4E293C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_7               0x4E2940
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_8               0x4E2944
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_9               0x4E2948
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_10              0x4E294C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_11              0x4E2950
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_12              0x4E2954
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_13              0x4E2958
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_14              0x4E295C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_15              0x4E2960
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_0              0x4E2964
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_1              0x4E2968
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_2              0x4E296C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_3              0x4E2970
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_4              0x4E2974
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_5              0x4E2978
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_6              0x4E297C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_7              0x4E2980
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_8              0x4E2984
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_9              0x4E2988
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_10             0x4E298C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_11             0x4E2990
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_12             0x4E2994
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_13             0x4E2998
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_14             0x4E299C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_15             0x4E29A0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_0               0x4E29A4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_1               0x4E29A8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_2               0x4E29AC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_3               0x4E29B0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_4               0x4E29B4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_5               0x4E29B8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_6               0x4E29BC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_7               0x4E29C0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_8               0x4E29C4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_9               0x4E29C8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_10              0x4E29CC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_11              0x4E29D0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_12              0x4E29D4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_13              0x4E29D8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_14              0x4E29DC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_15              0x4E29E0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_0              0x4E29E4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_1              0x4E29E8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_2              0x4E29EC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_3              0x4E29F0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_4              0x4E29F4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_5              0x4E29F8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_6              0x4E29FC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_7              0x4E2A00
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_8              0x4E2A04
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_9              0x4E2A08
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_10             0x4E2A0C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_11             0x4E2A10
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_12             0x4E2A14
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_13             0x4E2A18
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_14             0x4E2A1C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_15             0x4E2A20
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_HIT_AW                       0x4E2A64
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_HIT_AR                       0x4E2A68
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_HIT_AW                      0x4E2A6C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_HIT_AR                      0x4E2A70
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_CFG                                0x4E2B64
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_SHIFT                              0x4E2B68
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_0                     0x4E2B6C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_1                     0x4E2B70
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_2                     0x4E2B74
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_3                     0x4E2B78
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_4                     0x4E2B7C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_5                     0x4E2B80
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_6                     0x4E2B84
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_7                     0x4E2B88
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_0                            0x4E2BAC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_1                            0x4E2BB0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_2                            0x4E2BB4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_3                            0x4E2BB8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_4                            0x4E2BBC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_5                            0x4E2BC0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_6                            0x4E2BC4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_7                            0x4E2BC8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_0                          0x4E2BEC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_1                          0x4E2BF0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_2                          0x4E2BF4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_3                          0x4E2BF8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_4                          0x4E2BFC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_5                          0x4E2C00
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_6                          0x4E2C04
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_7                          0x4E2C08
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_WDT                                0x4E2C2C
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_WRAP               0x4E2C30
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_WRAP               0x4E2C34
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_WRAP               0x4E2C38
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_WRAP               0x4E2C3C
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_WRAP               0x4E2C40
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_WRAP               0x4E2C44
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_WRAP               0x4E2C48
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_WRAP               0x4E2C4C
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_CNT                0x4E2C50
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_CNT                0x4E2C54
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_CNT                0x4E2C58
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_CNT                0x4E2C5C
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_CNT                0x4E2C60
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_CNT                0x4E2C64
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_CNT                0x4E2C68
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_CNT                0x4E2C6C
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_WRAP               0x4E2C70
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_WRAP               0x4E2C74
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_WRAP               0x4E2C78
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_WRAP               0x4E2C7C
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_WRAP               0x4E2C80
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_WRAP               0x4E2C84
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_WRAP               0x4E2C88
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_WRAP               0x4E2C8C
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_CNT                0x4E2C90
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_CNT                0x4E2C94
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_CNT                0x4E2C98
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_CNT                0x4E2C9C
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_CNT                0x4E2CA0
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_CNT                0x4E2CA4
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_CNT                0x4E2CA8
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_CNT                0x4E2CAC
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_PC_SEL_0                        0x4E2CB0
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_PC_SEL_1                        0x4E2CB4
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_PC_SEL_2                        0x4E2CB8
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_PC_SEL_3                        0x4E2CBC
+
+#endif /* ASIC_REG_DMA_IF_E_N_DOWN_CH1_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_n_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_n_regs.h
new file mode 100644
index 000000000000..8a10c6a76156
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_n_regs.h
@@ -0,0 +1,860 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DMA_IF_E_N_REGS_H_
+#define ASIC_REG_DMA_IF_E_N_REGS_H_
+
+/*
+ *****************************************
+ *   DMA_IF_E_N (Prototype: DMA_IF)
+ *****************************************
+ */
+
+#define mmDMA_IF_E_N_HBM0_WR_CRED_CNT                                0x4E0000
+
+#define mmDMA_IF_E_N_HBM1_WR_CRED_CNT                                0x4E0004
+
+#define mmDMA_IF_E_N_HBM0_RD_CRED_CNT                                0x4E0008
+
+#define mmDMA_IF_E_N_HBM1_RD_CRED_CNT                                0x4E000C
+
+#define mmDMA_IF_E_N_HBM_LIMITER_0                                   0x4E0030
+
+#define mmDMA_IF_E_N_HBM_LIMITER_1                                   0x4E0034
+
+#define mmDMA_IF_E_N_HBM_LIMITER_2                                   0x4E0038
+
+#define mmDMA_IF_E_N_HBM_LIMITER_3                                   0x4E003C
+
+#define mmDMA_IF_E_N_HBM_ALMOST_EN_0                                 0x4E0040
+
+#define mmDMA_IF_E_N_HBM_ALMOST_EN_1                                 0x4E0044
+
+#define mmDMA_IF_E_N_HBM_CRED_EN_0                                   0x4E0050
+
+#define mmDMA_IF_E_N_HBM_CRED_EN_1                                   0x4E0054
+
+#define mmDMA_IF_E_N_SOB_MIN_RPROT_0                                 0x4E0100
+
+#define mmDMA_IF_E_N_SOB_MIN_RPROT_1                                 0x4E0104
+
+#define mmDMA_IF_E_N_SOB_MIN_RPROT_2                                 0x4E0108
+
+#define mmDMA_IF_E_N_SOB_MIN_RPROT_3                                 0x4E010C
+
+#define mmDMA_IF_E_N_SOB_MIN_RPROT_4                                 0x4E0110
+
+#define mmDMA_IF_E_N_SOB_MIN_RPROT_5                                 0x4E0114
+
+#define mmDMA_IF_E_N_SOB_MIN_RPROT_6                                 0x4E0118
+
+#define mmDMA_IF_E_N_SOB_MIN_RPROT_7                                 0x4E011C
+
+#define mmDMA_IF_E_N_SOB_MIN_RPROT_8                                 0x4E0120
+
+#define mmDMA_IF_E_N_SOB_MIN_RPROT_9                                 0x4E0124
+
+#define mmDMA_IF_E_N_SOB_MIN_RPROT_10                                0x4E0128
+
+#define mmDMA_IF_E_N_SOB_MIN_RPROT_11                                0x4E012C
+
+#define mmDMA_IF_E_N_SOB_MIN_RPROT_12                                0x4E0130
+
+#define mmDMA_IF_E_N_SOB_MIN_RPROT_13                                0x4E0134
+
+#define mmDMA_IF_E_N_SOB_MIN_RPROT_14                                0x4E0138
+
+#define mmDMA_IF_E_N_SOB_MIN_RPROT_15                                0x4E013C
+
+#define mmDMA_IF_E_N_SOB_MAX_RPROT_0                                 0x4E0140
+
+#define mmDMA_IF_E_N_SOB_MAX_RPROT_1                                 0x4E0144
+
+#define mmDMA_IF_E_N_SOB_MAX_RPROT_2                                 0x4E0148
+
+#define mmDMA_IF_E_N_SOB_MAX_RPROT_3                                 0x4E014C
+
+#define mmDMA_IF_E_N_SOB_MAX_RPROT_4                                 0x4E0150
+
+#define mmDMA_IF_E_N_SOB_MAX_RPROT_5                                 0x4E0154
+
+#define mmDMA_IF_E_N_SOB_MAX_RPROT_6                                 0x4E0158
+
+#define mmDMA_IF_E_N_SOB_MAX_RPROT_7                                 0x4E015C
+
+#define mmDMA_IF_E_N_SOB_MAX_RPROT_8                                 0x4E0160
+
+#define mmDMA_IF_E_N_SOB_MAX_RPROT_9                                 0x4E0164
+
+#define mmDMA_IF_E_N_SOB_MAX_RPROT_10                                0x4E0168
+
+#define mmDMA_IF_E_N_SOB_MAX_RPROT_11                                0x4E016C
+
+#define mmDMA_IF_E_N_SOB_MAX_RPROT_12                                0x4E0170
+
+#define mmDMA_IF_E_N_SOB_MAX_RPROT_13                                0x4E0174
+
+#define mmDMA_IF_E_N_SOB_MAX_RPROT_14                                0x4E0178
+
+#define mmDMA_IF_E_N_SOB_MAX_RPROT_15                                0x4E017C
+
+#define mmDMA_IF_E_N_SOB_MIN_WPROT_0                                 0x4E0180
+
+#define mmDMA_IF_E_N_SOB_MIN_WPROT_1                                 0x4E0184
+
+#define mmDMA_IF_E_N_SOB_MIN_WPROT_2                                 0x4E0188
+
+#define mmDMA_IF_E_N_SOB_MIN_WPROT_3                                 0x4E018C
+
+#define mmDMA_IF_E_N_SOB_MIN_WPROT_4                                 0x4E0190
+
+#define mmDMA_IF_E_N_SOB_MIN_WPROT_5                                 0x4E0194
+
+#define mmDMA_IF_E_N_SOB_MIN_WPROT_6                                 0x4E0198
+
+#define mmDMA_IF_E_N_SOB_MIN_WPROT_7                                 0x4E019C
+
+#define mmDMA_IF_E_N_SOB_MIN_WPROT_8                                 0x4E01A0
+
+#define mmDMA_IF_E_N_SOB_MIN_WPROT_9                                 0x4E01A4
+
+#define mmDMA_IF_E_N_SOB_MIN_WPROT_10                                0x4E01A8
+
+#define mmDMA_IF_E_N_SOB_MIN_WPROT_11                                0x4E01AC
+
+#define mmDMA_IF_E_N_SOB_MIN_WPROT_12                                0x4E01B0
+
+#define mmDMA_IF_E_N_SOB_MIN_WPROT_13                                0x4E01B4
+
+#define mmDMA_IF_E_N_SOB_MIN_WPROT_14                                0x4E01B8
+
+#define mmDMA_IF_E_N_SOB_MIN_WPROT_15                                0x4E01BC
+
+#define mmDMA_IF_E_N_SOB_MAX_WPROT_0                                 0x4E01C0
+
+#define mmDMA_IF_E_N_SOB_MAX_WPROT_1                                 0x4E01C4
+
+#define mmDMA_IF_E_N_SOB_MAX_WPROT_2                                 0x4E01C8
+
+#define mmDMA_IF_E_N_SOB_MAX_WPROT_3                                 0x4E01CC
+
+#define mmDMA_IF_E_N_SOB_MAX_WPROT_4                                 0x4E01D0
+
+#define mmDMA_IF_E_N_SOB_MAX_WPROT_5                                 0x4E01D4
+
+#define mmDMA_IF_E_N_SOB_MAX_WPROT_6                                 0x4E01D8
+
+#define mmDMA_IF_E_N_SOB_MAX_WPROT_7                                 0x4E01DC
+
+#define mmDMA_IF_E_N_SOB_MAX_WPROT_8                                 0x4E01E0
+
+#define mmDMA_IF_E_N_SOB_MAX_WPROT_9                                 0x4E01E4
+
+#define mmDMA_IF_E_N_SOB_MAX_WPROT_10                                0x4E01E8
+
+#define mmDMA_IF_E_N_SOB_MAX_WPROT_11                                0x4E01EC
+
+#define mmDMA_IF_E_N_SOB_MAX_WPROT_12                                0x4E01F0
+
+#define mmDMA_IF_E_N_SOB_MAX_WPROT_13                                0x4E01F4
+
+#define mmDMA_IF_E_N_SOB_MAX_WPROT_14                                0x4E01F8
+
+#define mmDMA_IF_E_N_SOB_MAX_WPROT_15                                0x4E01FC
+
+#define mmDMA_IF_E_N_SOB_MIN_RPRIV_0                                 0x4E0200
+
+#define mmDMA_IF_E_N_SOB_MIN_RPRIV_1                                 0x4E0204
+
+#define mmDMA_IF_E_N_SOB_MIN_RPRIV_2                                 0x4E0208
+
+#define mmDMA_IF_E_N_SOB_MIN_RPRIV_3                                 0x4E020C
+
+#define mmDMA_IF_E_N_SOB_MIN_RPRIV_4                                 0x4E0210
+
+#define mmDMA_IF_E_N_SOB_MIN_RPRIV_5                                 0x4E0214
+
+#define mmDMA_IF_E_N_SOB_MIN_RPRIV_6                                 0x4E0218
+
+#define mmDMA_IF_E_N_SOB_MIN_RPRIV_7                                 0x4E021C
+
+#define mmDMA_IF_E_N_SOB_MIN_RPRIV_8                                 0x4E0220
+
+#define mmDMA_IF_E_N_SOB_MIN_RPRIV_9                                 0x4E0224
+
+#define mmDMA_IF_E_N_SOB_MIN_RPRIV_10                                0x4E0228
+
+#define mmDMA_IF_E_N_SOB_MIN_RPRIV_11                                0x4E022C
+
+#define mmDMA_IF_E_N_SOB_MIN_RPRIV_12                                0x4E0230
+
+#define mmDMA_IF_E_N_SOB_MIN_RPRIV_13                                0x4E0234
+
+#define mmDMA_IF_E_N_SOB_MIN_RPRIV_14                                0x4E0238
+
+#define mmDMA_IF_E_N_SOB_MIN_RPRIV_15                                0x4E023C
+
+#define mmDMA_IF_E_N_SOB_MAX_RPRIV_0                                 0x4E0240
+
+#define mmDMA_IF_E_N_SOB_MAX_RPRIV_1                                 0x4E0244
+
+#define mmDMA_IF_E_N_SOB_MAX_RPRIV_2                                 0x4E0248
+
+#define mmDMA_IF_E_N_SOB_MAX_RPRIV_3                                 0x4E024C
+
+#define mmDMA_IF_E_N_SOB_MAX_RPRIV_4                                 0x4E0250
+
+#define mmDMA_IF_E_N_SOB_MAX_RPRIV_5                                 0x4E0254
+
+#define mmDMA_IF_E_N_SOB_MAX_RPRIV_6                                 0x4E0258
+
+#define mmDMA_IF_E_N_SOB_MAX_RPRIV_7                                 0x4E025C
+
+#define mmDMA_IF_E_N_SOB_MAX_RPRIV_8                                 0x4E0260
+
+#define mmDMA_IF_E_N_SOB_MAX_RPRIV_9                                 0x4E0264
+
+#define mmDMA_IF_E_N_SOB_MAX_RPRIV_10                                0x4E0268
+
+#define mmDMA_IF_E_N_SOB_MAX_RPRIV_11                                0x4E026C
+
+#define mmDMA_IF_E_N_SOB_MAX_RPRIV_12                                0x4E0270
+
+#define mmDMA_IF_E_N_SOB_MAX_RPRIV_13                                0x4E0274
+
+#define mmDMA_IF_E_N_SOB_MAX_RPRIV_14                                0x4E0278
+
+#define mmDMA_IF_E_N_SOB_MAX_RPRIV_15                                0x4E027C
+
+#define mmDMA_IF_E_N_SOB_MIN_WPRIV_0                                 0x4E0280
+
+#define mmDMA_IF_E_N_SOB_MIN_WPRIV_1                                 0x4E0284
+
+#define mmDMA_IF_E_N_SOB_MIN_WPRIV_2                                 0x4E0288
+
+#define mmDMA_IF_E_N_SOB_MIN_WPRIV_3                                 0x4E028C
+
+#define mmDMA_IF_E_N_SOB_MIN_WPRIV_4                                 0x4E0290
+
+#define mmDMA_IF_E_N_SOB_MIN_WPRIV_5                                 0x4E0294
+
+#define mmDMA_IF_E_N_SOB_MIN_WPRIV_6                                 0x4E0298
+
+#define mmDMA_IF_E_N_SOB_MIN_WPRIV_7                                 0x4E029C
+
+#define mmDMA_IF_E_N_SOB_MIN_WPRIV_8                                 0x4E02A0
+
+#define mmDMA_IF_E_N_SOB_MIN_WPRIV_9                                 0x4E02A4
+
+#define mmDMA_IF_E_N_SOB_MIN_WPRIV_10                                0x4E02A8
+
+#define mmDMA_IF_E_N_SOB_MIN_WPRIV_11                                0x4E02AC
+
+#define mmDMA_IF_E_N_SOB_MIN_WPRIV_12                                0x4E02B0
+
+#define mmDMA_IF_E_N_SOB_MIN_WPRIV_13                                0x4E02B4
+
+#define mmDMA_IF_E_N_SOB_MIN_WPRIV_14                                0x4E02B8
+
+#define mmDMA_IF_E_N_SOB_MIN_WPRIV_15                                0x4E02BC
+
+#define mmDMA_IF_E_N_SOB_MAX_WPRIV_0                                 0x4E02C0
+
+#define mmDMA_IF_E_N_SOB_MAX_WPRIV_1                                 0x4E02C4
+
+#define mmDMA_IF_E_N_SOB_MAX_WPRIV_2                                 0x4E02C8
+
+#define mmDMA_IF_E_N_SOB_MAX_WPRIV_3                                 0x4E02CC
+
+#define mmDMA_IF_E_N_SOB_MAX_WPRIV_4                                 0x4E02D0
+
+#define mmDMA_IF_E_N_SOB_MAX_WPRIV_5                                 0x4E02D4
+
+#define mmDMA_IF_E_N_SOB_MAX_WPRIV_6                                 0x4E02D8
+
+#define mmDMA_IF_E_N_SOB_MAX_WPRIV_7                                 0x4E02DC
+
+#define mmDMA_IF_E_N_SOB_MAX_WPRIV_8                                 0x4E02E0
+
+#define mmDMA_IF_E_N_SOB_MAX_WPRIV_9                                 0x4E02E4
+
+#define mmDMA_IF_E_N_SOB_MAX_WPRIV_10                                0x4E02E8
+
+#define mmDMA_IF_E_N_SOB_MAX_WPRIV_11                                0x4E02EC
+
+#define mmDMA_IF_E_N_SOB_MAX_WPRIV_12                                0x4E02F0
+
+#define mmDMA_IF_E_N_SOB_MAX_WPRIV_13                                0x4E02F4
+
+#define mmDMA_IF_E_N_SOB_MAX_WPRIV_14                                0x4E02F8
+
+#define mmDMA_IF_E_N_SOB_MAX_WPRIV_15                                0x4E02FC
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPROT_0                                0x4E0300
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPROT_1                                0x4E0304
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPROT_2                                0x4E0308
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPROT_3                                0x4E030C
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPROT_4                                0x4E0310
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPROT_5                                0x4E0314
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPROT_6                                0x4E0318
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPROT_7                                0x4E031C
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPROT_8                                0x4E0320
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPROT_9                                0x4E0324
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPROT_10                               0x4E0328
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPROT_11                               0x4E032C
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPROT_12                               0x4E0330
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPROT_13                               0x4E0334
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPROT_14                               0x4E0338
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPROT_15                               0x4E033C
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPROT_0                                0x4E0340
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPROT_1                                0x4E0344
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPROT_2                                0x4E0348
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPROT_3                                0x4E034C
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPROT_4                                0x4E0350
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPROT_5                                0x4E0354
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPROT_6                                0x4E0358
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPROT_7                                0x4E035C
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPROT_8                                0x4E0360
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPROT_9                                0x4E0364
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPROT_10                               0x4E0368
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPROT_11                               0x4E036C
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPROT_12                               0x4E0370
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPROT_13                               0x4E0374
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPROT_14                               0x4E0378
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPROT_15                               0x4E037C
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPROT_0                                0x4E0380
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPROT_1                                0x4E0384
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPROT_2                                0x4E0388
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPROT_3                                0x4E038C
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPROT_4                                0x4E0390
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPROT_5                                0x4E0394
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPROT_6                                0x4E0398
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPROT_7                                0x4E039C
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPROT_8                                0x4E03A0
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPROT_9                                0x4E03A4
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPROT_10                               0x4E03A8
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPROT_11                               0x4E03AC
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPROT_12                               0x4E03B0
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPROT_13                               0x4E03B4
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPROT_14                               0x4E03B8
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPROT_15                               0x4E03BC
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPROT_0                                0x4E03C0
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPROT_1                                0x4E03C4
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPROT_2                                0x4E03C8
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPROT_3                                0x4E03CC
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPROT_4                                0x4E03D0
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPROT_5                                0x4E03D4
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPROT_6                                0x4E03D8
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPROT_7                                0x4E03DC
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPROT_8                                0x4E03E0
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPROT_9                                0x4E03E4
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPROT_10                               0x4E03E8
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPROT_11                               0x4E03EC
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPROT_12                               0x4E03F0
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPROT_13                               0x4E03F4
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPROT_14                               0x4E03F8
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPROT_15                               0x4E03FC
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_0                                0x4E0400
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_1                                0x4E0404
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_2                                0x4E0408
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_3                                0x4E040C
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_4                                0x4E0410
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_5                                0x4E0414
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_6                                0x4E0418
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_7                                0x4E041C
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_8                                0x4E0420
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_9                                0x4E0424
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_10                               0x4E0428
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_11                               0x4E042C
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_12                               0x4E0430
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_13                               0x4E0434
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_14                               0x4E0438
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_15                               0x4E043C
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_0                                0x4E0440
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_1                                0x4E0444
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_2                                0x4E0448
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_3                                0x4E044C
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_4                                0x4E0450
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_5                                0x4E0454
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_6                                0x4E0458
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_7                                0x4E045C
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_8                                0x4E0460
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_9                                0x4E0464
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_10                               0x4E0468
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_11                               0x4E046C
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_12                               0x4E0470
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_13                               0x4E0474
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_14                               0x4E0478
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_15                               0x4E047C
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_0                                0x4E0480
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_1                                0x4E0484
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_2                                0x4E0488
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_3                                0x4E048C
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_4                                0x4E0490
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_5                                0x4E0494
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_6                                0x4E0498
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_7                                0x4E049C
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_8                                0x4E04A0
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_9                                0x4E04A4
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_10                               0x4E04A8
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_11                               0x4E04AC
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_12                               0x4E04B0
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_13                               0x4E04B4
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_14                               0x4E04B8
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_15                               0x4E04BC
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_0                                0x4E04C0
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_1                                0x4E04C4
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_2                                0x4E04C8
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_3                                0x4E04CC
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_4                                0x4E04D0
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_5                                0x4E04D4
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_6                                0x4E04D8
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_7                                0x4E04DC
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_8                                0x4E04E0
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_9                                0x4E04E4
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_10                               0x4E04E8
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_11                               0x4E04EC
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_12                               0x4E04F0
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_13                               0x4E04F4
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_14                               0x4E04F8
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_15                               0x4E04FC
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPROT_0                                0x4E0500
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPROT_1                                0x4E0504
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPROT_2                                0x4E0508
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPROT_3                                0x4E050C
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPROT_4                                0x4E0510
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPROT_5                                0x4E0514
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPROT_6                                0x4E0518
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPROT_7                                0x4E051C
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPROT_8                                0x4E0520
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPROT_9                                0x4E0524
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPROT_10                               0x4E0528
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPROT_11                               0x4E052C
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPROT_12                               0x4E0530
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPROT_13                               0x4E0534
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPROT_14                               0x4E0538
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPROT_15                               0x4E053C
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPROT_0                                0x4E0540
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPROT_1                                0x4E0544
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPROT_2                                0x4E0548
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPROT_3                                0x4E054C
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPROT_4                                0x4E0550
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPROT_5                                0x4E0554
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPROT_6                                0x4E0558
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPROT_7                                0x4E055C
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPROT_8                                0x4E0560
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPROT_9                                0x4E0564
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPROT_10                               0x4E0568
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPROT_11                               0x4E056C
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPROT_12                               0x4E0570
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPROT_13                               0x4E0574
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPROT_14                               0x4E0578
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPROT_15                               0x4E057C
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPROT_0                                0x4E0580
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPROT_1                                0x4E0584
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPROT_2                                0x4E0588
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPROT_3                                0x4E058C
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPROT_4                                0x4E0590
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPROT_5                                0x4E0594
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPROT_6                                0x4E0598
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPROT_7                                0x4E059C
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPROT_8                                0x4E05A0
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPROT_9                                0x4E05A4
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPROT_10                               0x4E05A8
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPROT_11                               0x4E05AC
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPROT_12                               0x4E05B0
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPROT_13                               0x4E05B4
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPROT_14                               0x4E05B8
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPROT_15                               0x4E05BC
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPROT_0                                0x4E05C0
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPROT_1                                0x4E05C4
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPROT_2                                0x4E05C8
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPROT_3                                0x4E05CC
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPROT_4                                0x4E05D0
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPROT_5                                0x4E05D4
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPROT_6                                0x4E05D8
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPROT_7                                0x4E05DC
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPROT_8                                0x4E05E0
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPROT_9                                0x4E05E4
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPROT_10                               0x4E05E8
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPROT_11                               0x4E05EC
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPROT_12                               0x4E05F0
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPROT_13                               0x4E05F4
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPROT_14                               0x4E05F8
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPROT_15                               0x4E05FC
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_0                                0x4E0600
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_1                                0x4E0604
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_2                                0x4E0608
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_3                                0x4E060C
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_4                                0x4E0610
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_5                                0x4E0614
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_6                                0x4E0618
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_7                                0x4E061C
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_8                                0x4E0620
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_9                                0x4E0624
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_10                               0x4E0628
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_11                               0x4E062C
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_12                               0x4E0630
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_13                               0x4E0634
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_14                               0x4E0638
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_15                               0x4E063C
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_0                                0x4E0640
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_1                                0x4E0644
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_2                                0x4E0648
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_3                                0x4E064C
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_4                                0x4E0650
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_5                                0x4E0654
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_6                                0x4E0658
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_7                                0x4E065C
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_8                                0x4E0660
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_9                                0x4E0664
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_10                               0x4E0668
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_11                               0x4E066C
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_12                               0x4E0670
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_13                               0x4E0674
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_14                               0x4E0678
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_15                               0x4E067C
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_0                                0x4E0680
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_1                                0x4E0684
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_2                                0x4E0688
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_3                                0x4E068C
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_4                                0x4E0690
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_5                                0x4E0694
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_6                                0x4E0698
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_7                                0x4E069C
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_8                                0x4E06A0
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_9                                0x4E06A4
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_10                               0x4E06A8
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_11                               0x4E06AC
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_12                               0x4E06B0
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_13                               0x4E06B4
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_14                               0x4E06B8
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_15                               0x4E06BC
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_0                                0x4E06C0
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_1                                0x4E06C4
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_2                                0x4E06C8
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_3                                0x4E06CC
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_4                                0x4E06D0
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_5                                0x4E06D4
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_6                                0x4E06D8
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_7                                0x4E06DC
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_8                                0x4E06E0
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_9                                0x4E06E4
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_10                               0x4E06E8
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_11                               0x4E06EC
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_12                               0x4E06F0
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_13                               0x4E06F4
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_14                               0x4E06F8
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_15                               0x4E06FC
+
+#define mmDMA_IF_E_N_SOB_HIT_RPROT                                   0x4E0700
+
+#define mmDMA_IF_E_N_SOB_HIT_WPROT                                   0x4E0704
+
+#define mmDMA_IF_E_N_SOB_HIT_RPRIV                                   0x4E070C
+
+#define mmDMA_IF_E_N_SOB_HIT_WPRIV                                   0x4E0710
+
+#define mmDMA_IF_E_N_DMA0_HIT_RPROT                                  0x4E071C
+
+#define mmDMA_IF_E_N_DMA0_HIT_WPROT                                  0x4E0720
+
+#define mmDMA_IF_E_N_DMA0_HIT_RPRIV                                  0x4E0724
+
+#define mmDMA_IF_E_N_DMA0_HIT_WPRIV                                  0x4E0728
+
+#define mmDMA_IF_E_N_DMA1_HIT_RPROT                                  0x4E0730
+
+#define mmDMA_IF_E_N_DMA1_HIT_WPROT                                  0x4E0734
+
+#define mmDMA_IF_E_N_DMA1_HIT_RPRIV                                  0x4E0738
+
+#define mmDMA_IF_E_N_DMA1_HIT_WPRIV                                  0x4E073C
+
+#define mmDMA_IF_E_N_HBM_BIN                                         0x4E0800
+
+#define mmDMA_IF_E_N_MME_BIN                                         0x4E0804
+
+#define mmDMA_IF_E_N_TPC_BIN                                         0x4E0808
+
+#define mmDMA_IF_E_N_DMA_BIN                                         0x4E080C
+
+#define mmDMA_IF_E_N_SOB_CG_EN                                       0x4E0810
+
+#define mmDMA_IF_E_N_HBM_I2C_ADDR_0                                  0x4E0820
+
+#define mmDMA_IF_E_N_HBM_I2C_ADDR_1                                  0x4E0824
+
+#define mmDMA_IF_E_N_HBM_I2C_ADDR_2                                  0x4E0828
+
+#define mmDMA_IF_E_N_HBM_I2C_ADDR_3                                  0x4E082C
+
+#define mmDMA_IF_E_N_HBM_I2C_ADDR_4                                  0x4E0830
+
+#define mmDMA_IF_E_N_HBM_MISC                                        0x4E0834
+
+#endif /* ASIC_REG_DMA_IF_E_N_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_s_down_ch0_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_s_down_ch0_regs.h
new file mode 100644
index 000000000000..cd61289a1e8a
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_s_down_ch0_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DMA_IF_E_S_DOWN_CH0_REGS_H_
+#define ASIC_REG_DMA_IF_E_S_DOWN_CH0_REGS_H_
+
+/*
+ *****************************************
+ *   DMA_IF_E_S_DOWN_CH0 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmDMA_IF_E_S_DOWN_CH0_PERM_SEL                               0x4A1108
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_0                          0x4A1114
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_1                          0x4A1118
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_2                          0x4A111C
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_3                          0x4A1120
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_4                          0x4A1124
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_5                          0x4A1128
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_6                          0x4A112C
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_7                          0x4A1130
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_8                          0x4A1134
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_9                          0x4A1138
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_10                         0x4A113C
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_11                         0x4A1140
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_12                         0x4A1144
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_13                         0x4A1148
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_14                         0x4A114C
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_15                         0x4A1150
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_16                         0x4A1154
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_17                         0x4A1158
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_18                         0x4A115C
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_19                         0x4A1160
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_20                         0x4A1164
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_21                         0x4A1168
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_22                         0x4A116C
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_23                         0x4A1170
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_24                         0x4A1174
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_25                         0x4A1178
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_26                         0x4A117C
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_27                         0x4A1180
+
+#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_0                         0x4A1184
+
+#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_1                         0x4A1188
+
+#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_2                         0x4A118C
+
+#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_3                         0x4A1190
+
+#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_4                         0x4A1194
+
+#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_5                         0x4A1198
+
+#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_6                         0x4A119C
+
+#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_7                         0x4A11A0
+
+#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_8                         0x4A11A4
+
+#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_9                         0x4A11A8
+
+#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_10                        0x4A11AC
+
+#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_11                        0x4A11B0
+
+#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_12                        0x4A11B4
+
+#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_13                        0x4A11B8
+
+#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_14                        0x4A11BC
+
+#define mmDMA_IF_E_S_DOWN_CH0_SCRAM_SRAM_EN                          0x4A126C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RL_HBM_EN                              0x4A1274
+
+#define mmDMA_IF_E_S_DOWN_CH0_RL_HBM_SAT                             0x4A1278
+
+#define mmDMA_IF_E_S_DOWN_CH0_RL_HBM_RST                             0x4A127C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RL_HBM_TIMEOUT                         0x4A1280
+
+#define mmDMA_IF_E_S_DOWN_CH0_SCRAM_HBM_EN                           0x4A1284
+
+#define mmDMA_IF_E_S_DOWN_CH0_RL_PCI_EN                              0x4A1288
+
+#define mmDMA_IF_E_S_DOWN_CH0_RL_PCI_SAT                             0x4A128C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RL_PCI_RST                             0x4A1290
+
+#define mmDMA_IF_E_S_DOWN_CH0_RL_PCI_TIMEOUT                         0x4A1294
+
+#define mmDMA_IF_E_S_DOWN_CH0_RL_SRAM_EN                             0x4A129C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RL_SRAM_SAT                            0x4A12A0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RL_SRAM_RST                            0x4A12A4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RL_SRAM_TIMEOUT                        0x4A12AC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RL_SRAM_RED                            0x4A12B4
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_HBM_EN                             0x4A12EC
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_PCI_EN                             0x4A12F0
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_HBM_WR_SIZE                        0x4A12F4
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_PCI_WR_SIZE                        0x4A12F8
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_PCI_CTR_SET_EN                  0x4A1404
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_PCI_CTR_SET                     0x4A1408
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_PCI_CTR_WRAP                    0x4A140C
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_PCI_CTR_CNT                     0x4A1410
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM_CTR_SET_EN                  0x4A1414
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM_CTR_SET                     0x4A1418
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_HBM_RD_SIZE                        0x4A141C
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_PCI_RD_SIZE                        0x4A1420
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_PCI_CTR_SET_EN                  0x4A1424
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_PCI_CTR_SET                     0x4A1428
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_PCI_CTR_WRAP                    0x4A142C
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_PCI_CTR_CNT                     0x4A1430
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM_CTR_SET_EN                  0x4A1434
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM_CTR_SET                     0x4A1438
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_SEL_0                           0x4A1450
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_SEL_1                           0x4A1454
+
+#define mmDMA_IF_E_S_DOWN_CH0_NON_LIN_EN                             0x4A1480
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_BANK_0                         0x4A1500
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_BANK_1                         0x4A1504
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_BANK_2                         0x4A1508
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_BANK_3                         0x4A150C
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_BANK_4                         0x4A1510
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_0                       0x4A1514
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_1                       0x4A1520
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_2                       0x4A1524
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_3                       0x4A1528
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_4                       0x4A152C
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_5                       0x4A1530
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_6                       0x4A1534
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_7                       0x4A1538
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_8                       0x4A153C
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_9                       0x4A1540
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_0                        0x4A1550
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_1                        0x4A1554
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_2                        0x4A1558
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_3                        0x4A155C
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_4                        0x4A1560
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_5                        0x4A1564
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_6                        0x4A1568
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_7                        0x4A156C
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_8                        0x4A1570
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_9                        0x4A1574
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_10                       0x4A1578
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_11                       0x4A157C
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_12                       0x4A1580
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_13                       0x4A1584
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_14                       0x4A1588
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_15                       0x4A158C
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_16                       0x4A1590
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_17                       0x4A1594
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_18                       0x4A1598
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_0                0x4A15E4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_1                0x4A15E8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_2                0x4A15EC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_3                0x4A15F0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_4                0x4A15F4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_5                0x4A15F8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_6                0x4A15FC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_7                0x4A1600
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_8                0x4A1604
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_9                0x4A1608
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_10               0x4A160C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_11               0x4A1610
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_12               0x4A1614
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_13               0x4A1618
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_14               0x4A161C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_15               0x4A1620
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_0               0x4A1624
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_1               0x4A1628
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_2               0x4A162C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_3               0x4A1630
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_4               0x4A1634
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_5               0x4A1638
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_6               0x4A163C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_7               0x4A1640
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_8               0x4A1644
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_9               0x4A1648
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_10              0x4A164C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_11              0x4A1650
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_12              0x4A1654
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_13              0x4A1658
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_14              0x4A165C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_15              0x4A1660
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_0                0x4A1664
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_1                0x4A1668
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_2                0x4A166C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_3                0x4A1670
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_4                0x4A1674
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_5                0x4A1678
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_6                0x4A167C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_7                0x4A1680
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_8                0x4A1684
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_9                0x4A1688
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_10               0x4A168C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_11               0x4A1690
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_12               0x4A1694
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_13               0x4A1698
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_14               0x4A169C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_15               0x4A16A0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_0               0x4A16A4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_1               0x4A16A8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_2               0x4A16AC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_3               0x4A16B0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_4               0x4A16B4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_5               0x4A16B8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_6               0x4A16BC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_7               0x4A16C0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_8               0x4A16C4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_9               0x4A16C8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_10              0x4A16CC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_11              0x4A16D0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_12              0x4A16D4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_13              0x4A16D8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_14              0x4A16DC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_15              0x4A16E0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_0               0x4A16E4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_1               0x4A16E8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_2               0x4A16EC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_3               0x4A16F0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_4               0x4A16F4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_5               0x4A16F8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_6               0x4A16FC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_7               0x4A1700
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_8               0x4A1704
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_9               0x4A1708
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_10              0x4A170C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_11              0x4A1710
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_12              0x4A1714
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_13              0x4A1718
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_14              0x4A171C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_15              0x4A1720
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_0              0x4A1724
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_1              0x4A1728
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_2              0x4A172C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_3              0x4A1730
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_4              0x4A1734
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_5              0x4A1738
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_6              0x4A173C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_7              0x4A1740
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_8              0x4A1744
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_9              0x4A1748
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_10             0x4A174C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_11             0x4A1750
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_12             0x4A1754
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_13             0x4A1758
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_14             0x4A175C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_15             0x4A1760
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_0               0x4A1764
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_1               0x4A1768
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_2               0x4A176C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_3               0x4A1770
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_4               0x4A1774
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_5               0x4A1778
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_6               0x4A177C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_7               0x4A1780
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_8               0x4A1784
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_9               0x4A1788
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_10              0x4A178C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_11              0x4A1790
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_12              0x4A1794
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_13              0x4A1798
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_14              0x4A179C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_15              0x4A17A0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_0              0x4A17A4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_1              0x4A17A8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_2              0x4A17AC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_3              0x4A17B0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_4              0x4A17B4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_5              0x4A17B8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_6              0x4A17BC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_7              0x4A17C0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_8              0x4A17C4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_9              0x4A17C8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_10             0x4A17CC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_11             0x4A17D0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_12             0x4A17D4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_13             0x4A17D8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_14             0x4A17DC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_15             0x4A17E0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_0                0x4A1824
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_1                0x4A1828
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_2                0x4A182C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_3                0x4A1830
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_4                0x4A1834
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_5                0x4A1838
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_6                0x4A183C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_7                0x4A1840
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_8                0x4A1844
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_9                0x4A1848
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_10               0x4A184C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_11               0x4A1850
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_12               0x4A1854
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_13               0x4A1858
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_14               0x4A185C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_15               0x4A1860
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_0               0x4A1864
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_1               0x4A1868
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_2               0x4A186C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_3               0x4A1870
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_4               0x4A1874
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_5               0x4A1878
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_6               0x4A187C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_7               0x4A1880
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_8               0x4A1884
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_9               0x4A1888
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_10              0x4A188C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_11              0x4A1890
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_12              0x4A1894
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_13              0x4A1898
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_14              0x4A189C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_15              0x4A18A0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_0                0x4A18A4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_1                0x4A18A8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_2                0x4A18AC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_3                0x4A18B0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_4                0x4A18B4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_5                0x4A18B8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_6                0x4A18BC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_7                0x4A18C0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_8                0x4A18C4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_9                0x4A18C8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_10               0x4A18CC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_11               0x4A18D0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_12               0x4A18D4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_13               0x4A18D8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_14               0x4A18DC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_15               0x4A18E0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_0               0x4A18E4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_1               0x4A18E8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_2               0x4A18EC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_3               0x4A18F0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_4               0x4A18F4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_5               0x4A18F8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_6               0x4A18FC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_7               0x4A1900
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_8               0x4A1904
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_9               0x4A1908
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_10              0x4A190C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_11              0x4A1910
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_12              0x4A1914
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_13              0x4A1918
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_14              0x4A191C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_15              0x4A1920
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_0               0x4A1924
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_1               0x4A1928
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_2               0x4A192C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_3               0x4A1930
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_4               0x4A1934
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_5               0x4A1938
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_6               0x4A193C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_7               0x4A1940
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_8               0x4A1944
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_9               0x4A1948
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_10              0x4A194C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_11              0x4A1950
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_12              0x4A1954
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_13              0x4A1958
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_14              0x4A195C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_15              0x4A1960
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_0              0x4A1964
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_1              0x4A1968
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_2              0x4A196C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_3              0x4A1970
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_4              0x4A1974
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_5              0x4A1978
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_6              0x4A197C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_7              0x4A1980
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_8              0x4A1984
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_9              0x4A1988
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_10             0x4A198C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_11             0x4A1990
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_12             0x4A1994
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_13             0x4A1998
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_14             0x4A199C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_15             0x4A19A0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_0               0x4A19A4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_1               0x4A19A8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_2               0x4A19AC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_3               0x4A19B0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_4               0x4A19B4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_5               0x4A19B8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_6               0x4A19BC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_7               0x4A19C0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_8               0x4A19C4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_9               0x4A19C8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_10              0x4A19CC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_11              0x4A19D0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_12              0x4A19D4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_13              0x4A19D8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_14              0x4A19DC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_15              0x4A19E0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_0              0x4A19E4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_1              0x4A19E8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_2              0x4A19EC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_3              0x4A19F0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_4              0x4A19F4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_5              0x4A19F8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_6              0x4A19FC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_7              0x4A1A00
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_8              0x4A1A04
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_9              0x4A1A08
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_10             0x4A1A0C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_11             0x4A1A10
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_12             0x4A1A14
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_13             0x4A1A18
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_14             0x4A1A1C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_15             0x4A1A20
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_HIT_AW                       0x4A1A64
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_HIT_AR                       0x4A1A68
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_HIT_AW                      0x4A1A6C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_HIT_AR                      0x4A1A70
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_CFG                                0x4A1B64
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_SHIFT                              0x4A1B68
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_0                     0x4A1B6C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_1                     0x4A1B70
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_2                     0x4A1B74
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_3                     0x4A1B78
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_4                     0x4A1B7C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_5                     0x4A1B80
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_6                     0x4A1B84
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_7                     0x4A1B88
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_0                            0x4A1BAC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_1                            0x4A1BB0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_2                            0x4A1BB4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_3                            0x4A1BB8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_4                            0x4A1BBC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_5                            0x4A1BC0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_6                            0x4A1BC4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_7                            0x4A1BC8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_0                          0x4A1BEC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_1                          0x4A1BF0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_2                          0x4A1BF4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_3                          0x4A1BF8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_4                          0x4A1BFC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_5                          0x4A1C00
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_6                          0x4A1C04
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_7                          0x4A1C08
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_WDT                                0x4A1C2C
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_WRAP               0x4A1C30
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_WRAP               0x4A1C34
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_WRAP               0x4A1C38
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_WRAP               0x4A1C3C
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_WRAP               0x4A1C40
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_WRAP               0x4A1C44
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_WRAP               0x4A1C48
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_WRAP               0x4A1C4C
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_CNT                0x4A1C50
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_CNT                0x4A1C54
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_CNT                0x4A1C58
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_CNT                0x4A1C5C
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_CNT                0x4A1C60
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_CNT                0x4A1C64
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_CNT                0x4A1C68
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_CNT                0x4A1C6C
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_WRAP               0x4A1C70
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_WRAP               0x4A1C74
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_WRAP               0x4A1C78
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_WRAP               0x4A1C7C
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_WRAP               0x4A1C80
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_WRAP               0x4A1C84
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_WRAP               0x4A1C88
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_WRAP               0x4A1C8C
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_CNT                0x4A1C90
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_CNT                0x4A1C94
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_CNT                0x4A1C98
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_CNT                0x4A1C9C
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_CNT                0x4A1CA0
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_CNT                0x4A1CA4
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_CNT                0x4A1CA8
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_CNT                0x4A1CAC
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_PC_SEL_0                        0x4A1CB0
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_PC_SEL_1                        0x4A1CB4
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_PC_SEL_2                        0x4A1CB8
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_PC_SEL_3                        0x4A1CBC
+
+#endif /* ASIC_REG_DMA_IF_E_S_DOWN_CH0_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_s_down_ch1_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_s_down_ch1_regs.h
new file mode 100644
index 000000000000..3f32370a14c7
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_s_down_ch1_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DMA_IF_E_S_DOWN_CH1_REGS_H_
+#define ASIC_REG_DMA_IF_E_S_DOWN_CH1_REGS_H_
+
+/*
+ *****************************************
+ *   DMA_IF_E_S_DOWN_CH1 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmDMA_IF_E_S_DOWN_CH1_PERM_SEL                               0x4A2108
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_0                          0x4A2114
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_1                          0x4A2118
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_2                          0x4A211C
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_3                          0x4A2120
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_4                          0x4A2124
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_5                          0x4A2128
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_6                          0x4A212C
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_7                          0x4A2130
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_8                          0x4A2134
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_9                          0x4A2138
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_10                         0x4A213C
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_11                         0x4A2140
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_12                         0x4A2144
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_13                         0x4A2148
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_14                         0x4A214C
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_15                         0x4A2150
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_16                         0x4A2154
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_17                         0x4A2158
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_18                         0x4A215C
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_19                         0x4A2160
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_20                         0x4A2164
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_21                         0x4A2168
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_22                         0x4A216C
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_23                         0x4A2170
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_24                         0x4A2174
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_25                         0x4A2178
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_26                         0x4A217C
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_27                         0x4A2180
+
+#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_0                         0x4A2184
+
+#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_1                         0x4A2188
+
+#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_2                         0x4A218C
+
+#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_3                         0x4A2190
+
+#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_4                         0x4A2194
+
+#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_5                         0x4A2198
+
+#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_6                         0x4A219C
+
+#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_7                         0x4A21A0
+
+#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_8                         0x4A21A4
+
+#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_9                         0x4A21A8
+
+#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_10                        0x4A21AC
+
+#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_11                        0x4A21B0
+
+#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_12                        0x4A21B4
+
+#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_13                        0x4A21B8
+
+#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_14                        0x4A21BC
+
+#define mmDMA_IF_E_S_DOWN_CH1_SCRAM_SRAM_EN                          0x4A226C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RL_HBM_EN                              0x4A2274
+
+#define mmDMA_IF_E_S_DOWN_CH1_RL_HBM_SAT                             0x4A2278
+
+#define mmDMA_IF_E_S_DOWN_CH1_RL_HBM_RST                             0x4A227C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RL_HBM_TIMEOUT                         0x4A2280
+
+#define mmDMA_IF_E_S_DOWN_CH1_SCRAM_HBM_EN                           0x4A2284
+
+#define mmDMA_IF_E_S_DOWN_CH1_RL_PCI_EN                              0x4A2288
+
+#define mmDMA_IF_E_S_DOWN_CH1_RL_PCI_SAT                             0x4A228C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RL_PCI_RST                             0x4A2290
+
+#define mmDMA_IF_E_S_DOWN_CH1_RL_PCI_TIMEOUT                         0x4A2294
+
+#define mmDMA_IF_E_S_DOWN_CH1_RL_SRAM_EN                             0x4A229C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RL_SRAM_SAT                            0x4A22A0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RL_SRAM_RST                            0x4A22A4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RL_SRAM_TIMEOUT                        0x4A22AC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RL_SRAM_RED                            0x4A22B4
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_HBM_EN                             0x4A22EC
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_PCI_EN                             0x4A22F0
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_HBM_WR_SIZE                        0x4A22F4
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_PCI_WR_SIZE                        0x4A22F8
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_PCI_CTR_SET_EN                  0x4A2404
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_PCI_CTR_SET                     0x4A2408
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_PCI_CTR_WRAP                    0x4A240C
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_PCI_CTR_CNT                     0x4A2410
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM_CTR_SET_EN                  0x4A2414
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM_CTR_SET                     0x4A2418
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_HBM_RD_SIZE                        0x4A241C
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_PCI_RD_SIZE                        0x4A2420
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_PCI_CTR_SET_EN                  0x4A2424
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_PCI_CTR_SET                     0x4A2428
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_PCI_CTR_WRAP                    0x4A242C
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_PCI_CTR_CNT                     0x4A2430
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM_CTR_SET_EN                  0x4A2434
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM_CTR_SET                     0x4A2438
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_SEL_0                           0x4A2450
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_SEL_1                           0x4A2454
+
+#define mmDMA_IF_E_S_DOWN_CH1_NON_LIN_EN                             0x4A2480
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_BANK_0                         0x4A2500
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_BANK_1                         0x4A2504
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_BANK_2                         0x4A2508
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_BANK_3                         0x4A250C
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_BANK_4                         0x4A2510
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_0                       0x4A2514
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_1                       0x4A2520
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_2                       0x4A2524
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_3                       0x4A2528
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_4                       0x4A252C
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_5                       0x4A2530
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_6                       0x4A2534
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_7                       0x4A2538
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_8                       0x4A253C
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_9                       0x4A2540
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_0                        0x4A2550
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_1                        0x4A2554
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_2                        0x4A2558
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_3                        0x4A255C
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_4                        0x4A2560
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_5                        0x4A2564
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_6                        0x4A2568
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_7                        0x4A256C
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_8                        0x4A2570
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_9                        0x4A2574
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_10                       0x4A2578
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_11                       0x4A257C
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_12                       0x4A2580
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_13                       0x4A2584
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_14                       0x4A2588
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_15                       0x4A258C
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_16                       0x4A2590
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_17                       0x4A2594
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_18                       0x4A2598
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0                0x4A25E4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_1                0x4A25E8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_2                0x4A25EC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_3                0x4A25F0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_4                0x4A25F4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_5                0x4A25F8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_6                0x4A25FC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_7                0x4A2600
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_8                0x4A2604
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_9                0x4A2608
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_10               0x4A260C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_11               0x4A2610
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_12               0x4A2614
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_13               0x4A2618
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_14               0x4A261C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_15               0x4A2620
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0               0x4A2624
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_1               0x4A2628
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_2               0x4A262C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_3               0x4A2630
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_4               0x4A2634
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_5               0x4A2638
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_6               0x4A263C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_7               0x4A2640
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_8               0x4A2644
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_9               0x4A2648
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_10              0x4A264C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_11              0x4A2650
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_12              0x4A2654
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_13              0x4A2658
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_14              0x4A265C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_15              0x4A2660
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0                0x4A2664
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_1                0x4A2668
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_2                0x4A266C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_3                0x4A2670
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_4                0x4A2674
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_5                0x4A2678
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_6                0x4A267C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_7                0x4A2680
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_8                0x4A2684
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_9                0x4A2688
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_10               0x4A268C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_11               0x4A2690
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_12               0x4A2694
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_13               0x4A2698
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_14               0x4A269C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_15               0x4A26A0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0               0x4A26A4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_1               0x4A26A8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_2               0x4A26AC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_3               0x4A26B0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_4               0x4A26B4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_5               0x4A26B8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_6               0x4A26BC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_7               0x4A26C0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_8               0x4A26C4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_9               0x4A26C8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_10              0x4A26CC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_11              0x4A26D0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_12              0x4A26D4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_13              0x4A26D8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_14              0x4A26DC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_15              0x4A26E0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_0               0x4A26E4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_1               0x4A26E8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_2               0x4A26EC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_3               0x4A26F0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_4               0x4A26F4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_5               0x4A26F8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_6               0x4A26FC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_7               0x4A2700
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_8               0x4A2704
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_9               0x4A2708
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_10              0x4A270C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_11              0x4A2710
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_12              0x4A2714
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_13              0x4A2718
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_14              0x4A271C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_15              0x4A2720
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_0              0x4A2724
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_1              0x4A2728
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_2              0x4A272C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_3              0x4A2730
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_4              0x4A2734
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_5              0x4A2738
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_6              0x4A273C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_7              0x4A2740
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_8              0x4A2744
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_9              0x4A2748
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_10             0x4A274C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_11             0x4A2750
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_12             0x4A2754
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_13             0x4A2758
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_14             0x4A275C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_15             0x4A2760
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_0               0x4A2764
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_1               0x4A2768
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_2               0x4A276C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_3               0x4A2770
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_4               0x4A2774
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_5               0x4A2778
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_6               0x4A277C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_7               0x4A2780
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_8               0x4A2784
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_9               0x4A2788
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_10              0x4A278C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_11              0x4A2790
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_12              0x4A2794
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_13              0x4A2798
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_14              0x4A279C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_15              0x4A27A0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_0              0x4A27A4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_1              0x4A27A8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_2              0x4A27AC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_3              0x4A27B0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_4              0x4A27B4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_5              0x4A27B8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_6              0x4A27BC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_7              0x4A27C0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_8              0x4A27C4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_9              0x4A27C8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_10             0x4A27CC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_11             0x4A27D0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_12             0x4A27D4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_13             0x4A27D8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_14             0x4A27DC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_15             0x4A27E0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0                0x4A2824
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_1                0x4A2828
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_2                0x4A282C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_3                0x4A2830
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_4                0x4A2834
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_5                0x4A2838
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_6                0x4A283C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_7                0x4A2840
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_8                0x4A2844
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_9                0x4A2848
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_10               0x4A284C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_11               0x4A2850
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_12               0x4A2854
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_13               0x4A2858
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_14               0x4A285C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_15               0x4A2860
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0               0x4A2864
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_1               0x4A2868
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_2               0x4A286C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_3               0x4A2870
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_4               0x4A2874
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_5               0x4A2878
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_6               0x4A287C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_7               0x4A2880
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_8               0x4A2884
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_9               0x4A2888
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_10              0x4A288C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_11              0x4A2890
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_12              0x4A2894
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_13              0x4A2898
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_14              0x4A289C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_15              0x4A28A0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0                0x4A28A4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_1                0x4A28A8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_2                0x4A28AC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_3                0x4A28B0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_4                0x4A28B4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_5                0x4A28B8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_6                0x4A28BC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_7                0x4A28C0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_8                0x4A28C4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_9                0x4A28C8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_10               0x4A28CC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_11               0x4A28D0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_12               0x4A28D4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_13               0x4A28D8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_14               0x4A28DC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_15               0x4A28E0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0               0x4A28E4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_1               0x4A28E8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_2               0x4A28EC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_3               0x4A28F0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_4               0x4A28F4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_5               0x4A28F8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_6               0x4A28FC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_7               0x4A2900
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_8               0x4A2904
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_9               0x4A2908
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_10              0x4A290C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_11              0x4A2910
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_12              0x4A2914
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_13              0x4A2918
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_14              0x4A291C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_15              0x4A2920
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_0               0x4A2924
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_1               0x4A2928
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_2               0x4A292C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_3               0x4A2930
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_4               0x4A2934
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_5               0x4A2938
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_6               0x4A293C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_7               0x4A2940
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_8               0x4A2944
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_9               0x4A2948
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_10              0x4A294C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_11              0x4A2950
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_12              0x4A2954
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_13              0x4A2958
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_14              0x4A295C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_15              0x4A2960
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_0              0x4A2964
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_1              0x4A2968
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_2              0x4A296C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_3              0x4A2970
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_4              0x4A2974
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_5              0x4A2978
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_6              0x4A297C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_7              0x4A2980
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_8              0x4A2984
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_9              0x4A2988
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_10             0x4A298C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_11             0x4A2990
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_12             0x4A2994
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_13             0x4A2998
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_14             0x4A299C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_15             0x4A29A0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_0               0x4A29A4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_1               0x4A29A8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_2               0x4A29AC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_3               0x4A29B0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_4               0x4A29B4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_5               0x4A29B8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_6               0x4A29BC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_7               0x4A29C0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_8               0x4A29C4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_9               0x4A29C8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_10              0x4A29CC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_11              0x4A29D0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_12              0x4A29D4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_13              0x4A29D8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_14              0x4A29DC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_15              0x4A29E0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_0              0x4A29E4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_1              0x4A29E8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_2              0x4A29EC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_3              0x4A29F0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_4              0x4A29F4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_5              0x4A29F8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_6              0x4A29FC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_7              0x4A2A00
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_8              0x4A2A04
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_9              0x4A2A08
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_10             0x4A2A0C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_11             0x4A2A10
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_12             0x4A2A14
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_13             0x4A2A18
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_14             0x4A2A1C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_15             0x4A2A20
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_HIT_AW                       0x4A2A64
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_HIT_AR                       0x4A2A68
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_HIT_AW                      0x4A2A6C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_HIT_AR                      0x4A2A70
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_CFG                                0x4A2B64
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_SHIFT                              0x4A2B68
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_0                     0x4A2B6C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_1                     0x4A2B70
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_2                     0x4A2B74
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_3                     0x4A2B78
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_4                     0x4A2B7C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_5                     0x4A2B80
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_6                     0x4A2B84
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_7                     0x4A2B88
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_0                            0x4A2BAC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_1                            0x4A2BB0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_2                            0x4A2BB4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_3                            0x4A2BB8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_4                            0x4A2BBC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_5                            0x4A2BC0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_6                            0x4A2BC4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_7                            0x4A2BC8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_0                          0x4A2BEC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_1                          0x4A2BF0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_2                          0x4A2BF4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_3                          0x4A2BF8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_4                          0x4A2BFC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_5                          0x4A2C00
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_6                          0x4A2C04
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_7                          0x4A2C08
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_WDT                                0x4A2C2C
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_WRAP               0x4A2C30
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_WRAP               0x4A2C34
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_WRAP               0x4A2C38
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_WRAP               0x4A2C3C
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_WRAP               0x4A2C40
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_WRAP               0x4A2C44
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_WRAP               0x4A2C48
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_WRAP               0x4A2C4C
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_CNT                0x4A2C50
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_CNT                0x4A2C54
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_CNT                0x4A2C58
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_CNT                0x4A2C5C
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_CNT                0x4A2C60
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_CNT                0x4A2C64
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_CNT                0x4A2C68
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_CNT                0x4A2C6C
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_WRAP               0x4A2C70
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_WRAP               0x4A2C74
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_WRAP               0x4A2C78
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_WRAP               0x4A2C7C
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_WRAP               0x4A2C80
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_WRAP               0x4A2C84
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_WRAP               0x4A2C88
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_WRAP               0x4A2C8C
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_CNT                0x4A2C90
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_CNT                0x4A2C94
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_CNT                0x4A2C98
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_CNT                0x4A2C9C
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_CNT                0x4A2CA0
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_CNT                0x4A2CA4
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_CNT                0x4A2CA8
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_CNT                0x4A2CAC
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_PC_SEL_0                        0x4A2CB0
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_PC_SEL_1                        0x4A2CB4
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_PC_SEL_2                        0x4A2CB8
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_PC_SEL_3                        0x4A2CBC
+
+#endif /* ASIC_REG_DMA_IF_E_S_DOWN_CH1_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_s_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_s_regs.h
new file mode 100644
index 000000000000..78c18da7154b
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_s_regs.h
@@ -0,0 +1,860 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DMA_IF_E_S_REGS_H_
+#define ASIC_REG_DMA_IF_E_S_REGS_H_
+
+/*
+ *****************************************
+ *   DMA_IF_E_S (Prototype: DMA_IF)
+ *****************************************
+ */
+
+#define mmDMA_IF_E_S_HBM0_WR_CRED_CNT                                0x4A0000
+
+#define mmDMA_IF_E_S_HBM1_WR_CRED_CNT                                0x4A0004
+
+#define mmDMA_IF_E_S_HBM0_RD_CRED_CNT                                0x4A0008
+
+#define mmDMA_IF_E_S_HBM1_RD_CRED_CNT                                0x4A000C
+
+#define mmDMA_IF_E_S_HBM_LIMITER_0                                   0x4A0030
+
+#define mmDMA_IF_E_S_HBM_LIMITER_1                                   0x4A0034
+
+#define mmDMA_IF_E_S_HBM_LIMITER_2                                   0x4A0038
+
+#define mmDMA_IF_E_S_HBM_LIMITER_3                                   0x4A003C
+
+#define mmDMA_IF_E_S_HBM_ALMOST_EN_0                                 0x4A0040
+
+#define mmDMA_IF_E_S_HBM_ALMOST_EN_1                                 0x4A0044
+
+#define mmDMA_IF_E_S_HBM_CRED_EN_0                                   0x4A0050
+
+#define mmDMA_IF_E_S_HBM_CRED_EN_1                                   0x4A0054
+
+#define mmDMA_IF_E_S_SOB_MIN_RPROT_0                                 0x4A0100
+
+#define mmDMA_IF_E_S_SOB_MIN_RPROT_1                                 0x4A0104
+
+#define mmDMA_IF_E_S_SOB_MIN_RPROT_2                                 0x4A0108
+
+#define mmDMA_IF_E_S_SOB_MIN_RPROT_3                                 0x4A010C
+
+#define mmDMA_IF_E_S_SOB_MIN_RPROT_4                                 0x4A0110
+
+#define mmDMA_IF_E_S_SOB_MIN_RPROT_5                                 0x4A0114
+
+#define mmDMA_IF_E_S_SOB_MIN_RPROT_6                                 0x4A0118
+
+#define mmDMA_IF_E_S_SOB_MIN_RPROT_7                                 0x4A011C
+
+#define mmDMA_IF_E_S_SOB_MIN_RPROT_8                                 0x4A0120
+
+#define mmDMA_IF_E_S_SOB_MIN_RPROT_9                                 0x4A0124
+
+#define mmDMA_IF_E_S_SOB_MIN_RPROT_10                                0x4A0128
+
+#define mmDMA_IF_E_S_SOB_MIN_RPROT_11                                0x4A012C
+
+#define mmDMA_IF_E_S_SOB_MIN_RPROT_12                                0x4A0130
+
+#define mmDMA_IF_E_S_SOB_MIN_RPROT_13                                0x4A0134
+
+#define mmDMA_IF_E_S_SOB_MIN_RPROT_14                                0x4A0138
+
+#define mmDMA_IF_E_S_SOB_MIN_RPROT_15                                0x4A013C
+
+#define mmDMA_IF_E_S_SOB_MAX_RPROT_0                                 0x4A0140
+
+#define mmDMA_IF_E_S_SOB_MAX_RPROT_1                                 0x4A0144
+
+#define mmDMA_IF_E_S_SOB_MAX_RPROT_2                                 0x4A0148
+
+#define mmDMA_IF_E_S_SOB_MAX_RPROT_3                                 0x4A014C
+
+#define mmDMA_IF_E_S_SOB_MAX_RPROT_4                                 0x4A0150
+
+#define mmDMA_IF_E_S_SOB_MAX_RPROT_5                                 0x4A0154
+
+#define mmDMA_IF_E_S_SOB_MAX_RPROT_6                                 0x4A0158
+
+#define mmDMA_IF_E_S_SOB_MAX_RPROT_7                                 0x4A015C
+
+#define mmDMA_IF_E_S_SOB_MAX_RPROT_8                                 0x4A0160
+
+#define mmDMA_IF_E_S_SOB_MAX_RPROT_9                                 0x4A0164
+
+#define mmDMA_IF_E_S_SOB_MAX_RPROT_10                                0x4A0168
+
+#define mmDMA_IF_E_S_SOB_MAX_RPROT_11                                0x4A016C
+
+#define mmDMA_IF_E_S_SOB_MAX_RPROT_12                                0x4A0170
+
+#define mmDMA_IF_E_S_SOB_MAX_RPROT_13                                0x4A0174
+
+#define mmDMA_IF_E_S_SOB_MAX_RPROT_14                                0x4A0178
+
+#define mmDMA_IF_E_S_SOB_MAX_RPROT_15                                0x4A017C
+
+#define mmDMA_IF_E_S_SOB_MIN_WPROT_0                                 0x4A0180
+
+#define mmDMA_IF_E_S_SOB_MIN_WPROT_1                                 0x4A0184
+
+#define mmDMA_IF_E_S_SOB_MIN_WPROT_2                                 0x4A0188
+
+#define mmDMA_IF_E_S_SOB_MIN_WPROT_3                                 0x4A018C
+
+#define mmDMA_IF_E_S_SOB_MIN_WPROT_4                                 0x4A0190
+
+#define mmDMA_IF_E_S_SOB_MIN_WPROT_5                                 0x4A0194
+
+#define mmDMA_IF_E_S_SOB_MIN_WPROT_6                                 0x4A0198
+
+#define mmDMA_IF_E_S_SOB_MIN_WPROT_7                                 0x4A019C
+
+#define mmDMA_IF_E_S_SOB_MIN_WPROT_8                                 0x4A01A0
+
+#define mmDMA_IF_E_S_SOB_MIN_WPROT_9                                 0x4A01A4
+
+#define mmDMA_IF_E_S_SOB_MIN_WPROT_10                                0x4A01A8
+
+#define mmDMA_IF_E_S_SOB_MIN_WPROT_11                                0x4A01AC
+
+#define mmDMA_IF_E_S_SOB_MIN_WPROT_12                                0x4A01B0
+
+#define mmDMA_IF_E_S_SOB_MIN_WPROT_13                                0x4A01B4
+
+#define mmDMA_IF_E_S_SOB_MIN_WPROT_14                                0x4A01B8
+
+#define mmDMA_IF_E_S_SOB_MIN_WPROT_15                                0x4A01BC
+
+#define mmDMA_IF_E_S_SOB_MAX_WPROT_0                                 0x4A01C0
+
+#define mmDMA_IF_E_S_SOB_MAX_WPROT_1                                 0x4A01C4
+
+#define mmDMA_IF_E_S_SOB_MAX_WPROT_2                                 0x4A01C8
+
+#define mmDMA_IF_E_S_SOB_MAX_WPROT_3                                 0x4A01CC
+
+#define mmDMA_IF_E_S_SOB_MAX_WPROT_4                                 0x4A01D0
+
+#define mmDMA_IF_E_S_SOB_MAX_WPROT_5                                 0x4A01D4
+
+#define mmDMA_IF_E_S_SOB_MAX_WPROT_6                                 0x4A01D8
+
+#define mmDMA_IF_E_S_SOB_MAX_WPROT_7                                 0x4A01DC
+
+#define mmDMA_IF_E_S_SOB_MAX_WPROT_8                                 0x4A01E0
+
+#define mmDMA_IF_E_S_SOB_MAX_WPROT_9                                 0x4A01E4
+
+#define mmDMA_IF_E_S_SOB_MAX_WPROT_10                                0x4A01E8
+
+#define mmDMA_IF_E_S_SOB_MAX_WPROT_11                                0x4A01EC
+
+#define mmDMA_IF_E_S_SOB_MAX_WPROT_12                                0x4A01F0
+
+#define mmDMA_IF_E_S_SOB_MAX_WPROT_13                                0x4A01F4
+
+#define mmDMA_IF_E_S_SOB_MAX_WPROT_14                                0x4A01F8
+
+#define mmDMA_IF_E_S_SOB_MAX_WPROT_15                                0x4A01FC
+
+#define mmDMA_IF_E_S_SOB_MIN_RPRIV_0                                 0x4A0200
+
+#define mmDMA_IF_E_S_SOB_MIN_RPRIV_1                                 0x4A0204
+
+#define mmDMA_IF_E_S_SOB_MIN_RPRIV_2                                 0x4A0208
+
+#define mmDMA_IF_E_S_SOB_MIN_RPRIV_3                                 0x4A020C
+
+#define mmDMA_IF_E_S_SOB_MIN_RPRIV_4                                 0x4A0210
+
+#define mmDMA_IF_E_S_SOB_MIN_RPRIV_5                                 0x4A0214
+
+#define mmDMA_IF_E_S_SOB_MIN_RPRIV_6                                 0x4A0218
+
+#define mmDMA_IF_E_S_SOB_MIN_RPRIV_7                                 0x4A021C
+
+#define mmDMA_IF_E_S_SOB_MIN_RPRIV_8                                 0x4A0220
+
+#define mmDMA_IF_E_S_SOB_MIN_RPRIV_9                                 0x4A0224
+
+#define mmDMA_IF_E_S_SOB_MIN_RPRIV_10                                0x4A0228
+
+#define mmDMA_IF_E_S_SOB_MIN_RPRIV_11                                0x4A022C
+
+#define mmDMA_IF_E_S_SOB_MIN_RPRIV_12                                0x4A0230
+
+#define mmDMA_IF_E_S_SOB_MIN_RPRIV_13                                0x4A0234
+
+#define mmDMA_IF_E_S_SOB_MIN_RPRIV_14                                0x4A0238
+
+#define mmDMA_IF_E_S_SOB_MIN_RPRIV_15                                0x4A023C
+
+#define mmDMA_IF_E_S_SOB_MAX_RPRIV_0                                 0x4A0240
+
+#define mmDMA_IF_E_S_SOB_MAX_RPRIV_1                                 0x4A0244
+
+#define mmDMA_IF_E_S_SOB_MAX_RPRIV_2                                 0x4A0248
+
+#define mmDMA_IF_E_S_SOB_MAX_RPRIV_3                                 0x4A024C
+
+#define mmDMA_IF_E_S_SOB_MAX_RPRIV_4                                 0x4A0250
+
+#define mmDMA_IF_E_S_SOB_MAX_RPRIV_5                                 0x4A0254
+
+#define mmDMA_IF_E_S_SOB_MAX_RPRIV_6                                 0x4A0258
+
+#define mmDMA_IF_E_S_SOB_MAX_RPRIV_7                                 0x4A025C
+
+#define mmDMA_IF_E_S_SOB_MAX_RPRIV_8                                 0x4A0260
+
+#define mmDMA_IF_E_S_SOB_MAX_RPRIV_9                                 0x4A0264
+
+#define mmDMA_IF_E_S_SOB_MAX_RPRIV_10                                0x4A0268
+
+#define mmDMA_IF_E_S_SOB_MAX_RPRIV_11                                0x4A026C
+
+#define mmDMA_IF_E_S_SOB_MAX_RPRIV_12                                0x4A0270
+
+#define mmDMA_IF_E_S_SOB_MAX_RPRIV_13                                0x4A0274
+
+#define mmDMA_IF_E_S_SOB_MAX_RPRIV_14                                0x4A0278
+
+#define mmDMA_IF_E_S_SOB_MAX_RPRIV_15                                0x4A027C
+
+#define mmDMA_IF_E_S_SOB_MIN_WPRIV_0                                 0x4A0280
+
+#define mmDMA_IF_E_S_SOB_MIN_WPRIV_1                                 0x4A0284
+
+#define mmDMA_IF_E_S_SOB_MIN_WPRIV_2                                 0x4A0288
+
+#define mmDMA_IF_E_S_SOB_MIN_WPRIV_3                                 0x4A028C
+
+#define mmDMA_IF_E_S_SOB_MIN_WPRIV_4                                 0x4A0290
+
+#define mmDMA_IF_E_S_SOB_MIN_WPRIV_5                                 0x4A0294
+
+#define mmDMA_IF_E_S_SOB_MIN_WPRIV_6                                 0x4A0298
+
+#define mmDMA_IF_E_S_SOB_MIN_WPRIV_7                                 0x4A029C
+
+#define mmDMA_IF_E_S_SOB_MIN_WPRIV_8                                 0x4A02A0
+
+#define mmDMA_IF_E_S_SOB_MIN_WPRIV_9                                 0x4A02A4
+
+#define mmDMA_IF_E_S_SOB_MIN_WPRIV_10                                0x4A02A8
+
+#define mmDMA_IF_E_S_SOB_MIN_WPRIV_11                                0x4A02AC
+
+#define mmDMA_IF_E_S_SOB_MIN_WPRIV_12                                0x4A02B0
+
+#define mmDMA_IF_E_S_SOB_MIN_WPRIV_13                                0x4A02B4
+
+#define mmDMA_IF_E_S_SOB_MIN_WPRIV_14                                0x4A02B8
+
+#define mmDMA_IF_E_S_SOB_MIN_WPRIV_15                                0x4A02BC
+
+#define mmDMA_IF_E_S_SOB_MAX_WPRIV_0                                 0x4A02C0
+
+#define mmDMA_IF_E_S_SOB_MAX_WPRIV_1                                 0x4A02C4
+
+#define mmDMA_IF_E_S_SOB_MAX_WPRIV_2                                 0x4A02C8
+
+#define mmDMA_IF_E_S_SOB_MAX_WPRIV_3                                 0x4A02CC
+
+#define mmDMA_IF_E_S_SOB_MAX_WPRIV_4                                 0x4A02D0
+
+#define mmDMA_IF_E_S_SOB_MAX_WPRIV_5                                 0x4A02D4
+
+#define mmDMA_IF_E_S_SOB_MAX_WPRIV_6                                 0x4A02D8
+
+#define mmDMA_IF_E_S_SOB_MAX_WPRIV_7                                 0x4A02DC
+
+#define mmDMA_IF_E_S_SOB_MAX_WPRIV_8                                 0x4A02E0
+
+#define mmDMA_IF_E_S_SOB_MAX_WPRIV_9                                 0x4A02E4
+
+#define mmDMA_IF_E_S_SOB_MAX_WPRIV_10                                0x4A02E8
+
+#define mmDMA_IF_E_S_SOB_MAX_WPRIV_11                                0x4A02EC
+
+#define mmDMA_IF_E_S_SOB_MAX_WPRIV_12                                0x4A02F0
+
+#define mmDMA_IF_E_S_SOB_MAX_WPRIV_13                                0x4A02F4
+
+#define mmDMA_IF_E_S_SOB_MAX_WPRIV_14                                0x4A02F8
+
+#define mmDMA_IF_E_S_SOB_MAX_WPRIV_15                                0x4A02FC
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPROT_0                                0x4A0300
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPROT_1                                0x4A0304
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPROT_2                                0x4A0308
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPROT_3                                0x4A030C
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPROT_4                                0x4A0310
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPROT_5                                0x4A0314
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPROT_6                                0x4A0318
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPROT_7                                0x4A031C
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPROT_8                                0x4A0320
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPROT_9                                0x4A0324
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPROT_10                               0x4A0328
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPROT_11                               0x4A032C
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPROT_12                               0x4A0330
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPROT_13                               0x4A0334
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPROT_14                               0x4A0338
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPROT_15                               0x4A033C
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPROT_0                                0x4A0340
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPROT_1                                0x4A0344
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPROT_2                                0x4A0348
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPROT_3                                0x4A034C
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPROT_4                                0x4A0350
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPROT_5                                0x4A0354
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPROT_6                                0x4A0358
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPROT_7                                0x4A035C
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPROT_8                                0x4A0360
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPROT_9                                0x4A0364
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPROT_10                               0x4A0368
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPROT_11                               0x4A036C
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPROT_12                               0x4A0370
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPROT_13                               0x4A0374
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPROT_14                               0x4A0378
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPROT_15                               0x4A037C
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPROT_0                                0x4A0380
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPROT_1                                0x4A0384
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPROT_2                                0x4A0388
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPROT_3                                0x4A038C
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPROT_4                                0x4A0390
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPROT_5                                0x4A0394
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPROT_6                                0x4A0398
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPROT_7                                0x4A039C
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPROT_8                                0x4A03A0
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPROT_9                                0x4A03A4
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPROT_10                               0x4A03A8
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPROT_11                               0x4A03AC
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPROT_12                               0x4A03B0
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPROT_13                               0x4A03B4
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPROT_14                               0x4A03B8
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPROT_15                               0x4A03BC
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPROT_0                                0x4A03C0
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPROT_1                                0x4A03C4
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPROT_2                                0x4A03C8
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPROT_3                                0x4A03CC
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPROT_4                                0x4A03D0
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPROT_5                                0x4A03D4
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPROT_6                                0x4A03D8
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPROT_7                                0x4A03DC
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPROT_8                                0x4A03E0
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPROT_9                                0x4A03E4
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPROT_10                               0x4A03E8
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPROT_11                               0x4A03EC
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPROT_12                               0x4A03F0
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPROT_13                               0x4A03F4
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPROT_14                               0x4A03F8
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPROT_15                               0x4A03FC
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_0                                0x4A0400
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_1                                0x4A0404
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_2                                0x4A0408
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_3                                0x4A040C
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_4                                0x4A0410
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_5                                0x4A0414
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_6                                0x4A0418
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_7                                0x4A041C
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_8                                0x4A0420
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_9                                0x4A0424
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_10                               0x4A0428
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_11                               0x4A042C
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_12                               0x4A0430
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_13                               0x4A0434
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_14                               0x4A0438
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_15                               0x4A043C
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_0                                0x4A0440
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_1                                0x4A0444
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_2                                0x4A0448
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_3                                0x4A044C
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_4                                0x4A0450
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_5                                0x4A0454
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_6                                0x4A0458
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_7                                0x4A045C
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_8                                0x4A0460
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_9                                0x4A0464
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_10                               0x4A0468
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_11                               0x4A046C
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_12                               0x4A0470
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_13                               0x4A0474
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_14                               0x4A0478
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_15                               0x4A047C
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_0                                0x4A0480
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_1                                0x4A0484
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_2                                0x4A0488
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_3                                0x4A048C
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_4                                0x4A0490
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_5                                0x4A0494
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_6                                0x4A0498
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_7                                0x4A049C
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_8                                0x4A04A0
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_9                                0x4A04A4
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_10                               0x4A04A8
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_11                               0x4A04AC
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_12                               0x4A04B0
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_13                               0x4A04B4
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_14                               0x4A04B8
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_15                               0x4A04BC
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_0                                0x4A04C0
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_1                                0x4A04C4
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_2                                0x4A04C8
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_3                                0x4A04CC
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_4                                0x4A04D0
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_5                                0x4A04D4
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_6                                0x4A04D8
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_7                                0x4A04DC
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_8                                0x4A04E0
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_9                                0x4A04E4
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_10                               0x4A04E8
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_11                               0x4A04EC
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_12                               0x4A04F0
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_13                               0x4A04F4
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_14                               0x4A04F8
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_15                               0x4A04FC
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPROT_0                                0x4A0500
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPROT_1                                0x4A0504
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPROT_2                                0x4A0508
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPROT_3                                0x4A050C
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPROT_4                                0x4A0510
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPROT_5                                0x4A0514
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPROT_6                                0x4A0518
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPROT_7                                0x4A051C
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPROT_8                                0x4A0520
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPROT_9                                0x4A0524
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPROT_10                               0x4A0528
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPROT_11                               0x4A052C
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPROT_12                               0x4A0530
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPROT_13                               0x4A0534
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPROT_14                               0x4A0538
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPROT_15                               0x4A053C
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPROT_0                                0x4A0540
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPROT_1                                0x4A0544
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPROT_2                                0x4A0548
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPROT_3                                0x4A054C
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPROT_4                                0x4A0550
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPROT_5                                0x4A0554
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPROT_6                                0x4A0558
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPROT_7                                0x4A055C
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPROT_8                                0x4A0560
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPROT_9                                0x4A0564
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPROT_10                               0x4A0568
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPROT_11                               0x4A056C
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPROT_12                               0x4A0570
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPROT_13                               0x4A0574
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPROT_14                               0x4A0578
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPROT_15                               0x4A057C
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPROT_0                                0x4A0580
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPROT_1                                0x4A0584
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPROT_2                                0x4A0588
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPROT_3                                0x4A058C
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPROT_4                                0x4A0590
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPROT_5                                0x4A0594
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPROT_6                                0x4A0598
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPROT_7                                0x4A059C
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPROT_8                                0x4A05A0
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPROT_9                                0x4A05A4
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPROT_10                               0x4A05A8
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPROT_11                               0x4A05AC
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPROT_12                               0x4A05B0
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPROT_13                               0x4A05B4
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPROT_14                               0x4A05B8
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPROT_15                               0x4A05BC
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPROT_0                                0x4A05C0
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPROT_1                                0x4A05C4
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPROT_2                                0x4A05C8
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPROT_3                                0x4A05CC
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPROT_4                                0x4A05D0
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPROT_5                                0x4A05D4
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPROT_6                                0x4A05D8
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPROT_7                                0x4A05DC
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPROT_8                                0x4A05E0
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPROT_9                                0x4A05E4
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPROT_10                               0x4A05E8
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPROT_11                               0x4A05EC
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPROT_12                               0x4A05F0
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPROT_13                               0x4A05F4
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPROT_14                               0x4A05F8
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPROT_15                               0x4A05FC
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_0                                0x4A0600
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_1                                0x4A0604
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_2                                0x4A0608
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_3                                0x4A060C
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_4                                0x4A0610
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_5                                0x4A0614
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_6                                0x4A0618
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_7                                0x4A061C
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_8                                0x4A0620
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_9                                0x4A0624
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_10                               0x4A0628
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_11                               0x4A062C
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_12                               0x4A0630
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_13                               0x4A0634
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_14                               0x4A0638
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_15                               0x4A063C
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_0                                0x4A0640
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_1                                0x4A0644
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_2                                0x4A0648
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_3                                0x4A064C
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_4                                0x4A0650
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_5                                0x4A0654
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_6                                0x4A0658
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_7                                0x4A065C
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_8                                0x4A0660
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_9                                0x4A0664
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_10                               0x4A0668
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_11                               0x4A066C
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_12                               0x4A0670
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_13                               0x4A0674
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_14                               0x4A0678
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_15                               0x4A067C
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_0                                0x4A0680
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_1                                0x4A0684
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_2                                0x4A0688
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_3                                0x4A068C
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_4                                0x4A0690
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_5                                0x4A0694
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_6                                0x4A0698
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_7                                0x4A069C
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_8                                0x4A06A0
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_9                                0x4A06A4
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_10                               0x4A06A8
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_11                               0x4A06AC
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_12                               0x4A06B0
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_13                               0x4A06B4
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_14                               0x4A06B8
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_15                               0x4A06BC
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_0                                0x4A06C0
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_1                                0x4A06C4
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_2                                0x4A06C8
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_3                                0x4A06CC
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_4                                0x4A06D0
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_5                                0x4A06D4
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_6                                0x4A06D8
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_7                                0x4A06DC
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_8                                0x4A06E0
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_9                                0x4A06E4
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_10                               0x4A06E8
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_11                               0x4A06EC
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_12                               0x4A06F0
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_13                               0x4A06F4
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_14                               0x4A06F8
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_15                               0x4A06FC
+
+#define mmDMA_IF_E_S_SOB_HIT_RPROT                                   0x4A0700
+
+#define mmDMA_IF_E_S_SOB_HIT_WPROT                                   0x4A0704
+
+#define mmDMA_IF_E_S_SOB_HIT_RPRIV                                   0x4A070C
+
+#define mmDMA_IF_E_S_SOB_HIT_WPRIV                                   0x4A0710
+
+#define mmDMA_IF_E_S_DMA0_HIT_RPROT                                  0x4A071C
+
+#define mmDMA_IF_E_S_DMA0_HIT_WPROT                                  0x4A0720
+
+#define mmDMA_IF_E_S_DMA0_HIT_RPRIV                                  0x4A0724
+
+#define mmDMA_IF_E_S_DMA0_HIT_WPRIV                                  0x4A0728
+
+#define mmDMA_IF_E_S_DMA1_HIT_RPROT                                  0x4A0730
+
+#define mmDMA_IF_E_S_DMA1_HIT_WPROT                                  0x4A0734
+
+#define mmDMA_IF_E_S_DMA1_HIT_RPRIV                                  0x4A0738
+
+#define mmDMA_IF_E_S_DMA1_HIT_WPRIV                                  0x4A073C
+
+#define mmDMA_IF_E_S_HBM_BIN                                         0x4A0800
+
+#define mmDMA_IF_E_S_MME_BIN                                         0x4A0804
+
+#define mmDMA_IF_E_S_TPC_BIN                                         0x4A0808
+
+#define mmDMA_IF_E_S_DMA_BIN                                         0x4A080C
+
+#define mmDMA_IF_E_S_SOB_CG_EN                                       0x4A0810
+
+#define mmDMA_IF_E_S_HBM_I2C_ADDR_0                                  0x4A0820
+
+#define mmDMA_IF_E_S_HBM_I2C_ADDR_1                                  0x4A0824
+
+#define mmDMA_IF_E_S_HBM_I2C_ADDR_2                                  0x4A0828
+
+#define mmDMA_IF_E_S_HBM_I2C_ADDR_3                                  0x4A082C
+
+#define mmDMA_IF_E_S_HBM_I2C_ADDR_4                                  0x4A0830
+
+#define mmDMA_IF_E_S_HBM_MISC                                        0x4A0834
+
+#endif /* ASIC_REG_DMA_IF_E_S_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_n_down_ch0_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_n_down_ch0_regs.h
new file mode 100644
index 000000000000..4ccaf8712948
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_n_down_ch0_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DMA_IF_W_N_DOWN_CH0_REGS_H_
+#define ASIC_REG_DMA_IF_W_N_DOWN_CH0_REGS_H_
+
+/*
+ *****************************************
+ *   DMA_IF_W_N_DOWN_CH0 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmDMA_IF_W_N_DOWN_CH0_PERM_SEL                               0x4C1108
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_0                          0x4C1114
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_1                          0x4C1118
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_2                          0x4C111C
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_3                          0x4C1120
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_4                          0x4C1124
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_5                          0x4C1128
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_6                          0x4C112C
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_7                          0x4C1130
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_8                          0x4C1134
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_9                          0x4C1138
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_10                         0x4C113C
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_11                         0x4C1140
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_12                         0x4C1144
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_13                         0x4C1148
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_14                         0x4C114C
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_15                         0x4C1150
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_16                         0x4C1154
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_17                         0x4C1158
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_18                         0x4C115C
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_19                         0x4C1160
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_20                         0x4C1164
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_21                         0x4C1168
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_22                         0x4C116C
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_23                         0x4C1170
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_24                         0x4C1174
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_25                         0x4C1178
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_26                         0x4C117C
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_27                         0x4C1180
+
+#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_0                         0x4C1184
+
+#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_1                         0x4C1188
+
+#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_2                         0x4C118C
+
+#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_3                         0x4C1190
+
+#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_4                         0x4C1194
+
+#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_5                         0x4C1198
+
+#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_6                         0x4C119C
+
+#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_7                         0x4C11A0
+
+#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_8                         0x4C11A4
+
+#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_9                         0x4C11A8
+
+#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_10                        0x4C11AC
+
+#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_11                        0x4C11B0
+
+#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_12                        0x4C11B4
+
+#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_13                        0x4C11B8
+
+#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_14                        0x4C11BC
+
+#define mmDMA_IF_W_N_DOWN_CH0_SCRAM_SRAM_EN                          0x4C126C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RL_HBM_EN                              0x4C1274
+
+#define mmDMA_IF_W_N_DOWN_CH0_RL_HBM_SAT                             0x4C1278
+
+#define mmDMA_IF_W_N_DOWN_CH0_RL_HBM_RST                             0x4C127C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RL_HBM_TIMEOUT                         0x4C1280
+
+#define mmDMA_IF_W_N_DOWN_CH0_SCRAM_HBM_EN                           0x4C1284
+
+#define mmDMA_IF_W_N_DOWN_CH0_RL_PCI_EN                              0x4C1288
+
+#define mmDMA_IF_W_N_DOWN_CH0_RL_PCI_SAT                             0x4C128C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RL_PCI_RST                             0x4C1290
+
+#define mmDMA_IF_W_N_DOWN_CH0_RL_PCI_TIMEOUT                         0x4C1294
+
+#define mmDMA_IF_W_N_DOWN_CH0_RL_SRAM_EN                             0x4C129C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RL_SRAM_SAT                            0x4C12A0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RL_SRAM_RST                            0x4C12A4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RL_SRAM_TIMEOUT                        0x4C12AC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RL_SRAM_RED                            0x4C12B4
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_HBM_EN                             0x4C12EC
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_PCI_EN                             0x4C12F0
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_HBM_WR_SIZE                        0x4C12F4
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_PCI_WR_SIZE                        0x4C12F8
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_PCI_CTR_SET_EN                  0x4C1404
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_PCI_CTR_SET                     0x4C1408
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_PCI_CTR_WRAP                    0x4C140C
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_PCI_CTR_CNT                     0x4C1410
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM_CTR_SET_EN                  0x4C1414
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM_CTR_SET                     0x4C1418
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_HBM_RD_SIZE                        0x4C141C
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_PCI_RD_SIZE                        0x4C1420
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_PCI_CTR_SET_EN                  0x4C1424
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_PCI_CTR_SET                     0x4C1428
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_PCI_CTR_WRAP                    0x4C142C
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_PCI_CTR_CNT                     0x4C1430
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM_CTR_SET_EN                  0x4C1434
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM_CTR_SET                     0x4C1438
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_SEL_0                           0x4C1450
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_SEL_1                           0x4C1454
+
+#define mmDMA_IF_W_N_DOWN_CH0_NON_LIN_EN                             0x4C1480
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_BANK_0                         0x4C1500
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_BANK_1                         0x4C1504
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_BANK_2                         0x4C1508
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_BANK_3                         0x4C150C
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_BANK_4                         0x4C1510
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_0                       0x4C1514
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_1                       0x4C1520
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_2                       0x4C1524
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_3                       0x4C1528
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_4                       0x4C152C
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_5                       0x4C1530
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_6                       0x4C1534
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_7                       0x4C1538
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_8                       0x4C153C
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_9                       0x4C1540
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_0                        0x4C1550
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_1                        0x4C1554
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_2                        0x4C1558
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_3                        0x4C155C
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_4                        0x4C1560
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_5                        0x4C1564
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_6                        0x4C1568
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_7                        0x4C156C
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_8                        0x4C1570
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_9                        0x4C1574
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_10                       0x4C1578
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_11                       0x4C157C
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_12                       0x4C1580
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_13                       0x4C1584
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_14                       0x4C1588
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_15                       0x4C158C
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_16                       0x4C1590
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_17                       0x4C1594
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_18                       0x4C1598
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_0                0x4C15E4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_1                0x4C15E8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_2                0x4C15EC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_3                0x4C15F0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_4                0x4C15F4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_5                0x4C15F8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_6                0x4C15FC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_7                0x4C1600
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_8                0x4C1604
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_9                0x4C1608
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_10               0x4C160C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_11               0x4C1610
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_12               0x4C1614
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_13               0x4C1618
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_14               0x4C161C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_15               0x4C1620
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_0               0x4C1624
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_1               0x4C1628
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_2               0x4C162C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_3               0x4C1630
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_4               0x4C1634
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_5               0x4C1638
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_6               0x4C163C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_7               0x4C1640
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_8               0x4C1644
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_9               0x4C1648
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_10              0x4C164C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_11              0x4C1650
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_12              0x4C1654
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_13              0x4C1658
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_14              0x4C165C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_15              0x4C1660
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_0                0x4C1664
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_1                0x4C1668
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_2                0x4C166C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_3                0x4C1670
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_4                0x4C1674
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_5                0x4C1678
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_6                0x4C167C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_7                0x4C1680
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_8                0x4C1684
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_9                0x4C1688
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_10               0x4C168C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_11               0x4C1690
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_12               0x4C1694
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_13               0x4C1698
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_14               0x4C169C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_15               0x4C16A0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_0               0x4C16A4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_1               0x4C16A8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_2               0x4C16AC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_3               0x4C16B0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_4               0x4C16B4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_5               0x4C16B8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_6               0x4C16BC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_7               0x4C16C0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_8               0x4C16C4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_9               0x4C16C8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_10              0x4C16CC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_11              0x4C16D0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_12              0x4C16D4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_13              0x4C16D8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_14              0x4C16DC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_15              0x4C16E0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_0               0x4C16E4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_1               0x4C16E8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_2               0x4C16EC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_3               0x4C16F0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_4               0x4C16F4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_5               0x4C16F8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_6               0x4C16FC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_7               0x4C1700
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_8               0x4C1704
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_9               0x4C1708
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_10              0x4C170C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_11              0x4C1710
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_12              0x4C1714
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_13              0x4C1718
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_14              0x4C171C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_15              0x4C1720
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_0              0x4C1724
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_1              0x4C1728
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_2              0x4C172C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_3              0x4C1730
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_4              0x4C1734
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_5              0x4C1738
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_6              0x4C173C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_7              0x4C1740
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_8              0x4C1744
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_9              0x4C1748
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_10             0x4C174C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_11             0x4C1750
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_12             0x4C1754
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_13             0x4C1758
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_14             0x4C175C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_15             0x4C1760
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_0               0x4C1764
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_1               0x4C1768
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_2               0x4C176C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_3               0x4C1770
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_4               0x4C1774
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_5               0x4C1778
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_6               0x4C177C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_7               0x4C1780
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_8               0x4C1784
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_9               0x4C1788
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_10              0x4C178C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_11              0x4C1790
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_12              0x4C1794
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_13              0x4C1798
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_14              0x4C179C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_15              0x4C17A0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_0              0x4C17A4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_1              0x4C17A8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_2              0x4C17AC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_3              0x4C17B0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_4              0x4C17B4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_5              0x4C17B8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_6              0x4C17BC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_7              0x4C17C0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_8              0x4C17C4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_9              0x4C17C8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_10             0x4C17CC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_11             0x4C17D0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_12             0x4C17D4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_13             0x4C17D8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_14             0x4C17DC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_15             0x4C17E0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_0                0x4C1824
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_1                0x4C1828
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_2                0x4C182C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_3                0x4C1830
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_4                0x4C1834
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_5                0x4C1838
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_6                0x4C183C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_7                0x4C1840
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_8                0x4C1844
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_9                0x4C1848
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_10               0x4C184C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_11               0x4C1850
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_12               0x4C1854
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_13               0x4C1858
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_14               0x4C185C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_15               0x4C1860
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_0               0x4C1864
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_1               0x4C1868
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_2               0x4C186C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_3               0x4C1870
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_4               0x4C1874
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_5               0x4C1878
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_6               0x4C187C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_7               0x4C1880
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_8               0x4C1884
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_9               0x4C1888
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_10              0x4C188C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_11              0x4C1890
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_12              0x4C1894
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_13              0x4C1898
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_14              0x4C189C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_15              0x4C18A0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_0                0x4C18A4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_1                0x4C18A8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_2                0x4C18AC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_3                0x4C18B0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_4                0x4C18B4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_5                0x4C18B8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_6                0x4C18BC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_7                0x4C18C0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_8                0x4C18C4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_9                0x4C18C8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_10               0x4C18CC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_11               0x4C18D0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_12               0x4C18D4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_13               0x4C18D8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_14               0x4C18DC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_15               0x4C18E0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_0               0x4C18E4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_1               0x4C18E8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_2               0x4C18EC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_3               0x4C18F0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_4               0x4C18F4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_5               0x4C18F8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_6               0x4C18FC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_7               0x4C1900
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_8               0x4C1904
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_9               0x4C1908
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_10              0x4C190C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_11              0x4C1910
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_12              0x4C1914
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_13              0x4C1918
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_14              0x4C191C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_15              0x4C1920
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_0               0x4C1924
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_1               0x4C1928
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_2               0x4C192C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_3               0x4C1930
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_4               0x4C1934
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_5               0x4C1938
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_6               0x4C193C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_7               0x4C1940
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_8               0x4C1944
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_9               0x4C1948
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_10              0x4C194C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_11              0x4C1950
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_12              0x4C1954
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_13              0x4C1958
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_14              0x4C195C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_15              0x4C1960
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_0              0x4C1964
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_1              0x4C1968
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_2              0x4C196C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_3              0x4C1970
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_4              0x4C1974
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_5              0x4C1978
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_6              0x4C197C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_7              0x4C1980
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_8              0x4C1984
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_9              0x4C1988
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_10             0x4C198C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_11             0x4C1990
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_12             0x4C1994
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_13             0x4C1998
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_14             0x4C199C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_15             0x4C19A0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_0               0x4C19A4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_1               0x4C19A8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_2               0x4C19AC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_3               0x4C19B0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_4               0x4C19B4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_5               0x4C19B8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_6               0x4C19BC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_7               0x4C19C0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_8               0x4C19C4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_9               0x4C19C8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_10              0x4C19CC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_11              0x4C19D0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_12              0x4C19D4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_13              0x4C19D8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_14              0x4C19DC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_15              0x4C19E0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_0              0x4C19E4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_1              0x4C19E8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_2              0x4C19EC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_3              0x4C19F0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_4              0x4C19F4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_5              0x4C19F8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_6              0x4C19FC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_7              0x4C1A00
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_8              0x4C1A04
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_9              0x4C1A08
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_10             0x4C1A0C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_11             0x4C1A10
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_12             0x4C1A14
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_13             0x4C1A18
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_14             0x4C1A1C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_15             0x4C1A20
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_HIT_AW                       0x4C1A64
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_HIT_AR                       0x4C1A68
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_HIT_AW                      0x4C1A6C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_HIT_AR                      0x4C1A70
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_CFG                                0x4C1B64
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_SHIFT                              0x4C1B68
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_EXPECTED_LAT_0                     0x4C1B6C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_EXPECTED_LAT_1                     0x4C1B70
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_EXPECTED_LAT_2                     0x4C1B74
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_EXPECTED_LAT_3                     0x4C1B78
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_EXPECTED_LAT_4                     0x4C1B7C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_EXPECTED_LAT_5                     0x4C1B80
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_EXPECTED_LAT_6                     0x4C1B84
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_EXPECTED_LAT_7                     0x4C1B88
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_TOKEN_0                            0x4C1BAC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_TOKEN_1                            0x4C1BB0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_TOKEN_2                            0x4C1BB4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_TOKEN_3                            0x4C1BB8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_TOKEN_4                            0x4C1BBC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_TOKEN_5                            0x4C1BC0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_TOKEN_6                            0x4C1BC4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_TOKEN_7                            0x4C1BC8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_BANK_ID_0                          0x4C1BEC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_BANK_ID_1                          0x4C1BF0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_BANK_ID_2                          0x4C1BF4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_BANK_ID_3                          0x4C1BF8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_BANK_ID_4                          0x4C1BFC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_BANK_ID_5                          0x4C1C00
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_BANK_ID_6                          0x4C1C04
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_BANK_ID_7                          0x4C1C08
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_WDT                                0x4C1C2C
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_WRAP               0x4C1C30
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_WRAP               0x4C1C34
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_WRAP               0x4C1C38
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_WRAP               0x4C1C3C
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_WRAP               0x4C1C40
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_WRAP               0x4C1C44
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_WRAP               0x4C1C48
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_WRAP               0x4C1C4C
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_CNT                0x4C1C50
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_CNT                0x4C1C54
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_CNT                0x4C1C58
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_CNT                0x4C1C5C
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_CNT                0x4C1C60
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_CNT                0x4C1C64
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_CNT                0x4C1C68
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_CNT                0x4C1C6C
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_WRAP               0x4C1C70
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_WRAP               0x4C1C74
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_WRAP               0x4C1C78
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_WRAP               0x4C1C7C
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_WRAP               0x4C1C80
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_WRAP               0x4C1C84
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_WRAP               0x4C1C88
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_WRAP               0x4C1C8C
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_CNT                0x4C1C90
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_CNT                0x4C1C94
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_CNT                0x4C1C98
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_CNT                0x4C1C9C
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_CNT                0x4C1CA0
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_CNT                0x4C1CA4
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_CNT                0x4C1CA8
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_CNT                0x4C1CAC
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_PC_SEL_0                        0x4C1CB0
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_PC_SEL_1                        0x4C1CB4
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_PC_SEL_2                        0x4C1CB8
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_PC_SEL_3                        0x4C1CBC
+
+#endif /* ASIC_REG_DMA_IF_W_N_DOWN_CH0_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_n_down_ch1_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_n_down_ch1_regs.h
new file mode 100644
index 000000000000..9236f4183084
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_n_down_ch1_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DMA_IF_W_N_DOWN_CH1_REGS_H_
+#define ASIC_REG_DMA_IF_W_N_DOWN_CH1_REGS_H_
+
+/*
+ *****************************************
+ *   DMA_IF_W_N_DOWN_CH1 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmDMA_IF_W_N_DOWN_CH1_PERM_SEL                               0x4C2108
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_0                          0x4C2114
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_1                          0x4C2118
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_2                          0x4C211C
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_3                          0x4C2120
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_4                          0x4C2124
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_5                          0x4C2128
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_6                          0x4C212C
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_7                          0x4C2130
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_8                          0x4C2134
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_9                          0x4C2138
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_10                         0x4C213C
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_11                         0x4C2140
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_12                         0x4C2144
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_13                         0x4C2148
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_14                         0x4C214C
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_15                         0x4C2150
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_16                         0x4C2154
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_17                         0x4C2158
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_18                         0x4C215C
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_19                         0x4C2160
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_20                         0x4C2164
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_21                         0x4C2168
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_22                         0x4C216C
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_23                         0x4C2170
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_24                         0x4C2174
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_25                         0x4C2178
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_26                         0x4C217C
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_27                         0x4C2180
+
+#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_0                         0x4C2184
+
+#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_1                         0x4C2188
+
+#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_2                         0x4C218C
+
+#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_3                         0x4C2190
+
+#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_4                         0x4C2194
+
+#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_5                         0x4C2198
+
+#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_6                         0x4C219C
+
+#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_7                         0x4C21A0
+
+#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_8                         0x4C21A4
+
+#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_9                         0x4C21A8
+
+#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_10                        0x4C21AC
+
+#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_11                        0x4C21B0
+
+#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_12                        0x4C21B4
+
+#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_13                        0x4C21B8
+
+#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_14                        0x4C21BC
+
+#define mmDMA_IF_W_N_DOWN_CH1_SCRAM_SRAM_EN                          0x4C226C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RL_HBM_EN                              0x4C2274
+
+#define mmDMA_IF_W_N_DOWN_CH1_RL_HBM_SAT                             0x4C2278
+
+#define mmDMA_IF_W_N_DOWN_CH1_RL_HBM_RST                             0x4C227C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RL_HBM_TIMEOUT                         0x4C2280
+
+#define mmDMA_IF_W_N_DOWN_CH1_SCRAM_HBM_EN                           0x4C2284
+
+#define mmDMA_IF_W_N_DOWN_CH1_RL_PCI_EN                              0x4C2288
+
+#define mmDMA_IF_W_N_DOWN_CH1_RL_PCI_SAT                             0x4C228C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RL_PCI_RST                             0x4C2290
+
+#define mmDMA_IF_W_N_DOWN_CH1_RL_PCI_TIMEOUT                         0x4C2294
+
+#define mmDMA_IF_W_N_DOWN_CH1_RL_SRAM_EN                             0x4C229C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RL_SRAM_SAT                            0x4C22A0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RL_SRAM_RST                            0x4C22A4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RL_SRAM_TIMEOUT                        0x4C22AC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RL_SRAM_RED                            0x4C22B4
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_HBM_EN                             0x4C22EC
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_PCI_EN                             0x4C22F0
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_HBM_WR_SIZE                        0x4C22F4
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_PCI_WR_SIZE                        0x4C22F8
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_PCI_CTR_SET_EN                  0x4C2404
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_PCI_CTR_SET                     0x4C2408
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_PCI_CTR_WRAP                    0x4C240C
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_PCI_CTR_CNT                     0x4C2410
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM_CTR_SET_EN                  0x4C2414
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM_CTR_SET                     0x4C2418
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_HBM_RD_SIZE                        0x4C241C
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_PCI_RD_SIZE                        0x4C2420
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_PCI_CTR_SET_EN                  0x4C2424
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_PCI_CTR_SET                     0x4C2428
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_PCI_CTR_WRAP                    0x4C242C
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_PCI_CTR_CNT                     0x4C2430
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM_CTR_SET_EN                  0x4C2434
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM_CTR_SET                     0x4C2438
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_SEL_0                           0x4C2450
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_SEL_1                           0x4C2454
+
+#define mmDMA_IF_W_N_DOWN_CH1_NON_LIN_EN                             0x4C2480
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_BANK_0                         0x4C2500
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_BANK_1                         0x4C2504
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_BANK_2                         0x4C2508
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_BANK_3                         0x4C250C
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_BANK_4                         0x4C2510
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_0                       0x4C2514
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_1                       0x4C2520
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_2                       0x4C2524
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_3                       0x4C2528
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_4                       0x4C252C
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_5                       0x4C2530
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_6                       0x4C2534
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_7                       0x4C2538
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_8                       0x4C253C
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_9                       0x4C2540
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_0                        0x4C2550
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_1                        0x4C2554
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_2                        0x4C2558
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_3                        0x4C255C
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_4                        0x4C2560
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_5                        0x4C2564
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_6                        0x4C2568
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_7                        0x4C256C
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_8                        0x4C2570
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_9                        0x4C2574
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_10                       0x4C2578
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_11                       0x4C257C
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_12                       0x4C2580
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_13                       0x4C2584
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_14                       0x4C2588
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_15                       0x4C258C
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_16                       0x4C2590
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_17                       0x4C2594
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_18                       0x4C2598
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0                0x4C25E4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_1                0x4C25E8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_2                0x4C25EC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_3                0x4C25F0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_4                0x4C25F4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_5                0x4C25F8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_6                0x4C25FC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_7                0x4C2600
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_8                0x4C2604
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_9                0x4C2608
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_10               0x4C260C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_11               0x4C2610
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_12               0x4C2614
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_13               0x4C2618
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_14               0x4C261C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_15               0x4C2620
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0               0x4C2624
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_1               0x4C2628
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_2               0x4C262C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_3               0x4C2630
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_4               0x4C2634
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_5               0x4C2638
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_6               0x4C263C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_7               0x4C2640
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_8               0x4C2644
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_9               0x4C2648
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_10              0x4C264C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_11              0x4C2650
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_12              0x4C2654
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_13              0x4C2658
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_14              0x4C265C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_15              0x4C2660
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0                0x4C2664
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_1                0x4C2668
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_2                0x4C266C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_3                0x4C2670
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_4                0x4C2674
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_5                0x4C2678
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_6                0x4C267C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_7                0x4C2680
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_8                0x4C2684
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_9                0x4C2688
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_10               0x4C268C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_11               0x4C2690
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_12               0x4C2694
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_13               0x4C2698
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_14               0x4C269C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_15               0x4C26A0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0               0x4C26A4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_1               0x4C26A8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_2               0x4C26AC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_3               0x4C26B0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_4               0x4C26B4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_5               0x4C26B8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_6               0x4C26BC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_7               0x4C26C0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_8               0x4C26C4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_9               0x4C26C8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_10              0x4C26CC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_11              0x4C26D0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_12              0x4C26D4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_13              0x4C26D8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_14              0x4C26DC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_15              0x4C26E0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_0               0x4C26E4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_1               0x4C26E8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_2               0x4C26EC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_3               0x4C26F0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_4               0x4C26F4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_5               0x4C26F8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_6               0x4C26FC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_7               0x4C2700
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_8               0x4C2704
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_9               0x4C2708
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_10              0x4C270C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_11              0x4C2710
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_12              0x4C2714
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_13              0x4C2718
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_14              0x4C271C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_15              0x4C2720
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_0              0x4C2724
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_1              0x4C2728
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_2              0x4C272C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_3              0x4C2730
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_4              0x4C2734
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_5              0x4C2738
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_6              0x4C273C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_7              0x4C2740
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_8              0x4C2744
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_9              0x4C2748
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_10             0x4C274C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_11             0x4C2750
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_12             0x4C2754
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_13             0x4C2758
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_14             0x4C275C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_15             0x4C2760
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_0               0x4C2764
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_1               0x4C2768
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_2               0x4C276C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_3               0x4C2770
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_4               0x4C2774
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_5               0x4C2778
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_6               0x4C277C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_7               0x4C2780
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_8               0x4C2784
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_9               0x4C2788
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_10              0x4C278C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_11              0x4C2790
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_12              0x4C2794
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_13              0x4C2798
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_14              0x4C279C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_15              0x4C27A0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_0              0x4C27A4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_1              0x4C27A8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_2              0x4C27AC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_3              0x4C27B0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_4              0x4C27B4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_5              0x4C27B8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_6              0x4C27BC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_7              0x4C27C0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_8              0x4C27C4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_9              0x4C27C8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_10             0x4C27CC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_11             0x4C27D0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_12             0x4C27D4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_13             0x4C27D8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_14             0x4C27DC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_15             0x4C27E0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0                0x4C2824
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_1                0x4C2828
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_2                0x4C282C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_3                0x4C2830
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_4                0x4C2834
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_5                0x4C2838
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_6                0x4C283C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_7                0x4C2840
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_8                0x4C2844
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_9                0x4C2848
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_10               0x4C284C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_11               0x4C2850
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_12               0x4C2854
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_13               0x4C2858
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_14               0x4C285C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_15               0x4C2860
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0               0x4C2864
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_1               0x4C2868
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_2               0x4C286C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_3               0x4C2870
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_4               0x4C2874
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_5               0x4C2878
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_6               0x4C287C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_7               0x4C2880
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_8               0x4C2884
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_9               0x4C2888
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_10              0x4C288C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_11              0x4C2890
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_12              0x4C2894
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_13              0x4C2898
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_14              0x4C289C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_15              0x4C28A0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0                0x4C28A4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_1                0x4C28A8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_2                0x4C28AC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_3                0x4C28B0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_4                0x4C28B4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_5                0x4C28B8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_6                0x4C28BC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_7                0x4C28C0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_8                0x4C28C4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_9                0x4C28C8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_10               0x4C28CC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_11               0x4C28D0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_12               0x4C28D4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_13               0x4C28D8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_14               0x4C28DC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_15               0x4C28E0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0               0x4C28E4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_1               0x4C28E8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_2               0x4C28EC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_3               0x4C28F0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_4               0x4C28F4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_5               0x4C28F8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_6               0x4C28FC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_7               0x4C2900
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_8               0x4C2904
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_9               0x4C2908
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_10              0x4C290C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_11              0x4C2910
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_12              0x4C2914
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_13              0x4C2918
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_14              0x4C291C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_15              0x4C2920
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_0               0x4C2924
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_1               0x4C2928
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_2               0x4C292C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_3               0x4C2930
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_4               0x4C2934
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_5               0x4C2938
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_6               0x4C293C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_7               0x4C2940
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_8               0x4C2944
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_9               0x4C2948
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_10              0x4C294C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_11              0x4C2950
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_12              0x4C2954
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_13              0x4C2958
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_14              0x4C295C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_15              0x4C2960
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_0              0x4C2964
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_1              0x4C2968
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_2              0x4C296C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_3              0x4C2970
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_4              0x4C2974
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_5              0x4C2978
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_6              0x4C297C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_7              0x4C2980
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_8              0x4C2984
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_9              0x4C2988
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_10             0x4C298C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_11             0x4C2990
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_12             0x4C2994
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_13             0x4C2998
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_14             0x4C299C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_15             0x4C29A0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_0               0x4C29A4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_1               0x4C29A8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_2               0x4C29AC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_3               0x4C29B0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_4               0x4C29B4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_5               0x4C29B8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_6               0x4C29BC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_7               0x4C29C0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_8               0x4C29C4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_9               0x4C29C8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_10              0x4C29CC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_11              0x4C29D0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_12              0x4C29D4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_13              0x4C29D8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_14              0x4C29DC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_15              0x4C29E0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_0              0x4C29E4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_1              0x4C29E8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_2              0x4C29EC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_3              0x4C29F0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_4              0x4C29F4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_5              0x4C29F8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_6              0x4C29FC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_7              0x4C2A00
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_8              0x4C2A04
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_9              0x4C2A08
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_10             0x4C2A0C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_11             0x4C2A10
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_12             0x4C2A14
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_13             0x4C2A18
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_14             0x4C2A1C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_15             0x4C2A20
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_HIT_AW                       0x4C2A64
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_HIT_AR                       0x4C2A68
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_HIT_AW                      0x4C2A6C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_HIT_AR                      0x4C2A70
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_CFG                                0x4C2B64
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_SHIFT                              0x4C2B68
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_0                     0x4C2B6C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_1                     0x4C2B70
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_2                     0x4C2B74
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_3                     0x4C2B78
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_4                     0x4C2B7C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_5                     0x4C2B80
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_6                     0x4C2B84
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_7                     0x4C2B88
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_0                            0x4C2BAC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_1                            0x4C2BB0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_2                            0x4C2BB4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_3                            0x4C2BB8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_4                            0x4C2BBC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_5                            0x4C2BC0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_6                            0x4C2BC4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_7                            0x4C2BC8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_0                          0x4C2BEC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_1                          0x4C2BF0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_2                          0x4C2BF4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_3                          0x4C2BF8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_4                          0x4C2BFC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_5                          0x4C2C00
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_6                          0x4C2C04
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_7                          0x4C2C08
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_WDT                                0x4C2C2C
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_WRAP               0x4C2C30
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_WRAP               0x4C2C34
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_WRAP               0x4C2C38
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_WRAP               0x4C2C3C
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_WRAP               0x4C2C40
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_WRAP               0x4C2C44
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_WRAP               0x4C2C48
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_WRAP               0x4C2C4C
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_CNT                0x4C2C50
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_CNT                0x4C2C54
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_CNT                0x4C2C58
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_CNT                0x4C2C5C
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_CNT                0x4C2C60
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_CNT                0x4C2C64
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_CNT                0x4C2C68
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_CNT                0x4C2C6C
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_WRAP               0x4C2C70
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_WRAP               0x4C2C74
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_WRAP               0x4C2C78
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_WRAP               0x4C2C7C
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_WRAP               0x4C2C80
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_WRAP               0x4C2C84
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_WRAP               0x4C2C88
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_WRAP               0x4C2C8C
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_CNT                0x4C2C90
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_CNT                0x4C2C94
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_CNT                0x4C2C98
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_CNT                0x4C2C9C
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_CNT                0x4C2CA0
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_CNT                0x4C2CA4
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_CNT                0x4C2CA8
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_CNT                0x4C2CAC
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_PC_SEL_0                        0x4C2CB0
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_PC_SEL_1                        0x4C2CB4
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_PC_SEL_2                        0x4C2CB8
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_PC_SEL_3                        0x4C2CBC
+
+#endif /* ASIC_REG_DMA_IF_W_N_DOWN_CH1_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_n_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_n_regs.h
new file mode 100644
index 000000000000..da60893a5fab
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_n_regs.h
@@ -0,0 +1,860 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DMA_IF_W_N_REGS_H_
+#define ASIC_REG_DMA_IF_W_N_REGS_H_
+
+/*
+ *****************************************
+ *   DMA_IF_W_N (Prototype: DMA_IF)
+ *****************************************
+ */
+
+#define mmDMA_IF_W_N_HBM0_WR_CRED_CNT                                0x4C0000
+
+#define mmDMA_IF_W_N_HBM1_WR_CRED_CNT                                0x4C0004
+
+#define mmDMA_IF_W_N_HBM0_RD_CRED_CNT                                0x4C0008
+
+#define mmDMA_IF_W_N_HBM1_RD_CRED_CNT                                0x4C000C
+
+#define mmDMA_IF_W_N_HBM_LIMITER_0                                   0x4C0030
+
+#define mmDMA_IF_W_N_HBM_LIMITER_1                                   0x4C0034
+
+#define mmDMA_IF_W_N_HBM_LIMITER_2                                   0x4C0038
+
+#define mmDMA_IF_W_N_HBM_LIMITER_3                                   0x4C003C
+
+#define mmDMA_IF_W_N_HBM_ALMOST_EN_0                                 0x4C0040
+
+#define mmDMA_IF_W_N_HBM_ALMOST_EN_1                                 0x4C0044
+
+#define mmDMA_IF_W_N_HBM_CRED_EN_0                                   0x4C0050
+
+#define mmDMA_IF_W_N_HBM_CRED_EN_1                                   0x4C0054
+
+#define mmDMA_IF_W_N_SOB_MIN_RPROT_0                                 0x4C0100
+
+#define mmDMA_IF_W_N_SOB_MIN_RPROT_1                                 0x4C0104
+
+#define mmDMA_IF_W_N_SOB_MIN_RPROT_2                                 0x4C0108
+
+#define mmDMA_IF_W_N_SOB_MIN_RPROT_3                                 0x4C010C
+
+#define mmDMA_IF_W_N_SOB_MIN_RPROT_4                                 0x4C0110
+
+#define mmDMA_IF_W_N_SOB_MIN_RPROT_5                                 0x4C0114
+
+#define mmDMA_IF_W_N_SOB_MIN_RPROT_6                                 0x4C0118
+
+#define mmDMA_IF_W_N_SOB_MIN_RPROT_7                                 0x4C011C
+
+#define mmDMA_IF_W_N_SOB_MIN_RPROT_8                                 0x4C0120
+
+#define mmDMA_IF_W_N_SOB_MIN_RPROT_9                                 0x4C0124
+
+#define mmDMA_IF_W_N_SOB_MIN_RPROT_10                                0x4C0128
+
+#define mmDMA_IF_W_N_SOB_MIN_RPROT_11                                0x4C012C
+
+#define mmDMA_IF_W_N_SOB_MIN_RPROT_12                                0x4C0130
+
+#define mmDMA_IF_W_N_SOB_MIN_RPROT_13                                0x4C0134
+
+#define mmDMA_IF_W_N_SOB_MIN_RPROT_14                                0x4C0138
+
+#define mmDMA_IF_W_N_SOB_MIN_RPROT_15                                0x4C013C
+
+#define mmDMA_IF_W_N_SOB_MAX_RPROT_0                                 0x4C0140
+
+#define mmDMA_IF_W_N_SOB_MAX_RPROT_1                                 0x4C0144
+
+#define mmDMA_IF_W_N_SOB_MAX_RPROT_2                                 0x4C0148
+
+#define mmDMA_IF_W_N_SOB_MAX_RPROT_3                                 0x4C014C
+
+#define mmDMA_IF_W_N_SOB_MAX_RPROT_4                                 0x4C0150
+
+#define mmDMA_IF_W_N_SOB_MAX_RPROT_5                                 0x4C0154
+
+#define mmDMA_IF_W_N_SOB_MAX_RPROT_6                                 0x4C0158
+
+#define mmDMA_IF_W_N_SOB_MAX_RPROT_7                                 0x4C015C
+
+#define mmDMA_IF_W_N_SOB_MAX_RPROT_8                                 0x4C0160
+
+#define mmDMA_IF_W_N_SOB_MAX_RPROT_9                                 0x4C0164
+
+#define mmDMA_IF_W_N_SOB_MAX_RPROT_10                                0x4C0168
+
+#define mmDMA_IF_W_N_SOB_MAX_RPROT_11                                0x4C016C
+
+#define mmDMA_IF_W_N_SOB_MAX_RPROT_12                                0x4C0170
+
+#define mmDMA_IF_W_N_SOB_MAX_RPROT_13                                0x4C0174
+
+#define mmDMA_IF_W_N_SOB_MAX_RPROT_14                                0x4C0178
+
+#define mmDMA_IF_W_N_SOB_MAX_RPROT_15                                0x4C017C
+
+#define mmDMA_IF_W_N_SOB_MIN_WPROT_0                                 0x4C0180
+
+#define mmDMA_IF_W_N_SOB_MIN_WPROT_1                                 0x4C0184
+
+#define mmDMA_IF_W_N_SOB_MIN_WPROT_2                                 0x4C0188
+
+#define mmDMA_IF_W_N_SOB_MIN_WPROT_3                                 0x4C018C
+
+#define mmDMA_IF_W_N_SOB_MIN_WPROT_4                                 0x4C0190
+
+#define mmDMA_IF_W_N_SOB_MIN_WPROT_5                                 0x4C0194
+
+#define mmDMA_IF_W_N_SOB_MIN_WPROT_6                                 0x4C0198
+
+#define mmDMA_IF_W_N_SOB_MIN_WPROT_7                                 0x4C019C
+
+#define mmDMA_IF_W_N_SOB_MIN_WPROT_8                                 0x4C01A0
+
+#define mmDMA_IF_W_N_SOB_MIN_WPROT_9                                 0x4C01A4
+
+#define mmDMA_IF_W_N_SOB_MIN_WPROT_10                                0x4C01A8
+
+#define mmDMA_IF_W_N_SOB_MIN_WPROT_11                                0x4C01AC
+
+#define mmDMA_IF_W_N_SOB_MIN_WPROT_12                                0x4C01B0
+
+#define mmDMA_IF_W_N_SOB_MIN_WPROT_13                                0x4C01B4
+
+#define mmDMA_IF_W_N_SOB_MIN_WPROT_14                                0x4C01B8
+
+#define mmDMA_IF_W_N_SOB_MIN_WPROT_15                                0x4C01BC
+
+#define mmDMA_IF_W_N_SOB_MAX_WPROT_0                                 0x4C01C0
+
+#define mmDMA_IF_W_N_SOB_MAX_WPROT_1                                 0x4C01C4
+
+#define mmDMA_IF_W_N_SOB_MAX_WPROT_2                                 0x4C01C8
+
+#define mmDMA_IF_W_N_SOB_MAX_WPROT_3                                 0x4C01CC
+
+#define mmDMA_IF_W_N_SOB_MAX_WPROT_4                                 0x4C01D0
+
+#define mmDMA_IF_W_N_SOB_MAX_WPROT_5                                 0x4C01D4
+
+#define mmDMA_IF_W_N_SOB_MAX_WPROT_6                                 0x4C01D8
+
+#define mmDMA_IF_W_N_SOB_MAX_WPROT_7                                 0x4C01DC
+
+#define mmDMA_IF_W_N_SOB_MAX_WPROT_8                                 0x4C01E0
+
+#define mmDMA_IF_W_N_SOB_MAX_WPROT_9                                 0x4C01E4
+
+#define mmDMA_IF_W_N_SOB_MAX_WPROT_10                                0x4C01E8
+
+#define mmDMA_IF_W_N_SOB_MAX_WPROT_11                                0x4C01EC
+
+#define mmDMA_IF_W_N_SOB_MAX_WPROT_12                                0x4C01F0
+
+#define mmDMA_IF_W_N_SOB_MAX_WPROT_13                                0x4C01F4
+
+#define mmDMA_IF_W_N_SOB_MAX_WPROT_14                                0x4C01F8
+
+#define mmDMA_IF_W_N_SOB_MAX_WPROT_15                                0x4C01FC
+
+#define mmDMA_IF_W_N_SOB_MIN_RPRIV_0                                 0x4C0200
+
+#define mmDMA_IF_W_N_SOB_MIN_RPRIV_1                                 0x4C0204
+
+#define mmDMA_IF_W_N_SOB_MIN_RPRIV_2                                 0x4C0208
+
+#define mmDMA_IF_W_N_SOB_MIN_RPRIV_3                                 0x4C020C
+
+#define mmDMA_IF_W_N_SOB_MIN_RPRIV_4                                 0x4C0210
+
+#define mmDMA_IF_W_N_SOB_MIN_RPRIV_5                                 0x4C0214
+
+#define mmDMA_IF_W_N_SOB_MIN_RPRIV_6                                 0x4C0218
+
+#define mmDMA_IF_W_N_SOB_MIN_RPRIV_7                                 0x4C021C
+
+#define mmDMA_IF_W_N_SOB_MIN_RPRIV_8                                 0x4C0220
+
+#define mmDMA_IF_W_N_SOB_MIN_RPRIV_9                                 0x4C0224
+
+#define mmDMA_IF_W_N_SOB_MIN_RPRIV_10                                0x4C0228
+
+#define mmDMA_IF_W_N_SOB_MIN_RPRIV_11                                0x4C022C
+
+#define mmDMA_IF_W_N_SOB_MIN_RPRIV_12                                0x4C0230
+
+#define mmDMA_IF_W_N_SOB_MIN_RPRIV_13                                0x4C0234
+
+#define mmDMA_IF_W_N_SOB_MIN_RPRIV_14                                0x4C0238
+
+#define mmDMA_IF_W_N_SOB_MIN_RPRIV_15                                0x4C023C
+
+#define mmDMA_IF_W_N_SOB_MAX_RPRIV_0                                 0x4C0240
+
+#define mmDMA_IF_W_N_SOB_MAX_RPRIV_1                                 0x4C0244
+
+#define mmDMA_IF_W_N_SOB_MAX_RPRIV_2                                 0x4C0248
+
+#define mmDMA_IF_W_N_SOB_MAX_RPRIV_3                                 0x4C024C
+
+#define mmDMA_IF_W_N_SOB_MAX_RPRIV_4                                 0x4C0250
+
+#define mmDMA_IF_W_N_SOB_MAX_RPRIV_5                                 0x4C0254
+
+#define mmDMA_IF_W_N_SOB_MAX_RPRIV_6                                 0x4C0258
+
+#define mmDMA_IF_W_N_SOB_MAX_RPRIV_7                                 0x4C025C
+
+#define mmDMA_IF_W_N_SOB_MAX_RPRIV_8                                 0x4C0260
+
+#define mmDMA_IF_W_N_SOB_MAX_RPRIV_9                                 0x4C0264
+
+#define mmDMA_IF_W_N_SOB_MAX_RPRIV_10                                0x4C0268
+
+#define mmDMA_IF_W_N_SOB_MAX_RPRIV_11                                0x4C026C
+
+#define mmDMA_IF_W_N_SOB_MAX_RPRIV_12                                0x4C0270
+
+#define mmDMA_IF_W_N_SOB_MAX_RPRIV_13                                0x4C0274
+
+#define mmDMA_IF_W_N_SOB_MAX_RPRIV_14                                0x4C0278
+
+#define mmDMA_IF_W_N_SOB_MAX_RPRIV_15                                0x4C027C
+
+#define mmDMA_IF_W_N_SOB_MIN_WPRIV_0                                 0x4C0280
+
+#define mmDMA_IF_W_N_SOB_MIN_WPRIV_1                                 0x4C0284
+
+#define mmDMA_IF_W_N_SOB_MIN_WPRIV_2                                 0x4C0288
+
+#define mmDMA_IF_W_N_SOB_MIN_WPRIV_3                                 0x4C028C
+
+#define mmDMA_IF_W_N_SOB_MIN_WPRIV_4                                 0x4C0290
+
+#define mmDMA_IF_W_N_SOB_MIN_WPRIV_5                                 0x4C0294
+
+#define mmDMA_IF_W_N_SOB_MIN_WPRIV_6                                 0x4C0298
+
+#define mmDMA_IF_W_N_SOB_MIN_WPRIV_7                                 0x4C029C
+
+#define mmDMA_IF_W_N_SOB_MIN_WPRIV_8                                 0x4C02A0
+
+#define mmDMA_IF_W_N_SOB_MIN_WPRIV_9                                 0x4C02A4
+
+#define mmDMA_IF_W_N_SOB_MIN_WPRIV_10                                0x4C02A8
+
+#define mmDMA_IF_W_N_SOB_MIN_WPRIV_11                                0x4C02AC
+
+#define mmDMA_IF_W_N_SOB_MIN_WPRIV_12                                0x4C02B0
+
+#define mmDMA_IF_W_N_SOB_MIN_WPRIV_13                                0x4C02B4
+
+#define mmDMA_IF_W_N_SOB_MIN_WPRIV_14                                0x4C02B8
+
+#define mmDMA_IF_W_N_SOB_MIN_WPRIV_15                                0x4C02BC
+
+#define mmDMA_IF_W_N_SOB_MAX_WPRIV_0                                 0x4C02C0
+
+#define mmDMA_IF_W_N_SOB_MAX_WPRIV_1                                 0x4C02C4
+
+#define mmDMA_IF_W_N_SOB_MAX_WPRIV_2                                 0x4C02C8
+
+#define mmDMA_IF_W_N_SOB_MAX_WPRIV_3                                 0x4C02CC
+
+#define mmDMA_IF_W_N_SOB_MAX_WPRIV_4                                 0x4C02D0
+
+#define mmDMA_IF_W_N_SOB_MAX_WPRIV_5                                 0x4C02D4
+
+#define mmDMA_IF_W_N_SOB_MAX_WPRIV_6                                 0x4C02D8
+
+#define mmDMA_IF_W_N_SOB_MAX_WPRIV_7                                 0x4C02DC
+
+#define mmDMA_IF_W_N_SOB_MAX_WPRIV_8                                 0x4C02E0
+
+#define mmDMA_IF_W_N_SOB_MAX_WPRIV_9                                 0x4C02E4
+
+#define mmDMA_IF_W_N_SOB_MAX_WPRIV_10                                0x4C02E8
+
+#define mmDMA_IF_W_N_SOB_MAX_WPRIV_11                                0x4C02EC
+
+#define mmDMA_IF_W_N_SOB_MAX_WPRIV_12                                0x4C02F0
+
+#define mmDMA_IF_W_N_SOB_MAX_WPRIV_13                                0x4C02F4
+
+#define mmDMA_IF_W_N_SOB_MAX_WPRIV_14                                0x4C02F8
+
+#define mmDMA_IF_W_N_SOB_MAX_WPRIV_15                                0x4C02FC
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPROT_0                                0x4C0300
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPROT_1                                0x4C0304
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPROT_2                                0x4C0308
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPROT_3                                0x4C030C
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPROT_4                                0x4C0310
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPROT_5                                0x4C0314
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPROT_6                                0x4C0318
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPROT_7                                0x4C031C
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPROT_8                                0x4C0320
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPROT_9                                0x4C0324
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPROT_10                               0x4C0328
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPROT_11                               0x4C032C
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPROT_12                               0x4C0330
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPROT_13                               0x4C0334
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPROT_14                               0x4C0338
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPROT_15                               0x4C033C
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPROT_0                                0x4C0340
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPROT_1                                0x4C0344
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPROT_2                                0x4C0348
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPROT_3                                0x4C034C
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPROT_4                                0x4C0350
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPROT_5                                0x4C0354
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPROT_6                                0x4C0358
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPROT_7                                0x4C035C
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPROT_8                                0x4C0360
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPROT_9                                0x4C0364
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPROT_10                               0x4C0368
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPROT_11                               0x4C036C
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPROT_12                               0x4C0370
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPROT_13                               0x4C0374
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPROT_14                               0x4C0378
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPROT_15                               0x4C037C
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPROT_0                                0x4C0380
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPROT_1                                0x4C0384
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPROT_2                                0x4C0388
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPROT_3                                0x4C038C
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPROT_4                                0x4C0390
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPROT_5                                0x4C0394
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPROT_6                                0x4C0398
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPROT_7                                0x4C039C
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPROT_8                                0x4C03A0
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPROT_9                                0x4C03A4
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPROT_10                               0x4C03A8
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPROT_11                               0x4C03AC
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPROT_12                               0x4C03B0
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPROT_13                               0x4C03B4
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPROT_14                               0x4C03B8
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPROT_15                               0x4C03BC
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPROT_0                                0x4C03C0
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPROT_1                                0x4C03C4
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPROT_2                                0x4C03C8
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPROT_3                                0x4C03CC
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPROT_4                                0x4C03D0
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPROT_5                                0x4C03D4
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPROT_6                                0x4C03D8
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPROT_7                                0x4C03DC
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPROT_8                                0x4C03E0
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPROT_9                                0x4C03E4
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPROT_10                               0x4C03E8
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPROT_11                               0x4C03EC
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPROT_12                               0x4C03F0
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPROT_13                               0x4C03F4
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPROT_14                               0x4C03F8
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPROT_15                               0x4C03FC
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_0                                0x4C0400
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_1                                0x4C0404
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_2                                0x4C0408
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_3                                0x4C040C
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_4                                0x4C0410
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_5                                0x4C0414
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_6                                0x4C0418
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_7                                0x4C041C
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_8                                0x4C0420
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_9                                0x4C0424
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_10                               0x4C0428
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_11                               0x4C042C
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_12                               0x4C0430
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_13                               0x4C0434
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_14                               0x4C0438
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_15                               0x4C043C
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_0                                0x4C0440
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_1                                0x4C0444
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_2                                0x4C0448
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_3                                0x4C044C
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_4                                0x4C0450
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_5                                0x4C0454
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_6                                0x4C0458
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_7                                0x4C045C
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_8                                0x4C0460
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_9                                0x4C0464
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_10                               0x4C0468
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_11                               0x4C046C
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_12                               0x4C0470
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_13                               0x4C0474
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_14                               0x4C0478
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_15                               0x4C047C
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_0                                0x4C0480
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_1                                0x4C0484
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_2                                0x4C0488
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_3                                0x4C048C
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_4                                0x4C0490
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_5                                0x4C0494
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_6                                0x4C0498
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_7                                0x4C049C
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_8                                0x4C04A0
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_9                                0x4C04A4
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_10                               0x4C04A8
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_11                               0x4C04AC
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_12                               0x4C04B0
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_13                               0x4C04B4
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_14                               0x4C04B8
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_15                               0x4C04BC
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_0                                0x4C04C0
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_1                                0x4C04C4
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_2                                0x4C04C8
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_3                                0x4C04CC
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_4                                0x4C04D0
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_5                                0x4C04D4
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_6                                0x4C04D8
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_7                                0x4C04DC
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_8                                0x4C04E0
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_9                                0x4C04E4
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_10                               0x4C04E8
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_11                               0x4C04EC
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_12                               0x4C04F0
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_13                               0x4C04F4
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_14                               0x4C04F8
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_15                               0x4C04FC
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPROT_0                                0x4C0500
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPROT_1                                0x4C0504
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPROT_2                                0x4C0508
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPROT_3                                0x4C050C
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPROT_4                                0x4C0510
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPROT_5                                0x4C0514
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPROT_6                                0x4C0518
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPROT_7                                0x4C051C
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPROT_8                                0x4C0520
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPROT_9                                0x4C0524
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPROT_10                               0x4C0528
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPROT_11                               0x4C052C
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPROT_12                               0x4C0530
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPROT_13                               0x4C0534
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPROT_14                               0x4C0538
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPROT_15                               0x4C053C
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPROT_0                                0x4C0540
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPROT_1                                0x4C0544
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPROT_2                                0x4C0548
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPROT_3                                0x4C054C
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPROT_4                                0x4C0550
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPROT_5                                0x4C0554
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPROT_6                                0x4C0558
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPROT_7                                0x4C055C
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPROT_8                                0x4C0560
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPROT_9                                0x4C0564
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPROT_10                               0x4C0568
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPROT_11                               0x4C056C
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPROT_12                               0x4C0570
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPROT_13                               0x4C0574
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPROT_14                               0x4C0578
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPROT_15                               0x4C057C
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPROT_0                                0x4C0580
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPROT_1                                0x4C0584
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPROT_2                                0x4C0588
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPROT_3                                0x4C058C
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPROT_4                                0x4C0590
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPROT_5                                0x4C0594
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPROT_6                                0x4C0598
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPROT_7                                0x4C059C
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPROT_8                                0x4C05A0
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPROT_9                                0x4C05A4
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPROT_10                               0x4C05A8
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPROT_11                               0x4C05AC
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPROT_12                               0x4C05B0
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPROT_13                               0x4C05B4
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPROT_14                               0x4C05B8
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPROT_15                               0x4C05BC
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPROT_0                                0x4C05C0
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPROT_1                                0x4C05C4
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPROT_2                                0x4C05C8
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPROT_3                                0x4C05CC
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPROT_4                                0x4C05D0
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPROT_5                                0x4C05D4
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPROT_6                                0x4C05D8
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPROT_7                                0x4C05DC
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPROT_8                                0x4C05E0
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPROT_9                                0x4C05E4
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPROT_10                               0x4C05E8
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPROT_11                               0x4C05EC
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPROT_12                               0x4C05F0
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPROT_13                               0x4C05F4
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPROT_14                               0x4C05F8
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPROT_15                               0x4C05FC
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_0                                0x4C0600
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_1                                0x4C0604
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_2                                0x4C0608
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_3                                0x4C060C
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_4                                0x4C0610
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_5                                0x4C0614
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_6                                0x4C0618
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_7                                0x4C061C
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_8                                0x4C0620
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_9                                0x4C0624
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_10                               0x4C0628
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_11                               0x4C062C
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_12                               0x4C0630
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_13                               0x4C0634
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_14                               0x4C0638
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_15                               0x4C063C
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_0                                0x4C0640
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_1                                0x4C0644
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_2                                0x4C0648
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_3                                0x4C064C
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_4                                0x4C0650
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_5                                0x4C0654
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_6                                0x4C0658
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_7                                0x4C065C
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_8                                0x4C0660
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_9                                0x4C0664
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_10                               0x4C0668
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_11                               0x4C066C
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_12                               0x4C0670
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_13                               0x4C0674
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_14                               0x4C0678
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_15                               0x4C067C
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_0                                0x4C0680
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_1                                0x4C0684
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_2                                0x4C0688
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_3                                0x4C068C
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_4                                0x4C0690
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_5                                0x4C0694
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_6                                0x4C0698
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_7                                0x4C069C
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_8                                0x4C06A0
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_9                                0x4C06A4
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_10                               0x4C06A8
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_11                               0x4C06AC
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_12                               0x4C06B0
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_13                               0x4C06B4
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_14                               0x4C06B8
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_15                               0x4C06BC
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_0                                0x4C06C0
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_1                                0x4C06C4
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_2                                0x4C06C8
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_3                                0x4C06CC
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_4                                0x4C06D0
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_5                                0x4C06D4
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_6                                0x4C06D8
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_7                                0x4C06DC
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_8                                0x4C06E0
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_9                                0x4C06E4
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_10                               0x4C06E8
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_11                               0x4C06EC
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_12                               0x4C06F0
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_13                               0x4C06F4
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_14                               0x4C06F8
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_15                               0x4C06FC
+
+#define mmDMA_IF_W_N_SOB_HIT_RPROT                                   0x4C0700
+
+#define mmDMA_IF_W_N_SOB_HIT_WPROT                                   0x4C0704
+
+#define mmDMA_IF_W_N_SOB_HIT_RPRIV                                   0x4C070C
+
+#define mmDMA_IF_W_N_SOB_HIT_WPRIV                                   0x4C0710
+
+#define mmDMA_IF_W_N_DMA0_HIT_RPROT                                  0x4C071C
+
+#define mmDMA_IF_W_N_DMA0_HIT_WPROT                                  0x4C0720
+
+#define mmDMA_IF_W_N_DMA0_HIT_RPRIV                                  0x4C0724
+
+#define mmDMA_IF_W_N_DMA0_HIT_WPRIV                                  0x4C0728
+
+#define mmDMA_IF_W_N_DMA1_HIT_RPROT                                  0x4C0730
+
+#define mmDMA_IF_W_N_DMA1_HIT_WPROT                                  0x4C0734
+
+#define mmDMA_IF_W_N_DMA1_HIT_RPRIV                                  0x4C0738
+
+#define mmDMA_IF_W_N_DMA1_HIT_WPRIV                                  0x4C073C
+
+#define mmDMA_IF_W_N_HBM_BIN                                         0x4C0800
+
+#define mmDMA_IF_W_N_MME_BIN                                         0x4C0804
+
+#define mmDMA_IF_W_N_TPC_BIN                                         0x4C0808
+
+#define mmDMA_IF_W_N_DMA_BIN                                         0x4C080C
+
+#define mmDMA_IF_W_N_SOB_CG_EN                                       0x4C0810
+
+#define mmDMA_IF_W_N_HBM_I2C_ADDR_0                                  0x4C0820
+
+#define mmDMA_IF_W_N_HBM_I2C_ADDR_1                                  0x4C0824
+
+#define mmDMA_IF_W_N_HBM_I2C_ADDR_2                                  0x4C0828
+
+#define mmDMA_IF_W_N_HBM_I2C_ADDR_3                                  0x4C082C
+
+#define mmDMA_IF_W_N_HBM_I2C_ADDR_4                                  0x4C0830
+
+#define mmDMA_IF_W_N_HBM_MISC                                        0x4C0834
+
+#endif /* ASIC_REG_DMA_IF_W_N_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_s_down_ch0_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_s_down_ch0_regs.h
new file mode 100644
index 000000000000..56ffc920d58a
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_s_down_ch0_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DMA_IF_W_S_DOWN_CH0_REGS_H_
+#define ASIC_REG_DMA_IF_W_S_DOWN_CH0_REGS_H_
+
+/*
+ *****************************************
+ *   DMA_IF_W_S_DOWN_CH0 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmDMA_IF_W_S_DOWN_CH0_PERM_SEL                               0x481108
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_0                          0x481114
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_1                          0x481118
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_2                          0x48111C
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_3                          0x481120
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_4                          0x481124
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_5                          0x481128
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_6                          0x48112C
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_7                          0x481130
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_8                          0x481134
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_9                          0x481138
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_10                         0x48113C
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_11                         0x481140
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_12                         0x481144
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_13                         0x481148
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_14                         0x48114C
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_15                         0x481150
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_16                         0x481154
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_17                         0x481158
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_18                         0x48115C
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_19                         0x481160
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_20                         0x481164
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_21                         0x481168
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_22                         0x48116C
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_23                         0x481170
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_24                         0x481174
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_25                         0x481178
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_26                         0x48117C
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_27                         0x481180
+
+#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_0                         0x481184
+
+#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_1                         0x481188
+
+#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_2                         0x48118C
+
+#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_3                         0x481190
+
+#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_4                         0x481194
+
+#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_5                         0x481198
+
+#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_6                         0x48119C
+
+#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_7                         0x4811A0
+
+#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_8                         0x4811A4
+
+#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_9                         0x4811A8
+
+#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_10                        0x4811AC
+
+#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_11                        0x4811B0
+
+#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_12                        0x4811B4
+
+#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_13                        0x4811B8
+
+#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_14                        0x4811BC
+
+#define mmDMA_IF_W_S_DOWN_CH0_SCRAM_SRAM_EN                          0x48126C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RL_HBM_EN                              0x481274
+
+#define mmDMA_IF_W_S_DOWN_CH0_RL_HBM_SAT                             0x481278
+
+#define mmDMA_IF_W_S_DOWN_CH0_RL_HBM_RST                             0x48127C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RL_HBM_TIMEOUT                         0x481280
+
+#define mmDMA_IF_W_S_DOWN_CH0_SCRAM_HBM_EN                           0x481284
+
+#define mmDMA_IF_W_S_DOWN_CH0_RL_PCI_EN                              0x481288
+
+#define mmDMA_IF_W_S_DOWN_CH0_RL_PCI_SAT                             0x48128C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RL_PCI_RST                             0x481290
+
+#define mmDMA_IF_W_S_DOWN_CH0_RL_PCI_TIMEOUT                         0x481294
+
+#define mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_EN                             0x48129C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_SAT                            0x4812A0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_RST                            0x4812A4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_TIMEOUT                        0x4812AC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_RED                            0x4812B4
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_HBM_EN                             0x4812EC
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_PCI_EN                             0x4812F0
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_HBM_WR_SIZE                        0x4812F4
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_PCI_WR_SIZE                        0x4812F8
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_PCI_CTR_SET_EN                  0x481404
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_PCI_CTR_SET                     0x481408
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_PCI_CTR_WRAP                    0x48140C
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_PCI_CTR_CNT                     0x481410
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM_CTR_SET_EN                  0x481414
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM_CTR_SET                     0x481418
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_HBM_RD_SIZE                        0x48141C
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_PCI_RD_SIZE                        0x481420
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_PCI_CTR_SET_EN                  0x481424
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_PCI_CTR_SET                     0x481428
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_PCI_CTR_WRAP                    0x48142C
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_PCI_CTR_CNT                     0x481430
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM_CTR_SET_EN                  0x481434
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM_CTR_SET                     0x481438
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_SEL_0                           0x481450
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_SEL_1                           0x481454
+
+#define mmDMA_IF_W_S_DOWN_CH0_NON_LIN_EN                             0x481480
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_BANK_0                         0x481500
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_BANK_1                         0x481504
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_BANK_2                         0x481508
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_BANK_3                         0x48150C
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_BANK_4                         0x481510
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_0                       0x481514
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_1                       0x481520
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_2                       0x481524
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_3                       0x481528
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_4                       0x48152C
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_5                       0x481530
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_6                       0x481534
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_7                       0x481538
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_8                       0x48153C
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_9                       0x481540
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_0                        0x481550
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_1                        0x481554
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_2                        0x481558
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_3                        0x48155C
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_4                        0x481560
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_5                        0x481564
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_6                        0x481568
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_7                        0x48156C
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_8                        0x481570
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_9                        0x481574
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_10                       0x481578
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_11                       0x48157C
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_12                       0x481580
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_13                       0x481584
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_14                       0x481588
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_15                       0x48158C
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_16                       0x481590
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_17                       0x481594
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_18                       0x481598
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_0                0x4815E4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_1                0x4815E8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_2                0x4815EC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_3                0x4815F0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_4                0x4815F4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_5                0x4815F8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_6                0x4815FC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_7                0x481600
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_8                0x481604
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_9                0x481608
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_10               0x48160C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_11               0x481610
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_12               0x481614
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_13               0x481618
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_14               0x48161C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_15               0x481620
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_0               0x481624
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_1               0x481628
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_2               0x48162C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_3               0x481630
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_4               0x481634
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_5               0x481638
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_6               0x48163C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_7               0x481640
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_8               0x481644
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_9               0x481648
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_10              0x48164C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_11              0x481650
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_12              0x481654
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_13              0x481658
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_14              0x48165C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_15              0x481660
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_0                0x481664
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_1                0x481668
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_2                0x48166C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_3                0x481670
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_4                0x481674
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_5                0x481678
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_6                0x48167C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_7                0x481680
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_8                0x481684
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_9                0x481688
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_10               0x48168C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_11               0x481690
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_12               0x481694
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_13               0x481698
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_14               0x48169C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_15               0x4816A0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_0               0x4816A4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_1               0x4816A8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_2               0x4816AC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_3               0x4816B0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_4               0x4816B4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_5               0x4816B8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_6               0x4816BC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_7               0x4816C0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_8               0x4816C4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_9               0x4816C8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_10              0x4816CC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_11              0x4816D0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_12              0x4816D4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_13              0x4816D8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_14              0x4816DC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_15              0x4816E0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_0               0x4816E4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_1               0x4816E8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_2               0x4816EC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_3               0x4816F0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_4               0x4816F4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_5               0x4816F8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_6               0x4816FC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_7               0x481700
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_8               0x481704
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_9               0x481708
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_10              0x48170C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_11              0x481710
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_12              0x481714
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_13              0x481718
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_14              0x48171C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_15              0x481720
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_0              0x481724
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_1              0x481728
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_2              0x48172C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_3              0x481730
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_4              0x481734
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_5              0x481738
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_6              0x48173C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_7              0x481740
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_8              0x481744
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_9              0x481748
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_10             0x48174C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_11             0x481750
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_12             0x481754
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_13             0x481758
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_14             0x48175C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_15             0x481760
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_0               0x481764
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_1               0x481768
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_2               0x48176C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_3               0x481770
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_4               0x481774
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_5               0x481778
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_6               0x48177C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_7               0x481780
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_8               0x481784
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_9               0x481788
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_10              0x48178C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_11              0x481790
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_12              0x481794
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_13              0x481798
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_14              0x48179C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_15              0x4817A0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_0              0x4817A4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_1              0x4817A8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_2              0x4817AC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_3              0x4817B0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_4              0x4817B4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_5              0x4817B8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_6              0x4817BC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_7              0x4817C0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_8              0x4817C4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_9              0x4817C8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_10             0x4817CC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_11             0x4817D0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_12             0x4817D4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_13             0x4817D8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_14             0x4817DC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_15             0x4817E0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_0                0x481824
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_1                0x481828
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_2                0x48182C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_3                0x481830
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_4                0x481834
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_5                0x481838
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_6                0x48183C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_7                0x481840
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_8                0x481844
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_9                0x481848
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_10               0x48184C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_11               0x481850
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_12               0x481854
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_13               0x481858
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_14               0x48185C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_15               0x481860
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_0               0x481864
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_1               0x481868
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_2               0x48186C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_3               0x481870
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_4               0x481874
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_5               0x481878
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_6               0x48187C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_7               0x481880
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_8               0x481884
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_9               0x481888
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_10              0x48188C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_11              0x481890
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_12              0x481894
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_13              0x481898
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_14              0x48189C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_15              0x4818A0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_0                0x4818A4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_1                0x4818A8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_2                0x4818AC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_3                0x4818B0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_4                0x4818B4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_5                0x4818B8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_6                0x4818BC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_7                0x4818C0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_8                0x4818C4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_9                0x4818C8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_10               0x4818CC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_11               0x4818D0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_12               0x4818D4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_13               0x4818D8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_14               0x4818DC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_15               0x4818E0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_0               0x4818E4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_1               0x4818E8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_2               0x4818EC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_3               0x4818F0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_4               0x4818F4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_5               0x4818F8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_6               0x4818FC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_7               0x481900
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_8               0x481904
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_9               0x481908
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_10              0x48190C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_11              0x481910
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_12              0x481914
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_13              0x481918
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_14              0x48191C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_15              0x481920
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_0               0x481924
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_1               0x481928
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_2               0x48192C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_3               0x481930
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_4               0x481934
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_5               0x481938
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_6               0x48193C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_7               0x481940
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_8               0x481944
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_9               0x481948
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_10              0x48194C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_11              0x481950
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_12              0x481954
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_13              0x481958
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_14              0x48195C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_15              0x481960
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_0              0x481964
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_1              0x481968
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_2              0x48196C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_3              0x481970
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_4              0x481974
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_5              0x481978
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_6              0x48197C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_7              0x481980
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_8              0x481984
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_9              0x481988
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_10             0x48198C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_11             0x481990
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_12             0x481994
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_13             0x481998
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_14             0x48199C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_15             0x4819A0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_0               0x4819A4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_1               0x4819A8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_2               0x4819AC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_3               0x4819B0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_4               0x4819B4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_5               0x4819B8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_6               0x4819BC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_7               0x4819C0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_8               0x4819C4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_9               0x4819C8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_10              0x4819CC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_11              0x4819D0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_12              0x4819D4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_13              0x4819D8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_14              0x4819DC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_15              0x4819E0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_0              0x4819E4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_1              0x4819E8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_2              0x4819EC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_3              0x4819F0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_4              0x4819F4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_5              0x4819F8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_6              0x4819FC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_7              0x481A00
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_8              0x481A04
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_9              0x481A08
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_10             0x481A0C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_11             0x481A10
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_12             0x481A14
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_13             0x481A18
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_14             0x481A1C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_15             0x481A20
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_HIT_AW                       0x481A64
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_HIT_AR                       0x481A68
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_HIT_AW                      0x481A6C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_HIT_AR                      0x481A70
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_CFG                                0x481B64
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_SHIFT                              0x481B68
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_0                     0x481B6C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_1                     0x481B70
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_2                     0x481B74
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_3                     0x481B78
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_4                     0x481B7C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_5                     0x481B80
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_6                     0x481B84
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_7                     0x481B88
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_0                            0x481BAC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_1                            0x481BB0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_2                            0x481BB4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_3                            0x481BB8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_4                            0x481BBC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_5                            0x481BC0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_6                            0x481BC4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_7                            0x481BC8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_0                          0x481BEC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_1                          0x481BF0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_2                          0x481BF4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_3                          0x481BF8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_4                          0x481BFC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_5                          0x481C00
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_6                          0x481C04
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_7                          0x481C08
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_WDT                                0x481C2C
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_WRAP               0x481C30
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_WRAP               0x481C34
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_WRAP               0x481C38
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_WRAP               0x481C3C
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_WRAP               0x481C40
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_WRAP               0x481C44
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_WRAP               0x481C48
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_WRAP               0x481C4C
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_CNT                0x481C50
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_CNT                0x481C54
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_CNT                0x481C58
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_CNT                0x481C5C
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_CNT                0x481C60
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_CNT                0x481C64
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_CNT                0x481C68
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_CNT                0x481C6C
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_WRAP               0x481C70
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_WRAP               0x481C74
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_WRAP               0x481C78
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_WRAP               0x481C7C
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_WRAP               0x481C80
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_WRAP               0x481C84
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_WRAP               0x481C88
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_WRAP               0x481C8C
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_CNT                0x481C90
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_CNT                0x481C94
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_CNT                0x481C98
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_CNT                0x481C9C
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_CNT                0x481CA0
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_CNT                0x481CA4
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_CNT                0x481CA8
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_CNT                0x481CAC
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_PC_SEL_0                        0x481CB0
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_PC_SEL_1                        0x481CB4
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_PC_SEL_2                        0x481CB8
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_PC_SEL_3                        0x481CBC
+
+#endif /* ASIC_REG_DMA_IF_W_S_DOWN_CH0_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_s_down_ch1_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_s_down_ch1_regs.h
new file mode 100644
index 000000000000..cbc642918deb
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_s_down_ch1_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DMA_IF_W_S_DOWN_CH1_REGS_H_
+#define ASIC_REG_DMA_IF_W_S_DOWN_CH1_REGS_H_
+
+/*
+ *****************************************
+ *   DMA_IF_W_S_DOWN_CH1 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmDMA_IF_W_S_DOWN_CH1_PERM_SEL                               0x482108
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_0                          0x482114
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_1                          0x482118
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_2                          0x48211C
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_3                          0x482120
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_4                          0x482124
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_5                          0x482128
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_6                          0x48212C
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_7                          0x482130
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_8                          0x482134
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_9                          0x482138
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_10                         0x48213C
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_11                         0x482140
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_12                         0x482144
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_13                         0x482148
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_14                         0x48214C
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_15                         0x482150
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_16                         0x482154
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_17                         0x482158
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_18                         0x48215C
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_19                         0x482160
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_20                         0x482164
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_21                         0x482168
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_22                         0x48216C
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_23                         0x482170
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_24                         0x482174
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_25                         0x482178
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_26                         0x48217C
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_27                         0x482180
+
+#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_0                         0x482184
+
+#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_1                         0x482188
+
+#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_2                         0x48218C
+
+#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_3                         0x482190
+
+#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_4                         0x482194
+
+#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_5                         0x482198
+
+#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_6                         0x48219C
+
+#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_7                         0x4821A0
+
+#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_8                         0x4821A4
+
+#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_9                         0x4821A8
+
+#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_10                        0x4821AC
+
+#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_11                        0x4821B0
+
+#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_12                        0x4821B4
+
+#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_13                        0x4821B8
+
+#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_14                        0x4821BC
+
+#define mmDMA_IF_W_S_DOWN_CH1_SCRAM_SRAM_EN                          0x48226C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RL_HBM_EN                              0x482274
+
+#define mmDMA_IF_W_S_DOWN_CH1_RL_HBM_SAT                             0x482278
+
+#define mmDMA_IF_W_S_DOWN_CH1_RL_HBM_RST                             0x48227C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RL_HBM_TIMEOUT                         0x482280
+
+#define mmDMA_IF_W_S_DOWN_CH1_SCRAM_HBM_EN                           0x482284
+
+#define mmDMA_IF_W_S_DOWN_CH1_RL_PCI_EN                              0x482288
+
+#define mmDMA_IF_W_S_DOWN_CH1_RL_PCI_SAT                             0x48228C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RL_PCI_RST                             0x482290
+
+#define mmDMA_IF_W_S_DOWN_CH1_RL_PCI_TIMEOUT                         0x482294
+
+#define mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_EN                             0x48229C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_SAT                            0x4822A0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_RST                            0x4822A4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_TIMEOUT                        0x4822AC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_RED                            0x4822B4
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_HBM_EN                             0x4822EC
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_PCI_EN                             0x4822F0
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_HBM_WR_SIZE                        0x4822F4
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_PCI_WR_SIZE                        0x4822F8
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_PCI_CTR_SET_EN                  0x482404
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_PCI_CTR_SET                     0x482408
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_PCI_CTR_WRAP                    0x48240C
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_PCI_CTR_CNT                     0x482410
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM_CTR_SET_EN                  0x482414
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM_CTR_SET                     0x482418
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_HBM_RD_SIZE                        0x48241C
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_PCI_RD_SIZE                        0x482420
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_PCI_CTR_SET_EN                  0x482424
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_PCI_CTR_SET                     0x482428
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_PCI_CTR_WRAP                    0x48242C
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_PCI_CTR_CNT                     0x482430
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM_CTR_SET_EN                  0x482434
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM_CTR_SET                     0x482438
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_SEL_0                           0x482450
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_SEL_1                           0x482454
+
+#define mmDMA_IF_W_S_DOWN_CH1_NON_LIN_EN                             0x482480
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_BANK_0                         0x482500
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_BANK_1                         0x482504
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_BANK_2                         0x482508
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_BANK_3                         0x48250C
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_BANK_4                         0x482510
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_0                       0x482514
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_1                       0x482520
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_2                       0x482524
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_3                       0x482528
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_4                       0x48252C
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_5                       0x482530
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_6                       0x482534
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_7                       0x482538
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_8                       0x48253C
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_9                       0x482540
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_0                        0x482550
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_1                        0x482554
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_2                        0x482558
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_3                        0x48255C
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_4                        0x482560
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_5                        0x482564
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_6                        0x482568
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_7                        0x48256C
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_8                        0x482570
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_9                        0x482574
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_10                       0x482578
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_11                       0x48257C
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_12                       0x482580
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_13                       0x482584
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_14                       0x482588
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_15                       0x48258C
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_16                       0x482590
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_17                       0x482594
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_18                       0x482598
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0                0x4825E4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_1                0x4825E8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_2                0x4825EC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_3                0x4825F0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_4                0x4825F4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_5                0x4825F8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_6                0x4825FC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_7                0x482600
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_8                0x482604
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_9                0x482608
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_10               0x48260C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_11               0x482610
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_12               0x482614
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_13               0x482618
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_14               0x48261C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_15               0x482620
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0               0x482624
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_1               0x482628
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_2               0x48262C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_3               0x482630
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_4               0x482634
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_5               0x482638
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_6               0x48263C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_7               0x482640
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_8               0x482644
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_9               0x482648
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_10              0x48264C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_11              0x482650
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_12              0x482654
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_13              0x482658
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_14              0x48265C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_15              0x482660
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0                0x482664
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_1                0x482668
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_2                0x48266C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_3                0x482670
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_4                0x482674
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_5                0x482678
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_6                0x48267C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_7                0x482680
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_8                0x482684
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_9                0x482688
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_10               0x48268C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_11               0x482690
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_12               0x482694
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_13               0x482698
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_14               0x48269C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_15               0x4826A0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0               0x4826A4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_1               0x4826A8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_2               0x4826AC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_3               0x4826B0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_4               0x4826B4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_5               0x4826B8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_6               0x4826BC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_7               0x4826C0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_8               0x4826C4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_9               0x4826C8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_10              0x4826CC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_11              0x4826D0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_12              0x4826D4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_13              0x4826D8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_14              0x4826DC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_15              0x4826E0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_0               0x4826E4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_1               0x4826E8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_2               0x4826EC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_3               0x4826F0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_4               0x4826F4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_5               0x4826F8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_6               0x4826FC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_7               0x482700
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_8               0x482704
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_9               0x482708
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_10              0x48270C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_11              0x482710
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_12              0x482714
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_13              0x482718
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_14              0x48271C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_15              0x482720
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_0              0x482724
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_1              0x482728
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_2              0x48272C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_3              0x482730
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_4              0x482734
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_5              0x482738
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_6              0x48273C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_7              0x482740
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_8              0x482744
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_9              0x482748
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_10             0x48274C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_11             0x482750
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_12             0x482754
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_13             0x482758
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_14             0x48275C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_15             0x482760
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_0               0x482764
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_1               0x482768
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_2               0x48276C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_3               0x482770
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_4               0x482774
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_5               0x482778
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_6               0x48277C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_7               0x482780
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_8               0x482784
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_9               0x482788
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_10              0x48278C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_11              0x482790
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_12              0x482794
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_13              0x482798
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_14              0x48279C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_15              0x4827A0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_0              0x4827A4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_1              0x4827A8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_2              0x4827AC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_3              0x4827B0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_4              0x4827B4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_5              0x4827B8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_6              0x4827BC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_7              0x4827C0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_8              0x4827C4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_9              0x4827C8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_10             0x4827CC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_11             0x4827D0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_12             0x4827D4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_13             0x4827D8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_14             0x4827DC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_15             0x4827E0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0                0x482824
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_1                0x482828
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_2                0x48282C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_3                0x482830
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_4                0x482834
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_5                0x482838
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_6                0x48283C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_7                0x482840
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_8                0x482844
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_9                0x482848
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_10               0x48284C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_11               0x482850
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_12               0x482854
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_13               0x482858
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_14               0x48285C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_15               0x482860
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0               0x482864
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_1               0x482868
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_2               0x48286C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_3               0x482870
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_4               0x482874
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_5               0x482878
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_6               0x48287C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_7               0x482880
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_8               0x482884
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_9               0x482888
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_10              0x48288C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_11              0x482890
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_12              0x482894
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_13              0x482898
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_14              0x48289C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_15              0x4828A0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0                0x4828A4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_1                0x4828A8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_2                0x4828AC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_3                0x4828B0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_4                0x4828B4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_5                0x4828B8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_6                0x4828BC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_7                0x4828C0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_8                0x4828C4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_9                0x4828C8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_10               0x4828CC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_11               0x4828D0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_12               0x4828D4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_13               0x4828D8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_14               0x4828DC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_15               0x4828E0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0               0x4828E4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_1               0x4828E8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_2               0x4828EC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_3               0x4828F0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_4               0x4828F4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_5               0x4828F8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_6               0x4828FC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_7               0x482900
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_8               0x482904
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_9               0x482908
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_10              0x48290C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_11              0x482910
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_12              0x482914
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_13              0x482918
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_14              0x48291C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_15              0x482920
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_0               0x482924
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_1               0x482928
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_2               0x48292C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_3               0x482930
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_4               0x482934
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_5               0x482938
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_6               0x48293C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_7               0x482940
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_8               0x482944
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_9               0x482948
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_10              0x48294C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_11              0x482950
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_12              0x482954
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_13              0x482958
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_14              0x48295C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_15              0x482960
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_0              0x482964
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_1              0x482968
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_2              0x48296C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_3              0x482970
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_4              0x482974
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_5              0x482978
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_6              0x48297C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_7              0x482980
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_8              0x482984
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_9              0x482988
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_10             0x48298C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_11             0x482990
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_12             0x482994
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_13             0x482998
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_14             0x48299C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_15             0x4829A0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_0               0x4829A4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_1               0x4829A8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_2               0x4829AC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_3               0x4829B0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_4               0x4829B4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_5               0x4829B8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_6               0x4829BC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_7               0x4829C0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_8               0x4829C4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_9               0x4829C8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_10              0x4829CC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_11              0x4829D0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_12              0x4829D4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_13              0x4829D8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_14              0x4829DC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_15              0x4829E0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_0              0x4829E4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_1              0x4829E8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_2              0x4829EC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_3              0x4829F0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_4              0x4829F4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_5              0x4829F8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_6              0x4829FC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_7              0x482A00
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_8              0x482A04
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_9              0x482A08
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_10             0x482A0C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_11             0x482A10
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_12             0x482A14
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_13             0x482A18
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_14             0x482A1C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_15             0x482A20
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_HIT_AW                       0x482A64
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_HIT_AR                       0x482A68
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_HIT_AW                      0x482A6C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_HIT_AR                      0x482A70
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_CFG                                0x482B64
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_SHIFT                              0x482B68
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_0                     0x482B6C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_1                     0x482B70
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_2                     0x482B74
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_3                     0x482B78
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_4                     0x482B7C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_5                     0x482B80
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_6                     0x482B84
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_7                     0x482B88
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_0                            0x482BAC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_1                            0x482BB0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_2                            0x482BB4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_3                            0x482BB8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_4                            0x482BBC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_5                            0x482BC0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_6                            0x482BC4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_7                            0x482BC8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_0                          0x482BEC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_1                          0x482BF0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_2                          0x482BF4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_3                          0x482BF8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_4                          0x482BFC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_5                          0x482C00
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_6                          0x482C04
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_7                          0x482C08
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_WDT                                0x482C2C
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_WRAP               0x482C30
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_WRAP               0x482C34
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_WRAP               0x482C38
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_WRAP               0x482C3C
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_WRAP               0x482C40
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_WRAP               0x482C44
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_WRAP               0x482C48
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_WRAP               0x482C4C
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_CNT                0x482C50
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_CNT                0x482C54
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_CNT                0x482C58
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_CNT                0x482C5C
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_CNT                0x482C60
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_CNT                0x482C64
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_CNT                0x482C68
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_CNT                0x482C6C
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_WRAP               0x482C70
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_WRAP               0x482C74
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_WRAP               0x482C78
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_WRAP               0x482C7C
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_WRAP               0x482C80
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_WRAP               0x482C84
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_WRAP               0x482C88
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_WRAP               0x482C8C
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_CNT                0x482C90
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_CNT                0x482C94
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_CNT                0x482C98
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_CNT                0x482C9C
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_CNT                0x482CA0
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_CNT                0x482CA4
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_CNT                0x482CA8
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_CNT                0x482CAC
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_PC_SEL_0                        0x482CB0
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_PC_SEL_1                        0x482CB4
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_PC_SEL_2                        0x482CB8
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_PC_SEL_3                        0x482CBC
+
+#endif /* ASIC_REG_DMA_IF_W_S_DOWN_CH1_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_s_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_s_regs.h
new file mode 100644
index 000000000000..2382bc41bea6
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_s_regs.h
@@ -0,0 +1,860 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DMA_IF_W_S_REGS_H_
+#define ASIC_REG_DMA_IF_W_S_REGS_H_
+
+/*
+ *****************************************
+ *   DMA_IF_W_S (Prototype: DMA_IF)
+ *****************************************
+ */
+
+#define mmDMA_IF_W_S_HBM0_WR_CRED_CNT                                0x480000
+
+#define mmDMA_IF_W_S_HBM1_WR_CRED_CNT                                0x480004
+
+#define mmDMA_IF_W_S_HBM0_RD_CRED_CNT                                0x480008
+
+#define mmDMA_IF_W_S_HBM1_RD_CRED_CNT                                0x48000C
+
+#define mmDMA_IF_W_S_HBM_LIMITER_0                                   0x480030
+
+#define mmDMA_IF_W_S_HBM_LIMITER_1                                   0x480034
+
+#define mmDMA_IF_W_S_HBM_LIMITER_2                                   0x480038
+
+#define mmDMA_IF_W_S_HBM_LIMITER_3                                   0x48003C
+
+#define mmDMA_IF_W_S_HBM_ALMOST_EN_0                                 0x480040
+
+#define mmDMA_IF_W_S_HBM_ALMOST_EN_1                                 0x480044
+
+#define mmDMA_IF_W_S_HBM_CRED_EN_0                                   0x480050
+
+#define mmDMA_IF_W_S_HBM_CRED_EN_1                                   0x480054
+
+#define mmDMA_IF_W_S_SOB_MIN_RPROT_0                                 0x480100
+
+#define mmDMA_IF_W_S_SOB_MIN_RPROT_1                                 0x480104
+
+#define mmDMA_IF_W_S_SOB_MIN_RPROT_2                                 0x480108
+
+#define mmDMA_IF_W_S_SOB_MIN_RPROT_3                                 0x48010C
+
+#define mmDMA_IF_W_S_SOB_MIN_RPROT_4                                 0x480110
+
+#define mmDMA_IF_W_S_SOB_MIN_RPROT_5                                 0x480114
+
+#define mmDMA_IF_W_S_SOB_MIN_RPROT_6                                 0x480118
+
+#define mmDMA_IF_W_S_SOB_MIN_RPROT_7                                 0x48011C
+
+#define mmDMA_IF_W_S_SOB_MIN_RPROT_8                                 0x480120
+
+#define mmDMA_IF_W_S_SOB_MIN_RPROT_9                                 0x480124
+
+#define mmDMA_IF_W_S_SOB_MIN_RPROT_10                                0x480128
+
+#define mmDMA_IF_W_S_SOB_MIN_RPROT_11                                0x48012C
+
+#define mmDMA_IF_W_S_SOB_MIN_RPROT_12                                0x480130
+
+#define mmDMA_IF_W_S_SOB_MIN_RPROT_13                                0x480134
+
+#define mmDMA_IF_W_S_SOB_MIN_RPROT_14                                0x480138
+
+#define mmDMA_IF_W_S_SOB_MIN_RPROT_15                                0x48013C
+
+#define mmDMA_IF_W_S_SOB_MAX_RPROT_0                                 0x480140
+
+#define mmDMA_IF_W_S_SOB_MAX_RPROT_1                                 0x480144
+
+#define mmDMA_IF_W_S_SOB_MAX_RPROT_2                                 0x480148
+
+#define mmDMA_IF_W_S_SOB_MAX_RPROT_3                                 0x48014C
+
+#define mmDMA_IF_W_S_SOB_MAX_RPROT_4                                 0x480150
+
+#define mmDMA_IF_W_S_SOB_MAX_RPROT_5                                 0x480154
+
+#define mmDMA_IF_W_S_SOB_MAX_RPROT_6                                 0x480158
+
+#define mmDMA_IF_W_S_SOB_MAX_RPROT_7                                 0x48015C
+
+#define mmDMA_IF_W_S_SOB_MAX_RPROT_8                                 0x480160
+
+#define mmDMA_IF_W_S_SOB_MAX_RPROT_9                                 0x480164
+
+#define mmDMA_IF_W_S_SOB_MAX_RPROT_10                                0x480168
+
+#define mmDMA_IF_W_S_SOB_MAX_RPROT_11                                0x48016C
+
+#define mmDMA_IF_W_S_SOB_MAX_RPROT_12                                0x480170
+
+#define mmDMA_IF_W_S_SOB_MAX_RPROT_13                                0x480174
+
+#define mmDMA_IF_W_S_SOB_MAX_RPROT_14                                0x480178
+
+#define mmDMA_IF_W_S_SOB_MAX_RPROT_15                                0x48017C
+
+#define mmDMA_IF_W_S_SOB_MIN_WPROT_0                                 0x480180
+
+#define mmDMA_IF_W_S_SOB_MIN_WPROT_1                                 0x480184
+
+#define mmDMA_IF_W_S_SOB_MIN_WPROT_2                                 0x480188
+
+#define mmDMA_IF_W_S_SOB_MIN_WPROT_3                                 0x48018C
+
+#define mmDMA_IF_W_S_SOB_MIN_WPROT_4                                 0x480190
+
+#define mmDMA_IF_W_S_SOB_MIN_WPROT_5                                 0x480194
+
+#define mmDMA_IF_W_S_SOB_MIN_WPROT_6                                 0x480198
+
+#define mmDMA_IF_W_S_SOB_MIN_WPROT_7                                 0x48019C
+
+#define mmDMA_IF_W_S_SOB_MIN_WPROT_8                                 0x4801A0
+
+#define mmDMA_IF_W_S_SOB_MIN_WPROT_9                                 0x4801A4
+
+#define mmDMA_IF_W_S_SOB_MIN_WPROT_10                                0x4801A8
+
+#define mmDMA_IF_W_S_SOB_MIN_WPROT_11                                0x4801AC
+
+#define mmDMA_IF_W_S_SOB_MIN_WPROT_12                                0x4801B0
+
+#define mmDMA_IF_W_S_SOB_MIN_WPROT_13                                0x4801B4
+
+#define mmDMA_IF_W_S_SOB_MIN_WPROT_14                                0x4801B8
+
+#define mmDMA_IF_W_S_SOB_MIN_WPROT_15                                0x4801BC
+
+#define mmDMA_IF_W_S_SOB_MAX_WPROT_0                                 0x4801C0
+
+#define mmDMA_IF_W_S_SOB_MAX_WPROT_1                                 0x4801C4
+
+#define mmDMA_IF_W_S_SOB_MAX_WPROT_2                                 0x4801C8
+
+#define mmDMA_IF_W_S_SOB_MAX_WPROT_3                                 0x4801CC
+
+#define mmDMA_IF_W_S_SOB_MAX_WPROT_4                                 0x4801D0
+
+#define mmDMA_IF_W_S_SOB_MAX_WPROT_5                                 0x4801D4
+
+#define mmDMA_IF_W_S_SOB_MAX_WPROT_6                                 0x4801D8
+
+#define mmDMA_IF_W_S_SOB_MAX_WPROT_7                                 0x4801DC
+
+#define mmDMA_IF_W_S_SOB_MAX_WPROT_8                                 0x4801E0
+
+#define mmDMA_IF_W_S_SOB_MAX_WPROT_9                                 0x4801E4
+
+#define mmDMA_IF_W_S_SOB_MAX_WPROT_10                                0x4801E8
+
+#define mmDMA_IF_W_S_SOB_MAX_WPROT_11                                0x4801EC
+
+#define mmDMA_IF_W_S_SOB_MAX_WPROT_12                                0x4801F0
+
+#define mmDMA_IF_W_S_SOB_MAX_WPROT_13                                0x4801F4
+
+#define mmDMA_IF_W_S_SOB_MAX_WPROT_14                                0x4801F8
+
+#define mmDMA_IF_W_S_SOB_MAX_WPROT_15                                0x4801FC
+
+#define mmDMA_IF_W_S_SOB_MIN_RPRIV_0                                 0x480200
+
+#define mmDMA_IF_W_S_SOB_MIN_RPRIV_1                                 0x480204
+
+#define mmDMA_IF_W_S_SOB_MIN_RPRIV_2                                 0x480208
+
+#define mmDMA_IF_W_S_SOB_MIN_RPRIV_3                                 0x48020C
+
+#define mmDMA_IF_W_S_SOB_MIN_RPRIV_4                                 0x480210
+
+#define mmDMA_IF_W_S_SOB_MIN_RPRIV_5                                 0x480214
+
+#define mmDMA_IF_W_S_SOB_MIN_RPRIV_6                                 0x480218
+
+#define mmDMA_IF_W_S_SOB_MIN_RPRIV_7                                 0x48021C
+
+#define mmDMA_IF_W_S_SOB_MIN_RPRIV_8                                 0x480220
+
+#define mmDMA_IF_W_S_SOB_MIN_RPRIV_9                                 0x480224
+
+#define mmDMA_IF_W_S_SOB_MIN_RPRIV_10                                0x480228
+
+#define mmDMA_IF_W_S_SOB_MIN_RPRIV_11                                0x48022C
+
+#define mmDMA_IF_W_S_SOB_MIN_RPRIV_12                                0x480230
+
+#define mmDMA_IF_W_S_SOB_MIN_RPRIV_13                                0x480234
+
+#define mmDMA_IF_W_S_SOB_MIN_RPRIV_14                                0x480238
+
+#define mmDMA_IF_W_S_SOB_MIN_RPRIV_15                                0x48023C
+
+#define mmDMA_IF_W_S_SOB_MAX_RPRIV_0                                 0x480240
+
+#define mmDMA_IF_W_S_SOB_MAX_RPRIV_1                                 0x480244
+
+#define mmDMA_IF_W_S_SOB_MAX_RPRIV_2                                 0x480248
+
+#define mmDMA_IF_W_S_SOB_MAX_RPRIV_3                                 0x48024C
+
+#define mmDMA_IF_W_S_SOB_MAX_RPRIV_4                                 0x480250
+
+#define mmDMA_IF_W_S_SOB_MAX_RPRIV_5                                 0x480254
+
+#define mmDMA_IF_W_S_SOB_MAX_RPRIV_6                                 0x480258
+
+#define mmDMA_IF_W_S_SOB_MAX_RPRIV_7                                 0x48025C
+
+#define mmDMA_IF_W_S_SOB_MAX_RPRIV_8                                 0x480260
+
+#define mmDMA_IF_W_S_SOB_MAX_RPRIV_9                                 0x480264
+
+#define mmDMA_IF_W_S_SOB_MAX_RPRIV_10                                0x480268
+
+#define mmDMA_IF_W_S_SOB_MAX_RPRIV_11                                0x48026C
+
+#define mmDMA_IF_W_S_SOB_MAX_RPRIV_12                                0x480270
+
+#define mmDMA_IF_W_S_SOB_MAX_RPRIV_13                                0x480274
+
+#define mmDMA_IF_W_S_SOB_MAX_RPRIV_14                                0x480278
+
+#define mmDMA_IF_W_S_SOB_MAX_RPRIV_15                                0x48027C
+
+#define mmDMA_IF_W_S_SOB_MIN_WPRIV_0                                 0x480280
+
+#define mmDMA_IF_W_S_SOB_MIN_WPRIV_1                                 0x480284
+
+#define mmDMA_IF_W_S_SOB_MIN_WPRIV_2                                 0x480288
+
+#define mmDMA_IF_W_S_SOB_MIN_WPRIV_3                                 0x48028C
+
+#define mmDMA_IF_W_S_SOB_MIN_WPRIV_4                                 0x480290
+
+#define mmDMA_IF_W_S_SOB_MIN_WPRIV_5                                 0x480294
+
+#define mmDMA_IF_W_S_SOB_MIN_WPRIV_6                                 0x480298
+
+#define mmDMA_IF_W_S_SOB_MIN_WPRIV_7                                 0x48029C
+
+#define mmDMA_IF_W_S_SOB_MIN_WPRIV_8                                 0x4802A0
+
+#define mmDMA_IF_W_S_SOB_MIN_WPRIV_9                                 0x4802A4
+
+#define mmDMA_IF_W_S_SOB_MIN_WPRIV_10                                0x4802A8
+
+#define mmDMA_IF_W_S_SOB_MIN_WPRIV_11                                0x4802AC
+
+#define mmDMA_IF_W_S_SOB_MIN_WPRIV_12                                0x4802B0
+
+#define mmDMA_IF_W_S_SOB_MIN_WPRIV_13                                0x4802B4
+
+#define mmDMA_IF_W_S_SOB_MIN_WPRIV_14                                0x4802B8
+
+#define mmDMA_IF_W_S_SOB_MIN_WPRIV_15                                0x4802BC
+
+#define mmDMA_IF_W_S_SOB_MAX_WPRIV_0                                 0x4802C0
+
+#define mmDMA_IF_W_S_SOB_MAX_WPRIV_1                                 0x4802C4
+
+#define mmDMA_IF_W_S_SOB_MAX_WPRIV_2                                 0x4802C8
+
+#define mmDMA_IF_W_S_SOB_MAX_WPRIV_3                                 0x4802CC
+
+#define mmDMA_IF_W_S_SOB_MAX_WPRIV_4                                 0x4802D0
+
+#define mmDMA_IF_W_S_SOB_MAX_WPRIV_5                                 0x4802D4
+
+#define mmDMA_IF_W_S_SOB_MAX_WPRIV_6                                 0x4802D8
+
+#define mmDMA_IF_W_S_SOB_MAX_WPRIV_7                                 0x4802DC
+
+#define mmDMA_IF_W_S_SOB_MAX_WPRIV_8                                 0x4802E0
+
+#define mmDMA_IF_W_S_SOB_MAX_WPRIV_9                                 0x4802E4
+
+#define mmDMA_IF_W_S_SOB_MAX_WPRIV_10                                0x4802E8
+
+#define mmDMA_IF_W_S_SOB_MAX_WPRIV_11                                0x4802EC
+
+#define mmDMA_IF_W_S_SOB_MAX_WPRIV_12                                0x4802F0
+
+#define mmDMA_IF_W_S_SOB_MAX_WPRIV_13                                0x4802F4
+
+#define mmDMA_IF_W_S_SOB_MAX_WPRIV_14                                0x4802F8
+
+#define mmDMA_IF_W_S_SOB_MAX_WPRIV_15                                0x4802FC
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPROT_0                                0x480300
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPROT_1                                0x480304
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPROT_2                                0x480308
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPROT_3                                0x48030C
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPROT_4                                0x480310
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPROT_5                                0x480314
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPROT_6                                0x480318
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPROT_7                                0x48031C
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPROT_8                                0x480320
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPROT_9                                0x480324
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPROT_10                               0x480328
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPROT_11                               0x48032C
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPROT_12                               0x480330
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPROT_13                               0x480334
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPROT_14                               0x480338
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPROT_15                               0x48033C
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPROT_0                                0x480340
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPROT_1                                0x480344
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPROT_2                                0x480348
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPROT_3                                0x48034C
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPROT_4                                0x480350
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPROT_5                                0x480354
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPROT_6                                0x480358
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPROT_7                                0x48035C
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPROT_8                                0x480360
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPROT_9                                0x480364
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPROT_10                               0x480368
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPROT_11                               0x48036C
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPROT_12                               0x480370
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPROT_13                               0x480374
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPROT_14                               0x480378
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPROT_15                               0x48037C
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPROT_0                                0x480380
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPROT_1                                0x480384
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPROT_2                                0x480388
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPROT_3                                0x48038C
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPROT_4                                0x480390
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPROT_5                                0x480394
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPROT_6                                0x480398
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPROT_7                                0x48039C
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPROT_8                                0x4803A0
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPROT_9                                0x4803A4
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPROT_10                               0x4803A8
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPROT_11                               0x4803AC
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPROT_12                               0x4803B0
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPROT_13                               0x4803B4
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPROT_14                               0x4803B8
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPROT_15                               0x4803BC
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPROT_0                                0x4803C0
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPROT_1                                0x4803C4
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPROT_2                                0x4803C8
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPROT_3                                0x4803CC
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPROT_4                                0x4803D0
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPROT_5                                0x4803D4
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPROT_6                                0x4803D8
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPROT_7                                0x4803DC
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPROT_8                                0x4803E0
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPROT_9                                0x4803E4
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPROT_10                               0x4803E8
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPROT_11                               0x4803EC
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPROT_12                               0x4803F0
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPROT_13                               0x4803F4
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPROT_14                               0x4803F8
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPROT_15                               0x4803FC
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_0                                0x480400
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_1                                0x480404
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_2                                0x480408
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_3                                0x48040C
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_4                                0x480410
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_5                                0x480414
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_6                                0x480418
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_7                                0x48041C
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_8                                0x480420
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_9                                0x480424
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_10                               0x480428
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_11                               0x48042C
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_12                               0x480430
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_13                               0x480434
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_14                               0x480438
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_15                               0x48043C
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_0                                0x480440
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_1                                0x480444
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_2                                0x480448
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_3                                0x48044C
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_4                                0x480450
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_5                                0x480454
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_6                                0x480458
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_7                                0x48045C
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_8                                0x480460
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_9                                0x480464
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_10                               0x480468
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_11                               0x48046C
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_12                               0x480470
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_13                               0x480474
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_14                               0x480478
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_15                               0x48047C
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_0                                0x480480
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_1                                0x480484
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_2                                0x480488
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_3                                0x48048C
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_4                                0x480490
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_5                                0x480494
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_6                                0x480498
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_7                                0x48049C
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_8                                0x4804A0
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_9                                0x4804A4
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_10                               0x4804A8
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_11                               0x4804AC
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_12                               0x4804B0
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_13                               0x4804B4
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_14                               0x4804B8
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_15                               0x4804BC
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_0                                0x4804C0
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_1                                0x4804C4
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_2                                0x4804C8
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_3                                0x4804CC
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_4                                0x4804D0
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_5                                0x4804D4
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_6                                0x4804D8
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_7                                0x4804DC
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_8                                0x4804E0
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_9                                0x4804E4
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_10                               0x4804E8
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_11                               0x4804EC
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_12                               0x4804F0
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_13                               0x4804F4
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_14                               0x4804F8
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_15                               0x4804FC
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPROT_0                                0x480500
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPROT_1                                0x480504
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPROT_2                                0x480508
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPROT_3                                0x48050C
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPROT_4                                0x480510
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPROT_5                                0x480514
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPROT_6                                0x480518
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPROT_7                                0x48051C
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPROT_8                                0x480520
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPROT_9                                0x480524
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPROT_10                               0x480528
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPROT_11                               0x48052C
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPROT_12                               0x480530
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPROT_13                               0x480534
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPROT_14                               0x480538
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPROT_15                               0x48053C
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPROT_0                                0x480540
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPROT_1                                0x480544
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPROT_2                                0x480548
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPROT_3                                0x48054C
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPROT_4                                0x480550
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPROT_5                                0x480554
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPROT_6                                0x480558
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPROT_7                                0x48055C
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPROT_8                                0x480560
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPROT_9                                0x480564
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPROT_10                               0x480568
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPROT_11                               0x48056C
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPROT_12                               0x480570
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPROT_13                               0x480574
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPROT_14                               0x480578
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPROT_15                               0x48057C
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPROT_0                                0x480580
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPROT_1                                0x480584
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPROT_2                                0x480588
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPROT_3                                0x48058C
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPROT_4                                0x480590
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPROT_5                                0x480594
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPROT_6                                0x480598
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPROT_7                                0x48059C
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPROT_8                                0x4805A0
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPROT_9                                0x4805A4
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPROT_10                               0x4805A8
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPROT_11                               0x4805AC
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPROT_12                               0x4805B0
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPROT_13                               0x4805B4
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPROT_14                               0x4805B8
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPROT_15                               0x4805BC
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPROT_0                                0x4805C0
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPROT_1                                0x4805C4
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPROT_2                                0x4805C8
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPROT_3                                0x4805CC
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPROT_4                                0x4805D0
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPROT_5                                0x4805D4
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPROT_6                                0x4805D8
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPROT_7                                0x4805DC
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPROT_8                                0x4805E0
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPROT_9                                0x4805E4
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPROT_10                               0x4805E8
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPROT_11                               0x4805EC
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPROT_12                               0x4805F0
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPROT_13                               0x4805F4
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPROT_14                               0x4805F8
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPROT_15                               0x4805FC
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_0                                0x480600
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_1                                0x480604
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_2                                0x480608
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_3                                0x48060C
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_4                                0x480610
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_5                                0x480614
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_6                                0x480618
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_7                                0x48061C
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_8                                0x480620
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_9                                0x480624
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_10                               0x480628
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_11                               0x48062C
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_12                               0x480630
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_13                               0x480634
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_14                               0x480638
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_15                               0x48063C
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_0                                0x480640
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_1                                0x480644
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_2                                0x480648
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_3                                0x48064C
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_4                                0x480650
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_5                                0x480654
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_6                                0x480658
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_7                                0x48065C
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_8                                0x480660
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_9                                0x480664
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_10                               0x480668
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_11                               0x48066C
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_12                               0x480670
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_13                               0x480674
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_14                               0x480678
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_15                               0x48067C
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_0                                0x480680
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_1                                0x480684
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_2                                0x480688
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_3                                0x48068C
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_4                                0x480690
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_5                                0x480694
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_6                                0x480698
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_7                                0x48069C
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_8                                0x4806A0
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_9                                0x4806A4
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_10                               0x4806A8
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_11                               0x4806AC
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_12                               0x4806B0
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_13                               0x4806B4
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_14                               0x4806B8
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_15                               0x4806BC
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_0                                0x4806C0
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_1                                0x4806C4
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_2                                0x4806C8
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_3                                0x4806CC
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_4                                0x4806D0
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_5                                0x4806D4
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_6                                0x4806D8
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_7                                0x4806DC
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_8                                0x4806E0
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_9                                0x4806E4
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_10                               0x4806E8
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_11                               0x4806EC
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_12                               0x4806F0
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_13                               0x4806F4
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_14                               0x4806F8
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_15                               0x4806FC
+
+#define mmDMA_IF_W_S_SOB_HIT_RPROT                                   0x480700
+
+#define mmDMA_IF_W_S_SOB_HIT_WPROT                                   0x480704
+
+#define mmDMA_IF_W_S_SOB_HIT_RPRIV                                   0x48070C
+
+#define mmDMA_IF_W_S_SOB_HIT_WPRIV                                   0x480710
+
+#define mmDMA_IF_W_S_DMA0_HIT_RPROT                                  0x48071C
+
+#define mmDMA_IF_W_S_DMA0_HIT_WPROT                                  0x480720
+
+#define mmDMA_IF_W_S_DMA0_HIT_RPRIV                                  0x480724
+
+#define mmDMA_IF_W_S_DMA0_HIT_WPRIV                                  0x480728
+
+#define mmDMA_IF_W_S_DMA1_HIT_RPROT                                  0x480730
+
+#define mmDMA_IF_W_S_DMA1_HIT_WPROT                                  0x480734
+
+#define mmDMA_IF_W_S_DMA1_HIT_RPRIV                                  0x480738
+
+#define mmDMA_IF_W_S_DMA1_HIT_WPRIV                                  0x48073C
+
+#define mmDMA_IF_W_S_HBM_BIN                                         0x480800
+
+#define mmDMA_IF_W_S_MME_BIN                                         0x480804
+
+#define mmDMA_IF_W_S_TPC_BIN                                         0x480808
+
+#define mmDMA_IF_W_S_DMA_BIN                                         0x48080C
+
+#define mmDMA_IF_W_S_SOB_CG_EN                                       0x480810
+
+#define mmDMA_IF_W_S_HBM_I2C_ADDR_0                                  0x480820
+
+#define mmDMA_IF_W_S_HBM_I2C_ADDR_1                                  0x480824
+
+#define mmDMA_IF_W_S_HBM_I2C_ADDR_2                                  0x480828
+
+#define mmDMA_IF_W_S_HBM_I2C_ADDR_3                                  0x48082C
+
+#define mmDMA_IF_W_S_HBM_I2C_ADDR_4                                  0x480830
+
+#define mmDMA_IF_W_S_HBM_MISC                                        0x480834
+
+#endif /* ASIC_REG_DMA_IF_W_S_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/gaudi_blocks.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/gaudi_blocks.h
new file mode 100644
index 000000000000..c7596aac7a5c
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/gaudi_blocks.h
@@ -0,0 +1,4974 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef GAUDI_BLOCKS_H_
+#define GAUDI_BLOCKS_H_
+
+#define mmNIC0_PHY0_BASE                           0x0ull
+#define NIC0_PHY0_MAX_OFFSET                       0x9F13
+#define mmMME0_ACC_BASE                            0x7FFC020000ull
+#define MME0_ACC_MAX_OFFSET                        0x5C00
+#define MME0_ACC_SECTION                           0x20000
+#define mmMME0_SBAB_BASE                           0x7FFC040000ull
+#define MME0_SBAB_MAX_OFFSET                       0x5800
+#define MME0_SBAB_SECTION                          0x1000
+#define mmMME0_PRTN_BASE                           0x7FFC041000ull
+#define MME0_PRTN_MAX_OFFSET                       0x5000
+#define MME0_PRTN_SECTION                          0x1F000
+#define mmMME0_CTRL_BASE                           0x7FFC060000ull
+#define MME0_CTRL_MAX_OFFSET                       0xDA80
+#define MME0_CTRL_SECTION                          0x8000
+#define mmARCH_MME0_CTRL_BASE                      0x7FFC060008ull
+#define ARCH_MME0_CTRL_MAX_OFFSET                  0x3400
+#define ARCH_MME0_CTRL_SECTION                     0x3400
+#define mmARCH_TENSOR_S_MME0_CTRL_BASE             0x7FFC06003Cull
+#define ARCH_TENSOR_S_MME0_CTRL_MAX_OFFSET         0x4C00
+#define ARCH_TENSOR_S_MME0_CTRL_SECTION            0x4C00
+#define mmARCH_AGU_S_MME0_CTRL_BASE                0x7FFC060088ull
+#define ARCH_AGU_S_MME0_CTRL_MAX_OFFSET            0x2400
+#define ARCH_AGU_S_MME0_CTRL_SECTION               0x2400
+#define mmARCH_TENSOR_L_MME0_CTRL_BASE             0x7FFC0600ACull
+#define ARCH_TENSOR_L_MME0_CTRL_MAX_OFFSET         0x4C00
+#define ARCH_TENSOR_L_MME0_CTRL_SECTION            0x4C00
+#define mmARCH_AGU_L_LOCAL_MME0_CTRL_BASE          0x7FFC0600F8ull
+#define ARCH_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET      0x2400
+#define ARCH_AGU_L_LOCAL_MME0_CTRL_SECTION         0x2400
+#define mmARCH_AGU_L_REMOTE_MME0_CTRL_BASE         0x7FFC06011Cull
+#define ARCH_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET     0x2400
+#define ARCH_AGU_L_REMOTE_MME0_CTRL_SECTION        0x2400
+#define mmARCH_TENSOR_O_MME0_CTRL_BASE             0x7FFC060140ull
+#define ARCH_TENSOR_O_MME0_CTRL_MAX_OFFSET         0x4C00
+#define ARCH_TENSOR_O_MME0_CTRL_SECTION            0x4C00
+#define mmARCH_AGU_O_LOCAL_MME0_CTRL_BASE          0x7FFC06018Cull
+#define ARCH_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET      0x2400
+#define ARCH_AGU_O_LOCAL_MME0_CTRL_SECTION         0x2400
+#define mmARCH_AGU_O_REMOTE_MME0_CTRL_BASE         0x7FFC0601B0ull
+#define ARCH_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET     0x2400
+#define ARCH_AGU_O_REMOTE_MME0_CTRL_SECTION        0x2400
+#define mmARCH_DESC_MME0_CTRL_BASE                 0x7FFC0601D4ull
+#define ARCH_DESC_MME0_CTRL_MAX_OFFSET             0x5400
+#define ARCH_DESC_MME0_CTRL_SECTION                0x2340
+#define mmSHADOW_0_MME0_CTRL_BASE                  0x7FFC060408ull
+#define SHADOW_0_MME0_CTRL_MAX_OFFSET              0x3400
+#define SHADOW_0_MME0_CTRL_SECTION                 0x3400
+#define mmSHADOW_0_TENSOR_S_MME0_CTRL_BASE         0x7FFC06043Cull
+#define SHADOW_0_TENSOR_S_MME0_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_0_TENSOR_S_MME0_CTRL_SECTION        0x4C00
+#define mmSHADOW_0_AGU_S_MME0_CTRL_BASE            0x7FFC060488ull
+#define SHADOW_0_AGU_S_MME0_CTRL_MAX_OFFSET        0x2400
+#define SHADOW_0_AGU_S_MME0_CTRL_SECTION           0x2400
+#define mmSHADOW_0_TENSOR_L_MME0_CTRL_BASE         0x7FFC0604ACull
+#define SHADOW_0_TENSOR_L_MME0_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_0_TENSOR_L_MME0_CTRL_SECTION        0x4C00
+#define mmSHADOW_0_AGU_L_LOCAL_MME0_CTRL_BASE      0x7FFC0604F8ull
+#define SHADOW_0_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET  0x2400
+#define SHADOW_0_AGU_L_LOCAL_MME0_CTRL_SECTION     0x2400
+#define mmSHADOW_0_AGU_L_REMOTE_MME0_CTRL_BASE     0x7FFC06051Cull
+#define SHADOW_0_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_0_AGU_L_REMOTE_MME0_CTRL_SECTION    0x2400
+#define mmSHADOW_0_TENSOR_O_MME0_CTRL_BASE         0x7FFC060540ull
+#define SHADOW_0_TENSOR_O_MME0_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_0_TENSOR_O_MME0_CTRL_SECTION        0x4C00
+#define mmSHADOW_0_AGU_O_LOCAL_MME0_CTRL_BASE      0x7FFC06058Cull
+#define SHADOW_0_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET  0x2400
+#define SHADOW_0_AGU_O_LOCAL_MME0_CTRL_SECTION     0x2400
+#define mmSHADOW_0_AGU_O_REMOTE_MME0_CTRL_BASE     0x7FFC0605B0ull
+#define SHADOW_0_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_0_AGU_O_REMOTE_MME0_CTRL_SECTION    0x2400
+#define mmSHADOW_0_DESC_MME0_CTRL_BASE             0x7FFC0605D4ull
+#define SHADOW_0_DESC_MME0_CTRL_MAX_OFFSET         0x5400
+#define SHADOW_0_DESC_MME0_CTRL_SECTION            0xB400
+#define mmSHADOW_1_MME0_CTRL_BASE                  0x7FFC060688ull
+#define SHADOW_1_MME0_CTRL_MAX_OFFSET              0x3400
+#define SHADOW_1_MME0_CTRL_SECTION                 0x3400
+#define mmSHADOW_1_TENSOR_S_MME0_CTRL_BASE         0x7FFC0606BCull
+#define SHADOW_1_TENSOR_S_MME0_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_1_TENSOR_S_MME0_CTRL_SECTION        0x4C00
+#define mmSHADOW_1_AGU_S_MME0_CTRL_BASE            0x7FFC060708ull
+#define SHADOW_1_AGU_S_MME0_CTRL_MAX_OFFSET        0x2400
+#define SHADOW_1_AGU_S_MME0_CTRL_SECTION           0x2400
+#define mmSHADOW_1_TENSOR_L_MME0_CTRL_BASE         0x7FFC06072Cull
+#define SHADOW_1_TENSOR_L_MME0_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_1_TENSOR_L_MME0_CTRL_SECTION        0x4C00
+#define mmSHADOW_1_AGU_L_LOCAL_MME0_CTRL_BASE      0x7FFC060778ull
+#define SHADOW_1_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET  0x2400
+#define SHADOW_1_AGU_L_LOCAL_MME0_CTRL_SECTION     0x2400
+#define mmSHADOW_1_AGU_L_REMOTE_MME0_CTRL_BASE     0x7FFC06079Cull
+#define SHADOW_1_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_1_AGU_L_REMOTE_MME0_CTRL_SECTION    0x2400
+#define mmSHADOW_1_TENSOR_O_MME0_CTRL_BASE         0x7FFC0607C0ull
+#define SHADOW_1_TENSOR_O_MME0_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_1_TENSOR_O_MME0_CTRL_SECTION        0x4C00
+#define mmSHADOW_1_AGU_O_LOCAL_MME0_CTRL_BASE      0x7FFC06080Cull
+#define SHADOW_1_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET  0x2400
+#define SHADOW_1_AGU_O_LOCAL_MME0_CTRL_SECTION     0x2400
+#define mmSHADOW_1_AGU_O_REMOTE_MME0_CTRL_BASE     0x7FFC060830ull
+#define SHADOW_1_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_1_AGU_O_REMOTE_MME0_CTRL_SECTION    0x2400
+#define mmSHADOW_1_DESC_MME0_CTRL_BASE             0x7FFC060854ull
+#define SHADOW_1_DESC_MME0_CTRL_MAX_OFFSET         0x5400
+#define SHADOW_1_DESC_MME0_CTRL_SECTION            0xB400
+#define mmSHADOW_2_MME0_CTRL_BASE                  0x7FFC060908ull
+#define SHADOW_2_MME0_CTRL_MAX_OFFSET              0x3400
+#define SHADOW_2_MME0_CTRL_SECTION                 0x3400
+#define mmSHADOW_2_TENSOR_S_MME0_CTRL_BASE         0x7FFC06093Cull
+#define SHADOW_2_TENSOR_S_MME0_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_2_TENSOR_S_MME0_CTRL_SECTION        0x4C00
+#define mmSHADOW_2_AGU_S_MME0_CTRL_BASE            0x7FFC060988ull
+#define SHADOW_2_AGU_S_MME0_CTRL_MAX_OFFSET        0x2400
+#define SHADOW_2_AGU_S_MME0_CTRL_SECTION           0x2400
+#define mmSHADOW_2_TENSOR_L_MME0_CTRL_BASE         0x7FFC0609ACull
+#define SHADOW_2_TENSOR_L_MME0_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_2_TENSOR_L_MME0_CTRL_SECTION        0x4C00
+#define mmSHADOW_2_AGU_L_LOCAL_MME0_CTRL_BASE      0x7FFC0609F8ull
+#define SHADOW_2_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET  0x2400
+#define SHADOW_2_AGU_L_LOCAL_MME0_CTRL_SECTION     0x2400
+#define mmSHADOW_2_AGU_L_REMOTE_MME0_CTRL_BASE     0x7FFC060A1Cull
+#define SHADOW_2_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_2_AGU_L_REMOTE_MME0_CTRL_SECTION    0x2400
+#define mmSHADOW_2_TENSOR_O_MME0_CTRL_BASE         0x7FFC060A40ull
+#define SHADOW_2_TENSOR_O_MME0_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_2_TENSOR_O_MME0_CTRL_SECTION        0x4C00
+#define mmSHADOW_2_AGU_O_LOCAL_MME0_CTRL_BASE      0x7FFC060A8Cull
+#define SHADOW_2_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET  0x2400
+#define SHADOW_2_AGU_O_LOCAL_MME0_CTRL_SECTION     0x2400
+#define mmSHADOW_2_AGU_O_REMOTE_MME0_CTRL_BASE     0x7FFC060AB0ull
+#define SHADOW_2_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_2_AGU_O_REMOTE_MME0_CTRL_SECTION    0x2400
+#define mmSHADOW_2_DESC_MME0_CTRL_BASE             0x7FFC060AD4ull
+#define SHADOW_2_DESC_MME0_CTRL_MAX_OFFSET         0x5400
+#define SHADOW_2_DESC_MME0_CTRL_SECTION            0xB400
+#define mmSHADOW_3_MME0_CTRL_BASE                  0x7FFC060B88ull
+#define SHADOW_3_MME0_CTRL_MAX_OFFSET              0x3400
+#define SHADOW_3_MME0_CTRL_SECTION                 0x3400
+#define mmSHADOW_3_TENSOR_S_MME0_CTRL_BASE         0x7FFC060BBCull
+#define SHADOW_3_TENSOR_S_MME0_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_3_TENSOR_S_MME0_CTRL_SECTION        0x4C00
+#define mmSHADOW_3_AGU_S_MME0_CTRL_BASE            0x7FFC060C08ull
+#define SHADOW_3_AGU_S_MME0_CTRL_MAX_OFFSET        0x2400
+#define SHADOW_3_AGU_S_MME0_CTRL_SECTION           0x2400
+#define mmSHADOW_3_TENSOR_L_MME0_CTRL_BASE         0x7FFC060C2Cull
+#define SHADOW_3_TENSOR_L_MME0_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_3_TENSOR_L_MME0_CTRL_SECTION        0x4C00
+#define mmSHADOW_3_AGU_L_LOCAL_MME0_CTRL_BASE      0x7FFC060C78ull
+#define SHADOW_3_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET  0x2400
+#define SHADOW_3_AGU_L_LOCAL_MME0_CTRL_SECTION     0x2400
+#define mmSHADOW_3_AGU_L_REMOTE_MME0_CTRL_BASE     0x7FFC060C9Cull
+#define SHADOW_3_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_3_AGU_L_REMOTE_MME0_CTRL_SECTION    0x2400
+#define mmSHADOW_3_TENSOR_O_MME0_CTRL_BASE         0x7FFC060CC0ull
+#define SHADOW_3_TENSOR_O_MME0_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_3_TENSOR_O_MME0_CTRL_SECTION        0x4C00
+#define mmSHADOW_3_AGU_O_LOCAL_MME0_CTRL_BASE      0x7FFC060D0Cull
+#define SHADOW_3_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET  0x2400
+#define SHADOW_3_AGU_O_LOCAL_MME0_CTRL_SECTION     0x2400
+#define mmSHADOW_3_AGU_O_REMOTE_MME0_CTRL_BASE     0x7FFC060D30ull
+#define SHADOW_3_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_3_AGU_O_REMOTE_MME0_CTRL_SECTION    0x2400
+#define mmSHADOW_3_DESC_MME0_CTRL_BASE             0x7FFC060D54ull
+#define SHADOW_3_DESC_MME0_CTRL_MAX_OFFSET         0x5400
+#define SHADOW_3_DESC_MME0_CTRL_SECTION            0x72AC
+#define mmMME0_QM_BASE                             0x7FFC068000ull
+#define MME0_QM_MAX_OFFSET                         0xD040
+#define MME0_QM_SECTION                            0x38000
+#define mmMME1_ACC_BASE                            0x7FFC0A0000ull
+#define MME1_ACC_MAX_OFFSET                        0x5C00
+#define MME1_ACC_SECTION                           0x20000
+#define mmMME1_SBAB_BASE                           0x7FFC0C0000ull
+#define MME1_SBAB_MAX_OFFSET                       0x5800
+#define MME1_SBAB_SECTION                          0x1000
+#define mmMME1_PRTN_BASE                           0x7FFC0C1000ull
+#define MME1_PRTN_MAX_OFFSET                       0x5000
+#define MME1_PRTN_SECTION                          0x1F000
+#define mmMME1_CTRL_BASE                           0x7FFC0E0000ull
+#define MME1_CTRL_MAX_OFFSET                       0xDA80
+#define MME1_CTRL_SECTION                          0x8000
+#define mmARCH_MME1_CTRL_BASE                      0x7FFC0E0008ull
+#define ARCH_MME1_CTRL_MAX_OFFSET                  0x3400
+#define ARCH_MME1_CTRL_SECTION                     0x3400
+#define mmARCH_TENSOR_S_MME1_CTRL_BASE             0x7FFC0E003Cull
+#define ARCH_TENSOR_S_MME1_CTRL_MAX_OFFSET         0x4C00
+#define ARCH_TENSOR_S_MME1_CTRL_SECTION            0x4C00
+#define mmARCH_AGU_S_MME1_CTRL_BASE                0x7FFC0E0088ull
+#define ARCH_AGU_S_MME1_CTRL_MAX_OFFSET            0x2400
+#define ARCH_AGU_S_MME1_CTRL_SECTION               0x2400
+#define mmARCH_TENSOR_L_MME1_CTRL_BASE             0x7FFC0E00ACull
+#define ARCH_TENSOR_L_MME1_CTRL_MAX_OFFSET         0x4C00
+#define ARCH_TENSOR_L_MME1_CTRL_SECTION            0x4C00
+#define mmARCH_AGU_L_LOCAL_MME1_CTRL_BASE          0x7FFC0E00F8ull
+#define ARCH_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET      0x2400
+#define ARCH_AGU_L_LOCAL_MME1_CTRL_SECTION         0x2400
+#define mmARCH_AGU_L_REMOTE_MME1_CTRL_BASE         0x7FFC0E011Cull
+#define ARCH_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET     0x2400
+#define ARCH_AGU_L_REMOTE_MME1_CTRL_SECTION        0x2400
+#define mmARCH_TENSOR_O_MME1_CTRL_BASE             0x7FFC0E0140ull
+#define ARCH_TENSOR_O_MME1_CTRL_MAX_OFFSET         0x4C00
+#define ARCH_TENSOR_O_MME1_CTRL_SECTION            0x4C00
+#define mmARCH_AGU_O_LOCAL_MME1_CTRL_BASE          0x7FFC0E018Cull
+#define ARCH_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET      0x2400
+#define ARCH_AGU_O_LOCAL_MME1_CTRL_SECTION         0x2400
+#define mmARCH_AGU_O_REMOTE_MME1_CTRL_BASE         0x7FFC0E01B0ull
+#define ARCH_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET     0x2400
+#define ARCH_AGU_O_REMOTE_MME1_CTRL_SECTION        0x2400
+#define mmARCH_DESC_MME1_CTRL_BASE                 0x7FFC0E01D4ull
+#define ARCH_DESC_MME1_CTRL_MAX_OFFSET             0x5400
+#define ARCH_DESC_MME1_CTRL_SECTION                0x2340
+#define mmSHADOW_0_MME1_CTRL_BASE                  0x7FFC0E0408ull
+#define SHADOW_0_MME1_CTRL_MAX_OFFSET              0x3400
+#define SHADOW_0_MME1_CTRL_SECTION                 0x3400
+#define mmSHADOW_0_TENSOR_S_MME1_CTRL_BASE         0x7FFC0E043Cull
+#define SHADOW_0_TENSOR_S_MME1_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_0_TENSOR_S_MME1_CTRL_SECTION        0x4C00
+#define mmSHADOW_0_AGU_S_MME1_CTRL_BASE            0x7FFC0E0488ull
+#define SHADOW_0_AGU_S_MME1_CTRL_MAX_OFFSET        0x2400
+#define SHADOW_0_AGU_S_MME1_CTRL_SECTION           0x2400
+#define mmSHADOW_0_TENSOR_L_MME1_CTRL_BASE         0x7FFC0E04ACull
+#define SHADOW_0_TENSOR_L_MME1_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_0_TENSOR_L_MME1_CTRL_SECTION        0x4C00
+#define mmSHADOW_0_AGU_L_LOCAL_MME1_CTRL_BASE      0x7FFC0E04F8ull
+#define SHADOW_0_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET  0x2400
+#define SHADOW_0_AGU_L_LOCAL_MME1_CTRL_SECTION     0x2400
+#define mmSHADOW_0_AGU_L_REMOTE_MME1_CTRL_BASE     0x7FFC0E051Cull
+#define SHADOW_0_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_0_AGU_L_REMOTE_MME1_CTRL_SECTION    0x2400
+#define mmSHADOW_0_TENSOR_O_MME1_CTRL_BASE         0x7FFC0E0540ull
+#define SHADOW_0_TENSOR_O_MME1_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_0_TENSOR_O_MME1_CTRL_SECTION        0x4C00
+#define mmSHADOW_0_AGU_O_LOCAL_MME1_CTRL_BASE      0x7FFC0E058Cull
+#define SHADOW_0_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET  0x2400
+#define SHADOW_0_AGU_O_LOCAL_MME1_CTRL_SECTION     0x2400
+#define mmSHADOW_0_AGU_O_REMOTE_MME1_CTRL_BASE     0x7FFC0E05B0ull
+#define SHADOW_0_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_0_AGU_O_REMOTE_MME1_CTRL_SECTION    0x2400
+#define mmSHADOW_0_DESC_MME1_CTRL_BASE             0x7FFC0E05D4ull
+#define SHADOW_0_DESC_MME1_CTRL_MAX_OFFSET         0x5400
+#define SHADOW_0_DESC_MME1_CTRL_SECTION            0xB400
+#define mmSHADOW_1_MME1_CTRL_BASE                  0x7FFC0E0688ull
+#define SHADOW_1_MME1_CTRL_MAX_OFFSET              0x3400
+#define SHADOW_1_MME1_CTRL_SECTION                 0x3400
+#define mmSHADOW_1_TENSOR_S_MME1_CTRL_BASE         0x7FFC0E06BCull
+#define SHADOW_1_TENSOR_S_MME1_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_1_TENSOR_S_MME1_CTRL_SECTION        0x4C00
+#define mmSHADOW_1_AGU_S_MME1_CTRL_BASE            0x7FFC0E0708ull
+#define SHADOW_1_AGU_S_MME1_CTRL_MAX_OFFSET        0x2400
+#define SHADOW_1_AGU_S_MME1_CTRL_SECTION           0x2400
+#define mmSHADOW_1_TENSOR_L_MME1_CTRL_BASE         0x7FFC0E072Cull
+#define SHADOW_1_TENSOR_L_MME1_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_1_TENSOR_L_MME1_CTRL_SECTION        0x4C00
+#define mmSHADOW_1_AGU_L_LOCAL_MME1_CTRL_BASE      0x7FFC0E0778ull
+#define SHADOW_1_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET  0x2400
+#define SHADOW_1_AGU_L_LOCAL_MME1_CTRL_SECTION     0x2400
+#define mmSHADOW_1_AGU_L_REMOTE_MME1_CTRL_BASE     0x7FFC0E079Cull
+#define SHADOW_1_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_1_AGU_L_REMOTE_MME1_CTRL_SECTION    0x2400
+#define mmSHADOW_1_TENSOR_O_MME1_CTRL_BASE         0x7FFC0E07C0ull
+#define SHADOW_1_TENSOR_O_MME1_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_1_TENSOR_O_MME1_CTRL_SECTION        0x4C00
+#define mmSHADOW_1_AGU_O_LOCAL_MME1_CTRL_BASE      0x7FFC0E080Cull
+#define SHADOW_1_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET  0x2400
+#define SHADOW_1_AGU_O_LOCAL_MME1_CTRL_SECTION     0x2400
+#define mmSHADOW_1_AGU_O_REMOTE_MME1_CTRL_BASE     0x7FFC0E0830ull
+#define SHADOW_1_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_1_AGU_O_REMOTE_MME1_CTRL_SECTION    0x2400
+#define mmSHADOW_1_DESC_MME1_CTRL_BASE             0x7FFC0E0854ull
+#define SHADOW_1_DESC_MME1_CTRL_MAX_OFFSET         0x5400
+#define SHADOW_1_DESC_MME1_CTRL_SECTION            0xB400
+#define mmSHADOW_2_MME1_CTRL_BASE                  0x7FFC0E0908ull
+#define SHADOW_2_MME1_CTRL_MAX_OFFSET              0x3400
+#define SHADOW_2_MME1_CTRL_SECTION                 0x3400
+#define mmSHADOW_2_TENSOR_S_MME1_CTRL_BASE         0x7FFC0E093Cull
+#define SHADOW_2_TENSOR_S_MME1_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_2_TENSOR_S_MME1_CTRL_SECTION        0x4C00
+#define mmSHADOW_2_AGU_S_MME1_CTRL_BASE            0x7FFC0E0988ull
+#define SHADOW_2_AGU_S_MME1_CTRL_MAX_OFFSET        0x2400
+#define SHADOW_2_AGU_S_MME1_CTRL_SECTION           0x2400
+#define mmSHADOW_2_TENSOR_L_MME1_CTRL_BASE         0x7FFC0E09ACull
+#define SHADOW_2_TENSOR_L_MME1_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_2_TENSOR_L_MME1_CTRL_SECTION        0x4C00
+#define mmSHADOW_2_AGU_L_LOCAL_MME1_CTRL_BASE      0x7FFC0E09F8ull
+#define SHADOW_2_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET  0x2400
+#define SHADOW_2_AGU_L_LOCAL_MME1_CTRL_SECTION     0x2400
+#define mmSHADOW_2_AGU_L_REMOTE_MME1_CTRL_BASE     0x7FFC0E0A1Cull
+#define SHADOW_2_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_2_AGU_L_REMOTE_MME1_CTRL_SECTION    0x2400
+#define mmSHADOW_2_TENSOR_O_MME1_CTRL_BASE         0x7FFC0E0A40ull
+#define SHADOW_2_TENSOR_O_MME1_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_2_TENSOR_O_MME1_CTRL_SECTION        0x4C00
+#define mmSHADOW_2_AGU_O_LOCAL_MME1_CTRL_BASE      0x7FFC0E0A8Cull
+#define SHADOW_2_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET  0x2400
+#define SHADOW_2_AGU_O_LOCAL_MME1_CTRL_SECTION     0x2400
+#define mmSHADOW_2_AGU_O_REMOTE_MME1_CTRL_BASE     0x7FFC0E0AB0ull
+#define SHADOW_2_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_2_AGU_O_REMOTE_MME1_CTRL_SECTION    0x2400
+#define mmSHADOW_2_DESC_MME1_CTRL_BASE             0x7FFC0E0AD4ull
+#define SHADOW_2_DESC_MME1_CTRL_MAX_OFFSET         0x5400
+#define SHADOW_2_DESC_MME1_CTRL_SECTION            0xB400
+#define mmSHADOW_3_MME1_CTRL_BASE                  0x7FFC0E0B88ull
+#define SHADOW_3_MME1_CTRL_MAX_OFFSET              0x3400
+#define SHADOW_3_MME1_CTRL_SECTION                 0x3400
+#define mmSHADOW_3_TENSOR_S_MME1_CTRL_BASE         0x7FFC0E0BBCull
+#define SHADOW_3_TENSOR_S_MME1_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_3_TENSOR_S_MME1_CTRL_SECTION        0x4C00
+#define mmSHADOW_3_AGU_S_MME1_CTRL_BASE            0x7FFC0E0C08ull
+#define SHADOW_3_AGU_S_MME1_CTRL_MAX_OFFSET        0x2400
+#define SHADOW_3_AGU_S_MME1_CTRL_SECTION           0x2400
+#define mmSHADOW_3_TENSOR_L_MME1_CTRL_BASE         0x7FFC0E0C2Cull
+#define SHADOW_3_TENSOR_L_MME1_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_3_TENSOR_L_MME1_CTRL_SECTION        0x4C00
+#define mmSHADOW_3_AGU_L_LOCAL_MME1_CTRL_BASE      0x7FFC0E0C78ull
+#define SHADOW_3_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET  0x2400
+#define SHADOW_3_AGU_L_LOCAL_MME1_CTRL_SECTION     0x2400
+#define mmSHADOW_3_AGU_L_REMOTE_MME1_CTRL_BASE     0x7FFC0E0C9Cull
+#define SHADOW_3_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_3_AGU_L_REMOTE_MME1_CTRL_SECTION    0x2400
+#define mmSHADOW_3_TENSOR_O_MME1_CTRL_BASE         0x7FFC0E0CC0ull
+#define SHADOW_3_TENSOR_O_MME1_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_3_TENSOR_O_MME1_CTRL_SECTION        0x4C00
+#define mmSHADOW_3_AGU_O_LOCAL_MME1_CTRL_BASE      0x7FFC0E0D0Cull
+#define SHADOW_3_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET  0x2400
+#define SHADOW_3_AGU_O_LOCAL_MME1_CTRL_SECTION     0x2400
+#define mmSHADOW_3_AGU_O_REMOTE_MME1_CTRL_BASE     0x7FFC0E0D30ull
+#define SHADOW_3_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_3_AGU_O_REMOTE_MME1_CTRL_SECTION    0x2400
+#define mmSHADOW_3_DESC_MME1_CTRL_BASE             0x7FFC0E0D54ull
+#define SHADOW_3_DESC_MME1_CTRL_MAX_OFFSET         0x5400
+#define SHADOW_3_DESC_MME1_CTRL_SECTION            0x72AC
+#define mmMME1_QM_BASE                             0x7FFC0E8000ull
+#define MME1_QM_MAX_OFFSET                         0xD040
+#define MME1_QM_SECTION                            0x38000
+#define mmMME2_ACC_BASE                            0x7FFC120000ull
+#define MME2_ACC_MAX_OFFSET                        0x5C00
+#define MME2_ACC_SECTION                           0x20000
+#define mmMME2_SBAB_BASE                           0x7FFC140000ull
+#define MME2_SBAB_MAX_OFFSET                       0x5800
+#define MME2_SBAB_SECTION                          0x1000
+#define mmMME2_PRTN_BASE                           0x7FFC141000ull
+#define MME2_PRTN_MAX_OFFSET                       0x5000
+#define MME2_PRTN_SECTION                          0x1F000
+#define mmMME2_CTRL_BASE                           0x7FFC160000ull
+#define MME2_CTRL_MAX_OFFSET                       0xDA80
+#define MME2_CTRL_SECTION                          0x8000
+#define mmARCH_MME2_CTRL_BASE                      0x7FFC160008ull
+#define ARCH_MME2_CTRL_MAX_OFFSET                  0x3400
+#define ARCH_MME2_CTRL_SECTION                     0x3400
+#define mmARCH_TENSOR_S_MME2_CTRL_BASE             0x7FFC16003Cull
+#define ARCH_TENSOR_S_MME2_CTRL_MAX_OFFSET         0x4C00
+#define ARCH_TENSOR_S_MME2_CTRL_SECTION            0x4C00
+#define mmARCH_AGU_S_MME2_CTRL_BASE                0x7FFC160088ull
+#define ARCH_AGU_S_MME2_CTRL_MAX_OFFSET            0x2400
+#define ARCH_AGU_S_MME2_CTRL_SECTION               0x2400
+#define mmARCH_TENSOR_L_MME2_CTRL_BASE             0x7FFC1600ACull
+#define ARCH_TENSOR_L_MME2_CTRL_MAX_OFFSET         0x4C00
+#define ARCH_TENSOR_L_MME2_CTRL_SECTION            0x4C00
+#define mmARCH_AGU_L_LOCAL_MME2_CTRL_BASE          0x7FFC1600F8ull
+#define ARCH_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET      0x2400
+#define ARCH_AGU_L_LOCAL_MME2_CTRL_SECTION         0x2400
+#define mmARCH_AGU_L_REMOTE_MME2_CTRL_BASE         0x7FFC16011Cull
+#define ARCH_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET     0x2400
+#define ARCH_AGU_L_REMOTE_MME2_CTRL_SECTION        0x2400
+#define mmARCH_TENSOR_O_MME2_CTRL_BASE             0x7FFC160140ull
+#define ARCH_TENSOR_O_MME2_CTRL_MAX_OFFSET         0x4C00
+#define ARCH_TENSOR_O_MME2_CTRL_SECTION            0x4C00
+#define mmARCH_AGU_O_LOCAL_MME2_CTRL_BASE          0x7FFC16018Cull
+#define ARCH_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET      0x2400
+#define ARCH_AGU_O_LOCAL_MME2_CTRL_SECTION         0x2400
+#define mmARCH_AGU_O_REMOTE_MME2_CTRL_BASE         0x7FFC1601B0ull
+#define ARCH_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET     0x2400
+#define ARCH_AGU_O_REMOTE_MME2_CTRL_SECTION        0x2400
+#define mmARCH_DESC_MME2_CTRL_BASE                 0x7FFC1601D4ull
+#define ARCH_DESC_MME2_CTRL_MAX_OFFSET             0x5400
+#define ARCH_DESC_MME2_CTRL_SECTION                0x2340
+#define mmSHADOW_0_MME2_CTRL_BASE                  0x7FFC160408ull
+#define SHADOW_0_MME2_CTRL_MAX_OFFSET              0x3400
+#define SHADOW_0_MME2_CTRL_SECTION                 0x3400
+#define mmSHADOW_0_TENSOR_S_MME2_CTRL_BASE         0x7FFC16043Cull
+#define SHADOW_0_TENSOR_S_MME2_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_0_TENSOR_S_MME2_CTRL_SECTION        0x4C00
+#define mmSHADOW_0_AGU_S_MME2_CTRL_BASE            0x7FFC160488ull
+#define SHADOW_0_AGU_S_MME2_CTRL_MAX_OFFSET        0x2400
+#define SHADOW_0_AGU_S_MME2_CTRL_SECTION           0x2400
+#define mmSHADOW_0_TENSOR_L_MME2_CTRL_BASE         0x7FFC1604ACull
+#define SHADOW_0_TENSOR_L_MME2_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_0_TENSOR_L_MME2_CTRL_SECTION        0x4C00
+#define mmSHADOW_0_AGU_L_LOCAL_MME2_CTRL_BASE      0x7FFC1604F8ull
+#define SHADOW_0_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET  0x2400
+#define SHADOW_0_AGU_L_LOCAL_MME2_CTRL_SECTION     0x2400
+#define mmSHADOW_0_AGU_L_REMOTE_MME2_CTRL_BASE     0x7FFC16051Cull
+#define SHADOW_0_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_0_AGU_L_REMOTE_MME2_CTRL_SECTION    0x2400
+#define mmSHADOW_0_TENSOR_O_MME2_CTRL_BASE         0x7FFC160540ull
+#define SHADOW_0_TENSOR_O_MME2_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_0_TENSOR_O_MME2_CTRL_SECTION        0x4C00
+#define mmSHADOW_0_AGU_O_LOCAL_MME2_CTRL_BASE      0x7FFC16058Cull
+#define SHADOW_0_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET  0x2400
+#define SHADOW_0_AGU_O_LOCAL_MME2_CTRL_SECTION     0x2400
+#define mmSHADOW_0_AGU_O_REMOTE_MME2_CTRL_BASE     0x7FFC1605B0ull
+#define SHADOW_0_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_0_AGU_O_REMOTE_MME2_CTRL_SECTION    0x2400
+#define mmSHADOW_0_DESC_MME2_CTRL_BASE             0x7FFC1605D4ull
+#define SHADOW_0_DESC_MME2_CTRL_MAX_OFFSET         0x5400
+#define SHADOW_0_DESC_MME2_CTRL_SECTION            0xB400
+#define mmSHADOW_1_MME2_CTRL_BASE                  0x7FFC160688ull
+#define SHADOW_1_MME2_CTRL_MAX_OFFSET              0x3400
+#define SHADOW_1_MME2_CTRL_SECTION                 0x3400
+#define mmSHADOW_1_TENSOR_S_MME2_CTRL_BASE         0x7FFC1606BCull
+#define SHADOW_1_TENSOR_S_MME2_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_1_TENSOR_S_MME2_CTRL_SECTION        0x4C00
+#define mmSHADOW_1_AGU_S_MME2_CTRL_BASE            0x7FFC160708ull
+#define SHADOW_1_AGU_S_MME2_CTRL_MAX_OFFSET        0x2400
+#define SHADOW_1_AGU_S_MME2_CTRL_SECTION           0x2400
+#define mmSHADOW_1_TENSOR_L_MME2_CTRL_BASE         0x7FFC16072Cull
+#define SHADOW_1_TENSOR_L_MME2_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_1_TENSOR_L_MME2_CTRL_SECTION        0x4C00
+#define mmSHADOW_1_AGU_L_LOCAL_MME2_CTRL_BASE      0x7FFC160778ull
+#define SHADOW_1_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET  0x2400
+#define SHADOW_1_AGU_L_LOCAL_MME2_CTRL_SECTION     0x2400
+#define mmSHADOW_1_AGU_L_REMOTE_MME2_CTRL_BASE     0x7FFC16079Cull
+#define SHADOW_1_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_1_AGU_L_REMOTE_MME2_CTRL_SECTION    0x2400
+#define mmSHADOW_1_TENSOR_O_MME2_CTRL_BASE         0x7FFC1607C0ull
+#define SHADOW_1_TENSOR_O_MME2_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_1_TENSOR_O_MME2_CTRL_SECTION        0x4C00
+#define mmSHADOW_1_AGU_O_LOCAL_MME2_CTRL_BASE      0x7FFC16080Cull
+#define SHADOW_1_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET  0x2400
+#define SHADOW_1_AGU_O_LOCAL_MME2_CTRL_SECTION     0x2400
+#define mmSHADOW_1_AGU_O_REMOTE_MME2_CTRL_BASE     0x7FFC160830ull
+#define SHADOW_1_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_1_AGU_O_REMOTE_MME2_CTRL_SECTION    0x2400
+#define mmSHADOW_1_DESC_MME2_CTRL_BASE             0x7FFC160854ull
+#define SHADOW_1_DESC_MME2_CTRL_MAX_OFFSET         0x5400
+#define SHADOW_1_DESC_MME2_CTRL_SECTION            0xB400
+#define mmSHADOW_2_MME2_CTRL_BASE                  0x7FFC160908ull
+#define SHADOW_2_MME2_CTRL_MAX_OFFSET              0x3400
+#define SHADOW_2_MME2_CTRL_SECTION                 0x3400
+#define mmSHADOW_2_TENSOR_S_MME2_CTRL_BASE         0x7FFC16093Cull
+#define SHADOW_2_TENSOR_S_MME2_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_2_TENSOR_S_MME2_CTRL_SECTION        0x4C00
+#define mmSHADOW_2_AGU_S_MME2_CTRL_BASE            0x7FFC160988ull
+#define SHADOW_2_AGU_S_MME2_CTRL_MAX_OFFSET        0x2400
+#define SHADOW_2_AGU_S_MME2_CTRL_SECTION           0x2400
+#define mmSHADOW_2_TENSOR_L_MME2_CTRL_BASE         0x7FFC1609ACull
+#define SHADOW_2_TENSOR_L_MME2_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_2_TENSOR_L_MME2_CTRL_SECTION        0x4C00
+#define mmSHADOW_2_AGU_L_LOCAL_MME2_CTRL_BASE      0x7FFC1609F8ull
+#define SHADOW_2_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET  0x2400
+#define SHADOW_2_AGU_L_LOCAL_MME2_CTRL_SECTION     0x2400
+#define mmSHADOW_2_AGU_L_REMOTE_MME2_CTRL_BASE     0x7FFC160A1Cull
+#define SHADOW_2_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_2_AGU_L_REMOTE_MME2_CTRL_SECTION    0x2400
+#define mmSHADOW_2_TENSOR_O_MME2_CTRL_BASE         0x7FFC160A40ull
+#define SHADOW_2_TENSOR_O_MME2_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_2_TENSOR_O_MME2_CTRL_SECTION        0x4C00
+#define mmSHADOW_2_AGU_O_LOCAL_MME2_CTRL_BASE      0x7FFC160A8Cull
+#define SHADOW_2_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET  0x2400
+#define SHADOW_2_AGU_O_LOCAL_MME2_CTRL_SECTION     0x2400
+#define mmSHADOW_2_AGU_O_REMOTE_MME2_CTRL_BASE     0x7FFC160AB0ull
+#define SHADOW_2_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_2_AGU_O_REMOTE_MME2_CTRL_SECTION    0x2400
+#define mmSHADOW_2_DESC_MME2_CTRL_BASE             0x7FFC160AD4ull
+#define SHADOW_2_DESC_MME2_CTRL_MAX_OFFSET         0x5400
+#define SHADOW_2_DESC_MME2_CTRL_SECTION            0xB400
+#define mmSHADOW_3_MME2_CTRL_BASE                  0x7FFC160B88ull
+#define SHADOW_3_MME2_CTRL_MAX_OFFSET              0x3400
+#define SHADOW_3_MME2_CTRL_SECTION                 0x3400
+#define mmSHADOW_3_TENSOR_S_MME2_CTRL_BASE         0x7FFC160BBCull
+#define SHADOW_3_TENSOR_S_MME2_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_3_TENSOR_S_MME2_CTRL_SECTION        0x4C00
+#define mmSHADOW_3_AGU_S_MME2_CTRL_BASE            0x7FFC160C08ull
+#define SHADOW_3_AGU_S_MME2_CTRL_MAX_OFFSET        0x2400
+#define SHADOW_3_AGU_S_MME2_CTRL_SECTION           0x2400
+#define mmSHADOW_3_TENSOR_L_MME2_CTRL_BASE         0x7FFC160C2Cull
+#define SHADOW_3_TENSOR_L_MME2_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_3_TENSOR_L_MME2_CTRL_SECTION        0x4C00
+#define mmSHADOW_3_AGU_L_LOCAL_MME2_CTRL_BASE      0x7FFC160C78ull
+#define SHADOW_3_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET  0x2400
+#define SHADOW_3_AGU_L_LOCAL_MME2_CTRL_SECTION     0x2400
+#define mmSHADOW_3_AGU_L_REMOTE_MME2_CTRL_BASE     0x7FFC160C9Cull
+#define SHADOW_3_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_3_AGU_L_REMOTE_MME2_CTRL_SECTION    0x2400
+#define mmSHADOW_3_TENSOR_O_MME2_CTRL_BASE         0x7FFC160CC0ull
+#define SHADOW_3_TENSOR_O_MME2_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_3_TENSOR_O_MME2_CTRL_SECTION        0x4C00
+#define mmSHADOW_3_AGU_O_LOCAL_MME2_CTRL_BASE      0x7FFC160D0Cull
+#define SHADOW_3_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET  0x2400
+#define SHADOW_3_AGU_O_LOCAL_MME2_CTRL_SECTION     0x2400
+#define mmSHADOW_3_AGU_O_REMOTE_MME2_CTRL_BASE     0x7FFC160D30ull
+#define SHADOW_3_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_3_AGU_O_REMOTE_MME2_CTRL_SECTION    0x2400
+#define mmSHADOW_3_DESC_MME2_CTRL_BASE             0x7FFC160D54ull
+#define SHADOW_3_DESC_MME2_CTRL_MAX_OFFSET         0x5400
+#define SHADOW_3_DESC_MME2_CTRL_SECTION            0x72AC
+#define mmMME2_QM_BASE                             0x7FFC168000ull
+#define MME2_QM_MAX_OFFSET                         0xD040
+#define MME2_QM_SECTION                            0x38000
+#define mmMME3_ACC_BASE                            0x7FFC1A0000ull
+#define MME3_ACC_MAX_OFFSET                        0x5C00
+#define MME3_ACC_SECTION                           0x20000
+#define mmMME3_SBAB_BASE                           0x7FFC1C0000ull
+#define MME3_SBAB_MAX_OFFSET                       0x5800
+#define MME3_SBAB_SECTION                          0x1000
+#define mmMME3_PRTN_BASE                           0x7FFC1C1000ull
+#define MME3_PRTN_MAX_OFFSET                       0x5000
+#define MME3_PRTN_SECTION                          0x1F000
+#define mmMME3_CTRL_BASE                           0x7FFC1E0000ull
+#define MME3_CTRL_MAX_OFFSET                       0xDA80
+#define MME3_CTRL_SECTION                          0x8000
+#define mmARCH_MME3_CTRL_BASE                      0x7FFC1E0008ull
+#define ARCH_MME3_CTRL_MAX_OFFSET                  0x3400
+#define ARCH_MME3_CTRL_SECTION                     0x3400
+#define mmARCH_TENSOR_S_MME3_CTRL_BASE             0x7FFC1E003Cull
+#define ARCH_TENSOR_S_MME3_CTRL_MAX_OFFSET         0x4C00
+#define ARCH_TENSOR_S_MME3_CTRL_SECTION            0x4C00
+#define mmARCH_AGU_S_MME3_CTRL_BASE                0x7FFC1E0088ull
+#define ARCH_AGU_S_MME3_CTRL_MAX_OFFSET            0x2400
+#define ARCH_AGU_S_MME3_CTRL_SECTION               0x2400
+#define mmARCH_TENSOR_L_MME3_CTRL_BASE             0x7FFC1E00ACull
+#define ARCH_TENSOR_L_MME3_CTRL_MAX_OFFSET         0x4C00
+#define ARCH_TENSOR_L_MME3_CTRL_SECTION            0x4C00
+#define mmARCH_AGU_L_LOCAL_MME3_CTRL_BASE          0x7FFC1E00F8ull
+#define ARCH_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET      0x2400
+#define ARCH_AGU_L_LOCAL_MME3_CTRL_SECTION         0x2400
+#define mmARCH_AGU_L_REMOTE_MME3_CTRL_BASE         0x7FFC1E011Cull
+#define ARCH_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET     0x2400
+#define ARCH_AGU_L_REMOTE_MME3_CTRL_SECTION        0x2400
+#define mmARCH_TENSOR_O_MME3_CTRL_BASE             0x7FFC1E0140ull
+#define ARCH_TENSOR_O_MME3_CTRL_MAX_OFFSET         0x4C00
+#define ARCH_TENSOR_O_MME3_CTRL_SECTION            0x4C00
+#define mmARCH_AGU_O_LOCAL_MME3_CTRL_BASE          0x7FFC1E018Cull
+#define ARCH_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET      0x2400
+#define ARCH_AGU_O_LOCAL_MME3_CTRL_SECTION         0x2400
+#define mmARCH_AGU_O_REMOTE_MME3_CTRL_BASE         0x7FFC1E01B0ull
+#define ARCH_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET     0x2400
+#define ARCH_AGU_O_REMOTE_MME3_CTRL_SECTION        0x2400
+#define mmARCH_DESC_MME3_CTRL_BASE                 0x7FFC1E01D4ull
+#define ARCH_DESC_MME3_CTRL_MAX_OFFSET             0x5400
+#define ARCH_DESC_MME3_CTRL_SECTION                0x2340
+#define mmSHADOW_0_MME3_CTRL_BASE                  0x7FFC1E0408ull
+#define SHADOW_0_MME3_CTRL_MAX_OFFSET              0x3400
+#define SHADOW_0_MME3_CTRL_SECTION                 0x3400
+#define mmSHADOW_0_TENSOR_S_MME3_CTRL_BASE         0x7FFC1E043Cull
+#define SHADOW_0_TENSOR_S_MME3_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_0_TENSOR_S_MME3_CTRL_SECTION        0x4C00
+#define mmSHADOW_0_AGU_S_MME3_CTRL_BASE            0x7FFC1E0488ull
+#define SHADOW_0_AGU_S_MME3_CTRL_MAX_OFFSET        0x2400
+#define SHADOW_0_AGU_S_MME3_CTRL_SECTION           0x2400
+#define mmSHADOW_0_TENSOR_L_MME3_CTRL_BASE         0x7FFC1E04ACull
+#define SHADOW_0_TENSOR_L_MME3_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_0_TENSOR_L_MME3_CTRL_SECTION        0x4C00
+#define mmSHADOW_0_AGU_L_LOCAL_MME3_CTRL_BASE      0x7FFC1E04F8ull
+#define SHADOW_0_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET  0x2400
+#define SHADOW_0_AGU_L_LOCAL_MME3_CTRL_SECTION     0x2400
+#define mmSHADOW_0_AGU_L_REMOTE_MME3_CTRL_BASE     0x7FFC1E051Cull
+#define SHADOW_0_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_0_AGU_L_REMOTE_MME3_CTRL_SECTION    0x2400
+#define mmSHADOW_0_TENSOR_O_MME3_CTRL_BASE         0x7FFC1E0540ull
+#define SHADOW_0_TENSOR_O_MME3_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_0_TENSOR_O_MME3_CTRL_SECTION        0x4C00
+#define mmSHADOW_0_AGU_O_LOCAL_MME3_CTRL_BASE      0x7FFC1E058Cull
+#define SHADOW_0_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET  0x2400
+#define SHADOW_0_AGU_O_LOCAL_MME3_CTRL_SECTION     0x2400
+#define mmSHADOW_0_AGU_O_REMOTE_MME3_CTRL_BASE     0x7FFC1E05B0ull
+#define SHADOW_0_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_0_AGU_O_REMOTE_MME3_CTRL_SECTION    0x2400
+#define mmSHADOW_0_DESC_MME3_CTRL_BASE             0x7FFC1E05D4ull
+#define SHADOW_0_DESC_MME3_CTRL_MAX_OFFSET         0x5400
+#define SHADOW_0_DESC_MME3_CTRL_SECTION            0xB400
+#define mmSHADOW_1_MME3_CTRL_BASE                  0x7FFC1E0688ull
+#define SHADOW_1_MME3_CTRL_MAX_OFFSET              0x3400
+#define SHADOW_1_MME3_CTRL_SECTION                 0x3400
+#define mmSHADOW_1_TENSOR_S_MME3_CTRL_BASE         0x7FFC1E06BCull
+#define SHADOW_1_TENSOR_S_MME3_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_1_TENSOR_S_MME3_CTRL_SECTION        0x4C00
+#define mmSHADOW_1_AGU_S_MME3_CTRL_BASE            0x7FFC1E0708ull
+#define SHADOW_1_AGU_S_MME3_CTRL_MAX_OFFSET        0x2400
+#define SHADOW_1_AGU_S_MME3_CTRL_SECTION           0x2400
+#define mmSHADOW_1_TENSOR_L_MME3_CTRL_BASE         0x7FFC1E072Cull
+#define SHADOW_1_TENSOR_L_MME3_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_1_TENSOR_L_MME3_CTRL_SECTION        0x4C00
+#define mmSHADOW_1_AGU_L_LOCAL_MME3_CTRL_BASE      0x7FFC1E0778ull
+#define SHADOW_1_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET  0x2400
+#define SHADOW_1_AGU_L_LOCAL_MME3_CTRL_SECTION     0x2400
+#define mmSHADOW_1_AGU_L_REMOTE_MME3_CTRL_BASE     0x7FFC1E079Cull
+#define SHADOW_1_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_1_AGU_L_REMOTE_MME3_CTRL_SECTION    0x2400
+#define mmSHADOW_1_TENSOR_O_MME3_CTRL_BASE         0x7FFC1E07C0ull
+#define SHADOW_1_TENSOR_O_MME3_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_1_TENSOR_O_MME3_CTRL_SECTION        0x4C00
+#define mmSHADOW_1_AGU_O_LOCAL_MME3_CTRL_BASE      0x7FFC1E080Cull
+#define SHADOW_1_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET  0x2400
+#define SHADOW_1_AGU_O_LOCAL_MME3_CTRL_SECTION     0x2400
+#define mmSHADOW_1_AGU_O_REMOTE_MME3_CTRL_BASE     0x7FFC1E0830ull
+#define SHADOW_1_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_1_AGU_O_REMOTE_MME3_CTRL_SECTION    0x2400
+#define mmSHADOW_1_DESC_MME3_CTRL_BASE             0x7FFC1E0854ull
+#define SHADOW_1_DESC_MME3_CTRL_MAX_OFFSET         0x5400
+#define SHADOW_1_DESC_MME3_CTRL_SECTION            0xB400
+#define mmSHADOW_2_MME3_CTRL_BASE                  0x7FFC1E0908ull
+#define SHADOW_2_MME3_CTRL_MAX_OFFSET              0x3400
+#define SHADOW_2_MME3_CTRL_SECTION                 0x3400
+#define mmSHADOW_2_TENSOR_S_MME3_CTRL_BASE         0x7FFC1E093Cull
+#define SHADOW_2_TENSOR_S_MME3_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_2_TENSOR_S_MME3_CTRL_SECTION        0x4C00
+#define mmSHADOW_2_AGU_S_MME3_CTRL_BASE            0x7FFC1E0988ull
+#define SHADOW_2_AGU_S_MME3_CTRL_MAX_OFFSET        0x2400
+#define SHADOW_2_AGU_S_MME3_CTRL_SECTION           0x2400
+#define mmSHADOW_2_TENSOR_L_MME3_CTRL_BASE         0x7FFC1E09ACull
+#define SHADOW_2_TENSOR_L_MME3_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_2_TENSOR_L_MME3_CTRL_SECTION        0x4C00
+#define mmSHADOW_2_AGU_L_LOCAL_MME3_CTRL_BASE      0x7FFC1E09F8ull
+#define SHADOW_2_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET  0x2400
+#define SHADOW_2_AGU_L_LOCAL_MME3_CTRL_SECTION     0x2400
+#define mmSHADOW_2_AGU_L_REMOTE_MME3_CTRL_BASE     0x7FFC1E0A1Cull
+#define SHADOW_2_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_2_AGU_L_REMOTE_MME3_CTRL_SECTION    0x2400
+#define mmSHADOW_2_TENSOR_O_MME3_CTRL_BASE         0x7FFC1E0A40ull
+#define SHADOW_2_TENSOR_O_MME3_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_2_TENSOR_O_MME3_CTRL_SECTION        0x4C00
+#define mmSHADOW_2_AGU_O_LOCAL_MME3_CTRL_BASE      0x7FFC1E0A8Cull
+#define SHADOW_2_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET  0x2400
+#define SHADOW_2_AGU_O_LOCAL_MME3_CTRL_SECTION     0x2400
+#define mmSHADOW_2_AGU_O_REMOTE_MME3_CTRL_BASE     0x7FFC1E0AB0ull
+#define SHADOW_2_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_2_AGU_O_REMOTE_MME3_CTRL_SECTION    0x2400
+#define mmSHADOW_2_DESC_MME3_CTRL_BASE             0x7FFC1E0AD4ull
+#define SHADOW_2_DESC_MME3_CTRL_MAX_OFFSET         0x5400
+#define SHADOW_2_DESC_MME3_CTRL_SECTION            0xB400
+#define mmSHADOW_3_MME3_CTRL_BASE                  0x7FFC1E0B88ull
+#define SHADOW_3_MME3_CTRL_MAX_OFFSET              0x3400
+#define SHADOW_3_MME3_CTRL_SECTION                 0x3400
+#define mmSHADOW_3_TENSOR_S_MME3_CTRL_BASE         0x7FFC1E0BBCull
+#define SHADOW_3_TENSOR_S_MME3_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_3_TENSOR_S_MME3_CTRL_SECTION        0x4C00
+#define mmSHADOW_3_AGU_S_MME3_CTRL_BASE            0x7FFC1E0C08ull
+#define SHADOW_3_AGU_S_MME3_CTRL_MAX_OFFSET        0x2400
+#define SHADOW_3_AGU_S_MME3_CTRL_SECTION           0x2400
+#define mmSHADOW_3_TENSOR_L_MME3_CTRL_BASE         0x7FFC1E0C2Cull
+#define SHADOW_3_TENSOR_L_MME3_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_3_TENSOR_L_MME3_CTRL_SECTION        0x4C00
+#define mmSHADOW_3_AGU_L_LOCAL_MME3_CTRL_BASE      0x7FFC1E0C78ull
+#define SHADOW_3_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET  0x2400
+#define SHADOW_3_AGU_L_LOCAL_MME3_CTRL_SECTION     0x2400
+#define mmSHADOW_3_AGU_L_REMOTE_MME3_CTRL_BASE     0x7FFC1E0C9Cull
+#define SHADOW_3_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_3_AGU_L_REMOTE_MME3_CTRL_SECTION    0x2400
+#define mmSHADOW_3_TENSOR_O_MME3_CTRL_BASE         0x7FFC1E0CC0ull
+#define SHADOW_3_TENSOR_O_MME3_CTRL_MAX_OFFSET     0x4C00
+#define SHADOW_3_TENSOR_O_MME3_CTRL_SECTION        0x4C00
+#define mmSHADOW_3_AGU_O_LOCAL_MME3_CTRL_BASE      0x7FFC1E0D0Cull
+#define SHADOW_3_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET  0x2400
+#define SHADOW_3_AGU_O_LOCAL_MME3_CTRL_SECTION     0x2400
+#define mmSHADOW_3_AGU_O_REMOTE_MME3_CTRL_BASE     0x7FFC1E0D30ull
+#define SHADOW_3_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_3_AGU_O_REMOTE_MME3_CTRL_SECTION    0x2400
+#define mmSHADOW_3_DESC_MME3_CTRL_BASE             0x7FFC1E0D54ull
+#define SHADOW_3_DESC_MME3_CTRL_MAX_OFFSET         0x5400
+#define SHADOW_3_DESC_MME3_CTRL_SECTION            0x72AC
+#define mmMME3_QM_BASE                             0x7FFC1E8000ull
+#define MME3_QM_MAX_OFFSET                         0xD040
+#define MME3_QM_SECTION                            0x18000
+#define mmSRAM_Y0_X0_BANK_BASE                     0x7FFC200000ull
+#define SRAM_Y0_X0_BANK_MAX_OFFSET                 0x4000
+#define SRAM_Y0_X0_BANK_SECTION                    0x1000
+#define mmSRAM_Y0_X0_RTR_BASE                      0x7FFC201000ull
+#define SRAM_Y0_X0_RTR_MAX_OFFSET                  0x3340
+#define SRAM_Y0_X0_RTR_SECTION                     0x7000
+#define mmSRAM_Y0_X1_BANK_BASE                     0x7FFC208000ull
+#define SRAM_Y0_X1_BANK_MAX_OFFSET                 0x4000
+#define SRAM_Y0_X1_BANK_SECTION                    0x1000
+#define mmSRAM_Y0_X1_RTR_BASE                      0x7FFC209000ull
+#define SRAM_Y0_X1_RTR_MAX_OFFSET                  0x3340
+#define SRAM_Y0_X1_RTR_SECTION                     0x7000
+#define mmSRAM_Y0_X2_BANK_BASE                     0x7FFC210000ull
+#define SRAM_Y0_X2_BANK_MAX_OFFSET                 0x4000
+#define SRAM_Y0_X2_BANK_SECTION                    0x1000
+#define mmSRAM_Y0_X2_RTR_BASE                      0x7FFC211000ull
+#define SRAM_Y0_X2_RTR_MAX_OFFSET                  0x3340
+#define SRAM_Y0_X2_RTR_SECTION                     0x7000
+#define mmSRAM_Y0_X3_BANK_BASE                     0x7FFC218000ull
+#define SRAM_Y0_X3_BANK_MAX_OFFSET                 0x4000
+#define SRAM_Y0_X3_BANK_SECTION                    0x1000
+#define mmSRAM_Y0_X3_RTR_BASE                      0x7FFC219000ull
+#define SRAM_Y0_X3_RTR_MAX_OFFSET                  0x3340
+#define SRAM_Y0_X3_RTR_SECTION                     0x7000
+#define mmSRAM_Y0_X4_BANK_BASE                     0x7FFC220000ull
+#define SRAM_Y0_X4_BANK_MAX_OFFSET                 0x4000
+#define SRAM_Y0_X4_BANK_SECTION                    0x1000
+#define mmSRAM_Y0_X4_RTR_BASE                      0x7FFC221000ull
+#define SRAM_Y0_X4_RTR_MAX_OFFSET                  0x3340
+#define SRAM_Y0_X4_RTR_SECTION                     0x7000
+#define mmSRAM_Y0_X5_BANK_BASE                     0x7FFC228000ull
+#define SRAM_Y0_X5_BANK_MAX_OFFSET                 0x4000
+#define SRAM_Y0_X5_BANK_SECTION                    0x1000
+#define mmSRAM_Y0_X5_RTR_BASE                      0x7FFC229000ull
+#define SRAM_Y0_X5_RTR_MAX_OFFSET                  0x3340
+#define SRAM_Y0_X5_RTR_SECTION                     0x7000
+#define mmSRAM_Y0_X6_BANK_BASE                     0x7FFC230000ull
+#define SRAM_Y0_X6_BANK_MAX_OFFSET                 0x4000
+#define SRAM_Y0_X6_BANK_SECTION                    0x1000
+#define mmSRAM_Y0_X6_RTR_BASE                      0x7FFC231000ull
+#define SRAM_Y0_X6_RTR_MAX_OFFSET                  0x3340
+#define SRAM_Y0_X6_RTR_SECTION                     0x7000
+#define mmSRAM_Y0_X7_BANK_BASE                     0x7FFC238000ull
+#define SRAM_Y0_X7_BANK_MAX_OFFSET                 0x4000
+#define SRAM_Y0_X7_BANK_SECTION                    0x1000
+#define mmSRAM_Y0_X7_RTR_BASE                      0x7FFC239000ull
+#define SRAM_Y0_X7_RTR_MAX_OFFSET                  0x3340
+#define SRAM_Y0_X7_RTR_SECTION                     0x7000
+#define mmSRAM_Y1_X0_BANK_BASE                     0x7FFC240000ull
+#define SRAM_Y1_X0_BANK_MAX_OFFSET                 0x4000
+#define SRAM_Y1_X0_BANK_SECTION                    0x1000
+#define mmSRAM_Y1_X0_RTR_BASE                      0x7FFC241000ull
+#define SRAM_Y1_X0_RTR_MAX_OFFSET                  0x3340
+#define SRAM_Y1_X0_RTR_SECTION                     0x7000
+#define mmSRAM_Y1_X1_BANK_BASE                     0x7FFC248000ull
+#define SRAM_Y1_X1_BANK_MAX_OFFSET                 0x4000
+#define SRAM_Y1_X1_BANK_SECTION                    0x1000
+#define mmSRAM_Y1_X1_RTR_BASE                      0x7FFC249000ull
+#define SRAM_Y1_X1_RTR_MAX_OFFSET                  0x3340
+#define SRAM_Y1_X1_RTR_SECTION                     0x7000
+#define mmSRAM_Y1_X2_BANK_BASE                     0x7FFC250000ull
+#define SRAM_Y1_X2_BANK_MAX_OFFSET                 0x4000
+#define SRAM_Y1_X2_BANK_SECTION                    0x1000
+#define mmSRAM_Y1_X2_RTR_BASE                      0x7FFC251000ull
+#define SRAM_Y1_X2_RTR_MAX_OFFSET                  0x3340
+#define SRAM_Y1_X2_RTR_SECTION                     0x7000
+#define mmSRAM_Y1_X3_BANK_BASE                     0x7FFC258000ull
+#define SRAM_Y1_X3_BANK_MAX_OFFSET                 0x4000
+#define SRAM_Y1_X3_BANK_SECTION                    0x1000
+#define mmSRAM_Y1_X3_RTR_BASE                      0x7FFC259000ull
+#define SRAM_Y1_X3_RTR_MAX_OFFSET                  0x3340
+#define SRAM_Y1_X3_RTR_SECTION                     0x7000
+#define mmSRAM_Y1_X4_BANK_BASE                     0x7FFC260000ull
+#define SRAM_Y1_X4_BANK_MAX_OFFSET                 0x4000
+#define SRAM_Y1_X4_BANK_SECTION                    0x1000
+#define mmSRAM_Y1_X4_RTR_BASE                      0x7FFC261000ull
+#define SRAM_Y1_X4_RTR_MAX_OFFSET                  0x3340
+#define SRAM_Y1_X4_RTR_SECTION                     0x7000
+#define mmSRAM_Y1_X5_BANK_BASE                     0x7FFC268000ull
+#define SRAM_Y1_X5_BANK_MAX_OFFSET                 0x4000
+#define SRAM_Y1_X5_BANK_SECTION                    0x1000
+#define mmSRAM_Y1_X5_RTR_BASE                      0x7FFC269000ull
+#define SRAM_Y1_X5_RTR_MAX_OFFSET                  0x3340
+#define SRAM_Y1_X5_RTR_SECTION                     0x7000
+#define mmSRAM_Y1_X6_BANK_BASE                     0x7FFC270000ull
+#define SRAM_Y1_X6_BANK_MAX_OFFSET                 0x4000
+#define SRAM_Y1_X6_BANK_SECTION                    0x1000
+#define mmSRAM_Y1_X6_RTR_BASE                      0x7FFC271000ull
+#define SRAM_Y1_X6_RTR_MAX_OFFSET                  0x3340
+#define SRAM_Y1_X6_RTR_SECTION                     0x7000
+#define mmSRAM_Y1_X7_BANK_BASE                     0x7FFC278000ull
+#define SRAM_Y1_X7_BANK_MAX_OFFSET                 0x4000
+#define SRAM_Y1_X7_BANK_SECTION                    0x1000
+#define mmSRAM_Y1_X7_RTR_BASE                      0x7FFC279000ull
+#define SRAM_Y1_X7_RTR_MAX_OFFSET                  0x3340
+#define SRAM_Y1_X7_RTR_SECTION                     0x7000
+#define mmSRAM_Y2_X0_BANK_BASE                     0x7FFC280000ull
+#define SRAM_Y2_X0_BANK_MAX_OFFSET                 0x4000
+#define SRAM_Y2_X0_BANK_SECTION                    0x1000
+#define mmSRAM_Y2_X0_RTR_BASE                      0x7FFC281000ull
+#define SRAM_Y2_X0_RTR_MAX_OFFSET                  0x3340
+#define SRAM_Y2_X0_RTR_SECTION                     0x7000
+#define mmSRAM_Y2_X1_BANK_BASE                     0x7FFC288000ull
+#define SRAM_Y2_X1_BANK_MAX_OFFSET                 0x4000
+#define SRAM_Y2_X1_BANK_SECTION                    0x1000
+#define mmSRAM_Y2_X1_RTR_BASE                      0x7FFC289000ull
+#define SRAM_Y2_X1_RTR_MAX_OFFSET                  0x3340
+#define SRAM_Y2_X1_RTR_SECTION                     0x7000
+#define mmSRAM_Y2_X2_BANK_BASE                     0x7FFC290000ull
+#define SRAM_Y2_X2_BANK_MAX_OFFSET                 0x4000
+#define SRAM_Y2_X2_BANK_SECTION                    0x1000
+#define mmSRAM_Y2_X2_RTR_BASE                      0x7FFC291000ull
+#define SRAM_Y2_X2_RTR_MAX_OFFSET                  0x3340
+#define SRAM_Y2_X2_RTR_SECTION                     0x7000
+#define mmSRAM_Y2_X3_BANK_BASE                     0x7FFC298000ull
+#define SRAM_Y2_X3_BANK_MAX_OFFSET                 0x4000
+#define SRAM_Y2_X3_BANK_SECTION                    0x1000
+#define mmSRAM_Y2_X3_RTR_BASE                      0x7FFC299000ull
+#define SRAM_Y2_X3_RTR_MAX_OFFSET                  0x3340
+#define SRAM_Y2_X3_RTR_SECTION                     0x7000
+#define mmSRAM_Y2_X4_BANK_BASE                     0x7FFC2A0000ull
+#define SRAM_Y2_X4_BANK_MAX_OFFSET                 0x4000
+#define SRAM_Y2_X4_BANK_SECTION                    0x1000
+#define mmSRAM_Y2_X4_RTR_BASE                      0x7FFC2A1000ull
+#define SRAM_Y2_X4_RTR_MAX_OFFSET                  0x3340
+#define SRAM_Y2_X4_RTR_SECTION                     0x7000
+#define mmSRAM_Y2_X5_BANK_BASE                     0x7FFC2A8000ull
+#define SRAM_Y2_X5_BANK_MAX_OFFSET                 0x4000
+#define SRAM_Y2_X5_BANK_SECTION                    0x1000
+#define mmSRAM_Y2_X5_RTR_BASE                      0x7FFC2A9000ull
+#define SRAM_Y2_X5_RTR_MAX_OFFSET                  0x3340
+#define SRAM_Y2_X5_RTR_SECTION                     0x7000
+#define mmSRAM_Y2_X6_BANK_BASE                     0x7FFC2B0000ull
+#define SRAM_Y2_X6_BANK_MAX_OFFSET                 0x4000
+#define SRAM_Y2_X6_BANK_SECTION                    0x1000
+#define mmSRAM_Y2_X6_RTR_BASE                      0x7FFC2B1000ull
+#define SRAM_Y2_X6_RTR_MAX_OFFSET                  0x3340
+#define SRAM_Y2_X6_RTR_SECTION                     0x7000
+#define mmSRAM_Y2_X7_BANK_BASE                     0x7FFC2B8000ull
+#define SRAM_Y2_X7_BANK_MAX_OFFSET                 0x4000
+#define SRAM_Y2_X7_BANK_SECTION                    0x1000
+#define mmSRAM_Y2_X7_RTR_BASE                      0x7FFC2B9000ull
+#define SRAM_Y2_X7_RTR_MAX_OFFSET                  0x3340
+#define SRAM_Y2_X7_RTR_SECTION                     0x7000
+#define mmSRAM_Y3_X0_BANK_BASE                     0x7FFC2C0000ull
+#define SRAM_Y3_X0_BANK_MAX_OFFSET                 0x4000
+#define SRAM_Y3_X0_BANK_SECTION                    0x1000
+#define mmSRAM_Y3_X0_RTR_BASE                      0x7FFC2C1000ull
+#define SRAM_Y3_X0_RTR_MAX_OFFSET                  0x3340
+#define SRAM_Y3_X0_RTR_SECTION                     0x7000
+#define mmSRAM_Y3_X1_BANK_BASE                     0x7FFC2C8000ull
+#define SRAM_Y3_X1_BANK_MAX_OFFSET                 0x4000
+#define SRAM_Y3_X1_BANK_SECTION                    0x1000
+#define mmSRAM_Y3_X1_RTR_BASE                      0x7FFC2C9000ull
+#define SRAM_Y3_X1_RTR_MAX_OFFSET                  0x3340
+#define SRAM_Y3_X1_RTR_SECTION                     0x7000
+#define mmSRAM_Y3_X2_BANK_BASE                     0x7FFC2D0000ull
+#define SRAM_Y3_X2_BANK_MAX_OFFSET                 0x4000
+#define SRAM_Y3_X2_BANK_SECTION                    0x1000
+#define mmSRAM_Y3_X2_RTR_BASE                      0x7FFC2D1000ull
+#define SRAM_Y3_X2_RTR_MAX_OFFSET                  0x3340
+#define SRAM_Y3_X2_RTR_SECTION                     0x7000
+#define mmSRAM_Y3_X3_BANK_BASE                     0x7FFC2D8000ull
+#define SRAM_Y3_X3_BANK_MAX_OFFSET                 0x4000
+#define SRAM_Y3_X3_BANK_SECTION                    0x1000
+#define mmSRAM_Y3_X3_RTR_BASE                      0x7FFC2D9000ull
+#define SRAM_Y3_X3_RTR_MAX_OFFSET                  0x3340
+#define SRAM_Y3_X3_RTR_SECTION                     0x7000
+#define mmSRAM_Y3_X4_BANK_BASE                     0x7FFC2E0000ull
+#define SRAM_Y3_X4_BANK_MAX_OFFSET                 0x4000
+#define SRAM_Y3_X4_BANK_SECTION                    0x1000
+#define mmSRAM_Y3_X4_RTR_BASE                      0x7FFC2E1000ull
+#define SRAM_Y3_X4_RTR_MAX_OFFSET                  0x3340
+#define SRAM_Y3_X4_RTR_SECTION                     0x7000
+#define mmSRAM_Y3_X5_BANK_BASE                     0x7FFC2E8000ull
+#define SRAM_Y3_X5_BANK_MAX_OFFSET                 0x4000
+#define SRAM_Y3_X5_BANK_SECTION                    0x1000
+#define mmSRAM_Y3_X5_RTR_BASE                      0x7FFC2E9000ull
+#define SRAM_Y3_X5_RTR_MAX_OFFSET                  0x3340
+#define SRAM_Y3_X5_RTR_SECTION                     0x7000
+#define mmSRAM_Y3_X6_BANK_BASE                     0x7FFC2F0000ull
+#define SRAM_Y3_X6_BANK_MAX_OFFSET                 0x4000
+#define SRAM_Y3_X6_BANK_SECTION                    0x1000
+#define mmSRAM_Y3_X6_RTR_BASE                      0x7FFC2F1000ull
+#define SRAM_Y3_X6_RTR_MAX_OFFSET                  0x3340
+#define SRAM_Y3_X6_RTR_SECTION                     0x7000
+#define mmSRAM_Y3_X7_BANK_BASE                     0x7FFC2F8000ull
+#define SRAM_Y3_X7_BANK_MAX_OFFSET                 0x4000
+#define SRAM_Y3_X7_BANK_SECTION                    0x1000
+#define mmSRAM_Y3_X7_RTR_BASE                      0x7FFC2F9000ull
+#define SRAM_Y3_X7_RTR_MAX_OFFSET                  0x3340
+#define SRAM_Y3_X7_RTR_SECTION                     0x7000
+#define mmSIF_RTR_0_BASE                           0x7FFC300000ull
+#define SIF_RTR_0_MAX_OFFSET                       0x6500
+#define SIF_RTR_0_SECTION                          0x6000
+#define mmSIF_RTR_CTRL_0_BASE                      0x7FFC306000ull
+#define SIF_RTR_CTRL_0_MAX_OFFSET                  0xCC00
+#define SIF_RTR_CTRL_0_SECTION                     0xA000
+#define mmSIF_RTR_1_BASE                           0x7FFC310000ull
+#define SIF_RTR_1_MAX_OFFSET                       0x6500
+#define SIF_RTR_1_SECTION                          0x6000
+#define mmSIF_RTR_CTRL_1_BASE                      0x7FFC316000ull
+#define SIF_RTR_CTRL_1_MAX_OFFSET                  0xCC00
+#define SIF_RTR_CTRL_1_SECTION                     0xA000
+#define mmSIF_RTR_2_BASE                           0x7FFC320000ull
+#define SIF_RTR_2_MAX_OFFSET                       0x6500
+#define SIF_RTR_2_SECTION                          0x6000
+#define mmSIF_RTR_CTRL_2_BASE                      0x7FFC326000ull
+#define SIF_RTR_CTRL_2_MAX_OFFSET                  0xCC00
+#define SIF_RTR_CTRL_2_SECTION                     0xA000
+#define mmSIF_RTR_3_BASE                           0x7FFC330000ull
+#define SIF_RTR_3_MAX_OFFSET                       0x6500
+#define SIF_RTR_3_SECTION                          0x6000
+#define mmSIF_RTR_CTRL_3_BASE                      0x7FFC336000ull
+#define SIF_RTR_CTRL_3_MAX_OFFSET                  0xCC00
+#define SIF_RTR_CTRL_3_SECTION                     0xA000
+#define mmSIF_RTR_4_BASE                           0x7FFC340000ull
+#define SIF_RTR_4_MAX_OFFSET                       0x6500
+#define SIF_RTR_4_SECTION                          0x6000
+#define mmSIF_RTR_CTRL_4_BASE                      0x7FFC346000ull
+#define SIF_RTR_CTRL_4_MAX_OFFSET                  0xCC00
+#define SIF_RTR_CTRL_4_SECTION                     0xA000
+#define mmSIF_RTR_5_BASE                           0x7FFC350000ull
+#define SIF_RTR_5_MAX_OFFSET                       0x6500
+#define SIF_RTR_5_SECTION                          0x6000
+#define mmSIF_RTR_CTRL_5_BASE                      0x7FFC356000ull
+#define SIF_RTR_CTRL_5_MAX_OFFSET                  0xCC00
+#define SIF_RTR_CTRL_5_SECTION                     0xA000
+#define mmSIF_RTR_6_BASE                           0x7FFC360000ull
+#define SIF_RTR_6_MAX_OFFSET                       0x6500
+#define SIF_RTR_6_SECTION                          0x6000
+#define mmSIF_RTR_CTRL_6_BASE                      0x7FFC366000ull
+#define SIF_RTR_CTRL_6_MAX_OFFSET                  0xCC00
+#define SIF_RTR_CTRL_6_SECTION                     0xA000
+#define mmSIF_RTR_7_BASE                           0x7FFC370000ull
+#define SIF_RTR_7_MAX_OFFSET                       0x6500
+#define SIF_RTR_7_SECTION                          0x6000
+#define mmSIF_RTR_CTRL_7_BASE                      0x7FFC376000ull
+#define SIF_RTR_CTRL_7_MAX_OFFSET                  0xCC00
+#define SIF_RTR_CTRL_7_SECTION                     0xA000
+#define mmNIF_RTR_0_BASE                           0x7FFC380000ull
+#define NIF_RTR_0_MAX_OFFSET                       0x6500
+#define NIF_RTR_0_SECTION                          0x6000
+#define mmNIF_RTR_CTRL_0_BASE                      0x7FFC386000ull
+#define NIF_RTR_CTRL_0_MAX_OFFSET                  0xCC00
+#define NIF_RTR_CTRL_0_SECTION                     0xA000
+#define mmNIF_RTR_1_BASE                           0x7FFC390000ull
+#define NIF_RTR_1_MAX_OFFSET                       0x6500
+#define NIF_RTR_1_SECTION                          0x6000
+#define mmNIF_RTR_CTRL_1_BASE                      0x7FFC396000ull
+#define NIF_RTR_CTRL_1_MAX_OFFSET                  0xCC00
+#define NIF_RTR_CTRL_1_SECTION                     0xA000
+#define mmNIF_RTR_2_BASE                           0x7FFC3A0000ull
+#define NIF_RTR_2_MAX_OFFSET                       0x6500
+#define NIF_RTR_2_SECTION                          0x6000
+#define mmNIF_RTR_CTRL_2_BASE                      0x7FFC3A6000ull
+#define NIF_RTR_CTRL_2_MAX_OFFSET                  0xCC00
+#define NIF_RTR_CTRL_2_SECTION                     0xA000
+#define mmNIF_RTR_3_BASE                           0x7FFC3B0000ull
+#define NIF_RTR_3_MAX_OFFSET                       0x6500
+#define NIF_RTR_3_SECTION                          0x6000
+#define mmNIF_RTR_CTRL_3_BASE                      0x7FFC3B6000ull
+#define NIF_RTR_CTRL_3_MAX_OFFSET                  0xCC00
+#define NIF_RTR_CTRL_3_SECTION                     0xA000
+#define mmNIF_RTR_4_BASE                           0x7FFC3C0000ull
+#define NIF_RTR_4_MAX_OFFSET                       0x6500
+#define NIF_RTR_4_SECTION                          0x6000
+#define mmNIF_RTR_CTRL_4_BASE                      0x7FFC3C6000ull
+#define NIF_RTR_CTRL_4_MAX_OFFSET                  0xCC00
+#define NIF_RTR_CTRL_4_SECTION                     0xA000
+#define mmNIF_RTR_5_BASE                           0x7FFC3D0000ull
+#define NIF_RTR_5_MAX_OFFSET                       0x6500
+#define NIF_RTR_5_SECTION                          0x6000
+#define mmNIF_RTR_CTRL_5_BASE                      0x7FFC3D6000ull
+#define NIF_RTR_CTRL_5_MAX_OFFSET                  0xCC00
+#define NIF_RTR_CTRL_5_SECTION                     0xA000
+#define mmNIF_RTR_6_BASE                           0x7FFC3E0000ull
+#define NIF_RTR_6_MAX_OFFSET                       0x6500
+#define NIF_RTR_6_SECTION                          0x6000
+#define mmNIF_RTR_CTRL_6_BASE                      0x7FFC3E6000ull
+#define NIF_RTR_CTRL_6_MAX_OFFSET                  0xCC00
+#define NIF_RTR_CTRL_6_SECTION                     0xA000
+#define mmNIF_RTR_7_BASE                           0x7FFC3F0000ull
+#define NIF_RTR_7_MAX_OFFSET                       0x6500
+#define NIF_RTR_7_SECTION                          0x6000
+#define mmNIF_RTR_CTRL_7_BASE                      0x7FFC3F6000ull
+#define NIF_RTR_CTRL_7_MAX_OFFSET                  0xCC00
+#define NIF_RTR_CTRL_7_SECTION                     0x4B000
+#define mmCPU_CA53_CFG_BASE                        0x7FFC441000ull
+#define CPU_CA53_CFG_MAX_OFFSET                    0x2180
+#define CPU_CA53_CFG_SECTION                       0x1000
+#define mmCPU_IF_BASE                              0x7FFC442000ull
+#define CPU_IF_MAX_OFFSET                          0x43C0
+#define CPU_IF_SECTION                             0x2000
+#define mmCPU_TIMESTAMP_BASE                       0x7FFC444000ull
+#define CPU_TIMESTAMP_MAX_OFFSET                   0x1000
+#define CPU_TIMESTAMP_SECTION                      0x3C000
+#define mmDMA_IF_W_S_BASE                          0x7FFC480000ull
+#define DMA_IF_W_S_MAX_OFFSET                      0x8380
+#define DMA_IF_W_S_SECTION                         0x1000
+#define mmDMA_IF_W_S_DOWN_CH0_BASE                 0x7FFC481000ull
+#define DMA_IF_W_S_DOWN_CH0_MAX_OFFSET             0xCC00
+#define DMA_IF_W_S_DOWN_CH0_SECTION                0x1000
+#define mmDMA_IF_W_S_DOWN_CH1_BASE                 0x7FFC482000ull
+#define DMA_IF_W_S_DOWN_CH1_MAX_OFFSET             0xCC00
+#define DMA_IF_W_S_DOWN_CH1_SECTION                0x5000
+#define mmDMA_W_PLL_BASE                           0x7FFC487000ull
+#define DMA_W_PLL_MAX_OFFSET                       0x5200
+#define DMA_W_PLL_SECTION                          0x1000
+#define mmIF_W_PLL_BASE                            0x7FFC488000ull
+#define IF_W_PLL_MAX_OFFSET                        0x5200
+#define IF_W_PLL_SECTION                           0x1000
+#define mmDMA_IF_W_S_DOWN_BASE                     0x7FFC489000ull
+#define DMA_IF_W_S_DOWN_MAX_OFFSET                 0x1500
+#define DMA_IF_W_S_DOWN_SECTION                    0x7000
+#define mmSYNC_MNGR_GLBL_W_S_BASE                  0x7FFC490000ull
+#define SYNC_MNGR_GLBL_W_S_MAX_OFFSET              0x6C00
+#define SYNC_MNGR_GLBL_W_S_SECTION                 0x1000
+#define mmSYNC_MNGR_OBJS_W_S_BASE                  0x7FFC491000ull
+#define SYNC_MNGR_OBJS_W_S_MAX_OFFSET              0x5C00
+#define SYNC_MNGR_OBJS_W_S_SECTION                 0xF000
+#define mmDMA_IF_E_S_BASE                          0x7FFC4A0000ull
+#define DMA_IF_E_S_MAX_OFFSET                      0x8380
+#define DMA_IF_E_S_SECTION                         0x1000
+#define mmDMA_IF_E_S_DOWN_CH0_BASE                 0x7FFC4A1000ull
+#define DMA_IF_E_S_DOWN_CH0_MAX_OFFSET             0xCC00
+#define DMA_IF_E_S_DOWN_CH0_SECTION                0x1000
+#define mmDMA_IF_E_S_DOWN_CH1_BASE                 0x7FFC4A2000ull
+#define DMA_IF_E_S_DOWN_CH1_MAX_OFFSET             0xCC00
+#define DMA_IF_E_S_DOWN_CH1_SECTION                0x5000
+#define mmIF_E_PLL_BASE                            0x7FFC4A7000ull
+#define IF_E_PLL_MAX_OFFSET                        0x5200
+#define IF_E_PLL_SECTION                           0x1000
+#define mmDMA_E_PLL_BASE                           0x7FFC4A8000ull
+#define DMA_E_PLL_MAX_OFFSET                       0x5200
+#define DMA_E_PLL_SECTION                          0x1000
+#define mmDMA_IF_E_S_DOWN_BASE                     0x7FFC4A9000ull
+#define DMA_IF_E_S_DOWN_MAX_OFFSET                 0x1500
+#define DMA_IF_E_S_DOWN_SECTION                    0x7000
+#define mmSYNC_MNGR_GLBL_E_S_BASE                  0x7FFC4B0000ull
+#define SYNC_MNGR_GLBL_E_S_MAX_OFFSET              0x6C00
+#define SYNC_MNGR_GLBL_E_S_SECTION                 0x1000
+#define mmSYNC_MNGR_OBJS_E_S_BASE                  0x7FFC4B1000ull
+#define SYNC_MNGR_OBJS_E_S_MAX_OFFSET              0x5C00
+#define SYNC_MNGR_OBJS_E_S_SECTION                 0xF000
+#define mmDMA_IF_W_N_BASE                          0x7FFC4C0000ull
+#define DMA_IF_W_N_MAX_OFFSET                      0x8380
+#define DMA_IF_W_N_SECTION                         0x1000
+#define mmDMA_IF_W_N_DOWN_CH0_BASE                 0x7FFC4C1000ull
+#define DMA_IF_W_N_DOWN_CH0_MAX_OFFSET             0xCC00
+#define DMA_IF_W_N_DOWN_CH0_SECTION                0x1000
+#define mmDMA_IF_W_N_DOWN_CH1_BASE                 0x7FFC4C2000ull
+#define DMA_IF_W_N_DOWN_CH1_MAX_OFFSET             0xCC00
+#define DMA_IF_W_N_DOWN_CH1_SECTION                0x5000
+#define mmMESH_W_PLL_BASE                          0x7FFC4C7000ull
+#define MESH_W_PLL_MAX_OFFSET                      0x5200
+#define MESH_W_PLL_SECTION                         0x1000
+#define mmSRAM_W_PLL_BASE                          0x7FFC4C8000ull
+#define SRAM_W_PLL_MAX_OFFSET                      0x5200
+#define SRAM_W_PLL_SECTION                         0x1000
+#define mmDMA_IF_W_N_DOWN_BASE                     0x7FFC4C9000ull
+#define DMA_IF_W_N_DOWN_MAX_OFFSET                 0x1500
+#define DMA_IF_W_N_DOWN_SECTION                    0x7000
+#define mmSYNC_MNGR_GLBL_W_N_BASE                  0x7FFC4D0000ull
+#define SYNC_MNGR_GLBL_W_N_MAX_OFFSET              0x6C00
+#define SYNC_MNGR_GLBL_W_N_SECTION                 0x1000
+#define mmSYNC_MNGR_OBJS_W_N_BASE                  0x7FFC4D1000ull
+#define SYNC_MNGR_OBJS_W_N_MAX_OFFSET              0x5C00
+#define SYNC_MNGR_OBJS_W_N_SECTION                 0xF000
+#define mmDMA_IF_E_N_BASE                          0x7FFC4E0000ull
+#define DMA_IF_E_N_MAX_OFFSET                      0x8380
+#define DMA_IF_E_N_SECTION                         0x1000
+#define mmDMA_IF_E_N_DOWN_CH0_BASE                 0x7FFC4E1000ull
+#define DMA_IF_E_N_DOWN_CH0_MAX_OFFSET             0xCC00
+#define DMA_IF_E_N_DOWN_CH0_SECTION                0x1000
+#define mmDMA_IF_E_N_DOWN_CH1_BASE                 0x7FFC4E2000ull
+#define DMA_IF_E_N_DOWN_CH1_MAX_OFFSET             0xCC00
+#define DMA_IF_E_N_DOWN_CH1_SECTION                0x5000
+#define mmMESH_E_PLL_BASE                          0x7FFC4E7000ull
+#define MESH_E_PLL_MAX_OFFSET                      0x5200
+#define MESH_E_PLL_SECTION                         0x1000
+#define mmSRAM_E_PLL_BASE                          0x7FFC4E8000ull
+#define SRAM_E_PLL_MAX_OFFSET                      0x5200
+#define SRAM_E_PLL_SECTION                         0x1000
+#define mmDMA_IF_E_N_DOWN_BASE                     0x7FFC4E9000ull
+#define DMA_IF_E_N_DOWN_MAX_OFFSET                 0x1500
+#define DMA_IF_E_N_DOWN_SECTION                    0x7000
+#define mmSYNC_MNGR_GLBL_E_N_BASE                  0x7FFC4F0000ull
+#define SYNC_MNGR_GLBL_E_N_MAX_OFFSET              0x6C00
+#define SYNC_MNGR_GLBL_E_N_SECTION                 0x1000
+#define mmSYNC_MNGR_OBJS_E_N_BASE                  0x7FFC4F1000ull
+#define SYNC_MNGR_OBJS_E_N_MAX_OFFSET              0x5C00
+#define SYNC_MNGR_OBJS_E_N_SECTION                 0xF000
+#define mmDMA0_CORE_BASE                           0x7FFC500000ull
+#define DMA0_CORE_MAX_OFFSET                       0x23C0
+#define DMA0_CORE_SECTION                          0x8000
+#define mmDMA0_QM_BASE                             0x7FFC508000ull
+#define DMA0_QM_MAX_OFFSET                         0xD040
+#define DMA0_QM_SECTION                            0x18000
+#define mmDMA1_CORE_BASE                           0x7FFC520000ull
+#define DMA1_CORE_MAX_OFFSET                       0x23C0
+#define DMA1_CORE_SECTION                          0x8000
+#define mmDMA1_QM_BASE                             0x7FFC528000ull
+#define DMA1_QM_MAX_OFFSET                         0xD040
+#define DMA1_QM_SECTION                            0x18000
+#define mmDMA2_CORE_BASE                           0x7FFC540000ull
+#define DMA2_CORE_MAX_OFFSET                       0x23C0
+#define DMA2_CORE_SECTION                          0x8000
+#define mmDMA2_QM_BASE                             0x7FFC548000ull
+#define DMA2_QM_MAX_OFFSET                         0xD040
+#define DMA2_QM_SECTION                            0x18000
+#define mmDMA3_CORE_BASE                           0x7FFC560000ull
+#define DMA3_CORE_MAX_OFFSET                       0x23C0
+#define DMA3_CORE_SECTION                          0x8000
+#define mmDMA3_QM_BASE                             0x7FFC568000ull
+#define DMA3_QM_MAX_OFFSET                         0xD040
+#define DMA3_QM_SECTION                            0x18000
+#define mmDMA4_CORE_BASE                           0x7FFC580000ull
+#define DMA4_CORE_MAX_OFFSET                       0x23C0
+#define DMA4_CORE_SECTION                          0x8000
+#define mmDMA4_QM_BASE                             0x7FFC588000ull
+#define DMA4_QM_MAX_OFFSET                         0xD040
+#define DMA4_QM_SECTION                            0x18000
+#define mmDMA5_CORE_BASE                           0x7FFC5A0000ull
+#define DMA5_CORE_MAX_OFFSET                       0x23C0
+#define DMA5_CORE_SECTION                          0x8000
+#define mmDMA5_QM_BASE                             0x7FFC5A8000ull
+#define DMA5_QM_MAX_OFFSET                         0xD040
+#define DMA5_QM_SECTION                            0x18000
+#define mmDMA6_CORE_BASE                           0x7FFC5C0000ull
+#define DMA6_CORE_MAX_OFFSET                       0x23C0
+#define DMA6_CORE_SECTION                          0x8000
+#define mmDMA6_QM_BASE                             0x7FFC5C8000ull
+#define DMA6_QM_MAX_OFFSET                         0xD040
+#define DMA6_QM_SECTION                            0x18000
+#define mmDMA7_CORE_BASE                           0x7FFC5E0000ull
+#define DMA7_CORE_MAX_OFFSET                       0x23C0
+#define DMA7_CORE_SECTION                          0x8000
+#define mmDMA7_QM_BASE                             0x7FFC5E8000ull
+#define DMA7_QM_MAX_OFFSET                         0xD040
+#define DMA7_QM_SECTION                            0x18000
+#define mmHBM0_BASE                                0x7FFC600000ull
+#define HBM0_MAX_OFFSET                            0x8F58
+#define HBM0_SECTION                               0x80000
+#define mmHBM1_BASE                                0x7FFC680000ull
+#define HBM1_MAX_OFFSET                            0x8F58
+#define HBM1_SECTION                               0x80000
+#define mmHBM2_BASE                                0x7FFC700000ull
+#define HBM2_MAX_OFFSET                            0x8F58
+#define HBM2_SECTION                               0x80000
+#define mmHBM3_BASE                                0x7FFC780000ull
+#define HBM3_MAX_OFFSET                            0x8F58
+#define HBM3_SECTION                               0x80000
+#define mmGIC_BASE                                 0x7FFC800000ull
+#define GIC_MAX_OFFSET                             0x10000
+#define GIC_SECTION                                0x401000
+#define mmPCIE_WRAP_BASE                           0x7FFCC01000ull
+#define PCIE_WRAP_MAX_OFFSET                       0xDF00
+#define PCIE_WRAP_SECTION                          0x1000
+#define mmPCIE_DBI_BASE                            0x7FFCC02000ull
+#define PCIE_DBI_MAX_OFFSET                        0xC040
+#define PCIE_DBI_SECTION                           0x2000
+#define mmPCIE_CORE_BASE                           0x7FFCC04000ull
+#define PCIE_CORE_MAX_OFFSET                       0x9BC0
+#define PCIE_CORE_SECTION                          0x3000
+#define mmPCIE_AUX_BASE                            0x7FFCC07000ull
+#define PCIE_AUX_MAX_OFFSET                        0x9C40
+#define PCIE_AUX_SECTION                           0x9000
+#define mmPCIE_PHY_BASE                            0x7FFCC10000ull
+#define PCIE_PHY_MAX_OFFSET                        0x9640
+#define PCIE_PHY_SECTION                           0x1000
+#define mmMMU_UP_BASE                              0x7FFCC11000ull
+#define MMU_UP_MAX_OFFSET                          0x7000
+#define MMU_UP_SECTION                             0x1000
+#define mmSTLB_BASE                                0x7FFCC12000ull
+#define STLB_MAX_OFFSET                            0x8800
+#define STLB_SECTION                               0x1000
+#define mmPCIE_MSI_BASE                            0x7FFCC13000ull
+#define PCIE_MSI_MAX_OFFSET                        0x8000
+#define PCIE_MSI_SECTION                           0x2D000
+#define mmPSOC_I2C_M0_BASE                         0x7FFCC40000ull
+#define PSOC_I2C_M0_MAX_OFFSET                     0x1000
+#define PSOC_I2C_M0_SECTION                        0x1000
+#define mmPSOC_I2C_M1_BASE                         0x7FFCC41000ull
+#define PSOC_I2C_M1_MAX_OFFSET                     0x1000
+#define PSOC_I2C_M1_SECTION                        0x1000
+#define mmPSOC_I2C_S_BASE                          0x7FFCC42000ull
+#define PSOC_I2C_S_MAX_OFFSET                      0x1000
+#define PSOC_I2C_S_SECTION                         0x1000
+#define mmPSOC_SPI_BASE                            0x7FFCC43000ull
+#define PSOC_SPI_MAX_OFFSET                        0x1000
+#define PSOC_SPI_SECTION                           0x2000
+#define mmPSOC_UART_0_BASE                         0x7FFCC45000ull
+#define PSOC_UART_0_MAX_OFFSET                     0x1000
+#define PSOC_UART_0_SECTION                        0x1000
+#define mmPSOC_UART_1_BASE                         0x7FFCC46000ull
+#define PSOC_UART_1_MAX_OFFSET                     0x1000
+#define PSOC_UART_1_SECTION                        0x1000
+#define mmPSOC_TIMER_BASE                          0x7FFCC47000ull
+#define PSOC_TIMER_MAX_OFFSET                      0x1000
+#define PSOC_TIMER_SECTION                         0x1000
+#define mmPSOC_WDOG_BASE                           0x7FFCC48000ull
+#define PSOC_WDOG_MAX_OFFSET                       0x1000
+#define PSOC_WDOG_SECTION                          0x1000
+#define mmPSOC_TIMESTAMP_BASE                      0x7FFCC49000ull
+#define PSOC_TIMESTAMP_MAX_OFFSET                  0x1000
+#define PSOC_TIMESTAMP_SECTION                     0x1000
+#define mmPSOC_EFUSE_BASE                          0x7FFCC4A000ull
+#define PSOC_EFUSE_MAX_OFFSET                      0x3040
+#define PSOC_EFUSE_SECTION                         0x1000
+#define mmPSOC_GLOBAL_CONF_BASE                    0x7FFCC4B000ull
+#define PSOC_GLOBAL_CONF_MAX_OFFSET                0xCD80
+#define PSOC_GLOBAL_CONF_SECTION                   0x1000
+#define mmPSOC_GPIO0_BASE                          0x7FFCC4C000ull
+#define PSOC_GPIO0_MAX_OFFSET                      0x1000
+#define PSOC_GPIO0_SECTION                         0x1000
+#define mmPSOC_GPIO1_BASE                          0x7FFCC4D000ull
+#define PSOC_GPIO1_MAX_OFFSET                      0x1000
+#define PSOC_GPIO1_SECTION                         0x1000
+#define mmPSOC_BTL_BASE                            0x7FFCC4E000ull
+#define PSOC_BTL_MAX_OFFSET                        0x1480
+#define PSOC_BTL_SECTION                           0x1000
+#define mmPSOC_CS_TRACE_BASE                       0x7FFCC4F000ull
+#define PSOC_CS_TRACE_MAX_OFFSET                   0x1680
+#define PSOC_CS_TRACE_SECTION                      0x1000
+#define mmPSOC_GPIO2_BASE                          0x7FFCC50000ull
+#define PSOC_GPIO2_MAX_OFFSET                      0x1000
+#define PSOC_GPIO2_SECTION                         0x1000
+#define mmPSOC_GPIO3_BASE                          0x7FFCC51000ull
+#define PSOC_GPIO3_MAX_OFFSET                      0x1000
+#define PSOC_GPIO3_SECTION                         0x1000
+#define mmPSOC_GPIO4_BASE                          0x7FFCC52000ull
+#define PSOC_GPIO4_MAX_OFFSET                      0x1000
+#define PSOC_GPIO4_SECTION                         0x1000
+#define mmPSOC_DFT_EFUSE_BASE                      0x7FFCC53000ull
+#define PSOC_DFT_EFUSE_MAX_OFFSET                  0x3040
+#define PSOC_DFT_EFUSE_SECTION                     0x1000
+#define mmPSOC_RPM_0_BASE                          0x7FFCC54000ull
+#define PSOC_RPM_0_MAX_OFFSET                      0x8800
+#define PSOC_RPM_0_SECTION                         0x1000
+#define mmPSOC_RPM_1_BASE                          0x7FFCC55000ull
+#define PSOC_RPM_1_MAX_OFFSET                      0x8800
+#define PSOC_RPM_1_SECTION                         0x1000
+#define mmPSOC_RPM_2_BASE                          0x7FFCC56000ull
+#define PSOC_RPM_2_MAX_OFFSET                      0x8800
+#define PSOC_RPM_2_SECTION                         0x1000
+#define mmPSOC_RPM_3_BASE                          0x7FFCC57000ull
+#define PSOC_RPM_3_MAX_OFFSET                      0x8800
+#define PSOC_RPM_3_SECTION                         0x19000
+#define mmPSOC_CPU_PLL_BASE                        0x7FFCC70000ull
+#define PSOC_CPU_PLL_MAX_OFFSET                    0x5200
+#define PSOC_CPU_PLL_SECTION                       0x1000
+#define mmPSOC_MME_PLL_BASE                        0x7FFCC71000ull
+#define PSOC_MME_PLL_MAX_OFFSET                    0x5200
+#define PSOC_MME_PLL_SECTION                       0x1000
+#define mmPSOC_PCI_PLL_BASE                        0x7FFCC72000ull
+#define PSOC_PCI_PLL_MAX_OFFSET                    0x5200
+#define PSOC_PCI_PLL_SECTION                       0x1000
+#define mmPSOC_TPC_PLL_BASE                        0x7FFCC73000ull
+#define PSOC_TPC_PLL_MAX_OFFSET                    0x5200
+#define PSOC_TPC_PLL_SECTION                       0x1000
+#define mmPSOC_HBM_PLL_BASE                        0x7FFCC74000ull
+#define PSOC_HBM_PLL_MAX_OFFSET                    0x5200
+#define PSOC_HBM_PLL_SECTION                       0x1000
+#define mmPSOC_PM_BASE                             0x7FFCC75000ull
+#define PSOC_PM_MAX_OFFSET                         0x1F00
+#define PSOC_PM_SECTION                            0x1000
+#define mmPSOC_TS_BASE                             0x7FFCC76000ull
+#define PSOC_TS_MAX_OFFSET                         0xE640
+#define PSOC_TS_SECTION                            0x2000
+#define mmPSOC_PWM0_BASE                           0x7FFCC78000ull
+#define PSOC_PWM0_MAX_OFFSET                       0x5800
+#define PSOC_PWM0_SECTION                          0x1000
+#define mmPSOC_PWM1_BASE                           0x7FFCC79000ull
+#define PSOC_PWM1_MAX_OFFSET                       0x5800
+#define PSOC_PWM1_SECTION                          0x1000
+#define mmPSOC_PWM2_BASE                           0x7FFCC7A000ull
+#define PSOC_PWM2_MAX_OFFSET                       0x5800
+#define PSOC_PWM2_SECTION                          0x1000
+#define mmPSOC_PWM3_BASE                           0x7FFCC7B000ull
+#define PSOC_PWM3_MAX_OFFSET                       0x5800
+#define PSOC_PWM3_SECTION                          0x1000
+#define mmPSOC_GPIO5_BASE                          0x7FFCC7C000ull
+#define PSOC_GPIO5_MAX_OFFSET                      0x1000
+#define PSOC_GPIO5_SECTION                         0x1000
+#define mmPSOC_GPIO6_BASE                          0x7FFCC7D000ull
+#define PSOC_GPIO6_MAX_OFFSET                      0x1000
+#define PSOC_GPIO6_SECTION                         0x3000
+#define mmPCIE_PMA_0_BASE                          0x7FFCC80000ull
+#define PCIE_PMA_0_MAX_OFFSET                      0x10003
+#define PCIE_PMA_0_SECTION                         0x10000
+#define mmPCIE_PMA_1_BASE                          0x7FFCC90000ull
+#define PCIE_PMA_1_MAX_OFFSET                      0x10003
+#define PCIE_PMA_1_SECTION                         0x10000
+#define mmPCIE_PMA_2_BASE                          0x7FFCCA0000ull
+#define PCIE_PMA_2_MAX_OFFSET                      0x10003
+#define PCIE_PMA_2_SECTION                         0x10000
+#define mmPCIE_PMA_3_BASE                          0x7FFCCB0000ull
+#define PCIE_PMA_3_MAX_OFFSET                      0x10003
+#define PCIE_PMA_3_SECTION                         0x10000
+#define mmNIC0_MAC_CH0_BASE                        0x7FFCCC0000ull
+#define NIC0_MAC_CH0_MAX_OFFSET                    0x8400
+#define NIC0_MAC_CH0_SECTION                       0x1000
+#define mmNIC0_MAC_CH1_BASE                        0x7FFCCC1000ull
+#define NIC0_MAC_CH1_MAX_OFFSET                    0x8400
+#define NIC0_MAC_CH1_SECTION                       0x1000
+#define mmNIC0_MAC_CH2_BASE                        0x7FFCCC2000ull
+#define NIC0_MAC_CH2_MAX_OFFSET                    0x8400
+#define NIC0_MAC_CH2_SECTION                       0x1000
+#define mmNIC0_MAC_CH3_BASE                        0x7FFCCC3000ull
+#define NIC0_MAC_CH3_MAX_OFFSET                    0x8400
+#define NIC0_MAC_CH3_SECTION                       0x1000
+#define mmNIC0_STAT_BASE                           0x7FFCCC4000ull
+#define NIC0_STAT_MAX_OFFSET                       0x4D00
+#define NIC0_STAT_SECTION                          0x1000
+#define mmNIC0_MAC_XPCS91_BASE                     0x7FFCCC5000ull
+#define NIC0_MAC_XPCS91_MAX_OFFSET                 0x2380
+#define NIC0_MAC_XPCS91_SECTION                    0x3000
+#define mmNIC0_MAC_CORE_BASE                       0x7FFCCC8000ull
+#define NIC0_MAC_CORE_MAX_OFFSET                   0x5400
+#define NIC0_MAC_CORE_SECTION                      0x1000
+#define mmNIC0_MAC_AUX_BASE                        0x7FFCCC9000ull
+#define NIC0_MAC_AUX_MAX_OFFSET                    0x3000
+#define NIC0_MAC_AUX_SECTION                       0xF000
+#define mmNIC0_PHY_BASE                            0x7FFCCD8000ull
+#define NIC0_PHY_MAX_OFFSET                        0x3400
+#define NIC0_PHY_SECTION                           0x8000
+#define mmNIC0_QM0_BASE                            0x7FFCCE0000ull
+#define NIC0_QM0_MAX_OFFSET                        0xD040
+#define NIC0_QM0_SECTION                           0x2000
+#define mmNIC0_QM1_BASE                            0x7FFCCE2000ull
+#define NIC0_QM1_MAX_OFFSET                        0xD040
+#define NIC0_QM1_SECTION                           0x2000
+#define mmNIC0_QPC0_BASE                           0x7FFCCE4000ull
+#define NIC0_QPC0_MAX_OFFSET                       0x7140
+#define NIC0_QPC0_SECTION                          0x1000
+#define mmNIC0_QPC1_BASE                           0x7FFCCE5000ull
+#define NIC0_QPC1_MAX_OFFSET                       0x7140
+#define NIC0_QPC1_SECTION                          0x3000
+#define mmNIC0_RXB_BASE                            0x7FFCCE8000ull
+#define NIC0_RXB_MAX_OFFSET                        0x6040
+#define NIC0_RXB_SECTION                           0x1000
+#define mmNIC0_RXE0_BASE                           0x7FFCCE9000ull
+#define NIC0_RXE0_MAX_OFFSET                       0x2FC0
+#define NIC0_RXE0_SECTION                          0x1000
+#define mmNIC0_RXE1_BASE                           0x7FFCCEA000ull
+#define NIC0_RXE1_MAX_OFFSET                       0x2FC0
+#define NIC0_RXE1_SECTION                          0x1000
+#define mmNIC0_RX_GW_BASE                          0x7FFCCEB000ull
+#define NIC0_RX_GW_MAX_OFFSET                      0x4540
+#define NIC0_RX_GW_SECTION                         0x5000
+#define mmNIC0_TXS0_BASE                           0x7FFCCF0000ull
+#define NIC0_TXS0_MAX_OFFSET                       0x19C0
+#define NIC0_TXS0_SECTION                          0x1000
+#define mmNIC0_TXS1_BASE                           0x7FFCCF1000ull
+#define NIC0_TXS1_MAX_OFFSET                       0x19C0
+#define NIC0_TXS1_SECTION                          0x1000
+#define mmNIC0_TXE0_BASE                           0x7FFCCF2000ull
+#define NIC0_TXE0_MAX_OFFSET                       0x2040
+#define NIC0_TXE0_SECTION                          0x1000
+#define mmNIC0_TXE1_BASE                           0x7FFCCF3000ull
+#define NIC0_TXE1_MAX_OFFSET                       0x2040
+#define NIC0_TXE1_SECTION                          0x1000
+#define mmNIC0_TXB_BASE                            0x7FFCCF4000ull
+#define NIC0_TXB_MAX_OFFSET                        0xD400
+#define NIC0_TXB_SECTION                           0x1000
+#define mmNIC0_TMR_BASE                            0x7FFCCF5000ull
+#define NIC0_TMR_MAX_OFFSET                        0x1600
+#define NIC0_TMR_SECTION                           0x1000
+#define mmNIC0_TX_GW_BASE                          0x7FFCCF6000ull
+#define NIC0_TX_GW_MAX_OFFSET                      0x1400
+#define NIC0_TX_GW_SECTION                         0x2000
+#define mmNIC0_TS_BASE                             0x7FFCCF8000ull
+#define NIC0_TS_MAX_OFFSET                         0xE640
+#define NIC0_TS_SECTION                            0x1000
+#define mmNIC0_PLL_BASE                            0x7FFCCF9000ull
+#define NIC0_PLL_MAX_OFFSET                        0x5200
+#define NIC0_PLL_SECTION                           0x1000
+#define mmNIC0_PM_BASE                             0x7FFCCFA000ull
+#define NIC0_PM_MAX_OFFSET                         0x1F00
+#define NIC0_PM_SECTION                            0x6000
+#define mmNIC1_MAC_CH0_BASE                        0x7FFCD00000ull
+#define NIC1_MAC_CH0_MAX_OFFSET                    0x8400
+#define NIC1_MAC_CH0_SECTION                       0x1000
+#define mmNIC1_MAC_CH1_BASE                        0x7FFCD01000ull
+#define NIC1_MAC_CH1_MAX_OFFSET                    0x8400
+#define NIC1_MAC_CH1_SECTION                       0x1000
+#define mmNIC1_MAC_CH2_BASE                        0x7FFCD02000ull
+#define NIC1_MAC_CH2_MAX_OFFSET                    0x8400
+#define NIC1_MAC_CH2_SECTION                       0x1000
+#define mmNIC1_MAC_CH3_BASE                        0x7FFCD03000ull
+#define NIC1_MAC_CH3_MAX_OFFSET                    0x8400
+#define NIC1_MAC_CH3_SECTION                       0x1000
+#define mmNIC1_STAT_BASE                           0x7FFCD04000ull
+#define NIC1_STAT_MAX_OFFSET                       0x4D00
+#define NIC1_STAT_SECTION                          0x1000
+#define mmNIC1_MAC_XPCS91_BASE                     0x7FFCD05000ull
+#define NIC1_MAC_XPCS91_MAX_OFFSET                 0x2380
+#define NIC1_MAC_XPCS91_SECTION                    0x3000
+#define mmNIC1_MAC_CORE_BASE                       0x7FFCD08000ull
+#define NIC1_MAC_CORE_MAX_OFFSET                   0x5400
+#define NIC1_MAC_CORE_SECTION                      0x1000
+#define mmNIC1_MAC_AUX_BASE                        0x7FFCD09000ull
+#define NIC1_MAC_AUX_MAX_OFFSET                    0x3000
+#define NIC1_MAC_AUX_SECTION                       0xF000
+#define mmNIC1_PHY_BASE                            0x7FFCD18000ull
+#define NIC1_PHY_MAX_OFFSET                        0x3400
+#define NIC1_PHY_SECTION                           0x8000
+#define mmNIC1_QM0_BASE                            0x7FFCD20000ull
+#define NIC1_QM0_MAX_OFFSET                        0xD040
+#define NIC1_QM0_SECTION                           0x2000
+#define mmNIC1_QM1_BASE                            0x7FFCD22000ull
+#define NIC1_QM1_MAX_OFFSET                        0xD040
+#define NIC1_QM1_SECTION                           0x2000
+#define mmNIC1_QPC0_BASE                           0x7FFCD24000ull
+#define NIC1_QPC0_MAX_OFFSET                       0x7140
+#define NIC1_QPC0_SECTION                          0x1000
+#define mmNIC1_QPC1_BASE                           0x7FFCD25000ull
+#define NIC1_QPC1_MAX_OFFSET                       0x7140
+#define NIC1_QPC1_SECTION                          0x3000
+#define mmNIC1_RXB_BASE                            0x7FFCD28000ull
+#define NIC1_RXB_MAX_OFFSET                        0x6040
+#define NIC1_RXB_SECTION                           0x1000
+#define mmNIC1_RXE0_BASE                           0x7FFCD29000ull
+#define NIC1_RXE0_MAX_OFFSET                       0x2FC0
+#define NIC1_RXE0_SECTION                          0x1000
+#define mmNIC1_RXE1_BASE                           0x7FFCD2A000ull
+#define NIC1_RXE1_MAX_OFFSET                       0x2FC0
+#define NIC1_RXE1_SECTION                          0x1000
+#define mmNIC1_RX_GW_BASE                          0x7FFCD2B000ull
+#define NIC1_RX_GW_MAX_OFFSET                      0x4540
+#define NIC1_RX_GW_SECTION                         0x5000
+#define mmNIC1_TXS0_BASE                           0x7FFCD30000ull
+#define NIC1_TXS0_MAX_OFFSET                       0x19C0
+#define NIC1_TXS0_SECTION                          0x1000
+#define mmNIC1_TXS1_BASE                           0x7FFCD31000ull
+#define NIC1_TXS1_MAX_OFFSET                       0x19C0
+#define NIC1_TXS1_SECTION                          0x1000
+#define mmNIC1_TXE0_BASE                           0x7FFCD32000ull
+#define NIC1_TXE0_MAX_OFFSET                       0x2040
+#define NIC1_TXE0_SECTION                          0x1000
+#define mmNIC1_TXE1_BASE                           0x7FFCD33000ull
+#define NIC1_TXE1_MAX_OFFSET                       0x2040
+#define NIC1_TXE1_SECTION                          0x1000
+#define mmNIC1_TXB_BASE                            0x7FFCD34000ull
+#define NIC1_TXB_MAX_OFFSET                        0xD400
+#define NIC1_TXB_SECTION                           0x1000
+#define mmNIC1_TMR_BASE                            0x7FFCD35000ull
+#define NIC1_TMR_MAX_OFFSET                        0x1600
+#define NIC1_TMR_SECTION                           0x1000
+#define mmNIC1_TX_GW_BASE                          0x7FFCD36000ull
+#define NIC1_TX_GW_MAX_OFFSET                      0x1400
+#define NIC1_TX_GW_SECTION                         0x2000
+#define mmNIC1_TS_BASE                             0x7FFCD38000ull
+#define NIC1_TS_MAX_OFFSET                         0xE640
+#define NIC1_TS_SECTION                            0x1000
+#define mmNIC1_PLL_BASE                            0x7FFCD39000ull
+#define NIC1_PLL_MAX_OFFSET                        0x5200
+#define NIC1_PLL_SECTION                           0x1000
+#define mmNIC1_PM_BASE                             0x7FFCD3A000ull
+#define NIC1_PM_MAX_OFFSET                         0x1F00
+#define NIC1_PM_SECTION                            0x6000
+#define mmNIC2_MAC_CH0_BASE                        0x7FFCD40000ull
+#define NIC2_MAC_CH0_MAX_OFFSET                    0x8400
+#define NIC2_MAC_CH0_SECTION                       0x1000
+#define mmNIC2_MAC_CH1_BASE                        0x7FFCD41000ull
+#define NIC2_MAC_CH1_MAX_OFFSET                    0x8400
+#define NIC2_MAC_CH1_SECTION                       0x1000
+#define mmNIC2_MAC_CH2_BASE                        0x7FFCD42000ull
+#define NIC2_MAC_CH2_MAX_OFFSET                    0x8400
+#define NIC2_MAC_CH2_SECTION                       0x1000
+#define mmNIC2_MAC_CH3_BASE                        0x7FFCD43000ull
+#define NIC2_MAC_CH3_MAX_OFFSET                    0x8400
+#define NIC2_MAC_CH3_SECTION                       0x1000
+#define mmNIC2_STAT_BASE                           0x7FFCD44000ull
+#define NIC2_STAT_MAX_OFFSET                       0x4D00
+#define NIC2_STAT_SECTION                          0x1000
+#define mmNIC2_MAC_XPCS91_BASE                     0x7FFCD45000ull
+#define NIC2_MAC_XPCS91_MAX_OFFSET                 0x2380
+#define NIC2_MAC_XPCS91_SECTION                    0x3000
+#define mmNIC2_MAC_CORE_BASE                       0x7FFCD48000ull
+#define NIC2_MAC_CORE_MAX_OFFSET                   0x5400
+#define NIC2_MAC_CORE_SECTION                      0x1000
+#define mmNIC2_MAC_AUX_BASE                        0x7FFCD49000ull
+#define NIC2_MAC_AUX_MAX_OFFSET                    0x3000
+#define NIC2_MAC_AUX_SECTION                       0xF000
+#define mmNIC2_PHY_BASE                            0x7FFCD58000ull
+#define NIC2_PHY_MAX_OFFSET                        0x3400
+#define NIC2_PHY_SECTION                           0x8000
+#define mmNIC2_QM0_BASE                            0x7FFCD60000ull
+#define NIC2_QM0_MAX_OFFSET                        0xD040
+#define NIC2_QM0_SECTION                           0x2000
+#define mmNIC2_QM1_BASE                            0x7FFCD62000ull
+#define NIC2_QM1_MAX_OFFSET                        0xD040
+#define NIC2_QM1_SECTION                           0x2000
+#define mmNIC2_QPC0_BASE                           0x7FFCD64000ull
+#define NIC2_QPC0_MAX_OFFSET                       0x7140
+#define NIC2_QPC0_SECTION                          0x1000
+#define mmNIC2_QPC1_BASE                           0x7FFCD65000ull
+#define NIC2_QPC1_MAX_OFFSET                       0x7140
+#define NIC2_QPC1_SECTION                          0x3000
+#define mmNIC2_RXB_BASE                            0x7FFCD68000ull
+#define NIC2_RXB_MAX_OFFSET                        0x6040
+#define NIC2_RXB_SECTION                           0x1000
+#define mmNIC2_RXE0_BASE                           0x7FFCD69000ull
+#define NIC2_RXE0_MAX_OFFSET                       0x2FC0
+#define NIC2_RXE0_SECTION                          0x1000
+#define mmNIC2_RXE1_BASE                           0x7FFCD6A000ull
+#define NIC2_RXE1_MAX_OFFSET                       0x2FC0
+#define NIC2_RXE1_SECTION                          0x1000
+#define mmNIC2_RX_GW_BASE                          0x7FFCD6B000ull
+#define NIC2_RX_GW_MAX_OFFSET                      0x4540
+#define NIC2_RX_GW_SECTION                         0x5000
+#define mmNIC2_TXS0_BASE                           0x7FFCD70000ull
+#define NIC2_TXS0_MAX_OFFSET                       0x19C0
+#define NIC2_TXS0_SECTION                          0x1000
+#define mmNIC2_TXS1_BASE                           0x7FFCD71000ull
+#define NIC2_TXS1_MAX_OFFSET                       0x19C0
+#define NIC2_TXS1_SECTION                          0x1000
+#define mmNIC2_TXE0_BASE                           0x7FFCD72000ull
+#define NIC2_TXE0_MAX_OFFSET                       0x2040
+#define NIC2_TXE0_SECTION                          0x1000
+#define mmNIC2_TXE1_BASE                           0x7FFCD73000ull
+#define NIC2_TXE1_MAX_OFFSET                       0x2040
+#define NIC2_TXE1_SECTION                          0x1000
+#define mmNIC2_TXB_BASE                            0x7FFCD74000ull
+#define NIC2_TXB_MAX_OFFSET                        0xD400
+#define NIC2_TXB_SECTION                           0x1000
+#define mmNIC2_TMR_BASE                            0x7FFCD75000ull
+#define NIC2_TMR_MAX_OFFSET                        0x1600
+#define NIC2_TMR_SECTION                           0x1000
+#define mmNIC2_TX_GW_BASE                          0x7FFCD76000ull
+#define NIC2_TX_GW_MAX_OFFSET                      0x1400
+#define NIC2_TX_GW_SECTION                         0x2000
+#define mmNIC2_HBM_PLL_BASE                        0x7FFCD78000ull
+#define NIC2_HBM_PLL_MAX_OFFSET                    0x5200
+#define NIC2_HBM_PLL_SECTION                       0x1000
+#define mmNIC2_MME_PLL_BASE                        0x7FFCD79000ull
+#define NIC2_MME_PLL_MAX_OFFSET                    0x5200
+#define NIC2_MME_PLL_SECTION                       0x1000
+#define mmNIC2_TPC_PLL_BASE                        0x7FFCD7A000ull
+#define NIC2_TPC_PLL_MAX_OFFSET                    0x5200
+#define NIC2_TPC_PLL_SECTION                       0x6000
+#define mmNIC3_MAC_CH0_BASE                        0x7FFCD80000ull
+#define NIC3_MAC_CH0_MAX_OFFSET                    0x8400
+#define NIC3_MAC_CH0_SECTION                       0x1000
+#define mmNIC3_MAC_CH1_BASE                        0x7FFCD81000ull
+#define NIC3_MAC_CH1_MAX_OFFSET                    0x8400
+#define NIC3_MAC_CH1_SECTION                       0x1000
+#define mmNIC3_MAC_CH2_BASE                        0x7FFCD82000ull
+#define NIC3_MAC_CH2_MAX_OFFSET                    0x8400
+#define NIC3_MAC_CH2_SECTION                       0x1000
+#define mmNIC3_MAC_CH3_BASE                        0x7FFCD83000ull
+#define NIC3_MAC_CH3_MAX_OFFSET                    0x8400
+#define NIC3_MAC_CH3_SECTION                       0x1000
+#define mmNIC3_STAT_BASE                           0x7FFCD84000ull
+#define NIC3_STAT_MAX_OFFSET                       0x4D00
+#define NIC3_STAT_SECTION                          0x1000
+#define mmNIC3_MAC_XPCS91_BASE                     0x7FFCD85000ull
+#define NIC3_MAC_XPCS91_MAX_OFFSET                 0x2380
+#define NIC3_MAC_XPCS91_SECTION                    0x3000
+#define mmNIC3_MAC_CORE_BASE                       0x7FFCD88000ull
+#define NIC3_MAC_CORE_MAX_OFFSET                   0x5400
+#define NIC3_MAC_CORE_SECTION                      0x1000
+#define mmNIC3_MAC_AUX_BASE                        0x7FFCD89000ull
+#define NIC3_MAC_AUX_MAX_OFFSET                    0x3000
+#define NIC3_MAC_AUX_SECTION                       0xF000
+#define mmNIC3_PHY_BASE                            0x7FFCD98000ull
+#define NIC3_PHY_MAX_OFFSET                        0x3400
+#define NIC3_PHY_SECTION                           0x8000
+#define mmNIC3_QM0_BASE                            0x7FFCDA0000ull
+#define NIC3_QM0_MAX_OFFSET                        0xD040
+#define NIC3_QM0_SECTION                           0x2000
+#define mmNIC3_QM1_BASE                            0x7FFCDA2000ull
+#define NIC3_QM1_MAX_OFFSET                        0xD040
+#define NIC3_QM1_SECTION                           0x2000
+#define mmNIC3_QPC0_BASE                           0x7FFCDA4000ull
+#define NIC3_QPC0_MAX_OFFSET                       0x7140
+#define NIC3_QPC0_SECTION                          0x1000
+#define mmNIC3_QPC1_BASE                           0x7FFCDA5000ull
+#define NIC3_QPC1_MAX_OFFSET                       0x7140
+#define NIC3_QPC1_SECTION                          0x3000
+#define mmNIC3_RXB_BASE                            0x7FFCDA8000ull
+#define NIC3_RXB_MAX_OFFSET                        0x6040
+#define NIC3_RXB_SECTION                           0x1000
+#define mmNIC3_RXE0_BASE                           0x7FFCDA9000ull
+#define NIC3_RXE0_MAX_OFFSET                       0x2FC0
+#define NIC3_RXE0_SECTION                          0x1000
+#define mmNIC3_RXE1_BASE                           0x7FFCDAA000ull
+#define NIC3_RXE1_MAX_OFFSET                       0x2FC0
+#define NIC3_RXE1_SECTION                          0x1000
+#define mmNIC3_RX_GW_BASE                          0x7FFCDAB000ull
+#define NIC3_RX_GW_MAX_OFFSET                      0x4540
+#define NIC3_RX_GW_SECTION                         0x5000
+#define mmNIC3_TXS0_BASE                           0x7FFCDB0000ull
+#define NIC3_TXS0_MAX_OFFSET                       0x19C0
+#define NIC3_TXS0_SECTION                          0x1000
+#define mmNIC3_TXS1_BASE                           0x7FFCDB1000ull
+#define NIC3_TXS1_MAX_OFFSET                       0x19C0
+#define NIC3_TXS1_SECTION                          0x1000
+#define mmNIC3_TXE0_BASE                           0x7FFCDB2000ull
+#define NIC3_TXE0_MAX_OFFSET                       0x2040
+#define NIC3_TXE0_SECTION                          0x1000
+#define mmNIC3_TXE1_BASE                           0x7FFCDB3000ull
+#define NIC3_TXE1_MAX_OFFSET                       0x2040
+#define NIC3_TXE1_SECTION                          0x1000
+#define mmNIC3_TXB_BASE                            0x7FFCDB4000ull
+#define NIC3_TXB_MAX_OFFSET                        0xD400
+#define NIC3_TXB_SECTION                           0x1000
+#define mmNIC3_TMR_BASE                            0x7FFCDB5000ull
+#define NIC3_TMR_MAX_OFFSET                        0x1600
+#define NIC3_TMR_SECTION                           0x1000
+#define mmNIC3_TX_GW_BASE                          0x7FFCDB6000ull
+#define NIC3_TX_GW_MAX_OFFSET                      0x1400
+#define NIC3_TX_GW_SECTION                         0x2000
+#define mmNIC3_TS_BASE                             0x7FFCDB8000ull
+#define NIC3_TS_MAX_OFFSET                         0xE640
+#define NIC3_TS_SECTION                            0x2000
+#define mmNIC3_PM_BASE                             0x7FFCDBA000ull
+#define NIC3_PM_MAX_OFFSET                         0x1F00
+#define NIC3_PM_SECTION                            0x6000
+#define mmNIC4_MAC_CH0_BASE                        0x7FFCDC0000ull
+#define NIC4_MAC_CH0_MAX_OFFSET                    0x8400
+#define NIC4_MAC_CH0_SECTION                       0x1000
+#define mmNIC4_MAC_CH1_BASE                        0x7FFCDC1000ull
+#define NIC4_MAC_CH1_MAX_OFFSET                    0x8400
+#define NIC4_MAC_CH1_SECTION                       0x1000
+#define mmNIC4_MAC_CH2_BASE                        0x7FFCDC2000ull
+#define NIC4_MAC_CH2_MAX_OFFSET                    0x8400
+#define NIC4_MAC_CH2_SECTION                       0x1000
+#define mmNIC4_MAC_CH3_BASE                        0x7FFCDC3000ull
+#define NIC4_MAC_CH3_MAX_OFFSET                    0x8400
+#define NIC4_MAC_CH3_SECTION                       0x1000
+#define mmNIC4_STAT_BASE                           0x7FFCDC4000ull
+#define NIC4_STAT_MAX_OFFSET                       0x4D00
+#define NIC4_STAT_SECTION                          0x1000
+#define mmNIC4_MAC_XPCS91_BASE                     0x7FFCDC5000ull
+#define NIC4_MAC_XPCS91_MAX_OFFSET                 0x2380
+#define NIC4_MAC_XPCS91_SECTION                    0x3000
+#define mmNIC4_MAC_CORE_BASE                       0x7FFCDC8000ull
+#define NIC4_MAC_CORE_MAX_OFFSET                   0x5400
+#define NIC4_MAC_CORE_SECTION                      0x1000
+#define mmNIC4_MAC_AUX_BASE                        0x7FFCDC9000ull
+#define NIC4_MAC_AUX_MAX_OFFSET                    0x3000
+#define NIC4_MAC_AUX_SECTION                       0xF000
+#define mmNIC4_PHY_BASE                            0x7FFCDD8000ull
+#define NIC4_PHY_MAX_OFFSET                        0x3400
+#define NIC4_PHY_SECTION                           0x8000
+#define mmNIC4_QM0_BASE                            0x7FFCDE0000ull
+#define NIC4_QM0_MAX_OFFSET                        0xD040
+#define NIC4_QM0_SECTION                           0x2000
+#define mmNIC4_QM1_BASE                            0x7FFCDE2000ull
+#define NIC4_QM1_MAX_OFFSET                        0xD040
+#define NIC4_QM1_SECTION                           0x2000
+#define mmNIC4_QPC0_BASE                           0x7FFCDE4000ull
+#define NIC4_QPC0_MAX_OFFSET                       0x7140
+#define NIC4_QPC0_SECTION                          0x1000
+#define mmNIC4_QPC1_BASE                           0x7FFCDE5000ull
+#define NIC4_QPC1_MAX_OFFSET                       0x7140
+#define NIC4_QPC1_SECTION                          0x3000
+#define mmNIC4_RXB_BASE                            0x7FFCDE8000ull
+#define NIC4_RXB_MAX_OFFSET                        0x6040
+#define NIC4_RXB_SECTION                           0x1000
+#define mmNIC4_RXE0_BASE                           0x7FFCDE9000ull
+#define NIC4_RXE0_MAX_OFFSET                       0x2FC0
+#define NIC4_RXE0_SECTION                          0x1000
+#define mmNIC4_RXE1_BASE                           0x7FFCDEA000ull
+#define NIC4_RXE1_MAX_OFFSET                       0x2FC0
+#define NIC4_RXE1_SECTION                          0x1000
+#define mmNIC4_RX_GW_BASE                          0x7FFCDEB000ull
+#define NIC4_RX_GW_MAX_OFFSET                      0x4540
+#define NIC4_RX_GW_SECTION                         0x5000
+#define mmNIC4_TXS0_BASE                           0x7FFCDF0000ull
+#define NIC4_TXS0_MAX_OFFSET                       0x19C0
+#define NIC4_TXS0_SECTION                          0x1000
+#define mmNIC4_TXS1_BASE                           0x7FFCDF1000ull
+#define NIC4_TXS1_MAX_OFFSET                       0x19C0
+#define NIC4_TXS1_SECTION                          0x1000
+#define mmNIC4_TXE0_BASE                           0x7FFCDF2000ull
+#define NIC4_TXE0_MAX_OFFSET                       0x2040
+#define NIC4_TXE0_SECTION                          0x1000
+#define mmNIC4_TXE1_BASE                           0x7FFCDF3000ull
+#define NIC4_TXE1_MAX_OFFSET                       0x2040
+#define NIC4_TXE1_SECTION                          0x1000
+#define mmNIC4_TXB_BASE                            0x7FFCDF4000ull
+#define NIC4_TXB_MAX_OFFSET                        0xD400
+#define NIC4_TXB_SECTION                           0x1000
+#define mmNIC4_TMR_BASE                            0x7FFCDF5000ull
+#define NIC4_TMR_MAX_OFFSET                        0x1600
+#define NIC4_TMR_SECTION                           0x1000
+#define mmNIC4_TX_GW_BASE                          0x7FFCDF6000ull
+#define NIC4_TX_GW_MAX_OFFSET                      0x1400
+#define NIC4_TX_GW_SECTION                         0x10000
+#define mmTPC0_CFG_BASE                            0x7FFCE06000ull
+#define TPC0_CFG_MAX_OFFSET                        0xE400
+#define TPC0_CFG_SECTION                           0x4000
+#define mmKERNEL_TENSOR_0_TPC0_CFG_BASE            0x7FFCE06400ull
+#define KERNEL_TENSOR_0_TPC0_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_0_TPC0_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_1_TPC0_CFG_BASE            0x7FFCE06438ull
+#define KERNEL_TENSOR_1_TPC0_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_1_TPC0_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_2_TPC0_CFG_BASE            0x7FFCE06470ull
+#define KERNEL_TENSOR_2_TPC0_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_2_TPC0_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_3_TPC0_CFG_BASE            0x7FFCE064A8ull
+#define KERNEL_TENSOR_3_TPC0_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_3_TPC0_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_4_TPC0_CFG_BASE            0x7FFCE064E0ull
+#define KERNEL_TENSOR_4_TPC0_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_4_TPC0_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_5_TPC0_CFG_BASE            0x7FFCE06518ull
+#define KERNEL_TENSOR_5_TPC0_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_5_TPC0_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_6_TPC0_CFG_BASE            0x7FFCE06550ull
+#define KERNEL_TENSOR_6_TPC0_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_6_TPC0_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_7_TPC0_CFG_BASE            0x7FFCE06588ull
+#define KERNEL_TENSOR_7_TPC0_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_7_TPC0_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_8_TPC0_CFG_BASE            0x7FFCE065C0ull
+#define KERNEL_TENSOR_8_TPC0_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_8_TPC0_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_9_TPC0_CFG_BASE            0x7FFCE065F8ull
+#define KERNEL_TENSOR_9_TPC0_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_9_TPC0_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_10_TPC0_CFG_BASE           0x7FFCE06630ull
+#define KERNEL_TENSOR_10_TPC0_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_10_TPC0_CFG_SECTION          0x3800
+#define mmKERNEL_TENSOR_11_TPC0_CFG_BASE           0x7FFCE06668ull
+#define KERNEL_TENSOR_11_TPC0_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_11_TPC0_CFG_SECTION          0x3800
+#define mmKERNEL_TENSOR_12_TPC0_CFG_BASE           0x7FFCE066A0ull
+#define KERNEL_TENSOR_12_TPC0_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_12_TPC0_CFG_SECTION          0x3800
+#define mmKERNEL_TENSOR_13_TPC0_CFG_BASE           0x7FFCE066D8ull
+#define KERNEL_TENSOR_13_TPC0_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_13_TPC0_CFG_SECTION          0x3800
+#define mmKERNEL_TENSOR_14_TPC0_CFG_BASE           0x7FFCE06710ull
+#define KERNEL_TENSOR_14_TPC0_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_14_TPC0_CFG_SECTION          0x3800
+#define mmKERNEL_TENSOR_15_TPC0_CFG_BASE           0x7FFCE06748ull
+#define KERNEL_TENSOR_15_TPC0_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_15_TPC0_CFG_SECTION          0x3800
+#define mmKERNEL_SYNC_OBJECT_TPC0_CFG_BASE         0x7FFCE06780ull
+#define KERNEL_SYNC_OBJECT_TPC0_CFG_MAX_OFFSET     0x8000
+#define KERNEL_SYNC_OBJECT_TPC0_CFG_SECTION        0x8000
+#define mmKERNEL_TPC0_CFG_BASE                     0x7FFCE06788ull
+#define KERNEL_TPC0_CFG_MAX_OFFSET                 0xB800
+#define KERNEL_TPC0_CFG_SECTION                    0x2780
+#define mmQM_TENSOR_0_TPC0_CFG_BASE                0x7FFCE06A00ull
+#define QM_TENSOR_0_TPC0_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_0_TPC0_CFG_SECTION               0x3800
+#define mmQM_TENSOR_1_TPC0_CFG_BASE                0x7FFCE06A38ull
+#define QM_TENSOR_1_TPC0_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_1_TPC0_CFG_SECTION               0x3800
+#define mmQM_TENSOR_2_TPC0_CFG_BASE                0x7FFCE06A70ull
+#define QM_TENSOR_2_TPC0_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_2_TPC0_CFG_SECTION               0x3800
+#define mmQM_TENSOR_3_TPC0_CFG_BASE                0x7FFCE06AA8ull
+#define QM_TENSOR_3_TPC0_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_3_TPC0_CFG_SECTION               0x3800
+#define mmQM_TENSOR_4_TPC0_CFG_BASE                0x7FFCE06AE0ull
+#define QM_TENSOR_4_TPC0_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_4_TPC0_CFG_SECTION               0x3800
+#define mmQM_TENSOR_5_TPC0_CFG_BASE                0x7FFCE06B18ull
+#define QM_TENSOR_5_TPC0_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_5_TPC0_CFG_SECTION               0x3800
+#define mmQM_TENSOR_6_TPC0_CFG_BASE                0x7FFCE06B50ull
+#define QM_TENSOR_6_TPC0_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_6_TPC0_CFG_SECTION               0x3800
+#define mmQM_TENSOR_7_TPC0_CFG_BASE                0x7FFCE06B88ull
+#define QM_TENSOR_7_TPC0_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_7_TPC0_CFG_SECTION               0x3800
+#define mmQM_TENSOR_8_TPC0_CFG_BASE                0x7FFCE06BC0ull
+#define QM_TENSOR_8_TPC0_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_8_TPC0_CFG_SECTION               0x3800
+#define mmQM_TENSOR_9_TPC0_CFG_BASE                0x7FFCE06BF8ull
+#define QM_TENSOR_9_TPC0_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_9_TPC0_CFG_SECTION               0x3800
+#define mmQM_TENSOR_10_TPC0_CFG_BASE               0x7FFCE06C30ull
+#define QM_TENSOR_10_TPC0_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_10_TPC0_CFG_SECTION              0x3800
+#define mmQM_TENSOR_11_TPC0_CFG_BASE               0x7FFCE06C68ull
+#define QM_TENSOR_11_TPC0_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_11_TPC0_CFG_SECTION              0x3800
+#define mmQM_TENSOR_12_TPC0_CFG_BASE               0x7FFCE06CA0ull
+#define QM_TENSOR_12_TPC0_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_12_TPC0_CFG_SECTION              0x3800
+#define mmQM_TENSOR_13_TPC0_CFG_BASE               0x7FFCE06CD8ull
+#define QM_TENSOR_13_TPC0_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_13_TPC0_CFG_SECTION              0x3800
+#define mmQM_TENSOR_14_TPC0_CFG_BASE               0x7FFCE06D10ull
+#define QM_TENSOR_14_TPC0_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_14_TPC0_CFG_SECTION              0x3800
+#define mmQM_TENSOR_15_TPC0_CFG_BASE               0x7FFCE06D48ull
+#define QM_TENSOR_15_TPC0_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_15_TPC0_CFG_SECTION              0x3800
+#define mmQM_SYNC_OBJECT_TPC0_CFG_BASE             0x7FFCE06D80ull
+#define QM_SYNC_OBJECT_TPC0_CFG_MAX_OFFSET         0x8000
+#define QM_SYNC_OBJECT_TPC0_CFG_SECTION            0x8000
+#define mmQM_TPC0_CFG_BASE                         0x7FFCE06D88ull
+#define QM_TPC0_CFG_MAX_OFFSET                     0xB800
+#define QM_TPC0_CFG_SECTION                        0x2780
+#define mmTPC0_E2E_CRED_BASE                       0x7FFCE07000ull
+#define TPC0_E2E_CRED_MAX_OFFSET                   0x1680
+#define TPC0_E2E_CRED_SECTION                      0x1000
+#define mmTPC0_QM_BASE                             0x7FFCE08000ull
+#define TPC0_QM_MAX_OFFSET                         0xD040
+#define TPC0_QM_SECTION                            0x3E000
+#define mmTPC1_CFG_BASE                            0x7FFCE46000ull
+#define TPC1_CFG_MAX_OFFSET                        0xE400
+#define TPC1_CFG_SECTION                           0x4000
+#define mmKERNEL_TENSOR_0_TPC1_CFG_BASE            0x7FFCE46400ull
+#define KERNEL_TENSOR_0_TPC1_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_0_TPC1_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_1_TPC1_CFG_BASE            0x7FFCE46438ull
+#define KERNEL_TENSOR_1_TPC1_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_1_TPC1_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_2_TPC1_CFG_BASE            0x7FFCE46470ull
+#define KERNEL_TENSOR_2_TPC1_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_2_TPC1_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_3_TPC1_CFG_BASE            0x7FFCE464A8ull
+#define KERNEL_TENSOR_3_TPC1_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_3_TPC1_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_4_TPC1_CFG_BASE            0x7FFCE464E0ull
+#define KERNEL_TENSOR_4_TPC1_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_4_TPC1_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_5_TPC1_CFG_BASE            0x7FFCE46518ull
+#define KERNEL_TENSOR_5_TPC1_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_5_TPC1_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_6_TPC1_CFG_BASE            0x7FFCE46550ull
+#define KERNEL_TENSOR_6_TPC1_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_6_TPC1_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_7_TPC1_CFG_BASE            0x7FFCE46588ull
+#define KERNEL_TENSOR_7_TPC1_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_7_TPC1_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_8_TPC1_CFG_BASE            0x7FFCE465C0ull
+#define KERNEL_TENSOR_8_TPC1_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_8_TPC1_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_9_TPC1_CFG_BASE            0x7FFCE465F8ull
+#define KERNEL_TENSOR_9_TPC1_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_9_TPC1_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_10_TPC1_CFG_BASE           0x7FFCE46630ull
+#define KERNEL_TENSOR_10_TPC1_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_10_TPC1_CFG_SECTION          0x3800
+#define mmKERNEL_TENSOR_11_TPC1_CFG_BASE           0x7FFCE46668ull
+#define KERNEL_TENSOR_11_TPC1_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_11_TPC1_CFG_SECTION          0x3800
+#define mmKERNEL_TENSOR_12_TPC1_CFG_BASE           0x7FFCE466A0ull
+#define KERNEL_TENSOR_12_TPC1_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_12_TPC1_CFG_SECTION          0x3800
+#define mmKERNEL_TENSOR_13_TPC1_CFG_BASE           0x7FFCE466D8ull
+#define KERNEL_TENSOR_13_TPC1_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_13_TPC1_CFG_SECTION          0x3800
+#define mmKERNEL_TENSOR_14_TPC1_CFG_BASE           0x7FFCE46710ull
+#define KERNEL_TENSOR_14_TPC1_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_14_TPC1_CFG_SECTION          0x3800
+#define mmKERNEL_TENSOR_15_TPC1_CFG_BASE           0x7FFCE46748ull
+#define KERNEL_TENSOR_15_TPC1_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_15_TPC1_CFG_SECTION          0x3800
+#define mmKERNEL_SYNC_OBJECT_TPC1_CFG_BASE         0x7FFCE46780ull
+#define KERNEL_SYNC_OBJECT_TPC1_CFG_MAX_OFFSET     0x8000
+#define KERNEL_SYNC_OBJECT_TPC1_CFG_SECTION        0x8000
+#define mmKERNEL_TPC1_CFG_BASE                     0x7FFCE46788ull
+#define KERNEL_TPC1_CFG_MAX_OFFSET                 0xB800
+#define KERNEL_TPC1_CFG_SECTION                    0x2780
+#define mmQM_TENSOR_0_TPC1_CFG_BASE                0x7FFCE46A00ull
+#define QM_TENSOR_0_TPC1_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_0_TPC1_CFG_SECTION               0x3800
+#define mmQM_TENSOR_1_TPC1_CFG_BASE                0x7FFCE46A38ull
+#define QM_TENSOR_1_TPC1_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_1_TPC1_CFG_SECTION               0x3800
+#define mmQM_TENSOR_2_TPC1_CFG_BASE                0x7FFCE46A70ull
+#define QM_TENSOR_2_TPC1_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_2_TPC1_CFG_SECTION               0x3800
+#define mmQM_TENSOR_3_TPC1_CFG_BASE                0x7FFCE46AA8ull
+#define QM_TENSOR_3_TPC1_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_3_TPC1_CFG_SECTION               0x3800
+#define mmQM_TENSOR_4_TPC1_CFG_BASE                0x7FFCE46AE0ull
+#define QM_TENSOR_4_TPC1_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_4_TPC1_CFG_SECTION               0x3800
+#define mmQM_TENSOR_5_TPC1_CFG_BASE                0x7FFCE46B18ull
+#define QM_TENSOR_5_TPC1_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_5_TPC1_CFG_SECTION               0x3800
+#define mmQM_TENSOR_6_TPC1_CFG_BASE                0x7FFCE46B50ull
+#define QM_TENSOR_6_TPC1_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_6_TPC1_CFG_SECTION               0x3800
+#define mmQM_TENSOR_7_TPC1_CFG_BASE                0x7FFCE46B88ull
+#define QM_TENSOR_7_TPC1_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_7_TPC1_CFG_SECTION               0x3800
+#define mmQM_TENSOR_8_TPC1_CFG_BASE                0x7FFCE46BC0ull
+#define QM_TENSOR_8_TPC1_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_8_TPC1_CFG_SECTION               0x3800
+#define mmQM_TENSOR_9_TPC1_CFG_BASE                0x7FFCE46BF8ull
+#define QM_TENSOR_9_TPC1_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_9_TPC1_CFG_SECTION               0x3800
+#define mmQM_TENSOR_10_TPC1_CFG_BASE               0x7FFCE46C30ull
+#define QM_TENSOR_10_TPC1_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_10_TPC1_CFG_SECTION              0x3800
+#define mmQM_TENSOR_11_TPC1_CFG_BASE               0x7FFCE46C68ull
+#define QM_TENSOR_11_TPC1_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_11_TPC1_CFG_SECTION              0x3800
+#define mmQM_TENSOR_12_TPC1_CFG_BASE               0x7FFCE46CA0ull
+#define QM_TENSOR_12_TPC1_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_12_TPC1_CFG_SECTION              0x3800
+#define mmQM_TENSOR_13_TPC1_CFG_BASE               0x7FFCE46CD8ull
+#define QM_TENSOR_13_TPC1_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_13_TPC1_CFG_SECTION              0x3800
+#define mmQM_TENSOR_14_TPC1_CFG_BASE               0x7FFCE46D10ull
+#define QM_TENSOR_14_TPC1_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_14_TPC1_CFG_SECTION              0x3800
+#define mmQM_TENSOR_15_TPC1_CFG_BASE               0x7FFCE46D48ull
+#define QM_TENSOR_15_TPC1_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_15_TPC1_CFG_SECTION              0x3800
+#define mmQM_SYNC_OBJECT_TPC1_CFG_BASE             0x7FFCE46D80ull
+#define QM_SYNC_OBJECT_TPC1_CFG_MAX_OFFSET         0x8000
+#define QM_SYNC_OBJECT_TPC1_CFG_SECTION            0x8000
+#define mmQM_TPC1_CFG_BASE                         0x7FFCE46D88ull
+#define QM_TPC1_CFG_MAX_OFFSET                     0xB800
+#define QM_TPC1_CFG_SECTION                        0x2780
+#define mmTPC1_E2E_CRED_BASE                       0x7FFCE47000ull
+#define TPC1_E2E_CRED_MAX_OFFSET                   0x1680
+#define TPC1_E2E_CRED_SECTION                      0x1000
+#define mmTPC1_QM_BASE                             0x7FFCE48000ull
+#define TPC1_QM_MAX_OFFSET                         0xD040
+#define TPC1_QM_SECTION                            0x3E000
+#define mmTPC2_CFG_BASE                            0x7FFCE86000ull
+#define TPC2_CFG_MAX_OFFSET                        0xE400
+#define TPC2_CFG_SECTION                           0x4000
+#define mmKERNEL_TENSOR_0_TPC2_CFG_BASE            0x7FFCE86400ull
+#define KERNEL_TENSOR_0_TPC2_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_0_TPC2_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_1_TPC2_CFG_BASE            0x7FFCE86438ull
+#define KERNEL_TENSOR_1_TPC2_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_1_TPC2_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_2_TPC2_CFG_BASE            0x7FFCE86470ull
+#define KERNEL_TENSOR_2_TPC2_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_2_TPC2_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_3_TPC2_CFG_BASE            0x7FFCE864A8ull
+#define KERNEL_TENSOR_3_TPC2_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_3_TPC2_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_4_TPC2_CFG_BASE            0x7FFCE864E0ull
+#define KERNEL_TENSOR_4_TPC2_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_4_TPC2_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_5_TPC2_CFG_BASE            0x7FFCE86518ull
+#define KERNEL_TENSOR_5_TPC2_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_5_TPC2_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_6_TPC2_CFG_BASE            0x7FFCE86550ull
+#define KERNEL_TENSOR_6_TPC2_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_6_TPC2_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_7_TPC2_CFG_BASE            0x7FFCE86588ull
+#define KERNEL_TENSOR_7_TPC2_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_7_TPC2_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_8_TPC2_CFG_BASE            0x7FFCE865C0ull
+#define KERNEL_TENSOR_8_TPC2_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_8_TPC2_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_9_TPC2_CFG_BASE            0x7FFCE865F8ull
+#define KERNEL_TENSOR_9_TPC2_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_9_TPC2_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_10_TPC2_CFG_BASE           0x7FFCE86630ull
+#define KERNEL_TENSOR_10_TPC2_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_10_TPC2_CFG_SECTION          0x3800
+#define mmKERNEL_TENSOR_11_TPC2_CFG_BASE           0x7FFCE86668ull
+#define KERNEL_TENSOR_11_TPC2_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_11_TPC2_CFG_SECTION          0x3800
+#define mmKERNEL_TENSOR_12_TPC2_CFG_BASE           0x7FFCE866A0ull
+#define KERNEL_TENSOR_12_TPC2_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_12_TPC2_CFG_SECTION          0x3800
+#define mmKERNEL_TENSOR_13_TPC2_CFG_BASE           0x7FFCE866D8ull
+#define KERNEL_TENSOR_13_TPC2_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_13_TPC2_CFG_SECTION          0x3800
+#define mmKERNEL_TENSOR_14_TPC2_CFG_BASE           0x7FFCE86710ull
+#define KERNEL_TENSOR_14_TPC2_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_14_TPC2_CFG_SECTION          0x3800
+#define mmKERNEL_TENSOR_15_TPC2_CFG_BASE           0x7FFCE86748ull
+#define KERNEL_TENSOR_15_TPC2_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_15_TPC2_CFG_SECTION          0x3800
+#define mmKERNEL_SYNC_OBJECT_TPC2_CFG_BASE         0x7FFCE86780ull
+#define KERNEL_SYNC_OBJECT_TPC2_CFG_MAX_OFFSET     0x8000
+#define KERNEL_SYNC_OBJECT_TPC2_CFG_SECTION        0x8000
+#define mmKERNEL_TPC2_CFG_BASE                     0x7FFCE86788ull
+#define KERNEL_TPC2_CFG_MAX_OFFSET                 0xB800
+#define KERNEL_TPC2_CFG_SECTION                    0x2780
+#define mmQM_TENSOR_0_TPC2_CFG_BASE                0x7FFCE86A00ull
+#define QM_TENSOR_0_TPC2_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_0_TPC2_CFG_SECTION               0x3800
+#define mmQM_TENSOR_1_TPC2_CFG_BASE                0x7FFCE86A38ull
+#define QM_TENSOR_1_TPC2_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_1_TPC2_CFG_SECTION               0x3800
+#define mmQM_TENSOR_2_TPC2_CFG_BASE                0x7FFCE86A70ull
+#define QM_TENSOR_2_TPC2_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_2_TPC2_CFG_SECTION               0x3800
+#define mmQM_TENSOR_3_TPC2_CFG_BASE                0x7FFCE86AA8ull
+#define QM_TENSOR_3_TPC2_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_3_TPC2_CFG_SECTION               0x3800
+#define mmQM_TENSOR_4_TPC2_CFG_BASE                0x7FFCE86AE0ull
+#define QM_TENSOR_4_TPC2_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_4_TPC2_CFG_SECTION               0x3800
+#define mmQM_TENSOR_5_TPC2_CFG_BASE                0x7FFCE86B18ull
+#define QM_TENSOR_5_TPC2_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_5_TPC2_CFG_SECTION               0x3800
+#define mmQM_TENSOR_6_TPC2_CFG_BASE                0x7FFCE86B50ull
+#define QM_TENSOR_6_TPC2_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_6_TPC2_CFG_SECTION               0x3800
+#define mmQM_TENSOR_7_TPC2_CFG_BASE                0x7FFCE86B88ull
+#define QM_TENSOR_7_TPC2_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_7_TPC2_CFG_SECTION               0x3800
+#define mmQM_TENSOR_8_TPC2_CFG_BASE                0x7FFCE86BC0ull
+#define QM_TENSOR_8_TPC2_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_8_TPC2_CFG_SECTION               0x3800
+#define mmQM_TENSOR_9_TPC2_CFG_BASE                0x7FFCE86BF8ull
+#define QM_TENSOR_9_TPC2_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_9_TPC2_CFG_SECTION               0x3800
+#define mmQM_TENSOR_10_TPC2_CFG_BASE               0x7FFCE86C30ull
+#define QM_TENSOR_10_TPC2_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_10_TPC2_CFG_SECTION              0x3800
+#define mmQM_TENSOR_11_TPC2_CFG_BASE               0x7FFCE86C68ull
+#define QM_TENSOR_11_TPC2_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_11_TPC2_CFG_SECTION              0x3800
+#define mmQM_TENSOR_12_TPC2_CFG_BASE               0x7FFCE86CA0ull
+#define QM_TENSOR_12_TPC2_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_12_TPC2_CFG_SECTION              0x3800
+#define mmQM_TENSOR_13_TPC2_CFG_BASE               0x7FFCE86CD8ull
+#define QM_TENSOR_13_TPC2_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_13_TPC2_CFG_SECTION              0x3800
+#define mmQM_TENSOR_14_TPC2_CFG_BASE               0x7FFCE86D10ull
+#define QM_TENSOR_14_TPC2_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_14_TPC2_CFG_SECTION              0x3800
+#define mmQM_TENSOR_15_TPC2_CFG_BASE               0x7FFCE86D48ull
+#define QM_TENSOR_15_TPC2_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_15_TPC2_CFG_SECTION              0x3800
+#define mmQM_SYNC_OBJECT_TPC2_CFG_BASE             0x7FFCE86D80ull
+#define QM_SYNC_OBJECT_TPC2_CFG_MAX_OFFSET         0x8000
+#define QM_SYNC_OBJECT_TPC2_CFG_SECTION            0x8000
+#define mmQM_TPC2_CFG_BASE                         0x7FFCE86D88ull
+#define QM_TPC2_CFG_MAX_OFFSET                     0xB800
+#define QM_TPC2_CFG_SECTION                        0x2780
+#define mmTPC2_E2E_CRED_BASE                       0x7FFCE87000ull
+#define TPC2_E2E_CRED_MAX_OFFSET                   0x1680
+#define TPC2_E2E_CRED_SECTION                      0x1000
+#define mmTPC2_QM_BASE                             0x7FFCE88000ull
+#define TPC2_QM_MAX_OFFSET                         0xD040
+#define TPC2_QM_SECTION                            0x3E000
+#define mmTPC3_CFG_BASE                            0x7FFCEC6000ull
+#define TPC3_CFG_MAX_OFFSET                        0xE400
+#define TPC3_CFG_SECTION                           0x4000
+#define mmKERNEL_TENSOR_0_TPC3_CFG_BASE            0x7FFCEC6400ull
+#define KERNEL_TENSOR_0_TPC3_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_0_TPC3_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_1_TPC3_CFG_BASE            0x7FFCEC6438ull
+#define KERNEL_TENSOR_1_TPC3_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_1_TPC3_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_2_TPC3_CFG_BASE            0x7FFCEC6470ull
+#define KERNEL_TENSOR_2_TPC3_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_2_TPC3_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_3_TPC3_CFG_BASE            0x7FFCEC64A8ull
+#define KERNEL_TENSOR_3_TPC3_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_3_TPC3_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_4_TPC3_CFG_BASE            0x7FFCEC64E0ull
+#define KERNEL_TENSOR_4_TPC3_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_4_TPC3_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_5_TPC3_CFG_BASE            0x7FFCEC6518ull
+#define KERNEL_TENSOR_5_TPC3_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_5_TPC3_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_6_TPC3_CFG_BASE            0x7FFCEC6550ull
+#define KERNEL_TENSOR_6_TPC3_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_6_TPC3_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_7_TPC3_CFG_BASE            0x7FFCEC6588ull
+#define KERNEL_TENSOR_7_TPC3_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_7_TPC3_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_8_TPC3_CFG_BASE            0x7FFCEC65C0ull
+#define KERNEL_TENSOR_8_TPC3_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_8_TPC3_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_9_TPC3_CFG_BASE            0x7FFCEC65F8ull
+#define KERNEL_TENSOR_9_TPC3_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_9_TPC3_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_10_TPC3_CFG_BASE           0x7FFCEC6630ull
+#define KERNEL_TENSOR_10_TPC3_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_10_TPC3_CFG_SECTION          0x3800
+#define mmKERNEL_TENSOR_11_TPC3_CFG_BASE           0x7FFCEC6668ull
+#define KERNEL_TENSOR_11_TPC3_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_11_TPC3_CFG_SECTION          0x3800
+#define mmKERNEL_TENSOR_12_TPC3_CFG_BASE           0x7FFCEC66A0ull
+#define KERNEL_TENSOR_12_TPC3_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_12_TPC3_CFG_SECTION          0x3800
+#define mmKERNEL_TENSOR_13_TPC3_CFG_BASE           0x7FFCEC66D8ull
+#define KERNEL_TENSOR_13_TPC3_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_13_TPC3_CFG_SECTION          0x3800
+#define mmKERNEL_TENSOR_14_TPC3_CFG_BASE           0x7FFCEC6710ull
+#define KERNEL_TENSOR_14_TPC3_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_14_TPC3_CFG_SECTION          0x3800
+#define mmKERNEL_TENSOR_15_TPC3_CFG_BASE           0x7FFCEC6748ull
+#define KERNEL_TENSOR_15_TPC3_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_15_TPC3_CFG_SECTION          0x3800
+#define mmKERNEL_SYNC_OBJECT_TPC3_CFG_BASE         0x7FFCEC6780ull
+#define KERNEL_SYNC_OBJECT_TPC3_CFG_MAX_OFFSET     0x8000
+#define KERNEL_SYNC_OBJECT_TPC3_CFG_SECTION        0x8000
+#define mmKERNEL_TPC3_CFG_BASE                     0x7FFCEC6788ull
+#define KERNEL_TPC3_CFG_MAX_OFFSET                 0xB800
+#define KERNEL_TPC3_CFG_SECTION                    0x2780
+#define mmQM_TENSOR_0_TPC3_CFG_BASE                0x7FFCEC6A00ull
+#define QM_TENSOR_0_TPC3_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_0_TPC3_CFG_SECTION               0x3800
+#define mmQM_TENSOR_1_TPC3_CFG_BASE                0x7FFCEC6A38ull
+#define QM_TENSOR_1_TPC3_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_1_TPC3_CFG_SECTION               0x3800
+#define mmQM_TENSOR_2_TPC3_CFG_BASE                0x7FFCEC6A70ull
+#define QM_TENSOR_2_TPC3_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_2_TPC3_CFG_SECTION               0x3800
+#define mmQM_TENSOR_3_TPC3_CFG_BASE                0x7FFCEC6AA8ull
+#define QM_TENSOR_3_TPC3_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_3_TPC3_CFG_SECTION               0x3800
+#define mmQM_TENSOR_4_TPC3_CFG_BASE                0x7FFCEC6AE0ull
+#define QM_TENSOR_4_TPC3_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_4_TPC3_CFG_SECTION               0x3800
+#define mmQM_TENSOR_5_TPC3_CFG_BASE                0x7FFCEC6B18ull
+#define QM_TENSOR_5_TPC3_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_5_TPC3_CFG_SECTION               0x3800
+#define mmQM_TENSOR_6_TPC3_CFG_BASE                0x7FFCEC6B50ull
+#define QM_TENSOR_6_TPC3_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_6_TPC3_CFG_SECTION               0x3800
+#define mmQM_TENSOR_7_TPC3_CFG_BASE                0x7FFCEC6B88ull
+#define QM_TENSOR_7_TPC3_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_7_TPC3_CFG_SECTION               0x3800
+#define mmQM_TENSOR_8_TPC3_CFG_BASE                0x7FFCEC6BC0ull
+#define QM_TENSOR_8_TPC3_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_8_TPC3_CFG_SECTION               0x3800
+#define mmQM_TENSOR_9_TPC3_CFG_BASE                0x7FFCEC6BF8ull
+#define QM_TENSOR_9_TPC3_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_9_TPC3_CFG_SECTION               0x3800
+#define mmQM_TENSOR_10_TPC3_CFG_BASE               0x7FFCEC6C30ull
+#define QM_TENSOR_10_TPC3_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_10_TPC3_CFG_SECTION              0x3800
+#define mmQM_TENSOR_11_TPC3_CFG_BASE               0x7FFCEC6C68ull
+#define QM_TENSOR_11_TPC3_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_11_TPC3_CFG_SECTION              0x3800
+#define mmQM_TENSOR_12_TPC3_CFG_BASE               0x7FFCEC6CA0ull
+#define QM_TENSOR_12_TPC3_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_12_TPC3_CFG_SECTION              0x3800
+#define mmQM_TENSOR_13_TPC3_CFG_BASE               0x7FFCEC6CD8ull
+#define QM_TENSOR_13_TPC3_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_13_TPC3_CFG_SECTION              0x3800
+#define mmQM_TENSOR_14_TPC3_CFG_BASE               0x7FFCEC6D10ull
+#define QM_TENSOR_14_TPC3_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_14_TPC3_CFG_SECTION              0x3800
+#define mmQM_TENSOR_15_TPC3_CFG_BASE               0x7FFCEC6D48ull
+#define QM_TENSOR_15_TPC3_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_15_TPC3_CFG_SECTION              0x3800
+#define mmQM_SYNC_OBJECT_TPC3_CFG_BASE             0x7FFCEC6D80ull
+#define QM_SYNC_OBJECT_TPC3_CFG_MAX_OFFSET         0x8000
+#define QM_SYNC_OBJECT_TPC3_CFG_SECTION            0x8000
+#define mmQM_TPC3_CFG_BASE                         0x7FFCEC6D88ull
+#define QM_TPC3_CFG_MAX_OFFSET                     0xB800
+#define QM_TPC3_CFG_SECTION                        0x2780
+#define mmTPC3_E2E_CRED_BASE                       0x7FFCEC7000ull
+#define TPC3_E2E_CRED_MAX_OFFSET                   0x1680
+#define TPC3_E2E_CRED_SECTION                      0x1000
+#define mmTPC3_QM_BASE                             0x7FFCEC8000ull
+#define TPC3_QM_MAX_OFFSET                         0xD040
+#define TPC3_QM_SECTION                            0x3E000
+#define mmTPC4_CFG_BASE                            0x7FFCF06000ull
+#define TPC4_CFG_MAX_OFFSET                        0xE400
+#define TPC4_CFG_SECTION                           0x4000
+#define mmKERNEL_TENSOR_0_TPC4_CFG_BASE            0x7FFCF06400ull
+#define KERNEL_TENSOR_0_TPC4_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_0_TPC4_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_1_TPC4_CFG_BASE            0x7FFCF06438ull
+#define KERNEL_TENSOR_1_TPC4_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_1_TPC4_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_2_TPC4_CFG_BASE            0x7FFCF06470ull
+#define KERNEL_TENSOR_2_TPC4_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_2_TPC4_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_3_TPC4_CFG_BASE            0x7FFCF064A8ull
+#define KERNEL_TENSOR_3_TPC4_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_3_TPC4_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_4_TPC4_CFG_BASE            0x7FFCF064E0ull
+#define KERNEL_TENSOR_4_TPC4_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_4_TPC4_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_5_TPC4_CFG_BASE            0x7FFCF06518ull
+#define KERNEL_TENSOR_5_TPC4_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_5_TPC4_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_6_TPC4_CFG_BASE            0x7FFCF06550ull
+#define KERNEL_TENSOR_6_TPC4_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_6_TPC4_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_7_TPC4_CFG_BASE            0x7FFCF06588ull
+#define KERNEL_TENSOR_7_TPC4_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_7_TPC4_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_8_TPC4_CFG_BASE            0x7FFCF065C0ull
+#define KERNEL_TENSOR_8_TPC4_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_8_TPC4_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_9_TPC4_CFG_BASE            0x7FFCF065F8ull
+#define KERNEL_TENSOR_9_TPC4_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_9_TPC4_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_10_TPC4_CFG_BASE           0x7FFCF06630ull
+#define KERNEL_TENSOR_10_TPC4_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_10_TPC4_CFG_SECTION          0x3800
+#define mmKERNEL_TENSOR_11_TPC4_CFG_BASE           0x7FFCF06668ull
+#define KERNEL_TENSOR_11_TPC4_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_11_TPC4_CFG_SECTION          0x3800
+#define mmKERNEL_TENSOR_12_TPC4_CFG_BASE           0x7FFCF066A0ull
+#define KERNEL_TENSOR_12_TPC4_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_12_TPC4_CFG_SECTION          0x3800
+#define mmKERNEL_TENSOR_13_TPC4_CFG_BASE           0x7FFCF066D8ull
+#define KERNEL_TENSOR_13_TPC4_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_13_TPC4_CFG_SECTION          0x3800
+#define mmKERNEL_TENSOR_14_TPC4_CFG_BASE           0x7FFCF06710ull
+#define KERNEL_TENSOR_14_TPC4_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_14_TPC4_CFG_SECTION          0x3800
+#define mmKERNEL_TENSOR_15_TPC4_CFG_BASE           0x7FFCF06748ull
+#define KERNEL_TENSOR_15_TPC4_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_15_TPC4_CFG_SECTION          0x3800
+#define mmKERNEL_SYNC_OBJECT_TPC4_CFG_BASE         0x7FFCF06780ull
+#define KERNEL_SYNC_OBJECT_TPC4_CFG_MAX_OFFSET     0x8000
+#define KERNEL_SYNC_OBJECT_TPC4_CFG_SECTION        0x8000
+#define mmKERNEL_TPC4_CFG_BASE                     0x7FFCF06788ull
+#define KERNEL_TPC4_CFG_MAX_OFFSET                 0xB800
+#define KERNEL_TPC4_CFG_SECTION                    0x2780
+#define mmQM_TENSOR_0_TPC4_CFG_BASE                0x7FFCF06A00ull
+#define QM_TENSOR_0_TPC4_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_0_TPC4_CFG_SECTION               0x3800
+#define mmQM_TENSOR_1_TPC4_CFG_BASE                0x7FFCF06A38ull
+#define QM_TENSOR_1_TPC4_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_1_TPC4_CFG_SECTION               0x3800
+#define mmQM_TENSOR_2_TPC4_CFG_BASE                0x7FFCF06A70ull
+#define QM_TENSOR_2_TPC4_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_2_TPC4_CFG_SECTION               0x3800
+#define mmQM_TENSOR_3_TPC4_CFG_BASE                0x7FFCF06AA8ull
+#define QM_TENSOR_3_TPC4_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_3_TPC4_CFG_SECTION               0x3800
+#define mmQM_TENSOR_4_TPC4_CFG_BASE                0x7FFCF06AE0ull
+#define QM_TENSOR_4_TPC4_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_4_TPC4_CFG_SECTION               0x3800
+#define mmQM_TENSOR_5_TPC4_CFG_BASE                0x7FFCF06B18ull
+#define QM_TENSOR_5_TPC4_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_5_TPC4_CFG_SECTION               0x3800
+#define mmQM_TENSOR_6_TPC4_CFG_BASE                0x7FFCF06B50ull
+#define QM_TENSOR_6_TPC4_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_6_TPC4_CFG_SECTION               0x3800
+#define mmQM_TENSOR_7_TPC4_CFG_BASE                0x7FFCF06B88ull
+#define QM_TENSOR_7_TPC4_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_7_TPC4_CFG_SECTION               0x3800
+#define mmQM_TENSOR_8_TPC4_CFG_BASE                0x7FFCF06BC0ull
+#define QM_TENSOR_8_TPC4_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_8_TPC4_CFG_SECTION               0x3800
+#define mmQM_TENSOR_9_TPC4_CFG_BASE                0x7FFCF06BF8ull
+#define QM_TENSOR_9_TPC4_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_9_TPC4_CFG_SECTION               0x3800
+#define mmQM_TENSOR_10_TPC4_CFG_BASE               0x7FFCF06C30ull
+#define QM_TENSOR_10_TPC4_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_10_TPC4_CFG_SECTION              0x3800
+#define mmQM_TENSOR_11_TPC4_CFG_BASE               0x7FFCF06C68ull
+#define QM_TENSOR_11_TPC4_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_11_TPC4_CFG_SECTION              0x3800
+#define mmQM_TENSOR_12_TPC4_CFG_BASE               0x7FFCF06CA0ull
+#define QM_TENSOR_12_TPC4_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_12_TPC4_CFG_SECTION              0x3800
+#define mmQM_TENSOR_13_TPC4_CFG_BASE               0x7FFCF06CD8ull
+#define QM_TENSOR_13_TPC4_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_13_TPC4_CFG_SECTION              0x3800
+#define mmQM_TENSOR_14_TPC4_CFG_BASE               0x7FFCF06D10ull
+#define QM_TENSOR_14_TPC4_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_14_TPC4_CFG_SECTION              0x3800
+#define mmQM_TENSOR_15_TPC4_CFG_BASE               0x7FFCF06D48ull
+#define QM_TENSOR_15_TPC4_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_15_TPC4_CFG_SECTION              0x3800
+#define mmQM_SYNC_OBJECT_TPC4_CFG_BASE             0x7FFCF06D80ull
+#define QM_SYNC_OBJECT_TPC4_CFG_MAX_OFFSET         0x8000
+#define QM_SYNC_OBJECT_TPC4_CFG_SECTION            0x8000
+#define mmQM_TPC4_CFG_BASE                         0x7FFCF06D88ull
+#define QM_TPC4_CFG_MAX_OFFSET                     0xB800
+#define QM_TPC4_CFG_SECTION                        0x2780
+#define mmTPC4_E2E_CRED_BASE                       0x7FFCF07000ull
+#define TPC4_E2E_CRED_MAX_OFFSET                   0x1680
+#define TPC4_E2E_CRED_SECTION                      0x1000
+#define mmTPC4_QM_BASE                             0x7FFCF08000ull
+#define TPC4_QM_MAX_OFFSET                         0xD040
+#define TPC4_QM_SECTION                            0x3E000
+#define mmTPC5_CFG_BASE                            0x7FFCF46000ull
+#define TPC5_CFG_MAX_OFFSET                        0xE400
+#define TPC5_CFG_SECTION                           0x4000
+#define mmKERNEL_TENSOR_0_TPC5_CFG_BASE            0x7FFCF46400ull
+#define KERNEL_TENSOR_0_TPC5_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_0_TPC5_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_1_TPC5_CFG_BASE            0x7FFCF46438ull
+#define KERNEL_TENSOR_1_TPC5_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_1_TPC5_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_2_TPC5_CFG_BASE            0x7FFCF46470ull
+#define KERNEL_TENSOR_2_TPC5_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_2_TPC5_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_3_TPC5_CFG_BASE            0x7FFCF464A8ull
+#define KERNEL_TENSOR_3_TPC5_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_3_TPC5_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_4_TPC5_CFG_BASE            0x7FFCF464E0ull
+#define KERNEL_TENSOR_4_TPC5_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_4_TPC5_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_5_TPC5_CFG_BASE            0x7FFCF46518ull
+#define KERNEL_TENSOR_5_TPC5_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_5_TPC5_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_6_TPC5_CFG_BASE            0x7FFCF46550ull
+#define KERNEL_TENSOR_6_TPC5_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_6_TPC5_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_7_TPC5_CFG_BASE            0x7FFCF46588ull
+#define KERNEL_TENSOR_7_TPC5_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_7_TPC5_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_8_TPC5_CFG_BASE            0x7FFCF465C0ull
+#define KERNEL_TENSOR_8_TPC5_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_8_TPC5_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_9_TPC5_CFG_BASE            0x7FFCF465F8ull
+#define KERNEL_TENSOR_9_TPC5_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_9_TPC5_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_10_TPC5_CFG_BASE           0x7FFCF46630ull
+#define KERNEL_TENSOR_10_TPC5_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_10_TPC5_CFG_SECTION          0x3800
+#define mmKERNEL_TENSOR_11_TPC5_CFG_BASE           0x7FFCF46668ull
+#define KERNEL_TENSOR_11_TPC5_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_11_TPC5_CFG_SECTION          0x3800
+#define mmKERNEL_TENSOR_12_TPC5_CFG_BASE           0x7FFCF466A0ull
+#define KERNEL_TENSOR_12_TPC5_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_12_TPC5_CFG_SECTION          0x3800
+#define mmKERNEL_TENSOR_13_TPC5_CFG_BASE           0x7FFCF466D8ull
+#define KERNEL_TENSOR_13_TPC5_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_13_TPC5_CFG_SECTION          0x3800
+#define mmKERNEL_TENSOR_14_TPC5_CFG_BASE           0x7FFCF46710ull
+#define KERNEL_TENSOR_14_TPC5_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_14_TPC5_CFG_SECTION          0x3800
+#define mmKERNEL_TENSOR_15_TPC5_CFG_BASE           0x7FFCF46748ull
+#define KERNEL_TENSOR_15_TPC5_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_15_TPC5_CFG_SECTION          0x3800
+#define mmKERNEL_SYNC_OBJECT_TPC5_CFG_BASE         0x7FFCF46780ull
+#define KERNEL_SYNC_OBJECT_TPC5_CFG_MAX_OFFSET     0x8000
+#define KERNEL_SYNC_OBJECT_TPC5_CFG_SECTION        0x8000
+#define mmKERNEL_TPC5_CFG_BASE                     0x7FFCF46788ull
+#define KERNEL_TPC5_CFG_MAX_OFFSET                 0xB800
+#define KERNEL_TPC5_CFG_SECTION                    0x2780
+#define mmQM_TENSOR_0_TPC5_CFG_BASE                0x7FFCF46A00ull
+#define QM_TENSOR_0_TPC5_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_0_TPC5_CFG_SECTION               0x3800
+#define mmQM_TENSOR_1_TPC5_CFG_BASE                0x7FFCF46A38ull
+#define QM_TENSOR_1_TPC5_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_1_TPC5_CFG_SECTION               0x3800
+#define mmQM_TENSOR_2_TPC5_CFG_BASE                0x7FFCF46A70ull
+#define QM_TENSOR_2_TPC5_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_2_TPC5_CFG_SECTION               0x3800
+#define mmQM_TENSOR_3_TPC5_CFG_BASE                0x7FFCF46AA8ull
+#define QM_TENSOR_3_TPC5_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_3_TPC5_CFG_SECTION               0x3800
+#define mmQM_TENSOR_4_TPC5_CFG_BASE                0x7FFCF46AE0ull
+#define QM_TENSOR_4_TPC5_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_4_TPC5_CFG_SECTION               0x3800
+#define mmQM_TENSOR_5_TPC5_CFG_BASE                0x7FFCF46B18ull
+#define QM_TENSOR_5_TPC5_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_5_TPC5_CFG_SECTION               0x3800
+#define mmQM_TENSOR_6_TPC5_CFG_BASE                0x7FFCF46B50ull
+#define QM_TENSOR_6_TPC5_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_6_TPC5_CFG_SECTION               0x3800
+#define mmQM_TENSOR_7_TPC5_CFG_BASE                0x7FFCF46B88ull
+#define QM_TENSOR_7_TPC5_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_7_TPC5_CFG_SECTION               0x3800
+#define mmQM_TENSOR_8_TPC5_CFG_BASE                0x7FFCF46BC0ull
+#define QM_TENSOR_8_TPC5_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_8_TPC5_CFG_SECTION               0x3800
+#define mmQM_TENSOR_9_TPC5_CFG_BASE                0x7FFCF46BF8ull
+#define QM_TENSOR_9_TPC5_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_9_TPC5_CFG_SECTION               0x3800
+#define mmQM_TENSOR_10_TPC5_CFG_BASE               0x7FFCF46C30ull
+#define QM_TENSOR_10_TPC5_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_10_TPC5_CFG_SECTION              0x3800
+#define mmQM_TENSOR_11_TPC5_CFG_BASE               0x7FFCF46C68ull
+#define QM_TENSOR_11_TPC5_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_11_TPC5_CFG_SECTION              0x3800
+#define mmQM_TENSOR_12_TPC5_CFG_BASE               0x7FFCF46CA0ull
+#define QM_TENSOR_12_TPC5_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_12_TPC5_CFG_SECTION              0x3800
+#define mmQM_TENSOR_13_TPC5_CFG_BASE               0x7FFCF46CD8ull
+#define QM_TENSOR_13_TPC5_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_13_TPC5_CFG_SECTION              0x3800
+#define mmQM_TENSOR_14_TPC5_CFG_BASE               0x7FFCF46D10ull
+#define QM_TENSOR_14_TPC5_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_14_TPC5_CFG_SECTION              0x3800
+#define mmQM_TENSOR_15_TPC5_CFG_BASE               0x7FFCF46D48ull
+#define QM_TENSOR_15_TPC5_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_15_TPC5_CFG_SECTION              0x3800
+#define mmQM_SYNC_OBJECT_TPC5_CFG_BASE             0x7FFCF46D80ull
+#define QM_SYNC_OBJECT_TPC5_CFG_MAX_OFFSET         0x8000
+#define QM_SYNC_OBJECT_TPC5_CFG_SECTION            0x8000
+#define mmQM_TPC5_CFG_BASE                         0x7FFCF46D88ull
+#define QM_TPC5_CFG_MAX_OFFSET                     0xB800
+#define QM_TPC5_CFG_SECTION                        0x2780
+#define mmTPC5_E2E_CRED_BASE                       0x7FFCF47000ull
+#define TPC5_E2E_CRED_MAX_OFFSET                   0x1680
+#define TPC5_E2E_CRED_SECTION                      0x1000
+#define mmTPC5_QM_BASE                             0x7FFCF48000ull
+#define TPC5_QM_MAX_OFFSET                         0xD040
+#define TPC5_QM_SECTION                            0x3E000
+#define mmTPC6_CFG_BASE                            0x7FFCF86000ull
+#define TPC6_CFG_MAX_OFFSET                        0xE400
+#define TPC6_CFG_SECTION                           0x4000
+#define mmKERNEL_TENSOR_0_TPC6_CFG_BASE            0x7FFCF86400ull
+#define KERNEL_TENSOR_0_TPC6_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_0_TPC6_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_1_TPC6_CFG_BASE            0x7FFCF86438ull
+#define KERNEL_TENSOR_1_TPC6_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_1_TPC6_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_2_TPC6_CFG_BASE            0x7FFCF86470ull
+#define KERNEL_TENSOR_2_TPC6_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_2_TPC6_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_3_TPC6_CFG_BASE            0x7FFCF864A8ull
+#define KERNEL_TENSOR_3_TPC6_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_3_TPC6_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_4_TPC6_CFG_BASE            0x7FFCF864E0ull
+#define KERNEL_TENSOR_4_TPC6_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_4_TPC6_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_5_TPC6_CFG_BASE            0x7FFCF86518ull
+#define KERNEL_TENSOR_5_TPC6_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_5_TPC6_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_6_TPC6_CFG_BASE            0x7FFCF86550ull
+#define KERNEL_TENSOR_6_TPC6_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_6_TPC6_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_7_TPC6_CFG_BASE            0x7FFCF86588ull
+#define KERNEL_TENSOR_7_TPC6_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_7_TPC6_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_8_TPC6_CFG_BASE            0x7FFCF865C0ull
+#define KERNEL_TENSOR_8_TPC6_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_8_TPC6_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_9_TPC6_CFG_BASE            0x7FFCF865F8ull
+#define KERNEL_TENSOR_9_TPC6_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_9_TPC6_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_10_TPC6_CFG_BASE           0x7FFCF86630ull
+#define KERNEL_TENSOR_10_TPC6_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_10_TPC6_CFG_SECTION          0x3800
+#define mmKERNEL_TENSOR_11_TPC6_CFG_BASE           0x7FFCF86668ull
+#define KERNEL_TENSOR_11_TPC6_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_11_TPC6_CFG_SECTION          0x3800
+#define mmKERNEL_TENSOR_12_TPC6_CFG_BASE           0x7FFCF866A0ull
+#define KERNEL_TENSOR_12_TPC6_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_12_TPC6_CFG_SECTION          0x3800
+#define mmKERNEL_TENSOR_13_TPC6_CFG_BASE           0x7FFCF866D8ull
+#define KERNEL_TENSOR_13_TPC6_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_13_TPC6_CFG_SECTION          0x3800
+#define mmKERNEL_TENSOR_14_TPC6_CFG_BASE           0x7FFCF86710ull
+#define KERNEL_TENSOR_14_TPC6_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_14_TPC6_CFG_SECTION          0x3800
+#define mmKERNEL_TENSOR_15_TPC6_CFG_BASE           0x7FFCF86748ull
+#define KERNEL_TENSOR_15_TPC6_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_15_TPC6_CFG_SECTION          0x3800
+#define mmKERNEL_SYNC_OBJECT_TPC6_CFG_BASE         0x7FFCF86780ull
+#define KERNEL_SYNC_OBJECT_TPC6_CFG_MAX_OFFSET     0x8000
+#define KERNEL_SYNC_OBJECT_TPC6_CFG_SECTION        0x8000
+#define mmKERNEL_TPC6_CFG_BASE                     0x7FFCF86788ull
+#define KERNEL_TPC6_CFG_MAX_OFFSET                 0xB800
+#define KERNEL_TPC6_CFG_SECTION                    0x2780
+#define mmQM_TENSOR_0_TPC6_CFG_BASE                0x7FFCF86A00ull
+#define QM_TENSOR_0_TPC6_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_0_TPC6_CFG_SECTION               0x3800
+#define mmQM_TENSOR_1_TPC6_CFG_BASE                0x7FFCF86A38ull
+#define QM_TENSOR_1_TPC6_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_1_TPC6_CFG_SECTION               0x3800
+#define mmQM_TENSOR_2_TPC6_CFG_BASE                0x7FFCF86A70ull
+#define QM_TENSOR_2_TPC6_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_2_TPC6_CFG_SECTION               0x3800
+#define mmQM_TENSOR_3_TPC6_CFG_BASE                0x7FFCF86AA8ull
+#define QM_TENSOR_3_TPC6_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_3_TPC6_CFG_SECTION               0x3800
+#define mmQM_TENSOR_4_TPC6_CFG_BASE                0x7FFCF86AE0ull
+#define QM_TENSOR_4_TPC6_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_4_TPC6_CFG_SECTION               0x3800
+#define mmQM_TENSOR_5_TPC6_CFG_BASE                0x7FFCF86B18ull
+#define QM_TENSOR_5_TPC6_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_5_TPC6_CFG_SECTION               0x3800
+#define mmQM_TENSOR_6_TPC6_CFG_BASE                0x7FFCF86B50ull
+#define QM_TENSOR_6_TPC6_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_6_TPC6_CFG_SECTION               0x3800
+#define mmQM_TENSOR_7_TPC6_CFG_BASE                0x7FFCF86B88ull
+#define QM_TENSOR_7_TPC6_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_7_TPC6_CFG_SECTION               0x3800
+#define mmQM_TENSOR_8_TPC6_CFG_BASE                0x7FFCF86BC0ull
+#define QM_TENSOR_8_TPC6_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_8_TPC6_CFG_SECTION               0x3800
+#define mmQM_TENSOR_9_TPC6_CFG_BASE                0x7FFCF86BF8ull
+#define QM_TENSOR_9_TPC6_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_9_TPC6_CFG_SECTION               0x3800
+#define mmQM_TENSOR_10_TPC6_CFG_BASE               0x7FFCF86C30ull
+#define QM_TENSOR_10_TPC6_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_10_TPC6_CFG_SECTION              0x3800
+#define mmQM_TENSOR_11_TPC6_CFG_BASE               0x7FFCF86C68ull
+#define QM_TENSOR_11_TPC6_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_11_TPC6_CFG_SECTION              0x3800
+#define mmQM_TENSOR_12_TPC6_CFG_BASE               0x7FFCF86CA0ull
+#define QM_TENSOR_12_TPC6_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_12_TPC6_CFG_SECTION              0x3800
+#define mmQM_TENSOR_13_TPC6_CFG_BASE               0x7FFCF86CD8ull
+#define QM_TENSOR_13_TPC6_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_13_TPC6_CFG_SECTION              0x3800
+#define mmQM_TENSOR_14_TPC6_CFG_BASE               0x7FFCF86D10ull
+#define QM_TENSOR_14_TPC6_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_14_TPC6_CFG_SECTION              0x3800
+#define mmQM_TENSOR_15_TPC6_CFG_BASE               0x7FFCF86D48ull
+#define QM_TENSOR_15_TPC6_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_15_TPC6_CFG_SECTION              0x3800
+#define mmQM_SYNC_OBJECT_TPC6_CFG_BASE             0x7FFCF86D80ull
+#define QM_SYNC_OBJECT_TPC6_CFG_MAX_OFFSET         0x8000
+#define QM_SYNC_OBJECT_TPC6_CFG_SECTION            0x8000
+#define mmQM_TPC6_CFG_BASE                         0x7FFCF86D88ull
+#define QM_TPC6_CFG_MAX_OFFSET                     0xB800
+#define QM_TPC6_CFG_SECTION                        0x2780
+#define mmTPC6_E2E_CRED_BASE                       0x7FFCF87000ull
+#define TPC6_E2E_CRED_MAX_OFFSET                   0x1680
+#define TPC6_E2E_CRED_SECTION                      0x1000
+#define mmTPC6_QM_BASE                             0x7FFCF88000ull
+#define TPC6_QM_MAX_OFFSET                         0xD040
+#define TPC6_QM_SECTION                            0x3E000
+#define mmTPC7_CFG_BASE                            0x7FFCFC6000ull
+#define TPC7_CFG_MAX_OFFSET                        0xE400
+#define TPC7_CFG_SECTION                           0x4000
+#define mmKERNEL_TENSOR_0_TPC7_CFG_BASE            0x7FFCFC6400ull
+#define KERNEL_TENSOR_0_TPC7_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_0_TPC7_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_1_TPC7_CFG_BASE            0x7FFCFC6438ull
+#define KERNEL_TENSOR_1_TPC7_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_1_TPC7_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_2_TPC7_CFG_BASE            0x7FFCFC6470ull
+#define KERNEL_TENSOR_2_TPC7_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_2_TPC7_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_3_TPC7_CFG_BASE            0x7FFCFC64A8ull
+#define KERNEL_TENSOR_3_TPC7_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_3_TPC7_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_4_TPC7_CFG_BASE            0x7FFCFC64E0ull
+#define KERNEL_TENSOR_4_TPC7_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_4_TPC7_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_5_TPC7_CFG_BASE            0x7FFCFC6518ull
+#define KERNEL_TENSOR_5_TPC7_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_5_TPC7_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_6_TPC7_CFG_BASE            0x7FFCFC6550ull
+#define KERNEL_TENSOR_6_TPC7_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_6_TPC7_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_7_TPC7_CFG_BASE            0x7FFCFC6588ull
+#define KERNEL_TENSOR_7_TPC7_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_7_TPC7_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_8_TPC7_CFG_BASE            0x7FFCFC65C0ull
+#define KERNEL_TENSOR_8_TPC7_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_8_TPC7_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_9_TPC7_CFG_BASE            0x7FFCFC65F8ull
+#define KERNEL_TENSOR_9_TPC7_CFG_MAX_OFFSET        0x3800
+#define KERNEL_TENSOR_9_TPC7_CFG_SECTION           0x3800
+#define mmKERNEL_TENSOR_10_TPC7_CFG_BASE           0x7FFCFC6630ull
+#define KERNEL_TENSOR_10_TPC7_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_10_TPC7_CFG_SECTION          0x3800
+#define mmKERNEL_TENSOR_11_TPC7_CFG_BASE           0x7FFCFC6668ull
+#define KERNEL_TENSOR_11_TPC7_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_11_TPC7_CFG_SECTION          0x3800
+#define mmKERNEL_TENSOR_12_TPC7_CFG_BASE           0x7FFCFC66A0ull
+#define KERNEL_TENSOR_12_TPC7_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_12_TPC7_CFG_SECTION          0x3800
+#define mmKERNEL_TENSOR_13_TPC7_CFG_BASE           0x7FFCFC66D8ull
+#define KERNEL_TENSOR_13_TPC7_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_13_TPC7_CFG_SECTION          0x3800
+#define mmKERNEL_TENSOR_14_TPC7_CFG_BASE           0x7FFCFC6710ull
+#define KERNEL_TENSOR_14_TPC7_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_14_TPC7_CFG_SECTION          0x3800
+#define mmKERNEL_TENSOR_15_TPC7_CFG_BASE           0x7FFCFC6748ull
+#define KERNEL_TENSOR_15_TPC7_CFG_MAX_OFFSET       0x3800
+#define KERNEL_TENSOR_15_TPC7_CFG_SECTION          0x3800
+#define mmKERNEL_SYNC_OBJECT_TPC7_CFG_BASE         0x7FFCFC6780ull
+#define KERNEL_SYNC_OBJECT_TPC7_CFG_MAX_OFFSET     0x8000
+#define KERNEL_SYNC_OBJECT_TPC7_CFG_SECTION        0x8000
+#define mmKERNEL_TPC7_CFG_BASE                     0x7FFCFC6788ull
+#define KERNEL_TPC7_CFG_MAX_OFFSET                 0xB800
+#define KERNEL_TPC7_CFG_SECTION                    0x2780
+#define mmQM_TENSOR_0_TPC7_CFG_BASE                0x7FFCFC6A00ull
+#define QM_TENSOR_0_TPC7_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_0_TPC7_CFG_SECTION               0x3800
+#define mmQM_TENSOR_1_TPC7_CFG_BASE                0x7FFCFC6A38ull
+#define QM_TENSOR_1_TPC7_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_1_TPC7_CFG_SECTION               0x3800
+#define mmQM_TENSOR_2_TPC7_CFG_BASE                0x7FFCFC6A70ull
+#define QM_TENSOR_2_TPC7_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_2_TPC7_CFG_SECTION               0x3800
+#define mmQM_TENSOR_3_TPC7_CFG_BASE                0x7FFCFC6AA8ull
+#define QM_TENSOR_3_TPC7_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_3_TPC7_CFG_SECTION               0x3800
+#define mmQM_TENSOR_4_TPC7_CFG_BASE                0x7FFCFC6AE0ull
+#define QM_TENSOR_4_TPC7_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_4_TPC7_CFG_SECTION               0x3800
+#define mmQM_TENSOR_5_TPC7_CFG_BASE                0x7FFCFC6B18ull
+#define QM_TENSOR_5_TPC7_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_5_TPC7_CFG_SECTION               0x3800
+#define mmQM_TENSOR_6_TPC7_CFG_BASE                0x7FFCFC6B50ull
+#define QM_TENSOR_6_TPC7_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_6_TPC7_CFG_SECTION               0x3800
+#define mmQM_TENSOR_7_TPC7_CFG_BASE                0x7FFCFC6B88ull
+#define QM_TENSOR_7_TPC7_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_7_TPC7_CFG_SECTION               0x3800
+#define mmQM_TENSOR_8_TPC7_CFG_BASE                0x7FFCFC6BC0ull
+#define QM_TENSOR_8_TPC7_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_8_TPC7_CFG_SECTION               0x3800
+#define mmQM_TENSOR_9_TPC7_CFG_BASE                0x7FFCFC6BF8ull
+#define QM_TENSOR_9_TPC7_CFG_MAX_OFFSET            0x3800
+#define QM_TENSOR_9_TPC7_CFG_SECTION               0x3800
+#define mmQM_TENSOR_10_TPC7_CFG_BASE               0x7FFCFC6C30ull
+#define QM_TENSOR_10_TPC7_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_10_TPC7_CFG_SECTION              0x3800
+#define mmQM_TENSOR_11_TPC7_CFG_BASE               0x7FFCFC6C68ull
+#define QM_TENSOR_11_TPC7_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_11_TPC7_CFG_SECTION              0x3800
+#define mmQM_TENSOR_12_TPC7_CFG_BASE               0x7FFCFC6CA0ull
+#define QM_TENSOR_12_TPC7_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_12_TPC7_CFG_SECTION              0x3800
+#define mmQM_TENSOR_13_TPC7_CFG_BASE               0x7FFCFC6CD8ull
+#define QM_TENSOR_13_TPC7_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_13_TPC7_CFG_SECTION              0x3800
+#define mmQM_TENSOR_14_TPC7_CFG_BASE               0x7FFCFC6D10ull
+#define QM_TENSOR_14_TPC7_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_14_TPC7_CFG_SECTION              0x3800
+#define mmQM_TENSOR_15_TPC7_CFG_BASE               0x7FFCFC6D48ull
+#define QM_TENSOR_15_TPC7_CFG_MAX_OFFSET           0x3800
+#define QM_TENSOR_15_TPC7_CFG_SECTION              0x3800
+#define mmQM_SYNC_OBJECT_TPC7_CFG_BASE             0x7FFCFC6D80ull
+#define QM_SYNC_OBJECT_TPC7_CFG_MAX_OFFSET         0x8000
+#define QM_SYNC_OBJECT_TPC7_CFG_SECTION            0x8000
+#define mmQM_TPC7_CFG_BASE                         0x7FFCFC6D88ull
+#define QM_TPC7_CFG_MAX_OFFSET                     0xB800
+#define QM_TPC7_CFG_SECTION                        0x2780
+#define mmTPC7_E2E_CRED_BASE                       0x7FFCFC7000ull
+#define TPC7_E2E_CRED_MAX_OFFSET                   0x1680
+#define TPC7_E2E_CRED_SECTION                      0x1000
+#define mmTPC7_QM_BASE                             0x7FFCFC8000ull
+#define TPC7_QM_MAX_OFFSET                         0xD040
+#define TPC7_QM_SECTION                            0x1038000
+#define mmMME_S_ROM_TABLE_BASE                     0x7FFE000000ull
+#define MME_S_ROM_TABLE_MAX_OFFSET                 0x1000
+#define MME_S_ROM_TABLE_SECTION                    0x21000
+#define mmMME0_ACC_STM_BASE                        0x7FFE021000ull
+#define MME0_ACC_STM_MAX_OFFSET                    0x1000
+#define MME0_ACC_STM_SECTION                       0x1000
+#define mmMME0_ACC_CTI_BASE                        0x7FFE022000ull
+#define MME0_ACC_CTI_MAX_OFFSET                    0x1000
+#define MME0_ACC_CTI_SECTION                       0x1000
+#define mmMME0_ACC_ETF_BASE                        0x7FFE023000ull
+#define MME0_ACC_ETF_MAX_OFFSET                    0x1000
+#define MME0_ACC_ETF_SECTION                       0x1000
+#define mmMME0_ACC_SPMU_BASE                       0x7FFE024000ull
+#define MME0_ACC_SPMU_MAX_OFFSET                   0x1000
+#define MME0_ACC_SPMU_SECTION                      0x1000
+#define mmMME0_ACC_CTI0_BASE                       0x7FFE025000ull
+#define MME0_ACC_CTI0_MAX_OFFSET                   0x1000
+#define MME0_ACC_CTI0_SECTION                      0x1000
+#define mmMME0_ACC_CTI1_BASE                       0x7FFE026000ull
+#define MME0_ACC_CTI1_MAX_OFFSET                   0x1000
+#define MME0_ACC_CTI1_SECTION                      0x1000
+#define mmMME0_ACC_BMON0_BASE                      0x7FFE027000ull
+#define MME0_ACC_BMON0_MAX_OFFSET                  0x1000
+#define MME0_ACC_BMON0_SECTION                     0x9000
+#define mmMME0_ACC_FUNNEL_BASE                     0x7FFE030000ull
+#define MME0_ACC_FUNNEL_MAX_OFFSET                 0x1000
+#define MME0_ACC_FUNNEL_SECTION                    0x11000
+#define mmMME0_SBAB_STM_BASE                       0x7FFE041000ull
+#define MME0_SBAB_STM_MAX_OFFSET                   0x1000
+#define MME0_SBAB_STM_SECTION                      0x1000
+#define mmMME0_SBAB_CTI_BASE                       0x7FFE042000ull
+#define MME0_SBAB_CTI_MAX_OFFSET                   0x1000
+#define MME0_SBAB_CTI_SECTION                      0x1000
+#define mmMME0_SBAB_ETF_BASE                       0x7FFE043000ull
+#define MME0_SBAB_ETF_MAX_OFFSET                   0x1000
+#define MME0_SBAB_ETF_SECTION                      0x1000
+#define mmMME0_SBAB_SPMU_BASE                      0x7FFE044000ull
+#define MME0_SBAB_SPMU_MAX_OFFSET                  0x1000
+#define MME0_SBAB_SPMU_SECTION                     0x1000
+#define mmMME0_SBAB_CTI0_BASE                      0x7FFE045000ull
+#define MME0_SBAB_CTI0_MAX_OFFSET                  0x1000
+#define MME0_SBAB_CTI0_SECTION                     0x1000
+#define mmMME0_SBAB_CTI1_BASE                      0x7FFE046000ull
+#define MME0_SBAB_CTI1_MAX_OFFSET                  0x1000
+#define MME0_SBAB_CTI1_SECTION                     0x1000
+#define mmMME0_SBAB_BMON0_BASE                     0x7FFE047000ull
+#define MME0_SBAB_BMON0_MAX_OFFSET                 0x1000
+#define MME0_SBAB_BMON0_SECTION                    0x1000
+#define mmMME0_SBAB_BMON1_BASE                     0x7FFE048000ull
+#define MME0_SBAB_BMON1_MAX_OFFSET                 0x1000
+#define MME0_SBAB_BMON1_SECTION                    0x19000
+#define mmMME0_CTRL_STM_BASE                       0x7FFE061000ull
+#define MME0_CTRL_STM_MAX_OFFSET                   0x1000
+#define MME0_CTRL_STM_SECTION                      0x1000
+#define mmMME0_CTRL_CTI_BASE                       0x7FFE062000ull
+#define MME0_CTRL_CTI_MAX_OFFSET                   0x1000
+#define MME0_CTRL_CTI_SECTION                      0x1000
+#define mmMME0_CTRL_ETF_BASE                       0x7FFE063000ull
+#define MME0_CTRL_ETF_MAX_OFFSET                   0x1000
+#define MME0_CTRL_ETF_SECTION                      0x1000
+#define mmMME0_CTRL_SPMU_BASE                      0x7FFE064000ull
+#define MME0_CTRL_SPMU_MAX_OFFSET                  0x1000
+#define MME0_CTRL_SPMU_SECTION                     0x1000
+#define mmMME0_CTRL_CTI0_BASE                      0x7FFE065000ull
+#define MME0_CTRL_CTI0_MAX_OFFSET                  0x1000
+#define MME0_CTRL_CTI0_SECTION                     0x1000
+#define mmMME0_CTRL_CTI1_BASE                      0x7FFE066000ull
+#define MME0_CTRL_CTI1_MAX_OFFSET                  0x1000
+#define MME0_CTRL_CTI1_SECTION                     0x1000
+#define mmMME0_CTRL_BMON0_BASE                     0x7FFE067000ull
+#define MME0_CTRL_BMON0_MAX_OFFSET                 0x1000
+#define MME0_CTRL_BMON0_SECTION                    0x1000
+#define mmMME0_CTRL_BMON1_BASE                     0x7FFE068000ull
+#define MME0_CTRL_BMON1_MAX_OFFSET                 0x1000
+#define MME0_CTRL_BMON1_SECTION                    0x39000
+#define mmMME1_ACC_STM_BASE                        0x7FFE0A1000ull
+#define MME1_ACC_STM_MAX_OFFSET                    0x1000
+#define MME1_ACC_STM_SECTION                       0x1000
+#define mmMME1_ACC_CTI_BASE                        0x7FFE0A2000ull
+#define MME1_ACC_CTI_MAX_OFFSET                    0x1000
+#define MME1_ACC_CTI_SECTION                       0x1000
+#define mmMME1_ACC_ETF_BASE                        0x7FFE0A3000ull
+#define MME1_ACC_ETF_MAX_OFFSET                    0x1000
+#define MME1_ACC_ETF_SECTION                       0x1000
+#define mmMME1_ACC_SPMU_BASE                       0x7FFE0A4000ull
+#define MME1_ACC_SPMU_MAX_OFFSET                   0x1000
+#define MME1_ACC_SPMU_SECTION                      0x1000
+#define mmMME1_ACC_CTI0_BASE                       0x7FFE0A5000ull
+#define MME1_ACC_CTI0_MAX_OFFSET                   0x1000
+#define MME1_ACC_CTI0_SECTION                      0x1000
+#define mmMME1_ACC_CTI1_BASE                       0x7FFE0A6000ull
+#define MME1_ACC_CTI1_MAX_OFFSET                   0x1000
+#define MME1_ACC_CTI1_SECTION                      0x1000
+#define mmMME1_ACC_BMON0_BASE                      0x7FFE0A7000ull
+#define MME1_ACC_BMON0_MAX_OFFSET                  0x1000
+#define MME1_ACC_BMON0_SECTION                     0x9000
+#define mmMME1_ACC_FUNNEL_BASE                     0x7FFE0B0000ull
+#define MME1_ACC_FUNNEL_MAX_OFFSET                 0x1000
+#define MME1_ACC_FUNNEL_SECTION                    0x11000
+#define mmMME1_SBAB_STM_BASE                       0x7FFE0C1000ull
+#define MME1_SBAB_STM_MAX_OFFSET                   0x1000
+#define MME1_SBAB_STM_SECTION                      0x1000
+#define mmMME1_SBAB_CTI_BASE                       0x7FFE0C2000ull
+#define MME1_SBAB_CTI_MAX_OFFSET                   0x1000
+#define MME1_SBAB_CTI_SECTION                      0x1000
+#define mmMME1_SBAB_ETF_BASE                       0x7FFE0C3000ull
+#define MME1_SBAB_ETF_MAX_OFFSET                   0x1000
+#define MME1_SBAB_ETF_SECTION                      0x1000
+#define mmMME1_SBAB_SPMU_BASE                      0x7FFE0C4000ull
+#define MME1_SBAB_SPMU_MAX_OFFSET                  0x1000
+#define MME1_SBAB_SPMU_SECTION                     0x1000
+#define mmMME1_SBAB_CTI0_BASE                      0x7FFE0C5000ull
+#define MME1_SBAB_CTI0_MAX_OFFSET                  0x1000
+#define MME1_SBAB_CTI0_SECTION                     0x1000
+#define mmMME1_SBAB_CTI1_BASE                      0x7FFE0C6000ull
+#define MME1_SBAB_CTI1_MAX_OFFSET                  0x1000
+#define MME1_SBAB_CTI1_SECTION                     0x1000
+#define mmMME1_SBAB_BMON0_BASE                     0x7FFE0C7000ull
+#define MME1_SBAB_BMON0_MAX_OFFSET                 0x1000
+#define MME1_SBAB_BMON0_SECTION                    0x1000
+#define mmMME1_SBAB_BMON1_BASE                     0x7FFE0C8000ull
+#define MME1_SBAB_BMON1_MAX_OFFSET                 0x1000
+#define MME1_SBAB_BMON1_SECTION                    0x19000
+#define mmMME1_CTRL_STM_BASE                       0x7FFE0E1000ull
+#define MME1_CTRL_STM_MAX_OFFSET                   0x1000
+#define MME1_CTRL_STM_SECTION                      0x1000
+#define mmMME1_CTRL_CTI_BASE                       0x7FFE0E2000ull
+#define MME1_CTRL_CTI_MAX_OFFSET                   0x1000
+#define MME1_CTRL_CTI_SECTION                      0x1000
+#define mmMME1_CTRL_ETF_BASE                       0x7FFE0E3000ull
+#define MME1_CTRL_ETF_MAX_OFFSET                   0x1000
+#define MME1_CTRL_ETF_SECTION                      0x1000
+#define mmMME1_CTRL_SPMU_BASE                      0x7FFE0E4000ull
+#define MME1_CTRL_SPMU_MAX_OFFSET                  0x1000
+#define MME1_CTRL_SPMU_SECTION                     0x1000
+#define mmMME1_CTRL_CTI0_BASE                      0x7FFE0E5000ull
+#define MME1_CTRL_CTI0_MAX_OFFSET                  0x1000
+#define MME1_CTRL_CTI0_SECTION                     0x1000
+#define mmMME1_CTRL_CTI1_BASE                      0x7FFE0E6000ull
+#define MME1_CTRL_CTI1_MAX_OFFSET                  0x1000
+#define MME1_CTRL_CTI1_SECTION                     0x1000
+#define mmMME1_CTRL_BMON0_BASE                     0x7FFE0E7000ull
+#define MME1_CTRL_BMON0_MAX_OFFSET                 0x1000
+#define MME1_CTRL_BMON0_SECTION                    0x1000
+#define mmMME1_CTRL_BMON1_BASE                     0x7FFE0E8000ull
+#define MME1_CTRL_BMON1_MAX_OFFSET                 0x1000
+#define MME1_CTRL_BMON1_SECTION                    0x18000
+#define mmMME_N_ROM_TABLE_BASE                     0x7FFE100000ull
+#define MME_N_ROM_TABLE_MAX_OFFSET                 0x1000
+#define MME_N_ROM_TABLE_SECTION                    0x21000
+#define mmMME2_ACC_STM_BASE                        0x7FFE121000ull
+#define MME2_ACC_STM_MAX_OFFSET                    0x1000
+#define MME2_ACC_STM_SECTION                       0x1000
+#define mmMME2_ACC_CTI_BASE                        0x7FFE122000ull
+#define MME2_ACC_CTI_MAX_OFFSET                    0x1000
+#define MME2_ACC_CTI_SECTION                       0x1000
+#define mmMME2_MME2_ACC_ETF_BASE                   0x7FFE123000ull
+#define MME2_MME2_ACC_ETF_MAX_OFFSET               0x1000
+#define MME2_MME2_ACC_ETF_SECTION                  0x1000
+#define mmMME2_ACC_SPMU_BASE                       0x7FFE124000ull
+#define MME2_ACC_SPMU_MAX_OFFSET                   0x1000
+#define MME2_ACC_SPMU_SECTION                      0x1000
+#define mmMME2_ACC_CTI0_BASE                       0x7FFE125000ull
+#define MME2_ACC_CTI0_MAX_OFFSET                   0x1000
+#define MME2_ACC_CTI0_SECTION                      0x1000
+#define mmMME2_ACC_CTI1_BASE                       0x7FFE126000ull
+#define MME2_ACC_CTI1_MAX_OFFSET                   0x1000
+#define MME2_ACC_CTI1_SECTION                      0x1000
+#define mmMME2_ACC_BMON0_BASE                      0x7FFE127000ull
+#define MME2_ACC_BMON0_MAX_OFFSET                  0x1000
+#define MME2_ACC_BMON0_SECTION                     0x9000
+#define mmMME2_ACC_FUNNEL_BASE                     0x7FFE130000ull
+#define MME2_ACC_FUNNEL_MAX_OFFSET                 0x1000
+#define MME2_ACC_FUNNEL_SECTION                    0x11000
+#define mmMME2_SBAB_STM_BASE                       0x7FFE141000ull
+#define MME2_SBAB_STM_MAX_OFFSET                   0x1000
+#define MME2_SBAB_STM_SECTION                      0x1000
+#define mmMME2_SBAB_CTI_BASE                       0x7FFE142000ull
+#define MME2_SBAB_CTI_MAX_OFFSET                   0x1000
+#define MME2_SBAB_CTI_SECTION                      0x1000
+#define mmMME2_SBAB_ETF_BASE                       0x7FFE143000ull
+#define MME2_SBAB_ETF_MAX_OFFSET                   0x1000
+#define MME2_SBAB_ETF_SECTION                      0x1000
+#define mmMME2_SBAB_SPMU_BASE                      0x7FFE144000ull
+#define MME2_SBAB_SPMU_MAX_OFFSET                  0x1000
+#define MME2_SBAB_SPMU_SECTION                     0x1000
+#define mmMME2_SBAB_CTI0_BASE                      0x7FFE145000ull
+#define MME2_SBAB_CTI0_MAX_OFFSET                  0x1000
+#define MME2_SBAB_CTI0_SECTION                     0x1000
+#define mmMME2_SBAB_CTI1_BASE                      0x7FFE146000ull
+#define MME2_SBAB_CTI1_MAX_OFFSET                  0x1000
+#define MME2_SBAB_CTI1_SECTION                     0x1000
+#define mmMME2_SBAB_BMON0_BASE                     0x7FFE147000ull
+#define MME2_SBAB_BMON0_MAX_OFFSET                 0x1000
+#define MME2_SBAB_BMON0_SECTION                    0x1000
+#define mmMME2_SBAB_BMON1_BASE                     0x7FFE148000ull
+#define MME2_SBAB_BMON1_MAX_OFFSET                 0x1000
+#define MME2_SBAB_BMON1_SECTION                    0x19000
+#define mmMME2_CTRL_STM_BASE                       0x7FFE161000ull
+#define MME2_CTRL_STM_MAX_OFFSET                   0x1000
+#define MME2_CTRL_STM_SECTION                      0x1000
+#define mmMME2_CTRL_CTI_BASE                       0x7FFE162000ull
+#define MME2_CTRL_CTI_MAX_OFFSET                   0x1000
+#define MME2_CTRL_CTI_SECTION                      0x1000
+#define mmMME2_CTRL_ETF_BASE                       0x7FFE163000ull
+#define MME2_CTRL_ETF_MAX_OFFSET                   0x1000
+#define MME2_CTRL_ETF_SECTION                      0x1000
+#define mmMME2_CTRL_SPMU_BASE                      0x7FFE164000ull
+#define MME2_CTRL_SPMU_MAX_OFFSET                  0x1000
+#define MME2_CTRL_SPMU_SECTION                     0x1000
+#define mmMME2_CTRL_CTI0_BASE                      0x7FFE165000ull
+#define MME2_CTRL_CTI0_MAX_OFFSET                  0x1000
+#define MME2_CTRL_CTI0_SECTION                     0x1000
+#define mmMME2_CTRL_CTI1_BASE                      0x7FFE166000ull
+#define MME2_CTRL_CTI1_MAX_OFFSET                  0x1000
+#define MME2_CTRL_CTI1_SECTION                     0x1000
+#define mmMME2_CTRL_BMON0_BASE                     0x7FFE167000ull
+#define MME2_CTRL_BMON0_MAX_OFFSET                 0x1000
+#define MME2_CTRL_BMON0_SECTION                    0x1000
+#define mmMME2_CTRL_BMON1_BASE                     0x7FFE168000ull
+#define MME2_CTRL_BMON1_MAX_OFFSET                 0x1000
+#define MME2_CTRL_BMON1_SECTION                    0x39000
+#define mmMME3_ACC_STM_BASE                        0x7FFE1A1000ull
+#define MME3_ACC_STM_MAX_OFFSET                    0x1000
+#define MME3_ACC_STM_SECTION                       0x1000
+#define mmMME3_ACC_CTI_BASE                        0x7FFE1A2000ull
+#define MME3_ACC_CTI_MAX_OFFSET                    0x1000
+#define MME3_ACC_CTI_SECTION                       0x1000
+#define mmMME3_ACC_ETF_BASE                        0x7FFE1A3000ull
+#define MME3_ACC_ETF_MAX_OFFSET                    0x1000
+#define MME3_ACC_ETF_SECTION                       0x1000
+#define mmMME3_ACC_SPMU_BASE                       0x7FFE1A4000ull
+#define MME3_ACC_SPMU_MAX_OFFSET                   0x1000
+#define MME3_ACC_SPMU_SECTION                      0x1000
+#define mmMME3_ACC_CTI0_BASE                       0x7FFE1A5000ull
+#define MME3_ACC_CTI0_MAX_OFFSET                   0x1000
+#define MME3_ACC_CTI0_SECTION                      0x1000
+#define mmMME3_ACC_CTI1_BASE                       0x7FFE1A6000ull
+#define MME3_ACC_CTI1_MAX_OFFSET                   0x1000
+#define MME3_ACC_CTI1_SECTION                      0x1000
+#define mmMME3_ACC_BMON0_BASE                      0x7FFE1A7000ull
+#define MME3_ACC_BMON0_MAX_OFFSET                  0x1000
+#define MME3_ACC_BMON0_SECTION                     0x9000
+#define mmMME3_ACC_FUNNEL_BASE                     0x7FFE1B0000ull
+#define MME3_ACC_FUNNEL_MAX_OFFSET                 0x1000
+#define MME3_ACC_FUNNEL_SECTION                    0x11000
+#define mmMME3_SBAB_STM_BASE                       0x7FFE1C1000ull
+#define MME3_SBAB_STM_MAX_OFFSET                   0x1000
+#define MME3_SBAB_STM_SECTION                      0x1000
+#define mmMME3_SBAB_CTI_BASE                       0x7FFE1C2000ull
+#define MME3_SBAB_CTI_MAX_OFFSET                   0x1000
+#define MME3_SBAB_CTI_SECTION                      0x1000
+#define mmMME3_SBAB_ETF_BASE                       0x7FFE1C3000ull
+#define MME3_SBAB_ETF_MAX_OFFSET                   0x1000
+#define MME3_SBAB_ETF_SECTION                      0x1000
+#define mmMME3_SBAB_SPMU_BASE                      0x7FFE1C4000ull
+#define MME3_SBAB_SPMU_MAX_OFFSET                  0x1000
+#define MME3_SBAB_SPMU_SECTION                     0x1000
+#define mmMME3_SBAB_CTI0_BASE                      0x7FFE1C5000ull
+#define MME3_SBAB_CTI0_MAX_OFFSET                  0x1000
+#define MME3_SBAB_CTI0_SECTION                     0x1000
+#define mmMME3_SBAB_CTI1_BASE                      0x7FFE1C6000ull
+#define MME3_SBAB_CTI1_MAX_OFFSET                  0x1000
+#define MME3_SBAB_CTI1_SECTION                     0x1000
+#define mmMME3_SBAB_BMON0_BASE                     0x7FFE1C7000ull
+#define MME3_SBAB_BMON0_MAX_OFFSET                 0x1000
+#define MME3_SBAB_BMON0_SECTION                    0x1000
+#define mmMME3_SBAB_BMON1_BASE                     0x7FFE1C8000ull
+#define MME3_SBAB_BMON1_MAX_OFFSET                 0x1000
+#define MME3_SBAB_BMON1_SECTION                    0x19000
+#define mmMME3_CTRL_STM_BASE                       0x7FFE1E1000ull
+#define MME3_CTRL_STM_MAX_OFFSET                   0x1000
+#define MME3_CTRL_STM_SECTION                      0x1000
+#define mmMME3_CTRL_CTI_BASE                       0x7FFE1E2000ull
+#define MME3_CTRL_CTI_MAX_OFFSET                   0x1000
+#define MME3_CTRL_CTI_SECTION                      0x1000
+#define mmMME3_CTRL_ETF_BASE                       0x7FFE1E3000ull
+#define MME3_CTRL_ETF_MAX_OFFSET                   0x1000
+#define MME3_CTRL_ETF_SECTION                      0x1000
+#define mmMME3_CTRL_SPMU_BASE                      0x7FFE1E4000ull
+#define MME3_CTRL_SPMU_MAX_OFFSET                  0x1000
+#define MME3_CTRL_SPMU_SECTION                     0x1000
+#define mmMME3_CTRL_CTI0_BASE                      0x7FFE1E5000ull
+#define MME3_CTRL_CTI0_MAX_OFFSET                  0x1000
+#define MME3_CTRL_CTI0_SECTION                     0x1000
+#define mmMME3_CTRL_CTI1_BASE                      0x7FFE1E6000ull
+#define MME3_CTRL_CTI1_MAX_OFFSET                  0x1000
+#define MME3_CTRL_CTI1_SECTION                     0x1000
+#define mmMME3_CTRL_BMON0_BASE                     0x7FFE1E7000ull
+#define MME3_CTRL_BMON0_MAX_OFFSET                 0x1000
+#define MME3_CTRL_BMON0_SECTION                    0x1000
+#define mmMME3_CTRL_BMON1_BASE                     0x7FFE1E8000ull
+#define MME3_CTRL_BMON1_MAX_OFFSET                 0x1000
+#define MME3_CTRL_BMON1_SECTION                    0x18000
+#define mmIC_ROM_TABLE_BASE                        0x7FFE200000ull
+#define IC_ROM_TABLE_MAX_OFFSET                    0x1000
+#define IC_ROM_TABLE_SECTION                       0x1000
+#define mmSRAM_Y0_X0_FUNNEL_BASE                   0x7FFE201000ull
+#define SRAM_Y0_X0_FUNNEL_MAX_OFFSET               0x1000
+#define SRAM_Y0_X0_FUNNEL_SECTION                  0x8000
+#define mmSRAM_Y0_X1_FUNNEL_BASE                   0x7FFE209000ull
+#define SRAM_Y0_X1_FUNNEL_MAX_OFFSET               0x1000
+#define SRAM_Y0_X1_FUNNEL_SECTION                  0x8000
+#define mmSRAM_Y0_X2_FUNNEL_BASE                   0x7FFE211000ull
+#define SRAM_Y0_X2_FUNNEL_MAX_OFFSET               0x1000
+#define SRAM_Y0_X2_FUNNEL_SECTION                  0x8000
+#define mmSRAM_Y0_X3_FUNNEL_BASE                   0x7FFE219000ull
+#define SRAM_Y0_X3_FUNNEL_MAX_OFFSET               0x1000
+#define SRAM_Y0_X3_FUNNEL_SECTION                  0x8000
+#define mmSRAM_Y0_X4_FUNNEL_BASE                   0x7FFE221000ull
+#define SRAM_Y0_X4_FUNNEL_MAX_OFFSET               0x1000
+#define SRAM_Y0_X4_FUNNEL_SECTION                  0x8000
+#define mmSRAM_Y0_X5_FUNNEL_BASE                   0x7FFE229000ull
+#define SRAM_Y0_X5_FUNNEL_MAX_OFFSET               0x1000
+#define SRAM_Y0_X5_FUNNEL_SECTION                  0x8000
+#define mmSRAM_Y0_X6_FUNNEL_BASE                   0x7FFE231000ull
+#define SRAM_Y0_X6_FUNNEL_MAX_OFFSET               0x1000
+#define SRAM_Y0_X6_FUNNEL_SECTION                  0x8000
+#define mmSRAM_Y0_X7_FUNNEL_BASE                   0x7FFE239000ull
+#define SRAM_Y0_X7_FUNNEL_MAX_OFFSET               0x1000
+#define SRAM_Y0_X7_FUNNEL_SECTION                  0x8000
+#define mmSRAM_Y1_X0_FUNNEL_BASE                   0x7FFE241000ull
+#define SRAM_Y1_X0_FUNNEL_MAX_OFFSET               0x1000
+#define SRAM_Y1_X0_FUNNEL_SECTION                  0x8000
+#define mmSRAM_Y1_X1_FUNNEL_BASE                   0x7FFE249000ull
+#define SRAM_Y1_X1_FUNNEL_MAX_OFFSET               0x1000
+#define SRAM_Y1_X1_FUNNEL_SECTION                  0x8000
+#define mmSRAM_Y1_X2_FUNNEL_BASE                   0x7FFE251000ull
+#define SRAM_Y1_X2_FUNNEL_MAX_OFFSET               0x1000
+#define SRAM_Y1_X2_FUNNEL_SECTION                  0x8000
+#define mmSRAM_Y1_X3_FUNNEL_BASE                   0x7FFE259000ull
+#define SRAM_Y1_X3_FUNNEL_MAX_OFFSET               0x1000
+#define SRAM_Y1_X3_FUNNEL_SECTION                  0x8000
+#define mmSRAM_Y1_X4_FUNNEL_BASE                   0x7FFE261000ull
+#define SRAM_Y1_X4_FUNNEL_MAX_OFFSET               0x1000
+#define SRAM_Y1_X4_FUNNEL_SECTION                  0x8000
+#define mmSRAM_Y1_X5_FUNNEL_BASE                   0x7FFE269000ull
+#define SRAM_Y1_X5_FUNNEL_MAX_OFFSET               0x1000
+#define SRAM_Y1_X5_FUNNEL_SECTION                  0x8000
+#define mmSRAM_Y1_X6_FUNNEL_BASE                   0x7FFE271000ull
+#define SRAM_Y1_X6_FUNNEL_MAX_OFFSET               0x1000
+#define SRAM_Y1_X6_FUNNEL_SECTION                  0x8000
+#define mmSRAM_Y1_X7_FUNNEL_BASE                   0x7FFE279000ull
+#define SRAM_Y1_X7_FUNNEL_MAX_OFFSET               0x1000
+#define SRAM_Y1_X7_FUNNEL_SECTION                  0x8000
+#define mmSRAM_Y2_X0_FUNNEL_BASE                   0x7FFE281000ull
+#define SRAM_Y2_X0_FUNNEL_MAX_OFFSET               0x1000
+#define SRAM_Y2_X0_FUNNEL_SECTION                  0x8000
+#define mmSRAM_Y2_X1_FUNNEL_BASE                   0x7FFE289000ull
+#define SRAM_Y2_X1_FUNNEL_MAX_OFFSET               0x1000
+#define SRAM_Y2_X1_FUNNEL_SECTION                  0x8000
+#define mmSRAM_Y2_X2_FUNNEL_BASE                   0x7FFE291000ull
+#define SRAM_Y2_X2_FUNNEL_MAX_OFFSET               0x1000
+#define SRAM_Y2_X2_FUNNEL_SECTION                  0x8000
+#define mmSRAM_Y2_X3_FUNNEL_BASE                   0x7FFE299000ull
+#define SRAM_Y2_X3_FUNNEL_MAX_OFFSET               0x1000
+#define SRAM_Y2_X3_FUNNEL_SECTION                  0x8000
+#define mmSRAM_Y2_X4_FUNNEL_BASE                   0x7FFE2A1000ull
+#define SRAM_Y2_X4_FUNNEL_MAX_OFFSET               0x1000
+#define SRAM_Y2_X4_FUNNEL_SECTION                  0x8000
+#define mmSRAM_Y2_X5_FUNNEL_BASE                   0x7FFE2A9000ull
+#define SRAM_Y2_X5_FUNNEL_MAX_OFFSET               0x1000
+#define SRAM_Y2_X5_FUNNEL_SECTION                  0x8000
+#define mmSRAM_Y2_X6_FUNNEL_BASE                   0x7FFE2B1000ull
+#define SRAM_Y2_X6_FUNNEL_MAX_OFFSET               0x1000
+#define SRAM_Y2_X6_FUNNEL_SECTION                  0x8000
+#define mmSRAM_Y2_X7_FUNNEL_BASE                   0x7FFE2B9000ull
+#define SRAM_Y2_X7_FUNNEL_MAX_OFFSET               0x1000
+#define SRAM_Y2_X7_FUNNEL_SECTION                  0x8000
+#define mmSRAM_Y3_X0_FUNNEL_BASE                   0x7FFE2C1000ull
+#define SRAM_Y3_X0_FUNNEL_MAX_OFFSET               0x1000
+#define SRAM_Y3_X0_FUNNEL_SECTION                  0x8000
+#define mmSRAM_Y3_X1_FUNNEL_BASE                   0x7FFE2C9000ull
+#define SRAM_Y3_X1_FUNNEL_MAX_OFFSET               0x1000
+#define SRAM_Y3_X1_FUNNEL_SECTION                  0x8000
+#define mmSRAM_Y3_X2_FUNNEL_BASE                   0x7FFE2D1000ull
+#define SRAM_Y3_X2_FUNNEL_MAX_OFFSET               0x1000
+#define SRAM_Y3_X2_FUNNEL_SECTION                  0x8000
+#define mmSRAM_Y3_X4_FUNNEL_BASE                   0x7FFE2D9000ull
+#define SRAM_Y3_X4_FUNNEL_MAX_OFFSET               0x1000
+#define SRAM_Y3_X4_FUNNEL_SECTION                  0x8000
+#define mmSRAM_Y3_X3_FUNNEL_BASE                   0x7FFE2E1000ull
+#define SRAM_Y3_X3_FUNNEL_MAX_OFFSET               0x1000
+#define SRAM_Y3_X3_FUNNEL_SECTION                  0x8000
+#define mmSRAM_Y3_X5_FUNNEL_BASE                   0x7FFE2E9000ull
+#define SRAM_Y3_X5_FUNNEL_MAX_OFFSET               0x1000
+#define SRAM_Y3_X5_FUNNEL_SECTION                  0x8000
+#define mmSRAM_Y3_X6_FUNNEL_BASE                   0x7FFE2F1000ull
+#define SRAM_Y3_X6_FUNNEL_MAX_OFFSET               0x1000
+#define SRAM_Y3_X6_FUNNEL_SECTION                  0x8000
+#define mmSRAM_Y3_X7_FUNNEL_BASE                   0x7FFE2F9000ull
+#define SRAM_Y3_X7_FUNNEL_MAX_OFFSET               0x1000
+#define SRAM_Y3_X7_FUNNEL_SECTION                  0x7000
+#define mmIF_ROM_TABLE_BASE                        0x7FFE300000ull
+#define IF_ROM_TABLE_MAX_OFFSET                    0x1000
+#define IF_ROM_TABLE_SECTION                       0x1000
+#define mmSIF_FUNNEL_0_BASE                        0x7FFE301000ull
+#define SIF_FUNNEL_0_MAX_OFFSET                    0x1000
+#define SIF_FUNNEL_0_SECTION                       0x10000
+#define mmSIF_FUNNEL_1_BASE                        0x7FFE311000ull
+#define SIF_FUNNEL_1_MAX_OFFSET                    0x1000
+#define SIF_FUNNEL_1_SECTION                       0x10000
+#define mmSIF_FUNNEL_2_BASE                        0x7FFE321000ull
+#define SIF_FUNNEL_2_MAX_OFFSET                    0x1000
+#define SIF_FUNNEL_2_SECTION                       0x10000
+#define mmSIF_FUNNEL_3_BASE                        0x7FFE331000ull
+#define SIF_FUNNEL_3_MAX_OFFSET                    0x1000
+#define SIF_FUNNEL_3_SECTION                       0x10000
+#define mmSIF_FUNNEL_4_BASE                        0x7FFE341000ull
+#define SIF_FUNNEL_4_MAX_OFFSET                    0x1000
+#define SIF_FUNNEL_4_SECTION                       0x10000
+#define mmSIF_FUNNEL_5_BASE                        0x7FFE351000ull
+#define SIF_FUNNEL_5_MAX_OFFSET                    0x1000
+#define SIF_FUNNEL_5_SECTION                       0x10000
+#define mmSIF_FUNNEL_6_BASE                        0x7FFE361000ull
+#define SIF_FUNNEL_6_MAX_OFFSET                    0x1000
+#define SIF_FUNNEL_6_SECTION                       0x10000
+#define mmSIF_FUNNEL_7_BASE                        0x7FFE371000ull
+#define SIF_FUNNEL_7_MAX_OFFSET                    0x1000
+#define SIF_FUNNEL_7_SECTION                       0x10000
+#define mmNIF_FUNNEL_0_BASE                        0x7FFE381000ull
+#define NIF_FUNNEL_0_MAX_OFFSET                    0x1000
+#define NIF_FUNNEL_0_SECTION                       0x10000
+#define mmNIF_FUNNEL_1_BASE                        0x7FFE391000ull
+#define NIF_FUNNEL_1_MAX_OFFSET                    0x1000
+#define NIF_FUNNEL_1_SECTION                       0x10000
+#define mmNIF_FUNNEL_2_BASE                        0x7FFE3A1000ull
+#define NIF_FUNNEL_2_MAX_OFFSET                    0x1000
+#define NIF_FUNNEL_2_SECTION                       0x10000
+#define mmNIF_FUNNEL_3_BASE                        0x7FFE3B1000ull
+#define NIF_FUNNEL_3_MAX_OFFSET                    0x1000
+#define NIF_FUNNEL_3_SECTION                       0x10000
+#define mmNIF_FUNNEL_4_BASE                        0x7FFE3C1000ull
+#define NIF_FUNNEL_4_MAX_OFFSET                    0x1000
+#define NIF_FUNNEL_4_SECTION                       0x10000
+#define mmNIF_FUNNEL_5_BASE                        0x7FFE3D1000ull
+#define NIF_FUNNEL_5_MAX_OFFSET                    0x1000
+#define NIF_FUNNEL_5_SECTION                       0x10000
+#define mmNIF_FUNNEL_6_BASE                        0x7FFE3E1000ull
+#define NIF_FUNNEL_6_MAX_OFFSET                    0x1000
+#define NIF_FUNNEL_6_SECTION                       0x10000
+#define mmNIF_FUNNEL_7_BASE                        0x7FFE3F1000ull
+#define NIF_FUNNEL_7_MAX_OFFSET                    0x1000
+#define NIF_FUNNEL_7_SECTION                       0xF000
+#define mmDMA_IF_ROM_TABLE_BASE                    0x7FFE400000ull
+#define DMA_IF_ROM_TABLE_MAX_OFFSET                0x1000
+#define DMA_IF_ROM_TABLE_SECTION                   0x1000
+#define mmDMA_IF_W_S_STM_BASE                      0x7FFE401000ull
+#define DMA_IF_W_S_STM_MAX_OFFSET                  0x1000
+#define DMA_IF_W_S_STM_SECTION                     0x1000
+#define mmDMA_IF_W_S_CTI_BASE                      0x7FFE402000ull
+#define DMA_IF_W_S_CTI_MAX_OFFSET                  0x1000
+#define DMA_IF_W_S_CTI_SECTION                     0x1000
+#define mmDMA_IF_W_S_ETF_BASE                      0x7FFE403000ull
+#define DMA_IF_W_S_ETF_MAX_OFFSET                  0x1000
+#define DMA_IF_W_S_ETF_SECTION                     0x2000
+#define mmDMA_IF_W_S_BMON0_CTI_BASE                0x7FFE405000ull
+#define DMA_IF_W_S_BMON0_CTI_MAX_OFFSET            0x1000
+#define DMA_IF_W_S_BMON0_CTI_SECTION               0x1000
+#define mmDMA_IF_W_S_BMON1_CTI_BASE                0x7FFE406000ull
+#define DMA_IF_W_S_BMON1_CTI_MAX_OFFSET            0x1000
+#define DMA_IF_W_S_BMON1_CTI_SECTION               0x1000
+#define mmDMA_IF_W_S_HBM0_WR_BMON_BASE             0x7FFE407000ull
+#define DMA_IF_W_S_HBM0_WR_BMON_MAX_OFFSET         0x1000
+#define DMA_IF_W_S_HBM0_WR_BMON_SECTION            0x1000
+#define mmDMA_IF_W_S_HBM0_RD_BMON_BASE             0x7FFE408000ull
+#define DMA_IF_W_S_HBM0_RD_BMON_MAX_OFFSET         0x1000
+#define DMA_IF_W_S_HBM0_RD_BMON_SECTION            0x1000
+#define mmDMA_IF_W_S_HBM1_WR_BMON_BASE             0x7FFE409000ull
+#define DMA_IF_W_S_HBM1_WR_BMON_MAX_OFFSET         0x1000
+#define DMA_IF_W_S_HBM1_WR_BMON_SECTION            0x1000
+#define mmDMA_IF_W_S_HBM1_RD_BMON_BASE             0x7FFE40A000ull
+#define DMA_IF_W_S_HBM1_RD_BMON_MAX_OFFSET         0x1000
+#define DMA_IF_W_S_HBM1_RD_BMON_SECTION            0x1000
+#define mmDMA_IF_W_S_SOB_WR_BMON_BASE              0x7FFE40B000ull
+#define DMA_IF_W_S_SOB_WR_BMON_MAX_OFFSET          0x1000
+#define DMA_IF_W_S_SOB_WR_BMON_SECTION             0x4000
+#define mmDMA_IF_W_S_FUNNEL_BASE                   0x7FFE40F000ull
+#define DMA_IF_W_S_FUNNEL_MAX_OFFSET               0x1000
+#define DMA_IF_W_S_FUNNEL_SECTION                  0x12000
+#define mmDMA_IF_E_S_STM_BASE                      0x7FFE421000ull
+#define DMA_IF_E_S_STM_MAX_OFFSET                  0x1000
+#define DMA_IF_E_S_STM_SECTION                     0x1000
+#define mmDMA_IF_E_S_CTI_BASE                      0x7FFE422000ull
+#define DMA_IF_E_S_CTI_MAX_OFFSET                  0x1000
+#define DMA_IF_E_S_CTI_SECTION                     0x1000
+#define mmDMA_IF_E_S_ETF_BASE                      0x7FFE423000ull
+#define DMA_IF_E_S_ETF_MAX_OFFSET                  0x1000
+#define DMA_IF_E_S_ETF_SECTION                     0x2000
+#define mmDMA_IF_E_S_BMON0_CTI_BASE                0x7FFE425000ull
+#define DMA_IF_E_S_BMON0_CTI_MAX_OFFSET            0x1000
+#define DMA_IF_E_S_BMON0_CTI_SECTION               0x1000
+#define mmDMA_IF_E_S_BMON1_CTI_BASE                0x7FFE426000ull
+#define DMA_IF_E_S_BMON1_CTI_MAX_OFFSET            0x1000
+#define DMA_IF_E_S_BMON1_CTI_SECTION               0x1000
+#define mmDMA_IF_E_S_HBM0_WR_BMON_BASE             0x7FFE427000ull
+#define DMA_IF_E_S_HBM0_WR_BMON_MAX_OFFSET         0x1000
+#define DMA_IF_E_S_HBM0_WR_BMON_SECTION            0x1000
+#define mmDMA_IF_E_S_HBM0_RD_BMON_BASE             0x7FFE428000ull
+#define DMA_IF_E_S_HBM0_RD_BMON_MAX_OFFSET         0x1000
+#define DMA_IF_E_S_HBM0_RD_BMON_SECTION            0x1000
+#define mmDMA_IF_E_S_HBM1_WR_BMON_BASE             0x7FFE429000ull
+#define DMA_IF_E_S_HBM1_WR_BMON_MAX_OFFSET         0x1000
+#define DMA_IF_E_S_HBM1_WR_BMON_SECTION            0x1000
+#define mmDMA_IF_E_S_HBM1_RD_BMON_BASE             0x7FFE42A000ull
+#define DMA_IF_E_S_HBM1_RD_BMON_MAX_OFFSET         0x1000
+#define DMA_IF_E_S_HBM1_RD_BMON_SECTION            0x1000
+#define mmDMA_IF_E_S_SOB_WR_BMON_BASE              0x7FFE42B000ull
+#define DMA_IF_E_S_SOB_WR_BMON_MAX_OFFSET          0x1000
+#define DMA_IF_E_S_SOB_WR_BMON_SECTION             0x4000
+#define mmDMA_IF_E_S_FUNNEL_BASE                   0x7FFE42F000ull
+#define DMA_IF_E_S_FUNNEL_MAX_OFFSET               0x1000
+#define DMA_IF_E_S_FUNNEL_SECTION                  0x12000
+#define mmDMA_IF_W_N_STM_BASE                      0x7FFE441000ull
+#define DMA_IF_W_N_STM_MAX_OFFSET                  0x1000
+#define DMA_IF_W_N_STM_SECTION                     0x1000
+#define mmDMA_IF_W_N_CTI_BASE                      0x7FFE442000ull
+#define DMA_IF_W_N_CTI_MAX_OFFSET                  0x1000
+#define DMA_IF_W_N_CTI_SECTION                     0x1000
+#define mmDMA_IF_W_N_ETF_BASE                      0x7FFE443000ull
+#define DMA_IF_W_N_ETF_MAX_OFFSET                  0x1000
+#define DMA_IF_W_N_ETF_SECTION                     0x2000
+#define mmDMA_IF_W_N_BMON0_CTI_BASE                0x7FFE445000ull
+#define DMA_IF_W_N_BMON0_CTI_MAX_OFFSET            0x1000
+#define DMA_IF_W_N_BMON0_CTI_SECTION               0x1000
+#define mmDMA_IF_W_N_BMON1_CTI_BASE                0x7FFE446000ull
+#define DMA_IF_W_N_BMON1_CTI_MAX_OFFSET            0x1000
+#define DMA_IF_W_N_BMON1_CTI_SECTION               0x1000
+#define mmDMA_IF_W_N_HBM0_WR_BMON_BASE             0x7FFE447000ull
+#define DMA_IF_W_N_HBM0_WR_BMON_MAX_OFFSET         0x1000
+#define DMA_IF_W_N_HBM0_WR_BMON_SECTION            0x1000
+#define mmDMA_IF_W_N_HBM0_RD_BMON_BASE             0x7FFE448000ull
+#define DMA_IF_W_N_HBM0_RD_BMON_MAX_OFFSET         0x1000
+#define DMA_IF_W_N_HBM0_RD_BMON_SECTION            0x1000
+#define mmDMA_IF_W_N_HBM1_WR_BMON_BASE             0x7FFE449000ull
+#define DMA_IF_W_N_HBM1_WR_BMON_MAX_OFFSET         0x1000
+#define DMA_IF_W_N_HBM1_WR_BMON_SECTION            0x1000
+#define mmDMA_IF_W_N_HBM1_RD_BMON_BASE             0x7FFE44A000ull
+#define DMA_IF_W_N_HBM1_RD_BMON_MAX_OFFSET         0x1000
+#define DMA_IF_W_N_HBM1_RD_BMON_SECTION            0x1000
+#define mmDMA_IF_W_N_SOB_WR_BMON_BASE              0x7FFE44B000ull
+#define DMA_IF_W_N_SOB_WR_BMON_MAX_OFFSET          0x1000
+#define DMA_IF_W_N_SOB_WR_BMON_SECTION             0x4000
+#define mmDMA_IF_W_N_FUNNEL_BASE                   0x7FFE44F000ull
+#define DMA_IF_W_N_FUNNEL_MAX_OFFSET               0x1000
+#define DMA_IF_W_N_FUNNEL_SECTION                  0x12000
+#define mmDMA_IF_E_N_STM_BASE                      0x7FFE461000ull
+#define DMA_IF_E_N_STM_MAX_OFFSET                  0x1000
+#define DMA_IF_E_N_STM_SECTION                     0x1000
+#define mmDMA_IF_E_N_CTI_BASE                      0x7FFE462000ull
+#define DMA_IF_E_N_CTI_MAX_OFFSET                  0x1000
+#define DMA_IF_E_N_CTI_SECTION                     0x1000
+#define mmDMA_IF_E_N_ETF_BASE                      0x7FFE463000ull
+#define DMA_IF_E_N_ETF_MAX_OFFSET                  0x1000
+#define DMA_IF_E_N_ETF_SECTION                     0x2000
+#define mmDMA_IF_E_N_BMON0_CTI_BASE                0x7FFE465000ull
+#define DMA_IF_E_N_BMON0_CTI_MAX_OFFSET            0x1000
+#define DMA_IF_E_N_BMON0_CTI_SECTION               0x1000
+#define mmDMA_IF_E_N_BMON1_CTI_BASE                0x7FFE466000ull
+#define DMA_IF_E_N_BMON1_CTI_MAX_OFFSET            0x1000
+#define DMA_IF_E_N_BMON1_CTI_SECTION               0x1000
+#define mmDMA_IF_E_N_HBM0_WR_BMON_BASE             0x7FFE467000ull
+#define DMA_IF_E_N_HBM0_WR_BMON_MAX_OFFSET         0x1000
+#define DMA_IF_E_N_HBM0_WR_BMON_SECTION            0x1000
+#define mmDMA_IF_E_N_HBM0_RD_BMON_BASE             0x7FFE468000ull
+#define DMA_IF_E_N_HBM0_RD_BMON_MAX_OFFSET         0x1000
+#define DMA_IF_E_N_HBM0_RD_BMON_SECTION            0x1000
+#define mmDMA_IF_E_N_HBM1_WR_BMON_BASE             0x7FFE469000ull
+#define DMA_IF_E_N_HBM1_WR_BMON_MAX_OFFSET         0x1000
+#define DMA_IF_E_N_HBM1_WR_BMON_SECTION            0x1000
+#define mmDMA_IF_E_N_HBM1_RD_BMON_BASE             0x7FFE46A000ull
+#define DMA_IF_E_N_HBM1_RD_BMON_MAX_OFFSET         0x1000
+#define DMA_IF_E_N_HBM1_RD_BMON_SECTION            0x1000
+#define mmDMA_IF_E_N_SOB_WR_BMON_BASE              0x7FFE46B000ull
+#define DMA_IF_E_N_SOB_WR_BMON_MAX_OFFSET          0x1000
+#define DMA_IF_E_N_SOB_WR_BMON_SECTION             0x4000
+#define mmDMA_IF_E_N_FUNNEL_BASE                   0x7FFE46F000ull
+#define DMA_IF_E_N_FUNNEL_MAX_OFFSET               0x1000
+#define DMA_IF_E_N_FUNNEL_SECTION                  0x11000
+#define mmCPU_ROM_TABLE_BASE                       0x7FFE480000ull
+#define CPU_ROM_TABLE_MAX_OFFSET                   0x1000
+#define CPU_ROM_TABLE_SECTION                      0x1000
+#define mmCPU_ETF_0_BASE                           0x7FFE481000ull
+#define CPU_ETF_0_MAX_OFFSET                       0x1000
+#define CPU_ETF_0_SECTION                          0x1000
+#define mmCPU_ETF_1_BASE                           0x7FFE482000ull
+#define CPU_ETF_1_MAX_OFFSET                       0x1000
+#define CPU_ETF_1_SECTION                          0x2000
+#define mmCPU_CTI_BASE                             0x7FFE484000ull
+#define CPU_CTI_MAX_OFFSET                         0x1000
+#define CPU_CTI_SECTION                            0x1000
+#define mmCPU_FUNNEL_BASE                          0x7FFE485000ull
+#define CPU_FUNNEL_MAX_OFFSET                      0x1000
+#define CPU_FUNNEL_SECTION                         0x1000
+#define mmCPU_STM_BASE                             0x7FFE486000ull
+#define CPU_STM_MAX_OFFSET                         0x1000
+#define CPU_STM_SECTION                            0x1000
+#define mmCPU_CTI_TRACE_BASE                       0x7FFE487000ull
+#define CPU_CTI_TRACE_MAX_OFFSET                   0x1000
+#define CPU_CTI_TRACE_SECTION                      0x1000
+#define mmCPU_ETF_TRACE_BASE                       0x7FFE488000ull
+#define CPU_ETF_TRACE_MAX_OFFSET                   0x1000
+#define CPU_ETF_TRACE_SECTION                      0x1000
+#define mmCPU_WR_BMON_BASE                         0x7FFE489000ull
+#define CPU_WR_BMON_MAX_OFFSET                     0x1000
+#define CPU_WR_BMON_SECTION                        0x1000
+#define mmCPU_RD_BMON_BASE                         0x7FFE48A000ull
+#define CPU_RD_BMON_MAX_OFFSET                     0x1000
+#define CPU_RD_BMON_SECTION                        0x76000
+#define mmDMA_ROM_TABLE_BASE                       0x7FFE500000ull
+#define DMA_ROM_TABLE_MAX_OFFSET                   0x1000
+#define DMA_ROM_TABLE_SECTION                      0x1000
+#define mmDMA_CH_0_CS_STM_BASE                     0x7FFE501000ull
+#define DMA_CH_0_CS_STM_MAX_OFFSET                 0x1000
+#define DMA_CH_0_CS_STM_SECTION                    0x1000
+#define mmDMA_CH_0_CS_CTI_BASE                     0x7FFE502000ull
+#define DMA_CH_0_CS_CTI_MAX_OFFSET                 0x1000
+#define DMA_CH_0_CS_CTI_SECTION                    0x1000
+#define mmDMA_CH_0_CS_ETF_BASE                     0x7FFE503000ull
+#define DMA_CH_0_CS_ETF_MAX_OFFSET                 0x1000
+#define DMA_CH_0_CS_ETF_SECTION                    0x1000
+#define mmDMA_CH_0_CS_SPMU_BASE                    0x7FFE504000ull
+#define DMA_CH_0_CS_SPMU_MAX_OFFSET                0x1000
+#define DMA_CH_0_CS_SPMU_SECTION                   0x1000
+#define mmDMA_CH_0_BMON_CTI_BASE                   0x7FFE505000ull
+#define DMA_CH_0_BMON_CTI_MAX_OFFSET               0x1000
+#define DMA_CH_0_BMON_CTI_SECTION                  0x1000
+#define mmDMA_CH_0_USER_CTI_BASE                   0x7FFE506000ull
+#define DMA_CH_0_USER_CTI_MAX_OFFSET               0x1000
+#define DMA_CH_0_USER_CTI_SECTION                  0x1000
+#define mmDMA_CH_0_BMON_0_BASE                     0x7FFE507000ull
+#define DMA_CH_0_BMON_0_MAX_OFFSET                 0x1000
+#define DMA_CH_0_BMON_0_SECTION                    0x1000
+#define mmDMA_CH_0_BMON_1_BASE                     0x7FFE508000ull
+#define DMA_CH_0_BMON_1_MAX_OFFSET                 0x1000
+#define DMA_CH_0_BMON_1_SECTION                    0x19000
+#define mmDMA_CH_1_CS_STM_BASE                     0x7FFE521000ull
+#define DMA_CH_1_CS_STM_MAX_OFFSET                 0x1000
+#define DMA_CH_1_CS_STM_SECTION                    0x1000
+#define mmDMA_CH_1_CS_CTI_BASE                     0x7FFE522000ull
+#define DMA_CH_1_CS_CTI_MAX_OFFSET                 0x1000
+#define DMA_CH_1_CS_CTI_SECTION                    0x1000
+#define mmDMA_CH_1_CS_ETF_BASE                     0x7FFE523000ull
+#define DMA_CH_1_CS_ETF_MAX_OFFSET                 0x1000
+#define DMA_CH_1_CS_ETF_SECTION                    0x1000
+#define mmDMA_CH_1_CS_SPMU_BASE                    0x7FFE524000ull
+#define DMA_CH_1_CS_SPMU_MAX_OFFSET                0x1000
+#define DMA_CH_1_CS_SPMU_SECTION                   0x1000
+#define mmDMA_CH_1_BMON_CTI_BASE                   0x7FFE525000ull
+#define DMA_CH_1_BMON_CTI_MAX_OFFSET               0x1000
+#define DMA_CH_1_BMON_CTI_SECTION                  0x1000
+#define mmDMA_CH_1_USER_CTI_BASE                   0x7FFE526000ull
+#define DMA_CH_1_USER_CTI_MAX_OFFSET               0x1000
+#define DMA_CH_1_USER_CTI_SECTION                  0x1000
+#define mmDMA_CH_1_BMON_0_BASE                     0x7FFE527000ull
+#define DMA_CH_1_BMON_0_MAX_OFFSET                 0x1000
+#define DMA_CH_1_BMON_0_SECTION                    0x1000
+#define mmDMA_CH_1_BMON_1_BASE                     0x7FFE528000ull
+#define DMA_CH_1_BMON_1_MAX_OFFSET                 0x1000
+#define DMA_CH_1_BMON_1_SECTION                    0x19000
+#define mmDMA_CH_2_CS_STM_BASE                     0x7FFE541000ull
+#define DMA_CH_2_CS_STM_MAX_OFFSET                 0x1000
+#define DMA_CH_2_CS_STM_SECTION                    0x1000
+#define mmDMA_CH_2_CS_CTI_BASE                     0x7FFE542000ull
+#define DMA_CH_2_CS_CTI_MAX_OFFSET                 0x1000
+#define DMA_CH_2_CS_CTI_SECTION                    0x1000
+#define mmDMA_CH_2_CS_ETF_BASE                     0x7FFE543000ull
+#define DMA_CH_2_CS_ETF_MAX_OFFSET                 0x1000
+#define DMA_CH_2_CS_ETF_SECTION                    0x1000
+#define mmDMA_CH_2_CS_SPMU_BASE                    0x7FFE544000ull
+#define DMA_CH_2_CS_SPMU_MAX_OFFSET                0x1000
+#define DMA_CH_2_CS_SPMU_SECTION                   0x1000
+#define mmDMA_CH_2_BMON_CTI_BASE                   0x7FFE545000ull
+#define DMA_CH_2_BMON_CTI_MAX_OFFSET               0x1000
+#define DMA_CH_2_BMON_CTI_SECTION                  0x1000
+#define mmDMA_CH_2_USER_CTI_BASE                   0x7FFE546000ull
+#define DMA_CH_2_USER_CTI_MAX_OFFSET               0x1000
+#define DMA_CH_2_USER_CTI_SECTION                  0x1000
+#define mmDMA_CH_2_BMON_0_BASE                     0x7FFE547000ull
+#define DMA_CH_2_BMON_0_MAX_OFFSET                 0x1000
+#define DMA_CH_2_BMON_0_SECTION                    0x1000
+#define mmDMA_CH_2_BMON_1_BASE                     0x7FFE548000ull
+#define DMA_CH_2_BMON_1_MAX_OFFSET                 0x1000
+#define DMA_CH_2_BMON_1_SECTION                    0x19000
+#define mmDMA_CH_3_CS_STM_BASE                     0x7FFE561000ull
+#define DMA_CH_3_CS_STM_MAX_OFFSET                 0x1000
+#define DMA_CH_3_CS_STM_SECTION                    0x1000
+#define mmDMA_CH_3_CS_CTI_BASE                     0x7FFE562000ull
+#define DMA_CH_3_CS_CTI_MAX_OFFSET                 0x1000
+#define DMA_CH_3_CS_CTI_SECTION                    0x1000
+#define mmDMA_CH_3_CS_ETF_BASE                     0x7FFE563000ull
+#define DMA_CH_3_CS_ETF_MAX_OFFSET                 0x1000
+#define DMA_CH_3_CS_ETF_SECTION                    0x1000
+#define mmDMA_CH_3_CS_SPMU_BASE                    0x7FFE564000ull
+#define DMA_CH_3_CS_SPMU_MAX_OFFSET                0x1000
+#define DMA_CH_3_CS_SPMU_SECTION                   0x1000
+#define mmDMA_CH_3_BMON_CTI_BASE                   0x7FFE565000ull
+#define DMA_CH_3_BMON_CTI_MAX_OFFSET               0x1000
+#define DMA_CH_3_BMON_CTI_SECTION                  0x1000
+#define mmDMA_CH_3_USER_CTI_BASE                   0x7FFE566000ull
+#define DMA_CH_3_USER_CTI_MAX_OFFSET               0x1000
+#define DMA_CH_3_USER_CTI_SECTION                  0x1000
+#define mmDMA_CH_3_BMON_0_BASE                     0x7FFE567000ull
+#define DMA_CH_3_BMON_0_MAX_OFFSET                 0x1000
+#define DMA_CH_3_BMON_0_SECTION                    0x1000
+#define mmDMA_CH_3_BMON_1_BASE                     0x7FFE568000ull
+#define DMA_CH_3_BMON_1_MAX_OFFSET                 0x1000
+#define DMA_CH_3_BMON_1_SECTION                    0x19000
+#define mmDMA_CH_4_CS_STM_BASE                     0x7FFE581000ull
+#define DMA_CH_4_CS_STM_MAX_OFFSET                 0x1000
+#define DMA_CH_4_CS_STM_SECTION                    0x1000
+#define mmDMA_CH_4_CS_CTI_BASE                     0x7FFE582000ull
+#define DMA_CH_4_CS_CTI_MAX_OFFSET                 0x1000
+#define DMA_CH_4_CS_CTI_SECTION                    0x1000
+#define mmDMA_CH_4_CS_ETF_BASE                     0x7FFE583000ull
+#define DMA_CH_4_CS_ETF_MAX_OFFSET                 0x1000
+#define DMA_CH_4_CS_ETF_SECTION                    0x1000
+#define mmDMA_CH_4_CS_SPMU_BASE                    0x7FFE584000ull
+#define DMA_CH_4_CS_SPMU_MAX_OFFSET                0x1000
+#define DMA_CH_4_CS_SPMU_SECTION                   0x1000
+#define mmDMA_CH_4_BMON_CTI_BASE                   0x7FFE585000ull
+#define DMA_CH_4_BMON_CTI_MAX_OFFSET               0x1000
+#define DMA_CH_4_BMON_CTI_SECTION                  0x1000
+#define mmDMA_CH_4_USER_CTI_BASE                   0x7FFE586000ull
+#define DMA_CH_4_USER_CTI_MAX_OFFSET               0x1000
+#define DMA_CH_4_USER_CTI_SECTION                  0x1000
+#define mmDMA_CH_4_BMON_0_BASE                     0x7FFE587000ull
+#define DMA_CH_4_BMON_0_MAX_OFFSET                 0x1000
+#define DMA_CH_4_BMON_0_SECTION                    0x1000
+#define mmDMA_CH_4_BMON_1_BASE                     0x7FFE588000ull
+#define DMA_CH_4_BMON_1_MAX_OFFSET                 0x1000
+#define DMA_CH_4_BMON_1_SECTION                    0x19000
+#define mmDMA_CH_5_CS_STM_BASE                     0x7FFE5A1000ull
+#define DMA_CH_5_CS_STM_MAX_OFFSET                 0x1000
+#define DMA_CH_5_CS_STM_SECTION                    0x1000
+#define mmDMA_CH_5_CS_CTI_BASE                     0x7FFE5A2000ull
+#define DMA_CH_5_CS_CTI_MAX_OFFSET                 0x1000
+#define DMA_CH_5_CS_CTI_SECTION                    0x1000
+#define mmDMA_CH_5_CS_ETF_BASE                     0x7FFE5A3000ull
+#define DMA_CH_5_CS_ETF_MAX_OFFSET                 0x1000
+#define DMA_CH_5_CS_ETF_SECTION                    0x1000
+#define mmDMA_CH_5_CS_SPMU_BASE                    0x7FFE5A4000ull
+#define DMA_CH_5_CS_SPMU_MAX_OFFSET                0x1000
+#define DMA_CH_5_CS_SPMU_SECTION                   0x1000
+#define mmDMA_CH_5_BMON_CTI_BASE                   0x7FFE5A5000ull
+#define DMA_CH_5_BMON_CTI_MAX_OFFSET               0x1000
+#define DMA_CH_5_BMON_CTI_SECTION                  0x1000
+#define mmDMA_CH_5_USER_CTI_BASE                   0x7FFE5A6000ull
+#define DMA_CH_5_USER_CTI_MAX_OFFSET               0x1000
+#define DMA_CH_5_USER_CTI_SECTION                  0x1000
+#define mmDMA_CH_5_BMON_0_BASE                     0x7FFE5A7000ull
+#define DMA_CH_5_BMON_0_MAX_OFFSET                 0x1000
+#define DMA_CH_5_BMON_0_SECTION                    0x1000
+#define mmDMA_CH_5_BMON_1_BASE                     0x7FFE5A8000ull
+#define DMA_CH_5_BMON_1_MAX_OFFSET                 0x1000
+#define DMA_CH_5_BMON_1_SECTION                    0x19000
+#define mmDMA_CH_6_CS_STM_BASE                     0x7FFE5C1000ull
+#define DMA_CH_6_CS_STM_MAX_OFFSET                 0x1000
+#define DMA_CH_6_CS_STM_SECTION                    0x1000
+#define mmDMA_CH_6_CS_CTI_BASE                     0x7FFE5C2000ull
+#define DMA_CH_6_CS_CTI_MAX_OFFSET                 0x1000
+#define DMA_CH_6_CS_CTI_SECTION                    0x1000
+#define mmDMA_CH_6_CS_ETF_BASE                     0x7FFE5C3000ull
+#define DMA_CH_6_CS_ETF_MAX_OFFSET                 0x1000
+#define DMA_CH_6_CS_ETF_SECTION                    0x1000
+#define mmDMA_CH_6_CS_SPMU_BASE                    0x7FFE5C4000ull
+#define DMA_CH_6_CS_SPMU_MAX_OFFSET                0x1000
+#define DMA_CH_6_CS_SPMU_SECTION                   0x1000
+#define mmDMA_CH_6_BMON_CTI_BASE                   0x7FFE5C5000ull
+#define DMA_CH_6_BMON_CTI_MAX_OFFSET               0x1000
+#define DMA_CH_6_BMON_CTI_SECTION                  0x1000
+#define mmDMA_CH_6_USER_CTI_BASE                   0x7FFE5C6000ull
+#define DMA_CH_6_USER_CTI_MAX_OFFSET               0x1000
+#define DMA_CH_6_USER_CTI_SECTION                  0x1000
+#define mmDMA_CH_6_BMON_0_BASE                     0x7FFE5C7000ull
+#define DMA_CH_6_BMON_0_MAX_OFFSET                 0x1000
+#define DMA_CH_6_BMON_0_SECTION                    0x1000
+#define mmDMA_CH_6_BMON_1_BASE                     0x7FFE5C8000ull
+#define DMA_CH_6_BMON_1_MAX_OFFSET                 0x1000
+#define DMA_CH_6_BMON_1_SECTION                    0x19000
+#define mmDMA_CH_7_CS_STM_BASE                     0x7FFE5E1000ull
+#define DMA_CH_7_CS_STM_MAX_OFFSET                 0x1000
+#define DMA_CH_7_CS_STM_SECTION                    0x1000
+#define mmDMA_CH_7_CS_CTI_BASE                     0x7FFE5E2000ull
+#define DMA_CH_7_CS_CTI_MAX_OFFSET                 0x1000
+#define DMA_CH_7_CS_CTI_SECTION                    0x1000
+#define mmDMA_CH_7_CS_ETF_BASE                     0x7FFE5E3000ull
+#define DMA_CH_7_CS_ETF_MAX_OFFSET                 0x1000
+#define DMA_CH_7_CS_ETF_SECTION                    0x1000
+#define mmDMA_CH_7_CS_SPMU_BASE                    0x7FFE5E4000ull
+#define DMA_CH_7_CS_SPMU_MAX_OFFSET                0x1000
+#define DMA_CH_7_CS_SPMU_SECTION                   0x1000
+#define mmDMA_CH_7_BMON_CTI_BASE                   0x7FFE5E5000ull
+#define DMA_CH_7_BMON_CTI_MAX_OFFSET               0x1000
+#define DMA_CH_7_BMON_CTI_SECTION                  0x1000
+#define mmDMA_CH_7_USER_CTI_BASE                   0x7FFE5E6000ull
+#define DMA_CH_7_USER_CTI_MAX_OFFSET               0x1000
+#define DMA_CH_7_USER_CTI_SECTION                  0x1000
+#define mmDMA_CH_7_BMON_0_BASE                     0x7FFE5E7000ull
+#define DMA_CH_7_BMON_0_MAX_OFFSET                 0x1000
+#define DMA_CH_7_BMON_0_SECTION                    0x1000
+#define mmDMA_CH_7_BMON_1_BASE                     0x7FFE5E8000ull
+#define DMA_CH_7_BMON_1_MAX_OFFSET                 0x1000
+#define DMA_CH_7_BMON_1_SECTION                    0x18000
+#define mmNIC_TPC_FUNNEL_W_S_BASE                  0x7FFE600000ull
+#define NIC_TPC_FUNNEL_W_S_MAX_OFFSET              0x1000
+#define NIC_TPC_FUNNEL_W_S_SECTION                 0x80000
+#define mmNIC_TPC_FUNNEL_E_S_BASE                  0x7FFE680000ull
+#define NIC_TPC_FUNNEL_E_S_MAX_OFFSET              0x1000
+#define NIC_TPC_FUNNEL_E_S_SECTION                 0x80000
+#define mmNIC_TPC_FUNNEL_W_N_BASE                  0x7FFE700000ull
+#define NIC_TPC_FUNNEL_W_N_MAX_OFFSET              0x1000
+#define NIC_TPC_FUNNEL_W_N_SECTION                 0x80000
+#define mmNIC_TPC_FUNNEL_E_N_BASE                  0x7FFE780000ull
+#define NIC_TPC_FUNNEL_E_N_MAX_OFFSET              0x1000
+#define NIC_TPC_FUNNEL_E_N_SECTION                 0x80000
+#define mmCA53_BASE                                0x7FFE800000ull
+#define CA53_MAX_OFFSET                            0x141000
+#define CA53_SECTION                               0x400000
+#define mmPCI_ROM_TABLE_BASE                       0x7FFEC00000ull
+#define PCI_ROM_TABLE_MAX_OFFSET                   0x1000
+#define PCI_ROM_TABLE_SECTION                      0x1000
+#define mmPCIE_STM_BASE                            0x7FFEC01000ull
+#define PCIE_STM_MAX_OFFSET                        0x1000
+#define PCIE_STM_SECTION                           0x1000
+#define mmPCIE_ETF_BASE                            0x7FFEC02000ull
+#define PCIE_ETF_MAX_OFFSET                        0x1000
+#define PCIE_ETF_SECTION                           0x1000
+#define mmPCIE_CTI_0_BASE                          0x7FFEC03000ull
+#define PCIE_CTI_0_MAX_OFFSET                      0x1000
+#define PCIE_CTI_0_SECTION                         0x1000
+#define mmPCIE_SPMU_BASE                           0x7FFEC04000ull
+#define PCIE_SPMU_MAX_OFFSET                       0x1000
+#define PCIE_SPMU_SECTION                          0x1000
+#define mmPCIE_CTI_1_BASE                          0x7FFEC05000ull
+#define PCIE_CTI_1_MAX_OFFSET                      0x1000
+#define PCIE_CTI_1_SECTION                         0x1000
+#define mmPCIE_FUNNEL_BASE                         0x7FFEC06000ull
+#define PCIE_FUNNEL_MAX_OFFSET                     0x1000
+#define PCIE_FUNNEL_SECTION                        0x1000
+#define mmPCIE_BMON_MSTR_WR_BASE                   0x7FFEC07000ull
+#define PCIE_BMON_MSTR_WR_MAX_OFFSET               0x1000
+#define PCIE_BMON_MSTR_WR_SECTION                  0x1000
+#define mmPCIE_BMON_MSTR_RD_BASE                   0x7FFEC08000ull
+#define PCIE_BMON_MSTR_RD_MAX_OFFSET               0x1000
+#define PCIE_BMON_MSTR_RD_SECTION                  0x1000
+#define mmPCIE_BMON_SLV_WR_BASE                    0x7FFEC09000ull
+#define PCIE_BMON_SLV_WR_MAX_OFFSET                0x1000
+#define PCIE_BMON_SLV_WR_SECTION                   0x1000
+#define mmPCIE_BMON_SLV_RD_BASE                    0x7FFEC0A000ull
+#define PCIE_BMON_SLV_RD_MAX_OFFSET                0x1000
+#define PCIE_BMON_SLV_RD_SECTION                   0x7000
+#define mmMMU_CS_STM_BASE                          0x7FFEC11000ull
+#define MMU_CS_STM_MAX_OFFSET                      0x1000
+#define MMU_CS_STM_SECTION                         0x1000
+#define mmMMU_CS_CTI_BASE                          0x7FFEC12000ull
+#define MMU_CS_CTI_MAX_OFFSET                      0x1000
+#define MMU_CS_CTI_SECTION                         0x1000
+#define mmMMU_CS_ETF_BASE                          0x7FFEC13000ull
+#define MMU_CS_ETF_MAX_OFFSET                      0x1000
+#define MMU_CS_ETF_SECTION                         0x1000
+#define mmMMU_CS_SPMU_BASE                         0x7FFEC14000ull
+#define MMU_CS_SPMU_MAX_OFFSET                     0x1000
+#define MMU_CS_SPMU_SECTION                        0x1000
+#define mmMMU_BMON_CTI_BASE                        0x7FFEC15000ull
+#define MMU_BMON_CTI_MAX_OFFSET                    0x1000
+#define MMU_BMON_CTI_SECTION                       0x1000
+#define mmMMU_USER_CTI_BASE                        0x7FFEC16000ull
+#define MMU_USER_CTI_MAX_OFFSET                    0x1000
+#define MMU_USER_CTI_SECTION                       0x1000
+#define mmMMU_BMON_0_BASE                          0x7FFEC17000ull
+#define MMU_BMON_0_MAX_OFFSET                      0x1000
+#define MMU_BMON_0_SECTION                         0x1000
+#define mmMMU_BMON_1_BASE                          0x7FFEC18000ull
+#define MMU_BMON_1_MAX_OFFSET                      0x1000
+#define MMU_BMON_1_SECTION                         0x28000
+#define mmPSOC_CTI_BASE                            0x7FFEC40000ull
+#define PSOC_CTI_MAX_OFFSET                        0x1000
+#define PSOC_CTI_SECTION                           0x1000
+#define mmPSOC_STM_BASE                            0x7FFEC41000ull
+#define PSOC_STM_MAX_OFFSET                        0x1000
+#define PSOC_STM_SECTION                           0x1000
+#define mmPSOC_FUNNEL_BASE                         0x7FFEC42000ull
+#define PSOC_FUNNEL_MAX_OFFSET                     0x1000
+#define PSOC_FUNNEL_SECTION                        0x1000
+#define mmPSOC_ETR_BASE                            0x7FFEC43000ull
+#define PSOC_ETR_MAX_OFFSET                        0x1000
+#define PSOC_ETR_SECTION                           0x1000
+#define mmPSOC_ETF_BASE                            0x7FFEC44000ull
+#define PSOC_ETF_MAX_OFFSET                        0x1000
+#define PSOC_ETF_SECTION                           0x1000
+#define mmPSOC_TS_CTI_BASE                         0x7FFEC45000ull
+#define PSOC_TS_CTI_MAX_OFFSET                     0x1000
+#define PSOC_TS_CTI_SECTION                        0xB000
+#define mmTOP_ROM_TABLE_BASE                       0x7FFEC50000ull
+#define TOP_ROM_TABLE_MAX_OFFSET                   0x1000
+#define TOP_ROM_TABLE_SECTION                      0x70000
+#define mmNIC0_ROM_TABLE_BASE                      0x7FFECC0000ull
+#define NIC0_ROM_TABLE_MAX_OFFSET                  0x1000
+#define NIC0_ROM_TABLE_SECTION                     0x1000
+#define mmSTM_0_NIC0_DBG_BASE                      0x7FFECC1000ull
+#define STM_0_NIC0_DBG_MAX_OFFSET                  0x21000
+#define STM_0_NIC0_DBG_SECTION                     0x1000
+#define mmCTI_0_NIC0_DBG_BASE                      0x7FFECC2000ull
+#define CTI_0_NIC0_DBG_MAX_OFFSET                  0x1000
+#define CTI_0_NIC0_DBG_SECTION                     0x1000
+#define mmETF_0_NIC0_DBG_BASE                      0x7FFECC3000ull
+#define ETF_0_NIC0_DBG_MAX_OFFSET                  0x1000
+#define ETF_0_NIC0_DBG_SECTION                     0x1000
+#define mmSPMU_0_NIC0_DBG_BASE                     0x7FFECC4000ull
+#define SPMU_0_NIC0_DBG_MAX_OFFSET                 0x1000
+#define SPMU_0_NIC0_DBG_SECTION                    0x2000
+#define mmUSER_CTI_0_NIC0_DBG_BASE                 0x7FFECC6000ull
+#define USER_CTI_0_NIC0_DBG_MAX_OFFSET             0x1000
+#define USER_CTI_0_NIC0_DBG_SECTION                0xB000
+#define mmSTM_1_NIC0_DBG_BASE                      0x7FFECD1000ull
+#define STM_1_NIC0_DBG_MAX_OFFSET                  0x1000
+#define STM_1_NIC0_DBG_SECTION                     0x1000
+#define mmCTI_1_NIC0_DBG_BASE                      0x7FFECD2000ull
+#define CTI_1_NIC0_DBG_MAX_OFFSET                  0x1000
+#define CTI_1_NIC0_DBG_SECTION                     0x1000
+#define mmETF_1_NIC0_DBG_BASE                      0x7FFECD3000ull
+#define ETF_1_NIC0_DBG_MAX_OFFSET                  0x1000
+#define ETF_1_NIC0_DBG_SECTION                     0x1000
+#define mmSPMU_1_NIC0_DBG_BASE                     0x7FFECD4000ull
+#define SPMU_1_NIC0_DBG_MAX_OFFSET                 0x1000
+#define SPMU_1_NIC0_DBG_SECTION                    0x1000
+#define mmBMON_CTI_NIC0_DBG_BASE                   0x7FFECD5000ull
+#define BMON_CTI_NIC0_DBG_MAX_OFFSET               0x1000
+#define BMON_CTI_NIC0_DBG_SECTION                  0x1000
+#define mmUSER_CTI_1_NIC0_DBG_BASE                 0x7FFECD6000ull
+#define USER_CTI_1_NIC0_DBG_MAX_OFFSET             0x1000
+#define USER_CTI_1_NIC0_DBG_SECTION                0x1000
+#define mmBMON0_NIC0_DBG_BASE                      0x7FFECD7000ull
+#define BMON0_NIC0_DBG_MAX_OFFSET                  0x1000
+#define BMON0_NIC0_DBG_SECTION                     0x1000
+#define mmBMON1_NIC0_DBG_BASE                      0x7FFECD8000ull
+#define BMON1_NIC0_DBG_MAX_OFFSET                  0x1000
+#define BMON1_NIC0_DBG_SECTION                     0x1000
+#define mmBMON2_NIC0_DBG_BASE                      0x7FFECD9000ull
+#define BMON2_NIC0_DBG_MAX_OFFSET                  0x1000
+#define BMON2_NIC0_DBG_SECTION                     0x1000
+#define mmBMON3_NIC0_DBG_BASE                      0x7FFECDA000ull
+#define BMON3_NIC0_DBG_MAX_OFFSET                  0x1000
+#define BMON3_NIC0_DBG_SECTION                     0x1000
+#define mmBMON4_NIC0_DBG_BASE                      0x7FFECDB000ull
+#define BMON4_NIC0_DBG_MAX_OFFSET                  0x1000
+#define BMON4_NIC0_DBG_SECTION                     0x6000
+#define mmFUNNEL_NIC0_DBG_BASE                     0x7FFECE1000ull
+#define FUNNEL_NIC0_DBG_MAX_OFFSET                 0x1000
+#define FUNNEL_NIC0_DBG_SECTION                    0x1F000
+#define mmNIC1_ROM_TABLE_BASE                      0x7FFED00000ull
+#define NIC1_ROM_TABLE_MAX_OFFSET                  0x1000
+#define NIC1_ROM_TABLE_SECTION                     0x1000
+#define mmSTM_0_NIC1_DBG_BASE                      0x7FFED01000ull
+#define STM_0_NIC1_DBG_MAX_OFFSET                  0x21000
+#define STM_0_NIC1_DBG_SECTION                     0x1000
+#define mmCTI_0_NIC1_DBG_BASE                      0x7FFED02000ull
+#define CTI_0_NIC1_DBG_MAX_OFFSET                  0x1000
+#define CTI_0_NIC1_DBG_SECTION                     0x1000
+#define mmETF_0_NIC1_DBG_BASE                      0x7FFED03000ull
+#define ETF_0_NIC1_DBG_MAX_OFFSET                  0x1000
+#define ETF_0_NIC1_DBG_SECTION                     0x1000
+#define mmSPMU_0_NIC1_DBG_BASE                     0x7FFED04000ull
+#define SPMU_0_NIC1_DBG_MAX_OFFSET                 0x1000
+#define SPMU_0_NIC1_DBG_SECTION                    0x2000
+#define mmUSER_CTI_0_NIC1_DBG_BASE                 0x7FFED06000ull
+#define USER_CTI_0_NIC1_DBG_MAX_OFFSET             0x1000
+#define USER_CTI_0_NIC1_DBG_SECTION                0xB000
+#define mmSTM_1_NIC1_DBG_BASE                      0x7FFED11000ull
+#define STM_1_NIC1_DBG_MAX_OFFSET                  0x1000
+#define STM_1_NIC1_DBG_SECTION                     0x1000
+#define mmCTI_1_NIC1_DBG_BASE                      0x7FFED12000ull
+#define CTI_1_NIC1_DBG_MAX_OFFSET                  0x1000
+#define CTI_1_NIC1_DBG_SECTION                     0x1000
+#define mmETF_1_NIC1_DBG_BASE                      0x7FFED13000ull
+#define ETF_1_NIC1_DBG_MAX_OFFSET                  0x1000
+#define ETF_1_NIC1_DBG_SECTION                     0x1000
+#define mmSPMU_1_NIC1_DBG_BASE                     0x7FFED14000ull
+#define SPMU_1_NIC1_DBG_MAX_OFFSET                 0x1000
+#define SPMU_1_NIC1_DBG_SECTION                    0x1000
+#define mmBMON_CTI_NIC1_DBG_BASE                   0x7FFED15000ull
+#define BMON_CTI_NIC1_DBG_MAX_OFFSET               0x1000
+#define BMON_CTI_NIC1_DBG_SECTION                  0x1000
+#define mmUSER_CTI_1_NIC1_DBG_BASE                 0x7FFED16000ull
+#define USER_CTI_1_NIC1_DBG_MAX_OFFSET             0x1000
+#define USER_CTI_1_NIC1_DBG_SECTION                0x1000
+#define mmBMON0_NIC1_DBG_BASE                      0x7FFED17000ull
+#define BMON0_NIC1_DBG_MAX_OFFSET                  0x1000
+#define BMON0_NIC1_DBG_SECTION                     0x1000
+#define mmBMON1_NIC1_DBG_BASE                      0x7FFED18000ull
+#define BMON1_NIC1_DBG_MAX_OFFSET                  0x1000
+#define BMON1_NIC1_DBG_SECTION                     0x1000
+#define mmBMON2_NIC1_DBG_BASE                      0x7FFED19000ull
+#define BMON2_NIC1_DBG_MAX_OFFSET                  0x1000
+#define BMON2_NIC1_DBG_SECTION                     0x1000
+#define mmBMON3_NIC1_DBG_BASE                      0x7FFED1A000ull
+#define BMON3_NIC1_DBG_MAX_OFFSET                  0x1000
+#define BMON3_NIC1_DBG_SECTION                     0x1000
+#define mmBMON4_NIC1_DBG_BASE                      0x7FFED1B000ull
+#define BMON4_NIC1_DBG_MAX_OFFSET                  0x1000
+#define BMON4_NIC1_DBG_SECTION                     0x6000
+#define mmFUNNEL_NIC1_DBG_BASE                     0x7FFED21000ull
+#define FUNNEL_NIC1_DBG_MAX_OFFSET                 0x1000
+#define FUNNEL_NIC1_DBG_SECTION                    0x1F000
+#define mmNIC2_ROM_TABLE_BASE                      0x7FFED40000ull
+#define NIC2_ROM_TABLE_MAX_OFFSET                  0x1000
+#define NIC2_ROM_TABLE_SECTION                     0x1000
+#define mmSTM_0_NIC2_DBG_BASE                      0x7FFED41000ull
+#define STM_0_NIC2_DBG_MAX_OFFSET                  0x21000
+#define STM_0_NIC2_DBG_SECTION                     0x1000
+#define mmCTI_0_NIC2_DBG_BASE                      0x7FFED42000ull
+#define CTI_0_NIC2_DBG_MAX_OFFSET                  0x1000
+#define CTI_0_NIC2_DBG_SECTION                     0x1000
+#define mmETF_0_NIC2_DBG_BASE                      0x7FFED43000ull
+#define ETF_0_NIC2_DBG_MAX_OFFSET                  0x1000
+#define ETF_0_NIC2_DBG_SECTION                     0x1000
+#define mmSPMU_0_NIC2_DBG_BASE                     0x7FFED44000ull
+#define SPMU_0_NIC2_DBG_MAX_OFFSET                 0x1000
+#define SPMU_0_NIC2_DBG_SECTION                    0x2000
+#define mmUSER_CTI_0_NIC2_DBG_BASE                 0x7FFED46000ull
+#define USER_CTI_0_NIC2_DBG_MAX_OFFSET             0x1000
+#define USER_CTI_0_NIC2_DBG_SECTION                0xB000
+#define mmSTM_1_NIC2_DBG_BASE                      0x7FFED51000ull
+#define STM_1_NIC2_DBG_MAX_OFFSET                  0x1000
+#define STM_1_NIC2_DBG_SECTION                     0x1000
+#define mmCTI_1_NIC2_DBG_BASE                      0x7FFED52000ull
+#define CTI_1_NIC2_DBG_MAX_OFFSET                  0x1000
+#define CTI_1_NIC2_DBG_SECTION                     0x1000
+#define mmETF_1_NIC2_DBG_BASE                      0x7FFED53000ull
+#define ETF_1_NIC2_DBG_MAX_OFFSET                  0x1000
+#define ETF_1_NIC2_DBG_SECTION                     0x1000
+#define mmSPMU_1_NIC2_DBG_BASE                     0x7FFED54000ull
+#define SPMU_1_NIC2_DBG_MAX_OFFSET                 0x1000
+#define SPMU_1_NIC2_DBG_SECTION                    0x1000
+#define mmBMON_CTI_NIC2_DBG_BASE                   0x7FFED55000ull
+#define BMON_CTI_NIC2_DBG_MAX_OFFSET               0x1000
+#define BMON_CTI_NIC2_DBG_SECTION                  0x1000
+#define mmUSER_CTI_1_NIC2_DBG_BASE                 0x7FFED56000ull
+#define USER_CTI_1_NIC2_DBG_MAX_OFFSET             0x1000
+#define USER_CTI_1_NIC2_DBG_SECTION                0x1000
+#define mmBMON0_NIC2_DBG_BASE                      0x7FFED57000ull
+#define BMON0_NIC2_DBG_MAX_OFFSET                  0x1000
+#define BMON0_NIC2_DBG_SECTION                     0x1000
+#define mmBMON1_NIC2_DBG_BASE                      0x7FFED58000ull
+#define BMON1_NIC2_DBG_MAX_OFFSET                  0x1000
+#define BMON1_NIC2_DBG_SECTION                     0x1000
+#define mmBMON2_NIC2_DBG_BASE                      0x7FFED59000ull
+#define BMON2_NIC2_DBG_MAX_OFFSET                  0x1000
+#define BMON2_NIC2_DBG_SECTION                     0x1000
+#define mmBMON3_NIC2_DBG_BASE                      0x7FFED5A000ull
+#define BMON3_NIC2_DBG_MAX_OFFSET                  0x1000
+#define BMON3_NIC2_DBG_SECTION                     0x1000
+#define mmBMON4_NIC2_DBG_BASE                      0x7FFED5B000ull
+#define BMON4_NIC2_DBG_MAX_OFFSET                  0x1000
+#define BMON4_NIC2_DBG_SECTION                     0x6000
+#define mmFUNNEL_NIC2_DBG_BASE                     0x7FFED61000ull
+#define FUNNEL_NIC2_DBG_MAX_OFFSET                 0x1000
+#define FUNNEL_NIC2_DBG_SECTION                    0x1F000
+#define mmNIC3_ROM_TABLE_BASE                      0x7FFED80000ull
+#define NIC3_ROM_TABLE_MAX_OFFSET                  0x1000
+#define NIC3_ROM_TABLE_SECTION                     0x1000
+#define mmSTM_0_NIC3_DBG_BASE                      0x7FFED81000ull
+#define STM_0_NIC3_DBG_MAX_OFFSET                  0x21000
+#define STM_0_NIC3_DBG_SECTION                     0x1000
+#define mmCTI_0_NIC3_DBG_BASE                      0x7FFED82000ull
+#define CTI_0_NIC3_DBG_MAX_OFFSET                  0x1000
+#define CTI_0_NIC3_DBG_SECTION                     0x1000
+#define mmETF_0_NIC3_DBG_BASE                      0x7FFED83000ull
+#define ETF_0_NIC3_DBG_MAX_OFFSET                  0x1000
+#define ETF_0_NIC3_DBG_SECTION                     0x1000
+#define mmSPMU_0_NIC3_DBG_BASE                     0x7FFED84000ull
+#define SPMU_0_NIC3_DBG_MAX_OFFSET                 0x1000
+#define SPMU_0_NIC3_DBG_SECTION                    0x2000
+#define mmUSER_CTI_0_NIC3_DBG_BASE                 0x7FFED86000ull
+#define USER_CTI_0_NIC3_DBG_MAX_OFFSET             0x1000
+#define USER_CTI_0_NIC3_DBG_SECTION                0xB000
+#define mmSTM_1_NIC3_DBG_BASE                      0x7FFED91000ull
+#define STM_1_NIC3_DBG_MAX_OFFSET                  0x1000
+#define STM_1_NIC3_DBG_SECTION                     0x1000
+#define mmCTI_1_NIC3_DBG_BASE                      0x7FFED92000ull
+#define CTI_1_NIC3_DBG_MAX_OFFSET                  0x1000
+#define CTI_1_NIC3_DBG_SECTION                     0x1000
+#define mmETF_1_NIC3_DBG_BASE                      0x7FFED93000ull
+#define ETF_1_NIC3_DBG_MAX_OFFSET                  0x1000
+#define ETF_1_NIC3_DBG_SECTION                     0x1000
+#define mmSPMU_1_NIC3_DBG_BASE                     0x7FFED94000ull
+#define SPMU_1_NIC3_DBG_MAX_OFFSET                 0x1000
+#define SPMU_1_NIC3_DBG_SECTION                    0x1000
+#define mmBMON_CTI_NIC3_DBG_BASE                   0x7FFED95000ull
+#define BMON_CTI_NIC3_DBG_MAX_OFFSET               0x1000
+#define BMON_CTI_NIC3_DBG_SECTION                  0x1000
+#define mmUSER_CTI_1_NIC3_DBG_BASE                 0x7FFED96000ull
+#define USER_CTI_1_NIC3_DBG_MAX_OFFSET             0x1000
+#define USER_CTI_1_NIC3_DBG_SECTION                0x1000
+#define mmBMON0_NIC3_DBG_BASE                      0x7FFED97000ull
+#define BMON0_NIC3_DBG_MAX_OFFSET                  0x1000
+#define BMON0_NIC3_DBG_SECTION                     0x1000
+#define mmBMON1_NIC3_DBG_BASE                      0x7FFED98000ull
+#define BMON1_NIC3_DBG_MAX_OFFSET                  0x1000
+#define BMON1_NIC3_DBG_SECTION                     0x1000
+#define mmBMON2_NIC3_DBG_BASE                      0x7FFED99000ull
+#define BMON2_NIC3_DBG_MAX_OFFSET                  0x1000
+#define BMON2_NIC3_DBG_SECTION                     0x1000
+#define mmBMON3_NIC3_DBG_BASE                      0x7FFED9A000ull
+#define BMON3_NIC3_DBG_MAX_OFFSET                  0x1000
+#define BMON3_NIC3_DBG_SECTION                     0x1000
+#define mmBMON4_NIC3_DBG_BASE                      0x7FFED9B000ull
+#define BMON4_NIC3_DBG_MAX_OFFSET                  0x1000
+#define BMON4_NIC3_DBG_SECTION                     0x6000
+#define mmFUNNEL_NIC3_DBG_BASE                     0x7FFEDA1000ull
+#define FUNNEL_NIC3_DBG_MAX_OFFSET                 0x1000
+#define FUNNEL_NIC3_DBG_SECTION                    0x1F000
+#define mmNIC4_ROM_TABLE_BASE                      0x7FFEDC0000ull
+#define NIC4_ROM_TABLE_MAX_OFFSET                  0x1000
+#define NIC4_ROM_TABLE_SECTION                     0x1000
+#define mmSTM_0_NIC4_DBG_BASE                      0x7FFEDC1000ull
+#define STM_0_NIC4_DBG_MAX_OFFSET                  0x21000
+#define STM_0_NIC4_DBG_SECTION                     0x1000
+#define mmCTI_0_NIC4_DBG_BASE                      0x7FFEDC2000ull
+#define CTI_0_NIC4_DBG_MAX_OFFSET                  0x1000
+#define CTI_0_NIC4_DBG_SECTION                     0x1000
+#define mmETF_0_NIC4_DBG_BASE                      0x7FFEDC3000ull
+#define ETF_0_NIC4_DBG_MAX_OFFSET                  0x1000
+#define ETF_0_NIC4_DBG_SECTION                     0x1000
+#define mmSPMU_0_NIC4_DBG_BASE                     0x7FFEDC4000ull
+#define SPMU_0_NIC4_DBG_MAX_OFFSET                 0x1000
+#define SPMU_0_NIC4_DBG_SECTION                    0x2000
+#define mmUSER_CTI_0_NIC4_DBG_BASE                 0x7FFEDC6000ull
+#define USER_CTI_0_NIC4_DBG_MAX_OFFSET             0x1000
+#define USER_CTI_0_NIC4_DBG_SECTION                0xB000
+#define mmSTM_1_NIC4_DBG_BASE                      0x7FFEDD1000ull
+#define STM_1_NIC4_DBG_MAX_OFFSET                  0x1000
+#define STM_1_NIC4_DBG_SECTION                     0x1000
+#define mmCTI_1_NIC4_DBG_BASE                      0x7FFEDD2000ull
+#define CTI_1_NIC4_DBG_MAX_OFFSET                  0x1000
+#define CTI_1_NIC4_DBG_SECTION                     0x1000
+#define mmETF_1_NIC4_DBG_BASE                      0x7FFEDD3000ull
+#define ETF_1_NIC4_DBG_MAX_OFFSET                  0x1000
+#define ETF_1_NIC4_DBG_SECTION                     0x1000
+#define mmSPMU_1_NIC4_DBG_BASE                     0x7FFEDD4000ull
+#define SPMU_1_NIC4_DBG_MAX_OFFSET                 0x1000
+#define SPMU_1_NIC4_DBG_SECTION                    0x1000
+#define mmBMON_CTI_NIC4_DBG_BASE                   0x7FFEDD5000ull
+#define BMON_CTI_NIC4_DBG_MAX_OFFSET               0x1000
+#define BMON_CTI_NIC4_DBG_SECTION                  0x1000
+#define mmUSER_CTI_1_NIC4_DBG_BASE                 0x7FFEDD6000ull
+#define USER_CTI_1_NIC4_DBG_MAX_OFFSET             0x1000
+#define USER_CTI_1_NIC4_DBG_SECTION                0x1000
+#define mmBMON0_NIC4_DBG_BASE                      0x7FFEDD7000ull
+#define BMON0_NIC4_DBG_MAX_OFFSET                  0x1000
+#define BMON0_NIC4_DBG_SECTION                     0x1000
+#define mmBMON1_NIC4_DBG_BASE                      0x7FFEDD8000ull
+#define BMON1_NIC4_DBG_MAX_OFFSET                  0x1000
+#define BMON1_NIC4_DBG_SECTION                     0x1000
+#define mmBMON2_NIC4_DBG_BASE                      0x7FFEDD9000ull
+#define BMON2_NIC4_DBG_MAX_OFFSET                  0x1000
+#define BMON2_NIC4_DBG_SECTION                     0x1000
+#define mmBMON3_NIC4_DBG_BASE                      0x7FFEDDA000ull
+#define BMON3_NIC4_DBG_MAX_OFFSET                  0x1000
+#define BMON3_NIC4_DBG_SECTION                     0x1000
+#define mmBMON4_NIC4_DBG_BASE                      0x7FFEDDB000ull
+#define BMON4_NIC4_DBG_MAX_OFFSET                  0x1000
+#define BMON4_NIC4_DBG_SECTION                     0x6000
+#define mmFUNNEL_NIC4_DBG_BASE                     0x7FFEDE1000ull
+#define FUNNEL_NIC4_DBG_MAX_OFFSET                 0x1000
+#define FUNNEL_NIC4_DBG_SECTION                    0x21F000
+#define mmTPC0_ROM_TABLE_BASE                      0x7FFF000000ull
+#define TPC0_ROM_TABLE_MAX_OFFSET                  0x1000
+#define TPC0_ROM_TABLE_SECTION                     0x1000
+#define mmTPC0_EML_SPMU_BASE                       0x7FFF001000ull
+#define TPC0_EML_SPMU_MAX_OFFSET                   0x1000
+#define TPC0_EML_SPMU_SECTION                      0x1000
+#define mmTPC0_EML_ETF_BASE                        0x7FFF002000ull
+#define TPC0_EML_ETF_MAX_OFFSET                    0x1000
+#define TPC0_EML_ETF_SECTION                       0x1000
+#define mmTPC0_EML_STM_BASE                        0x7FFF003000ull
+#define TPC0_EML_STM_MAX_OFFSET                    0x1000
+#define TPC0_EML_STM_SECTION                       0x2000
+#define mmTPC0_EML_CTI_BASE                        0x7FFF005000ull
+#define TPC0_EML_CTI_MAX_OFFSET                    0x1000
+#define TPC0_EML_CTI_SECTION                       0x1000
+#define mmTPC0_EML_FUNNEL_BASE                     0x7FFF006000ull
+#define TPC0_EML_FUNNEL_MAX_OFFSET                 0x1000
+#define TPC0_EML_FUNNEL_SECTION                    0x1000
+#define mmTPC0_EML_BUSMON_0_BASE                   0x7FFF007000ull
+#define TPC0_EML_BUSMON_0_MAX_OFFSET               0x1000
+#define TPC0_EML_BUSMON_0_SECTION                  0x1000
+#define mmTPC0_EML_BUSMON_1_BASE                   0x7FFF008000ull
+#define TPC0_EML_BUSMON_1_MAX_OFFSET               0x1000
+#define TPC0_EML_BUSMON_1_SECTION                  0x1000
+#define mmTPC0_EML_BUSMON_2_BASE                   0x7FFF009000ull
+#define TPC0_EML_BUSMON_2_MAX_OFFSET               0x1000
+#define TPC0_EML_BUSMON_2_SECTION                  0x1000
+#define mmTPC0_EML_BUSMON_3_BASE                   0x7FFF00A000ull
+#define TPC0_EML_BUSMON_3_MAX_OFFSET               0x1000
+#define TPC0_EML_BUSMON_3_SECTION                  0x36000
+#define mmTPC0_EML_CFG_BASE                        0x7FFF040000ull
+#define TPC0_EML_CFG_MAX_OFFSET                    0x3380
+#define TPC0_EML_CFG_SECTION                       0x1000
+#define mmTPC0_EML_TPC_CFG_BASE                    0x7FFF041000ull
+#define TPC0_EML_TPC_CFG_MAX_OFFSET                0xE400
+#define TPC0_EML_TPC_CFG_SECTION                   0x4000
+#define mmKERNEL_TENSOR_0_TPC0_EML_TPC_CFG_BASE    0x7FFF041400ull
+#define KERNEL_TENSOR_0_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_0_TPC0_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_1_TPC0_EML_TPC_CFG_BASE    0x7FFF041438ull
+#define KERNEL_TENSOR_1_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_1_TPC0_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_2_TPC0_EML_TPC_CFG_BASE    0x7FFF041470ull
+#define KERNEL_TENSOR_2_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_2_TPC0_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_3_TPC0_EML_TPC_CFG_BASE    0x7FFF0414A8ull
+#define KERNEL_TENSOR_3_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_3_TPC0_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_4_TPC0_EML_TPC_CFG_BASE    0x7FFF0414E0ull
+#define KERNEL_TENSOR_4_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_4_TPC0_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_5_TPC0_EML_TPC_CFG_BASE    0x7FFF041518ull
+#define KERNEL_TENSOR_5_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_5_TPC0_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_6_TPC0_EML_TPC_CFG_BASE    0x7FFF041550ull
+#define KERNEL_TENSOR_6_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_6_TPC0_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_7_TPC0_EML_TPC_CFG_BASE    0x7FFF041588ull
+#define KERNEL_TENSOR_7_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_7_TPC0_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_8_TPC0_EML_TPC_CFG_BASE    0x7FFF0415C0ull
+#define KERNEL_TENSOR_8_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_8_TPC0_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_9_TPC0_EML_TPC_CFG_BASE    0x7FFF0415F8ull
+#define KERNEL_TENSOR_9_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_9_TPC0_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_10_TPC0_EML_TPC_CFG_BASE   0x7FFF041630ull
+#define KERNEL_TENSOR_10_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_10_TPC0_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_TENSOR_11_TPC0_EML_TPC_CFG_BASE   0x7FFF041668ull
+#define KERNEL_TENSOR_11_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_11_TPC0_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_TENSOR_12_TPC0_EML_TPC_CFG_BASE   0x7FFF0416A0ull
+#define KERNEL_TENSOR_12_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_12_TPC0_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_TENSOR_13_TPC0_EML_TPC_CFG_BASE   0x7FFF0416D8ull
+#define KERNEL_TENSOR_13_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_13_TPC0_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_TENSOR_14_TPC0_EML_TPC_CFG_BASE   0x7FFF041710ull
+#define KERNEL_TENSOR_14_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_14_TPC0_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_TENSOR_15_TPC0_EML_TPC_CFG_BASE   0x7FFF041748ull
+#define KERNEL_TENSOR_15_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_15_TPC0_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_SYNC_OBJECT_TPC0_EML_TPC_CFG_BASE 0x7FFF041780ull
+#define KERNEL_SYNC_OBJECT_TPC0_EML_TPC_CFG_MAX_OFFSET 0x8000
+#define KERNEL_SYNC_OBJECT_TPC0_EML_TPC_CFG_SECTION 0x8000
+#define mmKERNEL_TPC0_EML_TPC_CFG_BASE             0x7FFF041788ull
+#define KERNEL_TPC0_EML_TPC_CFG_MAX_OFFSET         0xB800
+#define KERNEL_TPC0_EML_TPC_CFG_SECTION            0x2780
+#define mmQM_TENSOR_0_TPC0_EML_TPC_CFG_BASE        0x7FFF041A00ull
+#define QM_TENSOR_0_TPC0_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_0_TPC0_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_1_TPC0_EML_TPC_CFG_BASE        0x7FFF041A38ull
+#define QM_TENSOR_1_TPC0_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_1_TPC0_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_2_TPC0_EML_TPC_CFG_BASE        0x7FFF041A70ull
+#define QM_TENSOR_2_TPC0_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_2_TPC0_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_3_TPC0_EML_TPC_CFG_BASE        0x7FFF041AA8ull
+#define QM_TENSOR_3_TPC0_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_3_TPC0_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_4_TPC0_EML_TPC_CFG_BASE        0x7FFF041AE0ull
+#define QM_TENSOR_4_TPC0_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_4_TPC0_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_5_TPC0_EML_TPC_CFG_BASE        0x7FFF041B18ull
+#define QM_TENSOR_5_TPC0_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_5_TPC0_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_6_TPC0_EML_TPC_CFG_BASE        0x7FFF041B50ull
+#define QM_TENSOR_6_TPC0_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_6_TPC0_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_7_TPC0_EML_TPC_CFG_BASE        0x7FFF041B88ull
+#define QM_TENSOR_7_TPC0_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_7_TPC0_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_8_TPC0_EML_TPC_CFG_BASE        0x7FFF041BC0ull
+#define QM_TENSOR_8_TPC0_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_8_TPC0_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_9_TPC0_EML_TPC_CFG_BASE        0x7FFF041BF8ull
+#define QM_TENSOR_9_TPC0_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_9_TPC0_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_10_TPC0_EML_TPC_CFG_BASE       0x7FFF041C30ull
+#define QM_TENSOR_10_TPC0_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_10_TPC0_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_TENSOR_11_TPC0_EML_TPC_CFG_BASE       0x7FFF041C68ull
+#define QM_TENSOR_11_TPC0_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_11_TPC0_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_TENSOR_12_TPC0_EML_TPC_CFG_BASE       0x7FFF041CA0ull
+#define QM_TENSOR_12_TPC0_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_12_TPC0_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_TENSOR_13_TPC0_EML_TPC_CFG_BASE       0x7FFF041CD8ull
+#define QM_TENSOR_13_TPC0_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_13_TPC0_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_TENSOR_14_TPC0_EML_TPC_CFG_BASE       0x7FFF041D10ull
+#define QM_TENSOR_14_TPC0_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_14_TPC0_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_TENSOR_15_TPC0_EML_TPC_CFG_BASE       0x7FFF041D48ull
+#define QM_TENSOR_15_TPC0_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_15_TPC0_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_SYNC_OBJECT_TPC0_EML_TPC_CFG_BASE     0x7FFF041D80ull
+#define QM_SYNC_OBJECT_TPC0_EML_TPC_CFG_MAX_OFFSET 0x8000
+#define QM_SYNC_OBJECT_TPC0_EML_TPC_CFG_SECTION    0x8000
+#define mmQM_TPC0_EML_TPC_CFG_BASE                 0x7FFF041D88ull
+#define QM_TPC0_EML_TPC_CFG_MAX_OFFSET             0xB800
+#define QM_TPC0_EML_TPC_CFG_SECTION                0x2780
+#define mmTPC0_EML_TPC_QM_BASE                     0x7FFF042000ull
+#define TPC0_EML_TPC_QM_MAX_OFFSET                 0xD040
+#define TPC0_EML_TPC_QM_SECTION                    0x1BD000
+#define mmTPC0_EML_CS_BASE                         0x7FFF1FF000ull
+#define TPC0_EML_CS_MAX_OFFSET                     0x1000
+#define TPC0_EML_CS_SECTION                        0x1000
+#define mmTPC1_ROM_TABLE_BASE                      0x7FFF200000ull
+#define TPC1_ROM_TABLE_MAX_OFFSET                  0x1000
+#define TPC1_ROM_TABLE_SECTION                     0x1000
+#define mmTPC1_EML_SPMU_BASE                       0x7FFF201000ull
+#define TPC1_EML_SPMU_MAX_OFFSET                   0x1000
+#define TPC1_EML_SPMU_SECTION                      0x1000
+#define mmTPC1_EML_ETF_BASE                        0x7FFF202000ull
+#define TPC1_EML_ETF_MAX_OFFSET                    0x1000
+#define TPC1_EML_ETF_SECTION                       0x1000
+#define mmTPC1_EML_STM_BASE                        0x7FFF203000ull
+#define TPC1_EML_STM_MAX_OFFSET                    0x1000
+#define TPC1_EML_STM_SECTION                       0x2000
+#define mmTPC1_EML_CTI_BASE                        0x7FFF205000ull
+#define TPC1_EML_CTI_MAX_OFFSET                    0x1000
+#define TPC1_EML_CTI_SECTION                       0x1000
+#define mmTPC1_EML_FUNNEL_BASE                     0x7FFF206000ull
+#define TPC1_EML_FUNNEL_MAX_OFFSET                 0x1000
+#define TPC1_EML_FUNNEL_SECTION                    0x1000
+#define mmTPC1_EML_BUSMON_0_BASE                   0x7FFF207000ull
+#define TPC1_EML_BUSMON_0_MAX_OFFSET               0x1000
+#define TPC1_EML_BUSMON_0_SECTION                  0x1000
+#define mmTPC1_EML_BUSMON_1_BASE                   0x7FFF208000ull
+#define TPC1_EML_BUSMON_1_MAX_OFFSET               0x1000
+#define TPC1_EML_BUSMON_1_SECTION                  0x1000
+#define mmTPC1_EML_BUSMON_2_BASE                   0x7FFF209000ull
+#define TPC1_EML_BUSMON_2_MAX_OFFSET               0x1000
+#define TPC1_EML_BUSMON_2_SECTION                  0x1000
+#define mmTPC1_EML_BUSMON_3_BASE                   0x7FFF20A000ull
+#define TPC1_EML_BUSMON_3_MAX_OFFSET               0x1000
+#define TPC1_EML_BUSMON_3_SECTION                  0x36000
+#define mmTPC1_EML_CFG_BASE                        0x7FFF240000ull
+#define TPC1_EML_CFG_MAX_OFFSET                    0x3380
+#define TPC1_EML_CFG_SECTION                       0x1000
+#define mmTPC1_EML_TPC_CFG_BASE                    0x7FFF241000ull
+#define TPC1_EML_TPC_CFG_MAX_OFFSET                0xE400
+#define TPC1_EML_TPC_CFG_SECTION                   0x4000
+#define mmKERNEL_TENSOR_0_TPC1_EML_TPC_CFG_BASE    0x7FFF241400ull
+#define KERNEL_TENSOR_0_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_0_TPC1_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_1_TPC1_EML_TPC_CFG_BASE    0x7FFF241438ull
+#define KERNEL_TENSOR_1_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_1_TPC1_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_2_TPC1_EML_TPC_CFG_BASE    0x7FFF241470ull
+#define KERNEL_TENSOR_2_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_2_TPC1_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_3_TPC1_EML_TPC_CFG_BASE    0x7FFF2414A8ull
+#define KERNEL_TENSOR_3_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_3_TPC1_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_4_TPC1_EML_TPC_CFG_BASE    0x7FFF2414E0ull
+#define KERNEL_TENSOR_4_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_4_TPC1_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_5_TPC1_EML_TPC_CFG_BASE    0x7FFF241518ull
+#define KERNEL_TENSOR_5_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_5_TPC1_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_6_TPC1_EML_TPC_CFG_BASE    0x7FFF241550ull
+#define KERNEL_TENSOR_6_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_6_TPC1_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_7_TPC1_EML_TPC_CFG_BASE    0x7FFF241588ull
+#define KERNEL_TENSOR_7_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_7_TPC1_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_8_TPC1_EML_TPC_CFG_BASE    0x7FFF2415C0ull
+#define KERNEL_TENSOR_8_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_8_TPC1_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_9_TPC1_EML_TPC_CFG_BASE    0x7FFF2415F8ull
+#define KERNEL_TENSOR_9_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_9_TPC1_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_10_TPC1_EML_TPC_CFG_BASE   0x7FFF241630ull
+#define KERNEL_TENSOR_10_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_10_TPC1_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_TENSOR_11_TPC1_EML_TPC_CFG_BASE   0x7FFF241668ull
+#define KERNEL_TENSOR_11_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_11_TPC1_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_TENSOR_12_TPC1_EML_TPC_CFG_BASE   0x7FFF2416A0ull
+#define KERNEL_TENSOR_12_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_12_TPC1_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_TENSOR_13_TPC1_EML_TPC_CFG_BASE   0x7FFF2416D8ull
+#define KERNEL_TENSOR_13_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_13_TPC1_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_TENSOR_14_TPC1_EML_TPC_CFG_BASE   0x7FFF241710ull
+#define KERNEL_TENSOR_14_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_14_TPC1_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_TENSOR_15_TPC1_EML_TPC_CFG_BASE   0x7FFF241748ull
+#define KERNEL_TENSOR_15_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_15_TPC1_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_SYNC_OBJECT_TPC1_EML_TPC_CFG_BASE 0x7FFF241780ull
+#define KERNEL_SYNC_OBJECT_TPC1_EML_TPC_CFG_MAX_OFFSET 0x8000
+#define KERNEL_SYNC_OBJECT_TPC1_EML_TPC_CFG_SECTION 0x8000
+#define mmKERNEL_TPC1_EML_TPC_CFG_BASE             0x7FFF241788ull
+#define KERNEL_TPC1_EML_TPC_CFG_MAX_OFFSET         0xB800
+#define KERNEL_TPC1_EML_TPC_CFG_SECTION            0x2780
+#define mmQM_TENSOR_0_TPC1_EML_TPC_CFG_BASE        0x7FFF241A00ull
+#define QM_TENSOR_0_TPC1_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_0_TPC1_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_1_TPC1_EML_TPC_CFG_BASE        0x7FFF241A38ull
+#define QM_TENSOR_1_TPC1_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_1_TPC1_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_2_TPC1_EML_TPC_CFG_BASE        0x7FFF241A70ull
+#define QM_TENSOR_2_TPC1_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_2_TPC1_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_3_TPC1_EML_TPC_CFG_BASE        0x7FFF241AA8ull
+#define QM_TENSOR_3_TPC1_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_3_TPC1_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_4_TPC1_EML_TPC_CFG_BASE        0x7FFF241AE0ull
+#define QM_TENSOR_4_TPC1_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_4_TPC1_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_5_TPC1_EML_TPC_CFG_BASE        0x7FFF241B18ull
+#define QM_TENSOR_5_TPC1_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_5_TPC1_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_6_TPC1_EML_TPC_CFG_BASE        0x7FFF241B50ull
+#define QM_TENSOR_6_TPC1_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_6_TPC1_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_7_TPC1_EML_TPC_CFG_BASE        0x7FFF241B88ull
+#define QM_TENSOR_7_TPC1_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_7_TPC1_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_8_TPC1_EML_TPC_CFG_BASE        0x7FFF241BC0ull
+#define QM_TENSOR_8_TPC1_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_8_TPC1_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_9_TPC1_EML_TPC_CFG_BASE        0x7FFF241BF8ull
+#define QM_TENSOR_9_TPC1_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_9_TPC1_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_10_TPC1_EML_TPC_CFG_BASE       0x7FFF241C30ull
+#define QM_TENSOR_10_TPC1_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_10_TPC1_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_TENSOR_11_TPC1_EML_TPC_CFG_BASE       0x7FFF241C68ull
+#define QM_TENSOR_11_TPC1_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_11_TPC1_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_TENSOR_12_TPC1_EML_TPC_CFG_BASE       0x7FFF241CA0ull
+#define QM_TENSOR_12_TPC1_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_12_TPC1_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_TENSOR_13_TPC1_EML_TPC_CFG_BASE       0x7FFF241CD8ull
+#define QM_TENSOR_13_TPC1_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_13_TPC1_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_TENSOR_14_TPC1_EML_TPC_CFG_BASE       0x7FFF241D10ull
+#define QM_TENSOR_14_TPC1_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_14_TPC1_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_TENSOR_15_TPC1_EML_TPC_CFG_BASE       0x7FFF241D48ull
+#define QM_TENSOR_15_TPC1_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_15_TPC1_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_SYNC_OBJECT_TPC1_EML_TPC_CFG_BASE     0x7FFF241D80ull
+#define QM_SYNC_OBJECT_TPC1_EML_TPC_CFG_MAX_OFFSET 0x8000
+#define QM_SYNC_OBJECT_TPC1_EML_TPC_CFG_SECTION    0x8000
+#define mmQM_TPC1_EML_TPC_CFG_BASE                 0x7FFF241D88ull
+#define QM_TPC1_EML_TPC_CFG_MAX_OFFSET             0xB800
+#define QM_TPC1_EML_TPC_CFG_SECTION                0x2780
+#define mmTPC1_EML_TPC_QM_BASE                     0x7FFF242000ull
+#define TPC1_EML_TPC_QM_MAX_OFFSET                 0xD040
+#define TPC1_EML_TPC_QM_SECTION                    0x1BD000
+#define mmTPC1_EML_CS_BASE                         0x7FFF3FF000ull
+#define TPC1_EML_CS_MAX_OFFSET                     0x1000
+#define TPC1_EML_CS_SECTION                        0x1000
+#define mmTPC2_ROM_TABLE_BASE                      0x7FFF400000ull
+#define TPC2_ROM_TABLE_MAX_OFFSET                  0x1000
+#define TPC2_ROM_TABLE_SECTION                     0x1000
+#define mmTPC2_EML_SPMU_BASE                       0x7FFF401000ull
+#define TPC2_EML_SPMU_MAX_OFFSET                   0x1000
+#define TPC2_EML_SPMU_SECTION                      0x1000
+#define mmTPC2_EML_ETF_BASE                        0x7FFF402000ull
+#define TPC2_EML_ETF_MAX_OFFSET                    0x1000
+#define TPC2_EML_ETF_SECTION                       0x1000
+#define mmTPC2_EML_STM_BASE                        0x7FFF403000ull
+#define TPC2_EML_STM_MAX_OFFSET                    0x1000
+#define TPC2_EML_STM_SECTION                       0x2000
+#define mmTPC2_EML_CTI_BASE                        0x7FFF405000ull
+#define TPC2_EML_CTI_MAX_OFFSET                    0x1000
+#define TPC2_EML_CTI_SECTION                       0x1000
+#define mmTPC2_EML_FUNNEL_BASE                     0x7FFF406000ull
+#define TPC2_EML_FUNNEL_MAX_OFFSET                 0x1000
+#define TPC2_EML_FUNNEL_SECTION                    0x1000
+#define mmTPC2_EML_BUSMON_0_BASE                   0x7FFF407000ull
+#define TPC2_EML_BUSMON_0_MAX_OFFSET               0x1000
+#define TPC2_EML_BUSMON_0_SECTION                  0x1000
+#define mmTPC2_EML_BUSMON_1_BASE                   0x7FFF408000ull
+#define TPC2_EML_BUSMON_1_MAX_OFFSET               0x1000
+#define TPC2_EML_BUSMON_1_SECTION                  0x1000
+#define mmTPC2_EML_BUSMON_2_BASE                   0x7FFF409000ull
+#define TPC2_EML_BUSMON_2_MAX_OFFSET               0x1000
+#define TPC2_EML_BUSMON_2_SECTION                  0x1000
+#define mmTPC2_EML_BUSMON_3_BASE                   0x7FFF40A000ull
+#define TPC2_EML_BUSMON_3_MAX_OFFSET               0x1000
+#define TPC2_EML_BUSMON_3_SECTION                  0x36000
+#define mmTPC2_EML_CFG_BASE                        0x7FFF440000ull
+#define TPC2_EML_CFG_MAX_OFFSET                    0x3380
+#define TPC2_EML_CFG_SECTION                       0x1000
+#define mmTPC2_EML_TPC_CFG_BASE                    0x7FFF441000ull
+#define TPC2_EML_TPC_CFG_MAX_OFFSET                0xE400
+#define TPC2_EML_TPC_CFG_SECTION                   0x4000
+#define mmKERNEL_TENSOR_0_TPC2_EML_TPC_CFG_BASE    0x7FFF441400ull
+#define KERNEL_TENSOR_0_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_0_TPC2_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_1_TPC2_EML_TPC_CFG_BASE    0x7FFF441438ull
+#define KERNEL_TENSOR_1_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_1_TPC2_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_2_TPC2_EML_TPC_CFG_BASE    0x7FFF441470ull
+#define KERNEL_TENSOR_2_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_2_TPC2_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_3_TPC2_EML_TPC_CFG_BASE    0x7FFF4414A8ull
+#define KERNEL_TENSOR_3_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_3_TPC2_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_4_TPC2_EML_TPC_CFG_BASE    0x7FFF4414E0ull
+#define KERNEL_TENSOR_4_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_4_TPC2_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_5_TPC2_EML_TPC_CFG_BASE    0x7FFF441518ull
+#define KERNEL_TENSOR_5_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_5_TPC2_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_6_TPC2_EML_TPC_CFG_BASE    0x7FFF441550ull
+#define KERNEL_TENSOR_6_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_6_TPC2_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_7_TPC2_EML_TPC_CFG_BASE    0x7FFF441588ull
+#define KERNEL_TENSOR_7_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_7_TPC2_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_8_TPC2_EML_TPC_CFG_BASE    0x7FFF4415C0ull
+#define KERNEL_TENSOR_8_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_8_TPC2_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_9_TPC2_EML_TPC_CFG_BASE    0x7FFF4415F8ull
+#define KERNEL_TENSOR_9_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_9_TPC2_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_10_TPC2_EML_TPC_CFG_BASE   0x7FFF441630ull
+#define KERNEL_TENSOR_10_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_10_TPC2_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_TENSOR_11_TPC2_EML_TPC_CFG_BASE   0x7FFF441668ull
+#define KERNEL_TENSOR_11_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_11_TPC2_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_TENSOR_12_TPC2_EML_TPC_CFG_BASE   0x7FFF4416A0ull
+#define KERNEL_TENSOR_12_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_12_TPC2_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_TENSOR_13_TPC2_EML_TPC_CFG_BASE   0x7FFF4416D8ull
+#define KERNEL_TENSOR_13_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_13_TPC2_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_TENSOR_14_TPC2_EML_TPC_CFG_BASE   0x7FFF441710ull
+#define KERNEL_TENSOR_14_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_14_TPC2_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_TENSOR_15_TPC2_EML_TPC_CFG_BASE   0x7FFF441748ull
+#define KERNEL_TENSOR_15_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_15_TPC2_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_SYNC_OBJECT_TPC2_EML_TPC_CFG_BASE 0x7FFF441780ull
+#define KERNEL_SYNC_OBJECT_TPC2_EML_TPC_CFG_MAX_OFFSET 0x8000
+#define KERNEL_SYNC_OBJECT_TPC2_EML_TPC_CFG_SECTION 0x8000
+#define mmKERNEL_TPC2_EML_TPC_CFG_BASE             0x7FFF441788ull
+#define KERNEL_TPC2_EML_TPC_CFG_MAX_OFFSET         0xB800
+#define KERNEL_TPC2_EML_TPC_CFG_SECTION            0x2780
+#define mmQM_TENSOR_0_TPC2_EML_TPC_CFG_BASE        0x7FFF441A00ull
+#define QM_TENSOR_0_TPC2_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_0_TPC2_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_1_TPC2_EML_TPC_CFG_BASE        0x7FFF441A38ull
+#define QM_TENSOR_1_TPC2_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_1_TPC2_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_2_TPC2_EML_TPC_CFG_BASE        0x7FFF441A70ull
+#define QM_TENSOR_2_TPC2_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_2_TPC2_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_3_TPC2_EML_TPC_CFG_BASE        0x7FFF441AA8ull
+#define QM_TENSOR_3_TPC2_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_3_TPC2_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_4_TPC2_EML_TPC_CFG_BASE        0x7FFF441AE0ull
+#define QM_TENSOR_4_TPC2_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_4_TPC2_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_5_TPC2_EML_TPC_CFG_BASE        0x7FFF441B18ull
+#define QM_TENSOR_5_TPC2_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_5_TPC2_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_6_TPC2_EML_TPC_CFG_BASE        0x7FFF441B50ull
+#define QM_TENSOR_6_TPC2_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_6_TPC2_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_7_TPC2_EML_TPC_CFG_BASE        0x7FFF441B88ull
+#define QM_TENSOR_7_TPC2_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_7_TPC2_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_8_TPC2_EML_TPC_CFG_BASE        0x7FFF441BC0ull
+#define QM_TENSOR_8_TPC2_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_8_TPC2_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_9_TPC2_EML_TPC_CFG_BASE        0x7FFF441BF8ull
+#define QM_TENSOR_9_TPC2_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_9_TPC2_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_10_TPC2_EML_TPC_CFG_BASE       0x7FFF441C30ull
+#define QM_TENSOR_10_TPC2_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_10_TPC2_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_TENSOR_11_TPC2_EML_TPC_CFG_BASE       0x7FFF441C68ull
+#define QM_TENSOR_11_TPC2_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_11_TPC2_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_TENSOR_12_TPC2_EML_TPC_CFG_BASE       0x7FFF441CA0ull
+#define QM_TENSOR_12_TPC2_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_12_TPC2_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_TENSOR_13_TPC2_EML_TPC_CFG_BASE       0x7FFF441CD8ull
+#define QM_TENSOR_13_TPC2_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_13_TPC2_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_TENSOR_14_TPC2_EML_TPC_CFG_BASE       0x7FFF441D10ull
+#define QM_TENSOR_14_TPC2_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_14_TPC2_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_TENSOR_15_TPC2_EML_TPC_CFG_BASE       0x7FFF441D48ull
+#define QM_TENSOR_15_TPC2_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_15_TPC2_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_SYNC_OBJECT_TPC2_EML_TPC_CFG_BASE     0x7FFF441D80ull
+#define QM_SYNC_OBJECT_TPC2_EML_TPC_CFG_MAX_OFFSET 0x8000
+#define QM_SYNC_OBJECT_TPC2_EML_TPC_CFG_SECTION    0x8000
+#define mmQM_TPC2_EML_TPC_CFG_BASE                 0x7FFF441D88ull
+#define QM_TPC2_EML_TPC_CFG_MAX_OFFSET             0xB800
+#define QM_TPC2_EML_TPC_CFG_SECTION                0x2780
+#define mmTPC2_EML_TPC_QM_BASE                     0x7FFF442000ull
+#define TPC2_EML_TPC_QM_MAX_OFFSET                 0xD040
+#define TPC2_EML_TPC_QM_SECTION                    0x1BD000
+#define mmTPC2_EML_CS_BASE                         0x7FFF5FF000ull
+#define TPC2_EML_CS_MAX_OFFSET                     0x1000
+#define TPC2_EML_CS_SECTION                        0x1000
+#define mmTPC3_ROM_TABLE_BASE                      0x7FFF600000ull
+#define TPC3_ROM_TABLE_MAX_OFFSET                  0x1000
+#define TPC3_ROM_TABLE_SECTION                     0x1000
+#define mmTPC3_EML_SPMU_BASE                       0x7FFF601000ull
+#define TPC3_EML_SPMU_MAX_OFFSET                   0x1000
+#define TPC3_EML_SPMU_SECTION                      0x1000
+#define mmTPC3_EML_ETF_BASE                        0x7FFF602000ull
+#define TPC3_EML_ETF_MAX_OFFSET                    0x1000
+#define TPC3_EML_ETF_SECTION                       0x1000
+#define mmTPC3_EML_STM_BASE                        0x7FFF603000ull
+#define TPC3_EML_STM_MAX_OFFSET                    0x1000
+#define TPC3_EML_STM_SECTION                       0x2000
+#define mmTPC3_EML_CTI_BASE                        0x7FFF605000ull
+#define TPC3_EML_CTI_MAX_OFFSET                    0x1000
+#define TPC3_EML_CTI_SECTION                       0x1000
+#define mmTPC3_EML_FUNNEL_BASE                     0x7FFF606000ull
+#define TPC3_EML_FUNNEL_MAX_OFFSET                 0x1000
+#define TPC3_EML_FUNNEL_SECTION                    0x1000
+#define mmTPC3_EML_BUSMON_0_BASE                   0x7FFF607000ull
+#define TPC3_EML_BUSMON_0_MAX_OFFSET               0x1000
+#define TPC3_EML_BUSMON_0_SECTION                  0x1000
+#define mmTPC3_EML_BUSMON_1_BASE                   0x7FFF608000ull
+#define TPC3_EML_BUSMON_1_MAX_OFFSET               0x1000
+#define TPC3_EML_BUSMON_1_SECTION                  0x1000
+#define mmTPC3_EML_BUSMON_2_BASE                   0x7FFF609000ull
+#define TPC3_EML_BUSMON_2_MAX_OFFSET               0x1000
+#define TPC3_EML_BUSMON_2_SECTION                  0x1000
+#define mmTPC3_EML_BUSMON_3_BASE                   0x7FFF60A000ull
+#define TPC3_EML_BUSMON_3_MAX_OFFSET               0x1000
+#define TPC3_EML_BUSMON_3_SECTION                  0x36000
+#define mmTPC3_EML_CFG_BASE                        0x7FFF640000ull
+#define TPC3_EML_CFG_MAX_OFFSET                    0x3380
+#define TPC3_EML_CFG_SECTION                       0x1000
+#define mmTPC3_EML_TPC_CFG_BASE                    0x7FFF641000ull
+#define TPC3_EML_TPC_CFG_MAX_OFFSET                0xE400
+#define TPC3_EML_TPC_CFG_SECTION                   0x4000
+#define mmKERNEL_TENSOR_0_TPC3_EML_TPC_CFG_BASE    0x7FFF641400ull
+#define KERNEL_TENSOR_0_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_0_TPC3_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_1_TPC3_EML_TPC_CFG_BASE    0x7FFF641438ull
+#define KERNEL_TENSOR_1_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_1_TPC3_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_2_TPC3_EML_TPC_CFG_BASE    0x7FFF641470ull
+#define KERNEL_TENSOR_2_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_2_TPC3_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_3_TPC3_EML_TPC_CFG_BASE    0x7FFF6414A8ull
+#define KERNEL_TENSOR_3_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_3_TPC3_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_4_TPC3_EML_TPC_CFG_BASE    0x7FFF6414E0ull
+#define KERNEL_TENSOR_4_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_4_TPC3_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_5_TPC3_EML_TPC_CFG_BASE    0x7FFF641518ull
+#define KERNEL_TENSOR_5_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_5_TPC3_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_6_TPC3_EML_TPC_CFG_BASE    0x7FFF641550ull
+#define KERNEL_TENSOR_6_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_6_TPC3_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_7_TPC3_EML_TPC_CFG_BASE    0x7FFF641588ull
+#define KERNEL_TENSOR_7_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_7_TPC3_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_8_TPC3_EML_TPC_CFG_BASE    0x7FFF6415C0ull
+#define KERNEL_TENSOR_8_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_8_TPC3_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_9_TPC3_EML_TPC_CFG_BASE    0x7FFF6415F8ull
+#define KERNEL_TENSOR_9_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_9_TPC3_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_10_TPC3_EML_TPC_CFG_BASE   0x7FFF641630ull
+#define KERNEL_TENSOR_10_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_10_TPC3_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_TENSOR_11_TPC3_EML_TPC_CFG_BASE   0x7FFF641668ull
+#define KERNEL_TENSOR_11_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_11_TPC3_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_TENSOR_12_TPC3_EML_TPC_CFG_BASE   0x7FFF6416A0ull
+#define KERNEL_TENSOR_12_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_12_TPC3_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_TENSOR_13_TPC3_EML_TPC_CFG_BASE   0x7FFF6416D8ull
+#define KERNEL_TENSOR_13_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_13_TPC3_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_TENSOR_14_TPC3_EML_TPC_CFG_BASE   0x7FFF641710ull
+#define KERNEL_TENSOR_14_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_14_TPC3_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_TENSOR_15_TPC3_EML_TPC_CFG_BASE   0x7FFF641748ull
+#define KERNEL_TENSOR_15_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_15_TPC3_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_SYNC_OBJECT_TPC3_EML_TPC_CFG_BASE 0x7FFF641780ull
+#define KERNEL_SYNC_OBJECT_TPC3_EML_TPC_CFG_MAX_OFFSET 0x8000
+#define KERNEL_SYNC_OBJECT_TPC3_EML_TPC_CFG_SECTION 0x8000
+#define mmKERNEL_TPC3_EML_TPC_CFG_BASE             0x7FFF641788ull
+#define KERNEL_TPC3_EML_TPC_CFG_MAX_OFFSET         0xB800
+#define KERNEL_TPC3_EML_TPC_CFG_SECTION            0x2780
+#define mmQM_TENSOR_0_TPC3_EML_TPC_CFG_BASE        0x7FFF641A00ull
+#define QM_TENSOR_0_TPC3_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_0_TPC3_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_1_TPC3_EML_TPC_CFG_BASE        0x7FFF641A38ull
+#define QM_TENSOR_1_TPC3_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_1_TPC3_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_2_TPC3_EML_TPC_CFG_BASE        0x7FFF641A70ull
+#define QM_TENSOR_2_TPC3_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_2_TPC3_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_3_TPC3_EML_TPC_CFG_BASE        0x7FFF641AA8ull
+#define QM_TENSOR_3_TPC3_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_3_TPC3_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_4_TPC3_EML_TPC_CFG_BASE        0x7FFF641AE0ull
+#define QM_TENSOR_4_TPC3_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_4_TPC3_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_5_TPC3_EML_TPC_CFG_BASE        0x7FFF641B18ull
+#define QM_TENSOR_5_TPC3_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_5_TPC3_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_6_TPC3_EML_TPC_CFG_BASE        0x7FFF641B50ull
+#define QM_TENSOR_6_TPC3_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_6_TPC3_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_7_TPC3_EML_TPC_CFG_BASE        0x7FFF641B88ull
+#define QM_TENSOR_7_TPC3_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_7_TPC3_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_8_TPC3_EML_TPC_CFG_BASE        0x7FFF641BC0ull
+#define QM_TENSOR_8_TPC3_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_8_TPC3_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_9_TPC3_EML_TPC_CFG_BASE        0x7FFF641BF8ull
+#define QM_TENSOR_9_TPC3_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_9_TPC3_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_10_TPC3_EML_TPC_CFG_BASE       0x7FFF641C30ull
+#define QM_TENSOR_10_TPC3_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_10_TPC3_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_TENSOR_11_TPC3_EML_TPC_CFG_BASE       0x7FFF641C68ull
+#define QM_TENSOR_11_TPC3_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_11_TPC3_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_TENSOR_12_TPC3_EML_TPC_CFG_BASE       0x7FFF641CA0ull
+#define QM_TENSOR_12_TPC3_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_12_TPC3_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_TENSOR_13_TPC3_EML_TPC_CFG_BASE       0x7FFF641CD8ull
+#define QM_TENSOR_13_TPC3_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_13_TPC3_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_TENSOR_14_TPC3_EML_TPC_CFG_BASE       0x7FFF641D10ull
+#define QM_TENSOR_14_TPC3_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_14_TPC3_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_TENSOR_15_TPC3_EML_TPC_CFG_BASE       0x7FFF641D48ull
+#define QM_TENSOR_15_TPC3_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_15_TPC3_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_SYNC_OBJECT_TPC3_EML_TPC_CFG_BASE     0x7FFF641D80ull
+#define QM_SYNC_OBJECT_TPC3_EML_TPC_CFG_MAX_OFFSET 0x8000
+#define QM_SYNC_OBJECT_TPC3_EML_TPC_CFG_SECTION    0x8000
+#define mmQM_TPC3_EML_TPC_CFG_BASE                 0x7FFF641D88ull
+#define QM_TPC3_EML_TPC_CFG_MAX_OFFSET             0xB800
+#define QM_TPC3_EML_TPC_CFG_SECTION                0x2780
+#define mmTPC3_EML_TPC_QM_BASE                     0x7FFF642000ull
+#define TPC3_EML_TPC_QM_MAX_OFFSET                 0xD040
+#define TPC3_EML_TPC_QM_SECTION                    0x1BD000
+#define mmTPC3_EML_CS_BASE                         0x7FFF7FF000ull
+#define TPC3_EML_CS_MAX_OFFSET                     0x1000
+#define TPC3_EML_CS_SECTION                        0x1000
+#define mmTPC4_ROM_TABLE_BASE                      0x7FFF800000ull
+#define TPC4_ROM_TABLE_MAX_OFFSET                  0x1000
+#define TPC4_ROM_TABLE_SECTION                     0x1000
+#define mmTPC4_EML_SPMU_BASE                       0x7FFF801000ull
+#define TPC4_EML_SPMU_MAX_OFFSET                   0x1000
+#define TPC4_EML_SPMU_SECTION                      0x1000
+#define mmTPC4_EML_ETF_BASE                        0x7FFF802000ull
+#define TPC4_EML_ETF_MAX_OFFSET                    0x1000
+#define TPC4_EML_ETF_SECTION                       0x1000
+#define mmTPC4_EML_STM_BASE                        0x7FFF803000ull
+#define TPC4_EML_STM_MAX_OFFSET                    0x1000
+#define TPC4_EML_STM_SECTION                       0x2000
+#define mmTPC4_EML_CTI_BASE                        0x7FFF805000ull
+#define TPC4_EML_CTI_MAX_OFFSET                    0x1000
+#define TPC4_EML_CTI_SECTION                       0x1000
+#define mmTPC4_EML_FUNNEL_BASE                     0x7FFF806000ull
+#define TPC4_EML_FUNNEL_MAX_OFFSET                 0x1000
+#define TPC4_EML_FUNNEL_SECTION                    0x1000
+#define mmTPC4_EML_BUSMON_0_BASE                   0x7FFF807000ull
+#define TPC4_EML_BUSMON_0_MAX_OFFSET               0x1000
+#define TPC4_EML_BUSMON_0_SECTION                  0x1000
+#define mmTPC4_EML_BUSMON_1_BASE                   0x7FFF808000ull
+#define TPC4_EML_BUSMON_1_MAX_OFFSET               0x1000
+#define TPC4_EML_BUSMON_1_SECTION                  0x1000
+#define mmTPC4_EML_BUSMON_2_BASE                   0x7FFF809000ull
+#define TPC4_EML_BUSMON_2_MAX_OFFSET               0x1000
+#define TPC4_EML_BUSMON_2_SECTION                  0x1000
+#define mmTPC4_EML_BUSMON_3_BASE                   0x7FFF80A000ull
+#define TPC4_EML_BUSMON_3_MAX_OFFSET               0x1000
+#define TPC4_EML_BUSMON_3_SECTION                  0x36000
+#define mmTPC4_EML_CFG_BASE                        0x7FFF840000ull
+#define TPC4_EML_CFG_MAX_OFFSET                    0x3380
+#define TPC4_EML_CFG_SECTION                       0x1000
+#define mmTPC4_EML_TPC_CFG_BASE                    0x7FFF841000ull
+#define TPC4_EML_TPC_CFG_MAX_OFFSET                0xE400
+#define TPC4_EML_TPC_CFG_SECTION                   0x4000
+#define mmKERNEL_TENSOR_0_TPC4_EML_TPC_CFG_BASE    0x7FFF841400ull
+#define KERNEL_TENSOR_0_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_0_TPC4_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_1_TPC4_EML_TPC_CFG_BASE    0x7FFF841438ull
+#define KERNEL_TENSOR_1_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_1_TPC4_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_2_TPC4_EML_TPC_CFG_BASE    0x7FFF841470ull
+#define KERNEL_TENSOR_2_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_2_TPC4_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_3_TPC4_EML_TPC_CFG_BASE    0x7FFF8414A8ull
+#define KERNEL_TENSOR_3_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_3_TPC4_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_4_TPC4_EML_TPC_CFG_BASE    0x7FFF8414E0ull
+#define KERNEL_TENSOR_4_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_4_TPC4_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_5_TPC4_EML_TPC_CFG_BASE    0x7FFF841518ull
+#define KERNEL_TENSOR_5_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_5_TPC4_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_6_TPC4_EML_TPC_CFG_BASE    0x7FFF841550ull
+#define KERNEL_TENSOR_6_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_6_TPC4_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_7_TPC4_EML_TPC_CFG_BASE    0x7FFF841588ull
+#define KERNEL_TENSOR_7_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_7_TPC4_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_8_TPC4_EML_TPC_CFG_BASE    0x7FFF8415C0ull
+#define KERNEL_TENSOR_8_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_8_TPC4_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_9_TPC4_EML_TPC_CFG_BASE    0x7FFF8415F8ull
+#define KERNEL_TENSOR_9_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_9_TPC4_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_10_TPC4_EML_TPC_CFG_BASE   0x7FFF841630ull
+#define KERNEL_TENSOR_10_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_10_TPC4_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_TENSOR_11_TPC4_EML_TPC_CFG_BASE   0x7FFF841668ull
+#define KERNEL_TENSOR_11_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_11_TPC4_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_TENSOR_12_TPC4_EML_TPC_CFG_BASE   0x7FFF8416A0ull
+#define KERNEL_TENSOR_12_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_12_TPC4_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_TENSOR_13_TPC4_EML_TPC_CFG_BASE   0x7FFF8416D8ull
+#define KERNEL_TENSOR_13_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_13_TPC4_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_TENSOR_14_TPC4_EML_TPC_CFG_BASE   0x7FFF841710ull
+#define KERNEL_TENSOR_14_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_14_TPC4_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_TENSOR_15_TPC4_EML_TPC_CFG_BASE   0x7FFF841748ull
+#define KERNEL_TENSOR_15_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_15_TPC4_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_SYNC_OBJECT_TPC4_EML_TPC_CFG_BASE 0x7FFF841780ull
+#define KERNEL_SYNC_OBJECT_TPC4_EML_TPC_CFG_MAX_OFFSET 0x8000
+#define KERNEL_SYNC_OBJECT_TPC4_EML_TPC_CFG_SECTION 0x8000
+#define mmKERNEL_TPC4_EML_TPC_CFG_BASE             0x7FFF841788ull
+#define KERNEL_TPC4_EML_TPC_CFG_MAX_OFFSET         0xB800
+#define KERNEL_TPC4_EML_TPC_CFG_SECTION            0x2780
+#define mmQM_TENSOR_0_TPC4_EML_TPC_CFG_BASE        0x7FFF841A00ull
+#define QM_TENSOR_0_TPC4_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_0_TPC4_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_1_TPC4_EML_TPC_CFG_BASE        0x7FFF841A38ull
+#define QM_TENSOR_1_TPC4_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_1_TPC4_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_2_TPC4_EML_TPC_CFG_BASE        0x7FFF841A70ull
+#define QM_TENSOR_2_TPC4_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_2_TPC4_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_3_TPC4_EML_TPC_CFG_BASE        0x7FFF841AA8ull
+#define QM_TENSOR_3_TPC4_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_3_TPC4_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_4_TPC4_EML_TPC_CFG_BASE        0x7FFF841AE0ull
+#define QM_TENSOR_4_TPC4_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_4_TPC4_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_5_TPC4_EML_TPC_CFG_BASE        0x7FFF841B18ull
+#define QM_TENSOR_5_TPC4_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_5_TPC4_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_6_TPC4_EML_TPC_CFG_BASE        0x7FFF841B50ull
+#define QM_TENSOR_6_TPC4_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_6_TPC4_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_7_TPC4_EML_TPC_CFG_BASE        0x7FFF841B88ull
+#define QM_TENSOR_7_TPC4_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_7_TPC4_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_8_TPC4_EML_TPC_CFG_BASE        0x7FFF841BC0ull
+#define QM_TENSOR_8_TPC4_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_8_TPC4_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_9_TPC4_EML_TPC_CFG_BASE        0x7FFF841BF8ull
+#define QM_TENSOR_9_TPC4_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_9_TPC4_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_10_TPC4_EML_TPC_CFG_BASE       0x7FFF841C30ull
+#define QM_TENSOR_10_TPC4_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_10_TPC4_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_TENSOR_11_TPC4_EML_TPC_CFG_BASE       0x7FFF841C68ull
+#define QM_TENSOR_11_TPC4_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_11_TPC4_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_TENSOR_12_TPC4_EML_TPC_CFG_BASE       0x7FFF841CA0ull
+#define QM_TENSOR_12_TPC4_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_12_TPC4_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_TENSOR_13_TPC4_EML_TPC_CFG_BASE       0x7FFF841CD8ull
+#define QM_TENSOR_13_TPC4_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_13_TPC4_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_TENSOR_14_TPC4_EML_TPC_CFG_BASE       0x7FFF841D10ull
+#define QM_TENSOR_14_TPC4_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_14_TPC4_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_TENSOR_15_TPC4_EML_TPC_CFG_BASE       0x7FFF841D48ull
+#define QM_TENSOR_15_TPC4_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_15_TPC4_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_SYNC_OBJECT_TPC4_EML_TPC_CFG_BASE     0x7FFF841D80ull
+#define QM_SYNC_OBJECT_TPC4_EML_TPC_CFG_MAX_OFFSET 0x8000
+#define QM_SYNC_OBJECT_TPC4_EML_TPC_CFG_SECTION    0x8000
+#define mmQM_TPC4_EML_TPC_CFG_BASE                 0x7FFF841D88ull
+#define QM_TPC4_EML_TPC_CFG_MAX_OFFSET             0xB800
+#define QM_TPC4_EML_TPC_CFG_SECTION                0x2780
+#define mmTPC4_EML_TPC_QM_BASE                     0x7FFF842000ull
+#define TPC4_EML_TPC_QM_MAX_OFFSET                 0xD040
+#define TPC4_EML_TPC_QM_SECTION                    0x1BD000
+#define mmTPC4_EML_CS_BASE                         0x7FFF9FF000ull
+#define TPC4_EML_CS_MAX_OFFSET                     0x1000
+#define TPC4_EML_CS_SECTION                        0x1000
+#define mmTPC5_ROM_TABLE_BASE                      0x7FFFA00000ull
+#define TPC5_ROM_TABLE_MAX_OFFSET                  0x1000
+#define TPC5_ROM_TABLE_SECTION                     0x1000
+#define mmTPC5_EML_SPMU_BASE                       0x7FFFA01000ull
+#define TPC5_EML_SPMU_MAX_OFFSET                   0x1000
+#define TPC5_EML_SPMU_SECTION                      0x1000
+#define mmTPC5_EML_ETF_BASE                        0x7FFFA02000ull
+#define TPC5_EML_ETF_MAX_OFFSET                    0x1000
+#define TPC5_EML_ETF_SECTION                       0x1000
+#define mmTPC5_EML_STM_BASE                        0x7FFFA03000ull
+#define TPC5_EML_STM_MAX_OFFSET                    0x1000
+#define TPC5_EML_STM_SECTION                       0x2000
+#define mmTPC5_EML_CTI_BASE                        0x7FFFA05000ull
+#define TPC5_EML_CTI_MAX_OFFSET                    0x1000
+#define TPC5_EML_CTI_SECTION                       0x1000
+#define mmTPC5_EML_FUNNEL_BASE                     0x7FFFA06000ull
+#define TPC5_EML_FUNNEL_MAX_OFFSET                 0x1000
+#define TPC5_EML_FUNNEL_SECTION                    0x1000
+#define mmTPC5_EML_BUSMON_0_BASE                   0x7FFFA07000ull
+#define TPC5_EML_BUSMON_0_MAX_OFFSET               0x1000
+#define TPC5_EML_BUSMON_0_SECTION                  0x1000
+#define mmTPC5_EML_BUSMON_1_BASE                   0x7FFFA08000ull
+#define TPC5_EML_BUSMON_1_MAX_OFFSET               0x1000
+#define TPC5_EML_BUSMON_1_SECTION                  0x1000
+#define mmTPC5_EML_BUSMON_2_BASE                   0x7FFFA09000ull
+#define TPC5_EML_BUSMON_2_MAX_OFFSET               0x1000
+#define TPC5_EML_BUSMON_2_SECTION                  0x1000
+#define mmTPC5_EML_BUSMON_3_BASE                   0x7FFFA0A000ull
+#define TPC5_EML_BUSMON_3_MAX_OFFSET               0x1000
+#define TPC5_EML_BUSMON_3_SECTION                  0x36000
+#define mmTPC5_EML_CFG_BASE                        0x7FFFA40000ull
+#define TPC5_EML_CFG_MAX_OFFSET                    0x3380
+#define TPC5_EML_CFG_SECTION                       0x1000
+#define mmTPC5_EML_TPC_CFG_BASE                    0x7FFFA41000ull
+#define TPC5_EML_TPC_CFG_MAX_OFFSET                0xE400
+#define TPC5_EML_TPC_CFG_SECTION                   0x4000
+#define mmKERNEL_TENSOR_0_TPC5_EML_TPC_CFG_BASE    0x7FFFA41400ull
+#define KERNEL_TENSOR_0_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_0_TPC5_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_1_TPC5_EML_TPC_CFG_BASE    0x7FFFA41438ull
+#define KERNEL_TENSOR_1_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_1_TPC5_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_2_TPC5_EML_TPC_CFG_BASE    0x7FFFA41470ull
+#define KERNEL_TENSOR_2_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_2_TPC5_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_3_TPC5_EML_TPC_CFG_BASE    0x7FFFA414A8ull
+#define KERNEL_TENSOR_3_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_3_TPC5_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_4_TPC5_EML_TPC_CFG_BASE    0x7FFFA414E0ull
+#define KERNEL_TENSOR_4_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_4_TPC5_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_5_TPC5_EML_TPC_CFG_BASE    0x7FFFA41518ull
+#define KERNEL_TENSOR_5_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_5_TPC5_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_6_TPC5_EML_TPC_CFG_BASE    0x7FFFA41550ull
+#define KERNEL_TENSOR_6_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_6_TPC5_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_7_TPC5_EML_TPC_CFG_BASE    0x7FFFA41588ull
+#define KERNEL_TENSOR_7_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_7_TPC5_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_8_TPC5_EML_TPC_CFG_BASE    0x7FFFA415C0ull
+#define KERNEL_TENSOR_8_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_8_TPC5_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_9_TPC5_EML_TPC_CFG_BASE    0x7FFFA415F8ull
+#define KERNEL_TENSOR_9_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_9_TPC5_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_10_TPC5_EML_TPC_CFG_BASE   0x7FFFA41630ull
+#define KERNEL_TENSOR_10_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_10_TPC5_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_TENSOR_11_TPC5_EML_TPC_CFG_BASE   0x7FFFA41668ull
+#define KERNEL_TENSOR_11_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_11_TPC5_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_TENSOR_12_TPC5_EML_TPC_CFG_BASE   0x7FFFA416A0ull
+#define KERNEL_TENSOR_12_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_12_TPC5_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_TENSOR_13_TPC5_EML_TPC_CFG_BASE   0x7FFFA416D8ull
+#define KERNEL_TENSOR_13_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_13_TPC5_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_TENSOR_14_TPC5_EML_TPC_CFG_BASE   0x7FFFA41710ull
+#define KERNEL_TENSOR_14_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_14_TPC5_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_TENSOR_15_TPC5_EML_TPC_CFG_BASE   0x7FFFA41748ull
+#define KERNEL_TENSOR_15_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_15_TPC5_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_SYNC_OBJECT_TPC5_EML_TPC_CFG_BASE 0x7FFFA41780ull
+#define KERNEL_SYNC_OBJECT_TPC5_EML_TPC_CFG_MAX_OFFSET 0x8000
+#define KERNEL_SYNC_OBJECT_TPC5_EML_TPC_CFG_SECTION 0x8000
+#define mmKERNEL_TPC5_EML_TPC_CFG_BASE             0x7FFFA41788ull
+#define KERNEL_TPC5_EML_TPC_CFG_MAX_OFFSET         0xB800
+#define KERNEL_TPC5_EML_TPC_CFG_SECTION            0x2780
+#define mmQM_TENSOR_0_TPC5_EML_TPC_CFG_BASE        0x7FFFA41A00ull
+#define QM_TENSOR_0_TPC5_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_0_TPC5_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_1_TPC5_EML_TPC_CFG_BASE        0x7FFFA41A38ull
+#define QM_TENSOR_1_TPC5_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_1_TPC5_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_2_TPC5_EML_TPC_CFG_BASE        0x7FFFA41A70ull
+#define QM_TENSOR_2_TPC5_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_2_TPC5_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_3_TPC5_EML_TPC_CFG_BASE        0x7FFFA41AA8ull
+#define QM_TENSOR_3_TPC5_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_3_TPC5_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_4_TPC5_EML_TPC_CFG_BASE        0x7FFFA41AE0ull
+#define QM_TENSOR_4_TPC5_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_4_TPC5_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_5_TPC5_EML_TPC_CFG_BASE        0x7FFFA41B18ull
+#define QM_TENSOR_5_TPC5_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_5_TPC5_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_6_TPC5_EML_TPC_CFG_BASE        0x7FFFA41B50ull
+#define QM_TENSOR_6_TPC5_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_6_TPC5_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_7_TPC5_EML_TPC_CFG_BASE        0x7FFFA41B88ull
+#define QM_TENSOR_7_TPC5_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_7_TPC5_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_8_TPC5_EML_TPC_CFG_BASE        0x7FFFA41BC0ull
+#define QM_TENSOR_8_TPC5_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_8_TPC5_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_9_TPC5_EML_TPC_CFG_BASE        0x7FFFA41BF8ull
+#define QM_TENSOR_9_TPC5_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_9_TPC5_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_10_TPC5_EML_TPC_CFG_BASE       0x7FFFA41C30ull
+#define QM_TENSOR_10_TPC5_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_10_TPC5_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_TENSOR_11_TPC5_EML_TPC_CFG_BASE       0x7FFFA41C68ull
+#define QM_TENSOR_11_TPC5_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_11_TPC5_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_TENSOR_12_TPC5_EML_TPC_CFG_BASE       0x7FFFA41CA0ull
+#define QM_TENSOR_12_TPC5_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_12_TPC5_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_TENSOR_13_TPC5_EML_TPC_CFG_BASE       0x7FFFA41CD8ull
+#define QM_TENSOR_13_TPC5_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_13_TPC5_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_TENSOR_14_TPC5_EML_TPC_CFG_BASE       0x7FFFA41D10ull
+#define QM_TENSOR_14_TPC5_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_14_TPC5_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_TENSOR_15_TPC5_EML_TPC_CFG_BASE       0x7FFFA41D48ull
+#define QM_TENSOR_15_TPC5_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_15_TPC5_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_SYNC_OBJECT_TPC5_EML_TPC_CFG_BASE     0x7FFFA41D80ull
+#define QM_SYNC_OBJECT_TPC5_EML_TPC_CFG_MAX_OFFSET 0x8000
+#define QM_SYNC_OBJECT_TPC5_EML_TPC_CFG_SECTION    0x8000
+#define mmQM_TPC5_EML_TPC_CFG_BASE                 0x7FFFA41D88ull
+#define QM_TPC5_EML_TPC_CFG_MAX_OFFSET             0xB800
+#define QM_TPC5_EML_TPC_CFG_SECTION                0x2780
+#define mmTPC5_EML_TPC_QM_BASE                     0x7FFFA42000ull
+#define TPC5_EML_TPC_QM_MAX_OFFSET                 0xD040
+#define TPC5_EML_TPC_QM_SECTION                    0x1BD000
+#define mmTPC5_EML_CS_BASE                         0x7FFFBFF000ull
+#define TPC5_EML_CS_MAX_OFFSET                     0x1000
+#define TPC5_EML_CS_SECTION                        0x1000
+#define mmTPC6_ROM_TABLE_BASE                      0x7FFFC00000ull
+#define TPC6_ROM_TABLE_MAX_OFFSET                  0x1000
+#define TPC6_ROM_TABLE_SECTION                     0x1000
+#define mmTPC6_EML_SPMU_BASE                       0x7FFFC01000ull
+#define TPC6_EML_SPMU_MAX_OFFSET                   0x1000
+#define TPC6_EML_SPMU_SECTION                      0x1000
+#define mmTPC6_EML_ETF_BASE                        0x7FFFC02000ull
+#define TPC6_EML_ETF_MAX_OFFSET                    0x1000
+#define TPC6_EML_ETF_SECTION                       0x1000
+#define mmTPC6_EML_STM_BASE                        0x7FFFC03000ull
+#define TPC6_EML_STM_MAX_OFFSET                    0x1000
+#define TPC6_EML_STM_SECTION                       0x2000
+#define mmTPC6_EML_CTI_BASE                        0x7FFFC05000ull
+#define TPC6_EML_CTI_MAX_OFFSET                    0x1000
+#define TPC6_EML_CTI_SECTION                       0x1000
+#define mmTPC6_EML_FUNNEL_BASE                     0x7FFFC06000ull
+#define TPC6_EML_FUNNEL_MAX_OFFSET                 0x1000
+#define TPC6_EML_FUNNEL_SECTION                    0x1000
+#define mmTPC6_EML_BUSMON_0_BASE                   0x7FFFC07000ull
+#define TPC6_EML_BUSMON_0_MAX_OFFSET               0x1000
+#define TPC6_EML_BUSMON_0_SECTION                  0x1000
+#define mmTPC6_EML_BUSMON_1_BASE                   0x7FFFC08000ull
+#define TPC6_EML_BUSMON_1_MAX_OFFSET               0x1000
+#define TPC6_EML_BUSMON_1_SECTION                  0x1000
+#define mmTPC6_EML_BUSMON_2_BASE                   0x7FFFC09000ull
+#define TPC6_EML_BUSMON_2_MAX_OFFSET               0x1000
+#define TPC6_EML_BUSMON_2_SECTION                  0x1000
+#define mmTPC6_EML_BUSMON_3_BASE                   0x7FFFC0A000ull
+#define TPC6_EML_BUSMON_3_MAX_OFFSET               0x1000
+#define TPC6_EML_BUSMON_3_SECTION                  0x36000
+#define mmTPC6_EML_CFG_BASE                        0x7FFFC40000ull
+#define TPC6_EML_CFG_MAX_OFFSET                    0x3380
+#define TPC6_EML_CFG_SECTION                       0x1000
+#define mmTPC6_EML_TPC_CFG_BASE                    0x7FFFC41000ull
+#define TPC6_EML_TPC_CFG_MAX_OFFSET                0xE400
+#define TPC6_EML_TPC_CFG_SECTION                   0x4000
+#define mmKERNEL_TENSOR_0_TPC6_EML_TPC_CFG_BASE    0x7FFFC41400ull
+#define KERNEL_TENSOR_0_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_0_TPC6_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_1_TPC6_EML_TPC_CFG_BASE    0x7FFFC41438ull
+#define KERNEL_TENSOR_1_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_1_TPC6_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_2_TPC6_EML_TPC_CFG_BASE    0x7FFFC41470ull
+#define KERNEL_TENSOR_2_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_2_TPC6_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_3_TPC6_EML_TPC_CFG_BASE    0x7FFFC414A8ull
+#define KERNEL_TENSOR_3_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_3_TPC6_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_4_TPC6_EML_TPC_CFG_BASE    0x7FFFC414E0ull
+#define KERNEL_TENSOR_4_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_4_TPC6_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_5_TPC6_EML_TPC_CFG_BASE    0x7FFFC41518ull
+#define KERNEL_TENSOR_5_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_5_TPC6_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_6_TPC6_EML_TPC_CFG_BASE    0x7FFFC41550ull
+#define KERNEL_TENSOR_6_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_6_TPC6_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_7_TPC6_EML_TPC_CFG_BASE    0x7FFFC41588ull
+#define KERNEL_TENSOR_7_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_7_TPC6_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_8_TPC6_EML_TPC_CFG_BASE    0x7FFFC415C0ull
+#define KERNEL_TENSOR_8_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_8_TPC6_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_9_TPC6_EML_TPC_CFG_BASE    0x7FFFC415F8ull
+#define KERNEL_TENSOR_9_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_9_TPC6_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_10_TPC6_EML_TPC_CFG_BASE   0x7FFFC41630ull
+#define KERNEL_TENSOR_10_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_10_TPC6_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_TENSOR_11_TPC6_EML_TPC_CFG_BASE   0x7FFFC41668ull
+#define KERNEL_TENSOR_11_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_11_TPC6_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_TENSOR_12_TPC6_EML_TPC_CFG_BASE   0x7FFFC416A0ull
+#define KERNEL_TENSOR_12_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_12_TPC6_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_TENSOR_13_TPC6_EML_TPC_CFG_BASE   0x7FFFC416D8ull
+#define KERNEL_TENSOR_13_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_13_TPC6_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_TENSOR_14_TPC6_EML_TPC_CFG_BASE   0x7FFFC41710ull
+#define KERNEL_TENSOR_14_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_14_TPC6_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_TENSOR_15_TPC6_EML_TPC_CFG_BASE   0x7FFFC41748ull
+#define KERNEL_TENSOR_15_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_15_TPC6_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_SYNC_OBJECT_TPC6_EML_TPC_CFG_BASE 0x7FFFC41780ull
+#define KERNEL_SYNC_OBJECT_TPC6_EML_TPC_CFG_MAX_OFFSET 0x8000
+#define KERNEL_SYNC_OBJECT_TPC6_EML_TPC_CFG_SECTION 0x8000
+#define mmKERNEL_TPC6_EML_TPC_CFG_BASE             0x7FFFC41788ull
+#define KERNEL_TPC6_EML_TPC_CFG_MAX_OFFSET         0xB800
+#define KERNEL_TPC6_EML_TPC_CFG_SECTION            0x2780
+#define mmQM_TENSOR_0_TPC6_EML_TPC_CFG_BASE        0x7FFFC41A00ull
+#define QM_TENSOR_0_TPC6_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_0_TPC6_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_1_TPC6_EML_TPC_CFG_BASE        0x7FFFC41A38ull
+#define QM_TENSOR_1_TPC6_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_1_TPC6_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_2_TPC6_EML_TPC_CFG_BASE        0x7FFFC41A70ull
+#define QM_TENSOR_2_TPC6_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_2_TPC6_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_3_TPC6_EML_TPC_CFG_BASE        0x7FFFC41AA8ull
+#define QM_TENSOR_3_TPC6_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_3_TPC6_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_4_TPC6_EML_TPC_CFG_BASE        0x7FFFC41AE0ull
+#define QM_TENSOR_4_TPC6_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_4_TPC6_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_5_TPC6_EML_TPC_CFG_BASE        0x7FFFC41B18ull
+#define QM_TENSOR_5_TPC6_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_5_TPC6_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_6_TPC6_EML_TPC_CFG_BASE        0x7FFFC41B50ull
+#define QM_TENSOR_6_TPC6_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_6_TPC6_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_7_TPC6_EML_TPC_CFG_BASE        0x7FFFC41B88ull
+#define QM_TENSOR_7_TPC6_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_7_TPC6_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_8_TPC6_EML_TPC_CFG_BASE        0x7FFFC41BC0ull
+#define QM_TENSOR_8_TPC6_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_8_TPC6_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_9_TPC6_EML_TPC_CFG_BASE        0x7FFFC41BF8ull
+#define QM_TENSOR_9_TPC6_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_9_TPC6_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_10_TPC6_EML_TPC_CFG_BASE       0x7FFFC41C30ull
+#define QM_TENSOR_10_TPC6_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_10_TPC6_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_TENSOR_11_TPC6_EML_TPC_CFG_BASE       0x7FFFC41C68ull
+#define QM_TENSOR_11_TPC6_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_11_TPC6_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_TENSOR_12_TPC6_EML_TPC_CFG_BASE       0x7FFFC41CA0ull
+#define QM_TENSOR_12_TPC6_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_12_TPC6_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_TENSOR_13_TPC6_EML_TPC_CFG_BASE       0x7FFFC41CD8ull
+#define QM_TENSOR_13_TPC6_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_13_TPC6_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_TENSOR_14_TPC6_EML_TPC_CFG_BASE       0x7FFFC41D10ull
+#define QM_TENSOR_14_TPC6_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_14_TPC6_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_TENSOR_15_TPC6_EML_TPC_CFG_BASE       0x7FFFC41D48ull
+#define QM_TENSOR_15_TPC6_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_15_TPC6_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_SYNC_OBJECT_TPC6_EML_TPC_CFG_BASE     0x7FFFC41D80ull
+#define QM_SYNC_OBJECT_TPC6_EML_TPC_CFG_MAX_OFFSET 0x8000
+#define QM_SYNC_OBJECT_TPC6_EML_TPC_CFG_SECTION    0x8000
+#define mmQM_TPC6_EML_TPC_CFG_BASE                 0x7FFFC41D88ull
+#define QM_TPC6_EML_TPC_CFG_MAX_OFFSET             0xB800
+#define QM_TPC6_EML_TPC_CFG_SECTION                0x2780
+#define mmTPC6_EML_TPC_QM_BASE                     0x7FFFC42000ull
+#define TPC6_EML_TPC_QM_MAX_OFFSET                 0xD040
+#define TPC6_EML_TPC_QM_SECTION                    0x1BD000
+#define mmTPC6_EML_CS_BASE                         0x7FFFDFF000ull
+#define TPC6_EML_CS_MAX_OFFSET                     0x1000
+#define TPC6_EML_CS_SECTION                        0x1000
+#define mmTPC7_ROM_TABLE_BASE                      0x7FFFE00000ull
+#define TPC7_ROM_TABLE_MAX_OFFSET                  0x1000
+#define TPC7_ROM_TABLE_SECTION                     0x1000
+#define mmTPC7_EML_SPMU_BASE                       0x7FFFE01000ull
+#define TPC7_EML_SPMU_MAX_OFFSET                   0x1000
+#define TPC7_EML_SPMU_SECTION                      0x1000
+#define mmTPC7_EML_ETF_BASE                        0x7FFFE02000ull
+#define TPC7_EML_ETF_MAX_OFFSET                    0x1000
+#define TPC7_EML_ETF_SECTION                       0x1000
+#define mmTPC7_EML_STM_BASE                        0x7FFFE03000ull
+#define TPC7_EML_STM_MAX_OFFSET                    0x1000
+#define TPC7_EML_STM_SECTION                       0x2000
+#define mmTPC7_EML_CTI_BASE                        0x7FFFE05000ull
+#define TPC7_EML_CTI_MAX_OFFSET                    0x1000
+#define TPC7_EML_CTI_SECTION                       0x1000
+#define mmTPC7_EML_FUNNEL_BASE                     0x7FFFE06000ull
+#define TPC7_EML_FUNNEL_MAX_OFFSET                 0x1000
+#define TPC7_EML_FUNNEL_SECTION                    0x1000
+#define mmTPC7_EML_BUSMON_0_BASE                   0x7FFFE07000ull
+#define TPC7_EML_BUSMON_0_MAX_OFFSET               0x1000
+#define TPC7_EML_BUSMON_0_SECTION                  0x1000
+#define mmTPC7_EML_BUSMON_1_BASE                   0x7FFFE08000ull
+#define TPC7_EML_BUSMON_1_MAX_OFFSET               0x1000
+#define TPC7_EML_BUSMON_1_SECTION                  0x1000
+#define mmTPC7_EML_BUSMON_2_BASE                   0x7FFFE09000ull
+#define TPC7_EML_BUSMON_2_MAX_OFFSET               0x1000
+#define TPC7_EML_BUSMON_2_SECTION                  0x1000
+#define mmTPC7_EML_BUSMON_3_BASE                   0x7FFFE0A000ull
+#define TPC7_EML_BUSMON_3_MAX_OFFSET               0x1000
+#define TPC7_EML_BUSMON_3_SECTION                  0x36000
+#define mmTPC7_EML_CFG_BASE                        0x7FFFE40000ull
+#define TPC7_EML_CFG_MAX_OFFSET                    0x3380
+#define TPC7_EML_CFG_SECTION                       0x1000
+#define mmTPC7_EML_TPC_CFG_BASE                    0x7FFFE41000ull
+#define TPC7_EML_TPC_CFG_MAX_OFFSET                0xE400
+#define TPC7_EML_TPC_CFG_SECTION                   0x4000
+#define mmKERNEL_TENSOR_0_TPC7_EML_TPC_CFG_BASE    0x7FFFE41400ull
+#define KERNEL_TENSOR_0_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_0_TPC7_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_1_TPC7_EML_TPC_CFG_BASE    0x7FFFE41438ull
+#define KERNEL_TENSOR_1_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_1_TPC7_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_2_TPC7_EML_TPC_CFG_BASE    0x7FFFE41470ull
+#define KERNEL_TENSOR_2_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_2_TPC7_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_3_TPC7_EML_TPC_CFG_BASE    0x7FFFE414A8ull
+#define KERNEL_TENSOR_3_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_3_TPC7_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_4_TPC7_EML_TPC_CFG_BASE    0x7FFFE414E0ull
+#define KERNEL_TENSOR_4_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_4_TPC7_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_5_TPC7_EML_TPC_CFG_BASE    0x7FFFE41518ull
+#define KERNEL_TENSOR_5_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_5_TPC7_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_6_TPC7_EML_TPC_CFG_BASE    0x7FFFE41550ull
+#define KERNEL_TENSOR_6_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_6_TPC7_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_7_TPC7_EML_TPC_CFG_BASE    0x7FFFE41588ull
+#define KERNEL_TENSOR_7_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_7_TPC7_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_8_TPC7_EML_TPC_CFG_BASE    0x7FFFE415C0ull
+#define KERNEL_TENSOR_8_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_8_TPC7_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_9_TPC7_EML_TPC_CFG_BASE    0x7FFFE415F8ull
+#define KERNEL_TENSOR_9_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_9_TPC7_EML_TPC_CFG_SECTION   0x3800
+#define mmKERNEL_TENSOR_10_TPC7_EML_TPC_CFG_BASE   0x7FFFE41630ull
+#define KERNEL_TENSOR_10_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_10_TPC7_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_TENSOR_11_TPC7_EML_TPC_CFG_BASE   0x7FFFE41668ull
+#define KERNEL_TENSOR_11_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_11_TPC7_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_TENSOR_12_TPC7_EML_TPC_CFG_BASE   0x7FFFE416A0ull
+#define KERNEL_TENSOR_12_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_12_TPC7_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_TENSOR_13_TPC7_EML_TPC_CFG_BASE   0x7FFFE416D8ull
+#define KERNEL_TENSOR_13_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_13_TPC7_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_TENSOR_14_TPC7_EML_TPC_CFG_BASE   0x7FFFE41710ull
+#define KERNEL_TENSOR_14_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_14_TPC7_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_TENSOR_15_TPC7_EML_TPC_CFG_BASE   0x7FFFE41748ull
+#define KERNEL_TENSOR_15_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_15_TPC7_EML_TPC_CFG_SECTION  0x3800
+#define mmKERNEL_SYNC_OBJECT_TPC7_EML_TPC_CFG_BASE 0x7FFFE41780ull
+#define KERNEL_SYNC_OBJECT_TPC7_EML_TPC_CFG_MAX_OFFSET 0x8000
+#define KERNEL_SYNC_OBJECT_TPC7_EML_TPC_CFG_SECTION 0x8000
+#define mmKERNEL_TPC7_EML_TPC_CFG_BASE             0x7FFFE41788ull
+#define KERNEL_TPC7_EML_TPC_CFG_MAX_OFFSET         0xB800
+#define KERNEL_TPC7_EML_TPC_CFG_SECTION            0x2780
+#define mmQM_TENSOR_0_TPC7_EML_TPC_CFG_BASE        0x7FFFE41A00ull
+#define QM_TENSOR_0_TPC7_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_0_TPC7_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_1_TPC7_EML_TPC_CFG_BASE        0x7FFFE41A38ull
+#define QM_TENSOR_1_TPC7_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_1_TPC7_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_2_TPC7_EML_TPC_CFG_BASE        0x7FFFE41A70ull
+#define QM_TENSOR_2_TPC7_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_2_TPC7_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_3_TPC7_EML_TPC_CFG_BASE        0x7FFFE41AA8ull
+#define QM_TENSOR_3_TPC7_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_3_TPC7_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_4_TPC7_EML_TPC_CFG_BASE        0x7FFFE41AE0ull
+#define QM_TENSOR_4_TPC7_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_4_TPC7_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_5_TPC7_EML_TPC_CFG_BASE        0x7FFFE41B18ull
+#define QM_TENSOR_5_TPC7_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_5_TPC7_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_6_TPC7_EML_TPC_CFG_BASE        0x7FFFE41B50ull
+#define QM_TENSOR_6_TPC7_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_6_TPC7_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_7_TPC7_EML_TPC_CFG_BASE        0x7FFFE41B88ull
+#define QM_TENSOR_7_TPC7_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_7_TPC7_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_8_TPC7_EML_TPC_CFG_BASE        0x7FFFE41BC0ull
+#define QM_TENSOR_8_TPC7_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_8_TPC7_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_9_TPC7_EML_TPC_CFG_BASE        0x7FFFE41BF8ull
+#define QM_TENSOR_9_TPC7_EML_TPC_CFG_MAX_OFFSET    0x3800
+#define QM_TENSOR_9_TPC7_EML_TPC_CFG_SECTION       0x3800
+#define mmQM_TENSOR_10_TPC7_EML_TPC_CFG_BASE       0x7FFFE41C30ull
+#define QM_TENSOR_10_TPC7_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_10_TPC7_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_TENSOR_11_TPC7_EML_TPC_CFG_BASE       0x7FFFE41C68ull
+#define QM_TENSOR_11_TPC7_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_11_TPC7_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_TENSOR_12_TPC7_EML_TPC_CFG_BASE       0x7FFFE41CA0ull
+#define QM_TENSOR_12_TPC7_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_12_TPC7_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_TENSOR_13_TPC7_EML_TPC_CFG_BASE       0x7FFFE41CD8ull
+#define QM_TENSOR_13_TPC7_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_13_TPC7_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_TENSOR_14_TPC7_EML_TPC_CFG_BASE       0x7FFFE41D10ull
+#define QM_TENSOR_14_TPC7_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_14_TPC7_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_TENSOR_15_TPC7_EML_TPC_CFG_BASE       0x7FFFE41D48ull
+#define QM_TENSOR_15_TPC7_EML_TPC_CFG_MAX_OFFSET   0x3800
+#define QM_TENSOR_15_TPC7_EML_TPC_CFG_SECTION      0x3800
+#define mmQM_SYNC_OBJECT_TPC7_EML_TPC_CFG_BASE     0x7FFFE41D80ull
+#define QM_SYNC_OBJECT_TPC7_EML_TPC_CFG_MAX_OFFSET 0x8000
+#define QM_SYNC_OBJECT_TPC7_EML_TPC_CFG_SECTION    0x8000
+#define mmQM_TPC7_EML_TPC_CFG_BASE                 0x7FFFE41D88ull
+#define QM_TPC7_EML_TPC_CFG_MAX_OFFSET             0xB800
+#define QM_TPC7_EML_TPC_CFG_SECTION                0x2780
+#define mmTPC7_EML_TPC_QM_BASE                     0x7FFFE42000ull
+#define TPC7_EML_TPC_QM_MAX_OFFSET                 0xD040
+#define TPC7_EML_TPC_QM_SECTION                    0x1BD000
+#define mmTPC7_EML_CS_BASE                         0x7FFFFFF000ull
+#define TPC7_EML_CS_MAX_OFFSET                     0x1000
+
+#endif /* GAUDI_BLOCKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/gaudi_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/gaudi_regs.h
new file mode 100644
index 000000000000..23ee8691db46
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/gaudi_regs.h
@@ -0,0 +1,325 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+#ifndef ASIC_REG_GAUDI_REGS_H_
+#define ASIC_REG_GAUDI_REGS_H_
+
+#include "gaudi_blocks.h"
+#include "psoc_global_conf_regs.h"
+#include "psoc_timestamp_regs.h"
+#include "cpu_if_regs.h"
+#include "mmu_up_regs.h"
+#include "stlb_regs.h"
+#include "dma0_qm_regs.h"
+#include "dma1_qm_regs.h"
+#include "dma2_qm_regs.h"
+#include "dma3_qm_regs.h"
+#include "dma4_qm_regs.h"
+#include "dma5_qm_regs.h"
+#include "dma6_qm_regs.h"
+#include "dma7_qm_regs.h"
+#include "dma0_core_regs.h"
+#include "dma1_core_regs.h"
+#include "dma2_core_regs.h"
+#include "dma3_core_regs.h"
+#include "dma4_core_regs.h"
+#include "dma5_core_regs.h"
+#include "dma6_core_regs.h"
+#include "dma7_core_regs.h"
+#include "mme0_ctrl_regs.h"
+#include "mme1_ctrl_regs.h"
+#include "mme2_ctrl_regs.h"
+#include "mme3_ctrl_regs.h"
+#include "mme0_qm_regs.h"
+#include "mme2_qm_regs.h"
+#include "tpc0_cfg_regs.h"
+#include "tpc1_cfg_regs.h"
+#include "tpc2_cfg_regs.h"
+#include "tpc3_cfg_regs.h"
+#include "tpc4_cfg_regs.h"
+#include "tpc5_cfg_regs.h"
+#include "tpc6_cfg_regs.h"
+#include "tpc7_cfg_regs.h"
+#include "tpc0_qm_regs.h"
+#include "tpc1_qm_regs.h"
+#include "tpc2_qm_regs.h"
+#include "tpc3_qm_regs.h"
+#include "tpc4_qm_regs.h"
+#include "tpc5_qm_regs.h"
+#include "tpc6_qm_regs.h"
+#include "tpc7_qm_regs.h"
+#include "dma_if_e_n_down_ch0_regs.h"
+#include "dma_if_e_n_down_ch1_regs.h"
+#include "dma_if_e_s_down_ch0_regs.h"
+#include "dma_if_e_s_down_ch1_regs.h"
+#include "dma_if_w_n_down_ch0_regs.h"
+#include "dma_if_w_n_down_ch1_regs.h"
+#include "dma_if_w_s_down_ch0_regs.h"
+#include "dma_if_w_s_down_ch1_regs.h"
+#include "dma_if_e_n_regs.h"
+#include "dma_if_e_s_regs.h"
+#include "dma_if_w_n_regs.h"
+#include "dma_if_w_s_regs.h"
+#include "nif_rtr_ctrl_0_regs.h"
+#include "nif_rtr_ctrl_1_regs.h"
+#include "nif_rtr_ctrl_2_regs.h"
+#include "nif_rtr_ctrl_3_regs.h"
+#include "nif_rtr_ctrl_4_regs.h"
+#include "nif_rtr_ctrl_5_regs.h"
+#include "nif_rtr_ctrl_6_regs.h"
+#include "nif_rtr_ctrl_7_regs.h"
+#include "sif_rtr_ctrl_0_regs.h"
+#include "sif_rtr_ctrl_1_regs.h"
+#include "sif_rtr_ctrl_2_regs.h"
+#include "sif_rtr_ctrl_3_regs.h"
+#include "sif_rtr_ctrl_4_regs.h"
+#include "sif_rtr_ctrl_5_regs.h"
+#include "sif_rtr_ctrl_6_regs.h"
+#include "sif_rtr_ctrl_7_regs.h"
+#include "psoc_etr_regs.h"
+#include "psoc_cpu_pll_regs.h"
+
+#include "dma0_qm_masks.h"
+#include "mme0_qm_masks.h"
+#include "tpc0_qm_masks.h"
+#include "dma0_core_masks.h"
+#include "tpc0_cfg_masks.h"
+#include "psoc_global_conf_masks.h"
+
+#include "nic0_qm0_regs.h"
+#include "nic1_qm0_regs.h"
+#include "nic2_qm0_regs.h"
+#include "nic3_qm0_regs.h"
+#include "nic4_qm0_regs.h"
+#include "nic0_qm1_regs.h"
+#include "nic1_qm1_regs.h"
+#include "nic2_qm1_regs.h"
+#include "nic3_qm1_regs.h"
+#include "nic4_qm1_regs.h"
+
+#include "nic0_qm0_masks.h"
+
+#define GAUDI_ECC_MEM_SEL_OFFSET		0xF18
+#define GAUDI_ECC_ADDRESS_OFFSET		0xF1C
+#define GAUDI_ECC_SYNDROME_OFFSET		0xF20
+#define GAUDI_ECC_MEM_INFO_CLR_OFFSET		0xF28
+#define GAUDI_ECC_MEM_INFO_CLR_SERR_MASK	BIT(8)
+#define GAUDI_ECC_MEM_INFO_CLR_DERR_MASK	BIT(9)
+#define GAUDI_ECC_SERR0_OFFSET			0xF30
+#define GAUDI_ECC_DERR0_OFFSET			0xF40
+
+#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0                     0x492000
+#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0               0x494000
+#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRH_0               0x494800
+#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_DATA_0                0x495000
+#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0                     0x495800
+#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0                  0x496000
+#define mmSYNC_MNGR_E_S_SYNC_MNGR_OBJS_SOB_OBJ_0                     0x4B2000
+#define mmSYNC_MNGR_E_S_SYNC_MNGR_OBJS_MON_STATUS_0                  0x4B6000
+#define mmSYNC_MNGR_W_N_SYNC_MNGR_OBJS_SOB_OBJ_0                     0x4D2000
+#define mmSYNC_MNGR_W_N_SYNC_MNGR_OBJS_MON_STATUS_0                  0x4D6000
+#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0                     0x4F2000
+#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_1                     0x4F2004
+#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_2047                  0x4F3FFC
+#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0               0x4F4000
+#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRH_0               0x4F4800
+#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_DATA_0                0x4F5000
+#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_ARM_0                     0x4F5800
+#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_0                  0x4F6000
+#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_511                0x4F67FC
+
+#define mmSIF_RTR_0_LBW_RANGE_PROT_HIT_AW                            0x300400
+#define mmSIF_RTR_1_LBW_RANGE_PROT_HIT_AW                            0x310400
+#define mmSIF_RTR_2_LBW_RANGE_PROT_HIT_AW                            0x320400
+#define mmSIF_RTR_3_LBW_RANGE_PROT_HIT_AW                            0x330400
+#define mmSIF_RTR_4_LBW_RANGE_PROT_HIT_AW                            0x340400
+#define mmSIF_RTR_5_LBW_RANGE_PROT_HIT_AW                            0x350400
+#define mmSIF_RTR_6_LBW_RANGE_PROT_HIT_AW                            0x360400
+#define mmSIF_RTR_7_LBW_RANGE_PROT_HIT_AW                            0x370400
+
+#define mmSIF_RTR_0_LBW_RANGE_PROT_HIT_AR                            0x300490
+#define mmSIF_RTR_1_LBW_RANGE_PROT_HIT_AR                            0x310490
+#define mmSIF_RTR_2_LBW_RANGE_PROT_HIT_AR                            0x320490
+#define mmSIF_RTR_3_LBW_RANGE_PROT_HIT_AR                            0x330490
+#define mmSIF_RTR_4_LBW_RANGE_PROT_HIT_AR                            0x340490
+#define mmSIF_RTR_5_LBW_RANGE_PROT_HIT_AR                            0x350490
+#define mmSIF_RTR_6_LBW_RANGE_PROT_HIT_AR                            0x360490
+#define mmSIF_RTR_7_LBW_RANGE_PROT_HIT_AR                            0x370490
+
+#define mmSIF_RTR_0_LBW_RANGE_PROT_MIN_AW_0                          0x300410
+#define mmSIF_RTR_1_LBW_RANGE_PROT_MIN_AW_0                          0x310410
+#define mmSIF_RTR_2_LBW_RANGE_PROT_MIN_AW_0                          0x320410
+#define mmSIF_RTR_3_LBW_RANGE_PROT_MIN_AW_0                          0x330410
+#define mmSIF_RTR_4_LBW_RANGE_PROT_MIN_AW_0                          0x340410
+#define mmSIF_RTR_5_LBW_RANGE_PROT_MIN_AW_0                          0x350410
+#define mmSIF_RTR_6_LBW_RANGE_PROT_MIN_AW_0                          0x360410
+#define mmSIF_RTR_7_LBW_RANGE_PROT_MIN_AW_0                          0x370410
+
+#define mmSIF_RTR_0_LBW_RANGE_PROT_MAX_AW_0                          0x300450
+#define mmSIF_RTR_1_LBW_RANGE_PROT_MAX_AW_0                          0x310450
+#define mmSIF_RTR_2_LBW_RANGE_PROT_MAX_AW_0                          0x320450
+#define mmSIF_RTR_3_LBW_RANGE_PROT_MAX_AW_0                          0x330450
+#define mmSIF_RTR_4_LBW_RANGE_PROT_MAX_AW_0                          0x340450
+#define mmSIF_RTR_5_LBW_RANGE_PROT_MAX_AW_0                          0x350450
+#define mmSIF_RTR_6_LBW_RANGE_PROT_MAX_AW_0                          0x360450
+#define mmSIF_RTR_7_LBW_RANGE_PROT_MAX_AW_0                          0x370450
+
+#define mmSIF_RTR_0_LBW_RANGE_PROT_MIN_AR_0                          0x3004A0
+#define mmSIF_RTR_1_LBW_RANGE_PROT_MIN_AR_0                          0x3104A0
+#define mmSIF_RTR_2_LBW_RANGE_PROT_MIN_AR_0                          0x3204A0
+#define mmSIF_RTR_3_LBW_RANGE_PROT_MIN_AR_0                          0x3304A0
+#define mmSIF_RTR_4_LBW_RANGE_PROT_MIN_AR_0                          0x3404A0
+#define mmSIF_RTR_5_LBW_RANGE_PROT_MIN_AR_0                          0x3504A0
+#define mmSIF_RTR_6_LBW_RANGE_PROT_MIN_AR_0                          0x3604A0
+#define mmSIF_RTR_7_LBW_RANGE_PROT_MIN_AR_0                          0x3704A0
+
+#define mmSIF_RTR_0_LBW_RANGE_PROT_MAX_AR_0                          0x3004E0
+#define mmSIF_RTR_1_LBW_RANGE_PROT_MAX_AR_0                          0x3104E0
+#define mmSIF_RTR_2_LBW_RANGE_PROT_MAX_AR_0                          0x3204E0
+#define mmSIF_RTR_3_LBW_RANGE_PROT_MAX_AR_0                          0x3304E0
+#define mmSIF_RTR_4_LBW_RANGE_PROT_MAX_AR_0                          0x3404E0
+#define mmSIF_RTR_5_LBW_RANGE_PROT_MAX_AR_0                          0x3504E0
+#define mmSIF_RTR_6_LBW_RANGE_PROT_MAX_AR_0                          0x3604E0
+#define mmSIF_RTR_7_LBW_RANGE_PROT_MAX_AR_0                          0x3704E0
+
+#define mmNIF_RTR_0_LBW_RANGE_PROT_HIT_AW                            0x380400
+#define mmNIF_RTR_1_LBW_RANGE_PROT_HIT_AW                            0x390400
+#define mmNIF_RTR_2_LBW_RANGE_PROT_HIT_AW                            0x3A0400
+#define mmNIF_RTR_3_LBW_RANGE_PROT_HIT_AW                            0x3B0400
+#define mmNIF_RTR_4_LBW_RANGE_PROT_HIT_AW                            0x3C0400
+#define mmNIF_RTR_5_LBW_RANGE_PROT_HIT_AW                            0x3D0400
+#define mmNIF_RTR_6_LBW_RANGE_PROT_HIT_AW                            0x3E0400
+#define mmNIF_RTR_7_LBW_RANGE_PROT_HIT_AW                            0x3F0400
+
+#define mmNIF_RTR_0_LBW_RANGE_PROT_HIT_AR                            0x380490
+#define mmNIF_RTR_1_LBW_RANGE_PROT_HIT_AR                            0x390490
+#define mmNIF_RTR_2_LBW_RANGE_PROT_HIT_AR                            0x3A0490
+#define mmNIF_RTR_3_LBW_RANGE_PROT_HIT_AR                            0x3B0490
+#define mmNIF_RTR_4_LBW_RANGE_PROT_HIT_AR                            0x3C0490
+#define mmNIF_RTR_5_LBW_RANGE_PROT_HIT_AR                            0x3D0490
+#define mmNIF_RTR_6_LBW_RANGE_PROT_HIT_AR                            0x3E0490
+#define mmNIF_RTR_7_LBW_RANGE_PROT_HIT_AR                            0x3F0490
+
+#define mmNIF_RTR_0_LBW_RANGE_PROT_MIN_AW_0                          0x380410
+#define mmNIF_RTR_1_LBW_RANGE_PROT_MIN_AW_0                          0x390410
+#define mmNIF_RTR_2_LBW_RANGE_PROT_MIN_AW_0                          0x3A0410
+#define mmNIF_RTR_3_LBW_RANGE_PROT_MIN_AW_0                          0x3B0410
+#define mmNIF_RTR_4_LBW_RANGE_PROT_MIN_AW_0                          0x3C0410
+#define mmNIF_RTR_5_LBW_RANGE_PROT_MIN_AW_0                          0x3D0410
+#define mmNIF_RTR_6_LBW_RANGE_PROT_MIN_AW_0                          0x3E0410
+#define mmNIF_RTR_7_LBW_RANGE_PROT_MIN_AW_0                          0x3F0410
+
+#define mmNIF_RTR_0_LBW_RANGE_PROT_MAX_AW_0                          0x380450
+#define mmNIF_RTR_1_LBW_RANGE_PROT_MAX_AW_0                          0x390450
+#define mmNIF_RTR_2_LBW_RANGE_PROT_MAX_AW_0                          0x3A0450
+#define mmNIF_RTR_3_LBW_RANGE_PROT_MAX_AW_0                          0x3B0450
+#define mmNIF_RTR_4_LBW_RANGE_PROT_MAX_AW_0                          0x3C0450
+#define mmNIF_RTR_5_LBW_RANGE_PROT_MAX_AW_0                          0x3D0450
+#define mmNIF_RTR_6_LBW_RANGE_PROT_MAX_AW_0                          0x3E0450
+#define mmNIF_RTR_7_LBW_RANGE_PROT_MAX_AW_0                          0x3F0450
+
+#define mmNIF_RTR_0_LBW_RANGE_PROT_MIN_AR_0                          0x3804A0
+#define mmNIF_RTR_1_LBW_RANGE_PROT_MIN_AR_0                          0x3904A0
+#define mmNIF_RTR_2_LBW_RANGE_PROT_MIN_AR_0                          0x3A04A0
+#define mmNIF_RTR_3_LBW_RANGE_PROT_MIN_AR_0                          0x3B04A0
+#define mmNIF_RTR_4_LBW_RANGE_PROT_MIN_AR_0                          0x3C04A0
+#define mmNIF_RTR_5_LBW_RANGE_PROT_MIN_AR_0                          0x3D04A0
+#define mmNIF_RTR_6_LBW_RANGE_PROT_MIN_AR_0                          0x3E04A0
+#define mmNIF_RTR_7_LBW_RANGE_PROT_MIN_AR_0                          0x3F04A0
+
+#define mmNIF_RTR_0_LBW_RANGE_PROT_MAX_AR_0                          0x3804E0
+#define mmNIF_RTR_1_LBW_RANGE_PROT_MAX_AR_0                          0x3904E0
+#define mmNIF_RTR_2_LBW_RANGE_PROT_MAX_AR_0                          0x3A04E0
+#define mmNIF_RTR_3_LBW_RANGE_PROT_MAX_AR_0                          0x3B04E0
+#define mmNIF_RTR_4_LBW_RANGE_PROT_MAX_AR_0                          0x3C04E0
+#define mmNIF_RTR_5_LBW_RANGE_PROT_MAX_AR_0                          0x3D04E0
+#define mmNIF_RTR_6_LBW_RANGE_PROT_MAX_AR_0                          0x3E04E0
+#define mmNIF_RTR_7_LBW_RANGE_PROT_MAX_AR_0                          0x3F04E0
+
+#define mmDMA_IF_W_S_DOWN_RSP_MID_WGHT_0                             0x489030
+#define mmDMA_IF_W_S_DOWN_RSP_MID_WGHT_1                             0x489034
+
+#define mmDMA_IF_E_S_DOWN_RSP_MID_WGHT_0                             0x4A9030
+#define mmDMA_IF_E_S_DOWN_RSP_MID_WGHT_1                             0x4A9034
+
+#define mmDMA_IF_W_N_DOWN_RSP_MID_WGHT_0                             0x4C9030
+#define mmDMA_IF_W_N_DOWN_RSP_MID_WGHT_1                             0x4C9034
+
+#define mmDMA_IF_E_N_DOWN_RSP_MID_WGHT_0                             0x4E9030
+#define mmDMA_IF_E_N_DOWN_RSP_MID_WGHT_1                             0x4E9034
+
+#define mmMME1_QM_GLBL_CFG0                                          0xE8000
+#define mmMME1_QM_GLBL_STS0                                          0xE8038
+
+#define mmMME0_SBAB_SB_STALL                                         0x4002C
+#define mmMME0_SBAB_ARUSER0                                          0x40034
+#define mmMME0_SBAB_ARUSER1                                          0x40038
+#define mmMME0_SBAB_PROT                                             0x40050
+
+#define mmMME1_SBAB_SB_STALL                                         0xC002C
+#define mmMME1_SBAB_ARUSER0                                          0xC0034
+#define mmMME1_SBAB_ARUSER1                                          0xC0038
+#define mmMME1_SBAB_PROT                                             0xC0050
+
+#define mmMME2_SBAB_SB_STALL                                         0x14002C
+#define mmMME2_SBAB_ARUSER0                                          0x140034
+#define mmMME2_SBAB_ARUSER1                                          0x140038
+#define mmMME2_SBAB_PROT                                             0x140050
+
+#define mmMME3_SBAB_SB_STALL                                         0x1C002C
+#define mmMME3_SBAB_ARUSER0                                          0x1C0034
+#define mmMME3_SBAB_ARUSER1                                          0x1C0038
+#define mmMME3_SBAB_PROT                                             0x1C0050
+
+#define mmMME0_ACC_ACC_STALL                                         0x20028
+#define mmMME0_ACC_WBC                                               0x20038
+#define mmMME0_ACC_PROT                                              0x20050
+
+#define mmMME1_ACC_ACC_STALL                                         0xA0028
+#define mmMME1_ACC_WBC                                               0xA0038
+#define mmMME1_ACC_PROT                                              0xA0050
+
+#define mmMME2_ACC_ACC_STALL                                         0x120028
+#define mmMME2_ACC_WBC                                               0x120038
+#define mmMME2_ACC_PROT                                              0x120050
+
+#define mmMME3_ACC_ACC_STALL                                         0x1A0028
+#define mmMME3_ACC_WBC                                               0x1A0038
+#define mmMME3_ACC_PROT                                              0x1A0050
+
+#define mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR                         0x800040
+
+#define mmPSOC_EFUSE_READ                                            0xC4A000
+#define mmPSOC_EFUSE_DATA_0                                          0xC4A080
+
+#define mmPCIE_WRAP_MAX_OUTSTAND                                     0xC01B20
+#define mmPCIE_WRAP_LBW_PROT_OVR                                     0xC01B48
+#define mmPCIE_WRAP_HBW_DRAIN_CFG                                    0xC01D54
+#define mmPCIE_WRAP_LBW_DRAIN_CFG                                    0xC01D5C
+
+#define mmPCIE_MSI_INTR_0                                            0xC13000
+
+#define mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG                           0xC02000
+
+#define mmPCIE_AUX_FLR_CTRL                                          0xC07394
+#define mmPCIE_AUX_DBI                                               0xC07490
+
+#define mmPCIE_CORE_MSI_REQ                                          0xC04100
+
+#define mmPSOC_PCI_PLL_NR                                            0xC72100
+#define mmSRAM_W_PLL_NR                                              0x4C8100
+#define mmPSOC_HBM_PLL_NR                                            0xC74100
+#define mmNIC0_PLL_NR                                                0xCF9100
+#define mmDMA_W_PLL_NR                                               0x487100
+#define mmMESH_W_PLL_NR                                              0x4C7100
+#define mmPSOC_MME_PLL_NR                                            0xC71100
+#define mmPSOC_TPC_PLL_NR                                            0xC73100
+#define mmIF_W_PLL_NR                                                0x488100
+
+#define mmPCIE_WRAP_RR_ELBI_RD_SEC_REG_CTRL                          0xC01208
+
+#endif /* ASIC_REG_GAUDI_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/mme0_ctrl_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/mme0_ctrl_regs.h
new file mode 100644
index 000000000000..083d073a0128
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/mme0_ctrl_regs.h
@@ -0,0 +1,1456 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_MME0_CTRL_REGS_H_
+#define ASIC_REG_MME0_CTRL_REGS_H_
+
+/*
+ *****************************************
+ *   MME0_CTRL (Prototype: MME)
+ *****************************************
+ */
+
+#define mmMME0_CTRL_ARCH_STATUS                                      0x60000
+
+#define mmMME0_CTRL_ARCH_BASE_ADDR_HIGH_S                            0x60008
+
+#define mmMME0_CTRL_ARCH_BASE_ADDR_HIGH_L                            0x6000C
+
+#define mmMME0_CTRL_ARCH_BASE_ADDR_HIGH_O                            0x60010
+
+#define mmMME0_CTRL_ARCH_BASE_ADDR_LOW_S                             0x60014
+
+#define mmMME0_CTRL_ARCH_BASE_ADDR_LOW_L                             0x60018
+
+#define mmMME0_CTRL_ARCH_BASE_ADDR_LOW_O                             0x6001C
+
+#define mmMME0_CTRL_ARCH_HEADER_LOW                                  0x60020
+
+#define mmMME0_CTRL_ARCH_HEADER_HIGH                                 0x60024
+
+#define mmMME0_CTRL_ARCH_CONV_KERNEL_SIZE_MINUS_1                    0x60028
+
+#define mmMME0_CTRL_ARCH_CONV_ASSOCIATED_DIMS_LOW                    0x6002C
+
+#define mmMME0_CTRL_ARCH_CONV_ASSOCIATED_DIMS_HIGH                   0x60030
+
+#define mmMME0_CTRL_ARCH_NUM_ITERATIONS_MINUS_1                      0x60034
+
+#define mmMME0_CTRL_ARCH_OUTER_LOOP                                  0x60038
+
+#define mmMME0_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_0                   0x6003C
+
+#define mmMME0_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_1                   0x60040
+
+#define mmMME0_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_2                   0x60044
+
+#define mmMME0_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_3                   0x60048
+
+#define mmMME0_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_4                   0x6004C
+
+#define mmMME0_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_0                      0x60050
+
+#define mmMME0_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_1                      0x60054
+
+#define mmMME0_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_2                      0x60058
+
+#define mmMME0_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_3                      0x6005C
+
+#define mmMME0_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_4                      0x60060
+
+#define mmMME0_CTRL_ARCH_TENSOR_S_ROI_SIZE_0                         0x60064
+
+#define mmMME0_CTRL_ARCH_TENSOR_S_ROI_SIZE_1                         0x60068
+
+#define mmMME0_CTRL_ARCH_TENSOR_S_ROI_SIZE_2                         0x6006C
+
+#define mmMME0_CTRL_ARCH_TENSOR_S_ROI_SIZE_3                         0x60070
+
+#define mmMME0_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_0                  0x60074
+
+#define mmMME0_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_1                  0x60078
+
+#define mmMME0_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_2                  0x6007C
+
+#define mmMME0_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_3                  0x60080
+
+#define mmMME0_CTRL_ARCH_TENSOR_S_SPATIAL_SIZE_MINUS_1               0x60084
+
+#define mmMME0_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_0                     0x60088
+
+#define mmMME0_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_1                     0x6008C
+
+#define mmMME0_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_2                     0x60090
+
+#define mmMME0_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_3                     0x60094
+
+#define mmMME0_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_4                     0x60098
+
+#define mmMME0_CTRL_ARCH_AGU_S_START_OFFSET_0                        0x6009C
+
+#define mmMME0_CTRL_ARCH_AGU_S_START_OFFSET_1                        0x600A0
+
+#define mmMME0_CTRL_ARCH_AGU_S_START_OFFSET_2                        0x600A4
+
+#define mmMME0_CTRL_ARCH_AGU_S_START_OFFSET_3                        0x600A8
+
+#define mmMME0_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_0                   0x600AC
+
+#define mmMME0_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_1                   0x600B0
+
+#define mmMME0_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_2                   0x600B4
+
+#define mmMME0_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_3                   0x600B8
+
+#define mmMME0_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_4                   0x600BC
+
+#define mmMME0_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_0                      0x600C0
+
+#define mmMME0_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_1                      0x600C4
+
+#define mmMME0_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_2                      0x600C8
+
+#define mmMME0_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_3                      0x600CC
+
+#define mmMME0_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_4                      0x600D0
+
+#define mmMME0_CTRL_ARCH_TENSOR_L_ROI_SIZE_0                         0x600D4
+
+#define mmMME0_CTRL_ARCH_TENSOR_L_ROI_SIZE_1                         0x600D8
+
+#define mmMME0_CTRL_ARCH_TENSOR_L_ROI_SIZE_2                         0x600DC
+
+#define mmMME0_CTRL_ARCH_TENSOR_L_ROI_SIZE_3                         0x600E0
+
+#define mmMME0_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_0                  0x600E4
+
+#define mmMME0_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_1                  0x600E8
+
+#define mmMME0_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_2                  0x600EC
+
+#define mmMME0_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_3                  0x600F0
+
+#define mmMME0_CTRL_ARCH_TENSOR_L_SPATIAL_SIZE_MINUS_1               0x600F4
+
+#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_0               0x600F8
+
+#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_1               0x600FC
+
+#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_2               0x60100
+
+#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_3               0x60104
+
+#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_4               0x60108
+
+#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_0                  0x6010C
+
+#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_1                  0x60110
+
+#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_2                  0x60114
+
+#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_3                  0x60118
+
+#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_0              0x6011C
+
+#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_1              0x60120
+
+#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_2              0x60124
+
+#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_3              0x60128
+
+#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_4              0x6012C
+
+#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_0                 0x60130
+
+#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_1                 0x60134
+
+#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_2                 0x60138
+
+#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_3                 0x6013C
+
+#define mmMME0_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_0                   0x60140
+
+#define mmMME0_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_1                   0x60144
+
+#define mmMME0_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_2                   0x60148
+
+#define mmMME0_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_3                   0x6014C
+
+#define mmMME0_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_4                   0x60150
+
+#define mmMME0_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_0                      0x60154
+
+#define mmMME0_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_1                      0x60158
+
+#define mmMME0_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_2                      0x6015C
+
+#define mmMME0_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_3                      0x60160
+
+#define mmMME0_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_4                      0x60164
+
+#define mmMME0_CTRL_ARCH_TENSOR_O_ROI_SIZE_0                         0x60168
+
+#define mmMME0_CTRL_ARCH_TENSOR_O_ROI_SIZE_1                         0x6016C
+
+#define mmMME0_CTRL_ARCH_TENSOR_O_ROI_SIZE_2                         0x60170
+
+#define mmMME0_CTRL_ARCH_TENSOR_O_ROI_SIZE_3                         0x60174
+
+#define mmMME0_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_0                  0x60178
+
+#define mmMME0_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_1                  0x6017C
+
+#define mmMME0_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_2                  0x60180
+
+#define mmMME0_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_3                  0x60184
+
+#define mmMME0_CTRL_ARCH_TENSOR_O_SPATIAL_SIZE_MINUS_1               0x60188
+
+#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_0               0x6018C
+
+#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_1               0x60190
+
+#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_2               0x60194
+
+#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_3               0x60198
+
+#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_4               0x6019C
+
+#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_0                  0x601A0
+
+#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_1                  0x601A4
+
+#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_2                  0x601A8
+
+#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_3                  0x601AC
+
+#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_0              0x601B0
+
+#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_1              0x601B4
+
+#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_2              0x601B8
+
+#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_3              0x601BC
+
+#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_4              0x601C0
+
+#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_0                 0x601C4
+
+#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_1                 0x601C8
+
+#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_2                 0x601CC
+
+#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_3                 0x601D0
+
+#define mmMME0_CTRL_ARCH_DESC_SB_REPEAT                              0x601D4
+
+#define mmMME0_CTRL_ARCH_DESC_RATE_LIMITER                           0x601D8
+
+#define mmMME0_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL             0x601DC
+
+#define mmMME0_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE            0x601E0
+
+#define mmMME0_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_HIGH                  0x601E4
+
+#define mmMME0_CTRL_ARCH_DESC_SYNC_OBJECT_DATA                       0x601E8
+
+#define mmMME0_CTRL_ARCH_DESC_AXI_USER_DATA                          0x601EC
+
+#define mmMME0_CTRL_ARCH_DESC_PERF_EVT_S                             0x601F0
+
+#define mmMME0_CTRL_ARCH_DESC_PERF_EVT_L_LOCAL                       0x601F4
+
+#define mmMME0_CTRL_ARCH_DESC_PERF_EVT_L_REMOTE                      0x601F8
+
+#define mmMME0_CTRL_ARCH_DESC_PERF_EVT_O_LOCAL                       0x601FC
+
+#define mmMME0_CTRL_ARCH_DESC_PERF_EVT_O_REMOTE                      0x60200
+
+#define mmMME0_CTRL_ARCH_DESC_PADDING_VALUE_S                        0x60204
+
+#define mmMME0_CTRL_ARCH_DESC_PADDING_VALUE_L                        0x60208
+
+#define mmMME0_CTRL_ARCH_DESC_META_DATA_AGU_S                        0x6020C
+
+#define mmMME0_CTRL_ARCH_DESC_META_DATA_AGU_L_LOCAL                  0x60210
+
+#define mmMME0_CTRL_ARCH_DESC_META_DATA_AGU_L_REMOTE                 0x60214
+
+#define mmMME0_CTRL_ARCH_DESC_META_DATA_AGU_O_LOCAL                  0x60218
+
+#define mmMME0_CTRL_ARCH_DESC_META_DATA_AGU_O_REMOTE                 0x6021C
+
+#define mmMME0_CTRL_ARCH_DESC_PCU_RL_SATURATION                      0x60220
+
+#define mmMME0_CTRL_ARCH_DESC_DUMMY                                  0x60224
+
+#define mmMME0_CTRL_CMD                                              0x60280
+
+#define mmMME0_CTRL_STATUS1                                          0x60284
+
+#define mmMME0_CTRL_RESET                                            0x60288
+
+#define mmMME0_CTRL_QM_STALL                                         0x6028C
+
+#define mmMME0_CTRL_SYNC_OBJECT_FIFO_TH                              0x60290
+
+#define mmMME0_CTRL_EUS_ROLLUP_CNT_ADD                               0x60294
+
+#define mmMME0_CTRL_INTR_CAUSE                                       0x60298
+
+#define mmMME0_CTRL_INTR_MASK                                        0x6029C
+
+#define mmMME0_CTRL_LOG_SHADOW                                       0x602A0
+
+#define mmMME0_CTRL_PCU_RL_DESC0                                     0x602A4
+
+#define mmMME0_CTRL_PCU_RL_TOKEN_UPDATE                              0x602A8
+
+#define mmMME0_CTRL_PCU_RL_TH                                        0x602AC
+
+#define mmMME0_CTRL_PCU_RL_MIN                                       0x602B0
+
+#define mmMME0_CTRL_PCU_RL_CTRL_EN                                   0x602B4
+
+#define mmMME0_CTRL_PCU_RL_HISTORY_LOG_SIZE                          0x602B8
+
+#define mmMME0_CTRL_PCU_DUMMY_A_BF16                                 0x602BC
+
+#define mmMME0_CTRL_PCU_DUMMY_B_BF16                                 0x602C0
+
+#define mmMME0_CTRL_PCU_DUMMY_A_FP32_ODD                             0x602C4
+
+#define mmMME0_CTRL_PCU_DUMMY_A_FP32_EVEN                            0x602C8
+
+#define mmMME0_CTRL_PCU_DUMMY_B_FP32_ODD                             0x602CC
+
+#define mmMME0_CTRL_PCU_DUMMY_B_FP32_EVEN                            0x602D0
+
+#define mmMME0_CTRL_PROT                                             0x602D4
+
+#define mmMME0_CTRL_EU_POWER_SAVE_DISABLE                            0x602D8
+
+#define mmMME0_CTRL_CS_DBG_BLOCK_ID                                  0x602DC
+
+#define mmMME0_CTRL_CS_DBG_STATUS_DROP_CNT                           0x602E0
+
+#define mmMME0_CTRL_TE_CLOSE_CGATE                                   0x602E4
+
+#define mmMME0_CTRL_AGU_SM_INFLIGHT_CNTR                             0x602E8
+
+#define mmMME0_CTRL_AGU_SM_TOTAL_CNTR                                0x602EC
+
+#define mmMME0_CTRL_EZSYNC_OUT_CREDIT                                0x602F0
+
+#define mmMME0_CTRL_PCU_RL_SAT_SEC                                   0x602F4
+
+#define mmMME0_CTRL_AGU_SYNC_MSG_AXI_USER                            0x602F8
+
+#define mmMME0_CTRL_QM_SLV_LBW_CLK_EN                                0x602FC
+
+#define mmMME0_CTRL_SHADOW_0_STATUS                                  0x60400
+
+#define mmMME0_CTRL_SHADOW_0_BASE_ADDR_HIGH_S                        0x60408
+
+#define mmMME0_CTRL_SHADOW_0_BASE_ADDR_HIGH_L                        0x6040C
+
+#define mmMME0_CTRL_SHADOW_0_BASE_ADDR_HIGH_O                        0x60410
+
+#define mmMME0_CTRL_SHADOW_0_BASE_ADDR_LOW_S                         0x60414
+
+#define mmMME0_CTRL_SHADOW_0_BASE_ADDR_LOW_L                         0x60418
+
+#define mmMME0_CTRL_SHADOW_0_BASE_ADDR_LOW_O                         0x6041C
+
+#define mmMME0_CTRL_SHADOW_0_HEADER_LOW                              0x60420
+
+#define mmMME0_CTRL_SHADOW_0_HEADER_HIGH                             0x60424
+
+#define mmMME0_CTRL_SHADOW_0_CONV_KERNEL_SIZE_MINUS_1                0x60428
+
+#define mmMME0_CTRL_SHADOW_0_CONV_ASSOCIATED_DIMS_LOW                0x6042C
+
+#define mmMME0_CTRL_SHADOW_0_CONV_ASSOCIATED_DIMS_HIGH               0x60430
+
+#define mmMME0_CTRL_SHADOW_0_NUM_ITERATIONS_MINUS_1                  0x60434
+
+#define mmMME0_CTRL_SHADOW_0_OUTER_LOOP                              0x60438
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_0               0x6043C
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_1               0x60440
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_2               0x60444
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_3               0x60448
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_4               0x6044C
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_0                  0x60450
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_1                  0x60454
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_2                  0x60458
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_3                  0x6045C
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_4                  0x60460
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_0                     0x60464
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_1                     0x60468
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_2                     0x6046C
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_3                     0x60470
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_0              0x60474
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_1              0x60478
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_2              0x6047C
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_3              0x60480
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_S_SPATIAL_SIZE_MINUS_1           0x60484
+
+#define mmMME0_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_0                 0x60488
+
+#define mmMME0_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_1                 0x6048C
+
+#define mmMME0_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_2                 0x60490
+
+#define mmMME0_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_3                 0x60494
+
+#define mmMME0_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_4                 0x60498
+
+#define mmMME0_CTRL_SHADOW_0_AGU_S_START_OFFSET_0                    0x6049C
+
+#define mmMME0_CTRL_SHADOW_0_AGU_S_START_OFFSET_1                    0x604A0
+
+#define mmMME0_CTRL_SHADOW_0_AGU_S_START_OFFSET_2                    0x604A4
+
+#define mmMME0_CTRL_SHADOW_0_AGU_S_START_OFFSET_3                    0x604A8
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_0               0x604AC
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_1               0x604B0
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_2               0x604B4
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_3               0x604B8
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_4               0x604BC
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_0                  0x604C0
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_1                  0x604C4
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_2                  0x604C8
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_3                  0x604CC
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_4                  0x604D0
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_0                     0x604D4
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_1                     0x604D8
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_2                     0x604DC
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_3                     0x604E0
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_0              0x604E4
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_1              0x604E8
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_2              0x604EC
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_3              0x604F0
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_L_SPATIAL_SIZE_MINUS_1           0x604F4
+
+#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_0           0x604F8
+
+#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_1           0x604FC
+
+#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_2           0x60500
+
+#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_3           0x60504
+
+#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_4           0x60508
+
+#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_0              0x6050C
+
+#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_1              0x60510
+
+#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_2              0x60514
+
+#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_3              0x60518
+
+#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_0          0x6051C
+
+#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_1          0x60520
+
+#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_2          0x60524
+
+#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_3          0x60528
+
+#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_4          0x6052C
+
+#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_0             0x60530
+
+#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_1             0x60534
+
+#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_2             0x60538
+
+#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_3             0x6053C
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_0               0x60540
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_1               0x60544
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_2               0x60548
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_3               0x6054C
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_4               0x60550
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_0                  0x60554
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_1                  0x60558
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_2                  0x6055C
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_3                  0x60560
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_4                  0x60564
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_0                     0x60568
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_1                     0x6056C
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_2                     0x60570
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_3                     0x60574
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_0              0x60578
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_1              0x6057C
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_2              0x60580
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_3              0x60584
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_O_SPATIAL_SIZE_MINUS_1           0x60588
+
+#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_0           0x6058C
+
+#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_1           0x60590
+
+#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_2           0x60594
+
+#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_3           0x60598
+
+#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_4           0x6059C
+
+#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_0              0x605A0
+
+#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_1              0x605A4
+
+#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_2              0x605A8
+
+#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_3              0x605AC
+
+#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_0          0x605B0
+
+#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_1          0x605B4
+
+#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_2          0x605B8
+
+#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_3          0x605BC
+
+#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_4          0x605C0
+
+#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_0             0x605C4
+
+#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_1             0x605C8
+
+#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_2             0x605CC
+
+#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_3             0x605D0
+
+#define mmMME0_CTRL_SHADOW_0_DESC_SB_REPEAT                          0x605D4
+
+#define mmMME0_CTRL_SHADOW_0_DESC_RATE_LIMITER                       0x605D8
+
+#define mmMME0_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL         0x605DC
+
+#define mmMME0_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE        0x605E0
+
+#define mmMME0_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_HIGH              0x605E4
+
+#define mmMME0_CTRL_SHADOW_0_DESC_SYNC_OBJECT_DATA                   0x605E8
+
+#define mmMME0_CTRL_SHADOW_0_DESC_AXI_USER_DATA                      0x605EC
+
+#define mmMME0_CTRL_SHADOW_0_DESC_PERF_EVT_S                         0x605F0
+
+#define mmMME0_CTRL_SHADOW_0_DESC_PERF_EVT_L_LOCAL                   0x605F4
+
+#define mmMME0_CTRL_SHADOW_0_DESC_PERF_EVT_L_REMOTE                  0x605F8
+
+#define mmMME0_CTRL_SHADOW_0_DESC_PERF_EVT_O_LOCAL                   0x605FC
+
+#define mmMME0_CTRL_SHADOW_0_DESC_PERF_EVT_O_REMOTE                  0x60600
+
+#define mmMME0_CTRL_SHADOW_0_DESC_PADDING_VALUE_S                    0x60604
+
+#define mmMME0_CTRL_SHADOW_0_DESC_PADDING_VALUE_L                    0x60608
+
+#define mmMME0_CTRL_SHADOW_0_DESC_META_DATA_AGU_S                    0x6060C
+
+#define mmMME0_CTRL_SHADOW_0_DESC_META_DATA_AGU_L_LOCAL              0x60610
+
+#define mmMME0_CTRL_SHADOW_0_DESC_META_DATA_AGU_L_REMOTE             0x60614
+
+#define mmMME0_CTRL_SHADOW_0_DESC_META_DATA_AGU_O_LOCAL              0x60618
+
+#define mmMME0_CTRL_SHADOW_0_DESC_META_DATA_AGU_O_REMOTE             0x6061C
+
+#define mmMME0_CTRL_SHADOW_0_DESC_PCU_RL_SATURATION                  0x60620
+
+#define mmMME0_CTRL_SHADOW_0_DESC_DUMMY                              0x60624
+
+#define mmMME0_CTRL_SHADOW_1_STATUS                                  0x60680
+
+#define mmMME0_CTRL_SHADOW_1_BASE_ADDR_HIGH_S                        0x60688
+
+#define mmMME0_CTRL_SHADOW_1_BASE_ADDR_HIGH_L                        0x6068C
+
+#define mmMME0_CTRL_SHADOW_1_BASE_ADDR_HIGH_O                        0x60690
+
+#define mmMME0_CTRL_SHADOW_1_BASE_ADDR_LOW_S                         0x60694
+
+#define mmMME0_CTRL_SHADOW_1_BASE_ADDR_LOW_L                         0x60698
+
+#define mmMME0_CTRL_SHADOW_1_BASE_ADDR_LOW_O                         0x6069C
+
+#define mmMME0_CTRL_SHADOW_1_HEADER_LOW                              0x606A0
+
+#define mmMME0_CTRL_SHADOW_1_HEADER_HIGH                             0x606A4
+
+#define mmMME0_CTRL_SHADOW_1_CONV_KERNEL_SIZE_MINUS_1                0x606A8
+
+#define mmMME0_CTRL_SHADOW_1_CONV_ASSOCIATED_DIMS_LOW                0x606AC
+
+#define mmMME0_CTRL_SHADOW_1_CONV_ASSOCIATED_DIMS_HIGH               0x606B0
+
+#define mmMME0_CTRL_SHADOW_1_NUM_ITERATIONS_MINUS_1                  0x606B4
+
+#define mmMME0_CTRL_SHADOW_1_OUTER_LOOP                              0x606B8
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_0               0x606BC
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_1               0x606C0
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_2               0x606C4
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_3               0x606C8
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_4               0x606CC
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_0                  0x606D0
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_1                  0x606D4
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_2                  0x606D8
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_3                  0x606DC
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_4                  0x606E0
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_0                     0x606E4
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_1                     0x606E8
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_2                     0x606EC
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_3                     0x606F0
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_0              0x606F4
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_1              0x606F8
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_2              0x606FC
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_3              0x60700
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_S_SPATIAL_SIZE_MINUS_1           0x60704
+
+#define mmMME0_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_0                 0x60708
+
+#define mmMME0_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_1                 0x6070C
+
+#define mmMME0_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_2                 0x60710
+
+#define mmMME0_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_3                 0x60714
+
+#define mmMME0_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_4                 0x60718
+
+#define mmMME0_CTRL_SHADOW_1_AGU_S_START_OFFSET_0                    0x6071C
+
+#define mmMME0_CTRL_SHADOW_1_AGU_S_START_OFFSET_1                    0x60720
+
+#define mmMME0_CTRL_SHADOW_1_AGU_S_START_OFFSET_2                    0x60724
+
+#define mmMME0_CTRL_SHADOW_1_AGU_S_START_OFFSET_3                    0x60728
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_0               0x6072C
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_1               0x60730
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_2               0x60734
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_3               0x60738
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_4               0x6073C
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_0                  0x60740
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_1                  0x60744
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_2                  0x60748
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_3                  0x6074C
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_4                  0x60750
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_0                     0x60754
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_1                     0x60758
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_2                     0x6075C
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_3                     0x60760
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_0              0x60764
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_1              0x60768
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_2              0x6076C
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_3              0x60770
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_L_SPATIAL_SIZE_MINUS_1           0x60774
+
+#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_0           0x60778
+
+#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_1           0x6077C
+
+#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_2           0x60780
+
+#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_3           0x60784
+
+#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_4           0x60788
+
+#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_0              0x6078C
+
+#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_1              0x60790
+
+#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_2              0x60794
+
+#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_3              0x60798
+
+#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_0          0x6079C
+
+#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_1          0x607A0
+
+#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_2          0x607A4
+
+#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_3          0x607A8
+
+#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_4          0x607AC
+
+#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_0             0x607B0
+
+#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_1             0x607B4
+
+#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_2             0x607B8
+
+#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_3             0x607BC
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_0               0x607C0
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_1               0x607C4
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_2               0x607C8
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_3               0x607CC
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_4               0x607D0
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_0                  0x607D4
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_1                  0x607D8
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_2                  0x607DC
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_3                  0x607E0
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_4                  0x607E4
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_0                     0x607E8
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_1                     0x607EC
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_2                     0x607F0
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_3                     0x607F4
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_0              0x607F8
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_1              0x607FC
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_2              0x60800
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_3              0x60804
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_O_SPATIAL_SIZE_MINUS_1           0x60808
+
+#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_0           0x6080C
+
+#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_1           0x60810
+
+#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_2           0x60814
+
+#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_3           0x60818
+
+#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_4           0x6081C
+
+#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_0              0x60820
+
+#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_1              0x60824
+
+#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_2              0x60828
+
+#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_3              0x6082C
+
+#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_0          0x60830
+
+#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_1          0x60834
+
+#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_2          0x60838
+
+#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_3          0x6083C
+
+#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_4          0x60840
+
+#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_0             0x60844
+
+#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_1             0x60848
+
+#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_2             0x6084C
+
+#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_3             0x60850
+
+#define mmMME0_CTRL_SHADOW_1_DESC_SB_REPEAT                          0x60854
+
+#define mmMME0_CTRL_SHADOW_1_DESC_RATE_LIMITER                       0x60858
+
+#define mmMME0_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL         0x6085C
+
+#define mmMME0_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE        0x60860
+
+#define mmMME0_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_HIGH              0x60864
+
+#define mmMME0_CTRL_SHADOW_1_DESC_SYNC_OBJECT_DATA                   0x60868
+
+#define mmMME0_CTRL_SHADOW_1_DESC_AXI_USER_DATA                      0x6086C
+
+#define mmMME0_CTRL_SHADOW_1_DESC_PERF_EVT_S                         0x60870
+
+#define mmMME0_CTRL_SHADOW_1_DESC_PERF_EVT_L_LOCAL                   0x60874
+
+#define mmMME0_CTRL_SHADOW_1_DESC_PERF_EVT_L_REMOTE                  0x60878
+
+#define mmMME0_CTRL_SHADOW_1_DESC_PERF_EVT_O_LOCAL                   0x6087C
+
+#define mmMME0_CTRL_SHADOW_1_DESC_PERF_EVT_O_REMOTE                  0x60880
+
+#define mmMME0_CTRL_SHADOW_1_DESC_PADDING_VALUE_S                    0x60884
+
+#define mmMME0_CTRL_SHADOW_1_DESC_PADDING_VALUE_L                    0x60888
+
+#define mmMME0_CTRL_SHADOW_1_DESC_META_DATA_AGU_S                    0x6088C
+
+#define mmMME0_CTRL_SHADOW_1_DESC_META_DATA_AGU_L_LOCAL              0x60890
+
+#define mmMME0_CTRL_SHADOW_1_DESC_META_DATA_AGU_L_REMOTE             0x60894
+
+#define mmMME0_CTRL_SHADOW_1_DESC_META_DATA_AGU_O_LOCAL              0x60898
+
+#define mmMME0_CTRL_SHADOW_1_DESC_META_DATA_AGU_O_REMOTE             0x6089C
+
+#define mmMME0_CTRL_SHADOW_1_DESC_PCU_RL_SATURATION                  0x608A0
+
+#define mmMME0_CTRL_SHADOW_1_DESC_DUMMY                              0x608A4
+
+#define mmMME0_CTRL_SHADOW_2_STATUS                                  0x60900
+
+#define mmMME0_CTRL_SHADOW_2_BASE_ADDR_HIGH_S                        0x60908
+
+#define mmMME0_CTRL_SHADOW_2_BASE_ADDR_HIGH_L                        0x6090C
+
+#define mmMME0_CTRL_SHADOW_2_BASE_ADDR_HIGH_O                        0x60910
+
+#define mmMME0_CTRL_SHADOW_2_BASE_ADDR_LOW_S                         0x60914
+
+#define mmMME0_CTRL_SHADOW_2_BASE_ADDR_LOW_L                         0x60918
+
+#define mmMME0_CTRL_SHADOW_2_BASE_ADDR_LOW_O                         0x6091C
+
+#define mmMME0_CTRL_SHADOW_2_HEADER_LOW                              0x60920
+
+#define mmMME0_CTRL_SHADOW_2_HEADER_HIGH                             0x60924
+
+#define mmMME0_CTRL_SHADOW_2_CONV_KERNEL_SIZE_MINUS_1                0x60928
+
+#define mmMME0_CTRL_SHADOW_2_CONV_ASSOCIATED_DIMS_LOW                0x6092C
+
+#define mmMME0_CTRL_SHADOW_2_CONV_ASSOCIATED_DIMS_HIGH               0x60930
+
+#define mmMME0_CTRL_SHADOW_2_NUM_ITERATIONS_MINUS_1                  0x60934
+
+#define mmMME0_CTRL_SHADOW_2_OUTER_LOOP                              0x60938
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_0               0x6093C
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_1               0x60940
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_2               0x60944
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_3               0x60948
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_4               0x6094C
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_0                  0x60950
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_1                  0x60954
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_2                  0x60958
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_3                  0x6095C
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_4                  0x60960
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_0                     0x60964
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_1                     0x60968
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_2                     0x6096C
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_3                     0x60970
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_0              0x60974
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_1              0x60978
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_2              0x6097C
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_3              0x60980
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_S_SPATIAL_SIZE_MINUS_1           0x60984
+
+#define mmMME0_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_0                 0x60988
+
+#define mmMME0_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_1                 0x6098C
+
+#define mmMME0_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_2                 0x60990
+
+#define mmMME0_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_3                 0x60994
+
+#define mmMME0_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_4                 0x60998
+
+#define mmMME0_CTRL_SHADOW_2_AGU_S_START_OFFSET_0                    0x6099C
+
+#define mmMME0_CTRL_SHADOW_2_AGU_S_START_OFFSET_1                    0x609A0
+
+#define mmMME0_CTRL_SHADOW_2_AGU_S_START_OFFSET_2                    0x609A4
+
+#define mmMME0_CTRL_SHADOW_2_AGU_S_START_OFFSET_3                    0x609A8
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_0               0x609AC
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_1               0x609B0
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_2               0x609B4
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_3               0x609B8
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_4               0x609BC
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_0                  0x609C0
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_1                  0x609C4
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_2                  0x609C8
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_3                  0x609CC
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_4                  0x609D0
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_0                     0x609D4
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_1                     0x609D8
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_2                     0x609DC
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_3                     0x609E0
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_0              0x609E4
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_1              0x609E8
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_2              0x609EC
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_3              0x609F0
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_L_SPATIAL_SIZE_MINUS_1           0x609F4
+
+#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_0           0x609F8
+
+#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_1           0x609FC
+
+#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_2           0x60A00
+
+#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_3           0x60A04
+
+#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_4           0x60A08
+
+#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_0              0x60A0C
+
+#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_1              0x60A10
+
+#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_2              0x60A14
+
+#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_3              0x60A18
+
+#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_0          0x60A1C
+
+#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_1          0x60A20
+
+#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_2          0x60A24
+
+#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_3          0x60A28
+
+#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_4          0x60A2C
+
+#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_0             0x60A30
+
+#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_1             0x60A34
+
+#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_2             0x60A38
+
+#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_3             0x60A3C
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_0               0x60A40
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_1               0x60A44
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_2               0x60A48
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_3               0x60A4C
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_4               0x60A50
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_0                  0x60A54
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_1                  0x60A58
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_2                  0x60A5C
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_3                  0x60A60
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_4                  0x60A64
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_0                     0x60A68
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_1                     0x60A6C
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_2                     0x60A70
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_3                     0x60A74
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_0              0x60A78
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_1              0x60A7C
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_2              0x60A80
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_3              0x60A84
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_O_SPATIAL_SIZE_MINUS_1           0x60A88
+
+#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_0           0x60A8C
+
+#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_1           0x60A90
+
+#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_2           0x60A94
+
+#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_3           0x60A98
+
+#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_4           0x60A9C
+
+#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_0              0x60AA0
+
+#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_1              0x60AA4
+
+#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_2              0x60AA8
+
+#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_3              0x60AAC
+
+#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_0          0x60AB0
+
+#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_1          0x60AB4
+
+#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_2          0x60AB8
+
+#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_3          0x60ABC
+
+#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_4          0x60AC0
+
+#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_0             0x60AC4
+
+#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_1             0x60AC8
+
+#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_2             0x60ACC
+
+#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_3             0x60AD0
+
+#define mmMME0_CTRL_SHADOW_2_DESC_SB_REPEAT                          0x60AD4
+
+#define mmMME0_CTRL_SHADOW_2_DESC_RATE_LIMITER                       0x60AD8
+
+#define mmMME0_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL         0x60ADC
+
+#define mmMME0_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE        0x60AE0
+
+#define mmMME0_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_HIGH              0x60AE4
+
+#define mmMME0_CTRL_SHADOW_2_DESC_SYNC_OBJECT_DATA                   0x60AE8
+
+#define mmMME0_CTRL_SHADOW_2_DESC_AXI_USER_DATA                      0x60AEC
+
+#define mmMME0_CTRL_SHADOW_2_DESC_PERF_EVT_S                         0x60AF0
+
+#define mmMME0_CTRL_SHADOW_2_DESC_PERF_EVT_L_LOCAL                   0x60AF4
+
+#define mmMME0_CTRL_SHADOW_2_DESC_PERF_EVT_L_REMOTE                  0x60AF8
+
+#define mmMME0_CTRL_SHADOW_2_DESC_PERF_EVT_O_LOCAL                   0x60AFC
+
+#define mmMME0_CTRL_SHADOW_2_DESC_PERF_EVT_O_REMOTE                  0x60B00
+
+#define mmMME0_CTRL_SHADOW_2_DESC_PADDING_VALUE_S                    0x60B04
+
+#define mmMME0_CTRL_SHADOW_2_DESC_PADDING_VALUE_L                    0x60B08
+
+#define mmMME0_CTRL_SHADOW_2_DESC_META_DATA_AGU_S                    0x60B0C
+
+#define mmMME0_CTRL_SHADOW_2_DESC_META_DATA_AGU_L_LOCAL              0x60B10
+
+#define mmMME0_CTRL_SHADOW_2_DESC_META_DATA_AGU_L_REMOTE             0x60B14
+
+#define mmMME0_CTRL_SHADOW_2_DESC_META_DATA_AGU_O_LOCAL              0x60B18
+
+#define mmMME0_CTRL_SHADOW_2_DESC_META_DATA_AGU_O_REMOTE             0x60B1C
+
+#define mmMME0_CTRL_SHADOW_2_DESC_PCU_RL_SATURATION                  0x60B20
+
+#define mmMME0_CTRL_SHADOW_2_DESC_DUMMY                              0x60B24
+
+#define mmMME0_CTRL_SHADOW_3_STATUS                                  0x60B80
+
+#define mmMME0_CTRL_SHADOW_3_BASE_ADDR_HIGH_S                        0x60B88
+
+#define mmMME0_CTRL_SHADOW_3_BASE_ADDR_HIGH_L                        0x60B8C
+
+#define mmMME0_CTRL_SHADOW_3_BASE_ADDR_HIGH_O                        0x60B90
+
+#define mmMME0_CTRL_SHADOW_3_BASE_ADDR_LOW_S                         0x60B94
+
+#define mmMME0_CTRL_SHADOW_3_BASE_ADDR_LOW_L                         0x60B98
+
+#define mmMME0_CTRL_SHADOW_3_BASE_ADDR_LOW_O                         0x60B9C
+
+#define mmMME0_CTRL_SHADOW_3_HEADER_LOW                              0x60BA0
+
+#define mmMME0_CTRL_SHADOW_3_HEADER_HIGH                             0x60BA4
+
+#define mmMME0_CTRL_SHADOW_3_CONV_KERNEL_SIZE_MINUS_1                0x60BA8
+
+#define mmMME0_CTRL_SHADOW_3_CONV_ASSOCIATED_DIMS_LOW                0x60BAC
+
+#define mmMME0_CTRL_SHADOW_3_CONV_ASSOCIATED_DIMS_HIGH               0x60BB0
+
+#define mmMME0_CTRL_SHADOW_3_NUM_ITERATIONS_MINUS_1                  0x60BB4
+
+#define mmMME0_CTRL_SHADOW_3_OUTER_LOOP                              0x60BB8
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_0               0x60BBC
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_1               0x60BC0
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_2               0x60BC4
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_3               0x60BC8
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_4               0x60BCC
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_0                  0x60BD0
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_1                  0x60BD4
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_2                  0x60BD8
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_3                  0x60BDC
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_4                  0x60BE0
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_0                     0x60BE4
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_1                     0x60BE8
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_2                     0x60BEC
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_3                     0x60BF0
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_0              0x60BF4
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_1              0x60BF8
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_2              0x60BFC
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_3              0x60C00
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_S_SPATIAL_SIZE_MINUS_1           0x60C04
+
+#define mmMME0_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_0                 0x60C08
+
+#define mmMME0_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_1                 0x60C0C
+
+#define mmMME0_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_2                 0x60C10
+
+#define mmMME0_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_3                 0x60C14
+
+#define mmMME0_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_4                 0x60C18
+
+#define mmMME0_CTRL_SHADOW_3_AGU_S_START_OFFSET_0                    0x60C1C
+
+#define mmMME0_CTRL_SHADOW_3_AGU_S_START_OFFSET_1                    0x60C20
+
+#define mmMME0_CTRL_SHADOW_3_AGU_S_START_OFFSET_2                    0x60C24
+
+#define mmMME0_CTRL_SHADOW_3_AGU_S_START_OFFSET_3                    0x60C28
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_0               0x60C2C
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_1               0x60C30
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_2               0x60C34
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_3               0x60C38
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_4               0x60C3C
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_0                  0x60C40
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_1                  0x60C44
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_2                  0x60C48
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_3                  0x60C4C
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_4                  0x60C50
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_0                     0x60C54
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_1                     0x60C58
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_2                     0x60C5C
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_3                     0x60C60
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_0              0x60C64
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_1              0x60C68
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_2              0x60C6C
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_3              0x60C70
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_L_SPATIAL_SIZE_MINUS_1           0x60C74
+
+#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_0           0x60C78
+
+#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_1           0x60C7C
+
+#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_2           0x60C80
+
+#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_3           0x60C84
+
+#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_4           0x60C88
+
+#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_0              0x60C8C
+
+#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_1              0x60C90
+
+#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_2              0x60C94
+
+#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_3              0x60C98
+
+#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_0          0x60C9C
+
+#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_1          0x60CA0
+
+#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_2          0x60CA4
+
+#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_3          0x60CA8
+
+#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_4          0x60CAC
+
+#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_0             0x60CB0
+
+#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_1             0x60CB4
+
+#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_2             0x60CB8
+
+#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_3             0x60CBC
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_0               0x60CC0
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_1               0x60CC4
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_2               0x60CC8
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_3               0x60CCC
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_4               0x60CD0
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_0                  0x60CD4
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_1                  0x60CD8
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_2                  0x60CDC
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_3                  0x60CE0
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_4                  0x60CE4
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_0                     0x60CE8
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_1                     0x60CEC
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_2                     0x60CF0
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_3                     0x60CF4
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_0              0x60CF8
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_1              0x60CFC
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_2              0x60D00
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_3              0x60D04
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_O_SPATIAL_SIZE_MINUS_1           0x60D08
+
+#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_0           0x60D0C
+
+#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_1           0x60D10
+
+#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_2           0x60D14
+
+#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_3           0x60D18
+
+#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_4           0x60D1C
+
+#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_0              0x60D20
+
+#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_1              0x60D24
+
+#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_2              0x60D28
+
+#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_3              0x60D2C
+
+#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_0          0x60D30
+
+#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_1          0x60D34
+
+#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_2          0x60D38
+
+#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_3          0x60D3C
+
+#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_4          0x60D40
+
+#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_0             0x60D44
+
+#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_1             0x60D48
+
+#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_2             0x60D4C
+
+#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_3             0x60D50
+
+#define mmMME0_CTRL_SHADOW_3_DESC_SB_REPEAT                          0x60D54
+
+#define mmMME0_CTRL_SHADOW_3_DESC_RATE_LIMITER                       0x60D58
+
+#define mmMME0_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL         0x60D5C
+
+#define mmMME0_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE        0x60D60
+
+#define mmMME0_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_HIGH              0x60D64
+
+#define mmMME0_CTRL_SHADOW_3_DESC_SYNC_OBJECT_DATA                   0x60D68
+
+#define mmMME0_CTRL_SHADOW_3_DESC_AXI_USER_DATA                      0x60D6C
+
+#define mmMME0_CTRL_SHADOW_3_DESC_PERF_EVT_S                         0x60D70
+
+#define mmMME0_CTRL_SHADOW_3_DESC_PERF_EVT_L_LOCAL                   0x60D74
+
+#define mmMME0_CTRL_SHADOW_3_DESC_PERF_EVT_L_REMOTE                  0x60D78
+
+#define mmMME0_CTRL_SHADOW_3_DESC_PERF_EVT_O_LOCAL                   0x60D7C
+
+#define mmMME0_CTRL_SHADOW_3_DESC_PERF_EVT_O_REMOTE                  0x60D80
+
+#define mmMME0_CTRL_SHADOW_3_DESC_PADDING_VALUE_S                    0x60D84
+
+#define mmMME0_CTRL_SHADOW_3_DESC_PADDING_VALUE_L                    0x60D88
+
+#define mmMME0_CTRL_SHADOW_3_DESC_META_DATA_AGU_S                    0x60D8C
+
+#define mmMME0_CTRL_SHADOW_3_DESC_META_DATA_AGU_L_LOCAL              0x60D90
+
+#define mmMME0_CTRL_SHADOW_3_DESC_META_DATA_AGU_L_REMOTE             0x60D94
+
+#define mmMME0_CTRL_SHADOW_3_DESC_META_DATA_AGU_O_LOCAL              0x60D98
+
+#define mmMME0_CTRL_SHADOW_3_DESC_META_DATA_AGU_O_REMOTE             0x60D9C
+
+#define mmMME0_CTRL_SHADOW_3_DESC_PCU_RL_SATURATION                  0x60DA0
+
+#define mmMME0_CTRL_SHADOW_3_DESC_DUMMY                              0x60DA4
+
+#endif /* ASIC_REG_MME0_CTRL_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/mme0_qm_masks.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/mme0_qm_masks.h
new file mode 100644
index 000000000000..e6dd30ce0ca7
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/mme0_qm_masks.h
@@ -0,0 +1,800 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_MME0_QM_MASKS_H_
+#define ASIC_REG_MME0_QM_MASKS_H_
+
+/*
+ *****************************************
+ *   MME0_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+/* MME0_QM_GLBL_CFG0 */
+#define MME0_QM_GLBL_CFG0_PQF_EN_SHIFT                               0
+#define MME0_QM_GLBL_CFG0_PQF_EN_MASK                                0xF
+#define MME0_QM_GLBL_CFG0_CQF_EN_SHIFT                               4
+#define MME0_QM_GLBL_CFG0_CQF_EN_MASK                                0x1F0
+#define MME0_QM_GLBL_CFG0_CP_EN_SHIFT                                9
+#define MME0_QM_GLBL_CFG0_CP_EN_MASK                                 0x3E00
+
+/* MME0_QM_GLBL_CFG1 */
+#define MME0_QM_GLBL_CFG1_PQF_STOP_SHIFT                             0
+#define MME0_QM_GLBL_CFG1_PQF_STOP_MASK                              0xF
+#define MME0_QM_GLBL_CFG1_CQF_STOP_SHIFT                             4
+#define MME0_QM_GLBL_CFG1_CQF_STOP_MASK                              0x1F0
+#define MME0_QM_GLBL_CFG1_CP_STOP_SHIFT                              9
+#define MME0_QM_GLBL_CFG1_CP_STOP_MASK                               0x3E00
+#define MME0_QM_GLBL_CFG1_PQF_FLUSH_SHIFT                            16
+#define MME0_QM_GLBL_CFG1_PQF_FLUSH_MASK                             0xF0000
+#define MME0_QM_GLBL_CFG1_CQF_FLUSH_SHIFT                            20
+#define MME0_QM_GLBL_CFG1_CQF_FLUSH_MASK                             0x1F00000
+#define MME0_QM_GLBL_CFG1_CP_FLUSH_SHIFT                             25
+#define MME0_QM_GLBL_CFG1_CP_FLUSH_MASK                              0x3E000000
+
+/* MME0_QM_GLBL_PROT */
+#define MME0_QM_GLBL_PROT_PQF_SHIFT                                  0
+#define MME0_QM_GLBL_PROT_PQF_MASK                                   0xF
+#define MME0_QM_GLBL_PROT_CQF_SHIFT                                  4
+#define MME0_QM_GLBL_PROT_CQF_MASK                                   0x1F0
+#define MME0_QM_GLBL_PROT_CP_SHIFT                                   9
+#define MME0_QM_GLBL_PROT_CP_MASK                                    0x3E00
+#define MME0_QM_GLBL_PROT_ERR_SHIFT                                  14
+#define MME0_QM_GLBL_PROT_ERR_MASK                                   0x4000
+#define MME0_QM_GLBL_PROT_ARB_SHIFT                                  15
+#define MME0_QM_GLBL_PROT_ARB_MASK                                   0x8000
+
+/* MME0_QM_GLBL_ERR_CFG */
+#define MME0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT                    0
+#define MME0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK                     0xF
+#define MME0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT                    4
+#define MME0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK                     0x1F0
+#define MME0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT                     9
+#define MME0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK                      0x3E00
+#define MME0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT                   16
+#define MME0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK                    0xF0000
+#define MME0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT                   20
+#define MME0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK                    0x1F00000
+#define MME0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT                    25
+#define MME0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK                     0x3E000000
+#define MME0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT                   31
+#define MME0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK                    0x80000000
+
+/* MME0_QM_GLBL_SECURE_PROPS */
+#define MME0_QM_GLBL_SECURE_PROPS_0_ASID_SHIFT                       0
+#define MME0_QM_GLBL_SECURE_PROPS_0_ASID_MASK                        0x3FF
+#define MME0_QM_GLBL_SECURE_PROPS_1_ASID_SHIFT                       0
+#define MME0_QM_GLBL_SECURE_PROPS_1_ASID_MASK                        0x3FF
+#define MME0_QM_GLBL_SECURE_PROPS_2_ASID_SHIFT                       0
+#define MME0_QM_GLBL_SECURE_PROPS_2_ASID_MASK                        0x3FF
+#define MME0_QM_GLBL_SECURE_PROPS_3_ASID_SHIFT                       0
+#define MME0_QM_GLBL_SECURE_PROPS_3_ASID_MASK                        0x3FF
+#define MME0_QM_GLBL_SECURE_PROPS_4_ASID_SHIFT                       0
+#define MME0_QM_GLBL_SECURE_PROPS_4_ASID_MASK                        0x3FF
+#define MME0_QM_GLBL_SECURE_PROPS_0_MMBP_SHIFT                       10
+#define MME0_QM_GLBL_SECURE_PROPS_0_MMBP_MASK                        0x400
+#define MME0_QM_GLBL_SECURE_PROPS_1_MMBP_SHIFT                       10
+#define MME0_QM_GLBL_SECURE_PROPS_1_MMBP_MASK                        0x400
+#define MME0_QM_GLBL_SECURE_PROPS_2_MMBP_SHIFT                       10
+#define MME0_QM_GLBL_SECURE_PROPS_2_MMBP_MASK                        0x400
+#define MME0_QM_GLBL_SECURE_PROPS_3_MMBP_SHIFT                       10
+#define MME0_QM_GLBL_SECURE_PROPS_3_MMBP_MASK                        0x400
+#define MME0_QM_GLBL_SECURE_PROPS_4_MMBP_SHIFT                       10
+#define MME0_QM_GLBL_SECURE_PROPS_4_MMBP_MASK                        0x400
+
+/* MME0_QM_GLBL_NON_SECURE_PROPS */
+#define MME0_QM_GLBL_NON_SECURE_PROPS_0_ASID_SHIFT                   0
+#define MME0_QM_GLBL_NON_SECURE_PROPS_0_ASID_MASK                    0x3FF
+#define MME0_QM_GLBL_NON_SECURE_PROPS_1_ASID_SHIFT                   0
+#define MME0_QM_GLBL_NON_SECURE_PROPS_1_ASID_MASK                    0x3FF
+#define MME0_QM_GLBL_NON_SECURE_PROPS_2_ASID_SHIFT                   0
+#define MME0_QM_GLBL_NON_SECURE_PROPS_2_ASID_MASK                    0x3FF
+#define MME0_QM_GLBL_NON_SECURE_PROPS_3_ASID_SHIFT                   0
+#define MME0_QM_GLBL_NON_SECURE_PROPS_3_ASID_MASK                    0x3FF
+#define MME0_QM_GLBL_NON_SECURE_PROPS_4_ASID_SHIFT                   0
+#define MME0_QM_GLBL_NON_SECURE_PROPS_4_ASID_MASK                    0x3FF
+#define MME0_QM_GLBL_NON_SECURE_PROPS_0_MMBP_SHIFT                   10
+#define MME0_QM_GLBL_NON_SECURE_PROPS_0_MMBP_MASK                    0x400
+#define MME0_QM_GLBL_NON_SECURE_PROPS_1_MMBP_SHIFT                   10
+#define MME0_QM_GLBL_NON_SECURE_PROPS_1_MMBP_MASK                    0x400
+#define MME0_QM_GLBL_NON_SECURE_PROPS_2_MMBP_SHIFT                   10
+#define MME0_QM_GLBL_NON_SECURE_PROPS_2_MMBP_MASK                    0x400
+#define MME0_QM_GLBL_NON_SECURE_PROPS_3_MMBP_SHIFT                   10
+#define MME0_QM_GLBL_NON_SECURE_PROPS_3_MMBP_MASK                    0x400
+#define MME0_QM_GLBL_NON_SECURE_PROPS_4_MMBP_SHIFT                   10
+#define MME0_QM_GLBL_NON_SECURE_PROPS_4_MMBP_MASK                    0x400
+
+/* MME0_QM_GLBL_STS0 */
+#define MME0_QM_GLBL_STS0_PQF_IDLE_SHIFT                             0
+#define MME0_QM_GLBL_STS0_PQF_IDLE_MASK                              0xF
+#define MME0_QM_GLBL_STS0_CQF_IDLE_SHIFT                             4
+#define MME0_QM_GLBL_STS0_CQF_IDLE_MASK                              0x1F0
+#define MME0_QM_GLBL_STS0_CP_IDLE_SHIFT                              9
+#define MME0_QM_GLBL_STS0_CP_IDLE_MASK                               0x3E00
+#define MME0_QM_GLBL_STS0_PQF_IS_STOP_SHIFT                          16
+#define MME0_QM_GLBL_STS0_PQF_IS_STOP_MASK                           0xF0000
+#define MME0_QM_GLBL_STS0_CQF_IS_STOP_SHIFT                          20
+#define MME0_QM_GLBL_STS0_CQF_IS_STOP_MASK                           0x1F00000
+#define MME0_QM_GLBL_STS0_CP_IS_STOP_SHIFT                           25
+#define MME0_QM_GLBL_STS0_CP_IS_STOP_MASK                            0x3E000000
+#define MME0_QM_GLBL_STS0_ARB_IS_STOP_SHIFT                          31
+#define MME0_QM_GLBL_STS0_ARB_IS_STOP_MASK                           0x80000000
+
+/* MME0_QM_GLBL_STS1 */
+#define MME0_QM_GLBL_STS1_PQF_RD_ERR_SHIFT                           0
+#define MME0_QM_GLBL_STS1_PQF_RD_ERR_MASK                            0x1
+#define MME0_QM_GLBL_STS1_CQF_RD_ERR_SHIFT                           1
+#define MME0_QM_GLBL_STS1_CQF_RD_ERR_MASK                            0x2
+#define MME0_QM_GLBL_STS1_CP_RD_ERR_SHIFT                            2
+#define MME0_QM_GLBL_STS1_CP_RD_ERR_MASK                             0x4
+#define MME0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT                     3
+#define MME0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK                      0x8
+#define MME0_QM_GLBL_STS1_CP_STOP_OP_SHIFT                           4
+#define MME0_QM_GLBL_STS1_CP_STOP_OP_MASK                            0x10
+#define MME0_QM_GLBL_STS1_CP_MSG_WR_ERR_SHIFT                        5
+#define MME0_QM_GLBL_STS1_CP_MSG_WR_ERR_MASK                         0x20
+#define MME0_QM_GLBL_STS1_CP_WREG_ERR_SHIFT                          6
+#define MME0_QM_GLBL_STS1_CP_WREG_ERR_MASK                           0x40
+#define MME0_QM_GLBL_STS1_CP_FENCE0_OVF_ERR_SHIFT                    8
+#define MME0_QM_GLBL_STS1_CP_FENCE0_OVF_ERR_MASK                     0x100
+#define MME0_QM_GLBL_STS1_CP_FENCE1_OVF_ERR_SHIFT                    9
+#define MME0_QM_GLBL_STS1_CP_FENCE1_OVF_ERR_MASK                     0x200
+#define MME0_QM_GLBL_STS1_CP_FENCE2_OVF_ERR_SHIFT                    10
+#define MME0_QM_GLBL_STS1_CP_FENCE2_OVF_ERR_MASK                     0x400
+#define MME0_QM_GLBL_STS1_CP_FENCE3_OVF_ERR_SHIFT                    11
+#define MME0_QM_GLBL_STS1_CP_FENCE3_OVF_ERR_MASK                     0x800
+#define MME0_QM_GLBL_STS1_CP_FENCE0_UDF_ERR_SHIFT                    12
+#define MME0_QM_GLBL_STS1_CP_FENCE0_UDF_ERR_MASK                     0x1000
+#define MME0_QM_GLBL_STS1_CP_FENCE1_UDF_ERR_SHIFT                    13
+#define MME0_QM_GLBL_STS1_CP_FENCE1_UDF_ERR_MASK                     0x2000
+#define MME0_QM_GLBL_STS1_CP_FENCE2_UDF_ERR_SHIFT                    14
+#define MME0_QM_GLBL_STS1_CP_FENCE2_UDF_ERR_MASK                     0x4000
+#define MME0_QM_GLBL_STS1_CP_FENCE3_UDF_ERR_SHIFT                    15
+#define MME0_QM_GLBL_STS1_CP_FENCE3_UDF_ERR_MASK                     0x8000
+
+/* MME0_QM_GLBL_STS1_4 */
+#define MME0_QM_GLBL_STS1_4_CQF_RD_ERR_SHIFT                         1
+#define MME0_QM_GLBL_STS1_4_CQF_RD_ERR_MASK                          0x2
+#define MME0_QM_GLBL_STS1_4_CP_RD_ERR_SHIFT                          2
+#define MME0_QM_GLBL_STS1_4_CP_RD_ERR_MASK                           0x4
+#define MME0_QM_GLBL_STS1_4_CP_UNDEF_CMD_ERR_SHIFT                   3
+#define MME0_QM_GLBL_STS1_4_CP_UNDEF_CMD_ERR_MASK                    0x8
+#define MME0_QM_GLBL_STS1_4_CP_STOP_OP_SHIFT                         4
+#define MME0_QM_GLBL_STS1_4_CP_STOP_OP_MASK                          0x10
+#define MME0_QM_GLBL_STS1_4_CP_MSG_WR_ERR_SHIFT                      5
+#define MME0_QM_GLBL_STS1_4_CP_MSG_WR_ERR_MASK                       0x20
+#define MME0_QM_GLBL_STS1_4_CP_WREG_ERR_SHIFT                        6
+#define MME0_QM_GLBL_STS1_4_CP_WREG_ERR_MASK                         0x40
+#define MME0_QM_GLBL_STS1_4_CP_FENCE0_OVF_ERR_SHIFT                  8
+#define MME0_QM_GLBL_STS1_4_CP_FENCE0_OVF_ERR_MASK                   0x100
+#define MME0_QM_GLBL_STS1_4_CP_FENCE1_OVF_ERR_SHIFT                  9
+#define MME0_QM_GLBL_STS1_4_CP_FENCE1_OVF_ERR_MASK                   0x200
+#define MME0_QM_GLBL_STS1_4_CP_FENCE2_OVF_ERR_SHIFT                  10
+#define MME0_QM_GLBL_STS1_4_CP_FENCE2_OVF_ERR_MASK                   0x400
+#define MME0_QM_GLBL_STS1_4_CP_FENCE3_OVF_ERR_SHIFT                  11
+#define MME0_QM_GLBL_STS1_4_CP_FENCE3_OVF_ERR_MASK                   0x800
+#define MME0_QM_GLBL_STS1_4_CP_FENCE0_UDF_ERR_SHIFT                  12
+#define MME0_QM_GLBL_STS1_4_CP_FENCE0_UDF_ERR_MASK                   0x1000
+#define MME0_QM_GLBL_STS1_4_CP_FENCE1_UDF_ERR_SHIFT                  13
+#define MME0_QM_GLBL_STS1_4_CP_FENCE1_UDF_ERR_MASK                   0x2000
+#define MME0_QM_GLBL_STS1_4_CP_FENCE2_UDF_ERR_SHIFT                  14
+#define MME0_QM_GLBL_STS1_4_CP_FENCE2_UDF_ERR_MASK                   0x4000
+#define MME0_QM_GLBL_STS1_4_CP_FENCE3_UDF_ERR_SHIFT                  15
+#define MME0_QM_GLBL_STS1_4_CP_FENCE3_UDF_ERR_MASK                   0x8000
+
+/* MME0_QM_GLBL_MSG_EN */
+#define MME0_QM_GLBL_MSG_EN_PQF_RD_ERR_SHIFT                         0
+#define MME0_QM_GLBL_MSG_EN_PQF_RD_ERR_MASK                          0x1
+#define MME0_QM_GLBL_MSG_EN_CQF_RD_ERR_SHIFT                         1
+#define MME0_QM_GLBL_MSG_EN_CQF_RD_ERR_MASK                          0x2
+#define MME0_QM_GLBL_MSG_EN_CP_RD_ERR_SHIFT                          2
+#define MME0_QM_GLBL_MSG_EN_CP_RD_ERR_MASK                           0x4
+#define MME0_QM_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_SHIFT                   3
+#define MME0_QM_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_MASK                    0x8
+#define MME0_QM_GLBL_MSG_EN_CP_STOP_OP_SHIFT                         4
+#define MME0_QM_GLBL_MSG_EN_CP_STOP_OP_MASK                          0x10
+#define MME0_QM_GLBL_MSG_EN_CP_MSG_WR_ERR_SHIFT                      5
+#define MME0_QM_GLBL_MSG_EN_CP_MSG_WR_ERR_MASK                       0x20
+#define MME0_QM_GLBL_MSG_EN_CP_WREG_ERR_SHIFT                        6
+#define MME0_QM_GLBL_MSG_EN_CP_WREG_ERR_MASK                         0x40
+#define MME0_QM_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_SHIFT                  8
+#define MME0_QM_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_MASK                   0x100
+#define MME0_QM_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_SHIFT                  9
+#define MME0_QM_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_MASK                   0x200
+#define MME0_QM_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_SHIFT                  10
+#define MME0_QM_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_MASK                   0x400
+#define MME0_QM_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_SHIFT                  11
+#define MME0_QM_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_MASK                   0x800
+#define MME0_QM_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_SHIFT                  12
+#define MME0_QM_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_MASK                   0x1000
+#define MME0_QM_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_SHIFT                  13
+#define MME0_QM_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_MASK                   0x2000
+#define MME0_QM_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_SHIFT                  14
+#define MME0_QM_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_MASK                   0x4000
+#define MME0_QM_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_SHIFT                  15
+#define MME0_QM_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_MASK                   0x8000
+
+/* MME0_QM_GLBL_MSG_EN_4 */
+#define MME0_QM_GLBL_MSG_EN_4_CQF_RD_ERR_SHIFT                       1
+#define MME0_QM_GLBL_MSG_EN_4_CQF_RD_ERR_MASK                        0x2
+#define MME0_QM_GLBL_MSG_EN_4_CP_RD_ERR_SHIFT                        2
+#define MME0_QM_GLBL_MSG_EN_4_CP_RD_ERR_MASK                         0x4
+#define MME0_QM_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_SHIFT                 3
+#define MME0_QM_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_MASK                  0x8
+#define MME0_QM_GLBL_MSG_EN_4_CP_STOP_OP_SHIFT                       4
+#define MME0_QM_GLBL_MSG_EN_4_CP_STOP_OP_MASK                        0x10
+#define MME0_QM_GLBL_MSG_EN_4_CP_MSG_WR_ERR_SHIFT                    5
+#define MME0_QM_GLBL_MSG_EN_4_CP_MSG_WR_ERR_MASK                     0x20
+#define MME0_QM_GLBL_MSG_EN_4_CP_WREG_ERR_SHIFT                      6
+#define MME0_QM_GLBL_MSG_EN_4_CP_WREG_ERR_MASK                       0x40
+#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_SHIFT                8
+#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_MASK                 0x100
+#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_SHIFT                9
+#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_MASK                 0x200
+#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_SHIFT                10
+#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_MASK                 0x400
+#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_SHIFT                11
+#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_MASK                 0x800
+#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_SHIFT                12
+#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_MASK                 0x1000
+#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_SHIFT                13
+#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_MASK                 0x2000
+#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_SHIFT                14
+#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_MASK                 0x4000
+#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_SHIFT                15
+#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_MASK                 0x8000
+
+/* MME0_QM_PQ_BASE_LO */
+#define MME0_QM_PQ_BASE_LO_VAL_SHIFT                                 0
+#define MME0_QM_PQ_BASE_LO_VAL_MASK                                  0xFFFFFFFF
+
+/* MME0_QM_PQ_BASE_HI */
+#define MME0_QM_PQ_BASE_HI_VAL_SHIFT                                 0
+#define MME0_QM_PQ_BASE_HI_VAL_MASK                                  0xFFFFFFFF
+
+/* MME0_QM_PQ_SIZE */
+#define MME0_QM_PQ_SIZE_VAL_SHIFT                                    0
+#define MME0_QM_PQ_SIZE_VAL_MASK                                     0xFFFFFFFF
+
+/* MME0_QM_PQ_PI */
+#define MME0_QM_PQ_PI_VAL_SHIFT                                      0
+#define MME0_QM_PQ_PI_VAL_MASK                                       0xFFFFFFFF
+
+/* MME0_QM_PQ_CI */
+#define MME0_QM_PQ_CI_VAL_SHIFT                                      0
+#define MME0_QM_PQ_CI_VAL_MASK                                       0xFFFFFFFF
+
+/* MME0_QM_PQ_CFG0 */
+#define MME0_QM_PQ_CFG0_RESERVED_SHIFT                               0
+#define MME0_QM_PQ_CFG0_RESERVED_MASK                                0x1
+
+/* MME0_QM_PQ_CFG1 */
+#define MME0_QM_PQ_CFG1_CREDIT_LIM_SHIFT                             0
+#define MME0_QM_PQ_CFG1_CREDIT_LIM_MASK                              0xFFFF
+#define MME0_QM_PQ_CFG1_MAX_INFLIGHT_SHIFT                           16
+#define MME0_QM_PQ_CFG1_MAX_INFLIGHT_MASK                            0xFFFF0000
+
+/* MME0_QM_PQ_ARUSER_31_11 */
+#define MME0_QM_PQ_ARUSER_31_11_VAL_SHIFT                            0
+#define MME0_QM_PQ_ARUSER_31_11_VAL_MASK                             0x1FFFFF
+
+/* MME0_QM_PQ_STS0 */
+#define MME0_QM_PQ_STS0_PQ_CREDIT_CNT_SHIFT                          0
+#define MME0_QM_PQ_STS0_PQ_CREDIT_CNT_MASK                           0xFFFF
+#define MME0_QM_PQ_STS0_PQ_FREE_CNT_SHIFT                            16
+#define MME0_QM_PQ_STS0_PQ_FREE_CNT_MASK                             0xFFFF0000
+
+/* MME0_QM_PQ_STS1 */
+#define MME0_QM_PQ_STS1_PQ_INFLIGHT_CNT_SHIFT                        0
+#define MME0_QM_PQ_STS1_PQ_INFLIGHT_CNT_MASK                         0xFFFF
+#define MME0_QM_PQ_STS1_PQ_BUF_EMPTY_SHIFT                           30
+#define MME0_QM_PQ_STS1_PQ_BUF_EMPTY_MASK                            0x40000000
+#define MME0_QM_PQ_STS1_PQ_BUSY_SHIFT                                31
+#define MME0_QM_PQ_STS1_PQ_BUSY_MASK                                 0x80000000
+
+/* MME0_QM_CQ_CFG0 */
+#define MME0_QM_CQ_CFG0_RESERVED_SHIFT                               0
+#define MME0_QM_CQ_CFG0_RESERVED_MASK                                0x1
+
+/* MME0_QM_CQ_CFG1 */
+#define MME0_QM_CQ_CFG1_CREDIT_LIM_SHIFT                             0
+#define MME0_QM_CQ_CFG1_CREDIT_LIM_MASK                              0xFFFF
+#define MME0_QM_CQ_CFG1_MAX_INFLIGHT_SHIFT                           16
+#define MME0_QM_CQ_CFG1_MAX_INFLIGHT_MASK                            0xFFFF0000
+
+/* MME0_QM_CQ_ARUSER_31_11 */
+#define MME0_QM_CQ_ARUSER_31_11_VAL_SHIFT                            0
+#define MME0_QM_CQ_ARUSER_31_11_VAL_MASK                             0x1FFFFF
+
+/* MME0_QM_CQ_STS0 */
+#define MME0_QM_CQ_STS0_CQ_CREDIT_CNT_SHIFT                          0
+#define MME0_QM_CQ_STS0_CQ_CREDIT_CNT_MASK                           0xFFFF
+#define MME0_QM_CQ_STS0_CQ_FREE_CNT_SHIFT                            16
+#define MME0_QM_CQ_STS0_CQ_FREE_CNT_MASK                             0xFFFF0000
+
+/* MME0_QM_CQ_STS1 */
+#define MME0_QM_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT                        0
+#define MME0_QM_CQ_STS1_CQ_INFLIGHT_CNT_MASK                         0xFFFF
+#define MME0_QM_CQ_STS1_CQ_BUF_EMPTY_SHIFT                           30
+#define MME0_QM_CQ_STS1_CQ_BUF_EMPTY_MASK                            0x40000000
+#define MME0_QM_CQ_STS1_CQ_BUSY_SHIFT                                31
+#define MME0_QM_CQ_STS1_CQ_BUSY_MASK                                 0x80000000
+
+/* MME0_QM_CQ_PTR_LO_0 */
+#define MME0_QM_CQ_PTR_LO_0_VAL_SHIFT                                0
+#define MME0_QM_CQ_PTR_LO_0_VAL_MASK                                 0xFFFFFFFF
+
+/* MME0_QM_CQ_PTR_HI_0 */
+#define MME0_QM_CQ_PTR_HI_0_VAL_SHIFT                                0
+#define MME0_QM_CQ_PTR_HI_0_VAL_MASK                                 0xFFFFFFFF
+
+/* MME0_QM_CQ_TSIZE_0 */
+#define MME0_QM_CQ_TSIZE_0_VAL_SHIFT                                 0
+#define MME0_QM_CQ_TSIZE_0_VAL_MASK                                  0xFFFFFFFF
+
+/* MME0_QM_CQ_CTL_0 */
+#define MME0_QM_CQ_CTL_0_RPT_SHIFT                                   0
+#define MME0_QM_CQ_CTL_0_RPT_MASK                                    0xFFFF
+#define MME0_QM_CQ_CTL_0_CTL_SHIFT                                   16
+#define MME0_QM_CQ_CTL_0_CTL_MASK                                    0xFFFF0000
+
+/* MME0_QM_CQ_PTR_LO_1 */
+#define MME0_QM_CQ_PTR_LO_1_VAL_SHIFT                                0
+#define MME0_QM_CQ_PTR_LO_1_VAL_MASK                                 0xFFFFFFFF
+
+/* MME0_QM_CQ_PTR_HI_1 */
+#define MME0_QM_CQ_PTR_HI_1_VAL_SHIFT                                0
+#define MME0_QM_CQ_PTR_HI_1_VAL_MASK                                 0xFFFFFFFF
+
+/* MME0_QM_CQ_TSIZE_1 */
+#define MME0_QM_CQ_TSIZE_1_VAL_SHIFT                                 0
+#define MME0_QM_CQ_TSIZE_1_VAL_MASK                                  0xFFFFFFFF
+
+/* MME0_QM_CQ_CTL_1 */
+#define MME0_QM_CQ_CTL_1_RPT_SHIFT                                   0
+#define MME0_QM_CQ_CTL_1_RPT_MASK                                    0xFFFF
+#define MME0_QM_CQ_CTL_1_CTL_SHIFT                                   16
+#define MME0_QM_CQ_CTL_1_CTL_MASK                                    0xFFFF0000
+
+/* MME0_QM_CQ_PTR_LO_2 */
+#define MME0_QM_CQ_PTR_LO_2_VAL_SHIFT                                0
+#define MME0_QM_CQ_PTR_LO_2_VAL_MASK                                 0xFFFFFFFF
+
+/* MME0_QM_CQ_PTR_HI_2 */
+#define MME0_QM_CQ_PTR_HI_2_VAL_SHIFT                                0
+#define MME0_QM_CQ_PTR_HI_2_VAL_MASK                                 0xFFFFFFFF
+
+/* MME0_QM_CQ_TSIZE_2 */
+#define MME0_QM_CQ_TSIZE_2_VAL_SHIFT                                 0
+#define MME0_QM_CQ_TSIZE_2_VAL_MASK                                  0xFFFFFFFF
+
+/* MME0_QM_CQ_CTL_2 */
+#define MME0_QM_CQ_CTL_2_RPT_SHIFT                                   0
+#define MME0_QM_CQ_CTL_2_RPT_MASK                                    0xFFFF
+#define MME0_QM_CQ_CTL_2_CTL_SHIFT                                   16
+#define MME0_QM_CQ_CTL_2_CTL_MASK                                    0xFFFF0000
+
+/* MME0_QM_CQ_PTR_LO_3 */
+#define MME0_QM_CQ_PTR_LO_3_VAL_SHIFT                                0
+#define MME0_QM_CQ_PTR_LO_3_VAL_MASK                                 0xFFFFFFFF
+
+/* MME0_QM_CQ_PTR_HI_3 */
+#define MME0_QM_CQ_PTR_HI_3_VAL_SHIFT                                0
+#define MME0_QM_CQ_PTR_HI_3_VAL_MASK                                 0xFFFFFFFF
+
+/* MME0_QM_CQ_TSIZE_3 */
+#define MME0_QM_CQ_TSIZE_3_VAL_SHIFT                                 0
+#define MME0_QM_CQ_TSIZE_3_VAL_MASK                                  0xFFFFFFFF
+
+/* MME0_QM_CQ_CTL_3 */
+#define MME0_QM_CQ_CTL_3_RPT_SHIFT                                   0
+#define MME0_QM_CQ_CTL_3_RPT_MASK                                    0xFFFF
+#define MME0_QM_CQ_CTL_3_CTL_SHIFT                                   16
+#define MME0_QM_CQ_CTL_3_CTL_MASK                                    0xFFFF0000
+
+/* MME0_QM_CQ_PTR_LO_4 */
+#define MME0_QM_CQ_PTR_LO_4_VAL_SHIFT                                0
+#define MME0_QM_CQ_PTR_LO_4_VAL_MASK                                 0xFFFFFFFF
+
+/* MME0_QM_CQ_PTR_HI_4 */
+#define MME0_QM_CQ_PTR_HI_4_VAL_SHIFT                                0
+#define MME0_QM_CQ_PTR_HI_4_VAL_MASK                                 0xFFFFFFFF
+
+/* MME0_QM_CQ_TSIZE_4 */
+#define MME0_QM_CQ_TSIZE_4_VAL_SHIFT                                 0
+#define MME0_QM_CQ_TSIZE_4_VAL_MASK                                  0xFFFFFFFF
+
+/* MME0_QM_CQ_CTL_4 */
+#define MME0_QM_CQ_CTL_4_RPT_SHIFT                                   0
+#define MME0_QM_CQ_CTL_4_RPT_MASK                                    0xFFFF
+#define MME0_QM_CQ_CTL_4_CTL_SHIFT                                   16
+#define MME0_QM_CQ_CTL_4_CTL_MASK                                    0xFFFF0000
+
+/* MME0_QM_CQ_PTR_LO_STS */
+#define MME0_QM_CQ_PTR_LO_STS_VAL_SHIFT                              0
+#define MME0_QM_CQ_PTR_LO_STS_VAL_MASK                               0xFFFFFFFF
+
+/* MME0_QM_CQ_PTR_HI_STS */
+#define MME0_QM_CQ_PTR_HI_STS_VAL_SHIFT                              0
+#define MME0_QM_CQ_PTR_HI_STS_VAL_MASK                               0xFFFFFFFF
+
+/* MME0_QM_CQ_TSIZE_STS */
+#define MME0_QM_CQ_TSIZE_STS_VAL_SHIFT                               0
+#define MME0_QM_CQ_TSIZE_STS_VAL_MASK                                0xFFFFFFFF
+
+/* MME0_QM_CQ_CTL_STS */
+#define MME0_QM_CQ_CTL_STS_RPT_SHIFT                                 0
+#define MME0_QM_CQ_CTL_STS_RPT_MASK                                  0xFFFF
+#define MME0_QM_CQ_CTL_STS_CTL_SHIFT                                 16
+#define MME0_QM_CQ_CTL_STS_CTL_MASK                                  0xFFFF0000
+
+/* MME0_QM_CQ_IFIFO_CNT */
+#define MME0_QM_CQ_IFIFO_CNT_VAL_SHIFT                               0
+#define MME0_QM_CQ_IFIFO_CNT_VAL_MASK                                0x3
+
+/* MME0_QM_CP_MSG_BASE0_ADDR_LO */
+#define MME0_QM_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT                       0
+#define MME0_QM_CP_MSG_BASE0_ADDR_LO_VAL_MASK                        0xFFFFFFFF
+
+/* MME0_QM_CP_MSG_BASE0_ADDR_HI */
+#define MME0_QM_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT                       0
+#define MME0_QM_CP_MSG_BASE0_ADDR_HI_VAL_MASK                        0xFFFFFFFF
+
+/* MME0_QM_CP_MSG_BASE1_ADDR_LO */
+#define MME0_QM_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT                       0
+#define MME0_QM_CP_MSG_BASE1_ADDR_LO_VAL_MASK                        0xFFFFFFFF
+
+/* MME0_QM_CP_MSG_BASE1_ADDR_HI */
+#define MME0_QM_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT                       0
+#define MME0_QM_CP_MSG_BASE1_ADDR_HI_VAL_MASK                        0xFFFFFFFF
+
+/* MME0_QM_CP_MSG_BASE2_ADDR_LO */
+#define MME0_QM_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT                       0
+#define MME0_QM_CP_MSG_BASE2_ADDR_LO_VAL_MASK                        0xFFFFFFFF
+
+/* MME0_QM_CP_MSG_BASE2_ADDR_HI */
+#define MME0_QM_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT                       0
+#define MME0_QM_CP_MSG_BASE2_ADDR_HI_VAL_MASK                        0xFFFFFFFF
+
+/* MME0_QM_CP_MSG_BASE3_ADDR_LO */
+#define MME0_QM_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT                       0
+#define MME0_QM_CP_MSG_BASE3_ADDR_LO_VAL_MASK                        0xFFFFFFFF
+
+/* MME0_QM_CP_MSG_BASE3_ADDR_HI */
+#define MME0_QM_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT                       0
+#define MME0_QM_CP_MSG_BASE3_ADDR_HI_VAL_MASK                        0xFFFFFFFF
+
+/* MME0_QM_CP_LDMA_TSIZE_OFFSET */
+#define MME0_QM_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT                       0
+#define MME0_QM_CP_LDMA_TSIZE_OFFSET_VAL_MASK                        0xFFFFFFFF
+
+/* MME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET */
+#define MME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT                 0
+#define MME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK                  0xFFFFFFFF
+
+/* MME0_QM_CP_LDMA_DST_BASE_LO_OFFSET */
+#define MME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT                 0
+#define MME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK                  0xFFFFFFFF
+
+/* MME0_QM_CP_FENCE0_RDATA */
+#define MME0_QM_CP_FENCE0_RDATA_INC_VAL_SHIFT                        0
+#define MME0_QM_CP_FENCE0_RDATA_INC_VAL_MASK                         0xF
+
+/* MME0_QM_CP_FENCE1_RDATA */
+#define MME0_QM_CP_FENCE1_RDATA_INC_VAL_SHIFT                        0
+#define MME0_QM_CP_FENCE1_RDATA_INC_VAL_MASK                         0xF
+
+/* MME0_QM_CP_FENCE2_RDATA */
+#define MME0_QM_CP_FENCE2_RDATA_INC_VAL_SHIFT                        0
+#define MME0_QM_CP_FENCE2_RDATA_INC_VAL_MASK                         0xF
+
+/* MME0_QM_CP_FENCE3_RDATA */
+#define MME0_QM_CP_FENCE3_RDATA_INC_VAL_SHIFT                        0
+#define MME0_QM_CP_FENCE3_RDATA_INC_VAL_MASK                         0xF
+
+/* MME0_QM_CP_FENCE0_CNT */
+#define MME0_QM_CP_FENCE0_CNT_VAL_SHIFT                              0
+#define MME0_QM_CP_FENCE0_CNT_VAL_MASK                               0x3FFF
+
+/* MME0_QM_CP_FENCE1_CNT */
+#define MME0_QM_CP_FENCE1_CNT_VAL_SHIFT                              0
+#define MME0_QM_CP_FENCE1_CNT_VAL_MASK                               0x3FFF
+
+/* MME0_QM_CP_FENCE2_CNT */
+#define MME0_QM_CP_FENCE2_CNT_VAL_SHIFT                              0
+#define MME0_QM_CP_FENCE2_CNT_VAL_MASK                               0x3FFF
+
+/* MME0_QM_CP_FENCE3_CNT */
+#define MME0_QM_CP_FENCE3_CNT_VAL_SHIFT                              0
+#define MME0_QM_CP_FENCE3_CNT_VAL_MASK                               0x3FFF
+
+/* MME0_QM_CP_STS */
+#define MME0_QM_CP_STS_MSG_INFLIGHT_CNT_SHIFT                        0
+#define MME0_QM_CP_STS_MSG_INFLIGHT_CNT_MASK                         0xFFFF
+#define MME0_QM_CP_STS_ERDY_SHIFT                                    16
+#define MME0_QM_CP_STS_ERDY_MASK                                     0x10000
+#define MME0_QM_CP_STS_RRDY_SHIFT                                    17
+#define MME0_QM_CP_STS_RRDY_MASK                                     0x20000
+#define MME0_QM_CP_STS_MRDY_SHIFT                                    18
+#define MME0_QM_CP_STS_MRDY_MASK                                     0x40000
+#define MME0_QM_CP_STS_SW_STOP_SHIFT                                 19
+#define MME0_QM_CP_STS_SW_STOP_MASK                                  0x80000
+#define MME0_QM_CP_STS_FENCE_ID_SHIFT                                20
+#define MME0_QM_CP_STS_FENCE_ID_MASK                                 0x300000
+#define MME0_QM_CP_STS_FENCE_IN_PROGRESS_SHIFT                       22
+#define MME0_QM_CP_STS_FENCE_IN_PROGRESS_MASK                        0x400000
+
+/* MME0_QM_CP_CURRENT_INST_LO */
+#define MME0_QM_CP_CURRENT_INST_LO_VAL_SHIFT                         0
+#define MME0_QM_CP_CURRENT_INST_LO_VAL_MASK                          0xFFFFFFFF
+
+/* MME0_QM_CP_CURRENT_INST_HI */
+#define MME0_QM_CP_CURRENT_INST_HI_VAL_SHIFT                         0
+#define MME0_QM_CP_CURRENT_INST_HI_VAL_MASK                          0xFFFFFFFF
+
+/* MME0_QM_CP_BARRIER_CFG */
+#define MME0_QM_CP_BARRIER_CFG_EBGUARD_SHIFT                         0
+#define MME0_QM_CP_BARRIER_CFG_EBGUARD_MASK                          0xFFF
+#define MME0_QM_CP_BARRIER_CFG_RBGUARD_SHIFT                         16
+#define MME0_QM_CP_BARRIER_CFG_RBGUARD_MASK                          0xF0000
+
+/* MME0_QM_CP_DBG_0 */
+#define MME0_QM_CP_DBG_0_CS_SHIFT                                    0
+#define MME0_QM_CP_DBG_0_CS_MASK                                     0xF
+#define MME0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_SHIFT                       4
+#define MME0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_MASK                        0x10
+#define MME0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_SHIFT                     5
+#define MME0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_MASK                      0x20
+#define MME0_QM_CP_DBG_0_MREB_STALL_SHIFT                            6
+#define MME0_QM_CP_DBG_0_MREB_STALL_MASK                             0x40
+#define MME0_QM_CP_DBG_0_STALL_SHIFT                                 7
+#define MME0_QM_CP_DBG_0_STALL_MASK                                  0x80
+
+/* MME0_QM_CP_ARUSER_31_11 */
+#define MME0_QM_CP_ARUSER_31_11_VAL_SHIFT                            0
+#define MME0_QM_CP_ARUSER_31_11_VAL_MASK                             0x1FFFFF
+
+/* MME0_QM_CP_AWUSER_31_11 */
+#define MME0_QM_CP_AWUSER_31_11_VAL_SHIFT                            0
+#define MME0_QM_CP_AWUSER_31_11_VAL_MASK                             0x1FFFFF
+
+/* MME0_QM_ARB_CFG_0 */
+#define MME0_QM_ARB_CFG_0_TYPE_SHIFT                                 0
+#define MME0_QM_ARB_CFG_0_TYPE_MASK                                  0x1
+#define MME0_QM_ARB_CFG_0_IS_MASTER_SHIFT                            4
+#define MME0_QM_ARB_CFG_0_IS_MASTER_MASK                             0x10
+#define MME0_QM_ARB_CFG_0_EN_SHIFT                                   8
+#define MME0_QM_ARB_CFG_0_EN_MASK                                    0x100
+#define MME0_QM_ARB_CFG_0_MASK_SHIFT                                 12
+#define MME0_QM_ARB_CFG_0_MASK_MASK                                  0xF000
+#define MME0_QM_ARB_CFG_0_MST_MSG_NOSTALL_SHIFT                      16
+#define MME0_QM_ARB_CFG_0_MST_MSG_NOSTALL_MASK                       0x10000
+
+/* MME0_QM_ARB_CHOISE_Q_PUSH */
+#define MME0_QM_ARB_CHOISE_Q_PUSH_VAL_SHIFT                          0
+#define MME0_QM_ARB_CHOISE_Q_PUSH_VAL_MASK                           0x3
+
+/* MME0_QM_ARB_WRR_WEIGHT */
+#define MME0_QM_ARB_WRR_WEIGHT_VAL_SHIFT                             0
+#define MME0_QM_ARB_WRR_WEIGHT_VAL_MASK                              0xFFFFFFFF
+
+/* MME0_QM_ARB_CFG_1 */
+#define MME0_QM_ARB_CFG_1_CLR_SHIFT                                  0
+#define MME0_QM_ARB_CFG_1_CLR_MASK                                   0x1
+
+/* MME0_QM_ARB_MST_AVAIL_CRED */
+#define MME0_QM_ARB_MST_AVAIL_CRED_VAL_SHIFT                         0
+#define MME0_QM_ARB_MST_AVAIL_CRED_VAL_MASK                          0x7F
+
+/* MME0_QM_ARB_MST_CRED_INC */
+#define MME0_QM_ARB_MST_CRED_INC_VAL_SHIFT                           0
+#define MME0_QM_ARB_MST_CRED_INC_VAL_MASK                            0xFFFFFFFF
+
+/* MME0_QM_ARB_MST_CHOISE_PUSH_OFST */
+#define MME0_QM_ARB_MST_CHOISE_PUSH_OFST_VAL_SHIFT                   0
+#define MME0_QM_ARB_MST_CHOISE_PUSH_OFST_VAL_MASK                    0xFFFFFFFF
+
+/* MME0_QM_ARB_SLV_MASTER_INC_CRED_OFST */
+#define MME0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_SHIFT               0
+#define MME0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_MASK                0xFFFFFFFF
+
+/* MME0_QM_ARB_MST_SLAVE_EN */
+#define MME0_QM_ARB_MST_SLAVE_EN_VAL_SHIFT                           0
+#define MME0_QM_ARB_MST_SLAVE_EN_VAL_MASK                            0xFFFFFFFF
+
+/* MME0_QM_ARB_MST_QUIET_PER */
+#define MME0_QM_ARB_MST_QUIET_PER_VAL_SHIFT                          0
+#define MME0_QM_ARB_MST_QUIET_PER_VAL_MASK                           0xFFFFFFFF
+
+/* MME0_QM_ARB_SLV_CHOISE_WDT */
+#define MME0_QM_ARB_SLV_CHOISE_WDT_VAL_SHIFT                         0
+#define MME0_QM_ARB_SLV_CHOISE_WDT_VAL_MASK                          0xFFFFFFFF
+
+/* MME0_QM_ARB_SLV_ID */
+#define MME0_QM_ARB_SLV_ID_VAL_SHIFT                                 0
+#define MME0_QM_ARB_SLV_ID_VAL_MASK                                  0x1F
+
+/* MME0_QM_ARB_MSG_MAX_INFLIGHT */
+#define MME0_QM_ARB_MSG_MAX_INFLIGHT_VAL_SHIFT                       0
+#define MME0_QM_ARB_MSG_MAX_INFLIGHT_VAL_MASK                        0x3F
+
+/* MME0_QM_ARB_MSG_AWUSER_31_11 */
+#define MME0_QM_ARB_MSG_AWUSER_31_11_VAL_SHIFT                       0
+#define MME0_QM_ARB_MSG_AWUSER_31_11_VAL_MASK                        0x1FFFFF
+
+/* MME0_QM_ARB_MSG_AWUSER_SEC_PROP */
+#define MME0_QM_ARB_MSG_AWUSER_SEC_PROP_ASID_SHIFT                   0
+#define MME0_QM_ARB_MSG_AWUSER_SEC_PROP_ASID_MASK                    0x3FF
+#define MME0_QM_ARB_MSG_AWUSER_SEC_PROP_MMBP_SHIFT                   10
+#define MME0_QM_ARB_MSG_AWUSER_SEC_PROP_MMBP_MASK                    0x400
+
+/* MME0_QM_ARB_MSG_AWUSER_NON_SEC_PROP */
+#define MME0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_SHIFT               0
+#define MME0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_MASK                0x3FF
+#define MME0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_SHIFT               10
+#define MME0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_MASK                0x400
+
+/* MME0_QM_ARB_BASE_LO */
+#define MME0_QM_ARB_BASE_LO_VAL_SHIFT                                0
+#define MME0_QM_ARB_BASE_LO_VAL_MASK                                 0xFFFFFFFF
+
+/* MME0_QM_ARB_BASE_HI */
+#define MME0_QM_ARB_BASE_HI_VAL_SHIFT                                0
+#define MME0_QM_ARB_BASE_HI_VAL_MASK                                 0xFFFFFFFF
+
+/* MME0_QM_ARB_STATE_STS */
+#define MME0_QM_ARB_STATE_STS_VAL_SHIFT                              0
+#define MME0_QM_ARB_STATE_STS_VAL_MASK                               0xFFFFFFFF
+
+/* MME0_QM_ARB_CHOISE_FULLNESS_STS */
+#define MME0_QM_ARB_CHOISE_FULLNESS_STS_VAL_SHIFT                    0
+#define MME0_QM_ARB_CHOISE_FULLNESS_STS_VAL_MASK                     0x7F
+
+/* MME0_QM_ARB_MSG_STS */
+#define MME0_QM_ARB_MSG_STS_FULL_SHIFT                               0
+#define MME0_QM_ARB_MSG_STS_FULL_MASK                                0x1
+#define MME0_QM_ARB_MSG_STS_NO_INFLIGHT_SHIFT                        1
+#define MME0_QM_ARB_MSG_STS_NO_INFLIGHT_MASK                         0x2
+
+/* MME0_QM_ARB_SLV_CHOISE_Q_HEAD */
+#define MME0_QM_ARB_SLV_CHOISE_Q_HEAD_VAL_SHIFT                      0
+#define MME0_QM_ARB_SLV_CHOISE_Q_HEAD_VAL_MASK                       0x3
+
+/* MME0_QM_ARB_ERR_CAUSE */
+#define MME0_QM_ARB_ERR_CAUSE_CHOISE_OVF_SHIFT                       0
+#define MME0_QM_ARB_ERR_CAUSE_CHOISE_OVF_MASK                        0x1
+#define MME0_QM_ARB_ERR_CAUSE_CHOISE_WDT_SHIFT                       1
+#define MME0_QM_ARB_ERR_CAUSE_CHOISE_WDT_MASK                        0x2
+#define MME0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_SHIFT                      2
+#define MME0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_MASK                       0x4
+
+/* MME0_QM_ARB_ERR_MSG_EN */
+#define MME0_QM_ARB_ERR_MSG_EN_CHOISE_OVF_SHIFT                      0
+#define MME0_QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK                       0x1
+#define MME0_QM_ARB_ERR_MSG_EN_CHOISE_WDT_SHIFT                      1
+#define MME0_QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK                       0x2
+#define MME0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_SHIFT                     2
+#define MME0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK                      0x4
+
+/* MME0_QM_ARB_ERR_STS_DRP */
+#define MME0_QM_ARB_ERR_STS_DRP_VAL_SHIFT                            0
+#define MME0_QM_ARB_ERR_STS_DRP_VAL_MASK                             0x3
+
+/* MME0_QM_ARB_MST_CRED_STS */
+#define MME0_QM_ARB_MST_CRED_STS_VAL_SHIFT                           0
+#define MME0_QM_ARB_MST_CRED_STS_VAL_MASK                            0x7F
+
+/* MME0_QM_CGM_CFG */
+#define MME0_QM_CGM_CFG_IDLE_TH_SHIFT                                0
+#define MME0_QM_CGM_CFG_IDLE_TH_MASK                                 0xFFF
+#define MME0_QM_CGM_CFG_G2F_TH_SHIFT                                 16
+#define MME0_QM_CGM_CFG_G2F_TH_MASK                                  0xFF0000
+#define MME0_QM_CGM_CFG_CP_IDLE_MASK_SHIFT                           24
+#define MME0_QM_CGM_CFG_CP_IDLE_MASK_MASK                            0x1F000000
+#define MME0_QM_CGM_CFG_EN_SHIFT                                     31
+#define MME0_QM_CGM_CFG_EN_MASK                                      0x80000000
+
+/* MME0_QM_CGM_STS */
+#define MME0_QM_CGM_STS_ST_SHIFT                                     0
+#define MME0_QM_CGM_STS_ST_MASK                                      0x3
+#define MME0_QM_CGM_STS_CG_SHIFT                                     4
+#define MME0_QM_CGM_STS_CG_MASK                                      0x10
+#define MME0_QM_CGM_STS_AGENT_IDLE_SHIFT                             8
+#define MME0_QM_CGM_STS_AGENT_IDLE_MASK                              0x100
+#define MME0_QM_CGM_STS_AXI_IDLE_SHIFT                               9
+#define MME0_QM_CGM_STS_AXI_IDLE_MASK                                0x200
+#define MME0_QM_CGM_STS_CP_IDLE_SHIFT                                10
+#define MME0_QM_CGM_STS_CP_IDLE_MASK                                 0x400
+
+/* MME0_QM_CGM_CFG1 */
+#define MME0_QM_CGM_CFG1_MASK_TH_SHIFT                               0
+#define MME0_QM_CGM_CFG1_MASK_TH_MASK                                0xFF
+
+/* MME0_QM_LOCAL_RANGE_BASE */
+#define MME0_QM_LOCAL_RANGE_BASE_VAL_SHIFT                           0
+#define MME0_QM_LOCAL_RANGE_BASE_VAL_MASK                            0xFFFF
+
+/* MME0_QM_LOCAL_RANGE_SIZE */
+#define MME0_QM_LOCAL_RANGE_SIZE_VAL_SHIFT                           0
+#define MME0_QM_LOCAL_RANGE_SIZE_VAL_MASK                            0xFFFF
+
+/* MME0_QM_CSMR_STRICT_PRIO_CFG */
+#define MME0_QM_CSMR_STRICT_PRIO_CFG_TYPE_SHIFT                      0
+#define MME0_QM_CSMR_STRICT_PRIO_CFG_TYPE_MASK                       0x1
+
+/* MME0_QM_HBW_RD_RATE_LIM_CFG_1 */
+#define MME0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_SHIFT                     0
+#define MME0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_MASK                      0xFF
+#define MME0_QM_HBW_RD_RATE_LIM_CFG_1_EN_SHIFT                       31
+#define MME0_QM_HBW_RD_RATE_LIM_CFG_1_EN_MASK                        0x80000000
+
+/* MME0_QM_LBW_WR_RATE_LIM_CFG_0 */
+#define MME0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT                0
+#define MME0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK                 0xFF
+#define MME0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_SHIFT                      16
+#define MME0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_MASK                       0xFF0000
+
+/* MME0_QM_LBW_WR_RATE_LIM_CFG_1 */
+#define MME0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_SHIFT                     0
+#define MME0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_MASK                      0xFF
+#define MME0_QM_LBW_WR_RATE_LIM_CFG_1_EN_SHIFT                       31
+#define MME0_QM_LBW_WR_RATE_LIM_CFG_1_EN_MASK                        0x80000000
+
+/* MME0_QM_HBW_RD_RATE_LIM_CFG_0 */
+#define MME0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT                0
+#define MME0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK                 0xFF
+#define MME0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_SHIFT                      16
+#define MME0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_MASK                       0xFF0000
+
+/* MME0_QM_GLBL_AXCACHE */
+#define MME0_QM_GLBL_AXCACHE_AR_SHIFT                                0
+#define MME0_QM_GLBL_AXCACHE_AR_MASK                                 0xF
+#define MME0_QM_GLBL_AXCACHE_AW_SHIFT                                16
+#define MME0_QM_GLBL_AXCACHE_AW_MASK                                 0xF0000
+
+/* MME0_QM_IND_GW_APB_CFG */
+#define MME0_QM_IND_GW_APB_CFG_ADDR_SHIFT                            0
+#define MME0_QM_IND_GW_APB_CFG_ADDR_MASK                             0x7FFFFFFF
+#define MME0_QM_IND_GW_APB_CFG_CMD_SHIFT                             31
+#define MME0_QM_IND_GW_APB_CFG_CMD_MASK                              0x80000000
+
+/* MME0_QM_IND_GW_APB_WDATA */
+#define MME0_QM_IND_GW_APB_WDATA_VAL_SHIFT                           0
+#define MME0_QM_IND_GW_APB_WDATA_VAL_MASK                            0xFFFFFFFF
+
+/* MME0_QM_IND_GW_APB_RDATA */
+#define MME0_QM_IND_GW_APB_RDATA_VAL_SHIFT                           0
+#define MME0_QM_IND_GW_APB_RDATA_VAL_MASK                            0xFFFFFFFF
+
+/* MME0_QM_IND_GW_APB_STATUS */
+#define MME0_QM_IND_GW_APB_STATUS_RDY_SHIFT                          0
+#define MME0_QM_IND_GW_APB_STATUS_RDY_MASK                           0x1
+#define MME0_QM_IND_GW_APB_STATUS_ERR_SHIFT                          1
+#define MME0_QM_IND_GW_APB_STATUS_ERR_MASK                           0x2
+
+/* MME0_QM_GLBL_ERR_ADDR_LO */
+#define MME0_QM_GLBL_ERR_ADDR_LO_VAL_SHIFT                           0
+#define MME0_QM_GLBL_ERR_ADDR_LO_VAL_MASK                            0xFFFFFFFF
+
+/* MME0_QM_GLBL_ERR_ADDR_HI */
+#define MME0_QM_GLBL_ERR_ADDR_HI_VAL_SHIFT                           0
+#define MME0_QM_GLBL_ERR_ADDR_HI_VAL_MASK                            0xFFFFFFFF
+
+/* MME0_QM_GLBL_ERR_WDATA */
+#define MME0_QM_GLBL_ERR_WDATA_VAL_SHIFT                             0
+#define MME0_QM_GLBL_ERR_WDATA_VAL_MASK                              0xFFFFFFFF
+
+/* MME0_QM_GLBL_MEM_INIT_BUSY */
+#define MME0_QM_GLBL_MEM_INIT_BUSY_RBUF_SHIFT                        0
+#define MME0_QM_GLBL_MEM_INIT_BUSY_RBUF_MASK                         0xF
+
+#endif /* ASIC_REG_MME0_QM_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/mme0_qm_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/mme0_qm_regs.h
new file mode 100644
index 000000000000..4f078b328b00
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/mme0_qm_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_MME0_QM_REGS_H_
+#define ASIC_REG_MME0_QM_REGS_H_
+
+/*
+ *****************************************
+ *   MME0_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmMME0_QM_GLBL_CFG0                                          0x68000
+
+#define mmMME0_QM_GLBL_CFG1                                          0x68004
+
+#define mmMME0_QM_GLBL_PROT                                          0x68008
+
+#define mmMME0_QM_GLBL_ERR_CFG                                       0x6800C
+
+#define mmMME0_QM_GLBL_SECURE_PROPS_0                                0x68010
+
+#define mmMME0_QM_GLBL_SECURE_PROPS_1                                0x68014
+
+#define mmMME0_QM_GLBL_SECURE_PROPS_2                                0x68018
+
+#define mmMME0_QM_GLBL_SECURE_PROPS_3                                0x6801C
+
+#define mmMME0_QM_GLBL_SECURE_PROPS_4                                0x68020
+
+#define mmMME0_QM_GLBL_NON_SECURE_PROPS_0                            0x68024
+
+#define mmMME0_QM_GLBL_NON_SECURE_PROPS_1                            0x68028
+
+#define mmMME0_QM_GLBL_NON_SECURE_PROPS_2                            0x6802C
+
+#define mmMME0_QM_GLBL_NON_SECURE_PROPS_3                            0x68030
+
+#define mmMME0_QM_GLBL_NON_SECURE_PROPS_4                            0x68034
+
+#define mmMME0_QM_GLBL_STS0                                          0x68038
+
+#define mmMME0_QM_GLBL_STS1_0                                        0x68040
+
+#define mmMME0_QM_GLBL_STS1_1                                        0x68044
+
+#define mmMME0_QM_GLBL_STS1_2                                        0x68048
+
+#define mmMME0_QM_GLBL_STS1_3                                        0x6804C
+
+#define mmMME0_QM_GLBL_STS1_4                                        0x68050
+
+#define mmMME0_QM_GLBL_MSG_EN_0                                      0x68054
+
+#define mmMME0_QM_GLBL_MSG_EN_1                                      0x68058
+
+#define mmMME0_QM_GLBL_MSG_EN_2                                      0x6805C
+
+#define mmMME0_QM_GLBL_MSG_EN_3                                      0x68060
+
+#define mmMME0_QM_GLBL_MSG_EN_4                                      0x68068
+
+#define mmMME0_QM_PQ_BASE_LO_0                                       0x68070
+
+#define mmMME0_QM_PQ_BASE_LO_1                                       0x68074
+
+#define mmMME0_QM_PQ_BASE_LO_2                                       0x68078
+
+#define mmMME0_QM_PQ_BASE_LO_3                                       0x6807C
+
+#define mmMME0_QM_PQ_BASE_HI_0                                       0x68080
+
+#define mmMME0_QM_PQ_BASE_HI_1                                       0x68084
+
+#define mmMME0_QM_PQ_BASE_HI_2                                       0x68088
+
+#define mmMME0_QM_PQ_BASE_HI_3                                       0x6808C
+
+#define mmMME0_QM_PQ_SIZE_0                                          0x68090
+
+#define mmMME0_QM_PQ_SIZE_1                                          0x68094
+
+#define mmMME0_QM_PQ_SIZE_2                                          0x68098
+
+#define mmMME0_QM_PQ_SIZE_3                                          0x6809C
+
+#define mmMME0_QM_PQ_PI_0                                            0x680A0
+
+#define mmMME0_QM_PQ_PI_1                                            0x680A4
+
+#define mmMME0_QM_PQ_PI_2                                            0x680A8
+
+#define mmMME0_QM_PQ_PI_3                                            0x680AC
+
+#define mmMME0_QM_PQ_CI_0                                            0x680B0
+
+#define mmMME0_QM_PQ_CI_1                                            0x680B4
+
+#define mmMME0_QM_PQ_CI_2                                            0x680B8
+
+#define mmMME0_QM_PQ_CI_3                                            0x680BC
+
+#define mmMME0_QM_PQ_CFG0_0                                          0x680C0
+
+#define mmMME0_QM_PQ_CFG0_1                                          0x680C4
+
+#define mmMME0_QM_PQ_CFG0_2                                          0x680C8
+
+#define mmMME0_QM_PQ_CFG0_3                                          0x680CC
+
+#define mmMME0_QM_PQ_CFG1_0                                          0x680D0
+
+#define mmMME0_QM_PQ_CFG1_1                                          0x680D4
+
+#define mmMME0_QM_PQ_CFG1_2                                          0x680D8
+
+#define mmMME0_QM_PQ_CFG1_3                                          0x680DC
+
+#define mmMME0_QM_PQ_ARUSER_31_11_0                                  0x680E0
+
+#define mmMME0_QM_PQ_ARUSER_31_11_1                                  0x680E4
+
+#define mmMME0_QM_PQ_ARUSER_31_11_2                                  0x680E8
+
+#define mmMME0_QM_PQ_ARUSER_31_11_3                                  0x680EC
+
+#define mmMME0_QM_PQ_STS0_0                                          0x680F0
+
+#define mmMME0_QM_PQ_STS0_1                                          0x680F4
+
+#define mmMME0_QM_PQ_STS0_2                                          0x680F8
+
+#define mmMME0_QM_PQ_STS0_3                                          0x680FC
+
+#define mmMME0_QM_PQ_STS1_0                                          0x68100
+
+#define mmMME0_QM_PQ_STS1_1                                          0x68104
+
+#define mmMME0_QM_PQ_STS1_2                                          0x68108
+
+#define mmMME0_QM_PQ_STS1_3                                          0x6810C
+
+#define mmMME0_QM_CQ_CFG0_0                                          0x68110
+
+#define mmMME0_QM_CQ_CFG0_1                                          0x68114
+
+#define mmMME0_QM_CQ_CFG0_2                                          0x68118
+
+#define mmMME0_QM_CQ_CFG0_3                                          0x6811C
+
+#define mmMME0_QM_CQ_CFG0_4                                          0x68120
+
+#define mmMME0_QM_CQ_CFG1_0                                          0x68124
+
+#define mmMME0_QM_CQ_CFG1_1                                          0x68128
+
+#define mmMME0_QM_CQ_CFG1_2                                          0x6812C
+
+#define mmMME0_QM_CQ_CFG1_3                                          0x68130
+
+#define mmMME0_QM_CQ_CFG1_4                                          0x68134
+
+#define mmMME0_QM_CQ_ARUSER_31_11_0                                  0x68138
+
+#define mmMME0_QM_CQ_ARUSER_31_11_1                                  0x6813C
+
+#define mmMME0_QM_CQ_ARUSER_31_11_2                                  0x68140
+
+#define mmMME0_QM_CQ_ARUSER_31_11_3                                  0x68144
+
+#define mmMME0_QM_CQ_ARUSER_31_11_4                                  0x68148
+
+#define mmMME0_QM_CQ_STS0_0                                          0x6814C
+
+#define mmMME0_QM_CQ_STS0_1                                          0x68150
+
+#define mmMME0_QM_CQ_STS0_2                                          0x68154
+
+#define mmMME0_QM_CQ_STS0_3                                          0x68158
+
+#define mmMME0_QM_CQ_STS0_4                                          0x6815C
+
+#define mmMME0_QM_CQ_STS1_0                                          0x68160
+
+#define mmMME0_QM_CQ_STS1_1                                          0x68164
+
+#define mmMME0_QM_CQ_STS1_2                                          0x68168
+
+#define mmMME0_QM_CQ_STS1_3                                          0x6816C
+
+#define mmMME0_QM_CQ_STS1_4                                          0x68170
+
+#define mmMME0_QM_CQ_PTR_LO_0                                        0x68174
+
+#define mmMME0_QM_CQ_PTR_HI_0                                        0x68178
+
+#define mmMME0_QM_CQ_TSIZE_0                                         0x6817C
+
+#define mmMME0_QM_CQ_CTL_0                                           0x68180
+
+#define mmMME0_QM_CQ_PTR_LO_1                                        0x68184
+
+#define mmMME0_QM_CQ_PTR_HI_1                                        0x68188
+
+#define mmMME0_QM_CQ_TSIZE_1                                         0x6818C
+
+#define mmMME0_QM_CQ_CTL_1                                           0x68190
+
+#define mmMME0_QM_CQ_PTR_LO_2                                        0x68194
+
+#define mmMME0_QM_CQ_PTR_HI_2                                        0x68198
+
+#define mmMME0_QM_CQ_TSIZE_2                                         0x6819C
+
+#define mmMME0_QM_CQ_CTL_2                                           0x681A0
+
+#define mmMME0_QM_CQ_PTR_LO_3                                        0x681A4
+
+#define mmMME0_QM_CQ_PTR_HI_3                                        0x681A8
+
+#define mmMME0_QM_CQ_TSIZE_3                                         0x681AC
+
+#define mmMME0_QM_CQ_CTL_3                                           0x681B0
+
+#define mmMME0_QM_CQ_PTR_LO_4                                        0x681B4
+
+#define mmMME0_QM_CQ_PTR_HI_4                                        0x681B8
+
+#define mmMME0_QM_CQ_TSIZE_4                                         0x681BC
+
+#define mmMME0_QM_CQ_CTL_4                                           0x681C0
+
+#define mmMME0_QM_CQ_PTR_LO_STS_0                                    0x681C4
+
+#define mmMME0_QM_CQ_PTR_LO_STS_1                                    0x681C8
+
+#define mmMME0_QM_CQ_PTR_LO_STS_2                                    0x681CC
+
+#define mmMME0_QM_CQ_PTR_LO_STS_3                                    0x681D0
+
+#define mmMME0_QM_CQ_PTR_LO_STS_4                                    0x681D4
+
+#define mmMME0_QM_CQ_PTR_HI_STS_0                                    0x681D8
+
+#define mmMME0_QM_CQ_PTR_HI_STS_1                                    0x681DC
+
+#define mmMME0_QM_CQ_PTR_HI_STS_2                                    0x681E0
+
+#define mmMME0_QM_CQ_PTR_HI_STS_3                                    0x681E4
+
+#define mmMME0_QM_CQ_PTR_HI_STS_4                                    0x681E8
+
+#define mmMME0_QM_CQ_TSIZE_STS_0                                     0x681EC
+
+#define mmMME0_QM_CQ_TSIZE_STS_1                                     0x681F0
+
+#define mmMME0_QM_CQ_TSIZE_STS_2                                     0x681F4
+
+#define mmMME0_QM_CQ_TSIZE_STS_3                                     0x681F8
+
+#define mmMME0_QM_CQ_TSIZE_STS_4                                     0x681FC
+
+#define mmMME0_QM_CQ_CTL_STS_0                                       0x68200
+
+#define mmMME0_QM_CQ_CTL_STS_1                                       0x68204
+
+#define mmMME0_QM_CQ_CTL_STS_2                                       0x68208
+
+#define mmMME0_QM_CQ_CTL_STS_3                                       0x6820C
+
+#define mmMME0_QM_CQ_CTL_STS_4                                       0x68210
+
+#define mmMME0_QM_CQ_IFIFO_CNT_0                                     0x68214
+
+#define mmMME0_QM_CQ_IFIFO_CNT_1                                     0x68218
+
+#define mmMME0_QM_CQ_IFIFO_CNT_2                                     0x6821C
+
+#define mmMME0_QM_CQ_IFIFO_CNT_3                                     0x68220
+
+#define mmMME0_QM_CQ_IFIFO_CNT_4                                     0x68224
+
+#define mmMME0_QM_CP_MSG_BASE0_ADDR_LO_0                             0x68228
+
+#define mmMME0_QM_CP_MSG_BASE0_ADDR_LO_1                             0x6822C
+
+#define mmMME0_QM_CP_MSG_BASE0_ADDR_LO_2                             0x68230
+
+#define mmMME0_QM_CP_MSG_BASE0_ADDR_LO_3                             0x68234
+
+#define mmMME0_QM_CP_MSG_BASE0_ADDR_LO_4                             0x68238
+
+#define mmMME0_QM_CP_MSG_BASE0_ADDR_HI_0                             0x6823C
+
+#define mmMME0_QM_CP_MSG_BASE0_ADDR_HI_1                             0x68240
+
+#define mmMME0_QM_CP_MSG_BASE0_ADDR_HI_2                             0x68244
+
+#define mmMME0_QM_CP_MSG_BASE0_ADDR_HI_3                             0x68248
+
+#define mmMME0_QM_CP_MSG_BASE0_ADDR_HI_4                             0x6824C
+
+#define mmMME0_QM_CP_MSG_BASE1_ADDR_LO_0                             0x68250
+
+#define mmMME0_QM_CP_MSG_BASE1_ADDR_LO_1                             0x68254
+
+#define mmMME0_QM_CP_MSG_BASE1_ADDR_LO_2                             0x68258
+
+#define mmMME0_QM_CP_MSG_BASE1_ADDR_LO_3                             0x6825C
+
+#define mmMME0_QM_CP_MSG_BASE1_ADDR_LO_4                             0x68260
+
+#define mmMME0_QM_CP_MSG_BASE1_ADDR_HI_0                             0x68264
+
+#define mmMME0_QM_CP_MSG_BASE1_ADDR_HI_1                             0x68268
+
+#define mmMME0_QM_CP_MSG_BASE1_ADDR_HI_2                             0x6826C
+
+#define mmMME0_QM_CP_MSG_BASE1_ADDR_HI_3                             0x68270
+
+#define mmMME0_QM_CP_MSG_BASE1_ADDR_HI_4                             0x68274
+
+#define mmMME0_QM_CP_MSG_BASE2_ADDR_LO_0                             0x68278
+
+#define mmMME0_QM_CP_MSG_BASE2_ADDR_LO_1                             0x6827C
+
+#define mmMME0_QM_CP_MSG_BASE2_ADDR_LO_2                             0x68280
+
+#define mmMME0_QM_CP_MSG_BASE2_ADDR_LO_3                             0x68284
+
+#define mmMME0_QM_CP_MSG_BASE2_ADDR_LO_4                             0x68288
+
+#define mmMME0_QM_CP_MSG_BASE2_ADDR_HI_0                             0x6828C
+
+#define mmMME0_QM_CP_MSG_BASE2_ADDR_HI_1                             0x68290
+
+#define mmMME0_QM_CP_MSG_BASE2_ADDR_HI_2                             0x68294
+
+#define mmMME0_QM_CP_MSG_BASE2_ADDR_HI_3                             0x68298
+
+#define mmMME0_QM_CP_MSG_BASE2_ADDR_HI_4                             0x6829C
+
+#define mmMME0_QM_CP_MSG_BASE3_ADDR_LO_0                             0x682A0
+
+#define mmMME0_QM_CP_MSG_BASE3_ADDR_LO_1                             0x682A4
+
+#define mmMME0_QM_CP_MSG_BASE3_ADDR_LO_2                             0x682A8
+
+#define mmMME0_QM_CP_MSG_BASE3_ADDR_LO_3                             0x682AC
+
+#define mmMME0_QM_CP_MSG_BASE3_ADDR_LO_4                             0x682B0
+
+#define mmMME0_QM_CP_MSG_BASE3_ADDR_HI_0                             0x682B4
+
+#define mmMME0_QM_CP_MSG_BASE3_ADDR_HI_1                             0x682B8
+
+#define mmMME0_QM_CP_MSG_BASE3_ADDR_HI_2                             0x682BC
+
+#define mmMME0_QM_CP_MSG_BASE3_ADDR_HI_3                             0x682C0
+
+#define mmMME0_QM_CP_MSG_BASE3_ADDR_HI_4                             0x682C4
+
+#define mmMME0_QM_CP_LDMA_TSIZE_OFFSET_0                             0x682C8
+
+#define mmMME0_QM_CP_LDMA_TSIZE_OFFSET_1                             0x682CC
+
+#define mmMME0_QM_CP_LDMA_TSIZE_OFFSET_2                             0x682D0
+
+#define mmMME0_QM_CP_LDMA_TSIZE_OFFSET_3                             0x682D4
+
+#define mmMME0_QM_CP_LDMA_TSIZE_OFFSET_4                             0x682D8
+
+#define mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0                       0x682E0
+
+#define mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1                       0x682E4
+
+#define mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2                       0x682E8
+
+#define mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3                       0x682EC
+
+#define mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4                       0x682F0
+
+#define mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0                       0x682F4
+
+#define mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1                       0x682F8
+
+#define mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2                       0x682FC
+
+#define mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3                       0x68300
+
+#define mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4                       0x68304
+
+#define mmMME0_QM_CP_FENCE0_RDATA_0                                  0x68308
+
+#define mmMME0_QM_CP_FENCE0_RDATA_1                                  0x6830C
+
+#define mmMME0_QM_CP_FENCE0_RDATA_2                                  0x68310
+
+#define mmMME0_QM_CP_FENCE0_RDATA_3                                  0x68314
+
+#define mmMME0_QM_CP_FENCE0_RDATA_4                                  0x68318
+
+#define mmMME0_QM_CP_FENCE1_RDATA_0                                  0x6831C
+
+#define mmMME0_QM_CP_FENCE1_RDATA_1                                  0x68320
+
+#define mmMME0_QM_CP_FENCE1_RDATA_2                                  0x68324
+
+#define mmMME0_QM_CP_FENCE1_RDATA_3                                  0x68328
+
+#define mmMME0_QM_CP_FENCE1_RDATA_4                                  0x6832C
+
+#define mmMME0_QM_CP_FENCE2_RDATA_0                                  0x68330
+
+#define mmMME0_QM_CP_FENCE2_RDATA_1                                  0x68334
+
+#define mmMME0_QM_CP_FENCE2_RDATA_2                                  0x68338
+
+#define mmMME0_QM_CP_FENCE2_RDATA_3                                  0x6833C
+
+#define mmMME0_QM_CP_FENCE2_RDATA_4                                  0x68340
+
+#define mmMME0_QM_CP_FENCE3_RDATA_0                                  0x68344
+
+#define mmMME0_QM_CP_FENCE3_RDATA_1                                  0x68348
+
+#define mmMME0_QM_CP_FENCE3_RDATA_2                                  0x6834C
+
+#define mmMME0_QM_CP_FENCE3_RDATA_3                                  0x68350
+
+#define mmMME0_QM_CP_FENCE3_RDATA_4                                  0x68354
+
+#define mmMME0_QM_CP_FENCE0_CNT_0                                    0x68358
+
+#define mmMME0_QM_CP_FENCE0_CNT_1                                    0x6835C
+
+#define mmMME0_QM_CP_FENCE0_CNT_2                                    0x68360
+
+#define mmMME0_QM_CP_FENCE0_CNT_3                                    0x68364
+
+#define mmMME0_QM_CP_FENCE0_CNT_4                                    0x68368
+
+#define mmMME0_QM_CP_FENCE1_CNT_0                                    0x6836C
+
+#define mmMME0_QM_CP_FENCE1_CNT_1                                    0x68370
+
+#define mmMME0_QM_CP_FENCE1_CNT_2                                    0x68374
+
+#define mmMME0_QM_CP_FENCE1_CNT_3                                    0x68378
+
+#define mmMME0_QM_CP_FENCE1_CNT_4                                    0x6837C
+
+#define mmMME0_QM_CP_FENCE2_CNT_0                                    0x68380
+
+#define mmMME0_QM_CP_FENCE2_CNT_1                                    0x68384
+
+#define mmMME0_QM_CP_FENCE2_CNT_2                                    0x68388
+
+#define mmMME0_QM_CP_FENCE2_CNT_3                                    0x6838C
+
+#define mmMME0_QM_CP_FENCE2_CNT_4                                    0x68390
+
+#define mmMME0_QM_CP_FENCE3_CNT_0                                    0x68394
+
+#define mmMME0_QM_CP_FENCE3_CNT_1                                    0x68398
+
+#define mmMME0_QM_CP_FENCE3_CNT_2                                    0x6839C
+
+#define mmMME0_QM_CP_FENCE3_CNT_3                                    0x683A0
+
+#define mmMME0_QM_CP_FENCE3_CNT_4                                    0x683A4
+
+#define mmMME0_QM_CP_STS_0                                           0x683A8
+
+#define mmMME0_QM_CP_STS_1                                           0x683AC
+
+#define mmMME0_QM_CP_STS_2                                           0x683B0
+
+#define mmMME0_QM_CP_STS_3                                           0x683B4
+
+#define mmMME0_QM_CP_STS_4                                           0x683B8
+
+#define mmMME0_QM_CP_CURRENT_INST_LO_0                               0x683BC
+
+#define mmMME0_QM_CP_CURRENT_INST_LO_1                               0x683C0
+
+#define mmMME0_QM_CP_CURRENT_INST_LO_2                               0x683C4
+
+#define mmMME0_QM_CP_CURRENT_INST_LO_3                               0x683C8
+
+#define mmMME0_QM_CP_CURRENT_INST_LO_4                               0x683CC
+
+#define mmMME0_QM_CP_CURRENT_INST_HI_0                               0x683D0
+
+#define mmMME0_QM_CP_CURRENT_INST_HI_1                               0x683D4
+
+#define mmMME0_QM_CP_CURRENT_INST_HI_2                               0x683D8
+
+#define mmMME0_QM_CP_CURRENT_INST_HI_3                               0x683DC
+
+#define mmMME0_QM_CP_CURRENT_INST_HI_4                               0x683E0
+
+#define mmMME0_QM_CP_BARRIER_CFG_0                                   0x683F4
+
+#define mmMME0_QM_CP_BARRIER_CFG_1                                   0x683F8
+
+#define mmMME0_QM_CP_BARRIER_CFG_2                                   0x683FC
+
+#define mmMME0_QM_CP_BARRIER_CFG_3                                   0x68400
+
+#define mmMME0_QM_CP_BARRIER_CFG_4                                   0x68404
+
+#define mmMME0_QM_CP_DBG_0_0                                         0x68408
+
+#define mmMME0_QM_CP_DBG_0_1                                         0x6840C
+
+#define mmMME0_QM_CP_DBG_0_2                                         0x68410
+
+#define mmMME0_QM_CP_DBG_0_3                                         0x68414
+
+#define mmMME0_QM_CP_DBG_0_4                                         0x68418
+
+#define mmMME0_QM_CP_ARUSER_31_11_0                                  0x6841C
+
+#define mmMME0_QM_CP_ARUSER_31_11_1                                  0x68420
+
+#define mmMME0_QM_CP_ARUSER_31_11_2                                  0x68424
+
+#define mmMME0_QM_CP_ARUSER_31_11_3                                  0x68428
+
+#define mmMME0_QM_CP_ARUSER_31_11_4                                  0x6842C
+
+#define mmMME0_QM_CP_AWUSER_31_11_0                                  0x68430
+
+#define mmMME0_QM_CP_AWUSER_31_11_1                                  0x68434
+
+#define mmMME0_QM_CP_AWUSER_31_11_2                                  0x68438
+
+#define mmMME0_QM_CP_AWUSER_31_11_3                                  0x6843C
+
+#define mmMME0_QM_CP_AWUSER_31_11_4                                  0x68440
+
+#define mmMME0_QM_ARB_CFG_0                                          0x68A00
+
+#define mmMME0_QM_ARB_CHOISE_Q_PUSH                                  0x68A04
+
+#define mmMME0_QM_ARB_WRR_WEIGHT_0                                   0x68A08
+
+#define mmMME0_QM_ARB_WRR_WEIGHT_1                                   0x68A0C
+
+#define mmMME0_QM_ARB_WRR_WEIGHT_2                                   0x68A10
+
+#define mmMME0_QM_ARB_WRR_WEIGHT_3                                   0x68A14
+
+#define mmMME0_QM_ARB_CFG_1                                          0x68A18
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_0                               0x68A20
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_1                               0x68A24
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_2                               0x68A28
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_3                               0x68A2C
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_4                               0x68A30
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_5                               0x68A34
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_6                               0x68A38
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_7                               0x68A3C
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_8                               0x68A40
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_9                               0x68A44
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_10                              0x68A48
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_11                              0x68A4C
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_12                              0x68A50
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_13                              0x68A54
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_14                              0x68A58
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_15                              0x68A5C
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_16                              0x68A60
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_17                              0x68A64
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_18                              0x68A68
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_19                              0x68A6C
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_20                              0x68A70
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_21                              0x68A74
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_22                              0x68A78
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_23                              0x68A7C
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_24                              0x68A80
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_25                              0x68A84
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_26                              0x68A88
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_27                              0x68A8C
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_28                              0x68A90
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_29                              0x68A94
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_30                              0x68A98
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_31                              0x68A9C
+
+#define mmMME0_QM_ARB_MST_CRED_INC                                   0x68AA0
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_0                         0x68AA4
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_1                         0x68AA8
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_2                         0x68AAC
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_3                         0x68AB0
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_4                         0x68AB4
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_5                         0x68AB8
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_6                         0x68ABC
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_7                         0x68AC0
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_8                         0x68AC4
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_9                         0x68AC8
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_10                        0x68ACC
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_11                        0x68AD0
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_12                        0x68AD4
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_13                        0x68AD8
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_14                        0x68ADC
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_15                        0x68AE0
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_16                        0x68AE4
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_17                        0x68AE8
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_18                        0x68AEC
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_19                        0x68AF0
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_20                        0x68AF4
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_21                        0x68AF8
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_22                        0x68AFC
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_23                        0x68B00
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_24                        0x68B04
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_25                        0x68B08
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_26                        0x68B0C
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_27                        0x68B10
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_28                        0x68B14
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_29                        0x68B18
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_30                        0x68B1C
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_31                        0x68B20
+
+#define mmMME0_QM_ARB_SLV_MASTER_INC_CRED_OFST                       0x68B28
+
+#define mmMME0_QM_ARB_MST_SLAVE_EN                                   0x68B2C
+
+#define mmMME0_QM_ARB_MST_QUIET_PER                                  0x68B34
+
+#define mmMME0_QM_ARB_SLV_CHOISE_WDT                                 0x68B38
+
+#define mmMME0_QM_ARB_SLV_ID                                         0x68B3C
+
+#define mmMME0_QM_ARB_MSG_MAX_INFLIGHT                               0x68B44
+
+#define mmMME0_QM_ARB_MSG_AWUSER_31_11                               0x68B48
+
+#define mmMME0_QM_ARB_MSG_AWUSER_SEC_PROP                            0x68B4C
+
+#define mmMME0_QM_ARB_MSG_AWUSER_NON_SEC_PROP                        0x68B50
+
+#define mmMME0_QM_ARB_BASE_LO                                        0x68B54
+
+#define mmMME0_QM_ARB_BASE_HI                                        0x68B58
+
+#define mmMME0_QM_ARB_STATE_STS                                      0x68B80
+
+#define mmMME0_QM_ARB_CHOISE_FULLNESS_STS                            0x68B84
+
+#define mmMME0_QM_ARB_MSG_STS                                        0x68B88
+
+#define mmMME0_QM_ARB_SLV_CHOISE_Q_HEAD                              0x68B8C
+
+#define mmMME0_QM_ARB_ERR_CAUSE                                      0x68B9C
+
+#define mmMME0_QM_ARB_ERR_MSG_EN                                     0x68BA0
+
+#define mmMME0_QM_ARB_ERR_STS_DRP                                    0x68BA8
+
+#define mmMME0_QM_ARB_MST_CRED_STS_0                                 0x68BB0
+
+#define mmMME0_QM_ARB_MST_CRED_STS_1                                 0x68BB4
+
+#define mmMME0_QM_ARB_MST_CRED_STS_2                                 0x68BB8
+
+#define mmMME0_QM_ARB_MST_CRED_STS_3                                 0x68BBC
+
+#define mmMME0_QM_ARB_MST_CRED_STS_4                                 0x68BC0
+
+#define mmMME0_QM_ARB_MST_CRED_STS_5                                 0x68BC4
+
+#define mmMME0_QM_ARB_MST_CRED_STS_6                                 0x68BC8
+
+#define mmMME0_QM_ARB_MST_CRED_STS_7                                 0x68BCC
+
+#define mmMME0_QM_ARB_MST_CRED_STS_8                                 0x68BD0
+
+#define mmMME0_QM_ARB_MST_CRED_STS_9                                 0x68BD4
+
+#define mmMME0_QM_ARB_MST_CRED_STS_10                                0x68BD8
+
+#define mmMME0_QM_ARB_MST_CRED_STS_11                                0x68BDC
+
+#define mmMME0_QM_ARB_MST_CRED_STS_12                                0x68BE0
+
+#define mmMME0_QM_ARB_MST_CRED_STS_13                                0x68BE4
+
+#define mmMME0_QM_ARB_MST_CRED_STS_14                                0x68BE8
+
+#define mmMME0_QM_ARB_MST_CRED_STS_15                                0x68BEC
+
+#define mmMME0_QM_ARB_MST_CRED_STS_16                                0x68BF0
+
+#define mmMME0_QM_ARB_MST_CRED_STS_17                                0x68BF4
+
+#define mmMME0_QM_ARB_MST_CRED_STS_18                                0x68BF8
+
+#define mmMME0_QM_ARB_MST_CRED_STS_19                                0x68BFC
+
+#define mmMME0_QM_ARB_MST_CRED_STS_20                                0x68C00
+
+#define mmMME0_QM_ARB_MST_CRED_STS_21                                0x68C04
+
+#define mmMME0_QM_ARB_MST_CRED_STS_22                                0x68C08
+
+#define mmMME0_QM_ARB_MST_CRED_STS_23                                0x68C0C
+
+#define mmMME0_QM_ARB_MST_CRED_STS_24                                0x68C10
+
+#define mmMME0_QM_ARB_MST_CRED_STS_25                                0x68C14
+
+#define mmMME0_QM_ARB_MST_CRED_STS_26                                0x68C18
+
+#define mmMME0_QM_ARB_MST_CRED_STS_27                                0x68C1C
+
+#define mmMME0_QM_ARB_MST_CRED_STS_28                                0x68C20
+
+#define mmMME0_QM_ARB_MST_CRED_STS_29                                0x68C24
+
+#define mmMME0_QM_ARB_MST_CRED_STS_30                                0x68C28
+
+#define mmMME0_QM_ARB_MST_CRED_STS_31                                0x68C2C
+
+#define mmMME0_QM_CGM_CFG                                            0x68C70
+
+#define mmMME0_QM_CGM_STS                                            0x68C74
+
+#define mmMME0_QM_CGM_CFG1                                           0x68C78
+
+#define mmMME0_QM_LOCAL_RANGE_BASE                                   0x68C80
+
+#define mmMME0_QM_LOCAL_RANGE_SIZE                                   0x68C84
+
+#define mmMME0_QM_CSMR_STRICT_PRIO_CFG                               0x68C90
+
+#define mmMME0_QM_HBW_RD_RATE_LIM_CFG_1                              0x68C94
+
+#define mmMME0_QM_LBW_WR_RATE_LIM_CFG_0                              0x68C98
+
+#define mmMME0_QM_LBW_WR_RATE_LIM_CFG_1                              0x68C9C
+
+#define mmMME0_QM_HBW_RD_RATE_LIM_CFG_0                              0x68CA0
+
+#define mmMME0_QM_GLBL_AXCACHE                                       0x68CA4
+
+#define mmMME0_QM_IND_GW_APB_CFG                                     0x68CB0
+
+#define mmMME0_QM_IND_GW_APB_WDATA                                   0x68CB4
+
+#define mmMME0_QM_IND_GW_APB_RDATA                                   0x68CB8
+
+#define mmMME0_QM_IND_GW_APB_STATUS                                  0x68CBC
+
+#define mmMME0_QM_GLBL_ERR_ADDR_LO                                   0x68CD0
+
+#define mmMME0_QM_GLBL_ERR_ADDR_HI                                   0x68CD4
+
+#define mmMME0_QM_GLBL_ERR_WDATA                                     0x68CD8
+
+#define mmMME0_QM_GLBL_MEM_INIT_BUSY                                 0x68D00
+
+#endif /* ASIC_REG_MME0_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/mme1_ctrl_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/mme1_ctrl_regs.h
new file mode 100644
index 000000000000..6c07f7d45490
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/mme1_ctrl_regs.h
@@ -0,0 +1,1456 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_MME1_CTRL_REGS_H_
+#define ASIC_REG_MME1_CTRL_REGS_H_
+
+/*
+ *****************************************
+ *   MME1_CTRL (Prototype: MME)
+ *****************************************
+ */
+
+#define mmMME1_CTRL_ARCH_STATUS                                      0xE0000
+
+#define mmMME1_CTRL_ARCH_BASE_ADDR_HIGH_S                            0xE0008
+
+#define mmMME1_CTRL_ARCH_BASE_ADDR_HIGH_L                            0xE000C
+
+#define mmMME1_CTRL_ARCH_BASE_ADDR_HIGH_O                            0xE0010
+
+#define mmMME1_CTRL_ARCH_BASE_ADDR_LOW_S                             0xE0014
+
+#define mmMME1_CTRL_ARCH_BASE_ADDR_LOW_L                             0xE0018
+
+#define mmMME1_CTRL_ARCH_BASE_ADDR_LOW_O                             0xE001C
+
+#define mmMME1_CTRL_ARCH_HEADER_LOW                                  0xE0020
+
+#define mmMME1_CTRL_ARCH_HEADER_HIGH                                 0xE0024
+
+#define mmMME1_CTRL_ARCH_CONV_KERNEL_SIZE_MINUS_1                    0xE0028
+
+#define mmMME1_CTRL_ARCH_CONV_ASSOCIATED_DIMS_LOW                    0xE002C
+
+#define mmMME1_CTRL_ARCH_CONV_ASSOCIATED_DIMS_HIGH                   0xE0030
+
+#define mmMME1_CTRL_ARCH_NUM_ITERATIONS_MINUS_1                      0xE0034
+
+#define mmMME1_CTRL_ARCH_OUTER_LOOP                                  0xE0038
+
+#define mmMME1_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_0                   0xE003C
+
+#define mmMME1_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_1                   0xE0040
+
+#define mmMME1_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_2                   0xE0044
+
+#define mmMME1_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_3                   0xE0048
+
+#define mmMME1_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_4                   0xE004C
+
+#define mmMME1_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_0                      0xE0050
+
+#define mmMME1_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_1                      0xE0054
+
+#define mmMME1_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_2                      0xE0058
+
+#define mmMME1_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_3                      0xE005C
+
+#define mmMME1_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_4                      0xE0060
+
+#define mmMME1_CTRL_ARCH_TENSOR_S_ROI_SIZE_0                         0xE0064
+
+#define mmMME1_CTRL_ARCH_TENSOR_S_ROI_SIZE_1                         0xE0068
+
+#define mmMME1_CTRL_ARCH_TENSOR_S_ROI_SIZE_2                         0xE006C
+
+#define mmMME1_CTRL_ARCH_TENSOR_S_ROI_SIZE_3                         0xE0070
+
+#define mmMME1_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_0                  0xE0074
+
+#define mmMME1_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_1                  0xE0078
+
+#define mmMME1_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_2                  0xE007C
+
+#define mmMME1_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_3                  0xE0080
+
+#define mmMME1_CTRL_ARCH_TENSOR_S_SPATIAL_SIZE_MINUS_1               0xE0084
+
+#define mmMME1_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_0                     0xE0088
+
+#define mmMME1_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_1                     0xE008C
+
+#define mmMME1_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_2                     0xE0090
+
+#define mmMME1_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_3                     0xE0094
+
+#define mmMME1_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_4                     0xE0098
+
+#define mmMME1_CTRL_ARCH_AGU_S_START_OFFSET_0                        0xE009C
+
+#define mmMME1_CTRL_ARCH_AGU_S_START_OFFSET_1                        0xE00A0
+
+#define mmMME1_CTRL_ARCH_AGU_S_START_OFFSET_2                        0xE00A4
+
+#define mmMME1_CTRL_ARCH_AGU_S_START_OFFSET_3                        0xE00A8
+
+#define mmMME1_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_0                   0xE00AC
+
+#define mmMME1_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_1                   0xE00B0
+
+#define mmMME1_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_2                   0xE00B4
+
+#define mmMME1_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_3                   0xE00B8
+
+#define mmMME1_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_4                   0xE00BC
+
+#define mmMME1_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_0                      0xE00C0
+
+#define mmMME1_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_1                      0xE00C4
+
+#define mmMME1_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_2                      0xE00C8
+
+#define mmMME1_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_3                      0xE00CC
+
+#define mmMME1_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_4                      0xE00D0
+
+#define mmMME1_CTRL_ARCH_TENSOR_L_ROI_SIZE_0                         0xE00D4
+
+#define mmMME1_CTRL_ARCH_TENSOR_L_ROI_SIZE_1                         0xE00D8
+
+#define mmMME1_CTRL_ARCH_TENSOR_L_ROI_SIZE_2                         0xE00DC
+
+#define mmMME1_CTRL_ARCH_TENSOR_L_ROI_SIZE_3                         0xE00E0
+
+#define mmMME1_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_0                  0xE00E4
+
+#define mmMME1_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_1                  0xE00E8
+
+#define mmMME1_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_2                  0xE00EC
+
+#define mmMME1_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_3                  0xE00F0
+
+#define mmMME1_CTRL_ARCH_TENSOR_L_SPATIAL_SIZE_MINUS_1               0xE00F4
+
+#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_0               0xE00F8
+
+#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_1               0xE00FC
+
+#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_2               0xE0100
+
+#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_3               0xE0104
+
+#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_4               0xE0108
+
+#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_0                  0xE010C
+
+#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_1                  0xE0110
+
+#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_2                  0xE0114
+
+#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_3                  0xE0118
+
+#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_0              0xE011C
+
+#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_1              0xE0120
+
+#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_2              0xE0124
+
+#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_3              0xE0128
+
+#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_4              0xE012C
+
+#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_0                 0xE0130
+
+#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_1                 0xE0134
+
+#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_2                 0xE0138
+
+#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_3                 0xE013C
+
+#define mmMME1_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_0                   0xE0140
+
+#define mmMME1_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_1                   0xE0144
+
+#define mmMME1_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_2                   0xE0148
+
+#define mmMME1_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_3                   0xE014C
+
+#define mmMME1_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_4                   0xE0150
+
+#define mmMME1_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_0                      0xE0154
+
+#define mmMME1_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_1                      0xE0158
+
+#define mmMME1_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_2                      0xE015C
+
+#define mmMME1_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_3                      0xE0160
+
+#define mmMME1_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_4                      0xE0164
+
+#define mmMME1_CTRL_ARCH_TENSOR_O_ROI_SIZE_0                         0xE0168
+
+#define mmMME1_CTRL_ARCH_TENSOR_O_ROI_SIZE_1                         0xE016C
+
+#define mmMME1_CTRL_ARCH_TENSOR_O_ROI_SIZE_2                         0xE0170
+
+#define mmMME1_CTRL_ARCH_TENSOR_O_ROI_SIZE_3                         0xE0174
+
+#define mmMME1_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_0                  0xE0178
+
+#define mmMME1_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_1                  0xE017C
+
+#define mmMME1_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_2                  0xE0180
+
+#define mmMME1_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_3                  0xE0184
+
+#define mmMME1_CTRL_ARCH_TENSOR_O_SPATIAL_SIZE_MINUS_1               0xE0188
+
+#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_0               0xE018C
+
+#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_1               0xE0190
+
+#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_2               0xE0194
+
+#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_3               0xE0198
+
+#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_4               0xE019C
+
+#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_0                  0xE01A0
+
+#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_1                  0xE01A4
+
+#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_2                  0xE01A8
+
+#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_3                  0xE01AC
+
+#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_0              0xE01B0
+
+#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_1              0xE01B4
+
+#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_2              0xE01B8
+
+#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_3              0xE01BC
+
+#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_4              0xE01C0
+
+#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_0                 0xE01C4
+
+#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_1                 0xE01C8
+
+#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_2                 0xE01CC
+
+#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_3                 0xE01D0
+
+#define mmMME1_CTRL_ARCH_DESC_SB_REPEAT                              0xE01D4
+
+#define mmMME1_CTRL_ARCH_DESC_RATE_LIMITER                           0xE01D8
+
+#define mmMME1_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL             0xE01DC
+
+#define mmMME1_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE            0xE01E0
+
+#define mmMME1_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_HIGH                  0xE01E4
+
+#define mmMME1_CTRL_ARCH_DESC_SYNC_OBJECT_DATA                       0xE01E8
+
+#define mmMME1_CTRL_ARCH_DESC_AXI_USER_DATA                          0xE01EC
+
+#define mmMME1_CTRL_ARCH_DESC_PERF_EVT_S                             0xE01F0
+
+#define mmMME1_CTRL_ARCH_DESC_PERF_EVT_L_LOCAL                       0xE01F4
+
+#define mmMME1_CTRL_ARCH_DESC_PERF_EVT_L_REMOTE                      0xE01F8
+
+#define mmMME1_CTRL_ARCH_DESC_PERF_EVT_O_LOCAL                       0xE01FC
+
+#define mmMME1_CTRL_ARCH_DESC_PERF_EVT_O_REMOTE                      0xE0200
+
+#define mmMME1_CTRL_ARCH_DESC_PADDING_VALUE_S                        0xE0204
+
+#define mmMME1_CTRL_ARCH_DESC_PADDING_VALUE_L                        0xE0208
+
+#define mmMME1_CTRL_ARCH_DESC_META_DATA_AGU_S                        0xE020C
+
+#define mmMME1_CTRL_ARCH_DESC_META_DATA_AGU_L_LOCAL                  0xE0210
+
+#define mmMME1_CTRL_ARCH_DESC_META_DATA_AGU_L_REMOTE                 0xE0214
+
+#define mmMME1_CTRL_ARCH_DESC_META_DATA_AGU_O_LOCAL                  0xE0218
+
+#define mmMME1_CTRL_ARCH_DESC_META_DATA_AGU_O_REMOTE                 0xE021C
+
+#define mmMME1_CTRL_ARCH_DESC_PCU_RL_SATURATION                      0xE0220
+
+#define mmMME1_CTRL_ARCH_DESC_DUMMY                                  0xE0224
+
+#define mmMME1_CTRL_CMD                                              0xE0280
+
+#define mmMME1_CTRL_STATUS1                                          0xE0284
+
+#define mmMME1_CTRL_RESET                                            0xE0288
+
+#define mmMME1_CTRL_QM_STALL                                         0xE028C
+
+#define mmMME1_CTRL_SYNC_OBJECT_FIFO_TH                              0xE0290
+
+#define mmMME1_CTRL_EUS_ROLLUP_CNT_ADD                               0xE0294
+
+#define mmMME1_CTRL_INTR_CAUSE                                       0xE0298
+
+#define mmMME1_CTRL_INTR_MASK                                        0xE029C
+
+#define mmMME1_CTRL_LOG_SHADOW                                       0xE02A0
+
+#define mmMME1_CTRL_PCU_RL_DESC0                                     0xE02A4
+
+#define mmMME1_CTRL_PCU_RL_TOKEN_UPDATE                              0xE02A8
+
+#define mmMME1_CTRL_PCU_RL_TH                                        0xE02AC
+
+#define mmMME1_CTRL_PCU_RL_MIN                                       0xE02B0
+
+#define mmMME1_CTRL_PCU_RL_CTRL_EN                                   0xE02B4
+
+#define mmMME1_CTRL_PCU_RL_HISTORY_LOG_SIZE                          0xE02B8
+
+#define mmMME1_CTRL_PCU_DUMMY_A_BF16                                 0xE02BC
+
+#define mmMME1_CTRL_PCU_DUMMY_B_BF16                                 0xE02C0
+
+#define mmMME1_CTRL_PCU_DUMMY_A_FP32_ODD                             0xE02C4
+
+#define mmMME1_CTRL_PCU_DUMMY_A_FP32_EVEN                            0xE02C8
+
+#define mmMME1_CTRL_PCU_DUMMY_B_FP32_ODD                             0xE02CC
+
+#define mmMME1_CTRL_PCU_DUMMY_B_FP32_EVEN                            0xE02D0
+
+#define mmMME1_CTRL_PROT                                             0xE02D4
+
+#define mmMME1_CTRL_EU_POWER_SAVE_DISABLE                            0xE02D8
+
+#define mmMME1_CTRL_CS_DBG_BLOCK_ID                                  0xE02DC
+
+#define mmMME1_CTRL_CS_DBG_STATUS_DROP_CNT                           0xE02E0
+
+#define mmMME1_CTRL_TE_CLOSE_CGATE                                   0xE02E4
+
+#define mmMME1_CTRL_AGU_SM_INFLIGHT_CNTR                             0xE02E8
+
+#define mmMME1_CTRL_AGU_SM_TOTAL_CNTR                                0xE02EC
+
+#define mmMME1_CTRL_EZSYNC_OUT_CREDIT                                0xE02F0
+
+#define mmMME1_CTRL_PCU_RL_SAT_SEC                                   0xE02F4
+
+#define mmMME1_CTRL_AGU_SYNC_MSG_AXI_USER                            0xE02F8
+
+#define mmMME1_CTRL_QM_SLV_LBW_CLK_EN                                0xE02FC
+
+#define mmMME1_CTRL_SHADOW_0_STATUS                                  0xE0400
+
+#define mmMME1_CTRL_SHADOW_0_BASE_ADDR_HIGH_S                        0xE0408
+
+#define mmMME1_CTRL_SHADOW_0_BASE_ADDR_HIGH_L                        0xE040C
+
+#define mmMME1_CTRL_SHADOW_0_BASE_ADDR_HIGH_O                        0xE0410
+
+#define mmMME1_CTRL_SHADOW_0_BASE_ADDR_LOW_S                         0xE0414
+
+#define mmMME1_CTRL_SHADOW_0_BASE_ADDR_LOW_L                         0xE0418
+
+#define mmMME1_CTRL_SHADOW_0_BASE_ADDR_LOW_O                         0xE041C
+
+#define mmMME1_CTRL_SHADOW_0_HEADER_LOW                              0xE0420
+
+#define mmMME1_CTRL_SHADOW_0_HEADER_HIGH                             0xE0424
+
+#define mmMME1_CTRL_SHADOW_0_CONV_KERNEL_SIZE_MINUS_1                0xE0428
+
+#define mmMME1_CTRL_SHADOW_0_CONV_ASSOCIATED_DIMS_LOW                0xE042C
+
+#define mmMME1_CTRL_SHADOW_0_CONV_ASSOCIATED_DIMS_HIGH               0xE0430
+
+#define mmMME1_CTRL_SHADOW_0_NUM_ITERATIONS_MINUS_1                  0xE0434
+
+#define mmMME1_CTRL_SHADOW_0_OUTER_LOOP                              0xE0438
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_0               0xE043C
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_1               0xE0440
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_2               0xE0444
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_3               0xE0448
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_4               0xE044C
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_0                  0xE0450
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_1                  0xE0454
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_2                  0xE0458
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_3                  0xE045C
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_4                  0xE0460
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_0                     0xE0464
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_1                     0xE0468
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_2                     0xE046C
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_3                     0xE0470
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_0              0xE0474
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_1              0xE0478
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_2              0xE047C
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_3              0xE0480
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_S_SPATIAL_SIZE_MINUS_1           0xE0484
+
+#define mmMME1_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_0                 0xE0488
+
+#define mmMME1_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_1                 0xE048C
+
+#define mmMME1_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_2                 0xE0490
+
+#define mmMME1_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_3                 0xE0494
+
+#define mmMME1_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_4                 0xE0498
+
+#define mmMME1_CTRL_SHADOW_0_AGU_S_START_OFFSET_0                    0xE049C
+
+#define mmMME1_CTRL_SHADOW_0_AGU_S_START_OFFSET_1                    0xE04A0
+
+#define mmMME1_CTRL_SHADOW_0_AGU_S_START_OFFSET_2                    0xE04A4
+
+#define mmMME1_CTRL_SHADOW_0_AGU_S_START_OFFSET_3                    0xE04A8
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_0               0xE04AC
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_1               0xE04B0
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_2               0xE04B4
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_3               0xE04B8
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_4               0xE04BC
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_0                  0xE04C0
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_1                  0xE04C4
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_2                  0xE04C8
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_3                  0xE04CC
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_4                  0xE04D0
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_0                     0xE04D4
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_1                     0xE04D8
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_2                     0xE04DC
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_3                     0xE04E0
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_0              0xE04E4
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_1              0xE04E8
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_2              0xE04EC
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_3              0xE04F0
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_L_SPATIAL_SIZE_MINUS_1           0xE04F4
+
+#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_0           0xE04F8
+
+#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_1           0xE04FC
+
+#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_2           0xE0500
+
+#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_3           0xE0504
+
+#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_4           0xE0508
+
+#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_0              0xE050C
+
+#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_1              0xE0510
+
+#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_2              0xE0514
+
+#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_3              0xE0518
+
+#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_0          0xE051C
+
+#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_1          0xE0520
+
+#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_2          0xE0524
+
+#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_3          0xE0528
+
+#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_4          0xE052C
+
+#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_0             0xE0530
+
+#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_1             0xE0534
+
+#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_2             0xE0538
+
+#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_3             0xE053C
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_0               0xE0540
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_1               0xE0544
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_2               0xE0548
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_3               0xE054C
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_4               0xE0550
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_0                  0xE0554
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_1                  0xE0558
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_2                  0xE055C
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_3                  0xE0560
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_4                  0xE0564
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_0                     0xE0568
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_1                     0xE056C
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_2                     0xE0570
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_3                     0xE0574
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_0              0xE0578
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_1              0xE057C
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_2              0xE0580
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_3              0xE0584
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_O_SPATIAL_SIZE_MINUS_1           0xE0588
+
+#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_0           0xE058C
+
+#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_1           0xE0590
+
+#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_2           0xE0594
+
+#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_3           0xE0598
+
+#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_4           0xE059C
+
+#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_0              0xE05A0
+
+#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_1              0xE05A4
+
+#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_2              0xE05A8
+
+#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_3              0xE05AC
+
+#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_0          0xE05B0
+
+#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_1          0xE05B4
+
+#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_2          0xE05B8
+
+#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_3          0xE05BC
+
+#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_4          0xE05C0
+
+#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_0             0xE05C4
+
+#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_1             0xE05C8
+
+#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_2             0xE05CC
+
+#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_3             0xE05D0
+
+#define mmMME1_CTRL_SHADOW_0_DESC_SB_REPEAT                          0xE05D4
+
+#define mmMME1_CTRL_SHADOW_0_DESC_RATE_LIMITER                       0xE05D8
+
+#define mmMME1_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL         0xE05DC
+
+#define mmMME1_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE        0xE05E0
+
+#define mmMME1_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_HIGH              0xE05E4
+
+#define mmMME1_CTRL_SHADOW_0_DESC_SYNC_OBJECT_DATA                   0xE05E8
+
+#define mmMME1_CTRL_SHADOW_0_DESC_AXI_USER_DATA                      0xE05EC
+
+#define mmMME1_CTRL_SHADOW_0_DESC_PERF_EVT_S                         0xE05F0
+
+#define mmMME1_CTRL_SHADOW_0_DESC_PERF_EVT_L_LOCAL                   0xE05F4
+
+#define mmMME1_CTRL_SHADOW_0_DESC_PERF_EVT_L_REMOTE                  0xE05F8
+
+#define mmMME1_CTRL_SHADOW_0_DESC_PERF_EVT_O_LOCAL                   0xE05FC
+
+#define mmMME1_CTRL_SHADOW_0_DESC_PERF_EVT_O_REMOTE                  0xE0600
+
+#define mmMME1_CTRL_SHADOW_0_DESC_PADDING_VALUE_S                    0xE0604
+
+#define mmMME1_CTRL_SHADOW_0_DESC_PADDING_VALUE_L                    0xE0608
+
+#define mmMME1_CTRL_SHADOW_0_DESC_META_DATA_AGU_S                    0xE060C
+
+#define mmMME1_CTRL_SHADOW_0_DESC_META_DATA_AGU_L_LOCAL              0xE0610
+
+#define mmMME1_CTRL_SHADOW_0_DESC_META_DATA_AGU_L_REMOTE             0xE0614
+
+#define mmMME1_CTRL_SHADOW_0_DESC_META_DATA_AGU_O_LOCAL              0xE0618
+
+#define mmMME1_CTRL_SHADOW_0_DESC_META_DATA_AGU_O_REMOTE             0xE061C
+
+#define mmMME1_CTRL_SHADOW_0_DESC_PCU_RL_SATURATION                  0xE0620
+
+#define mmMME1_CTRL_SHADOW_0_DESC_DUMMY                              0xE0624
+
+#define mmMME1_CTRL_SHADOW_1_STATUS                                  0xE0680
+
+#define mmMME1_CTRL_SHADOW_1_BASE_ADDR_HIGH_S                        0xE0688
+
+#define mmMME1_CTRL_SHADOW_1_BASE_ADDR_HIGH_L                        0xE068C
+
+#define mmMME1_CTRL_SHADOW_1_BASE_ADDR_HIGH_O                        0xE0690
+
+#define mmMME1_CTRL_SHADOW_1_BASE_ADDR_LOW_S                         0xE0694
+
+#define mmMME1_CTRL_SHADOW_1_BASE_ADDR_LOW_L                         0xE0698
+
+#define mmMME1_CTRL_SHADOW_1_BASE_ADDR_LOW_O                         0xE069C
+
+#define mmMME1_CTRL_SHADOW_1_HEADER_LOW                              0xE06A0
+
+#define mmMME1_CTRL_SHADOW_1_HEADER_HIGH                             0xE06A4
+
+#define mmMME1_CTRL_SHADOW_1_CONV_KERNEL_SIZE_MINUS_1                0xE06A8
+
+#define mmMME1_CTRL_SHADOW_1_CONV_ASSOCIATED_DIMS_LOW                0xE06AC
+
+#define mmMME1_CTRL_SHADOW_1_CONV_ASSOCIATED_DIMS_HIGH               0xE06B0
+
+#define mmMME1_CTRL_SHADOW_1_NUM_ITERATIONS_MINUS_1                  0xE06B4
+
+#define mmMME1_CTRL_SHADOW_1_OUTER_LOOP                              0xE06B8
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_0               0xE06BC
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_1               0xE06C0
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_2               0xE06C4
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_3               0xE06C8
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_4               0xE06CC
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_0                  0xE06D0
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_1                  0xE06D4
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_2                  0xE06D8
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_3                  0xE06DC
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_4                  0xE06E0
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_0                     0xE06E4
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_1                     0xE06E8
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_2                     0xE06EC
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_3                     0xE06F0
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_0              0xE06F4
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_1              0xE06F8
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_2              0xE06FC
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_3              0xE0700
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_S_SPATIAL_SIZE_MINUS_1           0xE0704
+
+#define mmMME1_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_0                 0xE0708
+
+#define mmMME1_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_1                 0xE070C
+
+#define mmMME1_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_2                 0xE0710
+
+#define mmMME1_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_3                 0xE0714
+
+#define mmMME1_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_4                 0xE0718
+
+#define mmMME1_CTRL_SHADOW_1_AGU_S_START_OFFSET_0                    0xE071C
+
+#define mmMME1_CTRL_SHADOW_1_AGU_S_START_OFFSET_1                    0xE0720
+
+#define mmMME1_CTRL_SHADOW_1_AGU_S_START_OFFSET_2                    0xE0724
+
+#define mmMME1_CTRL_SHADOW_1_AGU_S_START_OFFSET_3                    0xE0728
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_0               0xE072C
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_1               0xE0730
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_2               0xE0734
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_3               0xE0738
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_4               0xE073C
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_0                  0xE0740
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_1                  0xE0744
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_2                  0xE0748
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_3                  0xE074C
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_4                  0xE0750
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_0                     0xE0754
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_1                     0xE0758
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_2                     0xE075C
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_3                     0xE0760
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_0              0xE0764
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_1              0xE0768
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_2              0xE076C
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_3              0xE0770
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_L_SPATIAL_SIZE_MINUS_1           0xE0774
+
+#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_0           0xE0778
+
+#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_1           0xE077C
+
+#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_2           0xE0780
+
+#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_3           0xE0784
+
+#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_4           0xE0788
+
+#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_0              0xE078C
+
+#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_1              0xE0790
+
+#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_2              0xE0794
+
+#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_3              0xE0798
+
+#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_0          0xE079C
+
+#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_1          0xE07A0
+
+#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_2          0xE07A4
+
+#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_3          0xE07A8
+
+#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_4          0xE07AC
+
+#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_0             0xE07B0
+
+#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_1             0xE07B4
+
+#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_2             0xE07B8
+
+#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_3             0xE07BC
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_0               0xE07C0
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_1               0xE07C4
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_2               0xE07C8
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_3               0xE07CC
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_4               0xE07D0
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_0                  0xE07D4
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_1                  0xE07D8
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_2                  0xE07DC
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_3                  0xE07E0
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_4                  0xE07E4
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_0                     0xE07E8
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_1                     0xE07EC
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_2                     0xE07F0
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_3                     0xE07F4
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_0              0xE07F8
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_1              0xE07FC
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_2              0xE0800
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_3              0xE0804
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_O_SPATIAL_SIZE_MINUS_1           0xE0808
+
+#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_0           0xE080C
+
+#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_1           0xE0810
+
+#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_2           0xE0814
+
+#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_3           0xE0818
+
+#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_4           0xE081C
+
+#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_0              0xE0820
+
+#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_1              0xE0824
+
+#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_2              0xE0828
+
+#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_3              0xE082C
+
+#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_0          0xE0830
+
+#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_1          0xE0834
+
+#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_2          0xE0838
+
+#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_3          0xE083C
+
+#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_4          0xE0840
+
+#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_0             0xE0844
+
+#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_1             0xE0848
+
+#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_2             0xE084C
+
+#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_3             0xE0850
+
+#define mmMME1_CTRL_SHADOW_1_DESC_SB_REPEAT                          0xE0854
+
+#define mmMME1_CTRL_SHADOW_1_DESC_RATE_LIMITER                       0xE0858
+
+#define mmMME1_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL         0xE085C
+
+#define mmMME1_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE        0xE0860
+
+#define mmMME1_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_HIGH              0xE0864
+
+#define mmMME1_CTRL_SHADOW_1_DESC_SYNC_OBJECT_DATA                   0xE0868
+
+#define mmMME1_CTRL_SHADOW_1_DESC_AXI_USER_DATA                      0xE086C
+
+#define mmMME1_CTRL_SHADOW_1_DESC_PERF_EVT_S                         0xE0870
+
+#define mmMME1_CTRL_SHADOW_1_DESC_PERF_EVT_L_LOCAL                   0xE0874
+
+#define mmMME1_CTRL_SHADOW_1_DESC_PERF_EVT_L_REMOTE                  0xE0878
+
+#define mmMME1_CTRL_SHADOW_1_DESC_PERF_EVT_O_LOCAL                   0xE087C
+
+#define mmMME1_CTRL_SHADOW_1_DESC_PERF_EVT_O_REMOTE                  0xE0880
+
+#define mmMME1_CTRL_SHADOW_1_DESC_PADDING_VALUE_S                    0xE0884
+
+#define mmMME1_CTRL_SHADOW_1_DESC_PADDING_VALUE_L                    0xE0888
+
+#define mmMME1_CTRL_SHADOW_1_DESC_META_DATA_AGU_S                    0xE088C
+
+#define mmMME1_CTRL_SHADOW_1_DESC_META_DATA_AGU_L_LOCAL              0xE0890
+
+#define mmMME1_CTRL_SHADOW_1_DESC_META_DATA_AGU_L_REMOTE             0xE0894
+
+#define mmMME1_CTRL_SHADOW_1_DESC_META_DATA_AGU_O_LOCAL              0xE0898
+
+#define mmMME1_CTRL_SHADOW_1_DESC_META_DATA_AGU_O_REMOTE             0xE089C
+
+#define mmMME1_CTRL_SHADOW_1_DESC_PCU_RL_SATURATION                  0xE08A0
+
+#define mmMME1_CTRL_SHADOW_1_DESC_DUMMY                              0xE08A4
+
+#define mmMME1_CTRL_SHADOW_2_STATUS                                  0xE0900
+
+#define mmMME1_CTRL_SHADOW_2_BASE_ADDR_HIGH_S                        0xE0908
+
+#define mmMME1_CTRL_SHADOW_2_BASE_ADDR_HIGH_L                        0xE090C
+
+#define mmMME1_CTRL_SHADOW_2_BASE_ADDR_HIGH_O                        0xE0910
+
+#define mmMME1_CTRL_SHADOW_2_BASE_ADDR_LOW_S                         0xE0914
+
+#define mmMME1_CTRL_SHADOW_2_BASE_ADDR_LOW_L                         0xE0918
+
+#define mmMME1_CTRL_SHADOW_2_BASE_ADDR_LOW_O                         0xE091C
+
+#define mmMME1_CTRL_SHADOW_2_HEADER_LOW                              0xE0920
+
+#define mmMME1_CTRL_SHADOW_2_HEADER_HIGH                             0xE0924
+
+#define mmMME1_CTRL_SHADOW_2_CONV_KERNEL_SIZE_MINUS_1                0xE0928
+
+#define mmMME1_CTRL_SHADOW_2_CONV_ASSOCIATED_DIMS_LOW                0xE092C
+
+#define mmMME1_CTRL_SHADOW_2_CONV_ASSOCIATED_DIMS_HIGH               0xE0930
+
+#define mmMME1_CTRL_SHADOW_2_NUM_ITERATIONS_MINUS_1                  0xE0934
+
+#define mmMME1_CTRL_SHADOW_2_OUTER_LOOP                              0xE0938
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_0               0xE093C
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_1               0xE0940
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_2               0xE0944
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_3               0xE0948
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_4               0xE094C
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_0                  0xE0950
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_1                  0xE0954
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_2                  0xE0958
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_3                  0xE095C
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_4                  0xE0960
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_0                     0xE0964
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_1                     0xE0968
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_2                     0xE096C
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_3                     0xE0970
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_0              0xE0974
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_1              0xE0978
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_2              0xE097C
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_3              0xE0980
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_S_SPATIAL_SIZE_MINUS_1           0xE0984
+
+#define mmMME1_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_0                 0xE0988
+
+#define mmMME1_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_1                 0xE098C
+
+#define mmMME1_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_2                 0xE0990
+
+#define mmMME1_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_3                 0xE0994
+
+#define mmMME1_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_4                 0xE0998
+
+#define mmMME1_CTRL_SHADOW_2_AGU_S_START_OFFSET_0                    0xE099C
+
+#define mmMME1_CTRL_SHADOW_2_AGU_S_START_OFFSET_1                    0xE09A0
+
+#define mmMME1_CTRL_SHADOW_2_AGU_S_START_OFFSET_2                    0xE09A4
+
+#define mmMME1_CTRL_SHADOW_2_AGU_S_START_OFFSET_3                    0xE09A8
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_0               0xE09AC
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_1               0xE09B0
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_2               0xE09B4
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_3               0xE09B8
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_4               0xE09BC
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_0                  0xE09C0
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_1                  0xE09C4
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_2                  0xE09C8
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_3                  0xE09CC
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_4                  0xE09D0
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_0                     0xE09D4
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_1                     0xE09D8
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_2                     0xE09DC
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_3                     0xE09E0
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_0              0xE09E4
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_1              0xE09E8
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_2              0xE09EC
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_3              0xE09F0
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_L_SPATIAL_SIZE_MINUS_1           0xE09F4
+
+#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_0           0xE09F8
+
+#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_1           0xE09FC
+
+#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_2           0xE0A00
+
+#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_3           0xE0A04
+
+#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_4           0xE0A08
+
+#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_0              0xE0A0C
+
+#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_1              0xE0A10
+
+#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_2              0xE0A14
+
+#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_3              0xE0A18
+
+#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_0          0xE0A1C
+
+#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_1          0xE0A20
+
+#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_2          0xE0A24
+
+#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_3          0xE0A28
+
+#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_4          0xE0A2C
+
+#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_0             0xE0A30
+
+#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_1             0xE0A34
+
+#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_2             0xE0A38
+
+#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_3             0xE0A3C
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_0               0xE0A40
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_1               0xE0A44
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_2               0xE0A48
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_3               0xE0A4C
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_4               0xE0A50
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_0                  0xE0A54
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_1                  0xE0A58
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_2                  0xE0A5C
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_3                  0xE0A60
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_4                  0xE0A64
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_0                     0xE0A68
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_1                     0xE0A6C
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_2                     0xE0A70
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_3                     0xE0A74
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_0              0xE0A78
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_1              0xE0A7C
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_2              0xE0A80
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_3              0xE0A84
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_O_SPATIAL_SIZE_MINUS_1           0xE0A88
+
+#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_0           0xE0A8C
+
+#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_1           0xE0A90
+
+#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_2           0xE0A94
+
+#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_3           0xE0A98
+
+#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_4           0xE0A9C
+
+#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_0              0xE0AA0
+
+#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_1              0xE0AA4
+
+#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_2              0xE0AA8
+
+#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_3              0xE0AAC
+
+#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_0          0xE0AB0
+
+#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_1          0xE0AB4
+
+#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_2          0xE0AB8
+
+#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_3          0xE0ABC
+
+#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_4          0xE0AC0
+
+#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_0             0xE0AC4
+
+#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_1             0xE0AC8
+
+#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_2             0xE0ACC
+
+#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_3             0xE0AD0
+
+#define mmMME1_CTRL_SHADOW_2_DESC_SB_REPEAT                          0xE0AD4
+
+#define mmMME1_CTRL_SHADOW_2_DESC_RATE_LIMITER                       0xE0AD8
+
+#define mmMME1_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL         0xE0ADC
+
+#define mmMME1_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE        0xE0AE0
+
+#define mmMME1_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_HIGH              0xE0AE4
+
+#define mmMME1_CTRL_SHADOW_2_DESC_SYNC_OBJECT_DATA                   0xE0AE8
+
+#define mmMME1_CTRL_SHADOW_2_DESC_AXI_USER_DATA                      0xE0AEC
+
+#define mmMME1_CTRL_SHADOW_2_DESC_PERF_EVT_S                         0xE0AF0
+
+#define mmMME1_CTRL_SHADOW_2_DESC_PERF_EVT_L_LOCAL                   0xE0AF4
+
+#define mmMME1_CTRL_SHADOW_2_DESC_PERF_EVT_L_REMOTE                  0xE0AF8
+
+#define mmMME1_CTRL_SHADOW_2_DESC_PERF_EVT_O_LOCAL                   0xE0AFC
+
+#define mmMME1_CTRL_SHADOW_2_DESC_PERF_EVT_O_REMOTE                  0xE0B00
+
+#define mmMME1_CTRL_SHADOW_2_DESC_PADDING_VALUE_S                    0xE0B04
+
+#define mmMME1_CTRL_SHADOW_2_DESC_PADDING_VALUE_L                    0xE0B08
+
+#define mmMME1_CTRL_SHADOW_2_DESC_META_DATA_AGU_S                    0xE0B0C
+
+#define mmMME1_CTRL_SHADOW_2_DESC_META_DATA_AGU_L_LOCAL              0xE0B10
+
+#define mmMME1_CTRL_SHADOW_2_DESC_META_DATA_AGU_L_REMOTE             0xE0B14
+
+#define mmMME1_CTRL_SHADOW_2_DESC_META_DATA_AGU_O_LOCAL              0xE0B18
+
+#define mmMME1_CTRL_SHADOW_2_DESC_META_DATA_AGU_O_REMOTE             0xE0B1C
+
+#define mmMME1_CTRL_SHADOW_2_DESC_PCU_RL_SATURATION                  0xE0B20
+
+#define mmMME1_CTRL_SHADOW_2_DESC_DUMMY                              0xE0B24
+
+#define mmMME1_CTRL_SHADOW_3_STATUS                                  0xE0B80
+
+#define mmMME1_CTRL_SHADOW_3_BASE_ADDR_HIGH_S                        0xE0B88
+
+#define mmMME1_CTRL_SHADOW_3_BASE_ADDR_HIGH_L                        0xE0B8C
+
+#define mmMME1_CTRL_SHADOW_3_BASE_ADDR_HIGH_O                        0xE0B90
+
+#define mmMME1_CTRL_SHADOW_3_BASE_ADDR_LOW_S                         0xE0B94
+
+#define mmMME1_CTRL_SHADOW_3_BASE_ADDR_LOW_L                         0xE0B98
+
+#define mmMME1_CTRL_SHADOW_3_BASE_ADDR_LOW_O                         0xE0B9C
+
+#define mmMME1_CTRL_SHADOW_3_HEADER_LOW                              0xE0BA0
+
+#define mmMME1_CTRL_SHADOW_3_HEADER_HIGH                             0xE0BA4
+
+#define mmMME1_CTRL_SHADOW_3_CONV_KERNEL_SIZE_MINUS_1                0xE0BA8
+
+#define mmMME1_CTRL_SHADOW_3_CONV_ASSOCIATED_DIMS_LOW                0xE0BAC
+
+#define mmMME1_CTRL_SHADOW_3_CONV_ASSOCIATED_DIMS_HIGH               0xE0BB0
+
+#define mmMME1_CTRL_SHADOW_3_NUM_ITERATIONS_MINUS_1                  0xE0BB4
+
+#define mmMME1_CTRL_SHADOW_3_OUTER_LOOP                              0xE0BB8
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_0               0xE0BBC
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_1               0xE0BC0
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_2               0xE0BC4
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_3               0xE0BC8
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_4               0xE0BCC
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_0                  0xE0BD0
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_1                  0xE0BD4
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_2                  0xE0BD8
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_3                  0xE0BDC
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_4                  0xE0BE0
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_0                     0xE0BE4
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_1                     0xE0BE8
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_2                     0xE0BEC
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_3                     0xE0BF0
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_0              0xE0BF4
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_1              0xE0BF8
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_2              0xE0BFC
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_3              0xE0C00
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_S_SPATIAL_SIZE_MINUS_1           0xE0C04
+
+#define mmMME1_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_0                 0xE0C08
+
+#define mmMME1_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_1                 0xE0C0C
+
+#define mmMME1_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_2                 0xE0C10
+
+#define mmMME1_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_3                 0xE0C14
+
+#define mmMME1_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_4                 0xE0C18
+
+#define mmMME1_CTRL_SHADOW_3_AGU_S_START_OFFSET_0                    0xE0C1C
+
+#define mmMME1_CTRL_SHADOW_3_AGU_S_START_OFFSET_1                    0xE0C20
+
+#define mmMME1_CTRL_SHADOW_3_AGU_S_START_OFFSET_2                    0xE0C24
+
+#define mmMME1_CTRL_SHADOW_3_AGU_S_START_OFFSET_3                    0xE0C28
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_0               0xE0C2C
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_1               0xE0C30
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_2               0xE0C34
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_3               0xE0C38
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_4               0xE0C3C
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_0                  0xE0C40
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_1                  0xE0C44
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_2                  0xE0C48
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_3                  0xE0C4C
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_4                  0xE0C50
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_0                     0xE0C54
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_1                     0xE0C58
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_2                     0xE0C5C
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_3                     0xE0C60
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_0              0xE0C64
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_1              0xE0C68
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_2              0xE0C6C
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_3              0xE0C70
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_L_SPATIAL_SIZE_MINUS_1           0xE0C74
+
+#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_0           0xE0C78
+
+#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_1           0xE0C7C
+
+#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_2           0xE0C80
+
+#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_3           0xE0C84
+
+#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_4           0xE0C88
+
+#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_0              0xE0C8C
+
+#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_1              0xE0C90
+
+#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_2              0xE0C94
+
+#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_3              0xE0C98
+
+#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_0          0xE0C9C
+
+#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_1          0xE0CA0
+
+#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_2          0xE0CA4
+
+#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_3          0xE0CA8
+
+#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_4          0xE0CAC
+
+#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_0             0xE0CB0
+
+#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_1             0xE0CB4
+
+#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_2             0xE0CB8
+
+#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_3             0xE0CBC
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_0               0xE0CC0
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_1               0xE0CC4
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_2               0xE0CC8
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_3               0xE0CCC
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_4               0xE0CD0
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_0                  0xE0CD4
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_1                  0xE0CD8
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_2                  0xE0CDC
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_3                  0xE0CE0
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_4                  0xE0CE4
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_0                     0xE0CE8
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_1                     0xE0CEC
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_2                     0xE0CF0
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_3                     0xE0CF4
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_0              0xE0CF8
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_1              0xE0CFC
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_2              0xE0D00
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_3              0xE0D04
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_O_SPATIAL_SIZE_MINUS_1           0xE0D08
+
+#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_0           0xE0D0C
+
+#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_1           0xE0D10
+
+#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_2           0xE0D14
+
+#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_3           0xE0D18
+
+#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_4           0xE0D1C
+
+#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_0              0xE0D20
+
+#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_1              0xE0D24
+
+#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_2              0xE0D28
+
+#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_3              0xE0D2C
+
+#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_0          0xE0D30
+
+#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_1          0xE0D34
+
+#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_2          0xE0D38
+
+#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_3          0xE0D3C
+
+#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_4          0xE0D40
+
+#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_0             0xE0D44
+
+#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_1             0xE0D48
+
+#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_2             0xE0D4C
+
+#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_3             0xE0D50
+
+#define mmMME1_CTRL_SHADOW_3_DESC_SB_REPEAT                          0xE0D54
+
+#define mmMME1_CTRL_SHADOW_3_DESC_RATE_LIMITER                       0xE0D58
+
+#define mmMME1_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL         0xE0D5C
+
+#define mmMME1_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE        0xE0D60
+
+#define mmMME1_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_HIGH              0xE0D64
+
+#define mmMME1_CTRL_SHADOW_3_DESC_SYNC_OBJECT_DATA                   0xE0D68
+
+#define mmMME1_CTRL_SHADOW_3_DESC_AXI_USER_DATA                      0xE0D6C
+
+#define mmMME1_CTRL_SHADOW_3_DESC_PERF_EVT_S                         0xE0D70
+
+#define mmMME1_CTRL_SHADOW_3_DESC_PERF_EVT_L_LOCAL                   0xE0D74
+
+#define mmMME1_CTRL_SHADOW_3_DESC_PERF_EVT_L_REMOTE                  0xE0D78
+
+#define mmMME1_CTRL_SHADOW_3_DESC_PERF_EVT_O_LOCAL                   0xE0D7C
+
+#define mmMME1_CTRL_SHADOW_3_DESC_PERF_EVT_O_REMOTE                  0xE0D80
+
+#define mmMME1_CTRL_SHADOW_3_DESC_PADDING_VALUE_S                    0xE0D84
+
+#define mmMME1_CTRL_SHADOW_3_DESC_PADDING_VALUE_L                    0xE0D88
+
+#define mmMME1_CTRL_SHADOW_3_DESC_META_DATA_AGU_S                    0xE0D8C
+
+#define mmMME1_CTRL_SHADOW_3_DESC_META_DATA_AGU_L_LOCAL              0xE0D90
+
+#define mmMME1_CTRL_SHADOW_3_DESC_META_DATA_AGU_L_REMOTE             0xE0D94
+
+#define mmMME1_CTRL_SHADOW_3_DESC_META_DATA_AGU_O_LOCAL              0xE0D98
+
+#define mmMME1_CTRL_SHADOW_3_DESC_META_DATA_AGU_O_REMOTE             0xE0D9C
+
+#define mmMME1_CTRL_SHADOW_3_DESC_PCU_RL_SATURATION                  0xE0DA0
+
+#define mmMME1_CTRL_SHADOW_3_DESC_DUMMY                              0xE0DA4
+
+#endif /* ASIC_REG_MME1_CTRL_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/mme2_ctrl_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/mme2_ctrl_regs.h
new file mode 100644
index 000000000000..a1f2eb8b91bd
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/mme2_ctrl_regs.h
@@ -0,0 +1,1456 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_MME2_CTRL_REGS_H_
+#define ASIC_REG_MME2_CTRL_REGS_H_
+
+/*
+ *****************************************
+ *   MME2_CTRL (Prototype: MME)
+ *****************************************
+ */
+
+#define mmMME2_CTRL_ARCH_STATUS                                      0x160000
+
+#define mmMME2_CTRL_ARCH_BASE_ADDR_HIGH_S                            0x160008
+
+#define mmMME2_CTRL_ARCH_BASE_ADDR_HIGH_L                            0x16000C
+
+#define mmMME2_CTRL_ARCH_BASE_ADDR_HIGH_O                            0x160010
+
+#define mmMME2_CTRL_ARCH_BASE_ADDR_LOW_S                             0x160014
+
+#define mmMME2_CTRL_ARCH_BASE_ADDR_LOW_L                             0x160018
+
+#define mmMME2_CTRL_ARCH_BASE_ADDR_LOW_O                             0x16001C
+
+#define mmMME2_CTRL_ARCH_HEADER_LOW                                  0x160020
+
+#define mmMME2_CTRL_ARCH_HEADER_HIGH                                 0x160024
+
+#define mmMME2_CTRL_ARCH_CONV_KERNEL_SIZE_MINUS_1                    0x160028
+
+#define mmMME2_CTRL_ARCH_CONV_ASSOCIATED_DIMS_LOW                    0x16002C
+
+#define mmMME2_CTRL_ARCH_CONV_ASSOCIATED_DIMS_HIGH                   0x160030
+
+#define mmMME2_CTRL_ARCH_NUM_ITERATIONS_MINUS_1                      0x160034
+
+#define mmMME2_CTRL_ARCH_OUTER_LOOP                                  0x160038
+
+#define mmMME2_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_0                   0x16003C
+
+#define mmMME2_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_1                   0x160040
+
+#define mmMME2_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_2                   0x160044
+
+#define mmMME2_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_3                   0x160048
+
+#define mmMME2_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_4                   0x16004C
+
+#define mmMME2_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_0                      0x160050
+
+#define mmMME2_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_1                      0x160054
+
+#define mmMME2_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_2                      0x160058
+
+#define mmMME2_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_3                      0x16005C
+
+#define mmMME2_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_4                      0x160060
+
+#define mmMME2_CTRL_ARCH_TENSOR_S_ROI_SIZE_0                         0x160064
+
+#define mmMME2_CTRL_ARCH_TENSOR_S_ROI_SIZE_1                         0x160068
+
+#define mmMME2_CTRL_ARCH_TENSOR_S_ROI_SIZE_2                         0x16006C
+
+#define mmMME2_CTRL_ARCH_TENSOR_S_ROI_SIZE_3                         0x160070
+
+#define mmMME2_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_0                  0x160074
+
+#define mmMME2_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_1                  0x160078
+
+#define mmMME2_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_2                  0x16007C
+
+#define mmMME2_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_3                  0x160080
+
+#define mmMME2_CTRL_ARCH_TENSOR_S_SPATIAL_SIZE_MINUS_1               0x160084
+
+#define mmMME2_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_0                     0x160088
+
+#define mmMME2_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_1                     0x16008C
+
+#define mmMME2_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_2                     0x160090
+
+#define mmMME2_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_3                     0x160094
+
+#define mmMME2_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_4                     0x160098
+
+#define mmMME2_CTRL_ARCH_AGU_S_START_OFFSET_0                        0x16009C
+
+#define mmMME2_CTRL_ARCH_AGU_S_START_OFFSET_1                        0x1600A0
+
+#define mmMME2_CTRL_ARCH_AGU_S_START_OFFSET_2                        0x1600A4
+
+#define mmMME2_CTRL_ARCH_AGU_S_START_OFFSET_3                        0x1600A8
+
+#define mmMME2_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_0                   0x1600AC
+
+#define mmMME2_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_1                   0x1600B0
+
+#define mmMME2_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_2                   0x1600B4
+
+#define mmMME2_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_3                   0x1600B8
+
+#define mmMME2_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_4                   0x1600BC
+
+#define mmMME2_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_0                      0x1600C0
+
+#define mmMME2_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_1                      0x1600C4
+
+#define mmMME2_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_2                      0x1600C8
+
+#define mmMME2_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_3                      0x1600CC
+
+#define mmMME2_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_4                      0x1600D0
+
+#define mmMME2_CTRL_ARCH_TENSOR_L_ROI_SIZE_0                         0x1600D4
+
+#define mmMME2_CTRL_ARCH_TENSOR_L_ROI_SIZE_1                         0x1600D8
+
+#define mmMME2_CTRL_ARCH_TENSOR_L_ROI_SIZE_2                         0x1600DC
+
+#define mmMME2_CTRL_ARCH_TENSOR_L_ROI_SIZE_3                         0x1600E0
+
+#define mmMME2_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_0                  0x1600E4
+
+#define mmMME2_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_1                  0x1600E8
+
+#define mmMME2_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_2                  0x1600EC
+
+#define mmMME2_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_3                  0x1600F0
+
+#define mmMME2_CTRL_ARCH_TENSOR_L_SPATIAL_SIZE_MINUS_1               0x1600F4
+
+#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_0               0x1600F8
+
+#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_1               0x1600FC
+
+#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_2               0x160100
+
+#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_3               0x160104
+
+#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_4               0x160108
+
+#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_0                  0x16010C
+
+#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_1                  0x160110
+
+#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_2                  0x160114
+
+#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_3                  0x160118
+
+#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_0              0x16011C
+
+#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_1              0x160120
+
+#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_2              0x160124
+
+#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_3              0x160128
+
+#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_4              0x16012C
+
+#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_0                 0x160130
+
+#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_1                 0x160134
+
+#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_2                 0x160138
+
+#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_3                 0x16013C
+
+#define mmMME2_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_0                   0x160140
+
+#define mmMME2_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_1                   0x160144
+
+#define mmMME2_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_2                   0x160148
+
+#define mmMME2_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_3                   0x16014C
+
+#define mmMME2_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_4                   0x160150
+
+#define mmMME2_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_0                      0x160154
+
+#define mmMME2_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_1                      0x160158
+
+#define mmMME2_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_2                      0x16015C
+
+#define mmMME2_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_3                      0x160160
+
+#define mmMME2_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_4                      0x160164
+
+#define mmMME2_CTRL_ARCH_TENSOR_O_ROI_SIZE_0                         0x160168
+
+#define mmMME2_CTRL_ARCH_TENSOR_O_ROI_SIZE_1                         0x16016C
+
+#define mmMME2_CTRL_ARCH_TENSOR_O_ROI_SIZE_2                         0x160170
+
+#define mmMME2_CTRL_ARCH_TENSOR_O_ROI_SIZE_3                         0x160174
+
+#define mmMME2_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_0                  0x160178
+
+#define mmMME2_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_1                  0x16017C
+
+#define mmMME2_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_2                  0x160180
+
+#define mmMME2_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_3                  0x160184
+
+#define mmMME2_CTRL_ARCH_TENSOR_O_SPATIAL_SIZE_MINUS_1               0x160188
+
+#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_0               0x16018C
+
+#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_1               0x160190
+
+#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_2               0x160194
+
+#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_3               0x160198
+
+#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_4               0x16019C
+
+#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_0                  0x1601A0
+
+#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_1                  0x1601A4
+
+#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_2                  0x1601A8
+
+#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_3                  0x1601AC
+
+#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_0              0x1601B0
+
+#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_1              0x1601B4
+
+#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_2              0x1601B8
+
+#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_3              0x1601BC
+
+#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_4              0x1601C0
+
+#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_0                 0x1601C4
+
+#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_1                 0x1601C8
+
+#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_2                 0x1601CC
+
+#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_3                 0x1601D0
+
+#define mmMME2_CTRL_ARCH_DESC_SB_REPEAT                              0x1601D4
+
+#define mmMME2_CTRL_ARCH_DESC_RATE_LIMITER                           0x1601D8
+
+#define mmMME2_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL             0x1601DC
+
+#define mmMME2_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE            0x1601E0
+
+#define mmMME2_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_HIGH                  0x1601E4
+
+#define mmMME2_CTRL_ARCH_DESC_SYNC_OBJECT_DATA                       0x1601E8
+
+#define mmMME2_CTRL_ARCH_DESC_AXI_USER_DATA                          0x1601EC
+
+#define mmMME2_CTRL_ARCH_DESC_PERF_EVT_S                             0x1601F0
+
+#define mmMME2_CTRL_ARCH_DESC_PERF_EVT_L_LOCAL                       0x1601F4
+
+#define mmMME2_CTRL_ARCH_DESC_PERF_EVT_L_REMOTE                      0x1601F8
+
+#define mmMME2_CTRL_ARCH_DESC_PERF_EVT_O_LOCAL                       0x1601FC
+
+#define mmMME2_CTRL_ARCH_DESC_PERF_EVT_O_REMOTE                      0x160200
+
+#define mmMME2_CTRL_ARCH_DESC_PADDING_VALUE_S                        0x160204
+
+#define mmMME2_CTRL_ARCH_DESC_PADDING_VALUE_L                        0x160208
+
+#define mmMME2_CTRL_ARCH_DESC_META_DATA_AGU_S                        0x16020C
+
+#define mmMME2_CTRL_ARCH_DESC_META_DATA_AGU_L_LOCAL                  0x160210
+
+#define mmMME2_CTRL_ARCH_DESC_META_DATA_AGU_L_REMOTE                 0x160214
+
+#define mmMME2_CTRL_ARCH_DESC_META_DATA_AGU_O_LOCAL                  0x160218
+
+#define mmMME2_CTRL_ARCH_DESC_META_DATA_AGU_O_REMOTE                 0x16021C
+
+#define mmMME2_CTRL_ARCH_DESC_PCU_RL_SATURATION                      0x160220
+
+#define mmMME2_CTRL_ARCH_DESC_DUMMY                                  0x160224
+
+#define mmMME2_CTRL_CMD                                              0x160280
+
+#define mmMME2_CTRL_STATUS1                                          0x160284
+
+#define mmMME2_CTRL_RESET                                            0x160288
+
+#define mmMME2_CTRL_QM_STALL                                         0x16028C
+
+#define mmMME2_CTRL_SYNC_OBJECT_FIFO_TH                              0x160290
+
+#define mmMME2_CTRL_EUS_ROLLUP_CNT_ADD                               0x160294
+
+#define mmMME2_CTRL_INTR_CAUSE                                       0x160298
+
+#define mmMME2_CTRL_INTR_MASK                                        0x16029C
+
+#define mmMME2_CTRL_LOG_SHADOW                                       0x1602A0
+
+#define mmMME2_CTRL_PCU_RL_DESC0                                     0x1602A4
+
+#define mmMME2_CTRL_PCU_RL_TOKEN_UPDATE                              0x1602A8
+
+#define mmMME2_CTRL_PCU_RL_TH                                        0x1602AC
+
+#define mmMME2_CTRL_PCU_RL_MIN                                       0x1602B0
+
+#define mmMME2_CTRL_PCU_RL_CTRL_EN                                   0x1602B4
+
+#define mmMME2_CTRL_PCU_RL_HISTORY_LOG_SIZE                          0x1602B8
+
+#define mmMME2_CTRL_PCU_DUMMY_A_BF16                                 0x1602BC
+
+#define mmMME2_CTRL_PCU_DUMMY_B_BF16                                 0x1602C0
+
+#define mmMME2_CTRL_PCU_DUMMY_A_FP32_ODD                             0x1602C4
+
+#define mmMME2_CTRL_PCU_DUMMY_A_FP32_EVEN                            0x1602C8
+
+#define mmMME2_CTRL_PCU_DUMMY_B_FP32_ODD                             0x1602CC
+
+#define mmMME2_CTRL_PCU_DUMMY_B_FP32_EVEN                            0x1602D0
+
+#define mmMME2_CTRL_PROT                                             0x1602D4
+
+#define mmMME2_CTRL_EU_POWER_SAVE_DISABLE                            0x1602D8
+
+#define mmMME2_CTRL_CS_DBG_BLOCK_ID                                  0x1602DC
+
+#define mmMME2_CTRL_CS_DBG_STATUS_DROP_CNT                           0x1602E0
+
+#define mmMME2_CTRL_TE_CLOSE_CGATE                                   0x1602E4
+
+#define mmMME2_CTRL_AGU_SM_INFLIGHT_CNTR                             0x1602E8
+
+#define mmMME2_CTRL_AGU_SM_TOTAL_CNTR                                0x1602EC
+
+#define mmMME2_CTRL_EZSYNC_OUT_CREDIT                                0x1602F0
+
+#define mmMME2_CTRL_PCU_RL_SAT_SEC                                   0x1602F4
+
+#define mmMME2_CTRL_AGU_SYNC_MSG_AXI_USER                            0x1602F8
+
+#define mmMME2_CTRL_QM_SLV_LBW_CLK_EN                                0x1602FC
+
+#define mmMME2_CTRL_SHADOW_0_STATUS                                  0x160400
+
+#define mmMME2_CTRL_SHADOW_0_BASE_ADDR_HIGH_S                        0x160408
+
+#define mmMME2_CTRL_SHADOW_0_BASE_ADDR_HIGH_L                        0x16040C
+
+#define mmMME2_CTRL_SHADOW_0_BASE_ADDR_HIGH_O                        0x160410
+
+#define mmMME2_CTRL_SHADOW_0_BASE_ADDR_LOW_S                         0x160414
+
+#define mmMME2_CTRL_SHADOW_0_BASE_ADDR_LOW_L                         0x160418
+
+#define mmMME2_CTRL_SHADOW_0_BASE_ADDR_LOW_O                         0x16041C
+
+#define mmMME2_CTRL_SHADOW_0_HEADER_LOW                              0x160420
+
+#define mmMME2_CTRL_SHADOW_0_HEADER_HIGH                             0x160424
+
+#define mmMME2_CTRL_SHADOW_0_CONV_KERNEL_SIZE_MINUS_1                0x160428
+
+#define mmMME2_CTRL_SHADOW_0_CONV_ASSOCIATED_DIMS_LOW                0x16042C
+
+#define mmMME2_CTRL_SHADOW_0_CONV_ASSOCIATED_DIMS_HIGH               0x160430
+
+#define mmMME2_CTRL_SHADOW_0_NUM_ITERATIONS_MINUS_1                  0x160434
+
+#define mmMME2_CTRL_SHADOW_0_OUTER_LOOP                              0x160438
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_0               0x16043C
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_1               0x160440
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_2               0x160444
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_3               0x160448
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_4               0x16044C
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_0                  0x160450
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_1                  0x160454
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_2                  0x160458
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_3                  0x16045C
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_4                  0x160460
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_0                     0x160464
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_1                     0x160468
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_2                     0x16046C
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_3                     0x160470
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_0              0x160474
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_1              0x160478
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_2              0x16047C
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_3              0x160480
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_S_SPATIAL_SIZE_MINUS_1           0x160484
+
+#define mmMME2_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_0                 0x160488
+
+#define mmMME2_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_1                 0x16048C
+
+#define mmMME2_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_2                 0x160490
+
+#define mmMME2_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_3                 0x160494
+
+#define mmMME2_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_4                 0x160498
+
+#define mmMME2_CTRL_SHADOW_0_AGU_S_START_OFFSET_0                    0x16049C
+
+#define mmMME2_CTRL_SHADOW_0_AGU_S_START_OFFSET_1                    0x1604A0
+
+#define mmMME2_CTRL_SHADOW_0_AGU_S_START_OFFSET_2                    0x1604A4
+
+#define mmMME2_CTRL_SHADOW_0_AGU_S_START_OFFSET_3                    0x1604A8
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_0               0x1604AC
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_1               0x1604B0
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_2               0x1604B4
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_3               0x1604B8
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_4               0x1604BC
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_0                  0x1604C0
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_1                  0x1604C4
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_2                  0x1604C8
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_3                  0x1604CC
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_4                  0x1604D0
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_0                     0x1604D4
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_1                     0x1604D8
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_2                     0x1604DC
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_3                     0x1604E0
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_0              0x1604E4
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_1              0x1604E8
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_2              0x1604EC
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_3              0x1604F0
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_L_SPATIAL_SIZE_MINUS_1           0x1604F4
+
+#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_0           0x1604F8
+
+#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_1           0x1604FC
+
+#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_2           0x160500
+
+#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_3           0x160504
+
+#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_4           0x160508
+
+#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_0              0x16050C
+
+#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_1              0x160510
+
+#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_2              0x160514
+
+#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_3              0x160518
+
+#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_0          0x16051C
+
+#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_1          0x160520
+
+#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_2          0x160524
+
+#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_3          0x160528
+
+#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_4          0x16052C
+
+#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_0             0x160530
+
+#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_1             0x160534
+
+#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_2             0x160538
+
+#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_3             0x16053C
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_0               0x160540
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_1               0x160544
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_2               0x160548
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_3               0x16054C
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_4               0x160550
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_0                  0x160554
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_1                  0x160558
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_2                  0x16055C
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_3                  0x160560
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_4                  0x160564
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_0                     0x160568
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_1                     0x16056C
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_2                     0x160570
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_3                     0x160574
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_0              0x160578
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_1              0x16057C
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_2              0x160580
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_3              0x160584
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_O_SPATIAL_SIZE_MINUS_1           0x160588
+
+#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_0           0x16058C
+
+#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_1           0x160590
+
+#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_2           0x160594
+
+#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_3           0x160598
+
+#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_4           0x16059C
+
+#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_0              0x1605A0
+
+#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_1              0x1605A4
+
+#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_2              0x1605A8
+
+#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_3              0x1605AC
+
+#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_0          0x1605B0
+
+#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_1          0x1605B4
+
+#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_2          0x1605B8
+
+#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_3          0x1605BC
+
+#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_4          0x1605C0
+
+#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_0             0x1605C4
+
+#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_1             0x1605C8
+
+#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_2             0x1605CC
+
+#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_3             0x1605D0
+
+#define mmMME2_CTRL_SHADOW_0_DESC_SB_REPEAT                          0x1605D4
+
+#define mmMME2_CTRL_SHADOW_0_DESC_RATE_LIMITER                       0x1605D8
+
+#define mmMME2_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL         0x1605DC
+
+#define mmMME2_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE        0x1605E0
+
+#define mmMME2_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_HIGH              0x1605E4
+
+#define mmMME2_CTRL_SHADOW_0_DESC_SYNC_OBJECT_DATA                   0x1605E8
+
+#define mmMME2_CTRL_SHADOW_0_DESC_AXI_USER_DATA                      0x1605EC
+
+#define mmMME2_CTRL_SHADOW_0_DESC_PERF_EVT_S                         0x1605F0
+
+#define mmMME2_CTRL_SHADOW_0_DESC_PERF_EVT_L_LOCAL                   0x1605F4
+
+#define mmMME2_CTRL_SHADOW_0_DESC_PERF_EVT_L_REMOTE                  0x1605F8
+
+#define mmMME2_CTRL_SHADOW_0_DESC_PERF_EVT_O_LOCAL                   0x1605FC
+
+#define mmMME2_CTRL_SHADOW_0_DESC_PERF_EVT_O_REMOTE                  0x160600
+
+#define mmMME2_CTRL_SHADOW_0_DESC_PADDING_VALUE_S                    0x160604
+
+#define mmMME2_CTRL_SHADOW_0_DESC_PADDING_VALUE_L                    0x160608
+
+#define mmMME2_CTRL_SHADOW_0_DESC_META_DATA_AGU_S                    0x16060C
+
+#define mmMME2_CTRL_SHADOW_0_DESC_META_DATA_AGU_L_LOCAL              0x160610
+
+#define mmMME2_CTRL_SHADOW_0_DESC_META_DATA_AGU_L_REMOTE             0x160614
+
+#define mmMME2_CTRL_SHADOW_0_DESC_META_DATA_AGU_O_LOCAL              0x160618
+
+#define mmMME2_CTRL_SHADOW_0_DESC_META_DATA_AGU_O_REMOTE             0x16061C
+
+#define mmMME2_CTRL_SHADOW_0_DESC_PCU_RL_SATURATION                  0x160620
+
+#define mmMME2_CTRL_SHADOW_0_DESC_DUMMY                              0x160624
+
+#define mmMME2_CTRL_SHADOW_1_STATUS                                  0x160680
+
+#define mmMME2_CTRL_SHADOW_1_BASE_ADDR_HIGH_S                        0x160688
+
+#define mmMME2_CTRL_SHADOW_1_BASE_ADDR_HIGH_L                        0x16068C
+
+#define mmMME2_CTRL_SHADOW_1_BASE_ADDR_HIGH_O                        0x160690
+
+#define mmMME2_CTRL_SHADOW_1_BASE_ADDR_LOW_S                         0x160694
+
+#define mmMME2_CTRL_SHADOW_1_BASE_ADDR_LOW_L                         0x160698
+
+#define mmMME2_CTRL_SHADOW_1_BASE_ADDR_LOW_O                         0x16069C
+
+#define mmMME2_CTRL_SHADOW_1_HEADER_LOW                              0x1606A0
+
+#define mmMME2_CTRL_SHADOW_1_HEADER_HIGH                             0x1606A4
+
+#define mmMME2_CTRL_SHADOW_1_CONV_KERNEL_SIZE_MINUS_1                0x1606A8
+
+#define mmMME2_CTRL_SHADOW_1_CONV_ASSOCIATED_DIMS_LOW                0x1606AC
+
+#define mmMME2_CTRL_SHADOW_1_CONV_ASSOCIATED_DIMS_HIGH               0x1606B0
+
+#define mmMME2_CTRL_SHADOW_1_NUM_ITERATIONS_MINUS_1                  0x1606B4
+
+#define mmMME2_CTRL_SHADOW_1_OUTER_LOOP                              0x1606B8
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_0               0x1606BC
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_1               0x1606C0
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_2               0x1606C4
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_3               0x1606C8
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_4               0x1606CC
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_0                  0x1606D0
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_1                  0x1606D4
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_2                  0x1606D8
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_3                  0x1606DC
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_4                  0x1606E0
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_0                     0x1606E4
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_1                     0x1606E8
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_2                     0x1606EC
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_3                     0x1606F0
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_0              0x1606F4
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_1              0x1606F8
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_2              0x1606FC
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_3              0x160700
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_S_SPATIAL_SIZE_MINUS_1           0x160704
+
+#define mmMME2_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_0                 0x160708
+
+#define mmMME2_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_1                 0x16070C
+
+#define mmMME2_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_2                 0x160710
+
+#define mmMME2_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_3                 0x160714
+
+#define mmMME2_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_4                 0x160718
+
+#define mmMME2_CTRL_SHADOW_1_AGU_S_START_OFFSET_0                    0x16071C
+
+#define mmMME2_CTRL_SHADOW_1_AGU_S_START_OFFSET_1                    0x160720
+
+#define mmMME2_CTRL_SHADOW_1_AGU_S_START_OFFSET_2                    0x160724
+
+#define mmMME2_CTRL_SHADOW_1_AGU_S_START_OFFSET_3                    0x160728
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_0               0x16072C
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_1               0x160730
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_2               0x160734
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_3               0x160738
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_4               0x16073C
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_0                  0x160740
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_1                  0x160744
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_2                  0x160748
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_3                  0x16074C
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_4                  0x160750
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_0                     0x160754
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_1                     0x160758
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_2                     0x16075C
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_3                     0x160760
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_0              0x160764
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_1              0x160768
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_2              0x16076C
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_3              0x160770
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_L_SPATIAL_SIZE_MINUS_1           0x160774
+
+#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_0           0x160778
+
+#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_1           0x16077C
+
+#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_2           0x160780
+
+#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_3           0x160784
+
+#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_4           0x160788
+
+#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_0              0x16078C
+
+#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_1              0x160790
+
+#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_2              0x160794
+
+#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_3              0x160798
+
+#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_0          0x16079C
+
+#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_1          0x1607A0
+
+#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_2          0x1607A4
+
+#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_3          0x1607A8
+
+#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_4          0x1607AC
+
+#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_0             0x1607B0
+
+#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_1             0x1607B4
+
+#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_2             0x1607B8
+
+#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_3             0x1607BC
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_0               0x1607C0
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_1               0x1607C4
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_2               0x1607C8
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_3               0x1607CC
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_4               0x1607D0
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_0                  0x1607D4
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_1                  0x1607D8
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_2                  0x1607DC
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_3                  0x1607E0
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_4                  0x1607E4
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_0                     0x1607E8
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_1                     0x1607EC
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_2                     0x1607F0
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_3                     0x1607F4
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_0              0x1607F8
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_1              0x1607FC
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_2              0x160800
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_3              0x160804
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_O_SPATIAL_SIZE_MINUS_1           0x160808
+
+#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_0           0x16080C
+
+#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_1           0x160810
+
+#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_2           0x160814
+
+#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_3           0x160818
+
+#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_4           0x16081C
+
+#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_0              0x160820
+
+#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_1              0x160824
+
+#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_2              0x160828
+
+#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_3              0x16082C
+
+#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_0          0x160830
+
+#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_1          0x160834
+
+#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_2          0x160838
+
+#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_3          0x16083C
+
+#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_4          0x160840
+
+#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_0             0x160844
+
+#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_1             0x160848
+
+#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_2             0x16084C
+
+#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_3             0x160850
+
+#define mmMME2_CTRL_SHADOW_1_DESC_SB_REPEAT                          0x160854
+
+#define mmMME2_CTRL_SHADOW_1_DESC_RATE_LIMITER                       0x160858
+
+#define mmMME2_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL         0x16085C
+
+#define mmMME2_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE        0x160860
+
+#define mmMME2_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_HIGH              0x160864
+
+#define mmMME2_CTRL_SHADOW_1_DESC_SYNC_OBJECT_DATA                   0x160868
+
+#define mmMME2_CTRL_SHADOW_1_DESC_AXI_USER_DATA                      0x16086C
+
+#define mmMME2_CTRL_SHADOW_1_DESC_PERF_EVT_S                         0x160870
+
+#define mmMME2_CTRL_SHADOW_1_DESC_PERF_EVT_L_LOCAL                   0x160874
+
+#define mmMME2_CTRL_SHADOW_1_DESC_PERF_EVT_L_REMOTE                  0x160878
+
+#define mmMME2_CTRL_SHADOW_1_DESC_PERF_EVT_O_LOCAL                   0x16087C
+
+#define mmMME2_CTRL_SHADOW_1_DESC_PERF_EVT_O_REMOTE                  0x160880
+
+#define mmMME2_CTRL_SHADOW_1_DESC_PADDING_VALUE_S                    0x160884
+
+#define mmMME2_CTRL_SHADOW_1_DESC_PADDING_VALUE_L                    0x160888
+
+#define mmMME2_CTRL_SHADOW_1_DESC_META_DATA_AGU_S                    0x16088C
+
+#define mmMME2_CTRL_SHADOW_1_DESC_META_DATA_AGU_L_LOCAL              0x160890
+
+#define mmMME2_CTRL_SHADOW_1_DESC_META_DATA_AGU_L_REMOTE             0x160894
+
+#define mmMME2_CTRL_SHADOW_1_DESC_META_DATA_AGU_O_LOCAL              0x160898
+
+#define mmMME2_CTRL_SHADOW_1_DESC_META_DATA_AGU_O_REMOTE             0x16089C
+
+#define mmMME2_CTRL_SHADOW_1_DESC_PCU_RL_SATURATION                  0x1608A0
+
+#define mmMME2_CTRL_SHADOW_1_DESC_DUMMY                              0x1608A4
+
+#define mmMME2_CTRL_SHADOW_2_STATUS                                  0x160900
+
+#define mmMME2_CTRL_SHADOW_2_BASE_ADDR_HIGH_S                        0x160908
+
+#define mmMME2_CTRL_SHADOW_2_BASE_ADDR_HIGH_L                        0x16090C
+
+#define mmMME2_CTRL_SHADOW_2_BASE_ADDR_HIGH_O                        0x160910
+
+#define mmMME2_CTRL_SHADOW_2_BASE_ADDR_LOW_S                         0x160914
+
+#define mmMME2_CTRL_SHADOW_2_BASE_ADDR_LOW_L                         0x160918
+
+#define mmMME2_CTRL_SHADOW_2_BASE_ADDR_LOW_O                         0x16091C
+
+#define mmMME2_CTRL_SHADOW_2_HEADER_LOW                              0x160920
+
+#define mmMME2_CTRL_SHADOW_2_HEADER_HIGH                             0x160924
+
+#define mmMME2_CTRL_SHADOW_2_CONV_KERNEL_SIZE_MINUS_1                0x160928
+
+#define mmMME2_CTRL_SHADOW_2_CONV_ASSOCIATED_DIMS_LOW                0x16092C
+
+#define mmMME2_CTRL_SHADOW_2_CONV_ASSOCIATED_DIMS_HIGH               0x160930
+
+#define mmMME2_CTRL_SHADOW_2_NUM_ITERATIONS_MINUS_1                  0x160934
+
+#define mmMME2_CTRL_SHADOW_2_OUTER_LOOP                              0x160938
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_0               0x16093C
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_1               0x160940
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_2               0x160944
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_3               0x160948
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_4               0x16094C
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_0                  0x160950
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_1                  0x160954
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_2                  0x160958
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_3                  0x16095C
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_4                  0x160960
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_0                     0x160964
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_1                     0x160968
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_2                     0x16096C
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_3                     0x160970
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_0              0x160974
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_1              0x160978
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_2              0x16097C
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_3              0x160980
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_S_SPATIAL_SIZE_MINUS_1           0x160984
+
+#define mmMME2_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_0                 0x160988
+
+#define mmMME2_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_1                 0x16098C
+
+#define mmMME2_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_2                 0x160990
+
+#define mmMME2_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_3                 0x160994
+
+#define mmMME2_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_4                 0x160998
+
+#define mmMME2_CTRL_SHADOW_2_AGU_S_START_OFFSET_0                    0x16099C
+
+#define mmMME2_CTRL_SHADOW_2_AGU_S_START_OFFSET_1                    0x1609A0
+
+#define mmMME2_CTRL_SHADOW_2_AGU_S_START_OFFSET_2                    0x1609A4
+
+#define mmMME2_CTRL_SHADOW_2_AGU_S_START_OFFSET_3                    0x1609A8
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_0               0x1609AC
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_1               0x1609B0
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_2               0x1609B4
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_3               0x1609B8
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_4               0x1609BC
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_0                  0x1609C0
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_1                  0x1609C4
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_2                  0x1609C8
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_3                  0x1609CC
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_4                  0x1609D0
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_0                     0x1609D4
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_1                     0x1609D8
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_2                     0x1609DC
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_3                     0x1609E0
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_0              0x1609E4
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_1              0x1609E8
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_2              0x1609EC
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_3              0x1609F0
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_L_SPATIAL_SIZE_MINUS_1           0x1609F4
+
+#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_0           0x1609F8
+
+#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_1           0x1609FC
+
+#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_2           0x160A00
+
+#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_3           0x160A04
+
+#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_4           0x160A08
+
+#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_0              0x160A0C
+
+#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_1              0x160A10
+
+#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_2              0x160A14
+
+#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_3              0x160A18
+
+#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_0          0x160A1C
+
+#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_1          0x160A20
+
+#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_2          0x160A24
+
+#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_3          0x160A28
+
+#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_4          0x160A2C
+
+#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_0             0x160A30
+
+#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_1             0x160A34
+
+#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_2             0x160A38
+
+#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_3             0x160A3C
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_0               0x160A40
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_1               0x160A44
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_2               0x160A48
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_3               0x160A4C
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_4               0x160A50
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_0                  0x160A54
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_1                  0x160A58
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_2                  0x160A5C
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_3                  0x160A60
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_4                  0x160A64
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_0                     0x160A68
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_1                     0x160A6C
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_2                     0x160A70
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_3                     0x160A74
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_0              0x160A78
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_1              0x160A7C
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_2              0x160A80
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_3              0x160A84
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_O_SPATIAL_SIZE_MINUS_1           0x160A88
+
+#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_0           0x160A8C
+
+#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_1           0x160A90
+
+#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_2           0x160A94
+
+#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_3           0x160A98
+
+#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_4           0x160A9C
+
+#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_0              0x160AA0
+
+#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_1              0x160AA4
+
+#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_2              0x160AA8
+
+#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_3              0x160AAC
+
+#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_0          0x160AB0
+
+#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_1          0x160AB4
+
+#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_2          0x160AB8
+
+#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_3          0x160ABC
+
+#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_4          0x160AC0
+
+#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_0             0x160AC4
+
+#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_1             0x160AC8
+
+#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_2             0x160ACC
+
+#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_3             0x160AD0
+
+#define mmMME2_CTRL_SHADOW_2_DESC_SB_REPEAT                          0x160AD4
+
+#define mmMME2_CTRL_SHADOW_2_DESC_RATE_LIMITER                       0x160AD8
+
+#define mmMME2_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL         0x160ADC
+
+#define mmMME2_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE        0x160AE0
+
+#define mmMME2_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_HIGH              0x160AE4
+
+#define mmMME2_CTRL_SHADOW_2_DESC_SYNC_OBJECT_DATA                   0x160AE8
+
+#define mmMME2_CTRL_SHADOW_2_DESC_AXI_USER_DATA                      0x160AEC
+
+#define mmMME2_CTRL_SHADOW_2_DESC_PERF_EVT_S                         0x160AF0
+
+#define mmMME2_CTRL_SHADOW_2_DESC_PERF_EVT_L_LOCAL                   0x160AF4
+
+#define mmMME2_CTRL_SHADOW_2_DESC_PERF_EVT_L_REMOTE                  0x160AF8
+
+#define mmMME2_CTRL_SHADOW_2_DESC_PERF_EVT_O_LOCAL                   0x160AFC
+
+#define mmMME2_CTRL_SHADOW_2_DESC_PERF_EVT_O_REMOTE                  0x160B00
+
+#define mmMME2_CTRL_SHADOW_2_DESC_PADDING_VALUE_S                    0x160B04
+
+#define mmMME2_CTRL_SHADOW_2_DESC_PADDING_VALUE_L                    0x160B08
+
+#define mmMME2_CTRL_SHADOW_2_DESC_META_DATA_AGU_S                    0x160B0C
+
+#define mmMME2_CTRL_SHADOW_2_DESC_META_DATA_AGU_L_LOCAL              0x160B10
+
+#define mmMME2_CTRL_SHADOW_2_DESC_META_DATA_AGU_L_REMOTE             0x160B14
+
+#define mmMME2_CTRL_SHADOW_2_DESC_META_DATA_AGU_O_LOCAL              0x160B18
+
+#define mmMME2_CTRL_SHADOW_2_DESC_META_DATA_AGU_O_REMOTE             0x160B1C
+
+#define mmMME2_CTRL_SHADOW_2_DESC_PCU_RL_SATURATION                  0x160B20
+
+#define mmMME2_CTRL_SHADOW_2_DESC_DUMMY                              0x160B24
+
+#define mmMME2_CTRL_SHADOW_3_STATUS                                  0x160B80
+
+#define mmMME2_CTRL_SHADOW_3_BASE_ADDR_HIGH_S                        0x160B88
+
+#define mmMME2_CTRL_SHADOW_3_BASE_ADDR_HIGH_L                        0x160B8C
+
+#define mmMME2_CTRL_SHADOW_3_BASE_ADDR_HIGH_O                        0x160B90
+
+#define mmMME2_CTRL_SHADOW_3_BASE_ADDR_LOW_S                         0x160B94
+
+#define mmMME2_CTRL_SHADOW_3_BASE_ADDR_LOW_L                         0x160B98
+
+#define mmMME2_CTRL_SHADOW_3_BASE_ADDR_LOW_O                         0x160B9C
+
+#define mmMME2_CTRL_SHADOW_3_HEADER_LOW                              0x160BA0
+
+#define mmMME2_CTRL_SHADOW_3_HEADER_HIGH                             0x160BA4
+
+#define mmMME2_CTRL_SHADOW_3_CONV_KERNEL_SIZE_MINUS_1                0x160BA8
+
+#define mmMME2_CTRL_SHADOW_3_CONV_ASSOCIATED_DIMS_LOW                0x160BAC
+
+#define mmMME2_CTRL_SHADOW_3_CONV_ASSOCIATED_DIMS_HIGH               0x160BB0
+
+#define mmMME2_CTRL_SHADOW_3_NUM_ITERATIONS_MINUS_1                  0x160BB4
+
+#define mmMME2_CTRL_SHADOW_3_OUTER_LOOP                              0x160BB8
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_0               0x160BBC
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_1               0x160BC0
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_2               0x160BC4
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_3               0x160BC8
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_4               0x160BCC
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_0                  0x160BD0
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_1                  0x160BD4
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_2                  0x160BD8
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_3                  0x160BDC
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_4                  0x160BE0
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_0                     0x160BE4
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_1                     0x160BE8
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_2                     0x160BEC
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_3                     0x160BF0
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_0              0x160BF4
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_1              0x160BF8
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_2              0x160BFC
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_3              0x160C00
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_S_SPATIAL_SIZE_MINUS_1           0x160C04
+
+#define mmMME2_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_0                 0x160C08
+
+#define mmMME2_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_1                 0x160C0C
+
+#define mmMME2_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_2                 0x160C10
+
+#define mmMME2_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_3                 0x160C14
+
+#define mmMME2_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_4                 0x160C18
+
+#define mmMME2_CTRL_SHADOW_3_AGU_S_START_OFFSET_0                    0x160C1C
+
+#define mmMME2_CTRL_SHADOW_3_AGU_S_START_OFFSET_1                    0x160C20
+
+#define mmMME2_CTRL_SHADOW_3_AGU_S_START_OFFSET_2                    0x160C24
+
+#define mmMME2_CTRL_SHADOW_3_AGU_S_START_OFFSET_3                    0x160C28
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_0               0x160C2C
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_1               0x160C30
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_2               0x160C34
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_3               0x160C38
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_4               0x160C3C
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_0                  0x160C40
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_1                  0x160C44
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_2                  0x160C48
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_3                  0x160C4C
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_4                  0x160C50
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_0                     0x160C54
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_1                     0x160C58
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_2                     0x160C5C
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_3                     0x160C60
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_0              0x160C64
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_1              0x160C68
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_2              0x160C6C
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_3              0x160C70
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_L_SPATIAL_SIZE_MINUS_1           0x160C74
+
+#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_0           0x160C78
+
+#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_1           0x160C7C
+
+#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_2           0x160C80
+
+#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_3           0x160C84
+
+#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_4           0x160C88
+
+#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_0              0x160C8C
+
+#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_1              0x160C90
+
+#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_2              0x160C94
+
+#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_3              0x160C98
+
+#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_0          0x160C9C
+
+#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_1          0x160CA0
+
+#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_2          0x160CA4
+
+#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_3          0x160CA8
+
+#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_4          0x160CAC
+
+#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_0             0x160CB0
+
+#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_1             0x160CB4
+
+#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_2             0x160CB8
+
+#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_3             0x160CBC
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_0               0x160CC0
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_1               0x160CC4
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_2               0x160CC8
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_3               0x160CCC
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_4               0x160CD0
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_0                  0x160CD4
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_1                  0x160CD8
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_2                  0x160CDC
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_3                  0x160CE0
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_4                  0x160CE4
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_0                     0x160CE8
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_1                     0x160CEC
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_2                     0x160CF0
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_3                     0x160CF4
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_0              0x160CF8
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_1              0x160CFC
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_2              0x160D00
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_3              0x160D04
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_O_SPATIAL_SIZE_MINUS_1           0x160D08
+
+#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_0           0x160D0C
+
+#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_1           0x160D10
+
+#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_2           0x160D14
+
+#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_3           0x160D18
+
+#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_4           0x160D1C
+
+#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_0              0x160D20
+
+#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_1              0x160D24
+
+#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_2              0x160D28
+
+#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_3              0x160D2C
+
+#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_0          0x160D30
+
+#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_1          0x160D34
+
+#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_2          0x160D38
+
+#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_3          0x160D3C
+
+#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_4          0x160D40
+
+#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_0             0x160D44
+
+#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_1             0x160D48
+
+#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_2             0x160D4C
+
+#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_3             0x160D50
+
+#define mmMME2_CTRL_SHADOW_3_DESC_SB_REPEAT                          0x160D54
+
+#define mmMME2_CTRL_SHADOW_3_DESC_RATE_LIMITER                       0x160D58
+
+#define mmMME2_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL         0x160D5C
+
+#define mmMME2_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE        0x160D60
+
+#define mmMME2_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_HIGH              0x160D64
+
+#define mmMME2_CTRL_SHADOW_3_DESC_SYNC_OBJECT_DATA                   0x160D68
+
+#define mmMME2_CTRL_SHADOW_3_DESC_AXI_USER_DATA                      0x160D6C
+
+#define mmMME2_CTRL_SHADOW_3_DESC_PERF_EVT_S                         0x160D70
+
+#define mmMME2_CTRL_SHADOW_3_DESC_PERF_EVT_L_LOCAL                   0x160D74
+
+#define mmMME2_CTRL_SHADOW_3_DESC_PERF_EVT_L_REMOTE                  0x160D78
+
+#define mmMME2_CTRL_SHADOW_3_DESC_PERF_EVT_O_LOCAL                   0x160D7C
+
+#define mmMME2_CTRL_SHADOW_3_DESC_PERF_EVT_O_REMOTE                  0x160D80
+
+#define mmMME2_CTRL_SHADOW_3_DESC_PADDING_VALUE_S                    0x160D84
+
+#define mmMME2_CTRL_SHADOW_3_DESC_PADDING_VALUE_L                    0x160D88
+
+#define mmMME2_CTRL_SHADOW_3_DESC_META_DATA_AGU_S                    0x160D8C
+
+#define mmMME2_CTRL_SHADOW_3_DESC_META_DATA_AGU_L_LOCAL              0x160D90
+
+#define mmMME2_CTRL_SHADOW_3_DESC_META_DATA_AGU_L_REMOTE             0x160D94
+
+#define mmMME2_CTRL_SHADOW_3_DESC_META_DATA_AGU_O_LOCAL              0x160D98
+
+#define mmMME2_CTRL_SHADOW_3_DESC_META_DATA_AGU_O_REMOTE             0x160D9C
+
+#define mmMME2_CTRL_SHADOW_3_DESC_PCU_RL_SATURATION                  0x160DA0
+
+#define mmMME2_CTRL_SHADOW_3_DESC_DUMMY                              0x160DA4
+
+#endif /* ASIC_REG_MME2_CTRL_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/mme2_qm_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/mme2_qm_regs.h
new file mode 100644
index 000000000000..c1ea6a422010
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/mme2_qm_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_MME2_QM_REGS_H_
+#define ASIC_REG_MME2_QM_REGS_H_
+
+/*
+ *****************************************
+ *   MME2_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmMME2_QM_GLBL_CFG0                                          0x168000
+
+#define mmMME2_QM_GLBL_CFG1                                          0x168004
+
+#define mmMME2_QM_GLBL_PROT                                          0x168008
+
+#define mmMME2_QM_GLBL_ERR_CFG                                       0x16800C
+
+#define mmMME2_QM_GLBL_SECURE_PROPS_0                                0x168010
+
+#define mmMME2_QM_GLBL_SECURE_PROPS_1                                0x168014
+
+#define mmMME2_QM_GLBL_SECURE_PROPS_2                                0x168018
+
+#define mmMME2_QM_GLBL_SECURE_PROPS_3                                0x16801C
+
+#define mmMME2_QM_GLBL_SECURE_PROPS_4                                0x168020
+
+#define mmMME2_QM_GLBL_NON_SECURE_PROPS_0                            0x168024
+
+#define mmMME2_QM_GLBL_NON_SECURE_PROPS_1                            0x168028
+
+#define mmMME2_QM_GLBL_NON_SECURE_PROPS_2                            0x16802C
+
+#define mmMME2_QM_GLBL_NON_SECURE_PROPS_3                            0x168030
+
+#define mmMME2_QM_GLBL_NON_SECURE_PROPS_4                            0x168034
+
+#define mmMME2_QM_GLBL_STS0                                          0x168038
+
+#define mmMME2_QM_GLBL_STS1_0                                        0x168040
+
+#define mmMME2_QM_GLBL_STS1_1                                        0x168044
+
+#define mmMME2_QM_GLBL_STS1_2                                        0x168048
+
+#define mmMME2_QM_GLBL_STS1_3                                        0x16804C
+
+#define mmMME2_QM_GLBL_STS1_4                                        0x168050
+
+#define mmMME2_QM_GLBL_MSG_EN_0                                      0x168054
+
+#define mmMME2_QM_GLBL_MSG_EN_1                                      0x168058
+
+#define mmMME2_QM_GLBL_MSG_EN_2                                      0x16805C
+
+#define mmMME2_QM_GLBL_MSG_EN_3                                      0x168060
+
+#define mmMME2_QM_GLBL_MSG_EN_4                                      0x168068
+
+#define mmMME2_QM_PQ_BASE_LO_0                                       0x168070
+
+#define mmMME2_QM_PQ_BASE_LO_1                                       0x168074
+
+#define mmMME2_QM_PQ_BASE_LO_2                                       0x168078
+
+#define mmMME2_QM_PQ_BASE_LO_3                                       0x16807C
+
+#define mmMME2_QM_PQ_BASE_HI_0                                       0x168080
+
+#define mmMME2_QM_PQ_BASE_HI_1                                       0x168084
+
+#define mmMME2_QM_PQ_BASE_HI_2                                       0x168088
+
+#define mmMME2_QM_PQ_BASE_HI_3                                       0x16808C
+
+#define mmMME2_QM_PQ_SIZE_0                                          0x168090
+
+#define mmMME2_QM_PQ_SIZE_1                                          0x168094
+
+#define mmMME2_QM_PQ_SIZE_2                                          0x168098
+
+#define mmMME2_QM_PQ_SIZE_3                                          0x16809C
+
+#define mmMME2_QM_PQ_PI_0                                            0x1680A0
+
+#define mmMME2_QM_PQ_PI_1                                            0x1680A4
+
+#define mmMME2_QM_PQ_PI_2                                            0x1680A8
+
+#define mmMME2_QM_PQ_PI_3                                            0x1680AC
+
+#define mmMME2_QM_PQ_CI_0                                            0x1680B0
+
+#define mmMME2_QM_PQ_CI_1                                            0x1680B4
+
+#define mmMME2_QM_PQ_CI_2                                            0x1680B8
+
+#define mmMME2_QM_PQ_CI_3                                            0x1680BC
+
+#define mmMME2_QM_PQ_CFG0_0                                          0x1680C0
+
+#define mmMME2_QM_PQ_CFG0_1                                          0x1680C4
+
+#define mmMME2_QM_PQ_CFG0_2                                          0x1680C8
+
+#define mmMME2_QM_PQ_CFG0_3                                          0x1680CC
+
+#define mmMME2_QM_PQ_CFG1_0                                          0x1680D0
+
+#define mmMME2_QM_PQ_CFG1_1                                          0x1680D4
+
+#define mmMME2_QM_PQ_CFG1_2                                          0x1680D8
+
+#define mmMME2_QM_PQ_CFG1_3                                          0x1680DC
+
+#define mmMME2_QM_PQ_ARUSER_31_11_0                                  0x1680E0
+
+#define mmMME2_QM_PQ_ARUSER_31_11_1                                  0x1680E4
+
+#define mmMME2_QM_PQ_ARUSER_31_11_2                                  0x1680E8
+
+#define mmMME2_QM_PQ_ARUSER_31_11_3                                  0x1680EC
+
+#define mmMME2_QM_PQ_STS0_0                                          0x1680F0
+
+#define mmMME2_QM_PQ_STS0_1                                          0x1680F4
+
+#define mmMME2_QM_PQ_STS0_2                                          0x1680F8
+
+#define mmMME2_QM_PQ_STS0_3                                          0x1680FC
+
+#define mmMME2_QM_PQ_STS1_0                                          0x168100
+
+#define mmMME2_QM_PQ_STS1_1                                          0x168104
+
+#define mmMME2_QM_PQ_STS1_2                                          0x168108
+
+#define mmMME2_QM_PQ_STS1_3                                          0x16810C
+
+#define mmMME2_QM_CQ_CFG0_0                                          0x168110
+
+#define mmMME2_QM_CQ_CFG0_1                                          0x168114
+
+#define mmMME2_QM_CQ_CFG0_2                                          0x168118
+
+#define mmMME2_QM_CQ_CFG0_3                                          0x16811C
+
+#define mmMME2_QM_CQ_CFG0_4                                          0x168120
+
+#define mmMME2_QM_CQ_CFG1_0                                          0x168124
+
+#define mmMME2_QM_CQ_CFG1_1                                          0x168128
+
+#define mmMME2_QM_CQ_CFG1_2                                          0x16812C
+
+#define mmMME2_QM_CQ_CFG1_3                                          0x168130
+
+#define mmMME2_QM_CQ_CFG1_4                                          0x168134
+
+#define mmMME2_QM_CQ_ARUSER_31_11_0                                  0x168138
+
+#define mmMME2_QM_CQ_ARUSER_31_11_1                                  0x16813C
+
+#define mmMME2_QM_CQ_ARUSER_31_11_2                                  0x168140
+
+#define mmMME2_QM_CQ_ARUSER_31_11_3                                  0x168144
+
+#define mmMME2_QM_CQ_ARUSER_31_11_4                                  0x168148
+
+#define mmMME2_QM_CQ_STS0_0                                          0x16814C
+
+#define mmMME2_QM_CQ_STS0_1                                          0x168150
+
+#define mmMME2_QM_CQ_STS0_2                                          0x168154
+
+#define mmMME2_QM_CQ_STS0_3                                          0x168158
+
+#define mmMME2_QM_CQ_STS0_4                                          0x16815C
+
+#define mmMME2_QM_CQ_STS1_0                                          0x168160
+
+#define mmMME2_QM_CQ_STS1_1                                          0x168164
+
+#define mmMME2_QM_CQ_STS1_2                                          0x168168
+
+#define mmMME2_QM_CQ_STS1_3                                          0x16816C
+
+#define mmMME2_QM_CQ_STS1_4                                          0x168170
+
+#define mmMME2_QM_CQ_PTR_LO_0                                        0x168174
+
+#define mmMME2_QM_CQ_PTR_HI_0                                        0x168178
+
+#define mmMME2_QM_CQ_TSIZE_0                                         0x16817C
+
+#define mmMME2_QM_CQ_CTL_0                                           0x168180
+
+#define mmMME2_QM_CQ_PTR_LO_1                                        0x168184
+
+#define mmMME2_QM_CQ_PTR_HI_1                                        0x168188
+
+#define mmMME2_QM_CQ_TSIZE_1                                         0x16818C
+
+#define mmMME2_QM_CQ_CTL_1                                           0x168190
+
+#define mmMME2_QM_CQ_PTR_LO_2                                        0x168194
+
+#define mmMME2_QM_CQ_PTR_HI_2                                        0x168198
+
+#define mmMME2_QM_CQ_TSIZE_2                                         0x16819C
+
+#define mmMME2_QM_CQ_CTL_2                                           0x1681A0
+
+#define mmMME2_QM_CQ_PTR_LO_3                                        0x1681A4
+
+#define mmMME2_QM_CQ_PTR_HI_3                                        0x1681A8
+
+#define mmMME2_QM_CQ_TSIZE_3                                         0x1681AC
+
+#define mmMME2_QM_CQ_CTL_3                                           0x1681B0
+
+#define mmMME2_QM_CQ_PTR_LO_4                                        0x1681B4
+
+#define mmMME2_QM_CQ_PTR_HI_4                                        0x1681B8
+
+#define mmMME2_QM_CQ_TSIZE_4                                         0x1681BC
+
+#define mmMME2_QM_CQ_CTL_4                                           0x1681C0
+
+#define mmMME2_QM_CQ_PTR_LO_STS_0                                    0x1681C4
+
+#define mmMME2_QM_CQ_PTR_LO_STS_1                                    0x1681C8
+
+#define mmMME2_QM_CQ_PTR_LO_STS_2                                    0x1681CC
+
+#define mmMME2_QM_CQ_PTR_LO_STS_3                                    0x1681D0
+
+#define mmMME2_QM_CQ_PTR_LO_STS_4                                    0x1681D4
+
+#define mmMME2_QM_CQ_PTR_HI_STS_0                                    0x1681D8
+
+#define mmMME2_QM_CQ_PTR_HI_STS_1                                    0x1681DC
+
+#define mmMME2_QM_CQ_PTR_HI_STS_2                                    0x1681E0
+
+#define mmMME2_QM_CQ_PTR_HI_STS_3                                    0x1681E4
+
+#define mmMME2_QM_CQ_PTR_HI_STS_4                                    0x1681E8
+
+#define mmMME2_QM_CQ_TSIZE_STS_0                                     0x1681EC
+
+#define mmMME2_QM_CQ_TSIZE_STS_1                                     0x1681F0
+
+#define mmMME2_QM_CQ_TSIZE_STS_2                                     0x1681F4
+
+#define mmMME2_QM_CQ_TSIZE_STS_3                                     0x1681F8
+
+#define mmMME2_QM_CQ_TSIZE_STS_4                                     0x1681FC
+
+#define mmMME2_QM_CQ_CTL_STS_0                                       0x168200
+
+#define mmMME2_QM_CQ_CTL_STS_1                                       0x168204
+
+#define mmMME2_QM_CQ_CTL_STS_2                                       0x168208
+
+#define mmMME2_QM_CQ_CTL_STS_3                                       0x16820C
+
+#define mmMME2_QM_CQ_CTL_STS_4                                       0x168210
+
+#define mmMME2_QM_CQ_IFIFO_CNT_0                                     0x168214
+
+#define mmMME2_QM_CQ_IFIFO_CNT_1                                     0x168218
+
+#define mmMME2_QM_CQ_IFIFO_CNT_2                                     0x16821C
+
+#define mmMME2_QM_CQ_IFIFO_CNT_3                                     0x168220
+
+#define mmMME2_QM_CQ_IFIFO_CNT_4                                     0x168224
+
+#define mmMME2_QM_CP_MSG_BASE0_ADDR_LO_0                             0x168228
+
+#define mmMME2_QM_CP_MSG_BASE0_ADDR_LO_1                             0x16822C
+
+#define mmMME2_QM_CP_MSG_BASE0_ADDR_LO_2                             0x168230
+
+#define mmMME2_QM_CP_MSG_BASE0_ADDR_LO_3                             0x168234
+
+#define mmMME2_QM_CP_MSG_BASE0_ADDR_LO_4                             0x168238
+
+#define mmMME2_QM_CP_MSG_BASE0_ADDR_HI_0                             0x16823C
+
+#define mmMME2_QM_CP_MSG_BASE0_ADDR_HI_1                             0x168240
+
+#define mmMME2_QM_CP_MSG_BASE0_ADDR_HI_2                             0x168244
+
+#define mmMME2_QM_CP_MSG_BASE0_ADDR_HI_3                             0x168248
+
+#define mmMME2_QM_CP_MSG_BASE0_ADDR_HI_4                             0x16824C
+
+#define mmMME2_QM_CP_MSG_BASE1_ADDR_LO_0                             0x168250
+
+#define mmMME2_QM_CP_MSG_BASE1_ADDR_LO_1                             0x168254
+
+#define mmMME2_QM_CP_MSG_BASE1_ADDR_LO_2                             0x168258
+
+#define mmMME2_QM_CP_MSG_BASE1_ADDR_LO_3                             0x16825C
+
+#define mmMME2_QM_CP_MSG_BASE1_ADDR_LO_4                             0x168260
+
+#define mmMME2_QM_CP_MSG_BASE1_ADDR_HI_0                             0x168264
+
+#define mmMME2_QM_CP_MSG_BASE1_ADDR_HI_1                             0x168268
+
+#define mmMME2_QM_CP_MSG_BASE1_ADDR_HI_2                             0x16826C
+
+#define mmMME2_QM_CP_MSG_BASE1_ADDR_HI_3                             0x168270
+
+#define mmMME2_QM_CP_MSG_BASE1_ADDR_HI_4                             0x168274
+
+#define mmMME2_QM_CP_MSG_BASE2_ADDR_LO_0                             0x168278
+
+#define mmMME2_QM_CP_MSG_BASE2_ADDR_LO_1                             0x16827C
+
+#define mmMME2_QM_CP_MSG_BASE2_ADDR_LO_2                             0x168280
+
+#define mmMME2_QM_CP_MSG_BASE2_ADDR_LO_3                             0x168284
+
+#define mmMME2_QM_CP_MSG_BASE2_ADDR_LO_4                             0x168288
+
+#define mmMME2_QM_CP_MSG_BASE2_ADDR_HI_0                             0x16828C
+
+#define mmMME2_QM_CP_MSG_BASE2_ADDR_HI_1                             0x168290
+
+#define mmMME2_QM_CP_MSG_BASE2_ADDR_HI_2                             0x168294
+
+#define mmMME2_QM_CP_MSG_BASE2_ADDR_HI_3                             0x168298
+
+#define mmMME2_QM_CP_MSG_BASE2_ADDR_HI_4                             0x16829C
+
+#define mmMME2_QM_CP_MSG_BASE3_ADDR_LO_0                             0x1682A0
+
+#define mmMME2_QM_CP_MSG_BASE3_ADDR_LO_1                             0x1682A4
+
+#define mmMME2_QM_CP_MSG_BASE3_ADDR_LO_2                             0x1682A8
+
+#define mmMME2_QM_CP_MSG_BASE3_ADDR_LO_3                             0x1682AC
+
+#define mmMME2_QM_CP_MSG_BASE3_ADDR_LO_4                             0x1682B0
+
+#define mmMME2_QM_CP_MSG_BASE3_ADDR_HI_0                             0x1682B4
+
+#define mmMME2_QM_CP_MSG_BASE3_ADDR_HI_1                             0x1682B8
+
+#define mmMME2_QM_CP_MSG_BASE3_ADDR_HI_2                             0x1682BC
+
+#define mmMME2_QM_CP_MSG_BASE3_ADDR_HI_3                             0x1682C0
+
+#define mmMME2_QM_CP_MSG_BASE3_ADDR_HI_4                             0x1682C4
+
+#define mmMME2_QM_CP_LDMA_TSIZE_OFFSET_0                             0x1682C8
+
+#define mmMME2_QM_CP_LDMA_TSIZE_OFFSET_1                             0x1682CC
+
+#define mmMME2_QM_CP_LDMA_TSIZE_OFFSET_2                             0x1682D0
+
+#define mmMME2_QM_CP_LDMA_TSIZE_OFFSET_3                             0x1682D4
+
+#define mmMME2_QM_CP_LDMA_TSIZE_OFFSET_4                             0x1682D8
+
+#define mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0                       0x1682E0
+
+#define mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1                       0x1682E4
+
+#define mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2                       0x1682E8
+
+#define mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3                       0x1682EC
+
+#define mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4                       0x1682F0
+
+#define mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_0                       0x1682F4
+
+#define mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_1                       0x1682F8
+
+#define mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_2                       0x1682FC
+
+#define mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3                       0x168300
+
+#define mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_4                       0x168304
+
+#define mmMME2_QM_CP_FENCE0_RDATA_0                                  0x168308
+
+#define mmMME2_QM_CP_FENCE0_RDATA_1                                  0x16830C
+
+#define mmMME2_QM_CP_FENCE0_RDATA_2                                  0x168310
+
+#define mmMME2_QM_CP_FENCE0_RDATA_3                                  0x168314
+
+#define mmMME2_QM_CP_FENCE0_RDATA_4                                  0x168318
+
+#define mmMME2_QM_CP_FENCE1_RDATA_0                                  0x16831C
+
+#define mmMME2_QM_CP_FENCE1_RDATA_1                                  0x168320
+
+#define mmMME2_QM_CP_FENCE1_RDATA_2                                  0x168324
+
+#define mmMME2_QM_CP_FENCE1_RDATA_3                                  0x168328
+
+#define mmMME2_QM_CP_FENCE1_RDATA_4                                  0x16832C
+
+#define mmMME2_QM_CP_FENCE2_RDATA_0                                  0x168330
+
+#define mmMME2_QM_CP_FENCE2_RDATA_1                                  0x168334
+
+#define mmMME2_QM_CP_FENCE2_RDATA_2                                  0x168338
+
+#define mmMME2_QM_CP_FENCE2_RDATA_3                                  0x16833C
+
+#define mmMME2_QM_CP_FENCE2_RDATA_4                                  0x168340
+
+#define mmMME2_QM_CP_FENCE3_RDATA_0                                  0x168344
+
+#define mmMME2_QM_CP_FENCE3_RDATA_1                                  0x168348
+
+#define mmMME2_QM_CP_FENCE3_RDATA_2                                  0x16834C
+
+#define mmMME2_QM_CP_FENCE3_RDATA_3                                  0x168350
+
+#define mmMME2_QM_CP_FENCE3_RDATA_4                                  0x168354
+
+#define mmMME2_QM_CP_FENCE0_CNT_0                                    0x168358
+
+#define mmMME2_QM_CP_FENCE0_CNT_1                                    0x16835C
+
+#define mmMME2_QM_CP_FENCE0_CNT_2                                    0x168360
+
+#define mmMME2_QM_CP_FENCE0_CNT_3                                    0x168364
+
+#define mmMME2_QM_CP_FENCE0_CNT_4                                    0x168368
+
+#define mmMME2_QM_CP_FENCE1_CNT_0                                    0x16836C
+
+#define mmMME2_QM_CP_FENCE1_CNT_1                                    0x168370
+
+#define mmMME2_QM_CP_FENCE1_CNT_2                                    0x168374
+
+#define mmMME2_QM_CP_FENCE1_CNT_3                                    0x168378
+
+#define mmMME2_QM_CP_FENCE1_CNT_4                                    0x16837C
+
+#define mmMME2_QM_CP_FENCE2_CNT_0                                    0x168380
+
+#define mmMME2_QM_CP_FENCE2_CNT_1                                    0x168384
+
+#define mmMME2_QM_CP_FENCE2_CNT_2                                    0x168388
+
+#define mmMME2_QM_CP_FENCE2_CNT_3                                    0x16838C
+
+#define mmMME2_QM_CP_FENCE2_CNT_4                                    0x168390
+
+#define mmMME2_QM_CP_FENCE3_CNT_0                                    0x168394
+
+#define mmMME2_QM_CP_FENCE3_CNT_1                                    0x168398
+
+#define mmMME2_QM_CP_FENCE3_CNT_2                                    0x16839C
+
+#define mmMME2_QM_CP_FENCE3_CNT_3                                    0x1683A0
+
+#define mmMME2_QM_CP_FENCE3_CNT_4                                    0x1683A4
+
+#define mmMME2_QM_CP_STS_0                                           0x1683A8
+
+#define mmMME2_QM_CP_STS_1                                           0x1683AC
+
+#define mmMME2_QM_CP_STS_2                                           0x1683B0
+
+#define mmMME2_QM_CP_STS_3                                           0x1683B4
+
+#define mmMME2_QM_CP_STS_4                                           0x1683B8
+
+#define mmMME2_QM_CP_CURRENT_INST_LO_0                               0x1683BC
+
+#define mmMME2_QM_CP_CURRENT_INST_LO_1                               0x1683C0
+
+#define mmMME2_QM_CP_CURRENT_INST_LO_2                               0x1683C4
+
+#define mmMME2_QM_CP_CURRENT_INST_LO_3                               0x1683C8
+
+#define mmMME2_QM_CP_CURRENT_INST_LO_4                               0x1683CC
+
+#define mmMME2_QM_CP_CURRENT_INST_HI_0                               0x1683D0
+
+#define mmMME2_QM_CP_CURRENT_INST_HI_1                               0x1683D4
+
+#define mmMME2_QM_CP_CURRENT_INST_HI_2                               0x1683D8
+
+#define mmMME2_QM_CP_CURRENT_INST_HI_3                               0x1683DC
+
+#define mmMME2_QM_CP_CURRENT_INST_HI_4                               0x1683E0
+
+#define mmMME2_QM_CP_BARRIER_CFG_0                                   0x1683F4
+
+#define mmMME2_QM_CP_BARRIER_CFG_1                                   0x1683F8
+
+#define mmMME2_QM_CP_BARRIER_CFG_2                                   0x1683FC
+
+#define mmMME2_QM_CP_BARRIER_CFG_3                                   0x168400
+
+#define mmMME2_QM_CP_BARRIER_CFG_4                                   0x168404
+
+#define mmMME2_QM_CP_DBG_0_0                                         0x168408
+
+#define mmMME2_QM_CP_DBG_0_1                                         0x16840C
+
+#define mmMME2_QM_CP_DBG_0_2                                         0x168410
+
+#define mmMME2_QM_CP_DBG_0_3                                         0x168414
+
+#define mmMME2_QM_CP_DBG_0_4                                         0x168418
+
+#define mmMME2_QM_CP_ARUSER_31_11_0                                  0x16841C
+
+#define mmMME2_QM_CP_ARUSER_31_11_1                                  0x168420
+
+#define mmMME2_QM_CP_ARUSER_31_11_2                                  0x168424
+
+#define mmMME2_QM_CP_ARUSER_31_11_3                                  0x168428
+
+#define mmMME2_QM_CP_ARUSER_31_11_4                                  0x16842C
+
+#define mmMME2_QM_CP_AWUSER_31_11_0                                  0x168430
+
+#define mmMME2_QM_CP_AWUSER_31_11_1                                  0x168434
+
+#define mmMME2_QM_CP_AWUSER_31_11_2                                  0x168438
+
+#define mmMME2_QM_CP_AWUSER_31_11_3                                  0x16843C
+
+#define mmMME2_QM_CP_AWUSER_31_11_4                                  0x168440
+
+#define mmMME2_QM_ARB_CFG_0                                          0x168A00
+
+#define mmMME2_QM_ARB_CHOISE_Q_PUSH                                  0x168A04
+
+#define mmMME2_QM_ARB_WRR_WEIGHT_0                                   0x168A08
+
+#define mmMME2_QM_ARB_WRR_WEIGHT_1                                   0x168A0C
+
+#define mmMME2_QM_ARB_WRR_WEIGHT_2                                   0x168A10
+
+#define mmMME2_QM_ARB_WRR_WEIGHT_3                                   0x168A14
+
+#define mmMME2_QM_ARB_CFG_1                                          0x168A18
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_0                               0x168A20
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_1                               0x168A24
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_2                               0x168A28
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_3                               0x168A2C
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_4                               0x168A30
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_5                               0x168A34
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_6                               0x168A38
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_7                               0x168A3C
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_8                               0x168A40
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_9                               0x168A44
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_10                              0x168A48
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_11                              0x168A4C
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_12                              0x168A50
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_13                              0x168A54
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_14                              0x168A58
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_15                              0x168A5C
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_16                              0x168A60
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_17                              0x168A64
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_18                              0x168A68
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_19                              0x168A6C
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_20                              0x168A70
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_21                              0x168A74
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_22                              0x168A78
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_23                              0x168A7C
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_24                              0x168A80
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_25                              0x168A84
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_26                              0x168A88
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_27                              0x168A8C
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_28                              0x168A90
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_29                              0x168A94
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_30                              0x168A98
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_31                              0x168A9C
+
+#define mmMME2_QM_ARB_MST_CRED_INC                                   0x168AA0
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_0                         0x168AA4
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_1                         0x168AA8
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_2                         0x168AAC
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_3                         0x168AB0
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_4                         0x168AB4
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_5                         0x168AB8
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_6                         0x168ABC
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_7                         0x168AC0
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_8                         0x168AC4
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_9                         0x168AC8
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_10                        0x168ACC
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_11                        0x168AD0
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_12                        0x168AD4
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_13                        0x168AD8
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_14                        0x168ADC
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_15                        0x168AE0
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_16                        0x168AE4
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_17                        0x168AE8
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_18                        0x168AEC
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_19                        0x168AF0
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_20                        0x168AF4
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_21                        0x168AF8
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_22                        0x168AFC
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_23                        0x168B00
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_24                        0x168B04
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_25                        0x168B08
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_26                        0x168B0C
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_27                        0x168B10
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_28                        0x168B14
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_29                        0x168B18
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_30                        0x168B1C
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_31                        0x168B20
+
+#define mmMME2_QM_ARB_SLV_MASTER_INC_CRED_OFST                       0x168B28
+
+#define mmMME2_QM_ARB_MST_SLAVE_EN                                   0x168B2C
+
+#define mmMME2_QM_ARB_MST_QUIET_PER                                  0x168B34
+
+#define mmMME2_QM_ARB_SLV_CHOISE_WDT                                 0x168B38
+
+#define mmMME2_QM_ARB_SLV_ID                                         0x168B3C
+
+#define mmMME2_QM_ARB_MSG_MAX_INFLIGHT                               0x168B44
+
+#define mmMME2_QM_ARB_MSG_AWUSER_31_11                               0x168B48
+
+#define mmMME2_QM_ARB_MSG_AWUSER_SEC_PROP                            0x168B4C
+
+#define mmMME2_QM_ARB_MSG_AWUSER_NON_SEC_PROP                        0x168B50
+
+#define mmMME2_QM_ARB_BASE_LO                                        0x168B54
+
+#define mmMME2_QM_ARB_BASE_HI                                        0x168B58
+
+#define mmMME2_QM_ARB_STATE_STS                                      0x168B80
+
+#define mmMME2_QM_ARB_CHOISE_FULLNESS_STS                            0x168B84
+
+#define mmMME2_QM_ARB_MSG_STS                                        0x168B88
+
+#define mmMME2_QM_ARB_SLV_CHOISE_Q_HEAD                              0x168B8C
+
+#define mmMME2_QM_ARB_ERR_CAUSE                                      0x168B9C
+
+#define mmMME2_QM_ARB_ERR_MSG_EN                                     0x168BA0
+
+#define mmMME2_QM_ARB_ERR_STS_DRP                                    0x168BA8
+
+#define mmMME2_QM_ARB_MST_CRED_STS_0                                 0x168BB0
+
+#define mmMME2_QM_ARB_MST_CRED_STS_1                                 0x168BB4
+
+#define mmMME2_QM_ARB_MST_CRED_STS_2                                 0x168BB8
+
+#define mmMME2_QM_ARB_MST_CRED_STS_3                                 0x168BBC
+
+#define mmMME2_QM_ARB_MST_CRED_STS_4                                 0x168BC0
+
+#define mmMME2_QM_ARB_MST_CRED_STS_5                                 0x168BC4
+
+#define mmMME2_QM_ARB_MST_CRED_STS_6                                 0x168BC8
+
+#define mmMME2_QM_ARB_MST_CRED_STS_7                                 0x168BCC
+
+#define mmMME2_QM_ARB_MST_CRED_STS_8                                 0x168BD0
+
+#define mmMME2_QM_ARB_MST_CRED_STS_9                                 0x168BD4
+
+#define mmMME2_QM_ARB_MST_CRED_STS_10                                0x168BD8
+
+#define mmMME2_QM_ARB_MST_CRED_STS_11                                0x168BDC
+
+#define mmMME2_QM_ARB_MST_CRED_STS_12                                0x168BE0
+
+#define mmMME2_QM_ARB_MST_CRED_STS_13                                0x168BE4
+
+#define mmMME2_QM_ARB_MST_CRED_STS_14                                0x168BE8
+
+#define mmMME2_QM_ARB_MST_CRED_STS_15                                0x168BEC
+
+#define mmMME2_QM_ARB_MST_CRED_STS_16                                0x168BF0
+
+#define mmMME2_QM_ARB_MST_CRED_STS_17                                0x168BF4
+
+#define mmMME2_QM_ARB_MST_CRED_STS_18                                0x168BF8
+
+#define mmMME2_QM_ARB_MST_CRED_STS_19                                0x168BFC
+
+#define mmMME2_QM_ARB_MST_CRED_STS_20                                0x168C00
+
+#define mmMME2_QM_ARB_MST_CRED_STS_21                                0x168C04
+
+#define mmMME2_QM_ARB_MST_CRED_STS_22                                0x168C08
+
+#define mmMME2_QM_ARB_MST_CRED_STS_23                                0x168C0C
+
+#define mmMME2_QM_ARB_MST_CRED_STS_24                                0x168C10
+
+#define mmMME2_QM_ARB_MST_CRED_STS_25                                0x168C14
+
+#define mmMME2_QM_ARB_MST_CRED_STS_26                                0x168C18
+
+#define mmMME2_QM_ARB_MST_CRED_STS_27                                0x168C1C
+
+#define mmMME2_QM_ARB_MST_CRED_STS_28                                0x168C20
+
+#define mmMME2_QM_ARB_MST_CRED_STS_29                                0x168C24
+
+#define mmMME2_QM_ARB_MST_CRED_STS_30                                0x168C28
+
+#define mmMME2_QM_ARB_MST_CRED_STS_31                                0x168C2C
+
+#define mmMME2_QM_CGM_CFG                                            0x168C70
+
+#define mmMME2_QM_CGM_STS                                            0x168C74
+
+#define mmMME2_QM_CGM_CFG1                                           0x168C78
+
+#define mmMME2_QM_LOCAL_RANGE_BASE                                   0x168C80
+
+#define mmMME2_QM_LOCAL_RANGE_SIZE                                   0x168C84
+
+#define mmMME2_QM_CSMR_STRICT_PRIO_CFG                               0x168C90
+
+#define mmMME2_QM_HBW_RD_RATE_LIM_CFG_1                              0x168C94
+
+#define mmMME2_QM_LBW_WR_RATE_LIM_CFG_0                              0x168C98
+
+#define mmMME2_QM_LBW_WR_RATE_LIM_CFG_1                              0x168C9C
+
+#define mmMME2_QM_HBW_RD_RATE_LIM_CFG_0                              0x168CA0
+
+#define mmMME2_QM_GLBL_AXCACHE                                       0x168CA4
+
+#define mmMME2_QM_IND_GW_APB_CFG                                     0x168CB0
+
+#define mmMME2_QM_IND_GW_APB_WDATA                                   0x168CB4
+
+#define mmMME2_QM_IND_GW_APB_RDATA                                   0x168CB8
+
+#define mmMME2_QM_IND_GW_APB_STATUS                                  0x168CBC
+
+#define mmMME2_QM_GLBL_ERR_ADDR_LO                                   0x168CD0
+
+#define mmMME2_QM_GLBL_ERR_ADDR_HI                                   0x168CD4
+
+#define mmMME2_QM_GLBL_ERR_WDATA                                     0x168CD8
+
+#define mmMME2_QM_GLBL_MEM_INIT_BUSY                                 0x168D00
+
+#endif /* ASIC_REG_MME2_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/mme3_ctrl_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/mme3_ctrl_regs.h
new file mode 100644
index 000000000000..36f6edc72e3d
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/mme3_ctrl_regs.h
@@ -0,0 +1,1456 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_MME3_CTRL_REGS_H_
+#define ASIC_REG_MME3_CTRL_REGS_H_
+
+/*
+ *****************************************
+ *   MME3_CTRL (Prototype: MME)
+ *****************************************
+ */
+
+#define mmMME3_CTRL_ARCH_STATUS                                      0x1E0000
+
+#define mmMME3_CTRL_ARCH_BASE_ADDR_HIGH_S                            0x1E0008
+
+#define mmMME3_CTRL_ARCH_BASE_ADDR_HIGH_L                            0x1E000C
+
+#define mmMME3_CTRL_ARCH_BASE_ADDR_HIGH_O                            0x1E0010
+
+#define mmMME3_CTRL_ARCH_BASE_ADDR_LOW_S                             0x1E0014
+
+#define mmMME3_CTRL_ARCH_BASE_ADDR_LOW_L                             0x1E0018
+
+#define mmMME3_CTRL_ARCH_BASE_ADDR_LOW_O                             0x1E001C
+
+#define mmMME3_CTRL_ARCH_HEADER_LOW                                  0x1E0020
+
+#define mmMME3_CTRL_ARCH_HEADER_HIGH                                 0x1E0024
+
+#define mmMME3_CTRL_ARCH_CONV_KERNEL_SIZE_MINUS_1                    0x1E0028
+
+#define mmMME3_CTRL_ARCH_CONV_ASSOCIATED_DIMS_LOW                    0x1E002C
+
+#define mmMME3_CTRL_ARCH_CONV_ASSOCIATED_DIMS_HIGH                   0x1E0030
+
+#define mmMME3_CTRL_ARCH_NUM_ITERATIONS_MINUS_1                      0x1E0034
+
+#define mmMME3_CTRL_ARCH_OUTER_LOOP                                  0x1E0038
+
+#define mmMME3_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_0                   0x1E003C
+
+#define mmMME3_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_1                   0x1E0040
+
+#define mmMME3_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_2                   0x1E0044
+
+#define mmMME3_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_3                   0x1E0048
+
+#define mmMME3_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_4                   0x1E004C
+
+#define mmMME3_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_0                      0x1E0050
+
+#define mmMME3_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_1                      0x1E0054
+
+#define mmMME3_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_2                      0x1E0058
+
+#define mmMME3_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_3                      0x1E005C
+
+#define mmMME3_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_4                      0x1E0060
+
+#define mmMME3_CTRL_ARCH_TENSOR_S_ROI_SIZE_0                         0x1E0064
+
+#define mmMME3_CTRL_ARCH_TENSOR_S_ROI_SIZE_1                         0x1E0068
+
+#define mmMME3_CTRL_ARCH_TENSOR_S_ROI_SIZE_2                         0x1E006C
+
+#define mmMME3_CTRL_ARCH_TENSOR_S_ROI_SIZE_3                         0x1E0070
+
+#define mmMME3_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_0                  0x1E0074
+
+#define mmMME3_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_1                  0x1E0078
+
+#define mmMME3_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_2                  0x1E007C
+
+#define mmMME3_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_3                  0x1E0080
+
+#define mmMME3_CTRL_ARCH_TENSOR_S_SPATIAL_SIZE_MINUS_1               0x1E0084
+
+#define mmMME3_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_0                     0x1E0088
+
+#define mmMME3_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_1                     0x1E008C
+
+#define mmMME3_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_2                     0x1E0090
+
+#define mmMME3_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_3                     0x1E0094
+
+#define mmMME3_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_4                     0x1E0098
+
+#define mmMME3_CTRL_ARCH_AGU_S_START_OFFSET_0                        0x1E009C
+
+#define mmMME3_CTRL_ARCH_AGU_S_START_OFFSET_1                        0x1E00A0
+
+#define mmMME3_CTRL_ARCH_AGU_S_START_OFFSET_2                        0x1E00A4
+
+#define mmMME3_CTRL_ARCH_AGU_S_START_OFFSET_3                        0x1E00A8
+
+#define mmMME3_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_0                   0x1E00AC
+
+#define mmMME3_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_1                   0x1E00B0
+
+#define mmMME3_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_2                   0x1E00B4
+
+#define mmMME3_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_3                   0x1E00B8
+
+#define mmMME3_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_4                   0x1E00BC
+
+#define mmMME3_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_0                      0x1E00C0
+
+#define mmMME3_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_1                      0x1E00C4
+
+#define mmMME3_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_2                      0x1E00C8
+
+#define mmMME3_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_3                      0x1E00CC
+
+#define mmMME3_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_4                      0x1E00D0
+
+#define mmMME3_CTRL_ARCH_TENSOR_L_ROI_SIZE_0                         0x1E00D4
+
+#define mmMME3_CTRL_ARCH_TENSOR_L_ROI_SIZE_1                         0x1E00D8
+
+#define mmMME3_CTRL_ARCH_TENSOR_L_ROI_SIZE_2                         0x1E00DC
+
+#define mmMME3_CTRL_ARCH_TENSOR_L_ROI_SIZE_3                         0x1E00E0
+
+#define mmMME3_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_0                  0x1E00E4
+
+#define mmMME3_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_1                  0x1E00E8
+
+#define mmMME3_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_2                  0x1E00EC
+
+#define mmMME3_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_3                  0x1E00F0
+
+#define mmMME3_CTRL_ARCH_TENSOR_L_SPATIAL_SIZE_MINUS_1               0x1E00F4
+
+#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_0               0x1E00F8
+
+#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_1               0x1E00FC
+
+#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_2               0x1E0100
+
+#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_3               0x1E0104
+
+#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_4               0x1E0108
+
+#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_0                  0x1E010C
+
+#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_1                  0x1E0110
+
+#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_2                  0x1E0114
+
+#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_3                  0x1E0118
+
+#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_0              0x1E011C
+
+#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_1              0x1E0120
+
+#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_2              0x1E0124
+
+#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_3              0x1E0128
+
+#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_4              0x1E012C
+
+#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_0                 0x1E0130
+
+#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_1                 0x1E0134
+
+#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_2                 0x1E0138
+
+#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_3                 0x1E013C
+
+#define mmMME3_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_0                   0x1E0140
+
+#define mmMME3_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_1                   0x1E0144
+
+#define mmMME3_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_2                   0x1E0148
+
+#define mmMME3_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_3                   0x1E014C
+
+#define mmMME3_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_4                   0x1E0150
+
+#define mmMME3_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_0                      0x1E0154
+
+#define mmMME3_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_1                      0x1E0158
+
+#define mmMME3_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_2                      0x1E015C
+
+#define mmMME3_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_3                      0x1E0160
+
+#define mmMME3_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_4                      0x1E0164
+
+#define mmMME3_CTRL_ARCH_TENSOR_O_ROI_SIZE_0                         0x1E0168
+
+#define mmMME3_CTRL_ARCH_TENSOR_O_ROI_SIZE_1                         0x1E016C
+
+#define mmMME3_CTRL_ARCH_TENSOR_O_ROI_SIZE_2                         0x1E0170
+
+#define mmMME3_CTRL_ARCH_TENSOR_O_ROI_SIZE_3                         0x1E0174
+
+#define mmMME3_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_0                  0x1E0178
+
+#define mmMME3_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_1                  0x1E017C
+
+#define mmMME3_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_2                  0x1E0180
+
+#define mmMME3_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_3                  0x1E0184
+
+#define mmMME3_CTRL_ARCH_TENSOR_O_SPATIAL_SIZE_MINUS_1               0x1E0188
+
+#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_0               0x1E018C
+
+#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_1               0x1E0190
+
+#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_2               0x1E0194
+
+#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_3               0x1E0198
+
+#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_4               0x1E019C
+
+#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_0                  0x1E01A0
+
+#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_1                  0x1E01A4
+
+#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_2                  0x1E01A8
+
+#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_3                  0x1E01AC
+
+#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_0              0x1E01B0
+
+#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_1              0x1E01B4
+
+#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_2              0x1E01B8
+
+#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_3              0x1E01BC
+
+#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_4              0x1E01C0
+
+#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_0                 0x1E01C4
+
+#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_1                 0x1E01C8
+
+#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_2                 0x1E01CC
+
+#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_3                 0x1E01D0
+
+#define mmMME3_CTRL_ARCH_DESC_SB_REPEAT                              0x1E01D4
+
+#define mmMME3_CTRL_ARCH_DESC_RATE_LIMITER                           0x1E01D8
+
+#define mmMME3_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL             0x1E01DC
+
+#define mmMME3_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE            0x1E01E0
+
+#define mmMME3_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_HIGH                  0x1E01E4
+
+#define mmMME3_CTRL_ARCH_DESC_SYNC_OBJECT_DATA                       0x1E01E8
+
+#define mmMME3_CTRL_ARCH_DESC_AXI_USER_DATA                          0x1E01EC
+
+#define mmMME3_CTRL_ARCH_DESC_PERF_EVT_S                             0x1E01F0
+
+#define mmMME3_CTRL_ARCH_DESC_PERF_EVT_L_LOCAL                       0x1E01F4
+
+#define mmMME3_CTRL_ARCH_DESC_PERF_EVT_L_REMOTE                      0x1E01F8
+
+#define mmMME3_CTRL_ARCH_DESC_PERF_EVT_O_LOCAL                       0x1E01FC
+
+#define mmMME3_CTRL_ARCH_DESC_PERF_EVT_O_REMOTE                      0x1E0200
+
+#define mmMME3_CTRL_ARCH_DESC_PADDING_VALUE_S                        0x1E0204
+
+#define mmMME3_CTRL_ARCH_DESC_PADDING_VALUE_L                        0x1E0208
+
+#define mmMME3_CTRL_ARCH_DESC_META_DATA_AGU_S                        0x1E020C
+
+#define mmMME3_CTRL_ARCH_DESC_META_DATA_AGU_L_LOCAL                  0x1E0210
+
+#define mmMME3_CTRL_ARCH_DESC_META_DATA_AGU_L_REMOTE                 0x1E0214
+
+#define mmMME3_CTRL_ARCH_DESC_META_DATA_AGU_O_LOCAL                  0x1E0218
+
+#define mmMME3_CTRL_ARCH_DESC_META_DATA_AGU_O_REMOTE                 0x1E021C
+
+#define mmMME3_CTRL_ARCH_DESC_PCU_RL_SATURATION                      0x1E0220
+
+#define mmMME3_CTRL_ARCH_DESC_DUMMY                                  0x1E0224
+
+#define mmMME3_CTRL_CMD                                              0x1E0280
+
+#define mmMME3_CTRL_STATUS1                                          0x1E0284
+
+#define mmMME3_CTRL_RESET                                            0x1E0288
+
+#define mmMME3_CTRL_QM_STALL                                         0x1E028C
+
+#define mmMME3_CTRL_SYNC_OBJECT_FIFO_TH                              0x1E0290
+
+#define mmMME3_CTRL_EUS_ROLLUP_CNT_ADD                               0x1E0294
+
+#define mmMME3_CTRL_INTR_CAUSE                                       0x1E0298
+
+#define mmMME3_CTRL_INTR_MASK                                        0x1E029C
+
+#define mmMME3_CTRL_LOG_SHADOW                                       0x1E02A0
+
+#define mmMME3_CTRL_PCU_RL_DESC0                                     0x1E02A4
+
+#define mmMME3_CTRL_PCU_RL_TOKEN_UPDATE                              0x1E02A8
+
+#define mmMME3_CTRL_PCU_RL_TH                                        0x1E02AC
+
+#define mmMME3_CTRL_PCU_RL_MIN                                       0x1E02B0
+
+#define mmMME3_CTRL_PCU_RL_CTRL_EN                                   0x1E02B4
+
+#define mmMME3_CTRL_PCU_RL_HISTORY_LOG_SIZE                          0x1E02B8
+
+#define mmMME3_CTRL_PCU_DUMMY_A_BF16                                 0x1E02BC
+
+#define mmMME3_CTRL_PCU_DUMMY_B_BF16                                 0x1E02C0
+
+#define mmMME3_CTRL_PCU_DUMMY_A_FP32_ODD                             0x1E02C4
+
+#define mmMME3_CTRL_PCU_DUMMY_A_FP32_EVEN                            0x1E02C8
+
+#define mmMME3_CTRL_PCU_DUMMY_B_FP32_ODD                             0x1E02CC
+
+#define mmMME3_CTRL_PCU_DUMMY_B_FP32_EVEN                            0x1E02D0
+
+#define mmMME3_CTRL_PROT                                             0x1E02D4
+
+#define mmMME3_CTRL_EU_POWER_SAVE_DISABLE                            0x1E02D8
+
+#define mmMME3_CTRL_CS_DBG_BLOCK_ID                                  0x1E02DC
+
+#define mmMME3_CTRL_CS_DBG_STATUS_DROP_CNT                           0x1E02E0
+
+#define mmMME3_CTRL_TE_CLOSE_CGATE                                   0x1E02E4
+
+#define mmMME3_CTRL_AGU_SM_INFLIGHT_CNTR                             0x1E02E8
+
+#define mmMME3_CTRL_AGU_SM_TOTAL_CNTR                                0x1E02EC
+
+#define mmMME3_CTRL_EZSYNC_OUT_CREDIT                                0x1E02F0
+
+#define mmMME3_CTRL_PCU_RL_SAT_SEC                                   0x1E02F4
+
+#define mmMME3_CTRL_AGU_SYNC_MSG_AXI_USER                            0x1E02F8
+
+#define mmMME3_CTRL_QM_SLV_LBW_CLK_EN                                0x1E02FC
+
+#define mmMME3_CTRL_SHADOW_0_STATUS                                  0x1E0400
+
+#define mmMME3_CTRL_SHADOW_0_BASE_ADDR_HIGH_S                        0x1E0408
+
+#define mmMME3_CTRL_SHADOW_0_BASE_ADDR_HIGH_L                        0x1E040C
+
+#define mmMME3_CTRL_SHADOW_0_BASE_ADDR_HIGH_O                        0x1E0410
+
+#define mmMME3_CTRL_SHADOW_0_BASE_ADDR_LOW_S                         0x1E0414
+
+#define mmMME3_CTRL_SHADOW_0_BASE_ADDR_LOW_L                         0x1E0418
+
+#define mmMME3_CTRL_SHADOW_0_BASE_ADDR_LOW_O                         0x1E041C
+
+#define mmMME3_CTRL_SHADOW_0_HEADER_LOW                              0x1E0420
+
+#define mmMME3_CTRL_SHADOW_0_HEADER_HIGH                             0x1E0424
+
+#define mmMME3_CTRL_SHADOW_0_CONV_KERNEL_SIZE_MINUS_1                0x1E0428
+
+#define mmMME3_CTRL_SHADOW_0_CONV_ASSOCIATED_DIMS_LOW                0x1E042C
+
+#define mmMME3_CTRL_SHADOW_0_CONV_ASSOCIATED_DIMS_HIGH               0x1E0430
+
+#define mmMME3_CTRL_SHADOW_0_NUM_ITERATIONS_MINUS_1                  0x1E0434
+
+#define mmMME3_CTRL_SHADOW_0_OUTER_LOOP                              0x1E0438
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_0               0x1E043C
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_1               0x1E0440
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_2               0x1E0444
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_3               0x1E0448
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_4               0x1E044C
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_0                  0x1E0450
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_1                  0x1E0454
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_2                  0x1E0458
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_3                  0x1E045C
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_4                  0x1E0460
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_0                     0x1E0464
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_1                     0x1E0468
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_2                     0x1E046C
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_3                     0x1E0470
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_0              0x1E0474
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_1              0x1E0478
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_2              0x1E047C
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_3              0x1E0480
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_S_SPATIAL_SIZE_MINUS_1           0x1E0484
+
+#define mmMME3_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_0                 0x1E0488
+
+#define mmMME3_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_1                 0x1E048C
+
+#define mmMME3_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_2                 0x1E0490
+
+#define mmMME3_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_3                 0x1E0494
+
+#define mmMME3_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_4                 0x1E0498
+
+#define mmMME3_CTRL_SHADOW_0_AGU_S_START_OFFSET_0                    0x1E049C
+
+#define mmMME3_CTRL_SHADOW_0_AGU_S_START_OFFSET_1                    0x1E04A0
+
+#define mmMME3_CTRL_SHADOW_0_AGU_S_START_OFFSET_2                    0x1E04A4
+
+#define mmMME3_CTRL_SHADOW_0_AGU_S_START_OFFSET_3                    0x1E04A8
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_0               0x1E04AC
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_1               0x1E04B0
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_2               0x1E04B4
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_3               0x1E04B8
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_4               0x1E04BC
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_0                  0x1E04C0
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_1                  0x1E04C4
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_2                  0x1E04C8
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_3                  0x1E04CC
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_4                  0x1E04D0
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_0                     0x1E04D4
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_1                     0x1E04D8
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_2                     0x1E04DC
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_3                     0x1E04E0
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_0              0x1E04E4
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_1              0x1E04E8
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_2              0x1E04EC
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_3              0x1E04F0
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_L_SPATIAL_SIZE_MINUS_1           0x1E04F4
+
+#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_0           0x1E04F8
+
+#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_1           0x1E04FC
+
+#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_2           0x1E0500
+
+#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_3           0x1E0504
+
+#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_4           0x1E0508
+
+#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_0              0x1E050C
+
+#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_1              0x1E0510
+
+#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_2              0x1E0514
+
+#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_3              0x1E0518
+
+#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_0          0x1E051C
+
+#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_1          0x1E0520
+
+#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_2          0x1E0524
+
+#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_3          0x1E0528
+
+#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_4          0x1E052C
+
+#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_0             0x1E0530
+
+#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_1             0x1E0534
+
+#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_2             0x1E0538
+
+#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_3             0x1E053C
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_0               0x1E0540
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_1               0x1E0544
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_2               0x1E0548
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_3               0x1E054C
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_4               0x1E0550
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_0                  0x1E0554
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_1                  0x1E0558
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_2                  0x1E055C
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_3                  0x1E0560
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_4                  0x1E0564
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_0                     0x1E0568
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_1                     0x1E056C
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_2                     0x1E0570
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_3                     0x1E0574
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_0              0x1E0578
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_1              0x1E057C
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_2              0x1E0580
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_3              0x1E0584
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_O_SPATIAL_SIZE_MINUS_1           0x1E0588
+
+#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_0           0x1E058C
+
+#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_1           0x1E0590
+
+#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_2           0x1E0594
+
+#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_3           0x1E0598
+
+#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_4           0x1E059C
+
+#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_0              0x1E05A0
+
+#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_1              0x1E05A4
+
+#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_2              0x1E05A8
+
+#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_3              0x1E05AC
+
+#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_0          0x1E05B0
+
+#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_1          0x1E05B4
+
+#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_2          0x1E05B8
+
+#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_3          0x1E05BC
+
+#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_4          0x1E05C0
+
+#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_0             0x1E05C4
+
+#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_1             0x1E05C8
+
+#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_2             0x1E05CC
+
+#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_3             0x1E05D0
+
+#define mmMME3_CTRL_SHADOW_0_DESC_SB_REPEAT                          0x1E05D4
+
+#define mmMME3_CTRL_SHADOW_0_DESC_RATE_LIMITER                       0x1E05D8
+
+#define mmMME3_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL         0x1E05DC
+
+#define mmMME3_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE        0x1E05E0
+
+#define mmMME3_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_HIGH              0x1E05E4
+
+#define mmMME3_CTRL_SHADOW_0_DESC_SYNC_OBJECT_DATA                   0x1E05E8
+
+#define mmMME3_CTRL_SHADOW_0_DESC_AXI_USER_DATA                      0x1E05EC
+
+#define mmMME3_CTRL_SHADOW_0_DESC_PERF_EVT_S                         0x1E05F0
+
+#define mmMME3_CTRL_SHADOW_0_DESC_PERF_EVT_L_LOCAL                   0x1E05F4
+
+#define mmMME3_CTRL_SHADOW_0_DESC_PERF_EVT_L_REMOTE                  0x1E05F8
+
+#define mmMME3_CTRL_SHADOW_0_DESC_PERF_EVT_O_LOCAL                   0x1E05FC
+
+#define mmMME3_CTRL_SHADOW_0_DESC_PERF_EVT_O_REMOTE                  0x1E0600
+
+#define mmMME3_CTRL_SHADOW_0_DESC_PADDING_VALUE_S                    0x1E0604
+
+#define mmMME3_CTRL_SHADOW_0_DESC_PADDING_VALUE_L                    0x1E0608
+
+#define mmMME3_CTRL_SHADOW_0_DESC_META_DATA_AGU_S                    0x1E060C
+
+#define mmMME3_CTRL_SHADOW_0_DESC_META_DATA_AGU_L_LOCAL              0x1E0610
+
+#define mmMME3_CTRL_SHADOW_0_DESC_META_DATA_AGU_L_REMOTE             0x1E0614
+
+#define mmMME3_CTRL_SHADOW_0_DESC_META_DATA_AGU_O_LOCAL              0x1E0618
+
+#define mmMME3_CTRL_SHADOW_0_DESC_META_DATA_AGU_O_REMOTE             0x1E061C
+
+#define mmMME3_CTRL_SHADOW_0_DESC_PCU_RL_SATURATION                  0x1E0620
+
+#define mmMME3_CTRL_SHADOW_0_DESC_DUMMY                              0x1E0624
+
+#define mmMME3_CTRL_SHADOW_1_STATUS                                  0x1E0680
+
+#define mmMME3_CTRL_SHADOW_1_BASE_ADDR_HIGH_S                        0x1E0688
+
+#define mmMME3_CTRL_SHADOW_1_BASE_ADDR_HIGH_L                        0x1E068C
+
+#define mmMME3_CTRL_SHADOW_1_BASE_ADDR_HIGH_O                        0x1E0690
+
+#define mmMME3_CTRL_SHADOW_1_BASE_ADDR_LOW_S                         0x1E0694
+
+#define mmMME3_CTRL_SHADOW_1_BASE_ADDR_LOW_L                         0x1E0698
+
+#define mmMME3_CTRL_SHADOW_1_BASE_ADDR_LOW_O                         0x1E069C
+
+#define mmMME3_CTRL_SHADOW_1_HEADER_LOW                              0x1E06A0
+
+#define mmMME3_CTRL_SHADOW_1_HEADER_HIGH                             0x1E06A4
+
+#define mmMME3_CTRL_SHADOW_1_CONV_KERNEL_SIZE_MINUS_1                0x1E06A8
+
+#define mmMME3_CTRL_SHADOW_1_CONV_ASSOCIATED_DIMS_LOW                0x1E06AC
+
+#define mmMME3_CTRL_SHADOW_1_CONV_ASSOCIATED_DIMS_HIGH               0x1E06B0
+
+#define mmMME3_CTRL_SHADOW_1_NUM_ITERATIONS_MINUS_1                  0x1E06B4
+
+#define mmMME3_CTRL_SHADOW_1_OUTER_LOOP                              0x1E06B8
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_0               0x1E06BC
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_1               0x1E06C0
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_2               0x1E06C4
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_3               0x1E06C8
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_4               0x1E06CC
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_0                  0x1E06D0
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_1                  0x1E06D4
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_2                  0x1E06D8
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_3                  0x1E06DC
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_4                  0x1E06E0
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_0                     0x1E06E4
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_1                     0x1E06E8
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_2                     0x1E06EC
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_3                     0x1E06F0
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_0              0x1E06F4
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_1              0x1E06F8
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_2              0x1E06FC
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_3              0x1E0700
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_S_SPATIAL_SIZE_MINUS_1           0x1E0704
+
+#define mmMME3_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_0                 0x1E0708
+
+#define mmMME3_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_1                 0x1E070C
+
+#define mmMME3_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_2                 0x1E0710
+
+#define mmMME3_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_3                 0x1E0714
+
+#define mmMME3_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_4                 0x1E0718
+
+#define mmMME3_CTRL_SHADOW_1_AGU_S_START_OFFSET_0                    0x1E071C
+
+#define mmMME3_CTRL_SHADOW_1_AGU_S_START_OFFSET_1                    0x1E0720
+
+#define mmMME3_CTRL_SHADOW_1_AGU_S_START_OFFSET_2                    0x1E0724
+
+#define mmMME3_CTRL_SHADOW_1_AGU_S_START_OFFSET_3                    0x1E0728
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_0               0x1E072C
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_1               0x1E0730
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_2               0x1E0734
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_3               0x1E0738
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_4               0x1E073C
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_0                  0x1E0740
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_1                  0x1E0744
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_2                  0x1E0748
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_3                  0x1E074C
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_4                  0x1E0750
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_0                     0x1E0754
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_1                     0x1E0758
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_2                     0x1E075C
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_3                     0x1E0760
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_0              0x1E0764
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_1              0x1E0768
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_2              0x1E076C
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_3              0x1E0770
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_L_SPATIAL_SIZE_MINUS_1           0x1E0774
+
+#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_0           0x1E0778
+
+#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_1           0x1E077C
+
+#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_2           0x1E0780
+
+#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_3           0x1E0784
+
+#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_4           0x1E0788
+
+#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_0              0x1E078C
+
+#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_1              0x1E0790
+
+#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_2              0x1E0794
+
+#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_3              0x1E0798
+
+#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_0          0x1E079C
+
+#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_1          0x1E07A0
+
+#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_2          0x1E07A4
+
+#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_3          0x1E07A8
+
+#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_4          0x1E07AC
+
+#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_0             0x1E07B0
+
+#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_1             0x1E07B4
+
+#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_2             0x1E07B8
+
+#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_3             0x1E07BC
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_0               0x1E07C0
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_1               0x1E07C4
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_2               0x1E07C8
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_3               0x1E07CC
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_4               0x1E07D0
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_0                  0x1E07D4
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_1                  0x1E07D8
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_2                  0x1E07DC
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_3                  0x1E07E0
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_4                  0x1E07E4
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_0                     0x1E07E8
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_1                     0x1E07EC
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_2                     0x1E07F0
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_3                     0x1E07F4
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_0              0x1E07F8
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_1              0x1E07FC
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_2              0x1E0800
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_3              0x1E0804
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_O_SPATIAL_SIZE_MINUS_1           0x1E0808
+
+#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_0           0x1E080C
+
+#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_1           0x1E0810
+
+#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_2           0x1E0814
+
+#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_3           0x1E0818
+
+#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_4           0x1E081C
+
+#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_0              0x1E0820
+
+#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_1              0x1E0824
+
+#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_2              0x1E0828
+
+#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_3              0x1E082C
+
+#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_0          0x1E0830
+
+#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_1          0x1E0834
+
+#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_2          0x1E0838
+
+#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_3          0x1E083C
+
+#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_4          0x1E0840
+
+#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_0             0x1E0844
+
+#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_1             0x1E0848
+
+#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_2             0x1E084C
+
+#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_3             0x1E0850
+
+#define mmMME3_CTRL_SHADOW_1_DESC_SB_REPEAT                          0x1E0854
+
+#define mmMME3_CTRL_SHADOW_1_DESC_RATE_LIMITER                       0x1E0858
+
+#define mmMME3_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL         0x1E085C
+
+#define mmMME3_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE        0x1E0860
+
+#define mmMME3_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_HIGH              0x1E0864
+
+#define mmMME3_CTRL_SHADOW_1_DESC_SYNC_OBJECT_DATA                   0x1E0868
+
+#define mmMME3_CTRL_SHADOW_1_DESC_AXI_USER_DATA                      0x1E086C
+
+#define mmMME3_CTRL_SHADOW_1_DESC_PERF_EVT_S                         0x1E0870
+
+#define mmMME3_CTRL_SHADOW_1_DESC_PERF_EVT_L_LOCAL                   0x1E0874
+
+#define mmMME3_CTRL_SHADOW_1_DESC_PERF_EVT_L_REMOTE                  0x1E0878
+
+#define mmMME3_CTRL_SHADOW_1_DESC_PERF_EVT_O_LOCAL                   0x1E087C
+
+#define mmMME3_CTRL_SHADOW_1_DESC_PERF_EVT_O_REMOTE                  0x1E0880
+
+#define mmMME3_CTRL_SHADOW_1_DESC_PADDING_VALUE_S                    0x1E0884
+
+#define mmMME3_CTRL_SHADOW_1_DESC_PADDING_VALUE_L                    0x1E0888
+
+#define mmMME3_CTRL_SHADOW_1_DESC_META_DATA_AGU_S                    0x1E088C
+
+#define mmMME3_CTRL_SHADOW_1_DESC_META_DATA_AGU_L_LOCAL              0x1E0890
+
+#define mmMME3_CTRL_SHADOW_1_DESC_META_DATA_AGU_L_REMOTE             0x1E0894
+
+#define mmMME3_CTRL_SHADOW_1_DESC_META_DATA_AGU_O_LOCAL              0x1E0898
+
+#define mmMME3_CTRL_SHADOW_1_DESC_META_DATA_AGU_O_REMOTE             0x1E089C
+
+#define mmMME3_CTRL_SHADOW_1_DESC_PCU_RL_SATURATION                  0x1E08A0
+
+#define mmMME3_CTRL_SHADOW_1_DESC_DUMMY                              0x1E08A4
+
+#define mmMME3_CTRL_SHADOW_2_STATUS                                  0x1E0900
+
+#define mmMME3_CTRL_SHADOW_2_BASE_ADDR_HIGH_S                        0x1E0908
+
+#define mmMME3_CTRL_SHADOW_2_BASE_ADDR_HIGH_L                        0x1E090C
+
+#define mmMME3_CTRL_SHADOW_2_BASE_ADDR_HIGH_O                        0x1E0910
+
+#define mmMME3_CTRL_SHADOW_2_BASE_ADDR_LOW_S                         0x1E0914
+
+#define mmMME3_CTRL_SHADOW_2_BASE_ADDR_LOW_L                         0x1E0918
+
+#define mmMME3_CTRL_SHADOW_2_BASE_ADDR_LOW_O                         0x1E091C
+
+#define mmMME3_CTRL_SHADOW_2_HEADER_LOW                              0x1E0920
+
+#define mmMME3_CTRL_SHADOW_2_HEADER_HIGH                             0x1E0924
+
+#define mmMME3_CTRL_SHADOW_2_CONV_KERNEL_SIZE_MINUS_1                0x1E0928
+
+#define mmMME3_CTRL_SHADOW_2_CONV_ASSOCIATED_DIMS_LOW                0x1E092C
+
+#define mmMME3_CTRL_SHADOW_2_CONV_ASSOCIATED_DIMS_HIGH               0x1E0930
+
+#define mmMME3_CTRL_SHADOW_2_NUM_ITERATIONS_MINUS_1                  0x1E0934
+
+#define mmMME3_CTRL_SHADOW_2_OUTER_LOOP                              0x1E0938
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_0               0x1E093C
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_1               0x1E0940
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_2               0x1E0944
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_3               0x1E0948
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_4               0x1E094C
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_0                  0x1E0950
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_1                  0x1E0954
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_2                  0x1E0958
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_3                  0x1E095C
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_4                  0x1E0960
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_0                     0x1E0964
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_1                     0x1E0968
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_2                     0x1E096C
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_3                     0x1E0970
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_0              0x1E0974
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_1              0x1E0978
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_2              0x1E097C
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_3              0x1E0980
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_S_SPATIAL_SIZE_MINUS_1           0x1E0984
+
+#define mmMME3_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_0                 0x1E0988
+
+#define mmMME3_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_1                 0x1E098C
+
+#define mmMME3_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_2                 0x1E0990
+
+#define mmMME3_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_3                 0x1E0994
+
+#define mmMME3_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_4                 0x1E0998
+
+#define mmMME3_CTRL_SHADOW_2_AGU_S_START_OFFSET_0                    0x1E099C
+
+#define mmMME3_CTRL_SHADOW_2_AGU_S_START_OFFSET_1                    0x1E09A0
+
+#define mmMME3_CTRL_SHADOW_2_AGU_S_START_OFFSET_2                    0x1E09A4
+
+#define mmMME3_CTRL_SHADOW_2_AGU_S_START_OFFSET_3                    0x1E09A8
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_0               0x1E09AC
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_1               0x1E09B0
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_2               0x1E09B4
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_3               0x1E09B8
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_4               0x1E09BC
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_0                  0x1E09C0
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_1                  0x1E09C4
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_2                  0x1E09C8
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_3                  0x1E09CC
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_4                  0x1E09D0
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_0                     0x1E09D4
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_1                     0x1E09D8
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_2                     0x1E09DC
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_3                     0x1E09E0
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_0              0x1E09E4
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_1              0x1E09E8
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_2              0x1E09EC
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_3              0x1E09F0
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_L_SPATIAL_SIZE_MINUS_1           0x1E09F4
+
+#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_0           0x1E09F8
+
+#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_1           0x1E09FC
+
+#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_2           0x1E0A00
+
+#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_3           0x1E0A04
+
+#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_4           0x1E0A08
+
+#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_0              0x1E0A0C
+
+#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_1              0x1E0A10
+
+#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_2              0x1E0A14
+
+#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_3              0x1E0A18
+
+#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_0          0x1E0A1C
+
+#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_1          0x1E0A20
+
+#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_2          0x1E0A24
+
+#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_3          0x1E0A28
+
+#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_4          0x1E0A2C
+
+#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_0             0x1E0A30
+
+#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_1             0x1E0A34
+
+#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_2             0x1E0A38
+
+#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_3             0x1E0A3C
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_0               0x1E0A40
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_1               0x1E0A44
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_2               0x1E0A48
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_3               0x1E0A4C
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_4               0x1E0A50
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_0                  0x1E0A54
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_1                  0x1E0A58
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_2                  0x1E0A5C
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_3                  0x1E0A60
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_4                  0x1E0A64
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_0                     0x1E0A68
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_1                     0x1E0A6C
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_2                     0x1E0A70
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_3                     0x1E0A74
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_0              0x1E0A78
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_1              0x1E0A7C
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_2              0x1E0A80
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_3              0x1E0A84
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_O_SPATIAL_SIZE_MINUS_1           0x1E0A88
+
+#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_0           0x1E0A8C
+
+#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_1           0x1E0A90
+
+#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_2           0x1E0A94
+
+#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_3           0x1E0A98
+
+#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_4           0x1E0A9C
+
+#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_0              0x1E0AA0
+
+#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_1              0x1E0AA4
+
+#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_2              0x1E0AA8
+
+#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_3              0x1E0AAC
+
+#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_0          0x1E0AB0
+
+#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_1          0x1E0AB4
+
+#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_2          0x1E0AB8
+
+#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_3          0x1E0ABC
+
+#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_4          0x1E0AC0
+
+#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_0             0x1E0AC4
+
+#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_1             0x1E0AC8
+
+#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_2             0x1E0ACC
+
+#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_3             0x1E0AD0
+
+#define mmMME3_CTRL_SHADOW_2_DESC_SB_REPEAT                          0x1E0AD4
+
+#define mmMME3_CTRL_SHADOW_2_DESC_RATE_LIMITER                       0x1E0AD8
+
+#define mmMME3_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL         0x1E0ADC
+
+#define mmMME3_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE        0x1E0AE0
+
+#define mmMME3_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_HIGH              0x1E0AE4
+
+#define mmMME3_CTRL_SHADOW_2_DESC_SYNC_OBJECT_DATA                   0x1E0AE8
+
+#define mmMME3_CTRL_SHADOW_2_DESC_AXI_USER_DATA                      0x1E0AEC
+
+#define mmMME3_CTRL_SHADOW_2_DESC_PERF_EVT_S                         0x1E0AF0
+
+#define mmMME3_CTRL_SHADOW_2_DESC_PERF_EVT_L_LOCAL                   0x1E0AF4
+
+#define mmMME3_CTRL_SHADOW_2_DESC_PERF_EVT_L_REMOTE                  0x1E0AF8
+
+#define mmMME3_CTRL_SHADOW_2_DESC_PERF_EVT_O_LOCAL                   0x1E0AFC
+
+#define mmMME3_CTRL_SHADOW_2_DESC_PERF_EVT_O_REMOTE                  0x1E0B00
+
+#define mmMME3_CTRL_SHADOW_2_DESC_PADDING_VALUE_S                    0x1E0B04
+
+#define mmMME3_CTRL_SHADOW_2_DESC_PADDING_VALUE_L                    0x1E0B08
+
+#define mmMME3_CTRL_SHADOW_2_DESC_META_DATA_AGU_S                    0x1E0B0C
+
+#define mmMME3_CTRL_SHADOW_2_DESC_META_DATA_AGU_L_LOCAL              0x1E0B10
+
+#define mmMME3_CTRL_SHADOW_2_DESC_META_DATA_AGU_L_REMOTE             0x1E0B14
+
+#define mmMME3_CTRL_SHADOW_2_DESC_META_DATA_AGU_O_LOCAL              0x1E0B18
+
+#define mmMME3_CTRL_SHADOW_2_DESC_META_DATA_AGU_O_REMOTE             0x1E0B1C
+
+#define mmMME3_CTRL_SHADOW_2_DESC_PCU_RL_SATURATION                  0x1E0B20
+
+#define mmMME3_CTRL_SHADOW_2_DESC_DUMMY                              0x1E0B24
+
+#define mmMME3_CTRL_SHADOW_3_STATUS                                  0x1E0B80
+
+#define mmMME3_CTRL_SHADOW_3_BASE_ADDR_HIGH_S                        0x1E0B88
+
+#define mmMME3_CTRL_SHADOW_3_BASE_ADDR_HIGH_L                        0x1E0B8C
+
+#define mmMME3_CTRL_SHADOW_3_BASE_ADDR_HIGH_O                        0x1E0B90
+
+#define mmMME3_CTRL_SHADOW_3_BASE_ADDR_LOW_S                         0x1E0B94
+
+#define mmMME3_CTRL_SHADOW_3_BASE_ADDR_LOW_L                         0x1E0B98
+
+#define mmMME3_CTRL_SHADOW_3_BASE_ADDR_LOW_O                         0x1E0B9C
+
+#define mmMME3_CTRL_SHADOW_3_HEADER_LOW                              0x1E0BA0
+
+#define mmMME3_CTRL_SHADOW_3_HEADER_HIGH                             0x1E0BA4
+
+#define mmMME3_CTRL_SHADOW_3_CONV_KERNEL_SIZE_MINUS_1                0x1E0BA8
+
+#define mmMME3_CTRL_SHADOW_3_CONV_ASSOCIATED_DIMS_LOW                0x1E0BAC
+
+#define mmMME3_CTRL_SHADOW_3_CONV_ASSOCIATED_DIMS_HIGH               0x1E0BB0
+
+#define mmMME3_CTRL_SHADOW_3_NUM_ITERATIONS_MINUS_1                  0x1E0BB4
+
+#define mmMME3_CTRL_SHADOW_3_OUTER_LOOP                              0x1E0BB8
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_0               0x1E0BBC
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_1               0x1E0BC0
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_2               0x1E0BC4
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_3               0x1E0BC8
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_4               0x1E0BCC
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_0                  0x1E0BD0
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_1                  0x1E0BD4
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_2                  0x1E0BD8
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_3                  0x1E0BDC
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_4                  0x1E0BE0
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_0                     0x1E0BE4
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_1                     0x1E0BE8
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_2                     0x1E0BEC
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_3                     0x1E0BF0
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_0              0x1E0BF4
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_1              0x1E0BF8
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_2              0x1E0BFC
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_3              0x1E0C00
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_S_SPATIAL_SIZE_MINUS_1           0x1E0C04
+
+#define mmMME3_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_0                 0x1E0C08
+
+#define mmMME3_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_1                 0x1E0C0C
+
+#define mmMME3_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_2                 0x1E0C10
+
+#define mmMME3_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_3                 0x1E0C14
+
+#define mmMME3_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_4                 0x1E0C18
+
+#define mmMME3_CTRL_SHADOW_3_AGU_S_START_OFFSET_0                    0x1E0C1C
+
+#define mmMME3_CTRL_SHADOW_3_AGU_S_START_OFFSET_1                    0x1E0C20
+
+#define mmMME3_CTRL_SHADOW_3_AGU_S_START_OFFSET_2                    0x1E0C24
+
+#define mmMME3_CTRL_SHADOW_3_AGU_S_START_OFFSET_3                    0x1E0C28
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_0               0x1E0C2C
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_1               0x1E0C30
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_2               0x1E0C34
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_3               0x1E0C38
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_4               0x1E0C3C
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_0                  0x1E0C40
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_1                  0x1E0C44
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_2                  0x1E0C48
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_3                  0x1E0C4C
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_4                  0x1E0C50
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_0                     0x1E0C54
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_1                     0x1E0C58
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_2                     0x1E0C5C
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_3                     0x1E0C60
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_0              0x1E0C64
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_1              0x1E0C68
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_2              0x1E0C6C
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_3              0x1E0C70
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_L_SPATIAL_SIZE_MINUS_1           0x1E0C74
+
+#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_0           0x1E0C78
+
+#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_1           0x1E0C7C
+
+#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_2           0x1E0C80
+
+#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_3           0x1E0C84
+
+#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_4           0x1E0C88
+
+#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_0              0x1E0C8C
+
+#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_1              0x1E0C90
+
+#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_2              0x1E0C94
+
+#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_3              0x1E0C98
+
+#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_0          0x1E0C9C
+
+#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_1          0x1E0CA0
+
+#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_2          0x1E0CA4
+
+#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_3          0x1E0CA8
+
+#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_4          0x1E0CAC
+
+#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_0             0x1E0CB0
+
+#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_1             0x1E0CB4
+
+#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_2             0x1E0CB8
+
+#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_3             0x1E0CBC
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_0               0x1E0CC0
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_1               0x1E0CC4
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_2               0x1E0CC8
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_3               0x1E0CCC
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_4               0x1E0CD0
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_0                  0x1E0CD4
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_1                  0x1E0CD8
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_2                  0x1E0CDC
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_3                  0x1E0CE0
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_4                  0x1E0CE4
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_0                     0x1E0CE8
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_1                     0x1E0CEC
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_2                     0x1E0CF0
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_3                     0x1E0CF4
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_0              0x1E0CF8
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_1              0x1E0CFC
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_2              0x1E0D00
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_3              0x1E0D04
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_O_SPATIAL_SIZE_MINUS_1           0x1E0D08
+
+#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_0           0x1E0D0C
+
+#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_1           0x1E0D10
+
+#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_2           0x1E0D14
+
+#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_3           0x1E0D18
+
+#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_4           0x1E0D1C
+
+#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_0              0x1E0D20
+
+#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_1              0x1E0D24
+
+#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_2              0x1E0D28
+
+#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_3              0x1E0D2C
+
+#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_0          0x1E0D30
+
+#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_1          0x1E0D34
+
+#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_2          0x1E0D38
+
+#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_3          0x1E0D3C
+
+#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_4          0x1E0D40
+
+#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_0             0x1E0D44
+
+#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_1             0x1E0D48
+
+#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_2             0x1E0D4C
+
+#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_3             0x1E0D50
+
+#define mmMME3_CTRL_SHADOW_3_DESC_SB_REPEAT                          0x1E0D54
+
+#define mmMME3_CTRL_SHADOW_3_DESC_RATE_LIMITER                       0x1E0D58
+
+#define mmMME3_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL         0x1E0D5C
+
+#define mmMME3_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE        0x1E0D60
+
+#define mmMME3_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_HIGH              0x1E0D64
+
+#define mmMME3_CTRL_SHADOW_3_DESC_SYNC_OBJECT_DATA                   0x1E0D68
+
+#define mmMME3_CTRL_SHADOW_3_DESC_AXI_USER_DATA                      0x1E0D6C
+
+#define mmMME3_CTRL_SHADOW_3_DESC_PERF_EVT_S                         0x1E0D70
+
+#define mmMME3_CTRL_SHADOW_3_DESC_PERF_EVT_L_LOCAL                   0x1E0D74
+
+#define mmMME3_CTRL_SHADOW_3_DESC_PERF_EVT_L_REMOTE                  0x1E0D78
+
+#define mmMME3_CTRL_SHADOW_3_DESC_PERF_EVT_O_LOCAL                   0x1E0D7C
+
+#define mmMME3_CTRL_SHADOW_3_DESC_PERF_EVT_O_REMOTE                  0x1E0D80
+
+#define mmMME3_CTRL_SHADOW_3_DESC_PADDING_VALUE_S                    0x1E0D84
+
+#define mmMME3_CTRL_SHADOW_3_DESC_PADDING_VALUE_L                    0x1E0D88
+
+#define mmMME3_CTRL_SHADOW_3_DESC_META_DATA_AGU_S                    0x1E0D8C
+
+#define mmMME3_CTRL_SHADOW_3_DESC_META_DATA_AGU_L_LOCAL              0x1E0D90
+
+#define mmMME3_CTRL_SHADOW_3_DESC_META_DATA_AGU_L_REMOTE             0x1E0D94
+
+#define mmMME3_CTRL_SHADOW_3_DESC_META_DATA_AGU_O_LOCAL              0x1E0D98
+
+#define mmMME3_CTRL_SHADOW_3_DESC_META_DATA_AGU_O_REMOTE             0x1E0D9C
+
+#define mmMME3_CTRL_SHADOW_3_DESC_PCU_RL_SATURATION                  0x1E0DA0
+
+#define mmMME3_CTRL_SHADOW_3_DESC_DUMMY                              0x1E0DA4
+
+#endif /* ASIC_REG_MME3_CTRL_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/mmu_up_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/mmu_up_regs.h
new file mode 100644
index 000000000000..61465b599850
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/mmu_up_regs.h
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_MMU_UP_REGS_H_
+#define ASIC_REG_MMU_UP_REGS_H_
+
+/*
+ *****************************************
+ *   MMU_UP (Prototype: MMU)
+ *****************************************
+ */
+
+#define mmMMU_UP_MMU_ENABLE                                          0xC1100C
+
+#define mmMMU_UP_FORCE_ORDERING                                      0xC11010
+
+#define mmMMU_UP_FEATURE_ENABLE                                      0xC11014
+
+#define mmMMU_UP_VA_ORDERING_MASK_31_7                               0xC11018
+
+#define mmMMU_UP_VA_ORDERING_MASK_49_32                              0xC1101C
+
+#define mmMMU_UP_LOG2_DDR_SIZE                                       0xC11020
+
+#define mmMMU_UP_SCRAMBLER                                           0xC11024
+
+#define mmMMU_UP_MEM_INIT_BUSY                                       0xC11028
+
+#define mmMMU_UP_SPI_MASK                                            0xC1102C
+
+#define mmMMU_UP_SPI_CAUSE                                           0xC11030
+
+#define mmMMU_UP_PAGE_ERROR_CAPTURE                                  0xC11034
+
+#define mmMMU_UP_PAGE_ERROR_CAPTURE_VA                               0xC11038
+
+#define mmMMU_UP_ACCESS_ERROR_CAPTURE                                0xC1103C
+
+#define mmMMU_UP_ACCESS_ERROR_CAPTURE_VA                             0xC11040
+
+#define mmMMU_UP_SPI_INTERRUPT_CLR                                   0xC11044
+
+#define mmMMU_UP_SPI_INTERRUPT_MASK                                  0xC11048
+
+#define mmMMU_UP_DBG_MEM_WRAP_RM                                     0xC1104C
+
+#define mmMMU_UP_SPI_CAUSE_CLR                                       0xC11050
+
+#define mmMMU_UP_SLICE_CREDIT                                        0xC11054
+
+#define mmMMU_UP_PIPE_CREDIT                                         0xC11058
+
+#define mmMMU_UP_RAZWI_WRITE_VLD                                     0xC1105C
+
+#define mmMMU_UP_RAZWI_WRITE_ID                                      0xC11060
+
+#define mmMMU_UP_RAZWI_READ_VLD                                      0xC11064
+
+#define mmMMU_UP_RAZWI_READ_ID                                       0xC11068
+
+#define mmMMU_UP_MMU_BYPASS                                          0xC1106C
+
+#endif /* ASIC_REG_MMU_UP_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/nic0_qm0_masks.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic0_qm0_masks.h
new file mode 100644
index 000000000000..bd37b6452133
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic0_qm0_masks.h
@@ -0,0 +1,800 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_QM0_MASKS_H_
+#define ASIC_REG_NIC0_QM0_MASKS_H_
+
+/*
+ *****************************************
+ *   NIC0_QM0 (Prototype: QMAN)
+ *****************************************
+ */
+
+/* NIC0_QM0_GLBL_CFG0 */
+#define NIC0_QM0_GLBL_CFG0_PQF_EN_SHIFT                              0
+#define NIC0_QM0_GLBL_CFG0_PQF_EN_MASK                               0xF
+#define NIC0_QM0_GLBL_CFG0_CQF_EN_SHIFT                              4
+#define NIC0_QM0_GLBL_CFG0_CQF_EN_MASK                               0x1F0
+#define NIC0_QM0_GLBL_CFG0_CP_EN_SHIFT                               9
+#define NIC0_QM0_GLBL_CFG0_CP_EN_MASK                                0x3E00
+
+/* NIC0_QM0_GLBL_CFG1 */
+#define NIC0_QM0_GLBL_CFG1_PQF_STOP_SHIFT                            0
+#define NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK                             0xF
+#define NIC0_QM0_GLBL_CFG1_CQF_STOP_SHIFT                            4
+#define NIC0_QM0_GLBL_CFG1_CQF_STOP_MASK                             0x1F0
+#define NIC0_QM0_GLBL_CFG1_CP_STOP_SHIFT                             9
+#define NIC0_QM0_GLBL_CFG1_CP_STOP_MASK                              0x3E00
+#define NIC0_QM0_GLBL_CFG1_PQF_FLUSH_SHIFT                           16
+#define NIC0_QM0_GLBL_CFG1_PQF_FLUSH_MASK                            0xF0000
+#define NIC0_QM0_GLBL_CFG1_CQF_FLUSH_SHIFT                           20
+#define NIC0_QM0_GLBL_CFG1_CQF_FLUSH_MASK                            0x1F00000
+#define NIC0_QM0_GLBL_CFG1_CP_FLUSH_SHIFT                            25
+#define NIC0_QM0_GLBL_CFG1_CP_FLUSH_MASK                             0x3E000000
+
+/* NIC0_QM0_GLBL_PROT */
+#define NIC0_QM0_GLBL_PROT_PQF_SHIFT                                 0
+#define NIC0_QM0_GLBL_PROT_PQF_MASK                                  0xF
+#define NIC0_QM0_GLBL_PROT_CQF_SHIFT                                 4
+#define NIC0_QM0_GLBL_PROT_CQF_MASK                                  0x1F0
+#define NIC0_QM0_GLBL_PROT_CP_SHIFT                                  9
+#define NIC0_QM0_GLBL_PROT_CP_MASK                                   0x3E00
+#define NIC0_QM0_GLBL_PROT_ERR_SHIFT                                 14
+#define NIC0_QM0_GLBL_PROT_ERR_MASK                                  0x4000
+#define NIC0_QM0_GLBL_PROT_ARB_SHIFT                                 15
+#define NIC0_QM0_GLBL_PROT_ARB_MASK                                  0x8000
+
+/* NIC0_QM0_GLBL_ERR_CFG */
+#define NIC0_QM0_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT                   0
+#define NIC0_QM0_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK                    0xF
+#define NIC0_QM0_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT                   4
+#define NIC0_QM0_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK                    0x1F0
+#define NIC0_QM0_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT                    9
+#define NIC0_QM0_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK                     0x3E00
+#define NIC0_QM0_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT                  16
+#define NIC0_QM0_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK                   0xF0000
+#define NIC0_QM0_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT                  20
+#define NIC0_QM0_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK                   0x1F00000
+#define NIC0_QM0_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT                   25
+#define NIC0_QM0_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK                    0x3E000000
+#define NIC0_QM0_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT                  31
+#define NIC0_QM0_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK                   0x80000000
+
+/* NIC0_QM0_GLBL_SECURE_PROPS */
+#define NIC0_QM0_GLBL_SECURE_PROPS_0_ASID_SHIFT                      0
+#define NIC0_QM0_GLBL_SECURE_PROPS_0_ASID_MASK                       0x3FF
+#define NIC0_QM0_GLBL_SECURE_PROPS_1_ASID_SHIFT                      0
+#define NIC0_QM0_GLBL_SECURE_PROPS_1_ASID_MASK                       0x3FF
+#define NIC0_QM0_GLBL_SECURE_PROPS_2_ASID_SHIFT                      0
+#define NIC0_QM0_GLBL_SECURE_PROPS_2_ASID_MASK                       0x3FF
+#define NIC0_QM0_GLBL_SECURE_PROPS_3_ASID_SHIFT                      0
+#define NIC0_QM0_GLBL_SECURE_PROPS_3_ASID_MASK                       0x3FF
+#define NIC0_QM0_GLBL_SECURE_PROPS_4_ASID_SHIFT                      0
+#define NIC0_QM0_GLBL_SECURE_PROPS_4_ASID_MASK                       0x3FF
+#define NIC0_QM0_GLBL_SECURE_PROPS_0_MMBP_SHIFT                      10
+#define NIC0_QM0_GLBL_SECURE_PROPS_0_MMBP_MASK                       0x400
+#define NIC0_QM0_GLBL_SECURE_PROPS_1_MMBP_SHIFT                      10
+#define NIC0_QM0_GLBL_SECURE_PROPS_1_MMBP_MASK                       0x400
+#define NIC0_QM0_GLBL_SECURE_PROPS_2_MMBP_SHIFT                      10
+#define NIC0_QM0_GLBL_SECURE_PROPS_2_MMBP_MASK                       0x400
+#define NIC0_QM0_GLBL_SECURE_PROPS_3_MMBP_SHIFT                      10
+#define NIC0_QM0_GLBL_SECURE_PROPS_3_MMBP_MASK                       0x400
+#define NIC0_QM0_GLBL_SECURE_PROPS_4_MMBP_SHIFT                      10
+#define NIC0_QM0_GLBL_SECURE_PROPS_4_MMBP_MASK                       0x400
+
+/* NIC0_QM0_GLBL_NON_SECURE_PROPS */
+#define NIC0_QM0_GLBL_NON_SECURE_PROPS_0_ASID_SHIFT                  0
+#define NIC0_QM0_GLBL_NON_SECURE_PROPS_0_ASID_MASK                   0x3FF
+#define NIC0_QM0_GLBL_NON_SECURE_PROPS_1_ASID_SHIFT                  0
+#define NIC0_QM0_GLBL_NON_SECURE_PROPS_1_ASID_MASK                   0x3FF
+#define NIC0_QM0_GLBL_NON_SECURE_PROPS_2_ASID_SHIFT                  0
+#define NIC0_QM0_GLBL_NON_SECURE_PROPS_2_ASID_MASK                   0x3FF
+#define NIC0_QM0_GLBL_NON_SECURE_PROPS_3_ASID_SHIFT                  0
+#define NIC0_QM0_GLBL_NON_SECURE_PROPS_3_ASID_MASK                   0x3FF
+#define NIC0_QM0_GLBL_NON_SECURE_PROPS_4_ASID_SHIFT                  0
+#define NIC0_QM0_GLBL_NON_SECURE_PROPS_4_ASID_MASK                   0x3FF
+#define NIC0_QM0_GLBL_NON_SECURE_PROPS_0_MMBP_SHIFT                  10
+#define NIC0_QM0_GLBL_NON_SECURE_PROPS_0_MMBP_MASK                   0x400
+#define NIC0_QM0_GLBL_NON_SECURE_PROPS_1_MMBP_SHIFT                  10
+#define NIC0_QM0_GLBL_NON_SECURE_PROPS_1_MMBP_MASK                   0x400
+#define NIC0_QM0_GLBL_NON_SECURE_PROPS_2_MMBP_SHIFT                  10
+#define NIC0_QM0_GLBL_NON_SECURE_PROPS_2_MMBP_MASK                   0x400
+#define NIC0_QM0_GLBL_NON_SECURE_PROPS_3_MMBP_SHIFT                  10
+#define NIC0_QM0_GLBL_NON_SECURE_PROPS_3_MMBP_MASK                   0x400
+#define NIC0_QM0_GLBL_NON_SECURE_PROPS_4_MMBP_SHIFT                  10
+#define NIC0_QM0_GLBL_NON_SECURE_PROPS_4_MMBP_MASK                   0x400
+
+/* NIC0_QM0_GLBL_STS0 */
+#define NIC0_QM0_GLBL_STS0_PQF_IDLE_SHIFT                            0
+#define NIC0_QM0_GLBL_STS0_PQF_IDLE_MASK                             0xF
+#define NIC0_QM0_GLBL_STS0_CQF_IDLE_SHIFT                            4
+#define NIC0_QM0_GLBL_STS0_CQF_IDLE_MASK                             0x1F0
+#define NIC0_QM0_GLBL_STS0_CP_IDLE_SHIFT                             9
+#define NIC0_QM0_GLBL_STS0_CP_IDLE_MASK                              0x3E00
+#define NIC0_QM0_GLBL_STS0_PQF_IS_STOP_SHIFT                         16
+#define NIC0_QM0_GLBL_STS0_PQF_IS_STOP_MASK                          0xF0000
+#define NIC0_QM0_GLBL_STS0_CQF_IS_STOP_SHIFT                         20
+#define NIC0_QM0_GLBL_STS0_CQF_IS_STOP_MASK                          0x1F00000
+#define NIC0_QM0_GLBL_STS0_CP_IS_STOP_SHIFT                          25
+#define NIC0_QM0_GLBL_STS0_CP_IS_STOP_MASK                           0x3E000000
+#define NIC0_QM0_GLBL_STS0_ARB_IS_STOP_SHIFT                         31
+#define NIC0_QM0_GLBL_STS0_ARB_IS_STOP_MASK                          0x80000000
+
+/* NIC0_QM0_GLBL_STS1 */
+#define NIC0_QM0_GLBL_STS1_PQF_RD_ERR_SHIFT                          0
+#define NIC0_QM0_GLBL_STS1_PQF_RD_ERR_MASK                           0x1
+#define NIC0_QM0_GLBL_STS1_CQF_RD_ERR_SHIFT                          1
+#define NIC0_QM0_GLBL_STS1_CQF_RD_ERR_MASK                           0x2
+#define NIC0_QM0_GLBL_STS1_CP_RD_ERR_SHIFT                           2
+#define NIC0_QM0_GLBL_STS1_CP_RD_ERR_MASK                            0x4
+#define NIC0_QM0_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT                    3
+#define NIC0_QM0_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK                     0x8
+#define NIC0_QM0_GLBL_STS1_CP_STOP_OP_SHIFT                          4
+#define NIC0_QM0_GLBL_STS1_CP_STOP_OP_MASK                           0x10
+#define NIC0_QM0_GLBL_STS1_CP_MSG_WR_ERR_SHIFT                       5
+#define NIC0_QM0_GLBL_STS1_CP_MSG_WR_ERR_MASK                        0x20
+#define NIC0_QM0_GLBL_STS1_CP_WREG_ERR_SHIFT                         6
+#define NIC0_QM0_GLBL_STS1_CP_WREG_ERR_MASK                          0x40
+#define NIC0_QM0_GLBL_STS1_CP_FENCE0_OVF_ERR_SHIFT                   8
+#define NIC0_QM0_GLBL_STS1_CP_FENCE0_OVF_ERR_MASK                    0x100
+#define NIC0_QM0_GLBL_STS1_CP_FENCE1_OVF_ERR_SHIFT                   9
+#define NIC0_QM0_GLBL_STS1_CP_FENCE1_OVF_ERR_MASK                    0x200
+#define NIC0_QM0_GLBL_STS1_CP_FENCE2_OVF_ERR_SHIFT                   10
+#define NIC0_QM0_GLBL_STS1_CP_FENCE2_OVF_ERR_MASK                    0x400
+#define NIC0_QM0_GLBL_STS1_CP_FENCE3_OVF_ERR_SHIFT                   11
+#define NIC0_QM0_GLBL_STS1_CP_FENCE3_OVF_ERR_MASK                    0x800
+#define NIC0_QM0_GLBL_STS1_CP_FENCE0_UDF_ERR_SHIFT                   12
+#define NIC0_QM0_GLBL_STS1_CP_FENCE0_UDF_ERR_MASK                    0x1000
+#define NIC0_QM0_GLBL_STS1_CP_FENCE1_UDF_ERR_SHIFT                   13
+#define NIC0_QM0_GLBL_STS1_CP_FENCE1_UDF_ERR_MASK                    0x2000
+#define NIC0_QM0_GLBL_STS1_CP_FENCE2_UDF_ERR_SHIFT                   14
+#define NIC0_QM0_GLBL_STS1_CP_FENCE2_UDF_ERR_MASK                    0x4000
+#define NIC0_QM0_GLBL_STS1_CP_FENCE3_UDF_ERR_SHIFT                   15
+#define NIC0_QM0_GLBL_STS1_CP_FENCE3_UDF_ERR_MASK                    0x8000
+
+/* NIC0_QM0_GLBL_STS1_4 */
+#define NIC0_QM0_GLBL_STS1_4_CQF_RD_ERR_SHIFT                        1
+#define NIC0_QM0_GLBL_STS1_4_CQF_RD_ERR_MASK                         0x2
+#define NIC0_QM0_GLBL_STS1_4_CP_RD_ERR_SHIFT                         2
+#define NIC0_QM0_GLBL_STS1_4_CP_RD_ERR_MASK                          0x4
+#define NIC0_QM0_GLBL_STS1_4_CP_UNDEF_CMD_ERR_SHIFT                  3
+#define NIC0_QM0_GLBL_STS1_4_CP_UNDEF_CMD_ERR_MASK                   0x8
+#define NIC0_QM0_GLBL_STS1_4_CP_STOP_OP_SHIFT                        4
+#define NIC0_QM0_GLBL_STS1_4_CP_STOP_OP_MASK                         0x10
+#define NIC0_QM0_GLBL_STS1_4_CP_MSG_WR_ERR_SHIFT                     5
+#define NIC0_QM0_GLBL_STS1_4_CP_MSG_WR_ERR_MASK                      0x20
+#define NIC0_QM0_GLBL_STS1_4_CP_WREG_ERR_SHIFT                       6
+#define NIC0_QM0_GLBL_STS1_4_CP_WREG_ERR_MASK                        0x40
+#define NIC0_QM0_GLBL_STS1_4_CP_FENCE0_OVF_ERR_SHIFT                 8
+#define NIC0_QM0_GLBL_STS1_4_CP_FENCE0_OVF_ERR_MASK                  0x100
+#define NIC0_QM0_GLBL_STS1_4_CP_FENCE1_OVF_ERR_SHIFT                 9
+#define NIC0_QM0_GLBL_STS1_4_CP_FENCE1_OVF_ERR_MASK                  0x200
+#define NIC0_QM0_GLBL_STS1_4_CP_FENCE2_OVF_ERR_SHIFT                 10
+#define NIC0_QM0_GLBL_STS1_4_CP_FENCE2_OVF_ERR_MASK                  0x400
+#define NIC0_QM0_GLBL_STS1_4_CP_FENCE3_OVF_ERR_SHIFT                 11
+#define NIC0_QM0_GLBL_STS1_4_CP_FENCE3_OVF_ERR_MASK                  0x800
+#define NIC0_QM0_GLBL_STS1_4_CP_FENCE0_UDF_ERR_SHIFT                 12
+#define NIC0_QM0_GLBL_STS1_4_CP_FENCE0_UDF_ERR_MASK                  0x1000
+#define NIC0_QM0_GLBL_STS1_4_CP_FENCE1_UDF_ERR_SHIFT                 13
+#define NIC0_QM0_GLBL_STS1_4_CP_FENCE1_UDF_ERR_MASK                  0x2000
+#define NIC0_QM0_GLBL_STS1_4_CP_FENCE2_UDF_ERR_SHIFT                 14
+#define NIC0_QM0_GLBL_STS1_4_CP_FENCE2_UDF_ERR_MASK                  0x4000
+#define NIC0_QM0_GLBL_STS1_4_CP_FENCE3_UDF_ERR_SHIFT                 15
+#define NIC0_QM0_GLBL_STS1_4_CP_FENCE3_UDF_ERR_MASK                  0x8000
+
+/* NIC0_QM0_GLBL_MSG_EN */
+#define NIC0_QM0_GLBL_MSG_EN_PQF_RD_ERR_SHIFT                        0
+#define NIC0_QM0_GLBL_MSG_EN_PQF_RD_ERR_MASK                         0x1
+#define NIC0_QM0_GLBL_MSG_EN_CQF_RD_ERR_SHIFT                        1
+#define NIC0_QM0_GLBL_MSG_EN_CQF_RD_ERR_MASK                         0x2
+#define NIC0_QM0_GLBL_MSG_EN_CP_RD_ERR_SHIFT                         2
+#define NIC0_QM0_GLBL_MSG_EN_CP_RD_ERR_MASK                          0x4
+#define NIC0_QM0_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_SHIFT                  3
+#define NIC0_QM0_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_MASK                   0x8
+#define NIC0_QM0_GLBL_MSG_EN_CP_STOP_OP_SHIFT                        4
+#define NIC0_QM0_GLBL_MSG_EN_CP_STOP_OP_MASK                         0x10
+#define NIC0_QM0_GLBL_MSG_EN_CP_MSG_WR_ERR_SHIFT                     5
+#define NIC0_QM0_GLBL_MSG_EN_CP_MSG_WR_ERR_MASK                      0x20
+#define NIC0_QM0_GLBL_MSG_EN_CP_WREG_ERR_SHIFT                       6
+#define NIC0_QM0_GLBL_MSG_EN_CP_WREG_ERR_MASK                        0x40
+#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_SHIFT                 8
+#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_MASK                  0x100
+#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_SHIFT                 9
+#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_MASK                  0x200
+#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_SHIFT                 10
+#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_MASK                  0x400
+#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_SHIFT                 11
+#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_MASK                  0x800
+#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_SHIFT                 12
+#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_MASK                  0x1000
+#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_SHIFT                 13
+#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_MASK                  0x2000
+#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_SHIFT                 14
+#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_MASK                  0x4000
+#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_SHIFT                 15
+#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_MASK                  0x8000
+
+/* NIC0_QM0_GLBL_MSG_EN_4 */
+#define NIC0_QM0_GLBL_MSG_EN_4_CQF_RD_ERR_SHIFT                      1
+#define NIC0_QM0_GLBL_MSG_EN_4_CQF_RD_ERR_MASK                       0x2
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_RD_ERR_SHIFT                       2
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_RD_ERR_MASK                        0x4
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_SHIFT                3
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_MASK                 0x8
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_STOP_OP_SHIFT                      4
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_STOP_OP_MASK                       0x10
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_MSG_WR_ERR_SHIFT                   5
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_MSG_WR_ERR_MASK                    0x20
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_WREG_ERR_SHIFT                     6
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_WREG_ERR_MASK                      0x40
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_SHIFT               8
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_MASK                0x100
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_SHIFT               9
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_MASK                0x200
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_SHIFT               10
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_MASK                0x400
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_SHIFT               11
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_MASK                0x800
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_SHIFT               12
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_MASK                0x1000
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_SHIFT               13
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_MASK                0x2000
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_SHIFT               14
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_MASK                0x4000
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_SHIFT               15
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_MASK                0x8000
+
+/* NIC0_QM0_PQ_BASE_LO */
+#define NIC0_QM0_PQ_BASE_LO_VAL_SHIFT                                0
+#define NIC0_QM0_PQ_BASE_LO_VAL_MASK                                 0xFFFFFFFF
+
+/* NIC0_QM0_PQ_BASE_HI */
+#define NIC0_QM0_PQ_BASE_HI_VAL_SHIFT                                0
+#define NIC0_QM0_PQ_BASE_HI_VAL_MASK                                 0xFFFFFFFF
+
+/* NIC0_QM0_PQ_SIZE */
+#define NIC0_QM0_PQ_SIZE_VAL_SHIFT                                   0
+#define NIC0_QM0_PQ_SIZE_VAL_MASK                                    0xFFFFFFFF
+
+/* NIC0_QM0_PQ_PI */
+#define NIC0_QM0_PQ_PI_VAL_SHIFT                                     0
+#define NIC0_QM0_PQ_PI_VAL_MASK                                      0xFFFFFFFF
+
+/* NIC0_QM0_PQ_CI */
+#define NIC0_QM0_PQ_CI_VAL_SHIFT                                     0
+#define NIC0_QM0_PQ_CI_VAL_MASK                                      0xFFFFFFFF
+
+/* NIC0_QM0_PQ_CFG0 */
+#define NIC0_QM0_PQ_CFG0_RESERVED_SHIFT                              0
+#define NIC0_QM0_PQ_CFG0_RESERVED_MASK                               0x1
+
+/* NIC0_QM0_PQ_CFG1 */
+#define NIC0_QM0_PQ_CFG1_CREDIT_LIM_SHIFT                            0
+#define NIC0_QM0_PQ_CFG1_CREDIT_LIM_MASK                             0xFFFF
+#define NIC0_QM0_PQ_CFG1_MAX_INFLIGHT_SHIFT                          16
+#define NIC0_QM0_PQ_CFG1_MAX_INFLIGHT_MASK                           0xFFFF0000
+
+/* NIC0_QM0_PQ_ARUSER_31_11 */
+#define NIC0_QM0_PQ_ARUSER_31_11_VAL_SHIFT                           0
+#define NIC0_QM0_PQ_ARUSER_31_11_VAL_MASK                            0x1FFFFF
+
+/* NIC0_QM0_PQ_STS0 */
+#define NIC0_QM0_PQ_STS0_PQ_CREDIT_CNT_SHIFT                         0
+#define NIC0_QM0_PQ_STS0_PQ_CREDIT_CNT_MASK                          0xFFFF
+#define NIC0_QM0_PQ_STS0_PQ_FREE_CNT_SHIFT                           16
+#define NIC0_QM0_PQ_STS0_PQ_FREE_CNT_MASK                            0xFFFF0000
+
+/* NIC0_QM0_PQ_STS1 */
+#define NIC0_QM0_PQ_STS1_PQ_INFLIGHT_CNT_SHIFT                       0
+#define NIC0_QM0_PQ_STS1_PQ_INFLIGHT_CNT_MASK                        0xFFFF
+#define NIC0_QM0_PQ_STS1_PQ_BUF_EMPTY_SHIFT                          30
+#define NIC0_QM0_PQ_STS1_PQ_BUF_EMPTY_MASK                           0x40000000
+#define NIC0_QM0_PQ_STS1_PQ_BUSY_SHIFT                               31
+#define NIC0_QM0_PQ_STS1_PQ_BUSY_MASK                                0x80000000
+
+/* NIC0_QM0_CQ_CFG0 */
+#define NIC0_QM0_CQ_CFG0_RESERVED_SHIFT                              0
+#define NIC0_QM0_CQ_CFG0_RESERVED_MASK                               0x1
+
+/* NIC0_QM0_CQ_CFG1 */
+#define NIC0_QM0_CQ_CFG1_CREDIT_LIM_SHIFT                            0
+#define NIC0_QM0_CQ_CFG1_CREDIT_LIM_MASK                             0xFFFF
+#define NIC0_QM0_CQ_CFG1_MAX_INFLIGHT_SHIFT                          16
+#define NIC0_QM0_CQ_CFG1_MAX_INFLIGHT_MASK                           0xFFFF0000
+
+/* NIC0_QM0_CQ_ARUSER_31_11 */
+#define NIC0_QM0_CQ_ARUSER_31_11_VAL_SHIFT                           0
+#define NIC0_QM0_CQ_ARUSER_31_11_VAL_MASK                            0x1FFFFF
+
+/* NIC0_QM0_CQ_STS0 */
+#define NIC0_QM0_CQ_STS0_CQ_CREDIT_CNT_SHIFT                         0
+#define NIC0_QM0_CQ_STS0_CQ_CREDIT_CNT_MASK                          0xFFFF
+#define NIC0_QM0_CQ_STS0_CQ_FREE_CNT_SHIFT                           16
+#define NIC0_QM0_CQ_STS0_CQ_FREE_CNT_MASK                            0xFFFF0000
+
+/* NIC0_QM0_CQ_STS1 */
+#define NIC0_QM0_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT                       0
+#define NIC0_QM0_CQ_STS1_CQ_INFLIGHT_CNT_MASK                        0xFFFF
+#define NIC0_QM0_CQ_STS1_CQ_BUF_EMPTY_SHIFT                          30
+#define NIC0_QM0_CQ_STS1_CQ_BUF_EMPTY_MASK                           0x40000000
+#define NIC0_QM0_CQ_STS1_CQ_BUSY_SHIFT                               31
+#define NIC0_QM0_CQ_STS1_CQ_BUSY_MASK                                0x80000000
+
+/* NIC0_QM0_CQ_PTR_LO_0 */
+#define NIC0_QM0_CQ_PTR_LO_0_VAL_SHIFT                               0
+#define NIC0_QM0_CQ_PTR_LO_0_VAL_MASK                                0xFFFFFFFF
+
+/* NIC0_QM0_CQ_PTR_HI_0 */
+#define NIC0_QM0_CQ_PTR_HI_0_VAL_SHIFT                               0
+#define NIC0_QM0_CQ_PTR_HI_0_VAL_MASK                                0xFFFFFFFF
+
+/* NIC0_QM0_CQ_TSIZE_0 */
+#define NIC0_QM0_CQ_TSIZE_0_VAL_SHIFT                                0
+#define NIC0_QM0_CQ_TSIZE_0_VAL_MASK                                 0xFFFFFFFF
+
+/* NIC0_QM0_CQ_CTL_0 */
+#define NIC0_QM0_CQ_CTL_0_RPT_SHIFT                                  0
+#define NIC0_QM0_CQ_CTL_0_RPT_MASK                                   0xFFFF
+#define NIC0_QM0_CQ_CTL_0_CTL_SHIFT                                  16
+#define NIC0_QM0_CQ_CTL_0_CTL_MASK                                   0xFFFF0000
+
+/* NIC0_QM0_CQ_PTR_LO_1 */
+#define NIC0_QM0_CQ_PTR_LO_1_VAL_SHIFT                               0
+#define NIC0_QM0_CQ_PTR_LO_1_VAL_MASK                                0xFFFFFFFF
+
+/* NIC0_QM0_CQ_PTR_HI_1 */
+#define NIC0_QM0_CQ_PTR_HI_1_VAL_SHIFT                               0
+#define NIC0_QM0_CQ_PTR_HI_1_VAL_MASK                                0xFFFFFFFF
+
+/* NIC0_QM0_CQ_TSIZE_1 */
+#define NIC0_QM0_CQ_TSIZE_1_VAL_SHIFT                                0
+#define NIC0_QM0_CQ_TSIZE_1_VAL_MASK                                 0xFFFFFFFF
+
+/* NIC0_QM0_CQ_CTL_1 */
+#define NIC0_QM0_CQ_CTL_1_RPT_SHIFT                                  0
+#define NIC0_QM0_CQ_CTL_1_RPT_MASK                                   0xFFFF
+#define NIC0_QM0_CQ_CTL_1_CTL_SHIFT                                  16
+#define NIC0_QM0_CQ_CTL_1_CTL_MASK                                   0xFFFF0000
+
+/* NIC0_QM0_CQ_PTR_LO_2 */
+#define NIC0_QM0_CQ_PTR_LO_2_VAL_SHIFT                               0
+#define NIC0_QM0_CQ_PTR_LO_2_VAL_MASK                                0xFFFFFFFF
+
+/* NIC0_QM0_CQ_PTR_HI_2 */
+#define NIC0_QM0_CQ_PTR_HI_2_VAL_SHIFT                               0
+#define NIC0_QM0_CQ_PTR_HI_2_VAL_MASK                                0xFFFFFFFF
+
+/* NIC0_QM0_CQ_TSIZE_2 */
+#define NIC0_QM0_CQ_TSIZE_2_VAL_SHIFT                                0
+#define NIC0_QM0_CQ_TSIZE_2_VAL_MASK                                 0xFFFFFFFF
+
+/* NIC0_QM0_CQ_CTL_2 */
+#define NIC0_QM0_CQ_CTL_2_RPT_SHIFT                                  0
+#define NIC0_QM0_CQ_CTL_2_RPT_MASK                                   0xFFFF
+#define NIC0_QM0_CQ_CTL_2_CTL_SHIFT                                  16
+#define NIC0_QM0_CQ_CTL_2_CTL_MASK                                   0xFFFF0000
+
+/* NIC0_QM0_CQ_PTR_LO_3 */
+#define NIC0_QM0_CQ_PTR_LO_3_VAL_SHIFT                               0
+#define NIC0_QM0_CQ_PTR_LO_3_VAL_MASK                                0xFFFFFFFF
+
+/* NIC0_QM0_CQ_PTR_HI_3 */
+#define NIC0_QM0_CQ_PTR_HI_3_VAL_SHIFT                               0
+#define NIC0_QM0_CQ_PTR_HI_3_VAL_MASK                                0xFFFFFFFF
+
+/* NIC0_QM0_CQ_TSIZE_3 */
+#define NIC0_QM0_CQ_TSIZE_3_VAL_SHIFT                                0
+#define NIC0_QM0_CQ_TSIZE_3_VAL_MASK                                 0xFFFFFFFF
+
+/* NIC0_QM0_CQ_CTL_3 */
+#define NIC0_QM0_CQ_CTL_3_RPT_SHIFT                                  0
+#define NIC0_QM0_CQ_CTL_3_RPT_MASK                                   0xFFFF
+#define NIC0_QM0_CQ_CTL_3_CTL_SHIFT                                  16
+#define NIC0_QM0_CQ_CTL_3_CTL_MASK                                   0xFFFF0000
+
+/* NIC0_QM0_CQ_PTR_LO_4 */
+#define NIC0_QM0_CQ_PTR_LO_4_VAL_SHIFT                               0
+#define NIC0_QM0_CQ_PTR_LO_4_VAL_MASK                                0xFFFFFFFF
+
+/* NIC0_QM0_CQ_PTR_HI_4 */
+#define NIC0_QM0_CQ_PTR_HI_4_VAL_SHIFT                               0
+#define NIC0_QM0_CQ_PTR_HI_4_VAL_MASK                                0xFFFFFFFF
+
+/* NIC0_QM0_CQ_TSIZE_4 */
+#define NIC0_QM0_CQ_TSIZE_4_VAL_SHIFT                                0
+#define NIC0_QM0_CQ_TSIZE_4_VAL_MASK                                 0xFFFFFFFF
+
+/* NIC0_QM0_CQ_CTL_4 */
+#define NIC0_QM0_CQ_CTL_4_RPT_SHIFT                                  0
+#define NIC0_QM0_CQ_CTL_4_RPT_MASK                                   0xFFFF
+#define NIC0_QM0_CQ_CTL_4_CTL_SHIFT                                  16
+#define NIC0_QM0_CQ_CTL_4_CTL_MASK                                   0xFFFF0000
+
+/* NIC0_QM0_CQ_PTR_LO_STS */
+#define NIC0_QM0_CQ_PTR_LO_STS_VAL_SHIFT                             0
+#define NIC0_QM0_CQ_PTR_LO_STS_VAL_MASK                              0xFFFFFFFF
+
+/* NIC0_QM0_CQ_PTR_HI_STS */
+#define NIC0_QM0_CQ_PTR_HI_STS_VAL_SHIFT                             0
+#define NIC0_QM0_CQ_PTR_HI_STS_VAL_MASK                              0xFFFFFFFF
+
+/* NIC0_QM0_CQ_TSIZE_STS */
+#define NIC0_QM0_CQ_TSIZE_STS_VAL_SHIFT                              0
+#define NIC0_QM0_CQ_TSIZE_STS_VAL_MASK                               0xFFFFFFFF
+
+/* NIC0_QM0_CQ_CTL_STS */
+#define NIC0_QM0_CQ_CTL_STS_RPT_SHIFT                                0
+#define NIC0_QM0_CQ_CTL_STS_RPT_MASK                                 0xFFFF
+#define NIC0_QM0_CQ_CTL_STS_CTL_SHIFT                                16
+#define NIC0_QM0_CQ_CTL_STS_CTL_MASK                                 0xFFFF0000
+
+/* NIC0_QM0_CQ_IFIFO_CNT */
+#define NIC0_QM0_CQ_IFIFO_CNT_VAL_SHIFT                              0
+#define NIC0_QM0_CQ_IFIFO_CNT_VAL_MASK                               0x3
+
+/* NIC0_QM0_CP_MSG_BASE0_ADDR_LO */
+#define NIC0_QM0_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT                      0
+#define NIC0_QM0_CP_MSG_BASE0_ADDR_LO_VAL_MASK                       0xFFFFFFFF
+
+/* NIC0_QM0_CP_MSG_BASE0_ADDR_HI */
+#define NIC0_QM0_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT                      0
+#define NIC0_QM0_CP_MSG_BASE0_ADDR_HI_VAL_MASK                       0xFFFFFFFF
+
+/* NIC0_QM0_CP_MSG_BASE1_ADDR_LO */
+#define NIC0_QM0_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT                      0
+#define NIC0_QM0_CP_MSG_BASE1_ADDR_LO_VAL_MASK                       0xFFFFFFFF
+
+/* NIC0_QM0_CP_MSG_BASE1_ADDR_HI */
+#define NIC0_QM0_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT                      0
+#define NIC0_QM0_CP_MSG_BASE1_ADDR_HI_VAL_MASK                       0xFFFFFFFF
+
+/* NIC0_QM0_CP_MSG_BASE2_ADDR_LO */
+#define NIC0_QM0_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT                      0
+#define NIC0_QM0_CP_MSG_BASE2_ADDR_LO_VAL_MASK                       0xFFFFFFFF
+
+/* NIC0_QM0_CP_MSG_BASE2_ADDR_HI */
+#define NIC0_QM0_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT                      0
+#define NIC0_QM0_CP_MSG_BASE2_ADDR_HI_VAL_MASK                       0xFFFFFFFF
+
+/* NIC0_QM0_CP_MSG_BASE3_ADDR_LO */
+#define NIC0_QM0_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT                      0
+#define NIC0_QM0_CP_MSG_BASE3_ADDR_LO_VAL_MASK                       0xFFFFFFFF
+
+/* NIC0_QM0_CP_MSG_BASE3_ADDR_HI */
+#define NIC0_QM0_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT                      0
+#define NIC0_QM0_CP_MSG_BASE3_ADDR_HI_VAL_MASK                       0xFFFFFFFF
+
+/* NIC0_QM0_CP_LDMA_TSIZE_OFFSET */
+#define NIC0_QM0_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT                      0
+#define NIC0_QM0_CP_LDMA_TSIZE_OFFSET_VAL_MASK                       0xFFFFFFFF
+
+/* NIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET */
+#define NIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT                0
+#define NIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK                 0xFFFFFFFF
+
+/* NIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET */
+#define NIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT                0
+#define NIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK                 0xFFFFFFFF
+
+/* NIC0_QM0_CP_FENCE0_RDATA */
+#define NIC0_QM0_CP_FENCE0_RDATA_INC_VAL_SHIFT                       0
+#define NIC0_QM0_CP_FENCE0_RDATA_INC_VAL_MASK                        0xF
+
+/* NIC0_QM0_CP_FENCE1_RDATA */
+#define NIC0_QM0_CP_FENCE1_RDATA_INC_VAL_SHIFT                       0
+#define NIC0_QM0_CP_FENCE1_RDATA_INC_VAL_MASK                        0xF
+
+/* NIC0_QM0_CP_FENCE2_RDATA */
+#define NIC0_QM0_CP_FENCE2_RDATA_INC_VAL_SHIFT                       0
+#define NIC0_QM0_CP_FENCE2_RDATA_INC_VAL_MASK                        0xF
+
+/* NIC0_QM0_CP_FENCE3_RDATA */
+#define NIC0_QM0_CP_FENCE3_RDATA_INC_VAL_SHIFT                       0
+#define NIC0_QM0_CP_FENCE3_RDATA_INC_VAL_MASK                        0xF
+
+/* NIC0_QM0_CP_FENCE0_CNT */
+#define NIC0_QM0_CP_FENCE0_CNT_VAL_SHIFT                             0
+#define NIC0_QM0_CP_FENCE0_CNT_VAL_MASK                              0x3FFF
+
+/* NIC0_QM0_CP_FENCE1_CNT */
+#define NIC0_QM0_CP_FENCE1_CNT_VAL_SHIFT                             0
+#define NIC0_QM0_CP_FENCE1_CNT_VAL_MASK                              0x3FFF
+
+/* NIC0_QM0_CP_FENCE2_CNT */
+#define NIC0_QM0_CP_FENCE2_CNT_VAL_SHIFT                             0
+#define NIC0_QM0_CP_FENCE2_CNT_VAL_MASK                              0x3FFF
+
+/* NIC0_QM0_CP_FENCE3_CNT */
+#define NIC0_QM0_CP_FENCE3_CNT_VAL_SHIFT                             0
+#define NIC0_QM0_CP_FENCE3_CNT_VAL_MASK                              0x3FFF
+
+/* NIC0_QM0_CP_STS */
+#define NIC0_QM0_CP_STS_MSG_INFLIGHT_CNT_SHIFT                       0
+#define NIC0_QM0_CP_STS_MSG_INFLIGHT_CNT_MASK                        0xFFFF
+#define NIC0_QM0_CP_STS_ERDY_SHIFT                                   16
+#define NIC0_QM0_CP_STS_ERDY_MASK                                    0x10000
+#define NIC0_QM0_CP_STS_RRDY_SHIFT                                   17
+#define NIC0_QM0_CP_STS_RRDY_MASK                                    0x20000
+#define NIC0_QM0_CP_STS_MRDY_SHIFT                                   18
+#define NIC0_QM0_CP_STS_MRDY_MASK                                    0x40000
+#define NIC0_QM0_CP_STS_SW_STOP_SHIFT                                19
+#define NIC0_QM0_CP_STS_SW_STOP_MASK                                 0x80000
+#define NIC0_QM0_CP_STS_FENCE_ID_SHIFT                               20
+#define NIC0_QM0_CP_STS_FENCE_ID_MASK                                0x300000
+#define NIC0_QM0_CP_STS_FENCE_IN_PROGRESS_SHIFT                      22
+#define NIC0_QM0_CP_STS_FENCE_IN_PROGRESS_MASK                       0x400000
+
+/* NIC0_QM0_CP_CURRENT_INST_LO */
+#define NIC0_QM0_CP_CURRENT_INST_LO_VAL_SHIFT                        0
+#define NIC0_QM0_CP_CURRENT_INST_LO_VAL_MASK                         0xFFFFFFFF
+
+/* NIC0_QM0_CP_CURRENT_INST_HI */
+#define NIC0_QM0_CP_CURRENT_INST_HI_VAL_SHIFT                        0
+#define NIC0_QM0_CP_CURRENT_INST_HI_VAL_MASK                         0xFFFFFFFF
+
+/* NIC0_QM0_CP_BARRIER_CFG */
+#define NIC0_QM0_CP_BARRIER_CFG_EBGUARD_SHIFT                        0
+#define NIC0_QM0_CP_BARRIER_CFG_EBGUARD_MASK                         0xFFF
+#define NIC0_QM0_CP_BARRIER_CFG_RBGUARD_SHIFT                        16
+#define NIC0_QM0_CP_BARRIER_CFG_RBGUARD_MASK                         0xF0000
+
+/* NIC0_QM0_CP_DBG_0 */
+#define NIC0_QM0_CP_DBG_0_CS_SHIFT                                   0
+#define NIC0_QM0_CP_DBG_0_CS_MASK                                    0xF
+#define NIC0_QM0_CP_DBG_0_EB_CNT_NOT_ZERO_SHIFT                      4
+#define NIC0_QM0_CP_DBG_0_EB_CNT_NOT_ZERO_MASK                       0x10
+#define NIC0_QM0_CP_DBG_0_BULK_CNT_NOT_ZERO_SHIFT                    5
+#define NIC0_QM0_CP_DBG_0_BULK_CNT_NOT_ZERO_MASK                     0x20
+#define NIC0_QM0_CP_DBG_0_MREB_STALL_SHIFT                           6
+#define NIC0_QM0_CP_DBG_0_MREB_STALL_MASK                            0x40
+#define NIC0_QM0_CP_DBG_0_STALL_SHIFT                                7
+#define NIC0_QM0_CP_DBG_0_STALL_MASK                                 0x80
+
+/* NIC0_QM0_CP_ARUSER_31_11 */
+#define NIC0_QM0_CP_ARUSER_31_11_VAL_SHIFT                           0
+#define NIC0_QM0_CP_ARUSER_31_11_VAL_MASK                            0x1FFFFF
+
+/* NIC0_QM0_CP_AWUSER_31_11 */
+#define NIC0_QM0_CP_AWUSER_31_11_VAL_SHIFT                           0
+#define NIC0_QM0_CP_AWUSER_31_11_VAL_MASK                            0x1FFFFF
+
+/* NIC0_QM0_ARB_CFG_0 */
+#define NIC0_QM0_ARB_CFG_0_TYPE_SHIFT                                0
+#define NIC0_QM0_ARB_CFG_0_TYPE_MASK                                 0x1
+#define NIC0_QM0_ARB_CFG_0_IS_MASTER_SHIFT                           4
+#define NIC0_QM0_ARB_CFG_0_IS_MASTER_MASK                            0x10
+#define NIC0_QM0_ARB_CFG_0_EN_SHIFT                                  8
+#define NIC0_QM0_ARB_CFG_0_EN_MASK                                   0x100
+#define NIC0_QM0_ARB_CFG_0_MASK_SHIFT                                12
+#define NIC0_QM0_ARB_CFG_0_MASK_MASK                                 0xF000
+#define NIC0_QM0_ARB_CFG_0_MST_MSG_NOSTALL_SHIFT                     16
+#define NIC0_QM0_ARB_CFG_0_MST_MSG_NOSTALL_MASK                      0x10000
+
+/* NIC0_QM0_ARB_CHOISE_Q_PUSH */
+#define NIC0_QM0_ARB_CHOISE_Q_PUSH_VAL_SHIFT                         0
+#define NIC0_QM0_ARB_CHOISE_Q_PUSH_VAL_MASK                          0x3
+
+/* NIC0_QM0_ARB_WRR_WEIGHT */
+#define NIC0_QM0_ARB_WRR_WEIGHT_VAL_SHIFT                            0
+#define NIC0_QM0_ARB_WRR_WEIGHT_VAL_MASK                             0xFFFFFFFF
+
+/* NIC0_QM0_ARB_CFG_1 */
+#define NIC0_QM0_ARB_CFG_1_CLR_SHIFT                                 0
+#define NIC0_QM0_ARB_CFG_1_CLR_MASK                                  0x1
+
+/* NIC0_QM0_ARB_MST_AVAIL_CRED */
+#define NIC0_QM0_ARB_MST_AVAIL_CRED_VAL_SHIFT                        0
+#define NIC0_QM0_ARB_MST_AVAIL_CRED_VAL_MASK                         0x7F
+
+/* NIC0_QM0_ARB_MST_CRED_INC */
+#define NIC0_QM0_ARB_MST_CRED_INC_VAL_SHIFT                          0
+#define NIC0_QM0_ARB_MST_CRED_INC_VAL_MASK                           0xFFFFFFFF
+
+/* NIC0_QM0_ARB_MST_CHOISE_PUSH_OFST */
+#define NIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_VAL_SHIFT                  0
+#define NIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_VAL_MASK                   0xFFFFFFFF
+
+/* NIC0_QM0_ARB_SLV_MASTER_INC_CRED_OFST */
+#define NIC0_QM0_ARB_SLV_MASTER_INC_CRED_OFST_VAL_SHIFT              0
+#define NIC0_QM0_ARB_SLV_MASTER_INC_CRED_OFST_VAL_MASK               0xFFFFFFFF
+
+/* NIC0_QM0_ARB_MST_SLAVE_EN */
+#define NIC0_QM0_ARB_MST_SLAVE_EN_VAL_SHIFT                          0
+#define NIC0_QM0_ARB_MST_SLAVE_EN_VAL_MASK                           0xFFFFFFFF
+
+/* NIC0_QM0_ARB_MST_QUIET_PER */
+#define NIC0_QM0_ARB_MST_QUIET_PER_VAL_SHIFT                         0
+#define NIC0_QM0_ARB_MST_QUIET_PER_VAL_MASK                          0xFFFFFFFF
+
+/* NIC0_QM0_ARB_SLV_CHOISE_WDT */
+#define NIC0_QM0_ARB_SLV_CHOISE_WDT_VAL_SHIFT                        0
+#define NIC0_QM0_ARB_SLV_CHOISE_WDT_VAL_MASK                         0xFFFFFFFF
+
+/* NIC0_QM0_ARB_SLV_ID */
+#define NIC0_QM0_ARB_SLV_ID_VAL_SHIFT                                0
+#define NIC0_QM0_ARB_SLV_ID_VAL_MASK                                 0x1F
+
+/* NIC0_QM0_ARB_MSG_MAX_INFLIGHT */
+#define NIC0_QM0_ARB_MSG_MAX_INFLIGHT_VAL_SHIFT                      0
+#define NIC0_QM0_ARB_MSG_MAX_INFLIGHT_VAL_MASK                       0x3F
+
+/* NIC0_QM0_ARB_MSG_AWUSER_31_11 */
+#define NIC0_QM0_ARB_MSG_AWUSER_31_11_VAL_SHIFT                      0
+#define NIC0_QM0_ARB_MSG_AWUSER_31_11_VAL_MASK                       0x1FFFFF
+
+/* NIC0_QM0_ARB_MSG_AWUSER_SEC_PROP */
+#define NIC0_QM0_ARB_MSG_AWUSER_SEC_PROP_ASID_SHIFT                  0
+#define NIC0_QM0_ARB_MSG_AWUSER_SEC_PROP_ASID_MASK                   0x3FF
+#define NIC0_QM0_ARB_MSG_AWUSER_SEC_PROP_MMBP_SHIFT                  10
+#define NIC0_QM0_ARB_MSG_AWUSER_SEC_PROP_MMBP_MASK                   0x400
+
+/* NIC0_QM0_ARB_MSG_AWUSER_NON_SEC_PROP */
+#define NIC0_QM0_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_SHIFT              0
+#define NIC0_QM0_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_MASK               0x3FF
+#define NIC0_QM0_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_SHIFT              10
+#define NIC0_QM0_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_MASK               0x400
+
+/* NIC0_QM0_ARB_BASE_LO */
+#define NIC0_QM0_ARB_BASE_LO_VAL_SHIFT                               0
+#define NIC0_QM0_ARB_BASE_LO_VAL_MASK                                0xFFFFFFFF
+
+/* NIC0_QM0_ARB_BASE_HI */
+#define NIC0_QM0_ARB_BASE_HI_VAL_SHIFT                               0
+#define NIC0_QM0_ARB_BASE_HI_VAL_MASK                                0xFFFFFFFF
+
+/* NIC0_QM0_ARB_STATE_STS */
+#define NIC0_QM0_ARB_STATE_STS_VAL_SHIFT                             0
+#define NIC0_QM0_ARB_STATE_STS_VAL_MASK                              0xFFFFFFFF
+
+/* NIC0_QM0_ARB_CHOISE_FULLNESS_STS */
+#define NIC0_QM0_ARB_CHOISE_FULLNESS_STS_VAL_SHIFT                   0
+#define NIC0_QM0_ARB_CHOISE_FULLNESS_STS_VAL_MASK                    0x7F
+
+/* NIC0_QM0_ARB_MSG_STS */
+#define NIC0_QM0_ARB_MSG_STS_FULL_SHIFT                              0
+#define NIC0_QM0_ARB_MSG_STS_FULL_MASK                               0x1
+#define NIC0_QM0_ARB_MSG_STS_NO_INFLIGHT_SHIFT                       1
+#define NIC0_QM0_ARB_MSG_STS_NO_INFLIGHT_MASK                        0x2
+
+/* NIC0_QM0_ARB_SLV_CHOISE_Q_HEAD */
+#define NIC0_QM0_ARB_SLV_CHOISE_Q_HEAD_VAL_SHIFT                     0
+#define NIC0_QM0_ARB_SLV_CHOISE_Q_HEAD_VAL_MASK                      0x3
+
+/* NIC0_QM0_ARB_ERR_CAUSE */
+#define NIC0_QM0_ARB_ERR_CAUSE_CHOISE_OVF_SHIFT                      0
+#define NIC0_QM0_ARB_ERR_CAUSE_CHOISE_OVF_MASK                       0x1
+#define NIC0_QM0_ARB_ERR_CAUSE_CHOISE_WDT_SHIFT                      1
+#define NIC0_QM0_ARB_ERR_CAUSE_CHOISE_WDT_MASK                       0x2
+#define NIC0_QM0_ARB_ERR_CAUSE_AXI_LBW_ERR_SHIFT                     2
+#define NIC0_QM0_ARB_ERR_CAUSE_AXI_LBW_ERR_MASK                      0x4
+
+/* NIC0_QM0_ARB_ERR_MSG_EN */
+#define NIC0_QM0_ARB_ERR_MSG_EN_CHOISE_OVF_SHIFT                     0
+#define NIC0_QM0_ARB_ERR_MSG_EN_CHOISE_OVF_MASK                      0x1
+#define NIC0_QM0_ARB_ERR_MSG_EN_CHOISE_WDT_SHIFT                     1
+#define NIC0_QM0_ARB_ERR_MSG_EN_CHOISE_WDT_MASK                      0x2
+#define NIC0_QM0_ARB_ERR_MSG_EN_AXI_LBW_ERR_SHIFT                    2
+#define NIC0_QM0_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK                     0x4
+
+/* NIC0_QM0_ARB_ERR_STS_DRP */
+#define NIC0_QM0_ARB_ERR_STS_DRP_VAL_SHIFT                           0
+#define NIC0_QM0_ARB_ERR_STS_DRP_VAL_MASK                            0x3
+
+/* NIC0_QM0_ARB_MST_CRED_STS */
+#define NIC0_QM0_ARB_MST_CRED_STS_VAL_SHIFT                          0
+#define NIC0_QM0_ARB_MST_CRED_STS_VAL_MASK                           0x7F
+
+/* NIC0_QM0_CGM_CFG */
+#define NIC0_QM0_CGM_CFG_IDLE_TH_SHIFT                               0
+#define NIC0_QM0_CGM_CFG_IDLE_TH_MASK                                0xFFF
+#define NIC0_QM0_CGM_CFG_G2F_TH_SHIFT                                16
+#define NIC0_QM0_CGM_CFG_G2F_TH_MASK                                 0xFF0000
+#define NIC0_QM0_CGM_CFG_CP_IDLE_MASK_SHIFT                          24
+#define NIC0_QM0_CGM_CFG_CP_IDLE_MASK_MASK                           0x1F000000
+#define NIC0_QM0_CGM_CFG_EN_SHIFT                                    31
+#define NIC0_QM0_CGM_CFG_EN_MASK                                     0x80000000
+
+/* NIC0_QM0_CGM_STS */
+#define NIC0_QM0_CGM_STS_ST_SHIFT                                    0
+#define NIC0_QM0_CGM_STS_ST_MASK                                     0x3
+#define NIC0_QM0_CGM_STS_CG_SHIFT                                    4
+#define NIC0_QM0_CGM_STS_CG_MASK                                     0x10
+#define NIC0_QM0_CGM_STS_AGENT_IDLE_SHIFT                            8
+#define NIC0_QM0_CGM_STS_AGENT_IDLE_MASK                             0x100
+#define NIC0_QM0_CGM_STS_AXI_IDLE_SHIFT                              9
+#define NIC0_QM0_CGM_STS_AXI_IDLE_MASK                               0x200
+#define NIC0_QM0_CGM_STS_CP_IDLE_SHIFT                               10
+#define NIC0_QM0_CGM_STS_CP_IDLE_MASK                                0x400
+
+/* NIC0_QM0_CGM_CFG1 */
+#define NIC0_QM0_CGM_CFG1_MASK_TH_SHIFT                              0
+#define NIC0_QM0_CGM_CFG1_MASK_TH_MASK                               0xFF
+
+/* NIC0_QM0_LOCAL_RANGE_BASE */
+#define NIC0_QM0_LOCAL_RANGE_BASE_VAL_SHIFT                          0
+#define NIC0_QM0_LOCAL_RANGE_BASE_VAL_MASK                           0xFFFF
+
+/* NIC0_QM0_LOCAL_RANGE_SIZE */
+#define NIC0_QM0_LOCAL_RANGE_SIZE_VAL_SHIFT                          0
+#define NIC0_QM0_LOCAL_RANGE_SIZE_VAL_MASK                           0xFFFF
+
+/* NIC0_QM0_CSMR_STRICT_PRIO_CFG */
+#define NIC0_QM0_CSMR_STRICT_PRIO_CFG_TYPE_SHIFT                     0
+#define NIC0_QM0_CSMR_STRICT_PRIO_CFG_TYPE_MASK                      0x1
+
+/* NIC0_QM0_HBW_RD_RATE_LIM_CFG_1 */
+#define NIC0_QM0_HBW_RD_RATE_LIM_CFG_1_TOUT_SHIFT                    0
+#define NIC0_QM0_HBW_RD_RATE_LIM_CFG_1_TOUT_MASK                     0xFF
+#define NIC0_QM0_HBW_RD_RATE_LIM_CFG_1_EN_SHIFT                      31
+#define NIC0_QM0_HBW_RD_RATE_LIM_CFG_1_EN_MASK                       0x80000000
+
+/* NIC0_QM0_LBW_WR_RATE_LIM_CFG_0 */
+#define NIC0_QM0_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT               0
+#define NIC0_QM0_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK                0xFF
+#define NIC0_QM0_LBW_WR_RATE_LIM_CFG_0_SAT_SHIFT                     16
+#define NIC0_QM0_LBW_WR_RATE_LIM_CFG_0_SAT_MASK                      0xFF0000
+
+/* NIC0_QM0_LBW_WR_RATE_LIM_CFG_1 */
+#define NIC0_QM0_LBW_WR_RATE_LIM_CFG_1_TOUT_SHIFT                    0
+#define NIC0_QM0_LBW_WR_RATE_LIM_CFG_1_TOUT_MASK                     0xFF
+#define NIC0_QM0_LBW_WR_RATE_LIM_CFG_1_EN_SHIFT                      31
+#define NIC0_QM0_LBW_WR_RATE_LIM_CFG_1_EN_MASK                       0x80000000
+
+/* NIC0_QM0_HBW_RD_RATE_LIM_CFG_0 */
+#define NIC0_QM0_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT               0
+#define NIC0_QM0_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK                0xFF
+#define NIC0_QM0_HBW_RD_RATE_LIM_CFG_0_SAT_SHIFT                     16
+#define NIC0_QM0_HBW_RD_RATE_LIM_CFG_0_SAT_MASK                      0xFF0000
+
+/* NIC0_QM0_GLBL_AXCACHE */
+#define NIC0_QM0_GLBL_AXCACHE_AR_SHIFT                               0
+#define NIC0_QM0_GLBL_AXCACHE_AR_MASK                                0xF
+#define NIC0_QM0_GLBL_AXCACHE_AW_SHIFT                               16
+#define NIC0_QM0_GLBL_AXCACHE_AW_MASK                                0xF0000
+
+/* NIC0_QM0_IND_GW_APB_CFG */
+#define NIC0_QM0_IND_GW_APB_CFG_ADDR_SHIFT                           0
+#define NIC0_QM0_IND_GW_APB_CFG_ADDR_MASK                            0x7FFFFFFF
+#define NIC0_QM0_IND_GW_APB_CFG_CMD_SHIFT                            31
+#define NIC0_QM0_IND_GW_APB_CFG_CMD_MASK                             0x80000000
+
+/* NIC0_QM0_IND_GW_APB_WDATA */
+#define NIC0_QM0_IND_GW_APB_WDATA_VAL_SHIFT                          0
+#define NIC0_QM0_IND_GW_APB_WDATA_VAL_MASK                           0xFFFFFFFF
+
+/* NIC0_QM0_IND_GW_APB_RDATA */
+#define NIC0_QM0_IND_GW_APB_RDATA_VAL_SHIFT                          0
+#define NIC0_QM0_IND_GW_APB_RDATA_VAL_MASK                           0xFFFFFFFF
+
+/* NIC0_QM0_IND_GW_APB_STATUS */
+#define NIC0_QM0_IND_GW_APB_STATUS_RDY_SHIFT                         0
+#define NIC0_QM0_IND_GW_APB_STATUS_RDY_MASK                          0x1
+#define NIC0_QM0_IND_GW_APB_STATUS_ERR_SHIFT                         1
+#define NIC0_QM0_IND_GW_APB_STATUS_ERR_MASK                          0x2
+
+/* NIC0_QM0_GLBL_ERR_ADDR_LO */
+#define NIC0_QM0_GLBL_ERR_ADDR_LO_VAL_SHIFT                          0
+#define NIC0_QM0_GLBL_ERR_ADDR_LO_VAL_MASK                           0xFFFFFFFF
+
+/* NIC0_QM0_GLBL_ERR_ADDR_HI */
+#define NIC0_QM0_GLBL_ERR_ADDR_HI_VAL_SHIFT                          0
+#define NIC0_QM0_GLBL_ERR_ADDR_HI_VAL_MASK                           0xFFFFFFFF
+
+/* NIC0_QM0_GLBL_ERR_WDATA */
+#define NIC0_QM0_GLBL_ERR_WDATA_VAL_SHIFT                            0
+#define NIC0_QM0_GLBL_ERR_WDATA_VAL_MASK                             0xFFFFFFFF
+
+/* NIC0_QM0_GLBL_MEM_INIT_BUSY */
+#define NIC0_QM0_GLBL_MEM_INIT_BUSY_RBUF_SHIFT                       0
+#define NIC0_QM0_GLBL_MEM_INIT_BUSY_RBUF_MASK                        0xF
+
+#endif /* ASIC_REG_NIC0_QM0_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/nic0_qm0_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic0_qm0_regs.h
new file mode 100644
index 000000000000..7c97f4041b8e
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic0_qm0_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_QM0_REGS_H_
+#define ASIC_REG_NIC0_QM0_REGS_H_
+
+/*
+ *****************************************
+ *   NIC0_QM0 (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmNIC0_QM0_GLBL_CFG0                                         0xCE0000
+
+#define mmNIC0_QM0_GLBL_CFG1                                         0xCE0004
+
+#define mmNIC0_QM0_GLBL_PROT                                         0xCE0008
+
+#define mmNIC0_QM0_GLBL_ERR_CFG                                      0xCE000C
+
+#define mmNIC0_QM0_GLBL_SECURE_PROPS_0                               0xCE0010
+
+#define mmNIC0_QM0_GLBL_SECURE_PROPS_1                               0xCE0014
+
+#define mmNIC0_QM0_GLBL_SECURE_PROPS_2                               0xCE0018
+
+#define mmNIC0_QM0_GLBL_SECURE_PROPS_3                               0xCE001C
+
+#define mmNIC0_QM0_GLBL_SECURE_PROPS_4                               0xCE0020
+
+#define mmNIC0_QM0_GLBL_NON_SECURE_PROPS_0                           0xCE0024
+
+#define mmNIC0_QM0_GLBL_NON_SECURE_PROPS_1                           0xCE0028
+
+#define mmNIC0_QM0_GLBL_NON_SECURE_PROPS_2                           0xCE002C
+
+#define mmNIC0_QM0_GLBL_NON_SECURE_PROPS_3                           0xCE0030
+
+#define mmNIC0_QM0_GLBL_NON_SECURE_PROPS_4                           0xCE0034
+
+#define mmNIC0_QM0_GLBL_STS0                                         0xCE0038
+
+#define mmNIC0_QM0_GLBL_STS1_0                                       0xCE0040
+
+#define mmNIC0_QM0_GLBL_STS1_1                                       0xCE0044
+
+#define mmNIC0_QM0_GLBL_STS1_2                                       0xCE0048
+
+#define mmNIC0_QM0_GLBL_STS1_3                                       0xCE004C
+
+#define mmNIC0_QM0_GLBL_STS1_4                                       0xCE0050
+
+#define mmNIC0_QM0_GLBL_MSG_EN_0                                     0xCE0054
+
+#define mmNIC0_QM0_GLBL_MSG_EN_1                                     0xCE0058
+
+#define mmNIC0_QM0_GLBL_MSG_EN_2                                     0xCE005C
+
+#define mmNIC0_QM0_GLBL_MSG_EN_3                                     0xCE0060
+
+#define mmNIC0_QM0_GLBL_MSG_EN_4                                     0xCE0068
+
+#define mmNIC0_QM0_PQ_BASE_LO_0                                      0xCE0070
+
+#define mmNIC0_QM0_PQ_BASE_LO_1                                      0xCE0074
+
+#define mmNIC0_QM0_PQ_BASE_LO_2                                      0xCE0078
+
+#define mmNIC0_QM0_PQ_BASE_LO_3                                      0xCE007C
+
+#define mmNIC0_QM0_PQ_BASE_HI_0                                      0xCE0080
+
+#define mmNIC0_QM0_PQ_BASE_HI_1                                      0xCE0084
+
+#define mmNIC0_QM0_PQ_BASE_HI_2                                      0xCE0088
+
+#define mmNIC0_QM0_PQ_BASE_HI_3                                      0xCE008C
+
+#define mmNIC0_QM0_PQ_SIZE_0                                         0xCE0090
+
+#define mmNIC0_QM0_PQ_SIZE_1                                         0xCE0094
+
+#define mmNIC0_QM0_PQ_SIZE_2                                         0xCE0098
+
+#define mmNIC0_QM0_PQ_SIZE_3                                         0xCE009C
+
+#define mmNIC0_QM0_PQ_PI_0                                           0xCE00A0
+
+#define mmNIC0_QM0_PQ_PI_1                                           0xCE00A4
+
+#define mmNIC0_QM0_PQ_PI_2                                           0xCE00A8
+
+#define mmNIC0_QM0_PQ_PI_3                                           0xCE00AC
+
+#define mmNIC0_QM0_PQ_CI_0                                           0xCE00B0
+
+#define mmNIC0_QM0_PQ_CI_1                                           0xCE00B4
+
+#define mmNIC0_QM0_PQ_CI_2                                           0xCE00B8
+
+#define mmNIC0_QM0_PQ_CI_3                                           0xCE00BC
+
+#define mmNIC0_QM0_PQ_CFG0_0                                         0xCE00C0
+
+#define mmNIC0_QM0_PQ_CFG0_1                                         0xCE00C4
+
+#define mmNIC0_QM0_PQ_CFG0_2                                         0xCE00C8
+
+#define mmNIC0_QM0_PQ_CFG0_3                                         0xCE00CC
+
+#define mmNIC0_QM0_PQ_CFG1_0                                         0xCE00D0
+
+#define mmNIC0_QM0_PQ_CFG1_1                                         0xCE00D4
+
+#define mmNIC0_QM0_PQ_CFG1_2                                         0xCE00D8
+
+#define mmNIC0_QM0_PQ_CFG1_3                                         0xCE00DC
+
+#define mmNIC0_QM0_PQ_ARUSER_31_11_0                                 0xCE00E0
+
+#define mmNIC0_QM0_PQ_ARUSER_31_11_1                                 0xCE00E4
+
+#define mmNIC0_QM0_PQ_ARUSER_31_11_2                                 0xCE00E8
+
+#define mmNIC0_QM0_PQ_ARUSER_31_11_3                                 0xCE00EC
+
+#define mmNIC0_QM0_PQ_STS0_0                                         0xCE00F0
+
+#define mmNIC0_QM0_PQ_STS0_1                                         0xCE00F4
+
+#define mmNIC0_QM0_PQ_STS0_2                                         0xCE00F8
+
+#define mmNIC0_QM0_PQ_STS0_3                                         0xCE00FC
+
+#define mmNIC0_QM0_PQ_STS1_0                                         0xCE0100
+
+#define mmNIC0_QM0_PQ_STS1_1                                         0xCE0104
+
+#define mmNIC0_QM0_PQ_STS1_2                                         0xCE0108
+
+#define mmNIC0_QM0_PQ_STS1_3                                         0xCE010C
+
+#define mmNIC0_QM0_CQ_CFG0_0                                         0xCE0110
+
+#define mmNIC0_QM0_CQ_CFG0_1                                         0xCE0114
+
+#define mmNIC0_QM0_CQ_CFG0_2                                         0xCE0118
+
+#define mmNIC0_QM0_CQ_CFG0_3                                         0xCE011C
+
+#define mmNIC0_QM0_CQ_CFG0_4                                         0xCE0120
+
+#define mmNIC0_QM0_CQ_CFG1_0                                         0xCE0124
+
+#define mmNIC0_QM0_CQ_CFG1_1                                         0xCE0128
+
+#define mmNIC0_QM0_CQ_CFG1_2                                         0xCE012C
+
+#define mmNIC0_QM0_CQ_CFG1_3                                         0xCE0130
+
+#define mmNIC0_QM0_CQ_CFG1_4                                         0xCE0134
+
+#define mmNIC0_QM0_CQ_ARUSER_31_11_0                                 0xCE0138
+
+#define mmNIC0_QM0_CQ_ARUSER_31_11_1                                 0xCE013C
+
+#define mmNIC0_QM0_CQ_ARUSER_31_11_2                                 0xCE0140
+
+#define mmNIC0_QM0_CQ_ARUSER_31_11_3                                 0xCE0144
+
+#define mmNIC0_QM0_CQ_ARUSER_31_11_4                                 0xCE0148
+
+#define mmNIC0_QM0_CQ_STS0_0                                         0xCE014C
+
+#define mmNIC0_QM0_CQ_STS0_1                                         0xCE0150
+
+#define mmNIC0_QM0_CQ_STS0_2                                         0xCE0154
+
+#define mmNIC0_QM0_CQ_STS0_3                                         0xCE0158
+
+#define mmNIC0_QM0_CQ_STS0_4                                         0xCE015C
+
+#define mmNIC0_QM0_CQ_STS1_0                                         0xCE0160
+
+#define mmNIC0_QM0_CQ_STS1_1                                         0xCE0164
+
+#define mmNIC0_QM0_CQ_STS1_2                                         0xCE0168
+
+#define mmNIC0_QM0_CQ_STS1_3                                         0xCE016C
+
+#define mmNIC0_QM0_CQ_STS1_4                                         0xCE0170
+
+#define mmNIC0_QM0_CQ_PTR_LO_0                                       0xCE0174
+
+#define mmNIC0_QM0_CQ_PTR_HI_0                                       0xCE0178
+
+#define mmNIC0_QM0_CQ_TSIZE_0                                        0xCE017C
+
+#define mmNIC0_QM0_CQ_CTL_0                                          0xCE0180
+
+#define mmNIC0_QM0_CQ_PTR_LO_1                                       0xCE0184
+
+#define mmNIC0_QM0_CQ_PTR_HI_1                                       0xCE0188
+
+#define mmNIC0_QM0_CQ_TSIZE_1                                        0xCE018C
+
+#define mmNIC0_QM0_CQ_CTL_1                                          0xCE0190
+
+#define mmNIC0_QM0_CQ_PTR_LO_2                                       0xCE0194
+
+#define mmNIC0_QM0_CQ_PTR_HI_2                                       0xCE0198
+
+#define mmNIC0_QM0_CQ_TSIZE_2                                        0xCE019C
+
+#define mmNIC0_QM0_CQ_CTL_2                                          0xCE01A0
+
+#define mmNIC0_QM0_CQ_PTR_LO_3                                       0xCE01A4
+
+#define mmNIC0_QM0_CQ_PTR_HI_3                                       0xCE01A8
+
+#define mmNIC0_QM0_CQ_TSIZE_3                                        0xCE01AC
+
+#define mmNIC0_QM0_CQ_CTL_3                                          0xCE01B0
+
+#define mmNIC0_QM0_CQ_PTR_LO_4                                       0xCE01B4
+
+#define mmNIC0_QM0_CQ_PTR_HI_4                                       0xCE01B8
+
+#define mmNIC0_QM0_CQ_TSIZE_4                                        0xCE01BC
+
+#define mmNIC0_QM0_CQ_CTL_4                                          0xCE01C0
+
+#define mmNIC0_QM0_CQ_PTR_LO_STS_0                                   0xCE01C4
+
+#define mmNIC0_QM0_CQ_PTR_LO_STS_1                                   0xCE01C8
+
+#define mmNIC0_QM0_CQ_PTR_LO_STS_2                                   0xCE01CC
+
+#define mmNIC0_QM0_CQ_PTR_LO_STS_3                                   0xCE01D0
+
+#define mmNIC0_QM0_CQ_PTR_LO_STS_4                                   0xCE01D4
+
+#define mmNIC0_QM0_CQ_PTR_HI_STS_0                                   0xCE01D8
+
+#define mmNIC0_QM0_CQ_PTR_HI_STS_1                                   0xCE01DC
+
+#define mmNIC0_QM0_CQ_PTR_HI_STS_2                                   0xCE01E0
+
+#define mmNIC0_QM0_CQ_PTR_HI_STS_3                                   0xCE01E4
+
+#define mmNIC0_QM0_CQ_PTR_HI_STS_4                                   0xCE01E8
+
+#define mmNIC0_QM0_CQ_TSIZE_STS_0                                    0xCE01EC
+
+#define mmNIC0_QM0_CQ_TSIZE_STS_1                                    0xCE01F0
+
+#define mmNIC0_QM0_CQ_TSIZE_STS_2                                    0xCE01F4
+
+#define mmNIC0_QM0_CQ_TSIZE_STS_3                                    0xCE01F8
+
+#define mmNIC0_QM0_CQ_TSIZE_STS_4                                    0xCE01FC
+
+#define mmNIC0_QM0_CQ_CTL_STS_0                                      0xCE0200
+
+#define mmNIC0_QM0_CQ_CTL_STS_1                                      0xCE0204
+
+#define mmNIC0_QM0_CQ_CTL_STS_2                                      0xCE0208
+
+#define mmNIC0_QM0_CQ_CTL_STS_3                                      0xCE020C
+
+#define mmNIC0_QM0_CQ_CTL_STS_4                                      0xCE0210
+
+#define mmNIC0_QM0_CQ_IFIFO_CNT_0                                    0xCE0214
+
+#define mmNIC0_QM0_CQ_IFIFO_CNT_1                                    0xCE0218
+
+#define mmNIC0_QM0_CQ_IFIFO_CNT_2                                    0xCE021C
+
+#define mmNIC0_QM0_CQ_IFIFO_CNT_3                                    0xCE0220
+
+#define mmNIC0_QM0_CQ_IFIFO_CNT_4                                    0xCE0224
+
+#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_0                            0xCE0228
+
+#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_1                            0xCE022C
+
+#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_2                            0xCE0230
+
+#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_3                            0xCE0234
+
+#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_4                            0xCE0238
+
+#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_0                            0xCE023C
+
+#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_1                            0xCE0240
+
+#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_2                            0xCE0244
+
+#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_3                            0xCE0248
+
+#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_4                            0xCE024C
+
+#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_0                            0xCE0250
+
+#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_1                            0xCE0254
+
+#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_2                            0xCE0258
+
+#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_3                            0xCE025C
+
+#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_4                            0xCE0260
+
+#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_0                            0xCE0264
+
+#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_1                            0xCE0268
+
+#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_2                            0xCE026C
+
+#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_3                            0xCE0270
+
+#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_4                            0xCE0274
+
+#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_0                            0xCE0278
+
+#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_1                            0xCE027C
+
+#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_2                            0xCE0280
+
+#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_3                            0xCE0284
+
+#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_4                            0xCE0288
+
+#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_0                            0xCE028C
+
+#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_1                            0xCE0290
+
+#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_2                            0xCE0294
+
+#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_3                            0xCE0298
+
+#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_4                            0xCE029C
+
+#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_0                            0xCE02A0
+
+#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_1                            0xCE02A4
+
+#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_2                            0xCE02A8
+
+#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_3                            0xCE02AC
+
+#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_4                            0xCE02B0
+
+#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_0                            0xCE02B4
+
+#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_1                            0xCE02B8
+
+#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_2                            0xCE02BC
+
+#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_3                            0xCE02C0
+
+#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_4                            0xCE02C4
+
+#define mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET_0                            0xCE02C8
+
+#define mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET_1                            0xCE02CC
+
+#define mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET_2                            0xCE02D0
+
+#define mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET_3                            0xCE02D4
+
+#define mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET_4                            0xCE02D8
+
+#define mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_0                      0xCE02E0
+
+#define mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_1                      0xCE02E4
+
+#define mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_2                      0xCE02E8
+
+#define mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_3                      0xCE02EC
+
+#define mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_4                      0xCE02F0
+
+#define mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_0                      0xCE02F4
+
+#define mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_1                      0xCE02F8
+
+#define mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_2                      0xCE02FC
+
+#define mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3                      0xCE0300
+
+#define mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_4                      0xCE0304
+
+#define mmNIC0_QM0_CP_FENCE0_RDATA_0                                 0xCE0308
+
+#define mmNIC0_QM0_CP_FENCE0_RDATA_1                                 0xCE030C
+
+#define mmNIC0_QM0_CP_FENCE0_RDATA_2                                 0xCE0310
+
+#define mmNIC0_QM0_CP_FENCE0_RDATA_3                                 0xCE0314
+
+#define mmNIC0_QM0_CP_FENCE0_RDATA_4                                 0xCE0318
+
+#define mmNIC0_QM0_CP_FENCE1_RDATA_0                                 0xCE031C
+
+#define mmNIC0_QM0_CP_FENCE1_RDATA_1                                 0xCE0320
+
+#define mmNIC0_QM0_CP_FENCE1_RDATA_2                                 0xCE0324
+
+#define mmNIC0_QM0_CP_FENCE1_RDATA_3                                 0xCE0328
+
+#define mmNIC0_QM0_CP_FENCE1_RDATA_4                                 0xCE032C
+
+#define mmNIC0_QM0_CP_FENCE2_RDATA_0                                 0xCE0330
+
+#define mmNIC0_QM0_CP_FENCE2_RDATA_1                                 0xCE0334
+
+#define mmNIC0_QM0_CP_FENCE2_RDATA_2                                 0xCE0338
+
+#define mmNIC0_QM0_CP_FENCE2_RDATA_3                                 0xCE033C
+
+#define mmNIC0_QM0_CP_FENCE2_RDATA_4                                 0xCE0340
+
+#define mmNIC0_QM0_CP_FENCE3_RDATA_0                                 0xCE0344
+
+#define mmNIC0_QM0_CP_FENCE3_RDATA_1                                 0xCE0348
+
+#define mmNIC0_QM0_CP_FENCE3_RDATA_2                                 0xCE034C
+
+#define mmNIC0_QM0_CP_FENCE3_RDATA_3                                 0xCE0350
+
+#define mmNIC0_QM0_CP_FENCE3_RDATA_4                                 0xCE0354
+
+#define mmNIC0_QM0_CP_FENCE0_CNT_0                                   0xCE0358
+
+#define mmNIC0_QM0_CP_FENCE0_CNT_1                                   0xCE035C
+
+#define mmNIC0_QM0_CP_FENCE0_CNT_2                                   0xCE0360
+
+#define mmNIC0_QM0_CP_FENCE0_CNT_3                                   0xCE0364
+
+#define mmNIC0_QM0_CP_FENCE0_CNT_4                                   0xCE0368
+
+#define mmNIC0_QM0_CP_FENCE1_CNT_0                                   0xCE036C
+
+#define mmNIC0_QM0_CP_FENCE1_CNT_1                                   0xCE0370
+
+#define mmNIC0_QM0_CP_FENCE1_CNT_2                                   0xCE0374
+
+#define mmNIC0_QM0_CP_FENCE1_CNT_3                                   0xCE0378
+
+#define mmNIC0_QM0_CP_FENCE1_CNT_4                                   0xCE037C
+
+#define mmNIC0_QM0_CP_FENCE2_CNT_0                                   0xCE0380
+
+#define mmNIC0_QM0_CP_FENCE2_CNT_1                                   0xCE0384
+
+#define mmNIC0_QM0_CP_FENCE2_CNT_2                                   0xCE0388
+
+#define mmNIC0_QM0_CP_FENCE2_CNT_3                                   0xCE038C
+
+#define mmNIC0_QM0_CP_FENCE2_CNT_4                                   0xCE0390
+
+#define mmNIC0_QM0_CP_FENCE3_CNT_0                                   0xCE0394
+
+#define mmNIC0_QM0_CP_FENCE3_CNT_1                                   0xCE0398
+
+#define mmNIC0_QM0_CP_FENCE3_CNT_2                                   0xCE039C
+
+#define mmNIC0_QM0_CP_FENCE3_CNT_3                                   0xCE03A0
+
+#define mmNIC0_QM0_CP_FENCE3_CNT_4                                   0xCE03A4
+
+#define mmNIC0_QM0_CP_STS_0                                          0xCE03A8
+
+#define mmNIC0_QM0_CP_STS_1                                          0xCE03AC
+
+#define mmNIC0_QM0_CP_STS_2                                          0xCE03B0
+
+#define mmNIC0_QM0_CP_STS_3                                          0xCE03B4
+
+#define mmNIC0_QM0_CP_STS_4                                          0xCE03B8
+
+#define mmNIC0_QM0_CP_CURRENT_INST_LO_0                              0xCE03BC
+
+#define mmNIC0_QM0_CP_CURRENT_INST_LO_1                              0xCE03C0
+
+#define mmNIC0_QM0_CP_CURRENT_INST_LO_2                              0xCE03C4
+
+#define mmNIC0_QM0_CP_CURRENT_INST_LO_3                              0xCE03C8
+
+#define mmNIC0_QM0_CP_CURRENT_INST_LO_4                              0xCE03CC
+
+#define mmNIC0_QM0_CP_CURRENT_INST_HI_0                              0xCE03D0
+
+#define mmNIC0_QM0_CP_CURRENT_INST_HI_1                              0xCE03D4
+
+#define mmNIC0_QM0_CP_CURRENT_INST_HI_2                              0xCE03D8
+
+#define mmNIC0_QM0_CP_CURRENT_INST_HI_3                              0xCE03DC
+
+#define mmNIC0_QM0_CP_CURRENT_INST_HI_4                              0xCE03E0
+
+#define mmNIC0_QM0_CP_BARRIER_CFG_0                                  0xCE03F4
+
+#define mmNIC0_QM0_CP_BARRIER_CFG_1                                  0xCE03F8
+
+#define mmNIC0_QM0_CP_BARRIER_CFG_2                                  0xCE03FC
+
+#define mmNIC0_QM0_CP_BARRIER_CFG_3                                  0xCE0400
+
+#define mmNIC0_QM0_CP_BARRIER_CFG_4                                  0xCE0404
+
+#define mmNIC0_QM0_CP_DBG_0_0                                        0xCE0408
+
+#define mmNIC0_QM0_CP_DBG_0_1                                        0xCE040C
+
+#define mmNIC0_QM0_CP_DBG_0_2                                        0xCE0410
+
+#define mmNIC0_QM0_CP_DBG_0_3                                        0xCE0414
+
+#define mmNIC0_QM0_CP_DBG_0_4                                        0xCE0418
+
+#define mmNIC0_QM0_CP_ARUSER_31_11_0                                 0xCE041C
+
+#define mmNIC0_QM0_CP_ARUSER_31_11_1                                 0xCE0420
+
+#define mmNIC0_QM0_CP_ARUSER_31_11_2                                 0xCE0424
+
+#define mmNIC0_QM0_CP_ARUSER_31_11_3                                 0xCE0428
+
+#define mmNIC0_QM0_CP_ARUSER_31_11_4                                 0xCE042C
+
+#define mmNIC0_QM0_CP_AWUSER_31_11_0                                 0xCE0430
+
+#define mmNIC0_QM0_CP_AWUSER_31_11_1                                 0xCE0434
+
+#define mmNIC0_QM0_CP_AWUSER_31_11_2                                 0xCE0438
+
+#define mmNIC0_QM0_CP_AWUSER_31_11_3                                 0xCE043C
+
+#define mmNIC0_QM0_CP_AWUSER_31_11_4                                 0xCE0440
+
+#define mmNIC0_QM0_ARB_CFG_0                                         0xCE0A00
+
+#define mmNIC0_QM0_ARB_CHOISE_Q_PUSH                                 0xCE0A04
+
+#define mmNIC0_QM0_ARB_WRR_WEIGHT_0                                  0xCE0A08
+
+#define mmNIC0_QM0_ARB_WRR_WEIGHT_1                                  0xCE0A0C
+
+#define mmNIC0_QM0_ARB_WRR_WEIGHT_2                                  0xCE0A10
+
+#define mmNIC0_QM0_ARB_WRR_WEIGHT_3                                  0xCE0A14
+
+#define mmNIC0_QM0_ARB_CFG_1                                         0xCE0A18
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_0                              0xCE0A20
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_1                              0xCE0A24
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_2                              0xCE0A28
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_3                              0xCE0A2C
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_4                              0xCE0A30
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_5                              0xCE0A34
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_6                              0xCE0A38
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_7                              0xCE0A3C
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_8                              0xCE0A40
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_9                              0xCE0A44
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_10                             0xCE0A48
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_11                             0xCE0A4C
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_12                             0xCE0A50
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_13                             0xCE0A54
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_14                             0xCE0A58
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_15                             0xCE0A5C
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_16                             0xCE0A60
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_17                             0xCE0A64
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_18                             0xCE0A68
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_19                             0xCE0A6C
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_20                             0xCE0A70
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_21                             0xCE0A74
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_22                             0xCE0A78
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_23                             0xCE0A7C
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_24                             0xCE0A80
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_25                             0xCE0A84
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_26                             0xCE0A88
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_27                             0xCE0A8C
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_28                             0xCE0A90
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_29                             0xCE0A94
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_30                             0xCE0A98
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_31                             0xCE0A9C
+
+#define mmNIC0_QM0_ARB_MST_CRED_INC                                  0xCE0AA0
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_0                        0xCE0AA4
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_1                        0xCE0AA8
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_2                        0xCE0AAC
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_3                        0xCE0AB0
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_4                        0xCE0AB4
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_5                        0xCE0AB8
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_6                        0xCE0ABC
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_7                        0xCE0AC0
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_8                        0xCE0AC4
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_9                        0xCE0AC8
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_10                       0xCE0ACC
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_11                       0xCE0AD0
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_12                       0xCE0AD4
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_13                       0xCE0AD8
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_14                       0xCE0ADC
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_15                       0xCE0AE0
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_16                       0xCE0AE4
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_17                       0xCE0AE8
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_18                       0xCE0AEC
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_19                       0xCE0AF0
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_20                       0xCE0AF4
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_21                       0xCE0AF8
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_22                       0xCE0AFC
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_23                       0xCE0B00
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_24                       0xCE0B04
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_25                       0xCE0B08
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_26                       0xCE0B0C
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_27                       0xCE0B10
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_28                       0xCE0B14
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_29                       0xCE0B18
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_30                       0xCE0B1C
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_31                       0xCE0B20
+
+#define mmNIC0_QM0_ARB_SLV_MASTER_INC_CRED_OFST                      0xCE0B28
+
+#define mmNIC0_QM0_ARB_MST_SLAVE_EN                                  0xCE0B2C
+
+#define mmNIC0_QM0_ARB_MST_QUIET_PER                                 0xCE0B34
+
+#define mmNIC0_QM0_ARB_SLV_CHOISE_WDT                                0xCE0B38
+
+#define mmNIC0_QM0_ARB_SLV_ID                                        0xCE0B3C
+
+#define mmNIC0_QM0_ARB_MSG_MAX_INFLIGHT                              0xCE0B44
+
+#define mmNIC0_QM0_ARB_MSG_AWUSER_31_11                              0xCE0B48
+
+#define mmNIC0_QM0_ARB_MSG_AWUSER_SEC_PROP                           0xCE0B4C
+
+#define mmNIC0_QM0_ARB_MSG_AWUSER_NON_SEC_PROP                       0xCE0B50
+
+#define mmNIC0_QM0_ARB_BASE_LO                                       0xCE0B54
+
+#define mmNIC0_QM0_ARB_BASE_HI                                       0xCE0B58
+
+#define mmNIC0_QM0_ARB_STATE_STS                                     0xCE0B80
+
+#define mmNIC0_QM0_ARB_CHOISE_FULLNESS_STS                           0xCE0B84
+
+#define mmNIC0_QM0_ARB_MSG_STS                                       0xCE0B88
+
+#define mmNIC0_QM0_ARB_SLV_CHOISE_Q_HEAD                             0xCE0B8C
+
+#define mmNIC0_QM0_ARB_ERR_CAUSE                                     0xCE0B9C
+
+#define mmNIC0_QM0_ARB_ERR_MSG_EN                                    0xCE0BA0
+
+#define mmNIC0_QM0_ARB_ERR_STS_DRP                                   0xCE0BA8
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_0                                0xCE0BB0
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_1                                0xCE0BB4
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_2                                0xCE0BB8
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_3                                0xCE0BBC
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_4                                0xCE0BC0
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_5                                0xCE0BC4
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_6                                0xCE0BC8
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_7                                0xCE0BCC
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_8                                0xCE0BD0
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_9                                0xCE0BD4
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_10                               0xCE0BD8
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_11                               0xCE0BDC
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_12                               0xCE0BE0
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_13                               0xCE0BE4
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_14                               0xCE0BE8
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_15                               0xCE0BEC
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_16                               0xCE0BF0
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_17                               0xCE0BF4
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_18                               0xCE0BF8
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_19                               0xCE0BFC
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_20                               0xCE0C00
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_21                               0xCE0C04
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_22                               0xCE0C08
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_23                               0xCE0C0C
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_24                               0xCE0C10
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_25                               0xCE0C14
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_26                               0xCE0C18
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_27                               0xCE0C1C
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_28                               0xCE0C20
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_29                               0xCE0C24
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_30                               0xCE0C28
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_31                               0xCE0C2C
+
+#define mmNIC0_QM0_CGM_CFG                                           0xCE0C70
+
+#define mmNIC0_QM0_CGM_STS                                           0xCE0C74
+
+#define mmNIC0_QM0_CGM_CFG1                                          0xCE0C78
+
+#define mmNIC0_QM0_LOCAL_RANGE_BASE                                  0xCE0C80
+
+#define mmNIC0_QM0_LOCAL_RANGE_SIZE                                  0xCE0C84
+
+#define mmNIC0_QM0_CSMR_STRICT_PRIO_CFG                              0xCE0C90
+
+#define mmNIC0_QM0_HBW_RD_RATE_LIM_CFG_1                             0xCE0C94
+
+#define mmNIC0_QM0_LBW_WR_RATE_LIM_CFG_0                             0xCE0C98
+
+#define mmNIC0_QM0_LBW_WR_RATE_LIM_CFG_1                             0xCE0C9C
+
+#define mmNIC0_QM0_HBW_RD_RATE_LIM_CFG_0                             0xCE0CA0
+
+#define mmNIC0_QM0_GLBL_AXCACHE                                      0xCE0CA4
+
+#define mmNIC0_QM0_IND_GW_APB_CFG                                    0xCE0CB0
+
+#define mmNIC0_QM0_IND_GW_APB_WDATA                                  0xCE0CB4
+
+#define mmNIC0_QM0_IND_GW_APB_RDATA                                  0xCE0CB8
+
+#define mmNIC0_QM0_IND_GW_APB_STATUS                                 0xCE0CBC
+
+#define mmNIC0_QM0_GLBL_ERR_ADDR_LO                                  0xCE0CD0
+
+#define mmNIC0_QM0_GLBL_ERR_ADDR_HI                                  0xCE0CD4
+
+#define mmNIC0_QM0_GLBL_ERR_WDATA                                    0xCE0CD8
+
+#define mmNIC0_QM0_GLBL_MEM_INIT_BUSY                                0xCE0D00
+
+#endif /* ASIC_REG_NIC0_QM0_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/nic0_qm1_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic0_qm1_regs.h
new file mode 100644
index 000000000000..fe96c575b5c6
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic0_qm1_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_QM1_REGS_H_
+#define ASIC_REG_NIC0_QM1_REGS_H_
+
+/*
+ *****************************************
+ *   NIC0_QM1 (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmNIC0_QM1_GLBL_CFG0                                         0xCE2000
+
+#define mmNIC0_QM1_GLBL_CFG1                                         0xCE2004
+
+#define mmNIC0_QM1_GLBL_PROT                                         0xCE2008
+
+#define mmNIC0_QM1_GLBL_ERR_CFG                                      0xCE200C
+
+#define mmNIC0_QM1_GLBL_SECURE_PROPS_0                               0xCE2010
+
+#define mmNIC0_QM1_GLBL_SECURE_PROPS_1                               0xCE2014
+
+#define mmNIC0_QM1_GLBL_SECURE_PROPS_2                               0xCE2018
+
+#define mmNIC0_QM1_GLBL_SECURE_PROPS_3                               0xCE201C
+
+#define mmNIC0_QM1_GLBL_SECURE_PROPS_4                               0xCE2020
+
+#define mmNIC0_QM1_GLBL_NON_SECURE_PROPS_0                           0xCE2024
+
+#define mmNIC0_QM1_GLBL_NON_SECURE_PROPS_1                           0xCE2028
+
+#define mmNIC0_QM1_GLBL_NON_SECURE_PROPS_2                           0xCE202C
+
+#define mmNIC0_QM1_GLBL_NON_SECURE_PROPS_3                           0xCE2030
+
+#define mmNIC0_QM1_GLBL_NON_SECURE_PROPS_4                           0xCE2034
+
+#define mmNIC0_QM1_GLBL_STS0                                         0xCE2038
+
+#define mmNIC0_QM1_GLBL_STS1_0                                       0xCE2040
+
+#define mmNIC0_QM1_GLBL_STS1_1                                       0xCE2044
+
+#define mmNIC0_QM1_GLBL_STS1_2                                       0xCE2048
+
+#define mmNIC0_QM1_GLBL_STS1_3                                       0xCE204C
+
+#define mmNIC0_QM1_GLBL_STS1_4                                       0xCE2050
+
+#define mmNIC0_QM1_GLBL_MSG_EN_0                                     0xCE2054
+
+#define mmNIC0_QM1_GLBL_MSG_EN_1                                     0xCE2058
+
+#define mmNIC0_QM1_GLBL_MSG_EN_2                                     0xCE205C
+
+#define mmNIC0_QM1_GLBL_MSG_EN_3                                     0xCE2060
+
+#define mmNIC0_QM1_GLBL_MSG_EN_4                                     0xCE2068
+
+#define mmNIC0_QM1_PQ_BASE_LO_0                                      0xCE2070
+
+#define mmNIC0_QM1_PQ_BASE_LO_1                                      0xCE2074
+
+#define mmNIC0_QM1_PQ_BASE_LO_2                                      0xCE2078
+
+#define mmNIC0_QM1_PQ_BASE_LO_3                                      0xCE207C
+
+#define mmNIC0_QM1_PQ_BASE_HI_0                                      0xCE2080
+
+#define mmNIC0_QM1_PQ_BASE_HI_1                                      0xCE2084
+
+#define mmNIC0_QM1_PQ_BASE_HI_2                                      0xCE2088
+
+#define mmNIC0_QM1_PQ_BASE_HI_3                                      0xCE208C
+
+#define mmNIC0_QM1_PQ_SIZE_0                                         0xCE2090
+
+#define mmNIC0_QM1_PQ_SIZE_1                                         0xCE2094
+
+#define mmNIC0_QM1_PQ_SIZE_2                                         0xCE2098
+
+#define mmNIC0_QM1_PQ_SIZE_3                                         0xCE209C
+
+#define mmNIC0_QM1_PQ_PI_0                                           0xCE20A0
+
+#define mmNIC0_QM1_PQ_PI_1                                           0xCE20A4
+
+#define mmNIC0_QM1_PQ_PI_2                                           0xCE20A8
+
+#define mmNIC0_QM1_PQ_PI_3                                           0xCE20AC
+
+#define mmNIC0_QM1_PQ_CI_0                                           0xCE20B0
+
+#define mmNIC0_QM1_PQ_CI_1                                           0xCE20B4
+
+#define mmNIC0_QM1_PQ_CI_2                                           0xCE20B8
+
+#define mmNIC0_QM1_PQ_CI_3                                           0xCE20BC
+
+#define mmNIC0_QM1_PQ_CFG0_0                                         0xCE20C0
+
+#define mmNIC0_QM1_PQ_CFG0_1                                         0xCE20C4
+
+#define mmNIC0_QM1_PQ_CFG0_2                                         0xCE20C8
+
+#define mmNIC0_QM1_PQ_CFG0_3                                         0xCE20CC
+
+#define mmNIC0_QM1_PQ_CFG1_0                                         0xCE20D0
+
+#define mmNIC0_QM1_PQ_CFG1_1                                         0xCE20D4
+
+#define mmNIC0_QM1_PQ_CFG1_2                                         0xCE20D8
+
+#define mmNIC0_QM1_PQ_CFG1_3                                         0xCE20DC
+
+#define mmNIC0_QM1_PQ_ARUSER_31_11_0                                 0xCE20E0
+
+#define mmNIC0_QM1_PQ_ARUSER_31_11_1                                 0xCE20E4
+
+#define mmNIC0_QM1_PQ_ARUSER_31_11_2                                 0xCE20E8
+
+#define mmNIC0_QM1_PQ_ARUSER_31_11_3                                 0xCE20EC
+
+#define mmNIC0_QM1_PQ_STS0_0                                         0xCE20F0
+
+#define mmNIC0_QM1_PQ_STS0_1                                         0xCE20F4
+
+#define mmNIC0_QM1_PQ_STS0_2                                         0xCE20F8
+
+#define mmNIC0_QM1_PQ_STS0_3                                         0xCE20FC
+
+#define mmNIC0_QM1_PQ_STS1_0                                         0xCE2100
+
+#define mmNIC0_QM1_PQ_STS1_1                                         0xCE2104
+
+#define mmNIC0_QM1_PQ_STS1_2                                         0xCE2108
+
+#define mmNIC0_QM1_PQ_STS1_3                                         0xCE210C
+
+#define mmNIC0_QM1_CQ_CFG0_0                                         0xCE2110
+
+#define mmNIC0_QM1_CQ_CFG0_1                                         0xCE2114
+
+#define mmNIC0_QM1_CQ_CFG0_2                                         0xCE2118
+
+#define mmNIC0_QM1_CQ_CFG0_3                                         0xCE211C
+
+#define mmNIC0_QM1_CQ_CFG0_4                                         0xCE2120
+
+#define mmNIC0_QM1_CQ_CFG1_0                                         0xCE2124
+
+#define mmNIC0_QM1_CQ_CFG1_1                                         0xCE2128
+
+#define mmNIC0_QM1_CQ_CFG1_2                                         0xCE212C
+
+#define mmNIC0_QM1_CQ_CFG1_3                                         0xCE2130
+
+#define mmNIC0_QM1_CQ_CFG1_4                                         0xCE2134
+
+#define mmNIC0_QM1_CQ_ARUSER_31_11_0                                 0xCE2138
+
+#define mmNIC0_QM1_CQ_ARUSER_31_11_1                                 0xCE213C
+
+#define mmNIC0_QM1_CQ_ARUSER_31_11_2                                 0xCE2140
+
+#define mmNIC0_QM1_CQ_ARUSER_31_11_3                                 0xCE2144
+
+#define mmNIC0_QM1_CQ_ARUSER_31_11_4                                 0xCE2148
+
+#define mmNIC0_QM1_CQ_STS0_0                                         0xCE214C
+
+#define mmNIC0_QM1_CQ_STS0_1                                         0xCE2150
+
+#define mmNIC0_QM1_CQ_STS0_2                                         0xCE2154
+
+#define mmNIC0_QM1_CQ_STS0_3                                         0xCE2158
+
+#define mmNIC0_QM1_CQ_STS0_4                                         0xCE215C
+
+#define mmNIC0_QM1_CQ_STS1_0                                         0xCE2160
+
+#define mmNIC0_QM1_CQ_STS1_1                                         0xCE2164
+
+#define mmNIC0_QM1_CQ_STS1_2                                         0xCE2168
+
+#define mmNIC0_QM1_CQ_STS1_3                                         0xCE216C
+
+#define mmNIC0_QM1_CQ_STS1_4                                         0xCE2170
+
+#define mmNIC0_QM1_CQ_PTR_LO_0                                       0xCE2174
+
+#define mmNIC0_QM1_CQ_PTR_HI_0                                       0xCE2178
+
+#define mmNIC0_QM1_CQ_TSIZE_0                                        0xCE217C
+
+#define mmNIC0_QM1_CQ_CTL_0                                          0xCE2180
+
+#define mmNIC0_QM1_CQ_PTR_LO_1                                       0xCE2184
+
+#define mmNIC0_QM1_CQ_PTR_HI_1                                       0xCE2188
+
+#define mmNIC0_QM1_CQ_TSIZE_1                                        0xCE218C
+
+#define mmNIC0_QM1_CQ_CTL_1                                          0xCE2190
+
+#define mmNIC0_QM1_CQ_PTR_LO_2                                       0xCE2194
+
+#define mmNIC0_QM1_CQ_PTR_HI_2                                       0xCE2198
+
+#define mmNIC0_QM1_CQ_TSIZE_2                                        0xCE219C
+
+#define mmNIC0_QM1_CQ_CTL_2                                          0xCE21A0
+
+#define mmNIC0_QM1_CQ_PTR_LO_3                                       0xCE21A4
+
+#define mmNIC0_QM1_CQ_PTR_HI_3                                       0xCE21A8
+
+#define mmNIC0_QM1_CQ_TSIZE_3                                        0xCE21AC
+
+#define mmNIC0_QM1_CQ_CTL_3                                          0xCE21B0
+
+#define mmNIC0_QM1_CQ_PTR_LO_4                                       0xCE21B4
+
+#define mmNIC0_QM1_CQ_PTR_HI_4                                       0xCE21B8
+
+#define mmNIC0_QM1_CQ_TSIZE_4                                        0xCE21BC
+
+#define mmNIC0_QM1_CQ_CTL_4                                          0xCE21C0
+
+#define mmNIC0_QM1_CQ_PTR_LO_STS_0                                   0xCE21C4
+
+#define mmNIC0_QM1_CQ_PTR_LO_STS_1                                   0xCE21C8
+
+#define mmNIC0_QM1_CQ_PTR_LO_STS_2                                   0xCE21CC
+
+#define mmNIC0_QM1_CQ_PTR_LO_STS_3                                   0xCE21D0
+
+#define mmNIC0_QM1_CQ_PTR_LO_STS_4                                   0xCE21D4
+
+#define mmNIC0_QM1_CQ_PTR_HI_STS_0                                   0xCE21D8
+
+#define mmNIC0_QM1_CQ_PTR_HI_STS_1                                   0xCE21DC
+
+#define mmNIC0_QM1_CQ_PTR_HI_STS_2                                   0xCE21E0
+
+#define mmNIC0_QM1_CQ_PTR_HI_STS_3                                   0xCE21E4
+
+#define mmNIC0_QM1_CQ_PTR_HI_STS_4                                   0xCE21E8
+
+#define mmNIC0_QM1_CQ_TSIZE_STS_0                                    0xCE21EC
+
+#define mmNIC0_QM1_CQ_TSIZE_STS_1                                    0xCE21F0
+
+#define mmNIC0_QM1_CQ_TSIZE_STS_2                                    0xCE21F4
+
+#define mmNIC0_QM1_CQ_TSIZE_STS_3                                    0xCE21F8
+
+#define mmNIC0_QM1_CQ_TSIZE_STS_4                                    0xCE21FC
+
+#define mmNIC0_QM1_CQ_CTL_STS_0                                      0xCE2200
+
+#define mmNIC0_QM1_CQ_CTL_STS_1                                      0xCE2204
+
+#define mmNIC0_QM1_CQ_CTL_STS_2                                      0xCE2208
+
+#define mmNIC0_QM1_CQ_CTL_STS_3                                      0xCE220C
+
+#define mmNIC0_QM1_CQ_CTL_STS_4                                      0xCE2210
+
+#define mmNIC0_QM1_CQ_IFIFO_CNT_0                                    0xCE2214
+
+#define mmNIC0_QM1_CQ_IFIFO_CNT_1                                    0xCE2218
+
+#define mmNIC0_QM1_CQ_IFIFO_CNT_2                                    0xCE221C
+
+#define mmNIC0_QM1_CQ_IFIFO_CNT_3                                    0xCE2220
+
+#define mmNIC0_QM1_CQ_IFIFO_CNT_4                                    0xCE2224
+
+#define mmNIC0_QM1_CP_MSG_BASE0_ADDR_LO_0                            0xCE2228
+
+#define mmNIC0_QM1_CP_MSG_BASE0_ADDR_LO_1                            0xCE222C
+
+#define mmNIC0_QM1_CP_MSG_BASE0_ADDR_LO_2                            0xCE2230
+
+#define mmNIC0_QM1_CP_MSG_BASE0_ADDR_LO_3                            0xCE2234
+
+#define mmNIC0_QM1_CP_MSG_BASE0_ADDR_LO_4                            0xCE2238
+
+#define mmNIC0_QM1_CP_MSG_BASE0_ADDR_HI_0                            0xCE223C
+
+#define mmNIC0_QM1_CP_MSG_BASE0_ADDR_HI_1                            0xCE2240
+
+#define mmNIC0_QM1_CP_MSG_BASE0_ADDR_HI_2                            0xCE2244
+
+#define mmNIC0_QM1_CP_MSG_BASE0_ADDR_HI_3                            0xCE2248
+
+#define mmNIC0_QM1_CP_MSG_BASE0_ADDR_HI_4                            0xCE224C
+
+#define mmNIC0_QM1_CP_MSG_BASE1_ADDR_LO_0                            0xCE2250
+
+#define mmNIC0_QM1_CP_MSG_BASE1_ADDR_LO_1                            0xCE2254
+
+#define mmNIC0_QM1_CP_MSG_BASE1_ADDR_LO_2                            0xCE2258
+
+#define mmNIC0_QM1_CP_MSG_BASE1_ADDR_LO_3                            0xCE225C
+
+#define mmNIC0_QM1_CP_MSG_BASE1_ADDR_LO_4                            0xCE2260
+
+#define mmNIC0_QM1_CP_MSG_BASE1_ADDR_HI_0                            0xCE2264
+
+#define mmNIC0_QM1_CP_MSG_BASE1_ADDR_HI_1                            0xCE2268
+
+#define mmNIC0_QM1_CP_MSG_BASE1_ADDR_HI_2                            0xCE226C
+
+#define mmNIC0_QM1_CP_MSG_BASE1_ADDR_HI_3                            0xCE2270
+
+#define mmNIC0_QM1_CP_MSG_BASE1_ADDR_HI_4                            0xCE2274
+
+#define mmNIC0_QM1_CP_MSG_BASE2_ADDR_LO_0                            0xCE2278
+
+#define mmNIC0_QM1_CP_MSG_BASE2_ADDR_LO_1                            0xCE227C
+
+#define mmNIC0_QM1_CP_MSG_BASE2_ADDR_LO_2                            0xCE2280
+
+#define mmNIC0_QM1_CP_MSG_BASE2_ADDR_LO_3                            0xCE2284
+
+#define mmNIC0_QM1_CP_MSG_BASE2_ADDR_LO_4                            0xCE2288
+
+#define mmNIC0_QM1_CP_MSG_BASE2_ADDR_HI_0                            0xCE228C
+
+#define mmNIC0_QM1_CP_MSG_BASE2_ADDR_HI_1                            0xCE2290
+
+#define mmNIC0_QM1_CP_MSG_BASE2_ADDR_HI_2                            0xCE2294
+
+#define mmNIC0_QM1_CP_MSG_BASE2_ADDR_HI_3                            0xCE2298
+
+#define mmNIC0_QM1_CP_MSG_BASE2_ADDR_HI_4                            0xCE229C
+
+#define mmNIC0_QM1_CP_MSG_BASE3_ADDR_LO_0                            0xCE22A0
+
+#define mmNIC0_QM1_CP_MSG_BASE3_ADDR_LO_1                            0xCE22A4
+
+#define mmNIC0_QM1_CP_MSG_BASE3_ADDR_LO_2                            0xCE22A8
+
+#define mmNIC0_QM1_CP_MSG_BASE3_ADDR_LO_3                            0xCE22AC
+
+#define mmNIC0_QM1_CP_MSG_BASE3_ADDR_LO_4                            0xCE22B0
+
+#define mmNIC0_QM1_CP_MSG_BASE3_ADDR_HI_0                            0xCE22B4
+
+#define mmNIC0_QM1_CP_MSG_BASE3_ADDR_HI_1                            0xCE22B8
+
+#define mmNIC0_QM1_CP_MSG_BASE3_ADDR_HI_2                            0xCE22BC
+
+#define mmNIC0_QM1_CP_MSG_BASE3_ADDR_HI_3                            0xCE22C0
+
+#define mmNIC0_QM1_CP_MSG_BASE3_ADDR_HI_4                            0xCE22C4
+
+#define mmNIC0_QM1_CP_LDMA_TSIZE_OFFSET_0                            0xCE22C8
+
+#define mmNIC0_QM1_CP_LDMA_TSIZE_OFFSET_1                            0xCE22CC
+
+#define mmNIC0_QM1_CP_LDMA_TSIZE_OFFSET_2                            0xCE22D0
+
+#define mmNIC0_QM1_CP_LDMA_TSIZE_OFFSET_3                            0xCE22D4
+
+#define mmNIC0_QM1_CP_LDMA_TSIZE_OFFSET_4                            0xCE22D8
+
+#define mmNIC0_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_0                      0xCE22E0
+
+#define mmNIC0_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_1                      0xCE22E4
+
+#define mmNIC0_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_2                      0xCE22E8
+
+#define mmNIC0_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_3                      0xCE22EC
+
+#define mmNIC0_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_4                      0xCE22F0
+
+#define mmNIC0_QM1_CP_LDMA_DST_BASE_LO_OFFSET_0                      0xCE22F4
+
+#define mmNIC0_QM1_CP_LDMA_DST_BASE_LO_OFFSET_1                      0xCE22F8
+
+#define mmNIC0_QM1_CP_LDMA_DST_BASE_LO_OFFSET_2                      0xCE22FC
+
+#define mmNIC0_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3                      0xCE2300
+
+#define mmNIC0_QM1_CP_LDMA_DST_BASE_LO_OFFSET_4                      0xCE2304
+
+#define mmNIC0_QM1_CP_FENCE0_RDATA_0                                 0xCE2308
+
+#define mmNIC0_QM1_CP_FENCE0_RDATA_1                                 0xCE230C
+
+#define mmNIC0_QM1_CP_FENCE0_RDATA_2                                 0xCE2310
+
+#define mmNIC0_QM1_CP_FENCE0_RDATA_3                                 0xCE2314
+
+#define mmNIC0_QM1_CP_FENCE0_RDATA_4                                 0xCE2318
+
+#define mmNIC0_QM1_CP_FENCE1_RDATA_0                                 0xCE231C
+
+#define mmNIC0_QM1_CP_FENCE1_RDATA_1                                 0xCE2320
+
+#define mmNIC0_QM1_CP_FENCE1_RDATA_2                                 0xCE2324
+
+#define mmNIC0_QM1_CP_FENCE1_RDATA_3                                 0xCE2328
+
+#define mmNIC0_QM1_CP_FENCE1_RDATA_4                                 0xCE232C
+
+#define mmNIC0_QM1_CP_FENCE2_RDATA_0                                 0xCE2330
+
+#define mmNIC0_QM1_CP_FENCE2_RDATA_1                                 0xCE2334
+
+#define mmNIC0_QM1_CP_FENCE2_RDATA_2                                 0xCE2338
+
+#define mmNIC0_QM1_CP_FENCE2_RDATA_3                                 0xCE233C
+
+#define mmNIC0_QM1_CP_FENCE2_RDATA_4                                 0xCE2340
+
+#define mmNIC0_QM1_CP_FENCE3_RDATA_0                                 0xCE2344
+
+#define mmNIC0_QM1_CP_FENCE3_RDATA_1                                 0xCE2348
+
+#define mmNIC0_QM1_CP_FENCE3_RDATA_2                                 0xCE234C
+
+#define mmNIC0_QM1_CP_FENCE3_RDATA_3                                 0xCE2350
+
+#define mmNIC0_QM1_CP_FENCE3_RDATA_4                                 0xCE2354
+
+#define mmNIC0_QM1_CP_FENCE0_CNT_0                                   0xCE2358
+
+#define mmNIC0_QM1_CP_FENCE0_CNT_1                                   0xCE235C
+
+#define mmNIC0_QM1_CP_FENCE0_CNT_2                                   0xCE2360
+
+#define mmNIC0_QM1_CP_FENCE0_CNT_3                                   0xCE2364
+
+#define mmNIC0_QM1_CP_FENCE0_CNT_4                                   0xCE2368
+
+#define mmNIC0_QM1_CP_FENCE1_CNT_0                                   0xCE236C
+
+#define mmNIC0_QM1_CP_FENCE1_CNT_1                                   0xCE2370
+
+#define mmNIC0_QM1_CP_FENCE1_CNT_2                                   0xCE2374
+
+#define mmNIC0_QM1_CP_FENCE1_CNT_3                                   0xCE2378
+
+#define mmNIC0_QM1_CP_FENCE1_CNT_4                                   0xCE237C
+
+#define mmNIC0_QM1_CP_FENCE2_CNT_0                                   0xCE2380
+
+#define mmNIC0_QM1_CP_FENCE2_CNT_1                                   0xCE2384
+
+#define mmNIC0_QM1_CP_FENCE2_CNT_2                                   0xCE2388
+
+#define mmNIC0_QM1_CP_FENCE2_CNT_3                                   0xCE238C
+
+#define mmNIC0_QM1_CP_FENCE2_CNT_4                                   0xCE2390
+
+#define mmNIC0_QM1_CP_FENCE3_CNT_0                                   0xCE2394
+
+#define mmNIC0_QM1_CP_FENCE3_CNT_1                                   0xCE2398
+
+#define mmNIC0_QM1_CP_FENCE3_CNT_2                                   0xCE239C
+
+#define mmNIC0_QM1_CP_FENCE3_CNT_3                                   0xCE23A0
+
+#define mmNIC0_QM1_CP_FENCE3_CNT_4                                   0xCE23A4
+
+#define mmNIC0_QM1_CP_STS_0                                          0xCE23A8
+
+#define mmNIC0_QM1_CP_STS_1                                          0xCE23AC
+
+#define mmNIC0_QM1_CP_STS_2                                          0xCE23B0
+
+#define mmNIC0_QM1_CP_STS_3                                          0xCE23B4
+
+#define mmNIC0_QM1_CP_STS_4                                          0xCE23B8
+
+#define mmNIC0_QM1_CP_CURRENT_INST_LO_0                              0xCE23BC
+
+#define mmNIC0_QM1_CP_CURRENT_INST_LO_1                              0xCE23C0
+
+#define mmNIC0_QM1_CP_CURRENT_INST_LO_2                              0xCE23C4
+
+#define mmNIC0_QM1_CP_CURRENT_INST_LO_3                              0xCE23C8
+
+#define mmNIC0_QM1_CP_CURRENT_INST_LO_4                              0xCE23CC
+
+#define mmNIC0_QM1_CP_CURRENT_INST_HI_0                              0xCE23D0
+
+#define mmNIC0_QM1_CP_CURRENT_INST_HI_1                              0xCE23D4
+
+#define mmNIC0_QM1_CP_CURRENT_INST_HI_2                              0xCE23D8
+
+#define mmNIC0_QM1_CP_CURRENT_INST_HI_3                              0xCE23DC
+
+#define mmNIC0_QM1_CP_CURRENT_INST_HI_4                              0xCE23E0
+
+#define mmNIC0_QM1_CP_BARRIER_CFG_0                                  0xCE23F4
+
+#define mmNIC0_QM1_CP_BARRIER_CFG_1                                  0xCE23F8
+
+#define mmNIC0_QM1_CP_BARRIER_CFG_2                                  0xCE23FC
+
+#define mmNIC0_QM1_CP_BARRIER_CFG_3                                  0xCE2400
+
+#define mmNIC0_QM1_CP_BARRIER_CFG_4                                  0xCE2404
+
+#define mmNIC0_QM1_CP_DBG_0_0                                        0xCE2408
+
+#define mmNIC0_QM1_CP_DBG_0_1                                        0xCE240C
+
+#define mmNIC0_QM1_CP_DBG_0_2                                        0xCE2410
+
+#define mmNIC0_QM1_CP_DBG_0_3                                        0xCE2414
+
+#define mmNIC0_QM1_CP_DBG_0_4                                        0xCE2418
+
+#define mmNIC0_QM1_CP_ARUSER_31_11_0                                 0xCE241C
+
+#define mmNIC0_QM1_CP_ARUSER_31_11_1                                 0xCE2420
+
+#define mmNIC0_QM1_CP_ARUSER_31_11_2                                 0xCE2424
+
+#define mmNIC0_QM1_CP_ARUSER_31_11_3                                 0xCE2428
+
+#define mmNIC0_QM1_CP_ARUSER_31_11_4                                 0xCE242C
+
+#define mmNIC0_QM1_CP_AWUSER_31_11_0                                 0xCE2430
+
+#define mmNIC0_QM1_CP_AWUSER_31_11_1                                 0xCE2434
+
+#define mmNIC0_QM1_CP_AWUSER_31_11_2                                 0xCE2438
+
+#define mmNIC0_QM1_CP_AWUSER_31_11_3                                 0xCE243C
+
+#define mmNIC0_QM1_CP_AWUSER_31_11_4                                 0xCE2440
+
+#define mmNIC0_QM1_ARB_CFG_0                                         0xCE2A00
+
+#define mmNIC0_QM1_ARB_CHOISE_Q_PUSH                                 0xCE2A04
+
+#define mmNIC0_QM1_ARB_WRR_WEIGHT_0                                  0xCE2A08
+
+#define mmNIC0_QM1_ARB_WRR_WEIGHT_1                                  0xCE2A0C
+
+#define mmNIC0_QM1_ARB_WRR_WEIGHT_2                                  0xCE2A10
+
+#define mmNIC0_QM1_ARB_WRR_WEIGHT_3                                  0xCE2A14
+
+#define mmNIC0_QM1_ARB_CFG_1                                         0xCE2A18
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_0                              0xCE2A20
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_1                              0xCE2A24
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_2                              0xCE2A28
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_3                              0xCE2A2C
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_4                              0xCE2A30
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_5                              0xCE2A34
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_6                              0xCE2A38
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_7                              0xCE2A3C
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_8                              0xCE2A40
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_9                              0xCE2A44
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_10                             0xCE2A48
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_11                             0xCE2A4C
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_12                             0xCE2A50
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_13                             0xCE2A54
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_14                             0xCE2A58
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_15                             0xCE2A5C
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_16                             0xCE2A60
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_17                             0xCE2A64
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_18                             0xCE2A68
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_19                             0xCE2A6C
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_20                             0xCE2A70
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_21                             0xCE2A74
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_22                             0xCE2A78
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_23                             0xCE2A7C
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_24                             0xCE2A80
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_25                             0xCE2A84
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_26                             0xCE2A88
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_27                             0xCE2A8C
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_28                             0xCE2A90
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_29                             0xCE2A94
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_30                             0xCE2A98
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_31                             0xCE2A9C
+
+#define mmNIC0_QM1_ARB_MST_CRED_INC                                  0xCE2AA0
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_0                        0xCE2AA4
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_1                        0xCE2AA8
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_2                        0xCE2AAC
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_3                        0xCE2AB0
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_4                        0xCE2AB4
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_5                        0xCE2AB8
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_6                        0xCE2ABC
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_7                        0xCE2AC0
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_8                        0xCE2AC4
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_9                        0xCE2AC8
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_10                       0xCE2ACC
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_11                       0xCE2AD0
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_12                       0xCE2AD4
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_13                       0xCE2AD8
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_14                       0xCE2ADC
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_15                       0xCE2AE0
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_16                       0xCE2AE4
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_17                       0xCE2AE8
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_18                       0xCE2AEC
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_19                       0xCE2AF0
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_20                       0xCE2AF4
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_21                       0xCE2AF8
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_22                       0xCE2AFC
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_23                       0xCE2B00
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_24                       0xCE2B04
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_25                       0xCE2B08
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_26                       0xCE2B0C
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_27                       0xCE2B10
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_28                       0xCE2B14
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_29                       0xCE2B18
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_30                       0xCE2B1C
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_31                       0xCE2B20
+
+#define mmNIC0_QM1_ARB_SLV_MASTER_INC_CRED_OFST                      0xCE2B28
+
+#define mmNIC0_QM1_ARB_MST_SLAVE_EN                                  0xCE2B2C
+
+#define mmNIC0_QM1_ARB_MST_QUIET_PER                                 0xCE2B34
+
+#define mmNIC0_QM1_ARB_SLV_CHOISE_WDT                                0xCE2B38
+
+#define mmNIC0_QM1_ARB_SLV_ID                                        0xCE2B3C
+
+#define mmNIC0_QM1_ARB_MSG_MAX_INFLIGHT                              0xCE2B44
+
+#define mmNIC0_QM1_ARB_MSG_AWUSER_31_11                              0xCE2B48
+
+#define mmNIC0_QM1_ARB_MSG_AWUSER_SEC_PROP                           0xCE2B4C
+
+#define mmNIC0_QM1_ARB_MSG_AWUSER_NON_SEC_PROP                       0xCE2B50
+
+#define mmNIC0_QM1_ARB_BASE_LO                                       0xCE2B54
+
+#define mmNIC0_QM1_ARB_BASE_HI                                       0xCE2B58
+
+#define mmNIC0_QM1_ARB_STATE_STS                                     0xCE2B80
+
+#define mmNIC0_QM1_ARB_CHOISE_FULLNESS_STS                           0xCE2B84
+
+#define mmNIC0_QM1_ARB_MSG_STS                                       0xCE2B88
+
+#define mmNIC0_QM1_ARB_SLV_CHOISE_Q_HEAD                             0xCE2B8C
+
+#define mmNIC0_QM1_ARB_ERR_CAUSE                                     0xCE2B9C
+
+#define mmNIC0_QM1_ARB_ERR_MSG_EN                                    0xCE2BA0
+
+#define mmNIC0_QM1_ARB_ERR_STS_DRP                                   0xCE2BA8
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_0                                0xCE2BB0
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_1                                0xCE2BB4
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_2                                0xCE2BB8
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_3                                0xCE2BBC
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_4                                0xCE2BC0
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_5                                0xCE2BC4
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_6                                0xCE2BC8
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_7                                0xCE2BCC
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_8                                0xCE2BD0
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_9                                0xCE2BD4
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_10                               0xCE2BD8
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_11                               0xCE2BDC
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_12                               0xCE2BE0
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_13                               0xCE2BE4
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_14                               0xCE2BE8
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_15                               0xCE2BEC
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_16                               0xCE2BF0
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_17                               0xCE2BF4
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_18                               0xCE2BF8
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_19                               0xCE2BFC
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_20                               0xCE2C00
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_21                               0xCE2C04
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_22                               0xCE2C08
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_23                               0xCE2C0C
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_24                               0xCE2C10
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_25                               0xCE2C14
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_26                               0xCE2C18
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_27                               0xCE2C1C
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_28                               0xCE2C20
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_29                               0xCE2C24
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_30                               0xCE2C28
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_31                               0xCE2C2C
+
+#define mmNIC0_QM1_CGM_CFG                                           0xCE2C70
+
+#define mmNIC0_QM1_CGM_STS                                           0xCE2C74
+
+#define mmNIC0_QM1_CGM_CFG1                                          0xCE2C78
+
+#define mmNIC0_QM1_LOCAL_RANGE_BASE                                  0xCE2C80
+
+#define mmNIC0_QM1_LOCAL_RANGE_SIZE                                  0xCE2C84
+
+#define mmNIC0_QM1_CSMR_STRICT_PRIO_CFG                              0xCE2C90
+
+#define mmNIC0_QM1_HBW_RD_RATE_LIM_CFG_1                             0xCE2C94
+
+#define mmNIC0_QM1_LBW_WR_RATE_LIM_CFG_0                             0xCE2C98
+
+#define mmNIC0_QM1_LBW_WR_RATE_LIM_CFG_1                             0xCE2C9C
+
+#define mmNIC0_QM1_HBW_RD_RATE_LIM_CFG_0                             0xCE2CA0
+
+#define mmNIC0_QM1_GLBL_AXCACHE                                      0xCE2CA4
+
+#define mmNIC0_QM1_IND_GW_APB_CFG                                    0xCE2CB0
+
+#define mmNIC0_QM1_IND_GW_APB_WDATA                                  0xCE2CB4
+
+#define mmNIC0_QM1_IND_GW_APB_RDATA                                  0xCE2CB8
+
+#define mmNIC0_QM1_IND_GW_APB_STATUS                                 0xCE2CBC
+
+#define mmNIC0_QM1_GLBL_ERR_ADDR_LO                                  0xCE2CD0
+
+#define mmNIC0_QM1_GLBL_ERR_ADDR_HI                                  0xCE2CD4
+
+#define mmNIC0_QM1_GLBL_ERR_WDATA                                    0xCE2CD8
+
+#define mmNIC0_QM1_GLBL_MEM_INIT_BUSY                                0xCE2D00
+
+#endif /* ASIC_REG_NIC0_QM1_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/nic1_qm0_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic1_qm0_regs.h
new file mode 100644
index 000000000000..0d1caf057ad0
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic1_qm0_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_NIC1_QM0_REGS_H_
+#define ASIC_REG_NIC1_QM0_REGS_H_
+
+/*
+ *****************************************
+ *   NIC1_QM0 (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmNIC1_QM0_GLBL_CFG0                                         0xD20000
+
+#define mmNIC1_QM0_GLBL_CFG1                                         0xD20004
+
+#define mmNIC1_QM0_GLBL_PROT                                         0xD20008
+
+#define mmNIC1_QM0_GLBL_ERR_CFG                                      0xD2000C
+
+#define mmNIC1_QM0_GLBL_SECURE_PROPS_0                               0xD20010
+
+#define mmNIC1_QM0_GLBL_SECURE_PROPS_1                               0xD20014
+
+#define mmNIC1_QM0_GLBL_SECURE_PROPS_2                               0xD20018
+
+#define mmNIC1_QM0_GLBL_SECURE_PROPS_3                               0xD2001C
+
+#define mmNIC1_QM0_GLBL_SECURE_PROPS_4                               0xD20020
+
+#define mmNIC1_QM0_GLBL_NON_SECURE_PROPS_0                           0xD20024
+
+#define mmNIC1_QM0_GLBL_NON_SECURE_PROPS_1                           0xD20028
+
+#define mmNIC1_QM0_GLBL_NON_SECURE_PROPS_2                           0xD2002C
+
+#define mmNIC1_QM0_GLBL_NON_SECURE_PROPS_3                           0xD20030
+
+#define mmNIC1_QM0_GLBL_NON_SECURE_PROPS_4                           0xD20034
+
+#define mmNIC1_QM0_GLBL_STS0                                         0xD20038
+
+#define mmNIC1_QM0_GLBL_STS1_0                                       0xD20040
+
+#define mmNIC1_QM0_GLBL_STS1_1                                       0xD20044
+
+#define mmNIC1_QM0_GLBL_STS1_2                                       0xD20048
+
+#define mmNIC1_QM0_GLBL_STS1_3                                       0xD2004C
+
+#define mmNIC1_QM0_GLBL_STS1_4                                       0xD20050
+
+#define mmNIC1_QM0_GLBL_MSG_EN_0                                     0xD20054
+
+#define mmNIC1_QM0_GLBL_MSG_EN_1                                     0xD20058
+
+#define mmNIC1_QM0_GLBL_MSG_EN_2                                     0xD2005C
+
+#define mmNIC1_QM0_GLBL_MSG_EN_3                                     0xD20060
+
+#define mmNIC1_QM0_GLBL_MSG_EN_4                                     0xD20068
+
+#define mmNIC1_QM0_PQ_BASE_LO_0                                      0xD20070
+
+#define mmNIC1_QM0_PQ_BASE_LO_1                                      0xD20074
+
+#define mmNIC1_QM0_PQ_BASE_LO_2                                      0xD20078
+
+#define mmNIC1_QM0_PQ_BASE_LO_3                                      0xD2007C
+
+#define mmNIC1_QM0_PQ_BASE_HI_0                                      0xD20080
+
+#define mmNIC1_QM0_PQ_BASE_HI_1                                      0xD20084
+
+#define mmNIC1_QM0_PQ_BASE_HI_2                                      0xD20088
+
+#define mmNIC1_QM0_PQ_BASE_HI_3                                      0xD2008C
+
+#define mmNIC1_QM0_PQ_SIZE_0                                         0xD20090
+
+#define mmNIC1_QM0_PQ_SIZE_1                                         0xD20094
+
+#define mmNIC1_QM0_PQ_SIZE_2                                         0xD20098
+
+#define mmNIC1_QM0_PQ_SIZE_3                                         0xD2009C
+
+#define mmNIC1_QM0_PQ_PI_0                                           0xD200A0
+
+#define mmNIC1_QM0_PQ_PI_1                                           0xD200A4
+
+#define mmNIC1_QM0_PQ_PI_2                                           0xD200A8
+
+#define mmNIC1_QM0_PQ_PI_3                                           0xD200AC
+
+#define mmNIC1_QM0_PQ_CI_0                                           0xD200B0
+
+#define mmNIC1_QM0_PQ_CI_1                                           0xD200B4
+
+#define mmNIC1_QM0_PQ_CI_2                                           0xD200B8
+
+#define mmNIC1_QM0_PQ_CI_3                                           0xD200BC
+
+#define mmNIC1_QM0_PQ_CFG0_0                                         0xD200C0
+
+#define mmNIC1_QM0_PQ_CFG0_1                                         0xD200C4
+
+#define mmNIC1_QM0_PQ_CFG0_2                                         0xD200C8
+
+#define mmNIC1_QM0_PQ_CFG0_3                                         0xD200CC
+
+#define mmNIC1_QM0_PQ_CFG1_0                                         0xD200D0
+
+#define mmNIC1_QM0_PQ_CFG1_1                                         0xD200D4
+
+#define mmNIC1_QM0_PQ_CFG1_2                                         0xD200D8
+
+#define mmNIC1_QM0_PQ_CFG1_3                                         0xD200DC
+
+#define mmNIC1_QM0_PQ_ARUSER_31_11_0                                 0xD200E0
+
+#define mmNIC1_QM0_PQ_ARUSER_31_11_1                                 0xD200E4
+
+#define mmNIC1_QM0_PQ_ARUSER_31_11_2                                 0xD200E8
+
+#define mmNIC1_QM0_PQ_ARUSER_31_11_3                                 0xD200EC
+
+#define mmNIC1_QM0_PQ_STS0_0                                         0xD200F0
+
+#define mmNIC1_QM0_PQ_STS0_1                                         0xD200F4
+
+#define mmNIC1_QM0_PQ_STS0_2                                         0xD200F8
+
+#define mmNIC1_QM0_PQ_STS0_3                                         0xD200FC
+
+#define mmNIC1_QM0_PQ_STS1_0                                         0xD20100
+
+#define mmNIC1_QM0_PQ_STS1_1                                         0xD20104
+
+#define mmNIC1_QM0_PQ_STS1_2                                         0xD20108
+
+#define mmNIC1_QM0_PQ_STS1_3                                         0xD2010C
+
+#define mmNIC1_QM0_CQ_CFG0_0                                         0xD20110
+
+#define mmNIC1_QM0_CQ_CFG0_1                                         0xD20114
+
+#define mmNIC1_QM0_CQ_CFG0_2                                         0xD20118
+
+#define mmNIC1_QM0_CQ_CFG0_3                                         0xD2011C
+
+#define mmNIC1_QM0_CQ_CFG0_4                                         0xD20120
+
+#define mmNIC1_QM0_CQ_CFG1_0                                         0xD20124
+
+#define mmNIC1_QM0_CQ_CFG1_1                                         0xD20128
+
+#define mmNIC1_QM0_CQ_CFG1_2                                         0xD2012C
+
+#define mmNIC1_QM0_CQ_CFG1_3                                         0xD20130
+
+#define mmNIC1_QM0_CQ_CFG1_4                                         0xD20134
+
+#define mmNIC1_QM0_CQ_ARUSER_31_11_0                                 0xD20138
+
+#define mmNIC1_QM0_CQ_ARUSER_31_11_1                                 0xD2013C
+
+#define mmNIC1_QM0_CQ_ARUSER_31_11_2                                 0xD20140
+
+#define mmNIC1_QM0_CQ_ARUSER_31_11_3                                 0xD20144
+
+#define mmNIC1_QM0_CQ_ARUSER_31_11_4                                 0xD20148
+
+#define mmNIC1_QM0_CQ_STS0_0                                         0xD2014C
+
+#define mmNIC1_QM0_CQ_STS0_1                                         0xD20150
+
+#define mmNIC1_QM0_CQ_STS0_2                                         0xD20154
+
+#define mmNIC1_QM0_CQ_STS0_3                                         0xD20158
+
+#define mmNIC1_QM0_CQ_STS0_4                                         0xD2015C
+
+#define mmNIC1_QM0_CQ_STS1_0                                         0xD20160
+
+#define mmNIC1_QM0_CQ_STS1_1                                         0xD20164
+
+#define mmNIC1_QM0_CQ_STS1_2                                         0xD20168
+
+#define mmNIC1_QM0_CQ_STS1_3                                         0xD2016C
+
+#define mmNIC1_QM0_CQ_STS1_4                                         0xD20170
+
+#define mmNIC1_QM0_CQ_PTR_LO_0                                       0xD20174
+
+#define mmNIC1_QM0_CQ_PTR_HI_0                                       0xD20178
+
+#define mmNIC1_QM0_CQ_TSIZE_0                                        0xD2017C
+
+#define mmNIC1_QM0_CQ_CTL_0                                          0xD20180
+
+#define mmNIC1_QM0_CQ_PTR_LO_1                                       0xD20184
+
+#define mmNIC1_QM0_CQ_PTR_HI_1                                       0xD20188
+
+#define mmNIC1_QM0_CQ_TSIZE_1                                        0xD2018C
+
+#define mmNIC1_QM0_CQ_CTL_1                                          0xD20190
+
+#define mmNIC1_QM0_CQ_PTR_LO_2                                       0xD20194
+
+#define mmNIC1_QM0_CQ_PTR_HI_2                                       0xD20198
+
+#define mmNIC1_QM0_CQ_TSIZE_2                                        0xD2019C
+
+#define mmNIC1_QM0_CQ_CTL_2                                          0xD201A0
+
+#define mmNIC1_QM0_CQ_PTR_LO_3                                       0xD201A4
+
+#define mmNIC1_QM0_CQ_PTR_HI_3                                       0xD201A8
+
+#define mmNIC1_QM0_CQ_TSIZE_3                                        0xD201AC
+
+#define mmNIC1_QM0_CQ_CTL_3                                          0xD201B0
+
+#define mmNIC1_QM0_CQ_PTR_LO_4                                       0xD201B4
+
+#define mmNIC1_QM0_CQ_PTR_HI_4                                       0xD201B8
+
+#define mmNIC1_QM0_CQ_TSIZE_4                                        0xD201BC
+
+#define mmNIC1_QM0_CQ_CTL_4                                          0xD201C0
+
+#define mmNIC1_QM0_CQ_PTR_LO_STS_0                                   0xD201C4
+
+#define mmNIC1_QM0_CQ_PTR_LO_STS_1                                   0xD201C8
+
+#define mmNIC1_QM0_CQ_PTR_LO_STS_2                                   0xD201CC
+
+#define mmNIC1_QM0_CQ_PTR_LO_STS_3                                   0xD201D0
+
+#define mmNIC1_QM0_CQ_PTR_LO_STS_4                                   0xD201D4
+
+#define mmNIC1_QM0_CQ_PTR_HI_STS_0                                   0xD201D8
+
+#define mmNIC1_QM0_CQ_PTR_HI_STS_1                                   0xD201DC
+
+#define mmNIC1_QM0_CQ_PTR_HI_STS_2                                   0xD201E0
+
+#define mmNIC1_QM0_CQ_PTR_HI_STS_3                                   0xD201E4
+
+#define mmNIC1_QM0_CQ_PTR_HI_STS_4                                   0xD201E8
+
+#define mmNIC1_QM0_CQ_TSIZE_STS_0                                    0xD201EC
+
+#define mmNIC1_QM0_CQ_TSIZE_STS_1                                    0xD201F0
+
+#define mmNIC1_QM0_CQ_TSIZE_STS_2                                    0xD201F4
+
+#define mmNIC1_QM0_CQ_TSIZE_STS_3                                    0xD201F8
+
+#define mmNIC1_QM0_CQ_TSIZE_STS_4                                    0xD201FC
+
+#define mmNIC1_QM0_CQ_CTL_STS_0                                      0xD20200
+
+#define mmNIC1_QM0_CQ_CTL_STS_1                                      0xD20204
+
+#define mmNIC1_QM0_CQ_CTL_STS_2                                      0xD20208
+
+#define mmNIC1_QM0_CQ_CTL_STS_3                                      0xD2020C
+
+#define mmNIC1_QM0_CQ_CTL_STS_4                                      0xD20210
+
+#define mmNIC1_QM0_CQ_IFIFO_CNT_0                                    0xD20214
+
+#define mmNIC1_QM0_CQ_IFIFO_CNT_1                                    0xD20218
+
+#define mmNIC1_QM0_CQ_IFIFO_CNT_2                                    0xD2021C
+
+#define mmNIC1_QM0_CQ_IFIFO_CNT_3                                    0xD20220
+
+#define mmNIC1_QM0_CQ_IFIFO_CNT_4                                    0xD20224
+
+#define mmNIC1_QM0_CP_MSG_BASE0_ADDR_LO_0                            0xD20228
+
+#define mmNIC1_QM0_CP_MSG_BASE0_ADDR_LO_1                            0xD2022C
+
+#define mmNIC1_QM0_CP_MSG_BASE0_ADDR_LO_2                            0xD20230
+
+#define mmNIC1_QM0_CP_MSG_BASE0_ADDR_LO_3                            0xD20234
+
+#define mmNIC1_QM0_CP_MSG_BASE0_ADDR_LO_4                            0xD20238
+
+#define mmNIC1_QM0_CP_MSG_BASE0_ADDR_HI_0                            0xD2023C
+
+#define mmNIC1_QM0_CP_MSG_BASE0_ADDR_HI_1                            0xD20240
+
+#define mmNIC1_QM0_CP_MSG_BASE0_ADDR_HI_2                            0xD20244
+
+#define mmNIC1_QM0_CP_MSG_BASE0_ADDR_HI_3                            0xD20248
+
+#define mmNIC1_QM0_CP_MSG_BASE0_ADDR_HI_4                            0xD2024C
+
+#define mmNIC1_QM0_CP_MSG_BASE1_ADDR_LO_0                            0xD20250
+
+#define mmNIC1_QM0_CP_MSG_BASE1_ADDR_LO_1                            0xD20254
+
+#define mmNIC1_QM0_CP_MSG_BASE1_ADDR_LO_2                            0xD20258
+
+#define mmNIC1_QM0_CP_MSG_BASE1_ADDR_LO_3                            0xD2025C
+
+#define mmNIC1_QM0_CP_MSG_BASE1_ADDR_LO_4                            0xD20260
+
+#define mmNIC1_QM0_CP_MSG_BASE1_ADDR_HI_0                            0xD20264
+
+#define mmNIC1_QM0_CP_MSG_BASE1_ADDR_HI_1                            0xD20268
+
+#define mmNIC1_QM0_CP_MSG_BASE1_ADDR_HI_2                            0xD2026C
+
+#define mmNIC1_QM0_CP_MSG_BASE1_ADDR_HI_3                            0xD20270
+
+#define mmNIC1_QM0_CP_MSG_BASE1_ADDR_HI_4                            0xD20274
+
+#define mmNIC1_QM0_CP_MSG_BASE2_ADDR_LO_0                            0xD20278
+
+#define mmNIC1_QM0_CP_MSG_BASE2_ADDR_LO_1                            0xD2027C
+
+#define mmNIC1_QM0_CP_MSG_BASE2_ADDR_LO_2                            0xD20280
+
+#define mmNIC1_QM0_CP_MSG_BASE2_ADDR_LO_3                            0xD20284
+
+#define mmNIC1_QM0_CP_MSG_BASE2_ADDR_LO_4                            0xD20288
+
+#define mmNIC1_QM0_CP_MSG_BASE2_ADDR_HI_0                            0xD2028C
+
+#define mmNIC1_QM0_CP_MSG_BASE2_ADDR_HI_1                            0xD20290
+
+#define mmNIC1_QM0_CP_MSG_BASE2_ADDR_HI_2                            0xD20294
+
+#define mmNIC1_QM0_CP_MSG_BASE2_ADDR_HI_3                            0xD20298
+
+#define mmNIC1_QM0_CP_MSG_BASE2_ADDR_HI_4                            0xD2029C
+
+#define mmNIC1_QM0_CP_MSG_BASE3_ADDR_LO_0                            0xD202A0
+
+#define mmNIC1_QM0_CP_MSG_BASE3_ADDR_LO_1                            0xD202A4
+
+#define mmNIC1_QM0_CP_MSG_BASE3_ADDR_LO_2                            0xD202A8
+
+#define mmNIC1_QM0_CP_MSG_BASE3_ADDR_LO_3                            0xD202AC
+
+#define mmNIC1_QM0_CP_MSG_BASE3_ADDR_LO_4                            0xD202B0
+
+#define mmNIC1_QM0_CP_MSG_BASE3_ADDR_HI_0                            0xD202B4
+
+#define mmNIC1_QM0_CP_MSG_BASE3_ADDR_HI_1                            0xD202B8
+
+#define mmNIC1_QM0_CP_MSG_BASE3_ADDR_HI_2                            0xD202BC
+
+#define mmNIC1_QM0_CP_MSG_BASE3_ADDR_HI_3                            0xD202C0
+
+#define mmNIC1_QM0_CP_MSG_BASE3_ADDR_HI_4                            0xD202C4
+
+#define mmNIC1_QM0_CP_LDMA_TSIZE_OFFSET_0                            0xD202C8
+
+#define mmNIC1_QM0_CP_LDMA_TSIZE_OFFSET_1                            0xD202CC
+
+#define mmNIC1_QM0_CP_LDMA_TSIZE_OFFSET_2                            0xD202D0
+
+#define mmNIC1_QM0_CP_LDMA_TSIZE_OFFSET_3                            0xD202D4
+
+#define mmNIC1_QM0_CP_LDMA_TSIZE_OFFSET_4                            0xD202D8
+
+#define mmNIC1_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_0                      0xD202E0
+
+#define mmNIC1_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_1                      0xD202E4
+
+#define mmNIC1_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_2                      0xD202E8
+
+#define mmNIC1_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_3                      0xD202EC
+
+#define mmNIC1_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_4                      0xD202F0
+
+#define mmNIC1_QM0_CP_LDMA_DST_BASE_LO_OFFSET_0                      0xD202F4
+
+#define mmNIC1_QM0_CP_LDMA_DST_BASE_LO_OFFSET_1                      0xD202F8
+
+#define mmNIC1_QM0_CP_LDMA_DST_BASE_LO_OFFSET_2                      0xD202FC
+
+#define mmNIC1_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3                      0xD20300
+
+#define mmNIC1_QM0_CP_LDMA_DST_BASE_LO_OFFSET_4                      0xD20304
+
+#define mmNIC1_QM0_CP_FENCE0_RDATA_0                                 0xD20308
+
+#define mmNIC1_QM0_CP_FENCE0_RDATA_1                                 0xD2030C
+
+#define mmNIC1_QM0_CP_FENCE0_RDATA_2                                 0xD20310
+
+#define mmNIC1_QM0_CP_FENCE0_RDATA_3                                 0xD20314
+
+#define mmNIC1_QM0_CP_FENCE0_RDATA_4                                 0xD20318
+
+#define mmNIC1_QM0_CP_FENCE1_RDATA_0                                 0xD2031C
+
+#define mmNIC1_QM0_CP_FENCE1_RDATA_1                                 0xD20320
+
+#define mmNIC1_QM0_CP_FENCE1_RDATA_2                                 0xD20324
+
+#define mmNIC1_QM0_CP_FENCE1_RDATA_3                                 0xD20328
+
+#define mmNIC1_QM0_CP_FENCE1_RDATA_4                                 0xD2032C
+
+#define mmNIC1_QM0_CP_FENCE2_RDATA_0                                 0xD20330
+
+#define mmNIC1_QM0_CP_FENCE2_RDATA_1                                 0xD20334
+
+#define mmNIC1_QM0_CP_FENCE2_RDATA_2                                 0xD20338
+
+#define mmNIC1_QM0_CP_FENCE2_RDATA_3                                 0xD2033C
+
+#define mmNIC1_QM0_CP_FENCE2_RDATA_4                                 0xD20340
+
+#define mmNIC1_QM0_CP_FENCE3_RDATA_0                                 0xD20344
+
+#define mmNIC1_QM0_CP_FENCE3_RDATA_1                                 0xD20348
+
+#define mmNIC1_QM0_CP_FENCE3_RDATA_2                                 0xD2034C
+
+#define mmNIC1_QM0_CP_FENCE3_RDATA_3                                 0xD20350
+
+#define mmNIC1_QM0_CP_FENCE3_RDATA_4                                 0xD20354
+
+#define mmNIC1_QM0_CP_FENCE0_CNT_0                                   0xD20358
+
+#define mmNIC1_QM0_CP_FENCE0_CNT_1                                   0xD2035C
+
+#define mmNIC1_QM0_CP_FENCE0_CNT_2                                   0xD20360
+
+#define mmNIC1_QM0_CP_FENCE0_CNT_3                                   0xD20364
+
+#define mmNIC1_QM0_CP_FENCE0_CNT_4                                   0xD20368
+
+#define mmNIC1_QM0_CP_FENCE1_CNT_0                                   0xD2036C
+
+#define mmNIC1_QM0_CP_FENCE1_CNT_1                                   0xD20370
+
+#define mmNIC1_QM0_CP_FENCE1_CNT_2                                   0xD20374
+
+#define mmNIC1_QM0_CP_FENCE1_CNT_3                                   0xD20378
+
+#define mmNIC1_QM0_CP_FENCE1_CNT_4                                   0xD2037C
+
+#define mmNIC1_QM0_CP_FENCE2_CNT_0                                   0xD20380
+
+#define mmNIC1_QM0_CP_FENCE2_CNT_1                                   0xD20384
+
+#define mmNIC1_QM0_CP_FENCE2_CNT_2                                   0xD20388
+
+#define mmNIC1_QM0_CP_FENCE2_CNT_3                                   0xD2038C
+
+#define mmNIC1_QM0_CP_FENCE2_CNT_4                                   0xD20390
+
+#define mmNIC1_QM0_CP_FENCE3_CNT_0                                   0xD20394
+
+#define mmNIC1_QM0_CP_FENCE3_CNT_1                                   0xD20398
+
+#define mmNIC1_QM0_CP_FENCE3_CNT_2                                   0xD2039C
+
+#define mmNIC1_QM0_CP_FENCE3_CNT_3                                   0xD203A0
+
+#define mmNIC1_QM0_CP_FENCE3_CNT_4                                   0xD203A4
+
+#define mmNIC1_QM0_CP_STS_0                                          0xD203A8
+
+#define mmNIC1_QM0_CP_STS_1                                          0xD203AC
+
+#define mmNIC1_QM0_CP_STS_2                                          0xD203B0
+
+#define mmNIC1_QM0_CP_STS_3                                          0xD203B4
+
+#define mmNIC1_QM0_CP_STS_4                                          0xD203B8
+
+#define mmNIC1_QM0_CP_CURRENT_INST_LO_0                              0xD203BC
+
+#define mmNIC1_QM0_CP_CURRENT_INST_LO_1                              0xD203C0
+
+#define mmNIC1_QM0_CP_CURRENT_INST_LO_2                              0xD203C4
+
+#define mmNIC1_QM0_CP_CURRENT_INST_LO_3                              0xD203C8
+
+#define mmNIC1_QM0_CP_CURRENT_INST_LO_4                              0xD203CC
+
+#define mmNIC1_QM0_CP_CURRENT_INST_HI_0                              0xD203D0
+
+#define mmNIC1_QM0_CP_CURRENT_INST_HI_1                              0xD203D4
+
+#define mmNIC1_QM0_CP_CURRENT_INST_HI_2                              0xD203D8
+
+#define mmNIC1_QM0_CP_CURRENT_INST_HI_3                              0xD203DC
+
+#define mmNIC1_QM0_CP_CURRENT_INST_HI_4                              0xD203E0
+
+#define mmNIC1_QM0_CP_BARRIER_CFG_0                                  0xD203F4
+
+#define mmNIC1_QM0_CP_BARRIER_CFG_1                                  0xD203F8
+
+#define mmNIC1_QM0_CP_BARRIER_CFG_2                                  0xD203FC
+
+#define mmNIC1_QM0_CP_BARRIER_CFG_3                                  0xD20400
+
+#define mmNIC1_QM0_CP_BARRIER_CFG_4                                  0xD20404
+
+#define mmNIC1_QM0_CP_DBG_0_0                                        0xD20408
+
+#define mmNIC1_QM0_CP_DBG_0_1                                        0xD2040C
+
+#define mmNIC1_QM0_CP_DBG_0_2                                        0xD20410
+
+#define mmNIC1_QM0_CP_DBG_0_3                                        0xD20414
+
+#define mmNIC1_QM0_CP_DBG_0_4                                        0xD20418
+
+#define mmNIC1_QM0_CP_ARUSER_31_11_0                                 0xD2041C
+
+#define mmNIC1_QM0_CP_ARUSER_31_11_1                                 0xD20420
+
+#define mmNIC1_QM0_CP_ARUSER_31_11_2                                 0xD20424
+
+#define mmNIC1_QM0_CP_ARUSER_31_11_3                                 0xD20428
+
+#define mmNIC1_QM0_CP_ARUSER_31_11_4                                 0xD2042C
+
+#define mmNIC1_QM0_CP_AWUSER_31_11_0                                 0xD20430
+
+#define mmNIC1_QM0_CP_AWUSER_31_11_1                                 0xD20434
+
+#define mmNIC1_QM0_CP_AWUSER_31_11_2                                 0xD20438
+
+#define mmNIC1_QM0_CP_AWUSER_31_11_3                                 0xD2043C
+
+#define mmNIC1_QM0_CP_AWUSER_31_11_4                                 0xD20440
+
+#define mmNIC1_QM0_ARB_CFG_0                                         0xD20A00
+
+#define mmNIC1_QM0_ARB_CHOISE_Q_PUSH                                 0xD20A04
+
+#define mmNIC1_QM0_ARB_WRR_WEIGHT_0                                  0xD20A08
+
+#define mmNIC1_QM0_ARB_WRR_WEIGHT_1                                  0xD20A0C
+
+#define mmNIC1_QM0_ARB_WRR_WEIGHT_2                                  0xD20A10
+
+#define mmNIC1_QM0_ARB_WRR_WEIGHT_3                                  0xD20A14
+
+#define mmNIC1_QM0_ARB_CFG_1                                         0xD20A18
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_0                              0xD20A20
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_1                              0xD20A24
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_2                              0xD20A28
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_3                              0xD20A2C
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_4                              0xD20A30
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_5                              0xD20A34
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_6                              0xD20A38
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_7                              0xD20A3C
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_8                              0xD20A40
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_9                              0xD20A44
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_10                             0xD20A48
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_11                             0xD20A4C
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_12                             0xD20A50
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_13                             0xD20A54
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_14                             0xD20A58
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_15                             0xD20A5C
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_16                             0xD20A60
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_17                             0xD20A64
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_18                             0xD20A68
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_19                             0xD20A6C
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_20                             0xD20A70
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_21                             0xD20A74
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_22                             0xD20A78
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_23                             0xD20A7C
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_24                             0xD20A80
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_25                             0xD20A84
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_26                             0xD20A88
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_27                             0xD20A8C
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_28                             0xD20A90
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_29                             0xD20A94
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_30                             0xD20A98
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_31                             0xD20A9C
+
+#define mmNIC1_QM0_ARB_MST_CRED_INC                                  0xD20AA0
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_0                        0xD20AA4
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_1                        0xD20AA8
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_2                        0xD20AAC
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_3                        0xD20AB0
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_4                        0xD20AB4
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_5                        0xD20AB8
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_6                        0xD20ABC
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_7                        0xD20AC0
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_8                        0xD20AC4
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_9                        0xD20AC8
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_10                       0xD20ACC
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_11                       0xD20AD0
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_12                       0xD20AD4
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_13                       0xD20AD8
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_14                       0xD20ADC
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_15                       0xD20AE0
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_16                       0xD20AE4
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_17                       0xD20AE8
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_18                       0xD20AEC
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_19                       0xD20AF0
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_20                       0xD20AF4
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_21                       0xD20AF8
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_22                       0xD20AFC
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_23                       0xD20B00
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_24                       0xD20B04
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_25                       0xD20B08
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_26                       0xD20B0C
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_27                       0xD20B10
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_28                       0xD20B14
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_29                       0xD20B18
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_30                       0xD20B1C
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_31                       0xD20B20
+
+#define mmNIC1_QM0_ARB_SLV_MASTER_INC_CRED_OFST                      0xD20B28
+
+#define mmNIC1_QM0_ARB_MST_SLAVE_EN                                  0xD20B2C
+
+#define mmNIC1_QM0_ARB_MST_QUIET_PER                                 0xD20B34
+
+#define mmNIC1_QM0_ARB_SLV_CHOISE_WDT                                0xD20B38
+
+#define mmNIC1_QM0_ARB_SLV_ID                                        0xD20B3C
+
+#define mmNIC1_QM0_ARB_MSG_MAX_INFLIGHT                              0xD20B44
+
+#define mmNIC1_QM0_ARB_MSG_AWUSER_31_11                              0xD20B48
+
+#define mmNIC1_QM0_ARB_MSG_AWUSER_SEC_PROP                           0xD20B4C
+
+#define mmNIC1_QM0_ARB_MSG_AWUSER_NON_SEC_PROP                       0xD20B50
+
+#define mmNIC1_QM0_ARB_BASE_LO                                       0xD20B54
+
+#define mmNIC1_QM0_ARB_BASE_HI                                       0xD20B58
+
+#define mmNIC1_QM0_ARB_STATE_STS                                     0xD20B80
+
+#define mmNIC1_QM0_ARB_CHOISE_FULLNESS_STS                           0xD20B84
+
+#define mmNIC1_QM0_ARB_MSG_STS                                       0xD20B88
+
+#define mmNIC1_QM0_ARB_SLV_CHOISE_Q_HEAD                             0xD20B8C
+
+#define mmNIC1_QM0_ARB_ERR_CAUSE                                     0xD20B9C
+
+#define mmNIC1_QM0_ARB_ERR_MSG_EN                                    0xD20BA0
+
+#define mmNIC1_QM0_ARB_ERR_STS_DRP                                   0xD20BA8
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_0                                0xD20BB0
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_1                                0xD20BB4
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_2                                0xD20BB8
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_3                                0xD20BBC
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_4                                0xD20BC0
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_5                                0xD20BC4
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_6                                0xD20BC8
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_7                                0xD20BCC
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_8                                0xD20BD0
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_9                                0xD20BD4
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_10                               0xD20BD8
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_11                               0xD20BDC
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_12                               0xD20BE0
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_13                               0xD20BE4
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_14                               0xD20BE8
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_15                               0xD20BEC
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_16                               0xD20BF0
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_17                               0xD20BF4
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_18                               0xD20BF8
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_19                               0xD20BFC
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_20                               0xD20C00
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_21                               0xD20C04
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_22                               0xD20C08
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_23                               0xD20C0C
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_24                               0xD20C10
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_25                               0xD20C14
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_26                               0xD20C18
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_27                               0xD20C1C
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_28                               0xD20C20
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_29                               0xD20C24
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_30                               0xD20C28
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_31                               0xD20C2C
+
+#define mmNIC1_QM0_CGM_CFG                                           0xD20C70
+
+#define mmNIC1_QM0_CGM_STS                                           0xD20C74
+
+#define mmNIC1_QM0_CGM_CFG1                                          0xD20C78
+
+#define mmNIC1_QM0_LOCAL_RANGE_BASE                                  0xD20C80
+
+#define mmNIC1_QM0_LOCAL_RANGE_SIZE                                  0xD20C84
+
+#define mmNIC1_QM0_CSMR_STRICT_PRIO_CFG                              0xD20C90
+
+#define mmNIC1_QM0_HBW_RD_RATE_LIM_CFG_1                             0xD20C94
+
+#define mmNIC1_QM0_LBW_WR_RATE_LIM_CFG_0                             0xD20C98
+
+#define mmNIC1_QM0_LBW_WR_RATE_LIM_CFG_1                             0xD20C9C
+
+#define mmNIC1_QM0_HBW_RD_RATE_LIM_CFG_0                             0xD20CA0
+
+#define mmNIC1_QM0_GLBL_AXCACHE                                      0xD20CA4
+
+#define mmNIC1_QM0_IND_GW_APB_CFG                                    0xD20CB0
+
+#define mmNIC1_QM0_IND_GW_APB_WDATA                                  0xD20CB4
+
+#define mmNIC1_QM0_IND_GW_APB_RDATA                                  0xD20CB8
+
+#define mmNIC1_QM0_IND_GW_APB_STATUS                                 0xD20CBC
+
+#define mmNIC1_QM0_GLBL_ERR_ADDR_LO                                  0xD20CD0
+
+#define mmNIC1_QM0_GLBL_ERR_ADDR_HI                                  0xD20CD4
+
+#define mmNIC1_QM0_GLBL_ERR_WDATA                                    0xD20CD8
+
+#define mmNIC1_QM0_GLBL_MEM_INIT_BUSY                                0xD20D00
+
+#endif /* ASIC_REG_NIC1_QM0_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/nic1_qm1_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic1_qm1_regs.h
new file mode 100644
index 000000000000..1b115ee6d6f0
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic1_qm1_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_NIC1_QM1_REGS_H_
+#define ASIC_REG_NIC1_QM1_REGS_H_
+
+/*
+ *****************************************
+ *   NIC1_QM1 (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmNIC1_QM1_GLBL_CFG0                                         0xD22000
+
+#define mmNIC1_QM1_GLBL_CFG1                                         0xD22004
+
+#define mmNIC1_QM1_GLBL_PROT                                         0xD22008
+
+#define mmNIC1_QM1_GLBL_ERR_CFG                                      0xD2200C
+
+#define mmNIC1_QM1_GLBL_SECURE_PROPS_0                               0xD22010
+
+#define mmNIC1_QM1_GLBL_SECURE_PROPS_1                               0xD22014
+
+#define mmNIC1_QM1_GLBL_SECURE_PROPS_2                               0xD22018
+
+#define mmNIC1_QM1_GLBL_SECURE_PROPS_3                               0xD2201C
+
+#define mmNIC1_QM1_GLBL_SECURE_PROPS_4                               0xD22020
+
+#define mmNIC1_QM1_GLBL_NON_SECURE_PROPS_0                           0xD22024
+
+#define mmNIC1_QM1_GLBL_NON_SECURE_PROPS_1                           0xD22028
+
+#define mmNIC1_QM1_GLBL_NON_SECURE_PROPS_2                           0xD2202C
+
+#define mmNIC1_QM1_GLBL_NON_SECURE_PROPS_3                           0xD22030
+
+#define mmNIC1_QM1_GLBL_NON_SECURE_PROPS_4                           0xD22034
+
+#define mmNIC1_QM1_GLBL_STS0                                         0xD22038
+
+#define mmNIC1_QM1_GLBL_STS1_0                                       0xD22040
+
+#define mmNIC1_QM1_GLBL_STS1_1                                       0xD22044
+
+#define mmNIC1_QM1_GLBL_STS1_2                                       0xD22048
+
+#define mmNIC1_QM1_GLBL_STS1_3                                       0xD2204C
+
+#define mmNIC1_QM1_GLBL_STS1_4                                       0xD22050
+
+#define mmNIC1_QM1_GLBL_MSG_EN_0                                     0xD22054
+
+#define mmNIC1_QM1_GLBL_MSG_EN_1                                     0xD22058
+
+#define mmNIC1_QM1_GLBL_MSG_EN_2                                     0xD2205C
+
+#define mmNIC1_QM1_GLBL_MSG_EN_3                                     0xD22060
+
+#define mmNIC1_QM1_GLBL_MSG_EN_4                                     0xD22068
+
+#define mmNIC1_QM1_PQ_BASE_LO_0                                      0xD22070
+
+#define mmNIC1_QM1_PQ_BASE_LO_1                                      0xD22074
+
+#define mmNIC1_QM1_PQ_BASE_LO_2                                      0xD22078
+
+#define mmNIC1_QM1_PQ_BASE_LO_3                                      0xD2207C
+
+#define mmNIC1_QM1_PQ_BASE_HI_0                                      0xD22080
+
+#define mmNIC1_QM1_PQ_BASE_HI_1                                      0xD22084
+
+#define mmNIC1_QM1_PQ_BASE_HI_2                                      0xD22088
+
+#define mmNIC1_QM1_PQ_BASE_HI_3                                      0xD2208C
+
+#define mmNIC1_QM1_PQ_SIZE_0                                         0xD22090
+
+#define mmNIC1_QM1_PQ_SIZE_1                                         0xD22094
+
+#define mmNIC1_QM1_PQ_SIZE_2                                         0xD22098
+
+#define mmNIC1_QM1_PQ_SIZE_3                                         0xD2209C
+
+#define mmNIC1_QM1_PQ_PI_0                                           0xD220A0
+
+#define mmNIC1_QM1_PQ_PI_1                                           0xD220A4
+
+#define mmNIC1_QM1_PQ_PI_2                                           0xD220A8
+
+#define mmNIC1_QM1_PQ_PI_3                                           0xD220AC
+
+#define mmNIC1_QM1_PQ_CI_0                                           0xD220B0
+
+#define mmNIC1_QM1_PQ_CI_1                                           0xD220B4
+
+#define mmNIC1_QM1_PQ_CI_2                                           0xD220B8
+
+#define mmNIC1_QM1_PQ_CI_3                                           0xD220BC
+
+#define mmNIC1_QM1_PQ_CFG0_0                                         0xD220C0
+
+#define mmNIC1_QM1_PQ_CFG0_1                                         0xD220C4
+
+#define mmNIC1_QM1_PQ_CFG0_2                                         0xD220C8
+
+#define mmNIC1_QM1_PQ_CFG0_3                                         0xD220CC
+
+#define mmNIC1_QM1_PQ_CFG1_0                                         0xD220D0
+
+#define mmNIC1_QM1_PQ_CFG1_1                                         0xD220D4
+
+#define mmNIC1_QM1_PQ_CFG1_2                                         0xD220D8
+
+#define mmNIC1_QM1_PQ_CFG1_3                                         0xD220DC
+
+#define mmNIC1_QM1_PQ_ARUSER_31_11_0                                 0xD220E0
+
+#define mmNIC1_QM1_PQ_ARUSER_31_11_1                                 0xD220E4
+
+#define mmNIC1_QM1_PQ_ARUSER_31_11_2                                 0xD220E8
+
+#define mmNIC1_QM1_PQ_ARUSER_31_11_3                                 0xD220EC
+
+#define mmNIC1_QM1_PQ_STS0_0                                         0xD220F0
+
+#define mmNIC1_QM1_PQ_STS0_1                                         0xD220F4
+
+#define mmNIC1_QM1_PQ_STS0_2                                         0xD220F8
+
+#define mmNIC1_QM1_PQ_STS0_3                                         0xD220FC
+
+#define mmNIC1_QM1_PQ_STS1_0                                         0xD22100
+
+#define mmNIC1_QM1_PQ_STS1_1                                         0xD22104
+
+#define mmNIC1_QM1_PQ_STS1_2                                         0xD22108
+
+#define mmNIC1_QM1_PQ_STS1_3                                         0xD2210C
+
+#define mmNIC1_QM1_CQ_CFG0_0                                         0xD22110
+
+#define mmNIC1_QM1_CQ_CFG0_1                                         0xD22114
+
+#define mmNIC1_QM1_CQ_CFG0_2                                         0xD22118
+
+#define mmNIC1_QM1_CQ_CFG0_3                                         0xD2211C
+
+#define mmNIC1_QM1_CQ_CFG0_4                                         0xD22120
+
+#define mmNIC1_QM1_CQ_CFG1_0                                         0xD22124
+
+#define mmNIC1_QM1_CQ_CFG1_1                                         0xD22128
+
+#define mmNIC1_QM1_CQ_CFG1_2                                         0xD2212C
+
+#define mmNIC1_QM1_CQ_CFG1_3                                         0xD22130
+
+#define mmNIC1_QM1_CQ_CFG1_4                                         0xD22134
+
+#define mmNIC1_QM1_CQ_ARUSER_31_11_0                                 0xD22138
+
+#define mmNIC1_QM1_CQ_ARUSER_31_11_1                                 0xD2213C
+
+#define mmNIC1_QM1_CQ_ARUSER_31_11_2                                 0xD22140
+
+#define mmNIC1_QM1_CQ_ARUSER_31_11_3                                 0xD22144
+
+#define mmNIC1_QM1_CQ_ARUSER_31_11_4                                 0xD22148
+
+#define mmNIC1_QM1_CQ_STS0_0                                         0xD2214C
+
+#define mmNIC1_QM1_CQ_STS0_1                                         0xD22150
+
+#define mmNIC1_QM1_CQ_STS0_2                                         0xD22154
+
+#define mmNIC1_QM1_CQ_STS0_3                                         0xD22158
+
+#define mmNIC1_QM1_CQ_STS0_4                                         0xD2215C
+
+#define mmNIC1_QM1_CQ_STS1_0                                         0xD22160
+
+#define mmNIC1_QM1_CQ_STS1_1                                         0xD22164
+
+#define mmNIC1_QM1_CQ_STS1_2                                         0xD22168
+
+#define mmNIC1_QM1_CQ_STS1_3                                         0xD2216C
+
+#define mmNIC1_QM1_CQ_STS1_4                                         0xD22170
+
+#define mmNIC1_QM1_CQ_PTR_LO_0                                       0xD22174
+
+#define mmNIC1_QM1_CQ_PTR_HI_0                                       0xD22178
+
+#define mmNIC1_QM1_CQ_TSIZE_0                                        0xD2217C
+
+#define mmNIC1_QM1_CQ_CTL_0                                          0xD22180
+
+#define mmNIC1_QM1_CQ_PTR_LO_1                                       0xD22184
+
+#define mmNIC1_QM1_CQ_PTR_HI_1                                       0xD22188
+
+#define mmNIC1_QM1_CQ_TSIZE_1                                        0xD2218C
+
+#define mmNIC1_QM1_CQ_CTL_1                                          0xD22190
+
+#define mmNIC1_QM1_CQ_PTR_LO_2                                       0xD22194
+
+#define mmNIC1_QM1_CQ_PTR_HI_2                                       0xD22198
+
+#define mmNIC1_QM1_CQ_TSIZE_2                                        0xD2219C
+
+#define mmNIC1_QM1_CQ_CTL_2                                          0xD221A0
+
+#define mmNIC1_QM1_CQ_PTR_LO_3                                       0xD221A4
+
+#define mmNIC1_QM1_CQ_PTR_HI_3                                       0xD221A8
+
+#define mmNIC1_QM1_CQ_TSIZE_3                                        0xD221AC
+
+#define mmNIC1_QM1_CQ_CTL_3                                          0xD221B0
+
+#define mmNIC1_QM1_CQ_PTR_LO_4                                       0xD221B4
+
+#define mmNIC1_QM1_CQ_PTR_HI_4                                       0xD221B8
+
+#define mmNIC1_QM1_CQ_TSIZE_4                                        0xD221BC
+
+#define mmNIC1_QM1_CQ_CTL_4                                          0xD221C0
+
+#define mmNIC1_QM1_CQ_PTR_LO_STS_0                                   0xD221C4
+
+#define mmNIC1_QM1_CQ_PTR_LO_STS_1                                   0xD221C8
+
+#define mmNIC1_QM1_CQ_PTR_LO_STS_2                                   0xD221CC
+
+#define mmNIC1_QM1_CQ_PTR_LO_STS_3                                   0xD221D0
+
+#define mmNIC1_QM1_CQ_PTR_LO_STS_4                                   0xD221D4
+
+#define mmNIC1_QM1_CQ_PTR_HI_STS_0                                   0xD221D8
+
+#define mmNIC1_QM1_CQ_PTR_HI_STS_1                                   0xD221DC
+
+#define mmNIC1_QM1_CQ_PTR_HI_STS_2                                   0xD221E0
+
+#define mmNIC1_QM1_CQ_PTR_HI_STS_3                                   0xD221E4
+
+#define mmNIC1_QM1_CQ_PTR_HI_STS_4                                   0xD221E8
+
+#define mmNIC1_QM1_CQ_TSIZE_STS_0                                    0xD221EC
+
+#define mmNIC1_QM1_CQ_TSIZE_STS_1                                    0xD221F0
+
+#define mmNIC1_QM1_CQ_TSIZE_STS_2                                    0xD221F4
+
+#define mmNIC1_QM1_CQ_TSIZE_STS_3                                    0xD221F8
+
+#define mmNIC1_QM1_CQ_TSIZE_STS_4                                    0xD221FC
+
+#define mmNIC1_QM1_CQ_CTL_STS_0                                      0xD22200
+
+#define mmNIC1_QM1_CQ_CTL_STS_1                                      0xD22204
+
+#define mmNIC1_QM1_CQ_CTL_STS_2                                      0xD22208
+
+#define mmNIC1_QM1_CQ_CTL_STS_3                                      0xD2220C
+
+#define mmNIC1_QM1_CQ_CTL_STS_4                                      0xD22210
+
+#define mmNIC1_QM1_CQ_IFIFO_CNT_0                                    0xD22214
+
+#define mmNIC1_QM1_CQ_IFIFO_CNT_1                                    0xD22218
+
+#define mmNIC1_QM1_CQ_IFIFO_CNT_2                                    0xD2221C
+
+#define mmNIC1_QM1_CQ_IFIFO_CNT_3                                    0xD22220
+
+#define mmNIC1_QM1_CQ_IFIFO_CNT_4                                    0xD22224
+
+#define mmNIC1_QM1_CP_MSG_BASE0_ADDR_LO_0                            0xD22228
+
+#define mmNIC1_QM1_CP_MSG_BASE0_ADDR_LO_1                            0xD2222C
+
+#define mmNIC1_QM1_CP_MSG_BASE0_ADDR_LO_2                            0xD22230
+
+#define mmNIC1_QM1_CP_MSG_BASE0_ADDR_LO_3                            0xD22234
+
+#define mmNIC1_QM1_CP_MSG_BASE0_ADDR_LO_4                            0xD22238
+
+#define mmNIC1_QM1_CP_MSG_BASE0_ADDR_HI_0                            0xD2223C
+
+#define mmNIC1_QM1_CP_MSG_BASE0_ADDR_HI_1                            0xD22240
+
+#define mmNIC1_QM1_CP_MSG_BASE0_ADDR_HI_2                            0xD22244
+
+#define mmNIC1_QM1_CP_MSG_BASE0_ADDR_HI_3                            0xD22248
+
+#define mmNIC1_QM1_CP_MSG_BASE0_ADDR_HI_4                            0xD2224C
+
+#define mmNIC1_QM1_CP_MSG_BASE1_ADDR_LO_0                            0xD22250
+
+#define mmNIC1_QM1_CP_MSG_BASE1_ADDR_LO_1                            0xD22254
+
+#define mmNIC1_QM1_CP_MSG_BASE1_ADDR_LO_2                            0xD22258
+
+#define mmNIC1_QM1_CP_MSG_BASE1_ADDR_LO_3                            0xD2225C
+
+#define mmNIC1_QM1_CP_MSG_BASE1_ADDR_LO_4                            0xD22260
+
+#define mmNIC1_QM1_CP_MSG_BASE1_ADDR_HI_0                            0xD22264
+
+#define mmNIC1_QM1_CP_MSG_BASE1_ADDR_HI_1                            0xD22268
+
+#define mmNIC1_QM1_CP_MSG_BASE1_ADDR_HI_2                            0xD2226C
+
+#define mmNIC1_QM1_CP_MSG_BASE1_ADDR_HI_3                            0xD22270
+
+#define mmNIC1_QM1_CP_MSG_BASE1_ADDR_HI_4                            0xD22274
+
+#define mmNIC1_QM1_CP_MSG_BASE2_ADDR_LO_0                            0xD22278
+
+#define mmNIC1_QM1_CP_MSG_BASE2_ADDR_LO_1                            0xD2227C
+
+#define mmNIC1_QM1_CP_MSG_BASE2_ADDR_LO_2                            0xD22280
+
+#define mmNIC1_QM1_CP_MSG_BASE2_ADDR_LO_3                            0xD22284
+
+#define mmNIC1_QM1_CP_MSG_BASE2_ADDR_LO_4                            0xD22288
+
+#define mmNIC1_QM1_CP_MSG_BASE2_ADDR_HI_0                            0xD2228C
+
+#define mmNIC1_QM1_CP_MSG_BASE2_ADDR_HI_1                            0xD22290
+
+#define mmNIC1_QM1_CP_MSG_BASE2_ADDR_HI_2                            0xD22294
+
+#define mmNIC1_QM1_CP_MSG_BASE2_ADDR_HI_3                            0xD22298
+
+#define mmNIC1_QM1_CP_MSG_BASE2_ADDR_HI_4                            0xD2229C
+
+#define mmNIC1_QM1_CP_MSG_BASE3_ADDR_LO_0                            0xD222A0
+
+#define mmNIC1_QM1_CP_MSG_BASE3_ADDR_LO_1                            0xD222A4
+
+#define mmNIC1_QM1_CP_MSG_BASE3_ADDR_LO_2                            0xD222A8
+
+#define mmNIC1_QM1_CP_MSG_BASE3_ADDR_LO_3                            0xD222AC
+
+#define mmNIC1_QM1_CP_MSG_BASE3_ADDR_LO_4                            0xD222B0
+
+#define mmNIC1_QM1_CP_MSG_BASE3_ADDR_HI_0                            0xD222B4
+
+#define mmNIC1_QM1_CP_MSG_BASE3_ADDR_HI_1                            0xD222B8
+
+#define mmNIC1_QM1_CP_MSG_BASE3_ADDR_HI_2                            0xD222BC
+
+#define mmNIC1_QM1_CP_MSG_BASE3_ADDR_HI_3                            0xD222C0
+
+#define mmNIC1_QM1_CP_MSG_BASE3_ADDR_HI_4                            0xD222C4
+
+#define mmNIC1_QM1_CP_LDMA_TSIZE_OFFSET_0                            0xD222C8
+
+#define mmNIC1_QM1_CP_LDMA_TSIZE_OFFSET_1                            0xD222CC
+
+#define mmNIC1_QM1_CP_LDMA_TSIZE_OFFSET_2                            0xD222D0
+
+#define mmNIC1_QM1_CP_LDMA_TSIZE_OFFSET_3                            0xD222D4
+
+#define mmNIC1_QM1_CP_LDMA_TSIZE_OFFSET_4                            0xD222D8
+
+#define mmNIC1_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_0                      0xD222E0
+
+#define mmNIC1_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_1                      0xD222E4
+
+#define mmNIC1_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_2                      0xD222E8
+
+#define mmNIC1_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_3                      0xD222EC
+
+#define mmNIC1_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_4                      0xD222F0
+
+#define mmNIC1_QM1_CP_LDMA_DST_BASE_LO_OFFSET_0                      0xD222F4
+
+#define mmNIC1_QM1_CP_LDMA_DST_BASE_LO_OFFSET_1                      0xD222F8
+
+#define mmNIC1_QM1_CP_LDMA_DST_BASE_LO_OFFSET_2                      0xD222FC
+
+#define mmNIC1_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3                      0xD22300
+
+#define mmNIC1_QM1_CP_LDMA_DST_BASE_LO_OFFSET_4                      0xD22304
+
+#define mmNIC1_QM1_CP_FENCE0_RDATA_0                                 0xD22308
+
+#define mmNIC1_QM1_CP_FENCE0_RDATA_1                                 0xD2230C
+
+#define mmNIC1_QM1_CP_FENCE0_RDATA_2                                 0xD22310
+
+#define mmNIC1_QM1_CP_FENCE0_RDATA_3                                 0xD22314
+
+#define mmNIC1_QM1_CP_FENCE0_RDATA_4                                 0xD22318
+
+#define mmNIC1_QM1_CP_FENCE1_RDATA_0                                 0xD2231C
+
+#define mmNIC1_QM1_CP_FENCE1_RDATA_1                                 0xD22320
+
+#define mmNIC1_QM1_CP_FENCE1_RDATA_2                                 0xD22324
+
+#define mmNIC1_QM1_CP_FENCE1_RDATA_3                                 0xD22328
+
+#define mmNIC1_QM1_CP_FENCE1_RDATA_4                                 0xD2232C
+
+#define mmNIC1_QM1_CP_FENCE2_RDATA_0                                 0xD22330
+
+#define mmNIC1_QM1_CP_FENCE2_RDATA_1                                 0xD22334
+
+#define mmNIC1_QM1_CP_FENCE2_RDATA_2                                 0xD22338
+
+#define mmNIC1_QM1_CP_FENCE2_RDATA_3                                 0xD2233C
+
+#define mmNIC1_QM1_CP_FENCE2_RDATA_4                                 0xD22340
+
+#define mmNIC1_QM1_CP_FENCE3_RDATA_0                                 0xD22344
+
+#define mmNIC1_QM1_CP_FENCE3_RDATA_1                                 0xD22348
+
+#define mmNIC1_QM1_CP_FENCE3_RDATA_2                                 0xD2234C
+
+#define mmNIC1_QM1_CP_FENCE3_RDATA_3                                 0xD22350
+
+#define mmNIC1_QM1_CP_FENCE3_RDATA_4                                 0xD22354
+
+#define mmNIC1_QM1_CP_FENCE0_CNT_0                                   0xD22358
+
+#define mmNIC1_QM1_CP_FENCE0_CNT_1                                   0xD2235C
+
+#define mmNIC1_QM1_CP_FENCE0_CNT_2                                   0xD22360
+
+#define mmNIC1_QM1_CP_FENCE0_CNT_3                                   0xD22364
+
+#define mmNIC1_QM1_CP_FENCE0_CNT_4                                   0xD22368
+
+#define mmNIC1_QM1_CP_FENCE1_CNT_0                                   0xD2236C
+
+#define mmNIC1_QM1_CP_FENCE1_CNT_1                                   0xD22370
+
+#define mmNIC1_QM1_CP_FENCE1_CNT_2                                   0xD22374
+
+#define mmNIC1_QM1_CP_FENCE1_CNT_3                                   0xD22378
+
+#define mmNIC1_QM1_CP_FENCE1_CNT_4                                   0xD2237C
+
+#define mmNIC1_QM1_CP_FENCE2_CNT_0                                   0xD22380
+
+#define mmNIC1_QM1_CP_FENCE2_CNT_1                                   0xD22384
+
+#define mmNIC1_QM1_CP_FENCE2_CNT_2                                   0xD22388
+
+#define mmNIC1_QM1_CP_FENCE2_CNT_3                                   0xD2238C
+
+#define mmNIC1_QM1_CP_FENCE2_CNT_4                                   0xD22390
+
+#define mmNIC1_QM1_CP_FENCE3_CNT_0                                   0xD22394
+
+#define mmNIC1_QM1_CP_FENCE3_CNT_1                                   0xD22398
+
+#define mmNIC1_QM1_CP_FENCE3_CNT_2                                   0xD2239C
+
+#define mmNIC1_QM1_CP_FENCE3_CNT_3                                   0xD223A0
+
+#define mmNIC1_QM1_CP_FENCE3_CNT_4                                   0xD223A4
+
+#define mmNIC1_QM1_CP_STS_0                                          0xD223A8
+
+#define mmNIC1_QM1_CP_STS_1                                          0xD223AC
+
+#define mmNIC1_QM1_CP_STS_2                                          0xD223B0
+
+#define mmNIC1_QM1_CP_STS_3                                          0xD223B4
+
+#define mmNIC1_QM1_CP_STS_4                                          0xD223B8
+
+#define mmNIC1_QM1_CP_CURRENT_INST_LO_0                              0xD223BC
+
+#define mmNIC1_QM1_CP_CURRENT_INST_LO_1                              0xD223C0
+
+#define mmNIC1_QM1_CP_CURRENT_INST_LO_2                              0xD223C4
+
+#define mmNIC1_QM1_CP_CURRENT_INST_LO_3                              0xD223C8
+
+#define mmNIC1_QM1_CP_CURRENT_INST_LO_4                              0xD223CC
+
+#define mmNIC1_QM1_CP_CURRENT_INST_HI_0                              0xD223D0
+
+#define mmNIC1_QM1_CP_CURRENT_INST_HI_1                              0xD223D4
+
+#define mmNIC1_QM1_CP_CURRENT_INST_HI_2                              0xD223D8
+
+#define mmNIC1_QM1_CP_CURRENT_INST_HI_3                              0xD223DC
+
+#define mmNIC1_QM1_CP_CURRENT_INST_HI_4                              0xD223E0
+
+#define mmNIC1_QM1_CP_BARRIER_CFG_0                                  0xD223F4
+
+#define mmNIC1_QM1_CP_BARRIER_CFG_1                                  0xD223F8
+
+#define mmNIC1_QM1_CP_BARRIER_CFG_2                                  0xD223FC
+
+#define mmNIC1_QM1_CP_BARRIER_CFG_3                                  0xD22400
+
+#define mmNIC1_QM1_CP_BARRIER_CFG_4                                  0xD22404
+
+#define mmNIC1_QM1_CP_DBG_0_0                                        0xD22408
+
+#define mmNIC1_QM1_CP_DBG_0_1                                        0xD2240C
+
+#define mmNIC1_QM1_CP_DBG_0_2                                        0xD22410
+
+#define mmNIC1_QM1_CP_DBG_0_3                                        0xD22414
+
+#define mmNIC1_QM1_CP_DBG_0_4                                        0xD22418
+
+#define mmNIC1_QM1_CP_ARUSER_31_11_0                                 0xD2241C
+
+#define mmNIC1_QM1_CP_ARUSER_31_11_1                                 0xD22420
+
+#define mmNIC1_QM1_CP_ARUSER_31_11_2                                 0xD22424
+
+#define mmNIC1_QM1_CP_ARUSER_31_11_3                                 0xD22428
+
+#define mmNIC1_QM1_CP_ARUSER_31_11_4                                 0xD2242C
+
+#define mmNIC1_QM1_CP_AWUSER_31_11_0                                 0xD22430
+
+#define mmNIC1_QM1_CP_AWUSER_31_11_1                                 0xD22434
+
+#define mmNIC1_QM1_CP_AWUSER_31_11_2                                 0xD22438
+
+#define mmNIC1_QM1_CP_AWUSER_31_11_3                                 0xD2243C
+
+#define mmNIC1_QM1_CP_AWUSER_31_11_4                                 0xD22440
+
+#define mmNIC1_QM1_ARB_CFG_0                                         0xD22A00
+
+#define mmNIC1_QM1_ARB_CHOISE_Q_PUSH                                 0xD22A04
+
+#define mmNIC1_QM1_ARB_WRR_WEIGHT_0                                  0xD22A08
+
+#define mmNIC1_QM1_ARB_WRR_WEIGHT_1                                  0xD22A0C
+
+#define mmNIC1_QM1_ARB_WRR_WEIGHT_2                                  0xD22A10
+
+#define mmNIC1_QM1_ARB_WRR_WEIGHT_3                                  0xD22A14
+
+#define mmNIC1_QM1_ARB_CFG_1                                         0xD22A18
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_0                              0xD22A20
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_1                              0xD22A24
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_2                              0xD22A28
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_3                              0xD22A2C
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_4                              0xD22A30
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_5                              0xD22A34
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_6                              0xD22A38
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_7                              0xD22A3C
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_8                              0xD22A40
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_9                              0xD22A44
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_10                             0xD22A48
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_11                             0xD22A4C
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_12                             0xD22A50
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_13                             0xD22A54
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_14                             0xD22A58
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_15                             0xD22A5C
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_16                             0xD22A60
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_17                             0xD22A64
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_18                             0xD22A68
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_19                             0xD22A6C
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_20                             0xD22A70
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_21                             0xD22A74
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_22                             0xD22A78
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_23                             0xD22A7C
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_24                             0xD22A80
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_25                             0xD22A84
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_26                             0xD22A88
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_27                             0xD22A8C
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_28                             0xD22A90
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_29                             0xD22A94
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_30                             0xD22A98
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_31                             0xD22A9C
+
+#define mmNIC1_QM1_ARB_MST_CRED_INC                                  0xD22AA0
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_0                        0xD22AA4
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_1                        0xD22AA8
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_2                        0xD22AAC
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_3                        0xD22AB0
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_4                        0xD22AB4
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_5                        0xD22AB8
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_6                        0xD22ABC
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_7                        0xD22AC0
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_8                        0xD22AC4
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_9                        0xD22AC8
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_10                       0xD22ACC
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_11                       0xD22AD0
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_12                       0xD22AD4
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_13                       0xD22AD8
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_14                       0xD22ADC
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_15                       0xD22AE0
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_16                       0xD22AE4
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_17                       0xD22AE8
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_18                       0xD22AEC
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_19                       0xD22AF0
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_20                       0xD22AF4
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_21                       0xD22AF8
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_22                       0xD22AFC
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_23                       0xD22B00
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_24                       0xD22B04
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_25                       0xD22B08
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_26                       0xD22B0C
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_27                       0xD22B10
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_28                       0xD22B14
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_29                       0xD22B18
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_30                       0xD22B1C
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_31                       0xD22B20
+
+#define mmNIC1_QM1_ARB_SLV_MASTER_INC_CRED_OFST                      0xD22B28
+
+#define mmNIC1_QM1_ARB_MST_SLAVE_EN                                  0xD22B2C
+
+#define mmNIC1_QM1_ARB_MST_QUIET_PER                                 0xD22B34
+
+#define mmNIC1_QM1_ARB_SLV_CHOISE_WDT                                0xD22B38
+
+#define mmNIC1_QM1_ARB_SLV_ID                                        0xD22B3C
+
+#define mmNIC1_QM1_ARB_MSG_MAX_INFLIGHT                              0xD22B44
+
+#define mmNIC1_QM1_ARB_MSG_AWUSER_31_11                              0xD22B48
+
+#define mmNIC1_QM1_ARB_MSG_AWUSER_SEC_PROP                           0xD22B4C
+
+#define mmNIC1_QM1_ARB_MSG_AWUSER_NON_SEC_PROP                       0xD22B50
+
+#define mmNIC1_QM1_ARB_BASE_LO                                       0xD22B54
+
+#define mmNIC1_QM1_ARB_BASE_HI                                       0xD22B58
+
+#define mmNIC1_QM1_ARB_STATE_STS                                     0xD22B80
+
+#define mmNIC1_QM1_ARB_CHOISE_FULLNESS_STS                           0xD22B84
+
+#define mmNIC1_QM1_ARB_MSG_STS                                       0xD22B88
+
+#define mmNIC1_QM1_ARB_SLV_CHOISE_Q_HEAD                             0xD22B8C
+
+#define mmNIC1_QM1_ARB_ERR_CAUSE                                     0xD22B9C
+
+#define mmNIC1_QM1_ARB_ERR_MSG_EN                                    0xD22BA0
+
+#define mmNIC1_QM1_ARB_ERR_STS_DRP                                   0xD22BA8
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_0                                0xD22BB0
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_1                                0xD22BB4
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_2                                0xD22BB8
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_3                                0xD22BBC
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_4                                0xD22BC0
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_5                                0xD22BC4
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_6                                0xD22BC8
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_7                                0xD22BCC
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_8                                0xD22BD0
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_9                                0xD22BD4
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_10                               0xD22BD8
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_11                               0xD22BDC
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_12                               0xD22BE0
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_13                               0xD22BE4
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_14                               0xD22BE8
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_15                               0xD22BEC
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_16                               0xD22BF0
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_17                               0xD22BF4
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_18                               0xD22BF8
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_19                               0xD22BFC
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_20                               0xD22C00
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_21                               0xD22C04
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_22                               0xD22C08
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_23                               0xD22C0C
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_24                               0xD22C10
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_25                               0xD22C14
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_26                               0xD22C18
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_27                               0xD22C1C
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_28                               0xD22C20
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_29                               0xD22C24
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_30                               0xD22C28
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_31                               0xD22C2C
+
+#define mmNIC1_QM1_CGM_CFG                                           0xD22C70
+
+#define mmNIC1_QM1_CGM_STS                                           0xD22C74
+
+#define mmNIC1_QM1_CGM_CFG1                                          0xD22C78
+
+#define mmNIC1_QM1_LOCAL_RANGE_BASE                                  0xD22C80
+
+#define mmNIC1_QM1_LOCAL_RANGE_SIZE                                  0xD22C84
+
+#define mmNIC1_QM1_CSMR_STRICT_PRIO_CFG                              0xD22C90
+
+#define mmNIC1_QM1_HBW_RD_RATE_LIM_CFG_1                             0xD22C94
+
+#define mmNIC1_QM1_LBW_WR_RATE_LIM_CFG_0                             0xD22C98
+
+#define mmNIC1_QM1_LBW_WR_RATE_LIM_CFG_1                             0xD22C9C
+
+#define mmNIC1_QM1_HBW_RD_RATE_LIM_CFG_0                             0xD22CA0
+
+#define mmNIC1_QM1_GLBL_AXCACHE                                      0xD22CA4
+
+#define mmNIC1_QM1_IND_GW_APB_CFG                                    0xD22CB0
+
+#define mmNIC1_QM1_IND_GW_APB_WDATA                                  0xD22CB4
+
+#define mmNIC1_QM1_IND_GW_APB_RDATA                                  0xD22CB8
+
+#define mmNIC1_QM1_IND_GW_APB_STATUS                                 0xD22CBC
+
+#define mmNIC1_QM1_GLBL_ERR_ADDR_LO                                  0xD22CD0
+
+#define mmNIC1_QM1_GLBL_ERR_ADDR_HI                                  0xD22CD4
+
+#define mmNIC1_QM1_GLBL_ERR_WDATA                                    0xD22CD8
+
+#define mmNIC1_QM1_GLBL_MEM_INIT_BUSY                                0xD22D00
+
+#endif /* ASIC_REG_NIC1_QM1_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/nic2_qm0_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic2_qm0_regs.h
new file mode 100644
index 000000000000..a89116a4586f
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic2_qm0_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_NIC2_QM0_REGS_H_
+#define ASIC_REG_NIC2_QM0_REGS_H_
+
+/*
+ *****************************************
+ *   NIC2_QM0 (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmNIC2_QM0_GLBL_CFG0                                         0xD60000
+
+#define mmNIC2_QM0_GLBL_CFG1                                         0xD60004
+
+#define mmNIC2_QM0_GLBL_PROT                                         0xD60008
+
+#define mmNIC2_QM0_GLBL_ERR_CFG                                      0xD6000C
+
+#define mmNIC2_QM0_GLBL_SECURE_PROPS_0                               0xD60010
+
+#define mmNIC2_QM0_GLBL_SECURE_PROPS_1                               0xD60014
+
+#define mmNIC2_QM0_GLBL_SECURE_PROPS_2                               0xD60018
+
+#define mmNIC2_QM0_GLBL_SECURE_PROPS_3                               0xD6001C
+
+#define mmNIC2_QM0_GLBL_SECURE_PROPS_4                               0xD60020
+
+#define mmNIC2_QM0_GLBL_NON_SECURE_PROPS_0                           0xD60024
+
+#define mmNIC2_QM0_GLBL_NON_SECURE_PROPS_1                           0xD60028
+
+#define mmNIC2_QM0_GLBL_NON_SECURE_PROPS_2                           0xD6002C
+
+#define mmNIC2_QM0_GLBL_NON_SECURE_PROPS_3                           0xD60030
+
+#define mmNIC2_QM0_GLBL_NON_SECURE_PROPS_4                           0xD60034
+
+#define mmNIC2_QM0_GLBL_STS0                                         0xD60038
+
+#define mmNIC2_QM0_GLBL_STS1_0                                       0xD60040
+
+#define mmNIC2_QM0_GLBL_STS1_1                                       0xD60044
+
+#define mmNIC2_QM0_GLBL_STS1_2                                       0xD60048
+
+#define mmNIC2_QM0_GLBL_STS1_3                                       0xD6004C
+
+#define mmNIC2_QM0_GLBL_STS1_4                                       0xD60050
+
+#define mmNIC2_QM0_GLBL_MSG_EN_0                                     0xD60054
+
+#define mmNIC2_QM0_GLBL_MSG_EN_1                                     0xD60058
+
+#define mmNIC2_QM0_GLBL_MSG_EN_2                                     0xD6005C
+
+#define mmNIC2_QM0_GLBL_MSG_EN_3                                     0xD60060
+
+#define mmNIC2_QM0_GLBL_MSG_EN_4                                     0xD60068
+
+#define mmNIC2_QM0_PQ_BASE_LO_0                                      0xD60070
+
+#define mmNIC2_QM0_PQ_BASE_LO_1                                      0xD60074
+
+#define mmNIC2_QM0_PQ_BASE_LO_2                                      0xD60078
+
+#define mmNIC2_QM0_PQ_BASE_LO_3                                      0xD6007C
+
+#define mmNIC2_QM0_PQ_BASE_HI_0                                      0xD60080
+
+#define mmNIC2_QM0_PQ_BASE_HI_1                                      0xD60084
+
+#define mmNIC2_QM0_PQ_BASE_HI_2                                      0xD60088
+
+#define mmNIC2_QM0_PQ_BASE_HI_3                                      0xD6008C
+
+#define mmNIC2_QM0_PQ_SIZE_0                                         0xD60090
+
+#define mmNIC2_QM0_PQ_SIZE_1                                         0xD60094
+
+#define mmNIC2_QM0_PQ_SIZE_2                                         0xD60098
+
+#define mmNIC2_QM0_PQ_SIZE_3                                         0xD6009C
+
+#define mmNIC2_QM0_PQ_PI_0                                           0xD600A0
+
+#define mmNIC2_QM0_PQ_PI_1                                           0xD600A4
+
+#define mmNIC2_QM0_PQ_PI_2                                           0xD600A8
+
+#define mmNIC2_QM0_PQ_PI_3                                           0xD600AC
+
+#define mmNIC2_QM0_PQ_CI_0                                           0xD600B0
+
+#define mmNIC2_QM0_PQ_CI_1                                           0xD600B4
+
+#define mmNIC2_QM0_PQ_CI_2                                           0xD600B8
+
+#define mmNIC2_QM0_PQ_CI_3                                           0xD600BC
+
+#define mmNIC2_QM0_PQ_CFG0_0                                         0xD600C0
+
+#define mmNIC2_QM0_PQ_CFG0_1                                         0xD600C4
+
+#define mmNIC2_QM0_PQ_CFG0_2                                         0xD600C8
+
+#define mmNIC2_QM0_PQ_CFG0_3                                         0xD600CC
+
+#define mmNIC2_QM0_PQ_CFG1_0                                         0xD600D0
+
+#define mmNIC2_QM0_PQ_CFG1_1                                         0xD600D4
+
+#define mmNIC2_QM0_PQ_CFG1_2                                         0xD600D8
+
+#define mmNIC2_QM0_PQ_CFG1_3                                         0xD600DC
+
+#define mmNIC2_QM0_PQ_ARUSER_31_11_0                                 0xD600E0
+
+#define mmNIC2_QM0_PQ_ARUSER_31_11_1                                 0xD600E4
+
+#define mmNIC2_QM0_PQ_ARUSER_31_11_2                                 0xD600E8
+
+#define mmNIC2_QM0_PQ_ARUSER_31_11_3                                 0xD600EC
+
+#define mmNIC2_QM0_PQ_STS0_0                                         0xD600F0
+
+#define mmNIC2_QM0_PQ_STS0_1                                         0xD600F4
+
+#define mmNIC2_QM0_PQ_STS0_2                                         0xD600F8
+
+#define mmNIC2_QM0_PQ_STS0_3                                         0xD600FC
+
+#define mmNIC2_QM0_PQ_STS1_0                                         0xD60100
+
+#define mmNIC2_QM0_PQ_STS1_1                                         0xD60104
+
+#define mmNIC2_QM0_PQ_STS1_2                                         0xD60108
+
+#define mmNIC2_QM0_PQ_STS1_3                                         0xD6010C
+
+#define mmNIC2_QM0_CQ_CFG0_0                                         0xD60110
+
+#define mmNIC2_QM0_CQ_CFG0_1                                         0xD60114
+
+#define mmNIC2_QM0_CQ_CFG0_2                                         0xD60118
+
+#define mmNIC2_QM0_CQ_CFG0_3                                         0xD6011C
+
+#define mmNIC2_QM0_CQ_CFG0_4                                         0xD60120
+
+#define mmNIC2_QM0_CQ_CFG1_0                                         0xD60124
+
+#define mmNIC2_QM0_CQ_CFG1_1                                         0xD60128
+
+#define mmNIC2_QM0_CQ_CFG1_2                                         0xD6012C
+
+#define mmNIC2_QM0_CQ_CFG1_3                                         0xD60130
+
+#define mmNIC2_QM0_CQ_CFG1_4                                         0xD60134
+
+#define mmNIC2_QM0_CQ_ARUSER_31_11_0                                 0xD60138
+
+#define mmNIC2_QM0_CQ_ARUSER_31_11_1                                 0xD6013C
+
+#define mmNIC2_QM0_CQ_ARUSER_31_11_2                                 0xD60140
+
+#define mmNIC2_QM0_CQ_ARUSER_31_11_3                                 0xD60144
+
+#define mmNIC2_QM0_CQ_ARUSER_31_11_4                                 0xD60148
+
+#define mmNIC2_QM0_CQ_STS0_0                                         0xD6014C
+
+#define mmNIC2_QM0_CQ_STS0_1                                         0xD60150
+
+#define mmNIC2_QM0_CQ_STS0_2                                         0xD60154
+
+#define mmNIC2_QM0_CQ_STS0_3                                         0xD60158
+
+#define mmNIC2_QM0_CQ_STS0_4                                         0xD6015C
+
+#define mmNIC2_QM0_CQ_STS1_0                                         0xD60160
+
+#define mmNIC2_QM0_CQ_STS1_1                                         0xD60164
+
+#define mmNIC2_QM0_CQ_STS1_2                                         0xD60168
+
+#define mmNIC2_QM0_CQ_STS1_3                                         0xD6016C
+
+#define mmNIC2_QM0_CQ_STS1_4                                         0xD60170
+
+#define mmNIC2_QM0_CQ_PTR_LO_0                                       0xD60174
+
+#define mmNIC2_QM0_CQ_PTR_HI_0                                       0xD60178
+
+#define mmNIC2_QM0_CQ_TSIZE_0                                        0xD6017C
+
+#define mmNIC2_QM0_CQ_CTL_0                                          0xD60180
+
+#define mmNIC2_QM0_CQ_PTR_LO_1                                       0xD60184
+
+#define mmNIC2_QM0_CQ_PTR_HI_1                                       0xD60188
+
+#define mmNIC2_QM0_CQ_TSIZE_1                                        0xD6018C
+
+#define mmNIC2_QM0_CQ_CTL_1                                          0xD60190
+
+#define mmNIC2_QM0_CQ_PTR_LO_2                                       0xD60194
+
+#define mmNIC2_QM0_CQ_PTR_HI_2                                       0xD60198
+
+#define mmNIC2_QM0_CQ_TSIZE_2                                        0xD6019C
+
+#define mmNIC2_QM0_CQ_CTL_2                                          0xD601A0
+
+#define mmNIC2_QM0_CQ_PTR_LO_3                                       0xD601A4
+
+#define mmNIC2_QM0_CQ_PTR_HI_3                                       0xD601A8
+
+#define mmNIC2_QM0_CQ_TSIZE_3                                        0xD601AC
+
+#define mmNIC2_QM0_CQ_CTL_3                                          0xD601B0
+
+#define mmNIC2_QM0_CQ_PTR_LO_4                                       0xD601B4
+
+#define mmNIC2_QM0_CQ_PTR_HI_4                                       0xD601B8
+
+#define mmNIC2_QM0_CQ_TSIZE_4                                        0xD601BC
+
+#define mmNIC2_QM0_CQ_CTL_4                                          0xD601C0
+
+#define mmNIC2_QM0_CQ_PTR_LO_STS_0                                   0xD601C4
+
+#define mmNIC2_QM0_CQ_PTR_LO_STS_1                                   0xD601C8
+
+#define mmNIC2_QM0_CQ_PTR_LO_STS_2                                   0xD601CC
+
+#define mmNIC2_QM0_CQ_PTR_LO_STS_3                                   0xD601D0
+
+#define mmNIC2_QM0_CQ_PTR_LO_STS_4                                   0xD601D4
+
+#define mmNIC2_QM0_CQ_PTR_HI_STS_0                                   0xD601D8
+
+#define mmNIC2_QM0_CQ_PTR_HI_STS_1                                   0xD601DC
+
+#define mmNIC2_QM0_CQ_PTR_HI_STS_2                                   0xD601E0
+
+#define mmNIC2_QM0_CQ_PTR_HI_STS_3                                   0xD601E4
+
+#define mmNIC2_QM0_CQ_PTR_HI_STS_4                                   0xD601E8
+
+#define mmNIC2_QM0_CQ_TSIZE_STS_0                                    0xD601EC
+
+#define mmNIC2_QM0_CQ_TSIZE_STS_1                                    0xD601F0
+
+#define mmNIC2_QM0_CQ_TSIZE_STS_2                                    0xD601F4
+
+#define mmNIC2_QM0_CQ_TSIZE_STS_3                                    0xD601F8
+
+#define mmNIC2_QM0_CQ_TSIZE_STS_4                                    0xD601FC
+
+#define mmNIC2_QM0_CQ_CTL_STS_0                                      0xD60200
+
+#define mmNIC2_QM0_CQ_CTL_STS_1                                      0xD60204
+
+#define mmNIC2_QM0_CQ_CTL_STS_2                                      0xD60208
+
+#define mmNIC2_QM0_CQ_CTL_STS_3                                      0xD6020C
+
+#define mmNIC2_QM0_CQ_CTL_STS_4                                      0xD60210
+
+#define mmNIC2_QM0_CQ_IFIFO_CNT_0                                    0xD60214
+
+#define mmNIC2_QM0_CQ_IFIFO_CNT_1                                    0xD60218
+
+#define mmNIC2_QM0_CQ_IFIFO_CNT_2                                    0xD6021C
+
+#define mmNIC2_QM0_CQ_IFIFO_CNT_3                                    0xD60220
+
+#define mmNIC2_QM0_CQ_IFIFO_CNT_4                                    0xD60224
+
+#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_LO_0                            0xD60228
+
+#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_LO_1                            0xD6022C
+
+#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_LO_2                            0xD60230
+
+#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_LO_3                            0xD60234
+
+#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_LO_4                            0xD60238
+
+#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_HI_0                            0xD6023C
+
+#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_HI_1                            0xD60240
+
+#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_HI_2                            0xD60244
+
+#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_HI_3                            0xD60248
+
+#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_HI_4                            0xD6024C
+
+#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_LO_0                            0xD60250
+
+#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_LO_1                            0xD60254
+
+#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_LO_2                            0xD60258
+
+#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_LO_3                            0xD6025C
+
+#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_LO_4                            0xD60260
+
+#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_HI_0                            0xD60264
+
+#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_HI_1                            0xD60268
+
+#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_HI_2                            0xD6026C
+
+#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_HI_3                            0xD60270
+
+#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_HI_4                            0xD60274
+
+#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_LO_0                            0xD60278
+
+#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_LO_1                            0xD6027C
+
+#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_LO_2                            0xD60280
+
+#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_LO_3                            0xD60284
+
+#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_LO_4                            0xD60288
+
+#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_HI_0                            0xD6028C
+
+#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_HI_1                            0xD60290
+
+#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_HI_2                            0xD60294
+
+#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_HI_3                            0xD60298
+
+#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_HI_4                            0xD6029C
+
+#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_LO_0                            0xD602A0
+
+#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_LO_1                            0xD602A4
+
+#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_LO_2                            0xD602A8
+
+#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_LO_3                            0xD602AC
+
+#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_LO_4                            0xD602B0
+
+#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_HI_0                            0xD602B4
+
+#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_HI_1                            0xD602B8
+
+#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_HI_2                            0xD602BC
+
+#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_HI_3                            0xD602C0
+
+#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_HI_4                            0xD602C4
+
+#define mmNIC2_QM0_CP_LDMA_TSIZE_OFFSET_0                            0xD602C8
+
+#define mmNIC2_QM0_CP_LDMA_TSIZE_OFFSET_1                            0xD602CC
+
+#define mmNIC2_QM0_CP_LDMA_TSIZE_OFFSET_2                            0xD602D0
+
+#define mmNIC2_QM0_CP_LDMA_TSIZE_OFFSET_3                            0xD602D4
+
+#define mmNIC2_QM0_CP_LDMA_TSIZE_OFFSET_4                            0xD602D8
+
+#define mmNIC2_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_0                      0xD602E0
+
+#define mmNIC2_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_1                      0xD602E4
+
+#define mmNIC2_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_2                      0xD602E8
+
+#define mmNIC2_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_3                      0xD602EC
+
+#define mmNIC2_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_4                      0xD602F0
+
+#define mmNIC2_QM0_CP_LDMA_DST_BASE_LO_OFFSET_0                      0xD602F4
+
+#define mmNIC2_QM0_CP_LDMA_DST_BASE_LO_OFFSET_1                      0xD602F8
+
+#define mmNIC2_QM0_CP_LDMA_DST_BASE_LO_OFFSET_2                      0xD602FC
+
+#define mmNIC2_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3                      0xD60300
+
+#define mmNIC2_QM0_CP_LDMA_DST_BASE_LO_OFFSET_4                      0xD60304
+
+#define mmNIC2_QM0_CP_FENCE0_RDATA_0                                 0xD60308
+
+#define mmNIC2_QM0_CP_FENCE0_RDATA_1                                 0xD6030C
+
+#define mmNIC2_QM0_CP_FENCE0_RDATA_2                                 0xD60310
+
+#define mmNIC2_QM0_CP_FENCE0_RDATA_3                                 0xD60314
+
+#define mmNIC2_QM0_CP_FENCE0_RDATA_4                                 0xD60318
+
+#define mmNIC2_QM0_CP_FENCE1_RDATA_0                                 0xD6031C
+
+#define mmNIC2_QM0_CP_FENCE1_RDATA_1                                 0xD60320
+
+#define mmNIC2_QM0_CP_FENCE1_RDATA_2                                 0xD60324
+
+#define mmNIC2_QM0_CP_FENCE1_RDATA_3                                 0xD60328
+
+#define mmNIC2_QM0_CP_FENCE1_RDATA_4                                 0xD6032C
+
+#define mmNIC2_QM0_CP_FENCE2_RDATA_0                                 0xD60330
+
+#define mmNIC2_QM0_CP_FENCE2_RDATA_1                                 0xD60334
+
+#define mmNIC2_QM0_CP_FENCE2_RDATA_2                                 0xD60338
+
+#define mmNIC2_QM0_CP_FENCE2_RDATA_3                                 0xD6033C
+
+#define mmNIC2_QM0_CP_FENCE2_RDATA_4                                 0xD60340
+
+#define mmNIC2_QM0_CP_FENCE3_RDATA_0                                 0xD60344
+
+#define mmNIC2_QM0_CP_FENCE3_RDATA_1                                 0xD60348
+
+#define mmNIC2_QM0_CP_FENCE3_RDATA_2                                 0xD6034C
+
+#define mmNIC2_QM0_CP_FENCE3_RDATA_3                                 0xD60350
+
+#define mmNIC2_QM0_CP_FENCE3_RDATA_4                                 0xD60354
+
+#define mmNIC2_QM0_CP_FENCE0_CNT_0                                   0xD60358
+
+#define mmNIC2_QM0_CP_FENCE0_CNT_1                                   0xD6035C
+
+#define mmNIC2_QM0_CP_FENCE0_CNT_2                                   0xD60360
+
+#define mmNIC2_QM0_CP_FENCE0_CNT_3                                   0xD60364
+
+#define mmNIC2_QM0_CP_FENCE0_CNT_4                                   0xD60368
+
+#define mmNIC2_QM0_CP_FENCE1_CNT_0                                   0xD6036C
+
+#define mmNIC2_QM0_CP_FENCE1_CNT_1                                   0xD60370
+
+#define mmNIC2_QM0_CP_FENCE1_CNT_2                                   0xD60374
+
+#define mmNIC2_QM0_CP_FENCE1_CNT_3                                   0xD60378
+
+#define mmNIC2_QM0_CP_FENCE1_CNT_4                                   0xD6037C
+
+#define mmNIC2_QM0_CP_FENCE2_CNT_0                                   0xD60380
+
+#define mmNIC2_QM0_CP_FENCE2_CNT_1                                   0xD60384
+
+#define mmNIC2_QM0_CP_FENCE2_CNT_2                                   0xD60388
+
+#define mmNIC2_QM0_CP_FENCE2_CNT_3                                   0xD6038C
+
+#define mmNIC2_QM0_CP_FENCE2_CNT_4                                   0xD60390
+
+#define mmNIC2_QM0_CP_FENCE3_CNT_0                                   0xD60394
+
+#define mmNIC2_QM0_CP_FENCE3_CNT_1                                   0xD60398
+
+#define mmNIC2_QM0_CP_FENCE3_CNT_2                                   0xD6039C
+
+#define mmNIC2_QM0_CP_FENCE3_CNT_3                                   0xD603A0
+
+#define mmNIC2_QM0_CP_FENCE3_CNT_4                                   0xD603A4
+
+#define mmNIC2_QM0_CP_STS_0                                          0xD603A8
+
+#define mmNIC2_QM0_CP_STS_1                                          0xD603AC
+
+#define mmNIC2_QM0_CP_STS_2                                          0xD603B0
+
+#define mmNIC2_QM0_CP_STS_3                                          0xD603B4
+
+#define mmNIC2_QM0_CP_STS_4                                          0xD603B8
+
+#define mmNIC2_QM0_CP_CURRENT_INST_LO_0                              0xD603BC
+
+#define mmNIC2_QM0_CP_CURRENT_INST_LO_1                              0xD603C0
+
+#define mmNIC2_QM0_CP_CURRENT_INST_LO_2                              0xD603C4
+
+#define mmNIC2_QM0_CP_CURRENT_INST_LO_3                              0xD603C8
+
+#define mmNIC2_QM0_CP_CURRENT_INST_LO_4                              0xD603CC
+
+#define mmNIC2_QM0_CP_CURRENT_INST_HI_0                              0xD603D0
+
+#define mmNIC2_QM0_CP_CURRENT_INST_HI_1                              0xD603D4
+
+#define mmNIC2_QM0_CP_CURRENT_INST_HI_2                              0xD603D8
+
+#define mmNIC2_QM0_CP_CURRENT_INST_HI_3                              0xD603DC
+
+#define mmNIC2_QM0_CP_CURRENT_INST_HI_4                              0xD603E0
+
+#define mmNIC2_QM0_CP_BARRIER_CFG_0                                  0xD603F4
+
+#define mmNIC2_QM0_CP_BARRIER_CFG_1                                  0xD603F8
+
+#define mmNIC2_QM0_CP_BARRIER_CFG_2                                  0xD603FC
+
+#define mmNIC2_QM0_CP_BARRIER_CFG_3                                  0xD60400
+
+#define mmNIC2_QM0_CP_BARRIER_CFG_4                                  0xD60404
+
+#define mmNIC2_QM0_CP_DBG_0_0                                        0xD60408
+
+#define mmNIC2_QM0_CP_DBG_0_1                                        0xD6040C
+
+#define mmNIC2_QM0_CP_DBG_0_2                                        0xD60410
+
+#define mmNIC2_QM0_CP_DBG_0_3                                        0xD60414
+
+#define mmNIC2_QM0_CP_DBG_0_4                                        0xD60418
+
+#define mmNIC2_QM0_CP_ARUSER_31_11_0                                 0xD6041C
+
+#define mmNIC2_QM0_CP_ARUSER_31_11_1                                 0xD60420
+
+#define mmNIC2_QM0_CP_ARUSER_31_11_2                                 0xD60424
+
+#define mmNIC2_QM0_CP_ARUSER_31_11_3                                 0xD60428
+
+#define mmNIC2_QM0_CP_ARUSER_31_11_4                                 0xD6042C
+
+#define mmNIC2_QM0_CP_AWUSER_31_11_0                                 0xD60430
+
+#define mmNIC2_QM0_CP_AWUSER_31_11_1                                 0xD60434
+
+#define mmNIC2_QM0_CP_AWUSER_31_11_2                                 0xD60438
+
+#define mmNIC2_QM0_CP_AWUSER_31_11_3                                 0xD6043C
+
+#define mmNIC2_QM0_CP_AWUSER_31_11_4                                 0xD60440
+
+#define mmNIC2_QM0_ARB_CFG_0                                         0xD60A00
+
+#define mmNIC2_QM0_ARB_CHOISE_Q_PUSH                                 0xD60A04
+
+#define mmNIC2_QM0_ARB_WRR_WEIGHT_0                                  0xD60A08
+
+#define mmNIC2_QM0_ARB_WRR_WEIGHT_1                                  0xD60A0C
+
+#define mmNIC2_QM0_ARB_WRR_WEIGHT_2                                  0xD60A10
+
+#define mmNIC2_QM0_ARB_WRR_WEIGHT_3                                  0xD60A14
+
+#define mmNIC2_QM0_ARB_CFG_1                                         0xD60A18
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_0                              0xD60A20
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_1                              0xD60A24
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_2                              0xD60A28
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_3                              0xD60A2C
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_4                              0xD60A30
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_5                              0xD60A34
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_6                              0xD60A38
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_7                              0xD60A3C
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_8                              0xD60A40
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_9                              0xD60A44
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_10                             0xD60A48
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_11                             0xD60A4C
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_12                             0xD60A50
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_13                             0xD60A54
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_14                             0xD60A58
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_15                             0xD60A5C
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_16                             0xD60A60
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_17                             0xD60A64
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_18                             0xD60A68
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_19                             0xD60A6C
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_20                             0xD60A70
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_21                             0xD60A74
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_22                             0xD60A78
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_23                             0xD60A7C
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_24                             0xD60A80
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_25                             0xD60A84
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_26                             0xD60A88
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_27                             0xD60A8C
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_28                             0xD60A90
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_29                             0xD60A94
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_30                             0xD60A98
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_31                             0xD60A9C
+
+#define mmNIC2_QM0_ARB_MST_CRED_INC                                  0xD60AA0
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_0                        0xD60AA4
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_1                        0xD60AA8
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_2                        0xD60AAC
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_3                        0xD60AB0
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_4                        0xD60AB4
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_5                        0xD60AB8
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_6                        0xD60ABC
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_7                        0xD60AC0
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_8                        0xD60AC4
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_9                        0xD60AC8
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_10                       0xD60ACC
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_11                       0xD60AD0
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_12                       0xD60AD4
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_13                       0xD60AD8
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_14                       0xD60ADC
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_15                       0xD60AE0
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_16                       0xD60AE4
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_17                       0xD60AE8
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_18                       0xD60AEC
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_19                       0xD60AF0
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_20                       0xD60AF4
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_21                       0xD60AF8
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_22                       0xD60AFC
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_23                       0xD60B00
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_24                       0xD60B04
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_25                       0xD60B08
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_26                       0xD60B0C
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_27                       0xD60B10
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_28                       0xD60B14
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_29                       0xD60B18
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_30                       0xD60B1C
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_31                       0xD60B20
+
+#define mmNIC2_QM0_ARB_SLV_MASTER_INC_CRED_OFST                      0xD60B28
+
+#define mmNIC2_QM0_ARB_MST_SLAVE_EN                                  0xD60B2C
+
+#define mmNIC2_QM0_ARB_MST_QUIET_PER                                 0xD60B34
+
+#define mmNIC2_QM0_ARB_SLV_CHOISE_WDT                                0xD60B38
+
+#define mmNIC2_QM0_ARB_SLV_ID                                        0xD60B3C
+
+#define mmNIC2_QM0_ARB_MSG_MAX_INFLIGHT                              0xD60B44
+
+#define mmNIC2_QM0_ARB_MSG_AWUSER_31_11                              0xD60B48
+
+#define mmNIC2_QM0_ARB_MSG_AWUSER_SEC_PROP                           0xD60B4C
+
+#define mmNIC2_QM0_ARB_MSG_AWUSER_NON_SEC_PROP                       0xD60B50
+
+#define mmNIC2_QM0_ARB_BASE_LO                                       0xD60B54
+
+#define mmNIC2_QM0_ARB_BASE_HI                                       0xD60B58
+
+#define mmNIC2_QM0_ARB_STATE_STS                                     0xD60B80
+
+#define mmNIC2_QM0_ARB_CHOISE_FULLNESS_STS                           0xD60B84
+
+#define mmNIC2_QM0_ARB_MSG_STS                                       0xD60B88
+
+#define mmNIC2_QM0_ARB_SLV_CHOISE_Q_HEAD                             0xD60B8C
+
+#define mmNIC2_QM0_ARB_ERR_CAUSE                                     0xD60B9C
+
+#define mmNIC2_QM0_ARB_ERR_MSG_EN                                    0xD60BA0
+
+#define mmNIC2_QM0_ARB_ERR_STS_DRP                                   0xD60BA8
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_0                                0xD60BB0
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_1                                0xD60BB4
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_2                                0xD60BB8
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_3                                0xD60BBC
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_4                                0xD60BC0
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_5                                0xD60BC4
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_6                                0xD60BC8
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_7                                0xD60BCC
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_8                                0xD60BD0
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_9                                0xD60BD4
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_10                               0xD60BD8
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_11                               0xD60BDC
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_12                               0xD60BE0
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_13                               0xD60BE4
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_14                               0xD60BE8
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_15                               0xD60BEC
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_16                               0xD60BF0
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_17                               0xD60BF4
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_18                               0xD60BF8
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_19                               0xD60BFC
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_20                               0xD60C00
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_21                               0xD60C04
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_22                               0xD60C08
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_23                               0xD60C0C
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_24                               0xD60C10
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_25                               0xD60C14
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_26                               0xD60C18
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_27                               0xD60C1C
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_28                               0xD60C20
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_29                               0xD60C24
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_30                               0xD60C28
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_31                               0xD60C2C
+
+#define mmNIC2_QM0_CGM_CFG                                           0xD60C70
+
+#define mmNIC2_QM0_CGM_STS                                           0xD60C74
+
+#define mmNIC2_QM0_CGM_CFG1                                          0xD60C78
+
+#define mmNIC2_QM0_LOCAL_RANGE_BASE                                  0xD60C80
+
+#define mmNIC2_QM0_LOCAL_RANGE_SIZE                                  0xD60C84
+
+#define mmNIC2_QM0_CSMR_STRICT_PRIO_CFG                              0xD60C90
+
+#define mmNIC2_QM0_HBW_RD_RATE_LIM_CFG_1                             0xD60C94
+
+#define mmNIC2_QM0_LBW_WR_RATE_LIM_CFG_0                             0xD60C98
+
+#define mmNIC2_QM0_LBW_WR_RATE_LIM_CFG_1                             0xD60C9C
+
+#define mmNIC2_QM0_HBW_RD_RATE_LIM_CFG_0                             0xD60CA0
+
+#define mmNIC2_QM0_GLBL_AXCACHE                                      0xD60CA4
+
+#define mmNIC2_QM0_IND_GW_APB_CFG                                    0xD60CB0
+
+#define mmNIC2_QM0_IND_GW_APB_WDATA                                  0xD60CB4
+
+#define mmNIC2_QM0_IND_GW_APB_RDATA                                  0xD60CB8
+
+#define mmNIC2_QM0_IND_GW_APB_STATUS                                 0xD60CBC
+
+#define mmNIC2_QM0_GLBL_ERR_ADDR_LO                                  0xD60CD0
+
+#define mmNIC2_QM0_GLBL_ERR_ADDR_HI                                  0xD60CD4
+
+#define mmNIC2_QM0_GLBL_ERR_WDATA                                    0xD60CD8
+
+#define mmNIC2_QM0_GLBL_MEM_INIT_BUSY                                0xD60D00
+
+#endif /* ASIC_REG_NIC2_QM0_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/nic2_qm1_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic2_qm1_regs.h
new file mode 100644
index 000000000000..b7f091ddc89c
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic2_qm1_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_NIC2_QM1_REGS_H_
+#define ASIC_REG_NIC2_QM1_REGS_H_
+
+/*
+ *****************************************
+ *   NIC2_QM1 (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmNIC2_QM1_GLBL_CFG0                                         0xD62000
+
+#define mmNIC2_QM1_GLBL_CFG1                                         0xD62004
+
+#define mmNIC2_QM1_GLBL_PROT                                         0xD62008
+
+#define mmNIC2_QM1_GLBL_ERR_CFG                                      0xD6200C
+
+#define mmNIC2_QM1_GLBL_SECURE_PROPS_0                               0xD62010
+
+#define mmNIC2_QM1_GLBL_SECURE_PROPS_1                               0xD62014
+
+#define mmNIC2_QM1_GLBL_SECURE_PROPS_2                               0xD62018
+
+#define mmNIC2_QM1_GLBL_SECURE_PROPS_3                               0xD6201C
+
+#define mmNIC2_QM1_GLBL_SECURE_PROPS_4                               0xD62020
+
+#define mmNIC2_QM1_GLBL_NON_SECURE_PROPS_0                           0xD62024
+
+#define mmNIC2_QM1_GLBL_NON_SECURE_PROPS_1                           0xD62028
+
+#define mmNIC2_QM1_GLBL_NON_SECURE_PROPS_2                           0xD6202C
+
+#define mmNIC2_QM1_GLBL_NON_SECURE_PROPS_3                           0xD62030
+
+#define mmNIC2_QM1_GLBL_NON_SECURE_PROPS_4                           0xD62034
+
+#define mmNIC2_QM1_GLBL_STS0                                         0xD62038
+
+#define mmNIC2_QM1_GLBL_STS1_0                                       0xD62040
+
+#define mmNIC2_QM1_GLBL_STS1_1                                       0xD62044
+
+#define mmNIC2_QM1_GLBL_STS1_2                                       0xD62048
+
+#define mmNIC2_QM1_GLBL_STS1_3                                       0xD6204C
+
+#define mmNIC2_QM1_GLBL_STS1_4                                       0xD62050
+
+#define mmNIC2_QM1_GLBL_MSG_EN_0                                     0xD62054
+
+#define mmNIC2_QM1_GLBL_MSG_EN_1                                     0xD62058
+
+#define mmNIC2_QM1_GLBL_MSG_EN_2                                     0xD6205C
+
+#define mmNIC2_QM1_GLBL_MSG_EN_3                                     0xD62060
+
+#define mmNIC2_QM1_GLBL_MSG_EN_4                                     0xD62068
+
+#define mmNIC2_QM1_PQ_BASE_LO_0                                      0xD62070
+
+#define mmNIC2_QM1_PQ_BASE_LO_1                                      0xD62074
+
+#define mmNIC2_QM1_PQ_BASE_LO_2                                      0xD62078
+
+#define mmNIC2_QM1_PQ_BASE_LO_3                                      0xD6207C
+
+#define mmNIC2_QM1_PQ_BASE_HI_0                                      0xD62080
+
+#define mmNIC2_QM1_PQ_BASE_HI_1                                      0xD62084
+
+#define mmNIC2_QM1_PQ_BASE_HI_2                                      0xD62088
+
+#define mmNIC2_QM1_PQ_BASE_HI_3                                      0xD6208C
+
+#define mmNIC2_QM1_PQ_SIZE_0                                         0xD62090
+
+#define mmNIC2_QM1_PQ_SIZE_1                                         0xD62094
+
+#define mmNIC2_QM1_PQ_SIZE_2                                         0xD62098
+
+#define mmNIC2_QM1_PQ_SIZE_3                                         0xD6209C
+
+#define mmNIC2_QM1_PQ_PI_0                                           0xD620A0
+
+#define mmNIC2_QM1_PQ_PI_1                                           0xD620A4
+
+#define mmNIC2_QM1_PQ_PI_2                                           0xD620A8
+
+#define mmNIC2_QM1_PQ_PI_3                                           0xD620AC
+
+#define mmNIC2_QM1_PQ_CI_0                                           0xD620B0
+
+#define mmNIC2_QM1_PQ_CI_1                                           0xD620B4
+
+#define mmNIC2_QM1_PQ_CI_2                                           0xD620B8
+
+#define mmNIC2_QM1_PQ_CI_3                                           0xD620BC
+
+#define mmNIC2_QM1_PQ_CFG0_0                                         0xD620C0
+
+#define mmNIC2_QM1_PQ_CFG0_1                                         0xD620C4
+
+#define mmNIC2_QM1_PQ_CFG0_2                                         0xD620C8
+
+#define mmNIC2_QM1_PQ_CFG0_3                                         0xD620CC
+
+#define mmNIC2_QM1_PQ_CFG1_0                                         0xD620D0
+
+#define mmNIC2_QM1_PQ_CFG1_1                                         0xD620D4
+
+#define mmNIC2_QM1_PQ_CFG1_2                                         0xD620D8
+
+#define mmNIC2_QM1_PQ_CFG1_3                                         0xD620DC
+
+#define mmNIC2_QM1_PQ_ARUSER_31_11_0                                 0xD620E0
+
+#define mmNIC2_QM1_PQ_ARUSER_31_11_1                                 0xD620E4
+
+#define mmNIC2_QM1_PQ_ARUSER_31_11_2                                 0xD620E8
+
+#define mmNIC2_QM1_PQ_ARUSER_31_11_3                                 0xD620EC
+
+#define mmNIC2_QM1_PQ_STS0_0                                         0xD620F0
+
+#define mmNIC2_QM1_PQ_STS0_1                                         0xD620F4
+
+#define mmNIC2_QM1_PQ_STS0_2                                         0xD620F8
+
+#define mmNIC2_QM1_PQ_STS0_3                                         0xD620FC
+
+#define mmNIC2_QM1_PQ_STS1_0                                         0xD62100
+
+#define mmNIC2_QM1_PQ_STS1_1                                         0xD62104
+
+#define mmNIC2_QM1_PQ_STS1_2                                         0xD62108
+
+#define mmNIC2_QM1_PQ_STS1_3                                         0xD6210C
+
+#define mmNIC2_QM1_CQ_CFG0_0                                         0xD62110
+
+#define mmNIC2_QM1_CQ_CFG0_1                                         0xD62114
+
+#define mmNIC2_QM1_CQ_CFG0_2                                         0xD62118
+
+#define mmNIC2_QM1_CQ_CFG0_3                                         0xD6211C
+
+#define mmNIC2_QM1_CQ_CFG0_4                                         0xD62120
+
+#define mmNIC2_QM1_CQ_CFG1_0                                         0xD62124
+
+#define mmNIC2_QM1_CQ_CFG1_1                                         0xD62128
+
+#define mmNIC2_QM1_CQ_CFG1_2                                         0xD6212C
+
+#define mmNIC2_QM1_CQ_CFG1_3                                         0xD62130
+
+#define mmNIC2_QM1_CQ_CFG1_4                                         0xD62134
+
+#define mmNIC2_QM1_CQ_ARUSER_31_11_0                                 0xD62138
+
+#define mmNIC2_QM1_CQ_ARUSER_31_11_1                                 0xD6213C
+
+#define mmNIC2_QM1_CQ_ARUSER_31_11_2                                 0xD62140
+
+#define mmNIC2_QM1_CQ_ARUSER_31_11_3                                 0xD62144
+
+#define mmNIC2_QM1_CQ_ARUSER_31_11_4                                 0xD62148
+
+#define mmNIC2_QM1_CQ_STS0_0                                         0xD6214C
+
+#define mmNIC2_QM1_CQ_STS0_1                                         0xD62150
+
+#define mmNIC2_QM1_CQ_STS0_2                                         0xD62154
+
+#define mmNIC2_QM1_CQ_STS0_3                                         0xD62158
+
+#define mmNIC2_QM1_CQ_STS0_4                                         0xD6215C
+
+#define mmNIC2_QM1_CQ_STS1_0                                         0xD62160
+
+#define mmNIC2_QM1_CQ_STS1_1                                         0xD62164
+
+#define mmNIC2_QM1_CQ_STS1_2                                         0xD62168
+
+#define mmNIC2_QM1_CQ_STS1_3                                         0xD6216C
+
+#define mmNIC2_QM1_CQ_STS1_4                                         0xD62170
+
+#define mmNIC2_QM1_CQ_PTR_LO_0                                       0xD62174
+
+#define mmNIC2_QM1_CQ_PTR_HI_0                                       0xD62178
+
+#define mmNIC2_QM1_CQ_TSIZE_0                                        0xD6217C
+
+#define mmNIC2_QM1_CQ_CTL_0                                          0xD62180
+
+#define mmNIC2_QM1_CQ_PTR_LO_1                                       0xD62184
+
+#define mmNIC2_QM1_CQ_PTR_HI_1                                       0xD62188
+
+#define mmNIC2_QM1_CQ_TSIZE_1                                        0xD6218C
+
+#define mmNIC2_QM1_CQ_CTL_1                                          0xD62190
+
+#define mmNIC2_QM1_CQ_PTR_LO_2                                       0xD62194
+
+#define mmNIC2_QM1_CQ_PTR_HI_2                                       0xD62198
+
+#define mmNIC2_QM1_CQ_TSIZE_2                                        0xD6219C
+
+#define mmNIC2_QM1_CQ_CTL_2                                          0xD621A0
+
+#define mmNIC2_QM1_CQ_PTR_LO_3                                       0xD621A4
+
+#define mmNIC2_QM1_CQ_PTR_HI_3                                       0xD621A8
+
+#define mmNIC2_QM1_CQ_TSIZE_3                                        0xD621AC
+
+#define mmNIC2_QM1_CQ_CTL_3                                          0xD621B0
+
+#define mmNIC2_QM1_CQ_PTR_LO_4                                       0xD621B4
+
+#define mmNIC2_QM1_CQ_PTR_HI_4                                       0xD621B8
+
+#define mmNIC2_QM1_CQ_TSIZE_4                                        0xD621BC
+
+#define mmNIC2_QM1_CQ_CTL_4                                          0xD621C0
+
+#define mmNIC2_QM1_CQ_PTR_LO_STS_0                                   0xD621C4
+
+#define mmNIC2_QM1_CQ_PTR_LO_STS_1                                   0xD621C8
+
+#define mmNIC2_QM1_CQ_PTR_LO_STS_2                                   0xD621CC
+
+#define mmNIC2_QM1_CQ_PTR_LO_STS_3                                   0xD621D0
+
+#define mmNIC2_QM1_CQ_PTR_LO_STS_4                                   0xD621D4
+
+#define mmNIC2_QM1_CQ_PTR_HI_STS_0                                   0xD621D8
+
+#define mmNIC2_QM1_CQ_PTR_HI_STS_1                                   0xD621DC
+
+#define mmNIC2_QM1_CQ_PTR_HI_STS_2                                   0xD621E0
+
+#define mmNIC2_QM1_CQ_PTR_HI_STS_3                                   0xD621E4
+
+#define mmNIC2_QM1_CQ_PTR_HI_STS_4                                   0xD621E8
+
+#define mmNIC2_QM1_CQ_TSIZE_STS_0                                    0xD621EC
+
+#define mmNIC2_QM1_CQ_TSIZE_STS_1                                    0xD621F0
+
+#define mmNIC2_QM1_CQ_TSIZE_STS_2                                    0xD621F4
+
+#define mmNIC2_QM1_CQ_TSIZE_STS_3                                    0xD621F8
+
+#define mmNIC2_QM1_CQ_TSIZE_STS_4                                    0xD621FC
+
+#define mmNIC2_QM1_CQ_CTL_STS_0                                      0xD62200
+
+#define mmNIC2_QM1_CQ_CTL_STS_1                                      0xD62204
+
+#define mmNIC2_QM1_CQ_CTL_STS_2                                      0xD62208
+
+#define mmNIC2_QM1_CQ_CTL_STS_3                                      0xD6220C
+
+#define mmNIC2_QM1_CQ_CTL_STS_4                                      0xD62210
+
+#define mmNIC2_QM1_CQ_IFIFO_CNT_0                                    0xD62214
+
+#define mmNIC2_QM1_CQ_IFIFO_CNT_1                                    0xD62218
+
+#define mmNIC2_QM1_CQ_IFIFO_CNT_2                                    0xD6221C
+
+#define mmNIC2_QM1_CQ_IFIFO_CNT_3                                    0xD62220
+
+#define mmNIC2_QM1_CQ_IFIFO_CNT_4                                    0xD62224
+
+#define mmNIC2_QM1_CP_MSG_BASE0_ADDR_LO_0                            0xD62228
+
+#define mmNIC2_QM1_CP_MSG_BASE0_ADDR_LO_1                            0xD6222C
+
+#define mmNIC2_QM1_CP_MSG_BASE0_ADDR_LO_2                            0xD62230
+
+#define mmNIC2_QM1_CP_MSG_BASE0_ADDR_LO_3                            0xD62234
+
+#define mmNIC2_QM1_CP_MSG_BASE0_ADDR_LO_4                            0xD62238
+
+#define mmNIC2_QM1_CP_MSG_BASE0_ADDR_HI_0                            0xD6223C
+
+#define mmNIC2_QM1_CP_MSG_BASE0_ADDR_HI_1                            0xD62240
+
+#define mmNIC2_QM1_CP_MSG_BASE0_ADDR_HI_2                            0xD62244
+
+#define mmNIC2_QM1_CP_MSG_BASE0_ADDR_HI_3                            0xD62248
+
+#define mmNIC2_QM1_CP_MSG_BASE0_ADDR_HI_4                            0xD6224C
+
+#define mmNIC2_QM1_CP_MSG_BASE1_ADDR_LO_0                            0xD62250
+
+#define mmNIC2_QM1_CP_MSG_BASE1_ADDR_LO_1                            0xD62254
+
+#define mmNIC2_QM1_CP_MSG_BASE1_ADDR_LO_2                            0xD62258
+
+#define mmNIC2_QM1_CP_MSG_BASE1_ADDR_LO_3                            0xD6225C
+
+#define mmNIC2_QM1_CP_MSG_BASE1_ADDR_LO_4                            0xD62260
+
+#define mmNIC2_QM1_CP_MSG_BASE1_ADDR_HI_0                            0xD62264
+
+#define mmNIC2_QM1_CP_MSG_BASE1_ADDR_HI_1                            0xD62268
+
+#define mmNIC2_QM1_CP_MSG_BASE1_ADDR_HI_2                            0xD6226C
+
+#define mmNIC2_QM1_CP_MSG_BASE1_ADDR_HI_3                            0xD62270
+
+#define mmNIC2_QM1_CP_MSG_BASE1_ADDR_HI_4                            0xD62274
+
+#define mmNIC2_QM1_CP_MSG_BASE2_ADDR_LO_0                            0xD62278
+
+#define mmNIC2_QM1_CP_MSG_BASE2_ADDR_LO_1                            0xD6227C
+
+#define mmNIC2_QM1_CP_MSG_BASE2_ADDR_LO_2                            0xD62280
+
+#define mmNIC2_QM1_CP_MSG_BASE2_ADDR_LO_3                            0xD62284
+
+#define mmNIC2_QM1_CP_MSG_BASE2_ADDR_LO_4                            0xD62288
+
+#define mmNIC2_QM1_CP_MSG_BASE2_ADDR_HI_0                            0xD6228C
+
+#define mmNIC2_QM1_CP_MSG_BASE2_ADDR_HI_1                            0xD62290
+
+#define mmNIC2_QM1_CP_MSG_BASE2_ADDR_HI_2                            0xD62294
+
+#define mmNIC2_QM1_CP_MSG_BASE2_ADDR_HI_3                            0xD62298
+
+#define mmNIC2_QM1_CP_MSG_BASE2_ADDR_HI_4                            0xD6229C
+
+#define mmNIC2_QM1_CP_MSG_BASE3_ADDR_LO_0                            0xD622A0
+
+#define mmNIC2_QM1_CP_MSG_BASE3_ADDR_LO_1                            0xD622A4
+
+#define mmNIC2_QM1_CP_MSG_BASE3_ADDR_LO_2                            0xD622A8
+
+#define mmNIC2_QM1_CP_MSG_BASE3_ADDR_LO_3                            0xD622AC
+
+#define mmNIC2_QM1_CP_MSG_BASE3_ADDR_LO_4                            0xD622B0
+
+#define mmNIC2_QM1_CP_MSG_BASE3_ADDR_HI_0                            0xD622B4
+
+#define mmNIC2_QM1_CP_MSG_BASE3_ADDR_HI_1                            0xD622B8
+
+#define mmNIC2_QM1_CP_MSG_BASE3_ADDR_HI_2                            0xD622BC
+
+#define mmNIC2_QM1_CP_MSG_BASE3_ADDR_HI_3                            0xD622C0
+
+#define mmNIC2_QM1_CP_MSG_BASE3_ADDR_HI_4                            0xD622C4
+
+#define mmNIC2_QM1_CP_LDMA_TSIZE_OFFSET_0                            0xD622C8
+
+#define mmNIC2_QM1_CP_LDMA_TSIZE_OFFSET_1                            0xD622CC
+
+#define mmNIC2_QM1_CP_LDMA_TSIZE_OFFSET_2                            0xD622D0
+
+#define mmNIC2_QM1_CP_LDMA_TSIZE_OFFSET_3                            0xD622D4
+
+#define mmNIC2_QM1_CP_LDMA_TSIZE_OFFSET_4                            0xD622D8
+
+#define mmNIC2_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_0                      0xD622E0
+
+#define mmNIC2_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_1                      0xD622E4
+
+#define mmNIC2_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_2                      0xD622E8
+
+#define mmNIC2_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_3                      0xD622EC
+
+#define mmNIC2_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_4                      0xD622F0
+
+#define mmNIC2_QM1_CP_LDMA_DST_BASE_LO_OFFSET_0                      0xD622F4
+
+#define mmNIC2_QM1_CP_LDMA_DST_BASE_LO_OFFSET_1                      0xD622F8
+
+#define mmNIC2_QM1_CP_LDMA_DST_BASE_LO_OFFSET_2                      0xD622FC
+
+#define mmNIC2_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3                      0xD62300
+
+#define mmNIC2_QM1_CP_LDMA_DST_BASE_LO_OFFSET_4                      0xD62304
+
+#define mmNIC2_QM1_CP_FENCE0_RDATA_0                                 0xD62308
+
+#define mmNIC2_QM1_CP_FENCE0_RDATA_1                                 0xD6230C
+
+#define mmNIC2_QM1_CP_FENCE0_RDATA_2                                 0xD62310
+
+#define mmNIC2_QM1_CP_FENCE0_RDATA_3                                 0xD62314
+
+#define mmNIC2_QM1_CP_FENCE0_RDATA_4                                 0xD62318
+
+#define mmNIC2_QM1_CP_FENCE1_RDATA_0                                 0xD6231C
+
+#define mmNIC2_QM1_CP_FENCE1_RDATA_1                                 0xD62320
+
+#define mmNIC2_QM1_CP_FENCE1_RDATA_2                                 0xD62324
+
+#define mmNIC2_QM1_CP_FENCE1_RDATA_3                                 0xD62328
+
+#define mmNIC2_QM1_CP_FENCE1_RDATA_4                                 0xD6232C
+
+#define mmNIC2_QM1_CP_FENCE2_RDATA_0                                 0xD62330
+
+#define mmNIC2_QM1_CP_FENCE2_RDATA_1                                 0xD62334
+
+#define mmNIC2_QM1_CP_FENCE2_RDATA_2                                 0xD62338
+
+#define mmNIC2_QM1_CP_FENCE2_RDATA_3                                 0xD6233C
+
+#define mmNIC2_QM1_CP_FENCE2_RDATA_4                                 0xD62340
+
+#define mmNIC2_QM1_CP_FENCE3_RDATA_0                                 0xD62344
+
+#define mmNIC2_QM1_CP_FENCE3_RDATA_1                                 0xD62348
+
+#define mmNIC2_QM1_CP_FENCE3_RDATA_2                                 0xD6234C
+
+#define mmNIC2_QM1_CP_FENCE3_RDATA_3                                 0xD62350
+
+#define mmNIC2_QM1_CP_FENCE3_RDATA_4                                 0xD62354
+
+#define mmNIC2_QM1_CP_FENCE0_CNT_0                                   0xD62358
+
+#define mmNIC2_QM1_CP_FENCE0_CNT_1                                   0xD6235C
+
+#define mmNIC2_QM1_CP_FENCE0_CNT_2                                   0xD62360
+
+#define mmNIC2_QM1_CP_FENCE0_CNT_3                                   0xD62364
+
+#define mmNIC2_QM1_CP_FENCE0_CNT_4                                   0xD62368
+
+#define mmNIC2_QM1_CP_FENCE1_CNT_0                                   0xD6236C
+
+#define mmNIC2_QM1_CP_FENCE1_CNT_1                                   0xD62370
+
+#define mmNIC2_QM1_CP_FENCE1_CNT_2                                   0xD62374
+
+#define mmNIC2_QM1_CP_FENCE1_CNT_3                                   0xD62378
+
+#define mmNIC2_QM1_CP_FENCE1_CNT_4                                   0xD6237C
+
+#define mmNIC2_QM1_CP_FENCE2_CNT_0                                   0xD62380
+
+#define mmNIC2_QM1_CP_FENCE2_CNT_1                                   0xD62384
+
+#define mmNIC2_QM1_CP_FENCE2_CNT_2                                   0xD62388
+
+#define mmNIC2_QM1_CP_FENCE2_CNT_3                                   0xD6238C
+
+#define mmNIC2_QM1_CP_FENCE2_CNT_4                                   0xD62390
+
+#define mmNIC2_QM1_CP_FENCE3_CNT_0                                   0xD62394
+
+#define mmNIC2_QM1_CP_FENCE3_CNT_1                                   0xD62398
+
+#define mmNIC2_QM1_CP_FENCE3_CNT_2                                   0xD6239C
+
+#define mmNIC2_QM1_CP_FENCE3_CNT_3                                   0xD623A0
+
+#define mmNIC2_QM1_CP_FENCE3_CNT_4                                   0xD623A4
+
+#define mmNIC2_QM1_CP_STS_0                                          0xD623A8
+
+#define mmNIC2_QM1_CP_STS_1                                          0xD623AC
+
+#define mmNIC2_QM1_CP_STS_2                                          0xD623B0
+
+#define mmNIC2_QM1_CP_STS_3                                          0xD623B4
+
+#define mmNIC2_QM1_CP_STS_4                                          0xD623B8
+
+#define mmNIC2_QM1_CP_CURRENT_INST_LO_0                              0xD623BC
+
+#define mmNIC2_QM1_CP_CURRENT_INST_LO_1                              0xD623C0
+
+#define mmNIC2_QM1_CP_CURRENT_INST_LO_2                              0xD623C4
+
+#define mmNIC2_QM1_CP_CURRENT_INST_LO_3                              0xD623C8
+
+#define mmNIC2_QM1_CP_CURRENT_INST_LO_4                              0xD623CC
+
+#define mmNIC2_QM1_CP_CURRENT_INST_HI_0                              0xD623D0
+
+#define mmNIC2_QM1_CP_CURRENT_INST_HI_1                              0xD623D4
+
+#define mmNIC2_QM1_CP_CURRENT_INST_HI_2                              0xD623D8
+
+#define mmNIC2_QM1_CP_CURRENT_INST_HI_3                              0xD623DC
+
+#define mmNIC2_QM1_CP_CURRENT_INST_HI_4                              0xD623E0
+
+#define mmNIC2_QM1_CP_BARRIER_CFG_0                                  0xD623F4
+
+#define mmNIC2_QM1_CP_BARRIER_CFG_1                                  0xD623F8
+
+#define mmNIC2_QM1_CP_BARRIER_CFG_2                                  0xD623FC
+
+#define mmNIC2_QM1_CP_BARRIER_CFG_3                                  0xD62400
+
+#define mmNIC2_QM1_CP_BARRIER_CFG_4                                  0xD62404
+
+#define mmNIC2_QM1_CP_DBG_0_0                                        0xD62408
+
+#define mmNIC2_QM1_CP_DBG_0_1                                        0xD6240C
+
+#define mmNIC2_QM1_CP_DBG_0_2                                        0xD62410
+
+#define mmNIC2_QM1_CP_DBG_0_3                                        0xD62414
+
+#define mmNIC2_QM1_CP_DBG_0_4                                        0xD62418
+
+#define mmNIC2_QM1_CP_ARUSER_31_11_0                                 0xD6241C
+
+#define mmNIC2_QM1_CP_ARUSER_31_11_1                                 0xD62420
+
+#define mmNIC2_QM1_CP_ARUSER_31_11_2                                 0xD62424
+
+#define mmNIC2_QM1_CP_ARUSER_31_11_3                                 0xD62428
+
+#define mmNIC2_QM1_CP_ARUSER_31_11_4                                 0xD6242C
+
+#define mmNIC2_QM1_CP_AWUSER_31_11_0                                 0xD62430
+
+#define mmNIC2_QM1_CP_AWUSER_31_11_1                                 0xD62434
+
+#define mmNIC2_QM1_CP_AWUSER_31_11_2                                 0xD62438
+
+#define mmNIC2_QM1_CP_AWUSER_31_11_3                                 0xD6243C
+
+#define mmNIC2_QM1_CP_AWUSER_31_11_4                                 0xD62440
+
+#define mmNIC2_QM1_ARB_CFG_0                                         0xD62A00
+
+#define mmNIC2_QM1_ARB_CHOISE_Q_PUSH                                 0xD62A04
+
+#define mmNIC2_QM1_ARB_WRR_WEIGHT_0                                  0xD62A08
+
+#define mmNIC2_QM1_ARB_WRR_WEIGHT_1                                  0xD62A0C
+
+#define mmNIC2_QM1_ARB_WRR_WEIGHT_2                                  0xD62A10
+
+#define mmNIC2_QM1_ARB_WRR_WEIGHT_3                                  0xD62A14
+
+#define mmNIC2_QM1_ARB_CFG_1                                         0xD62A18
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_0                              0xD62A20
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_1                              0xD62A24
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_2                              0xD62A28
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_3                              0xD62A2C
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_4                              0xD62A30
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_5                              0xD62A34
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_6                              0xD62A38
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_7                              0xD62A3C
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_8                              0xD62A40
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_9                              0xD62A44
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_10                             0xD62A48
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_11                             0xD62A4C
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_12                             0xD62A50
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_13                             0xD62A54
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_14                             0xD62A58
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_15                             0xD62A5C
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_16                             0xD62A60
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_17                             0xD62A64
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_18                             0xD62A68
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_19                             0xD62A6C
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_20                             0xD62A70
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_21                             0xD62A74
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_22                             0xD62A78
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_23                             0xD62A7C
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_24                             0xD62A80
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_25                             0xD62A84
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_26                             0xD62A88
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_27                             0xD62A8C
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_28                             0xD62A90
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_29                             0xD62A94
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_30                             0xD62A98
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_31                             0xD62A9C
+
+#define mmNIC2_QM1_ARB_MST_CRED_INC                                  0xD62AA0
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_0                        0xD62AA4
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_1                        0xD62AA8
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_2                        0xD62AAC
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_3                        0xD62AB0
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_4                        0xD62AB4
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_5                        0xD62AB8
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_6                        0xD62ABC
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_7                        0xD62AC0
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_8                        0xD62AC4
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_9                        0xD62AC8
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_10                       0xD62ACC
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_11                       0xD62AD0
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_12                       0xD62AD4
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_13                       0xD62AD8
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_14                       0xD62ADC
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_15                       0xD62AE0
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_16                       0xD62AE4
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_17                       0xD62AE8
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_18                       0xD62AEC
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_19                       0xD62AF0
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_20                       0xD62AF4
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_21                       0xD62AF8
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_22                       0xD62AFC
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_23                       0xD62B00
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_24                       0xD62B04
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_25                       0xD62B08
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_26                       0xD62B0C
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_27                       0xD62B10
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_28                       0xD62B14
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_29                       0xD62B18
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_30                       0xD62B1C
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_31                       0xD62B20
+
+#define mmNIC2_QM1_ARB_SLV_MASTER_INC_CRED_OFST                      0xD62B28
+
+#define mmNIC2_QM1_ARB_MST_SLAVE_EN                                  0xD62B2C
+
+#define mmNIC2_QM1_ARB_MST_QUIET_PER                                 0xD62B34
+
+#define mmNIC2_QM1_ARB_SLV_CHOISE_WDT                                0xD62B38
+
+#define mmNIC2_QM1_ARB_SLV_ID                                        0xD62B3C
+
+#define mmNIC2_QM1_ARB_MSG_MAX_INFLIGHT                              0xD62B44
+
+#define mmNIC2_QM1_ARB_MSG_AWUSER_31_11                              0xD62B48
+
+#define mmNIC2_QM1_ARB_MSG_AWUSER_SEC_PROP                           0xD62B4C
+
+#define mmNIC2_QM1_ARB_MSG_AWUSER_NON_SEC_PROP                       0xD62B50
+
+#define mmNIC2_QM1_ARB_BASE_LO                                       0xD62B54
+
+#define mmNIC2_QM1_ARB_BASE_HI                                       0xD62B58
+
+#define mmNIC2_QM1_ARB_STATE_STS                                     0xD62B80
+
+#define mmNIC2_QM1_ARB_CHOISE_FULLNESS_STS                           0xD62B84
+
+#define mmNIC2_QM1_ARB_MSG_STS                                       0xD62B88
+
+#define mmNIC2_QM1_ARB_SLV_CHOISE_Q_HEAD                             0xD62B8C
+
+#define mmNIC2_QM1_ARB_ERR_CAUSE                                     0xD62B9C
+
+#define mmNIC2_QM1_ARB_ERR_MSG_EN                                    0xD62BA0
+
+#define mmNIC2_QM1_ARB_ERR_STS_DRP                                   0xD62BA8
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_0                                0xD62BB0
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_1                                0xD62BB4
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_2                                0xD62BB8
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_3                                0xD62BBC
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_4                                0xD62BC0
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_5                                0xD62BC4
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_6                                0xD62BC8
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_7                                0xD62BCC
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_8                                0xD62BD0
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_9                                0xD62BD4
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_10                               0xD62BD8
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_11                               0xD62BDC
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_12                               0xD62BE0
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_13                               0xD62BE4
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_14                               0xD62BE8
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_15                               0xD62BEC
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_16                               0xD62BF0
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_17                               0xD62BF4
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_18                               0xD62BF8
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_19                               0xD62BFC
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_20                               0xD62C00
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_21                               0xD62C04
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_22                               0xD62C08
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_23                               0xD62C0C
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_24                               0xD62C10
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_25                               0xD62C14
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_26                               0xD62C18
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_27                               0xD62C1C
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_28                               0xD62C20
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_29                               0xD62C24
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_30                               0xD62C28
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_31                               0xD62C2C
+
+#define mmNIC2_QM1_CGM_CFG                                           0xD62C70
+
+#define mmNIC2_QM1_CGM_STS                                           0xD62C74
+
+#define mmNIC2_QM1_CGM_CFG1                                          0xD62C78
+
+#define mmNIC2_QM1_LOCAL_RANGE_BASE                                  0xD62C80
+
+#define mmNIC2_QM1_LOCAL_RANGE_SIZE                                  0xD62C84
+
+#define mmNIC2_QM1_CSMR_STRICT_PRIO_CFG                              0xD62C90
+
+#define mmNIC2_QM1_HBW_RD_RATE_LIM_CFG_1                             0xD62C94
+
+#define mmNIC2_QM1_LBW_WR_RATE_LIM_CFG_0                             0xD62C98
+
+#define mmNIC2_QM1_LBW_WR_RATE_LIM_CFG_1                             0xD62C9C
+
+#define mmNIC2_QM1_HBW_RD_RATE_LIM_CFG_0                             0xD62CA0
+
+#define mmNIC2_QM1_GLBL_AXCACHE                                      0xD62CA4
+
+#define mmNIC2_QM1_IND_GW_APB_CFG                                    0xD62CB0
+
+#define mmNIC2_QM1_IND_GW_APB_WDATA                                  0xD62CB4
+
+#define mmNIC2_QM1_IND_GW_APB_RDATA                                  0xD62CB8
+
+#define mmNIC2_QM1_IND_GW_APB_STATUS                                 0xD62CBC
+
+#define mmNIC2_QM1_GLBL_ERR_ADDR_LO                                  0xD62CD0
+
+#define mmNIC2_QM1_GLBL_ERR_ADDR_HI                                  0xD62CD4
+
+#define mmNIC2_QM1_GLBL_ERR_WDATA                                    0xD62CD8
+
+#define mmNIC2_QM1_GLBL_MEM_INIT_BUSY                                0xD62D00
+
+#endif /* ASIC_REG_NIC2_QM1_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/nic3_qm0_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic3_qm0_regs.h
new file mode 100644
index 000000000000..4712cc62b009
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic3_qm0_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_NIC3_QM0_REGS_H_
+#define ASIC_REG_NIC3_QM0_REGS_H_
+
+/*
+ *****************************************
+ *   NIC3_QM0 (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmNIC3_QM0_GLBL_CFG0                                         0xDA0000
+
+#define mmNIC3_QM0_GLBL_CFG1                                         0xDA0004
+
+#define mmNIC3_QM0_GLBL_PROT                                         0xDA0008
+
+#define mmNIC3_QM0_GLBL_ERR_CFG                                      0xDA000C
+
+#define mmNIC3_QM0_GLBL_SECURE_PROPS_0                               0xDA0010
+
+#define mmNIC3_QM0_GLBL_SECURE_PROPS_1                               0xDA0014
+
+#define mmNIC3_QM0_GLBL_SECURE_PROPS_2                               0xDA0018
+
+#define mmNIC3_QM0_GLBL_SECURE_PROPS_3                               0xDA001C
+
+#define mmNIC3_QM0_GLBL_SECURE_PROPS_4                               0xDA0020
+
+#define mmNIC3_QM0_GLBL_NON_SECURE_PROPS_0                           0xDA0024
+
+#define mmNIC3_QM0_GLBL_NON_SECURE_PROPS_1                           0xDA0028
+
+#define mmNIC3_QM0_GLBL_NON_SECURE_PROPS_2                           0xDA002C
+
+#define mmNIC3_QM0_GLBL_NON_SECURE_PROPS_3                           0xDA0030
+
+#define mmNIC3_QM0_GLBL_NON_SECURE_PROPS_4                           0xDA0034
+
+#define mmNIC3_QM0_GLBL_STS0                                         0xDA0038
+
+#define mmNIC3_QM0_GLBL_STS1_0                                       0xDA0040
+
+#define mmNIC3_QM0_GLBL_STS1_1                                       0xDA0044
+
+#define mmNIC3_QM0_GLBL_STS1_2                                       0xDA0048
+
+#define mmNIC3_QM0_GLBL_STS1_3                                       0xDA004C
+
+#define mmNIC3_QM0_GLBL_STS1_4                                       0xDA0050
+
+#define mmNIC3_QM0_GLBL_MSG_EN_0                                     0xDA0054
+
+#define mmNIC3_QM0_GLBL_MSG_EN_1                                     0xDA0058
+
+#define mmNIC3_QM0_GLBL_MSG_EN_2                                     0xDA005C
+
+#define mmNIC3_QM0_GLBL_MSG_EN_3                                     0xDA0060
+
+#define mmNIC3_QM0_GLBL_MSG_EN_4                                     0xDA0068
+
+#define mmNIC3_QM0_PQ_BASE_LO_0                                      0xDA0070
+
+#define mmNIC3_QM0_PQ_BASE_LO_1                                      0xDA0074
+
+#define mmNIC3_QM0_PQ_BASE_LO_2                                      0xDA0078
+
+#define mmNIC3_QM0_PQ_BASE_LO_3                                      0xDA007C
+
+#define mmNIC3_QM0_PQ_BASE_HI_0                                      0xDA0080
+
+#define mmNIC3_QM0_PQ_BASE_HI_1                                      0xDA0084
+
+#define mmNIC3_QM0_PQ_BASE_HI_2                                      0xDA0088
+
+#define mmNIC3_QM0_PQ_BASE_HI_3                                      0xDA008C
+
+#define mmNIC3_QM0_PQ_SIZE_0                                         0xDA0090
+
+#define mmNIC3_QM0_PQ_SIZE_1                                         0xDA0094
+
+#define mmNIC3_QM0_PQ_SIZE_2                                         0xDA0098
+
+#define mmNIC3_QM0_PQ_SIZE_3                                         0xDA009C
+
+#define mmNIC3_QM0_PQ_PI_0                                           0xDA00A0
+
+#define mmNIC3_QM0_PQ_PI_1                                           0xDA00A4
+
+#define mmNIC3_QM0_PQ_PI_2                                           0xDA00A8
+
+#define mmNIC3_QM0_PQ_PI_3                                           0xDA00AC
+
+#define mmNIC3_QM0_PQ_CI_0                                           0xDA00B0
+
+#define mmNIC3_QM0_PQ_CI_1                                           0xDA00B4
+
+#define mmNIC3_QM0_PQ_CI_2                                           0xDA00B8
+
+#define mmNIC3_QM0_PQ_CI_3                                           0xDA00BC
+
+#define mmNIC3_QM0_PQ_CFG0_0                                         0xDA00C0
+
+#define mmNIC3_QM0_PQ_CFG0_1                                         0xDA00C4
+
+#define mmNIC3_QM0_PQ_CFG0_2                                         0xDA00C8
+
+#define mmNIC3_QM0_PQ_CFG0_3                                         0xDA00CC
+
+#define mmNIC3_QM0_PQ_CFG1_0                                         0xDA00D0
+
+#define mmNIC3_QM0_PQ_CFG1_1                                         0xDA00D4
+
+#define mmNIC3_QM0_PQ_CFG1_2                                         0xDA00D8
+
+#define mmNIC3_QM0_PQ_CFG1_3                                         0xDA00DC
+
+#define mmNIC3_QM0_PQ_ARUSER_31_11_0                                 0xDA00E0
+
+#define mmNIC3_QM0_PQ_ARUSER_31_11_1                                 0xDA00E4
+
+#define mmNIC3_QM0_PQ_ARUSER_31_11_2                                 0xDA00E8
+
+#define mmNIC3_QM0_PQ_ARUSER_31_11_3                                 0xDA00EC
+
+#define mmNIC3_QM0_PQ_STS0_0                                         0xDA00F0
+
+#define mmNIC3_QM0_PQ_STS0_1                                         0xDA00F4
+
+#define mmNIC3_QM0_PQ_STS0_2                                         0xDA00F8
+
+#define mmNIC3_QM0_PQ_STS0_3                                         0xDA00FC
+
+#define mmNIC3_QM0_PQ_STS1_0                                         0xDA0100
+
+#define mmNIC3_QM0_PQ_STS1_1                                         0xDA0104
+
+#define mmNIC3_QM0_PQ_STS1_2                                         0xDA0108
+
+#define mmNIC3_QM0_PQ_STS1_3                                         0xDA010C
+
+#define mmNIC3_QM0_CQ_CFG0_0                                         0xDA0110
+
+#define mmNIC3_QM0_CQ_CFG0_1                                         0xDA0114
+
+#define mmNIC3_QM0_CQ_CFG0_2                                         0xDA0118
+
+#define mmNIC3_QM0_CQ_CFG0_3                                         0xDA011C
+
+#define mmNIC3_QM0_CQ_CFG0_4                                         0xDA0120
+
+#define mmNIC3_QM0_CQ_CFG1_0                                         0xDA0124
+
+#define mmNIC3_QM0_CQ_CFG1_1                                         0xDA0128
+
+#define mmNIC3_QM0_CQ_CFG1_2                                         0xDA012C
+
+#define mmNIC3_QM0_CQ_CFG1_3                                         0xDA0130
+
+#define mmNIC3_QM0_CQ_CFG1_4                                         0xDA0134
+
+#define mmNIC3_QM0_CQ_ARUSER_31_11_0                                 0xDA0138
+
+#define mmNIC3_QM0_CQ_ARUSER_31_11_1                                 0xDA013C
+
+#define mmNIC3_QM0_CQ_ARUSER_31_11_2                                 0xDA0140
+
+#define mmNIC3_QM0_CQ_ARUSER_31_11_3                                 0xDA0144
+
+#define mmNIC3_QM0_CQ_ARUSER_31_11_4                                 0xDA0148
+
+#define mmNIC3_QM0_CQ_STS0_0                                         0xDA014C
+
+#define mmNIC3_QM0_CQ_STS0_1                                         0xDA0150
+
+#define mmNIC3_QM0_CQ_STS0_2                                         0xDA0154
+
+#define mmNIC3_QM0_CQ_STS0_3                                         0xDA0158
+
+#define mmNIC3_QM0_CQ_STS0_4                                         0xDA015C
+
+#define mmNIC3_QM0_CQ_STS1_0                                         0xDA0160
+
+#define mmNIC3_QM0_CQ_STS1_1                                         0xDA0164
+
+#define mmNIC3_QM0_CQ_STS1_2                                         0xDA0168
+
+#define mmNIC3_QM0_CQ_STS1_3                                         0xDA016C
+
+#define mmNIC3_QM0_CQ_STS1_4                                         0xDA0170
+
+#define mmNIC3_QM0_CQ_PTR_LO_0                                       0xDA0174
+
+#define mmNIC3_QM0_CQ_PTR_HI_0                                       0xDA0178
+
+#define mmNIC3_QM0_CQ_TSIZE_0                                        0xDA017C
+
+#define mmNIC3_QM0_CQ_CTL_0                                          0xDA0180
+
+#define mmNIC3_QM0_CQ_PTR_LO_1                                       0xDA0184
+
+#define mmNIC3_QM0_CQ_PTR_HI_1                                       0xDA0188
+
+#define mmNIC3_QM0_CQ_TSIZE_1                                        0xDA018C
+
+#define mmNIC3_QM0_CQ_CTL_1                                          0xDA0190
+
+#define mmNIC3_QM0_CQ_PTR_LO_2                                       0xDA0194
+
+#define mmNIC3_QM0_CQ_PTR_HI_2                                       0xDA0198
+
+#define mmNIC3_QM0_CQ_TSIZE_2                                        0xDA019C
+
+#define mmNIC3_QM0_CQ_CTL_2                                          0xDA01A0
+
+#define mmNIC3_QM0_CQ_PTR_LO_3                                       0xDA01A4
+
+#define mmNIC3_QM0_CQ_PTR_HI_3                                       0xDA01A8
+
+#define mmNIC3_QM0_CQ_TSIZE_3                                        0xDA01AC
+
+#define mmNIC3_QM0_CQ_CTL_3                                          0xDA01B0
+
+#define mmNIC3_QM0_CQ_PTR_LO_4                                       0xDA01B4
+
+#define mmNIC3_QM0_CQ_PTR_HI_4                                       0xDA01B8
+
+#define mmNIC3_QM0_CQ_TSIZE_4                                        0xDA01BC
+
+#define mmNIC3_QM0_CQ_CTL_4                                          0xDA01C0
+
+#define mmNIC3_QM0_CQ_PTR_LO_STS_0                                   0xDA01C4
+
+#define mmNIC3_QM0_CQ_PTR_LO_STS_1                                   0xDA01C8
+
+#define mmNIC3_QM0_CQ_PTR_LO_STS_2                                   0xDA01CC
+
+#define mmNIC3_QM0_CQ_PTR_LO_STS_3                                   0xDA01D0
+
+#define mmNIC3_QM0_CQ_PTR_LO_STS_4                                   0xDA01D4
+
+#define mmNIC3_QM0_CQ_PTR_HI_STS_0                                   0xDA01D8
+
+#define mmNIC3_QM0_CQ_PTR_HI_STS_1                                   0xDA01DC
+
+#define mmNIC3_QM0_CQ_PTR_HI_STS_2                                   0xDA01E0
+
+#define mmNIC3_QM0_CQ_PTR_HI_STS_3                                   0xDA01E4
+
+#define mmNIC3_QM0_CQ_PTR_HI_STS_4                                   0xDA01E8
+
+#define mmNIC3_QM0_CQ_TSIZE_STS_0                                    0xDA01EC
+
+#define mmNIC3_QM0_CQ_TSIZE_STS_1                                    0xDA01F0
+
+#define mmNIC3_QM0_CQ_TSIZE_STS_2                                    0xDA01F4
+
+#define mmNIC3_QM0_CQ_TSIZE_STS_3                                    0xDA01F8
+
+#define mmNIC3_QM0_CQ_TSIZE_STS_4                                    0xDA01FC
+
+#define mmNIC3_QM0_CQ_CTL_STS_0                                      0xDA0200
+
+#define mmNIC3_QM0_CQ_CTL_STS_1                                      0xDA0204
+
+#define mmNIC3_QM0_CQ_CTL_STS_2                                      0xDA0208
+
+#define mmNIC3_QM0_CQ_CTL_STS_3                                      0xDA020C
+
+#define mmNIC3_QM0_CQ_CTL_STS_4                                      0xDA0210
+
+#define mmNIC3_QM0_CQ_IFIFO_CNT_0                                    0xDA0214
+
+#define mmNIC3_QM0_CQ_IFIFO_CNT_1                                    0xDA0218
+
+#define mmNIC3_QM0_CQ_IFIFO_CNT_2                                    0xDA021C
+
+#define mmNIC3_QM0_CQ_IFIFO_CNT_3                                    0xDA0220
+
+#define mmNIC3_QM0_CQ_IFIFO_CNT_4                                    0xDA0224
+
+#define mmNIC3_QM0_CP_MSG_BASE0_ADDR_LO_0                            0xDA0228
+
+#define mmNIC3_QM0_CP_MSG_BASE0_ADDR_LO_1                            0xDA022C
+
+#define mmNIC3_QM0_CP_MSG_BASE0_ADDR_LO_2                            0xDA0230
+
+#define mmNIC3_QM0_CP_MSG_BASE0_ADDR_LO_3                            0xDA0234
+
+#define mmNIC3_QM0_CP_MSG_BASE0_ADDR_LO_4                            0xDA0238
+
+#define mmNIC3_QM0_CP_MSG_BASE0_ADDR_HI_0                            0xDA023C
+
+#define mmNIC3_QM0_CP_MSG_BASE0_ADDR_HI_1                            0xDA0240
+
+#define mmNIC3_QM0_CP_MSG_BASE0_ADDR_HI_2                            0xDA0244
+
+#define mmNIC3_QM0_CP_MSG_BASE0_ADDR_HI_3                            0xDA0248
+
+#define mmNIC3_QM0_CP_MSG_BASE0_ADDR_HI_4                            0xDA024C
+
+#define mmNIC3_QM0_CP_MSG_BASE1_ADDR_LO_0                            0xDA0250
+
+#define mmNIC3_QM0_CP_MSG_BASE1_ADDR_LO_1                            0xDA0254
+
+#define mmNIC3_QM0_CP_MSG_BASE1_ADDR_LO_2                            0xDA0258
+
+#define mmNIC3_QM0_CP_MSG_BASE1_ADDR_LO_3                            0xDA025C
+
+#define mmNIC3_QM0_CP_MSG_BASE1_ADDR_LO_4                            0xDA0260
+
+#define mmNIC3_QM0_CP_MSG_BASE1_ADDR_HI_0                            0xDA0264
+
+#define mmNIC3_QM0_CP_MSG_BASE1_ADDR_HI_1                            0xDA0268
+
+#define mmNIC3_QM0_CP_MSG_BASE1_ADDR_HI_2                            0xDA026C
+
+#define mmNIC3_QM0_CP_MSG_BASE1_ADDR_HI_3                            0xDA0270
+
+#define mmNIC3_QM0_CP_MSG_BASE1_ADDR_HI_4                            0xDA0274
+
+#define mmNIC3_QM0_CP_MSG_BASE2_ADDR_LO_0                            0xDA0278
+
+#define mmNIC3_QM0_CP_MSG_BASE2_ADDR_LO_1                            0xDA027C
+
+#define mmNIC3_QM0_CP_MSG_BASE2_ADDR_LO_2                            0xDA0280
+
+#define mmNIC3_QM0_CP_MSG_BASE2_ADDR_LO_3                            0xDA0284
+
+#define mmNIC3_QM0_CP_MSG_BASE2_ADDR_LO_4                            0xDA0288
+
+#define mmNIC3_QM0_CP_MSG_BASE2_ADDR_HI_0                            0xDA028C
+
+#define mmNIC3_QM0_CP_MSG_BASE2_ADDR_HI_1                            0xDA0290
+
+#define mmNIC3_QM0_CP_MSG_BASE2_ADDR_HI_2                            0xDA0294
+
+#define mmNIC3_QM0_CP_MSG_BASE2_ADDR_HI_3                            0xDA0298
+
+#define mmNIC3_QM0_CP_MSG_BASE2_ADDR_HI_4                            0xDA029C
+
+#define mmNIC3_QM0_CP_MSG_BASE3_ADDR_LO_0                            0xDA02A0
+
+#define mmNIC3_QM0_CP_MSG_BASE3_ADDR_LO_1                            0xDA02A4
+
+#define mmNIC3_QM0_CP_MSG_BASE3_ADDR_LO_2                            0xDA02A8
+
+#define mmNIC3_QM0_CP_MSG_BASE3_ADDR_LO_3                            0xDA02AC
+
+#define mmNIC3_QM0_CP_MSG_BASE3_ADDR_LO_4                            0xDA02B0
+
+#define mmNIC3_QM0_CP_MSG_BASE3_ADDR_HI_0                            0xDA02B4
+
+#define mmNIC3_QM0_CP_MSG_BASE3_ADDR_HI_1                            0xDA02B8
+
+#define mmNIC3_QM0_CP_MSG_BASE3_ADDR_HI_2                            0xDA02BC
+
+#define mmNIC3_QM0_CP_MSG_BASE3_ADDR_HI_3                            0xDA02C0
+
+#define mmNIC3_QM0_CP_MSG_BASE3_ADDR_HI_4                            0xDA02C4
+
+#define mmNIC3_QM0_CP_LDMA_TSIZE_OFFSET_0                            0xDA02C8
+
+#define mmNIC3_QM0_CP_LDMA_TSIZE_OFFSET_1                            0xDA02CC
+
+#define mmNIC3_QM0_CP_LDMA_TSIZE_OFFSET_2                            0xDA02D0
+
+#define mmNIC3_QM0_CP_LDMA_TSIZE_OFFSET_3                            0xDA02D4
+
+#define mmNIC3_QM0_CP_LDMA_TSIZE_OFFSET_4                            0xDA02D8
+
+#define mmNIC3_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_0                      0xDA02E0
+
+#define mmNIC3_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_1                      0xDA02E4
+
+#define mmNIC3_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_2                      0xDA02E8
+
+#define mmNIC3_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_3                      0xDA02EC
+
+#define mmNIC3_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_4                      0xDA02F0
+
+#define mmNIC3_QM0_CP_LDMA_DST_BASE_LO_OFFSET_0                      0xDA02F4
+
+#define mmNIC3_QM0_CP_LDMA_DST_BASE_LO_OFFSET_1                      0xDA02F8
+
+#define mmNIC3_QM0_CP_LDMA_DST_BASE_LO_OFFSET_2                      0xDA02FC
+
+#define mmNIC3_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3                      0xDA0300
+
+#define mmNIC3_QM0_CP_LDMA_DST_BASE_LO_OFFSET_4                      0xDA0304
+
+#define mmNIC3_QM0_CP_FENCE0_RDATA_0                                 0xDA0308
+
+#define mmNIC3_QM0_CP_FENCE0_RDATA_1                                 0xDA030C
+
+#define mmNIC3_QM0_CP_FENCE0_RDATA_2                                 0xDA0310
+
+#define mmNIC3_QM0_CP_FENCE0_RDATA_3                                 0xDA0314
+
+#define mmNIC3_QM0_CP_FENCE0_RDATA_4                                 0xDA0318
+
+#define mmNIC3_QM0_CP_FENCE1_RDATA_0                                 0xDA031C
+
+#define mmNIC3_QM0_CP_FENCE1_RDATA_1                                 0xDA0320
+
+#define mmNIC3_QM0_CP_FENCE1_RDATA_2                                 0xDA0324
+
+#define mmNIC3_QM0_CP_FENCE1_RDATA_3                                 0xDA0328
+
+#define mmNIC3_QM0_CP_FENCE1_RDATA_4                                 0xDA032C
+
+#define mmNIC3_QM0_CP_FENCE2_RDATA_0                                 0xDA0330
+
+#define mmNIC3_QM0_CP_FENCE2_RDATA_1                                 0xDA0334
+
+#define mmNIC3_QM0_CP_FENCE2_RDATA_2                                 0xDA0338
+
+#define mmNIC3_QM0_CP_FENCE2_RDATA_3                                 0xDA033C
+
+#define mmNIC3_QM0_CP_FENCE2_RDATA_4                                 0xDA0340
+
+#define mmNIC3_QM0_CP_FENCE3_RDATA_0                                 0xDA0344
+
+#define mmNIC3_QM0_CP_FENCE3_RDATA_1                                 0xDA0348
+
+#define mmNIC3_QM0_CP_FENCE3_RDATA_2                                 0xDA034C
+
+#define mmNIC3_QM0_CP_FENCE3_RDATA_3                                 0xDA0350
+
+#define mmNIC3_QM0_CP_FENCE3_RDATA_4                                 0xDA0354
+
+#define mmNIC3_QM0_CP_FENCE0_CNT_0                                   0xDA0358
+
+#define mmNIC3_QM0_CP_FENCE0_CNT_1                                   0xDA035C
+
+#define mmNIC3_QM0_CP_FENCE0_CNT_2                                   0xDA0360
+
+#define mmNIC3_QM0_CP_FENCE0_CNT_3                                   0xDA0364
+
+#define mmNIC3_QM0_CP_FENCE0_CNT_4                                   0xDA0368
+
+#define mmNIC3_QM0_CP_FENCE1_CNT_0                                   0xDA036C
+
+#define mmNIC3_QM0_CP_FENCE1_CNT_1                                   0xDA0370
+
+#define mmNIC3_QM0_CP_FENCE1_CNT_2                                   0xDA0374
+
+#define mmNIC3_QM0_CP_FENCE1_CNT_3                                   0xDA0378
+
+#define mmNIC3_QM0_CP_FENCE1_CNT_4                                   0xDA037C
+
+#define mmNIC3_QM0_CP_FENCE2_CNT_0                                   0xDA0380
+
+#define mmNIC3_QM0_CP_FENCE2_CNT_1                                   0xDA0384
+
+#define mmNIC3_QM0_CP_FENCE2_CNT_2                                   0xDA0388
+
+#define mmNIC3_QM0_CP_FENCE2_CNT_3                                   0xDA038C
+
+#define mmNIC3_QM0_CP_FENCE2_CNT_4                                   0xDA0390
+
+#define mmNIC3_QM0_CP_FENCE3_CNT_0                                   0xDA0394
+
+#define mmNIC3_QM0_CP_FENCE3_CNT_1                                   0xDA0398
+
+#define mmNIC3_QM0_CP_FENCE3_CNT_2                                   0xDA039C
+
+#define mmNIC3_QM0_CP_FENCE3_CNT_3                                   0xDA03A0
+
+#define mmNIC3_QM0_CP_FENCE3_CNT_4                                   0xDA03A4
+
+#define mmNIC3_QM0_CP_STS_0                                          0xDA03A8
+
+#define mmNIC3_QM0_CP_STS_1                                          0xDA03AC
+
+#define mmNIC3_QM0_CP_STS_2                                          0xDA03B0
+
+#define mmNIC3_QM0_CP_STS_3                                          0xDA03B4
+
+#define mmNIC3_QM0_CP_STS_4                                          0xDA03B8
+
+#define mmNIC3_QM0_CP_CURRENT_INST_LO_0                              0xDA03BC
+
+#define mmNIC3_QM0_CP_CURRENT_INST_LO_1                              0xDA03C0
+
+#define mmNIC3_QM0_CP_CURRENT_INST_LO_2                              0xDA03C4
+
+#define mmNIC3_QM0_CP_CURRENT_INST_LO_3                              0xDA03C8
+
+#define mmNIC3_QM0_CP_CURRENT_INST_LO_4                              0xDA03CC
+
+#define mmNIC3_QM0_CP_CURRENT_INST_HI_0                              0xDA03D0
+
+#define mmNIC3_QM0_CP_CURRENT_INST_HI_1                              0xDA03D4
+
+#define mmNIC3_QM0_CP_CURRENT_INST_HI_2                              0xDA03D8
+
+#define mmNIC3_QM0_CP_CURRENT_INST_HI_3                              0xDA03DC
+
+#define mmNIC3_QM0_CP_CURRENT_INST_HI_4                              0xDA03E0
+
+#define mmNIC3_QM0_CP_BARRIER_CFG_0                                  0xDA03F4
+
+#define mmNIC3_QM0_CP_BARRIER_CFG_1                                  0xDA03F8
+
+#define mmNIC3_QM0_CP_BARRIER_CFG_2                                  0xDA03FC
+
+#define mmNIC3_QM0_CP_BARRIER_CFG_3                                  0xDA0400
+
+#define mmNIC3_QM0_CP_BARRIER_CFG_4                                  0xDA0404
+
+#define mmNIC3_QM0_CP_DBG_0_0                                        0xDA0408
+
+#define mmNIC3_QM0_CP_DBG_0_1                                        0xDA040C
+
+#define mmNIC3_QM0_CP_DBG_0_2                                        0xDA0410
+
+#define mmNIC3_QM0_CP_DBG_0_3                                        0xDA0414
+
+#define mmNIC3_QM0_CP_DBG_0_4                                        0xDA0418
+
+#define mmNIC3_QM0_CP_ARUSER_31_11_0                                 0xDA041C
+
+#define mmNIC3_QM0_CP_ARUSER_31_11_1                                 0xDA0420
+
+#define mmNIC3_QM0_CP_ARUSER_31_11_2                                 0xDA0424
+
+#define mmNIC3_QM0_CP_ARUSER_31_11_3                                 0xDA0428
+
+#define mmNIC3_QM0_CP_ARUSER_31_11_4                                 0xDA042C
+
+#define mmNIC3_QM0_CP_AWUSER_31_11_0                                 0xDA0430
+
+#define mmNIC3_QM0_CP_AWUSER_31_11_1                                 0xDA0434
+
+#define mmNIC3_QM0_CP_AWUSER_31_11_2                                 0xDA0438
+
+#define mmNIC3_QM0_CP_AWUSER_31_11_3                                 0xDA043C
+
+#define mmNIC3_QM0_CP_AWUSER_31_11_4                                 0xDA0440
+
+#define mmNIC3_QM0_ARB_CFG_0                                         0xDA0A00
+
+#define mmNIC3_QM0_ARB_CHOISE_Q_PUSH                                 0xDA0A04
+
+#define mmNIC3_QM0_ARB_WRR_WEIGHT_0                                  0xDA0A08
+
+#define mmNIC3_QM0_ARB_WRR_WEIGHT_1                                  0xDA0A0C
+
+#define mmNIC3_QM0_ARB_WRR_WEIGHT_2                                  0xDA0A10
+
+#define mmNIC3_QM0_ARB_WRR_WEIGHT_3                                  0xDA0A14
+
+#define mmNIC3_QM0_ARB_CFG_1                                         0xDA0A18
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_0                              0xDA0A20
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_1                              0xDA0A24
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_2                              0xDA0A28
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_3                              0xDA0A2C
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_4                              0xDA0A30
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_5                              0xDA0A34
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_6                              0xDA0A38
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_7                              0xDA0A3C
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_8                              0xDA0A40
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_9                              0xDA0A44
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_10                             0xDA0A48
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_11                             0xDA0A4C
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_12                             0xDA0A50
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_13                             0xDA0A54
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_14                             0xDA0A58
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_15                             0xDA0A5C
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_16                             0xDA0A60
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_17                             0xDA0A64
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_18                             0xDA0A68
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_19                             0xDA0A6C
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_20                             0xDA0A70
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_21                             0xDA0A74
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_22                             0xDA0A78
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_23                             0xDA0A7C
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_24                             0xDA0A80
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_25                             0xDA0A84
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_26                             0xDA0A88
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_27                             0xDA0A8C
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_28                             0xDA0A90
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_29                             0xDA0A94
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_30                             0xDA0A98
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_31                             0xDA0A9C
+
+#define mmNIC3_QM0_ARB_MST_CRED_INC                                  0xDA0AA0
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_0                        0xDA0AA4
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_1                        0xDA0AA8
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_2                        0xDA0AAC
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_3                        0xDA0AB0
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_4                        0xDA0AB4
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_5                        0xDA0AB8
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_6                        0xDA0ABC
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_7                        0xDA0AC0
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_8                        0xDA0AC4
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_9                        0xDA0AC8
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_10                       0xDA0ACC
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_11                       0xDA0AD0
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_12                       0xDA0AD4
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_13                       0xDA0AD8
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_14                       0xDA0ADC
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_15                       0xDA0AE0
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_16                       0xDA0AE4
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_17                       0xDA0AE8
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_18                       0xDA0AEC
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_19                       0xDA0AF0
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_20                       0xDA0AF4
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_21                       0xDA0AF8
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_22                       0xDA0AFC
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_23                       0xDA0B00
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_24                       0xDA0B04
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_25                       0xDA0B08
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_26                       0xDA0B0C
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_27                       0xDA0B10
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_28                       0xDA0B14
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_29                       0xDA0B18
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_30                       0xDA0B1C
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_31                       0xDA0B20
+
+#define mmNIC3_QM0_ARB_SLV_MASTER_INC_CRED_OFST                      0xDA0B28
+
+#define mmNIC3_QM0_ARB_MST_SLAVE_EN                                  0xDA0B2C
+
+#define mmNIC3_QM0_ARB_MST_QUIET_PER                                 0xDA0B34
+
+#define mmNIC3_QM0_ARB_SLV_CHOISE_WDT                                0xDA0B38
+
+#define mmNIC3_QM0_ARB_SLV_ID                                        0xDA0B3C
+
+#define mmNIC3_QM0_ARB_MSG_MAX_INFLIGHT                              0xDA0B44
+
+#define mmNIC3_QM0_ARB_MSG_AWUSER_31_11                              0xDA0B48
+
+#define mmNIC3_QM0_ARB_MSG_AWUSER_SEC_PROP                           0xDA0B4C
+
+#define mmNIC3_QM0_ARB_MSG_AWUSER_NON_SEC_PROP                       0xDA0B50
+
+#define mmNIC3_QM0_ARB_BASE_LO                                       0xDA0B54
+
+#define mmNIC3_QM0_ARB_BASE_HI                                       0xDA0B58
+
+#define mmNIC3_QM0_ARB_STATE_STS                                     0xDA0B80
+
+#define mmNIC3_QM0_ARB_CHOISE_FULLNESS_STS                           0xDA0B84
+
+#define mmNIC3_QM0_ARB_MSG_STS                                       0xDA0B88
+
+#define mmNIC3_QM0_ARB_SLV_CHOISE_Q_HEAD                             0xDA0B8C
+
+#define mmNIC3_QM0_ARB_ERR_CAUSE                                     0xDA0B9C
+
+#define mmNIC3_QM0_ARB_ERR_MSG_EN                                    0xDA0BA0
+
+#define mmNIC3_QM0_ARB_ERR_STS_DRP                                   0xDA0BA8
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_0                                0xDA0BB0
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_1                                0xDA0BB4
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_2                                0xDA0BB8
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_3                                0xDA0BBC
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_4                                0xDA0BC0
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_5                                0xDA0BC4
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_6                                0xDA0BC8
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_7                                0xDA0BCC
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_8                                0xDA0BD0
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_9                                0xDA0BD4
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_10                               0xDA0BD8
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_11                               0xDA0BDC
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_12                               0xDA0BE0
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_13                               0xDA0BE4
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_14                               0xDA0BE8
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_15                               0xDA0BEC
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_16                               0xDA0BF0
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_17                               0xDA0BF4
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_18                               0xDA0BF8
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_19                               0xDA0BFC
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_20                               0xDA0C00
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_21                               0xDA0C04
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_22                               0xDA0C08
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_23                               0xDA0C0C
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_24                               0xDA0C10
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_25                               0xDA0C14
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_26                               0xDA0C18
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_27                               0xDA0C1C
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_28                               0xDA0C20
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_29                               0xDA0C24
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_30                               0xDA0C28
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_31                               0xDA0C2C
+
+#define mmNIC3_QM0_CGM_CFG                                           0xDA0C70
+
+#define mmNIC3_QM0_CGM_STS                                           0xDA0C74
+
+#define mmNIC3_QM0_CGM_CFG1                                          0xDA0C78
+
+#define mmNIC3_QM0_LOCAL_RANGE_BASE                                  0xDA0C80
+
+#define mmNIC3_QM0_LOCAL_RANGE_SIZE                                  0xDA0C84
+
+#define mmNIC3_QM0_CSMR_STRICT_PRIO_CFG                              0xDA0C90
+
+#define mmNIC3_QM0_HBW_RD_RATE_LIM_CFG_1                             0xDA0C94
+
+#define mmNIC3_QM0_LBW_WR_RATE_LIM_CFG_0                             0xDA0C98
+
+#define mmNIC3_QM0_LBW_WR_RATE_LIM_CFG_1                             0xDA0C9C
+
+#define mmNIC3_QM0_HBW_RD_RATE_LIM_CFG_0                             0xDA0CA0
+
+#define mmNIC3_QM0_GLBL_AXCACHE                                      0xDA0CA4
+
+#define mmNIC3_QM0_IND_GW_APB_CFG                                    0xDA0CB0
+
+#define mmNIC3_QM0_IND_GW_APB_WDATA                                  0xDA0CB4
+
+#define mmNIC3_QM0_IND_GW_APB_RDATA                                  0xDA0CB8
+
+#define mmNIC3_QM0_IND_GW_APB_STATUS                                 0xDA0CBC
+
+#define mmNIC3_QM0_GLBL_ERR_ADDR_LO                                  0xDA0CD0
+
+#define mmNIC3_QM0_GLBL_ERR_ADDR_HI                                  0xDA0CD4
+
+#define mmNIC3_QM0_GLBL_ERR_WDATA                                    0xDA0CD8
+
+#define mmNIC3_QM0_GLBL_MEM_INIT_BUSY                                0xDA0D00
+
+#endif /* ASIC_REG_NIC3_QM0_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/nic3_qm1_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic3_qm1_regs.h
new file mode 100644
index 000000000000..7fa040f65004
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic3_qm1_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_NIC3_QM1_REGS_H_
+#define ASIC_REG_NIC3_QM1_REGS_H_
+
+/*
+ *****************************************
+ *   NIC3_QM1 (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmNIC3_QM1_GLBL_CFG0                                         0xDA2000
+
+#define mmNIC3_QM1_GLBL_CFG1                                         0xDA2004
+
+#define mmNIC3_QM1_GLBL_PROT                                         0xDA2008
+
+#define mmNIC3_QM1_GLBL_ERR_CFG                                      0xDA200C
+
+#define mmNIC3_QM1_GLBL_SECURE_PROPS_0                               0xDA2010
+
+#define mmNIC3_QM1_GLBL_SECURE_PROPS_1                               0xDA2014
+
+#define mmNIC3_QM1_GLBL_SECURE_PROPS_2                               0xDA2018
+
+#define mmNIC3_QM1_GLBL_SECURE_PROPS_3                               0xDA201C
+
+#define mmNIC3_QM1_GLBL_SECURE_PROPS_4                               0xDA2020
+
+#define mmNIC3_QM1_GLBL_NON_SECURE_PROPS_0                           0xDA2024
+
+#define mmNIC3_QM1_GLBL_NON_SECURE_PROPS_1                           0xDA2028
+
+#define mmNIC3_QM1_GLBL_NON_SECURE_PROPS_2                           0xDA202C
+
+#define mmNIC3_QM1_GLBL_NON_SECURE_PROPS_3                           0xDA2030
+
+#define mmNIC3_QM1_GLBL_NON_SECURE_PROPS_4                           0xDA2034
+
+#define mmNIC3_QM1_GLBL_STS0                                         0xDA2038
+
+#define mmNIC3_QM1_GLBL_STS1_0                                       0xDA2040
+
+#define mmNIC3_QM1_GLBL_STS1_1                                       0xDA2044
+
+#define mmNIC3_QM1_GLBL_STS1_2                                       0xDA2048
+
+#define mmNIC3_QM1_GLBL_STS1_3                                       0xDA204C
+
+#define mmNIC3_QM1_GLBL_STS1_4                                       0xDA2050
+
+#define mmNIC3_QM1_GLBL_MSG_EN_0                                     0xDA2054
+
+#define mmNIC3_QM1_GLBL_MSG_EN_1                                     0xDA2058
+
+#define mmNIC3_QM1_GLBL_MSG_EN_2                                     0xDA205C
+
+#define mmNIC3_QM1_GLBL_MSG_EN_3                                     0xDA2060
+
+#define mmNIC3_QM1_GLBL_MSG_EN_4                                     0xDA2068
+
+#define mmNIC3_QM1_PQ_BASE_LO_0                                      0xDA2070
+
+#define mmNIC3_QM1_PQ_BASE_LO_1                                      0xDA2074
+
+#define mmNIC3_QM1_PQ_BASE_LO_2                                      0xDA2078
+
+#define mmNIC3_QM1_PQ_BASE_LO_3                                      0xDA207C
+
+#define mmNIC3_QM1_PQ_BASE_HI_0                                      0xDA2080
+
+#define mmNIC3_QM1_PQ_BASE_HI_1                                      0xDA2084
+
+#define mmNIC3_QM1_PQ_BASE_HI_2                                      0xDA2088
+
+#define mmNIC3_QM1_PQ_BASE_HI_3                                      0xDA208C
+
+#define mmNIC3_QM1_PQ_SIZE_0                                         0xDA2090
+
+#define mmNIC3_QM1_PQ_SIZE_1                                         0xDA2094
+
+#define mmNIC3_QM1_PQ_SIZE_2                                         0xDA2098
+
+#define mmNIC3_QM1_PQ_SIZE_3                                         0xDA209C
+
+#define mmNIC3_QM1_PQ_PI_0                                           0xDA20A0
+
+#define mmNIC3_QM1_PQ_PI_1                                           0xDA20A4
+
+#define mmNIC3_QM1_PQ_PI_2                                           0xDA20A8
+
+#define mmNIC3_QM1_PQ_PI_3                                           0xDA20AC
+
+#define mmNIC3_QM1_PQ_CI_0                                           0xDA20B0
+
+#define mmNIC3_QM1_PQ_CI_1                                           0xDA20B4
+
+#define mmNIC3_QM1_PQ_CI_2                                           0xDA20B8
+
+#define mmNIC3_QM1_PQ_CI_3                                           0xDA20BC
+
+#define mmNIC3_QM1_PQ_CFG0_0                                         0xDA20C0
+
+#define mmNIC3_QM1_PQ_CFG0_1                                         0xDA20C4
+
+#define mmNIC3_QM1_PQ_CFG0_2                                         0xDA20C8
+
+#define mmNIC3_QM1_PQ_CFG0_3                                         0xDA20CC
+
+#define mmNIC3_QM1_PQ_CFG1_0                                         0xDA20D0
+
+#define mmNIC3_QM1_PQ_CFG1_1                                         0xDA20D4
+
+#define mmNIC3_QM1_PQ_CFG1_2                                         0xDA20D8
+
+#define mmNIC3_QM1_PQ_CFG1_3                                         0xDA20DC
+
+#define mmNIC3_QM1_PQ_ARUSER_31_11_0                                 0xDA20E0
+
+#define mmNIC3_QM1_PQ_ARUSER_31_11_1                                 0xDA20E4
+
+#define mmNIC3_QM1_PQ_ARUSER_31_11_2                                 0xDA20E8
+
+#define mmNIC3_QM1_PQ_ARUSER_31_11_3                                 0xDA20EC
+
+#define mmNIC3_QM1_PQ_STS0_0                                         0xDA20F0
+
+#define mmNIC3_QM1_PQ_STS0_1                                         0xDA20F4
+
+#define mmNIC3_QM1_PQ_STS0_2                                         0xDA20F8
+
+#define mmNIC3_QM1_PQ_STS0_3                                         0xDA20FC
+
+#define mmNIC3_QM1_PQ_STS1_0                                         0xDA2100
+
+#define mmNIC3_QM1_PQ_STS1_1                                         0xDA2104
+
+#define mmNIC3_QM1_PQ_STS1_2                                         0xDA2108
+
+#define mmNIC3_QM1_PQ_STS1_3                                         0xDA210C
+
+#define mmNIC3_QM1_CQ_CFG0_0                                         0xDA2110
+
+#define mmNIC3_QM1_CQ_CFG0_1                                         0xDA2114
+
+#define mmNIC3_QM1_CQ_CFG0_2                                         0xDA2118
+
+#define mmNIC3_QM1_CQ_CFG0_3                                         0xDA211C
+
+#define mmNIC3_QM1_CQ_CFG0_4                                         0xDA2120
+
+#define mmNIC3_QM1_CQ_CFG1_0                                         0xDA2124
+
+#define mmNIC3_QM1_CQ_CFG1_1                                         0xDA2128
+
+#define mmNIC3_QM1_CQ_CFG1_2                                         0xDA212C
+
+#define mmNIC3_QM1_CQ_CFG1_3                                         0xDA2130
+
+#define mmNIC3_QM1_CQ_CFG1_4                                         0xDA2134
+
+#define mmNIC3_QM1_CQ_ARUSER_31_11_0                                 0xDA2138
+
+#define mmNIC3_QM1_CQ_ARUSER_31_11_1                                 0xDA213C
+
+#define mmNIC3_QM1_CQ_ARUSER_31_11_2                                 0xDA2140
+
+#define mmNIC3_QM1_CQ_ARUSER_31_11_3                                 0xDA2144
+
+#define mmNIC3_QM1_CQ_ARUSER_31_11_4                                 0xDA2148
+
+#define mmNIC3_QM1_CQ_STS0_0                                         0xDA214C
+
+#define mmNIC3_QM1_CQ_STS0_1                                         0xDA2150
+
+#define mmNIC3_QM1_CQ_STS0_2                                         0xDA2154
+
+#define mmNIC3_QM1_CQ_STS0_3                                         0xDA2158
+
+#define mmNIC3_QM1_CQ_STS0_4                                         0xDA215C
+
+#define mmNIC3_QM1_CQ_STS1_0                                         0xDA2160
+
+#define mmNIC3_QM1_CQ_STS1_1                                         0xDA2164
+
+#define mmNIC3_QM1_CQ_STS1_2                                         0xDA2168
+
+#define mmNIC3_QM1_CQ_STS1_3                                         0xDA216C
+
+#define mmNIC3_QM1_CQ_STS1_4                                         0xDA2170
+
+#define mmNIC3_QM1_CQ_PTR_LO_0                                       0xDA2174
+
+#define mmNIC3_QM1_CQ_PTR_HI_0                                       0xDA2178
+
+#define mmNIC3_QM1_CQ_TSIZE_0                                        0xDA217C
+
+#define mmNIC3_QM1_CQ_CTL_0                                          0xDA2180
+
+#define mmNIC3_QM1_CQ_PTR_LO_1                                       0xDA2184
+
+#define mmNIC3_QM1_CQ_PTR_HI_1                                       0xDA2188
+
+#define mmNIC3_QM1_CQ_TSIZE_1                                        0xDA218C
+
+#define mmNIC3_QM1_CQ_CTL_1                                          0xDA2190
+
+#define mmNIC3_QM1_CQ_PTR_LO_2                                       0xDA2194
+
+#define mmNIC3_QM1_CQ_PTR_HI_2                                       0xDA2198
+
+#define mmNIC3_QM1_CQ_TSIZE_2                                        0xDA219C
+
+#define mmNIC3_QM1_CQ_CTL_2                                          0xDA21A0
+
+#define mmNIC3_QM1_CQ_PTR_LO_3                                       0xDA21A4
+
+#define mmNIC3_QM1_CQ_PTR_HI_3                                       0xDA21A8
+
+#define mmNIC3_QM1_CQ_TSIZE_3                                        0xDA21AC
+
+#define mmNIC3_QM1_CQ_CTL_3                                          0xDA21B0
+
+#define mmNIC3_QM1_CQ_PTR_LO_4                                       0xDA21B4
+
+#define mmNIC3_QM1_CQ_PTR_HI_4                                       0xDA21B8
+
+#define mmNIC3_QM1_CQ_TSIZE_4                                        0xDA21BC
+
+#define mmNIC3_QM1_CQ_CTL_4                                          0xDA21C0
+
+#define mmNIC3_QM1_CQ_PTR_LO_STS_0                                   0xDA21C4
+
+#define mmNIC3_QM1_CQ_PTR_LO_STS_1                                   0xDA21C8
+
+#define mmNIC3_QM1_CQ_PTR_LO_STS_2                                   0xDA21CC
+
+#define mmNIC3_QM1_CQ_PTR_LO_STS_3                                   0xDA21D0
+
+#define mmNIC3_QM1_CQ_PTR_LO_STS_4                                   0xDA21D4
+
+#define mmNIC3_QM1_CQ_PTR_HI_STS_0                                   0xDA21D8
+
+#define mmNIC3_QM1_CQ_PTR_HI_STS_1                                   0xDA21DC
+
+#define mmNIC3_QM1_CQ_PTR_HI_STS_2                                   0xDA21E0
+
+#define mmNIC3_QM1_CQ_PTR_HI_STS_3                                   0xDA21E4
+
+#define mmNIC3_QM1_CQ_PTR_HI_STS_4                                   0xDA21E8
+
+#define mmNIC3_QM1_CQ_TSIZE_STS_0                                    0xDA21EC
+
+#define mmNIC3_QM1_CQ_TSIZE_STS_1                                    0xDA21F0
+
+#define mmNIC3_QM1_CQ_TSIZE_STS_2                                    0xDA21F4
+
+#define mmNIC3_QM1_CQ_TSIZE_STS_3                                    0xDA21F8
+
+#define mmNIC3_QM1_CQ_TSIZE_STS_4                                    0xDA21FC
+
+#define mmNIC3_QM1_CQ_CTL_STS_0                                      0xDA2200
+
+#define mmNIC3_QM1_CQ_CTL_STS_1                                      0xDA2204
+
+#define mmNIC3_QM1_CQ_CTL_STS_2                                      0xDA2208
+
+#define mmNIC3_QM1_CQ_CTL_STS_3                                      0xDA220C
+
+#define mmNIC3_QM1_CQ_CTL_STS_4                                      0xDA2210
+
+#define mmNIC3_QM1_CQ_IFIFO_CNT_0                                    0xDA2214
+
+#define mmNIC3_QM1_CQ_IFIFO_CNT_1                                    0xDA2218
+
+#define mmNIC3_QM1_CQ_IFIFO_CNT_2                                    0xDA221C
+
+#define mmNIC3_QM1_CQ_IFIFO_CNT_3                                    0xDA2220
+
+#define mmNIC3_QM1_CQ_IFIFO_CNT_4                                    0xDA2224
+
+#define mmNIC3_QM1_CP_MSG_BASE0_ADDR_LO_0                            0xDA2228
+
+#define mmNIC3_QM1_CP_MSG_BASE0_ADDR_LO_1                            0xDA222C
+
+#define mmNIC3_QM1_CP_MSG_BASE0_ADDR_LO_2                            0xDA2230
+
+#define mmNIC3_QM1_CP_MSG_BASE0_ADDR_LO_3                            0xDA2234
+
+#define mmNIC3_QM1_CP_MSG_BASE0_ADDR_LO_4                            0xDA2238
+
+#define mmNIC3_QM1_CP_MSG_BASE0_ADDR_HI_0                            0xDA223C
+
+#define mmNIC3_QM1_CP_MSG_BASE0_ADDR_HI_1                            0xDA2240
+
+#define mmNIC3_QM1_CP_MSG_BASE0_ADDR_HI_2                            0xDA2244
+
+#define mmNIC3_QM1_CP_MSG_BASE0_ADDR_HI_3                            0xDA2248
+
+#define mmNIC3_QM1_CP_MSG_BASE0_ADDR_HI_4                            0xDA224C
+
+#define mmNIC3_QM1_CP_MSG_BASE1_ADDR_LO_0                            0xDA2250
+
+#define mmNIC3_QM1_CP_MSG_BASE1_ADDR_LO_1                            0xDA2254
+
+#define mmNIC3_QM1_CP_MSG_BASE1_ADDR_LO_2                            0xDA2258
+
+#define mmNIC3_QM1_CP_MSG_BASE1_ADDR_LO_3                            0xDA225C
+
+#define mmNIC3_QM1_CP_MSG_BASE1_ADDR_LO_4                            0xDA2260
+
+#define mmNIC3_QM1_CP_MSG_BASE1_ADDR_HI_0                            0xDA2264
+
+#define mmNIC3_QM1_CP_MSG_BASE1_ADDR_HI_1                            0xDA2268
+
+#define mmNIC3_QM1_CP_MSG_BASE1_ADDR_HI_2                            0xDA226C
+
+#define mmNIC3_QM1_CP_MSG_BASE1_ADDR_HI_3                            0xDA2270
+
+#define mmNIC3_QM1_CP_MSG_BASE1_ADDR_HI_4                            0xDA2274
+
+#define mmNIC3_QM1_CP_MSG_BASE2_ADDR_LO_0                            0xDA2278
+
+#define mmNIC3_QM1_CP_MSG_BASE2_ADDR_LO_1                            0xDA227C
+
+#define mmNIC3_QM1_CP_MSG_BASE2_ADDR_LO_2                            0xDA2280
+
+#define mmNIC3_QM1_CP_MSG_BASE2_ADDR_LO_3                            0xDA2284
+
+#define mmNIC3_QM1_CP_MSG_BASE2_ADDR_LO_4                            0xDA2288
+
+#define mmNIC3_QM1_CP_MSG_BASE2_ADDR_HI_0                            0xDA228C
+
+#define mmNIC3_QM1_CP_MSG_BASE2_ADDR_HI_1                            0xDA2290
+
+#define mmNIC3_QM1_CP_MSG_BASE2_ADDR_HI_2                            0xDA2294
+
+#define mmNIC3_QM1_CP_MSG_BASE2_ADDR_HI_3                            0xDA2298
+
+#define mmNIC3_QM1_CP_MSG_BASE2_ADDR_HI_4                            0xDA229C
+
+#define mmNIC3_QM1_CP_MSG_BASE3_ADDR_LO_0                            0xDA22A0
+
+#define mmNIC3_QM1_CP_MSG_BASE3_ADDR_LO_1                            0xDA22A4
+
+#define mmNIC3_QM1_CP_MSG_BASE3_ADDR_LO_2                            0xDA22A8
+
+#define mmNIC3_QM1_CP_MSG_BASE3_ADDR_LO_3                            0xDA22AC
+
+#define mmNIC3_QM1_CP_MSG_BASE3_ADDR_LO_4                            0xDA22B0
+
+#define mmNIC3_QM1_CP_MSG_BASE3_ADDR_HI_0                            0xDA22B4
+
+#define mmNIC3_QM1_CP_MSG_BASE3_ADDR_HI_1                            0xDA22B8
+
+#define mmNIC3_QM1_CP_MSG_BASE3_ADDR_HI_2                            0xDA22BC
+
+#define mmNIC3_QM1_CP_MSG_BASE3_ADDR_HI_3                            0xDA22C0
+
+#define mmNIC3_QM1_CP_MSG_BASE3_ADDR_HI_4                            0xDA22C4
+
+#define mmNIC3_QM1_CP_LDMA_TSIZE_OFFSET_0                            0xDA22C8
+
+#define mmNIC3_QM1_CP_LDMA_TSIZE_OFFSET_1                            0xDA22CC
+
+#define mmNIC3_QM1_CP_LDMA_TSIZE_OFFSET_2                            0xDA22D0
+
+#define mmNIC3_QM1_CP_LDMA_TSIZE_OFFSET_3                            0xDA22D4
+
+#define mmNIC3_QM1_CP_LDMA_TSIZE_OFFSET_4                            0xDA22D8
+
+#define mmNIC3_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_0                      0xDA22E0
+
+#define mmNIC3_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_1                      0xDA22E4
+
+#define mmNIC3_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_2                      0xDA22E8
+
+#define mmNIC3_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_3                      0xDA22EC
+
+#define mmNIC3_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_4                      0xDA22F0
+
+#define mmNIC3_QM1_CP_LDMA_DST_BASE_LO_OFFSET_0                      0xDA22F4
+
+#define mmNIC3_QM1_CP_LDMA_DST_BASE_LO_OFFSET_1                      0xDA22F8
+
+#define mmNIC3_QM1_CP_LDMA_DST_BASE_LO_OFFSET_2                      0xDA22FC
+
+#define mmNIC3_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3                      0xDA2300
+
+#define mmNIC3_QM1_CP_LDMA_DST_BASE_LO_OFFSET_4                      0xDA2304
+
+#define mmNIC3_QM1_CP_FENCE0_RDATA_0                                 0xDA2308
+
+#define mmNIC3_QM1_CP_FENCE0_RDATA_1                                 0xDA230C
+
+#define mmNIC3_QM1_CP_FENCE0_RDATA_2                                 0xDA2310
+
+#define mmNIC3_QM1_CP_FENCE0_RDATA_3                                 0xDA2314
+
+#define mmNIC3_QM1_CP_FENCE0_RDATA_4                                 0xDA2318
+
+#define mmNIC3_QM1_CP_FENCE1_RDATA_0                                 0xDA231C
+
+#define mmNIC3_QM1_CP_FENCE1_RDATA_1                                 0xDA2320
+
+#define mmNIC3_QM1_CP_FENCE1_RDATA_2                                 0xDA2324
+
+#define mmNIC3_QM1_CP_FENCE1_RDATA_3                                 0xDA2328
+
+#define mmNIC3_QM1_CP_FENCE1_RDATA_4                                 0xDA232C
+
+#define mmNIC3_QM1_CP_FENCE2_RDATA_0                                 0xDA2330
+
+#define mmNIC3_QM1_CP_FENCE2_RDATA_1                                 0xDA2334
+
+#define mmNIC3_QM1_CP_FENCE2_RDATA_2                                 0xDA2338
+
+#define mmNIC3_QM1_CP_FENCE2_RDATA_3                                 0xDA233C
+
+#define mmNIC3_QM1_CP_FENCE2_RDATA_4                                 0xDA2340
+
+#define mmNIC3_QM1_CP_FENCE3_RDATA_0                                 0xDA2344
+
+#define mmNIC3_QM1_CP_FENCE3_RDATA_1                                 0xDA2348
+
+#define mmNIC3_QM1_CP_FENCE3_RDATA_2                                 0xDA234C
+
+#define mmNIC3_QM1_CP_FENCE3_RDATA_3                                 0xDA2350
+
+#define mmNIC3_QM1_CP_FENCE3_RDATA_4                                 0xDA2354
+
+#define mmNIC3_QM1_CP_FENCE0_CNT_0                                   0xDA2358
+
+#define mmNIC3_QM1_CP_FENCE0_CNT_1                                   0xDA235C
+
+#define mmNIC3_QM1_CP_FENCE0_CNT_2                                   0xDA2360
+
+#define mmNIC3_QM1_CP_FENCE0_CNT_3                                   0xDA2364
+
+#define mmNIC3_QM1_CP_FENCE0_CNT_4                                   0xDA2368
+
+#define mmNIC3_QM1_CP_FENCE1_CNT_0                                   0xDA236C
+
+#define mmNIC3_QM1_CP_FENCE1_CNT_1                                   0xDA2370
+
+#define mmNIC3_QM1_CP_FENCE1_CNT_2                                   0xDA2374
+
+#define mmNIC3_QM1_CP_FENCE1_CNT_3                                   0xDA2378
+
+#define mmNIC3_QM1_CP_FENCE1_CNT_4                                   0xDA237C
+
+#define mmNIC3_QM1_CP_FENCE2_CNT_0                                   0xDA2380
+
+#define mmNIC3_QM1_CP_FENCE2_CNT_1                                   0xDA2384
+
+#define mmNIC3_QM1_CP_FENCE2_CNT_2                                   0xDA2388
+
+#define mmNIC3_QM1_CP_FENCE2_CNT_3                                   0xDA238C
+
+#define mmNIC3_QM1_CP_FENCE2_CNT_4                                   0xDA2390
+
+#define mmNIC3_QM1_CP_FENCE3_CNT_0                                   0xDA2394
+
+#define mmNIC3_QM1_CP_FENCE3_CNT_1                                   0xDA2398
+
+#define mmNIC3_QM1_CP_FENCE3_CNT_2                                   0xDA239C
+
+#define mmNIC3_QM1_CP_FENCE3_CNT_3                                   0xDA23A0
+
+#define mmNIC3_QM1_CP_FENCE3_CNT_4                                   0xDA23A4
+
+#define mmNIC3_QM1_CP_STS_0                                          0xDA23A8
+
+#define mmNIC3_QM1_CP_STS_1                                          0xDA23AC
+
+#define mmNIC3_QM1_CP_STS_2                                          0xDA23B0
+
+#define mmNIC3_QM1_CP_STS_3                                          0xDA23B4
+
+#define mmNIC3_QM1_CP_STS_4                                          0xDA23B8
+
+#define mmNIC3_QM1_CP_CURRENT_INST_LO_0                              0xDA23BC
+
+#define mmNIC3_QM1_CP_CURRENT_INST_LO_1                              0xDA23C0
+
+#define mmNIC3_QM1_CP_CURRENT_INST_LO_2                              0xDA23C4
+
+#define mmNIC3_QM1_CP_CURRENT_INST_LO_3                              0xDA23C8
+
+#define mmNIC3_QM1_CP_CURRENT_INST_LO_4                              0xDA23CC
+
+#define mmNIC3_QM1_CP_CURRENT_INST_HI_0                              0xDA23D0
+
+#define mmNIC3_QM1_CP_CURRENT_INST_HI_1                              0xDA23D4
+
+#define mmNIC3_QM1_CP_CURRENT_INST_HI_2                              0xDA23D8
+
+#define mmNIC3_QM1_CP_CURRENT_INST_HI_3                              0xDA23DC
+
+#define mmNIC3_QM1_CP_CURRENT_INST_HI_4                              0xDA23E0
+
+#define mmNIC3_QM1_CP_BARRIER_CFG_0                                  0xDA23F4
+
+#define mmNIC3_QM1_CP_BARRIER_CFG_1                                  0xDA23F8
+
+#define mmNIC3_QM1_CP_BARRIER_CFG_2                                  0xDA23FC
+
+#define mmNIC3_QM1_CP_BARRIER_CFG_3                                  0xDA2400
+
+#define mmNIC3_QM1_CP_BARRIER_CFG_4                                  0xDA2404
+
+#define mmNIC3_QM1_CP_DBG_0_0                                        0xDA2408
+
+#define mmNIC3_QM1_CP_DBG_0_1                                        0xDA240C
+
+#define mmNIC3_QM1_CP_DBG_0_2                                        0xDA2410
+
+#define mmNIC3_QM1_CP_DBG_0_3                                        0xDA2414
+
+#define mmNIC3_QM1_CP_DBG_0_4                                        0xDA2418
+
+#define mmNIC3_QM1_CP_ARUSER_31_11_0                                 0xDA241C
+
+#define mmNIC3_QM1_CP_ARUSER_31_11_1                                 0xDA2420
+
+#define mmNIC3_QM1_CP_ARUSER_31_11_2                                 0xDA2424
+
+#define mmNIC3_QM1_CP_ARUSER_31_11_3                                 0xDA2428
+
+#define mmNIC3_QM1_CP_ARUSER_31_11_4                                 0xDA242C
+
+#define mmNIC3_QM1_CP_AWUSER_31_11_0                                 0xDA2430
+
+#define mmNIC3_QM1_CP_AWUSER_31_11_1                                 0xDA2434
+
+#define mmNIC3_QM1_CP_AWUSER_31_11_2                                 0xDA2438
+
+#define mmNIC3_QM1_CP_AWUSER_31_11_3                                 0xDA243C
+
+#define mmNIC3_QM1_CP_AWUSER_31_11_4                                 0xDA2440
+
+#define mmNIC3_QM1_ARB_CFG_0                                         0xDA2A00
+
+#define mmNIC3_QM1_ARB_CHOISE_Q_PUSH                                 0xDA2A04
+
+#define mmNIC3_QM1_ARB_WRR_WEIGHT_0                                  0xDA2A08
+
+#define mmNIC3_QM1_ARB_WRR_WEIGHT_1                                  0xDA2A0C
+
+#define mmNIC3_QM1_ARB_WRR_WEIGHT_2                                  0xDA2A10
+
+#define mmNIC3_QM1_ARB_WRR_WEIGHT_3                                  0xDA2A14
+
+#define mmNIC3_QM1_ARB_CFG_1                                         0xDA2A18
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_0                              0xDA2A20
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_1                              0xDA2A24
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_2                              0xDA2A28
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_3                              0xDA2A2C
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_4                              0xDA2A30
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_5                              0xDA2A34
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_6                              0xDA2A38
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_7                              0xDA2A3C
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_8                              0xDA2A40
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_9                              0xDA2A44
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_10                             0xDA2A48
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_11                             0xDA2A4C
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_12                             0xDA2A50
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_13                             0xDA2A54
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_14                             0xDA2A58
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_15                             0xDA2A5C
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_16                             0xDA2A60
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_17                             0xDA2A64
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_18                             0xDA2A68
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_19                             0xDA2A6C
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_20                             0xDA2A70
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_21                             0xDA2A74
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_22                             0xDA2A78
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_23                             0xDA2A7C
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_24                             0xDA2A80
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_25                             0xDA2A84
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_26                             0xDA2A88
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_27                             0xDA2A8C
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_28                             0xDA2A90
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_29                             0xDA2A94
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_30                             0xDA2A98
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_31                             0xDA2A9C
+
+#define mmNIC3_QM1_ARB_MST_CRED_INC                                  0xDA2AA0
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_0                        0xDA2AA4
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_1                        0xDA2AA8
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_2                        0xDA2AAC
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_3                        0xDA2AB0
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_4                        0xDA2AB4
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_5                        0xDA2AB8
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_6                        0xDA2ABC
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_7                        0xDA2AC0
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_8                        0xDA2AC4
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_9                        0xDA2AC8
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_10                       0xDA2ACC
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_11                       0xDA2AD0
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_12                       0xDA2AD4
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_13                       0xDA2AD8
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_14                       0xDA2ADC
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_15                       0xDA2AE0
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_16                       0xDA2AE4
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_17                       0xDA2AE8
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_18                       0xDA2AEC
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_19                       0xDA2AF0
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_20                       0xDA2AF4
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_21                       0xDA2AF8
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_22                       0xDA2AFC
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_23                       0xDA2B00
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_24                       0xDA2B04
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_25                       0xDA2B08
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_26                       0xDA2B0C
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_27                       0xDA2B10
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_28                       0xDA2B14
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_29                       0xDA2B18
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_30                       0xDA2B1C
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_31                       0xDA2B20
+
+#define mmNIC3_QM1_ARB_SLV_MASTER_INC_CRED_OFST                      0xDA2B28
+
+#define mmNIC3_QM1_ARB_MST_SLAVE_EN                                  0xDA2B2C
+
+#define mmNIC3_QM1_ARB_MST_QUIET_PER                                 0xDA2B34
+
+#define mmNIC3_QM1_ARB_SLV_CHOISE_WDT                                0xDA2B38
+
+#define mmNIC3_QM1_ARB_SLV_ID                                        0xDA2B3C
+
+#define mmNIC3_QM1_ARB_MSG_MAX_INFLIGHT                              0xDA2B44
+
+#define mmNIC3_QM1_ARB_MSG_AWUSER_31_11                              0xDA2B48
+
+#define mmNIC3_QM1_ARB_MSG_AWUSER_SEC_PROP                           0xDA2B4C
+
+#define mmNIC3_QM1_ARB_MSG_AWUSER_NON_SEC_PROP                       0xDA2B50
+
+#define mmNIC3_QM1_ARB_BASE_LO                                       0xDA2B54
+
+#define mmNIC3_QM1_ARB_BASE_HI                                       0xDA2B58
+
+#define mmNIC3_QM1_ARB_STATE_STS                                     0xDA2B80
+
+#define mmNIC3_QM1_ARB_CHOISE_FULLNESS_STS                           0xDA2B84
+
+#define mmNIC3_QM1_ARB_MSG_STS                                       0xDA2B88
+
+#define mmNIC3_QM1_ARB_SLV_CHOISE_Q_HEAD                             0xDA2B8C
+
+#define mmNIC3_QM1_ARB_ERR_CAUSE                                     0xDA2B9C
+
+#define mmNIC3_QM1_ARB_ERR_MSG_EN                                    0xDA2BA0
+
+#define mmNIC3_QM1_ARB_ERR_STS_DRP                                   0xDA2BA8
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_0                                0xDA2BB0
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_1                                0xDA2BB4
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_2                                0xDA2BB8
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_3                                0xDA2BBC
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_4                                0xDA2BC0
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_5                                0xDA2BC4
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_6                                0xDA2BC8
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_7                                0xDA2BCC
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_8                                0xDA2BD0
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_9                                0xDA2BD4
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_10                               0xDA2BD8
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_11                               0xDA2BDC
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_12                               0xDA2BE0
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_13                               0xDA2BE4
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_14                               0xDA2BE8
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_15                               0xDA2BEC
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_16                               0xDA2BF0
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_17                               0xDA2BF4
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_18                               0xDA2BF8
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_19                               0xDA2BFC
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_20                               0xDA2C00
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_21                               0xDA2C04
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_22                               0xDA2C08
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_23                               0xDA2C0C
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_24                               0xDA2C10
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_25                               0xDA2C14
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_26                               0xDA2C18
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_27                               0xDA2C1C
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_28                               0xDA2C20
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_29                               0xDA2C24
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_30                               0xDA2C28
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_31                               0xDA2C2C
+
+#define mmNIC3_QM1_CGM_CFG                                           0xDA2C70
+
+#define mmNIC3_QM1_CGM_STS                                           0xDA2C74
+
+#define mmNIC3_QM1_CGM_CFG1                                          0xDA2C78
+
+#define mmNIC3_QM1_LOCAL_RANGE_BASE                                  0xDA2C80
+
+#define mmNIC3_QM1_LOCAL_RANGE_SIZE                                  0xDA2C84
+
+#define mmNIC3_QM1_CSMR_STRICT_PRIO_CFG                              0xDA2C90
+
+#define mmNIC3_QM1_HBW_RD_RATE_LIM_CFG_1                             0xDA2C94
+
+#define mmNIC3_QM1_LBW_WR_RATE_LIM_CFG_0                             0xDA2C98
+
+#define mmNIC3_QM1_LBW_WR_RATE_LIM_CFG_1                             0xDA2C9C
+
+#define mmNIC3_QM1_HBW_RD_RATE_LIM_CFG_0                             0xDA2CA0
+
+#define mmNIC3_QM1_GLBL_AXCACHE                                      0xDA2CA4
+
+#define mmNIC3_QM1_IND_GW_APB_CFG                                    0xDA2CB0
+
+#define mmNIC3_QM1_IND_GW_APB_WDATA                                  0xDA2CB4
+
+#define mmNIC3_QM1_IND_GW_APB_RDATA                                  0xDA2CB8
+
+#define mmNIC3_QM1_IND_GW_APB_STATUS                                 0xDA2CBC
+
+#define mmNIC3_QM1_GLBL_ERR_ADDR_LO                                  0xDA2CD0
+
+#define mmNIC3_QM1_GLBL_ERR_ADDR_HI                                  0xDA2CD4
+
+#define mmNIC3_QM1_GLBL_ERR_WDATA                                    0xDA2CD8
+
+#define mmNIC3_QM1_GLBL_MEM_INIT_BUSY                                0xDA2D00
+
+#endif /* ASIC_REG_NIC3_QM1_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/nic4_qm0_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic4_qm0_regs.h
new file mode 100644
index 000000000000..99d5319672dd
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic4_qm0_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_NIC4_QM0_REGS_H_
+#define ASIC_REG_NIC4_QM0_REGS_H_
+
+/*
+ *****************************************
+ *   NIC4_QM0 (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmNIC4_QM0_GLBL_CFG0                                         0xDE0000
+
+#define mmNIC4_QM0_GLBL_CFG1                                         0xDE0004
+
+#define mmNIC4_QM0_GLBL_PROT                                         0xDE0008
+
+#define mmNIC4_QM0_GLBL_ERR_CFG                                      0xDE000C
+
+#define mmNIC4_QM0_GLBL_SECURE_PROPS_0                               0xDE0010
+
+#define mmNIC4_QM0_GLBL_SECURE_PROPS_1                               0xDE0014
+
+#define mmNIC4_QM0_GLBL_SECURE_PROPS_2                               0xDE0018
+
+#define mmNIC4_QM0_GLBL_SECURE_PROPS_3                               0xDE001C
+
+#define mmNIC4_QM0_GLBL_SECURE_PROPS_4                               0xDE0020
+
+#define mmNIC4_QM0_GLBL_NON_SECURE_PROPS_0                           0xDE0024
+
+#define mmNIC4_QM0_GLBL_NON_SECURE_PROPS_1                           0xDE0028
+
+#define mmNIC4_QM0_GLBL_NON_SECURE_PROPS_2                           0xDE002C
+
+#define mmNIC4_QM0_GLBL_NON_SECURE_PROPS_3                           0xDE0030
+
+#define mmNIC4_QM0_GLBL_NON_SECURE_PROPS_4                           0xDE0034
+
+#define mmNIC4_QM0_GLBL_STS0                                         0xDE0038
+
+#define mmNIC4_QM0_GLBL_STS1_0                                       0xDE0040
+
+#define mmNIC4_QM0_GLBL_STS1_1                                       0xDE0044
+
+#define mmNIC4_QM0_GLBL_STS1_2                                       0xDE0048
+
+#define mmNIC4_QM0_GLBL_STS1_3                                       0xDE004C
+
+#define mmNIC4_QM0_GLBL_STS1_4                                       0xDE0050
+
+#define mmNIC4_QM0_GLBL_MSG_EN_0                                     0xDE0054
+
+#define mmNIC4_QM0_GLBL_MSG_EN_1                                     0xDE0058
+
+#define mmNIC4_QM0_GLBL_MSG_EN_2                                     0xDE005C
+
+#define mmNIC4_QM0_GLBL_MSG_EN_3                                     0xDE0060
+
+#define mmNIC4_QM0_GLBL_MSG_EN_4                                     0xDE0068
+
+#define mmNIC4_QM0_PQ_BASE_LO_0                                      0xDE0070
+
+#define mmNIC4_QM0_PQ_BASE_LO_1                                      0xDE0074
+
+#define mmNIC4_QM0_PQ_BASE_LO_2                                      0xDE0078
+
+#define mmNIC4_QM0_PQ_BASE_LO_3                                      0xDE007C
+
+#define mmNIC4_QM0_PQ_BASE_HI_0                                      0xDE0080
+
+#define mmNIC4_QM0_PQ_BASE_HI_1                                      0xDE0084
+
+#define mmNIC4_QM0_PQ_BASE_HI_2                                      0xDE0088
+
+#define mmNIC4_QM0_PQ_BASE_HI_3                                      0xDE008C
+
+#define mmNIC4_QM0_PQ_SIZE_0                                         0xDE0090
+
+#define mmNIC4_QM0_PQ_SIZE_1                                         0xDE0094
+
+#define mmNIC4_QM0_PQ_SIZE_2                                         0xDE0098
+
+#define mmNIC4_QM0_PQ_SIZE_3                                         0xDE009C
+
+#define mmNIC4_QM0_PQ_PI_0                                           0xDE00A0
+
+#define mmNIC4_QM0_PQ_PI_1                                           0xDE00A4
+
+#define mmNIC4_QM0_PQ_PI_2                                           0xDE00A8
+
+#define mmNIC4_QM0_PQ_PI_3                                           0xDE00AC
+
+#define mmNIC4_QM0_PQ_CI_0                                           0xDE00B0
+
+#define mmNIC4_QM0_PQ_CI_1                                           0xDE00B4
+
+#define mmNIC4_QM0_PQ_CI_2                                           0xDE00B8
+
+#define mmNIC4_QM0_PQ_CI_3                                           0xDE00BC
+
+#define mmNIC4_QM0_PQ_CFG0_0                                         0xDE00C0
+
+#define mmNIC4_QM0_PQ_CFG0_1                                         0xDE00C4
+
+#define mmNIC4_QM0_PQ_CFG0_2                                         0xDE00C8
+
+#define mmNIC4_QM0_PQ_CFG0_3                                         0xDE00CC
+
+#define mmNIC4_QM0_PQ_CFG1_0                                         0xDE00D0
+
+#define mmNIC4_QM0_PQ_CFG1_1                                         0xDE00D4
+
+#define mmNIC4_QM0_PQ_CFG1_2                                         0xDE00D8
+
+#define mmNIC4_QM0_PQ_CFG1_3                                         0xDE00DC
+
+#define mmNIC4_QM0_PQ_ARUSER_31_11_0                                 0xDE00E0
+
+#define mmNIC4_QM0_PQ_ARUSER_31_11_1                                 0xDE00E4
+
+#define mmNIC4_QM0_PQ_ARUSER_31_11_2                                 0xDE00E8
+
+#define mmNIC4_QM0_PQ_ARUSER_31_11_3                                 0xDE00EC
+
+#define mmNIC4_QM0_PQ_STS0_0                                         0xDE00F0
+
+#define mmNIC4_QM0_PQ_STS0_1                                         0xDE00F4
+
+#define mmNIC4_QM0_PQ_STS0_2                                         0xDE00F8
+
+#define mmNIC4_QM0_PQ_STS0_3                                         0xDE00FC
+
+#define mmNIC4_QM0_PQ_STS1_0                                         0xDE0100
+
+#define mmNIC4_QM0_PQ_STS1_1                                         0xDE0104
+
+#define mmNIC4_QM0_PQ_STS1_2                                         0xDE0108
+
+#define mmNIC4_QM0_PQ_STS1_3                                         0xDE010C
+
+#define mmNIC4_QM0_CQ_CFG0_0                                         0xDE0110
+
+#define mmNIC4_QM0_CQ_CFG0_1                                         0xDE0114
+
+#define mmNIC4_QM0_CQ_CFG0_2                                         0xDE0118
+
+#define mmNIC4_QM0_CQ_CFG0_3                                         0xDE011C
+
+#define mmNIC4_QM0_CQ_CFG0_4                                         0xDE0120
+
+#define mmNIC4_QM0_CQ_CFG1_0                                         0xDE0124
+
+#define mmNIC4_QM0_CQ_CFG1_1                                         0xDE0128
+
+#define mmNIC4_QM0_CQ_CFG1_2                                         0xDE012C
+
+#define mmNIC4_QM0_CQ_CFG1_3                                         0xDE0130
+
+#define mmNIC4_QM0_CQ_CFG1_4                                         0xDE0134
+
+#define mmNIC4_QM0_CQ_ARUSER_31_11_0                                 0xDE0138
+
+#define mmNIC4_QM0_CQ_ARUSER_31_11_1                                 0xDE013C
+
+#define mmNIC4_QM0_CQ_ARUSER_31_11_2                                 0xDE0140
+
+#define mmNIC4_QM0_CQ_ARUSER_31_11_3                                 0xDE0144
+
+#define mmNIC4_QM0_CQ_ARUSER_31_11_4                                 0xDE0148
+
+#define mmNIC4_QM0_CQ_STS0_0                                         0xDE014C
+
+#define mmNIC4_QM0_CQ_STS0_1                                         0xDE0150
+
+#define mmNIC4_QM0_CQ_STS0_2                                         0xDE0154
+
+#define mmNIC4_QM0_CQ_STS0_3                                         0xDE0158
+
+#define mmNIC4_QM0_CQ_STS0_4                                         0xDE015C
+
+#define mmNIC4_QM0_CQ_STS1_0                                         0xDE0160
+
+#define mmNIC4_QM0_CQ_STS1_1                                         0xDE0164
+
+#define mmNIC4_QM0_CQ_STS1_2                                         0xDE0168
+
+#define mmNIC4_QM0_CQ_STS1_3                                         0xDE016C
+
+#define mmNIC4_QM0_CQ_STS1_4                                         0xDE0170
+
+#define mmNIC4_QM0_CQ_PTR_LO_0                                       0xDE0174
+
+#define mmNIC4_QM0_CQ_PTR_HI_0                                       0xDE0178
+
+#define mmNIC4_QM0_CQ_TSIZE_0                                        0xDE017C
+
+#define mmNIC4_QM0_CQ_CTL_0                                          0xDE0180
+
+#define mmNIC4_QM0_CQ_PTR_LO_1                                       0xDE0184
+
+#define mmNIC4_QM0_CQ_PTR_HI_1                                       0xDE0188
+
+#define mmNIC4_QM0_CQ_TSIZE_1                                        0xDE018C
+
+#define mmNIC4_QM0_CQ_CTL_1                                          0xDE0190
+
+#define mmNIC4_QM0_CQ_PTR_LO_2                                       0xDE0194
+
+#define mmNIC4_QM0_CQ_PTR_HI_2                                       0xDE0198
+
+#define mmNIC4_QM0_CQ_TSIZE_2                                        0xDE019C
+
+#define mmNIC4_QM0_CQ_CTL_2                                          0xDE01A0
+
+#define mmNIC4_QM0_CQ_PTR_LO_3                                       0xDE01A4
+
+#define mmNIC4_QM0_CQ_PTR_HI_3                                       0xDE01A8
+
+#define mmNIC4_QM0_CQ_TSIZE_3                                        0xDE01AC
+
+#define mmNIC4_QM0_CQ_CTL_3                                          0xDE01B0
+
+#define mmNIC4_QM0_CQ_PTR_LO_4                                       0xDE01B4
+
+#define mmNIC4_QM0_CQ_PTR_HI_4                                       0xDE01B8
+
+#define mmNIC4_QM0_CQ_TSIZE_4                                        0xDE01BC
+
+#define mmNIC4_QM0_CQ_CTL_4                                          0xDE01C0
+
+#define mmNIC4_QM0_CQ_PTR_LO_STS_0                                   0xDE01C4
+
+#define mmNIC4_QM0_CQ_PTR_LO_STS_1                                   0xDE01C8
+
+#define mmNIC4_QM0_CQ_PTR_LO_STS_2                                   0xDE01CC
+
+#define mmNIC4_QM0_CQ_PTR_LO_STS_3                                   0xDE01D0
+
+#define mmNIC4_QM0_CQ_PTR_LO_STS_4                                   0xDE01D4
+
+#define mmNIC4_QM0_CQ_PTR_HI_STS_0                                   0xDE01D8
+
+#define mmNIC4_QM0_CQ_PTR_HI_STS_1                                   0xDE01DC
+
+#define mmNIC4_QM0_CQ_PTR_HI_STS_2                                   0xDE01E0
+
+#define mmNIC4_QM0_CQ_PTR_HI_STS_3                                   0xDE01E4
+
+#define mmNIC4_QM0_CQ_PTR_HI_STS_4                                   0xDE01E8
+
+#define mmNIC4_QM0_CQ_TSIZE_STS_0                                    0xDE01EC
+
+#define mmNIC4_QM0_CQ_TSIZE_STS_1                                    0xDE01F0
+
+#define mmNIC4_QM0_CQ_TSIZE_STS_2                                    0xDE01F4
+
+#define mmNIC4_QM0_CQ_TSIZE_STS_3                                    0xDE01F8
+
+#define mmNIC4_QM0_CQ_TSIZE_STS_4                                    0xDE01FC
+
+#define mmNIC4_QM0_CQ_CTL_STS_0                                      0xDE0200
+
+#define mmNIC4_QM0_CQ_CTL_STS_1                                      0xDE0204
+
+#define mmNIC4_QM0_CQ_CTL_STS_2                                      0xDE0208
+
+#define mmNIC4_QM0_CQ_CTL_STS_3                                      0xDE020C
+
+#define mmNIC4_QM0_CQ_CTL_STS_4                                      0xDE0210
+
+#define mmNIC4_QM0_CQ_IFIFO_CNT_0                                    0xDE0214
+
+#define mmNIC4_QM0_CQ_IFIFO_CNT_1                                    0xDE0218
+
+#define mmNIC4_QM0_CQ_IFIFO_CNT_2                                    0xDE021C
+
+#define mmNIC4_QM0_CQ_IFIFO_CNT_3                                    0xDE0220
+
+#define mmNIC4_QM0_CQ_IFIFO_CNT_4                                    0xDE0224
+
+#define mmNIC4_QM0_CP_MSG_BASE0_ADDR_LO_0                            0xDE0228
+
+#define mmNIC4_QM0_CP_MSG_BASE0_ADDR_LO_1                            0xDE022C
+
+#define mmNIC4_QM0_CP_MSG_BASE0_ADDR_LO_2                            0xDE0230
+
+#define mmNIC4_QM0_CP_MSG_BASE0_ADDR_LO_3                            0xDE0234
+
+#define mmNIC4_QM0_CP_MSG_BASE0_ADDR_LO_4                            0xDE0238
+
+#define mmNIC4_QM0_CP_MSG_BASE0_ADDR_HI_0                            0xDE023C
+
+#define mmNIC4_QM0_CP_MSG_BASE0_ADDR_HI_1                            0xDE0240
+
+#define mmNIC4_QM0_CP_MSG_BASE0_ADDR_HI_2                            0xDE0244
+
+#define mmNIC4_QM0_CP_MSG_BASE0_ADDR_HI_3                            0xDE0248
+
+#define mmNIC4_QM0_CP_MSG_BASE0_ADDR_HI_4                            0xDE024C
+
+#define mmNIC4_QM0_CP_MSG_BASE1_ADDR_LO_0                            0xDE0250
+
+#define mmNIC4_QM0_CP_MSG_BASE1_ADDR_LO_1                            0xDE0254
+
+#define mmNIC4_QM0_CP_MSG_BASE1_ADDR_LO_2                            0xDE0258
+
+#define mmNIC4_QM0_CP_MSG_BASE1_ADDR_LO_3                            0xDE025C
+
+#define mmNIC4_QM0_CP_MSG_BASE1_ADDR_LO_4                            0xDE0260
+
+#define mmNIC4_QM0_CP_MSG_BASE1_ADDR_HI_0                            0xDE0264
+
+#define mmNIC4_QM0_CP_MSG_BASE1_ADDR_HI_1                            0xDE0268
+
+#define mmNIC4_QM0_CP_MSG_BASE1_ADDR_HI_2                            0xDE026C
+
+#define mmNIC4_QM0_CP_MSG_BASE1_ADDR_HI_3                            0xDE0270
+
+#define mmNIC4_QM0_CP_MSG_BASE1_ADDR_HI_4                            0xDE0274
+
+#define mmNIC4_QM0_CP_MSG_BASE2_ADDR_LO_0                            0xDE0278
+
+#define mmNIC4_QM0_CP_MSG_BASE2_ADDR_LO_1                            0xDE027C
+
+#define mmNIC4_QM0_CP_MSG_BASE2_ADDR_LO_2                            0xDE0280
+
+#define mmNIC4_QM0_CP_MSG_BASE2_ADDR_LO_3                            0xDE0284
+
+#define mmNIC4_QM0_CP_MSG_BASE2_ADDR_LO_4                            0xDE0288
+
+#define mmNIC4_QM0_CP_MSG_BASE2_ADDR_HI_0                            0xDE028C
+
+#define mmNIC4_QM0_CP_MSG_BASE2_ADDR_HI_1                            0xDE0290
+
+#define mmNIC4_QM0_CP_MSG_BASE2_ADDR_HI_2                            0xDE0294
+
+#define mmNIC4_QM0_CP_MSG_BASE2_ADDR_HI_3                            0xDE0298
+
+#define mmNIC4_QM0_CP_MSG_BASE2_ADDR_HI_4                            0xDE029C
+
+#define mmNIC4_QM0_CP_MSG_BASE3_ADDR_LO_0                            0xDE02A0
+
+#define mmNIC4_QM0_CP_MSG_BASE3_ADDR_LO_1                            0xDE02A4
+
+#define mmNIC4_QM0_CP_MSG_BASE3_ADDR_LO_2                            0xDE02A8
+
+#define mmNIC4_QM0_CP_MSG_BASE3_ADDR_LO_3                            0xDE02AC
+
+#define mmNIC4_QM0_CP_MSG_BASE3_ADDR_LO_4                            0xDE02B0
+
+#define mmNIC4_QM0_CP_MSG_BASE3_ADDR_HI_0                            0xDE02B4
+
+#define mmNIC4_QM0_CP_MSG_BASE3_ADDR_HI_1                            0xDE02B8
+
+#define mmNIC4_QM0_CP_MSG_BASE3_ADDR_HI_2                            0xDE02BC
+
+#define mmNIC4_QM0_CP_MSG_BASE3_ADDR_HI_3                            0xDE02C0
+
+#define mmNIC4_QM0_CP_MSG_BASE3_ADDR_HI_4                            0xDE02C4
+
+#define mmNIC4_QM0_CP_LDMA_TSIZE_OFFSET_0                            0xDE02C8
+
+#define mmNIC4_QM0_CP_LDMA_TSIZE_OFFSET_1                            0xDE02CC
+
+#define mmNIC4_QM0_CP_LDMA_TSIZE_OFFSET_2                            0xDE02D0
+
+#define mmNIC4_QM0_CP_LDMA_TSIZE_OFFSET_3                            0xDE02D4
+
+#define mmNIC4_QM0_CP_LDMA_TSIZE_OFFSET_4                            0xDE02D8
+
+#define mmNIC4_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_0                      0xDE02E0
+
+#define mmNIC4_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_1                      0xDE02E4
+
+#define mmNIC4_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_2                      0xDE02E8
+
+#define mmNIC4_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_3                      0xDE02EC
+
+#define mmNIC4_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_4                      0xDE02F0
+
+#define mmNIC4_QM0_CP_LDMA_DST_BASE_LO_OFFSET_0                      0xDE02F4
+
+#define mmNIC4_QM0_CP_LDMA_DST_BASE_LO_OFFSET_1                      0xDE02F8
+
+#define mmNIC4_QM0_CP_LDMA_DST_BASE_LO_OFFSET_2                      0xDE02FC
+
+#define mmNIC4_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3                      0xDE0300
+
+#define mmNIC4_QM0_CP_LDMA_DST_BASE_LO_OFFSET_4                      0xDE0304
+
+#define mmNIC4_QM0_CP_FENCE0_RDATA_0                                 0xDE0308
+
+#define mmNIC4_QM0_CP_FENCE0_RDATA_1                                 0xDE030C
+
+#define mmNIC4_QM0_CP_FENCE0_RDATA_2                                 0xDE0310
+
+#define mmNIC4_QM0_CP_FENCE0_RDATA_3                                 0xDE0314
+
+#define mmNIC4_QM0_CP_FENCE0_RDATA_4                                 0xDE0318
+
+#define mmNIC4_QM0_CP_FENCE1_RDATA_0                                 0xDE031C
+
+#define mmNIC4_QM0_CP_FENCE1_RDATA_1                                 0xDE0320
+
+#define mmNIC4_QM0_CP_FENCE1_RDATA_2                                 0xDE0324
+
+#define mmNIC4_QM0_CP_FENCE1_RDATA_3                                 0xDE0328
+
+#define mmNIC4_QM0_CP_FENCE1_RDATA_4                                 0xDE032C
+
+#define mmNIC4_QM0_CP_FENCE2_RDATA_0                                 0xDE0330
+
+#define mmNIC4_QM0_CP_FENCE2_RDATA_1                                 0xDE0334
+
+#define mmNIC4_QM0_CP_FENCE2_RDATA_2                                 0xDE0338
+
+#define mmNIC4_QM0_CP_FENCE2_RDATA_3                                 0xDE033C
+
+#define mmNIC4_QM0_CP_FENCE2_RDATA_4                                 0xDE0340
+
+#define mmNIC4_QM0_CP_FENCE3_RDATA_0                                 0xDE0344
+
+#define mmNIC4_QM0_CP_FENCE3_RDATA_1                                 0xDE0348
+
+#define mmNIC4_QM0_CP_FENCE3_RDATA_2                                 0xDE034C
+
+#define mmNIC4_QM0_CP_FENCE3_RDATA_3                                 0xDE0350
+
+#define mmNIC4_QM0_CP_FENCE3_RDATA_4                                 0xDE0354
+
+#define mmNIC4_QM0_CP_FENCE0_CNT_0                                   0xDE0358
+
+#define mmNIC4_QM0_CP_FENCE0_CNT_1                                   0xDE035C
+
+#define mmNIC4_QM0_CP_FENCE0_CNT_2                                   0xDE0360
+
+#define mmNIC4_QM0_CP_FENCE0_CNT_3                                   0xDE0364
+
+#define mmNIC4_QM0_CP_FENCE0_CNT_4                                   0xDE0368
+
+#define mmNIC4_QM0_CP_FENCE1_CNT_0                                   0xDE036C
+
+#define mmNIC4_QM0_CP_FENCE1_CNT_1                                   0xDE0370
+
+#define mmNIC4_QM0_CP_FENCE1_CNT_2                                   0xDE0374
+
+#define mmNIC4_QM0_CP_FENCE1_CNT_3                                   0xDE0378
+
+#define mmNIC4_QM0_CP_FENCE1_CNT_4                                   0xDE037C
+
+#define mmNIC4_QM0_CP_FENCE2_CNT_0                                   0xDE0380
+
+#define mmNIC4_QM0_CP_FENCE2_CNT_1                                   0xDE0384
+
+#define mmNIC4_QM0_CP_FENCE2_CNT_2                                   0xDE0388
+
+#define mmNIC4_QM0_CP_FENCE2_CNT_3                                   0xDE038C
+
+#define mmNIC4_QM0_CP_FENCE2_CNT_4                                   0xDE0390
+
+#define mmNIC4_QM0_CP_FENCE3_CNT_0                                   0xDE0394
+
+#define mmNIC4_QM0_CP_FENCE3_CNT_1                                   0xDE0398
+
+#define mmNIC4_QM0_CP_FENCE3_CNT_2                                   0xDE039C
+
+#define mmNIC4_QM0_CP_FENCE3_CNT_3                                   0xDE03A0
+
+#define mmNIC4_QM0_CP_FENCE3_CNT_4                                   0xDE03A4
+
+#define mmNIC4_QM0_CP_STS_0                                          0xDE03A8
+
+#define mmNIC4_QM0_CP_STS_1                                          0xDE03AC
+
+#define mmNIC4_QM0_CP_STS_2                                          0xDE03B0
+
+#define mmNIC4_QM0_CP_STS_3                                          0xDE03B4
+
+#define mmNIC4_QM0_CP_STS_4                                          0xDE03B8
+
+#define mmNIC4_QM0_CP_CURRENT_INST_LO_0                              0xDE03BC
+
+#define mmNIC4_QM0_CP_CURRENT_INST_LO_1                              0xDE03C0
+
+#define mmNIC4_QM0_CP_CURRENT_INST_LO_2                              0xDE03C4
+
+#define mmNIC4_QM0_CP_CURRENT_INST_LO_3                              0xDE03C8
+
+#define mmNIC4_QM0_CP_CURRENT_INST_LO_4                              0xDE03CC
+
+#define mmNIC4_QM0_CP_CURRENT_INST_HI_0                              0xDE03D0
+
+#define mmNIC4_QM0_CP_CURRENT_INST_HI_1                              0xDE03D4
+
+#define mmNIC4_QM0_CP_CURRENT_INST_HI_2                              0xDE03D8
+
+#define mmNIC4_QM0_CP_CURRENT_INST_HI_3                              0xDE03DC
+
+#define mmNIC4_QM0_CP_CURRENT_INST_HI_4                              0xDE03E0
+
+#define mmNIC4_QM0_CP_BARRIER_CFG_0                                  0xDE03F4
+
+#define mmNIC4_QM0_CP_BARRIER_CFG_1                                  0xDE03F8
+
+#define mmNIC4_QM0_CP_BARRIER_CFG_2                                  0xDE03FC
+
+#define mmNIC4_QM0_CP_BARRIER_CFG_3                                  0xDE0400
+
+#define mmNIC4_QM0_CP_BARRIER_CFG_4                                  0xDE0404
+
+#define mmNIC4_QM0_CP_DBG_0_0                                        0xDE0408
+
+#define mmNIC4_QM0_CP_DBG_0_1                                        0xDE040C
+
+#define mmNIC4_QM0_CP_DBG_0_2                                        0xDE0410
+
+#define mmNIC4_QM0_CP_DBG_0_3                                        0xDE0414
+
+#define mmNIC4_QM0_CP_DBG_0_4                                        0xDE0418
+
+#define mmNIC4_QM0_CP_ARUSER_31_11_0                                 0xDE041C
+
+#define mmNIC4_QM0_CP_ARUSER_31_11_1                                 0xDE0420
+
+#define mmNIC4_QM0_CP_ARUSER_31_11_2                                 0xDE0424
+
+#define mmNIC4_QM0_CP_ARUSER_31_11_3                                 0xDE0428
+
+#define mmNIC4_QM0_CP_ARUSER_31_11_4                                 0xDE042C
+
+#define mmNIC4_QM0_CP_AWUSER_31_11_0                                 0xDE0430
+
+#define mmNIC4_QM0_CP_AWUSER_31_11_1                                 0xDE0434
+
+#define mmNIC4_QM0_CP_AWUSER_31_11_2                                 0xDE0438
+
+#define mmNIC4_QM0_CP_AWUSER_31_11_3                                 0xDE043C
+
+#define mmNIC4_QM0_CP_AWUSER_31_11_4                                 0xDE0440
+
+#define mmNIC4_QM0_ARB_CFG_0                                         0xDE0A00
+
+#define mmNIC4_QM0_ARB_CHOISE_Q_PUSH                                 0xDE0A04
+
+#define mmNIC4_QM0_ARB_WRR_WEIGHT_0                                  0xDE0A08
+
+#define mmNIC4_QM0_ARB_WRR_WEIGHT_1                                  0xDE0A0C
+
+#define mmNIC4_QM0_ARB_WRR_WEIGHT_2                                  0xDE0A10
+
+#define mmNIC4_QM0_ARB_WRR_WEIGHT_3                                  0xDE0A14
+
+#define mmNIC4_QM0_ARB_CFG_1                                         0xDE0A18
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_0                              0xDE0A20
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_1                              0xDE0A24
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_2                              0xDE0A28
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_3                              0xDE0A2C
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_4                              0xDE0A30
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_5                              0xDE0A34
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_6                              0xDE0A38
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_7                              0xDE0A3C
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_8                              0xDE0A40
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_9                              0xDE0A44
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_10                             0xDE0A48
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_11                             0xDE0A4C
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_12                             0xDE0A50
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_13                             0xDE0A54
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_14                             0xDE0A58
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_15                             0xDE0A5C
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_16                             0xDE0A60
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_17                             0xDE0A64
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_18                             0xDE0A68
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_19                             0xDE0A6C
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_20                             0xDE0A70
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_21                             0xDE0A74
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_22                             0xDE0A78
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_23                             0xDE0A7C
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_24                             0xDE0A80
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_25                             0xDE0A84
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_26                             0xDE0A88
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_27                             0xDE0A8C
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_28                             0xDE0A90
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_29                             0xDE0A94
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_30                             0xDE0A98
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_31                             0xDE0A9C
+
+#define mmNIC4_QM0_ARB_MST_CRED_INC                                  0xDE0AA0
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_0                        0xDE0AA4
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_1                        0xDE0AA8
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_2                        0xDE0AAC
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_3                        0xDE0AB0
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_4                        0xDE0AB4
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_5                        0xDE0AB8
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_6                        0xDE0ABC
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_7                        0xDE0AC0
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_8                        0xDE0AC4
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_9                        0xDE0AC8
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_10                       0xDE0ACC
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_11                       0xDE0AD0
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_12                       0xDE0AD4
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_13                       0xDE0AD8
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_14                       0xDE0ADC
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_15                       0xDE0AE0
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_16                       0xDE0AE4
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_17                       0xDE0AE8
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_18                       0xDE0AEC
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_19                       0xDE0AF0
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_20                       0xDE0AF4
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_21                       0xDE0AF8
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_22                       0xDE0AFC
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_23                       0xDE0B00
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_24                       0xDE0B04
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_25                       0xDE0B08
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_26                       0xDE0B0C
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_27                       0xDE0B10
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_28                       0xDE0B14
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_29                       0xDE0B18
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_30                       0xDE0B1C
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_31                       0xDE0B20
+
+#define mmNIC4_QM0_ARB_SLV_MASTER_INC_CRED_OFST                      0xDE0B28
+
+#define mmNIC4_QM0_ARB_MST_SLAVE_EN                                  0xDE0B2C
+
+#define mmNIC4_QM0_ARB_MST_QUIET_PER                                 0xDE0B34
+
+#define mmNIC4_QM0_ARB_SLV_CHOISE_WDT                                0xDE0B38
+
+#define mmNIC4_QM0_ARB_SLV_ID                                        0xDE0B3C
+
+#define mmNIC4_QM0_ARB_MSG_MAX_INFLIGHT                              0xDE0B44
+
+#define mmNIC4_QM0_ARB_MSG_AWUSER_31_11                              0xDE0B48
+
+#define mmNIC4_QM0_ARB_MSG_AWUSER_SEC_PROP                           0xDE0B4C
+
+#define mmNIC4_QM0_ARB_MSG_AWUSER_NON_SEC_PROP                       0xDE0B50
+
+#define mmNIC4_QM0_ARB_BASE_LO                                       0xDE0B54
+
+#define mmNIC4_QM0_ARB_BASE_HI                                       0xDE0B58
+
+#define mmNIC4_QM0_ARB_STATE_STS                                     0xDE0B80
+
+#define mmNIC4_QM0_ARB_CHOISE_FULLNESS_STS                           0xDE0B84
+
+#define mmNIC4_QM0_ARB_MSG_STS                                       0xDE0B88
+
+#define mmNIC4_QM0_ARB_SLV_CHOISE_Q_HEAD                             0xDE0B8C
+
+#define mmNIC4_QM0_ARB_ERR_CAUSE                                     0xDE0B9C
+
+#define mmNIC4_QM0_ARB_ERR_MSG_EN                                    0xDE0BA0
+
+#define mmNIC4_QM0_ARB_ERR_STS_DRP                                   0xDE0BA8
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_0                                0xDE0BB0
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_1                                0xDE0BB4
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_2                                0xDE0BB8
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_3                                0xDE0BBC
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_4                                0xDE0BC0
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_5                                0xDE0BC4
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_6                                0xDE0BC8
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_7                                0xDE0BCC
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_8                                0xDE0BD0
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_9                                0xDE0BD4
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_10                               0xDE0BD8
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_11                               0xDE0BDC
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_12                               0xDE0BE0
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_13                               0xDE0BE4
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_14                               0xDE0BE8
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_15                               0xDE0BEC
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_16                               0xDE0BF0
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_17                               0xDE0BF4
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_18                               0xDE0BF8
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_19                               0xDE0BFC
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_20                               0xDE0C00
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_21                               0xDE0C04
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_22                               0xDE0C08
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_23                               0xDE0C0C
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_24                               0xDE0C10
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_25                               0xDE0C14
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_26                               0xDE0C18
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_27                               0xDE0C1C
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_28                               0xDE0C20
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_29                               0xDE0C24
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_30                               0xDE0C28
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_31                               0xDE0C2C
+
+#define mmNIC4_QM0_CGM_CFG                                           0xDE0C70
+
+#define mmNIC4_QM0_CGM_STS                                           0xDE0C74
+
+#define mmNIC4_QM0_CGM_CFG1                                          0xDE0C78
+
+#define mmNIC4_QM0_LOCAL_RANGE_BASE                                  0xDE0C80
+
+#define mmNIC4_QM0_LOCAL_RANGE_SIZE                                  0xDE0C84
+
+#define mmNIC4_QM0_CSMR_STRICT_PRIO_CFG                              0xDE0C90
+
+#define mmNIC4_QM0_HBW_RD_RATE_LIM_CFG_1                             0xDE0C94
+
+#define mmNIC4_QM0_LBW_WR_RATE_LIM_CFG_0                             0xDE0C98
+
+#define mmNIC4_QM0_LBW_WR_RATE_LIM_CFG_1                             0xDE0C9C
+
+#define mmNIC4_QM0_HBW_RD_RATE_LIM_CFG_0                             0xDE0CA0
+
+#define mmNIC4_QM0_GLBL_AXCACHE                                      0xDE0CA4
+
+#define mmNIC4_QM0_IND_GW_APB_CFG                                    0xDE0CB0
+
+#define mmNIC4_QM0_IND_GW_APB_WDATA                                  0xDE0CB4
+
+#define mmNIC4_QM0_IND_GW_APB_RDATA                                  0xDE0CB8
+
+#define mmNIC4_QM0_IND_GW_APB_STATUS                                 0xDE0CBC
+
+#define mmNIC4_QM0_GLBL_ERR_ADDR_LO                                  0xDE0CD0
+
+#define mmNIC4_QM0_GLBL_ERR_ADDR_HI                                  0xDE0CD4
+
+#define mmNIC4_QM0_GLBL_ERR_WDATA                                    0xDE0CD8
+
+#define mmNIC4_QM0_GLBL_MEM_INIT_BUSY                                0xDE0D00
+
+#endif /* ASIC_REG_NIC4_QM0_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/nic4_qm1_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic4_qm1_regs.h
new file mode 100644
index 000000000000..34b21b21da52
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic4_qm1_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_NIC4_QM1_REGS_H_
+#define ASIC_REG_NIC4_QM1_REGS_H_
+
+/*
+ *****************************************
+ *   NIC4_QM1 (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmNIC4_QM1_GLBL_CFG0                                         0xDE2000
+
+#define mmNIC4_QM1_GLBL_CFG1                                         0xDE2004
+
+#define mmNIC4_QM1_GLBL_PROT                                         0xDE2008
+
+#define mmNIC4_QM1_GLBL_ERR_CFG                                      0xDE200C
+
+#define mmNIC4_QM1_GLBL_SECURE_PROPS_0                               0xDE2010
+
+#define mmNIC4_QM1_GLBL_SECURE_PROPS_1                               0xDE2014
+
+#define mmNIC4_QM1_GLBL_SECURE_PROPS_2                               0xDE2018
+
+#define mmNIC4_QM1_GLBL_SECURE_PROPS_3                               0xDE201C
+
+#define mmNIC4_QM1_GLBL_SECURE_PROPS_4                               0xDE2020
+
+#define mmNIC4_QM1_GLBL_NON_SECURE_PROPS_0                           0xDE2024
+
+#define mmNIC4_QM1_GLBL_NON_SECURE_PROPS_1                           0xDE2028
+
+#define mmNIC4_QM1_GLBL_NON_SECURE_PROPS_2                           0xDE202C
+
+#define mmNIC4_QM1_GLBL_NON_SECURE_PROPS_3                           0xDE2030
+
+#define mmNIC4_QM1_GLBL_NON_SECURE_PROPS_4                           0xDE2034
+
+#define mmNIC4_QM1_GLBL_STS0                                         0xDE2038
+
+#define mmNIC4_QM1_GLBL_STS1_0                                       0xDE2040
+
+#define mmNIC4_QM1_GLBL_STS1_1                                       0xDE2044
+
+#define mmNIC4_QM1_GLBL_STS1_2                                       0xDE2048
+
+#define mmNIC4_QM1_GLBL_STS1_3                                       0xDE204C
+
+#define mmNIC4_QM1_GLBL_STS1_4                                       0xDE2050
+
+#define mmNIC4_QM1_GLBL_MSG_EN_0                                     0xDE2054
+
+#define mmNIC4_QM1_GLBL_MSG_EN_1                                     0xDE2058
+
+#define mmNIC4_QM1_GLBL_MSG_EN_2                                     0xDE205C
+
+#define mmNIC4_QM1_GLBL_MSG_EN_3                                     0xDE2060
+
+#define mmNIC4_QM1_GLBL_MSG_EN_4                                     0xDE2068
+
+#define mmNIC4_QM1_PQ_BASE_LO_0                                      0xDE2070
+
+#define mmNIC4_QM1_PQ_BASE_LO_1                                      0xDE2074
+
+#define mmNIC4_QM1_PQ_BASE_LO_2                                      0xDE2078
+
+#define mmNIC4_QM1_PQ_BASE_LO_3                                      0xDE207C
+
+#define mmNIC4_QM1_PQ_BASE_HI_0                                      0xDE2080
+
+#define mmNIC4_QM1_PQ_BASE_HI_1                                      0xDE2084
+
+#define mmNIC4_QM1_PQ_BASE_HI_2                                      0xDE2088
+
+#define mmNIC4_QM1_PQ_BASE_HI_3                                      0xDE208C
+
+#define mmNIC4_QM1_PQ_SIZE_0                                         0xDE2090
+
+#define mmNIC4_QM1_PQ_SIZE_1                                         0xDE2094
+
+#define mmNIC4_QM1_PQ_SIZE_2                                         0xDE2098
+
+#define mmNIC4_QM1_PQ_SIZE_3                                         0xDE209C
+
+#define mmNIC4_QM1_PQ_PI_0                                           0xDE20A0
+
+#define mmNIC4_QM1_PQ_PI_1                                           0xDE20A4
+
+#define mmNIC4_QM1_PQ_PI_2                                           0xDE20A8
+
+#define mmNIC4_QM1_PQ_PI_3                                           0xDE20AC
+
+#define mmNIC4_QM1_PQ_CI_0                                           0xDE20B0
+
+#define mmNIC4_QM1_PQ_CI_1                                           0xDE20B4
+
+#define mmNIC4_QM1_PQ_CI_2                                           0xDE20B8
+
+#define mmNIC4_QM1_PQ_CI_3                                           0xDE20BC
+
+#define mmNIC4_QM1_PQ_CFG0_0                                         0xDE20C0
+
+#define mmNIC4_QM1_PQ_CFG0_1                                         0xDE20C4
+
+#define mmNIC4_QM1_PQ_CFG0_2                                         0xDE20C8
+
+#define mmNIC4_QM1_PQ_CFG0_3                                         0xDE20CC
+
+#define mmNIC4_QM1_PQ_CFG1_0                                         0xDE20D0
+
+#define mmNIC4_QM1_PQ_CFG1_1                                         0xDE20D4
+
+#define mmNIC4_QM1_PQ_CFG1_2                                         0xDE20D8
+
+#define mmNIC4_QM1_PQ_CFG1_3                                         0xDE20DC
+
+#define mmNIC4_QM1_PQ_ARUSER_31_11_0                                 0xDE20E0
+
+#define mmNIC4_QM1_PQ_ARUSER_31_11_1                                 0xDE20E4
+
+#define mmNIC4_QM1_PQ_ARUSER_31_11_2                                 0xDE20E8
+
+#define mmNIC4_QM1_PQ_ARUSER_31_11_3                                 0xDE20EC
+
+#define mmNIC4_QM1_PQ_STS0_0                                         0xDE20F0
+
+#define mmNIC4_QM1_PQ_STS0_1                                         0xDE20F4
+
+#define mmNIC4_QM1_PQ_STS0_2                                         0xDE20F8
+
+#define mmNIC4_QM1_PQ_STS0_3                                         0xDE20FC
+
+#define mmNIC4_QM1_PQ_STS1_0                                         0xDE2100
+
+#define mmNIC4_QM1_PQ_STS1_1                                         0xDE2104
+
+#define mmNIC4_QM1_PQ_STS1_2                                         0xDE2108
+
+#define mmNIC4_QM1_PQ_STS1_3                                         0xDE210C
+
+#define mmNIC4_QM1_CQ_CFG0_0                                         0xDE2110
+
+#define mmNIC4_QM1_CQ_CFG0_1                                         0xDE2114
+
+#define mmNIC4_QM1_CQ_CFG0_2                                         0xDE2118
+
+#define mmNIC4_QM1_CQ_CFG0_3                                         0xDE211C
+
+#define mmNIC4_QM1_CQ_CFG0_4                                         0xDE2120
+
+#define mmNIC4_QM1_CQ_CFG1_0                                         0xDE2124
+
+#define mmNIC4_QM1_CQ_CFG1_1                                         0xDE2128
+
+#define mmNIC4_QM1_CQ_CFG1_2                                         0xDE212C
+
+#define mmNIC4_QM1_CQ_CFG1_3                                         0xDE2130
+
+#define mmNIC4_QM1_CQ_CFG1_4                                         0xDE2134
+
+#define mmNIC4_QM1_CQ_ARUSER_31_11_0                                 0xDE2138
+
+#define mmNIC4_QM1_CQ_ARUSER_31_11_1                                 0xDE213C
+
+#define mmNIC4_QM1_CQ_ARUSER_31_11_2                                 0xDE2140
+
+#define mmNIC4_QM1_CQ_ARUSER_31_11_3                                 0xDE2144
+
+#define mmNIC4_QM1_CQ_ARUSER_31_11_4                                 0xDE2148
+
+#define mmNIC4_QM1_CQ_STS0_0                                         0xDE214C
+
+#define mmNIC4_QM1_CQ_STS0_1                                         0xDE2150
+
+#define mmNIC4_QM1_CQ_STS0_2                                         0xDE2154
+
+#define mmNIC4_QM1_CQ_STS0_3                                         0xDE2158
+
+#define mmNIC4_QM1_CQ_STS0_4                                         0xDE215C
+
+#define mmNIC4_QM1_CQ_STS1_0                                         0xDE2160
+
+#define mmNIC4_QM1_CQ_STS1_1                                         0xDE2164
+
+#define mmNIC4_QM1_CQ_STS1_2                                         0xDE2168
+
+#define mmNIC4_QM1_CQ_STS1_3                                         0xDE216C
+
+#define mmNIC4_QM1_CQ_STS1_4                                         0xDE2170
+
+#define mmNIC4_QM1_CQ_PTR_LO_0                                       0xDE2174
+
+#define mmNIC4_QM1_CQ_PTR_HI_0                                       0xDE2178
+
+#define mmNIC4_QM1_CQ_TSIZE_0                                        0xDE217C
+
+#define mmNIC4_QM1_CQ_CTL_0                                          0xDE2180
+
+#define mmNIC4_QM1_CQ_PTR_LO_1                                       0xDE2184
+
+#define mmNIC4_QM1_CQ_PTR_HI_1                                       0xDE2188
+
+#define mmNIC4_QM1_CQ_TSIZE_1                                        0xDE218C
+
+#define mmNIC4_QM1_CQ_CTL_1                                          0xDE2190
+
+#define mmNIC4_QM1_CQ_PTR_LO_2                                       0xDE2194
+
+#define mmNIC4_QM1_CQ_PTR_HI_2                                       0xDE2198
+
+#define mmNIC4_QM1_CQ_TSIZE_2                                        0xDE219C
+
+#define mmNIC4_QM1_CQ_CTL_2                                          0xDE21A0
+
+#define mmNIC4_QM1_CQ_PTR_LO_3                                       0xDE21A4
+
+#define mmNIC4_QM1_CQ_PTR_HI_3                                       0xDE21A8
+
+#define mmNIC4_QM1_CQ_TSIZE_3                                        0xDE21AC
+
+#define mmNIC4_QM1_CQ_CTL_3                                          0xDE21B0
+
+#define mmNIC4_QM1_CQ_PTR_LO_4                                       0xDE21B4
+
+#define mmNIC4_QM1_CQ_PTR_HI_4                                       0xDE21B8
+
+#define mmNIC4_QM1_CQ_TSIZE_4                                        0xDE21BC
+
+#define mmNIC4_QM1_CQ_CTL_4                                          0xDE21C0
+
+#define mmNIC4_QM1_CQ_PTR_LO_STS_0                                   0xDE21C4
+
+#define mmNIC4_QM1_CQ_PTR_LO_STS_1                                   0xDE21C8
+
+#define mmNIC4_QM1_CQ_PTR_LO_STS_2                                   0xDE21CC
+
+#define mmNIC4_QM1_CQ_PTR_LO_STS_3                                   0xDE21D0
+
+#define mmNIC4_QM1_CQ_PTR_LO_STS_4                                   0xDE21D4
+
+#define mmNIC4_QM1_CQ_PTR_HI_STS_0                                   0xDE21D8
+
+#define mmNIC4_QM1_CQ_PTR_HI_STS_1                                   0xDE21DC
+
+#define mmNIC4_QM1_CQ_PTR_HI_STS_2                                   0xDE21E0
+
+#define mmNIC4_QM1_CQ_PTR_HI_STS_3                                   0xDE21E4
+
+#define mmNIC4_QM1_CQ_PTR_HI_STS_4                                   0xDE21E8
+
+#define mmNIC4_QM1_CQ_TSIZE_STS_0                                    0xDE21EC
+
+#define mmNIC4_QM1_CQ_TSIZE_STS_1                                    0xDE21F0
+
+#define mmNIC4_QM1_CQ_TSIZE_STS_2                                    0xDE21F4
+
+#define mmNIC4_QM1_CQ_TSIZE_STS_3                                    0xDE21F8
+
+#define mmNIC4_QM1_CQ_TSIZE_STS_4                                    0xDE21FC
+
+#define mmNIC4_QM1_CQ_CTL_STS_0                                      0xDE2200
+
+#define mmNIC4_QM1_CQ_CTL_STS_1                                      0xDE2204
+
+#define mmNIC4_QM1_CQ_CTL_STS_2                                      0xDE2208
+
+#define mmNIC4_QM1_CQ_CTL_STS_3                                      0xDE220C
+
+#define mmNIC4_QM1_CQ_CTL_STS_4                                      0xDE2210
+
+#define mmNIC4_QM1_CQ_IFIFO_CNT_0                                    0xDE2214
+
+#define mmNIC4_QM1_CQ_IFIFO_CNT_1                                    0xDE2218
+
+#define mmNIC4_QM1_CQ_IFIFO_CNT_2                                    0xDE221C
+
+#define mmNIC4_QM1_CQ_IFIFO_CNT_3                                    0xDE2220
+
+#define mmNIC4_QM1_CQ_IFIFO_CNT_4                                    0xDE2224
+
+#define mmNIC4_QM1_CP_MSG_BASE0_ADDR_LO_0                            0xDE2228
+
+#define mmNIC4_QM1_CP_MSG_BASE0_ADDR_LO_1                            0xDE222C
+
+#define mmNIC4_QM1_CP_MSG_BASE0_ADDR_LO_2                            0xDE2230
+
+#define mmNIC4_QM1_CP_MSG_BASE0_ADDR_LO_3                            0xDE2234
+
+#define mmNIC4_QM1_CP_MSG_BASE0_ADDR_LO_4                            0xDE2238
+
+#define mmNIC4_QM1_CP_MSG_BASE0_ADDR_HI_0                            0xDE223C
+
+#define mmNIC4_QM1_CP_MSG_BASE0_ADDR_HI_1                            0xDE2240
+
+#define mmNIC4_QM1_CP_MSG_BASE0_ADDR_HI_2                            0xDE2244
+
+#define mmNIC4_QM1_CP_MSG_BASE0_ADDR_HI_3                            0xDE2248
+
+#define mmNIC4_QM1_CP_MSG_BASE0_ADDR_HI_4                            0xDE224C
+
+#define mmNIC4_QM1_CP_MSG_BASE1_ADDR_LO_0                            0xDE2250
+
+#define mmNIC4_QM1_CP_MSG_BASE1_ADDR_LO_1                            0xDE2254
+
+#define mmNIC4_QM1_CP_MSG_BASE1_ADDR_LO_2                            0xDE2258
+
+#define mmNIC4_QM1_CP_MSG_BASE1_ADDR_LO_3                            0xDE225C
+
+#define mmNIC4_QM1_CP_MSG_BASE1_ADDR_LO_4                            0xDE2260
+
+#define mmNIC4_QM1_CP_MSG_BASE1_ADDR_HI_0                            0xDE2264
+
+#define mmNIC4_QM1_CP_MSG_BASE1_ADDR_HI_1                            0xDE2268
+
+#define mmNIC4_QM1_CP_MSG_BASE1_ADDR_HI_2                            0xDE226C
+
+#define mmNIC4_QM1_CP_MSG_BASE1_ADDR_HI_3                            0xDE2270
+
+#define mmNIC4_QM1_CP_MSG_BASE1_ADDR_HI_4                            0xDE2274
+
+#define mmNIC4_QM1_CP_MSG_BASE2_ADDR_LO_0                            0xDE2278
+
+#define mmNIC4_QM1_CP_MSG_BASE2_ADDR_LO_1                            0xDE227C
+
+#define mmNIC4_QM1_CP_MSG_BASE2_ADDR_LO_2                            0xDE2280
+
+#define mmNIC4_QM1_CP_MSG_BASE2_ADDR_LO_3                            0xDE2284
+
+#define mmNIC4_QM1_CP_MSG_BASE2_ADDR_LO_4                            0xDE2288
+
+#define mmNIC4_QM1_CP_MSG_BASE2_ADDR_HI_0                            0xDE228C
+
+#define mmNIC4_QM1_CP_MSG_BASE2_ADDR_HI_1                            0xDE2290
+
+#define mmNIC4_QM1_CP_MSG_BASE2_ADDR_HI_2                            0xDE2294
+
+#define mmNIC4_QM1_CP_MSG_BASE2_ADDR_HI_3                            0xDE2298
+
+#define mmNIC4_QM1_CP_MSG_BASE2_ADDR_HI_4                            0xDE229C
+
+#define mmNIC4_QM1_CP_MSG_BASE3_ADDR_LO_0                            0xDE22A0
+
+#define mmNIC4_QM1_CP_MSG_BASE3_ADDR_LO_1                            0xDE22A4
+
+#define mmNIC4_QM1_CP_MSG_BASE3_ADDR_LO_2                            0xDE22A8
+
+#define mmNIC4_QM1_CP_MSG_BASE3_ADDR_LO_3                            0xDE22AC
+
+#define mmNIC4_QM1_CP_MSG_BASE3_ADDR_LO_4                            0xDE22B0
+
+#define mmNIC4_QM1_CP_MSG_BASE3_ADDR_HI_0                            0xDE22B4
+
+#define mmNIC4_QM1_CP_MSG_BASE3_ADDR_HI_1                            0xDE22B8
+
+#define mmNIC4_QM1_CP_MSG_BASE3_ADDR_HI_2                            0xDE22BC
+
+#define mmNIC4_QM1_CP_MSG_BASE3_ADDR_HI_3                            0xDE22C0
+
+#define mmNIC4_QM1_CP_MSG_BASE3_ADDR_HI_4                            0xDE22C4
+
+#define mmNIC4_QM1_CP_LDMA_TSIZE_OFFSET_0                            0xDE22C8
+
+#define mmNIC4_QM1_CP_LDMA_TSIZE_OFFSET_1                            0xDE22CC
+
+#define mmNIC4_QM1_CP_LDMA_TSIZE_OFFSET_2                            0xDE22D0
+
+#define mmNIC4_QM1_CP_LDMA_TSIZE_OFFSET_3                            0xDE22D4
+
+#define mmNIC4_QM1_CP_LDMA_TSIZE_OFFSET_4                            0xDE22D8
+
+#define mmNIC4_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_0                      0xDE22E0
+
+#define mmNIC4_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_1                      0xDE22E4
+
+#define mmNIC4_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_2                      0xDE22E8
+
+#define mmNIC4_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_3                      0xDE22EC
+
+#define mmNIC4_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_4                      0xDE22F0
+
+#define mmNIC4_QM1_CP_LDMA_DST_BASE_LO_OFFSET_0                      0xDE22F4
+
+#define mmNIC4_QM1_CP_LDMA_DST_BASE_LO_OFFSET_1                      0xDE22F8
+
+#define mmNIC4_QM1_CP_LDMA_DST_BASE_LO_OFFSET_2                      0xDE22FC
+
+#define mmNIC4_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3                      0xDE2300
+
+#define mmNIC4_QM1_CP_LDMA_DST_BASE_LO_OFFSET_4                      0xDE2304
+
+#define mmNIC4_QM1_CP_FENCE0_RDATA_0                                 0xDE2308
+
+#define mmNIC4_QM1_CP_FENCE0_RDATA_1                                 0xDE230C
+
+#define mmNIC4_QM1_CP_FENCE0_RDATA_2                                 0xDE2310
+
+#define mmNIC4_QM1_CP_FENCE0_RDATA_3                                 0xDE2314
+
+#define mmNIC4_QM1_CP_FENCE0_RDATA_4                                 0xDE2318
+
+#define mmNIC4_QM1_CP_FENCE1_RDATA_0                                 0xDE231C
+
+#define mmNIC4_QM1_CP_FENCE1_RDATA_1                                 0xDE2320
+
+#define mmNIC4_QM1_CP_FENCE1_RDATA_2                                 0xDE2324
+
+#define mmNIC4_QM1_CP_FENCE1_RDATA_3                                 0xDE2328
+
+#define mmNIC4_QM1_CP_FENCE1_RDATA_4                                 0xDE232C
+
+#define mmNIC4_QM1_CP_FENCE2_RDATA_0                                 0xDE2330
+
+#define mmNIC4_QM1_CP_FENCE2_RDATA_1                                 0xDE2334
+
+#define mmNIC4_QM1_CP_FENCE2_RDATA_2                                 0xDE2338
+
+#define mmNIC4_QM1_CP_FENCE2_RDATA_3                                 0xDE233C
+
+#define mmNIC4_QM1_CP_FENCE2_RDATA_4                                 0xDE2340
+
+#define mmNIC4_QM1_CP_FENCE3_RDATA_0                                 0xDE2344
+
+#define mmNIC4_QM1_CP_FENCE3_RDATA_1                                 0xDE2348
+
+#define mmNIC4_QM1_CP_FENCE3_RDATA_2                                 0xDE234C
+
+#define mmNIC4_QM1_CP_FENCE3_RDATA_3                                 0xDE2350
+
+#define mmNIC4_QM1_CP_FENCE3_RDATA_4                                 0xDE2354
+
+#define mmNIC4_QM1_CP_FENCE0_CNT_0                                   0xDE2358
+
+#define mmNIC4_QM1_CP_FENCE0_CNT_1                                   0xDE235C
+
+#define mmNIC4_QM1_CP_FENCE0_CNT_2                                   0xDE2360
+
+#define mmNIC4_QM1_CP_FENCE0_CNT_3                                   0xDE2364
+
+#define mmNIC4_QM1_CP_FENCE0_CNT_4                                   0xDE2368
+
+#define mmNIC4_QM1_CP_FENCE1_CNT_0                                   0xDE236C
+
+#define mmNIC4_QM1_CP_FENCE1_CNT_1                                   0xDE2370
+
+#define mmNIC4_QM1_CP_FENCE1_CNT_2                                   0xDE2374
+
+#define mmNIC4_QM1_CP_FENCE1_CNT_3                                   0xDE2378
+
+#define mmNIC4_QM1_CP_FENCE1_CNT_4                                   0xDE237C
+
+#define mmNIC4_QM1_CP_FENCE2_CNT_0                                   0xDE2380
+
+#define mmNIC4_QM1_CP_FENCE2_CNT_1                                   0xDE2384
+
+#define mmNIC4_QM1_CP_FENCE2_CNT_2                                   0xDE2388
+
+#define mmNIC4_QM1_CP_FENCE2_CNT_3                                   0xDE238C
+
+#define mmNIC4_QM1_CP_FENCE2_CNT_4                                   0xDE2390
+
+#define mmNIC4_QM1_CP_FENCE3_CNT_0                                   0xDE2394
+
+#define mmNIC4_QM1_CP_FENCE3_CNT_1                                   0xDE2398
+
+#define mmNIC4_QM1_CP_FENCE3_CNT_2                                   0xDE239C
+
+#define mmNIC4_QM1_CP_FENCE3_CNT_3                                   0xDE23A0
+
+#define mmNIC4_QM1_CP_FENCE3_CNT_4                                   0xDE23A4
+
+#define mmNIC4_QM1_CP_STS_0                                          0xDE23A8
+
+#define mmNIC4_QM1_CP_STS_1                                          0xDE23AC
+
+#define mmNIC4_QM1_CP_STS_2                                          0xDE23B0
+
+#define mmNIC4_QM1_CP_STS_3                                          0xDE23B4
+
+#define mmNIC4_QM1_CP_STS_4                                          0xDE23B8
+
+#define mmNIC4_QM1_CP_CURRENT_INST_LO_0                              0xDE23BC
+
+#define mmNIC4_QM1_CP_CURRENT_INST_LO_1                              0xDE23C0
+
+#define mmNIC4_QM1_CP_CURRENT_INST_LO_2                              0xDE23C4
+
+#define mmNIC4_QM1_CP_CURRENT_INST_LO_3                              0xDE23C8
+
+#define mmNIC4_QM1_CP_CURRENT_INST_LO_4                              0xDE23CC
+
+#define mmNIC4_QM1_CP_CURRENT_INST_HI_0                              0xDE23D0
+
+#define mmNIC4_QM1_CP_CURRENT_INST_HI_1                              0xDE23D4
+
+#define mmNIC4_QM1_CP_CURRENT_INST_HI_2                              0xDE23D8
+
+#define mmNIC4_QM1_CP_CURRENT_INST_HI_3                              0xDE23DC
+
+#define mmNIC4_QM1_CP_CURRENT_INST_HI_4                              0xDE23E0
+
+#define mmNIC4_QM1_CP_BARRIER_CFG_0                                  0xDE23F4
+
+#define mmNIC4_QM1_CP_BARRIER_CFG_1                                  0xDE23F8
+
+#define mmNIC4_QM1_CP_BARRIER_CFG_2                                  0xDE23FC
+
+#define mmNIC4_QM1_CP_BARRIER_CFG_3                                  0xDE2400
+
+#define mmNIC4_QM1_CP_BARRIER_CFG_4                                  0xDE2404
+
+#define mmNIC4_QM1_CP_DBG_0_0                                        0xDE2408
+
+#define mmNIC4_QM1_CP_DBG_0_1                                        0xDE240C
+
+#define mmNIC4_QM1_CP_DBG_0_2                                        0xDE2410
+
+#define mmNIC4_QM1_CP_DBG_0_3                                        0xDE2414
+
+#define mmNIC4_QM1_CP_DBG_0_4                                        0xDE2418
+
+#define mmNIC4_QM1_CP_ARUSER_31_11_0                                 0xDE241C
+
+#define mmNIC4_QM1_CP_ARUSER_31_11_1                                 0xDE2420
+
+#define mmNIC4_QM1_CP_ARUSER_31_11_2                                 0xDE2424
+
+#define mmNIC4_QM1_CP_ARUSER_31_11_3                                 0xDE2428
+
+#define mmNIC4_QM1_CP_ARUSER_31_11_4                                 0xDE242C
+
+#define mmNIC4_QM1_CP_AWUSER_31_11_0                                 0xDE2430
+
+#define mmNIC4_QM1_CP_AWUSER_31_11_1                                 0xDE2434
+
+#define mmNIC4_QM1_CP_AWUSER_31_11_2                                 0xDE2438
+
+#define mmNIC4_QM1_CP_AWUSER_31_11_3                                 0xDE243C
+
+#define mmNIC4_QM1_CP_AWUSER_31_11_4                                 0xDE2440
+
+#define mmNIC4_QM1_ARB_CFG_0                                         0xDE2A00
+
+#define mmNIC4_QM1_ARB_CHOISE_Q_PUSH                                 0xDE2A04
+
+#define mmNIC4_QM1_ARB_WRR_WEIGHT_0                                  0xDE2A08
+
+#define mmNIC4_QM1_ARB_WRR_WEIGHT_1                                  0xDE2A0C
+
+#define mmNIC4_QM1_ARB_WRR_WEIGHT_2                                  0xDE2A10
+
+#define mmNIC4_QM1_ARB_WRR_WEIGHT_3                                  0xDE2A14
+
+#define mmNIC4_QM1_ARB_CFG_1                                         0xDE2A18
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_0                              0xDE2A20
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_1                              0xDE2A24
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_2                              0xDE2A28
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_3                              0xDE2A2C
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_4                              0xDE2A30
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_5                              0xDE2A34
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_6                              0xDE2A38
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_7                              0xDE2A3C
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_8                              0xDE2A40
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_9                              0xDE2A44
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_10                             0xDE2A48
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_11                             0xDE2A4C
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_12                             0xDE2A50
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_13                             0xDE2A54
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_14                             0xDE2A58
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_15                             0xDE2A5C
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_16                             0xDE2A60
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_17                             0xDE2A64
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_18                             0xDE2A68
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_19                             0xDE2A6C
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_20                             0xDE2A70
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_21                             0xDE2A74
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_22                             0xDE2A78
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_23                             0xDE2A7C
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_24                             0xDE2A80
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_25                             0xDE2A84
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_26                             0xDE2A88
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_27                             0xDE2A8C
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_28                             0xDE2A90
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_29                             0xDE2A94
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_30                             0xDE2A98
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_31                             0xDE2A9C
+
+#define mmNIC4_QM1_ARB_MST_CRED_INC                                  0xDE2AA0
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_0                        0xDE2AA4
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_1                        0xDE2AA8
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_2                        0xDE2AAC
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_3                        0xDE2AB0
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_4                        0xDE2AB4
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_5                        0xDE2AB8
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_6                        0xDE2ABC
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_7                        0xDE2AC0
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_8                        0xDE2AC4
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_9                        0xDE2AC8
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_10                       0xDE2ACC
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_11                       0xDE2AD0
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_12                       0xDE2AD4
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_13                       0xDE2AD8
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_14                       0xDE2ADC
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_15                       0xDE2AE0
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_16                       0xDE2AE4
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_17                       0xDE2AE8
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_18                       0xDE2AEC
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_19                       0xDE2AF0
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_20                       0xDE2AF4
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_21                       0xDE2AF8
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_22                       0xDE2AFC
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_23                       0xDE2B00
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_24                       0xDE2B04
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_25                       0xDE2B08
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_26                       0xDE2B0C
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_27                       0xDE2B10
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_28                       0xDE2B14
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_29                       0xDE2B18
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_30                       0xDE2B1C
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_31                       0xDE2B20
+
+#define mmNIC4_QM1_ARB_SLV_MASTER_INC_CRED_OFST                      0xDE2B28
+
+#define mmNIC4_QM1_ARB_MST_SLAVE_EN                                  0xDE2B2C
+
+#define mmNIC4_QM1_ARB_MST_QUIET_PER                                 0xDE2B34
+
+#define mmNIC4_QM1_ARB_SLV_CHOISE_WDT                                0xDE2B38
+
+#define mmNIC4_QM1_ARB_SLV_ID                                        0xDE2B3C
+
+#define mmNIC4_QM1_ARB_MSG_MAX_INFLIGHT                              0xDE2B44
+
+#define mmNIC4_QM1_ARB_MSG_AWUSER_31_11                              0xDE2B48
+
+#define mmNIC4_QM1_ARB_MSG_AWUSER_SEC_PROP                           0xDE2B4C
+
+#define mmNIC4_QM1_ARB_MSG_AWUSER_NON_SEC_PROP                       0xDE2B50
+
+#define mmNIC4_QM1_ARB_BASE_LO                                       0xDE2B54
+
+#define mmNIC4_QM1_ARB_BASE_HI                                       0xDE2B58
+
+#define mmNIC4_QM1_ARB_STATE_STS                                     0xDE2B80
+
+#define mmNIC4_QM1_ARB_CHOISE_FULLNESS_STS                           0xDE2B84
+
+#define mmNIC4_QM1_ARB_MSG_STS                                       0xDE2B88
+
+#define mmNIC4_QM1_ARB_SLV_CHOISE_Q_HEAD                             0xDE2B8C
+
+#define mmNIC4_QM1_ARB_ERR_CAUSE                                     0xDE2B9C
+
+#define mmNIC4_QM1_ARB_ERR_MSG_EN                                    0xDE2BA0
+
+#define mmNIC4_QM1_ARB_ERR_STS_DRP                                   0xDE2BA8
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_0                                0xDE2BB0
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_1                                0xDE2BB4
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_2                                0xDE2BB8
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_3                                0xDE2BBC
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_4                                0xDE2BC0
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_5                                0xDE2BC4
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_6                                0xDE2BC8
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_7                                0xDE2BCC
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_8                                0xDE2BD0
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_9                                0xDE2BD4
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_10                               0xDE2BD8
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_11                               0xDE2BDC
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_12                               0xDE2BE0
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_13                               0xDE2BE4
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_14                               0xDE2BE8
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_15                               0xDE2BEC
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_16                               0xDE2BF0
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_17                               0xDE2BF4
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_18                               0xDE2BF8
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_19                               0xDE2BFC
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_20                               0xDE2C00
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_21                               0xDE2C04
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_22                               0xDE2C08
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_23                               0xDE2C0C
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_24                               0xDE2C10
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_25                               0xDE2C14
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_26                               0xDE2C18
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_27                               0xDE2C1C
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_28                               0xDE2C20
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_29                               0xDE2C24
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_30                               0xDE2C28
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_31                               0xDE2C2C
+
+#define mmNIC4_QM1_CGM_CFG                                           0xDE2C70
+
+#define mmNIC4_QM1_CGM_STS                                           0xDE2C74
+
+#define mmNIC4_QM1_CGM_CFG1                                          0xDE2C78
+
+#define mmNIC4_QM1_LOCAL_RANGE_BASE                                  0xDE2C80
+
+#define mmNIC4_QM1_LOCAL_RANGE_SIZE                                  0xDE2C84
+
+#define mmNIC4_QM1_CSMR_STRICT_PRIO_CFG                              0xDE2C90
+
+#define mmNIC4_QM1_HBW_RD_RATE_LIM_CFG_1                             0xDE2C94
+
+#define mmNIC4_QM1_LBW_WR_RATE_LIM_CFG_0                             0xDE2C98
+
+#define mmNIC4_QM1_LBW_WR_RATE_LIM_CFG_1                             0xDE2C9C
+
+#define mmNIC4_QM1_HBW_RD_RATE_LIM_CFG_0                             0xDE2CA0
+
+#define mmNIC4_QM1_GLBL_AXCACHE                                      0xDE2CA4
+
+#define mmNIC4_QM1_IND_GW_APB_CFG                                    0xDE2CB0
+
+#define mmNIC4_QM1_IND_GW_APB_WDATA                                  0xDE2CB4
+
+#define mmNIC4_QM1_IND_GW_APB_RDATA                                  0xDE2CB8
+
+#define mmNIC4_QM1_IND_GW_APB_STATUS                                 0xDE2CBC
+
+#define mmNIC4_QM1_GLBL_ERR_ADDR_LO                                  0xDE2CD0
+
+#define mmNIC4_QM1_GLBL_ERR_ADDR_HI                                  0xDE2CD4
+
+#define mmNIC4_QM1_GLBL_ERR_WDATA                                    0xDE2CD8
+
+#define mmNIC4_QM1_GLBL_MEM_INIT_BUSY                                0xDE2D00
+
+#endif /* ASIC_REG_NIC4_QM1_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_0_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_0_regs.h
new file mode 100644
index 000000000000..2efa2a54deb4
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_0_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_NIF_RTR_CTRL_0_REGS_H_
+#define ASIC_REG_NIF_RTR_CTRL_0_REGS_H_
+
+/*
+ *****************************************
+ *   NIF_RTR_CTRL_0 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmNIF_RTR_CTRL_0_PERM_SEL                                    0x386108
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_0                               0x386114
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_1                               0x386118
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_2                               0x38611C
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_3                               0x386120
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_4                               0x386124
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_5                               0x386128
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_6                               0x38612C
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_7                               0x386130
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_8                               0x386134
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_9                               0x386138
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_10                              0x38613C
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_11                              0x386140
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_12                              0x386144
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_13                              0x386148
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_14                              0x38614C
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_15                              0x386150
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_16                              0x386154
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_17                              0x386158
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_18                              0x38615C
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_19                              0x386160
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_20                              0x386164
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_21                              0x386168
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_22                              0x38616C
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_23                              0x386170
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_24                              0x386174
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_25                              0x386178
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_26                              0x38617C
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_27                              0x386180
+
+#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_0                              0x386184
+
+#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_1                              0x386188
+
+#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_2                              0x38618C
+
+#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_3                              0x386190
+
+#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_4                              0x386194
+
+#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_5                              0x386198
+
+#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_6                              0x38619C
+
+#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_7                              0x3861A0
+
+#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_8                              0x3861A4
+
+#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_9                              0x3861A8
+
+#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_10                             0x3861AC
+
+#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_11                             0x3861B0
+
+#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_12                             0x3861B4
+
+#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_13                             0x3861B8
+
+#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_14                             0x3861BC
+
+#define mmNIF_RTR_CTRL_0_SCRAM_SRAM_EN                               0x38626C
+
+#define mmNIF_RTR_CTRL_0_RL_HBM_EN                                   0x386274
+
+#define mmNIF_RTR_CTRL_0_RL_HBM_SAT                                  0x386278
+
+#define mmNIF_RTR_CTRL_0_RL_HBM_RST                                  0x38627C
+
+#define mmNIF_RTR_CTRL_0_RL_HBM_TIMEOUT                              0x386280
+
+#define mmNIF_RTR_CTRL_0_SCRAM_HBM_EN                                0x386284
+
+#define mmNIF_RTR_CTRL_0_RL_PCI_EN                                   0x386288
+
+#define mmNIF_RTR_CTRL_0_RL_PCI_SAT                                  0x38628C
+
+#define mmNIF_RTR_CTRL_0_RL_PCI_RST                                  0x386290
+
+#define mmNIF_RTR_CTRL_0_RL_PCI_TIMEOUT                              0x386294
+
+#define mmNIF_RTR_CTRL_0_RL_SRAM_EN                                  0x38629C
+
+#define mmNIF_RTR_CTRL_0_RL_SRAM_SAT                                 0x3862A0
+
+#define mmNIF_RTR_CTRL_0_RL_SRAM_RST                                 0x3862A4
+
+#define mmNIF_RTR_CTRL_0_RL_SRAM_TIMEOUT                             0x3862AC
+
+#define mmNIF_RTR_CTRL_0_RL_SRAM_RED                                 0x3862B4
+
+#define mmNIF_RTR_CTRL_0_E2E_HBM_EN                                  0x3862EC
+
+#define mmNIF_RTR_CTRL_0_E2E_PCI_EN                                  0x3862F0
+
+#define mmNIF_RTR_CTRL_0_E2E_HBM_WR_SIZE                             0x3862F4
+
+#define mmNIF_RTR_CTRL_0_E2E_PCI_WR_SIZE                             0x3862F8
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_PCI_CTR_SET_EN                       0x386404
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_PCI_CTR_SET                          0x386408
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_PCI_CTR_WRAP                         0x38640C
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_PCI_CTR_CNT                          0x386410
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_HBM_CTR_SET_EN                       0x386414
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_HBM_CTR_SET                          0x386418
+
+#define mmNIF_RTR_CTRL_0_E2E_HBM_RD_SIZE                             0x38641C
+
+#define mmNIF_RTR_CTRL_0_E2E_PCI_RD_SIZE                             0x386420
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_PCI_CTR_SET_EN                       0x386424
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_PCI_CTR_SET                          0x386428
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_PCI_CTR_WRAP                         0x38642C
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_PCI_CTR_CNT                          0x386430
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_HBM_CTR_SET_EN                       0x386434
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_HBM_CTR_SET                          0x386438
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_SEL_0                                0x386450
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_SEL_1                                0x386454
+
+#define mmNIF_RTR_CTRL_0_NON_LIN_EN                                  0x386480
+
+#define mmNIF_RTR_CTRL_0_NL_SRAM_BANK_0                              0x386500
+
+#define mmNIF_RTR_CTRL_0_NL_SRAM_BANK_1                              0x386504
+
+#define mmNIF_RTR_CTRL_0_NL_SRAM_BANK_2                              0x386508
+
+#define mmNIF_RTR_CTRL_0_NL_SRAM_BANK_3                              0x38650C
+
+#define mmNIF_RTR_CTRL_0_NL_SRAM_BANK_4                              0x386510
+
+#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_0                            0x386514
+
+#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_1                            0x386520
+
+#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_2                            0x386524
+
+#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_3                            0x386528
+
+#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_4                            0x38652C
+
+#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_5                            0x386530
+
+#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_6                            0x386534
+
+#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_7                            0x386538
+
+#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_8                            0x38653C
+
+#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_9                            0x386540
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_0                             0x386550
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_1                             0x386554
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_2                             0x386558
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_3                             0x38655C
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_4                             0x386560
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_5                             0x386564
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_6                             0x386568
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_7                             0x38656C
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_8                             0x386570
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_9                             0x386574
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_10                            0x386578
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_11                            0x38657C
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_12                            0x386580
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_13                            0x386584
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_14                            0x386588
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_15                            0x38658C
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_16                            0x386590
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_17                            0x386594
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_18                            0x386598
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_0                     0x3865E4
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_1                     0x3865E8
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_2                     0x3865EC
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_3                     0x3865F0
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_4                     0x3865F4
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_5                     0x3865F8
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_6                     0x3865FC
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_7                     0x386600
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_8                     0x386604
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_9                     0x386608
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_10                    0x38660C
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_11                    0x386610
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_12                    0x386614
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_13                    0x386618
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_14                    0x38661C
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_15                    0x386620
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_0                    0x386624
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_1                    0x386628
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_2                    0x38662C
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_3                    0x386630
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_4                    0x386634
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_5                    0x386638
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_6                    0x38663C
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_7                    0x386640
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_8                    0x386644
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_9                    0x386648
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_10                   0x38664C
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_11                   0x386650
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_12                   0x386654
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_13                   0x386658
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_14                   0x38665C
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_15                   0x386660
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_0                     0x386664
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_1                     0x386668
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_2                     0x38666C
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_3                     0x386670
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_4                     0x386674
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_5                     0x386678
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_6                     0x38667C
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_7                     0x386680
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_8                     0x386684
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_9                     0x386688
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_10                    0x38668C
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_11                    0x386690
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_12                    0x386694
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_13                    0x386698
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_14                    0x38669C
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_15                    0x3866A0
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_0                    0x3866A4
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_1                    0x3866A8
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_2                    0x3866AC
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_3                    0x3866B0
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_4                    0x3866B4
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_5                    0x3866B8
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_6                    0x3866BC
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_7                    0x3866C0
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_8                    0x3866C4
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_9                    0x3866C8
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_10                   0x3866CC
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_11                   0x3866D0
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_12                   0x3866D4
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_13                   0x3866D8
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_14                   0x3866DC
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_15                   0x3866E0
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_0                    0x3866E4
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_1                    0x3866E8
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_2                    0x3866EC
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_3                    0x3866F0
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_4                    0x3866F4
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_5                    0x3866F8
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_6                    0x3866FC
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_7                    0x386700
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_8                    0x386704
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_9                    0x386708
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_10                   0x38670C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_11                   0x386710
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_12                   0x386714
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_13                   0x386718
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_14                   0x38671C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_15                   0x386720
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_0                   0x386724
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_1                   0x386728
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_2                   0x38672C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_3                   0x386730
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_4                   0x386734
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_5                   0x386738
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_6                   0x38673C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_7                   0x386740
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_8                   0x386744
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_9                   0x386748
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_10                  0x38674C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_11                  0x386750
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_12                  0x386754
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_13                  0x386758
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_14                  0x38675C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_15                  0x386760
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_0                    0x386764
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_1                    0x386768
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_2                    0x38676C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_3                    0x386770
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_4                    0x386774
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_5                    0x386778
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_6                    0x38677C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_7                    0x386780
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_8                    0x386784
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_9                    0x386788
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_10                   0x38678C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_11                   0x386790
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_12                   0x386794
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_13                   0x386798
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_14                   0x38679C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_15                   0x3867A0
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_0                   0x3867A4
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_1                   0x3867A8
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_2                   0x3867AC
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_3                   0x3867B0
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_4                   0x3867B4
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_5                   0x3867B8
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_6                   0x3867BC
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_7                   0x3867C0
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_8                   0x3867C4
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_9                   0x3867C8
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_10                  0x3867CC
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_11                  0x3867D0
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_12                  0x3867D4
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_13                  0x3867D8
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_14                  0x3867DC
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_15                  0x3867E0
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_0                     0x386824
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_1                     0x386828
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_2                     0x38682C
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_3                     0x386830
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_4                     0x386834
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_5                     0x386838
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_6                     0x38683C
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_7                     0x386840
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_8                     0x386844
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_9                     0x386848
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_10                    0x38684C
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_11                    0x386850
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_12                    0x386854
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_13                    0x386858
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_14                    0x38685C
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_15                    0x386860
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_0                    0x386864
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_1                    0x386868
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_2                    0x38686C
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_3                    0x386870
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_4                    0x386874
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_5                    0x386878
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_6                    0x38687C
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_7                    0x386880
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_8                    0x386884
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_9                    0x386888
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_10                   0x38688C
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_11                   0x386890
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_12                   0x386894
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_13                   0x386898
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_14                   0x38689C
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_15                   0x3868A0
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_0                     0x3868A4
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_1                     0x3868A8
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_2                     0x3868AC
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_3                     0x3868B0
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_4                     0x3868B4
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_5                     0x3868B8
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_6                     0x3868BC
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_7                     0x3868C0
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_8                     0x3868C4
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_9                     0x3868C8
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_10                    0x3868CC
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_11                    0x3868D0
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_12                    0x3868D4
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_13                    0x3868D8
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_14                    0x3868DC
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_15                    0x3868E0
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_0                    0x3868E4
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_1                    0x3868E8
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_2                    0x3868EC
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_3                    0x3868F0
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_4                    0x3868F4
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_5                    0x3868F8
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_6                    0x3868FC
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_7                    0x386900
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_8                    0x386904
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_9                    0x386908
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_10                   0x38690C
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_11                   0x386910
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_12                   0x386914
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_13                   0x386918
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_14                   0x38691C
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_15                   0x386920
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_0                    0x386924
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_1                    0x386928
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_2                    0x38692C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_3                    0x386930
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_4                    0x386934
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_5                    0x386938
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_6                    0x38693C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_7                    0x386940
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_8                    0x386944
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_9                    0x386948
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_10                   0x38694C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_11                   0x386950
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_12                   0x386954
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_13                   0x386958
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_14                   0x38695C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_15                   0x386960
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_0                   0x386964
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_1                   0x386968
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_2                   0x38696C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_3                   0x386970
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_4                   0x386974
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_5                   0x386978
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_6                   0x38697C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_7                   0x386980
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_8                   0x386984
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_9                   0x386988
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_10                  0x38698C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_11                  0x386990
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_12                  0x386994
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_13                  0x386998
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_14                  0x38699C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_15                  0x3869A0
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_0                    0x3869A4
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_1                    0x3869A8
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_2                    0x3869AC
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_3                    0x3869B0
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_4                    0x3869B4
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_5                    0x3869B8
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_6                    0x3869BC
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_7                    0x3869C0
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_8                    0x3869C4
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_9                    0x3869C8
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_10                   0x3869CC
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_11                   0x3869D0
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_12                   0x3869D4
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_13                   0x3869D8
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_14                   0x3869DC
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_15                   0x3869E0
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_0                   0x3869E4
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_1                   0x3869E8
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_2                   0x3869EC
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_3                   0x3869F0
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_4                   0x3869F4
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_5                   0x3869F8
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_6                   0x3869FC
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_7                   0x386A00
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_8                   0x386A04
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_9                   0x386A08
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_10                  0x386A0C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_11                  0x386A10
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_12                  0x386A14
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_13                  0x386A18
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_14                  0x386A1C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_15                  0x386A20
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_HIT_AW                            0x386A64
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_HIT_AR                            0x386A68
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_HIT_AW                           0x386A6C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_HIT_AR                           0x386A70
+
+#define mmNIF_RTR_CTRL_0_RGL_CFG                                     0x386B64
+
+#define mmNIF_RTR_CTRL_0_RGL_SHIFT                                   0x386B68
+
+#define mmNIF_RTR_CTRL_0_RGL_EXPECTED_LAT_0                          0x386B6C
+
+#define mmNIF_RTR_CTRL_0_RGL_EXPECTED_LAT_1                          0x386B70
+
+#define mmNIF_RTR_CTRL_0_RGL_EXPECTED_LAT_2                          0x386B74
+
+#define mmNIF_RTR_CTRL_0_RGL_EXPECTED_LAT_3                          0x386B78
+
+#define mmNIF_RTR_CTRL_0_RGL_EXPECTED_LAT_4                          0x386B7C
+
+#define mmNIF_RTR_CTRL_0_RGL_EXPECTED_LAT_5                          0x386B80
+
+#define mmNIF_RTR_CTRL_0_RGL_EXPECTED_LAT_6                          0x386B84
+
+#define mmNIF_RTR_CTRL_0_RGL_EXPECTED_LAT_7                          0x386B88
+
+#define mmNIF_RTR_CTRL_0_RGL_TOKEN_0                                 0x386BAC
+
+#define mmNIF_RTR_CTRL_0_RGL_TOKEN_1                                 0x386BB0
+
+#define mmNIF_RTR_CTRL_0_RGL_TOKEN_2                                 0x386BB4
+
+#define mmNIF_RTR_CTRL_0_RGL_TOKEN_3                                 0x386BB8
+
+#define mmNIF_RTR_CTRL_0_RGL_TOKEN_4                                 0x386BBC
+
+#define mmNIF_RTR_CTRL_0_RGL_TOKEN_5                                 0x386BC0
+
+#define mmNIF_RTR_CTRL_0_RGL_TOKEN_6                                 0x386BC4
+
+#define mmNIF_RTR_CTRL_0_RGL_TOKEN_7                                 0x386BC8
+
+#define mmNIF_RTR_CTRL_0_RGL_BANK_ID_0                               0x386BEC
+
+#define mmNIF_RTR_CTRL_0_RGL_BANK_ID_1                               0x386BF0
+
+#define mmNIF_RTR_CTRL_0_RGL_BANK_ID_2                               0x386BF4
+
+#define mmNIF_RTR_CTRL_0_RGL_BANK_ID_3                               0x386BF8
+
+#define mmNIF_RTR_CTRL_0_RGL_BANK_ID_4                               0x386BFC
+
+#define mmNIF_RTR_CTRL_0_RGL_BANK_ID_5                               0x386C00
+
+#define mmNIF_RTR_CTRL_0_RGL_BANK_ID_6                               0x386C04
+
+#define mmNIF_RTR_CTRL_0_RGL_BANK_ID_7                               0x386C08
+
+#define mmNIF_RTR_CTRL_0_RGL_WDT                                     0x386C2C
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_HBM0_CH0_CTR_WRAP                    0x386C30
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_HBM0_CH1_CTR_WRAP                    0x386C34
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_HBM1_CH0_CTR_WRAP                    0x386C38
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_HBM1_CH1_CTR_WRAP                    0x386C3C
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_HBM2_CH0_CTR_WRAP                    0x386C40
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_HBM2_CH1_CTR_WRAP                    0x386C44
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_HBM3_CH0_CTR_WRAP                    0x386C48
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_HBM3_CH1_CTR_WRAP                    0x386C4C
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_HBM0_CH0_CTR_CNT                     0x386C50
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_HBM0_CH1_CTR_CNT                     0x386C54
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_HBM1_CH0_CTR_CNT                     0x386C58
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_HBM1_CH1_CTR_CNT                     0x386C5C
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_HBM2_CH0_CTR_CNT                     0x386C60
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_HBM2_CH1_CTR_CNT                     0x386C64
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_HBM3_CH0_CTR_CNT                     0x386C68
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_HBM3_CH1_CTR_CNT                     0x386C6C
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_HBM0_CH0_CTR_WRAP                    0x386C70
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_HBM0_CH1_CTR_WRAP                    0x386C74
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_HBM1_CH0_CTR_WRAP                    0x386C78
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_HBM1_CH1_CTR_WRAP                    0x386C7C
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_HBM2_CH0_CTR_WRAP                    0x386C80
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_HBM2_CH1_CTR_WRAP                    0x386C84
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_HBM3_CH0_CTR_WRAP                    0x386C88
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_HBM3_CH1_CTR_WRAP                    0x386C8C
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_HBM0_CH0_CTR_CNT                     0x386C90
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_HBM0_CH1_CTR_CNT                     0x386C94
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_HBM1_CH0_CTR_CNT                     0x386C98
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_HBM1_CH1_CTR_CNT                     0x386C9C
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_HBM2_CH0_CTR_CNT                     0x386CA0
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_HBM2_CH1_CTR_CNT                     0x386CA4
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_HBM3_CH0_CTR_CNT                     0x386CA8
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_HBM3_CH1_CTR_CNT                     0x386CAC
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_PC_SEL_0                             0x386CB0
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_PC_SEL_1                             0x386CB4
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_PC_SEL_2                             0x386CB8
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_PC_SEL_3                             0x386CBC
+
+#endif /* ASIC_REG_NIF_RTR_CTRL_0_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_1_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_1_regs.h
new file mode 100644
index 000000000000..a6047d4e2560
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_1_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_NIF_RTR_CTRL_1_REGS_H_
+#define ASIC_REG_NIF_RTR_CTRL_1_REGS_H_
+
+/*
+ *****************************************
+ *   NIF_RTR_CTRL_1 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmNIF_RTR_CTRL_1_PERM_SEL                                    0x396108
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_0                               0x396114
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_1                               0x396118
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_2                               0x39611C
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_3                               0x396120
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_4                               0x396124
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_5                               0x396128
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_6                               0x39612C
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_7                               0x396130
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_8                               0x396134
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_9                               0x396138
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_10                              0x39613C
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_11                              0x396140
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_12                              0x396144
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_13                              0x396148
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_14                              0x39614C
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_15                              0x396150
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_16                              0x396154
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_17                              0x396158
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_18                              0x39615C
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_19                              0x396160
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_20                              0x396164
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_21                              0x396168
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_22                              0x39616C
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_23                              0x396170
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_24                              0x396174
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_25                              0x396178
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_26                              0x39617C
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_27                              0x396180
+
+#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_0                              0x396184
+
+#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_1                              0x396188
+
+#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_2                              0x39618C
+
+#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_3                              0x396190
+
+#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_4                              0x396194
+
+#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_5                              0x396198
+
+#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_6                              0x39619C
+
+#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_7                              0x3961A0
+
+#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_8                              0x3961A4
+
+#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_9                              0x3961A8
+
+#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_10                             0x3961AC
+
+#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_11                             0x3961B0
+
+#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_12                             0x3961B4
+
+#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_13                             0x3961B8
+
+#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_14                             0x3961BC
+
+#define mmNIF_RTR_CTRL_1_SCRAM_SRAM_EN                               0x39626C
+
+#define mmNIF_RTR_CTRL_1_RL_HBM_EN                                   0x396274
+
+#define mmNIF_RTR_CTRL_1_RL_HBM_SAT                                  0x396278
+
+#define mmNIF_RTR_CTRL_1_RL_HBM_RST                                  0x39627C
+
+#define mmNIF_RTR_CTRL_1_RL_HBM_TIMEOUT                              0x396280
+
+#define mmNIF_RTR_CTRL_1_SCRAM_HBM_EN                                0x396284
+
+#define mmNIF_RTR_CTRL_1_RL_PCI_EN                                   0x396288
+
+#define mmNIF_RTR_CTRL_1_RL_PCI_SAT                                  0x39628C
+
+#define mmNIF_RTR_CTRL_1_RL_PCI_RST                                  0x396290
+
+#define mmNIF_RTR_CTRL_1_RL_PCI_TIMEOUT                              0x396294
+
+#define mmNIF_RTR_CTRL_1_RL_SRAM_EN                                  0x39629C
+
+#define mmNIF_RTR_CTRL_1_RL_SRAM_SAT                                 0x3962A0
+
+#define mmNIF_RTR_CTRL_1_RL_SRAM_RST                                 0x3962A4
+
+#define mmNIF_RTR_CTRL_1_RL_SRAM_TIMEOUT                             0x3962AC
+
+#define mmNIF_RTR_CTRL_1_RL_SRAM_RED                                 0x3962B4
+
+#define mmNIF_RTR_CTRL_1_E2E_HBM_EN                                  0x3962EC
+
+#define mmNIF_RTR_CTRL_1_E2E_PCI_EN                                  0x3962F0
+
+#define mmNIF_RTR_CTRL_1_E2E_HBM_WR_SIZE                             0x3962F4
+
+#define mmNIF_RTR_CTRL_1_E2E_PCI_WR_SIZE                             0x3962F8
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_PCI_CTR_SET_EN                       0x396404
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_PCI_CTR_SET                          0x396408
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_PCI_CTR_WRAP                         0x39640C
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_PCI_CTR_CNT                          0x396410
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_HBM_CTR_SET_EN                       0x396414
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_HBM_CTR_SET                          0x396418
+
+#define mmNIF_RTR_CTRL_1_E2E_HBM_RD_SIZE                             0x39641C
+
+#define mmNIF_RTR_CTRL_1_E2E_PCI_RD_SIZE                             0x396420
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_PCI_CTR_SET_EN                       0x396424
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_PCI_CTR_SET                          0x396428
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_PCI_CTR_WRAP                         0x39642C
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_PCI_CTR_CNT                          0x396430
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_HBM_CTR_SET_EN                       0x396434
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_HBM_CTR_SET                          0x396438
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_SEL_0                                0x396450
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_SEL_1                                0x396454
+
+#define mmNIF_RTR_CTRL_1_NON_LIN_EN                                  0x396480
+
+#define mmNIF_RTR_CTRL_1_NL_SRAM_BANK_0                              0x396500
+
+#define mmNIF_RTR_CTRL_1_NL_SRAM_BANK_1                              0x396504
+
+#define mmNIF_RTR_CTRL_1_NL_SRAM_BANK_2                              0x396508
+
+#define mmNIF_RTR_CTRL_1_NL_SRAM_BANK_3                              0x39650C
+
+#define mmNIF_RTR_CTRL_1_NL_SRAM_BANK_4                              0x396510
+
+#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_0                            0x396514
+
+#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_1                            0x396520
+
+#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_2                            0x396524
+
+#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_3                            0x396528
+
+#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_4                            0x39652C
+
+#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_5                            0x396530
+
+#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_6                            0x396534
+
+#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_7                            0x396538
+
+#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_8                            0x39653C
+
+#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_9                            0x396540
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_0                             0x396550
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_1                             0x396554
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_2                             0x396558
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_3                             0x39655C
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_4                             0x396560
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_5                             0x396564
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_6                             0x396568
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_7                             0x39656C
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_8                             0x396570
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_9                             0x396574
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_10                            0x396578
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_11                            0x39657C
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_12                            0x396580
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_13                            0x396584
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_14                            0x396588
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_15                            0x39658C
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_16                            0x396590
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_17                            0x396594
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_18                            0x396598
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_0                     0x3965E4
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_1                     0x3965E8
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_2                     0x3965EC
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_3                     0x3965F0
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_4                     0x3965F4
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_5                     0x3965F8
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_6                     0x3965FC
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_7                     0x396600
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_8                     0x396604
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_9                     0x396608
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_10                    0x39660C
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_11                    0x396610
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_12                    0x396614
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_13                    0x396618
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_14                    0x39661C
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_15                    0x396620
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_0                    0x396624
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_1                    0x396628
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_2                    0x39662C
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_3                    0x396630
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_4                    0x396634
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_5                    0x396638
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_6                    0x39663C
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_7                    0x396640
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_8                    0x396644
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_9                    0x396648
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_10                   0x39664C
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_11                   0x396650
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_12                   0x396654
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_13                   0x396658
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_14                   0x39665C
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_15                   0x396660
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_0                     0x396664
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_1                     0x396668
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_2                     0x39666C
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_3                     0x396670
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_4                     0x396674
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_5                     0x396678
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_6                     0x39667C
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_7                     0x396680
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_8                     0x396684
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_9                     0x396688
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_10                    0x39668C
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_11                    0x396690
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_12                    0x396694
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_13                    0x396698
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_14                    0x39669C
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_15                    0x3966A0
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_0                    0x3966A4
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_1                    0x3966A8
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_2                    0x3966AC
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_3                    0x3966B0
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_4                    0x3966B4
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_5                    0x3966B8
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_6                    0x3966BC
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_7                    0x3966C0
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_8                    0x3966C4
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_9                    0x3966C8
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_10                   0x3966CC
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_11                   0x3966D0
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_12                   0x3966D4
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_13                   0x3966D8
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_14                   0x3966DC
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_15                   0x3966E0
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_0                    0x3966E4
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_1                    0x3966E8
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_2                    0x3966EC
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_3                    0x3966F0
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_4                    0x3966F4
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_5                    0x3966F8
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_6                    0x3966FC
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_7                    0x396700
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_8                    0x396704
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_9                    0x396708
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_10                   0x39670C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_11                   0x396710
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_12                   0x396714
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_13                   0x396718
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_14                   0x39671C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_15                   0x396720
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_0                   0x396724
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_1                   0x396728
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_2                   0x39672C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_3                   0x396730
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_4                   0x396734
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_5                   0x396738
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_6                   0x39673C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_7                   0x396740
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_8                   0x396744
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_9                   0x396748
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_10                  0x39674C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_11                  0x396750
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_12                  0x396754
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_13                  0x396758
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_14                  0x39675C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_15                  0x396760
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_0                    0x396764
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_1                    0x396768
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_2                    0x39676C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_3                    0x396770
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_4                    0x396774
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_5                    0x396778
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_6                    0x39677C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_7                    0x396780
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_8                    0x396784
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_9                    0x396788
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_10                   0x39678C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_11                   0x396790
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_12                   0x396794
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_13                   0x396798
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_14                   0x39679C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_15                   0x3967A0
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_0                   0x3967A4
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_1                   0x3967A8
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_2                   0x3967AC
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_3                   0x3967B0
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_4                   0x3967B4
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_5                   0x3967B8
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_6                   0x3967BC
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_7                   0x3967C0
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_8                   0x3967C4
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_9                   0x3967C8
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_10                  0x3967CC
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_11                  0x3967D0
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_12                  0x3967D4
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_13                  0x3967D8
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_14                  0x3967DC
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_15                  0x3967E0
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_0                     0x396824
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_1                     0x396828
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_2                     0x39682C
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_3                     0x396830
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_4                     0x396834
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_5                     0x396838
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_6                     0x39683C
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_7                     0x396840
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_8                     0x396844
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_9                     0x396848
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_10                    0x39684C
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_11                    0x396850
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_12                    0x396854
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_13                    0x396858
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_14                    0x39685C
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_15                    0x396860
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_0                    0x396864
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_1                    0x396868
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_2                    0x39686C
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_3                    0x396870
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_4                    0x396874
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_5                    0x396878
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_6                    0x39687C
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_7                    0x396880
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_8                    0x396884
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_9                    0x396888
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_10                   0x39688C
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_11                   0x396890
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_12                   0x396894
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_13                   0x396898
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_14                   0x39689C
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_15                   0x3968A0
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_0                     0x3968A4
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_1                     0x3968A8
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_2                     0x3968AC
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_3                     0x3968B0
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_4                     0x3968B4
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_5                     0x3968B8
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_6                     0x3968BC
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_7                     0x3968C0
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_8                     0x3968C4
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_9                     0x3968C8
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_10                    0x3968CC
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_11                    0x3968D0
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_12                    0x3968D4
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_13                    0x3968D8
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_14                    0x3968DC
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_15                    0x3968E0
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_0                    0x3968E4
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_1                    0x3968E8
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_2                    0x3968EC
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_3                    0x3968F0
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_4                    0x3968F4
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_5                    0x3968F8
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_6                    0x3968FC
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_7                    0x396900
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_8                    0x396904
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_9                    0x396908
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_10                   0x39690C
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_11                   0x396910
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_12                   0x396914
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_13                   0x396918
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_14                   0x39691C
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_15                   0x396920
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_0                    0x396924
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_1                    0x396928
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_2                    0x39692C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_3                    0x396930
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_4                    0x396934
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_5                    0x396938
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_6                    0x39693C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_7                    0x396940
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_8                    0x396944
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_9                    0x396948
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_10                   0x39694C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_11                   0x396950
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_12                   0x396954
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_13                   0x396958
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_14                   0x39695C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_15                   0x396960
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_0                   0x396964
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_1                   0x396968
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_2                   0x39696C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_3                   0x396970
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_4                   0x396974
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_5                   0x396978
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_6                   0x39697C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_7                   0x396980
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_8                   0x396984
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_9                   0x396988
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_10                  0x39698C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_11                  0x396990
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_12                  0x396994
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_13                  0x396998
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_14                  0x39699C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_15                  0x3969A0
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_0                    0x3969A4
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_1                    0x3969A8
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_2                    0x3969AC
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_3                    0x3969B0
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_4                    0x3969B4
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_5                    0x3969B8
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_6                    0x3969BC
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_7                    0x3969C0
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_8                    0x3969C4
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_9                    0x3969C8
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_10                   0x3969CC
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_11                   0x3969D0
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_12                   0x3969D4
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_13                   0x3969D8
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_14                   0x3969DC
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_15                   0x3969E0
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_0                   0x3969E4
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_1                   0x3969E8
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_2                   0x3969EC
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_3                   0x3969F0
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_4                   0x3969F4
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_5                   0x3969F8
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_6                   0x3969FC
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_7                   0x396A00
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_8                   0x396A04
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_9                   0x396A08
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_10                  0x396A0C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_11                  0x396A10
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_12                  0x396A14
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_13                  0x396A18
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_14                  0x396A1C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_15                  0x396A20
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_HIT_AW                            0x396A64
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_HIT_AR                            0x396A68
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_HIT_AW                           0x396A6C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_HIT_AR                           0x396A70
+
+#define mmNIF_RTR_CTRL_1_RGL_CFG                                     0x396B64
+
+#define mmNIF_RTR_CTRL_1_RGL_SHIFT                                   0x396B68
+
+#define mmNIF_RTR_CTRL_1_RGL_EXPECTED_LAT_0                          0x396B6C
+
+#define mmNIF_RTR_CTRL_1_RGL_EXPECTED_LAT_1                          0x396B70
+
+#define mmNIF_RTR_CTRL_1_RGL_EXPECTED_LAT_2                          0x396B74
+
+#define mmNIF_RTR_CTRL_1_RGL_EXPECTED_LAT_3                          0x396B78
+
+#define mmNIF_RTR_CTRL_1_RGL_EXPECTED_LAT_4                          0x396B7C
+
+#define mmNIF_RTR_CTRL_1_RGL_EXPECTED_LAT_5                          0x396B80
+
+#define mmNIF_RTR_CTRL_1_RGL_EXPECTED_LAT_6                          0x396B84
+
+#define mmNIF_RTR_CTRL_1_RGL_EXPECTED_LAT_7                          0x396B88
+
+#define mmNIF_RTR_CTRL_1_RGL_TOKEN_0                                 0x396BAC
+
+#define mmNIF_RTR_CTRL_1_RGL_TOKEN_1                                 0x396BB0
+
+#define mmNIF_RTR_CTRL_1_RGL_TOKEN_2                                 0x396BB4
+
+#define mmNIF_RTR_CTRL_1_RGL_TOKEN_3                                 0x396BB8
+
+#define mmNIF_RTR_CTRL_1_RGL_TOKEN_4                                 0x396BBC
+
+#define mmNIF_RTR_CTRL_1_RGL_TOKEN_5                                 0x396BC0
+
+#define mmNIF_RTR_CTRL_1_RGL_TOKEN_6                                 0x396BC4
+
+#define mmNIF_RTR_CTRL_1_RGL_TOKEN_7                                 0x396BC8
+
+#define mmNIF_RTR_CTRL_1_RGL_BANK_ID_0                               0x396BEC
+
+#define mmNIF_RTR_CTRL_1_RGL_BANK_ID_1                               0x396BF0
+
+#define mmNIF_RTR_CTRL_1_RGL_BANK_ID_2                               0x396BF4
+
+#define mmNIF_RTR_CTRL_1_RGL_BANK_ID_3                               0x396BF8
+
+#define mmNIF_RTR_CTRL_1_RGL_BANK_ID_4                               0x396BFC
+
+#define mmNIF_RTR_CTRL_1_RGL_BANK_ID_5                               0x396C00
+
+#define mmNIF_RTR_CTRL_1_RGL_BANK_ID_6                               0x396C04
+
+#define mmNIF_RTR_CTRL_1_RGL_BANK_ID_7                               0x396C08
+
+#define mmNIF_RTR_CTRL_1_RGL_WDT                                     0x396C2C
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_HBM0_CH0_CTR_WRAP                    0x396C30
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_HBM0_CH1_CTR_WRAP                    0x396C34
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_HBM1_CH0_CTR_WRAP                    0x396C38
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_HBM1_CH1_CTR_WRAP                    0x396C3C
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_HBM2_CH0_CTR_WRAP                    0x396C40
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_HBM2_CH1_CTR_WRAP                    0x396C44
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_HBM3_CH0_CTR_WRAP                    0x396C48
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_HBM3_CH1_CTR_WRAP                    0x396C4C
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_HBM0_CH0_CTR_CNT                     0x396C50
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_HBM0_CH1_CTR_CNT                     0x396C54
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_HBM1_CH0_CTR_CNT                     0x396C58
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_HBM1_CH1_CTR_CNT                     0x396C5C
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_HBM2_CH0_CTR_CNT                     0x396C60
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_HBM2_CH1_CTR_CNT                     0x396C64
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_HBM3_CH0_CTR_CNT                     0x396C68
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_HBM3_CH1_CTR_CNT                     0x396C6C
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_HBM0_CH0_CTR_WRAP                    0x396C70
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_HBM0_CH1_CTR_WRAP                    0x396C74
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_HBM1_CH0_CTR_WRAP                    0x396C78
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_HBM1_CH1_CTR_WRAP                    0x396C7C
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_HBM2_CH0_CTR_WRAP                    0x396C80
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_HBM2_CH1_CTR_WRAP                    0x396C84
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_HBM3_CH0_CTR_WRAP                    0x396C88
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_HBM3_CH1_CTR_WRAP                    0x396C8C
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_HBM0_CH0_CTR_CNT                     0x396C90
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_HBM0_CH1_CTR_CNT                     0x396C94
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_HBM1_CH0_CTR_CNT                     0x396C98
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_HBM1_CH1_CTR_CNT                     0x396C9C
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_HBM2_CH0_CTR_CNT                     0x396CA0
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_HBM2_CH1_CTR_CNT                     0x396CA4
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_HBM3_CH0_CTR_CNT                     0x396CA8
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_HBM3_CH1_CTR_CNT                     0x396CAC
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_PC_SEL_0                             0x396CB0
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_PC_SEL_1                             0x396CB4
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_PC_SEL_2                             0x396CB8
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_PC_SEL_3                             0x396CBC
+
+#endif /* ASIC_REG_NIF_RTR_CTRL_1_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_2_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_2_regs.h
new file mode 100644
index 000000000000..9de8442f9bc2
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_2_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_NIF_RTR_CTRL_2_REGS_H_
+#define ASIC_REG_NIF_RTR_CTRL_2_REGS_H_
+
+/*
+ *****************************************
+ *   NIF_RTR_CTRL_2 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmNIF_RTR_CTRL_2_PERM_SEL                                    0x3A6108
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_0                               0x3A6114
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_1                               0x3A6118
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_2                               0x3A611C
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_3                               0x3A6120
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_4                               0x3A6124
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_5                               0x3A6128
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_6                               0x3A612C
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_7                               0x3A6130
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_8                               0x3A6134
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_9                               0x3A6138
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_10                              0x3A613C
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_11                              0x3A6140
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_12                              0x3A6144
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_13                              0x3A6148
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_14                              0x3A614C
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_15                              0x3A6150
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_16                              0x3A6154
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_17                              0x3A6158
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_18                              0x3A615C
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_19                              0x3A6160
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_20                              0x3A6164
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_21                              0x3A6168
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_22                              0x3A616C
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_23                              0x3A6170
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_24                              0x3A6174
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_25                              0x3A6178
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_26                              0x3A617C
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_27                              0x3A6180
+
+#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_0                              0x3A6184
+
+#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_1                              0x3A6188
+
+#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_2                              0x3A618C
+
+#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_3                              0x3A6190
+
+#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_4                              0x3A6194
+
+#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_5                              0x3A6198
+
+#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_6                              0x3A619C
+
+#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_7                              0x3A61A0
+
+#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_8                              0x3A61A4
+
+#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_9                              0x3A61A8
+
+#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_10                             0x3A61AC
+
+#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_11                             0x3A61B0
+
+#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_12                             0x3A61B4
+
+#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_13                             0x3A61B8
+
+#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_14                             0x3A61BC
+
+#define mmNIF_RTR_CTRL_2_SCRAM_SRAM_EN                               0x3A626C
+
+#define mmNIF_RTR_CTRL_2_RL_HBM_EN                                   0x3A6274
+
+#define mmNIF_RTR_CTRL_2_RL_HBM_SAT                                  0x3A6278
+
+#define mmNIF_RTR_CTRL_2_RL_HBM_RST                                  0x3A627C
+
+#define mmNIF_RTR_CTRL_2_RL_HBM_TIMEOUT                              0x3A6280
+
+#define mmNIF_RTR_CTRL_2_SCRAM_HBM_EN                                0x3A6284
+
+#define mmNIF_RTR_CTRL_2_RL_PCI_EN                                   0x3A6288
+
+#define mmNIF_RTR_CTRL_2_RL_PCI_SAT                                  0x3A628C
+
+#define mmNIF_RTR_CTRL_2_RL_PCI_RST                                  0x3A6290
+
+#define mmNIF_RTR_CTRL_2_RL_PCI_TIMEOUT                              0x3A6294
+
+#define mmNIF_RTR_CTRL_2_RL_SRAM_EN                                  0x3A629C
+
+#define mmNIF_RTR_CTRL_2_RL_SRAM_SAT                                 0x3A62A0
+
+#define mmNIF_RTR_CTRL_2_RL_SRAM_RST                                 0x3A62A4
+
+#define mmNIF_RTR_CTRL_2_RL_SRAM_TIMEOUT                             0x3A62AC
+
+#define mmNIF_RTR_CTRL_2_RL_SRAM_RED                                 0x3A62B4
+
+#define mmNIF_RTR_CTRL_2_E2E_HBM_EN                                  0x3A62EC
+
+#define mmNIF_RTR_CTRL_2_E2E_PCI_EN                                  0x3A62F0
+
+#define mmNIF_RTR_CTRL_2_E2E_HBM_WR_SIZE                             0x3A62F4
+
+#define mmNIF_RTR_CTRL_2_E2E_PCI_WR_SIZE                             0x3A62F8
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_PCI_CTR_SET_EN                       0x3A6404
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_PCI_CTR_SET                          0x3A6408
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_PCI_CTR_WRAP                         0x3A640C
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_PCI_CTR_CNT                          0x3A6410
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_HBM_CTR_SET_EN                       0x3A6414
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_HBM_CTR_SET                          0x3A6418
+
+#define mmNIF_RTR_CTRL_2_E2E_HBM_RD_SIZE                             0x3A641C
+
+#define mmNIF_RTR_CTRL_2_E2E_PCI_RD_SIZE                             0x3A6420
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_PCI_CTR_SET_EN                       0x3A6424
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_PCI_CTR_SET                          0x3A6428
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_PCI_CTR_WRAP                         0x3A642C
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_PCI_CTR_CNT                          0x3A6430
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_HBM_CTR_SET_EN                       0x3A6434
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_HBM_CTR_SET                          0x3A6438
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_SEL_0                                0x3A6450
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_SEL_1                                0x3A6454
+
+#define mmNIF_RTR_CTRL_2_NON_LIN_EN                                  0x3A6480
+
+#define mmNIF_RTR_CTRL_2_NL_SRAM_BANK_0                              0x3A6500
+
+#define mmNIF_RTR_CTRL_2_NL_SRAM_BANK_1                              0x3A6504
+
+#define mmNIF_RTR_CTRL_2_NL_SRAM_BANK_2                              0x3A6508
+
+#define mmNIF_RTR_CTRL_2_NL_SRAM_BANK_3                              0x3A650C
+
+#define mmNIF_RTR_CTRL_2_NL_SRAM_BANK_4                              0x3A6510
+
+#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_0                            0x3A6514
+
+#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_1                            0x3A6520
+
+#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_2                            0x3A6524
+
+#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_3                            0x3A6528
+
+#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_4                            0x3A652C
+
+#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_5                            0x3A6530
+
+#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_6                            0x3A6534
+
+#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_7                            0x3A6538
+
+#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_8                            0x3A653C
+
+#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_9                            0x3A6540
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_0                             0x3A6550
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_1                             0x3A6554
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_2                             0x3A6558
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_3                             0x3A655C
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_4                             0x3A6560
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_5                             0x3A6564
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_6                             0x3A6568
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_7                             0x3A656C
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_8                             0x3A6570
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_9                             0x3A6574
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_10                            0x3A6578
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_11                            0x3A657C
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_12                            0x3A6580
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_13                            0x3A6584
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_14                            0x3A6588
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_15                            0x3A658C
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_16                            0x3A6590
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_17                            0x3A6594
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_18                            0x3A6598
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_0                     0x3A65E4
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_1                     0x3A65E8
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_2                     0x3A65EC
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_3                     0x3A65F0
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_4                     0x3A65F4
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_5                     0x3A65F8
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_6                     0x3A65FC
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_7                     0x3A6600
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_8                     0x3A6604
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_9                     0x3A6608
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_10                    0x3A660C
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_11                    0x3A6610
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_12                    0x3A6614
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_13                    0x3A6618
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_14                    0x3A661C
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_15                    0x3A6620
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_0                    0x3A6624
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_1                    0x3A6628
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_2                    0x3A662C
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_3                    0x3A6630
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_4                    0x3A6634
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_5                    0x3A6638
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_6                    0x3A663C
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_7                    0x3A6640
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_8                    0x3A6644
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_9                    0x3A6648
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_10                   0x3A664C
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_11                   0x3A6650
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_12                   0x3A6654
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_13                   0x3A6658
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_14                   0x3A665C
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_15                   0x3A6660
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_0                     0x3A6664
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_1                     0x3A6668
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_2                     0x3A666C
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_3                     0x3A6670
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_4                     0x3A6674
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_5                     0x3A6678
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_6                     0x3A667C
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_7                     0x3A6680
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_8                     0x3A6684
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_9                     0x3A6688
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_10                    0x3A668C
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_11                    0x3A6690
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_12                    0x3A6694
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_13                    0x3A6698
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_14                    0x3A669C
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_15                    0x3A66A0
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_0                    0x3A66A4
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_1                    0x3A66A8
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_2                    0x3A66AC
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_3                    0x3A66B0
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_4                    0x3A66B4
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_5                    0x3A66B8
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_6                    0x3A66BC
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_7                    0x3A66C0
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_8                    0x3A66C4
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_9                    0x3A66C8
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_10                   0x3A66CC
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_11                   0x3A66D0
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_12                   0x3A66D4
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_13                   0x3A66D8
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_14                   0x3A66DC
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_15                   0x3A66E0
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_0                    0x3A66E4
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_1                    0x3A66E8
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_2                    0x3A66EC
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_3                    0x3A66F0
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_4                    0x3A66F4
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_5                    0x3A66F8
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_6                    0x3A66FC
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_7                    0x3A6700
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_8                    0x3A6704
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_9                    0x3A6708
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_10                   0x3A670C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_11                   0x3A6710
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_12                   0x3A6714
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_13                   0x3A6718
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_14                   0x3A671C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_15                   0x3A6720
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_0                   0x3A6724
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_1                   0x3A6728
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_2                   0x3A672C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_3                   0x3A6730
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_4                   0x3A6734
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_5                   0x3A6738
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_6                   0x3A673C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_7                   0x3A6740
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_8                   0x3A6744
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_9                   0x3A6748
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_10                  0x3A674C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_11                  0x3A6750
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_12                  0x3A6754
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_13                  0x3A6758
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_14                  0x3A675C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_15                  0x3A6760
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_0                    0x3A6764
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_1                    0x3A6768
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_2                    0x3A676C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_3                    0x3A6770
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_4                    0x3A6774
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_5                    0x3A6778
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_6                    0x3A677C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_7                    0x3A6780
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_8                    0x3A6784
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_9                    0x3A6788
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_10                   0x3A678C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_11                   0x3A6790
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_12                   0x3A6794
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_13                   0x3A6798
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_14                   0x3A679C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_15                   0x3A67A0
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_0                   0x3A67A4
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_1                   0x3A67A8
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_2                   0x3A67AC
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_3                   0x3A67B0
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_4                   0x3A67B4
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_5                   0x3A67B8
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_6                   0x3A67BC
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_7                   0x3A67C0
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_8                   0x3A67C4
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_9                   0x3A67C8
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_10                  0x3A67CC
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_11                  0x3A67D0
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_12                  0x3A67D4
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_13                  0x3A67D8
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_14                  0x3A67DC
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_15                  0x3A67E0
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_0                     0x3A6824
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_1                     0x3A6828
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_2                     0x3A682C
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_3                     0x3A6830
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_4                     0x3A6834
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_5                     0x3A6838
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_6                     0x3A683C
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_7                     0x3A6840
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_8                     0x3A6844
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_9                     0x3A6848
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_10                    0x3A684C
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_11                    0x3A6850
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_12                    0x3A6854
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_13                    0x3A6858
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_14                    0x3A685C
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_15                    0x3A6860
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_0                    0x3A6864
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_1                    0x3A6868
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_2                    0x3A686C
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_3                    0x3A6870
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_4                    0x3A6874
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_5                    0x3A6878
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_6                    0x3A687C
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_7                    0x3A6880
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_8                    0x3A6884
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_9                    0x3A6888
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_10                   0x3A688C
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_11                   0x3A6890
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_12                   0x3A6894
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_13                   0x3A6898
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_14                   0x3A689C
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_15                   0x3A68A0
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_0                     0x3A68A4
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_1                     0x3A68A8
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_2                     0x3A68AC
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_3                     0x3A68B0
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_4                     0x3A68B4
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_5                     0x3A68B8
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_6                     0x3A68BC
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_7                     0x3A68C0
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_8                     0x3A68C4
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_9                     0x3A68C8
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_10                    0x3A68CC
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_11                    0x3A68D0
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_12                    0x3A68D4
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_13                    0x3A68D8
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_14                    0x3A68DC
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_15                    0x3A68E0
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_0                    0x3A68E4
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_1                    0x3A68E8
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_2                    0x3A68EC
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_3                    0x3A68F0
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_4                    0x3A68F4
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_5                    0x3A68F8
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_6                    0x3A68FC
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_7                    0x3A6900
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_8                    0x3A6904
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_9                    0x3A6908
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_10                   0x3A690C
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_11                   0x3A6910
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_12                   0x3A6914
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_13                   0x3A6918
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_14                   0x3A691C
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_15                   0x3A6920
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_0                    0x3A6924
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_1                    0x3A6928
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_2                    0x3A692C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_3                    0x3A6930
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_4                    0x3A6934
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_5                    0x3A6938
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_6                    0x3A693C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_7                    0x3A6940
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_8                    0x3A6944
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_9                    0x3A6948
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_10                   0x3A694C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_11                   0x3A6950
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_12                   0x3A6954
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_13                   0x3A6958
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_14                   0x3A695C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_15                   0x3A6960
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_0                   0x3A6964
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_1                   0x3A6968
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_2                   0x3A696C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_3                   0x3A6970
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_4                   0x3A6974
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_5                   0x3A6978
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_6                   0x3A697C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_7                   0x3A6980
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_8                   0x3A6984
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_9                   0x3A6988
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_10                  0x3A698C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_11                  0x3A6990
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_12                  0x3A6994
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_13                  0x3A6998
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_14                  0x3A699C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_15                  0x3A69A0
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_0                    0x3A69A4
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_1                    0x3A69A8
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_2                    0x3A69AC
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_3                    0x3A69B0
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_4                    0x3A69B4
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_5                    0x3A69B8
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_6                    0x3A69BC
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_7                    0x3A69C0
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_8                    0x3A69C4
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_9                    0x3A69C8
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_10                   0x3A69CC
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_11                   0x3A69D0
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_12                   0x3A69D4
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_13                   0x3A69D8
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_14                   0x3A69DC
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_15                   0x3A69E0
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_0                   0x3A69E4
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_1                   0x3A69E8
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_2                   0x3A69EC
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_3                   0x3A69F0
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_4                   0x3A69F4
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_5                   0x3A69F8
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_6                   0x3A69FC
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_7                   0x3A6A00
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_8                   0x3A6A04
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_9                   0x3A6A08
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_10                  0x3A6A0C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_11                  0x3A6A10
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_12                  0x3A6A14
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_13                  0x3A6A18
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_14                  0x3A6A1C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_15                  0x3A6A20
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_HIT_AW                            0x3A6A64
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_HIT_AR                            0x3A6A68
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_HIT_AW                           0x3A6A6C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_HIT_AR                           0x3A6A70
+
+#define mmNIF_RTR_CTRL_2_RGL_CFG                                     0x3A6B64
+
+#define mmNIF_RTR_CTRL_2_RGL_SHIFT                                   0x3A6B68
+
+#define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_0                          0x3A6B6C
+
+#define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_1                          0x3A6B70
+
+#define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_2                          0x3A6B74
+
+#define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_3                          0x3A6B78
+
+#define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_4                          0x3A6B7C
+
+#define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_5                          0x3A6B80
+
+#define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_6                          0x3A6B84
+
+#define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_7                          0x3A6B88
+
+#define mmNIF_RTR_CTRL_2_RGL_TOKEN_0                                 0x3A6BAC
+
+#define mmNIF_RTR_CTRL_2_RGL_TOKEN_1                                 0x3A6BB0
+
+#define mmNIF_RTR_CTRL_2_RGL_TOKEN_2                                 0x3A6BB4
+
+#define mmNIF_RTR_CTRL_2_RGL_TOKEN_3                                 0x3A6BB8
+
+#define mmNIF_RTR_CTRL_2_RGL_TOKEN_4                                 0x3A6BBC
+
+#define mmNIF_RTR_CTRL_2_RGL_TOKEN_5                                 0x3A6BC0
+
+#define mmNIF_RTR_CTRL_2_RGL_TOKEN_6                                 0x3A6BC4
+
+#define mmNIF_RTR_CTRL_2_RGL_TOKEN_7                                 0x3A6BC8
+
+#define mmNIF_RTR_CTRL_2_RGL_BANK_ID_0                               0x3A6BEC
+
+#define mmNIF_RTR_CTRL_2_RGL_BANK_ID_1                               0x3A6BF0
+
+#define mmNIF_RTR_CTRL_2_RGL_BANK_ID_2                               0x3A6BF4
+
+#define mmNIF_RTR_CTRL_2_RGL_BANK_ID_3                               0x3A6BF8
+
+#define mmNIF_RTR_CTRL_2_RGL_BANK_ID_4                               0x3A6BFC
+
+#define mmNIF_RTR_CTRL_2_RGL_BANK_ID_5                               0x3A6C00
+
+#define mmNIF_RTR_CTRL_2_RGL_BANK_ID_6                               0x3A6C04
+
+#define mmNIF_RTR_CTRL_2_RGL_BANK_ID_7                               0x3A6C08
+
+#define mmNIF_RTR_CTRL_2_RGL_WDT                                     0x3A6C2C
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_HBM0_CH0_CTR_WRAP                    0x3A6C30
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_HBM0_CH1_CTR_WRAP                    0x3A6C34
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_HBM1_CH0_CTR_WRAP                    0x3A6C38
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_HBM1_CH1_CTR_WRAP                    0x3A6C3C
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_HBM2_CH0_CTR_WRAP                    0x3A6C40
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_HBM2_CH1_CTR_WRAP                    0x3A6C44
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_HBM3_CH0_CTR_WRAP                    0x3A6C48
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_HBM3_CH1_CTR_WRAP                    0x3A6C4C
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_HBM0_CH0_CTR_CNT                     0x3A6C50
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_HBM0_CH1_CTR_CNT                     0x3A6C54
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_HBM1_CH0_CTR_CNT                     0x3A6C58
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_HBM1_CH1_CTR_CNT                     0x3A6C5C
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_HBM2_CH0_CTR_CNT                     0x3A6C60
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_HBM2_CH1_CTR_CNT                     0x3A6C64
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_HBM3_CH0_CTR_CNT                     0x3A6C68
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_HBM3_CH1_CTR_CNT                     0x3A6C6C
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_HBM0_CH0_CTR_WRAP                    0x3A6C70
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_HBM0_CH1_CTR_WRAP                    0x3A6C74
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_HBM1_CH0_CTR_WRAP                    0x3A6C78
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_HBM1_CH1_CTR_WRAP                    0x3A6C7C
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_HBM2_CH0_CTR_WRAP                    0x3A6C80
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_HBM2_CH1_CTR_WRAP                    0x3A6C84
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_HBM3_CH0_CTR_WRAP                    0x3A6C88
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_HBM3_CH1_CTR_WRAP                    0x3A6C8C
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_HBM0_CH0_CTR_CNT                     0x3A6C90
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_HBM0_CH1_CTR_CNT                     0x3A6C94
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_HBM1_CH0_CTR_CNT                     0x3A6C98
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_HBM1_CH1_CTR_CNT                     0x3A6C9C
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_HBM2_CH0_CTR_CNT                     0x3A6CA0
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_HBM2_CH1_CTR_CNT                     0x3A6CA4
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_HBM3_CH0_CTR_CNT                     0x3A6CA8
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_HBM3_CH1_CTR_CNT                     0x3A6CAC
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_PC_SEL_0                             0x3A6CB0
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_PC_SEL_1                             0x3A6CB4
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_PC_SEL_2                             0x3A6CB8
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_PC_SEL_3                             0x3A6CBC
+
+#endif /* ASIC_REG_NIF_RTR_CTRL_2_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_3_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_3_regs.h
new file mode 100644
index 000000000000..34fd47685edd
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_3_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_NIF_RTR_CTRL_3_REGS_H_
+#define ASIC_REG_NIF_RTR_CTRL_3_REGS_H_
+
+/*
+ *****************************************
+ *   NIF_RTR_CTRL_3 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmNIF_RTR_CTRL_3_PERM_SEL                                    0x3B6108
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_0                               0x3B6114
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_1                               0x3B6118
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_2                               0x3B611C
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_3                               0x3B6120
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_4                               0x3B6124
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_5                               0x3B6128
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_6                               0x3B612C
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_7                               0x3B6130
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_8                               0x3B6134
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_9                               0x3B6138
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_10                              0x3B613C
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_11                              0x3B6140
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_12                              0x3B6144
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_13                              0x3B6148
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_14                              0x3B614C
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_15                              0x3B6150
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_16                              0x3B6154
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_17                              0x3B6158
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_18                              0x3B615C
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_19                              0x3B6160
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_20                              0x3B6164
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_21                              0x3B6168
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_22                              0x3B616C
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_23                              0x3B6170
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_24                              0x3B6174
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_25                              0x3B6178
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_26                              0x3B617C
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_27                              0x3B6180
+
+#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_0                              0x3B6184
+
+#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_1                              0x3B6188
+
+#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_2                              0x3B618C
+
+#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_3                              0x3B6190
+
+#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_4                              0x3B6194
+
+#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_5                              0x3B6198
+
+#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_6                              0x3B619C
+
+#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_7                              0x3B61A0
+
+#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_8                              0x3B61A4
+
+#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_9                              0x3B61A8
+
+#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_10                             0x3B61AC
+
+#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_11                             0x3B61B0
+
+#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_12                             0x3B61B4
+
+#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_13                             0x3B61B8
+
+#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_14                             0x3B61BC
+
+#define mmNIF_RTR_CTRL_3_SCRAM_SRAM_EN                               0x3B626C
+
+#define mmNIF_RTR_CTRL_3_RL_HBM_EN                                   0x3B6274
+
+#define mmNIF_RTR_CTRL_3_RL_HBM_SAT                                  0x3B6278
+
+#define mmNIF_RTR_CTRL_3_RL_HBM_RST                                  0x3B627C
+
+#define mmNIF_RTR_CTRL_3_RL_HBM_TIMEOUT                              0x3B6280
+
+#define mmNIF_RTR_CTRL_3_SCRAM_HBM_EN                                0x3B6284
+
+#define mmNIF_RTR_CTRL_3_RL_PCI_EN                                   0x3B6288
+
+#define mmNIF_RTR_CTRL_3_RL_PCI_SAT                                  0x3B628C
+
+#define mmNIF_RTR_CTRL_3_RL_PCI_RST                                  0x3B6290
+
+#define mmNIF_RTR_CTRL_3_RL_PCI_TIMEOUT                              0x3B6294
+
+#define mmNIF_RTR_CTRL_3_RL_SRAM_EN                                  0x3B629C
+
+#define mmNIF_RTR_CTRL_3_RL_SRAM_SAT                                 0x3B62A0
+
+#define mmNIF_RTR_CTRL_3_RL_SRAM_RST                                 0x3B62A4
+
+#define mmNIF_RTR_CTRL_3_RL_SRAM_TIMEOUT                             0x3B62AC
+
+#define mmNIF_RTR_CTRL_3_RL_SRAM_RED                                 0x3B62B4
+
+#define mmNIF_RTR_CTRL_3_E2E_HBM_EN                                  0x3B62EC
+
+#define mmNIF_RTR_CTRL_3_E2E_PCI_EN                                  0x3B62F0
+
+#define mmNIF_RTR_CTRL_3_E2E_HBM_WR_SIZE                             0x3B62F4
+
+#define mmNIF_RTR_CTRL_3_E2E_PCI_WR_SIZE                             0x3B62F8
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_PCI_CTR_SET_EN                       0x3B6404
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_PCI_CTR_SET                          0x3B6408
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_PCI_CTR_WRAP                         0x3B640C
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_PCI_CTR_CNT                          0x3B6410
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_HBM_CTR_SET_EN                       0x3B6414
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_HBM_CTR_SET                          0x3B6418
+
+#define mmNIF_RTR_CTRL_3_E2E_HBM_RD_SIZE                             0x3B641C
+
+#define mmNIF_RTR_CTRL_3_E2E_PCI_RD_SIZE                             0x3B6420
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_PCI_CTR_SET_EN                       0x3B6424
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_PCI_CTR_SET                          0x3B6428
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_PCI_CTR_WRAP                         0x3B642C
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_PCI_CTR_CNT                          0x3B6430
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_HBM_CTR_SET_EN                       0x3B6434
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_HBM_CTR_SET                          0x3B6438
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_SEL_0                                0x3B6450
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_SEL_1                                0x3B6454
+
+#define mmNIF_RTR_CTRL_3_NON_LIN_EN                                  0x3B6480
+
+#define mmNIF_RTR_CTRL_3_NL_SRAM_BANK_0                              0x3B6500
+
+#define mmNIF_RTR_CTRL_3_NL_SRAM_BANK_1                              0x3B6504
+
+#define mmNIF_RTR_CTRL_3_NL_SRAM_BANK_2                              0x3B6508
+
+#define mmNIF_RTR_CTRL_3_NL_SRAM_BANK_3                              0x3B650C
+
+#define mmNIF_RTR_CTRL_3_NL_SRAM_BANK_4                              0x3B6510
+
+#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_0                            0x3B6514
+
+#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_1                            0x3B6520
+
+#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_2                            0x3B6524
+
+#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_3                            0x3B6528
+
+#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_4                            0x3B652C
+
+#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_5                            0x3B6530
+
+#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_6                            0x3B6534
+
+#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_7                            0x3B6538
+
+#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_8                            0x3B653C
+
+#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_9                            0x3B6540
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_0                             0x3B6550
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_1                             0x3B6554
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_2                             0x3B6558
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_3                             0x3B655C
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_4                             0x3B6560
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_5                             0x3B6564
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_6                             0x3B6568
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_7                             0x3B656C
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_8                             0x3B6570
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_9                             0x3B6574
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_10                            0x3B6578
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_11                            0x3B657C
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_12                            0x3B6580
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_13                            0x3B6584
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_14                            0x3B6588
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_15                            0x3B658C
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_16                            0x3B6590
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_17                            0x3B6594
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_18                            0x3B6598
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_0                     0x3B65E4
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_1                     0x3B65E8
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_2                     0x3B65EC
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_3                     0x3B65F0
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_4                     0x3B65F4
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_5                     0x3B65F8
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_6                     0x3B65FC
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_7                     0x3B6600
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_8                     0x3B6604
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_9                     0x3B6608
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_10                    0x3B660C
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_11                    0x3B6610
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_12                    0x3B6614
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_13                    0x3B6618
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_14                    0x3B661C
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_15                    0x3B6620
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_0                    0x3B6624
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_1                    0x3B6628
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_2                    0x3B662C
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_3                    0x3B6630
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_4                    0x3B6634
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_5                    0x3B6638
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_6                    0x3B663C
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_7                    0x3B6640
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_8                    0x3B6644
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_9                    0x3B6648
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_10                   0x3B664C
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_11                   0x3B6650
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_12                   0x3B6654
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_13                   0x3B6658
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_14                   0x3B665C
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_15                   0x3B6660
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_0                     0x3B6664
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_1                     0x3B6668
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_2                     0x3B666C
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_3                     0x3B6670
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_4                     0x3B6674
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_5                     0x3B6678
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_6                     0x3B667C
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_7                     0x3B6680
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_8                     0x3B6684
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_9                     0x3B6688
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_10                    0x3B668C
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_11                    0x3B6690
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_12                    0x3B6694
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_13                    0x3B6698
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_14                    0x3B669C
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_15                    0x3B66A0
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_0                    0x3B66A4
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_1                    0x3B66A8
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_2                    0x3B66AC
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_3                    0x3B66B0
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_4                    0x3B66B4
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_5                    0x3B66B8
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_6                    0x3B66BC
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_7                    0x3B66C0
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_8                    0x3B66C4
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_9                    0x3B66C8
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_10                   0x3B66CC
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_11                   0x3B66D0
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_12                   0x3B66D4
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_13                   0x3B66D8
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_14                   0x3B66DC
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_15                   0x3B66E0
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_0                    0x3B66E4
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_1                    0x3B66E8
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_2                    0x3B66EC
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_3                    0x3B66F0
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_4                    0x3B66F4
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_5                    0x3B66F8
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_6                    0x3B66FC
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_7                    0x3B6700
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_8                    0x3B6704
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_9                    0x3B6708
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_10                   0x3B670C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_11                   0x3B6710
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_12                   0x3B6714
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_13                   0x3B6718
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_14                   0x3B671C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_15                   0x3B6720
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_0                   0x3B6724
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_1                   0x3B6728
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_2                   0x3B672C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_3                   0x3B6730
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_4                   0x3B6734
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_5                   0x3B6738
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_6                   0x3B673C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_7                   0x3B6740
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_8                   0x3B6744
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_9                   0x3B6748
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_10                  0x3B674C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_11                  0x3B6750
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_12                  0x3B6754
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_13                  0x3B6758
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_14                  0x3B675C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_15                  0x3B6760
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_0                    0x3B6764
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_1                    0x3B6768
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_2                    0x3B676C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_3                    0x3B6770
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_4                    0x3B6774
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_5                    0x3B6778
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_6                    0x3B677C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_7                    0x3B6780
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_8                    0x3B6784
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_9                    0x3B6788
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_10                   0x3B678C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_11                   0x3B6790
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_12                   0x3B6794
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_13                   0x3B6798
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_14                   0x3B679C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_15                   0x3B67A0
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_0                   0x3B67A4
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_1                   0x3B67A8
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_2                   0x3B67AC
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_3                   0x3B67B0
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_4                   0x3B67B4
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_5                   0x3B67B8
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_6                   0x3B67BC
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_7                   0x3B67C0
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_8                   0x3B67C4
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_9                   0x3B67C8
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_10                  0x3B67CC
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_11                  0x3B67D0
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_12                  0x3B67D4
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_13                  0x3B67D8
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_14                  0x3B67DC
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_15                  0x3B67E0
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_0                     0x3B6824
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_1                     0x3B6828
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_2                     0x3B682C
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_3                     0x3B6830
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_4                     0x3B6834
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_5                     0x3B6838
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_6                     0x3B683C
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_7                     0x3B6840
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_8                     0x3B6844
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_9                     0x3B6848
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_10                    0x3B684C
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_11                    0x3B6850
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_12                    0x3B6854
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_13                    0x3B6858
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_14                    0x3B685C
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_15                    0x3B6860
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_0                    0x3B6864
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_1                    0x3B6868
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_2                    0x3B686C
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_3                    0x3B6870
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_4                    0x3B6874
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_5                    0x3B6878
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_6                    0x3B687C
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_7                    0x3B6880
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_8                    0x3B6884
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_9                    0x3B6888
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_10                   0x3B688C
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_11                   0x3B6890
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_12                   0x3B6894
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_13                   0x3B6898
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_14                   0x3B689C
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_15                   0x3B68A0
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_0                     0x3B68A4
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_1                     0x3B68A8
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_2                     0x3B68AC
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_3                     0x3B68B0
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_4                     0x3B68B4
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_5                     0x3B68B8
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_6                     0x3B68BC
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_7                     0x3B68C0
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_8                     0x3B68C4
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_9                     0x3B68C8
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_10                    0x3B68CC
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_11                    0x3B68D0
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_12                    0x3B68D4
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_13                    0x3B68D8
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_14                    0x3B68DC
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_15                    0x3B68E0
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_0                    0x3B68E4
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_1                    0x3B68E8
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_2                    0x3B68EC
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_3                    0x3B68F0
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_4                    0x3B68F4
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_5                    0x3B68F8
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_6                    0x3B68FC
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_7                    0x3B6900
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_8                    0x3B6904
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_9                    0x3B6908
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_10                   0x3B690C
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_11                   0x3B6910
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_12                   0x3B6914
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_13                   0x3B6918
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_14                   0x3B691C
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_15                   0x3B6920
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_0                    0x3B6924
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_1                    0x3B6928
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_2                    0x3B692C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_3                    0x3B6930
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_4                    0x3B6934
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_5                    0x3B6938
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_6                    0x3B693C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_7                    0x3B6940
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_8                    0x3B6944
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_9                    0x3B6948
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_10                   0x3B694C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_11                   0x3B6950
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_12                   0x3B6954
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_13                   0x3B6958
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_14                   0x3B695C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_15                   0x3B6960
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_0                   0x3B6964
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_1                   0x3B6968
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_2                   0x3B696C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_3                   0x3B6970
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_4                   0x3B6974
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_5                   0x3B6978
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_6                   0x3B697C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_7                   0x3B6980
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_8                   0x3B6984
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_9                   0x3B6988
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_10                  0x3B698C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_11                  0x3B6990
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_12                  0x3B6994
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_13                  0x3B6998
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_14                  0x3B699C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_15                  0x3B69A0
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_0                    0x3B69A4
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_1                    0x3B69A8
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_2                    0x3B69AC
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_3                    0x3B69B0
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_4                    0x3B69B4
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_5                    0x3B69B8
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_6                    0x3B69BC
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_7                    0x3B69C0
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_8                    0x3B69C4
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_9                    0x3B69C8
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_10                   0x3B69CC
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_11                   0x3B69D0
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_12                   0x3B69D4
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_13                   0x3B69D8
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_14                   0x3B69DC
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_15                   0x3B69E0
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_0                   0x3B69E4
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_1                   0x3B69E8
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_2                   0x3B69EC
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_3                   0x3B69F0
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_4                   0x3B69F4
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_5                   0x3B69F8
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_6                   0x3B69FC
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_7                   0x3B6A00
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_8                   0x3B6A04
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_9                   0x3B6A08
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_10                  0x3B6A0C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_11                  0x3B6A10
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_12                  0x3B6A14
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_13                  0x3B6A18
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_14                  0x3B6A1C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_15                  0x3B6A20
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_HIT_AW                            0x3B6A64
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_HIT_AR                            0x3B6A68
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_HIT_AW                           0x3B6A6C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_HIT_AR                           0x3B6A70
+
+#define mmNIF_RTR_CTRL_3_RGL_CFG                                     0x3B6B64
+
+#define mmNIF_RTR_CTRL_3_RGL_SHIFT                                   0x3B6B68
+
+#define mmNIF_RTR_CTRL_3_RGL_EXPECTED_LAT_0                          0x3B6B6C
+
+#define mmNIF_RTR_CTRL_3_RGL_EXPECTED_LAT_1                          0x3B6B70
+
+#define mmNIF_RTR_CTRL_3_RGL_EXPECTED_LAT_2                          0x3B6B74
+
+#define mmNIF_RTR_CTRL_3_RGL_EXPECTED_LAT_3                          0x3B6B78
+
+#define mmNIF_RTR_CTRL_3_RGL_EXPECTED_LAT_4                          0x3B6B7C
+
+#define mmNIF_RTR_CTRL_3_RGL_EXPECTED_LAT_5                          0x3B6B80
+
+#define mmNIF_RTR_CTRL_3_RGL_EXPECTED_LAT_6                          0x3B6B84
+
+#define mmNIF_RTR_CTRL_3_RGL_EXPECTED_LAT_7                          0x3B6B88
+
+#define mmNIF_RTR_CTRL_3_RGL_TOKEN_0                                 0x3B6BAC
+
+#define mmNIF_RTR_CTRL_3_RGL_TOKEN_1                                 0x3B6BB0
+
+#define mmNIF_RTR_CTRL_3_RGL_TOKEN_2                                 0x3B6BB4
+
+#define mmNIF_RTR_CTRL_3_RGL_TOKEN_3                                 0x3B6BB8
+
+#define mmNIF_RTR_CTRL_3_RGL_TOKEN_4                                 0x3B6BBC
+
+#define mmNIF_RTR_CTRL_3_RGL_TOKEN_5                                 0x3B6BC0
+
+#define mmNIF_RTR_CTRL_3_RGL_TOKEN_6                                 0x3B6BC4
+
+#define mmNIF_RTR_CTRL_3_RGL_TOKEN_7                                 0x3B6BC8
+
+#define mmNIF_RTR_CTRL_3_RGL_BANK_ID_0                               0x3B6BEC
+
+#define mmNIF_RTR_CTRL_3_RGL_BANK_ID_1                               0x3B6BF0
+
+#define mmNIF_RTR_CTRL_3_RGL_BANK_ID_2                               0x3B6BF4
+
+#define mmNIF_RTR_CTRL_3_RGL_BANK_ID_3                               0x3B6BF8
+
+#define mmNIF_RTR_CTRL_3_RGL_BANK_ID_4                               0x3B6BFC
+
+#define mmNIF_RTR_CTRL_3_RGL_BANK_ID_5                               0x3B6C00
+
+#define mmNIF_RTR_CTRL_3_RGL_BANK_ID_6                               0x3B6C04
+
+#define mmNIF_RTR_CTRL_3_RGL_BANK_ID_7                               0x3B6C08
+
+#define mmNIF_RTR_CTRL_3_RGL_WDT                                     0x3B6C2C
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_HBM0_CH0_CTR_WRAP                    0x3B6C30
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_HBM0_CH1_CTR_WRAP                    0x3B6C34
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_HBM1_CH0_CTR_WRAP                    0x3B6C38
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_HBM1_CH1_CTR_WRAP                    0x3B6C3C
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_HBM2_CH0_CTR_WRAP                    0x3B6C40
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_HBM2_CH1_CTR_WRAP                    0x3B6C44
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_HBM3_CH0_CTR_WRAP                    0x3B6C48
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_HBM3_CH1_CTR_WRAP                    0x3B6C4C
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_HBM0_CH0_CTR_CNT                     0x3B6C50
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_HBM0_CH1_CTR_CNT                     0x3B6C54
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_HBM1_CH0_CTR_CNT                     0x3B6C58
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_HBM1_CH1_CTR_CNT                     0x3B6C5C
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_HBM2_CH0_CTR_CNT                     0x3B6C60
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_HBM2_CH1_CTR_CNT                     0x3B6C64
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_HBM3_CH0_CTR_CNT                     0x3B6C68
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_HBM3_CH1_CTR_CNT                     0x3B6C6C
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_HBM0_CH0_CTR_WRAP                    0x3B6C70
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_HBM0_CH1_CTR_WRAP                    0x3B6C74
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_HBM1_CH0_CTR_WRAP                    0x3B6C78
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_HBM1_CH1_CTR_WRAP                    0x3B6C7C
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_HBM2_CH0_CTR_WRAP                    0x3B6C80
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_HBM2_CH1_CTR_WRAP                    0x3B6C84
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_HBM3_CH0_CTR_WRAP                    0x3B6C88
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_HBM3_CH1_CTR_WRAP                    0x3B6C8C
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_HBM0_CH0_CTR_CNT                     0x3B6C90
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_HBM0_CH1_CTR_CNT                     0x3B6C94
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_HBM1_CH0_CTR_CNT                     0x3B6C98
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_HBM1_CH1_CTR_CNT                     0x3B6C9C
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_HBM2_CH0_CTR_CNT                     0x3B6CA0
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_HBM2_CH1_CTR_CNT                     0x3B6CA4
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_HBM3_CH0_CTR_CNT                     0x3B6CA8
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_HBM3_CH1_CTR_CNT                     0x3B6CAC
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_PC_SEL_0                             0x3B6CB0
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_PC_SEL_1                             0x3B6CB4
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_PC_SEL_2                             0x3B6CB8
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_PC_SEL_3                             0x3B6CBC
+
+#endif /* ASIC_REG_NIF_RTR_CTRL_3_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_4_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_4_regs.h
new file mode 100644
index 000000000000..543a98f81767
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_4_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_NIF_RTR_CTRL_4_REGS_H_
+#define ASIC_REG_NIF_RTR_CTRL_4_REGS_H_
+
+/*
+ *****************************************
+ *   NIF_RTR_CTRL_4 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmNIF_RTR_CTRL_4_PERM_SEL                                    0x3C6108
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_0                               0x3C6114
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_1                               0x3C6118
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_2                               0x3C611C
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_3                               0x3C6120
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_4                               0x3C6124
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_5                               0x3C6128
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_6                               0x3C612C
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_7                               0x3C6130
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_8                               0x3C6134
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_9                               0x3C6138
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_10                              0x3C613C
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_11                              0x3C6140
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_12                              0x3C6144
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_13                              0x3C6148
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_14                              0x3C614C
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_15                              0x3C6150
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_16                              0x3C6154
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_17                              0x3C6158
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_18                              0x3C615C
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_19                              0x3C6160
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_20                              0x3C6164
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_21                              0x3C6168
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_22                              0x3C616C
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_23                              0x3C6170
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_24                              0x3C6174
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_25                              0x3C6178
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_26                              0x3C617C
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_27                              0x3C6180
+
+#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_0                              0x3C6184
+
+#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_1                              0x3C6188
+
+#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_2                              0x3C618C
+
+#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_3                              0x3C6190
+
+#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_4                              0x3C6194
+
+#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_5                              0x3C6198
+
+#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_6                              0x3C619C
+
+#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_7                              0x3C61A0
+
+#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_8                              0x3C61A4
+
+#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_9                              0x3C61A8
+
+#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_10                             0x3C61AC
+
+#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_11                             0x3C61B0
+
+#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_12                             0x3C61B4
+
+#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_13                             0x3C61B8
+
+#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_14                             0x3C61BC
+
+#define mmNIF_RTR_CTRL_4_SCRAM_SRAM_EN                               0x3C626C
+
+#define mmNIF_RTR_CTRL_4_RL_HBM_EN                                   0x3C6274
+
+#define mmNIF_RTR_CTRL_4_RL_HBM_SAT                                  0x3C6278
+
+#define mmNIF_RTR_CTRL_4_RL_HBM_RST                                  0x3C627C
+
+#define mmNIF_RTR_CTRL_4_RL_HBM_TIMEOUT                              0x3C6280
+
+#define mmNIF_RTR_CTRL_4_SCRAM_HBM_EN                                0x3C6284
+
+#define mmNIF_RTR_CTRL_4_RL_PCI_EN                                   0x3C6288
+
+#define mmNIF_RTR_CTRL_4_RL_PCI_SAT                                  0x3C628C
+
+#define mmNIF_RTR_CTRL_4_RL_PCI_RST                                  0x3C6290
+
+#define mmNIF_RTR_CTRL_4_RL_PCI_TIMEOUT                              0x3C6294
+
+#define mmNIF_RTR_CTRL_4_RL_SRAM_EN                                  0x3C629C
+
+#define mmNIF_RTR_CTRL_4_RL_SRAM_SAT                                 0x3C62A0
+
+#define mmNIF_RTR_CTRL_4_RL_SRAM_RST                                 0x3C62A4
+
+#define mmNIF_RTR_CTRL_4_RL_SRAM_TIMEOUT                             0x3C62AC
+
+#define mmNIF_RTR_CTRL_4_RL_SRAM_RED                                 0x3C62B4
+
+#define mmNIF_RTR_CTRL_4_E2E_HBM_EN                                  0x3C62EC
+
+#define mmNIF_RTR_CTRL_4_E2E_PCI_EN                                  0x3C62F0
+
+#define mmNIF_RTR_CTRL_4_E2E_HBM_WR_SIZE                             0x3C62F4
+
+#define mmNIF_RTR_CTRL_4_E2E_PCI_WR_SIZE                             0x3C62F8
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_PCI_CTR_SET_EN                       0x3C6404
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_PCI_CTR_SET                          0x3C6408
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_PCI_CTR_WRAP                         0x3C640C
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_PCI_CTR_CNT                          0x3C6410
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_HBM_CTR_SET_EN                       0x3C6414
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_HBM_CTR_SET                          0x3C6418
+
+#define mmNIF_RTR_CTRL_4_E2E_HBM_RD_SIZE                             0x3C641C
+
+#define mmNIF_RTR_CTRL_4_E2E_PCI_RD_SIZE                             0x3C6420
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_PCI_CTR_SET_EN                       0x3C6424
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_PCI_CTR_SET                          0x3C6428
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_PCI_CTR_WRAP                         0x3C642C
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_PCI_CTR_CNT                          0x3C6430
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_HBM_CTR_SET_EN                       0x3C6434
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_HBM_CTR_SET                          0x3C6438
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_SEL_0                                0x3C6450
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_SEL_1                                0x3C6454
+
+#define mmNIF_RTR_CTRL_4_NON_LIN_EN                                  0x3C6480
+
+#define mmNIF_RTR_CTRL_4_NL_SRAM_BANK_0                              0x3C6500
+
+#define mmNIF_RTR_CTRL_4_NL_SRAM_BANK_1                              0x3C6504
+
+#define mmNIF_RTR_CTRL_4_NL_SRAM_BANK_2                              0x3C6508
+
+#define mmNIF_RTR_CTRL_4_NL_SRAM_BANK_3                              0x3C650C
+
+#define mmNIF_RTR_CTRL_4_NL_SRAM_BANK_4                              0x3C6510
+
+#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_0                            0x3C6514
+
+#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_1                            0x3C6520
+
+#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_2                            0x3C6524
+
+#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_3                            0x3C6528
+
+#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_4                            0x3C652C
+
+#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_5                            0x3C6530
+
+#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_6                            0x3C6534
+
+#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_7                            0x3C6538
+
+#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_8                            0x3C653C
+
+#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_9                            0x3C6540
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_0                             0x3C6550
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_1                             0x3C6554
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_2                             0x3C6558
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_3                             0x3C655C
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_4                             0x3C6560
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_5                             0x3C6564
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_6                             0x3C6568
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_7                             0x3C656C
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_8                             0x3C6570
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_9                             0x3C6574
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_10                            0x3C6578
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_11                            0x3C657C
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_12                            0x3C6580
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_13                            0x3C6584
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_14                            0x3C6588
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_15                            0x3C658C
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_16                            0x3C6590
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_17                            0x3C6594
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_18                            0x3C6598
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_0                     0x3C65E4
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_1                     0x3C65E8
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_2                     0x3C65EC
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_3                     0x3C65F0
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_4                     0x3C65F4
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_5                     0x3C65F8
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_6                     0x3C65FC
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_7                     0x3C6600
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_8                     0x3C6604
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_9                     0x3C6608
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_10                    0x3C660C
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_11                    0x3C6610
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_12                    0x3C6614
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_13                    0x3C6618
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_14                    0x3C661C
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_15                    0x3C6620
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_0                    0x3C6624
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_1                    0x3C6628
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_2                    0x3C662C
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_3                    0x3C6630
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_4                    0x3C6634
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_5                    0x3C6638
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_6                    0x3C663C
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_7                    0x3C6640
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_8                    0x3C6644
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_9                    0x3C6648
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_10                   0x3C664C
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_11                   0x3C6650
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_12                   0x3C6654
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_13                   0x3C6658
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_14                   0x3C665C
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_15                   0x3C6660
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_0                     0x3C6664
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_1                     0x3C6668
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_2                     0x3C666C
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_3                     0x3C6670
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_4                     0x3C6674
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_5                     0x3C6678
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_6                     0x3C667C
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_7                     0x3C6680
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_8                     0x3C6684
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_9                     0x3C6688
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_10                    0x3C668C
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_11                    0x3C6690
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_12                    0x3C6694
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_13                    0x3C6698
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_14                    0x3C669C
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_15                    0x3C66A0
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_0                    0x3C66A4
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_1                    0x3C66A8
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_2                    0x3C66AC
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_3                    0x3C66B0
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_4                    0x3C66B4
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_5                    0x3C66B8
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_6                    0x3C66BC
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_7                    0x3C66C0
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_8                    0x3C66C4
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_9                    0x3C66C8
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_10                   0x3C66CC
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_11                   0x3C66D0
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_12                   0x3C66D4
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_13                   0x3C66D8
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_14                   0x3C66DC
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_15                   0x3C66E0
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_0                    0x3C66E4
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_1                    0x3C66E8
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_2                    0x3C66EC
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_3                    0x3C66F0
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_4                    0x3C66F4
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_5                    0x3C66F8
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_6                    0x3C66FC
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_7                    0x3C6700
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_8                    0x3C6704
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_9                    0x3C6708
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_10                   0x3C670C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_11                   0x3C6710
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_12                   0x3C6714
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_13                   0x3C6718
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_14                   0x3C671C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_15                   0x3C6720
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_0                   0x3C6724
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_1                   0x3C6728
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_2                   0x3C672C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_3                   0x3C6730
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_4                   0x3C6734
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_5                   0x3C6738
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_6                   0x3C673C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_7                   0x3C6740
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_8                   0x3C6744
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_9                   0x3C6748
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_10                  0x3C674C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_11                  0x3C6750
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_12                  0x3C6754
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_13                  0x3C6758
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_14                  0x3C675C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_15                  0x3C6760
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_0                    0x3C6764
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_1                    0x3C6768
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_2                    0x3C676C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_3                    0x3C6770
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_4                    0x3C6774
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_5                    0x3C6778
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_6                    0x3C677C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_7                    0x3C6780
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_8                    0x3C6784
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_9                    0x3C6788
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_10                   0x3C678C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_11                   0x3C6790
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_12                   0x3C6794
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_13                   0x3C6798
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_14                   0x3C679C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_15                   0x3C67A0
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_0                   0x3C67A4
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_1                   0x3C67A8
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_2                   0x3C67AC
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_3                   0x3C67B0
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_4                   0x3C67B4
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_5                   0x3C67B8
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_6                   0x3C67BC
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_7                   0x3C67C0
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_8                   0x3C67C4
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_9                   0x3C67C8
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_10                  0x3C67CC
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_11                  0x3C67D0
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_12                  0x3C67D4
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_13                  0x3C67D8
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_14                  0x3C67DC
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_15                  0x3C67E0
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_0                     0x3C6824
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_1                     0x3C6828
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_2                     0x3C682C
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_3                     0x3C6830
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_4                     0x3C6834
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_5                     0x3C6838
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_6                     0x3C683C
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_7                     0x3C6840
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_8                     0x3C6844
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_9                     0x3C6848
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_10                    0x3C684C
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_11                    0x3C6850
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_12                    0x3C6854
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_13                    0x3C6858
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_14                    0x3C685C
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_15                    0x3C6860
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_0                    0x3C6864
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_1                    0x3C6868
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_2                    0x3C686C
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_3                    0x3C6870
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_4                    0x3C6874
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_5                    0x3C6878
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_6                    0x3C687C
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_7                    0x3C6880
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_8                    0x3C6884
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_9                    0x3C6888
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_10                   0x3C688C
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_11                   0x3C6890
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_12                   0x3C6894
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_13                   0x3C6898
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_14                   0x3C689C
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_15                   0x3C68A0
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_0                     0x3C68A4
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_1                     0x3C68A8
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_2                     0x3C68AC
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_3                     0x3C68B0
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_4                     0x3C68B4
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_5                     0x3C68B8
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_6                     0x3C68BC
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_7                     0x3C68C0
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_8                     0x3C68C4
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_9                     0x3C68C8
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_10                    0x3C68CC
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_11                    0x3C68D0
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_12                    0x3C68D4
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_13                    0x3C68D8
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_14                    0x3C68DC
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_15                    0x3C68E0
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_0                    0x3C68E4
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_1                    0x3C68E8
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_2                    0x3C68EC
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_3                    0x3C68F0
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_4                    0x3C68F4
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_5                    0x3C68F8
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_6                    0x3C68FC
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_7                    0x3C6900
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_8                    0x3C6904
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_9                    0x3C6908
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_10                   0x3C690C
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_11                   0x3C6910
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_12                   0x3C6914
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_13                   0x3C6918
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_14                   0x3C691C
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_15                   0x3C6920
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_0                    0x3C6924
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_1                    0x3C6928
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_2                    0x3C692C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_3                    0x3C6930
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_4                    0x3C6934
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_5                    0x3C6938
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_6                    0x3C693C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_7                    0x3C6940
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_8                    0x3C6944
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_9                    0x3C6948
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_10                   0x3C694C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_11                   0x3C6950
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_12                   0x3C6954
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_13                   0x3C6958
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_14                   0x3C695C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_15                   0x3C6960
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_0                   0x3C6964
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_1                   0x3C6968
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_2                   0x3C696C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_3                   0x3C6970
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_4                   0x3C6974
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_5                   0x3C6978
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_6                   0x3C697C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_7                   0x3C6980
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_8                   0x3C6984
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_9                   0x3C6988
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_10                  0x3C698C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_11                  0x3C6990
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_12                  0x3C6994
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_13                  0x3C6998
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_14                  0x3C699C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_15                  0x3C69A0
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_0                    0x3C69A4
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_1                    0x3C69A8
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_2                    0x3C69AC
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_3                    0x3C69B0
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_4                    0x3C69B4
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_5                    0x3C69B8
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_6                    0x3C69BC
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_7                    0x3C69C0
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_8                    0x3C69C4
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_9                    0x3C69C8
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_10                   0x3C69CC
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_11                   0x3C69D0
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_12                   0x3C69D4
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_13                   0x3C69D8
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_14                   0x3C69DC
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_15                   0x3C69E0
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_0                   0x3C69E4
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_1                   0x3C69E8
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_2                   0x3C69EC
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_3                   0x3C69F0
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_4                   0x3C69F4
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_5                   0x3C69F8
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_6                   0x3C69FC
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_7                   0x3C6A00
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_8                   0x3C6A04
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_9                   0x3C6A08
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_10                  0x3C6A0C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_11                  0x3C6A10
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_12                  0x3C6A14
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_13                  0x3C6A18
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_14                  0x3C6A1C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_15                  0x3C6A20
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_HIT_AW                            0x3C6A64
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_HIT_AR                            0x3C6A68
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_HIT_AW                           0x3C6A6C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_HIT_AR                           0x3C6A70
+
+#define mmNIF_RTR_CTRL_4_RGL_CFG                                     0x3C6B64
+
+#define mmNIF_RTR_CTRL_4_RGL_SHIFT                                   0x3C6B68
+
+#define mmNIF_RTR_CTRL_4_RGL_EXPECTED_LAT_0                          0x3C6B6C
+
+#define mmNIF_RTR_CTRL_4_RGL_EXPECTED_LAT_1                          0x3C6B70
+
+#define mmNIF_RTR_CTRL_4_RGL_EXPECTED_LAT_2                          0x3C6B74
+
+#define mmNIF_RTR_CTRL_4_RGL_EXPECTED_LAT_3                          0x3C6B78
+
+#define mmNIF_RTR_CTRL_4_RGL_EXPECTED_LAT_4                          0x3C6B7C
+
+#define mmNIF_RTR_CTRL_4_RGL_EXPECTED_LAT_5                          0x3C6B80
+
+#define mmNIF_RTR_CTRL_4_RGL_EXPECTED_LAT_6                          0x3C6B84
+
+#define mmNIF_RTR_CTRL_4_RGL_EXPECTED_LAT_7                          0x3C6B88
+
+#define mmNIF_RTR_CTRL_4_RGL_TOKEN_0                                 0x3C6BAC
+
+#define mmNIF_RTR_CTRL_4_RGL_TOKEN_1                                 0x3C6BB0
+
+#define mmNIF_RTR_CTRL_4_RGL_TOKEN_2                                 0x3C6BB4
+
+#define mmNIF_RTR_CTRL_4_RGL_TOKEN_3                                 0x3C6BB8
+
+#define mmNIF_RTR_CTRL_4_RGL_TOKEN_4                                 0x3C6BBC
+
+#define mmNIF_RTR_CTRL_4_RGL_TOKEN_5                                 0x3C6BC0
+
+#define mmNIF_RTR_CTRL_4_RGL_TOKEN_6                                 0x3C6BC4
+
+#define mmNIF_RTR_CTRL_4_RGL_TOKEN_7                                 0x3C6BC8
+
+#define mmNIF_RTR_CTRL_4_RGL_BANK_ID_0                               0x3C6BEC
+
+#define mmNIF_RTR_CTRL_4_RGL_BANK_ID_1                               0x3C6BF0
+
+#define mmNIF_RTR_CTRL_4_RGL_BANK_ID_2                               0x3C6BF4
+
+#define mmNIF_RTR_CTRL_4_RGL_BANK_ID_3                               0x3C6BF8
+
+#define mmNIF_RTR_CTRL_4_RGL_BANK_ID_4                               0x3C6BFC
+
+#define mmNIF_RTR_CTRL_4_RGL_BANK_ID_5                               0x3C6C00
+
+#define mmNIF_RTR_CTRL_4_RGL_BANK_ID_6                               0x3C6C04
+
+#define mmNIF_RTR_CTRL_4_RGL_BANK_ID_7                               0x3C6C08
+
+#define mmNIF_RTR_CTRL_4_RGL_WDT                                     0x3C6C2C
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_HBM0_CH0_CTR_WRAP                    0x3C6C30
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_HBM0_CH1_CTR_WRAP                    0x3C6C34
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_HBM1_CH0_CTR_WRAP                    0x3C6C38
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_HBM1_CH1_CTR_WRAP                    0x3C6C3C
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_HBM2_CH0_CTR_WRAP                    0x3C6C40
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_HBM2_CH1_CTR_WRAP                    0x3C6C44
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_HBM3_CH0_CTR_WRAP                    0x3C6C48
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_HBM3_CH1_CTR_WRAP                    0x3C6C4C
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_HBM0_CH0_CTR_CNT                     0x3C6C50
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_HBM0_CH1_CTR_CNT                     0x3C6C54
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_HBM1_CH0_CTR_CNT                     0x3C6C58
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_HBM1_CH1_CTR_CNT                     0x3C6C5C
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_HBM2_CH0_CTR_CNT                     0x3C6C60
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_HBM2_CH1_CTR_CNT                     0x3C6C64
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_HBM3_CH0_CTR_CNT                     0x3C6C68
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_HBM3_CH1_CTR_CNT                     0x3C6C6C
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_HBM0_CH0_CTR_WRAP                    0x3C6C70
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_HBM0_CH1_CTR_WRAP                    0x3C6C74
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_HBM1_CH0_CTR_WRAP                    0x3C6C78
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_HBM1_CH1_CTR_WRAP                    0x3C6C7C
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_HBM2_CH0_CTR_WRAP                    0x3C6C80
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_HBM2_CH1_CTR_WRAP                    0x3C6C84
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_HBM3_CH0_CTR_WRAP                    0x3C6C88
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_HBM3_CH1_CTR_WRAP                    0x3C6C8C
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_HBM0_CH0_CTR_CNT                     0x3C6C90
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_HBM0_CH1_CTR_CNT                     0x3C6C94
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_HBM1_CH0_CTR_CNT                     0x3C6C98
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_HBM1_CH1_CTR_CNT                     0x3C6C9C
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_HBM2_CH0_CTR_CNT                     0x3C6CA0
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_HBM2_CH1_CTR_CNT                     0x3C6CA4
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_HBM3_CH0_CTR_CNT                     0x3C6CA8
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_HBM3_CH1_CTR_CNT                     0x3C6CAC
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_PC_SEL_0                             0x3C6CB0
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_PC_SEL_1                             0x3C6CB4
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_PC_SEL_2                             0x3C6CB8
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_PC_SEL_3                             0x3C6CBC
+
+#endif /* ASIC_REG_NIF_RTR_CTRL_4_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_5_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_5_regs.h
new file mode 100644
index 000000000000..95486b7ddf1d
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_5_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_NIF_RTR_CTRL_5_REGS_H_
+#define ASIC_REG_NIF_RTR_CTRL_5_REGS_H_
+
+/*
+ *****************************************
+ *   NIF_RTR_CTRL_5 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmNIF_RTR_CTRL_5_PERM_SEL                                    0x3D6108
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_0                               0x3D6114
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_1                               0x3D6118
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_2                               0x3D611C
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_3                               0x3D6120
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_4                               0x3D6124
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_5                               0x3D6128
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_6                               0x3D612C
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_7                               0x3D6130
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_8                               0x3D6134
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_9                               0x3D6138
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_10                              0x3D613C
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_11                              0x3D6140
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_12                              0x3D6144
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_13                              0x3D6148
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_14                              0x3D614C
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_15                              0x3D6150
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_16                              0x3D6154
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_17                              0x3D6158
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_18                              0x3D615C
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_19                              0x3D6160
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_20                              0x3D6164
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_21                              0x3D6168
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_22                              0x3D616C
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_23                              0x3D6170
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_24                              0x3D6174
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_25                              0x3D6178
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_26                              0x3D617C
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_27                              0x3D6180
+
+#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_0                              0x3D6184
+
+#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_1                              0x3D6188
+
+#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_2                              0x3D618C
+
+#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_3                              0x3D6190
+
+#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_4                              0x3D6194
+
+#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_5                              0x3D6198
+
+#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_6                              0x3D619C
+
+#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_7                              0x3D61A0
+
+#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_8                              0x3D61A4
+
+#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_9                              0x3D61A8
+
+#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_10                             0x3D61AC
+
+#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_11                             0x3D61B0
+
+#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_12                             0x3D61B4
+
+#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_13                             0x3D61B8
+
+#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_14                             0x3D61BC
+
+#define mmNIF_RTR_CTRL_5_SCRAM_SRAM_EN                               0x3D626C
+
+#define mmNIF_RTR_CTRL_5_RL_HBM_EN                                   0x3D6274
+
+#define mmNIF_RTR_CTRL_5_RL_HBM_SAT                                  0x3D6278
+
+#define mmNIF_RTR_CTRL_5_RL_HBM_RST                                  0x3D627C
+
+#define mmNIF_RTR_CTRL_5_RL_HBM_TIMEOUT                              0x3D6280
+
+#define mmNIF_RTR_CTRL_5_SCRAM_HBM_EN                                0x3D6284
+
+#define mmNIF_RTR_CTRL_5_RL_PCI_EN                                   0x3D6288
+
+#define mmNIF_RTR_CTRL_5_RL_PCI_SAT                                  0x3D628C
+
+#define mmNIF_RTR_CTRL_5_RL_PCI_RST                                  0x3D6290
+
+#define mmNIF_RTR_CTRL_5_RL_PCI_TIMEOUT                              0x3D6294
+
+#define mmNIF_RTR_CTRL_5_RL_SRAM_EN                                  0x3D629C
+
+#define mmNIF_RTR_CTRL_5_RL_SRAM_SAT                                 0x3D62A0
+
+#define mmNIF_RTR_CTRL_5_RL_SRAM_RST                                 0x3D62A4
+
+#define mmNIF_RTR_CTRL_5_RL_SRAM_TIMEOUT                             0x3D62AC
+
+#define mmNIF_RTR_CTRL_5_RL_SRAM_RED                                 0x3D62B4
+
+#define mmNIF_RTR_CTRL_5_E2E_HBM_EN                                  0x3D62EC
+
+#define mmNIF_RTR_CTRL_5_E2E_PCI_EN                                  0x3D62F0
+
+#define mmNIF_RTR_CTRL_5_E2E_HBM_WR_SIZE                             0x3D62F4
+
+#define mmNIF_RTR_CTRL_5_E2E_PCI_WR_SIZE                             0x3D62F8
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_PCI_CTR_SET_EN                       0x3D6404
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_PCI_CTR_SET                          0x3D6408
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_PCI_CTR_WRAP                         0x3D640C
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_PCI_CTR_CNT                          0x3D6410
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_HBM_CTR_SET_EN                       0x3D6414
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_HBM_CTR_SET                          0x3D6418
+
+#define mmNIF_RTR_CTRL_5_E2E_HBM_RD_SIZE                             0x3D641C
+
+#define mmNIF_RTR_CTRL_5_E2E_PCI_RD_SIZE                             0x3D6420
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_PCI_CTR_SET_EN                       0x3D6424
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_PCI_CTR_SET                          0x3D6428
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_PCI_CTR_WRAP                         0x3D642C
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_PCI_CTR_CNT                          0x3D6430
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_HBM_CTR_SET_EN                       0x3D6434
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_HBM_CTR_SET                          0x3D6438
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_SEL_0                                0x3D6450
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_SEL_1                                0x3D6454
+
+#define mmNIF_RTR_CTRL_5_NON_LIN_EN                                  0x3D6480
+
+#define mmNIF_RTR_CTRL_5_NL_SRAM_BANK_0                              0x3D6500
+
+#define mmNIF_RTR_CTRL_5_NL_SRAM_BANK_1                              0x3D6504
+
+#define mmNIF_RTR_CTRL_5_NL_SRAM_BANK_2                              0x3D6508
+
+#define mmNIF_RTR_CTRL_5_NL_SRAM_BANK_3                              0x3D650C
+
+#define mmNIF_RTR_CTRL_5_NL_SRAM_BANK_4                              0x3D6510
+
+#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_0                            0x3D6514
+
+#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_1                            0x3D6520
+
+#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_2                            0x3D6524
+
+#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_3                            0x3D6528
+
+#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_4                            0x3D652C
+
+#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_5                            0x3D6530
+
+#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_6                            0x3D6534
+
+#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_7                            0x3D6538
+
+#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_8                            0x3D653C
+
+#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_9                            0x3D6540
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_0                             0x3D6550
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_1                             0x3D6554
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_2                             0x3D6558
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_3                             0x3D655C
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_4                             0x3D6560
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_5                             0x3D6564
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_6                             0x3D6568
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_7                             0x3D656C
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_8                             0x3D6570
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_9                             0x3D6574
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_10                            0x3D6578
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_11                            0x3D657C
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_12                            0x3D6580
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_13                            0x3D6584
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_14                            0x3D6588
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_15                            0x3D658C
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_16                            0x3D6590
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_17                            0x3D6594
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_18                            0x3D6598
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_0                     0x3D65E4
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_1                     0x3D65E8
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_2                     0x3D65EC
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_3                     0x3D65F0
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_4                     0x3D65F4
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_5                     0x3D65F8
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_6                     0x3D65FC
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_7                     0x3D6600
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_8                     0x3D6604
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_9                     0x3D6608
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_10                    0x3D660C
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_11                    0x3D6610
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_12                    0x3D6614
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_13                    0x3D6618
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_14                    0x3D661C
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_15                    0x3D6620
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_0                    0x3D6624
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_1                    0x3D6628
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_2                    0x3D662C
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_3                    0x3D6630
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_4                    0x3D6634
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_5                    0x3D6638
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_6                    0x3D663C
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_7                    0x3D6640
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_8                    0x3D6644
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_9                    0x3D6648
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_10                   0x3D664C
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_11                   0x3D6650
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_12                   0x3D6654
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_13                   0x3D6658
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_14                   0x3D665C
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_15                   0x3D6660
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_0                     0x3D6664
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_1                     0x3D6668
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_2                     0x3D666C
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_3                     0x3D6670
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_4                     0x3D6674
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_5                     0x3D6678
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_6                     0x3D667C
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_7                     0x3D6680
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_8                     0x3D6684
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_9                     0x3D6688
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_10                    0x3D668C
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_11                    0x3D6690
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_12                    0x3D6694
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_13                    0x3D6698
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_14                    0x3D669C
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_15                    0x3D66A0
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_0                    0x3D66A4
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_1                    0x3D66A8
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_2                    0x3D66AC
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_3                    0x3D66B0
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_4                    0x3D66B4
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_5                    0x3D66B8
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_6                    0x3D66BC
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_7                    0x3D66C0
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_8                    0x3D66C4
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_9                    0x3D66C8
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_10                   0x3D66CC
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_11                   0x3D66D0
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_12                   0x3D66D4
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_13                   0x3D66D8
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_14                   0x3D66DC
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_15                   0x3D66E0
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_0                    0x3D66E4
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_1                    0x3D66E8
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_2                    0x3D66EC
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_3                    0x3D66F0
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_4                    0x3D66F4
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_5                    0x3D66F8
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_6                    0x3D66FC
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_7                    0x3D6700
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_8                    0x3D6704
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_9                    0x3D6708
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_10                   0x3D670C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_11                   0x3D6710
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_12                   0x3D6714
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_13                   0x3D6718
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_14                   0x3D671C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_15                   0x3D6720
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_0                   0x3D6724
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_1                   0x3D6728
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_2                   0x3D672C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_3                   0x3D6730
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_4                   0x3D6734
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_5                   0x3D6738
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_6                   0x3D673C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_7                   0x3D6740
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_8                   0x3D6744
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_9                   0x3D6748
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_10                  0x3D674C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_11                  0x3D6750
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_12                  0x3D6754
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_13                  0x3D6758
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_14                  0x3D675C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_15                  0x3D6760
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_0                    0x3D6764
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_1                    0x3D6768
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_2                    0x3D676C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_3                    0x3D6770
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_4                    0x3D6774
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_5                    0x3D6778
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_6                    0x3D677C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_7                    0x3D6780
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_8                    0x3D6784
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_9                    0x3D6788
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_10                   0x3D678C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_11                   0x3D6790
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_12                   0x3D6794
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_13                   0x3D6798
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_14                   0x3D679C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_15                   0x3D67A0
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_0                   0x3D67A4
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_1                   0x3D67A8
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_2                   0x3D67AC
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_3                   0x3D67B0
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_4                   0x3D67B4
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_5                   0x3D67B8
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_6                   0x3D67BC
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_7                   0x3D67C0
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_8                   0x3D67C4
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_9                   0x3D67C8
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_10                  0x3D67CC
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_11                  0x3D67D0
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_12                  0x3D67D4
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_13                  0x3D67D8
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_14                  0x3D67DC
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_15                  0x3D67E0
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_0                     0x3D6824
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_1                     0x3D6828
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_2                     0x3D682C
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_3                     0x3D6830
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_4                     0x3D6834
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_5                     0x3D6838
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_6                     0x3D683C
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_7                     0x3D6840
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_8                     0x3D6844
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_9                     0x3D6848
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_10                    0x3D684C
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_11                    0x3D6850
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_12                    0x3D6854
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_13                    0x3D6858
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_14                    0x3D685C
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_15                    0x3D6860
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_0                    0x3D6864
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_1                    0x3D6868
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_2                    0x3D686C
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_3                    0x3D6870
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_4                    0x3D6874
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_5                    0x3D6878
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_6                    0x3D687C
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_7                    0x3D6880
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_8                    0x3D6884
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_9                    0x3D6888
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_10                   0x3D688C
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_11                   0x3D6890
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_12                   0x3D6894
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_13                   0x3D6898
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_14                   0x3D689C
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_15                   0x3D68A0
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_0                     0x3D68A4
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_1                     0x3D68A8
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_2                     0x3D68AC
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_3                     0x3D68B0
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_4                     0x3D68B4
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_5                     0x3D68B8
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_6                     0x3D68BC
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_7                     0x3D68C0
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_8                     0x3D68C4
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_9                     0x3D68C8
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_10                    0x3D68CC
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_11                    0x3D68D0
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_12                    0x3D68D4
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_13                    0x3D68D8
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_14                    0x3D68DC
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_15                    0x3D68E0
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_0                    0x3D68E4
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_1                    0x3D68E8
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_2                    0x3D68EC
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_3                    0x3D68F0
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_4                    0x3D68F4
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_5                    0x3D68F8
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_6                    0x3D68FC
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_7                    0x3D6900
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_8                    0x3D6904
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_9                    0x3D6908
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_10                   0x3D690C
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_11                   0x3D6910
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_12                   0x3D6914
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_13                   0x3D6918
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_14                   0x3D691C
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_15                   0x3D6920
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_0                    0x3D6924
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_1                    0x3D6928
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_2                    0x3D692C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_3                    0x3D6930
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_4                    0x3D6934
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_5                    0x3D6938
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_6                    0x3D693C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_7                    0x3D6940
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_8                    0x3D6944
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_9                    0x3D6948
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_10                   0x3D694C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_11                   0x3D6950
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_12                   0x3D6954
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_13                   0x3D6958
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_14                   0x3D695C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_15                   0x3D6960
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_0                   0x3D6964
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_1                   0x3D6968
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_2                   0x3D696C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_3                   0x3D6970
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_4                   0x3D6974
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_5                   0x3D6978
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_6                   0x3D697C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_7                   0x3D6980
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_8                   0x3D6984
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_9                   0x3D6988
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_10                  0x3D698C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_11                  0x3D6990
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_12                  0x3D6994
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_13                  0x3D6998
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_14                  0x3D699C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_15                  0x3D69A0
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_0                    0x3D69A4
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_1                    0x3D69A8
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_2                    0x3D69AC
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_3                    0x3D69B0
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_4                    0x3D69B4
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_5                    0x3D69B8
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_6                    0x3D69BC
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_7                    0x3D69C0
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_8                    0x3D69C4
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_9                    0x3D69C8
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_10                   0x3D69CC
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_11                   0x3D69D0
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_12                   0x3D69D4
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_13                   0x3D69D8
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_14                   0x3D69DC
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_15                   0x3D69E0
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_0                   0x3D69E4
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_1                   0x3D69E8
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_2                   0x3D69EC
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_3                   0x3D69F0
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_4                   0x3D69F4
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_5                   0x3D69F8
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_6                   0x3D69FC
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_7                   0x3D6A00
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_8                   0x3D6A04
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_9                   0x3D6A08
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_10                  0x3D6A0C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_11                  0x3D6A10
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_12                  0x3D6A14
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_13                  0x3D6A18
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_14                  0x3D6A1C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_15                  0x3D6A20
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_HIT_AW                            0x3D6A64
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_HIT_AR                            0x3D6A68
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_HIT_AW                           0x3D6A6C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_HIT_AR                           0x3D6A70
+
+#define mmNIF_RTR_CTRL_5_RGL_CFG                                     0x3D6B64
+
+#define mmNIF_RTR_CTRL_5_RGL_SHIFT                                   0x3D6B68
+
+#define mmNIF_RTR_CTRL_5_RGL_EXPECTED_LAT_0                          0x3D6B6C
+
+#define mmNIF_RTR_CTRL_5_RGL_EXPECTED_LAT_1                          0x3D6B70
+
+#define mmNIF_RTR_CTRL_5_RGL_EXPECTED_LAT_2                          0x3D6B74
+
+#define mmNIF_RTR_CTRL_5_RGL_EXPECTED_LAT_3                          0x3D6B78
+
+#define mmNIF_RTR_CTRL_5_RGL_EXPECTED_LAT_4                          0x3D6B7C
+
+#define mmNIF_RTR_CTRL_5_RGL_EXPECTED_LAT_5                          0x3D6B80
+
+#define mmNIF_RTR_CTRL_5_RGL_EXPECTED_LAT_6                          0x3D6B84
+
+#define mmNIF_RTR_CTRL_5_RGL_EXPECTED_LAT_7                          0x3D6B88
+
+#define mmNIF_RTR_CTRL_5_RGL_TOKEN_0                                 0x3D6BAC
+
+#define mmNIF_RTR_CTRL_5_RGL_TOKEN_1                                 0x3D6BB0
+
+#define mmNIF_RTR_CTRL_5_RGL_TOKEN_2                                 0x3D6BB4
+
+#define mmNIF_RTR_CTRL_5_RGL_TOKEN_3                                 0x3D6BB8
+
+#define mmNIF_RTR_CTRL_5_RGL_TOKEN_4                                 0x3D6BBC
+
+#define mmNIF_RTR_CTRL_5_RGL_TOKEN_5                                 0x3D6BC0
+
+#define mmNIF_RTR_CTRL_5_RGL_TOKEN_6                                 0x3D6BC4
+
+#define mmNIF_RTR_CTRL_5_RGL_TOKEN_7                                 0x3D6BC8
+
+#define mmNIF_RTR_CTRL_5_RGL_BANK_ID_0                               0x3D6BEC
+
+#define mmNIF_RTR_CTRL_5_RGL_BANK_ID_1                               0x3D6BF0
+
+#define mmNIF_RTR_CTRL_5_RGL_BANK_ID_2                               0x3D6BF4
+
+#define mmNIF_RTR_CTRL_5_RGL_BANK_ID_3                               0x3D6BF8
+
+#define mmNIF_RTR_CTRL_5_RGL_BANK_ID_4                               0x3D6BFC
+
+#define mmNIF_RTR_CTRL_5_RGL_BANK_ID_5                               0x3D6C00
+
+#define mmNIF_RTR_CTRL_5_RGL_BANK_ID_6                               0x3D6C04
+
+#define mmNIF_RTR_CTRL_5_RGL_BANK_ID_7                               0x3D6C08
+
+#define mmNIF_RTR_CTRL_5_RGL_WDT                                     0x3D6C2C
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_HBM0_CH0_CTR_WRAP                    0x3D6C30
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_HBM0_CH1_CTR_WRAP                    0x3D6C34
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_HBM1_CH0_CTR_WRAP                    0x3D6C38
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_HBM1_CH1_CTR_WRAP                    0x3D6C3C
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_HBM2_CH0_CTR_WRAP                    0x3D6C40
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_HBM2_CH1_CTR_WRAP                    0x3D6C44
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_HBM3_CH0_CTR_WRAP                    0x3D6C48
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_HBM3_CH1_CTR_WRAP                    0x3D6C4C
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_HBM0_CH0_CTR_CNT                     0x3D6C50
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_HBM0_CH1_CTR_CNT                     0x3D6C54
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_HBM1_CH0_CTR_CNT                     0x3D6C58
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_HBM1_CH1_CTR_CNT                     0x3D6C5C
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_HBM2_CH0_CTR_CNT                     0x3D6C60
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_HBM2_CH1_CTR_CNT                     0x3D6C64
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_HBM3_CH0_CTR_CNT                     0x3D6C68
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_HBM3_CH1_CTR_CNT                     0x3D6C6C
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_HBM0_CH0_CTR_WRAP                    0x3D6C70
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_HBM0_CH1_CTR_WRAP                    0x3D6C74
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_HBM1_CH0_CTR_WRAP                    0x3D6C78
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_HBM1_CH1_CTR_WRAP                    0x3D6C7C
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_HBM2_CH0_CTR_WRAP                    0x3D6C80
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_HBM2_CH1_CTR_WRAP                    0x3D6C84
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_HBM3_CH0_CTR_WRAP                    0x3D6C88
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_HBM3_CH1_CTR_WRAP                    0x3D6C8C
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_HBM0_CH0_CTR_CNT                     0x3D6C90
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_HBM0_CH1_CTR_CNT                     0x3D6C94
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_HBM1_CH0_CTR_CNT                     0x3D6C98
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_HBM1_CH1_CTR_CNT                     0x3D6C9C
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_HBM2_CH0_CTR_CNT                     0x3D6CA0
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_HBM2_CH1_CTR_CNT                     0x3D6CA4
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_HBM3_CH0_CTR_CNT                     0x3D6CA8
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_HBM3_CH1_CTR_CNT                     0x3D6CAC
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_PC_SEL_0                             0x3D6CB0
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_PC_SEL_1                             0x3D6CB4
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_PC_SEL_2                             0x3D6CB8
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_PC_SEL_3                             0x3D6CBC
+
+#endif /* ASIC_REG_NIF_RTR_CTRL_5_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_6_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_6_regs.h
new file mode 100644
index 000000000000..b79c59887b21
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_6_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_NIF_RTR_CTRL_6_REGS_H_
+#define ASIC_REG_NIF_RTR_CTRL_6_REGS_H_
+
+/*
+ *****************************************
+ *   NIF_RTR_CTRL_6 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmNIF_RTR_CTRL_6_PERM_SEL                                    0x3E6108
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_0                               0x3E6114
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_1                               0x3E6118
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_2                               0x3E611C
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_3                               0x3E6120
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_4                               0x3E6124
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_5                               0x3E6128
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_6                               0x3E612C
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_7                               0x3E6130
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_8                               0x3E6134
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_9                               0x3E6138
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_10                              0x3E613C
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_11                              0x3E6140
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_12                              0x3E6144
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_13                              0x3E6148
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_14                              0x3E614C
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_15                              0x3E6150
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_16                              0x3E6154
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_17                              0x3E6158
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_18                              0x3E615C
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_19                              0x3E6160
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_20                              0x3E6164
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_21                              0x3E6168
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_22                              0x3E616C
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_23                              0x3E6170
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_24                              0x3E6174
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_25                              0x3E6178
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_26                              0x3E617C
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_27                              0x3E6180
+
+#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_0                              0x3E6184
+
+#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_1                              0x3E6188
+
+#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_2                              0x3E618C
+
+#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_3                              0x3E6190
+
+#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_4                              0x3E6194
+
+#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_5                              0x3E6198
+
+#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_6                              0x3E619C
+
+#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_7                              0x3E61A0
+
+#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_8                              0x3E61A4
+
+#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_9                              0x3E61A8
+
+#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_10                             0x3E61AC
+
+#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_11                             0x3E61B0
+
+#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_12                             0x3E61B4
+
+#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_13                             0x3E61B8
+
+#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_14                             0x3E61BC
+
+#define mmNIF_RTR_CTRL_6_SCRAM_SRAM_EN                               0x3E626C
+
+#define mmNIF_RTR_CTRL_6_RL_HBM_EN                                   0x3E6274
+
+#define mmNIF_RTR_CTRL_6_RL_HBM_SAT                                  0x3E6278
+
+#define mmNIF_RTR_CTRL_6_RL_HBM_RST                                  0x3E627C
+
+#define mmNIF_RTR_CTRL_6_RL_HBM_TIMEOUT                              0x3E6280
+
+#define mmNIF_RTR_CTRL_6_SCRAM_HBM_EN                                0x3E6284
+
+#define mmNIF_RTR_CTRL_6_RL_PCI_EN                                   0x3E6288
+
+#define mmNIF_RTR_CTRL_6_RL_PCI_SAT                                  0x3E628C
+
+#define mmNIF_RTR_CTRL_6_RL_PCI_RST                                  0x3E6290
+
+#define mmNIF_RTR_CTRL_6_RL_PCI_TIMEOUT                              0x3E6294
+
+#define mmNIF_RTR_CTRL_6_RL_SRAM_EN                                  0x3E629C
+
+#define mmNIF_RTR_CTRL_6_RL_SRAM_SAT                                 0x3E62A0
+
+#define mmNIF_RTR_CTRL_6_RL_SRAM_RST                                 0x3E62A4
+
+#define mmNIF_RTR_CTRL_6_RL_SRAM_TIMEOUT                             0x3E62AC
+
+#define mmNIF_RTR_CTRL_6_RL_SRAM_RED                                 0x3E62B4
+
+#define mmNIF_RTR_CTRL_6_E2E_HBM_EN                                  0x3E62EC
+
+#define mmNIF_RTR_CTRL_6_E2E_PCI_EN                                  0x3E62F0
+
+#define mmNIF_RTR_CTRL_6_E2E_HBM_WR_SIZE                             0x3E62F4
+
+#define mmNIF_RTR_CTRL_6_E2E_PCI_WR_SIZE                             0x3E62F8
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_PCI_CTR_SET_EN                       0x3E6404
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_PCI_CTR_SET                          0x3E6408
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_PCI_CTR_WRAP                         0x3E640C
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_PCI_CTR_CNT                          0x3E6410
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_HBM_CTR_SET_EN                       0x3E6414
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_HBM_CTR_SET                          0x3E6418
+
+#define mmNIF_RTR_CTRL_6_E2E_HBM_RD_SIZE                             0x3E641C
+
+#define mmNIF_RTR_CTRL_6_E2E_PCI_RD_SIZE                             0x3E6420
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_PCI_CTR_SET_EN                       0x3E6424
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_PCI_CTR_SET                          0x3E6428
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_PCI_CTR_WRAP                         0x3E642C
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_PCI_CTR_CNT                          0x3E6430
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_HBM_CTR_SET_EN                       0x3E6434
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_HBM_CTR_SET                          0x3E6438
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_SEL_0                                0x3E6450
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_SEL_1                                0x3E6454
+
+#define mmNIF_RTR_CTRL_6_NON_LIN_EN                                  0x3E6480
+
+#define mmNIF_RTR_CTRL_6_NL_SRAM_BANK_0                              0x3E6500
+
+#define mmNIF_RTR_CTRL_6_NL_SRAM_BANK_1                              0x3E6504
+
+#define mmNIF_RTR_CTRL_6_NL_SRAM_BANK_2                              0x3E6508
+
+#define mmNIF_RTR_CTRL_6_NL_SRAM_BANK_3                              0x3E650C
+
+#define mmNIF_RTR_CTRL_6_NL_SRAM_BANK_4                              0x3E6510
+
+#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_0                            0x3E6514
+
+#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_1                            0x3E6520
+
+#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_2                            0x3E6524
+
+#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_3                            0x3E6528
+
+#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_4                            0x3E652C
+
+#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_5                            0x3E6530
+
+#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_6                            0x3E6534
+
+#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_7                            0x3E6538
+
+#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_8                            0x3E653C
+
+#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_9                            0x3E6540
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_0                             0x3E6550
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_1                             0x3E6554
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_2                             0x3E6558
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_3                             0x3E655C
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_4                             0x3E6560
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_5                             0x3E6564
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_6                             0x3E6568
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_7                             0x3E656C
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_8                             0x3E6570
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_9                             0x3E6574
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_10                            0x3E6578
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_11                            0x3E657C
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_12                            0x3E6580
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_13                            0x3E6584
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_14                            0x3E6588
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_15                            0x3E658C
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_16                            0x3E6590
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_17                            0x3E6594
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_18                            0x3E6598
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_0                     0x3E65E4
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_1                     0x3E65E8
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_2                     0x3E65EC
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_3                     0x3E65F0
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_4                     0x3E65F4
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_5                     0x3E65F8
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_6                     0x3E65FC
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_7                     0x3E6600
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_8                     0x3E6604
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_9                     0x3E6608
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_10                    0x3E660C
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_11                    0x3E6610
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_12                    0x3E6614
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_13                    0x3E6618
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_14                    0x3E661C
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_15                    0x3E6620
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_0                    0x3E6624
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_1                    0x3E6628
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_2                    0x3E662C
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_3                    0x3E6630
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_4                    0x3E6634
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_5                    0x3E6638
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_6                    0x3E663C
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_7                    0x3E6640
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_8                    0x3E6644
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_9                    0x3E6648
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_10                   0x3E664C
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_11                   0x3E6650
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_12                   0x3E6654
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_13                   0x3E6658
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_14                   0x3E665C
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_15                   0x3E6660
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_0                     0x3E6664
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_1                     0x3E6668
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_2                     0x3E666C
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_3                     0x3E6670
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_4                     0x3E6674
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_5                     0x3E6678
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_6                     0x3E667C
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_7                     0x3E6680
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_8                     0x3E6684
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_9                     0x3E6688
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_10                    0x3E668C
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_11                    0x3E6690
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_12                    0x3E6694
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_13                    0x3E6698
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_14                    0x3E669C
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_15                    0x3E66A0
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_0                    0x3E66A4
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_1                    0x3E66A8
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_2                    0x3E66AC
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_3                    0x3E66B0
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_4                    0x3E66B4
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_5                    0x3E66B8
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_6                    0x3E66BC
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_7                    0x3E66C0
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_8                    0x3E66C4
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_9                    0x3E66C8
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_10                   0x3E66CC
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_11                   0x3E66D0
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_12                   0x3E66D4
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_13                   0x3E66D8
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_14                   0x3E66DC
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_15                   0x3E66E0
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_0                    0x3E66E4
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_1                    0x3E66E8
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_2                    0x3E66EC
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_3                    0x3E66F0
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_4                    0x3E66F4
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_5                    0x3E66F8
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_6                    0x3E66FC
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_7                    0x3E6700
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_8                    0x3E6704
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_9                    0x3E6708
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_10                   0x3E670C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_11                   0x3E6710
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_12                   0x3E6714
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_13                   0x3E6718
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_14                   0x3E671C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_15                   0x3E6720
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_0                   0x3E6724
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_1                   0x3E6728
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_2                   0x3E672C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_3                   0x3E6730
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_4                   0x3E6734
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_5                   0x3E6738
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_6                   0x3E673C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_7                   0x3E6740
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_8                   0x3E6744
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_9                   0x3E6748
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_10                  0x3E674C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_11                  0x3E6750
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_12                  0x3E6754
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_13                  0x3E6758
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_14                  0x3E675C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_15                  0x3E6760
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_0                    0x3E6764
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_1                    0x3E6768
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_2                    0x3E676C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_3                    0x3E6770
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_4                    0x3E6774
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_5                    0x3E6778
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_6                    0x3E677C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_7                    0x3E6780
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_8                    0x3E6784
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_9                    0x3E6788
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_10                   0x3E678C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_11                   0x3E6790
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_12                   0x3E6794
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_13                   0x3E6798
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_14                   0x3E679C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_15                   0x3E67A0
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_0                   0x3E67A4
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_1                   0x3E67A8
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_2                   0x3E67AC
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_3                   0x3E67B0
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_4                   0x3E67B4
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_5                   0x3E67B8
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_6                   0x3E67BC
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_7                   0x3E67C0
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_8                   0x3E67C4
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_9                   0x3E67C8
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_10                  0x3E67CC
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_11                  0x3E67D0
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_12                  0x3E67D4
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_13                  0x3E67D8
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_14                  0x3E67DC
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_15                  0x3E67E0
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_0                     0x3E6824
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_1                     0x3E6828
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_2                     0x3E682C
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_3                     0x3E6830
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_4                     0x3E6834
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_5                     0x3E6838
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_6                     0x3E683C
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_7                     0x3E6840
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_8                     0x3E6844
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_9                     0x3E6848
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_10                    0x3E684C
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_11                    0x3E6850
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_12                    0x3E6854
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_13                    0x3E6858
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_14                    0x3E685C
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_15                    0x3E6860
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_0                    0x3E6864
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_1                    0x3E6868
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_2                    0x3E686C
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_3                    0x3E6870
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_4                    0x3E6874
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_5                    0x3E6878
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_6                    0x3E687C
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_7                    0x3E6880
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_8                    0x3E6884
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_9                    0x3E6888
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_10                   0x3E688C
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_11                   0x3E6890
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_12                   0x3E6894
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_13                   0x3E6898
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_14                   0x3E689C
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_15                   0x3E68A0
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_0                     0x3E68A4
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_1                     0x3E68A8
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_2                     0x3E68AC
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_3                     0x3E68B0
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_4                     0x3E68B4
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_5                     0x3E68B8
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_6                     0x3E68BC
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_7                     0x3E68C0
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_8                     0x3E68C4
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_9                     0x3E68C8
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_10                    0x3E68CC
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_11                    0x3E68D0
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_12                    0x3E68D4
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_13                    0x3E68D8
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_14                    0x3E68DC
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_15                    0x3E68E0
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_0                    0x3E68E4
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_1                    0x3E68E8
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_2                    0x3E68EC
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_3                    0x3E68F0
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_4                    0x3E68F4
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_5                    0x3E68F8
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_6                    0x3E68FC
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_7                    0x3E6900
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_8                    0x3E6904
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_9                    0x3E6908
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_10                   0x3E690C
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_11                   0x3E6910
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_12                   0x3E6914
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_13                   0x3E6918
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_14                   0x3E691C
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_15                   0x3E6920
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_0                    0x3E6924
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_1                    0x3E6928
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_2                    0x3E692C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_3                    0x3E6930
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_4                    0x3E6934
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_5                    0x3E6938
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_6                    0x3E693C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_7                    0x3E6940
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_8                    0x3E6944
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_9                    0x3E6948
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_10                   0x3E694C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_11                   0x3E6950
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_12                   0x3E6954
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_13                   0x3E6958
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_14                   0x3E695C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_15                   0x3E6960
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_0                   0x3E6964
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_1                   0x3E6968
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_2                   0x3E696C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_3                   0x3E6970
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_4                   0x3E6974
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_5                   0x3E6978
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_6                   0x3E697C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_7                   0x3E6980
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_8                   0x3E6984
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_9                   0x3E6988
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_10                  0x3E698C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_11                  0x3E6990
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_12                  0x3E6994
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_13                  0x3E6998
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_14                  0x3E699C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_15                  0x3E69A0
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_0                    0x3E69A4
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_1                    0x3E69A8
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_2                    0x3E69AC
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_3                    0x3E69B0
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_4                    0x3E69B4
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_5                    0x3E69B8
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_6                    0x3E69BC
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_7                    0x3E69C0
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_8                    0x3E69C4
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_9                    0x3E69C8
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_10                   0x3E69CC
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_11                   0x3E69D0
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_12                   0x3E69D4
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_13                   0x3E69D8
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_14                   0x3E69DC
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_15                   0x3E69E0
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_0                   0x3E69E4
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_1                   0x3E69E8
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_2                   0x3E69EC
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_3                   0x3E69F0
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_4                   0x3E69F4
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_5                   0x3E69F8
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_6                   0x3E69FC
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_7                   0x3E6A00
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_8                   0x3E6A04
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_9                   0x3E6A08
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_10                  0x3E6A0C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_11                  0x3E6A10
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_12                  0x3E6A14
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_13                  0x3E6A18
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_14                  0x3E6A1C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_15                  0x3E6A20
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_HIT_AW                            0x3E6A64
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_HIT_AR                            0x3E6A68
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_HIT_AW                           0x3E6A6C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_HIT_AR                           0x3E6A70
+
+#define mmNIF_RTR_CTRL_6_RGL_CFG                                     0x3E6B64
+
+#define mmNIF_RTR_CTRL_6_RGL_SHIFT                                   0x3E6B68
+
+#define mmNIF_RTR_CTRL_6_RGL_EXPECTED_LAT_0                          0x3E6B6C
+
+#define mmNIF_RTR_CTRL_6_RGL_EXPECTED_LAT_1                          0x3E6B70
+
+#define mmNIF_RTR_CTRL_6_RGL_EXPECTED_LAT_2                          0x3E6B74
+
+#define mmNIF_RTR_CTRL_6_RGL_EXPECTED_LAT_3                          0x3E6B78
+
+#define mmNIF_RTR_CTRL_6_RGL_EXPECTED_LAT_4                          0x3E6B7C
+
+#define mmNIF_RTR_CTRL_6_RGL_EXPECTED_LAT_5                          0x3E6B80
+
+#define mmNIF_RTR_CTRL_6_RGL_EXPECTED_LAT_6                          0x3E6B84
+
+#define mmNIF_RTR_CTRL_6_RGL_EXPECTED_LAT_7                          0x3E6B88
+
+#define mmNIF_RTR_CTRL_6_RGL_TOKEN_0                                 0x3E6BAC
+
+#define mmNIF_RTR_CTRL_6_RGL_TOKEN_1                                 0x3E6BB0
+
+#define mmNIF_RTR_CTRL_6_RGL_TOKEN_2                                 0x3E6BB4
+
+#define mmNIF_RTR_CTRL_6_RGL_TOKEN_3                                 0x3E6BB8
+
+#define mmNIF_RTR_CTRL_6_RGL_TOKEN_4                                 0x3E6BBC
+
+#define mmNIF_RTR_CTRL_6_RGL_TOKEN_5                                 0x3E6BC0
+
+#define mmNIF_RTR_CTRL_6_RGL_TOKEN_6                                 0x3E6BC4
+
+#define mmNIF_RTR_CTRL_6_RGL_TOKEN_7                                 0x3E6BC8
+
+#define mmNIF_RTR_CTRL_6_RGL_BANK_ID_0                               0x3E6BEC
+
+#define mmNIF_RTR_CTRL_6_RGL_BANK_ID_1                               0x3E6BF0
+
+#define mmNIF_RTR_CTRL_6_RGL_BANK_ID_2                               0x3E6BF4
+
+#define mmNIF_RTR_CTRL_6_RGL_BANK_ID_3                               0x3E6BF8
+
+#define mmNIF_RTR_CTRL_6_RGL_BANK_ID_4                               0x3E6BFC
+
+#define mmNIF_RTR_CTRL_6_RGL_BANK_ID_5                               0x3E6C00
+
+#define mmNIF_RTR_CTRL_6_RGL_BANK_ID_6                               0x3E6C04
+
+#define mmNIF_RTR_CTRL_6_RGL_BANK_ID_7                               0x3E6C08
+
+#define mmNIF_RTR_CTRL_6_RGL_WDT                                     0x3E6C2C
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_HBM0_CH0_CTR_WRAP                    0x3E6C30
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_HBM0_CH1_CTR_WRAP                    0x3E6C34
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_HBM1_CH0_CTR_WRAP                    0x3E6C38
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_HBM1_CH1_CTR_WRAP                    0x3E6C3C
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_HBM2_CH0_CTR_WRAP                    0x3E6C40
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_HBM2_CH1_CTR_WRAP                    0x3E6C44
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_HBM3_CH0_CTR_WRAP                    0x3E6C48
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_HBM3_CH1_CTR_WRAP                    0x3E6C4C
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_HBM0_CH0_CTR_CNT                     0x3E6C50
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_HBM0_CH1_CTR_CNT                     0x3E6C54
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_HBM1_CH0_CTR_CNT                     0x3E6C58
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_HBM1_CH1_CTR_CNT                     0x3E6C5C
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_HBM2_CH0_CTR_CNT                     0x3E6C60
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_HBM2_CH1_CTR_CNT                     0x3E6C64
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_HBM3_CH0_CTR_CNT                     0x3E6C68
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_HBM3_CH1_CTR_CNT                     0x3E6C6C
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_HBM0_CH0_CTR_WRAP                    0x3E6C70
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_HBM0_CH1_CTR_WRAP                    0x3E6C74
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_HBM1_CH0_CTR_WRAP                    0x3E6C78
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_HBM1_CH1_CTR_WRAP                    0x3E6C7C
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_HBM2_CH0_CTR_WRAP                    0x3E6C80
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_HBM2_CH1_CTR_WRAP                    0x3E6C84
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_HBM3_CH0_CTR_WRAP                    0x3E6C88
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_HBM3_CH1_CTR_WRAP                    0x3E6C8C
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_HBM0_CH0_CTR_CNT                     0x3E6C90
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_HBM0_CH1_CTR_CNT                     0x3E6C94
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_HBM1_CH0_CTR_CNT                     0x3E6C98
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_HBM1_CH1_CTR_CNT                     0x3E6C9C
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_HBM2_CH0_CTR_CNT                     0x3E6CA0
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_HBM2_CH1_CTR_CNT                     0x3E6CA4
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_HBM3_CH0_CTR_CNT                     0x3E6CA8
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_HBM3_CH1_CTR_CNT                     0x3E6CAC
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_PC_SEL_0                             0x3E6CB0
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_PC_SEL_1                             0x3E6CB4
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_PC_SEL_2                             0x3E6CB8
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_PC_SEL_3                             0x3E6CBC
+
+#endif /* ASIC_REG_NIF_RTR_CTRL_6_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_7_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_7_regs.h
new file mode 100644
index 000000000000..3a6a34ba2958
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_7_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_NIF_RTR_CTRL_7_REGS_H_
+#define ASIC_REG_NIF_RTR_CTRL_7_REGS_H_
+
+/*
+ *****************************************
+ *   NIF_RTR_CTRL_7 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmNIF_RTR_CTRL_7_PERM_SEL                                    0x3F6108
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_0                               0x3F6114
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_1                               0x3F6118
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_2                               0x3F611C
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_3                               0x3F6120
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_4                               0x3F6124
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_5                               0x3F6128
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_6                               0x3F612C
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_7                               0x3F6130
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_8                               0x3F6134
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_9                               0x3F6138
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_10                              0x3F613C
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_11                              0x3F6140
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_12                              0x3F6144
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_13                              0x3F6148
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_14                              0x3F614C
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_15                              0x3F6150
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_16                              0x3F6154
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_17                              0x3F6158
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_18                              0x3F615C
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_19                              0x3F6160
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_20                              0x3F6164
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_21                              0x3F6168
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_22                              0x3F616C
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_23                              0x3F6170
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_24                              0x3F6174
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_25                              0x3F6178
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_26                              0x3F617C
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_27                              0x3F6180
+
+#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_0                              0x3F6184
+
+#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_1                              0x3F6188
+
+#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_2                              0x3F618C
+
+#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_3                              0x3F6190
+
+#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_4                              0x3F6194
+
+#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_5                              0x3F6198
+
+#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_6                              0x3F619C
+
+#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_7                              0x3F61A0
+
+#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_8                              0x3F61A4
+
+#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_9                              0x3F61A8
+
+#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_10                             0x3F61AC
+
+#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_11                             0x3F61B0
+
+#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_12                             0x3F61B4
+
+#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_13                             0x3F61B8
+
+#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_14                             0x3F61BC
+
+#define mmNIF_RTR_CTRL_7_SCRAM_SRAM_EN                               0x3F626C
+
+#define mmNIF_RTR_CTRL_7_RL_HBM_EN                                   0x3F6274
+
+#define mmNIF_RTR_CTRL_7_RL_HBM_SAT                                  0x3F6278
+
+#define mmNIF_RTR_CTRL_7_RL_HBM_RST                                  0x3F627C
+
+#define mmNIF_RTR_CTRL_7_RL_HBM_TIMEOUT                              0x3F6280
+
+#define mmNIF_RTR_CTRL_7_SCRAM_HBM_EN                                0x3F6284
+
+#define mmNIF_RTR_CTRL_7_RL_PCI_EN                                   0x3F6288
+
+#define mmNIF_RTR_CTRL_7_RL_PCI_SAT                                  0x3F628C
+
+#define mmNIF_RTR_CTRL_7_RL_PCI_RST                                  0x3F6290
+
+#define mmNIF_RTR_CTRL_7_RL_PCI_TIMEOUT                              0x3F6294
+
+#define mmNIF_RTR_CTRL_7_RL_SRAM_EN                                  0x3F629C
+
+#define mmNIF_RTR_CTRL_7_RL_SRAM_SAT                                 0x3F62A0
+
+#define mmNIF_RTR_CTRL_7_RL_SRAM_RST                                 0x3F62A4
+
+#define mmNIF_RTR_CTRL_7_RL_SRAM_TIMEOUT                             0x3F62AC
+
+#define mmNIF_RTR_CTRL_7_RL_SRAM_RED                                 0x3F62B4
+
+#define mmNIF_RTR_CTRL_7_E2E_HBM_EN                                  0x3F62EC
+
+#define mmNIF_RTR_CTRL_7_E2E_PCI_EN                                  0x3F62F0
+
+#define mmNIF_RTR_CTRL_7_E2E_HBM_WR_SIZE                             0x3F62F4
+
+#define mmNIF_RTR_CTRL_7_E2E_PCI_WR_SIZE                             0x3F62F8
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_PCI_CTR_SET_EN                       0x3F6404
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_PCI_CTR_SET                          0x3F6408
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_PCI_CTR_WRAP                         0x3F640C
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_PCI_CTR_CNT                          0x3F6410
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_HBM_CTR_SET_EN                       0x3F6414
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_HBM_CTR_SET                          0x3F6418
+
+#define mmNIF_RTR_CTRL_7_E2E_HBM_RD_SIZE                             0x3F641C
+
+#define mmNIF_RTR_CTRL_7_E2E_PCI_RD_SIZE                             0x3F6420
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_PCI_CTR_SET_EN                       0x3F6424
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_PCI_CTR_SET                          0x3F6428
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_PCI_CTR_WRAP                         0x3F642C
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_PCI_CTR_CNT                          0x3F6430
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_HBM_CTR_SET_EN                       0x3F6434
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_HBM_CTR_SET                          0x3F6438
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_SEL_0                                0x3F6450
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_SEL_1                                0x3F6454
+
+#define mmNIF_RTR_CTRL_7_NON_LIN_EN                                  0x3F6480
+
+#define mmNIF_RTR_CTRL_7_NL_SRAM_BANK_0                              0x3F6500
+
+#define mmNIF_RTR_CTRL_7_NL_SRAM_BANK_1                              0x3F6504
+
+#define mmNIF_RTR_CTRL_7_NL_SRAM_BANK_2                              0x3F6508
+
+#define mmNIF_RTR_CTRL_7_NL_SRAM_BANK_3                              0x3F650C
+
+#define mmNIF_RTR_CTRL_7_NL_SRAM_BANK_4                              0x3F6510
+
+#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_0                            0x3F6514
+
+#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_1                            0x3F6520
+
+#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_2                            0x3F6524
+
+#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_3                            0x3F6528
+
+#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_4                            0x3F652C
+
+#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_5                            0x3F6530
+
+#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_6                            0x3F6534
+
+#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_7                            0x3F6538
+
+#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_8                            0x3F653C
+
+#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_9                            0x3F6540
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_0                             0x3F6550
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_1                             0x3F6554
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_2                             0x3F6558
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_3                             0x3F655C
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_4                             0x3F6560
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_5                             0x3F6564
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_6                             0x3F6568
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_7                             0x3F656C
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_8                             0x3F6570
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_9                             0x3F6574
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_10                            0x3F6578
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_11                            0x3F657C
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_12                            0x3F6580
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_13                            0x3F6584
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_14                            0x3F6588
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_15                            0x3F658C
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_16                            0x3F6590
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_17                            0x3F6594
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_18                            0x3F6598
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_0                     0x3F65E4
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_1                     0x3F65E8
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_2                     0x3F65EC
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_3                     0x3F65F0
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_4                     0x3F65F4
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_5                     0x3F65F8
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_6                     0x3F65FC
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_7                     0x3F6600
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_8                     0x3F6604
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_9                     0x3F6608
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_10                    0x3F660C
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_11                    0x3F6610
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_12                    0x3F6614
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_13                    0x3F6618
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_14                    0x3F661C
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_15                    0x3F6620
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_0                    0x3F6624
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_1                    0x3F6628
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_2                    0x3F662C
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_3                    0x3F6630
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_4                    0x3F6634
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_5                    0x3F6638
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_6                    0x3F663C
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_7                    0x3F6640
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_8                    0x3F6644
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_9                    0x3F6648
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_10                   0x3F664C
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_11                   0x3F6650
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_12                   0x3F6654
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_13                   0x3F6658
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_14                   0x3F665C
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_15                   0x3F6660
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_0                     0x3F6664
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_1                     0x3F6668
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_2                     0x3F666C
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_3                     0x3F6670
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_4                     0x3F6674
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_5                     0x3F6678
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_6                     0x3F667C
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_7                     0x3F6680
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_8                     0x3F6684
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_9                     0x3F6688
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_10                    0x3F668C
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_11                    0x3F6690
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_12                    0x3F6694
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_13                    0x3F6698
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_14                    0x3F669C
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_15                    0x3F66A0
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_0                    0x3F66A4
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_1                    0x3F66A8
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_2                    0x3F66AC
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_3                    0x3F66B0
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_4                    0x3F66B4
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_5                    0x3F66B8
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_6                    0x3F66BC
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_7                    0x3F66C0
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_8                    0x3F66C4
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_9                    0x3F66C8
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_10                   0x3F66CC
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_11                   0x3F66D0
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_12                   0x3F66D4
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_13                   0x3F66D8
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_14                   0x3F66DC
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_15                   0x3F66E0
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_0                    0x3F66E4
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_1                    0x3F66E8
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_2                    0x3F66EC
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_3                    0x3F66F0
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_4                    0x3F66F4
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_5                    0x3F66F8
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_6                    0x3F66FC
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_7                    0x3F6700
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_8                    0x3F6704
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_9                    0x3F6708
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_10                   0x3F670C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_11                   0x3F6710
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_12                   0x3F6714
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_13                   0x3F6718
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_14                   0x3F671C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_15                   0x3F6720
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_0                   0x3F6724
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_1                   0x3F6728
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_2                   0x3F672C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_3                   0x3F6730
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_4                   0x3F6734
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_5                   0x3F6738
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_6                   0x3F673C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_7                   0x3F6740
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_8                   0x3F6744
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_9                   0x3F6748
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_10                  0x3F674C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_11                  0x3F6750
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_12                  0x3F6754
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_13                  0x3F6758
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_14                  0x3F675C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_15                  0x3F6760
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_0                    0x3F6764
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_1                    0x3F6768
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_2                    0x3F676C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_3                    0x3F6770
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_4                    0x3F6774
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_5                    0x3F6778
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_6                    0x3F677C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_7                    0x3F6780
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_8                    0x3F6784
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_9                    0x3F6788
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_10                   0x3F678C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_11                   0x3F6790
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_12                   0x3F6794
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_13                   0x3F6798
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_14                   0x3F679C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_15                   0x3F67A0
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_0                   0x3F67A4
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_1                   0x3F67A8
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_2                   0x3F67AC
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_3                   0x3F67B0
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_4                   0x3F67B4
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_5                   0x3F67B8
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_6                   0x3F67BC
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_7                   0x3F67C0
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_8                   0x3F67C4
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_9                   0x3F67C8
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_10                  0x3F67CC
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_11                  0x3F67D0
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_12                  0x3F67D4
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_13                  0x3F67D8
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_14                  0x3F67DC
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_15                  0x3F67E0
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_0                     0x3F6824
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_1                     0x3F6828
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_2                     0x3F682C
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_3                     0x3F6830
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_4                     0x3F6834
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_5                     0x3F6838
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_6                     0x3F683C
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_7                     0x3F6840
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_8                     0x3F6844
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_9                     0x3F6848
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_10                    0x3F684C
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_11                    0x3F6850
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_12                    0x3F6854
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_13                    0x3F6858
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_14                    0x3F685C
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_15                    0x3F6860
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_0                    0x3F6864
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_1                    0x3F6868
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_2                    0x3F686C
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_3                    0x3F6870
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_4                    0x3F6874
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_5                    0x3F6878
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_6                    0x3F687C
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_7                    0x3F6880
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_8                    0x3F6884
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_9                    0x3F6888
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_10                   0x3F688C
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_11                   0x3F6890
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_12                   0x3F6894
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_13                   0x3F6898
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_14                   0x3F689C
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_15                   0x3F68A0
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_0                     0x3F68A4
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_1                     0x3F68A8
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_2                     0x3F68AC
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_3                     0x3F68B0
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_4                     0x3F68B4
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_5                     0x3F68B8
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_6                     0x3F68BC
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_7                     0x3F68C0
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_8                     0x3F68C4
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_9                     0x3F68C8
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_10                    0x3F68CC
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_11                    0x3F68D0
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_12                    0x3F68D4
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_13                    0x3F68D8
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_14                    0x3F68DC
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_15                    0x3F68E0
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_0                    0x3F68E4
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_1                    0x3F68E8
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_2                    0x3F68EC
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_3                    0x3F68F0
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_4                    0x3F68F4
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_5                    0x3F68F8
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_6                    0x3F68FC
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_7                    0x3F6900
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_8                    0x3F6904
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_9                    0x3F6908
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_10                   0x3F690C
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_11                   0x3F6910
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_12                   0x3F6914
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_13                   0x3F6918
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_14                   0x3F691C
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_15                   0x3F6920
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_0                    0x3F6924
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_1                    0x3F6928
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_2                    0x3F692C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_3                    0x3F6930
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_4                    0x3F6934
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_5                    0x3F6938
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_6                    0x3F693C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_7                    0x3F6940
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_8                    0x3F6944
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_9                    0x3F6948
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_10                   0x3F694C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_11                   0x3F6950
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_12                   0x3F6954
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_13                   0x3F6958
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_14                   0x3F695C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_15                   0x3F6960
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_0                   0x3F6964
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_1                   0x3F6968
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_2                   0x3F696C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_3                   0x3F6970
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_4                   0x3F6974
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_5                   0x3F6978
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_6                   0x3F697C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_7                   0x3F6980
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_8                   0x3F6984
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_9                   0x3F6988
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_10                  0x3F698C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_11                  0x3F6990
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_12                  0x3F6994
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_13                  0x3F6998
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_14                  0x3F699C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_15                  0x3F69A0
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_0                    0x3F69A4
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_1                    0x3F69A8
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_2                    0x3F69AC
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_3                    0x3F69B0
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_4                    0x3F69B4
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_5                    0x3F69B8
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_6                    0x3F69BC
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_7                    0x3F69C0
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_8                    0x3F69C4
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_9                    0x3F69C8
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_10                   0x3F69CC
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_11                   0x3F69D0
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_12                   0x3F69D4
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_13                   0x3F69D8
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_14                   0x3F69DC
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_15                   0x3F69E0
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_0                   0x3F69E4
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_1                   0x3F69E8
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_2                   0x3F69EC
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_3                   0x3F69F0
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_4                   0x3F69F4
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_5                   0x3F69F8
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_6                   0x3F69FC
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_7                   0x3F6A00
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_8                   0x3F6A04
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_9                   0x3F6A08
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_10                  0x3F6A0C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_11                  0x3F6A10
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_12                  0x3F6A14
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_13                  0x3F6A18
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_14                  0x3F6A1C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_15                  0x3F6A20
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_HIT_AW                            0x3F6A64
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_HIT_AR                            0x3F6A68
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_HIT_AW                           0x3F6A6C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_HIT_AR                           0x3F6A70
+
+#define mmNIF_RTR_CTRL_7_RGL_CFG                                     0x3F6B64
+
+#define mmNIF_RTR_CTRL_7_RGL_SHIFT                                   0x3F6B68
+
+#define mmNIF_RTR_CTRL_7_RGL_EXPECTED_LAT_0                          0x3F6B6C
+
+#define mmNIF_RTR_CTRL_7_RGL_EXPECTED_LAT_1                          0x3F6B70
+
+#define mmNIF_RTR_CTRL_7_RGL_EXPECTED_LAT_2                          0x3F6B74
+
+#define mmNIF_RTR_CTRL_7_RGL_EXPECTED_LAT_3                          0x3F6B78
+
+#define mmNIF_RTR_CTRL_7_RGL_EXPECTED_LAT_4                          0x3F6B7C
+
+#define mmNIF_RTR_CTRL_7_RGL_EXPECTED_LAT_5                          0x3F6B80
+
+#define mmNIF_RTR_CTRL_7_RGL_EXPECTED_LAT_6                          0x3F6B84
+
+#define mmNIF_RTR_CTRL_7_RGL_EXPECTED_LAT_7                          0x3F6B88
+
+#define mmNIF_RTR_CTRL_7_RGL_TOKEN_0                                 0x3F6BAC
+
+#define mmNIF_RTR_CTRL_7_RGL_TOKEN_1                                 0x3F6BB0
+
+#define mmNIF_RTR_CTRL_7_RGL_TOKEN_2                                 0x3F6BB4
+
+#define mmNIF_RTR_CTRL_7_RGL_TOKEN_3                                 0x3F6BB8
+
+#define mmNIF_RTR_CTRL_7_RGL_TOKEN_4                                 0x3F6BBC
+
+#define mmNIF_RTR_CTRL_7_RGL_TOKEN_5                                 0x3F6BC0
+
+#define mmNIF_RTR_CTRL_7_RGL_TOKEN_6                                 0x3F6BC4
+
+#define mmNIF_RTR_CTRL_7_RGL_TOKEN_7                                 0x3F6BC8
+
+#define mmNIF_RTR_CTRL_7_RGL_BANK_ID_0                               0x3F6BEC
+
+#define mmNIF_RTR_CTRL_7_RGL_BANK_ID_1                               0x3F6BF0
+
+#define mmNIF_RTR_CTRL_7_RGL_BANK_ID_2                               0x3F6BF4
+
+#define mmNIF_RTR_CTRL_7_RGL_BANK_ID_3                               0x3F6BF8
+
+#define mmNIF_RTR_CTRL_7_RGL_BANK_ID_4                               0x3F6BFC
+
+#define mmNIF_RTR_CTRL_7_RGL_BANK_ID_5                               0x3F6C00
+
+#define mmNIF_RTR_CTRL_7_RGL_BANK_ID_6                               0x3F6C04
+
+#define mmNIF_RTR_CTRL_7_RGL_BANK_ID_7                               0x3F6C08
+
+#define mmNIF_RTR_CTRL_7_RGL_WDT                                     0x3F6C2C
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_HBM0_CH0_CTR_WRAP                    0x3F6C30
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_HBM0_CH1_CTR_WRAP                    0x3F6C34
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_HBM1_CH0_CTR_WRAP                    0x3F6C38
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_HBM1_CH1_CTR_WRAP                    0x3F6C3C
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_HBM2_CH0_CTR_WRAP                    0x3F6C40
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_HBM2_CH1_CTR_WRAP                    0x3F6C44
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_HBM3_CH0_CTR_WRAP                    0x3F6C48
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_HBM3_CH1_CTR_WRAP                    0x3F6C4C
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_HBM0_CH0_CTR_CNT                     0x3F6C50
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_HBM0_CH1_CTR_CNT                     0x3F6C54
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_HBM1_CH0_CTR_CNT                     0x3F6C58
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_HBM1_CH1_CTR_CNT                     0x3F6C5C
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_HBM2_CH0_CTR_CNT                     0x3F6C60
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_HBM2_CH1_CTR_CNT                     0x3F6C64
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_HBM3_CH0_CTR_CNT                     0x3F6C68
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_HBM3_CH1_CTR_CNT                     0x3F6C6C
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_HBM0_CH0_CTR_WRAP                    0x3F6C70
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_HBM0_CH1_CTR_WRAP                    0x3F6C74
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_HBM1_CH0_CTR_WRAP                    0x3F6C78
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_HBM1_CH1_CTR_WRAP                    0x3F6C7C
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_HBM2_CH0_CTR_WRAP                    0x3F6C80
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_HBM2_CH1_CTR_WRAP                    0x3F6C84
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_HBM3_CH0_CTR_WRAP                    0x3F6C88
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_HBM3_CH1_CTR_WRAP                    0x3F6C8C
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_HBM0_CH0_CTR_CNT                     0x3F6C90
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_HBM0_CH1_CTR_CNT                     0x3F6C94
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_HBM1_CH0_CTR_CNT                     0x3F6C98
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_HBM1_CH1_CTR_CNT                     0x3F6C9C
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_HBM2_CH0_CTR_CNT                     0x3F6CA0
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_HBM2_CH1_CTR_CNT                     0x3F6CA4
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_HBM3_CH0_CTR_CNT                     0x3F6CA8
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_HBM3_CH1_CTR_CNT                     0x3F6CAC
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_PC_SEL_0                             0x3F6CB0
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_PC_SEL_1                             0x3F6CB4
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_PC_SEL_2                             0x3F6CB8
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_PC_SEL_3                             0x3F6CBC
+
+#endif /* ASIC_REG_NIF_RTR_CTRL_7_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/psoc_cpu_pll_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/psoc_cpu_pll_regs.h
new file mode 100644
index 000000000000..2585c70f59ef
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/psoc_cpu_pll_regs.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PSOC_CPU_PLL_REGS_H_
+#define ASIC_REG_PSOC_CPU_PLL_REGS_H_
+
+/*
+ *****************************************
+ *   PSOC_CPU_PLL (Prototype: PLL)
+ *****************************************
+ */
+
+#define mmPSOC_CPU_PLL_NR                                            0xC70100
+
+#define mmPSOC_CPU_PLL_NF                                            0xC70104
+
+#define mmPSOC_CPU_PLL_OD                                            0xC70108
+
+#define mmPSOC_CPU_PLL_NB                                            0xC7010C
+
+#define mmPSOC_CPU_PLL_CFG                                           0xC70110
+
+#define mmPSOC_CPU_PLL_LOSE_MASK                                     0xC70120
+
+#define mmPSOC_CPU_PLL_LOCK_INTR                                     0xC70128
+
+#define mmPSOC_CPU_PLL_LOCK_BYPASS                                   0xC7012C
+
+#define mmPSOC_CPU_PLL_DATA_CHNG                                     0xC70130
+
+#define mmPSOC_CPU_PLL_RST                                           0xC70134
+
+#define mmPSOC_CPU_PLL_SLIP_WD_CNTR                                  0xC70150
+
+#define mmPSOC_CPU_PLL_DIV_FACTOR_0                                  0xC70200
+
+#define mmPSOC_CPU_PLL_DIV_FACTOR_1                                  0xC70204
+
+#define mmPSOC_CPU_PLL_DIV_FACTOR_2                                  0xC70208
+
+#define mmPSOC_CPU_PLL_DIV_FACTOR_3                                  0xC7020C
+
+#define mmPSOC_CPU_PLL_DIV_FACTOR_CMD_0                              0xC70220
+
+#define mmPSOC_CPU_PLL_DIV_FACTOR_CMD_1                              0xC70224
+
+#define mmPSOC_CPU_PLL_DIV_FACTOR_CMD_2                              0xC70228
+
+#define mmPSOC_CPU_PLL_DIV_FACTOR_CMD_3                              0xC7022C
+
+#define mmPSOC_CPU_PLL_DIV_SEL_0                                     0xC70280
+
+#define mmPSOC_CPU_PLL_DIV_SEL_1                                     0xC70284
+
+#define mmPSOC_CPU_PLL_DIV_SEL_2                                     0xC70288
+
+#define mmPSOC_CPU_PLL_DIV_SEL_3                                     0xC7028C
+
+#define mmPSOC_CPU_PLL_DIV_EN_0                                      0xC702A0
+
+#define mmPSOC_CPU_PLL_DIV_EN_1                                      0xC702A4
+
+#define mmPSOC_CPU_PLL_DIV_EN_2                                      0xC702A8
+
+#define mmPSOC_CPU_PLL_DIV_EN_3                                      0xC702AC
+
+#define mmPSOC_CPU_PLL_DIV_FACTOR_BUSY_0                             0xC702C0
+
+#define mmPSOC_CPU_PLL_DIV_FACTOR_BUSY_1                             0xC702C4
+
+#define mmPSOC_CPU_PLL_DIV_FACTOR_BUSY_2                             0xC702C8
+
+#define mmPSOC_CPU_PLL_DIV_FACTOR_BUSY_3                             0xC702CC
+
+#define mmPSOC_CPU_PLL_CLK_GATER                                     0xC70300
+
+#define mmPSOC_CPU_PLL_CLK_RLX_0                                     0xC70310
+
+#define mmPSOC_CPU_PLL_CLK_RLX_1                                     0xC70314
+
+#define mmPSOC_CPU_PLL_CLK_RLX_2                                     0xC70318
+
+#define mmPSOC_CPU_PLL_CLK_RLX_3                                     0xC7031C
+
+#define mmPSOC_CPU_PLL_REF_CNTR_PERIOD                               0xC70400
+
+#define mmPSOC_CPU_PLL_REF_LOW_THRESHOLD                             0xC70410
+
+#define mmPSOC_CPU_PLL_REF_HIGH_THRESHOLD                            0xC70420
+
+#define mmPSOC_CPU_PLL_PLL_NOT_STABLE                                0xC70430
+
+#define mmPSOC_CPU_PLL_FREQ_CALC_EN                                  0xC70440
+
+#define mmPSOC_CPU_PLL_RLX_BITMAP_CFG                                0xC70500
+
+#define mmPSOC_CPU_PLL_RLX_BITMAP_0                                  0xC70510
+
+#define mmPSOC_CPU_PLL_RLX_BITMAP_1                                  0xC70514
+
+#define mmPSOC_CPU_PLL_RLX_BITMAP_2                                  0xC70518
+
+#define mmPSOC_CPU_PLL_RLX_BITMAP_3                                  0xC7051C
+
+#endif /* ASIC_REG_PSOC_CPU_PLL_REGS_H_ */
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/psoc_etr_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/psoc_etr_regs.h
index b7c33e025db5..b7c33e025db5 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/psoc_etr_regs.h
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/psoc_etr_regs.h
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/psoc_global_conf_masks.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/psoc_global_conf_masks.h
new file mode 100644
index 000000000000..6703e678ee9f
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/psoc_global_conf_masks.h
@@ -0,0 +1,502 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_
+#define ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_
+
+/*
+ *****************************************
+ *   PSOC_GLOBAL_CONF (Prototype: GLOBAL_CONF)
+ *****************************************
+ */
+
+/* PSOC_GLOBAL_CONF_NON_RST_FLOPS */
+#define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_SHIFT                     0
+#define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_MASK                      0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_PCI_FW_FSM */
+#define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_SHIFT                         0
+#define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_MASK                          0x1
+
+/* PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START */
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT                 0
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_MASK                  0x1
+
+/* PSOC_GLOBAL_CONF_BTM_FSM */
+#define PSOC_GLOBAL_CONF_BTM_FSM_STATE_SHIFT                         0
+#define PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK                          0xF
+
+/* PSOC_GLOBAL_CONF_SW_BTM_FSM */
+#define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_SHIFT                       0
+#define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_MASK                        0xF
+
+/* PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM */
+#define PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM_CTRL_SHIFT                  0
+#define PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM_CTRL_MASK                   0xF
+
+/* PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT */
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT_VAL_SHIFT                  0
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT_VAL_MASK                   0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_SPI_MEM_EN */
+#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_SHIFT                        0
+#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_MASK                         0x1
+
+/* PSOC_GLOBAL_CONF_PRSTN */
+#define PSOC_GLOBAL_CONF_PRSTN_VAL_SHIFT                             0
+#define PSOC_GLOBAL_CONF_PRSTN_VAL_MASK                              0x1
+
+/* PSOC_GLOBAL_CONF_PCIE_EN */
+#define PSOC_GLOBAL_CONF_PCIE_EN_MASK_SHIFT                          0
+#define PSOC_GLOBAL_CONF_PCIE_EN_MASK_MASK                           0x1
+
+/* PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR */
+#define PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR_IND_SHIFT                   0
+#define PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR_IND_MASK                    0x1
+
+/* PSOC_GLOBAL_CONF_SPI_IMG_STS */
+#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRI_SHIFT                       0
+#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRI_MASK                        0x1
+#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SEC_SHIFT                       1
+#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SEC_MASK                        0x2
+#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_SHIFT                     2
+#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_MASK                      0x4
+#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCI_SHIFT                       3
+#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCI_MASK                        0x8
+
+/* PSOC_GLOBAL_CONF_BOOT_SEQ_FSM */
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_IDLE_SHIFT                     0
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_IDLE_MASK                      0x1
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_BOOT_INIT_SHIFT                1
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_BOOT_INIT_MASK                 0x2
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRI_SHIFT                  2
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRI_MASK                   0x4
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_SEC_SHIFT                  3
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_SEC_MASK                   0x8
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRSTN_SHIFT                4
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRSTN_MASK                 0x10
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PCIE_SHIFT                 5
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PCIE_MASK                  0x20
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_ROM_SHIFT                      6
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_ROM_MASK                       0x40
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_PCLK_READY_SHIFT               7
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_PCLK_READY_MASK                0x80
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_LTSSM_EN_SHIFT                 8
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_LTSSM_EN_MASK                  0x100
+
+/* PSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD */
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD_DONE_SHIFT                  0
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD_DONE_MASK                   0x1
+
+/* PSOC_GLOBAL_CONF_PHY_STABLE */
+#define PSOC_GLOBAL_CONF_PHY_STABLE_PRSTN_SHIFT                      0
+#define PSOC_GLOBAL_CONF_PHY_STABLE_PRSTN_MASK                       0x1
+
+/* PSOC_GLOBAL_CONF_PRSTN_OVR */
+#define PSOC_GLOBAL_CONF_PRSTN_OVR_EN_SHIFT                          0
+#define PSOC_GLOBAL_CONF_PRSTN_OVR_EN_MASK                           0x1
+#define PSOC_GLOBAL_CONF_PRSTN_OVR_VAL_SHIFT                         4
+#define PSOC_GLOBAL_CONF_PRSTN_OVR_VAL_MASK                          0x10
+
+/* PSOC_GLOBAL_CONF_ETR_FLUSH */
+#define PSOC_GLOBAL_CONF_ETR_FLUSH_MASK_SHIFT                        0
+#define PSOC_GLOBAL_CONF_ETR_FLUSH_MASK_MASK                         0x1
+
+/* PSOC_GLOBAL_CONF_COLD_RST_FLOPS */
+#define PSOC_GLOBAL_CONF_COLD_RST_FLOPS_VAL_SHIFT                    0
+#define PSOC_GLOBAL_CONF_COLD_RST_FLOPS_VAL_MASK                     0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_DIS_RAZWI_ERR */
+#define PSOC_GLOBAL_CONF_DIS_RAZWI_ERR_IND_SHIFT                     0
+#define PSOC_GLOBAL_CONF_DIS_RAZWI_ERR_IND_MASK                      0x1
+
+/* PSOC_GLOBAL_CONF_PCIE_PHY_RST_N */
+#define PSOC_GLOBAL_CONF_PCIE_PHY_RST_N_IND_SHIFT                    0
+#define PSOC_GLOBAL_CONF_PCIE_PHY_RST_N_IND_MASK                     0x1
+
+/* PSOC_GLOBAL_CONF_RAZWI */
+#define PSOC_GLOBAL_CONF_RAZWI_INTR_SHIFT                            0
+#define PSOC_GLOBAL_CONF_RAZWI_INTR_MASK                             0x1
+#define PSOC_GLOBAL_CONF_RAZWI_MASK_SHIFT                            4
+#define PSOC_GLOBAL_CONF_RAZWI_MASK_MASK                             0x10
+
+/* PSOC_GLOBAL_CONF_PROT */
+#define PSOC_GLOBAL_CONF_PROT_AR_SHIFT                               0
+#define PSOC_GLOBAL_CONF_PROT_AR_MASK                                0x7
+#define PSOC_GLOBAL_CONF_PROT_AW_SHIFT                               4
+#define PSOC_GLOBAL_CONF_PROT_AW_MASK                                0x70
+
+/* PSOC_GLOBAL_CONF_ADC */
+#define PSOC_GLOBAL_CONF_ADC_INTR_SHIFT                              0
+#define PSOC_GLOBAL_CONF_ADC_INTR_MASK                               0x1
+#define PSOC_GLOBAL_CONF_ADC_MASK_SHIFT                              4
+#define PSOC_GLOBAL_CONF_ADC_MASK_MASK                               0x10
+
+/* PSOC_GLOBAL_CONF_BOOT_SEQ_TO */
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_TO_MASK_SHIFT                      0
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_TO_MASK_MASK                       0x1
+
+/* PSOC_GLOBAL_CONF_SCRATCHPAD */
+#define PSOC_GLOBAL_CONF_SCRATCHPAD_REG_SHIFT                        0
+#define PSOC_GLOBAL_CONF_SCRATCHPAD_REG_MASK                         0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_SEMAPHORE */
+#define PSOC_GLOBAL_CONF_SEMAPHORE_REG_SHIFT                         0
+#define PSOC_GLOBAL_CONF_SEMAPHORE_REG_MASK                          0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_CPU_BOOT_STATUS */
+#define PSOC_GLOBAL_CONF_CPU_BOOT_STATUS_CNTR_SHIFT                  0
+#define PSOC_GLOBAL_CONF_CPU_BOOT_STATUS_CNTR_MASK                   0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_KMD_MSG_TO_CPU */
+#define PSOC_GLOBAL_CONF_KMD_MSG_TO_CPU_VAL_SHIFT                    0
+#define PSOC_GLOBAL_CONF_KMD_MSG_TO_CPU_VAL_MASK                     0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_SPL_SOURCE */
+#define PSOC_GLOBAL_CONF_SPL_SOURCE_VAL_SHIFT                        0
+#define PSOC_GLOBAL_CONF_SPL_SOURCE_VAL_MASK                         0x7
+
+/* PSOC_GLOBAL_CONF_I2C_MSTR1_DBG */
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_S_GEN_SHIFT                   0
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_S_GEN_MASK                    0x1
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_P_GEN_SHIFT                   1
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_P_GEN_MASK                    0x2
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_DATA_SHIFT                    2
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_DATA_MASK                     0x4
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_SHIFT                    3
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_MASK                     0x8
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_RD_SHIFT                      4
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_RD_MASK                       0x10
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_WR_SHIFT                      5
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_WR_MASK                       0x20
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_HS_SHIFT                      6
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_HS_MASK                       0x40
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MASTER_ACT_SHIFT              7
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MASTER_ACT_MASK               0x80
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLAVE_ACT_SHIFT               8
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLAVE_ACT_MASK                0x100
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_10BIT_SHIFT              9
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_10BIT_MASK               0x200
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MST_CSTATE_SHIFT              10
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MST_CSTATE_MASK               0x7C00
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLV_CSTATE_SHIFT              15
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLV_CSTATE_MASK               0x78000
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_IC_EN_SHIFT                   19
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_IC_EN_MASK                    0x80000
+
+/* PSOC_GLOBAL_CONF_I2C_SLV */
+#define PSOC_GLOBAL_CONF_I2C_SLV_CPU_CTRL_SHIFT                      0
+#define PSOC_GLOBAL_CONF_I2C_SLV_CPU_CTRL_MASK                       0x1
+
+/* PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK */
+#define PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK_FLD_INT_SHIFT             0
+#define PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK_FLD_INT_MASK              0x1
+
+/* PSOC_GLOBAL_CONF_TRACE_ADDR */
+#define PSOC_GLOBAL_CONF_TRACE_ADDR_MSB_SHIFT                        0
+#define PSOC_GLOBAL_CONF_TRACE_ADDR_MSB_MASK                         0x3FF
+
+/* PSOC_GLOBAL_CONF_ARUSER */
+#define PSOC_GLOBAL_CONF_ARUSER_VAL_SHIFT                            0
+#define PSOC_GLOBAL_CONF_ARUSER_VAL_MASK                             0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_AWUSER */
+#define PSOC_GLOBAL_CONF_AWUSER_VAL_SHIFT                            0
+#define PSOC_GLOBAL_CONF_AWUSER_VAL_MASK                             0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_TRACE_AWUSER */
+#define PSOC_GLOBAL_CONF_TRACE_AWUSER_VAL_SHIFT                      0
+#define PSOC_GLOBAL_CONF_TRACE_AWUSER_VAL_MASK                       0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_TRACE_ARUSER */
+#define PSOC_GLOBAL_CONF_TRACE_ARUSER_VAL_SHIFT                      0
+#define PSOC_GLOBAL_CONF_TRACE_ARUSER_VAL_MASK                       0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_BTL_STS */
+#define PSOC_GLOBAL_CONF_BTL_STS_DONE_SHIFT                          0
+#define PSOC_GLOBAL_CONF_BTL_STS_DONE_MASK                           0x1
+#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_SHIFT                          4
+#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_MASK                           0x10
+#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_CODE_SHIFT                     8
+#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_CODE_MASK                      0xF00
+
+/* PSOC_GLOBAL_CONF_TIMEOUT_INTR */
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_0_SHIFT                   0
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_0_MASK                    0x1
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_1_SHIFT                   1
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_1_MASK                    0x2
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_2_SHIFT                   2
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_2_MASK                    0x4
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_3_SHIFT                   3
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_3_MASK                    0x8
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_4_SHIFT                   4
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_4_MASK                    0x10
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_TIMER_SHIFT                    5
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_TIMER_MASK                     0x20
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_0_SHIFT                   6
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_0_MASK                    0x40
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_1_SHIFT                   7
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_1_MASK                    0x80
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_5_SHIFT                   8
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_5_MASK                    0x100
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_6_SHIFT                   9
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_6_MASK                    0x200
+
+/* PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR */
+#define PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR_IND_SHIFT                 0
+#define PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR_IND_MASK                  0x1
+
+/* PSOC_GLOBAL_CONF_PERIPH_INTR */
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TX_SHIFT                 0
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TX_MASK                  0x1
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RX_SHIFT                 1
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RX_MASK                  0x2
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TXOVR_SHIFT              2
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TXOVR_MASK               0x4
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RXOVR_SHIFT              3
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RXOVR_MASK               0x8
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TX_SHIFT                 4
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TX_MASK                  0x10
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RX_SHIFT                 5
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RX_MASK                  0x20
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TXOVR_SHIFT              6
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TXOVR_MASK               0x40
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RXOVR_SHIFT              7
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RXOVR_MASK               0x80
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_SHIFT                      12
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_MASK                       0x1000
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_WAKEUP_SHIFT               13
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_WAKEUP_MASK                0x2000
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_MII_SHIFT                       16
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_MII_MASK                        0x10000
+
+/* PSOC_GLOBAL_CONF_COMB_PERIPH_INTR */
+#define PSOC_GLOBAL_CONF_COMB_PERIPH_INTR_IND_SHIFT                  0
+#define PSOC_GLOBAL_CONF_COMB_PERIPH_INTR_IND_MASK                   0x1
+
+/* PSOC_GLOBAL_CONF_AXI_ERR_INTR */
+#define PSOC_GLOBAL_CONF_AXI_ERR_INTR_IND_SHIFT                      0
+#define PSOC_GLOBAL_CONF_AXI_ERR_INTR_IND_MASK                       0x1
+
+/* PSOC_GLOBAL_CONF_TARGETID */
+#define PSOC_GLOBAL_CONF_TARGETID_TDESIGNER_SHIFT                    1
+#define PSOC_GLOBAL_CONF_TARGETID_TDESIGNER_MASK                     0xFFE
+#define PSOC_GLOBAL_CONF_TARGETID_TPARTNO_SHIFT                      16
+#define PSOC_GLOBAL_CONF_TARGETID_TPARTNO_MASK                       0xFFF0000
+#define PSOC_GLOBAL_CONF_TARGETID_TREVISION_SHIFT                    28
+#define PSOC_GLOBAL_CONF_TARGETID_TREVISION_MASK                     0xF0000000
+
+/* PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE */
+#define PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE_IND_SHIFT               0
+#define PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE_IND_MASK                0x1
+
+/* PSOC_GLOBAL_CONF_BOOT_STRAP_PINS */
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_SLV_ADDR_SHIFT          0
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_SLV_ADDR_MASK           0x1
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PCIE_EN_SHIFT               1
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PCIE_EN_MASK                0x2
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_REPAIR_CFG_SHIFT            2
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_REPAIR_CFG_MASK             0xC
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPOL_SHIFT                  4
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPOL_MASK                   0x10
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPHA_SHIFT                  5
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPHA_MASK                   0x20
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_EN_SHIFT                6
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_EN_MASK                 0x40
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_ROM_EN_SHIFT            7
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_ROM_EN_MASK             0x80
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_DUMP_SEL_SHIFT              8
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_DUMP_SEL_MASK               0x1FFF00
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_GRAD_RST_SHIFT              22
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_GRAD_RST_MASK               0x400000
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_DUMP_DIS_SHIFT              23
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_DUMP_DIS_MASK               0x800000
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_SHIFT                   24
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_MASK                    0x1F000000
+
+/* PSOC_GLOBAL_CONF_MEM_REPAIR_DIV */
+#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_EN_SHIFT                     0
+#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_EN_MASK                      0x1
+#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_VAL_SHIFT                    8
+#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_VAL_MASK                     0xFF00
+
+/* PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL */
+#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_SET_SHIFT                   0
+#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_SET_MASK                    0x1
+#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_CLR_SHIFT                   1
+#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_CLR_MASK                    0x2
+
+/* PSOC_GLOBAL_CONF_MEM_REPAIR_STS */
+#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_IND_SHIFT                    0
+#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_IND_MASK                     0x1
+#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_FAIL_SHIFT                   4
+#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_FAIL_MASK                    0x10
+
+/* PSOC_GLOBAL_CONF_OUTSTANT_TRANS */
+#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_RD_SHIFT                     0
+#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_RD_MASK                      0x1
+#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_WR_SHIFT                     1
+#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_WR_MASK                      0x2
+
+/* PSOC_GLOBAL_CONF_MASK_REQ */
+#define PSOC_GLOBAL_CONF_MASK_REQ_IND_SHIFT                          0
+#define PSOC_GLOBAL_CONF_MASK_REQ_IND_MASK                           0x1
+
+/* PSOC_GLOBAL_CONF_WD_RST_CFG_L */
+#define PSOC_GLOBAL_CONF_WD_RST_CFG_L_VAL_SHIFT                      0
+#define PSOC_GLOBAL_CONF_WD_RST_CFG_L_VAL_MASK                       0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_WD_RST_CFG_H */
+#define PSOC_GLOBAL_CONF_WD_RST_CFG_H_VAL_SHIFT                      0
+#define PSOC_GLOBAL_CONF_WD_RST_CFG_H_VAL_MASK                       0x3FFFFF
+
+/* PSOC_GLOBAL_CONF_MNL_RST_CFG_L */
+#define PSOC_GLOBAL_CONF_MNL_RST_CFG_L_VAL_SHIFT                     0
+#define PSOC_GLOBAL_CONF_MNL_RST_CFG_L_VAL_MASK                      0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_MNL_RST_CFG_H */
+#define PSOC_GLOBAL_CONF_MNL_RST_CFG_H_VAL_SHIFT                     0
+#define PSOC_GLOBAL_CONF_MNL_RST_CFG_H_VAL_MASK                      0x3FFFFF
+
+/* PSOC_GLOBAL_CONF_PRSTN_RST_CFG_L */
+#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_L_VAL_SHIFT                   0
+#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_L_VAL_MASK                    0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_PRSTN_RST_CFG_H */
+#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_H_VAL_SHIFT                   0
+#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_H_VAL_MASK                    0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_L */
+#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_L_VAL_SHIFT                  0
+#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_L_VAL_MASK                   0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_H */
+#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_H_VAL_SHIFT                  0
+#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_H_VAL_MASK                   0x3FFFFF
+
+/* PSOC_GLOBAL_CONF_SW_ALL_RST */
+#define PSOC_GLOBAL_CONF_SW_ALL_RST_IND_SHIFT                        0
+#define PSOC_GLOBAL_CONF_SW_ALL_RST_IND_MASK                         0x1
+
+/* PSOC_GLOBAL_CONF_SOFT_RST */
+#define PSOC_GLOBAL_CONF_SOFT_RST_IND_SHIFT                          0
+#define PSOC_GLOBAL_CONF_SOFT_RST_IND_MASK                           0x1
+
+/* PSOC_GLOBAL_CONF_SOFT_RST_CFG_L */
+#define PSOC_GLOBAL_CONF_SOFT_RST_CFG_L_VAL_SHIFT                    0
+#define PSOC_GLOBAL_CONF_SOFT_RST_CFG_L_VAL_MASK                     0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_SOFT_RST_CFG_H */
+#define PSOC_GLOBAL_CONF_SOFT_RST_CFG_H_VAL_SHIFT                    0
+#define PSOC_GLOBAL_CONF_SOFT_RST_CFG_H_VAL_MASK                     0x3FFFFF
+
+/* PSOC_GLOBAL_CONF_UNIT_RST_N */
+#define PSOC_GLOBAL_CONF_UNIT_RST_N_IND_SHIFT                        0
+#define PSOC_GLOBAL_CONF_UNIT_RST_N_IND_MASK                         0x1
+
+/* PSOC_GLOBAL_CONF_UNIT_RST_N_L */
+#define PSOC_GLOBAL_CONF_UNIT_RST_N_L_VAL_SHIFT                      0
+#define PSOC_GLOBAL_CONF_UNIT_RST_N_L_VAL_MASK                       0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_UNIT_RST_N_H */
+#define PSOC_GLOBAL_CONF_UNIT_RST_N_H_VAL_SHIFT                      0
+#define PSOC_GLOBAL_CONF_UNIT_RST_N_H_VAL_MASK                       0x3FFFFF
+
+/* PSOC_GLOBAL_CONF_BTL_IMG */
+#define PSOC_GLOBAL_CONF_BTL_IMG_SEL_SHIFT                           0
+#define PSOC_GLOBAL_CONF_BTL_IMG_SEL_MASK                            0x1
+
+/* PSOC_GLOBAL_CONF_PRSTN_MASK */
+#define PSOC_GLOBAL_CONF_PRSTN_MASK_IND_SHIFT                        0
+#define PSOC_GLOBAL_CONF_PRSTN_MASK_IND_MASK                         0x1
+
+/* PSOC_GLOBAL_CONF_WD_MASK */
+#define PSOC_GLOBAL_CONF_WD_MASK_IND_SHIFT                           0
+#define PSOC_GLOBAL_CONF_WD_MASK_IND_MASK                            0x1
+
+/* PSOC_GLOBAL_CONF_RST_SRC */
+#define PSOC_GLOBAL_CONF_RST_SRC_VAL_SHIFT                           0
+#define PSOC_GLOBAL_CONF_RST_SRC_VAL_MASK                            0xF
+
+/* PSOC_GLOBAL_CONF_BOOT_STATE */
+#define PSOC_GLOBAL_CONF_BOOT_STATE_VAL_SHIFT                        0
+#define PSOC_GLOBAL_CONF_BOOT_STATE_VAL_MASK                         0x1
+
+/* PSOC_GLOBAL_CONF_PAD_1V8_CFG */
+#define PSOC_GLOBAL_CONF_PAD_1V8_CFG_VAL_SHIFT                       0
+#define PSOC_GLOBAL_CONF_PAD_1V8_CFG_VAL_MASK                        0x7F
+
+/* PSOC_GLOBAL_CONF_PAD_3V3_CFG */
+#define PSOC_GLOBAL_CONF_PAD_3V3_CFG_VAL_SHIFT                       0
+#define PSOC_GLOBAL_CONF_PAD_3V3_CFG_VAL_MASK                        0x7F
+
+/* PSOC_GLOBAL_CONF_PAD_1V8_INPUT */
+#define PSOC_GLOBAL_CONF_PAD_1V8_INPUT_CFG_SHIFT                     0
+#define PSOC_GLOBAL_CONF_PAD_1V8_INPUT_CFG_MASK                      0x7
+
+/* PSOC_GLOBAL_CONF_BNK3V3_MS */
+#define PSOC_GLOBAL_CONF_BNK3V3_MS_VAL_SHIFT                         0
+#define PSOC_GLOBAL_CONF_BNK3V3_MS_VAL_MASK                          0x3
+
+/* PSOC_GLOBAL_CONF_ADC_CLK_FREQ */
+#define PSOC_GLOBAL_CONF_ADC_CLK_FREQ_VAL_SHIFT                      0
+#define PSOC_GLOBAL_CONF_ADC_CLK_FREQ_VAL_MASK                       0xFF
+
+/* PSOC_GLOBAL_CONF_ADC_DELAY_FROM_START */
+#define PSOC_GLOBAL_CONF_ADC_DELAY_FROM_START_VAL_SHIFT              0
+#define PSOC_GLOBAL_CONF_ADC_DELAY_FROM_START_VAL_MASK               0xFF
+
+/* PSOC_GLOBAL_CONF_ADC_DATA_SAMPLES */
+#define PSOC_GLOBAL_CONF_ADC_DATA_SAMPLES_VAL_SHIFT                  0
+#define PSOC_GLOBAL_CONF_ADC_DATA_SAMPLES_VAL_MASK                   0x1F
+
+/* PSOC_GLOBAL_CONF_ADC_TPH_CS */
+#define PSOC_GLOBAL_CONF_ADC_TPH_CS_VAL_SHIFT                        0
+#define PSOC_GLOBAL_CONF_ADC_TPH_CS_VAL_MASK                         0xFF
+
+/* PSOC_GLOBAL_CONF_ADC_LSB_NMSB */
+#define PSOC_GLOBAL_CONF_ADC_LSB_NMSB_VAL_SHIFT                      0
+#define PSOC_GLOBAL_CONF_ADC_LSB_NMSB_VAL_MASK                       0x1
+
+/* PSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES */
+#define PSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES_VAL_SHIFT                 0
+#define PSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES_VAL_MASK                  0x1
+
+/* PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE */
+#define PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_VAL_SHIFT                  0
+#define PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_VAL_MASK                   0x1
+
+/* PSOC_GLOBAL_CONF_ADC_CFG_DATA */
+#define PSOC_GLOBAL_CONF_ADC_CFG_DATA_VAL_SHIFT                      0
+#define PSOC_GLOBAL_CONF_ADC_CFG_DATA_VAL_MASK                       0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_ADC_TDV_CSDO */
+#define PSOC_GLOBAL_CONF_ADC_TDV_CSDO_VAL_SHIFT                      0
+#define PSOC_GLOBAL_CONF_ADC_TDV_CSDO_VAL_MASK                       0xFF
+
+/* PSOC_GLOBAL_CONF_ADC_TSU_CSCK */
+#define PSOC_GLOBAL_CONF_ADC_TSU_CSCK_VAL_SHIFT                      0
+#define PSOC_GLOBAL_CONF_ADC_TSU_CSCK_VAL_MASK                       0xFF
+
+/* PSOC_GLOBAL_CONF_PAD_DEFAULT */
+#define PSOC_GLOBAL_CONF_PAD_DEFAULT_VAL_SHIFT                       0
+#define PSOC_GLOBAL_CONF_PAD_DEFAULT_VAL_MASK                        0xF
+
+/* PSOC_GLOBAL_CONF_PAD_SEL */
+#define PSOC_GLOBAL_CONF_PAD_SEL_VAL_SHIFT                           0
+#define PSOC_GLOBAL_CONF_PAD_SEL_VAL_MASK                            0x3
+
+/* PSOC_GLOBAL_CONF_RST_CTRL */
+#define PSOC_GLOBAL_CONF_RST_CTRL_SEL_SHIFT                          0
+#define PSOC_GLOBAL_CONF_RST_CTRL_SEL_MASK                           0xFF
+
+#endif /* ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/psoc_global_conf_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/psoc_global_conf_regs.h
new file mode 100644
index 000000000000..1b5cfcc1d85f
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/psoc_global_conf_regs.h
@@ -0,0 +1,1062 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_
+#define ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_
+
+/*
+ *****************************************
+ *   PSOC_GLOBAL_CONF (Prototype: GLOBAL_CONF)
+ *****************************************
+ */
+
+#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_0                           0xC4B000
+
+#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_1                           0xC4B004
+
+#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_2                           0xC4B008
+
+#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_3                           0xC4B00C
+
+#define mmPSOC_GLOBAL_CONF_PCI_FW_FSM                                0xC4B020
+
+#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_RE_START                         0xC4B024
+
+#define mmPSOC_GLOBAL_CONF_BTM_FSM                                   0xC4B028
+
+#define mmPSOC_GLOBAL_CONF_SW_BTM_FSM                                0xC4B030
+
+#define mmPSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM                           0xC4B034
+
+#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT                          0xC4B038
+
+#define mmPSOC_GLOBAL_CONF_SPI_MEM_EN                                0xC4B040
+
+#define mmPSOC_GLOBAL_CONF_PRSTN                                     0xC4B044
+
+#define mmPSOC_GLOBAL_CONF_PCIE_EN                                   0xC4B048
+
+#define mmPSOC_GLOBAL_CONF_PCIE_PRSTN_INTR                           0xC4B04C
+
+#define mmPSOC_GLOBAL_CONF_SPI_IMG_STS                               0xC4B050
+
+#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_FSM                              0xC4B054
+
+#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD                           0xC4B058
+
+#define mmPSOC_GLOBAL_CONF_PHY_STABLE                                0xC4B060
+
+#define mmPSOC_GLOBAL_CONF_PRSTN_OVR                                 0xC4B064
+
+#define mmPSOC_GLOBAL_CONF_ETR_FLUSH                                 0xC4B068
+
+#define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_0                          0xC4B070
+
+#define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_1                          0xC4B074
+
+#define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_2                          0xC4B078
+
+#define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_3                          0xC4B07C
+
+#define mmPSOC_GLOBAL_CONF_DIS_RAZWI_ERR                             0xC4B080
+
+#define mmPSOC_GLOBAL_CONF_PCIE_PHY_RST_N                            0xC4B084
+
+#define mmPSOC_GLOBAL_CONF_RAZWI                                     0xC4B088
+
+#define mmPSOC_GLOBAL_CONF_PROT                                      0xC4B090
+
+#define mmPSOC_GLOBAL_CONF_ADC                                       0xC4B094
+
+#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_TO                               0xC4B098
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_0                              0xC4B100
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_1                              0xC4B104
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_2                              0xC4B108
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_3                              0xC4B10C
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_4                              0xC4B110
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_5                              0xC4B114
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_6                              0xC4B118
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_7                              0xC4B11C
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_8                              0xC4B120
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_9                              0xC4B124
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_10                             0xC4B128
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_11                             0xC4B12C
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_12                             0xC4B130
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_13                             0xC4B134
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_14                             0xC4B138
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_15                             0xC4B13C
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_16                             0xC4B140
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_17                             0xC4B144
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_18                             0xC4B148
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_19                             0xC4B14C
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_20                             0xC4B150
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_21                             0xC4B154
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_22                             0xC4B158
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_23                             0xC4B15C
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_24                             0xC4B160
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_25                             0xC4B164
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_26                             0xC4B168
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_27                             0xC4B16C
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_28                             0xC4B170
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_29                             0xC4B174
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_30                             0xC4B178
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_31                             0xC4B17C
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_0                               0xC4B200
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_1                               0xC4B204
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_2                               0xC4B208
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_3                               0xC4B20C
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_4                               0xC4B210
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_5                               0xC4B214
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_6                               0xC4B218
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_7                               0xC4B21C
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_8                               0xC4B220
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_9                               0xC4B224
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_10                              0xC4B228
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_11                              0xC4B22C
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_12                              0xC4B230
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_13                              0xC4B234
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_14                              0xC4B238
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_15                              0xC4B23C
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_16                              0xC4B240
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_17                              0xC4B244
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_18                              0xC4B248
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_19                              0xC4B24C
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_20                              0xC4B250
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_21                              0xC4B254
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_22                              0xC4B258
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_23                              0xC4B25C
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_24                              0xC4B260
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_25                              0xC4B264
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_26                              0xC4B268
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_27                              0xC4B26C
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_28                              0xC4B270
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_29                              0xC4B274
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_30                              0xC4B278
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_31                              0xC4B27C
+
+#define mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS                           0xC4B300
+
+#define mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU                            0xC4B304
+
+#define mmPSOC_GLOBAL_CONF_SPL_SOURCE                                0xC4B308
+
+#define mmPSOC_GLOBAL_CONF_I2C_MSTR1_DBG                             0xC4B30C
+
+#define mmPSOC_GLOBAL_CONF_I2C_SLV                                   0xC4B310
+
+#define mmPSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK                         0xC4B314
+
+#define mmPSOC_GLOBAL_CONF_TRACE_ADDR                                0xC4B320
+
+#define mmPSOC_GLOBAL_CONF_ARUSER                                    0xC4B330
+
+#define mmPSOC_GLOBAL_CONF_AWUSER                                    0xC4B334
+
+#define mmPSOC_GLOBAL_CONF_TRACE_AWUSER                              0xC4B338
+
+#define mmPSOC_GLOBAL_CONF_TRACE_ARUSER                              0xC4B33C
+
+#define mmPSOC_GLOBAL_CONF_BTL_STS                                   0xC4B340
+
+#define mmPSOC_GLOBAL_CONF_TIMEOUT_INTR                              0xC4B350
+
+#define mmPSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR                         0xC4B354
+
+#define mmPSOC_GLOBAL_CONF_PERIPH_INTR                               0xC4B358
+
+#define mmPSOC_GLOBAL_CONF_COMB_PERIPH_INTR                          0xC4B35C
+
+#define mmPSOC_GLOBAL_CONF_AXI_ERR_INTR                              0xC4B360
+
+#define mmPSOC_GLOBAL_CONF_TARGETID                                  0xC4B400
+
+#define mmPSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE                       0xC4B420
+
+#define mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS                           0xC4B430
+
+#define mmPSOC_GLOBAL_CONF_MEM_REPAIR_DIV                            0xC4B44C
+
+#define mmPSOC_GLOBAL_CONF_MEM_REPAIR_CTRL                           0xC4B450
+
+#define mmPSOC_GLOBAL_CONF_MEM_REPAIR_STS                            0xC4B454
+
+#define mmPSOC_GLOBAL_CONF_OUTSTANT_TRANS                            0xC4B458
+
+#define mmPSOC_GLOBAL_CONF_MASK_REQ                                  0xC4B45C
+
+#define mmPSOC_GLOBAL_CONF_WD_RST_CFG_L                              0xC4B460
+
+#define mmPSOC_GLOBAL_CONF_WD_RST_CFG_H                              0xC4B464
+
+#define mmPSOC_GLOBAL_CONF_MNL_RST_CFG_L                             0xC4B470
+
+#define mmPSOC_GLOBAL_CONF_MNL_RST_CFG_H                             0xC4B474
+
+#define mmPSOC_GLOBAL_CONF_PRSTN_RST_CFG_L                           0xC4B480
+
+#define mmPSOC_GLOBAL_CONF_PRSTN_RST_CFG_H                           0xC4B484
+
+#define mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG_L                          0xC4B490
+
+#define mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG_H                          0xC4B494
+
+#define mmPSOC_GLOBAL_CONF_SW_ALL_RST                                0xC4B498
+
+#define mmPSOC_GLOBAL_CONF_SOFT_RST                                  0xC4B4A0
+
+#define mmPSOC_GLOBAL_CONF_SOFT_RST_CFG_L                            0xC4B4A4
+
+#define mmPSOC_GLOBAL_CONF_SOFT_RST_CFG_H                            0xC4B4A8
+
+#define mmPSOC_GLOBAL_CONF_UNIT_RST_N                                0xC4B4B0
+
+#define mmPSOC_GLOBAL_CONF_UNIT_RST_N_L                              0xC4B4B4
+
+#define mmPSOC_GLOBAL_CONF_UNIT_RST_N_H                              0xC4B4B8
+
+#define mmPSOC_GLOBAL_CONF_BTL_IMG                                   0xC4B4E0
+
+#define mmPSOC_GLOBAL_CONF_PRSTN_MASK                                0xC4B4E4
+
+#define mmPSOC_GLOBAL_CONF_WD_MASK                                   0xC4B4E8
+
+#define mmPSOC_GLOBAL_CONF_RST_SRC                                   0xC4B4F0
+
+#define mmPSOC_GLOBAL_CONF_BOOT_STATE                                0xC4B4F4
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_0                             0xC4B500
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_1                             0xC4B504
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_2                             0xC4B508
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_3                             0xC4B50C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_4                             0xC4B510
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_5                             0xC4B514
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_6                             0xC4B518
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_7                             0xC4B51C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_8                             0xC4B520
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_9                             0xC4B524
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_10                            0xC4B528
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_11                            0xC4B52C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_12                            0xC4B530
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_13                            0xC4B534
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_14                            0xC4B538
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_15                            0xC4B53C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_16                            0xC4B540
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_17                            0xC4B544
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_18                            0xC4B548
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_19                            0xC4B54C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_20                            0xC4B550
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_21                            0xC4B554
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_22                            0xC4B558
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_23                            0xC4B55C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_24                            0xC4B560
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_25                            0xC4B564
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_26                            0xC4B568
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_27                            0xC4B56C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_28                            0xC4B570
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_29                            0xC4B574
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_30                            0xC4B578
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_31                            0xC4B57C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_32                            0xC4B580
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_33                            0xC4B584
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_34                            0xC4B588
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_35                            0xC4B58C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_36                            0xC4B590
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_37                            0xC4B594
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_38                            0xC4B598
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_39                            0xC4B59C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_40                            0xC4B5A0
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_41                            0xC4B5A4
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_42                            0xC4B5A8
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_43                            0xC4B5AC
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_44                            0xC4B5B0
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_45                            0xC4B5B4
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_46                            0xC4B5B8
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_47                            0xC4B5BC
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_48                            0xC4B5C0
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_49                            0xC4B5C4
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_50                            0xC4B5C8
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_51                            0xC4B5CC
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_52                            0xC4B5D0
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_53                            0xC4B5D4
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_54                            0xC4B5D8
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_55                            0xC4B5DC
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_56                            0xC4B5E0
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_57                            0xC4B5E4
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_58                            0xC4B5E8
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_59                            0xC4B5EC
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_60                            0xC4B5F0
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_61                            0xC4B5F4
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_62                            0xC4B5F8
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_63                            0xC4B5FC
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_64                            0xC4B600
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_65                            0xC4B604
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_66                            0xC4B608
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_67                            0xC4B60C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_68                            0xC4B610
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_69                            0xC4B614
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_70                            0xC4B618
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_71                            0xC4B61C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_72                            0xC4B620
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_73                            0xC4B624
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_74                            0xC4B628
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_75                            0xC4B62C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_76                            0xC4B630
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_77                            0xC4B634
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_78                            0xC4B638
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_79                            0xC4B63C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_80                            0xC4B640
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_81                            0xC4B644
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_82                            0xC4B648
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_83                            0xC4B64C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_84                            0xC4B650
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_85                            0xC4B654
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_86                            0xC4B658
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_87                            0xC4B65C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_88                            0xC4B660
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_89                            0xC4B664
+
+#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_0                             0xC4B690
+
+#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_1                             0xC4B694
+
+#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_2                             0xC4B698
+
+#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_3                             0xC4B69C
+
+#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_4                             0xC4B6A0
+
+#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_5                             0xC4B6A4
+
+#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_6                             0xC4B6A8
+
+#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_7                             0xC4B6AC
+
+#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_8                             0xC4B6B0
+
+#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_9                             0xC4B6B4
+
+#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_10                            0xC4B6B8
+
+#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_11                            0xC4B6BC
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_0                           0xC4B6C0
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_1                           0xC4B6C4
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_2                           0xC4B6C8
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_3                           0xC4B6CC
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_4                           0xC4B6D0
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_5                           0xC4B6D4
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_6                           0xC4B6D8
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_7                           0xC4B6DC
+
+#define mmPSOC_GLOBAL_CONF_BNK3V3_MS                                 0xC4B710
+
+#define mmPSOC_GLOBAL_CONF_ADC_CLK_FREQ                              0xC4B720
+
+#define mmPSOC_GLOBAL_CONF_ADC_DELAY_FROM_START                      0xC4B724
+
+#define mmPSOC_GLOBAL_CONF_ADC_DATA_SAMPLES                          0xC4B728
+
+#define mmPSOC_GLOBAL_CONF_ADC_TPH_CS                                0xC4B72C
+
+#define mmPSOC_GLOBAL_CONF_ADC_LSB_NMSB                              0xC4B730
+
+#define mmPSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES                         0xC4B734
+
+#define mmPSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE                          0xC4B738
+
+#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA                              0xC4B73C
+
+#define mmPSOC_GLOBAL_CONF_ADC_TDV_CSDO                              0xC4B740
+
+#define mmPSOC_GLOBAL_CONF_ADC_TSU_CSCK                              0xC4B744
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_0                             0xC4B800
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_1                             0xC4B804
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_2                             0xC4B808
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_3                             0xC4B80C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_4                             0xC4B810
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_5                             0xC4B814
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_6                             0xC4B818
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_7                             0xC4B81C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_8                             0xC4B820
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_9                             0xC4B824
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_10                            0xC4B828
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_11                            0xC4B82C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_12                            0xC4B830
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_13                            0xC4B834
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_14                            0xC4B838
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_15                            0xC4B83C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_16                            0xC4B840
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_17                            0xC4B844
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_18                            0xC4B848
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_19                            0xC4B84C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_20                            0xC4B850
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_21                            0xC4B854
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_22                            0xC4B858
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_23                            0xC4B85C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_24                            0xC4B860
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_25                            0xC4B864
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_26                            0xC4B868
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_27                            0xC4B86C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_28                            0xC4B870
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_29                            0xC4B874
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_30                            0xC4B878
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_31                            0xC4B87C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_32                            0xC4B880
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_33                            0xC4B884
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_34                            0xC4B888
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_35                            0xC4B88C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_36                            0xC4B890
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_37                            0xC4B894
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_38                            0xC4B898
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_39                            0xC4B89C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_40                            0xC4B8A0
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_41                            0xC4B8A4
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_42                            0xC4B8A8
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_43                            0xC4B8AC
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_44                            0xC4B8B0
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_45                            0xC4B8B4
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_46                            0xC4B8B8
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_47                            0xC4B8BC
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_48                            0xC4B8C0
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_49                            0xC4B8C4
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_50                            0xC4B8C8
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_51                            0xC4B8CC
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_52                            0xC4B8D0
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_53                            0xC4B8D4
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_54                            0xC4B8D8
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_55                            0xC4B8DC
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_56                            0xC4B8E0
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_57                            0xC4B8E4
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_58                            0xC4B8E8
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_59                            0xC4B8EC
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_60                            0xC4B8F0
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_61                            0xC4B8F4
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_62                            0xC4B8F8
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_63                            0xC4B8FC
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_64                            0xC4B900
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_65                            0xC4B904
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_66                            0xC4B908
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_67                            0xC4B90C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_68                            0xC4B910
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_69                            0xC4B914
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_70                            0xC4B918
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_71                            0xC4B91C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_72                            0xC4B920
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_73                            0xC4B924
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_74                            0xC4B928
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_75                            0xC4B92C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_76                            0xC4B930
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_77                            0xC4B934
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_78                            0xC4B938
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_79                            0xC4B93C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_80                            0xC4B940
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_81                            0xC4B944
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_82                            0xC4B948
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_83                            0xC4B94C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_84                            0xC4B950
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_85                            0xC4B954
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_86                            0xC4B958
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_87                            0xC4B95C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_88                            0xC4B960
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_89                            0xC4B964
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_90                            0xC4B968
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_91                            0xC4B96C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_92                            0xC4B970
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_93                            0xC4B974
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_94                            0xC4B978
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_95                            0xC4B97C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_96                            0xC4B980
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_97                            0xC4B984
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_98                            0xC4B988
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_99                            0xC4B98C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_100                           0xC4B990
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_101                           0xC4B994
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_102                           0xC4B998
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_0                                 0xC4BA00
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_1                                 0xC4BA04
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_2                                 0xC4BA08
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_3                                 0xC4BA0C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_4                                 0xC4BA10
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_5                                 0xC4BA14
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_6                                 0xC4BA18
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_7                                 0xC4BA1C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_8                                 0xC4BA20
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_9                                 0xC4BA24
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_10                                0xC4BA28
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_11                                0xC4BA2C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_12                                0xC4BA30
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_13                                0xC4BA34
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_14                                0xC4BA38
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_15                                0xC4BA3C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_16                                0xC4BA40
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_17                                0xC4BA44
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_18                                0xC4BA48
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_19                                0xC4BA4C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_20                                0xC4BA50
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_21                                0xC4BA54
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_22                                0xC4BA58
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_23                                0xC4BA5C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_24                                0xC4BA60
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_25                                0xC4BA64
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_26                                0xC4BA68
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_27                                0xC4BA6C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_28                                0xC4BA70
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_29                                0xC4BA74
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_30                                0xC4BA78
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_31                                0xC4BA7C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_32                                0xC4BA80
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_33                                0xC4BA84
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_34                                0xC4BA88
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_35                                0xC4BA8C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_36                                0xC4BA90
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_37                                0xC4BA94
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_38                                0xC4BA98
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_39                                0xC4BA9C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_40                                0xC4BAA0
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_41                                0xC4BAA4
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_42                                0xC4BAA8
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_43                                0xC4BAAC
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_44                                0xC4BAB0
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_45                                0xC4BAB4
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_46                                0xC4BAB8
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_47                                0xC4BABC
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_48                                0xC4BAC0
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_49                                0xC4BAC4
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_50                                0xC4BAC8
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_51                                0xC4BACC
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_52                                0xC4BAD0
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_53                                0xC4BAD4
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_54                                0xC4BAD8
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_55                                0xC4BADC
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_56                                0xC4BAE0
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_57                                0xC4BAE4
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_58                                0xC4BAE8
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_59                                0xC4BAEC
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_60                                0xC4BAF0
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_61                                0xC4BAF4
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_62                                0xC4BAF8
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_63                                0xC4BAFC
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_64                                0xC4BB00
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_65                                0xC4BB04
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_66                                0xC4BB08
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_67                                0xC4BB0C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_68                                0xC4BB10
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_69                                0xC4BB14
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_70                                0xC4BB18
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_71                                0xC4BB1C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_72                                0xC4BB20
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_73                                0xC4BB24
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_74                                0xC4BB28
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_75                                0xC4BB2C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_76                                0xC4BB30
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_77                                0xC4BB34
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_78                                0xC4BB38
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_79                                0xC4BB3C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_80                                0xC4BB40
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_81                                0xC4BB44
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_82                                0xC4BB48
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_83                                0xC4BB4C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_84                                0xC4BB50
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_85                                0xC4BB54
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_86                                0xC4BB58
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_87                                0xC4BB5C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_88                                0xC4BB60
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_89                                0xC4BB64
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_90                                0xC4BB68
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_91                                0xC4BB6C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_92                                0xC4BB70
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_93                                0xC4BB74
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_94                                0xC4BB78
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_95                                0xC4BB7C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_96                                0xC4BB80
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_97                                0xC4BB84
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_98                                0xC4BB88
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_99                                0xC4BB8C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_100                               0xC4BB90
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_101                               0xC4BB94
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_102                               0xC4BB98
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_0                                0xC4BC00
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_1                                0xC4BC04
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_2                                0xC4BC08
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_3                                0xC4BC0C
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_4                                0xC4BC10
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_5                                0xC4BC14
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_6                                0xC4BC18
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_7                                0xC4BC1C
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_8                                0xC4BC20
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_9                                0xC4BC24
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_10                               0xC4BC28
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_11                               0xC4BC2C
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_12                               0xC4BC30
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_13                               0xC4BC34
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_14                               0xC4BC38
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_15                               0xC4BC3C
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_16                               0xC4BC40
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_17                               0xC4BC44
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_18                               0xC4BC48
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_19                               0xC4BC4C
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_20                               0xC4BC50
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_21                               0xC4BC54
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_22                               0xC4BC58
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_23                               0xC4BC5C
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_24                               0xC4BC60
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_25                               0xC4BC64
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_26                               0xC4BC68
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_27                               0xC4BC6C
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_28                               0xC4BC70
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_29                               0xC4BC74
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_30                               0xC4BC78
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_31                               0xC4BC7C
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_32                               0xC4BC80
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_33                               0xC4BC84
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_34                               0xC4BC88
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_35                               0xC4BC8C
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_36                               0xC4BC90
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_37                               0xC4BC94
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_38                               0xC4BC98
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_39                               0xC4BC9C
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_40                               0xC4BCA0
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_41                               0xC4BCA4
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_42                               0xC4BCA8
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_43                               0xC4BCAC
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_44                               0xC4BCB0
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_45                               0xC4BCB4
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_46                               0xC4BCB8
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_47                               0xC4BCBC
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_48                               0xC4BCC0
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_49                               0xC4BCC4
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_50                               0xC4BCC8
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_51                               0xC4BCCC
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_52                               0xC4BCD0
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_53                               0xC4BCD4
+
+#endif /* ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/psoc_timestamp_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/psoc_timestamp_regs.h
new file mode 100644
index 000000000000..9ce24597d4b0
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/psoc_timestamp_regs.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PSOC_TIMESTAMP_REGS_H_
+#define ASIC_REG_PSOC_TIMESTAMP_REGS_H_
+
+/*
+ *****************************************
+ *   PSOC_TIMESTAMP (Prototype: TIMESTAMP)
+ *****************************************
+ */
+
+#define mmPSOC_TIMESTAMP_CNTCR                                       0xC49000
+
+#define mmPSOC_TIMESTAMP_CNTSR                                       0xC49004
+
+#define mmPSOC_TIMESTAMP_CNTCVL                                      0xC49008
+
+#define mmPSOC_TIMESTAMP_CNTCVU                                      0xC4900C
+
+#define mmPSOC_TIMESTAMP_CNTFID0                                     0xC49020
+
+#define mmPSOC_TIMESTAMP_PIDR4                                       0xC49FD0
+
+#define mmPSOC_TIMESTAMP_PIDR5                                       0xC49FD4
+
+#define mmPSOC_TIMESTAMP_PIDR6                                       0xC49FD8
+
+#define mmPSOC_TIMESTAMP_PIDR7                                       0xC49FDC
+
+#define mmPSOC_TIMESTAMP_PIDR0                                       0xC49FE0
+
+#define mmPSOC_TIMESTAMP_PIDR1                                       0xC49FE4
+
+#define mmPSOC_TIMESTAMP_PIDR2                                       0xC49FE8
+
+#define mmPSOC_TIMESTAMP_PIDR3                                       0xC49FEC
+
+#define mmPSOC_TIMESTAMP_CIDR0                                       0xC49FF0
+
+#define mmPSOC_TIMESTAMP_CIDR1                                       0xC49FF4
+
+#define mmPSOC_TIMESTAMP_CIDR2                                       0xC49FF8
+
+#define mmPSOC_TIMESTAMP_CIDR3                                       0xC49FFC
+
+#endif /* ASIC_REG_PSOC_TIMESTAMP_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_0_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_0_regs.h
new file mode 100644
index 000000000000..ddf824392cf7
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_0_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_SIF_RTR_CTRL_0_REGS_H_
+#define ASIC_REG_SIF_RTR_CTRL_0_REGS_H_
+
+/*
+ *****************************************
+ *   SIF_RTR_CTRL_0 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmSIF_RTR_CTRL_0_PERM_SEL                                    0x306108
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_0                               0x306114
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_1                               0x306118
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_2                               0x30611C
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_3                               0x306120
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_4                               0x306124
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_5                               0x306128
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_6                               0x30612C
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_7                               0x306130
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_8                               0x306134
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_9                               0x306138
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_10                              0x30613C
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_11                              0x306140
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_12                              0x306144
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_13                              0x306148
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_14                              0x30614C
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_15                              0x306150
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_16                              0x306154
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_17                              0x306158
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_18                              0x30615C
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_19                              0x306160
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_20                              0x306164
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_21                              0x306168
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_22                              0x30616C
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_23                              0x306170
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_24                              0x306174
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_25                              0x306178
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_26                              0x30617C
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_27                              0x306180
+
+#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_0                              0x306184
+
+#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_1                              0x306188
+
+#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_2                              0x30618C
+
+#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_3                              0x306190
+
+#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_4                              0x306194
+
+#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_5                              0x306198
+
+#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_6                              0x30619C
+
+#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_7                              0x3061A0
+
+#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_8                              0x3061A4
+
+#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_9                              0x3061A8
+
+#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_10                             0x3061AC
+
+#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_11                             0x3061B0
+
+#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_12                             0x3061B4
+
+#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_13                             0x3061B8
+
+#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_14                             0x3061BC
+
+#define mmSIF_RTR_CTRL_0_SCRAM_SRAM_EN                               0x30626C
+
+#define mmSIF_RTR_CTRL_0_RL_HBM_EN                                   0x306274
+
+#define mmSIF_RTR_CTRL_0_RL_HBM_SAT                                  0x306278
+
+#define mmSIF_RTR_CTRL_0_RL_HBM_RST                                  0x30627C
+
+#define mmSIF_RTR_CTRL_0_RL_HBM_TIMEOUT                              0x306280
+
+#define mmSIF_RTR_CTRL_0_SCRAM_HBM_EN                                0x306284
+
+#define mmSIF_RTR_CTRL_0_RL_PCI_EN                                   0x306288
+
+#define mmSIF_RTR_CTRL_0_RL_PCI_SAT                                  0x30628C
+
+#define mmSIF_RTR_CTRL_0_RL_PCI_RST                                  0x306290
+
+#define mmSIF_RTR_CTRL_0_RL_PCI_TIMEOUT                              0x306294
+
+#define mmSIF_RTR_CTRL_0_RL_SRAM_EN                                  0x30629C
+
+#define mmSIF_RTR_CTRL_0_RL_SRAM_SAT                                 0x3062A0
+
+#define mmSIF_RTR_CTRL_0_RL_SRAM_RST                                 0x3062A4
+
+#define mmSIF_RTR_CTRL_0_RL_SRAM_TIMEOUT                             0x3062AC
+
+#define mmSIF_RTR_CTRL_0_RL_SRAM_RED                                 0x3062B4
+
+#define mmSIF_RTR_CTRL_0_E2E_HBM_EN                                  0x3062EC
+
+#define mmSIF_RTR_CTRL_0_E2E_PCI_EN                                  0x3062F0
+
+#define mmSIF_RTR_CTRL_0_E2E_HBM_WR_SIZE                             0x3062F4
+
+#define mmSIF_RTR_CTRL_0_E2E_PCI_WR_SIZE                             0x3062F8
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_PCI_CTR_SET_EN                       0x306404
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_PCI_CTR_SET                          0x306408
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_PCI_CTR_WRAP                         0x30640C
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_PCI_CTR_CNT                          0x306410
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_HBM_CTR_SET_EN                       0x306414
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_HBM_CTR_SET                          0x306418
+
+#define mmSIF_RTR_CTRL_0_E2E_HBM_RD_SIZE                             0x30641C
+
+#define mmSIF_RTR_CTRL_0_E2E_PCI_RD_SIZE                             0x306420
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_PCI_CTR_SET_EN                       0x306424
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_PCI_CTR_SET                          0x306428
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_PCI_CTR_WRAP                         0x30642C
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_PCI_CTR_CNT                          0x306430
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_HBM_CTR_SET_EN                       0x306434
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_HBM_CTR_SET                          0x306438
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_SEL_0                                0x306450
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_SEL_1                                0x306454
+
+#define mmSIF_RTR_CTRL_0_NON_LIN_EN                                  0x306480
+
+#define mmSIF_RTR_CTRL_0_NL_SRAM_BANK_0                              0x306500
+
+#define mmSIF_RTR_CTRL_0_NL_SRAM_BANK_1                              0x306504
+
+#define mmSIF_RTR_CTRL_0_NL_SRAM_BANK_2                              0x306508
+
+#define mmSIF_RTR_CTRL_0_NL_SRAM_BANK_3                              0x30650C
+
+#define mmSIF_RTR_CTRL_0_NL_SRAM_BANK_4                              0x306510
+
+#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_0                            0x306514
+
+#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_1                            0x306520
+
+#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_2                            0x306524
+
+#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_3                            0x306528
+
+#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_4                            0x30652C
+
+#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_5                            0x306530
+
+#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_6                            0x306534
+
+#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_7                            0x306538
+
+#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_8                            0x30653C
+
+#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_9                            0x306540
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_0                             0x306550
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_1                             0x306554
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_2                             0x306558
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_3                             0x30655C
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_4                             0x306560
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_5                             0x306564
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_6                             0x306568
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_7                             0x30656C
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_8                             0x306570
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_9                             0x306574
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_10                            0x306578
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_11                            0x30657C
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_12                            0x306580
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_13                            0x306584
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_14                            0x306588
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_15                            0x30658C
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_16                            0x306590
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_17                            0x306594
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_18                            0x306598
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_0                     0x3065E4
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_1                     0x3065E8
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_2                     0x3065EC
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_3                     0x3065F0
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_4                     0x3065F4
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_5                     0x3065F8
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_6                     0x3065FC
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_7                     0x306600
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_8                     0x306604
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_9                     0x306608
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_10                    0x30660C
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_11                    0x306610
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_12                    0x306614
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_13                    0x306618
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_14                    0x30661C
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_15                    0x306620
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_0                    0x306624
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_1                    0x306628
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_2                    0x30662C
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_3                    0x306630
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_4                    0x306634
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_5                    0x306638
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_6                    0x30663C
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_7                    0x306640
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_8                    0x306644
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_9                    0x306648
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_10                   0x30664C
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_11                   0x306650
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_12                   0x306654
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_13                   0x306658
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_14                   0x30665C
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_15                   0x306660
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_0                     0x306664
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_1                     0x306668
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_2                     0x30666C
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_3                     0x306670
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_4                     0x306674
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_5                     0x306678
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_6                     0x30667C
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_7                     0x306680
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_8                     0x306684
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_9                     0x306688
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_10                    0x30668C
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_11                    0x306690
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_12                    0x306694
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_13                    0x306698
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_14                    0x30669C
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_15                    0x3066A0
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_0                    0x3066A4
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_1                    0x3066A8
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_2                    0x3066AC
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_3                    0x3066B0
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_4                    0x3066B4
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_5                    0x3066B8
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_6                    0x3066BC
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_7                    0x3066C0
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_8                    0x3066C4
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_9                    0x3066C8
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_10                   0x3066CC
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_11                   0x3066D0
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_12                   0x3066D4
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_13                   0x3066D8
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_14                   0x3066DC
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_15                   0x3066E0
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_0                    0x3066E4
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_1                    0x3066E8
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_2                    0x3066EC
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_3                    0x3066F0
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_4                    0x3066F4
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_5                    0x3066F8
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_6                    0x3066FC
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_7                    0x306700
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_8                    0x306704
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_9                    0x306708
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_10                   0x30670C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_11                   0x306710
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_12                   0x306714
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_13                   0x306718
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_14                   0x30671C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_15                   0x306720
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_0                   0x306724
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_1                   0x306728
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_2                   0x30672C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_3                   0x306730
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_4                   0x306734
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_5                   0x306738
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_6                   0x30673C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_7                   0x306740
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_8                   0x306744
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_9                   0x306748
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_10                  0x30674C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_11                  0x306750
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_12                  0x306754
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_13                  0x306758
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_14                  0x30675C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_15                  0x306760
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_0                    0x306764
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_1                    0x306768
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_2                    0x30676C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_3                    0x306770
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_4                    0x306774
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_5                    0x306778
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_6                    0x30677C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_7                    0x306780
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_8                    0x306784
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_9                    0x306788
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_10                   0x30678C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_11                   0x306790
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_12                   0x306794
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_13                   0x306798
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_14                   0x30679C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_15                   0x3067A0
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_0                   0x3067A4
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_1                   0x3067A8
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_2                   0x3067AC
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_3                   0x3067B0
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_4                   0x3067B4
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_5                   0x3067B8
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_6                   0x3067BC
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_7                   0x3067C0
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_8                   0x3067C4
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_9                   0x3067C8
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_10                  0x3067CC
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_11                  0x3067D0
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_12                  0x3067D4
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_13                  0x3067D8
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_14                  0x3067DC
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_15                  0x3067E0
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_0                     0x306824
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_1                     0x306828
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_2                     0x30682C
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_3                     0x306830
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_4                     0x306834
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_5                     0x306838
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_6                     0x30683C
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_7                     0x306840
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_8                     0x306844
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_9                     0x306848
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_10                    0x30684C
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_11                    0x306850
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_12                    0x306854
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_13                    0x306858
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_14                    0x30685C
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_15                    0x306860
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_0                    0x306864
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_1                    0x306868
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_2                    0x30686C
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_3                    0x306870
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_4                    0x306874
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_5                    0x306878
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_6                    0x30687C
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_7                    0x306880
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_8                    0x306884
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_9                    0x306888
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_10                   0x30688C
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_11                   0x306890
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_12                   0x306894
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_13                   0x306898
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_14                   0x30689C
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_15                   0x3068A0
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_0                     0x3068A4
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_1                     0x3068A8
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_2                     0x3068AC
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_3                     0x3068B0
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_4                     0x3068B4
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_5                     0x3068B8
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_6                     0x3068BC
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_7                     0x3068C0
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_8                     0x3068C4
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_9                     0x3068C8
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_10                    0x3068CC
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_11                    0x3068D0
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_12                    0x3068D4
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_13                    0x3068D8
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_14                    0x3068DC
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_15                    0x3068E0
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_0                    0x3068E4
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_1                    0x3068E8
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_2                    0x3068EC
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_3                    0x3068F0
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_4                    0x3068F4
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_5                    0x3068F8
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_6                    0x3068FC
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_7                    0x306900
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_8                    0x306904
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_9                    0x306908
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_10                   0x30690C
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_11                   0x306910
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_12                   0x306914
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_13                   0x306918
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_14                   0x30691C
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_15                   0x306920
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_0                    0x306924
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_1                    0x306928
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_2                    0x30692C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_3                    0x306930
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_4                    0x306934
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_5                    0x306938
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_6                    0x30693C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_7                    0x306940
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_8                    0x306944
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_9                    0x306948
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_10                   0x30694C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_11                   0x306950
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_12                   0x306954
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_13                   0x306958
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_14                   0x30695C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_15                   0x306960
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_0                   0x306964
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_1                   0x306968
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_2                   0x30696C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_3                   0x306970
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_4                   0x306974
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_5                   0x306978
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_6                   0x30697C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_7                   0x306980
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_8                   0x306984
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_9                   0x306988
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_10                  0x30698C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_11                  0x306990
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_12                  0x306994
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_13                  0x306998
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_14                  0x30699C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_15                  0x3069A0
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_0                    0x3069A4
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_1                    0x3069A8
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_2                    0x3069AC
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_3                    0x3069B0
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_4                    0x3069B4
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_5                    0x3069B8
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_6                    0x3069BC
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_7                    0x3069C0
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_8                    0x3069C4
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_9                    0x3069C8
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_10                   0x3069CC
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_11                   0x3069D0
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_12                   0x3069D4
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_13                   0x3069D8
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_14                   0x3069DC
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_15                   0x3069E0
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_0                   0x3069E4
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_1                   0x3069E8
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_2                   0x3069EC
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_3                   0x3069F0
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_4                   0x3069F4
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_5                   0x3069F8
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_6                   0x3069FC
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_7                   0x306A00
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_8                   0x306A04
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_9                   0x306A08
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_10                  0x306A0C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_11                  0x306A10
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_12                  0x306A14
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_13                  0x306A18
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_14                  0x306A1C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_15                  0x306A20
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_HIT_AW                            0x306A64
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_HIT_AR                            0x306A68
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_HIT_AW                           0x306A6C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_HIT_AR                           0x306A70
+
+#define mmSIF_RTR_CTRL_0_RGL_CFG                                     0x306B64
+
+#define mmSIF_RTR_CTRL_0_RGL_SHIFT                                   0x306B68
+
+#define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_0                          0x306B6C
+
+#define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_1                          0x306B70
+
+#define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_2                          0x306B74
+
+#define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_3                          0x306B78
+
+#define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_4                          0x306B7C
+
+#define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_5                          0x306B80
+
+#define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_6                          0x306B84
+
+#define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_7                          0x306B88
+
+#define mmSIF_RTR_CTRL_0_RGL_TOKEN_0                                 0x306BAC
+
+#define mmSIF_RTR_CTRL_0_RGL_TOKEN_1                                 0x306BB0
+
+#define mmSIF_RTR_CTRL_0_RGL_TOKEN_2                                 0x306BB4
+
+#define mmSIF_RTR_CTRL_0_RGL_TOKEN_3                                 0x306BB8
+
+#define mmSIF_RTR_CTRL_0_RGL_TOKEN_4                                 0x306BBC
+
+#define mmSIF_RTR_CTRL_0_RGL_TOKEN_5                                 0x306BC0
+
+#define mmSIF_RTR_CTRL_0_RGL_TOKEN_6                                 0x306BC4
+
+#define mmSIF_RTR_CTRL_0_RGL_TOKEN_7                                 0x306BC8
+
+#define mmSIF_RTR_CTRL_0_RGL_BANK_ID_0                               0x306BEC
+
+#define mmSIF_RTR_CTRL_0_RGL_BANK_ID_1                               0x306BF0
+
+#define mmSIF_RTR_CTRL_0_RGL_BANK_ID_2                               0x306BF4
+
+#define mmSIF_RTR_CTRL_0_RGL_BANK_ID_3                               0x306BF8
+
+#define mmSIF_RTR_CTRL_0_RGL_BANK_ID_4                               0x306BFC
+
+#define mmSIF_RTR_CTRL_0_RGL_BANK_ID_5                               0x306C00
+
+#define mmSIF_RTR_CTRL_0_RGL_BANK_ID_6                               0x306C04
+
+#define mmSIF_RTR_CTRL_0_RGL_BANK_ID_7                               0x306C08
+
+#define mmSIF_RTR_CTRL_0_RGL_WDT                                     0x306C2C
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_HBM0_CH0_CTR_WRAP                    0x306C30
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_HBM0_CH1_CTR_WRAP                    0x306C34
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_HBM1_CH0_CTR_WRAP                    0x306C38
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_HBM1_CH1_CTR_WRAP                    0x306C3C
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_HBM2_CH0_CTR_WRAP                    0x306C40
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_HBM2_CH1_CTR_WRAP                    0x306C44
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_HBM3_CH0_CTR_WRAP                    0x306C48
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_HBM3_CH1_CTR_WRAP                    0x306C4C
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_HBM0_CH0_CTR_CNT                     0x306C50
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_HBM0_CH1_CTR_CNT                     0x306C54
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_HBM1_CH0_CTR_CNT                     0x306C58
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_HBM1_CH1_CTR_CNT                     0x306C5C
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_HBM2_CH0_CTR_CNT                     0x306C60
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_HBM2_CH1_CTR_CNT                     0x306C64
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_HBM3_CH0_CTR_CNT                     0x306C68
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_HBM3_CH1_CTR_CNT                     0x306C6C
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_HBM0_CH0_CTR_WRAP                    0x306C70
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_HBM0_CH1_CTR_WRAP                    0x306C74
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_HBM1_CH0_CTR_WRAP                    0x306C78
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_HBM1_CH1_CTR_WRAP                    0x306C7C
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_HBM2_CH0_CTR_WRAP                    0x306C80
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_HBM2_CH1_CTR_WRAP                    0x306C84
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_HBM3_CH0_CTR_WRAP                    0x306C88
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_HBM3_CH1_CTR_WRAP                    0x306C8C
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_HBM0_CH0_CTR_CNT                     0x306C90
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_HBM0_CH1_CTR_CNT                     0x306C94
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_HBM1_CH0_CTR_CNT                     0x306C98
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_HBM1_CH1_CTR_CNT                     0x306C9C
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_HBM2_CH0_CTR_CNT                     0x306CA0
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_HBM2_CH1_CTR_CNT                     0x306CA4
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_HBM3_CH0_CTR_CNT                     0x306CA8
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_HBM3_CH1_CTR_CNT                     0x306CAC
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_PC_SEL_0                             0x306CB0
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_PC_SEL_1                             0x306CB4
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_PC_SEL_2                             0x306CB8
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_PC_SEL_3                             0x306CBC
+
+#endif /* ASIC_REG_SIF_RTR_CTRL_0_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_1_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_1_regs.h
new file mode 100644
index 000000000000..c6d517dbbd54
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_1_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_SIF_RTR_CTRL_1_REGS_H_
+#define ASIC_REG_SIF_RTR_CTRL_1_REGS_H_
+
+/*
+ *****************************************
+ *   SIF_RTR_CTRL_1 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmSIF_RTR_CTRL_1_PERM_SEL                                    0x316108
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_0                               0x316114
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_1                               0x316118
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_2                               0x31611C
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_3                               0x316120
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_4                               0x316124
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_5                               0x316128
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_6                               0x31612C
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_7                               0x316130
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_8                               0x316134
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_9                               0x316138
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_10                              0x31613C
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_11                              0x316140
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_12                              0x316144
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_13                              0x316148
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_14                              0x31614C
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_15                              0x316150
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_16                              0x316154
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_17                              0x316158
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_18                              0x31615C
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_19                              0x316160
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_20                              0x316164
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_21                              0x316168
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_22                              0x31616C
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_23                              0x316170
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_24                              0x316174
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_25                              0x316178
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_26                              0x31617C
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_27                              0x316180
+
+#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_0                              0x316184
+
+#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_1                              0x316188
+
+#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_2                              0x31618C
+
+#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_3                              0x316190
+
+#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_4                              0x316194
+
+#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_5                              0x316198
+
+#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_6                              0x31619C
+
+#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_7                              0x3161A0
+
+#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_8                              0x3161A4
+
+#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_9                              0x3161A8
+
+#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_10                             0x3161AC
+
+#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_11                             0x3161B0
+
+#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_12                             0x3161B4
+
+#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_13                             0x3161B8
+
+#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_14                             0x3161BC
+
+#define mmSIF_RTR_CTRL_1_SCRAM_SRAM_EN                               0x31626C
+
+#define mmSIF_RTR_CTRL_1_RL_HBM_EN                                   0x316274
+
+#define mmSIF_RTR_CTRL_1_RL_HBM_SAT                                  0x316278
+
+#define mmSIF_RTR_CTRL_1_RL_HBM_RST                                  0x31627C
+
+#define mmSIF_RTR_CTRL_1_RL_HBM_TIMEOUT                              0x316280
+
+#define mmSIF_RTR_CTRL_1_SCRAM_HBM_EN                                0x316284
+
+#define mmSIF_RTR_CTRL_1_RL_PCI_EN                                   0x316288
+
+#define mmSIF_RTR_CTRL_1_RL_PCI_SAT                                  0x31628C
+
+#define mmSIF_RTR_CTRL_1_RL_PCI_RST                                  0x316290
+
+#define mmSIF_RTR_CTRL_1_RL_PCI_TIMEOUT                              0x316294
+
+#define mmSIF_RTR_CTRL_1_RL_SRAM_EN                                  0x31629C
+
+#define mmSIF_RTR_CTRL_1_RL_SRAM_SAT                                 0x3162A0
+
+#define mmSIF_RTR_CTRL_1_RL_SRAM_RST                                 0x3162A4
+
+#define mmSIF_RTR_CTRL_1_RL_SRAM_TIMEOUT                             0x3162AC
+
+#define mmSIF_RTR_CTRL_1_RL_SRAM_RED                                 0x3162B4
+
+#define mmSIF_RTR_CTRL_1_E2E_HBM_EN                                  0x3162EC
+
+#define mmSIF_RTR_CTRL_1_E2E_PCI_EN                                  0x3162F0
+
+#define mmSIF_RTR_CTRL_1_E2E_HBM_WR_SIZE                             0x3162F4
+
+#define mmSIF_RTR_CTRL_1_E2E_PCI_WR_SIZE                             0x3162F8
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_PCI_CTR_SET_EN                       0x316404
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_PCI_CTR_SET                          0x316408
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_PCI_CTR_WRAP                         0x31640C
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_PCI_CTR_CNT                          0x316410
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_HBM_CTR_SET_EN                       0x316414
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_HBM_CTR_SET                          0x316418
+
+#define mmSIF_RTR_CTRL_1_E2E_HBM_RD_SIZE                             0x31641C
+
+#define mmSIF_RTR_CTRL_1_E2E_PCI_RD_SIZE                             0x316420
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_PCI_CTR_SET_EN                       0x316424
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_PCI_CTR_SET                          0x316428
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_PCI_CTR_WRAP                         0x31642C
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_PCI_CTR_CNT                          0x316430
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_HBM_CTR_SET_EN                       0x316434
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_HBM_CTR_SET                          0x316438
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_SEL_0                                0x316450
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_SEL_1                                0x316454
+
+#define mmSIF_RTR_CTRL_1_NON_LIN_EN                                  0x316480
+
+#define mmSIF_RTR_CTRL_1_NL_SRAM_BANK_0                              0x316500
+
+#define mmSIF_RTR_CTRL_1_NL_SRAM_BANK_1                              0x316504
+
+#define mmSIF_RTR_CTRL_1_NL_SRAM_BANK_2                              0x316508
+
+#define mmSIF_RTR_CTRL_1_NL_SRAM_BANK_3                              0x31650C
+
+#define mmSIF_RTR_CTRL_1_NL_SRAM_BANK_4                              0x316510
+
+#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_0                            0x316514
+
+#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_1                            0x316520
+
+#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_2                            0x316524
+
+#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_3                            0x316528
+
+#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_4                            0x31652C
+
+#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_5                            0x316530
+
+#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_6                            0x316534
+
+#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_7                            0x316538
+
+#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_8                            0x31653C
+
+#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_9                            0x316540
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_0                             0x316550
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_1                             0x316554
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_2                             0x316558
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_3                             0x31655C
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_4                             0x316560
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_5                             0x316564
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_6                             0x316568
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_7                             0x31656C
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_8                             0x316570
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_9                             0x316574
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_10                            0x316578
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_11                            0x31657C
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_12                            0x316580
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_13                            0x316584
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_14                            0x316588
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_15                            0x31658C
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_16                            0x316590
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_17                            0x316594
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_18                            0x316598
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_0                     0x3165E4
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_1                     0x3165E8
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_2                     0x3165EC
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_3                     0x3165F0
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_4                     0x3165F4
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_5                     0x3165F8
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_6                     0x3165FC
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_7                     0x316600
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_8                     0x316604
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_9                     0x316608
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_10                    0x31660C
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_11                    0x316610
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_12                    0x316614
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_13                    0x316618
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_14                    0x31661C
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_15                    0x316620
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_0                    0x316624
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_1                    0x316628
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_2                    0x31662C
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_3                    0x316630
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_4                    0x316634
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_5                    0x316638
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_6                    0x31663C
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_7                    0x316640
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_8                    0x316644
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_9                    0x316648
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_10                   0x31664C
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_11                   0x316650
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_12                   0x316654
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_13                   0x316658
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_14                   0x31665C
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_15                   0x316660
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_0                     0x316664
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_1                     0x316668
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_2                     0x31666C
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_3                     0x316670
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_4                     0x316674
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_5                     0x316678
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_6                     0x31667C
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_7                     0x316680
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_8                     0x316684
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_9                     0x316688
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_10                    0x31668C
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_11                    0x316690
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_12                    0x316694
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_13                    0x316698
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_14                    0x31669C
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_15                    0x3166A0
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_0                    0x3166A4
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_1                    0x3166A8
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_2                    0x3166AC
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_3                    0x3166B0
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_4                    0x3166B4
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_5                    0x3166B8
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_6                    0x3166BC
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_7                    0x3166C0
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_8                    0x3166C4
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_9                    0x3166C8
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_10                   0x3166CC
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_11                   0x3166D0
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_12                   0x3166D4
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_13                   0x3166D8
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_14                   0x3166DC
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_15                   0x3166E0
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_0                    0x3166E4
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_1                    0x3166E8
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_2                    0x3166EC
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_3                    0x3166F0
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_4                    0x3166F4
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_5                    0x3166F8
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_6                    0x3166FC
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_7                    0x316700
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_8                    0x316704
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_9                    0x316708
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_10                   0x31670C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_11                   0x316710
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_12                   0x316714
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_13                   0x316718
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_14                   0x31671C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_15                   0x316720
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_0                   0x316724
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_1                   0x316728
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_2                   0x31672C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_3                   0x316730
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_4                   0x316734
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_5                   0x316738
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_6                   0x31673C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_7                   0x316740
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_8                   0x316744
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_9                   0x316748
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_10                  0x31674C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_11                  0x316750
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_12                  0x316754
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_13                  0x316758
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_14                  0x31675C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_15                  0x316760
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_0                    0x316764
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_1                    0x316768
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_2                    0x31676C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_3                    0x316770
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_4                    0x316774
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_5                    0x316778
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_6                    0x31677C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_7                    0x316780
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_8                    0x316784
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_9                    0x316788
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_10                   0x31678C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_11                   0x316790
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_12                   0x316794
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_13                   0x316798
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_14                   0x31679C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_15                   0x3167A0
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_0                   0x3167A4
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_1                   0x3167A8
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_2                   0x3167AC
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_3                   0x3167B0
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_4                   0x3167B4
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_5                   0x3167B8
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_6                   0x3167BC
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_7                   0x3167C0
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_8                   0x3167C4
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_9                   0x3167C8
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_10                  0x3167CC
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_11                  0x3167D0
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_12                  0x3167D4
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_13                  0x3167D8
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_14                  0x3167DC
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_15                  0x3167E0
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_0                     0x316824
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_1                     0x316828
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_2                     0x31682C
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_3                     0x316830
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_4                     0x316834
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_5                     0x316838
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_6                     0x31683C
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_7                     0x316840
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_8                     0x316844
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_9                     0x316848
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_10                    0x31684C
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_11                    0x316850
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_12                    0x316854
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_13                    0x316858
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_14                    0x31685C
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_15                    0x316860
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_0                    0x316864
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_1                    0x316868
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_2                    0x31686C
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_3                    0x316870
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_4                    0x316874
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_5                    0x316878
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_6                    0x31687C
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_7                    0x316880
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_8                    0x316884
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_9                    0x316888
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_10                   0x31688C
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_11                   0x316890
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_12                   0x316894
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_13                   0x316898
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_14                   0x31689C
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_15                   0x3168A0
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_0                     0x3168A4
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_1                     0x3168A8
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_2                     0x3168AC
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_3                     0x3168B0
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_4                     0x3168B4
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_5                     0x3168B8
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_6                     0x3168BC
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_7                     0x3168C0
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_8                     0x3168C4
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_9                     0x3168C8
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_10                    0x3168CC
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_11                    0x3168D0
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_12                    0x3168D4
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_13                    0x3168D8
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_14                    0x3168DC
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_15                    0x3168E0
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_0                    0x3168E4
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_1                    0x3168E8
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_2                    0x3168EC
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_3                    0x3168F0
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_4                    0x3168F4
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_5                    0x3168F8
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_6                    0x3168FC
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_7                    0x316900
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_8                    0x316904
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_9                    0x316908
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_10                   0x31690C
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_11                   0x316910
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_12                   0x316914
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_13                   0x316918
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_14                   0x31691C
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_15                   0x316920
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_0                    0x316924
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_1                    0x316928
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_2                    0x31692C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_3                    0x316930
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_4                    0x316934
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_5                    0x316938
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_6                    0x31693C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_7                    0x316940
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_8                    0x316944
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_9                    0x316948
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_10                   0x31694C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_11                   0x316950
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_12                   0x316954
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_13                   0x316958
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_14                   0x31695C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_15                   0x316960
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_0                   0x316964
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_1                   0x316968
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_2                   0x31696C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_3                   0x316970
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_4                   0x316974
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_5                   0x316978
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_6                   0x31697C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_7                   0x316980
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_8                   0x316984
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_9                   0x316988
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_10                  0x31698C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_11                  0x316990
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_12                  0x316994
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_13                  0x316998
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_14                  0x31699C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_15                  0x3169A0
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_0                    0x3169A4
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_1                    0x3169A8
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_2                    0x3169AC
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_3                    0x3169B0
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_4                    0x3169B4
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_5                    0x3169B8
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_6                    0x3169BC
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_7                    0x3169C0
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_8                    0x3169C4
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_9                    0x3169C8
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_10                   0x3169CC
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_11                   0x3169D0
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_12                   0x3169D4
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_13                   0x3169D8
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_14                   0x3169DC
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_15                   0x3169E0
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_0                   0x3169E4
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_1                   0x3169E8
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_2                   0x3169EC
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_3                   0x3169F0
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_4                   0x3169F4
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_5                   0x3169F8
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_6                   0x3169FC
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_7                   0x316A00
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_8                   0x316A04
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_9                   0x316A08
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_10                  0x316A0C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_11                  0x316A10
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_12                  0x316A14
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_13                  0x316A18
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_14                  0x316A1C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_15                  0x316A20
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_HIT_AW                            0x316A64
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_HIT_AR                            0x316A68
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_HIT_AW                           0x316A6C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_HIT_AR                           0x316A70
+
+#define mmSIF_RTR_CTRL_1_RGL_CFG                                     0x316B64
+
+#define mmSIF_RTR_CTRL_1_RGL_SHIFT                                   0x316B68
+
+#define mmSIF_RTR_CTRL_1_RGL_EXPECTED_LAT_0                          0x316B6C
+
+#define mmSIF_RTR_CTRL_1_RGL_EXPECTED_LAT_1                          0x316B70
+
+#define mmSIF_RTR_CTRL_1_RGL_EXPECTED_LAT_2                          0x316B74
+
+#define mmSIF_RTR_CTRL_1_RGL_EXPECTED_LAT_3                          0x316B78
+
+#define mmSIF_RTR_CTRL_1_RGL_EXPECTED_LAT_4                          0x316B7C
+
+#define mmSIF_RTR_CTRL_1_RGL_EXPECTED_LAT_5                          0x316B80
+
+#define mmSIF_RTR_CTRL_1_RGL_EXPECTED_LAT_6                          0x316B84
+
+#define mmSIF_RTR_CTRL_1_RGL_EXPECTED_LAT_7                          0x316B88
+
+#define mmSIF_RTR_CTRL_1_RGL_TOKEN_0                                 0x316BAC
+
+#define mmSIF_RTR_CTRL_1_RGL_TOKEN_1                                 0x316BB0
+
+#define mmSIF_RTR_CTRL_1_RGL_TOKEN_2                                 0x316BB4
+
+#define mmSIF_RTR_CTRL_1_RGL_TOKEN_3                                 0x316BB8
+
+#define mmSIF_RTR_CTRL_1_RGL_TOKEN_4                                 0x316BBC
+
+#define mmSIF_RTR_CTRL_1_RGL_TOKEN_5                                 0x316BC0
+
+#define mmSIF_RTR_CTRL_1_RGL_TOKEN_6                                 0x316BC4
+
+#define mmSIF_RTR_CTRL_1_RGL_TOKEN_7                                 0x316BC8
+
+#define mmSIF_RTR_CTRL_1_RGL_BANK_ID_0                               0x316BEC
+
+#define mmSIF_RTR_CTRL_1_RGL_BANK_ID_1                               0x316BF0
+
+#define mmSIF_RTR_CTRL_1_RGL_BANK_ID_2                               0x316BF4
+
+#define mmSIF_RTR_CTRL_1_RGL_BANK_ID_3                               0x316BF8
+
+#define mmSIF_RTR_CTRL_1_RGL_BANK_ID_4                               0x316BFC
+
+#define mmSIF_RTR_CTRL_1_RGL_BANK_ID_5                               0x316C00
+
+#define mmSIF_RTR_CTRL_1_RGL_BANK_ID_6                               0x316C04
+
+#define mmSIF_RTR_CTRL_1_RGL_BANK_ID_7                               0x316C08
+
+#define mmSIF_RTR_CTRL_1_RGL_WDT                                     0x316C2C
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_HBM0_CH0_CTR_WRAP                    0x316C30
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_HBM0_CH1_CTR_WRAP                    0x316C34
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_HBM1_CH0_CTR_WRAP                    0x316C38
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_HBM1_CH1_CTR_WRAP                    0x316C3C
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_HBM2_CH0_CTR_WRAP                    0x316C40
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_HBM2_CH1_CTR_WRAP                    0x316C44
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_HBM3_CH0_CTR_WRAP                    0x316C48
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_HBM3_CH1_CTR_WRAP                    0x316C4C
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_HBM0_CH0_CTR_CNT                     0x316C50
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_HBM0_CH1_CTR_CNT                     0x316C54
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_HBM1_CH0_CTR_CNT                     0x316C58
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_HBM1_CH1_CTR_CNT                     0x316C5C
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_HBM2_CH0_CTR_CNT                     0x316C60
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_HBM2_CH1_CTR_CNT                     0x316C64
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_HBM3_CH0_CTR_CNT                     0x316C68
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_HBM3_CH1_CTR_CNT                     0x316C6C
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_HBM0_CH0_CTR_WRAP                    0x316C70
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_HBM0_CH1_CTR_WRAP                    0x316C74
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_HBM1_CH0_CTR_WRAP                    0x316C78
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_HBM1_CH1_CTR_WRAP                    0x316C7C
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_HBM2_CH0_CTR_WRAP                    0x316C80
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_HBM2_CH1_CTR_WRAP                    0x316C84
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_HBM3_CH0_CTR_WRAP                    0x316C88
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_HBM3_CH1_CTR_WRAP                    0x316C8C
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_HBM0_CH0_CTR_CNT                     0x316C90
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_HBM0_CH1_CTR_CNT                     0x316C94
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_HBM1_CH0_CTR_CNT                     0x316C98
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_HBM1_CH1_CTR_CNT                     0x316C9C
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_HBM2_CH0_CTR_CNT                     0x316CA0
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_HBM2_CH1_CTR_CNT                     0x316CA4
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_HBM3_CH0_CTR_CNT                     0x316CA8
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_HBM3_CH1_CTR_CNT                     0x316CAC
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_PC_SEL_0                             0x316CB0
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_PC_SEL_1                             0x316CB4
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_PC_SEL_2                             0x316CB8
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_PC_SEL_3                             0x316CBC
+
+#endif /* ASIC_REG_SIF_RTR_CTRL_1_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_2_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_2_regs.h
new file mode 100644
index 000000000000..330e5b42d679
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_2_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_SIF_RTR_CTRL_2_REGS_H_
+#define ASIC_REG_SIF_RTR_CTRL_2_REGS_H_
+
+/*
+ *****************************************
+ *   SIF_RTR_CTRL_2 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmSIF_RTR_CTRL_2_PERM_SEL                                    0x326108
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_0                               0x326114
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_1                               0x326118
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_2                               0x32611C
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_3                               0x326120
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_4                               0x326124
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_5                               0x326128
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_6                               0x32612C
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_7                               0x326130
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_8                               0x326134
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_9                               0x326138
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_10                              0x32613C
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_11                              0x326140
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_12                              0x326144
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_13                              0x326148
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_14                              0x32614C
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_15                              0x326150
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_16                              0x326154
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_17                              0x326158
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_18                              0x32615C
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_19                              0x326160
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_20                              0x326164
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_21                              0x326168
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_22                              0x32616C
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_23                              0x326170
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_24                              0x326174
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_25                              0x326178
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_26                              0x32617C
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_27                              0x326180
+
+#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_0                              0x326184
+
+#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_1                              0x326188
+
+#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_2                              0x32618C
+
+#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_3                              0x326190
+
+#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_4                              0x326194
+
+#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_5                              0x326198
+
+#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_6                              0x32619C
+
+#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_7                              0x3261A0
+
+#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_8                              0x3261A4
+
+#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_9                              0x3261A8
+
+#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_10                             0x3261AC
+
+#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_11                             0x3261B0
+
+#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_12                             0x3261B4
+
+#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_13                             0x3261B8
+
+#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_14                             0x3261BC
+
+#define mmSIF_RTR_CTRL_2_SCRAM_SRAM_EN                               0x32626C
+
+#define mmSIF_RTR_CTRL_2_RL_HBM_EN                                   0x326274
+
+#define mmSIF_RTR_CTRL_2_RL_HBM_SAT                                  0x326278
+
+#define mmSIF_RTR_CTRL_2_RL_HBM_RST                                  0x32627C
+
+#define mmSIF_RTR_CTRL_2_RL_HBM_TIMEOUT                              0x326280
+
+#define mmSIF_RTR_CTRL_2_SCRAM_HBM_EN                                0x326284
+
+#define mmSIF_RTR_CTRL_2_RL_PCI_EN                                   0x326288
+
+#define mmSIF_RTR_CTRL_2_RL_PCI_SAT                                  0x32628C
+
+#define mmSIF_RTR_CTRL_2_RL_PCI_RST                                  0x326290
+
+#define mmSIF_RTR_CTRL_2_RL_PCI_TIMEOUT                              0x326294
+
+#define mmSIF_RTR_CTRL_2_RL_SRAM_EN                                  0x32629C
+
+#define mmSIF_RTR_CTRL_2_RL_SRAM_SAT                                 0x3262A0
+
+#define mmSIF_RTR_CTRL_2_RL_SRAM_RST                                 0x3262A4
+
+#define mmSIF_RTR_CTRL_2_RL_SRAM_TIMEOUT                             0x3262AC
+
+#define mmSIF_RTR_CTRL_2_RL_SRAM_RED                                 0x3262B4
+
+#define mmSIF_RTR_CTRL_2_E2E_HBM_EN                                  0x3262EC
+
+#define mmSIF_RTR_CTRL_2_E2E_PCI_EN                                  0x3262F0
+
+#define mmSIF_RTR_CTRL_2_E2E_HBM_WR_SIZE                             0x3262F4
+
+#define mmSIF_RTR_CTRL_2_E2E_PCI_WR_SIZE                             0x3262F8
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_PCI_CTR_SET_EN                       0x326404
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_PCI_CTR_SET                          0x326408
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_PCI_CTR_WRAP                         0x32640C
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_PCI_CTR_CNT                          0x326410
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_HBM_CTR_SET_EN                       0x326414
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_HBM_CTR_SET                          0x326418
+
+#define mmSIF_RTR_CTRL_2_E2E_HBM_RD_SIZE                             0x32641C
+
+#define mmSIF_RTR_CTRL_2_E2E_PCI_RD_SIZE                             0x326420
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_PCI_CTR_SET_EN                       0x326424
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_PCI_CTR_SET                          0x326428
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_PCI_CTR_WRAP                         0x32642C
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_PCI_CTR_CNT                          0x326430
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_HBM_CTR_SET_EN                       0x326434
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_HBM_CTR_SET                          0x326438
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_SEL_0                                0x326450
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_SEL_1                                0x326454
+
+#define mmSIF_RTR_CTRL_2_NON_LIN_EN                                  0x326480
+
+#define mmSIF_RTR_CTRL_2_NL_SRAM_BANK_0                              0x326500
+
+#define mmSIF_RTR_CTRL_2_NL_SRAM_BANK_1                              0x326504
+
+#define mmSIF_RTR_CTRL_2_NL_SRAM_BANK_2                              0x326508
+
+#define mmSIF_RTR_CTRL_2_NL_SRAM_BANK_3                              0x32650C
+
+#define mmSIF_RTR_CTRL_2_NL_SRAM_BANK_4                              0x326510
+
+#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_0                            0x326514
+
+#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_1                            0x326520
+
+#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_2                            0x326524
+
+#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_3                            0x326528
+
+#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_4                            0x32652C
+
+#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_5                            0x326530
+
+#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_6                            0x326534
+
+#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_7                            0x326538
+
+#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_8                            0x32653C
+
+#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_9                            0x326540
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_0                             0x326550
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_1                             0x326554
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_2                             0x326558
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_3                             0x32655C
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_4                             0x326560
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_5                             0x326564
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_6                             0x326568
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_7                             0x32656C
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_8                             0x326570
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_9                             0x326574
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_10                            0x326578
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_11                            0x32657C
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_12                            0x326580
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_13                            0x326584
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_14                            0x326588
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_15                            0x32658C
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_16                            0x326590
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_17                            0x326594
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_18                            0x326598
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_0                     0x3265E4
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_1                     0x3265E8
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_2                     0x3265EC
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_3                     0x3265F0
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_4                     0x3265F4
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_5                     0x3265F8
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_6                     0x3265FC
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_7                     0x326600
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_8                     0x326604
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_9                     0x326608
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_10                    0x32660C
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_11                    0x326610
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_12                    0x326614
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_13                    0x326618
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_14                    0x32661C
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_15                    0x326620
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_0                    0x326624
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_1                    0x326628
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_2                    0x32662C
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_3                    0x326630
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_4                    0x326634
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_5                    0x326638
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_6                    0x32663C
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_7                    0x326640
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_8                    0x326644
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_9                    0x326648
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_10                   0x32664C
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_11                   0x326650
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_12                   0x326654
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_13                   0x326658
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_14                   0x32665C
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_15                   0x326660
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_0                     0x326664
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_1                     0x326668
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_2                     0x32666C
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_3                     0x326670
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_4                     0x326674
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_5                     0x326678
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_6                     0x32667C
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_7                     0x326680
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_8                     0x326684
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_9                     0x326688
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_10                    0x32668C
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_11                    0x326690
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_12                    0x326694
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_13                    0x326698
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_14                    0x32669C
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_15                    0x3266A0
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_0                    0x3266A4
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_1                    0x3266A8
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_2                    0x3266AC
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_3                    0x3266B0
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_4                    0x3266B4
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_5                    0x3266B8
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_6                    0x3266BC
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_7                    0x3266C0
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_8                    0x3266C4
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_9                    0x3266C8
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_10                   0x3266CC
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_11                   0x3266D0
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_12                   0x3266D4
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_13                   0x3266D8
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_14                   0x3266DC
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_15                   0x3266E0
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_0                    0x3266E4
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_1                    0x3266E8
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_2                    0x3266EC
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_3                    0x3266F0
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_4                    0x3266F4
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_5                    0x3266F8
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_6                    0x3266FC
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_7                    0x326700
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_8                    0x326704
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_9                    0x326708
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_10                   0x32670C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_11                   0x326710
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_12                   0x326714
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_13                   0x326718
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_14                   0x32671C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_15                   0x326720
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_0                   0x326724
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_1                   0x326728
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_2                   0x32672C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_3                   0x326730
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_4                   0x326734
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_5                   0x326738
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_6                   0x32673C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_7                   0x326740
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_8                   0x326744
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_9                   0x326748
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_10                  0x32674C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_11                  0x326750
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_12                  0x326754
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_13                  0x326758
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_14                  0x32675C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_15                  0x326760
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_0                    0x326764
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_1                    0x326768
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_2                    0x32676C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_3                    0x326770
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_4                    0x326774
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_5                    0x326778
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_6                    0x32677C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_7                    0x326780
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_8                    0x326784
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_9                    0x326788
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_10                   0x32678C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_11                   0x326790
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_12                   0x326794
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_13                   0x326798
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_14                   0x32679C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_15                   0x3267A0
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_0                   0x3267A4
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_1                   0x3267A8
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_2                   0x3267AC
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_3                   0x3267B0
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_4                   0x3267B4
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_5                   0x3267B8
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_6                   0x3267BC
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_7                   0x3267C0
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_8                   0x3267C4
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_9                   0x3267C8
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_10                  0x3267CC
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_11                  0x3267D0
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_12                  0x3267D4
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_13                  0x3267D8
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_14                  0x3267DC
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_15                  0x3267E0
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_0                     0x326824
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_1                     0x326828
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_2                     0x32682C
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_3                     0x326830
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_4                     0x326834
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_5                     0x326838
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_6                     0x32683C
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_7                     0x326840
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_8                     0x326844
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_9                     0x326848
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_10                    0x32684C
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_11                    0x326850
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_12                    0x326854
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_13                    0x326858
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_14                    0x32685C
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_15                    0x326860
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_0                    0x326864
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_1                    0x326868
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_2                    0x32686C
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_3                    0x326870
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_4                    0x326874
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_5                    0x326878
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_6                    0x32687C
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_7                    0x326880
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_8                    0x326884
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_9                    0x326888
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_10                   0x32688C
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_11                   0x326890
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_12                   0x326894
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_13                   0x326898
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_14                   0x32689C
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_15                   0x3268A0
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_0                     0x3268A4
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_1                     0x3268A8
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_2                     0x3268AC
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_3                     0x3268B0
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_4                     0x3268B4
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_5                     0x3268B8
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_6                     0x3268BC
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_7                     0x3268C0
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_8                     0x3268C4
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_9                     0x3268C8
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_10                    0x3268CC
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_11                    0x3268D0
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_12                    0x3268D4
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_13                    0x3268D8
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_14                    0x3268DC
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_15                    0x3268E0
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_0                    0x3268E4
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_1                    0x3268E8
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_2                    0x3268EC
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_3                    0x3268F0
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_4                    0x3268F4
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_5                    0x3268F8
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_6                    0x3268FC
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_7                    0x326900
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_8                    0x326904
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_9                    0x326908
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_10                   0x32690C
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_11                   0x326910
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_12                   0x326914
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_13                   0x326918
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_14                   0x32691C
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_15                   0x326920
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_0                    0x326924
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_1                    0x326928
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_2                    0x32692C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_3                    0x326930
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_4                    0x326934
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_5                    0x326938
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_6                    0x32693C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_7                    0x326940
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_8                    0x326944
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_9                    0x326948
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_10                   0x32694C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_11                   0x326950
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_12                   0x326954
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_13                   0x326958
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_14                   0x32695C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_15                   0x326960
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_0                   0x326964
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_1                   0x326968
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_2                   0x32696C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_3                   0x326970
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_4                   0x326974
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_5                   0x326978
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_6                   0x32697C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_7                   0x326980
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_8                   0x326984
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_9                   0x326988
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_10                  0x32698C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_11                  0x326990
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_12                  0x326994
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_13                  0x326998
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_14                  0x32699C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_15                  0x3269A0
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_0                    0x3269A4
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_1                    0x3269A8
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_2                    0x3269AC
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_3                    0x3269B0
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_4                    0x3269B4
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_5                    0x3269B8
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_6                    0x3269BC
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_7                    0x3269C0
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_8                    0x3269C4
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_9                    0x3269C8
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_10                   0x3269CC
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_11                   0x3269D0
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_12                   0x3269D4
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_13                   0x3269D8
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_14                   0x3269DC
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_15                   0x3269E0
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_0                   0x3269E4
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_1                   0x3269E8
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_2                   0x3269EC
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_3                   0x3269F0
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_4                   0x3269F4
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_5                   0x3269F8
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_6                   0x3269FC
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_7                   0x326A00
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_8                   0x326A04
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_9                   0x326A08
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_10                  0x326A0C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_11                  0x326A10
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_12                  0x326A14
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_13                  0x326A18
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_14                  0x326A1C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_15                  0x326A20
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_HIT_AW                            0x326A64
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_HIT_AR                            0x326A68
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_HIT_AW                           0x326A6C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_HIT_AR                           0x326A70
+
+#define mmSIF_RTR_CTRL_2_RGL_CFG                                     0x326B64
+
+#define mmSIF_RTR_CTRL_2_RGL_SHIFT                                   0x326B68
+
+#define mmSIF_RTR_CTRL_2_RGL_EXPECTED_LAT_0                          0x326B6C
+
+#define mmSIF_RTR_CTRL_2_RGL_EXPECTED_LAT_1                          0x326B70
+
+#define mmSIF_RTR_CTRL_2_RGL_EXPECTED_LAT_2                          0x326B74
+
+#define mmSIF_RTR_CTRL_2_RGL_EXPECTED_LAT_3                          0x326B78
+
+#define mmSIF_RTR_CTRL_2_RGL_EXPECTED_LAT_4                          0x326B7C
+
+#define mmSIF_RTR_CTRL_2_RGL_EXPECTED_LAT_5                          0x326B80
+
+#define mmSIF_RTR_CTRL_2_RGL_EXPECTED_LAT_6                          0x326B84
+
+#define mmSIF_RTR_CTRL_2_RGL_EXPECTED_LAT_7                          0x326B88
+
+#define mmSIF_RTR_CTRL_2_RGL_TOKEN_0                                 0x326BAC
+
+#define mmSIF_RTR_CTRL_2_RGL_TOKEN_1                                 0x326BB0
+
+#define mmSIF_RTR_CTRL_2_RGL_TOKEN_2                                 0x326BB4
+
+#define mmSIF_RTR_CTRL_2_RGL_TOKEN_3                                 0x326BB8
+
+#define mmSIF_RTR_CTRL_2_RGL_TOKEN_4                                 0x326BBC
+
+#define mmSIF_RTR_CTRL_2_RGL_TOKEN_5                                 0x326BC0
+
+#define mmSIF_RTR_CTRL_2_RGL_TOKEN_6                                 0x326BC4
+
+#define mmSIF_RTR_CTRL_2_RGL_TOKEN_7                                 0x326BC8
+
+#define mmSIF_RTR_CTRL_2_RGL_BANK_ID_0                               0x326BEC
+
+#define mmSIF_RTR_CTRL_2_RGL_BANK_ID_1                               0x326BF0
+
+#define mmSIF_RTR_CTRL_2_RGL_BANK_ID_2                               0x326BF4
+
+#define mmSIF_RTR_CTRL_2_RGL_BANK_ID_3                               0x326BF8
+
+#define mmSIF_RTR_CTRL_2_RGL_BANK_ID_4                               0x326BFC
+
+#define mmSIF_RTR_CTRL_2_RGL_BANK_ID_5                               0x326C00
+
+#define mmSIF_RTR_CTRL_2_RGL_BANK_ID_6                               0x326C04
+
+#define mmSIF_RTR_CTRL_2_RGL_BANK_ID_7                               0x326C08
+
+#define mmSIF_RTR_CTRL_2_RGL_WDT                                     0x326C2C
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_HBM0_CH0_CTR_WRAP                    0x326C30
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_HBM0_CH1_CTR_WRAP                    0x326C34
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_HBM1_CH0_CTR_WRAP                    0x326C38
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_HBM1_CH1_CTR_WRAP                    0x326C3C
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_HBM2_CH0_CTR_WRAP                    0x326C40
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_HBM2_CH1_CTR_WRAP                    0x326C44
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_HBM3_CH0_CTR_WRAP                    0x326C48
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_HBM3_CH1_CTR_WRAP                    0x326C4C
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_HBM0_CH0_CTR_CNT                     0x326C50
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_HBM0_CH1_CTR_CNT                     0x326C54
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_HBM1_CH0_CTR_CNT                     0x326C58
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_HBM1_CH1_CTR_CNT                     0x326C5C
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_HBM2_CH0_CTR_CNT                     0x326C60
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_HBM2_CH1_CTR_CNT                     0x326C64
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_HBM3_CH0_CTR_CNT                     0x326C68
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_HBM3_CH1_CTR_CNT                     0x326C6C
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_HBM0_CH0_CTR_WRAP                    0x326C70
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_HBM0_CH1_CTR_WRAP                    0x326C74
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_HBM1_CH0_CTR_WRAP                    0x326C78
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_HBM1_CH1_CTR_WRAP                    0x326C7C
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_HBM2_CH0_CTR_WRAP                    0x326C80
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_HBM2_CH1_CTR_WRAP                    0x326C84
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_HBM3_CH0_CTR_WRAP                    0x326C88
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_HBM3_CH1_CTR_WRAP                    0x326C8C
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_HBM0_CH0_CTR_CNT                     0x326C90
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_HBM0_CH1_CTR_CNT                     0x326C94
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_HBM1_CH0_CTR_CNT                     0x326C98
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_HBM1_CH1_CTR_CNT                     0x326C9C
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_HBM2_CH0_CTR_CNT                     0x326CA0
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_HBM2_CH1_CTR_CNT                     0x326CA4
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_HBM3_CH0_CTR_CNT                     0x326CA8
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_HBM3_CH1_CTR_CNT                     0x326CAC
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_PC_SEL_0                             0x326CB0
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_PC_SEL_1                             0x326CB4
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_PC_SEL_2                             0x326CB8
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_PC_SEL_3                             0x326CBC
+
+#endif /* ASIC_REG_SIF_RTR_CTRL_2_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_3_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_3_regs.h
new file mode 100644
index 000000000000..d749f1968e5e
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_3_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_SIF_RTR_CTRL_3_REGS_H_
+#define ASIC_REG_SIF_RTR_CTRL_3_REGS_H_
+
+/*
+ *****************************************
+ *   SIF_RTR_CTRL_3 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmSIF_RTR_CTRL_3_PERM_SEL                                    0x336108
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_0                               0x336114
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_1                               0x336118
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_2                               0x33611C
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_3                               0x336120
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_4                               0x336124
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_5                               0x336128
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_6                               0x33612C
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_7                               0x336130
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_8                               0x336134
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_9                               0x336138
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_10                              0x33613C
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_11                              0x336140
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_12                              0x336144
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_13                              0x336148
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_14                              0x33614C
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_15                              0x336150
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_16                              0x336154
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_17                              0x336158
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_18                              0x33615C
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_19                              0x336160
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_20                              0x336164
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_21                              0x336168
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_22                              0x33616C
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_23                              0x336170
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_24                              0x336174
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_25                              0x336178
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_26                              0x33617C
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_27                              0x336180
+
+#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_0                              0x336184
+
+#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_1                              0x336188
+
+#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_2                              0x33618C
+
+#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_3                              0x336190
+
+#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_4                              0x336194
+
+#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_5                              0x336198
+
+#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_6                              0x33619C
+
+#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_7                              0x3361A0
+
+#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_8                              0x3361A4
+
+#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_9                              0x3361A8
+
+#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_10                             0x3361AC
+
+#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_11                             0x3361B0
+
+#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_12                             0x3361B4
+
+#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_13                             0x3361B8
+
+#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_14                             0x3361BC
+
+#define mmSIF_RTR_CTRL_3_SCRAM_SRAM_EN                               0x33626C
+
+#define mmSIF_RTR_CTRL_3_RL_HBM_EN                                   0x336274
+
+#define mmSIF_RTR_CTRL_3_RL_HBM_SAT                                  0x336278
+
+#define mmSIF_RTR_CTRL_3_RL_HBM_RST                                  0x33627C
+
+#define mmSIF_RTR_CTRL_3_RL_HBM_TIMEOUT                              0x336280
+
+#define mmSIF_RTR_CTRL_3_SCRAM_HBM_EN                                0x336284
+
+#define mmSIF_RTR_CTRL_3_RL_PCI_EN                                   0x336288
+
+#define mmSIF_RTR_CTRL_3_RL_PCI_SAT                                  0x33628C
+
+#define mmSIF_RTR_CTRL_3_RL_PCI_RST                                  0x336290
+
+#define mmSIF_RTR_CTRL_3_RL_PCI_TIMEOUT                              0x336294
+
+#define mmSIF_RTR_CTRL_3_RL_SRAM_EN                                  0x33629C
+
+#define mmSIF_RTR_CTRL_3_RL_SRAM_SAT                                 0x3362A0
+
+#define mmSIF_RTR_CTRL_3_RL_SRAM_RST                                 0x3362A4
+
+#define mmSIF_RTR_CTRL_3_RL_SRAM_TIMEOUT                             0x3362AC
+
+#define mmSIF_RTR_CTRL_3_RL_SRAM_RED                                 0x3362B4
+
+#define mmSIF_RTR_CTRL_3_E2E_HBM_EN                                  0x3362EC
+
+#define mmSIF_RTR_CTRL_3_E2E_PCI_EN                                  0x3362F0
+
+#define mmSIF_RTR_CTRL_3_E2E_HBM_WR_SIZE                             0x3362F4
+
+#define mmSIF_RTR_CTRL_3_E2E_PCI_WR_SIZE                             0x3362F8
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_PCI_CTR_SET_EN                       0x336404
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_PCI_CTR_SET                          0x336408
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_PCI_CTR_WRAP                         0x33640C
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_PCI_CTR_CNT                          0x336410
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_HBM_CTR_SET_EN                       0x336414
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_HBM_CTR_SET                          0x336418
+
+#define mmSIF_RTR_CTRL_3_E2E_HBM_RD_SIZE                             0x33641C
+
+#define mmSIF_RTR_CTRL_3_E2E_PCI_RD_SIZE                             0x336420
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_PCI_CTR_SET_EN                       0x336424
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_PCI_CTR_SET                          0x336428
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_PCI_CTR_WRAP                         0x33642C
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_PCI_CTR_CNT                          0x336430
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_HBM_CTR_SET_EN                       0x336434
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_HBM_CTR_SET                          0x336438
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_SEL_0                                0x336450
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_SEL_1                                0x336454
+
+#define mmSIF_RTR_CTRL_3_NON_LIN_EN                                  0x336480
+
+#define mmSIF_RTR_CTRL_3_NL_SRAM_BANK_0                              0x336500
+
+#define mmSIF_RTR_CTRL_3_NL_SRAM_BANK_1                              0x336504
+
+#define mmSIF_RTR_CTRL_3_NL_SRAM_BANK_2                              0x336508
+
+#define mmSIF_RTR_CTRL_3_NL_SRAM_BANK_3                              0x33650C
+
+#define mmSIF_RTR_CTRL_3_NL_SRAM_BANK_4                              0x336510
+
+#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_0                            0x336514
+
+#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_1                            0x336520
+
+#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_2                            0x336524
+
+#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_3                            0x336528
+
+#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_4                            0x33652C
+
+#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_5                            0x336530
+
+#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_6                            0x336534
+
+#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_7                            0x336538
+
+#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_8                            0x33653C
+
+#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_9                            0x336540
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_0                             0x336550
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_1                             0x336554
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_2                             0x336558
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_3                             0x33655C
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_4                             0x336560
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_5                             0x336564
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_6                             0x336568
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_7                             0x33656C
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_8                             0x336570
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_9                             0x336574
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_10                            0x336578
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_11                            0x33657C
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_12                            0x336580
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_13                            0x336584
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_14                            0x336588
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_15                            0x33658C
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_16                            0x336590
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_17                            0x336594
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_18                            0x336598
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_0                     0x3365E4
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_1                     0x3365E8
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_2                     0x3365EC
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_3                     0x3365F0
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_4                     0x3365F4
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_5                     0x3365F8
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_6                     0x3365FC
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_7                     0x336600
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_8                     0x336604
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_9                     0x336608
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_10                    0x33660C
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_11                    0x336610
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_12                    0x336614
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_13                    0x336618
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_14                    0x33661C
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_15                    0x336620
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_0                    0x336624
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_1                    0x336628
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_2                    0x33662C
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_3                    0x336630
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_4                    0x336634
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_5                    0x336638
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_6                    0x33663C
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_7                    0x336640
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_8                    0x336644
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_9                    0x336648
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_10                   0x33664C
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_11                   0x336650
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_12                   0x336654
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_13                   0x336658
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_14                   0x33665C
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_15                   0x336660
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_0                     0x336664
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_1                     0x336668
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_2                     0x33666C
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_3                     0x336670
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_4                     0x336674
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_5                     0x336678
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_6                     0x33667C
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_7                     0x336680
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_8                     0x336684
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_9                     0x336688
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_10                    0x33668C
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_11                    0x336690
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_12                    0x336694
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_13                    0x336698
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_14                    0x33669C
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_15                    0x3366A0
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_0                    0x3366A4
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_1                    0x3366A8
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_2                    0x3366AC
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_3                    0x3366B0
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_4                    0x3366B4
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_5                    0x3366B8
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_6                    0x3366BC
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_7                    0x3366C0
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_8                    0x3366C4
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_9                    0x3366C8
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_10                   0x3366CC
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_11                   0x3366D0
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_12                   0x3366D4
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_13                   0x3366D8
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_14                   0x3366DC
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_15                   0x3366E0
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_0                    0x3366E4
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_1                    0x3366E8
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_2                    0x3366EC
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_3                    0x3366F0
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_4                    0x3366F4
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_5                    0x3366F8
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_6                    0x3366FC
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_7                    0x336700
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_8                    0x336704
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_9                    0x336708
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_10                   0x33670C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_11                   0x336710
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_12                   0x336714
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_13                   0x336718
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_14                   0x33671C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_15                   0x336720
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_0                   0x336724
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_1                   0x336728
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_2                   0x33672C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_3                   0x336730
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_4                   0x336734
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_5                   0x336738
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_6                   0x33673C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_7                   0x336740
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_8                   0x336744
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_9                   0x336748
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_10                  0x33674C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_11                  0x336750
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_12                  0x336754
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_13                  0x336758
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_14                  0x33675C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_15                  0x336760
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_0                    0x336764
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_1                    0x336768
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_2                    0x33676C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_3                    0x336770
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_4                    0x336774
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_5                    0x336778
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_6                    0x33677C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_7                    0x336780
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_8                    0x336784
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_9                    0x336788
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_10                   0x33678C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_11                   0x336790
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_12                   0x336794
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_13                   0x336798
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_14                   0x33679C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_15                   0x3367A0
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_0                   0x3367A4
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_1                   0x3367A8
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_2                   0x3367AC
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_3                   0x3367B0
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_4                   0x3367B4
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_5                   0x3367B8
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_6                   0x3367BC
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_7                   0x3367C0
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_8                   0x3367C4
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_9                   0x3367C8
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_10                  0x3367CC
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_11                  0x3367D0
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_12                  0x3367D4
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_13                  0x3367D8
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_14                  0x3367DC
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_15                  0x3367E0
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_0                     0x336824
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_1                     0x336828
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_2                     0x33682C
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_3                     0x336830
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_4                     0x336834
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_5                     0x336838
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_6                     0x33683C
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_7                     0x336840
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_8                     0x336844
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_9                     0x336848
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_10                    0x33684C
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_11                    0x336850
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_12                    0x336854
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_13                    0x336858
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_14                    0x33685C
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_15                    0x336860
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_0                    0x336864
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_1                    0x336868
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_2                    0x33686C
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_3                    0x336870
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_4                    0x336874
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_5                    0x336878
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_6                    0x33687C
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_7                    0x336880
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_8                    0x336884
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_9                    0x336888
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_10                   0x33688C
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_11                   0x336890
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_12                   0x336894
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_13                   0x336898
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_14                   0x33689C
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_15                   0x3368A0
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_0                     0x3368A4
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_1                     0x3368A8
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_2                     0x3368AC
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_3                     0x3368B0
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_4                     0x3368B4
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_5                     0x3368B8
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_6                     0x3368BC
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_7                     0x3368C0
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_8                     0x3368C4
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_9                     0x3368C8
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_10                    0x3368CC
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_11                    0x3368D0
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_12                    0x3368D4
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_13                    0x3368D8
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_14                    0x3368DC
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_15                    0x3368E0
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_0                    0x3368E4
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_1                    0x3368E8
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_2                    0x3368EC
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_3                    0x3368F0
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_4                    0x3368F4
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_5                    0x3368F8
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_6                    0x3368FC
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_7                    0x336900
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_8                    0x336904
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_9                    0x336908
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_10                   0x33690C
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_11                   0x336910
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_12                   0x336914
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_13                   0x336918
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_14                   0x33691C
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_15                   0x336920
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_0                    0x336924
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_1                    0x336928
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_2                    0x33692C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_3                    0x336930
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_4                    0x336934
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_5                    0x336938
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_6                    0x33693C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_7                    0x336940
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_8                    0x336944
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_9                    0x336948
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_10                   0x33694C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_11                   0x336950
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_12                   0x336954
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_13                   0x336958
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_14                   0x33695C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_15                   0x336960
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_0                   0x336964
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_1                   0x336968
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_2                   0x33696C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_3                   0x336970
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_4                   0x336974
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_5                   0x336978
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_6                   0x33697C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_7                   0x336980
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_8                   0x336984
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_9                   0x336988
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_10                  0x33698C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_11                  0x336990
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_12                  0x336994
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_13                  0x336998
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_14                  0x33699C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_15                  0x3369A0
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_0                    0x3369A4
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_1                    0x3369A8
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_2                    0x3369AC
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_3                    0x3369B0
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_4                    0x3369B4
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_5                    0x3369B8
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_6                    0x3369BC
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_7                    0x3369C0
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_8                    0x3369C4
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_9                    0x3369C8
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_10                   0x3369CC
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_11                   0x3369D0
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_12                   0x3369D4
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_13                   0x3369D8
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_14                   0x3369DC
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_15                   0x3369E0
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_0                   0x3369E4
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_1                   0x3369E8
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_2                   0x3369EC
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_3                   0x3369F0
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_4                   0x3369F4
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_5                   0x3369F8
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_6                   0x3369FC
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_7                   0x336A00
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_8                   0x336A04
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_9                   0x336A08
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_10                  0x336A0C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_11                  0x336A10
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_12                  0x336A14
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_13                  0x336A18
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_14                  0x336A1C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_15                  0x336A20
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_HIT_AW                            0x336A64
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_HIT_AR                            0x336A68
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_HIT_AW                           0x336A6C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_HIT_AR                           0x336A70
+
+#define mmSIF_RTR_CTRL_3_RGL_CFG                                     0x336B64
+
+#define mmSIF_RTR_CTRL_3_RGL_SHIFT                                   0x336B68
+
+#define mmSIF_RTR_CTRL_3_RGL_EXPECTED_LAT_0                          0x336B6C
+
+#define mmSIF_RTR_CTRL_3_RGL_EXPECTED_LAT_1                          0x336B70
+
+#define mmSIF_RTR_CTRL_3_RGL_EXPECTED_LAT_2                          0x336B74
+
+#define mmSIF_RTR_CTRL_3_RGL_EXPECTED_LAT_3                          0x336B78
+
+#define mmSIF_RTR_CTRL_3_RGL_EXPECTED_LAT_4                          0x336B7C
+
+#define mmSIF_RTR_CTRL_3_RGL_EXPECTED_LAT_5                          0x336B80
+
+#define mmSIF_RTR_CTRL_3_RGL_EXPECTED_LAT_6                          0x336B84
+
+#define mmSIF_RTR_CTRL_3_RGL_EXPECTED_LAT_7                          0x336B88
+
+#define mmSIF_RTR_CTRL_3_RGL_TOKEN_0                                 0x336BAC
+
+#define mmSIF_RTR_CTRL_3_RGL_TOKEN_1                                 0x336BB0
+
+#define mmSIF_RTR_CTRL_3_RGL_TOKEN_2                                 0x336BB4
+
+#define mmSIF_RTR_CTRL_3_RGL_TOKEN_3                                 0x336BB8
+
+#define mmSIF_RTR_CTRL_3_RGL_TOKEN_4                                 0x336BBC
+
+#define mmSIF_RTR_CTRL_3_RGL_TOKEN_5                                 0x336BC0
+
+#define mmSIF_RTR_CTRL_3_RGL_TOKEN_6                                 0x336BC4
+
+#define mmSIF_RTR_CTRL_3_RGL_TOKEN_7                                 0x336BC8
+
+#define mmSIF_RTR_CTRL_3_RGL_BANK_ID_0                               0x336BEC
+
+#define mmSIF_RTR_CTRL_3_RGL_BANK_ID_1                               0x336BF0
+
+#define mmSIF_RTR_CTRL_3_RGL_BANK_ID_2                               0x336BF4
+
+#define mmSIF_RTR_CTRL_3_RGL_BANK_ID_3                               0x336BF8
+
+#define mmSIF_RTR_CTRL_3_RGL_BANK_ID_4                               0x336BFC
+
+#define mmSIF_RTR_CTRL_3_RGL_BANK_ID_5                               0x336C00
+
+#define mmSIF_RTR_CTRL_3_RGL_BANK_ID_6                               0x336C04
+
+#define mmSIF_RTR_CTRL_3_RGL_BANK_ID_7                               0x336C08
+
+#define mmSIF_RTR_CTRL_3_RGL_WDT                                     0x336C2C
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_HBM0_CH0_CTR_WRAP                    0x336C30
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_HBM0_CH1_CTR_WRAP                    0x336C34
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_HBM1_CH0_CTR_WRAP                    0x336C38
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_HBM1_CH1_CTR_WRAP                    0x336C3C
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_HBM2_CH0_CTR_WRAP                    0x336C40
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_HBM2_CH1_CTR_WRAP                    0x336C44
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_HBM3_CH0_CTR_WRAP                    0x336C48
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_HBM3_CH1_CTR_WRAP                    0x336C4C
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_HBM0_CH0_CTR_CNT                     0x336C50
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_HBM0_CH1_CTR_CNT                     0x336C54
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_HBM1_CH0_CTR_CNT                     0x336C58
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_HBM1_CH1_CTR_CNT                     0x336C5C
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_HBM2_CH0_CTR_CNT                     0x336C60
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_HBM2_CH1_CTR_CNT                     0x336C64
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_HBM3_CH0_CTR_CNT                     0x336C68
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_HBM3_CH1_CTR_CNT                     0x336C6C
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_HBM0_CH0_CTR_WRAP                    0x336C70
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_HBM0_CH1_CTR_WRAP                    0x336C74
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_HBM1_CH0_CTR_WRAP                    0x336C78
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_HBM1_CH1_CTR_WRAP                    0x336C7C
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_HBM2_CH0_CTR_WRAP                    0x336C80
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_HBM2_CH1_CTR_WRAP                    0x336C84
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_HBM3_CH0_CTR_WRAP                    0x336C88
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_HBM3_CH1_CTR_WRAP                    0x336C8C
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_HBM0_CH0_CTR_CNT                     0x336C90
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_HBM0_CH1_CTR_CNT                     0x336C94
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_HBM1_CH0_CTR_CNT                     0x336C98
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_HBM1_CH1_CTR_CNT                     0x336C9C
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_HBM2_CH0_CTR_CNT                     0x336CA0
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_HBM2_CH1_CTR_CNT                     0x336CA4
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_HBM3_CH0_CTR_CNT                     0x336CA8
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_HBM3_CH1_CTR_CNT                     0x336CAC
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_PC_SEL_0                             0x336CB0
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_PC_SEL_1                             0x336CB4
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_PC_SEL_2                             0x336CB8
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_PC_SEL_3                             0x336CBC
+
+#endif /* ASIC_REG_SIF_RTR_CTRL_3_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_4_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_4_regs.h
new file mode 100644
index 000000000000..ad48773c4bbd
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_4_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_SIF_RTR_CTRL_4_REGS_H_
+#define ASIC_REG_SIF_RTR_CTRL_4_REGS_H_
+
+/*
+ *****************************************
+ *   SIF_RTR_CTRL_4 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmSIF_RTR_CTRL_4_PERM_SEL                                    0x346108
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_0                               0x346114
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_1                               0x346118
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_2                               0x34611C
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_3                               0x346120
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_4                               0x346124
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_5                               0x346128
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_6                               0x34612C
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_7                               0x346130
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_8                               0x346134
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_9                               0x346138
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_10                              0x34613C
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_11                              0x346140
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_12                              0x346144
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_13                              0x346148
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_14                              0x34614C
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_15                              0x346150
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_16                              0x346154
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_17                              0x346158
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_18                              0x34615C
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_19                              0x346160
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_20                              0x346164
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_21                              0x346168
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_22                              0x34616C
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_23                              0x346170
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_24                              0x346174
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_25                              0x346178
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_26                              0x34617C
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_27                              0x346180
+
+#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_0                              0x346184
+
+#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_1                              0x346188
+
+#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_2                              0x34618C
+
+#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_3                              0x346190
+
+#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_4                              0x346194
+
+#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_5                              0x346198
+
+#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_6                              0x34619C
+
+#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_7                              0x3461A0
+
+#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_8                              0x3461A4
+
+#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_9                              0x3461A8
+
+#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_10                             0x3461AC
+
+#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_11                             0x3461B0
+
+#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_12                             0x3461B4
+
+#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_13                             0x3461B8
+
+#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_14                             0x3461BC
+
+#define mmSIF_RTR_CTRL_4_SCRAM_SRAM_EN                               0x34626C
+
+#define mmSIF_RTR_CTRL_4_RL_HBM_EN                                   0x346274
+
+#define mmSIF_RTR_CTRL_4_RL_HBM_SAT                                  0x346278
+
+#define mmSIF_RTR_CTRL_4_RL_HBM_RST                                  0x34627C
+
+#define mmSIF_RTR_CTRL_4_RL_HBM_TIMEOUT                              0x346280
+
+#define mmSIF_RTR_CTRL_4_SCRAM_HBM_EN                                0x346284
+
+#define mmSIF_RTR_CTRL_4_RL_PCI_EN                                   0x346288
+
+#define mmSIF_RTR_CTRL_4_RL_PCI_SAT                                  0x34628C
+
+#define mmSIF_RTR_CTRL_4_RL_PCI_RST                                  0x346290
+
+#define mmSIF_RTR_CTRL_4_RL_PCI_TIMEOUT                              0x346294
+
+#define mmSIF_RTR_CTRL_4_RL_SRAM_EN                                  0x34629C
+
+#define mmSIF_RTR_CTRL_4_RL_SRAM_SAT                                 0x3462A0
+
+#define mmSIF_RTR_CTRL_4_RL_SRAM_RST                                 0x3462A4
+
+#define mmSIF_RTR_CTRL_4_RL_SRAM_TIMEOUT                             0x3462AC
+
+#define mmSIF_RTR_CTRL_4_RL_SRAM_RED                                 0x3462B4
+
+#define mmSIF_RTR_CTRL_4_E2E_HBM_EN                                  0x3462EC
+
+#define mmSIF_RTR_CTRL_4_E2E_PCI_EN                                  0x3462F0
+
+#define mmSIF_RTR_CTRL_4_E2E_HBM_WR_SIZE                             0x3462F4
+
+#define mmSIF_RTR_CTRL_4_E2E_PCI_WR_SIZE                             0x3462F8
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_PCI_CTR_SET_EN                       0x346404
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_PCI_CTR_SET                          0x346408
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_PCI_CTR_WRAP                         0x34640C
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_PCI_CTR_CNT                          0x346410
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_HBM_CTR_SET_EN                       0x346414
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_HBM_CTR_SET                          0x346418
+
+#define mmSIF_RTR_CTRL_4_E2E_HBM_RD_SIZE                             0x34641C
+
+#define mmSIF_RTR_CTRL_4_E2E_PCI_RD_SIZE                             0x346420
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_PCI_CTR_SET_EN                       0x346424
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_PCI_CTR_SET                          0x346428
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_PCI_CTR_WRAP                         0x34642C
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_PCI_CTR_CNT                          0x346430
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_HBM_CTR_SET_EN                       0x346434
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_HBM_CTR_SET                          0x346438
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_SEL_0                                0x346450
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_SEL_1                                0x346454
+
+#define mmSIF_RTR_CTRL_4_NON_LIN_EN                                  0x346480
+
+#define mmSIF_RTR_CTRL_4_NL_SRAM_BANK_0                              0x346500
+
+#define mmSIF_RTR_CTRL_4_NL_SRAM_BANK_1                              0x346504
+
+#define mmSIF_RTR_CTRL_4_NL_SRAM_BANK_2                              0x346508
+
+#define mmSIF_RTR_CTRL_4_NL_SRAM_BANK_3                              0x34650C
+
+#define mmSIF_RTR_CTRL_4_NL_SRAM_BANK_4                              0x346510
+
+#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_0                            0x346514
+
+#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_1                            0x346520
+
+#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_2                            0x346524
+
+#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_3                            0x346528
+
+#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_4                            0x34652C
+
+#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_5                            0x346530
+
+#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_6                            0x346534
+
+#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_7                            0x346538
+
+#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_8                            0x34653C
+
+#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_9                            0x346540
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_0                             0x346550
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_1                             0x346554
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_2                             0x346558
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_3                             0x34655C
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_4                             0x346560
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_5                             0x346564
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_6                             0x346568
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_7                             0x34656C
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_8                             0x346570
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_9                             0x346574
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_10                            0x346578
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_11                            0x34657C
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_12                            0x346580
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_13                            0x346584
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_14                            0x346588
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_15                            0x34658C
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_16                            0x346590
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_17                            0x346594
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_18                            0x346598
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_0                     0x3465E4
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_1                     0x3465E8
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_2                     0x3465EC
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_3                     0x3465F0
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_4                     0x3465F4
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_5                     0x3465F8
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_6                     0x3465FC
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_7                     0x346600
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_8                     0x346604
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_9                     0x346608
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_10                    0x34660C
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_11                    0x346610
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_12                    0x346614
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_13                    0x346618
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_14                    0x34661C
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_15                    0x346620
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_0                    0x346624
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_1                    0x346628
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_2                    0x34662C
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_3                    0x346630
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_4                    0x346634
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_5                    0x346638
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_6                    0x34663C
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_7                    0x346640
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_8                    0x346644
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_9                    0x346648
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_10                   0x34664C
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_11                   0x346650
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_12                   0x346654
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_13                   0x346658
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_14                   0x34665C
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_15                   0x346660
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_0                     0x346664
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_1                     0x346668
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_2                     0x34666C
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_3                     0x346670
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_4                     0x346674
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_5                     0x346678
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_6                     0x34667C
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_7                     0x346680
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_8                     0x346684
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_9                     0x346688
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_10                    0x34668C
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_11                    0x346690
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_12                    0x346694
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_13                    0x346698
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_14                    0x34669C
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_15                    0x3466A0
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_0                    0x3466A4
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_1                    0x3466A8
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_2                    0x3466AC
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_3                    0x3466B0
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_4                    0x3466B4
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_5                    0x3466B8
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_6                    0x3466BC
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_7                    0x3466C0
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_8                    0x3466C4
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_9                    0x3466C8
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_10                   0x3466CC
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_11                   0x3466D0
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_12                   0x3466D4
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_13                   0x3466D8
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_14                   0x3466DC
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_15                   0x3466E0
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_0                    0x3466E4
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_1                    0x3466E8
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_2                    0x3466EC
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_3                    0x3466F0
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_4                    0x3466F4
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_5                    0x3466F8
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_6                    0x3466FC
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_7                    0x346700
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_8                    0x346704
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_9                    0x346708
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_10                   0x34670C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_11                   0x346710
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_12                   0x346714
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_13                   0x346718
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_14                   0x34671C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_15                   0x346720
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_0                   0x346724
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_1                   0x346728
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_2                   0x34672C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_3                   0x346730
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_4                   0x346734
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_5                   0x346738
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_6                   0x34673C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_7                   0x346740
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_8                   0x346744
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_9                   0x346748
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_10                  0x34674C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_11                  0x346750
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_12                  0x346754
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_13                  0x346758
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_14                  0x34675C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_15                  0x346760
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_0                    0x346764
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_1                    0x346768
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_2                    0x34676C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_3                    0x346770
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_4                    0x346774
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_5                    0x346778
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_6                    0x34677C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_7                    0x346780
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_8                    0x346784
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_9                    0x346788
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_10                   0x34678C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_11                   0x346790
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_12                   0x346794
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_13                   0x346798
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_14                   0x34679C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_15                   0x3467A0
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_0                   0x3467A4
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_1                   0x3467A8
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_2                   0x3467AC
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_3                   0x3467B0
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_4                   0x3467B4
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_5                   0x3467B8
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_6                   0x3467BC
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_7                   0x3467C0
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_8                   0x3467C4
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_9                   0x3467C8
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_10                  0x3467CC
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_11                  0x3467D0
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_12                  0x3467D4
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_13                  0x3467D8
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_14                  0x3467DC
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_15                  0x3467E0
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_0                     0x346824
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_1                     0x346828
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_2                     0x34682C
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_3                     0x346830
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_4                     0x346834
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_5                     0x346838
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_6                     0x34683C
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_7                     0x346840
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_8                     0x346844
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_9                     0x346848
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_10                    0x34684C
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_11                    0x346850
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_12                    0x346854
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_13                    0x346858
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_14                    0x34685C
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_15                    0x346860
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_0                    0x346864
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_1                    0x346868
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_2                    0x34686C
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_3                    0x346870
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_4                    0x346874
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_5                    0x346878
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_6                    0x34687C
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_7                    0x346880
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_8                    0x346884
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_9                    0x346888
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_10                   0x34688C
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_11                   0x346890
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_12                   0x346894
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_13                   0x346898
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_14                   0x34689C
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_15                   0x3468A0
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_0                     0x3468A4
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_1                     0x3468A8
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_2                     0x3468AC
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_3                     0x3468B0
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_4                     0x3468B4
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_5                     0x3468B8
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_6                     0x3468BC
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_7                     0x3468C0
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_8                     0x3468C4
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_9                     0x3468C8
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_10                    0x3468CC
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_11                    0x3468D0
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_12                    0x3468D4
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_13                    0x3468D8
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_14                    0x3468DC
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_15                    0x3468E0
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_0                    0x3468E4
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_1                    0x3468E8
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_2                    0x3468EC
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_3                    0x3468F0
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_4                    0x3468F4
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_5                    0x3468F8
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_6                    0x3468FC
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_7                    0x346900
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_8                    0x346904
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_9                    0x346908
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_10                   0x34690C
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_11                   0x346910
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_12                   0x346914
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_13                   0x346918
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_14                   0x34691C
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_15                   0x346920
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_0                    0x346924
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_1                    0x346928
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_2                    0x34692C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_3                    0x346930
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_4                    0x346934
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_5                    0x346938
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_6                    0x34693C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_7                    0x346940
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_8                    0x346944
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_9                    0x346948
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_10                   0x34694C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_11                   0x346950
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_12                   0x346954
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_13                   0x346958
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_14                   0x34695C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_15                   0x346960
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_0                   0x346964
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_1                   0x346968
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_2                   0x34696C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_3                   0x346970
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_4                   0x346974
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_5                   0x346978
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_6                   0x34697C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_7                   0x346980
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_8                   0x346984
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_9                   0x346988
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_10                  0x34698C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_11                  0x346990
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_12                  0x346994
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_13                  0x346998
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_14                  0x34699C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_15                  0x3469A0
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_0                    0x3469A4
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_1                    0x3469A8
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_2                    0x3469AC
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_3                    0x3469B0
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_4                    0x3469B4
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_5                    0x3469B8
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_6                    0x3469BC
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_7                    0x3469C0
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_8                    0x3469C4
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_9                    0x3469C8
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_10                   0x3469CC
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_11                   0x3469D0
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_12                   0x3469D4
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_13                   0x3469D8
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_14                   0x3469DC
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_15                   0x3469E0
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_0                   0x3469E4
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_1                   0x3469E8
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_2                   0x3469EC
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_3                   0x3469F0
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_4                   0x3469F4
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_5                   0x3469F8
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_6                   0x3469FC
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_7                   0x346A00
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_8                   0x346A04
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_9                   0x346A08
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_10                  0x346A0C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_11                  0x346A10
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_12                  0x346A14
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_13                  0x346A18
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_14                  0x346A1C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_15                  0x346A20
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_HIT_AW                            0x346A64
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_HIT_AR                            0x346A68
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_HIT_AW                           0x346A6C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_HIT_AR                           0x346A70
+
+#define mmSIF_RTR_CTRL_4_RGL_CFG                                     0x346B64
+
+#define mmSIF_RTR_CTRL_4_RGL_SHIFT                                   0x346B68
+
+#define mmSIF_RTR_CTRL_4_RGL_EXPECTED_LAT_0                          0x346B6C
+
+#define mmSIF_RTR_CTRL_4_RGL_EXPECTED_LAT_1                          0x346B70
+
+#define mmSIF_RTR_CTRL_4_RGL_EXPECTED_LAT_2                          0x346B74
+
+#define mmSIF_RTR_CTRL_4_RGL_EXPECTED_LAT_3                          0x346B78
+
+#define mmSIF_RTR_CTRL_4_RGL_EXPECTED_LAT_4                          0x346B7C
+
+#define mmSIF_RTR_CTRL_4_RGL_EXPECTED_LAT_5                          0x346B80
+
+#define mmSIF_RTR_CTRL_4_RGL_EXPECTED_LAT_6                          0x346B84
+
+#define mmSIF_RTR_CTRL_4_RGL_EXPECTED_LAT_7                          0x346B88
+
+#define mmSIF_RTR_CTRL_4_RGL_TOKEN_0                                 0x346BAC
+
+#define mmSIF_RTR_CTRL_4_RGL_TOKEN_1                                 0x346BB0
+
+#define mmSIF_RTR_CTRL_4_RGL_TOKEN_2                                 0x346BB4
+
+#define mmSIF_RTR_CTRL_4_RGL_TOKEN_3                                 0x346BB8
+
+#define mmSIF_RTR_CTRL_4_RGL_TOKEN_4                                 0x346BBC
+
+#define mmSIF_RTR_CTRL_4_RGL_TOKEN_5                                 0x346BC0
+
+#define mmSIF_RTR_CTRL_4_RGL_TOKEN_6                                 0x346BC4
+
+#define mmSIF_RTR_CTRL_4_RGL_TOKEN_7                                 0x346BC8
+
+#define mmSIF_RTR_CTRL_4_RGL_BANK_ID_0                               0x346BEC
+
+#define mmSIF_RTR_CTRL_4_RGL_BANK_ID_1                               0x346BF0
+
+#define mmSIF_RTR_CTRL_4_RGL_BANK_ID_2                               0x346BF4
+
+#define mmSIF_RTR_CTRL_4_RGL_BANK_ID_3                               0x346BF8
+
+#define mmSIF_RTR_CTRL_4_RGL_BANK_ID_4                               0x346BFC
+
+#define mmSIF_RTR_CTRL_4_RGL_BANK_ID_5                               0x346C00
+
+#define mmSIF_RTR_CTRL_4_RGL_BANK_ID_6                               0x346C04
+
+#define mmSIF_RTR_CTRL_4_RGL_BANK_ID_7                               0x346C08
+
+#define mmSIF_RTR_CTRL_4_RGL_WDT                                     0x346C2C
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_HBM0_CH0_CTR_WRAP                    0x346C30
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_HBM0_CH1_CTR_WRAP                    0x346C34
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_HBM1_CH0_CTR_WRAP                    0x346C38
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_HBM1_CH1_CTR_WRAP                    0x346C3C
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_HBM2_CH0_CTR_WRAP                    0x346C40
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_HBM2_CH1_CTR_WRAP                    0x346C44
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_HBM3_CH0_CTR_WRAP                    0x346C48
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_HBM3_CH1_CTR_WRAP                    0x346C4C
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_HBM0_CH0_CTR_CNT                     0x346C50
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_HBM0_CH1_CTR_CNT                     0x346C54
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_HBM1_CH0_CTR_CNT                     0x346C58
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_HBM1_CH1_CTR_CNT                     0x346C5C
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_HBM2_CH0_CTR_CNT                     0x346C60
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_HBM2_CH1_CTR_CNT                     0x346C64
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_HBM3_CH0_CTR_CNT                     0x346C68
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_HBM3_CH1_CTR_CNT                     0x346C6C
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_HBM0_CH0_CTR_WRAP                    0x346C70
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_HBM0_CH1_CTR_WRAP                    0x346C74
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_HBM1_CH0_CTR_WRAP                    0x346C78
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_HBM1_CH1_CTR_WRAP                    0x346C7C
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_HBM2_CH0_CTR_WRAP                    0x346C80
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_HBM2_CH1_CTR_WRAP                    0x346C84
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_HBM3_CH0_CTR_WRAP                    0x346C88
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_HBM3_CH1_CTR_WRAP                    0x346C8C
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_HBM0_CH0_CTR_CNT                     0x346C90
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_HBM0_CH1_CTR_CNT                     0x346C94
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_HBM1_CH0_CTR_CNT                     0x346C98
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_HBM1_CH1_CTR_CNT                     0x346C9C
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_HBM2_CH0_CTR_CNT                     0x346CA0
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_HBM2_CH1_CTR_CNT                     0x346CA4
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_HBM3_CH0_CTR_CNT                     0x346CA8
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_HBM3_CH1_CTR_CNT                     0x346CAC
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_PC_SEL_0                             0x346CB0
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_PC_SEL_1                             0x346CB4
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_PC_SEL_2                             0x346CB8
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_PC_SEL_3                             0x346CBC
+
+#endif /* ASIC_REG_SIF_RTR_CTRL_4_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_5_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_5_regs.h
new file mode 100644
index 000000000000..6c27850ca3f5
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_5_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_SIF_RTR_CTRL_5_REGS_H_
+#define ASIC_REG_SIF_RTR_CTRL_5_REGS_H_
+
+/*
+ *****************************************
+ *   SIF_RTR_CTRL_5 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmSIF_RTR_CTRL_5_PERM_SEL                                    0x356108
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_0                               0x356114
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_1                               0x356118
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_2                               0x35611C
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_3                               0x356120
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_4                               0x356124
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_5                               0x356128
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_6                               0x35612C
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_7                               0x356130
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_8                               0x356134
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_9                               0x356138
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_10                              0x35613C
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_11                              0x356140
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_12                              0x356144
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_13                              0x356148
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_14                              0x35614C
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_15                              0x356150
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_16                              0x356154
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_17                              0x356158
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_18                              0x35615C
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_19                              0x356160
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_20                              0x356164
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_21                              0x356168
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_22                              0x35616C
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_23                              0x356170
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_24                              0x356174
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_25                              0x356178
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_26                              0x35617C
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_27                              0x356180
+
+#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_0                              0x356184
+
+#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_1                              0x356188
+
+#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_2                              0x35618C
+
+#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_3                              0x356190
+
+#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_4                              0x356194
+
+#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_5                              0x356198
+
+#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_6                              0x35619C
+
+#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_7                              0x3561A0
+
+#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_8                              0x3561A4
+
+#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_9                              0x3561A8
+
+#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_10                             0x3561AC
+
+#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_11                             0x3561B0
+
+#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_12                             0x3561B4
+
+#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_13                             0x3561B8
+
+#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_14                             0x3561BC
+
+#define mmSIF_RTR_CTRL_5_SCRAM_SRAM_EN                               0x35626C
+
+#define mmSIF_RTR_CTRL_5_RL_HBM_EN                                   0x356274
+
+#define mmSIF_RTR_CTRL_5_RL_HBM_SAT                                  0x356278
+
+#define mmSIF_RTR_CTRL_5_RL_HBM_RST                                  0x35627C
+
+#define mmSIF_RTR_CTRL_5_RL_HBM_TIMEOUT                              0x356280
+
+#define mmSIF_RTR_CTRL_5_SCRAM_HBM_EN                                0x356284
+
+#define mmSIF_RTR_CTRL_5_RL_PCI_EN                                   0x356288
+
+#define mmSIF_RTR_CTRL_5_RL_PCI_SAT                                  0x35628C
+
+#define mmSIF_RTR_CTRL_5_RL_PCI_RST                                  0x356290
+
+#define mmSIF_RTR_CTRL_5_RL_PCI_TIMEOUT                              0x356294
+
+#define mmSIF_RTR_CTRL_5_RL_SRAM_EN                                  0x35629C
+
+#define mmSIF_RTR_CTRL_5_RL_SRAM_SAT                                 0x3562A0
+
+#define mmSIF_RTR_CTRL_5_RL_SRAM_RST                                 0x3562A4
+
+#define mmSIF_RTR_CTRL_5_RL_SRAM_TIMEOUT                             0x3562AC
+
+#define mmSIF_RTR_CTRL_5_RL_SRAM_RED                                 0x3562B4
+
+#define mmSIF_RTR_CTRL_5_E2E_HBM_EN                                  0x3562EC
+
+#define mmSIF_RTR_CTRL_5_E2E_PCI_EN                                  0x3562F0
+
+#define mmSIF_RTR_CTRL_5_E2E_HBM_WR_SIZE                             0x3562F4
+
+#define mmSIF_RTR_CTRL_5_E2E_PCI_WR_SIZE                             0x3562F8
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_PCI_CTR_SET_EN                       0x356404
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_PCI_CTR_SET                          0x356408
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_PCI_CTR_WRAP                         0x35640C
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_PCI_CTR_CNT                          0x356410
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_HBM_CTR_SET_EN                       0x356414
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_HBM_CTR_SET                          0x356418
+
+#define mmSIF_RTR_CTRL_5_E2E_HBM_RD_SIZE                             0x35641C
+
+#define mmSIF_RTR_CTRL_5_E2E_PCI_RD_SIZE                             0x356420
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_PCI_CTR_SET_EN                       0x356424
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_PCI_CTR_SET                          0x356428
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_PCI_CTR_WRAP                         0x35642C
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_PCI_CTR_CNT                          0x356430
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_HBM_CTR_SET_EN                       0x356434
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_HBM_CTR_SET                          0x356438
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_SEL_0                                0x356450
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_SEL_1                                0x356454
+
+#define mmSIF_RTR_CTRL_5_NON_LIN_EN                                  0x356480
+
+#define mmSIF_RTR_CTRL_5_NL_SRAM_BANK_0                              0x356500
+
+#define mmSIF_RTR_CTRL_5_NL_SRAM_BANK_1                              0x356504
+
+#define mmSIF_RTR_CTRL_5_NL_SRAM_BANK_2                              0x356508
+
+#define mmSIF_RTR_CTRL_5_NL_SRAM_BANK_3                              0x35650C
+
+#define mmSIF_RTR_CTRL_5_NL_SRAM_BANK_4                              0x356510
+
+#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_0                            0x356514
+
+#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_1                            0x356520
+
+#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_2                            0x356524
+
+#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_3                            0x356528
+
+#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_4                            0x35652C
+
+#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_5                            0x356530
+
+#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_6                            0x356534
+
+#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_7                            0x356538
+
+#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_8                            0x35653C
+
+#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_9                            0x356540
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_0                             0x356550
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_1                             0x356554
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_2                             0x356558
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_3                             0x35655C
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_4                             0x356560
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_5                             0x356564
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_6                             0x356568
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_7                             0x35656C
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_8                             0x356570
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_9                             0x356574
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_10                            0x356578
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_11                            0x35657C
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_12                            0x356580
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_13                            0x356584
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_14                            0x356588
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_15                            0x35658C
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_16                            0x356590
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_17                            0x356594
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_18                            0x356598
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_0                     0x3565E4
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_1                     0x3565E8
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_2                     0x3565EC
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_3                     0x3565F0
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_4                     0x3565F4
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_5                     0x3565F8
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_6                     0x3565FC
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_7                     0x356600
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_8                     0x356604
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_9                     0x356608
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_10                    0x35660C
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_11                    0x356610
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_12                    0x356614
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_13                    0x356618
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_14                    0x35661C
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_15                    0x356620
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_0                    0x356624
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_1                    0x356628
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_2                    0x35662C
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_3                    0x356630
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_4                    0x356634
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_5                    0x356638
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_6                    0x35663C
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_7                    0x356640
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_8                    0x356644
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_9                    0x356648
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_10                   0x35664C
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_11                   0x356650
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_12                   0x356654
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_13                   0x356658
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_14                   0x35665C
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_15                   0x356660
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_0                     0x356664
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_1                     0x356668
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_2                     0x35666C
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_3                     0x356670
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_4                     0x356674
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_5                     0x356678
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_6                     0x35667C
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_7                     0x356680
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_8                     0x356684
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_9                     0x356688
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_10                    0x35668C
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_11                    0x356690
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_12                    0x356694
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_13                    0x356698
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_14                    0x35669C
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_15                    0x3566A0
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_0                    0x3566A4
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_1                    0x3566A8
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_2                    0x3566AC
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_3                    0x3566B0
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_4                    0x3566B4
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_5                    0x3566B8
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_6                    0x3566BC
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_7                    0x3566C0
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_8                    0x3566C4
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_9                    0x3566C8
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_10                   0x3566CC
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_11                   0x3566D0
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_12                   0x3566D4
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_13                   0x3566D8
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_14                   0x3566DC
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_15                   0x3566E0
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_0                    0x3566E4
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_1                    0x3566E8
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_2                    0x3566EC
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_3                    0x3566F0
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_4                    0x3566F4
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_5                    0x3566F8
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_6                    0x3566FC
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_7                    0x356700
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_8                    0x356704
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_9                    0x356708
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_10                   0x35670C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_11                   0x356710
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_12                   0x356714
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_13                   0x356718
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_14                   0x35671C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_15                   0x356720
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_0                   0x356724
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_1                   0x356728
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_2                   0x35672C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_3                   0x356730
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_4                   0x356734
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_5                   0x356738
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_6                   0x35673C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_7                   0x356740
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_8                   0x356744
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_9                   0x356748
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_10                  0x35674C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_11                  0x356750
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_12                  0x356754
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_13                  0x356758
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_14                  0x35675C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_15                  0x356760
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_0                    0x356764
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_1                    0x356768
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_2                    0x35676C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_3                    0x356770
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_4                    0x356774
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_5                    0x356778
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_6                    0x35677C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_7                    0x356780
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_8                    0x356784
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_9                    0x356788
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_10                   0x35678C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_11                   0x356790
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_12                   0x356794
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_13                   0x356798
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_14                   0x35679C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_15                   0x3567A0
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_0                   0x3567A4
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_1                   0x3567A8
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_2                   0x3567AC
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_3                   0x3567B0
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_4                   0x3567B4
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_5                   0x3567B8
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_6                   0x3567BC
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_7                   0x3567C0
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_8                   0x3567C4
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_9                   0x3567C8
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_10                  0x3567CC
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_11                  0x3567D0
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_12                  0x3567D4
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_13                  0x3567D8
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_14                  0x3567DC
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_15                  0x3567E0
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_0                     0x356824
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_1                     0x356828
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_2                     0x35682C
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_3                     0x356830
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_4                     0x356834
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_5                     0x356838
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_6                     0x35683C
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_7                     0x356840
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_8                     0x356844
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_9                     0x356848
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_10                    0x35684C
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_11                    0x356850
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_12                    0x356854
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_13                    0x356858
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_14                    0x35685C
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_15                    0x356860
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_0                    0x356864
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_1                    0x356868
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_2                    0x35686C
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_3                    0x356870
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_4                    0x356874
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_5                    0x356878
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_6                    0x35687C
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_7                    0x356880
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_8                    0x356884
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_9                    0x356888
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_10                   0x35688C
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_11                   0x356890
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_12                   0x356894
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_13                   0x356898
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_14                   0x35689C
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_15                   0x3568A0
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_0                     0x3568A4
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_1                     0x3568A8
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_2                     0x3568AC
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_3                     0x3568B0
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_4                     0x3568B4
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_5                     0x3568B8
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_6                     0x3568BC
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_7                     0x3568C0
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_8                     0x3568C4
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_9                     0x3568C8
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_10                    0x3568CC
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_11                    0x3568D0
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_12                    0x3568D4
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_13                    0x3568D8
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_14                    0x3568DC
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_15                    0x3568E0
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_0                    0x3568E4
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_1                    0x3568E8
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_2                    0x3568EC
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_3                    0x3568F0
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_4                    0x3568F4
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_5                    0x3568F8
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_6                    0x3568FC
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_7                    0x356900
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_8                    0x356904
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_9                    0x356908
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_10                   0x35690C
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_11                   0x356910
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_12                   0x356914
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_13                   0x356918
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_14                   0x35691C
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_15                   0x356920
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_0                    0x356924
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_1                    0x356928
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_2                    0x35692C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_3                    0x356930
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_4                    0x356934
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_5                    0x356938
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_6                    0x35693C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_7                    0x356940
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_8                    0x356944
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_9                    0x356948
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_10                   0x35694C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_11                   0x356950
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_12                   0x356954
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_13                   0x356958
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_14                   0x35695C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_15                   0x356960
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_0                   0x356964
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_1                   0x356968
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_2                   0x35696C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_3                   0x356970
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_4                   0x356974
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_5                   0x356978
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_6                   0x35697C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_7                   0x356980
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_8                   0x356984
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_9                   0x356988
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_10                  0x35698C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_11                  0x356990
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_12                  0x356994
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_13                  0x356998
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_14                  0x35699C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_15                  0x3569A0
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_0                    0x3569A4
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_1                    0x3569A8
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_2                    0x3569AC
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_3                    0x3569B0
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_4                    0x3569B4
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_5                    0x3569B8
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_6                    0x3569BC
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_7                    0x3569C0
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_8                    0x3569C4
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_9                    0x3569C8
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_10                   0x3569CC
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_11                   0x3569D0
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_12                   0x3569D4
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_13                   0x3569D8
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_14                   0x3569DC
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_15                   0x3569E0
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_0                   0x3569E4
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_1                   0x3569E8
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_2                   0x3569EC
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_3                   0x3569F0
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_4                   0x3569F4
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_5                   0x3569F8
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_6                   0x3569FC
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_7                   0x356A00
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_8                   0x356A04
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_9                   0x356A08
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_10                  0x356A0C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_11                  0x356A10
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_12                  0x356A14
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_13                  0x356A18
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_14                  0x356A1C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_15                  0x356A20
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_HIT_AW                            0x356A64
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_HIT_AR                            0x356A68
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_HIT_AW                           0x356A6C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_HIT_AR                           0x356A70
+
+#define mmSIF_RTR_CTRL_5_RGL_CFG                                     0x356B64
+
+#define mmSIF_RTR_CTRL_5_RGL_SHIFT                                   0x356B68
+
+#define mmSIF_RTR_CTRL_5_RGL_EXPECTED_LAT_0                          0x356B6C
+
+#define mmSIF_RTR_CTRL_5_RGL_EXPECTED_LAT_1                          0x356B70
+
+#define mmSIF_RTR_CTRL_5_RGL_EXPECTED_LAT_2                          0x356B74
+
+#define mmSIF_RTR_CTRL_5_RGL_EXPECTED_LAT_3                          0x356B78
+
+#define mmSIF_RTR_CTRL_5_RGL_EXPECTED_LAT_4                          0x356B7C
+
+#define mmSIF_RTR_CTRL_5_RGL_EXPECTED_LAT_5                          0x356B80
+
+#define mmSIF_RTR_CTRL_5_RGL_EXPECTED_LAT_6                          0x356B84
+
+#define mmSIF_RTR_CTRL_5_RGL_EXPECTED_LAT_7                          0x356B88
+
+#define mmSIF_RTR_CTRL_5_RGL_TOKEN_0                                 0x356BAC
+
+#define mmSIF_RTR_CTRL_5_RGL_TOKEN_1                                 0x356BB0
+
+#define mmSIF_RTR_CTRL_5_RGL_TOKEN_2                                 0x356BB4
+
+#define mmSIF_RTR_CTRL_5_RGL_TOKEN_3                                 0x356BB8
+
+#define mmSIF_RTR_CTRL_5_RGL_TOKEN_4                                 0x356BBC
+
+#define mmSIF_RTR_CTRL_5_RGL_TOKEN_5                                 0x356BC0
+
+#define mmSIF_RTR_CTRL_5_RGL_TOKEN_6                                 0x356BC4
+
+#define mmSIF_RTR_CTRL_5_RGL_TOKEN_7                                 0x356BC8
+
+#define mmSIF_RTR_CTRL_5_RGL_BANK_ID_0                               0x356BEC
+
+#define mmSIF_RTR_CTRL_5_RGL_BANK_ID_1                               0x356BF0
+
+#define mmSIF_RTR_CTRL_5_RGL_BANK_ID_2                               0x356BF4
+
+#define mmSIF_RTR_CTRL_5_RGL_BANK_ID_3                               0x356BF8
+
+#define mmSIF_RTR_CTRL_5_RGL_BANK_ID_4                               0x356BFC
+
+#define mmSIF_RTR_CTRL_5_RGL_BANK_ID_5                               0x356C00
+
+#define mmSIF_RTR_CTRL_5_RGL_BANK_ID_6                               0x356C04
+
+#define mmSIF_RTR_CTRL_5_RGL_BANK_ID_7                               0x356C08
+
+#define mmSIF_RTR_CTRL_5_RGL_WDT                                     0x356C2C
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_HBM0_CH0_CTR_WRAP                    0x356C30
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_HBM0_CH1_CTR_WRAP                    0x356C34
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_HBM1_CH0_CTR_WRAP                    0x356C38
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_HBM1_CH1_CTR_WRAP                    0x356C3C
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_HBM2_CH0_CTR_WRAP                    0x356C40
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_HBM2_CH1_CTR_WRAP                    0x356C44
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_HBM3_CH0_CTR_WRAP                    0x356C48
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_HBM3_CH1_CTR_WRAP                    0x356C4C
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_HBM0_CH0_CTR_CNT                     0x356C50
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_HBM0_CH1_CTR_CNT                     0x356C54
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_HBM1_CH0_CTR_CNT                     0x356C58
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_HBM1_CH1_CTR_CNT                     0x356C5C
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_HBM2_CH0_CTR_CNT                     0x356C60
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_HBM2_CH1_CTR_CNT                     0x356C64
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_HBM3_CH0_CTR_CNT                     0x356C68
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_HBM3_CH1_CTR_CNT                     0x356C6C
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_HBM0_CH0_CTR_WRAP                    0x356C70
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_HBM0_CH1_CTR_WRAP                    0x356C74
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_HBM1_CH0_CTR_WRAP                    0x356C78
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_HBM1_CH1_CTR_WRAP                    0x356C7C
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_HBM2_CH0_CTR_WRAP                    0x356C80
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_HBM2_CH1_CTR_WRAP                    0x356C84
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_HBM3_CH0_CTR_WRAP                    0x356C88
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_HBM3_CH1_CTR_WRAP                    0x356C8C
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_HBM0_CH0_CTR_CNT                     0x356C90
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_HBM0_CH1_CTR_CNT                     0x356C94
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_HBM1_CH0_CTR_CNT                     0x356C98
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_HBM1_CH1_CTR_CNT                     0x356C9C
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_HBM2_CH0_CTR_CNT                     0x356CA0
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_HBM2_CH1_CTR_CNT                     0x356CA4
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_HBM3_CH0_CTR_CNT                     0x356CA8
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_HBM3_CH1_CTR_CNT                     0x356CAC
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_PC_SEL_0                             0x356CB0
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_PC_SEL_1                             0x356CB4
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_PC_SEL_2                             0x356CB8
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_PC_SEL_3                             0x356CBC
+
+#endif /* ASIC_REG_SIF_RTR_CTRL_5_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_6_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_6_regs.h
new file mode 100644
index 000000000000..a9ea89aa6405
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_6_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_SIF_RTR_CTRL_6_REGS_H_
+#define ASIC_REG_SIF_RTR_CTRL_6_REGS_H_
+
+/*
+ *****************************************
+ *   SIF_RTR_CTRL_6 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmSIF_RTR_CTRL_6_PERM_SEL                                    0x366108
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_0                               0x366114
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_1                               0x366118
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_2                               0x36611C
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_3                               0x366120
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_4                               0x366124
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_5                               0x366128
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_6                               0x36612C
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_7                               0x366130
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_8                               0x366134
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_9                               0x366138
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_10                              0x36613C
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_11                              0x366140
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_12                              0x366144
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_13                              0x366148
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_14                              0x36614C
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_15                              0x366150
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_16                              0x366154
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_17                              0x366158
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_18                              0x36615C
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_19                              0x366160
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_20                              0x366164
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_21                              0x366168
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_22                              0x36616C
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_23                              0x366170
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_24                              0x366174
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_25                              0x366178
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_26                              0x36617C
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_27                              0x366180
+
+#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_0                              0x366184
+
+#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_1                              0x366188
+
+#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_2                              0x36618C
+
+#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_3                              0x366190
+
+#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_4                              0x366194
+
+#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_5                              0x366198
+
+#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_6                              0x36619C
+
+#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_7                              0x3661A0
+
+#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_8                              0x3661A4
+
+#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_9                              0x3661A8
+
+#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_10                             0x3661AC
+
+#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_11                             0x3661B0
+
+#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_12                             0x3661B4
+
+#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_13                             0x3661B8
+
+#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_14                             0x3661BC
+
+#define mmSIF_RTR_CTRL_6_SCRAM_SRAM_EN                               0x36626C
+
+#define mmSIF_RTR_CTRL_6_RL_HBM_EN                                   0x366274
+
+#define mmSIF_RTR_CTRL_6_RL_HBM_SAT                                  0x366278
+
+#define mmSIF_RTR_CTRL_6_RL_HBM_RST                                  0x36627C
+
+#define mmSIF_RTR_CTRL_6_RL_HBM_TIMEOUT                              0x366280
+
+#define mmSIF_RTR_CTRL_6_SCRAM_HBM_EN                                0x366284
+
+#define mmSIF_RTR_CTRL_6_RL_PCI_EN                                   0x366288
+
+#define mmSIF_RTR_CTRL_6_RL_PCI_SAT                                  0x36628C
+
+#define mmSIF_RTR_CTRL_6_RL_PCI_RST                                  0x366290
+
+#define mmSIF_RTR_CTRL_6_RL_PCI_TIMEOUT                              0x366294
+
+#define mmSIF_RTR_CTRL_6_RL_SRAM_EN                                  0x36629C
+
+#define mmSIF_RTR_CTRL_6_RL_SRAM_SAT                                 0x3662A0
+
+#define mmSIF_RTR_CTRL_6_RL_SRAM_RST                                 0x3662A4
+
+#define mmSIF_RTR_CTRL_6_RL_SRAM_TIMEOUT                             0x3662AC
+
+#define mmSIF_RTR_CTRL_6_RL_SRAM_RED                                 0x3662B4
+
+#define mmSIF_RTR_CTRL_6_E2E_HBM_EN                                  0x3662EC
+
+#define mmSIF_RTR_CTRL_6_E2E_PCI_EN                                  0x3662F0
+
+#define mmSIF_RTR_CTRL_6_E2E_HBM_WR_SIZE                             0x3662F4
+
+#define mmSIF_RTR_CTRL_6_E2E_PCI_WR_SIZE                             0x3662F8
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_PCI_CTR_SET_EN                       0x366404
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_PCI_CTR_SET                          0x366408
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_PCI_CTR_WRAP                         0x36640C
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_PCI_CTR_CNT                          0x366410
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_HBM_CTR_SET_EN                       0x366414
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_HBM_CTR_SET                          0x366418
+
+#define mmSIF_RTR_CTRL_6_E2E_HBM_RD_SIZE                             0x36641C
+
+#define mmSIF_RTR_CTRL_6_E2E_PCI_RD_SIZE                             0x366420
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_PCI_CTR_SET_EN                       0x366424
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_PCI_CTR_SET                          0x366428
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_PCI_CTR_WRAP                         0x36642C
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_PCI_CTR_CNT                          0x366430
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_HBM_CTR_SET_EN                       0x366434
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_HBM_CTR_SET                          0x366438
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_SEL_0                                0x366450
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_SEL_1                                0x366454
+
+#define mmSIF_RTR_CTRL_6_NON_LIN_EN                                  0x366480
+
+#define mmSIF_RTR_CTRL_6_NL_SRAM_BANK_0                              0x366500
+
+#define mmSIF_RTR_CTRL_6_NL_SRAM_BANK_1                              0x366504
+
+#define mmSIF_RTR_CTRL_6_NL_SRAM_BANK_2                              0x366508
+
+#define mmSIF_RTR_CTRL_6_NL_SRAM_BANK_3                              0x36650C
+
+#define mmSIF_RTR_CTRL_6_NL_SRAM_BANK_4                              0x366510
+
+#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_0                            0x366514
+
+#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_1                            0x366520
+
+#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_2                            0x366524
+
+#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_3                            0x366528
+
+#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_4                            0x36652C
+
+#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_5                            0x366530
+
+#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_6                            0x366534
+
+#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_7                            0x366538
+
+#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_8                            0x36653C
+
+#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_9                            0x366540
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_0                             0x366550
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_1                             0x366554
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_2                             0x366558
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_3                             0x36655C
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_4                             0x366560
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_5                             0x366564
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_6                             0x366568
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_7                             0x36656C
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_8                             0x366570
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_9                             0x366574
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_10                            0x366578
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_11                            0x36657C
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_12                            0x366580
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_13                            0x366584
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_14                            0x366588
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_15                            0x36658C
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_16                            0x366590
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_17                            0x366594
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_18                            0x366598
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_0                     0x3665E4
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_1                     0x3665E8
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_2                     0x3665EC
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_3                     0x3665F0
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_4                     0x3665F4
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_5                     0x3665F8
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_6                     0x3665FC
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_7                     0x366600
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_8                     0x366604
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_9                     0x366608
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_10                    0x36660C
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_11                    0x366610
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_12                    0x366614
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_13                    0x366618
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_14                    0x36661C
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_15                    0x366620
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_0                    0x366624
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_1                    0x366628
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_2                    0x36662C
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_3                    0x366630
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_4                    0x366634
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_5                    0x366638
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_6                    0x36663C
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_7                    0x366640
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_8                    0x366644
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_9                    0x366648
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_10                   0x36664C
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_11                   0x366650
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_12                   0x366654
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_13                   0x366658
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_14                   0x36665C
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_15                   0x366660
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_0                     0x366664
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_1                     0x366668
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_2                     0x36666C
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_3                     0x366670
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_4                     0x366674
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_5                     0x366678
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_6                     0x36667C
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_7                     0x366680
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_8                     0x366684
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_9                     0x366688
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_10                    0x36668C
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_11                    0x366690
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_12                    0x366694
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_13                    0x366698
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_14                    0x36669C
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_15                    0x3666A0
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_0                    0x3666A4
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_1                    0x3666A8
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_2                    0x3666AC
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_3                    0x3666B0
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_4                    0x3666B4
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_5                    0x3666B8
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_6                    0x3666BC
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_7                    0x3666C0
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_8                    0x3666C4
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_9                    0x3666C8
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_10                   0x3666CC
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_11                   0x3666D0
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_12                   0x3666D4
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_13                   0x3666D8
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_14                   0x3666DC
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_15                   0x3666E0
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_0                    0x3666E4
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_1                    0x3666E8
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_2                    0x3666EC
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_3                    0x3666F0
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_4                    0x3666F4
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_5                    0x3666F8
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_6                    0x3666FC
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_7                    0x366700
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_8                    0x366704
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_9                    0x366708
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_10                   0x36670C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_11                   0x366710
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_12                   0x366714
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_13                   0x366718
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_14                   0x36671C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_15                   0x366720
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_0                   0x366724
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_1                   0x366728
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_2                   0x36672C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_3                   0x366730
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_4                   0x366734
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_5                   0x366738
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_6                   0x36673C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_7                   0x366740
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_8                   0x366744
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_9                   0x366748
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_10                  0x36674C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_11                  0x366750
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_12                  0x366754
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_13                  0x366758
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_14                  0x36675C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_15                  0x366760
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_0                    0x366764
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_1                    0x366768
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_2                    0x36676C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_3                    0x366770
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_4                    0x366774
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_5                    0x366778
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_6                    0x36677C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_7                    0x366780
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_8                    0x366784
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_9                    0x366788
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_10                   0x36678C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_11                   0x366790
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_12                   0x366794
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_13                   0x366798
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_14                   0x36679C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_15                   0x3667A0
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_0                   0x3667A4
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_1                   0x3667A8
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_2                   0x3667AC
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_3                   0x3667B0
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_4                   0x3667B4
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_5                   0x3667B8
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_6                   0x3667BC
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_7                   0x3667C0
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_8                   0x3667C4
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_9                   0x3667C8
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_10                  0x3667CC
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_11                  0x3667D0
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_12                  0x3667D4
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_13                  0x3667D8
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_14                  0x3667DC
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_15                  0x3667E0
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_0                     0x366824
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_1                     0x366828
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_2                     0x36682C
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_3                     0x366830
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_4                     0x366834
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_5                     0x366838
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_6                     0x36683C
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_7                     0x366840
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_8                     0x366844
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_9                     0x366848
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_10                    0x36684C
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_11                    0x366850
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_12                    0x366854
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_13                    0x366858
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_14                    0x36685C
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_15                    0x366860
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_0                    0x366864
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_1                    0x366868
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_2                    0x36686C
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_3                    0x366870
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_4                    0x366874
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_5                    0x366878
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_6                    0x36687C
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_7                    0x366880
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_8                    0x366884
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_9                    0x366888
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_10                   0x36688C
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_11                   0x366890
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_12                   0x366894
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_13                   0x366898
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_14                   0x36689C
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_15                   0x3668A0
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_0                     0x3668A4
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_1                     0x3668A8
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_2                     0x3668AC
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_3                     0x3668B0
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_4                     0x3668B4
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_5                     0x3668B8
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_6                     0x3668BC
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_7                     0x3668C0
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_8                     0x3668C4
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_9                     0x3668C8
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_10                    0x3668CC
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_11                    0x3668D0
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_12                    0x3668D4
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_13                    0x3668D8
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_14                    0x3668DC
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_15                    0x3668E0
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_0                    0x3668E4
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_1                    0x3668E8
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_2                    0x3668EC
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_3                    0x3668F0
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_4                    0x3668F4
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_5                    0x3668F8
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_6                    0x3668FC
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_7                    0x366900
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_8                    0x366904
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_9                    0x366908
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_10                   0x36690C
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_11                   0x366910
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_12                   0x366914
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_13                   0x366918
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_14                   0x36691C
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_15                   0x366920
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_0                    0x366924
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_1                    0x366928
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_2                    0x36692C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_3                    0x366930
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_4                    0x366934
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_5                    0x366938
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_6                    0x36693C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_7                    0x366940
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_8                    0x366944
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_9                    0x366948
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_10                   0x36694C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_11                   0x366950
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_12                   0x366954
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_13                   0x366958
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_14                   0x36695C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_15                   0x366960
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_0                   0x366964
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_1                   0x366968
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_2                   0x36696C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_3                   0x366970
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_4                   0x366974
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_5                   0x366978
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_6                   0x36697C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_7                   0x366980
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_8                   0x366984
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_9                   0x366988
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_10                  0x36698C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_11                  0x366990
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_12                  0x366994
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_13                  0x366998
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_14                  0x36699C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_15                  0x3669A0
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_0                    0x3669A4
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_1                    0x3669A8
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_2                    0x3669AC
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_3                    0x3669B0
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_4                    0x3669B4
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_5                    0x3669B8
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_6                    0x3669BC
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_7                    0x3669C0
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_8                    0x3669C4
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_9                    0x3669C8
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_10                   0x3669CC
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_11                   0x3669D0
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_12                   0x3669D4
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_13                   0x3669D8
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_14                   0x3669DC
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_15                   0x3669E0
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_0                   0x3669E4
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_1                   0x3669E8
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_2                   0x3669EC
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_3                   0x3669F0
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_4                   0x3669F4
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_5                   0x3669F8
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_6                   0x3669FC
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_7                   0x366A00
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_8                   0x366A04
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_9                   0x366A08
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_10                  0x366A0C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_11                  0x366A10
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_12                  0x366A14
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_13                  0x366A18
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_14                  0x366A1C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_15                  0x366A20
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_HIT_AW                            0x366A64
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_HIT_AR                            0x366A68
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_HIT_AW                           0x366A6C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_HIT_AR                           0x366A70
+
+#define mmSIF_RTR_CTRL_6_RGL_CFG                                     0x366B64
+
+#define mmSIF_RTR_CTRL_6_RGL_SHIFT                                   0x366B68
+
+#define mmSIF_RTR_CTRL_6_RGL_EXPECTED_LAT_0                          0x366B6C
+
+#define mmSIF_RTR_CTRL_6_RGL_EXPECTED_LAT_1                          0x366B70
+
+#define mmSIF_RTR_CTRL_6_RGL_EXPECTED_LAT_2                          0x366B74
+
+#define mmSIF_RTR_CTRL_6_RGL_EXPECTED_LAT_3                          0x366B78
+
+#define mmSIF_RTR_CTRL_6_RGL_EXPECTED_LAT_4                          0x366B7C
+
+#define mmSIF_RTR_CTRL_6_RGL_EXPECTED_LAT_5                          0x366B80
+
+#define mmSIF_RTR_CTRL_6_RGL_EXPECTED_LAT_6                          0x366B84
+
+#define mmSIF_RTR_CTRL_6_RGL_EXPECTED_LAT_7                          0x366B88
+
+#define mmSIF_RTR_CTRL_6_RGL_TOKEN_0                                 0x366BAC
+
+#define mmSIF_RTR_CTRL_6_RGL_TOKEN_1                                 0x366BB0
+
+#define mmSIF_RTR_CTRL_6_RGL_TOKEN_2                                 0x366BB4
+
+#define mmSIF_RTR_CTRL_6_RGL_TOKEN_3                                 0x366BB8
+
+#define mmSIF_RTR_CTRL_6_RGL_TOKEN_4                                 0x366BBC
+
+#define mmSIF_RTR_CTRL_6_RGL_TOKEN_5                                 0x366BC0
+
+#define mmSIF_RTR_CTRL_6_RGL_TOKEN_6                                 0x366BC4
+
+#define mmSIF_RTR_CTRL_6_RGL_TOKEN_7                                 0x366BC8
+
+#define mmSIF_RTR_CTRL_6_RGL_BANK_ID_0                               0x366BEC
+
+#define mmSIF_RTR_CTRL_6_RGL_BANK_ID_1                               0x366BF0
+
+#define mmSIF_RTR_CTRL_6_RGL_BANK_ID_2                               0x366BF4
+
+#define mmSIF_RTR_CTRL_6_RGL_BANK_ID_3                               0x366BF8
+
+#define mmSIF_RTR_CTRL_6_RGL_BANK_ID_4                               0x366BFC
+
+#define mmSIF_RTR_CTRL_6_RGL_BANK_ID_5                               0x366C00
+
+#define mmSIF_RTR_CTRL_6_RGL_BANK_ID_6                               0x366C04
+
+#define mmSIF_RTR_CTRL_6_RGL_BANK_ID_7                               0x366C08
+
+#define mmSIF_RTR_CTRL_6_RGL_WDT                                     0x366C2C
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_HBM0_CH0_CTR_WRAP                    0x366C30
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_HBM0_CH1_CTR_WRAP                    0x366C34
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_HBM1_CH0_CTR_WRAP                    0x366C38
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_HBM1_CH1_CTR_WRAP                    0x366C3C
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_HBM2_CH0_CTR_WRAP                    0x366C40
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_HBM2_CH1_CTR_WRAP                    0x366C44
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_HBM3_CH0_CTR_WRAP                    0x366C48
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_HBM3_CH1_CTR_WRAP                    0x366C4C
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_HBM0_CH0_CTR_CNT                     0x366C50
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_HBM0_CH1_CTR_CNT                     0x366C54
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_HBM1_CH0_CTR_CNT                     0x366C58
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_HBM1_CH1_CTR_CNT                     0x366C5C
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_HBM2_CH0_CTR_CNT                     0x366C60
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_HBM2_CH1_CTR_CNT                     0x366C64
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_HBM3_CH0_CTR_CNT                     0x366C68
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_HBM3_CH1_CTR_CNT                     0x366C6C
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_HBM0_CH0_CTR_WRAP                    0x366C70
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_HBM0_CH1_CTR_WRAP                    0x366C74
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_HBM1_CH0_CTR_WRAP                    0x366C78
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_HBM1_CH1_CTR_WRAP                    0x366C7C
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_HBM2_CH0_CTR_WRAP                    0x366C80
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_HBM2_CH1_CTR_WRAP                    0x366C84
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_HBM3_CH0_CTR_WRAP                    0x366C88
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_HBM3_CH1_CTR_WRAP                    0x366C8C
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_HBM0_CH0_CTR_CNT                     0x366C90
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_HBM0_CH1_CTR_CNT                     0x366C94
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_HBM1_CH0_CTR_CNT                     0x366C98
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_HBM1_CH1_CTR_CNT                     0x366C9C
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_HBM2_CH0_CTR_CNT                     0x366CA0
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_HBM2_CH1_CTR_CNT                     0x366CA4
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_HBM3_CH0_CTR_CNT                     0x366CA8
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_HBM3_CH1_CTR_CNT                     0x366CAC
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_PC_SEL_0                             0x366CB0
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_PC_SEL_1                             0x366CB4
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_PC_SEL_2                             0x366CB8
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_PC_SEL_3                             0x366CBC
+
+#endif /* ASIC_REG_SIF_RTR_CTRL_6_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_7_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_7_regs.h
new file mode 100644
index 000000000000..a37772c531d9
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_7_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_SIF_RTR_CTRL_7_REGS_H_
+#define ASIC_REG_SIF_RTR_CTRL_7_REGS_H_
+
+/*
+ *****************************************
+ *   SIF_RTR_CTRL_7 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmSIF_RTR_CTRL_7_PERM_SEL                                    0x376108
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_0                               0x376114
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_1                               0x376118
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_2                               0x37611C
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_3                               0x376120
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_4                               0x376124
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_5                               0x376128
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_6                               0x37612C
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_7                               0x376130
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_8                               0x376134
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_9                               0x376138
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_10                              0x37613C
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_11                              0x376140
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_12                              0x376144
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_13                              0x376148
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_14                              0x37614C
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_15                              0x376150
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_16                              0x376154
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_17                              0x376158
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_18                              0x37615C
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_19                              0x376160
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_20                              0x376164
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_21                              0x376168
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_22                              0x37616C
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_23                              0x376170
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_24                              0x376174
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_25                              0x376178
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_26                              0x37617C
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_27                              0x376180
+
+#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_0                              0x376184
+
+#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_1                              0x376188
+
+#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_2                              0x37618C
+
+#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_3                              0x376190
+
+#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_4                              0x376194
+
+#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_5                              0x376198
+
+#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_6                              0x37619C
+
+#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_7                              0x3761A0
+
+#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_8                              0x3761A4
+
+#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_9                              0x3761A8
+
+#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_10                             0x3761AC
+
+#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_11                             0x3761B0
+
+#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_12                             0x3761B4
+
+#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_13                             0x3761B8
+
+#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_14                             0x3761BC
+
+#define mmSIF_RTR_CTRL_7_SCRAM_SRAM_EN                               0x37626C
+
+#define mmSIF_RTR_CTRL_7_RL_HBM_EN                                   0x376274
+
+#define mmSIF_RTR_CTRL_7_RL_HBM_SAT                                  0x376278
+
+#define mmSIF_RTR_CTRL_7_RL_HBM_RST                                  0x37627C
+
+#define mmSIF_RTR_CTRL_7_RL_HBM_TIMEOUT                              0x376280
+
+#define mmSIF_RTR_CTRL_7_SCRAM_HBM_EN                                0x376284
+
+#define mmSIF_RTR_CTRL_7_RL_PCI_EN                                   0x376288
+
+#define mmSIF_RTR_CTRL_7_RL_PCI_SAT                                  0x37628C
+
+#define mmSIF_RTR_CTRL_7_RL_PCI_RST                                  0x376290
+
+#define mmSIF_RTR_CTRL_7_RL_PCI_TIMEOUT                              0x376294
+
+#define mmSIF_RTR_CTRL_7_RL_SRAM_EN                                  0x37629C
+
+#define mmSIF_RTR_CTRL_7_RL_SRAM_SAT                                 0x3762A0
+
+#define mmSIF_RTR_CTRL_7_RL_SRAM_RST                                 0x3762A4
+
+#define mmSIF_RTR_CTRL_7_RL_SRAM_TIMEOUT                             0x3762AC
+
+#define mmSIF_RTR_CTRL_7_RL_SRAM_RED                                 0x3762B4
+
+#define mmSIF_RTR_CTRL_7_E2E_HBM_EN                                  0x3762EC
+
+#define mmSIF_RTR_CTRL_7_E2E_PCI_EN                                  0x3762F0
+
+#define mmSIF_RTR_CTRL_7_E2E_HBM_WR_SIZE                             0x3762F4
+
+#define mmSIF_RTR_CTRL_7_E2E_PCI_WR_SIZE                             0x3762F8
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_PCI_CTR_SET_EN                       0x376404
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_PCI_CTR_SET                          0x376408
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_PCI_CTR_WRAP                         0x37640C
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_PCI_CTR_CNT                          0x376410
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_HBM_CTR_SET_EN                       0x376414
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_HBM_CTR_SET                          0x376418
+
+#define mmSIF_RTR_CTRL_7_E2E_HBM_RD_SIZE                             0x37641C
+
+#define mmSIF_RTR_CTRL_7_E2E_PCI_RD_SIZE                             0x376420
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_PCI_CTR_SET_EN                       0x376424
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_PCI_CTR_SET                          0x376428
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_PCI_CTR_WRAP                         0x37642C
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_PCI_CTR_CNT                          0x376430
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_HBM_CTR_SET_EN                       0x376434
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_HBM_CTR_SET                          0x376438
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_SEL_0                                0x376450
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_SEL_1                                0x376454
+
+#define mmSIF_RTR_CTRL_7_NON_LIN_EN                                  0x376480
+
+#define mmSIF_RTR_CTRL_7_NL_SRAM_BANK_0                              0x376500
+
+#define mmSIF_RTR_CTRL_7_NL_SRAM_BANK_1                              0x376504
+
+#define mmSIF_RTR_CTRL_7_NL_SRAM_BANK_2                              0x376508
+
+#define mmSIF_RTR_CTRL_7_NL_SRAM_BANK_3                              0x37650C
+
+#define mmSIF_RTR_CTRL_7_NL_SRAM_BANK_4                              0x376510
+
+#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_0                            0x376514
+
+#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_1                            0x376520
+
+#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_2                            0x376524
+
+#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_3                            0x376528
+
+#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_4                            0x37652C
+
+#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_5                            0x376530
+
+#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_6                            0x376534
+
+#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_7                            0x376538
+
+#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_8                            0x37653C
+
+#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_9                            0x376540
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_0                             0x376550
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_1                             0x376554
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_2                             0x376558
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_3                             0x37655C
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_4                             0x376560
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_5                             0x376564
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_6                             0x376568
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_7                             0x37656C
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_8                             0x376570
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_9                             0x376574
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_10                            0x376578
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_11                            0x37657C
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_12                            0x376580
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_13                            0x376584
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_14                            0x376588
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_15                            0x37658C
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_16                            0x376590
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_17                            0x376594
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_18                            0x376598
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_0                     0x3765E4
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_1                     0x3765E8
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_2                     0x3765EC
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_3                     0x3765F0
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_4                     0x3765F4
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_5                     0x3765F8
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_6                     0x3765FC
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_7                     0x376600
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_8                     0x376604
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_9                     0x376608
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_10                    0x37660C
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_11                    0x376610
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_12                    0x376614
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_13                    0x376618
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_14                    0x37661C
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_15                    0x376620
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_0                    0x376624
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_1                    0x376628
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_2                    0x37662C
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_3                    0x376630
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_4                    0x376634
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_5                    0x376638
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_6                    0x37663C
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_7                    0x376640
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_8                    0x376644
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_9                    0x376648
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_10                   0x37664C
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_11                   0x376650
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_12                   0x376654
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_13                   0x376658
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_14                   0x37665C
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_15                   0x376660
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_0                     0x376664
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_1                     0x376668
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_2                     0x37666C
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_3                     0x376670
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_4                     0x376674
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_5                     0x376678
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_6                     0x37667C
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_7                     0x376680
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_8                     0x376684
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_9                     0x376688
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_10                    0x37668C
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_11                    0x376690
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_12                    0x376694
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_13                    0x376698
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_14                    0x37669C
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_15                    0x3766A0
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_0                    0x3766A4
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_1                    0x3766A8
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_2                    0x3766AC
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_3                    0x3766B0
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_4                    0x3766B4
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_5                    0x3766B8
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_6                    0x3766BC
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_7                    0x3766C0
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_8                    0x3766C4
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_9                    0x3766C8
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_10                   0x3766CC
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_11                   0x3766D0
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_12                   0x3766D4
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_13                   0x3766D8
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_14                   0x3766DC
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_15                   0x3766E0
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_0                    0x3766E4
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_1                    0x3766E8
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_2                    0x3766EC
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_3                    0x3766F0
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_4                    0x3766F4
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_5                    0x3766F8
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_6                    0x3766FC
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_7                    0x376700
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_8                    0x376704
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_9                    0x376708
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_10                   0x37670C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_11                   0x376710
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_12                   0x376714
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_13                   0x376718
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_14                   0x37671C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_15                   0x376720
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_0                   0x376724
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_1                   0x376728
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_2                   0x37672C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_3                   0x376730
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_4                   0x376734
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_5                   0x376738
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_6                   0x37673C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_7                   0x376740
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_8                   0x376744
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_9                   0x376748
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_10                  0x37674C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_11                  0x376750
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_12                  0x376754
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_13                  0x376758
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_14                  0x37675C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_15                  0x376760
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_0                    0x376764
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_1                    0x376768
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_2                    0x37676C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_3                    0x376770
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_4                    0x376774
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_5                    0x376778
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_6                    0x37677C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_7                    0x376780
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_8                    0x376784
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_9                    0x376788
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_10                   0x37678C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_11                   0x376790
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_12                   0x376794
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_13                   0x376798
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_14                   0x37679C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_15                   0x3767A0
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_0                   0x3767A4
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_1                   0x3767A8
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_2                   0x3767AC
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_3                   0x3767B0
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_4                   0x3767B4
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_5                   0x3767B8
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_6                   0x3767BC
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_7                   0x3767C0
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_8                   0x3767C4
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_9                   0x3767C8
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_10                  0x3767CC
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_11                  0x3767D0
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_12                  0x3767D4
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_13                  0x3767D8
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_14                  0x3767DC
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_15                  0x3767E0
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_0                     0x376824
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_1                     0x376828
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_2                     0x37682C
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_3                     0x376830
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_4                     0x376834
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_5                     0x376838
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_6                     0x37683C
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_7                     0x376840
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_8                     0x376844
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_9                     0x376848
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_10                    0x37684C
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_11                    0x376850
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_12                    0x376854
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_13                    0x376858
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_14                    0x37685C
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_15                    0x376860
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_0                    0x376864
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_1                    0x376868
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_2                    0x37686C
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_3                    0x376870
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_4                    0x376874
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_5                    0x376878
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_6                    0x37687C
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_7                    0x376880
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_8                    0x376884
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_9                    0x376888
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_10                   0x37688C
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_11                   0x376890
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_12                   0x376894
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_13                   0x376898
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_14                   0x37689C
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_15                   0x3768A0
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_0                     0x3768A4
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_1                     0x3768A8
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_2                     0x3768AC
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_3                     0x3768B0
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_4                     0x3768B4
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_5                     0x3768B8
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_6                     0x3768BC
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_7                     0x3768C0
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_8                     0x3768C4
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_9                     0x3768C8
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_10                    0x3768CC
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_11                    0x3768D0
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_12                    0x3768D4
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_13                    0x3768D8
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_14                    0x3768DC
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_15                    0x3768E0
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_0                    0x3768E4
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_1                    0x3768E8
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_2                    0x3768EC
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_3                    0x3768F0
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_4                    0x3768F4
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_5                    0x3768F8
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_6                    0x3768FC
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_7                    0x376900
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_8                    0x376904
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_9                    0x376908
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_10                   0x37690C
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_11                   0x376910
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_12                   0x376914
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_13                   0x376918
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_14                   0x37691C
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_15                   0x376920
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_0                    0x376924
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_1                    0x376928
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_2                    0x37692C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_3                    0x376930
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_4                    0x376934
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_5                    0x376938
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_6                    0x37693C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_7                    0x376940
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_8                    0x376944
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_9                    0x376948
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_10                   0x37694C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_11                   0x376950
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_12                   0x376954
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_13                   0x376958
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_14                   0x37695C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_15                   0x376960
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_0                   0x376964
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_1                   0x376968
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_2                   0x37696C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_3                   0x376970
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_4                   0x376974
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_5                   0x376978
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_6                   0x37697C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_7                   0x376980
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_8                   0x376984
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_9                   0x376988
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_10                  0x37698C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_11                  0x376990
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_12                  0x376994
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_13                  0x376998
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_14                  0x37699C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_15                  0x3769A0
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_0                    0x3769A4
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_1                    0x3769A8
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_2                    0x3769AC
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_3                    0x3769B0
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_4                    0x3769B4
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_5                    0x3769B8
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_6                    0x3769BC
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_7                    0x3769C0
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_8                    0x3769C4
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_9                    0x3769C8
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_10                   0x3769CC
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_11                   0x3769D0
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_12                   0x3769D4
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_13                   0x3769D8
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_14                   0x3769DC
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_15                   0x3769E0
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_0                   0x3769E4
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_1                   0x3769E8
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_2                   0x3769EC
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_3                   0x3769F0
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_4                   0x3769F4
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_5                   0x3769F8
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_6                   0x3769FC
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_7                   0x376A00
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_8                   0x376A04
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_9                   0x376A08
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_10                  0x376A0C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_11                  0x376A10
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_12                  0x376A14
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_13                  0x376A18
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_14                  0x376A1C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_15                  0x376A20
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_HIT_AW                            0x376A64
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_HIT_AR                            0x376A68
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_HIT_AW                           0x376A6C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_HIT_AR                           0x376A70
+
+#define mmSIF_RTR_CTRL_7_RGL_CFG                                     0x376B64
+
+#define mmSIF_RTR_CTRL_7_RGL_SHIFT                                   0x376B68
+
+#define mmSIF_RTR_CTRL_7_RGL_EXPECTED_LAT_0                          0x376B6C
+
+#define mmSIF_RTR_CTRL_7_RGL_EXPECTED_LAT_1                          0x376B70
+
+#define mmSIF_RTR_CTRL_7_RGL_EXPECTED_LAT_2                          0x376B74
+
+#define mmSIF_RTR_CTRL_7_RGL_EXPECTED_LAT_3                          0x376B78
+
+#define mmSIF_RTR_CTRL_7_RGL_EXPECTED_LAT_4                          0x376B7C
+
+#define mmSIF_RTR_CTRL_7_RGL_EXPECTED_LAT_5                          0x376B80
+
+#define mmSIF_RTR_CTRL_7_RGL_EXPECTED_LAT_6                          0x376B84
+
+#define mmSIF_RTR_CTRL_7_RGL_EXPECTED_LAT_7                          0x376B88
+
+#define mmSIF_RTR_CTRL_7_RGL_TOKEN_0                                 0x376BAC
+
+#define mmSIF_RTR_CTRL_7_RGL_TOKEN_1                                 0x376BB0
+
+#define mmSIF_RTR_CTRL_7_RGL_TOKEN_2                                 0x376BB4
+
+#define mmSIF_RTR_CTRL_7_RGL_TOKEN_3                                 0x376BB8
+
+#define mmSIF_RTR_CTRL_7_RGL_TOKEN_4                                 0x376BBC
+
+#define mmSIF_RTR_CTRL_7_RGL_TOKEN_5                                 0x376BC0
+
+#define mmSIF_RTR_CTRL_7_RGL_TOKEN_6                                 0x376BC4
+
+#define mmSIF_RTR_CTRL_7_RGL_TOKEN_7                                 0x376BC8
+
+#define mmSIF_RTR_CTRL_7_RGL_BANK_ID_0                               0x376BEC
+
+#define mmSIF_RTR_CTRL_7_RGL_BANK_ID_1                               0x376BF0
+
+#define mmSIF_RTR_CTRL_7_RGL_BANK_ID_2                               0x376BF4
+
+#define mmSIF_RTR_CTRL_7_RGL_BANK_ID_3                               0x376BF8
+
+#define mmSIF_RTR_CTRL_7_RGL_BANK_ID_4                               0x376BFC
+
+#define mmSIF_RTR_CTRL_7_RGL_BANK_ID_5                               0x376C00
+
+#define mmSIF_RTR_CTRL_7_RGL_BANK_ID_6                               0x376C04
+
+#define mmSIF_RTR_CTRL_7_RGL_BANK_ID_7                               0x376C08
+
+#define mmSIF_RTR_CTRL_7_RGL_WDT                                     0x376C2C
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_HBM0_CH0_CTR_WRAP                    0x376C30
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_HBM0_CH1_CTR_WRAP                    0x376C34
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_HBM1_CH0_CTR_WRAP                    0x376C38
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_HBM1_CH1_CTR_WRAP                    0x376C3C
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_HBM2_CH0_CTR_WRAP                    0x376C40
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_HBM2_CH1_CTR_WRAP                    0x376C44
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_HBM3_CH0_CTR_WRAP                    0x376C48
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_HBM3_CH1_CTR_WRAP                    0x376C4C
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_HBM0_CH0_CTR_CNT                     0x376C50
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_HBM0_CH1_CTR_CNT                     0x376C54
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_HBM1_CH0_CTR_CNT                     0x376C58
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_HBM1_CH1_CTR_CNT                     0x376C5C
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_HBM2_CH0_CTR_CNT                     0x376C60
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_HBM2_CH1_CTR_CNT                     0x376C64
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_HBM3_CH0_CTR_CNT                     0x376C68
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_HBM3_CH1_CTR_CNT                     0x376C6C
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_HBM0_CH0_CTR_WRAP                    0x376C70
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_HBM0_CH1_CTR_WRAP                    0x376C74
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_HBM1_CH0_CTR_WRAP                    0x376C78
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_HBM1_CH1_CTR_WRAP                    0x376C7C
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_HBM2_CH0_CTR_WRAP                    0x376C80
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_HBM2_CH1_CTR_WRAP                    0x376C84
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_HBM3_CH0_CTR_WRAP                    0x376C88
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_HBM3_CH1_CTR_WRAP                    0x376C8C
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_HBM0_CH0_CTR_CNT                     0x376C90
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_HBM0_CH1_CTR_CNT                     0x376C94
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_HBM1_CH0_CTR_CNT                     0x376C98
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_HBM1_CH1_CTR_CNT                     0x376C9C
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_HBM2_CH0_CTR_CNT                     0x376CA0
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_HBM2_CH1_CTR_CNT                     0x376CA4
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_HBM3_CH0_CTR_CNT                     0x376CA8
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_HBM3_CH1_CTR_CNT                     0x376CAC
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_PC_SEL_0                             0x376CB0
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_PC_SEL_1                             0x376CB4
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_PC_SEL_2                             0x376CB8
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_PC_SEL_3                             0x376CBC
+
+#endif /* ASIC_REG_SIF_RTR_CTRL_7_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/stlb_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/stlb_regs.h
new file mode 100644
index 000000000000..07d2a9000102
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/stlb_regs.h
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_STLB_REGS_H_
+#define ASIC_REG_STLB_REGS_H_
+
+/*
+ *****************************************
+ *   STLB (Prototype: STLB)
+ *****************************************
+ */
+
+#define mmSTLB_CACHE_INV                                             0xC12010
+
+#define mmSTLB_CACHE_INV_BASE_39_8                                   0xC12014
+
+#define mmSTLB_CACHE_INV_BASE_49_40                                  0xC12018
+
+#define mmSTLB_STLB_FEATURE_EN                                       0xC1201C
+
+#define mmSTLB_STLB_AXI_CACHE                                        0xC12020
+
+#define mmSTLB_HOP_CONFIGURATION                                     0xC12024
+
+#define mmSTLB_LINK_LIST_LOOKUP_MASK_49_32                           0xC12028
+
+#define mmSTLB_LINK_LIST_LOOKUP_MASK_31_0                            0xC1202C
+
+#define mmSTLB_LINK_LIST                                             0xC12030
+
+#define mmSTLB_INV_ALL_START                                         0xC12034
+
+#define mmSTLB_INV_ALL_SET                                           0xC12038
+
+#define mmSTLB_INV_PS                                                0xC1203C
+
+#define mmSTLB_INV_CONSUMER_INDEX                                    0xC12040
+
+#define mmSTLB_INV_HIT_COUNT                                         0xC12044
+
+#define mmSTLB_INV_SET                                               0xC12048
+
+#define mmSTLB_SRAM_INIT                                             0xC1204C
+
+#define mmSTLB_MEM_CACHE_INVALIDATION                                0xC12050
+
+#define mmSTLB_MEM_CACHE_INV_STATUS                                  0xC12054
+
+#define mmSTLB_MEM_CACHE_BASE_38_7                                   0xC12058
+
+#define mmSTLB_MEM_CACHE_BASE_49_39                                  0xC1205C
+
+#define mmSTLB_MEM_CACHE_CONFIG                                      0xC12060
+
+#define mmSTLB_SET_THRESHOLD_HOP4                                    0xC12064
+
+#define mmSTLB_SET_THRESHOLD_HOP3                                    0xC12068
+
+#define mmSTLB_SET_THRESHOLD_HOP2                                    0xC1206C
+
+#define mmSTLB_SET_THRESHOLD_HOP1                                    0xC12070
+
+#define mmSTLB_SET_THRESHOLD_HOP0                                    0xC12074
+
+#define mmSTLB_MULTI_HIT_INTERRUPT_CLR                               0xC12078
+
+#define mmSTLB_MULTI_HIT_INTERRUPT_MASK                              0xC1207C
+
+#define mmSTLB_MEM_L0_CACHE_CFG                                      0xC12080
+
+#define mmSTLB_MEM_READ_ARPROT                                       0xC12084
+
+#endif /* ASIC_REG_STLB_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc0_cfg_masks.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc0_cfg_masks.h
new file mode 100644
index 000000000000..8f67c11c8de9
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc0_cfg_masks.h
@@ -0,0 +1,2578 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_TPC0_CFG_MASKS_H_
+#define ASIC_REG_TPC0_CFG_MASKS_H_
+
+/*
+ *****************************************
+ *   TPC0_CFG (Prototype: TPC)
+ *****************************************
+ */
+
+/* TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW */
+#define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH */
+#define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT              0
+#define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE */
+#define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG */
+#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
+#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK        0x7
+#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
+#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
+#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_SHIFT        16
+#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
+#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_SET_SHIFT         19
+#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_SET_MASK          0x80000
+#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_RESERV_SHIFT      20
+#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_RESERV_MASK       0x100000
+#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_OP_SHIFT          21
+#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_OP_MASK           0x600000
+
+/* TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW */
+#define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH */
+#define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH_V_SHIFT              0
+#define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE */
+#define TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG */
+#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
+#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_MASK        0x7
+#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
+#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
+#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_LAST_DIM_SHIFT        16
+#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
+#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_SET_SHIFT         19
+#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_SET_MASK          0x80000
+#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_RESERV_SHIFT      20
+#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_RESERV_MASK       0x100000
+#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_OP_SHIFT          21
+#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_OP_MASK           0x600000
+
+/* TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW */
+#define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH */
+#define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH_V_SHIFT              0
+#define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE */
+#define TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG */
+#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
+#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_MASK        0x7
+#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
+#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
+#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_LAST_DIM_SHIFT        16
+#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
+#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_SET_SHIFT         19
+#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_SET_MASK          0x80000
+#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_RESERV_SHIFT      20
+#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_RESERV_MASK       0x100000
+#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_OP_SHIFT          21
+#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_OP_MASK           0x600000
+
+/* TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW */
+#define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH */
+#define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH_V_SHIFT              0
+#define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE */
+#define TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG */
+#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
+#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_MASK        0x7
+#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
+#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
+#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_LAST_DIM_SHIFT        16
+#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
+#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_SET_SHIFT         19
+#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_SET_MASK          0x80000
+#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_RESERV_SHIFT      20
+#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_RESERV_MASK       0x100000
+#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_OP_SHIFT          21
+#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_OP_MASK           0x600000
+
+/* TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW */
+#define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH */
+#define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH_V_SHIFT              0
+#define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE */
+#define TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG */
+#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
+#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_MASK        0x7
+#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
+#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
+#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_LAST_DIM_SHIFT        16
+#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
+#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_SET_SHIFT         19
+#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_SET_MASK          0x80000
+#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_RESERV_SHIFT      20
+#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_RESERV_MASK       0x100000
+#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_OP_SHIFT          21
+#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_OP_MASK           0x600000
+
+/* TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW */
+#define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH */
+#define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH_V_SHIFT              0
+#define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE */
+#define TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG */
+#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
+#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_MASK        0x7
+#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
+#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
+#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_LAST_DIM_SHIFT        16
+#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
+#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_SET_SHIFT         19
+#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_SET_MASK          0x80000
+#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_RESERV_SHIFT      20
+#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_RESERV_MASK       0x100000
+#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_OP_SHIFT          21
+#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_OP_MASK           0x600000
+
+/* TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW */
+#define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH */
+#define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH_V_SHIFT              0
+#define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE */
+#define TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG */
+#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
+#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_MASK        0x7
+#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
+#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
+#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_LAST_DIM_SHIFT        16
+#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
+#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_SET_SHIFT         19
+#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_SET_MASK          0x80000
+#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_RESERV_SHIFT      20
+#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_RESERV_MASK       0x100000
+#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_OP_SHIFT          21
+#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_OP_MASK           0x600000
+
+/* TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW */
+#define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH */
+#define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH_V_SHIFT              0
+#define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE */
+#define TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG */
+#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
+#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_MASK        0x7
+#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
+#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
+#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_LAST_DIM_SHIFT        16
+#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
+#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_SET_SHIFT         19
+#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_SET_MASK          0x80000
+#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_RESERV_SHIFT      20
+#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_RESERV_MASK       0x100000
+#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_OP_SHIFT          21
+#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_OP_MASK           0x600000
+
+/* TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW */
+#define TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH */
+#define TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH_V_SHIFT              0
+#define TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_8_PADDING_VALUE */
+#define TPC0_CFG_KERNEL_TENSOR_8_PADDING_VALUE_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_8_PADDING_VALUE_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG */
+#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
+#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_DATA_TYPE_MASK        0x7
+#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
+#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
+#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_LAST_DIM_SHIFT        16
+#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
+#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_SET_SHIFT         19
+#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_SET_MASK          0x80000
+#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_RESERV_SHIFT      20
+#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_RESERV_MASK       0x100000
+#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_OP_SHIFT          21
+#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_OP_MASK           0x600000
+
+/* TPC0_CFG_KERNEL_TENSOR_8_DIM_0_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_8_DIM_0_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_8_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_8_DIM_1_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_8_DIM_1_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_8_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_8_DIM_2_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_8_DIM_2_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_8_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_8_DIM_3_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_8_DIM_3_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_8_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_8_DIM_4_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_8_DIM_4_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_8_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW */
+#define TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH */
+#define TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH_V_SHIFT              0
+#define TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_9_PADDING_VALUE */
+#define TPC0_CFG_KERNEL_TENSOR_9_PADDING_VALUE_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_9_PADDING_VALUE_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG */
+#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
+#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_DATA_TYPE_MASK        0x7
+#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
+#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
+#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_LAST_DIM_SHIFT        16
+#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
+#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_SET_SHIFT         19
+#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_SET_MASK          0x80000
+#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_RESERV_SHIFT      20
+#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_RESERV_MASK       0x100000
+#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_OP_SHIFT          21
+#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_OP_MASK           0x600000
+
+/* TPC0_CFG_KERNEL_TENSOR_9_DIM_0_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_9_DIM_0_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_9_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_9_DIM_1_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_9_DIM_1_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_9_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_9_DIM_2_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_9_DIM_2_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_9_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_9_DIM_3_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_9_DIM_3_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_9_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_9_DIM_4_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_9_DIM_4_SIZE_V_SHIFT                  0
+#define TPC0_CFG_KERNEL_TENSOR_9_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE_V_SHIFT                0
+#define TPC0_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW */
+#define TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW_V_SHIFT              0
+#define TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW_V_MASK               0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH */
+#define TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH_V_SHIFT             0
+#define TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH_V_MASK              0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_10_PADDING_VALUE */
+#define TPC0_CFG_KERNEL_TENSOR_10_PADDING_VALUE_V_SHIFT              0
+#define TPC0_CFG_KERNEL_TENSOR_10_PADDING_VALUE_V_MASK               0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG */
+#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_DATA_TYPE_SHIFT      0
+#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_DATA_TYPE_MASK       0x7
+#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
+#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_VALID_DIM_MASK_MASK  0x1F00
+#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_LAST_DIM_SHIFT       16
+#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_LAST_DIM_MASK        0x70000
+#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_SET_SHIFT        19
+#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_SET_MASK         0x80000
+#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_RESERV_SHIFT     20
+#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_RESERV_MASK      0x100000
+#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_OP_SHIFT         21
+#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_OP_MASK          0x600000
+
+/* TPC0_CFG_KERNEL_TENSOR_10_DIM_0_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_10_DIM_0_SIZE_V_SHIFT                 0
+#define TPC0_CFG_KERNEL_TENSOR_10_DIM_0_SIZE_V_MASK                  0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_10_DIM_1_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_10_DIM_1_SIZE_V_SHIFT                 0
+#define TPC0_CFG_KERNEL_TENSOR_10_DIM_1_SIZE_V_MASK                  0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_10_DIM_2_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_10_DIM_2_SIZE_V_SHIFT                 0
+#define TPC0_CFG_KERNEL_TENSOR_10_DIM_2_SIZE_V_MASK                  0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_10_DIM_3_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_10_DIM_3_SIZE_V_SHIFT                 0
+#define TPC0_CFG_KERNEL_TENSOR_10_DIM_3_SIZE_V_MASK                  0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_10_DIM_4_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_10_DIM_4_SIZE_V_SHIFT                 0
+#define TPC0_CFG_KERNEL_TENSOR_10_DIM_4_SIZE_V_MASK                  0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW */
+#define TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW_V_SHIFT              0
+#define TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW_V_MASK               0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH */
+#define TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH_V_SHIFT             0
+#define TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH_V_MASK              0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_11_PADDING_VALUE */
+#define TPC0_CFG_KERNEL_TENSOR_11_PADDING_VALUE_V_SHIFT              0
+#define TPC0_CFG_KERNEL_TENSOR_11_PADDING_VALUE_V_MASK               0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG */
+#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_DATA_TYPE_SHIFT      0
+#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_DATA_TYPE_MASK       0x7
+#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
+#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_VALID_DIM_MASK_MASK  0x1F00
+#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_LAST_DIM_SHIFT       16
+#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_LAST_DIM_MASK        0x70000
+#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_SET_SHIFT        19
+#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_SET_MASK         0x80000
+#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_RESERV_SHIFT     20
+#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_RESERV_MASK      0x100000
+#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_OP_SHIFT         21
+#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_OP_MASK          0x600000
+
+/* TPC0_CFG_KERNEL_TENSOR_11_DIM_0_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_11_DIM_0_SIZE_V_SHIFT                 0
+#define TPC0_CFG_KERNEL_TENSOR_11_DIM_0_SIZE_V_MASK                  0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_11_DIM_1_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_11_DIM_1_SIZE_V_SHIFT                 0
+#define TPC0_CFG_KERNEL_TENSOR_11_DIM_1_SIZE_V_MASK                  0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_11_DIM_2_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_11_DIM_2_SIZE_V_SHIFT                 0
+#define TPC0_CFG_KERNEL_TENSOR_11_DIM_2_SIZE_V_MASK                  0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_11_DIM_3_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_11_DIM_3_SIZE_V_SHIFT                 0
+#define TPC0_CFG_KERNEL_TENSOR_11_DIM_3_SIZE_V_MASK                  0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_11_DIM_4_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_11_DIM_4_SIZE_V_SHIFT                 0
+#define TPC0_CFG_KERNEL_TENSOR_11_DIM_4_SIZE_V_MASK                  0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW */
+#define TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW_V_SHIFT              0
+#define TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW_V_MASK               0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH */
+#define TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH_V_SHIFT             0
+#define TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH_V_MASK              0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_12_PADDING_VALUE */
+#define TPC0_CFG_KERNEL_TENSOR_12_PADDING_VALUE_V_SHIFT              0
+#define TPC0_CFG_KERNEL_TENSOR_12_PADDING_VALUE_V_MASK               0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG */
+#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_DATA_TYPE_SHIFT      0
+#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_DATA_TYPE_MASK       0x7
+#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
+#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_VALID_DIM_MASK_MASK  0x1F00
+#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_LAST_DIM_SHIFT       16
+#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_LAST_DIM_MASK        0x70000
+#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_SET_SHIFT        19
+#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_SET_MASK         0x80000
+#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_RESERV_SHIFT     20
+#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_RESERV_MASK      0x100000
+#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_OP_SHIFT         21
+#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_OP_MASK          0x600000
+
+/* TPC0_CFG_KERNEL_TENSOR_12_DIM_0_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_12_DIM_0_SIZE_V_SHIFT                 0
+#define TPC0_CFG_KERNEL_TENSOR_12_DIM_0_SIZE_V_MASK                  0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_12_DIM_1_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_12_DIM_1_SIZE_V_SHIFT                 0
+#define TPC0_CFG_KERNEL_TENSOR_12_DIM_1_SIZE_V_MASK                  0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_12_DIM_2_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_12_DIM_2_SIZE_V_SHIFT                 0
+#define TPC0_CFG_KERNEL_TENSOR_12_DIM_2_SIZE_V_MASK                  0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_12_DIM_3_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_12_DIM_3_SIZE_V_SHIFT                 0
+#define TPC0_CFG_KERNEL_TENSOR_12_DIM_3_SIZE_V_MASK                  0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_12_DIM_4_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_12_DIM_4_SIZE_V_SHIFT                 0
+#define TPC0_CFG_KERNEL_TENSOR_12_DIM_4_SIZE_V_MASK                  0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW */
+#define TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW_V_SHIFT              0
+#define TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW_V_MASK               0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH */
+#define TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH_V_SHIFT             0
+#define TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH_V_MASK              0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_13_PADDING_VALUE */
+#define TPC0_CFG_KERNEL_TENSOR_13_PADDING_VALUE_V_SHIFT              0
+#define TPC0_CFG_KERNEL_TENSOR_13_PADDING_VALUE_V_MASK               0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG */
+#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_DATA_TYPE_SHIFT      0
+#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_DATA_TYPE_MASK       0x7
+#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
+#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_VALID_DIM_MASK_MASK  0x1F00
+#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_LAST_DIM_SHIFT       16
+#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_LAST_DIM_MASK        0x70000
+#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_SET_SHIFT        19
+#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_SET_MASK         0x80000
+#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_RESERV_SHIFT     20
+#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_RESERV_MASK      0x100000
+#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_OP_SHIFT         21
+#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_OP_MASK          0x600000
+
+/* TPC0_CFG_KERNEL_TENSOR_13_DIM_0_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_13_DIM_0_SIZE_V_SHIFT                 0
+#define TPC0_CFG_KERNEL_TENSOR_13_DIM_0_SIZE_V_MASK                  0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_13_DIM_1_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_13_DIM_1_SIZE_V_SHIFT                 0
+#define TPC0_CFG_KERNEL_TENSOR_13_DIM_1_SIZE_V_MASK                  0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_13_DIM_2_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_13_DIM_2_SIZE_V_SHIFT                 0
+#define TPC0_CFG_KERNEL_TENSOR_13_DIM_2_SIZE_V_MASK                  0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_13_DIM_3_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_13_DIM_3_SIZE_V_SHIFT                 0
+#define TPC0_CFG_KERNEL_TENSOR_13_DIM_3_SIZE_V_MASK                  0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_13_DIM_4_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_13_DIM_4_SIZE_V_SHIFT                 0
+#define TPC0_CFG_KERNEL_TENSOR_13_DIM_4_SIZE_V_MASK                  0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW */
+#define TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW_V_SHIFT              0
+#define TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW_V_MASK               0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH */
+#define TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH_V_SHIFT             0
+#define TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH_V_MASK              0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_14_PADDING_VALUE */
+#define TPC0_CFG_KERNEL_TENSOR_14_PADDING_VALUE_V_SHIFT              0
+#define TPC0_CFG_KERNEL_TENSOR_14_PADDING_VALUE_V_MASK               0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG */
+#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_DATA_TYPE_SHIFT      0
+#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_DATA_TYPE_MASK       0x7
+#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
+#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_VALID_DIM_MASK_MASK  0x1F00
+#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_LAST_DIM_SHIFT       16
+#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_LAST_DIM_MASK        0x70000
+#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_SET_SHIFT        19
+#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_SET_MASK         0x80000
+#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_RESERV_SHIFT     20
+#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_RESERV_MASK      0x100000
+#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_OP_SHIFT         21
+#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_OP_MASK          0x600000
+
+/* TPC0_CFG_KERNEL_TENSOR_14_DIM_0_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_14_DIM_0_SIZE_V_SHIFT                 0
+#define TPC0_CFG_KERNEL_TENSOR_14_DIM_0_SIZE_V_MASK                  0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_14_DIM_1_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_14_DIM_1_SIZE_V_SHIFT                 0
+#define TPC0_CFG_KERNEL_TENSOR_14_DIM_1_SIZE_V_MASK                  0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_14_DIM_2_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_14_DIM_2_SIZE_V_SHIFT                 0
+#define TPC0_CFG_KERNEL_TENSOR_14_DIM_2_SIZE_V_MASK                  0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_14_DIM_3_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_14_DIM_3_SIZE_V_SHIFT                 0
+#define TPC0_CFG_KERNEL_TENSOR_14_DIM_3_SIZE_V_MASK                  0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_14_DIM_4_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_14_DIM_4_SIZE_V_SHIFT                 0
+#define TPC0_CFG_KERNEL_TENSOR_14_DIM_4_SIZE_V_MASK                  0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW */
+#define TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW_V_SHIFT              0
+#define TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW_V_MASK               0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH */
+#define TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH_V_SHIFT             0
+#define TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH_V_MASK              0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_15_PADDING_VALUE */
+#define TPC0_CFG_KERNEL_TENSOR_15_PADDING_VALUE_V_SHIFT              0
+#define TPC0_CFG_KERNEL_TENSOR_15_PADDING_VALUE_V_MASK               0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG */
+#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_DATA_TYPE_SHIFT      0
+#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_DATA_TYPE_MASK       0x7
+#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
+#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_VALID_DIM_MASK_MASK  0x1F00
+#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_LAST_DIM_SHIFT       16
+#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_LAST_DIM_MASK        0x70000
+#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_SET_SHIFT        19
+#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_SET_MASK         0x80000
+#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_RESERV_SHIFT     20
+#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_RESERV_MASK      0x100000
+#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_OP_SHIFT         21
+#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_OP_MASK          0x600000
+
+/* TPC0_CFG_KERNEL_TENSOR_15_DIM_0_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_15_DIM_0_SIZE_V_SHIFT                 0
+#define TPC0_CFG_KERNEL_TENSOR_15_DIM_0_SIZE_V_MASK                  0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_15_DIM_1_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_15_DIM_1_SIZE_V_SHIFT                 0
+#define TPC0_CFG_KERNEL_TENSOR_15_DIM_1_SIZE_V_MASK                  0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_15_DIM_2_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_15_DIM_2_SIZE_V_SHIFT                 0
+#define TPC0_CFG_KERNEL_TENSOR_15_DIM_2_SIZE_V_MASK                  0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_15_DIM_3_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_15_DIM_3_SIZE_V_SHIFT                 0
+#define TPC0_CFG_KERNEL_TENSOR_15_DIM_3_SIZE_V_MASK                  0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_15_DIM_4_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_15_DIM_4_SIZE_V_SHIFT                 0
+#define TPC0_CFG_KERNEL_TENSOR_15_DIM_4_SIZE_V_MASK                  0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE_V_SHIFT               0
+#define TPC0_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE_V_MASK                0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE */
+#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT     0
+#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK      0xFFFF
+#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_RSV_SHIFT                16
+#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_RSV_MASK                 0x1FFF0000
+#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT       29
+#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK        0xE0000000
+
+/* TPC0_CFG_KERNEL_SYNC_OBJECT_ADDR */
+#define TPC0_CFG_KERNEL_SYNC_OBJECT_ADDR_V_SHIFT                     0
+#define TPC0_CFG_KERNEL_SYNC_OBJECT_ADDR_V_MASK                      0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW */
+#define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW_V_SHIFT              0
+#define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW_V_MASK               0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH */
+#define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH_V_SHIFT             0
+#define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH_V_MASK              0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TID_BASE_DIM_0 */
+#define TPC0_CFG_KERNEL_TID_BASE_DIM_0_V_SHIFT                       0
+#define TPC0_CFG_KERNEL_TID_BASE_DIM_0_V_MASK                        0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TID_SIZE_DIM_0 */
+#define TPC0_CFG_KERNEL_TID_SIZE_DIM_0_V_SHIFT                       0
+#define TPC0_CFG_KERNEL_TID_SIZE_DIM_0_V_MASK                        0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TID_BASE_DIM_1 */
+#define TPC0_CFG_KERNEL_TID_BASE_DIM_1_V_SHIFT                       0
+#define TPC0_CFG_KERNEL_TID_BASE_DIM_1_V_MASK                        0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TID_SIZE_DIM_1 */
+#define TPC0_CFG_KERNEL_TID_SIZE_DIM_1_V_SHIFT                       0
+#define TPC0_CFG_KERNEL_TID_SIZE_DIM_1_V_MASK                        0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TID_BASE_DIM_2 */
+#define TPC0_CFG_KERNEL_TID_BASE_DIM_2_V_SHIFT                       0
+#define TPC0_CFG_KERNEL_TID_BASE_DIM_2_V_MASK                        0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TID_SIZE_DIM_2 */
+#define TPC0_CFG_KERNEL_TID_SIZE_DIM_2_V_SHIFT                       0
+#define TPC0_CFG_KERNEL_TID_SIZE_DIM_2_V_MASK                        0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TID_BASE_DIM_3 */
+#define TPC0_CFG_KERNEL_TID_BASE_DIM_3_V_SHIFT                       0
+#define TPC0_CFG_KERNEL_TID_BASE_DIM_3_V_MASK                        0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TID_SIZE_DIM_3 */
+#define TPC0_CFG_KERNEL_TID_SIZE_DIM_3_V_SHIFT                       0
+#define TPC0_CFG_KERNEL_TID_SIZE_DIM_3_V_MASK                        0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TID_BASE_DIM_4 */
+#define TPC0_CFG_KERNEL_TID_BASE_DIM_4_V_SHIFT                       0
+#define TPC0_CFG_KERNEL_TID_BASE_DIM_4_V_MASK                        0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TID_SIZE_DIM_4 */
+#define TPC0_CFG_KERNEL_TID_SIZE_DIM_4_V_SHIFT                       0
+#define TPC0_CFG_KERNEL_TID_SIZE_DIM_4_V_MASK                        0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_KERNEL_CONFIG */
+#define TPC0_CFG_KERNEL_KERNEL_CONFIG_SMALL_VLM_SHIFT                0
+#define TPC0_CFG_KERNEL_KERNEL_CONFIG_SMALL_VLM_MASK                 0x1
+#define TPC0_CFG_KERNEL_KERNEL_CONFIG_ASO_EVICT_L0_SHIFT             1
+#define TPC0_CFG_KERNEL_KERNEL_CONFIG_ASO_EVICT_L0_MASK              0x2
+#define TPC0_CFG_KERNEL_KERNEL_CONFIG_NUM_VALID_SRFS_SHIFT           2
+#define TPC0_CFG_KERNEL_KERNEL_CONFIG_NUM_VALID_SRFS_MASK            0xFC
+#define TPC0_CFG_KERNEL_KERNEL_CONFIG_RD_RATE_LIMIT_RST_TOKEN_SHIFT  8
+#define TPC0_CFG_KERNEL_KERNEL_CONFIG_RD_RATE_LIMIT_RST_TOKEN_MASK   0xFF00
+#define TPC0_CFG_KERNEL_KERNEL_CONFIG_WR_RATE_LIMIT_RST_TOKEN_SHIFT  16
+#define TPC0_CFG_KERNEL_KERNEL_CONFIG_WR_RATE_LIMIT_RST_TOKEN_MASK   0xFF0000
+
+/* TPC0_CFG_KERNEL_KERNEL_ID */
+#define TPC0_CFG_KERNEL_KERNEL_ID_V_SHIFT                            0
+#define TPC0_CFG_KERNEL_KERNEL_ID_V_MASK                             0xFFFF
+
+/* TPC0_CFG_KERNEL_SRF */
+#define TPC0_CFG_KERNEL_SRF_V_SHIFT                                  0
+#define TPC0_CFG_KERNEL_SRF_V_MASK                                   0xFFFFFFFF
+
+/* TPC0_CFG_ROUND_CSR */
+#define TPC0_CFG_ROUND_CSR_MODE_SHIFT                                0
+#define TPC0_CFG_ROUND_CSR_MODE_MASK                                 0x7
+
+/* TPC0_CFG_PROT */
+#define TPC0_CFG_PROT_AWPROT_SHIFT                                   0
+#define TPC0_CFG_PROT_AWPROT_MASK                                    0x7
+#define TPC0_CFG_PROT_ARPROT_SHIFT                                   3
+#define TPC0_CFG_PROT_ARPROT_MASK                                    0x38
+
+/* TPC0_CFG_SEMAPHORE */
+#define TPC0_CFG_SEMAPHORE_V_SHIFT                                   0
+#define TPC0_CFG_SEMAPHORE_V_MASK                                    0xFFFFFFFF
+
+/* TPC0_CFG_VFLAGS */
+#define TPC0_CFG_VFLAGS_V_SHIFT                                      0
+#define TPC0_CFG_VFLAGS_V_MASK                                       0xF
+
+/* TPC0_CFG_SFLAGS */
+#define TPC0_CFG_SFLAGS_V_SHIFT                                      0
+#define TPC0_CFG_SFLAGS_V_MASK                                       0xF
+
+/* TPC0_CFG_LFSR_POLYNOM */
+#define TPC0_CFG_LFSR_POLYNOM_V_SHIFT                                0
+#define TPC0_CFG_LFSR_POLYNOM_V_MASK                                 0xFFFFFFFF
+
+/* TPC0_CFG_STATUS */
+#define TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_SHIFT                      1
+#define TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_MASK                       0x2
+#define TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_SHIFT                      2
+#define TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK                       0x4
+#define TPC0_CFG_STATUS_IQ_EMPTY_SHIFT                               3
+#define TPC0_CFG_STATUS_IQ_EMPTY_MASK                                0x8
+#define TPC0_CFG_STATUS_SB_EMPTY_SHIFT                               5
+#define TPC0_CFG_STATUS_SB_EMPTY_MASK                                0x20
+#define TPC0_CFG_STATUS_QM_IDLE_SHIFT                                6
+#define TPC0_CFG_STATUS_QM_IDLE_MASK                                 0x40
+#define TPC0_CFG_STATUS_QM_RDY_SHIFT                                 7
+#define TPC0_CFG_STATUS_QM_RDY_MASK                                  0x80
+
+/* TPC0_CFG_CFG_BASE_ADDRESS_HIGH */
+#define TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_SHIFT                       0
+#define TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_MASK                        0xFFFFFFFF
+
+/* TPC0_CFG_CFG_SUBTRACT_VALUE */
+#define TPC0_CFG_CFG_SUBTRACT_VALUE_V_SHIFT                          0
+#define TPC0_CFG_CFG_SUBTRACT_VALUE_V_MASK                           0xFFFFFFFF
+
+/* TPC0_CFG_SM_BASE_ADDRESS_HIGH */
+#define TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_SHIFT                        0
+#define TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_MASK                         0xFFFFFFFF
+
+/* TPC0_CFG_TPC_CMD */
+#define TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_SHIFT                     0
+#define TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_MASK                      0x1
+#define TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_SHIFT                     1
+#define TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_MASK                      0x2
+#define TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_SHIFT                     2
+#define TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_MASK                      0x4
+#define TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_SHIFT                     3
+#define TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_MASK                      0x8
+#define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_SHIFT                  4
+#define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_MASK                   0x10
+#define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_SHIFT                  5
+#define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_MASK                   0x20
+#define TPC0_CFG_TPC_CMD_QMAN_STOP_SHIFT                             6
+#define TPC0_CFG_TPC_CMD_QMAN_STOP_MASK                              0x40
+
+/* TPC0_CFG_TPC_EXECUTE */
+#define TPC0_CFG_TPC_EXECUTE_V_SHIFT                                 0
+#define TPC0_CFG_TPC_EXECUTE_V_MASK                                  0x1
+
+/* TPC0_CFG_TPC_STALL */
+#define TPC0_CFG_TPC_STALL_V_SHIFT                                   0
+#define TPC0_CFG_TPC_STALL_V_MASK                                    0x1
+
+/* TPC0_CFG_ICACHE_BASE_ADDERESS_LOW */
+#define TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_SHIFT                    0
+#define TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH */
+#define TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_SHIFT                   0
+#define TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_RD_RATE_LIMIT */
+#define TPC0_CFG_RD_RATE_LIMIT_ENABLE_SHIFT                          0
+#define TPC0_CFG_RD_RATE_LIMIT_ENABLE_MASK                           0x1
+#define TPC0_CFG_RD_RATE_LIMIT_SATURATION_SHIFT                      1
+#define TPC0_CFG_RD_RATE_LIMIT_SATURATION_MASK                       0x1FE
+#define TPC0_CFG_RD_RATE_LIMIT_TIMEOUT_SHIFT                         9
+#define TPC0_CFG_RD_RATE_LIMIT_TIMEOUT_MASK                          0x1FE00
+
+/* TPC0_CFG_WR_RATE_LIMIT */
+#define TPC0_CFG_WR_RATE_LIMIT_ENABLE_SHIFT                          0
+#define TPC0_CFG_WR_RATE_LIMIT_ENABLE_MASK                           0x1
+#define TPC0_CFG_WR_RATE_LIMIT_SATURATION_SHIFT                      1
+#define TPC0_CFG_WR_RATE_LIMIT_SATURATION_MASK                       0x1FE
+#define TPC0_CFG_WR_RATE_LIMIT_TIMEOUT_SHIFT                         9
+#define TPC0_CFG_WR_RATE_LIMIT_TIMEOUT_MASK                          0x1FE00
+
+/* TPC0_CFG_MSS_CONFIG */
+#define TPC0_CFG_MSS_CONFIG_AWCACHE_SHIFT                            0
+#define TPC0_CFG_MSS_CONFIG_AWCACHE_MASK                             0xF
+#define TPC0_CFG_MSS_CONFIG_ARCACHE_SHIFT                            4
+#define TPC0_CFG_MSS_CONFIG_ARCACHE_MASK                             0xF0
+#define TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_SHIFT              8
+#define TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_MASK               0x300
+#define TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_SHIFT                   10
+#define TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_MASK                    0x400
+#define TPC0_CFG_MSS_CONFIG_DCACHE_PREFETCH_DIS_SHIFT                11
+#define TPC0_CFG_MSS_CONFIG_DCACHE_PREFETCH_DIS_MASK                 0x800
+
+/* TPC0_CFG_TPC_INTR_CAUSE */
+#define TPC0_CFG_TPC_INTR_CAUSE_CAUSE_SHIFT                          0
+#define TPC0_CFG_TPC_INTR_CAUSE_CAUSE_MASK                           0xFFFFF
+
+/* TPC0_CFG_TPC_INTR_MASK */
+#define TPC0_CFG_TPC_INTR_MASK_MASK_SHIFT                            0
+#define TPC0_CFG_TPC_INTR_MASK_MASK_MASK                             0xFFFFF
+
+/* TPC0_CFG_WQ_CREDITS */
+#define TPC0_CFG_WQ_CREDITS_ST_G_SHIFT                               0
+#define TPC0_CFG_WQ_CREDITS_ST_G_MASK                                0xF
+#define TPC0_CFG_WQ_CREDITS_KERNEL_FIFO_SHIFT                        4
+#define TPC0_CFG_WQ_CREDITS_KERNEL_FIFO_MASK                         0x70
+
+/* TPC0_CFG_ARUSER_LO */
+#define TPC0_CFG_ARUSER_LO_V_SHIFT                                   0
+#define TPC0_CFG_ARUSER_LO_V_MASK                                    0x7FF
+
+/* TPC0_CFG_ARUSER_HI */
+#define TPC0_CFG_ARUSER_HI_V_SHIFT                                   11
+#define TPC0_CFG_ARUSER_HI_V_MASK                                    0x1800
+#define TPC0_CFG_ARUSER_HI_RSRV_SHIFT                                13
+#define TPC0_CFG_ARUSER_HI_RSRV_MASK                                 0xFFFFE000
+
+/* TPC0_CFG_AWUSER_LO */
+#define TPC0_CFG_AWUSER_LO_V_SHIFT                                   0
+#define TPC0_CFG_AWUSER_LO_V_MASK                                    0x7FF
+
+/* TPC0_CFG_AWUSER_HI */
+#define TPC0_CFG_AWUSER_HI_V_SHIFT                                   11
+#define TPC0_CFG_AWUSER_HI_V_MASK                                    0x1800
+#define TPC0_CFG_AWUSER_HI_RSRV_SHIFT                                13
+#define TPC0_CFG_AWUSER_HI_RSRV_MASK                                 0xFFFFE000
+
+/* TPC0_CFG_OPCODE_EXEC */
+#define TPC0_CFG_OPCODE_EXEC_SPU_OP_SHIFT                            0
+#define TPC0_CFG_OPCODE_EXEC_SPU_OP_MASK                             0x7F
+#define TPC0_CFG_OPCODE_EXEC_SPU_EN_SHIFT                            7
+#define TPC0_CFG_OPCODE_EXEC_SPU_EN_MASK                             0x80
+#define TPC0_CFG_OPCODE_EXEC_VPU_OP_SHIFT                            8
+#define TPC0_CFG_OPCODE_EXEC_VPU_OP_MASK                             0x7F00
+#define TPC0_CFG_OPCODE_EXEC_VPU_EN_SHIFT                            15
+#define TPC0_CFG_OPCODE_EXEC_VPU_EN_MASK                             0x8000
+#define TPC0_CFG_OPCODE_EXEC_LD_OP_SHIFT                             16
+#define TPC0_CFG_OPCODE_EXEC_LD_OP_MASK                              0x7F0000
+#define TPC0_CFG_OPCODE_EXEC_LD_EN_SHIFT                             23
+#define TPC0_CFG_OPCODE_EXEC_LD_EN_MASK                              0x800000
+#define TPC0_CFG_OPCODE_EXEC_ST_OP_SHIFT                             24
+#define TPC0_CFG_OPCODE_EXEC_ST_OP_MASK                              0x7F000000
+#define TPC0_CFG_OPCODE_EXEC_ST_EN_SHIFT                             31
+#define TPC0_CFG_OPCODE_EXEC_ST_EN_MASK                              0x80000000
+
+/* TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO */
+#define TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO_V_SHIFT                     0
+#define TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO_V_MASK                      0xFFFFFFFF
+
+/* TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI */
+#define TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI_V_SHIFT                     0
+#define TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI_V_MASK                      0xFFFFFFFF
+
+/* TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO */
+#define TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO_V_SHIFT                     0
+#define TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO_V_MASK                      0xFFFFFFFF
+
+/* TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI */
+#define TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI_V_SHIFT                     0
+#define TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI_V_MASK                      0xFFFFFFFF
+
+/* TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO */
+#define TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO_V_SHIFT                    0
+#define TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI */
+#define TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI_V_SHIFT                    0
+#define TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO */
+#define TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO_V_SHIFT                    0
+#define TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI */
+#define TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI_V_SHIFT                    0
+#define TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_TSB_CFG_MAX_SIZE */
+#define TPC0_CFG_TSB_CFG_MAX_SIZE_DATA_SHIFT                         0
+#define TPC0_CFG_TSB_CFG_MAX_SIZE_DATA_MASK                          0xFFFF
+#define TPC0_CFG_TSB_CFG_MAX_SIZE_MD_SHIFT                           16
+#define TPC0_CFG_TSB_CFG_MAX_SIZE_MD_MASK                            0xFFFF0000
+
+/* TPC0_CFG_TSB_CFG */
+#define TPC0_CFG_TSB_CFG_FORCE_MISS_SHIFT                            0
+#define TPC0_CFG_TSB_CFG_FORCE_MISS_MASK                             0x1
+#define TPC0_CFG_TSB_CFG_MAX_OS_SHIFT                                1
+#define TPC0_CFG_TSB_CFG_MAX_OS_MASK                                 0x1FFFE
+
+/* TPC0_CFG_DBGMEM_ADD */
+#define TPC0_CFG_DBGMEM_ADD_V_SHIFT                                  0
+#define TPC0_CFG_DBGMEM_ADD_V_MASK                                   0xFFFFFFFF
+
+/* TPC0_CFG_DBGMEM_DATA_WR */
+#define TPC0_CFG_DBGMEM_DATA_WR_V_SHIFT                              0
+#define TPC0_CFG_DBGMEM_DATA_WR_V_MASK                               0xFFFFFFFF
+
+/* TPC0_CFG_DBGMEM_DATA_RD */
+#define TPC0_CFG_DBGMEM_DATA_RD_V_SHIFT                              0
+#define TPC0_CFG_DBGMEM_DATA_RD_V_MASK                               0xFFFFFFFF
+
+/* TPC0_CFG_DBGMEM_CTRL */
+#define TPC0_CFG_DBGMEM_CTRL_WR_NRD_SHIFT                            0
+#define TPC0_CFG_DBGMEM_CTRL_WR_NRD_MASK                             0x1
+
+/* TPC0_CFG_DBGMEM_RC */
+#define TPC0_CFG_DBGMEM_RC_VALID_SHIFT                               0
+#define TPC0_CFG_DBGMEM_RC_VALID_MASK                                0x1
+
+/* TPC0_CFG_TSB_INFLIGHT_CNTR */
+#define TPC0_CFG_TSB_INFLIGHT_CNTR_V_SHIFT                           0
+#define TPC0_CFG_TSB_INFLIGHT_CNTR_V_MASK                            0xFFFFFFFF
+
+/* TPC0_CFG_WQ_INFLIGHT_CNTR */
+#define TPC0_CFG_WQ_INFLIGHT_CNTR_HBW_SHIFT                          0
+#define TPC0_CFG_WQ_INFLIGHT_CNTR_HBW_MASK                           0xFFFF
+#define TPC0_CFG_WQ_INFLIGHT_CNTR_LBW_SHIFT                          16
+#define TPC0_CFG_WQ_INFLIGHT_CNTR_LBW_MASK                           0xF0000
+
+/* TPC0_CFG_WQ_LBW_TOTAL_CNTR */
+#define TPC0_CFG_WQ_LBW_TOTAL_CNTR_V_SHIFT                           0
+#define TPC0_CFG_WQ_LBW_TOTAL_CNTR_V_MASK                            0xFFFFFFFF
+
+/* TPC0_CFG_WQ_HBW_TOTAL_CNTR */
+#define TPC0_CFG_WQ_HBW_TOTAL_CNTR_V_SHIFT                           0
+#define TPC0_CFG_WQ_HBW_TOTAL_CNTR_V_MASK                            0xFFFFFFFF
+
+/* TPC0_CFG_IRQ_OCCOUPY_CNTR */
+#define TPC0_CFG_IRQ_OCCOUPY_CNTR_V_SHIFT                            0
+#define TPC0_CFG_IRQ_OCCOUPY_CNTR_V_MASK                             0xFFFFFFFF
+
+/* TPC0_CFG_FUNC_MBIST_CNTRL */
+#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_SHIFT                  0
+#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_MASK                   0x1
+#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_SHIFT                   1
+#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_MASK                    0x2
+#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_SHIFT                 2
+#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_MASK                  0x4
+#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_FAILED_SHIFT                 16
+#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_FAILED_MASK                  0x3FF0000
+
+/* TPC0_CFG_FUNC_MBIST_PAT */
+#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_EVEN_SHIFT            0
+#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_EVEN_MASK             0x3
+#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_ODD_SHIFT             2
+#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_ODD_MASK              0xC
+#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_EVEN_SHIFT            4
+#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_EVEN_MASK             0x30
+#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_ODD_SHIFT             6
+#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_ODD_MASK              0xC0
+#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_EVEN_SHIFT            8
+#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_EVEN_MASK             0x300
+#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_ODD_SHIFT             10
+#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_ODD_MASK              0xC00
+
+/* TPC0_CFG_FUNC_MBIST_MEM */
+#define TPC0_CFG_FUNC_MBIST_MEM_MAX_ADDR_SHIFT                       0
+#define TPC0_CFG_FUNC_MBIST_MEM_MAX_ADDR_MASK                        0x7FF
+#define TPC0_CFG_FUNC_MBIST_MEM_PATTERN_EN_SHIFT                     12
+#define TPC0_CFG_FUNC_MBIST_MEM_PATTERN_EN_MASK                      0x7000
+#define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_ADDR_SHIFT               16
+#define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_ADDR_MASK                0x7FF0000
+#define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_PATTERN_SHIFT            28
+#define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_PATTERN_MASK             0x70000000
+
+/* TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW */
+#define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH */
+#define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT                  0
+#define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_0_PADDING_VALUE */
+#define TPC0_CFG_QM_TENSOR_0_PADDING_VALUE_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_0_PADDING_VALUE_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG */
+#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
+#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK            0x7
+#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
+#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
+#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_LAST_DIM_SHIFT            16
+#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
+#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_SET_SHIFT             19
+#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_SET_MASK              0x80000
+#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_RESERV_SHIFT          20
+#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_RESERV_MASK           0x100000
+#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_OP_SHIFT              21
+#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_OP_MASK               0x600000
+
+/* TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE */
+#define TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE */
+#define TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE */
+#define TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE */
+#define TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE */
+#define TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE */
+#define TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE */
+#define TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE */
+#define TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE */
+#define TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE */
+#define TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW */
+#define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH */
+#define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH_V_SHIFT                  0
+#define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_1_PADDING_VALUE */
+#define TPC0_CFG_QM_TENSOR_1_PADDING_VALUE_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_1_PADDING_VALUE_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG */
+#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
+#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_MASK            0x7
+#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
+#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
+#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_LAST_DIM_SHIFT            16
+#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
+#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_SET_SHIFT             19
+#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_SET_MASK              0x80000
+#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_RESERV_SHIFT          20
+#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_RESERV_MASK           0x100000
+#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_OP_SHIFT              21
+#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_OP_MASK               0x600000
+
+/* TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE */
+#define TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE */
+#define TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE */
+#define TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE */
+#define TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE */
+#define TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE */
+#define TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE */
+#define TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE */
+#define TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE */
+#define TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE */
+#define TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW */
+#define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH */
+#define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH_V_SHIFT                  0
+#define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_2_PADDING_VALUE */
+#define TPC0_CFG_QM_TENSOR_2_PADDING_VALUE_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_2_PADDING_VALUE_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG */
+#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
+#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_MASK            0x7
+#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
+#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
+#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_LAST_DIM_SHIFT            16
+#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
+#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_SET_SHIFT             19
+#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_SET_MASK              0x80000
+#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_RESERV_SHIFT          20
+#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_RESERV_MASK           0x100000
+#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_OP_SHIFT              21
+#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_OP_MASK               0x600000
+
+/* TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE */
+#define TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE */
+#define TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE */
+#define TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE */
+#define TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE */
+#define TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE */
+#define TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE */
+#define TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE */
+#define TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE */
+#define TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE */
+#define TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW */
+#define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH */
+#define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH_V_SHIFT                  0
+#define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_3_PADDING_VALUE */
+#define TPC0_CFG_QM_TENSOR_3_PADDING_VALUE_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_3_PADDING_VALUE_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG */
+#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
+#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_MASK            0x7
+#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
+#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
+#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_LAST_DIM_SHIFT            16
+#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
+#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_SET_SHIFT             19
+#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_SET_MASK              0x80000
+#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_RESERV_SHIFT          20
+#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_RESERV_MASK           0x100000
+#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_OP_SHIFT              21
+#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_OP_MASK               0x600000
+
+/* TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE */
+#define TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE */
+#define TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE */
+#define TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE */
+#define TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE */
+#define TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE */
+#define TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE */
+#define TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE */
+#define TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE */
+#define TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE */
+#define TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW */
+#define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH */
+#define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH_V_SHIFT                  0
+#define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_4_PADDING_VALUE */
+#define TPC0_CFG_QM_TENSOR_4_PADDING_VALUE_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_4_PADDING_VALUE_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG */
+#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
+#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_MASK            0x7
+#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
+#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
+#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_LAST_DIM_SHIFT            16
+#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
+#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_SET_SHIFT             19
+#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_SET_MASK              0x80000
+#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_RESERV_SHIFT          20
+#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_RESERV_MASK           0x100000
+#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_OP_SHIFT              21
+#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_OP_MASK               0x600000
+
+/* TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE */
+#define TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE */
+#define TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE */
+#define TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE */
+#define TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE */
+#define TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE */
+#define TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE */
+#define TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE */
+#define TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE */
+#define TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE */
+#define TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW */
+#define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH */
+#define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH_V_SHIFT                  0
+#define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_5_PADDING_VALUE */
+#define TPC0_CFG_QM_TENSOR_5_PADDING_VALUE_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_5_PADDING_VALUE_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG */
+#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
+#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_MASK            0x7
+#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
+#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
+#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_LAST_DIM_SHIFT            16
+#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
+#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_SET_SHIFT             19
+#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_SET_MASK              0x80000
+#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_RESERV_SHIFT          20
+#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_RESERV_MASK           0x100000
+#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_OP_SHIFT              21
+#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_OP_MASK               0x600000
+
+/* TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE */
+#define TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE */
+#define TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE */
+#define TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE */
+#define TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE */
+#define TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE */
+#define TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE */
+#define TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE */
+#define TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE */
+#define TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE */
+#define TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW */
+#define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH */
+#define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH_V_SHIFT                  0
+#define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_6_PADDING_VALUE */
+#define TPC0_CFG_QM_TENSOR_6_PADDING_VALUE_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_6_PADDING_VALUE_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG */
+#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
+#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_MASK            0x7
+#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
+#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
+#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_LAST_DIM_SHIFT            16
+#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
+#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_SET_SHIFT             19
+#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_SET_MASK              0x80000
+#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_RESERV_SHIFT          20
+#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_RESERV_MASK           0x100000
+#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_OP_SHIFT              21
+#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_OP_MASK               0x600000
+
+/* TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE */
+#define TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE */
+#define TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE */
+#define TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE */
+#define TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE */
+#define TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE */
+#define TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE */
+#define TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE */
+#define TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE */
+#define TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE */
+#define TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW */
+#define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH */
+#define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH_V_SHIFT                  0
+#define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_7_PADDING_VALUE */
+#define TPC0_CFG_QM_TENSOR_7_PADDING_VALUE_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_7_PADDING_VALUE_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG */
+#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
+#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_MASK            0x7
+#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
+#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
+#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_LAST_DIM_SHIFT            16
+#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
+#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_SET_SHIFT             19
+#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_SET_MASK              0x80000
+#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_RESERV_SHIFT          20
+#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_RESERV_MASK           0x100000
+#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_OP_SHIFT              21
+#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_OP_MASK               0x600000
+
+/* TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE */
+#define TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE */
+#define TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE */
+#define TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE */
+#define TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE */
+#define TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE */
+#define TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE */
+#define TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE */
+#define TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE */
+#define TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE */
+#define TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_8_BASE_ADDR_LOW */
+#define TPC0_CFG_QM_TENSOR_8_BASE_ADDR_LOW_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_8_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_8_BASE_ADDR_HIGH */
+#define TPC0_CFG_QM_TENSOR_8_BASE_ADDR_HIGH_V_SHIFT                  0
+#define TPC0_CFG_QM_TENSOR_8_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_8_PADDING_VALUE */
+#define TPC0_CFG_QM_TENSOR_8_PADDING_VALUE_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_8_PADDING_VALUE_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG */
+#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
+#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_DATA_TYPE_MASK            0x7
+#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
+#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
+#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_LAST_DIM_SHIFT            16
+#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
+#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_SET_SHIFT             19
+#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_SET_MASK              0x80000
+#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_RESERV_SHIFT          20
+#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_RESERV_MASK           0x100000
+#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_OP_SHIFT              21
+#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_OP_MASK               0x600000
+
+/* TPC0_CFG_QM_TENSOR_8_DIM_0_SIZE */
+#define TPC0_CFG_QM_TENSOR_8_DIM_0_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_8_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_8_DIM_0_STRIDE */
+#define TPC0_CFG_QM_TENSOR_8_DIM_0_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_8_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_8_DIM_1_SIZE */
+#define TPC0_CFG_QM_TENSOR_8_DIM_1_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_8_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_8_DIM_1_STRIDE */
+#define TPC0_CFG_QM_TENSOR_8_DIM_1_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_8_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_8_DIM_2_SIZE */
+#define TPC0_CFG_QM_TENSOR_8_DIM_2_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_8_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_8_DIM_2_STRIDE */
+#define TPC0_CFG_QM_TENSOR_8_DIM_2_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_8_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_8_DIM_3_SIZE */
+#define TPC0_CFG_QM_TENSOR_8_DIM_3_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_8_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_8_DIM_3_STRIDE */
+#define TPC0_CFG_QM_TENSOR_8_DIM_3_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_8_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_8_DIM_4_SIZE */
+#define TPC0_CFG_QM_TENSOR_8_DIM_4_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_8_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_8_DIM_4_STRIDE */
+#define TPC0_CFG_QM_TENSOR_8_DIM_4_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_8_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_9_BASE_ADDR_LOW */
+#define TPC0_CFG_QM_TENSOR_9_BASE_ADDR_LOW_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_9_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_9_BASE_ADDR_HIGH */
+#define TPC0_CFG_QM_TENSOR_9_BASE_ADDR_HIGH_V_SHIFT                  0
+#define TPC0_CFG_QM_TENSOR_9_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_9_PADDING_VALUE */
+#define TPC0_CFG_QM_TENSOR_9_PADDING_VALUE_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_9_PADDING_VALUE_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG */
+#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
+#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_DATA_TYPE_MASK            0x7
+#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
+#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
+#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_LAST_DIM_SHIFT            16
+#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
+#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_SET_SHIFT             19
+#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_SET_MASK              0x80000
+#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_RESERV_SHIFT          20
+#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_RESERV_MASK           0x100000
+#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_OP_SHIFT              21
+#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_OP_MASK               0x600000
+
+/* TPC0_CFG_QM_TENSOR_9_DIM_0_SIZE */
+#define TPC0_CFG_QM_TENSOR_9_DIM_0_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_9_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_9_DIM_0_STRIDE */
+#define TPC0_CFG_QM_TENSOR_9_DIM_0_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_9_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_9_DIM_1_SIZE */
+#define TPC0_CFG_QM_TENSOR_9_DIM_1_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_9_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_9_DIM_1_STRIDE */
+#define TPC0_CFG_QM_TENSOR_9_DIM_1_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_9_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_9_DIM_2_SIZE */
+#define TPC0_CFG_QM_TENSOR_9_DIM_2_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_9_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_9_DIM_2_STRIDE */
+#define TPC0_CFG_QM_TENSOR_9_DIM_2_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_9_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_9_DIM_3_SIZE */
+#define TPC0_CFG_QM_TENSOR_9_DIM_3_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_9_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_9_DIM_3_STRIDE */
+#define TPC0_CFG_QM_TENSOR_9_DIM_3_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_9_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_9_DIM_4_SIZE */
+#define TPC0_CFG_QM_TENSOR_9_DIM_4_SIZE_V_SHIFT                      0
+#define TPC0_CFG_QM_TENSOR_9_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_9_DIM_4_STRIDE */
+#define TPC0_CFG_QM_TENSOR_9_DIM_4_STRIDE_V_SHIFT                    0
+#define TPC0_CFG_QM_TENSOR_9_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_10_BASE_ADDR_LOW */
+#define TPC0_CFG_QM_TENSOR_10_BASE_ADDR_LOW_V_SHIFT                  0
+#define TPC0_CFG_QM_TENSOR_10_BASE_ADDR_LOW_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_10_BASE_ADDR_HIGH */
+#define TPC0_CFG_QM_TENSOR_10_BASE_ADDR_HIGH_V_SHIFT                 0
+#define TPC0_CFG_QM_TENSOR_10_BASE_ADDR_HIGH_V_MASK                  0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_10_PADDING_VALUE */
+#define TPC0_CFG_QM_TENSOR_10_PADDING_VALUE_V_SHIFT                  0
+#define TPC0_CFG_QM_TENSOR_10_PADDING_VALUE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG */
+#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_DATA_TYPE_SHIFT          0
+#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_DATA_TYPE_MASK           0x7
+#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT     8
+#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_VALID_DIM_MASK_MASK      0x1F00
+#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_LAST_DIM_SHIFT           16
+#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_LAST_DIM_MASK            0x70000
+#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_SET_SHIFT            19
+#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_SET_MASK             0x80000
+#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_RESERV_SHIFT         20
+#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_RESERV_MASK          0x100000
+#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_OP_SHIFT             21
+#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_OP_MASK              0x600000
+
+/* TPC0_CFG_QM_TENSOR_10_DIM_0_SIZE */
+#define TPC0_CFG_QM_TENSOR_10_DIM_0_SIZE_V_SHIFT                     0
+#define TPC0_CFG_QM_TENSOR_10_DIM_0_SIZE_V_MASK                      0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_10_DIM_0_STRIDE */
+#define TPC0_CFG_QM_TENSOR_10_DIM_0_STRIDE_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_10_DIM_0_STRIDE_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_10_DIM_1_SIZE */
+#define TPC0_CFG_QM_TENSOR_10_DIM_1_SIZE_V_SHIFT                     0
+#define TPC0_CFG_QM_TENSOR_10_DIM_1_SIZE_V_MASK                      0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_10_DIM_1_STRIDE */
+#define TPC0_CFG_QM_TENSOR_10_DIM_1_STRIDE_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_10_DIM_1_STRIDE_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_10_DIM_2_SIZE */
+#define TPC0_CFG_QM_TENSOR_10_DIM_2_SIZE_V_SHIFT                     0
+#define TPC0_CFG_QM_TENSOR_10_DIM_2_SIZE_V_MASK                      0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_10_DIM_2_STRIDE */
+#define TPC0_CFG_QM_TENSOR_10_DIM_2_STRIDE_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_10_DIM_2_STRIDE_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_10_DIM_3_SIZE */
+#define TPC0_CFG_QM_TENSOR_10_DIM_3_SIZE_V_SHIFT                     0
+#define TPC0_CFG_QM_TENSOR_10_DIM_3_SIZE_V_MASK                      0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_10_DIM_3_STRIDE */
+#define TPC0_CFG_QM_TENSOR_10_DIM_3_STRIDE_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_10_DIM_3_STRIDE_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_10_DIM_4_SIZE */
+#define TPC0_CFG_QM_TENSOR_10_DIM_4_SIZE_V_SHIFT                     0
+#define TPC0_CFG_QM_TENSOR_10_DIM_4_SIZE_V_MASK                      0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_10_DIM_4_STRIDE */
+#define TPC0_CFG_QM_TENSOR_10_DIM_4_STRIDE_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_10_DIM_4_STRIDE_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_11_BASE_ADDR_LOW */
+#define TPC0_CFG_QM_TENSOR_11_BASE_ADDR_LOW_V_SHIFT                  0
+#define TPC0_CFG_QM_TENSOR_11_BASE_ADDR_LOW_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_11_BASE_ADDR_HIGH */
+#define TPC0_CFG_QM_TENSOR_11_BASE_ADDR_HIGH_V_SHIFT                 0
+#define TPC0_CFG_QM_TENSOR_11_BASE_ADDR_HIGH_V_MASK                  0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_11_PADDING_VALUE */
+#define TPC0_CFG_QM_TENSOR_11_PADDING_VALUE_V_SHIFT                  0
+#define TPC0_CFG_QM_TENSOR_11_PADDING_VALUE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG */
+#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_DATA_TYPE_SHIFT          0
+#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_DATA_TYPE_MASK           0x7
+#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT     8
+#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_VALID_DIM_MASK_MASK      0x1F00
+#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_LAST_DIM_SHIFT           16
+#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_LAST_DIM_MASK            0x70000
+#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_SET_SHIFT            19
+#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_SET_MASK             0x80000
+#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_RESERV_SHIFT         20
+#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_RESERV_MASK          0x100000
+#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_OP_SHIFT             21
+#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_OP_MASK              0x600000
+
+/* TPC0_CFG_QM_TENSOR_11_DIM_0_SIZE */
+#define TPC0_CFG_QM_TENSOR_11_DIM_0_SIZE_V_SHIFT                     0
+#define TPC0_CFG_QM_TENSOR_11_DIM_0_SIZE_V_MASK                      0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_11_DIM_0_STRIDE */
+#define TPC0_CFG_QM_TENSOR_11_DIM_0_STRIDE_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_11_DIM_0_STRIDE_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_11_DIM_1_SIZE */
+#define TPC0_CFG_QM_TENSOR_11_DIM_1_SIZE_V_SHIFT                     0
+#define TPC0_CFG_QM_TENSOR_11_DIM_1_SIZE_V_MASK                      0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_11_DIM_1_STRIDE */
+#define TPC0_CFG_QM_TENSOR_11_DIM_1_STRIDE_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_11_DIM_1_STRIDE_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_11_DIM_2_SIZE */
+#define TPC0_CFG_QM_TENSOR_11_DIM_2_SIZE_V_SHIFT                     0
+#define TPC0_CFG_QM_TENSOR_11_DIM_2_SIZE_V_MASK                      0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_11_DIM_2_STRIDE */
+#define TPC0_CFG_QM_TENSOR_11_DIM_2_STRIDE_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_11_DIM_2_STRIDE_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_11_DIM_3_SIZE */
+#define TPC0_CFG_QM_TENSOR_11_DIM_3_SIZE_V_SHIFT                     0
+#define TPC0_CFG_QM_TENSOR_11_DIM_3_SIZE_V_MASK                      0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_11_DIM_3_STRIDE */
+#define TPC0_CFG_QM_TENSOR_11_DIM_3_STRIDE_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_11_DIM_3_STRIDE_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_11_DIM_4_SIZE */
+#define TPC0_CFG_QM_TENSOR_11_DIM_4_SIZE_V_SHIFT                     0
+#define TPC0_CFG_QM_TENSOR_11_DIM_4_SIZE_V_MASK                      0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_11_DIM_4_STRIDE */
+#define TPC0_CFG_QM_TENSOR_11_DIM_4_STRIDE_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_11_DIM_4_STRIDE_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_12_BASE_ADDR_LOW */
+#define TPC0_CFG_QM_TENSOR_12_BASE_ADDR_LOW_V_SHIFT                  0
+#define TPC0_CFG_QM_TENSOR_12_BASE_ADDR_LOW_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_12_BASE_ADDR_HIGH */
+#define TPC0_CFG_QM_TENSOR_12_BASE_ADDR_HIGH_V_SHIFT                 0
+#define TPC0_CFG_QM_TENSOR_12_BASE_ADDR_HIGH_V_MASK                  0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_12_PADDING_VALUE */
+#define TPC0_CFG_QM_TENSOR_12_PADDING_VALUE_V_SHIFT                  0
+#define TPC0_CFG_QM_TENSOR_12_PADDING_VALUE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG */
+#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_DATA_TYPE_SHIFT          0
+#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_DATA_TYPE_MASK           0x7
+#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT     8
+#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_VALID_DIM_MASK_MASK      0x1F00
+#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_LAST_DIM_SHIFT           16
+#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_LAST_DIM_MASK            0x70000
+#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_SET_SHIFT            19
+#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_SET_MASK             0x80000
+#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_RESERV_SHIFT         20
+#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_RESERV_MASK          0x100000
+#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_OP_SHIFT             21
+#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_OP_MASK              0x600000
+
+/* TPC0_CFG_QM_TENSOR_12_DIM_0_SIZE */
+#define TPC0_CFG_QM_TENSOR_12_DIM_0_SIZE_V_SHIFT                     0
+#define TPC0_CFG_QM_TENSOR_12_DIM_0_SIZE_V_MASK                      0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_12_DIM_0_STRIDE */
+#define TPC0_CFG_QM_TENSOR_12_DIM_0_STRIDE_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_12_DIM_0_STRIDE_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_12_DIM_1_SIZE */
+#define TPC0_CFG_QM_TENSOR_12_DIM_1_SIZE_V_SHIFT                     0
+#define TPC0_CFG_QM_TENSOR_12_DIM_1_SIZE_V_MASK                      0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_12_DIM_1_STRIDE */
+#define TPC0_CFG_QM_TENSOR_12_DIM_1_STRIDE_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_12_DIM_1_STRIDE_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_12_DIM_2_SIZE */
+#define TPC0_CFG_QM_TENSOR_12_DIM_2_SIZE_V_SHIFT                     0
+#define TPC0_CFG_QM_TENSOR_12_DIM_2_SIZE_V_MASK                      0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_12_DIM_2_STRIDE */
+#define TPC0_CFG_QM_TENSOR_12_DIM_2_STRIDE_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_12_DIM_2_STRIDE_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_12_DIM_3_SIZE */
+#define TPC0_CFG_QM_TENSOR_12_DIM_3_SIZE_V_SHIFT                     0
+#define TPC0_CFG_QM_TENSOR_12_DIM_3_SIZE_V_MASK                      0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_12_DIM_3_STRIDE */
+#define TPC0_CFG_QM_TENSOR_12_DIM_3_STRIDE_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_12_DIM_3_STRIDE_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_12_DIM_4_SIZE */
+#define TPC0_CFG_QM_TENSOR_12_DIM_4_SIZE_V_SHIFT                     0
+#define TPC0_CFG_QM_TENSOR_12_DIM_4_SIZE_V_MASK                      0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_12_DIM_4_STRIDE */
+#define TPC0_CFG_QM_TENSOR_12_DIM_4_STRIDE_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_12_DIM_4_STRIDE_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_13_BASE_ADDR_LOW */
+#define TPC0_CFG_QM_TENSOR_13_BASE_ADDR_LOW_V_SHIFT                  0
+#define TPC0_CFG_QM_TENSOR_13_BASE_ADDR_LOW_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_13_BASE_ADDR_HIGH */
+#define TPC0_CFG_QM_TENSOR_13_BASE_ADDR_HIGH_V_SHIFT                 0
+#define TPC0_CFG_QM_TENSOR_13_BASE_ADDR_HIGH_V_MASK                  0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_13_PADDING_VALUE */
+#define TPC0_CFG_QM_TENSOR_13_PADDING_VALUE_V_SHIFT                  0
+#define TPC0_CFG_QM_TENSOR_13_PADDING_VALUE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG */
+#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_DATA_TYPE_SHIFT          0
+#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_DATA_TYPE_MASK           0x7
+#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT     8
+#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_VALID_DIM_MASK_MASK      0x1F00
+#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_LAST_DIM_SHIFT           16
+#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_LAST_DIM_MASK            0x70000
+#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_SET_SHIFT            19
+#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_SET_MASK             0x80000
+#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_RESERV_SHIFT         20
+#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_RESERV_MASK          0x100000
+#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_OP_SHIFT             21
+#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_OP_MASK              0x600000
+
+/* TPC0_CFG_QM_TENSOR_13_DIM_0_SIZE */
+#define TPC0_CFG_QM_TENSOR_13_DIM_0_SIZE_V_SHIFT                     0
+#define TPC0_CFG_QM_TENSOR_13_DIM_0_SIZE_V_MASK                      0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_13_DIM_0_STRIDE */
+#define TPC0_CFG_QM_TENSOR_13_DIM_0_STRIDE_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_13_DIM_0_STRIDE_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_13_DIM_1_SIZE */
+#define TPC0_CFG_QM_TENSOR_13_DIM_1_SIZE_V_SHIFT                     0
+#define TPC0_CFG_QM_TENSOR_13_DIM_1_SIZE_V_MASK                      0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_13_DIM_1_STRIDE */
+#define TPC0_CFG_QM_TENSOR_13_DIM_1_STRIDE_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_13_DIM_1_STRIDE_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_13_DIM_2_SIZE */
+#define TPC0_CFG_QM_TENSOR_13_DIM_2_SIZE_V_SHIFT                     0
+#define TPC0_CFG_QM_TENSOR_13_DIM_2_SIZE_V_MASK                      0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_13_DIM_2_STRIDE */
+#define TPC0_CFG_QM_TENSOR_13_DIM_2_STRIDE_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_13_DIM_2_STRIDE_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_13_DIM_3_SIZE */
+#define TPC0_CFG_QM_TENSOR_13_DIM_3_SIZE_V_SHIFT                     0
+#define TPC0_CFG_QM_TENSOR_13_DIM_3_SIZE_V_MASK                      0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_13_DIM_3_STRIDE */
+#define TPC0_CFG_QM_TENSOR_13_DIM_3_STRIDE_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_13_DIM_3_STRIDE_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_13_DIM_4_SIZE */
+#define TPC0_CFG_QM_TENSOR_13_DIM_4_SIZE_V_SHIFT                     0
+#define TPC0_CFG_QM_TENSOR_13_DIM_4_SIZE_V_MASK                      0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_13_DIM_4_STRIDE */
+#define TPC0_CFG_QM_TENSOR_13_DIM_4_STRIDE_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_13_DIM_4_STRIDE_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_14_BASE_ADDR_LOW */
+#define TPC0_CFG_QM_TENSOR_14_BASE_ADDR_LOW_V_SHIFT                  0
+#define TPC0_CFG_QM_TENSOR_14_BASE_ADDR_LOW_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_14_BASE_ADDR_HIGH */
+#define TPC0_CFG_QM_TENSOR_14_BASE_ADDR_HIGH_V_SHIFT                 0
+#define TPC0_CFG_QM_TENSOR_14_BASE_ADDR_HIGH_V_MASK                  0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_14_PADDING_VALUE */
+#define TPC0_CFG_QM_TENSOR_14_PADDING_VALUE_V_SHIFT                  0
+#define TPC0_CFG_QM_TENSOR_14_PADDING_VALUE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG */
+#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_DATA_TYPE_SHIFT          0
+#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_DATA_TYPE_MASK           0x7
+#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT     8
+#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_VALID_DIM_MASK_MASK      0x1F00
+#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_LAST_DIM_SHIFT           16
+#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_LAST_DIM_MASK            0x70000
+#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_SET_SHIFT            19
+#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_SET_MASK             0x80000
+#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_RESERV_SHIFT         20
+#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_RESERV_MASK          0x100000
+#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_OP_SHIFT             21
+#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_OP_MASK              0x600000
+
+/* TPC0_CFG_QM_TENSOR_14_DIM_0_SIZE */
+#define TPC0_CFG_QM_TENSOR_14_DIM_0_SIZE_V_SHIFT                     0
+#define TPC0_CFG_QM_TENSOR_14_DIM_0_SIZE_V_MASK                      0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_14_DIM_0_STRIDE */
+#define TPC0_CFG_QM_TENSOR_14_DIM_0_STRIDE_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_14_DIM_0_STRIDE_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_14_DIM_1_SIZE */
+#define TPC0_CFG_QM_TENSOR_14_DIM_1_SIZE_V_SHIFT                     0
+#define TPC0_CFG_QM_TENSOR_14_DIM_1_SIZE_V_MASK                      0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_14_DIM_1_STRIDE */
+#define TPC0_CFG_QM_TENSOR_14_DIM_1_STRIDE_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_14_DIM_1_STRIDE_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_14_DIM_2_SIZE */
+#define TPC0_CFG_QM_TENSOR_14_DIM_2_SIZE_V_SHIFT                     0
+#define TPC0_CFG_QM_TENSOR_14_DIM_2_SIZE_V_MASK                      0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_14_DIM_2_STRIDE */
+#define TPC0_CFG_QM_TENSOR_14_DIM_2_STRIDE_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_14_DIM_2_STRIDE_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_14_DIM_3_SIZE */
+#define TPC0_CFG_QM_TENSOR_14_DIM_3_SIZE_V_SHIFT                     0
+#define TPC0_CFG_QM_TENSOR_14_DIM_3_SIZE_V_MASK                      0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_14_DIM_3_STRIDE */
+#define TPC0_CFG_QM_TENSOR_14_DIM_3_STRIDE_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_14_DIM_3_STRIDE_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_14_DIM_4_SIZE */
+#define TPC0_CFG_QM_TENSOR_14_DIM_4_SIZE_V_SHIFT                     0
+#define TPC0_CFG_QM_TENSOR_14_DIM_4_SIZE_V_MASK                      0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_14_DIM_4_STRIDE */
+#define TPC0_CFG_QM_TENSOR_14_DIM_4_STRIDE_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_14_DIM_4_STRIDE_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_15_BASE_ADDR_LOW */
+#define TPC0_CFG_QM_TENSOR_15_BASE_ADDR_LOW_V_SHIFT                  0
+#define TPC0_CFG_QM_TENSOR_15_BASE_ADDR_LOW_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_15_BASE_ADDR_HIGH */
+#define TPC0_CFG_QM_TENSOR_15_BASE_ADDR_HIGH_V_SHIFT                 0
+#define TPC0_CFG_QM_TENSOR_15_BASE_ADDR_HIGH_V_MASK                  0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_15_PADDING_VALUE */
+#define TPC0_CFG_QM_TENSOR_15_PADDING_VALUE_V_SHIFT                  0
+#define TPC0_CFG_QM_TENSOR_15_PADDING_VALUE_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG */
+#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_DATA_TYPE_SHIFT          0
+#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_DATA_TYPE_MASK           0x7
+#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT     8
+#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_VALID_DIM_MASK_MASK      0x1F00
+#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_LAST_DIM_SHIFT           16
+#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_LAST_DIM_MASK            0x70000
+#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_SET_SHIFT            19
+#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_SET_MASK             0x80000
+#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_RESERV_SHIFT         20
+#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_RESERV_MASK          0x100000
+#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_OP_SHIFT             21
+#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_OP_MASK              0x600000
+
+/* TPC0_CFG_QM_TENSOR_15_DIM_0_SIZE */
+#define TPC0_CFG_QM_TENSOR_15_DIM_0_SIZE_V_SHIFT                     0
+#define TPC0_CFG_QM_TENSOR_15_DIM_0_SIZE_V_MASK                      0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_15_DIM_0_STRIDE */
+#define TPC0_CFG_QM_TENSOR_15_DIM_0_STRIDE_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_15_DIM_0_STRIDE_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_15_DIM_1_SIZE */
+#define TPC0_CFG_QM_TENSOR_15_DIM_1_SIZE_V_SHIFT                     0
+#define TPC0_CFG_QM_TENSOR_15_DIM_1_SIZE_V_MASK                      0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_15_DIM_1_STRIDE */
+#define TPC0_CFG_QM_TENSOR_15_DIM_1_STRIDE_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_15_DIM_1_STRIDE_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_15_DIM_2_SIZE */
+#define TPC0_CFG_QM_TENSOR_15_DIM_2_SIZE_V_SHIFT                     0
+#define TPC0_CFG_QM_TENSOR_15_DIM_2_SIZE_V_MASK                      0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_15_DIM_2_STRIDE */
+#define TPC0_CFG_QM_TENSOR_15_DIM_2_STRIDE_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_15_DIM_2_STRIDE_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_15_DIM_3_SIZE */
+#define TPC0_CFG_QM_TENSOR_15_DIM_3_SIZE_V_SHIFT                     0
+#define TPC0_CFG_QM_TENSOR_15_DIM_3_SIZE_V_MASK                      0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_15_DIM_3_STRIDE */
+#define TPC0_CFG_QM_TENSOR_15_DIM_3_STRIDE_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_15_DIM_3_STRIDE_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_15_DIM_4_SIZE */
+#define TPC0_CFG_QM_TENSOR_15_DIM_4_SIZE_V_SHIFT                     0
+#define TPC0_CFG_QM_TENSOR_15_DIM_4_SIZE_V_MASK                      0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_15_DIM_4_STRIDE */
+#define TPC0_CFG_QM_TENSOR_15_DIM_4_STRIDE_V_SHIFT                   0
+#define TPC0_CFG_QM_TENSOR_15_DIM_4_STRIDE_V_MASK                    0xFFFFFFFF
+
+/* TPC0_CFG_QM_SYNC_OBJECT_MESSAGE */
+#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT         0
+#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK          0xFFFF
+#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_RSV_SHIFT                    16
+#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_RSV_MASK                     0x1FFF0000
+#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT           29
+#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK            0xE0000000
+
+/* TPC0_CFG_QM_SYNC_OBJECT_ADDR */
+#define TPC0_CFG_QM_SYNC_OBJECT_ADDR_V_SHIFT                         0
+#define TPC0_CFG_QM_SYNC_OBJECT_ADDR_V_MASK                          0xFFFFFFFF
+
+/* TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW */
+#define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW_V_SHIFT                  0
+#define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW_V_MASK                   0xFFFFFFFF
+
+/* TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH */
+#define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH_V_SHIFT                 0
+#define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH_V_MASK                  0xFFFFFFFF
+
+/* TPC0_CFG_QM_TID_BASE_DIM_0 */
+#define TPC0_CFG_QM_TID_BASE_DIM_0_V_SHIFT                           0
+#define TPC0_CFG_QM_TID_BASE_DIM_0_V_MASK                            0xFFFFFFFF
+
+/* TPC0_CFG_QM_TID_SIZE_DIM_0 */
+#define TPC0_CFG_QM_TID_SIZE_DIM_0_V_SHIFT                           0
+#define TPC0_CFG_QM_TID_SIZE_DIM_0_V_MASK                            0xFFFFFFFF
+
+/* TPC0_CFG_QM_TID_BASE_DIM_1 */
+#define TPC0_CFG_QM_TID_BASE_DIM_1_V_SHIFT                           0
+#define TPC0_CFG_QM_TID_BASE_DIM_1_V_MASK                            0xFFFFFFFF
+
+/* TPC0_CFG_QM_TID_SIZE_DIM_1 */
+#define TPC0_CFG_QM_TID_SIZE_DIM_1_V_SHIFT                           0
+#define TPC0_CFG_QM_TID_SIZE_DIM_1_V_MASK                            0xFFFFFFFF
+
+/* TPC0_CFG_QM_TID_BASE_DIM_2 */
+#define TPC0_CFG_QM_TID_BASE_DIM_2_V_SHIFT                           0
+#define TPC0_CFG_QM_TID_BASE_DIM_2_V_MASK                            0xFFFFFFFF
+
+/* TPC0_CFG_QM_TID_SIZE_DIM_2 */
+#define TPC0_CFG_QM_TID_SIZE_DIM_2_V_SHIFT                           0
+#define TPC0_CFG_QM_TID_SIZE_DIM_2_V_MASK                            0xFFFFFFFF
+
+/* TPC0_CFG_QM_TID_BASE_DIM_3 */
+#define TPC0_CFG_QM_TID_BASE_DIM_3_V_SHIFT                           0
+#define TPC0_CFG_QM_TID_BASE_DIM_3_V_MASK                            0xFFFFFFFF
+
+/* TPC0_CFG_QM_TID_SIZE_DIM_3 */
+#define TPC0_CFG_QM_TID_SIZE_DIM_3_V_SHIFT                           0
+#define TPC0_CFG_QM_TID_SIZE_DIM_3_V_MASK                            0xFFFFFFFF
+
+/* TPC0_CFG_QM_TID_BASE_DIM_4 */
+#define TPC0_CFG_QM_TID_BASE_DIM_4_V_SHIFT                           0
+#define TPC0_CFG_QM_TID_BASE_DIM_4_V_MASK                            0xFFFFFFFF
+
+/* TPC0_CFG_QM_TID_SIZE_DIM_4 */
+#define TPC0_CFG_QM_TID_SIZE_DIM_4_V_SHIFT                           0
+#define TPC0_CFG_QM_TID_SIZE_DIM_4_V_MASK                            0xFFFFFFFF
+
+/* TPC0_CFG_QM_KERNEL_CONFIG */
+#define TPC0_CFG_QM_KERNEL_CONFIG_SMALL_VLM_SHIFT                    0
+#define TPC0_CFG_QM_KERNEL_CONFIG_SMALL_VLM_MASK                     0x1
+#define TPC0_CFG_QM_KERNEL_CONFIG_ASO_EVICT_L0_SHIFT                 1
+#define TPC0_CFG_QM_KERNEL_CONFIG_ASO_EVICT_L0_MASK                  0x2
+#define TPC0_CFG_QM_KERNEL_CONFIG_NUM_VALID_SRFS_SHIFT               2
+#define TPC0_CFG_QM_KERNEL_CONFIG_NUM_VALID_SRFS_MASK                0xFC
+#define TPC0_CFG_QM_KERNEL_CONFIG_RD_RATE_LIMIT_RST_TOKEN_SHIFT      8
+#define TPC0_CFG_QM_KERNEL_CONFIG_RD_RATE_LIMIT_RST_TOKEN_MASK       0xFF00
+#define TPC0_CFG_QM_KERNEL_CONFIG_WR_RATE_LIMIT_RST_TOKEN_SHIFT      16
+#define TPC0_CFG_QM_KERNEL_CONFIG_WR_RATE_LIMIT_RST_TOKEN_MASK       0xFF0000
+
+/* TPC0_CFG_QM_KERNEL_ID */
+#define TPC0_CFG_QM_KERNEL_ID_V_SHIFT                                0
+#define TPC0_CFG_QM_KERNEL_ID_V_MASK                                 0xFFFF
+
+/* TPC0_CFG_QM_SRF */
+#define TPC0_CFG_QM_SRF_V_SHIFT                                      0
+#define TPC0_CFG_QM_SRF_V_MASK                                       0xFFFFFFFF
+
+#endif /* ASIC_REG_TPC0_CFG_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc0_cfg_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc0_cfg_regs.h
new file mode 100644
index 000000000000..b82a906265a8
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc0_cfg_regs.h
@@ -0,0 +1,1226 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_TPC0_CFG_REGS_H_
+#define ASIC_REG_TPC0_CFG_REGS_H_
+
+/*
+ *****************************************
+ *   TPC0_CFG (Prototype: TPC)
+ *****************************************
+ */
+
+#define mmTPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW                     0xE06400
+
+#define mmTPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH                    0xE06404
+
+#define mmTPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE                     0xE06408
+
+#define mmTPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG                     0xE0640C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE                        0xE06410
+
+#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE                      0xE06414
+
+#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE                        0xE06418
+
+#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE                      0xE0641C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE                        0xE06420
+
+#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE                      0xE06424
+
+#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE                        0xE06428
+
+#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE                      0xE0642C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE                        0xE06430
+
+#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE                      0xE06434
+
+#define mmTPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW                     0xE06438
+
+#define mmTPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH                    0xE0643C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE                     0xE06440
+
+#define mmTPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG                     0xE06444
+
+#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE                        0xE06448
+
+#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE                      0xE0644C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE                        0xE06450
+
+#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE                      0xE06454
+
+#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE                        0xE06458
+
+#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE                      0xE0645C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE                        0xE06460
+
+#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE                      0xE06464
+
+#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE                        0xE06468
+
+#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE                      0xE0646C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW                     0xE06470
+
+#define mmTPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH                    0xE06474
+
+#define mmTPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE                     0xE06478
+
+#define mmTPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG                     0xE0647C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE                        0xE06480
+
+#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE                      0xE06484
+
+#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE                        0xE06488
+
+#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE                      0xE0648C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE                        0xE06490
+
+#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE                      0xE06494
+
+#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE                        0xE06498
+
+#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE                      0xE0649C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE                        0xE064A0
+
+#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE                      0xE064A4
+
+#define mmTPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW                     0xE064A8
+
+#define mmTPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH                    0xE064AC
+
+#define mmTPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE                     0xE064B0
+
+#define mmTPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG                     0xE064B4
+
+#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE                        0xE064B8
+
+#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE                      0xE064BC
+
+#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE                        0xE064C0
+
+#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE                      0xE064C4
+
+#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE                        0xE064C8
+
+#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE                      0xE064CC
+
+#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE                        0xE064D0
+
+#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE                      0xE064D4
+
+#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE                        0xE064D8
+
+#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE                      0xE064DC
+
+#define mmTPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW                     0xE064E0
+
+#define mmTPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH                    0xE064E4
+
+#define mmTPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE                     0xE064E8
+
+#define mmTPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG                     0xE064EC
+
+#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE                        0xE064F0
+
+#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE                      0xE064F4
+
+#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE                        0xE064F8
+
+#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE                      0xE064FC
+
+#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE                        0xE06500
+
+#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE                      0xE06504
+
+#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE                        0xE06508
+
+#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE                      0xE0650C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE                        0xE06510
+
+#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE                      0xE06514
+
+#define mmTPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW                     0xE06518
+
+#define mmTPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH                    0xE0651C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE                     0xE06520
+
+#define mmTPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG                     0xE06524
+
+#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE                        0xE06528
+
+#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE                      0xE0652C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE                        0xE06530
+
+#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE                      0xE06534
+
+#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE                        0xE06538
+
+#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE                      0xE0653C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE                        0xE06540
+
+#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE                      0xE06544
+
+#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE                        0xE06548
+
+#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE                      0xE0654C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW                     0xE06550
+
+#define mmTPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH                    0xE06554
+
+#define mmTPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE                     0xE06558
+
+#define mmTPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG                     0xE0655C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE                        0xE06560
+
+#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE                      0xE06564
+
+#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE                        0xE06568
+
+#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE                      0xE0656C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE                        0xE06570
+
+#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE                      0xE06574
+
+#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE                        0xE06578
+
+#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE                      0xE0657C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE                        0xE06580
+
+#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE                      0xE06584
+
+#define mmTPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW                     0xE06588
+
+#define mmTPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH                    0xE0658C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE                     0xE06590
+
+#define mmTPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG                     0xE06594
+
+#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE                        0xE06598
+
+#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE                      0xE0659C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE                        0xE065A0
+
+#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE                      0xE065A4
+
+#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE                        0xE065A8
+
+#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE                      0xE065AC
+
+#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE                        0xE065B0
+
+#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE                      0xE065B4
+
+#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE                        0xE065B8
+
+#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE                      0xE065BC
+
+#define mmTPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW                     0xE065C0
+
+#define mmTPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH                    0xE065C4
+
+#define mmTPC0_CFG_KERNEL_TENSOR_8_PADDING_VALUE                     0xE065C8
+
+#define mmTPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG                     0xE065CC
+
+#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_0_SIZE                        0xE065D0
+
+#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE                      0xE065D4
+
+#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_1_SIZE                        0xE065D8
+
+#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE                      0xE065DC
+
+#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_2_SIZE                        0xE065E0
+
+#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE                      0xE065E4
+
+#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_3_SIZE                        0xE065E8
+
+#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE                      0xE065EC
+
+#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_4_SIZE                        0xE065F0
+
+#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE                      0xE065F4
+
+#define mmTPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW                     0xE065F8
+
+#define mmTPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH                    0xE065FC
+
+#define mmTPC0_CFG_KERNEL_TENSOR_9_PADDING_VALUE                     0xE06600
+
+#define mmTPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG                     0xE06604
+
+#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_0_SIZE                        0xE06608
+
+#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE                      0xE0660C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_1_SIZE                        0xE06610
+
+#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE                      0xE06614
+
+#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_2_SIZE                        0xE06618
+
+#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE                      0xE0661C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_3_SIZE                        0xE06620
+
+#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE                      0xE06624
+
+#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_4_SIZE                        0xE06628
+
+#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE                      0xE0662C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW                    0xE06630
+
+#define mmTPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH                   0xE06634
+
+#define mmTPC0_CFG_KERNEL_TENSOR_10_PADDING_VALUE                    0xE06638
+
+#define mmTPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG                    0xE0663C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_0_SIZE                       0xE06640
+
+#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE                     0xE06644
+
+#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_1_SIZE                       0xE06648
+
+#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE                     0xE0664C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_2_SIZE                       0xE06650
+
+#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE                     0xE06654
+
+#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_3_SIZE                       0xE06658
+
+#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE                     0xE0665C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_4_SIZE                       0xE06660
+
+#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE                     0xE06664
+
+#define mmTPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW                    0xE06668
+
+#define mmTPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH                   0xE0666C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_11_PADDING_VALUE                    0xE06670
+
+#define mmTPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG                    0xE06674
+
+#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_0_SIZE                       0xE06678
+
+#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE                     0xE0667C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_1_SIZE                       0xE06680
+
+#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE                     0xE06684
+
+#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_2_SIZE                       0xE06688
+
+#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE                     0xE0668C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_3_SIZE                       0xE06690
+
+#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE                     0xE06694
+
+#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_4_SIZE                       0xE06698
+
+#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE                     0xE0669C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW                    0xE066A0
+
+#define mmTPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH                   0xE066A4
+
+#define mmTPC0_CFG_KERNEL_TENSOR_12_PADDING_VALUE                    0xE066A8
+
+#define mmTPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG                    0xE066AC
+
+#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_0_SIZE                       0xE066B0
+
+#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE                     0xE066B4
+
+#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_1_SIZE                       0xE066B8
+
+#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE                     0xE066BC
+
+#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_2_SIZE                       0xE066C0
+
+#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE                     0xE066C4
+
+#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_3_SIZE                       0xE066C8
+
+#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE                     0xE066CC
+
+#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_4_SIZE                       0xE066D0
+
+#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE                     0xE066D4
+
+#define mmTPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW                    0xE066D8
+
+#define mmTPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH                   0xE066DC
+
+#define mmTPC0_CFG_KERNEL_TENSOR_13_PADDING_VALUE                    0xE066E0
+
+#define mmTPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG                    0xE066E4
+
+#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_0_SIZE                       0xE066E8
+
+#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE                     0xE066EC
+
+#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_1_SIZE                       0xE066F0
+
+#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE                     0xE066F4
+
+#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_2_SIZE                       0xE066F8
+
+#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE                     0xE066FC
+
+#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_3_SIZE                       0xE06700
+
+#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE                     0xE06704
+
+#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_4_SIZE                       0xE06708
+
+#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE                     0xE0670C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW                    0xE06710
+
+#define mmTPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH                   0xE06714
+
+#define mmTPC0_CFG_KERNEL_TENSOR_14_PADDING_VALUE                    0xE06718
+
+#define mmTPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG                    0xE0671C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_0_SIZE                       0xE06720
+
+#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE                     0xE06724
+
+#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_1_SIZE                       0xE06728
+
+#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE                     0xE0672C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_2_SIZE                       0xE06730
+
+#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE                     0xE06734
+
+#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_3_SIZE                       0xE06738
+
+#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE                     0xE0673C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_4_SIZE                       0xE06740
+
+#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE                     0xE06744
+
+#define mmTPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW                    0xE06748
+
+#define mmTPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH                   0xE0674C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_15_PADDING_VALUE                    0xE06750
+
+#define mmTPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG                    0xE06754
+
+#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_0_SIZE                       0xE06758
+
+#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE                     0xE0675C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_1_SIZE                       0xE06760
+
+#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE                     0xE06764
+
+#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_2_SIZE                       0xE06768
+
+#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE                     0xE0676C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_3_SIZE                       0xE06770
+
+#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE                     0xE06774
+
+#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_4_SIZE                       0xE06778
+
+#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE                     0xE0677C
+
+#define mmTPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE                        0xE06780
+
+#define mmTPC0_CFG_KERNEL_SYNC_OBJECT_ADDR                           0xE06784
+
+#define mmTPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW                    0xE06788
+
+#define mmTPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH                   0xE0678C
+
+#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_0                             0xE06790
+
+#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_0                             0xE06794
+
+#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_1                             0xE06798
+
+#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_1                             0xE0679C
+
+#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_2                             0xE067A0
+
+#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_2                             0xE067A4
+
+#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_3                             0xE067A8
+
+#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_3                             0xE067AC
+
+#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_4                             0xE067B0
+
+#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_4                             0xE067B4
+
+#define mmTPC0_CFG_KERNEL_KERNEL_CONFIG                              0xE067B8
+
+#define mmTPC0_CFG_KERNEL_KERNEL_ID                                  0xE067BC
+
+#define mmTPC0_CFG_KERNEL_SRF_0                                      0xE067C0
+
+#define mmTPC0_CFG_KERNEL_SRF_1                                      0xE067C4
+
+#define mmTPC0_CFG_KERNEL_SRF_2                                      0xE067C8
+
+#define mmTPC0_CFG_KERNEL_SRF_3                                      0xE067CC
+
+#define mmTPC0_CFG_KERNEL_SRF_4                                      0xE067D0
+
+#define mmTPC0_CFG_KERNEL_SRF_5                                      0xE067D4
+
+#define mmTPC0_CFG_KERNEL_SRF_6                                      0xE067D8
+
+#define mmTPC0_CFG_KERNEL_SRF_7                                      0xE067DC
+
+#define mmTPC0_CFG_KERNEL_SRF_8                                      0xE067E0
+
+#define mmTPC0_CFG_KERNEL_SRF_9                                      0xE067E4
+
+#define mmTPC0_CFG_KERNEL_SRF_10                                     0xE067E8
+
+#define mmTPC0_CFG_KERNEL_SRF_11                                     0xE067EC
+
+#define mmTPC0_CFG_KERNEL_SRF_12                                     0xE067F0
+
+#define mmTPC0_CFG_KERNEL_SRF_13                                     0xE067F4
+
+#define mmTPC0_CFG_KERNEL_SRF_14                                     0xE067F8
+
+#define mmTPC0_CFG_KERNEL_SRF_15                                     0xE067FC
+
+#define mmTPC0_CFG_KERNEL_SRF_16                                     0xE06800
+
+#define mmTPC0_CFG_KERNEL_SRF_17                                     0xE06804
+
+#define mmTPC0_CFG_KERNEL_SRF_18                                     0xE06808
+
+#define mmTPC0_CFG_KERNEL_SRF_19                                     0xE0680C
+
+#define mmTPC0_CFG_KERNEL_SRF_20                                     0xE06810
+
+#define mmTPC0_CFG_KERNEL_SRF_21                                     0xE06814
+
+#define mmTPC0_CFG_KERNEL_SRF_22                                     0xE06818
+
+#define mmTPC0_CFG_KERNEL_SRF_23                                     0xE0681C
+
+#define mmTPC0_CFG_KERNEL_SRF_24                                     0xE06820
+
+#define mmTPC0_CFG_KERNEL_SRF_25                                     0xE06824
+
+#define mmTPC0_CFG_KERNEL_SRF_26                                     0xE06828
+
+#define mmTPC0_CFG_KERNEL_SRF_27                                     0xE0682C
+
+#define mmTPC0_CFG_KERNEL_SRF_28                                     0xE06830
+
+#define mmTPC0_CFG_KERNEL_SRF_29                                     0xE06834
+
+#define mmTPC0_CFG_KERNEL_SRF_30                                     0xE06838
+
+#define mmTPC0_CFG_KERNEL_SRF_31                                     0xE0683C
+
+#define mmTPC0_CFG_ROUND_CSR                                         0xE068FC
+
+#define mmTPC0_CFG_PROT                                              0xE06900
+
+#define mmTPC0_CFG_SEMAPHORE                                         0xE06908
+
+#define mmTPC0_CFG_VFLAGS                                            0xE0690C
+
+#define mmTPC0_CFG_SFLAGS                                            0xE06910
+
+#define mmTPC0_CFG_LFSR_POLYNOM                                      0xE06918
+
+#define mmTPC0_CFG_STATUS                                            0xE0691C
+
+#define mmTPC0_CFG_CFG_BASE_ADDRESS_HIGH                             0xE06920
+
+#define mmTPC0_CFG_CFG_SUBTRACT_VALUE                                0xE06924
+
+#define mmTPC0_CFG_SM_BASE_ADDRESS_HIGH                              0xE0692C
+
+#define mmTPC0_CFG_TPC_CMD                                           0xE06930
+
+#define mmTPC0_CFG_TPC_EXECUTE                                       0xE06938
+
+#define mmTPC0_CFG_TPC_STALL                                         0xE0693C
+
+#define mmTPC0_CFG_ICACHE_BASE_ADDERESS_LOW                          0xE06940
+
+#define mmTPC0_CFG_ICACHE_BASE_ADDERESS_HIGH                         0xE06944
+
+#define mmTPC0_CFG_RD_RATE_LIMIT                                     0xE06948
+
+#define mmTPC0_CFG_WR_RATE_LIMIT                                     0xE06950
+
+#define mmTPC0_CFG_MSS_CONFIG                                        0xE06954
+
+#define mmTPC0_CFG_TPC_INTR_CAUSE                                    0xE06958
+
+#define mmTPC0_CFG_TPC_INTR_MASK                                     0xE0695C
+
+#define mmTPC0_CFG_WQ_CREDITS                                        0xE06960
+
+#define mmTPC0_CFG_ARUSER_LO                                         0xE06964
+
+#define mmTPC0_CFG_ARUSER_HI                                         0xE06968
+
+#define mmTPC0_CFG_AWUSER_LO                                         0xE0696C
+
+#define mmTPC0_CFG_AWUSER_HI                                         0xE06970
+
+#define mmTPC0_CFG_OPCODE_EXEC                                       0xE06974
+
+#define mmTPC0_CFG_LUT_FUNC32_BASE_ADDR_LO                           0xE06978
+
+#define mmTPC0_CFG_LUT_FUNC32_BASE_ADDR_HI                           0xE0697C
+
+#define mmTPC0_CFG_LUT_FUNC64_BASE_ADDR_LO                           0xE06980
+
+#define mmTPC0_CFG_LUT_FUNC64_BASE_ADDR_HI                           0xE06984
+
+#define mmTPC0_CFG_LUT_FUNC128_BASE_ADDR_LO                          0xE06988
+
+#define mmTPC0_CFG_LUT_FUNC128_BASE_ADDR_HI                          0xE0698C
+
+#define mmTPC0_CFG_LUT_FUNC256_BASE_ADDR_LO                          0xE06990
+
+#define mmTPC0_CFG_LUT_FUNC256_BASE_ADDR_HI                          0xE06994
+
+#define mmTPC0_CFG_TSB_CFG_MAX_SIZE                                  0xE06998
+
+#define mmTPC0_CFG_TSB_CFG                                           0xE0699C
+
+#define mmTPC0_CFG_DBGMEM_ADD                                        0xE069A0
+
+#define mmTPC0_CFG_DBGMEM_DATA_WR                                    0xE069A4
+
+#define mmTPC0_CFG_DBGMEM_DATA_RD                                    0xE069A8
+
+#define mmTPC0_CFG_DBGMEM_CTRL                                       0xE069AC
+
+#define mmTPC0_CFG_DBGMEM_RC                                         0xE069B0
+
+#define mmTPC0_CFG_TSB_INFLIGHT_CNTR                                 0xE069B4
+
+#define mmTPC0_CFG_WQ_INFLIGHT_CNTR                                  0xE069B8
+
+#define mmTPC0_CFG_WQ_LBW_TOTAL_CNTR                                 0xE069BC
+
+#define mmTPC0_CFG_WQ_HBW_TOTAL_CNTR                                 0xE069C0
+
+#define mmTPC0_CFG_IRQ_OCCOUPY_CNTR                                  0xE069C4
+
+#define mmTPC0_CFG_FUNC_MBIST_CNTRL                                  0xE069D0
+
+#define mmTPC0_CFG_FUNC_MBIST_PAT                                    0xE069D4
+
+#define mmTPC0_CFG_FUNC_MBIST_MEM_0                                  0xE069D8
+
+#define mmTPC0_CFG_FUNC_MBIST_MEM_1                                  0xE069DC
+
+#define mmTPC0_CFG_FUNC_MBIST_MEM_2                                  0xE069E0
+
+#define mmTPC0_CFG_FUNC_MBIST_MEM_3                                  0xE069E4
+
+#define mmTPC0_CFG_FUNC_MBIST_MEM_4                                  0xE069E8
+
+#define mmTPC0_CFG_FUNC_MBIST_MEM_5                                  0xE069EC
+
+#define mmTPC0_CFG_FUNC_MBIST_MEM_6                                  0xE069F0
+
+#define mmTPC0_CFG_FUNC_MBIST_MEM_7                                  0xE069F4
+
+#define mmTPC0_CFG_FUNC_MBIST_MEM_8                                  0xE069F8
+
+#define mmTPC0_CFG_FUNC_MBIST_MEM_9                                  0xE069FC
+
+#define mmTPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW                         0xE06A00
+
+#define mmTPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH                        0xE06A04
+
+#define mmTPC0_CFG_QM_TENSOR_0_PADDING_VALUE                         0xE06A08
+
+#define mmTPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG                         0xE06A0C
+
+#define mmTPC0_CFG_QM_TENSOR_0_DIM_0_SIZE                            0xE06A10
+
+#define mmTPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE                          0xE06A14
+
+#define mmTPC0_CFG_QM_TENSOR_0_DIM_1_SIZE                            0xE06A18
+
+#define mmTPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE                          0xE06A1C
+
+#define mmTPC0_CFG_QM_TENSOR_0_DIM_2_SIZE                            0xE06A20
+
+#define mmTPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE                          0xE06A24
+
+#define mmTPC0_CFG_QM_TENSOR_0_DIM_3_SIZE                            0xE06A28
+
+#define mmTPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE                          0xE06A2C
+
+#define mmTPC0_CFG_QM_TENSOR_0_DIM_4_SIZE                            0xE06A30
+
+#define mmTPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE                          0xE06A34
+
+#define mmTPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW                         0xE06A38
+
+#define mmTPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH                        0xE06A3C
+
+#define mmTPC0_CFG_QM_TENSOR_1_PADDING_VALUE                         0xE06A40
+
+#define mmTPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG                         0xE06A44
+
+#define mmTPC0_CFG_QM_TENSOR_1_DIM_0_SIZE                            0xE06A48
+
+#define mmTPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE                          0xE06A4C
+
+#define mmTPC0_CFG_QM_TENSOR_1_DIM_1_SIZE                            0xE06A50
+
+#define mmTPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE                          0xE06A54
+
+#define mmTPC0_CFG_QM_TENSOR_1_DIM_2_SIZE                            0xE06A58
+
+#define mmTPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE                          0xE06A5C
+
+#define mmTPC0_CFG_QM_TENSOR_1_DIM_3_SIZE                            0xE06A60
+
+#define mmTPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE                          0xE06A64
+
+#define mmTPC0_CFG_QM_TENSOR_1_DIM_4_SIZE                            0xE06A68
+
+#define mmTPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE                          0xE06A6C
+
+#define mmTPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW                         0xE06A70
+
+#define mmTPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH                        0xE06A74
+
+#define mmTPC0_CFG_QM_TENSOR_2_PADDING_VALUE                         0xE06A78
+
+#define mmTPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG                         0xE06A7C
+
+#define mmTPC0_CFG_QM_TENSOR_2_DIM_0_SIZE                            0xE06A80
+
+#define mmTPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE                          0xE06A84
+
+#define mmTPC0_CFG_QM_TENSOR_2_DIM_1_SIZE                            0xE06A88
+
+#define mmTPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE                          0xE06A8C
+
+#define mmTPC0_CFG_QM_TENSOR_2_DIM_2_SIZE                            0xE06A90
+
+#define mmTPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE                          0xE06A94
+
+#define mmTPC0_CFG_QM_TENSOR_2_DIM_3_SIZE                            0xE06A98
+
+#define mmTPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE                          0xE06A9C
+
+#define mmTPC0_CFG_QM_TENSOR_2_DIM_4_SIZE                            0xE06AA0
+
+#define mmTPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE                          0xE06AA4
+
+#define mmTPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW                         0xE06AA8
+
+#define mmTPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH                        0xE06AAC
+
+#define mmTPC0_CFG_QM_TENSOR_3_PADDING_VALUE                         0xE06AB0
+
+#define mmTPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG                         0xE06AB4
+
+#define mmTPC0_CFG_QM_TENSOR_3_DIM_0_SIZE                            0xE06AB8
+
+#define mmTPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE                          0xE06ABC
+
+#define mmTPC0_CFG_QM_TENSOR_3_DIM_1_SIZE                            0xE06AC0
+
+#define mmTPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE                          0xE06AC4
+
+#define mmTPC0_CFG_QM_TENSOR_3_DIM_2_SIZE                            0xE06AC8
+
+#define mmTPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE                          0xE06ACC
+
+#define mmTPC0_CFG_QM_TENSOR_3_DIM_3_SIZE                            0xE06AD0
+
+#define mmTPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE                          0xE06AD4
+
+#define mmTPC0_CFG_QM_TENSOR_3_DIM_4_SIZE                            0xE06AD8
+
+#define mmTPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE                          0xE06ADC
+
+#define mmTPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW                         0xE06AE0
+
+#define mmTPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH                        0xE06AE4
+
+#define mmTPC0_CFG_QM_TENSOR_4_PADDING_VALUE                         0xE06AE8
+
+#define mmTPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG                         0xE06AEC
+
+#define mmTPC0_CFG_QM_TENSOR_4_DIM_0_SIZE                            0xE06AF0
+
+#define mmTPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE                          0xE06AF4
+
+#define mmTPC0_CFG_QM_TENSOR_4_DIM_1_SIZE                            0xE06AF8
+
+#define mmTPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE                          0xE06AFC
+
+#define mmTPC0_CFG_QM_TENSOR_4_DIM_2_SIZE                            0xE06B00
+
+#define mmTPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE                          0xE06B04
+
+#define mmTPC0_CFG_QM_TENSOR_4_DIM_3_SIZE                            0xE06B08
+
+#define mmTPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE                          0xE06B0C
+
+#define mmTPC0_CFG_QM_TENSOR_4_DIM_4_SIZE                            0xE06B10
+
+#define mmTPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE                          0xE06B14
+
+#define mmTPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW                         0xE06B18
+
+#define mmTPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH                        0xE06B1C
+
+#define mmTPC0_CFG_QM_TENSOR_5_PADDING_VALUE                         0xE06B20
+
+#define mmTPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG                         0xE06B24
+
+#define mmTPC0_CFG_QM_TENSOR_5_DIM_0_SIZE                            0xE06B28
+
+#define mmTPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE                          0xE06B2C
+
+#define mmTPC0_CFG_QM_TENSOR_5_DIM_1_SIZE                            0xE06B30
+
+#define mmTPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE                          0xE06B34
+
+#define mmTPC0_CFG_QM_TENSOR_5_DIM_2_SIZE                            0xE06B38
+
+#define mmTPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE                          0xE06B3C
+
+#define mmTPC0_CFG_QM_TENSOR_5_DIM_3_SIZE                            0xE06B40
+
+#define mmTPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE                          0xE06B44
+
+#define mmTPC0_CFG_QM_TENSOR_5_DIM_4_SIZE                            0xE06B48
+
+#define mmTPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE                          0xE06B4C
+
+#define mmTPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW                         0xE06B50
+
+#define mmTPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH                        0xE06B54
+
+#define mmTPC0_CFG_QM_TENSOR_6_PADDING_VALUE                         0xE06B58
+
+#define mmTPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG                         0xE06B5C
+
+#define mmTPC0_CFG_QM_TENSOR_6_DIM_0_SIZE                            0xE06B60
+
+#define mmTPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE                          0xE06B64
+
+#define mmTPC0_CFG_QM_TENSOR_6_DIM_1_SIZE                            0xE06B68
+
+#define mmTPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE                          0xE06B6C
+
+#define mmTPC0_CFG_QM_TENSOR_6_DIM_2_SIZE                            0xE06B70
+
+#define mmTPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE                          0xE06B74
+
+#define mmTPC0_CFG_QM_TENSOR_6_DIM_3_SIZE                            0xE06B78
+
+#define mmTPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE                          0xE06B7C
+
+#define mmTPC0_CFG_QM_TENSOR_6_DIM_4_SIZE                            0xE06B80
+
+#define mmTPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE                          0xE06B84
+
+#define mmTPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW                         0xE06B88
+
+#define mmTPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH                        0xE06B8C
+
+#define mmTPC0_CFG_QM_TENSOR_7_PADDING_VALUE                         0xE06B90
+
+#define mmTPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG                         0xE06B94
+
+#define mmTPC0_CFG_QM_TENSOR_7_DIM_0_SIZE                            0xE06B98
+
+#define mmTPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE                          0xE06B9C
+
+#define mmTPC0_CFG_QM_TENSOR_7_DIM_1_SIZE                            0xE06BA0
+
+#define mmTPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE                          0xE06BA4
+
+#define mmTPC0_CFG_QM_TENSOR_7_DIM_2_SIZE                            0xE06BA8
+
+#define mmTPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE                          0xE06BAC
+
+#define mmTPC0_CFG_QM_TENSOR_7_DIM_3_SIZE                            0xE06BB0
+
+#define mmTPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE                          0xE06BB4
+
+#define mmTPC0_CFG_QM_TENSOR_7_DIM_4_SIZE                            0xE06BB8
+
+#define mmTPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE                          0xE06BBC
+
+#define mmTPC0_CFG_QM_TENSOR_8_BASE_ADDR_LOW                         0xE06BC0
+
+#define mmTPC0_CFG_QM_TENSOR_8_BASE_ADDR_HIGH                        0xE06BC4
+
+#define mmTPC0_CFG_QM_TENSOR_8_PADDING_VALUE                         0xE06BC8
+
+#define mmTPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG                         0xE06BCC
+
+#define mmTPC0_CFG_QM_TENSOR_8_DIM_0_SIZE                            0xE06BD0
+
+#define mmTPC0_CFG_QM_TENSOR_8_DIM_0_STRIDE                          0xE06BD4
+
+#define mmTPC0_CFG_QM_TENSOR_8_DIM_1_SIZE                            0xE06BD8
+
+#define mmTPC0_CFG_QM_TENSOR_8_DIM_1_STRIDE                          0xE06BDC
+
+#define mmTPC0_CFG_QM_TENSOR_8_DIM_2_SIZE                            0xE06BE0
+
+#define mmTPC0_CFG_QM_TENSOR_8_DIM_2_STRIDE                          0xE06BE4
+
+#define mmTPC0_CFG_QM_TENSOR_8_DIM_3_SIZE                            0xE06BE8
+
+#define mmTPC0_CFG_QM_TENSOR_8_DIM_3_STRIDE                          0xE06BEC
+
+#define mmTPC0_CFG_QM_TENSOR_8_DIM_4_SIZE                            0xE06BF0
+
+#define mmTPC0_CFG_QM_TENSOR_8_DIM_4_STRIDE                          0xE06BF4
+
+#define mmTPC0_CFG_QM_TENSOR_9_BASE_ADDR_LOW                         0xE06BF8
+
+#define mmTPC0_CFG_QM_TENSOR_9_BASE_ADDR_HIGH                        0xE06BFC
+
+#define mmTPC0_CFG_QM_TENSOR_9_PADDING_VALUE                         0xE06C00
+
+#define mmTPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG                         0xE06C04
+
+#define mmTPC0_CFG_QM_TENSOR_9_DIM_0_SIZE                            0xE06C08
+
+#define mmTPC0_CFG_QM_TENSOR_9_DIM_0_STRIDE                          0xE06C0C
+
+#define mmTPC0_CFG_QM_TENSOR_9_DIM_1_SIZE                            0xE06C10
+
+#define mmTPC0_CFG_QM_TENSOR_9_DIM_1_STRIDE                          0xE06C14
+
+#define mmTPC0_CFG_QM_TENSOR_9_DIM_2_SIZE                            0xE06C18
+
+#define mmTPC0_CFG_QM_TENSOR_9_DIM_2_STRIDE                          0xE06C1C
+
+#define mmTPC0_CFG_QM_TENSOR_9_DIM_3_SIZE                            0xE06C20
+
+#define mmTPC0_CFG_QM_TENSOR_9_DIM_3_STRIDE                          0xE06C24
+
+#define mmTPC0_CFG_QM_TENSOR_9_DIM_4_SIZE                            0xE06C28
+
+#define mmTPC0_CFG_QM_TENSOR_9_DIM_4_STRIDE                          0xE06C2C
+
+#define mmTPC0_CFG_QM_TENSOR_10_BASE_ADDR_LOW                        0xE06C30
+
+#define mmTPC0_CFG_QM_TENSOR_10_BASE_ADDR_HIGH                       0xE06C34
+
+#define mmTPC0_CFG_QM_TENSOR_10_PADDING_VALUE                        0xE06C38
+
+#define mmTPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG                        0xE06C3C
+
+#define mmTPC0_CFG_QM_TENSOR_10_DIM_0_SIZE                           0xE06C40
+
+#define mmTPC0_CFG_QM_TENSOR_10_DIM_0_STRIDE                         0xE06C44
+
+#define mmTPC0_CFG_QM_TENSOR_10_DIM_1_SIZE                           0xE06C48
+
+#define mmTPC0_CFG_QM_TENSOR_10_DIM_1_STRIDE                         0xE06C4C
+
+#define mmTPC0_CFG_QM_TENSOR_10_DIM_2_SIZE                           0xE06C50
+
+#define mmTPC0_CFG_QM_TENSOR_10_DIM_2_STRIDE                         0xE06C54
+
+#define mmTPC0_CFG_QM_TENSOR_10_DIM_3_SIZE                           0xE06C58
+
+#define mmTPC0_CFG_QM_TENSOR_10_DIM_3_STRIDE                         0xE06C5C
+
+#define mmTPC0_CFG_QM_TENSOR_10_DIM_4_SIZE                           0xE06C60
+
+#define mmTPC0_CFG_QM_TENSOR_10_DIM_4_STRIDE                         0xE06C64
+
+#define mmTPC0_CFG_QM_TENSOR_11_BASE_ADDR_LOW                        0xE06C68
+
+#define mmTPC0_CFG_QM_TENSOR_11_BASE_ADDR_HIGH                       0xE06C6C
+
+#define mmTPC0_CFG_QM_TENSOR_11_PADDING_VALUE                        0xE06C70
+
+#define mmTPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG                        0xE06C74
+
+#define mmTPC0_CFG_QM_TENSOR_11_DIM_0_SIZE                           0xE06C78
+
+#define mmTPC0_CFG_QM_TENSOR_11_DIM_0_STRIDE                         0xE06C7C
+
+#define mmTPC0_CFG_QM_TENSOR_11_DIM_1_SIZE                           0xE06C80
+
+#define mmTPC0_CFG_QM_TENSOR_11_DIM_1_STRIDE                         0xE06C84
+
+#define mmTPC0_CFG_QM_TENSOR_11_DIM_2_SIZE                           0xE06C88
+
+#define mmTPC0_CFG_QM_TENSOR_11_DIM_2_STRIDE                         0xE06C8C
+
+#define mmTPC0_CFG_QM_TENSOR_11_DIM_3_SIZE                           0xE06C90
+
+#define mmTPC0_CFG_QM_TENSOR_11_DIM_3_STRIDE                         0xE06C94
+
+#define mmTPC0_CFG_QM_TENSOR_11_DIM_4_SIZE                           0xE06C98
+
+#define mmTPC0_CFG_QM_TENSOR_11_DIM_4_STRIDE                         0xE06C9C
+
+#define mmTPC0_CFG_QM_TENSOR_12_BASE_ADDR_LOW                        0xE06CA0
+
+#define mmTPC0_CFG_QM_TENSOR_12_BASE_ADDR_HIGH                       0xE06CA4
+
+#define mmTPC0_CFG_QM_TENSOR_12_PADDING_VALUE                        0xE06CA8
+
+#define mmTPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG                        0xE06CAC
+
+#define mmTPC0_CFG_QM_TENSOR_12_DIM_0_SIZE                           0xE06CB0
+
+#define mmTPC0_CFG_QM_TENSOR_12_DIM_0_STRIDE                         0xE06CB4
+
+#define mmTPC0_CFG_QM_TENSOR_12_DIM_1_SIZE                           0xE06CB8
+
+#define mmTPC0_CFG_QM_TENSOR_12_DIM_1_STRIDE                         0xE06CBC
+
+#define mmTPC0_CFG_QM_TENSOR_12_DIM_2_SIZE                           0xE06CC0
+
+#define mmTPC0_CFG_QM_TENSOR_12_DIM_2_STRIDE                         0xE06CC4
+
+#define mmTPC0_CFG_QM_TENSOR_12_DIM_3_SIZE                           0xE06CC8
+
+#define mmTPC0_CFG_QM_TENSOR_12_DIM_3_STRIDE                         0xE06CCC
+
+#define mmTPC0_CFG_QM_TENSOR_12_DIM_4_SIZE                           0xE06CD0
+
+#define mmTPC0_CFG_QM_TENSOR_12_DIM_4_STRIDE                         0xE06CD4
+
+#define mmTPC0_CFG_QM_TENSOR_13_BASE_ADDR_LOW                        0xE06CD8
+
+#define mmTPC0_CFG_QM_TENSOR_13_BASE_ADDR_HIGH                       0xE06CDC
+
+#define mmTPC0_CFG_QM_TENSOR_13_PADDING_VALUE                        0xE06CE0
+
+#define mmTPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG                        0xE06CE4
+
+#define mmTPC0_CFG_QM_TENSOR_13_DIM_0_SIZE                           0xE06CE8
+
+#define mmTPC0_CFG_QM_TENSOR_13_DIM_0_STRIDE                         0xE06CEC
+
+#define mmTPC0_CFG_QM_TENSOR_13_DIM_1_SIZE                           0xE06CF0
+
+#define mmTPC0_CFG_QM_TENSOR_13_DIM_1_STRIDE                         0xE06CF4
+
+#define mmTPC0_CFG_QM_TENSOR_13_DIM_2_SIZE                           0xE06CF8
+
+#define mmTPC0_CFG_QM_TENSOR_13_DIM_2_STRIDE                         0xE06CFC
+
+#define mmTPC0_CFG_QM_TENSOR_13_DIM_3_SIZE                           0xE06D00
+
+#define mmTPC0_CFG_QM_TENSOR_13_DIM_3_STRIDE                         0xE06D04
+
+#define mmTPC0_CFG_QM_TENSOR_13_DIM_4_SIZE                           0xE06D08
+
+#define mmTPC0_CFG_QM_TENSOR_13_DIM_4_STRIDE                         0xE06D0C
+
+#define mmTPC0_CFG_QM_TENSOR_14_BASE_ADDR_LOW                        0xE06D10
+
+#define mmTPC0_CFG_QM_TENSOR_14_BASE_ADDR_HIGH                       0xE06D14
+
+#define mmTPC0_CFG_QM_TENSOR_14_PADDING_VALUE                        0xE06D18
+
+#define mmTPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG                        0xE06D1C
+
+#define mmTPC0_CFG_QM_TENSOR_14_DIM_0_SIZE                           0xE06D20
+
+#define mmTPC0_CFG_QM_TENSOR_14_DIM_0_STRIDE                         0xE06D24
+
+#define mmTPC0_CFG_QM_TENSOR_14_DIM_1_SIZE                           0xE06D28
+
+#define mmTPC0_CFG_QM_TENSOR_14_DIM_1_STRIDE                         0xE06D2C
+
+#define mmTPC0_CFG_QM_TENSOR_14_DIM_2_SIZE                           0xE06D30
+
+#define mmTPC0_CFG_QM_TENSOR_14_DIM_2_STRIDE                         0xE06D34
+
+#define mmTPC0_CFG_QM_TENSOR_14_DIM_3_SIZE                           0xE06D38
+
+#define mmTPC0_CFG_QM_TENSOR_14_DIM_3_STRIDE                         0xE06D3C
+
+#define mmTPC0_CFG_QM_TENSOR_14_DIM_4_SIZE                           0xE06D40
+
+#define mmTPC0_CFG_QM_TENSOR_14_DIM_4_STRIDE                         0xE06D44
+
+#define mmTPC0_CFG_QM_TENSOR_15_BASE_ADDR_LOW                        0xE06D48
+
+#define mmTPC0_CFG_QM_TENSOR_15_BASE_ADDR_HIGH                       0xE06D4C
+
+#define mmTPC0_CFG_QM_TENSOR_15_PADDING_VALUE                        0xE06D50
+
+#define mmTPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG                        0xE06D54
+
+#define mmTPC0_CFG_QM_TENSOR_15_DIM_0_SIZE                           0xE06D58
+
+#define mmTPC0_CFG_QM_TENSOR_15_DIM_0_STRIDE                         0xE06D5C
+
+#define mmTPC0_CFG_QM_TENSOR_15_DIM_1_SIZE                           0xE06D60
+
+#define mmTPC0_CFG_QM_TENSOR_15_DIM_1_STRIDE                         0xE06D64
+
+#define mmTPC0_CFG_QM_TENSOR_15_DIM_2_SIZE                           0xE06D68
+
+#define mmTPC0_CFG_QM_TENSOR_15_DIM_2_STRIDE                         0xE06D6C
+
+#define mmTPC0_CFG_QM_TENSOR_15_DIM_3_SIZE                           0xE06D70
+
+#define mmTPC0_CFG_QM_TENSOR_15_DIM_3_STRIDE                         0xE06D74
+
+#define mmTPC0_CFG_QM_TENSOR_15_DIM_4_SIZE                           0xE06D78
+
+#define mmTPC0_CFG_QM_TENSOR_15_DIM_4_STRIDE                         0xE06D7C
+
+#define mmTPC0_CFG_QM_SYNC_OBJECT_MESSAGE                            0xE06D80
+
+#define mmTPC0_CFG_QM_SYNC_OBJECT_ADDR                               0xE06D84
+
+#define mmTPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW                        0xE06D88
+
+#define mmTPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH                       0xE06D8C
+
+#define mmTPC0_CFG_QM_TID_BASE_DIM_0                                 0xE06D90
+
+#define mmTPC0_CFG_QM_TID_SIZE_DIM_0                                 0xE06D94
+
+#define mmTPC0_CFG_QM_TID_BASE_DIM_1                                 0xE06D98
+
+#define mmTPC0_CFG_QM_TID_SIZE_DIM_1                                 0xE06D9C
+
+#define mmTPC0_CFG_QM_TID_BASE_DIM_2                                 0xE06DA0
+
+#define mmTPC0_CFG_QM_TID_SIZE_DIM_2                                 0xE06DA4
+
+#define mmTPC0_CFG_QM_TID_BASE_DIM_3                                 0xE06DA8
+
+#define mmTPC0_CFG_QM_TID_SIZE_DIM_3                                 0xE06DAC
+
+#define mmTPC0_CFG_QM_TID_BASE_DIM_4                                 0xE06DB0
+
+#define mmTPC0_CFG_QM_TID_SIZE_DIM_4                                 0xE06DB4
+
+#define mmTPC0_CFG_QM_KERNEL_CONFIG                                  0xE06DB8
+
+#define mmTPC0_CFG_QM_KERNEL_ID                                      0xE06DBC
+
+#define mmTPC0_CFG_QM_SRF_0                                          0xE06DC0
+
+#define mmTPC0_CFG_QM_SRF_1                                          0xE06DC4
+
+#define mmTPC0_CFG_QM_SRF_2                                          0xE06DC8
+
+#define mmTPC0_CFG_QM_SRF_3                                          0xE06DCC
+
+#define mmTPC0_CFG_QM_SRF_4                                          0xE06DD0
+
+#define mmTPC0_CFG_QM_SRF_5                                          0xE06DD4
+
+#define mmTPC0_CFG_QM_SRF_6                                          0xE06DD8
+
+#define mmTPC0_CFG_QM_SRF_7                                          0xE06DDC
+
+#define mmTPC0_CFG_QM_SRF_8                                          0xE06DE0
+
+#define mmTPC0_CFG_QM_SRF_9                                          0xE06DE4
+
+#define mmTPC0_CFG_QM_SRF_10                                         0xE06DE8
+
+#define mmTPC0_CFG_QM_SRF_11                                         0xE06DEC
+
+#define mmTPC0_CFG_QM_SRF_12                                         0xE06DF0
+
+#define mmTPC0_CFG_QM_SRF_13                                         0xE06DF4
+
+#define mmTPC0_CFG_QM_SRF_14                                         0xE06DF8
+
+#define mmTPC0_CFG_QM_SRF_15                                         0xE06DFC
+
+#define mmTPC0_CFG_QM_SRF_16                                         0xE06E00
+
+#define mmTPC0_CFG_QM_SRF_17                                         0xE06E04
+
+#define mmTPC0_CFG_QM_SRF_18                                         0xE06E08
+
+#define mmTPC0_CFG_QM_SRF_19                                         0xE06E0C
+
+#define mmTPC0_CFG_QM_SRF_20                                         0xE06E10
+
+#define mmTPC0_CFG_QM_SRF_21                                         0xE06E14
+
+#define mmTPC0_CFG_QM_SRF_22                                         0xE06E18
+
+#define mmTPC0_CFG_QM_SRF_23                                         0xE06E1C
+
+#define mmTPC0_CFG_QM_SRF_24                                         0xE06E20
+
+#define mmTPC0_CFG_QM_SRF_25                                         0xE06E24
+
+#define mmTPC0_CFG_QM_SRF_26                                         0xE06E28
+
+#define mmTPC0_CFG_QM_SRF_27                                         0xE06E2C
+
+#define mmTPC0_CFG_QM_SRF_28                                         0xE06E30
+
+#define mmTPC0_CFG_QM_SRF_29                                         0xE06E34
+
+#define mmTPC0_CFG_QM_SRF_30                                         0xE06E38
+
+#define mmTPC0_CFG_QM_SRF_31                                         0xE06E3C
+
+#endif /* ASIC_REG_TPC0_CFG_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc0_qm_masks.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc0_qm_masks.h
new file mode 100644
index 000000000000..8e71532c6f36
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc0_qm_masks.h
@@ -0,0 +1,800 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_TPC0_QM_MASKS_H_
+#define ASIC_REG_TPC0_QM_MASKS_H_
+
+/*
+ *****************************************
+ *   TPC0_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+/* TPC0_QM_GLBL_CFG0 */
+#define TPC0_QM_GLBL_CFG0_PQF_EN_SHIFT                               0
+#define TPC0_QM_GLBL_CFG0_PQF_EN_MASK                                0xF
+#define TPC0_QM_GLBL_CFG0_CQF_EN_SHIFT                               4
+#define TPC0_QM_GLBL_CFG0_CQF_EN_MASK                                0x1F0
+#define TPC0_QM_GLBL_CFG0_CP_EN_SHIFT                                9
+#define TPC0_QM_GLBL_CFG0_CP_EN_MASK                                 0x3E00
+
+/* TPC0_QM_GLBL_CFG1 */
+#define TPC0_QM_GLBL_CFG1_PQF_STOP_SHIFT                             0
+#define TPC0_QM_GLBL_CFG1_PQF_STOP_MASK                              0xF
+#define TPC0_QM_GLBL_CFG1_CQF_STOP_SHIFT                             4
+#define TPC0_QM_GLBL_CFG1_CQF_STOP_MASK                              0x1F0
+#define TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT                              9
+#define TPC0_QM_GLBL_CFG1_CP_STOP_MASK                               0x3E00
+#define TPC0_QM_GLBL_CFG1_PQF_FLUSH_SHIFT                            16
+#define TPC0_QM_GLBL_CFG1_PQF_FLUSH_MASK                             0xF0000
+#define TPC0_QM_GLBL_CFG1_CQF_FLUSH_SHIFT                            20
+#define TPC0_QM_GLBL_CFG1_CQF_FLUSH_MASK                             0x1F00000
+#define TPC0_QM_GLBL_CFG1_CP_FLUSH_SHIFT                             25
+#define TPC0_QM_GLBL_CFG1_CP_FLUSH_MASK                              0x3E000000
+
+/* TPC0_QM_GLBL_PROT */
+#define TPC0_QM_GLBL_PROT_PQF_SHIFT                                  0
+#define TPC0_QM_GLBL_PROT_PQF_MASK                                   0xF
+#define TPC0_QM_GLBL_PROT_CQF_SHIFT                                  4
+#define TPC0_QM_GLBL_PROT_CQF_MASK                                   0x1F0
+#define TPC0_QM_GLBL_PROT_CP_SHIFT                                   9
+#define TPC0_QM_GLBL_PROT_CP_MASK                                    0x3E00
+#define TPC0_QM_GLBL_PROT_ERR_SHIFT                                  14
+#define TPC0_QM_GLBL_PROT_ERR_MASK                                   0x4000
+#define TPC0_QM_GLBL_PROT_ARB_SHIFT                                  15
+#define TPC0_QM_GLBL_PROT_ARB_MASK                                   0x8000
+
+/* TPC0_QM_GLBL_ERR_CFG */
+#define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT                    0
+#define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK                     0xF
+#define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT                    4
+#define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK                     0x1F0
+#define TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT                     9
+#define TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK                      0x3E00
+#define TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT                   16
+#define TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK                    0xF0000
+#define TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT                   20
+#define TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK                    0x1F00000
+#define TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT                    25
+#define TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK                     0x3E000000
+#define TPC0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT                   31
+#define TPC0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK                    0x80000000
+
+/* TPC0_QM_GLBL_SECURE_PROPS */
+#define TPC0_QM_GLBL_SECURE_PROPS_0_ASID_SHIFT                       0
+#define TPC0_QM_GLBL_SECURE_PROPS_0_ASID_MASK                        0x3FF
+#define TPC0_QM_GLBL_SECURE_PROPS_1_ASID_SHIFT                       0
+#define TPC0_QM_GLBL_SECURE_PROPS_1_ASID_MASK                        0x3FF
+#define TPC0_QM_GLBL_SECURE_PROPS_2_ASID_SHIFT                       0
+#define TPC0_QM_GLBL_SECURE_PROPS_2_ASID_MASK                        0x3FF
+#define TPC0_QM_GLBL_SECURE_PROPS_3_ASID_SHIFT                       0
+#define TPC0_QM_GLBL_SECURE_PROPS_3_ASID_MASK                        0x3FF
+#define TPC0_QM_GLBL_SECURE_PROPS_4_ASID_SHIFT                       0
+#define TPC0_QM_GLBL_SECURE_PROPS_4_ASID_MASK                        0x3FF
+#define TPC0_QM_GLBL_SECURE_PROPS_0_MMBP_SHIFT                       10
+#define TPC0_QM_GLBL_SECURE_PROPS_0_MMBP_MASK                        0x400
+#define TPC0_QM_GLBL_SECURE_PROPS_1_MMBP_SHIFT                       10
+#define TPC0_QM_GLBL_SECURE_PROPS_1_MMBP_MASK                        0x400
+#define TPC0_QM_GLBL_SECURE_PROPS_2_MMBP_SHIFT                       10
+#define TPC0_QM_GLBL_SECURE_PROPS_2_MMBP_MASK                        0x400
+#define TPC0_QM_GLBL_SECURE_PROPS_3_MMBP_SHIFT                       10
+#define TPC0_QM_GLBL_SECURE_PROPS_3_MMBP_MASK                        0x400
+#define TPC0_QM_GLBL_SECURE_PROPS_4_MMBP_SHIFT                       10
+#define TPC0_QM_GLBL_SECURE_PROPS_4_MMBP_MASK                        0x400
+
+/* TPC0_QM_GLBL_NON_SECURE_PROPS */
+#define TPC0_QM_GLBL_NON_SECURE_PROPS_0_ASID_SHIFT                   0
+#define TPC0_QM_GLBL_NON_SECURE_PROPS_0_ASID_MASK                    0x3FF
+#define TPC0_QM_GLBL_NON_SECURE_PROPS_1_ASID_SHIFT                   0
+#define TPC0_QM_GLBL_NON_SECURE_PROPS_1_ASID_MASK                    0x3FF
+#define TPC0_QM_GLBL_NON_SECURE_PROPS_2_ASID_SHIFT                   0
+#define TPC0_QM_GLBL_NON_SECURE_PROPS_2_ASID_MASK                    0x3FF
+#define TPC0_QM_GLBL_NON_SECURE_PROPS_3_ASID_SHIFT                   0
+#define TPC0_QM_GLBL_NON_SECURE_PROPS_3_ASID_MASK                    0x3FF
+#define TPC0_QM_GLBL_NON_SECURE_PROPS_4_ASID_SHIFT                   0
+#define TPC0_QM_GLBL_NON_SECURE_PROPS_4_ASID_MASK                    0x3FF
+#define TPC0_QM_GLBL_NON_SECURE_PROPS_0_MMBP_SHIFT                   10
+#define TPC0_QM_GLBL_NON_SECURE_PROPS_0_MMBP_MASK                    0x400
+#define TPC0_QM_GLBL_NON_SECURE_PROPS_1_MMBP_SHIFT                   10
+#define TPC0_QM_GLBL_NON_SECURE_PROPS_1_MMBP_MASK                    0x400
+#define TPC0_QM_GLBL_NON_SECURE_PROPS_2_MMBP_SHIFT                   10
+#define TPC0_QM_GLBL_NON_SECURE_PROPS_2_MMBP_MASK                    0x400
+#define TPC0_QM_GLBL_NON_SECURE_PROPS_3_MMBP_SHIFT                   10
+#define TPC0_QM_GLBL_NON_SECURE_PROPS_3_MMBP_MASK                    0x400
+#define TPC0_QM_GLBL_NON_SECURE_PROPS_4_MMBP_SHIFT                   10
+#define TPC0_QM_GLBL_NON_SECURE_PROPS_4_MMBP_MASK                    0x400
+
+/* TPC0_QM_GLBL_STS0 */
+#define TPC0_QM_GLBL_STS0_PQF_IDLE_SHIFT                             0
+#define TPC0_QM_GLBL_STS0_PQF_IDLE_MASK                              0xF
+#define TPC0_QM_GLBL_STS0_CQF_IDLE_SHIFT                             4
+#define TPC0_QM_GLBL_STS0_CQF_IDLE_MASK                              0x1F0
+#define TPC0_QM_GLBL_STS0_CP_IDLE_SHIFT                              9
+#define TPC0_QM_GLBL_STS0_CP_IDLE_MASK                               0x3E00
+#define TPC0_QM_GLBL_STS0_PQF_IS_STOP_SHIFT                          16
+#define TPC0_QM_GLBL_STS0_PQF_IS_STOP_MASK                           0xF0000
+#define TPC0_QM_GLBL_STS0_CQF_IS_STOP_SHIFT                          20
+#define TPC0_QM_GLBL_STS0_CQF_IS_STOP_MASK                           0x1F00000
+#define TPC0_QM_GLBL_STS0_CP_IS_STOP_SHIFT                           25
+#define TPC0_QM_GLBL_STS0_CP_IS_STOP_MASK                            0x3E000000
+#define TPC0_QM_GLBL_STS0_ARB_IS_STOP_SHIFT                          31
+#define TPC0_QM_GLBL_STS0_ARB_IS_STOP_MASK                           0x80000000
+
+/* TPC0_QM_GLBL_STS1 */
+#define TPC0_QM_GLBL_STS1_PQF_RD_ERR_SHIFT                           0
+#define TPC0_QM_GLBL_STS1_PQF_RD_ERR_MASK                            0x1
+#define TPC0_QM_GLBL_STS1_CQF_RD_ERR_SHIFT                           1
+#define TPC0_QM_GLBL_STS1_CQF_RD_ERR_MASK                            0x2
+#define TPC0_QM_GLBL_STS1_CP_RD_ERR_SHIFT                            2
+#define TPC0_QM_GLBL_STS1_CP_RD_ERR_MASK                             0x4
+#define TPC0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT                     3
+#define TPC0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK                      0x8
+#define TPC0_QM_GLBL_STS1_CP_STOP_OP_SHIFT                           4
+#define TPC0_QM_GLBL_STS1_CP_STOP_OP_MASK                            0x10
+#define TPC0_QM_GLBL_STS1_CP_MSG_WR_ERR_SHIFT                        5
+#define TPC0_QM_GLBL_STS1_CP_MSG_WR_ERR_MASK                         0x20
+#define TPC0_QM_GLBL_STS1_CP_WREG_ERR_SHIFT                          6
+#define TPC0_QM_GLBL_STS1_CP_WREG_ERR_MASK                           0x40
+#define TPC0_QM_GLBL_STS1_CP_FENCE0_OVF_ERR_SHIFT                    8
+#define TPC0_QM_GLBL_STS1_CP_FENCE0_OVF_ERR_MASK                     0x100
+#define TPC0_QM_GLBL_STS1_CP_FENCE1_OVF_ERR_SHIFT                    9
+#define TPC0_QM_GLBL_STS1_CP_FENCE1_OVF_ERR_MASK                     0x200
+#define TPC0_QM_GLBL_STS1_CP_FENCE2_OVF_ERR_SHIFT                    10
+#define TPC0_QM_GLBL_STS1_CP_FENCE2_OVF_ERR_MASK                     0x400
+#define TPC0_QM_GLBL_STS1_CP_FENCE3_OVF_ERR_SHIFT                    11
+#define TPC0_QM_GLBL_STS1_CP_FENCE3_OVF_ERR_MASK                     0x800
+#define TPC0_QM_GLBL_STS1_CP_FENCE0_UDF_ERR_SHIFT                    12
+#define TPC0_QM_GLBL_STS1_CP_FENCE0_UDF_ERR_MASK                     0x1000
+#define TPC0_QM_GLBL_STS1_CP_FENCE1_UDF_ERR_SHIFT                    13
+#define TPC0_QM_GLBL_STS1_CP_FENCE1_UDF_ERR_MASK                     0x2000
+#define TPC0_QM_GLBL_STS1_CP_FENCE2_UDF_ERR_SHIFT                    14
+#define TPC0_QM_GLBL_STS1_CP_FENCE2_UDF_ERR_MASK                     0x4000
+#define TPC0_QM_GLBL_STS1_CP_FENCE3_UDF_ERR_SHIFT                    15
+#define TPC0_QM_GLBL_STS1_CP_FENCE3_UDF_ERR_MASK                     0x8000
+
+/* TPC0_QM_GLBL_STS1_4 */
+#define TPC0_QM_GLBL_STS1_4_CQF_RD_ERR_SHIFT                         1
+#define TPC0_QM_GLBL_STS1_4_CQF_RD_ERR_MASK                          0x2
+#define TPC0_QM_GLBL_STS1_4_CP_RD_ERR_SHIFT                          2
+#define TPC0_QM_GLBL_STS1_4_CP_RD_ERR_MASK                           0x4
+#define TPC0_QM_GLBL_STS1_4_CP_UNDEF_CMD_ERR_SHIFT                   3
+#define TPC0_QM_GLBL_STS1_4_CP_UNDEF_CMD_ERR_MASK                    0x8
+#define TPC0_QM_GLBL_STS1_4_CP_STOP_OP_SHIFT                         4
+#define TPC0_QM_GLBL_STS1_4_CP_STOP_OP_MASK                          0x10
+#define TPC0_QM_GLBL_STS1_4_CP_MSG_WR_ERR_SHIFT                      5
+#define TPC0_QM_GLBL_STS1_4_CP_MSG_WR_ERR_MASK                       0x20
+#define TPC0_QM_GLBL_STS1_4_CP_WREG_ERR_SHIFT                        6
+#define TPC0_QM_GLBL_STS1_4_CP_WREG_ERR_MASK                         0x40
+#define TPC0_QM_GLBL_STS1_4_CP_FENCE0_OVF_ERR_SHIFT                  8
+#define TPC0_QM_GLBL_STS1_4_CP_FENCE0_OVF_ERR_MASK                   0x100
+#define TPC0_QM_GLBL_STS1_4_CP_FENCE1_OVF_ERR_SHIFT                  9
+#define TPC0_QM_GLBL_STS1_4_CP_FENCE1_OVF_ERR_MASK                   0x200
+#define TPC0_QM_GLBL_STS1_4_CP_FENCE2_OVF_ERR_SHIFT                  10
+#define TPC0_QM_GLBL_STS1_4_CP_FENCE2_OVF_ERR_MASK                   0x400
+#define TPC0_QM_GLBL_STS1_4_CP_FENCE3_OVF_ERR_SHIFT                  11
+#define TPC0_QM_GLBL_STS1_4_CP_FENCE3_OVF_ERR_MASK                   0x800
+#define TPC0_QM_GLBL_STS1_4_CP_FENCE0_UDF_ERR_SHIFT                  12
+#define TPC0_QM_GLBL_STS1_4_CP_FENCE0_UDF_ERR_MASK                   0x1000
+#define TPC0_QM_GLBL_STS1_4_CP_FENCE1_UDF_ERR_SHIFT                  13
+#define TPC0_QM_GLBL_STS1_4_CP_FENCE1_UDF_ERR_MASK                   0x2000
+#define TPC0_QM_GLBL_STS1_4_CP_FENCE2_UDF_ERR_SHIFT                  14
+#define TPC0_QM_GLBL_STS1_4_CP_FENCE2_UDF_ERR_MASK                   0x4000
+#define TPC0_QM_GLBL_STS1_4_CP_FENCE3_UDF_ERR_SHIFT                  15
+#define TPC0_QM_GLBL_STS1_4_CP_FENCE3_UDF_ERR_MASK                   0x8000
+
+/* TPC0_QM_GLBL_MSG_EN */
+#define TPC0_QM_GLBL_MSG_EN_PQF_RD_ERR_SHIFT                         0
+#define TPC0_QM_GLBL_MSG_EN_PQF_RD_ERR_MASK                          0x1
+#define TPC0_QM_GLBL_MSG_EN_CQF_RD_ERR_SHIFT                         1
+#define TPC0_QM_GLBL_MSG_EN_CQF_RD_ERR_MASK                          0x2
+#define TPC0_QM_GLBL_MSG_EN_CP_RD_ERR_SHIFT                          2
+#define TPC0_QM_GLBL_MSG_EN_CP_RD_ERR_MASK                           0x4
+#define TPC0_QM_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_SHIFT                   3
+#define TPC0_QM_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_MASK                    0x8
+#define TPC0_QM_GLBL_MSG_EN_CP_STOP_OP_SHIFT                         4
+#define TPC0_QM_GLBL_MSG_EN_CP_STOP_OP_MASK                          0x10
+#define TPC0_QM_GLBL_MSG_EN_CP_MSG_WR_ERR_SHIFT                      5
+#define TPC0_QM_GLBL_MSG_EN_CP_MSG_WR_ERR_MASK                       0x20
+#define TPC0_QM_GLBL_MSG_EN_CP_WREG_ERR_SHIFT                        6
+#define TPC0_QM_GLBL_MSG_EN_CP_WREG_ERR_MASK                         0x40
+#define TPC0_QM_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_SHIFT                  8
+#define TPC0_QM_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_MASK                   0x100
+#define TPC0_QM_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_SHIFT                  9
+#define TPC0_QM_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_MASK                   0x200
+#define TPC0_QM_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_SHIFT                  10
+#define TPC0_QM_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_MASK                   0x400
+#define TPC0_QM_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_SHIFT                  11
+#define TPC0_QM_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_MASK                   0x800
+#define TPC0_QM_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_SHIFT                  12
+#define TPC0_QM_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_MASK                   0x1000
+#define TPC0_QM_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_SHIFT                  13
+#define TPC0_QM_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_MASK                   0x2000
+#define TPC0_QM_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_SHIFT                  14
+#define TPC0_QM_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_MASK                   0x4000
+#define TPC0_QM_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_SHIFT                  15
+#define TPC0_QM_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_MASK                   0x8000
+
+/* TPC0_QM_GLBL_MSG_EN_4 */
+#define TPC0_QM_GLBL_MSG_EN_4_CQF_RD_ERR_SHIFT                       1
+#define TPC0_QM_GLBL_MSG_EN_4_CQF_RD_ERR_MASK                        0x2
+#define TPC0_QM_GLBL_MSG_EN_4_CP_RD_ERR_SHIFT                        2
+#define TPC0_QM_GLBL_MSG_EN_4_CP_RD_ERR_MASK                         0x4
+#define TPC0_QM_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_SHIFT                 3
+#define TPC0_QM_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_MASK                  0x8
+#define TPC0_QM_GLBL_MSG_EN_4_CP_STOP_OP_SHIFT                       4
+#define TPC0_QM_GLBL_MSG_EN_4_CP_STOP_OP_MASK                        0x10
+#define TPC0_QM_GLBL_MSG_EN_4_CP_MSG_WR_ERR_SHIFT                    5
+#define TPC0_QM_GLBL_MSG_EN_4_CP_MSG_WR_ERR_MASK                     0x20
+#define TPC0_QM_GLBL_MSG_EN_4_CP_WREG_ERR_SHIFT                      6
+#define TPC0_QM_GLBL_MSG_EN_4_CP_WREG_ERR_MASK                       0x40
+#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_SHIFT                8
+#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_MASK                 0x100
+#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_SHIFT                9
+#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_MASK                 0x200
+#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_SHIFT                10
+#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_MASK                 0x400
+#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_SHIFT                11
+#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_MASK                 0x800
+#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_SHIFT                12
+#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_MASK                 0x1000
+#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_SHIFT                13
+#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_MASK                 0x2000
+#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_SHIFT                14
+#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_MASK                 0x4000
+#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_SHIFT                15
+#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_MASK                 0x8000
+
+/* TPC0_QM_PQ_BASE_LO */
+#define TPC0_QM_PQ_BASE_LO_VAL_SHIFT                                 0
+#define TPC0_QM_PQ_BASE_LO_VAL_MASK                                  0xFFFFFFFF
+
+/* TPC0_QM_PQ_BASE_HI */
+#define TPC0_QM_PQ_BASE_HI_VAL_SHIFT                                 0
+#define TPC0_QM_PQ_BASE_HI_VAL_MASK                                  0xFFFFFFFF
+
+/* TPC0_QM_PQ_SIZE */
+#define TPC0_QM_PQ_SIZE_VAL_SHIFT                                    0
+#define TPC0_QM_PQ_SIZE_VAL_MASK                                     0xFFFFFFFF
+
+/* TPC0_QM_PQ_PI */
+#define TPC0_QM_PQ_PI_VAL_SHIFT                                      0
+#define TPC0_QM_PQ_PI_VAL_MASK                                       0xFFFFFFFF
+
+/* TPC0_QM_PQ_CI */
+#define TPC0_QM_PQ_CI_VAL_SHIFT                                      0
+#define TPC0_QM_PQ_CI_VAL_MASK                                       0xFFFFFFFF
+
+/* TPC0_QM_PQ_CFG0 */
+#define TPC0_QM_PQ_CFG0_RESERVED_SHIFT                               0
+#define TPC0_QM_PQ_CFG0_RESERVED_MASK                                0x1
+
+/* TPC0_QM_PQ_CFG1 */
+#define TPC0_QM_PQ_CFG1_CREDIT_LIM_SHIFT                             0
+#define TPC0_QM_PQ_CFG1_CREDIT_LIM_MASK                              0xFFFF
+#define TPC0_QM_PQ_CFG1_MAX_INFLIGHT_SHIFT                           16
+#define TPC0_QM_PQ_CFG1_MAX_INFLIGHT_MASK                            0xFFFF0000
+
+/* TPC0_QM_PQ_ARUSER_31_11 */
+#define TPC0_QM_PQ_ARUSER_31_11_VAL_SHIFT                            0
+#define TPC0_QM_PQ_ARUSER_31_11_VAL_MASK                             0x1FFFFF
+
+/* TPC0_QM_PQ_STS0 */
+#define TPC0_QM_PQ_STS0_PQ_CREDIT_CNT_SHIFT                          0
+#define TPC0_QM_PQ_STS0_PQ_CREDIT_CNT_MASK                           0xFFFF
+#define TPC0_QM_PQ_STS0_PQ_FREE_CNT_SHIFT                            16
+#define TPC0_QM_PQ_STS0_PQ_FREE_CNT_MASK                             0xFFFF0000
+
+/* TPC0_QM_PQ_STS1 */
+#define TPC0_QM_PQ_STS1_PQ_INFLIGHT_CNT_SHIFT                        0
+#define TPC0_QM_PQ_STS1_PQ_INFLIGHT_CNT_MASK                         0xFFFF
+#define TPC0_QM_PQ_STS1_PQ_BUF_EMPTY_SHIFT                           30
+#define TPC0_QM_PQ_STS1_PQ_BUF_EMPTY_MASK                            0x40000000
+#define TPC0_QM_PQ_STS1_PQ_BUSY_SHIFT                                31
+#define TPC0_QM_PQ_STS1_PQ_BUSY_MASK                                 0x80000000
+
+/* TPC0_QM_CQ_CFG0 */
+#define TPC0_QM_CQ_CFG0_RESERVED_SHIFT                               0
+#define TPC0_QM_CQ_CFG0_RESERVED_MASK                                0x1
+
+/* TPC0_QM_CQ_CFG1 */
+#define TPC0_QM_CQ_CFG1_CREDIT_LIM_SHIFT                             0
+#define TPC0_QM_CQ_CFG1_CREDIT_LIM_MASK                              0xFFFF
+#define TPC0_QM_CQ_CFG1_MAX_INFLIGHT_SHIFT                           16
+#define TPC0_QM_CQ_CFG1_MAX_INFLIGHT_MASK                            0xFFFF0000
+
+/* TPC0_QM_CQ_ARUSER_31_11 */
+#define TPC0_QM_CQ_ARUSER_31_11_VAL_SHIFT                            0
+#define TPC0_QM_CQ_ARUSER_31_11_VAL_MASK                             0x1FFFFF
+
+/* TPC0_QM_CQ_STS0 */
+#define TPC0_QM_CQ_STS0_CQ_CREDIT_CNT_SHIFT                          0
+#define TPC0_QM_CQ_STS0_CQ_CREDIT_CNT_MASK                           0xFFFF
+#define TPC0_QM_CQ_STS0_CQ_FREE_CNT_SHIFT                            16
+#define TPC0_QM_CQ_STS0_CQ_FREE_CNT_MASK                             0xFFFF0000
+
+/* TPC0_QM_CQ_STS1 */
+#define TPC0_QM_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT                        0
+#define TPC0_QM_CQ_STS1_CQ_INFLIGHT_CNT_MASK                         0xFFFF
+#define TPC0_QM_CQ_STS1_CQ_BUF_EMPTY_SHIFT                           30
+#define TPC0_QM_CQ_STS1_CQ_BUF_EMPTY_MASK                            0x40000000
+#define TPC0_QM_CQ_STS1_CQ_BUSY_SHIFT                                31
+#define TPC0_QM_CQ_STS1_CQ_BUSY_MASK                                 0x80000000
+
+/* TPC0_QM_CQ_PTR_LO_0 */
+#define TPC0_QM_CQ_PTR_LO_0_VAL_SHIFT                                0
+#define TPC0_QM_CQ_PTR_LO_0_VAL_MASK                                 0xFFFFFFFF
+
+/* TPC0_QM_CQ_PTR_HI_0 */
+#define TPC0_QM_CQ_PTR_HI_0_VAL_SHIFT                                0
+#define TPC0_QM_CQ_PTR_HI_0_VAL_MASK                                 0xFFFFFFFF
+
+/* TPC0_QM_CQ_TSIZE_0 */
+#define TPC0_QM_CQ_TSIZE_0_VAL_SHIFT                                 0
+#define TPC0_QM_CQ_TSIZE_0_VAL_MASK                                  0xFFFFFFFF
+
+/* TPC0_QM_CQ_CTL_0 */
+#define TPC0_QM_CQ_CTL_0_RPT_SHIFT                                   0
+#define TPC0_QM_CQ_CTL_0_RPT_MASK                                    0xFFFF
+#define TPC0_QM_CQ_CTL_0_CTL_SHIFT                                   16
+#define TPC0_QM_CQ_CTL_0_CTL_MASK                                    0xFFFF0000
+
+/* TPC0_QM_CQ_PTR_LO_1 */
+#define TPC0_QM_CQ_PTR_LO_1_VAL_SHIFT                                0
+#define TPC0_QM_CQ_PTR_LO_1_VAL_MASK                                 0xFFFFFFFF
+
+/* TPC0_QM_CQ_PTR_HI_1 */
+#define TPC0_QM_CQ_PTR_HI_1_VAL_SHIFT                                0
+#define TPC0_QM_CQ_PTR_HI_1_VAL_MASK                                 0xFFFFFFFF
+
+/* TPC0_QM_CQ_TSIZE_1 */
+#define TPC0_QM_CQ_TSIZE_1_VAL_SHIFT                                 0
+#define TPC0_QM_CQ_TSIZE_1_VAL_MASK                                  0xFFFFFFFF
+
+/* TPC0_QM_CQ_CTL_1 */
+#define TPC0_QM_CQ_CTL_1_RPT_SHIFT                                   0
+#define TPC0_QM_CQ_CTL_1_RPT_MASK                                    0xFFFF
+#define TPC0_QM_CQ_CTL_1_CTL_SHIFT                                   16
+#define TPC0_QM_CQ_CTL_1_CTL_MASK                                    0xFFFF0000
+
+/* TPC0_QM_CQ_PTR_LO_2 */
+#define TPC0_QM_CQ_PTR_LO_2_VAL_SHIFT                                0
+#define TPC0_QM_CQ_PTR_LO_2_VAL_MASK                                 0xFFFFFFFF
+
+/* TPC0_QM_CQ_PTR_HI_2 */
+#define TPC0_QM_CQ_PTR_HI_2_VAL_SHIFT                                0
+#define TPC0_QM_CQ_PTR_HI_2_VAL_MASK                                 0xFFFFFFFF
+
+/* TPC0_QM_CQ_TSIZE_2 */
+#define TPC0_QM_CQ_TSIZE_2_VAL_SHIFT                                 0
+#define TPC0_QM_CQ_TSIZE_2_VAL_MASK                                  0xFFFFFFFF
+
+/* TPC0_QM_CQ_CTL_2 */
+#define TPC0_QM_CQ_CTL_2_RPT_SHIFT                                   0
+#define TPC0_QM_CQ_CTL_2_RPT_MASK                                    0xFFFF
+#define TPC0_QM_CQ_CTL_2_CTL_SHIFT                                   16
+#define TPC0_QM_CQ_CTL_2_CTL_MASK                                    0xFFFF0000
+
+/* TPC0_QM_CQ_PTR_LO_3 */
+#define TPC0_QM_CQ_PTR_LO_3_VAL_SHIFT                                0
+#define TPC0_QM_CQ_PTR_LO_3_VAL_MASK                                 0xFFFFFFFF
+
+/* TPC0_QM_CQ_PTR_HI_3 */
+#define TPC0_QM_CQ_PTR_HI_3_VAL_SHIFT                                0
+#define TPC0_QM_CQ_PTR_HI_3_VAL_MASK                                 0xFFFFFFFF
+
+/* TPC0_QM_CQ_TSIZE_3 */
+#define TPC0_QM_CQ_TSIZE_3_VAL_SHIFT                                 0
+#define TPC0_QM_CQ_TSIZE_3_VAL_MASK                                  0xFFFFFFFF
+
+/* TPC0_QM_CQ_CTL_3 */
+#define TPC0_QM_CQ_CTL_3_RPT_SHIFT                                   0
+#define TPC0_QM_CQ_CTL_3_RPT_MASK                                    0xFFFF
+#define TPC0_QM_CQ_CTL_3_CTL_SHIFT                                   16
+#define TPC0_QM_CQ_CTL_3_CTL_MASK                                    0xFFFF0000
+
+/* TPC0_QM_CQ_PTR_LO_4 */
+#define TPC0_QM_CQ_PTR_LO_4_VAL_SHIFT                                0
+#define TPC0_QM_CQ_PTR_LO_4_VAL_MASK                                 0xFFFFFFFF
+
+/* TPC0_QM_CQ_PTR_HI_4 */
+#define TPC0_QM_CQ_PTR_HI_4_VAL_SHIFT                                0
+#define TPC0_QM_CQ_PTR_HI_4_VAL_MASK                                 0xFFFFFFFF
+
+/* TPC0_QM_CQ_TSIZE_4 */
+#define TPC0_QM_CQ_TSIZE_4_VAL_SHIFT                                 0
+#define TPC0_QM_CQ_TSIZE_4_VAL_MASK                                  0xFFFFFFFF
+
+/* TPC0_QM_CQ_CTL_4 */
+#define TPC0_QM_CQ_CTL_4_RPT_SHIFT                                   0
+#define TPC0_QM_CQ_CTL_4_RPT_MASK                                    0xFFFF
+#define TPC0_QM_CQ_CTL_4_CTL_SHIFT                                   16
+#define TPC0_QM_CQ_CTL_4_CTL_MASK                                    0xFFFF0000
+
+/* TPC0_QM_CQ_PTR_LO_STS */
+#define TPC0_QM_CQ_PTR_LO_STS_VAL_SHIFT                              0
+#define TPC0_QM_CQ_PTR_LO_STS_VAL_MASK                               0xFFFFFFFF
+
+/* TPC0_QM_CQ_PTR_HI_STS */
+#define TPC0_QM_CQ_PTR_HI_STS_VAL_SHIFT                              0
+#define TPC0_QM_CQ_PTR_HI_STS_VAL_MASK                               0xFFFFFFFF
+
+/* TPC0_QM_CQ_TSIZE_STS */
+#define TPC0_QM_CQ_TSIZE_STS_VAL_SHIFT                               0
+#define TPC0_QM_CQ_TSIZE_STS_VAL_MASK                                0xFFFFFFFF
+
+/* TPC0_QM_CQ_CTL_STS */
+#define TPC0_QM_CQ_CTL_STS_RPT_SHIFT                                 0
+#define TPC0_QM_CQ_CTL_STS_RPT_MASK                                  0xFFFF
+#define TPC0_QM_CQ_CTL_STS_CTL_SHIFT                                 16
+#define TPC0_QM_CQ_CTL_STS_CTL_MASK                                  0xFFFF0000
+
+/* TPC0_QM_CQ_IFIFO_CNT */
+#define TPC0_QM_CQ_IFIFO_CNT_VAL_SHIFT                               0
+#define TPC0_QM_CQ_IFIFO_CNT_VAL_MASK                                0x3
+
+/* TPC0_QM_CP_MSG_BASE0_ADDR_LO */
+#define TPC0_QM_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT                       0
+#define TPC0_QM_CP_MSG_BASE0_ADDR_LO_VAL_MASK                        0xFFFFFFFF
+
+/* TPC0_QM_CP_MSG_BASE0_ADDR_HI */
+#define TPC0_QM_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT                       0
+#define TPC0_QM_CP_MSG_BASE0_ADDR_HI_VAL_MASK                        0xFFFFFFFF
+
+/* TPC0_QM_CP_MSG_BASE1_ADDR_LO */
+#define TPC0_QM_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT                       0
+#define TPC0_QM_CP_MSG_BASE1_ADDR_LO_VAL_MASK                        0xFFFFFFFF
+
+/* TPC0_QM_CP_MSG_BASE1_ADDR_HI */
+#define TPC0_QM_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT                       0
+#define TPC0_QM_CP_MSG_BASE1_ADDR_HI_VAL_MASK                        0xFFFFFFFF
+
+/* TPC0_QM_CP_MSG_BASE2_ADDR_LO */
+#define TPC0_QM_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT                       0
+#define TPC0_QM_CP_MSG_BASE2_ADDR_LO_VAL_MASK                        0xFFFFFFFF
+
+/* TPC0_QM_CP_MSG_BASE2_ADDR_HI */
+#define TPC0_QM_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT                       0
+#define TPC0_QM_CP_MSG_BASE2_ADDR_HI_VAL_MASK                        0xFFFFFFFF
+
+/* TPC0_QM_CP_MSG_BASE3_ADDR_LO */
+#define TPC0_QM_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT                       0
+#define TPC0_QM_CP_MSG_BASE3_ADDR_LO_VAL_MASK                        0xFFFFFFFF
+
+/* TPC0_QM_CP_MSG_BASE3_ADDR_HI */
+#define TPC0_QM_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT                       0
+#define TPC0_QM_CP_MSG_BASE3_ADDR_HI_VAL_MASK                        0xFFFFFFFF
+
+/* TPC0_QM_CP_LDMA_TSIZE_OFFSET */
+#define TPC0_QM_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT                       0
+#define TPC0_QM_CP_LDMA_TSIZE_OFFSET_VAL_MASK                        0xFFFFFFFF
+
+/* TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET */
+#define TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT                 0
+#define TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK                  0xFFFFFFFF
+
+/* TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET */
+#define TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT                 0
+#define TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK                  0xFFFFFFFF
+
+/* TPC0_QM_CP_FENCE0_RDATA */
+#define TPC0_QM_CP_FENCE0_RDATA_INC_VAL_SHIFT                        0
+#define TPC0_QM_CP_FENCE0_RDATA_INC_VAL_MASK                         0xF
+
+/* TPC0_QM_CP_FENCE1_RDATA */
+#define TPC0_QM_CP_FENCE1_RDATA_INC_VAL_SHIFT                        0
+#define TPC0_QM_CP_FENCE1_RDATA_INC_VAL_MASK                         0xF
+
+/* TPC0_QM_CP_FENCE2_RDATA */
+#define TPC0_QM_CP_FENCE2_RDATA_INC_VAL_SHIFT                        0
+#define TPC0_QM_CP_FENCE2_RDATA_INC_VAL_MASK                         0xF
+
+/* TPC0_QM_CP_FENCE3_RDATA */
+#define TPC0_QM_CP_FENCE3_RDATA_INC_VAL_SHIFT                        0
+#define TPC0_QM_CP_FENCE3_RDATA_INC_VAL_MASK                         0xF
+
+/* TPC0_QM_CP_FENCE0_CNT */
+#define TPC0_QM_CP_FENCE0_CNT_VAL_SHIFT                              0
+#define TPC0_QM_CP_FENCE0_CNT_VAL_MASK                               0x3FFF
+
+/* TPC0_QM_CP_FENCE1_CNT */
+#define TPC0_QM_CP_FENCE1_CNT_VAL_SHIFT                              0
+#define TPC0_QM_CP_FENCE1_CNT_VAL_MASK                               0x3FFF
+
+/* TPC0_QM_CP_FENCE2_CNT */
+#define TPC0_QM_CP_FENCE2_CNT_VAL_SHIFT                              0
+#define TPC0_QM_CP_FENCE2_CNT_VAL_MASK                               0x3FFF
+
+/* TPC0_QM_CP_FENCE3_CNT */
+#define TPC0_QM_CP_FENCE3_CNT_VAL_SHIFT                              0
+#define TPC0_QM_CP_FENCE3_CNT_VAL_MASK                               0x3FFF
+
+/* TPC0_QM_CP_STS */
+#define TPC0_QM_CP_STS_MSG_INFLIGHT_CNT_SHIFT                        0
+#define TPC0_QM_CP_STS_MSG_INFLIGHT_CNT_MASK                         0xFFFF
+#define TPC0_QM_CP_STS_ERDY_SHIFT                                    16
+#define TPC0_QM_CP_STS_ERDY_MASK                                     0x10000
+#define TPC0_QM_CP_STS_RRDY_SHIFT                                    17
+#define TPC0_QM_CP_STS_RRDY_MASK                                     0x20000
+#define TPC0_QM_CP_STS_MRDY_SHIFT                                    18
+#define TPC0_QM_CP_STS_MRDY_MASK                                     0x40000
+#define TPC0_QM_CP_STS_SW_STOP_SHIFT                                 19
+#define TPC0_QM_CP_STS_SW_STOP_MASK                                  0x80000
+#define TPC0_QM_CP_STS_FENCE_ID_SHIFT                                20
+#define TPC0_QM_CP_STS_FENCE_ID_MASK                                 0x300000
+#define TPC0_QM_CP_STS_FENCE_IN_PROGRESS_SHIFT                       22
+#define TPC0_QM_CP_STS_FENCE_IN_PROGRESS_MASK                        0x400000
+
+/* TPC0_QM_CP_CURRENT_INST_LO */
+#define TPC0_QM_CP_CURRENT_INST_LO_VAL_SHIFT                         0
+#define TPC0_QM_CP_CURRENT_INST_LO_VAL_MASK                          0xFFFFFFFF
+
+/* TPC0_QM_CP_CURRENT_INST_HI */
+#define TPC0_QM_CP_CURRENT_INST_HI_VAL_SHIFT                         0
+#define TPC0_QM_CP_CURRENT_INST_HI_VAL_MASK                          0xFFFFFFFF
+
+/* TPC0_QM_CP_BARRIER_CFG */
+#define TPC0_QM_CP_BARRIER_CFG_EBGUARD_SHIFT                         0
+#define TPC0_QM_CP_BARRIER_CFG_EBGUARD_MASK                          0xFFF
+#define TPC0_QM_CP_BARRIER_CFG_RBGUARD_SHIFT                         16
+#define TPC0_QM_CP_BARRIER_CFG_RBGUARD_MASK                          0xF0000
+
+/* TPC0_QM_CP_DBG_0 */
+#define TPC0_QM_CP_DBG_0_CS_SHIFT                                    0
+#define TPC0_QM_CP_DBG_0_CS_MASK                                     0xF
+#define TPC0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_SHIFT                       4
+#define TPC0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_MASK                        0x10
+#define TPC0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_SHIFT                     5
+#define TPC0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_MASK                      0x20
+#define TPC0_QM_CP_DBG_0_MREB_STALL_SHIFT                            6
+#define TPC0_QM_CP_DBG_0_MREB_STALL_MASK                             0x40
+#define TPC0_QM_CP_DBG_0_STALL_SHIFT                                 7
+#define TPC0_QM_CP_DBG_0_STALL_MASK                                  0x80
+
+/* TPC0_QM_CP_ARUSER_31_11 */
+#define TPC0_QM_CP_ARUSER_31_11_VAL_SHIFT                            0
+#define TPC0_QM_CP_ARUSER_31_11_VAL_MASK                             0x1FFFFF
+
+/* TPC0_QM_CP_AWUSER_31_11 */
+#define TPC0_QM_CP_AWUSER_31_11_VAL_SHIFT                            0
+#define TPC0_QM_CP_AWUSER_31_11_VAL_MASK                             0x1FFFFF
+
+/* TPC0_QM_ARB_CFG_0 */
+#define TPC0_QM_ARB_CFG_0_TYPE_SHIFT                                 0
+#define TPC0_QM_ARB_CFG_0_TYPE_MASK                                  0x1
+#define TPC0_QM_ARB_CFG_0_IS_MASTER_SHIFT                            4
+#define TPC0_QM_ARB_CFG_0_IS_MASTER_MASK                             0x10
+#define TPC0_QM_ARB_CFG_0_EN_SHIFT                                   8
+#define TPC0_QM_ARB_CFG_0_EN_MASK                                    0x100
+#define TPC0_QM_ARB_CFG_0_MASK_SHIFT                                 12
+#define TPC0_QM_ARB_CFG_0_MASK_MASK                                  0xF000
+#define TPC0_QM_ARB_CFG_0_MST_MSG_NOSTALL_SHIFT                      16
+#define TPC0_QM_ARB_CFG_0_MST_MSG_NOSTALL_MASK                       0x10000
+
+/* TPC0_QM_ARB_CHOISE_Q_PUSH */
+#define TPC0_QM_ARB_CHOISE_Q_PUSH_VAL_SHIFT                          0
+#define TPC0_QM_ARB_CHOISE_Q_PUSH_VAL_MASK                           0x3
+
+/* TPC0_QM_ARB_WRR_WEIGHT */
+#define TPC0_QM_ARB_WRR_WEIGHT_VAL_SHIFT                             0
+#define TPC0_QM_ARB_WRR_WEIGHT_VAL_MASK                              0xFFFFFFFF
+
+/* TPC0_QM_ARB_CFG_1 */
+#define TPC0_QM_ARB_CFG_1_CLR_SHIFT                                  0
+#define TPC0_QM_ARB_CFG_1_CLR_MASK                                   0x1
+
+/* TPC0_QM_ARB_MST_AVAIL_CRED */
+#define TPC0_QM_ARB_MST_AVAIL_CRED_VAL_SHIFT                         0
+#define TPC0_QM_ARB_MST_AVAIL_CRED_VAL_MASK                          0x7F
+
+/* TPC0_QM_ARB_MST_CRED_INC */
+#define TPC0_QM_ARB_MST_CRED_INC_VAL_SHIFT                           0
+#define TPC0_QM_ARB_MST_CRED_INC_VAL_MASK                            0xFFFFFFFF
+
+/* TPC0_QM_ARB_MST_CHOISE_PUSH_OFST */
+#define TPC0_QM_ARB_MST_CHOISE_PUSH_OFST_VAL_SHIFT                   0
+#define TPC0_QM_ARB_MST_CHOISE_PUSH_OFST_VAL_MASK                    0xFFFFFFFF
+
+/* TPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST */
+#define TPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_SHIFT               0
+#define TPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_MASK                0xFFFFFFFF
+
+/* TPC0_QM_ARB_MST_SLAVE_EN */
+#define TPC0_QM_ARB_MST_SLAVE_EN_VAL_SHIFT                           0
+#define TPC0_QM_ARB_MST_SLAVE_EN_VAL_MASK                            0xFFFFFFFF
+
+/* TPC0_QM_ARB_MST_QUIET_PER */
+#define TPC0_QM_ARB_MST_QUIET_PER_VAL_SHIFT                          0
+#define TPC0_QM_ARB_MST_QUIET_PER_VAL_MASK                           0xFFFFFFFF
+
+/* TPC0_QM_ARB_SLV_CHOISE_WDT */
+#define TPC0_QM_ARB_SLV_CHOISE_WDT_VAL_SHIFT                         0
+#define TPC0_QM_ARB_SLV_CHOISE_WDT_VAL_MASK                          0xFFFFFFFF
+
+/* TPC0_QM_ARB_SLV_ID */
+#define TPC0_QM_ARB_SLV_ID_VAL_SHIFT                                 0
+#define TPC0_QM_ARB_SLV_ID_VAL_MASK                                  0x1F
+
+/* TPC0_QM_ARB_MSG_MAX_INFLIGHT */
+#define TPC0_QM_ARB_MSG_MAX_INFLIGHT_VAL_SHIFT                       0
+#define TPC0_QM_ARB_MSG_MAX_INFLIGHT_VAL_MASK                        0x3F
+
+/* TPC0_QM_ARB_MSG_AWUSER_31_11 */
+#define TPC0_QM_ARB_MSG_AWUSER_31_11_VAL_SHIFT                       0
+#define TPC0_QM_ARB_MSG_AWUSER_31_11_VAL_MASK                        0x1FFFFF
+
+/* TPC0_QM_ARB_MSG_AWUSER_SEC_PROP */
+#define TPC0_QM_ARB_MSG_AWUSER_SEC_PROP_ASID_SHIFT                   0
+#define TPC0_QM_ARB_MSG_AWUSER_SEC_PROP_ASID_MASK                    0x3FF
+#define TPC0_QM_ARB_MSG_AWUSER_SEC_PROP_MMBP_SHIFT                   10
+#define TPC0_QM_ARB_MSG_AWUSER_SEC_PROP_MMBP_MASK                    0x400
+
+/* TPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP */
+#define TPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_SHIFT               0
+#define TPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_MASK                0x3FF
+#define TPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_SHIFT               10
+#define TPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_MASK                0x400
+
+/* TPC0_QM_ARB_BASE_LO */
+#define TPC0_QM_ARB_BASE_LO_VAL_SHIFT                                0
+#define TPC0_QM_ARB_BASE_LO_VAL_MASK                                 0xFFFFFFFF
+
+/* TPC0_QM_ARB_BASE_HI */
+#define TPC0_QM_ARB_BASE_HI_VAL_SHIFT                                0
+#define TPC0_QM_ARB_BASE_HI_VAL_MASK                                 0xFFFFFFFF
+
+/* TPC0_QM_ARB_STATE_STS */
+#define TPC0_QM_ARB_STATE_STS_VAL_SHIFT                              0
+#define TPC0_QM_ARB_STATE_STS_VAL_MASK                               0xFFFFFFFF
+
+/* TPC0_QM_ARB_CHOISE_FULLNESS_STS */
+#define TPC0_QM_ARB_CHOISE_FULLNESS_STS_VAL_SHIFT                    0
+#define TPC0_QM_ARB_CHOISE_FULLNESS_STS_VAL_MASK                     0x7F
+
+/* TPC0_QM_ARB_MSG_STS */
+#define TPC0_QM_ARB_MSG_STS_FULL_SHIFT                               0
+#define TPC0_QM_ARB_MSG_STS_FULL_MASK                                0x1
+#define TPC0_QM_ARB_MSG_STS_NO_INFLIGHT_SHIFT                        1
+#define TPC0_QM_ARB_MSG_STS_NO_INFLIGHT_MASK                         0x2
+
+/* TPC0_QM_ARB_SLV_CHOISE_Q_HEAD */
+#define TPC0_QM_ARB_SLV_CHOISE_Q_HEAD_VAL_SHIFT                      0
+#define TPC0_QM_ARB_SLV_CHOISE_Q_HEAD_VAL_MASK                       0x3
+
+/* TPC0_QM_ARB_ERR_CAUSE */
+#define TPC0_QM_ARB_ERR_CAUSE_CHOISE_OVF_SHIFT                       0
+#define TPC0_QM_ARB_ERR_CAUSE_CHOISE_OVF_MASK                        0x1
+#define TPC0_QM_ARB_ERR_CAUSE_CHOISE_WDT_SHIFT                       1
+#define TPC0_QM_ARB_ERR_CAUSE_CHOISE_WDT_MASK                        0x2
+#define TPC0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_SHIFT                      2
+#define TPC0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_MASK                       0x4
+
+/* TPC0_QM_ARB_ERR_MSG_EN */
+#define TPC0_QM_ARB_ERR_MSG_EN_CHOISE_OVF_SHIFT                      0
+#define TPC0_QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK                       0x1
+#define TPC0_QM_ARB_ERR_MSG_EN_CHOISE_WDT_SHIFT                      1
+#define TPC0_QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK                       0x2
+#define TPC0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_SHIFT                     2
+#define TPC0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK                      0x4
+
+/* TPC0_QM_ARB_ERR_STS_DRP */
+#define TPC0_QM_ARB_ERR_STS_DRP_VAL_SHIFT                            0
+#define TPC0_QM_ARB_ERR_STS_DRP_VAL_MASK                             0x3
+
+/* TPC0_QM_ARB_MST_CRED_STS */
+#define TPC0_QM_ARB_MST_CRED_STS_VAL_SHIFT                           0
+#define TPC0_QM_ARB_MST_CRED_STS_VAL_MASK                            0x7F
+
+/* TPC0_QM_CGM_CFG */
+#define TPC0_QM_CGM_CFG_IDLE_TH_SHIFT                                0
+#define TPC0_QM_CGM_CFG_IDLE_TH_MASK                                 0xFFF
+#define TPC0_QM_CGM_CFG_G2F_TH_SHIFT                                 16
+#define TPC0_QM_CGM_CFG_G2F_TH_MASK                                  0xFF0000
+#define TPC0_QM_CGM_CFG_CP_IDLE_MASK_SHIFT                           24
+#define TPC0_QM_CGM_CFG_CP_IDLE_MASK_MASK                            0x1F000000
+#define TPC0_QM_CGM_CFG_EN_SHIFT                                     31
+#define TPC0_QM_CGM_CFG_EN_MASK                                      0x80000000
+
+/* TPC0_QM_CGM_STS */
+#define TPC0_QM_CGM_STS_ST_SHIFT                                     0
+#define TPC0_QM_CGM_STS_ST_MASK                                      0x3
+#define TPC0_QM_CGM_STS_CG_SHIFT                                     4
+#define TPC0_QM_CGM_STS_CG_MASK                                      0x10
+#define TPC0_QM_CGM_STS_AGENT_IDLE_SHIFT                             8
+#define TPC0_QM_CGM_STS_AGENT_IDLE_MASK                              0x100
+#define TPC0_QM_CGM_STS_AXI_IDLE_SHIFT                               9
+#define TPC0_QM_CGM_STS_AXI_IDLE_MASK                                0x200
+#define TPC0_QM_CGM_STS_CP_IDLE_SHIFT                                10
+#define TPC0_QM_CGM_STS_CP_IDLE_MASK                                 0x400
+
+/* TPC0_QM_CGM_CFG1 */
+#define TPC0_QM_CGM_CFG1_MASK_TH_SHIFT                               0
+#define TPC0_QM_CGM_CFG1_MASK_TH_MASK                                0xFF
+
+/* TPC0_QM_LOCAL_RANGE_BASE */
+#define TPC0_QM_LOCAL_RANGE_BASE_VAL_SHIFT                           0
+#define TPC0_QM_LOCAL_RANGE_BASE_VAL_MASK                            0xFFFF
+
+/* TPC0_QM_LOCAL_RANGE_SIZE */
+#define TPC0_QM_LOCAL_RANGE_SIZE_VAL_SHIFT                           0
+#define TPC0_QM_LOCAL_RANGE_SIZE_VAL_MASK                            0xFFFF
+
+/* TPC0_QM_CSMR_STRICT_PRIO_CFG */
+#define TPC0_QM_CSMR_STRICT_PRIO_CFG_TYPE_SHIFT                      0
+#define TPC0_QM_CSMR_STRICT_PRIO_CFG_TYPE_MASK                       0x1
+
+/* TPC0_QM_HBW_RD_RATE_LIM_CFG_1 */
+#define TPC0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_SHIFT                     0
+#define TPC0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_MASK                      0xFF
+#define TPC0_QM_HBW_RD_RATE_LIM_CFG_1_EN_SHIFT                       31
+#define TPC0_QM_HBW_RD_RATE_LIM_CFG_1_EN_MASK                        0x80000000
+
+/* TPC0_QM_LBW_WR_RATE_LIM_CFG_0 */
+#define TPC0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT                0
+#define TPC0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK                 0xFF
+#define TPC0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_SHIFT                      16
+#define TPC0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_MASK                       0xFF0000
+
+/* TPC0_QM_LBW_WR_RATE_LIM_CFG_1 */
+#define TPC0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_SHIFT                     0
+#define TPC0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_MASK                      0xFF
+#define TPC0_QM_LBW_WR_RATE_LIM_CFG_1_EN_SHIFT                       31
+#define TPC0_QM_LBW_WR_RATE_LIM_CFG_1_EN_MASK                        0x80000000
+
+/* TPC0_QM_HBW_RD_RATE_LIM_CFG_0 */
+#define TPC0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT                0
+#define TPC0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK                 0xFF
+#define TPC0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_SHIFT                      16
+#define TPC0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_MASK                       0xFF0000
+
+/* TPC0_QM_GLBL_AXCACHE */
+#define TPC0_QM_GLBL_AXCACHE_AR_SHIFT                                0
+#define TPC0_QM_GLBL_AXCACHE_AR_MASK                                 0xF
+#define TPC0_QM_GLBL_AXCACHE_AW_SHIFT                                16
+#define TPC0_QM_GLBL_AXCACHE_AW_MASK                                 0xF0000
+
+/* TPC0_QM_IND_GW_APB_CFG */
+#define TPC0_QM_IND_GW_APB_CFG_ADDR_SHIFT                            0
+#define TPC0_QM_IND_GW_APB_CFG_ADDR_MASK                             0x7FFFFFFF
+#define TPC0_QM_IND_GW_APB_CFG_CMD_SHIFT                             31
+#define TPC0_QM_IND_GW_APB_CFG_CMD_MASK                              0x80000000
+
+/* TPC0_QM_IND_GW_APB_WDATA */
+#define TPC0_QM_IND_GW_APB_WDATA_VAL_SHIFT                           0
+#define TPC0_QM_IND_GW_APB_WDATA_VAL_MASK                            0xFFFFFFFF
+
+/* TPC0_QM_IND_GW_APB_RDATA */
+#define TPC0_QM_IND_GW_APB_RDATA_VAL_SHIFT                           0
+#define TPC0_QM_IND_GW_APB_RDATA_VAL_MASK                            0xFFFFFFFF
+
+/* TPC0_QM_IND_GW_APB_STATUS */
+#define TPC0_QM_IND_GW_APB_STATUS_RDY_SHIFT                          0
+#define TPC0_QM_IND_GW_APB_STATUS_RDY_MASK                           0x1
+#define TPC0_QM_IND_GW_APB_STATUS_ERR_SHIFT                          1
+#define TPC0_QM_IND_GW_APB_STATUS_ERR_MASK                           0x2
+
+/* TPC0_QM_GLBL_ERR_ADDR_LO */
+#define TPC0_QM_GLBL_ERR_ADDR_LO_VAL_SHIFT                           0
+#define TPC0_QM_GLBL_ERR_ADDR_LO_VAL_MASK                            0xFFFFFFFF
+
+/* TPC0_QM_GLBL_ERR_ADDR_HI */
+#define TPC0_QM_GLBL_ERR_ADDR_HI_VAL_SHIFT                           0
+#define TPC0_QM_GLBL_ERR_ADDR_HI_VAL_MASK                            0xFFFFFFFF
+
+/* TPC0_QM_GLBL_ERR_WDATA */
+#define TPC0_QM_GLBL_ERR_WDATA_VAL_SHIFT                             0
+#define TPC0_QM_GLBL_ERR_WDATA_VAL_MASK                              0xFFFFFFFF
+
+/* TPC0_QM_GLBL_MEM_INIT_BUSY */
+#define TPC0_QM_GLBL_MEM_INIT_BUSY_RBUF_SHIFT                        0
+#define TPC0_QM_GLBL_MEM_INIT_BUSY_RBUF_MASK                         0xF
+
+#endif /* ASIC_REG_TPC0_QM_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc0_qm_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc0_qm_regs.h
new file mode 100644
index 000000000000..f9e310ab6df2
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc0_qm_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_TPC0_QM_REGS_H_
+#define ASIC_REG_TPC0_QM_REGS_H_
+
+/*
+ *****************************************
+ *   TPC0_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmTPC0_QM_GLBL_CFG0                                          0xE08000
+
+#define mmTPC0_QM_GLBL_CFG1                                          0xE08004
+
+#define mmTPC0_QM_GLBL_PROT                                          0xE08008
+
+#define mmTPC0_QM_GLBL_ERR_CFG                                       0xE0800C
+
+#define mmTPC0_QM_GLBL_SECURE_PROPS_0                                0xE08010
+
+#define mmTPC0_QM_GLBL_SECURE_PROPS_1                                0xE08014
+
+#define mmTPC0_QM_GLBL_SECURE_PROPS_2                                0xE08018
+
+#define mmTPC0_QM_GLBL_SECURE_PROPS_3                                0xE0801C
+
+#define mmTPC0_QM_GLBL_SECURE_PROPS_4                                0xE08020
+
+#define mmTPC0_QM_GLBL_NON_SECURE_PROPS_0                            0xE08024
+
+#define mmTPC0_QM_GLBL_NON_SECURE_PROPS_1                            0xE08028
+
+#define mmTPC0_QM_GLBL_NON_SECURE_PROPS_2                            0xE0802C
+
+#define mmTPC0_QM_GLBL_NON_SECURE_PROPS_3                            0xE08030
+
+#define mmTPC0_QM_GLBL_NON_SECURE_PROPS_4                            0xE08034
+
+#define mmTPC0_QM_GLBL_STS0                                          0xE08038
+
+#define mmTPC0_QM_GLBL_STS1_0                                        0xE08040
+
+#define mmTPC0_QM_GLBL_STS1_1                                        0xE08044
+
+#define mmTPC0_QM_GLBL_STS1_2                                        0xE08048
+
+#define mmTPC0_QM_GLBL_STS1_3                                        0xE0804C
+
+#define mmTPC0_QM_GLBL_STS1_4                                        0xE08050
+
+#define mmTPC0_QM_GLBL_MSG_EN_0                                      0xE08054
+
+#define mmTPC0_QM_GLBL_MSG_EN_1                                      0xE08058
+
+#define mmTPC0_QM_GLBL_MSG_EN_2                                      0xE0805C
+
+#define mmTPC0_QM_GLBL_MSG_EN_3                                      0xE08060
+
+#define mmTPC0_QM_GLBL_MSG_EN_4                                      0xE08068
+
+#define mmTPC0_QM_PQ_BASE_LO_0                                       0xE08070
+
+#define mmTPC0_QM_PQ_BASE_LO_1                                       0xE08074
+
+#define mmTPC0_QM_PQ_BASE_LO_2                                       0xE08078
+
+#define mmTPC0_QM_PQ_BASE_LO_3                                       0xE0807C
+
+#define mmTPC0_QM_PQ_BASE_HI_0                                       0xE08080
+
+#define mmTPC0_QM_PQ_BASE_HI_1                                       0xE08084
+
+#define mmTPC0_QM_PQ_BASE_HI_2                                       0xE08088
+
+#define mmTPC0_QM_PQ_BASE_HI_3                                       0xE0808C
+
+#define mmTPC0_QM_PQ_SIZE_0                                          0xE08090
+
+#define mmTPC0_QM_PQ_SIZE_1                                          0xE08094
+
+#define mmTPC0_QM_PQ_SIZE_2                                          0xE08098
+
+#define mmTPC0_QM_PQ_SIZE_3                                          0xE0809C
+
+#define mmTPC0_QM_PQ_PI_0                                            0xE080A0
+
+#define mmTPC0_QM_PQ_PI_1                                            0xE080A4
+
+#define mmTPC0_QM_PQ_PI_2                                            0xE080A8
+
+#define mmTPC0_QM_PQ_PI_3                                            0xE080AC
+
+#define mmTPC0_QM_PQ_CI_0                                            0xE080B0
+
+#define mmTPC0_QM_PQ_CI_1                                            0xE080B4
+
+#define mmTPC0_QM_PQ_CI_2                                            0xE080B8
+
+#define mmTPC0_QM_PQ_CI_3                                            0xE080BC
+
+#define mmTPC0_QM_PQ_CFG0_0                                          0xE080C0
+
+#define mmTPC0_QM_PQ_CFG0_1                                          0xE080C4
+
+#define mmTPC0_QM_PQ_CFG0_2                                          0xE080C8
+
+#define mmTPC0_QM_PQ_CFG0_3                                          0xE080CC
+
+#define mmTPC0_QM_PQ_CFG1_0                                          0xE080D0
+
+#define mmTPC0_QM_PQ_CFG1_1                                          0xE080D4
+
+#define mmTPC0_QM_PQ_CFG1_2                                          0xE080D8
+
+#define mmTPC0_QM_PQ_CFG1_3                                          0xE080DC
+
+#define mmTPC0_QM_PQ_ARUSER_31_11_0                                  0xE080E0
+
+#define mmTPC0_QM_PQ_ARUSER_31_11_1                                  0xE080E4
+
+#define mmTPC0_QM_PQ_ARUSER_31_11_2                                  0xE080E8
+
+#define mmTPC0_QM_PQ_ARUSER_31_11_3                                  0xE080EC
+
+#define mmTPC0_QM_PQ_STS0_0                                          0xE080F0
+
+#define mmTPC0_QM_PQ_STS0_1                                          0xE080F4
+
+#define mmTPC0_QM_PQ_STS0_2                                          0xE080F8
+
+#define mmTPC0_QM_PQ_STS0_3                                          0xE080FC
+
+#define mmTPC0_QM_PQ_STS1_0                                          0xE08100
+
+#define mmTPC0_QM_PQ_STS1_1                                          0xE08104
+
+#define mmTPC0_QM_PQ_STS1_2                                          0xE08108
+
+#define mmTPC0_QM_PQ_STS1_3                                          0xE0810C
+
+#define mmTPC0_QM_CQ_CFG0_0                                          0xE08110
+
+#define mmTPC0_QM_CQ_CFG0_1                                          0xE08114
+
+#define mmTPC0_QM_CQ_CFG0_2                                          0xE08118
+
+#define mmTPC0_QM_CQ_CFG0_3                                          0xE0811C
+
+#define mmTPC0_QM_CQ_CFG0_4                                          0xE08120
+
+#define mmTPC0_QM_CQ_CFG1_0                                          0xE08124
+
+#define mmTPC0_QM_CQ_CFG1_1                                          0xE08128
+
+#define mmTPC0_QM_CQ_CFG1_2                                          0xE0812C
+
+#define mmTPC0_QM_CQ_CFG1_3                                          0xE08130
+
+#define mmTPC0_QM_CQ_CFG1_4                                          0xE08134
+
+#define mmTPC0_QM_CQ_ARUSER_31_11_0                                  0xE08138
+
+#define mmTPC0_QM_CQ_ARUSER_31_11_1                                  0xE0813C
+
+#define mmTPC0_QM_CQ_ARUSER_31_11_2                                  0xE08140
+
+#define mmTPC0_QM_CQ_ARUSER_31_11_3                                  0xE08144
+
+#define mmTPC0_QM_CQ_ARUSER_31_11_4                                  0xE08148
+
+#define mmTPC0_QM_CQ_STS0_0                                          0xE0814C
+
+#define mmTPC0_QM_CQ_STS0_1                                          0xE08150
+
+#define mmTPC0_QM_CQ_STS0_2                                          0xE08154
+
+#define mmTPC0_QM_CQ_STS0_3                                          0xE08158
+
+#define mmTPC0_QM_CQ_STS0_4                                          0xE0815C
+
+#define mmTPC0_QM_CQ_STS1_0                                          0xE08160
+
+#define mmTPC0_QM_CQ_STS1_1                                          0xE08164
+
+#define mmTPC0_QM_CQ_STS1_2                                          0xE08168
+
+#define mmTPC0_QM_CQ_STS1_3                                          0xE0816C
+
+#define mmTPC0_QM_CQ_STS1_4                                          0xE08170
+
+#define mmTPC0_QM_CQ_PTR_LO_0                                        0xE08174
+
+#define mmTPC0_QM_CQ_PTR_HI_0                                        0xE08178
+
+#define mmTPC0_QM_CQ_TSIZE_0                                         0xE0817C
+
+#define mmTPC0_QM_CQ_CTL_0                                           0xE08180
+
+#define mmTPC0_QM_CQ_PTR_LO_1                                        0xE08184
+
+#define mmTPC0_QM_CQ_PTR_HI_1                                        0xE08188
+
+#define mmTPC0_QM_CQ_TSIZE_1                                         0xE0818C
+
+#define mmTPC0_QM_CQ_CTL_1                                           0xE08190
+
+#define mmTPC0_QM_CQ_PTR_LO_2                                        0xE08194
+
+#define mmTPC0_QM_CQ_PTR_HI_2                                        0xE08198
+
+#define mmTPC0_QM_CQ_TSIZE_2                                         0xE0819C
+
+#define mmTPC0_QM_CQ_CTL_2                                           0xE081A0
+
+#define mmTPC0_QM_CQ_PTR_LO_3                                        0xE081A4
+
+#define mmTPC0_QM_CQ_PTR_HI_3                                        0xE081A8
+
+#define mmTPC0_QM_CQ_TSIZE_3                                         0xE081AC
+
+#define mmTPC0_QM_CQ_CTL_3                                           0xE081B0
+
+#define mmTPC0_QM_CQ_PTR_LO_4                                        0xE081B4
+
+#define mmTPC0_QM_CQ_PTR_HI_4                                        0xE081B8
+
+#define mmTPC0_QM_CQ_TSIZE_4                                         0xE081BC
+
+#define mmTPC0_QM_CQ_CTL_4                                           0xE081C0
+
+#define mmTPC0_QM_CQ_PTR_LO_STS_0                                    0xE081C4
+
+#define mmTPC0_QM_CQ_PTR_LO_STS_1                                    0xE081C8
+
+#define mmTPC0_QM_CQ_PTR_LO_STS_2                                    0xE081CC
+
+#define mmTPC0_QM_CQ_PTR_LO_STS_3                                    0xE081D0
+
+#define mmTPC0_QM_CQ_PTR_LO_STS_4                                    0xE081D4
+
+#define mmTPC0_QM_CQ_PTR_HI_STS_0                                    0xE081D8
+
+#define mmTPC0_QM_CQ_PTR_HI_STS_1                                    0xE081DC
+
+#define mmTPC0_QM_CQ_PTR_HI_STS_2                                    0xE081E0
+
+#define mmTPC0_QM_CQ_PTR_HI_STS_3                                    0xE081E4
+
+#define mmTPC0_QM_CQ_PTR_HI_STS_4                                    0xE081E8
+
+#define mmTPC0_QM_CQ_TSIZE_STS_0                                     0xE081EC
+
+#define mmTPC0_QM_CQ_TSIZE_STS_1                                     0xE081F0
+
+#define mmTPC0_QM_CQ_TSIZE_STS_2                                     0xE081F4
+
+#define mmTPC0_QM_CQ_TSIZE_STS_3                                     0xE081F8
+
+#define mmTPC0_QM_CQ_TSIZE_STS_4                                     0xE081FC
+
+#define mmTPC0_QM_CQ_CTL_STS_0                                       0xE08200
+
+#define mmTPC0_QM_CQ_CTL_STS_1                                       0xE08204
+
+#define mmTPC0_QM_CQ_CTL_STS_2                                       0xE08208
+
+#define mmTPC0_QM_CQ_CTL_STS_3                                       0xE0820C
+
+#define mmTPC0_QM_CQ_CTL_STS_4                                       0xE08210
+
+#define mmTPC0_QM_CQ_IFIFO_CNT_0                                     0xE08214
+
+#define mmTPC0_QM_CQ_IFIFO_CNT_1                                     0xE08218
+
+#define mmTPC0_QM_CQ_IFIFO_CNT_2                                     0xE0821C
+
+#define mmTPC0_QM_CQ_IFIFO_CNT_3                                     0xE08220
+
+#define mmTPC0_QM_CQ_IFIFO_CNT_4                                     0xE08224
+
+#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_0                             0xE08228
+
+#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_1                             0xE0822C
+
+#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_2                             0xE08230
+
+#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_3                             0xE08234
+
+#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_4                             0xE08238
+
+#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_0                             0xE0823C
+
+#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_1                             0xE08240
+
+#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_2                             0xE08244
+
+#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_3                             0xE08248
+
+#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_4                             0xE0824C
+
+#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_0                             0xE08250
+
+#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_1                             0xE08254
+
+#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_2                             0xE08258
+
+#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_3                             0xE0825C
+
+#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_4                             0xE08260
+
+#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_0                             0xE08264
+
+#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_1                             0xE08268
+
+#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_2                             0xE0826C
+
+#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_3                             0xE08270
+
+#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_4                             0xE08274
+
+#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_0                             0xE08278
+
+#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_1                             0xE0827C
+
+#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_2                             0xE08280
+
+#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_3                             0xE08284
+
+#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_4                             0xE08288
+
+#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_0                             0xE0828C
+
+#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_1                             0xE08290
+
+#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_2                             0xE08294
+
+#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_3                             0xE08298
+
+#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_4                             0xE0829C
+
+#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_0                             0xE082A0
+
+#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_1                             0xE082A4
+
+#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_2                             0xE082A8
+
+#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_3                             0xE082AC
+
+#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_4                             0xE082B0
+
+#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_0                             0xE082B4
+
+#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_1                             0xE082B8
+
+#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_2                             0xE082BC
+
+#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_3                             0xE082C0
+
+#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_4                             0xE082C4
+
+#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_0                             0xE082C8
+
+#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_1                             0xE082CC
+
+#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_2                             0xE082D0
+
+#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_3                             0xE082D4
+
+#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_4                             0xE082D8
+
+#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0                       0xE082E0
+
+#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1                       0xE082E4
+
+#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2                       0xE082E8
+
+#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3                       0xE082EC
+
+#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4                       0xE082F0
+
+#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0                       0xE082F4
+
+#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1                       0xE082F8
+
+#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2                       0xE082FC
+
+#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3                       0xE08300
+
+#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4                       0xE08304
+
+#define mmTPC0_QM_CP_FENCE0_RDATA_0                                  0xE08308
+
+#define mmTPC0_QM_CP_FENCE0_RDATA_1                                  0xE0830C
+
+#define mmTPC0_QM_CP_FENCE0_RDATA_2                                  0xE08310
+
+#define mmTPC0_QM_CP_FENCE0_RDATA_3                                  0xE08314
+
+#define mmTPC0_QM_CP_FENCE0_RDATA_4                                  0xE08318
+
+#define mmTPC0_QM_CP_FENCE1_RDATA_0                                  0xE0831C
+
+#define mmTPC0_QM_CP_FENCE1_RDATA_1                                  0xE08320
+
+#define mmTPC0_QM_CP_FENCE1_RDATA_2                                  0xE08324
+
+#define mmTPC0_QM_CP_FENCE1_RDATA_3                                  0xE08328
+
+#define mmTPC0_QM_CP_FENCE1_RDATA_4                                  0xE0832C
+
+#define mmTPC0_QM_CP_FENCE2_RDATA_0                                  0xE08330
+
+#define mmTPC0_QM_CP_FENCE2_RDATA_1                                  0xE08334
+
+#define mmTPC0_QM_CP_FENCE2_RDATA_2                                  0xE08338
+
+#define mmTPC0_QM_CP_FENCE2_RDATA_3                                  0xE0833C
+
+#define mmTPC0_QM_CP_FENCE2_RDATA_4                                  0xE08340
+
+#define mmTPC0_QM_CP_FENCE3_RDATA_0                                  0xE08344
+
+#define mmTPC0_QM_CP_FENCE3_RDATA_1                                  0xE08348
+
+#define mmTPC0_QM_CP_FENCE3_RDATA_2                                  0xE0834C
+
+#define mmTPC0_QM_CP_FENCE3_RDATA_3                                  0xE08350
+
+#define mmTPC0_QM_CP_FENCE3_RDATA_4                                  0xE08354
+
+#define mmTPC0_QM_CP_FENCE0_CNT_0                                    0xE08358
+
+#define mmTPC0_QM_CP_FENCE0_CNT_1                                    0xE0835C
+
+#define mmTPC0_QM_CP_FENCE0_CNT_2                                    0xE08360
+
+#define mmTPC0_QM_CP_FENCE0_CNT_3                                    0xE08364
+
+#define mmTPC0_QM_CP_FENCE0_CNT_4                                    0xE08368
+
+#define mmTPC0_QM_CP_FENCE1_CNT_0                                    0xE0836C
+
+#define mmTPC0_QM_CP_FENCE1_CNT_1                                    0xE08370
+
+#define mmTPC0_QM_CP_FENCE1_CNT_2                                    0xE08374
+
+#define mmTPC0_QM_CP_FENCE1_CNT_3                                    0xE08378
+
+#define mmTPC0_QM_CP_FENCE1_CNT_4                                    0xE0837C
+
+#define mmTPC0_QM_CP_FENCE2_CNT_0                                    0xE08380
+
+#define mmTPC0_QM_CP_FENCE2_CNT_1                                    0xE08384
+
+#define mmTPC0_QM_CP_FENCE2_CNT_2                                    0xE08388
+
+#define mmTPC0_QM_CP_FENCE2_CNT_3                                    0xE0838C
+
+#define mmTPC0_QM_CP_FENCE2_CNT_4                                    0xE08390
+
+#define mmTPC0_QM_CP_FENCE3_CNT_0                                    0xE08394
+
+#define mmTPC0_QM_CP_FENCE3_CNT_1                                    0xE08398
+
+#define mmTPC0_QM_CP_FENCE3_CNT_2                                    0xE0839C
+
+#define mmTPC0_QM_CP_FENCE3_CNT_3                                    0xE083A0
+
+#define mmTPC0_QM_CP_FENCE3_CNT_4                                    0xE083A4
+
+#define mmTPC0_QM_CP_STS_0                                           0xE083A8
+
+#define mmTPC0_QM_CP_STS_1                                           0xE083AC
+
+#define mmTPC0_QM_CP_STS_2                                           0xE083B0
+
+#define mmTPC0_QM_CP_STS_3                                           0xE083B4
+
+#define mmTPC0_QM_CP_STS_4                                           0xE083B8
+
+#define mmTPC0_QM_CP_CURRENT_INST_LO_0                               0xE083BC
+
+#define mmTPC0_QM_CP_CURRENT_INST_LO_1                               0xE083C0
+
+#define mmTPC0_QM_CP_CURRENT_INST_LO_2                               0xE083C4
+
+#define mmTPC0_QM_CP_CURRENT_INST_LO_3                               0xE083C8
+
+#define mmTPC0_QM_CP_CURRENT_INST_LO_4                               0xE083CC
+
+#define mmTPC0_QM_CP_CURRENT_INST_HI_0                               0xE083D0
+
+#define mmTPC0_QM_CP_CURRENT_INST_HI_1                               0xE083D4
+
+#define mmTPC0_QM_CP_CURRENT_INST_HI_2                               0xE083D8
+
+#define mmTPC0_QM_CP_CURRENT_INST_HI_3                               0xE083DC
+
+#define mmTPC0_QM_CP_CURRENT_INST_HI_4                               0xE083E0
+
+#define mmTPC0_QM_CP_BARRIER_CFG_0                                   0xE083F4
+
+#define mmTPC0_QM_CP_BARRIER_CFG_1                                   0xE083F8
+
+#define mmTPC0_QM_CP_BARRIER_CFG_2                                   0xE083FC
+
+#define mmTPC0_QM_CP_BARRIER_CFG_3                                   0xE08400
+
+#define mmTPC0_QM_CP_BARRIER_CFG_4                                   0xE08404
+
+#define mmTPC0_QM_CP_DBG_0_0                                         0xE08408
+
+#define mmTPC0_QM_CP_DBG_0_1                                         0xE0840C
+
+#define mmTPC0_QM_CP_DBG_0_2                                         0xE08410
+
+#define mmTPC0_QM_CP_DBG_0_3                                         0xE08414
+
+#define mmTPC0_QM_CP_DBG_0_4                                         0xE08418
+
+#define mmTPC0_QM_CP_ARUSER_31_11_0                                  0xE0841C
+
+#define mmTPC0_QM_CP_ARUSER_31_11_1                                  0xE08420
+
+#define mmTPC0_QM_CP_ARUSER_31_11_2                                  0xE08424
+
+#define mmTPC0_QM_CP_ARUSER_31_11_3                                  0xE08428
+
+#define mmTPC0_QM_CP_ARUSER_31_11_4                                  0xE0842C
+
+#define mmTPC0_QM_CP_AWUSER_31_11_0                                  0xE08430
+
+#define mmTPC0_QM_CP_AWUSER_31_11_1                                  0xE08434
+
+#define mmTPC0_QM_CP_AWUSER_31_11_2                                  0xE08438
+
+#define mmTPC0_QM_CP_AWUSER_31_11_3                                  0xE0843C
+
+#define mmTPC0_QM_CP_AWUSER_31_11_4                                  0xE08440
+
+#define mmTPC0_QM_ARB_CFG_0                                          0xE08A00
+
+#define mmTPC0_QM_ARB_CHOISE_Q_PUSH                                  0xE08A04
+
+#define mmTPC0_QM_ARB_WRR_WEIGHT_0                                   0xE08A08
+
+#define mmTPC0_QM_ARB_WRR_WEIGHT_1                                   0xE08A0C
+
+#define mmTPC0_QM_ARB_WRR_WEIGHT_2                                   0xE08A10
+
+#define mmTPC0_QM_ARB_WRR_WEIGHT_3                                   0xE08A14
+
+#define mmTPC0_QM_ARB_CFG_1                                          0xE08A18
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_0                               0xE08A20
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_1                               0xE08A24
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_2                               0xE08A28
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_3                               0xE08A2C
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_4                               0xE08A30
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_5                               0xE08A34
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_6                               0xE08A38
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_7                               0xE08A3C
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_8                               0xE08A40
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_9                               0xE08A44
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_10                              0xE08A48
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_11                              0xE08A4C
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_12                              0xE08A50
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_13                              0xE08A54
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_14                              0xE08A58
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_15                              0xE08A5C
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_16                              0xE08A60
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_17                              0xE08A64
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_18                              0xE08A68
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_19                              0xE08A6C
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_20                              0xE08A70
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_21                              0xE08A74
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_22                              0xE08A78
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_23                              0xE08A7C
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_24                              0xE08A80
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_25                              0xE08A84
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_26                              0xE08A88
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_27                              0xE08A8C
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_28                              0xE08A90
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_29                              0xE08A94
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_30                              0xE08A98
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_31                              0xE08A9C
+
+#define mmTPC0_QM_ARB_MST_CRED_INC                                   0xE08AA0
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_0                         0xE08AA4
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_1                         0xE08AA8
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_2                         0xE08AAC
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_3                         0xE08AB0
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_4                         0xE08AB4
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_5                         0xE08AB8
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_6                         0xE08ABC
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_7                         0xE08AC0
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_8                         0xE08AC4
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_9                         0xE08AC8
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_10                        0xE08ACC
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_11                        0xE08AD0
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_12                        0xE08AD4
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_13                        0xE08AD8
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_14                        0xE08ADC
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_15                        0xE08AE0
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_16                        0xE08AE4
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_17                        0xE08AE8
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_18                        0xE08AEC
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_19                        0xE08AF0
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_20                        0xE08AF4
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_21                        0xE08AF8
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_22                        0xE08AFC
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_23                        0xE08B00
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_24                        0xE08B04
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_25                        0xE08B08
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_26                        0xE08B0C
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_27                        0xE08B10
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_28                        0xE08B14
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_29                        0xE08B18
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_30                        0xE08B1C
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_31                        0xE08B20
+
+#define mmTPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST                       0xE08B28
+
+#define mmTPC0_QM_ARB_MST_SLAVE_EN                                   0xE08B2C
+
+#define mmTPC0_QM_ARB_MST_QUIET_PER                                  0xE08B34
+
+#define mmTPC0_QM_ARB_SLV_CHOISE_WDT                                 0xE08B38
+
+#define mmTPC0_QM_ARB_SLV_ID                                         0xE08B3C
+
+#define mmTPC0_QM_ARB_MSG_MAX_INFLIGHT                               0xE08B44
+
+#define mmTPC0_QM_ARB_MSG_AWUSER_31_11                               0xE08B48
+
+#define mmTPC0_QM_ARB_MSG_AWUSER_SEC_PROP                            0xE08B4C
+
+#define mmTPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP                        0xE08B50
+
+#define mmTPC0_QM_ARB_BASE_LO                                        0xE08B54
+
+#define mmTPC0_QM_ARB_BASE_HI                                        0xE08B58
+
+#define mmTPC0_QM_ARB_STATE_STS                                      0xE08B80
+
+#define mmTPC0_QM_ARB_CHOISE_FULLNESS_STS                            0xE08B84
+
+#define mmTPC0_QM_ARB_MSG_STS                                        0xE08B88
+
+#define mmTPC0_QM_ARB_SLV_CHOISE_Q_HEAD                              0xE08B8C
+
+#define mmTPC0_QM_ARB_ERR_CAUSE                                      0xE08B9C
+
+#define mmTPC0_QM_ARB_ERR_MSG_EN                                     0xE08BA0
+
+#define mmTPC0_QM_ARB_ERR_STS_DRP                                    0xE08BA8
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_0                                 0xE08BB0
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_1                                 0xE08BB4
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_2                                 0xE08BB8
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_3                                 0xE08BBC
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_4                                 0xE08BC0
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_5                                 0xE08BC4
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_6                                 0xE08BC8
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_7                                 0xE08BCC
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_8                                 0xE08BD0
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_9                                 0xE08BD4
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_10                                0xE08BD8
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_11                                0xE08BDC
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_12                                0xE08BE0
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_13                                0xE08BE4
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_14                                0xE08BE8
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_15                                0xE08BEC
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_16                                0xE08BF0
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_17                                0xE08BF4
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_18                                0xE08BF8
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_19                                0xE08BFC
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_20                                0xE08C00
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_21                                0xE08C04
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_22                                0xE08C08
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_23                                0xE08C0C
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_24                                0xE08C10
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_25                                0xE08C14
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_26                                0xE08C18
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_27                                0xE08C1C
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_28                                0xE08C20
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_29                                0xE08C24
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_30                                0xE08C28
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_31                                0xE08C2C
+
+#define mmTPC0_QM_CGM_CFG                                            0xE08C70
+
+#define mmTPC0_QM_CGM_STS                                            0xE08C74
+
+#define mmTPC0_QM_CGM_CFG1                                           0xE08C78
+
+#define mmTPC0_QM_LOCAL_RANGE_BASE                                   0xE08C80
+
+#define mmTPC0_QM_LOCAL_RANGE_SIZE                                   0xE08C84
+
+#define mmTPC0_QM_CSMR_STRICT_PRIO_CFG                               0xE08C90
+
+#define mmTPC0_QM_HBW_RD_RATE_LIM_CFG_1                              0xE08C94
+
+#define mmTPC0_QM_LBW_WR_RATE_LIM_CFG_0                              0xE08C98
+
+#define mmTPC0_QM_LBW_WR_RATE_LIM_CFG_1                              0xE08C9C
+
+#define mmTPC0_QM_HBW_RD_RATE_LIM_CFG_0                              0xE08CA0
+
+#define mmTPC0_QM_GLBL_AXCACHE                                       0xE08CA4
+
+#define mmTPC0_QM_IND_GW_APB_CFG                                     0xE08CB0
+
+#define mmTPC0_QM_IND_GW_APB_WDATA                                   0xE08CB4
+
+#define mmTPC0_QM_IND_GW_APB_RDATA                                   0xE08CB8
+
+#define mmTPC0_QM_IND_GW_APB_STATUS                                  0xE08CBC
+
+#define mmTPC0_QM_GLBL_ERR_ADDR_LO                                   0xE08CD0
+
+#define mmTPC0_QM_GLBL_ERR_ADDR_HI                                   0xE08CD4
+
+#define mmTPC0_QM_GLBL_ERR_WDATA                                     0xE08CD8
+
+#define mmTPC0_QM_GLBL_MEM_INIT_BUSY                                 0xE08D00
+
+#endif /* ASIC_REG_TPC0_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc1_cfg_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc1_cfg_regs.h
new file mode 100644
index 000000000000..6736c476d979
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc1_cfg_regs.h
@@ -0,0 +1,1226 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_TPC1_CFG_REGS_H_
+#define ASIC_REG_TPC1_CFG_REGS_H_
+
+/*
+ *****************************************
+ *   TPC1_CFG (Prototype: TPC)
+ *****************************************
+ */
+
+#define mmTPC1_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW                     0xE46400
+
+#define mmTPC1_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH                    0xE46404
+
+#define mmTPC1_CFG_KERNEL_TENSOR_0_PADDING_VALUE                     0xE46408
+
+#define mmTPC1_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG                     0xE4640C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_0_SIZE                        0xE46410
+
+#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE                      0xE46414
+
+#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_1_SIZE                        0xE46418
+
+#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE                      0xE4641C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_2_SIZE                        0xE46420
+
+#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE                      0xE46424
+
+#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_3_SIZE                        0xE46428
+
+#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE                      0xE4642C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_4_SIZE                        0xE46430
+
+#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE                      0xE46434
+
+#define mmTPC1_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW                     0xE46438
+
+#define mmTPC1_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH                    0xE4643C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_1_PADDING_VALUE                     0xE46440
+
+#define mmTPC1_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG                     0xE46444
+
+#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_0_SIZE                        0xE46448
+
+#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE                      0xE4644C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_1_SIZE                        0xE46450
+
+#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE                      0xE46454
+
+#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_2_SIZE                        0xE46458
+
+#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE                      0xE4645C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_3_SIZE                        0xE46460
+
+#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE                      0xE46464
+
+#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_4_SIZE                        0xE46468
+
+#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE                      0xE4646C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW                     0xE46470
+
+#define mmTPC1_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH                    0xE46474
+
+#define mmTPC1_CFG_KERNEL_TENSOR_2_PADDING_VALUE                     0xE46478
+
+#define mmTPC1_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG                     0xE4647C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_0_SIZE                        0xE46480
+
+#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE                      0xE46484
+
+#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_1_SIZE                        0xE46488
+
+#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE                      0xE4648C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_2_SIZE                        0xE46490
+
+#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE                      0xE46494
+
+#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_3_SIZE                        0xE46498
+
+#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE                      0xE4649C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_4_SIZE                        0xE464A0
+
+#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE                      0xE464A4
+
+#define mmTPC1_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW                     0xE464A8
+
+#define mmTPC1_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH                    0xE464AC
+
+#define mmTPC1_CFG_KERNEL_TENSOR_3_PADDING_VALUE                     0xE464B0
+
+#define mmTPC1_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG                     0xE464B4
+
+#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_0_SIZE                        0xE464B8
+
+#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE                      0xE464BC
+
+#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_1_SIZE                        0xE464C0
+
+#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE                      0xE464C4
+
+#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_2_SIZE                        0xE464C8
+
+#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE                      0xE464CC
+
+#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_3_SIZE                        0xE464D0
+
+#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE                      0xE464D4
+
+#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_4_SIZE                        0xE464D8
+
+#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE                      0xE464DC
+
+#define mmTPC1_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW                     0xE464E0
+
+#define mmTPC1_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH                    0xE464E4
+
+#define mmTPC1_CFG_KERNEL_TENSOR_4_PADDING_VALUE                     0xE464E8
+
+#define mmTPC1_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG                     0xE464EC
+
+#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_0_SIZE                        0xE464F0
+
+#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE                      0xE464F4
+
+#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_1_SIZE                        0xE464F8
+
+#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE                      0xE464FC
+
+#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_2_SIZE                        0xE46500
+
+#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE                      0xE46504
+
+#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_3_SIZE                        0xE46508
+
+#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE                      0xE4650C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_4_SIZE                        0xE46510
+
+#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE                      0xE46514
+
+#define mmTPC1_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW                     0xE46518
+
+#define mmTPC1_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH                    0xE4651C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_5_PADDING_VALUE                     0xE46520
+
+#define mmTPC1_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG                     0xE46524
+
+#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_0_SIZE                        0xE46528
+
+#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE                      0xE4652C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_1_SIZE                        0xE46530
+
+#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE                      0xE46534
+
+#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_2_SIZE                        0xE46538
+
+#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE                      0xE4653C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_3_SIZE                        0xE46540
+
+#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE                      0xE46544
+
+#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_4_SIZE                        0xE46548
+
+#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE                      0xE4654C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW                     0xE46550
+
+#define mmTPC1_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH                    0xE46554
+
+#define mmTPC1_CFG_KERNEL_TENSOR_6_PADDING_VALUE                     0xE46558
+
+#define mmTPC1_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG                     0xE4655C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_0_SIZE                        0xE46560
+
+#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE                      0xE46564
+
+#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_1_SIZE                        0xE46568
+
+#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE                      0xE4656C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_2_SIZE                        0xE46570
+
+#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE                      0xE46574
+
+#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_3_SIZE                        0xE46578
+
+#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE                      0xE4657C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_4_SIZE                        0xE46580
+
+#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE                      0xE46584
+
+#define mmTPC1_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW                     0xE46588
+
+#define mmTPC1_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH                    0xE4658C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_7_PADDING_VALUE                     0xE46590
+
+#define mmTPC1_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG                     0xE46594
+
+#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_0_SIZE                        0xE46598
+
+#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE                      0xE4659C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_1_SIZE                        0xE465A0
+
+#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE                      0xE465A4
+
+#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_2_SIZE                        0xE465A8
+
+#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE                      0xE465AC
+
+#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_3_SIZE                        0xE465B0
+
+#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE                      0xE465B4
+
+#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_4_SIZE                        0xE465B8
+
+#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE                      0xE465BC
+
+#define mmTPC1_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW                     0xE465C0
+
+#define mmTPC1_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH                    0xE465C4
+
+#define mmTPC1_CFG_KERNEL_TENSOR_8_PADDING_VALUE                     0xE465C8
+
+#define mmTPC1_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG                     0xE465CC
+
+#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_0_SIZE                        0xE465D0
+
+#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE                      0xE465D4
+
+#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_1_SIZE                        0xE465D8
+
+#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE                      0xE465DC
+
+#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_2_SIZE                        0xE465E0
+
+#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE                      0xE465E4
+
+#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_3_SIZE                        0xE465E8
+
+#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE                      0xE465EC
+
+#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_4_SIZE                        0xE465F0
+
+#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE                      0xE465F4
+
+#define mmTPC1_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW                     0xE465F8
+
+#define mmTPC1_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH                    0xE465FC
+
+#define mmTPC1_CFG_KERNEL_TENSOR_9_PADDING_VALUE                     0xE46600
+
+#define mmTPC1_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG                     0xE46604
+
+#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_0_SIZE                        0xE46608
+
+#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE                      0xE4660C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_1_SIZE                        0xE46610
+
+#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE                      0xE46614
+
+#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_2_SIZE                        0xE46618
+
+#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE                      0xE4661C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_3_SIZE                        0xE46620
+
+#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE                      0xE46624
+
+#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_4_SIZE                        0xE46628
+
+#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE                      0xE4662C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW                    0xE46630
+
+#define mmTPC1_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH                   0xE46634
+
+#define mmTPC1_CFG_KERNEL_TENSOR_10_PADDING_VALUE                    0xE46638
+
+#define mmTPC1_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG                    0xE4663C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_0_SIZE                       0xE46640
+
+#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE                     0xE46644
+
+#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_1_SIZE                       0xE46648
+
+#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE                     0xE4664C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_2_SIZE                       0xE46650
+
+#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE                     0xE46654
+
+#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_3_SIZE                       0xE46658
+
+#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE                     0xE4665C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_4_SIZE                       0xE46660
+
+#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE                     0xE46664
+
+#define mmTPC1_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW                    0xE46668
+
+#define mmTPC1_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH                   0xE4666C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_11_PADDING_VALUE                    0xE46670
+
+#define mmTPC1_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG                    0xE46674
+
+#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_0_SIZE                       0xE46678
+
+#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE                     0xE4667C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_1_SIZE                       0xE46680
+
+#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE                     0xE46684
+
+#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_2_SIZE                       0xE46688
+
+#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE                     0xE4668C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_3_SIZE                       0xE46690
+
+#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE                     0xE46694
+
+#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_4_SIZE                       0xE46698
+
+#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE                     0xE4669C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW                    0xE466A0
+
+#define mmTPC1_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH                   0xE466A4
+
+#define mmTPC1_CFG_KERNEL_TENSOR_12_PADDING_VALUE                    0xE466A8
+
+#define mmTPC1_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG                    0xE466AC
+
+#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_0_SIZE                       0xE466B0
+
+#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE                     0xE466B4
+
+#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_1_SIZE                       0xE466B8
+
+#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE                     0xE466BC
+
+#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_2_SIZE                       0xE466C0
+
+#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE                     0xE466C4
+
+#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_3_SIZE                       0xE466C8
+
+#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE                     0xE466CC
+
+#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_4_SIZE                       0xE466D0
+
+#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE                     0xE466D4
+
+#define mmTPC1_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW                    0xE466D8
+
+#define mmTPC1_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH                   0xE466DC
+
+#define mmTPC1_CFG_KERNEL_TENSOR_13_PADDING_VALUE                    0xE466E0
+
+#define mmTPC1_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG                    0xE466E4
+
+#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_0_SIZE                       0xE466E8
+
+#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE                     0xE466EC
+
+#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_1_SIZE                       0xE466F0
+
+#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE                     0xE466F4
+
+#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_2_SIZE                       0xE466F8
+
+#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE                     0xE466FC
+
+#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_3_SIZE                       0xE46700
+
+#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE                     0xE46704
+
+#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_4_SIZE                       0xE46708
+
+#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE                     0xE4670C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW                    0xE46710
+
+#define mmTPC1_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH                   0xE46714
+
+#define mmTPC1_CFG_KERNEL_TENSOR_14_PADDING_VALUE                    0xE46718
+
+#define mmTPC1_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG                    0xE4671C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_0_SIZE                       0xE46720
+
+#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE                     0xE46724
+
+#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_1_SIZE                       0xE46728
+
+#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE                     0xE4672C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_2_SIZE                       0xE46730
+
+#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE                     0xE46734
+
+#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_3_SIZE                       0xE46738
+
+#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE                     0xE4673C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_4_SIZE                       0xE46740
+
+#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE                     0xE46744
+
+#define mmTPC1_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW                    0xE46748
+
+#define mmTPC1_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH                   0xE4674C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_15_PADDING_VALUE                    0xE46750
+
+#define mmTPC1_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG                    0xE46754
+
+#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_0_SIZE                       0xE46758
+
+#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE                     0xE4675C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_1_SIZE                       0xE46760
+
+#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE                     0xE46764
+
+#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_2_SIZE                       0xE46768
+
+#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE                     0xE4676C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_3_SIZE                       0xE46770
+
+#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE                     0xE46774
+
+#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_4_SIZE                       0xE46778
+
+#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE                     0xE4677C
+
+#define mmTPC1_CFG_KERNEL_SYNC_OBJECT_MESSAGE                        0xE46780
+
+#define mmTPC1_CFG_KERNEL_SYNC_OBJECT_ADDR                           0xE46784
+
+#define mmTPC1_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW                    0xE46788
+
+#define mmTPC1_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH                   0xE4678C
+
+#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_0                             0xE46790
+
+#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_0                             0xE46794
+
+#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_1                             0xE46798
+
+#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_1                             0xE4679C
+
+#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_2                             0xE467A0
+
+#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_2                             0xE467A4
+
+#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_3                             0xE467A8
+
+#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_3                             0xE467AC
+
+#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_4                             0xE467B0
+
+#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_4                             0xE467B4
+
+#define mmTPC1_CFG_KERNEL_KERNEL_CONFIG                              0xE467B8
+
+#define mmTPC1_CFG_KERNEL_KERNEL_ID                                  0xE467BC
+
+#define mmTPC1_CFG_KERNEL_SRF_0                                      0xE467C0
+
+#define mmTPC1_CFG_KERNEL_SRF_1                                      0xE467C4
+
+#define mmTPC1_CFG_KERNEL_SRF_2                                      0xE467C8
+
+#define mmTPC1_CFG_KERNEL_SRF_3                                      0xE467CC
+
+#define mmTPC1_CFG_KERNEL_SRF_4                                      0xE467D0
+
+#define mmTPC1_CFG_KERNEL_SRF_5                                      0xE467D4
+
+#define mmTPC1_CFG_KERNEL_SRF_6                                      0xE467D8
+
+#define mmTPC1_CFG_KERNEL_SRF_7                                      0xE467DC
+
+#define mmTPC1_CFG_KERNEL_SRF_8                                      0xE467E0
+
+#define mmTPC1_CFG_KERNEL_SRF_9                                      0xE467E4
+
+#define mmTPC1_CFG_KERNEL_SRF_10                                     0xE467E8
+
+#define mmTPC1_CFG_KERNEL_SRF_11                                     0xE467EC
+
+#define mmTPC1_CFG_KERNEL_SRF_12                                     0xE467F0
+
+#define mmTPC1_CFG_KERNEL_SRF_13                                     0xE467F4
+
+#define mmTPC1_CFG_KERNEL_SRF_14                                     0xE467F8
+
+#define mmTPC1_CFG_KERNEL_SRF_15                                     0xE467FC
+
+#define mmTPC1_CFG_KERNEL_SRF_16                                     0xE46800
+
+#define mmTPC1_CFG_KERNEL_SRF_17                                     0xE46804
+
+#define mmTPC1_CFG_KERNEL_SRF_18                                     0xE46808
+
+#define mmTPC1_CFG_KERNEL_SRF_19                                     0xE4680C
+
+#define mmTPC1_CFG_KERNEL_SRF_20                                     0xE46810
+
+#define mmTPC1_CFG_KERNEL_SRF_21                                     0xE46814
+
+#define mmTPC1_CFG_KERNEL_SRF_22                                     0xE46818
+
+#define mmTPC1_CFG_KERNEL_SRF_23                                     0xE4681C
+
+#define mmTPC1_CFG_KERNEL_SRF_24                                     0xE46820
+
+#define mmTPC1_CFG_KERNEL_SRF_25                                     0xE46824
+
+#define mmTPC1_CFG_KERNEL_SRF_26                                     0xE46828
+
+#define mmTPC1_CFG_KERNEL_SRF_27                                     0xE4682C
+
+#define mmTPC1_CFG_KERNEL_SRF_28                                     0xE46830
+
+#define mmTPC1_CFG_KERNEL_SRF_29                                     0xE46834
+
+#define mmTPC1_CFG_KERNEL_SRF_30                                     0xE46838
+
+#define mmTPC1_CFG_KERNEL_SRF_31                                     0xE4683C
+
+#define mmTPC1_CFG_ROUND_CSR                                         0xE468FC
+
+#define mmTPC1_CFG_PROT                                              0xE46900
+
+#define mmTPC1_CFG_SEMAPHORE                                         0xE46908
+
+#define mmTPC1_CFG_VFLAGS                                            0xE4690C
+
+#define mmTPC1_CFG_SFLAGS                                            0xE46910
+
+#define mmTPC1_CFG_LFSR_POLYNOM                                      0xE46918
+
+#define mmTPC1_CFG_STATUS                                            0xE4691C
+
+#define mmTPC1_CFG_CFG_BASE_ADDRESS_HIGH                             0xE46920
+
+#define mmTPC1_CFG_CFG_SUBTRACT_VALUE                                0xE46924
+
+#define mmTPC1_CFG_SM_BASE_ADDRESS_HIGH                              0xE4692C
+
+#define mmTPC1_CFG_TPC_CMD                                           0xE46930
+
+#define mmTPC1_CFG_TPC_EXECUTE                                       0xE46938
+
+#define mmTPC1_CFG_TPC_STALL                                         0xE4693C
+
+#define mmTPC1_CFG_ICACHE_BASE_ADDERESS_LOW                          0xE46940
+
+#define mmTPC1_CFG_ICACHE_BASE_ADDERESS_HIGH                         0xE46944
+
+#define mmTPC1_CFG_RD_RATE_LIMIT                                     0xE46948
+
+#define mmTPC1_CFG_WR_RATE_LIMIT                                     0xE46950
+
+#define mmTPC1_CFG_MSS_CONFIG                                        0xE46954
+
+#define mmTPC1_CFG_TPC_INTR_CAUSE                                    0xE46958
+
+#define mmTPC1_CFG_TPC_INTR_MASK                                     0xE4695C
+
+#define mmTPC1_CFG_WQ_CREDITS                                        0xE46960
+
+#define mmTPC1_CFG_ARUSER_LO                                         0xE46964
+
+#define mmTPC1_CFG_ARUSER_HI                                         0xE46968
+
+#define mmTPC1_CFG_AWUSER_LO                                         0xE4696C
+
+#define mmTPC1_CFG_AWUSER_HI                                         0xE46970
+
+#define mmTPC1_CFG_OPCODE_EXEC                                       0xE46974
+
+#define mmTPC1_CFG_LUT_FUNC32_BASE_ADDR_LO                           0xE46978
+
+#define mmTPC1_CFG_LUT_FUNC32_BASE_ADDR_HI                           0xE4697C
+
+#define mmTPC1_CFG_LUT_FUNC64_BASE_ADDR_LO                           0xE46980
+
+#define mmTPC1_CFG_LUT_FUNC64_BASE_ADDR_HI                           0xE46984
+
+#define mmTPC1_CFG_LUT_FUNC128_BASE_ADDR_LO                          0xE46988
+
+#define mmTPC1_CFG_LUT_FUNC128_BASE_ADDR_HI                          0xE4698C
+
+#define mmTPC1_CFG_LUT_FUNC256_BASE_ADDR_LO                          0xE46990
+
+#define mmTPC1_CFG_LUT_FUNC256_BASE_ADDR_HI                          0xE46994
+
+#define mmTPC1_CFG_TSB_CFG_MAX_SIZE                                  0xE46998
+
+#define mmTPC1_CFG_TSB_CFG                                           0xE4699C
+
+#define mmTPC1_CFG_DBGMEM_ADD                                        0xE469A0
+
+#define mmTPC1_CFG_DBGMEM_DATA_WR                                    0xE469A4
+
+#define mmTPC1_CFG_DBGMEM_DATA_RD                                    0xE469A8
+
+#define mmTPC1_CFG_DBGMEM_CTRL                                       0xE469AC
+
+#define mmTPC1_CFG_DBGMEM_RC                                         0xE469B0
+
+#define mmTPC1_CFG_TSB_INFLIGHT_CNTR                                 0xE469B4
+
+#define mmTPC1_CFG_WQ_INFLIGHT_CNTR                                  0xE469B8
+
+#define mmTPC1_CFG_WQ_LBW_TOTAL_CNTR                                 0xE469BC
+
+#define mmTPC1_CFG_WQ_HBW_TOTAL_CNTR                                 0xE469C0
+
+#define mmTPC1_CFG_IRQ_OCCOUPY_CNTR                                  0xE469C4
+
+#define mmTPC1_CFG_FUNC_MBIST_CNTRL                                  0xE469D0
+
+#define mmTPC1_CFG_FUNC_MBIST_PAT                                    0xE469D4
+
+#define mmTPC1_CFG_FUNC_MBIST_MEM_0                                  0xE469D8
+
+#define mmTPC1_CFG_FUNC_MBIST_MEM_1                                  0xE469DC
+
+#define mmTPC1_CFG_FUNC_MBIST_MEM_2                                  0xE469E0
+
+#define mmTPC1_CFG_FUNC_MBIST_MEM_3                                  0xE469E4
+
+#define mmTPC1_CFG_FUNC_MBIST_MEM_4                                  0xE469E8
+
+#define mmTPC1_CFG_FUNC_MBIST_MEM_5                                  0xE469EC
+
+#define mmTPC1_CFG_FUNC_MBIST_MEM_6                                  0xE469F0
+
+#define mmTPC1_CFG_FUNC_MBIST_MEM_7                                  0xE469F4
+
+#define mmTPC1_CFG_FUNC_MBIST_MEM_8                                  0xE469F8
+
+#define mmTPC1_CFG_FUNC_MBIST_MEM_9                                  0xE469FC
+
+#define mmTPC1_CFG_QM_TENSOR_0_BASE_ADDR_LOW                         0xE46A00
+
+#define mmTPC1_CFG_QM_TENSOR_0_BASE_ADDR_HIGH                        0xE46A04
+
+#define mmTPC1_CFG_QM_TENSOR_0_PADDING_VALUE                         0xE46A08
+
+#define mmTPC1_CFG_QM_TENSOR_0_TENSOR_CONFIG                         0xE46A0C
+
+#define mmTPC1_CFG_QM_TENSOR_0_DIM_0_SIZE                            0xE46A10
+
+#define mmTPC1_CFG_QM_TENSOR_0_DIM_0_STRIDE                          0xE46A14
+
+#define mmTPC1_CFG_QM_TENSOR_0_DIM_1_SIZE                            0xE46A18
+
+#define mmTPC1_CFG_QM_TENSOR_0_DIM_1_STRIDE                          0xE46A1C
+
+#define mmTPC1_CFG_QM_TENSOR_0_DIM_2_SIZE                            0xE46A20
+
+#define mmTPC1_CFG_QM_TENSOR_0_DIM_2_STRIDE                          0xE46A24
+
+#define mmTPC1_CFG_QM_TENSOR_0_DIM_3_SIZE                            0xE46A28
+
+#define mmTPC1_CFG_QM_TENSOR_0_DIM_3_STRIDE                          0xE46A2C
+
+#define mmTPC1_CFG_QM_TENSOR_0_DIM_4_SIZE                            0xE46A30
+
+#define mmTPC1_CFG_QM_TENSOR_0_DIM_4_STRIDE                          0xE46A34
+
+#define mmTPC1_CFG_QM_TENSOR_1_BASE_ADDR_LOW                         0xE46A38
+
+#define mmTPC1_CFG_QM_TENSOR_1_BASE_ADDR_HIGH                        0xE46A3C
+
+#define mmTPC1_CFG_QM_TENSOR_1_PADDING_VALUE                         0xE46A40
+
+#define mmTPC1_CFG_QM_TENSOR_1_TENSOR_CONFIG                         0xE46A44
+
+#define mmTPC1_CFG_QM_TENSOR_1_DIM_0_SIZE                            0xE46A48
+
+#define mmTPC1_CFG_QM_TENSOR_1_DIM_0_STRIDE                          0xE46A4C
+
+#define mmTPC1_CFG_QM_TENSOR_1_DIM_1_SIZE                            0xE46A50
+
+#define mmTPC1_CFG_QM_TENSOR_1_DIM_1_STRIDE                          0xE46A54
+
+#define mmTPC1_CFG_QM_TENSOR_1_DIM_2_SIZE                            0xE46A58
+
+#define mmTPC1_CFG_QM_TENSOR_1_DIM_2_STRIDE                          0xE46A5C
+
+#define mmTPC1_CFG_QM_TENSOR_1_DIM_3_SIZE                            0xE46A60
+
+#define mmTPC1_CFG_QM_TENSOR_1_DIM_3_STRIDE                          0xE46A64
+
+#define mmTPC1_CFG_QM_TENSOR_1_DIM_4_SIZE                            0xE46A68
+
+#define mmTPC1_CFG_QM_TENSOR_1_DIM_4_STRIDE                          0xE46A6C
+
+#define mmTPC1_CFG_QM_TENSOR_2_BASE_ADDR_LOW                         0xE46A70
+
+#define mmTPC1_CFG_QM_TENSOR_2_BASE_ADDR_HIGH                        0xE46A74
+
+#define mmTPC1_CFG_QM_TENSOR_2_PADDING_VALUE                         0xE46A78
+
+#define mmTPC1_CFG_QM_TENSOR_2_TENSOR_CONFIG                         0xE46A7C
+
+#define mmTPC1_CFG_QM_TENSOR_2_DIM_0_SIZE                            0xE46A80
+
+#define mmTPC1_CFG_QM_TENSOR_2_DIM_0_STRIDE                          0xE46A84
+
+#define mmTPC1_CFG_QM_TENSOR_2_DIM_1_SIZE                            0xE46A88
+
+#define mmTPC1_CFG_QM_TENSOR_2_DIM_1_STRIDE                          0xE46A8C
+
+#define mmTPC1_CFG_QM_TENSOR_2_DIM_2_SIZE                            0xE46A90
+
+#define mmTPC1_CFG_QM_TENSOR_2_DIM_2_STRIDE                          0xE46A94
+
+#define mmTPC1_CFG_QM_TENSOR_2_DIM_3_SIZE                            0xE46A98
+
+#define mmTPC1_CFG_QM_TENSOR_2_DIM_3_STRIDE                          0xE46A9C
+
+#define mmTPC1_CFG_QM_TENSOR_2_DIM_4_SIZE                            0xE46AA0
+
+#define mmTPC1_CFG_QM_TENSOR_2_DIM_4_STRIDE                          0xE46AA4
+
+#define mmTPC1_CFG_QM_TENSOR_3_BASE_ADDR_LOW                         0xE46AA8
+
+#define mmTPC1_CFG_QM_TENSOR_3_BASE_ADDR_HIGH                        0xE46AAC
+
+#define mmTPC1_CFG_QM_TENSOR_3_PADDING_VALUE                         0xE46AB0
+
+#define mmTPC1_CFG_QM_TENSOR_3_TENSOR_CONFIG                         0xE46AB4
+
+#define mmTPC1_CFG_QM_TENSOR_3_DIM_0_SIZE                            0xE46AB8
+
+#define mmTPC1_CFG_QM_TENSOR_3_DIM_0_STRIDE                          0xE46ABC
+
+#define mmTPC1_CFG_QM_TENSOR_3_DIM_1_SIZE                            0xE46AC0
+
+#define mmTPC1_CFG_QM_TENSOR_3_DIM_1_STRIDE                          0xE46AC4
+
+#define mmTPC1_CFG_QM_TENSOR_3_DIM_2_SIZE                            0xE46AC8
+
+#define mmTPC1_CFG_QM_TENSOR_3_DIM_2_STRIDE                          0xE46ACC
+
+#define mmTPC1_CFG_QM_TENSOR_3_DIM_3_SIZE                            0xE46AD0
+
+#define mmTPC1_CFG_QM_TENSOR_3_DIM_3_STRIDE                          0xE46AD4
+
+#define mmTPC1_CFG_QM_TENSOR_3_DIM_4_SIZE                            0xE46AD8
+
+#define mmTPC1_CFG_QM_TENSOR_3_DIM_4_STRIDE                          0xE46ADC
+
+#define mmTPC1_CFG_QM_TENSOR_4_BASE_ADDR_LOW                         0xE46AE0
+
+#define mmTPC1_CFG_QM_TENSOR_4_BASE_ADDR_HIGH                        0xE46AE4
+
+#define mmTPC1_CFG_QM_TENSOR_4_PADDING_VALUE                         0xE46AE8
+
+#define mmTPC1_CFG_QM_TENSOR_4_TENSOR_CONFIG                         0xE46AEC
+
+#define mmTPC1_CFG_QM_TENSOR_4_DIM_0_SIZE                            0xE46AF0
+
+#define mmTPC1_CFG_QM_TENSOR_4_DIM_0_STRIDE                          0xE46AF4
+
+#define mmTPC1_CFG_QM_TENSOR_4_DIM_1_SIZE                            0xE46AF8
+
+#define mmTPC1_CFG_QM_TENSOR_4_DIM_1_STRIDE                          0xE46AFC
+
+#define mmTPC1_CFG_QM_TENSOR_4_DIM_2_SIZE                            0xE46B00
+
+#define mmTPC1_CFG_QM_TENSOR_4_DIM_2_STRIDE                          0xE46B04
+
+#define mmTPC1_CFG_QM_TENSOR_4_DIM_3_SIZE                            0xE46B08
+
+#define mmTPC1_CFG_QM_TENSOR_4_DIM_3_STRIDE                          0xE46B0C
+
+#define mmTPC1_CFG_QM_TENSOR_4_DIM_4_SIZE                            0xE46B10
+
+#define mmTPC1_CFG_QM_TENSOR_4_DIM_4_STRIDE                          0xE46B14
+
+#define mmTPC1_CFG_QM_TENSOR_5_BASE_ADDR_LOW                         0xE46B18
+
+#define mmTPC1_CFG_QM_TENSOR_5_BASE_ADDR_HIGH                        0xE46B1C
+
+#define mmTPC1_CFG_QM_TENSOR_5_PADDING_VALUE                         0xE46B20
+
+#define mmTPC1_CFG_QM_TENSOR_5_TENSOR_CONFIG                         0xE46B24
+
+#define mmTPC1_CFG_QM_TENSOR_5_DIM_0_SIZE                            0xE46B28
+
+#define mmTPC1_CFG_QM_TENSOR_5_DIM_0_STRIDE                          0xE46B2C
+
+#define mmTPC1_CFG_QM_TENSOR_5_DIM_1_SIZE                            0xE46B30
+
+#define mmTPC1_CFG_QM_TENSOR_5_DIM_1_STRIDE                          0xE46B34
+
+#define mmTPC1_CFG_QM_TENSOR_5_DIM_2_SIZE                            0xE46B38
+
+#define mmTPC1_CFG_QM_TENSOR_5_DIM_2_STRIDE                          0xE46B3C
+
+#define mmTPC1_CFG_QM_TENSOR_5_DIM_3_SIZE                            0xE46B40
+
+#define mmTPC1_CFG_QM_TENSOR_5_DIM_3_STRIDE                          0xE46B44
+
+#define mmTPC1_CFG_QM_TENSOR_5_DIM_4_SIZE                            0xE46B48
+
+#define mmTPC1_CFG_QM_TENSOR_5_DIM_4_STRIDE                          0xE46B4C
+
+#define mmTPC1_CFG_QM_TENSOR_6_BASE_ADDR_LOW                         0xE46B50
+
+#define mmTPC1_CFG_QM_TENSOR_6_BASE_ADDR_HIGH                        0xE46B54
+
+#define mmTPC1_CFG_QM_TENSOR_6_PADDING_VALUE                         0xE46B58
+
+#define mmTPC1_CFG_QM_TENSOR_6_TENSOR_CONFIG                         0xE46B5C
+
+#define mmTPC1_CFG_QM_TENSOR_6_DIM_0_SIZE                            0xE46B60
+
+#define mmTPC1_CFG_QM_TENSOR_6_DIM_0_STRIDE                          0xE46B64
+
+#define mmTPC1_CFG_QM_TENSOR_6_DIM_1_SIZE                            0xE46B68
+
+#define mmTPC1_CFG_QM_TENSOR_6_DIM_1_STRIDE                          0xE46B6C
+
+#define mmTPC1_CFG_QM_TENSOR_6_DIM_2_SIZE                            0xE46B70
+
+#define mmTPC1_CFG_QM_TENSOR_6_DIM_2_STRIDE                          0xE46B74
+
+#define mmTPC1_CFG_QM_TENSOR_6_DIM_3_SIZE                            0xE46B78
+
+#define mmTPC1_CFG_QM_TENSOR_6_DIM_3_STRIDE                          0xE46B7C
+
+#define mmTPC1_CFG_QM_TENSOR_6_DIM_4_SIZE                            0xE46B80
+
+#define mmTPC1_CFG_QM_TENSOR_6_DIM_4_STRIDE                          0xE46B84
+
+#define mmTPC1_CFG_QM_TENSOR_7_BASE_ADDR_LOW                         0xE46B88
+
+#define mmTPC1_CFG_QM_TENSOR_7_BASE_ADDR_HIGH                        0xE46B8C
+
+#define mmTPC1_CFG_QM_TENSOR_7_PADDING_VALUE                         0xE46B90
+
+#define mmTPC1_CFG_QM_TENSOR_7_TENSOR_CONFIG                         0xE46B94
+
+#define mmTPC1_CFG_QM_TENSOR_7_DIM_0_SIZE                            0xE46B98
+
+#define mmTPC1_CFG_QM_TENSOR_7_DIM_0_STRIDE                          0xE46B9C
+
+#define mmTPC1_CFG_QM_TENSOR_7_DIM_1_SIZE                            0xE46BA0
+
+#define mmTPC1_CFG_QM_TENSOR_7_DIM_1_STRIDE                          0xE46BA4
+
+#define mmTPC1_CFG_QM_TENSOR_7_DIM_2_SIZE                            0xE46BA8
+
+#define mmTPC1_CFG_QM_TENSOR_7_DIM_2_STRIDE                          0xE46BAC
+
+#define mmTPC1_CFG_QM_TENSOR_7_DIM_3_SIZE                            0xE46BB0
+
+#define mmTPC1_CFG_QM_TENSOR_7_DIM_3_STRIDE                          0xE46BB4
+
+#define mmTPC1_CFG_QM_TENSOR_7_DIM_4_SIZE                            0xE46BB8
+
+#define mmTPC1_CFG_QM_TENSOR_7_DIM_4_STRIDE                          0xE46BBC
+
+#define mmTPC1_CFG_QM_TENSOR_8_BASE_ADDR_LOW                         0xE46BC0
+
+#define mmTPC1_CFG_QM_TENSOR_8_BASE_ADDR_HIGH                        0xE46BC4
+
+#define mmTPC1_CFG_QM_TENSOR_8_PADDING_VALUE                         0xE46BC8
+
+#define mmTPC1_CFG_QM_TENSOR_8_TENSOR_CONFIG                         0xE46BCC
+
+#define mmTPC1_CFG_QM_TENSOR_8_DIM_0_SIZE                            0xE46BD0
+
+#define mmTPC1_CFG_QM_TENSOR_8_DIM_0_STRIDE                          0xE46BD4
+
+#define mmTPC1_CFG_QM_TENSOR_8_DIM_1_SIZE                            0xE46BD8
+
+#define mmTPC1_CFG_QM_TENSOR_8_DIM_1_STRIDE                          0xE46BDC
+
+#define mmTPC1_CFG_QM_TENSOR_8_DIM_2_SIZE                            0xE46BE0
+
+#define mmTPC1_CFG_QM_TENSOR_8_DIM_2_STRIDE                          0xE46BE4
+
+#define mmTPC1_CFG_QM_TENSOR_8_DIM_3_SIZE                            0xE46BE8
+
+#define mmTPC1_CFG_QM_TENSOR_8_DIM_3_STRIDE                          0xE46BEC
+
+#define mmTPC1_CFG_QM_TENSOR_8_DIM_4_SIZE                            0xE46BF0
+
+#define mmTPC1_CFG_QM_TENSOR_8_DIM_4_STRIDE                          0xE46BF4
+
+#define mmTPC1_CFG_QM_TENSOR_9_BASE_ADDR_LOW                         0xE46BF8
+
+#define mmTPC1_CFG_QM_TENSOR_9_BASE_ADDR_HIGH                        0xE46BFC
+
+#define mmTPC1_CFG_QM_TENSOR_9_PADDING_VALUE                         0xE46C00
+
+#define mmTPC1_CFG_QM_TENSOR_9_TENSOR_CONFIG                         0xE46C04
+
+#define mmTPC1_CFG_QM_TENSOR_9_DIM_0_SIZE                            0xE46C08
+
+#define mmTPC1_CFG_QM_TENSOR_9_DIM_0_STRIDE                          0xE46C0C
+
+#define mmTPC1_CFG_QM_TENSOR_9_DIM_1_SIZE                            0xE46C10
+
+#define mmTPC1_CFG_QM_TENSOR_9_DIM_1_STRIDE                          0xE46C14
+
+#define mmTPC1_CFG_QM_TENSOR_9_DIM_2_SIZE                            0xE46C18
+
+#define mmTPC1_CFG_QM_TENSOR_9_DIM_2_STRIDE                          0xE46C1C
+
+#define mmTPC1_CFG_QM_TENSOR_9_DIM_3_SIZE                            0xE46C20
+
+#define mmTPC1_CFG_QM_TENSOR_9_DIM_3_STRIDE                          0xE46C24
+
+#define mmTPC1_CFG_QM_TENSOR_9_DIM_4_SIZE                            0xE46C28
+
+#define mmTPC1_CFG_QM_TENSOR_9_DIM_4_STRIDE                          0xE46C2C
+
+#define mmTPC1_CFG_QM_TENSOR_10_BASE_ADDR_LOW                        0xE46C30
+
+#define mmTPC1_CFG_QM_TENSOR_10_BASE_ADDR_HIGH                       0xE46C34
+
+#define mmTPC1_CFG_QM_TENSOR_10_PADDING_VALUE                        0xE46C38
+
+#define mmTPC1_CFG_QM_TENSOR_10_TENSOR_CONFIG                        0xE46C3C
+
+#define mmTPC1_CFG_QM_TENSOR_10_DIM_0_SIZE                           0xE46C40
+
+#define mmTPC1_CFG_QM_TENSOR_10_DIM_0_STRIDE                         0xE46C44
+
+#define mmTPC1_CFG_QM_TENSOR_10_DIM_1_SIZE                           0xE46C48
+
+#define mmTPC1_CFG_QM_TENSOR_10_DIM_1_STRIDE                         0xE46C4C
+
+#define mmTPC1_CFG_QM_TENSOR_10_DIM_2_SIZE                           0xE46C50
+
+#define mmTPC1_CFG_QM_TENSOR_10_DIM_2_STRIDE                         0xE46C54
+
+#define mmTPC1_CFG_QM_TENSOR_10_DIM_3_SIZE                           0xE46C58
+
+#define mmTPC1_CFG_QM_TENSOR_10_DIM_3_STRIDE                         0xE46C5C
+
+#define mmTPC1_CFG_QM_TENSOR_10_DIM_4_SIZE                           0xE46C60
+
+#define mmTPC1_CFG_QM_TENSOR_10_DIM_4_STRIDE                         0xE46C64
+
+#define mmTPC1_CFG_QM_TENSOR_11_BASE_ADDR_LOW                        0xE46C68
+
+#define mmTPC1_CFG_QM_TENSOR_11_BASE_ADDR_HIGH                       0xE46C6C
+
+#define mmTPC1_CFG_QM_TENSOR_11_PADDING_VALUE                        0xE46C70
+
+#define mmTPC1_CFG_QM_TENSOR_11_TENSOR_CONFIG                        0xE46C74
+
+#define mmTPC1_CFG_QM_TENSOR_11_DIM_0_SIZE                           0xE46C78
+
+#define mmTPC1_CFG_QM_TENSOR_11_DIM_0_STRIDE                         0xE46C7C
+
+#define mmTPC1_CFG_QM_TENSOR_11_DIM_1_SIZE                           0xE46C80
+
+#define mmTPC1_CFG_QM_TENSOR_11_DIM_1_STRIDE                         0xE46C84
+
+#define mmTPC1_CFG_QM_TENSOR_11_DIM_2_SIZE                           0xE46C88
+
+#define mmTPC1_CFG_QM_TENSOR_11_DIM_2_STRIDE                         0xE46C8C
+
+#define mmTPC1_CFG_QM_TENSOR_11_DIM_3_SIZE                           0xE46C90
+
+#define mmTPC1_CFG_QM_TENSOR_11_DIM_3_STRIDE                         0xE46C94
+
+#define mmTPC1_CFG_QM_TENSOR_11_DIM_4_SIZE                           0xE46C98
+
+#define mmTPC1_CFG_QM_TENSOR_11_DIM_4_STRIDE                         0xE46C9C
+
+#define mmTPC1_CFG_QM_TENSOR_12_BASE_ADDR_LOW                        0xE46CA0
+
+#define mmTPC1_CFG_QM_TENSOR_12_BASE_ADDR_HIGH                       0xE46CA4
+
+#define mmTPC1_CFG_QM_TENSOR_12_PADDING_VALUE                        0xE46CA8
+
+#define mmTPC1_CFG_QM_TENSOR_12_TENSOR_CONFIG                        0xE46CAC
+
+#define mmTPC1_CFG_QM_TENSOR_12_DIM_0_SIZE                           0xE46CB0
+
+#define mmTPC1_CFG_QM_TENSOR_12_DIM_0_STRIDE                         0xE46CB4
+
+#define mmTPC1_CFG_QM_TENSOR_12_DIM_1_SIZE                           0xE46CB8
+
+#define mmTPC1_CFG_QM_TENSOR_12_DIM_1_STRIDE                         0xE46CBC
+
+#define mmTPC1_CFG_QM_TENSOR_12_DIM_2_SIZE                           0xE46CC0
+
+#define mmTPC1_CFG_QM_TENSOR_12_DIM_2_STRIDE                         0xE46CC4
+
+#define mmTPC1_CFG_QM_TENSOR_12_DIM_3_SIZE                           0xE46CC8
+
+#define mmTPC1_CFG_QM_TENSOR_12_DIM_3_STRIDE                         0xE46CCC
+
+#define mmTPC1_CFG_QM_TENSOR_12_DIM_4_SIZE                           0xE46CD0
+
+#define mmTPC1_CFG_QM_TENSOR_12_DIM_4_STRIDE                         0xE46CD4
+
+#define mmTPC1_CFG_QM_TENSOR_13_BASE_ADDR_LOW                        0xE46CD8
+
+#define mmTPC1_CFG_QM_TENSOR_13_BASE_ADDR_HIGH                       0xE46CDC
+
+#define mmTPC1_CFG_QM_TENSOR_13_PADDING_VALUE                        0xE46CE0
+
+#define mmTPC1_CFG_QM_TENSOR_13_TENSOR_CONFIG                        0xE46CE4
+
+#define mmTPC1_CFG_QM_TENSOR_13_DIM_0_SIZE                           0xE46CE8
+
+#define mmTPC1_CFG_QM_TENSOR_13_DIM_0_STRIDE                         0xE46CEC
+
+#define mmTPC1_CFG_QM_TENSOR_13_DIM_1_SIZE                           0xE46CF0
+
+#define mmTPC1_CFG_QM_TENSOR_13_DIM_1_STRIDE                         0xE46CF4
+
+#define mmTPC1_CFG_QM_TENSOR_13_DIM_2_SIZE                           0xE46CF8
+
+#define mmTPC1_CFG_QM_TENSOR_13_DIM_2_STRIDE                         0xE46CFC
+
+#define mmTPC1_CFG_QM_TENSOR_13_DIM_3_SIZE                           0xE46D00
+
+#define mmTPC1_CFG_QM_TENSOR_13_DIM_3_STRIDE                         0xE46D04
+
+#define mmTPC1_CFG_QM_TENSOR_13_DIM_4_SIZE                           0xE46D08
+
+#define mmTPC1_CFG_QM_TENSOR_13_DIM_4_STRIDE                         0xE46D0C
+
+#define mmTPC1_CFG_QM_TENSOR_14_BASE_ADDR_LOW                        0xE46D10
+
+#define mmTPC1_CFG_QM_TENSOR_14_BASE_ADDR_HIGH                       0xE46D14
+
+#define mmTPC1_CFG_QM_TENSOR_14_PADDING_VALUE                        0xE46D18
+
+#define mmTPC1_CFG_QM_TENSOR_14_TENSOR_CONFIG                        0xE46D1C
+
+#define mmTPC1_CFG_QM_TENSOR_14_DIM_0_SIZE                           0xE46D20
+
+#define mmTPC1_CFG_QM_TENSOR_14_DIM_0_STRIDE                         0xE46D24
+
+#define mmTPC1_CFG_QM_TENSOR_14_DIM_1_SIZE                           0xE46D28
+
+#define mmTPC1_CFG_QM_TENSOR_14_DIM_1_STRIDE                         0xE46D2C
+
+#define mmTPC1_CFG_QM_TENSOR_14_DIM_2_SIZE                           0xE46D30
+
+#define mmTPC1_CFG_QM_TENSOR_14_DIM_2_STRIDE                         0xE46D34
+
+#define mmTPC1_CFG_QM_TENSOR_14_DIM_3_SIZE                           0xE46D38
+
+#define mmTPC1_CFG_QM_TENSOR_14_DIM_3_STRIDE                         0xE46D3C
+
+#define mmTPC1_CFG_QM_TENSOR_14_DIM_4_SIZE                           0xE46D40
+
+#define mmTPC1_CFG_QM_TENSOR_14_DIM_4_STRIDE                         0xE46D44
+
+#define mmTPC1_CFG_QM_TENSOR_15_BASE_ADDR_LOW                        0xE46D48
+
+#define mmTPC1_CFG_QM_TENSOR_15_BASE_ADDR_HIGH                       0xE46D4C
+
+#define mmTPC1_CFG_QM_TENSOR_15_PADDING_VALUE                        0xE46D50
+
+#define mmTPC1_CFG_QM_TENSOR_15_TENSOR_CONFIG                        0xE46D54
+
+#define mmTPC1_CFG_QM_TENSOR_15_DIM_0_SIZE                           0xE46D58
+
+#define mmTPC1_CFG_QM_TENSOR_15_DIM_0_STRIDE                         0xE46D5C
+
+#define mmTPC1_CFG_QM_TENSOR_15_DIM_1_SIZE                           0xE46D60
+
+#define mmTPC1_CFG_QM_TENSOR_15_DIM_1_STRIDE                         0xE46D64
+
+#define mmTPC1_CFG_QM_TENSOR_15_DIM_2_SIZE                           0xE46D68
+
+#define mmTPC1_CFG_QM_TENSOR_15_DIM_2_STRIDE                         0xE46D6C
+
+#define mmTPC1_CFG_QM_TENSOR_15_DIM_3_SIZE                           0xE46D70
+
+#define mmTPC1_CFG_QM_TENSOR_15_DIM_3_STRIDE                         0xE46D74
+
+#define mmTPC1_CFG_QM_TENSOR_15_DIM_4_SIZE                           0xE46D78
+
+#define mmTPC1_CFG_QM_TENSOR_15_DIM_4_STRIDE                         0xE46D7C
+
+#define mmTPC1_CFG_QM_SYNC_OBJECT_MESSAGE                            0xE46D80
+
+#define mmTPC1_CFG_QM_SYNC_OBJECT_ADDR                               0xE46D84
+
+#define mmTPC1_CFG_QM_KERNEL_BASE_ADDRESS_LOW                        0xE46D88
+
+#define mmTPC1_CFG_QM_KERNEL_BASE_ADDRESS_HIGH                       0xE46D8C
+
+#define mmTPC1_CFG_QM_TID_BASE_DIM_0                                 0xE46D90
+
+#define mmTPC1_CFG_QM_TID_SIZE_DIM_0                                 0xE46D94
+
+#define mmTPC1_CFG_QM_TID_BASE_DIM_1                                 0xE46D98
+
+#define mmTPC1_CFG_QM_TID_SIZE_DIM_1                                 0xE46D9C
+
+#define mmTPC1_CFG_QM_TID_BASE_DIM_2                                 0xE46DA0
+
+#define mmTPC1_CFG_QM_TID_SIZE_DIM_2                                 0xE46DA4
+
+#define mmTPC1_CFG_QM_TID_BASE_DIM_3                                 0xE46DA8
+
+#define mmTPC1_CFG_QM_TID_SIZE_DIM_3                                 0xE46DAC
+
+#define mmTPC1_CFG_QM_TID_BASE_DIM_4                                 0xE46DB0
+
+#define mmTPC1_CFG_QM_TID_SIZE_DIM_4                                 0xE46DB4
+
+#define mmTPC1_CFG_QM_KERNEL_CONFIG                                  0xE46DB8
+
+#define mmTPC1_CFG_QM_KERNEL_ID                                      0xE46DBC
+
+#define mmTPC1_CFG_QM_SRF_0                                          0xE46DC0
+
+#define mmTPC1_CFG_QM_SRF_1                                          0xE46DC4
+
+#define mmTPC1_CFG_QM_SRF_2                                          0xE46DC8
+
+#define mmTPC1_CFG_QM_SRF_3                                          0xE46DCC
+
+#define mmTPC1_CFG_QM_SRF_4                                          0xE46DD0
+
+#define mmTPC1_CFG_QM_SRF_5                                          0xE46DD4
+
+#define mmTPC1_CFG_QM_SRF_6                                          0xE46DD8
+
+#define mmTPC1_CFG_QM_SRF_7                                          0xE46DDC
+
+#define mmTPC1_CFG_QM_SRF_8                                          0xE46DE0
+
+#define mmTPC1_CFG_QM_SRF_9                                          0xE46DE4
+
+#define mmTPC1_CFG_QM_SRF_10                                         0xE46DE8
+
+#define mmTPC1_CFG_QM_SRF_11                                         0xE46DEC
+
+#define mmTPC1_CFG_QM_SRF_12                                         0xE46DF0
+
+#define mmTPC1_CFG_QM_SRF_13                                         0xE46DF4
+
+#define mmTPC1_CFG_QM_SRF_14                                         0xE46DF8
+
+#define mmTPC1_CFG_QM_SRF_15                                         0xE46DFC
+
+#define mmTPC1_CFG_QM_SRF_16                                         0xE46E00
+
+#define mmTPC1_CFG_QM_SRF_17                                         0xE46E04
+
+#define mmTPC1_CFG_QM_SRF_18                                         0xE46E08
+
+#define mmTPC1_CFG_QM_SRF_19                                         0xE46E0C
+
+#define mmTPC1_CFG_QM_SRF_20                                         0xE46E10
+
+#define mmTPC1_CFG_QM_SRF_21                                         0xE46E14
+
+#define mmTPC1_CFG_QM_SRF_22                                         0xE46E18
+
+#define mmTPC1_CFG_QM_SRF_23                                         0xE46E1C
+
+#define mmTPC1_CFG_QM_SRF_24                                         0xE46E20
+
+#define mmTPC1_CFG_QM_SRF_25                                         0xE46E24
+
+#define mmTPC1_CFG_QM_SRF_26                                         0xE46E28
+
+#define mmTPC1_CFG_QM_SRF_27                                         0xE46E2C
+
+#define mmTPC1_CFG_QM_SRF_28                                         0xE46E30
+
+#define mmTPC1_CFG_QM_SRF_29                                         0xE46E34
+
+#define mmTPC1_CFG_QM_SRF_30                                         0xE46E38
+
+#define mmTPC1_CFG_QM_SRF_31                                         0xE46E3C
+
+#endif /* ASIC_REG_TPC1_CFG_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc1_qm_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc1_qm_regs.h
new file mode 100644
index 000000000000..af10ef7a87d9
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc1_qm_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_TPC1_QM_REGS_H_
+#define ASIC_REG_TPC1_QM_REGS_H_
+
+/*
+ *****************************************
+ *   TPC1_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmTPC1_QM_GLBL_CFG0                                          0xE48000
+
+#define mmTPC1_QM_GLBL_CFG1                                          0xE48004
+
+#define mmTPC1_QM_GLBL_PROT                                          0xE48008
+
+#define mmTPC1_QM_GLBL_ERR_CFG                                       0xE4800C
+
+#define mmTPC1_QM_GLBL_SECURE_PROPS_0                                0xE48010
+
+#define mmTPC1_QM_GLBL_SECURE_PROPS_1                                0xE48014
+
+#define mmTPC1_QM_GLBL_SECURE_PROPS_2                                0xE48018
+
+#define mmTPC1_QM_GLBL_SECURE_PROPS_3                                0xE4801C
+
+#define mmTPC1_QM_GLBL_SECURE_PROPS_4                                0xE48020
+
+#define mmTPC1_QM_GLBL_NON_SECURE_PROPS_0                            0xE48024
+
+#define mmTPC1_QM_GLBL_NON_SECURE_PROPS_1                            0xE48028
+
+#define mmTPC1_QM_GLBL_NON_SECURE_PROPS_2                            0xE4802C
+
+#define mmTPC1_QM_GLBL_NON_SECURE_PROPS_3                            0xE48030
+
+#define mmTPC1_QM_GLBL_NON_SECURE_PROPS_4                            0xE48034
+
+#define mmTPC1_QM_GLBL_STS0                                          0xE48038
+
+#define mmTPC1_QM_GLBL_STS1_0                                        0xE48040
+
+#define mmTPC1_QM_GLBL_STS1_1                                        0xE48044
+
+#define mmTPC1_QM_GLBL_STS1_2                                        0xE48048
+
+#define mmTPC1_QM_GLBL_STS1_3                                        0xE4804C
+
+#define mmTPC1_QM_GLBL_STS1_4                                        0xE48050
+
+#define mmTPC1_QM_GLBL_MSG_EN_0                                      0xE48054
+
+#define mmTPC1_QM_GLBL_MSG_EN_1                                      0xE48058
+
+#define mmTPC1_QM_GLBL_MSG_EN_2                                      0xE4805C
+
+#define mmTPC1_QM_GLBL_MSG_EN_3                                      0xE48060
+
+#define mmTPC1_QM_GLBL_MSG_EN_4                                      0xE48068
+
+#define mmTPC1_QM_PQ_BASE_LO_0                                       0xE48070
+
+#define mmTPC1_QM_PQ_BASE_LO_1                                       0xE48074
+
+#define mmTPC1_QM_PQ_BASE_LO_2                                       0xE48078
+
+#define mmTPC1_QM_PQ_BASE_LO_3                                       0xE4807C
+
+#define mmTPC1_QM_PQ_BASE_HI_0                                       0xE48080
+
+#define mmTPC1_QM_PQ_BASE_HI_1                                       0xE48084
+
+#define mmTPC1_QM_PQ_BASE_HI_2                                       0xE48088
+
+#define mmTPC1_QM_PQ_BASE_HI_3                                       0xE4808C
+
+#define mmTPC1_QM_PQ_SIZE_0                                          0xE48090
+
+#define mmTPC1_QM_PQ_SIZE_1                                          0xE48094
+
+#define mmTPC1_QM_PQ_SIZE_2                                          0xE48098
+
+#define mmTPC1_QM_PQ_SIZE_3                                          0xE4809C
+
+#define mmTPC1_QM_PQ_PI_0                                            0xE480A0
+
+#define mmTPC1_QM_PQ_PI_1                                            0xE480A4
+
+#define mmTPC1_QM_PQ_PI_2                                            0xE480A8
+
+#define mmTPC1_QM_PQ_PI_3                                            0xE480AC
+
+#define mmTPC1_QM_PQ_CI_0                                            0xE480B0
+
+#define mmTPC1_QM_PQ_CI_1                                            0xE480B4
+
+#define mmTPC1_QM_PQ_CI_2                                            0xE480B8
+
+#define mmTPC1_QM_PQ_CI_3                                            0xE480BC
+
+#define mmTPC1_QM_PQ_CFG0_0                                          0xE480C0
+
+#define mmTPC1_QM_PQ_CFG0_1                                          0xE480C4
+
+#define mmTPC1_QM_PQ_CFG0_2                                          0xE480C8
+
+#define mmTPC1_QM_PQ_CFG0_3                                          0xE480CC
+
+#define mmTPC1_QM_PQ_CFG1_0                                          0xE480D0
+
+#define mmTPC1_QM_PQ_CFG1_1                                          0xE480D4
+
+#define mmTPC1_QM_PQ_CFG1_2                                          0xE480D8
+
+#define mmTPC1_QM_PQ_CFG1_3                                          0xE480DC
+
+#define mmTPC1_QM_PQ_ARUSER_31_11_0                                  0xE480E0
+
+#define mmTPC1_QM_PQ_ARUSER_31_11_1                                  0xE480E4
+
+#define mmTPC1_QM_PQ_ARUSER_31_11_2                                  0xE480E8
+
+#define mmTPC1_QM_PQ_ARUSER_31_11_3                                  0xE480EC
+
+#define mmTPC1_QM_PQ_STS0_0                                          0xE480F0
+
+#define mmTPC1_QM_PQ_STS0_1                                          0xE480F4
+
+#define mmTPC1_QM_PQ_STS0_2                                          0xE480F8
+
+#define mmTPC1_QM_PQ_STS0_3                                          0xE480FC
+
+#define mmTPC1_QM_PQ_STS1_0                                          0xE48100
+
+#define mmTPC1_QM_PQ_STS1_1                                          0xE48104
+
+#define mmTPC1_QM_PQ_STS1_2                                          0xE48108
+
+#define mmTPC1_QM_PQ_STS1_3                                          0xE4810C
+
+#define mmTPC1_QM_CQ_CFG0_0                                          0xE48110
+
+#define mmTPC1_QM_CQ_CFG0_1                                          0xE48114
+
+#define mmTPC1_QM_CQ_CFG0_2                                          0xE48118
+
+#define mmTPC1_QM_CQ_CFG0_3                                          0xE4811C
+
+#define mmTPC1_QM_CQ_CFG0_4                                          0xE48120
+
+#define mmTPC1_QM_CQ_CFG1_0                                          0xE48124
+
+#define mmTPC1_QM_CQ_CFG1_1                                          0xE48128
+
+#define mmTPC1_QM_CQ_CFG1_2                                          0xE4812C
+
+#define mmTPC1_QM_CQ_CFG1_3                                          0xE48130
+
+#define mmTPC1_QM_CQ_CFG1_4                                          0xE48134
+
+#define mmTPC1_QM_CQ_ARUSER_31_11_0                                  0xE48138
+
+#define mmTPC1_QM_CQ_ARUSER_31_11_1                                  0xE4813C
+
+#define mmTPC1_QM_CQ_ARUSER_31_11_2                                  0xE48140
+
+#define mmTPC1_QM_CQ_ARUSER_31_11_3                                  0xE48144
+
+#define mmTPC1_QM_CQ_ARUSER_31_11_4                                  0xE48148
+
+#define mmTPC1_QM_CQ_STS0_0                                          0xE4814C
+
+#define mmTPC1_QM_CQ_STS0_1                                          0xE48150
+
+#define mmTPC1_QM_CQ_STS0_2                                          0xE48154
+
+#define mmTPC1_QM_CQ_STS0_3                                          0xE48158
+
+#define mmTPC1_QM_CQ_STS0_4                                          0xE4815C
+
+#define mmTPC1_QM_CQ_STS1_0                                          0xE48160
+
+#define mmTPC1_QM_CQ_STS1_1                                          0xE48164
+
+#define mmTPC1_QM_CQ_STS1_2                                          0xE48168
+
+#define mmTPC1_QM_CQ_STS1_3                                          0xE4816C
+
+#define mmTPC1_QM_CQ_STS1_4                                          0xE48170
+
+#define mmTPC1_QM_CQ_PTR_LO_0                                        0xE48174
+
+#define mmTPC1_QM_CQ_PTR_HI_0                                        0xE48178
+
+#define mmTPC1_QM_CQ_TSIZE_0                                         0xE4817C
+
+#define mmTPC1_QM_CQ_CTL_0                                           0xE48180
+
+#define mmTPC1_QM_CQ_PTR_LO_1                                        0xE48184
+
+#define mmTPC1_QM_CQ_PTR_HI_1                                        0xE48188
+
+#define mmTPC1_QM_CQ_TSIZE_1                                         0xE4818C
+
+#define mmTPC1_QM_CQ_CTL_1                                           0xE48190
+
+#define mmTPC1_QM_CQ_PTR_LO_2                                        0xE48194
+
+#define mmTPC1_QM_CQ_PTR_HI_2                                        0xE48198
+
+#define mmTPC1_QM_CQ_TSIZE_2                                         0xE4819C
+
+#define mmTPC1_QM_CQ_CTL_2                                           0xE481A0
+
+#define mmTPC1_QM_CQ_PTR_LO_3                                        0xE481A4
+
+#define mmTPC1_QM_CQ_PTR_HI_3                                        0xE481A8
+
+#define mmTPC1_QM_CQ_TSIZE_3                                         0xE481AC
+
+#define mmTPC1_QM_CQ_CTL_3                                           0xE481B0
+
+#define mmTPC1_QM_CQ_PTR_LO_4                                        0xE481B4
+
+#define mmTPC1_QM_CQ_PTR_HI_4                                        0xE481B8
+
+#define mmTPC1_QM_CQ_TSIZE_4                                         0xE481BC
+
+#define mmTPC1_QM_CQ_CTL_4                                           0xE481C0
+
+#define mmTPC1_QM_CQ_PTR_LO_STS_0                                    0xE481C4
+
+#define mmTPC1_QM_CQ_PTR_LO_STS_1                                    0xE481C8
+
+#define mmTPC1_QM_CQ_PTR_LO_STS_2                                    0xE481CC
+
+#define mmTPC1_QM_CQ_PTR_LO_STS_3                                    0xE481D0
+
+#define mmTPC1_QM_CQ_PTR_LO_STS_4                                    0xE481D4
+
+#define mmTPC1_QM_CQ_PTR_HI_STS_0                                    0xE481D8
+
+#define mmTPC1_QM_CQ_PTR_HI_STS_1                                    0xE481DC
+
+#define mmTPC1_QM_CQ_PTR_HI_STS_2                                    0xE481E0
+
+#define mmTPC1_QM_CQ_PTR_HI_STS_3                                    0xE481E4
+
+#define mmTPC1_QM_CQ_PTR_HI_STS_4                                    0xE481E8
+
+#define mmTPC1_QM_CQ_TSIZE_STS_0                                     0xE481EC
+
+#define mmTPC1_QM_CQ_TSIZE_STS_1                                     0xE481F0
+
+#define mmTPC1_QM_CQ_TSIZE_STS_2                                     0xE481F4
+
+#define mmTPC1_QM_CQ_TSIZE_STS_3                                     0xE481F8
+
+#define mmTPC1_QM_CQ_TSIZE_STS_4                                     0xE481FC
+
+#define mmTPC1_QM_CQ_CTL_STS_0                                       0xE48200
+
+#define mmTPC1_QM_CQ_CTL_STS_1                                       0xE48204
+
+#define mmTPC1_QM_CQ_CTL_STS_2                                       0xE48208
+
+#define mmTPC1_QM_CQ_CTL_STS_3                                       0xE4820C
+
+#define mmTPC1_QM_CQ_CTL_STS_4                                       0xE48210
+
+#define mmTPC1_QM_CQ_IFIFO_CNT_0                                     0xE48214
+
+#define mmTPC1_QM_CQ_IFIFO_CNT_1                                     0xE48218
+
+#define mmTPC1_QM_CQ_IFIFO_CNT_2                                     0xE4821C
+
+#define mmTPC1_QM_CQ_IFIFO_CNT_3                                     0xE48220
+
+#define mmTPC1_QM_CQ_IFIFO_CNT_4                                     0xE48224
+
+#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_0                             0xE48228
+
+#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_1                             0xE4822C
+
+#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_2                             0xE48230
+
+#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_3                             0xE48234
+
+#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_4                             0xE48238
+
+#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_0                             0xE4823C
+
+#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_1                             0xE48240
+
+#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_2                             0xE48244
+
+#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_3                             0xE48248
+
+#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_4                             0xE4824C
+
+#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_0                             0xE48250
+
+#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_1                             0xE48254
+
+#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_2                             0xE48258
+
+#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_3                             0xE4825C
+
+#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_4                             0xE48260
+
+#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_0                             0xE48264
+
+#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_1                             0xE48268
+
+#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_2                             0xE4826C
+
+#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_3                             0xE48270
+
+#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_4                             0xE48274
+
+#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_0                             0xE48278
+
+#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_1                             0xE4827C
+
+#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_2                             0xE48280
+
+#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_3                             0xE48284
+
+#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_4                             0xE48288
+
+#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_0                             0xE4828C
+
+#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_1                             0xE48290
+
+#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_2                             0xE48294
+
+#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_3                             0xE48298
+
+#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_4                             0xE4829C
+
+#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_0                             0xE482A0
+
+#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_1                             0xE482A4
+
+#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_2                             0xE482A8
+
+#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_3                             0xE482AC
+
+#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_4                             0xE482B0
+
+#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_0                             0xE482B4
+
+#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_1                             0xE482B8
+
+#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_2                             0xE482BC
+
+#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_3                             0xE482C0
+
+#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_4                             0xE482C4
+
+#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_0                             0xE482C8
+
+#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_1                             0xE482CC
+
+#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_2                             0xE482D0
+
+#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_3                             0xE482D4
+
+#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_4                             0xE482D8
+
+#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0                       0xE482E0
+
+#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1                       0xE482E4
+
+#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2                       0xE482E8
+
+#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3                       0xE482EC
+
+#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4                       0xE482F0
+
+#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_0                       0xE482F4
+
+#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_1                       0xE482F8
+
+#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_2                       0xE482FC
+
+#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3                       0xE48300
+
+#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_4                       0xE48304
+
+#define mmTPC1_QM_CP_FENCE0_RDATA_0                                  0xE48308
+
+#define mmTPC1_QM_CP_FENCE0_RDATA_1                                  0xE4830C
+
+#define mmTPC1_QM_CP_FENCE0_RDATA_2                                  0xE48310
+
+#define mmTPC1_QM_CP_FENCE0_RDATA_3                                  0xE48314
+
+#define mmTPC1_QM_CP_FENCE0_RDATA_4                                  0xE48318
+
+#define mmTPC1_QM_CP_FENCE1_RDATA_0                                  0xE4831C
+
+#define mmTPC1_QM_CP_FENCE1_RDATA_1                                  0xE48320
+
+#define mmTPC1_QM_CP_FENCE1_RDATA_2                                  0xE48324
+
+#define mmTPC1_QM_CP_FENCE1_RDATA_3                                  0xE48328
+
+#define mmTPC1_QM_CP_FENCE1_RDATA_4                                  0xE4832C
+
+#define mmTPC1_QM_CP_FENCE2_RDATA_0                                  0xE48330
+
+#define mmTPC1_QM_CP_FENCE2_RDATA_1                                  0xE48334
+
+#define mmTPC1_QM_CP_FENCE2_RDATA_2                                  0xE48338
+
+#define mmTPC1_QM_CP_FENCE2_RDATA_3                                  0xE4833C
+
+#define mmTPC1_QM_CP_FENCE2_RDATA_4                                  0xE48340
+
+#define mmTPC1_QM_CP_FENCE3_RDATA_0                                  0xE48344
+
+#define mmTPC1_QM_CP_FENCE3_RDATA_1                                  0xE48348
+
+#define mmTPC1_QM_CP_FENCE3_RDATA_2                                  0xE4834C
+
+#define mmTPC1_QM_CP_FENCE3_RDATA_3                                  0xE48350
+
+#define mmTPC1_QM_CP_FENCE3_RDATA_4                                  0xE48354
+
+#define mmTPC1_QM_CP_FENCE0_CNT_0                                    0xE48358
+
+#define mmTPC1_QM_CP_FENCE0_CNT_1                                    0xE4835C
+
+#define mmTPC1_QM_CP_FENCE0_CNT_2                                    0xE48360
+
+#define mmTPC1_QM_CP_FENCE0_CNT_3                                    0xE48364
+
+#define mmTPC1_QM_CP_FENCE0_CNT_4                                    0xE48368
+
+#define mmTPC1_QM_CP_FENCE1_CNT_0                                    0xE4836C
+
+#define mmTPC1_QM_CP_FENCE1_CNT_1                                    0xE48370
+
+#define mmTPC1_QM_CP_FENCE1_CNT_2                                    0xE48374
+
+#define mmTPC1_QM_CP_FENCE1_CNT_3                                    0xE48378
+
+#define mmTPC1_QM_CP_FENCE1_CNT_4                                    0xE4837C
+
+#define mmTPC1_QM_CP_FENCE2_CNT_0                                    0xE48380
+
+#define mmTPC1_QM_CP_FENCE2_CNT_1                                    0xE48384
+
+#define mmTPC1_QM_CP_FENCE2_CNT_2                                    0xE48388
+
+#define mmTPC1_QM_CP_FENCE2_CNT_3                                    0xE4838C
+
+#define mmTPC1_QM_CP_FENCE2_CNT_4                                    0xE48390
+
+#define mmTPC1_QM_CP_FENCE3_CNT_0                                    0xE48394
+
+#define mmTPC1_QM_CP_FENCE3_CNT_1                                    0xE48398
+
+#define mmTPC1_QM_CP_FENCE3_CNT_2                                    0xE4839C
+
+#define mmTPC1_QM_CP_FENCE3_CNT_3                                    0xE483A0
+
+#define mmTPC1_QM_CP_FENCE3_CNT_4                                    0xE483A4
+
+#define mmTPC1_QM_CP_STS_0                                           0xE483A8
+
+#define mmTPC1_QM_CP_STS_1                                           0xE483AC
+
+#define mmTPC1_QM_CP_STS_2                                           0xE483B0
+
+#define mmTPC1_QM_CP_STS_3                                           0xE483B4
+
+#define mmTPC1_QM_CP_STS_4                                           0xE483B8
+
+#define mmTPC1_QM_CP_CURRENT_INST_LO_0                               0xE483BC
+
+#define mmTPC1_QM_CP_CURRENT_INST_LO_1                               0xE483C0
+
+#define mmTPC1_QM_CP_CURRENT_INST_LO_2                               0xE483C4
+
+#define mmTPC1_QM_CP_CURRENT_INST_LO_3                               0xE483C8
+
+#define mmTPC1_QM_CP_CURRENT_INST_LO_4                               0xE483CC
+
+#define mmTPC1_QM_CP_CURRENT_INST_HI_0                               0xE483D0
+
+#define mmTPC1_QM_CP_CURRENT_INST_HI_1                               0xE483D4
+
+#define mmTPC1_QM_CP_CURRENT_INST_HI_2                               0xE483D8
+
+#define mmTPC1_QM_CP_CURRENT_INST_HI_3                               0xE483DC
+
+#define mmTPC1_QM_CP_CURRENT_INST_HI_4                               0xE483E0
+
+#define mmTPC1_QM_CP_BARRIER_CFG_0                                   0xE483F4
+
+#define mmTPC1_QM_CP_BARRIER_CFG_1                                   0xE483F8
+
+#define mmTPC1_QM_CP_BARRIER_CFG_2                                   0xE483FC
+
+#define mmTPC1_QM_CP_BARRIER_CFG_3                                   0xE48400
+
+#define mmTPC1_QM_CP_BARRIER_CFG_4                                   0xE48404
+
+#define mmTPC1_QM_CP_DBG_0_0                                         0xE48408
+
+#define mmTPC1_QM_CP_DBG_0_1                                         0xE4840C
+
+#define mmTPC1_QM_CP_DBG_0_2                                         0xE48410
+
+#define mmTPC1_QM_CP_DBG_0_3                                         0xE48414
+
+#define mmTPC1_QM_CP_DBG_0_4                                         0xE48418
+
+#define mmTPC1_QM_CP_ARUSER_31_11_0                                  0xE4841C
+
+#define mmTPC1_QM_CP_ARUSER_31_11_1                                  0xE48420
+
+#define mmTPC1_QM_CP_ARUSER_31_11_2                                  0xE48424
+
+#define mmTPC1_QM_CP_ARUSER_31_11_3                                  0xE48428
+
+#define mmTPC1_QM_CP_ARUSER_31_11_4                                  0xE4842C
+
+#define mmTPC1_QM_CP_AWUSER_31_11_0                                  0xE48430
+
+#define mmTPC1_QM_CP_AWUSER_31_11_1                                  0xE48434
+
+#define mmTPC1_QM_CP_AWUSER_31_11_2                                  0xE48438
+
+#define mmTPC1_QM_CP_AWUSER_31_11_3                                  0xE4843C
+
+#define mmTPC1_QM_CP_AWUSER_31_11_4                                  0xE48440
+
+#define mmTPC1_QM_ARB_CFG_0                                          0xE48A00
+
+#define mmTPC1_QM_ARB_CHOISE_Q_PUSH                                  0xE48A04
+
+#define mmTPC1_QM_ARB_WRR_WEIGHT_0                                   0xE48A08
+
+#define mmTPC1_QM_ARB_WRR_WEIGHT_1                                   0xE48A0C
+
+#define mmTPC1_QM_ARB_WRR_WEIGHT_2                                   0xE48A10
+
+#define mmTPC1_QM_ARB_WRR_WEIGHT_3                                   0xE48A14
+
+#define mmTPC1_QM_ARB_CFG_1                                          0xE48A18
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_0                               0xE48A20
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_1                               0xE48A24
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_2                               0xE48A28
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_3                               0xE48A2C
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_4                               0xE48A30
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_5                               0xE48A34
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_6                               0xE48A38
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_7                               0xE48A3C
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_8                               0xE48A40
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_9                               0xE48A44
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_10                              0xE48A48
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_11                              0xE48A4C
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_12                              0xE48A50
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_13                              0xE48A54
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_14                              0xE48A58
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_15                              0xE48A5C
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_16                              0xE48A60
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_17                              0xE48A64
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_18                              0xE48A68
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_19                              0xE48A6C
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_20                              0xE48A70
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_21                              0xE48A74
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_22                              0xE48A78
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_23                              0xE48A7C
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_24                              0xE48A80
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_25                              0xE48A84
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_26                              0xE48A88
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_27                              0xE48A8C
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_28                              0xE48A90
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_29                              0xE48A94
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_30                              0xE48A98
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_31                              0xE48A9C
+
+#define mmTPC1_QM_ARB_MST_CRED_INC                                   0xE48AA0
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_0                         0xE48AA4
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_1                         0xE48AA8
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_2                         0xE48AAC
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_3                         0xE48AB0
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_4                         0xE48AB4
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_5                         0xE48AB8
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_6                         0xE48ABC
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_7                         0xE48AC0
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_8                         0xE48AC4
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_9                         0xE48AC8
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_10                        0xE48ACC
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_11                        0xE48AD0
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_12                        0xE48AD4
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_13                        0xE48AD8
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_14                        0xE48ADC
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_15                        0xE48AE0
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_16                        0xE48AE4
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_17                        0xE48AE8
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_18                        0xE48AEC
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_19                        0xE48AF0
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_20                        0xE48AF4
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_21                        0xE48AF8
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_22                        0xE48AFC
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_23                        0xE48B00
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_24                        0xE48B04
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_25                        0xE48B08
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_26                        0xE48B0C
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_27                        0xE48B10
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_28                        0xE48B14
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_29                        0xE48B18
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_30                        0xE48B1C
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_31                        0xE48B20
+
+#define mmTPC1_QM_ARB_SLV_MASTER_INC_CRED_OFST                       0xE48B28
+
+#define mmTPC1_QM_ARB_MST_SLAVE_EN                                   0xE48B2C
+
+#define mmTPC1_QM_ARB_MST_QUIET_PER                                  0xE48B34
+
+#define mmTPC1_QM_ARB_SLV_CHOISE_WDT                                 0xE48B38
+
+#define mmTPC1_QM_ARB_SLV_ID                                         0xE48B3C
+
+#define mmTPC1_QM_ARB_MSG_MAX_INFLIGHT                               0xE48B44
+
+#define mmTPC1_QM_ARB_MSG_AWUSER_31_11                               0xE48B48
+
+#define mmTPC1_QM_ARB_MSG_AWUSER_SEC_PROP                            0xE48B4C
+
+#define mmTPC1_QM_ARB_MSG_AWUSER_NON_SEC_PROP                        0xE48B50
+
+#define mmTPC1_QM_ARB_BASE_LO                                        0xE48B54
+
+#define mmTPC1_QM_ARB_BASE_HI                                        0xE48B58
+
+#define mmTPC1_QM_ARB_STATE_STS                                      0xE48B80
+
+#define mmTPC1_QM_ARB_CHOISE_FULLNESS_STS                            0xE48B84
+
+#define mmTPC1_QM_ARB_MSG_STS                                        0xE48B88
+
+#define mmTPC1_QM_ARB_SLV_CHOISE_Q_HEAD                              0xE48B8C
+
+#define mmTPC1_QM_ARB_ERR_CAUSE                                      0xE48B9C
+
+#define mmTPC1_QM_ARB_ERR_MSG_EN                                     0xE48BA0
+
+#define mmTPC1_QM_ARB_ERR_STS_DRP                                    0xE48BA8
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_0                                 0xE48BB0
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_1                                 0xE48BB4
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_2                                 0xE48BB8
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_3                                 0xE48BBC
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_4                                 0xE48BC0
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_5                                 0xE48BC4
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_6                                 0xE48BC8
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_7                                 0xE48BCC
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_8                                 0xE48BD0
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_9                                 0xE48BD4
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_10                                0xE48BD8
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_11                                0xE48BDC
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_12                                0xE48BE0
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_13                                0xE48BE4
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_14                                0xE48BE8
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_15                                0xE48BEC
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_16                                0xE48BF0
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_17                                0xE48BF4
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_18                                0xE48BF8
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_19                                0xE48BFC
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_20                                0xE48C00
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_21                                0xE48C04
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_22                                0xE48C08
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_23                                0xE48C0C
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_24                                0xE48C10
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_25                                0xE48C14
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_26                                0xE48C18
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_27                                0xE48C1C
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_28                                0xE48C20
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_29                                0xE48C24
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_30                                0xE48C28
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_31                                0xE48C2C
+
+#define mmTPC1_QM_CGM_CFG                                            0xE48C70
+
+#define mmTPC1_QM_CGM_STS                                            0xE48C74
+
+#define mmTPC1_QM_CGM_CFG1                                           0xE48C78
+
+#define mmTPC1_QM_LOCAL_RANGE_BASE                                   0xE48C80
+
+#define mmTPC1_QM_LOCAL_RANGE_SIZE                                   0xE48C84
+
+#define mmTPC1_QM_CSMR_STRICT_PRIO_CFG                               0xE48C90
+
+#define mmTPC1_QM_HBW_RD_RATE_LIM_CFG_1                              0xE48C94
+
+#define mmTPC1_QM_LBW_WR_RATE_LIM_CFG_0                              0xE48C98
+
+#define mmTPC1_QM_LBW_WR_RATE_LIM_CFG_1                              0xE48C9C
+
+#define mmTPC1_QM_HBW_RD_RATE_LIM_CFG_0                              0xE48CA0
+
+#define mmTPC1_QM_GLBL_AXCACHE                                       0xE48CA4
+
+#define mmTPC1_QM_IND_GW_APB_CFG                                     0xE48CB0
+
+#define mmTPC1_QM_IND_GW_APB_WDATA                                   0xE48CB4
+
+#define mmTPC1_QM_IND_GW_APB_RDATA                                   0xE48CB8
+
+#define mmTPC1_QM_IND_GW_APB_STATUS                                  0xE48CBC
+
+#define mmTPC1_QM_GLBL_ERR_ADDR_LO                                   0xE48CD0
+
+#define mmTPC1_QM_GLBL_ERR_ADDR_HI                                   0xE48CD4
+
+#define mmTPC1_QM_GLBL_ERR_WDATA                                     0xE48CD8
+
+#define mmTPC1_QM_GLBL_MEM_INIT_BUSY                                 0xE48D00
+
+#endif /* ASIC_REG_TPC1_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc2_cfg_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc2_cfg_regs.h
new file mode 100644
index 000000000000..3e77c37952bc
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc2_cfg_regs.h
@@ -0,0 +1,1226 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_TPC2_CFG_REGS_H_
+#define ASIC_REG_TPC2_CFG_REGS_H_
+
+/*
+ *****************************************
+ *   TPC2_CFG (Prototype: TPC)
+ *****************************************
+ */
+
+#define mmTPC2_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW                     0xE86400
+
+#define mmTPC2_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH                    0xE86404
+
+#define mmTPC2_CFG_KERNEL_TENSOR_0_PADDING_VALUE                     0xE86408
+
+#define mmTPC2_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG                     0xE8640C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_0_SIZE                        0xE86410
+
+#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE                      0xE86414
+
+#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_1_SIZE                        0xE86418
+
+#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE                      0xE8641C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_2_SIZE                        0xE86420
+
+#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE                      0xE86424
+
+#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_3_SIZE                        0xE86428
+
+#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE                      0xE8642C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_4_SIZE                        0xE86430
+
+#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE                      0xE86434
+
+#define mmTPC2_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW                     0xE86438
+
+#define mmTPC2_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH                    0xE8643C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_1_PADDING_VALUE                     0xE86440
+
+#define mmTPC2_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG                     0xE86444
+
+#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_0_SIZE                        0xE86448
+
+#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE                      0xE8644C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_1_SIZE                        0xE86450
+
+#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE                      0xE86454
+
+#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_2_SIZE                        0xE86458
+
+#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE                      0xE8645C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_3_SIZE                        0xE86460
+
+#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE                      0xE86464
+
+#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_4_SIZE                        0xE86468
+
+#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE                      0xE8646C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW                     0xE86470
+
+#define mmTPC2_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH                    0xE86474
+
+#define mmTPC2_CFG_KERNEL_TENSOR_2_PADDING_VALUE                     0xE86478
+
+#define mmTPC2_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG                     0xE8647C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_0_SIZE                        0xE86480
+
+#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE                      0xE86484
+
+#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_1_SIZE                        0xE86488
+
+#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE                      0xE8648C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_2_SIZE                        0xE86490
+
+#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE                      0xE86494
+
+#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_3_SIZE                        0xE86498
+
+#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE                      0xE8649C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_4_SIZE                        0xE864A0
+
+#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE                      0xE864A4
+
+#define mmTPC2_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW                     0xE864A8
+
+#define mmTPC2_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH                    0xE864AC
+
+#define mmTPC2_CFG_KERNEL_TENSOR_3_PADDING_VALUE                     0xE864B0
+
+#define mmTPC2_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG                     0xE864B4
+
+#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_0_SIZE                        0xE864B8
+
+#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE                      0xE864BC
+
+#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_1_SIZE                        0xE864C0
+
+#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE                      0xE864C4
+
+#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_2_SIZE                        0xE864C8
+
+#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE                      0xE864CC
+
+#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_3_SIZE                        0xE864D0
+
+#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE                      0xE864D4
+
+#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_4_SIZE                        0xE864D8
+
+#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE                      0xE864DC
+
+#define mmTPC2_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW                     0xE864E0
+
+#define mmTPC2_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH                    0xE864E4
+
+#define mmTPC2_CFG_KERNEL_TENSOR_4_PADDING_VALUE                     0xE864E8
+
+#define mmTPC2_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG                     0xE864EC
+
+#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_0_SIZE                        0xE864F0
+
+#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE                      0xE864F4
+
+#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_1_SIZE                        0xE864F8
+
+#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE                      0xE864FC
+
+#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_2_SIZE                        0xE86500
+
+#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE                      0xE86504
+
+#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_3_SIZE                        0xE86508
+
+#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE                      0xE8650C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_4_SIZE                        0xE86510
+
+#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE                      0xE86514
+
+#define mmTPC2_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW                     0xE86518
+
+#define mmTPC2_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH                    0xE8651C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_5_PADDING_VALUE                     0xE86520
+
+#define mmTPC2_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG                     0xE86524
+
+#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_0_SIZE                        0xE86528
+
+#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE                      0xE8652C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_1_SIZE                        0xE86530
+
+#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE                      0xE86534
+
+#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_2_SIZE                        0xE86538
+
+#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE                      0xE8653C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_3_SIZE                        0xE86540
+
+#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE                      0xE86544
+
+#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_4_SIZE                        0xE86548
+
+#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE                      0xE8654C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW                     0xE86550
+
+#define mmTPC2_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH                    0xE86554
+
+#define mmTPC2_CFG_KERNEL_TENSOR_6_PADDING_VALUE                     0xE86558
+
+#define mmTPC2_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG                     0xE8655C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_0_SIZE                        0xE86560
+
+#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE                      0xE86564
+
+#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_1_SIZE                        0xE86568
+
+#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE                      0xE8656C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_2_SIZE                        0xE86570
+
+#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE                      0xE86574
+
+#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_3_SIZE                        0xE86578
+
+#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE                      0xE8657C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_4_SIZE                        0xE86580
+
+#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE                      0xE86584
+
+#define mmTPC2_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW                     0xE86588
+
+#define mmTPC2_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH                    0xE8658C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_7_PADDING_VALUE                     0xE86590
+
+#define mmTPC2_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG                     0xE86594
+
+#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_0_SIZE                        0xE86598
+
+#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE                      0xE8659C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_1_SIZE                        0xE865A0
+
+#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE                      0xE865A4
+
+#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_2_SIZE                        0xE865A8
+
+#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE                      0xE865AC
+
+#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_3_SIZE                        0xE865B0
+
+#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE                      0xE865B4
+
+#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_4_SIZE                        0xE865B8
+
+#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE                      0xE865BC
+
+#define mmTPC2_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW                     0xE865C0
+
+#define mmTPC2_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH                    0xE865C4
+
+#define mmTPC2_CFG_KERNEL_TENSOR_8_PADDING_VALUE                     0xE865C8
+
+#define mmTPC2_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG                     0xE865CC
+
+#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_0_SIZE                        0xE865D0
+
+#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE                      0xE865D4
+
+#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_1_SIZE                        0xE865D8
+
+#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE                      0xE865DC
+
+#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_2_SIZE                        0xE865E0
+
+#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE                      0xE865E4
+
+#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_3_SIZE                        0xE865E8
+
+#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE                      0xE865EC
+
+#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_4_SIZE                        0xE865F0
+
+#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE                      0xE865F4
+
+#define mmTPC2_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW                     0xE865F8
+
+#define mmTPC2_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH                    0xE865FC
+
+#define mmTPC2_CFG_KERNEL_TENSOR_9_PADDING_VALUE                     0xE86600
+
+#define mmTPC2_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG                     0xE86604
+
+#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_0_SIZE                        0xE86608
+
+#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE                      0xE8660C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_1_SIZE                        0xE86610
+
+#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE                      0xE86614
+
+#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_2_SIZE                        0xE86618
+
+#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE                      0xE8661C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_3_SIZE                        0xE86620
+
+#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE                      0xE86624
+
+#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_4_SIZE                        0xE86628
+
+#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE                      0xE8662C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW                    0xE86630
+
+#define mmTPC2_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH                   0xE86634
+
+#define mmTPC2_CFG_KERNEL_TENSOR_10_PADDING_VALUE                    0xE86638
+
+#define mmTPC2_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG                    0xE8663C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_0_SIZE                       0xE86640
+
+#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE                     0xE86644
+
+#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_1_SIZE                       0xE86648
+
+#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE                     0xE8664C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_2_SIZE                       0xE86650
+
+#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE                     0xE86654
+
+#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_3_SIZE                       0xE86658
+
+#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE                     0xE8665C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_4_SIZE                       0xE86660
+
+#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE                     0xE86664
+
+#define mmTPC2_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW                    0xE86668
+
+#define mmTPC2_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH                   0xE8666C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_11_PADDING_VALUE                    0xE86670
+
+#define mmTPC2_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG                    0xE86674
+
+#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_0_SIZE                       0xE86678
+
+#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE                     0xE8667C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_1_SIZE                       0xE86680
+
+#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE                     0xE86684
+
+#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_2_SIZE                       0xE86688
+
+#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE                     0xE8668C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_3_SIZE                       0xE86690
+
+#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE                     0xE86694
+
+#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_4_SIZE                       0xE86698
+
+#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE                     0xE8669C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW                    0xE866A0
+
+#define mmTPC2_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH                   0xE866A4
+
+#define mmTPC2_CFG_KERNEL_TENSOR_12_PADDING_VALUE                    0xE866A8
+
+#define mmTPC2_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG                    0xE866AC
+
+#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_0_SIZE                       0xE866B0
+
+#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE                     0xE866B4
+
+#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_1_SIZE                       0xE866B8
+
+#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE                     0xE866BC
+
+#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_2_SIZE                       0xE866C0
+
+#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE                     0xE866C4
+
+#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_3_SIZE                       0xE866C8
+
+#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE                     0xE866CC
+
+#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_4_SIZE                       0xE866D0
+
+#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE                     0xE866D4
+
+#define mmTPC2_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW                    0xE866D8
+
+#define mmTPC2_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH                   0xE866DC
+
+#define mmTPC2_CFG_KERNEL_TENSOR_13_PADDING_VALUE                    0xE866E0
+
+#define mmTPC2_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG                    0xE866E4
+
+#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_0_SIZE                       0xE866E8
+
+#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE                     0xE866EC
+
+#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_1_SIZE                       0xE866F0
+
+#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE                     0xE866F4
+
+#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_2_SIZE                       0xE866F8
+
+#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE                     0xE866FC
+
+#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_3_SIZE                       0xE86700
+
+#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE                     0xE86704
+
+#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_4_SIZE                       0xE86708
+
+#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE                     0xE8670C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW                    0xE86710
+
+#define mmTPC2_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH                   0xE86714
+
+#define mmTPC2_CFG_KERNEL_TENSOR_14_PADDING_VALUE                    0xE86718
+
+#define mmTPC2_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG                    0xE8671C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_0_SIZE                       0xE86720
+
+#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE                     0xE86724
+
+#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_1_SIZE                       0xE86728
+
+#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE                     0xE8672C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_2_SIZE                       0xE86730
+
+#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE                     0xE86734
+
+#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_3_SIZE                       0xE86738
+
+#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE                     0xE8673C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_4_SIZE                       0xE86740
+
+#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE                     0xE86744
+
+#define mmTPC2_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW                    0xE86748
+
+#define mmTPC2_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH                   0xE8674C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_15_PADDING_VALUE                    0xE86750
+
+#define mmTPC2_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG                    0xE86754
+
+#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_0_SIZE                       0xE86758
+
+#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE                     0xE8675C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_1_SIZE                       0xE86760
+
+#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE                     0xE86764
+
+#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_2_SIZE                       0xE86768
+
+#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE                     0xE8676C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_3_SIZE                       0xE86770
+
+#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE                     0xE86774
+
+#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_4_SIZE                       0xE86778
+
+#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE                     0xE8677C
+
+#define mmTPC2_CFG_KERNEL_SYNC_OBJECT_MESSAGE                        0xE86780
+
+#define mmTPC2_CFG_KERNEL_SYNC_OBJECT_ADDR                           0xE86784
+
+#define mmTPC2_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW                    0xE86788
+
+#define mmTPC2_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH                   0xE8678C
+
+#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_0                             0xE86790
+
+#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_0                             0xE86794
+
+#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_1                             0xE86798
+
+#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_1                             0xE8679C
+
+#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_2                             0xE867A0
+
+#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_2                             0xE867A4
+
+#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_3                             0xE867A8
+
+#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_3                             0xE867AC
+
+#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_4                             0xE867B0
+
+#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_4                             0xE867B4
+
+#define mmTPC2_CFG_KERNEL_KERNEL_CONFIG                              0xE867B8
+
+#define mmTPC2_CFG_KERNEL_KERNEL_ID                                  0xE867BC
+
+#define mmTPC2_CFG_KERNEL_SRF_0                                      0xE867C0
+
+#define mmTPC2_CFG_KERNEL_SRF_1                                      0xE867C4
+
+#define mmTPC2_CFG_KERNEL_SRF_2                                      0xE867C8
+
+#define mmTPC2_CFG_KERNEL_SRF_3                                      0xE867CC
+
+#define mmTPC2_CFG_KERNEL_SRF_4                                      0xE867D0
+
+#define mmTPC2_CFG_KERNEL_SRF_5                                      0xE867D4
+
+#define mmTPC2_CFG_KERNEL_SRF_6                                      0xE867D8
+
+#define mmTPC2_CFG_KERNEL_SRF_7                                      0xE867DC
+
+#define mmTPC2_CFG_KERNEL_SRF_8                                      0xE867E0
+
+#define mmTPC2_CFG_KERNEL_SRF_9                                      0xE867E4
+
+#define mmTPC2_CFG_KERNEL_SRF_10                                     0xE867E8
+
+#define mmTPC2_CFG_KERNEL_SRF_11                                     0xE867EC
+
+#define mmTPC2_CFG_KERNEL_SRF_12                                     0xE867F0
+
+#define mmTPC2_CFG_KERNEL_SRF_13                                     0xE867F4
+
+#define mmTPC2_CFG_KERNEL_SRF_14                                     0xE867F8
+
+#define mmTPC2_CFG_KERNEL_SRF_15                                     0xE867FC
+
+#define mmTPC2_CFG_KERNEL_SRF_16                                     0xE86800
+
+#define mmTPC2_CFG_KERNEL_SRF_17                                     0xE86804
+
+#define mmTPC2_CFG_KERNEL_SRF_18                                     0xE86808
+
+#define mmTPC2_CFG_KERNEL_SRF_19                                     0xE8680C
+
+#define mmTPC2_CFG_KERNEL_SRF_20                                     0xE86810
+
+#define mmTPC2_CFG_KERNEL_SRF_21                                     0xE86814
+
+#define mmTPC2_CFG_KERNEL_SRF_22                                     0xE86818
+
+#define mmTPC2_CFG_KERNEL_SRF_23                                     0xE8681C
+
+#define mmTPC2_CFG_KERNEL_SRF_24                                     0xE86820
+
+#define mmTPC2_CFG_KERNEL_SRF_25                                     0xE86824
+
+#define mmTPC2_CFG_KERNEL_SRF_26                                     0xE86828
+
+#define mmTPC2_CFG_KERNEL_SRF_27                                     0xE8682C
+
+#define mmTPC2_CFG_KERNEL_SRF_28                                     0xE86830
+
+#define mmTPC2_CFG_KERNEL_SRF_29                                     0xE86834
+
+#define mmTPC2_CFG_KERNEL_SRF_30                                     0xE86838
+
+#define mmTPC2_CFG_KERNEL_SRF_31                                     0xE8683C
+
+#define mmTPC2_CFG_ROUND_CSR                                         0xE868FC
+
+#define mmTPC2_CFG_PROT                                              0xE86900
+
+#define mmTPC2_CFG_SEMAPHORE                                         0xE86908
+
+#define mmTPC2_CFG_VFLAGS                                            0xE8690C
+
+#define mmTPC2_CFG_SFLAGS                                            0xE86910
+
+#define mmTPC2_CFG_LFSR_POLYNOM                                      0xE86918
+
+#define mmTPC2_CFG_STATUS                                            0xE8691C
+
+#define mmTPC2_CFG_CFG_BASE_ADDRESS_HIGH                             0xE86920
+
+#define mmTPC2_CFG_CFG_SUBTRACT_VALUE                                0xE86924
+
+#define mmTPC2_CFG_SM_BASE_ADDRESS_HIGH                              0xE8692C
+
+#define mmTPC2_CFG_TPC_CMD                                           0xE86930
+
+#define mmTPC2_CFG_TPC_EXECUTE                                       0xE86938
+
+#define mmTPC2_CFG_TPC_STALL                                         0xE8693C
+
+#define mmTPC2_CFG_ICACHE_BASE_ADDERESS_LOW                          0xE86940
+
+#define mmTPC2_CFG_ICACHE_BASE_ADDERESS_HIGH                         0xE86944
+
+#define mmTPC2_CFG_RD_RATE_LIMIT                                     0xE86948
+
+#define mmTPC2_CFG_WR_RATE_LIMIT                                     0xE86950
+
+#define mmTPC2_CFG_MSS_CONFIG                                        0xE86954
+
+#define mmTPC2_CFG_TPC_INTR_CAUSE                                    0xE86958
+
+#define mmTPC2_CFG_TPC_INTR_MASK                                     0xE8695C
+
+#define mmTPC2_CFG_WQ_CREDITS                                        0xE86960
+
+#define mmTPC2_CFG_ARUSER_LO                                         0xE86964
+
+#define mmTPC2_CFG_ARUSER_HI                                         0xE86968
+
+#define mmTPC2_CFG_AWUSER_LO                                         0xE8696C
+
+#define mmTPC2_CFG_AWUSER_HI                                         0xE86970
+
+#define mmTPC2_CFG_OPCODE_EXEC                                       0xE86974
+
+#define mmTPC2_CFG_LUT_FUNC32_BASE_ADDR_LO                           0xE86978
+
+#define mmTPC2_CFG_LUT_FUNC32_BASE_ADDR_HI                           0xE8697C
+
+#define mmTPC2_CFG_LUT_FUNC64_BASE_ADDR_LO                           0xE86980
+
+#define mmTPC2_CFG_LUT_FUNC64_BASE_ADDR_HI                           0xE86984
+
+#define mmTPC2_CFG_LUT_FUNC128_BASE_ADDR_LO                          0xE86988
+
+#define mmTPC2_CFG_LUT_FUNC128_BASE_ADDR_HI                          0xE8698C
+
+#define mmTPC2_CFG_LUT_FUNC256_BASE_ADDR_LO                          0xE86990
+
+#define mmTPC2_CFG_LUT_FUNC256_BASE_ADDR_HI                          0xE86994
+
+#define mmTPC2_CFG_TSB_CFG_MAX_SIZE                                  0xE86998
+
+#define mmTPC2_CFG_TSB_CFG                                           0xE8699C
+
+#define mmTPC2_CFG_DBGMEM_ADD                                        0xE869A0
+
+#define mmTPC2_CFG_DBGMEM_DATA_WR                                    0xE869A4
+
+#define mmTPC2_CFG_DBGMEM_DATA_RD                                    0xE869A8
+
+#define mmTPC2_CFG_DBGMEM_CTRL                                       0xE869AC
+
+#define mmTPC2_CFG_DBGMEM_RC                                         0xE869B0
+
+#define mmTPC2_CFG_TSB_INFLIGHT_CNTR                                 0xE869B4
+
+#define mmTPC2_CFG_WQ_INFLIGHT_CNTR                                  0xE869B8
+
+#define mmTPC2_CFG_WQ_LBW_TOTAL_CNTR                                 0xE869BC
+
+#define mmTPC2_CFG_WQ_HBW_TOTAL_CNTR                                 0xE869C0
+
+#define mmTPC2_CFG_IRQ_OCCOUPY_CNTR                                  0xE869C4
+
+#define mmTPC2_CFG_FUNC_MBIST_CNTRL                                  0xE869D0
+
+#define mmTPC2_CFG_FUNC_MBIST_PAT                                    0xE869D4
+
+#define mmTPC2_CFG_FUNC_MBIST_MEM_0                                  0xE869D8
+
+#define mmTPC2_CFG_FUNC_MBIST_MEM_1                                  0xE869DC
+
+#define mmTPC2_CFG_FUNC_MBIST_MEM_2                                  0xE869E0
+
+#define mmTPC2_CFG_FUNC_MBIST_MEM_3                                  0xE869E4
+
+#define mmTPC2_CFG_FUNC_MBIST_MEM_4                                  0xE869E8
+
+#define mmTPC2_CFG_FUNC_MBIST_MEM_5                                  0xE869EC
+
+#define mmTPC2_CFG_FUNC_MBIST_MEM_6                                  0xE869F0
+
+#define mmTPC2_CFG_FUNC_MBIST_MEM_7                                  0xE869F4
+
+#define mmTPC2_CFG_FUNC_MBIST_MEM_8                                  0xE869F8
+
+#define mmTPC2_CFG_FUNC_MBIST_MEM_9                                  0xE869FC
+
+#define mmTPC2_CFG_QM_TENSOR_0_BASE_ADDR_LOW                         0xE86A00
+
+#define mmTPC2_CFG_QM_TENSOR_0_BASE_ADDR_HIGH                        0xE86A04
+
+#define mmTPC2_CFG_QM_TENSOR_0_PADDING_VALUE                         0xE86A08
+
+#define mmTPC2_CFG_QM_TENSOR_0_TENSOR_CONFIG                         0xE86A0C
+
+#define mmTPC2_CFG_QM_TENSOR_0_DIM_0_SIZE                            0xE86A10
+
+#define mmTPC2_CFG_QM_TENSOR_0_DIM_0_STRIDE                          0xE86A14
+
+#define mmTPC2_CFG_QM_TENSOR_0_DIM_1_SIZE                            0xE86A18
+
+#define mmTPC2_CFG_QM_TENSOR_0_DIM_1_STRIDE                          0xE86A1C
+
+#define mmTPC2_CFG_QM_TENSOR_0_DIM_2_SIZE                            0xE86A20
+
+#define mmTPC2_CFG_QM_TENSOR_0_DIM_2_STRIDE                          0xE86A24
+
+#define mmTPC2_CFG_QM_TENSOR_0_DIM_3_SIZE                            0xE86A28
+
+#define mmTPC2_CFG_QM_TENSOR_0_DIM_3_STRIDE                          0xE86A2C
+
+#define mmTPC2_CFG_QM_TENSOR_0_DIM_4_SIZE                            0xE86A30
+
+#define mmTPC2_CFG_QM_TENSOR_0_DIM_4_STRIDE                          0xE86A34
+
+#define mmTPC2_CFG_QM_TENSOR_1_BASE_ADDR_LOW                         0xE86A38
+
+#define mmTPC2_CFG_QM_TENSOR_1_BASE_ADDR_HIGH                        0xE86A3C
+
+#define mmTPC2_CFG_QM_TENSOR_1_PADDING_VALUE                         0xE86A40
+
+#define mmTPC2_CFG_QM_TENSOR_1_TENSOR_CONFIG                         0xE86A44
+
+#define mmTPC2_CFG_QM_TENSOR_1_DIM_0_SIZE                            0xE86A48
+
+#define mmTPC2_CFG_QM_TENSOR_1_DIM_0_STRIDE                          0xE86A4C
+
+#define mmTPC2_CFG_QM_TENSOR_1_DIM_1_SIZE                            0xE86A50
+
+#define mmTPC2_CFG_QM_TENSOR_1_DIM_1_STRIDE                          0xE86A54
+
+#define mmTPC2_CFG_QM_TENSOR_1_DIM_2_SIZE                            0xE86A58
+
+#define mmTPC2_CFG_QM_TENSOR_1_DIM_2_STRIDE                          0xE86A5C
+
+#define mmTPC2_CFG_QM_TENSOR_1_DIM_3_SIZE                            0xE86A60
+
+#define mmTPC2_CFG_QM_TENSOR_1_DIM_3_STRIDE                          0xE86A64
+
+#define mmTPC2_CFG_QM_TENSOR_1_DIM_4_SIZE                            0xE86A68
+
+#define mmTPC2_CFG_QM_TENSOR_1_DIM_4_STRIDE                          0xE86A6C
+
+#define mmTPC2_CFG_QM_TENSOR_2_BASE_ADDR_LOW                         0xE86A70
+
+#define mmTPC2_CFG_QM_TENSOR_2_BASE_ADDR_HIGH                        0xE86A74
+
+#define mmTPC2_CFG_QM_TENSOR_2_PADDING_VALUE                         0xE86A78
+
+#define mmTPC2_CFG_QM_TENSOR_2_TENSOR_CONFIG                         0xE86A7C
+
+#define mmTPC2_CFG_QM_TENSOR_2_DIM_0_SIZE                            0xE86A80
+
+#define mmTPC2_CFG_QM_TENSOR_2_DIM_0_STRIDE                          0xE86A84
+
+#define mmTPC2_CFG_QM_TENSOR_2_DIM_1_SIZE                            0xE86A88
+
+#define mmTPC2_CFG_QM_TENSOR_2_DIM_1_STRIDE                          0xE86A8C
+
+#define mmTPC2_CFG_QM_TENSOR_2_DIM_2_SIZE                            0xE86A90
+
+#define mmTPC2_CFG_QM_TENSOR_2_DIM_2_STRIDE                          0xE86A94
+
+#define mmTPC2_CFG_QM_TENSOR_2_DIM_3_SIZE                            0xE86A98
+
+#define mmTPC2_CFG_QM_TENSOR_2_DIM_3_STRIDE                          0xE86A9C
+
+#define mmTPC2_CFG_QM_TENSOR_2_DIM_4_SIZE                            0xE86AA0
+
+#define mmTPC2_CFG_QM_TENSOR_2_DIM_4_STRIDE                          0xE86AA4
+
+#define mmTPC2_CFG_QM_TENSOR_3_BASE_ADDR_LOW                         0xE86AA8
+
+#define mmTPC2_CFG_QM_TENSOR_3_BASE_ADDR_HIGH                        0xE86AAC
+
+#define mmTPC2_CFG_QM_TENSOR_3_PADDING_VALUE                         0xE86AB0
+
+#define mmTPC2_CFG_QM_TENSOR_3_TENSOR_CONFIG                         0xE86AB4
+
+#define mmTPC2_CFG_QM_TENSOR_3_DIM_0_SIZE                            0xE86AB8
+
+#define mmTPC2_CFG_QM_TENSOR_3_DIM_0_STRIDE                          0xE86ABC
+
+#define mmTPC2_CFG_QM_TENSOR_3_DIM_1_SIZE                            0xE86AC0
+
+#define mmTPC2_CFG_QM_TENSOR_3_DIM_1_STRIDE                          0xE86AC4
+
+#define mmTPC2_CFG_QM_TENSOR_3_DIM_2_SIZE                            0xE86AC8
+
+#define mmTPC2_CFG_QM_TENSOR_3_DIM_2_STRIDE                          0xE86ACC
+
+#define mmTPC2_CFG_QM_TENSOR_3_DIM_3_SIZE                            0xE86AD0
+
+#define mmTPC2_CFG_QM_TENSOR_3_DIM_3_STRIDE                          0xE86AD4
+
+#define mmTPC2_CFG_QM_TENSOR_3_DIM_4_SIZE                            0xE86AD8
+
+#define mmTPC2_CFG_QM_TENSOR_3_DIM_4_STRIDE                          0xE86ADC
+
+#define mmTPC2_CFG_QM_TENSOR_4_BASE_ADDR_LOW                         0xE86AE0
+
+#define mmTPC2_CFG_QM_TENSOR_4_BASE_ADDR_HIGH                        0xE86AE4
+
+#define mmTPC2_CFG_QM_TENSOR_4_PADDING_VALUE                         0xE86AE8
+
+#define mmTPC2_CFG_QM_TENSOR_4_TENSOR_CONFIG                         0xE86AEC
+
+#define mmTPC2_CFG_QM_TENSOR_4_DIM_0_SIZE                            0xE86AF0
+
+#define mmTPC2_CFG_QM_TENSOR_4_DIM_0_STRIDE                          0xE86AF4
+
+#define mmTPC2_CFG_QM_TENSOR_4_DIM_1_SIZE                            0xE86AF8
+
+#define mmTPC2_CFG_QM_TENSOR_4_DIM_1_STRIDE                          0xE86AFC
+
+#define mmTPC2_CFG_QM_TENSOR_4_DIM_2_SIZE                            0xE86B00
+
+#define mmTPC2_CFG_QM_TENSOR_4_DIM_2_STRIDE                          0xE86B04
+
+#define mmTPC2_CFG_QM_TENSOR_4_DIM_3_SIZE                            0xE86B08
+
+#define mmTPC2_CFG_QM_TENSOR_4_DIM_3_STRIDE                          0xE86B0C
+
+#define mmTPC2_CFG_QM_TENSOR_4_DIM_4_SIZE                            0xE86B10
+
+#define mmTPC2_CFG_QM_TENSOR_4_DIM_4_STRIDE                          0xE86B14
+
+#define mmTPC2_CFG_QM_TENSOR_5_BASE_ADDR_LOW                         0xE86B18
+
+#define mmTPC2_CFG_QM_TENSOR_5_BASE_ADDR_HIGH                        0xE86B1C
+
+#define mmTPC2_CFG_QM_TENSOR_5_PADDING_VALUE                         0xE86B20
+
+#define mmTPC2_CFG_QM_TENSOR_5_TENSOR_CONFIG                         0xE86B24
+
+#define mmTPC2_CFG_QM_TENSOR_5_DIM_0_SIZE                            0xE86B28
+
+#define mmTPC2_CFG_QM_TENSOR_5_DIM_0_STRIDE                          0xE86B2C
+
+#define mmTPC2_CFG_QM_TENSOR_5_DIM_1_SIZE                            0xE86B30
+
+#define mmTPC2_CFG_QM_TENSOR_5_DIM_1_STRIDE                          0xE86B34
+
+#define mmTPC2_CFG_QM_TENSOR_5_DIM_2_SIZE                            0xE86B38
+
+#define mmTPC2_CFG_QM_TENSOR_5_DIM_2_STRIDE                          0xE86B3C
+
+#define mmTPC2_CFG_QM_TENSOR_5_DIM_3_SIZE                            0xE86B40
+
+#define mmTPC2_CFG_QM_TENSOR_5_DIM_3_STRIDE                          0xE86B44
+
+#define mmTPC2_CFG_QM_TENSOR_5_DIM_4_SIZE                            0xE86B48
+
+#define mmTPC2_CFG_QM_TENSOR_5_DIM_4_STRIDE                          0xE86B4C
+
+#define mmTPC2_CFG_QM_TENSOR_6_BASE_ADDR_LOW                         0xE86B50
+
+#define mmTPC2_CFG_QM_TENSOR_6_BASE_ADDR_HIGH                        0xE86B54
+
+#define mmTPC2_CFG_QM_TENSOR_6_PADDING_VALUE                         0xE86B58
+
+#define mmTPC2_CFG_QM_TENSOR_6_TENSOR_CONFIG                         0xE86B5C
+
+#define mmTPC2_CFG_QM_TENSOR_6_DIM_0_SIZE                            0xE86B60
+
+#define mmTPC2_CFG_QM_TENSOR_6_DIM_0_STRIDE                          0xE86B64
+
+#define mmTPC2_CFG_QM_TENSOR_6_DIM_1_SIZE                            0xE86B68
+
+#define mmTPC2_CFG_QM_TENSOR_6_DIM_1_STRIDE                          0xE86B6C
+
+#define mmTPC2_CFG_QM_TENSOR_6_DIM_2_SIZE                            0xE86B70
+
+#define mmTPC2_CFG_QM_TENSOR_6_DIM_2_STRIDE                          0xE86B74
+
+#define mmTPC2_CFG_QM_TENSOR_6_DIM_3_SIZE                            0xE86B78
+
+#define mmTPC2_CFG_QM_TENSOR_6_DIM_3_STRIDE                          0xE86B7C
+
+#define mmTPC2_CFG_QM_TENSOR_6_DIM_4_SIZE                            0xE86B80
+
+#define mmTPC2_CFG_QM_TENSOR_6_DIM_4_STRIDE                          0xE86B84
+
+#define mmTPC2_CFG_QM_TENSOR_7_BASE_ADDR_LOW                         0xE86B88
+
+#define mmTPC2_CFG_QM_TENSOR_7_BASE_ADDR_HIGH                        0xE86B8C
+
+#define mmTPC2_CFG_QM_TENSOR_7_PADDING_VALUE                         0xE86B90
+
+#define mmTPC2_CFG_QM_TENSOR_7_TENSOR_CONFIG                         0xE86B94
+
+#define mmTPC2_CFG_QM_TENSOR_7_DIM_0_SIZE                            0xE86B98
+
+#define mmTPC2_CFG_QM_TENSOR_7_DIM_0_STRIDE                          0xE86B9C
+
+#define mmTPC2_CFG_QM_TENSOR_7_DIM_1_SIZE                            0xE86BA0
+
+#define mmTPC2_CFG_QM_TENSOR_7_DIM_1_STRIDE                          0xE86BA4
+
+#define mmTPC2_CFG_QM_TENSOR_7_DIM_2_SIZE                            0xE86BA8
+
+#define mmTPC2_CFG_QM_TENSOR_7_DIM_2_STRIDE                          0xE86BAC
+
+#define mmTPC2_CFG_QM_TENSOR_7_DIM_3_SIZE                            0xE86BB0
+
+#define mmTPC2_CFG_QM_TENSOR_7_DIM_3_STRIDE                          0xE86BB4
+
+#define mmTPC2_CFG_QM_TENSOR_7_DIM_4_SIZE                            0xE86BB8
+
+#define mmTPC2_CFG_QM_TENSOR_7_DIM_4_STRIDE                          0xE86BBC
+
+#define mmTPC2_CFG_QM_TENSOR_8_BASE_ADDR_LOW                         0xE86BC0
+
+#define mmTPC2_CFG_QM_TENSOR_8_BASE_ADDR_HIGH                        0xE86BC4
+
+#define mmTPC2_CFG_QM_TENSOR_8_PADDING_VALUE                         0xE86BC8
+
+#define mmTPC2_CFG_QM_TENSOR_8_TENSOR_CONFIG                         0xE86BCC
+
+#define mmTPC2_CFG_QM_TENSOR_8_DIM_0_SIZE                            0xE86BD0
+
+#define mmTPC2_CFG_QM_TENSOR_8_DIM_0_STRIDE                          0xE86BD4
+
+#define mmTPC2_CFG_QM_TENSOR_8_DIM_1_SIZE                            0xE86BD8
+
+#define mmTPC2_CFG_QM_TENSOR_8_DIM_1_STRIDE                          0xE86BDC
+
+#define mmTPC2_CFG_QM_TENSOR_8_DIM_2_SIZE                            0xE86BE0
+
+#define mmTPC2_CFG_QM_TENSOR_8_DIM_2_STRIDE                          0xE86BE4
+
+#define mmTPC2_CFG_QM_TENSOR_8_DIM_3_SIZE                            0xE86BE8
+
+#define mmTPC2_CFG_QM_TENSOR_8_DIM_3_STRIDE                          0xE86BEC
+
+#define mmTPC2_CFG_QM_TENSOR_8_DIM_4_SIZE                            0xE86BF0
+
+#define mmTPC2_CFG_QM_TENSOR_8_DIM_4_STRIDE                          0xE86BF4
+
+#define mmTPC2_CFG_QM_TENSOR_9_BASE_ADDR_LOW                         0xE86BF8
+
+#define mmTPC2_CFG_QM_TENSOR_9_BASE_ADDR_HIGH                        0xE86BFC
+
+#define mmTPC2_CFG_QM_TENSOR_9_PADDING_VALUE                         0xE86C00
+
+#define mmTPC2_CFG_QM_TENSOR_9_TENSOR_CONFIG                         0xE86C04
+
+#define mmTPC2_CFG_QM_TENSOR_9_DIM_0_SIZE                            0xE86C08
+
+#define mmTPC2_CFG_QM_TENSOR_9_DIM_0_STRIDE                          0xE86C0C
+
+#define mmTPC2_CFG_QM_TENSOR_9_DIM_1_SIZE                            0xE86C10
+
+#define mmTPC2_CFG_QM_TENSOR_9_DIM_1_STRIDE                          0xE86C14
+
+#define mmTPC2_CFG_QM_TENSOR_9_DIM_2_SIZE                            0xE86C18
+
+#define mmTPC2_CFG_QM_TENSOR_9_DIM_2_STRIDE                          0xE86C1C
+
+#define mmTPC2_CFG_QM_TENSOR_9_DIM_3_SIZE                            0xE86C20
+
+#define mmTPC2_CFG_QM_TENSOR_9_DIM_3_STRIDE                          0xE86C24
+
+#define mmTPC2_CFG_QM_TENSOR_9_DIM_4_SIZE                            0xE86C28
+
+#define mmTPC2_CFG_QM_TENSOR_9_DIM_4_STRIDE                          0xE86C2C
+
+#define mmTPC2_CFG_QM_TENSOR_10_BASE_ADDR_LOW                        0xE86C30
+
+#define mmTPC2_CFG_QM_TENSOR_10_BASE_ADDR_HIGH                       0xE86C34
+
+#define mmTPC2_CFG_QM_TENSOR_10_PADDING_VALUE                        0xE86C38
+
+#define mmTPC2_CFG_QM_TENSOR_10_TENSOR_CONFIG                        0xE86C3C
+
+#define mmTPC2_CFG_QM_TENSOR_10_DIM_0_SIZE                           0xE86C40
+
+#define mmTPC2_CFG_QM_TENSOR_10_DIM_0_STRIDE                         0xE86C44
+
+#define mmTPC2_CFG_QM_TENSOR_10_DIM_1_SIZE                           0xE86C48
+
+#define mmTPC2_CFG_QM_TENSOR_10_DIM_1_STRIDE                         0xE86C4C
+
+#define mmTPC2_CFG_QM_TENSOR_10_DIM_2_SIZE                           0xE86C50
+
+#define mmTPC2_CFG_QM_TENSOR_10_DIM_2_STRIDE                         0xE86C54
+
+#define mmTPC2_CFG_QM_TENSOR_10_DIM_3_SIZE                           0xE86C58
+
+#define mmTPC2_CFG_QM_TENSOR_10_DIM_3_STRIDE                         0xE86C5C
+
+#define mmTPC2_CFG_QM_TENSOR_10_DIM_4_SIZE                           0xE86C60
+
+#define mmTPC2_CFG_QM_TENSOR_10_DIM_4_STRIDE                         0xE86C64
+
+#define mmTPC2_CFG_QM_TENSOR_11_BASE_ADDR_LOW                        0xE86C68
+
+#define mmTPC2_CFG_QM_TENSOR_11_BASE_ADDR_HIGH                       0xE86C6C
+
+#define mmTPC2_CFG_QM_TENSOR_11_PADDING_VALUE                        0xE86C70
+
+#define mmTPC2_CFG_QM_TENSOR_11_TENSOR_CONFIG                        0xE86C74
+
+#define mmTPC2_CFG_QM_TENSOR_11_DIM_0_SIZE                           0xE86C78
+
+#define mmTPC2_CFG_QM_TENSOR_11_DIM_0_STRIDE                         0xE86C7C
+
+#define mmTPC2_CFG_QM_TENSOR_11_DIM_1_SIZE                           0xE86C80
+
+#define mmTPC2_CFG_QM_TENSOR_11_DIM_1_STRIDE                         0xE86C84
+
+#define mmTPC2_CFG_QM_TENSOR_11_DIM_2_SIZE                           0xE86C88
+
+#define mmTPC2_CFG_QM_TENSOR_11_DIM_2_STRIDE                         0xE86C8C
+
+#define mmTPC2_CFG_QM_TENSOR_11_DIM_3_SIZE                           0xE86C90
+
+#define mmTPC2_CFG_QM_TENSOR_11_DIM_3_STRIDE                         0xE86C94
+
+#define mmTPC2_CFG_QM_TENSOR_11_DIM_4_SIZE                           0xE86C98
+
+#define mmTPC2_CFG_QM_TENSOR_11_DIM_4_STRIDE                         0xE86C9C
+
+#define mmTPC2_CFG_QM_TENSOR_12_BASE_ADDR_LOW                        0xE86CA0
+
+#define mmTPC2_CFG_QM_TENSOR_12_BASE_ADDR_HIGH                       0xE86CA4
+
+#define mmTPC2_CFG_QM_TENSOR_12_PADDING_VALUE                        0xE86CA8
+
+#define mmTPC2_CFG_QM_TENSOR_12_TENSOR_CONFIG                        0xE86CAC
+
+#define mmTPC2_CFG_QM_TENSOR_12_DIM_0_SIZE                           0xE86CB0
+
+#define mmTPC2_CFG_QM_TENSOR_12_DIM_0_STRIDE                         0xE86CB4
+
+#define mmTPC2_CFG_QM_TENSOR_12_DIM_1_SIZE                           0xE86CB8
+
+#define mmTPC2_CFG_QM_TENSOR_12_DIM_1_STRIDE                         0xE86CBC
+
+#define mmTPC2_CFG_QM_TENSOR_12_DIM_2_SIZE                           0xE86CC0
+
+#define mmTPC2_CFG_QM_TENSOR_12_DIM_2_STRIDE                         0xE86CC4
+
+#define mmTPC2_CFG_QM_TENSOR_12_DIM_3_SIZE                           0xE86CC8
+
+#define mmTPC2_CFG_QM_TENSOR_12_DIM_3_STRIDE                         0xE86CCC
+
+#define mmTPC2_CFG_QM_TENSOR_12_DIM_4_SIZE                           0xE86CD0
+
+#define mmTPC2_CFG_QM_TENSOR_12_DIM_4_STRIDE                         0xE86CD4
+
+#define mmTPC2_CFG_QM_TENSOR_13_BASE_ADDR_LOW                        0xE86CD8
+
+#define mmTPC2_CFG_QM_TENSOR_13_BASE_ADDR_HIGH                       0xE86CDC
+
+#define mmTPC2_CFG_QM_TENSOR_13_PADDING_VALUE                        0xE86CE0
+
+#define mmTPC2_CFG_QM_TENSOR_13_TENSOR_CONFIG                        0xE86CE4
+
+#define mmTPC2_CFG_QM_TENSOR_13_DIM_0_SIZE                           0xE86CE8
+
+#define mmTPC2_CFG_QM_TENSOR_13_DIM_0_STRIDE                         0xE86CEC
+
+#define mmTPC2_CFG_QM_TENSOR_13_DIM_1_SIZE                           0xE86CF0
+
+#define mmTPC2_CFG_QM_TENSOR_13_DIM_1_STRIDE                         0xE86CF4
+
+#define mmTPC2_CFG_QM_TENSOR_13_DIM_2_SIZE                           0xE86CF8
+
+#define mmTPC2_CFG_QM_TENSOR_13_DIM_2_STRIDE                         0xE86CFC
+
+#define mmTPC2_CFG_QM_TENSOR_13_DIM_3_SIZE                           0xE86D00
+
+#define mmTPC2_CFG_QM_TENSOR_13_DIM_3_STRIDE                         0xE86D04
+
+#define mmTPC2_CFG_QM_TENSOR_13_DIM_4_SIZE                           0xE86D08
+
+#define mmTPC2_CFG_QM_TENSOR_13_DIM_4_STRIDE                         0xE86D0C
+
+#define mmTPC2_CFG_QM_TENSOR_14_BASE_ADDR_LOW                        0xE86D10
+
+#define mmTPC2_CFG_QM_TENSOR_14_BASE_ADDR_HIGH                       0xE86D14
+
+#define mmTPC2_CFG_QM_TENSOR_14_PADDING_VALUE                        0xE86D18
+
+#define mmTPC2_CFG_QM_TENSOR_14_TENSOR_CONFIG                        0xE86D1C
+
+#define mmTPC2_CFG_QM_TENSOR_14_DIM_0_SIZE                           0xE86D20
+
+#define mmTPC2_CFG_QM_TENSOR_14_DIM_0_STRIDE                         0xE86D24
+
+#define mmTPC2_CFG_QM_TENSOR_14_DIM_1_SIZE                           0xE86D28
+
+#define mmTPC2_CFG_QM_TENSOR_14_DIM_1_STRIDE                         0xE86D2C
+
+#define mmTPC2_CFG_QM_TENSOR_14_DIM_2_SIZE                           0xE86D30
+
+#define mmTPC2_CFG_QM_TENSOR_14_DIM_2_STRIDE                         0xE86D34
+
+#define mmTPC2_CFG_QM_TENSOR_14_DIM_3_SIZE                           0xE86D38
+
+#define mmTPC2_CFG_QM_TENSOR_14_DIM_3_STRIDE                         0xE86D3C
+
+#define mmTPC2_CFG_QM_TENSOR_14_DIM_4_SIZE                           0xE86D40
+
+#define mmTPC2_CFG_QM_TENSOR_14_DIM_4_STRIDE                         0xE86D44
+
+#define mmTPC2_CFG_QM_TENSOR_15_BASE_ADDR_LOW                        0xE86D48
+
+#define mmTPC2_CFG_QM_TENSOR_15_BASE_ADDR_HIGH                       0xE86D4C
+
+#define mmTPC2_CFG_QM_TENSOR_15_PADDING_VALUE                        0xE86D50
+
+#define mmTPC2_CFG_QM_TENSOR_15_TENSOR_CONFIG                        0xE86D54
+
+#define mmTPC2_CFG_QM_TENSOR_15_DIM_0_SIZE                           0xE86D58
+
+#define mmTPC2_CFG_QM_TENSOR_15_DIM_0_STRIDE                         0xE86D5C
+
+#define mmTPC2_CFG_QM_TENSOR_15_DIM_1_SIZE                           0xE86D60
+
+#define mmTPC2_CFG_QM_TENSOR_15_DIM_1_STRIDE                         0xE86D64
+
+#define mmTPC2_CFG_QM_TENSOR_15_DIM_2_SIZE                           0xE86D68
+
+#define mmTPC2_CFG_QM_TENSOR_15_DIM_2_STRIDE                         0xE86D6C
+
+#define mmTPC2_CFG_QM_TENSOR_15_DIM_3_SIZE                           0xE86D70
+
+#define mmTPC2_CFG_QM_TENSOR_15_DIM_3_STRIDE                         0xE86D74
+
+#define mmTPC2_CFG_QM_TENSOR_15_DIM_4_SIZE                           0xE86D78
+
+#define mmTPC2_CFG_QM_TENSOR_15_DIM_4_STRIDE                         0xE86D7C
+
+#define mmTPC2_CFG_QM_SYNC_OBJECT_MESSAGE                            0xE86D80
+
+#define mmTPC2_CFG_QM_SYNC_OBJECT_ADDR                               0xE86D84
+
+#define mmTPC2_CFG_QM_KERNEL_BASE_ADDRESS_LOW                        0xE86D88
+
+#define mmTPC2_CFG_QM_KERNEL_BASE_ADDRESS_HIGH                       0xE86D8C
+
+#define mmTPC2_CFG_QM_TID_BASE_DIM_0                                 0xE86D90
+
+#define mmTPC2_CFG_QM_TID_SIZE_DIM_0                                 0xE86D94
+
+#define mmTPC2_CFG_QM_TID_BASE_DIM_1                                 0xE86D98
+
+#define mmTPC2_CFG_QM_TID_SIZE_DIM_1                                 0xE86D9C
+
+#define mmTPC2_CFG_QM_TID_BASE_DIM_2                                 0xE86DA0
+
+#define mmTPC2_CFG_QM_TID_SIZE_DIM_2                                 0xE86DA4
+
+#define mmTPC2_CFG_QM_TID_BASE_DIM_3                                 0xE86DA8
+
+#define mmTPC2_CFG_QM_TID_SIZE_DIM_3                                 0xE86DAC
+
+#define mmTPC2_CFG_QM_TID_BASE_DIM_4                                 0xE86DB0
+
+#define mmTPC2_CFG_QM_TID_SIZE_DIM_4                                 0xE86DB4
+
+#define mmTPC2_CFG_QM_KERNEL_CONFIG                                  0xE86DB8
+
+#define mmTPC2_CFG_QM_KERNEL_ID                                      0xE86DBC
+
+#define mmTPC2_CFG_QM_SRF_0                                          0xE86DC0
+
+#define mmTPC2_CFG_QM_SRF_1                                          0xE86DC4
+
+#define mmTPC2_CFG_QM_SRF_2                                          0xE86DC8
+
+#define mmTPC2_CFG_QM_SRF_3                                          0xE86DCC
+
+#define mmTPC2_CFG_QM_SRF_4                                          0xE86DD0
+
+#define mmTPC2_CFG_QM_SRF_5                                          0xE86DD4
+
+#define mmTPC2_CFG_QM_SRF_6                                          0xE86DD8
+
+#define mmTPC2_CFG_QM_SRF_7                                          0xE86DDC
+
+#define mmTPC2_CFG_QM_SRF_8                                          0xE86DE0
+
+#define mmTPC2_CFG_QM_SRF_9                                          0xE86DE4
+
+#define mmTPC2_CFG_QM_SRF_10                                         0xE86DE8
+
+#define mmTPC2_CFG_QM_SRF_11                                         0xE86DEC
+
+#define mmTPC2_CFG_QM_SRF_12                                         0xE86DF0
+
+#define mmTPC2_CFG_QM_SRF_13                                         0xE86DF4
+
+#define mmTPC2_CFG_QM_SRF_14                                         0xE86DF8
+
+#define mmTPC2_CFG_QM_SRF_15                                         0xE86DFC
+
+#define mmTPC2_CFG_QM_SRF_16                                         0xE86E00
+
+#define mmTPC2_CFG_QM_SRF_17                                         0xE86E04
+
+#define mmTPC2_CFG_QM_SRF_18                                         0xE86E08
+
+#define mmTPC2_CFG_QM_SRF_19                                         0xE86E0C
+
+#define mmTPC2_CFG_QM_SRF_20                                         0xE86E10
+
+#define mmTPC2_CFG_QM_SRF_21                                         0xE86E14
+
+#define mmTPC2_CFG_QM_SRF_22                                         0xE86E18
+
+#define mmTPC2_CFG_QM_SRF_23                                         0xE86E1C
+
+#define mmTPC2_CFG_QM_SRF_24                                         0xE86E20
+
+#define mmTPC2_CFG_QM_SRF_25                                         0xE86E24
+
+#define mmTPC2_CFG_QM_SRF_26                                         0xE86E28
+
+#define mmTPC2_CFG_QM_SRF_27                                         0xE86E2C
+
+#define mmTPC2_CFG_QM_SRF_28                                         0xE86E30
+
+#define mmTPC2_CFG_QM_SRF_29                                         0xE86E34
+
+#define mmTPC2_CFG_QM_SRF_30                                         0xE86E38
+
+#define mmTPC2_CFG_QM_SRF_31                                         0xE86E3C
+
+#endif /* ASIC_REG_TPC2_CFG_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc2_qm_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc2_qm_regs.h
new file mode 100644
index 000000000000..2919e2fa58f8
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc2_qm_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_TPC2_QM_REGS_H_
+#define ASIC_REG_TPC2_QM_REGS_H_
+
+/*
+ *****************************************
+ *   TPC2_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmTPC2_QM_GLBL_CFG0                                          0xE88000
+
+#define mmTPC2_QM_GLBL_CFG1                                          0xE88004
+
+#define mmTPC2_QM_GLBL_PROT                                          0xE88008
+
+#define mmTPC2_QM_GLBL_ERR_CFG                                       0xE8800C
+
+#define mmTPC2_QM_GLBL_SECURE_PROPS_0                                0xE88010
+
+#define mmTPC2_QM_GLBL_SECURE_PROPS_1                                0xE88014
+
+#define mmTPC2_QM_GLBL_SECURE_PROPS_2                                0xE88018
+
+#define mmTPC2_QM_GLBL_SECURE_PROPS_3                                0xE8801C
+
+#define mmTPC2_QM_GLBL_SECURE_PROPS_4                                0xE88020
+
+#define mmTPC2_QM_GLBL_NON_SECURE_PROPS_0                            0xE88024
+
+#define mmTPC2_QM_GLBL_NON_SECURE_PROPS_1                            0xE88028
+
+#define mmTPC2_QM_GLBL_NON_SECURE_PROPS_2                            0xE8802C
+
+#define mmTPC2_QM_GLBL_NON_SECURE_PROPS_3                            0xE88030
+
+#define mmTPC2_QM_GLBL_NON_SECURE_PROPS_4                            0xE88034
+
+#define mmTPC2_QM_GLBL_STS0                                          0xE88038
+
+#define mmTPC2_QM_GLBL_STS1_0                                        0xE88040
+
+#define mmTPC2_QM_GLBL_STS1_1                                        0xE88044
+
+#define mmTPC2_QM_GLBL_STS1_2                                        0xE88048
+
+#define mmTPC2_QM_GLBL_STS1_3                                        0xE8804C
+
+#define mmTPC2_QM_GLBL_STS1_4                                        0xE88050
+
+#define mmTPC2_QM_GLBL_MSG_EN_0                                      0xE88054
+
+#define mmTPC2_QM_GLBL_MSG_EN_1                                      0xE88058
+
+#define mmTPC2_QM_GLBL_MSG_EN_2                                      0xE8805C
+
+#define mmTPC2_QM_GLBL_MSG_EN_3                                      0xE88060
+
+#define mmTPC2_QM_GLBL_MSG_EN_4                                      0xE88068
+
+#define mmTPC2_QM_PQ_BASE_LO_0                                       0xE88070
+
+#define mmTPC2_QM_PQ_BASE_LO_1                                       0xE88074
+
+#define mmTPC2_QM_PQ_BASE_LO_2                                       0xE88078
+
+#define mmTPC2_QM_PQ_BASE_LO_3                                       0xE8807C
+
+#define mmTPC2_QM_PQ_BASE_HI_0                                       0xE88080
+
+#define mmTPC2_QM_PQ_BASE_HI_1                                       0xE88084
+
+#define mmTPC2_QM_PQ_BASE_HI_2                                       0xE88088
+
+#define mmTPC2_QM_PQ_BASE_HI_3                                       0xE8808C
+
+#define mmTPC2_QM_PQ_SIZE_0                                          0xE88090
+
+#define mmTPC2_QM_PQ_SIZE_1                                          0xE88094
+
+#define mmTPC2_QM_PQ_SIZE_2                                          0xE88098
+
+#define mmTPC2_QM_PQ_SIZE_3                                          0xE8809C
+
+#define mmTPC2_QM_PQ_PI_0                                            0xE880A0
+
+#define mmTPC2_QM_PQ_PI_1                                            0xE880A4
+
+#define mmTPC2_QM_PQ_PI_2                                            0xE880A8
+
+#define mmTPC2_QM_PQ_PI_3                                            0xE880AC
+
+#define mmTPC2_QM_PQ_CI_0                                            0xE880B0
+
+#define mmTPC2_QM_PQ_CI_1                                            0xE880B4
+
+#define mmTPC2_QM_PQ_CI_2                                            0xE880B8
+
+#define mmTPC2_QM_PQ_CI_3                                            0xE880BC
+
+#define mmTPC2_QM_PQ_CFG0_0                                          0xE880C0
+
+#define mmTPC2_QM_PQ_CFG0_1                                          0xE880C4
+
+#define mmTPC2_QM_PQ_CFG0_2                                          0xE880C8
+
+#define mmTPC2_QM_PQ_CFG0_3                                          0xE880CC
+
+#define mmTPC2_QM_PQ_CFG1_0                                          0xE880D0
+
+#define mmTPC2_QM_PQ_CFG1_1                                          0xE880D4
+
+#define mmTPC2_QM_PQ_CFG1_2                                          0xE880D8
+
+#define mmTPC2_QM_PQ_CFG1_3                                          0xE880DC
+
+#define mmTPC2_QM_PQ_ARUSER_31_11_0                                  0xE880E0
+
+#define mmTPC2_QM_PQ_ARUSER_31_11_1                                  0xE880E4
+
+#define mmTPC2_QM_PQ_ARUSER_31_11_2                                  0xE880E8
+
+#define mmTPC2_QM_PQ_ARUSER_31_11_3                                  0xE880EC
+
+#define mmTPC2_QM_PQ_STS0_0                                          0xE880F0
+
+#define mmTPC2_QM_PQ_STS0_1                                          0xE880F4
+
+#define mmTPC2_QM_PQ_STS0_2                                          0xE880F8
+
+#define mmTPC2_QM_PQ_STS0_3                                          0xE880FC
+
+#define mmTPC2_QM_PQ_STS1_0                                          0xE88100
+
+#define mmTPC2_QM_PQ_STS1_1                                          0xE88104
+
+#define mmTPC2_QM_PQ_STS1_2                                          0xE88108
+
+#define mmTPC2_QM_PQ_STS1_3                                          0xE8810C
+
+#define mmTPC2_QM_CQ_CFG0_0                                          0xE88110
+
+#define mmTPC2_QM_CQ_CFG0_1                                          0xE88114
+
+#define mmTPC2_QM_CQ_CFG0_2                                          0xE88118
+
+#define mmTPC2_QM_CQ_CFG0_3                                          0xE8811C
+
+#define mmTPC2_QM_CQ_CFG0_4                                          0xE88120
+
+#define mmTPC2_QM_CQ_CFG1_0                                          0xE88124
+
+#define mmTPC2_QM_CQ_CFG1_1                                          0xE88128
+
+#define mmTPC2_QM_CQ_CFG1_2                                          0xE8812C
+
+#define mmTPC2_QM_CQ_CFG1_3                                          0xE88130
+
+#define mmTPC2_QM_CQ_CFG1_4                                          0xE88134
+
+#define mmTPC2_QM_CQ_ARUSER_31_11_0                                  0xE88138
+
+#define mmTPC2_QM_CQ_ARUSER_31_11_1                                  0xE8813C
+
+#define mmTPC2_QM_CQ_ARUSER_31_11_2                                  0xE88140
+
+#define mmTPC2_QM_CQ_ARUSER_31_11_3                                  0xE88144
+
+#define mmTPC2_QM_CQ_ARUSER_31_11_4                                  0xE88148
+
+#define mmTPC2_QM_CQ_STS0_0                                          0xE8814C
+
+#define mmTPC2_QM_CQ_STS0_1                                          0xE88150
+
+#define mmTPC2_QM_CQ_STS0_2                                          0xE88154
+
+#define mmTPC2_QM_CQ_STS0_3                                          0xE88158
+
+#define mmTPC2_QM_CQ_STS0_4                                          0xE8815C
+
+#define mmTPC2_QM_CQ_STS1_0                                          0xE88160
+
+#define mmTPC2_QM_CQ_STS1_1                                          0xE88164
+
+#define mmTPC2_QM_CQ_STS1_2                                          0xE88168
+
+#define mmTPC2_QM_CQ_STS1_3                                          0xE8816C
+
+#define mmTPC2_QM_CQ_STS1_4                                          0xE88170
+
+#define mmTPC2_QM_CQ_PTR_LO_0                                        0xE88174
+
+#define mmTPC2_QM_CQ_PTR_HI_0                                        0xE88178
+
+#define mmTPC2_QM_CQ_TSIZE_0                                         0xE8817C
+
+#define mmTPC2_QM_CQ_CTL_0                                           0xE88180
+
+#define mmTPC2_QM_CQ_PTR_LO_1                                        0xE88184
+
+#define mmTPC2_QM_CQ_PTR_HI_1                                        0xE88188
+
+#define mmTPC2_QM_CQ_TSIZE_1                                         0xE8818C
+
+#define mmTPC2_QM_CQ_CTL_1                                           0xE88190
+
+#define mmTPC2_QM_CQ_PTR_LO_2                                        0xE88194
+
+#define mmTPC2_QM_CQ_PTR_HI_2                                        0xE88198
+
+#define mmTPC2_QM_CQ_TSIZE_2                                         0xE8819C
+
+#define mmTPC2_QM_CQ_CTL_2                                           0xE881A0
+
+#define mmTPC2_QM_CQ_PTR_LO_3                                        0xE881A4
+
+#define mmTPC2_QM_CQ_PTR_HI_3                                        0xE881A8
+
+#define mmTPC2_QM_CQ_TSIZE_3                                         0xE881AC
+
+#define mmTPC2_QM_CQ_CTL_3                                           0xE881B0
+
+#define mmTPC2_QM_CQ_PTR_LO_4                                        0xE881B4
+
+#define mmTPC2_QM_CQ_PTR_HI_4                                        0xE881B8
+
+#define mmTPC2_QM_CQ_TSIZE_4                                         0xE881BC
+
+#define mmTPC2_QM_CQ_CTL_4                                           0xE881C0
+
+#define mmTPC2_QM_CQ_PTR_LO_STS_0                                    0xE881C4
+
+#define mmTPC2_QM_CQ_PTR_LO_STS_1                                    0xE881C8
+
+#define mmTPC2_QM_CQ_PTR_LO_STS_2                                    0xE881CC
+
+#define mmTPC2_QM_CQ_PTR_LO_STS_3                                    0xE881D0
+
+#define mmTPC2_QM_CQ_PTR_LO_STS_4                                    0xE881D4
+
+#define mmTPC2_QM_CQ_PTR_HI_STS_0                                    0xE881D8
+
+#define mmTPC2_QM_CQ_PTR_HI_STS_1                                    0xE881DC
+
+#define mmTPC2_QM_CQ_PTR_HI_STS_2                                    0xE881E0
+
+#define mmTPC2_QM_CQ_PTR_HI_STS_3                                    0xE881E4
+
+#define mmTPC2_QM_CQ_PTR_HI_STS_4                                    0xE881E8
+
+#define mmTPC2_QM_CQ_TSIZE_STS_0                                     0xE881EC
+
+#define mmTPC2_QM_CQ_TSIZE_STS_1                                     0xE881F0
+
+#define mmTPC2_QM_CQ_TSIZE_STS_2                                     0xE881F4
+
+#define mmTPC2_QM_CQ_TSIZE_STS_3                                     0xE881F8
+
+#define mmTPC2_QM_CQ_TSIZE_STS_4                                     0xE881FC
+
+#define mmTPC2_QM_CQ_CTL_STS_0                                       0xE88200
+
+#define mmTPC2_QM_CQ_CTL_STS_1                                       0xE88204
+
+#define mmTPC2_QM_CQ_CTL_STS_2                                       0xE88208
+
+#define mmTPC2_QM_CQ_CTL_STS_3                                       0xE8820C
+
+#define mmTPC2_QM_CQ_CTL_STS_4                                       0xE88210
+
+#define mmTPC2_QM_CQ_IFIFO_CNT_0                                     0xE88214
+
+#define mmTPC2_QM_CQ_IFIFO_CNT_1                                     0xE88218
+
+#define mmTPC2_QM_CQ_IFIFO_CNT_2                                     0xE8821C
+
+#define mmTPC2_QM_CQ_IFIFO_CNT_3                                     0xE88220
+
+#define mmTPC2_QM_CQ_IFIFO_CNT_4                                     0xE88224
+
+#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_0                             0xE88228
+
+#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_1                             0xE8822C
+
+#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_2                             0xE88230
+
+#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_3                             0xE88234
+
+#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_4                             0xE88238
+
+#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_0                             0xE8823C
+
+#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_1                             0xE88240
+
+#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_2                             0xE88244
+
+#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_3                             0xE88248
+
+#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_4                             0xE8824C
+
+#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_0                             0xE88250
+
+#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_1                             0xE88254
+
+#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_2                             0xE88258
+
+#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_3                             0xE8825C
+
+#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_4                             0xE88260
+
+#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_0                             0xE88264
+
+#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_1                             0xE88268
+
+#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_2                             0xE8826C
+
+#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_3                             0xE88270
+
+#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_4                             0xE88274
+
+#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_0                             0xE88278
+
+#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_1                             0xE8827C
+
+#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_2                             0xE88280
+
+#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_3                             0xE88284
+
+#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_4                             0xE88288
+
+#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_0                             0xE8828C
+
+#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_1                             0xE88290
+
+#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_2                             0xE88294
+
+#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_3                             0xE88298
+
+#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_4                             0xE8829C
+
+#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_0                             0xE882A0
+
+#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_1                             0xE882A4
+
+#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_2                             0xE882A8
+
+#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_3                             0xE882AC
+
+#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_4                             0xE882B0
+
+#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_0                             0xE882B4
+
+#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_1                             0xE882B8
+
+#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_2                             0xE882BC
+
+#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_3                             0xE882C0
+
+#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_4                             0xE882C4
+
+#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_0                             0xE882C8
+
+#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_1                             0xE882CC
+
+#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_2                             0xE882D0
+
+#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_3                             0xE882D4
+
+#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_4                             0xE882D8
+
+#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0                       0xE882E0
+
+#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1                       0xE882E4
+
+#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2                       0xE882E8
+
+#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3                       0xE882EC
+
+#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4                       0xE882F0
+
+#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_0                       0xE882F4
+
+#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_1                       0xE882F8
+
+#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_2                       0xE882FC
+
+#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3                       0xE88300
+
+#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_4                       0xE88304
+
+#define mmTPC2_QM_CP_FENCE0_RDATA_0                                  0xE88308
+
+#define mmTPC2_QM_CP_FENCE0_RDATA_1                                  0xE8830C
+
+#define mmTPC2_QM_CP_FENCE0_RDATA_2                                  0xE88310
+
+#define mmTPC2_QM_CP_FENCE0_RDATA_3                                  0xE88314
+
+#define mmTPC2_QM_CP_FENCE0_RDATA_4                                  0xE88318
+
+#define mmTPC2_QM_CP_FENCE1_RDATA_0                                  0xE8831C
+
+#define mmTPC2_QM_CP_FENCE1_RDATA_1                                  0xE88320
+
+#define mmTPC2_QM_CP_FENCE1_RDATA_2                                  0xE88324
+
+#define mmTPC2_QM_CP_FENCE1_RDATA_3                                  0xE88328
+
+#define mmTPC2_QM_CP_FENCE1_RDATA_4                                  0xE8832C
+
+#define mmTPC2_QM_CP_FENCE2_RDATA_0                                  0xE88330
+
+#define mmTPC2_QM_CP_FENCE2_RDATA_1                                  0xE88334
+
+#define mmTPC2_QM_CP_FENCE2_RDATA_2                                  0xE88338
+
+#define mmTPC2_QM_CP_FENCE2_RDATA_3                                  0xE8833C
+
+#define mmTPC2_QM_CP_FENCE2_RDATA_4                                  0xE88340
+
+#define mmTPC2_QM_CP_FENCE3_RDATA_0                                  0xE88344
+
+#define mmTPC2_QM_CP_FENCE3_RDATA_1                                  0xE88348
+
+#define mmTPC2_QM_CP_FENCE3_RDATA_2                                  0xE8834C
+
+#define mmTPC2_QM_CP_FENCE3_RDATA_3                                  0xE88350
+
+#define mmTPC2_QM_CP_FENCE3_RDATA_4                                  0xE88354
+
+#define mmTPC2_QM_CP_FENCE0_CNT_0                                    0xE88358
+
+#define mmTPC2_QM_CP_FENCE0_CNT_1                                    0xE8835C
+
+#define mmTPC2_QM_CP_FENCE0_CNT_2                                    0xE88360
+
+#define mmTPC2_QM_CP_FENCE0_CNT_3                                    0xE88364
+
+#define mmTPC2_QM_CP_FENCE0_CNT_4                                    0xE88368
+
+#define mmTPC2_QM_CP_FENCE1_CNT_0                                    0xE8836C
+
+#define mmTPC2_QM_CP_FENCE1_CNT_1                                    0xE88370
+
+#define mmTPC2_QM_CP_FENCE1_CNT_2                                    0xE88374
+
+#define mmTPC2_QM_CP_FENCE1_CNT_3                                    0xE88378
+
+#define mmTPC2_QM_CP_FENCE1_CNT_4                                    0xE8837C
+
+#define mmTPC2_QM_CP_FENCE2_CNT_0                                    0xE88380
+
+#define mmTPC2_QM_CP_FENCE2_CNT_1                                    0xE88384
+
+#define mmTPC2_QM_CP_FENCE2_CNT_2                                    0xE88388
+
+#define mmTPC2_QM_CP_FENCE2_CNT_3                                    0xE8838C
+
+#define mmTPC2_QM_CP_FENCE2_CNT_4                                    0xE88390
+
+#define mmTPC2_QM_CP_FENCE3_CNT_0                                    0xE88394
+
+#define mmTPC2_QM_CP_FENCE3_CNT_1                                    0xE88398
+
+#define mmTPC2_QM_CP_FENCE3_CNT_2                                    0xE8839C
+
+#define mmTPC2_QM_CP_FENCE3_CNT_3                                    0xE883A0
+
+#define mmTPC2_QM_CP_FENCE3_CNT_4                                    0xE883A4
+
+#define mmTPC2_QM_CP_STS_0                                           0xE883A8
+
+#define mmTPC2_QM_CP_STS_1                                           0xE883AC
+
+#define mmTPC2_QM_CP_STS_2                                           0xE883B0
+
+#define mmTPC2_QM_CP_STS_3                                           0xE883B4
+
+#define mmTPC2_QM_CP_STS_4                                           0xE883B8
+
+#define mmTPC2_QM_CP_CURRENT_INST_LO_0                               0xE883BC
+
+#define mmTPC2_QM_CP_CURRENT_INST_LO_1                               0xE883C0
+
+#define mmTPC2_QM_CP_CURRENT_INST_LO_2                               0xE883C4
+
+#define mmTPC2_QM_CP_CURRENT_INST_LO_3                               0xE883C8
+
+#define mmTPC2_QM_CP_CURRENT_INST_LO_4                               0xE883CC
+
+#define mmTPC2_QM_CP_CURRENT_INST_HI_0                               0xE883D0
+
+#define mmTPC2_QM_CP_CURRENT_INST_HI_1                               0xE883D4
+
+#define mmTPC2_QM_CP_CURRENT_INST_HI_2                               0xE883D8
+
+#define mmTPC2_QM_CP_CURRENT_INST_HI_3                               0xE883DC
+
+#define mmTPC2_QM_CP_CURRENT_INST_HI_4                               0xE883E0
+
+#define mmTPC2_QM_CP_BARRIER_CFG_0                                   0xE883F4
+
+#define mmTPC2_QM_CP_BARRIER_CFG_1                                   0xE883F8
+
+#define mmTPC2_QM_CP_BARRIER_CFG_2                                   0xE883FC
+
+#define mmTPC2_QM_CP_BARRIER_CFG_3                                   0xE88400
+
+#define mmTPC2_QM_CP_BARRIER_CFG_4                                   0xE88404
+
+#define mmTPC2_QM_CP_DBG_0_0                                         0xE88408
+
+#define mmTPC2_QM_CP_DBG_0_1                                         0xE8840C
+
+#define mmTPC2_QM_CP_DBG_0_2                                         0xE88410
+
+#define mmTPC2_QM_CP_DBG_0_3                                         0xE88414
+
+#define mmTPC2_QM_CP_DBG_0_4                                         0xE88418
+
+#define mmTPC2_QM_CP_ARUSER_31_11_0                                  0xE8841C
+
+#define mmTPC2_QM_CP_ARUSER_31_11_1                                  0xE88420
+
+#define mmTPC2_QM_CP_ARUSER_31_11_2                                  0xE88424
+
+#define mmTPC2_QM_CP_ARUSER_31_11_3                                  0xE88428
+
+#define mmTPC2_QM_CP_ARUSER_31_11_4                                  0xE8842C
+
+#define mmTPC2_QM_CP_AWUSER_31_11_0                                  0xE88430
+
+#define mmTPC2_QM_CP_AWUSER_31_11_1                                  0xE88434
+
+#define mmTPC2_QM_CP_AWUSER_31_11_2                                  0xE88438
+
+#define mmTPC2_QM_CP_AWUSER_31_11_3                                  0xE8843C
+
+#define mmTPC2_QM_CP_AWUSER_31_11_4                                  0xE88440
+
+#define mmTPC2_QM_ARB_CFG_0                                          0xE88A00
+
+#define mmTPC2_QM_ARB_CHOISE_Q_PUSH                                  0xE88A04
+
+#define mmTPC2_QM_ARB_WRR_WEIGHT_0                                   0xE88A08
+
+#define mmTPC2_QM_ARB_WRR_WEIGHT_1                                   0xE88A0C
+
+#define mmTPC2_QM_ARB_WRR_WEIGHT_2                                   0xE88A10
+
+#define mmTPC2_QM_ARB_WRR_WEIGHT_3                                   0xE88A14
+
+#define mmTPC2_QM_ARB_CFG_1                                          0xE88A18
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_0                               0xE88A20
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_1                               0xE88A24
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_2                               0xE88A28
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_3                               0xE88A2C
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_4                               0xE88A30
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_5                               0xE88A34
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_6                               0xE88A38
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_7                               0xE88A3C
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_8                               0xE88A40
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_9                               0xE88A44
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_10                              0xE88A48
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_11                              0xE88A4C
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_12                              0xE88A50
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_13                              0xE88A54
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_14                              0xE88A58
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_15                              0xE88A5C
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_16                              0xE88A60
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_17                              0xE88A64
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_18                              0xE88A68
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_19                              0xE88A6C
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_20                              0xE88A70
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_21                              0xE88A74
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_22                              0xE88A78
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_23                              0xE88A7C
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_24                              0xE88A80
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_25                              0xE88A84
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_26                              0xE88A88
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_27                              0xE88A8C
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_28                              0xE88A90
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_29                              0xE88A94
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_30                              0xE88A98
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_31                              0xE88A9C
+
+#define mmTPC2_QM_ARB_MST_CRED_INC                                   0xE88AA0
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_0                         0xE88AA4
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_1                         0xE88AA8
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_2                         0xE88AAC
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_3                         0xE88AB0
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_4                         0xE88AB4
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_5                         0xE88AB8
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_6                         0xE88ABC
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_7                         0xE88AC0
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_8                         0xE88AC4
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_9                         0xE88AC8
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_10                        0xE88ACC
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_11                        0xE88AD0
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_12                        0xE88AD4
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_13                        0xE88AD8
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_14                        0xE88ADC
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_15                        0xE88AE0
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_16                        0xE88AE4
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_17                        0xE88AE8
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_18                        0xE88AEC
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_19                        0xE88AF0
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_20                        0xE88AF4
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_21                        0xE88AF8
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_22                        0xE88AFC
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_23                        0xE88B00
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_24                        0xE88B04
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_25                        0xE88B08
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_26                        0xE88B0C
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_27                        0xE88B10
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_28                        0xE88B14
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_29                        0xE88B18
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_30                        0xE88B1C
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_31                        0xE88B20
+
+#define mmTPC2_QM_ARB_SLV_MASTER_INC_CRED_OFST                       0xE88B28
+
+#define mmTPC2_QM_ARB_MST_SLAVE_EN                                   0xE88B2C
+
+#define mmTPC2_QM_ARB_MST_QUIET_PER                                  0xE88B34
+
+#define mmTPC2_QM_ARB_SLV_CHOISE_WDT                                 0xE88B38
+
+#define mmTPC2_QM_ARB_SLV_ID                                         0xE88B3C
+
+#define mmTPC2_QM_ARB_MSG_MAX_INFLIGHT                               0xE88B44
+
+#define mmTPC2_QM_ARB_MSG_AWUSER_31_11                               0xE88B48
+
+#define mmTPC2_QM_ARB_MSG_AWUSER_SEC_PROP                            0xE88B4C
+
+#define mmTPC2_QM_ARB_MSG_AWUSER_NON_SEC_PROP                        0xE88B50
+
+#define mmTPC2_QM_ARB_BASE_LO                                        0xE88B54
+
+#define mmTPC2_QM_ARB_BASE_HI                                        0xE88B58
+
+#define mmTPC2_QM_ARB_STATE_STS                                      0xE88B80
+
+#define mmTPC2_QM_ARB_CHOISE_FULLNESS_STS                            0xE88B84
+
+#define mmTPC2_QM_ARB_MSG_STS                                        0xE88B88
+
+#define mmTPC2_QM_ARB_SLV_CHOISE_Q_HEAD                              0xE88B8C
+
+#define mmTPC2_QM_ARB_ERR_CAUSE                                      0xE88B9C
+
+#define mmTPC2_QM_ARB_ERR_MSG_EN                                     0xE88BA0
+
+#define mmTPC2_QM_ARB_ERR_STS_DRP                                    0xE88BA8
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_0                                 0xE88BB0
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_1                                 0xE88BB4
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_2                                 0xE88BB8
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_3                                 0xE88BBC
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_4                                 0xE88BC0
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_5                                 0xE88BC4
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_6                                 0xE88BC8
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_7                                 0xE88BCC
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_8                                 0xE88BD0
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_9                                 0xE88BD4
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_10                                0xE88BD8
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_11                                0xE88BDC
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_12                                0xE88BE0
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_13                                0xE88BE4
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_14                                0xE88BE8
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_15                                0xE88BEC
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_16                                0xE88BF0
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_17                                0xE88BF4
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_18                                0xE88BF8
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_19                                0xE88BFC
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_20                                0xE88C00
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_21                                0xE88C04
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_22                                0xE88C08
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_23                                0xE88C0C
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_24                                0xE88C10
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_25                                0xE88C14
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_26                                0xE88C18
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_27                                0xE88C1C
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_28                                0xE88C20
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_29                                0xE88C24
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_30                                0xE88C28
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_31                                0xE88C2C
+
+#define mmTPC2_QM_CGM_CFG                                            0xE88C70
+
+#define mmTPC2_QM_CGM_STS                                            0xE88C74
+
+#define mmTPC2_QM_CGM_CFG1                                           0xE88C78
+
+#define mmTPC2_QM_LOCAL_RANGE_BASE                                   0xE88C80
+
+#define mmTPC2_QM_LOCAL_RANGE_SIZE                                   0xE88C84
+
+#define mmTPC2_QM_CSMR_STRICT_PRIO_CFG                               0xE88C90
+
+#define mmTPC2_QM_HBW_RD_RATE_LIM_CFG_1                              0xE88C94
+
+#define mmTPC2_QM_LBW_WR_RATE_LIM_CFG_0                              0xE88C98
+
+#define mmTPC2_QM_LBW_WR_RATE_LIM_CFG_1                              0xE88C9C
+
+#define mmTPC2_QM_HBW_RD_RATE_LIM_CFG_0                              0xE88CA0
+
+#define mmTPC2_QM_GLBL_AXCACHE                                       0xE88CA4
+
+#define mmTPC2_QM_IND_GW_APB_CFG                                     0xE88CB0
+
+#define mmTPC2_QM_IND_GW_APB_WDATA                                   0xE88CB4
+
+#define mmTPC2_QM_IND_GW_APB_RDATA                                   0xE88CB8
+
+#define mmTPC2_QM_IND_GW_APB_STATUS                                  0xE88CBC
+
+#define mmTPC2_QM_GLBL_ERR_ADDR_LO                                   0xE88CD0
+
+#define mmTPC2_QM_GLBL_ERR_ADDR_HI                                   0xE88CD4
+
+#define mmTPC2_QM_GLBL_ERR_WDATA                                     0xE88CD8
+
+#define mmTPC2_QM_GLBL_MEM_INIT_BUSY                                 0xE88D00
+
+#endif /* ASIC_REG_TPC2_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc3_cfg_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc3_cfg_regs.h
new file mode 100644
index 000000000000..6d42469659f1
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc3_cfg_regs.h
@@ -0,0 +1,1226 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_TPC3_CFG_REGS_H_
+#define ASIC_REG_TPC3_CFG_REGS_H_
+
+/*
+ *****************************************
+ *   TPC3_CFG (Prototype: TPC)
+ *****************************************
+ */
+
+#define mmTPC3_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW                     0xEC6400
+
+#define mmTPC3_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH                    0xEC6404
+
+#define mmTPC3_CFG_KERNEL_TENSOR_0_PADDING_VALUE                     0xEC6408
+
+#define mmTPC3_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG                     0xEC640C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_0_SIZE                        0xEC6410
+
+#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE                      0xEC6414
+
+#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_1_SIZE                        0xEC6418
+
+#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE                      0xEC641C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_2_SIZE                        0xEC6420
+
+#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE                      0xEC6424
+
+#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_3_SIZE                        0xEC6428
+
+#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE                      0xEC642C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_4_SIZE                        0xEC6430
+
+#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE                      0xEC6434
+
+#define mmTPC3_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW                     0xEC6438
+
+#define mmTPC3_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH                    0xEC643C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_1_PADDING_VALUE                     0xEC6440
+
+#define mmTPC3_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG                     0xEC6444
+
+#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_0_SIZE                        0xEC6448
+
+#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE                      0xEC644C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_1_SIZE                        0xEC6450
+
+#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE                      0xEC6454
+
+#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_2_SIZE                        0xEC6458
+
+#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE                      0xEC645C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_3_SIZE                        0xEC6460
+
+#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE                      0xEC6464
+
+#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_4_SIZE                        0xEC6468
+
+#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE                      0xEC646C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW                     0xEC6470
+
+#define mmTPC3_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH                    0xEC6474
+
+#define mmTPC3_CFG_KERNEL_TENSOR_2_PADDING_VALUE                     0xEC6478
+
+#define mmTPC3_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG                     0xEC647C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_0_SIZE                        0xEC6480
+
+#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE                      0xEC6484
+
+#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_1_SIZE                        0xEC6488
+
+#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE                      0xEC648C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_2_SIZE                        0xEC6490
+
+#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE                      0xEC6494
+
+#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_3_SIZE                        0xEC6498
+
+#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE                      0xEC649C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_4_SIZE                        0xEC64A0
+
+#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE                      0xEC64A4
+
+#define mmTPC3_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW                     0xEC64A8
+
+#define mmTPC3_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH                    0xEC64AC
+
+#define mmTPC3_CFG_KERNEL_TENSOR_3_PADDING_VALUE                     0xEC64B0
+
+#define mmTPC3_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG                     0xEC64B4
+
+#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_0_SIZE                        0xEC64B8
+
+#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE                      0xEC64BC
+
+#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_1_SIZE                        0xEC64C0
+
+#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE                      0xEC64C4
+
+#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_2_SIZE                        0xEC64C8
+
+#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE                      0xEC64CC
+
+#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_3_SIZE                        0xEC64D0
+
+#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE                      0xEC64D4
+
+#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_4_SIZE                        0xEC64D8
+
+#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE                      0xEC64DC
+
+#define mmTPC3_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW                     0xEC64E0
+
+#define mmTPC3_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH                    0xEC64E4
+
+#define mmTPC3_CFG_KERNEL_TENSOR_4_PADDING_VALUE                     0xEC64E8
+
+#define mmTPC3_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG                     0xEC64EC
+
+#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_0_SIZE                        0xEC64F0
+
+#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE                      0xEC64F4
+
+#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_1_SIZE                        0xEC64F8
+
+#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE                      0xEC64FC
+
+#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_2_SIZE                        0xEC6500
+
+#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE                      0xEC6504
+
+#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_3_SIZE                        0xEC6508
+
+#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE                      0xEC650C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_4_SIZE                        0xEC6510
+
+#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE                      0xEC6514
+
+#define mmTPC3_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW                     0xEC6518
+
+#define mmTPC3_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH                    0xEC651C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_5_PADDING_VALUE                     0xEC6520
+
+#define mmTPC3_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG                     0xEC6524
+
+#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_0_SIZE                        0xEC6528
+
+#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE                      0xEC652C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_1_SIZE                        0xEC6530
+
+#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE                      0xEC6534
+
+#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_2_SIZE                        0xEC6538
+
+#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE                      0xEC653C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_3_SIZE                        0xEC6540
+
+#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE                      0xEC6544
+
+#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_4_SIZE                        0xEC6548
+
+#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE                      0xEC654C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW                     0xEC6550
+
+#define mmTPC3_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH                    0xEC6554
+
+#define mmTPC3_CFG_KERNEL_TENSOR_6_PADDING_VALUE                     0xEC6558
+
+#define mmTPC3_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG                     0xEC655C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_0_SIZE                        0xEC6560
+
+#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE                      0xEC6564
+
+#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_1_SIZE                        0xEC6568
+
+#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE                      0xEC656C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_2_SIZE                        0xEC6570
+
+#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE                      0xEC6574
+
+#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_3_SIZE                        0xEC6578
+
+#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE                      0xEC657C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_4_SIZE                        0xEC6580
+
+#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE                      0xEC6584
+
+#define mmTPC3_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW                     0xEC6588
+
+#define mmTPC3_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH                    0xEC658C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_7_PADDING_VALUE                     0xEC6590
+
+#define mmTPC3_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG                     0xEC6594
+
+#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_0_SIZE                        0xEC6598
+
+#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE                      0xEC659C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_1_SIZE                        0xEC65A0
+
+#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE                      0xEC65A4
+
+#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_2_SIZE                        0xEC65A8
+
+#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE                      0xEC65AC
+
+#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_3_SIZE                        0xEC65B0
+
+#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE                      0xEC65B4
+
+#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_4_SIZE                        0xEC65B8
+
+#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE                      0xEC65BC
+
+#define mmTPC3_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW                     0xEC65C0
+
+#define mmTPC3_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH                    0xEC65C4
+
+#define mmTPC3_CFG_KERNEL_TENSOR_8_PADDING_VALUE                     0xEC65C8
+
+#define mmTPC3_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG                     0xEC65CC
+
+#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_0_SIZE                        0xEC65D0
+
+#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE                      0xEC65D4
+
+#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_1_SIZE                        0xEC65D8
+
+#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE                      0xEC65DC
+
+#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_2_SIZE                        0xEC65E0
+
+#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE                      0xEC65E4
+
+#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_3_SIZE                        0xEC65E8
+
+#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE                      0xEC65EC
+
+#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_4_SIZE                        0xEC65F0
+
+#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE                      0xEC65F4
+
+#define mmTPC3_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW                     0xEC65F8
+
+#define mmTPC3_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH                    0xEC65FC
+
+#define mmTPC3_CFG_KERNEL_TENSOR_9_PADDING_VALUE                     0xEC6600
+
+#define mmTPC3_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG                     0xEC6604
+
+#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_0_SIZE                        0xEC6608
+
+#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE                      0xEC660C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_1_SIZE                        0xEC6610
+
+#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE                      0xEC6614
+
+#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_2_SIZE                        0xEC6618
+
+#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE                      0xEC661C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_3_SIZE                        0xEC6620
+
+#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE                      0xEC6624
+
+#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_4_SIZE                        0xEC6628
+
+#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE                      0xEC662C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW                    0xEC6630
+
+#define mmTPC3_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH                   0xEC6634
+
+#define mmTPC3_CFG_KERNEL_TENSOR_10_PADDING_VALUE                    0xEC6638
+
+#define mmTPC3_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG                    0xEC663C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_0_SIZE                       0xEC6640
+
+#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE                     0xEC6644
+
+#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_1_SIZE                       0xEC6648
+
+#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE                     0xEC664C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_2_SIZE                       0xEC6650
+
+#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE                     0xEC6654
+
+#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_3_SIZE                       0xEC6658
+
+#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE                     0xEC665C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_4_SIZE                       0xEC6660
+
+#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE                     0xEC6664
+
+#define mmTPC3_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW                    0xEC6668
+
+#define mmTPC3_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH                   0xEC666C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_11_PADDING_VALUE                    0xEC6670
+
+#define mmTPC3_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG                    0xEC6674
+
+#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_0_SIZE                       0xEC6678
+
+#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE                     0xEC667C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_1_SIZE                       0xEC6680
+
+#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE                     0xEC6684
+
+#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_2_SIZE                       0xEC6688
+
+#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE                     0xEC668C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_3_SIZE                       0xEC6690
+
+#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE                     0xEC6694
+
+#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_4_SIZE                       0xEC6698
+
+#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE                     0xEC669C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW                    0xEC66A0
+
+#define mmTPC3_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH                   0xEC66A4
+
+#define mmTPC3_CFG_KERNEL_TENSOR_12_PADDING_VALUE                    0xEC66A8
+
+#define mmTPC3_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG                    0xEC66AC
+
+#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_0_SIZE                       0xEC66B0
+
+#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE                     0xEC66B4
+
+#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_1_SIZE                       0xEC66B8
+
+#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE                     0xEC66BC
+
+#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_2_SIZE                       0xEC66C0
+
+#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE                     0xEC66C4
+
+#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_3_SIZE                       0xEC66C8
+
+#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE                     0xEC66CC
+
+#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_4_SIZE                       0xEC66D0
+
+#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE                     0xEC66D4
+
+#define mmTPC3_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW                    0xEC66D8
+
+#define mmTPC3_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH                   0xEC66DC
+
+#define mmTPC3_CFG_KERNEL_TENSOR_13_PADDING_VALUE                    0xEC66E0
+
+#define mmTPC3_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG                    0xEC66E4
+
+#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_0_SIZE                       0xEC66E8
+
+#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE                     0xEC66EC
+
+#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_1_SIZE                       0xEC66F0
+
+#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE                     0xEC66F4
+
+#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_2_SIZE                       0xEC66F8
+
+#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE                     0xEC66FC
+
+#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_3_SIZE                       0xEC6700
+
+#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE                     0xEC6704
+
+#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_4_SIZE                       0xEC6708
+
+#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE                     0xEC670C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW                    0xEC6710
+
+#define mmTPC3_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH                   0xEC6714
+
+#define mmTPC3_CFG_KERNEL_TENSOR_14_PADDING_VALUE                    0xEC6718
+
+#define mmTPC3_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG                    0xEC671C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_0_SIZE                       0xEC6720
+
+#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE                     0xEC6724
+
+#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_1_SIZE                       0xEC6728
+
+#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE                     0xEC672C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_2_SIZE                       0xEC6730
+
+#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE                     0xEC6734
+
+#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_3_SIZE                       0xEC6738
+
+#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE                     0xEC673C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_4_SIZE                       0xEC6740
+
+#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE                     0xEC6744
+
+#define mmTPC3_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW                    0xEC6748
+
+#define mmTPC3_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH                   0xEC674C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_15_PADDING_VALUE                    0xEC6750
+
+#define mmTPC3_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG                    0xEC6754
+
+#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_0_SIZE                       0xEC6758
+
+#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE                     0xEC675C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_1_SIZE                       0xEC6760
+
+#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE                     0xEC6764
+
+#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_2_SIZE                       0xEC6768
+
+#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE                     0xEC676C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_3_SIZE                       0xEC6770
+
+#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE                     0xEC6774
+
+#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_4_SIZE                       0xEC6778
+
+#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE                     0xEC677C
+
+#define mmTPC3_CFG_KERNEL_SYNC_OBJECT_MESSAGE                        0xEC6780
+
+#define mmTPC3_CFG_KERNEL_SYNC_OBJECT_ADDR                           0xEC6784
+
+#define mmTPC3_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW                    0xEC6788
+
+#define mmTPC3_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH                   0xEC678C
+
+#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_0                             0xEC6790
+
+#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_0                             0xEC6794
+
+#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_1                             0xEC6798
+
+#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_1                             0xEC679C
+
+#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_2                             0xEC67A0
+
+#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_2                             0xEC67A4
+
+#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_3                             0xEC67A8
+
+#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_3                             0xEC67AC
+
+#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_4                             0xEC67B0
+
+#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_4                             0xEC67B4
+
+#define mmTPC3_CFG_KERNEL_KERNEL_CONFIG                              0xEC67B8
+
+#define mmTPC3_CFG_KERNEL_KERNEL_ID                                  0xEC67BC
+
+#define mmTPC3_CFG_KERNEL_SRF_0                                      0xEC67C0
+
+#define mmTPC3_CFG_KERNEL_SRF_1                                      0xEC67C4
+
+#define mmTPC3_CFG_KERNEL_SRF_2                                      0xEC67C8
+
+#define mmTPC3_CFG_KERNEL_SRF_3                                      0xEC67CC
+
+#define mmTPC3_CFG_KERNEL_SRF_4                                      0xEC67D0
+
+#define mmTPC3_CFG_KERNEL_SRF_5                                      0xEC67D4
+
+#define mmTPC3_CFG_KERNEL_SRF_6                                      0xEC67D8
+
+#define mmTPC3_CFG_KERNEL_SRF_7                                      0xEC67DC
+
+#define mmTPC3_CFG_KERNEL_SRF_8                                      0xEC67E0
+
+#define mmTPC3_CFG_KERNEL_SRF_9                                      0xEC67E4
+
+#define mmTPC3_CFG_KERNEL_SRF_10                                     0xEC67E8
+
+#define mmTPC3_CFG_KERNEL_SRF_11                                     0xEC67EC
+
+#define mmTPC3_CFG_KERNEL_SRF_12                                     0xEC67F0
+
+#define mmTPC3_CFG_KERNEL_SRF_13                                     0xEC67F4
+
+#define mmTPC3_CFG_KERNEL_SRF_14                                     0xEC67F8
+
+#define mmTPC3_CFG_KERNEL_SRF_15                                     0xEC67FC
+
+#define mmTPC3_CFG_KERNEL_SRF_16                                     0xEC6800
+
+#define mmTPC3_CFG_KERNEL_SRF_17                                     0xEC6804
+
+#define mmTPC3_CFG_KERNEL_SRF_18                                     0xEC6808
+
+#define mmTPC3_CFG_KERNEL_SRF_19                                     0xEC680C
+
+#define mmTPC3_CFG_KERNEL_SRF_20                                     0xEC6810
+
+#define mmTPC3_CFG_KERNEL_SRF_21                                     0xEC6814
+
+#define mmTPC3_CFG_KERNEL_SRF_22                                     0xEC6818
+
+#define mmTPC3_CFG_KERNEL_SRF_23                                     0xEC681C
+
+#define mmTPC3_CFG_KERNEL_SRF_24                                     0xEC6820
+
+#define mmTPC3_CFG_KERNEL_SRF_25                                     0xEC6824
+
+#define mmTPC3_CFG_KERNEL_SRF_26                                     0xEC6828
+
+#define mmTPC3_CFG_KERNEL_SRF_27                                     0xEC682C
+
+#define mmTPC3_CFG_KERNEL_SRF_28                                     0xEC6830
+
+#define mmTPC3_CFG_KERNEL_SRF_29                                     0xEC6834
+
+#define mmTPC3_CFG_KERNEL_SRF_30                                     0xEC6838
+
+#define mmTPC3_CFG_KERNEL_SRF_31                                     0xEC683C
+
+#define mmTPC3_CFG_ROUND_CSR                                         0xEC68FC
+
+#define mmTPC3_CFG_PROT                                              0xEC6900
+
+#define mmTPC3_CFG_SEMAPHORE                                         0xEC6908
+
+#define mmTPC3_CFG_VFLAGS                                            0xEC690C
+
+#define mmTPC3_CFG_SFLAGS                                            0xEC6910
+
+#define mmTPC3_CFG_LFSR_POLYNOM                                      0xEC6918
+
+#define mmTPC3_CFG_STATUS                                            0xEC691C
+
+#define mmTPC3_CFG_CFG_BASE_ADDRESS_HIGH                             0xEC6920
+
+#define mmTPC3_CFG_CFG_SUBTRACT_VALUE                                0xEC6924
+
+#define mmTPC3_CFG_SM_BASE_ADDRESS_HIGH                              0xEC692C
+
+#define mmTPC3_CFG_TPC_CMD                                           0xEC6930
+
+#define mmTPC3_CFG_TPC_EXECUTE                                       0xEC6938
+
+#define mmTPC3_CFG_TPC_STALL                                         0xEC693C
+
+#define mmTPC3_CFG_ICACHE_BASE_ADDERESS_LOW                          0xEC6940
+
+#define mmTPC3_CFG_ICACHE_BASE_ADDERESS_HIGH                         0xEC6944
+
+#define mmTPC3_CFG_RD_RATE_LIMIT                                     0xEC6948
+
+#define mmTPC3_CFG_WR_RATE_LIMIT                                     0xEC6950
+
+#define mmTPC3_CFG_MSS_CONFIG                                        0xEC6954
+
+#define mmTPC3_CFG_TPC_INTR_CAUSE                                    0xEC6958
+
+#define mmTPC3_CFG_TPC_INTR_MASK                                     0xEC695C
+
+#define mmTPC3_CFG_WQ_CREDITS                                        0xEC6960
+
+#define mmTPC3_CFG_ARUSER_LO                                         0xEC6964
+
+#define mmTPC3_CFG_ARUSER_HI                                         0xEC6968
+
+#define mmTPC3_CFG_AWUSER_LO                                         0xEC696C
+
+#define mmTPC3_CFG_AWUSER_HI                                         0xEC6970
+
+#define mmTPC3_CFG_OPCODE_EXEC                                       0xEC6974
+
+#define mmTPC3_CFG_LUT_FUNC32_BASE_ADDR_LO                           0xEC6978
+
+#define mmTPC3_CFG_LUT_FUNC32_BASE_ADDR_HI                           0xEC697C
+
+#define mmTPC3_CFG_LUT_FUNC64_BASE_ADDR_LO                           0xEC6980
+
+#define mmTPC3_CFG_LUT_FUNC64_BASE_ADDR_HI                           0xEC6984
+
+#define mmTPC3_CFG_LUT_FUNC128_BASE_ADDR_LO                          0xEC6988
+
+#define mmTPC3_CFG_LUT_FUNC128_BASE_ADDR_HI                          0xEC698C
+
+#define mmTPC3_CFG_LUT_FUNC256_BASE_ADDR_LO                          0xEC6990
+
+#define mmTPC3_CFG_LUT_FUNC256_BASE_ADDR_HI                          0xEC6994
+
+#define mmTPC3_CFG_TSB_CFG_MAX_SIZE                                  0xEC6998
+
+#define mmTPC3_CFG_TSB_CFG                                           0xEC699C
+
+#define mmTPC3_CFG_DBGMEM_ADD                                        0xEC69A0
+
+#define mmTPC3_CFG_DBGMEM_DATA_WR                                    0xEC69A4
+
+#define mmTPC3_CFG_DBGMEM_DATA_RD                                    0xEC69A8
+
+#define mmTPC3_CFG_DBGMEM_CTRL                                       0xEC69AC
+
+#define mmTPC3_CFG_DBGMEM_RC                                         0xEC69B0
+
+#define mmTPC3_CFG_TSB_INFLIGHT_CNTR                                 0xEC69B4
+
+#define mmTPC3_CFG_WQ_INFLIGHT_CNTR                                  0xEC69B8
+
+#define mmTPC3_CFG_WQ_LBW_TOTAL_CNTR                                 0xEC69BC
+
+#define mmTPC3_CFG_WQ_HBW_TOTAL_CNTR                                 0xEC69C0
+
+#define mmTPC3_CFG_IRQ_OCCOUPY_CNTR                                  0xEC69C4
+
+#define mmTPC3_CFG_FUNC_MBIST_CNTRL                                  0xEC69D0
+
+#define mmTPC3_CFG_FUNC_MBIST_PAT                                    0xEC69D4
+
+#define mmTPC3_CFG_FUNC_MBIST_MEM_0                                  0xEC69D8
+
+#define mmTPC3_CFG_FUNC_MBIST_MEM_1                                  0xEC69DC
+
+#define mmTPC3_CFG_FUNC_MBIST_MEM_2                                  0xEC69E0
+
+#define mmTPC3_CFG_FUNC_MBIST_MEM_3                                  0xEC69E4
+
+#define mmTPC3_CFG_FUNC_MBIST_MEM_4                                  0xEC69E8
+
+#define mmTPC3_CFG_FUNC_MBIST_MEM_5                                  0xEC69EC
+
+#define mmTPC3_CFG_FUNC_MBIST_MEM_6                                  0xEC69F0
+
+#define mmTPC3_CFG_FUNC_MBIST_MEM_7                                  0xEC69F4
+
+#define mmTPC3_CFG_FUNC_MBIST_MEM_8                                  0xEC69F8
+
+#define mmTPC3_CFG_FUNC_MBIST_MEM_9                                  0xEC69FC
+
+#define mmTPC3_CFG_QM_TENSOR_0_BASE_ADDR_LOW                         0xEC6A00
+
+#define mmTPC3_CFG_QM_TENSOR_0_BASE_ADDR_HIGH                        0xEC6A04
+
+#define mmTPC3_CFG_QM_TENSOR_0_PADDING_VALUE                         0xEC6A08
+
+#define mmTPC3_CFG_QM_TENSOR_0_TENSOR_CONFIG                         0xEC6A0C
+
+#define mmTPC3_CFG_QM_TENSOR_0_DIM_0_SIZE                            0xEC6A10
+
+#define mmTPC3_CFG_QM_TENSOR_0_DIM_0_STRIDE                          0xEC6A14
+
+#define mmTPC3_CFG_QM_TENSOR_0_DIM_1_SIZE                            0xEC6A18
+
+#define mmTPC3_CFG_QM_TENSOR_0_DIM_1_STRIDE                          0xEC6A1C
+
+#define mmTPC3_CFG_QM_TENSOR_0_DIM_2_SIZE                            0xEC6A20
+
+#define mmTPC3_CFG_QM_TENSOR_0_DIM_2_STRIDE                          0xEC6A24
+
+#define mmTPC3_CFG_QM_TENSOR_0_DIM_3_SIZE                            0xEC6A28
+
+#define mmTPC3_CFG_QM_TENSOR_0_DIM_3_STRIDE                          0xEC6A2C
+
+#define mmTPC3_CFG_QM_TENSOR_0_DIM_4_SIZE                            0xEC6A30
+
+#define mmTPC3_CFG_QM_TENSOR_0_DIM_4_STRIDE                          0xEC6A34
+
+#define mmTPC3_CFG_QM_TENSOR_1_BASE_ADDR_LOW                         0xEC6A38
+
+#define mmTPC3_CFG_QM_TENSOR_1_BASE_ADDR_HIGH                        0xEC6A3C
+
+#define mmTPC3_CFG_QM_TENSOR_1_PADDING_VALUE                         0xEC6A40
+
+#define mmTPC3_CFG_QM_TENSOR_1_TENSOR_CONFIG                         0xEC6A44
+
+#define mmTPC3_CFG_QM_TENSOR_1_DIM_0_SIZE                            0xEC6A48
+
+#define mmTPC3_CFG_QM_TENSOR_1_DIM_0_STRIDE                          0xEC6A4C
+
+#define mmTPC3_CFG_QM_TENSOR_1_DIM_1_SIZE                            0xEC6A50
+
+#define mmTPC3_CFG_QM_TENSOR_1_DIM_1_STRIDE                          0xEC6A54
+
+#define mmTPC3_CFG_QM_TENSOR_1_DIM_2_SIZE                            0xEC6A58
+
+#define mmTPC3_CFG_QM_TENSOR_1_DIM_2_STRIDE                          0xEC6A5C
+
+#define mmTPC3_CFG_QM_TENSOR_1_DIM_3_SIZE                            0xEC6A60
+
+#define mmTPC3_CFG_QM_TENSOR_1_DIM_3_STRIDE                          0xEC6A64
+
+#define mmTPC3_CFG_QM_TENSOR_1_DIM_4_SIZE                            0xEC6A68
+
+#define mmTPC3_CFG_QM_TENSOR_1_DIM_4_STRIDE                          0xEC6A6C
+
+#define mmTPC3_CFG_QM_TENSOR_2_BASE_ADDR_LOW                         0xEC6A70
+
+#define mmTPC3_CFG_QM_TENSOR_2_BASE_ADDR_HIGH                        0xEC6A74
+
+#define mmTPC3_CFG_QM_TENSOR_2_PADDING_VALUE                         0xEC6A78
+
+#define mmTPC3_CFG_QM_TENSOR_2_TENSOR_CONFIG                         0xEC6A7C
+
+#define mmTPC3_CFG_QM_TENSOR_2_DIM_0_SIZE                            0xEC6A80
+
+#define mmTPC3_CFG_QM_TENSOR_2_DIM_0_STRIDE                          0xEC6A84
+
+#define mmTPC3_CFG_QM_TENSOR_2_DIM_1_SIZE                            0xEC6A88
+
+#define mmTPC3_CFG_QM_TENSOR_2_DIM_1_STRIDE                          0xEC6A8C
+
+#define mmTPC3_CFG_QM_TENSOR_2_DIM_2_SIZE                            0xEC6A90
+
+#define mmTPC3_CFG_QM_TENSOR_2_DIM_2_STRIDE                          0xEC6A94
+
+#define mmTPC3_CFG_QM_TENSOR_2_DIM_3_SIZE                            0xEC6A98
+
+#define mmTPC3_CFG_QM_TENSOR_2_DIM_3_STRIDE                          0xEC6A9C
+
+#define mmTPC3_CFG_QM_TENSOR_2_DIM_4_SIZE                            0xEC6AA0
+
+#define mmTPC3_CFG_QM_TENSOR_2_DIM_4_STRIDE                          0xEC6AA4
+
+#define mmTPC3_CFG_QM_TENSOR_3_BASE_ADDR_LOW                         0xEC6AA8
+
+#define mmTPC3_CFG_QM_TENSOR_3_BASE_ADDR_HIGH                        0xEC6AAC
+
+#define mmTPC3_CFG_QM_TENSOR_3_PADDING_VALUE                         0xEC6AB0
+
+#define mmTPC3_CFG_QM_TENSOR_3_TENSOR_CONFIG                         0xEC6AB4
+
+#define mmTPC3_CFG_QM_TENSOR_3_DIM_0_SIZE                            0xEC6AB8
+
+#define mmTPC3_CFG_QM_TENSOR_3_DIM_0_STRIDE                          0xEC6ABC
+
+#define mmTPC3_CFG_QM_TENSOR_3_DIM_1_SIZE                            0xEC6AC0
+
+#define mmTPC3_CFG_QM_TENSOR_3_DIM_1_STRIDE                          0xEC6AC4
+
+#define mmTPC3_CFG_QM_TENSOR_3_DIM_2_SIZE                            0xEC6AC8
+
+#define mmTPC3_CFG_QM_TENSOR_3_DIM_2_STRIDE                          0xEC6ACC
+
+#define mmTPC3_CFG_QM_TENSOR_3_DIM_3_SIZE                            0xEC6AD0
+
+#define mmTPC3_CFG_QM_TENSOR_3_DIM_3_STRIDE                          0xEC6AD4
+
+#define mmTPC3_CFG_QM_TENSOR_3_DIM_4_SIZE                            0xEC6AD8
+
+#define mmTPC3_CFG_QM_TENSOR_3_DIM_4_STRIDE                          0xEC6ADC
+
+#define mmTPC3_CFG_QM_TENSOR_4_BASE_ADDR_LOW                         0xEC6AE0
+
+#define mmTPC3_CFG_QM_TENSOR_4_BASE_ADDR_HIGH                        0xEC6AE4
+
+#define mmTPC3_CFG_QM_TENSOR_4_PADDING_VALUE                         0xEC6AE8
+
+#define mmTPC3_CFG_QM_TENSOR_4_TENSOR_CONFIG                         0xEC6AEC
+
+#define mmTPC3_CFG_QM_TENSOR_4_DIM_0_SIZE                            0xEC6AF0
+
+#define mmTPC3_CFG_QM_TENSOR_4_DIM_0_STRIDE                          0xEC6AF4
+
+#define mmTPC3_CFG_QM_TENSOR_4_DIM_1_SIZE                            0xEC6AF8
+
+#define mmTPC3_CFG_QM_TENSOR_4_DIM_1_STRIDE                          0xEC6AFC
+
+#define mmTPC3_CFG_QM_TENSOR_4_DIM_2_SIZE                            0xEC6B00
+
+#define mmTPC3_CFG_QM_TENSOR_4_DIM_2_STRIDE                          0xEC6B04
+
+#define mmTPC3_CFG_QM_TENSOR_4_DIM_3_SIZE                            0xEC6B08
+
+#define mmTPC3_CFG_QM_TENSOR_4_DIM_3_STRIDE                          0xEC6B0C
+
+#define mmTPC3_CFG_QM_TENSOR_4_DIM_4_SIZE                            0xEC6B10
+
+#define mmTPC3_CFG_QM_TENSOR_4_DIM_4_STRIDE                          0xEC6B14
+
+#define mmTPC3_CFG_QM_TENSOR_5_BASE_ADDR_LOW                         0xEC6B18
+
+#define mmTPC3_CFG_QM_TENSOR_5_BASE_ADDR_HIGH                        0xEC6B1C
+
+#define mmTPC3_CFG_QM_TENSOR_5_PADDING_VALUE                         0xEC6B20
+
+#define mmTPC3_CFG_QM_TENSOR_5_TENSOR_CONFIG                         0xEC6B24
+
+#define mmTPC3_CFG_QM_TENSOR_5_DIM_0_SIZE                            0xEC6B28
+
+#define mmTPC3_CFG_QM_TENSOR_5_DIM_0_STRIDE                          0xEC6B2C
+
+#define mmTPC3_CFG_QM_TENSOR_5_DIM_1_SIZE                            0xEC6B30
+
+#define mmTPC3_CFG_QM_TENSOR_5_DIM_1_STRIDE                          0xEC6B34
+
+#define mmTPC3_CFG_QM_TENSOR_5_DIM_2_SIZE                            0xEC6B38
+
+#define mmTPC3_CFG_QM_TENSOR_5_DIM_2_STRIDE                          0xEC6B3C
+
+#define mmTPC3_CFG_QM_TENSOR_5_DIM_3_SIZE                            0xEC6B40
+
+#define mmTPC3_CFG_QM_TENSOR_5_DIM_3_STRIDE                          0xEC6B44
+
+#define mmTPC3_CFG_QM_TENSOR_5_DIM_4_SIZE                            0xEC6B48
+
+#define mmTPC3_CFG_QM_TENSOR_5_DIM_4_STRIDE                          0xEC6B4C
+
+#define mmTPC3_CFG_QM_TENSOR_6_BASE_ADDR_LOW                         0xEC6B50
+
+#define mmTPC3_CFG_QM_TENSOR_6_BASE_ADDR_HIGH                        0xEC6B54
+
+#define mmTPC3_CFG_QM_TENSOR_6_PADDING_VALUE                         0xEC6B58
+
+#define mmTPC3_CFG_QM_TENSOR_6_TENSOR_CONFIG                         0xEC6B5C
+
+#define mmTPC3_CFG_QM_TENSOR_6_DIM_0_SIZE                            0xEC6B60
+
+#define mmTPC3_CFG_QM_TENSOR_6_DIM_0_STRIDE                          0xEC6B64
+
+#define mmTPC3_CFG_QM_TENSOR_6_DIM_1_SIZE                            0xEC6B68
+
+#define mmTPC3_CFG_QM_TENSOR_6_DIM_1_STRIDE                          0xEC6B6C
+
+#define mmTPC3_CFG_QM_TENSOR_6_DIM_2_SIZE                            0xEC6B70
+
+#define mmTPC3_CFG_QM_TENSOR_6_DIM_2_STRIDE                          0xEC6B74
+
+#define mmTPC3_CFG_QM_TENSOR_6_DIM_3_SIZE                            0xEC6B78
+
+#define mmTPC3_CFG_QM_TENSOR_6_DIM_3_STRIDE                          0xEC6B7C
+
+#define mmTPC3_CFG_QM_TENSOR_6_DIM_4_SIZE                            0xEC6B80
+
+#define mmTPC3_CFG_QM_TENSOR_6_DIM_4_STRIDE                          0xEC6B84
+
+#define mmTPC3_CFG_QM_TENSOR_7_BASE_ADDR_LOW                         0xEC6B88
+
+#define mmTPC3_CFG_QM_TENSOR_7_BASE_ADDR_HIGH                        0xEC6B8C
+
+#define mmTPC3_CFG_QM_TENSOR_7_PADDING_VALUE                         0xEC6B90
+
+#define mmTPC3_CFG_QM_TENSOR_7_TENSOR_CONFIG                         0xEC6B94
+
+#define mmTPC3_CFG_QM_TENSOR_7_DIM_0_SIZE                            0xEC6B98
+
+#define mmTPC3_CFG_QM_TENSOR_7_DIM_0_STRIDE                          0xEC6B9C
+
+#define mmTPC3_CFG_QM_TENSOR_7_DIM_1_SIZE                            0xEC6BA0
+
+#define mmTPC3_CFG_QM_TENSOR_7_DIM_1_STRIDE                          0xEC6BA4
+
+#define mmTPC3_CFG_QM_TENSOR_7_DIM_2_SIZE                            0xEC6BA8
+
+#define mmTPC3_CFG_QM_TENSOR_7_DIM_2_STRIDE                          0xEC6BAC
+
+#define mmTPC3_CFG_QM_TENSOR_7_DIM_3_SIZE                            0xEC6BB0
+
+#define mmTPC3_CFG_QM_TENSOR_7_DIM_3_STRIDE                          0xEC6BB4
+
+#define mmTPC3_CFG_QM_TENSOR_7_DIM_4_SIZE                            0xEC6BB8
+
+#define mmTPC3_CFG_QM_TENSOR_7_DIM_4_STRIDE                          0xEC6BBC
+
+#define mmTPC3_CFG_QM_TENSOR_8_BASE_ADDR_LOW                         0xEC6BC0
+
+#define mmTPC3_CFG_QM_TENSOR_8_BASE_ADDR_HIGH                        0xEC6BC4
+
+#define mmTPC3_CFG_QM_TENSOR_8_PADDING_VALUE                         0xEC6BC8
+
+#define mmTPC3_CFG_QM_TENSOR_8_TENSOR_CONFIG                         0xEC6BCC
+
+#define mmTPC3_CFG_QM_TENSOR_8_DIM_0_SIZE                            0xEC6BD0
+
+#define mmTPC3_CFG_QM_TENSOR_8_DIM_0_STRIDE                          0xEC6BD4
+
+#define mmTPC3_CFG_QM_TENSOR_8_DIM_1_SIZE                            0xEC6BD8
+
+#define mmTPC3_CFG_QM_TENSOR_8_DIM_1_STRIDE                          0xEC6BDC
+
+#define mmTPC3_CFG_QM_TENSOR_8_DIM_2_SIZE                            0xEC6BE0
+
+#define mmTPC3_CFG_QM_TENSOR_8_DIM_2_STRIDE                          0xEC6BE4
+
+#define mmTPC3_CFG_QM_TENSOR_8_DIM_3_SIZE                            0xEC6BE8
+
+#define mmTPC3_CFG_QM_TENSOR_8_DIM_3_STRIDE                          0xEC6BEC
+
+#define mmTPC3_CFG_QM_TENSOR_8_DIM_4_SIZE                            0xEC6BF0
+
+#define mmTPC3_CFG_QM_TENSOR_8_DIM_4_STRIDE                          0xEC6BF4
+
+#define mmTPC3_CFG_QM_TENSOR_9_BASE_ADDR_LOW                         0xEC6BF8
+
+#define mmTPC3_CFG_QM_TENSOR_9_BASE_ADDR_HIGH                        0xEC6BFC
+
+#define mmTPC3_CFG_QM_TENSOR_9_PADDING_VALUE                         0xEC6C00
+
+#define mmTPC3_CFG_QM_TENSOR_9_TENSOR_CONFIG                         0xEC6C04
+
+#define mmTPC3_CFG_QM_TENSOR_9_DIM_0_SIZE                            0xEC6C08
+
+#define mmTPC3_CFG_QM_TENSOR_9_DIM_0_STRIDE                          0xEC6C0C
+
+#define mmTPC3_CFG_QM_TENSOR_9_DIM_1_SIZE                            0xEC6C10
+
+#define mmTPC3_CFG_QM_TENSOR_9_DIM_1_STRIDE                          0xEC6C14
+
+#define mmTPC3_CFG_QM_TENSOR_9_DIM_2_SIZE                            0xEC6C18
+
+#define mmTPC3_CFG_QM_TENSOR_9_DIM_2_STRIDE                          0xEC6C1C
+
+#define mmTPC3_CFG_QM_TENSOR_9_DIM_3_SIZE                            0xEC6C20
+
+#define mmTPC3_CFG_QM_TENSOR_9_DIM_3_STRIDE                          0xEC6C24
+
+#define mmTPC3_CFG_QM_TENSOR_9_DIM_4_SIZE                            0xEC6C28
+
+#define mmTPC3_CFG_QM_TENSOR_9_DIM_4_STRIDE                          0xEC6C2C
+
+#define mmTPC3_CFG_QM_TENSOR_10_BASE_ADDR_LOW                        0xEC6C30
+
+#define mmTPC3_CFG_QM_TENSOR_10_BASE_ADDR_HIGH                       0xEC6C34
+
+#define mmTPC3_CFG_QM_TENSOR_10_PADDING_VALUE                        0xEC6C38
+
+#define mmTPC3_CFG_QM_TENSOR_10_TENSOR_CONFIG                        0xEC6C3C
+
+#define mmTPC3_CFG_QM_TENSOR_10_DIM_0_SIZE                           0xEC6C40
+
+#define mmTPC3_CFG_QM_TENSOR_10_DIM_0_STRIDE                         0xEC6C44
+
+#define mmTPC3_CFG_QM_TENSOR_10_DIM_1_SIZE                           0xEC6C48
+
+#define mmTPC3_CFG_QM_TENSOR_10_DIM_1_STRIDE                         0xEC6C4C
+
+#define mmTPC3_CFG_QM_TENSOR_10_DIM_2_SIZE                           0xEC6C50
+
+#define mmTPC3_CFG_QM_TENSOR_10_DIM_2_STRIDE                         0xEC6C54
+
+#define mmTPC3_CFG_QM_TENSOR_10_DIM_3_SIZE                           0xEC6C58
+
+#define mmTPC3_CFG_QM_TENSOR_10_DIM_3_STRIDE                         0xEC6C5C
+
+#define mmTPC3_CFG_QM_TENSOR_10_DIM_4_SIZE                           0xEC6C60
+
+#define mmTPC3_CFG_QM_TENSOR_10_DIM_4_STRIDE                         0xEC6C64
+
+#define mmTPC3_CFG_QM_TENSOR_11_BASE_ADDR_LOW                        0xEC6C68
+
+#define mmTPC3_CFG_QM_TENSOR_11_BASE_ADDR_HIGH                       0xEC6C6C
+
+#define mmTPC3_CFG_QM_TENSOR_11_PADDING_VALUE                        0xEC6C70
+
+#define mmTPC3_CFG_QM_TENSOR_11_TENSOR_CONFIG                        0xEC6C74
+
+#define mmTPC3_CFG_QM_TENSOR_11_DIM_0_SIZE                           0xEC6C78
+
+#define mmTPC3_CFG_QM_TENSOR_11_DIM_0_STRIDE                         0xEC6C7C
+
+#define mmTPC3_CFG_QM_TENSOR_11_DIM_1_SIZE                           0xEC6C80
+
+#define mmTPC3_CFG_QM_TENSOR_11_DIM_1_STRIDE                         0xEC6C84
+
+#define mmTPC3_CFG_QM_TENSOR_11_DIM_2_SIZE                           0xEC6C88
+
+#define mmTPC3_CFG_QM_TENSOR_11_DIM_2_STRIDE                         0xEC6C8C
+
+#define mmTPC3_CFG_QM_TENSOR_11_DIM_3_SIZE                           0xEC6C90
+
+#define mmTPC3_CFG_QM_TENSOR_11_DIM_3_STRIDE                         0xEC6C94
+
+#define mmTPC3_CFG_QM_TENSOR_11_DIM_4_SIZE                           0xEC6C98
+
+#define mmTPC3_CFG_QM_TENSOR_11_DIM_4_STRIDE                         0xEC6C9C
+
+#define mmTPC3_CFG_QM_TENSOR_12_BASE_ADDR_LOW                        0xEC6CA0
+
+#define mmTPC3_CFG_QM_TENSOR_12_BASE_ADDR_HIGH                       0xEC6CA4
+
+#define mmTPC3_CFG_QM_TENSOR_12_PADDING_VALUE                        0xEC6CA8
+
+#define mmTPC3_CFG_QM_TENSOR_12_TENSOR_CONFIG                        0xEC6CAC
+
+#define mmTPC3_CFG_QM_TENSOR_12_DIM_0_SIZE                           0xEC6CB0
+
+#define mmTPC3_CFG_QM_TENSOR_12_DIM_0_STRIDE                         0xEC6CB4
+
+#define mmTPC3_CFG_QM_TENSOR_12_DIM_1_SIZE                           0xEC6CB8
+
+#define mmTPC3_CFG_QM_TENSOR_12_DIM_1_STRIDE                         0xEC6CBC
+
+#define mmTPC3_CFG_QM_TENSOR_12_DIM_2_SIZE                           0xEC6CC0
+
+#define mmTPC3_CFG_QM_TENSOR_12_DIM_2_STRIDE                         0xEC6CC4
+
+#define mmTPC3_CFG_QM_TENSOR_12_DIM_3_SIZE                           0xEC6CC8
+
+#define mmTPC3_CFG_QM_TENSOR_12_DIM_3_STRIDE                         0xEC6CCC
+
+#define mmTPC3_CFG_QM_TENSOR_12_DIM_4_SIZE                           0xEC6CD0
+
+#define mmTPC3_CFG_QM_TENSOR_12_DIM_4_STRIDE                         0xEC6CD4
+
+#define mmTPC3_CFG_QM_TENSOR_13_BASE_ADDR_LOW                        0xEC6CD8
+
+#define mmTPC3_CFG_QM_TENSOR_13_BASE_ADDR_HIGH                       0xEC6CDC
+
+#define mmTPC3_CFG_QM_TENSOR_13_PADDING_VALUE                        0xEC6CE0
+
+#define mmTPC3_CFG_QM_TENSOR_13_TENSOR_CONFIG                        0xEC6CE4
+
+#define mmTPC3_CFG_QM_TENSOR_13_DIM_0_SIZE                           0xEC6CE8
+
+#define mmTPC3_CFG_QM_TENSOR_13_DIM_0_STRIDE                         0xEC6CEC
+
+#define mmTPC3_CFG_QM_TENSOR_13_DIM_1_SIZE                           0xEC6CF0
+
+#define mmTPC3_CFG_QM_TENSOR_13_DIM_1_STRIDE                         0xEC6CF4
+
+#define mmTPC3_CFG_QM_TENSOR_13_DIM_2_SIZE                           0xEC6CF8
+
+#define mmTPC3_CFG_QM_TENSOR_13_DIM_2_STRIDE                         0xEC6CFC
+
+#define mmTPC3_CFG_QM_TENSOR_13_DIM_3_SIZE                           0xEC6D00
+
+#define mmTPC3_CFG_QM_TENSOR_13_DIM_3_STRIDE                         0xEC6D04
+
+#define mmTPC3_CFG_QM_TENSOR_13_DIM_4_SIZE                           0xEC6D08
+
+#define mmTPC3_CFG_QM_TENSOR_13_DIM_4_STRIDE                         0xEC6D0C
+
+#define mmTPC3_CFG_QM_TENSOR_14_BASE_ADDR_LOW                        0xEC6D10
+
+#define mmTPC3_CFG_QM_TENSOR_14_BASE_ADDR_HIGH                       0xEC6D14
+
+#define mmTPC3_CFG_QM_TENSOR_14_PADDING_VALUE                        0xEC6D18
+
+#define mmTPC3_CFG_QM_TENSOR_14_TENSOR_CONFIG                        0xEC6D1C
+
+#define mmTPC3_CFG_QM_TENSOR_14_DIM_0_SIZE                           0xEC6D20
+
+#define mmTPC3_CFG_QM_TENSOR_14_DIM_0_STRIDE                         0xEC6D24
+
+#define mmTPC3_CFG_QM_TENSOR_14_DIM_1_SIZE                           0xEC6D28
+
+#define mmTPC3_CFG_QM_TENSOR_14_DIM_1_STRIDE                         0xEC6D2C
+
+#define mmTPC3_CFG_QM_TENSOR_14_DIM_2_SIZE                           0xEC6D30
+
+#define mmTPC3_CFG_QM_TENSOR_14_DIM_2_STRIDE                         0xEC6D34
+
+#define mmTPC3_CFG_QM_TENSOR_14_DIM_3_SIZE                           0xEC6D38
+
+#define mmTPC3_CFG_QM_TENSOR_14_DIM_3_STRIDE                         0xEC6D3C
+
+#define mmTPC3_CFG_QM_TENSOR_14_DIM_4_SIZE                           0xEC6D40
+
+#define mmTPC3_CFG_QM_TENSOR_14_DIM_4_STRIDE                         0xEC6D44
+
+#define mmTPC3_CFG_QM_TENSOR_15_BASE_ADDR_LOW                        0xEC6D48
+
+#define mmTPC3_CFG_QM_TENSOR_15_BASE_ADDR_HIGH                       0xEC6D4C
+
+#define mmTPC3_CFG_QM_TENSOR_15_PADDING_VALUE                        0xEC6D50
+
+#define mmTPC3_CFG_QM_TENSOR_15_TENSOR_CONFIG                        0xEC6D54
+
+#define mmTPC3_CFG_QM_TENSOR_15_DIM_0_SIZE                           0xEC6D58
+
+#define mmTPC3_CFG_QM_TENSOR_15_DIM_0_STRIDE                         0xEC6D5C
+
+#define mmTPC3_CFG_QM_TENSOR_15_DIM_1_SIZE                           0xEC6D60
+
+#define mmTPC3_CFG_QM_TENSOR_15_DIM_1_STRIDE                         0xEC6D64
+
+#define mmTPC3_CFG_QM_TENSOR_15_DIM_2_SIZE                           0xEC6D68
+
+#define mmTPC3_CFG_QM_TENSOR_15_DIM_2_STRIDE                         0xEC6D6C
+
+#define mmTPC3_CFG_QM_TENSOR_15_DIM_3_SIZE                           0xEC6D70
+
+#define mmTPC3_CFG_QM_TENSOR_15_DIM_3_STRIDE                         0xEC6D74
+
+#define mmTPC3_CFG_QM_TENSOR_15_DIM_4_SIZE                           0xEC6D78
+
+#define mmTPC3_CFG_QM_TENSOR_15_DIM_4_STRIDE                         0xEC6D7C
+
+#define mmTPC3_CFG_QM_SYNC_OBJECT_MESSAGE                            0xEC6D80
+
+#define mmTPC3_CFG_QM_SYNC_OBJECT_ADDR                               0xEC6D84
+
+#define mmTPC3_CFG_QM_KERNEL_BASE_ADDRESS_LOW                        0xEC6D88
+
+#define mmTPC3_CFG_QM_KERNEL_BASE_ADDRESS_HIGH                       0xEC6D8C
+
+#define mmTPC3_CFG_QM_TID_BASE_DIM_0                                 0xEC6D90
+
+#define mmTPC3_CFG_QM_TID_SIZE_DIM_0                                 0xEC6D94
+
+#define mmTPC3_CFG_QM_TID_BASE_DIM_1                                 0xEC6D98
+
+#define mmTPC3_CFG_QM_TID_SIZE_DIM_1                                 0xEC6D9C
+
+#define mmTPC3_CFG_QM_TID_BASE_DIM_2                                 0xEC6DA0
+
+#define mmTPC3_CFG_QM_TID_SIZE_DIM_2                                 0xEC6DA4
+
+#define mmTPC3_CFG_QM_TID_BASE_DIM_3                                 0xEC6DA8
+
+#define mmTPC3_CFG_QM_TID_SIZE_DIM_3                                 0xEC6DAC
+
+#define mmTPC3_CFG_QM_TID_BASE_DIM_4                                 0xEC6DB0
+
+#define mmTPC3_CFG_QM_TID_SIZE_DIM_4                                 0xEC6DB4
+
+#define mmTPC3_CFG_QM_KERNEL_CONFIG                                  0xEC6DB8
+
+#define mmTPC3_CFG_QM_KERNEL_ID                                      0xEC6DBC
+
+#define mmTPC3_CFG_QM_SRF_0                                          0xEC6DC0
+
+#define mmTPC3_CFG_QM_SRF_1                                          0xEC6DC4
+
+#define mmTPC3_CFG_QM_SRF_2                                          0xEC6DC8
+
+#define mmTPC3_CFG_QM_SRF_3                                          0xEC6DCC
+
+#define mmTPC3_CFG_QM_SRF_4                                          0xEC6DD0
+
+#define mmTPC3_CFG_QM_SRF_5                                          0xEC6DD4
+
+#define mmTPC3_CFG_QM_SRF_6                                          0xEC6DD8
+
+#define mmTPC3_CFG_QM_SRF_7                                          0xEC6DDC
+
+#define mmTPC3_CFG_QM_SRF_8                                          0xEC6DE0
+
+#define mmTPC3_CFG_QM_SRF_9                                          0xEC6DE4
+
+#define mmTPC3_CFG_QM_SRF_10                                         0xEC6DE8
+
+#define mmTPC3_CFG_QM_SRF_11                                         0xEC6DEC
+
+#define mmTPC3_CFG_QM_SRF_12                                         0xEC6DF0
+
+#define mmTPC3_CFG_QM_SRF_13                                         0xEC6DF4
+
+#define mmTPC3_CFG_QM_SRF_14                                         0xEC6DF8
+
+#define mmTPC3_CFG_QM_SRF_15                                         0xEC6DFC
+
+#define mmTPC3_CFG_QM_SRF_16                                         0xEC6E00
+
+#define mmTPC3_CFG_QM_SRF_17                                         0xEC6E04
+
+#define mmTPC3_CFG_QM_SRF_18                                         0xEC6E08
+
+#define mmTPC3_CFG_QM_SRF_19                                         0xEC6E0C
+
+#define mmTPC3_CFG_QM_SRF_20                                         0xEC6E10
+
+#define mmTPC3_CFG_QM_SRF_21                                         0xEC6E14
+
+#define mmTPC3_CFG_QM_SRF_22                                         0xEC6E18
+
+#define mmTPC3_CFG_QM_SRF_23                                         0xEC6E1C
+
+#define mmTPC3_CFG_QM_SRF_24                                         0xEC6E20
+
+#define mmTPC3_CFG_QM_SRF_25                                         0xEC6E24
+
+#define mmTPC3_CFG_QM_SRF_26                                         0xEC6E28
+
+#define mmTPC3_CFG_QM_SRF_27                                         0xEC6E2C
+
+#define mmTPC3_CFG_QM_SRF_28                                         0xEC6E30
+
+#define mmTPC3_CFG_QM_SRF_29                                         0xEC6E34
+
+#define mmTPC3_CFG_QM_SRF_30                                         0xEC6E38
+
+#define mmTPC3_CFG_QM_SRF_31                                         0xEC6E3C
+
+#endif /* ASIC_REG_TPC3_CFG_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc3_qm_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc3_qm_regs.h
new file mode 100644
index 000000000000..5f2a0fd86c9e
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc3_qm_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_TPC3_QM_REGS_H_
+#define ASIC_REG_TPC3_QM_REGS_H_
+
+/*
+ *****************************************
+ *   TPC3_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmTPC3_QM_GLBL_CFG0                                          0xEC8000
+
+#define mmTPC3_QM_GLBL_CFG1                                          0xEC8004
+
+#define mmTPC3_QM_GLBL_PROT                                          0xEC8008
+
+#define mmTPC3_QM_GLBL_ERR_CFG                                       0xEC800C
+
+#define mmTPC3_QM_GLBL_SECURE_PROPS_0                                0xEC8010
+
+#define mmTPC3_QM_GLBL_SECURE_PROPS_1                                0xEC8014
+
+#define mmTPC3_QM_GLBL_SECURE_PROPS_2                                0xEC8018
+
+#define mmTPC3_QM_GLBL_SECURE_PROPS_3                                0xEC801C
+
+#define mmTPC3_QM_GLBL_SECURE_PROPS_4                                0xEC8020
+
+#define mmTPC3_QM_GLBL_NON_SECURE_PROPS_0                            0xEC8024
+
+#define mmTPC3_QM_GLBL_NON_SECURE_PROPS_1                            0xEC8028
+
+#define mmTPC3_QM_GLBL_NON_SECURE_PROPS_2                            0xEC802C
+
+#define mmTPC3_QM_GLBL_NON_SECURE_PROPS_3                            0xEC8030
+
+#define mmTPC3_QM_GLBL_NON_SECURE_PROPS_4                            0xEC8034
+
+#define mmTPC3_QM_GLBL_STS0                                          0xEC8038
+
+#define mmTPC3_QM_GLBL_STS1_0                                        0xEC8040
+
+#define mmTPC3_QM_GLBL_STS1_1                                        0xEC8044
+
+#define mmTPC3_QM_GLBL_STS1_2                                        0xEC8048
+
+#define mmTPC3_QM_GLBL_STS1_3                                        0xEC804C
+
+#define mmTPC3_QM_GLBL_STS1_4                                        0xEC8050
+
+#define mmTPC3_QM_GLBL_MSG_EN_0                                      0xEC8054
+
+#define mmTPC3_QM_GLBL_MSG_EN_1                                      0xEC8058
+
+#define mmTPC3_QM_GLBL_MSG_EN_2                                      0xEC805C
+
+#define mmTPC3_QM_GLBL_MSG_EN_3                                      0xEC8060
+
+#define mmTPC3_QM_GLBL_MSG_EN_4                                      0xEC8068
+
+#define mmTPC3_QM_PQ_BASE_LO_0                                       0xEC8070
+
+#define mmTPC3_QM_PQ_BASE_LO_1                                       0xEC8074
+
+#define mmTPC3_QM_PQ_BASE_LO_2                                       0xEC8078
+
+#define mmTPC3_QM_PQ_BASE_LO_3                                       0xEC807C
+
+#define mmTPC3_QM_PQ_BASE_HI_0                                       0xEC8080
+
+#define mmTPC3_QM_PQ_BASE_HI_1                                       0xEC8084
+
+#define mmTPC3_QM_PQ_BASE_HI_2                                       0xEC8088
+
+#define mmTPC3_QM_PQ_BASE_HI_3                                       0xEC808C
+
+#define mmTPC3_QM_PQ_SIZE_0                                          0xEC8090
+
+#define mmTPC3_QM_PQ_SIZE_1                                          0xEC8094
+
+#define mmTPC3_QM_PQ_SIZE_2                                          0xEC8098
+
+#define mmTPC3_QM_PQ_SIZE_3                                          0xEC809C
+
+#define mmTPC3_QM_PQ_PI_0                                            0xEC80A0
+
+#define mmTPC3_QM_PQ_PI_1                                            0xEC80A4
+
+#define mmTPC3_QM_PQ_PI_2                                            0xEC80A8
+
+#define mmTPC3_QM_PQ_PI_3                                            0xEC80AC
+
+#define mmTPC3_QM_PQ_CI_0                                            0xEC80B0
+
+#define mmTPC3_QM_PQ_CI_1                                            0xEC80B4
+
+#define mmTPC3_QM_PQ_CI_2                                            0xEC80B8
+
+#define mmTPC3_QM_PQ_CI_3                                            0xEC80BC
+
+#define mmTPC3_QM_PQ_CFG0_0                                          0xEC80C0
+
+#define mmTPC3_QM_PQ_CFG0_1                                          0xEC80C4
+
+#define mmTPC3_QM_PQ_CFG0_2                                          0xEC80C8
+
+#define mmTPC3_QM_PQ_CFG0_3                                          0xEC80CC
+
+#define mmTPC3_QM_PQ_CFG1_0                                          0xEC80D0
+
+#define mmTPC3_QM_PQ_CFG1_1                                          0xEC80D4
+
+#define mmTPC3_QM_PQ_CFG1_2                                          0xEC80D8
+
+#define mmTPC3_QM_PQ_CFG1_3                                          0xEC80DC
+
+#define mmTPC3_QM_PQ_ARUSER_31_11_0                                  0xEC80E0
+
+#define mmTPC3_QM_PQ_ARUSER_31_11_1                                  0xEC80E4
+
+#define mmTPC3_QM_PQ_ARUSER_31_11_2                                  0xEC80E8
+
+#define mmTPC3_QM_PQ_ARUSER_31_11_3                                  0xEC80EC
+
+#define mmTPC3_QM_PQ_STS0_0                                          0xEC80F0
+
+#define mmTPC3_QM_PQ_STS0_1                                          0xEC80F4
+
+#define mmTPC3_QM_PQ_STS0_2                                          0xEC80F8
+
+#define mmTPC3_QM_PQ_STS0_3                                          0xEC80FC
+
+#define mmTPC3_QM_PQ_STS1_0                                          0xEC8100
+
+#define mmTPC3_QM_PQ_STS1_1                                          0xEC8104
+
+#define mmTPC3_QM_PQ_STS1_2                                          0xEC8108
+
+#define mmTPC3_QM_PQ_STS1_3                                          0xEC810C
+
+#define mmTPC3_QM_CQ_CFG0_0                                          0xEC8110
+
+#define mmTPC3_QM_CQ_CFG0_1                                          0xEC8114
+
+#define mmTPC3_QM_CQ_CFG0_2                                          0xEC8118
+
+#define mmTPC3_QM_CQ_CFG0_3                                          0xEC811C
+
+#define mmTPC3_QM_CQ_CFG0_4                                          0xEC8120
+
+#define mmTPC3_QM_CQ_CFG1_0                                          0xEC8124
+
+#define mmTPC3_QM_CQ_CFG1_1                                          0xEC8128
+
+#define mmTPC3_QM_CQ_CFG1_2                                          0xEC812C
+
+#define mmTPC3_QM_CQ_CFG1_3                                          0xEC8130
+
+#define mmTPC3_QM_CQ_CFG1_4                                          0xEC8134
+
+#define mmTPC3_QM_CQ_ARUSER_31_11_0                                  0xEC8138
+
+#define mmTPC3_QM_CQ_ARUSER_31_11_1                                  0xEC813C
+
+#define mmTPC3_QM_CQ_ARUSER_31_11_2                                  0xEC8140
+
+#define mmTPC3_QM_CQ_ARUSER_31_11_3                                  0xEC8144
+
+#define mmTPC3_QM_CQ_ARUSER_31_11_4                                  0xEC8148
+
+#define mmTPC3_QM_CQ_STS0_0                                          0xEC814C
+
+#define mmTPC3_QM_CQ_STS0_1                                          0xEC8150
+
+#define mmTPC3_QM_CQ_STS0_2                                          0xEC8154
+
+#define mmTPC3_QM_CQ_STS0_3                                          0xEC8158
+
+#define mmTPC3_QM_CQ_STS0_4                                          0xEC815C
+
+#define mmTPC3_QM_CQ_STS1_0                                          0xEC8160
+
+#define mmTPC3_QM_CQ_STS1_1                                          0xEC8164
+
+#define mmTPC3_QM_CQ_STS1_2                                          0xEC8168
+
+#define mmTPC3_QM_CQ_STS1_3                                          0xEC816C
+
+#define mmTPC3_QM_CQ_STS1_4                                          0xEC8170
+
+#define mmTPC3_QM_CQ_PTR_LO_0                                        0xEC8174
+
+#define mmTPC3_QM_CQ_PTR_HI_0                                        0xEC8178
+
+#define mmTPC3_QM_CQ_TSIZE_0                                         0xEC817C
+
+#define mmTPC3_QM_CQ_CTL_0                                           0xEC8180
+
+#define mmTPC3_QM_CQ_PTR_LO_1                                        0xEC8184
+
+#define mmTPC3_QM_CQ_PTR_HI_1                                        0xEC8188
+
+#define mmTPC3_QM_CQ_TSIZE_1                                         0xEC818C
+
+#define mmTPC3_QM_CQ_CTL_1                                           0xEC8190
+
+#define mmTPC3_QM_CQ_PTR_LO_2                                        0xEC8194
+
+#define mmTPC3_QM_CQ_PTR_HI_2                                        0xEC8198
+
+#define mmTPC3_QM_CQ_TSIZE_2                                         0xEC819C
+
+#define mmTPC3_QM_CQ_CTL_2                                           0xEC81A0
+
+#define mmTPC3_QM_CQ_PTR_LO_3                                        0xEC81A4
+
+#define mmTPC3_QM_CQ_PTR_HI_3                                        0xEC81A8
+
+#define mmTPC3_QM_CQ_TSIZE_3                                         0xEC81AC
+
+#define mmTPC3_QM_CQ_CTL_3                                           0xEC81B0
+
+#define mmTPC3_QM_CQ_PTR_LO_4                                        0xEC81B4
+
+#define mmTPC3_QM_CQ_PTR_HI_4                                        0xEC81B8
+
+#define mmTPC3_QM_CQ_TSIZE_4                                         0xEC81BC
+
+#define mmTPC3_QM_CQ_CTL_4                                           0xEC81C0
+
+#define mmTPC3_QM_CQ_PTR_LO_STS_0                                    0xEC81C4
+
+#define mmTPC3_QM_CQ_PTR_LO_STS_1                                    0xEC81C8
+
+#define mmTPC3_QM_CQ_PTR_LO_STS_2                                    0xEC81CC
+
+#define mmTPC3_QM_CQ_PTR_LO_STS_3                                    0xEC81D0
+
+#define mmTPC3_QM_CQ_PTR_LO_STS_4                                    0xEC81D4
+
+#define mmTPC3_QM_CQ_PTR_HI_STS_0                                    0xEC81D8
+
+#define mmTPC3_QM_CQ_PTR_HI_STS_1                                    0xEC81DC
+
+#define mmTPC3_QM_CQ_PTR_HI_STS_2                                    0xEC81E0
+
+#define mmTPC3_QM_CQ_PTR_HI_STS_3                                    0xEC81E4
+
+#define mmTPC3_QM_CQ_PTR_HI_STS_4                                    0xEC81E8
+
+#define mmTPC3_QM_CQ_TSIZE_STS_0                                     0xEC81EC
+
+#define mmTPC3_QM_CQ_TSIZE_STS_1                                     0xEC81F0
+
+#define mmTPC3_QM_CQ_TSIZE_STS_2                                     0xEC81F4
+
+#define mmTPC3_QM_CQ_TSIZE_STS_3                                     0xEC81F8
+
+#define mmTPC3_QM_CQ_TSIZE_STS_4                                     0xEC81FC
+
+#define mmTPC3_QM_CQ_CTL_STS_0                                       0xEC8200
+
+#define mmTPC3_QM_CQ_CTL_STS_1                                       0xEC8204
+
+#define mmTPC3_QM_CQ_CTL_STS_2                                       0xEC8208
+
+#define mmTPC3_QM_CQ_CTL_STS_3                                       0xEC820C
+
+#define mmTPC3_QM_CQ_CTL_STS_4                                       0xEC8210
+
+#define mmTPC3_QM_CQ_IFIFO_CNT_0                                     0xEC8214
+
+#define mmTPC3_QM_CQ_IFIFO_CNT_1                                     0xEC8218
+
+#define mmTPC3_QM_CQ_IFIFO_CNT_2                                     0xEC821C
+
+#define mmTPC3_QM_CQ_IFIFO_CNT_3                                     0xEC8220
+
+#define mmTPC3_QM_CQ_IFIFO_CNT_4                                     0xEC8224
+
+#define mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_0                             0xEC8228
+
+#define mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_1                             0xEC822C
+
+#define mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_2                             0xEC8230
+
+#define mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_3                             0xEC8234
+
+#define mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_4                             0xEC8238
+
+#define mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_0                             0xEC823C
+
+#define mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_1                             0xEC8240
+
+#define mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_2                             0xEC8244
+
+#define mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_3                             0xEC8248
+
+#define mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_4                             0xEC824C
+
+#define mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_0                             0xEC8250
+
+#define mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_1                             0xEC8254
+
+#define mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_2                             0xEC8258
+
+#define mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_3                             0xEC825C
+
+#define mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_4                             0xEC8260
+
+#define mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_0                             0xEC8264
+
+#define mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_1                             0xEC8268
+
+#define mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_2                             0xEC826C
+
+#define mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_3                             0xEC8270
+
+#define mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_4                             0xEC8274
+
+#define mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_0                             0xEC8278
+
+#define mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_1                             0xEC827C
+
+#define mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_2                             0xEC8280
+
+#define mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_3                             0xEC8284
+
+#define mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_4                             0xEC8288
+
+#define mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_0                             0xEC828C
+
+#define mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_1                             0xEC8290
+
+#define mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_2                             0xEC8294
+
+#define mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_3                             0xEC8298
+
+#define mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_4                             0xEC829C
+
+#define mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_0                             0xEC82A0
+
+#define mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_1                             0xEC82A4
+
+#define mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_2                             0xEC82A8
+
+#define mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_3                             0xEC82AC
+
+#define mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_4                             0xEC82B0
+
+#define mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_0                             0xEC82B4
+
+#define mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_1                             0xEC82B8
+
+#define mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_2                             0xEC82BC
+
+#define mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_3                             0xEC82C0
+
+#define mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_4                             0xEC82C4
+
+#define mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_0                             0xEC82C8
+
+#define mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_1                             0xEC82CC
+
+#define mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_2                             0xEC82D0
+
+#define mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_3                             0xEC82D4
+
+#define mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_4                             0xEC82D8
+
+#define mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0                       0xEC82E0
+
+#define mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1                       0xEC82E4
+
+#define mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2                       0xEC82E8
+
+#define mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3                       0xEC82EC
+
+#define mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4                       0xEC82F0
+
+#define mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_0                       0xEC82F4
+
+#define mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_1                       0xEC82F8
+
+#define mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_2                       0xEC82FC
+
+#define mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3                       0xEC8300
+
+#define mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_4                       0xEC8304
+
+#define mmTPC3_QM_CP_FENCE0_RDATA_0                                  0xEC8308
+
+#define mmTPC3_QM_CP_FENCE0_RDATA_1                                  0xEC830C
+
+#define mmTPC3_QM_CP_FENCE0_RDATA_2                                  0xEC8310
+
+#define mmTPC3_QM_CP_FENCE0_RDATA_3                                  0xEC8314
+
+#define mmTPC3_QM_CP_FENCE0_RDATA_4                                  0xEC8318
+
+#define mmTPC3_QM_CP_FENCE1_RDATA_0                                  0xEC831C
+
+#define mmTPC3_QM_CP_FENCE1_RDATA_1                                  0xEC8320
+
+#define mmTPC3_QM_CP_FENCE1_RDATA_2                                  0xEC8324
+
+#define mmTPC3_QM_CP_FENCE1_RDATA_3                                  0xEC8328
+
+#define mmTPC3_QM_CP_FENCE1_RDATA_4                                  0xEC832C
+
+#define mmTPC3_QM_CP_FENCE2_RDATA_0                                  0xEC8330
+
+#define mmTPC3_QM_CP_FENCE2_RDATA_1                                  0xEC8334
+
+#define mmTPC3_QM_CP_FENCE2_RDATA_2                                  0xEC8338
+
+#define mmTPC3_QM_CP_FENCE2_RDATA_3                                  0xEC833C
+
+#define mmTPC3_QM_CP_FENCE2_RDATA_4                                  0xEC8340
+
+#define mmTPC3_QM_CP_FENCE3_RDATA_0                                  0xEC8344
+
+#define mmTPC3_QM_CP_FENCE3_RDATA_1                                  0xEC8348
+
+#define mmTPC3_QM_CP_FENCE3_RDATA_2                                  0xEC834C
+
+#define mmTPC3_QM_CP_FENCE3_RDATA_3                                  0xEC8350
+
+#define mmTPC3_QM_CP_FENCE3_RDATA_4                                  0xEC8354
+
+#define mmTPC3_QM_CP_FENCE0_CNT_0                                    0xEC8358
+
+#define mmTPC3_QM_CP_FENCE0_CNT_1                                    0xEC835C
+
+#define mmTPC3_QM_CP_FENCE0_CNT_2                                    0xEC8360
+
+#define mmTPC3_QM_CP_FENCE0_CNT_3                                    0xEC8364
+
+#define mmTPC3_QM_CP_FENCE0_CNT_4                                    0xEC8368
+
+#define mmTPC3_QM_CP_FENCE1_CNT_0                                    0xEC836C
+
+#define mmTPC3_QM_CP_FENCE1_CNT_1                                    0xEC8370
+
+#define mmTPC3_QM_CP_FENCE1_CNT_2                                    0xEC8374
+
+#define mmTPC3_QM_CP_FENCE1_CNT_3                                    0xEC8378
+
+#define mmTPC3_QM_CP_FENCE1_CNT_4                                    0xEC837C
+
+#define mmTPC3_QM_CP_FENCE2_CNT_0                                    0xEC8380
+
+#define mmTPC3_QM_CP_FENCE2_CNT_1                                    0xEC8384
+
+#define mmTPC3_QM_CP_FENCE2_CNT_2                                    0xEC8388
+
+#define mmTPC3_QM_CP_FENCE2_CNT_3                                    0xEC838C
+
+#define mmTPC3_QM_CP_FENCE2_CNT_4                                    0xEC8390
+
+#define mmTPC3_QM_CP_FENCE3_CNT_0                                    0xEC8394
+
+#define mmTPC3_QM_CP_FENCE3_CNT_1                                    0xEC8398
+
+#define mmTPC3_QM_CP_FENCE3_CNT_2                                    0xEC839C
+
+#define mmTPC3_QM_CP_FENCE3_CNT_3                                    0xEC83A0
+
+#define mmTPC3_QM_CP_FENCE3_CNT_4                                    0xEC83A4
+
+#define mmTPC3_QM_CP_STS_0                                           0xEC83A8
+
+#define mmTPC3_QM_CP_STS_1                                           0xEC83AC
+
+#define mmTPC3_QM_CP_STS_2                                           0xEC83B0
+
+#define mmTPC3_QM_CP_STS_3                                           0xEC83B4
+
+#define mmTPC3_QM_CP_STS_4                                           0xEC83B8
+
+#define mmTPC3_QM_CP_CURRENT_INST_LO_0                               0xEC83BC
+
+#define mmTPC3_QM_CP_CURRENT_INST_LO_1                               0xEC83C0
+
+#define mmTPC3_QM_CP_CURRENT_INST_LO_2                               0xEC83C4
+
+#define mmTPC3_QM_CP_CURRENT_INST_LO_3                               0xEC83C8
+
+#define mmTPC3_QM_CP_CURRENT_INST_LO_4                               0xEC83CC
+
+#define mmTPC3_QM_CP_CURRENT_INST_HI_0                               0xEC83D0
+
+#define mmTPC3_QM_CP_CURRENT_INST_HI_1                               0xEC83D4
+
+#define mmTPC3_QM_CP_CURRENT_INST_HI_2                               0xEC83D8
+
+#define mmTPC3_QM_CP_CURRENT_INST_HI_3                               0xEC83DC
+
+#define mmTPC3_QM_CP_CURRENT_INST_HI_4                               0xEC83E0
+
+#define mmTPC3_QM_CP_BARRIER_CFG_0                                   0xEC83F4
+
+#define mmTPC3_QM_CP_BARRIER_CFG_1                                   0xEC83F8
+
+#define mmTPC3_QM_CP_BARRIER_CFG_2                                   0xEC83FC
+
+#define mmTPC3_QM_CP_BARRIER_CFG_3                                   0xEC8400
+
+#define mmTPC3_QM_CP_BARRIER_CFG_4                                   0xEC8404
+
+#define mmTPC3_QM_CP_DBG_0_0                                         0xEC8408
+
+#define mmTPC3_QM_CP_DBG_0_1                                         0xEC840C
+
+#define mmTPC3_QM_CP_DBG_0_2                                         0xEC8410
+
+#define mmTPC3_QM_CP_DBG_0_3                                         0xEC8414
+
+#define mmTPC3_QM_CP_DBG_0_4                                         0xEC8418
+
+#define mmTPC3_QM_CP_ARUSER_31_11_0                                  0xEC841C
+
+#define mmTPC3_QM_CP_ARUSER_31_11_1                                  0xEC8420
+
+#define mmTPC3_QM_CP_ARUSER_31_11_2                                  0xEC8424
+
+#define mmTPC3_QM_CP_ARUSER_31_11_3                                  0xEC8428
+
+#define mmTPC3_QM_CP_ARUSER_31_11_4                                  0xEC842C
+
+#define mmTPC3_QM_CP_AWUSER_31_11_0                                  0xEC8430
+
+#define mmTPC3_QM_CP_AWUSER_31_11_1                                  0xEC8434
+
+#define mmTPC3_QM_CP_AWUSER_31_11_2                                  0xEC8438
+
+#define mmTPC3_QM_CP_AWUSER_31_11_3                                  0xEC843C
+
+#define mmTPC3_QM_CP_AWUSER_31_11_4                                  0xEC8440
+
+#define mmTPC3_QM_ARB_CFG_0                                          0xEC8A00
+
+#define mmTPC3_QM_ARB_CHOISE_Q_PUSH                                  0xEC8A04
+
+#define mmTPC3_QM_ARB_WRR_WEIGHT_0                                   0xEC8A08
+
+#define mmTPC3_QM_ARB_WRR_WEIGHT_1                                   0xEC8A0C
+
+#define mmTPC3_QM_ARB_WRR_WEIGHT_2                                   0xEC8A10
+
+#define mmTPC3_QM_ARB_WRR_WEIGHT_3                                   0xEC8A14
+
+#define mmTPC3_QM_ARB_CFG_1                                          0xEC8A18
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_0                               0xEC8A20
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_1                               0xEC8A24
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_2                               0xEC8A28
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_3                               0xEC8A2C
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_4                               0xEC8A30
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_5                               0xEC8A34
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_6                               0xEC8A38
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_7                               0xEC8A3C
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_8                               0xEC8A40
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_9                               0xEC8A44
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_10                              0xEC8A48
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_11                              0xEC8A4C
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_12                              0xEC8A50
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_13                              0xEC8A54
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_14                              0xEC8A58
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_15                              0xEC8A5C
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_16                              0xEC8A60
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_17                              0xEC8A64
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_18                              0xEC8A68
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_19                              0xEC8A6C
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_20                              0xEC8A70
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_21                              0xEC8A74
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_22                              0xEC8A78
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_23                              0xEC8A7C
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_24                              0xEC8A80
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_25                              0xEC8A84
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_26                              0xEC8A88
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_27                              0xEC8A8C
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_28                              0xEC8A90
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_29                              0xEC8A94
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_30                              0xEC8A98
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_31                              0xEC8A9C
+
+#define mmTPC3_QM_ARB_MST_CRED_INC                                   0xEC8AA0
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_0                         0xEC8AA4
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_1                         0xEC8AA8
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_2                         0xEC8AAC
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_3                         0xEC8AB0
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_4                         0xEC8AB4
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_5                         0xEC8AB8
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_6                         0xEC8ABC
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_7                         0xEC8AC0
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_8                         0xEC8AC4
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_9                         0xEC8AC8
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_10                        0xEC8ACC
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_11                        0xEC8AD0
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_12                        0xEC8AD4
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_13                        0xEC8AD8
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_14                        0xEC8ADC
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_15                        0xEC8AE0
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_16                        0xEC8AE4
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_17                        0xEC8AE8
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_18                        0xEC8AEC
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_19                        0xEC8AF0
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_20                        0xEC8AF4
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_21                        0xEC8AF8
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_22                        0xEC8AFC
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_23                        0xEC8B00
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_24                        0xEC8B04
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_25                        0xEC8B08
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_26                        0xEC8B0C
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_27                        0xEC8B10
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_28                        0xEC8B14
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_29                        0xEC8B18
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_30                        0xEC8B1C
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_31                        0xEC8B20
+
+#define mmTPC3_QM_ARB_SLV_MASTER_INC_CRED_OFST                       0xEC8B28
+
+#define mmTPC3_QM_ARB_MST_SLAVE_EN                                   0xEC8B2C
+
+#define mmTPC3_QM_ARB_MST_QUIET_PER                                  0xEC8B34
+
+#define mmTPC3_QM_ARB_SLV_CHOISE_WDT                                 0xEC8B38
+
+#define mmTPC3_QM_ARB_SLV_ID                                         0xEC8B3C
+
+#define mmTPC3_QM_ARB_MSG_MAX_INFLIGHT                               0xEC8B44
+
+#define mmTPC3_QM_ARB_MSG_AWUSER_31_11                               0xEC8B48
+
+#define mmTPC3_QM_ARB_MSG_AWUSER_SEC_PROP                            0xEC8B4C
+
+#define mmTPC3_QM_ARB_MSG_AWUSER_NON_SEC_PROP                        0xEC8B50
+
+#define mmTPC3_QM_ARB_BASE_LO                                        0xEC8B54
+
+#define mmTPC3_QM_ARB_BASE_HI                                        0xEC8B58
+
+#define mmTPC3_QM_ARB_STATE_STS                                      0xEC8B80
+
+#define mmTPC3_QM_ARB_CHOISE_FULLNESS_STS                            0xEC8B84
+
+#define mmTPC3_QM_ARB_MSG_STS                                        0xEC8B88
+
+#define mmTPC3_QM_ARB_SLV_CHOISE_Q_HEAD                              0xEC8B8C
+
+#define mmTPC3_QM_ARB_ERR_CAUSE                                      0xEC8B9C
+
+#define mmTPC3_QM_ARB_ERR_MSG_EN                                     0xEC8BA0
+
+#define mmTPC3_QM_ARB_ERR_STS_DRP                                    0xEC8BA8
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_0                                 0xEC8BB0
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_1                                 0xEC8BB4
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_2                                 0xEC8BB8
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_3                                 0xEC8BBC
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_4                                 0xEC8BC0
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_5                                 0xEC8BC4
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_6                                 0xEC8BC8
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_7                                 0xEC8BCC
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_8                                 0xEC8BD0
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_9                                 0xEC8BD4
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_10                                0xEC8BD8
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_11                                0xEC8BDC
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_12                                0xEC8BE0
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_13                                0xEC8BE4
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_14                                0xEC8BE8
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_15                                0xEC8BEC
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_16                                0xEC8BF0
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_17                                0xEC8BF4
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_18                                0xEC8BF8
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_19                                0xEC8BFC
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_20                                0xEC8C00
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_21                                0xEC8C04
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_22                                0xEC8C08
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_23                                0xEC8C0C
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_24                                0xEC8C10
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_25                                0xEC8C14
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_26                                0xEC8C18
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_27                                0xEC8C1C
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_28                                0xEC8C20
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_29                                0xEC8C24
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_30                                0xEC8C28
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_31                                0xEC8C2C
+
+#define mmTPC3_QM_CGM_CFG                                            0xEC8C70
+
+#define mmTPC3_QM_CGM_STS                                            0xEC8C74
+
+#define mmTPC3_QM_CGM_CFG1                                           0xEC8C78
+
+#define mmTPC3_QM_LOCAL_RANGE_BASE                                   0xEC8C80
+
+#define mmTPC3_QM_LOCAL_RANGE_SIZE                                   0xEC8C84
+
+#define mmTPC3_QM_CSMR_STRICT_PRIO_CFG                               0xEC8C90
+
+#define mmTPC3_QM_HBW_RD_RATE_LIM_CFG_1                              0xEC8C94
+
+#define mmTPC3_QM_LBW_WR_RATE_LIM_CFG_0                              0xEC8C98
+
+#define mmTPC3_QM_LBW_WR_RATE_LIM_CFG_1                              0xEC8C9C
+
+#define mmTPC3_QM_HBW_RD_RATE_LIM_CFG_0                              0xEC8CA0
+
+#define mmTPC3_QM_GLBL_AXCACHE                                       0xEC8CA4
+
+#define mmTPC3_QM_IND_GW_APB_CFG                                     0xEC8CB0
+
+#define mmTPC3_QM_IND_GW_APB_WDATA                                   0xEC8CB4
+
+#define mmTPC3_QM_IND_GW_APB_RDATA                                   0xEC8CB8
+
+#define mmTPC3_QM_IND_GW_APB_STATUS                                  0xEC8CBC
+
+#define mmTPC3_QM_GLBL_ERR_ADDR_LO                                   0xEC8CD0
+
+#define mmTPC3_QM_GLBL_ERR_ADDR_HI                                   0xEC8CD4
+
+#define mmTPC3_QM_GLBL_ERR_WDATA                                     0xEC8CD8
+
+#define mmTPC3_QM_GLBL_MEM_INIT_BUSY                                 0xEC8D00
+
+#endif /* ASIC_REG_TPC3_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc4_cfg_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc4_cfg_regs.h
new file mode 100644
index 000000000000..7a9447f39a74
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc4_cfg_regs.h
@@ -0,0 +1,1226 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_TPC4_CFG_REGS_H_
+#define ASIC_REG_TPC4_CFG_REGS_H_
+
+/*
+ *****************************************
+ *   TPC4_CFG (Prototype: TPC)
+ *****************************************
+ */
+
+#define mmTPC4_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW                     0xF06400
+
+#define mmTPC4_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH                    0xF06404
+
+#define mmTPC4_CFG_KERNEL_TENSOR_0_PADDING_VALUE                     0xF06408
+
+#define mmTPC4_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG                     0xF0640C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_0_SIZE                        0xF06410
+
+#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE                      0xF06414
+
+#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_1_SIZE                        0xF06418
+
+#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE                      0xF0641C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_2_SIZE                        0xF06420
+
+#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE                      0xF06424
+
+#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_3_SIZE                        0xF06428
+
+#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE                      0xF0642C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_4_SIZE                        0xF06430
+
+#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE                      0xF06434
+
+#define mmTPC4_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW                     0xF06438
+
+#define mmTPC4_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH                    0xF0643C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_1_PADDING_VALUE                     0xF06440
+
+#define mmTPC4_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG                     0xF06444
+
+#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_0_SIZE                        0xF06448
+
+#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE                      0xF0644C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_1_SIZE                        0xF06450
+
+#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE                      0xF06454
+
+#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_2_SIZE                        0xF06458
+
+#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE                      0xF0645C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_3_SIZE                        0xF06460
+
+#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE                      0xF06464
+
+#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_4_SIZE                        0xF06468
+
+#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE                      0xF0646C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW                     0xF06470
+
+#define mmTPC4_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH                    0xF06474
+
+#define mmTPC4_CFG_KERNEL_TENSOR_2_PADDING_VALUE                     0xF06478
+
+#define mmTPC4_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG                     0xF0647C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_0_SIZE                        0xF06480
+
+#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE                      0xF06484
+
+#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_1_SIZE                        0xF06488
+
+#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE                      0xF0648C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_2_SIZE                        0xF06490
+
+#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE                      0xF06494
+
+#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_3_SIZE                        0xF06498
+
+#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE                      0xF0649C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_4_SIZE                        0xF064A0
+
+#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE                      0xF064A4
+
+#define mmTPC4_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW                     0xF064A8
+
+#define mmTPC4_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH                    0xF064AC
+
+#define mmTPC4_CFG_KERNEL_TENSOR_3_PADDING_VALUE                     0xF064B0
+
+#define mmTPC4_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG                     0xF064B4
+
+#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_0_SIZE                        0xF064B8
+
+#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE                      0xF064BC
+
+#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_1_SIZE                        0xF064C0
+
+#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE                      0xF064C4
+
+#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_2_SIZE                        0xF064C8
+
+#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE                      0xF064CC
+
+#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_3_SIZE                        0xF064D0
+
+#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE                      0xF064D4
+
+#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_4_SIZE                        0xF064D8
+
+#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE                      0xF064DC
+
+#define mmTPC4_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW                     0xF064E0
+
+#define mmTPC4_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH                    0xF064E4
+
+#define mmTPC4_CFG_KERNEL_TENSOR_4_PADDING_VALUE                     0xF064E8
+
+#define mmTPC4_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG                     0xF064EC
+
+#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_0_SIZE                        0xF064F0
+
+#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE                      0xF064F4
+
+#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_1_SIZE                        0xF064F8
+
+#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE                      0xF064FC
+
+#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_2_SIZE                        0xF06500
+
+#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE                      0xF06504
+
+#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_3_SIZE                        0xF06508
+
+#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE                      0xF0650C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_4_SIZE                        0xF06510
+
+#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE                      0xF06514
+
+#define mmTPC4_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW                     0xF06518
+
+#define mmTPC4_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH                    0xF0651C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_5_PADDING_VALUE                     0xF06520
+
+#define mmTPC4_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG                     0xF06524
+
+#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_0_SIZE                        0xF06528
+
+#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE                      0xF0652C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_1_SIZE                        0xF06530
+
+#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE                      0xF06534
+
+#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_2_SIZE                        0xF06538
+
+#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE                      0xF0653C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_3_SIZE                        0xF06540
+
+#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE                      0xF06544
+
+#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_4_SIZE                        0xF06548
+
+#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE                      0xF0654C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW                     0xF06550
+
+#define mmTPC4_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH                    0xF06554
+
+#define mmTPC4_CFG_KERNEL_TENSOR_6_PADDING_VALUE                     0xF06558
+
+#define mmTPC4_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG                     0xF0655C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_0_SIZE                        0xF06560
+
+#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE                      0xF06564
+
+#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_1_SIZE                        0xF06568
+
+#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE                      0xF0656C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_2_SIZE                        0xF06570
+
+#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE                      0xF06574
+
+#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_3_SIZE                        0xF06578
+
+#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE                      0xF0657C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_4_SIZE                        0xF06580
+
+#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE                      0xF06584
+
+#define mmTPC4_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW                     0xF06588
+
+#define mmTPC4_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH                    0xF0658C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_7_PADDING_VALUE                     0xF06590
+
+#define mmTPC4_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG                     0xF06594
+
+#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_0_SIZE                        0xF06598
+
+#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE                      0xF0659C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_1_SIZE                        0xF065A0
+
+#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE                      0xF065A4
+
+#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_2_SIZE                        0xF065A8
+
+#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE                      0xF065AC
+
+#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_3_SIZE                        0xF065B0
+
+#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE                      0xF065B4
+
+#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_4_SIZE                        0xF065B8
+
+#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE                      0xF065BC
+
+#define mmTPC4_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW                     0xF065C0
+
+#define mmTPC4_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH                    0xF065C4
+
+#define mmTPC4_CFG_KERNEL_TENSOR_8_PADDING_VALUE                     0xF065C8
+
+#define mmTPC4_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG                     0xF065CC
+
+#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_0_SIZE                        0xF065D0
+
+#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE                      0xF065D4
+
+#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_1_SIZE                        0xF065D8
+
+#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE                      0xF065DC
+
+#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_2_SIZE                        0xF065E0
+
+#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE                      0xF065E4
+
+#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_3_SIZE                        0xF065E8
+
+#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE                      0xF065EC
+
+#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_4_SIZE                        0xF065F0
+
+#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE                      0xF065F4
+
+#define mmTPC4_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW                     0xF065F8
+
+#define mmTPC4_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH                    0xF065FC
+
+#define mmTPC4_CFG_KERNEL_TENSOR_9_PADDING_VALUE                     0xF06600
+
+#define mmTPC4_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG                     0xF06604
+
+#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_0_SIZE                        0xF06608
+
+#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE                      0xF0660C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_1_SIZE                        0xF06610
+
+#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE                      0xF06614
+
+#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_2_SIZE                        0xF06618
+
+#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE                      0xF0661C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_3_SIZE                        0xF06620
+
+#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE                      0xF06624
+
+#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_4_SIZE                        0xF06628
+
+#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE                      0xF0662C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW                    0xF06630
+
+#define mmTPC4_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH                   0xF06634
+
+#define mmTPC4_CFG_KERNEL_TENSOR_10_PADDING_VALUE                    0xF06638
+
+#define mmTPC4_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG                    0xF0663C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_0_SIZE                       0xF06640
+
+#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE                     0xF06644
+
+#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_1_SIZE                       0xF06648
+
+#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE                     0xF0664C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_2_SIZE                       0xF06650
+
+#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE                     0xF06654
+
+#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_3_SIZE                       0xF06658
+
+#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE                     0xF0665C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_4_SIZE                       0xF06660
+
+#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE                     0xF06664
+
+#define mmTPC4_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW                    0xF06668
+
+#define mmTPC4_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH                   0xF0666C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_11_PADDING_VALUE                    0xF06670
+
+#define mmTPC4_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG                    0xF06674
+
+#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_0_SIZE                       0xF06678
+
+#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE                     0xF0667C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_1_SIZE                       0xF06680
+
+#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE                     0xF06684
+
+#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_2_SIZE                       0xF06688
+
+#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE                     0xF0668C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_3_SIZE                       0xF06690
+
+#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE                     0xF06694
+
+#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_4_SIZE                       0xF06698
+
+#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE                     0xF0669C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW                    0xF066A0
+
+#define mmTPC4_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH                   0xF066A4
+
+#define mmTPC4_CFG_KERNEL_TENSOR_12_PADDING_VALUE                    0xF066A8
+
+#define mmTPC4_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG                    0xF066AC
+
+#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_0_SIZE                       0xF066B0
+
+#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE                     0xF066B4
+
+#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_1_SIZE                       0xF066B8
+
+#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE                     0xF066BC
+
+#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_2_SIZE                       0xF066C0
+
+#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE                     0xF066C4
+
+#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_3_SIZE                       0xF066C8
+
+#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE                     0xF066CC
+
+#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_4_SIZE                       0xF066D0
+
+#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE                     0xF066D4
+
+#define mmTPC4_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW                    0xF066D8
+
+#define mmTPC4_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH                   0xF066DC
+
+#define mmTPC4_CFG_KERNEL_TENSOR_13_PADDING_VALUE                    0xF066E0
+
+#define mmTPC4_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG                    0xF066E4
+
+#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_0_SIZE                       0xF066E8
+
+#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE                     0xF066EC
+
+#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_1_SIZE                       0xF066F0
+
+#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE                     0xF066F4
+
+#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_2_SIZE                       0xF066F8
+
+#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE                     0xF066FC
+
+#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_3_SIZE                       0xF06700
+
+#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE                     0xF06704
+
+#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_4_SIZE                       0xF06708
+
+#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE                     0xF0670C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW                    0xF06710
+
+#define mmTPC4_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH                   0xF06714
+
+#define mmTPC4_CFG_KERNEL_TENSOR_14_PADDING_VALUE                    0xF06718
+
+#define mmTPC4_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG                    0xF0671C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_0_SIZE                       0xF06720
+
+#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE                     0xF06724
+
+#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_1_SIZE                       0xF06728
+
+#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE                     0xF0672C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_2_SIZE                       0xF06730
+
+#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE                     0xF06734
+
+#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_3_SIZE                       0xF06738
+
+#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE                     0xF0673C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_4_SIZE                       0xF06740
+
+#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE                     0xF06744
+
+#define mmTPC4_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW                    0xF06748
+
+#define mmTPC4_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH                   0xF0674C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_15_PADDING_VALUE                    0xF06750
+
+#define mmTPC4_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG                    0xF06754
+
+#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_0_SIZE                       0xF06758
+
+#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE                     0xF0675C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_1_SIZE                       0xF06760
+
+#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE                     0xF06764
+
+#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_2_SIZE                       0xF06768
+
+#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE                     0xF0676C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_3_SIZE                       0xF06770
+
+#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE                     0xF06774
+
+#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_4_SIZE                       0xF06778
+
+#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE                     0xF0677C
+
+#define mmTPC4_CFG_KERNEL_SYNC_OBJECT_MESSAGE                        0xF06780
+
+#define mmTPC4_CFG_KERNEL_SYNC_OBJECT_ADDR                           0xF06784
+
+#define mmTPC4_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW                    0xF06788
+
+#define mmTPC4_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH                   0xF0678C
+
+#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_0                             0xF06790
+
+#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_0                             0xF06794
+
+#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_1                             0xF06798
+
+#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_1                             0xF0679C
+
+#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_2                             0xF067A0
+
+#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_2                             0xF067A4
+
+#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_3                             0xF067A8
+
+#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_3                             0xF067AC
+
+#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_4                             0xF067B0
+
+#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_4                             0xF067B4
+
+#define mmTPC4_CFG_KERNEL_KERNEL_CONFIG                              0xF067B8
+
+#define mmTPC4_CFG_KERNEL_KERNEL_ID                                  0xF067BC
+
+#define mmTPC4_CFG_KERNEL_SRF_0                                      0xF067C0
+
+#define mmTPC4_CFG_KERNEL_SRF_1                                      0xF067C4
+
+#define mmTPC4_CFG_KERNEL_SRF_2                                      0xF067C8
+
+#define mmTPC4_CFG_KERNEL_SRF_3                                      0xF067CC
+
+#define mmTPC4_CFG_KERNEL_SRF_4                                      0xF067D0
+
+#define mmTPC4_CFG_KERNEL_SRF_5                                      0xF067D4
+
+#define mmTPC4_CFG_KERNEL_SRF_6                                      0xF067D8
+
+#define mmTPC4_CFG_KERNEL_SRF_7                                      0xF067DC
+
+#define mmTPC4_CFG_KERNEL_SRF_8                                      0xF067E0
+
+#define mmTPC4_CFG_KERNEL_SRF_9                                      0xF067E4
+
+#define mmTPC4_CFG_KERNEL_SRF_10                                     0xF067E8
+
+#define mmTPC4_CFG_KERNEL_SRF_11                                     0xF067EC
+
+#define mmTPC4_CFG_KERNEL_SRF_12                                     0xF067F0
+
+#define mmTPC4_CFG_KERNEL_SRF_13                                     0xF067F4
+
+#define mmTPC4_CFG_KERNEL_SRF_14                                     0xF067F8
+
+#define mmTPC4_CFG_KERNEL_SRF_15                                     0xF067FC
+
+#define mmTPC4_CFG_KERNEL_SRF_16                                     0xF06800
+
+#define mmTPC4_CFG_KERNEL_SRF_17                                     0xF06804
+
+#define mmTPC4_CFG_KERNEL_SRF_18                                     0xF06808
+
+#define mmTPC4_CFG_KERNEL_SRF_19                                     0xF0680C
+
+#define mmTPC4_CFG_KERNEL_SRF_20                                     0xF06810
+
+#define mmTPC4_CFG_KERNEL_SRF_21                                     0xF06814
+
+#define mmTPC4_CFG_KERNEL_SRF_22                                     0xF06818
+
+#define mmTPC4_CFG_KERNEL_SRF_23                                     0xF0681C
+
+#define mmTPC4_CFG_KERNEL_SRF_24                                     0xF06820
+
+#define mmTPC4_CFG_KERNEL_SRF_25                                     0xF06824
+
+#define mmTPC4_CFG_KERNEL_SRF_26                                     0xF06828
+
+#define mmTPC4_CFG_KERNEL_SRF_27                                     0xF0682C
+
+#define mmTPC4_CFG_KERNEL_SRF_28                                     0xF06830
+
+#define mmTPC4_CFG_KERNEL_SRF_29                                     0xF06834
+
+#define mmTPC4_CFG_KERNEL_SRF_30                                     0xF06838
+
+#define mmTPC4_CFG_KERNEL_SRF_31                                     0xF0683C
+
+#define mmTPC4_CFG_ROUND_CSR                                         0xF068FC
+
+#define mmTPC4_CFG_PROT                                              0xF06900
+
+#define mmTPC4_CFG_SEMAPHORE                                         0xF06908
+
+#define mmTPC4_CFG_VFLAGS                                            0xF0690C
+
+#define mmTPC4_CFG_SFLAGS                                            0xF06910
+
+#define mmTPC4_CFG_LFSR_POLYNOM                                      0xF06918
+
+#define mmTPC4_CFG_STATUS                                            0xF0691C
+
+#define mmTPC4_CFG_CFG_BASE_ADDRESS_HIGH                             0xF06920
+
+#define mmTPC4_CFG_CFG_SUBTRACT_VALUE                                0xF06924
+
+#define mmTPC4_CFG_SM_BASE_ADDRESS_HIGH                              0xF0692C
+
+#define mmTPC4_CFG_TPC_CMD                                           0xF06930
+
+#define mmTPC4_CFG_TPC_EXECUTE                                       0xF06938
+
+#define mmTPC4_CFG_TPC_STALL                                         0xF0693C
+
+#define mmTPC4_CFG_ICACHE_BASE_ADDERESS_LOW                          0xF06940
+
+#define mmTPC4_CFG_ICACHE_BASE_ADDERESS_HIGH                         0xF06944
+
+#define mmTPC4_CFG_RD_RATE_LIMIT                                     0xF06948
+
+#define mmTPC4_CFG_WR_RATE_LIMIT                                     0xF06950
+
+#define mmTPC4_CFG_MSS_CONFIG                                        0xF06954
+
+#define mmTPC4_CFG_TPC_INTR_CAUSE                                    0xF06958
+
+#define mmTPC4_CFG_TPC_INTR_MASK                                     0xF0695C
+
+#define mmTPC4_CFG_WQ_CREDITS                                        0xF06960
+
+#define mmTPC4_CFG_ARUSER_LO                                         0xF06964
+
+#define mmTPC4_CFG_ARUSER_HI                                         0xF06968
+
+#define mmTPC4_CFG_AWUSER_LO                                         0xF0696C
+
+#define mmTPC4_CFG_AWUSER_HI                                         0xF06970
+
+#define mmTPC4_CFG_OPCODE_EXEC                                       0xF06974
+
+#define mmTPC4_CFG_LUT_FUNC32_BASE_ADDR_LO                           0xF06978
+
+#define mmTPC4_CFG_LUT_FUNC32_BASE_ADDR_HI                           0xF0697C
+
+#define mmTPC4_CFG_LUT_FUNC64_BASE_ADDR_LO                           0xF06980
+
+#define mmTPC4_CFG_LUT_FUNC64_BASE_ADDR_HI                           0xF06984
+
+#define mmTPC4_CFG_LUT_FUNC128_BASE_ADDR_LO                          0xF06988
+
+#define mmTPC4_CFG_LUT_FUNC128_BASE_ADDR_HI                          0xF0698C
+
+#define mmTPC4_CFG_LUT_FUNC256_BASE_ADDR_LO                          0xF06990
+
+#define mmTPC4_CFG_LUT_FUNC256_BASE_ADDR_HI                          0xF06994
+
+#define mmTPC4_CFG_TSB_CFG_MAX_SIZE                                  0xF06998
+
+#define mmTPC4_CFG_TSB_CFG                                           0xF0699C
+
+#define mmTPC4_CFG_DBGMEM_ADD                                        0xF069A0
+
+#define mmTPC4_CFG_DBGMEM_DATA_WR                                    0xF069A4
+
+#define mmTPC4_CFG_DBGMEM_DATA_RD                                    0xF069A8
+
+#define mmTPC4_CFG_DBGMEM_CTRL                                       0xF069AC
+
+#define mmTPC4_CFG_DBGMEM_RC                                         0xF069B0
+
+#define mmTPC4_CFG_TSB_INFLIGHT_CNTR                                 0xF069B4
+
+#define mmTPC4_CFG_WQ_INFLIGHT_CNTR                                  0xF069B8
+
+#define mmTPC4_CFG_WQ_LBW_TOTAL_CNTR                                 0xF069BC
+
+#define mmTPC4_CFG_WQ_HBW_TOTAL_CNTR                                 0xF069C0
+
+#define mmTPC4_CFG_IRQ_OCCOUPY_CNTR                                  0xF069C4
+
+#define mmTPC4_CFG_FUNC_MBIST_CNTRL                                  0xF069D0
+
+#define mmTPC4_CFG_FUNC_MBIST_PAT                                    0xF069D4
+
+#define mmTPC4_CFG_FUNC_MBIST_MEM_0                                  0xF069D8
+
+#define mmTPC4_CFG_FUNC_MBIST_MEM_1                                  0xF069DC
+
+#define mmTPC4_CFG_FUNC_MBIST_MEM_2                                  0xF069E0
+
+#define mmTPC4_CFG_FUNC_MBIST_MEM_3                                  0xF069E4
+
+#define mmTPC4_CFG_FUNC_MBIST_MEM_4                                  0xF069E8
+
+#define mmTPC4_CFG_FUNC_MBIST_MEM_5                                  0xF069EC
+
+#define mmTPC4_CFG_FUNC_MBIST_MEM_6                                  0xF069F0
+
+#define mmTPC4_CFG_FUNC_MBIST_MEM_7                                  0xF069F4
+
+#define mmTPC4_CFG_FUNC_MBIST_MEM_8                                  0xF069F8
+
+#define mmTPC4_CFG_FUNC_MBIST_MEM_9                                  0xF069FC
+
+#define mmTPC4_CFG_QM_TENSOR_0_BASE_ADDR_LOW                         0xF06A00
+
+#define mmTPC4_CFG_QM_TENSOR_0_BASE_ADDR_HIGH                        0xF06A04
+
+#define mmTPC4_CFG_QM_TENSOR_0_PADDING_VALUE                         0xF06A08
+
+#define mmTPC4_CFG_QM_TENSOR_0_TENSOR_CONFIG                         0xF06A0C
+
+#define mmTPC4_CFG_QM_TENSOR_0_DIM_0_SIZE                            0xF06A10
+
+#define mmTPC4_CFG_QM_TENSOR_0_DIM_0_STRIDE                          0xF06A14
+
+#define mmTPC4_CFG_QM_TENSOR_0_DIM_1_SIZE                            0xF06A18
+
+#define mmTPC4_CFG_QM_TENSOR_0_DIM_1_STRIDE                          0xF06A1C
+
+#define mmTPC4_CFG_QM_TENSOR_0_DIM_2_SIZE                            0xF06A20
+
+#define mmTPC4_CFG_QM_TENSOR_0_DIM_2_STRIDE                          0xF06A24
+
+#define mmTPC4_CFG_QM_TENSOR_0_DIM_3_SIZE                            0xF06A28
+
+#define mmTPC4_CFG_QM_TENSOR_0_DIM_3_STRIDE                          0xF06A2C
+
+#define mmTPC4_CFG_QM_TENSOR_0_DIM_4_SIZE                            0xF06A30
+
+#define mmTPC4_CFG_QM_TENSOR_0_DIM_4_STRIDE                          0xF06A34
+
+#define mmTPC4_CFG_QM_TENSOR_1_BASE_ADDR_LOW                         0xF06A38
+
+#define mmTPC4_CFG_QM_TENSOR_1_BASE_ADDR_HIGH                        0xF06A3C
+
+#define mmTPC4_CFG_QM_TENSOR_1_PADDING_VALUE                         0xF06A40
+
+#define mmTPC4_CFG_QM_TENSOR_1_TENSOR_CONFIG                         0xF06A44
+
+#define mmTPC4_CFG_QM_TENSOR_1_DIM_0_SIZE                            0xF06A48
+
+#define mmTPC4_CFG_QM_TENSOR_1_DIM_0_STRIDE                          0xF06A4C
+
+#define mmTPC4_CFG_QM_TENSOR_1_DIM_1_SIZE                            0xF06A50
+
+#define mmTPC4_CFG_QM_TENSOR_1_DIM_1_STRIDE                          0xF06A54
+
+#define mmTPC4_CFG_QM_TENSOR_1_DIM_2_SIZE                            0xF06A58
+
+#define mmTPC4_CFG_QM_TENSOR_1_DIM_2_STRIDE                          0xF06A5C
+
+#define mmTPC4_CFG_QM_TENSOR_1_DIM_3_SIZE                            0xF06A60
+
+#define mmTPC4_CFG_QM_TENSOR_1_DIM_3_STRIDE                          0xF06A64
+
+#define mmTPC4_CFG_QM_TENSOR_1_DIM_4_SIZE                            0xF06A68
+
+#define mmTPC4_CFG_QM_TENSOR_1_DIM_4_STRIDE                          0xF06A6C
+
+#define mmTPC4_CFG_QM_TENSOR_2_BASE_ADDR_LOW                         0xF06A70
+
+#define mmTPC4_CFG_QM_TENSOR_2_BASE_ADDR_HIGH                        0xF06A74
+
+#define mmTPC4_CFG_QM_TENSOR_2_PADDING_VALUE                         0xF06A78
+
+#define mmTPC4_CFG_QM_TENSOR_2_TENSOR_CONFIG                         0xF06A7C
+
+#define mmTPC4_CFG_QM_TENSOR_2_DIM_0_SIZE                            0xF06A80
+
+#define mmTPC4_CFG_QM_TENSOR_2_DIM_0_STRIDE                          0xF06A84
+
+#define mmTPC4_CFG_QM_TENSOR_2_DIM_1_SIZE                            0xF06A88
+
+#define mmTPC4_CFG_QM_TENSOR_2_DIM_1_STRIDE                          0xF06A8C
+
+#define mmTPC4_CFG_QM_TENSOR_2_DIM_2_SIZE                            0xF06A90
+
+#define mmTPC4_CFG_QM_TENSOR_2_DIM_2_STRIDE                          0xF06A94
+
+#define mmTPC4_CFG_QM_TENSOR_2_DIM_3_SIZE                            0xF06A98
+
+#define mmTPC4_CFG_QM_TENSOR_2_DIM_3_STRIDE                          0xF06A9C
+
+#define mmTPC4_CFG_QM_TENSOR_2_DIM_4_SIZE                            0xF06AA0
+
+#define mmTPC4_CFG_QM_TENSOR_2_DIM_4_STRIDE                          0xF06AA4
+
+#define mmTPC4_CFG_QM_TENSOR_3_BASE_ADDR_LOW                         0xF06AA8
+
+#define mmTPC4_CFG_QM_TENSOR_3_BASE_ADDR_HIGH                        0xF06AAC
+
+#define mmTPC4_CFG_QM_TENSOR_3_PADDING_VALUE                         0xF06AB0
+
+#define mmTPC4_CFG_QM_TENSOR_3_TENSOR_CONFIG                         0xF06AB4
+
+#define mmTPC4_CFG_QM_TENSOR_3_DIM_0_SIZE                            0xF06AB8
+
+#define mmTPC4_CFG_QM_TENSOR_3_DIM_0_STRIDE                          0xF06ABC
+
+#define mmTPC4_CFG_QM_TENSOR_3_DIM_1_SIZE                            0xF06AC0
+
+#define mmTPC4_CFG_QM_TENSOR_3_DIM_1_STRIDE                          0xF06AC4
+
+#define mmTPC4_CFG_QM_TENSOR_3_DIM_2_SIZE                            0xF06AC8
+
+#define mmTPC4_CFG_QM_TENSOR_3_DIM_2_STRIDE                          0xF06ACC
+
+#define mmTPC4_CFG_QM_TENSOR_3_DIM_3_SIZE                            0xF06AD0
+
+#define mmTPC4_CFG_QM_TENSOR_3_DIM_3_STRIDE                          0xF06AD4
+
+#define mmTPC4_CFG_QM_TENSOR_3_DIM_4_SIZE                            0xF06AD8
+
+#define mmTPC4_CFG_QM_TENSOR_3_DIM_4_STRIDE                          0xF06ADC
+
+#define mmTPC4_CFG_QM_TENSOR_4_BASE_ADDR_LOW                         0xF06AE0
+
+#define mmTPC4_CFG_QM_TENSOR_4_BASE_ADDR_HIGH                        0xF06AE4
+
+#define mmTPC4_CFG_QM_TENSOR_4_PADDING_VALUE                         0xF06AE8
+
+#define mmTPC4_CFG_QM_TENSOR_4_TENSOR_CONFIG                         0xF06AEC
+
+#define mmTPC4_CFG_QM_TENSOR_4_DIM_0_SIZE                            0xF06AF0
+
+#define mmTPC4_CFG_QM_TENSOR_4_DIM_0_STRIDE                          0xF06AF4
+
+#define mmTPC4_CFG_QM_TENSOR_4_DIM_1_SIZE                            0xF06AF8
+
+#define mmTPC4_CFG_QM_TENSOR_4_DIM_1_STRIDE                          0xF06AFC
+
+#define mmTPC4_CFG_QM_TENSOR_4_DIM_2_SIZE                            0xF06B00
+
+#define mmTPC4_CFG_QM_TENSOR_4_DIM_2_STRIDE                          0xF06B04
+
+#define mmTPC4_CFG_QM_TENSOR_4_DIM_3_SIZE                            0xF06B08
+
+#define mmTPC4_CFG_QM_TENSOR_4_DIM_3_STRIDE                          0xF06B0C
+
+#define mmTPC4_CFG_QM_TENSOR_4_DIM_4_SIZE                            0xF06B10
+
+#define mmTPC4_CFG_QM_TENSOR_4_DIM_4_STRIDE                          0xF06B14
+
+#define mmTPC4_CFG_QM_TENSOR_5_BASE_ADDR_LOW                         0xF06B18
+
+#define mmTPC4_CFG_QM_TENSOR_5_BASE_ADDR_HIGH                        0xF06B1C
+
+#define mmTPC4_CFG_QM_TENSOR_5_PADDING_VALUE                         0xF06B20
+
+#define mmTPC4_CFG_QM_TENSOR_5_TENSOR_CONFIG                         0xF06B24
+
+#define mmTPC4_CFG_QM_TENSOR_5_DIM_0_SIZE                            0xF06B28
+
+#define mmTPC4_CFG_QM_TENSOR_5_DIM_0_STRIDE                          0xF06B2C
+
+#define mmTPC4_CFG_QM_TENSOR_5_DIM_1_SIZE                            0xF06B30
+
+#define mmTPC4_CFG_QM_TENSOR_5_DIM_1_STRIDE                          0xF06B34
+
+#define mmTPC4_CFG_QM_TENSOR_5_DIM_2_SIZE                            0xF06B38
+
+#define mmTPC4_CFG_QM_TENSOR_5_DIM_2_STRIDE                          0xF06B3C
+
+#define mmTPC4_CFG_QM_TENSOR_5_DIM_3_SIZE                            0xF06B40
+
+#define mmTPC4_CFG_QM_TENSOR_5_DIM_3_STRIDE                          0xF06B44
+
+#define mmTPC4_CFG_QM_TENSOR_5_DIM_4_SIZE                            0xF06B48
+
+#define mmTPC4_CFG_QM_TENSOR_5_DIM_4_STRIDE                          0xF06B4C
+
+#define mmTPC4_CFG_QM_TENSOR_6_BASE_ADDR_LOW                         0xF06B50
+
+#define mmTPC4_CFG_QM_TENSOR_6_BASE_ADDR_HIGH                        0xF06B54
+
+#define mmTPC4_CFG_QM_TENSOR_6_PADDING_VALUE                         0xF06B58
+
+#define mmTPC4_CFG_QM_TENSOR_6_TENSOR_CONFIG                         0xF06B5C
+
+#define mmTPC4_CFG_QM_TENSOR_6_DIM_0_SIZE                            0xF06B60
+
+#define mmTPC4_CFG_QM_TENSOR_6_DIM_0_STRIDE                          0xF06B64
+
+#define mmTPC4_CFG_QM_TENSOR_6_DIM_1_SIZE                            0xF06B68
+
+#define mmTPC4_CFG_QM_TENSOR_6_DIM_1_STRIDE                          0xF06B6C
+
+#define mmTPC4_CFG_QM_TENSOR_6_DIM_2_SIZE                            0xF06B70
+
+#define mmTPC4_CFG_QM_TENSOR_6_DIM_2_STRIDE                          0xF06B74
+
+#define mmTPC4_CFG_QM_TENSOR_6_DIM_3_SIZE                            0xF06B78
+
+#define mmTPC4_CFG_QM_TENSOR_6_DIM_3_STRIDE                          0xF06B7C
+
+#define mmTPC4_CFG_QM_TENSOR_6_DIM_4_SIZE                            0xF06B80
+
+#define mmTPC4_CFG_QM_TENSOR_6_DIM_4_STRIDE                          0xF06B84
+
+#define mmTPC4_CFG_QM_TENSOR_7_BASE_ADDR_LOW                         0xF06B88
+
+#define mmTPC4_CFG_QM_TENSOR_7_BASE_ADDR_HIGH                        0xF06B8C
+
+#define mmTPC4_CFG_QM_TENSOR_7_PADDING_VALUE                         0xF06B90
+
+#define mmTPC4_CFG_QM_TENSOR_7_TENSOR_CONFIG                         0xF06B94
+
+#define mmTPC4_CFG_QM_TENSOR_7_DIM_0_SIZE                            0xF06B98
+
+#define mmTPC4_CFG_QM_TENSOR_7_DIM_0_STRIDE                          0xF06B9C
+
+#define mmTPC4_CFG_QM_TENSOR_7_DIM_1_SIZE                            0xF06BA0
+
+#define mmTPC4_CFG_QM_TENSOR_7_DIM_1_STRIDE                          0xF06BA4
+
+#define mmTPC4_CFG_QM_TENSOR_7_DIM_2_SIZE                            0xF06BA8
+
+#define mmTPC4_CFG_QM_TENSOR_7_DIM_2_STRIDE                          0xF06BAC
+
+#define mmTPC4_CFG_QM_TENSOR_7_DIM_3_SIZE                            0xF06BB0
+
+#define mmTPC4_CFG_QM_TENSOR_7_DIM_3_STRIDE                          0xF06BB4
+
+#define mmTPC4_CFG_QM_TENSOR_7_DIM_4_SIZE                            0xF06BB8
+
+#define mmTPC4_CFG_QM_TENSOR_7_DIM_4_STRIDE                          0xF06BBC
+
+#define mmTPC4_CFG_QM_TENSOR_8_BASE_ADDR_LOW                         0xF06BC0
+
+#define mmTPC4_CFG_QM_TENSOR_8_BASE_ADDR_HIGH                        0xF06BC4
+
+#define mmTPC4_CFG_QM_TENSOR_8_PADDING_VALUE                         0xF06BC8
+
+#define mmTPC4_CFG_QM_TENSOR_8_TENSOR_CONFIG                         0xF06BCC
+
+#define mmTPC4_CFG_QM_TENSOR_8_DIM_0_SIZE                            0xF06BD0
+
+#define mmTPC4_CFG_QM_TENSOR_8_DIM_0_STRIDE                          0xF06BD4
+
+#define mmTPC4_CFG_QM_TENSOR_8_DIM_1_SIZE                            0xF06BD8
+
+#define mmTPC4_CFG_QM_TENSOR_8_DIM_1_STRIDE                          0xF06BDC
+
+#define mmTPC4_CFG_QM_TENSOR_8_DIM_2_SIZE                            0xF06BE0
+
+#define mmTPC4_CFG_QM_TENSOR_8_DIM_2_STRIDE                          0xF06BE4
+
+#define mmTPC4_CFG_QM_TENSOR_8_DIM_3_SIZE                            0xF06BE8
+
+#define mmTPC4_CFG_QM_TENSOR_8_DIM_3_STRIDE                          0xF06BEC
+
+#define mmTPC4_CFG_QM_TENSOR_8_DIM_4_SIZE                            0xF06BF0
+
+#define mmTPC4_CFG_QM_TENSOR_8_DIM_4_STRIDE                          0xF06BF4
+
+#define mmTPC4_CFG_QM_TENSOR_9_BASE_ADDR_LOW                         0xF06BF8
+
+#define mmTPC4_CFG_QM_TENSOR_9_BASE_ADDR_HIGH                        0xF06BFC
+
+#define mmTPC4_CFG_QM_TENSOR_9_PADDING_VALUE                         0xF06C00
+
+#define mmTPC4_CFG_QM_TENSOR_9_TENSOR_CONFIG                         0xF06C04
+
+#define mmTPC4_CFG_QM_TENSOR_9_DIM_0_SIZE                            0xF06C08
+
+#define mmTPC4_CFG_QM_TENSOR_9_DIM_0_STRIDE                          0xF06C0C
+
+#define mmTPC4_CFG_QM_TENSOR_9_DIM_1_SIZE                            0xF06C10
+
+#define mmTPC4_CFG_QM_TENSOR_9_DIM_1_STRIDE                          0xF06C14
+
+#define mmTPC4_CFG_QM_TENSOR_9_DIM_2_SIZE                            0xF06C18
+
+#define mmTPC4_CFG_QM_TENSOR_9_DIM_2_STRIDE                          0xF06C1C
+
+#define mmTPC4_CFG_QM_TENSOR_9_DIM_3_SIZE                            0xF06C20
+
+#define mmTPC4_CFG_QM_TENSOR_9_DIM_3_STRIDE                          0xF06C24
+
+#define mmTPC4_CFG_QM_TENSOR_9_DIM_4_SIZE                            0xF06C28
+
+#define mmTPC4_CFG_QM_TENSOR_9_DIM_4_STRIDE                          0xF06C2C
+
+#define mmTPC4_CFG_QM_TENSOR_10_BASE_ADDR_LOW                        0xF06C30
+
+#define mmTPC4_CFG_QM_TENSOR_10_BASE_ADDR_HIGH                       0xF06C34
+
+#define mmTPC4_CFG_QM_TENSOR_10_PADDING_VALUE                        0xF06C38
+
+#define mmTPC4_CFG_QM_TENSOR_10_TENSOR_CONFIG                        0xF06C3C
+
+#define mmTPC4_CFG_QM_TENSOR_10_DIM_0_SIZE                           0xF06C40
+
+#define mmTPC4_CFG_QM_TENSOR_10_DIM_0_STRIDE                         0xF06C44
+
+#define mmTPC4_CFG_QM_TENSOR_10_DIM_1_SIZE                           0xF06C48
+
+#define mmTPC4_CFG_QM_TENSOR_10_DIM_1_STRIDE                         0xF06C4C
+
+#define mmTPC4_CFG_QM_TENSOR_10_DIM_2_SIZE                           0xF06C50
+
+#define mmTPC4_CFG_QM_TENSOR_10_DIM_2_STRIDE                         0xF06C54
+
+#define mmTPC4_CFG_QM_TENSOR_10_DIM_3_SIZE                           0xF06C58
+
+#define mmTPC4_CFG_QM_TENSOR_10_DIM_3_STRIDE                         0xF06C5C
+
+#define mmTPC4_CFG_QM_TENSOR_10_DIM_4_SIZE                           0xF06C60
+
+#define mmTPC4_CFG_QM_TENSOR_10_DIM_4_STRIDE                         0xF06C64
+
+#define mmTPC4_CFG_QM_TENSOR_11_BASE_ADDR_LOW                        0xF06C68
+
+#define mmTPC4_CFG_QM_TENSOR_11_BASE_ADDR_HIGH                       0xF06C6C
+
+#define mmTPC4_CFG_QM_TENSOR_11_PADDING_VALUE                        0xF06C70
+
+#define mmTPC4_CFG_QM_TENSOR_11_TENSOR_CONFIG                        0xF06C74
+
+#define mmTPC4_CFG_QM_TENSOR_11_DIM_0_SIZE                           0xF06C78
+
+#define mmTPC4_CFG_QM_TENSOR_11_DIM_0_STRIDE                         0xF06C7C
+
+#define mmTPC4_CFG_QM_TENSOR_11_DIM_1_SIZE                           0xF06C80
+
+#define mmTPC4_CFG_QM_TENSOR_11_DIM_1_STRIDE                         0xF06C84
+
+#define mmTPC4_CFG_QM_TENSOR_11_DIM_2_SIZE                           0xF06C88
+
+#define mmTPC4_CFG_QM_TENSOR_11_DIM_2_STRIDE                         0xF06C8C
+
+#define mmTPC4_CFG_QM_TENSOR_11_DIM_3_SIZE                           0xF06C90
+
+#define mmTPC4_CFG_QM_TENSOR_11_DIM_3_STRIDE                         0xF06C94
+
+#define mmTPC4_CFG_QM_TENSOR_11_DIM_4_SIZE                           0xF06C98
+
+#define mmTPC4_CFG_QM_TENSOR_11_DIM_4_STRIDE                         0xF06C9C
+
+#define mmTPC4_CFG_QM_TENSOR_12_BASE_ADDR_LOW                        0xF06CA0
+
+#define mmTPC4_CFG_QM_TENSOR_12_BASE_ADDR_HIGH                       0xF06CA4
+
+#define mmTPC4_CFG_QM_TENSOR_12_PADDING_VALUE                        0xF06CA8
+
+#define mmTPC4_CFG_QM_TENSOR_12_TENSOR_CONFIG                        0xF06CAC
+
+#define mmTPC4_CFG_QM_TENSOR_12_DIM_0_SIZE                           0xF06CB0
+
+#define mmTPC4_CFG_QM_TENSOR_12_DIM_0_STRIDE                         0xF06CB4
+
+#define mmTPC4_CFG_QM_TENSOR_12_DIM_1_SIZE                           0xF06CB8
+
+#define mmTPC4_CFG_QM_TENSOR_12_DIM_1_STRIDE                         0xF06CBC
+
+#define mmTPC4_CFG_QM_TENSOR_12_DIM_2_SIZE                           0xF06CC0
+
+#define mmTPC4_CFG_QM_TENSOR_12_DIM_2_STRIDE                         0xF06CC4
+
+#define mmTPC4_CFG_QM_TENSOR_12_DIM_3_SIZE                           0xF06CC8
+
+#define mmTPC4_CFG_QM_TENSOR_12_DIM_3_STRIDE                         0xF06CCC
+
+#define mmTPC4_CFG_QM_TENSOR_12_DIM_4_SIZE                           0xF06CD0
+
+#define mmTPC4_CFG_QM_TENSOR_12_DIM_4_STRIDE                         0xF06CD4
+
+#define mmTPC4_CFG_QM_TENSOR_13_BASE_ADDR_LOW                        0xF06CD8
+
+#define mmTPC4_CFG_QM_TENSOR_13_BASE_ADDR_HIGH                       0xF06CDC
+
+#define mmTPC4_CFG_QM_TENSOR_13_PADDING_VALUE                        0xF06CE0
+
+#define mmTPC4_CFG_QM_TENSOR_13_TENSOR_CONFIG                        0xF06CE4
+
+#define mmTPC4_CFG_QM_TENSOR_13_DIM_0_SIZE                           0xF06CE8
+
+#define mmTPC4_CFG_QM_TENSOR_13_DIM_0_STRIDE                         0xF06CEC
+
+#define mmTPC4_CFG_QM_TENSOR_13_DIM_1_SIZE                           0xF06CF0
+
+#define mmTPC4_CFG_QM_TENSOR_13_DIM_1_STRIDE                         0xF06CF4
+
+#define mmTPC4_CFG_QM_TENSOR_13_DIM_2_SIZE                           0xF06CF8
+
+#define mmTPC4_CFG_QM_TENSOR_13_DIM_2_STRIDE                         0xF06CFC
+
+#define mmTPC4_CFG_QM_TENSOR_13_DIM_3_SIZE                           0xF06D00
+
+#define mmTPC4_CFG_QM_TENSOR_13_DIM_3_STRIDE                         0xF06D04
+
+#define mmTPC4_CFG_QM_TENSOR_13_DIM_4_SIZE                           0xF06D08
+
+#define mmTPC4_CFG_QM_TENSOR_13_DIM_4_STRIDE                         0xF06D0C
+
+#define mmTPC4_CFG_QM_TENSOR_14_BASE_ADDR_LOW                        0xF06D10
+
+#define mmTPC4_CFG_QM_TENSOR_14_BASE_ADDR_HIGH                       0xF06D14
+
+#define mmTPC4_CFG_QM_TENSOR_14_PADDING_VALUE                        0xF06D18
+
+#define mmTPC4_CFG_QM_TENSOR_14_TENSOR_CONFIG                        0xF06D1C
+
+#define mmTPC4_CFG_QM_TENSOR_14_DIM_0_SIZE                           0xF06D20
+
+#define mmTPC4_CFG_QM_TENSOR_14_DIM_0_STRIDE                         0xF06D24
+
+#define mmTPC4_CFG_QM_TENSOR_14_DIM_1_SIZE                           0xF06D28
+
+#define mmTPC4_CFG_QM_TENSOR_14_DIM_1_STRIDE                         0xF06D2C
+
+#define mmTPC4_CFG_QM_TENSOR_14_DIM_2_SIZE                           0xF06D30
+
+#define mmTPC4_CFG_QM_TENSOR_14_DIM_2_STRIDE                         0xF06D34
+
+#define mmTPC4_CFG_QM_TENSOR_14_DIM_3_SIZE                           0xF06D38
+
+#define mmTPC4_CFG_QM_TENSOR_14_DIM_3_STRIDE                         0xF06D3C
+
+#define mmTPC4_CFG_QM_TENSOR_14_DIM_4_SIZE                           0xF06D40
+
+#define mmTPC4_CFG_QM_TENSOR_14_DIM_4_STRIDE                         0xF06D44
+
+#define mmTPC4_CFG_QM_TENSOR_15_BASE_ADDR_LOW                        0xF06D48
+
+#define mmTPC4_CFG_QM_TENSOR_15_BASE_ADDR_HIGH                       0xF06D4C
+
+#define mmTPC4_CFG_QM_TENSOR_15_PADDING_VALUE                        0xF06D50
+
+#define mmTPC4_CFG_QM_TENSOR_15_TENSOR_CONFIG                        0xF06D54
+
+#define mmTPC4_CFG_QM_TENSOR_15_DIM_0_SIZE                           0xF06D58
+
+#define mmTPC4_CFG_QM_TENSOR_15_DIM_0_STRIDE                         0xF06D5C
+
+#define mmTPC4_CFG_QM_TENSOR_15_DIM_1_SIZE                           0xF06D60
+
+#define mmTPC4_CFG_QM_TENSOR_15_DIM_1_STRIDE                         0xF06D64
+
+#define mmTPC4_CFG_QM_TENSOR_15_DIM_2_SIZE                           0xF06D68
+
+#define mmTPC4_CFG_QM_TENSOR_15_DIM_2_STRIDE                         0xF06D6C
+
+#define mmTPC4_CFG_QM_TENSOR_15_DIM_3_SIZE                           0xF06D70
+
+#define mmTPC4_CFG_QM_TENSOR_15_DIM_3_STRIDE                         0xF06D74
+
+#define mmTPC4_CFG_QM_TENSOR_15_DIM_4_SIZE                           0xF06D78
+
+#define mmTPC4_CFG_QM_TENSOR_15_DIM_4_STRIDE                         0xF06D7C
+
+#define mmTPC4_CFG_QM_SYNC_OBJECT_MESSAGE                            0xF06D80
+
+#define mmTPC4_CFG_QM_SYNC_OBJECT_ADDR                               0xF06D84
+
+#define mmTPC4_CFG_QM_KERNEL_BASE_ADDRESS_LOW                        0xF06D88
+
+#define mmTPC4_CFG_QM_KERNEL_BASE_ADDRESS_HIGH                       0xF06D8C
+
+#define mmTPC4_CFG_QM_TID_BASE_DIM_0                                 0xF06D90
+
+#define mmTPC4_CFG_QM_TID_SIZE_DIM_0                                 0xF06D94
+
+#define mmTPC4_CFG_QM_TID_BASE_DIM_1                                 0xF06D98
+
+#define mmTPC4_CFG_QM_TID_SIZE_DIM_1                                 0xF06D9C
+
+#define mmTPC4_CFG_QM_TID_BASE_DIM_2                                 0xF06DA0
+
+#define mmTPC4_CFG_QM_TID_SIZE_DIM_2                                 0xF06DA4
+
+#define mmTPC4_CFG_QM_TID_BASE_DIM_3                                 0xF06DA8
+
+#define mmTPC4_CFG_QM_TID_SIZE_DIM_3                                 0xF06DAC
+
+#define mmTPC4_CFG_QM_TID_BASE_DIM_4                                 0xF06DB0
+
+#define mmTPC4_CFG_QM_TID_SIZE_DIM_4                                 0xF06DB4
+
+#define mmTPC4_CFG_QM_KERNEL_CONFIG                                  0xF06DB8
+
+#define mmTPC4_CFG_QM_KERNEL_ID                                      0xF06DBC
+
+#define mmTPC4_CFG_QM_SRF_0                                          0xF06DC0
+
+#define mmTPC4_CFG_QM_SRF_1                                          0xF06DC4
+
+#define mmTPC4_CFG_QM_SRF_2                                          0xF06DC8
+
+#define mmTPC4_CFG_QM_SRF_3                                          0xF06DCC
+
+#define mmTPC4_CFG_QM_SRF_4                                          0xF06DD0
+
+#define mmTPC4_CFG_QM_SRF_5                                          0xF06DD4
+
+#define mmTPC4_CFG_QM_SRF_6                                          0xF06DD8
+
+#define mmTPC4_CFG_QM_SRF_7                                          0xF06DDC
+
+#define mmTPC4_CFG_QM_SRF_8                                          0xF06DE0
+
+#define mmTPC4_CFG_QM_SRF_9                                          0xF06DE4
+
+#define mmTPC4_CFG_QM_SRF_10                                         0xF06DE8
+
+#define mmTPC4_CFG_QM_SRF_11                                         0xF06DEC
+
+#define mmTPC4_CFG_QM_SRF_12                                         0xF06DF0
+
+#define mmTPC4_CFG_QM_SRF_13                                         0xF06DF4
+
+#define mmTPC4_CFG_QM_SRF_14                                         0xF06DF8
+
+#define mmTPC4_CFG_QM_SRF_15                                         0xF06DFC
+
+#define mmTPC4_CFG_QM_SRF_16                                         0xF06E00
+
+#define mmTPC4_CFG_QM_SRF_17                                         0xF06E04
+
+#define mmTPC4_CFG_QM_SRF_18                                         0xF06E08
+
+#define mmTPC4_CFG_QM_SRF_19                                         0xF06E0C
+
+#define mmTPC4_CFG_QM_SRF_20                                         0xF06E10
+
+#define mmTPC4_CFG_QM_SRF_21                                         0xF06E14
+
+#define mmTPC4_CFG_QM_SRF_22                                         0xF06E18
+
+#define mmTPC4_CFG_QM_SRF_23                                         0xF06E1C
+
+#define mmTPC4_CFG_QM_SRF_24                                         0xF06E20
+
+#define mmTPC4_CFG_QM_SRF_25                                         0xF06E24
+
+#define mmTPC4_CFG_QM_SRF_26                                         0xF06E28
+
+#define mmTPC4_CFG_QM_SRF_27                                         0xF06E2C
+
+#define mmTPC4_CFG_QM_SRF_28                                         0xF06E30
+
+#define mmTPC4_CFG_QM_SRF_29                                         0xF06E34
+
+#define mmTPC4_CFG_QM_SRF_30                                         0xF06E38
+
+#define mmTPC4_CFG_QM_SRF_31                                         0xF06E3C
+
+#endif /* ASIC_REG_TPC4_CFG_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc4_qm_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc4_qm_regs.h
new file mode 100644
index 000000000000..80e63402f6e0
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc4_qm_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_TPC4_QM_REGS_H_
+#define ASIC_REG_TPC4_QM_REGS_H_
+
+/*
+ *****************************************
+ *   TPC4_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmTPC4_QM_GLBL_CFG0                                          0xF08000
+
+#define mmTPC4_QM_GLBL_CFG1                                          0xF08004
+
+#define mmTPC4_QM_GLBL_PROT                                          0xF08008
+
+#define mmTPC4_QM_GLBL_ERR_CFG                                       0xF0800C
+
+#define mmTPC4_QM_GLBL_SECURE_PROPS_0                                0xF08010
+
+#define mmTPC4_QM_GLBL_SECURE_PROPS_1                                0xF08014
+
+#define mmTPC4_QM_GLBL_SECURE_PROPS_2                                0xF08018
+
+#define mmTPC4_QM_GLBL_SECURE_PROPS_3                                0xF0801C
+
+#define mmTPC4_QM_GLBL_SECURE_PROPS_4                                0xF08020
+
+#define mmTPC4_QM_GLBL_NON_SECURE_PROPS_0                            0xF08024
+
+#define mmTPC4_QM_GLBL_NON_SECURE_PROPS_1                            0xF08028
+
+#define mmTPC4_QM_GLBL_NON_SECURE_PROPS_2                            0xF0802C
+
+#define mmTPC4_QM_GLBL_NON_SECURE_PROPS_3                            0xF08030
+
+#define mmTPC4_QM_GLBL_NON_SECURE_PROPS_4                            0xF08034
+
+#define mmTPC4_QM_GLBL_STS0                                          0xF08038
+
+#define mmTPC4_QM_GLBL_STS1_0                                        0xF08040
+
+#define mmTPC4_QM_GLBL_STS1_1                                        0xF08044
+
+#define mmTPC4_QM_GLBL_STS1_2                                        0xF08048
+
+#define mmTPC4_QM_GLBL_STS1_3                                        0xF0804C
+
+#define mmTPC4_QM_GLBL_STS1_4                                        0xF08050
+
+#define mmTPC4_QM_GLBL_MSG_EN_0                                      0xF08054
+
+#define mmTPC4_QM_GLBL_MSG_EN_1                                      0xF08058
+
+#define mmTPC4_QM_GLBL_MSG_EN_2                                      0xF0805C
+
+#define mmTPC4_QM_GLBL_MSG_EN_3                                      0xF08060
+
+#define mmTPC4_QM_GLBL_MSG_EN_4                                      0xF08068
+
+#define mmTPC4_QM_PQ_BASE_LO_0                                       0xF08070
+
+#define mmTPC4_QM_PQ_BASE_LO_1                                       0xF08074
+
+#define mmTPC4_QM_PQ_BASE_LO_2                                       0xF08078
+
+#define mmTPC4_QM_PQ_BASE_LO_3                                       0xF0807C
+
+#define mmTPC4_QM_PQ_BASE_HI_0                                       0xF08080
+
+#define mmTPC4_QM_PQ_BASE_HI_1                                       0xF08084
+
+#define mmTPC4_QM_PQ_BASE_HI_2                                       0xF08088
+
+#define mmTPC4_QM_PQ_BASE_HI_3                                       0xF0808C
+
+#define mmTPC4_QM_PQ_SIZE_0                                          0xF08090
+
+#define mmTPC4_QM_PQ_SIZE_1                                          0xF08094
+
+#define mmTPC4_QM_PQ_SIZE_2                                          0xF08098
+
+#define mmTPC4_QM_PQ_SIZE_3                                          0xF0809C
+
+#define mmTPC4_QM_PQ_PI_0                                            0xF080A0
+
+#define mmTPC4_QM_PQ_PI_1                                            0xF080A4
+
+#define mmTPC4_QM_PQ_PI_2                                            0xF080A8
+
+#define mmTPC4_QM_PQ_PI_3                                            0xF080AC
+
+#define mmTPC4_QM_PQ_CI_0                                            0xF080B0
+
+#define mmTPC4_QM_PQ_CI_1                                            0xF080B4
+
+#define mmTPC4_QM_PQ_CI_2                                            0xF080B8
+
+#define mmTPC4_QM_PQ_CI_3                                            0xF080BC
+
+#define mmTPC4_QM_PQ_CFG0_0                                          0xF080C0
+
+#define mmTPC4_QM_PQ_CFG0_1                                          0xF080C4
+
+#define mmTPC4_QM_PQ_CFG0_2                                          0xF080C8
+
+#define mmTPC4_QM_PQ_CFG0_3                                          0xF080CC
+
+#define mmTPC4_QM_PQ_CFG1_0                                          0xF080D0
+
+#define mmTPC4_QM_PQ_CFG1_1                                          0xF080D4
+
+#define mmTPC4_QM_PQ_CFG1_2                                          0xF080D8
+
+#define mmTPC4_QM_PQ_CFG1_3                                          0xF080DC
+
+#define mmTPC4_QM_PQ_ARUSER_31_11_0                                  0xF080E0
+
+#define mmTPC4_QM_PQ_ARUSER_31_11_1                                  0xF080E4
+
+#define mmTPC4_QM_PQ_ARUSER_31_11_2                                  0xF080E8
+
+#define mmTPC4_QM_PQ_ARUSER_31_11_3                                  0xF080EC
+
+#define mmTPC4_QM_PQ_STS0_0                                          0xF080F0
+
+#define mmTPC4_QM_PQ_STS0_1                                          0xF080F4
+
+#define mmTPC4_QM_PQ_STS0_2                                          0xF080F8
+
+#define mmTPC4_QM_PQ_STS0_3                                          0xF080FC
+
+#define mmTPC4_QM_PQ_STS1_0                                          0xF08100
+
+#define mmTPC4_QM_PQ_STS1_1                                          0xF08104
+
+#define mmTPC4_QM_PQ_STS1_2                                          0xF08108
+
+#define mmTPC4_QM_PQ_STS1_3                                          0xF0810C
+
+#define mmTPC4_QM_CQ_CFG0_0                                          0xF08110
+
+#define mmTPC4_QM_CQ_CFG0_1                                          0xF08114
+
+#define mmTPC4_QM_CQ_CFG0_2                                          0xF08118
+
+#define mmTPC4_QM_CQ_CFG0_3                                          0xF0811C
+
+#define mmTPC4_QM_CQ_CFG0_4                                          0xF08120
+
+#define mmTPC4_QM_CQ_CFG1_0                                          0xF08124
+
+#define mmTPC4_QM_CQ_CFG1_1                                          0xF08128
+
+#define mmTPC4_QM_CQ_CFG1_2                                          0xF0812C
+
+#define mmTPC4_QM_CQ_CFG1_3                                          0xF08130
+
+#define mmTPC4_QM_CQ_CFG1_4                                          0xF08134
+
+#define mmTPC4_QM_CQ_ARUSER_31_11_0                                  0xF08138
+
+#define mmTPC4_QM_CQ_ARUSER_31_11_1                                  0xF0813C
+
+#define mmTPC4_QM_CQ_ARUSER_31_11_2                                  0xF08140
+
+#define mmTPC4_QM_CQ_ARUSER_31_11_3                                  0xF08144
+
+#define mmTPC4_QM_CQ_ARUSER_31_11_4                                  0xF08148
+
+#define mmTPC4_QM_CQ_STS0_0                                          0xF0814C
+
+#define mmTPC4_QM_CQ_STS0_1                                          0xF08150
+
+#define mmTPC4_QM_CQ_STS0_2                                          0xF08154
+
+#define mmTPC4_QM_CQ_STS0_3                                          0xF08158
+
+#define mmTPC4_QM_CQ_STS0_4                                          0xF0815C
+
+#define mmTPC4_QM_CQ_STS1_0                                          0xF08160
+
+#define mmTPC4_QM_CQ_STS1_1                                          0xF08164
+
+#define mmTPC4_QM_CQ_STS1_2                                          0xF08168
+
+#define mmTPC4_QM_CQ_STS1_3                                          0xF0816C
+
+#define mmTPC4_QM_CQ_STS1_4                                          0xF08170
+
+#define mmTPC4_QM_CQ_PTR_LO_0                                        0xF08174
+
+#define mmTPC4_QM_CQ_PTR_HI_0                                        0xF08178
+
+#define mmTPC4_QM_CQ_TSIZE_0                                         0xF0817C
+
+#define mmTPC4_QM_CQ_CTL_0                                           0xF08180
+
+#define mmTPC4_QM_CQ_PTR_LO_1                                        0xF08184
+
+#define mmTPC4_QM_CQ_PTR_HI_1                                        0xF08188
+
+#define mmTPC4_QM_CQ_TSIZE_1                                         0xF0818C
+
+#define mmTPC4_QM_CQ_CTL_1                                           0xF08190
+
+#define mmTPC4_QM_CQ_PTR_LO_2                                        0xF08194
+
+#define mmTPC4_QM_CQ_PTR_HI_2                                        0xF08198
+
+#define mmTPC4_QM_CQ_TSIZE_2                                         0xF0819C
+
+#define mmTPC4_QM_CQ_CTL_2                                           0xF081A0
+
+#define mmTPC4_QM_CQ_PTR_LO_3                                        0xF081A4
+
+#define mmTPC4_QM_CQ_PTR_HI_3                                        0xF081A8
+
+#define mmTPC4_QM_CQ_TSIZE_3                                         0xF081AC
+
+#define mmTPC4_QM_CQ_CTL_3                                           0xF081B0
+
+#define mmTPC4_QM_CQ_PTR_LO_4                                        0xF081B4
+
+#define mmTPC4_QM_CQ_PTR_HI_4                                        0xF081B8
+
+#define mmTPC4_QM_CQ_TSIZE_4                                         0xF081BC
+
+#define mmTPC4_QM_CQ_CTL_4                                           0xF081C0
+
+#define mmTPC4_QM_CQ_PTR_LO_STS_0                                    0xF081C4
+
+#define mmTPC4_QM_CQ_PTR_LO_STS_1                                    0xF081C8
+
+#define mmTPC4_QM_CQ_PTR_LO_STS_2                                    0xF081CC
+
+#define mmTPC4_QM_CQ_PTR_LO_STS_3                                    0xF081D0
+
+#define mmTPC4_QM_CQ_PTR_LO_STS_4                                    0xF081D4
+
+#define mmTPC4_QM_CQ_PTR_HI_STS_0                                    0xF081D8
+
+#define mmTPC4_QM_CQ_PTR_HI_STS_1                                    0xF081DC
+
+#define mmTPC4_QM_CQ_PTR_HI_STS_2                                    0xF081E0
+
+#define mmTPC4_QM_CQ_PTR_HI_STS_3                                    0xF081E4
+
+#define mmTPC4_QM_CQ_PTR_HI_STS_4                                    0xF081E8
+
+#define mmTPC4_QM_CQ_TSIZE_STS_0                                     0xF081EC
+
+#define mmTPC4_QM_CQ_TSIZE_STS_1                                     0xF081F0
+
+#define mmTPC4_QM_CQ_TSIZE_STS_2                                     0xF081F4
+
+#define mmTPC4_QM_CQ_TSIZE_STS_3                                     0xF081F8
+
+#define mmTPC4_QM_CQ_TSIZE_STS_4                                     0xF081FC
+
+#define mmTPC4_QM_CQ_CTL_STS_0                                       0xF08200
+
+#define mmTPC4_QM_CQ_CTL_STS_1                                       0xF08204
+
+#define mmTPC4_QM_CQ_CTL_STS_2                                       0xF08208
+
+#define mmTPC4_QM_CQ_CTL_STS_3                                       0xF0820C
+
+#define mmTPC4_QM_CQ_CTL_STS_4                                       0xF08210
+
+#define mmTPC4_QM_CQ_IFIFO_CNT_0                                     0xF08214
+
+#define mmTPC4_QM_CQ_IFIFO_CNT_1                                     0xF08218
+
+#define mmTPC4_QM_CQ_IFIFO_CNT_2                                     0xF0821C
+
+#define mmTPC4_QM_CQ_IFIFO_CNT_3                                     0xF08220
+
+#define mmTPC4_QM_CQ_IFIFO_CNT_4                                     0xF08224
+
+#define mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_0                             0xF08228
+
+#define mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_1                             0xF0822C
+
+#define mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_2                             0xF08230
+
+#define mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_3                             0xF08234
+
+#define mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_4                             0xF08238
+
+#define mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_0                             0xF0823C
+
+#define mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_1                             0xF08240
+
+#define mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_2                             0xF08244
+
+#define mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_3                             0xF08248
+
+#define mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_4                             0xF0824C
+
+#define mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_0                             0xF08250
+
+#define mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_1                             0xF08254
+
+#define mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_2                             0xF08258
+
+#define mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_3                             0xF0825C
+
+#define mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_4                             0xF08260
+
+#define mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_0                             0xF08264
+
+#define mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_1                             0xF08268
+
+#define mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_2                             0xF0826C
+
+#define mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_3                             0xF08270
+
+#define mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_4                             0xF08274
+
+#define mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_0                             0xF08278
+
+#define mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_1                             0xF0827C
+
+#define mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_2                             0xF08280
+
+#define mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_3                             0xF08284
+
+#define mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_4                             0xF08288
+
+#define mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_0                             0xF0828C
+
+#define mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_1                             0xF08290
+
+#define mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_2                             0xF08294
+
+#define mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_3                             0xF08298
+
+#define mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_4                             0xF0829C
+
+#define mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_0                             0xF082A0
+
+#define mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_1                             0xF082A4
+
+#define mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_2                             0xF082A8
+
+#define mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_3                             0xF082AC
+
+#define mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_4                             0xF082B0
+
+#define mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_0                             0xF082B4
+
+#define mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_1                             0xF082B8
+
+#define mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_2                             0xF082BC
+
+#define mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_3                             0xF082C0
+
+#define mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_4                             0xF082C4
+
+#define mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_0                             0xF082C8
+
+#define mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_1                             0xF082CC
+
+#define mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_2                             0xF082D0
+
+#define mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_3                             0xF082D4
+
+#define mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_4                             0xF082D8
+
+#define mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0                       0xF082E0
+
+#define mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1                       0xF082E4
+
+#define mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2                       0xF082E8
+
+#define mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3                       0xF082EC
+
+#define mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4                       0xF082F0
+
+#define mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_0                       0xF082F4
+
+#define mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_1                       0xF082F8
+
+#define mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_2                       0xF082FC
+
+#define mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3                       0xF08300
+
+#define mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_4                       0xF08304
+
+#define mmTPC4_QM_CP_FENCE0_RDATA_0                                  0xF08308
+
+#define mmTPC4_QM_CP_FENCE0_RDATA_1                                  0xF0830C
+
+#define mmTPC4_QM_CP_FENCE0_RDATA_2                                  0xF08310
+
+#define mmTPC4_QM_CP_FENCE0_RDATA_3                                  0xF08314
+
+#define mmTPC4_QM_CP_FENCE0_RDATA_4                                  0xF08318
+
+#define mmTPC4_QM_CP_FENCE1_RDATA_0                                  0xF0831C
+
+#define mmTPC4_QM_CP_FENCE1_RDATA_1                                  0xF08320
+
+#define mmTPC4_QM_CP_FENCE1_RDATA_2                                  0xF08324
+
+#define mmTPC4_QM_CP_FENCE1_RDATA_3                                  0xF08328
+
+#define mmTPC4_QM_CP_FENCE1_RDATA_4                                  0xF0832C
+
+#define mmTPC4_QM_CP_FENCE2_RDATA_0                                  0xF08330
+
+#define mmTPC4_QM_CP_FENCE2_RDATA_1                                  0xF08334
+
+#define mmTPC4_QM_CP_FENCE2_RDATA_2                                  0xF08338
+
+#define mmTPC4_QM_CP_FENCE2_RDATA_3                                  0xF0833C
+
+#define mmTPC4_QM_CP_FENCE2_RDATA_4                                  0xF08340
+
+#define mmTPC4_QM_CP_FENCE3_RDATA_0                                  0xF08344
+
+#define mmTPC4_QM_CP_FENCE3_RDATA_1                                  0xF08348
+
+#define mmTPC4_QM_CP_FENCE3_RDATA_2                                  0xF0834C
+
+#define mmTPC4_QM_CP_FENCE3_RDATA_3                                  0xF08350
+
+#define mmTPC4_QM_CP_FENCE3_RDATA_4                                  0xF08354
+
+#define mmTPC4_QM_CP_FENCE0_CNT_0                                    0xF08358
+
+#define mmTPC4_QM_CP_FENCE0_CNT_1                                    0xF0835C
+
+#define mmTPC4_QM_CP_FENCE0_CNT_2                                    0xF08360
+
+#define mmTPC4_QM_CP_FENCE0_CNT_3                                    0xF08364
+
+#define mmTPC4_QM_CP_FENCE0_CNT_4                                    0xF08368
+
+#define mmTPC4_QM_CP_FENCE1_CNT_0                                    0xF0836C
+
+#define mmTPC4_QM_CP_FENCE1_CNT_1                                    0xF08370
+
+#define mmTPC4_QM_CP_FENCE1_CNT_2                                    0xF08374
+
+#define mmTPC4_QM_CP_FENCE1_CNT_3                                    0xF08378
+
+#define mmTPC4_QM_CP_FENCE1_CNT_4                                    0xF0837C
+
+#define mmTPC4_QM_CP_FENCE2_CNT_0                                    0xF08380
+
+#define mmTPC4_QM_CP_FENCE2_CNT_1                                    0xF08384
+
+#define mmTPC4_QM_CP_FENCE2_CNT_2                                    0xF08388
+
+#define mmTPC4_QM_CP_FENCE2_CNT_3                                    0xF0838C
+
+#define mmTPC4_QM_CP_FENCE2_CNT_4                                    0xF08390
+
+#define mmTPC4_QM_CP_FENCE3_CNT_0                                    0xF08394
+
+#define mmTPC4_QM_CP_FENCE3_CNT_1                                    0xF08398
+
+#define mmTPC4_QM_CP_FENCE3_CNT_2                                    0xF0839C
+
+#define mmTPC4_QM_CP_FENCE3_CNT_3                                    0xF083A0
+
+#define mmTPC4_QM_CP_FENCE3_CNT_4                                    0xF083A4
+
+#define mmTPC4_QM_CP_STS_0                                           0xF083A8
+
+#define mmTPC4_QM_CP_STS_1                                           0xF083AC
+
+#define mmTPC4_QM_CP_STS_2                                           0xF083B0
+
+#define mmTPC4_QM_CP_STS_3                                           0xF083B4
+
+#define mmTPC4_QM_CP_STS_4                                           0xF083B8
+
+#define mmTPC4_QM_CP_CURRENT_INST_LO_0                               0xF083BC
+
+#define mmTPC4_QM_CP_CURRENT_INST_LO_1                               0xF083C0
+
+#define mmTPC4_QM_CP_CURRENT_INST_LO_2                               0xF083C4
+
+#define mmTPC4_QM_CP_CURRENT_INST_LO_3                               0xF083C8
+
+#define mmTPC4_QM_CP_CURRENT_INST_LO_4                               0xF083CC
+
+#define mmTPC4_QM_CP_CURRENT_INST_HI_0                               0xF083D0
+
+#define mmTPC4_QM_CP_CURRENT_INST_HI_1                               0xF083D4
+
+#define mmTPC4_QM_CP_CURRENT_INST_HI_2                               0xF083D8
+
+#define mmTPC4_QM_CP_CURRENT_INST_HI_3                               0xF083DC
+
+#define mmTPC4_QM_CP_CURRENT_INST_HI_4                               0xF083E0
+
+#define mmTPC4_QM_CP_BARRIER_CFG_0                                   0xF083F4
+
+#define mmTPC4_QM_CP_BARRIER_CFG_1                                   0xF083F8
+
+#define mmTPC4_QM_CP_BARRIER_CFG_2                                   0xF083FC
+
+#define mmTPC4_QM_CP_BARRIER_CFG_3                                   0xF08400
+
+#define mmTPC4_QM_CP_BARRIER_CFG_4                                   0xF08404
+
+#define mmTPC4_QM_CP_DBG_0_0                                         0xF08408
+
+#define mmTPC4_QM_CP_DBG_0_1                                         0xF0840C
+
+#define mmTPC4_QM_CP_DBG_0_2                                         0xF08410
+
+#define mmTPC4_QM_CP_DBG_0_3                                         0xF08414
+
+#define mmTPC4_QM_CP_DBG_0_4                                         0xF08418
+
+#define mmTPC4_QM_CP_ARUSER_31_11_0                                  0xF0841C
+
+#define mmTPC4_QM_CP_ARUSER_31_11_1                                  0xF08420
+
+#define mmTPC4_QM_CP_ARUSER_31_11_2                                  0xF08424
+
+#define mmTPC4_QM_CP_ARUSER_31_11_3                                  0xF08428
+
+#define mmTPC4_QM_CP_ARUSER_31_11_4                                  0xF0842C
+
+#define mmTPC4_QM_CP_AWUSER_31_11_0                                  0xF08430
+
+#define mmTPC4_QM_CP_AWUSER_31_11_1                                  0xF08434
+
+#define mmTPC4_QM_CP_AWUSER_31_11_2                                  0xF08438
+
+#define mmTPC4_QM_CP_AWUSER_31_11_3                                  0xF0843C
+
+#define mmTPC4_QM_CP_AWUSER_31_11_4                                  0xF08440
+
+#define mmTPC4_QM_ARB_CFG_0                                          0xF08A00
+
+#define mmTPC4_QM_ARB_CHOISE_Q_PUSH                                  0xF08A04
+
+#define mmTPC4_QM_ARB_WRR_WEIGHT_0                                   0xF08A08
+
+#define mmTPC4_QM_ARB_WRR_WEIGHT_1                                   0xF08A0C
+
+#define mmTPC4_QM_ARB_WRR_WEIGHT_2                                   0xF08A10
+
+#define mmTPC4_QM_ARB_WRR_WEIGHT_3                                   0xF08A14
+
+#define mmTPC4_QM_ARB_CFG_1                                          0xF08A18
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_0                               0xF08A20
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_1                               0xF08A24
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_2                               0xF08A28
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_3                               0xF08A2C
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_4                               0xF08A30
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_5                               0xF08A34
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_6                               0xF08A38
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_7                               0xF08A3C
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_8                               0xF08A40
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_9                               0xF08A44
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_10                              0xF08A48
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_11                              0xF08A4C
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_12                              0xF08A50
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_13                              0xF08A54
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_14                              0xF08A58
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_15                              0xF08A5C
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_16                              0xF08A60
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_17                              0xF08A64
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_18                              0xF08A68
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_19                              0xF08A6C
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_20                              0xF08A70
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_21                              0xF08A74
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_22                              0xF08A78
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_23                              0xF08A7C
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_24                              0xF08A80
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_25                              0xF08A84
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_26                              0xF08A88
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_27                              0xF08A8C
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_28                              0xF08A90
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_29                              0xF08A94
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_30                              0xF08A98
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_31                              0xF08A9C
+
+#define mmTPC4_QM_ARB_MST_CRED_INC                                   0xF08AA0
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_0                         0xF08AA4
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_1                         0xF08AA8
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_2                         0xF08AAC
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_3                         0xF08AB0
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_4                         0xF08AB4
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_5                         0xF08AB8
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_6                         0xF08ABC
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_7                         0xF08AC0
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_8                         0xF08AC4
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_9                         0xF08AC8
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_10                        0xF08ACC
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_11                        0xF08AD0
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_12                        0xF08AD4
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_13                        0xF08AD8
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_14                        0xF08ADC
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_15                        0xF08AE0
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_16                        0xF08AE4
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_17                        0xF08AE8
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_18                        0xF08AEC
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_19                        0xF08AF0
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_20                        0xF08AF4
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_21                        0xF08AF8
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_22                        0xF08AFC
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_23                        0xF08B00
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_24                        0xF08B04
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_25                        0xF08B08
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_26                        0xF08B0C
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_27                        0xF08B10
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_28                        0xF08B14
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_29                        0xF08B18
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_30                        0xF08B1C
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_31                        0xF08B20
+
+#define mmTPC4_QM_ARB_SLV_MASTER_INC_CRED_OFST                       0xF08B28
+
+#define mmTPC4_QM_ARB_MST_SLAVE_EN                                   0xF08B2C
+
+#define mmTPC4_QM_ARB_MST_QUIET_PER                                  0xF08B34
+
+#define mmTPC4_QM_ARB_SLV_CHOISE_WDT                                 0xF08B38
+
+#define mmTPC4_QM_ARB_SLV_ID                                         0xF08B3C
+
+#define mmTPC4_QM_ARB_MSG_MAX_INFLIGHT                               0xF08B44
+
+#define mmTPC4_QM_ARB_MSG_AWUSER_31_11                               0xF08B48
+
+#define mmTPC4_QM_ARB_MSG_AWUSER_SEC_PROP                            0xF08B4C
+
+#define mmTPC4_QM_ARB_MSG_AWUSER_NON_SEC_PROP                        0xF08B50
+
+#define mmTPC4_QM_ARB_BASE_LO                                        0xF08B54
+
+#define mmTPC4_QM_ARB_BASE_HI                                        0xF08B58
+
+#define mmTPC4_QM_ARB_STATE_STS                                      0xF08B80
+
+#define mmTPC4_QM_ARB_CHOISE_FULLNESS_STS                            0xF08B84
+
+#define mmTPC4_QM_ARB_MSG_STS                                        0xF08B88
+
+#define mmTPC4_QM_ARB_SLV_CHOISE_Q_HEAD                              0xF08B8C
+
+#define mmTPC4_QM_ARB_ERR_CAUSE                                      0xF08B9C
+
+#define mmTPC4_QM_ARB_ERR_MSG_EN                                     0xF08BA0
+
+#define mmTPC4_QM_ARB_ERR_STS_DRP                                    0xF08BA8
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_0                                 0xF08BB0
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_1                                 0xF08BB4
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_2                                 0xF08BB8
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_3                                 0xF08BBC
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_4                                 0xF08BC0
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_5                                 0xF08BC4
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_6                                 0xF08BC8
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_7                                 0xF08BCC
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_8                                 0xF08BD0
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_9                                 0xF08BD4
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_10                                0xF08BD8
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_11                                0xF08BDC
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_12                                0xF08BE0
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_13                                0xF08BE4
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_14                                0xF08BE8
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_15                                0xF08BEC
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_16                                0xF08BF0
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_17                                0xF08BF4
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_18                                0xF08BF8
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_19                                0xF08BFC
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_20                                0xF08C00
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_21                                0xF08C04
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_22                                0xF08C08
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_23                                0xF08C0C
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_24                                0xF08C10
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_25                                0xF08C14
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_26                                0xF08C18
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_27                                0xF08C1C
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_28                                0xF08C20
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_29                                0xF08C24
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_30                                0xF08C28
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_31                                0xF08C2C
+
+#define mmTPC4_QM_CGM_CFG                                            0xF08C70
+
+#define mmTPC4_QM_CGM_STS                                            0xF08C74
+
+#define mmTPC4_QM_CGM_CFG1                                           0xF08C78
+
+#define mmTPC4_QM_LOCAL_RANGE_BASE                                   0xF08C80
+
+#define mmTPC4_QM_LOCAL_RANGE_SIZE                                   0xF08C84
+
+#define mmTPC4_QM_CSMR_STRICT_PRIO_CFG                               0xF08C90
+
+#define mmTPC4_QM_HBW_RD_RATE_LIM_CFG_1                              0xF08C94
+
+#define mmTPC4_QM_LBW_WR_RATE_LIM_CFG_0                              0xF08C98
+
+#define mmTPC4_QM_LBW_WR_RATE_LIM_CFG_1                              0xF08C9C
+
+#define mmTPC4_QM_HBW_RD_RATE_LIM_CFG_0                              0xF08CA0
+
+#define mmTPC4_QM_GLBL_AXCACHE                                       0xF08CA4
+
+#define mmTPC4_QM_IND_GW_APB_CFG                                     0xF08CB0
+
+#define mmTPC4_QM_IND_GW_APB_WDATA                                   0xF08CB4
+
+#define mmTPC4_QM_IND_GW_APB_RDATA                                   0xF08CB8
+
+#define mmTPC4_QM_IND_GW_APB_STATUS                                  0xF08CBC
+
+#define mmTPC4_QM_GLBL_ERR_ADDR_LO                                   0xF08CD0
+
+#define mmTPC4_QM_GLBL_ERR_ADDR_HI                                   0xF08CD4
+
+#define mmTPC4_QM_GLBL_ERR_WDATA                                     0xF08CD8
+
+#define mmTPC4_QM_GLBL_MEM_INIT_BUSY                                 0xF08D00
+
+#endif /* ASIC_REG_TPC4_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc5_cfg_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc5_cfg_regs.h
new file mode 100644
index 000000000000..f428f891935a
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc5_cfg_regs.h
@@ -0,0 +1,1226 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_TPC5_CFG_REGS_H_
+#define ASIC_REG_TPC5_CFG_REGS_H_
+
+/*
+ *****************************************
+ *   TPC5_CFG (Prototype: TPC)
+ *****************************************
+ */
+
+#define mmTPC5_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW                     0xF46400
+
+#define mmTPC5_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH                    0xF46404
+
+#define mmTPC5_CFG_KERNEL_TENSOR_0_PADDING_VALUE                     0xF46408
+
+#define mmTPC5_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG                     0xF4640C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_0_SIZE                        0xF46410
+
+#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE                      0xF46414
+
+#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_1_SIZE                        0xF46418
+
+#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE                      0xF4641C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_2_SIZE                        0xF46420
+
+#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE                      0xF46424
+
+#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_3_SIZE                        0xF46428
+
+#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE                      0xF4642C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_4_SIZE                        0xF46430
+
+#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE                      0xF46434
+
+#define mmTPC5_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW                     0xF46438
+
+#define mmTPC5_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH                    0xF4643C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_1_PADDING_VALUE                     0xF46440
+
+#define mmTPC5_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG                     0xF46444
+
+#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_0_SIZE                        0xF46448
+
+#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE                      0xF4644C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_1_SIZE                        0xF46450
+
+#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE                      0xF46454
+
+#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_2_SIZE                        0xF46458
+
+#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE                      0xF4645C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_3_SIZE                        0xF46460
+
+#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE                      0xF46464
+
+#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_4_SIZE                        0xF46468
+
+#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE                      0xF4646C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW                     0xF46470
+
+#define mmTPC5_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH                    0xF46474
+
+#define mmTPC5_CFG_KERNEL_TENSOR_2_PADDING_VALUE                     0xF46478
+
+#define mmTPC5_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG                     0xF4647C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_0_SIZE                        0xF46480
+
+#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE                      0xF46484
+
+#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_1_SIZE                        0xF46488
+
+#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE                      0xF4648C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_2_SIZE                        0xF46490
+
+#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE                      0xF46494
+
+#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_3_SIZE                        0xF46498
+
+#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE                      0xF4649C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_4_SIZE                        0xF464A0
+
+#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE                      0xF464A4
+
+#define mmTPC5_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW                     0xF464A8
+
+#define mmTPC5_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH                    0xF464AC
+
+#define mmTPC5_CFG_KERNEL_TENSOR_3_PADDING_VALUE                     0xF464B0
+
+#define mmTPC5_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG                     0xF464B4
+
+#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_0_SIZE                        0xF464B8
+
+#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE                      0xF464BC
+
+#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_1_SIZE                        0xF464C0
+
+#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE                      0xF464C4
+
+#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_2_SIZE                        0xF464C8
+
+#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE                      0xF464CC
+
+#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_3_SIZE                        0xF464D0
+
+#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE                      0xF464D4
+
+#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_4_SIZE                        0xF464D8
+
+#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE                      0xF464DC
+
+#define mmTPC5_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW                     0xF464E0
+
+#define mmTPC5_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH                    0xF464E4
+
+#define mmTPC5_CFG_KERNEL_TENSOR_4_PADDING_VALUE                     0xF464E8
+
+#define mmTPC5_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG                     0xF464EC
+
+#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_0_SIZE                        0xF464F0
+
+#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE                      0xF464F4
+
+#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_1_SIZE                        0xF464F8
+
+#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE                      0xF464FC
+
+#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_2_SIZE                        0xF46500
+
+#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE                      0xF46504
+
+#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_3_SIZE                        0xF46508
+
+#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE                      0xF4650C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_4_SIZE                        0xF46510
+
+#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE                      0xF46514
+
+#define mmTPC5_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW                     0xF46518
+
+#define mmTPC5_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH                    0xF4651C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_5_PADDING_VALUE                     0xF46520
+
+#define mmTPC5_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG                     0xF46524
+
+#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_0_SIZE                        0xF46528
+
+#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE                      0xF4652C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_1_SIZE                        0xF46530
+
+#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE                      0xF46534
+
+#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_2_SIZE                        0xF46538
+
+#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE                      0xF4653C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_3_SIZE                        0xF46540
+
+#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE                      0xF46544
+
+#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_4_SIZE                        0xF46548
+
+#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE                      0xF4654C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW                     0xF46550
+
+#define mmTPC5_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH                    0xF46554
+
+#define mmTPC5_CFG_KERNEL_TENSOR_6_PADDING_VALUE                     0xF46558
+
+#define mmTPC5_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG                     0xF4655C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_0_SIZE                        0xF46560
+
+#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE                      0xF46564
+
+#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_1_SIZE                        0xF46568
+
+#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE                      0xF4656C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_2_SIZE                        0xF46570
+
+#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE                      0xF46574
+
+#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_3_SIZE                        0xF46578
+
+#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE                      0xF4657C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_4_SIZE                        0xF46580
+
+#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE                      0xF46584
+
+#define mmTPC5_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW                     0xF46588
+
+#define mmTPC5_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH                    0xF4658C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_7_PADDING_VALUE                     0xF46590
+
+#define mmTPC5_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG                     0xF46594
+
+#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_0_SIZE                        0xF46598
+
+#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE                      0xF4659C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_1_SIZE                        0xF465A0
+
+#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE                      0xF465A4
+
+#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_2_SIZE                        0xF465A8
+
+#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE                      0xF465AC
+
+#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_3_SIZE                        0xF465B0
+
+#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE                      0xF465B4
+
+#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_4_SIZE                        0xF465B8
+
+#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE                      0xF465BC
+
+#define mmTPC5_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW                     0xF465C0
+
+#define mmTPC5_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH                    0xF465C4
+
+#define mmTPC5_CFG_KERNEL_TENSOR_8_PADDING_VALUE                     0xF465C8
+
+#define mmTPC5_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG                     0xF465CC
+
+#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_0_SIZE                        0xF465D0
+
+#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE                      0xF465D4
+
+#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_1_SIZE                        0xF465D8
+
+#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE                      0xF465DC
+
+#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_2_SIZE                        0xF465E0
+
+#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE                      0xF465E4
+
+#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_3_SIZE                        0xF465E8
+
+#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE                      0xF465EC
+
+#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_4_SIZE                        0xF465F0
+
+#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE                      0xF465F4
+
+#define mmTPC5_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW                     0xF465F8
+
+#define mmTPC5_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH                    0xF465FC
+
+#define mmTPC5_CFG_KERNEL_TENSOR_9_PADDING_VALUE                     0xF46600
+
+#define mmTPC5_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG                     0xF46604
+
+#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_0_SIZE                        0xF46608
+
+#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE                      0xF4660C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_1_SIZE                        0xF46610
+
+#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE                      0xF46614
+
+#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_2_SIZE                        0xF46618
+
+#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE                      0xF4661C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_3_SIZE                        0xF46620
+
+#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE                      0xF46624
+
+#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_4_SIZE                        0xF46628
+
+#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE                      0xF4662C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW                    0xF46630
+
+#define mmTPC5_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH                   0xF46634
+
+#define mmTPC5_CFG_KERNEL_TENSOR_10_PADDING_VALUE                    0xF46638
+
+#define mmTPC5_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG                    0xF4663C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_0_SIZE                       0xF46640
+
+#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE                     0xF46644
+
+#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_1_SIZE                       0xF46648
+
+#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE                     0xF4664C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_2_SIZE                       0xF46650
+
+#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE                     0xF46654
+
+#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_3_SIZE                       0xF46658
+
+#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE                     0xF4665C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_4_SIZE                       0xF46660
+
+#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE                     0xF46664
+
+#define mmTPC5_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW                    0xF46668
+
+#define mmTPC5_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH                   0xF4666C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_11_PADDING_VALUE                    0xF46670
+
+#define mmTPC5_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG                    0xF46674
+
+#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_0_SIZE                       0xF46678
+
+#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE                     0xF4667C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_1_SIZE                       0xF46680
+
+#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE                     0xF46684
+
+#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_2_SIZE                       0xF46688
+
+#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE                     0xF4668C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_3_SIZE                       0xF46690
+
+#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE                     0xF46694
+
+#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_4_SIZE                       0xF46698
+
+#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE                     0xF4669C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW                    0xF466A0
+
+#define mmTPC5_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH                   0xF466A4
+
+#define mmTPC5_CFG_KERNEL_TENSOR_12_PADDING_VALUE                    0xF466A8
+
+#define mmTPC5_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG                    0xF466AC
+
+#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_0_SIZE                       0xF466B0
+
+#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE                     0xF466B4
+
+#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_1_SIZE                       0xF466B8
+
+#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE                     0xF466BC
+
+#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_2_SIZE                       0xF466C0
+
+#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE                     0xF466C4
+
+#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_3_SIZE                       0xF466C8
+
+#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE                     0xF466CC
+
+#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_4_SIZE                       0xF466D0
+
+#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE                     0xF466D4
+
+#define mmTPC5_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW                    0xF466D8
+
+#define mmTPC5_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH                   0xF466DC
+
+#define mmTPC5_CFG_KERNEL_TENSOR_13_PADDING_VALUE                    0xF466E0
+
+#define mmTPC5_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG                    0xF466E4
+
+#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_0_SIZE                       0xF466E8
+
+#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE                     0xF466EC
+
+#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_1_SIZE                       0xF466F0
+
+#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE                     0xF466F4
+
+#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_2_SIZE                       0xF466F8
+
+#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE                     0xF466FC
+
+#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_3_SIZE                       0xF46700
+
+#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE                     0xF46704
+
+#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_4_SIZE                       0xF46708
+
+#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE                     0xF4670C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW                    0xF46710
+
+#define mmTPC5_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH                   0xF46714
+
+#define mmTPC5_CFG_KERNEL_TENSOR_14_PADDING_VALUE                    0xF46718
+
+#define mmTPC5_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG                    0xF4671C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_0_SIZE                       0xF46720
+
+#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE                     0xF46724
+
+#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_1_SIZE                       0xF46728
+
+#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE                     0xF4672C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_2_SIZE                       0xF46730
+
+#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE                     0xF46734
+
+#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_3_SIZE                       0xF46738
+
+#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE                     0xF4673C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_4_SIZE                       0xF46740
+
+#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE                     0xF46744
+
+#define mmTPC5_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW                    0xF46748
+
+#define mmTPC5_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH                   0xF4674C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_15_PADDING_VALUE                    0xF46750
+
+#define mmTPC5_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG                    0xF46754
+
+#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_0_SIZE                       0xF46758
+
+#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE                     0xF4675C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_1_SIZE                       0xF46760
+
+#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE                     0xF46764
+
+#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_2_SIZE                       0xF46768
+
+#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE                     0xF4676C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_3_SIZE                       0xF46770
+
+#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE                     0xF46774
+
+#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_4_SIZE                       0xF46778
+
+#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE                     0xF4677C
+
+#define mmTPC5_CFG_KERNEL_SYNC_OBJECT_MESSAGE                        0xF46780
+
+#define mmTPC5_CFG_KERNEL_SYNC_OBJECT_ADDR                           0xF46784
+
+#define mmTPC5_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW                    0xF46788
+
+#define mmTPC5_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH                   0xF4678C
+
+#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_0                             0xF46790
+
+#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_0                             0xF46794
+
+#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_1                             0xF46798
+
+#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_1                             0xF4679C
+
+#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_2                             0xF467A0
+
+#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_2                             0xF467A4
+
+#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_3                             0xF467A8
+
+#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_3                             0xF467AC
+
+#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_4                             0xF467B0
+
+#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_4                             0xF467B4
+
+#define mmTPC5_CFG_KERNEL_KERNEL_CONFIG                              0xF467B8
+
+#define mmTPC5_CFG_KERNEL_KERNEL_ID                                  0xF467BC
+
+#define mmTPC5_CFG_KERNEL_SRF_0                                      0xF467C0
+
+#define mmTPC5_CFG_KERNEL_SRF_1                                      0xF467C4
+
+#define mmTPC5_CFG_KERNEL_SRF_2                                      0xF467C8
+
+#define mmTPC5_CFG_KERNEL_SRF_3                                      0xF467CC
+
+#define mmTPC5_CFG_KERNEL_SRF_4                                      0xF467D0
+
+#define mmTPC5_CFG_KERNEL_SRF_5                                      0xF467D4
+
+#define mmTPC5_CFG_KERNEL_SRF_6                                      0xF467D8
+
+#define mmTPC5_CFG_KERNEL_SRF_7                                      0xF467DC
+
+#define mmTPC5_CFG_KERNEL_SRF_8                                      0xF467E0
+
+#define mmTPC5_CFG_KERNEL_SRF_9                                      0xF467E4
+
+#define mmTPC5_CFG_KERNEL_SRF_10                                     0xF467E8
+
+#define mmTPC5_CFG_KERNEL_SRF_11                                     0xF467EC
+
+#define mmTPC5_CFG_KERNEL_SRF_12                                     0xF467F0
+
+#define mmTPC5_CFG_KERNEL_SRF_13                                     0xF467F4
+
+#define mmTPC5_CFG_KERNEL_SRF_14                                     0xF467F8
+
+#define mmTPC5_CFG_KERNEL_SRF_15                                     0xF467FC
+
+#define mmTPC5_CFG_KERNEL_SRF_16                                     0xF46800
+
+#define mmTPC5_CFG_KERNEL_SRF_17                                     0xF46804
+
+#define mmTPC5_CFG_KERNEL_SRF_18                                     0xF46808
+
+#define mmTPC5_CFG_KERNEL_SRF_19                                     0xF4680C
+
+#define mmTPC5_CFG_KERNEL_SRF_20                                     0xF46810
+
+#define mmTPC5_CFG_KERNEL_SRF_21                                     0xF46814
+
+#define mmTPC5_CFG_KERNEL_SRF_22                                     0xF46818
+
+#define mmTPC5_CFG_KERNEL_SRF_23                                     0xF4681C
+
+#define mmTPC5_CFG_KERNEL_SRF_24                                     0xF46820
+
+#define mmTPC5_CFG_KERNEL_SRF_25                                     0xF46824
+
+#define mmTPC5_CFG_KERNEL_SRF_26                                     0xF46828
+
+#define mmTPC5_CFG_KERNEL_SRF_27                                     0xF4682C
+
+#define mmTPC5_CFG_KERNEL_SRF_28                                     0xF46830
+
+#define mmTPC5_CFG_KERNEL_SRF_29                                     0xF46834
+
+#define mmTPC5_CFG_KERNEL_SRF_30                                     0xF46838
+
+#define mmTPC5_CFG_KERNEL_SRF_31                                     0xF4683C
+
+#define mmTPC5_CFG_ROUND_CSR                                         0xF468FC
+
+#define mmTPC5_CFG_PROT                                              0xF46900
+
+#define mmTPC5_CFG_SEMAPHORE                                         0xF46908
+
+#define mmTPC5_CFG_VFLAGS                                            0xF4690C
+
+#define mmTPC5_CFG_SFLAGS                                            0xF46910
+
+#define mmTPC5_CFG_LFSR_POLYNOM                                      0xF46918
+
+#define mmTPC5_CFG_STATUS                                            0xF4691C
+
+#define mmTPC5_CFG_CFG_BASE_ADDRESS_HIGH                             0xF46920
+
+#define mmTPC5_CFG_CFG_SUBTRACT_VALUE                                0xF46924
+
+#define mmTPC5_CFG_SM_BASE_ADDRESS_HIGH                              0xF4692C
+
+#define mmTPC5_CFG_TPC_CMD                                           0xF46930
+
+#define mmTPC5_CFG_TPC_EXECUTE                                       0xF46938
+
+#define mmTPC5_CFG_TPC_STALL                                         0xF4693C
+
+#define mmTPC5_CFG_ICACHE_BASE_ADDERESS_LOW                          0xF46940
+
+#define mmTPC5_CFG_ICACHE_BASE_ADDERESS_HIGH                         0xF46944
+
+#define mmTPC5_CFG_RD_RATE_LIMIT                                     0xF46948
+
+#define mmTPC5_CFG_WR_RATE_LIMIT                                     0xF46950
+
+#define mmTPC5_CFG_MSS_CONFIG                                        0xF46954
+
+#define mmTPC5_CFG_TPC_INTR_CAUSE                                    0xF46958
+
+#define mmTPC5_CFG_TPC_INTR_MASK                                     0xF4695C
+
+#define mmTPC5_CFG_WQ_CREDITS                                        0xF46960
+
+#define mmTPC5_CFG_ARUSER_LO                                         0xF46964
+
+#define mmTPC5_CFG_ARUSER_HI                                         0xF46968
+
+#define mmTPC5_CFG_AWUSER_LO                                         0xF4696C
+
+#define mmTPC5_CFG_AWUSER_HI                                         0xF46970
+
+#define mmTPC5_CFG_OPCODE_EXEC                                       0xF46974
+
+#define mmTPC5_CFG_LUT_FUNC32_BASE_ADDR_LO                           0xF46978
+
+#define mmTPC5_CFG_LUT_FUNC32_BASE_ADDR_HI                           0xF4697C
+
+#define mmTPC5_CFG_LUT_FUNC64_BASE_ADDR_LO                           0xF46980
+
+#define mmTPC5_CFG_LUT_FUNC64_BASE_ADDR_HI                           0xF46984
+
+#define mmTPC5_CFG_LUT_FUNC128_BASE_ADDR_LO                          0xF46988
+
+#define mmTPC5_CFG_LUT_FUNC128_BASE_ADDR_HI                          0xF4698C
+
+#define mmTPC5_CFG_LUT_FUNC256_BASE_ADDR_LO                          0xF46990
+
+#define mmTPC5_CFG_LUT_FUNC256_BASE_ADDR_HI                          0xF46994
+
+#define mmTPC5_CFG_TSB_CFG_MAX_SIZE                                  0xF46998
+
+#define mmTPC5_CFG_TSB_CFG                                           0xF4699C
+
+#define mmTPC5_CFG_DBGMEM_ADD                                        0xF469A0
+
+#define mmTPC5_CFG_DBGMEM_DATA_WR                                    0xF469A4
+
+#define mmTPC5_CFG_DBGMEM_DATA_RD                                    0xF469A8
+
+#define mmTPC5_CFG_DBGMEM_CTRL                                       0xF469AC
+
+#define mmTPC5_CFG_DBGMEM_RC                                         0xF469B0
+
+#define mmTPC5_CFG_TSB_INFLIGHT_CNTR                                 0xF469B4
+
+#define mmTPC5_CFG_WQ_INFLIGHT_CNTR                                  0xF469B8
+
+#define mmTPC5_CFG_WQ_LBW_TOTAL_CNTR                                 0xF469BC
+
+#define mmTPC5_CFG_WQ_HBW_TOTAL_CNTR                                 0xF469C0
+
+#define mmTPC5_CFG_IRQ_OCCOUPY_CNTR                                  0xF469C4
+
+#define mmTPC5_CFG_FUNC_MBIST_CNTRL                                  0xF469D0
+
+#define mmTPC5_CFG_FUNC_MBIST_PAT                                    0xF469D4
+
+#define mmTPC5_CFG_FUNC_MBIST_MEM_0                                  0xF469D8
+
+#define mmTPC5_CFG_FUNC_MBIST_MEM_1                                  0xF469DC
+
+#define mmTPC5_CFG_FUNC_MBIST_MEM_2                                  0xF469E0
+
+#define mmTPC5_CFG_FUNC_MBIST_MEM_3                                  0xF469E4
+
+#define mmTPC5_CFG_FUNC_MBIST_MEM_4                                  0xF469E8
+
+#define mmTPC5_CFG_FUNC_MBIST_MEM_5                                  0xF469EC
+
+#define mmTPC5_CFG_FUNC_MBIST_MEM_6                                  0xF469F0
+
+#define mmTPC5_CFG_FUNC_MBIST_MEM_7                                  0xF469F4
+
+#define mmTPC5_CFG_FUNC_MBIST_MEM_8                                  0xF469F8
+
+#define mmTPC5_CFG_FUNC_MBIST_MEM_9                                  0xF469FC
+
+#define mmTPC5_CFG_QM_TENSOR_0_BASE_ADDR_LOW                         0xF46A00
+
+#define mmTPC5_CFG_QM_TENSOR_0_BASE_ADDR_HIGH                        0xF46A04
+
+#define mmTPC5_CFG_QM_TENSOR_0_PADDING_VALUE                         0xF46A08
+
+#define mmTPC5_CFG_QM_TENSOR_0_TENSOR_CONFIG                         0xF46A0C
+
+#define mmTPC5_CFG_QM_TENSOR_0_DIM_0_SIZE                            0xF46A10
+
+#define mmTPC5_CFG_QM_TENSOR_0_DIM_0_STRIDE                          0xF46A14
+
+#define mmTPC5_CFG_QM_TENSOR_0_DIM_1_SIZE                            0xF46A18
+
+#define mmTPC5_CFG_QM_TENSOR_0_DIM_1_STRIDE                          0xF46A1C
+
+#define mmTPC5_CFG_QM_TENSOR_0_DIM_2_SIZE                            0xF46A20
+
+#define mmTPC5_CFG_QM_TENSOR_0_DIM_2_STRIDE                          0xF46A24
+
+#define mmTPC5_CFG_QM_TENSOR_0_DIM_3_SIZE                            0xF46A28
+
+#define mmTPC5_CFG_QM_TENSOR_0_DIM_3_STRIDE                          0xF46A2C
+
+#define mmTPC5_CFG_QM_TENSOR_0_DIM_4_SIZE                            0xF46A30
+
+#define mmTPC5_CFG_QM_TENSOR_0_DIM_4_STRIDE                          0xF46A34
+
+#define mmTPC5_CFG_QM_TENSOR_1_BASE_ADDR_LOW                         0xF46A38
+
+#define mmTPC5_CFG_QM_TENSOR_1_BASE_ADDR_HIGH                        0xF46A3C
+
+#define mmTPC5_CFG_QM_TENSOR_1_PADDING_VALUE                         0xF46A40
+
+#define mmTPC5_CFG_QM_TENSOR_1_TENSOR_CONFIG                         0xF46A44
+
+#define mmTPC5_CFG_QM_TENSOR_1_DIM_0_SIZE                            0xF46A48
+
+#define mmTPC5_CFG_QM_TENSOR_1_DIM_0_STRIDE                          0xF46A4C
+
+#define mmTPC5_CFG_QM_TENSOR_1_DIM_1_SIZE                            0xF46A50
+
+#define mmTPC5_CFG_QM_TENSOR_1_DIM_1_STRIDE                          0xF46A54
+
+#define mmTPC5_CFG_QM_TENSOR_1_DIM_2_SIZE                            0xF46A58
+
+#define mmTPC5_CFG_QM_TENSOR_1_DIM_2_STRIDE                          0xF46A5C
+
+#define mmTPC5_CFG_QM_TENSOR_1_DIM_3_SIZE                            0xF46A60
+
+#define mmTPC5_CFG_QM_TENSOR_1_DIM_3_STRIDE                          0xF46A64
+
+#define mmTPC5_CFG_QM_TENSOR_1_DIM_4_SIZE                            0xF46A68
+
+#define mmTPC5_CFG_QM_TENSOR_1_DIM_4_STRIDE                          0xF46A6C
+
+#define mmTPC5_CFG_QM_TENSOR_2_BASE_ADDR_LOW                         0xF46A70
+
+#define mmTPC5_CFG_QM_TENSOR_2_BASE_ADDR_HIGH                        0xF46A74
+
+#define mmTPC5_CFG_QM_TENSOR_2_PADDING_VALUE                         0xF46A78
+
+#define mmTPC5_CFG_QM_TENSOR_2_TENSOR_CONFIG                         0xF46A7C
+
+#define mmTPC5_CFG_QM_TENSOR_2_DIM_0_SIZE                            0xF46A80
+
+#define mmTPC5_CFG_QM_TENSOR_2_DIM_0_STRIDE                          0xF46A84
+
+#define mmTPC5_CFG_QM_TENSOR_2_DIM_1_SIZE                            0xF46A88
+
+#define mmTPC5_CFG_QM_TENSOR_2_DIM_1_STRIDE                          0xF46A8C
+
+#define mmTPC5_CFG_QM_TENSOR_2_DIM_2_SIZE                            0xF46A90
+
+#define mmTPC5_CFG_QM_TENSOR_2_DIM_2_STRIDE                          0xF46A94
+
+#define mmTPC5_CFG_QM_TENSOR_2_DIM_3_SIZE                            0xF46A98
+
+#define mmTPC5_CFG_QM_TENSOR_2_DIM_3_STRIDE                          0xF46A9C
+
+#define mmTPC5_CFG_QM_TENSOR_2_DIM_4_SIZE                            0xF46AA0
+
+#define mmTPC5_CFG_QM_TENSOR_2_DIM_4_STRIDE                          0xF46AA4
+
+#define mmTPC5_CFG_QM_TENSOR_3_BASE_ADDR_LOW                         0xF46AA8
+
+#define mmTPC5_CFG_QM_TENSOR_3_BASE_ADDR_HIGH                        0xF46AAC
+
+#define mmTPC5_CFG_QM_TENSOR_3_PADDING_VALUE                         0xF46AB0
+
+#define mmTPC5_CFG_QM_TENSOR_3_TENSOR_CONFIG                         0xF46AB4
+
+#define mmTPC5_CFG_QM_TENSOR_3_DIM_0_SIZE                            0xF46AB8
+
+#define mmTPC5_CFG_QM_TENSOR_3_DIM_0_STRIDE                          0xF46ABC
+
+#define mmTPC5_CFG_QM_TENSOR_3_DIM_1_SIZE                            0xF46AC0
+
+#define mmTPC5_CFG_QM_TENSOR_3_DIM_1_STRIDE                          0xF46AC4
+
+#define mmTPC5_CFG_QM_TENSOR_3_DIM_2_SIZE                            0xF46AC8
+
+#define mmTPC5_CFG_QM_TENSOR_3_DIM_2_STRIDE                          0xF46ACC
+
+#define mmTPC5_CFG_QM_TENSOR_3_DIM_3_SIZE                            0xF46AD0
+
+#define mmTPC5_CFG_QM_TENSOR_3_DIM_3_STRIDE                          0xF46AD4
+
+#define mmTPC5_CFG_QM_TENSOR_3_DIM_4_SIZE                            0xF46AD8
+
+#define mmTPC5_CFG_QM_TENSOR_3_DIM_4_STRIDE                          0xF46ADC
+
+#define mmTPC5_CFG_QM_TENSOR_4_BASE_ADDR_LOW                         0xF46AE0
+
+#define mmTPC5_CFG_QM_TENSOR_4_BASE_ADDR_HIGH                        0xF46AE4
+
+#define mmTPC5_CFG_QM_TENSOR_4_PADDING_VALUE                         0xF46AE8
+
+#define mmTPC5_CFG_QM_TENSOR_4_TENSOR_CONFIG                         0xF46AEC
+
+#define mmTPC5_CFG_QM_TENSOR_4_DIM_0_SIZE                            0xF46AF0
+
+#define mmTPC5_CFG_QM_TENSOR_4_DIM_0_STRIDE                          0xF46AF4
+
+#define mmTPC5_CFG_QM_TENSOR_4_DIM_1_SIZE                            0xF46AF8
+
+#define mmTPC5_CFG_QM_TENSOR_4_DIM_1_STRIDE                          0xF46AFC
+
+#define mmTPC5_CFG_QM_TENSOR_4_DIM_2_SIZE                            0xF46B00
+
+#define mmTPC5_CFG_QM_TENSOR_4_DIM_2_STRIDE                          0xF46B04
+
+#define mmTPC5_CFG_QM_TENSOR_4_DIM_3_SIZE                            0xF46B08
+
+#define mmTPC5_CFG_QM_TENSOR_4_DIM_3_STRIDE                          0xF46B0C
+
+#define mmTPC5_CFG_QM_TENSOR_4_DIM_4_SIZE                            0xF46B10
+
+#define mmTPC5_CFG_QM_TENSOR_4_DIM_4_STRIDE                          0xF46B14
+
+#define mmTPC5_CFG_QM_TENSOR_5_BASE_ADDR_LOW                         0xF46B18
+
+#define mmTPC5_CFG_QM_TENSOR_5_BASE_ADDR_HIGH                        0xF46B1C
+
+#define mmTPC5_CFG_QM_TENSOR_5_PADDING_VALUE                         0xF46B20
+
+#define mmTPC5_CFG_QM_TENSOR_5_TENSOR_CONFIG                         0xF46B24
+
+#define mmTPC5_CFG_QM_TENSOR_5_DIM_0_SIZE                            0xF46B28
+
+#define mmTPC5_CFG_QM_TENSOR_5_DIM_0_STRIDE                          0xF46B2C
+
+#define mmTPC5_CFG_QM_TENSOR_5_DIM_1_SIZE                            0xF46B30
+
+#define mmTPC5_CFG_QM_TENSOR_5_DIM_1_STRIDE                          0xF46B34
+
+#define mmTPC5_CFG_QM_TENSOR_5_DIM_2_SIZE                            0xF46B38
+
+#define mmTPC5_CFG_QM_TENSOR_5_DIM_2_STRIDE                          0xF46B3C
+
+#define mmTPC5_CFG_QM_TENSOR_5_DIM_3_SIZE                            0xF46B40
+
+#define mmTPC5_CFG_QM_TENSOR_5_DIM_3_STRIDE                          0xF46B44
+
+#define mmTPC5_CFG_QM_TENSOR_5_DIM_4_SIZE                            0xF46B48
+
+#define mmTPC5_CFG_QM_TENSOR_5_DIM_4_STRIDE                          0xF46B4C
+
+#define mmTPC5_CFG_QM_TENSOR_6_BASE_ADDR_LOW                         0xF46B50
+
+#define mmTPC5_CFG_QM_TENSOR_6_BASE_ADDR_HIGH                        0xF46B54
+
+#define mmTPC5_CFG_QM_TENSOR_6_PADDING_VALUE                         0xF46B58
+
+#define mmTPC5_CFG_QM_TENSOR_6_TENSOR_CONFIG                         0xF46B5C
+
+#define mmTPC5_CFG_QM_TENSOR_6_DIM_0_SIZE                            0xF46B60
+
+#define mmTPC5_CFG_QM_TENSOR_6_DIM_0_STRIDE                          0xF46B64
+
+#define mmTPC5_CFG_QM_TENSOR_6_DIM_1_SIZE                            0xF46B68
+
+#define mmTPC5_CFG_QM_TENSOR_6_DIM_1_STRIDE                          0xF46B6C
+
+#define mmTPC5_CFG_QM_TENSOR_6_DIM_2_SIZE                            0xF46B70
+
+#define mmTPC5_CFG_QM_TENSOR_6_DIM_2_STRIDE                          0xF46B74
+
+#define mmTPC5_CFG_QM_TENSOR_6_DIM_3_SIZE                            0xF46B78
+
+#define mmTPC5_CFG_QM_TENSOR_6_DIM_3_STRIDE                          0xF46B7C
+
+#define mmTPC5_CFG_QM_TENSOR_6_DIM_4_SIZE                            0xF46B80
+
+#define mmTPC5_CFG_QM_TENSOR_6_DIM_4_STRIDE                          0xF46B84
+
+#define mmTPC5_CFG_QM_TENSOR_7_BASE_ADDR_LOW                         0xF46B88
+
+#define mmTPC5_CFG_QM_TENSOR_7_BASE_ADDR_HIGH                        0xF46B8C
+
+#define mmTPC5_CFG_QM_TENSOR_7_PADDING_VALUE                         0xF46B90
+
+#define mmTPC5_CFG_QM_TENSOR_7_TENSOR_CONFIG                         0xF46B94
+
+#define mmTPC5_CFG_QM_TENSOR_7_DIM_0_SIZE                            0xF46B98
+
+#define mmTPC5_CFG_QM_TENSOR_7_DIM_0_STRIDE                          0xF46B9C
+
+#define mmTPC5_CFG_QM_TENSOR_7_DIM_1_SIZE                            0xF46BA0
+
+#define mmTPC5_CFG_QM_TENSOR_7_DIM_1_STRIDE                          0xF46BA4
+
+#define mmTPC5_CFG_QM_TENSOR_7_DIM_2_SIZE                            0xF46BA8
+
+#define mmTPC5_CFG_QM_TENSOR_7_DIM_2_STRIDE                          0xF46BAC
+
+#define mmTPC5_CFG_QM_TENSOR_7_DIM_3_SIZE                            0xF46BB0
+
+#define mmTPC5_CFG_QM_TENSOR_7_DIM_3_STRIDE                          0xF46BB4
+
+#define mmTPC5_CFG_QM_TENSOR_7_DIM_4_SIZE                            0xF46BB8
+
+#define mmTPC5_CFG_QM_TENSOR_7_DIM_4_STRIDE                          0xF46BBC
+
+#define mmTPC5_CFG_QM_TENSOR_8_BASE_ADDR_LOW                         0xF46BC0
+
+#define mmTPC5_CFG_QM_TENSOR_8_BASE_ADDR_HIGH                        0xF46BC4
+
+#define mmTPC5_CFG_QM_TENSOR_8_PADDING_VALUE                         0xF46BC8
+
+#define mmTPC5_CFG_QM_TENSOR_8_TENSOR_CONFIG                         0xF46BCC
+
+#define mmTPC5_CFG_QM_TENSOR_8_DIM_0_SIZE                            0xF46BD0
+
+#define mmTPC5_CFG_QM_TENSOR_8_DIM_0_STRIDE                          0xF46BD4
+
+#define mmTPC5_CFG_QM_TENSOR_8_DIM_1_SIZE                            0xF46BD8
+
+#define mmTPC5_CFG_QM_TENSOR_8_DIM_1_STRIDE                          0xF46BDC
+
+#define mmTPC5_CFG_QM_TENSOR_8_DIM_2_SIZE                            0xF46BE0
+
+#define mmTPC5_CFG_QM_TENSOR_8_DIM_2_STRIDE                          0xF46BE4
+
+#define mmTPC5_CFG_QM_TENSOR_8_DIM_3_SIZE                            0xF46BE8
+
+#define mmTPC5_CFG_QM_TENSOR_8_DIM_3_STRIDE                          0xF46BEC
+
+#define mmTPC5_CFG_QM_TENSOR_8_DIM_4_SIZE                            0xF46BF0
+
+#define mmTPC5_CFG_QM_TENSOR_8_DIM_4_STRIDE                          0xF46BF4
+
+#define mmTPC5_CFG_QM_TENSOR_9_BASE_ADDR_LOW                         0xF46BF8
+
+#define mmTPC5_CFG_QM_TENSOR_9_BASE_ADDR_HIGH                        0xF46BFC
+
+#define mmTPC5_CFG_QM_TENSOR_9_PADDING_VALUE                         0xF46C00
+
+#define mmTPC5_CFG_QM_TENSOR_9_TENSOR_CONFIG                         0xF46C04
+
+#define mmTPC5_CFG_QM_TENSOR_9_DIM_0_SIZE                            0xF46C08
+
+#define mmTPC5_CFG_QM_TENSOR_9_DIM_0_STRIDE                          0xF46C0C
+
+#define mmTPC5_CFG_QM_TENSOR_9_DIM_1_SIZE                            0xF46C10
+
+#define mmTPC5_CFG_QM_TENSOR_9_DIM_1_STRIDE                          0xF46C14
+
+#define mmTPC5_CFG_QM_TENSOR_9_DIM_2_SIZE                            0xF46C18
+
+#define mmTPC5_CFG_QM_TENSOR_9_DIM_2_STRIDE                          0xF46C1C
+
+#define mmTPC5_CFG_QM_TENSOR_9_DIM_3_SIZE                            0xF46C20
+
+#define mmTPC5_CFG_QM_TENSOR_9_DIM_3_STRIDE                          0xF46C24
+
+#define mmTPC5_CFG_QM_TENSOR_9_DIM_4_SIZE                            0xF46C28
+
+#define mmTPC5_CFG_QM_TENSOR_9_DIM_4_STRIDE                          0xF46C2C
+
+#define mmTPC5_CFG_QM_TENSOR_10_BASE_ADDR_LOW                        0xF46C30
+
+#define mmTPC5_CFG_QM_TENSOR_10_BASE_ADDR_HIGH                       0xF46C34
+
+#define mmTPC5_CFG_QM_TENSOR_10_PADDING_VALUE                        0xF46C38
+
+#define mmTPC5_CFG_QM_TENSOR_10_TENSOR_CONFIG                        0xF46C3C
+
+#define mmTPC5_CFG_QM_TENSOR_10_DIM_0_SIZE                           0xF46C40
+
+#define mmTPC5_CFG_QM_TENSOR_10_DIM_0_STRIDE                         0xF46C44
+
+#define mmTPC5_CFG_QM_TENSOR_10_DIM_1_SIZE                           0xF46C48
+
+#define mmTPC5_CFG_QM_TENSOR_10_DIM_1_STRIDE                         0xF46C4C
+
+#define mmTPC5_CFG_QM_TENSOR_10_DIM_2_SIZE                           0xF46C50
+
+#define mmTPC5_CFG_QM_TENSOR_10_DIM_2_STRIDE                         0xF46C54
+
+#define mmTPC5_CFG_QM_TENSOR_10_DIM_3_SIZE                           0xF46C58
+
+#define mmTPC5_CFG_QM_TENSOR_10_DIM_3_STRIDE                         0xF46C5C
+
+#define mmTPC5_CFG_QM_TENSOR_10_DIM_4_SIZE                           0xF46C60
+
+#define mmTPC5_CFG_QM_TENSOR_10_DIM_4_STRIDE                         0xF46C64
+
+#define mmTPC5_CFG_QM_TENSOR_11_BASE_ADDR_LOW                        0xF46C68
+
+#define mmTPC5_CFG_QM_TENSOR_11_BASE_ADDR_HIGH                       0xF46C6C
+
+#define mmTPC5_CFG_QM_TENSOR_11_PADDING_VALUE                        0xF46C70
+
+#define mmTPC5_CFG_QM_TENSOR_11_TENSOR_CONFIG                        0xF46C74
+
+#define mmTPC5_CFG_QM_TENSOR_11_DIM_0_SIZE                           0xF46C78
+
+#define mmTPC5_CFG_QM_TENSOR_11_DIM_0_STRIDE                         0xF46C7C
+
+#define mmTPC5_CFG_QM_TENSOR_11_DIM_1_SIZE                           0xF46C80
+
+#define mmTPC5_CFG_QM_TENSOR_11_DIM_1_STRIDE                         0xF46C84
+
+#define mmTPC5_CFG_QM_TENSOR_11_DIM_2_SIZE                           0xF46C88
+
+#define mmTPC5_CFG_QM_TENSOR_11_DIM_2_STRIDE                         0xF46C8C
+
+#define mmTPC5_CFG_QM_TENSOR_11_DIM_3_SIZE                           0xF46C90
+
+#define mmTPC5_CFG_QM_TENSOR_11_DIM_3_STRIDE                         0xF46C94
+
+#define mmTPC5_CFG_QM_TENSOR_11_DIM_4_SIZE                           0xF46C98
+
+#define mmTPC5_CFG_QM_TENSOR_11_DIM_4_STRIDE                         0xF46C9C
+
+#define mmTPC5_CFG_QM_TENSOR_12_BASE_ADDR_LOW                        0xF46CA0
+
+#define mmTPC5_CFG_QM_TENSOR_12_BASE_ADDR_HIGH                       0xF46CA4
+
+#define mmTPC5_CFG_QM_TENSOR_12_PADDING_VALUE                        0xF46CA8
+
+#define mmTPC5_CFG_QM_TENSOR_12_TENSOR_CONFIG                        0xF46CAC
+
+#define mmTPC5_CFG_QM_TENSOR_12_DIM_0_SIZE                           0xF46CB0
+
+#define mmTPC5_CFG_QM_TENSOR_12_DIM_0_STRIDE                         0xF46CB4
+
+#define mmTPC5_CFG_QM_TENSOR_12_DIM_1_SIZE                           0xF46CB8
+
+#define mmTPC5_CFG_QM_TENSOR_12_DIM_1_STRIDE                         0xF46CBC
+
+#define mmTPC5_CFG_QM_TENSOR_12_DIM_2_SIZE                           0xF46CC0
+
+#define mmTPC5_CFG_QM_TENSOR_12_DIM_2_STRIDE                         0xF46CC4
+
+#define mmTPC5_CFG_QM_TENSOR_12_DIM_3_SIZE                           0xF46CC8
+
+#define mmTPC5_CFG_QM_TENSOR_12_DIM_3_STRIDE                         0xF46CCC
+
+#define mmTPC5_CFG_QM_TENSOR_12_DIM_4_SIZE                           0xF46CD0
+
+#define mmTPC5_CFG_QM_TENSOR_12_DIM_4_STRIDE                         0xF46CD4
+
+#define mmTPC5_CFG_QM_TENSOR_13_BASE_ADDR_LOW                        0xF46CD8
+
+#define mmTPC5_CFG_QM_TENSOR_13_BASE_ADDR_HIGH                       0xF46CDC
+
+#define mmTPC5_CFG_QM_TENSOR_13_PADDING_VALUE                        0xF46CE0
+
+#define mmTPC5_CFG_QM_TENSOR_13_TENSOR_CONFIG                        0xF46CE4
+
+#define mmTPC5_CFG_QM_TENSOR_13_DIM_0_SIZE                           0xF46CE8
+
+#define mmTPC5_CFG_QM_TENSOR_13_DIM_0_STRIDE                         0xF46CEC
+
+#define mmTPC5_CFG_QM_TENSOR_13_DIM_1_SIZE                           0xF46CF0
+
+#define mmTPC5_CFG_QM_TENSOR_13_DIM_1_STRIDE                         0xF46CF4
+
+#define mmTPC5_CFG_QM_TENSOR_13_DIM_2_SIZE                           0xF46CF8
+
+#define mmTPC5_CFG_QM_TENSOR_13_DIM_2_STRIDE                         0xF46CFC
+
+#define mmTPC5_CFG_QM_TENSOR_13_DIM_3_SIZE                           0xF46D00
+
+#define mmTPC5_CFG_QM_TENSOR_13_DIM_3_STRIDE                         0xF46D04
+
+#define mmTPC5_CFG_QM_TENSOR_13_DIM_4_SIZE                           0xF46D08
+
+#define mmTPC5_CFG_QM_TENSOR_13_DIM_4_STRIDE                         0xF46D0C
+
+#define mmTPC5_CFG_QM_TENSOR_14_BASE_ADDR_LOW                        0xF46D10
+
+#define mmTPC5_CFG_QM_TENSOR_14_BASE_ADDR_HIGH                       0xF46D14
+
+#define mmTPC5_CFG_QM_TENSOR_14_PADDING_VALUE                        0xF46D18
+
+#define mmTPC5_CFG_QM_TENSOR_14_TENSOR_CONFIG                        0xF46D1C
+
+#define mmTPC5_CFG_QM_TENSOR_14_DIM_0_SIZE                           0xF46D20
+
+#define mmTPC5_CFG_QM_TENSOR_14_DIM_0_STRIDE                         0xF46D24
+
+#define mmTPC5_CFG_QM_TENSOR_14_DIM_1_SIZE                           0xF46D28
+
+#define mmTPC5_CFG_QM_TENSOR_14_DIM_1_STRIDE                         0xF46D2C
+
+#define mmTPC5_CFG_QM_TENSOR_14_DIM_2_SIZE                           0xF46D30
+
+#define mmTPC5_CFG_QM_TENSOR_14_DIM_2_STRIDE                         0xF46D34
+
+#define mmTPC5_CFG_QM_TENSOR_14_DIM_3_SIZE                           0xF46D38
+
+#define mmTPC5_CFG_QM_TENSOR_14_DIM_3_STRIDE                         0xF46D3C
+
+#define mmTPC5_CFG_QM_TENSOR_14_DIM_4_SIZE                           0xF46D40
+
+#define mmTPC5_CFG_QM_TENSOR_14_DIM_4_STRIDE                         0xF46D44
+
+#define mmTPC5_CFG_QM_TENSOR_15_BASE_ADDR_LOW                        0xF46D48
+
+#define mmTPC5_CFG_QM_TENSOR_15_BASE_ADDR_HIGH                       0xF46D4C
+
+#define mmTPC5_CFG_QM_TENSOR_15_PADDING_VALUE                        0xF46D50
+
+#define mmTPC5_CFG_QM_TENSOR_15_TENSOR_CONFIG                        0xF46D54
+
+#define mmTPC5_CFG_QM_TENSOR_15_DIM_0_SIZE                           0xF46D58
+
+#define mmTPC5_CFG_QM_TENSOR_15_DIM_0_STRIDE                         0xF46D5C
+
+#define mmTPC5_CFG_QM_TENSOR_15_DIM_1_SIZE                           0xF46D60
+
+#define mmTPC5_CFG_QM_TENSOR_15_DIM_1_STRIDE                         0xF46D64
+
+#define mmTPC5_CFG_QM_TENSOR_15_DIM_2_SIZE                           0xF46D68
+
+#define mmTPC5_CFG_QM_TENSOR_15_DIM_2_STRIDE                         0xF46D6C
+
+#define mmTPC5_CFG_QM_TENSOR_15_DIM_3_SIZE                           0xF46D70
+
+#define mmTPC5_CFG_QM_TENSOR_15_DIM_3_STRIDE                         0xF46D74
+
+#define mmTPC5_CFG_QM_TENSOR_15_DIM_4_SIZE                           0xF46D78
+
+#define mmTPC5_CFG_QM_TENSOR_15_DIM_4_STRIDE                         0xF46D7C
+
+#define mmTPC5_CFG_QM_SYNC_OBJECT_MESSAGE                            0xF46D80
+
+#define mmTPC5_CFG_QM_SYNC_OBJECT_ADDR                               0xF46D84
+
+#define mmTPC5_CFG_QM_KERNEL_BASE_ADDRESS_LOW                        0xF46D88
+
+#define mmTPC5_CFG_QM_KERNEL_BASE_ADDRESS_HIGH                       0xF46D8C
+
+#define mmTPC5_CFG_QM_TID_BASE_DIM_0                                 0xF46D90
+
+#define mmTPC5_CFG_QM_TID_SIZE_DIM_0                                 0xF46D94
+
+#define mmTPC5_CFG_QM_TID_BASE_DIM_1                                 0xF46D98
+
+#define mmTPC5_CFG_QM_TID_SIZE_DIM_1                                 0xF46D9C
+
+#define mmTPC5_CFG_QM_TID_BASE_DIM_2                                 0xF46DA0
+
+#define mmTPC5_CFG_QM_TID_SIZE_DIM_2                                 0xF46DA4
+
+#define mmTPC5_CFG_QM_TID_BASE_DIM_3                                 0xF46DA8
+
+#define mmTPC5_CFG_QM_TID_SIZE_DIM_3                                 0xF46DAC
+
+#define mmTPC5_CFG_QM_TID_BASE_DIM_4                                 0xF46DB0
+
+#define mmTPC5_CFG_QM_TID_SIZE_DIM_4                                 0xF46DB4
+
+#define mmTPC5_CFG_QM_KERNEL_CONFIG                                  0xF46DB8
+
+#define mmTPC5_CFG_QM_KERNEL_ID                                      0xF46DBC
+
+#define mmTPC5_CFG_QM_SRF_0                                          0xF46DC0
+
+#define mmTPC5_CFG_QM_SRF_1                                          0xF46DC4
+
+#define mmTPC5_CFG_QM_SRF_2                                          0xF46DC8
+
+#define mmTPC5_CFG_QM_SRF_3                                          0xF46DCC
+
+#define mmTPC5_CFG_QM_SRF_4                                          0xF46DD0
+
+#define mmTPC5_CFG_QM_SRF_5                                          0xF46DD4
+
+#define mmTPC5_CFG_QM_SRF_6                                          0xF46DD8
+
+#define mmTPC5_CFG_QM_SRF_7                                          0xF46DDC
+
+#define mmTPC5_CFG_QM_SRF_8                                          0xF46DE0
+
+#define mmTPC5_CFG_QM_SRF_9                                          0xF46DE4
+
+#define mmTPC5_CFG_QM_SRF_10                                         0xF46DE8
+
+#define mmTPC5_CFG_QM_SRF_11                                         0xF46DEC
+
+#define mmTPC5_CFG_QM_SRF_12                                         0xF46DF0
+
+#define mmTPC5_CFG_QM_SRF_13                                         0xF46DF4
+
+#define mmTPC5_CFG_QM_SRF_14                                         0xF46DF8
+
+#define mmTPC5_CFG_QM_SRF_15                                         0xF46DFC
+
+#define mmTPC5_CFG_QM_SRF_16                                         0xF46E00
+
+#define mmTPC5_CFG_QM_SRF_17                                         0xF46E04
+
+#define mmTPC5_CFG_QM_SRF_18                                         0xF46E08
+
+#define mmTPC5_CFG_QM_SRF_19                                         0xF46E0C
+
+#define mmTPC5_CFG_QM_SRF_20                                         0xF46E10
+
+#define mmTPC5_CFG_QM_SRF_21                                         0xF46E14
+
+#define mmTPC5_CFG_QM_SRF_22                                         0xF46E18
+
+#define mmTPC5_CFG_QM_SRF_23                                         0xF46E1C
+
+#define mmTPC5_CFG_QM_SRF_24                                         0xF46E20
+
+#define mmTPC5_CFG_QM_SRF_25                                         0xF46E24
+
+#define mmTPC5_CFG_QM_SRF_26                                         0xF46E28
+
+#define mmTPC5_CFG_QM_SRF_27                                         0xF46E2C
+
+#define mmTPC5_CFG_QM_SRF_28                                         0xF46E30
+
+#define mmTPC5_CFG_QM_SRF_29                                         0xF46E34
+
+#define mmTPC5_CFG_QM_SRF_30                                         0xF46E38
+
+#define mmTPC5_CFG_QM_SRF_31                                         0xF46E3C
+
+#endif /* ASIC_REG_TPC5_CFG_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc5_qm_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc5_qm_regs.h
new file mode 100644
index 000000000000..cd3a810ff4c4
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc5_qm_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_TPC5_QM_REGS_H_
+#define ASIC_REG_TPC5_QM_REGS_H_
+
+/*
+ *****************************************
+ *   TPC5_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmTPC5_QM_GLBL_CFG0                                          0xF48000
+
+#define mmTPC5_QM_GLBL_CFG1                                          0xF48004
+
+#define mmTPC5_QM_GLBL_PROT                                          0xF48008
+
+#define mmTPC5_QM_GLBL_ERR_CFG                                       0xF4800C
+
+#define mmTPC5_QM_GLBL_SECURE_PROPS_0                                0xF48010
+
+#define mmTPC5_QM_GLBL_SECURE_PROPS_1                                0xF48014
+
+#define mmTPC5_QM_GLBL_SECURE_PROPS_2                                0xF48018
+
+#define mmTPC5_QM_GLBL_SECURE_PROPS_3                                0xF4801C
+
+#define mmTPC5_QM_GLBL_SECURE_PROPS_4                                0xF48020
+
+#define mmTPC5_QM_GLBL_NON_SECURE_PROPS_0                            0xF48024
+
+#define mmTPC5_QM_GLBL_NON_SECURE_PROPS_1                            0xF48028
+
+#define mmTPC5_QM_GLBL_NON_SECURE_PROPS_2                            0xF4802C
+
+#define mmTPC5_QM_GLBL_NON_SECURE_PROPS_3                            0xF48030
+
+#define mmTPC5_QM_GLBL_NON_SECURE_PROPS_4                            0xF48034
+
+#define mmTPC5_QM_GLBL_STS0                                          0xF48038
+
+#define mmTPC5_QM_GLBL_STS1_0                                        0xF48040
+
+#define mmTPC5_QM_GLBL_STS1_1                                        0xF48044
+
+#define mmTPC5_QM_GLBL_STS1_2                                        0xF48048
+
+#define mmTPC5_QM_GLBL_STS1_3                                        0xF4804C
+
+#define mmTPC5_QM_GLBL_STS1_4                                        0xF48050
+
+#define mmTPC5_QM_GLBL_MSG_EN_0                                      0xF48054
+
+#define mmTPC5_QM_GLBL_MSG_EN_1                                      0xF48058
+
+#define mmTPC5_QM_GLBL_MSG_EN_2                                      0xF4805C
+
+#define mmTPC5_QM_GLBL_MSG_EN_3                                      0xF48060
+
+#define mmTPC5_QM_GLBL_MSG_EN_4                                      0xF48068
+
+#define mmTPC5_QM_PQ_BASE_LO_0                                       0xF48070
+
+#define mmTPC5_QM_PQ_BASE_LO_1                                       0xF48074
+
+#define mmTPC5_QM_PQ_BASE_LO_2                                       0xF48078
+
+#define mmTPC5_QM_PQ_BASE_LO_3                                       0xF4807C
+
+#define mmTPC5_QM_PQ_BASE_HI_0                                       0xF48080
+
+#define mmTPC5_QM_PQ_BASE_HI_1                                       0xF48084
+
+#define mmTPC5_QM_PQ_BASE_HI_2                                       0xF48088
+
+#define mmTPC5_QM_PQ_BASE_HI_3                                       0xF4808C
+
+#define mmTPC5_QM_PQ_SIZE_0                                          0xF48090
+
+#define mmTPC5_QM_PQ_SIZE_1                                          0xF48094
+
+#define mmTPC5_QM_PQ_SIZE_2                                          0xF48098
+
+#define mmTPC5_QM_PQ_SIZE_3                                          0xF4809C
+
+#define mmTPC5_QM_PQ_PI_0                                            0xF480A0
+
+#define mmTPC5_QM_PQ_PI_1                                            0xF480A4
+
+#define mmTPC5_QM_PQ_PI_2                                            0xF480A8
+
+#define mmTPC5_QM_PQ_PI_3                                            0xF480AC
+
+#define mmTPC5_QM_PQ_CI_0                                            0xF480B0
+
+#define mmTPC5_QM_PQ_CI_1                                            0xF480B4
+
+#define mmTPC5_QM_PQ_CI_2                                            0xF480B8
+
+#define mmTPC5_QM_PQ_CI_3                                            0xF480BC
+
+#define mmTPC5_QM_PQ_CFG0_0                                          0xF480C0
+
+#define mmTPC5_QM_PQ_CFG0_1                                          0xF480C4
+
+#define mmTPC5_QM_PQ_CFG0_2                                          0xF480C8
+
+#define mmTPC5_QM_PQ_CFG0_3                                          0xF480CC
+
+#define mmTPC5_QM_PQ_CFG1_0                                          0xF480D0
+
+#define mmTPC5_QM_PQ_CFG1_1                                          0xF480D4
+
+#define mmTPC5_QM_PQ_CFG1_2                                          0xF480D8
+
+#define mmTPC5_QM_PQ_CFG1_3                                          0xF480DC
+
+#define mmTPC5_QM_PQ_ARUSER_31_11_0                                  0xF480E0
+
+#define mmTPC5_QM_PQ_ARUSER_31_11_1                                  0xF480E4
+
+#define mmTPC5_QM_PQ_ARUSER_31_11_2                                  0xF480E8
+
+#define mmTPC5_QM_PQ_ARUSER_31_11_3                                  0xF480EC
+
+#define mmTPC5_QM_PQ_STS0_0                                          0xF480F0
+
+#define mmTPC5_QM_PQ_STS0_1                                          0xF480F4
+
+#define mmTPC5_QM_PQ_STS0_2                                          0xF480F8
+
+#define mmTPC5_QM_PQ_STS0_3                                          0xF480FC
+
+#define mmTPC5_QM_PQ_STS1_0                                          0xF48100
+
+#define mmTPC5_QM_PQ_STS1_1                                          0xF48104
+
+#define mmTPC5_QM_PQ_STS1_2                                          0xF48108
+
+#define mmTPC5_QM_PQ_STS1_3                                          0xF4810C
+
+#define mmTPC5_QM_CQ_CFG0_0                                          0xF48110
+
+#define mmTPC5_QM_CQ_CFG0_1                                          0xF48114
+
+#define mmTPC5_QM_CQ_CFG0_2                                          0xF48118
+
+#define mmTPC5_QM_CQ_CFG0_3                                          0xF4811C
+
+#define mmTPC5_QM_CQ_CFG0_4                                          0xF48120
+
+#define mmTPC5_QM_CQ_CFG1_0                                          0xF48124
+
+#define mmTPC5_QM_CQ_CFG1_1                                          0xF48128
+
+#define mmTPC5_QM_CQ_CFG1_2                                          0xF4812C
+
+#define mmTPC5_QM_CQ_CFG1_3                                          0xF48130
+
+#define mmTPC5_QM_CQ_CFG1_4                                          0xF48134
+
+#define mmTPC5_QM_CQ_ARUSER_31_11_0                                  0xF48138
+
+#define mmTPC5_QM_CQ_ARUSER_31_11_1                                  0xF4813C
+
+#define mmTPC5_QM_CQ_ARUSER_31_11_2                                  0xF48140
+
+#define mmTPC5_QM_CQ_ARUSER_31_11_3                                  0xF48144
+
+#define mmTPC5_QM_CQ_ARUSER_31_11_4                                  0xF48148
+
+#define mmTPC5_QM_CQ_STS0_0                                          0xF4814C
+
+#define mmTPC5_QM_CQ_STS0_1                                          0xF48150
+
+#define mmTPC5_QM_CQ_STS0_2                                          0xF48154
+
+#define mmTPC5_QM_CQ_STS0_3                                          0xF48158
+
+#define mmTPC5_QM_CQ_STS0_4                                          0xF4815C
+
+#define mmTPC5_QM_CQ_STS1_0                                          0xF48160
+
+#define mmTPC5_QM_CQ_STS1_1                                          0xF48164
+
+#define mmTPC5_QM_CQ_STS1_2                                          0xF48168
+
+#define mmTPC5_QM_CQ_STS1_3                                          0xF4816C
+
+#define mmTPC5_QM_CQ_STS1_4                                          0xF48170
+
+#define mmTPC5_QM_CQ_PTR_LO_0                                        0xF48174
+
+#define mmTPC5_QM_CQ_PTR_HI_0                                        0xF48178
+
+#define mmTPC5_QM_CQ_TSIZE_0                                         0xF4817C
+
+#define mmTPC5_QM_CQ_CTL_0                                           0xF48180
+
+#define mmTPC5_QM_CQ_PTR_LO_1                                        0xF48184
+
+#define mmTPC5_QM_CQ_PTR_HI_1                                        0xF48188
+
+#define mmTPC5_QM_CQ_TSIZE_1                                         0xF4818C
+
+#define mmTPC5_QM_CQ_CTL_1                                           0xF48190
+
+#define mmTPC5_QM_CQ_PTR_LO_2                                        0xF48194
+
+#define mmTPC5_QM_CQ_PTR_HI_2                                        0xF48198
+
+#define mmTPC5_QM_CQ_TSIZE_2                                         0xF4819C
+
+#define mmTPC5_QM_CQ_CTL_2                                           0xF481A0
+
+#define mmTPC5_QM_CQ_PTR_LO_3                                        0xF481A4
+
+#define mmTPC5_QM_CQ_PTR_HI_3                                        0xF481A8
+
+#define mmTPC5_QM_CQ_TSIZE_3                                         0xF481AC
+
+#define mmTPC5_QM_CQ_CTL_3                                           0xF481B0
+
+#define mmTPC5_QM_CQ_PTR_LO_4                                        0xF481B4
+
+#define mmTPC5_QM_CQ_PTR_HI_4                                        0xF481B8
+
+#define mmTPC5_QM_CQ_TSIZE_4                                         0xF481BC
+
+#define mmTPC5_QM_CQ_CTL_4                                           0xF481C0
+
+#define mmTPC5_QM_CQ_PTR_LO_STS_0                                    0xF481C4
+
+#define mmTPC5_QM_CQ_PTR_LO_STS_1                                    0xF481C8
+
+#define mmTPC5_QM_CQ_PTR_LO_STS_2                                    0xF481CC
+
+#define mmTPC5_QM_CQ_PTR_LO_STS_3                                    0xF481D0
+
+#define mmTPC5_QM_CQ_PTR_LO_STS_4                                    0xF481D4
+
+#define mmTPC5_QM_CQ_PTR_HI_STS_0                                    0xF481D8
+
+#define mmTPC5_QM_CQ_PTR_HI_STS_1                                    0xF481DC
+
+#define mmTPC5_QM_CQ_PTR_HI_STS_2                                    0xF481E0
+
+#define mmTPC5_QM_CQ_PTR_HI_STS_3                                    0xF481E4
+
+#define mmTPC5_QM_CQ_PTR_HI_STS_4                                    0xF481E8
+
+#define mmTPC5_QM_CQ_TSIZE_STS_0                                     0xF481EC
+
+#define mmTPC5_QM_CQ_TSIZE_STS_1                                     0xF481F0
+
+#define mmTPC5_QM_CQ_TSIZE_STS_2                                     0xF481F4
+
+#define mmTPC5_QM_CQ_TSIZE_STS_3                                     0xF481F8
+
+#define mmTPC5_QM_CQ_TSIZE_STS_4                                     0xF481FC
+
+#define mmTPC5_QM_CQ_CTL_STS_0                                       0xF48200
+
+#define mmTPC5_QM_CQ_CTL_STS_1                                       0xF48204
+
+#define mmTPC5_QM_CQ_CTL_STS_2                                       0xF48208
+
+#define mmTPC5_QM_CQ_CTL_STS_3                                       0xF4820C
+
+#define mmTPC5_QM_CQ_CTL_STS_4                                       0xF48210
+
+#define mmTPC5_QM_CQ_IFIFO_CNT_0                                     0xF48214
+
+#define mmTPC5_QM_CQ_IFIFO_CNT_1                                     0xF48218
+
+#define mmTPC5_QM_CQ_IFIFO_CNT_2                                     0xF4821C
+
+#define mmTPC5_QM_CQ_IFIFO_CNT_3                                     0xF48220
+
+#define mmTPC5_QM_CQ_IFIFO_CNT_4                                     0xF48224
+
+#define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_0                             0xF48228
+
+#define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_1                             0xF4822C
+
+#define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_2                             0xF48230
+
+#define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_3                             0xF48234
+
+#define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_4                             0xF48238
+
+#define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_0                             0xF4823C
+
+#define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_1                             0xF48240
+
+#define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_2                             0xF48244
+
+#define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_3                             0xF48248
+
+#define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_4                             0xF4824C
+
+#define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_0                             0xF48250
+
+#define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_1                             0xF48254
+
+#define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_2                             0xF48258
+
+#define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_3                             0xF4825C
+
+#define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_4                             0xF48260
+
+#define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_0                             0xF48264
+
+#define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_1                             0xF48268
+
+#define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_2                             0xF4826C
+
+#define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_3                             0xF48270
+
+#define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_4                             0xF48274
+
+#define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_0                             0xF48278
+
+#define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_1                             0xF4827C
+
+#define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_2                             0xF48280
+
+#define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_3                             0xF48284
+
+#define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_4                             0xF48288
+
+#define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_0                             0xF4828C
+
+#define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_1                             0xF48290
+
+#define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_2                             0xF48294
+
+#define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_3                             0xF48298
+
+#define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_4                             0xF4829C
+
+#define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_0                             0xF482A0
+
+#define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_1                             0xF482A4
+
+#define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_2                             0xF482A8
+
+#define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_3                             0xF482AC
+
+#define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_4                             0xF482B0
+
+#define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_0                             0xF482B4
+
+#define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_1                             0xF482B8
+
+#define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_2                             0xF482BC
+
+#define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_3                             0xF482C0
+
+#define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_4                             0xF482C4
+
+#define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_0                             0xF482C8
+
+#define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_1                             0xF482CC
+
+#define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_2                             0xF482D0
+
+#define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_3                             0xF482D4
+
+#define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_4                             0xF482D8
+
+#define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0                       0xF482E0
+
+#define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1                       0xF482E4
+
+#define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2                       0xF482E8
+
+#define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3                       0xF482EC
+
+#define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4                       0xF482F0
+
+#define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_0                       0xF482F4
+
+#define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_1                       0xF482F8
+
+#define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_2                       0xF482FC
+
+#define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3                       0xF48300
+
+#define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_4                       0xF48304
+
+#define mmTPC5_QM_CP_FENCE0_RDATA_0                                  0xF48308
+
+#define mmTPC5_QM_CP_FENCE0_RDATA_1                                  0xF4830C
+
+#define mmTPC5_QM_CP_FENCE0_RDATA_2                                  0xF48310
+
+#define mmTPC5_QM_CP_FENCE0_RDATA_3                                  0xF48314
+
+#define mmTPC5_QM_CP_FENCE0_RDATA_4                                  0xF48318
+
+#define mmTPC5_QM_CP_FENCE1_RDATA_0                                  0xF4831C
+
+#define mmTPC5_QM_CP_FENCE1_RDATA_1                                  0xF48320
+
+#define mmTPC5_QM_CP_FENCE1_RDATA_2                                  0xF48324
+
+#define mmTPC5_QM_CP_FENCE1_RDATA_3                                  0xF48328
+
+#define mmTPC5_QM_CP_FENCE1_RDATA_4                                  0xF4832C
+
+#define mmTPC5_QM_CP_FENCE2_RDATA_0                                  0xF48330
+
+#define mmTPC5_QM_CP_FENCE2_RDATA_1                                  0xF48334
+
+#define mmTPC5_QM_CP_FENCE2_RDATA_2                                  0xF48338
+
+#define mmTPC5_QM_CP_FENCE2_RDATA_3                                  0xF4833C
+
+#define mmTPC5_QM_CP_FENCE2_RDATA_4                                  0xF48340
+
+#define mmTPC5_QM_CP_FENCE3_RDATA_0                                  0xF48344
+
+#define mmTPC5_QM_CP_FENCE3_RDATA_1                                  0xF48348
+
+#define mmTPC5_QM_CP_FENCE3_RDATA_2                                  0xF4834C
+
+#define mmTPC5_QM_CP_FENCE3_RDATA_3                                  0xF48350
+
+#define mmTPC5_QM_CP_FENCE3_RDATA_4                                  0xF48354
+
+#define mmTPC5_QM_CP_FENCE0_CNT_0                                    0xF48358
+
+#define mmTPC5_QM_CP_FENCE0_CNT_1                                    0xF4835C
+
+#define mmTPC5_QM_CP_FENCE0_CNT_2                                    0xF48360
+
+#define mmTPC5_QM_CP_FENCE0_CNT_3                                    0xF48364
+
+#define mmTPC5_QM_CP_FENCE0_CNT_4                                    0xF48368
+
+#define mmTPC5_QM_CP_FENCE1_CNT_0                                    0xF4836C
+
+#define mmTPC5_QM_CP_FENCE1_CNT_1                                    0xF48370
+
+#define mmTPC5_QM_CP_FENCE1_CNT_2                                    0xF48374
+
+#define mmTPC5_QM_CP_FENCE1_CNT_3                                    0xF48378
+
+#define mmTPC5_QM_CP_FENCE1_CNT_4                                    0xF4837C
+
+#define mmTPC5_QM_CP_FENCE2_CNT_0                                    0xF48380
+
+#define mmTPC5_QM_CP_FENCE2_CNT_1                                    0xF48384
+
+#define mmTPC5_QM_CP_FENCE2_CNT_2                                    0xF48388
+
+#define mmTPC5_QM_CP_FENCE2_CNT_3                                    0xF4838C
+
+#define mmTPC5_QM_CP_FENCE2_CNT_4                                    0xF48390
+
+#define mmTPC5_QM_CP_FENCE3_CNT_0                                    0xF48394
+
+#define mmTPC5_QM_CP_FENCE3_CNT_1                                    0xF48398
+
+#define mmTPC5_QM_CP_FENCE3_CNT_2                                    0xF4839C
+
+#define mmTPC5_QM_CP_FENCE3_CNT_3                                    0xF483A0
+
+#define mmTPC5_QM_CP_FENCE3_CNT_4                                    0xF483A4
+
+#define mmTPC5_QM_CP_STS_0                                           0xF483A8
+
+#define mmTPC5_QM_CP_STS_1                                           0xF483AC
+
+#define mmTPC5_QM_CP_STS_2                                           0xF483B0
+
+#define mmTPC5_QM_CP_STS_3                                           0xF483B4
+
+#define mmTPC5_QM_CP_STS_4                                           0xF483B8
+
+#define mmTPC5_QM_CP_CURRENT_INST_LO_0                               0xF483BC
+
+#define mmTPC5_QM_CP_CURRENT_INST_LO_1                               0xF483C0
+
+#define mmTPC5_QM_CP_CURRENT_INST_LO_2                               0xF483C4
+
+#define mmTPC5_QM_CP_CURRENT_INST_LO_3                               0xF483C8
+
+#define mmTPC5_QM_CP_CURRENT_INST_LO_4                               0xF483CC
+
+#define mmTPC5_QM_CP_CURRENT_INST_HI_0                               0xF483D0
+
+#define mmTPC5_QM_CP_CURRENT_INST_HI_1                               0xF483D4
+
+#define mmTPC5_QM_CP_CURRENT_INST_HI_2                               0xF483D8
+
+#define mmTPC5_QM_CP_CURRENT_INST_HI_3                               0xF483DC
+
+#define mmTPC5_QM_CP_CURRENT_INST_HI_4                               0xF483E0
+
+#define mmTPC5_QM_CP_BARRIER_CFG_0                                   0xF483F4
+
+#define mmTPC5_QM_CP_BARRIER_CFG_1                                   0xF483F8
+
+#define mmTPC5_QM_CP_BARRIER_CFG_2                                   0xF483FC
+
+#define mmTPC5_QM_CP_BARRIER_CFG_3                                   0xF48400
+
+#define mmTPC5_QM_CP_BARRIER_CFG_4                                   0xF48404
+
+#define mmTPC5_QM_CP_DBG_0_0                                         0xF48408
+
+#define mmTPC5_QM_CP_DBG_0_1                                         0xF4840C
+
+#define mmTPC5_QM_CP_DBG_0_2                                         0xF48410
+
+#define mmTPC5_QM_CP_DBG_0_3                                         0xF48414
+
+#define mmTPC5_QM_CP_DBG_0_4                                         0xF48418
+
+#define mmTPC5_QM_CP_ARUSER_31_11_0                                  0xF4841C
+
+#define mmTPC5_QM_CP_ARUSER_31_11_1                                  0xF48420
+
+#define mmTPC5_QM_CP_ARUSER_31_11_2                                  0xF48424
+
+#define mmTPC5_QM_CP_ARUSER_31_11_3                                  0xF48428
+
+#define mmTPC5_QM_CP_ARUSER_31_11_4                                  0xF4842C
+
+#define mmTPC5_QM_CP_AWUSER_31_11_0                                  0xF48430
+
+#define mmTPC5_QM_CP_AWUSER_31_11_1                                  0xF48434
+
+#define mmTPC5_QM_CP_AWUSER_31_11_2                                  0xF48438
+
+#define mmTPC5_QM_CP_AWUSER_31_11_3                                  0xF4843C
+
+#define mmTPC5_QM_CP_AWUSER_31_11_4                                  0xF48440
+
+#define mmTPC5_QM_ARB_CFG_0                                          0xF48A00
+
+#define mmTPC5_QM_ARB_CHOISE_Q_PUSH                                  0xF48A04
+
+#define mmTPC5_QM_ARB_WRR_WEIGHT_0                                   0xF48A08
+
+#define mmTPC5_QM_ARB_WRR_WEIGHT_1                                   0xF48A0C
+
+#define mmTPC5_QM_ARB_WRR_WEIGHT_2                                   0xF48A10
+
+#define mmTPC5_QM_ARB_WRR_WEIGHT_3                                   0xF48A14
+
+#define mmTPC5_QM_ARB_CFG_1                                          0xF48A18
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_0                               0xF48A20
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_1                               0xF48A24
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_2                               0xF48A28
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_3                               0xF48A2C
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_4                               0xF48A30
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_5                               0xF48A34
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_6                               0xF48A38
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_7                               0xF48A3C
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_8                               0xF48A40
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_9                               0xF48A44
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_10                              0xF48A48
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_11                              0xF48A4C
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_12                              0xF48A50
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_13                              0xF48A54
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_14                              0xF48A58
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_15                              0xF48A5C
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_16                              0xF48A60
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_17                              0xF48A64
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_18                              0xF48A68
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_19                              0xF48A6C
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_20                              0xF48A70
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_21                              0xF48A74
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_22                              0xF48A78
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_23                              0xF48A7C
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_24                              0xF48A80
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_25                              0xF48A84
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_26                              0xF48A88
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_27                              0xF48A8C
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_28                              0xF48A90
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_29                              0xF48A94
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_30                              0xF48A98
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_31                              0xF48A9C
+
+#define mmTPC5_QM_ARB_MST_CRED_INC                                   0xF48AA0
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_0                         0xF48AA4
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_1                         0xF48AA8
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_2                         0xF48AAC
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_3                         0xF48AB0
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_4                         0xF48AB4
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_5                         0xF48AB8
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_6                         0xF48ABC
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_7                         0xF48AC0
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_8                         0xF48AC4
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_9                         0xF48AC8
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_10                        0xF48ACC
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_11                        0xF48AD0
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_12                        0xF48AD4
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_13                        0xF48AD8
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_14                        0xF48ADC
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_15                        0xF48AE0
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_16                        0xF48AE4
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_17                        0xF48AE8
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_18                        0xF48AEC
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_19                        0xF48AF0
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_20                        0xF48AF4
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_21                        0xF48AF8
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_22                        0xF48AFC
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_23                        0xF48B00
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_24                        0xF48B04
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_25                        0xF48B08
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_26                        0xF48B0C
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_27                        0xF48B10
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_28                        0xF48B14
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_29                        0xF48B18
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_30                        0xF48B1C
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_31                        0xF48B20
+
+#define mmTPC5_QM_ARB_SLV_MASTER_INC_CRED_OFST                       0xF48B28
+
+#define mmTPC5_QM_ARB_MST_SLAVE_EN                                   0xF48B2C
+
+#define mmTPC5_QM_ARB_MST_QUIET_PER                                  0xF48B34
+
+#define mmTPC5_QM_ARB_SLV_CHOISE_WDT                                 0xF48B38
+
+#define mmTPC5_QM_ARB_SLV_ID                                         0xF48B3C
+
+#define mmTPC5_QM_ARB_MSG_MAX_INFLIGHT                               0xF48B44
+
+#define mmTPC5_QM_ARB_MSG_AWUSER_31_11                               0xF48B48
+
+#define mmTPC5_QM_ARB_MSG_AWUSER_SEC_PROP                            0xF48B4C
+
+#define mmTPC5_QM_ARB_MSG_AWUSER_NON_SEC_PROP                        0xF48B50
+
+#define mmTPC5_QM_ARB_BASE_LO                                        0xF48B54
+
+#define mmTPC5_QM_ARB_BASE_HI                                        0xF48B58
+
+#define mmTPC5_QM_ARB_STATE_STS                                      0xF48B80
+
+#define mmTPC5_QM_ARB_CHOISE_FULLNESS_STS                            0xF48B84
+
+#define mmTPC5_QM_ARB_MSG_STS                                        0xF48B88
+
+#define mmTPC5_QM_ARB_SLV_CHOISE_Q_HEAD                              0xF48B8C
+
+#define mmTPC5_QM_ARB_ERR_CAUSE                                      0xF48B9C
+
+#define mmTPC5_QM_ARB_ERR_MSG_EN                                     0xF48BA0
+
+#define mmTPC5_QM_ARB_ERR_STS_DRP                                    0xF48BA8
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_0                                 0xF48BB0
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_1                                 0xF48BB4
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_2                                 0xF48BB8
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_3                                 0xF48BBC
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_4                                 0xF48BC0
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_5                                 0xF48BC4
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_6                                 0xF48BC8
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_7                                 0xF48BCC
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_8                                 0xF48BD0
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_9                                 0xF48BD4
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_10                                0xF48BD8
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_11                                0xF48BDC
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_12                                0xF48BE0
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_13                                0xF48BE4
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_14                                0xF48BE8
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_15                                0xF48BEC
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_16                                0xF48BF0
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_17                                0xF48BF4
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_18                                0xF48BF8
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_19                                0xF48BFC
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_20                                0xF48C00
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_21                                0xF48C04
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_22                                0xF48C08
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_23                                0xF48C0C
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_24                                0xF48C10
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_25                                0xF48C14
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_26                                0xF48C18
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_27                                0xF48C1C
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_28                                0xF48C20
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_29                                0xF48C24
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_30                                0xF48C28
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_31                                0xF48C2C
+
+#define mmTPC5_QM_CGM_CFG                                            0xF48C70
+
+#define mmTPC5_QM_CGM_STS                                            0xF48C74
+
+#define mmTPC5_QM_CGM_CFG1                                           0xF48C78
+
+#define mmTPC5_QM_LOCAL_RANGE_BASE                                   0xF48C80
+
+#define mmTPC5_QM_LOCAL_RANGE_SIZE                                   0xF48C84
+
+#define mmTPC5_QM_CSMR_STRICT_PRIO_CFG                               0xF48C90
+
+#define mmTPC5_QM_HBW_RD_RATE_LIM_CFG_1                              0xF48C94
+
+#define mmTPC5_QM_LBW_WR_RATE_LIM_CFG_0                              0xF48C98
+
+#define mmTPC5_QM_LBW_WR_RATE_LIM_CFG_1                              0xF48C9C
+
+#define mmTPC5_QM_HBW_RD_RATE_LIM_CFG_0                              0xF48CA0
+
+#define mmTPC5_QM_GLBL_AXCACHE                                       0xF48CA4
+
+#define mmTPC5_QM_IND_GW_APB_CFG                                     0xF48CB0
+
+#define mmTPC5_QM_IND_GW_APB_WDATA                                   0xF48CB4
+
+#define mmTPC5_QM_IND_GW_APB_RDATA                                   0xF48CB8
+
+#define mmTPC5_QM_IND_GW_APB_STATUS                                  0xF48CBC
+
+#define mmTPC5_QM_GLBL_ERR_ADDR_LO                                   0xF48CD0
+
+#define mmTPC5_QM_GLBL_ERR_ADDR_HI                                   0xF48CD4
+
+#define mmTPC5_QM_GLBL_ERR_WDATA                                     0xF48CD8
+
+#define mmTPC5_QM_GLBL_MEM_INIT_BUSY                                 0xF48D00
+
+#endif /* ASIC_REG_TPC5_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc6_cfg_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc6_cfg_regs.h
new file mode 100644
index 000000000000..eb251e72813f
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc6_cfg_regs.h
@@ -0,0 +1,1226 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_TPC6_CFG_REGS_H_
+#define ASIC_REG_TPC6_CFG_REGS_H_
+
+/*
+ *****************************************
+ *   TPC6_CFG (Prototype: TPC)
+ *****************************************
+ */
+
+#define mmTPC6_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW                     0xF86400
+
+#define mmTPC6_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH                    0xF86404
+
+#define mmTPC6_CFG_KERNEL_TENSOR_0_PADDING_VALUE                     0xF86408
+
+#define mmTPC6_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG                     0xF8640C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_0_SIZE                        0xF86410
+
+#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE                      0xF86414
+
+#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_1_SIZE                        0xF86418
+
+#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE                      0xF8641C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_2_SIZE                        0xF86420
+
+#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE                      0xF86424
+
+#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_3_SIZE                        0xF86428
+
+#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE                      0xF8642C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_4_SIZE                        0xF86430
+
+#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE                      0xF86434
+
+#define mmTPC6_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW                     0xF86438
+
+#define mmTPC6_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH                    0xF8643C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_1_PADDING_VALUE                     0xF86440
+
+#define mmTPC6_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG                     0xF86444
+
+#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_0_SIZE                        0xF86448
+
+#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE                      0xF8644C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_1_SIZE                        0xF86450
+
+#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE                      0xF86454
+
+#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_2_SIZE                        0xF86458
+
+#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE                      0xF8645C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_3_SIZE                        0xF86460
+
+#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE                      0xF86464
+
+#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_4_SIZE                        0xF86468
+
+#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE                      0xF8646C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW                     0xF86470
+
+#define mmTPC6_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH                    0xF86474
+
+#define mmTPC6_CFG_KERNEL_TENSOR_2_PADDING_VALUE                     0xF86478
+
+#define mmTPC6_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG                     0xF8647C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_0_SIZE                        0xF86480
+
+#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE                      0xF86484
+
+#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_1_SIZE                        0xF86488
+
+#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE                      0xF8648C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_2_SIZE                        0xF86490
+
+#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE                      0xF86494
+
+#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_3_SIZE                        0xF86498
+
+#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE                      0xF8649C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_4_SIZE                        0xF864A0
+
+#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE                      0xF864A4
+
+#define mmTPC6_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW                     0xF864A8
+
+#define mmTPC6_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH                    0xF864AC
+
+#define mmTPC6_CFG_KERNEL_TENSOR_3_PADDING_VALUE                     0xF864B0
+
+#define mmTPC6_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG                     0xF864B4
+
+#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_0_SIZE                        0xF864B8
+
+#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE                      0xF864BC
+
+#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_1_SIZE                        0xF864C0
+
+#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE                      0xF864C4
+
+#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_2_SIZE                        0xF864C8
+
+#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE                      0xF864CC
+
+#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_3_SIZE                        0xF864D0
+
+#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE                      0xF864D4
+
+#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_4_SIZE                        0xF864D8
+
+#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE                      0xF864DC
+
+#define mmTPC6_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW                     0xF864E0
+
+#define mmTPC6_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH                    0xF864E4
+
+#define mmTPC6_CFG_KERNEL_TENSOR_4_PADDING_VALUE                     0xF864E8
+
+#define mmTPC6_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG                     0xF864EC
+
+#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_0_SIZE                        0xF864F0
+
+#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE                      0xF864F4
+
+#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_1_SIZE                        0xF864F8
+
+#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE                      0xF864FC
+
+#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_2_SIZE                        0xF86500
+
+#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE                      0xF86504
+
+#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_3_SIZE                        0xF86508
+
+#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE                      0xF8650C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_4_SIZE                        0xF86510
+
+#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE                      0xF86514
+
+#define mmTPC6_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW                     0xF86518
+
+#define mmTPC6_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH                    0xF8651C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_5_PADDING_VALUE                     0xF86520
+
+#define mmTPC6_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG                     0xF86524
+
+#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_0_SIZE                        0xF86528
+
+#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE                      0xF8652C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_1_SIZE                        0xF86530
+
+#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE                      0xF86534
+
+#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_2_SIZE                        0xF86538
+
+#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE                      0xF8653C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_3_SIZE                        0xF86540
+
+#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE                      0xF86544
+
+#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_4_SIZE                        0xF86548
+
+#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE                      0xF8654C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW                     0xF86550
+
+#define mmTPC6_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH                    0xF86554
+
+#define mmTPC6_CFG_KERNEL_TENSOR_6_PADDING_VALUE                     0xF86558
+
+#define mmTPC6_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG                     0xF8655C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_0_SIZE                        0xF86560
+
+#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE                      0xF86564
+
+#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_1_SIZE                        0xF86568
+
+#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE                      0xF8656C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_2_SIZE                        0xF86570
+
+#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE                      0xF86574
+
+#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_3_SIZE                        0xF86578
+
+#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE                      0xF8657C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_4_SIZE                        0xF86580
+
+#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE                      0xF86584
+
+#define mmTPC6_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW                     0xF86588
+
+#define mmTPC6_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH                    0xF8658C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_7_PADDING_VALUE                     0xF86590
+
+#define mmTPC6_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG                     0xF86594
+
+#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_0_SIZE                        0xF86598
+
+#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE                      0xF8659C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_1_SIZE                        0xF865A0
+
+#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE                      0xF865A4
+
+#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_2_SIZE                        0xF865A8
+
+#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE                      0xF865AC
+
+#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_3_SIZE                        0xF865B0
+
+#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE                      0xF865B4
+
+#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_4_SIZE                        0xF865B8
+
+#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE                      0xF865BC
+
+#define mmTPC6_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW                     0xF865C0
+
+#define mmTPC6_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH                    0xF865C4
+
+#define mmTPC6_CFG_KERNEL_TENSOR_8_PADDING_VALUE                     0xF865C8
+
+#define mmTPC6_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG                     0xF865CC
+
+#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_0_SIZE                        0xF865D0
+
+#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE                      0xF865D4
+
+#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_1_SIZE                        0xF865D8
+
+#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE                      0xF865DC
+
+#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_2_SIZE                        0xF865E0
+
+#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE                      0xF865E4
+
+#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_3_SIZE                        0xF865E8
+
+#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE                      0xF865EC
+
+#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_4_SIZE                        0xF865F0
+
+#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE                      0xF865F4
+
+#define mmTPC6_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW                     0xF865F8
+
+#define mmTPC6_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH                    0xF865FC
+
+#define mmTPC6_CFG_KERNEL_TENSOR_9_PADDING_VALUE                     0xF86600
+
+#define mmTPC6_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG                     0xF86604
+
+#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_0_SIZE                        0xF86608
+
+#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE                      0xF8660C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_1_SIZE                        0xF86610
+
+#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE                      0xF86614
+
+#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_2_SIZE                        0xF86618
+
+#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE                      0xF8661C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_3_SIZE                        0xF86620
+
+#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE                      0xF86624
+
+#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_4_SIZE                        0xF86628
+
+#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE                      0xF8662C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW                    0xF86630
+
+#define mmTPC6_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH                   0xF86634
+
+#define mmTPC6_CFG_KERNEL_TENSOR_10_PADDING_VALUE                    0xF86638
+
+#define mmTPC6_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG                    0xF8663C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_0_SIZE                       0xF86640
+
+#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE                     0xF86644
+
+#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_1_SIZE                       0xF86648
+
+#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE                     0xF8664C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_2_SIZE                       0xF86650
+
+#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE                     0xF86654
+
+#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_3_SIZE                       0xF86658
+
+#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE                     0xF8665C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_4_SIZE                       0xF86660
+
+#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE                     0xF86664
+
+#define mmTPC6_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW                    0xF86668
+
+#define mmTPC6_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH                   0xF8666C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_11_PADDING_VALUE                    0xF86670
+
+#define mmTPC6_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG                    0xF86674
+
+#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_0_SIZE                       0xF86678
+
+#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE                     0xF8667C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_1_SIZE                       0xF86680
+
+#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE                     0xF86684
+
+#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_2_SIZE                       0xF86688
+
+#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE                     0xF8668C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_3_SIZE                       0xF86690
+
+#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE                     0xF86694
+
+#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_4_SIZE                       0xF86698
+
+#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE                     0xF8669C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW                    0xF866A0
+
+#define mmTPC6_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH                   0xF866A4
+
+#define mmTPC6_CFG_KERNEL_TENSOR_12_PADDING_VALUE                    0xF866A8
+
+#define mmTPC6_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG                    0xF866AC
+
+#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_0_SIZE                       0xF866B0
+
+#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE                     0xF866B4
+
+#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_1_SIZE                       0xF866B8
+
+#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE                     0xF866BC
+
+#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_2_SIZE                       0xF866C0
+
+#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE                     0xF866C4
+
+#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_3_SIZE                       0xF866C8
+
+#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE                     0xF866CC
+
+#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_4_SIZE                       0xF866D0
+
+#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE                     0xF866D4
+
+#define mmTPC6_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW                    0xF866D8
+
+#define mmTPC6_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH                   0xF866DC
+
+#define mmTPC6_CFG_KERNEL_TENSOR_13_PADDING_VALUE                    0xF866E0
+
+#define mmTPC6_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG                    0xF866E4
+
+#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_0_SIZE                       0xF866E8
+
+#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE                     0xF866EC
+
+#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_1_SIZE                       0xF866F0
+
+#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE                     0xF866F4
+
+#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_2_SIZE                       0xF866F8
+
+#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE                     0xF866FC
+
+#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_3_SIZE                       0xF86700
+
+#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE                     0xF86704
+
+#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_4_SIZE                       0xF86708
+
+#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE                     0xF8670C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW                    0xF86710
+
+#define mmTPC6_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH                   0xF86714
+
+#define mmTPC6_CFG_KERNEL_TENSOR_14_PADDING_VALUE                    0xF86718
+
+#define mmTPC6_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG                    0xF8671C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_0_SIZE                       0xF86720
+
+#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE                     0xF86724
+
+#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_1_SIZE                       0xF86728
+
+#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE                     0xF8672C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_2_SIZE                       0xF86730
+
+#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE                     0xF86734
+
+#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_3_SIZE                       0xF86738
+
+#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE                     0xF8673C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_4_SIZE                       0xF86740
+
+#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE                     0xF86744
+
+#define mmTPC6_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW                    0xF86748
+
+#define mmTPC6_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH                   0xF8674C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_15_PADDING_VALUE                    0xF86750
+
+#define mmTPC6_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG                    0xF86754
+
+#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_0_SIZE                       0xF86758
+
+#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE                     0xF8675C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_1_SIZE                       0xF86760
+
+#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE                     0xF86764
+
+#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_2_SIZE                       0xF86768
+
+#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE                     0xF8676C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_3_SIZE                       0xF86770
+
+#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE                     0xF86774
+
+#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_4_SIZE                       0xF86778
+
+#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE                     0xF8677C
+
+#define mmTPC6_CFG_KERNEL_SYNC_OBJECT_MESSAGE                        0xF86780
+
+#define mmTPC6_CFG_KERNEL_SYNC_OBJECT_ADDR                           0xF86784
+
+#define mmTPC6_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW                    0xF86788
+
+#define mmTPC6_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH                   0xF8678C
+
+#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_0                             0xF86790
+
+#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_0                             0xF86794
+
+#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_1                             0xF86798
+
+#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_1                             0xF8679C
+
+#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_2                             0xF867A0
+
+#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_2                             0xF867A4
+
+#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_3                             0xF867A8
+
+#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_3                             0xF867AC
+
+#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_4                             0xF867B0
+
+#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_4                             0xF867B4
+
+#define mmTPC6_CFG_KERNEL_KERNEL_CONFIG                              0xF867B8
+
+#define mmTPC6_CFG_KERNEL_KERNEL_ID                                  0xF867BC
+
+#define mmTPC6_CFG_KERNEL_SRF_0                                      0xF867C0
+
+#define mmTPC6_CFG_KERNEL_SRF_1                                      0xF867C4
+
+#define mmTPC6_CFG_KERNEL_SRF_2                                      0xF867C8
+
+#define mmTPC6_CFG_KERNEL_SRF_3                                      0xF867CC
+
+#define mmTPC6_CFG_KERNEL_SRF_4                                      0xF867D0
+
+#define mmTPC6_CFG_KERNEL_SRF_5                                      0xF867D4
+
+#define mmTPC6_CFG_KERNEL_SRF_6                                      0xF867D8
+
+#define mmTPC6_CFG_KERNEL_SRF_7                                      0xF867DC
+
+#define mmTPC6_CFG_KERNEL_SRF_8                                      0xF867E0
+
+#define mmTPC6_CFG_KERNEL_SRF_9                                      0xF867E4
+
+#define mmTPC6_CFG_KERNEL_SRF_10                                     0xF867E8
+
+#define mmTPC6_CFG_KERNEL_SRF_11                                     0xF867EC
+
+#define mmTPC6_CFG_KERNEL_SRF_12                                     0xF867F0
+
+#define mmTPC6_CFG_KERNEL_SRF_13                                     0xF867F4
+
+#define mmTPC6_CFG_KERNEL_SRF_14                                     0xF867F8
+
+#define mmTPC6_CFG_KERNEL_SRF_15                                     0xF867FC
+
+#define mmTPC6_CFG_KERNEL_SRF_16                                     0xF86800
+
+#define mmTPC6_CFG_KERNEL_SRF_17                                     0xF86804
+
+#define mmTPC6_CFG_KERNEL_SRF_18                                     0xF86808
+
+#define mmTPC6_CFG_KERNEL_SRF_19                                     0xF8680C
+
+#define mmTPC6_CFG_KERNEL_SRF_20                                     0xF86810
+
+#define mmTPC6_CFG_KERNEL_SRF_21                                     0xF86814
+
+#define mmTPC6_CFG_KERNEL_SRF_22                                     0xF86818
+
+#define mmTPC6_CFG_KERNEL_SRF_23                                     0xF8681C
+
+#define mmTPC6_CFG_KERNEL_SRF_24                                     0xF86820
+
+#define mmTPC6_CFG_KERNEL_SRF_25                                     0xF86824
+
+#define mmTPC6_CFG_KERNEL_SRF_26                                     0xF86828
+
+#define mmTPC6_CFG_KERNEL_SRF_27                                     0xF8682C
+
+#define mmTPC6_CFG_KERNEL_SRF_28                                     0xF86830
+
+#define mmTPC6_CFG_KERNEL_SRF_29                                     0xF86834
+
+#define mmTPC6_CFG_KERNEL_SRF_30                                     0xF86838
+
+#define mmTPC6_CFG_KERNEL_SRF_31                                     0xF8683C
+
+#define mmTPC6_CFG_ROUND_CSR                                         0xF868FC
+
+#define mmTPC6_CFG_PROT                                              0xF86900
+
+#define mmTPC6_CFG_SEMAPHORE                                         0xF86908
+
+#define mmTPC6_CFG_VFLAGS                                            0xF8690C
+
+#define mmTPC6_CFG_SFLAGS                                            0xF86910
+
+#define mmTPC6_CFG_LFSR_POLYNOM                                      0xF86918
+
+#define mmTPC6_CFG_STATUS                                            0xF8691C
+
+#define mmTPC6_CFG_CFG_BASE_ADDRESS_HIGH                             0xF86920
+
+#define mmTPC6_CFG_CFG_SUBTRACT_VALUE                                0xF86924
+
+#define mmTPC6_CFG_SM_BASE_ADDRESS_HIGH                              0xF8692C
+
+#define mmTPC6_CFG_TPC_CMD                                           0xF86930
+
+#define mmTPC6_CFG_TPC_EXECUTE                                       0xF86938
+
+#define mmTPC6_CFG_TPC_STALL                                         0xF8693C
+
+#define mmTPC6_CFG_ICACHE_BASE_ADDERESS_LOW                          0xF86940
+
+#define mmTPC6_CFG_ICACHE_BASE_ADDERESS_HIGH                         0xF86944
+
+#define mmTPC6_CFG_RD_RATE_LIMIT                                     0xF86948
+
+#define mmTPC6_CFG_WR_RATE_LIMIT                                     0xF86950
+
+#define mmTPC6_CFG_MSS_CONFIG                                        0xF86954
+
+#define mmTPC6_CFG_TPC_INTR_CAUSE                                    0xF86958
+
+#define mmTPC6_CFG_TPC_INTR_MASK                                     0xF8695C
+
+#define mmTPC6_CFG_WQ_CREDITS                                        0xF86960
+
+#define mmTPC6_CFG_ARUSER_LO                                         0xF86964
+
+#define mmTPC6_CFG_ARUSER_HI                                         0xF86968
+
+#define mmTPC6_CFG_AWUSER_LO                                         0xF8696C
+
+#define mmTPC6_CFG_AWUSER_HI                                         0xF86970
+
+#define mmTPC6_CFG_OPCODE_EXEC                                       0xF86974
+
+#define mmTPC6_CFG_LUT_FUNC32_BASE_ADDR_LO                           0xF86978
+
+#define mmTPC6_CFG_LUT_FUNC32_BASE_ADDR_HI                           0xF8697C
+
+#define mmTPC6_CFG_LUT_FUNC64_BASE_ADDR_LO                           0xF86980
+
+#define mmTPC6_CFG_LUT_FUNC64_BASE_ADDR_HI                           0xF86984
+
+#define mmTPC6_CFG_LUT_FUNC128_BASE_ADDR_LO                          0xF86988
+
+#define mmTPC6_CFG_LUT_FUNC128_BASE_ADDR_HI                          0xF8698C
+
+#define mmTPC6_CFG_LUT_FUNC256_BASE_ADDR_LO                          0xF86990
+
+#define mmTPC6_CFG_LUT_FUNC256_BASE_ADDR_HI                          0xF86994
+
+#define mmTPC6_CFG_TSB_CFG_MAX_SIZE                                  0xF86998
+
+#define mmTPC6_CFG_TSB_CFG                                           0xF8699C
+
+#define mmTPC6_CFG_DBGMEM_ADD                                        0xF869A0
+
+#define mmTPC6_CFG_DBGMEM_DATA_WR                                    0xF869A4
+
+#define mmTPC6_CFG_DBGMEM_DATA_RD                                    0xF869A8
+
+#define mmTPC6_CFG_DBGMEM_CTRL                                       0xF869AC
+
+#define mmTPC6_CFG_DBGMEM_RC                                         0xF869B0
+
+#define mmTPC6_CFG_TSB_INFLIGHT_CNTR                                 0xF869B4
+
+#define mmTPC6_CFG_WQ_INFLIGHT_CNTR                                  0xF869B8
+
+#define mmTPC6_CFG_WQ_LBW_TOTAL_CNTR                                 0xF869BC
+
+#define mmTPC6_CFG_WQ_HBW_TOTAL_CNTR                                 0xF869C0
+
+#define mmTPC6_CFG_IRQ_OCCOUPY_CNTR                                  0xF869C4
+
+#define mmTPC6_CFG_FUNC_MBIST_CNTRL                                  0xF869D0
+
+#define mmTPC6_CFG_FUNC_MBIST_PAT                                    0xF869D4
+
+#define mmTPC6_CFG_FUNC_MBIST_MEM_0                                  0xF869D8
+
+#define mmTPC6_CFG_FUNC_MBIST_MEM_1                                  0xF869DC
+
+#define mmTPC6_CFG_FUNC_MBIST_MEM_2                                  0xF869E0
+
+#define mmTPC6_CFG_FUNC_MBIST_MEM_3                                  0xF869E4
+
+#define mmTPC6_CFG_FUNC_MBIST_MEM_4                                  0xF869E8
+
+#define mmTPC6_CFG_FUNC_MBIST_MEM_5                                  0xF869EC
+
+#define mmTPC6_CFG_FUNC_MBIST_MEM_6                                  0xF869F0
+
+#define mmTPC6_CFG_FUNC_MBIST_MEM_7                                  0xF869F4
+
+#define mmTPC6_CFG_FUNC_MBIST_MEM_8                                  0xF869F8
+
+#define mmTPC6_CFG_FUNC_MBIST_MEM_9                                  0xF869FC
+
+#define mmTPC6_CFG_QM_TENSOR_0_BASE_ADDR_LOW                         0xF86A00
+
+#define mmTPC6_CFG_QM_TENSOR_0_BASE_ADDR_HIGH                        0xF86A04
+
+#define mmTPC6_CFG_QM_TENSOR_0_PADDING_VALUE                         0xF86A08
+
+#define mmTPC6_CFG_QM_TENSOR_0_TENSOR_CONFIG                         0xF86A0C
+
+#define mmTPC6_CFG_QM_TENSOR_0_DIM_0_SIZE                            0xF86A10
+
+#define mmTPC6_CFG_QM_TENSOR_0_DIM_0_STRIDE                          0xF86A14
+
+#define mmTPC6_CFG_QM_TENSOR_0_DIM_1_SIZE                            0xF86A18
+
+#define mmTPC6_CFG_QM_TENSOR_0_DIM_1_STRIDE                          0xF86A1C
+
+#define mmTPC6_CFG_QM_TENSOR_0_DIM_2_SIZE                            0xF86A20
+
+#define mmTPC6_CFG_QM_TENSOR_0_DIM_2_STRIDE                          0xF86A24
+
+#define mmTPC6_CFG_QM_TENSOR_0_DIM_3_SIZE                            0xF86A28
+
+#define mmTPC6_CFG_QM_TENSOR_0_DIM_3_STRIDE                          0xF86A2C
+
+#define mmTPC6_CFG_QM_TENSOR_0_DIM_4_SIZE                            0xF86A30
+
+#define mmTPC6_CFG_QM_TENSOR_0_DIM_4_STRIDE                          0xF86A34
+
+#define mmTPC6_CFG_QM_TENSOR_1_BASE_ADDR_LOW                         0xF86A38
+
+#define mmTPC6_CFG_QM_TENSOR_1_BASE_ADDR_HIGH                        0xF86A3C
+
+#define mmTPC6_CFG_QM_TENSOR_1_PADDING_VALUE                         0xF86A40
+
+#define mmTPC6_CFG_QM_TENSOR_1_TENSOR_CONFIG                         0xF86A44
+
+#define mmTPC6_CFG_QM_TENSOR_1_DIM_0_SIZE                            0xF86A48
+
+#define mmTPC6_CFG_QM_TENSOR_1_DIM_0_STRIDE                          0xF86A4C
+
+#define mmTPC6_CFG_QM_TENSOR_1_DIM_1_SIZE                            0xF86A50
+
+#define mmTPC6_CFG_QM_TENSOR_1_DIM_1_STRIDE                          0xF86A54
+
+#define mmTPC6_CFG_QM_TENSOR_1_DIM_2_SIZE                            0xF86A58
+
+#define mmTPC6_CFG_QM_TENSOR_1_DIM_2_STRIDE                          0xF86A5C
+
+#define mmTPC6_CFG_QM_TENSOR_1_DIM_3_SIZE                            0xF86A60
+
+#define mmTPC6_CFG_QM_TENSOR_1_DIM_3_STRIDE                          0xF86A64
+
+#define mmTPC6_CFG_QM_TENSOR_1_DIM_4_SIZE                            0xF86A68
+
+#define mmTPC6_CFG_QM_TENSOR_1_DIM_4_STRIDE                          0xF86A6C
+
+#define mmTPC6_CFG_QM_TENSOR_2_BASE_ADDR_LOW                         0xF86A70
+
+#define mmTPC6_CFG_QM_TENSOR_2_BASE_ADDR_HIGH                        0xF86A74
+
+#define mmTPC6_CFG_QM_TENSOR_2_PADDING_VALUE                         0xF86A78
+
+#define mmTPC6_CFG_QM_TENSOR_2_TENSOR_CONFIG                         0xF86A7C
+
+#define mmTPC6_CFG_QM_TENSOR_2_DIM_0_SIZE                            0xF86A80
+
+#define mmTPC6_CFG_QM_TENSOR_2_DIM_0_STRIDE                          0xF86A84
+
+#define mmTPC6_CFG_QM_TENSOR_2_DIM_1_SIZE                            0xF86A88
+
+#define mmTPC6_CFG_QM_TENSOR_2_DIM_1_STRIDE                          0xF86A8C
+
+#define mmTPC6_CFG_QM_TENSOR_2_DIM_2_SIZE                            0xF86A90
+
+#define mmTPC6_CFG_QM_TENSOR_2_DIM_2_STRIDE                          0xF86A94
+
+#define mmTPC6_CFG_QM_TENSOR_2_DIM_3_SIZE                            0xF86A98
+
+#define mmTPC6_CFG_QM_TENSOR_2_DIM_3_STRIDE                          0xF86A9C
+
+#define mmTPC6_CFG_QM_TENSOR_2_DIM_4_SIZE                            0xF86AA0
+
+#define mmTPC6_CFG_QM_TENSOR_2_DIM_4_STRIDE                          0xF86AA4
+
+#define mmTPC6_CFG_QM_TENSOR_3_BASE_ADDR_LOW                         0xF86AA8
+
+#define mmTPC6_CFG_QM_TENSOR_3_BASE_ADDR_HIGH                        0xF86AAC
+
+#define mmTPC6_CFG_QM_TENSOR_3_PADDING_VALUE                         0xF86AB0
+
+#define mmTPC6_CFG_QM_TENSOR_3_TENSOR_CONFIG                         0xF86AB4
+
+#define mmTPC6_CFG_QM_TENSOR_3_DIM_0_SIZE                            0xF86AB8
+
+#define mmTPC6_CFG_QM_TENSOR_3_DIM_0_STRIDE                          0xF86ABC
+
+#define mmTPC6_CFG_QM_TENSOR_3_DIM_1_SIZE                            0xF86AC0
+
+#define mmTPC6_CFG_QM_TENSOR_3_DIM_1_STRIDE                          0xF86AC4
+
+#define mmTPC6_CFG_QM_TENSOR_3_DIM_2_SIZE                            0xF86AC8
+
+#define mmTPC6_CFG_QM_TENSOR_3_DIM_2_STRIDE                          0xF86ACC
+
+#define mmTPC6_CFG_QM_TENSOR_3_DIM_3_SIZE                            0xF86AD0
+
+#define mmTPC6_CFG_QM_TENSOR_3_DIM_3_STRIDE                          0xF86AD4
+
+#define mmTPC6_CFG_QM_TENSOR_3_DIM_4_SIZE                            0xF86AD8
+
+#define mmTPC6_CFG_QM_TENSOR_3_DIM_4_STRIDE                          0xF86ADC
+
+#define mmTPC6_CFG_QM_TENSOR_4_BASE_ADDR_LOW                         0xF86AE0
+
+#define mmTPC6_CFG_QM_TENSOR_4_BASE_ADDR_HIGH                        0xF86AE4
+
+#define mmTPC6_CFG_QM_TENSOR_4_PADDING_VALUE                         0xF86AE8
+
+#define mmTPC6_CFG_QM_TENSOR_4_TENSOR_CONFIG                         0xF86AEC
+
+#define mmTPC6_CFG_QM_TENSOR_4_DIM_0_SIZE                            0xF86AF0
+
+#define mmTPC6_CFG_QM_TENSOR_4_DIM_0_STRIDE                          0xF86AF4
+
+#define mmTPC6_CFG_QM_TENSOR_4_DIM_1_SIZE                            0xF86AF8
+
+#define mmTPC6_CFG_QM_TENSOR_4_DIM_1_STRIDE                          0xF86AFC
+
+#define mmTPC6_CFG_QM_TENSOR_4_DIM_2_SIZE                            0xF86B00
+
+#define mmTPC6_CFG_QM_TENSOR_4_DIM_2_STRIDE                          0xF86B04
+
+#define mmTPC6_CFG_QM_TENSOR_4_DIM_3_SIZE                            0xF86B08
+
+#define mmTPC6_CFG_QM_TENSOR_4_DIM_3_STRIDE                          0xF86B0C
+
+#define mmTPC6_CFG_QM_TENSOR_4_DIM_4_SIZE                            0xF86B10
+
+#define mmTPC6_CFG_QM_TENSOR_4_DIM_4_STRIDE                          0xF86B14
+
+#define mmTPC6_CFG_QM_TENSOR_5_BASE_ADDR_LOW                         0xF86B18
+
+#define mmTPC6_CFG_QM_TENSOR_5_BASE_ADDR_HIGH                        0xF86B1C
+
+#define mmTPC6_CFG_QM_TENSOR_5_PADDING_VALUE                         0xF86B20
+
+#define mmTPC6_CFG_QM_TENSOR_5_TENSOR_CONFIG                         0xF86B24
+
+#define mmTPC6_CFG_QM_TENSOR_5_DIM_0_SIZE                            0xF86B28
+
+#define mmTPC6_CFG_QM_TENSOR_5_DIM_0_STRIDE                          0xF86B2C
+
+#define mmTPC6_CFG_QM_TENSOR_5_DIM_1_SIZE                            0xF86B30
+
+#define mmTPC6_CFG_QM_TENSOR_5_DIM_1_STRIDE                          0xF86B34
+
+#define mmTPC6_CFG_QM_TENSOR_5_DIM_2_SIZE                            0xF86B38
+
+#define mmTPC6_CFG_QM_TENSOR_5_DIM_2_STRIDE                          0xF86B3C
+
+#define mmTPC6_CFG_QM_TENSOR_5_DIM_3_SIZE                            0xF86B40
+
+#define mmTPC6_CFG_QM_TENSOR_5_DIM_3_STRIDE                          0xF86B44
+
+#define mmTPC6_CFG_QM_TENSOR_5_DIM_4_SIZE                            0xF86B48
+
+#define mmTPC6_CFG_QM_TENSOR_5_DIM_4_STRIDE                          0xF86B4C
+
+#define mmTPC6_CFG_QM_TENSOR_6_BASE_ADDR_LOW                         0xF86B50
+
+#define mmTPC6_CFG_QM_TENSOR_6_BASE_ADDR_HIGH                        0xF86B54
+
+#define mmTPC6_CFG_QM_TENSOR_6_PADDING_VALUE                         0xF86B58
+
+#define mmTPC6_CFG_QM_TENSOR_6_TENSOR_CONFIG                         0xF86B5C
+
+#define mmTPC6_CFG_QM_TENSOR_6_DIM_0_SIZE                            0xF86B60
+
+#define mmTPC6_CFG_QM_TENSOR_6_DIM_0_STRIDE                          0xF86B64
+
+#define mmTPC6_CFG_QM_TENSOR_6_DIM_1_SIZE                            0xF86B68
+
+#define mmTPC6_CFG_QM_TENSOR_6_DIM_1_STRIDE                          0xF86B6C
+
+#define mmTPC6_CFG_QM_TENSOR_6_DIM_2_SIZE                            0xF86B70
+
+#define mmTPC6_CFG_QM_TENSOR_6_DIM_2_STRIDE                          0xF86B74
+
+#define mmTPC6_CFG_QM_TENSOR_6_DIM_3_SIZE                            0xF86B78
+
+#define mmTPC6_CFG_QM_TENSOR_6_DIM_3_STRIDE                          0xF86B7C
+
+#define mmTPC6_CFG_QM_TENSOR_6_DIM_4_SIZE                            0xF86B80
+
+#define mmTPC6_CFG_QM_TENSOR_6_DIM_4_STRIDE                          0xF86B84
+
+#define mmTPC6_CFG_QM_TENSOR_7_BASE_ADDR_LOW                         0xF86B88
+
+#define mmTPC6_CFG_QM_TENSOR_7_BASE_ADDR_HIGH                        0xF86B8C
+
+#define mmTPC6_CFG_QM_TENSOR_7_PADDING_VALUE                         0xF86B90
+
+#define mmTPC6_CFG_QM_TENSOR_7_TENSOR_CONFIG                         0xF86B94
+
+#define mmTPC6_CFG_QM_TENSOR_7_DIM_0_SIZE                            0xF86B98
+
+#define mmTPC6_CFG_QM_TENSOR_7_DIM_0_STRIDE                          0xF86B9C
+
+#define mmTPC6_CFG_QM_TENSOR_7_DIM_1_SIZE                            0xF86BA0
+
+#define mmTPC6_CFG_QM_TENSOR_7_DIM_1_STRIDE                          0xF86BA4
+
+#define mmTPC6_CFG_QM_TENSOR_7_DIM_2_SIZE                            0xF86BA8
+
+#define mmTPC6_CFG_QM_TENSOR_7_DIM_2_STRIDE                          0xF86BAC
+
+#define mmTPC6_CFG_QM_TENSOR_7_DIM_3_SIZE                            0xF86BB0
+
+#define mmTPC6_CFG_QM_TENSOR_7_DIM_3_STRIDE                          0xF86BB4
+
+#define mmTPC6_CFG_QM_TENSOR_7_DIM_4_SIZE                            0xF86BB8
+
+#define mmTPC6_CFG_QM_TENSOR_7_DIM_4_STRIDE                          0xF86BBC
+
+#define mmTPC6_CFG_QM_TENSOR_8_BASE_ADDR_LOW                         0xF86BC0
+
+#define mmTPC6_CFG_QM_TENSOR_8_BASE_ADDR_HIGH                        0xF86BC4
+
+#define mmTPC6_CFG_QM_TENSOR_8_PADDING_VALUE                         0xF86BC8
+
+#define mmTPC6_CFG_QM_TENSOR_8_TENSOR_CONFIG                         0xF86BCC
+
+#define mmTPC6_CFG_QM_TENSOR_8_DIM_0_SIZE                            0xF86BD0
+
+#define mmTPC6_CFG_QM_TENSOR_8_DIM_0_STRIDE                          0xF86BD4
+
+#define mmTPC6_CFG_QM_TENSOR_8_DIM_1_SIZE                            0xF86BD8
+
+#define mmTPC6_CFG_QM_TENSOR_8_DIM_1_STRIDE                          0xF86BDC
+
+#define mmTPC6_CFG_QM_TENSOR_8_DIM_2_SIZE                            0xF86BE0
+
+#define mmTPC6_CFG_QM_TENSOR_8_DIM_2_STRIDE                          0xF86BE4
+
+#define mmTPC6_CFG_QM_TENSOR_8_DIM_3_SIZE                            0xF86BE8
+
+#define mmTPC6_CFG_QM_TENSOR_8_DIM_3_STRIDE                          0xF86BEC
+
+#define mmTPC6_CFG_QM_TENSOR_8_DIM_4_SIZE                            0xF86BF0
+
+#define mmTPC6_CFG_QM_TENSOR_8_DIM_4_STRIDE                          0xF86BF4
+
+#define mmTPC6_CFG_QM_TENSOR_9_BASE_ADDR_LOW                         0xF86BF8
+
+#define mmTPC6_CFG_QM_TENSOR_9_BASE_ADDR_HIGH                        0xF86BFC
+
+#define mmTPC6_CFG_QM_TENSOR_9_PADDING_VALUE                         0xF86C00
+
+#define mmTPC6_CFG_QM_TENSOR_9_TENSOR_CONFIG                         0xF86C04
+
+#define mmTPC6_CFG_QM_TENSOR_9_DIM_0_SIZE                            0xF86C08
+
+#define mmTPC6_CFG_QM_TENSOR_9_DIM_0_STRIDE                          0xF86C0C
+
+#define mmTPC6_CFG_QM_TENSOR_9_DIM_1_SIZE                            0xF86C10
+
+#define mmTPC6_CFG_QM_TENSOR_9_DIM_1_STRIDE                          0xF86C14
+
+#define mmTPC6_CFG_QM_TENSOR_9_DIM_2_SIZE                            0xF86C18
+
+#define mmTPC6_CFG_QM_TENSOR_9_DIM_2_STRIDE                          0xF86C1C
+
+#define mmTPC6_CFG_QM_TENSOR_9_DIM_3_SIZE                            0xF86C20
+
+#define mmTPC6_CFG_QM_TENSOR_9_DIM_3_STRIDE                          0xF86C24
+
+#define mmTPC6_CFG_QM_TENSOR_9_DIM_4_SIZE                            0xF86C28
+
+#define mmTPC6_CFG_QM_TENSOR_9_DIM_4_STRIDE                          0xF86C2C
+
+#define mmTPC6_CFG_QM_TENSOR_10_BASE_ADDR_LOW                        0xF86C30
+
+#define mmTPC6_CFG_QM_TENSOR_10_BASE_ADDR_HIGH                       0xF86C34
+
+#define mmTPC6_CFG_QM_TENSOR_10_PADDING_VALUE                        0xF86C38
+
+#define mmTPC6_CFG_QM_TENSOR_10_TENSOR_CONFIG                        0xF86C3C
+
+#define mmTPC6_CFG_QM_TENSOR_10_DIM_0_SIZE                           0xF86C40
+
+#define mmTPC6_CFG_QM_TENSOR_10_DIM_0_STRIDE                         0xF86C44
+
+#define mmTPC6_CFG_QM_TENSOR_10_DIM_1_SIZE                           0xF86C48
+
+#define mmTPC6_CFG_QM_TENSOR_10_DIM_1_STRIDE                         0xF86C4C
+
+#define mmTPC6_CFG_QM_TENSOR_10_DIM_2_SIZE                           0xF86C50
+
+#define mmTPC6_CFG_QM_TENSOR_10_DIM_2_STRIDE                         0xF86C54
+
+#define mmTPC6_CFG_QM_TENSOR_10_DIM_3_SIZE                           0xF86C58
+
+#define mmTPC6_CFG_QM_TENSOR_10_DIM_3_STRIDE                         0xF86C5C
+
+#define mmTPC6_CFG_QM_TENSOR_10_DIM_4_SIZE                           0xF86C60
+
+#define mmTPC6_CFG_QM_TENSOR_10_DIM_4_STRIDE                         0xF86C64
+
+#define mmTPC6_CFG_QM_TENSOR_11_BASE_ADDR_LOW                        0xF86C68
+
+#define mmTPC6_CFG_QM_TENSOR_11_BASE_ADDR_HIGH                       0xF86C6C
+
+#define mmTPC6_CFG_QM_TENSOR_11_PADDING_VALUE                        0xF86C70
+
+#define mmTPC6_CFG_QM_TENSOR_11_TENSOR_CONFIG                        0xF86C74
+
+#define mmTPC6_CFG_QM_TENSOR_11_DIM_0_SIZE                           0xF86C78
+
+#define mmTPC6_CFG_QM_TENSOR_11_DIM_0_STRIDE                         0xF86C7C
+
+#define mmTPC6_CFG_QM_TENSOR_11_DIM_1_SIZE                           0xF86C80
+
+#define mmTPC6_CFG_QM_TENSOR_11_DIM_1_STRIDE                         0xF86C84
+
+#define mmTPC6_CFG_QM_TENSOR_11_DIM_2_SIZE                           0xF86C88
+
+#define mmTPC6_CFG_QM_TENSOR_11_DIM_2_STRIDE                         0xF86C8C
+
+#define mmTPC6_CFG_QM_TENSOR_11_DIM_3_SIZE                           0xF86C90
+
+#define mmTPC6_CFG_QM_TENSOR_11_DIM_3_STRIDE                         0xF86C94
+
+#define mmTPC6_CFG_QM_TENSOR_11_DIM_4_SIZE                           0xF86C98
+
+#define mmTPC6_CFG_QM_TENSOR_11_DIM_4_STRIDE                         0xF86C9C
+
+#define mmTPC6_CFG_QM_TENSOR_12_BASE_ADDR_LOW                        0xF86CA0
+
+#define mmTPC6_CFG_QM_TENSOR_12_BASE_ADDR_HIGH                       0xF86CA4
+
+#define mmTPC6_CFG_QM_TENSOR_12_PADDING_VALUE                        0xF86CA8
+
+#define mmTPC6_CFG_QM_TENSOR_12_TENSOR_CONFIG                        0xF86CAC
+
+#define mmTPC6_CFG_QM_TENSOR_12_DIM_0_SIZE                           0xF86CB0
+
+#define mmTPC6_CFG_QM_TENSOR_12_DIM_0_STRIDE                         0xF86CB4
+
+#define mmTPC6_CFG_QM_TENSOR_12_DIM_1_SIZE                           0xF86CB8
+
+#define mmTPC6_CFG_QM_TENSOR_12_DIM_1_STRIDE                         0xF86CBC
+
+#define mmTPC6_CFG_QM_TENSOR_12_DIM_2_SIZE                           0xF86CC0
+
+#define mmTPC6_CFG_QM_TENSOR_12_DIM_2_STRIDE                         0xF86CC4
+
+#define mmTPC6_CFG_QM_TENSOR_12_DIM_3_SIZE                           0xF86CC8
+
+#define mmTPC6_CFG_QM_TENSOR_12_DIM_3_STRIDE                         0xF86CCC
+
+#define mmTPC6_CFG_QM_TENSOR_12_DIM_4_SIZE                           0xF86CD0
+
+#define mmTPC6_CFG_QM_TENSOR_12_DIM_4_STRIDE                         0xF86CD4
+
+#define mmTPC6_CFG_QM_TENSOR_13_BASE_ADDR_LOW                        0xF86CD8
+
+#define mmTPC6_CFG_QM_TENSOR_13_BASE_ADDR_HIGH                       0xF86CDC
+
+#define mmTPC6_CFG_QM_TENSOR_13_PADDING_VALUE                        0xF86CE0
+
+#define mmTPC6_CFG_QM_TENSOR_13_TENSOR_CONFIG                        0xF86CE4
+
+#define mmTPC6_CFG_QM_TENSOR_13_DIM_0_SIZE                           0xF86CE8
+
+#define mmTPC6_CFG_QM_TENSOR_13_DIM_0_STRIDE                         0xF86CEC
+
+#define mmTPC6_CFG_QM_TENSOR_13_DIM_1_SIZE                           0xF86CF0
+
+#define mmTPC6_CFG_QM_TENSOR_13_DIM_1_STRIDE                         0xF86CF4
+
+#define mmTPC6_CFG_QM_TENSOR_13_DIM_2_SIZE                           0xF86CF8
+
+#define mmTPC6_CFG_QM_TENSOR_13_DIM_2_STRIDE                         0xF86CFC
+
+#define mmTPC6_CFG_QM_TENSOR_13_DIM_3_SIZE                           0xF86D00
+
+#define mmTPC6_CFG_QM_TENSOR_13_DIM_3_STRIDE                         0xF86D04
+
+#define mmTPC6_CFG_QM_TENSOR_13_DIM_4_SIZE                           0xF86D08
+
+#define mmTPC6_CFG_QM_TENSOR_13_DIM_4_STRIDE                         0xF86D0C
+
+#define mmTPC6_CFG_QM_TENSOR_14_BASE_ADDR_LOW                        0xF86D10
+
+#define mmTPC6_CFG_QM_TENSOR_14_BASE_ADDR_HIGH                       0xF86D14
+
+#define mmTPC6_CFG_QM_TENSOR_14_PADDING_VALUE                        0xF86D18
+
+#define mmTPC6_CFG_QM_TENSOR_14_TENSOR_CONFIG                        0xF86D1C
+
+#define mmTPC6_CFG_QM_TENSOR_14_DIM_0_SIZE                           0xF86D20
+
+#define mmTPC6_CFG_QM_TENSOR_14_DIM_0_STRIDE                         0xF86D24
+
+#define mmTPC6_CFG_QM_TENSOR_14_DIM_1_SIZE                           0xF86D28
+
+#define mmTPC6_CFG_QM_TENSOR_14_DIM_1_STRIDE                         0xF86D2C
+
+#define mmTPC6_CFG_QM_TENSOR_14_DIM_2_SIZE                           0xF86D30
+
+#define mmTPC6_CFG_QM_TENSOR_14_DIM_2_STRIDE                         0xF86D34
+
+#define mmTPC6_CFG_QM_TENSOR_14_DIM_3_SIZE                           0xF86D38
+
+#define mmTPC6_CFG_QM_TENSOR_14_DIM_3_STRIDE                         0xF86D3C
+
+#define mmTPC6_CFG_QM_TENSOR_14_DIM_4_SIZE                           0xF86D40
+
+#define mmTPC6_CFG_QM_TENSOR_14_DIM_4_STRIDE                         0xF86D44
+
+#define mmTPC6_CFG_QM_TENSOR_15_BASE_ADDR_LOW                        0xF86D48
+
+#define mmTPC6_CFG_QM_TENSOR_15_BASE_ADDR_HIGH                       0xF86D4C
+
+#define mmTPC6_CFG_QM_TENSOR_15_PADDING_VALUE                        0xF86D50
+
+#define mmTPC6_CFG_QM_TENSOR_15_TENSOR_CONFIG                        0xF86D54
+
+#define mmTPC6_CFG_QM_TENSOR_15_DIM_0_SIZE                           0xF86D58
+
+#define mmTPC6_CFG_QM_TENSOR_15_DIM_0_STRIDE                         0xF86D5C
+
+#define mmTPC6_CFG_QM_TENSOR_15_DIM_1_SIZE                           0xF86D60
+
+#define mmTPC6_CFG_QM_TENSOR_15_DIM_1_STRIDE                         0xF86D64
+
+#define mmTPC6_CFG_QM_TENSOR_15_DIM_2_SIZE                           0xF86D68
+
+#define mmTPC6_CFG_QM_TENSOR_15_DIM_2_STRIDE                         0xF86D6C
+
+#define mmTPC6_CFG_QM_TENSOR_15_DIM_3_SIZE                           0xF86D70
+
+#define mmTPC6_CFG_QM_TENSOR_15_DIM_3_STRIDE                         0xF86D74
+
+#define mmTPC6_CFG_QM_TENSOR_15_DIM_4_SIZE                           0xF86D78
+
+#define mmTPC6_CFG_QM_TENSOR_15_DIM_4_STRIDE                         0xF86D7C
+
+#define mmTPC6_CFG_QM_SYNC_OBJECT_MESSAGE                            0xF86D80
+
+#define mmTPC6_CFG_QM_SYNC_OBJECT_ADDR                               0xF86D84
+
+#define mmTPC6_CFG_QM_KERNEL_BASE_ADDRESS_LOW                        0xF86D88
+
+#define mmTPC6_CFG_QM_KERNEL_BASE_ADDRESS_HIGH                       0xF86D8C
+
+#define mmTPC6_CFG_QM_TID_BASE_DIM_0                                 0xF86D90
+
+#define mmTPC6_CFG_QM_TID_SIZE_DIM_0                                 0xF86D94
+
+#define mmTPC6_CFG_QM_TID_BASE_DIM_1                                 0xF86D98
+
+#define mmTPC6_CFG_QM_TID_SIZE_DIM_1                                 0xF86D9C
+
+#define mmTPC6_CFG_QM_TID_BASE_DIM_2                                 0xF86DA0
+
+#define mmTPC6_CFG_QM_TID_SIZE_DIM_2                                 0xF86DA4
+
+#define mmTPC6_CFG_QM_TID_BASE_DIM_3                                 0xF86DA8
+
+#define mmTPC6_CFG_QM_TID_SIZE_DIM_3                                 0xF86DAC
+
+#define mmTPC6_CFG_QM_TID_BASE_DIM_4                                 0xF86DB0
+
+#define mmTPC6_CFG_QM_TID_SIZE_DIM_4                                 0xF86DB4
+
+#define mmTPC6_CFG_QM_KERNEL_CONFIG                                  0xF86DB8
+
+#define mmTPC6_CFG_QM_KERNEL_ID                                      0xF86DBC
+
+#define mmTPC6_CFG_QM_SRF_0                                          0xF86DC0
+
+#define mmTPC6_CFG_QM_SRF_1                                          0xF86DC4
+
+#define mmTPC6_CFG_QM_SRF_2                                          0xF86DC8
+
+#define mmTPC6_CFG_QM_SRF_3                                          0xF86DCC
+
+#define mmTPC6_CFG_QM_SRF_4                                          0xF86DD0
+
+#define mmTPC6_CFG_QM_SRF_5                                          0xF86DD4
+
+#define mmTPC6_CFG_QM_SRF_6                                          0xF86DD8
+
+#define mmTPC6_CFG_QM_SRF_7                                          0xF86DDC
+
+#define mmTPC6_CFG_QM_SRF_8                                          0xF86DE0
+
+#define mmTPC6_CFG_QM_SRF_9                                          0xF86DE4
+
+#define mmTPC6_CFG_QM_SRF_10                                         0xF86DE8
+
+#define mmTPC6_CFG_QM_SRF_11                                         0xF86DEC
+
+#define mmTPC6_CFG_QM_SRF_12                                         0xF86DF0
+
+#define mmTPC6_CFG_QM_SRF_13                                         0xF86DF4
+
+#define mmTPC6_CFG_QM_SRF_14                                         0xF86DF8
+
+#define mmTPC6_CFG_QM_SRF_15                                         0xF86DFC
+
+#define mmTPC6_CFG_QM_SRF_16                                         0xF86E00
+
+#define mmTPC6_CFG_QM_SRF_17                                         0xF86E04
+
+#define mmTPC6_CFG_QM_SRF_18                                         0xF86E08
+
+#define mmTPC6_CFG_QM_SRF_19                                         0xF86E0C
+
+#define mmTPC6_CFG_QM_SRF_20                                         0xF86E10
+
+#define mmTPC6_CFG_QM_SRF_21                                         0xF86E14
+
+#define mmTPC6_CFG_QM_SRF_22                                         0xF86E18
+
+#define mmTPC6_CFG_QM_SRF_23                                         0xF86E1C
+
+#define mmTPC6_CFG_QM_SRF_24                                         0xF86E20
+
+#define mmTPC6_CFG_QM_SRF_25                                         0xF86E24
+
+#define mmTPC6_CFG_QM_SRF_26                                         0xF86E28
+
+#define mmTPC6_CFG_QM_SRF_27                                         0xF86E2C
+
+#define mmTPC6_CFG_QM_SRF_28                                         0xF86E30
+
+#define mmTPC6_CFG_QM_SRF_29                                         0xF86E34
+
+#define mmTPC6_CFG_QM_SRF_30                                         0xF86E38
+
+#define mmTPC6_CFG_QM_SRF_31                                         0xF86E3C
+
+#endif /* ASIC_REG_TPC6_CFG_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc6_qm_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc6_qm_regs.h
new file mode 100644
index 000000000000..e35ef7fd8b1c
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc6_qm_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_TPC6_QM_REGS_H_
+#define ASIC_REG_TPC6_QM_REGS_H_
+
+/*
+ *****************************************
+ *   TPC6_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmTPC6_QM_GLBL_CFG0                                          0xF88000
+
+#define mmTPC6_QM_GLBL_CFG1                                          0xF88004
+
+#define mmTPC6_QM_GLBL_PROT                                          0xF88008
+
+#define mmTPC6_QM_GLBL_ERR_CFG                                       0xF8800C
+
+#define mmTPC6_QM_GLBL_SECURE_PROPS_0                                0xF88010
+
+#define mmTPC6_QM_GLBL_SECURE_PROPS_1                                0xF88014
+
+#define mmTPC6_QM_GLBL_SECURE_PROPS_2                                0xF88018
+
+#define mmTPC6_QM_GLBL_SECURE_PROPS_3                                0xF8801C
+
+#define mmTPC6_QM_GLBL_SECURE_PROPS_4                                0xF88020
+
+#define mmTPC6_QM_GLBL_NON_SECURE_PROPS_0                            0xF88024
+
+#define mmTPC6_QM_GLBL_NON_SECURE_PROPS_1                            0xF88028
+
+#define mmTPC6_QM_GLBL_NON_SECURE_PROPS_2                            0xF8802C
+
+#define mmTPC6_QM_GLBL_NON_SECURE_PROPS_3                            0xF88030
+
+#define mmTPC6_QM_GLBL_NON_SECURE_PROPS_4                            0xF88034
+
+#define mmTPC6_QM_GLBL_STS0                                          0xF88038
+
+#define mmTPC6_QM_GLBL_STS1_0                                        0xF88040
+
+#define mmTPC6_QM_GLBL_STS1_1                                        0xF88044
+
+#define mmTPC6_QM_GLBL_STS1_2                                        0xF88048
+
+#define mmTPC6_QM_GLBL_STS1_3                                        0xF8804C
+
+#define mmTPC6_QM_GLBL_STS1_4                                        0xF88050
+
+#define mmTPC6_QM_GLBL_MSG_EN_0                                      0xF88054
+
+#define mmTPC6_QM_GLBL_MSG_EN_1                                      0xF88058
+
+#define mmTPC6_QM_GLBL_MSG_EN_2                                      0xF8805C
+
+#define mmTPC6_QM_GLBL_MSG_EN_3                                      0xF88060
+
+#define mmTPC6_QM_GLBL_MSG_EN_4                                      0xF88068
+
+#define mmTPC6_QM_PQ_BASE_LO_0                                       0xF88070
+
+#define mmTPC6_QM_PQ_BASE_LO_1                                       0xF88074
+
+#define mmTPC6_QM_PQ_BASE_LO_2                                       0xF88078
+
+#define mmTPC6_QM_PQ_BASE_LO_3                                       0xF8807C
+
+#define mmTPC6_QM_PQ_BASE_HI_0                                       0xF88080
+
+#define mmTPC6_QM_PQ_BASE_HI_1                                       0xF88084
+
+#define mmTPC6_QM_PQ_BASE_HI_2                                       0xF88088
+
+#define mmTPC6_QM_PQ_BASE_HI_3                                       0xF8808C
+
+#define mmTPC6_QM_PQ_SIZE_0                                          0xF88090
+
+#define mmTPC6_QM_PQ_SIZE_1                                          0xF88094
+
+#define mmTPC6_QM_PQ_SIZE_2                                          0xF88098
+
+#define mmTPC6_QM_PQ_SIZE_3                                          0xF8809C
+
+#define mmTPC6_QM_PQ_PI_0                                            0xF880A0
+
+#define mmTPC6_QM_PQ_PI_1                                            0xF880A4
+
+#define mmTPC6_QM_PQ_PI_2                                            0xF880A8
+
+#define mmTPC6_QM_PQ_PI_3                                            0xF880AC
+
+#define mmTPC6_QM_PQ_CI_0                                            0xF880B0
+
+#define mmTPC6_QM_PQ_CI_1                                            0xF880B4
+
+#define mmTPC6_QM_PQ_CI_2                                            0xF880B8
+
+#define mmTPC6_QM_PQ_CI_3                                            0xF880BC
+
+#define mmTPC6_QM_PQ_CFG0_0                                          0xF880C0
+
+#define mmTPC6_QM_PQ_CFG0_1                                          0xF880C4
+
+#define mmTPC6_QM_PQ_CFG0_2                                          0xF880C8
+
+#define mmTPC6_QM_PQ_CFG0_3                                          0xF880CC
+
+#define mmTPC6_QM_PQ_CFG1_0                                          0xF880D0
+
+#define mmTPC6_QM_PQ_CFG1_1                                          0xF880D4
+
+#define mmTPC6_QM_PQ_CFG1_2                                          0xF880D8
+
+#define mmTPC6_QM_PQ_CFG1_3                                          0xF880DC
+
+#define mmTPC6_QM_PQ_ARUSER_31_11_0                                  0xF880E0
+
+#define mmTPC6_QM_PQ_ARUSER_31_11_1                                  0xF880E4
+
+#define mmTPC6_QM_PQ_ARUSER_31_11_2                                  0xF880E8
+
+#define mmTPC6_QM_PQ_ARUSER_31_11_3                                  0xF880EC
+
+#define mmTPC6_QM_PQ_STS0_0                                          0xF880F0
+
+#define mmTPC6_QM_PQ_STS0_1                                          0xF880F4
+
+#define mmTPC6_QM_PQ_STS0_2                                          0xF880F8
+
+#define mmTPC6_QM_PQ_STS0_3                                          0xF880FC
+
+#define mmTPC6_QM_PQ_STS1_0                                          0xF88100
+
+#define mmTPC6_QM_PQ_STS1_1                                          0xF88104
+
+#define mmTPC6_QM_PQ_STS1_2                                          0xF88108
+
+#define mmTPC6_QM_PQ_STS1_3                                          0xF8810C
+
+#define mmTPC6_QM_CQ_CFG0_0                                          0xF88110
+
+#define mmTPC6_QM_CQ_CFG0_1                                          0xF88114
+
+#define mmTPC6_QM_CQ_CFG0_2                                          0xF88118
+
+#define mmTPC6_QM_CQ_CFG0_3                                          0xF8811C
+
+#define mmTPC6_QM_CQ_CFG0_4                                          0xF88120
+
+#define mmTPC6_QM_CQ_CFG1_0                                          0xF88124
+
+#define mmTPC6_QM_CQ_CFG1_1                                          0xF88128
+
+#define mmTPC6_QM_CQ_CFG1_2                                          0xF8812C
+
+#define mmTPC6_QM_CQ_CFG1_3                                          0xF88130
+
+#define mmTPC6_QM_CQ_CFG1_4                                          0xF88134
+
+#define mmTPC6_QM_CQ_ARUSER_31_11_0                                  0xF88138
+
+#define mmTPC6_QM_CQ_ARUSER_31_11_1                                  0xF8813C
+
+#define mmTPC6_QM_CQ_ARUSER_31_11_2                                  0xF88140
+
+#define mmTPC6_QM_CQ_ARUSER_31_11_3                                  0xF88144
+
+#define mmTPC6_QM_CQ_ARUSER_31_11_4                                  0xF88148
+
+#define mmTPC6_QM_CQ_STS0_0                                          0xF8814C
+
+#define mmTPC6_QM_CQ_STS0_1                                          0xF88150
+
+#define mmTPC6_QM_CQ_STS0_2                                          0xF88154
+
+#define mmTPC6_QM_CQ_STS0_3                                          0xF88158
+
+#define mmTPC6_QM_CQ_STS0_4                                          0xF8815C
+
+#define mmTPC6_QM_CQ_STS1_0                                          0xF88160
+
+#define mmTPC6_QM_CQ_STS1_1                                          0xF88164
+
+#define mmTPC6_QM_CQ_STS1_2                                          0xF88168
+
+#define mmTPC6_QM_CQ_STS1_3                                          0xF8816C
+
+#define mmTPC6_QM_CQ_STS1_4                                          0xF88170
+
+#define mmTPC6_QM_CQ_PTR_LO_0                                        0xF88174
+
+#define mmTPC6_QM_CQ_PTR_HI_0                                        0xF88178
+
+#define mmTPC6_QM_CQ_TSIZE_0                                         0xF8817C
+
+#define mmTPC6_QM_CQ_CTL_0                                           0xF88180
+
+#define mmTPC6_QM_CQ_PTR_LO_1                                        0xF88184
+
+#define mmTPC6_QM_CQ_PTR_HI_1                                        0xF88188
+
+#define mmTPC6_QM_CQ_TSIZE_1                                         0xF8818C
+
+#define mmTPC6_QM_CQ_CTL_1                                           0xF88190
+
+#define mmTPC6_QM_CQ_PTR_LO_2                                        0xF88194
+
+#define mmTPC6_QM_CQ_PTR_HI_2                                        0xF88198
+
+#define mmTPC6_QM_CQ_TSIZE_2                                         0xF8819C
+
+#define mmTPC6_QM_CQ_CTL_2                                           0xF881A0
+
+#define mmTPC6_QM_CQ_PTR_LO_3                                        0xF881A4
+
+#define mmTPC6_QM_CQ_PTR_HI_3                                        0xF881A8
+
+#define mmTPC6_QM_CQ_TSIZE_3                                         0xF881AC
+
+#define mmTPC6_QM_CQ_CTL_3                                           0xF881B0
+
+#define mmTPC6_QM_CQ_PTR_LO_4                                        0xF881B4
+
+#define mmTPC6_QM_CQ_PTR_HI_4                                        0xF881B8
+
+#define mmTPC6_QM_CQ_TSIZE_4                                         0xF881BC
+
+#define mmTPC6_QM_CQ_CTL_4                                           0xF881C0
+
+#define mmTPC6_QM_CQ_PTR_LO_STS_0                                    0xF881C4
+
+#define mmTPC6_QM_CQ_PTR_LO_STS_1                                    0xF881C8
+
+#define mmTPC6_QM_CQ_PTR_LO_STS_2                                    0xF881CC
+
+#define mmTPC6_QM_CQ_PTR_LO_STS_3                                    0xF881D0
+
+#define mmTPC6_QM_CQ_PTR_LO_STS_4                                    0xF881D4
+
+#define mmTPC6_QM_CQ_PTR_HI_STS_0                                    0xF881D8
+
+#define mmTPC6_QM_CQ_PTR_HI_STS_1                                    0xF881DC
+
+#define mmTPC6_QM_CQ_PTR_HI_STS_2                                    0xF881E0
+
+#define mmTPC6_QM_CQ_PTR_HI_STS_3                                    0xF881E4
+
+#define mmTPC6_QM_CQ_PTR_HI_STS_4                                    0xF881E8
+
+#define mmTPC6_QM_CQ_TSIZE_STS_0                                     0xF881EC
+
+#define mmTPC6_QM_CQ_TSIZE_STS_1                                     0xF881F0
+
+#define mmTPC6_QM_CQ_TSIZE_STS_2                                     0xF881F4
+
+#define mmTPC6_QM_CQ_TSIZE_STS_3                                     0xF881F8
+
+#define mmTPC6_QM_CQ_TSIZE_STS_4                                     0xF881FC
+
+#define mmTPC6_QM_CQ_CTL_STS_0                                       0xF88200
+
+#define mmTPC6_QM_CQ_CTL_STS_1                                       0xF88204
+
+#define mmTPC6_QM_CQ_CTL_STS_2                                       0xF88208
+
+#define mmTPC6_QM_CQ_CTL_STS_3                                       0xF8820C
+
+#define mmTPC6_QM_CQ_CTL_STS_4                                       0xF88210
+
+#define mmTPC6_QM_CQ_IFIFO_CNT_0                                     0xF88214
+
+#define mmTPC6_QM_CQ_IFIFO_CNT_1                                     0xF88218
+
+#define mmTPC6_QM_CQ_IFIFO_CNT_2                                     0xF8821C
+
+#define mmTPC6_QM_CQ_IFIFO_CNT_3                                     0xF88220
+
+#define mmTPC6_QM_CQ_IFIFO_CNT_4                                     0xF88224
+
+#define mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_0                             0xF88228
+
+#define mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_1                             0xF8822C
+
+#define mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_2                             0xF88230
+
+#define mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_3                             0xF88234
+
+#define mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_4                             0xF88238
+
+#define mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_0                             0xF8823C
+
+#define mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_1                             0xF88240
+
+#define mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_2                             0xF88244
+
+#define mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_3                             0xF88248
+
+#define mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_4                             0xF8824C
+
+#define mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_0                             0xF88250
+
+#define mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_1                             0xF88254
+
+#define mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_2                             0xF88258
+
+#define mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_3                             0xF8825C
+
+#define mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_4                             0xF88260
+
+#define mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_0                             0xF88264
+
+#define mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_1                             0xF88268
+
+#define mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_2                             0xF8826C
+
+#define mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_3                             0xF88270
+
+#define mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_4                             0xF88274
+
+#define mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_0                             0xF88278
+
+#define mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_1                             0xF8827C
+
+#define mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_2                             0xF88280
+
+#define mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_3                             0xF88284
+
+#define mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_4                             0xF88288
+
+#define mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_0                             0xF8828C
+
+#define mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_1                             0xF88290
+
+#define mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_2                             0xF88294
+
+#define mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_3                             0xF88298
+
+#define mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_4                             0xF8829C
+
+#define mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_0                             0xF882A0
+
+#define mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_1                             0xF882A4
+
+#define mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_2                             0xF882A8
+
+#define mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_3                             0xF882AC
+
+#define mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_4                             0xF882B0
+
+#define mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_0                             0xF882B4
+
+#define mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_1                             0xF882B8
+
+#define mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_2                             0xF882BC
+
+#define mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_3                             0xF882C0
+
+#define mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_4                             0xF882C4
+
+#define mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_0                             0xF882C8
+
+#define mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_1                             0xF882CC
+
+#define mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_2                             0xF882D0
+
+#define mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_3                             0xF882D4
+
+#define mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_4                             0xF882D8
+
+#define mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0                       0xF882E0
+
+#define mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1                       0xF882E4
+
+#define mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2                       0xF882E8
+
+#define mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3                       0xF882EC
+
+#define mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4                       0xF882F0
+
+#define mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_0                       0xF882F4
+
+#define mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_1                       0xF882F8
+
+#define mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_2                       0xF882FC
+
+#define mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3                       0xF88300
+
+#define mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_4                       0xF88304
+
+#define mmTPC6_QM_CP_FENCE0_RDATA_0                                  0xF88308
+
+#define mmTPC6_QM_CP_FENCE0_RDATA_1                                  0xF8830C
+
+#define mmTPC6_QM_CP_FENCE0_RDATA_2                                  0xF88310
+
+#define mmTPC6_QM_CP_FENCE0_RDATA_3                                  0xF88314
+
+#define mmTPC6_QM_CP_FENCE0_RDATA_4                                  0xF88318
+
+#define mmTPC6_QM_CP_FENCE1_RDATA_0                                  0xF8831C
+
+#define mmTPC6_QM_CP_FENCE1_RDATA_1                                  0xF88320
+
+#define mmTPC6_QM_CP_FENCE1_RDATA_2                                  0xF88324
+
+#define mmTPC6_QM_CP_FENCE1_RDATA_3                                  0xF88328
+
+#define mmTPC6_QM_CP_FENCE1_RDATA_4                                  0xF8832C
+
+#define mmTPC6_QM_CP_FENCE2_RDATA_0                                  0xF88330
+
+#define mmTPC6_QM_CP_FENCE2_RDATA_1                                  0xF88334
+
+#define mmTPC6_QM_CP_FENCE2_RDATA_2                                  0xF88338
+
+#define mmTPC6_QM_CP_FENCE2_RDATA_3                                  0xF8833C
+
+#define mmTPC6_QM_CP_FENCE2_RDATA_4                                  0xF88340
+
+#define mmTPC6_QM_CP_FENCE3_RDATA_0                                  0xF88344
+
+#define mmTPC6_QM_CP_FENCE3_RDATA_1                                  0xF88348
+
+#define mmTPC6_QM_CP_FENCE3_RDATA_2                                  0xF8834C
+
+#define mmTPC6_QM_CP_FENCE3_RDATA_3                                  0xF88350
+
+#define mmTPC6_QM_CP_FENCE3_RDATA_4                                  0xF88354
+
+#define mmTPC6_QM_CP_FENCE0_CNT_0                                    0xF88358
+
+#define mmTPC6_QM_CP_FENCE0_CNT_1                                    0xF8835C
+
+#define mmTPC6_QM_CP_FENCE0_CNT_2                                    0xF88360
+
+#define mmTPC6_QM_CP_FENCE0_CNT_3                                    0xF88364
+
+#define mmTPC6_QM_CP_FENCE0_CNT_4                                    0xF88368
+
+#define mmTPC6_QM_CP_FENCE1_CNT_0                                    0xF8836C
+
+#define mmTPC6_QM_CP_FENCE1_CNT_1                                    0xF88370
+
+#define mmTPC6_QM_CP_FENCE1_CNT_2                                    0xF88374
+
+#define mmTPC6_QM_CP_FENCE1_CNT_3                                    0xF88378
+
+#define mmTPC6_QM_CP_FENCE1_CNT_4                                    0xF8837C
+
+#define mmTPC6_QM_CP_FENCE2_CNT_0                                    0xF88380
+
+#define mmTPC6_QM_CP_FENCE2_CNT_1                                    0xF88384
+
+#define mmTPC6_QM_CP_FENCE2_CNT_2                                    0xF88388
+
+#define mmTPC6_QM_CP_FENCE2_CNT_3                                    0xF8838C
+
+#define mmTPC6_QM_CP_FENCE2_CNT_4                                    0xF88390
+
+#define mmTPC6_QM_CP_FENCE3_CNT_0                                    0xF88394
+
+#define mmTPC6_QM_CP_FENCE3_CNT_1                                    0xF88398
+
+#define mmTPC6_QM_CP_FENCE3_CNT_2                                    0xF8839C
+
+#define mmTPC6_QM_CP_FENCE3_CNT_3                                    0xF883A0
+
+#define mmTPC6_QM_CP_FENCE3_CNT_4                                    0xF883A4
+
+#define mmTPC6_QM_CP_STS_0                                           0xF883A8
+
+#define mmTPC6_QM_CP_STS_1                                           0xF883AC
+
+#define mmTPC6_QM_CP_STS_2                                           0xF883B0
+
+#define mmTPC6_QM_CP_STS_3                                           0xF883B4
+
+#define mmTPC6_QM_CP_STS_4                                           0xF883B8
+
+#define mmTPC6_QM_CP_CURRENT_INST_LO_0                               0xF883BC
+
+#define mmTPC6_QM_CP_CURRENT_INST_LO_1                               0xF883C0
+
+#define mmTPC6_QM_CP_CURRENT_INST_LO_2                               0xF883C4
+
+#define mmTPC6_QM_CP_CURRENT_INST_LO_3                               0xF883C8
+
+#define mmTPC6_QM_CP_CURRENT_INST_LO_4                               0xF883CC
+
+#define mmTPC6_QM_CP_CURRENT_INST_HI_0                               0xF883D0
+
+#define mmTPC6_QM_CP_CURRENT_INST_HI_1                               0xF883D4
+
+#define mmTPC6_QM_CP_CURRENT_INST_HI_2                               0xF883D8
+
+#define mmTPC6_QM_CP_CURRENT_INST_HI_3                               0xF883DC
+
+#define mmTPC6_QM_CP_CURRENT_INST_HI_4                               0xF883E0
+
+#define mmTPC6_QM_CP_BARRIER_CFG_0                                   0xF883F4
+
+#define mmTPC6_QM_CP_BARRIER_CFG_1                                   0xF883F8
+
+#define mmTPC6_QM_CP_BARRIER_CFG_2                                   0xF883FC
+
+#define mmTPC6_QM_CP_BARRIER_CFG_3                                   0xF88400
+
+#define mmTPC6_QM_CP_BARRIER_CFG_4                                   0xF88404
+
+#define mmTPC6_QM_CP_DBG_0_0                                         0xF88408
+
+#define mmTPC6_QM_CP_DBG_0_1                                         0xF8840C
+
+#define mmTPC6_QM_CP_DBG_0_2                                         0xF88410
+
+#define mmTPC6_QM_CP_DBG_0_3                                         0xF88414
+
+#define mmTPC6_QM_CP_DBG_0_4                                         0xF88418
+
+#define mmTPC6_QM_CP_ARUSER_31_11_0                                  0xF8841C
+
+#define mmTPC6_QM_CP_ARUSER_31_11_1                                  0xF88420
+
+#define mmTPC6_QM_CP_ARUSER_31_11_2                                  0xF88424
+
+#define mmTPC6_QM_CP_ARUSER_31_11_3                                  0xF88428
+
+#define mmTPC6_QM_CP_ARUSER_31_11_4                                  0xF8842C
+
+#define mmTPC6_QM_CP_AWUSER_31_11_0                                  0xF88430
+
+#define mmTPC6_QM_CP_AWUSER_31_11_1                                  0xF88434
+
+#define mmTPC6_QM_CP_AWUSER_31_11_2                                  0xF88438
+
+#define mmTPC6_QM_CP_AWUSER_31_11_3                                  0xF8843C
+
+#define mmTPC6_QM_CP_AWUSER_31_11_4                                  0xF88440
+
+#define mmTPC6_QM_ARB_CFG_0                                          0xF88A00
+
+#define mmTPC6_QM_ARB_CHOISE_Q_PUSH                                  0xF88A04
+
+#define mmTPC6_QM_ARB_WRR_WEIGHT_0                                   0xF88A08
+
+#define mmTPC6_QM_ARB_WRR_WEIGHT_1                                   0xF88A0C
+
+#define mmTPC6_QM_ARB_WRR_WEIGHT_2                                   0xF88A10
+
+#define mmTPC6_QM_ARB_WRR_WEIGHT_3                                   0xF88A14
+
+#define mmTPC6_QM_ARB_CFG_1                                          0xF88A18
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_0                               0xF88A20
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_1                               0xF88A24
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_2                               0xF88A28
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_3                               0xF88A2C
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_4                               0xF88A30
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_5                               0xF88A34
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_6                               0xF88A38
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_7                               0xF88A3C
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_8                               0xF88A40
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_9                               0xF88A44
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_10                              0xF88A48
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_11                              0xF88A4C
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_12                              0xF88A50
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_13                              0xF88A54
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_14                              0xF88A58
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_15                              0xF88A5C
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_16                              0xF88A60
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_17                              0xF88A64
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_18                              0xF88A68
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_19                              0xF88A6C
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_20                              0xF88A70
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_21                              0xF88A74
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_22                              0xF88A78
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_23                              0xF88A7C
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_24                              0xF88A80
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_25                              0xF88A84
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_26                              0xF88A88
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_27                              0xF88A8C
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_28                              0xF88A90
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_29                              0xF88A94
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_30                              0xF88A98
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_31                              0xF88A9C
+
+#define mmTPC6_QM_ARB_MST_CRED_INC                                   0xF88AA0
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_0                         0xF88AA4
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_1                         0xF88AA8
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_2                         0xF88AAC
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_3                         0xF88AB0
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_4                         0xF88AB4
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_5                         0xF88AB8
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_6                         0xF88ABC
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_7                         0xF88AC0
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_8                         0xF88AC4
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_9                         0xF88AC8
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_10                        0xF88ACC
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_11                        0xF88AD0
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_12                        0xF88AD4
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_13                        0xF88AD8
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_14                        0xF88ADC
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_15                        0xF88AE0
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_16                        0xF88AE4
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_17                        0xF88AE8
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_18                        0xF88AEC
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_19                        0xF88AF0
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_20                        0xF88AF4
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_21                        0xF88AF8
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_22                        0xF88AFC
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_23                        0xF88B00
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_24                        0xF88B04
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_25                        0xF88B08
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_26                        0xF88B0C
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_27                        0xF88B10
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_28                        0xF88B14
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_29                        0xF88B18
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_30                        0xF88B1C
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_31                        0xF88B20
+
+#define mmTPC6_QM_ARB_SLV_MASTER_INC_CRED_OFST                       0xF88B28
+
+#define mmTPC6_QM_ARB_MST_SLAVE_EN                                   0xF88B2C
+
+#define mmTPC6_QM_ARB_MST_QUIET_PER                                  0xF88B34
+
+#define mmTPC6_QM_ARB_SLV_CHOISE_WDT                                 0xF88B38
+
+#define mmTPC6_QM_ARB_SLV_ID                                         0xF88B3C
+
+#define mmTPC6_QM_ARB_MSG_MAX_INFLIGHT                               0xF88B44
+
+#define mmTPC6_QM_ARB_MSG_AWUSER_31_11                               0xF88B48
+
+#define mmTPC6_QM_ARB_MSG_AWUSER_SEC_PROP                            0xF88B4C
+
+#define mmTPC6_QM_ARB_MSG_AWUSER_NON_SEC_PROP                        0xF88B50
+
+#define mmTPC6_QM_ARB_BASE_LO                                        0xF88B54
+
+#define mmTPC6_QM_ARB_BASE_HI                                        0xF88B58
+
+#define mmTPC6_QM_ARB_STATE_STS                                      0xF88B80
+
+#define mmTPC6_QM_ARB_CHOISE_FULLNESS_STS                            0xF88B84
+
+#define mmTPC6_QM_ARB_MSG_STS                                        0xF88B88
+
+#define mmTPC6_QM_ARB_SLV_CHOISE_Q_HEAD                              0xF88B8C
+
+#define mmTPC6_QM_ARB_ERR_CAUSE                                      0xF88B9C
+
+#define mmTPC6_QM_ARB_ERR_MSG_EN                                     0xF88BA0
+
+#define mmTPC6_QM_ARB_ERR_STS_DRP                                    0xF88BA8
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_0                                 0xF88BB0
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_1                                 0xF88BB4
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_2                                 0xF88BB8
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_3                                 0xF88BBC
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_4                                 0xF88BC0
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_5                                 0xF88BC4
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_6                                 0xF88BC8
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_7                                 0xF88BCC
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_8                                 0xF88BD0
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_9                                 0xF88BD4
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_10                                0xF88BD8
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_11                                0xF88BDC
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_12                                0xF88BE0
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_13                                0xF88BE4
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_14                                0xF88BE8
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_15                                0xF88BEC
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_16                                0xF88BF0
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_17                                0xF88BF4
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_18                                0xF88BF8
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_19                                0xF88BFC
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_20                                0xF88C00
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_21                                0xF88C04
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_22                                0xF88C08
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_23                                0xF88C0C
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_24                                0xF88C10
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_25                                0xF88C14
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_26                                0xF88C18
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_27                                0xF88C1C
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_28                                0xF88C20
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_29                                0xF88C24
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_30                                0xF88C28
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_31                                0xF88C2C
+
+#define mmTPC6_QM_CGM_CFG                                            0xF88C70
+
+#define mmTPC6_QM_CGM_STS                                            0xF88C74
+
+#define mmTPC6_QM_CGM_CFG1                                           0xF88C78
+
+#define mmTPC6_QM_LOCAL_RANGE_BASE                                   0xF88C80
+
+#define mmTPC6_QM_LOCAL_RANGE_SIZE                                   0xF88C84
+
+#define mmTPC6_QM_CSMR_STRICT_PRIO_CFG                               0xF88C90
+
+#define mmTPC6_QM_HBW_RD_RATE_LIM_CFG_1                              0xF88C94
+
+#define mmTPC6_QM_LBW_WR_RATE_LIM_CFG_0                              0xF88C98
+
+#define mmTPC6_QM_LBW_WR_RATE_LIM_CFG_1                              0xF88C9C
+
+#define mmTPC6_QM_HBW_RD_RATE_LIM_CFG_0                              0xF88CA0
+
+#define mmTPC6_QM_GLBL_AXCACHE                                       0xF88CA4
+
+#define mmTPC6_QM_IND_GW_APB_CFG                                     0xF88CB0
+
+#define mmTPC6_QM_IND_GW_APB_WDATA                                   0xF88CB4
+
+#define mmTPC6_QM_IND_GW_APB_RDATA                                   0xF88CB8
+
+#define mmTPC6_QM_IND_GW_APB_STATUS                                  0xF88CBC
+
+#define mmTPC6_QM_GLBL_ERR_ADDR_LO                                   0xF88CD0
+
+#define mmTPC6_QM_GLBL_ERR_ADDR_HI                                   0xF88CD4
+
+#define mmTPC6_QM_GLBL_ERR_WDATA                                     0xF88CD8
+
+#define mmTPC6_QM_GLBL_MEM_INIT_BUSY                                 0xF88D00
+
+#endif /* ASIC_REG_TPC6_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc7_cfg_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc7_cfg_regs.h
new file mode 100644
index 000000000000..1887b10e58e2
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc7_cfg_regs.h
@@ -0,0 +1,1226 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_TPC7_CFG_REGS_H_
+#define ASIC_REG_TPC7_CFG_REGS_H_
+
+/*
+ *****************************************
+ *   TPC7_CFG (Prototype: TPC)
+ *****************************************
+ */
+
+#define mmTPC7_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW                     0xFC6400
+
+#define mmTPC7_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH                    0xFC6404
+
+#define mmTPC7_CFG_KERNEL_TENSOR_0_PADDING_VALUE                     0xFC6408
+
+#define mmTPC7_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG                     0xFC640C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_0_SIZE                        0xFC6410
+
+#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE                      0xFC6414
+
+#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_1_SIZE                        0xFC6418
+
+#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE                      0xFC641C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_2_SIZE                        0xFC6420
+
+#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE                      0xFC6424
+
+#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_3_SIZE                        0xFC6428
+
+#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE                      0xFC642C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_4_SIZE                        0xFC6430
+
+#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE                      0xFC6434
+
+#define mmTPC7_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW                     0xFC6438
+
+#define mmTPC7_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH                    0xFC643C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_1_PADDING_VALUE                     0xFC6440
+
+#define mmTPC7_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG                     0xFC6444
+
+#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_0_SIZE                        0xFC6448
+
+#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE                      0xFC644C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_1_SIZE                        0xFC6450
+
+#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE                      0xFC6454
+
+#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_2_SIZE                        0xFC6458
+
+#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE                      0xFC645C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_3_SIZE                        0xFC6460
+
+#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE                      0xFC6464
+
+#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_4_SIZE                        0xFC6468
+
+#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE                      0xFC646C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW                     0xFC6470
+
+#define mmTPC7_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH                    0xFC6474
+
+#define mmTPC7_CFG_KERNEL_TENSOR_2_PADDING_VALUE                     0xFC6478
+
+#define mmTPC7_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG                     0xFC647C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_0_SIZE                        0xFC6480
+
+#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE                      0xFC6484
+
+#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_1_SIZE                        0xFC6488
+
+#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE                      0xFC648C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_2_SIZE                        0xFC6490
+
+#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE                      0xFC6494
+
+#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_3_SIZE                        0xFC6498
+
+#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE                      0xFC649C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_4_SIZE                        0xFC64A0
+
+#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE                      0xFC64A4
+
+#define mmTPC7_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW                     0xFC64A8
+
+#define mmTPC7_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH                    0xFC64AC
+
+#define mmTPC7_CFG_KERNEL_TENSOR_3_PADDING_VALUE                     0xFC64B0
+
+#define mmTPC7_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG                     0xFC64B4
+
+#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_0_SIZE                        0xFC64B8
+
+#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE                      0xFC64BC
+
+#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_1_SIZE                        0xFC64C0
+
+#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE                      0xFC64C4
+
+#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_2_SIZE                        0xFC64C8
+
+#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE                      0xFC64CC
+
+#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_3_SIZE                        0xFC64D0
+
+#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE                      0xFC64D4
+
+#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_4_SIZE                        0xFC64D8
+
+#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE                      0xFC64DC
+
+#define mmTPC7_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW                     0xFC64E0
+
+#define mmTPC7_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH                    0xFC64E4
+
+#define mmTPC7_CFG_KERNEL_TENSOR_4_PADDING_VALUE                     0xFC64E8
+
+#define mmTPC7_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG                     0xFC64EC
+
+#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_0_SIZE                        0xFC64F0
+
+#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE                      0xFC64F4
+
+#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_1_SIZE                        0xFC64F8
+
+#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE                      0xFC64FC
+
+#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_2_SIZE                        0xFC6500
+
+#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE                      0xFC6504
+
+#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_3_SIZE                        0xFC6508
+
+#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE                      0xFC650C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_4_SIZE                        0xFC6510
+
+#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE                      0xFC6514
+
+#define mmTPC7_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW                     0xFC6518
+
+#define mmTPC7_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH                    0xFC651C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_5_PADDING_VALUE                     0xFC6520
+
+#define mmTPC7_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG                     0xFC6524
+
+#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_0_SIZE                        0xFC6528
+
+#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE                      0xFC652C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_1_SIZE                        0xFC6530
+
+#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE                      0xFC6534
+
+#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_2_SIZE                        0xFC6538
+
+#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE                      0xFC653C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_3_SIZE                        0xFC6540
+
+#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE                      0xFC6544
+
+#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_4_SIZE                        0xFC6548
+
+#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE                      0xFC654C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW                     0xFC6550
+
+#define mmTPC7_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH                    0xFC6554
+
+#define mmTPC7_CFG_KERNEL_TENSOR_6_PADDING_VALUE                     0xFC6558
+
+#define mmTPC7_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG                     0xFC655C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_0_SIZE                        0xFC6560
+
+#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE                      0xFC6564
+
+#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_1_SIZE                        0xFC6568
+
+#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE                      0xFC656C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_2_SIZE                        0xFC6570
+
+#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE                      0xFC6574
+
+#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_3_SIZE                        0xFC6578
+
+#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE                      0xFC657C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_4_SIZE                        0xFC6580
+
+#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE                      0xFC6584
+
+#define mmTPC7_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW                     0xFC6588
+
+#define mmTPC7_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH                    0xFC658C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_7_PADDING_VALUE                     0xFC6590
+
+#define mmTPC7_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG                     0xFC6594
+
+#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_0_SIZE                        0xFC6598
+
+#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE                      0xFC659C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_1_SIZE                        0xFC65A0
+
+#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE                      0xFC65A4
+
+#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_2_SIZE                        0xFC65A8
+
+#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE                      0xFC65AC
+
+#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_3_SIZE                        0xFC65B0
+
+#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE                      0xFC65B4
+
+#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_4_SIZE                        0xFC65B8
+
+#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE                      0xFC65BC
+
+#define mmTPC7_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW                     0xFC65C0
+
+#define mmTPC7_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH                    0xFC65C4
+
+#define mmTPC7_CFG_KERNEL_TENSOR_8_PADDING_VALUE                     0xFC65C8
+
+#define mmTPC7_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG                     0xFC65CC
+
+#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_0_SIZE                        0xFC65D0
+
+#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE                      0xFC65D4
+
+#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_1_SIZE                        0xFC65D8
+
+#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE                      0xFC65DC
+
+#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_2_SIZE                        0xFC65E0
+
+#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE                      0xFC65E4
+
+#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_3_SIZE                        0xFC65E8
+
+#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE                      0xFC65EC
+
+#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_4_SIZE                        0xFC65F0
+
+#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE                      0xFC65F4
+
+#define mmTPC7_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW                     0xFC65F8
+
+#define mmTPC7_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH                    0xFC65FC
+
+#define mmTPC7_CFG_KERNEL_TENSOR_9_PADDING_VALUE                     0xFC6600
+
+#define mmTPC7_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG                     0xFC6604
+
+#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_0_SIZE                        0xFC6608
+
+#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE                      0xFC660C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_1_SIZE                        0xFC6610
+
+#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE                      0xFC6614
+
+#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_2_SIZE                        0xFC6618
+
+#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE                      0xFC661C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_3_SIZE                        0xFC6620
+
+#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE                      0xFC6624
+
+#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_4_SIZE                        0xFC6628
+
+#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE                      0xFC662C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW                    0xFC6630
+
+#define mmTPC7_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH                   0xFC6634
+
+#define mmTPC7_CFG_KERNEL_TENSOR_10_PADDING_VALUE                    0xFC6638
+
+#define mmTPC7_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG                    0xFC663C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_0_SIZE                       0xFC6640
+
+#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE                     0xFC6644
+
+#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_1_SIZE                       0xFC6648
+
+#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE                     0xFC664C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_2_SIZE                       0xFC6650
+
+#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE                     0xFC6654
+
+#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_3_SIZE                       0xFC6658
+
+#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE                     0xFC665C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_4_SIZE                       0xFC6660
+
+#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE                     0xFC6664
+
+#define mmTPC7_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW                    0xFC6668
+
+#define mmTPC7_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH                   0xFC666C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_11_PADDING_VALUE                    0xFC6670
+
+#define mmTPC7_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG                    0xFC6674
+
+#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_0_SIZE                       0xFC6678
+
+#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE                     0xFC667C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_1_SIZE                       0xFC6680
+
+#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE                     0xFC6684
+
+#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_2_SIZE                       0xFC6688
+
+#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE                     0xFC668C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_3_SIZE                       0xFC6690
+
+#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE                     0xFC6694
+
+#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_4_SIZE                       0xFC6698
+
+#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE                     0xFC669C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW                    0xFC66A0
+
+#define mmTPC7_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH                   0xFC66A4
+
+#define mmTPC7_CFG_KERNEL_TENSOR_12_PADDING_VALUE                    0xFC66A8
+
+#define mmTPC7_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG                    0xFC66AC
+
+#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_0_SIZE                       0xFC66B0
+
+#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE                     0xFC66B4
+
+#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_1_SIZE                       0xFC66B8
+
+#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE                     0xFC66BC
+
+#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_2_SIZE                       0xFC66C0
+
+#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE                     0xFC66C4
+
+#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_3_SIZE                       0xFC66C8
+
+#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE                     0xFC66CC
+
+#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_4_SIZE                       0xFC66D0
+
+#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE                     0xFC66D4
+
+#define mmTPC7_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW                    0xFC66D8
+
+#define mmTPC7_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH                   0xFC66DC
+
+#define mmTPC7_CFG_KERNEL_TENSOR_13_PADDING_VALUE                    0xFC66E0
+
+#define mmTPC7_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG                    0xFC66E4
+
+#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_0_SIZE                       0xFC66E8
+
+#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE                     0xFC66EC
+
+#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_1_SIZE                       0xFC66F0
+
+#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE                     0xFC66F4
+
+#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_2_SIZE                       0xFC66F8
+
+#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE                     0xFC66FC
+
+#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_3_SIZE                       0xFC6700
+
+#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE                     0xFC6704
+
+#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_4_SIZE                       0xFC6708
+
+#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE                     0xFC670C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW                    0xFC6710
+
+#define mmTPC7_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH                   0xFC6714
+
+#define mmTPC7_CFG_KERNEL_TENSOR_14_PADDING_VALUE                    0xFC6718
+
+#define mmTPC7_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG                    0xFC671C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_0_SIZE                       0xFC6720
+
+#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE                     0xFC6724
+
+#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_1_SIZE                       0xFC6728
+
+#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE                     0xFC672C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_2_SIZE                       0xFC6730
+
+#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE                     0xFC6734
+
+#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_3_SIZE                       0xFC6738
+
+#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE                     0xFC673C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_4_SIZE                       0xFC6740
+
+#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE                     0xFC6744
+
+#define mmTPC7_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW                    0xFC6748
+
+#define mmTPC7_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH                   0xFC674C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_15_PADDING_VALUE                    0xFC6750
+
+#define mmTPC7_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG                    0xFC6754
+
+#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_0_SIZE                       0xFC6758
+
+#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE                     0xFC675C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_1_SIZE                       0xFC6760
+
+#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE                     0xFC6764
+
+#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_2_SIZE                       0xFC6768
+
+#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE                     0xFC676C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_3_SIZE                       0xFC6770
+
+#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE                     0xFC6774
+
+#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_4_SIZE                       0xFC6778
+
+#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE                     0xFC677C
+
+#define mmTPC7_CFG_KERNEL_SYNC_OBJECT_MESSAGE                        0xFC6780
+
+#define mmTPC7_CFG_KERNEL_SYNC_OBJECT_ADDR                           0xFC6784
+
+#define mmTPC7_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW                    0xFC6788
+
+#define mmTPC7_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH                   0xFC678C
+
+#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_0                             0xFC6790
+
+#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_0                             0xFC6794
+
+#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_1                             0xFC6798
+
+#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_1                             0xFC679C
+
+#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_2                             0xFC67A0
+
+#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_2                             0xFC67A4
+
+#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_3                             0xFC67A8
+
+#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_3                             0xFC67AC
+
+#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_4                             0xFC67B0
+
+#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_4                             0xFC67B4
+
+#define mmTPC7_CFG_KERNEL_KERNEL_CONFIG                              0xFC67B8
+
+#define mmTPC7_CFG_KERNEL_KERNEL_ID                                  0xFC67BC
+
+#define mmTPC7_CFG_KERNEL_SRF_0                                      0xFC67C0
+
+#define mmTPC7_CFG_KERNEL_SRF_1                                      0xFC67C4
+
+#define mmTPC7_CFG_KERNEL_SRF_2                                      0xFC67C8
+
+#define mmTPC7_CFG_KERNEL_SRF_3                                      0xFC67CC
+
+#define mmTPC7_CFG_KERNEL_SRF_4                                      0xFC67D0
+
+#define mmTPC7_CFG_KERNEL_SRF_5                                      0xFC67D4
+
+#define mmTPC7_CFG_KERNEL_SRF_6                                      0xFC67D8
+
+#define mmTPC7_CFG_KERNEL_SRF_7                                      0xFC67DC
+
+#define mmTPC7_CFG_KERNEL_SRF_8                                      0xFC67E0
+
+#define mmTPC7_CFG_KERNEL_SRF_9                                      0xFC67E4
+
+#define mmTPC7_CFG_KERNEL_SRF_10                                     0xFC67E8
+
+#define mmTPC7_CFG_KERNEL_SRF_11                                     0xFC67EC
+
+#define mmTPC7_CFG_KERNEL_SRF_12                                     0xFC67F0
+
+#define mmTPC7_CFG_KERNEL_SRF_13                                     0xFC67F4
+
+#define mmTPC7_CFG_KERNEL_SRF_14                                     0xFC67F8
+
+#define mmTPC7_CFG_KERNEL_SRF_15                                     0xFC67FC
+
+#define mmTPC7_CFG_KERNEL_SRF_16                                     0xFC6800
+
+#define mmTPC7_CFG_KERNEL_SRF_17                                     0xFC6804
+
+#define mmTPC7_CFG_KERNEL_SRF_18                                     0xFC6808
+
+#define mmTPC7_CFG_KERNEL_SRF_19                                     0xFC680C
+
+#define mmTPC7_CFG_KERNEL_SRF_20                                     0xFC6810
+
+#define mmTPC7_CFG_KERNEL_SRF_21                                     0xFC6814
+
+#define mmTPC7_CFG_KERNEL_SRF_22                                     0xFC6818
+
+#define mmTPC7_CFG_KERNEL_SRF_23                                     0xFC681C
+
+#define mmTPC7_CFG_KERNEL_SRF_24                                     0xFC6820
+
+#define mmTPC7_CFG_KERNEL_SRF_25                                     0xFC6824
+
+#define mmTPC7_CFG_KERNEL_SRF_26                                     0xFC6828
+
+#define mmTPC7_CFG_KERNEL_SRF_27                                     0xFC682C
+
+#define mmTPC7_CFG_KERNEL_SRF_28                                     0xFC6830
+
+#define mmTPC7_CFG_KERNEL_SRF_29                                     0xFC6834
+
+#define mmTPC7_CFG_KERNEL_SRF_30                                     0xFC6838
+
+#define mmTPC7_CFG_KERNEL_SRF_31                                     0xFC683C
+
+#define mmTPC7_CFG_ROUND_CSR                                         0xFC68FC
+
+#define mmTPC7_CFG_PROT                                              0xFC6900
+
+#define mmTPC7_CFG_SEMAPHORE                                         0xFC6908
+
+#define mmTPC7_CFG_VFLAGS                                            0xFC690C
+
+#define mmTPC7_CFG_SFLAGS                                            0xFC6910
+
+#define mmTPC7_CFG_LFSR_POLYNOM                                      0xFC6918
+
+#define mmTPC7_CFG_STATUS                                            0xFC691C
+
+#define mmTPC7_CFG_CFG_BASE_ADDRESS_HIGH                             0xFC6920
+
+#define mmTPC7_CFG_CFG_SUBTRACT_VALUE                                0xFC6924
+
+#define mmTPC7_CFG_SM_BASE_ADDRESS_HIGH                              0xFC692C
+
+#define mmTPC7_CFG_TPC_CMD                                           0xFC6930
+
+#define mmTPC7_CFG_TPC_EXECUTE                                       0xFC6938
+
+#define mmTPC7_CFG_TPC_STALL                                         0xFC693C
+
+#define mmTPC7_CFG_ICACHE_BASE_ADDERESS_LOW                          0xFC6940
+
+#define mmTPC7_CFG_ICACHE_BASE_ADDERESS_HIGH                         0xFC6944
+
+#define mmTPC7_CFG_RD_RATE_LIMIT                                     0xFC6948
+
+#define mmTPC7_CFG_WR_RATE_LIMIT                                     0xFC6950
+
+#define mmTPC7_CFG_MSS_CONFIG                                        0xFC6954
+
+#define mmTPC7_CFG_TPC_INTR_CAUSE                                    0xFC6958
+
+#define mmTPC7_CFG_TPC_INTR_MASK                                     0xFC695C
+
+#define mmTPC7_CFG_WQ_CREDITS                                        0xFC6960
+
+#define mmTPC7_CFG_ARUSER_LO                                         0xFC6964
+
+#define mmTPC7_CFG_ARUSER_HI                                         0xFC6968
+
+#define mmTPC7_CFG_AWUSER_LO                                         0xFC696C
+
+#define mmTPC7_CFG_AWUSER_HI                                         0xFC6970
+
+#define mmTPC7_CFG_OPCODE_EXEC                                       0xFC6974
+
+#define mmTPC7_CFG_LUT_FUNC32_BASE_ADDR_LO                           0xFC6978
+
+#define mmTPC7_CFG_LUT_FUNC32_BASE_ADDR_HI                           0xFC697C
+
+#define mmTPC7_CFG_LUT_FUNC64_BASE_ADDR_LO                           0xFC6980
+
+#define mmTPC7_CFG_LUT_FUNC64_BASE_ADDR_HI                           0xFC6984
+
+#define mmTPC7_CFG_LUT_FUNC128_BASE_ADDR_LO                          0xFC6988
+
+#define mmTPC7_CFG_LUT_FUNC128_BASE_ADDR_HI                          0xFC698C
+
+#define mmTPC7_CFG_LUT_FUNC256_BASE_ADDR_LO                          0xFC6990
+
+#define mmTPC7_CFG_LUT_FUNC256_BASE_ADDR_HI                          0xFC6994
+
+#define mmTPC7_CFG_TSB_CFG_MAX_SIZE                                  0xFC6998
+
+#define mmTPC7_CFG_TSB_CFG                                           0xFC699C
+
+#define mmTPC7_CFG_DBGMEM_ADD                                        0xFC69A0
+
+#define mmTPC7_CFG_DBGMEM_DATA_WR                                    0xFC69A4
+
+#define mmTPC7_CFG_DBGMEM_DATA_RD                                    0xFC69A8
+
+#define mmTPC7_CFG_DBGMEM_CTRL                                       0xFC69AC
+
+#define mmTPC7_CFG_DBGMEM_RC                                         0xFC69B0
+
+#define mmTPC7_CFG_TSB_INFLIGHT_CNTR                                 0xFC69B4
+
+#define mmTPC7_CFG_WQ_INFLIGHT_CNTR                                  0xFC69B8
+
+#define mmTPC7_CFG_WQ_LBW_TOTAL_CNTR                                 0xFC69BC
+
+#define mmTPC7_CFG_WQ_HBW_TOTAL_CNTR                                 0xFC69C0
+
+#define mmTPC7_CFG_IRQ_OCCOUPY_CNTR                                  0xFC69C4
+
+#define mmTPC7_CFG_FUNC_MBIST_CNTRL                                  0xFC69D0
+
+#define mmTPC7_CFG_FUNC_MBIST_PAT                                    0xFC69D4
+
+#define mmTPC7_CFG_FUNC_MBIST_MEM_0                                  0xFC69D8
+
+#define mmTPC7_CFG_FUNC_MBIST_MEM_1                                  0xFC69DC
+
+#define mmTPC7_CFG_FUNC_MBIST_MEM_2                                  0xFC69E0
+
+#define mmTPC7_CFG_FUNC_MBIST_MEM_3                                  0xFC69E4
+
+#define mmTPC7_CFG_FUNC_MBIST_MEM_4                                  0xFC69E8
+
+#define mmTPC7_CFG_FUNC_MBIST_MEM_5                                  0xFC69EC
+
+#define mmTPC7_CFG_FUNC_MBIST_MEM_6                                  0xFC69F0
+
+#define mmTPC7_CFG_FUNC_MBIST_MEM_7                                  0xFC69F4
+
+#define mmTPC7_CFG_FUNC_MBIST_MEM_8                                  0xFC69F8
+
+#define mmTPC7_CFG_FUNC_MBIST_MEM_9                                  0xFC69FC
+
+#define mmTPC7_CFG_QM_TENSOR_0_BASE_ADDR_LOW                         0xFC6A00
+
+#define mmTPC7_CFG_QM_TENSOR_0_BASE_ADDR_HIGH                        0xFC6A04
+
+#define mmTPC7_CFG_QM_TENSOR_0_PADDING_VALUE                         0xFC6A08
+
+#define mmTPC7_CFG_QM_TENSOR_0_TENSOR_CONFIG                         0xFC6A0C
+
+#define mmTPC7_CFG_QM_TENSOR_0_DIM_0_SIZE                            0xFC6A10
+
+#define mmTPC7_CFG_QM_TENSOR_0_DIM_0_STRIDE                          0xFC6A14
+
+#define mmTPC7_CFG_QM_TENSOR_0_DIM_1_SIZE                            0xFC6A18
+
+#define mmTPC7_CFG_QM_TENSOR_0_DIM_1_STRIDE                          0xFC6A1C
+
+#define mmTPC7_CFG_QM_TENSOR_0_DIM_2_SIZE                            0xFC6A20
+
+#define mmTPC7_CFG_QM_TENSOR_0_DIM_2_STRIDE                          0xFC6A24
+
+#define mmTPC7_CFG_QM_TENSOR_0_DIM_3_SIZE                            0xFC6A28
+
+#define mmTPC7_CFG_QM_TENSOR_0_DIM_3_STRIDE                          0xFC6A2C
+
+#define mmTPC7_CFG_QM_TENSOR_0_DIM_4_SIZE                            0xFC6A30
+
+#define mmTPC7_CFG_QM_TENSOR_0_DIM_4_STRIDE                          0xFC6A34
+
+#define mmTPC7_CFG_QM_TENSOR_1_BASE_ADDR_LOW                         0xFC6A38
+
+#define mmTPC7_CFG_QM_TENSOR_1_BASE_ADDR_HIGH                        0xFC6A3C
+
+#define mmTPC7_CFG_QM_TENSOR_1_PADDING_VALUE                         0xFC6A40
+
+#define mmTPC7_CFG_QM_TENSOR_1_TENSOR_CONFIG                         0xFC6A44
+
+#define mmTPC7_CFG_QM_TENSOR_1_DIM_0_SIZE                            0xFC6A48
+
+#define mmTPC7_CFG_QM_TENSOR_1_DIM_0_STRIDE                          0xFC6A4C
+
+#define mmTPC7_CFG_QM_TENSOR_1_DIM_1_SIZE                            0xFC6A50
+
+#define mmTPC7_CFG_QM_TENSOR_1_DIM_1_STRIDE                          0xFC6A54
+
+#define mmTPC7_CFG_QM_TENSOR_1_DIM_2_SIZE                            0xFC6A58
+
+#define mmTPC7_CFG_QM_TENSOR_1_DIM_2_STRIDE                          0xFC6A5C
+
+#define mmTPC7_CFG_QM_TENSOR_1_DIM_3_SIZE                            0xFC6A60
+
+#define mmTPC7_CFG_QM_TENSOR_1_DIM_3_STRIDE                          0xFC6A64
+
+#define mmTPC7_CFG_QM_TENSOR_1_DIM_4_SIZE                            0xFC6A68
+
+#define mmTPC7_CFG_QM_TENSOR_1_DIM_4_STRIDE                          0xFC6A6C
+
+#define mmTPC7_CFG_QM_TENSOR_2_BASE_ADDR_LOW                         0xFC6A70
+
+#define mmTPC7_CFG_QM_TENSOR_2_BASE_ADDR_HIGH                        0xFC6A74
+
+#define mmTPC7_CFG_QM_TENSOR_2_PADDING_VALUE                         0xFC6A78
+
+#define mmTPC7_CFG_QM_TENSOR_2_TENSOR_CONFIG                         0xFC6A7C
+
+#define mmTPC7_CFG_QM_TENSOR_2_DIM_0_SIZE                            0xFC6A80
+
+#define mmTPC7_CFG_QM_TENSOR_2_DIM_0_STRIDE                          0xFC6A84
+
+#define mmTPC7_CFG_QM_TENSOR_2_DIM_1_SIZE                            0xFC6A88
+
+#define mmTPC7_CFG_QM_TENSOR_2_DIM_1_STRIDE                          0xFC6A8C
+
+#define mmTPC7_CFG_QM_TENSOR_2_DIM_2_SIZE                            0xFC6A90
+
+#define mmTPC7_CFG_QM_TENSOR_2_DIM_2_STRIDE                          0xFC6A94
+
+#define mmTPC7_CFG_QM_TENSOR_2_DIM_3_SIZE                            0xFC6A98
+
+#define mmTPC7_CFG_QM_TENSOR_2_DIM_3_STRIDE                          0xFC6A9C
+
+#define mmTPC7_CFG_QM_TENSOR_2_DIM_4_SIZE                            0xFC6AA0
+
+#define mmTPC7_CFG_QM_TENSOR_2_DIM_4_STRIDE                          0xFC6AA4
+
+#define mmTPC7_CFG_QM_TENSOR_3_BASE_ADDR_LOW                         0xFC6AA8
+
+#define mmTPC7_CFG_QM_TENSOR_3_BASE_ADDR_HIGH                        0xFC6AAC
+
+#define mmTPC7_CFG_QM_TENSOR_3_PADDING_VALUE                         0xFC6AB0
+
+#define mmTPC7_CFG_QM_TENSOR_3_TENSOR_CONFIG                         0xFC6AB4
+
+#define mmTPC7_CFG_QM_TENSOR_3_DIM_0_SIZE                            0xFC6AB8
+
+#define mmTPC7_CFG_QM_TENSOR_3_DIM_0_STRIDE                          0xFC6ABC
+
+#define mmTPC7_CFG_QM_TENSOR_3_DIM_1_SIZE                            0xFC6AC0
+
+#define mmTPC7_CFG_QM_TENSOR_3_DIM_1_STRIDE                          0xFC6AC4
+
+#define mmTPC7_CFG_QM_TENSOR_3_DIM_2_SIZE                            0xFC6AC8
+
+#define mmTPC7_CFG_QM_TENSOR_3_DIM_2_STRIDE                          0xFC6ACC
+
+#define mmTPC7_CFG_QM_TENSOR_3_DIM_3_SIZE                            0xFC6AD0
+
+#define mmTPC7_CFG_QM_TENSOR_3_DIM_3_STRIDE                          0xFC6AD4
+
+#define mmTPC7_CFG_QM_TENSOR_3_DIM_4_SIZE                            0xFC6AD8
+
+#define mmTPC7_CFG_QM_TENSOR_3_DIM_4_STRIDE                          0xFC6ADC
+
+#define mmTPC7_CFG_QM_TENSOR_4_BASE_ADDR_LOW                         0xFC6AE0
+
+#define mmTPC7_CFG_QM_TENSOR_4_BASE_ADDR_HIGH                        0xFC6AE4
+
+#define mmTPC7_CFG_QM_TENSOR_4_PADDING_VALUE                         0xFC6AE8
+
+#define mmTPC7_CFG_QM_TENSOR_4_TENSOR_CONFIG                         0xFC6AEC
+
+#define mmTPC7_CFG_QM_TENSOR_4_DIM_0_SIZE                            0xFC6AF0
+
+#define mmTPC7_CFG_QM_TENSOR_4_DIM_0_STRIDE                          0xFC6AF4
+
+#define mmTPC7_CFG_QM_TENSOR_4_DIM_1_SIZE                            0xFC6AF8
+
+#define mmTPC7_CFG_QM_TENSOR_4_DIM_1_STRIDE                          0xFC6AFC
+
+#define mmTPC7_CFG_QM_TENSOR_4_DIM_2_SIZE                            0xFC6B00
+
+#define mmTPC7_CFG_QM_TENSOR_4_DIM_2_STRIDE                          0xFC6B04
+
+#define mmTPC7_CFG_QM_TENSOR_4_DIM_3_SIZE                            0xFC6B08
+
+#define mmTPC7_CFG_QM_TENSOR_4_DIM_3_STRIDE                          0xFC6B0C
+
+#define mmTPC7_CFG_QM_TENSOR_4_DIM_4_SIZE                            0xFC6B10
+
+#define mmTPC7_CFG_QM_TENSOR_4_DIM_4_STRIDE                          0xFC6B14
+
+#define mmTPC7_CFG_QM_TENSOR_5_BASE_ADDR_LOW                         0xFC6B18
+
+#define mmTPC7_CFG_QM_TENSOR_5_BASE_ADDR_HIGH                        0xFC6B1C
+
+#define mmTPC7_CFG_QM_TENSOR_5_PADDING_VALUE                         0xFC6B20
+
+#define mmTPC7_CFG_QM_TENSOR_5_TENSOR_CONFIG                         0xFC6B24
+
+#define mmTPC7_CFG_QM_TENSOR_5_DIM_0_SIZE                            0xFC6B28
+
+#define mmTPC7_CFG_QM_TENSOR_5_DIM_0_STRIDE                          0xFC6B2C
+
+#define mmTPC7_CFG_QM_TENSOR_5_DIM_1_SIZE                            0xFC6B30
+
+#define mmTPC7_CFG_QM_TENSOR_5_DIM_1_STRIDE                          0xFC6B34
+
+#define mmTPC7_CFG_QM_TENSOR_5_DIM_2_SIZE                            0xFC6B38
+
+#define mmTPC7_CFG_QM_TENSOR_5_DIM_2_STRIDE                          0xFC6B3C
+
+#define mmTPC7_CFG_QM_TENSOR_5_DIM_3_SIZE                            0xFC6B40
+
+#define mmTPC7_CFG_QM_TENSOR_5_DIM_3_STRIDE                          0xFC6B44
+
+#define mmTPC7_CFG_QM_TENSOR_5_DIM_4_SIZE                            0xFC6B48
+
+#define mmTPC7_CFG_QM_TENSOR_5_DIM_4_STRIDE                          0xFC6B4C
+
+#define mmTPC7_CFG_QM_TENSOR_6_BASE_ADDR_LOW                         0xFC6B50
+
+#define mmTPC7_CFG_QM_TENSOR_6_BASE_ADDR_HIGH                        0xFC6B54
+
+#define mmTPC7_CFG_QM_TENSOR_6_PADDING_VALUE                         0xFC6B58
+
+#define mmTPC7_CFG_QM_TENSOR_6_TENSOR_CONFIG                         0xFC6B5C
+
+#define mmTPC7_CFG_QM_TENSOR_6_DIM_0_SIZE                            0xFC6B60
+
+#define mmTPC7_CFG_QM_TENSOR_6_DIM_0_STRIDE                          0xFC6B64
+
+#define mmTPC7_CFG_QM_TENSOR_6_DIM_1_SIZE                            0xFC6B68
+
+#define mmTPC7_CFG_QM_TENSOR_6_DIM_1_STRIDE                          0xFC6B6C
+
+#define mmTPC7_CFG_QM_TENSOR_6_DIM_2_SIZE                            0xFC6B70
+
+#define mmTPC7_CFG_QM_TENSOR_6_DIM_2_STRIDE                          0xFC6B74
+
+#define mmTPC7_CFG_QM_TENSOR_6_DIM_3_SIZE                            0xFC6B78
+
+#define mmTPC7_CFG_QM_TENSOR_6_DIM_3_STRIDE                          0xFC6B7C
+
+#define mmTPC7_CFG_QM_TENSOR_6_DIM_4_SIZE                            0xFC6B80
+
+#define mmTPC7_CFG_QM_TENSOR_6_DIM_4_STRIDE                          0xFC6B84
+
+#define mmTPC7_CFG_QM_TENSOR_7_BASE_ADDR_LOW                         0xFC6B88
+
+#define mmTPC7_CFG_QM_TENSOR_7_BASE_ADDR_HIGH                        0xFC6B8C
+
+#define mmTPC7_CFG_QM_TENSOR_7_PADDING_VALUE                         0xFC6B90
+
+#define mmTPC7_CFG_QM_TENSOR_7_TENSOR_CONFIG                         0xFC6B94
+
+#define mmTPC7_CFG_QM_TENSOR_7_DIM_0_SIZE                            0xFC6B98
+
+#define mmTPC7_CFG_QM_TENSOR_7_DIM_0_STRIDE                          0xFC6B9C
+
+#define mmTPC7_CFG_QM_TENSOR_7_DIM_1_SIZE                            0xFC6BA0
+
+#define mmTPC7_CFG_QM_TENSOR_7_DIM_1_STRIDE                          0xFC6BA4
+
+#define mmTPC7_CFG_QM_TENSOR_7_DIM_2_SIZE                            0xFC6BA8
+
+#define mmTPC7_CFG_QM_TENSOR_7_DIM_2_STRIDE                          0xFC6BAC
+
+#define mmTPC7_CFG_QM_TENSOR_7_DIM_3_SIZE                            0xFC6BB0
+
+#define mmTPC7_CFG_QM_TENSOR_7_DIM_3_STRIDE                          0xFC6BB4
+
+#define mmTPC7_CFG_QM_TENSOR_7_DIM_4_SIZE                            0xFC6BB8
+
+#define mmTPC7_CFG_QM_TENSOR_7_DIM_4_STRIDE                          0xFC6BBC
+
+#define mmTPC7_CFG_QM_TENSOR_8_BASE_ADDR_LOW                         0xFC6BC0
+
+#define mmTPC7_CFG_QM_TENSOR_8_BASE_ADDR_HIGH                        0xFC6BC4
+
+#define mmTPC7_CFG_QM_TENSOR_8_PADDING_VALUE                         0xFC6BC8
+
+#define mmTPC7_CFG_QM_TENSOR_8_TENSOR_CONFIG                         0xFC6BCC
+
+#define mmTPC7_CFG_QM_TENSOR_8_DIM_0_SIZE                            0xFC6BD0
+
+#define mmTPC7_CFG_QM_TENSOR_8_DIM_0_STRIDE                          0xFC6BD4
+
+#define mmTPC7_CFG_QM_TENSOR_8_DIM_1_SIZE                            0xFC6BD8
+
+#define mmTPC7_CFG_QM_TENSOR_8_DIM_1_STRIDE                          0xFC6BDC
+
+#define mmTPC7_CFG_QM_TENSOR_8_DIM_2_SIZE                            0xFC6BE0
+
+#define mmTPC7_CFG_QM_TENSOR_8_DIM_2_STRIDE                          0xFC6BE4
+
+#define mmTPC7_CFG_QM_TENSOR_8_DIM_3_SIZE                            0xFC6BE8
+
+#define mmTPC7_CFG_QM_TENSOR_8_DIM_3_STRIDE                          0xFC6BEC
+
+#define mmTPC7_CFG_QM_TENSOR_8_DIM_4_SIZE                            0xFC6BF0
+
+#define mmTPC7_CFG_QM_TENSOR_8_DIM_4_STRIDE                          0xFC6BF4
+
+#define mmTPC7_CFG_QM_TENSOR_9_BASE_ADDR_LOW                         0xFC6BF8
+
+#define mmTPC7_CFG_QM_TENSOR_9_BASE_ADDR_HIGH                        0xFC6BFC
+
+#define mmTPC7_CFG_QM_TENSOR_9_PADDING_VALUE                         0xFC6C00
+
+#define mmTPC7_CFG_QM_TENSOR_9_TENSOR_CONFIG                         0xFC6C04
+
+#define mmTPC7_CFG_QM_TENSOR_9_DIM_0_SIZE                            0xFC6C08
+
+#define mmTPC7_CFG_QM_TENSOR_9_DIM_0_STRIDE                          0xFC6C0C
+
+#define mmTPC7_CFG_QM_TENSOR_9_DIM_1_SIZE                            0xFC6C10
+
+#define mmTPC7_CFG_QM_TENSOR_9_DIM_1_STRIDE                          0xFC6C14
+
+#define mmTPC7_CFG_QM_TENSOR_9_DIM_2_SIZE                            0xFC6C18
+
+#define mmTPC7_CFG_QM_TENSOR_9_DIM_2_STRIDE                          0xFC6C1C
+
+#define mmTPC7_CFG_QM_TENSOR_9_DIM_3_SIZE                            0xFC6C20
+
+#define mmTPC7_CFG_QM_TENSOR_9_DIM_3_STRIDE                          0xFC6C24
+
+#define mmTPC7_CFG_QM_TENSOR_9_DIM_4_SIZE                            0xFC6C28
+
+#define mmTPC7_CFG_QM_TENSOR_9_DIM_4_STRIDE                          0xFC6C2C
+
+#define mmTPC7_CFG_QM_TENSOR_10_BASE_ADDR_LOW                        0xFC6C30
+
+#define mmTPC7_CFG_QM_TENSOR_10_BASE_ADDR_HIGH                       0xFC6C34
+
+#define mmTPC7_CFG_QM_TENSOR_10_PADDING_VALUE                        0xFC6C38
+
+#define mmTPC7_CFG_QM_TENSOR_10_TENSOR_CONFIG                        0xFC6C3C
+
+#define mmTPC7_CFG_QM_TENSOR_10_DIM_0_SIZE                           0xFC6C40
+
+#define mmTPC7_CFG_QM_TENSOR_10_DIM_0_STRIDE                         0xFC6C44
+
+#define mmTPC7_CFG_QM_TENSOR_10_DIM_1_SIZE                           0xFC6C48
+
+#define mmTPC7_CFG_QM_TENSOR_10_DIM_1_STRIDE                         0xFC6C4C
+
+#define mmTPC7_CFG_QM_TENSOR_10_DIM_2_SIZE                           0xFC6C50
+
+#define mmTPC7_CFG_QM_TENSOR_10_DIM_2_STRIDE                         0xFC6C54
+
+#define mmTPC7_CFG_QM_TENSOR_10_DIM_3_SIZE                           0xFC6C58
+
+#define mmTPC7_CFG_QM_TENSOR_10_DIM_3_STRIDE                         0xFC6C5C
+
+#define mmTPC7_CFG_QM_TENSOR_10_DIM_4_SIZE                           0xFC6C60
+
+#define mmTPC7_CFG_QM_TENSOR_10_DIM_4_STRIDE                         0xFC6C64
+
+#define mmTPC7_CFG_QM_TENSOR_11_BASE_ADDR_LOW                        0xFC6C68
+
+#define mmTPC7_CFG_QM_TENSOR_11_BASE_ADDR_HIGH                       0xFC6C6C
+
+#define mmTPC7_CFG_QM_TENSOR_11_PADDING_VALUE                        0xFC6C70
+
+#define mmTPC7_CFG_QM_TENSOR_11_TENSOR_CONFIG                        0xFC6C74
+
+#define mmTPC7_CFG_QM_TENSOR_11_DIM_0_SIZE                           0xFC6C78
+
+#define mmTPC7_CFG_QM_TENSOR_11_DIM_0_STRIDE                         0xFC6C7C
+
+#define mmTPC7_CFG_QM_TENSOR_11_DIM_1_SIZE                           0xFC6C80
+
+#define mmTPC7_CFG_QM_TENSOR_11_DIM_1_STRIDE                         0xFC6C84
+
+#define mmTPC7_CFG_QM_TENSOR_11_DIM_2_SIZE                           0xFC6C88
+
+#define mmTPC7_CFG_QM_TENSOR_11_DIM_2_STRIDE                         0xFC6C8C
+
+#define mmTPC7_CFG_QM_TENSOR_11_DIM_3_SIZE                           0xFC6C90
+
+#define mmTPC7_CFG_QM_TENSOR_11_DIM_3_STRIDE                         0xFC6C94
+
+#define mmTPC7_CFG_QM_TENSOR_11_DIM_4_SIZE                           0xFC6C98
+
+#define mmTPC7_CFG_QM_TENSOR_11_DIM_4_STRIDE                         0xFC6C9C
+
+#define mmTPC7_CFG_QM_TENSOR_12_BASE_ADDR_LOW                        0xFC6CA0
+
+#define mmTPC7_CFG_QM_TENSOR_12_BASE_ADDR_HIGH                       0xFC6CA4
+
+#define mmTPC7_CFG_QM_TENSOR_12_PADDING_VALUE                        0xFC6CA8
+
+#define mmTPC7_CFG_QM_TENSOR_12_TENSOR_CONFIG                        0xFC6CAC
+
+#define mmTPC7_CFG_QM_TENSOR_12_DIM_0_SIZE                           0xFC6CB0
+
+#define mmTPC7_CFG_QM_TENSOR_12_DIM_0_STRIDE                         0xFC6CB4
+
+#define mmTPC7_CFG_QM_TENSOR_12_DIM_1_SIZE                           0xFC6CB8
+
+#define mmTPC7_CFG_QM_TENSOR_12_DIM_1_STRIDE                         0xFC6CBC
+
+#define mmTPC7_CFG_QM_TENSOR_12_DIM_2_SIZE                           0xFC6CC0
+
+#define mmTPC7_CFG_QM_TENSOR_12_DIM_2_STRIDE                         0xFC6CC4
+
+#define mmTPC7_CFG_QM_TENSOR_12_DIM_3_SIZE                           0xFC6CC8
+
+#define mmTPC7_CFG_QM_TENSOR_12_DIM_3_STRIDE                         0xFC6CCC
+
+#define mmTPC7_CFG_QM_TENSOR_12_DIM_4_SIZE                           0xFC6CD0
+
+#define mmTPC7_CFG_QM_TENSOR_12_DIM_4_STRIDE                         0xFC6CD4
+
+#define mmTPC7_CFG_QM_TENSOR_13_BASE_ADDR_LOW                        0xFC6CD8
+
+#define mmTPC7_CFG_QM_TENSOR_13_BASE_ADDR_HIGH                       0xFC6CDC
+
+#define mmTPC7_CFG_QM_TENSOR_13_PADDING_VALUE                        0xFC6CE0
+
+#define mmTPC7_CFG_QM_TENSOR_13_TENSOR_CONFIG                        0xFC6CE4
+
+#define mmTPC7_CFG_QM_TENSOR_13_DIM_0_SIZE                           0xFC6CE8
+
+#define mmTPC7_CFG_QM_TENSOR_13_DIM_0_STRIDE                         0xFC6CEC
+
+#define mmTPC7_CFG_QM_TENSOR_13_DIM_1_SIZE                           0xFC6CF0
+
+#define mmTPC7_CFG_QM_TENSOR_13_DIM_1_STRIDE                         0xFC6CF4
+
+#define mmTPC7_CFG_QM_TENSOR_13_DIM_2_SIZE                           0xFC6CF8
+
+#define mmTPC7_CFG_QM_TENSOR_13_DIM_2_STRIDE                         0xFC6CFC
+
+#define mmTPC7_CFG_QM_TENSOR_13_DIM_3_SIZE                           0xFC6D00
+
+#define mmTPC7_CFG_QM_TENSOR_13_DIM_3_STRIDE                         0xFC6D04
+
+#define mmTPC7_CFG_QM_TENSOR_13_DIM_4_SIZE                           0xFC6D08
+
+#define mmTPC7_CFG_QM_TENSOR_13_DIM_4_STRIDE                         0xFC6D0C
+
+#define mmTPC7_CFG_QM_TENSOR_14_BASE_ADDR_LOW                        0xFC6D10
+
+#define mmTPC7_CFG_QM_TENSOR_14_BASE_ADDR_HIGH                       0xFC6D14
+
+#define mmTPC7_CFG_QM_TENSOR_14_PADDING_VALUE                        0xFC6D18
+
+#define mmTPC7_CFG_QM_TENSOR_14_TENSOR_CONFIG                        0xFC6D1C
+
+#define mmTPC7_CFG_QM_TENSOR_14_DIM_0_SIZE                           0xFC6D20
+
+#define mmTPC7_CFG_QM_TENSOR_14_DIM_0_STRIDE                         0xFC6D24
+
+#define mmTPC7_CFG_QM_TENSOR_14_DIM_1_SIZE                           0xFC6D28
+
+#define mmTPC7_CFG_QM_TENSOR_14_DIM_1_STRIDE                         0xFC6D2C
+
+#define mmTPC7_CFG_QM_TENSOR_14_DIM_2_SIZE                           0xFC6D30
+
+#define mmTPC7_CFG_QM_TENSOR_14_DIM_2_STRIDE                         0xFC6D34
+
+#define mmTPC7_CFG_QM_TENSOR_14_DIM_3_SIZE                           0xFC6D38
+
+#define mmTPC7_CFG_QM_TENSOR_14_DIM_3_STRIDE                         0xFC6D3C
+
+#define mmTPC7_CFG_QM_TENSOR_14_DIM_4_SIZE                           0xFC6D40
+
+#define mmTPC7_CFG_QM_TENSOR_14_DIM_4_STRIDE                         0xFC6D44
+
+#define mmTPC7_CFG_QM_TENSOR_15_BASE_ADDR_LOW                        0xFC6D48
+
+#define mmTPC7_CFG_QM_TENSOR_15_BASE_ADDR_HIGH                       0xFC6D4C
+
+#define mmTPC7_CFG_QM_TENSOR_15_PADDING_VALUE                        0xFC6D50
+
+#define mmTPC7_CFG_QM_TENSOR_15_TENSOR_CONFIG                        0xFC6D54
+
+#define mmTPC7_CFG_QM_TENSOR_15_DIM_0_SIZE                           0xFC6D58
+
+#define mmTPC7_CFG_QM_TENSOR_15_DIM_0_STRIDE                         0xFC6D5C
+
+#define mmTPC7_CFG_QM_TENSOR_15_DIM_1_SIZE                           0xFC6D60
+
+#define mmTPC7_CFG_QM_TENSOR_15_DIM_1_STRIDE                         0xFC6D64
+
+#define mmTPC7_CFG_QM_TENSOR_15_DIM_2_SIZE                           0xFC6D68
+
+#define mmTPC7_CFG_QM_TENSOR_15_DIM_2_STRIDE                         0xFC6D6C
+
+#define mmTPC7_CFG_QM_TENSOR_15_DIM_3_SIZE                           0xFC6D70
+
+#define mmTPC7_CFG_QM_TENSOR_15_DIM_3_STRIDE                         0xFC6D74
+
+#define mmTPC7_CFG_QM_TENSOR_15_DIM_4_SIZE                           0xFC6D78
+
+#define mmTPC7_CFG_QM_TENSOR_15_DIM_4_STRIDE                         0xFC6D7C
+
+#define mmTPC7_CFG_QM_SYNC_OBJECT_MESSAGE                            0xFC6D80
+
+#define mmTPC7_CFG_QM_SYNC_OBJECT_ADDR                               0xFC6D84
+
+#define mmTPC7_CFG_QM_KERNEL_BASE_ADDRESS_LOW                        0xFC6D88
+
+#define mmTPC7_CFG_QM_KERNEL_BASE_ADDRESS_HIGH                       0xFC6D8C
+
+#define mmTPC7_CFG_QM_TID_BASE_DIM_0                                 0xFC6D90
+
+#define mmTPC7_CFG_QM_TID_SIZE_DIM_0                                 0xFC6D94
+
+#define mmTPC7_CFG_QM_TID_BASE_DIM_1                                 0xFC6D98
+
+#define mmTPC7_CFG_QM_TID_SIZE_DIM_1                                 0xFC6D9C
+
+#define mmTPC7_CFG_QM_TID_BASE_DIM_2                                 0xFC6DA0
+
+#define mmTPC7_CFG_QM_TID_SIZE_DIM_2                                 0xFC6DA4
+
+#define mmTPC7_CFG_QM_TID_BASE_DIM_3                                 0xFC6DA8
+
+#define mmTPC7_CFG_QM_TID_SIZE_DIM_3                                 0xFC6DAC
+
+#define mmTPC7_CFG_QM_TID_BASE_DIM_4                                 0xFC6DB0
+
+#define mmTPC7_CFG_QM_TID_SIZE_DIM_4                                 0xFC6DB4
+
+#define mmTPC7_CFG_QM_KERNEL_CONFIG                                  0xFC6DB8
+
+#define mmTPC7_CFG_QM_KERNEL_ID                                      0xFC6DBC
+
+#define mmTPC7_CFG_QM_SRF_0                                          0xFC6DC0
+
+#define mmTPC7_CFG_QM_SRF_1                                          0xFC6DC4
+
+#define mmTPC7_CFG_QM_SRF_2                                          0xFC6DC8
+
+#define mmTPC7_CFG_QM_SRF_3                                          0xFC6DCC
+
+#define mmTPC7_CFG_QM_SRF_4                                          0xFC6DD0
+
+#define mmTPC7_CFG_QM_SRF_5                                          0xFC6DD4
+
+#define mmTPC7_CFG_QM_SRF_6                                          0xFC6DD8
+
+#define mmTPC7_CFG_QM_SRF_7                                          0xFC6DDC
+
+#define mmTPC7_CFG_QM_SRF_8                                          0xFC6DE0
+
+#define mmTPC7_CFG_QM_SRF_9                                          0xFC6DE4
+
+#define mmTPC7_CFG_QM_SRF_10                                         0xFC6DE8
+
+#define mmTPC7_CFG_QM_SRF_11                                         0xFC6DEC
+
+#define mmTPC7_CFG_QM_SRF_12                                         0xFC6DF0
+
+#define mmTPC7_CFG_QM_SRF_13                                         0xFC6DF4
+
+#define mmTPC7_CFG_QM_SRF_14                                         0xFC6DF8
+
+#define mmTPC7_CFG_QM_SRF_15                                         0xFC6DFC
+
+#define mmTPC7_CFG_QM_SRF_16                                         0xFC6E00
+
+#define mmTPC7_CFG_QM_SRF_17                                         0xFC6E04
+
+#define mmTPC7_CFG_QM_SRF_18                                         0xFC6E08
+
+#define mmTPC7_CFG_QM_SRF_19                                         0xFC6E0C
+
+#define mmTPC7_CFG_QM_SRF_20                                         0xFC6E10
+
+#define mmTPC7_CFG_QM_SRF_21                                         0xFC6E14
+
+#define mmTPC7_CFG_QM_SRF_22                                         0xFC6E18
+
+#define mmTPC7_CFG_QM_SRF_23                                         0xFC6E1C
+
+#define mmTPC7_CFG_QM_SRF_24                                         0xFC6E20
+
+#define mmTPC7_CFG_QM_SRF_25                                         0xFC6E24
+
+#define mmTPC7_CFG_QM_SRF_26                                         0xFC6E28
+
+#define mmTPC7_CFG_QM_SRF_27                                         0xFC6E2C
+
+#define mmTPC7_CFG_QM_SRF_28                                         0xFC6E30
+
+#define mmTPC7_CFG_QM_SRF_29                                         0xFC6E34
+
+#define mmTPC7_CFG_QM_SRF_30                                         0xFC6E38
+
+#define mmTPC7_CFG_QM_SRF_31                                         0xFC6E3C
+
+#endif /* ASIC_REG_TPC7_CFG_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc7_qm_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc7_qm_regs.h
new file mode 100644
index 000000000000..5c36c972c027
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc7_qm_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_TPC7_QM_REGS_H_
+#define ASIC_REG_TPC7_QM_REGS_H_
+
+/*
+ *****************************************
+ *   TPC7_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmTPC7_QM_GLBL_CFG0                                          0xFC8000
+
+#define mmTPC7_QM_GLBL_CFG1                                          0xFC8004
+
+#define mmTPC7_QM_GLBL_PROT                                          0xFC8008
+
+#define mmTPC7_QM_GLBL_ERR_CFG                                       0xFC800C
+
+#define mmTPC7_QM_GLBL_SECURE_PROPS_0                                0xFC8010
+
+#define mmTPC7_QM_GLBL_SECURE_PROPS_1                                0xFC8014
+
+#define mmTPC7_QM_GLBL_SECURE_PROPS_2                                0xFC8018
+
+#define mmTPC7_QM_GLBL_SECURE_PROPS_3                                0xFC801C
+
+#define mmTPC7_QM_GLBL_SECURE_PROPS_4                                0xFC8020
+
+#define mmTPC7_QM_GLBL_NON_SECURE_PROPS_0                            0xFC8024
+
+#define mmTPC7_QM_GLBL_NON_SECURE_PROPS_1                            0xFC8028
+
+#define mmTPC7_QM_GLBL_NON_SECURE_PROPS_2                            0xFC802C
+
+#define mmTPC7_QM_GLBL_NON_SECURE_PROPS_3                            0xFC8030
+
+#define mmTPC7_QM_GLBL_NON_SECURE_PROPS_4                            0xFC8034
+
+#define mmTPC7_QM_GLBL_STS0                                          0xFC8038
+
+#define mmTPC7_QM_GLBL_STS1_0                                        0xFC8040
+
+#define mmTPC7_QM_GLBL_STS1_1                                        0xFC8044
+
+#define mmTPC7_QM_GLBL_STS1_2                                        0xFC8048
+
+#define mmTPC7_QM_GLBL_STS1_3                                        0xFC804C
+
+#define mmTPC7_QM_GLBL_STS1_4                                        0xFC8050
+
+#define mmTPC7_QM_GLBL_MSG_EN_0                                      0xFC8054
+
+#define mmTPC7_QM_GLBL_MSG_EN_1                                      0xFC8058
+
+#define mmTPC7_QM_GLBL_MSG_EN_2                                      0xFC805C
+
+#define mmTPC7_QM_GLBL_MSG_EN_3                                      0xFC8060
+
+#define mmTPC7_QM_GLBL_MSG_EN_4                                      0xFC8068
+
+#define mmTPC7_QM_PQ_BASE_LO_0                                       0xFC8070
+
+#define mmTPC7_QM_PQ_BASE_LO_1                                       0xFC8074
+
+#define mmTPC7_QM_PQ_BASE_LO_2                                       0xFC8078
+
+#define mmTPC7_QM_PQ_BASE_LO_3                                       0xFC807C
+
+#define mmTPC7_QM_PQ_BASE_HI_0                                       0xFC8080
+
+#define mmTPC7_QM_PQ_BASE_HI_1                                       0xFC8084
+
+#define mmTPC7_QM_PQ_BASE_HI_2                                       0xFC8088
+
+#define mmTPC7_QM_PQ_BASE_HI_3                                       0xFC808C
+
+#define mmTPC7_QM_PQ_SIZE_0                                          0xFC8090
+
+#define mmTPC7_QM_PQ_SIZE_1                                          0xFC8094
+
+#define mmTPC7_QM_PQ_SIZE_2                                          0xFC8098
+
+#define mmTPC7_QM_PQ_SIZE_3                                          0xFC809C
+
+#define mmTPC7_QM_PQ_PI_0                                            0xFC80A0
+
+#define mmTPC7_QM_PQ_PI_1                                            0xFC80A4
+
+#define mmTPC7_QM_PQ_PI_2                                            0xFC80A8
+
+#define mmTPC7_QM_PQ_PI_3                                            0xFC80AC
+
+#define mmTPC7_QM_PQ_CI_0                                            0xFC80B0
+
+#define mmTPC7_QM_PQ_CI_1                                            0xFC80B4
+
+#define mmTPC7_QM_PQ_CI_2                                            0xFC80B8
+
+#define mmTPC7_QM_PQ_CI_3                                            0xFC80BC
+
+#define mmTPC7_QM_PQ_CFG0_0                                          0xFC80C0
+
+#define mmTPC7_QM_PQ_CFG0_1                                          0xFC80C4
+
+#define mmTPC7_QM_PQ_CFG0_2                                          0xFC80C8
+
+#define mmTPC7_QM_PQ_CFG0_3                                          0xFC80CC
+
+#define mmTPC7_QM_PQ_CFG1_0                                          0xFC80D0
+
+#define mmTPC7_QM_PQ_CFG1_1                                          0xFC80D4
+
+#define mmTPC7_QM_PQ_CFG1_2                                          0xFC80D8
+
+#define mmTPC7_QM_PQ_CFG1_3                                          0xFC80DC
+
+#define mmTPC7_QM_PQ_ARUSER_31_11_0                                  0xFC80E0
+
+#define mmTPC7_QM_PQ_ARUSER_31_11_1                                  0xFC80E4
+
+#define mmTPC7_QM_PQ_ARUSER_31_11_2                                  0xFC80E8
+
+#define mmTPC7_QM_PQ_ARUSER_31_11_3                                  0xFC80EC
+
+#define mmTPC7_QM_PQ_STS0_0                                          0xFC80F0
+
+#define mmTPC7_QM_PQ_STS0_1                                          0xFC80F4
+
+#define mmTPC7_QM_PQ_STS0_2                                          0xFC80F8
+
+#define mmTPC7_QM_PQ_STS0_3                                          0xFC80FC
+
+#define mmTPC7_QM_PQ_STS1_0                                          0xFC8100
+
+#define mmTPC7_QM_PQ_STS1_1                                          0xFC8104
+
+#define mmTPC7_QM_PQ_STS1_2                                          0xFC8108
+
+#define mmTPC7_QM_PQ_STS1_3                                          0xFC810C
+
+#define mmTPC7_QM_CQ_CFG0_0                                          0xFC8110
+
+#define mmTPC7_QM_CQ_CFG0_1                                          0xFC8114
+
+#define mmTPC7_QM_CQ_CFG0_2                                          0xFC8118
+
+#define mmTPC7_QM_CQ_CFG0_3                                          0xFC811C
+
+#define mmTPC7_QM_CQ_CFG0_4                                          0xFC8120
+
+#define mmTPC7_QM_CQ_CFG1_0                                          0xFC8124
+
+#define mmTPC7_QM_CQ_CFG1_1                                          0xFC8128
+
+#define mmTPC7_QM_CQ_CFG1_2                                          0xFC812C
+
+#define mmTPC7_QM_CQ_CFG1_3                                          0xFC8130
+
+#define mmTPC7_QM_CQ_CFG1_4                                          0xFC8134
+
+#define mmTPC7_QM_CQ_ARUSER_31_11_0                                  0xFC8138
+
+#define mmTPC7_QM_CQ_ARUSER_31_11_1                                  0xFC813C
+
+#define mmTPC7_QM_CQ_ARUSER_31_11_2                                  0xFC8140
+
+#define mmTPC7_QM_CQ_ARUSER_31_11_3                                  0xFC8144
+
+#define mmTPC7_QM_CQ_ARUSER_31_11_4                                  0xFC8148
+
+#define mmTPC7_QM_CQ_STS0_0                                          0xFC814C
+
+#define mmTPC7_QM_CQ_STS0_1                                          0xFC8150
+
+#define mmTPC7_QM_CQ_STS0_2                                          0xFC8154
+
+#define mmTPC7_QM_CQ_STS0_3                                          0xFC8158
+
+#define mmTPC7_QM_CQ_STS0_4                                          0xFC815C
+
+#define mmTPC7_QM_CQ_STS1_0                                          0xFC8160
+
+#define mmTPC7_QM_CQ_STS1_1                                          0xFC8164
+
+#define mmTPC7_QM_CQ_STS1_2                                          0xFC8168
+
+#define mmTPC7_QM_CQ_STS1_3                                          0xFC816C
+
+#define mmTPC7_QM_CQ_STS1_4                                          0xFC8170
+
+#define mmTPC7_QM_CQ_PTR_LO_0                                        0xFC8174
+
+#define mmTPC7_QM_CQ_PTR_HI_0                                        0xFC8178
+
+#define mmTPC7_QM_CQ_TSIZE_0                                         0xFC817C
+
+#define mmTPC7_QM_CQ_CTL_0                                           0xFC8180
+
+#define mmTPC7_QM_CQ_PTR_LO_1                                        0xFC8184
+
+#define mmTPC7_QM_CQ_PTR_HI_1                                        0xFC8188
+
+#define mmTPC7_QM_CQ_TSIZE_1                                         0xFC818C
+
+#define mmTPC7_QM_CQ_CTL_1                                           0xFC8190
+
+#define mmTPC7_QM_CQ_PTR_LO_2                                        0xFC8194
+
+#define mmTPC7_QM_CQ_PTR_HI_2                                        0xFC8198
+
+#define mmTPC7_QM_CQ_TSIZE_2                                         0xFC819C
+
+#define mmTPC7_QM_CQ_CTL_2                                           0xFC81A0
+
+#define mmTPC7_QM_CQ_PTR_LO_3                                        0xFC81A4
+
+#define mmTPC7_QM_CQ_PTR_HI_3                                        0xFC81A8
+
+#define mmTPC7_QM_CQ_TSIZE_3                                         0xFC81AC
+
+#define mmTPC7_QM_CQ_CTL_3                                           0xFC81B0
+
+#define mmTPC7_QM_CQ_PTR_LO_4                                        0xFC81B4
+
+#define mmTPC7_QM_CQ_PTR_HI_4                                        0xFC81B8
+
+#define mmTPC7_QM_CQ_TSIZE_4                                         0xFC81BC
+
+#define mmTPC7_QM_CQ_CTL_4                                           0xFC81C0
+
+#define mmTPC7_QM_CQ_PTR_LO_STS_0                                    0xFC81C4
+
+#define mmTPC7_QM_CQ_PTR_LO_STS_1                                    0xFC81C8
+
+#define mmTPC7_QM_CQ_PTR_LO_STS_2                                    0xFC81CC
+
+#define mmTPC7_QM_CQ_PTR_LO_STS_3                                    0xFC81D0
+
+#define mmTPC7_QM_CQ_PTR_LO_STS_4                                    0xFC81D4
+
+#define mmTPC7_QM_CQ_PTR_HI_STS_0                                    0xFC81D8
+
+#define mmTPC7_QM_CQ_PTR_HI_STS_1                                    0xFC81DC
+
+#define mmTPC7_QM_CQ_PTR_HI_STS_2                                    0xFC81E0
+
+#define mmTPC7_QM_CQ_PTR_HI_STS_3                                    0xFC81E4
+
+#define mmTPC7_QM_CQ_PTR_HI_STS_4                                    0xFC81E8
+
+#define mmTPC7_QM_CQ_TSIZE_STS_0                                     0xFC81EC
+
+#define mmTPC7_QM_CQ_TSIZE_STS_1                                     0xFC81F0
+
+#define mmTPC7_QM_CQ_TSIZE_STS_2                                     0xFC81F4
+
+#define mmTPC7_QM_CQ_TSIZE_STS_3                                     0xFC81F8
+
+#define mmTPC7_QM_CQ_TSIZE_STS_4                                     0xFC81FC
+
+#define mmTPC7_QM_CQ_CTL_STS_0                                       0xFC8200
+
+#define mmTPC7_QM_CQ_CTL_STS_1                                       0xFC8204
+
+#define mmTPC7_QM_CQ_CTL_STS_2                                       0xFC8208
+
+#define mmTPC7_QM_CQ_CTL_STS_3                                       0xFC820C
+
+#define mmTPC7_QM_CQ_CTL_STS_4                                       0xFC8210
+
+#define mmTPC7_QM_CQ_IFIFO_CNT_0                                     0xFC8214
+
+#define mmTPC7_QM_CQ_IFIFO_CNT_1                                     0xFC8218
+
+#define mmTPC7_QM_CQ_IFIFO_CNT_2                                     0xFC821C
+
+#define mmTPC7_QM_CQ_IFIFO_CNT_3                                     0xFC8220
+
+#define mmTPC7_QM_CQ_IFIFO_CNT_4                                     0xFC8224
+
+#define mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_0                             0xFC8228
+
+#define mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_1                             0xFC822C
+
+#define mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_2                             0xFC8230
+
+#define mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_3                             0xFC8234
+
+#define mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_4                             0xFC8238
+
+#define mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_0                             0xFC823C
+
+#define mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_1                             0xFC8240
+
+#define mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_2                             0xFC8244
+
+#define mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_3                             0xFC8248
+
+#define mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_4                             0xFC824C
+
+#define mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_0                             0xFC8250
+
+#define mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_1                             0xFC8254
+
+#define mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_2                             0xFC8258
+
+#define mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_3                             0xFC825C
+
+#define mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_4                             0xFC8260
+
+#define mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_0                             0xFC8264
+
+#define mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_1                             0xFC8268
+
+#define mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_2                             0xFC826C
+
+#define mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_3                             0xFC8270
+
+#define mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_4                             0xFC8274
+
+#define mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_0                             0xFC8278
+
+#define mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_1                             0xFC827C
+
+#define mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_2                             0xFC8280
+
+#define mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_3                             0xFC8284
+
+#define mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_4                             0xFC8288
+
+#define mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_0                             0xFC828C
+
+#define mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_1                             0xFC8290
+
+#define mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_2                             0xFC8294
+
+#define mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_3                             0xFC8298
+
+#define mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_4                             0xFC829C
+
+#define mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_0                             0xFC82A0
+
+#define mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_1                             0xFC82A4
+
+#define mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_2                             0xFC82A8
+
+#define mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_3                             0xFC82AC
+
+#define mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_4                             0xFC82B0
+
+#define mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_0                             0xFC82B4
+
+#define mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_1                             0xFC82B8
+
+#define mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_2                             0xFC82BC
+
+#define mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_3                             0xFC82C0
+
+#define mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_4                             0xFC82C4
+
+#define mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_0                             0xFC82C8
+
+#define mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_1                             0xFC82CC
+
+#define mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_2                             0xFC82D0
+
+#define mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_3                             0xFC82D4
+
+#define mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_4                             0xFC82D8
+
+#define mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0                       0xFC82E0
+
+#define mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1                       0xFC82E4
+
+#define mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2                       0xFC82E8
+
+#define mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3                       0xFC82EC
+
+#define mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4                       0xFC82F0
+
+#define mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_0                       0xFC82F4
+
+#define mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_1                       0xFC82F8
+
+#define mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_2                       0xFC82FC
+
+#define mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3                       0xFC8300
+
+#define mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_4                       0xFC8304
+
+#define mmTPC7_QM_CP_FENCE0_RDATA_0                                  0xFC8308
+
+#define mmTPC7_QM_CP_FENCE0_RDATA_1                                  0xFC830C
+
+#define mmTPC7_QM_CP_FENCE0_RDATA_2                                  0xFC8310
+
+#define mmTPC7_QM_CP_FENCE0_RDATA_3                                  0xFC8314
+
+#define mmTPC7_QM_CP_FENCE0_RDATA_4                                  0xFC8318
+
+#define mmTPC7_QM_CP_FENCE1_RDATA_0                                  0xFC831C
+
+#define mmTPC7_QM_CP_FENCE1_RDATA_1                                  0xFC8320
+
+#define mmTPC7_QM_CP_FENCE1_RDATA_2                                  0xFC8324
+
+#define mmTPC7_QM_CP_FENCE1_RDATA_3                                  0xFC8328
+
+#define mmTPC7_QM_CP_FENCE1_RDATA_4                                  0xFC832C
+
+#define mmTPC7_QM_CP_FENCE2_RDATA_0                                  0xFC8330
+
+#define mmTPC7_QM_CP_FENCE2_RDATA_1                                  0xFC8334
+
+#define mmTPC7_QM_CP_FENCE2_RDATA_2                                  0xFC8338
+
+#define mmTPC7_QM_CP_FENCE2_RDATA_3                                  0xFC833C
+
+#define mmTPC7_QM_CP_FENCE2_RDATA_4                                  0xFC8340
+
+#define mmTPC7_QM_CP_FENCE3_RDATA_0                                  0xFC8344
+
+#define mmTPC7_QM_CP_FENCE3_RDATA_1                                  0xFC8348
+
+#define mmTPC7_QM_CP_FENCE3_RDATA_2                                  0xFC834C
+
+#define mmTPC7_QM_CP_FENCE3_RDATA_3                                  0xFC8350
+
+#define mmTPC7_QM_CP_FENCE3_RDATA_4                                  0xFC8354
+
+#define mmTPC7_QM_CP_FENCE0_CNT_0                                    0xFC8358
+
+#define mmTPC7_QM_CP_FENCE0_CNT_1                                    0xFC835C
+
+#define mmTPC7_QM_CP_FENCE0_CNT_2                                    0xFC8360
+
+#define mmTPC7_QM_CP_FENCE0_CNT_3                                    0xFC8364
+
+#define mmTPC7_QM_CP_FENCE0_CNT_4                                    0xFC8368
+
+#define mmTPC7_QM_CP_FENCE1_CNT_0                                    0xFC836C
+
+#define mmTPC7_QM_CP_FENCE1_CNT_1                                    0xFC8370
+
+#define mmTPC7_QM_CP_FENCE1_CNT_2                                    0xFC8374
+
+#define mmTPC7_QM_CP_FENCE1_CNT_3                                    0xFC8378
+
+#define mmTPC7_QM_CP_FENCE1_CNT_4                                    0xFC837C
+
+#define mmTPC7_QM_CP_FENCE2_CNT_0                                    0xFC8380
+
+#define mmTPC7_QM_CP_FENCE2_CNT_1                                    0xFC8384
+
+#define mmTPC7_QM_CP_FENCE2_CNT_2                                    0xFC8388
+
+#define mmTPC7_QM_CP_FENCE2_CNT_3                                    0xFC838C
+
+#define mmTPC7_QM_CP_FENCE2_CNT_4                                    0xFC8390
+
+#define mmTPC7_QM_CP_FENCE3_CNT_0                                    0xFC8394
+
+#define mmTPC7_QM_CP_FENCE3_CNT_1                                    0xFC8398
+
+#define mmTPC7_QM_CP_FENCE3_CNT_2                                    0xFC839C
+
+#define mmTPC7_QM_CP_FENCE3_CNT_3                                    0xFC83A0
+
+#define mmTPC7_QM_CP_FENCE3_CNT_4                                    0xFC83A4
+
+#define mmTPC7_QM_CP_STS_0                                           0xFC83A8
+
+#define mmTPC7_QM_CP_STS_1                                           0xFC83AC
+
+#define mmTPC7_QM_CP_STS_2                                           0xFC83B0
+
+#define mmTPC7_QM_CP_STS_3                                           0xFC83B4
+
+#define mmTPC7_QM_CP_STS_4                                           0xFC83B8
+
+#define mmTPC7_QM_CP_CURRENT_INST_LO_0                               0xFC83BC
+
+#define mmTPC7_QM_CP_CURRENT_INST_LO_1                               0xFC83C0
+
+#define mmTPC7_QM_CP_CURRENT_INST_LO_2                               0xFC83C4
+
+#define mmTPC7_QM_CP_CURRENT_INST_LO_3                               0xFC83C8
+
+#define mmTPC7_QM_CP_CURRENT_INST_LO_4                               0xFC83CC
+
+#define mmTPC7_QM_CP_CURRENT_INST_HI_0                               0xFC83D0
+
+#define mmTPC7_QM_CP_CURRENT_INST_HI_1                               0xFC83D4
+
+#define mmTPC7_QM_CP_CURRENT_INST_HI_2                               0xFC83D8
+
+#define mmTPC7_QM_CP_CURRENT_INST_HI_3                               0xFC83DC
+
+#define mmTPC7_QM_CP_CURRENT_INST_HI_4                               0xFC83E0
+
+#define mmTPC7_QM_CP_BARRIER_CFG_0                                   0xFC83F4
+
+#define mmTPC7_QM_CP_BARRIER_CFG_1                                   0xFC83F8
+
+#define mmTPC7_QM_CP_BARRIER_CFG_2                                   0xFC83FC
+
+#define mmTPC7_QM_CP_BARRIER_CFG_3                                   0xFC8400
+
+#define mmTPC7_QM_CP_BARRIER_CFG_4                                   0xFC8404
+
+#define mmTPC7_QM_CP_DBG_0_0                                         0xFC8408
+
+#define mmTPC7_QM_CP_DBG_0_1                                         0xFC840C
+
+#define mmTPC7_QM_CP_DBG_0_2                                         0xFC8410
+
+#define mmTPC7_QM_CP_DBG_0_3                                         0xFC8414
+
+#define mmTPC7_QM_CP_DBG_0_4                                         0xFC8418
+
+#define mmTPC7_QM_CP_ARUSER_31_11_0                                  0xFC841C
+
+#define mmTPC7_QM_CP_ARUSER_31_11_1                                  0xFC8420
+
+#define mmTPC7_QM_CP_ARUSER_31_11_2                                  0xFC8424
+
+#define mmTPC7_QM_CP_ARUSER_31_11_3                                  0xFC8428
+
+#define mmTPC7_QM_CP_ARUSER_31_11_4                                  0xFC842C
+
+#define mmTPC7_QM_CP_AWUSER_31_11_0                                  0xFC8430
+
+#define mmTPC7_QM_CP_AWUSER_31_11_1                                  0xFC8434
+
+#define mmTPC7_QM_CP_AWUSER_31_11_2                                  0xFC8438
+
+#define mmTPC7_QM_CP_AWUSER_31_11_3                                  0xFC843C
+
+#define mmTPC7_QM_CP_AWUSER_31_11_4                                  0xFC8440
+
+#define mmTPC7_QM_ARB_CFG_0                                          0xFC8A00
+
+#define mmTPC7_QM_ARB_CHOISE_Q_PUSH                                  0xFC8A04
+
+#define mmTPC7_QM_ARB_WRR_WEIGHT_0                                   0xFC8A08
+
+#define mmTPC7_QM_ARB_WRR_WEIGHT_1                                   0xFC8A0C
+
+#define mmTPC7_QM_ARB_WRR_WEIGHT_2                                   0xFC8A10
+
+#define mmTPC7_QM_ARB_WRR_WEIGHT_3                                   0xFC8A14
+
+#define mmTPC7_QM_ARB_CFG_1                                          0xFC8A18
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_0                               0xFC8A20
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_1                               0xFC8A24
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_2                               0xFC8A28
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_3                               0xFC8A2C
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_4                               0xFC8A30
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_5                               0xFC8A34
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_6                               0xFC8A38
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_7                               0xFC8A3C
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_8                               0xFC8A40
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_9                               0xFC8A44
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_10                              0xFC8A48
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_11                              0xFC8A4C
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_12                              0xFC8A50
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_13                              0xFC8A54
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_14                              0xFC8A58
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_15                              0xFC8A5C
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_16                              0xFC8A60
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_17                              0xFC8A64
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_18                              0xFC8A68
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_19                              0xFC8A6C
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_20                              0xFC8A70
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_21                              0xFC8A74
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_22                              0xFC8A78
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_23                              0xFC8A7C
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_24                              0xFC8A80
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_25                              0xFC8A84
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_26                              0xFC8A88
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_27                              0xFC8A8C
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_28                              0xFC8A90
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_29                              0xFC8A94
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_30                              0xFC8A98
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_31                              0xFC8A9C
+
+#define mmTPC7_QM_ARB_MST_CRED_INC                                   0xFC8AA0
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_0                         0xFC8AA4
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_1                         0xFC8AA8
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_2                         0xFC8AAC
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_3                         0xFC8AB0
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_4                         0xFC8AB4
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_5                         0xFC8AB8
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_6                         0xFC8ABC
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_7                         0xFC8AC0
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_8                         0xFC8AC4
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_9                         0xFC8AC8
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_10                        0xFC8ACC
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_11                        0xFC8AD0
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_12                        0xFC8AD4
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_13                        0xFC8AD8
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_14                        0xFC8ADC
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_15                        0xFC8AE0
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_16                        0xFC8AE4
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_17                        0xFC8AE8
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_18                        0xFC8AEC
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_19                        0xFC8AF0
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_20                        0xFC8AF4
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_21                        0xFC8AF8
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_22                        0xFC8AFC
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_23                        0xFC8B00
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_24                        0xFC8B04
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_25                        0xFC8B08
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_26                        0xFC8B0C
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_27                        0xFC8B10
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_28                        0xFC8B14
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_29                        0xFC8B18
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_30                        0xFC8B1C
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_31                        0xFC8B20
+
+#define mmTPC7_QM_ARB_SLV_MASTER_INC_CRED_OFST                       0xFC8B28
+
+#define mmTPC7_QM_ARB_MST_SLAVE_EN                                   0xFC8B2C
+
+#define mmTPC7_QM_ARB_MST_QUIET_PER                                  0xFC8B34
+
+#define mmTPC7_QM_ARB_SLV_CHOISE_WDT                                 0xFC8B38
+
+#define mmTPC7_QM_ARB_SLV_ID                                         0xFC8B3C
+
+#define mmTPC7_QM_ARB_MSG_MAX_INFLIGHT                               0xFC8B44
+
+#define mmTPC7_QM_ARB_MSG_AWUSER_31_11                               0xFC8B48
+
+#define mmTPC7_QM_ARB_MSG_AWUSER_SEC_PROP                            0xFC8B4C
+
+#define mmTPC7_QM_ARB_MSG_AWUSER_NON_SEC_PROP                        0xFC8B50
+
+#define mmTPC7_QM_ARB_BASE_LO                                        0xFC8B54
+
+#define mmTPC7_QM_ARB_BASE_HI                                        0xFC8B58
+
+#define mmTPC7_QM_ARB_STATE_STS                                      0xFC8B80
+
+#define mmTPC7_QM_ARB_CHOISE_FULLNESS_STS                            0xFC8B84
+
+#define mmTPC7_QM_ARB_MSG_STS                                        0xFC8B88
+
+#define mmTPC7_QM_ARB_SLV_CHOISE_Q_HEAD                              0xFC8B8C
+
+#define mmTPC7_QM_ARB_ERR_CAUSE                                      0xFC8B9C
+
+#define mmTPC7_QM_ARB_ERR_MSG_EN                                     0xFC8BA0
+
+#define mmTPC7_QM_ARB_ERR_STS_DRP                                    0xFC8BA8
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_0                                 0xFC8BB0
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_1                                 0xFC8BB4
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_2                                 0xFC8BB8
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_3                                 0xFC8BBC
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_4                                 0xFC8BC0
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_5                                 0xFC8BC4
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_6                                 0xFC8BC8
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_7                                 0xFC8BCC
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_8                                 0xFC8BD0
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_9                                 0xFC8BD4
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_10                                0xFC8BD8
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_11                                0xFC8BDC
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_12                                0xFC8BE0
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_13                                0xFC8BE4
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_14                                0xFC8BE8
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_15                                0xFC8BEC
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_16                                0xFC8BF0
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_17                                0xFC8BF4
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_18                                0xFC8BF8
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_19                                0xFC8BFC
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_20                                0xFC8C00
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_21                                0xFC8C04
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_22                                0xFC8C08
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_23                                0xFC8C0C
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_24                                0xFC8C10
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_25                                0xFC8C14
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_26                                0xFC8C18
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_27                                0xFC8C1C
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_28                                0xFC8C20
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_29                                0xFC8C24
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_30                                0xFC8C28
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_31                                0xFC8C2C
+
+#define mmTPC7_QM_CGM_CFG                                            0xFC8C70
+
+#define mmTPC7_QM_CGM_STS                                            0xFC8C74
+
+#define mmTPC7_QM_CGM_CFG1                                           0xFC8C78
+
+#define mmTPC7_QM_LOCAL_RANGE_BASE                                   0xFC8C80
+
+#define mmTPC7_QM_LOCAL_RANGE_SIZE                                   0xFC8C84
+
+#define mmTPC7_QM_CSMR_STRICT_PRIO_CFG                               0xFC8C90
+
+#define mmTPC7_QM_HBW_RD_RATE_LIM_CFG_1                              0xFC8C94
+
+#define mmTPC7_QM_LBW_WR_RATE_LIM_CFG_0                              0xFC8C98
+
+#define mmTPC7_QM_LBW_WR_RATE_LIM_CFG_1                              0xFC8C9C
+
+#define mmTPC7_QM_HBW_RD_RATE_LIM_CFG_0                              0xFC8CA0
+
+#define mmTPC7_QM_GLBL_AXCACHE                                       0xFC8CA4
+
+#define mmTPC7_QM_IND_GW_APB_CFG                                     0xFC8CB0
+
+#define mmTPC7_QM_IND_GW_APB_WDATA                                   0xFC8CB4
+
+#define mmTPC7_QM_IND_GW_APB_RDATA                                   0xFC8CB8
+
+#define mmTPC7_QM_IND_GW_APB_STATUS                                  0xFC8CBC
+
+#define mmTPC7_QM_GLBL_ERR_ADDR_LO                                   0xFC8CD0
+
+#define mmTPC7_QM_GLBL_ERR_ADDR_HI                                   0xFC8CD4
+
+#define mmTPC7_QM_GLBL_ERR_WDATA                                     0xFC8CD8
+
+#define mmTPC7_QM_GLBL_MEM_INIT_BUSY                                 0xFC8D00
+
+#endif /* ASIC_REG_TPC7_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/gaudi.h b/drivers/accel/habanalabs/include/gaudi/gaudi.h
new file mode 100644
index 000000000000..ffae107b1693
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/gaudi.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2018-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+#ifndef GAUDI_H
+#define GAUDI_H
+
+#define SRAM_BAR_ID		0
+#define CFG_BAR_ID		2
+#define HBM_BAR_ID		4
+
+#define SRAM_BAR_SIZE		0x4000000ull		/* 64MB */
+#define CFG_BAR_SIZE		0x8000000ull		/* 128MB */
+
+#define CFG_BASE		0x7FFC000000ull
+#define CFG_SIZE		0x4000000		/* 32MB CFG + 32MB DBG*/
+
+#define SRAM_BASE_ADDR		0x7FF0000000ull
+#define SRAM_SIZE		0x1400000		/* 20MB */
+
+#define SPI_FLASH_BASE_ADDR	0x7FF8000000ull
+
+#define PSOC_SCRATCHPAD_ADDR	0x7FFBFE0000ull
+#define PSOC_SCRATCHPAD_SIZE	0x10000			/* 64KB */
+
+#define PCIE_FW_SRAM_ADDR	0x7FFBFF0000ull
+#define PCIE_FW_SRAM_SIZE	0x8000			/* 32KB */
+
+#define DRAM_PHYS_BASE		0x0ull
+
+#define HOST_PHYS_BASE		0x8000000000ull		/* 0.5TB */
+#define HOST_PHYS_SIZE		0x1000000000000ull	/* 0.25PB (48 bits) */
+
+#define GAUDI_MSI_ENTRIES	32
+
+#define QMAN_PQ_ENTRY_SIZE	16			/* Bytes */
+
+#define MAX_ASID		2
+
+#define PROT_BITS_OFFS		0xF80
+
+#define MME_NUMBER_OF_MASTER_ENGINES	2
+
+#define MME_NUMBER_OF_SLAVE_ENGINES	2
+
+#define TPC_NUMBER_OF_ENGINES	8
+
+#define DMA_NUMBER_OF_CHANNELS	8
+
+#define NIC_NUMBER_OF_MACROS	5
+
+#define NIC_NUMBER_OF_ENGINES	(NIC_NUMBER_OF_MACROS * 2)
+
+#define NUMBER_OF_IF		8
+
+#define DEVICE_CACHE_LINE_SIZE	128
+
+#endif /* GAUDI_H */
diff --git a/drivers/accel/habanalabs/include/gaudi/gaudi_async_events.h b/drivers/accel/habanalabs/include/gaudi/gaudi_async_events.h
new file mode 100644
index 000000000000..c07ed4ed304c
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/gaudi_async_events.h
@@ -0,0 +1,332 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2018-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef __GAUDI_ASYNC_EVENTS_H_
+#define __GAUDI_ASYNC_EVENTS_H_
+
+enum gaudi_async_event_id {
+	GAUDI_EVENT_PCIE_CORE_SERR = 32,
+	GAUDI_EVENT_PCIE_CORE_DERR = 33,
+	GAUDI_EVENT_PCIE_IF_SERR = 34,
+	GAUDI_EVENT_PCIE_IF_DERR = 35,
+	GAUDI_EVENT_PCIE_PHY_SERR = 36,
+	GAUDI_EVENT_PCIE_PHY_DERR = 37,
+	GAUDI_EVENT_TPC0_SERR = 38,
+	GAUDI_EVENT_TPC1_SERR = 39,
+	GAUDI_EVENT_TPC2_SERR = 40,
+	GAUDI_EVENT_TPC3_SERR = 41,
+	GAUDI_EVENT_TPC4_SERR = 42,
+	GAUDI_EVENT_TPC5_SERR = 43,
+	GAUDI_EVENT_TPC6_SERR = 44,
+	GAUDI_EVENT_TPC7_SERR = 45,
+	GAUDI_EVENT_TPC0_DERR = 46,
+	GAUDI_EVENT_TPC1_DERR = 47,
+	GAUDI_EVENT_TPC2_DERR = 48,
+	GAUDI_EVENT_TPC3_DERR = 49,
+	GAUDI_EVENT_TPC4_DERR = 50,
+	GAUDI_EVENT_TPC5_DERR = 51,
+	GAUDI_EVENT_TPC6_DERR = 52,
+	GAUDI_EVENT_TPC7_DERR = 53,
+	GAUDI_EVENT_MME0_ACC_SERR = 54,
+	GAUDI_EVENT_MME0_ACC_DERR = 55,
+	GAUDI_EVENT_MME0_SBAB_SERR = 56,
+	GAUDI_EVENT_MME0_SBAB_DERR = 57,
+	GAUDI_EVENT_MME1_ACC_SERR = 58,
+	GAUDI_EVENT_MME1_ACC_DERR = 59,
+	GAUDI_EVENT_MME1_SBAB_SERR = 60,
+	GAUDI_EVENT_MME1_SBAB_DERR = 61,
+	GAUDI_EVENT_MME2_ACC_SERR = 62,
+	GAUDI_EVENT_MME2_ACC_DERR = 63,
+	GAUDI_EVENT_MME2_SBAB_SERR = 64,
+	GAUDI_EVENT_MME2_SBAB_DERR = 65,
+	GAUDI_EVENT_MME3_ACC_SERR = 66,
+	GAUDI_EVENT_MME3_ACC_DERR = 67,
+	GAUDI_EVENT_MME3_SBAB_SERR = 68,
+	GAUDI_EVENT_MME3_SBAB_DERR = 69,
+	GAUDI_EVENT_DMA0_SERR_ECC = 70,
+	GAUDI_EVENT_DMA1_SERR_ECC = 71,
+	GAUDI_EVENT_DMA2_SERR_ECC = 72,
+	GAUDI_EVENT_DMA3_SERR_ECC = 73,
+	GAUDI_EVENT_DMA4_SERR_ECC = 74,
+	GAUDI_EVENT_DMA5_SERR_ECC = 75,
+	GAUDI_EVENT_DMA6_SERR_ECC = 76,
+	GAUDI_EVENT_DMA7_SERR_ECC = 77,
+	GAUDI_EVENT_DMA0_DERR_ECC = 78,
+	GAUDI_EVENT_DMA1_DERR_ECC = 79,
+	GAUDI_EVENT_DMA2_DERR_ECC = 80,
+	GAUDI_EVENT_DMA3_DERR_ECC = 81,
+	GAUDI_EVENT_DMA4_DERR_ECC = 82,
+	GAUDI_EVENT_DMA5_DERR_ECC = 83,
+	GAUDI_EVENT_DMA6_DERR_ECC = 84,
+	GAUDI_EVENT_DMA7_DERR_ECC = 85,
+	GAUDI_EVENT_CPU_IF_ECC_SERR = 86,
+	GAUDI_EVENT_CPU_IF_ECC_DERR = 87,
+	GAUDI_EVENT_PSOC_MEM_SERR = 88,
+	GAUDI_EVENT_PSOC_CORESIGHT_SERR = 89,
+	GAUDI_EVENT_PSOC_MEM_DERR = 90,
+	GAUDI_EVENT_PSOC_CORESIGHT_DERR = 91,
+	GAUDI_EVENT_SRAM0_SERR = 92,
+	GAUDI_EVENT_SRAM1_SERR = 93,
+	GAUDI_EVENT_SRAM2_SERR = 94,
+	GAUDI_EVENT_SRAM3_SERR = 95,
+	GAUDI_EVENT_SRAM7_SERR = 96,
+	GAUDI_EVENT_SRAM6_SERR = 97,
+	GAUDI_EVENT_SRAM5_SERR = 98,
+	GAUDI_EVENT_SRAM4_SERR = 99,
+	GAUDI_EVENT_SRAM8_SERR = 100,
+	GAUDI_EVENT_SRAM9_SERR = 101,
+	GAUDI_EVENT_SRAM10_SERR = 102,
+	GAUDI_EVENT_SRAM11_SERR = 103,
+	GAUDI_EVENT_SRAM15_SERR = 104,
+	GAUDI_EVENT_SRAM14_SERR = 105,
+	GAUDI_EVENT_SRAM13_SERR = 106,
+	GAUDI_EVENT_SRAM12_SERR = 107,
+	GAUDI_EVENT_SRAM16_SERR = 108,
+	GAUDI_EVENT_SRAM17_SERR = 109,
+	GAUDI_EVENT_SRAM18_SERR = 110,
+	GAUDI_EVENT_SRAM19_SERR = 111,
+	GAUDI_EVENT_SRAM23_SERR = 112,
+	GAUDI_EVENT_SRAM22_SERR = 113,
+	GAUDI_EVENT_SRAM21_SERR = 114,
+	GAUDI_EVENT_SRAM20_SERR = 115,
+	GAUDI_EVENT_SRAM24_SERR = 116,
+	GAUDI_EVENT_SRAM25_SERR = 117,
+	GAUDI_EVENT_SRAM26_SERR = 118,
+	GAUDI_EVENT_SRAM27_SERR = 119,
+	GAUDI_EVENT_SRAM31_SERR = 120,
+	GAUDI_EVENT_SRAM30_SERR = 121,
+	GAUDI_EVENT_SRAM29_SERR = 122,
+	GAUDI_EVENT_SRAM28_SERR = 123,
+	GAUDI_EVENT_SRAM0_DERR = 124,
+	GAUDI_EVENT_SRAM1_DERR = 125,
+	GAUDI_EVENT_SRAM2_DERR = 126,
+	GAUDI_EVENT_SRAM3_DERR = 127,
+	GAUDI_EVENT_SRAM7_DERR = 128,
+	GAUDI_EVENT_SRAM6_DERR = 129,
+	GAUDI_EVENT_SRAM5_DERR = 130,
+	GAUDI_EVENT_SRAM4_DERR = 131,
+	GAUDI_EVENT_SRAM8_DERR = 132,
+	GAUDI_EVENT_SRAM9_DERR = 133,
+	GAUDI_EVENT_SRAM10_DERR = 134,
+	GAUDI_EVENT_SRAM11_DERR = 135,
+	GAUDI_EVENT_SRAM15_DERR = 136,
+	GAUDI_EVENT_SRAM14_DERR = 137,
+	GAUDI_EVENT_SRAM13_DERR = 138,
+	GAUDI_EVENT_SRAM12_DERR = 139,
+	GAUDI_EVENT_SRAM16_DERR = 140,
+	GAUDI_EVENT_SRAM17_DERR = 141,
+	GAUDI_EVENT_SRAM18_DERR = 142,
+	GAUDI_EVENT_SRAM19_DERR = 143,
+	GAUDI_EVENT_SRAM23_DERR = 144,
+	GAUDI_EVENT_SRAM22_DERR = 145,
+	GAUDI_EVENT_SRAM21_DERR = 146,
+	GAUDI_EVENT_SRAM20_DERR = 147,
+	GAUDI_EVENT_SRAM24_DERR = 148,
+	GAUDI_EVENT_SRAM25_DERR = 149,
+	GAUDI_EVENT_SRAM26_DERR = 150,
+	GAUDI_EVENT_SRAM27_DERR = 151,
+	GAUDI_EVENT_SRAM31_DERR = 152,
+	GAUDI_EVENT_SRAM30_DERR = 153,
+	GAUDI_EVENT_SRAM29_DERR = 154,
+	GAUDI_EVENT_SRAM28_DERR = 155,
+	GAUDI_EVENT_NIC0_SERR = 156,
+	GAUDI_EVENT_NIC1_SERR = 157,
+	GAUDI_EVENT_NIC2_SERR = 158,
+	GAUDI_EVENT_NIC3_SERR = 159,
+	GAUDI_EVENT_NIC4_SERR = 160,
+	GAUDI_EVENT_NIC0_DERR = 166,
+	GAUDI_EVENT_NIC1_DERR = 167,
+	GAUDI_EVENT_NIC2_DERR = 168,
+	GAUDI_EVENT_NIC3_DERR = 169,
+	GAUDI_EVENT_NIC4_DERR = 170,
+	GAUDI_EVENT_DMA_IF0_SERR = 176,
+	GAUDI_EVENT_DMA_IF1_SERR = 177,
+	GAUDI_EVENT_DMA_IF2_SERR = 178,
+	GAUDI_EVENT_DMA_IF3_SERR = 179,
+	GAUDI_EVENT_DMA_IF0_DERR = 180,
+	GAUDI_EVENT_DMA_IF1_DERR = 181,
+	GAUDI_EVENT_DMA_IF2_DERR = 182,
+	GAUDI_EVENT_DMA_IF3_DERR = 183,
+	GAUDI_EVENT_GIC500 = 184,
+	GAUDI_EVENT_HBM_0_SERR = 185,
+	GAUDI_EVENT_HBM_1_SERR = 186,
+	GAUDI_EVENT_HBM_2_SERR = 187,
+	GAUDI_EVENT_HBM_3_SERR = 188,
+	GAUDI_EVENT_HBM_0_DERR = 189,
+	GAUDI_EVENT_HBM_1_DERR = 190,
+	GAUDI_EVENT_HBM_2_DERR = 191,
+	GAUDI_EVENT_HBM_3_DERR = 192,
+	GAUDI_EVENT_MMU_SERR = 193,
+	GAUDI_EVENT_MMU_DERR = 194,
+	GAUDI_EVENT_PCIE_DEC = 200,
+	GAUDI_EVENT_TPC0_DEC = 201,
+	GAUDI_EVENT_TPC1_DEC = 203,
+	GAUDI_EVENT_TPC2_DEC = 205,
+	GAUDI_EVENT_TPC3_DEC = 207,
+	GAUDI_EVENT_TPC4_DEC = 209,
+	GAUDI_EVENT_TPC5_DEC = 211,
+	GAUDI_EVENT_TPC6_DEC = 213,
+	GAUDI_EVENT_TPC7_DEC = 215,
+	GAUDI_EVENT_AXI_ECC = 217,
+	GAUDI_EVENT_L2_RAM_ECC = 218,
+	GAUDI_EVENT_MME0_WBC_RSP = 219,
+	GAUDI_EVENT_MME0_SBAB0_RSP = 220,
+	GAUDI_EVENT_MME1_WBC_RSP = 224,
+	GAUDI_EVENT_MME1_SBAB0_RSP = 225,
+	GAUDI_EVENT_MME2_WBC_RSP = 229,
+	GAUDI_EVENT_MME2_SBAB0_RSP = 230,
+	GAUDI_EVENT_MME3_WBC_RSP = 234,
+	GAUDI_EVENT_MME3_SBAB0_RSP = 235,
+	GAUDI_EVENT_PLL0 = 239,
+	GAUDI_EVENT_PLL1 = 240,
+	GAUDI_EVENT_PLL2 = 241,
+	GAUDI_EVENT_PLL3 = 242,
+	GAUDI_EVENT_PLL4 = 243,
+	GAUDI_EVENT_PLL5 = 244,
+	GAUDI_EVENT_PLL6 = 245,
+	GAUDI_EVENT_PLL7 = 246,
+	GAUDI_EVENT_PLL8 = 247,
+	GAUDI_EVENT_PLL9 = 248,
+	GAUDI_EVENT_PLL10 = 249,
+	GAUDI_EVENT_PLL11 = 250,
+	GAUDI_EVENT_PLL12 = 251,
+	GAUDI_EVENT_PLL13 = 252,
+	GAUDI_EVENT_PLL14 = 253,
+	GAUDI_EVENT_PLL15 = 254,
+	GAUDI_EVENT_PLL16 = 255,
+	GAUDI_EVENT_PLL17 = 256,
+	GAUDI_EVENT_CPU_AXI_SPLITTER = 257,
+	GAUDI_EVENT_PSOC_AXI_DEC = 262,
+	GAUDI_EVENT_PSOC_PRSTN_FALL = 263,
+	GAUDI_EVENT_NIC_SEI_0 = 264,
+	GAUDI_EVENT_NIC_SEI_1 = 265,
+	GAUDI_EVENT_NIC_SEI_2 = 266,
+	GAUDI_EVENT_NIC_SEI_3 = 267,
+	GAUDI_EVENT_NIC_SEI_4 = 268,
+	GAUDI_EVENT_DMA_IF_SEI_0 = 277,
+	GAUDI_EVENT_DMA_IF_SEI_1 = 278,
+	GAUDI_EVENT_DMA_IF_SEI_2 = 279,
+	GAUDI_EVENT_DMA_IF_SEI_3 = 280,
+	GAUDI_EVENT_PCIE_FLR = 290,
+	GAUDI_EVENT_TPC0_BMON_SPMU = 300,
+	GAUDI_EVENT_TPC0_KRN_ERR = 301,
+	GAUDI_EVENT_TPC1_BMON_SPMU = 306,
+	GAUDI_EVENT_TPC1_KRN_ERR = 307,
+	GAUDI_EVENT_TPC2_BMON_SPMU = 312,
+	GAUDI_EVENT_TPC2_KRN_ERR = 313,
+	GAUDI_EVENT_TPC3_BMON_SPMU = 318,
+	GAUDI_EVENT_TPC3_KRN_ERR = 319,
+	GAUDI_EVENT_TPC4_BMON_SPMU = 324,
+	GAUDI_EVENT_TPC4_KRN_ERR = 325,
+	GAUDI_EVENT_TPC5_BMON_SPMU = 330,
+	GAUDI_EVENT_TPC5_KRN_ERR = 331,
+	GAUDI_EVENT_TPC6_BMON_SPMU = 336,
+	GAUDI_EVENT_TPC6_KRN_ERR = 337,
+	GAUDI_EVENT_TPC7_BMON_SPMU = 342,
+	GAUDI_EVENT_TPC7_KRN_ERR = 343,
+	GAUDI_EVENT_MMU_PAGE_FAULT = 380,
+	GAUDI_EVENT_MMU_WR_PERM = 381,
+	GAUDI_EVENT_DMA_BM_CH0 = 383,
+	GAUDI_EVENT_DMA_BM_CH1 = 384,
+	GAUDI_EVENT_DMA_BM_CH2 = 385,
+	GAUDI_EVENT_DMA_BM_CH3 = 386,
+	GAUDI_EVENT_DMA_BM_CH4 = 387,
+	GAUDI_EVENT_DMA_BM_CH5 = 388,
+	GAUDI_EVENT_DMA_BM_CH6 = 389,
+	GAUDI_EVENT_DMA_BM_CH7 = 390,
+	GAUDI_EVENT_HBM0_SPI_0 = 395,
+	GAUDI_EVENT_HBM0_SPI_1 = 396,
+	GAUDI_EVENT_HBM1_SPI_0 = 399,
+	GAUDI_EVENT_HBM1_SPI_1 = 400,
+	GAUDI_EVENT_HBM2_SPI_0 = 403,
+	GAUDI_EVENT_HBM2_SPI_1 = 404,
+	GAUDI_EVENT_HBM3_SPI_0 = 407,
+	GAUDI_EVENT_HBM3_SPI_1 = 408,
+	GAUDI_EVENT_PSOC_GPIO_U16_0 = 421,
+	GAUDI_EVENT_NIC0_CS_DBG_DERR = 483,
+	GAUDI_EVENT_NIC1_CS_DBG_DERR = 487,
+	GAUDI_EVENT_NIC2_CS_DBG_DERR = 491,
+	GAUDI_EVENT_NIC3_CS_DBG_DERR = 495,
+	GAUDI_EVENT_NIC4_CS_DBG_DERR = 499,
+	GAUDI_EVENT_RAZWI_OR_ADC = 548,
+	GAUDI_EVENT_TPC0_QM = 572,
+	GAUDI_EVENT_TPC1_QM = 573,
+	GAUDI_EVENT_TPC2_QM = 574,
+	GAUDI_EVENT_TPC3_QM = 575,
+	GAUDI_EVENT_TPC4_QM = 576,
+	GAUDI_EVENT_TPC5_QM = 577,
+	GAUDI_EVENT_TPC6_QM = 578,
+	GAUDI_EVENT_TPC7_QM = 579,
+	GAUDI_EVENT_MME0_QM = 581,
+	GAUDI_EVENT_MME2_QM = 582,
+	GAUDI_EVENT_DMA0_QM = 583,
+	GAUDI_EVENT_DMA1_QM = 584,
+	GAUDI_EVENT_DMA2_QM = 585,
+	GAUDI_EVENT_DMA3_QM = 586,
+	GAUDI_EVENT_DMA4_QM = 587,
+	GAUDI_EVENT_DMA5_QM = 588,
+	GAUDI_EVENT_DMA6_QM = 589,
+	GAUDI_EVENT_DMA7_QM = 590,
+	GAUDI_EVENT_NIC0_QM0 = 594,
+	GAUDI_EVENT_NIC0_QM1 = 595,
+	GAUDI_EVENT_NIC1_QM0 = 596,
+	GAUDI_EVENT_NIC1_QM1 = 597,
+	GAUDI_EVENT_NIC2_QM0 = 598,
+	GAUDI_EVENT_NIC2_QM1 = 599,
+	GAUDI_EVENT_NIC3_QM0 = 600,
+	GAUDI_EVENT_NIC3_QM1 = 601,
+	GAUDI_EVENT_NIC4_QM0 = 602,
+	GAUDI_EVENT_NIC4_QM1 = 603,
+	GAUDI_EVENT_DMA0_CORE = 604,
+	GAUDI_EVENT_DMA1_CORE = 605,
+	GAUDI_EVENT_DMA2_CORE = 606,
+	GAUDI_EVENT_DMA3_CORE = 607,
+	GAUDI_EVENT_DMA4_CORE = 608,
+	GAUDI_EVENT_DMA5_CORE = 609,
+	GAUDI_EVENT_DMA6_CORE = 610,
+	GAUDI_EVENT_DMA7_CORE = 611,
+	GAUDI_EVENT_NIC0_QP0 = 612,
+	GAUDI_EVENT_NIC0_QP1 = 613,
+	GAUDI_EVENT_NIC1_QP0 = 614,
+	GAUDI_EVENT_NIC1_QP1 = 615,
+	GAUDI_EVENT_NIC2_QP0 = 616,
+	GAUDI_EVENT_NIC2_QP1 = 617,
+	GAUDI_EVENT_NIC3_QP0 = 618,
+	GAUDI_EVENT_NIC3_QP1 = 619,
+	GAUDI_EVENT_NIC4_QP0 = 620,
+	GAUDI_EVENT_NIC4_QP1 = 621,
+	GAUDI_EVENT_PI_UPDATE = 635,
+	GAUDI_EVENT_HALT_MACHINE = 636,
+	GAUDI_EVENT_INTS_REGISTER = 637,
+	GAUDI_EVENT_SOFT_RESET = 638,
+	GAUDI_EVENT_FW_ALIVE_S = 645,
+	GAUDI_EVENT_DEV_RESET_REQ = 646,
+	GAUDI_EVENT_PKT_QUEUE_OUT_SYNC = 647,
+	GAUDI_EVENT_STATUS_NIC0_ENG0 = 648,
+	GAUDI_EVENT_STATUS_NIC0_ENG1 = 649,
+	GAUDI_EVENT_STATUS_NIC1_ENG0 = 650,
+	GAUDI_EVENT_STATUS_NIC1_ENG1 = 651,
+	GAUDI_EVENT_STATUS_NIC2_ENG0 = 652,
+	GAUDI_EVENT_STATUS_NIC2_ENG1 = 653,
+	GAUDI_EVENT_STATUS_NIC3_ENG0 = 654,
+	GAUDI_EVENT_STATUS_NIC3_ENG1 = 655,
+	GAUDI_EVENT_STATUS_NIC4_ENG0 = 656,
+	GAUDI_EVENT_STATUS_NIC4_ENG1 = 657,
+	GAUDI_EVENT_FIX_POWER_ENV_S = 658,
+	GAUDI_EVENT_FIX_POWER_ENV_E = 659,
+	GAUDI_EVENT_FIX_THERMAL_ENV_S = 660,
+	GAUDI_EVENT_FIX_THERMAL_ENV_E = 661,
+	GAUDI_EVENT_RAZWI_OR_ADC_SW = 662,
+	GAUDI_EVENT_SIZE,
+};
+
+#endif /* __GAUDI_ASYNC_EVENTS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/gaudi_async_ids_map_extended.h b/drivers/accel/habanalabs/include/gaudi/gaudi_async_ids_map_extended.h
new file mode 100644
index 000000000000..479b6b038254
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/gaudi_async_ids_map_extended.h
@@ -0,0 +1,710 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2018-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef __GAUDI_ASYNC_IDS_MAP_EVENTS_EXT_H_
+#define __GAUDI_ASYNC_IDS_MAP_EVENTS_EXT_H_
+
+struct gaudi_async_events_ids_map {
+	int fc_id;
+	int cpu_id;
+	int valid;
+	char name[64];
+};
+
+static struct gaudi_async_events_ids_map gaudi_irq_map_table[] = {
+	{ .fc_id = 0, .cpu_id = 0, .valid = 0, .name = "" },
+	{ .fc_id = 1, .cpu_id = 1, .valid = 0, .name = "" },
+	{ .fc_id = 2, .cpu_id = 2, .valid = 0, .name = "" },
+	{ .fc_id = 3, .cpu_id = 3, .valid = 0, .name = "" },
+	{ .fc_id = 4, .cpu_id = 4, .valid = 0, .name = "" },
+	{ .fc_id = 5, .cpu_id = 5, .valid = 0, .name = "" },
+	{ .fc_id = 6, .cpu_id = 6, .valid = 0, .name = "" },
+	{ .fc_id = 7, .cpu_id = 7, .valid = 0, .name = "" },
+	{ .fc_id = 8, .cpu_id = 8, .valid = 0, .name = "" },
+	{ .fc_id = 9, .cpu_id = 9, .valid = 0, .name = "" },
+	{ .fc_id = 10, .cpu_id = 10, .valid = 0, .name = "" },
+	{ .fc_id = 11, .cpu_id = 11, .valid = 0, .name = "" },
+	{ .fc_id = 12, .cpu_id = 12, .valid = 0, .name = "" },
+	{ .fc_id = 13, .cpu_id = 13, .valid = 0, .name = "" },
+	{ .fc_id = 14, .cpu_id = 14, .valid = 0, .name = "" },
+	{ .fc_id = 15, .cpu_id = 15, .valid = 0, .name = "" },
+	{ .fc_id = 16, .cpu_id = 16, .valid = 0, .name = "" },
+	{ .fc_id = 17, .cpu_id = 17, .valid = 0, .name = "" },
+	{ .fc_id = 18, .cpu_id = 18, .valid = 0, .name = "" },
+	{ .fc_id = 19, .cpu_id = 19, .valid = 0, .name = "" },
+	{ .fc_id = 20, .cpu_id = 20, .valid = 0, .name = "" },
+	{ .fc_id = 21, .cpu_id = 21, .valid = 0, .name = "" },
+	{ .fc_id = 22, .cpu_id = 22, .valid = 0, .name = "" },
+	{ .fc_id = 23, .cpu_id = 23, .valid = 0, .name = "" },
+	{ .fc_id = 24, .cpu_id = 24, .valid = 0, .name = "" },
+	{ .fc_id = 25, .cpu_id = 25, .valid = 0, .name = "" },
+	{ .fc_id = 26, .cpu_id = 26, .valid = 0, .name = "" },
+	{ .fc_id = 27, .cpu_id = 27, .valid = 0, .name = "" },
+	{ .fc_id = 28, .cpu_id = 28, .valid = 0, .name = "" },
+	{ .fc_id = 29, .cpu_id = 29, .valid = 0, .name = "" },
+	{ .fc_id = 30, .cpu_id = 30, .valid = 0, .name = "" },
+	{ .fc_id = 31, .cpu_id = 31, .valid = 0, .name = "" },
+	{ .fc_id = 32, .cpu_id = 32, .valid = 1, .name = "PCIE_CORE_SERR" },
+	{ .fc_id = 33, .cpu_id = 33, .valid = 1, .name = "PCIE_CORE_DERR" },
+	{ .fc_id = 34, .cpu_id = 34, .valid = 1, .name = "PCIE_IF_SERR" },
+	{ .fc_id = 35, .cpu_id = 35, .valid = 1, .name = "PCIE_IF_DERR" },
+	{ .fc_id = 36, .cpu_id = 36, .valid = 1, .name = "PCIE_PHY_SERR" },
+	{ .fc_id = 37, .cpu_id = 37, .valid = 1, .name = "PCIE_PHY_DERR" },
+	{ .fc_id = 38, .cpu_id = 38, .valid = 1, .name = "TPC0_SERR" },
+	{ .fc_id = 39, .cpu_id = 38, .valid = 1, .name = "TPC1_SERR" },
+	{ .fc_id = 40, .cpu_id = 38, .valid = 1, .name = "TPC2_SERR" },
+	{ .fc_id = 41, .cpu_id = 38, .valid = 1, .name = "TPC3_SERR" },
+	{ .fc_id = 42, .cpu_id = 38, .valid = 1, .name = "TPC4_SERR" },
+	{ .fc_id = 43, .cpu_id = 38, .valid = 1, .name = "TPC5_SERR" },
+	{ .fc_id = 44, .cpu_id = 38, .valid = 1, .name = "TPC6_SERR" },
+	{ .fc_id = 45, .cpu_id = 38, .valid = 1, .name = "TPC7_SERR" },
+	{ .fc_id = 46, .cpu_id = 39, .valid = 1, .name = "TPC0_DERR" },
+	{ .fc_id = 47, .cpu_id = 39, .valid = 1, .name = "TPC1_DERR" },
+	{ .fc_id = 48, .cpu_id = 39, .valid = 1, .name = "TPC2_DERR" },
+	{ .fc_id = 49, .cpu_id = 39, .valid = 1, .name = "TPC3_DERR" },
+	{ .fc_id = 50, .cpu_id = 39, .valid = 1, .name = "TPC4_DERR" },
+	{ .fc_id = 51, .cpu_id = 39, .valid = 1, .name = "TPC5_DERR" },
+	{ .fc_id = 52, .cpu_id = 39, .valid = 1, .name = "TPC6_DERR" },
+	{ .fc_id = 53, .cpu_id = 39, .valid = 1, .name = "TPC7_DERR" },
+	{ .fc_id = 54, .cpu_id = 40, .valid = 1, .name = "MME0_ACC_SERR" },
+	{ .fc_id = 55, .cpu_id = 41, .valid = 1, .name = "MME0_ACC_DERR" },
+	{ .fc_id = 56, .cpu_id = 42, .valid = 1, .name = "MME0_SBAB_SERR" },
+	{ .fc_id = 57, .cpu_id = 43, .valid = 1, .name = "MME0_SBAB_DERR" },
+	{ .fc_id = 58, .cpu_id = 44, .valid = 1, .name = "MME1_ACC_SERR" },
+	{ .fc_id = 59, .cpu_id = 45, .valid = 1, .name = "MME1_ACC_DERR" },
+	{ .fc_id = 60, .cpu_id = 46, .valid = 1, .name = "MME1_SBAB_SERR" },
+	{ .fc_id = 61, .cpu_id = 47, .valid = 1, .name = "MME1_SBAB_DERR" },
+	{ .fc_id = 62, .cpu_id = 48, .valid = 1, .name = "MME2_ACC_SERR" },
+	{ .fc_id = 63, .cpu_id = 49, .valid = 1, .name = "MME2_ACC_DERR" },
+	{ .fc_id = 64, .cpu_id = 50, .valid = 1, .name = "MME2_SBAB_SERR" },
+	{ .fc_id = 65, .cpu_id = 51, .valid = 1, .name = "MME2_SBAB_DERR" },
+	{ .fc_id = 66, .cpu_id = 52, .valid = 1, .name = "MME3_ACC_SERR" },
+	{ .fc_id = 67, .cpu_id = 53, .valid = 1, .name = "MME3_ACC_DERR" },
+	{ .fc_id = 68, .cpu_id = 54, .valid = 1, .name = "MME3_SBAB_SERR" },
+	{ .fc_id = 69, .cpu_id = 55, .valid = 1, .name = "MME3_SBAB_DERR" },
+	{ .fc_id = 70, .cpu_id = 56, .valid = 1, .name = "DMA0_SERR_ECC" },
+	{ .fc_id = 71, .cpu_id = 56, .valid = 1, .name = "DMA1_SERR_ECC" },
+	{ .fc_id = 72, .cpu_id = 56, .valid = 1, .name = "DMA2_SERR_ECC" },
+	{ .fc_id = 73, .cpu_id = 56, .valid = 1, .name = "DMA3_SERR_ECC" },
+	{ .fc_id = 74, .cpu_id = 56, .valid = 1, .name = "DMA4_SERR_ECC" },
+	{ .fc_id = 75, .cpu_id = 56, .valid = 1, .name = "DMA5_SERR_ECC" },
+	{ .fc_id = 76, .cpu_id = 56, .valid = 1, .name = "DMA6_SERR_ECC" },
+	{ .fc_id = 77, .cpu_id = 56, .valid = 1, .name = "DMA7_SERR_ECC" },
+	{ .fc_id = 78, .cpu_id = 57, .valid = 1, .name = "DMA0_DERR_ECC" },
+	{ .fc_id = 79, .cpu_id = 57, .valid = 1, .name = "DMA1_DERR_ECC" },
+	{ .fc_id = 80, .cpu_id = 57, .valid = 1, .name = "DMA2_DERR_ECC" },
+	{ .fc_id = 81, .cpu_id = 57, .valid = 1, .name = "DMA3_DERR_ECC" },
+	{ .fc_id = 82, .cpu_id = 57, .valid = 1, .name = "DMA4_DERR_ECC" },
+	{ .fc_id = 83, .cpu_id = 57, .valid = 1, .name = "DMA5_DERR_ECC" },
+	{ .fc_id = 84, .cpu_id = 57, .valid = 1, .name = "DMA6_DERR_ECC" },
+	{ .fc_id = 85, .cpu_id = 57, .valid = 1, .name = "DMA7_DERR_ECC" },
+	{ .fc_id = 86, .cpu_id = 58, .valid = 1, .name = "CPU_IF_ECC_SERR" },
+	{ .fc_id = 87, .cpu_id = 59, .valid = 1, .name = "CPU_IF_ECC_DERR" },
+	{ .fc_id = 88, .cpu_id = 60, .valid = 1, .name = "PSOC_MEM_SERR" },
+	{ .fc_id = 89, .cpu_id = 61, .valid = 1,
+		.name = "PSOC_CORESIGHT_SERR" },
+	{ .fc_id = 90, .cpu_id = 62, .valid = 1, .name = "PSOC_MEM_DERR" },
+	{ .fc_id = 91, .cpu_id = 63, .valid = 1,
+		.name = "PSOC_CORESIGHT_DERR" },
+	{ .fc_id = 92, .cpu_id = 64, .valid = 1, .name = "SRAM0_SERR" },
+	{ .fc_id = 93, .cpu_id = 64, .valid = 1, .name = "SRAM1_SERR" },
+	{ .fc_id = 94, .cpu_id = 64, .valid = 1, .name = "SRAM2_SERR" },
+	{ .fc_id = 95, .cpu_id = 64, .valid = 1, .name = "SRAM3_SERR" },
+	{ .fc_id = 96, .cpu_id = 64, .valid = 1, .name = "SRAM7_SERR" },
+	{ .fc_id = 97, .cpu_id = 64, .valid = 1, .name = "SRAM6_SERR" },
+	{ .fc_id = 98, .cpu_id = 64, .valid = 1, .name = "SRAM5_SERR" },
+	{ .fc_id = 99, .cpu_id = 64, .valid = 1, .name = "SRAM4_SERR" },
+	{ .fc_id = 100, .cpu_id = 64, .valid = 1, .name = "SRAM8_SERR" },
+	{ .fc_id = 101, .cpu_id = 64, .valid = 1, .name = "SRAM9_SERR" },
+	{ .fc_id = 102, .cpu_id = 64, .valid = 1, .name = "SRAM10_SERR" },
+	{ .fc_id = 103, .cpu_id = 64, .valid = 1, .name = "SRAM11_SERR" },
+	{ .fc_id = 104, .cpu_id = 64, .valid = 1, .name = "SRAM15_SERR" },
+	{ .fc_id = 105, .cpu_id = 64, .valid = 1, .name = "SRAM14_SERR" },
+	{ .fc_id = 106, .cpu_id = 64, .valid = 1, .name = "SRAM13_SERR" },
+	{ .fc_id = 107, .cpu_id = 64, .valid = 1, .name = "SRAM12_SERR" },
+	{ .fc_id = 108, .cpu_id = 64, .valid = 1, .name = "SRAM16_SERR" },
+	{ .fc_id = 109, .cpu_id = 64, .valid = 1, .name = "SRAM17_SERR" },
+	{ .fc_id = 110, .cpu_id = 64, .valid = 1, .name = "SRAM18_SERR" },
+	{ .fc_id = 111, .cpu_id = 64, .valid = 1, .name = "SRAM19_SERR" },
+	{ .fc_id = 112, .cpu_id = 64, .valid = 1, .name = "SRAM23_SERR" },
+	{ .fc_id = 113, .cpu_id = 64, .valid = 1, .name = "SRAM22_SERR" },
+	{ .fc_id = 114, .cpu_id = 64, .valid = 1, .name = "SRAM21_SERR" },
+	{ .fc_id = 115, .cpu_id = 64, .valid = 1, .name = "SRAM20_SERR" },
+	{ .fc_id = 116, .cpu_id = 64, .valid = 1, .name = "SRAM24_SERR" },
+	{ .fc_id = 117, .cpu_id = 64, .valid = 1, .name = "SRAM25_SERR" },
+	{ .fc_id = 118, .cpu_id = 64, .valid = 1, .name = "SRAM26_SERR" },
+	{ .fc_id = 119, .cpu_id = 64, .valid = 1, .name = "SRAM27_SERR" },
+	{ .fc_id = 120, .cpu_id = 64, .valid = 1, .name = "SRAM31_SERR" },
+	{ .fc_id = 121, .cpu_id = 64, .valid = 1, .name = "SRAM30_SERR" },
+	{ .fc_id = 122, .cpu_id = 64, .valid = 1, .name = "SRAM29_SERR" },
+	{ .fc_id = 123, .cpu_id = 64, .valid = 1, .name = "SRAM28_SERR" },
+	{ .fc_id = 124, .cpu_id = 65, .valid = 1, .name = "SRAM0_DERR" },
+	{ .fc_id = 125, .cpu_id = 65, .valid = 1, .name = "SRAM1_DERR" },
+	{ .fc_id = 126, .cpu_id = 65, .valid = 1, .name = "SRAM2_DERR" },
+	{ .fc_id = 127, .cpu_id = 65, .valid = 1, .name = "SRAM3_DERR" },
+	{ .fc_id = 128, .cpu_id = 65, .valid = 1, .name = "SRAM7_DERR" },
+	{ .fc_id = 129, .cpu_id = 65, .valid = 1, .name = "SRAM6_DERR" },
+	{ .fc_id = 130, .cpu_id = 65, .valid = 1, .name = "SRAM5_DERR" },
+	{ .fc_id = 131, .cpu_id = 65, .valid = 1, .name = "SRAM4_DERR" },
+	{ .fc_id = 132, .cpu_id = 65, .valid = 1, .name = "SRAM8_DERR" },
+	{ .fc_id = 133, .cpu_id = 65, .valid = 1, .name = "SRAM9_DERR" },
+	{ .fc_id = 134, .cpu_id = 65, .valid = 1, .name = "SRAM10_DERR" },
+	{ .fc_id = 135, .cpu_id = 65, .valid = 1, .name = "SRAM11_DERR" },
+	{ .fc_id = 136, .cpu_id = 65, .valid = 1, .name = "SRAM15_DERR" },
+	{ .fc_id = 137, .cpu_id = 65, .valid = 1, .name = "SRAM14_DERR" },
+	{ .fc_id = 138, .cpu_id = 65, .valid = 1, .name = "SRAM13_DERR" },
+	{ .fc_id = 139, .cpu_id = 65, .valid = 1, .name = "SRAM12_DERR" },
+	{ .fc_id = 140, .cpu_id = 65, .valid = 1, .name = "SRAM16_DERR" },
+	{ .fc_id = 141, .cpu_id = 65, .valid = 1, .name = "SRAM17_DERR" },
+	{ .fc_id = 142, .cpu_id = 65, .valid = 1, .name = "SRAM18_DERR" },
+	{ .fc_id = 143, .cpu_id = 65, .valid = 1, .name = "SRAM19_DERR" },
+	{ .fc_id = 144, .cpu_id = 65, .valid = 1, .name = "SRAM23_DERR" },
+	{ .fc_id = 145, .cpu_id = 65, .valid = 1, .name = "SRAM22_DERR" },
+	{ .fc_id = 146, .cpu_id = 65, .valid = 1, .name = "SRAM21_DERR" },
+	{ .fc_id = 147, .cpu_id = 65, .valid = 1, .name = "SRAM20_DERR" },
+	{ .fc_id = 148, .cpu_id = 65, .valid = 1, .name = "SRAM24_DERR" },
+	{ .fc_id = 149, .cpu_id = 65, .valid = 1, .name = "SRAM25_DERR" },
+	{ .fc_id = 150, .cpu_id = 65, .valid = 1, .name = "SRAM26_DERR" },
+	{ .fc_id = 151, .cpu_id = 65, .valid = 1, .name = "SRAM27_DERR" },
+	{ .fc_id = 152, .cpu_id = 65, .valid = 1, .name = "SRAM31_DERR" },
+	{ .fc_id = 153, .cpu_id = 65, .valid = 1, .name = "SRAM30_DERR" },
+	{ .fc_id = 154, .cpu_id = 65, .valid = 1, .name = "SRAM29_DERR" },
+	{ .fc_id = 155, .cpu_id = 65, .valid = 1, .name = "SRAM28_DERR" },
+	{ .fc_id = 156, .cpu_id = 66, .valid = 1, .name = "NIC0_SERR" },
+	{ .fc_id = 157, .cpu_id = 66, .valid = 1, .name = "NIC1_SERR" },
+	{ .fc_id = 158, .cpu_id = 66, .valid = 1, .name = "NIC2_SERR" },
+	{ .fc_id = 159, .cpu_id = 66, .valid = 1, .name = "NIC3_SERR" },
+	{ .fc_id = 160, .cpu_id = 66, .valid = 1, .name = "NIC4_SERR" },
+	{ .fc_id = 161, .cpu_id = 66, .valid = 0, .name = "" },
+	{ .fc_id = 162, .cpu_id = 66, .valid = 0, .name = "" },
+	{ .fc_id = 163, .cpu_id = 66, .valid = 0, .name = "" },
+	{ .fc_id = 164, .cpu_id = 66, .valid = 0, .name = "" },
+	{ .fc_id = 165, .cpu_id = 66, .valid = 0, .name = "" },
+	{ .fc_id = 166, .cpu_id = 67, .valid = 1, .name = "NIC0_DERR" },
+	{ .fc_id = 167, .cpu_id = 67, .valid = 1, .name = "NIC1_DERR" },
+	{ .fc_id = 168, .cpu_id = 67, .valid = 1, .name = "NIC2_DERR" },
+	{ .fc_id = 169, .cpu_id = 67, .valid = 1, .name = "NIC3_DERR" },
+	{ .fc_id = 170, .cpu_id = 67, .valid = 1, .name = "NIC4_DERR" },
+	{ .fc_id = 171, .cpu_id = 67, .valid = 0, .name = "" },
+	{ .fc_id = 172, .cpu_id = 67, .valid = 0, .name = "" },
+	{ .fc_id = 173, .cpu_id = 67, .valid = 0, .name = "" },
+	{ .fc_id = 174, .cpu_id = 67, .valid = 0, .name = "" },
+	{ .fc_id = 175, .cpu_id = 67, .valid = 0, .name = "" },
+	{ .fc_id = 176, .cpu_id = 68, .valid = 1, .name = "DMA_IF0_SERR" },
+	{ .fc_id = 177, .cpu_id = 68, .valid = 1, .name = "DMA_IF1_SERR" },
+	{ .fc_id = 178, .cpu_id = 68, .valid = 1, .name = "DMA_IF2_SERR" },
+	{ .fc_id = 179, .cpu_id = 68, .valid = 1, .name = "DMA_IF3_SERR" },
+	{ .fc_id = 180, .cpu_id = 69, .valid = 1, .name = "DMA_IF0_DERR" },
+	{ .fc_id = 181, .cpu_id = 69, .valid = 1, .name = "DMA_IF1_DERR" },
+	{ .fc_id = 182, .cpu_id = 69, .valid = 1, .name = "DMA_IF2_DERR" },
+	{ .fc_id = 183, .cpu_id = 69, .valid = 1, .name = "DMA_IF3_DERR" },
+	{ .fc_id = 184, .cpu_id = 70, .valid = 1, .name = "GIC500" },
+	{ .fc_id = 185, .cpu_id = 71, .valid = 1, .name = "HBM_0_SERR" },
+	{ .fc_id = 186, .cpu_id = 71, .valid = 1, .name = "HBM_1_SERR" },
+	{ .fc_id = 187, .cpu_id = 71, .valid = 1, .name = "HBM_2_SERR" },
+	{ .fc_id = 188, .cpu_id = 71, .valid = 1, .name = "HBM_3_SERR" },
+	{ .fc_id = 189, .cpu_id = 72, .valid = 1, .name = "HBM_0_DERR" },
+	{ .fc_id = 190, .cpu_id = 72, .valid = 1, .name = "HBM_1_DERR" },
+	{ .fc_id = 191, .cpu_id = 72, .valid = 1, .name = "HBM_2_DERR" },
+	{ .fc_id = 192, .cpu_id = 72, .valid = 1, .name = "HBM_3_DERR" },
+	{ .fc_id = 193, .cpu_id = 73, .valid = 1, .name = "MMU_SERR" },
+	{ .fc_id = 194, .cpu_id = 74, .valid = 1, .name = "MMU_DERR" },
+	{ .fc_id = 195, .cpu_id = 75, .valid = 0, .name = "" },
+	{ .fc_id = 196, .cpu_id = 76, .valid = 0, .name = "" },
+	{ .fc_id = 197, .cpu_id = 77, .valid = 0, .name = "" },
+	{ .fc_id = 198, .cpu_id = 78, .valid = 0, .name = "" },
+	{ .fc_id = 199, .cpu_id = 79, .valid = 0, .name = "" },
+	{ .fc_id = 200, .cpu_id = 80, .valid = 1, .name = "PCIE_DEC" },
+	{ .fc_id = 201, .cpu_id = 81, .valid = 1, .name = "TPC0_DEC" },
+	{ .fc_id = 202, .cpu_id = 82, .valid = 0, .name = "" },
+	{ .fc_id = 203, .cpu_id = 83, .valid = 1, .name = "TPC1_DEC" },
+	{ .fc_id = 204, .cpu_id = 84, .valid = 0, .name = "" },
+	{ .fc_id = 205, .cpu_id = 85, .valid = 1, .name = "TPC2_DEC" },
+	{ .fc_id = 206, .cpu_id = 86, .valid = 0, .name = "" },
+	{ .fc_id = 207, .cpu_id = 87, .valid = 1, .name = "TPC3_DEC" },
+	{ .fc_id = 208, .cpu_id = 88, .valid = 0, .name = "" },
+	{ .fc_id = 209, .cpu_id = 89, .valid = 1, .name = "TPC4_DEC" },
+	{ .fc_id = 210, .cpu_id = 90, .valid = 0, .name = "" },
+	{ .fc_id = 211, .cpu_id = 91, .valid = 1, .name = "TPC5_DEC" },
+	{ .fc_id = 212, .cpu_id = 92, .valid = 0, .name = "" },
+	{ .fc_id = 213, .cpu_id = 93, .valid = 1, .name = "TPC6_DEC" },
+	{ .fc_id = 214, .cpu_id = 94, .valid = 0, .name = "" },
+	{ .fc_id = 215, .cpu_id = 95, .valid = 1, .name = "TPC7_DEC" },
+	{ .fc_id = 216, .cpu_id = 96, .valid = 0, .name = "" },
+	{ .fc_id = 217, .cpu_id = 97, .valid = 1, .name = "AXI_ECC" },
+	{ .fc_id = 218, .cpu_id = 98, .valid = 1, .name = "L2_RAM_ECC" },
+	{ .fc_id = 219, .cpu_id = 99, .valid = 1, .name = "MME0_WBC_RSP" },
+	{ .fc_id = 220, .cpu_id = 100, .valid = 1, .name = "MME0_SBAB0_RSP" },
+	{ .fc_id = 221, .cpu_id = 101, .valid = 0, .name = "" },
+	{ .fc_id = 222, .cpu_id = 102, .valid = 0, .name = "" },
+	{ .fc_id = 223, .cpu_id = 103, .valid = 0, .name = "" },
+	{ .fc_id = 224, .cpu_id = 104, .valid = 1, .name = "MME1_WBC_RSP" },
+	{ .fc_id = 225, .cpu_id = 105, .valid = 1, .name = "MME1_SBAB0_RSP" },
+	{ .fc_id = 226, .cpu_id = 106, .valid = 0, .name = "" },
+	{ .fc_id = 227, .cpu_id = 107, .valid = 0, .name = "" },
+	{ .fc_id = 228, .cpu_id = 108, .valid = 0, .name = "" },
+	{ .fc_id = 229, .cpu_id = 109, .valid = 1, .name = "MME2_WBC_RSP" },
+	{ .fc_id = 230, .cpu_id = 110, .valid = 1, .name = "MME2_SBAB0_RSP" },
+	{ .fc_id = 231, .cpu_id = 111, .valid = 0, .name = "" },
+	{ .fc_id = 232, .cpu_id = 112, .valid = 0, .name = "" },
+	{ .fc_id = 233, .cpu_id = 113, .valid = 0, .name = "" },
+	{ .fc_id = 234, .cpu_id = 114, .valid = 1, .name = "MME3_WBC_RSP" },
+	{ .fc_id = 235, .cpu_id = 115, .valid = 1, .name = "MME3_SBAB0_RSP" },
+	{ .fc_id = 236, .cpu_id = 116, .valid = 0, .name = "" },
+	{ .fc_id = 237, .cpu_id = 117, .valid = 0, .name = "" },
+	{ .fc_id = 238, .cpu_id = 118, .valid = 0, .name = "" },
+	{ .fc_id = 239, .cpu_id = 119, .valid = 1, .name = "PLL0" },
+	{ .fc_id = 240, .cpu_id = 119, .valid = 1, .name = "PLL1" },
+	{ .fc_id = 241, .cpu_id = 119, .valid = 1, .name = "PLL2" },
+	{ .fc_id = 242, .cpu_id = 119, .valid = 1, .name = "PLL3" },
+	{ .fc_id = 243, .cpu_id = 119, .valid = 1, .name = "PLL4" },
+	{ .fc_id = 244, .cpu_id = 119, .valid = 1, .name = "PLL5" },
+	{ .fc_id = 245, .cpu_id = 119, .valid = 1, .name = "PLL6" },
+	{ .fc_id = 246, .cpu_id = 119, .valid = 1, .name = "PLL7" },
+	{ .fc_id = 247, .cpu_id = 119, .valid = 1, .name = "PLL8" },
+	{ .fc_id = 248, .cpu_id = 119, .valid = 1, .name = "PLL9" },
+	{ .fc_id = 249, .cpu_id = 119, .valid = 1, .name = "PLL10" },
+	{ .fc_id = 250, .cpu_id = 119, .valid = 1, .name = "PLL11" },
+	{ .fc_id = 251, .cpu_id = 119, .valid = 1, .name = "PLL12" },
+	{ .fc_id = 252, .cpu_id = 119, .valid = 1, .name = "PLL13" },
+	{ .fc_id = 253, .cpu_id = 119, .valid = 1, .name = "PLL14" },
+	{ .fc_id = 254, .cpu_id = 119, .valid = 1, .name = "PLL15" },
+	{ .fc_id = 255, .cpu_id = 119, .valid = 1, .name = "PLL16" },
+	{ .fc_id = 256, .cpu_id = 119, .valid = 1, .name = "PLL17" },
+	{ .fc_id = 257, .cpu_id = 120, .valid = 1,
+		.name = "CPU_AXI_SPLITTER" },
+	{ .fc_id = 258, .cpu_id = 121, .valid = 0, .name = "" },
+	{ .fc_id = 259, .cpu_id = 122, .valid = 0, .name = "" },
+	{ .fc_id = 260, .cpu_id = 123, .valid = 0, .name = "" },
+	{ .fc_id = 261, .cpu_id = 124, .valid = 0, .name = "" },
+	{ .fc_id = 262, .cpu_id = 125, .valid = 1, .name = "PSOC_AXI_DEC" },
+	{ .fc_id = 263, .cpu_id = 126, .valid = 1, .name = "PSOC_PRSTN_FALL" },
+	{ .fc_id = 264, .cpu_id = 127, .valid = 1, .name = "NIC_SEI_0" },
+	{ .fc_id = 265, .cpu_id = 127, .valid = 1, .name = "NIC_SEI_1" },
+	{ .fc_id = 266, .cpu_id = 127, .valid = 1, .name = "NIC_SEI_2" },
+	{ .fc_id = 267, .cpu_id = 127, .valid = 1, .name = "NIC_SEI_3" },
+	{ .fc_id = 268, .cpu_id = 127, .valid = 1, .name = "NIC_SEI_4" },
+	{ .fc_id = 269, .cpu_id = 128, .valid = 0, .name = "" },
+	{ .fc_id = 270, .cpu_id = 128, .valid = 0, .name = "" },
+	{ .fc_id = 271, .cpu_id = 128, .valid = 0, .name = "" },
+	{ .fc_id = 272, .cpu_id = 128, .valid = 0, .name = "" },
+	{ .fc_id = 273, .cpu_id = 128, .valid = 0, .name = "" },
+	{ .fc_id = 274, .cpu_id = 128, .valid = 0, .name = "" },
+	{ .fc_id = 275, .cpu_id = 128, .valid = 0, .name = "" },
+	{ .fc_id = 276, .cpu_id = 128, .valid = 0, .name = "" },
+	{ .fc_id = 277, .cpu_id = 129, .valid = 1, .name = "DMA_IF_SEI_0" },
+	{ .fc_id = 278, .cpu_id = 129, .valid = 1, .name = "DMA_IF_SEI_1" },
+	{ .fc_id = 279, .cpu_id = 129, .valid = 1, .name = "DMA_IF_SEI_2" },
+	{ .fc_id = 280, .cpu_id = 129, .valid = 1, .name = "DMA_IF_SEI_3" },
+	{ .fc_id = 281, .cpu_id = 130, .valid = 0, .name = "" },
+	{ .fc_id = 282, .cpu_id = 131, .valid = 0, .name = "" },
+	{ .fc_id = 283, .cpu_id = 132, .valid = 0, .name = "" },
+	{ .fc_id = 284, .cpu_id = 133, .valid = 0, .name = "" },
+	{ .fc_id = 285, .cpu_id = 134, .valid = 0, .name = "" },
+	{ .fc_id = 286, .cpu_id = 135, .valid = 0, .name = "" },
+	{ .fc_id = 287, .cpu_id = 136, .valid = 0, .name = "" },
+	{ .fc_id = 288, .cpu_id = 137, .valid = 0, .name = "" },
+	{ .fc_id = 289, .cpu_id = 138, .valid = 0, .name = "" },
+	{ .fc_id = 290, .cpu_id = 139, .valid = 1, .name = "PCIE_FLR" },
+	{ .fc_id = 291, .cpu_id = 140, .valid = 0, .name = "" },
+	{ .fc_id = 292, .cpu_id = 141, .valid = 0, .name = "" },
+	{ .fc_id = 293, .cpu_id = 142, .valid = 0, .name = "" },
+	{ .fc_id = 294, .cpu_id = 143, .valid = 0, .name = "" },
+	{ .fc_id = 295, .cpu_id = 144, .valid = 0, .name = "" },
+	{ .fc_id = 296, .cpu_id = 145, .valid = 0, .name = "" },
+	{ .fc_id = 297, .cpu_id = 146, .valid = 0, .name = "" },
+	{ .fc_id = 298, .cpu_id = 147, .valid = 0, .name = "" },
+	{ .fc_id = 299, .cpu_id = 148, .valid = 0, .name = "" },
+	{ .fc_id = 300, .cpu_id = 149, .valid = 1, .name = "TPC0_BMON_SPMU" },
+	{ .fc_id = 301, .cpu_id = 150, .valid = 1, .name = "TPC0_KRN_ERR" },
+	{ .fc_id = 302, .cpu_id = 151, .valid = 0, .name = "" },
+	{ .fc_id = 303, .cpu_id = 152, .valid = 0, .name = "" },
+	{ .fc_id = 304, .cpu_id = 153, .valid = 0, .name = "" },
+	{ .fc_id = 305, .cpu_id = 154, .valid = 0, .name = "" },
+	{ .fc_id = 306, .cpu_id = 155, .valid = 1, .name = "TPC1_BMON_SPMU" },
+	{ .fc_id = 307, .cpu_id = 156, .valid = 1, .name = "TPC1_KRN_ERR" },
+	{ .fc_id = 308, .cpu_id = 157, .valid = 0, .name = "" },
+	{ .fc_id = 309, .cpu_id = 158, .valid = 0, .name = "" },
+	{ .fc_id = 310, .cpu_id = 159, .valid = 0, .name = "" },
+	{ .fc_id = 311, .cpu_id = 160, .valid = 0, .name = "" },
+	{ .fc_id = 312, .cpu_id = 161, .valid = 1, .name = "TPC2_BMON_SPMU" },
+	{ .fc_id = 313, .cpu_id = 162, .valid = 1, .name = "TPC2_KRN_ERR" },
+	{ .fc_id = 314, .cpu_id = 163, .valid = 0, .name = "" },
+	{ .fc_id = 315, .cpu_id = 164, .valid = 0, .name = "" },
+	{ .fc_id = 316, .cpu_id = 165, .valid = 0, .name = "" },
+	{ .fc_id = 317, .cpu_id = 166, .valid = 0, .name = "" },
+	{ .fc_id = 318, .cpu_id = 167, .valid = 1, .name = "TPC3_BMON_SPMU" },
+	{ .fc_id = 319, .cpu_id = 168, .valid = 1, .name = "TPC3_KRN_ERR" },
+	{ .fc_id = 320, .cpu_id = 169, .valid = 0, .name = "" },
+	{ .fc_id = 321, .cpu_id = 170, .valid = 0, .name = "" },
+	{ .fc_id = 322, .cpu_id = 171, .valid = 0, .name = "" },
+	{ .fc_id = 323, .cpu_id = 172, .valid = 0, .name = "" },
+	{ .fc_id = 324, .cpu_id = 173, .valid = 1, .name = "TPC4_BMON_SPMU" },
+	{ .fc_id = 325, .cpu_id = 174, .valid = 1, .name = "TPC4_KRN_ERR" },
+	{ .fc_id = 326, .cpu_id = 175, .valid = 0, .name = "" },
+	{ .fc_id = 327, .cpu_id = 176, .valid = 0, .name = "" },
+	{ .fc_id = 328, .cpu_id = 177, .valid = 0, .name = "" },
+	{ .fc_id = 329, .cpu_id = 178, .valid = 0, .name = "" },
+	{ .fc_id = 330, .cpu_id = 179, .valid = 1, .name = "TPC5_BMON_SPMU" },
+	{ .fc_id = 331, .cpu_id = 180, .valid = 1, .name = "TPC5_KRN_ERR" },
+	{ .fc_id = 332, .cpu_id = 181, .valid = 0, .name = "" },
+	{ .fc_id = 333, .cpu_id = 182, .valid = 0, .name = "" },
+	{ .fc_id = 334, .cpu_id = 183, .valid = 0, .name = "" },
+	{ .fc_id = 335, .cpu_id = 184, .valid = 0, .name = "" },
+	{ .fc_id = 336, .cpu_id = 185, .valid = 1, .name = "TPC6_BMON_SPMU" },
+	{ .fc_id = 337, .cpu_id = 186, .valid = 1, .name = "TPC6_KRN_ERR" },
+	{ .fc_id = 338, .cpu_id = 187, .valid = 0, .name = "" },
+	{ .fc_id = 339, .cpu_id = 188, .valid = 0, .name = "" },
+	{ .fc_id = 340, .cpu_id = 189, .valid = 0, .name = "" },
+	{ .fc_id = 341, .cpu_id = 190, .valid = 0, .name = "" },
+	{ .fc_id = 342, .cpu_id = 191, .valid = 1, .name = "TPC7_BMON_SPMU" },
+	{ .fc_id = 343, .cpu_id = 192, .valid = 1, .name = "TPC7_KRN_ERR" },
+	{ .fc_id = 344, .cpu_id = 193, .valid = 0, .name = "" },
+	{ .fc_id = 345, .cpu_id = 194, .valid = 0, .name = "" },
+	{ .fc_id = 346, .cpu_id = 195, .valid = 0, .name = "" },
+	{ .fc_id = 347, .cpu_id = 196, .valid = 0, .name = "" },
+	{ .fc_id = 348, .cpu_id = 197, .valid = 0, .name = "" },
+	{ .fc_id = 349, .cpu_id = 198, .valid = 0, .name = "" },
+	{ .fc_id = 350, .cpu_id = 199, .valid = 0, .name = "" },
+	{ .fc_id = 351, .cpu_id = 200, .valid = 0, .name = "" },
+	{ .fc_id = 352, .cpu_id = 201, .valid = 0, .name = "" },
+	{ .fc_id = 353, .cpu_id = 202, .valid = 0, .name = "" },
+	{ .fc_id = 354, .cpu_id = 203, .valid = 0, .name = "" },
+	{ .fc_id = 355, .cpu_id = 204, .valid = 0, .name = "" },
+	{ .fc_id = 356, .cpu_id = 205, .valid = 0, .name = "" },
+	{ .fc_id = 357, .cpu_id = 206, .valid = 0, .name = "" },
+	{ .fc_id = 358, .cpu_id = 207, .valid = 0, .name = "" },
+	{ .fc_id = 359, .cpu_id = 208, .valid = 0, .name = "" },
+	{ .fc_id = 360, .cpu_id = 209, .valid = 0, .name = "" },
+	{ .fc_id = 361, .cpu_id = 210, .valid = 0, .name = "" },
+	{ .fc_id = 362, .cpu_id = 211, .valid = 0, .name = "" },
+	{ .fc_id = 363, .cpu_id = 212, .valid = 0, .name = "" },
+	{ .fc_id = 364, .cpu_id = 213, .valid = 0, .name = "" },
+	{ .fc_id = 365, .cpu_id = 214, .valid = 0, .name = "" },
+	{ .fc_id = 366, .cpu_id = 215, .valid = 0, .name = "" },
+	{ .fc_id = 367, .cpu_id = 216, .valid = 0, .name = "" },
+	{ .fc_id = 368, .cpu_id = 217, .valid = 0, .name = "" },
+	{ .fc_id = 369, .cpu_id = 218, .valid = 0, .name = "" },
+	{ .fc_id = 370, .cpu_id = 219, .valid = 0, .name = "" },
+	{ .fc_id = 371, .cpu_id = 220, .valid = 0, .name = "" },
+	{ .fc_id = 372, .cpu_id = 221, .valid = 0, .name = "" },
+	{ .fc_id = 373, .cpu_id = 222, .valid = 0, .name = "" },
+	{ .fc_id = 374, .cpu_id = 223, .valid = 0, .name = "" },
+	{ .fc_id = 375, .cpu_id = 224, .valid = 0, .name = "" },
+	{ .fc_id = 376, .cpu_id = 225, .valid = 0, .name = "" },
+	{ .fc_id = 377, .cpu_id = 226, .valid = 0, .name = "" },
+	{ .fc_id = 378, .cpu_id = 227, .valid = 0, .name = "" },
+	{ .fc_id = 379, .cpu_id = 228, .valid = 0, .name = "" },
+	{ .fc_id = 380, .cpu_id = 229, .valid = 1, .name = "MMU_PAGE_FAULT" },
+	{ .fc_id = 381, .cpu_id = 230, .valid = 1, .name = "MMU_WR_PERM" },
+	{ .fc_id = 382, .cpu_id = 231, .valid = 0, .name = "" },
+	{ .fc_id = 383, .cpu_id = 232, .valid = 1, .name = "DMA_BM_CH0" },
+	{ .fc_id = 384, .cpu_id = 233, .valid = 1, .name = "DMA_BM_CH1" },
+	{ .fc_id = 385, .cpu_id = 234, .valid = 1, .name = "DMA_BM_CH2" },
+	{ .fc_id = 386, .cpu_id = 235, .valid = 1, .name = "DMA_BM_CH3" },
+	{ .fc_id = 387, .cpu_id = 236, .valid = 1, .name = "DMA_BM_CH4" },
+	{ .fc_id = 388, .cpu_id = 237, .valid = 1, .name = "DMA_BM_CH5" },
+	{ .fc_id = 389, .cpu_id = 238, .valid = 1, .name = "DMA_BM_CH6" },
+	{ .fc_id = 390, .cpu_id = 239, .valid = 1, .name = "DMA_BM_CH7" },
+	{ .fc_id = 391, .cpu_id = 240, .valid = 0, .name = "" },
+	{ .fc_id = 392, .cpu_id = 241, .valid = 0, .name = "" },
+	{ .fc_id = 393, .cpu_id = 242, .valid = 0, .name = "" },
+	{ .fc_id = 394, .cpu_id = 243, .valid = 0, .name = "" },
+	{ .fc_id = 395, .cpu_id = 244, .valid = 1, .name = "HBM0_SPI_0" },
+	{ .fc_id = 396, .cpu_id = 245, .valid = 1, .name = "HBM0_SPI_1" },
+	{ .fc_id = 397, .cpu_id = 246, .valid = 0, .name = "" },
+	{ .fc_id = 398, .cpu_id = 247, .valid = 0, .name = "" },
+	{ .fc_id = 399, .cpu_id = 248, .valid = 1, .name = "HBM1_SPI_0" },
+	{ .fc_id = 400, .cpu_id = 249, .valid = 1, .name = "HBM1_SPI_1" },
+	{ .fc_id = 401, .cpu_id = 250, .valid = 0, .name = "" },
+	{ .fc_id = 402, .cpu_id = 251, .valid = 0, .name = "" },
+	{ .fc_id = 403, .cpu_id = 252, .valid = 1, .name = "HBM2_SPI_0" },
+	{ .fc_id = 404, .cpu_id = 253, .valid = 1, .name = "HBM2_SPI_1" },
+	{ .fc_id = 405, .cpu_id = 254, .valid = 0, .name = "" },
+	{ .fc_id = 406, .cpu_id = 255, .valid = 0, .name = "" },
+	{ .fc_id = 407, .cpu_id = 256, .valid = 1, .name = "HBM3_SPI_0" },
+	{ .fc_id = 408, .cpu_id = 257, .valid = 1, .name = "HBM3_SPI_1" },
+	{ .fc_id = 409, .cpu_id = 258, .valid = 0, .name = "" },
+	{ .fc_id = 410, .cpu_id = 259, .valid = 0, .name = "" },
+	{ .fc_id = 411, .cpu_id = 260, .valid = 0, .name = "" },
+	{ .fc_id = 412, .cpu_id = 261, .valid = 0, .name = "" },
+	{ .fc_id = 413, .cpu_id = 262, .valid = 0, .name = "" },
+	{ .fc_id = 414, .cpu_id = 263, .valid = 0, .name = "" },
+	{ .fc_id = 415, .cpu_id = 264, .valid = 0, .name = "" },
+	{ .fc_id = 416, .cpu_id = 265, .valid = 0, .name = "" },
+	{ .fc_id = 417, .cpu_id = 266, .valid = 0, .name = "" },
+	{ .fc_id = 418, .cpu_id = 267, .valid = 0, .name = "" },
+	{ .fc_id = 419, .cpu_id = 268, .valid = 0, .name = "" },
+	{ .fc_id = 420, .cpu_id = 269, .valid = 0, .name = "" },
+	{ .fc_id = 421, .cpu_id = 270, .valid = 1, .name = "PSOC_GPIO_U16_0" },
+	{ .fc_id = 422, .cpu_id = 271, .valid = 0, .name = "" },
+	{ .fc_id = 423, .cpu_id = 272, .valid = 0, .name = "" },
+	{ .fc_id = 424, .cpu_id = 273, .valid = 0, .name = "" },
+	{ .fc_id = 425, .cpu_id = 274, .valid = 0, .name = "" },
+	{ .fc_id = 426, .cpu_id = 275, .valid = 0, .name = "" },
+	{ .fc_id = 427, .cpu_id = 276, .valid = 0, .name = "" },
+	{ .fc_id = 428, .cpu_id = 277, .valid = 0, .name = "" },
+	{ .fc_id = 429, .cpu_id = 278, .valid = 0, .name = "" },
+	{ .fc_id = 430, .cpu_id = 279, .valid = 0, .name = "" },
+	{ .fc_id = 431, .cpu_id = 280, .valid = 0, .name = "" },
+	{ .fc_id = 432, .cpu_id = 281, .valid = 0, .name = "" },
+	{ .fc_id = 433, .cpu_id = 282, .valid = 0, .name = "" },
+	{ .fc_id = 434, .cpu_id = 283, .valid = 0, .name = "" },
+	{ .fc_id = 435, .cpu_id = 284, .valid = 0, .name = "" },
+	{ .fc_id = 436, .cpu_id = 285, .valid = 0, .name = "" },
+	{ .fc_id = 437, .cpu_id = 286, .valid = 0, .name = "" },
+	{ .fc_id = 438, .cpu_id = 287, .valid = 0, .name = "" },
+	{ .fc_id = 439, .cpu_id = 288, .valid = 0, .name = "" },
+	{ .fc_id = 440, .cpu_id = 289, .valid = 0, .name = "" },
+	{ .fc_id = 441, .cpu_id = 290, .valid = 0, .name = "" },
+	{ .fc_id = 442, .cpu_id = 291, .valid = 0, .name = "" },
+	{ .fc_id = 443, .cpu_id = 292, .valid = 0, .name = "" },
+	{ .fc_id = 444, .cpu_id = 293, .valid = 0, .name = "" },
+	{ .fc_id = 445, .cpu_id = 294, .valid = 0, .name = "" },
+	{ .fc_id = 446, .cpu_id = 295, .valid = 0, .name = "" },
+	{ .fc_id = 447, .cpu_id = 296, .valid = 0, .name = "" },
+	{ .fc_id = 448, .cpu_id = 297, .valid = 0, .name = "" },
+	{ .fc_id = 449, .cpu_id = 298, .valid = 0, .name = "" },
+	{ .fc_id = 450, .cpu_id = 299, .valid = 0, .name = "" },
+	{ .fc_id = 451, .cpu_id = 300, .valid = 0, .name = "" },
+	{ .fc_id = 452, .cpu_id = 301, .valid = 0, .name = "" },
+	{ .fc_id = 453, .cpu_id = 302, .valid = 0, .name = "" },
+	{ .fc_id = 454, .cpu_id = 303, .valid = 0, .name = "" },
+	{ .fc_id = 455, .cpu_id = 304, .valid = 0, .name = "" },
+	{ .fc_id = 456, .cpu_id = 305, .valid = 0, .name = "" },
+	{ .fc_id = 457, .cpu_id = 306, .valid = 0, .name = "" },
+	{ .fc_id = 458, .cpu_id = 307, .valid = 0, .name = "" },
+	{ .fc_id = 459, .cpu_id = 308, .valid = 0, .name = "" },
+	{ .fc_id = 460, .cpu_id = 309, .valid = 0, .name = "" },
+	{ .fc_id = 461, .cpu_id = 310, .valid = 0, .name = "" },
+	{ .fc_id = 462, .cpu_id = 311, .valid = 0, .name = "" },
+	{ .fc_id = 463, .cpu_id = 312, .valid = 0, .name = "" },
+	{ .fc_id = 464, .cpu_id = 313, .valid = 0, .name = "" },
+	{ .fc_id = 465, .cpu_id = 314, .valid = 0, .name = "" },
+	{ .fc_id = 466, .cpu_id = 315, .valid = 0, .name = "" },
+	{ .fc_id = 467, .cpu_id = 316, .valid = 0, .name = "" },
+	{ .fc_id = 468, .cpu_id = 317, .valid = 0, .name = "" },
+	{ .fc_id = 469, .cpu_id = 318, .valid = 0, .name = "" },
+	{ .fc_id = 470, .cpu_id = 319, .valid = 0, .name = "" },
+	{ .fc_id = 471, .cpu_id = 320, .valid = 0, .name = "" },
+	{ .fc_id = 472, .cpu_id = 321, .valid = 0, .name = "" },
+	{ .fc_id = 473, .cpu_id = 322, .valid = 0, .name = "" },
+	{ .fc_id = 474, .cpu_id = 323, .valid = 0, .name = "" },
+	{ .fc_id = 475, .cpu_id = 324, .valid = 0, .name = "" },
+	{ .fc_id = 476, .cpu_id = 325, .valid = 0, .name = "" },
+	{ .fc_id = 477, .cpu_id = 326, .valid = 0, .name = "" },
+	{ .fc_id = 478, .cpu_id = 327, .valid = 0, .name = "" },
+	{ .fc_id = 479, .cpu_id = 328, .valid = 0, .name = "" },
+	{ .fc_id = 480, .cpu_id = 329, .valid = 0, .name = "" },
+	{ .fc_id = 481, .cpu_id = 330, .valid = 0, .name = "" },
+	{ .fc_id = 482, .cpu_id = 331, .valid = 0, .name = "" },
+	{ .fc_id = 483, .cpu_id = 332, .valid = 1,
+		.name = "NIC0_CS_DBG_DERR" },
+	{ .fc_id = 484, .cpu_id = 333, .valid = 0, .name = "" },
+	{ .fc_id = 485, .cpu_id = 334, .valid = 0, .name = "" },
+	{ .fc_id = 486, .cpu_id = 335, .valid = 0, .name = "" },
+	{ .fc_id = 487, .cpu_id = 336, .valid = 1,
+		.name = "NIC1_CS_DBG_DERR" },
+	{ .fc_id = 488, .cpu_id = 337, .valid = 0, .name = "" },
+	{ .fc_id = 489, .cpu_id = 338, .valid = 0, .name = "" },
+	{ .fc_id = 490, .cpu_id = 339, .valid = 0, .name = "" },
+	{ .fc_id = 491, .cpu_id = 340, .valid = 1,
+		.name = "NIC2_CS_DBG_DERR" },
+	{ .fc_id = 492, .cpu_id = 341, .valid = 0, .name = "" },
+	{ .fc_id = 493, .cpu_id = 342, .valid = 0, .name = "" },
+	{ .fc_id = 494, .cpu_id = 343, .valid = 0, .name = "" },
+	{ .fc_id = 495, .cpu_id = 344, .valid = 1,
+		.name = "NIC3_CS_DBG_DERR" },
+	{ .fc_id = 496, .cpu_id = 345, .valid = 0, .name = "" },
+	{ .fc_id = 497, .cpu_id = 346, .valid = 0, .name = "" },
+	{ .fc_id = 498, .cpu_id = 347, .valid = 0, .name = "" },
+	{ .fc_id = 499, .cpu_id = 348, .valid = 1,
+		.name = "NIC4_CS_DBG_DERR" },
+	{ .fc_id = 500, .cpu_id = 349, .valid = 0, .name = "" },
+	{ .fc_id = 501, .cpu_id = 350, .valid = 0, .name = "" },
+	{ .fc_id = 502, .cpu_id = 351, .valid = 0, .name = "" },
+	{ .fc_id = 503, .cpu_id = 352, .valid = 0, .name = "" },
+	{ .fc_id = 504, .cpu_id = 353, .valid = 0, .name = "" },
+	{ .fc_id = 505, .cpu_id = 354, .valid = 0, .name = "" },
+	{ .fc_id = 506, .cpu_id = 355, .valid = 0, .name = "" },
+	{ .fc_id = 507, .cpu_id = 356, .valid = 0, .name = "" },
+	{ .fc_id = 508, .cpu_id = 357, .valid = 0, .name = "" },
+	{ .fc_id = 509, .cpu_id = 358, .valid = 0, .name = "" },
+	{ .fc_id = 510, .cpu_id = 359, .valid = 0, .name = "" },
+	{ .fc_id = 511, .cpu_id = 360, .valid = 0, .name = "" },
+	{ .fc_id = 512, .cpu_id = 361, .valid = 0, .name = "" },
+	{ .fc_id = 513, .cpu_id = 362, .valid = 0, .name = "" },
+	{ .fc_id = 514, .cpu_id = 363, .valid = 0, .name = "" },
+	{ .fc_id = 515, .cpu_id = 364, .valid = 0, .name = "" },
+	{ .fc_id = 516, .cpu_id = 365, .valid = 0, .name = "" },
+	{ .fc_id = 517, .cpu_id = 366, .valid = 0, .name = "" },
+	{ .fc_id = 518, .cpu_id = 367, .valid = 0, .name = "" },
+	{ .fc_id = 519, .cpu_id = 368, .valid = 0, .name = "" },
+	{ .fc_id = 520, .cpu_id = 369, .valid = 0, .name = "" },
+	{ .fc_id = 521, .cpu_id = 370, .valid = 0, .name = "" },
+	{ .fc_id = 522, .cpu_id = 371, .valid = 0, .name = "" },
+	{ .fc_id = 523, .cpu_id = 372, .valid = 0, .name = "" },
+	{ .fc_id = 524, .cpu_id = 373, .valid = 0, .name = "" },
+	{ .fc_id = 525, .cpu_id = 374, .valid = 0, .name = "" },
+	{ .fc_id = 526, .cpu_id = 375, .valid = 0, .name = "" },
+	{ .fc_id = 527, .cpu_id = 376, .valid = 0, .name = "" },
+	{ .fc_id = 528, .cpu_id = 377, .valid = 0, .name = "" },
+	{ .fc_id = 529, .cpu_id = 378, .valid = 0, .name = "" },
+	{ .fc_id = 530, .cpu_id = 379, .valid = 0, .name = "" },
+	{ .fc_id = 531, .cpu_id = 380, .valid = 0, .name = "" },
+	{ .fc_id = 532, .cpu_id = 381, .valid = 0, .name = "" },
+	{ .fc_id = 533, .cpu_id = 382, .valid = 0, .name = "" },
+	{ .fc_id = 534, .cpu_id = 383, .valid = 0, .name = "" },
+	{ .fc_id = 535, .cpu_id = 384, .valid = 0, .name = "" },
+	{ .fc_id = 536, .cpu_id = 385, .valid = 0, .name = "" },
+	{ .fc_id = 537, .cpu_id = 386, .valid = 0, .name = "" },
+	{ .fc_id = 538, .cpu_id = 387, .valid = 0, .name = "" },
+	{ .fc_id = 539, .cpu_id = 388, .valid = 0, .name = "" },
+	{ .fc_id = 540, .cpu_id = 389, .valid = 0, .name = "" },
+	{ .fc_id = 541, .cpu_id = 390, .valid = 0, .name = "" },
+	{ .fc_id = 542, .cpu_id = 391, .valid = 0, .name = "" },
+	{ .fc_id = 543, .cpu_id = 392, .valid = 0, .name = "" },
+	{ .fc_id = 544, .cpu_id = 393, .valid = 0, .name = "" },
+	{ .fc_id = 545, .cpu_id = 394, .valid = 0, .name = "" },
+	{ .fc_id = 546, .cpu_id = 395, .valid = 0, .name = "" },
+	{ .fc_id = 547, .cpu_id = 396, .valid = 0, .name = "" },
+	{ .fc_id = 548, .cpu_id = 397, .valid = 1, .name = "RAZWI_OR_ADC" },
+	{ .fc_id = 549, .cpu_id = 398, .valid = 0, .name = "" },
+	{ .fc_id = 550, .cpu_id = 399, .valid = 0, .name = "" },
+	{ .fc_id = 551, .cpu_id = 400, .valid = 0, .name = "" },
+	{ .fc_id = 552, .cpu_id = 401, .valid = 0, .name = "" },
+	{ .fc_id = 553, .cpu_id = 402, .valid = 0, .name = "" },
+	{ .fc_id = 554, .cpu_id = 403, .valid = 0, .name = "" },
+	{ .fc_id = 555, .cpu_id = 404, .valid = 0, .name = "" },
+	{ .fc_id = 556, .cpu_id = 405, .valid = 0, .name = "" },
+	{ .fc_id = 557, .cpu_id = 406, .valid = 0, .name = "" },
+	{ .fc_id = 558, .cpu_id = 407, .valid = 0, .name = "" },
+	{ .fc_id = 559, .cpu_id = 408, .valid = 0, .name = "" },
+	{ .fc_id = 560, .cpu_id = 409, .valid = 0, .name = "" },
+	{ .fc_id = 561, .cpu_id = 410, .valid = 0, .name = "" },
+	{ .fc_id = 562, .cpu_id = 411, .valid = 0, .name = "" },
+	{ .fc_id = 563, .cpu_id = 412, .valid = 0, .name = "" },
+	{ .fc_id = 564, .cpu_id = 413, .valid = 0, .name = "" },
+	{ .fc_id = 565, .cpu_id = 414, .valid = 0, .name = "" },
+	{ .fc_id = 566, .cpu_id = 415, .valid = 0, .name = "" },
+	{ .fc_id = 567, .cpu_id = 416, .valid = 0, .name = "" },
+	{ .fc_id = 568, .cpu_id = 417, .valid = 0, .name = "" },
+	{ .fc_id = 569, .cpu_id = 418, .valid = 0, .name = "" },
+	{ .fc_id = 570, .cpu_id = 419, .valid = 0, .name = "" },
+	{ .fc_id = 571, .cpu_id = 420, .valid = 0, .name = "" },
+	{ .fc_id = 572, .cpu_id = 421, .valid = 1, .name = "TPC0_QM" },
+	{ .fc_id = 573, .cpu_id = 422, .valid = 1, .name = "TPC1_QM" },
+	{ .fc_id = 574, .cpu_id = 423, .valid = 1, .name = "TPC2_QM" },
+	{ .fc_id = 575, .cpu_id = 424, .valid = 1, .name = "TPC3_QM" },
+	{ .fc_id = 576, .cpu_id = 425, .valid = 1, .name = "TPC4_QM" },
+	{ .fc_id = 577, .cpu_id = 426, .valid = 1, .name = "TPC5_QM" },
+	{ .fc_id = 578, .cpu_id = 427, .valid = 1, .name = "TPC6_QM" },
+	{ .fc_id = 579, .cpu_id = 428, .valid = 1, .name = "TPC7_QM" },
+	{ .fc_id = 580, .cpu_id = 429, .valid = 0, .name = "" },
+	{ .fc_id = 581, .cpu_id = 430, .valid = 1, .name = "MME0_QM" },
+	{ .fc_id = 582, .cpu_id = 431, .valid = 1, .name = "MME2_QM" },
+	{ .fc_id = 583, .cpu_id = 432, .valid = 1, .name = "DMA0_QM" },
+	{ .fc_id = 584, .cpu_id = 433, .valid = 1, .name = "DMA1_QM" },
+	{ .fc_id = 585, .cpu_id = 434, .valid = 1, .name = "DMA2_QM" },
+	{ .fc_id = 586, .cpu_id = 435, .valid = 1, .name = "DMA3_QM" },
+	{ .fc_id = 587, .cpu_id = 436, .valid = 1, .name = "DMA4_QM" },
+	{ .fc_id = 588, .cpu_id = 437, .valid = 1, .name = "DMA5_QM" },
+	{ .fc_id = 589, .cpu_id = 438, .valid = 1, .name = "DMA6_QM" },
+	{ .fc_id = 590, .cpu_id = 439, .valid = 1, .name = "DMA7_QM" },
+	{ .fc_id = 591, .cpu_id = 440, .valid = 0, .name = "" },
+	{ .fc_id = 592, .cpu_id = 441, .valid = 0, .name = "" },
+	{ .fc_id = 593, .cpu_id = 442, .valid = 0, .name = "" },
+	{ .fc_id = 594, .cpu_id = 443, .valid = 1, .name = "NIC0_QM0" },
+	{ .fc_id = 595, .cpu_id = 444, .valid = 1, .name = "NIC0_QM1" },
+	{ .fc_id = 596, .cpu_id = 445, .valid = 1, .name = "NIC1_QM0" },
+	{ .fc_id = 597, .cpu_id = 446, .valid = 1, .name = "NIC1_QM1" },
+	{ .fc_id = 598, .cpu_id = 447, .valid = 1, .name = "NIC2_QM0" },
+	{ .fc_id = 599, .cpu_id = 448, .valid = 1, .name = "NIC2_QM1" },
+	{ .fc_id = 600, .cpu_id = 449, .valid = 1, .name = "NIC3_QM0" },
+	{ .fc_id = 601, .cpu_id = 450, .valid = 1, .name = "NIC3_QM1" },
+	{ .fc_id = 602, .cpu_id = 451, .valid = 1, .name = "NIC4_QM0" },
+	{ .fc_id = 603, .cpu_id = 452, .valid = 1, .name = "NIC4_QM1" },
+	{ .fc_id = 604, .cpu_id = 453, .valid = 1, .name = "DMA0_CORE" },
+	{ .fc_id = 605, .cpu_id = 454, .valid = 1, .name = "DMA1_CORE" },
+	{ .fc_id = 606, .cpu_id = 455, .valid = 1, .name = "DMA2_CORE" },
+	{ .fc_id = 607, .cpu_id = 456, .valid = 1, .name = "DMA3_CORE" },
+	{ .fc_id = 608, .cpu_id = 457, .valid = 1, .name = "DMA4_CORE" },
+	{ .fc_id = 609, .cpu_id = 458, .valid = 1, .name = "DMA5_CORE" },
+	{ .fc_id = 610, .cpu_id = 459, .valid = 1, .name = "DMA6_CORE" },
+	{ .fc_id = 611, .cpu_id = 460, .valid = 1, .name = "DMA7_CORE" },
+	{ .fc_id = 612, .cpu_id = 461, .valid = 1, .name = "NIC0_QP0" },
+	{ .fc_id = 613, .cpu_id = 462, .valid = 1, .name = "NIC0_QP1" },
+	{ .fc_id = 614, .cpu_id = 463, .valid = 1, .name = "NIC1_QP0" },
+	{ .fc_id = 615, .cpu_id = 464, .valid = 1, .name = "NIC1_QP1" },
+	{ .fc_id = 616, .cpu_id = 465, .valid = 1, .name = "NIC2_QP0" },
+	{ .fc_id = 617, .cpu_id = 466, .valid = 1, .name = "NIC2_QP1" },
+	{ .fc_id = 618, .cpu_id = 467, .valid = 1, .name = "NIC3_QP0" },
+	{ .fc_id = 619, .cpu_id = 468, .valid = 1, .name = "NIC3_QP1" },
+	{ .fc_id = 620, .cpu_id = 469, .valid = 1, .name = "NIC4_QP0" },
+	{ .fc_id = 621, .cpu_id = 470, .valid = 1, .name = "NIC4_QP1" },
+	{ .fc_id = 622, .cpu_id = 471, .valid = 0, .name = "" },
+	{ .fc_id = 623, .cpu_id = 472, .valid = 0, .name = "" },
+	{ .fc_id = 624, .cpu_id = 473, .valid = 0, .name = "" },
+	{ .fc_id = 625, .cpu_id = 474, .valid = 0, .name = "" },
+	{ .fc_id = 626, .cpu_id = 475, .valid = 0, .name = "" },
+	{ .fc_id = 627, .cpu_id = 476, .valid = 0, .name = "" },
+	{ .fc_id = 628, .cpu_id = 477, .valid = 0, .name = "" },
+	{ .fc_id = 629, .cpu_id = 478, .valid = 0, .name = "" },
+	{ .fc_id = 630, .cpu_id = 479, .valid = 0, .name = "" },
+	{ .fc_id = 631, .cpu_id = 480, .valid = 0, .name = "" },
+	{ .fc_id = 632, .cpu_id = 481, .valid = 0, .name = "" },
+	{ .fc_id = 633, .cpu_id = 482, .valid = 0, .name = "" },
+	{ .fc_id = 634, .cpu_id = 483, .valid = 0, .name = "" },
+	{ .fc_id = 635, .cpu_id = 484, .valid = 1, .name = "PI_UPDATE" },
+	{ .fc_id = 636, .cpu_id = 485, .valid = 1, .name = "HALT_MACHINE" },
+	{ .fc_id = 637, .cpu_id = 486, .valid = 1, .name = "INTS_REGISTER" },
+	{ .fc_id = 638, .cpu_id = 487, .valid = 1, .name = "SOFT_RESET" },
+	{ .fc_id = 639, .cpu_id = 488, .valid = 0, .name = "" },
+	{ .fc_id = 640, .cpu_id = 489, .valid = 0, .name = "" },
+	{ .fc_id = 641, .cpu_id = 490, .valid = 0, .name = "" },
+	{ .fc_id = 642, .cpu_id = 491, .valid = 0, .name = "" },
+	{ .fc_id = 643, .cpu_id = 492, .valid = 0, .name = "" },
+	{ .fc_id = 644, .cpu_id = 493, .valid = 0, .name = "" },
+	{ .fc_id = 645, .cpu_id = 494, .valid = 1, .name = "FW_ALIVE_S" },
+	{ .fc_id = 646, .cpu_id = 495, .valid = 1, .name = "DEV_RESET_REQ" },
+	{ .fc_id = 647, .cpu_id = 496, .valid = 1,
+		.name = "PKT_QUEUE_OUT_SYNC" },
+	{ .fc_id = 648, .cpu_id = 497, .valid = 1,
+		.name = "STATUS_NIC0_ENG0" },
+	{ .fc_id = 649, .cpu_id = 498, .valid = 1,
+		.name = "STATUS_NIC0_ENG1" },
+	{ .fc_id = 650, .cpu_id = 499, .valid = 1,
+		.name = "STATUS_NIC1_ENG0" },
+	{ .fc_id = 651, .cpu_id = 500, .valid = 1,
+		.name = "STATUS_NIC1_ENG1" },
+	{ .fc_id = 652, .cpu_id = 501, .valid = 1,
+		.name = "STATUS_NIC2_ENG0" },
+	{ .fc_id = 653, .cpu_id = 502, .valid = 1,
+		.name = "STATUS_NIC2_ENG1" },
+	{ .fc_id = 654, .cpu_id = 503, .valid = 1,
+		.name = "STATUS_NIC3_ENG0" },
+	{ .fc_id = 655, .cpu_id = 504, .valid = 1,
+		.name = "STATUS_NIC3_ENG1" },
+	{ .fc_id = 656, .cpu_id = 505, .valid = 1,
+		.name = "STATUS_NIC4_ENG0" },
+	{ .fc_id = 657, .cpu_id = 506, .valid = 1,
+		.name = "STATUS_NIC4_ENG1" },
+	{ .fc_id = 658, .cpu_id = 507, .valid = 1, .name = "FIX_POWER_ENV_S" },
+	{ .fc_id = 659, .cpu_id = 508, .valid = 1, .name = "FIX_POWER_ENV_E" },
+	{ .fc_id = 660, .cpu_id = 509, .valid = 1,
+		.name = "FIX_THERMAL_ENV_S" },
+	{ .fc_id = 661, .cpu_id = 510, .valid = 1,
+		.name = "FIX_THERMAL_ENV_E" },
+	{ .fc_id = 662, .cpu_id = 511, .valid = 1, .name = "RAZWI_OR_ADC_SW" },
+};
+
+#endif /* __GAUDI_ASYNC_IDS_MAP_EVENTS_EXT_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/gaudi_coresight.h b/drivers/accel/habanalabs/include/gaudi/gaudi_coresight.h
new file mode 100644
index 000000000000..c45cc7f4d4d7
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/gaudi_coresight.h
@@ -0,0 +1,367 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+#ifndef GAUDI_CORESIGHT_H
+#define GAUDI_CORESIGHT_H
+
+enum gaudi_debug_stm_regs_index {
+	GAUDI_STM_FIRST = 0,
+	GAUDI_STM_MME0_ACC = GAUDI_STM_FIRST,
+	GAUDI_STM_MME0_SBAB,
+	GAUDI_STM_MME0_CTRL,
+	GAUDI_STM_MME1_ACC,
+	GAUDI_STM_MME1_SBAB,
+	GAUDI_STM_MME1_CTRL,
+	GAUDI_STM_MME2_ACC,
+	GAUDI_STM_MME2_SBAB,
+	GAUDI_STM_MME2_CTRL,
+	GAUDI_STM_MME3_ACC,
+	GAUDI_STM_MME3_SBAB,
+	GAUDI_STM_MME3_CTRL,
+	GAUDI_STM_DMA_IF_W_S,
+	GAUDI_STM_DMA_IF_E_S,
+	GAUDI_STM_DMA_IF_W_N,
+	GAUDI_STM_DMA_IF_E_N,
+	GAUDI_STM_CPU,
+	GAUDI_STM_DMA_CH_0_CS,
+	GAUDI_STM_DMA_CH_1_CS,
+	GAUDI_STM_DMA_CH_2_CS,
+	GAUDI_STM_DMA_CH_3_CS,
+	GAUDI_STM_DMA_CH_4_CS,
+	GAUDI_STM_DMA_CH_5_CS,
+	GAUDI_STM_DMA_CH_6_CS,
+	GAUDI_STM_DMA_CH_7_CS,
+	GAUDI_STM_PCIE,
+	GAUDI_STM_MMU_CS,
+	GAUDI_STM_PSOC,
+	GAUDI_STM_NIC0_0,
+	GAUDI_STM_NIC0_1,
+	GAUDI_STM_NIC1_0,
+	GAUDI_STM_NIC1_1,
+	GAUDI_STM_NIC2_0,
+	GAUDI_STM_NIC2_1,
+	GAUDI_STM_NIC3_0,
+	GAUDI_STM_NIC3_1,
+	GAUDI_STM_NIC4_0,
+	GAUDI_STM_NIC4_1,
+	GAUDI_STM_TPC0_EML,
+	GAUDI_STM_TPC1_EML,
+	GAUDI_STM_TPC2_EML,
+	GAUDI_STM_TPC3_EML,
+	GAUDI_STM_TPC4_EML,
+	GAUDI_STM_TPC5_EML,
+	GAUDI_STM_TPC6_EML,
+	GAUDI_STM_TPC7_EML,
+	GAUDI_STM_LAST = GAUDI_STM_TPC7_EML
+};
+
+enum gaudi_debug_etf_regs_index {
+	GAUDI_ETF_FIRST = 0,
+	GAUDI_ETF_MME0_ACC = GAUDI_ETF_FIRST,
+	GAUDI_ETF_MME0_SBAB,
+	GAUDI_ETF_MME0_CTRL,
+	GAUDI_ETF_MME1_ACC,
+	GAUDI_ETF_MME1_SBAB,
+	GAUDI_ETF_MME1_CTRL,
+	GAUDI_ETF_MME2_ACC,
+	GAUDI_ETF_MME2_SBAB,
+	GAUDI_ETF_MME2_CTRL,
+	GAUDI_ETF_MME3_ACC,
+	GAUDI_ETF_MME3_SBAB,
+	GAUDI_ETF_MME3_CTRL,
+	GAUDI_ETF_DMA_IF_W_S,
+	GAUDI_ETF_DMA_IF_E_S,
+	GAUDI_ETF_DMA_IF_W_N,
+	GAUDI_ETF_DMA_IF_E_N,
+	GAUDI_ETF_CPU_0,
+	GAUDI_ETF_CPU_1,
+	GAUDI_ETF_CPU_TRACE,
+	GAUDI_ETF_DMA_CH_0_CS,
+	GAUDI_ETF_DMA_CH_1_CS,
+	GAUDI_ETF_DMA_CH_2_CS,
+	GAUDI_ETF_DMA_CH_3_CS,
+	GAUDI_ETF_DMA_CH_4_CS,
+	GAUDI_ETF_DMA_CH_5_CS,
+	GAUDI_ETF_DMA_CH_6_CS,
+	GAUDI_ETF_DMA_CH_7_CS,
+	GAUDI_ETF_PCIE,
+	GAUDI_ETF_MMU_CS,
+	GAUDI_ETF_PSOC,
+	GAUDI_ETF_NIC0_0,
+	GAUDI_ETF_NIC0_1,
+	GAUDI_ETF_NIC1_0,
+	GAUDI_ETF_NIC1_1,
+	GAUDI_ETF_NIC2_0,
+	GAUDI_ETF_NIC2_1,
+	GAUDI_ETF_NIC3_0,
+	GAUDI_ETF_NIC3_1,
+	GAUDI_ETF_NIC4_0,
+	GAUDI_ETF_NIC4_1,
+	GAUDI_ETF_TPC0_EML,
+	GAUDI_ETF_TPC1_EML,
+	GAUDI_ETF_TPC2_EML,
+	GAUDI_ETF_TPC3_EML,
+	GAUDI_ETF_TPC4_EML,
+	GAUDI_ETF_TPC5_EML,
+	GAUDI_ETF_TPC6_EML,
+	GAUDI_ETF_TPC7_EML,
+	GAUDI_ETF_LAST = GAUDI_ETF_TPC7_EML
+};
+
+enum gaudi_debug_funnel_regs_index {
+	GAUDI_FUNNEL_FIRST = 0,
+	GAUDI_FUNNEL_MME0_ACC = GAUDI_FUNNEL_FIRST,
+	GAUDI_FUNNEL_MME1_ACC,
+	GAUDI_FUNNEL_MME2_ACC,
+	GAUDI_FUNNEL_MME3_ACC,
+	GAUDI_FUNNEL_SRAM_Y0_X0,
+	GAUDI_FUNNEL_SRAM_Y0_X1,
+	GAUDI_FUNNEL_SRAM_Y0_X2,
+	GAUDI_FUNNEL_SRAM_Y0_X3,
+	GAUDI_FUNNEL_SRAM_Y0_X4,
+	GAUDI_FUNNEL_SRAM_Y0_X5,
+	GAUDI_FUNNEL_SRAM_Y0_X6,
+	GAUDI_FUNNEL_SRAM_Y0_X7,
+	GAUDI_FUNNEL_SRAM_Y1_X0,
+	GAUDI_FUNNEL_SRAM_Y1_X1,
+	GAUDI_FUNNEL_SRAM_Y1_X2,
+	GAUDI_FUNNEL_SRAM_Y1_X3,
+	GAUDI_FUNNEL_SRAM_Y1_X4,
+	GAUDI_FUNNEL_SRAM_Y1_X5,
+	GAUDI_FUNNEL_SRAM_Y1_X6,
+	GAUDI_FUNNEL_SRAM_Y1_X7,
+	GAUDI_FUNNEL_SRAM_Y2_X0,
+	GAUDI_FUNNEL_SRAM_Y2_X1,
+	GAUDI_FUNNEL_SRAM_Y2_X2,
+	GAUDI_FUNNEL_SRAM_Y2_X3,
+	GAUDI_FUNNEL_SRAM_Y2_X4,
+	GAUDI_FUNNEL_SRAM_Y2_X5,
+	GAUDI_FUNNEL_SRAM_Y2_X6,
+	GAUDI_FUNNEL_SRAM_Y2_X7,
+	GAUDI_FUNNEL_SRAM_Y3_X0,
+	GAUDI_FUNNEL_SRAM_Y3_X1,
+	GAUDI_FUNNEL_SRAM_Y3_X2,
+	GAUDI_FUNNEL_SRAM_Y3_X4,
+	GAUDI_FUNNEL_SRAM_Y3_X3,
+	GAUDI_FUNNEL_SRAM_Y3_X5,
+	GAUDI_FUNNEL_SRAM_Y3_X6,
+	GAUDI_FUNNEL_SRAM_Y3_X7,
+	GAUDI_FUNNEL_SIF_0,
+	GAUDI_FUNNEL_SIF_1,
+	GAUDI_FUNNEL_SIF_2,
+	GAUDI_FUNNEL_SIF_3,
+	GAUDI_FUNNEL_SIF_4,
+	GAUDI_FUNNEL_SIF_5,
+	GAUDI_FUNNEL_SIF_6,
+	GAUDI_FUNNEL_SIF_7,
+	GAUDI_FUNNEL_NIF_0,
+	GAUDI_FUNNEL_NIF_1,
+	GAUDI_FUNNEL_NIF_2,
+	GAUDI_FUNNEL_NIF_3,
+	GAUDI_FUNNEL_NIF_4,
+	GAUDI_FUNNEL_NIF_5,
+	GAUDI_FUNNEL_NIF_6,
+	GAUDI_FUNNEL_NIF_7,
+	GAUDI_FUNNEL_DMA_IF_W_S,
+	GAUDI_FUNNEL_DMA_IF_E_S,
+	GAUDI_FUNNEL_DMA_IF_W_N,
+	GAUDI_FUNNEL_DMA_IF_E_N,
+	GAUDI_FUNNEL_CPU,
+	GAUDI_FUNNEL_NIC_TPC_W_S,
+	GAUDI_FUNNEL_NIC_TPC_E_S,
+	GAUDI_FUNNEL_NIC_TPC_W_N,
+	GAUDI_FUNNEL_NIC_TPC_E_N,
+	GAUDI_FUNNEL_PCIE,
+	GAUDI_FUNNEL_PSOC,
+	GAUDI_FUNNEL_NIC0,
+	GAUDI_FUNNEL_NIC1,
+	GAUDI_FUNNEL_NIC2,
+	GAUDI_FUNNEL_NIC3,
+	GAUDI_FUNNEL_NIC4,
+	GAUDI_FUNNEL_TPC0_EML,
+	GAUDI_FUNNEL_TPC1_EML,
+	GAUDI_FUNNEL_TPC2_EML,
+	GAUDI_FUNNEL_TPC3_EML,
+	GAUDI_FUNNEL_TPC4_EML,
+	GAUDI_FUNNEL_TPC5_EML,
+	GAUDI_FUNNEL_TPC6_EML,
+	GAUDI_FUNNEL_TPC7_EML,
+	GAUDI_FUNNEL_LAST = GAUDI_FUNNEL_TPC7_EML
+};
+
+enum gaudi_debug_bmon_regs_index {
+	GAUDI_BMON_FIRST = 0,
+	GAUDI_BMON_MME0_ACC_0 = GAUDI_BMON_FIRST,
+	GAUDI_BMON_MME0_SBAB_0,
+	GAUDI_BMON_MME0_SBAB_1,
+	GAUDI_BMON_MME0_CTRL_0,
+	GAUDI_BMON_MME0_CTRL_1,
+	GAUDI_BMON_MME1_ACC_0,
+	GAUDI_BMON_MME1_SBAB_0,
+	GAUDI_BMON_MME1_SBAB_1,
+	GAUDI_BMON_MME1_CTRL_0,
+	GAUDI_BMON_MME1_CTRL_1,
+	GAUDI_BMON_MME2_ACC_0,
+	GAUDI_BMON_MME2_SBAB_0,
+	GAUDI_BMON_MME2_SBAB_1,
+	GAUDI_BMON_MME2_CTRL_0,
+	GAUDI_BMON_MME2_CTRL_1,
+	GAUDI_BMON_MME3_ACC_0,
+	GAUDI_BMON_MME3_SBAB_0,
+	GAUDI_BMON_MME3_SBAB_1,
+	GAUDI_BMON_MME3_CTRL_0,
+	GAUDI_BMON_MME3_CTRL_1,
+	GAUDI_BMON_DMA_IF_W_S_SOB_WR,
+	GAUDI_BMON_DMA_IF_W_S_0_WR,
+	GAUDI_BMON_DMA_IF_W_S_0_RD,
+	GAUDI_BMON_DMA_IF_W_S_1_WR,
+	GAUDI_BMON_DMA_IF_W_S_1_RD,
+	GAUDI_BMON_DMA_IF_E_S_SOB_WR,
+	GAUDI_BMON_DMA_IF_E_S_0_WR,
+	GAUDI_BMON_DMA_IF_E_S_0_RD,
+	GAUDI_BMON_DMA_IF_E_S_1_WR,
+	GAUDI_BMON_DMA_IF_E_S_1_RD,
+	GAUDI_BMON_DMA_IF_W_N_SOB_WR,
+	GAUDI_BMON_DMA_IF_W_N_HBM0_WR,
+	GAUDI_BMON_DMA_IF_W_N_HBM0_RD,
+	GAUDI_BMON_DMA_IF_W_N_HBM1_WR,
+	GAUDI_BMON_DMA_IF_W_N_HBM1_RD,
+	GAUDI_BMON_DMA_IF_E_N_SOB_WR,
+	GAUDI_BMON_DMA_IF_E_N_HBM0_WR,
+	GAUDI_BMON_DMA_IF_E_N_HBM0_RD,
+	GAUDI_BMON_DMA_IF_E_N_HBM1_WR,
+	GAUDI_BMON_DMA_IF_E_N_HBM1_RD,
+	GAUDI_BMON_CPU_WR,
+	GAUDI_BMON_CPU_RD,
+	GAUDI_BMON_DMA_CH_0_0,
+	GAUDI_BMON_DMA_CH_0_1,
+	GAUDI_BMON_DMA_CH_1_0,
+	GAUDI_BMON_DMA_CH_1_1,
+	GAUDI_BMON_DMA_CH_2_0,
+	GAUDI_BMON_DMA_CH_2_1,
+	GAUDI_BMON_DMA_CH_3_0,
+	GAUDI_BMON_DMA_CH_3_1,
+	GAUDI_BMON_DMA_CH_4_0,
+	GAUDI_BMON_DMA_CH_4_1,
+	GAUDI_BMON_DMA_CH_5_0,
+	GAUDI_BMON_DMA_CH_5_1,
+	GAUDI_BMON_DMA_CH_6_0,
+	GAUDI_BMON_DMA_CH_6_1,
+	GAUDI_BMON_DMA_CH_7_0,
+	GAUDI_BMON_DMA_CH_7_1,
+	GAUDI_BMON_PCIE_MSTR_WR,
+	GAUDI_BMON_PCIE_MSTR_RD,
+	GAUDI_BMON_PCIE_SLV_WR,
+	GAUDI_BMON_PCIE_SLV_RD,
+	GAUDI_BMON_MMU_0,
+	GAUDI_BMON_MMU_1,
+	GAUDI_BMON_NIC0_0,
+	GAUDI_BMON_NIC0_1,
+	GAUDI_BMON_NIC0_2,
+	GAUDI_BMON_NIC0_3,
+	GAUDI_BMON_NIC0_4,
+	GAUDI_BMON_NIC1_0,
+	GAUDI_BMON_NIC1_1,
+	GAUDI_BMON_NIC1_2,
+	GAUDI_BMON_NIC1_3,
+	GAUDI_BMON_NIC1_4,
+	GAUDI_BMON_NIC2_0,
+	GAUDI_BMON_NIC2_1,
+	GAUDI_BMON_NIC2_2,
+	GAUDI_BMON_NIC2_3,
+	GAUDI_BMON_NIC2_4,
+	GAUDI_BMON_NIC3_0,
+	GAUDI_BMON_NIC3_1,
+	GAUDI_BMON_NIC3_2,
+	GAUDI_BMON_NIC3_3,
+	GAUDI_BMON_NIC3_4,
+	GAUDI_BMON_NIC4_0,
+	GAUDI_BMON_NIC4_1,
+	GAUDI_BMON_NIC4_2,
+	GAUDI_BMON_NIC4_3,
+	GAUDI_BMON_NIC4_4,
+	GAUDI_BMON_TPC0_EML_0,
+	GAUDI_BMON_TPC0_EML_1,
+	GAUDI_BMON_TPC0_EML_2,
+	GAUDI_BMON_TPC0_EML_3,
+	GAUDI_BMON_TPC1_EML_0,
+	GAUDI_BMON_TPC1_EML_1,
+	GAUDI_BMON_TPC1_EML_2,
+	GAUDI_BMON_TPC1_EML_3,
+	GAUDI_BMON_TPC2_EML_0,
+	GAUDI_BMON_TPC2_EML_1,
+	GAUDI_BMON_TPC2_EML_2,
+	GAUDI_BMON_TPC2_EML_3,
+	GAUDI_BMON_TPC3_EML_0,
+	GAUDI_BMON_TPC3_EML_1,
+	GAUDI_BMON_TPC3_EML_2,
+	GAUDI_BMON_TPC3_EML_3,
+	GAUDI_BMON_TPC4_EML_0,
+	GAUDI_BMON_TPC4_EML_1,
+	GAUDI_BMON_TPC4_EML_2,
+	GAUDI_BMON_TPC4_EML_3,
+	GAUDI_BMON_TPC5_EML_0,
+	GAUDI_BMON_TPC5_EML_1,
+	GAUDI_BMON_TPC5_EML_2,
+	GAUDI_BMON_TPC5_EML_3,
+	GAUDI_BMON_TPC6_EML_0,
+	GAUDI_BMON_TPC6_EML_1,
+	GAUDI_BMON_TPC6_EML_2,
+	GAUDI_BMON_TPC6_EML_3,
+	GAUDI_BMON_TPC7_EML_0,
+	GAUDI_BMON_TPC7_EML_1,
+	GAUDI_BMON_TPC7_EML_2,
+	GAUDI_BMON_TPC7_EML_3,
+	GAUDI_BMON_LAST = GAUDI_BMON_TPC7_EML_3
+};
+
+enum gaudi_debug_spmu_regs_index {
+	GAUDI_SPMU_FIRST = 0,
+	GAUDI_SPMU_MME0_ACC = GAUDI_SPMU_FIRST,
+	GAUDI_SPMU_MME0_SBAB,
+	GAUDI_SPMU_MME0_CTRL,
+	GAUDI_SPMU_MME1_ACC,
+	GAUDI_SPMU_MME1_SBAB,
+	GAUDI_SPMU_MME1_CTRL,
+	GAUDI_SPMU_MME2_MME2_ACC,
+	GAUDI_SPMU_MME2_SBAB,
+	GAUDI_SPMU_MME2_CTRL,
+	GAUDI_SPMU_MME3_ACC,
+	GAUDI_SPMU_MME3_SBAB,
+	GAUDI_SPMU_MME3_CTRL,
+	GAUDI_SPMU_DMA_CH_0_CS,
+	GAUDI_SPMU_DMA_CH_1_CS,
+	GAUDI_SPMU_DMA_CH_2_CS,
+	GAUDI_SPMU_DMA_CH_3_CS,
+	GAUDI_SPMU_DMA_CH_4_CS,
+	GAUDI_SPMU_DMA_CH_5_CS,
+	GAUDI_SPMU_DMA_CH_6_CS,
+	GAUDI_SPMU_DMA_CH_7_CS,
+	GAUDI_SPMU_PCIE,
+	GAUDI_SPMU_MMU_CS,
+	GAUDI_SPMU_NIC0_0,
+	GAUDI_SPMU_NIC0_1,
+	GAUDI_SPMU_NIC1_0,
+	GAUDI_SPMU_NIC1_1,
+	GAUDI_SPMU_NIC2_0,
+	GAUDI_SPMU_NIC2_1,
+	GAUDI_SPMU_NIC3_0,
+	GAUDI_SPMU_NIC3_1,
+	GAUDI_SPMU_NIC4_0,
+	GAUDI_SPMU_NIC4_1,
+	GAUDI_SPMU_TPC0_EML,
+	GAUDI_SPMU_TPC1_EML,
+	GAUDI_SPMU_TPC2_EML,
+	GAUDI_SPMU_TPC3_EML,
+	GAUDI_SPMU_TPC4_EML,
+	GAUDI_SPMU_TPC5_EML,
+	GAUDI_SPMU_TPC6_EML,
+	GAUDI_SPMU_TPC7_EML,
+	GAUDI_SPMU_LAST = GAUDI_SPMU_TPC7_EML
+};
+
+#endif /* GAUDI_CORESIGHT_H */
diff --git a/drivers/accel/habanalabs/include/gaudi/gaudi_fw_if.h b/drivers/accel/habanalabs/include/gaudi/gaudi_fw_if.h
new file mode 100644
index 000000000000..a2547f306750
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/gaudi_fw_if.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2019-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+#ifndef GAUDI_FW_IF_H
+#define GAUDI_FW_IF_H
+
+#define GAUDI_EVENT_QUEUE_MSI_IDX	8
+#define GAUDI_NIC_PORT1_MSI_IDX		10
+#define GAUDI_NIC_PORT3_MSI_IDX		12
+#define GAUDI_NIC_PORT5_MSI_IDX		14
+#define GAUDI_NIC_PORT7_MSI_IDX		16
+#define GAUDI_NIC_PORT9_MSI_IDX		18
+
+#define UBOOT_FW_OFFSET			0x100000	/* 1MB in SRAM */
+#define LINUX_FW_OFFSET			0x800000	/* 8MB in HBM */
+
+/* HBM thermal delta in [Deg] added to composite (CTemp) */
+#define HBM_TEMP_ADJUST_COEFF		6
+
+enum gaudi_nic_axi_error {
+	RXB,
+	RXE,
+	TXS,
+	TXE,
+	QPC_RESP,
+	NON_AXI_ERR,
+	TMR,
+};
+
+/*
+ * struct eq_nic_sei_event - describes an AXI error cause.
+ * @axi_error_cause: one of the events defined in enum gaudi_nic_axi_error.
+ * @id: can be either 0 or 1, to further describe unit with interrupt cause
+ *      (i.e. TXE0 or TXE1).
+ * @pad[6]: padding structure to 64bit.
+ */
+struct eq_nic_sei_event {
+	__u8 axi_error_cause;
+	__u8 id;
+	__u8 pad[6];
+};
+
+struct gaudi_cold_rst_data {
+	union {
+		struct {
+			u32 spsram_init_done : 1;
+			u32 reserved : 31;
+		};
+		__le32 data;
+	};
+};
+
+#define GAUDI_PLL_FREQ_LOW		200000000 /* 200 MHz */
+
+#endif /* GAUDI_FW_IF_H */
diff --git a/drivers/accel/habanalabs/include/gaudi/gaudi_masks.h b/drivers/accel/habanalabs/include/gaudi/gaudi_masks.h
new file mode 100644
index 000000000000..880c57b26c63
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/gaudi_masks.h
@@ -0,0 +1,470 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+#ifndef GAUDI_MASKS_H_
+#define GAUDI_MASKS_H_
+
+#include "asic_reg/gaudi_regs.h"
+
+/* Useful masks for bits in various registers */
+#define PCI_DMA_QMAN_ENABLE		(\
+	(FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
+	(FIELD_PREP(DMA0_QM_GLBL_CFG0_CQF_EN_MASK, 0xF)) | \
+	(FIELD_PREP(DMA0_QM_GLBL_CFG0_CP_EN_MASK, 0xF)))
+
+#define QMAN_EXTERNAL_MAKE_TRUSTED	(\
+	(FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \
+	(FIELD_PREP(DMA0_QM_GLBL_PROT_CQF_MASK, 0xF)) | \
+	(FIELD_PREP(DMA0_QM_GLBL_PROT_CP_MASK, 0xF)) | \
+	(FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1)))
+
+#define QMAN_INTERNAL_MAKE_TRUSTED	(\
+	(FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \
+	(FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1)))
+
+#define HBM_DMA_QMAN_ENABLE		(\
+	(FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
+	(FIELD_PREP(DMA0_QM_GLBL_CFG0_CQF_EN_MASK, 0x1F)) | \
+	(FIELD_PREP(DMA0_QM_GLBL_CFG0_CP_EN_MASK, 0x1F)))
+
+#define QMAN_MME_ENABLE		(\
+	(FIELD_PREP(MME0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
+	(FIELD_PREP(MME0_QM_GLBL_CFG0_CQF_EN_MASK, 0x1F)) | \
+	(FIELD_PREP(MME0_QM_GLBL_CFG0_CP_EN_MASK, 0x1F)))
+
+#define QMAN_TPC_ENABLE		(\
+	(FIELD_PREP(TPC0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
+	(FIELD_PREP(TPC0_QM_GLBL_CFG0_CQF_EN_MASK, 0x1F)) | \
+	(FIELD_PREP(TPC0_QM_GLBL_CFG0_CP_EN_MASK, 0x1F)))
+
+#define NIC_QMAN_ENABLE		(\
+	(FIELD_PREP(NIC0_QM0_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
+	(FIELD_PREP(NIC0_QM0_GLBL_CFG0_CQF_EN_MASK, 0xF)) | \
+	(FIELD_PREP(NIC0_QM0_GLBL_CFG0_CP_EN_MASK, 0xF)))
+
+#define QMAN_UPPER_CP_CGM_PWR_GATE_EN	(\
+	(FIELD_PREP(DMA0_QM_CGM_CFG_IDLE_TH_MASK, 0x20)) | \
+	(FIELD_PREP(DMA0_QM_CGM_CFG_G2F_TH_MASK, 0xA)) | \
+	(FIELD_PREP(DMA0_QM_CGM_CFG_CP_IDLE_MASK_MASK, 0x10)) | \
+	(FIELD_PREP(DMA0_QM_CGM_CFG_EN_MASK, 0x1)))
+
+#define QMAN_COMMON_CP_CGM_PWR_GATE_EN	(\
+	(FIELD_PREP(DMA0_QM_CGM_CFG_IDLE_TH_MASK, 0x20)) | \
+	(FIELD_PREP(DMA0_QM_CGM_CFG_G2F_TH_MASK, 0xA)) | \
+	(FIELD_PREP(DMA0_QM_CGM_CFG_CP_IDLE_MASK_MASK, 0xF)) | \
+	(FIELD_PREP(DMA0_QM_CGM_CFG_EN_MASK, 0x1)))
+
+#define PCI_DMA_QMAN_GLBL_ERR_CFG_MSG_EN_MASK	(\
+	(FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \
+	(FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0xF)) | \
+	(FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0xF)))
+
+#define PCI_DMA_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK	(\
+	(FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \
+	(FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0xF)) | \
+	(FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0xF)) | \
+	(FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK, 0x1)))
+
+#define HBM_DMA_QMAN_GLBL_ERR_CFG_MSG_EN_MASK	(\
+	(FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \
+	(FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0x1F)) | \
+	(FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0x1F)))
+
+#define HBM_DMA_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK	(\
+	(FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \
+	(FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0x1F)) | \
+	(FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0x1F)) | \
+	(FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK, 0x1)))
+
+#define TPC_QMAN_GLBL_ERR_CFG_MSG_EN_MASK	(\
+	(FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \
+	(FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0x1F)) | \
+	(FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0x1F)))
+
+#define TPC_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK	(\
+	(FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \
+	(FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0x1F)) | \
+	(FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0x1F)) | \
+	(FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK, 0x1)))
+
+#define MME_QMAN_GLBL_ERR_CFG_MSG_EN_MASK	(\
+	(FIELD_PREP(MME0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \
+	(FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0x1F)) | \
+	(FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0x1F)))
+
+#define MME_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK	(\
+	(FIELD_PREP(MME0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \
+	(FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0x1F)) | \
+	(FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0x1F)) | \
+	(FIELD_PREP(MME0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK, 0x1)))
+
+#define NIC_QMAN_GLBL_ERR_CFG_MSG_EN_MASK	(\
+	(FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \
+	(FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0xF)) | \
+	(FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0xF)))
+
+#define NIC_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK	(\
+	(FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \
+	(FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0xF)) | \
+	(FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0xF)) | \
+	(FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK, 0x1)))
+
+#define QMAN_CGM1_PWR_GATE_EN	(FIELD_PREP(DMA0_QM_CGM_CFG1_MASK_TH_MASK, 0xA))
+
+/* RESET registers configuration */
+#define CFG_RST_L_PSOC_MASK		BIT_MASK(0)
+#define CFG_RST_L_PCIE_MASK		BIT_MASK(1)
+#define CFG_RST_L_PCIE_IF_MASK		BIT_MASK(2)
+#define CFG_RST_L_HBM_S_PLL_MASK	BIT_MASK(3)
+#define CFG_RST_L_TPC_S_PLL_MASK	BIT_MASK(4)
+#define CFG_RST_L_MME_S_PLL_MASK	BIT_MASK(5)
+#define CFG_RST_L_CPU_PLL_MASK		BIT_MASK(6)
+#define CFG_RST_L_PCIE_PLL_MASK		BIT_MASK(7)
+#define CFG_RST_L_NIC_S_PLL_MASK	BIT_MASK(8)
+#define CFG_RST_L_HBM_N_PLL_MASK	BIT_MASK(9)
+#define CFG_RST_L_TPC_N_PLL_MASK	BIT_MASK(10)
+#define CFG_RST_L_MME_N_PLL_MASK	BIT_MASK(11)
+#define CFG_RST_L_NIC_N_PLL_MASK	BIT_MASK(12)
+#define CFG_RST_L_DMA_W_PLL_MASK	BIT_MASK(13)
+#define CFG_RST_L_SIF_W_PLL_MASK	BIT_MASK(14)
+#define CFG_RST_L_MESH_W_PLL_MASK	BIT_MASK(15)
+#define CFG_RST_L_SRAM_W_PLL_MASK	BIT_MASK(16)
+#define CFG_RST_L_DMA_E_PLL_MASK	BIT_MASK(17)
+#define CFG_RST_L_SIF_E_PLL_MASK	BIT_MASK(18)
+#define CFG_RST_L_MESH_E_PLL_MASK	BIT_MASK(19)
+#define CFG_RST_L_SRAM_E_PLL_MASK	BIT_MASK(20)
+
+#define CFG_RST_L_IF_1_MASK		BIT_MASK(21)
+#define CFG_RST_L_IF_0_MASK		BIT_MASK(22)
+#define CFG_RST_L_IF_2_MASK		BIT_MASK(23)
+#define CFG_RST_L_IF_3_MASK		BIT_MASK(24)
+#define CFG_RST_L_IF_MASK		GENMASK(24, 21)
+
+#define CFG_RST_L_TPC_0_MASK		BIT_MASK(25)
+#define CFG_RST_L_TPC_1_MASK		BIT_MASK(26)
+#define CFG_RST_L_TPC_2_MASK		BIT_MASK(27)
+#define CFG_RST_L_TPC_3_MASK		BIT_MASK(28)
+#define CFG_RST_L_TPC_4_MASK		BIT_MASK(29)
+#define CFG_RST_L_TPC_5_MASK		BIT_MASK(30)
+#define CFG_RST_L_TPC_6_MASK		BIT_MASK(31)
+#define CFG_RST_L_TPC_MASK		GENMASK(31, 25)
+
+#define CFG_RST_H_TPC_7_MASK		BIT_MASK(0)
+
+#define CFG_RST_H_MME_0_MASK		BIT_MASK(1)
+#define CFG_RST_H_MME_1_MASK		BIT_MASK(2)
+#define CFG_RST_H_MME_2_MASK		BIT_MASK(3)
+#define CFG_RST_H_MME_3_MASK		BIT_MASK(4)
+#define CFG_RST_H_MME_MASK		GENMASK(4, 1)
+
+#define CFG_RST_H_HBM_0_MASK		BIT_MASK(5)
+#define CFG_RST_H_HBM_1_MASK		BIT_MASK(6)
+#define CFG_RST_H_HBM_2_MASK		BIT_MASK(7)
+#define CFG_RST_H_HBM_3_MASK		BIT_MASK(8)
+#define CFG_RST_H_HBM_MASK		GENMASK(8, 5)
+
+#define CFG_RST_H_NIC_0_MASK		BIT_MASK(9)
+#define CFG_RST_H_NIC_1_MASK		BIT_MASK(10)
+#define CFG_RST_H_NIC_2_MASK		BIT_MASK(11)
+#define CFG_RST_H_NIC_3_MASK		BIT_MASK(12)
+#define CFG_RST_H_NIC_4_MASK		BIT_MASK(13)
+#define CFG_RST_H_NIC_MASK		GENMASK(13, 9)
+
+#define CFG_RST_H_SM_0_MASK		BIT_MASK(14)
+#define CFG_RST_H_SM_1_MASK		BIT_MASK(15)
+#define CFG_RST_H_SM_2_MASK		BIT_MASK(16)
+#define CFG_RST_H_SM_3_MASK		BIT_MASK(17)
+#define CFG_RST_H_SM_MASK		GENMASK(17, 14)
+
+#define CFG_RST_H_DMA_0_MASK		BIT_MASK(18)
+#define CFG_RST_H_DMA_1_MASK		BIT_MASK(19)
+#define CFG_RST_H_DMA_MASK		GENMASK(19, 18)
+
+#define CFG_RST_H_CPU_MASK		BIT_MASK(20)
+#define CFG_RST_H_MMU_MASK		BIT_MASK(21)
+
+#define UNIT_RST_L_PSOC_SHIFT		0
+#define UNIT_RST_L_PCIE_SHIFT		1
+#define UNIT_RST_L_PCIE_IF_SHIFT	2
+#define UNIT_RST_L_HBM_S_PLL_SHIFT	3
+#define UNIT_RST_L_TPC_S_PLL_SHIFT	4
+#define UNIT_RST_L_MME_S_PLL_SHIFT	5
+#define UNIT_RST_L_CPU_PLL_SHIFT	6
+#define UNIT_RST_L_PCIE_PLL_SHIFT	7
+#define UNIT_RST_L_NIC_S_PLL_SHIFT	8
+#define UNIT_RST_L_HBM_N_PLL_SHIFT	9
+#define UNIT_RST_L_TPC_N_PLL_SHIFT	10
+#define UNIT_RST_L_MME_N_PLL_SHIFT	11
+#define UNIT_RST_L_NIC_N_PLL_SHIFT	12
+#define UNIT_RST_L_DMA_W_PLL_SHIFT	13
+#define UNIT_RST_L_SIF_W_PLL_SHIFT	14
+#define UNIT_RST_L_MESH_W_PLL_SHIFT	15
+#define UNIT_RST_L_SRAM_W_PLL_SHIFT	16
+#define UNIT_RST_L_DMA_E_PLL_SHIFT	17
+#define UNIT_RST_L_SIF_E_PLL_SHIFT	18
+#define UNIT_RST_L_MESH_E_PLL_SHIFT	19
+#define UNIT_RST_L_SRAM_E_PLL_SHIFT	20
+#define UNIT_RST_L_TPC_0_SHIFT		21
+#define UNIT_RST_L_TPC_1_SHIFT		22
+#define UNIT_RST_L_TPC_2_SHIFT		23
+#define UNIT_RST_L_TPC_3_SHIFT		24
+#define UNIT_RST_L_TPC_4_SHIFT		25
+#define UNIT_RST_L_TPC_5_SHIFT		26
+#define UNIT_RST_L_TPC_6_SHIFT		27
+#define UNIT_RST_L_TPC_7_SHIFT		28
+#define UNIT_RST_L_MME_0_SHIFT		29
+#define UNIT_RST_L_MME_1_SHIFT		30
+#define UNIT_RST_L_MME_2_SHIFT		31
+
+#define UNIT_RST_H_MME_3_SHIFT		0
+#define UNIT_RST_H_HBM_0_SHIFT		1
+#define UNIT_RST_H_HBM_1_SHIFT		2
+#define UNIT_RST_H_HBM_2_SHIFT		3
+#define UNIT_RST_H_HBM_3_SHIFT		4
+#define UNIT_RST_H_NIC_0_SHIFT		5
+#define UNIT_RST_H_NIC_1_SHIFT		6
+#define UNIT_RST_H_NIC_2_SHIFT		7
+#define UNIT_RST_H_NIC_3_SHIFT		8
+#define UNIT_RST_H_NIC_4_SHIFT		9
+#define UNIT_RST_H_SM_0_SHIFT		10
+#define UNIT_RST_H_SM_1_SHIFT		11
+#define UNIT_RST_H_SM_2_SHIFT		12
+#define UNIT_RST_H_SM_3_SHIFT		13
+#define UNIT_RST_H_IF_0_SHIFT		14
+#define UNIT_RST_H_IF_1_SHIFT		15
+#define UNIT_RST_H_IF_2_SHIFT		16
+#define UNIT_RST_H_IF_3_SHIFT		17
+#define UNIT_RST_H_DMA_0_SHIFT		18
+#define UNIT_RST_H_DMA_1_SHIFT		19
+#define UNIT_RST_H_CPU_SHIFT		20
+#define UNIT_RST_H_MMU_SHIFT		21
+
+#define UNIT_RST_H_HBM_MASK		((1 << UNIT_RST_H_HBM_0_SHIFT) | \
+					(1 << UNIT_RST_H_HBM_1_SHIFT) | \
+					(1 << UNIT_RST_H_HBM_2_SHIFT) | \
+					(1 << UNIT_RST_H_HBM_3_SHIFT))
+
+#define UNIT_RST_H_NIC_MASK		((1 << UNIT_RST_H_NIC_0_SHIFT) | \
+					(1 << UNIT_RST_H_NIC_1_SHIFT) | \
+					(1 << UNIT_RST_H_NIC_2_SHIFT) | \
+					(1 << UNIT_RST_H_NIC_3_SHIFT) | \
+					(1 << UNIT_RST_H_NIC_4_SHIFT))
+
+#define UNIT_RST_H_SM_MASK		((1 << UNIT_RST_H_SM_0_SHIFT) | \
+					(1 << UNIT_RST_H_SM_1_SHIFT) | \
+					(1 << UNIT_RST_H_SM_2_SHIFT) | \
+					(1 << UNIT_RST_H_SM_3_SHIFT))
+
+#define UNIT_RST_H_MME_MASK		((1 << UNIT_RST_H_MME_0_SHIFT) | \
+					(1 << UNIT_RST_H_MME_1_SHIFT) | \
+					(1 << UNIT_RST_H_MME_2_SHIFT))
+
+#define UNIT_RST_L_MME_MASK		(1 << UNIT_RST_L_MME_3_SHIFT)
+
+#define UNIT_RST_L_IF_MASK		((1 << UNIT_RST_L_IF_0_SHIFT) | \
+					(1 << UNIT_RST_L_IF_1_SHIFT) | \
+					(1 << UNIT_RST_L_IF_2_SHIFT) | \
+					(1 << UNIT_RST_L_IF_3_SHIFT))
+
+#define UNIT_RST_L_TPC_MASK		((1 << UNIT_RST_L_TPC_0_SHIFT) | \
+					(1 << UNIT_RST_L_TPC_1_SHIFT) | \
+					(1 << UNIT_RST_L_TPC_2_SHIFT) | \
+					(1 << UNIT_RST_L_TPC_3_SHIFT) | \
+					(1 << UNIT_RST_L_TPC_4_SHIFT) | \
+					(1 << UNIT_RST_L_TPC_5_SHIFT) | \
+					(1 << UNIT_RST_L_TPC_6_SHIFT) | \
+					(1 << UNIT_RST_L_TPC_7_SHIFT))
+
+/* CPU_CA53_CFG_ARM_RST_CONTROL */
+#define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT               0
+#define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_MASK                0x3
+#define CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_SHIFT                4
+#define CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_MASK                 0x30
+#define CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_SHIFT                  8
+#define CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_MASK                   0x100
+#define CPU_CA53_CFG_ARM_RST_CONTROL_NPRESETDBG_SHIFT                12
+#define CPU_CA53_CFG_ARM_RST_CONTROL_NPRESETDBG_MASK                 0x1000
+#define CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT               16
+#define CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_MASK                0x10000
+#define CPU_CA53_CFG_ARM_RST_CONTROL_WARMRSTREQ_SHIFT                20
+#define CPU_CA53_CFG_ARM_RST_CONTROL_WARMRSTREQ_MASK                 0x300000
+
+#define CPU_RESET_ASSERT	(\
+			1 << CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT)
+
+#define CPU_RESET_CORE0_DEASSERT	(\
+			1 << CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT |\
+			1 << CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_SHIFT |\
+			1 << CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_SHIFT |\
+			1 << CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT)
+
+/* QM_IDLE_MASK is valid for all engines QM idle check */
+#define QM_IDLE_MASK	(DMA0_QM_GLBL_STS0_PQF_IDLE_MASK | \
+			DMA0_QM_GLBL_STS0_CQF_IDLE_MASK | \
+			DMA0_QM_GLBL_STS0_CP_IDLE_MASK)
+
+/* CGM_IDLE_MASK is valid for all engines CGM idle check */
+#define CGM_IDLE_MASK	DMA0_QM_CGM_STS_AGENT_IDLE_MASK
+
+#define TPC_IDLE_MASK	((1 << TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_SHIFT) | \
+			(1 << TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_SHIFT) | \
+			(1 << TPC0_CFG_STATUS_IQ_EMPTY_SHIFT) | \
+			(1 << TPC0_CFG_STATUS_SB_EMPTY_SHIFT) | \
+			(1 << TPC0_CFG_STATUS_QM_IDLE_SHIFT) | \
+			(1 << TPC0_CFG_STATUS_QM_RDY_SHIFT))
+
+#define MME0_CTRL_ARCH_STATUS_SB_A_EMPTY_MASK                        0x80
+#define MME0_CTRL_ARCH_STATUS_SB_B_EMPTY_MASK                        0x100
+#define MME0_CTRL_ARCH_STATUS_WBC_AXI_IDLE_MASK                      0x1000
+
+#define MME_ARCH_IDLE_MASK	(MME0_CTRL_ARCH_STATUS_SB_A_EMPTY_MASK | \
+				MME0_CTRL_ARCH_STATUS_SB_B_EMPTY_MASK | \
+				MME0_CTRL_ARCH_STATUS_WBC_AXI_IDLE_MASK)
+
+#define IS_QM_IDLE(qm_glbl_sts0, qm_cgm_sts) \
+	((((qm_glbl_sts0) & QM_IDLE_MASK) == QM_IDLE_MASK) && \
+			(((qm_cgm_sts) & CGM_IDLE_MASK) == CGM_IDLE_MASK))
+
+#define IS_DMA_IDLE(dma_core_sts0) \
+	!(dma_core_sts0 & DMA0_CORE_STS0_BUSY_MASK)
+
+#define IS_TPC_IDLE(tpc_cfg_sts) \
+	(((tpc_cfg_sts) & TPC_IDLE_MASK) == TPC_IDLE_MASK)
+
+#define IS_MME_IDLE(mme_arch_sts) \
+	(((mme_arch_sts) & MME_ARCH_IDLE_MASK) == MME_ARCH_IDLE_MASK)
+
+enum axi_id {
+	AXI_ID_MME,
+	AXI_ID_TPC,
+	AXI_ID_DMA,
+	AXI_ID_NIC,	/* Local NIC */
+	AXI_ID_PCI,
+	AXI_ID_CPU,
+	AXI_ID_PSOC,
+	AXI_ID_MMU,
+	AXI_ID_NIC_FT	/* Feed-Through NIC */
+};
+
+/* RAZWI initiator ID is built from the location in the chip and the AXI ID */
+
+#define RAZWI_INITIATOR_AXI_ID_SHIFT	20
+#define RAZWI_INITIATOR_AXI_ID_MASK	0xF
+#define RAZWI_INITIATOR_X_SHIFT		24
+#define RAZWI_INITIATOR_X_MASK		0xF
+#define RAZWI_INITIATOR_Y_SHIFT		28
+#define RAZWI_INITIATOR_Y_MASK		0x7
+
+#define RAZWI_INITIATOR_ID_AXI_ID(axi_id) \
+	(((axi_id) & RAZWI_INITIATOR_AXI_ID_MASK) << \
+		RAZWI_INITIATOR_AXI_ID_SHIFT)
+
+#define RAZWI_INITIATOR_ID_X_Y(x, y) \
+	((((y) & RAZWI_INITIATOR_Y_MASK) << RAZWI_INITIATOR_Y_SHIFT) | \
+		(((x) & RAZWI_INITIATOR_X_MASK) << RAZWI_INITIATOR_X_SHIFT))
+
+#define RAZWI_INITIATOR_ID_X_Y_TPC0_NIC0	RAZWI_INITIATOR_ID_X_Y(1, 1)
+#define RAZWI_INITIATOR_ID_X_Y_TPC1		RAZWI_INITIATOR_ID_X_Y(2, 1)
+#define RAZWI_INITIATOR_ID_X_Y_MME0_0		RAZWI_INITIATOR_ID_X_Y(3, 1)
+#define RAZWI_INITIATOR_ID_X_Y_MME0_1		RAZWI_INITIATOR_ID_X_Y(4, 1)
+#define RAZWI_INITIATOR_ID_X_Y_MME1_0		RAZWI_INITIATOR_ID_X_Y(5, 1)
+#define RAZWI_INITIATOR_ID_X_Y_MME1_1		RAZWI_INITIATOR_ID_X_Y(6, 1)
+#define RAZWI_INITIATOR_ID_X_Y_TPC2		RAZWI_INITIATOR_ID_X_Y(7, 1)
+#define RAZWI_INITIATOR_ID_X_Y_TPC3_PCI_CPU_PSOC \
+						RAZWI_INITIATOR_ID_X_Y(8, 1)
+#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_0	RAZWI_INITIATOR_ID_X_Y(0, 1)
+#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_0	RAZWI_INITIATOR_ID_X_Y(9, 1)
+#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_1	RAZWI_INITIATOR_ID_X_Y(0, 2)
+#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_1	RAZWI_INITIATOR_ID_X_Y(9, 2)
+#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_0	RAZWI_INITIATOR_ID_X_Y(0, 3)
+#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_0	RAZWI_INITIATOR_ID_X_Y(9, 3)
+#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_1	RAZWI_INITIATOR_ID_X_Y(0, 4)
+#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_1	RAZWI_INITIATOR_ID_X_Y(9, 4)
+#define RAZWI_INITIATOR_ID_X_Y_TPC4_NIC1_NIC2	RAZWI_INITIATOR_ID_X_Y(1, 6)
+#define RAZWI_INITIATOR_ID_X_Y_TPC5		RAZWI_INITIATOR_ID_X_Y(2, 6)
+#define RAZWI_INITIATOR_ID_X_Y_MME2_0		RAZWI_INITIATOR_ID_X_Y(3, 6)
+#define RAZWI_INITIATOR_ID_X_Y_MME2_1		RAZWI_INITIATOR_ID_X_Y(4, 6)
+#define RAZWI_INITIATOR_ID_X_Y_MME3_0		RAZWI_INITIATOR_ID_X_Y(5, 6)
+#define RAZWI_INITIATOR_ID_X_Y_MME3_1		RAZWI_INITIATOR_ID_X_Y(6, 6)
+#define RAZWI_INITIATOR_ID_X_Y_TPC6		RAZWI_INITIATOR_ID_X_Y(7, 6)
+#define RAZWI_INITIATOR_ID_X_Y_TPC7_NIC4_NIC5	RAZWI_INITIATOR_ID_X_Y(8, 6)
+
+#define PSOC_ETR_AXICTL_PROTCTRLBIT1_SHIFT	1
+#define PSOC_ETR_AXICTL_PROTCTRLBIT0_MASK	0x1
+#define PSOC_ETR_AXICTL_PROTCTRLBIT1_MASK	0x2
+#define PSOC_ETR_AXICTL_WRBURSTLEN_MASK		0xF00
+
+/* STLB_CACHE_INV */
+#define STLB_CACHE_INV_PRODUCER_INDEX_SHIFT                          0
+#define STLB_CACHE_INV_PRODUCER_INDEX_MASK                           0xFF
+#define STLB_CACHE_INV_INDEX_MASK_SHIFT                              8
+#define STLB_CACHE_INV_INDEX_MASK_MASK                               0xFF00
+
+#define MME_ACC_ACC_STALL_R_SHIFT                                    0
+#define MME_SBAB_SB_STALL_R_SHIFT                                    0
+
+#define PCIE_WRAP_LBW_PROT_OVR_RD_EN_MASK                            0x700
+#define PCIE_WRAP_LBW_PROT_OVR_WR_EN_MASK                            0x7000
+
+#define PCIE_WRAP_LBW_DRAIN_CFG_EN_SHIFT                             0
+#define PCIE_WRAP_HBW_DRAIN_CFG_EN_SHIFT                             0
+
+/* DMA_IF_HBM_CRED_EN */
+#define DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT                      0
+#define DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_MASK                       0x1
+#define DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT                     1
+#define DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_MASK                      0x2
+
+#define DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT                      0
+#define DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT                       0
+#define DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT                         0
+#define DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT                         0
+
+#define IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT                          0
+#define IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT                           0
+
+#define IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT                             0
+#define IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT                             0
+
+/* MMU_UP_PAGE_ERROR_CAPTURE */
+#define MMU_UP_PAGE_ERROR_CAPTURE_VA_49_32_MASK                      0x3FFFF
+#define MMU_UP_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK                   0x40000
+
+/* MMU_UP_ACCESS_ERROR_CAPTURE */
+#define MMU_UP_ACCESS_ERROR_CAPTURE_VA_49_32_MASK                    0x3FFFF
+#define MMU_UP_ACCESS_ERROR_CAPTURE_ENTRY_VALID_MASK                 0x40000
+
+#define QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK                            0x1
+#define QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK                            0x2
+#define QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK                           0x4
+
+#define QM_ARB_ERR_MSG_EN_MASK		(\
+					QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK |\
+					QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK |\
+					QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK)
+
+#define PCIE_AUX_FLR_CTRL_HW_CTRL_MASK                               0x1
+#define PCIE_AUX_FLR_CTRL_INT_MASK_MASK                              0x2
+
+#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0_VALID_SHIFT        0
+#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0_VALID_MASK         0x1
+#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0_PENDING_SHIFT      1
+#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0_PENDING_MASK       0x1FE
+#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SID_SHIFT             0
+#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SID_MASK              0xFF
+#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_MASK_SHIFT            8
+#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_MASK_MASK             0xFF00
+#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SOP_SHIFT             16
+#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SOP_MASK              0x10000
+#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SOD_SHIFT             17
+#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SOD_MASK              0xFFFE0000
+#define TPC0_QM_CP_STS_0_FENCE_ID_SHIFT                              20
+#define TPC0_QM_CP_STS_0_FENCE_ID_MASK                               0x300000
+#define TPC0_QM_CP_STS_0_FENCE_IN_PROGRESS_SHIFT                     22
+#define TPC0_QM_CP_STS_0_FENCE_IN_PROGRESS_MASK                      0x400000
+
+#endif /* GAUDI_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/gaudi_packets.h b/drivers/accel/habanalabs/include/gaudi/gaudi_packets.h
new file mode 100644
index 000000000000..66fc083a7c6a
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/gaudi_packets.h
@@ -0,0 +1,194 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2017-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+#ifndef GAUDI_PACKETS_H
+#define GAUDI_PACKETS_H
+
+#include <linux/types.h>
+
+#define PACKET_HEADER_PACKET_ID_SHIFT		56
+#define PACKET_HEADER_PACKET_ID_MASK		0x1F00000000000000ull
+
+enum packet_id {
+	PACKET_WREG_32 = 0x1,
+	PACKET_WREG_BULK = 0x2,
+	PACKET_MSG_LONG = 0x3,
+	PACKET_MSG_SHORT = 0x4,
+	PACKET_CP_DMA = 0x5,
+	PACKET_REPEAT = 0x6,
+	PACKET_MSG_PROT = 0x7,
+	PACKET_FENCE = 0x8,
+	PACKET_LIN_DMA = 0x9,
+	PACKET_NOP = 0xA,
+	PACKET_STOP = 0xB,
+	PACKET_ARB_POINT = 0xC,
+	PACKET_WAIT = 0xD,
+	PACKET_LOAD_AND_EXE = 0xF,
+	MAX_PACKET_ID = (PACKET_HEADER_PACKET_ID_MASK >>
+				PACKET_HEADER_PACKET_ID_SHIFT) + 1
+};
+
+#define GAUDI_PKT_CTL_OPCODE_SHIFT	24
+#define GAUDI_PKT_CTL_OPCODE_MASK	0x1F000000
+
+#define GAUDI_PKT_CTL_EB_SHIFT		29
+#define GAUDI_PKT_CTL_EB_MASK		0x20000000
+
+#define GAUDI_PKT_CTL_RB_SHIFT		30
+#define GAUDI_PKT_CTL_RB_MASK		0x40000000
+
+#define GAUDI_PKT_CTL_MB_SHIFT		31
+#define GAUDI_PKT_CTL_MB_MASK		0x80000000
+
+/* All packets have, at least, an 8-byte header, which contains
+ * the packet type. The kernel driver uses the packet header for packet
+ * validation and to perform any necessary required preparation before
+ * sending them off to the hardware.
+ */
+struct gaudi_packet {
+	__le64 header;
+	/* The rest of the packet data follows. Use the corresponding
+	 * packet_XXX struct to deference the data, based on packet type
+	 */
+	u8 contents[];
+};
+
+struct packet_nop {
+	__le32 reserved;
+	__le32 ctl;
+};
+
+struct packet_stop {
+	__le32 reserved;
+	__le32 ctl;
+};
+
+struct packet_wreg32 {
+	__le32 value;
+	__le32 ctl;
+};
+
+struct packet_wreg_bulk {
+	__le32 size64;
+	__le32 ctl;
+	__le64 values[]; /* data starts here */
+};
+
+#define GAUDI_PKT_LONG_CTL_OP_SHIFT		20
+#define GAUDI_PKT_LONG_CTL_OP_MASK		0x00300000
+
+struct packet_msg_long {
+	__le32 value;
+	__le32 ctl;
+	__le64 addr;
+};
+
+#define GAUDI_PKT_SHORT_VAL_SOB_SYNC_VAL_SHIFT	0
+#define GAUDI_PKT_SHORT_VAL_SOB_SYNC_VAL_MASK	0x00007FFF
+
+#define GAUDI_PKT_SHORT_VAL_SOB_MOD_SHIFT	31
+#define GAUDI_PKT_SHORT_VAL_SOB_MOD_MASK	0x80000000
+
+#define GAUDI_PKT_SHORT_VAL_MON_SYNC_GID_SHIFT	0
+#define GAUDI_PKT_SHORT_VAL_MON_SYNC_GID_MASK	0x000000FF
+
+#define GAUDI_PKT_SHORT_VAL_MON_MASK_SHIFT	8
+#define GAUDI_PKT_SHORT_VAL_MON_MASK_MASK	0x0000FF00
+
+#define GAUDI_PKT_SHORT_VAL_MON_MODE_SHIFT	16
+#define GAUDI_PKT_SHORT_VAL_MON_MODE_MASK	0x00010000
+
+#define GAUDI_PKT_SHORT_VAL_MON_SYNC_VAL_SHIFT	17
+#define GAUDI_PKT_SHORT_VAL_MON_SYNC_VAL_MASK	0xFFFE0000
+
+#define GAUDI_PKT_SHORT_CTL_ADDR_SHIFT		0
+#define GAUDI_PKT_SHORT_CTL_ADDR_MASK		0x0000FFFF
+
+#define GAUDI_PKT_SHORT_CTL_OP_SHIFT		20
+#define GAUDI_PKT_SHORT_CTL_OP_MASK		0x00300000
+
+#define GAUDI_PKT_SHORT_CTL_BASE_SHIFT		22
+#define GAUDI_PKT_SHORT_CTL_BASE_MASK		0x00C00000
+
+struct packet_msg_short {
+	__le32 value;
+	__le32 ctl;
+};
+
+struct packet_msg_prot {
+	__le32 value;
+	__le32 ctl;
+	__le64 addr;
+};
+
+#define GAUDI_PKT_FENCE_CFG_DEC_VAL_SHIFT	0
+#define GAUDI_PKT_FENCE_CFG_DEC_VAL_MASK	0x0000000F
+
+#define GAUDI_PKT_FENCE_CFG_TARGET_VAL_SHIFT	16
+#define GAUDI_PKT_FENCE_CFG_TARGET_VAL_MASK	0x00FF0000
+
+#define GAUDI_PKT_FENCE_CFG_ID_SHIFT		30
+#define GAUDI_PKT_FENCE_CFG_ID_MASK		0xC0000000
+
+#define GAUDI_PKT_FENCE_CTL_PRED_SHIFT		0
+#define GAUDI_PKT_FENCE_CTL_PRED_MASK		0x0000001F
+
+struct packet_fence {
+	__le32 cfg;
+	__le32 ctl;
+};
+
+#define GAUDI_PKT_LIN_DMA_CTL_WRCOMP_EN_SHIFT	0
+#define GAUDI_PKT_LIN_DMA_CTL_WRCOMP_EN_MASK	0x00000001
+
+#define GAUDI_PKT_LIN_DMA_CTL_LIN_SHIFT		3
+#define GAUDI_PKT_LIN_DMA_CTL_LIN_MASK		0x00000008
+
+#define GAUDI_PKT_LIN_DMA_CTL_MEMSET_SHIFT	4
+#define GAUDI_PKT_LIN_DMA_CTL_MEMSET_MASK	0x00000010
+
+#define GAUDI_PKT_LIN_DMA_DST_ADDR_SHIFT	0
+#define GAUDI_PKT_LIN_DMA_DST_ADDR_MASK		0x00FFFFFFFFFFFFFFull
+
+struct packet_lin_dma {
+	__le32 tsize;
+	__le32 ctl;
+	__le64 src_addr;
+	__le64 dst_addr;
+};
+
+struct packet_arb_point {
+	__le32 cfg;
+	__le32 ctl;
+};
+
+struct packet_repeat {
+	__le32 cfg;
+	__le32 ctl;
+};
+
+struct packet_wait {
+	__le32 cfg;
+	__le32 ctl;
+};
+
+#define GAUDI_PKT_LOAD_AND_EXE_CFG_DST_SHIFT	0
+#define GAUDI_PKT_LOAD_AND_EXE_CFG_DST_MASK	0x00000001
+
+struct packet_load_and_exe {
+	__le32 cfg;
+	__le32 ctl;
+	__le64 src_addr;
+};
+
+struct packet_cp_dma {
+	__le32 tsize;
+	__le32 ctl;
+	__le64 src_addr;
+};
+
+#endif /* GAUDI_PACKETS_H */
diff --git a/drivers/accel/habanalabs/include/gaudi/gaudi_reg_map.h b/drivers/accel/habanalabs/include/gaudi/gaudi_reg_map.h
new file mode 100644
index 000000000000..92f25c2ae083
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/gaudi_reg_map.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2019-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+#ifndef GAUDI_REG_MAP_H_
+#define GAUDI_REG_MAP_H_
+
+/*
+ * PSOC scratch-pad registers
+ */
+#define mmHW_STATE			mmPSOC_GLOBAL_CONF_SCRATCHPAD_0
+#define mmGIC_HOST_PI_UPD_IRQ_POLL_REG	mmPSOC_GLOBAL_CONF_SCRATCHPAD_1
+#define mmGIC_TPC_QM_IRQ_CTRL_POLL_REG	mmPSOC_GLOBAL_CONF_SCRATCHPAD_2
+#define mmGIC_MME_QM_IRQ_CTRL_POLL_REG	mmPSOC_GLOBAL_CONF_SCRATCHPAD_3
+#define mmGIC_DMA_QM_IRQ_CTRL_POLL_REG	mmPSOC_GLOBAL_CONF_SCRATCHPAD_4
+#define mmGIC_NIC_QM_IRQ_CTRL_POLL_REG	mmPSOC_GLOBAL_CONF_SCRATCHPAD_5
+#define mmGIC_DMA_CR_IRQ_CTRL_POLL_REG	mmPSOC_GLOBAL_CONF_SCRATCHPAD_6
+#define mmGIC_HOST_HALT_IRQ_POLL_REG	mmPSOC_GLOBAL_CONF_SCRATCHPAD_7
+#define mmGIC_HOST_INTS_IRQ_POLL_REG	mmPSOC_GLOBAL_CONF_SCRATCHPAD_8
+#define mmCPU_BOOT_DEV_STS0		mmPSOC_GLOBAL_CONF_SCRATCHPAD_20
+#define mmCPU_BOOT_DEV_STS1		mmPSOC_GLOBAL_CONF_SCRATCHPAD_21
+#define mmFUSE_VER_OFFSET		mmPSOC_GLOBAL_CONF_SCRATCHPAD_22
+#define mmCPU_CMD_STATUS_TO_HOST	mmPSOC_GLOBAL_CONF_SCRATCHPAD_23
+#define mmCPU_BOOT_ERR0			mmPSOC_GLOBAL_CONF_SCRATCHPAD_24
+#define mmCPU_BOOT_ERR1			mmPSOC_GLOBAL_CONF_SCRATCHPAD_25
+#define mmUPD_STS			mmPSOC_GLOBAL_CONF_SCRATCHPAD_26
+#define mmUPD_CMD			mmPSOC_GLOBAL_CONF_SCRATCHPAD_27
+#define mmPREBOOT_VER_OFFSET		mmPSOC_GLOBAL_CONF_SCRATCHPAD_28
+#define mmUBOOT_VER_OFFSET		mmPSOC_GLOBAL_CONF_SCRATCHPAD_29
+#define mmRDWR_TEST			mmPSOC_GLOBAL_CONF_SCRATCHPAD_30
+#define mmBTL_ID			mmPSOC_GLOBAL_CONF_SCRATCHPAD_31
+#define mmPREBOOT_PCIE_EN		mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_1
+#define mmCOLD_RST_DATA			mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_2
+#define mmUPD_PENDING_STS		mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_3
+
+#endif /* GAUDI_REG_MAP_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/arc/gaudi2_arc_common_packets.h b/drivers/accel/habanalabs/include/gaudi2/arc/gaudi2_arc_common_packets.h
new file mode 100644
index 000000000000..22a6ab9a7f47
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/arc/gaudi2_arc_common_packets.h
@@ -0,0 +1,211 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2020 HabanaLabs Ltd.
+ * All Rights Reserved.
+ */
+
+#ifndef __GAUDI2_ARC_COMMON_PACKETS_H__
+#define __GAUDI2_ARC_COMMON_PACKETS_H__
+
+enum {
+	CPU_ID_SCHED_ARC0 = 0, /* FARM_ARC0 */
+	CPU_ID_SCHED_ARC1 = 1, /* FARM_ARC1 */
+	CPU_ID_SCHED_ARC2 = 2, /* FARM_ARC2 */
+	CPU_ID_SCHED_ARC3 = 3, /* FARM_ARC3 */
+	/* Dcore1 MME Engine ARC instance used as scheduler */
+	CPU_ID_SCHED_ARC4 = 4, /* DCORE1_MME0 */
+	/* Dcore3 MME Engine ARC instance used as scheduler */
+	CPU_ID_SCHED_ARC5 = 5, /* DCORE3_MME0 */
+
+	CPU_ID_TPC_QMAN_ARC0 = 6,   /* DCORE0_TPC0 */
+	CPU_ID_TPC_QMAN_ARC1 = 7,   /* DCORE0_TPC1 */
+	CPU_ID_TPC_QMAN_ARC2 = 8,   /* DCORE0_TPC2 */
+	CPU_ID_TPC_QMAN_ARC3 = 9,   /* DCORE0_TPC3 */
+	CPU_ID_TPC_QMAN_ARC4 = 10,  /* DCORE0_TPC4 */
+	CPU_ID_TPC_QMAN_ARC5 = 11,  /* DCORE0_TPC5 */
+	CPU_ID_TPC_QMAN_ARC6 = 12,  /* DCORE1_TPC0 */
+	CPU_ID_TPC_QMAN_ARC7 = 13,  /* DCORE1_TPC1 */
+	CPU_ID_TPC_QMAN_ARC8 = 14,  /* DCORE1_TPC2 */
+	CPU_ID_TPC_QMAN_ARC9 = 15,  /* DCORE1_TPC3 */
+	CPU_ID_TPC_QMAN_ARC10 = 16, /* DCORE1_TPC4 */
+	CPU_ID_TPC_QMAN_ARC11 = 17, /* DCORE1_TPC5 */
+	CPU_ID_TPC_QMAN_ARC12 = 18, /* DCORE2_TPC0 */
+	CPU_ID_TPC_QMAN_ARC13 = 19, /* DCORE2_TPC1 */
+	CPU_ID_TPC_QMAN_ARC14 = 20, /* DCORE2_TPC2 */
+	CPU_ID_TPC_QMAN_ARC15 = 21, /* DCORE2_TPC3 */
+	CPU_ID_TPC_QMAN_ARC16 = 22, /* DCORE2_TPC4 */
+	CPU_ID_TPC_QMAN_ARC17 = 23, /* DCORE2_TPC5 */
+	CPU_ID_TPC_QMAN_ARC18 = 24, /* DCORE3_TPC0 */
+	CPU_ID_TPC_QMAN_ARC19 = 25, /* DCORE3_TPC1 */
+	CPU_ID_TPC_QMAN_ARC20 = 26, /* DCORE3_TPC2 */
+	CPU_ID_TPC_QMAN_ARC21 = 27, /* DCORE3_TPC3 */
+	CPU_ID_TPC_QMAN_ARC22 = 28, /* DCORE3_TPC4 */
+	CPU_ID_TPC_QMAN_ARC23 = 29, /* DCORE3_TPC5 */
+	CPU_ID_TPC_QMAN_ARC24 = 30, /* DCORE0_TPC6 - Never present */
+
+	CPU_ID_MME_QMAN_ARC0 = 31, /* DCORE0_MME0 */
+	CPU_ID_MME_QMAN_ARC1 = 32, /* DCORE2_MME0 */
+
+	CPU_ID_EDMA_QMAN_ARC0 = 33, /* DCORE0_EDMA0 */
+	CPU_ID_EDMA_QMAN_ARC1 = 34, /* DCORE0_EDMA1 */
+	CPU_ID_EDMA_QMAN_ARC2 = 35, /* DCORE1_EDMA0 */
+	CPU_ID_EDMA_QMAN_ARC3 = 36, /* DCORE1_EDMA1 */
+	CPU_ID_EDMA_QMAN_ARC4 = 37, /* DCORE2_EDMA0 */
+	CPU_ID_EDMA_QMAN_ARC5 = 38, /* DCORE2_EDMA1 */
+	CPU_ID_EDMA_QMAN_ARC6 = 39, /* DCORE3_EDMA0 */
+	CPU_ID_EDMA_QMAN_ARC7 = 40, /* DCORE3_EDMA1 */
+
+	CPU_ID_PDMA_QMAN_ARC0 = 41, /* DCORE0_PDMA0 */
+	CPU_ID_PDMA_QMAN_ARC1 = 42, /* DCORE0_PDMA1 */
+
+	CPU_ID_ROT_QMAN_ARC0 = 43, /* ROT0 */
+	CPU_ID_ROT_QMAN_ARC1 = 44, /* ROT1 */
+
+	CPU_ID_NIC_QMAN_ARC0 = 45,  /* NIC0_0 */
+	CPU_ID_NIC_QMAN_ARC1 = 46,  /* NIC0_1 */
+	CPU_ID_NIC_QMAN_ARC2 = 47,  /* NIC1_0 */
+	CPU_ID_NIC_QMAN_ARC3 = 48,  /* NIC1_1 */
+	CPU_ID_NIC_QMAN_ARC4 = 49,  /* NIC2_0 */
+	CPU_ID_NIC_QMAN_ARC5 = 50,  /* NIC2_1 */
+	CPU_ID_NIC_QMAN_ARC6 = 51,  /* NIC3_0 */
+	CPU_ID_NIC_QMAN_ARC7 = 52,  /* NIC3_1 */
+	CPU_ID_NIC_QMAN_ARC8 = 53,  /* NIC4_0 */
+	CPU_ID_NIC_QMAN_ARC9 = 54,  /* NIC4_1 */
+	CPU_ID_NIC_QMAN_ARC10 = 55, /* NIC5_0 */
+	CPU_ID_NIC_QMAN_ARC11 = 56, /* NIC5_1 */
+	CPU_ID_NIC_QMAN_ARC12 = 57, /* NIC6_0 */
+	CPU_ID_NIC_QMAN_ARC13 = 58, /* NIC6_1 */
+	CPU_ID_NIC_QMAN_ARC14 = 59, /* NIC7_0 */
+	CPU_ID_NIC_QMAN_ARC15 = 60, /* NIC7_1 */
+	CPU_ID_NIC_QMAN_ARC16 = 61, /* NIC8_0 */
+	CPU_ID_NIC_QMAN_ARC17 = 62, /* NIC8_1 */
+	CPU_ID_NIC_QMAN_ARC18 = 63, /* NIC9_0 */
+	CPU_ID_NIC_QMAN_ARC19 = 64, /* NIC9_1 */
+	CPU_ID_NIC_QMAN_ARC20 = 65, /* NIC10_0 */
+	CPU_ID_NIC_QMAN_ARC21 = 66, /* NIC10_1 */
+	CPU_ID_NIC_QMAN_ARC22 = 67, /* NIC11_0 */
+	CPU_ID_NIC_QMAN_ARC23 = 68, /* NIC11_1 */
+
+	CPU_ID_MAX = 69,
+	CPU_ID_SCHED_MAX = 6,
+
+	CPU_ID_ALL = 0xFE,
+	CPU_ID_INVALID = 0xFF,
+};
+
+enum arc_regions_t {
+	ARC_REGION0_UNSED  = 0,
+	/*
+	 * Extension registers
+	 * None
+	 */
+	ARC_REGION1_SRAM = 1,
+	/*
+	 * Extension registers
+	 * AUX_SRAM_LSB_ADDR
+	 * AUX_SRAM_MSB_ADDR
+	 * ARC Address: 0x1000_0000
+	 */
+	ARC_REGION2_CFG = 2,
+	/*
+	 * Extension registers
+	 * AUX_CFG_LSB_ADDR
+	 * AUX_CFG_MSB_ADDR
+	 * ARC Address: 0x2000_0000
+	 */
+	ARC_REGION3_GENERAL = 3,
+	/*
+	 * Extension registers
+	 * AUX_GENERAL_PURPOSE_LSB_ADDR_0
+	 * AUX_GENERAL_PURPOSE_MSB_ADDR_0
+	 * ARC Address: 0x3000_0000
+	 */
+	ARC_REGION4_HBM0_FW = 4,
+	/*
+	 * Extension registers
+	 * AUX_HBM0_LSB_ADDR
+	 * AUX_HBM0_MSB_ADDR
+	 * AUX_HBM0_OFFSET
+	 * ARC Address: 0x4000_0000
+	 */
+	ARC_REGION5_HBM1_GC_DATA = 5,
+	/*
+	 * Extension registers
+	 * AUX_HBM1_LSB_ADDR
+	 * AUX_HBM1_MSB_ADDR
+	 * AUX_HBM1_OFFSET
+	 * ARC Address: 0x5000_0000
+	 */
+	ARC_REGION6_HBM2_GC_DATA = 6,
+	/*
+	 * Extension registers
+	 * AUX_HBM2_LSB_ADDR
+	 * AUX_HBM2_MSB_ADDR
+	 * AUX_HBM2_OFFSET
+	 * ARC Address: 0x6000_0000
+	 */
+	ARC_REGION7_HBM3_GC_DATA = 7,
+	/*
+	 * Extension registers
+	 * AUX_HBM3_LSB_ADDR
+	 * AUX_HBM3_MSB_ADDR
+	 * AUX_HBM3_OFFSET
+	 * ARC Address: 0x7000_0000
+	 */
+	ARC_REGION8_DCCM = 8,
+	/*
+	 * Extension registers
+	 * None
+	 * ARC Address: 0x8000_0000
+	 */
+	ARC_REGION9_PCIE = 9,
+	/*
+	 * Extension registers
+	 * AUX_PCIE_LSB_ADDR
+	 * AUX_PCIE_MSB_ADDR
+	 * ARC Address: 0x9000_0000
+	 */
+	ARC_REGION10_GENERAL = 10,
+	/*
+	 * Extension registers
+	 * AUX_GENERAL_PURPOSE_LSB_ADDR_1
+	 * AUX_GENERAL_PURPOSE_MSB_ADDR_1
+	 * ARC Address: 0xA000_0000
+	 */
+	ARC_REGION11_GENERAL = 11,
+	/*
+	 * Extension registers
+	 * AUX_GENERAL_PURPOSE_LSB_ADDR_2
+	 * AUX_GENERAL_PURPOSE_MSB_ADDR_2
+	 * ARC Address: 0xB000_0000
+	 */
+	ARC_REGION12_GENERAL = 12,
+	/*
+	 * Extension registers
+	 * AUX_GENERAL_PURPOSE_LSB_ADDR_3
+	 * AUX_GENERAL_PURPOSE_MSB_ADDR_3
+	 * ARC Address: 0xC000_0000
+	 */
+	ARC_REGION13_GENERAL = 13,
+	/*
+	 * Extension registers
+	 * AUX_GENERAL_PURPOSE_LSB_ADDR_4
+	 * AUX_GENERAL_PURPOSE_MSB_ADDR_4
+	 * ARC Address: 0xD000_0000
+	 */
+	ARC_REGION14_GENERAL = 14,
+	/*
+	 * Extension registers
+	 * AUX_GENERAL_PURPOSE_LSB_ADDR_5
+	 * AUX_GENERAL_PURPOSE_MSB_ADDR_5
+	 * ARC Address: 0xE000_0000
+	 */
+	ARC_REGION15_LBU = 15
+	/*
+	 * Extension registers
+	 * None
+	 * ARC Address: 0xF000_0000
+	 */
+};
+
+#endif /* __GAUDI2_ARC_COMMON_PACKETS_H__ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_acp_eng_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_acp_eng_regs.h
new file mode 100644
index 000000000000..1974df13b5f9
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_acp_eng_regs.h
@@ -0,0 +1,567 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_ARC_FARM_ARC0_ACP_ENG_REGS_H_
+#define ASIC_REG_ARC_FARM_ARC0_ACP_ENG_REGS_H_
+
+/*
+ *****************************************
+ *   ARC_FARM_ARC0_ACP_ENG
+ *   (Prototype: ARC_ACP_ENG)
+ *****************************************
+ */
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_0 0x4E8F000
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_1 0x4E8F004
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_2 0x4E8F008
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_3 0x4E8F00C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_4 0x4E8F010
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_5 0x4E8F014
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_6 0x4E8F018
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_7 0x4E8F01C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_8 0x4E8F020
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_9 0x4E8F024
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_10 0x4E8F028
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_11 0x4E8F02C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_12 0x4E8F030
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_13 0x4E8F034
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_14 0x4E8F038
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_15 0x4E8F03C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_16 0x4E8F040
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_17 0x4E8F044
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_18 0x4E8F048
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_19 0x4E8F04C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_20 0x4E8F050
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_21 0x4E8F054
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_22 0x4E8F058
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_23 0x4E8F05C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_24 0x4E8F060
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_25 0x4E8F064
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_26 0x4E8F068
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_27 0x4E8F06C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_28 0x4E8F070
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_29 0x4E8F074
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_30 0x4E8F078
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_31 0x4E8F07C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_32 0x4E8F080
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_33 0x4E8F084
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_34 0x4E8F088
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_35 0x4E8F08C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_36 0x4E8F090
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_37 0x4E8F094
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_38 0x4E8F098
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_39 0x4E8F09C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_40 0x4E8F0A0
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_41 0x4E8F0A4
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_42 0x4E8F0A8
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_43 0x4E8F0AC
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_44 0x4E8F0B0
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_45 0x4E8F0B4
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_46 0x4E8F0B8
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_47 0x4E8F0BC
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_48 0x4E8F0C0
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_49 0x4E8F0C4
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_50 0x4E8F0C8
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_51 0x4E8F0CC
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_52 0x4E8F0D0
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_53 0x4E8F0D4
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_54 0x4E8F0D8
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_55 0x4E8F0DC
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_56 0x4E8F0E0
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_57 0x4E8F0E4
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_58 0x4E8F0E8
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_59 0x4E8F0EC
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_60 0x4E8F0F0
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_61 0x4E8F0F4
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_62 0x4E8F0F8
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_63 0x4E8F0FC
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_0 0x4E8F100
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_1 0x4E8F104
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_2 0x4E8F108
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_3 0x4E8F10C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_4 0x4E8F110
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_5 0x4E8F114
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_6 0x4E8F118
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_7 0x4E8F11C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_8 0x4E8F120
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_9 0x4E8F124
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_10 0x4E8F128
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_11 0x4E8F12C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_12 0x4E8F130
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_13 0x4E8F134
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_14 0x4E8F138
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_15 0x4E8F13C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_16 0x4E8F140
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_17 0x4E8F144
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_18 0x4E8F148
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_19 0x4E8F14C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_20 0x4E8F150
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_21 0x4E8F154
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_22 0x4E8F158
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_23 0x4E8F15C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_24 0x4E8F160
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_25 0x4E8F164
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_26 0x4E8F168
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_27 0x4E8F16C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_28 0x4E8F170
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_29 0x4E8F174
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_30 0x4E8F178
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_31 0x4E8F17C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_32 0x4E8F180
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_33 0x4E8F184
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_34 0x4E8F188
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_35 0x4E8F18C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_36 0x4E8F190
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_37 0x4E8F194
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_38 0x4E8F198
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_39 0x4E8F19C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_40 0x4E8F1A0
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_41 0x4E8F1A4
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_42 0x4E8F1A8
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_43 0x4E8F1AC
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_44 0x4E8F1B0
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_45 0x4E8F1B4
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_46 0x4E8F1B8
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_47 0x4E8F1BC
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_48 0x4E8F1C0
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_49 0x4E8F1C4
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_50 0x4E8F1C8
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_51 0x4E8F1CC
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_52 0x4E8F1D0
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_53 0x4E8F1D4
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_54 0x4E8F1D8
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_55 0x4E8F1DC
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_56 0x4E8F1E0
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_57 0x4E8F1E4
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_58 0x4E8F1E8
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_59 0x4E8F1EC
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_60 0x4E8F1F0
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_61 0x4E8F1F4
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_62 0x4E8F1F8
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_CI_REG_63 0x4E8F1FC
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_0 0x4E8F200
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_1 0x4E8F204
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_2 0x4E8F208
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_3 0x4E8F20C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_4 0x4E8F210
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_5 0x4E8F214
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_6 0x4E8F218
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_7 0x4E8F21C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_8 0x4E8F220
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_9 0x4E8F224
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_10 0x4E8F228
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_11 0x4E8F22C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_12 0x4E8F230
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_13 0x4E8F234
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_14 0x4E8F238
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_15 0x4E8F23C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_16 0x4E8F240
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_17 0x4E8F244
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_18 0x4E8F248
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_19 0x4E8F24C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_20 0x4E8F250
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_21 0x4E8F254
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_22 0x4E8F258
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_23 0x4E8F25C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_24 0x4E8F260
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_25 0x4E8F264
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_26 0x4E8F268
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_27 0x4E8F26C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_28 0x4E8F270
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_29 0x4E8F274
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_30 0x4E8F278
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_31 0x4E8F27C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_32 0x4E8F280
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_33 0x4E8F284
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_34 0x4E8F288
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_35 0x4E8F28C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_36 0x4E8F290
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_37 0x4E8F294
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_38 0x4E8F298
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_39 0x4E8F29C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_40 0x4E8F2A0
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_41 0x4E8F2A4
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_42 0x4E8F2A8
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_43 0x4E8F2AC
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_44 0x4E8F2B0
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_45 0x4E8F2B4
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_46 0x4E8F2B8
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_47 0x4E8F2BC
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_48 0x4E8F2C0
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_49 0x4E8F2C4
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_50 0x4E8F2C8
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_51 0x4E8F2CC
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_52 0x4E8F2D0
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_53 0x4E8F2D4
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_54 0x4E8F2D8
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_55 0x4E8F2DC
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_56 0x4E8F2E0
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_57 0x4E8F2E4
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_58 0x4E8F2E8
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_59 0x4E8F2EC
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_60 0x4E8F2F0
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_61 0x4E8F2F4
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_62 0x4E8F2F8
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_PR_REG_63 0x4E8F2FC
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_0 0x4E8F300
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_1 0x4E8F304
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_2 0x4E8F308
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_3 0x4E8F30C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_4 0x4E8F310
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_5 0x4E8F314
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_6 0x4E8F318
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_7 0x4E8F31C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_8 0x4E8F320
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_9 0x4E8F324
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_10 0x4E8F328
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_11 0x4E8F32C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_12 0x4E8F330
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_13 0x4E8F334
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_14 0x4E8F338
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_15 0x4E8F33C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_16 0x4E8F340
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_17 0x4E8F344
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_18 0x4E8F348
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_19 0x4E8F34C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_20 0x4E8F350
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_21 0x4E8F354
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_22 0x4E8F358
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_23 0x4E8F35C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_24 0x4E8F360
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_25 0x4E8F364
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_26 0x4E8F368
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_27 0x4E8F36C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_28 0x4E8F370
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_29 0x4E8F374
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_30 0x4E8F378
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_31 0x4E8F37C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_32 0x4E8F380
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_33 0x4E8F384
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_34 0x4E8F388
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_35 0x4E8F38C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_36 0x4E8F390
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_37 0x4E8F394
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_38 0x4E8F398
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_39 0x4E8F39C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_40 0x4E8F3A0
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_41 0x4E8F3A4
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_42 0x4E8F3A8
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_43 0x4E8F3AC
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_44 0x4E8F3B0
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_45 0x4E8F3B4
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_46 0x4E8F3B8
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_47 0x4E8F3BC
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_48 0x4E8F3C0
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_49 0x4E8F3C4
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_50 0x4E8F3C8
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_51 0x4E8F3CC
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_52 0x4E8F3D0
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_53 0x4E8F3D4
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_54 0x4E8F3D8
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_55 0x4E8F3DC
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_56 0x4E8F3E0
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_57 0x4E8F3E4
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_58 0x4E8F3E8
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_59 0x4E8F3EC
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_60 0x4E8F3F0
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_61 0x4E8F3F4
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_62 0x4E8F3F8
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_MK_REG_63 0x4E8F3FC
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_SELECTED_QUEUE_ID 0x4E8F400
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_GRANTS_WEIGHT_PRIO_0 0x4E8F404
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_GRANTS_WEIGHT_PRIO_1 0x4E8F408
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_GRANTS_WEIGHT_PRIO_2 0x4E8F40C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_GRANTS_COUNTER_PRIO_0 0x4E8F410
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_GRANTS_COUNTER_PRIO_1 0x4E8F414
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_GRANTS_COUNTER_PRIO_2 0x4E8F418
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_PRIO_OUT_CNT_0 0x4E8F41C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_PRIO_OUT_CNT_1 0x4E8F420
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_PRIO_OUT_CNT_2 0x4E8F424
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_PRIO_OUT_CNT_3 0x4E8F428
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_PRIO_RD_CNT_0 0x4E8F42C
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_PRIO_RD_CNT_1 0x4E8F430
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_PRIO_RD_CNT_2 0x4E8F434
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_PRIO_RD_CNT_3 0x4E8F438
+
+#define mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_REG 0x4E8F43C
+
+#endif /* ASIC_REG_ARC_FARM_ARC0_ACP_ENG_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_aux_masks.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_aux_masks.h
new file mode 100644
index 000000000000..fc2c52af6509
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_aux_masks.h
@@ -0,0 +1,819 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_ARC_FARM_ARC0_AUX_MASKS_H_
+#define ASIC_REG_ARC_FARM_ARC0_AUX_MASKS_H_
+
+/*
+ *****************************************
+ *   ARC_FARM_ARC0_AUX
+ *   (Prototype: QMAN_ARC_AUX)
+ *****************************************
+ */
+
+/* ARC_FARM_ARC0_AUX_RUN_HALT_REQ */
+#define ARC_FARM_ARC0_AUX_RUN_HALT_REQ_RUN_REQ_SHIFT 0
+#define ARC_FARM_ARC0_AUX_RUN_HALT_REQ_RUN_REQ_MASK 0x1
+#define ARC_FARM_ARC0_AUX_RUN_HALT_REQ_HALT_REQ_SHIFT 1
+#define ARC_FARM_ARC0_AUX_RUN_HALT_REQ_HALT_REQ_MASK 0x2
+
+/* ARC_FARM_ARC0_AUX_RUN_HALT_ACK */
+#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_RUN_ACK_SHIFT 0
+#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_RUN_ACK_MASK 0x1
+#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_HALT_ACK_SHIFT 4
+#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_HALT_ACK_MASK 0x10
+#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_HALT_R_SHIFT 8
+#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_HALT_R_MASK 0x100
+#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_TF_HALT_R_SHIFT 12
+#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_TF_HALT_R_MASK 0x1000
+#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_SLEEP_R_SHIFT 16
+#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_SLEEP_R_MASK 0x10000
+#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_SLEEP_MODE_R_SHIFT 17
+#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_SLEEP_MODE_R_MASK 0xE0000
+#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_WATCHDOG_RESET_SHIFT 20
+#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_WATCHDOG_RESET_MASK 0x100000
+
+/* ARC_FARM_ARC0_AUX_RST_VEC_ADDR */
+#define ARC_FARM_ARC0_AUX_RST_VEC_ADDR_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_RST_VEC_ADDR_VAL_MASK 0x3FFFFF
+
+/* ARC_FARM_ARC0_AUX_DBG_MODE */
+#define ARC_FARM_ARC0_AUX_DBG_MODE_DBG_PROT_SEL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_DBG_MODE_DBG_PROT_SEL_MASK 0x1
+#define ARC_FARM_ARC0_AUX_DBG_MODE_DBGEN_SHIFT 4
+#define ARC_FARM_ARC0_AUX_DBG_MODE_DBGEN_MASK 0x10
+#define ARC_FARM_ARC0_AUX_DBG_MODE_NIDEN_SHIFT 8
+#define ARC_FARM_ARC0_AUX_DBG_MODE_NIDEN_MASK 0x100
+#define ARC_FARM_ARC0_AUX_DBG_MODE_CASHE_RST_DISABLE_SHIFT 12
+#define ARC_FARM_ARC0_AUX_DBG_MODE_CASHE_RST_DISABLE_MASK 0x1000
+#define ARC_FARM_ARC0_AUX_DBG_MODE_DDCM_DMI_PRIORITY_SHIFT 16
+#define ARC_FARM_ARC0_AUX_DBG_MODE_DDCM_DMI_PRIORITY_MASK 0x10000
+
+/* ARC_FARM_ARC0_AUX_CLUSTER_NUM */
+#define ARC_FARM_ARC0_AUX_CLUSTER_NUM_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CLUSTER_NUM_VAL_MASK 0xFF
+
+/* ARC_FARM_ARC0_AUX_ARC_NUM */
+#define ARC_FARM_ARC0_AUX_ARC_NUM_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_ARC_NUM_VAL_MASK 0xFF
+
+/* ARC_FARM_ARC0_AUX_WAKE_UP_EVENT */
+#define ARC_FARM_ARC0_AUX_WAKE_UP_EVENT_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_WAKE_UP_EVENT_VAL_MASK 0x1
+
+/* ARC_FARM_ARC0_AUX_DCCM_SYS_ADDR_BASE */
+#define ARC_FARM_ARC0_AUX_DCCM_SYS_ADDR_BASE_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_DCCM_SYS_ADDR_BASE_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_CTI_AP_STS */
+#define ARC_FARM_ARC0_AUX_CTI_AP_STS_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CTI_AP_STS_VAL_MASK 0xFF
+
+/* ARC_FARM_ARC0_AUX_CTI_CFG_MUX_SEL */
+#define ARC_FARM_ARC0_AUX_CTI_CFG_MUX_SEL_RUN_HALT_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CTI_CFG_MUX_SEL_RUN_HALT_MASK 0x1
+
+/* ARC_FARM_ARC0_AUX_ARC_RST */
+#define ARC_FARM_ARC0_AUX_ARC_RST_CORE_SHIFT 0
+#define ARC_FARM_ARC0_AUX_ARC_RST_CORE_MASK 0x1
+#define ARC_FARM_ARC0_AUX_ARC_RST_PRESETDBGN_SHIFT 4
+#define ARC_FARM_ARC0_AUX_ARC_RST_PRESETDBGN_MASK 0x10
+
+/* ARC_FARM_ARC0_AUX_ARC_RST_REQ */
+#define ARC_FARM_ARC0_AUX_ARC_RST_REQ_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_ARC_RST_REQ_VAL_MASK 0x1
+
+/* ARC_FARM_ARC0_AUX_SRAM_LSB_ADDR */
+#define ARC_FARM_ARC0_AUX_SRAM_LSB_ADDR_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_SRAM_LSB_ADDR_VAL_MASK 0x3F
+
+/* ARC_FARM_ARC0_AUX_SRAM_MSB_ADDR */
+#define ARC_FARM_ARC0_AUX_SRAM_MSB_ADDR_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_SRAM_MSB_ADDR_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_PCIE_LSB_ADDR */
+#define ARC_FARM_ARC0_AUX_PCIE_LSB_ADDR_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_PCIE_LSB_ADDR_VAL_MASK 0xF
+
+/* ARC_FARM_ARC0_AUX_PCIE_MSB_ADDR */
+#define ARC_FARM_ARC0_AUX_PCIE_MSB_ADDR_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_PCIE_MSB_ADDR_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_CFG_LSB_ADDR */
+#define ARC_FARM_ARC0_AUX_CFG_LSB_ADDR_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CFG_LSB_ADDR_VAL_MASK 0xF
+
+/* ARC_FARM_ARC0_AUX_CFG_MSB_ADDR */
+#define ARC_FARM_ARC0_AUX_CFG_MSB_ADDR_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CFG_MSB_ADDR_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_HBM0_LSB_ADDR */
+#define ARC_FARM_ARC0_AUX_HBM0_LSB_ADDR_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_HBM0_LSB_ADDR_VAL_MASK 0xF
+
+/* ARC_FARM_ARC0_AUX_HBM0_MSB_ADDR */
+#define ARC_FARM_ARC0_AUX_HBM0_MSB_ADDR_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_HBM0_MSB_ADDR_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_HBM1_LSB_ADDR */
+#define ARC_FARM_ARC0_AUX_HBM1_LSB_ADDR_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_HBM1_LSB_ADDR_VAL_MASK 0xF
+
+/* ARC_FARM_ARC0_AUX_HBM1_MSB_ADDR */
+#define ARC_FARM_ARC0_AUX_HBM1_MSB_ADDR_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_HBM1_MSB_ADDR_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_HBM2_LSB_ADDR */
+#define ARC_FARM_ARC0_AUX_HBM2_LSB_ADDR_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_HBM2_LSB_ADDR_VAL_MASK 0xF
+
+/* ARC_FARM_ARC0_AUX_HBM2_MSB_ADDR */
+#define ARC_FARM_ARC0_AUX_HBM2_MSB_ADDR_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_HBM2_MSB_ADDR_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_HBM3_LSB_ADDR */
+#define ARC_FARM_ARC0_AUX_HBM3_LSB_ADDR_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_HBM3_LSB_ADDR_VAL_MASK 0xF
+
+/* ARC_FARM_ARC0_AUX_HBM3_MSB_ADDR */
+#define ARC_FARM_ARC0_AUX_HBM3_MSB_ADDR_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_HBM3_MSB_ADDR_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_HBM0_OFFSET */
+#define ARC_FARM_ARC0_AUX_HBM0_OFFSET_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_HBM0_OFFSET_VAL_MASK 0xFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_HBM1_OFFSET */
+#define ARC_FARM_ARC0_AUX_HBM1_OFFSET_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_HBM1_OFFSET_VAL_MASK 0xFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_HBM2_OFFSET */
+#define ARC_FARM_ARC0_AUX_HBM2_OFFSET_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_HBM2_OFFSET_VAL_MASK 0xFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_HBM3_OFFSET */
+#define ARC_FARM_ARC0_AUX_HBM3_OFFSET_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_HBM3_OFFSET_VAL_MASK 0xFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_GENERAL_PURPOSE_LSB_ADDR */
+#define ARC_FARM_ARC0_AUX_GENERAL_PURPOSE_LSB_ADDR_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_GENERAL_PURPOSE_LSB_ADDR_VAL_MASK 0xF
+
+/* ARC_FARM_ARC0_AUX_GENERAL_PURPOSE_MSB_ADDR */
+#define ARC_FARM_ARC0_AUX_GENERAL_PURPOSE_MSB_ADDR_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_GENERAL_PURPOSE_MSB_ADDR_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_ARC_CBU_AWCACHE_OVR */
+#define ARC_FARM_ARC0_AUX_ARC_CBU_AWCACHE_OVR_AXI_WRITE_SHIFT 0
+#define ARC_FARM_ARC0_AUX_ARC_CBU_AWCACHE_OVR_AXI_WRITE_MASK 0xF
+#define ARC_FARM_ARC0_AUX_ARC_CBU_AWCACHE_OVR_AXI_WRITE_EN_SHIFT 4
+#define ARC_FARM_ARC0_AUX_ARC_CBU_AWCACHE_OVR_AXI_WRITE_EN_MASK 0xF0
+
+/* ARC_FARM_ARC0_AUX_ARC_LBU_AWCACHE_OVR */
+#define ARC_FARM_ARC0_AUX_ARC_LBU_AWCACHE_OVR_AXI_WRITE_SHIFT 0
+#define ARC_FARM_ARC0_AUX_ARC_LBU_AWCACHE_OVR_AXI_WRITE_MASK 0xF
+#define ARC_FARM_ARC0_AUX_ARC_LBU_AWCACHE_OVR_AXI_WRITE_EN_SHIFT 4
+#define ARC_FARM_ARC0_AUX_ARC_LBU_AWCACHE_OVR_AXI_WRITE_EN_MASK 0xF0
+
+/* ARC_FARM_ARC0_AUX_CONTEXT_ID */
+#define ARC_FARM_ARC0_AUX_CONTEXT_ID_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CONTEXT_ID_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_CID_OFFSET */
+#define ARC_FARM_ARC0_AUX_CID_OFFSET_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CID_OFFSET_VAL_MASK 0xFF
+
+/* ARC_FARM_ARC0_AUX_SW_INTR */
+#define ARC_FARM_ARC0_AUX_SW_INTR_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_SW_INTR_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_IRQ_INTR_MASK */
+#define ARC_FARM_ARC0_AUX_IRQ_INTR_MASK_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_IRQ_INTR_MASK_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_ARC_SEI_INTR_STS */
+#define ARC_FARM_ARC0_AUX_ARC_SEI_INTR_STS_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_ARC_SEI_INTR_STS_VAL_MASK 0x3FFF
+
+/* ARC_FARM_ARC0_AUX_ARC_SEI_INTR_CLR */
+#define ARC_FARM_ARC0_AUX_ARC_SEI_INTR_CLR_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_ARC_SEI_INTR_CLR_VAL_MASK 0x3FFF
+
+/* ARC_FARM_ARC0_AUX_ARC_SEI_INTR_MASK */
+#define ARC_FARM_ARC0_AUX_ARC_SEI_INTR_MASK_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_ARC_SEI_INTR_MASK_VAL_MASK 0x3FFF
+
+/* ARC_FARM_ARC0_AUX_ARC_EXCPTN_CAUSE */
+#define ARC_FARM_ARC0_AUX_ARC_EXCPTN_CAUSE_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_ARC_EXCPTN_CAUSE_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_SEI_INTR_HALT_EN */
+#define ARC_FARM_ARC0_AUX_SEI_INTR_HALT_EN_INTR_EN_SHIFT 0
+#define ARC_FARM_ARC0_AUX_SEI_INTR_HALT_EN_INTR_EN_MASK 0x1
+#define ARC_FARM_ARC0_AUX_SEI_INTR_HALT_EN_HALT_EN_SHIFT 1
+#define ARC_FARM_ARC0_AUX_SEI_INTR_HALT_EN_HALT_EN_MASK 0x2
+
+/* ARC_FARM_ARC0_AUX_ARC_SEI_INTR_HALT_MASK */
+#define ARC_FARM_ARC0_AUX_ARC_SEI_INTR_HALT_MASK_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_ARC_SEI_INTR_HALT_MASK_VAL_MASK 0x3FFF
+
+/* ARC_FARM_ARC0_AUX_QMAN_SEI_INTR_HALT_MASK */
+#define ARC_FARM_ARC0_AUX_QMAN_SEI_INTR_HALT_MASK_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_QMAN_SEI_INTR_HALT_MASK_VAL_MASK 0x3FFF
+
+/* ARC_FARM_ARC0_AUX_ARC_REI_INTR_STS */
+#define ARC_FARM_ARC0_AUX_ARC_REI_INTR_STS_SERR_SHIFT 0
+#define ARC_FARM_ARC0_AUX_ARC_REI_INTR_STS_SERR_MASK 0x1
+#define ARC_FARM_ARC0_AUX_ARC_REI_INTR_STS_DERR_SHIFT 1
+#define ARC_FARM_ARC0_AUX_ARC_REI_INTR_STS_DERR_MASK 0x2
+
+/* ARC_FARM_ARC0_AUX_ARC_REI_INTR_CLR */
+#define ARC_FARM_ARC0_AUX_ARC_REI_INTR_CLR_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_ARC_REI_INTR_CLR_VAL_MASK 0x3
+
+/* ARC_FARM_ARC0_AUX_ARC_REI_INTR_MASK */
+#define ARC_FARM_ARC0_AUX_ARC_REI_INTR_MASK_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_ARC_REI_INTR_MASK_VAL_MASK 0x3
+
+/* ARC_FARM_ARC0_AUX_DCCM_ECC_ERR_ADDR */
+#define ARC_FARM_ARC0_AUX_DCCM_ECC_ERR_ADDR_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_DCCM_ECC_ERR_ADDR_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_DCCM_ECC_SYNDROME */
+#define ARC_FARM_ARC0_AUX_DCCM_ECC_SYNDROME_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_DCCM_ECC_SYNDROME_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_I_CACHE_ECC_ERR_ADDR */
+#define ARC_FARM_ARC0_AUX_I_CACHE_ECC_ERR_ADDR_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_I_CACHE_ECC_ERR_ADDR_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_I_CACHE_ECC_SYNDROME */
+#define ARC_FARM_ARC0_AUX_I_CACHE_ECC_SYNDROME_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_I_CACHE_ECC_SYNDROME_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_D_CACHE_ECC_ERR_ADDR */
+#define ARC_FARM_ARC0_AUX_D_CACHE_ECC_ERR_ADDR_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_D_CACHE_ECC_ERR_ADDR_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_D_CACHE_ECC_SYNDROME */
+#define ARC_FARM_ARC0_AUX_D_CACHE_ECC_SYNDROME_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_D_CACHE_ECC_SYNDROME_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_LBW_TRMINATE_AWADDR_ERR */
+#define ARC_FARM_ARC0_AUX_LBW_TRMINATE_AWADDR_ERR_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_LBW_TRMINATE_AWADDR_ERR_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_LBW_TRMINATE_ARADDR_ERR */
+#define ARC_FARM_ARC0_AUX_LBW_TRMINATE_ARADDR_ERR_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_LBW_TRMINATE_ARADDR_ERR_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_BRESP */
+#define ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_BRESP_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_BRESP_VAL_MASK 0x3
+
+/* ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_RRESP */
+#define ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_RRESP_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_RRESP_VAL_MASK 0x3
+
+/* ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_AXLEN */
+#define ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_AXLEN_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_AXLEN_VAL_MASK 0xFF
+
+/* ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_AXSIZE */
+#define ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_AXSIZE_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_AXSIZE_VAL_MASK 0x7
+
+/* ARC_FARM_ARC0_AUX_SCRATCHPAD */
+#define ARC_FARM_ARC0_AUX_SCRATCHPAD_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_SCRATCHPAD_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_TOTAL_CBU_WR_CNT */
+#define ARC_FARM_ARC0_AUX_TOTAL_CBU_WR_CNT_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_TOTAL_CBU_WR_CNT_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_INFLIGHT_CBU_WR_CNT */
+#define ARC_FARM_ARC0_AUX_INFLIGHT_CBU_WR_CNT_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_INFLIGHT_CBU_WR_CNT_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_TOTAL_CBU_RD_CNT */
+#define ARC_FARM_ARC0_AUX_TOTAL_CBU_RD_CNT_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_TOTAL_CBU_RD_CNT_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_INFLIGHT_CBU_RD_CNT */
+#define ARC_FARM_ARC0_AUX_INFLIGHT_CBU_RD_CNT_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_INFLIGHT_CBU_RD_CNT_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_TOTAL_LBU_WR_CNT */
+#define ARC_FARM_ARC0_AUX_TOTAL_LBU_WR_CNT_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_TOTAL_LBU_WR_CNT_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_INFLIGHT_LBU_WR_CNT */
+#define ARC_FARM_ARC0_AUX_INFLIGHT_LBU_WR_CNT_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_INFLIGHT_LBU_WR_CNT_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_TOTAL_LBU_RD_CNT */
+#define ARC_FARM_ARC0_AUX_TOTAL_LBU_RD_CNT_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_TOTAL_LBU_RD_CNT_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_INFLIGHT_LBU_RD_CNT */
+#define ARC_FARM_ARC0_AUX_INFLIGHT_LBU_RD_CNT_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_INFLIGHT_LBU_RD_CNT_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_CBU_ARUSER_OVR */
+#define ARC_FARM_ARC0_AUX_CBU_ARUSER_OVR_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CBU_ARUSER_OVR_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_CBU_ARUSER_OVR_EN */
+#define ARC_FARM_ARC0_AUX_CBU_ARUSER_OVR_EN_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CBU_ARUSER_OVR_EN_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_CBU_AWUSER_OVR */
+#define ARC_FARM_ARC0_AUX_CBU_AWUSER_OVR_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CBU_AWUSER_OVR_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_CBU_AWUSER_OVR_EN */
+#define ARC_FARM_ARC0_AUX_CBU_AWUSER_OVR_EN_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CBU_AWUSER_OVR_EN_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_CBU_ARUSER_MSB_OVR */
+#define ARC_FARM_ARC0_AUX_CBU_ARUSER_MSB_OVR_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CBU_ARUSER_MSB_OVR_VAL_MASK 0x3FF
+
+/* ARC_FARM_ARC0_AUX_CBU_ARUSER_MSB_OVR_EN */
+#define ARC_FARM_ARC0_AUX_CBU_ARUSER_MSB_OVR_EN_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CBU_ARUSER_MSB_OVR_EN_VAL_MASK 0x3FF
+
+/* ARC_FARM_ARC0_AUX_CBU_AWUSER_MSB_OVR */
+#define ARC_FARM_ARC0_AUX_CBU_AWUSER_MSB_OVR_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CBU_AWUSER_MSB_OVR_VAL_MASK 0x3FF
+
+/* ARC_FARM_ARC0_AUX_CBU_AWUSER_MSB_OVR_EN */
+#define ARC_FARM_ARC0_AUX_CBU_AWUSER_MSB_OVR_EN_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CBU_AWUSER_MSB_OVR_EN_VAL_MASK 0x3FF
+
+/* ARC_FARM_ARC0_AUX_CBU_AXCACHE_OVR */
+#define ARC_FARM_ARC0_AUX_CBU_AXCACHE_OVR_CBU_READ_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CBU_AXCACHE_OVR_CBU_READ_MASK 0xF
+#define ARC_FARM_ARC0_AUX_CBU_AXCACHE_OVR_CBU_WRITE_SHIFT 4
+#define ARC_FARM_ARC0_AUX_CBU_AXCACHE_OVR_CBU_WRITE_MASK 0xF0
+#define ARC_FARM_ARC0_AUX_CBU_AXCACHE_OVR_CBU_RD_EN_SHIFT 8
+#define ARC_FARM_ARC0_AUX_CBU_AXCACHE_OVR_CBU_RD_EN_MASK 0xF00
+#define ARC_FARM_ARC0_AUX_CBU_AXCACHE_OVR_CBU_WR_EN_SHIFT 12
+#define ARC_FARM_ARC0_AUX_CBU_AXCACHE_OVR_CBU_WR_EN_MASK 0xF000
+
+/* ARC_FARM_ARC0_AUX_CBU_LOCK_OVR */
+#define ARC_FARM_ARC0_AUX_CBU_LOCK_OVR_CBU_READ_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CBU_LOCK_OVR_CBU_READ_MASK 0x3
+#define ARC_FARM_ARC0_AUX_CBU_LOCK_OVR_CBU_WRITE_SHIFT 4
+#define ARC_FARM_ARC0_AUX_CBU_LOCK_OVR_CBU_WRITE_MASK 0x30
+#define ARC_FARM_ARC0_AUX_CBU_LOCK_OVR_CBU_RD_EN_SHIFT 8
+#define ARC_FARM_ARC0_AUX_CBU_LOCK_OVR_CBU_RD_EN_MASK 0x300
+#define ARC_FARM_ARC0_AUX_CBU_LOCK_OVR_CBU_WR_EN_SHIFT 12
+#define ARC_FARM_ARC0_AUX_CBU_LOCK_OVR_CBU_WR_EN_MASK 0x3000
+
+/* ARC_FARM_ARC0_AUX_CBU_PROT_OVR */
+#define ARC_FARM_ARC0_AUX_CBU_PROT_OVR_CBU_READ_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CBU_PROT_OVR_CBU_READ_MASK 0x7
+#define ARC_FARM_ARC0_AUX_CBU_PROT_OVR_CBU_WRITE_SHIFT 4
+#define ARC_FARM_ARC0_AUX_CBU_PROT_OVR_CBU_WRITE_MASK 0x70
+#define ARC_FARM_ARC0_AUX_CBU_PROT_OVR_CBU_RD_EN_SHIFT 8
+#define ARC_FARM_ARC0_AUX_CBU_PROT_OVR_CBU_RD_EN_MASK 0x700
+#define ARC_FARM_ARC0_AUX_CBU_PROT_OVR_CBU_WR_EN_SHIFT 12
+#define ARC_FARM_ARC0_AUX_CBU_PROT_OVR_CBU_WR_EN_MASK 0x7000
+
+/* ARC_FARM_ARC0_AUX_CBU_MAX_OUTSTANDING */
+#define ARC_FARM_ARC0_AUX_CBU_MAX_OUTSTANDING_CBU_READ_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CBU_MAX_OUTSTANDING_CBU_READ_MASK 0xFF
+#define ARC_FARM_ARC0_AUX_CBU_MAX_OUTSTANDING_CBU_WRITE_SHIFT 8
+#define ARC_FARM_ARC0_AUX_CBU_MAX_OUTSTANDING_CBU_WRITE_MASK 0xFF00
+
+/* ARC_FARM_ARC0_AUX_CBU_EARLY_BRESP_EN */
+#define ARC_FARM_ARC0_AUX_CBU_EARLY_BRESP_EN_CBU_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CBU_EARLY_BRESP_EN_CBU_VAL_MASK 0x1
+
+/* ARC_FARM_ARC0_AUX_CBU_FORCE_RSP_OK */
+#define ARC_FARM_ARC0_AUX_CBU_FORCE_RSP_OK_CBU_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CBU_FORCE_RSP_OK_CBU_VAL_MASK 0x1
+
+/* ARC_FARM_ARC0_AUX_CBU_NO_WR_INFLIGHT */
+#define ARC_FARM_ARC0_AUX_CBU_NO_WR_INFLIGHT_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CBU_NO_WR_INFLIGHT_VAL_MASK 0x1
+
+/* ARC_FARM_ARC0_AUX_CBU_SEI_INTR_ID */
+#define ARC_FARM_ARC0_AUX_CBU_SEI_INTR_ID_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CBU_SEI_INTR_ID_VAL_MASK 0x7F
+
+/* ARC_FARM_ARC0_AUX_LBU_ARUSER_OVR */
+#define ARC_FARM_ARC0_AUX_LBU_ARUSER_OVR_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_LBU_ARUSER_OVR_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_LBU_ARUSER_OVR_EN */
+#define ARC_FARM_ARC0_AUX_LBU_ARUSER_OVR_EN_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_LBU_ARUSER_OVR_EN_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_LBU_AWUSER_OVR */
+#define ARC_FARM_ARC0_AUX_LBU_AWUSER_OVR_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_LBU_AWUSER_OVR_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_LBU_AWUSER_OVR_EN */
+#define ARC_FARM_ARC0_AUX_LBU_AWUSER_OVR_EN_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_LBU_AWUSER_OVR_EN_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_LBU_AXCACHE_OVR */
+#define ARC_FARM_ARC0_AUX_LBU_AXCACHE_OVR_LBU_READ_SHIFT 0
+#define ARC_FARM_ARC0_AUX_LBU_AXCACHE_OVR_LBU_READ_MASK 0xF
+#define ARC_FARM_ARC0_AUX_LBU_AXCACHE_OVR_LBU_WRITE_SHIFT 4
+#define ARC_FARM_ARC0_AUX_LBU_AXCACHE_OVR_LBU_WRITE_MASK 0xF0
+#define ARC_FARM_ARC0_AUX_LBU_AXCACHE_OVR_LBU_RD_EN_SHIFT 8
+#define ARC_FARM_ARC0_AUX_LBU_AXCACHE_OVR_LBU_RD_EN_MASK 0xF00
+#define ARC_FARM_ARC0_AUX_LBU_AXCACHE_OVR_LBU_WR_EN_SHIFT 12
+#define ARC_FARM_ARC0_AUX_LBU_AXCACHE_OVR_LBU_WR_EN_MASK 0xF000
+
+/* ARC_FARM_ARC0_AUX_LBU_LOCK_OVR */
+#define ARC_FARM_ARC0_AUX_LBU_LOCK_OVR_LBU_READ_SHIFT 0
+#define ARC_FARM_ARC0_AUX_LBU_LOCK_OVR_LBU_READ_MASK 0x3
+#define ARC_FARM_ARC0_AUX_LBU_LOCK_OVR_LBU_WRITE_SHIFT 4
+#define ARC_FARM_ARC0_AUX_LBU_LOCK_OVR_LBU_WRITE_MASK 0x30
+#define ARC_FARM_ARC0_AUX_LBU_LOCK_OVR_LBU_RD_EN_SHIFT 8
+#define ARC_FARM_ARC0_AUX_LBU_LOCK_OVR_LBU_RD_EN_MASK 0x300
+#define ARC_FARM_ARC0_AUX_LBU_LOCK_OVR_LBU_WR_EN_SHIFT 12
+#define ARC_FARM_ARC0_AUX_LBU_LOCK_OVR_LBU_WR_EN_MASK 0x3000
+
+/* ARC_FARM_ARC0_AUX_LBU_PROT_OVR */
+#define ARC_FARM_ARC0_AUX_LBU_PROT_OVR_LBU_READ_SHIFT 0
+#define ARC_FARM_ARC0_AUX_LBU_PROT_OVR_LBU_READ_MASK 0x7
+#define ARC_FARM_ARC0_AUX_LBU_PROT_OVR_LBU_WRITE_SHIFT 4
+#define ARC_FARM_ARC0_AUX_LBU_PROT_OVR_LBU_WRITE_MASK 0x70
+#define ARC_FARM_ARC0_AUX_LBU_PROT_OVR_LBU_RD_EN_SHIFT 8
+#define ARC_FARM_ARC0_AUX_LBU_PROT_OVR_LBU_RD_EN_MASK 0x700
+#define ARC_FARM_ARC0_AUX_LBU_PROT_OVR_LBU_WR_EN_SHIFT 12
+#define ARC_FARM_ARC0_AUX_LBU_PROT_OVR_LBU_WR_EN_MASK 0x7000
+
+/* ARC_FARM_ARC0_AUX_LBU_MAX_OUTSTANDING */
+#define ARC_FARM_ARC0_AUX_LBU_MAX_OUTSTANDING_LBU_READ_SHIFT 0
+#define ARC_FARM_ARC0_AUX_LBU_MAX_OUTSTANDING_LBU_READ_MASK 0xFF
+#define ARC_FARM_ARC0_AUX_LBU_MAX_OUTSTANDING_LBU_WRITE_SHIFT 8
+#define ARC_FARM_ARC0_AUX_LBU_MAX_OUTSTANDING_LBU_WRITE_MASK 0xFF00
+
+/* ARC_FARM_ARC0_AUX_LBU_EARLY_BRESP_EN */
+#define ARC_FARM_ARC0_AUX_LBU_EARLY_BRESP_EN_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_LBU_EARLY_BRESP_EN_VAL_MASK 0x1
+
+/* ARC_FARM_ARC0_AUX_LBU_FORCE_RSP_OK */
+#define ARC_FARM_ARC0_AUX_LBU_FORCE_RSP_OK_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_LBU_FORCE_RSP_OK_VAL_MASK 0x1
+
+/* ARC_FARM_ARC0_AUX_LBU_NO_WR_INFLIGHT */
+#define ARC_FARM_ARC0_AUX_LBU_NO_WR_INFLIGHT_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_LBU_NO_WR_INFLIGHT_VAL_MASK 0x1
+
+/* ARC_FARM_ARC0_AUX_LBU_SEI_INTR_ID */
+#define ARC_FARM_ARC0_AUX_LBU_SEI_INTR_ID_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_LBU_SEI_INTR_ID_VAL_MASK 0x3FF
+
+/* ARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR */
+#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR_VAL_MASK 0xFFFFFF
+
+/* ARC_FARM_ARC0_AUX_DCCM_QUEUE_SIZE */
+#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_SIZE_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_SIZE_VAL_MASK 0xFFFFFF
+
+/* ARC_FARM_ARC0_AUX_DCCM_QUEUE_PI */
+#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_PI_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_PI_VAL_MASK 0xFFFFFF
+
+/* ARC_FARM_ARC0_AUX_DCCM_QUEUE_CI */
+#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_CI_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_CI_VAL_MASK 0xFFFFFF
+
+/* ARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG */
+#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_DCCM_QUEUE_MAX_OCCUPANCY */
+#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_MAX_OCCUPANCY_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_MAX_OCCUPANCY_VAL_MASK 0xFFFFFF
+
+/* ARC_FARM_ARC0_AUX_DCCM_QUEUE_VALID_ENTRIES */
+#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_VALID_ENTRIES_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_VALID_ENTRIES_VAL_MASK 0xFFFFFF
+
+/* ARC_FARM_ARC0_AUX_GENERAL_Q_VLD_ENTRY_MASK */
+#define ARC_FARM_ARC0_AUX_GENERAL_Q_VLD_ENTRY_MASK_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_GENERAL_Q_VLD_ENTRY_MASK_VAL_MASK 0xFF
+
+/* ARC_FARM_ARC0_AUX_NIC_Q_VLD_ENTRY_MASK */
+#define ARC_FARM_ARC0_AUX_NIC_Q_VLD_ENTRY_MASK_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_NIC_Q_VLD_ENTRY_MASK_VAL_MASK 0xFF
+
+/* ARC_FARM_ARC0_AUX_DCCM_QUEUE_DROP_EN */
+#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_DROP_EN_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_DROP_EN_VAL_MASK 0x1
+
+/* ARC_FARM_ARC0_AUX_DCCM_QUEUE_WARN_MSG */
+#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_WARN_MSG_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_WARN_MSG_VAL_MASK 0xFFFF
+
+/* ARC_FARM_ARC0_AUX_DCCM_QUEUE_ALERT_MSG */
+#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_ALERT_MSG_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_DCCM_QUEUE_ALERT_MSG_VAL_MASK 0xFFFF
+
+/* ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWPROT */
+#define ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWPROT_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWPROT_VAL_MASK 0x7
+
+/* ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWUSER */
+#define ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWUSER_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWUSER_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWBURST */
+#define ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWBURST_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWBURST_VAL_MASK 0x3
+
+/* ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWLOCK */
+#define ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWLOCK_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWLOCK_VAL_MASK 0x1
+
+/* ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWCACHE */
+#define ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWCACHE_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWCACHE_VAL_MASK 0xF
+
+/* ARC_FARM_ARC0_AUX_DCCM_WRR_ARB_WEIGHT */
+#define ARC_FARM_ARC0_AUX_DCCM_WRR_ARB_WEIGHT_LBW_SLV_AXI_SHIFT 0
+#define ARC_FARM_ARC0_AUX_DCCM_WRR_ARB_WEIGHT_LBW_SLV_AXI_MASK 0xF
+#define ARC_FARM_ARC0_AUX_DCCM_WRR_ARB_WEIGHT_GEN_AXI_SHIFT 4
+#define ARC_FARM_ARC0_AUX_DCCM_WRR_ARB_WEIGHT_GEN_AXI_MASK 0xF0
+
+/* ARC_FARM_ARC0_AUX_DCCM_Q_PUSH_FIFO_FULL_CFG */
+#define ARC_FARM_ARC0_AUX_DCCM_Q_PUSH_FIFO_FULL_CFG_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_DCCM_Q_PUSH_FIFO_FULL_CFG_VAL_MASK 0x1F
+
+/* ARC_FARM_ARC0_AUX_DCCM_Q_PUSH_FIFO_CNT */
+#define ARC_FARM_ARC0_AUX_DCCM_Q_PUSH_FIFO_CNT_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_DCCM_Q_PUSH_FIFO_CNT_VAL_MASK 0x1F
+
+/* ARC_FARM_ARC0_AUX_QMAN_CQ_IFIFO_SHADOW_CI */
+#define ARC_FARM_ARC0_AUX_QMAN_CQ_IFIFO_SHADOW_CI_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_QMAN_CQ_IFIFO_SHADOW_CI_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_QMAN_ARC_CQ_IFIFO_SHADOW_CI */
+#define ARC_FARM_ARC0_AUX_QMAN_ARC_CQ_IFIFO_SHADOW_CI_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_QMAN_ARC_CQ_IFIFO_SHADOW_CI_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_QMAN_CQ_SHADOW_CI */
+#define ARC_FARM_ARC0_AUX_QMAN_CQ_SHADOW_CI_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_QMAN_CQ_SHADOW_CI_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_QMAN_ARC_CQ_SHADOW_CI */
+#define ARC_FARM_ARC0_AUX_QMAN_ARC_CQ_SHADOW_CI_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_QMAN_ARC_CQ_SHADOW_CI_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_AUX2APB_PROT */
+#define ARC_FARM_ARC0_AUX_AUX2APB_PROT_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_AUX2APB_PROT_VAL_MASK 0x7
+
+/* ARC_FARM_ARC0_AUX_LBW_FORK_WIN_EN */
+#define ARC_FARM_ARC0_AUX_LBW_FORK_WIN_EN_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_LBW_FORK_WIN_EN_VAL_MASK 0x3
+
+/* ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_BASE_ADDR0 */
+#define ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_BASE_ADDR0_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_BASE_ADDR0_VAL_MASK 0x7FFFFFF
+
+/* ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_ADDR_MASK0 */
+#define ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_ADDR_MASK0_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_ADDR_MASK0_VAL_MASK 0x7FFFFFF
+
+/* ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_BASE_ADDR1 */
+#define ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_BASE_ADDR1_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_BASE_ADDR1_VAL_MASK 0x7FFFFFF
+
+/* ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_ADDR_MASK1 */
+#define ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_ADDR_MASK1_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_QMAN_LBW_FORK_ADDR_MASK1_VAL_MASK 0x7FFFFFF
+
+/* ARC_FARM_ARC0_AUX_FARM_LBW_FORK_BASE_ADDR0 */
+#define ARC_FARM_ARC0_AUX_FARM_LBW_FORK_BASE_ADDR0_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_FARM_LBW_FORK_BASE_ADDR0_VAL_MASK 0x7FFFFFF
+
+/* ARC_FARM_ARC0_AUX_FARM_LBW_FORK_ADDR_MASK0 */
+#define ARC_FARM_ARC0_AUX_FARM_LBW_FORK_ADDR_MASK0_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_FARM_LBW_FORK_ADDR_MASK0_VAL_MASK 0x7FFFFFF
+
+/* ARC_FARM_ARC0_AUX_FARM_LBW_FORK_BASE_ADDR1 */
+#define ARC_FARM_ARC0_AUX_FARM_LBW_FORK_BASE_ADDR1_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_FARM_LBW_FORK_BASE_ADDR1_VAL_MASK 0x7FFFFFF
+
+/* ARC_FARM_ARC0_AUX_FARM_LBW_FORK_ADDR_MASK1 */
+#define ARC_FARM_ARC0_AUX_FARM_LBW_FORK_ADDR_MASK1_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_FARM_LBW_FORK_ADDR_MASK1_VAL_MASK 0x7FFFFFF
+
+/* ARC_FARM_ARC0_AUX_LBW_APB_FORK_MAX_ADDR0 */
+#define ARC_FARM_ARC0_AUX_LBW_APB_FORK_MAX_ADDR0_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_LBW_APB_FORK_MAX_ADDR0_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_LBW_APB_FORK_MAX_ADDR1 */
+#define ARC_FARM_ARC0_AUX_LBW_APB_FORK_MAX_ADDR1_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_LBW_APB_FORK_MAX_ADDR1_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_ARC_ACC_ENGS_LBW_FORK_MASK */
+#define ARC_FARM_ARC0_AUX_ARC_ACC_ENGS_LBW_FORK_MASK_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_ARC_ACC_ENGS_LBW_FORK_MASK_VAL_MASK 0x7FFFFFF
+
+/* ARC_FARM_ARC0_AUX_ARC_DUP_ENG_LBW_FORK_ADDR */
+#define ARC_FARM_ARC0_AUX_ARC_DUP_ENG_LBW_FORK_ADDR_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_ARC_DUP_ENG_LBW_FORK_ADDR_VAL_MASK 0x7FFFFFF
+
+/* ARC_FARM_ARC0_AUX_ARC_ACP_ENG_LBW_FORK_ADDR */
+#define ARC_FARM_ARC0_AUX_ARC_ACP_ENG_LBW_FORK_ADDR_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_ARC_ACP_ENG_LBW_FORK_ADDR_VAL_MASK 0x7FFFFFF
+
+/* ARC_FARM_ARC0_AUX_ARC_ACC_ENGS_VIRTUAL_ADDR */
+#define ARC_FARM_ARC0_AUX_ARC_ACC_ENGS_VIRTUAL_ADDR_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_ARC_ACC_ENGS_VIRTUAL_ADDR_VAL_MASK 0x7FFFFFF
+
+/* ARC_FARM_ARC0_AUX_CBU_FORK_WIN_EN */
+#define ARC_FARM_ARC0_AUX_CBU_FORK_WIN_EN_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CBU_FORK_WIN_EN_VAL_MASK 0xF
+
+/* ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR0_LSB */
+#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR0_LSB_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR0_LSB_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR0_MSB */
+#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR0_MSB_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR0_MSB_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK0_LSB */
+#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK0_LSB_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK0_LSB_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK0_MSB */
+#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK0_MSB_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK0_MSB_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR1_LSB */
+#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR1_LSB_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR1_LSB_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR1_MSB */
+#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR1_MSB_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR1_MSB_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK1_LSB */
+#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK1_LSB_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK1_LSB_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK1_MSB */
+#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK1_MSB_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK1_MSB_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR2_LSB */
+#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR2_LSB_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR2_LSB_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR2_MSB */
+#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR2_MSB_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR2_MSB_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK2_LSB */
+#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK2_LSB_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK2_LSB_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK2_MSB */
+#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK2_MSB_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK2_MSB_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR3_LSB */
+#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR3_LSB_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR3_LSB_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR3_MSB */
+#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR3_MSB_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR3_MSB_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK3_LSB */
+#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK3_LSB_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK3_LSB_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK3_MSB */
+#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK3_MSB_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK3_MSB_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_CBU_TRMINATE_ARADDR_LSB */
+#define ARC_FARM_ARC0_AUX_CBU_TRMINATE_ARADDR_LSB_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CBU_TRMINATE_ARADDR_LSB_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_CBU_TRMINATE_ARADDR_MSB */
+#define ARC_FARM_ARC0_AUX_CBU_TRMINATE_ARADDR_MSB_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CBU_TRMINATE_ARADDR_MSB_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_CFG_CBU_TERMINATE_BRESP */
+#define ARC_FARM_ARC0_AUX_CFG_CBU_TERMINATE_BRESP_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CFG_CBU_TERMINATE_BRESP_VAL_MASK 0x3
+
+/* ARC_FARM_ARC0_AUX_CFG_CBU_TERMINATE_RRESP */
+#define ARC_FARM_ARC0_AUX_CFG_CBU_TERMINATE_RRESP_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CFG_CBU_TERMINATE_RRESP_VAL_MASK 0x3
+
+/* ARC_FARM_ARC0_AUX_ARC_REGION_CFG */
+#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_0_ASID_SHIFT 0
+#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_0_ASID_MASK 0x3FF
+#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_1_ASID_SHIFT 0
+#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_1_ASID_MASK 0x3FF
+#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_2_ASID_SHIFT 0
+#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_2_ASID_MASK 0x3FF
+#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_3_ASID_SHIFT 0
+#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_3_ASID_MASK 0x3FF
+#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_4_ASID_SHIFT 0
+#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_4_ASID_MASK 0x3FF
+#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_5_ASID_SHIFT 0
+#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_5_ASID_MASK 0x3FF
+#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_6_ASID_SHIFT 0
+#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_6_ASID_MASK 0x3FF
+#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_7_ASID_SHIFT 0
+#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_7_ASID_MASK 0x3FF
+#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_8_ASID_SHIFT 0
+#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_8_ASID_MASK 0x3FF
+#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_9_ASID_SHIFT 0
+#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_9_ASID_MASK 0x3FF
+#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_10_ASID_SHIFT 0
+#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_10_ASID_MASK 0x3FF
+#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_11_ASID_SHIFT 0
+#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_11_ASID_MASK 0x3FF
+#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_12_ASID_SHIFT 0
+#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_12_ASID_MASK 0x3FF
+#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_13_ASID_SHIFT 0
+#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_13_ASID_MASK 0x3FF
+#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_14_ASID_SHIFT 0
+#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_14_ASID_MASK 0x3FF
+#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_15_ASID_SHIFT 0
+#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_15_ASID_MASK 0x3FF
+#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_MMU_BP_SHIFT 12
+#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_MMU_BP_MASK 0x1000
+#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_PROT_VAL_SHIFT 16
+#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_PROT_VAL_MASK 0x70000
+#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_PROT_VAL_EN_SHIFT 20
+#define ARC_FARM_ARC0_AUX_ARC_REGION_CFG_PROT_VAL_EN_MASK 0x700000
+
+/* ARC_FARM_ARC0_AUX_DCCM_TRMINATE_AWADDR_ERR */
+#define ARC_FARM_ARC0_AUX_DCCM_TRMINATE_AWADDR_ERR_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_DCCM_TRMINATE_AWADDR_ERR_VAL_MASK 0xFFFFFF
+
+/* ARC_FARM_ARC0_AUX_DCCM_TRMINATE_ARADDR_ERR */
+#define ARC_FARM_ARC0_AUX_DCCM_TRMINATE_ARADDR_ERR_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_DCCM_TRMINATE_ARADDR_ERR_VAL_MASK 0xFFFFFF
+
+/* ARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_BRESP */
+#define ARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_BRESP_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_BRESP_VAL_MASK 0x3
+
+/* ARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_RRESP */
+#define ARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_RRESP_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_RRESP_VAL_MASK 0x3
+
+/* ARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_EN */
+#define ARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_EN_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_EN_VAL_MASK 0x1
+
+/* ARC_FARM_ARC0_AUX_CFG_DCCM_SECURE_REGION */
+#define ARC_FARM_ARC0_AUX_CFG_DCCM_SECURE_REGION_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_CFG_DCCM_SECURE_REGION_VAL_MASK 0xFFFFFF
+
+/* ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_WR_IF_CNT */
+#define ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_WR_IF_CNT_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_WR_IF_CNT_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_CTL */
+#define ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_CTL_ENABLE_BP_SHIFT 0
+#define ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_CTL_ENABLE_BP_MASK 0x1
+#define ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_CTL_RD_DELAY_CC_SHIFT 1
+#define ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_CTL_RD_DELAY_CC_MASK 0x3E
+
+/* ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_ADDR_MSK */
+#define ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_ADDR_MSK_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_ADDR_MSK_VAL_MASK 0x7FFFFFF
+
+/* ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_ADDR */
+#define ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_ADDR_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_ADDR_VAL_MASK 0x7FFFFFF
+
+/* ARC_FARM_ARC0_AUX_ARC_ACC_ENGS_BUSER */
+#define ARC_FARM_ARC0_AUX_ARC_ACC_ENGS_BUSER_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_ARC_ACC_ENGS_BUSER_VAL_MASK 0x3
+
+/* ARC_FARM_ARC0_AUX_MME_ARC_UPPER_DCCM_EN */
+#define ARC_FARM_ARC0_AUX_MME_ARC_UPPER_DCCM_EN_VAL_SHIFT 0
+#define ARC_FARM_ARC0_AUX_MME_ARC_UPPER_DCCM_EN_VAL_MASK 0x1
+
+#endif /* ASIC_REG_ARC_FARM_ARC0_AUX_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_aux_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_aux_regs.h
new file mode 100644
index 000000000000..5345b5faa3a2
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_aux_regs.h
@@ -0,0 +1,591 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_ARC_FARM_ARC0_AUX_REGS_H_
+#define ASIC_REG_ARC_FARM_ARC0_AUX_REGS_H_
+
+/*
+ *****************************************
+ *   ARC_FARM_ARC0_AUX
+ *   (Prototype: QMAN_ARC_AUX)
+ *****************************************
+ */
+
+#define mmARC_FARM_ARC0_AUX_RUN_HALT_REQ 0x4E88100
+
+#define mmARC_FARM_ARC0_AUX_RUN_HALT_ACK 0x4E88104
+
+#define mmARC_FARM_ARC0_AUX_RST_VEC_ADDR 0x4E88108
+
+#define mmARC_FARM_ARC0_AUX_DBG_MODE 0x4E8810C
+
+#define mmARC_FARM_ARC0_AUX_CLUSTER_NUM 0x4E88110
+
+#define mmARC_FARM_ARC0_AUX_ARC_NUM 0x4E88114
+
+#define mmARC_FARM_ARC0_AUX_WAKE_UP_EVENT 0x4E88118
+
+#define mmARC_FARM_ARC0_AUX_DCCM_SYS_ADDR_BASE 0x4E8811C
+
+#define mmARC_FARM_ARC0_AUX_CTI_AP_STS 0x4E88120
+
+#define mmARC_FARM_ARC0_AUX_CTI_CFG_MUX_SEL 0x4E88124
+
+#define mmARC_FARM_ARC0_AUX_ARC_RST 0x4E88128
+
+#define mmARC_FARM_ARC0_AUX_ARC_RST_REQ 0x4E8812C
+
+#define mmARC_FARM_ARC0_AUX_SRAM_LSB_ADDR 0x4E88130
+
+#define mmARC_FARM_ARC0_AUX_SRAM_MSB_ADDR 0x4E88134
+
+#define mmARC_FARM_ARC0_AUX_PCIE_LSB_ADDR 0x4E88138
+
+#define mmARC_FARM_ARC0_AUX_PCIE_MSB_ADDR 0x4E8813C
+
+#define mmARC_FARM_ARC0_AUX_CFG_LSB_ADDR 0x4E88140
+
+#define mmARC_FARM_ARC0_AUX_CFG_MSB_ADDR 0x4E88144
+
+#define mmARC_FARM_ARC0_AUX_HBM0_LSB_ADDR 0x4E88150
+
+#define mmARC_FARM_ARC0_AUX_HBM0_MSB_ADDR 0x4E88154
+
+#define mmARC_FARM_ARC0_AUX_HBM1_LSB_ADDR 0x4E88158
+
+#define mmARC_FARM_ARC0_AUX_HBM1_MSB_ADDR 0x4E8815C
+
+#define mmARC_FARM_ARC0_AUX_HBM2_LSB_ADDR 0x4E88160
+
+#define mmARC_FARM_ARC0_AUX_HBM2_MSB_ADDR 0x4E88164
+
+#define mmARC_FARM_ARC0_AUX_HBM3_LSB_ADDR 0x4E88168
+
+#define mmARC_FARM_ARC0_AUX_HBM3_MSB_ADDR 0x4E8816C
+
+#define mmARC_FARM_ARC0_AUX_HBM0_OFFSET 0x4E88170
+
+#define mmARC_FARM_ARC0_AUX_HBM1_OFFSET 0x4E88174
+
+#define mmARC_FARM_ARC0_AUX_HBM2_OFFSET 0x4E88178
+
+#define mmARC_FARM_ARC0_AUX_HBM3_OFFSET 0x4E8817C
+
+#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_LSB_ADDR_0 0x4E88180
+
+#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_LSB_ADDR_1 0x4E88184
+
+#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_LSB_ADDR_2 0x4E88188
+
+#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_LSB_ADDR_3 0x4E8818C
+
+#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_LSB_ADDR_4 0x4E88190
+
+#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_LSB_ADDR_5 0x4E88194
+
+#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_LSB_ADDR_6 0x4E88198
+
+#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_MSB_ADDR_0 0x4E8819C
+
+#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_MSB_ADDR_1 0x4E881A0
+
+#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_MSB_ADDR_2 0x4E881A4
+
+#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_MSB_ADDR_3 0x4E881A8
+
+#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_MSB_ADDR_4 0x4E881AC
+
+#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_MSB_ADDR_5 0x4E881B0
+
+#define mmARC_FARM_ARC0_AUX_GENERAL_PURPOSE_MSB_ADDR_6 0x4E881B4
+
+#define mmARC_FARM_ARC0_AUX_ARC_CBU_AWCACHE_OVR 0x4E881B8
+
+#define mmARC_FARM_ARC0_AUX_ARC_LBU_AWCACHE_OVR 0x4E881BC
+
+#define mmARC_FARM_ARC0_AUX_CONTEXT_ID_0 0x4E881C0
+
+#define mmARC_FARM_ARC0_AUX_CONTEXT_ID_1 0x4E881C4
+
+#define mmARC_FARM_ARC0_AUX_CONTEXT_ID_2 0x4E881C8
+
+#define mmARC_FARM_ARC0_AUX_CONTEXT_ID_3 0x4E881CC
+
+#define mmARC_FARM_ARC0_AUX_CONTEXT_ID_4 0x4E881D0
+
+#define mmARC_FARM_ARC0_AUX_CONTEXT_ID_5 0x4E881D4
+
+#define mmARC_FARM_ARC0_AUX_CONTEXT_ID_6 0x4E881D8
+
+#define mmARC_FARM_ARC0_AUX_CONTEXT_ID_7 0x4E881DC
+
+#define mmARC_FARM_ARC0_AUX_CID_OFFSET_0 0x4E881E0
+
+#define mmARC_FARM_ARC0_AUX_CID_OFFSET_1 0x4E881E4
+
+#define mmARC_FARM_ARC0_AUX_CID_OFFSET_2 0x4E881E8
+
+#define mmARC_FARM_ARC0_AUX_CID_OFFSET_3 0x4E881EC
+
+#define mmARC_FARM_ARC0_AUX_CID_OFFSET_4 0x4E881F0
+
+#define mmARC_FARM_ARC0_AUX_CID_OFFSET_5 0x4E881F4
+
+#define mmARC_FARM_ARC0_AUX_CID_OFFSET_6 0x4E881F8
+
+#define mmARC_FARM_ARC0_AUX_CID_OFFSET_7 0x4E881FC
+
+#define mmARC_FARM_ARC0_AUX_SW_INTR_0 0x4E88200
+
+#define mmARC_FARM_ARC0_AUX_SW_INTR_1 0x4E88204
+
+#define mmARC_FARM_ARC0_AUX_SW_INTR_2 0x4E88208
+
+#define mmARC_FARM_ARC0_AUX_SW_INTR_3 0x4E8820C
+
+#define mmARC_FARM_ARC0_AUX_SW_INTR_4 0x4E88210
+
+#define mmARC_FARM_ARC0_AUX_SW_INTR_5 0x4E88214
+
+#define mmARC_FARM_ARC0_AUX_SW_INTR_6 0x4E88218
+
+#define mmARC_FARM_ARC0_AUX_SW_INTR_7 0x4E8821C
+
+#define mmARC_FARM_ARC0_AUX_SW_INTR_8 0x4E88220
+
+#define mmARC_FARM_ARC0_AUX_SW_INTR_9 0x4E88224
+
+#define mmARC_FARM_ARC0_AUX_SW_INTR_10 0x4E88228
+
+#define mmARC_FARM_ARC0_AUX_SW_INTR_11 0x4E8822C
+
+#define mmARC_FARM_ARC0_AUX_SW_INTR_12 0x4E88230
+
+#define mmARC_FARM_ARC0_AUX_SW_INTR_13 0x4E88234
+
+#define mmARC_FARM_ARC0_AUX_SW_INTR_14 0x4E88238
+
+#define mmARC_FARM_ARC0_AUX_SW_INTR_15 0x4E8823C
+
+#define mmARC_FARM_ARC0_AUX_IRQ_INTR_MASK_0 0x4E88280
+
+#define mmARC_FARM_ARC0_AUX_IRQ_INTR_MASK_1 0x4E88284
+
+#define mmARC_FARM_ARC0_AUX_ARC_SEI_INTR_STS 0x4E88290
+
+#define mmARC_FARM_ARC0_AUX_ARC_SEI_INTR_CLR 0x4E88294
+
+#define mmARC_FARM_ARC0_AUX_ARC_SEI_INTR_MASK 0x4E88298
+
+#define mmARC_FARM_ARC0_AUX_ARC_EXCPTN_CAUSE 0x4E8829C
+
+#define mmARC_FARM_ARC0_AUX_SEI_INTR_HALT_EN 0x4E882A0
+
+#define mmARC_FARM_ARC0_AUX_ARC_SEI_INTR_HALT_MASK 0x4E882A4
+
+#define mmARC_FARM_ARC0_AUX_QMAN_SEI_INTR_HALT_MASK 0x4E882A8
+
+#define mmARC_FARM_ARC0_AUX_ARC_REI_INTR_STS 0x4E882B0
+
+#define mmARC_FARM_ARC0_AUX_ARC_REI_INTR_CLR 0x4E882B4
+
+#define mmARC_FARM_ARC0_AUX_ARC_REI_INTR_MASK 0x4E882B8
+
+#define mmARC_FARM_ARC0_AUX_DCCM_ECC_ERR_ADDR 0x4E882BC
+
+#define mmARC_FARM_ARC0_AUX_DCCM_ECC_SYNDROME 0x4E882C0
+
+#define mmARC_FARM_ARC0_AUX_I_CACHE_ECC_ERR_ADDR 0x4E882C4
+
+#define mmARC_FARM_ARC0_AUX_I_CACHE_ECC_SYNDROME 0x4E882C8
+
+#define mmARC_FARM_ARC0_AUX_D_CACHE_ECC_ERR_ADDR 0x4E882CC
+
+#define mmARC_FARM_ARC0_AUX_D_CACHE_ECC_SYNDROME 0x4E882D0
+
+#define mmARC_FARM_ARC0_AUX_LBW_TRMINATE_AWADDR_ERR 0x4E882E0
+
+#define mmARC_FARM_ARC0_AUX_LBW_TRMINATE_ARADDR_ERR 0x4E882E4
+
+#define mmARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_BRESP 0x4E882E8
+
+#define mmARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_RRESP 0x4E882EC
+
+#define mmARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_AXLEN 0x4E882F0
+
+#define mmARC_FARM_ARC0_AUX_CFG_LBW_TERMINATE_AXSIZE 0x4E882F4
+
+#define mmARC_FARM_ARC0_AUX_SCRATCHPAD_0 0x4E88300
+
+#define mmARC_FARM_ARC0_AUX_SCRATCHPAD_1 0x4E88304
+
+#define mmARC_FARM_ARC0_AUX_SCRATCHPAD_2 0x4E88308
+
+#define mmARC_FARM_ARC0_AUX_SCRATCHPAD_3 0x4E8830C
+
+#define mmARC_FARM_ARC0_AUX_SCRATCHPAD_4 0x4E88310
+
+#define mmARC_FARM_ARC0_AUX_SCRATCHPAD_5 0x4E88314
+
+#define mmARC_FARM_ARC0_AUX_SCRATCHPAD_6 0x4E88318
+
+#define mmARC_FARM_ARC0_AUX_SCRATCHPAD_7 0x4E8831C
+
+#define mmARC_FARM_ARC0_AUX_TOTAL_CBU_WR_CNT 0x4E88320
+
+#define mmARC_FARM_ARC0_AUX_INFLIGHT_CBU_WR_CNT 0x4E88324
+
+#define mmARC_FARM_ARC0_AUX_TOTAL_CBU_RD_CNT 0x4E88328
+
+#define mmARC_FARM_ARC0_AUX_INFLIGHT_CBU_RD_CNT 0x4E8832C
+
+#define mmARC_FARM_ARC0_AUX_TOTAL_LBU_WR_CNT 0x4E88330
+
+#define mmARC_FARM_ARC0_AUX_INFLIGHT_LBU_WR_CNT 0x4E88334
+
+#define mmARC_FARM_ARC0_AUX_TOTAL_LBU_RD_CNT 0x4E88338
+
+#define mmARC_FARM_ARC0_AUX_INFLIGHT_LBU_RD_CNT 0x4E8833C
+
+#define mmARC_FARM_ARC0_AUX_CBU_ARUSER_OVR 0x4E88350
+
+#define mmARC_FARM_ARC0_AUX_CBU_ARUSER_OVR_EN 0x4E88354
+
+#define mmARC_FARM_ARC0_AUX_CBU_AWUSER_OVR 0x4E88358
+
+#define mmARC_FARM_ARC0_AUX_CBU_AWUSER_OVR_EN 0x4E8835C
+
+#define mmARC_FARM_ARC0_AUX_CBU_ARUSER_MSB_OVR 0x4E88360
+
+#define mmARC_FARM_ARC0_AUX_CBU_ARUSER_MSB_OVR_EN 0x4E88364
+
+#define mmARC_FARM_ARC0_AUX_CBU_AWUSER_MSB_OVR 0x4E88368
+
+#define mmARC_FARM_ARC0_AUX_CBU_AWUSER_MSB_OVR_EN 0x4E8836C
+
+#define mmARC_FARM_ARC0_AUX_CBU_AXCACHE_OVR 0x4E88370
+
+#define mmARC_FARM_ARC0_AUX_CBU_LOCK_OVR 0x4E88374
+
+#define mmARC_FARM_ARC0_AUX_CBU_PROT_OVR 0x4E88378
+
+#define mmARC_FARM_ARC0_AUX_CBU_MAX_OUTSTANDING 0x4E8837C
+
+#define mmARC_FARM_ARC0_AUX_CBU_EARLY_BRESP_EN 0x4E88380
+
+#define mmARC_FARM_ARC0_AUX_CBU_FORCE_RSP_OK 0x4E88384
+
+#define mmARC_FARM_ARC0_AUX_CBU_NO_WR_INFLIGHT 0x4E8838C
+
+#define mmARC_FARM_ARC0_AUX_CBU_SEI_INTR_ID 0x4E88390
+
+#define mmARC_FARM_ARC0_AUX_LBU_ARUSER_OVR 0x4E88400
+
+#define mmARC_FARM_ARC0_AUX_LBU_ARUSER_OVR_EN 0x4E88404
+
+#define mmARC_FARM_ARC0_AUX_LBU_AWUSER_OVR 0x4E88408
+
+#define mmARC_FARM_ARC0_AUX_LBU_AWUSER_OVR_EN 0x4E8840C
+
+#define mmARC_FARM_ARC0_AUX_LBU_AXCACHE_OVR 0x4E88420
+
+#define mmARC_FARM_ARC0_AUX_LBU_LOCK_OVR 0x4E88424
+
+#define mmARC_FARM_ARC0_AUX_LBU_PROT_OVR 0x4E88428
+
+#define mmARC_FARM_ARC0_AUX_LBU_MAX_OUTSTANDING 0x4E8842C
+
+#define mmARC_FARM_ARC0_AUX_LBU_EARLY_BRESP_EN 0x4E88430
+
+#define mmARC_FARM_ARC0_AUX_LBU_FORCE_RSP_OK 0x4E88434
+
+#define mmARC_FARM_ARC0_AUX_LBU_NO_WR_INFLIGHT 0x4E8843C
+
+#define mmARC_FARM_ARC0_AUX_LBU_SEI_INTR_ID 0x4E88440
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR_0 0x4E88500
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR_1 0x4E88504
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR_2 0x4E88508
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR_3 0x4E8850C
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR_4 0x4E88510
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR_5 0x4E88514
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR_6 0x4E88518
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR_7 0x4E8851C
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_SIZE_0 0x4E88520
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_SIZE_1 0x4E88524
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_SIZE_2 0x4E88528
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_SIZE_3 0x4E8852C
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_SIZE_4 0x4E88530
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_SIZE_5 0x4E88534
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_SIZE_6 0x4E88538
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_SIZE_7 0x4E8853C
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PI_0 0x4E88540
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PI_1 0x4E88544
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PI_2 0x4E88548
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PI_3 0x4E8854C
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PI_4 0x4E88550
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PI_5 0x4E88554
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PI_6 0x4E88558
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PI_7 0x4E8855C
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_CI_0 0x4E88560
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_CI_1 0x4E88564
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_CI_2 0x4E88568
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_CI_3 0x4E8856C
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_CI_4 0x4E88570
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_CI_5 0x4E88574
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_CI_6 0x4E88578
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_CI_7 0x4E8857C
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG_0 0x4E88580
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG_1 0x4E88584
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG_2 0x4E88588
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG_3 0x4E8858C
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG_4 0x4E88590
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG_5 0x4E88594
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG_6 0x4E88598
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG_7 0x4E8859C
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_MAX_OCCUPANCY_0 0x4E885A0
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_MAX_OCCUPANCY_1 0x4E885A4
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_MAX_OCCUPANCY_2 0x4E885A8
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_MAX_OCCUPANCY_3 0x4E885AC
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_MAX_OCCUPANCY_4 0x4E885B0
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_MAX_OCCUPANCY_5 0x4E885B4
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_MAX_OCCUPANCY_6 0x4E885B8
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_MAX_OCCUPANCY_7 0x4E885BC
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_VALID_ENTRIES_0 0x4E885C0
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_VALID_ENTRIES_1 0x4E885C4
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_VALID_ENTRIES_2 0x4E885C8
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_VALID_ENTRIES_3 0x4E885CC
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_VALID_ENTRIES_4 0x4E885D0
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_VALID_ENTRIES_5 0x4E885D4
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_VALID_ENTRIES_6 0x4E885D8
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_VALID_ENTRIES_7 0x4E885DC
+
+#define mmARC_FARM_ARC0_AUX_GENERAL_Q_VLD_ENTRY_MASK 0x4E885E0
+
+#define mmARC_FARM_ARC0_AUX_NIC_Q_VLD_ENTRY_MASK 0x4E885E4
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_DROP_EN 0x4E88620
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_WARN_MSG 0x4E88624
+
+#define mmARC_FARM_ARC0_AUX_DCCM_QUEUE_ALERT_MSG 0x4E88628
+
+#define mmARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWPROT 0x4E88630
+
+#define mmARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWUSER 0x4E88634
+
+#define mmARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWBURST 0x4E88638
+
+#define mmARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWLOCK 0x4E8863C
+
+#define mmARC_FARM_ARC0_AUX_DCCM_GEN_AXI_AWCACHE 0x4E88640
+
+#define mmARC_FARM_ARC0_AUX_DCCM_WRR_ARB_WEIGHT 0x4E88644
+
+#define mmARC_FARM_ARC0_AUX_DCCM_Q_PUSH_FIFO_FULL_CFG 0x4E88648
+
+#define mmARC_FARM_ARC0_AUX_DCCM_Q_PUSH_FIFO_CNT 0x4E8864C
+
+#define mmARC_FARM_ARC0_AUX_QMAN_CQ_IFIFO_SHADOW_CI 0x4E88650
+
+#define mmARC_FARM_ARC0_AUX_QMAN_ARC_CQ_IFIFO_SHADOW_CI 0x4E88654
+
+#define mmARC_FARM_ARC0_AUX_QMAN_CQ_SHADOW_CI 0x4E88658
+
+#define mmARC_FARM_ARC0_AUX_QMAN_ARC_CQ_SHADOW_CI 0x4E8865C
+
+#define mmARC_FARM_ARC0_AUX_AUX2APB_PROT 0x4E88700
+
+#define mmARC_FARM_ARC0_AUX_LBW_FORK_WIN_EN 0x4E88704
+
+#define mmARC_FARM_ARC0_AUX_QMAN_LBW_FORK_BASE_ADDR0 0x4E88708
+
+#define mmARC_FARM_ARC0_AUX_QMAN_LBW_FORK_ADDR_MASK0 0x4E8870C
+
+#define mmARC_FARM_ARC0_AUX_QMAN_LBW_FORK_BASE_ADDR1 0x4E88710
+
+#define mmARC_FARM_ARC0_AUX_QMAN_LBW_FORK_ADDR_MASK1 0x4E88714
+
+#define mmARC_FARM_ARC0_AUX_FARM_LBW_FORK_BASE_ADDR0 0x4E88718
+
+#define mmARC_FARM_ARC0_AUX_FARM_LBW_FORK_ADDR_MASK0 0x4E8871C
+
+#define mmARC_FARM_ARC0_AUX_FARM_LBW_FORK_BASE_ADDR1 0x4E88720
+
+#define mmARC_FARM_ARC0_AUX_FARM_LBW_FORK_ADDR_MASK1 0x4E88724
+
+#define mmARC_FARM_ARC0_AUX_LBW_APB_FORK_MAX_ADDR0 0x4E88728
+
+#define mmARC_FARM_ARC0_AUX_LBW_APB_FORK_MAX_ADDR1 0x4E8872C
+
+#define mmARC_FARM_ARC0_AUX_ARC_ACC_ENGS_LBW_FORK_MASK 0x4E88730
+
+#define mmARC_FARM_ARC0_AUX_ARC_DUP_ENG_LBW_FORK_ADDR 0x4E88734
+
+#define mmARC_FARM_ARC0_AUX_ARC_ACP_ENG_LBW_FORK_ADDR 0x4E88738
+
+#define mmARC_FARM_ARC0_AUX_ARC_ACC_ENGS_VIRTUAL_ADDR 0x4E8873C
+
+#define mmARC_FARM_ARC0_AUX_CBU_FORK_WIN_EN 0x4E88740
+
+#define mmARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR0_LSB 0x4E88750
+
+#define mmARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR0_MSB 0x4E88754
+
+#define mmARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK0_LSB 0x4E88758
+
+#define mmARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK0_MSB 0x4E8875C
+
+#define mmARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR1_LSB 0x4E88760
+
+#define mmARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR1_MSB 0x4E88764
+
+#define mmARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK1_LSB 0x4E88768
+
+#define mmARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK1_MSB 0x4E8876C
+
+#define mmARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR2_LSB 0x4E88770
+
+#define mmARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR2_MSB 0x4E88774
+
+#define mmARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK2_LSB 0x4E88778
+
+#define mmARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK2_MSB 0x4E8877C
+
+#define mmARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR3_LSB 0x4E88780
+
+#define mmARC_FARM_ARC0_AUX_CBU_FORK_BASE_ADDR3_MSB 0x4E88784
+
+#define mmARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK3_LSB 0x4E88788
+
+#define mmARC_FARM_ARC0_AUX_CBU_FORK_ADDR_MASK3_MSB 0x4E8878C
+
+#define mmARC_FARM_ARC0_AUX_CBU_TRMINATE_ARADDR_LSB 0x4E88790
+
+#define mmARC_FARM_ARC0_AUX_CBU_TRMINATE_ARADDR_MSB 0x4E88794
+
+#define mmARC_FARM_ARC0_AUX_CFG_CBU_TERMINATE_BRESP 0x4E88798
+
+#define mmARC_FARM_ARC0_AUX_CFG_CBU_TERMINATE_RRESP 0x4E8879C
+
+#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_0 0x4E88800
+
+#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_1 0x4E88804
+
+#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_2 0x4E88808
+
+#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_3 0x4E8880C
+
+#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_4 0x4E88810
+
+#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_5 0x4E88814
+
+#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_6 0x4E88818
+
+#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_7 0x4E8881C
+
+#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_8 0x4E88820
+
+#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_9 0x4E88824
+
+#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_10 0x4E88828
+
+#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_11 0x4E8882C
+
+#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_12 0x4E88830
+
+#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_13 0x4E88834
+
+#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_14 0x4E88838
+
+#define mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_15 0x4E8883C
+
+#define mmARC_FARM_ARC0_AUX_DCCM_TRMINATE_AWADDR_ERR 0x4E88840
+
+#define mmARC_FARM_ARC0_AUX_DCCM_TRMINATE_ARADDR_ERR 0x4E88844
+
+#define mmARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_BRESP 0x4E88848
+
+#define mmARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_RRESP 0x4E8884C
+
+#define mmARC_FARM_ARC0_AUX_CFG_DCCM_TERMINATE_EN 0x4E88850
+
+#define mmARC_FARM_ARC0_AUX_CFG_DCCM_SECURE_REGION 0x4E88854
+
+#define mmARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_WR_IF_CNT 0x4E88900
+
+#define mmARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_CTL 0x4E88904
+
+#define mmARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_ADDR_MSK 0x4E88908
+
+#define mmARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_ADDR 0x4E8890C
+
+#define mmARC_FARM_ARC0_AUX_ARC_ACC_ENGS_BUSER 0x4E88910
+
+#define mmARC_FARM_ARC0_AUX_MME_ARC_UPPER_DCCM_EN 0x4E88920
+
+#endif /* ASIC_REG_ARC_FARM_ARC0_AUX_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_dup_eng_axuser_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_dup_eng_axuser_regs.h
new file mode 100644
index 000000000000..bde077eed285
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_dup_eng_axuser_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_ARC_FARM_ARC0_DUP_ENG_AXUSER_REGS_H_
+#define ASIC_REG_ARC_FARM_ARC0_DUP_ENG_AXUSER_REGS_H_
+
+/*
+ *****************************************
+ *   ARC_FARM_ARC0_DUP_ENG_AXUSER
+ *   (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_ASID 0x4E89900
+
+#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_MMU_BP 0x4E89904
+
+#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_STRONG_ORDER 0x4E89908
+
+#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_NO_SNOOP 0x4E8990C
+
+#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_WR_REDUCTION 0x4E89910
+
+#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_RD_ATOMIC 0x4E89914
+
+#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_QOS 0x4E89918
+
+#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_RSVD 0x4E8991C
+
+#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_EMEM_CPAGE 0x4E89920
+
+#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_CORE 0x4E89924
+
+#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_E2E_COORD 0x4E89928
+
+#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_WR_OVRD_LO 0x4E89930
+
+#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_WR_OVRD_HI 0x4E89934
+
+#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_RD_OVRD_LO 0x4E89938
+
+#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_RD_OVRD_HI 0x4E8993C
+
+#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_LB_COORD 0x4E89940
+
+#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_LB_LOCK 0x4E89944
+
+#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_LB_RSVD 0x4E89948
+
+#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_LB_OVRD 0x4E8994C
+
+#endif /* ASIC_REG_ARC_FARM_ARC0_DUP_ENG_AXUSER_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_dup_eng_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_dup_eng_regs.h
new file mode 100644
index 000000000000..491af75c12c3
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_dup_eng_regs.h
@@ -0,0 +1,575 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_ARC_FARM_ARC0_DUP_ENG_REGS_H_
+#define ASIC_REG_ARC_FARM_ARC0_DUP_ENG_REGS_H_
+
+/*
+ *****************************************
+ *   ARC_FARM_ARC0_DUP_ENG
+ *   (Prototype: ARC_DUP_ENG)
+ *****************************************
+ */
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_0 0x4E89000
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_1 0x4E89004
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_2 0x4E89008
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_3 0x4E8900C
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_4 0x4E89010
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_5 0x4E89014
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_6 0x4E89018
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_7 0x4E8901C
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_8 0x4E89020
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_9 0x4E89024
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_10 0x4E89028
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_11 0x4E8902C
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_12 0x4E89030
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_13 0x4E89034
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_14 0x4E89038
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_15 0x4E8903C
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_16 0x4E89040
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_17 0x4E89044
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_18 0x4E89048
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_19 0x4E8904C
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_20 0x4E89050
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_21 0x4E89054
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_22 0x4E89058
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_23 0x4E8905C
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_24 0x4E89060
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_MME_ENG_ADDR_0 0x4E89064
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_MME_ENG_ADDR_1 0x4E89068
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_MME_ENG_ADDR_2 0x4E8906C
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_MME_ENG_ADDR_3 0x4E89070
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_0 0x4E89074
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_1 0x4E89078
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_2 0x4E8907C
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_3 0x4E89080
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_4 0x4E89084
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_5 0x4E89088
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_6 0x4E8908C
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_7 0x4E89090
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_8 0x4E89094
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_9 0x4E89098
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_10 0x4E8909C
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_11 0x4E890A0
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_12 0x4E890A4
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_13 0x4E890A8
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_14 0x4E890AC
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_15 0x4E890B0
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_16 0x4E890B4
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_17 0x4E890B8
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_18 0x4E890BC
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_19 0x4E890C0
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_20 0x4E890C4
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_21 0x4E890C8
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_22 0x4E890CC
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_ADDR_23 0x4E890D0
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_EDMA_ENG_ADDR_0 0x4E890D4
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_EDMA_ENG_ADDR_1 0x4E890D8
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_EDMA_ENG_ADDR_2 0x4E890DC
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_EDMA_ENG_ADDR_3 0x4E890E0
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_EDMA_ENG_ADDR_4 0x4E890E4
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_EDMA_ENG_ADDR_5 0x4E890E8
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_EDMA_ENG_ADDR_6 0x4E890EC
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_EDMA_ENG_ADDR_7 0x4E890F0
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_PDMA_ENG_ADDR_0 0x4E890F4
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_PDMA_ENG_ADDR_1 0x4E890F8
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_ROT_ENG_ADDR_0 0x4E890FC
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_ROT_ENG_ADDR_1 0x4E89100
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_0 0x4E89104
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_1 0x4E89108
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_2 0x4E8910C
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_3 0x4E89110
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_4 0x4E89114
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_5 0x4E89118
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_6 0x4E8911C
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_7 0x4E89120
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_8 0x4E89124
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_9 0x4E89128
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_10 0x4E8912C
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_11 0x4E89130
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_12 0x4E89134
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_13 0x4E89138
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_14 0x4E8913C
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_ADDR_15 0x4E89140
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_MASK 0x4E89200
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_MME_ENG_MASK 0x4E89204
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_EDMA_ENG_MASK 0x4E89208
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_PDMA_ENG_MASK 0x4E8920C
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_ROT_ENG_MASK 0x4E89210
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_RSVD_ENG_MASK 0x4E89214
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_MASK_0 0x4E89218
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_MASK_1 0x4E8921C
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_MASK_2 0x4E89220
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_MASK_3 0x4E89224
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_MASK_4 0x4E89228
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_MASK_5 0x4E8922C
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_MASK_6 0x4E89230
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_NIC_ENG_MASK_7 0x4E89234
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_0 0x4E89238
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_1 0x4E8923C
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_2 0x4E89240
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_3 0x4E89244
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_4 0x4E89248
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_5 0x4E8924C
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_6 0x4E89250
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_7 0x4E89254
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_8 0x4E89258
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_9 0x4E8925C
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_10 0x4E89260
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_11 0x4E89264
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_12 0x4E89268
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_0_13 0x4E8926C
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_1_0 0x4E89288
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_1_1 0x4E8928C
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_1_2 0x4E89290
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_1_3 0x4E89294
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_1_4 0x4E89298
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_1_5 0x4E8929C
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_2_0 0x4E892A0
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_2_1 0x4E892A4
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_2_2 0x4E892A8
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_2_3 0x4E892AC
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_2_4 0x4E892B0
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_2_5 0x4E892B4
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_3_0 0x4E892B8
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_3_1 0x4E892BC
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_3_2 0x4E892C0
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_3_3 0x4E892C4
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_3_4 0x4E892C8
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_TRANS_DATA_Q_3_5 0x4E892CC
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_GENERAL_CFG 0x4E892D0
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_BP_CFG 0x4E892D4
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_0 0x4E892D8
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_1 0x4E892DC
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_2 0x4E892E0
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_3 0x4E892E4
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_4 0x4E892E8
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_5 0x4E892EC
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_6 0x4E892F0
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_7 0x4E892F4
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_8 0x4E892F8
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_9 0x4E892FC
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_10 0x4E89300
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_11 0x4E89304
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_12 0x4E89308
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_13 0x4E8930C
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_DBG_IN_GRP_TRANS_0 0x4E894A0
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_DBG_IN_GRP_TRANS_1 0x4E894A4
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_DBG_IN_GRP_TRANS_2 0x4E894A8
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_DBG_STS 0x4E894AC
+
+#define mmARC_FARM_ARC0_DUP_ENG_DUP_DBG_OUT_RQ_CNT 0x4E894B0
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_0 0x4E894B4
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_1 0x4E894B8
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_2 0x4E894BC
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_3 0x4E894C0
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_4 0x4E894C4
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_5 0x4E894C8
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_6 0x4E894CC
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_7 0x4E894D0
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_8 0x4E894D4
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_9 0x4E894D8
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_10 0x4E894DC
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_11 0x4E894E0
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_12 0x4E894E4
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_13 0x4E894E8
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_14 0x4E894EC
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_15 0x4E894F0
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_16 0x4E894F4
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_17 0x4E894F8
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_18 0x4E894FC
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_19 0x4E89500
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_20 0x4E89504
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_21 0x4E89508
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_22 0x4E8950C
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_23 0x4E89510
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_24 0x4E89514
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_25 0x4E89518
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_26 0x4E8951C
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_27 0x4E89520
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_28 0x4E89524
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_29 0x4E89528
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_30 0x4E8952C
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_31 0x4E89530
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_32 0x4E89534
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_33 0x4E89538
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_34 0x4E8953C
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_35 0x4E89540
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_36 0x4E89544
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_37 0x4E89548
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_38 0x4E8954C
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_39 0x4E89550
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_40 0x4E89554
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_41 0x4E89558
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_42 0x4E8955C
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_43 0x4E89560
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_44 0x4E89564
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_45 0x4E89568
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_46 0x4E8956C
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_47 0x4E89570
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_48 0x4E89574
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_49 0x4E89578
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_50 0x4E8957C
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_51 0x4E89580
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_52 0x4E89584
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_53 0x4E89588
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_54 0x4E8958C
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_55 0x4E89590
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_56 0x4E89594
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_57 0x4E89598
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_58 0x4E8959C
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_59 0x4E895A0
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_60 0x4E895A4
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_61 0x4E895A8
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_62 0x4E895AC
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CONTEXT_ID_63 0x4E895B0
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_0 0x4E895B4
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_1 0x4E895B8
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_2 0x4E895BC
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_3 0x4E895C0
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_4 0x4E895C4
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_5 0x4E895C8
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_6 0x4E895CC
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_7 0x4E895D0
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_8 0x4E895D4
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_9 0x4E895D8
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_10 0x4E895DC
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_11 0x4E895E0
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_12 0x4E895E4
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_13 0x4E895E8
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_14 0x4E895EC
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_15 0x4E895F0
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_16 0x4E895F4
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_17 0x4E895F8
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_18 0x4E895FC
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_19 0x4E89600
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_20 0x4E89604
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_21 0x4E89608
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_22 0x4E8960C
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_23 0x4E89610
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_24 0x4E89614
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_25 0x4E89618
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_26 0x4E8961C
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_27 0x4E89620
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_28 0x4E89624
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_29 0x4E89628
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_30 0x4E8962C
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_31 0x4E89630
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_32 0x4E89634
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_33 0x4E89638
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_34 0x4E8963C
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_35 0x4E89640
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_36 0x4E89644
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_37 0x4E89648
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_38 0x4E8964C
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_39 0x4E89650
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_40 0x4E89654
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_41 0x4E89658
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_42 0x4E8965C
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_43 0x4E89660
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_44 0x4E89664
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_45 0x4E89668
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_46 0x4E8966C
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_47 0x4E89670
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_48 0x4E89674
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_49 0x4E89678
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_50 0x4E8967C
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_51 0x4E89680
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_52 0x4E89684
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_53 0x4E89688
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_54 0x4E8968C
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_55 0x4E89690
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_56 0x4E89694
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_57 0x4E89698
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_58 0x4E8969C
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_59 0x4E896A0
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_60 0x4E896A4
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_61 0x4E896A8
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_62 0x4E896AC
+
+#define mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_63 0x4E896B0
+
+#endif /* ASIC_REG_ARC_FARM_ARC0_DUP_ENG_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_ctx_axuser_masks.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_ctx_axuser_masks.h
new file mode 100644
index 000000000000..12d6a124a2e9
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_ctx_axuser_masks.h
@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_ARC_FARM_KDMA_CTX_AXUSER_MASKS_H_
+#define ASIC_REG_ARC_FARM_KDMA_CTX_AXUSER_MASKS_H_
+
+/*
+ *****************************************
+ *   ARC_FARM_KDMA_CTX_AXUSER
+ *   (Prototype: AXUSER)
+ *****************************************
+ */
+
+/* ARC_FARM_KDMA_CTX_AXUSER_HB_ASID */
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_WR_SHIFT 0
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_WR_MASK 0x3FF
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_RD_SHIFT 16
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_RD_MASK 0x3FF0000
+
+/* ARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP */
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP_WR_SHIFT 0
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP_WR_MASK 0x1
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP_RD_SHIFT 4
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP_RD_MASK 0x10
+
+/* ARC_FARM_KDMA_CTX_AXUSER_HB_STRONG_ORDER */
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_STRONG_ORDER_WR_SHIFT 0
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_STRONG_ORDER_WR_MASK 0x1
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_STRONG_ORDER_RD_SHIFT 4
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_STRONG_ORDER_RD_MASK 0x10
+
+/* ARC_FARM_KDMA_CTX_AXUSER_HB_NO_SNOOP */
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_NO_SNOOP_WR_SHIFT 0
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_NO_SNOOP_WR_MASK 0x1
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_NO_SNOOP_RD_SHIFT 4
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_NO_SNOOP_RD_MASK 0x10
+
+/* ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION */
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_IND_SHIFT 0
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_IND_MASK 0x1
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_DTYPE_SHIFT 4
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_DTYPE_MASK 0xF0
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_OP_SHIFT 8
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_OP_MASK 0x300
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_ROUND_SHIFT 12
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_ROUND_MASK 0x3000
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_MAX_SHIFT 16
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION_MAX_MASK 0x10000
+
+/* ARC_FARM_KDMA_CTX_AXUSER_HB_RD_ATOMIC */
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_ATOMIC_IND_SHIFT 0
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_ATOMIC_IND_MASK 0x3
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_ATOMIC_ADDITION_SIZE_SHIFT 4
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_ATOMIC_ADDITION_SIZE_MASK 0xFF0
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_ATOMIC_MSB_MASK_SHIFT 12
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_ATOMIC_MSB_MASK_MASK 0x1F000
+
+/* ARC_FARM_KDMA_CTX_AXUSER_HB_QOS */
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_QOS_WR_SHIFT 0
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_QOS_WR_MASK 0xF
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_QOS_RD_SHIFT 4
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_QOS_RD_MASK 0x70
+
+/* ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD */
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD_WR_BIT_27_SHIFT 0
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD_WR_BIT_27_MASK 0x1
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD_WR_BIT_28_SHIFT 1
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD_WR_BIT_28_MASK 0x2
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD_WR_BIT_30_SHIFT 2
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD_WR_BIT_30_MASK 0x4
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD_WR_BIT_31_SHIFT 3
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_RSVD_WR_BIT_31_MASK 0x8
+
+/* ARC_FARM_KDMA_CTX_AXUSER_HB_EMEM_CPAGE */
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_EMEM_CPAGE_WR_SHIFT 0
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_EMEM_CPAGE_WR_MASK 0x1
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_EMEM_CPAGE_RD_SHIFT 4
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_EMEM_CPAGE_RD_MASK 0x10
+
+/* ARC_FARM_KDMA_CTX_AXUSER_HB_CORE */
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_CORE_WR_SHIFT 0
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_CORE_WR_MASK 0x1
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_CORE_RD_SHIFT 4
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_CORE_RD_MASK 0x10
+
+/* ARC_FARM_KDMA_CTX_AXUSER_E2E_COORD */
+#define ARC_FARM_KDMA_CTX_AXUSER_E2E_COORD_X_SHIFT 0
+#define ARC_FARM_KDMA_CTX_AXUSER_E2E_COORD_X_MASK 0x1F
+#define ARC_FARM_KDMA_CTX_AXUSER_E2E_COORD_Y_SHIFT 8
+#define ARC_FARM_KDMA_CTX_AXUSER_E2E_COORD_Y_MASK 0xF00
+
+/* ARC_FARM_KDMA_CTX_AXUSER_HB_WR_OVRD_LO */
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_OVRD_LO_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_OVRD_LO_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_CTX_AXUSER_HB_WR_OVRD_HI */
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_OVRD_HI_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_WR_OVRD_HI_VAL_MASK 0x3FF
+
+/* ARC_FARM_KDMA_CTX_AXUSER_HB_RD_OVRD_LO */
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_OVRD_LO_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_OVRD_LO_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_CTX_AXUSER_HB_RD_OVRD_HI */
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_OVRD_HI_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_AXUSER_HB_RD_OVRD_HI_VAL_MASK 0x3FF
+
+/* ARC_FARM_KDMA_CTX_AXUSER_LB_COORD */
+#define ARC_FARM_KDMA_CTX_AXUSER_LB_COORD_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_AXUSER_LB_COORD_VAL_MASK 0x3FF
+
+/* ARC_FARM_KDMA_CTX_AXUSER_LB_LOCK */
+#define ARC_FARM_KDMA_CTX_AXUSER_LB_LOCK_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_AXUSER_LB_LOCK_VAL_MASK 0x1
+
+/* ARC_FARM_KDMA_CTX_AXUSER_LB_RSVD */
+#define ARC_FARM_KDMA_CTX_AXUSER_LB_RSVD_BIT_21_11_SHIFT 0
+#define ARC_FARM_KDMA_CTX_AXUSER_LB_RSVD_BIT_21_11_MASK 0x7FF
+#define ARC_FARM_KDMA_CTX_AXUSER_LB_RSVD_BIT_22_SHIFT 12
+#define ARC_FARM_KDMA_CTX_AXUSER_LB_RSVD_BIT_22_MASK 0x1000
+
+/* ARC_FARM_KDMA_CTX_AXUSER_LB_OVRD */
+#define ARC_FARM_KDMA_CTX_AXUSER_LB_OVRD_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_AXUSER_LB_OVRD_VAL_MASK 0xFFFFFFFF
+
+#endif /* ASIC_REG_ARC_FARM_KDMA_CTX_AXUSER_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_ctx_axuser_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_ctx_axuser_regs.h
new file mode 100644
index 000000000000..23f9d2df52a7
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_ctx_axuser_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_ARC_FARM_KDMA_CTX_AXUSER_REGS_H_
+#define ASIC_REG_ARC_FARM_KDMA_CTX_AXUSER_REGS_H_
+
+/*
+ *****************************************
+ *   ARC_FARM_KDMA_CTX_AXUSER
+ *   (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define mmARC_FARM_KDMA_CTX_AXUSER_HB_ASID 0x4E8B800
+
+#define mmARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP 0x4E8B804
+
+#define mmARC_FARM_KDMA_CTX_AXUSER_HB_STRONG_ORDER 0x4E8B808
+
+#define mmARC_FARM_KDMA_CTX_AXUSER_HB_NO_SNOOP 0x4E8B80C
+
+#define mmARC_FARM_KDMA_CTX_AXUSER_HB_WR_REDUCTION 0x4E8B810
+
+#define mmARC_FARM_KDMA_CTX_AXUSER_HB_RD_ATOMIC 0x4E8B814
+
+#define mmARC_FARM_KDMA_CTX_AXUSER_HB_QOS 0x4E8B818
+
+#define mmARC_FARM_KDMA_CTX_AXUSER_HB_RSVD 0x4E8B81C
+
+#define mmARC_FARM_KDMA_CTX_AXUSER_HB_EMEM_CPAGE 0x4E8B820
+
+#define mmARC_FARM_KDMA_CTX_AXUSER_HB_CORE 0x4E8B824
+
+#define mmARC_FARM_KDMA_CTX_AXUSER_E2E_COORD 0x4E8B828
+
+#define mmARC_FARM_KDMA_CTX_AXUSER_HB_WR_OVRD_LO 0x4E8B830
+
+#define mmARC_FARM_KDMA_CTX_AXUSER_HB_WR_OVRD_HI 0x4E8B834
+
+#define mmARC_FARM_KDMA_CTX_AXUSER_HB_RD_OVRD_LO 0x4E8B838
+
+#define mmARC_FARM_KDMA_CTX_AXUSER_HB_RD_OVRD_HI 0x4E8B83C
+
+#define mmARC_FARM_KDMA_CTX_AXUSER_LB_COORD 0x4E8B840
+
+#define mmARC_FARM_KDMA_CTX_AXUSER_LB_LOCK 0x4E8B844
+
+#define mmARC_FARM_KDMA_CTX_AXUSER_LB_RSVD 0x4E8B848
+
+#define mmARC_FARM_KDMA_CTX_AXUSER_LB_OVRD 0x4E8B84C
+
+#endif /* ASIC_REG_ARC_FARM_KDMA_CTX_AXUSER_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_ctx_masks.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_ctx_masks.h
new file mode 100644
index 000000000000..bee4de0b28d6
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_ctx_masks.h
@@ -0,0 +1,221 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_ARC_FARM_KDMA_CTX_MASKS_H_
+#define ASIC_REG_ARC_FARM_KDMA_CTX_MASKS_H_
+
+/*
+ *****************************************
+ *   ARC_FARM_KDMA_CTX
+ *   (Prototype: DMA_CORE_CTX)
+ *****************************************
+ */
+
+/* ARC_FARM_KDMA_CTX_RATE_LIM_TKN */
+#define ARC_FARM_KDMA_CTX_RATE_LIM_TKN_RD_SHIFT 0
+#define ARC_FARM_KDMA_CTX_RATE_LIM_TKN_RD_MASK 0xFF
+#define ARC_FARM_KDMA_CTX_RATE_LIM_TKN_WR_SHIFT 16
+#define ARC_FARM_KDMA_CTX_RATE_LIM_TKN_WR_MASK 0xFF0000
+
+/* ARC_FARM_KDMA_CTX_PWRLP */
+#define ARC_FARM_KDMA_CTX_PWRLP_DATA_SHIFT 0
+#define ARC_FARM_KDMA_CTX_PWRLP_DATA_MASK 0xFF
+#define ARC_FARM_KDMA_CTX_PWRLP_EN_SHIFT 8
+#define ARC_FARM_KDMA_CTX_PWRLP_EN_MASK 0x100
+
+/* ARC_FARM_KDMA_CTX_TE_NUMROWS */
+#define ARC_FARM_KDMA_CTX_TE_NUMROWS_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_TE_NUMROWS_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_CTX_IDX */
+#define ARC_FARM_KDMA_CTX_IDX_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_IDX_VAL_MASK 0xFFFF
+
+/* ARC_FARM_KDMA_CTX_IDX_INC */
+#define ARC_FARM_KDMA_CTX_IDX_INC_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_IDX_INC_VAL_MASK 0xFF
+
+/* ARC_FARM_KDMA_CTX_CTRL */
+#define ARC_FARM_KDMA_CTX_CTRL_TRANSPOSE_SHIFT 0
+#define ARC_FARM_KDMA_CTX_CTRL_TRANSPOSE_MASK 0x1
+#define ARC_FARM_KDMA_CTX_CTRL_DTYPE_SHIFT 4
+#define ARC_FARM_KDMA_CTX_CTRL_DTYPE_MASK 0x30
+#define ARC_FARM_KDMA_CTX_CTRL_COMPRESS_SHIFT 8
+#define ARC_FARM_KDMA_CTX_CTRL_COMPRESS_MASK 0x100
+#define ARC_FARM_KDMA_CTX_CTRL_DECOMPRESS_SHIFT 9
+#define ARC_FARM_KDMA_CTX_CTRL_DECOMPRESS_MASK 0x200
+#define ARC_FARM_KDMA_CTX_CTRL_RD_UNCACHEABLE_SHIFT 12
+#define ARC_FARM_KDMA_CTX_CTRL_RD_UNCACHEABLE_MASK 0x1000
+
+/* ARC_FARM_KDMA_CTX_SRC_TSIZE_0 */
+#define ARC_FARM_KDMA_CTX_SRC_TSIZE_0_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_SRC_TSIZE_0_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_CTX_SRC_TSIZE_1 */
+#define ARC_FARM_KDMA_CTX_SRC_TSIZE_1_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_SRC_TSIZE_1_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_CTX_SRC_STRIDE_1 */
+#define ARC_FARM_KDMA_CTX_SRC_STRIDE_1_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_SRC_STRIDE_1_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_CTX_SRC_TSIZE_2 */
+#define ARC_FARM_KDMA_CTX_SRC_TSIZE_2_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_SRC_TSIZE_2_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_CTX_SRC_STRIDE_2 */
+#define ARC_FARM_KDMA_CTX_SRC_STRIDE_2_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_SRC_STRIDE_2_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_CTX_SRC_TSIZE_3 */
+#define ARC_FARM_KDMA_CTX_SRC_TSIZE_3_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_SRC_TSIZE_3_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_CTX_SRC_STRIDE_3 */
+#define ARC_FARM_KDMA_CTX_SRC_STRIDE_3_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_SRC_STRIDE_3_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_CTX_SRC_TSIZE_4 */
+#define ARC_FARM_KDMA_CTX_SRC_TSIZE_4_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_SRC_TSIZE_4_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_CTX_SRC_STRIDE_4 */
+#define ARC_FARM_KDMA_CTX_SRC_STRIDE_4_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_SRC_STRIDE_4_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_CTX_DST_TSIZE_1 */
+#define ARC_FARM_KDMA_CTX_DST_TSIZE_1_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_DST_TSIZE_1_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_CTX_DST_STRIDE_1 */
+#define ARC_FARM_KDMA_CTX_DST_STRIDE_1_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_DST_STRIDE_1_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_CTX_DST_TSIZE_2 */
+#define ARC_FARM_KDMA_CTX_DST_TSIZE_2_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_DST_TSIZE_2_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_CTX_DST_STRIDE_2 */
+#define ARC_FARM_KDMA_CTX_DST_STRIDE_2_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_DST_STRIDE_2_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_CTX_DST_TSIZE_3 */
+#define ARC_FARM_KDMA_CTX_DST_TSIZE_3_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_DST_TSIZE_3_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_CTX_DST_STRIDE_3 */
+#define ARC_FARM_KDMA_CTX_DST_STRIDE_3_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_DST_STRIDE_3_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_CTX_DST_TSIZE_4 */
+#define ARC_FARM_KDMA_CTX_DST_TSIZE_4_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_DST_TSIZE_4_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_CTX_DST_STRIDE_4 */
+#define ARC_FARM_KDMA_CTX_DST_STRIDE_4_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_DST_STRIDE_4_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_CTX_WR_COMP_ADDR_HI */
+#define ARC_FARM_KDMA_CTX_WR_COMP_ADDR_HI_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_WR_COMP_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_CTX_WR_COMP_ADDR_LO */
+#define ARC_FARM_KDMA_CTX_WR_COMP_ADDR_LO_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_WR_COMP_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_CTX_WR_COMP_WDATA */
+#define ARC_FARM_KDMA_CTX_WR_COMP_WDATA_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_WR_COMP_WDATA_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_CTX_SRC_OFFSET_LO */
+#define ARC_FARM_KDMA_CTX_SRC_OFFSET_LO_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_SRC_OFFSET_LO_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_CTX_SRC_OFFSET_HI */
+#define ARC_FARM_KDMA_CTX_SRC_OFFSET_HI_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_SRC_OFFSET_HI_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_CTX_DST_OFFSET_LO */
+#define ARC_FARM_KDMA_CTX_DST_OFFSET_LO_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_DST_OFFSET_LO_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_CTX_DST_OFFSET_HI */
+#define ARC_FARM_KDMA_CTX_DST_OFFSET_HI_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_DST_OFFSET_HI_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_CTX_SRC_BASE_LO */
+#define ARC_FARM_KDMA_CTX_SRC_BASE_LO_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_SRC_BASE_LO_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_CTX_SRC_BASE_HI */
+#define ARC_FARM_KDMA_CTX_SRC_BASE_HI_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_SRC_BASE_HI_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_CTX_DST_BASE_LO */
+#define ARC_FARM_KDMA_CTX_DST_BASE_LO_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_DST_BASE_LO_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_CTX_DST_BASE_HI */
+#define ARC_FARM_KDMA_CTX_DST_BASE_HI_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_DST_BASE_HI_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_CTX_DST_TSIZE_0 */
+#define ARC_FARM_KDMA_CTX_DST_TSIZE_0_VAL_SHIFT 0
+#define ARC_FARM_KDMA_CTX_DST_TSIZE_0_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_CTX_COMMIT */
+#define ARC_FARM_KDMA_CTX_COMMIT_WR_COMP_EN_SHIFT 0
+#define ARC_FARM_KDMA_CTX_COMMIT_WR_COMP_EN_MASK 0x1
+#define ARC_FARM_KDMA_CTX_COMMIT_ENDIAN_SWAP_SHIFT 1
+#define ARC_FARM_KDMA_CTX_COMMIT_ENDIAN_SWAP_MASK 0x6
+#define ARC_FARM_KDMA_CTX_COMMIT_MEM_SET_SHIFT 4
+#define ARC_FARM_KDMA_CTX_COMMIT_MEM_SET_MASK 0x10
+#define ARC_FARM_KDMA_CTX_COMMIT_BF16_SHIFT 6
+#define ARC_FARM_KDMA_CTX_COMMIT_BF16_MASK 0x40
+#define ARC_FARM_KDMA_CTX_COMMIT_FP16_SHIFT 7
+#define ARC_FARM_KDMA_CTX_COMMIT_FP16_MASK 0x80
+#define ARC_FARM_KDMA_CTX_COMMIT_CTX_ID_INC_SHIFT 8
+#define ARC_FARM_KDMA_CTX_COMMIT_CTX_ID_INC_MASK 0x100
+#define ARC_FARM_KDMA_CTX_COMMIT_ADD_OFFSET_0_SHIFT 9
+#define ARC_FARM_KDMA_CTX_COMMIT_ADD_OFFSET_0_MASK 0x200
+#define ARC_FARM_KDMA_CTX_COMMIT_SRC_SIZE0_FROM_DST_SIZE0_SHIFT 10
+#define ARC_FARM_KDMA_CTX_COMMIT_SRC_SIZE0_FROM_DST_SIZE0_MASK 0x400
+#define ARC_FARM_KDMA_CTX_COMMIT_SRC_OFST_FROM_DST_OFST_SHIFT 11
+#define ARC_FARM_KDMA_CTX_COMMIT_SRC_OFST_FROM_DST_OFST_MASK 0x800
+#define ARC_FARM_KDMA_CTX_COMMIT_DISABLE_DIM1_SHIFT 12
+#define ARC_FARM_KDMA_CTX_COMMIT_DISABLE_DIM1_MASK 0x1000
+#define ARC_FARM_KDMA_CTX_COMMIT_DISABLE_DIM2_SHIFT 13
+#define ARC_FARM_KDMA_CTX_COMMIT_DISABLE_DIM2_MASK 0x2000
+#define ARC_FARM_KDMA_CTX_COMMIT_DISABLE_DIM3_SHIFT 14
+#define ARC_FARM_KDMA_CTX_COMMIT_DISABLE_DIM3_MASK 0x4000
+#define ARC_FARM_KDMA_CTX_COMMIT_DISABLE_DIM4_SHIFT 15
+#define ARC_FARM_KDMA_CTX_COMMIT_DISABLE_DIM4_MASK 0x8000
+#define ARC_FARM_KDMA_CTX_COMMIT_SRC_SIZE1_FROM_DST_SIZE1_SHIFT 16
+#define ARC_FARM_KDMA_CTX_COMMIT_SRC_SIZE1_FROM_DST_SIZE1_MASK 0x10000
+#define ARC_FARM_KDMA_CTX_COMMIT_SRC_SIZE2_FROM_DST_SIZE2_SHIFT 17
+#define ARC_FARM_KDMA_CTX_COMMIT_SRC_SIZE2_FROM_DST_SIZE2_MASK 0x20000
+#define ARC_FARM_KDMA_CTX_COMMIT_SRC_SIZE3_FROM_DST_SIZE3_SHIFT 18
+#define ARC_FARM_KDMA_CTX_COMMIT_SRC_SIZE3_FROM_DST_SIZE3_MASK 0x40000
+#define ARC_FARM_KDMA_CTX_COMMIT_SRC_SIZE4_FROM_DST_SIZE4_SHIFT 19
+#define ARC_FARM_KDMA_CTX_COMMIT_SRC_SIZE4_FROM_DST_SIZE4_MASK 0x80000
+#define ARC_FARM_KDMA_CTX_COMMIT_SRC_STRD1_FROM_DST_STRD1_SHIFT 20
+#define ARC_FARM_KDMA_CTX_COMMIT_SRC_STRD1_FROM_DST_STRD1_MASK 0x100000
+#define ARC_FARM_KDMA_CTX_COMMIT_SRC_STRD2_FROM_DST_STRD2_SHIFT 21
+#define ARC_FARM_KDMA_CTX_COMMIT_SRC_STRD2_FROM_DST_STRD2_MASK 0x200000
+#define ARC_FARM_KDMA_CTX_COMMIT_SRC_STRD3_FROM_DST_STRD3_SHIFT 22
+#define ARC_FARM_KDMA_CTX_COMMIT_SRC_STRD3_FROM_DST_STRD3_MASK 0x400000
+#define ARC_FARM_KDMA_CTX_COMMIT_SRC_STRD4_FROM_DST_STRD4_SHIFT 23
+#define ARC_FARM_KDMA_CTX_COMMIT_SRC_STRD4_FROM_DST_STRD4_MASK 0x800000
+#define ARC_FARM_KDMA_CTX_COMMIT_LIN_SHIFT 31
+#define ARC_FARM_KDMA_CTX_COMMIT_LIN_MASK 0x80000000
+
+#endif /* ASIC_REG_ARC_FARM_KDMA_CTX_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_ctx_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_ctx_regs.h
new file mode 100644
index 000000000000..b9f09e8199e6
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_ctx_regs.h
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_ARC_FARM_KDMA_CTX_REGS_H_
+#define ASIC_REG_ARC_FARM_KDMA_CTX_REGS_H_
+
+/*
+ *****************************************
+ *   ARC_FARM_KDMA_CTX
+ *   (Prototype: DMA_CORE_CTX)
+ *****************************************
+ */
+
+#define mmARC_FARM_KDMA_CTX_RATE_LIM_TKN 0x4E8B860
+
+#define mmARC_FARM_KDMA_CTX_PWRLP 0x4E8B864
+
+#define mmARC_FARM_KDMA_CTX_TE_NUMROWS 0x4E8B868
+
+#define mmARC_FARM_KDMA_CTX_IDX 0x4E8B86C
+
+#define mmARC_FARM_KDMA_CTX_IDX_INC 0x4E8B870
+
+#define mmARC_FARM_KDMA_CTX_CTRL 0x4E8B874
+
+#define mmARC_FARM_KDMA_CTX_SRC_TSIZE_0 0x4E8B878
+
+#define mmARC_FARM_KDMA_CTX_SRC_TSIZE_1 0x4E8B87C
+
+#define mmARC_FARM_KDMA_CTX_SRC_STRIDE_1 0x4E8B880
+
+#define mmARC_FARM_KDMA_CTX_SRC_TSIZE_2 0x4E8B884
+
+#define mmARC_FARM_KDMA_CTX_SRC_STRIDE_2 0x4E8B888
+
+#define mmARC_FARM_KDMA_CTX_SRC_TSIZE_3 0x4E8B88C
+
+#define mmARC_FARM_KDMA_CTX_SRC_STRIDE_3 0x4E8B890
+
+#define mmARC_FARM_KDMA_CTX_SRC_TSIZE_4 0x4E8B894
+
+#define mmARC_FARM_KDMA_CTX_SRC_STRIDE_4 0x4E8B898
+
+#define mmARC_FARM_KDMA_CTX_DST_TSIZE_1 0x4E8B89C
+
+#define mmARC_FARM_KDMA_CTX_DST_STRIDE_1 0x4E8B8A0
+
+#define mmARC_FARM_KDMA_CTX_DST_TSIZE_2 0x4E8B8A4
+
+#define mmARC_FARM_KDMA_CTX_DST_STRIDE_2 0x4E8B8A8
+
+#define mmARC_FARM_KDMA_CTX_DST_TSIZE_3 0x4E8B8AC
+
+#define mmARC_FARM_KDMA_CTX_DST_STRIDE_3 0x4E8B8B0
+
+#define mmARC_FARM_KDMA_CTX_DST_TSIZE_4 0x4E8B8B4
+
+#define mmARC_FARM_KDMA_CTX_DST_STRIDE_4 0x4E8B8B8
+
+#define mmARC_FARM_KDMA_CTX_WR_COMP_ADDR_HI 0x4E8B8BC
+
+#define mmARC_FARM_KDMA_CTX_WR_COMP_ADDR_LO 0x4E8B8C0
+
+#define mmARC_FARM_KDMA_CTX_WR_COMP_WDATA 0x4E8B8C4
+
+#define mmARC_FARM_KDMA_CTX_SRC_OFFSET_LO 0x4E8B8C8
+
+#define mmARC_FARM_KDMA_CTX_SRC_OFFSET_HI 0x4E8B8CC
+
+#define mmARC_FARM_KDMA_CTX_DST_OFFSET_LO 0x4E8B8D0
+
+#define mmARC_FARM_KDMA_CTX_DST_OFFSET_HI 0x4E8B8D4
+
+#define mmARC_FARM_KDMA_CTX_SRC_BASE_LO 0x4E8B8D8
+
+#define mmARC_FARM_KDMA_CTX_SRC_BASE_HI 0x4E8B8DC
+
+#define mmARC_FARM_KDMA_CTX_DST_BASE_LO 0x4E8B8E0
+
+#define mmARC_FARM_KDMA_CTX_DST_BASE_HI 0x4E8B8E4
+
+#define mmARC_FARM_KDMA_CTX_DST_TSIZE_0 0x4E8B8E8
+
+#define mmARC_FARM_KDMA_CTX_COMMIT 0x4E8B8EC
+
+#endif /* ASIC_REG_ARC_FARM_KDMA_CTX_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_kdma_cgm_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_kdma_cgm_regs.h
new file mode 100644
index 000000000000..d6dd2c066fa9
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_kdma_cgm_regs.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_ARC_FARM_KDMA_KDMA_CGM_REGS_H_
+#define ASIC_REG_ARC_FARM_KDMA_KDMA_CGM_REGS_H_
+
+/*
+ *****************************************
+ *   ARC_FARM_KDMA_KDMA_CGM
+ *   (Prototype: QMAN_CGM)
+ *****************************************
+ */
+
+#define mmARC_FARM_KDMA_KDMA_CGM_CFG 0x4E8BE00
+
+#define mmARC_FARM_KDMA_KDMA_CGM_STS 0x4E8BE04
+
+#define mmARC_FARM_KDMA_KDMA_CGM_CFG1 0x4E8BE08
+
+#endif /* ASIC_REG_ARC_FARM_KDMA_KDMA_CGM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_masks.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_masks.h
new file mode 100644
index 000000000000..5903dbacec80
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_masks.h
@@ -0,0 +1,415 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_ARC_FARM_KDMA_MASKS_H_
+#define ASIC_REG_ARC_FARM_KDMA_MASKS_H_
+
+/*
+ *****************************************
+ *   ARC_FARM_KDMA
+ *   (Prototype: DMA_CORE)
+ *****************************************
+ */
+
+/* ARC_FARM_KDMA_CFG_0 */
+#define ARC_FARM_KDMA_CFG_0_EN_SHIFT 0
+#define ARC_FARM_KDMA_CFG_0_EN_MASK 0x1
+
+/* ARC_FARM_KDMA_CFG_1 */
+#define ARC_FARM_KDMA_CFG_1_HALT_SHIFT 0
+#define ARC_FARM_KDMA_CFG_1_HALT_MASK 0x1
+#define ARC_FARM_KDMA_CFG_1_FLUSH_SHIFT 1
+#define ARC_FARM_KDMA_CFG_1_FLUSH_MASK 0x2
+
+/* ARC_FARM_KDMA_PROT */
+#define ARC_FARM_KDMA_PROT_VAL_SHIFT 0
+#define ARC_FARM_KDMA_PROT_VAL_MASK 0x1
+#define ARC_FARM_KDMA_PROT_ERR_VAL_SHIFT 1
+#define ARC_FARM_KDMA_PROT_ERR_VAL_MASK 0x2
+
+/* ARC_FARM_KDMA_CKG */
+#define ARC_FARM_KDMA_CKG_HBW_RBUF_SHIFT 0
+#define ARC_FARM_KDMA_CKG_HBW_RBUF_MASK 0x1
+#define ARC_FARM_KDMA_CKG_LBW_RBUF_KDMA_SHIFT 1
+#define ARC_FARM_KDMA_CKG_LBW_RBUF_KDMA_MASK 0x2
+#define ARC_FARM_KDMA_CKG_TE_SHIFT 2
+#define ARC_FARM_KDMA_CKG_TE_MASK 0x4
+
+/* ARC_FARM_KDMA_RD_GLBL */
+#define ARC_FARM_KDMA_RD_GLBL_LBW_VIA_HBW_SHIFT 0
+#define ARC_FARM_KDMA_RD_GLBL_LBW_VIA_HBW_MASK 0x1
+#define ARC_FARM_KDMA_RD_GLBL_HBW_FORCE_MISS_SHIFT 4
+#define ARC_FARM_KDMA_RD_GLBL_HBW_FORCE_MISS_MASK 0x10
+#define ARC_FARM_KDMA_RD_GLBL_LBW_FORCE_MISS_SHIFT 5
+#define ARC_FARM_KDMA_RD_GLBL_LBW_FORCE_MISS_MASK 0x20
+
+/* ARC_FARM_KDMA_RD_HBW_MAX_OUTSTAND */
+#define ARC_FARM_KDMA_RD_HBW_MAX_OUTSTAND_VAL_SHIFT 0
+#define ARC_FARM_KDMA_RD_HBW_MAX_OUTSTAND_VAL_MASK 0xFFF
+
+/* ARC_FARM_KDMA_RD_HBW_MAX_SIZE */
+#define ARC_FARM_KDMA_RD_HBW_MAX_SIZE_DATA_SHIFT 0
+#define ARC_FARM_KDMA_RD_HBW_MAX_SIZE_DATA_MASK 0xFFF
+#define ARC_FARM_KDMA_RD_HBW_MAX_SIZE_MD_SHIFT 16
+#define ARC_FARM_KDMA_RD_HBW_MAX_SIZE_MD_MASK 0xFFF0000
+
+/* ARC_FARM_KDMA_RD_HBW_ARCACHE */
+#define ARC_FARM_KDMA_RD_HBW_ARCACHE_VAL_SHIFT 0
+#define ARC_FARM_KDMA_RD_HBW_ARCACHE_VAL_MASK 0xF
+
+/* ARC_FARM_KDMA_RD_HBW_INFLIGHTS */
+#define ARC_FARM_KDMA_RD_HBW_INFLIGHTS_VAL_SHIFT 0
+#define ARC_FARM_KDMA_RD_HBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_RD_HBW_RATE_LIM_CFG */
+#define ARC_FARM_KDMA_RD_HBW_RATE_LIM_CFG_TOUT_SHIFT 0
+#define ARC_FARM_KDMA_RD_HBW_RATE_LIM_CFG_TOUT_MASK 0xFF
+#define ARC_FARM_KDMA_RD_HBW_RATE_LIM_CFG_SAT_SHIFT 16
+#define ARC_FARM_KDMA_RD_HBW_RATE_LIM_CFG_SAT_MASK 0xFF0000
+#define ARC_FARM_KDMA_RD_HBW_RATE_LIM_CFG_EN_SHIFT 31
+#define ARC_FARM_KDMA_RD_HBW_RATE_LIM_CFG_EN_MASK 0x80000000
+
+/* ARC_FARM_KDMA_RD_LBW_MAX_OUTSTAND */
+#define ARC_FARM_KDMA_RD_LBW_MAX_OUTSTAND_VAL_SHIFT 0
+#define ARC_FARM_KDMA_RD_LBW_MAX_OUTSTAND_VAL_MASK 0xFFF
+
+/* ARC_FARM_KDMA_RD_LBW_MAX_SIZE */
+#define ARC_FARM_KDMA_RD_LBW_MAX_SIZE_DATA_SHIFT 0
+#define ARC_FARM_KDMA_RD_LBW_MAX_SIZE_DATA_MASK 0xFFF
+#define ARC_FARM_KDMA_RD_LBW_MAX_SIZE_MD_SHIFT 16
+#define ARC_FARM_KDMA_RD_LBW_MAX_SIZE_MD_MASK 0xFFF0000
+
+/* ARC_FARM_KDMA_RD_LBW_ARCACHE */
+#define ARC_FARM_KDMA_RD_LBW_ARCACHE_VAL_SHIFT 0
+#define ARC_FARM_KDMA_RD_LBW_ARCACHE_VAL_MASK 0xF
+
+/* ARC_FARM_KDMA_RD_LBW_INFLIGHTS */
+#define ARC_FARM_KDMA_RD_LBW_INFLIGHTS_VAL_SHIFT 0
+#define ARC_FARM_KDMA_RD_LBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_RD_LBW_RATE_LIM_CFG */
+#define ARC_FARM_KDMA_RD_LBW_RATE_LIM_CFG_TOUT_SHIFT 0
+#define ARC_FARM_KDMA_RD_LBW_RATE_LIM_CFG_TOUT_MASK 0xFF
+#define ARC_FARM_KDMA_RD_LBW_RATE_LIM_CFG_SAT_SHIFT 16
+#define ARC_FARM_KDMA_RD_LBW_RATE_LIM_CFG_SAT_MASK 0xFF0000
+#define ARC_FARM_KDMA_RD_LBW_RATE_LIM_CFG_EN_SHIFT 31
+#define ARC_FARM_KDMA_RD_LBW_RATE_LIM_CFG_EN_MASK 0x80000000
+
+/* ARC_FARM_KDMA_WR_HBW_MAX_OUTSTAND */
+#define ARC_FARM_KDMA_WR_HBW_MAX_OUTSTAND_VAL_SHIFT 0
+#define ARC_FARM_KDMA_WR_HBW_MAX_OUTSTAND_VAL_MASK 0xFFFF
+
+/* ARC_FARM_KDMA_WR_HBW_MAX_AWID */
+#define ARC_FARM_KDMA_WR_HBW_MAX_AWID_VAL_SHIFT 0
+#define ARC_FARM_KDMA_WR_HBW_MAX_AWID_VAL_MASK 0x3FFF
+
+/* ARC_FARM_KDMA_WR_HBW_AWCACHE */
+#define ARC_FARM_KDMA_WR_HBW_AWCACHE_VAL_SHIFT 0
+#define ARC_FARM_KDMA_WR_HBW_AWCACHE_VAL_MASK 0xF
+
+/* ARC_FARM_KDMA_WR_HBW_INFLIGHTS */
+#define ARC_FARM_KDMA_WR_HBW_INFLIGHTS_VAL_SHIFT 0
+#define ARC_FARM_KDMA_WR_HBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_WR_HBW_RATE_LIM_CFG */
+#define ARC_FARM_KDMA_WR_HBW_RATE_LIM_CFG_TOUT_SHIFT 0
+#define ARC_FARM_KDMA_WR_HBW_RATE_LIM_CFG_TOUT_MASK 0xFF
+#define ARC_FARM_KDMA_WR_HBW_RATE_LIM_CFG_SAT_SHIFT 16
+#define ARC_FARM_KDMA_WR_HBW_RATE_LIM_CFG_SAT_MASK 0xFF0000
+#define ARC_FARM_KDMA_WR_HBW_RATE_LIM_CFG_EN_SHIFT 31
+#define ARC_FARM_KDMA_WR_HBW_RATE_LIM_CFG_EN_MASK 0x80000000
+
+/* ARC_FARM_KDMA_WR_LBW_MAX_OUTSTAND */
+#define ARC_FARM_KDMA_WR_LBW_MAX_OUTSTAND_VAL_SHIFT 0
+#define ARC_FARM_KDMA_WR_LBW_MAX_OUTSTAND_VAL_MASK 0xFFFF
+
+/* ARC_FARM_KDMA_WR_LBW_MAX_AWID */
+#define ARC_FARM_KDMA_WR_LBW_MAX_AWID_VAL_SHIFT 0
+#define ARC_FARM_KDMA_WR_LBW_MAX_AWID_VAL_MASK 0x7F
+
+/* ARC_FARM_KDMA_WR_LBW_AWCACHE */
+#define ARC_FARM_KDMA_WR_LBW_AWCACHE_VAL_SHIFT 0
+#define ARC_FARM_KDMA_WR_LBW_AWCACHE_VAL_MASK 0xF
+
+/* ARC_FARM_KDMA_WR_LBW_INFLIGHTS */
+#define ARC_FARM_KDMA_WR_LBW_INFLIGHTS_VAL_SHIFT 0
+#define ARC_FARM_KDMA_WR_LBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_WR_LBW_RATE_LIM_CFG */
+#define ARC_FARM_KDMA_WR_LBW_RATE_LIM_CFG_TOUT_SHIFT 0
+#define ARC_FARM_KDMA_WR_LBW_RATE_LIM_CFG_TOUT_MASK 0xFF
+#define ARC_FARM_KDMA_WR_LBW_RATE_LIM_CFG_SAT_SHIFT 16
+#define ARC_FARM_KDMA_WR_LBW_RATE_LIM_CFG_SAT_MASK 0xFF0000
+#define ARC_FARM_KDMA_WR_LBW_RATE_LIM_CFG_EN_SHIFT 31
+#define ARC_FARM_KDMA_WR_LBW_RATE_LIM_CFG_EN_MASK 0x80000000
+
+/* ARC_FARM_KDMA_WR_COMP_MAX_OUTSTAND */
+#define ARC_FARM_KDMA_WR_COMP_MAX_OUTSTAND_VAL_SHIFT 0
+#define ARC_FARM_KDMA_WR_COMP_MAX_OUTSTAND_VAL_MASK 0x1F
+
+/* ARC_FARM_KDMA_WR_COMP_AWUSER */
+#define ARC_FARM_KDMA_WR_COMP_AWUSER_VAL_SHIFT 0
+#define ARC_FARM_KDMA_WR_COMP_AWUSER_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_ERR_CFG */
+#define ARC_FARM_KDMA_ERR_CFG_ERR_MSG_EN_SHIFT 0
+#define ARC_FARM_KDMA_ERR_CFG_ERR_MSG_EN_MASK 0x1
+#define ARC_FARM_KDMA_ERR_CFG_STOP_ON_ERR_SHIFT 1
+#define ARC_FARM_KDMA_ERR_CFG_STOP_ON_ERR_MASK 0x2
+
+/* ARC_FARM_KDMA_ERR_CAUSE */
+#define ARC_FARM_KDMA_ERR_CAUSE_HBW_RD_ERR_SHIFT 0
+#define ARC_FARM_KDMA_ERR_CAUSE_HBW_RD_ERR_MASK 0x1
+#define ARC_FARM_KDMA_ERR_CAUSE_HBW_WR_ERR_SHIFT 1
+#define ARC_FARM_KDMA_ERR_CAUSE_HBW_WR_ERR_MASK 0x2
+#define ARC_FARM_KDMA_ERR_CAUSE_LBW_MSG_WR_ERR_SHIFT 2
+#define ARC_FARM_KDMA_ERR_CAUSE_LBW_MSG_WR_ERR_MASK 0x4
+#define ARC_FARM_KDMA_ERR_CAUSE_DESC_OVF_SHIFT 3
+#define ARC_FARM_KDMA_ERR_CAUSE_DESC_OVF_MASK 0x8
+#define ARC_FARM_KDMA_ERR_CAUSE_LBW_RD_ERR_SHIFT 4
+#define ARC_FARM_KDMA_ERR_CAUSE_LBW_RD_ERR_MASK 0x10
+#define ARC_FARM_KDMA_ERR_CAUSE_LBW_WR_ERR_SHIFT 5
+#define ARC_FARM_KDMA_ERR_CAUSE_LBW_WR_ERR_MASK 0x20
+#define ARC_FARM_KDMA_ERR_CAUSE_TE_DESC_FIFO_OVFL_SHIFT 6
+#define ARC_FARM_KDMA_ERR_CAUSE_TE_DESC_FIFO_OVFL_MASK 0x40
+#define ARC_FARM_KDMA_ERR_CAUSE_LIN_DMA_COMMIT_CFG_ERR_SHIFT 7
+#define ARC_FARM_KDMA_ERR_CAUSE_LIN_DMA_COMMIT_CFG_ERR_MASK 0x80
+
+/* ARC_FARM_KDMA_ERRMSG_ADDR_LO */
+#define ARC_FARM_KDMA_ERRMSG_ADDR_LO_VAL_SHIFT 0
+#define ARC_FARM_KDMA_ERRMSG_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_ERRMSG_ADDR_HI */
+#define ARC_FARM_KDMA_ERRMSG_ADDR_HI_VAL_SHIFT 0
+#define ARC_FARM_KDMA_ERRMSG_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_ERRMSG_WDATA */
+#define ARC_FARM_KDMA_ERRMSG_WDATA_VAL_SHIFT 0
+#define ARC_FARM_KDMA_ERRMSG_WDATA_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_STS0 */
+#define ARC_FARM_KDMA_STS0_RD_REQ_CNT_SHIFT 0
+#define ARC_FARM_KDMA_STS0_RD_REQ_CNT_MASK 0x7FFF
+#define ARC_FARM_KDMA_STS0_WR_REQ_CNT_SHIFT 16
+#define ARC_FARM_KDMA_STS0_WR_REQ_CNT_MASK 0x7FFF0000
+#define ARC_FARM_KDMA_STS0_BUSY_SHIFT 31
+#define ARC_FARM_KDMA_STS0_BUSY_MASK 0x80000000
+
+/* ARC_FARM_KDMA_STS1 */
+#define ARC_FARM_KDMA_STS1_IS_HALT_SHIFT 0
+#define ARC_FARM_KDMA_STS1_IS_HALT_MASK 0x1
+
+/* ARC_FARM_KDMA_STS_RD_CTX_SEL */
+#define ARC_FARM_KDMA_STS_RD_CTX_SEL_VAL_SHIFT 0
+#define ARC_FARM_KDMA_STS_RD_CTX_SEL_VAL_MASK 0x7
+#define ARC_FARM_KDMA_STS_RD_CTX_SEL_STRIDE_SHIFT 8
+#define ARC_FARM_KDMA_STS_RD_CTX_SEL_STRIDE_MASK 0x100
+
+/* ARC_FARM_KDMA_STS_RD_CTX_SIZE */
+#define ARC_FARM_KDMA_STS_RD_CTX_SIZE_VAL_SHIFT 0
+#define ARC_FARM_KDMA_STS_RD_CTX_SIZE_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_STS_RD_CTX_BASE_LO */
+#define ARC_FARM_KDMA_STS_RD_CTX_BASE_LO_VAL_SHIFT 0
+#define ARC_FARM_KDMA_STS_RD_CTX_BASE_LO_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_STS_RD_CTX_BASE_HI */
+#define ARC_FARM_KDMA_STS_RD_CTX_BASE_HI_VAL_SHIFT 0
+#define ARC_FARM_KDMA_STS_RD_CTX_BASE_HI_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_STS_RD_CTX_ID */
+#define ARC_FARM_KDMA_STS_RD_CTX_ID_VAL_SHIFT 0
+#define ARC_FARM_KDMA_STS_RD_CTX_ID_VAL_MASK 0xFFFF
+
+/* ARC_FARM_KDMA_STS_RD_HB_AXI_ADDR_LO */
+#define ARC_FARM_KDMA_STS_RD_HB_AXI_ADDR_LO_VAL_SHIFT 0
+#define ARC_FARM_KDMA_STS_RD_HB_AXI_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_STS_RD_HB_AXI_ADDR_HI */
+#define ARC_FARM_KDMA_STS_RD_HB_AXI_ADDR_HI_VAL_SHIFT 0
+#define ARC_FARM_KDMA_STS_RD_HB_AXI_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_STS_RD_LB_AXI_ADDR */
+#define ARC_FARM_KDMA_STS_RD_LB_AXI_ADDR_VAL_SHIFT 0
+#define ARC_FARM_KDMA_STS_RD_LB_AXI_ADDR_VAL_MASK 0x3FFFFFF
+#define ARC_FARM_KDMA_STS_RD_LB_AXI_ADDR_RDY_SHIFT 30
+#define ARC_FARM_KDMA_STS_RD_LB_AXI_ADDR_RDY_MASK 0x40000000
+#define ARC_FARM_KDMA_STS_RD_LB_AXI_ADDR_VLD_SHIFT 31
+#define ARC_FARM_KDMA_STS_RD_LB_AXI_ADDR_VLD_MASK 0x80000000
+
+/* ARC_FARM_KDMA_STS_WR_CTX_SEL */
+#define ARC_FARM_KDMA_STS_WR_CTX_SEL_VAL_SHIFT 0
+#define ARC_FARM_KDMA_STS_WR_CTX_SEL_VAL_MASK 0x7
+#define ARC_FARM_KDMA_STS_WR_CTX_SEL_STRIDE_SHIFT 8
+#define ARC_FARM_KDMA_STS_WR_CTX_SEL_STRIDE_MASK 0x100
+
+/* ARC_FARM_KDMA_STS_WR_CTX_SIZE */
+#define ARC_FARM_KDMA_STS_WR_CTX_SIZE_VAL_SHIFT 0
+#define ARC_FARM_KDMA_STS_WR_CTX_SIZE_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_STS_WR_CTX_BASE_LO */
+#define ARC_FARM_KDMA_STS_WR_CTX_BASE_LO_VAL_SHIFT 0
+#define ARC_FARM_KDMA_STS_WR_CTX_BASE_LO_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_STS_WR_CTX_BASE_HI */
+#define ARC_FARM_KDMA_STS_WR_CTX_BASE_HI_VAL_SHIFT 0
+#define ARC_FARM_KDMA_STS_WR_CTX_BASE_HI_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_STS_WR_CTX_ID */
+#define ARC_FARM_KDMA_STS_WR_CTX_ID_VAL_SHIFT 0
+#define ARC_FARM_KDMA_STS_WR_CTX_ID_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_LO */
+#define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_LO_VAL_SHIFT 0
+#define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_LO_VAL_MASK 0x3FFFF
+#define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_LO_RDY_SHIFT 30
+#define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_LO_RDY_MASK 0x40000000
+#define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_LO_VLD_SHIFT 31
+#define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_LO_VLD_MASK 0x80000000
+
+/* ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_HI */
+#define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_HI_VAL_SHIFT 0
+#define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_HI_VAL_MASK 0x3FFFF
+#define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_HI_RDY_SHIFT 30
+#define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_HI_RDY_MASK 0x40000000
+#define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_HI_VLD_SHIFT 31
+#define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_HI_VLD_MASK 0x80000000
+
+/* ARC_FARM_KDMA_STS_WR_LB_AXI_ADDR */
+#define ARC_FARM_KDMA_STS_WR_LB_AXI_ADDR_VAL_SHIFT 0
+#define ARC_FARM_KDMA_STS_WR_LB_AXI_ADDR_VAL_MASK 0x3FFFFFF
+#define ARC_FARM_KDMA_STS_WR_LB_AXI_ADDR_RDY_SHIFT 30
+#define ARC_FARM_KDMA_STS_WR_LB_AXI_ADDR_RDY_MASK 0x40000000
+#define ARC_FARM_KDMA_STS_WR_LB_AXI_ADDR_VLD_SHIFT 31
+#define ARC_FARM_KDMA_STS_WR_LB_AXI_ADDR_VLD_MASK 0x80000000
+
+/* ARC_FARM_KDMA_PWRLP_CFG */
+#define ARC_FARM_KDMA_PWRLP_CFG_GLBL_EN_SHIFT 0
+#define ARC_FARM_KDMA_PWRLP_CFG_GLBL_EN_MASK 0x1
+#define ARC_FARM_KDMA_PWRLP_CFG_CLR_SHIFT 4
+#define ARC_FARM_KDMA_PWRLP_CFG_CLR_MASK 0x10
+
+/* ARC_FARM_KDMA_PWRLP_STS */
+#define ARC_FARM_KDMA_PWRLP_STS_RLVL_SHIFT 0
+#define ARC_FARM_KDMA_PWRLP_STS_RLVL_MASK 0x7F
+#define ARC_FARM_KDMA_PWRLP_STS_WLVL_SHIFT 8
+#define ARC_FARM_KDMA_PWRLP_STS_WLVL_MASK 0x7F00
+#define ARC_FARM_KDMA_PWRLP_STS_RCNT_SHIFT 16
+#define ARC_FARM_KDMA_PWRLP_STS_RCNT_MASK 0x7F0000
+#define ARC_FARM_KDMA_PWRLP_STS_WCNT_SHIFT 23
+#define ARC_FARM_KDMA_PWRLP_STS_WCNT_MASK 0x3F800000
+#define ARC_FARM_KDMA_PWRLP_STS_RFULL_SHIFT 30
+#define ARC_FARM_KDMA_PWRLP_STS_RFULL_MASK 0x40000000
+#define ARC_FARM_KDMA_PWRLP_STS_WFULL_SHIFT 31
+#define ARC_FARM_KDMA_PWRLP_STS_WFULL_MASK 0x80000000
+
+/* ARC_FARM_KDMA_DBG_DESC_CNT */
+#define ARC_FARM_KDMA_DBG_DESC_CNT_VAL_SHIFT 0
+#define ARC_FARM_KDMA_DBG_DESC_CNT_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_DBG_STS */
+#define ARC_FARM_KDMA_DBG_STS_RD_CTX_FULL_SHIFT 0
+#define ARC_FARM_KDMA_DBG_STS_RD_CTX_FULL_MASK 0x1
+#define ARC_FARM_KDMA_DBG_STS_WR_CTX_FULL_SHIFT 1
+#define ARC_FARM_KDMA_DBG_STS_WR_CTX_FULL_MASK 0x2
+#define ARC_FARM_KDMA_DBG_STS_WR_COMP_FULL_SHIFT 2
+#define ARC_FARM_KDMA_DBG_STS_WR_COMP_FULL_MASK 0x4
+#define ARC_FARM_KDMA_DBG_STS_RD_CTX_EMPTY_SHIFT 3
+#define ARC_FARM_KDMA_DBG_STS_RD_CTX_EMPTY_MASK 0x8
+#define ARC_FARM_KDMA_DBG_STS_WR_CTX_EMPTY_SHIFT 4
+#define ARC_FARM_KDMA_DBG_STS_WR_CTX_EMPTY_MASK 0x10
+#define ARC_FARM_KDMA_DBG_STS_WR_COMP_EMPTY_SHIFT 5
+#define ARC_FARM_KDMA_DBG_STS_WR_COMP_EMPTY_MASK 0x20
+#define ARC_FARM_KDMA_DBG_STS_TE_EMPTY_SHIFT 6
+#define ARC_FARM_KDMA_DBG_STS_TE_EMPTY_MASK 0x40
+#define ARC_FARM_KDMA_DBG_STS_TE_BUSY_SHIFT 7
+#define ARC_FARM_KDMA_DBG_STS_TE_BUSY_MASK 0x80
+#define ARC_FARM_KDMA_DBG_STS_GSKT_EMPTY_SHIFT 8
+#define ARC_FARM_KDMA_DBG_STS_GSKT_EMPTY_MASK 0x100
+#define ARC_FARM_KDMA_DBG_STS_GSKT_FULL_SHIFT 9
+#define ARC_FARM_KDMA_DBG_STS_GSKT_FULL_MASK 0x200
+#define ARC_FARM_KDMA_DBG_STS_RD_AGU_CS_SHIFT 10
+#define ARC_FARM_KDMA_DBG_STS_RD_AGU_CS_MASK 0x400
+#define ARC_FARM_KDMA_DBG_STS_WR_AGU_CS_SHIFT 11
+#define ARC_FARM_KDMA_DBG_STS_WR_AGU_CS_MASK 0x800
+
+/* ARC_FARM_KDMA_DBG_BUF_STS */
+#define ARC_FARM_KDMA_DBG_BUF_STS_HBW_FULLNESS_SHIFT 0
+#define ARC_FARM_KDMA_DBG_BUF_STS_HBW_FULLNESS_MASK 0xFFF
+#define ARC_FARM_KDMA_DBG_BUF_STS_LBW_FULLNESS_SHIFT 16
+#define ARC_FARM_KDMA_DBG_BUF_STS_LBW_FULLNESS_MASK 0xFFF0000
+
+/* ARC_FARM_KDMA_DBG_RD_DESC_ID */
+#define ARC_FARM_KDMA_DBG_RD_DESC_ID_VAL_SHIFT 0
+#define ARC_FARM_KDMA_DBG_RD_DESC_ID_VAL_MASK 0xFFFF
+
+/* ARC_FARM_KDMA_DBG_WR_DESC_ID */
+#define ARC_FARM_KDMA_DBG_WR_DESC_ID_VAL_SHIFT 0
+#define ARC_FARM_KDMA_DBG_WR_DESC_ID_VAL_MASK 0xFFFF
+
+/* ARC_FARM_KDMA_APB_DMA_LBW_BASE */
+#define ARC_FARM_KDMA_APB_DMA_LBW_BASE_VAL_SHIFT 0
+#define ARC_FARM_KDMA_APB_DMA_LBW_BASE_VAL_MASK 0xFFFF
+
+/* ARC_FARM_KDMA_APB_MSTR_IF_LBW_BASE */
+#define ARC_FARM_KDMA_APB_MSTR_IF_LBW_BASE_VAL_SHIFT 0
+#define ARC_FARM_KDMA_APB_MSTR_IF_LBW_BASE_VAL_MASK 0xFFFF
+
+/* ARC_FARM_KDMA_E2E_CRED_ASYNC_CFG */
+#define ARC_FARM_KDMA_E2E_CRED_ASYNC_CFG_Y_X_FORCE_SHIFT 0
+#define ARC_FARM_KDMA_E2E_CRED_ASYNC_CFG_Y_X_FORCE_MASK 0x1FF
+#define ARC_FARM_KDMA_E2E_CRED_ASYNC_CFG_FORCE_EN_SHIFT 9
+#define ARC_FARM_KDMA_E2E_CRED_ASYNC_CFG_FORCE_EN_MASK 0x200
+
+/* ARC_FARM_KDMA_DBG_APB_ENABLER */
+#define ARC_FARM_KDMA_DBG_APB_ENABLER_DIS_SHIFT 0
+#define ARC_FARM_KDMA_DBG_APB_ENABLER_DIS_MASK 0x1
+
+/* ARC_FARM_KDMA_L2H_CMPR_LO */
+#define ARC_FARM_KDMA_L2H_CMPR_LO_VAL_SHIFT 20
+#define ARC_FARM_KDMA_L2H_CMPR_LO_VAL_MASK 0xFFF00000
+
+/* ARC_FARM_KDMA_L2H_CMPR_HI */
+#define ARC_FARM_KDMA_L2H_CMPR_HI_VAL_SHIFT 0
+#define ARC_FARM_KDMA_L2H_CMPR_HI_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_L2H_MASK_LO */
+#define ARC_FARM_KDMA_L2H_MASK_LO_VAL_SHIFT 20
+#define ARC_FARM_KDMA_L2H_MASK_LO_VAL_MASK 0xFFF00000
+
+/* ARC_FARM_KDMA_L2H_MASK_HI */
+#define ARC_FARM_KDMA_L2H_MASK_HI_VAL_SHIFT 0
+#define ARC_FARM_KDMA_L2H_MASK_HI_VAL_MASK 0xFFFFFFFF
+
+/* ARC_FARM_KDMA_IDLE_IND_MASK */
+#define ARC_FARM_KDMA_IDLE_IND_MASK_DESC_SHIFT 0
+#define ARC_FARM_KDMA_IDLE_IND_MASK_DESC_MASK 0x1
+#define ARC_FARM_KDMA_IDLE_IND_MASK_COMP_SHIFT 1
+#define ARC_FARM_KDMA_IDLE_IND_MASK_COMP_MASK 0x2
+#define ARC_FARM_KDMA_IDLE_IND_MASK_INSTAGE_SHIFT 2
+#define ARC_FARM_KDMA_IDLE_IND_MASK_INSTAGE_MASK 0x4
+#define ARC_FARM_KDMA_IDLE_IND_MASK_CORE_SHIFT 3
+#define ARC_FARM_KDMA_IDLE_IND_MASK_CORE_MASK 0x8
+#define ARC_FARM_KDMA_IDLE_IND_MASK_DESC_CNT_STS_SHIFT 8
+#define ARC_FARM_KDMA_IDLE_IND_MASK_DESC_CNT_STS_MASK 0x1F00
+#define ARC_FARM_KDMA_IDLE_IND_MASK_COMP_CNT_STS_SHIFT 16
+#define ARC_FARM_KDMA_IDLE_IND_MASK_COMP_CNT_STS_MASK 0x1F0000
+#define ARC_FARM_KDMA_IDLE_IND_MASK_INSTAGE_EMPTY_SHIFT 24
+#define ARC_FARM_KDMA_IDLE_IND_MASK_INSTAGE_EMPTY_MASK 0x1000000
+#define ARC_FARM_KDMA_IDLE_IND_MASK_CORE_IDLE_STS_SHIFT 25
+#define ARC_FARM_KDMA_IDLE_IND_MASK_CORE_IDLE_STS_MASK 0x2000000
+
+/* ARC_FARM_KDMA_APB_ENABLER */
+#define ARC_FARM_KDMA_APB_ENABLER_DIS_SHIFT 0
+#define ARC_FARM_KDMA_APB_ENABLER_DIS_MASK 0x1
+
+#endif /* ASIC_REG_ARC_FARM_KDMA_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_regs.h
new file mode 100644
index 000000000000..e312cf810c0e
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_regs.h
@@ -0,0 +1,157 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_ARC_FARM_KDMA_REGS_H_
+#define ASIC_REG_ARC_FARM_KDMA_REGS_H_
+
+/*
+ *****************************************
+ *   ARC_FARM_KDMA
+ *   (Prototype: DMA_CORE)
+ *****************************************
+ */
+
+#define mmARC_FARM_KDMA_CFG_0 0x4E8B000
+
+#define mmARC_FARM_KDMA_CFG_1 0x4E8B004
+
+#define mmARC_FARM_KDMA_PROT 0x4E8B008
+
+#define mmARC_FARM_KDMA_CKG 0x4E8B00C
+
+#define mmARC_FARM_KDMA_RD_GLBL 0x4E8B07C
+
+#define mmARC_FARM_KDMA_RD_HBW_MAX_OUTSTAND 0x4E8B080
+
+#define mmARC_FARM_KDMA_RD_HBW_MAX_SIZE 0x4E8B084
+
+#define mmARC_FARM_KDMA_RD_HBW_ARCACHE 0x4E8B088
+
+#define mmARC_FARM_KDMA_RD_HBW_INFLIGHTS 0x4E8B090
+
+#define mmARC_FARM_KDMA_RD_HBW_RATE_LIM_CFG 0x4E8B094
+
+#define mmARC_FARM_KDMA_RD_LBW_MAX_OUTSTAND 0x4E8B0C0
+
+#define mmARC_FARM_KDMA_RD_LBW_MAX_SIZE 0x4E8B0C4
+
+#define mmARC_FARM_KDMA_RD_LBW_ARCACHE 0x4E8B0C8
+
+#define mmARC_FARM_KDMA_RD_LBW_INFLIGHTS 0x4E8B0D0
+
+#define mmARC_FARM_KDMA_RD_LBW_RATE_LIM_CFG 0x4E8B0D4
+
+#define mmARC_FARM_KDMA_WR_HBW_MAX_OUTSTAND 0x4E8B100
+
+#define mmARC_FARM_KDMA_WR_HBW_MAX_AWID 0x4E8B104
+
+#define mmARC_FARM_KDMA_WR_HBW_AWCACHE 0x4E8B108
+
+#define mmARC_FARM_KDMA_WR_HBW_INFLIGHTS 0x4E8B10C
+
+#define mmARC_FARM_KDMA_WR_HBW_RATE_LIM_CFG 0x4E8B110
+
+#define mmARC_FARM_KDMA_WR_LBW_MAX_OUTSTAND 0x4E8B140
+
+#define mmARC_FARM_KDMA_WR_LBW_MAX_AWID 0x4E8B144
+
+#define mmARC_FARM_KDMA_WR_LBW_AWCACHE 0x4E8B148
+
+#define mmARC_FARM_KDMA_WR_LBW_INFLIGHTS 0x4E8B14C
+
+#define mmARC_FARM_KDMA_WR_LBW_RATE_LIM_CFG 0x4E8B150
+
+#define mmARC_FARM_KDMA_WR_COMP_MAX_OUTSTAND 0x4E8B180
+
+#define mmARC_FARM_KDMA_WR_COMP_AWUSER 0x4E8B184
+
+#define mmARC_FARM_KDMA_ERR_CFG 0x4E8B300
+
+#define mmARC_FARM_KDMA_ERR_CAUSE 0x4E8B304
+
+#define mmARC_FARM_KDMA_ERRMSG_ADDR_LO 0x4E8B308
+
+#define mmARC_FARM_KDMA_ERRMSG_ADDR_HI 0x4E8B30C
+
+#define mmARC_FARM_KDMA_ERRMSG_WDATA 0x4E8B310
+
+#define mmARC_FARM_KDMA_STS0 0x4E8B380
+
+#define mmARC_FARM_KDMA_STS1 0x4E8B384
+
+#define mmARC_FARM_KDMA_STS_RD_CTX_SEL 0x4E8B400
+
+#define mmARC_FARM_KDMA_STS_RD_CTX_SIZE 0x4E8B404
+
+#define mmARC_FARM_KDMA_STS_RD_CTX_BASE_LO 0x4E8B408
+
+#define mmARC_FARM_KDMA_STS_RD_CTX_BASE_HI 0x4E8B40C
+
+#define mmARC_FARM_KDMA_STS_RD_CTX_ID 0x4E8B410
+
+#define mmARC_FARM_KDMA_STS_RD_HB_AXI_ADDR_LO 0x4E8B414
+
+#define mmARC_FARM_KDMA_STS_RD_HB_AXI_ADDR_HI 0x4E8B418
+
+#define mmARC_FARM_KDMA_STS_RD_LB_AXI_ADDR 0x4E8B41C
+
+#define mmARC_FARM_KDMA_STS_WR_CTX_SEL 0x4E8B420
+
+#define mmARC_FARM_KDMA_STS_WR_CTX_SIZE 0x4E8B424
+
+#define mmARC_FARM_KDMA_STS_WR_CTX_BASE_LO 0x4E8B428
+
+#define mmARC_FARM_KDMA_STS_WR_CTX_BASE_HI 0x4E8B42C
+
+#define mmARC_FARM_KDMA_STS_WR_CTX_ID 0x4E8B430
+
+#define mmARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_LO 0x4E8B434
+
+#define mmARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_HI 0x4E8B438
+
+#define mmARC_FARM_KDMA_STS_WR_LB_AXI_ADDR 0x4E8B43C
+
+#define mmARC_FARM_KDMA_PWRLP_CFG 0x4E8B700
+
+#define mmARC_FARM_KDMA_PWRLP_STS 0x4E8B704
+
+#define mmARC_FARM_KDMA_DBG_DESC_CNT 0x4E8B710
+
+#define mmARC_FARM_KDMA_DBG_STS 0x4E8B714
+
+#define mmARC_FARM_KDMA_DBG_BUF_STS 0x4E8B718
+
+#define mmARC_FARM_KDMA_DBG_RD_DESC_ID 0x4E8B720
+
+#define mmARC_FARM_KDMA_DBG_WR_DESC_ID 0x4E8B724
+
+#define mmARC_FARM_KDMA_APB_DMA_LBW_BASE 0x4E8B728
+
+#define mmARC_FARM_KDMA_APB_MSTR_IF_LBW_BASE 0x4E8B72C
+
+#define mmARC_FARM_KDMA_E2E_CRED_ASYNC_CFG 0x4E8B730
+
+#define mmARC_FARM_KDMA_DBG_APB_ENABLER 0x4E8BE1C
+
+#define mmARC_FARM_KDMA_L2H_CMPR_LO 0x4E8BE20
+
+#define mmARC_FARM_KDMA_L2H_CMPR_HI 0x4E8BE24
+
+#define mmARC_FARM_KDMA_L2H_MASK_LO 0x4E8BE28
+
+#define mmARC_FARM_KDMA_L2H_MASK_HI 0x4E8BE2C
+
+#define mmARC_FARM_KDMA_IDLE_IND_MASK 0x4E8BE30
+
+#define mmARC_FARM_KDMA_APB_ENABLER 0x4E8BE34
+
+#endif /* ASIC_REG_ARC_FARM_KDMA_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/cpu_if_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/cpu_if_regs.h
new file mode 100644
index 000000000000..9b3eceec9d5d
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/cpu_if_regs.h
@@ -0,0 +1,777 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_CPU_IF_REGS_H_
+#define ASIC_REG_CPU_IF_REGS_H_
+
+/*
+ *****************************************
+ *   CPU_IF
+ *   (Prototype: CPU_IF)
+ *****************************************
+ */
+
+#define mmCPU_IF_ARUSER_OVR 0x4CC1104
+
+#define mmCPU_IF_ARUSER_OVR_EN 0x4CC1108
+
+#define mmCPU_IF_AWUSER_OVR 0x4CC110C
+
+#define mmCPU_IF_AWUSER_OVR_EN 0x4CC1110
+
+#define mmCPU_IF_ARUSER_MSB_OVR 0x4CC1114
+
+#define mmCPU_IF_AWUSER_MSB_OVR 0x4CC1120
+
+#define mmCPU_IF_AXCACHE_OVR 0x4CC1128
+
+#define mmCPU_IF_LOCK_OVR 0x4CC112C
+
+#define mmCPU_IF_PROT_OVR 0x4CC1130
+
+#define mmCPU_IF_MAX_OUTSTANDING 0x4CC1134
+
+#define mmCPU_IF_EARLY_BRESP_EN 0x4CC1138
+
+#define mmCPU_IF_FORCE_RSP_OK 0x4CC113C
+
+#define mmCPU_IF_CPU_SEI_INTR_STS 0x4CC1140
+
+#define mmCPU_IF_CPU_SEI_INTR_CLR 0x4CC1144
+
+#define mmCPU_IF_CPU_SEI_INTR_MASK 0x4CC1148
+
+#define mmCPU_IF_AXI_SPLIT_NO_WR_INFLIGHT 0x4CC114C
+
+#define mmCPU_IF_AXI_SPLIT_SEI_INTR_ID 0x4CC1150
+
+#define mmCPU_IF_TOTAL_WR_CNT 0x4CC1154
+
+#define mmCPU_IF_INFLIGHT_WR_CNT 0x4CC1158
+
+#define mmCPU_IF_TOTAL_RD_CNT 0x4CC115C
+
+#define mmCPU_IF_INFLIGHT_RD_CNT 0x4CC1160
+
+#define mmCPU_IF_SRAM_MSB_ADDR 0x4CC1164
+
+#define mmCPU_IF_CFG_MSB_ADDR 0x4CC1168
+
+#define mmCPU_IF_HBM_MSB_ADDR 0x4CC116C
+
+#define mmCPU_IF_PCIE_MSB_ADDR 0x4CC1170
+
+#define mmCPU_IF_KMD_HW_DIRTY_STATUS 0x4CC1174
+
+#define mmCPU_IF_MSTR_IF_E2E_FORCE_BP 0x4CC1188
+
+#define mmCPU_IF_MSTR_IF_E2E_GRCFL_CLR 0x4CC118C
+
+#define mmCPU_IF_LBW_TERMINATE_AWADDR_ERR 0x4CC11A0
+
+#define mmCPU_IF_LBW_TERMINATE_ARADDR_ERR 0x4CC11A4
+
+#define mmCPU_IF_CFG_LBW_TERMINATE_BRESP 0x4CC11A8
+
+#define mmCPU_IF_CFG_LBW_TERMINATE_RRESP 0x4CC11AC
+
+#define mmCPU_IF_PF_PQ_PI 0x4CC1200
+
+#define mmCPU_IF_PQ_BASE_ADDR_LOW 0x4CC1204
+
+#define mmCPU_IF_PQ_BASE_ADDR_HIGH 0x4CC1208
+
+#define mmCPU_IF_PQ_LENGTH 0x4CC120C
+
+#define mmCPU_IF_CQ_BASE_ADDR_LOW 0x4CC1210
+
+#define mmCPU_IF_CQ_BASE_ADDR_HIGH 0x4CC1214
+
+#define mmCPU_IF_CQ_LENGTH 0x4CC1218
+
+#define mmCPU_IF_EQ_BASE_ADDR_LOW 0x4CC1220
+
+#define mmCPU_IF_EQ_BASE_ADDR_HIGH 0x4CC1224
+
+#define mmCPU_IF_EQ_LENGTH 0x4CC1228
+
+#define mmCPU_IF_EQ_RD_OFFS 0x4CC122C
+
+#define mmCPU_IF_QUEUE_INIT 0x4CC1230
+
+#define mmCPU_IF_TPC_SERR_INTR_STS 0x4CC1300
+
+#define mmCPU_IF_TPC_SERR_INTR_CLR 0x4CC1304
+
+#define mmCPU_IF_TPC_SERR_INTR_MASK 0x4CC1308
+
+#define mmCPU_IF_TPC_DERR_INTR_STS 0x4CC1310
+
+#define mmCPU_IF_TPC_DERR_INTR_CLR 0x4CC1314
+
+#define mmCPU_IF_TPC_DERR_INTR_MASK 0x4CC1318
+
+#define mmCPU_IF_MME_SERR_INTR_STS_0 0x4CC1320
+
+#define mmCPU_IF_MME_SERR_INTR_STS_1 0x4CC1324
+
+#define mmCPU_IF_MME_SERR_INTR_STS_2 0x4CC1328
+
+#define mmCPU_IF_MME_SERR_INTR_STS_3 0x4CC132C
+
+#define mmCPU_IF_MME_SERR_INTR_CLR_0 0x4CC1330
+
+#define mmCPU_IF_MME_SERR_INTR_CLR_1 0x4CC1334
+
+#define mmCPU_IF_MME_SERR_INTR_CLR_2 0x4CC1338
+
+#define mmCPU_IF_MME_SERR_INTR_CLR_3 0x4CC133C
+
+#define mmCPU_IF_MME_SERR_INTR_MASK_0 0x4CC1340
+
+#define mmCPU_IF_MME_SERR_INTR_MASK_1 0x4CC1344
+
+#define mmCPU_IF_MME_SERR_INTR_MASK_2 0x4CC1348
+
+#define mmCPU_IF_MME_SERR_INTR_MASK_3 0x4CC134C
+
+#define mmCPU_IF_MME_DERR_INTR_STS_0 0x4CC1350
+
+#define mmCPU_IF_MME_DERR_INTR_STS_1 0x4CC1354
+
+#define mmCPU_IF_MME_DERR_INTR_STS_2 0x4CC1358
+
+#define mmCPU_IF_MME_DERR_INTR_STS_3 0x4CC135C
+
+#define mmCPU_IF_MME_DERR_INTR_CLR_0 0x4CC1360
+
+#define mmCPU_IF_MME_DERR_INTR_CLR_1 0x4CC1364
+
+#define mmCPU_IF_MME_DERR_INTR_CLR_2 0x4CC1368
+
+#define mmCPU_IF_MME_DERR_INTR_CLR_3 0x4CC136C
+
+#define mmCPU_IF_MME_DERR_INTR_MASK_0 0x4CC1370
+
+#define mmCPU_IF_MME_DERR_INTR_MASK_1 0x4CC1374
+
+#define mmCPU_IF_MME_DERR_INTR_MASK_2 0x4CC1378
+
+#define mmCPU_IF_MME_DERR_INTR_MASK_3 0x4CC137C
+
+#define mmCPU_IF_HDMA_SERR_INTR_STS 0x4CC1380
+
+#define mmCPU_IF_HDMA_SERR_INTR_CLR 0x4CC1384
+
+#define mmCPU_IF_HDMA_SERR_INTR_MASK 0x4CC1388
+
+#define mmCPU_IF_HDMA_DERR_INTR_STS 0x4CC1390
+
+#define mmCPU_IF_HDMA_DERR_INTR_CLR 0x4CC1394
+
+#define mmCPU_IF_HDMA_DERR_INTR_MASK 0x4CC1398
+
+#define mmCPU_IF_PDMA_SERR_INTR_STS 0x4CC13A0
+
+#define mmCPU_IF_PDMA_SERR_INTR_CLR 0x4CC13A4
+
+#define mmCPU_IF_PDMA_SERR_INTR_MASK 0x4CC13A8
+
+#define mmCPU_IF_PDMA_DERR_INTR_STS 0x4CC13B0
+
+#define mmCPU_IF_PDMA_DERR_INTR_CLR 0x4CC13B4
+
+#define mmCPU_IF_PDMA_DERR_INTR_MASK 0x4CC13B8
+
+#define mmCPU_IF_SRAM_SERR_INTR_STS 0x4CC13C0
+
+#define mmCPU_IF_SRAM_SERR_INTR_CLR 0x4CC13C4
+
+#define mmCPU_IF_SRAM_SERR_INTR_MASK 0x4CC13C8
+
+#define mmCPU_IF_SRAM_DERR_INTR_STS 0x4CC13D0
+
+#define mmCPU_IF_SRAM_DERR_INTR_CLR 0x4CC13D4
+
+#define mmCPU_IF_SRAM_DERR_INTR_MASK 0x4CC13D8
+
+#define mmCPU_IF_HBM_SERR_INTR_STS 0x4CC13E0
+
+#define mmCPU_IF_HBM_SERR_INTR_CLR 0x4CC13E4
+
+#define mmCPU_IF_HBM_SERR_INTR_MASK 0x4CC13E8
+
+#define mmCPU_IF_HBM_DERR_INTR_STS 0x4CC13F0
+
+#define mmCPU_IF_HBM_DERR_INTR_CLR 0x4CC13F4
+
+#define mmCPU_IF_HBM_DERR_INTR_MASK 0x4CC13F8
+
+#define mmCPU_IF_HMMU_SERR_INTR_STS 0x4CC1400
+
+#define mmCPU_IF_HMMU_SERR_INTR_CLR 0x4CC1404
+
+#define mmCPU_IF_HMMU_SERR_INTR_MASK 0x4CC1408
+
+#define mmCPU_IF_HMMU_DERR_INTR_STS 0x4CC1410
+
+#define mmCPU_IF_HMMU_DERR_INTR_CLR 0x4CC1414
+
+#define mmCPU_IF_HMMU_DERR_INTR_MASK 0x4CC1418
+
+#define mmCPU_IF_DEC_SERR_INTR_STS 0x4CC1420
+
+#define mmCPU_IF_DEC_SERR_INTR_CLR 0x4CC1424
+
+#define mmCPU_IF_DEC_SERR_INTR_MASK 0x4CC1428
+
+#define mmCPU_IF_DEC_DERR_INTR_STS 0x4CC1430
+
+#define mmCPU_IF_DEC_DERR_INTR_CLR 0x4CC1434
+
+#define mmCPU_IF_DEC_DERR_INTR_MASK 0x4CC1438
+
+#define mmCPU_IF_NIC_SERR_INTR_STS 0x4CC1440
+
+#define mmCPU_IF_NIC_SERR_INTR_CLR 0x4CC1444
+
+#define mmCPU_IF_NIC_SERR_INTR_MASK 0x4CC1448
+
+#define mmCPU_IF_NIC_DERR_INTR_STS 0x4CC1450
+
+#define mmCPU_IF_NIC_DERR_INTR_CLR 0x4CC1454
+
+#define mmCPU_IF_NIC_DERR_INTR_MASK 0x4CC1458
+
+#define mmCPU_IF_SYNC_MNGR_SERR_INTR_STS 0x4CC1460
+
+#define mmCPU_IF_SYNC_MNGR_SERR_INTR_CLR 0x4CC1464
+
+#define mmCPU_IF_SYNC_MNGR_SERR_INTR_MASK 0x4CC1468
+
+#define mmCPU_IF_SYNC_MNGR_DERR_INTR_STS 0x4CC1470
+
+#define mmCPU_IF_SYNC_MNGR_DERR_INTR_CLR 0x4CC1474
+
+#define mmCPU_IF_SYNC_MNGR_DERR_INTR_MASK 0x4CC1478
+
+#define mmCPU_IF_HIF_SERR_INTR_STS 0x4CC1480
+
+#define mmCPU_IF_HIF_SERR_INTR_CLR 0x4CC1484
+
+#define mmCPU_IF_HIF_SERR_INTR_MASK 0x4CC1488
+
+#define mmCPU_IF_HIF_DERR_INTR_STS 0x4CC1490
+
+#define mmCPU_IF_HIF_DERR_INTR_CLR 0x4CC1494
+
+#define mmCPU_IF_HIF_DERR_INTR_MASK 0x4CC1498
+
+#define mmCPU_IF_XBAR_SERR_INTR_STS 0x4CC14A0
+
+#define mmCPU_IF_XBAR_SERR_INTR_CLR 0x4CC14A4
+
+#define mmCPU_IF_XBAR_SERR_INTR_MASK 0x4CC14A8
+
+#define mmCPU_IF_XBAR_DERR_INTR_STS 0x4CC14B0
+
+#define mmCPU_IF_XBAR_DERR_INTR_CLR 0x4CC14B4
+
+#define mmCPU_IF_XBAR_DERR_INTR_MASK 0x4CC14B8
+
+#define mmCPU_IF_TPC_SEI_INTR_STS 0x4CC14C0
+
+#define mmCPU_IF_TPC_SEI_INTR_CLR 0x4CC14C4
+
+#define mmCPU_IF_TPC_SEI_INTR_MASK 0x4CC14C8
+
+#define mmCPU_IF_MME_SEI_INTR_STS_0 0x4CC14D0
+
+#define mmCPU_IF_MME_SEI_INTR_STS_1 0x4CC14D4
+
+#define mmCPU_IF_MME_SEI_INTR_STS_2 0x4CC14D8
+
+#define mmCPU_IF_MME_SEI_INTR_STS_3 0x4CC14DC
+
+#define mmCPU_IF_MME_SEI_INTR_CLR_0 0x4CC14E0
+
+#define mmCPU_IF_MME_SEI_INTR_CLR_1 0x4CC14E4
+
+#define mmCPU_IF_MME_SEI_INTR_CLR_2 0x4CC14E8
+
+#define mmCPU_IF_MME_SEI_INTR_CLR_3 0x4CC14EC
+
+#define mmCPU_IF_MME_SEI_INTR_MASK_0 0x4CC14F0
+
+#define mmCPU_IF_MME_SEI_INTR_MASK_1 0x4CC14F4
+
+#define mmCPU_IF_MME_SEI_INTR_MASK_2 0x4CC14F8
+
+#define mmCPU_IF_MME_SEI_INTR_MASK_3 0x4CC14FC
+
+#define mmCPU_IF_PLL_LSB_SEI_INTR_STS 0x4CC1500
+
+#define mmCPU_IF_PLL_LSB_SEI_INTR_CLR 0x4CC1504
+
+#define mmCPU_IF_PLL_LSB_SEI_INTR_MASK 0x4CC1508
+
+#define mmCPU_IF_PLL_MSB_SEI_INTR_STS 0x4CC1510
+
+#define mmCPU_IF_PLL_MSB_SEI_INTR_CLR 0x4CC1514
+
+#define mmCPU_IF_PLL_MSB_SEI_INTR_MASK 0x4CC1518
+
+#define mmCPU_IF_HMMU_SEI_INTR_STS 0x4CC1520
+
+#define mmCPU_IF_HMMU_SEI_INTR_CLR 0x4CC1524
+
+#define mmCPU_IF_HMMU_SEI_INTR_MASK 0x4CC1528
+
+#define mmCPU_IF_HDMA_SEI_INTR_STS 0x4CC1530
+
+#define mmCPU_IF_HDMA_SEI_INTR_CLR 0x4CC1534
+
+#define mmCPU_IF_HDMA_SEI_INTR_MASK 0x4CC1538
+
+#define mmCPU_IF_PDMA_SEI_INTR_STS 0x4CC1540
+
+#define mmCPU_IF_PDMA_SEI_INTR_CLR 0x4CC1544
+
+#define mmCPU_IF_PDMA_SEI_INTR_MASK 0x4CC1548
+
+#define mmCPU_IF_HBM_SEI_INTR_STS 0x4CC1550
+
+#define mmCPU_IF_HBM_SEI_INTR_CLR 0x4CC1554
+
+#define mmCPU_IF_HBM_SEI_INTR_MASK 0x4CC1558
+
+#define mmCPU_IF_DEC_SEI_INTR_STS 0x4CC1560
+
+#define mmCPU_IF_DEC_SEI_INTR_CLR 0x4CC1564
+
+#define mmCPU_IF_DEC_SEI_INTR_MASK 0x4CC1568
+
+#define mmCPU_IF_HIF_SEI_INTR_STS 0x4CC1570
+
+#define mmCPU_IF_HIF_SEI_INTR_CLR 0x4CC1574
+
+#define mmCPU_IF_HIF_SEI_INTR_MASK 0x4CC1578
+
+#define mmCPU_IF_SYNC_MNGR_SEI_INTR_STS 0x4CC1580
+
+#define mmCPU_IF_SYNC_MNGR_SEI_INTR_CLR 0x4CC1584
+
+#define mmCPU_IF_SYNC_MNGR_SEI_INTR_MASK 0x4CC1588
+
+#define mmCPU_IF_NIC_SEI_INTR_STS 0x4CC1590
+
+#define mmCPU_IF_NIC_SEI_INTR_CLR 0x4CC1594
+
+#define mmCPU_IF_NIC_SEI_INTR_MASK 0x4CC1598
+
+#define mmCPU_IF_PCIE_SPI_INTR_STS 0x4CC1600
+
+#define mmCPU_IF_PCIE_SPI_INTR_CLR 0x4CC1604
+
+#define mmCPU_IF_PCIE_SPI_INTR_MASK 0x4CC1608
+
+#define mmCPU_IF_MME_SPI_INTR_STS_0 0x4CC1610
+
+#define mmCPU_IF_MME_SPI_INTR_STS_1 0x4CC1614
+
+#define mmCPU_IF_MME_SPI_INTR_STS_2 0x4CC1618
+
+#define mmCPU_IF_MME_SPI_INTR_STS_3 0x4CC161C
+
+#define mmCPU_IF_MME_SPI_INTR_CLR_0 0x4CC1620
+
+#define mmCPU_IF_MME_SPI_INTR_CLR_1 0x4CC1624
+
+#define mmCPU_IF_MME_SPI_INTR_CLR_2 0x4CC1628
+
+#define mmCPU_IF_MME_SPI_INTR_CLR_3 0x4CC162C
+
+#define mmCPU_IF_MME_SPI_INTR_MASK_0 0x4CC1630
+
+#define mmCPU_IF_MME_SPI_INTR_MASK_1 0x4CC1634
+
+#define mmCPU_IF_MME_SPI_INTR_MASK_2 0x4CC1638
+
+#define mmCPU_IF_MME_SPI_INTR_MASK_3 0x4CC163C
+
+#define mmCPU_IF_HMMU_SPI_INTR_STS_0 0x4CC1640
+
+#define mmCPU_IF_HMMU_SPI_INTR_STS_1 0x4CC1644
+
+#define mmCPU_IF_HMMU_SPI_INTR_STS_2 0x4CC1648
+
+#define mmCPU_IF_HMMU_SPI_INTR_STS_3 0x4CC164C
+
+#define mmCPU_IF_HMMU_SPI_INTR_STS_4 0x4CC1650
+
+#define mmCPU_IF_HMMU_SPI_INTR_STS_5 0x4CC1654
+
+#define mmCPU_IF_HMMU_SPI_INTR_STS_6 0x4CC1658
+
+#define mmCPU_IF_HMMU_SPI_INTR_STS_7 0x4CC165C
+
+#define mmCPU_IF_HMMU_SPI_INTR_STS_8 0x4CC1660
+
+#define mmCPU_IF_HMMU_SPI_INTR_STS_9 0x4CC1664
+
+#define mmCPU_IF_HMMU_SPI_INTR_STS_10 0x4CC1668
+
+#define mmCPU_IF_HMMU_SPI_INTR_STS_11 0x4CC166C
+
+#define mmCPU_IF_HMMU_SPI_INTR_STS_12 0x4CC1670
+
+#define mmCPU_IF_HMMU_SPI_INTR_STS_13 0x4CC1674
+
+#define mmCPU_IF_HMMU_SPI_INTR_STS_14 0x4CC1678
+
+#define mmCPU_IF_HMMU_SPI_INTR_STS_15 0x4CC167C
+
+#define mmCPU_IF_HMMU_SPI_INTR_CLR_0 0x4CC1680
+
+#define mmCPU_IF_HMMU_SPI_INTR_CLR_1 0x4CC1684
+
+#define mmCPU_IF_HMMU_SPI_INTR_CLR_2 0x4CC1688
+
+#define mmCPU_IF_HMMU_SPI_INTR_CLR_3 0x4CC168C
+
+#define mmCPU_IF_HMMU_SPI_INTR_CLR_4 0x4CC1690
+
+#define mmCPU_IF_HMMU_SPI_INTR_CLR_5 0x4CC1694
+
+#define mmCPU_IF_HMMU_SPI_INTR_CLR_6 0x4CC1698
+
+#define mmCPU_IF_HMMU_SPI_INTR_CLR_7 0x4CC169C
+
+#define mmCPU_IF_HMMU_SPI_INTR_CLR_8 0x4CC16A0
+
+#define mmCPU_IF_HMMU_SPI_INTR_CLR_9 0x4CC16A4
+
+#define mmCPU_IF_HMMU_SPI_INTR_CLR_10 0x4CC16A8
+
+#define mmCPU_IF_HMMU_SPI_INTR_CLR_11 0x4CC16AC
+
+#define mmCPU_IF_HMMU_SPI_INTR_CLR_12 0x4CC16B0
+
+#define mmCPU_IF_HMMU_SPI_INTR_CLR_13 0x4CC16B4
+
+#define mmCPU_IF_HMMU_SPI_INTR_CLR_14 0x4CC16B8
+
+#define mmCPU_IF_HMMU_SPI_INTR_CLR_15 0x4CC16BC
+
+#define mmCPU_IF_HMMU_SPI_INTR_MASK_0 0x4CC16C0
+
+#define mmCPU_IF_HMMU_SPI_INTR_MASK_1 0x4CC16C4
+
+#define mmCPU_IF_HMMU_SPI_INTR_MASK_2 0x4CC16C8
+
+#define mmCPU_IF_HMMU_SPI_INTR_MASK_3 0x4CC16CC
+
+#define mmCPU_IF_HMMU_SPI_INTR_MASK_4 0x4CC16D0
+
+#define mmCPU_IF_HMMU_SPI_INTR_MASK_5 0x4CC16D4
+
+#define mmCPU_IF_HMMU_SPI_INTR_MASK_6 0x4CC16D8
+
+#define mmCPU_IF_HMMU_SPI_INTR_MASK_7 0x4CC16DC
+
+#define mmCPU_IF_HMMU_SPI_INTR_MASK_8 0x4CC16E0
+
+#define mmCPU_IF_HMMU_SPI_INTR_MASK_9 0x4CC16E4
+
+#define mmCPU_IF_HMMU_SPI_INTR_MASK_10 0x4CC16E8
+
+#define mmCPU_IF_HMMU_SPI_INTR_MASK_11 0x4CC16EC
+
+#define mmCPU_IF_HMMU_SPI_INTR_MASK_12 0x4CC16F0
+
+#define mmCPU_IF_HMMU_SPI_INTR_MASK_13 0x4CC16F4
+
+#define mmCPU_IF_HMMU_SPI_INTR_MASK_14 0x4CC16F8
+
+#define mmCPU_IF_HMMU_SPI_INTR_MASK_15 0x4CC16FC
+
+#define mmCPU_IF_DEC_SPI_INTR_STS_0 0x4CC1700
+
+#define mmCPU_IF_DEC_SPI_INTR_STS_1 0x4CC1704
+
+#define mmCPU_IF_DEC_SPI_INTR_STS_2 0x4CC1708
+
+#define mmCPU_IF_DEC_SPI_INTR_STS_3 0x4CC170C
+
+#define mmCPU_IF_DEC_SPI_INTR_STS_4 0x4CC1710
+
+#define mmCPU_IF_DEC_SPI_INTR_STS_5 0x4CC1714
+
+#define mmCPU_IF_DEC_SPI_INTR_STS_6 0x4CC1718
+
+#define mmCPU_IF_DEC_SPI_INTR_STS_7 0x4CC171C
+
+#define mmCPU_IF_DEC_SPI_INTR_STS_8 0x4CC1720
+
+#define mmCPU_IF_DEC_SPI_INTR_STS_9 0x4CC1724
+
+#define mmCPU_IF_DEC_SPI_INTR_CLR_0 0x4CC1730
+
+#define mmCPU_IF_DEC_SPI_INTR_CLR_1 0x4CC1734
+
+#define mmCPU_IF_DEC_SPI_INTR_CLR_2 0x4CC1738
+
+#define mmCPU_IF_DEC_SPI_INTR_CLR_3 0x4CC173C
+
+#define mmCPU_IF_DEC_SPI_INTR_CLR_4 0x4CC1740
+
+#define mmCPU_IF_DEC_SPI_INTR_CLR_5 0x4CC1744
+
+#define mmCPU_IF_DEC_SPI_INTR_CLR_6 0x4CC1748
+
+#define mmCPU_IF_DEC_SPI_INTR_CLR_7 0x4CC174C
+
+#define mmCPU_IF_DEC_SPI_INTR_CLR_8 0x4CC1750
+
+#define mmCPU_IF_DEC_SPI_INTR_CLR_9 0x4CC1754
+
+#define mmCPU_IF_DEC_SPI_INTR_MASK_0 0x4CC1760
+
+#define mmCPU_IF_DEC_SPI_INTR_MASK_1 0x4CC1764
+
+#define mmCPU_IF_DEC_SPI_INTR_MASK_2 0x4CC1768
+
+#define mmCPU_IF_DEC_SPI_INTR_MASK_3 0x4CC176C
+
+#define mmCPU_IF_DEC_SPI_INTR_MASK_4 0x4CC1770
+
+#define mmCPU_IF_DEC_SPI_INTR_MASK_5 0x4CC1774
+
+#define mmCPU_IF_DEC_SPI_INTR_MASK_6 0x4CC1778
+
+#define mmCPU_IF_DEC_SPI_INTR_MASK_7 0x4CC177C
+
+#define mmCPU_IF_DEC_SPI_INTR_MASK_8 0x4CC1780
+
+#define mmCPU_IF_DEC_SPI_INTR_MASK_9 0x4CC1784
+
+#define mmCPU_IF_HIF_SPI_INTR_STS 0x4CC17A0
+
+#define mmCPU_IF_HIF_SPI_INTR_CLR 0x4CC17A4
+
+#define mmCPU_IF_HIF_SPI_INTR_MASK 0x4CC17A8
+
+#define mmCPU_IF_NIC_SPI_INTR_STS_0 0x4CC17B0
+
+#define mmCPU_IF_NIC_SPI_INTR_STS_1 0x4CC17B4
+
+#define mmCPU_IF_NIC_SPI_INTR_STS_2 0x4CC17B8
+
+#define mmCPU_IF_NIC_SPI_INTR_STS_3 0x4CC17BC
+
+#define mmCPU_IF_NIC_SPI_INTR_STS_4 0x4CC17C0
+
+#define mmCPU_IF_NIC_SPI_INTR_STS_5 0x4CC17C4
+
+#define mmCPU_IF_NIC_SPI_INTR_STS_6 0x4CC17C8
+
+#define mmCPU_IF_NIC_SPI_INTR_STS_7 0x4CC17CC
+
+#define mmCPU_IF_NIC_SPI_INTR_STS_8 0x4CC17D0
+
+#define mmCPU_IF_NIC_SPI_INTR_STS_9 0x4CC17D4
+
+#define mmCPU_IF_NIC_SPI_INTR_STS_10 0x4CC17D8
+
+#define mmCPU_IF_NIC_SPI_INTR_STS_11 0x4CC17DC
+
+#define mmCPU_IF_NIC_SPI_INTR_CLR_0 0x4CC17E0
+
+#define mmCPU_IF_NIC_SPI_INTR_CLR_1 0x4CC17E4
+
+#define mmCPU_IF_NIC_SPI_INTR_CLR_2 0x4CC17E8
+
+#define mmCPU_IF_NIC_SPI_INTR_CLR_3 0x4CC17EC
+
+#define mmCPU_IF_NIC_SPI_INTR_CLR_4 0x4CC17F0
+
+#define mmCPU_IF_NIC_SPI_INTR_CLR_5 0x4CC17F4
+
+#define mmCPU_IF_NIC_SPI_INTR_CLR_6 0x4CC17F8
+
+#define mmCPU_IF_NIC_SPI_INTR_CLR_7 0x4CC17FC
+
+#define mmCPU_IF_NIC_SPI_INTR_CLR_8 0x4CC1800
+
+#define mmCPU_IF_NIC_SPI_INTR_CLR_9 0x4CC1804
+
+#define mmCPU_IF_NIC_SPI_INTR_CLR_10 0x4CC1808
+
+#define mmCPU_IF_NIC_SPI_INTR_CLR_11 0x4CC180C
+
+#define mmCPU_IF_NIC_SPI_INTR_MASK_0 0x4CC1810
+
+#define mmCPU_IF_NIC_SPI_INTR_MASK_1 0x4CC1814
+
+#define mmCPU_IF_NIC_SPI_INTR_MASK_2 0x4CC1818
+
+#define mmCPU_IF_NIC_SPI_INTR_MASK_3 0x4CC181C
+
+#define mmCPU_IF_NIC_SPI_INTR_MASK_4 0x4CC1820
+
+#define mmCPU_IF_NIC_SPI_INTR_MASK_5 0x4CC1824
+
+#define mmCPU_IF_NIC_SPI_INTR_MASK_6 0x4CC1828
+
+#define mmCPU_IF_NIC_SPI_INTR_MASK_7 0x4CC182C
+
+#define mmCPU_IF_NIC_SPI_INTR_MASK_8 0x4CC1830
+
+#define mmCPU_IF_NIC_SPI_INTR_MASK_9 0x4CC1834
+
+#define mmCPU_IF_NIC_SPI_INTR_MASK_10 0x4CC1838
+
+#define mmCPU_IF_NIC_SPI_INTR_MASK_11 0x4CC183C
+
+#define mmCPU_IF_DEC_ECO_INTR_STS 0x4CC1840
+
+#define mmCPU_IF_DEC_ECO_INTR_CLR 0x4CC1844
+
+#define mmCPU_IF_DEC_ECO_INTR_MASK 0x4CC1848
+
+#define mmCPU_IF_HIF_ECO_INTR_STS 0x4CC1850
+
+#define mmCPU_IF_HIF_ECO_INTR_CLR 0x4CC1854
+
+#define mmCPU_IF_HIF_ECO_INTR_MASK 0x4CC1858
+
+#define mmCPU_IF_HMMU_ECO_INTR_STS 0x4CC1860
+
+#define mmCPU_IF_HMMU_ECO_INTR_CLR 0x4CC1864
+
+#define mmCPU_IF_HMMU_ECO_INTR_MASK 0x4CC1868
+
+#define mmCPU_IF_NIC_ECO_INTR_STS 0x4CC1870
+
+#define mmCPU_IF_NIC_ECO_INTR_CLR 0x4CC1874
+
+#define mmCPU_IF_NIC_ECO_INTR_MASK 0x4CC1878
+
+#define mmCPU_IF_MSI_X_INTR_STS_0 0x4CC1900
+
+#define mmCPU_IF_MSI_X_INTR_STS_1 0x4CC1904
+
+#define mmCPU_IF_MSI_X_INTR_STS_2 0x4CC1908
+
+#define mmCPU_IF_MSI_X_INTR_STS_3 0x4CC190C
+
+#define mmCPU_IF_MSI_X_INTR_STS_4 0x4CC1910
+
+#define mmCPU_IF_MSI_X_INTR_STS_5 0x4CC1914
+
+#define mmCPU_IF_MSI_X_INTR_STS_6 0x4CC1918
+
+#define mmCPU_IF_MSI_X_INTR_STS_7 0x4CC191C
+
+#define mmCPU_IF_MSI_X_INTR_STS_8 0x4CC1920
+
+#define mmCPU_IF_MSI_X_INTR_STS_9 0x4CC1924
+
+#define mmCPU_IF_MSI_X_INTR_STS_10 0x4CC1928
+
+#define mmCPU_IF_MSI_X_INTR_STS_11 0x4CC192C
+
+#define mmCPU_IF_MSI_X_INTR_STS_12 0x4CC1930
+
+#define mmCPU_IF_MSI_X_INTR_STS_13 0x4CC1934
+
+#define mmCPU_IF_MSI_X_INTR_STS_14 0x4CC1938
+
+#define mmCPU_IF_MSI_X_INTR_STS_15 0x4CC193C
+
+#define mmCPU_IF_MSI_X_INTR_CLR_0 0x4CC1940
+
+#define mmCPU_IF_MSI_X_INTR_CLR_1 0x4CC1944
+
+#define mmCPU_IF_MSI_X_INTR_CLR_2 0x4CC1948
+
+#define mmCPU_IF_MSI_X_INTR_CLR_3 0x4CC194C
+
+#define mmCPU_IF_MSI_X_INTR_CLR_4 0x4CC1950
+
+#define mmCPU_IF_MSI_X_INTR_CLR_5 0x4CC1954
+
+#define mmCPU_IF_MSI_X_INTR_CLR_6 0x4CC1958
+
+#define mmCPU_IF_MSI_X_INTR_CLR_7 0x4CC195C
+
+#define mmCPU_IF_MSI_X_INTR_CLR_8 0x4CC1960
+
+#define mmCPU_IF_MSI_X_INTR_CLR_9 0x4CC1964
+
+#define mmCPU_IF_MSI_X_INTR_CLR_10 0x4CC1968
+
+#define mmCPU_IF_MSI_X_INTR_CLR_11 0x4CC196C
+
+#define mmCPU_IF_MSI_X_INTR_CLR_12 0x4CC1970
+
+#define mmCPU_IF_MSI_X_INTR_CLR_13 0x4CC1974
+
+#define mmCPU_IF_MSI_X_INTR_CLR_14 0x4CC1978
+
+#define mmCPU_IF_MSI_X_INTR_CLR_15 0x4CC197C
+
+#define mmCPU_IF_MSI_X_INTR_MASK_0 0x4CC1980
+
+#define mmCPU_IF_MSI_X_INTR_MASK_1 0x4CC1984
+
+#define mmCPU_IF_MSI_X_INTR_MASK_2 0x4CC1988
+
+#define mmCPU_IF_MSI_X_INTR_MASK_3 0x4CC198C
+
+#define mmCPU_IF_MSI_X_INTR_MASK_4 0x4CC1990
+
+#define mmCPU_IF_MSI_X_INTR_MASK_5 0x4CC1994
+
+#define mmCPU_IF_MSI_X_INTR_MASK_6 0x4CC1998
+
+#define mmCPU_IF_MSI_X_INTR_MASK_7 0x4CC199C
+
+#define mmCPU_IF_MSI_X_INTR_MASK_8 0x4CC19A0
+
+#define mmCPU_IF_MSI_X_INTR_MASK_9 0x4CC19A4
+
+#define mmCPU_IF_MSI_X_INTR_MASK_10 0x4CC19A8
+
+#define mmCPU_IF_MSI_X_INTR_MASK_11 0x4CC19AC
+
+#define mmCPU_IF_MSI_X_INTR_MASK_12 0x4CC19B0
+
+#define mmCPU_IF_MSI_X_INTR_MASK_13 0x4CC19B4
+
+#define mmCPU_IF_MSI_X_INTR_MASK_14 0x4CC19B8
+
+#define mmCPU_IF_MSI_X_INTR_MASK_15 0x4CC19BC
+
+#define mmCPU_IF_MSI_X_BUSY_INTR_STS 0x4CC19C0
+
+#define mmCPU_IF_MSI_X_BUSY_INTR_CLR 0x4CC19C4
+
+#define mmCPU_IF_MSI_X_BUSY_INTR_MASK 0x4CC19C8
+
+#define mmCPU_IF_MSI_X_GEN_ADDR 0x4CC19D0
+
+#define mmCPU_IF_MSI_X_GEN_DATA 0x4CC19D4
+
+#define mmCPU_IF_MSI_X_GEN_AWPROT 0x4CC19D8
+
+#endif /* ASIC_REG_CPU_IF_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_dec0_cmd_masks.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_dec0_cmd_masks.h
new file mode 100644
index 000000000000..296ab832013f
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_dec0_cmd_masks.h
@@ -0,0 +1,229 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_DEC0_CMD_MASKS_H_
+#define ASIC_REG_DCORE0_DEC0_CMD_MASKS_H_
+
+/*
+ *****************************************
+ *   DCORE0_DEC0_CMD
+ *   (Prototype: VSI_CMD)
+ *****************************************
+ */
+
+/* DCORE0_DEC0_CMD_SWREG0 */
+#define DCORE0_DEC0_CMD_SWREG0_SW_HW_VERSION_SHIFT 0
+#define DCORE0_DEC0_CMD_SWREG0_SW_HW_VERSION_MASK 0xFFFF
+#define DCORE0_DEC0_CMD_SWREG0_SW_HW_ID_SHIFT 16
+#define DCORE0_DEC0_CMD_SWREG0_SW_HW_ID_MASK 0xFFFF0000
+
+/* DCORE0_DEC0_CMD_SWREG1 */
+#define DCORE0_DEC0_CMD_SWREG1_SW_HW_BUILDDATE_SHIFT 0
+#define DCORE0_DEC0_CMD_SWREG1_SW_HW_BUILDDATE_MASK 0xFFFFFFFF
+
+/* DCORE0_DEC0_CMD_SWREG2 */
+#define DCORE0_DEC0_CMD_SWREG2_SW_EXT_NORM_INTR_SRC_SHIFT 0
+#define DCORE0_DEC0_CMD_SWREG2_SW_EXT_NORM_INTR_SRC_MASK 0xFFFF
+#define DCORE0_DEC0_CMD_SWREG2_SW_EXT_ABN_INTR_SRC_SHIFT 16
+#define DCORE0_DEC0_CMD_SWREG2_SW_EXT_ABN_INTR_SRC_MASK 0xFFFF0000
+
+/* DCORE0_DEC0_CMD_SWREG3 */
+#define DCORE0_DEC0_CMD_SWREG3_SW_EXE_CMDBUF_COUNT_SHIFT 0
+#define DCORE0_DEC0_CMD_SWREG3_SW_EXE_CMDBUF_COUNT_MASK 0xFFFFFFFF
+
+/* DCORE0_DEC0_CMD_SWREG4 */
+#define DCORE0_DEC0_CMD_SWREG4_SW_CMD_EXE_LSB_SHIFT 0
+#define DCORE0_DEC0_CMD_SWREG4_SW_CMD_EXE_LSB_MASK 0xFFFFFFFF
+
+/* DCORE0_DEC0_CMD_SWREG5 */
+#define DCORE0_DEC0_CMD_SWREG5_SW_CMD_EXE_MSB_SHIFT 0
+#define DCORE0_DEC0_CMD_SWREG5_SW_CMD_EXE_MSB_MASK 0xFFFFFFFF
+
+/* DCORE0_DEC0_CMD_SWREG6 */
+#define DCORE0_DEC0_CMD_SWREG6_SW_AXI_TOTALARLEN_SHIFT 0
+#define DCORE0_DEC0_CMD_SWREG6_SW_AXI_TOTALARLEN_MASK 0xFFFFFFFF
+
+/* DCORE0_DEC0_CMD_SWREG7 */
+#define DCORE0_DEC0_CMD_SWREG7_SW_AXI_TOTALR_SHIFT 0
+#define DCORE0_DEC0_CMD_SWREG7_SW_AXI_TOTALR_MASK 0xFFFFFFFF
+
+/* DCORE0_DEC0_CMD_SWREG8 */
+#define DCORE0_DEC0_CMD_SWREG8_SW_AXI_TOTALAR_SHIFT 0
+#define DCORE0_DEC0_CMD_SWREG8_SW_AXI_TOTALAR_MASK 0xFFFFFFFF
+
+/* DCORE0_DEC0_CMD_SWREG9 */
+#define DCORE0_DEC0_CMD_SWREG9_SW_AXI_TOTALRLAST_SHIFT 0
+#define DCORE0_DEC0_CMD_SWREG9_SW_AXI_TOTALRLAST_MASK 0xFFFFFFFF
+
+/* DCORE0_DEC0_CMD_SWREG10 */
+#define DCORE0_DEC0_CMD_SWREG10_SW_AXI_TOTALAWLEN_SHIFT 0
+#define DCORE0_DEC0_CMD_SWREG10_SW_AXI_TOTALAWLEN_MASK 0xFFFFFFFF
+
+/* DCORE0_DEC0_CMD_SWREG11 */
+#define DCORE0_DEC0_CMD_SWREG11_SW_AXI_TOTALW_SHIFT 0
+#define DCORE0_DEC0_CMD_SWREG11_SW_AXI_TOTALW_MASK 0xFFFFFFFF
+
+/* DCORE0_DEC0_CMD_SWREG12 */
+#define DCORE0_DEC0_CMD_SWREG12_SW_AXI_TOTALAW_SHIFT 0
+#define DCORE0_DEC0_CMD_SWREG12_SW_AXI_TOTALAW_MASK 0xFFFFFFFF
+
+/* DCORE0_DEC0_CMD_SWREG13 */
+#define DCORE0_DEC0_CMD_SWREG13_SW_AXI_TOTALWLAST_SHIFT 0
+#define DCORE0_DEC0_CMD_SWREG13_SW_AXI_TOTALWLAST_MASK 0xFFFFFFFF
+
+/* DCORE0_DEC0_CMD_SWREG14 */
+#define DCORE0_DEC0_CMD_SWREG14_SW_AXI_TOTALB_SHIFT 0
+#define DCORE0_DEC0_CMD_SWREG14_SW_AXI_TOTALB_MASK 0xFFFFFFFF
+
+/* DCORE0_DEC0_CMD_SWREG15 */
+#define DCORE0_DEC0_CMD_SWREG15_SW_WORK_STATE_SHIFT 0
+#define DCORE0_DEC0_CMD_SWREG15_SW_WORK_STATE_MASK 0x7
+#define DCORE0_DEC0_CMD_SWREG15_RSV_SHIFT 3
+#define DCORE0_DEC0_CMD_SWREG15_RSV_MASK 0x3FFFF8
+#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_BREADY_SHIFT 22
+#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_BREADY_MASK 0x400000
+#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_BVALID_SHIFT 23
+#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_BVALID_MASK 0x800000
+#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_WREADY_SHIFT 24
+#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_WREADY_MASK 0x1000000
+#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_WVALID_SHIFT 25
+#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_WVALID_MASK 0x2000000
+#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_AWREADY_SHIFT 26
+#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_AWREADY_MASK 0x4000000
+#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_AWVALID_SHIFT 27
+#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_AWVALID_MASK 0x8000000
+#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_RREADY_SHIFT 28
+#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_RREADY_MASK 0x10000000
+#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_RVALID_SHIFT 29
+#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_RVALID_MASK 0x20000000
+#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_ARREADY_SHIFT 30
+#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_ARREADY_MASK 0x40000000
+#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_ARVALID_SHIFT 31
+#define DCORE0_DEC0_CMD_SWREG15_SW_AXI_ARVALID_MASK 0x80000000
+
+/* DCORE0_DEC0_CMD_SWREG16 */
+#define DCORE0_DEC0_CMD_SWREG16_SW_START_TRIGGER_SHIFT 0
+#define DCORE0_DEC0_CMD_SWREG16_SW_START_TRIGGER_MASK 0x1
+#define DCORE0_DEC0_CMD_SWREG16_SW_RESET_ALL_SHIFT 1
+#define DCORE0_DEC0_CMD_SWREG16_SW_RESET_ALL_MASK 0x2
+#define DCORE0_DEC0_CMD_SWREG16_SW_RESET_CORE_SHIFT 2
+#define DCORE0_DEC0_CMD_SWREG16_SW_RESET_CORE_MASK 0x4
+#define DCORE0_DEC0_CMD_SWREG16_SW_ABORT_MODE_SHIFT 3
+#define DCORE0_DEC0_CMD_SWREG16_SW_ABORT_MODE_MASK 0x8
+#define DCORE0_DEC0_CMD_SWREG16_SW_CORE_CLK_GATE_DISABLE_SHIFT 4
+#define DCORE0_DEC0_CMD_SWREG16_SW_CORE_CLK_GATE_DISABLE_MASK 0x10
+#define DCORE0_DEC0_CMD_SWREG16_SW_MASTER_OUT_CLK_GATE_DISABLE_SHIFT 5
+#define DCORE0_DEC0_CMD_SWREG16_SW_MASTER_OUT_CLK_GATE_DISABLE_MASK 0x20
+#define DCORE0_DEC0_CMD_SWREG16_SW_AXI_CLK_GATE_DISABLE_SHIFT 6
+#define DCORE0_DEC0_CMD_SWREG16_SW_AXI_CLK_GATE_DISABLE_MASK 0x40
+#define DCORE0_DEC0_CMD_SWREG16_RSV_SHIFT 7
+#define DCORE0_DEC0_CMD_SWREG16_RSV_MASK 0xFFFFFF80
+
+/* DCORE0_DEC0_CMD_SWREG17 */
+#define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_ENDCMD_SHIFT 0
+#define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_ENDCMD_MASK 0x1
+#define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_BUSERR_SHIFT 1
+#define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_BUSERR_MASK 0x2
+#define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_TIMEOUT_SHIFT 2
+#define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_TIMEOUT_MASK 0x4
+#define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_CMDERR_SHIFT 3
+#define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_CMDERR_MASK 0x8
+#define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_ABORT_SHIFT 4
+#define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_ABORT_MASK 0x10
+#define DCORE0_DEC0_CMD_SWREG17_RSV_1_SHIFT 5
+#define DCORE0_DEC0_CMD_SWREG17_RSV_1_MASK 0x20
+#define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_JMP_SHIFT 6
+#define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_JMP_MASK 0x40
+#define DCORE0_DEC0_CMD_SWREG17_RSV_SHIFT 7
+#define DCORE0_DEC0_CMD_SWREG17_RSV_MASK 0xFFFFFF80
+
+/* DCORE0_DEC0_CMD_SWREG18 */
+#define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_ENDCMD_EN_SHIFT 0
+#define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_ENDCMD_EN_MASK 0x1
+#define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_BUSERR_EN_SHIFT 1
+#define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_BUSERR_EN_MASK 0x2
+#define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_TIMEOUT_EN_SHIFT 2
+#define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_TIMEOUT_EN_MASK 0x4
+#define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_CMDERR_EN_SHIFT 3
+#define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_CMDERR_EN_MASK 0x8
+#define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_ABORT_EN_SHIFT 4
+#define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_ABORT_EN_MASK 0x10
+#define DCORE0_DEC0_CMD_SWREG18_RSV_1_SHIFT 5
+#define DCORE0_DEC0_CMD_SWREG18_RSV_1_MASK 0x20
+#define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_JMP_EN_SHIFT 6
+#define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_JMP_EN_MASK 0x40
+#define DCORE0_DEC0_CMD_SWREG18_RSV_SHIFT 7
+#define DCORE0_DEC0_CMD_SWREG18_RSV_MASK 0xFFFFFF80
+
+/* DCORE0_DEC0_CMD_SWREG19 */
+#define DCORE0_DEC0_CMD_SWREG19_SW_TIMEOUT_CYCLES_SHIFT 0
+#define DCORE0_DEC0_CMD_SWREG19_SW_TIMEOUT_CYCLES_MASK 0x7FFFFFFF
+#define DCORE0_DEC0_CMD_SWREG19_SW_TIMEOUT_ENABLE_SHIFT 31
+#define DCORE0_DEC0_CMD_SWREG19_SW_TIMEOUT_ENABLE_MASK 0x80000000
+
+/* DCORE0_DEC0_CMD_SWREG20 */
+#define DCORE0_DEC0_CMD_SWREG20_SW_CMDBUF_EXE_ADDR_LSB_SHIFT 0
+#define DCORE0_DEC0_CMD_SWREG20_SW_CMDBUF_EXE_ADDR_LSB_MASK 0xFFFFFFFF
+
+/* DCORE0_DEC0_CMD_SWREG21 */
+#define DCORE0_DEC0_CMD_SWREG21_SW_CMDBUF_EXE_ADDR_MSB_SHIFT 0
+#define DCORE0_DEC0_CMD_SWREG21_SW_CMDBUF_EXE_ADDR_MSB_MASK 0xFFFFFFFF
+
+/* DCORE0_DEC0_CMD_SWREG22 */
+#define DCORE0_DEC0_CMD_SWREG22_SW_CMDBUF_EXE_LENGTH_SHIFT 0
+#define DCORE0_DEC0_CMD_SWREG22_SW_CMDBUF_EXE_LENGTH_MASK 0xFFFF
+#define DCORE0_DEC0_CMD_SWREG22_RSV_SHIFT 16
+#define DCORE0_DEC0_CMD_SWREG22_RSV_MASK 0xFFFF0000
+
+/* DCORE0_DEC0_CMD_SWREG23 */
+#define DCORE0_DEC0_CMD_SWREG23_SW_AXI_ID_WR_SHIFT 0
+#define DCORE0_DEC0_CMD_SWREG23_SW_AXI_ID_WR_MASK 0xFF
+#define DCORE0_DEC0_CMD_SWREG23_SW_AXI_ID_RD_SHIFT 8
+#define DCORE0_DEC0_CMD_SWREG23_SW_AXI_ID_RD_MASK 0xFF00
+#define DCORE0_DEC0_CMD_SWREG23_SW_MAX_BURST_LEN_SHIFT 16
+#define DCORE0_DEC0_CMD_SWREG23_SW_MAX_BURST_LEN_MASK 0xFF0000
+#define DCORE0_DEC0_CMD_SWREG23_RSV_SHIFT 24
+#define DCORE0_DEC0_CMD_SWREG23_RSV_MASK 0xF000000
+#define DCORE0_DEC0_CMD_SWREG23_SW_CMD_SWAP_SHIFT 28
+#define DCORE0_DEC0_CMD_SWREG23_SW_CMD_SWAP_MASK 0xF0000000
+
+/* DCORE0_DEC0_CMD_SWREG24 */
+#define DCORE0_DEC0_CMD_SWREG24_SW_RDY_CMDBUF_COUNT_SHIFT 0
+#define DCORE0_DEC0_CMD_SWREG24_SW_RDY_CMDBUF_COUNT_MASK 0xFFFFFFFF
+
+/* DCORE0_DEC0_CMD_SWREG25 */
+#define DCORE0_DEC0_CMD_SWREG25_SW_EXT_NORM_INTR_GATE_SHIFT 0
+#define DCORE0_DEC0_CMD_SWREG25_SW_EXT_NORM_INTR_GATE_MASK 0xFFFF
+#define DCORE0_DEC0_CMD_SWREG25_SW_EXT_ABN_INTR_GATE_SHIFT 16
+#define DCORE0_DEC0_CMD_SWREG25_SW_EXT_ABN_INTR_GATE_MASK 0xFFFF0000
+
+/* DCORE0_DEC0_CMD_SWREG26 */
+#define DCORE0_DEC0_CMD_SWREG26_SW_CMDBUF_EXE_ID_SHIFT 0
+#define DCORE0_DEC0_CMD_SWREG26_SW_CMDBUF_EXE_ID_MASK 0xFFFFFFFF
+
+/* DCORE0_DEC0_CMD_SWREG64 */
+#define DCORE0_DEC0_CMD_SWREG64_SW_DUMMY0_SHIFT 0
+#define DCORE0_DEC0_CMD_SWREG64_SW_DUMMY0_MASK 0xFFFFFFFF
+
+/* DCORE0_DEC0_CMD_SWREG65 */
+#define DCORE0_DEC0_CMD_SWREG65_SW_DUMMY1_SHIFT 0
+#define DCORE0_DEC0_CMD_SWREG65_SW_DUMMY1_MASK 0xFFFFFFFF
+
+/* DCORE0_DEC0_CMD_SWREG66 */
+#define DCORE0_DEC0_CMD_SWREG66_SW_DUMMY2_SHIFT 0
+#define DCORE0_DEC0_CMD_SWREG66_SW_DUMMY2_MASK 0xFFFFFFFF
+
+/* DCORE0_DEC0_CMD_SWREG67 */
+#define DCORE0_DEC0_CMD_SWREG67_SW_DUMMY3_SHIFT 0
+#define DCORE0_DEC0_CMD_SWREG67_SW_DUMMY3_MASK 0xFFFFFFFF
+
+#endif /* ASIC_REG_DCORE0_DEC0_CMD_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_dec0_cmd_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_dec0_cmd_regs.h
new file mode 100644
index 000000000000..e26f0d77c9dc
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_dec0_cmd_regs.h
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_DEC0_CMD_REGS_H_
+#define ASIC_REG_DCORE0_DEC0_CMD_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_DEC0_CMD
+ *   (Prototype: VSI_CMD)
+ *****************************************
+ */
+
+#define mmDCORE0_DEC0_CMD_SWREG0 0x41E0000
+
+#define mmDCORE0_DEC0_CMD_SWREG1 0x41E0004
+
+#define mmDCORE0_DEC0_CMD_SWREG2 0x41E0008
+
+#define mmDCORE0_DEC0_CMD_SWREG3 0x41E000C
+
+#define mmDCORE0_DEC0_CMD_SWREG4 0x41E0010
+
+#define mmDCORE0_DEC0_CMD_SWREG5 0x41E0014
+
+#define mmDCORE0_DEC0_CMD_SWREG6 0x41E0018
+
+#define mmDCORE0_DEC0_CMD_SWREG7 0x41E001C
+
+#define mmDCORE0_DEC0_CMD_SWREG8 0x41E0020
+
+#define mmDCORE0_DEC0_CMD_SWREG9 0x41E0024
+
+#define mmDCORE0_DEC0_CMD_SWREG10 0x41E0028
+
+#define mmDCORE0_DEC0_CMD_SWREG11 0x41E002C
+
+#define mmDCORE0_DEC0_CMD_SWREG12 0x41E0030
+
+#define mmDCORE0_DEC0_CMD_SWREG13 0x41E0034
+
+#define mmDCORE0_DEC0_CMD_SWREG14 0x41E0038
+
+#define mmDCORE0_DEC0_CMD_SWREG15 0x41E003C
+
+#define mmDCORE0_DEC0_CMD_SWREG16 0x41E0040
+
+#define mmDCORE0_DEC0_CMD_SWREG17 0x41E0044
+
+#define mmDCORE0_DEC0_CMD_SWREG18 0x41E0048
+
+#define mmDCORE0_DEC0_CMD_SWREG19 0x41E004C
+
+#define mmDCORE0_DEC0_CMD_SWREG20 0x41E0050
+
+#define mmDCORE0_DEC0_CMD_SWREG21 0x41E0054
+
+#define mmDCORE0_DEC0_CMD_SWREG22 0x41E0058
+
+#define mmDCORE0_DEC0_CMD_SWREG23 0x41E005C
+
+#define mmDCORE0_DEC0_CMD_SWREG24 0x41E0060
+
+#define mmDCORE0_DEC0_CMD_SWREG25 0x41E0064
+
+#define mmDCORE0_DEC0_CMD_SWREG26 0x41E0068
+
+#define mmDCORE0_DEC0_CMD_SWREG64 0x41E0100
+
+#define mmDCORE0_DEC0_CMD_SWREG65 0x41E0104
+
+#define mmDCORE0_DEC0_CMD_SWREG66 0x41E0108
+
+#define mmDCORE0_DEC0_CMD_SWREG67 0x41E010C
+
+#endif /* ASIC_REG_DCORE0_DEC0_CMD_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_ctx_axuser_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_ctx_axuser_regs.h
new file mode 100644
index 000000000000..8de48939243b
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_ctx_axuser_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_EDMA0_CORE_CTX_AXUSER_REGS_H_
+#define ASIC_REG_DCORE0_EDMA0_CORE_CTX_AXUSER_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_EDMA0_CORE_CTX_AXUSER
+ *   (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_ASID 0x41CB800
+
+#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_MMU_BP 0x41CB804
+
+#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_STRONG_ORDER 0x41CB808
+
+#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_NO_SNOOP 0x41CB80C
+
+#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_WR_REDUCTION 0x41CB810
+
+#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_RD_ATOMIC 0x41CB814
+
+#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_QOS 0x41CB818
+
+#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_RSVD 0x41CB81C
+
+#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_EMEM_CPAGE 0x41CB820
+
+#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_CORE 0x41CB824
+
+#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_E2E_COORD 0x41CB828
+
+#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_WR_OVRD_LO 0x41CB830
+
+#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_WR_OVRD_HI 0x41CB834
+
+#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_RD_OVRD_LO 0x41CB838
+
+#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_RD_OVRD_HI 0x41CB83C
+
+#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_LB_COORD 0x41CB840
+
+#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_LB_LOCK 0x41CB844
+
+#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_LB_RSVD 0x41CB848
+
+#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_LB_OVRD 0x41CB84C
+
+#endif /* ASIC_REG_DCORE0_EDMA0_CORE_CTX_AXUSER_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_ctx_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_ctx_regs.h
new file mode 100644
index 000000000000..f73e76c8f5bd
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_ctx_regs.h
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_EDMA0_CORE_CTX_REGS_H_
+#define ASIC_REG_DCORE0_EDMA0_CORE_CTX_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_EDMA0_CORE_CTX
+ *   (Prototype: DMA_CORE_CTX)
+ *****************************************
+ */
+
+#define mmDCORE0_EDMA0_CORE_CTX_RATE_LIM_TKN 0x41CB860
+
+#define mmDCORE0_EDMA0_CORE_CTX_PWRLP 0x41CB864
+
+#define mmDCORE0_EDMA0_CORE_CTX_TE_NUMROWS 0x41CB868
+
+#define mmDCORE0_EDMA0_CORE_CTX_IDX 0x41CB86C
+
+#define mmDCORE0_EDMA0_CORE_CTX_IDX_INC 0x41CB870
+
+#define mmDCORE0_EDMA0_CORE_CTX_CTRL 0x41CB874
+
+#define mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_0 0x41CB878
+
+#define mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_1 0x41CB87C
+
+#define mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_1 0x41CB880
+
+#define mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_2 0x41CB884
+
+#define mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_2 0x41CB888
+
+#define mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_3 0x41CB88C
+
+#define mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_3 0x41CB890
+
+#define mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_4 0x41CB894
+
+#define mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_4 0x41CB898
+
+#define mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_1 0x41CB89C
+
+#define mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_1 0x41CB8A0
+
+#define mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_2 0x41CB8A4
+
+#define mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_2 0x41CB8A8
+
+#define mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_3 0x41CB8AC
+
+#define mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_3 0x41CB8B0
+
+#define mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_4 0x41CB8B4
+
+#define mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_4 0x41CB8B8
+
+#define mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_HI 0x41CB8BC
+
+#define mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_LO 0x41CB8C0
+
+#define mmDCORE0_EDMA0_CORE_CTX_WR_COMP_WDATA 0x41CB8C4
+
+#define mmDCORE0_EDMA0_CORE_CTX_SRC_OFFSET_LO 0x41CB8C8
+
+#define mmDCORE0_EDMA0_CORE_CTX_SRC_OFFSET_HI 0x41CB8CC
+
+#define mmDCORE0_EDMA0_CORE_CTX_DST_OFFSET_LO 0x41CB8D0
+
+#define mmDCORE0_EDMA0_CORE_CTX_DST_OFFSET_HI 0x41CB8D4
+
+#define mmDCORE0_EDMA0_CORE_CTX_SRC_BASE_LO 0x41CB8D8
+
+#define mmDCORE0_EDMA0_CORE_CTX_SRC_BASE_HI 0x41CB8DC
+
+#define mmDCORE0_EDMA0_CORE_CTX_DST_BASE_LO 0x41CB8E0
+
+#define mmDCORE0_EDMA0_CORE_CTX_DST_BASE_HI 0x41CB8E4
+
+#define mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_0 0x41CB8E8
+
+#define mmDCORE0_EDMA0_CORE_CTX_COMMIT 0x41CB8EC
+
+#endif /* ASIC_REG_DCORE0_EDMA0_CORE_CTX_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_masks.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_masks.h
new file mode 100644
index 000000000000..d600f6bf70d8
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_masks.h
@@ -0,0 +1,415 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_EDMA0_CORE_MASKS_H_
+#define ASIC_REG_DCORE0_EDMA0_CORE_MASKS_H_
+
+/*
+ *****************************************
+ *   DCORE0_EDMA0_CORE
+ *   (Prototype: DMA_CORE)
+ *****************************************
+ */
+
+/* DCORE0_EDMA0_CORE_CFG_0 */
+#define DCORE0_EDMA0_CORE_CFG_0_EN_SHIFT 0
+#define DCORE0_EDMA0_CORE_CFG_0_EN_MASK 0x1
+
+/* DCORE0_EDMA0_CORE_CFG_1 */
+#define DCORE0_EDMA0_CORE_CFG_1_HALT_SHIFT 0
+#define DCORE0_EDMA0_CORE_CFG_1_HALT_MASK 0x1
+#define DCORE0_EDMA0_CORE_CFG_1_FLUSH_SHIFT 1
+#define DCORE0_EDMA0_CORE_CFG_1_FLUSH_MASK 0x2
+
+/* DCORE0_EDMA0_CORE_PROT */
+#define DCORE0_EDMA0_CORE_PROT_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_PROT_VAL_MASK 0x1
+#define DCORE0_EDMA0_CORE_PROT_ERR_VAL_SHIFT 1
+#define DCORE0_EDMA0_CORE_PROT_ERR_VAL_MASK 0x2
+
+/* DCORE0_EDMA0_CORE_CKG */
+#define DCORE0_EDMA0_CORE_CKG_HBW_RBUF_SHIFT 0
+#define DCORE0_EDMA0_CORE_CKG_HBW_RBUF_MASK 0x1
+#define DCORE0_EDMA0_CORE_CKG_LBW_RBUF_KDMA_SHIFT 1
+#define DCORE0_EDMA0_CORE_CKG_LBW_RBUF_KDMA_MASK 0x2
+#define DCORE0_EDMA0_CORE_CKG_TE_SHIFT 2
+#define DCORE0_EDMA0_CORE_CKG_TE_MASK 0x4
+
+/* DCORE0_EDMA0_CORE_RD_GLBL */
+#define DCORE0_EDMA0_CORE_RD_GLBL_LBW_VIA_HBW_SHIFT 0
+#define DCORE0_EDMA0_CORE_RD_GLBL_LBW_VIA_HBW_MASK 0x1
+#define DCORE0_EDMA0_CORE_RD_GLBL_HBW_FORCE_MISS_SHIFT 4
+#define DCORE0_EDMA0_CORE_RD_GLBL_HBW_FORCE_MISS_MASK 0x10
+#define DCORE0_EDMA0_CORE_RD_GLBL_LBW_FORCE_MISS_SHIFT 5
+#define DCORE0_EDMA0_CORE_RD_GLBL_LBW_FORCE_MISS_MASK 0x20
+
+/* DCORE0_EDMA0_CORE_RD_HBW_MAX_OUTSTAND */
+#define DCORE0_EDMA0_CORE_RD_HBW_MAX_OUTSTAND_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_RD_HBW_MAX_OUTSTAND_VAL_MASK 0xFFF
+
+/* DCORE0_EDMA0_CORE_RD_HBW_MAX_SIZE */
+#define DCORE0_EDMA0_CORE_RD_HBW_MAX_SIZE_DATA_SHIFT 0
+#define DCORE0_EDMA0_CORE_RD_HBW_MAX_SIZE_DATA_MASK 0xFFF
+#define DCORE0_EDMA0_CORE_RD_HBW_MAX_SIZE_MD_SHIFT 16
+#define DCORE0_EDMA0_CORE_RD_HBW_MAX_SIZE_MD_MASK 0xFFF0000
+
+/* DCORE0_EDMA0_CORE_RD_HBW_ARCACHE */
+#define DCORE0_EDMA0_CORE_RD_HBW_ARCACHE_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_RD_HBW_ARCACHE_VAL_MASK 0xF
+
+/* DCORE0_EDMA0_CORE_RD_HBW_INFLIGHTS */
+#define DCORE0_EDMA0_CORE_RD_HBW_INFLIGHTS_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_RD_HBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG */
+#define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_TOUT_SHIFT 0
+#define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_TOUT_MASK 0xFF
+#define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_SAT_SHIFT 16
+#define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_SAT_MASK 0xFF0000
+#define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_EN_SHIFT 31
+#define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_EN_MASK 0x80000000
+
+/* DCORE0_EDMA0_CORE_RD_LBW_MAX_OUTSTAND */
+#define DCORE0_EDMA0_CORE_RD_LBW_MAX_OUTSTAND_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_RD_LBW_MAX_OUTSTAND_VAL_MASK 0xFFF
+
+/* DCORE0_EDMA0_CORE_RD_LBW_MAX_SIZE */
+#define DCORE0_EDMA0_CORE_RD_LBW_MAX_SIZE_DATA_SHIFT 0
+#define DCORE0_EDMA0_CORE_RD_LBW_MAX_SIZE_DATA_MASK 0xFFF
+#define DCORE0_EDMA0_CORE_RD_LBW_MAX_SIZE_MD_SHIFT 16
+#define DCORE0_EDMA0_CORE_RD_LBW_MAX_SIZE_MD_MASK 0xFFF0000
+
+/* DCORE0_EDMA0_CORE_RD_LBW_ARCACHE */
+#define DCORE0_EDMA0_CORE_RD_LBW_ARCACHE_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_RD_LBW_ARCACHE_VAL_MASK 0xF
+
+/* DCORE0_EDMA0_CORE_RD_LBW_INFLIGHTS */
+#define DCORE0_EDMA0_CORE_RD_LBW_INFLIGHTS_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_RD_LBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG */
+#define DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG_TOUT_SHIFT 0
+#define DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG_TOUT_MASK 0xFF
+#define DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG_SAT_SHIFT 16
+#define DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG_SAT_MASK 0xFF0000
+#define DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG_EN_SHIFT 31
+#define DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG_EN_MASK 0x80000000
+
+/* DCORE0_EDMA0_CORE_WR_HBW_MAX_OUTSTAND */
+#define DCORE0_EDMA0_CORE_WR_HBW_MAX_OUTSTAND_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_WR_HBW_MAX_OUTSTAND_VAL_MASK 0xFFFF
+
+/* DCORE0_EDMA0_CORE_WR_HBW_MAX_AWID */
+#define DCORE0_EDMA0_CORE_WR_HBW_MAX_AWID_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_WR_HBW_MAX_AWID_VAL_MASK 0x3FFF
+
+/* DCORE0_EDMA0_CORE_WR_HBW_AWCACHE */
+#define DCORE0_EDMA0_CORE_WR_HBW_AWCACHE_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_WR_HBW_AWCACHE_VAL_MASK 0xF
+
+/* DCORE0_EDMA0_CORE_WR_HBW_INFLIGHTS */
+#define DCORE0_EDMA0_CORE_WR_HBW_INFLIGHTS_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_WR_HBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG */
+#define DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG_TOUT_SHIFT 0
+#define DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG_TOUT_MASK 0xFF
+#define DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG_SAT_SHIFT 16
+#define DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG_SAT_MASK 0xFF0000
+#define DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG_EN_SHIFT 31
+#define DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG_EN_MASK 0x80000000
+
+/* DCORE0_EDMA0_CORE_WR_LBW_MAX_OUTSTAND */
+#define DCORE0_EDMA0_CORE_WR_LBW_MAX_OUTSTAND_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_WR_LBW_MAX_OUTSTAND_VAL_MASK 0xFFFF
+
+/* DCORE0_EDMA0_CORE_WR_LBW_MAX_AWID */
+#define DCORE0_EDMA0_CORE_WR_LBW_MAX_AWID_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_WR_LBW_MAX_AWID_VAL_MASK 0x7F
+
+/* DCORE0_EDMA0_CORE_WR_LBW_AWCACHE */
+#define DCORE0_EDMA0_CORE_WR_LBW_AWCACHE_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_WR_LBW_AWCACHE_VAL_MASK 0xF
+
+/* DCORE0_EDMA0_CORE_WR_LBW_INFLIGHTS */
+#define DCORE0_EDMA0_CORE_WR_LBW_INFLIGHTS_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_WR_LBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG */
+#define DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG_TOUT_SHIFT 0
+#define DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG_TOUT_MASK 0xFF
+#define DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG_SAT_SHIFT 16
+#define DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG_SAT_MASK 0xFF0000
+#define DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG_EN_SHIFT 31
+#define DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG_EN_MASK 0x80000000
+
+/* DCORE0_EDMA0_CORE_WR_COMP_MAX_OUTSTAND */
+#define DCORE0_EDMA0_CORE_WR_COMP_MAX_OUTSTAND_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_WR_COMP_MAX_OUTSTAND_VAL_MASK 0x1F
+
+/* DCORE0_EDMA0_CORE_WR_COMP_AWUSER */
+#define DCORE0_EDMA0_CORE_WR_COMP_AWUSER_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_WR_COMP_AWUSER_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_CORE_ERR_CFG */
+#define DCORE0_EDMA0_CORE_ERR_CFG_ERR_MSG_EN_SHIFT 0
+#define DCORE0_EDMA0_CORE_ERR_CFG_ERR_MSG_EN_MASK 0x1
+#define DCORE0_EDMA0_CORE_ERR_CFG_STOP_ON_ERR_SHIFT 1
+#define DCORE0_EDMA0_CORE_ERR_CFG_STOP_ON_ERR_MASK 0x2
+
+/* DCORE0_EDMA0_CORE_ERR_CAUSE */
+#define DCORE0_EDMA0_CORE_ERR_CAUSE_HBW_RD_ERR_SHIFT 0
+#define DCORE0_EDMA0_CORE_ERR_CAUSE_HBW_RD_ERR_MASK 0x1
+#define DCORE0_EDMA0_CORE_ERR_CAUSE_HBW_WR_ERR_SHIFT 1
+#define DCORE0_EDMA0_CORE_ERR_CAUSE_HBW_WR_ERR_MASK 0x2
+#define DCORE0_EDMA0_CORE_ERR_CAUSE_LBW_MSG_WR_ERR_SHIFT 2
+#define DCORE0_EDMA0_CORE_ERR_CAUSE_LBW_MSG_WR_ERR_MASK 0x4
+#define DCORE0_EDMA0_CORE_ERR_CAUSE_DESC_OVF_SHIFT 3
+#define DCORE0_EDMA0_CORE_ERR_CAUSE_DESC_OVF_MASK 0x8
+#define DCORE0_EDMA0_CORE_ERR_CAUSE_LBW_RD_ERR_SHIFT 4
+#define DCORE0_EDMA0_CORE_ERR_CAUSE_LBW_RD_ERR_MASK 0x10
+#define DCORE0_EDMA0_CORE_ERR_CAUSE_LBW_WR_ERR_SHIFT 5
+#define DCORE0_EDMA0_CORE_ERR_CAUSE_LBW_WR_ERR_MASK 0x20
+#define DCORE0_EDMA0_CORE_ERR_CAUSE_TE_DESC_FIFO_OVFL_SHIFT 6
+#define DCORE0_EDMA0_CORE_ERR_CAUSE_TE_DESC_FIFO_OVFL_MASK 0x40
+#define DCORE0_EDMA0_CORE_ERR_CAUSE_LIN_DMA_COMMIT_CFG_ERR_SHIFT 7
+#define DCORE0_EDMA0_CORE_ERR_CAUSE_LIN_DMA_COMMIT_CFG_ERR_MASK 0x80
+
+/* DCORE0_EDMA0_CORE_ERRMSG_ADDR_LO */
+#define DCORE0_EDMA0_CORE_ERRMSG_ADDR_LO_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_ERRMSG_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_CORE_ERRMSG_ADDR_HI */
+#define DCORE0_EDMA0_CORE_ERRMSG_ADDR_HI_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_ERRMSG_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_CORE_ERRMSG_WDATA */
+#define DCORE0_EDMA0_CORE_ERRMSG_WDATA_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_ERRMSG_WDATA_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_CORE_STS0 */
+#define DCORE0_EDMA0_CORE_STS0_RD_REQ_CNT_SHIFT 0
+#define DCORE0_EDMA0_CORE_STS0_RD_REQ_CNT_MASK 0x7FFF
+#define DCORE0_EDMA0_CORE_STS0_WR_REQ_CNT_SHIFT 16
+#define DCORE0_EDMA0_CORE_STS0_WR_REQ_CNT_MASK 0x7FFF0000
+#define DCORE0_EDMA0_CORE_STS0_BUSY_SHIFT 31
+#define DCORE0_EDMA0_CORE_STS0_BUSY_MASK 0x80000000
+
+/* DCORE0_EDMA0_CORE_STS1 */
+#define DCORE0_EDMA0_CORE_STS1_IS_HALT_SHIFT 0
+#define DCORE0_EDMA0_CORE_STS1_IS_HALT_MASK 0x1
+
+/* DCORE0_EDMA0_CORE_STS_RD_CTX_SEL */
+#define DCORE0_EDMA0_CORE_STS_RD_CTX_SEL_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_STS_RD_CTX_SEL_VAL_MASK 0x7
+#define DCORE0_EDMA0_CORE_STS_RD_CTX_SEL_STRIDE_SHIFT 8
+#define DCORE0_EDMA0_CORE_STS_RD_CTX_SEL_STRIDE_MASK 0x100
+
+/* DCORE0_EDMA0_CORE_STS_RD_CTX_SIZE */
+#define DCORE0_EDMA0_CORE_STS_RD_CTX_SIZE_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_STS_RD_CTX_SIZE_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_CORE_STS_RD_CTX_BASE_LO */
+#define DCORE0_EDMA0_CORE_STS_RD_CTX_BASE_LO_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_STS_RD_CTX_BASE_LO_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_CORE_STS_RD_CTX_BASE_HI */
+#define DCORE0_EDMA0_CORE_STS_RD_CTX_BASE_HI_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_STS_RD_CTX_BASE_HI_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_CORE_STS_RD_CTX_ID */
+#define DCORE0_EDMA0_CORE_STS_RD_CTX_ID_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_STS_RD_CTX_ID_VAL_MASK 0xFFFF
+
+/* DCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_LO */
+#define DCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_LO_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_HI */
+#define DCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_HI_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR */
+#define DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR_VAL_MASK 0x3FFFFFF
+#define DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR_RDY_SHIFT 30
+#define DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR_RDY_MASK 0x40000000
+#define DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR_VLD_SHIFT 31
+#define DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR_VLD_MASK 0x80000000
+
+/* DCORE0_EDMA0_CORE_STS_WR_CTX_SEL */
+#define DCORE0_EDMA0_CORE_STS_WR_CTX_SEL_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_STS_WR_CTX_SEL_VAL_MASK 0x7
+#define DCORE0_EDMA0_CORE_STS_WR_CTX_SEL_STRIDE_SHIFT 8
+#define DCORE0_EDMA0_CORE_STS_WR_CTX_SEL_STRIDE_MASK 0x100
+
+/* DCORE0_EDMA0_CORE_STS_WR_CTX_SIZE */
+#define DCORE0_EDMA0_CORE_STS_WR_CTX_SIZE_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_STS_WR_CTX_SIZE_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_CORE_STS_WR_CTX_BASE_LO */
+#define DCORE0_EDMA0_CORE_STS_WR_CTX_BASE_LO_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_STS_WR_CTX_BASE_LO_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_CORE_STS_WR_CTX_BASE_HI */
+#define DCORE0_EDMA0_CORE_STS_WR_CTX_BASE_HI_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_STS_WR_CTX_BASE_HI_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_CORE_STS_WR_CTX_ID */
+#define DCORE0_EDMA0_CORE_STS_WR_CTX_ID_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_STS_WR_CTX_ID_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO */
+#define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_VAL_MASK 0x3FFFF
+#define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_RDY_SHIFT 30
+#define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_RDY_MASK 0x40000000
+#define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_VLD_SHIFT 31
+#define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_VLD_MASK 0x80000000
+
+/* DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI */
+#define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_VAL_MASK 0x3FFFF
+#define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_RDY_SHIFT 30
+#define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_RDY_MASK 0x40000000
+#define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_VLD_SHIFT 31
+#define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_VLD_MASK 0x80000000
+
+/* DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR */
+#define DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR_VAL_MASK 0x3FFFFFF
+#define DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR_RDY_SHIFT 30
+#define DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR_RDY_MASK 0x40000000
+#define DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR_VLD_SHIFT 31
+#define DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR_VLD_MASK 0x80000000
+
+/* DCORE0_EDMA0_CORE_PWRLP_CFG */
+#define DCORE0_EDMA0_CORE_PWRLP_CFG_GLBL_EN_SHIFT 0
+#define DCORE0_EDMA0_CORE_PWRLP_CFG_GLBL_EN_MASK 0x1
+#define DCORE0_EDMA0_CORE_PWRLP_CFG_CLR_SHIFT 4
+#define DCORE0_EDMA0_CORE_PWRLP_CFG_CLR_MASK 0x10
+
+/* DCORE0_EDMA0_CORE_PWRLP_STS */
+#define DCORE0_EDMA0_CORE_PWRLP_STS_RLVL_SHIFT 0
+#define DCORE0_EDMA0_CORE_PWRLP_STS_RLVL_MASK 0x7F
+#define DCORE0_EDMA0_CORE_PWRLP_STS_WLVL_SHIFT 8
+#define DCORE0_EDMA0_CORE_PWRLP_STS_WLVL_MASK 0x7F00
+#define DCORE0_EDMA0_CORE_PWRLP_STS_RCNT_SHIFT 16
+#define DCORE0_EDMA0_CORE_PWRLP_STS_RCNT_MASK 0x7F0000
+#define DCORE0_EDMA0_CORE_PWRLP_STS_WCNT_SHIFT 23
+#define DCORE0_EDMA0_CORE_PWRLP_STS_WCNT_MASK 0x3F800000
+#define DCORE0_EDMA0_CORE_PWRLP_STS_RFULL_SHIFT 30
+#define DCORE0_EDMA0_CORE_PWRLP_STS_RFULL_MASK 0x40000000
+#define DCORE0_EDMA0_CORE_PWRLP_STS_WFULL_SHIFT 31
+#define DCORE0_EDMA0_CORE_PWRLP_STS_WFULL_MASK 0x80000000
+
+/* DCORE0_EDMA0_CORE_DBG_DESC_CNT */
+#define DCORE0_EDMA0_CORE_DBG_DESC_CNT_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_DBG_DESC_CNT_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_CORE_DBG_STS */
+#define DCORE0_EDMA0_CORE_DBG_STS_RD_CTX_FULL_SHIFT 0
+#define DCORE0_EDMA0_CORE_DBG_STS_RD_CTX_FULL_MASK 0x1
+#define DCORE0_EDMA0_CORE_DBG_STS_WR_CTX_FULL_SHIFT 1
+#define DCORE0_EDMA0_CORE_DBG_STS_WR_CTX_FULL_MASK 0x2
+#define DCORE0_EDMA0_CORE_DBG_STS_WR_COMP_FULL_SHIFT 2
+#define DCORE0_EDMA0_CORE_DBG_STS_WR_COMP_FULL_MASK 0x4
+#define DCORE0_EDMA0_CORE_DBG_STS_RD_CTX_EMPTY_SHIFT 3
+#define DCORE0_EDMA0_CORE_DBG_STS_RD_CTX_EMPTY_MASK 0x8
+#define DCORE0_EDMA0_CORE_DBG_STS_WR_CTX_EMPTY_SHIFT 4
+#define DCORE0_EDMA0_CORE_DBG_STS_WR_CTX_EMPTY_MASK 0x10
+#define DCORE0_EDMA0_CORE_DBG_STS_WR_COMP_EMPTY_SHIFT 5
+#define DCORE0_EDMA0_CORE_DBG_STS_WR_COMP_EMPTY_MASK 0x20
+#define DCORE0_EDMA0_CORE_DBG_STS_TE_EMPTY_SHIFT 6
+#define DCORE0_EDMA0_CORE_DBG_STS_TE_EMPTY_MASK 0x40
+#define DCORE0_EDMA0_CORE_DBG_STS_TE_BUSY_SHIFT 7
+#define DCORE0_EDMA0_CORE_DBG_STS_TE_BUSY_MASK 0x80
+#define DCORE0_EDMA0_CORE_DBG_STS_GSKT_EMPTY_SHIFT 8
+#define DCORE0_EDMA0_CORE_DBG_STS_GSKT_EMPTY_MASK 0x100
+#define DCORE0_EDMA0_CORE_DBG_STS_GSKT_FULL_SHIFT 9
+#define DCORE0_EDMA0_CORE_DBG_STS_GSKT_FULL_MASK 0x200
+#define DCORE0_EDMA0_CORE_DBG_STS_RD_AGU_CS_SHIFT 10
+#define DCORE0_EDMA0_CORE_DBG_STS_RD_AGU_CS_MASK 0x400
+#define DCORE0_EDMA0_CORE_DBG_STS_WR_AGU_CS_SHIFT 11
+#define DCORE0_EDMA0_CORE_DBG_STS_WR_AGU_CS_MASK 0x800
+
+/* DCORE0_EDMA0_CORE_DBG_BUF_STS */
+#define DCORE0_EDMA0_CORE_DBG_BUF_STS_HBW_FULLNESS_SHIFT 0
+#define DCORE0_EDMA0_CORE_DBG_BUF_STS_HBW_FULLNESS_MASK 0xFFF
+#define DCORE0_EDMA0_CORE_DBG_BUF_STS_LBW_FULLNESS_SHIFT 16
+#define DCORE0_EDMA0_CORE_DBG_BUF_STS_LBW_FULLNESS_MASK 0xFFF0000
+
+/* DCORE0_EDMA0_CORE_DBG_RD_DESC_ID */
+#define DCORE0_EDMA0_CORE_DBG_RD_DESC_ID_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_DBG_RD_DESC_ID_VAL_MASK 0xFFFF
+
+/* DCORE0_EDMA0_CORE_DBG_WR_DESC_ID */
+#define DCORE0_EDMA0_CORE_DBG_WR_DESC_ID_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_DBG_WR_DESC_ID_VAL_MASK 0xFFFF
+
+/* DCORE0_EDMA0_CORE_APB_DMA_LBW_BASE */
+#define DCORE0_EDMA0_CORE_APB_DMA_LBW_BASE_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_APB_DMA_LBW_BASE_VAL_MASK 0xFFFF
+
+/* DCORE0_EDMA0_CORE_APB_MSTR_IF_LBW_BASE */
+#define DCORE0_EDMA0_CORE_APB_MSTR_IF_LBW_BASE_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_APB_MSTR_IF_LBW_BASE_VAL_MASK 0xFFFF
+
+/* DCORE0_EDMA0_CORE_E2E_CRED_ASYNC_CFG */
+#define DCORE0_EDMA0_CORE_E2E_CRED_ASYNC_CFG_Y_X_FORCE_SHIFT 0
+#define DCORE0_EDMA0_CORE_E2E_CRED_ASYNC_CFG_Y_X_FORCE_MASK 0x1FF
+#define DCORE0_EDMA0_CORE_E2E_CRED_ASYNC_CFG_FORCE_EN_SHIFT 9
+#define DCORE0_EDMA0_CORE_E2E_CRED_ASYNC_CFG_FORCE_EN_MASK 0x200
+
+/* DCORE0_EDMA0_CORE_DBG_APB_ENABLER */
+#define DCORE0_EDMA0_CORE_DBG_APB_ENABLER_DIS_SHIFT 0
+#define DCORE0_EDMA0_CORE_DBG_APB_ENABLER_DIS_MASK 0x1
+
+/* DCORE0_EDMA0_CORE_L2H_CMPR_LO */
+#define DCORE0_EDMA0_CORE_L2H_CMPR_LO_VAL_SHIFT 20
+#define DCORE0_EDMA0_CORE_L2H_CMPR_LO_VAL_MASK 0xFFF00000
+
+/* DCORE0_EDMA0_CORE_L2H_CMPR_HI */
+#define DCORE0_EDMA0_CORE_L2H_CMPR_HI_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_L2H_CMPR_HI_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_CORE_L2H_MASK_LO */
+#define DCORE0_EDMA0_CORE_L2H_MASK_LO_VAL_SHIFT 20
+#define DCORE0_EDMA0_CORE_L2H_MASK_LO_VAL_MASK 0xFFF00000
+
+/* DCORE0_EDMA0_CORE_L2H_MASK_HI */
+#define DCORE0_EDMA0_CORE_L2H_MASK_HI_VAL_SHIFT 0
+#define DCORE0_EDMA0_CORE_L2H_MASK_HI_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_CORE_IDLE_IND_MASK */
+#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_DESC_SHIFT 0
+#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_DESC_MASK 0x1
+#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_COMP_SHIFT 1
+#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_COMP_MASK 0x2
+#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_INSTAGE_SHIFT 2
+#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_INSTAGE_MASK 0x4
+#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_CORE_SHIFT 3
+#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_CORE_MASK 0x8
+#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_DESC_CNT_STS_SHIFT 8
+#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_DESC_CNT_STS_MASK 0x1F00
+#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_COMP_CNT_STS_SHIFT 16
+#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_COMP_CNT_STS_MASK 0x1F0000
+#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_INSTAGE_EMPTY_SHIFT 24
+#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_INSTAGE_EMPTY_MASK 0x1000000
+#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_CORE_IDLE_STS_SHIFT 25
+#define DCORE0_EDMA0_CORE_IDLE_IND_MASK_CORE_IDLE_STS_MASK 0x2000000
+
+/* DCORE0_EDMA0_CORE_APB_ENABLER */
+#define DCORE0_EDMA0_CORE_APB_ENABLER_DIS_SHIFT 0
+#define DCORE0_EDMA0_CORE_APB_ENABLER_DIS_MASK 0x1
+
+#endif /* ASIC_REG_DCORE0_EDMA0_CORE_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_regs.h
new file mode 100644
index 000000000000..84f068e4c602
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_regs.h
@@ -0,0 +1,157 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_EDMA0_CORE_REGS_H_
+#define ASIC_REG_DCORE0_EDMA0_CORE_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_EDMA0_CORE
+ *   (Prototype: DMA_CORE)
+ *****************************************
+ */
+
+#define mmDCORE0_EDMA0_CORE_CFG_0 0x41CB000
+
+#define mmDCORE0_EDMA0_CORE_CFG_1 0x41CB004
+
+#define mmDCORE0_EDMA0_CORE_PROT 0x41CB008
+
+#define mmDCORE0_EDMA0_CORE_CKG 0x41CB00C
+
+#define mmDCORE0_EDMA0_CORE_RD_GLBL 0x41CB07C
+
+#define mmDCORE0_EDMA0_CORE_RD_HBW_MAX_OUTSTAND 0x41CB080
+
+#define mmDCORE0_EDMA0_CORE_RD_HBW_MAX_SIZE 0x41CB084
+
+#define mmDCORE0_EDMA0_CORE_RD_HBW_ARCACHE 0x41CB088
+
+#define mmDCORE0_EDMA0_CORE_RD_HBW_INFLIGHTS 0x41CB090
+
+#define mmDCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG 0x41CB094
+
+#define mmDCORE0_EDMA0_CORE_RD_LBW_MAX_OUTSTAND 0x41CB0C0
+
+#define mmDCORE0_EDMA0_CORE_RD_LBW_MAX_SIZE 0x41CB0C4
+
+#define mmDCORE0_EDMA0_CORE_RD_LBW_ARCACHE 0x41CB0C8
+
+#define mmDCORE0_EDMA0_CORE_RD_LBW_INFLIGHTS 0x41CB0D0
+
+#define mmDCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG 0x41CB0D4
+
+#define mmDCORE0_EDMA0_CORE_WR_HBW_MAX_OUTSTAND 0x41CB100
+
+#define mmDCORE0_EDMA0_CORE_WR_HBW_MAX_AWID 0x41CB104
+
+#define mmDCORE0_EDMA0_CORE_WR_HBW_AWCACHE 0x41CB108
+
+#define mmDCORE0_EDMA0_CORE_WR_HBW_INFLIGHTS 0x41CB10C
+
+#define mmDCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG 0x41CB110
+
+#define mmDCORE0_EDMA0_CORE_WR_LBW_MAX_OUTSTAND 0x41CB140
+
+#define mmDCORE0_EDMA0_CORE_WR_LBW_MAX_AWID 0x41CB144
+
+#define mmDCORE0_EDMA0_CORE_WR_LBW_AWCACHE 0x41CB148
+
+#define mmDCORE0_EDMA0_CORE_WR_LBW_INFLIGHTS 0x41CB14C
+
+#define mmDCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG 0x41CB150
+
+#define mmDCORE0_EDMA0_CORE_WR_COMP_MAX_OUTSTAND 0x41CB180
+
+#define mmDCORE0_EDMA0_CORE_WR_COMP_AWUSER 0x41CB184
+
+#define mmDCORE0_EDMA0_CORE_ERR_CFG 0x41CB300
+
+#define mmDCORE0_EDMA0_CORE_ERR_CAUSE 0x41CB304
+
+#define mmDCORE0_EDMA0_CORE_ERRMSG_ADDR_LO 0x41CB308
+
+#define mmDCORE0_EDMA0_CORE_ERRMSG_ADDR_HI 0x41CB30C
+
+#define mmDCORE0_EDMA0_CORE_ERRMSG_WDATA 0x41CB310
+
+#define mmDCORE0_EDMA0_CORE_STS0 0x41CB380
+
+#define mmDCORE0_EDMA0_CORE_STS1 0x41CB384
+
+#define mmDCORE0_EDMA0_CORE_STS_RD_CTX_SEL 0x41CB400
+
+#define mmDCORE0_EDMA0_CORE_STS_RD_CTX_SIZE 0x41CB404
+
+#define mmDCORE0_EDMA0_CORE_STS_RD_CTX_BASE_LO 0x41CB408
+
+#define mmDCORE0_EDMA0_CORE_STS_RD_CTX_BASE_HI 0x41CB40C
+
+#define mmDCORE0_EDMA0_CORE_STS_RD_CTX_ID 0x41CB410
+
+#define mmDCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_LO 0x41CB414
+
+#define mmDCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_HI 0x41CB418
+
+#define mmDCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR 0x41CB41C
+
+#define mmDCORE0_EDMA0_CORE_STS_WR_CTX_SEL 0x41CB420
+
+#define mmDCORE0_EDMA0_CORE_STS_WR_CTX_SIZE 0x41CB424
+
+#define mmDCORE0_EDMA0_CORE_STS_WR_CTX_BASE_LO 0x41CB428
+
+#define mmDCORE0_EDMA0_CORE_STS_WR_CTX_BASE_HI 0x41CB42C
+
+#define mmDCORE0_EDMA0_CORE_STS_WR_CTX_ID 0x41CB430
+
+#define mmDCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO 0x41CB434
+
+#define mmDCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI 0x41CB438
+
+#define mmDCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR 0x41CB43C
+
+#define mmDCORE0_EDMA0_CORE_PWRLP_CFG 0x41CB700
+
+#define mmDCORE0_EDMA0_CORE_PWRLP_STS 0x41CB704
+
+#define mmDCORE0_EDMA0_CORE_DBG_DESC_CNT 0x41CB710
+
+#define mmDCORE0_EDMA0_CORE_DBG_STS 0x41CB714
+
+#define mmDCORE0_EDMA0_CORE_DBG_BUF_STS 0x41CB718
+
+#define mmDCORE0_EDMA0_CORE_DBG_RD_DESC_ID 0x41CB720
+
+#define mmDCORE0_EDMA0_CORE_DBG_WR_DESC_ID 0x41CB724
+
+#define mmDCORE0_EDMA0_CORE_APB_DMA_LBW_BASE 0x41CB728
+
+#define mmDCORE0_EDMA0_CORE_APB_MSTR_IF_LBW_BASE 0x41CB72C
+
+#define mmDCORE0_EDMA0_CORE_E2E_CRED_ASYNC_CFG 0x41CB730
+
+#define mmDCORE0_EDMA0_CORE_DBG_APB_ENABLER 0x41CBE1C
+
+#define mmDCORE0_EDMA0_CORE_L2H_CMPR_LO 0x41CBE20
+
+#define mmDCORE0_EDMA0_CORE_L2H_CMPR_HI 0x41CBE24
+
+#define mmDCORE0_EDMA0_CORE_L2H_MASK_LO 0x41CBE28
+
+#define mmDCORE0_EDMA0_CORE_L2H_MASK_HI 0x41CBE2C
+
+#define mmDCORE0_EDMA0_CORE_IDLE_IND_MASK 0x41CBE30
+
+#define mmDCORE0_EDMA0_CORE_APB_ENABLER 0x41CBE34
+
+#endif /* ASIC_REG_DCORE0_EDMA0_CORE_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_arc_aux_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_arc_aux_regs.h
new file mode 100644
index 000000000000..0fc45300df81
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_arc_aux_regs.h
@@ -0,0 +1,591 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_EDMA0_QM_ARC_AUX_REGS_H_
+#define ASIC_REG_DCORE0_EDMA0_QM_ARC_AUX_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_EDMA0_QM_ARC_AUX
+ *   (Prototype: QMAN_ARC_AUX)
+ *****************************************
+ */
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_RUN_HALT_REQ 0x41C8100
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_RUN_HALT_ACK 0x41C8104
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_RST_VEC_ADDR 0x41C8108
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DBG_MODE 0x41C810C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CLUSTER_NUM 0x41C8110
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_NUM 0x41C8114
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_WAKE_UP_EVENT 0x41C8118
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_SYS_ADDR_BASE 0x41C811C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CTI_AP_STS 0x41C8120
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CTI_CFG_MUX_SEL 0x41C8124
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_RST 0x41C8128
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_RST_REQ 0x41C812C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_SRAM_LSB_ADDR 0x41C8130
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_SRAM_MSB_ADDR 0x41C8134
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_PCIE_LSB_ADDR 0x41C8138
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_PCIE_MSB_ADDR 0x41C813C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CFG_LSB_ADDR 0x41C8140
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CFG_MSB_ADDR 0x41C8144
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_HBM0_LSB_ADDR 0x41C8150
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_HBM0_MSB_ADDR 0x41C8154
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_HBM1_LSB_ADDR 0x41C8158
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_HBM1_MSB_ADDR 0x41C815C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_HBM2_LSB_ADDR 0x41C8160
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_HBM2_MSB_ADDR 0x41C8164
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_HBM3_LSB_ADDR 0x41C8168
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_HBM3_MSB_ADDR 0x41C816C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_HBM0_OFFSET 0x41C8170
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_HBM1_OFFSET 0x41C8174
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_HBM2_OFFSET 0x41C8178
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_HBM3_OFFSET 0x41C817C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_0 0x41C8180
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_1 0x41C8184
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_2 0x41C8188
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_3 0x41C818C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_4 0x41C8190
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_5 0x41C8194
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_6 0x41C8198
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_0 0x41C819C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_1 0x41C81A0
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_2 0x41C81A4
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_3 0x41C81A8
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_4 0x41C81AC
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_5 0x41C81B0
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_6 0x41C81B4
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_CBU_AWCACHE_OVR 0x41C81B8
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_LBU_AWCACHE_OVR 0x41C81BC
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CONTEXT_ID_0 0x41C81C0
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CONTEXT_ID_1 0x41C81C4
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CONTEXT_ID_2 0x41C81C8
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CONTEXT_ID_3 0x41C81CC
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CONTEXT_ID_4 0x41C81D0
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CONTEXT_ID_5 0x41C81D4
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CONTEXT_ID_6 0x41C81D8
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CONTEXT_ID_7 0x41C81DC
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CID_OFFSET_0 0x41C81E0
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CID_OFFSET_1 0x41C81E4
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CID_OFFSET_2 0x41C81E8
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CID_OFFSET_3 0x41C81EC
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CID_OFFSET_4 0x41C81F0
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CID_OFFSET_5 0x41C81F4
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CID_OFFSET_6 0x41C81F8
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CID_OFFSET_7 0x41C81FC
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_0 0x41C8200
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_1 0x41C8204
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_2 0x41C8208
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_3 0x41C820C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_4 0x41C8210
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_5 0x41C8214
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_6 0x41C8218
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_7 0x41C821C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_8 0x41C8220
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_9 0x41C8224
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_10 0x41C8228
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_11 0x41C822C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_12 0x41C8230
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_13 0x41C8234
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_14 0x41C8238
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_SW_INTR_15 0x41C823C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_IRQ_INTR_MASK_0 0x41C8280
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_IRQ_INTR_MASK_1 0x41C8284
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_SEI_INTR_STS 0x41C8290
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_SEI_INTR_CLR 0x41C8294
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_SEI_INTR_MASK 0x41C8298
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_EXCPTN_CAUSE 0x41C829C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_SEI_INTR_HALT_EN 0x41C82A0
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_SEI_INTR_HALT_MASK 0x41C82A4
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_QMAN_SEI_INTR_HALT_MASK 0x41C82A8
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REI_INTR_STS 0x41C82B0
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REI_INTR_CLR 0x41C82B4
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REI_INTR_MASK 0x41C82B8
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_ECC_ERR_ADDR 0x41C82BC
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_ECC_SYNDROME 0x41C82C0
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_I_CACHE_ECC_ERR_ADDR 0x41C82C4
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_I_CACHE_ECC_SYNDROME 0x41C82C8
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_D_CACHE_ECC_ERR_ADDR 0x41C82CC
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_D_CACHE_ECC_SYNDROME 0x41C82D0
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_LBW_TRMINATE_AWADDR_ERR 0x41C82E0
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_LBW_TRMINATE_ARADDR_ERR 0x41C82E4
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CFG_LBW_TERMINATE_BRESP 0x41C82E8
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CFG_LBW_TERMINATE_RRESP 0x41C82EC
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CFG_LBW_TERMINATE_AXLEN 0x41C82F0
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CFG_LBW_TERMINATE_AXSIZE 0x41C82F4
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_SCRATCHPAD_0 0x41C8300
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_SCRATCHPAD_1 0x41C8304
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_SCRATCHPAD_2 0x41C8308
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_SCRATCHPAD_3 0x41C830C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_SCRATCHPAD_4 0x41C8310
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_SCRATCHPAD_5 0x41C8314
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_SCRATCHPAD_6 0x41C8318
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_SCRATCHPAD_7 0x41C831C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_TOTAL_CBU_WR_CNT 0x41C8320
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_INFLIGHT_CBU_WR_CNT 0x41C8324
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_TOTAL_CBU_RD_CNT 0x41C8328
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_INFLIGHT_CBU_RD_CNT 0x41C832C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_TOTAL_LBU_WR_CNT 0x41C8330
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_INFLIGHT_LBU_WR_CNT 0x41C8334
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_TOTAL_LBU_RD_CNT 0x41C8338
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT 0x41C833C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_ARUSER_OVR 0x41C8350
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_ARUSER_OVR_EN 0x41C8354
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_AWUSER_OVR 0x41C8358
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_AWUSER_OVR_EN 0x41C835C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_ARUSER_MSB_OVR 0x41C8360
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_ARUSER_MSB_OVR_EN 0x41C8364
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_AWUSER_MSB_OVR 0x41C8368
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_AWUSER_MSB_OVR_EN 0x41C836C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_AXCACHE_OVR 0x41C8370
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_LOCK_OVR 0x41C8374
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_PROT_OVR 0x41C8378
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_MAX_OUTSTANDING 0x41C837C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN 0x41C8380
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORCE_RSP_OK 0x41C8384
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_NO_WR_INFLIGHT 0x41C838C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_SEI_INTR_ID 0x41C8390
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_LBU_ARUSER_OVR 0x41C8400
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_LBU_ARUSER_OVR_EN 0x41C8404
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_LBU_AWUSER_OVR 0x41C8408
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_LBU_AWUSER_OVR_EN 0x41C840C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_LBU_AXCACHE_OVR 0x41C8420
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_LBU_LOCK_OVR 0x41C8424
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_LBU_PROT_OVR 0x41C8428
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_LBU_MAX_OUTSTANDING 0x41C842C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN 0x41C8430
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_LBU_FORCE_RSP_OK 0x41C8434
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_LBU_NO_WR_INFLIGHT 0x41C843C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_LBU_SEI_INTR_ID 0x41C8440
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0 0x41C8500
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_1 0x41C8504
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_2 0x41C8508
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_3 0x41C850C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_4 0x41C8510
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_5 0x41C8514
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_6 0x41C8518
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_7 0x41C851C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_0 0x41C8520
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_1 0x41C8524
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_2 0x41C8528
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_3 0x41C852C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_4 0x41C8530
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_5 0x41C8534
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_6 0x41C8538
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_7 0x41C853C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_0 0x41C8540
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_1 0x41C8544
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_2 0x41C8548
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_3 0x41C854C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_4 0x41C8550
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_5 0x41C8554
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_6 0x41C8558
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_7 0x41C855C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_0 0x41C8560
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_1 0x41C8564
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_2 0x41C8568
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_3 0x41C856C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_4 0x41C8570
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_5 0x41C8574
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_6 0x41C8578
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_7 0x41C857C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_0 0x41C8580
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_1 0x41C8584
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_2 0x41C8588
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_3 0x41C858C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_4 0x41C8590
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_5 0x41C8594
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_6 0x41C8598
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_7 0x41C859C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_0 0x41C85A0
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_1 0x41C85A4
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_2 0x41C85A8
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_3 0x41C85AC
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_4 0x41C85B0
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_5 0x41C85B4
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_6 0x41C85B8
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_7 0x41C85BC
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_0 0x41C85C0
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_1 0x41C85C4
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_2 0x41C85C8
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_3 0x41C85CC
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_4 0x41C85D0
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_5 0x41C85D4
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_6 0x41C85D8
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_7 0x41C85DC
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_GENERAL_Q_VLD_ENTRY_MASK 0x41C85E0
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_NIC_Q_VLD_ENTRY_MASK 0x41C85E4
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_DROP_EN 0x41C8620
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_WARN_MSG 0x41C8624
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG 0x41C8628
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_GEN_AXI_AWPROT 0x41C8630
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_GEN_AXI_AWUSER 0x41C8634
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_GEN_AXI_AWBURST 0x41C8638
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_GEN_AXI_AWLOCK 0x41C863C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_GEN_AXI_AWCACHE 0x41C8640
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_WRR_ARB_WEIGHT 0x41C8644
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_FULL_CFG 0x41C8648
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT 0x41C864C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_QMAN_CQ_IFIFO_SHADOW_CI 0x41C8650
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_QMAN_ARC_CQ_IFIFO_SHADOW_CI 0x41C8654
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_QMAN_CQ_SHADOW_CI 0x41C8658
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI 0x41C865C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_AUX2APB_PROT 0x41C8700
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_LBW_FORK_WIN_EN 0x41C8704
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR0 0x41C8708
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK0 0x41C870C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR1 0x41C8710
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK1 0x41C8714
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR0 0x41C8718
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK0 0x41C871C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR1 0x41C8720
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK1 0x41C8724
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR0 0x41C8728
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR1 0x41C872C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_ACC_ENGS_LBW_FORK_MASK 0x41C8730
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_DUP_ENG_LBW_FORK_ADDR 0x41C8734
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_ACP_ENG_LBW_FORK_ADDR 0x41C8738
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_ACC_ENGS_VIRTUAL_ADDR 0x41C873C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_WIN_EN 0x41C8740
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_LSB 0x41C8750
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_MSB 0x41C8754
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_LSB 0x41C8758
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_MSB 0x41C875C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_LSB 0x41C8760
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_MSB 0x41C8764
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_LSB 0x41C8768
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_MSB 0x41C876C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_LSB 0x41C8770
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_MSB 0x41C8774
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_LSB 0x41C8778
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_MSB 0x41C877C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_LSB 0x41C8780
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_MSB 0x41C8784
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_LSB 0x41C8788
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_MSB 0x41C878C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_TRMINATE_ARADDR_LSB 0x41C8790
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CBU_TRMINATE_ARADDR_MSB 0x41C8794
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CFG_CBU_TERMINATE_BRESP 0x41C8798
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CFG_CBU_TERMINATE_RRESP 0x41C879C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_0 0x41C8800
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_1 0x41C8804
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_2 0x41C8808
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_3 0x41C880C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_4 0x41C8810
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_5 0x41C8814
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_6 0x41C8818
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_7 0x41C881C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_8 0x41C8820
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_9 0x41C8824
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_10 0x41C8828
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_11 0x41C882C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_12 0x41C8830
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_13 0x41C8834
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_14 0x41C8838
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_REGION_CFG_15 0x41C883C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_TRMINATE_AWADDR_ERR 0x41C8840
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_TRMINATE_ARADDR_ERR 0x41C8844
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CFG_DCCM_TERMINATE_BRESP 0x41C8848
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CFG_DCCM_TERMINATE_RRESP 0x41C884C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CFG_DCCM_TERMINATE_EN 0x41C8850
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_CFG_DCCM_SECURE_REGION 0x41C8854
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT 0x41C8900
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_CTL 0x41C8904
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR_MSK 0x41C8908
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR 0x41C890C
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_ARC_ACC_ENGS_BUSER 0x41C8910
+
+#define mmDCORE0_EDMA0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN 0x41C8920
+
+#endif /* ASIC_REG_DCORE0_EDMA0_QM_ARC_AUX_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_axuser_nonsecured_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_axuser_nonsecured_regs.h
new file mode 100644
index 000000000000..88d2a133f129
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_axuser_nonsecured_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_EDMA0_QM_AXUSER_NONSECURED_REGS_H_
+#define ASIC_REG_DCORE0_EDMA0_QM_AXUSER_NONSECURED_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_EDMA0_QM_AXUSER_NONSECURED
+ *   (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_ASID 0x41CAB80
+
+#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_MMU_BP 0x41CAB84
+
+#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_STRONG_ORDER 0x41CAB88
+
+#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_NO_SNOOP 0x41CAB8C
+
+#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_WR_REDUCTION 0x41CAB90
+
+#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_RD_ATOMIC 0x41CAB94
+
+#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_QOS 0x41CAB98
+
+#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_RSVD 0x41CAB9C
+
+#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_EMEM_CPAGE 0x41CABA0
+
+#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_CORE 0x41CABA4
+
+#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_E2E_COORD 0x41CABA8
+
+#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_WR_OVRD_LO 0x41CABB0
+
+#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_WR_OVRD_HI 0x41CABB4
+
+#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_RD_OVRD_LO 0x41CABB8
+
+#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_RD_OVRD_HI 0x41CABBC
+
+#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_LB_COORD 0x41CABC0
+
+#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_LB_LOCK 0x41CABC4
+
+#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_LB_RSVD 0x41CABC8
+
+#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_LB_OVRD 0x41CABCC
+
+#endif /* ASIC_REG_DCORE0_EDMA0_QM_AXUSER_NONSECURED_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_cgm_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_cgm_regs.h
new file mode 100644
index 000000000000..0b0a76a5b2a0
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_cgm_regs.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_EDMA0_QM_CGM_REGS_H_
+#define ASIC_REG_DCORE0_EDMA0_QM_CGM_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_EDMA0_QM_CGM
+ *   (Prototype: QMAN_CGM)
+ *****************************************
+ */
+
+#define mmDCORE0_EDMA0_QM_CGM_CFG 0x41CAD80
+
+#define mmDCORE0_EDMA0_QM_CGM_STS 0x41CAD84
+
+#define mmDCORE0_EDMA0_QM_CGM_CFG1 0x41CAD88
+
+#endif /* ASIC_REG_DCORE0_EDMA0_QM_CGM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_masks.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_masks.h
new file mode 100644
index 000000000000..102e2a65811c
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_masks.h
@@ -0,0 +1,1165 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_EDMA0_QM_MASKS_H_
+#define ASIC_REG_DCORE0_EDMA0_QM_MASKS_H_
+
+/*
+ *****************************************
+ *   DCORE0_EDMA0_QM
+ *   (Prototype: QMAN)
+ *****************************************
+ */
+
+/* DCORE0_EDMA0_QM_GLBL_CFG0 */
+#define DCORE0_EDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
+#define DCORE0_EDMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
+#define DCORE0_EDMA0_QM_GLBL_CFG0_CQF_EN_SHIFT 4
+#define DCORE0_EDMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
+#define DCORE0_EDMA0_QM_GLBL_CFG0_CP_EN_SHIFT 9
+#define DCORE0_EDMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
+#define DCORE0_EDMA0_QM_GLBL_CFG0_ARC_CQF_EN_SHIFT 14
+#define DCORE0_EDMA0_QM_GLBL_CFG0_ARC_CQF_EN_MASK 0x4000
+
+/* DCORE0_EDMA0_QM_GLBL_CFG1 */
+#define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
+#define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
+#define DCORE0_EDMA0_QM_GLBL_CFG1_CQF_STOP_SHIFT 4
+#define DCORE0_EDMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
+#define DCORE0_EDMA0_QM_GLBL_CFG1_CP_STOP_SHIFT 9
+#define DCORE0_EDMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
+#define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_FLUSH_SHIFT 16
+#define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
+#define DCORE0_EDMA0_QM_GLBL_CFG1_CQF_FLUSH_SHIFT 20
+#define DCORE0_EDMA0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
+#define DCORE0_EDMA0_QM_GLBL_CFG1_CP_FLUSH_SHIFT 25
+#define DCORE0_EDMA0_QM_GLBL_CFG1_CP_FLUSH_MASK 0x3E000000
+
+/* DCORE0_EDMA0_QM_GLBL_CFG2 */
+#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_CQF_STOP_SHIFT 0
+#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_CQF_STOP_MASK 0x1
+#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_CQF_FLUSH_SHIFT 1
+#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_CQF_FLUSH_MASK 0x2
+#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_AWUSER_OVRD_SHIFT 4
+#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_AWUSER_OVRD_MASK 0x10
+#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_ARUSER_OVRD_SHIFT 5
+#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_ARUSER_OVRD_MASK 0x20
+#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_AWUSER_OVRD_SHIFT 6
+#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_AWUSER_OVRD_MASK 0x40
+#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_ARUSER_OVRD_SHIFT 7
+#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_ARUSER_OVRD_MASK 0x80
+#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_AWPROT_OVRD_SHIFT 8
+#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_AWPROT_OVRD_MASK 0x100
+#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_ARPROT_OVRD_SHIFT 9
+#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_ARPROT_OVRD_MASK 0x200
+#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_AWPROT_OVRD_SHIFT 10
+#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_AWPROT_OVRD_MASK 0x400
+#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_ARPROT_OVRD_SHIFT 11
+#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_ARPROT_OVRD_MASK 0x800
+#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_AWCACHE_OVRD_SHIFT 12
+#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_AWCACHE_OVRD_MASK 0x1000
+#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_ARCACHE_OVRD_SHIFT 13
+#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_ARCACHE_OVRD_MASK 0x2000
+#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_AWCACHE_OVRD_SHIFT 14
+#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_AWCACHE_OVRD_MASK 0x4000
+#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_ARCACHE_OVRD_SHIFT 15
+#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_ARCACHE_OVRD_MASK 0x8000
+#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_BUSER_OVRD_SHIFT 16
+#define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_BUSER_OVRD_MASK 0x10000
+
+/* DCORE0_EDMA0_QM_GLBL_ERR_CFG */
+#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 0
+#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0xF
+#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4
+#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x1F0
+#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 9
+#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x3E00
+#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 16
+#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0xF0000
+#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 20
+#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x1F00000
+#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 25
+#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x3E000000
+#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT 31
+#define DCORE0_EDMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK 0x80000000
+
+/* DCORE0_EDMA0_QM_GLBL_ERR_CFG1 */
+#define DCORE0_EDMA0_QM_GLBL_ERR_CFG1_CQF_ERR_MSG_EN_SHIFT 0
+#define DCORE0_EDMA0_QM_GLBL_ERR_CFG1_CQF_ERR_MSG_EN_MASK 0x1
+#define DCORE0_EDMA0_QM_GLBL_ERR_CFG1_CQF_STOP_ON_ERR_SHIFT 1
+#define DCORE0_EDMA0_QM_GLBL_ERR_CFG1_CQF_STOP_ON_ERR_MASK 0x2
+#define DCORE0_EDMA0_QM_GLBL_ERR_CFG1_ARC_STOP_ON_ERR_SHIFT 2
+#define DCORE0_EDMA0_QM_GLBL_ERR_CFG1_ARC_STOP_ON_ERR_MASK 0x4
+
+/* DCORE0_EDMA0_QM_GLBL_ERR_ARC_HALT_EN */
+#define DCORE0_EDMA0_QM_GLBL_ERR_ARC_HALT_EN_ERR_IND_SHIFT 0
+#define DCORE0_EDMA0_QM_GLBL_ERR_ARC_HALT_EN_ERR_IND_MASK 0xFFFFFF
+
+/* DCORE0_EDMA0_QM_GLBL_AXCACHE */
+#define DCORE0_EDMA0_QM_GLBL_AXCACHE_HBW_AR_SHIFT 0
+#define DCORE0_EDMA0_QM_GLBL_AXCACHE_HBW_AR_MASK 0xF
+#define DCORE0_EDMA0_QM_GLBL_AXCACHE_HBW_AW_SHIFT 16
+#define DCORE0_EDMA0_QM_GLBL_AXCACHE_HBW_AW_MASK 0xF0000
+#define DCORE0_EDMA0_QM_GLBL_AXCACHE_LBW_AW_SHIFT 20
+#define DCORE0_EDMA0_QM_GLBL_AXCACHE_LBW_AW_MASK 0xF00000
+#define DCORE0_EDMA0_QM_GLBL_AXCACHE_LBW_AR_SHIFT 24
+#define DCORE0_EDMA0_QM_GLBL_AXCACHE_LBW_AR_MASK 0xF000000
+
+/* DCORE0_EDMA0_QM_GLBL_STS0 */
+#define DCORE0_EDMA0_QM_GLBL_STS0_PQF_IDLE_SHIFT 0
+#define DCORE0_EDMA0_QM_GLBL_STS0_PQF_IDLE_MASK 0xF
+#define DCORE0_EDMA0_QM_GLBL_STS0_CQF_IDLE_SHIFT 4
+#define DCORE0_EDMA0_QM_GLBL_STS0_CQF_IDLE_MASK 0x1F0
+#define DCORE0_EDMA0_QM_GLBL_STS0_CP_IDLE_SHIFT 9
+#define DCORE0_EDMA0_QM_GLBL_STS0_CP_IDLE_MASK 0x3E00
+#define DCORE0_EDMA0_QM_GLBL_STS0_PQF_IS_STOP_SHIFT 16
+#define DCORE0_EDMA0_QM_GLBL_STS0_PQF_IS_STOP_MASK 0xF0000
+#define DCORE0_EDMA0_QM_GLBL_STS0_CQF_IS_STOP_SHIFT 20
+#define DCORE0_EDMA0_QM_GLBL_STS0_CQF_IS_STOP_MASK 0x1F00000
+#define DCORE0_EDMA0_QM_GLBL_STS0_CP_IS_STOP_SHIFT 25
+#define DCORE0_EDMA0_QM_GLBL_STS0_CP_IS_STOP_MASK 0x3E000000
+#define DCORE0_EDMA0_QM_GLBL_STS0_ARB_IS_STOP_SHIFT 31
+#define DCORE0_EDMA0_QM_GLBL_STS0_ARB_IS_STOP_MASK 0x80000000
+
+/* DCORE0_EDMA0_QM_GLBL_STS1 */
+#define DCORE0_EDMA0_QM_GLBL_STS1_ARC_CQF_IDLE_SHIFT 0
+#define DCORE0_EDMA0_QM_GLBL_STS1_ARC_CQF_IDLE_MASK 0x1
+#define DCORE0_EDMA0_QM_GLBL_STS1_ARC_CQF_IS_STOP_SHIFT 1
+#define DCORE0_EDMA0_QM_GLBL_STS1_ARC_CQF_IS_STOP_MASK 0x2
+
+/* DCORE0_EDMA0_QM_GLBL_ERR_STS */
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_PQF_RD_ERR_SHIFT 0
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_PQF_RD_ERR_MASK 0x1
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CQF_RD_ERR_SHIFT 1
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CQF_RD_ERR_MASK 0x2
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_RD_ERR_SHIFT 2
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_RD_ERR_MASK 0x4
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_UNDEF_CMD_ERR_SHIFT 3
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_UNDEF_CMD_ERR_MASK 0x8
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_STOP_OP_SHIFT 4
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_STOP_OP_MASK 0x10
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_MSG_WR_ERR_SHIFT 5
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_MSG_WR_ERR_MASK 0x20
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_WREG_ERR_SHIFT 6
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_WREG_ERR_MASK 0x40
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE0_OVF_ERR_SHIFT 8
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE0_OVF_ERR_MASK 0x100
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE1_OVF_ERR_SHIFT 9
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE1_OVF_ERR_MASK 0x200
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE2_OVF_ERR_SHIFT 10
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE2_OVF_ERR_MASK 0x400
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE3_OVF_ERR_SHIFT 11
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE3_OVF_ERR_MASK 0x800
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE0_UDF_ERR_SHIFT 12
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE0_UDF_ERR_MASK 0x1000
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE1_UDF_ERR_SHIFT 13
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE1_UDF_ERR_MASK 0x2000
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE2_UDF_ERR_SHIFT 14
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE2_UDF_ERR_MASK 0x4000
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE3_UDF_ERR_SHIFT 15
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE3_UDF_ERR_MASK 0x8000
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CPDMA_UP_OVF_ERR_SHIFT 16
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_CPDMA_UP_OVF_ERR_MASK 0x10000
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_PQC_L2H_ERR_SHIFT 17
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_PQC_L2H_ERR_MASK 0x20000
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_RSVD_18_24_SHIFT 18
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_RSVD_18_24_MASK 0x1FC0000
+
+/* DCORE0_EDMA0_QM_GLBL_ERR_STS_4 */
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_RSVD0_SHIFT 0
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_RSVD0_MASK 0x1
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CQF_RD_ERR_SHIFT 1
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CQF_RD_ERR_MASK 0x2
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_RD_ERR_SHIFT 2
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_RD_ERR_MASK 0x4
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_UNDEF_CMD_ERR_SHIFT 3
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_UNDEF_CMD_ERR_MASK 0x8
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_STOP_OP_SHIFT 4
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_STOP_OP_MASK 0x10
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_MSG_WR_ERR_SHIFT 5
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_MSG_WR_ERR_MASK 0x20
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_WREG_ERR_SHIFT 6
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_WREG_ERR_MASK 0x40
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_OVF_ERR_SHIFT 8
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_OVF_ERR_MASK 0x100
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_OVF_ERR_SHIFT 9
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_OVF_ERR_MASK 0x200
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_OVF_ERR_SHIFT 10
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_OVF_ERR_MASK 0x400
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_OVF_ERR_SHIFT 11
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_OVF_ERR_MASK 0x800
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_UDF_ERR_SHIFT 12
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_UDF_ERR_MASK 0x1000
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_UDF_ERR_SHIFT 13
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_UDF_ERR_MASK 0x2000
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_UDF_ERR_SHIFT 14
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_UDF_ERR_MASK 0x4000
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_UDF_ERR_SHIFT 15
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_UDF_ERR_MASK 0x8000
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CPDMA_UP_OVF_ERR_SHIFT 16
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CPDMA_UP_OVF_ERR_MASK 0x10000
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_RSVD17_SHIFT 17
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_RSVD17_MASK 0x20000
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CQ_WR_IFIFO_CI_ERR_SHIFT 18
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CQ_WR_IFIFO_CI_ERR_MASK 0x40000
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CQ_WR_CTL_CI_ERR_SHIFT 19
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CQ_WR_CTL_CI_ERR_MASK 0x80000
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_CQF_RD_ERR_SHIFT 20
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_CQF_RD_ERR_MASK 0x100000
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_IFIFO_CI_ERR_SHIFT 21
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_IFIFO_CI_ERR_MASK 0x200000
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_CTL_CI_ERR_SHIFT 22
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_CTL_CI_ERR_MASK 0x400000
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_AXI_ERR_SHIFT 23
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_AXI_ERR_MASK 0x800000
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_SWITCH_WDT_ERR_SHIFT 24
+#define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_SWITCH_WDT_ERR_MASK 0x1000000
+
+/* DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN */
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_PQF_RD_ERR_SHIFT 0
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_PQF_RD_ERR_MASK 0x1
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CQF_RD_ERR_SHIFT 1
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CQF_RD_ERR_MASK 0x2
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_RD_ERR_SHIFT 2
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_RD_ERR_MASK 0x4
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_UNDEF_CMD_ERR_SHIFT 3
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_UNDEF_CMD_ERR_MASK 0x8
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_STOP_OP_SHIFT 4
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_STOP_OP_MASK 0x10
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_MSG_WR_ERR_SHIFT 5
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_MSG_WR_ERR_MASK 0x20
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_WREG_ERR_SHIFT 6
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_WREG_ERR_MASK 0x40
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_OVF_ERR_SHIFT 8
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_OVF_ERR_MASK 0x100
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_OVF_ERR_SHIFT 9
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_OVF_ERR_MASK 0x200
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_OVF_ERR_SHIFT 10
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_OVF_ERR_MASK 0x400
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_OVF_ERR_SHIFT 11
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_OVF_ERR_MASK 0x800
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_UDF_ERR_SHIFT 12
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_UDF_ERR_MASK 0x1000
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_UDF_ERR_SHIFT 13
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_UDF_ERR_MASK 0x2000
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_UDF_ERR_SHIFT 14
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_UDF_ERR_MASK 0x4000
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_UDF_ERR_SHIFT 15
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_UDF_ERR_MASK 0x8000
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CPDMA_UP_OVF_ERR_SHIFT 16
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CPDMA_UP_OVF_ERR_MASK 0x10000
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_PQC_L2H_ERR_SHIFT 17
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_PQC_L2H_ERR_MASK 0x20000
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_RSVD_18_24_SHIFT 18
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_RSVD_18_24_MASK 0x1FC0000
+
+/* DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4 */
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD0_SHIFT 0
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD0_MASK 0x1
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CQF_RD_ERR_SHIFT 1
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CQF_RD_ERR_MASK 0x2
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_RD_ERR_SHIFT 2
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_RD_ERR_MASK 0x4
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_UNDEF_CMD_ERR_SHIFT 3
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_UNDEF_CMD_ERR_MASK 0x8
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_STOP_OP_SHIFT 4
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_STOP_OP_MASK 0x10
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_MSG_WR_ERR_SHIFT 5
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_MSG_WR_ERR_MASK 0x20
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_WREG_ERR_SHIFT 6
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_WREG_ERR_MASK 0x40
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_OVF_ERR_SHIFT 8
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_OVF_ERR_MASK 0x100
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_OVF_ERR_SHIFT 9
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_OVF_ERR_MASK 0x200
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_OVF_ERR_SHIFT 10
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_OVF_ERR_MASK 0x400
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_OVF_ERR_SHIFT 11
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_OVF_ERR_MASK 0x800
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_UDF_ERR_SHIFT 12
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_UDF_ERR_MASK 0x1000
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_UDF_ERR_SHIFT 13
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_UDF_ERR_MASK 0x2000
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_UDF_ERR_SHIFT 14
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_UDF_ERR_MASK 0x4000
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_UDF_ERR_SHIFT 15
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_UDF_ERR_MASK 0x8000
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CPDMA_UP_OVF_ERR_SHIFT 16
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CPDMA_UP_OVF_ERR_MASK 0x10000
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD17_SHIFT 17
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD17_MASK 0x20000
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_IFIFO_CI_ERR_SHIFT 18
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_IFIFO_CI_ERR_MASK 0x40000
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_CTL_CI_ERR_SHIFT 19
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_CTL_CI_ERR_MASK 0x80000
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQF_RD_ERR_SHIFT 20
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQF_RD_ERR_MASK 0x100000
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_IFIFO_CI_ERR_SHIFT 21
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_IFIFO_CI_ERR_MASK 0x200000
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_CTL_CI_ERR_SHIFT 22
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_CTL_CI_ERR_MASK 0x400000
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_AXI_ERR_SHIFT 23
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_AXI_ERR_MASK 0x800000
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_SWITCH_WDT_ERR_SHIFT 24
+#define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_SWITCH_WDT_ERR_MASK 0x1000000
+
+/* DCORE0_EDMA0_QM_GLBL_PROT */
+#define DCORE0_EDMA0_QM_GLBL_PROT_PQF_SHIFT 0
+#define DCORE0_EDMA0_QM_GLBL_PROT_PQF_MASK 0xF
+#define DCORE0_EDMA0_QM_GLBL_PROT_CQF_SHIFT 4
+#define DCORE0_EDMA0_QM_GLBL_PROT_CQF_MASK 0x1F0
+#define DCORE0_EDMA0_QM_GLBL_PROT_CP_SHIFT 9
+#define DCORE0_EDMA0_QM_GLBL_PROT_CP_MASK 0x3E00
+#define DCORE0_EDMA0_QM_GLBL_PROT_ERR_SHIFT 14
+#define DCORE0_EDMA0_QM_GLBL_PROT_ERR_MASK 0x4000
+#define DCORE0_EDMA0_QM_GLBL_PROT_ARB_SHIFT 15
+#define DCORE0_EDMA0_QM_GLBL_PROT_ARB_MASK 0x8000
+#define DCORE0_EDMA0_QM_GLBL_PROT_PQC_SHIFT 16
+#define DCORE0_EDMA0_QM_GLBL_PROT_PQC_MASK 0x10000
+#define DCORE0_EDMA0_QM_GLBL_PROT_CQ_IFIFO_MSG_SHIFT 17
+#define DCORE0_EDMA0_QM_GLBL_PROT_CQ_IFIFO_MSG_MASK 0x20000
+#define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CQ_IFIFO_MSG_SHIFT 18
+#define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CQ_IFIFO_MSG_MASK 0x40000
+#define DCORE0_EDMA0_QM_GLBL_PROT_CQ_CTL_MSG_SHIFT 19
+#define DCORE0_EDMA0_QM_GLBL_PROT_CQ_CTL_MSG_MASK 0x80000
+#define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CQ_CTL_MSG_SHIFT 20
+#define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CQ_CTL_MSG_MASK 0x100000
+#define DCORE0_EDMA0_QM_GLBL_PROT_CP_WR_ARC_SHIFT 21
+#define DCORE0_EDMA0_QM_GLBL_PROT_CP_WR_ARC_MASK 0x200000
+#define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CQF_SHIFT 22
+#define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CQF_MASK 0x400000
+#define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CORE_SHIFT 23
+#define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CORE_MASK 0x800000
+
+/* DCORE0_EDMA0_QM_PQ_BASE_LO */
+#define DCORE0_EDMA0_QM_PQ_BASE_LO_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_PQ_BASE_LO_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_PQ_BASE_HI */
+#define DCORE0_EDMA0_QM_PQ_BASE_HI_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_PQ_BASE_HI_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_PQ_SIZE */
+#define DCORE0_EDMA0_QM_PQ_SIZE_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_PQ_SIZE_VAL_MASK 0x1F
+
+/* DCORE0_EDMA0_QM_PQ_PI */
+#define DCORE0_EDMA0_QM_PQ_PI_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_PQ_PI_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_PQ_CI */
+#define DCORE0_EDMA0_QM_PQ_CI_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_PQ_CI_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_PQ_CFG0 */
+#define DCORE0_EDMA0_QM_PQ_CFG0_FORCE_STALL_SHIFT 0
+#define DCORE0_EDMA0_QM_PQ_CFG0_FORCE_STALL_MASK 0x1
+
+/* DCORE0_EDMA0_QM_PQ_CFG1 */
+#define DCORE0_EDMA0_QM_PQ_CFG1_CREDIT_LIM_SHIFT 0
+#define DCORE0_EDMA0_QM_PQ_CFG1_CREDIT_LIM_MASK 0xFF
+#define DCORE0_EDMA0_QM_PQ_CFG1_MAX_INFLIGHT_SHIFT 16
+#define DCORE0_EDMA0_QM_PQ_CFG1_MAX_INFLIGHT_MASK 0xFF0000
+
+/* DCORE0_EDMA0_QM_PQ_STS0 */
+#define DCORE0_EDMA0_QM_PQ_STS0_CREDIT_CNT_SHIFT 0
+#define DCORE0_EDMA0_QM_PQ_STS0_CREDIT_CNT_MASK 0xFF
+#define DCORE0_EDMA0_QM_PQ_STS0_FREE_CNT_SHIFT 8
+#define DCORE0_EDMA0_QM_PQ_STS0_FREE_CNT_MASK 0xFF00
+#define DCORE0_EDMA0_QM_PQ_STS0_INFLIGHT_CNT_SHIFT 16
+#define DCORE0_EDMA0_QM_PQ_STS0_INFLIGHT_CNT_MASK 0xFF0000
+
+/* DCORE0_EDMA0_QM_PQ_STS1 */
+#define DCORE0_EDMA0_QM_PQ_STS1_BUF_EMPTY_SHIFT 0
+#define DCORE0_EDMA0_QM_PQ_STS1_BUF_EMPTY_MASK 0x1
+#define DCORE0_EDMA0_QM_PQ_STS1_BUSY_SHIFT 1
+#define DCORE0_EDMA0_QM_PQ_STS1_BUSY_MASK 0x2
+
+/* DCORE0_EDMA0_QM_CQ_CFG0 */
+#define DCORE0_EDMA0_QM_CQ_CFG0_IF_B2B_EN_SHIFT 0
+#define DCORE0_EDMA0_QM_CQ_CFG0_IF_B2B_EN_MASK 0x1
+#define DCORE0_EDMA0_QM_CQ_CFG0_IF_MSG_EN_SHIFT 1
+#define DCORE0_EDMA0_QM_CQ_CFG0_IF_MSG_EN_MASK 0x2
+#define DCORE0_EDMA0_QM_CQ_CFG0_CTL_MSG_EN_SHIFT 2
+#define DCORE0_EDMA0_QM_CQ_CFG0_CTL_MSG_EN_MASK 0x4
+
+/* DCORE0_EDMA0_QM_CQ_STS0 */
+#define DCORE0_EDMA0_QM_CQ_STS0_CREDIT_CNT_SHIFT 0
+#define DCORE0_EDMA0_QM_CQ_STS0_CREDIT_CNT_MASK 0xFF
+#define DCORE0_EDMA0_QM_CQ_STS0_FREE_CNT_SHIFT 8
+#define DCORE0_EDMA0_QM_CQ_STS0_FREE_CNT_MASK 0xFF00
+#define DCORE0_EDMA0_QM_CQ_STS0_INFLIGHT_CNT_SHIFT 16
+#define DCORE0_EDMA0_QM_CQ_STS0_INFLIGHT_CNT_MASK 0xFF0000
+
+/* DCORE0_EDMA0_QM_CQ_CFG1 */
+#define DCORE0_EDMA0_QM_CQ_CFG1_CREDIT_LIM_SHIFT 0
+#define DCORE0_EDMA0_QM_CQ_CFG1_CREDIT_LIM_MASK 0xFF
+#define DCORE0_EDMA0_QM_CQ_CFG1_MAX_INFLIGHT_SHIFT 16
+#define DCORE0_EDMA0_QM_CQ_CFG1_MAX_INFLIGHT_MASK 0xFF0000
+
+/* DCORE0_EDMA0_QM_CQ_STS1 */
+#define DCORE0_EDMA0_QM_CQ_STS1_BUF_EMPTY_SHIFT 0
+#define DCORE0_EDMA0_QM_CQ_STS1_BUF_EMPTY_MASK 0x1
+#define DCORE0_EDMA0_QM_CQ_STS1_BUSY_SHIFT 1
+#define DCORE0_EDMA0_QM_CQ_STS1_BUSY_MASK 0x2
+
+/* DCORE0_EDMA0_QM_CQ_PTR_LO_0 */
+#define DCORE0_EDMA0_QM_CQ_PTR_LO_0_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CQ_PTR_LO_0_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_CQ_PTR_HI_0 */
+#define DCORE0_EDMA0_QM_CQ_PTR_HI_0_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CQ_PTR_HI_0_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_CQ_TSIZE_0 */
+#define DCORE0_EDMA0_QM_CQ_TSIZE_0_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CQ_TSIZE_0_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_CQ_CTL_0 */
+#define DCORE0_EDMA0_QM_CQ_CTL_0_UP_SHIFT 28
+#define DCORE0_EDMA0_QM_CQ_CTL_0_UP_MASK 0xF0000000
+
+/* DCORE0_EDMA0_QM_CQ_PTR_LO_1 */
+#define DCORE0_EDMA0_QM_CQ_PTR_LO_1_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CQ_PTR_LO_1_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_CQ_PTR_HI_1 */
+#define DCORE0_EDMA0_QM_CQ_PTR_HI_1_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CQ_PTR_HI_1_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_CQ_TSIZE_1 */
+#define DCORE0_EDMA0_QM_CQ_TSIZE_1_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CQ_TSIZE_1_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_CQ_CTL_1 */
+#define DCORE0_EDMA0_QM_CQ_CTL_1_UP_SHIFT 28
+#define DCORE0_EDMA0_QM_CQ_CTL_1_UP_MASK 0xF0000000
+
+/* DCORE0_EDMA0_QM_CQ_PTR_LO_2 */
+#define DCORE0_EDMA0_QM_CQ_PTR_LO_2_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CQ_PTR_LO_2_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_CQ_PTR_HI_2 */
+#define DCORE0_EDMA0_QM_CQ_PTR_HI_2_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CQ_PTR_HI_2_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_CQ_TSIZE_2 */
+#define DCORE0_EDMA0_QM_CQ_TSIZE_2_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CQ_TSIZE_2_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_CQ_CTL_2 */
+#define DCORE0_EDMA0_QM_CQ_CTL_2_UP_SHIFT 28
+#define DCORE0_EDMA0_QM_CQ_CTL_2_UP_MASK 0xF0000000
+
+/* DCORE0_EDMA0_QM_CQ_PTR_LO_3 */
+#define DCORE0_EDMA0_QM_CQ_PTR_LO_3_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CQ_PTR_LO_3_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_CQ_PTR_HI_3 */
+#define DCORE0_EDMA0_QM_CQ_PTR_HI_3_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CQ_PTR_HI_3_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_CQ_TSIZE_3 */
+#define DCORE0_EDMA0_QM_CQ_TSIZE_3_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CQ_TSIZE_3_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_CQ_CTL_3 */
+#define DCORE0_EDMA0_QM_CQ_CTL_3_UP_SHIFT 28
+#define DCORE0_EDMA0_QM_CQ_CTL_3_UP_MASK 0xF0000000
+
+/* DCORE0_EDMA0_QM_CQ_PTR_LO_4 */
+#define DCORE0_EDMA0_QM_CQ_PTR_LO_4_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CQ_PTR_LO_4_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_CQ_PTR_HI_4 */
+#define DCORE0_EDMA0_QM_CQ_PTR_HI_4_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CQ_PTR_HI_4_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_CQ_TSIZE_4 */
+#define DCORE0_EDMA0_QM_CQ_TSIZE_4_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CQ_TSIZE_4_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_CQ_CTL_4 */
+#define DCORE0_EDMA0_QM_CQ_CTL_4_UP_SHIFT 28
+#define DCORE0_EDMA0_QM_CQ_CTL_4_UP_MASK 0xF0000000
+
+/* DCORE0_EDMA0_QM_CQ_TSIZE_STS */
+#define DCORE0_EDMA0_QM_CQ_TSIZE_STS_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_CQ_PTR_LO_STS */
+#define DCORE0_EDMA0_QM_CQ_PTR_LO_STS_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_CQ_PTR_HI_STS */
+#define DCORE0_EDMA0_QM_CQ_PTR_HI_STS_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_CQ_IFIFO_STS */
+#define DCORE0_EDMA0_QM_CQ_IFIFO_STS_CNT_SHIFT 0
+#define DCORE0_EDMA0_QM_CQ_IFIFO_STS_CNT_MASK 0x7
+#define DCORE0_EDMA0_QM_CQ_IFIFO_STS_RDY_SHIFT 4
+#define DCORE0_EDMA0_QM_CQ_IFIFO_STS_RDY_MASK 0x10
+#define DCORE0_EDMA0_QM_CQ_IFIFO_STS_CTL_STALL_SHIFT 8
+#define DCORE0_EDMA0_QM_CQ_IFIFO_STS_CTL_STALL_MASK 0x100
+
+/* DCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO */
+#define DCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI */
+#define DCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO */
+#define DCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI */
+#define DCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO */
+#define DCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI */
+#define DCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO */
+#define DCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI */
+#define DCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_CP_FENCE0_RDATA */
+#define DCORE0_EDMA0_QM_CP_FENCE0_RDATA_INC_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CP_FENCE0_RDATA_INC_VAL_MASK 0xF
+
+/* DCORE0_EDMA0_QM_CP_FENCE1_RDATA */
+#define DCORE0_EDMA0_QM_CP_FENCE1_RDATA_INC_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CP_FENCE1_RDATA_INC_VAL_MASK 0xF
+
+/* DCORE0_EDMA0_QM_CP_FENCE2_RDATA */
+#define DCORE0_EDMA0_QM_CP_FENCE2_RDATA_INC_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CP_FENCE2_RDATA_INC_VAL_MASK 0xF
+
+/* DCORE0_EDMA0_QM_CP_FENCE3_RDATA */
+#define DCORE0_EDMA0_QM_CP_FENCE3_RDATA_INC_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CP_FENCE3_RDATA_INC_VAL_MASK 0xF
+
+/* DCORE0_EDMA0_QM_CP_FENCE0_CNT */
+#define DCORE0_EDMA0_QM_CP_FENCE0_CNT_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CP_FENCE0_CNT_VAL_MASK 0x3FFF
+
+/* DCORE0_EDMA0_QM_CP_FENCE1_CNT */
+#define DCORE0_EDMA0_QM_CP_FENCE1_CNT_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CP_FENCE1_CNT_VAL_MASK 0x3FFF
+
+/* DCORE0_EDMA0_QM_CP_FENCE2_CNT */
+#define DCORE0_EDMA0_QM_CP_FENCE2_CNT_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CP_FENCE2_CNT_VAL_MASK 0x3FFF
+
+/* DCORE0_EDMA0_QM_CP_FENCE3_CNT */
+#define DCORE0_EDMA0_QM_CP_FENCE3_CNT_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CP_FENCE3_CNT_VAL_MASK 0x3FFF
+
+/* DCORE0_EDMA0_QM_CP_BARRIER_CFG */
+#define DCORE0_EDMA0_QM_CP_BARRIER_CFG_EBGUARD_SHIFT 0
+#define DCORE0_EDMA0_QM_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF
+#define DCORE0_EDMA0_QM_CP_BARRIER_CFG_RBGUARD_SHIFT 16
+#define DCORE0_EDMA0_QM_CP_BARRIER_CFG_RBGUARD_MASK 0xF0000
+
+/* DCORE0_EDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET */
+#define DCORE0_EDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFF
+
+/* DCORE0_EDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET */
+#define DCORE0_EDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFF
+
+/* DCORE0_EDMA0_QM_CP_LDMA_TSIZE_OFFSET */
+#define DCORE0_EDMA0_QM_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFF
+
+/* DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_0 */
+#define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_0_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_0_VAL_MASK 0xFFFF
+
+/* DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_1 */
+#define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_1_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_1_VAL_MASK 0xFFFF
+
+/* DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_2 */
+#define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_2_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_2_VAL_MASK 0xFFFF
+
+/* DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_3 */
+#define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_3_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_3_VAL_MASK 0xFFFF
+
+/* DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_4 */
+#define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_4_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_4_VAL_MASK 0xFFFF
+
+/* DCORE0_EDMA0_QM_CP_STS */
+#define DCORE0_EDMA0_QM_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0
+#define DCORE0_EDMA0_QM_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFF
+#define DCORE0_EDMA0_QM_CP_STS_ERDY_SHIFT 8
+#define DCORE0_EDMA0_QM_CP_STS_ERDY_MASK 0x100
+#define DCORE0_EDMA0_QM_CP_STS_SWITCH_EN_SHIFT 9
+#define DCORE0_EDMA0_QM_CP_STS_SWITCH_EN_MASK 0x200
+#define DCORE0_EDMA0_QM_CP_STS_MRDY_SHIFT 10
+#define DCORE0_EDMA0_QM_CP_STS_MRDY_MASK 0x400
+#define DCORE0_EDMA0_QM_CP_STS_SW_STOP_SHIFT 11
+#define DCORE0_EDMA0_QM_CP_STS_SW_STOP_MASK 0x800
+#define DCORE0_EDMA0_QM_CP_STS_FENCE_ID_SHIFT 12
+#define DCORE0_EDMA0_QM_CP_STS_FENCE_ID_MASK 0x3000
+#define DCORE0_EDMA0_QM_CP_STS_FENCE_IN_PROGRESS_SHIFT 14
+#define DCORE0_EDMA0_QM_CP_STS_FENCE_IN_PROGRESS_MASK 0x4000
+#define DCORE0_EDMA0_QM_CP_STS_FENCE_TARGET_SHIFT 16
+#define DCORE0_EDMA0_QM_CP_STS_FENCE_TARGET_MASK 0x3FFF0000
+#define DCORE0_EDMA0_QM_CP_STS_CUR_CQ_SHIFT 30
+#define DCORE0_EDMA0_QM_CP_STS_CUR_CQ_MASK 0x40000000
+
+/* DCORE0_EDMA0_QM_CP_CURRENT_INST_LO */
+#define DCORE0_EDMA0_QM_CP_CURRENT_INST_LO_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_CP_CURRENT_INST_HI */
+#define DCORE0_EDMA0_QM_CP_CURRENT_INST_HI_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_CP_PRED */
+#define DCORE0_EDMA0_QM_CP_PRED_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CP_PRED_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_CP_PRED_UPEN */
+#define DCORE0_EDMA0_QM_CP_PRED_UPEN_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CP_PRED_UPEN_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_CP_DBG_0 */
+#define DCORE0_EDMA0_QM_CP_DBG_0_CS_SHIFT 0
+#define DCORE0_EDMA0_QM_CP_DBG_0_CS_MASK 0x1F
+#define DCORE0_EDMA0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_SHIFT 5
+#define DCORE0_EDMA0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_MASK 0x20
+#define DCORE0_EDMA0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_SHIFT 6
+#define DCORE0_EDMA0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_MASK 0x40
+#define DCORE0_EDMA0_QM_CP_DBG_0_MREB_STALL_SHIFT 7
+#define DCORE0_EDMA0_QM_CP_DBG_0_MREB_STALL_MASK 0x80
+#define DCORE0_EDMA0_QM_CP_DBG_0_STALL_SHIFT 8
+#define DCORE0_EDMA0_QM_CP_DBG_0_STALL_MASK 0x100
+
+/* DCORE0_EDMA0_QM_CP_CPDMA_UP_CRED */
+#define DCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_TH_SHIFT 0
+#define DCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_TH_MASK 0x3
+#define DCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_VAL_SHIFT 8
+#define DCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_VAL_MASK 0x300
+
+/* DCORE0_EDMA0_QM_CP_IN_DATA_LO */
+#define DCORE0_EDMA0_QM_CP_IN_DATA_LO_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CP_IN_DATA_LO_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_CP_IN_DATA_HI */
+#define DCORE0_EDMA0_QM_CP_IN_DATA_HI_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CP_IN_DATA_HI_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_PQC_HBW_BASE_LO */
+#define DCORE0_EDMA0_QM_PQC_HBW_BASE_LO_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_PQC_HBW_BASE_LO_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_PQC_HBW_BASE_HI */
+#define DCORE0_EDMA0_QM_PQC_HBW_BASE_HI_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_PQC_HBW_BASE_HI_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_PQC_SIZE */
+#define DCORE0_EDMA0_QM_PQC_SIZE_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_PQC_SIZE_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_PQC_PI */
+#define DCORE0_EDMA0_QM_PQC_PI_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_PQC_PI_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_PQC_LBW_WDATA */
+#define DCORE0_EDMA0_QM_PQC_LBW_WDATA_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_PQC_LBW_WDATA_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_PQC_LBW_BASE_LO */
+#define DCORE0_EDMA0_QM_PQC_LBW_BASE_LO_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_PQC_LBW_BASE_LO_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_PQC_LBW_BASE_HI */
+#define DCORE0_EDMA0_QM_PQC_LBW_BASE_HI_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_PQC_LBW_BASE_HI_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_PQC_CFG */
+#define DCORE0_EDMA0_QM_PQC_CFG_EN_SHIFT 0
+#define DCORE0_EDMA0_QM_PQC_CFG_EN_MASK 0x1
+#define DCORE0_EDMA0_QM_PQC_CFG_DIRECT_SHIFT 4
+#define DCORE0_EDMA0_QM_PQC_CFG_DIRECT_MASK 0x10
+
+/* DCORE0_EDMA0_QM_PQC_SECURE_PUSH_IND */
+#define DCORE0_EDMA0_QM_PQC_SECURE_PUSH_IND_CP_NUM_SHIFT 0
+#define DCORE0_EDMA0_QM_PQC_SECURE_PUSH_IND_CP_NUM_MASK 0x3
+
+/* DCORE0_EDMA0_QM_ARB_MASK */
+#define DCORE0_EDMA0_QM_ARB_MASK_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_ARB_MASK_VAL_MASK 0xF
+
+/* DCORE0_EDMA0_QM_ARB_CFG_0 */
+#define DCORE0_EDMA0_QM_ARB_CFG_0_PRIO_TYPE_SHIFT 0
+#define DCORE0_EDMA0_QM_ARB_CFG_0_PRIO_TYPE_MASK 0x1
+#define DCORE0_EDMA0_QM_ARB_CFG_0_IS_MASTER_SHIFT 4
+#define DCORE0_EDMA0_QM_ARB_CFG_0_IS_MASTER_MASK 0x10
+#define DCORE0_EDMA0_QM_ARB_CFG_0_EN_SHIFT 8
+#define DCORE0_EDMA0_QM_ARB_CFG_0_EN_MASK 0x100
+#define DCORE0_EDMA0_QM_ARB_CFG_0_MST_MSG_NOSTALL_SHIFT 9
+#define DCORE0_EDMA0_QM_ARB_CFG_0_MST_MSG_NOSTALL_MASK 0x200
+
+/* DCORE0_EDMA0_QM_ARB_CHOICE_Q_PUSH */
+#define DCORE0_EDMA0_QM_ARB_CHOICE_Q_PUSH_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_ARB_CHOICE_Q_PUSH_VAL_MASK 0x3
+
+/* DCORE0_EDMA0_QM_ARB_WRR_WEIGHT */
+#define DCORE0_EDMA0_QM_ARB_WRR_WEIGHT_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_ARB_WRR_WEIGHT_VAL_MASK 0xFF
+
+/* DCORE0_EDMA0_QM_ARB_CFG_1 */
+#define DCORE0_EDMA0_QM_ARB_CFG_1_CLR_SHIFT 0
+#define DCORE0_EDMA0_QM_ARB_CFG_1_CLR_MASK 0x1
+
+/* DCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED */
+#define DCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_VAL_MASK 0x7F
+
+/* DCORE0_EDMA0_QM_ARB_MST_CRED_INC */
+#define DCORE0_EDMA0_QM_ARB_MST_CRED_INC_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_ARB_MST_CRED_INC_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST */
+#define DCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST */
+#define DCORE0_EDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_ARB_MST_SLAVE_EN */
+#define DCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_1 */
+#define DCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_1_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_1_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_ARB_SLV_CHOICE_WDT */
+#define DCORE0_EDMA0_QM_ARB_SLV_CHOICE_WDT_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_ARB_SLV_CHOICE_WDT_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_ARB_SLV_ID */
+#define DCORE0_EDMA0_QM_ARB_SLV_ID_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_ARB_SLV_ID_VAL_MASK 0x7F
+
+/* DCORE0_EDMA0_QM_ARB_MST_QUIET_PER */
+#define DCORE0_EDMA0_QM_ARB_MST_QUIET_PER_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_ARB_MST_QUIET_PER_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_ARB_MSG_MAX_INFLIGHT */
+#define DCORE0_EDMA0_QM_ARB_MSG_MAX_INFLIGHT_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_ARB_MSG_MAX_INFLIGHT_VAL_MASK 0x3F
+
+/* DCORE0_EDMA0_QM_ARB_BASE_LO */
+#define DCORE0_EDMA0_QM_ARB_BASE_LO_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_ARB_BASE_LO_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_ARB_BASE_HI */
+#define DCORE0_EDMA0_QM_ARB_BASE_HI_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_ARB_BASE_HI_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_ARB_STATE_STS */
+#define DCORE0_EDMA0_QM_ARB_STATE_STS_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_ARB_STATE_STS_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_ARB_CHOICE_FULLNESS_STS */
+#define DCORE0_EDMA0_QM_ARB_CHOICE_FULLNESS_STS_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_ARB_CHOICE_FULLNESS_STS_VAL_MASK 0x7F
+
+/* DCORE0_EDMA0_QM_ARB_MSG_STS */
+#define DCORE0_EDMA0_QM_ARB_MSG_STS_FULL_SHIFT 0
+#define DCORE0_EDMA0_QM_ARB_MSG_STS_FULL_MASK 0x1
+#define DCORE0_EDMA0_QM_ARB_MSG_STS_NO_INFLIGHT_SHIFT 1
+#define DCORE0_EDMA0_QM_ARB_MSG_STS_NO_INFLIGHT_MASK 0x2
+
+/* DCORE0_EDMA0_QM_ARB_SLV_CHOICE_Q_HEAD */
+#define DCORE0_EDMA0_QM_ARB_SLV_CHOICE_Q_HEAD_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_ARB_SLV_CHOICE_Q_HEAD_VAL_MASK 0x3
+
+/* DCORE0_EDMA0_QM_ARB_ERR_CAUSE */
+#define DCORE0_EDMA0_QM_ARB_ERR_CAUSE_CHOICE_OVF_SHIFT 0
+#define DCORE0_EDMA0_QM_ARB_ERR_CAUSE_CHOICE_OVF_MASK 0x1
+#define DCORE0_EDMA0_QM_ARB_ERR_CAUSE_CHOICE_WDT_SHIFT 1
+#define DCORE0_EDMA0_QM_ARB_ERR_CAUSE_CHOICE_WDT_MASK 0x2
+#define DCORE0_EDMA0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_SHIFT 2
+#define DCORE0_EDMA0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_MASK 0x4
+
+/* DCORE0_EDMA0_QM_ARB_ERR_MSG_EN */
+#define DCORE0_EDMA0_QM_ARB_ERR_MSG_EN_CHOICE_OVF_SHIFT 0
+#define DCORE0_EDMA0_QM_ARB_ERR_MSG_EN_CHOICE_OVF_MASK 0x1
+#define DCORE0_EDMA0_QM_ARB_ERR_MSG_EN_CHOICE_WDT_SHIFT 1
+#define DCORE0_EDMA0_QM_ARB_ERR_MSG_EN_CHOICE_WDT_MASK 0x2
+#define DCORE0_EDMA0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_SHIFT 2
+#define DCORE0_EDMA0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4
+
+/* DCORE0_EDMA0_QM_ARB_ERR_STS_DRP */
+#define DCORE0_EDMA0_QM_ARB_ERR_STS_DRP_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_ARB_ERR_STS_DRP_VAL_MASK 0x3
+
+/* DCORE0_EDMA0_QM_ARB_MST_CRED_STS */
+#define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_VAL_MASK 0x7F
+#define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_IDX_SHIFT 24
+#define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_IDX_MASK 0x1F000000
+
+/* DCORE0_EDMA0_QM_ARB_MST_CRED_STS_1 */
+#define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_1_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_1_VAL_MASK 0x7F
+#define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_1_IDX_SHIFT 24
+#define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_1_IDX_MASK 0x1F000000
+
+/* DCORE0_EDMA0_QM_CSMR_STRICT_PRIO_CFG */
+#define DCORE0_EDMA0_QM_CSMR_STRICT_PRIO_CFG_ARB_TYPE_SHIFT 0
+#define DCORE0_EDMA0_QM_CSMR_STRICT_PRIO_CFG_ARB_TYPE_MASK 0x1
+#define DCORE0_EDMA0_QM_CSMR_STRICT_PRIO_CFG_PER_ENTRY_SHIFT 4
+#define DCORE0_EDMA0_QM_CSMR_STRICT_PRIO_CFG_PER_ENTRY_MASK 0x10
+
+/* DCORE0_EDMA0_QM_ARC_CQ_CFG0 */
+#define DCORE0_EDMA0_QM_ARC_CQ_CFG0_IF_B2B_EN_SHIFT 0
+#define DCORE0_EDMA0_QM_ARC_CQ_CFG0_IF_B2B_EN_MASK 0x1
+#define DCORE0_EDMA0_QM_ARC_CQ_CFG0_IF_MSG_EN_SHIFT 1
+#define DCORE0_EDMA0_QM_ARC_CQ_CFG0_IF_MSG_EN_MASK 0x2
+#define DCORE0_EDMA0_QM_ARC_CQ_CFG0_CTL_MSG_EN_SHIFT 2
+#define DCORE0_EDMA0_QM_ARC_CQ_CFG0_CTL_MSG_EN_MASK 0x4
+
+/* DCORE0_EDMA0_QM_ARC_CQ_CFG1 */
+#define DCORE0_EDMA0_QM_ARC_CQ_CFG1_CREDIT_LIM_SHIFT 0
+#define DCORE0_EDMA0_QM_ARC_CQ_CFG1_CREDIT_LIM_MASK 0xFF
+#define DCORE0_EDMA0_QM_ARC_CQ_CFG1_MAX_INFLIGHT_SHIFT 16
+#define DCORE0_EDMA0_QM_ARC_CQ_CFG1_MAX_INFLIGHT_MASK 0xFF0000
+
+/* DCORE0_EDMA0_QM_ARC_CQ_PTR_LO */
+#define DCORE0_EDMA0_QM_ARC_CQ_PTR_LO_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_ARC_CQ_PTR_LO_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_ARC_CQ_PTR_HI */
+#define DCORE0_EDMA0_QM_ARC_CQ_PTR_HI_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_ARC_CQ_PTR_HI_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_ARC_CQ_TSIZE */
+#define DCORE0_EDMA0_QM_ARC_CQ_TSIZE_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_ARC_CQ_TSIZE_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_ARC_CQ_CTL */
+#define DCORE0_EDMA0_QM_ARC_CQ_CTL_UP_SHIFT 28
+#define DCORE0_EDMA0_QM_ARC_CQ_CTL_UP_MASK 0xF0000000
+
+/* DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS */
+#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS_CNT_SHIFT 0
+#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS_CNT_MASK 0x7
+#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS_RDY_SHIFT 4
+#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS_RDY_MASK 0x10
+#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS_CTL_STALL_SHIFT 8
+#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS_CTL_STALL_MASK 0x100
+
+/* DCORE0_EDMA0_QM_ARC_CQ_STS0 */
+#define DCORE0_EDMA0_QM_ARC_CQ_STS0_CREDIT_CNT_SHIFT 0
+#define DCORE0_EDMA0_QM_ARC_CQ_STS0_CREDIT_CNT_MASK 0xFF
+#define DCORE0_EDMA0_QM_ARC_CQ_STS0_FREE_CNT_SHIFT 8
+#define DCORE0_EDMA0_QM_ARC_CQ_STS0_FREE_CNT_MASK 0xFF00
+#define DCORE0_EDMA0_QM_ARC_CQ_STS0_INFLIGHT_CNT_SHIFT 16
+#define DCORE0_EDMA0_QM_ARC_CQ_STS0_INFLIGHT_CNT_MASK 0xFF0000
+
+/* DCORE0_EDMA0_QM_ARC_CQ_STS1 */
+#define DCORE0_EDMA0_QM_ARC_CQ_STS1_BUF_EMPTY_SHIFT 0
+#define DCORE0_EDMA0_QM_ARC_CQ_STS1_BUF_EMPTY_MASK 0x1
+#define DCORE0_EDMA0_QM_ARC_CQ_STS1_BUSY_SHIFT 1
+#define DCORE0_EDMA0_QM_ARC_CQ_STS1_BUSY_MASK 0x2
+
+/* DCORE0_EDMA0_QM_ARC_CQ_TSIZE_STS */
+#define DCORE0_EDMA0_QM_ARC_CQ_TSIZE_STS_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_ARC_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_ARC_CQ_PTR_LO_STS */
+#define DCORE0_EDMA0_QM_ARC_CQ_PTR_LO_STS_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_ARC_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_ARC_CQ_PTR_HI_STS */
+#define DCORE0_EDMA0_QM_ARC_CQ_PTR_HI_STS_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_ARC_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_CP_WR_ARC_ADDR_HI */
+#define DCORE0_EDMA0_QM_CP_WR_ARC_ADDR_HI_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CP_WR_ARC_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_CP_WR_ARC_ADDR_LO */
+#define DCORE0_EDMA0_QM_CP_WR_ARC_ADDR_LO_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CP_WR_ARC_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI */
+#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO */
+#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI */
+#define DCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO */
+#define DCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_HI */
+#define DCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_HI_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_LO */
+#define DCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_LO_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_HI */
+#define DCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_HI_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_LO */
+#define DCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_LO_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_ADDR_OVRD */
+#define DCORE0_EDMA0_QM_ADDR_OVRD_IDX_SHIFT 0
+#define DCORE0_EDMA0_QM_ADDR_OVRD_IDX_MASK 0xFF
+
+/* DCORE0_EDMA0_QM_CQ_IFIFO_CI */
+#define DCORE0_EDMA0_QM_CQ_IFIFO_CI_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CQ_IFIFO_CI_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_ARC_CQ_IFIFO_CI */
+#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_CI_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_CI_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_CQ_CTL_CI */
+#define DCORE0_EDMA0_QM_CQ_CTL_CI_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CQ_CTL_CI_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_ARC_CQ_CTL_CI */
+#define DCORE0_EDMA0_QM_ARC_CQ_CTL_CI_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_ARC_CQ_CTL_CI_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_CP_CFG */
+#define DCORE0_EDMA0_QM_CP_CFG_SWITCH_EN_SHIFT 0
+#define DCORE0_EDMA0_QM_CP_CFG_SWITCH_EN_MASK 0x1
+#define DCORE0_EDMA0_QM_CP_CFG_SWITCH_WD_EN_SHIFT 1
+#define DCORE0_EDMA0_QM_CP_CFG_SWITCH_WD_EN_MASK 0x2
+
+/* DCORE0_EDMA0_QM_CP_EXT_SWITCH */
+#define DCORE0_EDMA0_QM_CP_EXT_SWITCH_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CP_EXT_SWITCH_VAL_MASK 0x1
+
+/* DCORE0_EDMA0_QM_CP_SWITCH_WD_SET */
+#define DCORE0_EDMA0_QM_CP_SWITCH_WD_SET_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CP_SWITCH_WD_SET_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_CP_SWITCH_WD */
+#define DCORE0_EDMA0_QM_CP_SWITCH_WD_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_CP_SWITCH_WD_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_LO */
+#define DCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_LO_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_LO_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_HI */
+#define DCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_HI_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_HI_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_ENGINE_BASE_ADDR_HI */
+#define DCORE0_EDMA0_QM_ENGINE_BASE_ADDR_HI_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_ENGINE_BASE_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_ENGINE_BASE_ADDR_LO */
+#define DCORE0_EDMA0_QM_ENGINE_BASE_ADDR_LO_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_ENGINE_BASE_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_ENGINE_ADDR_RANGE_SIZE */
+#define DCORE0_EDMA0_QM_ENGINE_ADDR_RANGE_SIZE_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_ENGINE_ADDR_RANGE_SIZE_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI */
+#define DCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO */
+#define DCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_QM_BASE_ADDR_HI */
+#define DCORE0_EDMA0_QM_QM_BASE_ADDR_HI_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_QM_BASE_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_QM_BASE_ADDR_LO */
+#define DCORE0_EDMA0_QM_QM_BASE_ADDR_LO_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_QM_BASE_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_ARC_PQC_SECURE_PUSH_IND */
+#define DCORE0_EDMA0_QM_ARC_PQC_SECURE_PUSH_IND_CP_NUM_SHIFT 0
+#define DCORE0_EDMA0_QM_ARC_PQC_SECURE_PUSH_IND_CP_NUM_MASK 0x3
+
+/* DCORE0_EDMA0_QM_PQC_STS_0 */
+#define DCORE0_EDMA0_QM_PQC_STS_0_COMP_DATA_SHIFT 0
+#define DCORE0_EDMA0_QM_PQC_STS_0_COMP_DATA_MASK 0xFFFF
+#define DCORE0_EDMA0_QM_PQC_STS_0_COMP_OFST_SHIFT 16
+#define DCORE0_EDMA0_QM_PQC_STS_0_COMP_OFST_MASK 0xFFFF0000
+
+/* DCORE0_EDMA0_QM_PQC_STS_1 */
+#define DCORE0_EDMA0_QM_PQC_STS_1_COMP_FIFO_CNTR_SHIFT 0
+#define DCORE0_EDMA0_QM_PQC_STS_1_COMP_FIFO_CNTR_MASK 0xF
+#define DCORE0_EDMA0_QM_PQC_STS_1_COMP_FIFO_EMPTY_SHIFT 4
+#define DCORE0_EDMA0_QM_PQC_STS_1_COMP_FIFO_EMPTY_MASK 0x10
+#define DCORE0_EDMA0_QM_PQC_STS_1_COMP_FIFO_FULL_SHIFT 5
+#define DCORE0_EDMA0_QM_PQC_STS_1_COMP_FIFO_FULL_MASK 0x20
+
+/* DCORE0_EDMA0_QM_SEI_STATUS */
+#define DCORE0_EDMA0_QM_SEI_STATUS_QM_INT_SHIFT 0
+#define DCORE0_EDMA0_QM_SEI_STATUS_QM_INT_MASK 0x1
+#define DCORE0_EDMA0_QM_SEI_STATUS_ARC_INT_SHIFT 1
+#define DCORE0_EDMA0_QM_SEI_STATUS_ARC_INT_MASK 0x2
+
+/* DCORE0_EDMA0_QM_SEI_MASK */
+#define DCORE0_EDMA0_QM_SEI_MASK_QM_INT_SHIFT 0
+#define DCORE0_EDMA0_QM_SEI_MASK_QM_INT_MASK 0x1
+#define DCORE0_EDMA0_QM_SEI_MASK_ARC_INT_SHIFT 1
+#define DCORE0_EDMA0_QM_SEI_MASK_ARC_INT_MASK 0x2
+
+/* DCORE0_EDMA0_QM_GLBL_ERR_ADDR_LO */
+#define DCORE0_EDMA0_QM_GLBL_ERR_ADDR_LO_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_GLBL_ERR_ADDR_HI */
+#define DCORE0_EDMA0_QM_GLBL_ERR_ADDR_HI_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_GLBL_ERR_WDATA */
+#define DCORE0_EDMA0_QM_GLBL_ERR_WDATA_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_L2H_MASK_LO */
+#define DCORE0_EDMA0_QM_L2H_MASK_LO_VAL_SHIFT 20
+#define DCORE0_EDMA0_QM_L2H_MASK_LO_VAL_MASK 0xFFF00000
+
+/* DCORE0_EDMA0_QM_L2H_MASK_HI */
+#define DCORE0_EDMA0_QM_L2H_MASK_HI_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_L2H_MASK_HI_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_L2H_CMPR_LO */
+#define DCORE0_EDMA0_QM_L2H_CMPR_LO_VAL_SHIFT 20
+#define DCORE0_EDMA0_QM_L2H_CMPR_LO_VAL_MASK 0xFFF00000
+
+/* DCORE0_EDMA0_QM_L2H_CMPR_HI */
+#define DCORE0_EDMA0_QM_L2H_CMPR_HI_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_L2H_CMPR_HI_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_LOCAL_RANGE_BASE */
+#define DCORE0_EDMA0_QM_LOCAL_RANGE_BASE_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_LOCAL_RANGE_BASE_VAL_MASK 0xFFFF
+
+/* DCORE0_EDMA0_QM_LOCAL_RANGE_SIZE */
+#define DCORE0_EDMA0_QM_LOCAL_RANGE_SIZE_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_LOCAL_RANGE_SIZE_VAL_MASK 0xFFFF
+
+/* DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_1 */
+#define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_SHIFT 0
+#define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_MASK 0xFF
+#define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_1_EN_SHIFT 31
+#define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_1_EN_MASK 0x80000000
+
+/* DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_0 */
+#define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0
+#define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF
+#define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_SHIFT 16
+#define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_MASK 0xFF0000
+
+/* DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_1 */
+#define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_SHIFT 0
+#define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_MASK 0xFF
+#define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_1_EN_SHIFT 31
+#define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_1_EN_MASK 0x80000000
+
+/* DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_0 */
+#define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0
+#define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF
+#define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_SHIFT 16
+#define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_MASK 0xFF0000
+
+/* DCORE0_EDMA0_QM_IND_GW_APB_CFG */
+#define DCORE0_EDMA0_QM_IND_GW_APB_CFG_ADDR_SHIFT 0
+#define DCORE0_EDMA0_QM_IND_GW_APB_CFG_ADDR_MASK 0x7FFFFFFF
+#define DCORE0_EDMA0_QM_IND_GW_APB_CFG_CMD_SHIFT 31
+#define DCORE0_EDMA0_QM_IND_GW_APB_CFG_CMD_MASK 0x80000000
+
+/* DCORE0_EDMA0_QM_IND_GW_APB_WDATA */
+#define DCORE0_EDMA0_QM_IND_GW_APB_WDATA_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_IND_GW_APB_WDATA_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_IND_GW_APB_RDATA */
+#define DCORE0_EDMA0_QM_IND_GW_APB_RDATA_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_IND_GW_APB_RDATA_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_IND_GW_APB_STATUS */
+#define DCORE0_EDMA0_QM_IND_GW_APB_STATUS_RDY_SHIFT 0
+#define DCORE0_EDMA0_QM_IND_GW_APB_STATUS_RDY_MASK 0x1
+#define DCORE0_EDMA0_QM_IND_GW_APB_STATUS_ERR_SHIFT 1
+#define DCORE0_EDMA0_QM_IND_GW_APB_STATUS_ERR_MASK 0x2
+
+/* DCORE0_EDMA0_QM_PERF_CNT_FREE_LO */
+#define DCORE0_EDMA0_QM_PERF_CNT_FREE_LO_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_PERF_CNT_FREE_LO_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_PERF_CNT_FREE_HI */
+#define DCORE0_EDMA0_QM_PERF_CNT_FREE_HI_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_PERF_CNT_FREE_HI_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_PERF_CNT_IDLE_LO */
+#define DCORE0_EDMA0_QM_PERF_CNT_IDLE_LO_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_PERF_CNT_IDLE_LO_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_PERF_CNT_IDLE_HI */
+#define DCORE0_EDMA0_QM_PERF_CNT_IDLE_HI_VAL_SHIFT 0
+#define DCORE0_EDMA0_QM_PERF_CNT_IDLE_HI_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_EDMA0_QM_PERF_CNT_CFG */
+#define DCORE0_EDMA0_QM_PERF_CNT_CFG_PQ_MASK_SHIFT 0
+#define DCORE0_EDMA0_QM_PERF_CNT_CFG_PQ_MASK_MASK 0xF
+#define DCORE0_EDMA0_QM_PERF_CNT_CFG_CQ_MASK_SHIFT 8
+#define DCORE0_EDMA0_QM_PERF_CNT_CFG_CQ_MASK_MASK 0x1F00
+#define DCORE0_EDMA0_QM_PERF_CNT_CFG_CP_MASK_SHIFT 16
+#define DCORE0_EDMA0_QM_PERF_CNT_CFG_CP_MASK_MASK 0x1F0000
+#define DCORE0_EDMA0_QM_PERF_CNT_CFG_AGENT_MASK_SHIFT 24
+#define DCORE0_EDMA0_QM_PERF_CNT_CFG_AGENT_MASK_MASK 0x1000000
+#define DCORE0_EDMA0_QM_PERF_CNT_CFG_EN_FREE_SHIFT 30
+#define DCORE0_EDMA0_QM_PERF_CNT_CFG_EN_FREE_MASK 0x40000000
+#define DCORE0_EDMA0_QM_PERF_CNT_CFG_EN_IDLE_SHIFT 31
+#define DCORE0_EDMA0_QM_PERF_CNT_CFG_EN_IDLE_MASK 0x80000000
+
+#endif /* ASIC_REG_DCORE0_EDMA0_QM_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_regs.h
new file mode 100644
index 000000000000..32d475b9ed11
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_regs.h
@@ -0,0 +1,1057 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_EDMA0_QM_REGS_H_
+#define ASIC_REG_DCORE0_EDMA0_QM_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_EDMA0_QM
+ *   (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmDCORE0_EDMA0_QM_GLBL_CFG0 0x41CA000
+
+#define mmDCORE0_EDMA0_QM_GLBL_CFG1 0x41CA004
+
+#define mmDCORE0_EDMA0_QM_GLBL_CFG2 0x41CA008
+
+#define mmDCORE0_EDMA0_QM_GLBL_ERR_CFG 0x41CA00C
+
+#define mmDCORE0_EDMA0_QM_GLBL_ERR_CFG1 0x41CA010
+
+#define mmDCORE0_EDMA0_QM_GLBL_ERR_ARC_HALT_EN 0x41CA014
+
+#define mmDCORE0_EDMA0_QM_GLBL_AXCACHE 0x41CA018
+
+#define mmDCORE0_EDMA0_QM_GLBL_STS0 0x41CA01C
+
+#define mmDCORE0_EDMA0_QM_GLBL_STS1 0x41CA020
+
+#define mmDCORE0_EDMA0_QM_GLBL_ERR_STS_0 0x41CA024
+
+#define mmDCORE0_EDMA0_QM_GLBL_ERR_STS_1 0x41CA028
+
+#define mmDCORE0_EDMA0_QM_GLBL_ERR_STS_2 0x41CA02C
+
+#define mmDCORE0_EDMA0_QM_GLBL_ERR_STS_3 0x41CA030
+
+#define mmDCORE0_EDMA0_QM_GLBL_ERR_STS_4 0x41CA034
+
+#define mmDCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_0 0x41CA038
+
+#define mmDCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_1 0x41CA03C
+
+#define mmDCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_2 0x41CA040
+
+#define mmDCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_3 0x41CA044
+
+#define mmDCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4 0x41CA048
+
+#define mmDCORE0_EDMA0_QM_GLBL_PROT 0x41CA04C
+
+#define mmDCORE0_EDMA0_QM_PQ_BASE_LO_0 0x41CA050
+
+#define mmDCORE0_EDMA0_QM_PQ_BASE_LO_1 0x41CA054
+
+#define mmDCORE0_EDMA0_QM_PQ_BASE_LO_2 0x41CA058
+
+#define mmDCORE0_EDMA0_QM_PQ_BASE_LO_3 0x41CA05C
+
+#define mmDCORE0_EDMA0_QM_PQ_BASE_HI_0 0x41CA060
+
+#define mmDCORE0_EDMA0_QM_PQ_BASE_HI_1 0x41CA064
+
+#define mmDCORE0_EDMA0_QM_PQ_BASE_HI_2 0x41CA068
+
+#define mmDCORE0_EDMA0_QM_PQ_BASE_HI_3 0x41CA06C
+
+#define mmDCORE0_EDMA0_QM_PQ_SIZE_0 0x41CA070
+
+#define mmDCORE0_EDMA0_QM_PQ_SIZE_1 0x41CA074
+
+#define mmDCORE0_EDMA0_QM_PQ_SIZE_2 0x41CA078
+
+#define mmDCORE0_EDMA0_QM_PQ_SIZE_3 0x41CA07C
+
+#define mmDCORE0_EDMA0_QM_PQ_PI_0 0x41CA080
+
+#define mmDCORE0_EDMA0_QM_PQ_PI_1 0x41CA084
+
+#define mmDCORE0_EDMA0_QM_PQ_PI_2 0x41CA088
+
+#define mmDCORE0_EDMA0_QM_PQ_PI_3 0x41CA08C
+
+#define mmDCORE0_EDMA0_QM_PQ_CI_0 0x41CA090
+
+#define mmDCORE0_EDMA0_QM_PQ_CI_1 0x41CA094
+
+#define mmDCORE0_EDMA0_QM_PQ_CI_2 0x41CA098
+
+#define mmDCORE0_EDMA0_QM_PQ_CI_3 0x41CA09C
+
+#define mmDCORE0_EDMA0_QM_PQ_CFG0_0 0x41CA0A0
+
+#define mmDCORE0_EDMA0_QM_PQ_CFG0_1 0x41CA0A4
+
+#define mmDCORE0_EDMA0_QM_PQ_CFG0_2 0x41CA0A8
+
+#define mmDCORE0_EDMA0_QM_PQ_CFG0_3 0x41CA0AC
+
+#define mmDCORE0_EDMA0_QM_PQ_CFG1_0 0x41CA0B0
+
+#define mmDCORE0_EDMA0_QM_PQ_CFG1_1 0x41CA0B4
+
+#define mmDCORE0_EDMA0_QM_PQ_CFG1_2 0x41CA0B8
+
+#define mmDCORE0_EDMA0_QM_PQ_CFG1_3 0x41CA0BC
+
+#define mmDCORE0_EDMA0_QM_PQ_STS0_0 0x41CA0C0
+
+#define mmDCORE0_EDMA0_QM_PQ_STS0_1 0x41CA0C4
+
+#define mmDCORE0_EDMA0_QM_PQ_STS0_2 0x41CA0C8
+
+#define mmDCORE0_EDMA0_QM_PQ_STS0_3 0x41CA0CC
+
+#define mmDCORE0_EDMA0_QM_PQ_STS1_0 0x41CA0D0
+
+#define mmDCORE0_EDMA0_QM_PQ_STS1_1 0x41CA0D4
+
+#define mmDCORE0_EDMA0_QM_PQ_STS1_2 0x41CA0D8
+
+#define mmDCORE0_EDMA0_QM_PQ_STS1_3 0x41CA0DC
+
+#define mmDCORE0_EDMA0_QM_CQ_CFG0_0 0x41CA0E0
+
+#define mmDCORE0_EDMA0_QM_CQ_CFG0_1 0x41CA0E4
+
+#define mmDCORE0_EDMA0_QM_CQ_CFG0_2 0x41CA0E8
+
+#define mmDCORE0_EDMA0_QM_CQ_CFG0_3 0x41CA0EC
+
+#define mmDCORE0_EDMA0_QM_CQ_CFG0_4 0x41CA0F0
+
+#define mmDCORE0_EDMA0_QM_CQ_STS0_0 0x41CA0F4
+
+#define mmDCORE0_EDMA0_QM_CQ_STS0_1 0x41CA0F8
+
+#define mmDCORE0_EDMA0_QM_CQ_STS0_2 0x41CA0FC
+
+#define mmDCORE0_EDMA0_QM_CQ_STS0_3 0x41CA100
+
+#define mmDCORE0_EDMA0_QM_CQ_STS0_4 0x41CA104
+
+#define mmDCORE0_EDMA0_QM_CQ_CFG1_0 0x41CA108
+
+#define mmDCORE0_EDMA0_QM_CQ_CFG1_1 0x41CA10C
+
+#define mmDCORE0_EDMA0_QM_CQ_CFG1_2 0x41CA110
+
+#define mmDCORE0_EDMA0_QM_CQ_CFG1_3 0x41CA114
+
+#define mmDCORE0_EDMA0_QM_CQ_CFG1_4 0x41CA118
+
+#define mmDCORE0_EDMA0_QM_CQ_STS1_0 0x41CA11C
+
+#define mmDCORE0_EDMA0_QM_CQ_STS1_1 0x41CA120
+
+#define mmDCORE0_EDMA0_QM_CQ_STS1_2 0x41CA124
+
+#define mmDCORE0_EDMA0_QM_CQ_STS1_3 0x41CA128
+
+#define mmDCORE0_EDMA0_QM_CQ_STS1_4 0x41CA12C
+
+#define mmDCORE0_EDMA0_QM_CQ_PTR_LO_0 0x41CA150
+
+#define mmDCORE0_EDMA0_QM_CQ_PTR_HI_0 0x41CA154
+
+#define mmDCORE0_EDMA0_QM_CQ_TSIZE_0 0x41CA158
+
+#define mmDCORE0_EDMA0_QM_CQ_CTL_0 0x41CA15C
+
+#define mmDCORE0_EDMA0_QM_CQ_PTR_LO_1 0x41CA160
+
+#define mmDCORE0_EDMA0_QM_CQ_PTR_HI_1 0x41CA164
+
+#define mmDCORE0_EDMA0_QM_CQ_TSIZE_1 0x41CA168
+
+#define mmDCORE0_EDMA0_QM_CQ_CTL_1 0x41CA16C
+
+#define mmDCORE0_EDMA0_QM_CQ_PTR_LO_2 0x41CA170
+
+#define mmDCORE0_EDMA0_QM_CQ_PTR_HI_2 0x41CA174
+
+#define mmDCORE0_EDMA0_QM_CQ_TSIZE_2 0x41CA178
+
+#define mmDCORE0_EDMA0_QM_CQ_CTL_2 0x41CA17C
+
+#define mmDCORE0_EDMA0_QM_CQ_PTR_LO_3 0x41CA180
+
+#define mmDCORE0_EDMA0_QM_CQ_PTR_HI_3 0x41CA184
+
+#define mmDCORE0_EDMA0_QM_CQ_TSIZE_3 0x41CA188
+
+#define mmDCORE0_EDMA0_QM_CQ_CTL_3 0x41CA18C
+
+#define mmDCORE0_EDMA0_QM_CQ_PTR_LO_4 0x41CA190
+
+#define mmDCORE0_EDMA0_QM_CQ_PTR_HI_4 0x41CA194
+
+#define mmDCORE0_EDMA0_QM_CQ_TSIZE_4 0x41CA198
+
+#define mmDCORE0_EDMA0_QM_CQ_CTL_4 0x41CA19C
+
+#define mmDCORE0_EDMA0_QM_CQ_TSIZE_STS_0 0x41CA1A0
+
+#define mmDCORE0_EDMA0_QM_CQ_TSIZE_STS_1 0x41CA1A4
+
+#define mmDCORE0_EDMA0_QM_CQ_TSIZE_STS_2 0x41CA1A8
+
+#define mmDCORE0_EDMA0_QM_CQ_TSIZE_STS_3 0x41CA1AC
+
+#define mmDCORE0_EDMA0_QM_CQ_TSIZE_STS_4 0x41CA1B0
+
+#define mmDCORE0_EDMA0_QM_CQ_PTR_LO_STS_0 0x41CA1B4
+
+#define mmDCORE0_EDMA0_QM_CQ_PTR_LO_STS_1 0x41CA1B8
+
+#define mmDCORE0_EDMA0_QM_CQ_PTR_LO_STS_2 0x41CA1BC
+
+#define mmDCORE0_EDMA0_QM_CQ_PTR_LO_STS_3 0x41CA1C0
+
+#define mmDCORE0_EDMA0_QM_CQ_PTR_LO_STS_4 0x41CA1C4
+
+#define mmDCORE0_EDMA0_QM_CQ_PTR_HI_STS_0 0x41CA1C8
+
+#define mmDCORE0_EDMA0_QM_CQ_PTR_HI_STS_1 0x41CA1CC
+
+#define mmDCORE0_EDMA0_QM_CQ_PTR_HI_STS_2 0x41CA1D0
+
+#define mmDCORE0_EDMA0_QM_CQ_PTR_HI_STS_3 0x41CA1D4
+
+#define mmDCORE0_EDMA0_QM_CQ_PTR_HI_STS_4 0x41CA1D8
+
+#define mmDCORE0_EDMA0_QM_CQ_IFIFO_STS_0 0x41CA1DC
+
+#define mmDCORE0_EDMA0_QM_CQ_IFIFO_STS_1 0x41CA1E0
+
+#define mmDCORE0_EDMA0_QM_CQ_IFIFO_STS_2 0x41CA1E4
+
+#define mmDCORE0_EDMA0_QM_CQ_IFIFO_STS_3 0x41CA1E8
+
+#define mmDCORE0_EDMA0_QM_CQ_IFIFO_STS_4 0x41CA1EC
+
+#define mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 0x41CA1F0
+
+#define mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_1 0x41CA1F4
+
+#define mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_2 0x41CA1F8
+
+#define mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_3 0x41CA1FC
+
+#define mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_4 0x41CA200
+
+#define mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 0x41CA204
+
+#define mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_1 0x41CA208
+
+#define mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_2 0x41CA20C
+
+#define mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_3 0x41CA210
+
+#define mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_4 0x41CA214
+
+#define mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 0x41CA218
+
+#define mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_1 0x41CA21C
+
+#define mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_2 0x41CA220
+
+#define mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_3 0x41CA224
+
+#define mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_4 0x41CA228
+
+#define mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 0x41CA22C
+
+#define mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_1 0x41CA230
+
+#define mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_2 0x41CA234
+
+#define mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_3 0x41CA238
+
+#define mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_4 0x41CA23C
+
+#define mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_0 0x41CA240
+
+#define mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_1 0x41CA244
+
+#define mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_2 0x41CA248
+
+#define mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_3 0x41CA24C
+
+#define mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_4 0x41CA250
+
+#define mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_0 0x41CA254
+
+#define mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_1 0x41CA258
+
+#define mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_2 0x41CA25C
+
+#define mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_3 0x41CA260
+
+#define mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_4 0x41CA264
+
+#define mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_0 0x41CA268
+
+#define mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_1 0x41CA26C
+
+#define mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_2 0x41CA270
+
+#define mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_3 0x41CA274
+
+#define mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_4 0x41CA278
+
+#define mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_0 0x41CA27C
+
+#define mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_1 0x41CA280
+
+#define mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_2 0x41CA284
+
+#define mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_3 0x41CA288
+
+#define mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_4 0x41CA28C
+
+#define mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_0 0x41CA290
+
+#define mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_1 0x41CA294
+
+#define mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_2 0x41CA298
+
+#define mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_3 0x41CA29C
+
+#define mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_4 0x41CA2A0
+
+#define mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_0 0x41CA2A4
+
+#define mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_1 0x41CA2A8
+
+#define mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_2 0x41CA2AC
+
+#define mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_3 0x41CA2B0
+
+#define mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_4 0x41CA2B4
+
+#define mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_0 0x41CA2B8
+
+#define mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_1 0x41CA2BC
+
+#define mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_2 0x41CA2C0
+
+#define mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_3 0x41CA2C4
+
+#define mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_4 0x41CA2C8
+
+#define mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_0 0x41CA2CC
+
+#define mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_1 0x41CA2D0
+
+#define mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_2 0x41CA2D4
+
+#define mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_3 0x41CA2D8
+
+#define mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_4 0x41CA2DC
+
+#define mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_0 0x41CA2E0
+
+#define mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_1 0x41CA2E4
+
+#define mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_2 0x41CA2E8
+
+#define mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_3 0x41CA2EC
+
+#define mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_4 0x41CA2F0
+
+#define mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_0 0x41CA2F4
+
+#define mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_1 0x41CA2F8
+
+#define mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_2 0x41CA2FC
+
+#define mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_3 0x41CA300
+
+#define mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_4 0x41CA304
+
+#define mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_0 0x41CA308
+
+#define mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_1 0x41CA30C
+
+#define mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_2 0x41CA310
+
+#define mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_3 0x41CA314
+
+#define mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_4 0x41CA318
+
+#define mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_0 0x41CA31C
+
+#define mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_1 0x41CA320
+
+#define mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_2 0x41CA324
+
+#define mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_3 0x41CA328
+
+#define mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_4 0x41CA32C
+
+#define mmDCORE0_EDMA0_QM_CP_BARRIER_CFG 0x41CA330
+
+#define mmDCORE0_EDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0x41CA334
+
+#define mmDCORE0_EDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET 0x41CA338
+
+#define mmDCORE0_EDMA0_QM_CP_LDMA_TSIZE_OFFSET 0x41CA33C
+
+#define mmDCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_0 0x41CA340
+
+#define mmDCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_1 0x41CA344
+
+#define mmDCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_2 0x41CA348
+
+#define mmDCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_3 0x41CA34C
+
+#define mmDCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_4 0x41CA350
+
+#define mmDCORE0_EDMA0_QM_CP_STS_0 0x41CA368
+
+#define mmDCORE0_EDMA0_QM_CP_STS_1 0x41CA36C
+
+#define mmDCORE0_EDMA0_QM_CP_STS_2 0x41CA370
+
+#define mmDCORE0_EDMA0_QM_CP_STS_3 0x41CA374
+
+#define mmDCORE0_EDMA0_QM_CP_STS_4 0x41CA378
+
+#define mmDCORE0_EDMA0_QM_CP_CURRENT_INST_LO_0 0x41CA37C
+
+#define mmDCORE0_EDMA0_QM_CP_CURRENT_INST_LO_1 0x41CA380
+
+#define mmDCORE0_EDMA0_QM_CP_CURRENT_INST_LO_2 0x41CA384
+
+#define mmDCORE0_EDMA0_QM_CP_CURRENT_INST_LO_3 0x41CA388
+
+#define mmDCORE0_EDMA0_QM_CP_CURRENT_INST_LO_4 0x41CA38C
+
+#define mmDCORE0_EDMA0_QM_CP_CURRENT_INST_HI_0 0x41CA390
+
+#define mmDCORE0_EDMA0_QM_CP_CURRENT_INST_HI_1 0x41CA394
+
+#define mmDCORE0_EDMA0_QM_CP_CURRENT_INST_HI_2 0x41CA398
+
+#define mmDCORE0_EDMA0_QM_CP_CURRENT_INST_HI_3 0x41CA39C
+
+#define mmDCORE0_EDMA0_QM_CP_CURRENT_INST_HI_4 0x41CA3A0
+
+#define mmDCORE0_EDMA0_QM_CP_PRED_0 0x41CA3A4
+
+#define mmDCORE0_EDMA0_QM_CP_PRED_1 0x41CA3A8
+
+#define mmDCORE0_EDMA0_QM_CP_PRED_2 0x41CA3AC
+
+#define mmDCORE0_EDMA0_QM_CP_PRED_3 0x41CA3B0
+
+#define mmDCORE0_EDMA0_QM_CP_PRED_4 0x41CA3B4
+
+#define mmDCORE0_EDMA0_QM_CP_PRED_UPEN_0 0x41CA3B8
+
+#define mmDCORE0_EDMA0_QM_CP_PRED_UPEN_1 0x41CA3BC
+
+#define mmDCORE0_EDMA0_QM_CP_PRED_UPEN_2 0x41CA3C0
+
+#define mmDCORE0_EDMA0_QM_CP_PRED_UPEN_3 0x41CA3C4
+
+#define mmDCORE0_EDMA0_QM_CP_PRED_UPEN_4 0x41CA3C8
+
+#define mmDCORE0_EDMA0_QM_CP_DBG_0_0 0x41CA3CC
+
+#define mmDCORE0_EDMA0_QM_CP_DBG_0_1 0x41CA3D0
+
+#define mmDCORE0_EDMA0_QM_CP_DBG_0_2 0x41CA3D4
+
+#define mmDCORE0_EDMA0_QM_CP_DBG_0_3 0x41CA3D8
+
+#define mmDCORE0_EDMA0_QM_CP_DBG_0_4 0x41CA3DC
+
+#define mmDCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_0 0x41CA3E0
+
+#define mmDCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_1 0x41CA3E4
+
+#define mmDCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_2 0x41CA3E8
+
+#define mmDCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_3 0x41CA3EC
+
+#define mmDCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_4 0x41CA3F0
+
+#define mmDCORE0_EDMA0_QM_CP_IN_DATA_LO_0 0x41CA3F4
+
+#define mmDCORE0_EDMA0_QM_CP_IN_DATA_LO_1 0x41CA3F8
+
+#define mmDCORE0_EDMA0_QM_CP_IN_DATA_LO_2 0x41CA3FC
+
+#define mmDCORE0_EDMA0_QM_CP_IN_DATA_LO_3 0x41CA400
+
+#define mmDCORE0_EDMA0_QM_CP_IN_DATA_LO_4 0x41CA404
+
+#define mmDCORE0_EDMA0_QM_CP_IN_DATA_HI_0 0x41CA408
+
+#define mmDCORE0_EDMA0_QM_CP_IN_DATA_HI_1 0x41CA40C
+
+#define mmDCORE0_EDMA0_QM_CP_IN_DATA_HI_2 0x41CA410
+
+#define mmDCORE0_EDMA0_QM_CP_IN_DATA_HI_3 0x41CA414
+
+#define mmDCORE0_EDMA0_QM_CP_IN_DATA_HI_4 0x41CA418
+
+#define mmDCORE0_EDMA0_QM_PQC_HBW_BASE_LO_0 0x41CA41C
+
+#define mmDCORE0_EDMA0_QM_PQC_HBW_BASE_LO_1 0x41CA420
+
+#define mmDCORE0_EDMA0_QM_PQC_HBW_BASE_LO_2 0x41CA424
+
+#define mmDCORE0_EDMA0_QM_PQC_HBW_BASE_LO_3 0x41CA428
+
+#define mmDCORE0_EDMA0_QM_PQC_HBW_BASE_HI_0 0x41CA42C
+
+#define mmDCORE0_EDMA0_QM_PQC_HBW_BASE_HI_1 0x41CA430
+
+#define mmDCORE0_EDMA0_QM_PQC_HBW_BASE_HI_2 0x41CA434
+
+#define mmDCORE0_EDMA0_QM_PQC_HBW_BASE_HI_3 0x41CA438
+
+#define mmDCORE0_EDMA0_QM_PQC_SIZE_0 0x41CA43C
+
+#define mmDCORE0_EDMA0_QM_PQC_SIZE_1 0x41CA440
+
+#define mmDCORE0_EDMA0_QM_PQC_SIZE_2 0x41CA444
+
+#define mmDCORE0_EDMA0_QM_PQC_SIZE_3 0x41CA448
+
+#define mmDCORE0_EDMA0_QM_PQC_PI_0 0x41CA44C
+
+#define mmDCORE0_EDMA0_QM_PQC_PI_1 0x41CA450
+
+#define mmDCORE0_EDMA0_QM_PQC_PI_2 0x41CA454
+
+#define mmDCORE0_EDMA0_QM_PQC_PI_3 0x41CA458
+
+#define mmDCORE0_EDMA0_QM_PQC_LBW_WDATA_0 0x41CA45C
+
+#define mmDCORE0_EDMA0_QM_PQC_LBW_WDATA_1 0x41CA460
+
+#define mmDCORE0_EDMA0_QM_PQC_LBW_WDATA_2 0x41CA464
+
+#define mmDCORE0_EDMA0_QM_PQC_LBW_WDATA_3 0x41CA468
+
+#define mmDCORE0_EDMA0_QM_PQC_LBW_BASE_LO_0 0x41CA46C
+
+#define mmDCORE0_EDMA0_QM_PQC_LBW_BASE_LO_1 0x41CA470
+
+#define mmDCORE0_EDMA0_QM_PQC_LBW_BASE_LO_2 0x41CA474
+
+#define mmDCORE0_EDMA0_QM_PQC_LBW_BASE_LO_3 0x41CA478
+
+#define mmDCORE0_EDMA0_QM_PQC_LBW_BASE_HI_0 0x41CA47C
+
+#define mmDCORE0_EDMA0_QM_PQC_LBW_BASE_HI_1 0x41CA480
+
+#define mmDCORE0_EDMA0_QM_PQC_LBW_BASE_HI_2 0x41CA484
+
+#define mmDCORE0_EDMA0_QM_PQC_LBW_BASE_HI_3 0x41CA488
+
+#define mmDCORE0_EDMA0_QM_PQC_CFG 0x41CA48C
+
+#define mmDCORE0_EDMA0_QM_PQC_SECURE_PUSH_IND 0x41CA490
+
+#define mmDCORE0_EDMA0_QM_ARB_MASK 0x41CA4A0
+
+#define mmDCORE0_EDMA0_QM_ARB_CFG_0 0x41CA4A4
+
+#define mmDCORE0_EDMA0_QM_ARB_CHOICE_Q_PUSH 0x41CA4A8
+
+#define mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_0 0x41CA4AC
+
+#define mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_1 0x41CA4B0
+
+#define mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_2 0x41CA4B4
+
+#define mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_3 0x41CA4B8
+
+#define mmDCORE0_EDMA0_QM_ARB_CFG_1 0x41CA4BC
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_0 0x41CA4C0
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_1 0x41CA4C4
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_2 0x41CA4C8
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_3 0x41CA4CC
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_4 0x41CA4D0
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_5 0x41CA4D4
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_6 0x41CA4D8
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_7 0x41CA4DC
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_8 0x41CA4E0
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_9 0x41CA4E4
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_10 0x41CA4E8
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_11 0x41CA4EC
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_12 0x41CA4F0
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_13 0x41CA4F4
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_14 0x41CA4F8
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_15 0x41CA4FC
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_16 0x41CA500
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_17 0x41CA504
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_18 0x41CA508
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_19 0x41CA50C
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_20 0x41CA510
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_21 0x41CA514
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_22 0x41CA518
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_23 0x41CA51C
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_24 0x41CA520
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_25 0x41CA524
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_26 0x41CA528
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_27 0x41CA52C
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_28 0x41CA530
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_29 0x41CA534
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_30 0x41CA538
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_31 0x41CA53C
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_32 0x41CA540
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_33 0x41CA544
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_34 0x41CA548
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_35 0x41CA54C
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_36 0x41CA550
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_37 0x41CA554
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_38 0x41CA558
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_39 0x41CA55C
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_40 0x41CA560
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_41 0x41CA564
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_42 0x41CA568
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_43 0x41CA56C
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_44 0x41CA570
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_45 0x41CA574
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_46 0x41CA578
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_47 0x41CA57C
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_48 0x41CA580
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_49 0x41CA584
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_50 0x41CA588
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_51 0x41CA58C
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_52 0x41CA590
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_53 0x41CA594
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_54 0x41CA598
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_55 0x41CA59C
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_56 0x41CA5A0
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_57 0x41CA5A4
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_58 0x41CA5A8
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_59 0x41CA5AC
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_60 0x41CA5B0
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_61 0x41CA5B4
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_62 0x41CA5B8
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_63 0x41CA5BC
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CRED_INC 0x41CA5E0
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_0 0x41CA5E4
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_1 0x41CA5E8
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_2 0x41CA5EC
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_3 0x41CA5F0
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_4 0x41CA5F4
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_5 0x41CA5F8
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_6 0x41CA5FC
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_7 0x41CA600
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_8 0x41CA604
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_9 0x41CA608
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_10 0x41CA60C
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_11 0x41CA610
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_12 0x41CA614
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_13 0x41CA618
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_14 0x41CA61C
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_15 0x41CA620
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_16 0x41CA624
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_17 0x41CA628
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_18 0x41CA62C
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_19 0x41CA630
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_20 0x41CA634
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_21 0x41CA638
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_22 0x41CA63C
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_23 0x41CA640
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_24 0x41CA644
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_25 0x41CA648
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_26 0x41CA64C
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_27 0x41CA650
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_28 0x41CA654
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_29 0x41CA658
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_30 0x41CA65C
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_31 0x41CA660
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_32 0x41CA664
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_33 0x41CA668
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_34 0x41CA66C
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_35 0x41CA670
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_36 0x41CA674
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_37 0x41CA678
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_38 0x41CA67C
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_39 0x41CA680
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_40 0x41CA684
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_41 0x41CA688
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_42 0x41CA68C
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_43 0x41CA690
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_44 0x41CA694
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_45 0x41CA698
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_46 0x41CA69C
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_47 0x41CA6A0
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_48 0x41CA6A4
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_49 0x41CA6A8
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_50 0x41CA6AC
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_51 0x41CA6B0
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_52 0x41CA6B4
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_53 0x41CA6B8
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_54 0x41CA6BC
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_55 0x41CA6C0
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_56 0x41CA6C4
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_57 0x41CA6C8
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_58 0x41CA6CC
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_59 0x41CA6D0
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_60 0x41CA6D4
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_61 0x41CA6D8
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_62 0x41CA6DC
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_63 0x41CA6E0
+
+#define mmDCORE0_EDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x41CA704
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_SLAVE_EN 0x41CA708
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_1 0x41CA70C
+
+#define mmDCORE0_EDMA0_QM_ARB_SLV_CHOICE_WDT 0x41CA710
+
+#define mmDCORE0_EDMA0_QM_ARB_SLV_ID 0x41CA714
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_QUIET_PER 0x41CA718
+
+#define mmDCORE0_EDMA0_QM_ARB_MSG_MAX_INFLIGHT 0x41CA744
+
+#define mmDCORE0_EDMA0_QM_ARB_BASE_LO 0x41CA754
+
+#define mmDCORE0_EDMA0_QM_ARB_BASE_HI 0x41CA758
+
+#define mmDCORE0_EDMA0_QM_ARB_STATE_STS 0x41CA780
+
+#define mmDCORE0_EDMA0_QM_ARB_CHOICE_FULLNESS_STS 0x41CA784
+
+#define mmDCORE0_EDMA0_QM_ARB_MSG_STS 0x41CA788
+
+#define mmDCORE0_EDMA0_QM_ARB_SLV_CHOICE_Q_HEAD 0x41CA78C
+
+#define mmDCORE0_EDMA0_QM_ARB_ERR_CAUSE 0x41CA79C
+
+#define mmDCORE0_EDMA0_QM_ARB_ERR_MSG_EN 0x41CA7A0
+
+#define mmDCORE0_EDMA0_QM_ARB_ERR_STS_DRP 0x41CA7A8
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CRED_STS 0x41CA7B0
+
+#define mmDCORE0_EDMA0_QM_ARB_MST_CRED_STS_1 0x41CA7B4
+
+#define mmDCORE0_EDMA0_QM_CSMR_STRICT_PRIO_CFG 0x41CA7FC
+
+#define mmDCORE0_EDMA0_QM_ARC_CQ_CFG0 0x41CA800
+
+#define mmDCORE0_EDMA0_QM_ARC_CQ_CFG1 0x41CA804
+
+#define mmDCORE0_EDMA0_QM_ARC_CQ_PTR_LO 0x41CA808
+
+#define mmDCORE0_EDMA0_QM_ARC_CQ_PTR_HI 0x41CA80C
+
+#define mmDCORE0_EDMA0_QM_ARC_CQ_TSIZE 0x41CA810
+
+#define mmDCORE0_EDMA0_QM_ARC_CQ_CTL 0x41CA814
+
+#define mmDCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS 0x41CA81C
+
+#define mmDCORE0_EDMA0_QM_ARC_CQ_STS0 0x41CA820
+
+#define mmDCORE0_EDMA0_QM_ARC_CQ_STS1 0x41CA824
+
+#define mmDCORE0_EDMA0_QM_ARC_CQ_TSIZE_STS 0x41CA828
+
+#define mmDCORE0_EDMA0_QM_ARC_CQ_PTR_LO_STS 0x41CA82C
+
+#define mmDCORE0_EDMA0_QM_ARC_CQ_PTR_HI_STS 0x41CA830
+
+#define mmDCORE0_EDMA0_QM_CP_WR_ARC_ADDR_HI 0x41CA834
+
+#define mmDCORE0_EDMA0_QM_CP_WR_ARC_ADDR_LO 0x41CA838
+
+#define mmDCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI 0x41CA83C
+
+#define mmDCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO 0x41CA840
+
+#define mmDCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI 0x41CA844
+
+#define mmDCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO 0x41CA848
+
+#define mmDCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_HI 0x41CA84C
+
+#define mmDCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_LO 0x41CA850
+
+#define mmDCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_HI 0x41CA854
+
+#define mmDCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_LO 0x41CA858
+
+#define mmDCORE0_EDMA0_QM_ADDR_OVRD 0x41CA85C
+
+#define mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_0 0x41CA860
+
+#define mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_1 0x41CA864
+
+#define mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_2 0x41CA868
+
+#define mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_3 0x41CA86C
+
+#define mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_4 0x41CA870
+
+#define mmDCORE0_EDMA0_QM_ARC_CQ_IFIFO_CI 0x41CA874
+
+#define mmDCORE0_EDMA0_QM_CQ_CTL_CI_0 0x41CA878
+
+#define mmDCORE0_EDMA0_QM_CQ_CTL_CI_1 0x41CA87C
+
+#define mmDCORE0_EDMA0_QM_CQ_CTL_CI_2 0x41CA880
+
+#define mmDCORE0_EDMA0_QM_CQ_CTL_CI_3 0x41CA884
+
+#define mmDCORE0_EDMA0_QM_CQ_CTL_CI_4 0x41CA888
+
+#define mmDCORE0_EDMA0_QM_ARC_CQ_CTL_CI 0x41CA88C
+
+#define mmDCORE0_EDMA0_QM_CP_CFG 0x41CA890
+
+#define mmDCORE0_EDMA0_QM_CP_EXT_SWITCH 0x41CA894
+
+#define mmDCORE0_EDMA0_QM_CP_SWITCH_WD_SET 0x41CA898
+
+#define mmDCORE0_EDMA0_QM_CP_SWITCH_WD 0x41CA89C
+
+#define mmDCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_LO 0x41CA8A4
+
+#define mmDCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_HI 0x41CA8A8
+
+#define mmDCORE0_EDMA0_QM_ENGINE_BASE_ADDR_HI 0x41CA8AC
+
+#define mmDCORE0_EDMA0_QM_ENGINE_BASE_ADDR_LO 0x41CA8B0
+
+#define mmDCORE0_EDMA0_QM_ENGINE_ADDR_RANGE_SIZE 0x41CA8B4
+
+#define mmDCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI 0x41CA8B8
+
+#define mmDCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO 0x41CA8BC
+
+#define mmDCORE0_EDMA0_QM_QM_BASE_ADDR_HI 0x41CA8C0
+
+#define mmDCORE0_EDMA0_QM_QM_BASE_ADDR_LO 0x41CA8C4
+
+#define mmDCORE0_EDMA0_QM_ARC_PQC_SECURE_PUSH_IND 0x41CA8C8
+
+#define mmDCORE0_EDMA0_QM_PQC_STS_0_0 0x41CA8D0
+
+#define mmDCORE0_EDMA0_QM_PQC_STS_0_1 0x41CA8D4
+
+#define mmDCORE0_EDMA0_QM_PQC_STS_0_2 0x41CA8D8
+
+#define mmDCORE0_EDMA0_QM_PQC_STS_0_3 0x41CA8DC
+
+#define mmDCORE0_EDMA0_QM_PQC_STS_1_0 0x41CA8E0
+
+#define mmDCORE0_EDMA0_QM_PQC_STS_1_1 0x41CA8E4
+
+#define mmDCORE0_EDMA0_QM_PQC_STS_1_2 0x41CA8E8
+
+#define mmDCORE0_EDMA0_QM_PQC_STS_1_3 0x41CA8EC
+
+#define mmDCORE0_EDMA0_QM_SEI_STATUS 0x41CA8F0
+
+#define mmDCORE0_EDMA0_QM_SEI_MASK 0x41CA8F4
+
+#define mmDCORE0_EDMA0_QM_GLBL_ERR_ADDR_LO 0x41CAD00
+
+#define mmDCORE0_EDMA0_QM_GLBL_ERR_ADDR_HI 0x41CAD04
+
+#define mmDCORE0_EDMA0_QM_GLBL_ERR_WDATA 0x41CAD08
+
+#define mmDCORE0_EDMA0_QM_L2H_MASK_LO 0x41CAD14
+
+#define mmDCORE0_EDMA0_QM_L2H_MASK_HI 0x41CAD18
+
+#define mmDCORE0_EDMA0_QM_L2H_CMPR_LO 0x41CAD1C
+
+#define mmDCORE0_EDMA0_QM_L2H_CMPR_HI 0x41CAD20
+
+#define mmDCORE0_EDMA0_QM_LOCAL_RANGE_BASE 0x41CAD24
+
+#define mmDCORE0_EDMA0_QM_LOCAL_RANGE_SIZE 0x41CAD28
+
+#define mmDCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_1 0x41CAD30
+
+#define mmDCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_0 0x41CAD34
+
+#define mmDCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_1 0x41CAD38
+
+#define mmDCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_0 0x41CAD3C
+
+#define mmDCORE0_EDMA0_QM_IND_GW_APB_CFG 0x41CAD40
+
+#define mmDCORE0_EDMA0_QM_IND_GW_APB_WDATA 0x41CAD44
+
+#define mmDCORE0_EDMA0_QM_IND_GW_APB_RDATA 0x41CAD48
+
+#define mmDCORE0_EDMA0_QM_IND_GW_APB_STATUS 0x41CAD4C
+
+#define mmDCORE0_EDMA0_QM_PERF_CNT_FREE_LO 0x41CAD60
+
+#define mmDCORE0_EDMA0_QM_PERF_CNT_FREE_HI 0x41CAD64
+
+#define mmDCORE0_EDMA0_QM_PERF_CNT_IDLE_LO 0x41CAD68
+
+#define mmDCORE0_EDMA0_QM_PERF_CNT_IDLE_HI 0x41CAD6C
+
+#define mmDCORE0_EDMA0_QM_PERF_CNT_CFG 0x41CAD70
+
+#endif /* ASIC_REG_DCORE0_EDMA0_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma1_core_ctx_axuser_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma1_core_ctx_axuser_regs.h
new file mode 100644
index 000000000000..b608a634562f
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma1_core_ctx_axuser_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_EDMA1_CORE_CTX_AXUSER_REGS_H_
+#define ASIC_REG_DCORE0_EDMA1_CORE_CTX_AXUSER_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_EDMA1_CORE_CTX_AXUSER
+ *   (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_ASID 0x41DB800
+
+#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_MMU_BP 0x41DB804
+
+#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_STRONG_ORDER 0x41DB808
+
+#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_NO_SNOOP 0x41DB80C
+
+#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_WR_REDUCTION 0x41DB810
+
+#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_RD_ATOMIC 0x41DB814
+
+#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_QOS 0x41DB818
+
+#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_RSVD 0x41DB81C
+
+#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_EMEM_CPAGE 0x41DB820
+
+#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_CORE 0x41DB824
+
+#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_E2E_COORD 0x41DB828
+
+#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_WR_OVRD_LO 0x41DB830
+
+#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_WR_OVRD_HI 0x41DB834
+
+#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_RD_OVRD_LO 0x41DB838
+
+#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_RD_OVRD_HI 0x41DB83C
+
+#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_LB_COORD 0x41DB840
+
+#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_LB_LOCK 0x41DB844
+
+#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_LB_RSVD 0x41DB848
+
+#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_LB_OVRD 0x41DB84C
+
+#endif /* ASIC_REG_DCORE0_EDMA1_CORE_CTX_AXUSER_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma1_qm_axuser_nonsecured_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma1_qm_axuser_nonsecured_regs.h
new file mode 100644
index 000000000000..c3a462f2a9ac
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma1_qm_axuser_nonsecured_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_EDMA1_QM_AXUSER_NONSECURED_REGS_H_
+#define ASIC_REG_DCORE0_EDMA1_QM_AXUSER_NONSECURED_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_EDMA1_QM_AXUSER_NONSECURED
+ *   (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_ASID 0x41DAB80
+
+#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_MMU_BP 0x41DAB84
+
+#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_STRONG_ORDER 0x41DAB88
+
+#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_NO_SNOOP 0x41DAB8C
+
+#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_WR_REDUCTION 0x41DAB90
+
+#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_RD_ATOMIC 0x41DAB94
+
+#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_QOS 0x41DAB98
+
+#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_RSVD 0x41DAB9C
+
+#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_EMEM_CPAGE 0x41DABA0
+
+#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_CORE 0x41DABA4
+
+#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_E2E_COORD 0x41DABA8
+
+#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_WR_OVRD_LO 0x41DABB0
+
+#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_WR_OVRD_HI 0x41DABB4
+
+#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_RD_OVRD_LO 0x41DABB8
+
+#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_RD_OVRD_HI 0x41DABBC
+
+#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_LB_COORD 0x41DABC0
+
+#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_LB_LOCK 0x41DABC4
+
+#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_LB_RSVD 0x41DABC8
+
+#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_LB_OVRD 0x41DABCC
+
+#endif /* ASIC_REG_DCORE0_EDMA1_QM_AXUSER_NONSECURED_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_mmu_masks.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_mmu_masks.h
new file mode 100644
index 000000000000..2965b6a3b423
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_mmu_masks.h
@@ -0,0 +1,289 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_HMMU0_MMU_MASKS_H_
+#define ASIC_REG_DCORE0_HMMU0_MMU_MASKS_H_
+
+/*
+ *****************************************
+ *   DCORE0_HMMU0_MMU
+ *   (Prototype: MMU)
+ *****************************************
+ */
+
+/* DCORE0_HMMU0_MMU_MMU_ENABLE */
+#define DCORE0_HMMU0_MMU_MMU_ENABLE_R_SHIFT 0
+#define DCORE0_HMMU0_MMU_MMU_ENABLE_R_MASK 0x1
+
+/* DCORE0_HMMU0_MMU_FORCE_ORDERING */
+#define DCORE0_HMMU0_MMU_FORCE_ORDERING_WEAK_ORDERING_SHIFT 0
+#define DCORE0_HMMU0_MMU_FORCE_ORDERING_WEAK_ORDERING_MASK 0x1
+#define DCORE0_HMMU0_MMU_FORCE_ORDERING_STRONG_ORDERING_SHIFT 1
+#define DCORE0_HMMU0_MMU_FORCE_ORDERING_STRONG_ORDERING_MASK 0x2
+
+/* DCORE0_HMMU0_MMU_FEATURE_ENABLE */
+#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_VA_ORDERING_EN_SHIFT 0
+#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_VA_ORDERING_EN_MASK 0x1
+#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_CLEAN_LINK_LIST_SHIFT 1
+#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_CLEAN_LINK_LIST_MASK 0x2
+#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_HOP_OFFSET_EN_SHIFT 2
+#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_HOP_OFFSET_EN_MASK 0x4
+#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_OBI_ORDERING_EN_SHIFT 3
+#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_OBI_ORDERING_EN_MASK 0x8
+#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_STRONG_ORDERING_READ_EN_SHIFT 4
+#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_STRONG_ORDERING_READ_EN_MASK 0x10
+#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_ENABLE_SHIFT 5
+#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_ENABLE_MASK 0x20
+#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_EV_MMU_OR_STLB_SHIFT 6
+#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_EV_MMU_OR_STLB_MASK 0x40
+#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_CLKH_EQUAL_CLKL_SHIFT 7
+#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_CLKH_EQUAL_CLKL_MASK 0x80
+
+/* DCORE0_HMMU0_MMU_VA_ORDERING_MASK_38_7 */
+#define DCORE0_HMMU0_MMU_VA_ORDERING_MASK_38_7_R_SHIFT 0
+#define DCORE0_HMMU0_MMU_VA_ORDERING_MASK_38_7_R_MASK 0xFFFFFFFF
+
+/* DCORE0_HMMU0_MMU_VA_ORDERING_MASK_64_39 */
+#define DCORE0_HMMU0_MMU_VA_ORDERING_MASK_64_39_R_SHIFT 0
+#define DCORE0_HMMU0_MMU_VA_ORDERING_MASK_64_39_R_MASK 0x3FFFFFF
+
+/* DCORE0_HMMU0_MMU_LOG2_DDR_SIZE */
+#define DCORE0_HMMU0_MMU_LOG2_DDR_SIZE_R_SHIFT 0
+#define DCORE0_HMMU0_MMU_LOG2_DDR_SIZE_R_MASK 0xFF
+
+/* DCORE0_HMMU0_MMU_SCRAMBLER */
+#define DCORE0_HMMU0_MMU_SCRAMBLER_ADDR_BIT_SHIFT 0
+#define DCORE0_HMMU0_MMU_SCRAMBLER_ADDR_BIT_MASK 0x3F
+#define DCORE0_HMMU0_MMU_SCRAMBLER_SINGLE_DDR_EN_SHIFT 6
+#define DCORE0_HMMU0_MMU_SCRAMBLER_SINGLE_DDR_EN_MASK 0x40
+#define DCORE0_HMMU0_MMU_SCRAMBLER_SINGLE_DDR_ID_SHIFT 7
+#define DCORE0_HMMU0_MMU_SCRAMBLER_SINGLE_DDR_ID_MASK 0x80
+#define DCORE0_HMMU0_MMU_SCRAMBLER_DDR_CH_LSB_BIT_LOCATION_SHIFT 8
+#define DCORE0_HMMU0_MMU_SCRAMBLER_DDR_CH_LSB_BIT_LOCATION_MASK 0x7F00
+
+/* DCORE0_HMMU0_MMU_MEM_INIT_BUSY */
+#define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_DATA_SHIFT 0
+#define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_DATA_MASK 0x3
+#define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_OBI0_SHIFT 2
+#define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_OBI0_MASK 0x4
+#define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_OBI1_SHIFT 3
+#define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_OBI1_MASK 0x8
+
+/* DCORE0_HMMU0_MMU_SPI_SEI_MASK */
+#define DCORE0_HMMU0_MMU_SPI_SEI_MASK_R_SHIFT 0
+#define DCORE0_HMMU0_MMU_SPI_SEI_MASK_R_MASK 0x7FFFF
+
+/* DCORE0_HMMU0_MMU_SPI_SEI_CAUSE */
+#define DCORE0_HMMU0_MMU_SPI_SEI_CAUSE_R_SHIFT 0
+#define DCORE0_HMMU0_MMU_SPI_SEI_CAUSE_R_MASK 0x7FFFF
+
+/* DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE */
+#define DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA_63_32_SHIFT 0
+#define DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA_63_32_MASK 0xFFFFFFFF
+
+/* DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA */
+#define DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA_VA_31_0_SHIFT 0
+#define DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA_VA_31_0_MASK 0xFFFFFFFF
+
+/* DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE */
+#define DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA_63_32_SHIFT 0
+#define DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA_63_32_MASK 0xFFFFFFFF
+
+/* DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA */
+#define DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA_VA_31_0_SHIFT 0
+#define DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA_VA_31_0_MASK 0xFFFFFFFF
+
+/* DCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID */
+#define DCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID_PAGE_ERR_VALID_ENTRY_SHIFT 0
+#define DCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID_PAGE_ERR_VALID_ENTRY_MASK 0x1
+#define DCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID_ACCESS_ERR_VALID_ENTRY_SHIFT 1
+#define DCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID_ACCESS_ERR_VALID_ENTRY_MASK 0x2
+
+/* DCORE0_HMMU0_MMU_INTERRUPT_CLR */
+#define DCORE0_HMMU0_MMU_INTERRUPT_CLR_R_SHIFT 0
+#define DCORE0_HMMU0_MMU_INTERRUPT_CLR_R_MASK 0xFFFFFFFF
+
+/* DCORE0_HMMU0_MMU_INTERRUPT_MASK */
+#define DCORE0_HMMU0_MMU_INTERRUPT_MASK_R_SHIFT 0
+#define DCORE0_HMMU0_MMU_INTERRUPT_MASK_R_MASK 0xFF
+
+/* DCORE0_HMMU0_MMU_DBG_MEM_WRAP_RM */
+#define DCORE0_HMMU0_MMU_DBG_MEM_WRAP_RM_R_SHIFT 0
+#define DCORE0_HMMU0_MMU_DBG_MEM_WRAP_RM_R_MASK 0x3FFFFFFF
+
+/* DCORE0_HMMU0_MMU_SPI_CAUSE_CLR */
+#define DCORE0_HMMU0_MMU_SPI_CAUSE_CLR_CLR_SHIFT 0
+#define DCORE0_HMMU0_MMU_SPI_CAUSE_CLR_CLR_MASK 0x1
+
+/* DCORE0_HMMU0_MMU_PIPE_CREDIT */
+#define DCORE0_HMMU0_MMU_PIPE_CREDIT_READ_CREDIT_SHIFT 0
+#define DCORE0_HMMU0_MMU_PIPE_CREDIT_READ_CREDIT_MASK 0xF
+#define DCORE0_HMMU0_MMU_PIPE_CREDIT_READ_FORCE_FULL_SHIFT 7
+#define DCORE0_HMMU0_MMU_PIPE_CREDIT_READ_FORCE_FULL_MASK 0x80
+#define DCORE0_HMMU0_MMU_PIPE_CREDIT_WRITE_CREDIT_SHIFT 8
+#define DCORE0_HMMU0_MMU_PIPE_CREDIT_WRITE_CREDIT_MASK 0xF00
+#define DCORE0_HMMU0_MMU_PIPE_CREDIT_WRITE_FORCE_FULL_SHIFT 15
+#define DCORE0_HMMU0_MMU_PIPE_CREDIT_WRITE_FORCE_FULL_MASK 0x8000
+
+/* DCORE0_HMMU0_MMU_MMU_BYPASS */
+#define DCORE0_HMMU0_MMU_MMU_BYPASS_R_SHIFT 0
+#define DCORE0_HMMU0_MMU_MMU_BYPASS_R_MASK 0x1
+
+/* DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE */
+#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP5_PAGE_SIZE_SHIFT 0
+#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP5_PAGE_SIZE_MASK 0xF
+#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP4_PAGE_SIZE_SHIFT 4
+#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP4_PAGE_SIZE_MASK 0xF0
+#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP3_PAGE_SIZE_SHIFT 8
+#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP3_PAGE_SIZE_MASK 0xF00
+#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP2_PAGE_SIZE_SHIFT 12
+#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP2_PAGE_SIZE_MASK 0xF000
+#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP1_PAGE_SIZE_SHIFT 16
+#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP1_PAGE_SIZE_MASK 0xF0000
+#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_CFG_8_BITS_HOP_MODE_EN_SHIFT 20
+#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_CFG_8_BITS_HOP_MODE_EN_MASK 0x100000
+
+/* DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG */
+#define DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG_CORE_SET_MASK_SHIFT 0
+#define DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG_CORE_SET_MASK_MASK 0x1FF
+#define DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG_CORE_SET_MIN_SHIFT 10
+#define DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG_CORE_SET_MIN_MASK 0x7FC00
+#define DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG_CORE_SET_MAX_SHIFT 20
+#define DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG_CORE_SET_MAX_MASK 0x1FF00000
+
+/* DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT */
+#define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_WRITE_CRED_SHIFT 0
+#define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_WRITE_CRED_MASK 0x1FF
+#define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_READ_CRED_SHIFT 9
+#define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_READ_CRED_MASK 0x3FE00
+#define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_TOTAL_SHIFT 18
+#define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_TOTAL_MASK 0x7FC0000
+#define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_FORCE_FULL_WRITE_SHIFT 27
+#define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_FORCE_FULL_WRITE_MASK 0x8000000
+#define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_FORCE_FULL_READ_SHIFT 28
+#define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_FORCE_FULL_READ_MASK 0x10000000
+#define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_FORCE_FULL_TOTAL_SHIFT 29
+#define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_FORCE_FULL_TOTAL_MASK 0x20000000
+
+/* DCORE0_HMMU0_MMU_TOTAL_SLICE_CREDIT */
+#define DCORE0_HMMU0_MMU_TOTAL_SLICE_CREDIT_TOTAL_SHIFT 18
+#define DCORE0_HMMU0_MMU_TOTAL_SLICE_CREDIT_TOTAL_MASK 0x7FC0000
+#define DCORE0_HMMU0_MMU_TOTAL_SLICE_CREDIT_FORCE_FULL_TOTAL_SHIFT 29
+#define DCORE0_HMMU0_MMU_TOTAL_SLICE_CREDIT_FORCE_FULL_TOTAL_MASK 0x20000000
+
+/* DCORE0_HMMU0_MMU_PAGE_FAULT_ID_LSB */
+#define DCORE0_HMMU0_MMU_PAGE_FAULT_ID_LSB_PAGE_FAULT_ID_31_0_SHIFT 0
+#define DCORE0_HMMU0_MMU_PAGE_FAULT_ID_LSB_PAGE_FAULT_ID_31_0_MASK 0xFFFFFFFF
+
+/* DCORE0_HMMU0_MMU_PAGE_FAULT_ID_MSB */
+#define DCORE0_HMMU0_MMU_PAGE_FAULT_ID_MSB_PAGE_FAULT_ID_42_32_SHIFT 0
+#define DCORE0_HMMU0_MMU_PAGE_FAULT_ID_MSB_PAGE_FAULT_ID_42_32_MASK 0x7FF
+
+/* DCORE0_HMMU0_MMU_PAGE_ACCESS_ID_LSB */
+#define DCORE0_HMMU0_MMU_PAGE_ACCESS_ID_LSB_PAGE_ACCESS_ID_31_0_SHIFT 0
+#define DCORE0_HMMU0_MMU_PAGE_ACCESS_ID_LSB_PAGE_ACCESS_ID_31_0_MASK 0xFFFFFFFF
+
+/* DCORE0_HMMU0_MMU_PAGE_ACCESS_ID_MSB */
+#define DCORE0_HMMU0_MMU_PAGE_ACCESS_ID_MSB_PAGE_ACCESS_ID_42_32_SHIFT 0
+#define DCORE0_HMMU0_MMU_PAGE_ACCESS_ID_MSB_PAGE_ACCESS_ID_42_32_MASK 0x7FF
+
+/* DCORE0_HMMU0_MMU_DDR_RANGE_REG_ENABLE */
+#define DCORE0_HMMU0_MMU_DDR_RANGE_REG_ENABLE_ENABLE_SHIFT 0
+#define DCORE0_HMMU0_MMU_DDR_RANGE_REG_ENABLE_ENABLE_MASK 0x1
+
+/* DCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32 */
+#define DCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_SEC_MIN_63_32_SHIFT 0
+#define DCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_SEC_MIN_63_32_MASK 0xFFFFFFFF
+
+/* DCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0 */
+#define DCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_SEC_MIN_31_0_SHIFT 0
+#define DCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_SEC_MIN_31_0_MASK 0xFFFFFFFF
+
+/* DCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32 */
+#define DCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_SEC_MAX_63_32_SHIFT 0
+#define DCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_SEC_MAX_63_32_MASK 0xFFFFFFFF
+
+/* DCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0 */
+#define DCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_SEC_MAX_31_0_SHIFT 0
+#define DCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_SEC_MAX_31_0_MASK 0xFFFFFFFF
+
+/* DCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32 */
+#define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_PRIV_MIN_63_32_SHIFT 0
+#define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_PRIV_MIN_63_32_MASK 0xFFFFFFFF
+
+/* DCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0 */
+#define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_PRIV_MIN_31_0_SHIFT 0
+#define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_PRIV_MIN_31_0_MASK 0xFFFFFFFF
+
+/* DCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32 */
+#define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_PRIV_MAX_63_32_SHIFT 0
+#define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_PRIV_MAX_63_32_MASK 0xFFFFFFFF
+
+/* DCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0 */
+#define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_PRIV_MAX_31_0_SHIFT 0
+#define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_PRIV_MAX_31_0_MASK 0xFFFFFFFF
+
+/* DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_63_32 */
+#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_63_32_ILLEGAL_ADDR_63_32_SHIFT 0
+#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_63_32_ILLEGAL_ADDR_63_32_MASK 0xFFFFFFFF
+
+/* DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_31_0 */
+#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_31_0_ILLEGAL_ADDR_31_0_SHIFT 0
+#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_31_0_ILLEGAL_ADDR_31_0_MASK 0xFFFFFFFF
+
+/* DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_63_32 */
+#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_63_32_ILLEGAL_ADDR_63_32_SHIFT 0
+#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_63_32_ILLEGAL_ADDR_63_32_MASK 0xFFFFFFFF
+
+/* DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_31_0 */
+#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_31_0_ILLEGAL_ADDR_31_0_SHIFT 0
+#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_31_0_ILLEGAL_ADDR_31_0_MASK 0xFFFFFFFF
+
+/* DCORE0_HMMU0_MMU_RAZWI_WRITE_VLD */
+#define DCORE0_HMMU0_MMU_RAZWI_WRITE_VLD_R_SHIFT 0
+#define DCORE0_HMMU0_MMU_RAZWI_WRITE_VLD_R_MASK 0x1
+
+/* DCORE0_HMMU0_MMU_RAZWI_WRITE_ID_31_0 */
+#define DCORE0_HMMU0_MMU_RAZWI_WRITE_ID_31_0_R_SHIFT 0
+#define DCORE0_HMMU0_MMU_RAZWI_WRITE_ID_31_0_R_MASK 0xFFFFFFFF
+
+/* DCORE0_HMMU0_MMU_RAZWI_WRITE_ID_42_32 */
+#define DCORE0_HMMU0_MMU_RAZWI_WRITE_ID_42_32_R_SHIFT 0
+#define DCORE0_HMMU0_MMU_RAZWI_WRITE_ID_42_32_R_MASK 0x7FF
+
+/* DCORE0_HMMU0_MMU_RAZWI_READ_VLD */
+#define DCORE0_HMMU0_MMU_RAZWI_READ_VLD_R_SHIFT 0
+#define DCORE0_HMMU0_MMU_RAZWI_READ_VLD_R_MASK 0x1
+
+/* DCORE0_HMMU0_MMU_RAZWI_READ_ID_31_0 */
+#define DCORE0_HMMU0_MMU_RAZWI_READ_ID_31_0_R_SHIFT 0
+#define DCORE0_HMMU0_MMU_RAZWI_READ_ID_31_0_R_MASK 0xFFFFFFFF
+
+/* DCORE0_HMMU0_MMU_RAZWI_READ_ID_42_32 */
+#define DCORE0_HMMU0_MMU_RAZWI_READ_ID_42_32_R_SHIFT 0
+#define DCORE0_HMMU0_MMU_RAZWI_READ_ID_42_32_R_MASK 0x7FF
+
+/* DCORE0_HMMU0_MMU_MMU_SRC_NUM */
+#define DCORE0_HMMU0_MMU_MMU_SRC_NUM_OVERRIDE_SRC_NUM_EN_SHIFT 0
+#define DCORE0_HMMU0_MMU_MMU_SRC_NUM_OVERRIDE_SRC_NUM_EN_MASK 0x1
+#define DCORE0_HMMU0_MMU_MMU_SRC_NUM_SRC_NUM_SHIFT 1
+#define DCORE0_HMMU0_MMU_MMU_SRC_NUM_SRC_NUM_MASK 0x1E
+
+/* DCORE0_HMMU0_MMU_RAZWI_ADDR_LSB */
+#define DCORE0_HMMU0_MMU_RAZWI_ADDR_LSB_ADDR_SHIFT 0
+#define DCORE0_HMMU0_MMU_RAZWI_ADDR_LSB_ADDR_MASK 0xFFFFFFFF
+
+/* DCORE0_HMMU0_MMU_RAZWI_ADDR_MSB */
+#define DCORE0_HMMU0_MMU_RAZWI_ADDR_MSB_ADDR_SHIFT 0
+#define DCORE0_HMMU0_MMU_RAZWI_ADDR_MSB_ADDR_MASK 0xFFFFFFFF
+
+#endif /* ASIC_REG_DCORE0_HMMU0_MMU_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_mmu_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_mmu_regs.h
new file mode 100644
index 000000000000..08ccd695ec89
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_mmu_regs.h
@@ -0,0 +1,237 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_HMMU0_MMU_REGS_H_
+#define ASIC_REG_DCORE0_HMMU0_MMU_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_HMMU0_MMU
+ *   (Prototype: MMU)
+ *****************************************
+ */
+
+#define mmDCORE0_HMMU0_MMU_MMU_ENABLE 0x408000C
+
+#define mmDCORE0_HMMU0_MMU_FORCE_ORDERING 0x4080010
+
+#define mmDCORE0_HMMU0_MMU_FEATURE_ENABLE 0x4080014
+
+#define mmDCORE0_HMMU0_MMU_VA_ORDERING_MASK_38_7 0x4080018
+
+#define mmDCORE0_HMMU0_MMU_VA_ORDERING_MASK_64_39 0x408001C
+
+#define mmDCORE0_HMMU0_MMU_LOG2_DDR_SIZE 0x4080020
+
+#define mmDCORE0_HMMU0_MMU_SCRAMBLER 0x4080024
+
+#define mmDCORE0_HMMU0_MMU_MEM_INIT_BUSY 0x4080028
+
+#define mmDCORE0_HMMU0_MMU_SPI_SEI_MASK 0x408002C
+
+#define mmDCORE0_HMMU0_MMU_SPI_SEI_CAUSE 0x4080030
+
+#define mmDCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE 0x4080034
+
+#define mmDCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA 0x4080038
+
+#define mmDCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE 0x408003C
+
+#define mmDCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA 0x4080040
+
+#define mmDCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID 0x4080044
+
+#define mmDCORE0_HMMU0_MMU_INTERRUPT_CLR 0x4080048
+
+#define mmDCORE0_HMMU0_MMU_INTERRUPT_MASK 0x408004C
+
+#define mmDCORE0_HMMU0_MMU_DBG_MEM_WRAP_RM 0x4080050
+
+#define mmDCORE0_HMMU0_MMU_SPI_CAUSE_CLR 0x4080054
+
+#define mmDCORE0_HMMU0_MMU_PIPE_CREDIT 0x4080058
+
+#define mmDCORE0_HMMU0_MMU_MMU_BYPASS 0x408006C
+
+#define mmDCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE 0x4080070
+
+#define mmDCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG 0x40800A0
+
+#define mmDCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT 0x40800D0
+
+#define mmDCORE0_HMMU0_MMU_TOTAL_SLICE_CREDIT 0x40800F4
+
+#define mmDCORE0_HMMU0_MMU_PAGE_FAULT_ID_LSB 0x40800F8
+
+#define mmDCORE0_HMMU0_MMU_PAGE_FAULT_ID_MSB 0x40800FC
+
+#define mmDCORE0_HMMU0_MMU_PAGE_ACCESS_ID_LSB 0x4080100
+
+#define mmDCORE0_HMMU0_MMU_PAGE_ACCESS_ID_MSB 0x4080104
+
+#define mmDCORE0_HMMU0_MMU_DDR_RANGE_REG_ENABLE 0x4080108
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_0 0x4080110
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_1 0x4080114
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_2 0x4080118
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_3 0x408011C
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_4 0x4080120
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_5 0x4080124
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_6 0x4080128
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_7 0x408012C
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_0 0x4080140
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_1 0x4080144
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_2 0x4080148
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_3 0x408014C
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_4 0x4080150
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_5 0x4080154
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_6 0x4080158
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_7 0x408015C
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_0 0x4080170
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_1 0x4080174
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_2 0x4080178
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_3 0x408017C
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_4 0x4080180
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_5 0x4080184
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_6 0x4080188
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_7 0x408018C
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_0 0x40801A0
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_1 0x40801A4
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_2 0x40801A8
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_3 0x40801AC
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_4 0x40801B0
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_5 0x40801B4
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_6 0x40801B8
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_7 0x40801BC
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_0 0x40801D0
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_1 0x40801D4
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_2 0x40801D8
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_3 0x40801DC
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_4 0x40801E0
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_5 0x40801E4
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_6 0x40801E8
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_7 0x40801EC
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_0 0x4080200
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_1 0x4080204
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_2 0x4080208
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_3 0x408020C
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_4 0x4080210
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_5 0x4080214
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_6 0x4080218
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_7 0x408021C
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_0 0x4080230
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_1 0x4080234
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_2 0x4080238
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_3 0x408023C
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_4 0x4080240
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_5 0x4080244
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_6 0x4080248
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_7 0x408024C
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_0 0x4080260
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_1 0x4080264
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_2 0x4080268
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_3 0x408026C
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_4 0x4080270
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_5 0x4080274
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_6 0x4080278
+
+#define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_7 0x408027C
+
+#define mmDCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_63_32 0x4080290
+
+#define mmDCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_31_0 0x4080294
+
+#define mmDCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_63_32 0x4080298
+
+#define mmDCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_31_0 0x408029C
+
+#define mmDCORE0_HMMU0_MMU_RAZWI_WRITE_VLD 0x4080300
+
+#define mmDCORE0_HMMU0_MMU_RAZWI_WRITE_ID_31_0 0x4080304
+
+#define mmDCORE0_HMMU0_MMU_RAZWI_WRITE_ID_42_32 0x4080308
+
+#define mmDCORE0_HMMU0_MMU_RAZWI_READ_VLD 0x408030C
+
+#define mmDCORE0_HMMU0_MMU_RAZWI_READ_ID_31_0 0x4080310
+
+#define mmDCORE0_HMMU0_MMU_RAZWI_READ_ID_42_32 0x4080314
+
+#define mmDCORE0_HMMU0_MMU_MMU_SRC_NUM 0x408031C
+
+#define mmDCORE0_HMMU0_MMU_RAZWI_ADDR_LSB 0x4080320
+
+#define mmDCORE0_HMMU0_MMU_RAZWI_ADDR_MSB 0x4080324
+
+#endif /* ASIC_REG_DCORE0_HMMU0_MMU_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_stlb_masks.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_stlb_masks.h
new file mode 100644
index 000000000000..a311778b21e7
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_stlb_masks.h
@@ -0,0 +1,333 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_HMMU0_STLB_MASKS_H_
+#define ASIC_REG_DCORE0_HMMU0_STLB_MASKS_H_
+
+/*
+ *****************************************
+ *   DCORE0_HMMU0_STLB
+ *   (Prototype: STLB)
+ *****************************************
+ */
+
+/* DCORE0_HMMU0_STLB_BUSY */
+#define DCORE0_HMMU0_STLB_BUSY_BUSY_SHIFT 0
+#define DCORE0_HMMU0_STLB_BUSY_BUSY_MASK 0xFFFFFFFF
+
+/* DCORE0_HMMU0_STLB_ASID */
+#define DCORE0_HMMU0_STLB_ASID_ASID_SHIFT 0
+#define DCORE0_HMMU0_STLB_ASID_ASID_MASK 0x3FF
+
+/* DCORE0_HMMU0_STLB_HOP0_PA43_12 */
+#define DCORE0_HMMU0_STLB_HOP0_PA43_12_HOP0_PA43_12_SHIFT 0
+#define DCORE0_HMMU0_STLB_HOP0_PA43_12_HOP0_PA43_12_MASK 0xFFFFFFFF
+
+/* DCORE0_HMMU0_STLB_HOP0_PA63_44 */
+#define DCORE0_HMMU0_STLB_HOP0_PA63_44_HOP0_PA63_44_SHIFT 0
+#define DCORE0_HMMU0_STLB_HOP0_PA63_44_HOP0_PA63_44_MASK 0xFFFFF
+
+/* DCORE0_HMMU0_STLB_CACHE_INV */
+#define DCORE0_HMMU0_STLB_CACHE_INV_PRODUCER_INDEX_SHIFT 0
+#define DCORE0_HMMU0_STLB_CACHE_INV_PRODUCER_INDEX_MASK 0xFF
+#define DCORE0_HMMU0_STLB_CACHE_INV_INDEX_MASK_SHIFT 8
+#define DCORE0_HMMU0_STLB_CACHE_INV_INDEX_MASK_MASK 0xFF00
+
+/* DCORE0_HMMU0_STLB_CACHE_INV_BASE_39_8 */
+#define DCORE0_HMMU0_STLB_CACHE_INV_BASE_39_8_PA_SHIFT 0
+#define DCORE0_HMMU0_STLB_CACHE_INV_BASE_39_8_PA_MASK 0xFFFFFFFF
+
+/* DCORE0_HMMU0_STLB_CACHE_INV_BASE_63_40 */
+#define DCORE0_HMMU0_STLB_CACHE_INV_BASE_63_40_PA_SHIFT 0
+#define DCORE0_HMMU0_STLB_CACHE_INV_BASE_63_40_PA_MASK 0xFFFFFF
+
+/* DCORE0_HMMU0_STLB_STLB_FEATURE_EN */
+#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_STLB_CTRL_MULTI_PAGE_SIZE_EN_SHIFT 0
+#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_STLB_CTRL_MULTI_PAGE_SIZE_EN_MASK 0x1
+#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_MULTI_PAGE_SIZE_EN_SHIFT 1
+#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_MULTI_PAGE_SIZE_EN_MASK 0x2
+#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_LOOKUP_EN_SHIFT 2
+#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_LOOKUP_EN_MASK 0x4
+#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_BYPASS_SHIFT 3
+#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_BYPASS_MASK 0x8
+#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_BANK_STOP_SHIFT 4
+#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_BANK_STOP_MASK 0x10
+#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_TRACE_EN_SHIFT 5
+#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_TRACE_EN_MASK 0x20
+#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_FOLLOWER_EN_SHIFT 6
+#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_FOLLOWER_EN_MASK 0x40
+#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_CACHING_EN_SHIFT 7
+#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_CACHING_EN_MASK 0x1F80
+#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_FOLLOWING_NUM_LIMIT_SHIFT 13
+#define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_FOLLOWING_NUM_LIMIT_MASK 0xE000
+
+/* DCORE0_HMMU0_STLB_STLB_AXI_CACHE */
+#define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_STLB_CTRL_ARCACHE_SHIFT 0
+#define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_STLB_CTRL_ARCACHE_MASK 0xF
+#define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_STLB_CTRL_AWCACHE_SHIFT 4
+#define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_STLB_CTRL_AWCACHE_MASK 0xF0
+#define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_INV_ARCACHE_SHIFT 8
+#define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_INV_ARCACHE_MASK 0xF00
+
+/* DCORE0_HMMU0_STLB_HOP_CONFIGURATION */
+#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_HOP_SHIFT 0
+#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_HOP_MASK 0x7
+#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_SMALL_P_SHIFT 4
+#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_SMALL_P_MASK 0x70
+#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_LARGE_P_SHIFT 8
+#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_LARGE_P_MASK 0x700
+#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LAST_HOP_SHIFT 12
+#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LAST_HOP_MASK 0x7000
+#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FOLLOWER_HOP_SHIFT 16
+#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FOLLOWER_HOP_MASK 0x70000
+#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_ONLY_LARGE_PAGE_SHIFT 20
+#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_ONLY_LARGE_PAGE_MASK 0x100000
+#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LARGE_PAGE_INDICATION_BIT_SHIFT 21
+#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LARGE_PAGE_INDICATION_BIT_MASK 0x7E00000
+
+/* DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_63_32 */
+#define DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_63_32_R_SHIFT 0
+#define DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_63_32_R_MASK 0xFFFFFFFF
+
+/* DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_31_0 */
+#define DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_31_0_R_SHIFT 0
+#define DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_31_0_R_MASK 0xFFFFFFFF
+
+/* DCORE0_HMMU0_STLB_INV_ALL_START */
+#define DCORE0_HMMU0_STLB_INV_ALL_START_R_SHIFT 0
+#define DCORE0_HMMU0_STLB_INV_ALL_START_R_MASK 0x1
+
+/* DCORE0_HMMU0_STLB_INV_ALL_SET */
+#define DCORE0_HMMU0_STLB_INV_ALL_SET_R_SHIFT 0
+#define DCORE0_HMMU0_STLB_INV_ALL_SET_R_MASK 0xFF
+
+/* DCORE0_HMMU0_STLB_INV_PS */
+#define DCORE0_HMMU0_STLB_INV_PS_R_SHIFT 0
+#define DCORE0_HMMU0_STLB_INV_PS_R_MASK 0x3
+
+/* DCORE0_HMMU0_STLB_INV_CONSUMER_INDEX */
+#define DCORE0_HMMU0_STLB_INV_CONSUMER_INDEX_R_SHIFT 0
+#define DCORE0_HMMU0_STLB_INV_CONSUMER_INDEX_R_MASK 0xFF
+
+/* DCORE0_HMMU0_STLB_INV_HIT_COUNT */
+#define DCORE0_HMMU0_STLB_INV_HIT_COUNT_R_SHIFT 0
+#define DCORE0_HMMU0_STLB_INV_HIT_COUNT_R_MASK 0x7FF
+
+/* DCORE0_HMMU0_STLB_INV_SET */
+#define DCORE0_HMMU0_STLB_INV_SET_R_SHIFT 0
+#define DCORE0_HMMU0_STLB_INV_SET_R_MASK 0xFF
+
+/* DCORE0_HMMU0_STLB_SRAM_INIT */
+#define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_TAG_SHIFT 0
+#define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_TAG_MASK 0x3
+#define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_SLICE_SHIFT 2
+#define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_SLICE_MASK 0xC
+#define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_DATA_SHIFT 4
+#define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_DATA_MASK 0x10
+
+/* DCORE0_HMMU0_STLB_MEM_CACHE_INVALIDATION */
+
+/* DCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS */
+#define DCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS_INVALIDATE_DONE_SHIFT 0
+#define DCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS_INVALIDATE_DONE_MASK 0x1
+#define DCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS_CACHE_IDLE_SHIFT 1
+#define DCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS_CACHE_IDLE_MASK 0x2
+
+/* DCORE0_HMMU0_STLB_MEM_CACHE_BASE_38_7 */
+#define DCORE0_HMMU0_STLB_MEM_CACHE_BASE_38_7_R_SHIFT 0
+#define DCORE0_HMMU0_STLB_MEM_CACHE_BASE_38_7_R_MASK 0xFFFFFFFF
+
+/* DCORE0_HMMU0_STLB_MEM_CACHE_BASE_63_39 */
+#define DCORE0_HMMU0_STLB_MEM_CACHE_BASE_63_39_R_SHIFT 0
+#define DCORE0_HMMU0_STLB_MEM_CACHE_BASE_63_39_R_MASK 0x1FFFFFF
+
+/* DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG */
+#define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_CACHE_HOP_EN_SHIFT 0
+#define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_CACHE_HOP_EN_MASK 0x3F
+#define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_CACHE_HOP_PREFETCH_EN_SHIFT 6
+#define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_CACHE_HOP_PREFETCH_EN_MASK 0xFC0
+#define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_BYPASS_EN_SHIFT 12
+#define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_BYPASS_EN_MASK 0x1000
+#define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_RELEASE_INVALIDATE_SHIFT 13
+#define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_RELEASE_INVALIDATE_MASK 0x2000
+
+/* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5 */
+#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MIN_SHIFT 0
+#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MIN_MASK 0x1FF
+#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MAX_SHIFT 9
+#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MAX_MASK 0x3FE00
+#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MASK_SHIFT 18
+#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MASK_MASK 0x7FC0000
+
+/* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4 */
+#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MIN_SHIFT 0
+#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MIN_MASK 0x1FF
+#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MAX_SHIFT 9
+#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MAX_MASK 0x3FE00
+#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MASK_SHIFT 18
+#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MASK_MASK 0x7FC0000
+
+/* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3 */
+#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MIN_SHIFT 0
+#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MIN_MASK 0x1FF
+#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MAX_SHIFT 9
+#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MAX_MASK 0x3FE00
+#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MASK_SHIFT 18
+#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MASK_MASK 0x7FC0000
+
+/* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2 */
+#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MIN_SHIFT 0
+#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MIN_MASK 0x1FF
+#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MAX_SHIFT 9
+#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MAX_MASK 0x3FE00
+#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MASK_SHIFT 18
+#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MASK_MASK 0x7FC0000
+
+/* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1 */
+#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MIN_SHIFT 0
+#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MIN_MASK 0x1FF
+#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MAX_SHIFT 9
+#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MAX_MASK 0x3FE00
+#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MASK_SHIFT 18
+#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MASK_MASK 0x7FC0000
+
+/* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0 */
+#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MIN_SHIFT 0
+#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MIN_MASK 0x1FF
+#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MAX_SHIFT 9
+#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MAX_MASK 0x3FE00
+#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MASK_SHIFT 18
+#define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MASK_MASK 0x7FC0000
+
+/* DCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_CLR */
+
+/* DCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_MASK */
+#define DCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_MASK_R_SHIFT 0
+#define DCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_MASK_R_MASK 0x1
+
+/* DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG */
+#define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_PLRU_EVICTION_SHIFT 0
+#define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_PLRU_EVICTION_MASK 0x1
+#define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_CACHE_STOP_SHIFT 1
+#define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_CACHE_STOP_MASK 0x2
+#define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_INV_WRITEBACK_SHIFT 2
+#define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_INV_WRITEBACK_MASK 0x4
+
+/* DCORE0_HMMU0_STLB_MEM_READ_ARPROT */
+#define DCORE0_HMMU0_STLB_MEM_READ_ARPROT_R_SHIFT 0
+#define DCORE0_HMMU0_STLB_MEM_READ_ARPROT_R_MASK 0x7
+
+/* DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION */
+#define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_RANGE_INVALIDATION_ENABLE_SHIFT 0
+#define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_RANGE_INVALIDATION_ENABLE_MASK 0x1
+#define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_EN_SHIFT 1
+#define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_EN_MASK 0x2
+#define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_SHIFT 2
+#define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_MASK 0xFFC
+
+/* DCORE0_HMMU0_STLB_RANGE_INV_START_LSB */
+#define DCORE0_HMMU0_STLB_RANGE_INV_START_LSB_INV_START_LSB_SHIFT 0
+#define DCORE0_HMMU0_STLB_RANGE_INV_START_LSB_INV_START_LSB_MASK 0xFFFFFFFF
+
+/* DCORE0_HMMU0_STLB_RANGE_INV_START_MSB */
+#define DCORE0_HMMU0_STLB_RANGE_INV_START_MSB_INV_START_MSB_SHIFT 0
+#define DCORE0_HMMU0_STLB_RANGE_INV_START_MSB_INV_START_MSB_MASK 0xFFFFF
+
+/* DCORE0_HMMU0_STLB_RANGE_INV_END_LSB */
+#define DCORE0_HMMU0_STLB_RANGE_INV_END_LSB_INV_END_LSB_SHIFT 0
+#define DCORE0_HMMU0_STLB_RANGE_INV_END_LSB_INV_END_LSB_MASK 0xFFFFFFFF
+
+/* DCORE0_HMMU0_STLB_RANGE_INV_END_MSB */
+#define DCORE0_HMMU0_STLB_RANGE_INV_END_MSB_INV_END_MSB_SHIFT 0
+#define DCORE0_HMMU0_STLB_RANGE_INV_END_MSB_INV_END_MSB_MASK 0xFFFFF
+
+/* DCORE0_HMMU0_STLB_ASID_SCRAMBLER_CTRL */
+#define DCORE0_HMMU0_STLB_ASID_SCRAMBLER_CTRL_SCRAMBLER_SCRAM_EN_SHIFT 0
+#define DCORE0_HMMU0_STLB_ASID_SCRAMBLER_CTRL_SCRAMBLER_SCRAM_EN_MASK 0x1
+
+/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_0 */
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_0_ASID_POLY_MATRIX_H3_SHIFT 0
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_0_ASID_POLY_MATRIX_H3_MASK 0x1FF
+
+/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_1 */
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_1_ASID_POLY_MATRIX_H3_SHIFT 0
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_1_ASID_POLY_MATRIX_H3_MASK 0x1FF
+
+/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_2 */
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_2_ASID_POLY_MATRIX_H3_SHIFT 0
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_2_ASID_POLY_MATRIX_H3_MASK 0x1FF
+
+/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_3 */
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_3_ASID_POLY_MATRIX_H3_SHIFT 0
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_3_ASID_POLY_MATRIX_H3_MASK 0x1FF
+
+/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_4 */
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_4_ASID_POLY_MATRIX_H3_SHIFT 0
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_4_ASID_POLY_MATRIX_H3_MASK 0x1FF
+
+/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_5 */
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_5_ASID_POLY_MATRIX_H3_SHIFT 0
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_5_ASID_POLY_MATRIX_H3_MASK 0x1FF
+
+/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_6 */
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_6_ASID_POLY_MATRIX_H3_SHIFT 0
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_6_ASID_POLY_MATRIX_H3_MASK 0x1FF
+
+/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_7 */
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_7_ASID_POLY_MATRIX_H3_SHIFT 0
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_7_ASID_POLY_MATRIX_H3_MASK 0x1FF
+
+/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_8 */
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_8_ASID_POLY_MATRIX_H3_SHIFT 0
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_8_ASID_POLY_MATRIX_H3_MASK 0x1FF
+
+/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_9 */
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_9_ASID_POLY_MATRIX_H3_SHIFT 0
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_9_ASID_POLY_MATRIX_H3_MASK 0x1FF
+
+/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_10 */
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_10_ASID_POLY_MATRIX_H3_SHIFT 0
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_10_ASID_POLY_MATRIX_H3_MASK 0x1FF
+
+/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_11 */
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_11_ASID_POLY_MATRIX_H3_SHIFT 0
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_11_ASID_POLY_MATRIX_H3_MASK 0x1FF
+
+/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_12 */
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_12_ASID_POLY_MATRIX_H3_SHIFT 0
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_12_ASID_POLY_MATRIX_H3_MASK 0x1FF
+
+/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_13 */
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_13_ASID_POLY_MATRIX_H3_SHIFT 0
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_13_ASID_POLY_MATRIX_H3_MASK 0x1FF
+
+/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_14 */
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_14_ASID_POLY_MATRIX_H3_SHIFT 0
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_14_ASID_POLY_MATRIX_H3_MASK 0x1FF
+
+/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_15 */
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_15_ASID_POLY_MATRIX_H3_SHIFT 0
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_15_ASID_POLY_MATRIX_H3_MASK 0x1FF
+
+/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_16 */
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_16_ASID_POLY_MATRIX_H3_SHIFT 0
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_16_ASID_POLY_MATRIX_H3_MASK 0x1FF
+
+/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_17 */
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_17_ASID_POLY_MATRIX_H3_SHIFT 0
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_17_ASID_POLY_MATRIX_H3_MASK 0x1FF
+
+/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_18 */
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_18_ASID_POLY_MATRIX_H3_SHIFT 0
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_18_ASID_POLY_MATRIX_H3_MASK 0x1FF
+
+#endif /* ASIC_REG_DCORE0_HMMU0_STLB_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_stlb_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_stlb_regs.h
new file mode 100644
index 000000000000..864a259f68e2
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_stlb_regs.h
@@ -0,0 +1,141 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_HMMU0_STLB_REGS_H_
+#define ASIC_REG_DCORE0_HMMU0_STLB_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_HMMU0_STLB
+ *   (Prototype: STLB)
+ *****************************************
+ */
+
+#define mmDCORE0_HMMU0_STLB_BUSY 0x4081000
+
+#define mmDCORE0_HMMU0_STLB_ASID 0x4081004
+
+#define mmDCORE0_HMMU0_STLB_HOP0_PA43_12 0x4081008
+
+#define mmDCORE0_HMMU0_STLB_HOP0_PA63_44 0x408100C
+
+#define mmDCORE0_HMMU0_STLB_CACHE_INV 0x4081010
+
+#define mmDCORE0_HMMU0_STLB_CACHE_INV_BASE_39_8 0x4081014
+
+#define mmDCORE0_HMMU0_STLB_CACHE_INV_BASE_63_40 0x4081018
+
+#define mmDCORE0_HMMU0_STLB_STLB_FEATURE_EN 0x408101C
+
+#define mmDCORE0_HMMU0_STLB_STLB_AXI_CACHE 0x4081020
+
+#define mmDCORE0_HMMU0_STLB_HOP_CONFIGURATION 0x4081024
+
+#define mmDCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_63_32 0x4081028
+
+#define mmDCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_31_0 0x408102C
+
+#define mmDCORE0_HMMU0_STLB_INV_ALL_START 0x4081034
+
+#define mmDCORE0_HMMU0_STLB_INV_ALL_SET 0x4081038
+
+#define mmDCORE0_HMMU0_STLB_INV_PS 0x408103C
+
+#define mmDCORE0_HMMU0_STLB_INV_CONSUMER_INDEX 0x4081040
+
+#define mmDCORE0_HMMU0_STLB_INV_HIT_COUNT 0x4081044
+
+#define mmDCORE0_HMMU0_STLB_INV_SET 0x4081048
+
+#define mmDCORE0_HMMU0_STLB_SRAM_INIT 0x408104C
+
+#define mmDCORE0_HMMU0_STLB_MEM_CACHE_INVALIDATION 0x4081050
+
+#define mmDCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS 0x4081054
+
+#define mmDCORE0_HMMU0_STLB_MEM_CACHE_BASE_38_7 0x4081058
+
+#define mmDCORE0_HMMU0_STLB_MEM_CACHE_BASE_63_39 0x408105C
+
+#define mmDCORE0_HMMU0_STLB_MEM_CACHE_CONFIG 0x4081060
+
+#define mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5 0x4081064
+
+#define mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4 0x4081068
+
+#define mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3 0x408106C
+
+#define mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2 0x4081070
+
+#define mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1 0x4081074
+
+#define mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0 0x4081078
+
+#define mmDCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_CLR 0x408107C
+
+#define mmDCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_MASK 0x4081080
+
+#define mmDCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG 0x4081084
+
+#define mmDCORE0_HMMU0_STLB_MEM_READ_ARPROT 0x4081088
+
+#define mmDCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION 0x408108C
+
+#define mmDCORE0_HMMU0_STLB_RANGE_INV_START_LSB 0x4081090
+
+#define mmDCORE0_HMMU0_STLB_RANGE_INV_START_MSB 0x4081094
+
+#define mmDCORE0_HMMU0_STLB_RANGE_INV_END_LSB 0x4081098
+
+#define mmDCORE0_HMMU0_STLB_RANGE_INV_END_MSB 0x408109C
+
+#define mmDCORE0_HMMU0_STLB_ASID_SCRAMBLER_CTRL 0x4081100
+
+#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_0 0x4081104
+
+#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_1 0x4081108
+
+#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_2 0x408110C
+
+#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_3 0x4081110
+
+#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_4 0x4081114
+
+#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_5 0x4081118
+
+#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_6 0x408111C
+
+#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_7 0x4081120
+
+#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_8 0x4081124
+
+#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_9 0x4081128
+
+#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_10 0x408112C
+
+#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_11 0x4081130
+
+#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_12 0x4081134
+
+#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_13 0x4081138
+
+#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_14 0x408113C
+
+#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_15 0x4081140
+
+#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_16 0x4081144
+
+#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_17 0x4081148
+
+#define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_18 0x408114C
+
+#endif /* ASIC_REG_DCORE0_HMMU0_STLB_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_acc_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_acc_regs.h
new file mode 100644
index 000000000000..07bed3ec740e
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_acc_regs.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_MME_ACC_REGS_H_
+#define ASIC_REG_DCORE0_MME_ACC_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_MME_ACC
+ *   (Prototype: ACC)
+ *****************************************
+ */
+
+#define mmDCORE0_MME_ACC_WBC0_AXI 0x40F8000
+
+#define mmDCORE0_MME_ACC_WBC1_AXI 0x40F8004
+
+#define mmDCORE0_MME_ACC_WBC0_RL 0x40F8008
+
+#define mmDCORE0_MME_ACC_WBC1_RL 0x40F800C
+
+#define mmDCORE0_MME_ACC_WBC_STALL 0x40F8010
+
+#define mmDCORE0_MME_ACC_AWCACHE 0x40F8014
+
+#define mmDCORE0_MME_ACC_AWPROT 0x40F8018
+
+#define mmDCORE0_MME_ACC_AP_LFSR_POLY 0x40F801C
+
+#define mmDCORE0_MME_ACC_AP_LFSR_SEED_WDATA 0x40F8020
+
+#define mmDCORE0_MME_ACC_AP_LFSR_SEED_SEL 0x40F8024
+
+#define mmDCORE0_MME_ACC_AP_LFSR_SEED_RDATA 0x40F8028
+
+#define mmDCORE0_MME_ACC_AP_LFSR_CLOSE_CGATE_DLY 0x40F802C
+
+#define mmDCORE0_MME_ACC_WBC_SRC_BP 0x40F8030
+
+#define mmDCORE0_MME_ACC_CLK_GATE_EN 0x40F8034
+
+#define mmDCORE0_MME_ACC_WBC_INFLIGHTS 0x40F8038
+
+#define mmDCORE0_MME_ACC_HBW_CLK_ENABLER_DIS 0x40F803C
+
+#define mmDCORE0_MME_ACC_E2E_CRDT_TOP0 0x40F8040
+
+#define mmDCORE0_MME_ACC_E2E_CRDT_TOP1 0x40F8044
+
+#define mmDCORE0_MME_ACC_INTR_CAUSE 0x40F8048
+
+#define mmDCORE0_MME_ACC_INTR_MASK 0x40F804C
+
+#define mmDCORE0_MME_ACC_INTR_CLEAR 0x40F8050
+
+#define mmDCORE0_MME_ACC_WR_AXI_AGG_COUT0 0x40F8054
+
+#define mmDCORE0_MME_ACC_WR_AXI_AGG_COUT1 0x40F8058
+
+#define mmDCORE0_MME_ACC_BIST 0x40F805C
+
+#define mmDCORE0_MME_ACC_WR_AXI_AGG_2P_BVALID 0x40F8060
+
+#endif /* ASIC_REG_DCORE0_MME_ACC_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_cout0_master_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_cout0_master_regs.h
new file mode 100644
index 000000000000..c9043979fd69
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_cout0_master_regs.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_REGS_H_
+#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER
+ *   (Prototype: MME_AGU_CORE)
+ *****************************************
+ */
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_0 0x40CB22C
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_1 0x40CB230
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_2 0x40CB234
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_3 0x40CB238
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_4 0x40CB23C
+
+#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_cout0_slave_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_cout0_slave_regs.h
new file mode 100644
index 000000000000..7d74aea4576f
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_cout0_slave_regs.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_REGS_H_
+#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE
+ *   (Prototype: MME_AGU_CORE)
+ *****************************************
+ */
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_0 0x40CB240
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_1 0x40CB244
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_2 0x40CB248
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_3 0x40CB24C
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_4 0x40CB250
+
+#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_cout1_master_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_cout1_master_regs.h
new file mode 100644
index 000000000000..f6f519eb5f6f
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_cout1_master_regs.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_REGS_H_
+#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER
+ *   (Prototype: MME_AGU_CORE)
+ *****************************************
+ */
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_0 0x40CB254
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_1 0x40CB258
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_2 0x40CB25C
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_3 0x40CB260
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_4 0x40CB264
+
+#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_cout1_slave_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_cout1_slave_regs.h
new file mode 100644
index 000000000000..0e0c056ade9b
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_cout1_slave_regs.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_REGS_H_
+#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE
+ *   (Prototype: MME_AGU_CORE)
+ *****************************************
+ */
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_0 0x40CB268
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_1 0x40CB26C
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_2 0x40CB270
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_3 0x40CB274
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_4 0x40CB278
+
+#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in0_master_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in0_master_regs.h
new file mode 100644
index 000000000000..34c6134a2f93
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in0_master_regs.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_REGS_H_
+#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER
+ *   (Prototype: MME_AGU_CORE)
+ *****************************************
+ */
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_0 0x40CB15C
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_1 0x40CB160
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_2 0x40CB164
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_3 0x40CB168
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_4 0x40CB16C
+
+#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in0_slave_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in0_slave_regs.h
new file mode 100644
index 000000000000..55065032f87c
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in0_slave_regs.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_REGS_H_
+#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE
+ *   (Prototype: MME_AGU_CORE)
+ *****************************************
+ */
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_0 0x40CB170
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_1 0x40CB174
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_2 0x40CB178
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_3 0x40CB17C
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_4 0x40CB180
+
+#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in1_master_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in1_master_regs.h
new file mode 100644
index 000000000000..6022b387eacf
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in1_master_regs.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_REGS_H_
+#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER
+ *   (Prototype: MME_AGU_CORE)
+ *****************************************
+ */
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_0 0x40CB184
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_1 0x40CB188
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_2 0x40CB18C
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_3 0x40CB190
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_4 0x40CB194
+
+#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in1_slave_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in1_slave_regs.h
new file mode 100644
index 000000000000..f9c9b01f0d1a
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in1_slave_regs.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_REGS_H_
+#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE
+ *   (Prototype: MME_AGU_CORE)
+ *****************************************
+ */
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_0 0x40CB198
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_1 0x40CB19C
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_2 0x40CB1A0
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_3 0x40CB1A4
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_4 0x40CB1A8
+
+#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in2_master_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in2_master_regs.h
new file mode 100644
index 000000000000..d96119b8c435
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in2_master_regs.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_REGS_H_
+#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER
+ *   (Prototype: MME_AGU_CORE)
+ *****************************************
+ */
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_0 0x40CB1AC
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_1 0x40CB1B0
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_2 0x40CB1B4
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_3 0x40CB1B8
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_4 0x40CB1BC
+
+#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in2_slave_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in2_slave_regs.h
new file mode 100644
index 000000000000..c80d6817efe1
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in2_slave_regs.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_REGS_H_
+#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE
+ *   (Prototype: MME_AGU_CORE)
+ *****************************************
+ */
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_0 0x40CB1C0
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_1 0x40CB1C4
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_2 0x40CB1C8
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_3 0x40CB1CC
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_4 0x40CB1D0
+
+#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in3_master_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in3_master_regs.h
new file mode 100644
index 000000000000..753b31dc1760
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in3_master_regs.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_REGS_H_
+#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER
+ *   (Prototype: MME_AGU_CORE)
+ *****************************************
+ */
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_0 0x40CB1D4
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_1 0x40CB1D8
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_2 0x40CB1DC
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_3 0x40CB1E0
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_4 0x40CB1E4
+
+#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in3_slave_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in3_slave_regs.h
new file mode 100644
index 000000000000..f68d043edcd9
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in3_slave_regs.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_REGS_H_
+#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE
+ *   (Prototype: MME_AGU_CORE)
+ *****************************************
+ */
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_0 0x40CB1E8
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_1 0x40CB1EC
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_2 0x40CB1F0
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_3 0x40CB1F4
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_4 0x40CB1F8
+
+#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in4_master_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in4_master_regs.h
new file mode 100644
index 000000000000..a6dce326bd74
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in4_master_regs.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_REGS_H_
+#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER
+ *   (Prototype: MME_AGU_CORE)
+ *****************************************
+ */
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_0 0x40CB1FC
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_1 0x40CB200
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_2 0x40CB204
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_3 0x40CB208
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_4 0x40CB20C
+
+#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in4_slave_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in4_slave_regs.h
new file mode 100644
index 000000000000..5ace0f43cc78
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in4_slave_regs.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_REGS_H_
+#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE
+ *   (Prototype: MME_AGU_CORE)
+ *****************************************
+ */
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_0 0x40CB210
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_1 0x40CB214
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_2 0x40CB218
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_3 0x40CB21C
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_4 0x40CB220
+
+#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_base_addr_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_base_addr_regs.h
new file mode 100644
index 000000000000..b375393dfdc0
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_base_addr_regs.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_REGS_H_
+#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_MME_CTRL_LO_ARCH_BASE_ADDR
+ *   (Prototype: MME_ADDRESS_DESCRIPTOR)
+ *****************************************
+ */
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT1_LOW 0x40CB008
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT1_HIGH 0x40CB00C
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT0_LOW 0x40CB010
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT0_HIGH 0x40CB014
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_A_LOW 0x40CB018
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_A_HIGH 0x40CB01C
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_B_LOW 0x40CB020
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_B_HIGH 0x40CB024
+
+#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_non_tensor_end_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_non_tensor_end_regs.h
new file mode 100644
index 000000000000..fb53feb0a1a6
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_non_tensor_end_regs.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_REGS_H_
+#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END
+ *   (Prototype: MME_NON_TENSOR_DESCRIPTOR)
+ *****************************************
+ */
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_KERNEL_SIZE_MINUS_1 0x40CB280
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_LOW 0x40CB284
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_HIGH 0x40CB288
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_OUTER_LOOP 0x40CB28C
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_NUM_ITERATIONS_MINUS_1 0x40CB290
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SB_REPEAT 0x40CB294
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_FP8_BIAS 0x40CB298
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_RATE_LIMITER 0x40CB29C
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_USER_DATA 0x40CB2A0
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PERF_EVT_IN 0x40CB2A4
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PERF_EVT_OUT 0x40CB2A8
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PCU 0x40CB2AC
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SLAVE_SYNC_OBJ0_ADDR 0x40CB2B0
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SLAVE_SYNC_OBJ1_ADDR 0x40CB2B4
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_POWER_LOOP 0x40CB2B8
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE0_MASTER 0x40CB2BC
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE1_MASTER 0x40CB2C0
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE2_MASTER 0x40CB2C4
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE3_MASTER 0x40CB2C8
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE0_SLAVE 0x40CB2CC
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE1_SLAVE 0x40CB2D0
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE2_SLAVE 0x40CB2D4
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE3_SLAVE 0x40CB2D8
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_WKL_ID 0x40CB2DC
+
+#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_non_tensor_start_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_non_tensor_start_regs.h
new file mode 100644
index 000000000000..d17c165faf8b
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_non_tensor_start_regs.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_REGS_H_
+#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START
+ *   (Prototype: MME_NON_TENSOR_DESCRIPTOR_START)
+ *****************************************
+ */
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BRAINS_LOW 0x40CB028
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BRAINS_HIGH 0x40CB02C
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_HEADER_LOW 0x40CB030
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_HEADER_HIGH 0x40CB034
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_EUS_MASTER 0x40CB038
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_EUS_SLAVE 0x40CB03C
+
+#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_tensor_a_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_tensor_a_regs.h
new file mode 100644
index 000000000000..7b77884e0024
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_tensor_a_regs.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_TENSOR_A_REGS_H_
+#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_TENSOR_A_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_MME_CTRL_LO_ARCH_TENSOR_A
+ *   (Prototype: MME_TENSOR)
+ *****************************************
+ */
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_0 0x40CB040
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_1 0x40CB044
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_2 0x40CB048
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_3 0x40CB04C
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_4 0x40CB050
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_0 0x40CB054
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_1 0x40CB058
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_2 0x40CB05C
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_3 0x40CB060
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_4 0x40CB064
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_0 0x40CB068
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_1 0x40CB06C
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_2 0x40CB070
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_3 0x40CB074
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_0 0x40CB078
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_1 0x40CB07C
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_2 0x40CB080
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_3 0x40CB084
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_0 0x40CB088
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_1 0x40CB08C
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_2 0x40CB090
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_3 0x40CB094
+
+#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_TENSOR_A_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_tensor_b_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_tensor_b_regs.h
new file mode 100644
index 000000000000..a2a2ba454d6d
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_tensor_b_regs.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_TENSOR_B_REGS_H_
+#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_TENSOR_B_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_MME_CTRL_LO_ARCH_TENSOR_B
+ *   (Prototype: MME_TENSOR)
+ *****************************************
+ */
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_0 0x40CB098
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_1 0x40CB09C
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_2 0x40CB0A0
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_3 0x40CB0A4
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_4 0x40CB0A8
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_0 0x40CB0AC
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_1 0x40CB0B0
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_2 0x40CB0B4
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_3 0x40CB0B8
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_4 0x40CB0BC
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_0 0x40CB0C0
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_1 0x40CB0C4
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_2 0x40CB0C8
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_3 0x40CB0CC
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_0 0x40CB0D0
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_1 0x40CB0D4
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_2 0x40CB0D8
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_3 0x40CB0DC
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_0 0x40CB0E0
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_1 0x40CB0E4
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_2 0x40CB0E8
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_3 0x40CB0EC
+
+#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_TENSOR_B_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_tensor_cout_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_tensor_cout_regs.h
new file mode 100644
index 000000000000..7ad7b197cf87
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_tensor_cout_regs.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_REGS_H_
+#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT
+ *   (Prototype: MME_TENSOR)
+ *****************************************
+ */
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_0 0x40CB0F0
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_1 0x40CB0F4
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_2 0x40CB0F8
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_3 0x40CB0FC
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_4 0x40CB100
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_0 0x40CB104
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_1 0x40CB108
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_2 0x40CB10C
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_3 0x40CB110
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_4 0x40CB114
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_0 0x40CB118
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_1 0x40CB11C
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_2 0x40CB120
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_3 0x40CB124
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_0 0x40CB128
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_1 0x40CB12C
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_2 0x40CB130
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_3 0x40CB134
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_0 0x40CB138
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_1 0x40CB13C
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_2 0x40CB140
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_3 0x40CB144
+
+#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_masks.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_masks.h
new file mode 100644
index 000000000000..da0c94075e64
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_masks.h
@@ -0,0 +1,465 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_MASKS_H_
+#define ASIC_REG_DCORE0_MME_CTRL_LO_MASKS_H_
+
+/*
+ *****************************************
+ *   DCORE0_MME_CTRL_LO
+ *   (Prototype: MME_CTRL_LO)
+ *****************************************
+ */
+
+/* DCORE0_MME_CTRL_LO_ARCH_STATUS */
+#define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_IN_SHIFT 0
+#define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_IN_MASK 0x1F
+#define DCORE0_MME_CTRL_LO_ARCH_STATUS_EU_SHIFT 5
+#define DCORE0_MME_CTRL_LO_ARCH_STATUS_EU_MASK 0x20
+#define DCORE0_MME_CTRL_LO_ARCH_STATUS_AP_SHIFT 6
+#define DCORE0_MME_CTRL_LO_ARCH_STATUS_AP_MASK 0x40
+#define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_SHIFT 7
+#define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_MASK 0x180
+#define DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_EMPTY_SHIFT 9
+#define DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_EMPTY_MASK 0x3E00
+#define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_SM_IDLE_SHIFT 14
+#define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_SM_IDLE_MASK 0xC000
+#define DCORE0_MME_CTRL_LO_ARCH_STATUS_WBC_AXI_IDLE_SHIFT 16
+#define DCORE0_MME_CTRL_LO_ARCH_STATUS_WBC_AXI_IDLE_MASK 0x30000
+#define DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_AXI_IDLE_SHIFT 18
+#define DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_AXI_IDLE_MASK 0x7C0000
+#define DCORE0_MME_CTRL_LO_ARCH_STATUS_ACCUM_FREE_SHIFT 23
+#define DCORE0_MME_CTRL_LO_ARCH_STATUS_ACCUM_FREE_MASK 0x3800000
+#define DCORE0_MME_CTRL_LO_ARCH_STATUS_QM_IDLE_SHIFT 30
+#define DCORE0_MME_CTRL_LO_ARCH_STATUS_QM_IDLE_MASK 0x40000000
+#define DCORE0_MME_CTRL_LO_ARCH_STATUS_QM_RDY_SHIFT 31
+#define DCORE0_MME_CTRL_LO_ARCH_STATUS_QM_RDY_MASK 0x80000000
+
+/* DCORE0_MME_CTRL_LO_CMD */
+#define DCORE0_MME_CTRL_LO_CMD_AGU_IN_SHIFT 0
+#define DCORE0_MME_CTRL_LO_CMD_AGU_IN_MASK 0x1F
+#define DCORE0_MME_CTRL_LO_CMD_EU_SHIFT 5
+#define DCORE0_MME_CTRL_LO_CMD_EU_MASK 0x20
+#define DCORE0_MME_CTRL_LO_CMD_AP_SHIFT 6
+#define DCORE0_MME_CTRL_LO_CMD_AP_MASK 0x40
+#define DCORE0_MME_CTRL_LO_CMD_AGU_COUT_SHIFT 7
+#define DCORE0_MME_CTRL_LO_CMD_AGU_COUT_MASK 0x180
+#define DCORE0_MME_CTRL_LO_CMD_COPY_AND_INC_SHIFT 9
+#define DCORE0_MME_CTRL_LO_CMD_COPY_AND_INC_MASK 0x200
+#define DCORE0_MME_CTRL_LO_CMD_DESC_SEL_SHIFT 10
+#define DCORE0_MME_CTRL_LO_CMD_DESC_SEL_MASK 0xC00
+#define DCORE0_MME_CTRL_LO_CMD_MASK_IDLE_IND_SHIFT 12
+#define DCORE0_MME_CTRL_LO_CMD_MASK_IDLE_IND_MASK 0x1000
+#define DCORE0_MME_CTRL_LO_CMD_AGU_OUT1_FROM_AGU0_DW0_SHIFT 13
+#define DCORE0_MME_CTRL_LO_CMD_AGU_OUT1_FROM_AGU0_DW0_MASK 0x2000
+#define DCORE0_MME_CTRL_LO_CMD_AGU_OUT1_FROM_AGU0_DW1_4_SHIFT 14
+#define DCORE0_MME_CTRL_LO_CMD_AGU_OUT1_FROM_AGU0_DW1_4_MASK 0x4000
+#define DCORE0_MME_CTRL_LO_CMD_NULL_DESC_SHIFT 15
+#define DCORE0_MME_CTRL_LO_CMD_NULL_DESC_MASK 0x8000
+
+/* DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0 */
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_MASK0_SHIFT 0
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_MASK0_MASK 0x3F
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_EN0_SHIFT 6
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_EN0_MASK 0x40
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_MASK1_SHIFT 8
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_MASK1_MASK 0x3F00
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_EN1_SHIFT 14
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_EN1_MASK 0x4000
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_MASTER_WAIT_SLAVE_FENCE_SHIFT 15
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_MASTER_WAIT_SLAVE_FENCE_MASK 0x8000
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE_SEND_FENCE2MASTER_SHIFT 16
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE_SEND_FENCE2MASTER_MASK 0x10000
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE_SIGNAL_EN_SHIFT 17
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE_SIGNAL_EN_MASK 0x20000
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE0_USE_SLV_ADR_SHIFT 18
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE0_USE_SLV_ADR_MASK 0x40000
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE1_USE_SLV_ADR_SHIFT 19
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE1_USE_SLV_ADR_MASK 0x80000
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE0_USE_MSTR_ADR_PLUS4_SHIFT 20
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE0_USE_MSTR_ADR_PLUS4_MASK 0x100000
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE1_USE_MSTR_ADR_PLUS4_SHIFT 21
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE1_USE_MSTR_ADR_PLUS4_MASK 0x200000
+
+/* DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0 */
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0_V_SHIFT 0
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0_V_MASK 0xFFFFFFFF
+
+/* DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0 */
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_VALUE_SHIFT 0
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_VALUE_MASK 0x7FFF
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_RESERVED_SHIFT 15
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_RESERVED_MASK 0x3FFF8000
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_PERF_EN_SHIFT 30
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_PERF_EN_MASK 0x40000000
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_OP_SHIFT 31
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_OP_MASK 0x80000000
+
+/* DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1 */
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1_V_SHIFT 0
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1_V_MASK 0xFFFFFFFF
+
+/* DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1 */
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_VALUE_SHIFT 0
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_VALUE_MASK 0x7FFF
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_RESERVED_SHIFT 15
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_RESERVED_MASK 0x3FFF8000
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_PERF_EN_SHIFT 30
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_PERF_EN_MASK 0x40000000
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_OP_SHIFT 31
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_OP_MASK 0x80000000
+
+/* DCORE0_MME_CTRL_LO_ARCH_A_SS */
+#define DCORE0_MME_CTRL_LO_ARCH_A_SS_MINUS_1_SHIFT 0
+#define DCORE0_MME_CTRL_LO_ARCH_A_SS_MINUS_1_MASK 0xFFFFFFFF
+
+/* DCORE0_MME_CTRL_LO_ARCH_B_SS */
+#define DCORE0_MME_CTRL_LO_ARCH_B_SS_MINUS_1_SHIFT 0
+#define DCORE0_MME_CTRL_LO_ARCH_B_SS_MINUS_1_MASK 0xFFFFFFFF
+
+/* DCORE0_MME_CTRL_LO_ARCH_COUT_SS */
+#define DCORE0_MME_CTRL_LO_ARCH_COUT_SS_MINUS_1_SHIFT 0
+#define DCORE0_MME_CTRL_LO_ARCH_COUT_SS_MINUS_1_MASK 0xFFFFFFFF
+
+/* DCORE0_MME_CTRL_LO_QM_STALL */
+#define DCORE0_MME_CTRL_LO_QM_STALL_V_SHIFT 0
+#define DCORE0_MME_CTRL_LO_QM_STALL_V_MASK 0x1
+
+/* DCORE0_MME_CTRL_LO_LOG_SHADOW_LO */
+#define DCORE0_MME_CTRL_LO_LOG_SHADOW_LO_MASK_0_SHIFT 0
+#define DCORE0_MME_CTRL_LO_LOG_SHADOW_LO_MASK_0_MASK 0x1FF
+#define DCORE0_MME_CTRL_LO_LOG_SHADOW_LO_MASK_1_SHIFT 9
+#define DCORE0_MME_CTRL_LO_LOG_SHADOW_LO_MASK_1_MASK 0x3FE00
+
+/* DCORE0_MME_CTRL_LO_LOG_SHADOW_HI */
+#define DCORE0_MME_CTRL_LO_LOG_SHADOW_HI_MASK_2_SHIFT 0
+#define DCORE0_MME_CTRL_LO_LOG_SHADOW_HI_MASK_2_MASK 0x1FF
+#define DCORE0_MME_CTRL_LO_LOG_SHADOW_HI_MASK_3_SHIFT 9
+#define DCORE0_MME_CTRL_LO_LOG_SHADOW_HI_MASK_3_MASK 0x3FE00
+
+/* DCORE0_MME_CTRL_LO_SYNC_OBJECT_FIFO_TH */
+#define DCORE0_MME_CTRL_LO_SYNC_OBJECT_FIFO_TH_V_SHIFT 0
+#define DCORE0_MME_CTRL_LO_SYNC_OBJECT_FIFO_TH_V_MASK 0x1F
+
+/* DCORE0_MME_CTRL_LO_REDUN */
+#define DCORE0_MME_CTRL_LO_REDUN_FMA_SHIFT 0
+#define DCORE0_MME_CTRL_LO_REDUN_FMA_MASK 0x3F
+
+/* DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH */
+#define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO0_SHIFT 0
+#define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO0_MASK 0x1F
+#define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO1_SHIFT 5
+#define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO1_MASK 0x3E0
+#define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO2_SHIFT 10
+#define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO2_MASK 0x7C00
+
+/* DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0 */
+#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_SHIFT 0
+#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_MASK 0xFF
+#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE0_SHIFT 8
+#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE0_MASK 0x1F00
+#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE1_SHIFT 13
+#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE1_MASK 0x3E000
+#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE2_SHIFT 18
+#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE2_MASK 0x7C0000
+#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE3_SHIFT 23
+#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE3_MASK 0xF800000
+
+/* DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1 */
+#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1_FP_PE4_SHIFT 0
+#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1_FP_PE4_MASK 0x1F
+#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1_FP_PE_HI_SHIFT 5
+#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1_FP_PE_HI_MASK 0x3E0
+
+/* DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16 */
+#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16_DLY_SHIFT 0
+#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16_DLY_MASK 0xFFF
+#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16_EN_SHIFT 31
+#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16_EN_MASK 0x80000000
+
+/* DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8 */
+#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8_DLY_SHIFT 0
+#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8_DLY_MASK 0xFFF
+#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8_EN_SHIFT 31
+#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8_EN_MASK 0x80000000
+
+/* DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32 */
+#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32_DLY_SHIFT 0
+#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32_DLY_MASK 0xFFF
+#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32_EN_SHIFT 31
+#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32_EN_MASK 0x80000000
+
+/* DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I */
+#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I_DLY_SHIFT 0
+#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I_DLY_MASK 0xFFF
+#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I_EN_SHIFT 31
+#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I_EN_MASK 0x80000000
+
+/* DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32 */
+#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32_DLY_SHIFT 0
+#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32_DLY_MASK 0xFFF
+#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32_EN_SHIFT 31
+#define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32_EN_MASK 0x80000000
+
+/* DCORE0_MME_CTRL_LO_PCU_RL_DESC0 */
+#define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_RST_TOKEN_SHIFT 0
+#define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_RST_TOKEN_MASK 0xFFFF
+#define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_TIMEOUT_SHIFT 16
+#define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_TIMEOUT_MASK 0xFF0000
+#define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_DUMMY2REAL_PERIOD_SHIFT 24
+#define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_DUMMY2REAL_PERIOD_MASK 0xFF000000
+
+/* DCORE0_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE */
+#define DCORE0_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE_INC_VAL_SHIFT 0
+#define DCORE0_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE_INC_VAL_MASK 0xFFFF
+#define DCORE0_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE_DEC_VAL_SHIFT 16
+#define DCORE0_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE_DEC_VAL_MASK 0xFFFF0000
+
+/* DCORE0_MME_CTRL_LO_PCU_RL_TH */
+#define DCORE0_MME_CTRL_LO_PCU_RL_TH_POOL_TH_DEC_SHIFT 0
+#define DCORE0_MME_CTRL_LO_PCU_RL_TH_POOL_TH_DEC_MASK 0xFFFF
+#define DCORE0_MME_CTRL_LO_PCU_RL_TH_DUMMY_REAL_DIFF_TH_SHIFT 16
+#define DCORE0_MME_CTRL_LO_PCU_RL_TH_DUMMY_REAL_DIFF_TH_MASK 0xFFFF0000
+
+/* DCORE0_MME_CTRL_LO_PCU_RL_MIN */
+#define DCORE0_MME_CTRL_LO_PCU_RL_MIN_AVG_MIN_TO_FORCE_DUMMY_SHIFT 0
+#define DCORE0_MME_CTRL_LO_PCU_RL_MIN_AVG_MIN_TO_FORCE_DUMMY_MASK 0xFFFF
+#define DCORE0_MME_CTRL_LO_PCU_RL_MIN_TOKEN_MIN_VAL_SHIFT 16
+#define DCORE0_MME_CTRL_LO_PCU_RL_MIN_TOKEN_MIN_VAL_MASK 0xFFFF0000
+
+/* DCORE0_MME_CTRL_LO_PCU_RL_CTRL_EN */
+#define DCORE0_MME_CTRL_LO_PCU_RL_CTRL_EN_PCU_DISABLE_SHIFT 0
+#define DCORE0_MME_CTRL_LO_PCU_RL_CTRL_EN_PCU_DISABLE_MASK 0x1
+#define DCORE0_MME_CTRL_LO_PCU_RL_CTRL_EN_MIN_VAL_PROT_EN_SHIFT 1
+#define DCORE0_MME_CTRL_LO_PCU_RL_CTRL_EN_MIN_VAL_PROT_EN_MASK 0x2
+
+/* DCORE0_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE */
+#define DCORE0_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE_ALL_MACS_SHIFT 0
+#define DCORE0_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE_ALL_MACS_MASK 0x7
+#define DCORE0_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE_REAL_MACS_SHIFT 3
+#define DCORE0_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE_REAL_MACS_MASK 0x18
+
+/* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_BF16 */
+#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_BF16_ODD_SHIFT 0
+#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_BF16_ODD_MASK 0xFFFF
+#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_BF16_EVEN_SHIFT 16
+#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_BF16_EVEN_MASK 0xFFFF0000
+
+/* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_BF16 */
+#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_BF16_ODD_SHIFT 0
+#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_BF16_ODD_MASK 0xFFFF
+#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_BF16_EVEN_SHIFT 16
+#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_BF16_EVEN_MASK 0xFFFF0000
+
+/* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP16 */
+#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP16_ODD_SHIFT 0
+#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP16_ODD_MASK 0xFFFF
+#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP16_EVEN_SHIFT 16
+#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP16_EVEN_MASK 0xFFFF0000
+
+/* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP16 */
+#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP16_ODD_SHIFT 0
+#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP16_ODD_MASK 0xFFFF
+#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP16_EVEN_SHIFT 16
+#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP16_EVEN_MASK 0xFFFF0000
+
+/* DCORE0_MME_CTRL_LO_PCU_DUMMY_F8 */
+#define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_A_VAL_ODD_SHIFT 0
+#define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_A_VAL_ODD_MASK 0xFF
+#define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_A_VAL_EVEN_SHIFT 8
+#define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_A_VAL_EVEN_MASK 0xFF00
+#define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_B_VAL_ODD_SHIFT 16
+#define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_B_VAL_ODD_MASK 0xFF0000
+#define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_B_VAL_EVEN_SHIFT 24
+#define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_B_VAL_EVEN_MASK 0xFF000000
+
+/* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_ODD */
+#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_ODD_V_SHIFT 0
+#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_ODD_V_MASK 0xFFFFFFFF
+
+/* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_EVEN */
+#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_EVEN_V_SHIFT 0
+#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_EVEN_V_MASK 0xFFFFFFFF
+
+/* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_ODD */
+#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_ODD_V_SHIFT 0
+#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_ODD_V_MASK 0xFFFFFFFF
+
+/* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_EVEN */
+#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_EVEN_V_SHIFT 0
+#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_EVEN_V_MASK 0xFFFFFFFF
+
+/* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_ODD */
+#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_ODD_V_SHIFT 0
+#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_ODD_V_MASK 0xFFFFFFFF
+
+/* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_EVEN */
+#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_EVEN_V_SHIFT 0
+#define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_EVEN_V_MASK 0xFFFFFFFF
+
+/* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_ODD */
+#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_ODD_V_SHIFT 0
+#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_ODD_V_MASK 0xFFFFFFFF
+
+/* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_EVEN */
+#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_EVEN_V_SHIFT 0
+#define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_EVEN_V_MASK 0xFFFFFFFF
+
+/* DCORE0_MME_CTRL_LO_PROT */
+#define DCORE0_MME_CTRL_LO_PROT_VALUE_SHIFT 0
+#define DCORE0_MME_CTRL_LO_PROT_VALUE_MASK 0x7
+
+/* DCORE0_MME_CTRL_LO_EU */
+#define DCORE0_MME_CTRL_LO_EU_POWER_SAVE_DISABLE_SHIFT 0
+#define DCORE0_MME_CTRL_LO_EU_POWER_SAVE_DISABLE_MASK 0x1
+#define DCORE0_MME_CTRL_LO_EU_FP_PYR_CLOSE_CGATE_EN_SHIFT 1
+#define DCORE0_MME_CTRL_LO_EU_FP_PYR_CLOSE_CGATE_EN_MASK 0x2
+#define DCORE0_MME_CTRL_LO_EU_FP_CLS_CLOSE_CGATE_EN_SHIFT 2
+#define DCORE0_MME_CTRL_LO_EU_FP_CLS_CLOSE_CGATE_EN_MASK 0x4
+#define DCORE0_MME_CTRL_LO_EU_FP_CLOSE_CGATE_DLY_SHIFT 8
+#define DCORE0_MME_CTRL_LO_EU_FP_CLOSE_CGATE_DLY_MASK 0xFFF00
+#define DCORE0_MME_CTRL_LO_EU_FP_CLOSE_CGATE_ON_DESC_SHIFT 20
+#define DCORE0_MME_CTRL_LO_EU_FP_CLOSE_CGATE_ON_DESC_MASK 0x100000
+#define DCORE0_MME_CTRL_LO_EU_FP_ROLLUP_CDC_STALL_DIS_SHIFT 21
+#define DCORE0_MME_CTRL_LO_EU_FP_ROLLUP_CDC_STALL_DIS_MASK 0x200000
+
+/* DCORE0_MME_CTRL_LO_SBTE */
+#define DCORE0_MME_CTRL_LO_SBTE_CLOSE_CGATE_SHIFT 0
+#define DCORE0_MME_CTRL_LO_SBTE_CLOSE_CGATE_MASK 0x1F
+
+/* DCORE0_MME_CTRL_LO_AGU_SM_INFLIGHT_CNTR */
+#define DCORE0_MME_CTRL_LO_AGU_SM_INFLIGHT_CNTR_V_SHIFT 0
+#define DCORE0_MME_CTRL_LO_AGU_SM_INFLIGHT_CNTR_V_MASK 0xFFFFFFFF
+
+/* DCORE0_MME_CTRL_LO_AGU_SM_TOTAL_CNTR */
+#define DCORE0_MME_CTRL_LO_AGU_SM_TOTAL_CNTR_V_SHIFT 0
+#define DCORE0_MME_CTRL_LO_AGU_SM_TOTAL_CNTR_V_MASK 0xFFFFFFFF
+
+/* DCORE0_MME_CTRL_LO_PCU_RL_SAT_SEC */
+#define DCORE0_MME_CTRL_LO_PCU_RL_SAT_SEC_VAL_SHIFT 0
+#define DCORE0_MME_CTRL_LO_PCU_RL_SAT_SEC_VAL_MASK 0xFFFFF
+#define DCORE0_MME_CTRL_LO_PCU_RL_SAT_SEC_SEL_SHIFT 31
+#define DCORE0_MME_CTRL_LO_PCU_RL_SAT_SEC_SEL_MASK 0x80000000
+
+/* DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN32 */
+#define DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN32_V_NMB__SHIFT 0
+#define DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN32_V_NMB__MASK 0xFFFFFFFF
+
+/* DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN33 */
+#define DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN33_V_NMB__SHIFT 0
+#define DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN33_V_NMB__MASK 0x1
+
+/* DCORE0_MME_CTRL_LO_EU_ISOLATION_DIS */
+#define DCORE0_MME_CTRL_LO_EU_ISOLATION_DIS_FMA_SHIFT 0
+#define DCORE0_MME_CTRL_LO_EU_ISOLATION_DIS_FMA_MASK 0x1
+
+/* DCORE0_MME_CTRL_LO_QM_SLV_CLK_EN */
+#define DCORE0_MME_CTRL_LO_QM_SLV_CLK_EN_V_SHIFT 0
+#define DCORE0_MME_CTRL_LO_QM_SLV_CLK_EN_V_MASK 0x1
+
+/* DCORE0_MME_CTRL_LO_HBW_CLK_ENABLER_DIS */
+#define DCORE0_MME_CTRL_LO_HBW_CLK_ENABLER_DIS_AXI_SHIFT 0
+#define DCORE0_MME_CTRL_LO_HBW_CLK_ENABLER_DIS_AXI_MASK 0x1
+#define DCORE0_MME_CTRL_LO_HBW_CLK_ENABLER_DIS_APB_SHIFT 1
+#define DCORE0_MME_CTRL_LO_HBW_CLK_ENABLER_DIS_APB_MASK 0x2
+
+/* DCORE0_MME_CTRL_LO_AGU */
+#define DCORE0_MME_CTRL_LO_AGU_COUT_H_FROM_SPATIAL_LOOP_SHIFT 0
+#define DCORE0_MME_CTRL_LO_AGU_COUT_H_FROM_SPATIAL_LOOP_MASK 0x1
+
+/* DCORE0_MME_CTRL_LO_QM */
+#define DCORE0_MME_CTRL_LO_QM_STOP_ON_SBTE_ERR_SHIFT 0
+#define DCORE0_MME_CTRL_LO_QM_STOP_ON_SBTE_ERR_MASK 0x1
+#define DCORE0_MME_CTRL_LO_QM_EXT_ADDR_ERR_EN_SHIFT 1
+#define DCORE0_MME_CTRL_LO_QM_EXT_ADDR_ERR_EN_MASK 0x2
+
+/* DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS */
+#define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AGU_COUT0_SHIFT 0
+#define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AGU_COUT0_MASK 0xF
+#define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AGU_COUT1_SHIFT 4
+#define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AGU_COUT1_MASK 0xF0
+#define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AP_BRAIN_SHIFT 8
+#define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AP_BRAIN_MASK 0xF00
+#define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_EU_BRAIN_SHIFT 12
+#define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_EU_BRAIN_MASK 0xF000
+
+/* DCORE0_MME_CTRL_LO_INTR_CAUSE */
+#define DCORE0_MME_CTRL_LO_INTR_CAUSE_V_SHIFT 0
+#define DCORE0_MME_CTRL_LO_INTR_CAUSE_V_MASK 0xFFFF
+
+/* DCORE0_MME_CTRL_LO_INTR_MASK */
+#define DCORE0_MME_CTRL_LO_INTR_MASK_V_SHIFT 0
+#define DCORE0_MME_CTRL_LO_INTR_MASK_V_MASK 0x3FFFFF
+
+/* DCORE0_MME_CTRL_LO_INTR_CLEAR */
+#define DCORE0_MME_CTRL_LO_INTR_CLEAR_V_SHIFT 0
+#define DCORE0_MME_CTRL_LO_INTR_CLEAR_V_MASK 0xFFFF
+
+/* DCORE0_MME_CTRL_LO_REDUN_PSOC_SEL_SEC */
+#define DCORE0_MME_CTRL_LO_REDUN_PSOC_SEL_SEC_V_SHIFT 0
+#define DCORE0_MME_CTRL_LO_REDUN_PSOC_SEL_SEC_V_MASK 0x1
+
+/* DCORE0_MME_CTRL_LO_BIST */
+#define DCORE0_MME_CTRL_LO_BIST_FUNC_MODE_SHIFT 0
+#define DCORE0_MME_CTRL_LO_BIST_FUNC_MODE_MASK 0x1
+#define DCORE0_MME_CTRL_LO_BIST_APB_SW_MODE_SHIFT 1
+#define DCORE0_MME_CTRL_LO_BIST_APB_SW_MODE_MASK 0x2
+
+/* DCORE0_MME_CTRL_LO_EU_RL_ENABLE */
+#define DCORE0_MME_CTRL_LO_EU_RL_ENABLE_V_SHIFT 0
+#define DCORE0_MME_CTRL_LO_EU_RL_ENABLE_V_MASK 0x1
+
+/* DCORE0_MME_CTRL_LO_EU_RL_TOKEN_SEL */
+#define DCORE0_MME_CTRL_LO_EU_RL_TOKEN_SEL_STAT_SHIFT 0
+#define DCORE0_MME_CTRL_LO_EU_RL_TOKEN_SEL_STAT_MASK 0x1
+
+/* DCORE0_MME_CTRL_LO_EU_RL_CFG */
+#define DCORE0_MME_CTRL_LO_EU_RL_CFG_RST_TOKEN_SHIFT 0
+#define DCORE0_MME_CTRL_LO_EU_RL_CFG_RST_TOKEN_MASK 0xFF
+#define DCORE0_MME_CTRL_LO_EU_RL_CFG_TIMEOUT_SHIFT 8
+#define DCORE0_MME_CTRL_LO_EU_RL_CFG_TIMEOUT_MASK 0xFF00
+#define DCORE0_MME_CTRL_LO_EU_RL_CFG_SATURATION_SHIFT 16
+#define DCORE0_MME_CTRL_LO_EU_RL_CFG_SATURATION_MASK 0xFF0000
+#define DCORE0_MME_CTRL_LO_EU_RL_CFG_DATA_SIZE_SHIFT 24
+#define DCORE0_MME_CTRL_LO_EU_RL_CFG_DATA_SIZE_MASK 0xFF000000
+
+/* DCORE0_MME_CTRL_LO_PCU_DBG_DW0 */
+#define DCORE0_MME_CTRL_LO_PCU_DBG_DW0_FSM_STATE_SHIFT 0
+#define DCORE0_MME_CTRL_LO_PCU_DBG_DW0_FSM_STATE_MASK 0x1
+#define DCORE0_MME_CTRL_LO_PCU_DBG_DW0_REAL_POOL_TOKENS_SHIFT 8
+#define DCORE0_MME_CTRL_LO_PCU_DBG_DW0_REAL_POOL_TOKENS_MASK 0xFFFFF00
+
+/* DCORE0_MME_CTRL_LO_PCU_DBG_DW1 */
+#define DCORE0_MME_CTRL_LO_PCU_DBG_DW1_ALL_POOL_TOKENS_SHIFT 0
+#define DCORE0_MME_CTRL_LO_PCU_DBG_DW1_ALL_POOL_TOKENS_MASK 0xFFFFF
+
+/* DCORE0_MME_CTRL_LO_PCU_DBG_DW2 */
+#define DCORE0_MME_CTRL_LO_PCU_DBG_DW2_BUBBLE_CYC_CNTR_SHIFT 0
+#define DCORE0_MME_CTRL_LO_PCU_DBG_DW2_BUBBLE_CYC_CNTR_MASK 0xFFFF
+#define DCORE0_MME_CTRL_LO_PCU_DBG_DW2_DUMMY_CYC_CNTR_SHIFT 16
+#define DCORE0_MME_CTRL_LO_PCU_DBG_DW2_DUMMY_CYC_CNTR_MASK 0xFFFF0000
+
+/* DCORE0_MME_CTRL_LO_PCU_DBG_DW3 */
+#define DCORE0_MME_CTRL_LO_PCU_DBG_DW3_REAL_MACS_HISTORY_SHIFT 0
+#define DCORE0_MME_CTRL_LO_PCU_DBG_DW3_REAL_MACS_HISTORY_MASK 0xFFFF
+#define DCORE0_MME_CTRL_LO_PCU_DBG_DW3_ALL_MACS_HISTORY_SHIFT 16
+#define DCORE0_MME_CTRL_LO_PCU_DBG_DW3_ALL_MACS_HISTORY_MASK 0xFFFF0000
+
+/* DCORE0_MME_CTRL_LO_PCU_DBG_WKL_ID */
+#define DCORE0_MME_CTRL_LO_PCU_DBG_WKL_ID_B_SHIFT 0
+#define DCORE0_MME_CTRL_LO_PCU_DBG_WKL_ID_B_MASK 0xFFFFFFFF
+
+/* DCORE0_MME_CTRL_LO_ETF_MEM_WRAP_RM */
+#define DCORE0_MME_CTRL_LO_ETF_MEM_WRAP_RM_V_SHIFT 0
+#define DCORE0_MME_CTRL_LO_ETF_MEM_WRAP_RM_V_MASK 0x3FFFFFFF
+
+#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_mme_axuser_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_mme_axuser_regs.h
new file mode 100644
index 000000000000..a51617a6f1fb
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_mme_axuser_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_MME_AXUSER_REGS_H_
+#define ASIC_REG_DCORE0_MME_CTRL_LO_MME_AXUSER_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_MME_CTRL_LO_MME_AXUSER
+ *   (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_ASID 0x40CBE00
+
+#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_MMU_BP 0x40CBE04
+
+#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_STRONG_ORDER 0x40CBE08
+
+#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_NO_SNOOP 0x40CBE0C
+
+#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_WR_REDUCTION 0x40CBE10
+
+#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_RD_ATOMIC 0x40CBE14
+
+#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_QOS 0x40CBE18
+
+#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_RSVD 0x40CBE1C
+
+#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_EMEM_CPAGE 0x40CBE20
+
+#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_CORE 0x40CBE24
+
+#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_E2E_COORD 0x40CBE28
+
+#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_WR_OVRD_LO 0x40CBE30
+
+#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_WR_OVRD_HI 0x40CBE34
+
+#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_RD_OVRD_LO 0x40CBE38
+
+#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_RD_OVRD_HI 0x40CBE3C
+
+#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_LB_COORD 0x40CBE40
+
+#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_LB_LOCK 0x40CBE44
+
+#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_LB_RSVD 0x40CBE48
+
+#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_LB_OVRD 0x40CBE4C
+
+#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_MME_AXUSER_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_regs.h
new file mode 100644
index 000000000000..1b91c9c13132
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_regs.h
@@ -0,0 +1,163 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_REGS_H_
+#define ASIC_REG_DCORE0_MME_CTRL_LO_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_MME_CTRL_LO
+ *   (Prototype: MME_CTRL_LO)
+ *****************************************
+ */
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_STATUS 0x40CB000
+
+#define mmDCORE0_MME_CTRL_LO_CMD 0x40CB004
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0 0x40CB148
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0 0x40CB14C
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0 0x40CB150
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1 0x40CB154
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1 0x40CB158
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_A_SS 0x40CB224
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_B_SS 0x40CB228
+
+#define mmDCORE0_MME_CTRL_LO_ARCH_COUT_SS 0x40CB27C
+
+#define mmDCORE0_MME_CTRL_LO_QM_STALL 0x40CB400
+
+#define mmDCORE0_MME_CTRL_LO_LOG_SHADOW_LO 0x40CB404
+
+#define mmDCORE0_MME_CTRL_LO_LOG_SHADOW_HI 0x40CB408
+
+#define mmDCORE0_MME_CTRL_LO_SYNC_OBJECT_FIFO_TH 0x40CB40C
+
+#define mmDCORE0_MME_CTRL_LO_REDUN 0x40CB410
+
+#define mmDCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH 0x40CB414
+
+#define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0 0x40CB418
+
+#define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1 0x40CB41C
+
+#define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16 0x40CB420
+
+#define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8 0x40CB424
+
+#define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32 0x40CB428
+
+#define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I 0x40CB42C
+
+#define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32 0x40CB430
+
+#define mmDCORE0_MME_CTRL_LO_PCU_RL_DESC0 0x40CB434
+
+#define mmDCORE0_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE 0x40CB438
+
+#define mmDCORE0_MME_CTRL_LO_PCU_RL_TH 0x40CB43C
+
+#define mmDCORE0_MME_CTRL_LO_PCU_RL_MIN 0x40CB440
+
+#define mmDCORE0_MME_CTRL_LO_PCU_RL_CTRL_EN 0x40CB444
+
+#define mmDCORE0_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE 0x40CB448
+
+#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_A_BF16 0x40CB44C
+
+#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_B_BF16 0x40CB450
+
+#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP16 0x40CB454
+
+#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP16 0x40CB458
+
+#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_F8 0x40CB45C
+
+#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_ODD 0x40CB460
+
+#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_EVEN 0x40CB464
+
+#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_ODD 0x40CB468
+
+#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_EVEN 0x40CB46C
+
+#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_ODD 0x40CB470
+
+#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_EVEN 0x40CB474
+
+#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_ODD 0x40CB478
+
+#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_EVEN 0x40CB47C
+
+#define mmDCORE0_MME_CTRL_LO_PROT 0x40CB480
+
+#define mmDCORE0_MME_CTRL_LO_EU 0x40CB484
+
+#define mmDCORE0_MME_CTRL_LO_SBTE 0x40CB488
+
+#define mmDCORE0_MME_CTRL_LO_AGU_SM_INFLIGHT_CNTR 0x40CB48C
+
+#define mmDCORE0_MME_CTRL_LO_AGU_SM_TOTAL_CNTR 0x40CB490
+
+#define mmDCORE0_MME_CTRL_LO_PCU_RL_SAT_SEC 0x40CB494
+
+#define mmDCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN32 0x40CB498
+
+#define mmDCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN33 0x40CB49C
+
+#define mmDCORE0_MME_CTRL_LO_EU_ISOLATION_DIS 0x40CB4A0
+
+#define mmDCORE0_MME_CTRL_LO_QM_SLV_CLK_EN 0x40CB4A4
+
+#define mmDCORE0_MME_CTRL_LO_HBW_CLK_ENABLER_DIS 0x40CB4A8
+
+#define mmDCORE0_MME_CTRL_LO_AGU 0x40CB4AC
+
+#define mmDCORE0_MME_CTRL_LO_QM 0x40CB4B0
+
+#define mmDCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS 0x40CB4B4
+
+#define mmDCORE0_MME_CTRL_LO_INTR_CAUSE 0x40CB4B8
+
+#define mmDCORE0_MME_CTRL_LO_INTR_MASK 0x40CB4BC
+
+#define mmDCORE0_MME_CTRL_LO_INTR_CLEAR 0x40CB4C0
+
+#define mmDCORE0_MME_CTRL_LO_REDUN_PSOC_SEL_SEC 0x40CB4C4
+
+#define mmDCORE0_MME_CTRL_LO_BIST 0x40CB4C8
+
+#define mmDCORE0_MME_CTRL_LO_EU_RL_ENABLE 0x40CB4CC
+
+#define mmDCORE0_MME_CTRL_LO_EU_RL_TOKEN_SEL 0x40CB4D0
+
+#define mmDCORE0_MME_CTRL_LO_EU_RL_CFG 0x40CB4D4
+
+#define mmDCORE0_MME_CTRL_LO_PCU_DBG_DW0 0x40CB4D8
+
+#define mmDCORE0_MME_CTRL_LO_PCU_DBG_DW1 0x40CB4DC
+
+#define mmDCORE0_MME_CTRL_LO_PCU_DBG_DW2 0x40CB4E0
+
+#define mmDCORE0_MME_CTRL_LO_PCU_DBG_DW3 0x40CB4E4
+
+#define mmDCORE0_MME_CTRL_LO_PCU_DBG_WKL_ID 0x40CB4E8
+
+#define mmDCORE0_MME_CTRL_LO_ETF_MEM_WRAP_RM 0x40CB4EC
+
+#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_acp_eng_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_acp_eng_regs.h
new file mode 100644
index 000000000000..f702fe6e9365
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_acp_eng_regs.h
@@ -0,0 +1,567 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_MME_QM_ARC_ACP_ENG_REGS_H_
+#define ASIC_REG_DCORE0_MME_QM_ARC_ACP_ENG_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_MME_QM_ARC_ACP_ENG
+ *   (Prototype: ARC_ACP_ENG)
+ *****************************************
+ */
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_0 0x40CF000
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_1 0x40CF004
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_2 0x40CF008
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_3 0x40CF00C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_4 0x40CF010
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_5 0x40CF014
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_6 0x40CF018
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_7 0x40CF01C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_8 0x40CF020
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_9 0x40CF024
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_10 0x40CF028
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_11 0x40CF02C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_12 0x40CF030
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_13 0x40CF034
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_14 0x40CF038
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_15 0x40CF03C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_16 0x40CF040
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_17 0x40CF044
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_18 0x40CF048
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_19 0x40CF04C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_20 0x40CF050
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_21 0x40CF054
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_22 0x40CF058
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_23 0x40CF05C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_24 0x40CF060
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_25 0x40CF064
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_26 0x40CF068
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_27 0x40CF06C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_28 0x40CF070
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_29 0x40CF074
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_30 0x40CF078
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_31 0x40CF07C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_32 0x40CF080
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_33 0x40CF084
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_34 0x40CF088
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_35 0x40CF08C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_36 0x40CF090
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_37 0x40CF094
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_38 0x40CF098
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_39 0x40CF09C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_40 0x40CF0A0
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_41 0x40CF0A4
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_42 0x40CF0A8
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_43 0x40CF0AC
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_44 0x40CF0B0
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_45 0x40CF0B4
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_46 0x40CF0B8
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_47 0x40CF0BC
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_48 0x40CF0C0
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_49 0x40CF0C4
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_50 0x40CF0C8
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_51 0x40CF0CC
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_52 0x40CF0D0
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_53 0x40CF0D4
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_54 0x40CF0D8
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_55 0x40CF0DC
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_56 0x40CF0E0
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_57 0x40CF0E4
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_58 0x40CF0E8
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_59 0x40CF0EC
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_60 0x40CF0F0
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_61 0x40CF0F4
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_62 0x40CF0F8
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_63 0x40CF0FC
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_0 0x40CF100
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_1 0x40CF104
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_2 0x40CF108
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_3 0x40CF10C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_4 0x40CF110
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_5 0x40CF114
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_6 0x40CF118
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_7 0x40CF11C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_8 0x40CF120
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_9 0x40CF124
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_10 0x40CF128
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_11 0x40CF12C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_12 0x40CF130
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_13 0x40CF134
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_14 0x40CF138
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_15 0x40CF13C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_16 0x40CF140
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_17 0x40CF144
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_18 0x40CF148
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_19 0x40CF14C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_20 0x40CF150
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_21 0x40CF154
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_22 0x40CF158
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_23 0x40CF15C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_24 0x40CF160
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_25 0x40CF164
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_26 0x40CF168
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_27 0x40CF16C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_28 0x40CF170
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_29 0x40CF174
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_30 0x40CF178
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_31 0x40CF17C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_32 0x40CF180
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_33 0x40CF184
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_34 0x40CF188
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_35 0x40CF18C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_36 0x40CF190
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_37 0x40CF194
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_38 0x40CF198
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_39 0x40CF19C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_40 0x40CF1A0
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_41 0x40CF1A4
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_42 0x40CF1A8
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_43 0x40CF1AC
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_44 0x40CF1B0
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_45 0x40CF1B4
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_46 0x40CF1B8
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_47 0x40CF1BC
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_48 0x40CF1C0
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_49 0x40CF1C4
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_50 0x40CF1C8
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_51 0x40CF1CC
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_52 0x40CF1D0
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_53 0x40CF1D4
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_54 0x40CF1D8
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_55 0x40CF1DC
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_56 0x40CF1E0
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_57 0x40CF1E4
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_58 0x40CF1E8
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_59 0x40CF1EC
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_60 0x40CF1F0
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_61 0x40CF1F4
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_62 0x40CF1F8
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_63 0x40CF1FC
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_0 0x40CF200
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_1 0x40CF204
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_2 0x40CF208
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_3 0x40CF20C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_4 0x40CF210
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_5 0x40CF214
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_6 0x40CF218
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_7 0x40CF21C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_8 0x40CF220
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_9 0x40CF224
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_10 0x40CF228
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_11 0x40CF22C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_12 0x40CF230
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_13 0x40CF234
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_14 0x40CF238
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_15 0x40CF23C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_16 0x40CF240
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_17 0x40CF244
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_18 0x40CF248
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_19 0x40CF24C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_20 0x40CF250
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_21 0x40CF254
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_22 0x40CF258
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_23 0x40CF25C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_24 0x40CF260
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_25 0x40CF264
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_26 0x40CF268
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_27 0x40CF26C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_28 0x40CF270
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_29 0x40CF274
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_30 0x40CF278
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_31 0x40CF27C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_32 0x40CF280
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_33 0x40CF284
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_34 0x40CF288
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_35 0x40CF28C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_36 0x40CF290
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_37 0x40CF294
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_38 0x40CF298
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_39 0x40CF29C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_40 0x40CF2A0
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_41 0x40CF2A4
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_42 0x40CF2A8
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_43 0x40CF2AC
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_44 0x40CF2B0
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_45 0x40CF2B4
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_46 0x40CF2B8
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_47 0x40CF2BC
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_48 0x40CF2C0
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_49 0x40CF2C4
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_50 0x40CF2C8
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_51 0x40CF2CC
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_52 0x40CF2D0
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_53 0x40CF2D4
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_54 0x40CF2D8
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_55 0x40CF2DC
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_56 0x40CF2E0
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_57 0x40CF2E4
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_58 0x40CF2E8
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_59 0x40CF2EC
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_60 0x40CF2F0
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_61 0x40CF2F4
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_62 0x40CF2F8
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_63 0x40CF2FC
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_0 0x40CF300
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_1 0x40CF304
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_2 0x40CF308
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_3 0x40CF30C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_4 0x40CF310
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_5 0x40CF314
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_6 0x40CF318
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_7 0x40CF31C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_8 0x40CF320
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_9 0x40CF324
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_10 0x40CF328
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_11 0x40CF32C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_12 0x40CF330
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_13 0x40CF334
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_14 0x40CF338
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_15 0x40CF33C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_16 0x40CF340
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_17 0x40CF344
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_18 0x40CF348
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_19 0x40CF34C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_20 0x40CF350
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_21 0x40CF354
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_22 0x40CF358
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_23 0x40CF35C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_24 0x40CF360
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_25 0x40CF364
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_26 0x40CF368
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_27 0x40CF36C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_28 0x40CF370
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_29 0x40CF374
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_30 0x40CF378
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_31 0x40CF37C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_32 0x40CF380
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_33 0x40CF384
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_34 0x40CF388
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_35 0x40CF38C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_36 0x40CF390
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_37 0x40CF394
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_38 0x40CF398
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_39 0x40CF39C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_40 0x40CF3A0
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_41 0x40CF3A4
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_42 0x40CF3A8
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_43 0x40CF3AC
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_44 0x40CF3B0
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_45 0x40CF3B4
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_46 0x40CF3B8
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_47 0x40CF3BC
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_48 0x40CF3C0
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_49 0x40CF3C4
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_50 0x40CF3C8
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_51 0x40CF3CC
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_52 0x40CF3D0
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_53 0x40CF3D4
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_54 0x40CF3D8
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_55 0x40CF3DC
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_56 0x40CF3E0
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_57 0x40CF3E4
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_58 0x40CF3E8
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_59 0x40CF3EC
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_60 0x40CF3F0
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_61 0x40CF3F4
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_62 0x40CF3F8
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_63 0x40CF3FC
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_SELECTED_QUEUE_ID 0x40CF400
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_GRANTS_WEIGHT_PRIO_0 0x40CF404
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_GRANTS_WEIGHT_PRIO_1 0x40CF408
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_GRANTS_WEIGHT_PRIO_2 0x40CF40C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_GRANTS_COUNTER_PRIO_0 0x40CF410
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_GRANTS_COUNTER_PRIO_1 0x40CF414
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_GRANTS_COUNTER_PRIO_2 0x40CF418
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_PRIO_OUT_CNT_0 0x40CF41C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_PRIO_OUT_CNT_1 0x40CF420
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_PRIO_OUT_CNT_2 0x40CF424
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_PRIO_OUT_CNT_3 0x40CF428
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_PRIO_RD_CNT_0 0x40CF42C
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_PRIO_RD_CNT_1 0x40CF430
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_PRIO_RD_CNT_2 0x40CF434
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_PRIO_RD_CNT_3 0x40CF438
+
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_REG 0x40CF43C
+
+#endif /* ASIC_REG_DCORE0_MME_QM_ARC_ACP_ENG_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_aux_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_aux_regs.h
new file mode 100644
index 000000000000..917f8ab88373
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_aux_regs.h
@@ -0,0 +1,591 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_MME_QM_ARC_AUX_REGS_H_
+#define ASIC_REG_DCORE0_MME_QM_ARC_AUX_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_MME_QM_ARC_AUX
+ *   (Prototype: QMAN_ARC_AUX)
+ *****************************************
+ */
+
+#define mmDCORE0_MME_QM_ARC_AUX_RUN_HALT_REQ 0x40C8100
+
+#define mmDCORE0_MME_QM_ARC_AUX_RUN_HALT_ACK 0x40C8104
+
+#define mmDCORE0_MME_QM_ARC_AUX_RST_VEC_ADDR 0x40C8108
+
+#define mmDCORE0_MME_QM_ARC_AUX_DBG_MODE 0x40C810C
+
+#define mmDCORE0_MME_QM_ARC_AUX_CLUSTER_NUM 0x40C8110
+
+#define mmDCORE0_MME_QM_ARC_AUX_ARC_NUM 0x40C8114
+
+#define mmDCORE0_MME_QM_ARC_AUX_WAKE_UP_EVENT 0x40C8118
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_SYS_ADDR_BASE 0x40C811C
+
+#define mmDCORE0_MME_QM_ARC_AUX_CTI_AP_STS 0x40C8120
+
+#define mmDCORE0_MME_QM_ARC_AUX_CTI_CFG_MUX_SEL 0x40C8124
+
+#define mmDCORE0_MME_QM_ARC_AUX_ARC_RST 0x40C8128
+
+#define mmDCORE0_MME_QM_ARC_AUX_ARC_RST_REQ 0x40C812C
+
+#define mmDCORE0_MME_QM_ARC_AUX_SRAM_LSB_ADDR 0x40C8130
+
+#define mmDCORE0_MME_QM_ARC_AUX_SRAM_MSB_ADDR 0x40C8134
+
+#define mmDCORE0_MME_QM_ARC_AUX_PCIE_LSB_ADDR 0x40C8138
+
+#define mmDCORE0_MME_QM_ARC_AUX_PCIE_MSB_ADDR 0x40C813C
+
+#define mmDCORE0_MME_QM_ARC_AUX_CFG_LSB_ADDR 0x40C8140
+
+#define mmDCORE0_MME_QM_ARC_AUX_CFG_MSB_ADDR 0x40C8144
+
+#define mmDCORE0_MME_QM_ARC_AUX_HBM0_LSB_ADDR 0x40C8150
+
+#define mmDCORE0_MME_QM_ARC_AUX_HBM0_MSB_ADDR 0x40C8154
+
+#define mmDCORE0_MME_QM_ARC_AUX_HBM1_LSB_ADDR 0x40C8158
+
+#define mmDCORE0_MME_QM_ARC_AUX_HBM1_MSB_ADDR 0x40C815C
+
+#define mmDCORE0_MME_QM_ARC_AUX_HBM2_LSB_ADDR 0x40C8160
+
+#define mmDCORE0_MME_QM_ARC_AUX_HBM2_MSB_ADDR 0x40C8164
+
+#define mmDCORE0_MME_QM_ARC_AUX_HBM3_LSB_ADDR 0x40C8168
+
+#define mmDCORE0_MME_QM_ARC_AUX_HBM3_MSB_ADDR 0x40C816C
+
+#define mmDCORE0_MME_QM_ARC_AUX_HBM0_OFFSET 0x40C8170
+
+#define mmDCORE0_MME_QM_ARC_AUX_HBM1_OFFSET 0x40C8174
+
+#define mmDCORE0_MME_QM_ARC_AUX_HBM2_OFFSET 0x40C8178
+
+#define mmDCORE0_MME_QM_ARC_AUX_HBM3_OFFSET 0x40C817C
+
+#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_0 0x40C8180
+
+#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_1 0x40C8184
+
+#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_2 0x40C8188
+
+#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_3 0x40C818C
+
+#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_4 0x40C8190
+
+#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_5 0x40C8194
+
+#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_6 0x40C8198
+
+#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_0 0x40C819C
+
+#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_1 0x40C81A0
+
+#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_2 0x40C81A4
+
+#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_3 0x40C81A8
+
+#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_4 0x40C81AC
+
+#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_5 0x40C81B0
+
+#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_6 0x40C81B4
+
+#define mmDCORE0_MME_QM_ARC_AUX_ARC_CBU_AWCACHE_OVR 0x40C81B8
+
+#define mmDCORE0_MME_QM_ARC_AUX_ARC_LBU_AWCACHE_OVR 0x40C81BC
+
+#define mmDCORE0_MME_QM_ARC_AUX_CONTEXT_ID_0 0x40C81C0
+
+#define mmDCORE0_MME_QM_ARC_AUX_CONTEXT_ID_1 0x40C81C4
+
+#define mmDCORE0_MME_QM_ARC_AUX_CONTEXT_ID_2 0x40C81C8
+
+#define mmDCORE0_MME_QM_ARC_AUX_CONTEXT_ID_3 0x40C81CC
+
+#define mmDCORE0_MME_QM_ARC_AUX_CONTEXT_ID_4 0x40C81D0
+
+#define mmDCORE0_MME_QM_ARC_AUX_CONTEXT_ID_5 0x40C81D4
+
+#define mmDCORE0_MME_QM_ARC_AUX_CONTEXT_ID_6 0x40C81D8
+
+#define mmDCORE0_MME_QM_ARC_AUX_CONTEXT_ID_7 0x40C81DC
+
+#define mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_0 0x40C81E0
+
+#define mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_1 0x40C81E4
+
+#define mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_2 0x40C81E8
+
+#define mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_3 0x40C81EC
+
+#define mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_4 0x40C81F0
+
+#define mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_5 0x40C81F4
+
+#define mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_6 0x40C81F8
+
+#define mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_7 0x40C81FC
+
+#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_0 0x40C8200
+
+#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_1 0x40C8204
+
+#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_2 0x40C8208
+
+#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_3 0x40C820C
+
+#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_4 0x40C8210
+
+#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_5 0x40C8214
+
+#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_6 0x40C8218
+
+#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_7 0x40C821C
+
+#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_8 0x40C8220
+
+#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_9 0x40C8224
+
+#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_10 0x40C8228
+
+#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_11 0x40C822C
+
+#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_12 0x40C8230
+
+#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_13 0x40C8234
+
+#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_14 0x40C8238
+
+#define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_15 0x40C823C
+
+#define mmDCORE0_MME_QM_ARC_AUX_IRQ_INTR_MASK_0 0x40C8280
+
+#define mmDCORE0_MME_QM_ARC_AUX_IRQ_INTR_MASK_1 0x40C8284
+
+#define mmDCORE0_MME_QM_ARC_AUX_ARC_SEI_INTR_STS 0x40C8290
+
+#define mmDCORE0_MME_QM_ARC_AUX_ARC_SEI_INTR_CLR 0x40C8294
+
+#define mmDCORE0_MME_QM_ARC_AUX_ARC_SEI_INTR_MASK 0x40C8298
+
+#define mmDCORE0_MME_QM_ARC_AUX_ARC_EXCPTN_CAUSE 0x40C829C
+
+#define mmDCORE0_MME_QM_ARC_AUX_SEI_INTR_HALT_EN 0x40C82A0
+
+#define mmDCORE0_MME_QM_ARC_AUX_ARC_SEI_INTR_HALT_MASK 0x40C82A4
+
+#define mmDCORE0_MME_QM_ARC_AUX_QMAN_SEI_INTR_HALT_MASK 0x40C82A8
+
+#define mmDCORE0_MME_QM_ARC_AUX_ARC_REI_INTR_STS 0x40C82B0
+
+#define mmDCORE0_MME_QM_ARC_AUX_ARC_REI_INTR_CLR 0x40C82B4
+
+#define mmDCORE0_MME_QM_ARC_AUX_ARC_REI_INTR_MASK 0x40C82B8
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_ECC_ERR_ADDR 0x40C82BC
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_ECC_SYNDROME 0x40C82C0
+
+#define mmDCORE0_MME_QM_ARC_AUX_I_CACHE_ECC_ERR_ADDR 0x40C82C4
+
+#define mmDCORE0_MME_QM_ARC_AUX_I_CACHE_ECC_SYNDROME 0x40C82C8
+
+#define mmDCORE0_MME_QM_ARC_AUX_D_CACHE_ECC_ERR_ADDR 0x40C82CC
+
+#define mmDCORE0_MME_QM_ARC_AUX_D_CACHE_ECC_SYNDROME 0x40C82D0
+
+#define mmDCORE0_MME_QM_ARC_AUX_LBW_TRMINATE_AWADDR_ERR 0x40C82E0
+
+#define mmDCORE0_MME_QM_ARC_AUX_LBW_TRMINATE_ARADDR_ERR 0x40C82E4
+
+#define mmDCORE0_MME_QM_ARC_AUX_CFG_LBW_TERMINATE_BRESP 0x40C82E8
+
+#define mmDCORE0_MME_QM_ARC_AUX_CFG_LBW_TERMINATE_RRESP 0x40C82EC
+
+#define mmDCORE0_MME_QM_ARC_AUX_CFG_LBW_TERMINATE_AXLEN 0x40C82F0
+
+#define mmDCORE0_MME_QM_ARC_AUX_CFG_LBW_TERMINATE_AXSIZE 0x40C82F4
+
+#define mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_0 0x40C8300
+
+#define mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_1 0x40C8304
+
+#define mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_2 0x40C8308
+
+#define mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_3 0x40C830C
+
+#define mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_4 0x40C8310
+
+#define mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_5 0x40C8314
+
+#define mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_6 0x40C8318
+
+#define mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_7 0x40C831C
+
+#define mmDCORE0_MME_QM_ARC_AUX_TOTAL_CBU_WR_CNT 0x40C8320
+
+#define mmDCORE0_MME_QM_ARC_AUX_INFLIGHT_CBU_WR_CNT 0x40C8324
+
+#define mmDCORE0_MME_QM_ARC_AUX_TOTAL_CBU_RD_CNT 0x40C8328
+
+#define mmDCORE0_MME_QM_ARC_AUX_INFLIGHT_CBU_RD_CNT 0x40C832C
+
+#define mmDCORE0_MME_QM_ARC_AUX_TOTAL_LBU_WR_CNT 0x40C8330
+
+#define mmDCORE0_MME_QM_ARC_AUX_INFLIGHT_LBU_WR_CNT 0x40C8334
+
+#define mmDCORE0_MME_QM_ARC_AUX_TOTAL_LBU_RD_CNT 0x40C8338
+
+#define mmDCORE0_MME_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT 0x40C833C
+
+#define mmDCORE0_MME_QM_ARC_AUX_CBU_ARUSER_OVR 0x40C8350
+
+#define mmDCORE0_MME_QM_ARC_AUX_CBU_ARUSER_OVR_EN 0x40C8354
+
+#define mmDCORE0_MME_QM_ARC_AUX_CBU_AWUSER_OVR 0x40C8358
+
+#define mmDCORE0_MME_QM_ARC_AUX_CBU_AWUSER_OVR_EN 0x40C835C
+
+#define mmDCORE0_MME_QM_ARC_AUX_CBU_ARUSER_MSB_OVR 0x40C8360
+
+#define mmDCORE0_MME_QM_ARC_AUX_CBU_ARUSER_MSB_OVR_EN 0x40C8364
+
+#define mmDCORE0_MME_QM_ARC_AUX_CBU_AWUSER_MSB_OVR 0x40C8368
+
+#define mmDCORE0_MME_QM_ARC_AUX_CBU_AWUSER_MSB_OVR_EN 0x40C836C
+
+#define mmDCORE0_MME_QM_ARC_AUX_CBU_AXCACHE_OVR 0x40C8370
+
+#define mmDCORE0_MME_QM_ARC_AUX_CBU_LOCK_OVR 0x40C8374
+
+#define mmDCORE0_MME_QM_ARC_AUX_CBU_PROT_OVR 0x40C8378
+
+#define mmDCORE0_MME_QM_ARC_AUX_CBU_MAX_OUTSTANDING 0x40C837C
+
+#define mmDCORE0_MME_QM_ARC_AUX_CBU_EARLY_BRESP_EN 0x40C8380
+
+#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORCE_RSP_OK 0x40C8384
+
+#define mmDCORE0_MME_QM_ARC_AUX_CBU_NO_WR_INFLIGHT 0x40C838C
+
+#define mmDCORE0_MME_QM_ARC_AUX_CBU_SEI_INTR_ID 0x40C8390
+
+#define mmDCORE0_MME_QM_ARC_AUX_LBU_ARUSER_OVR 0x40C8400
+
+#define mmDCORE0_MME_QM_ARC_AUX_LBU_ARUSER_OVR_EN 0x40C8404
+
+#define mmDCORE0_MME_QM_ARC_AUX_LBU_AWUSER_OVR 0x40C8408
+
+#define mmDCORE0_MME_QM_ARC_AUX_LBU_AWUSER_OVR_EN 0x40C840C
+
+#define mmDCORE0_MME_QM_ARC_AUX_LBU_AXCACHE_OVR 0x40C8420
+
+#define mmDCORE0_MME_QM_ARC_AUX_LBU_LOCK_OVR 0x40C8424
+
+#define mmDCORE0_MME_QM_ARC_AUX_LBU_PROT_OVR 0x40C8428
+
+#define mmDCORE0_MME_QM_ARC_AUX_LBU_MAX_OUTSTANDING 0x40C842C
+
+#define mmDCORE0_MME_QM_ARC_AUX_LBU_EARLY_BRESP_EN 0x40C8430
+
+#define mmDCORE0_MME_QM_ARC_AUX_LBU_FORCE_RSP_OK 0x40C8434
+
+#define mmDCORE0_MME_QM_ARC_AUX_LBU_NO_WR_INFLIGHT 0x40C843C
+
+#define mmDCORE0_MME_QM_ARC_AUX_LBU_SEI_INTR_ID 0x40C8440
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0 0x40C8500
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_1 0x40C8504
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_2 0x40C8508
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_3 0x40C850C
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_4 0x40C8510
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_5 0x40C8514
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_6 0x40C8518
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_7 0x40C851C
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_SIZE_0 0x40C8520
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_SIZE_1 0x40C8524
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_SIZE_2 0x40C8528
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_SIZE_3 0x40C852C
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_SIZE_4 0x40C8530
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_SIZE_5 0x40C8534
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_SIZE_6 0x40C8538
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_SIZE_7 0x40C853C
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PI_0 0x40C8540
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PI_1 0x40C8544
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PI_2 0x40C8548
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PI_3 0x40C854C
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PI_4 0x40C8550
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PI_5 0x40C8554
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PI_6 0x40C8558
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PI_7 0x40C855C
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_CI_0 0x40C8560
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_CI_1 0x40C8564
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_CI_2 0x40C8568
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_CI_3 0x40C856C
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_CI_4 0x40C8570
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_CI_5 0x40C8574
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_CI_6 0x40C8578
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_CI_7 0x40C857C
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_0 0x40C8580
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_1 0x40C8584
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_2 0x40C8588
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_3 0x40C858C
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_4 0x40C8590
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_5 0x40C8594
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_6 0x40C8598
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_7 0x40C859C
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_0 0x40C85A0
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_1 0x40C85A4
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_2 0x40C85A8
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_3 0x40C85AC
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_4 0x40C85B0
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_5 0x40C85B4
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_6 0x40C85B8
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_7 0x40C85BC
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_0 0x40C85C0
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_1 0x40C85C4
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_2 0x40C85C8
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_3 0x40C85CC
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_4 0x40C85D0
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_5 0x40C85D4
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_6 0x40C85D8
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_7 0x40C85DC
+
+#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_Q_VLD_ENTRY_MASK 0x40C85E0
+
+#define mmDCORE0_MME_QM_ARC_AUX_NIC_Q_VLD_ENTRY_MASK 0x40C85E4
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_DROP_EN 0x40C8620
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_WARN_MSG 0x40C8624
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG 0x40C8628
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_GEN_AXI_AWPROT 0x40C8630
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_GEN_AXI_AWUSER 0x40C8634
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_GEN_AXI_AWBURST 0x40C8638
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_GEN_AXI_AWLOCK 0x40C863C
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_GEN_AXI_AWCACHE 0x40C8640
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_WRR_ARB_WEIGHT 0x40C8644
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_FULL_CFG 0x40C8648
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT 0x40C864C
+
+#define mmDCORE0_MME_QM_ARC_AUX_QMAN_CQ_IFIFO_SHADOW_CI 0x40C8650
+
+#define mmDCORE0_MME_QM_ARC_AUX_QMAN_ARC_CQ_IFIFO_SHADOW_CI 0x40C8654
+
+#define mmDCORE0_MME_QM_ARC_AUX_QMAN_CQ_SHADOW_CI 0x40C8658
+
+#define mmDCORE0_MME_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI 0x40C865C
+
+#define mmDCORE0_MME_QM_ARC_AUX_AUX2APB_PROT 0x40C8700
+
+#define mmDCORE0_MME_QM_ARC_AUX_LBW_FORK_WIN_EN 0x40C8704
+
+#define mmDCORE0_MME_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR0 0x40C8708
+
+#define mmDCORE0_MME_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK0 0x40C870C
+
+#define mmDCORE0_MME_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR1 0x40C8710
+
+#define mmDCORE0_MME_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK1 0x40C8714
+
+#define mmDCORE0_MME_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR0 0x40C8718
+
+#define mmDCORE0_MME_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK0 0x40C871C
+
+#define mmDCORE0_MME_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR1 0x40C8720
+
+#define mmDCORE0_MME_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK1 0x40C8724
+
+#define mmDCORE0_MME_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR0 0x40C8728
+
+#define mmDCORE0_MME_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR1 0x40C872C
+
+#define mmDCORE0_MME_QM_ARC_AUX_ARC_ACC_ENGS_LBW_FORK_MASK 0x40C8730
+
+#define mmDCORE0_MME_QM_ARC_AUX_ARC_DUP_ENG_LBW_FORK_ADDR 0x40C8734
+
+#define mmDCORE0_MME_QM_ARC_AUX_ARC_ACP_ENG_LBW_FORK_ADDR 0x40C8738
+
+#define mmDCORE0_MME_QM_ARC_AUX_ARC_ACC_ENGS_VIRTUAL_ADDR 0x40C873C
+
+#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_WIN_EN 0x40C8740
+
+#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_LSB 0x40C8750
+
+#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_MSB 0x40C8754
+
+#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_LSB 0x40C8758
+
+#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_MSB 0x40C875C
+
+#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_LSB 0x40C8760
+
+#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_MSB 0x40C8764
+
+#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_LSB 0x40C8768
+
+#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_MSB 0x40C876C
+
+#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_LSB 0x40C8770
+
+#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_MSB 0x40C8774
+
+#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_LSB 0x40C8778
+
+#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_MSB 0x40C877C
+
+#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_LSB 0x40C8780
+
+#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_MSB 0x40C8784
+
+#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_LSB 0x40C8788
+
+#define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_MSB 0x40C878C
+
+#define mmDCORE0_MME_QM_ARC_AUX_CBU_TRMINATE_ARADDR_LSB 0x40C8790
+
+#define mmDCORE0_MME_QM_ARC_AUX_CBU_TRMINATE_ARADDR_MSB 0x40C8794
+
+#define mmDCORE0_MME_QM_ARC_AUX_CFG_CBU_TERMINATE_BRESP 0x40C8798
+
+#define mmDCORE0_MME_QM_ARC_AUX_CFG_CBU_TERMINATE_RRESP 0x40C879C
+
+#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_0 0x40C8800
+
+#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_1 0x40C8804
+
+#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_2 0x40C8808
+
+#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_3 0x40C880C
+
+#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_4 0x40C8810
+
+#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_5 0x40C8814
+
+#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_6 0x40C8818
+
+#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_7 0x40C881C
+
+#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_8 0x40C8820
+
+#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_9 0x40C8824
+
+#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_10 0x40C8828
+
+#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_11 0x40C882C
+
+#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_12 0x40C8830
+
+#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_13 0x40C8834
+
+#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_14 0x40C8838
+
+#define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_15 0x40C883C
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_TRMINATE_AWADDR_ERR 0x40C8840
+
+#define mmDCORE0_MME_QM_ARC_AUX_DCCM_TRMINATE_ARADDR_ERR 0x40C8844
+
+#define mmDCORE0_MME_QM_ARC_AUX_CFG_DCCM_TERMINATE_BRESP 0x40C8848
+
+#define mmDCORE0_MME_QM_ARC_AUX_CFG_DCCM_TERMINATE_RRESP 0x40C884C
+
+#define mmDCORE0_MME_QM_ARC_AUX_CFG_DCCM_TERMINATE_EN 0x40C8850
+
+#define mmDCORE0_MME_QM_ARC_AUX_CFG_DCCM_SECURE_REGION 0x40C8854
+
+#define mmDCORE0_MME_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT 0x40C8900
+
+#define mmDCORE0_MME_QM_ARC_AUX_ARC_AXI_ORDERING_CTL 0x40C8904
+
+#define mmDCORE0_MME_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR_MSK 0x40C8908
+
+#define mmDCORE0_MME_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR 0x40C890C
+
+#define mmDCORE0_MME_QM_ARC_AUX_ARC_ACC_ENGS_BUSER 0x40C8910
+
+#define mmDCORE0_MME_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN 0x40C8920
+
+#endif /* ASIC_REG_DCORE0_MME_QM_ARC_AUX_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_dup_eng_axuser_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_dup_eng_axuser_regs.h
new file mode 100644
index 000000000000..c7ebaf73c51e
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_dup_eng_axuser_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_MME_QM_ARC_DUP_ENG_AXUSER_REGS_H_
+#define ASIC_REG_DCORE0_MME_QM_ARC_DUP_ENG_AXUSER_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_MME_QM_ARC_DUP_ENG_AXUSER
+ *   (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_ASID 0x40C9900
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_MMU_BP 0x40C9904
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_STRONG_ORDER 0x40C9908
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_NO_SNOOP 0x40C990C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_WR_REDUCTION 0x40C9910
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_RD_ATOMIC 0x40C9914
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_QOS 0x40C9918
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_RSVD 0x40C991C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_EMEM_CPAGE 0x40C9920
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_CORE 0x40C9924
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_E2E_COORD 0x40C9928
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_WR_OVRD_LO 0x40C9930
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_WR_OVRD_HI 0x40C9934
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_RD_OVRD_LO 0x40C9938
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_RD_OVRD_HI 0x40C993C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_LB_COORD 0x40C9940
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_LB_LOCK 0x40C9944
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_LB_RSVD 0x40C9948
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_LB_OVRD 0x40C994C
+
+#endif /* ASIC_REG_DCORE0_MME_QM_ARC_DUP_ENG_AXUSER_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_dup_eng_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_dup_eng_regs.h
new file mode 100644
index 000000000000..61654e37335b
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_dup_eng_regs.h
@@ -0,0 +1,575 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_MME_QM_ARC_DUP_ENG_REGS_H_
+#define ASIC_REG_DCORE0_MME_QM_ARC_DUP_ENG_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_MME_QM_ARC_DUP_ENG
+ *   (Prototype: ARC_DUP_ENG)
+ *****************************************
+ */
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_0 0x40C9000
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_1 0x40C9004
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_2 0x40C9008
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_3 0x40C900C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_4 0x40C9010
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_5 0x40C9014
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_6 0x40C9018
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_7 0x40C901C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_8 0x40C9020
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_9 0x40C9024
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_10 0x40C9028
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_11 0x40C902C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_12 0x40C9030
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_13 0x40C9034
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_14 0x40C9038
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_15 0x40C903C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_16 0x40C9040
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_17 0x40C9044
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_18 0x40C9048
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_19 0x40C904C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_20 0x40C9050
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_21 0x40C9054
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_22 0x40C9058
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_23 0x40C905C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_24 0x40C9060
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_MME_ENG_ADDR_0 0x40C9064
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_MME_ENG_ADDR_1 0x40C9068
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_MME_ENG_ADDR_2 0x40C906C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_MME_ENG_ADDR_3 0x40C9070
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_0 0x40C9074
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_1 0x40C9078
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_2 0x40C907C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_3 0x40C9080
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_4 0x40C9084
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_5 0x40C9088
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_6 0x40C908C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_7 0x40C9090
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_8 0x40C9094
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_9 0x40C9098
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_10 0x40C909C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_11 0x40C90A0
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_12 0x40C90A4
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_13 0x40C90A8
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_14 0x40C90AC
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_15 0x40C90B0
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_16 0x40C90B4
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_17 0x40C90B8
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_18 0x40C90BC
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_19 0x40C90C0
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_20 0x40C90C4
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_21 0x40C90C8
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_22 0x40C90CC
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_23 0x40C90D0
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_ADDR_0 0x40C90D4
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_ADDR_1 0x40C90D8
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_ADDR_2 0x40C90DC
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_ADDR_3 0x40C90E0
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_ADDR_4 0x40C90E4
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_ADDR_5 0x40C90E8
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_ADDR_6 0x40C90EC
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_ADDR_7 0x40C90F0
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_PDMA_ENG_ADDR_0 0x40C90F4
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_PDMA_ENG_ADDR_1 0x40C90F8
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_ROT_ENG_ADDR_0 0x40C90FC
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_ROT_ENG_ADDR_1 0x40C9100
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_0 0x40C9104
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_1 0x40C9108
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_2 0x40C910C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_3 0x40C9110
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_4 0x40C9114
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_5 0x40C9118
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_6 0x40C911C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_7 0x40C9120
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_8 0x40C9124
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_9 0x40C9128
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_10 0x40C912C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_11 0x40C9130
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_12 0x40C9134
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_13 0x40C9138
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_14 0x40C913C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_15 0x40C9140
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_MASK 0x40C9200
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_MME_ENG_MASK 0x40C9204
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_MASK 0x40C9208
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_PDMA_ENG_MASK 0x40C920C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_ROT_ENG_MASK 0x40C9210
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_MASK 0x40C9214
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_MASK_0 0x40C9218
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_MASK_1 0x40C921C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_MASK_2 0x40C9220
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_MASK_3 0x40C9224
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_MASK_4 0x40C9228
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_MASK_5 0x40C922C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_MASK_6 0x40C9230
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_MASK_7 0x40C9234
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_0 0x40C9238
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_1 0x40C923C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_2 0x40C9240
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_3 0x40C9244
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_4 0x40C9248
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_5 0x40C924C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_6 0x40C9250
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_7 0x40C9254
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_8 0x40C9258
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_9 0x40C925C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_10 0x40C9260
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_11 0x40C9264
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_12 0x40C9268
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_13 0x40C926C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_1_0 0x40C9288
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_1_1 0x40C928C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_1_2 0x40C9290
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_1_3 0x40C9294
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_1_4 0x40C9298
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_1_5 0x40C929C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_2_0 0x40C92A0
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_2_1 0x40C92A4
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_2_2 0x40C92A8
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_2_3 0x40C92AC
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_2_4 0x40C92B0
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_2_5 0x40C92B4
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_3_0 0x40C92B8
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_3_1 0x40C92BC
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_3_2 0x40C92C0
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_3_3 0x40C92C4
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_3_4 0x40C92C8
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_3_5 0x40C92CC
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GENERAL_CFG 0x40C92D0
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_BP_CFG 0x40C92D4
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_0 0x40C92D8
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_1 0x40C92DC
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_2 0x40C92E0
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_3 0x40C92E4
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_4 0x40C92E8
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_5 0x40C92EC
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_6 0x40C92F0
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_7 0x40C92F4
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_8 0x40C92F8
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_9 0x40C92FC
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_10 0x40C9300
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_11 0x40C9304
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_12 0x40C9308
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_13 0x40C930C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_DBG_IN_GRP_TRANS_0 0x40C94A0
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_DBG_IN_GRP_TRANS_1 0x40C94A4
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_DBG_IN_GRP_TRANS_2 0x40C94A8
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_DBG_STS 0x40C94AC
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_DBG_OUT_RQ_CNT 0x40C94B0
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_0 0x40C94B4
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_1 0x40C94B8
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_2 0x40C94BC
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_3 0x40C94C0
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_4 0x40C94C4
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_5 0x40C94C8
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_6 0x40C94CC
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_7 0x40C94D0
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_8 0x40C94D4
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_9 0x40C94D8
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_10 0x40C94DC
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_11 0x40C94E0
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_12 0x40C94E4
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_13 0x40C94E8
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_14 0x40C94EC
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_15 0x40C94F0
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_16 0x40C94F4
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_17 0x40C94F8
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_18 0x40C94FC
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_19 0x40C9500
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_20 0x40C9504
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_21 0x40C9508
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_22 0x40C950C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_23 0x40C9510
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_24 0x40C9514
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_25 0x40C9518
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_26 0x40C951C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_27 0x40C9520
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_28 0x40C9524
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_29 0x40C9528
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_30 0x40C952C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_31 0x40C9530
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_32 0x40C9534
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_33 0x40C9538
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_34 0x40C953C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_35 0x40C9540
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_36 0x40C9544
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_37 0x40C9548
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_38 0x40C954C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_39 0x40C9550
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_40 0x40C9554
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_41 0x40C9558
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_42 0x40C955C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_43 0x40C9560
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_44 0x40C9564
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_45 0x40C9568
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_46 0x40C956C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_47 0x40C9570
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_48 0x40C9574
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_49 0x40C9578
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_50 0x40C957C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_51 0x40C9580
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_52 0x40C9584
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_53 0x40C9588
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_54 0x40C958C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_55 0x40C9590
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_56 0x40C9594
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_57 0x40C9598
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_58 0x40C959C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_59 0x40C95A0
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_60 0x40C95A4
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_61 0x40C95A8
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_62 0x40C95AC
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_63 0x40C95B0
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_0 0x40C95B4
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_1 0x40C95B8
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_2 0x40C95BC
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_3 0x40C95C0
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_4 0x40C95C4
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_5 0x40C95C8
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_6 0x40C95CC
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_7 0x40C95D0
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_8 0x40C95D4
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_9 0x40C95D8
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_10 0x40C95DC
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_11 0x40C95E0
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_12 0x40C95E4
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_13 0x40C95E8
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_14 0x40C95EC
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_15 0x40C95F0
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_16 0x40C95F4
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_17 0x40C95F8
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_18 0x40C95FC
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_19 0x40C9600
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_20 0x40C9604
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_21 0x40C9608
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_22 0x40C960C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_23 0x40C9610
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_24 0x40C9614
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_25 0x40C9618
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_26 0x40C961C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_27 0x40C9620
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_28 0x40C9624
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_29 0x40C9628
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_30 0x40C962C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_31 0x40C9630
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_32 0x40C9634
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_33 0x40C9638
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_34 0x40C963C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_35 0x40C9640
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_36 0x40C9644
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_37 0x40C9648
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_38 0x40C964C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_39 0x40C9650
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_40 0x40C9654
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_41 0x40C9658
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_42 0x40C965C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_43 0x40C9660
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_44 0x40C9664
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_45 0x40C9668
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_46 0x40C966C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_47 0x40C9670
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_48 0x40C9674
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_49 0x40C9678
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_50 0x40C967C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_51 0x40C9680
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_52 0x40C9684
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_53 0x40C9688
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_54 0x40C968C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_55 0x40C9690
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_56 0x40C9694
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_57 0x40C9698
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_58 0x40C969C
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_59 0x40C96A0
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_60 0x40C96A4
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_61 0x40C96A8
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_62 0x40C96AC
+
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_63 0x40C96B0
+
+#endif /* ASIC_REG_DCORE0_MME_QM_ARC_DUP_ENG_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_axuser_nonsecured_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_axuser_nonsecured_regs.h
new file mode 100644
index 000000000000..32089b8250ed
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_axuser_nonsecured_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_MME_QM_AXUSER_NONSECURED_REGS_H_
+#define ASIC_REG_DCORE0_MME_QM_AXUSER_NONSECURED_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_MME_QM_AXUSER_NONSECURED
+ *   (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_ASID 0x40CAB80
+
+#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_MMU_BP 0x40CAB84
+
+#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_STRONG_ORDER 0x40CAB88
+
+#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_NO_SNOOP 0x40CAB8C
+
+#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_WR_REDUCTION 0x40CAB90
+
+#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_RD_ATOMIC 0x40CAB94
+
+#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_QOS 0x40CAB98
+
+#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_RSVD 0x40CAB9C
+
+#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_EMEM_CPAGE 0x40CABA0
+
+#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_CORE 0x40CABA4
+
+#define mmDCORE0_MME_QM_AXUSER_NONSECURED_E2E_COORD 0x40CABA8
+
+#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_WR_OVRD_LO 0x40CABB0
+
+#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_WR_OVRD_HI 0x40CABB4
+
+#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_RD_OVRD_LO 0x40CABB8
+
+#define mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_RD_OVRD_HI 0x40CABBC
+
+#define mmDCORE0_MME_QM_AXUSER_NONSECURED_LB_COORD 0x40CABC0
+
+#define mmDCORE0_MME_QM_AXUSER_NONSECURED_LB_LOCK 0x40CABC4
+
+#define mmDCORE0_MME_QM_AXUSER_NONSECURED_LB_RSVD 0x40CABC8
+
+#define mmDCORE0_MME_QM_AXUSER_NONSECURED_LB_OVRD 0x40CABCC
+
+#endif /* ASIC_REG_DCORE0_MME_QM_AXUSER_NONSECURED_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_axuser_secured_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_axuser_secured_regs.h
new file mode 100644
index 000000000000..e168c1cc2a7d
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_axuser_secured_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_MME_QM_AXUSER_SECURED_REGS_H_
+#define ASIC_REG_DCORE0_MME_QM_AXUSER_SECURED_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_MME_QM_AXUSER_SECURED
+ *   (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_ASID 0x40CAB00
+
+#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_MMU_BP 0x40CAB04
+
+#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_STRONG_ORDER 0x40CAB08
+
+#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_NO_SNOOP 0x40CAB0C
+
+#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_WR_REDUCTION 0x40CAB10
+
+#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_RD_ATOMIC 0x40CAB14
+
+#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_QOS 0x40CAB18
+
+#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_RSVD 0x40CAB1C
+
+#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_EMEM_CPAGE 0x40CAB20
+
+#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_CORE 0x40CAB24
+
+#define mmDCORE0_MME_QM_AXUSER_SECURED_E2E_COORD 0x40CAB28
+
+#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_WR_OVRD_LO 0x40CAB30
+
+#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_WR_OVRD_HI 0x40CAB34
+
+#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_RD_OVRD_LO 0x40CAB38
+
+#define mmDCORE0_MME_QM_AXUSER_SECURED_HB_RD_OVRD_HI 0x40CAB3C
+
+#define mmDCORE0_MME_QM_AXUSER_SECURED_LB_COORD 0x40CAB40
+
+#define mmDCORE0_MME_QM_AXUSER_SECURED_LB_LOCK 0x40CAB44
+
+#define mmDCORE0_MME_QM_AXUSER_SECURED_LB_RSVD 0x40CAB48
+
+#define mmDCORE0_MME_QM_AXUSER_SECURED_LB_OVRD 0x40CAB4C
+
+#endif /* ASIC_REG_DCORE0_MME_QM_AXUSER_SECURED_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_cgm_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_cgm_regs.h
new file mode 100644
index 000000000000..543aba18ef68
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_cgm_regs.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_MME_QM_CGM_REGS_H_
+#define ASIC_REG_DCORE0_MME_QM_CGM_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_MME_QM_CGM
+ *   (Prototype: QMAN_CGM)
+ *****************************************
+ */
+
+#define mmDCORE0_MME_QM_CGM_CFG 0x40CAD80
+
+#define mmDCORE0_MME_QM_CGM_STS 0x40CAD84
+
+#define mmDCORE0_MME_QM_CGM_CFG1 0x40CAD88
+
+#endif /* ASIC_REG_DCORE0_MME_QM_CGM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_regs.h
new file mode 100644
index 000000000000..c45583fcc2cf
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_regs.h
@@ -0,0 +1,1057 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_MME_QM_REGS_H_
+#define ASIC_REG_DCORE0_MME_QM_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_MME_QM
+ *   (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmDCORE0_MME_QM_GLBL_CFG0 0x40CA000
+
+#define mmDCORE0_MME_QM_GLBL_CFG1 0x40CA004
+
+#define mmDCORE0_MME_QM_GLBL_CFG2 0x40CA008
+
+#define mmDCORE0_MME_QM_GLBL_ERR_CFG 0x40CA00C
+
+#define mmDCORE0_MME_QM_GLBL_ERR_CFG1 0x40CA010
+
+#define mmDCORE0_MME_QM_GLBL_ERR_ARC_HALT_EN 0x40CA014
+
+#define mmDCORE0_MME_QM_GLBL_AXCACHE 0x40CA018
+
+#define mmDCORE0_MME_QM_GLBL_STS0 0x40CA01C
+
+#define mmDCORE0_MME_QM_GLBL_STS1 0x40CA020
+
+#define mmDCORE0_MME_QM_GLBL_ERR_STS_0 0x40CA024
+
+#define mmDCORE0_MME_QM_GLBL_ERR_STS_1 0x40CA028
+
+#define mmDCORE0_MME_QM_GLBL_ERR_STS_2 0x40CA02C
+
+#define mmDCORE0_MME_QM_GLBL_ERR_STS_3 0x40CA030
+
+#define mmDCORE0_MME_QM_GLBL_ERR_STS_4 0x40CA034
+
+#define mmDCORE0_MME_QM_GLBL_ERR_MSG_EN_0 0x40CA038
+
+#define mmDCORE0_MME_QM_GLBL_ERR_MSG_EN_1 0x40CA03C
+
+#define mmDCORE0_MME_QM_GLBL_ERR_MSG_EN_2 0x40CA040
+
+#define mmDCORE0_MME_QM_GLBL_ERR_MSG_EN_3 0x40CA044
+
+#define mmDCORE0_MME_QM_GLBL_ERR_MSG_EN_4 0x40CA048
+
+#define mmDCORE0_MME_QM_GLBL_PROT 0x40CA04C
+
+#define mmDCORE0_MME_QM_PQ_BASE_LO_0 0x40CA050
+
+#define mmDCORE0_MME_QM_PQ_BASE_LO_1 0x40CA054
+
+#define mmDCORE0_MME_QM_PQ_BASE_LO_2 0x40CA058
+
+#define mmDCORE0_MME_QM_PQ_BASE_LO_3 0x40CA05C
+
+#define mmDCORE0_MME_QM_PQ_BASE_HI_0 0x40CA060
+
+#define mmDCORE0_MME_QM_PQ_BASE_HI_1 0x40CA064
+
+#define mmDCORE0_MME_QM_PQ_BASE_HI_2 0x40CA068
+
+#define mmDCORE0_MME_QM_PQ_BASE_HI_3 0x40CA06C
+
+#define mmDCORE0_MME_QM_PQ_SIZE_0 0x40CA070
+
+#define mmDCORE0_MME_QM_PQ_SIZE_1 0x40CA074
+
+#define mmDCORE0_MME_QM_PQ_SIZE_2 0x40CA078
+
+#define mmDCORE0_MME_QM_PQ_SIZE_3 0x40CA07C
+
+#define mmDCORE0_MME_QM_PQ_PI_0 0x40CA080
+
+#define mmDCORE0_MME_QM_PQ_PI_1 0x40CA084
+
+#define mmDCORE0_MME_QM_PQ_PI_2 0x40CA088
+
+#define mmDCORE0_MME_QM_PQ_PI_3 0x40CA08C
+
+#define mmDCORE0_MME_QM_PQ_CI_0 0x40CA090
+
+#define mmDCORE0_MME_QM_PQ_CI_1 0x40CA094
+
+#define mmDCORE0_MME_QM_PQ_CI_2 0x40CA098
+
+#define mmDCORE0_MME_QM_PQ_CI_3 0x40CA09C
+
+#define mmDCORE0_MME_QM_PQ_CFG0_0 0x40CA0A0
+
+#define mmDCORE0_MME_QM_PQ_CFG0_1 0x40CA0A4
+
+#define mmDCORE0_MME_QM_PQ_CFG0_2 0x40CA0A8
+
+#define mmDCORE0_MME_QM_PQ_CFG0_3 0x40CA0AC
+
+#define mmDCORE0_MME_QM_PQ_CFG1_0 0x40CA0B0
+
+#define mmDCORE0_MME_QM_PQ_CFG1_1 0x40CA0B4
+
+#define mmDCORE0_MME_QM_PQ_CFG1_2 0x40CA0B8
+
+#define mmDCORE0_MME_QM_PQ_CFG1_3 0x40CA0BC
+
+#define mmDCORE0_MME_QM_PQ_STS0_0 0x40CA0C0
+
+#define mmDCORE0_MME_QM_PQ_STS0_1 0x40CA0C4
+
+#define mmDCORE0_MME_QM_PQ_STS0_2 0x40CA0C8
+
+#define mmDCORE0_MME_QM_PQ_STS0_3 0x40CA0CC
+
+#define mmDCORE0_MME_QM_PQ_STS1_0 0x40CA0D0
+
+#define mmDCORE0_MME_QM_PQ_STS1_1 0x40CA0D4
+
+#define mmDCORE0_MME_QM_PQ_STS1_2 0x40CA0D8
+
+#define mmDCORE0_MME_QM_PQ_STS1_3 0x40CA0DC
+
+#define mmDCORE0_MME_QM_CQ_CFG0_0 0x40CA0E0
+
+#define mmDCORE0_MME_QM_CQ_CFG0_1 0x40CA0E4
+
+#define mmDCORE0_MME_QM_CQ_CFG0_2 0x40CA0E8
+
+#define mmDCORE0_MME_QM_CQ_CFG0_3 0x40CA0EC
+
+#define mmDCORE0_MME_QM_CQ_CFG0_4 0x40CA0F0
+
+#define mmDCORE0_MME_QM_CQ_STS0_0 0x40CA0F4
+
+#define mmDCORE0_MME_QM_CQ_STS0_1 0x40CA0F8
+
+#define mmDCORE0_MME_QM_CQ_STS0_2 0x40CA0FC
+
+#define mmDCORE0_MME_QM_CQ_STS0_3 0x40CA100
+
+#define mmDCORE0_MME_QM_CQ_STS0_4 0x40CA104
+
+#define mmDCORE0_MME_QM_CQ_CFG1_0 0x40CA108
+
+#define mmDCORE0_MME_QM_CQ_CFG1_1 0x40CA10C
+
+#define mmDCORE0_MME_QM_CQ_CFG1_2 0x40CA110
+
+#define mmDCORE0_MME_QM_CQ_CFG1_3 0x40CA114
+
+#define mmDCORE0_MME_QM_CQ_CFG1_4 0x40CA118
+
+#define mmDCORE0_MME_QM_CQ_STS1_0 0x40CA11C
+
+#define mmDCORE0_MME_QM_CQ_STS1_1 0x40CA120
+
+#define mmDCORE0_MME_QM_CQ_STS1_2 0x40CA124
+
+#define mmDCORE0_MME_QM_CQ_STS1_3 0x40CA128
+
+#define mmDCORE0_MME_QM_CQ_STS1_4 0x40CA12C
+
+#define mmDCORE0_MME_QM_CQ_PTR_LO_0 0x40CA150
+
+#define mmDCORE0_MME_QM_CQ_PTR_HI_0 0x40CA154
+
+#define mmDCORE0_MME_QM_CQ_TSIZE_0 0x40CA158
+
+#define mmDCORE0_MME_QM_CQ_CTL_0 0x40CA15C
+
+#define mmDCORE0_MME_QM_CQ_PTR_LO_1 0x40CA160
+
+#define mmDCORE0_MME_QM_CQ_PTR_HI_1 0x40CA164
+
+#define mmDCORE0_MME_QM_CQ_TSIZE_1 0x40CA168
+
+#define mmDCORE0_MME_QM_CQ_CTL_1 0x40CA16C
+
+#define mmDCORE0_MME_QM_CQ_PTR_LO_2 0x40CA170
+
+#define mmDCORE0_MME_QM_CQ_PTR_HI_2 0x40CA174
+
+#define mmDCORE0_MME_QM_CQ_TSIZE_2 0x40CA178
+
+#define mmDCORE0_MME_QM_CQ_CTL_2 0x40CA17C
+
+#define mmDCORE0_MME_QM_CQ_PTR_LO_3 0x40CA180
+
+#define mmDCORE0_MME_QM_CQ_PTR_HI_3 0x40CA184
+
+#define mmDCORE0_MME_QM_CQ_TSIZE_3 0x40CA188
+
+#define mmDCORE0_MME_QM_CQ_CTL_3 0x40CA18C
+
+#define mmDCORE0_MME_QM_CQ_PTR_LO_4 0x40CA190
+
+#define mmDCORE0_MME_QM_CQ_PTR_HI_4 0x40CA194
+
+#define mmDCORE0_MME_QM_CQ_TSIZE_4 0x40CA198
+
+#define mmDCORE0_MME_QM_CQ_CTL_4 0x40CA19C
+
+#define mmDCORE0_MME_QM_CQ_TSIZE_STS_0 0x40CA1A0
+
+#define mmDCORE0_MME_QM_CQ_TSIZE_STS_1 0x40CA1A4
+
+#define mmDCORE0_MME_QM_CQ_TSIZE_STS_2 0x40CA1A8
+
+#define mmDCORE0_MME_QM_CQ_TSIZE_STS_3 0x40CA1AC
+
+#define mmDCORE0_MME_QM_CQ_TSIZE_STS_4 0x40CA1B0
+
+#define mmDCORE0_MME_QM_CQ_PTR_LO_STS_0 0x40CA1B4
+
+#define mmDCORE0_MME_QM_CQ_PTR_LO_STS_1 0x40CA1B8
+
+#define mmDCORE0_MME_QM_CQ_PTR_LO_STS_2 0x40CA1BC
+
+#define mmDCORE0_MME_QM_CQ_PTR_LO_STS_3 0x40CA1C0
+
+#define mmDCORE0_MME_QM_CQ_PTR_LO_STS_4 0x40CA1C4
+
+#define mmDCORE0_MME_QM_CQ_PTR_HI_STS_0 0x40CA1C8
+
+#define mmDCORE0_MME_QM_CQ_PTR_HI_STS_1 0x40CA1CC
+
+#define mmDCORE0_MME_QM_CQ_PTR_HI_STS_2 0x40CA1D0
+
+#define mmDCORE0_MME_QM_CQ_PTR_HI_STS_3 0x40CA1D4
+
+#define mmDCORE0_MME_QM_CQ_PTR_HI_STS_4 0x40CA1D8
+
+#define mmDCORE0_MME_QM_CQ_IFIFO_STS_0 0x40CA1DC
+
+#define mmDCORE0_MME_QM_CQ_IFIFO_STS_1 0x40CA1E0
+
+#define mmDCORE0_MME_QM_CQ_IFIFO_STS_2 0x40CA1E4
+
+#define mmDCORE0_MME_QM_CQ_IFIFO_STS_3 0x40CA1E8
+
+#define mmDCORE0_MME_QM_CQ_IFIFO_STS_4 0x40CA1EC
+
+#define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_0 0x40CA1F0
+
+#define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_1 0x40CA1F4
+
+#define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_2 0x40CA1F8
+
+#define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_3 0x40CA1FC
+
+#define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_4 0x40CA200
+
+#define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_0 0x40CA204
+
+#define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_1 0x40CA208
+
+#define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_2 0x40CA20C
+
+#define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_3 0x40CA210
+
+#define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_4 0x40CA214
+
+#define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_0 0x40CA218
+
+#define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_1 0x40CA21C
+
+#define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_2 0x40CA220
+
+#define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_3 0x40CA224
+
+#define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_4 0x40CA228
+
+#define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_0 0x40CA22C
+
+#define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_1 0x40CA230
+
+#define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_2 0x40CA234
+
+#define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_3 0x40CA238
+
+#define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_4 0x40CA23C
+
+#define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_0 0x40CA240
+
+#define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_1 0x40CA244
+
+#define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_2 0x40CA248
+
+#define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_3 0x40CA24C
+
+#define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_4 0x40CA250
+
+#define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_0 0x40CA254
+
+#define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_1 0x40CA258
+
+#define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_2 0x40CA25C
+
+#define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_3 0x40CA260
+
+#define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_4 0x40CA264
+
+#define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_0 0x40CA268
+
+#define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_1 0x40CA26C
+
+#define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_2 0x40CA270
+
+#define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_3 0x40CA274
+
+#define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_4 0x40CA278
+
+#define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_0 0x40CA27C
+
+#define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_1 0x40CA280
+
+#define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_2 0x40CA284
+
+#define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_3 0x40CA288
+
+#define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_4 0x40CA28C
+
+#define mmDCORE0_MME_QM_CP_FENCE0_RDATA_0 0x40CA290
+
+#define mmDCORE0_MME_QM_CP_FENCE0_RDATA_1 0x40CA294
+
+#define mmDCORE0_MME_QM_CP_FENCE0_RDATA_2 0x40CA298
+
+#define mmDCORE0_MME_QM_CP_FENCE0_RDATA_3 0x40CA29C
+
+#define mmDCORE0_MME_QM_CP_FENCE0_RDATA_4 0x40CA2A0
+
+#define mmDCORE0_MME_QM_CP_FENCE1_RDATA_0 0x40CA2A4
+
+#define mmDCORE0_MME_QM_CP_FENCE1_RDATA_1 0x40CA2A8
+
+#define mmDCORE0_MME_QM_CP_FENCE1_RDATA_2 0x40CA2AC
+
+#define mmDCORE0_MME_QM_CP_FENCE1_RDATA_3 0x40CA2B0
+
+#define mmDCORE0_MME_QM_CP_FENCE1_RDATA_4 0x40CA2B4
+
+#define mmDCORE0_MME_QM_CP_FENCE2_RDATA_0 0x40CA2B8
+
+#define mmDCORE0_MME_QM_CP_FENCE2_RDATA_1 0x40CA2BC
+
+#define mmDCORE0_MME_QM_CP_FENCE2_RDATA_2 0x40CA2C0
+
+#define mmDCORE0_MME_QM_CP_FENCE2_RDATA_3 0x40CA2C4
+
+#define mmDCORE0_MME_QM_CP_FENCE2_RDATA_4 0x40CA2C8
+
+#define mmDCORE0_MME_QM_CP_FENCE3_RDATA_0 0x40CA2CC
+
+#define mmDCORE0_MME_QM_CP_FENCE3_RDATA_1 0x40CA2D0
+
+#define mmDCORE0_MME_QM_CP_FENCE3_RDATA_2 0x40CA2D4
+
+#define mmDCORE0_MME_QM_CP_FENCE3_RDATA_3 0x40CA2D8
+
+#define mmDCORE0_MME_QM_CP_FENCE3_RDATA_4 0x40CA2DC
+
+#define mmDCORE0_MME_QM_CP_FENCE0_CNT_0 0x40CA2E0
+
+#define mmDCORE0_MME_QM_CP_FENCE0_CNT_1 0x40CA2E4
+
+#define mmDCORE0_MME_QM_CP_FENCE0_CNT_2 0x40CA2E8
+
+#define mmDCORE0_MME_QM_CP_FENCE0_CNT_3 0x40CA2EC
+
+#define mmDCORE0_MME_QM_CP_FENCE0_CNT_4 0x40CA2F0
+
+#define mmDCORE0_MME_QM_CP_FENCE1_CNT_0 0x40CA2F4
+
+#define mmDCORE0_MME_QM_CP_FENCE1_CNT_1 0x40CA2F8
+
+#define mmDCORE0_MME_QM_CP_FENCE1_CNT_2 0x40CA2FC
+
+#define mmDCORE0_MME_QM_CP_FENCE1_CNT_3 0x40CA300
+
+#define mmDCORE0_MME_QM_CP_FENCE1_CNT_4 0x40CA304
+
+#define mmDCORE0_MME_QM_CP_FENCE2_CNT_0 0x40CA308
+
+#define mmDCORE0_MME_QM_CP_FENCE2_CNT_1 0x40CA30C
+
+#define mmDCORE0_MME_QM_CP_FENCE2_CNT_2 0x40CA310
+
+#define mmDCORE0_MME_QM_CP_FENCE2_CNT_3 0x40CA314
+
+#define mmDCORE0_MME_QM_CP_FENCE2_CNT_4 0x40CA318
+
+#define mmDCORE0_MME_QM_CP_FENCE3_CNT_0 0x40CA31C
+
+#define mmDCORE0_MME_QM_CP_FENCE3_CNT_1 0x40CA320
+
+#define mmDCORE0_MME_QM_CP_FENCE3_CNT_2 0x40CA324
+
+#define mmDCORE0_MME_QM_CP_FENCE3_CNT_3 0x40CA328
+
+#define mmDCORE0_MME_QM_CP_FENCE3_CNT_4 0x40CA32C
+
+#define mmDCORE0_MME_QM_CP_BARRIER_CFG 0x40CA330
+
+#define mmDCORE0_MME_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0x40CA334
+
+#define mmDCORE0_MME_QM_CP_LDMA_DST_BASE_LO_OFFSET 0x40CA338
+
+#define mmDCORE0_MME_QM_CP_LDMA_TSIZE_OFFSET 0x40CA33C
+
+#define mmDCORE0_MME_QM_CP_CQ_PTR_LO_OFFSET_0 0x40CA340
+
+#define mmDCORE0_MME_QM_CP_CQ_PTR_LO_OFFSET_1 0x40CA344
+
+#define mmDCORE0_MME_QM_CP_CQ_PTR_LO_OFFSET_2 0x40CA348
+
+#define mmDCORE0_MME_QM_CP_CQ_PTR_LO_OFFSET_3 0x40CA34C
+
+#define mmDCORE0_MME_QM_CP_CQ_PTR_LO_OFFSET_4 0x40CA350
+
+#define mmDCORE0_MME_QM_CP_STS_0 0x40CA368
+
+#define mmDCORE0_MME_QM_CP_STS_1 0x40CA36C
+
+#define mmDCORE0_MME_QM_CP_STS_2 0x40CA370
+
+#define mmDCORE0_MME_QM_CP_STS_3 0x40CA374
+
+#define mmDCORE0_MME_QM_CP_STS_4 0x40CA378
+
+#define mmDCORE0_MME_QM_CP_CURRENT_INST_LO_0 0x40CA37C
+
+#define mmDCORE0_MME_QM_CP_CURRENT_INST_LO_1 0x40CA380
+
+#define mmDCORE0_MME_QM_CP_CURRENT_INST_LO_2 0x40CA384
+
+#define mmDCORE0_MME_QM_CP_CURRENT_INST_LO_3 0x40CA388
+
+#define mmDCORE0_MME_QM_CP_CURRENT_INST_LO_4 0x40CA38C
+
+#define mmDCORE0_MME_QM_CP_CURRENT_INST_HI_0 0x40CA390
+
+#define mmDCORE0_MME_QM_CP_CURRENT_INST_HI_1 0x40CA394
+
+#define mmDCORE0_MME_QM_CP_CURRENT_INST_HI_2 0x40CA398
+
+#define mmDCORE0_MME_QM_CP_CURRENT_INST_HI_3 0x40CA39C
+
+#define mmDCORE0_MME_QM_CP_CURRENT_INST_HI_4 0x40CA3A0
+
+#define mmDCORE0_MME_QM_CP_PRED_0 0x40CA3A4
+
+#define mmDCORE0_MME_QM_CP_PRED_1 0x40CA3A8
+
+#define mmDCORE0_MME_QM_CP_PRED_2 0x40CA3AC
+
+#define mmDCORE0_MME_QM_CP_PRED_3 0x40CA3B0
+
+#define mmDCORE0_MME_QM_CP_PRED_4 0x40CA3B4
+
+#define mmDCORE0_MME_QM_CP_PRED_UPEN_0 0x40CA3B8
+
+#define mmDCORE0_MME_QM_CP_PRED_UPEN_1 0x40CA3BC
+
+#define mmDCORE0_MME_QM_CP_PRED_UPEN_2 0x40CA3C0
+
+#define mmDCORE0_MME_QM_CP_PRED_UPEN_3 0x40CA3C4
+
+#define mmDCORE0_MME_QM_CP_PRED_UPEN_4 0x40CA3C8
+
+#define mmDCORE0_MME_QM_CP_DBG_0_0 0x40CA3CC
+
+#define mmDCORE0_MME_QM_CP_DBG_0_1 0x40CA3D0
+
+#define mmDCORE0_MME_QM_CP_DBG_0_2 0x40CA3D4
+
+#define mmDCORE0_MME_QM_CP_DBG_0_3 0x40CA3D8
+
+#define mmDCORE0_MME_QM_CP_DBG_0_4 0x40CA3DC
+
+#define mmDCORE0_MME_QM_CP_CPDMA_UP_CRED_0 0x40CA3E0
+
+#define mmDCORE0_MME_QM_CP_CPDMA_UP_CRED_1 0x40CA3E4
+
+#define mmDCORE0_MME_QM_CP_CPDMA_UP_CRED_2 0x40CA3E8
+
+#define mmDCORE0_MME_QM_CP_CPDMA_UP_CRED_3 0x40CA3EC
+
+#define mmDCORE0_MME_QM_CP_CPDMA_UP_CRED_4 0x40CA3F0
+
+#define mmDCORE0_MME_QM_CP_IN_DATA_LO_0 0x40CA3F4
+
+#define mmDCORE0_MME_QM_CP_IN_DATA_LO_1 0x40CA3F8
+
+#define mmDCORE0_MME_QM_CP_IN_DATA_LO_2 0x40CA3FC
+
+#define mmDCORE0_MME_QM_CP_IN_DATA_LO_3 0x40CA400
+
+#define mmDCORE0_MME_QM_CP_IN_DATA_LO_4 0x40CA404
+
+#define mmDCORE0_MME_QM_CP_IN_DATA_HI_0 0x40CA408
+
+#define mmDCORE0_MME_QM_CP_IN_DATA_HI_1 0x40CA40C
+
+#define mmDCORE0_MME_QM_CP_IN_DATA_HI_2 0x40CA410
+
+#define mmDCORE0_MME_QM_CP_IN_DATA_HI_3 0x40CA414
+
+#define mmDCORE0_MME_QM_CP_IN_DATA_HI_4 0x40CA418
+
+#define mmDCORE0_MME_QM_PQC_HBW_BASE_LO_0 0x40CA41C
+
+#define mmDCORE0_MME_QM_PQC_HBW_BASE_LO_1 0x40CA420
+
+#define mmDCORE0_MME_QM_PQC_HBW_BASE_LO_2 0x40CA424
+
+#define mmDCORE0_MME_QM_PQC_HBW_BASE_LO_3 0x40CA428
+
+#define mmDCORE0_MME_QM_PQC_HBW_BASE_HI_0 0x40CA42C
+
+#define mmDCORE0_MME_QM_PQC_HBW_BASE_HI_1 0x40CA430
+
+#define mmDCORE0_MME_QM_PQC_HBW_BASE_HI_2 0x40CA434
+
+#define mmDCORE0_MME_QM_PQC_HBW_BASE_HI_3 0x40CA438
+
+#define mmDCORE0_MME_QM_PQC_SIZE_0 0x40CA43C
+
+#define mmDCORE0_MME_QM_PQC_SIZE_1 0x40CA440
+
+#define mmDCORE0_MME_QM_PQC_SIZE_2 0x40CA444
+
+#define mmDCORE0_MME_QM_PQC_SIZE_3 0x40CA448
+
+#define mmDCORE0_MME_QM_PQC_PI_0 0x40CA44C
+
+#define mmDCORE0_MME_QM_PQC_PI_1 0x40CA450
+
+#define mmDCORE0_MME_QM_PQC_PI_2 0x40CA454
+
+#define mmDCORE0_MME_QM_PQC_PI_3 0x40CA458
+
+#define mmDCORE0_MME_QM_PQC_LBW_WDATA_0 0x40CA45C
+
+#define mmDCORE0_MME_QM_PQC_LBW_WDATA_1 0x40CA460
+
+#define mmDCORE0_MME_QM_PQC_LBW_WDATA_2 0x40CA464
+
+#define mmDCORE0_MME_QM_PQC_LBW_WDATA_3 0x40CA468
+
+#define mmDCORE0_MME_QM_PQC_LBW_BASE_LO_0 0x40CA46C
+
+#define mmDCORE0_MME_QM_PQC_LBW_BASE_LO_1 0x40CA470
+
+#define mmDCORE0_MME_QM_PQC_LBW_BASE_LO_2 0x40CA474
+
+#define mmDCORE0_MME_QM_PQC_LBW_BASE_LO_3 0x40CA478
+
+#define mmDCORE0_MME_QM_PQC_LBW_BASE_HI_0 0x40CA47C
+
+#define mmDCORE0_MME_QM_PQC_LBW_BASE_HI_1 0x40CA480
+
+#define mmDCORE0_MME_QM_PQC_LBW_BASE_HI_2 0x40CA484
+
+#define mmDCORE0_MME_QM_PQC_LBW_BASE_HI_3 0x40CA488
+
+#define mmDCORE0_MME_QM_PQC_CFG 0x40CA48C
+
+#define mmDCORE0_MME_QM_PQC_SECURE_PUSH_IND 0x40CA490
+
+#define mmDCORE0_MME_QM_ARB_MASK 0x40CA4A0
+
+#define mmDCORE0_MME_QM_ARB_CFG_0 0x40CA4A4
+
+#define mmDCORE0_MME_QM_ARB_CHOICE_Q_PUSH 0x40CA4A8
+
+#define mmDCORE0_MME_QM_ARB_WRR_WEIGHT_0 0x40CA4AC
+
+#define mmDCORE0_MME_QM_ARB_WRR_WEIGHT_1 0x40CA4B0
+
+#define mmDCORE0_MME_QM_ARB_WRR_WEIGHT_2 0x40CA4B4
+
+#define mmDCORE0_MME_QM_ARB_WRR_WEIGHT_3 0x40CA4B8
+
+#define mmDCORE0_MME_QM_ARB_CFG_1 0x40CA4BC
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_0 0x40CA4C0
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_1 0x40CA4C4
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_2 0x40CA4C8
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_3 0x40CA4CC
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_4 0x40CA4D0
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_5 0x40CA4D4
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_6 0x40CA4D8
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_7 0x40CA4DC
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_8 0x40CA4E0
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_9 0x40CA4E4
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_10 0x40CA4E8
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_11 0x40CA4EC
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_12 0x40CA4F0
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_13 0x40CA4F4
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_14 0x40CA4F8
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_15 0x40CA4FC
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_16 0x40CA500
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_17 0x40CA504
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_18 0x40CA508
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_19 0x40CA50C
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_20 0x40CA510
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_21 0x40CA514
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_22 0x40CA518
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_23 0x40CA51C
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_24 0x40CA520
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_25 0x40CA524
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_26 0x40CA528
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_27 0x40CA52C
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_28 0x40CA530
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_29 0x40CA534
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_30 0x40CA538
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_31 0x40CA53C
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_32 0x40CA540
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_33 0x40CA544
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_34 0x40CA548
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_35 0x40CA54C
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_36 0x40CA550
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_37 0x40CA554
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_38 0x40CA558
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_39 0x40CA55C
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_40 0x40CA560
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_41 0x40CA564
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_42 0x40CA568
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_43 0x40CA56C
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_44 0x40CA570
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_45 0x40CA574
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_46 0x40CA578
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_47 0x40CA57C
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_48 0x40CA580
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_49 0x40CA584
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_50 0x40CA588
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_51 0x40CA58C
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_52 0x40CA590
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_53 0x40CA594
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_54 0x40CA598
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_55 0x40CA59C
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_56 0x40CA5A0
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_57 0x40CA5A4
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_58 0x40CA5A8
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_59 0x40CA5AC
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_60 0x40CA5B0
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_61 0x40CA5B4
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_62 0x40CA5B8
+
+#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_63 0x40CA5BC
+
+#define mmDCORE0_MME_QM_ARB_MST_CRED_INC 0x40CA5E0
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_0 0x40CA5E4
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_1 0x40CA5E8
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_2 0x40CA5EC
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_3 0x40CA5F0
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_4 0x40CA5F4
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_5 0x40CA5F8
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_6 0x40CA5FC
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_7 0x40CA600
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_8 0x40CA604
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_9 0x40CA608
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_10 0x40CA60C
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_11 0x40CA610
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_12 0x40CA614
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_13 0x40CA618
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_14 0x40CA61C
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_15 0x40CA620
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_16 0x40CA624
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_17 0x40CA628
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_18 0x40CA62C
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_19 0x40CA630
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_20 0x40CA634
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_21 0x40CA638
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_22 0x40CA63C
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_23 0x40CA640
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_24 0x40CA644
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_25 0x40CA648
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_26 0x40CA64C
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_27 0x40CA650
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_28 0x40CA654
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_29 0x40CA658
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_30 0x40CA65C
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_31 0x40CA660
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_32 0x40CA664
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_33 0x40CA668
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_34 0x40CA66C
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_35 0x40CA670
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_36 0x40CA674
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_37 0x40CA678
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_38 0x40CA67C
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_39 0x40CA680
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_40 0x40CA684
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_41 0x40CA688
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_42 0x40CA68C
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_43 0x40CA690
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_44 0x40CA694
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_45 0x40CA698
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_46 0x40CA69C
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_47 0x40CA6A0
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_48 0x40CA6A4
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_49 0x40CA6A8
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_50 0x40CA6AC
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_51 0x40CA6B0
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_52 0x40CA6B4
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_53 0x40CA6B8
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_54 0x40CA6BC
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_55 0x40CA6C0
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_56 0x40CA6C4
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_57 0x40CA6C8
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_58 0x40CA6CC
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_59 0x40CA6D0
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_60 0x40CA6D4
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_61 0x40CA6D8
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_62 0x40CA6DC
+
+#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_63 0x40CA6E0
+
+#define mmDCORE0_MME_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x40CA704
+
+#define mmDCORE0_MME_QM_ARB_MST_SLAVE_EN 0x40CA708
+
+#define mmDCORE0_MME_QM_ARB_MST_SLAVE_EN_1 0x40CA70C
+
+#define mmDCORE0_MME_QM_ARB_SLV_CHOICE_WDT 0x40CA710
+
+#define mmDCORE0_MME_QM_ARB_SLV_ID 0x40CA714
+
+#define mmDCORE0_MME_QM_ARB_MST_QUIET_PER 0x40CA718
+
+#define mmDCORE0_MME_QM_ARB_MSG_MAX_INFLIGHT 0x40CA744
+
+#define mmDCORE0_MME_QM_ARB_BASE_LO 0x40CA754
+
+#define mmDCORE0_MME_QM_ARB_BASE_HI 0x40CA758
+
+#define mmDCORE0_MME_QM_ARB_STATE_STS 0x40CA780
+
+#define mmDCORE0_MME_QM_ARB_CHOICE_FULLNESS_STS 0x40CA784
+
+#define mmDCORE0_MME_QM_ARB_MSG_STS 0x40CA788
+
+#define mmDCORE0_MME_QM_ARB_SLV_CHOICE_Q_HEAD 0x40CA78C
+
+#define mmDCORE0_MME_QM_ARB_ERR_CAUSE 0x40CA79C
+
+#define mmDCORE0_MME_QM_ARB_ERR_MSG_EN 0x40CA7A0
+
+#define mmDCORE0_MME_QM_ARB_ERR_STS_DRP 0x40CA7A8
+
+#define mmDCORE0_MME_QM_ARB_MST_CRED_STS 0x40CA7B0
+
+#define mmDCORE0_MME_QM_ARB_MST_CRED_STS_1 0x40CA7B4
+
+#define mmDCORE0_MME_QM_CSMR_STRICT_PRIO_CFG 0x40CA7FC
+
+#define mmDCORE0_MME_QM_ARC_CQ_CFG0 0x40CA800
+
+#define mmDCORE0_MME_QM_ARC_CQ_CFG1 0x40CA804
+
+#define mmDCORE0_MME_QM_ARC_CQ_PTR_LO 0x40CA808
+
+#define mmDCORE0_MME_QM_ARC_CQ_PTR_HI 0x40CA80C
+
+#define mmDCORE0_MME_QM_ARC_CQ_TSIZE 0x40CA810
+
+#define mmDCORE0_MME_QM_ARC_CQ_CTL 0x40CA814
+
+#define mmDCORE0_MME_QM_ARC_CQ_IFIFO_STS 0x40CA81C
+
+#define mmDCORE0_MME_QM_ARC_CQ_STS0 0x40CA820
+
+#define mmDCORE0_MME_QM_ARC_CQ_STS1 0x40CA824
+
+#define mmDCORE0_MME_QM_ARC_CQ_TSIZE_STS 0x40CA828
+
+#define mmDCORE0_MME_QM_ARC_CQ_PTR_LO_STS 0x40CA82C
+
+#define mmDCORE0_MME_QM_ARC_CQ_PTR_HI_STS 0x40CA830
+
+#define mmDCORE0_MME_QM_CP_WR_ARC_ADDR_HI 0x40CA834
+
+#define mmDCORE0_MME_QM_CP_WR_ARC_ADDR_LO 0x40CA838
+
+#define mmDCORE0_MME_QM_ARC_CQ_IFIFO_MSG_BASE_HI 0x40CA83C
+
+#define mmDCORE0_MME_QM_ARC_CQ_IFIFO_MSG_BASE_LO 0x40CA840
+
+#define mmDCORE0_MME_QM_ARC_CQ_CTL_MSG_BASE_HI 0x40CA844
+
+#define mmDCORE0_MME_QM_ARC_CQ_CTL_MSG_BASE_LO 0x40CA848
+
+#define mmDCORE0_MME_QM_CQ_IFIFO_MSG_BASE_HI 0x40CA84C
+
+#define mmDCORE0_MME_QM_CQ_IFIFO_MSG_BASE_LO 0x40CA850
+
+#define mmDCORE0_MME_QM_CQ_CTL_MSG_BASE_HI 0x40CA854
+
+#define mmDCORE0_MME_QM_CQ_CTL_MSG_BASE_LO 0x40CA858
+
+#define mmDCORE0_MME_QM_ADDR_OVRD 0x40CA85C
+
+#define mmDCORE0_MME_QM_CQ_IFIFO_CI_0 0x40CA860
+
+#define mmDCORE0_MME_QM_CQ_IFIFO_CI_1 0x40CA864
+
+#define mmDCORE0_MME_QM_CQ_IFIFO_CI_2 0x40CA868
+
+#define mmDCORE0_MME_QM_CQ_IFIFO_CI_3 0x40CA86C
+
+#define mmDCORE0_MME_QM_CQ_IFIFO_CI_4 0x40CA870
+
+#define mmDCORE0_MME_QM_ARC_CQ_IFIFO_CI 0x40CA874
+
+#define mmDCORE0_MME_QM_CQ_CTL_CI_0 0x40CA878
+
+#define mmDCORE0_MME_QM_CQ_CTL_CI_1 0x40CA87C
+
+#define mmDCORE0_MME_QM_CQ_CTL_CI_2 0x40CA880
+
+#define mmDCORE0_MME_QM_CQ_CTL_CI_3 0x40CA884
+
+#define mmDCORE0_MME_QM_CQ_CTL_CI_4 0x40CA888
+
+#define mmDCORE0_MME_QM_ARC_CQ_CTL_CI 0x40CA88C
+
+#define mmDCORE0_MME_QM_CP_CFG 0x40CA890
+
+#define mmDCORE0_MME_QM_CP_EXT_SWITCH 0x40CA894
+
+#define mmDCORE0_MME_QM_CP_SWITCH_WD_SET 0x40CA898
+
+#define mmDCORE0_MME_QM_CP_SWITCH_WD 0x40CA89C
+
+#define mmDCORE0_MME_QM_ARC_LB_ADDR_BASE_LO 0x40CA8A4
+
+#define mmDCORE0_MME_QM_ARC_LB_ADDR_BASE_HI 0x40CA8A8
+
+#define mmDCORE0_MME_QM_ENGINE_BASE_ADDR_HI 0x40CA8AC
+
+#define mmDCORE0_MME_QM_ENGINE_BASE_ADDR_LO 0x40CA8B0
+
+#define mmDCORE0_MME_QM_ENGINE_ADDR_RANGE_SIZE 0x40CA8B4
+
+#define mmDCORE0_MME_QM_QM_ARC_AUX_BASE_ADDR_HI 0x40CA8B8
+
+#define mmDCORE0_MME_QM_QM_ARC_AUX_BASE_ADDR_LO 0x40CA8BC
+
+#define mmDCORE0_MME_QM_QM_BASE_ADDR_HI 0x40CA8C0
+
+#define mmDCORE0_MME_QM_QM_BASE_ADDR_LO 0x40CA8C4
+
+#define mmDCORE0_MME_QM_ARC_PQC_SECURE_PUSH_IND 0x40CA8C8
+
+#define mmDCORE0_MME_QM_PQC_STS_0_0 0x40CA8D0
+
+#define mmDCORE0_MME_QM_PQC_STS_0_1 0x40CA8D4
+
+#define mmDCORE0_MME_QM_PQC_STS_0_2 0x40CA8D8
+
+#define mmDCORE0_MME_QM_PQC_STS_0_3 0x40CA8DC
+
+#define mmDCORE0_MME_QM_PQC_STS_1_0 0x40CA8E0
+
+#define mmDCORE0_MME_QM_PQC_STS_1_1 0x40CA8E4
+
+#define mmDCORE0_MME_QM_PQC_STS_1_2 0x40CA8E8
+
+#define mmDCORE0_MME_QM_PQC_STS_1_3 0x40CA8EC
+
+#define mmDCORE0_MME_QM_SEI_STATUS 0x40CA8F0
+
+#define mmDCORE0_MME_QM_SEI_MASK 0x40CA8F4
+
+#define mmDCORE0_MME_QM_GLBL_ERR_ADDR_LO 0x40CAD00
+
+#define mmDCORE0_MME_QM_GLBL_ERR_ADDR_HI 0x40CAD04
+
+#define mmDCORE0_MME_QM_GLBL_ERR_WDATA 0x40CAD08
+
+#define mmDCORE0_MME_QM_L2H_MASK_LO 0x40CAD14
+
+#define mmDCORE0_MME_QM_L2H_MASK_HI 0x40CAD18
+
+#define mmDCORE0_MME_QM_L2H_CMPR_LO 0x40CAD1C
+
+#define mmDCORE0_MME_QM_L2H_CMPR_HI 0x40CAD20
+
+#define mmDCORE0_MME_QM_LOCAL_RANGE_BASE 0x40CAD24
+
+#define mmDCORE0_MME_QM_LOCAL_RANGE_SIZE 0x40CAD28
+
+#define mmDCORE0_MME_QM_HBW_RD_RATE_LIM_CFG_1 0x40CAD30
+
+#define mmDCORE0_MME_QM_LBW_WR_RATE_LIM_CFG_0 0x40CAD34
+
+#define mmDCORE0_MME_QM_LBW_WR_RATE_LIM_CFG_1 0x40CAD38
+
+#define mmDCORE0_MME_QM_HBW_RD_RATE_LIM_CFG_0 0x40CAD3C
+
+#define mmDCORE0_MME_QM_IND_GW_APB_CFG 0x40CAD40
+
+#define mmDCORE0_MME_QM_IND_GW_APB_WDATA 0x40CAD44
+
+#define mmDCORE0_MME_QM_IND_GW_APB_RDATA 0x40CAD48
+
+#define mmDCORE0_MME_QM_IND_GW_APB_STATUS 0x40CAD4C
+
+#define mmDCORE0_MME_QM_PERF_CNT_FREE_LO 0x40CAD60
+
+#define mmDCORE0_MME_QM_PERF_CNT_FREE_HI 0x40CAD64
+
+#define mmDCORE0_MME_QM_PERF_CNT_IDLE_LO 0x40CAD68
+
+#define mmDCORE0_MME_QM_PERF_CNT_IDLE_HI 0x40CAD6C
+
+#define mmDCORE0_MME_QM_PERF_CNT_CFG 0x40CAD70
+
+#endif /* ASIC_REG_DCORE0_MME_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_sbte0_masks.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_sbte0_masks.h
new file mode 100644
index 000000000000..077ae5232790
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_sbte0_masks.h
@@ -0,0 +1,107 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_MME_SBTE0_MASKS_H_
+#define ASIC_REG_DCORE0_MME_SBTE0_MASKS_H_
+
+/*
+ *****************************************
+ *   DCORE0_MME_SBTE0
+ *   (Prototype: SB)
+ *****************************************
+ */
+
+/* DCORE0_MME_SBTE0_MAX_SIZE */
+#define DCORE0_MME_SBTE0_MAX_SIZE_DATA_SHIFT 0
+#define DCORE0_MME_SBTE0_MAX_SIZE_DATA_MASK 0xFFFF
+#define DCORE0_MME_SBTE0_MAX_SIZE_MD_SHIFT 16
+#define DCORE0_MME_SBTE0_MAX_SIZE_MD_MASK 0xFFFF0000
+
+/* DCORE0_MME_SBTE0_FORCE_MISS */
+#define DCORE0_MME_SBTE0_FORCE_MISS_R_SHIFT 0
+#define DCORE0_MME_SBTE0_FORCE_MISS_R_MASK 0x1
+
+/* DCORE0_MME_SBTE0_MAX */
+#define DCORE0_MME_SBTE0_MAX_OS_SHIFT 0
+#define DCORE0_MME_SBTE0_MAX_OS_MASK 0xFFFF
+
+/* DCORE0_MME_SBTE0_RL */
+#define DCORE0_MME_SBTE0_RL_SATURATION_SHIFT 0
+#define DCORE0_MME_SBTE0_RL_SATURATION_MASK 0xFF
+#define DCORE0_MME_SBTE0_RL_TIMEOUT_SHIFT 8
+#define DCORE0_MME_SBTE0_RL_TIMEOUT_MASK 0xFF00
+#define DCORE0_MME_SBTE0_RL_RATE_LIMITER_EN_SHIFT 16
+#define DCORE0_MME_SBTE0_RL_RATE_LIMITER_EN_MASK 0x10000
+
+/* DCORE0_MME_SBTE0_SB_STALL */
+#define DCORE0_MME_SBTE0_SB_STALL_R_SHIFT 0
+#define DCORE0_MME_SBTE0_SB_STALL_R_MASK 0x1
+
+/* DCORE0_MME_SBTE0_INTR */
+#define DCORE0_MME_SBTE0_INTR_I0_SHIFT 0
+#define DCORE0_MME_SBTE0_INTR_I0_MASK 0x1
+
+/* DCORE0_MME_SBTE0_ARUSER */
+#define DCORE0_MME_SBTE0_ARUSER_ASID_SHIFT 0
+#define DCORE0_MME_SBTE0_ARUSER_ASID_MASK 0x3FF
+#define DCORE0_MME_SBTE0_ARUSER_MMBP_SHIFT 10
+#define DCORE0_MME_SBTE0_ARUSER_MMBP_MASK 0x400
+#define DCORE0_MME_SBTE0_ARUSER_DUMMY_SHIFT 11
+#define DCORE0_MME_SBTE0_ARUSER_DUMMY_MASK 0xFFFFF800
+
+/* DCORE0_MME_SBTE0_ARCACHE */
+#define DCORE0_MME_SBTE0_ARCACHE_N_SHIFT 0
+#define DCORE0_MME_SBTE0_ARCACHE_N_MASK 0xF
+
+/* DCORE0_MME_SBTE0_STATUS */
+#define DCORE0_MME_SBTE0_STATUS_DROP_CNT_SHIFT 0
+#define DCORE0_MME_SBTE0_STATUS_DROP_CNT_MASK 0xFFFFFFFF
+
+/* DCORE0_MME_SBTE0_PRTN */
+#define DCORE0_MME_SBTE0_PRTN_CLK_EN_SHIFT 0
+#define DCORE0_MME_SBTE0_PRTN_CLK_EN_MASK 0x1
+
+/* DCORE0_MME_SBTE0_CFG_SB_INFLIGHTS */
+#define DCORE0_MME_SBTE0_CFG_SB_INFLIGHTS_W_SHIFT 0
+#define DCORE0_MME_SBTE0_CFG_SB_INFLIGHTS_W_MASK 0xFFFFFFFF
+
+/* DCORE0_MME_SBTE0_PROT */
+#define DCORE0_MME_SBTE0_PROT_W_SHIFT 0
+#define DCORE0_MME_SBTE0_PROT_W_MASK 0x7
+
+/* DCORE0_MME_SBTE0_INTR_MASK */
+#define DCORE0_MME_SBTE0_INTR_MASK_W_SHIFT 0
+#define DCORE0_MME_SBTE0_INTR_MASK_W_MASK 0x1
+
+/* DCORE0_MME_SBTE0_ARUSER_MSB */
+#define DCORE0_MME_SBTE0_ARUSER_MSB_VAL_SHIFT 0
+#define DCORE0_MME_SBTE0_ARUSER_MSB_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_MME_SBTE0_CFG_SB_OCCUPIENCY */
+#define DCORE0_MME_SBTE0_CFG_SB_OCCUPIENCY_VAL_SHIFT 0
+#define DCORE0_MME_SBTE0_CFG_SB_OCCUPIENCY_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_MME_SBTE0_ENABLE_CGATE */
+#define DCORE0_MME_SBTE0_ENABLE_CGATE_TE_EN_SHIFT 0
+#define DCORE0_MME_SBTE0_ENABLE_CGATE_TE_EN_MASK 0x1
+#define DCORE0_MME_SBTE0_ENABLE_CGATE_SB_EN_SHIFT 4
+#define DCORE0_MME_SBTE0_ENABLE_CGATE_SB_EN_MASK 0x10
+
+/* DCORE0_MME_SBTE0_INTF_VLD_DBG */
+#define DCORE0_MME_SBTE0_INTF_VLD_DBG_VLD_SHIFT 0
+#define DCORE0_MME_SBTE0_INTF_VLD_DBG_VLD_MASK 0xFFFFFFFF
+
+/* DCORE0_MME_SBTE0_INTF_RDY_DBG */
+#define DCORE0_MME_SBTE0_INTF_RDY_DBG_RDY_SHIFT 0
+#define DCORE0_MME_SBTE0_INTF_RDY_DBG_RDY_MASK 0xFFFFFFFF
+
+#endif /* ASIC_REG_DCORE0_MME_SBTE0_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_sbte0_mstr_if_axuser_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_sbte0_mstr_if_axuser_regs.h
new file mode 100644
index 000000000000..211fa2c2c35b
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_sbte0_mstr_if_axuser_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_MME_SBTE0_MSTR_IF_AXUSER_REGS_H_
+#define ASIC_REG_DCORE0_MME_SBTE0_MSTR_IF_AXUSER_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_MME_SBTE0_MSTR_IF_AXUSER
+ *   (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_ASID 0x40D1A80
+
+#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_MMU_BP 0x40D1A84
+
+#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_STRONG_ORDER 0x40D1A88
+
+#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_NO_SNOOP 0x40D1A8C
+
+#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_WR_REDUCTION 0x40D1A90
+
+#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_RD_ATOMIC 0x40D1A94
+
+#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_QOS 0x40D1A98
+
+#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_RSVD 0x40D1A9C
+
+#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_EMEM_CPAGE 0x40D1AA0
+
+#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_CORE 0x40D1AA4
+
+#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_E2E_COORD 0x40D1AA8
+
+#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_WR_OVRD_LO 0x40D1AB0
+
+#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_WR_OVRD_HI 0x40D1AB4
+
+#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_RD_OVRD_LO 0x40D1AB8
+
+#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_RD_OVRD_HI 0x40D1ABC
+
+#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_LB_COORD 0x40D1AC0
+
+#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_LB_LOCK 0x40D1AC4
+
+#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_LB_RSVD 0x40D1AC8
+
+#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_LB_OVRD 0x40D1ACC
+
+#endif /* ASIC_REG_DCORE0_MME_SBTE0_MSTR_IF_AXUSER_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_wb0_mstr_if_axuser_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_wb0_mstr_if_axuser_regs.h
new file mode 100644
index 000000000000..374a01d2b8d5
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_wb0_mstr_if_axuser_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_MME_WB0_MSTR_IF_AXUSER_REGS_H_
+#define ASIC_REG_DCORE0_MME_WB0_MSTR_IF_AXUSER_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_MME_WB0_MSTR_IF_AXUSER
+ *   (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_ASID 0x40F9A80
+
+#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_MMU_BP 0x40F9A84
+
+#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_STRONG_ORDER 0x40F9A88
+
+#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_NO_SNOOP 0x40F9A8C
+
+#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_WR_REDUCTION 0x40F9A90
+
+#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_RD_ATOMIC 0x40F9A94
+
+#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_QOS 0x40F9A98
+
+#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_RSVD 0x40F9A9C
+
+#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_EMEM_CPAGE 0x40F9AA0
+
+#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_CORE 0x40F9AA4
+
+#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_E2E_COORD 0x40F9AA8
+
+#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_WR_OVRD_LO 0x40F9AB0
+
+#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_WR_OVRD_HI 0x40F9AB4
+
+#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_RD_OVRD_LO 0x40F9AB8
+
+#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_HB_RD_OVRD_HI 0x40F9ABC
+
+#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_LB_COORD 0x40F9AC0
+
+#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_LB_LOCK 0x40F9AC4
+
+#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_LB_RSVD 0x40F9AC8
+
+#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_LB_OVRD 0x40F9ACC
+
+#endif /* ASIC_REG_DCORE0_MME_WB0_MSTR_IF_AXUSER_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_ctrl_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_ctrl_regs.h
new file mode 100644
index 000000000000..22f4d6c805c5
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_ctrl_regs.h
@@ -0,0 +1,291 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_RTR0_CTRL_REGS_H_
+#define ASIC_REG_DCORE0_RTR0_CTRL_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_RTR0_CTRL
+ *   (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmDCORE0_RTR0_CTRL_MEM_NUM 0x4140100
+
+#define mmDCORE0_RTR0_CTRL_MEM_MAP 0x4140104
+
+#define mmDCORE0_RTR0_CTRL_WR_RL_MEM 0x4140108
+
+#define mmDCORE0_RTR0_CTRL_WR_RL_PCI 0x414010C
+
+#define mmDCORE0_RTR0_CTRL_WR_RL_SRAM 0x4140110
+
+#define mmDCORE0_RTR0_CTRL_RD_RL_MEM 0x4140114
+
+#define mmDCORE0_RTR0_CTRL_RD_RL_PCI 0x4140118
+
+#define mmDCORE0_RTR0_CTRL_RD_RL_SRAM 0x414011C
+
+#define mmDCORE0_RTR0_CTRL_WR_RL_MEM_RED 0x4140120
+
+#define mmDCORE0_RTR0_CTRL_RL_MEM_REDUCTION 0x4140124
+
+#define mmDCORE0_RTR0_CTRL_WR_RL_SRAM_RED 0x4140128
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_CFG_0 0x4140400
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_CFG_1 0x4140404
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_SHIFT_0 0x4140408
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_SHIFT_1 0x414040C
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_0 0x4140410
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_1 0x4140414
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_2 0x4140418
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_3 0x414041C
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_4 0x4140420
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_5 0x4140424
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_6 0x4140428
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_7 0x414042C
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_8 0x4140430
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_9 0x4140434
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_10 0x4140438
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_11 0x414043C
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_12 0x4140440
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_13 0x4140444
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_14 0x4140448
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_15 0x414044C
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_0 0x4140450
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_1 0x4140454
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_2 0x4140458
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_3 0x414045C
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_4 0x4140460
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_5 0x4140464
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_6 0x4140468
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_7 0x414046C
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_8 0x4140470
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_9 0x4140474
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_10 0x4140478
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_11 0x414047C
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_12 0x4140480
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_13 0x4140484
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_14 0x4140488
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_15 0x414048C
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_0 0x4140490
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_1 0x4140494
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_2 0x4140498
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_3 0x414049C
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_4 0x41404A0
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_5 0x41404A4
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_6 0x41404A8
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_7 0x41404AC
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_8 0x41404B0
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_9 0x41404B4
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_10 0x41404B8
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_11 0x41404BC
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_12 0x41404C0
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_13 0x41404C4
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_14 0x41404C8
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_15 0x41404CC
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_WDT_0 0x41404D0
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_WDT_1 0x41404D4
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_DEC_TOKEN_0 0x41404D8
+
+#define mmDCORE0_RTR0_CTRL_RGL_SRAM_DEC_TOKEN_1 0x41404DC
+
+#define mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_HI_ADDR 0x4140AB8
+
+#define mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_LO_ADDR 0x4140ABC
+
+#define mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_SET 0x4140AC0
+
+#define mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AR_HI_ADDR 0x4140AC4
+
+#define mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AR_LO_ADDR 0x4140AC8
+
+#define mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AR_SET 0x4140ACC
+
+#define mmDCORE0_RTR0_CTRL_DEC_RAZWI_LBW_AW_ADDR 0x4140AD0
+
+#define mmDCORE0_RTR0_CTRL_DEC_RAZWI_LBW_AW_SET 0x4140AD4
+
+#define mmDCORE0_RTR0_CTRL_DEC_RAZWI_LBW_AR_ADDR 0x4140AD8
+
+#define mmDCORE0_RTR0_CTRL_DEC_RAZWI_LBW_AR_SET 0x4140ADC
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_CFG_0 0x4140AE4
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_CFG_1 0x4140AE8
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_SHIFT_0 0x4140AEC
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_SHIFT_1 0x4140AF0
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_0 0x4140AF4
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_1 0x4140AF8
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_2 0x4140AFC
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_3 0x4140B00
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_4 0x4140B04
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_5 0x4140B08
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_6 0x4140B0C
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_7 0x4140B10
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_8 0x4140B14
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_9 0x4140B18
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_10 0x4140B1C
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_11 0x4140B20
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_12 0x4140B24
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_13 0x4140B28
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_14 0x4140B2C
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_15 0x4140B30
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_0 0x4140B34
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_1 0x4140B38
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_2 0x4140B3C
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_3 0x4140B40
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_4 0x4140B44
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_5 0x4140B48
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_6 0x4140B4C
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_7 0x4140B50
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_8 0x4140B54
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_9 0x4140B58
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_10 0x4140B5C
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_11 0x4140B60
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_12 0x4140B64
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_13 0x4140B68
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_14 0x4140B6C
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_15 0x4140B70
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_0 0x4140B74
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_1 0x4140B78
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_2 0x4140B7C
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_3 0x4140B80
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_4 0x4140B84
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_5 0x4140B88
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_6 0x4140B8C
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_7 0x4140B90
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_8 0x4140B94
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_9 0x4140B98
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_10 0x4140B9C
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_11 0x4140BA0
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_12 0x4140BA4
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_13 0x4140BA8
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_14 0x4140BAC
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_15 0x4140BB0
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_WDT_0 0x4140BB4
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_WDT_1 0x4140BB8
+
+#define mmDCORE0_RTR0_CTRL_RGL_WR_RED_CNT 0x4140BBC
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_DEC_TOKEN_0 0x4140BC0
+
+#define mmDCORE0_RTR0_CTRL_RGL_MEM_DEC_TOKEN_1 0x4140BC4
+
+#endif /* ASIC_REG_DCORE0_RTR0_CTRL_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_prvt_hbw_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_prvt_hbw_regs.h
new file mode 100644
index 000000000000..3a7290b3a5c9
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_prvt_hbw_regs.h
@@ -0,0 +1,213 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_REGS_H_
+#define ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_RTR0_MSTR_IF_RR_PRVT_HBW
+ *   (Prototype: RANGE_REG_HBW)
+ *****************************************
+ */
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_LO_0 0x4142200
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_LO_1 0x4142204
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_LO_2 0x4142208
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_LO_3 0x414220C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_LO_4 0x4142210
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_LO_5 0x4142214
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_HI_0 0x4142218
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_HI_1 0x414221C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_HI_2 0x4142220
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_HI_3 0x4142224
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_HI_4 0x4142228
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_HI_5 0x414222C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_LO_0 0x4142230
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_LO_1 0x4142234
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_LO_2 0x4142238
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_LO_3 0x414223C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_LO_4 0x4142240
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_LO_5 0x4142244
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_HI_0 0x4142248
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_HI_1 0x414224C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_HI_2 0x4142250
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_HI_3 0x4142254
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_HI_4 0x4142258
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_HI_5 0x414225C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_LO_0 0x4142260
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_LO_1 0x4142264
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_LO_2 0x4142268
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_LO_3 0x414226C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_LO_4 0x4142270
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_LO_5 0x4142274
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_HI_0 0x4142278
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_HI_1 0x414227C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_HI_2 0x4142280
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_HI_3 0x4142284
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_HI_4 0x4142288
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_HI_5 0x414228C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_SHORT_LO_0 0x4142290
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_SHORT_LO_1 0x4142294
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_SHORT_LO_2 0x4142298
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_SHORT_LO_3 0x414229C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_SHORT_LO_4 0x41422A0
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_SHORT_LO_5 0x41422A4
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_SHORT_HI_0 0x41422A8
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_SHORT_HI_1 0x41422AC
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_SHORT_HI_2 0x41422B0
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_SHORT_HI_3 0x41422B4
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_SHORT_HI_4 0x41422B8
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_SHORT_HI_5 0x41422BC
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_HI_0 0x41422C0
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_HI_1 0x41422C4
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_HI_2 0x41422C8
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_HI_3 0x41422CC
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_LO_0 0x41422D0
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_LO_1 0x41422D4
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_LO_2 0x41422D8
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_LO_3 0x41422DC
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_HI_0 0x41422E0
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_HI_1 0x41422E4
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_HI_2 0x41422E8
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_HI_3 0x41422EC
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_LO_0 0x41422F0
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_LO_1 0x41422F4
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_LO_2 0x41422F8
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_LO_3 0x41422FC
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_HI_0 0x4142300
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_HI_1 0x4142304
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_HI_2 0x4142308
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_HI_3 0x414230C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_LO_0 0x4142310
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_LO_1 0x4142314
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_LO_2 0x4142318
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_LO_3 0x414231C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_HI_0 0x4142320
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_HI_1 0x4142324
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_HI_2 0x4142328
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_HI_3 0x414232C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_LO_0 0x4142330
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_LO_1 0x4142334
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_LO_2 0x4142338
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_LO_3 0x414233C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_PCIE_EN 0x4142340
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_PCIE_EN 0x4142344
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_HIT_AW 0x4142348
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_HIT_AW 0x414234C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_HIT_AR 0x4142350
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_HIT_AR 0x4142354
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_AW_RAZWI_HI 0x4142358
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_AW_RAZWI_LO 0x414235C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_AR_RAZWI_HI 0x4142360
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_AR_RAZWI_LO 0x4142364
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_AW_RAZWI_XY 0x4142368
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_AR_RAZWI_XY 0x414236C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_AW_RAZWI_HAPPENED 0x4142370
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_AR_RAZWI_HAPPENED 0x4142374
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_RAZWI_ERR_RESP 0x4142378
+
+#endif /* ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_prvt_lbw_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_prvt_lbw_regs.h
new file mode 100644
index 000000000000..5b52b88fee0f
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_prvt_lbw_regs.h
@@ -0,0 +1,189 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_REGS_H_
+#define ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_RTR0_MSTR_IF_RR_PRVT_LBW
+ *   (Prototype: RANGE_REG_LBW)
+ *****************************************
+ */
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_0 0x4142600
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_1 0x4142604
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_2 0x4142608
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_3 0x414260C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_4 0x4142610
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_5 0x4142614
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_6 0x4142618
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_7 0x414261C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_8 0x4142620
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_9 0x4142624
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_10 0x4142628
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_11 0x414262C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_12 0x4142630
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_13 0x4142634
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_0 0x4142638
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_1 0x414263C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_2 0x4142640
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_3 0x4142644
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_4 0x4142648
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_5 0x414264C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_6 0x4142650
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_7 0x4142654
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_8 0x4142658
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_9 0x414265C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_10 0x4142660
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_11 0x4142664
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_12 0x4142668
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_13 0x414266C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_0 0x4142670
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_1 0x4142674
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_2 0x4142678
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_3 0x414267C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_4 0x4142680
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_5 0x4142684
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_6 0x4142688
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_7 0x414268C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_8 0x4142690
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_9 0x4142694
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_10 0x4142698
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_11 0x414269C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_12 0x41426A0
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_13 0x41426A4
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_0 0x41426A8
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_1 0x41426AC
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_2 0x41426B0
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_3 0x41426B4
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_4 0x41426B8
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_5 0x41426BC
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_6 0x41426C0
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_7 0x41426C4
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_8 0x41426C8
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_9 0x41426CC
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_10 0x41426D0
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_11 0x41426D4
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_12 0x41426D8
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_13 0x41426DC
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_0 0x41426E0
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_1 0x41426E4
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_2 0x41426E8
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_3 0x41426EC
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_0 0x41426F0
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_1 0x41426F4
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_2 0x41426F8
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_3 0x41426FC
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_0 0x4142700
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_1 0x4142704
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_2 0x4142708
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_3 0x414270C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_0 0x4142710
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_1 0x4142714
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_2 0x4142718
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_3 0x414271C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_HIT_AW 0x4142720
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_HIT_AW 0x4142724
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_HIT_AR 0x4142728
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_HIT_AR 0x414272C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_AW_RAZWI 0x4142730
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_AR_RAZWI 0x4142734
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_AW_RAZWI_XY 0x4142738
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_AR_RAZWI_XY 0x414273C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_AW_RAZWI_HAPPENED 0x4142740
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_AR_RAZWI_HAPPENED 0x4142744
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_RAZWI_ERR_RESP 0x4142748
+
+#endif /* ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_shrd_hbw_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_shrd_hbw_regs.h
new file mode 100644
index 000000000000..d9b3f5cd392b
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_shrd_hbw_regs.h
@@ -0,0 +1,213 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_REGS_H_
+#define ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_RTR0_MSTR_IF_RR_SHRD_HBW
+ *   (Prototype: RANGE_REG_HBW)
+ *****************************************
+ */
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_0 0x4142000
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_1 0x4142004
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_2 0x4142008
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_3 0x414200C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_4 0x4142010
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_5 0x4142014
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_0 0x4142018
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_1 0x414201C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_2 0x4142020
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_3 0x4142024
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_4 0x4142028
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_5 0x414202C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_0 0x4142030
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_1 0x4142034
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_2 0x4142038
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_3 0x414203C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_4 0x4142040
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_5 0x4142044
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_0 0x4142048
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_1 0x414204C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_2 0x4142050
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_3 0x4142054
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_4 0x4142058
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_5 0x414205C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_0 0x4142060
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_1 0x4142064
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_2 0x4142068
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_3 0x414206C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_4 0x4142070
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_5 0x4142074
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_0 0x4142078
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_1 0x414207C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_2 0x4142080
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_3 0x4142084
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_4 0x4142088
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_5 0x414208C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_0 0x4142090
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_1 0x4142094
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_2 0x4142098
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_3 0x414209C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_4 0x41420A0
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_5 0x41420A4
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_0 0x41420A8
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_1 0x41420AC
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_2 0x41420B0
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_3 0x41420B4
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_4 0x41420B8
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_5 0x41420BC
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_HI_0 0x41420C0
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_HI_1 0x41420C4
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_HI_2 0x41420C8
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_HI_3 0x41420CC
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_LO_0 0x41420D0
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_LO_1 0x41420D4
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_LO_2 0x41420D8
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_LO_3 0x41420DC
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_HI_0 0x41420E0
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_HI_1 0x41420E4
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_HI_2 0x41420E8
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_HI_3 0x41420EC
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_LO_0 0x41420F0
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_LO_1 0x41420F4
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_LO_2 0x41420F8
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_LO_3 0x41420FC
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_HI_0 0x4142100
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_HI_1 0x4142104
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_HI_2 0x4142108
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_HI_3 0x414210C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_LO_0 0x4142110
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_LO_1 0x4142114
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_LO_2 0x4142118
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_LO_3 0x414211C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_HI_0 0x4142120
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_HI_1 0x4142124
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_HI_2 0x4142128
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_HI_3 0x414212C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_LO_0 0x4142130
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_LO_1 0x4142134
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_LO_2 0x4142138
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_LO_3 0x414213C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_PCIE_EN 0x4142140
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_PCIE_EN 0x4142144
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_HIT_AW 0x4142148
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_HIT_AW 0x414214C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_HIT_AR 0x4142150
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_HIT_AR 0x4142154
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_HI 0x4142158
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_LO 0x414215C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_HI 0x4142160
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_LO 0x4142164
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_XY 0x4142168
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_XY 0x414216C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_HAPPENED 0x4142170
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_HAPPENED 0x4142174
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_RAZWI_ERR_RESP 0x4142178
+
+#endif /* ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_shrd_lbw_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_shrd_lbw_regs.h
new file mode 100644
index 000000000000..1bba940d3031
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_shrd_lbw_regs.h
@@ -0,0 +1,189 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_REGS_H_
+#define ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_RTR0_MSTR_IF_RR_SHRD_LBW
+ *   (Prototype: RANGE_REG_LBW)
+ *****************************************
+ */
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_0 0x4142400
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_1 0x4142404
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_2 0x4142408
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_3 0x414240C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_4 0x4142410
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_5 0x4142414
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_6 0x4142418
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_7 0x414241C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_8 0x4142420
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_9 0x4142424
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_10 0x4142428
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_11 0x414242C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_12 0x4142430
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_13 0x4142434
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_0 0x4142438
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_1 0x414243C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_2 0x4142440
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_3 0x4142444
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_4 0x4142448
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_5 0x414244C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_6 0x4142450
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_7 0x4142454
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_8 0x4142458
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_9 0x414245C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_10 0x4142460
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_11 0x4142464
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_12 0x4142468
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_13 0x414246C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_0 0x4142470
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_1 0x4142474
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_2 0x4142478
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_3 0x414247C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_4 0x4142480
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_5 0x4142484
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_6 0x4142488
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_7 0x414248C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_8 0x4142490
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_9 0x4142494
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_10 0x4142498
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_11 0x414249C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_12 0x41424A0
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_13 0x41424A4
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_0 0x41424A8
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_1 0x41424AC
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_2 0x41424B0
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_3 0x41424B4
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_4 0x41424B8
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_5 0x41424BC
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_6 0x41424C0
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_7 0x41424C4
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_8 0x41424C8
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_9 0x41424CC
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_10 0x41424D0
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_11 0x41424D4
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_12 0x41424D8
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_13 0x41424DC
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_0 0x41424E0
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_1 0x41424E4
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_2 0x41424E8
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_3 0x41424EC
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_0 0x41424F0
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_1 0x41424F4
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_2 0x41424F8
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_3 0x41424FC
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_0 0x4142500
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_1 0x4142504
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_2 0x4142508
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_3 0x414250C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_0 0x4142510
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_1 0x4142514
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_2 0x4142518
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_3 0x414251C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_HIT_AW 0x4142520
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_HIT_AW 0x4142524
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_HIT_AR 0x4142528
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_HIT_AR 0x414252C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AW_RAZWI 0x4142530
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AR_RAZWI 0x4142534
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AW_RAZWI_XY 0x4142538
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AR_RAZWI_XY 0x414253C
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AW_RAZWI_HAPPENED 0x4142540
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AR_RAZWI_HAPPENED 0x4142544
+
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_RAZWI_ERR_RESP 0x4142548
+
+#endif /* ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_glbl_masks.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_glbl_masks.h
new file mode 100644
index 000000000000..f21540501cdd
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_glbl_masks.h
@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_SYNC_MNGR_GLBL_MASKS_H_
+#define ASIC_REG_DCORE0_SYNC_MNGR_GLBL_MASKS_H_
+
+/*
+ *****************************************
+ *   DCORE0_SYNC_MNGR_GLBL
+ *   (Prototype: SOB_GLBL)
+ *****************************************
+ */
+
+/* DCORE0_SYNC_MNGR_GLBL_SM_SEI_MASK */
+#define DCORE0_SYNC_MNGR_GLBL_SM_SEI_MASK_SO_OVERFLOW_SHIFT 0
+#define DCORE0_SYNC_MNGR_GLBL_SM_SEI_MASK_SO_OVERFLOW_MASK 0x1
+#define DCORE0_SYNC_MNGR_GLBL_SM_SEI_MASK_MST_UNALIGN4B_SHIFT 1
+#define DCORE0_SYNC_MNGR_GLBL_SM_SEI_MASK_MST_UNALIGN4B_MASK 0x2
+#define DCORE0_SYNC_MNGR_GLBL_SM_SEI_MASK_MST_RSP_ERR_SHIFT 2
+#define DCORE0_SYNC_MNGR_GLBL_SM_SEI_MASK_MST_RSP_ERR_MASK 0x4
+
+/* DCORE0_SYNC_MNGR_GLBL_SM_SEI_CAUSE */
+#define DCORE0_SYNC_MNGR_GLBL_SM_SEI_CAUSE_CAUSE_SHIFT 0
+#define DCORE0_SYNC_MNGR_GLBL_SM_SEI_CAUSE_CAUSE_MASK 0x7
+#define DCORE0_SYNC_MNGR_GLBL_SM_SEI_CAUSE_LOG_SHIFT 4
+#define DCORE0_SYNC_MNGR_GLBL_SM_SEI_CAUSE_LOG_MASK 0xFFFF0
+
+/* DCORE0_SYNC_MNGR_GLBL_L2H_CPMR_L */
+#define DCORE0_SYNC_MNGR_GLBL_L2H_CPMR_L_VAL_SHIFT 0
+#define DCORE0_SYNC_MNGR_GLBL_L2H_CPMR_L_VAL_MASK 0xFFF
+
+/* DCORE0_SYNC_MNGR_GLBL_L2H_CPMR_H */
+#define DCORE0_SYNC_MNGR_GLBL_L2H_CPMR_H_VAL_SHIFT 0
+#define DCORE0_SYNC_MNGR_GLBL_L2H_CPMR_H_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_SYNC_MNGR_GLBL_L2H_MASK_L */
+#define DCORE0_SYNC_MNGR_GLBL_L2H_MASK_L_VAL_SHIFT 0
+#define DCORE0_SYNC_MNGR_GLBL_L2H_MASK_L_VAL_MASK 0xFFF
+
+/* DCORE0_SYNC_MNGR_GLBL_L2H_MASK_H */
+#define DCORE0_SYNC_MNGR_GLBL_L2H_MASK_H_VAL_SHIFT 0
+#define DCORE0_SYNC_MNGR_GLBL_L2H_MASK_H_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_SYNC_MNGR_GLBL_ASID_SEC */
+#define DCORE0_SYNC_MNGR_GLBL_ASID_SEC_ASID_SHIFT 0
+#define DCORE0_SYNC_MNGR_GLBL_ASID_SEC_ASID_MASK 0xFFFF
+#define DCORE0_SYNC_MNGR_GLBL_ASID_SEC_BP_MMU_SHIFT 16
+#define DCORE0_SYNC_MNGR_GLBL_ASID_SEC_BP_MMU_MASK 0x10000
+
+/* DCORE0_SYNC_MNGR_GLBL_ASID_PRIV_ONLY */
+#define DCORE0_SYNC_MNGR_GLBL_ASID_PRIV_ONLY_ASID_SHIFT 0
+#define DCORE0_SYNC_MNGR_GLBL_ASID_PRIV_ONLY_ASID_MASK 0xFFFF
+#define DCORE0_SYNC_MNGR_GLBL_ASID_PRIV_ONLY_BP_MMU_SHIFT 16
+#define DCORE0_SYNC_MNGR_GLBL_ASID_PRIV_ONLY_BP_MMU_MASK 0x10000
+
+/* DCORE0_SYNC_MNGR_GLBL_LBW_DELAY */
+#define DCORE0_SYNC_MNGR_GLBL_LBW_DELAY_VAL_SHIFT 0
+#define DCORE0_SYNC_MNGR_GLBL_LBW_DELAY_VAL_MASK 0xFFFF
+#define DCORE0_SYNC_MNGR_GLBL_LBW_DELAY_EN_SHIFT 16
+#define DCORE0_SYNC_MNGR_GLBL_LBW_DELAY_EN_MASK 0x10000
+
+/* DCORE0_SYNC_MNGR_GLBL_PI_SIZE */
+#define DCORE0_SYNC_MNGR_GLBL_PI_SIZE_VAL_SHIFT 0
+#define DCORE0_SYNC_MNGR_GLBL_PI_SIZE_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_SYNC_MNGR_GLBL_SOB_ONLY */
+#define DCORE0_SYNC_MNGR_GLBL_SOB_ONLY_EN_SHIFT 0
+#define DCORE0_SYNC_MNGR_GLBL_SOB_ONLY_EN_MASK 0x1
+
+/* DCORE0_SYNC_MNGR_GLBL_CQ_INTR */
+#define DCORE0_SYNC_MNGR_GLBL_CQ_INTR_CQ_SEC_INTR_SHIFT 0
+#define DCORE0_SYNC_MNGR_GLBL_CQ_INTR_CQ_SEC_INTR_MASK 0x1
+#define DCORE0_SYNC_MNGR_GLBL_CQ_INTR_CQ_SEC_INTR_MASK_SHIFT 8
+#define DCORE0_SYNC_MNGR_GLBL_CQ_INTR_CQ_SEC_INTR_MASK_MASK 0x100
+#define DCORE0_SYNC_MNGR_GLBL_CQ_INTR_CQ_INTR_QUEUE_INDEX_SHIFT 16
+#define DCORE0_SYNC_MNGR_GLBL_CQ_INTR_CQ_INTR_QUEUE_INDEX_MASK 0x3F0000
+
+/* DCORE0_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV */
+#define DCORE0_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV_ASID_SHIFT 0
+#define DCORE0_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV_ASID_MASK 0xFFFF
+#define DCORE0_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV_BP_MMU_SHIFT 16
+#define DCORE0_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV_BP_MMU_MASK 0x10000
+
+/* DCORE0_SYNC_MNGR_GLBL_PI_INC_MODE_SIZE */
+#define DCORE0_SYNC_MNGR_GLBL_PI_INC_MODE_SIZE_VAL_SHIFT 0
+#define DCORE0_SYNC_MNGR_GLBL_PI_INC_MODE_SIZE_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L */
+#define DCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_VAL_SHIFT 0
+#define DCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H */
+#define DCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_VAL_SHIFT 0
+#define DCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2 */
+#define DCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_VAL_SHIFT 0
+#define DCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_VAL_MASK 0xFF
+
+/* DCORE0_SYNC_MNGR_GLBL_CQ_PI */
+#define DCORE0_SYNC_MNGR_GLBL_CQ_PI_VAL_SHIFT 0
+#define DCORE0_SYNC_MNGR_GLBL_CQ_PI_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_SYNC_MNGR_GLBL_CQ_SEC */
+#define DCORE0_SYNC_MNGR_GLBL_CQ_SEC_SEC_SHIFT 0
+#define DCORE0_SYNC_MNGR_GLBL_CQ_SEC_SEC_MASK 0x1
+#define DCORE0_SYNC_MNGR_GLBL_CQ_SEC_PRIV_SHIFT 4
+#define DCORE0_SYNC_MNGR_GLBL_CQ_SEC_PRIV_MASK 0x10
+
+/* DCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L */
+#define DCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_ADDRL_SHIFT 0
+#define DCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_ADDRL_MASK 0xFFFFFFFF
+
+/* DCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H */
+#define DCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_ADDRH_SHIFT 0
+#define DCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_ADDRH_MASK 0xFFFFFFFF
+
+/* DCORE0_SYNC_MNGR_GLBL_LBW_DATA */
+#define DCORE0_SYNC_MNGR_GLBL_LBW_DATA_VAL_SHIFT 0
+#define DCORE0_SYNC_MNGR_GLBL_LBW_DATA_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE */
+#define DCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_MODE_SHIFT 0
+#define DCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_MODE_MASK 0x1
+
+#endif /* ASIC_REG_DCORE0_SYNC_MNGR_GLBL_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_glbl_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_glbl_regs.h
new file mode 100644
index 000000000000..c3c4991e6660
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_glbl_regs.h
@@ -0,0 +1,1203 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_SYNC_MNGR_GLBL_REGS_H_
+#define ASIC_REG_DCORE0_SYNC_MNGR_GLBL_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_SYNC_MNGR_GLBL
+ *   (Prototype: SOB_GLBL)
+ *****************************************
+ */
+
+#define mmDCORE0_SYNC_MNGR_GLBL_SM_SEI_MASK 0x411E000
+
+#define mmDCORE0_SYNC_MNGR_GLBL_SM_SEI_CAUSE 0x411E004
+
+#define mmDCORE0_SYNC_MNGR_GLBL_L2H_CPMR_L 0x411E008
+
+#define mmDCORE0_SYNC_MNGR_GLBL_L2H_CPMR_H 0x411E00C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_L2H_MASK_L 0x411E020
+
+#define mmDCORE0_SYNC_MNGR_GLBL_L2H_MASK_H 0x411E024
+
+#define mmDCORE0_SYNC_MNGR_GLBL_ASID_SEC 0x411E030
+
+#define mmDCORE0_SYNC_MNGR_GLBL_ASID_PRIV_ONLY 0x411E034
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DELAY 0x411E038
+
+#define mmDCORE0_SYNC_MNGR_GLBL_PI_SIZE 0x411E03C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_SOB_ONLY 0x411E040
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INTR 0x411E044
+
+#define mmDCORE0_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV 0x411E048
+
+#define mmDCORE0_SYNC_MNGR_GLBL_PI_INC_MODE_SIZE 0x411E04C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_0 0x411E050
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_1 0x411E054
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_2 0x411E058
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_3 0x411E05C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_4 0x411E060
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_5 0x411E064
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_6 0x411E068
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_7 0x411E06C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_8 0x411E070
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_9 0x411E074
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_10 0x411E078
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_11 0x411E07C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_12 0x411E080
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_13 0x411E084
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_14 0x411E088
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_15 0x411E08C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_16 0x411E090
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_17 0x411E094
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_18 0x411E098
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_19 0x411E09C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_20 0x411E0A0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_21 0x411E0A4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_22 0x411E0A8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_23 0x411E0AC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_24 0x411E0B0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_25 0x411E0B4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_26 0x411E0B8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_27 0x411E0BC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_28 0x411E0C0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_29 0x411E0C4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_30 0x411E0C8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_31 0x411E0CC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_32 0x411E0D0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_33 0x411E0D4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_34 0x411E0D8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_35 0x411E0DC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_36 0x411E0E0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_37 0x411E0E4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_38 0x411E0E8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_39 0x411E0EC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_40 0x411E0F0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_41 0x411E0F4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_42 0x411E0F8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_43 0x411E0FC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_44 0x411E100
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_45 0x411E104
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_46 0x411E108
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_47 0x411E10C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_48 0x411E110
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_49 0x411E114
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_50 0x411E118
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_51 0x411E11C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_52 0x411E120
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_53 0x411E124
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_54 0x411E128
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_55 0x411E12C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_56 0x411E130
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_57 0x411E134
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_58 0x411E138
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_59 0x411E13C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_60 0x411E140
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_61 0x411E144
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_62 0x411E148
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_63 0x411E14C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_0 0x411E150
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_1 0x411E154
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_2 0x411E158
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_3 0x411E15C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_4 0x411E160
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_5 0x411E164
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_6 0x411E168
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_7 0x411E16C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_8 0x411E170
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_9 0x411E174
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_10 0x411E178
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_11 0x411E17C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_12 0x411E180
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_13 0x411E184
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_14 0x411E188
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_15 0x411E18C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_16 0x411E190
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_17 0x411E194
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_18 0x411E198
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_19 0x411E19C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_20 0x411E1A0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_21 0x411E1A4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_22 0x411E1A8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_23 0x411E1AC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_24 0x411E1B0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_25 0x411E1B4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_26 0x411E1B8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_27 0x411E1BC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_28 0x411E1C0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_29 0x411E1C4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_30 0x411E1C8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_31 0x411E1CC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_32 0x411E1D0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_33 0x411E1D4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_34 0x411E1D8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_35 0x411E1DC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_36 0x411E1E0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_37 0x411E1E4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_38 0x411E1E8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_39 0x411E1EC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_40 0x411E1F0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_41 0x411E1F4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_42 0x411E1F8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_43 0x411E1FC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_44 0x411E200
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_45 0x411E204
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_46 0x411E208
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_47 0x411E20C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_48 0x411E210
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_49 0x411E214
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_50 0x411E218
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_51 0x411E21C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_52 0x411E220
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_53 0x411E224
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_54 0x411E228
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_55 0x411E22C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_56 0x411E230
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_57 0x411E234
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_58 0x411E238
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_59 0x411E23C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_60 0x411E240
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_61 0x411E244
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_62 0x411E248
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_63 0x411E24C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_0 0x411E250
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_1 0x411E254
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_2 0x411E258
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_3 0x411E25C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_4 0x411E260
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_5 0x411E264
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_6 0x411E268
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_7 0x411E26C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_8 0x411E270
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_9 0x411E274
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_10 0x411E278
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_11 0x411E27C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_12 0x411E280
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_13 0x411E284
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_14 0x411E288
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_15 0x411E28C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_16 0x411E290
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_17 0x411E294
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_18 0x411E298
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_19 0x411E29C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_20 0x411E2A0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_21 0x411E2A4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_22 0x411E2A8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_23 0x411E2AC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_24 0x411E2B0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_25 0x411E2B4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_26 0x411E2B8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_27 0x411E2BC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_28 0x411E2C0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_29 0x411E2C4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_30 0x411E2C8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_31 0x411E2CC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_32 0x411E2D0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_33 0x411E2D4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_34 0x411E2D8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_35 0x411E2DC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_36 0x411E2E0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_37 0x411E2E4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_38 0x411E2E8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_39 0x411E2EC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_40 0x411E2F0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_41 0x411E2F4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_42 0x411E2F8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_43 0x411E2FC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_44 0x411E300
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_45 0x411E304
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_46 0x411E308
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_47 0x411E30C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_48 0x411E310
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_49 0x411E314
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_50 0x411E318
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_51 0x411E31C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_52 0x411E320
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_53 0x411E324
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_54 0x411E328
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_55 0x411E32C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_56 0x411E330
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_57 0x411E334
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_58 0x411E338
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_59 0x411E33C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_60 0x411E340
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_61 0x411E344
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_62 0x411E348
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_63 0x411E34C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_0 0x411E350
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_1 0x411E354
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_2 0x411E358
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_3 0x411E35C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_4 0x411E360
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_5 0x411E364
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_6 0x411E368
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_7 0x411E36C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_8 0x411E370
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_9 0x411E374
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_10 0x411E378
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_11 0x411E37C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_12 0x411E380
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_13 0x411E384
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_14 0x411E388
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_15 0x411E38C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_16 0x411E390
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_17 0x411E394
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_18 0x411E398
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_19 0x411E39C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_20 0x411E3A0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_21 0x411E3A4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_22 0x411E3A8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_23 0x411E3AC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_24 0x411E3B0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_25 0x411E3B4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_26 0x411E3B8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_27 0x411E3BC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_28 0x411E3C0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_29 0x411E3C4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_30 0x411E3C8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_31 0x411E3CC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_32 0x411E3D0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_33 0x411E3D4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_34 0x411E3D8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_35 0x411E3DC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_36 0x411E3E0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_37 0x411E3E4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_38 0x411E3E8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_39 0x411E3EC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_40 0x411E3F0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_41 0x411E3F4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_42 0x411E3F8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_43 0x411E3FC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_44 0x411E400
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_45 0x411E404
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_46 0x411E408
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_47 0x411E40C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_48 0x411E410
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_49 0x411E414
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_50 0x411E418
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_51 0x411E41C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_52 0x411E420
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_53 0x411E424
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_54 0x411E428
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_55 0x411E42C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_56 0x411E430
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_57 0x411E434
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_58 0x411E438
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_59 0x411E43C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_60 0x411E440
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_61 0x411E444
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_62 0x411E448
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_63 0x411E44C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_0 0x411E450
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_1 0x411E454
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_2 0x411E458
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_3 0x411E45C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_4 0x411E460
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_5 0x411E464
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_6 0x411E468
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_7 0x411E46C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_8 0x411E470
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_9 0x411E474
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_10 0x411E478
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_11 0x411E47C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_12 0x411E480
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_13 0x411E484
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_14 0x411E488
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_15 0x411E48C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_16 0x411E490
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_17 0x411E494
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_18 0x411E498
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_19 0x411E49C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_20 0x411E4A0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_21 0x411E4A4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_22 0x411E4A8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_23 0x411E4AC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_24 0x411E4B0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_25 0x411E4B4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_26 0x411E4B8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_27 0x411E4BC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_28 0x411E4C0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_29 0x411E4C4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_30 0x411E4C8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_31 0x411E4CC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_32 0x411E4D0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_33 0x411E4D4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_34 0x411E4D8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_35 0x411E4DC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_36 0x411E4E0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_37 0x411E4E4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_38 0x411E4E8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_39 0x411E4EC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_40 0x411E4F0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_41 0x411E4F4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_42 0x411E4F8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_43 0x411E4FC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_44 0x411E500
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_45 0x411E504
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_46 0x411E508
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_47 0x411E50C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_48 0x411E510
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_49 0x411E514
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_50 0x411E518
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_51 0x411E51C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_52 0x411E520
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_53 0x411E524
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_54 0x411E528
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_55 0x411E52C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_56 0x411E530
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_57 0x411E534
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_58 0x411E538
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_59 0x411E53C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_60 0x411E540
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_61 0x411E544
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_62 0x411E548
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_63 0x411E54C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_0 0x411E550
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_1 0x411E554
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_2 0x411E558
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_3 0x411E55C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_4 0x411E560
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_5 0x411E564
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_6 0x411E568
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_7 0x411E56C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_8 0x411E570
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_9 0x411E574
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_10 0x411E578
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_11 0x411E57C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_12 0x411E580
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_13 0x411E584
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_14 0x411E588
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_15 0x411E58C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_16 0x411E590
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_17 0x411E594
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_18 0x411E598
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_19 0x411E59C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_20 0x411E5A0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_21 0x411E5A4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_22 0x411E5A8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_23 0x411E5AC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_24 0x411E5B0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_25 0x411E5B4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_26 0x411E5B8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_27 0x411E5BC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_28 0x411E5C0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_29 0x411E5C4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_30 0x411E5C8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_31 0x411E5CC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_32 0x411E5D0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_33 0x411E5D4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_34 0x411E5D8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_35 0x411E5DC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_36 0x411E5E0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_37 0x411E5E4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_38 0x411E5E8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_39 0x411E5EC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_40 0x411E5F0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_41 0x411E5F4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_42 0x411E5F8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_43 0x411E5FC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_44 0x411E600
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_45 0x411E604
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_46 0x411E608
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_47 0x411E60C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_48 0x411E610
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_49 0x411E614
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_50 0x411E618
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_51 0x411E61C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_52 0x411E620
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_53 0x411E624
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_54 0x411E628
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_55 0x411E62C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_56 0x411E630
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_57 0x411E634
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_58 0x411E638
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_59 0x411E63C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_60 0x411E640
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_61 0x411E644
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_62 0x411E648
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_63 0x411E64C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_0 0x411E650
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_1 0x411E654
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_2 0x411E658
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_3 0x411E65C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_4 0x411E660
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_5 0x411E664
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_6 0x411E668
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_7 0x411E66C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_8 0x411E670
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_9 0x411E674
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_10 0x411E678
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_11 0x411E67C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_12 0x411E680
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_13 0x411E684
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_14 0x411E688
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_15 0x411E68C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_16 0x411E690
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_17 0x411E694
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_18 0x411E698
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_19 0x411E69C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_20 0x411E6A0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_21 0x411E6A4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_22 0x411E6A8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_23 0x411E6AC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_24 0x411E6B0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_25 0x411E6B4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_26 0x411E6B8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_27 0x411E6BC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_28 0x411E6C0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_29 0x411E6C4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_30 0x411E6C8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_31 0x411E6CC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_32 0x411E6D0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_33 0x411E6D4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_34 0x411E6D8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_35 0x411E6DC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_36 0x411E6E0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_37 0x411E6E4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_38 0x411E6E8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_39 0x411E6EC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_40 0x411E6F0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_41 0x411E6F4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_42 0x411E6F8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_43 0x411E6FC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_44 0x411E700
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_45 0x411E704
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_46 0x411E708
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_47 0x411E70C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_48 0x411E710
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_49 0x411E714
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_50 0x411E718
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_51 0x411E71C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_52 0x411E720
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_53 0x411E724
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_54 0x411E728
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_55 0x411E72C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_56 0x411E730
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_57 0x411E734
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_58 0x411E738
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_59 0x411E73C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_60 0x411E740
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_61 0x411E744
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_62 0x411E748
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_63 0x411E74C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_0 0x411E750
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_1 0x411E754
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_2 0x411E758
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_3 0x411E75C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_4 0x411E760
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_5 0x411E764
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_6 0x411E768
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_7 0x411E76C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_8 0x411E770
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_9 0x411E774
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_10 0x411E778
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_11 0x411E77C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_12 0x411E780
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_13 0x411E784
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_14 0x411E788
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_15 0x411E78C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_16 0x411E790
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_17 0x411E794
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_18 0x411E798
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_19 0x411E79C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_20 0x411E7A0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_21 0x411E7A4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_22 0x411E7A8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_23 0x411E7AC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_24 0x411E7B0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_25 0x411E7B4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_26 0x411E7B8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_27 0x411E7BC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_28 0x411E7C0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_29 0x411E7C4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_30 0x411E7C8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_31 0x411E7CC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_32 0x411E7D0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_33 0x411E7D4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_34 0x411E7D8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_35 0x411E7DC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_36 0x411E7E0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_37 0x411E7E4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_38 0x411E7E8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_39 0x411E7EC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_40 0x411E7F0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_41 0x411E7F4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_42 0x411E7F8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_43 0x411E7FC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_44 0x411E800
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_45 0x411E804
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_46 0x411E808
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_47 0x411E80C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_48 0x411E810
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_49 0x411E814
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_50 0x411E818
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_51 0x411E81C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_52 0x411E820
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_53 0x411E824
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_54 0x411E828
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_55 0x411E82C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_56 0x411E830
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_57 0x411E834
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_58 0x411E838
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_59 0x411E83C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_60 0x411E840
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_61 0x411E844
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_62 0x411E848
+
+#define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_63 0x411E84C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_0 0x411E850
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_1 0x411E854
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_2 0x411E858
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_3 0x411E85C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_4 0x411E860
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_5 0x411E864
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_6 0x411E868
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_7 0x411E86C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_8 0x411E870
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_9 0x411E874
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_10 0x411E878
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_11 0x411E87C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_12 0x411E880
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_13 0x411E884
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_14 0x411E888
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_15 0x411E88C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_16 0x411E890
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_17 0x411E894
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_18 0x411E898
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_19 0x411E89C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_20 0x411E8A0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_21 0x411E8A4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_22 0x411E8A8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_23 0x411E8AC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_24 0x411E8B0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_25 0x411E8B4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_26 0x411E8B8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_27 0x411E8BC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_28 0x411E8C0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_29 0x411E8C4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_30 0x411E8C8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_31 0x411E8CC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_32 0x411E8D0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_33 0x411E8D4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_34 0x411E8D8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_35 0x411E8DC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_36 0x411E8E0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_37 0x411E8E4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_38 0x411E8E8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_39 0x411E8EC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_40 0x411E8F0
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_41 0x411E8F4
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_42 0x411E8F8
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_43 0x411E8FC
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_44 0x411E900
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_45 0x411E904
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_46 0x411E908
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_47 0x411E90C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_48 0x411E910
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_49 0x411E914
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_50 0x411E918
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_51 0x411E91C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_52 0x411E920
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_53 0x411E924
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_54 0x411E928
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_55 0x411E92C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_56 0x411E930
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_57 0x411E934
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_58 0x411E938
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_59 0x411E93C
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_60 0x411E940
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_61 0x411E944
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_62 0x411E948
+
+#define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_63 0x411E94C
+
+#endif /* ASIC_REG_DCORE0_SYNC_MNGR_GLBL_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_mstr_if_axuser_masks.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_mstr_if_axuser_masks.h
new file mode 100644
index 000000000000..76b273a41255
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_mstr_if_axuser_masks.h
@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_MASKS_H_
+#define ASIC_REG_DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_MASKS_H_
+
+/*
+ *****************************************
+ *   DCORE0_SYNC_MNGR_MSTR_IF_AXUSER
+ *   (Prototype: AXUSER)
+ *****************************************
+ */
+
+/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_ASID */
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_ASID_WR_SHIFT 0
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_ASID_WR_MASK 0x3FF
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_ASID_RD_SHIFT 16
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_ASID_RD_MASK 0x3FF0000
+
+/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_MMU_BP */
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_MMU_BP_WR_SHIFT 0
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_MMU_BP_WR_MASK 0x1
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_MMU_BP_RD_SHIFT 4
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_MMU_BP_RD_MASK 0x10
+
+/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_STRONG_ORDER */
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_STRONG_ORDER_WR_SHIFT 0
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_STRONG_ORDER_WR_MASK 0x1
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_STRONG_ORDER_RD_SHIFT 4
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_STRONG_ORDER_RD_MASK 0x10
+
+/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_NO_SNOOP */
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_NO_SNOOP_WR_SHIFT 0
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_NO_SNOOP_WR_MASK 0x1
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_NO_SNOOP_RD_SHIFT 4
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_NO_SNOOP_RD_MASK 0x10
+
+/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION */
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION_IND_SHIFT 0
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION_IND_MASK 0x1
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION_DTYPE_SHIFT 4
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION_DTYPE_MASK 0xF0
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION_OP_SHIFT 8
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION_OP_MASK 0x300
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION_ROUND_SHIFT 12
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION_ROUND_MASK 0x3000
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION_MAX_SHIFT 16
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION_MAX_MASK 0x10000
+
+/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_ATOMIC */
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_ATOMIC_IND_SHIFT 0
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_ATOMIC_IND_MASK 0x3
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_ATOMIC_ADDITION_SIZE_SHIFT 4
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_ATOMIC_ADDITION_SIZE_MASK 0xFF0
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_ATOMIC_MSB_MASK_SHIFT 12
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_ATOMIC_MSB_MASK_MASK 0x1F000
+
+/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_QOS */
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_QOS_WR_SHIFT 0
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_QOS_WR_MASK 0xF
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_QOS_RD_SHIFT 4
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_QOS_RD_MASK 0x70
+
+/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RSVD */
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RSVD_WR_BIT_27_SHIFT 0
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RSVD_WR_BIT_27_MASK 0x1
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RSVD_WR_BIT_28_SHIFT 1
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RSVD_WR_BIT_28_MASK 0x2
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RSVD_WR_BIT_30_SHIFT 2
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RSVD_WR_BIT_30_MASK 0x4
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RSVD_WR_BIT_31_SHIFT 3
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RSVD_WR_BIT_31_MASK 0x8
+
+/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_EMEM_CPAGE */
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_EMEM_CPAGE_WR_SHIFT 0
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_EMEM_CPAGE_WR_MASK 0x1
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_EMEM_CPAGE_RD_SHIFT 4
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_EMEM_CPAGE_RD_MASK 0x10
+
+/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_CORE */
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_CORE_WR_SHIFT 0
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_CORE_WR_MASK 0x1
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_CORE_RD_SHIFT 4
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_CORE_RD_MASK 0x10
+
+/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_E2E_COORD */
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_E2E_COORD_X_SHIFT 0
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_E2E_COORD_X_MASK 0x1F
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_E2E_COORD_Y_SHIFT 8
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_E2E_COORD_Y_MASK 0xF00
+
+/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_OVRD_LO */
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_OVRD_LO_VAL_SHIFT 0
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_OVRD_LO_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_OVRD_HI */
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_OVRD_HI_VAL_SHIFT 0
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_OVRD_HI_VAL_MASK 0x3FF
+
+/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_OVRD_LO */
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_OVRD_LO_VAL_SHIFT 0
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_OVRD_LO_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_OVRD_HI */
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_OVRD_HI_VAL_SHIFT 0
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_OVRD_HI_VAL_MASK 0x3FF
+
+/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_COORD */
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_COORD_VAL_SHIFT 0
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_COORD_VAL_MASK 0x3FF
+
+/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_LOCK */
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_LOCK_VAL_SHIFT 0
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_LOCK_VAL_MASK 0x1
+
+/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_RSVD */
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_RSVD_BIT_21_11_SHIFT 0
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_RSVD_BIT_21_11_MASK 0x7FF
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_RSVD_BIT_22_SHIFT 12
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_RSVD_BIT_22_MASK 0x1000
+
+/* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_OVRD */
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_OVRD_VAL_SHIFT 0
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_OVRD_VAL_MASK 0xFFFFFFFF
+
+#endif /* ASIC_REG_DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_mstr_if_axuser_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_mstr_if_axuser_regs.h
new file mode 100644
index 000000000000..0bddc734329f
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_mstr_if_axuser_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_REGS_H_
+#define ASIC_REG_DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_SYNC_MNGR_MSTR_IF_AXUSER
+ *   (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_ASID 0x411FA80
+
+#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_MMU_BP 0x411FA84
+
+#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_STRONG_ORDER 0x411FA88
+
+#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_NO_SNOOP 0x411FA8C
+
+#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION 0x411FA90
+
+#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_ATOMIC 0x411FA94
+
+#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_QOS 0x411FA98
+
+#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RSVD 0x411FA9C
+
+#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_EMEM_CPAGE 0x411FAA0
+
+#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_CORE 0x411FAA4
+
+#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_E2E_COORD 0x411FAA8
+
+#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_OVRD_LO 0x411FAB0
+
+#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_OVRD_HI 0x411FAB4
+
+#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_OVRD_LO 0x411FAB8
+
+#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_OVRD_HI 0x411FABC
+
+#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_COORD 0x411FAC0
+
+#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_LOCK 0x411FAC4
+
+#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_RSVD 0x411FAC8
+
+#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_OVRD 0x411FACC
+
+#endif /* ASIC_REG_DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_objs_masks.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_objs_masks.h
new file mode 100644
index 000000000000..3a5b27df0ab4
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_objs_masks.h
@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_SYNC_MNGR_OBJS_MASKS_H_
+#define ASIC_REG_DCORE0_SYNC_MNGR_OBJS_MASKS_H_
+
+/*
+ *****************************************
+ *   DCORE0_SYNC_MNGR_OBJS
+ *   (Prototype: SOB_OBJS)
+ *****************************************
+ */
+
+/* DCORE0_SYNC_MNGR_OBJS_SOB_OBJ */
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_VAL_SHIFT 0
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_VAL_MASK 0x7FFF
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_LONG_SOB_SHIFT 24
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_LONG_SOB_MASK 0x1000000
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_TRACE_EVICT_SHIFT 30
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_TRACE_EVICT_MASK 0x40000000
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_INC_SHIFT 31
+#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_INC_MASK 0x80000000
+
+/* DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL */
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_ADDRL_SHIFT 0
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_ADDRL_MASK 0xFFFFFFFF
+
+/* DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH */
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_ADDRH_SHIFT 0
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_ADDRH_MASK 0xFFFFFFFF
+
+/* DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA */
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_DATA_SHIFT 0
+#define DCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_DATA_MASK 0xFFFFFFFF
+
+/* DCORE0_SYNC_MNGR_OBJS_MON_ARM */
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_SID_SHIFT 0
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_SID_MASK 0xFF
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_MASK_SHIFT 8
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_MASK_MASK 0xFF00
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_SOP_SHIFT 16
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_SOP_MASK 0x10000
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_SOD_SHIFT 17
+#define DCORE0_SYNC_MNGR_OBJS_MON_ARM_SOD_MASK 0xFFFE0000
+
+/* DCORE0_SYNC_MNGR_OBJS_MON_CONFIG */
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_LONG_SOB_SHIFT 0
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_LONG_SOB_MASK 0x1
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_CQ_EN_SHIFT 4
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_CQ_EN_MASK 0x10
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_WR_NUM_SHIFT 5
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_WR_NUM_MASK 0x60
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_LBW_EN_SHIFT 8
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_LBW_EN_MASK 0x100
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_MSB_SID_SHIFT 16
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_MSB_SID_MASK 0xF0000
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_LONG_HIGH_GROUP_SHIFT 31
+#define DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_LONG_HIGH_GROUP_MASK 0x80000000
+
+/* DCORE0_SYNC_MNGR_OBJS_MON_STATUS */
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_VALID_SHIFT 0
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_VALID_MASK 0x1
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_PENDING_SHIFT 1
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_PENDING_MASK 0x1FE
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_PROT_SHIFT 9
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_PROT_MASK 0x200
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_PRIV_SHIFT 10
+#define DCORE0_SYNC_MNGR_OBJS_MON_STATUS_PRIV_MASK 0x400
+
+/* DCORE0_SYNC_MNGR_OBJS_SM_SEC */
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_SEC_VEC_SHIFT 0
+#define DCORE0_SYNC_MNGR_OBJS_SM_SEC_SEC_VEC_MASK 0xFFFFFFFF
+
+/* DCORE0_SYNC_MNGR_OBJS_SM_PRIV */
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_PRIV_SHIFT 0
+#define DCORE0_SYNC_MNGR_OBJS_SM_PRIV_PRIV_MASK 0xFFFFFFFF
+
+#endif /* ASIC_REG_DCORE0_SYNC_MNGR_OBJS_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_objs_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_objs_regs.h
new file mode 100644
index 000000000000..8f082a1c9b1b
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_sync_mngr_objs_regs.h
@@ -0,0 +1,43543 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_SYNC_MNGR_OBJS_REGS_H_
+#define ASIC_REG_DCORE0_SYNC_MNGR_OBJS_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_SYNC_MNGR_OBJS
+ *   (Prototype: SOB_OBJS)
+ *****************************************
+ */
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 0x4100000
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1 0x4100004
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2 0x4100008
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3 0x410000C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4 0x4100010
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5 0x4100014
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6 0x4100018
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7 0x410001C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8 0x4100020
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_9 0x4100024
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_10 0x4100028
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_11 0x410002C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_12 0x4100030
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_13 0x4100034
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_14 0x4100038
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_15 0x410003C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_16 0x4100040
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_17 0x4100044
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_18 0x4100048
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_19 0x410004C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_20 0x4100050
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_21 0x4100054
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_22 0x4100058
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_23 0x410005C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_24 0x4100060
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_25 0x4100064
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_26 0x4100068
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_27 0x410006C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_28 0x4100070
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_29 0x4100074
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_30 0x4100078
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_31 0x410007C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_32 0x4100080
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_33 0x4100084
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_34 0x4100088
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_35 0x410008C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_36 0x4100090
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_37 0x4100094
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_38 0x4100098
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_39 0x410009C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_40 0x41000A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_41 0x41000A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_42 0x41000A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_43 0x41000AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_44 0x41000B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_45 0x41000B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_46 0x41000B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_47 0x41000BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_48 0x41000C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_49 0x41000C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_50 0x41000C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_51 0x41000CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_52 0x41000D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_53 0x41000D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_54 0x41000D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_55 0x41000DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_56 0x41000E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_57 0x41000E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_58 0x41000E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_59 0x41000EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_60 0x41000F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_61 0x41000F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_62 0x41000F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_63 0x41000FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_64 0x4100100
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_65 0x4100104
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_66 0x4100108
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_67 0x410010C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_68 0x4100110
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_69 0x4100114
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_70 0x4100118
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_71 0x410011C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_72 0x4100120
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_73 0x4100124
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_74 0x4100128
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_75 0x410012C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_76 0x4100130
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_77 0x4100134
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_78 0x4100138
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_79 0x410013C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_80 0x4100140
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_81 0x4100144
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_82 0x4100148
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_83 0x410014C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_84 0x4100150
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_85 0x4100154
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_86 0x4100158
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_87 0x410015C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_88 0x4100160
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_89 0x4100164
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_90 0x4100168
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_91 0x410016C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_92 0x4100170
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_93 0x4100174
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_94 0x4100178
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_95 0x410017C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_96 0x4100180
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_97 0x4100184
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_98 0x4100188
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_99 0x410018C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_100 0x4100190
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_101 0x4100194
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_102 0x4100198
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_103 0x410019C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_104 0x41001A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_105 0x41001A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_106 0x41001A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_107 0x41001AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_108 0x41001B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_109 0x41001B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_110 0x41001B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_111 0x41001BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_112 0x41001C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_113 0x41001C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_114 0x41001C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_115 0x41001CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_116 0x41001D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_117 0x41001D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_118 0x41001D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_119 0x41001DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_120 0x41001E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_121 0x41001E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_122 0x41001E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_123 0x41001EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_124 0x41001F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_125 0x41001F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_126 0x41001F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_127 0x41001FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_128 0x4100200
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_129 0x4100204
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_130 0x4100208
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_131 0x410020C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_132 0x4100210
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_133 0x4100214
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_134 0x4100218
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_135 0x410021C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_136 0x4100220
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_137 0x4100224
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_138 0x4100228
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_139 0x410022C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_140 0x4100230
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_141 0x4100234
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_142 0x4100238
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_143 0x410023C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_144 0x4100240
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_145 0x4100244
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_146 0x4100248
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_147 0x410024C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_148 0x4100250
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_149 0x4100254
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_150 0x4100258
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_151 0x410025C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_152 0x4100260
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_153 0x4100264
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_154 0x4100268
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_155 0x410026C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_156 0x4100270
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_157 0x4100274
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_158 0x4100278
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_159 0x410027C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_160 0x4100280
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_161 0x4100284
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_162 0x4100288
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_163 0x410028C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_164 0x4100290
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_165 0x4100294
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_166 0x4100298
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_167 0x410029C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_168 0x41002A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_169 0x41002A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_170 0x41002A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_171 0x41002AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_172 0x41002B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_173 0x41002B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_174 0x41002B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_175 0x41002BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_176 0x41002C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_177 0x41002C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_178 0x41002C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_179 0x41002CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_180 0x41002D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_181 0x41002D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_182 0x41002D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_183 0x41002DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_184 0x41002E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_185 0x41002E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_186 0x41002E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_187 0x41002EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_188 0x41002F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_189 0x41002F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_190 0x41002F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_191 0x41002FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_192 0x4100300
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_193 0x4100304
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_194 0x4100308
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_195 0x410030C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_196 0x4100310
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_197 0x4100314
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_198 0x4100318
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_199 0x410031C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_200 0x4100320
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_201 0x4100324
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_202 0x4100328
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_203 0x410032C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_204 0x4100330
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_205 0x4100334
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_206 0x4100338
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_207 0x410033C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_208 0x4100340
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_209 0x4100344
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_210 0x4100348
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_211 0x410034C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_212 0x4100350
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_213 0x4100354
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_214 0x4100358
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_215 0x410035C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_216 0x4100360
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_217 0x4100364
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_218 0x4100368
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_219 0x410036C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_220 0x4100370
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_221 0x4100374
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_222 0x4100378
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_223 0x410037C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_224 0x4100380
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_225 0x4100384
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_226 0x4100388
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_227 0x410038C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_228 0x4100390
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_229 0x4100394
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_230 0x4100398
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_231 0x410039C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_232 0x41003A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_233 0x41003A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_234 0x41003A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_235 0x41003AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_236 0x41003B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_237 0x41003B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_238 0x41003B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_239 0x41003BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_240 0x41003C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_241 0x41003C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_242 0x41003C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_243 0x41003CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_244 0x41003D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_245 0x41003D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_246 0x41003D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_247 0x41003DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_248 0x41003E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_249 0x41003E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_250 0x41003E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_251 0x41003EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_252 0x41003F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_253 0x41003F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_254 0x41003F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_255 0x41003FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_256 0x4100400
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_257 0x4100404
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_258 0x4100408
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_259 0x410040C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_260 0x4100410
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_261 0x4100414
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_262 0x4100418
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_263 0x410041C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_264 0x4100420
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_265 0x4100424
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_266 0x4100428
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_267 0x410042C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_268 0x4100430
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_269 0x4100434
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_270 0x4100438
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_271 0x410043C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_272 0x4100440
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_273 0x4100444
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_274 0x4100448
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_275 0x410044C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_276 0x4100450
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_277 0x4100454
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_278 0x4100458
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_279 0x410045C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_280 0x4100460
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_281 0x4100464
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_282 0x4100468
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_283 0x410046C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_284 0x4100470
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_285 0x4100474
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_286 0x4100478
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_287 0x410047C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_288 0x4100480
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_289 0x4100484
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_290 0x4100488
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_291 0x410048C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_292 0x4100490
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_293 0x4100494
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_294 0x4100498
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_295 0x410049C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_296 0x41004A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_297 0x41004A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_298 0x41004A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_299 0x41004AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_300 0x41004B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_301 0x41004B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_302 0x41004B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_303 0x41004BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_304 0x41004C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_305 0x41004C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_306 0x41004C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_307 0x41004CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_308 0x41004D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_309 0x41004D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_310 0x41004D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_311 0x41004DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_312 0x41004E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_313 0x41004E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_314 0x41004E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_315 0x41004EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_316 0x41004F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_317 0x41004F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_318 0x41004F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_319 0x41004FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_320 0x4100500
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_321 0x4100504
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_322 0x4100508
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_323 0x410050C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_324 0x4100510
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_325 0x4100514
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_326 0x4100518
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_327 0x410051C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_328 0x4100520
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_329 0x4100524
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_330 0x4100528
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_331 0x410052C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_332 0x4100530
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_333 0x4100534
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_334 0x4100538
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_335 0x410053C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_336 0x4100540
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_337 0x4100544
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_338 0x4100548
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_339 0x410054C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_340 0x4100550
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_341 0x4100554
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_342 0x4100558
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_343 0x410055C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_344 0x4100560
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_345 0x4100564
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_346 0x4100568
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_347 0x410056C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_348 0x4100570
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_349 0x4100574
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_350 0x4100578
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_351 0x410057C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_352 0x4100580
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_353 0x4100584
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_354 0x4100588
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_355 0x410058C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_356 0x4100590
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_357 0x4100594
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_358 0x4100598
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_359 0x410059C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_360 0x41005A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_361 0x41005A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_362 0x41005A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_363 0x41005AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_364 0x41005B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_365 0x41005B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_366 0x41005B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_367 0x41005BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_368 0x41005C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_369 0x41005C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_370 0x41005C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_371 0x41005CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_372 0x41005D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_373 0x41005D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_374 0x41005D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_375 0x41005DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_376 0x41005E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_377 0x41005E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_378 0x41005E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_379 0x41005EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_380 0x41005F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_381 0x41005F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_382 0x41005F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_383 0x41005FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_384 0x4100600
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_385 0x4100604
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_386 0x4100608
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_387 0x410060C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_388 0x4100610
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_389 0x4100614
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_390 0x4100618
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_391 0x410061C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_392 0x4100620
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_393 0x4100624
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_394 0x4100628
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_395 0x410062C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_396 0x4100630
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_397 0x4100634
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_398 0x4100638
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_399 0x410063C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_400 0x4100640
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_401 0x4100644
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_402 0x4100648
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_403 0x410064C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_404 0x4100650
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_405 0x4100654
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_406 0x4100658
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_407 0x410065C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_408 0x4100660
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_409 0x4100664
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_410 0x4100668
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_411 0x410066C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_412 0x4100670
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_413 0x4100674
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_414 0x4100678
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_415 0x410067C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_416 0x4100680
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_417 0x4100684
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_418 0x4100688
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_419 0x410068C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_420 0x4100690
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_421 0x4100694
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_422 0x4100698
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_423 0x410069C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_424 0x41006A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_425 0x41006A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_426 0x41006A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_427 0x41006AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_428 0x41006B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_429 0x41006B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_430 0x41006B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_431 0x41006BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_432 0x41006C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_433 0x41006C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_434 0x41006C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_435 0x41006CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_436 0x41006D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_437 0x41006D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_438 0x41006D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_439 0x41006DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_440 0x41006E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_441 0x41006E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_442 0x41006E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_443 0x41006EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_444 0x41006F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_445 0x41006F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_446 0x41006F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_447 0x41006FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_448 0x4100700
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_449 0x4100704
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_450 0x4100708
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_451 0x410070C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_452 0x4100710
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_453 0x4100714
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_454 0x4100718
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_455 0x410071C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_456 0x4100720
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_457 0x4100724
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_458 0x4100728
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_459 0x410072C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_460 0x4100730
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_461 0x4100734
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_462 0x4100738
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_463 0x410073C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_464 0x4100740
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_465 0x4100744
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_466 0x4100748
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_467 0x410074C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_468 0x4100750
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_469 0x4100754
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_470 0x4100758
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_471 0x410075C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_472 0x4100760
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_473 0x4100764
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_474 0x4100768
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_475 0x410076C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_476 0x4100770
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_477 0x4100774
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_478 0x4100778
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_479 0x410077C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_480 0x4100780
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_481 0x4100784
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_482 0x4100788
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_483 0x410078C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_484 0x4100790
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_485 0x4100794
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_486 0x4100798
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_487 0x410079C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_488 0x41007A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_489 0x41007A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_490 0x41007A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_491 0x41007AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_492 0x41007B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_493 0x41007B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_494 0x41007B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_495 0x41007BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_496 0x41007C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_497 0x41007C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_498 0x41007C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_499 0x41007CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_500 0x41007D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_501 0x41007D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_502 0x41007D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_503 0x41007DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_504 0x41007E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_505 0x41007E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_506 0x41007E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_507 0x41007EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_508 0x41007F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_509 0x41007F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_510 0x41007F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_511 0x41007FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_512 0x4100800
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_513 0x4100804
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_514 0x4100808
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_515 0x410080C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_516 0x4100810
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_517 0x4100814
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_518 0x4100818
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_519 0x410081C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_520 0x4100820
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_521 0x4100824
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_522 0x4100828
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_523 0x410082C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_524 0x4100830
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_525 0x4100834
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_526 0x4100838
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_527 0x410083C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_528 0x4100840
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_529 0x4100844
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_530 0x4100848
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_531 0x410084C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_532 0x4100850
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_533 0x4100854
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_534 0x4100858
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_535 0x410085C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_536 0x4100860
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_537 0x4100864
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_538 0x4100868
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_539 0x410086C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_540 0x4100870
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_541 0x4100874
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_542 0x4100878
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_543 0x410087C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_544 0x4100880
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_545 0x4100884
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_546 0x4100888
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_547 0x410088C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_548 0x4100890
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_549 0x4100894
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_550 0x4100898
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_551 0x410089C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_552 0x41008A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_553 0x41008A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_554 0x41008A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_555 0x41008AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_556 0x41008B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_557 0x41008B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_558 0x41008B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_559 0x41008BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_560 0x41008C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_561 0x41008C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_562 0x41008C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_563 0x41008CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_564 0x41008D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_565 0x41008D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_566 0x41008D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_567 0x41008DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_568 0x41008E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_569 0x41008E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_570 0x41008E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_571 0x41008EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_572 0x41008F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_573 0x41008F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_574 0x41008F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_575 0x41008FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_576 0x4100900
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_577 0x4100904
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_578 0x4100908
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_579 0x410090C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_580 0x4100910
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_581 0x4100914
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_582 0x4100918
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_583 0x410091C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_584 0x4100920
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_585 0x4100924
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_586 0x4100928
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_587 0x410092C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_588 0x4100930
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_589 0x4100934
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_590 0x4100938
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_591 0x410093C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_592 0x4100940
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_593 0x4100944
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_594 0x4100948
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_595 0x410094C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_596 0x4100950
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_597 0x4100954
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_598 0x4100958
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_599 0x410095C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_600 0x4100960
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_601 0x4100964
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_602 0x4100968
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_603 0x410096C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_604 0x4100970
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_605 0x4100974
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_606 0x4100978
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_607 0x410097C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_608 0x4100980
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_609 0x4100984
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_610 0x4100988
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_611 0x410098C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_612 0x4100990
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_613 0x4100994
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_614 0x4100998
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_615 0x410099C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_616 0x41009A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_617 0x41009A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_618 0x41009A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_619 0x41009AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_620 0x41009B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_621 0x41009B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_622 0x41009B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_623 0x41009BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_624 0x41009C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_625 0x41009C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_626 0x41009C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_627 0x41009CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_628 0x41009D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_629 0x41009D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_630 0x41009D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_631 0x41009DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_632 0x41009E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_633 0x41009E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_634 0x41009E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_635 0x41009EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_636 0x41009F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_637 0x41009F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_638 0x41009F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_639 0x41009FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_640 0x4100A00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_641 0x4100A04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_642 0x4100A08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_643 0x4100A0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_644 0x4100A10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_645 0x4100A14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_646 0x4100A18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_647 0x4100A1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_648 0x4100A20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_649 0x4100A24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_650 0x4100A28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_651 0x4100A2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_652 0x4100A30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_653 0x4100A34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_654 0x4100A38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_655 0x4100A3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_656 0x4100A40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_657 0x4100A44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_658 0x4100A48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_659 0x4100A4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_660 0x4100A50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_661 0x4100A54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_662 0x4100A58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_663 0x4100A5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_664 0x4100A60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_665 0x4100A64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_666 0x4100A68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_667 0x4100A6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_668 0x4100A70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_669 0x4100A74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_670 0x4100A78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_671 0x4100A7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_672 0x4100A80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_673 0x4100A84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_674 0x4100A88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_675 0x4100A8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_676 0x4100A90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_677 0x4100A94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_678 0x4100A98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_679 0x4100A9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_680 0x4100AA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_681 0x4100AA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_682 0x4100AA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_683 0x4100AAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_684 0x4100AB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_685 0x4100AB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_686 0x4100AB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_687 0x4100ABC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_688 0x4100AC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_689 0x4100AC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_690 0x4100AC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_691 0x4100ACC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_692 0x4100AD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_693 0x4100AD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_694 0x4100AD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_695 0x4100ADC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_696 0x4100AE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_697 0x4100AE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_698 0x4100AE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_699 0x4100AEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_700 0x4100AF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_701 0x4100AF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_702 0x4100AF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_703 0x4100AFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_704 0x4100B00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_705 0x4100B04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_706 0x4100B08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_707 0x4100B0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_708 0x4100B10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_709 0x4100B14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_710 0x4100B18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_711 0x4100B1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_712 0x4100B20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_713 0x4100B24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_714 0x4100B28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_715 0x4100B2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_716 0x4100B30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_717 0x4100B34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_718 0x4100B38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_719 0x4100B3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_720 0x4100B40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_721 0x4100B44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_722 0x4100B48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_723 0x4100B4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_724 0x4100B50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_725 0x4100B54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_726 0x4100B58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_727 0x4100B5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_728 0x4100B60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_729 0x4100B64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_730 0x4100B68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_731 0x4100B6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_732 0x4100B70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_733 0x4100B74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_734 0x4100B78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_735 0x4100B7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_736 0x4100B80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_737 0x4100B84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_738 0x4100B88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_739 0x4100B8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_740 0x4100B90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_741 0x4100B94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_742 0x4100B98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_743 0x4100B9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_744 0x4100BA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_745 0x4100BA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_746 0x4100BA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_747 0x4100BAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_748 0x4100BB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_749 0x4100BB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_750 0x4100BB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_751 0x4100BBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_752 0x4100BC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_753 0x4100BC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_754 0x4100BC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_755 0x4100BCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_756 0x4100BD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_757 0x4100BD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_758 0x4100BD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_759 0x4100BDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_760 0x4100BE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_761 0x4100BE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_762 0x4100BE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_763 0x4100BEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_764 0x4100BF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_765 0x4100BF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_766 0x4100BF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_767 0x4100BFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_768 0x4100C00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_769 0x4100C04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_770 0x4100C08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_771 0x4100C0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_772 0x4100C10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_773 0x4100C14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_774 0x4100C18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_775 0x4100C1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_776 0x4100C20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_777 0x4100C24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_778 0x4100C28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_779 0x4100C2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_780 0x4100C30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_781 0x4100C34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_782 0x4100C38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_783 0x4100C3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_784 0x4100C40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_785 0x4100C44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_786 0x4100C48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_787 0x4100C4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_788 0x4100C50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_789 0x4100C54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_790 0x4100C58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_791 0x4100C5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_792 0x4100C60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_793 0x4100C64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_794 0x4100C68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_795 0x4100C6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_796 0x4100C70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_797 0x4100C74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_798 0x4100C78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_799 0x4100C7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_800 0x4100C80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_801 0x4100C84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_802 0x4100C88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_803 0x4100C8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_804 0x4100C90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_805 0x4100C94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_806 0x4100C98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_807 0x4100C9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_808 0x4100CA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_809 0x4100CA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_810 0x4100CA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_811 0x4100CAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_812 0x4100CB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_813 0x4100CB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_814 0x4100CB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_815 0x4100CBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_816 0x4100CC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_817 0x4100CC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_818 0x4100CC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_819 0x4100CCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_820 0x4100CD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_821 0x4100CD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_822 0x4100CD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_823 0x4100CDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_824 0x4100CE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_825 0x4100CE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_826 0x4100CE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_827 0x4100CEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_828 0x4100CF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_829 0x4100CF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_830 0x4100CF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_831 0x4100CFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_832 0x4100D00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_833 0x4100D04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_834 0x4100D08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_835 0x4100D0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_836 0x4100D10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_837 0x4100D14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_838 0x4100D18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_839 0x4100D1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_840 0x4100D20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_841 0x4100D24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_842 0x4100D28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_843 0x4100D2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_844 0x4100D30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_845 0x4100D34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_846 0x4100D38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_847 0x4100D3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_848 0x4100D40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_849 0x4100D44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_850 0x4100D48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_851 0x4100D4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_852 0x4100D50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_853 0x4100D54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_854 0x4100D58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_855 0x4100D5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_856 0x4100D60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_857 0x4100D64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_858 0x4100D68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_859 0x4100D6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_860 0x4100D70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_861 0x4100D74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_862 0x4100D78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_863 0x4100D7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_864 0x4100D80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_865 0x4100D84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_866 0x4100D88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_867 0x4100D8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_868 0x4100D90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_869 0x4100D94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_870 0x4100D98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_871 0x4100D9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_872 0x4100DA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_873 0x4100DA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_874 0x4100DA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_875 0x4100DAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_876 0x4100DB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_877 0x4100DB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_878 0x4100DB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_879 0x4100DBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_880 0x4100DC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_881 0x4100DC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_882 0x4100DC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_883 0x4100DCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_884 0x4100DD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_885 0x4100DD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_886 0x4100DD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_887 0x4100DDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_888 0x4100DE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_889 0x4100DE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_890 0x4100DE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_891 0x4100DEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_892 0x4100DF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_893 0x4100DF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_894 0x4100DF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_895 0x4100DFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_896 0x4100E00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_897 0x4100E04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_898 0x4100E08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_899 0x4100E0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_900 0x4100E10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_901 0x4100E14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_902 0x4100E18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_903 0x4100E1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_904 0x4100E20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_905 0x4100E24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_906 0x4100E28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_907 0x4100E2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_908 0x4100E30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_909 0x4100E34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_910 0x4100E38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_911 0x4100E3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_912 0x4100E40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_913 0x4100E44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_914 0x4100E48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_915 0x4100E4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_916 0x4100E50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_917 0x4100E54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_918 0x4100E58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_919 0x4100E5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_920 0x4100E60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_921 0x4100E64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_922 0x4100E68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_923 0x4100E6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_924 0x4100E70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_925 0x4100E74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_926 0x4100E78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_927 0x4100E7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_928 0x4100E80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_929 0x4100E84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_930 0x4100E88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_931 0x4100E8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_932 0x4100E90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_933 0x4100E94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_934 0x4100E98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_935 0x4100E9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_936 0x4100EA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_937 0x4100EA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_938 0x4100EA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_939 0x4100EAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_940 0x4100EB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_941 0x4100EB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_942 0x4100EB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_943 0x4100EBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_944 0x4100EC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_945 0x4100EC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_946 0x4100EC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_947 0x4100ECC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_948 0x4100ED0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_949 0x4100ED4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_950 0x4100ED8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_951 0x4100EDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_952 0x4100EE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_953 0x4100EE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_954 0x4100EE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_955 0x4100EEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_956 0x4100EF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_957 0x4100EF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_958 0x4100EF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_959 0x4100EFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_960 0x4100F00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_961 0x4100F04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_962 0x4100F08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_963 0x4100F0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_964 0x4100F10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_965 0x4100F14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_966 0x4100F18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_967 0x4100F1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_968 0x4100F20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_969 0x4100F24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_970 0x4100F28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_971 0x4100F2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_972 0x4100F30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_973 0x4100F34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_974 0x4100F38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_975 0x4100F3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_976 0x4100F40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_977 0x4100F44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_978 0x4100F48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_979 0x4100F4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_980 0x4100F50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_981 0x4100F54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_982 0x4100F58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_983 0x4100F5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_984 0x4100F60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_985 0x4100F64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_986 0x4100F68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_987 0x4100F6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_988 0x4100F70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_989 0x4100F74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_990 0x4100F78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_991 0x4100F7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_992 0x4100F80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_993 0x4100F84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_994 0x4100F88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_995 0x4100F8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_996 0x4100F90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_997 0x4100F94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_998 0x4100F98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_999 0x4100F9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1000 0x4100FA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1001 0x4100FA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1002 0x4100FA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1003 0x4100FAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1004 0x4100FB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1005 0x4100FB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1006 0x4100FB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1007 0x4100FBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1008 0x4100FC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1009 0x4100FC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1010 0x4100FC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1011 0x4100FCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1012 0x4100FD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1013 0x4100FD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1014 0x4100FD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1015 0x4100FDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1016 0x4100FE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1017 0x4100FE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1018 0x4100FE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1019 0x4100FEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1020 0x4100FF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1021 0x4100FF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1022 0x4100FF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1023 0x4100FFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1024 0x4101000
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1025 0x4101004
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1026 0x4101008
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1027 0x410100C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1028 0x4101010
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1029 0x4101014
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1030 0x4101018
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1031 0x410101C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1032 0x4101020
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1033 0x4101024
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1034 0x4101028
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1035 0x410102C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1036 0x4101030
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1037 0x4101034
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1038 0x4101038
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1039 0x410103C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1040 0x4101040
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1041 0x4101044
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1042 0x4101048
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1043 0x410104C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1044 0x4101050
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1045 0x4101054
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1046 0x4101058
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1047 0x410105C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1048 0x4101060
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1049 0x4101064
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1050 0x4101068
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1051 0x410106C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1052 0x4101070
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1053 0x4101074
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1054 0x4101078
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1055 0x410107C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1056 0x4101080
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1057 0x4101084
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1058 0x4101088
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1059 0x410108C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1060 0x4101090
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1061 0x4101094
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1062 0x4101098
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1063 0x410109C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1064 0x41010A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1065 0x41010A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1066 0x41010A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1067 0x41010AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1068 0x41010B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1069 0x41010B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1070 0x41010B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1071 0x41010BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1072 0x41010C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1073 0x41010C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1074 0x41010C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1075 0x41010CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1076 0x41010D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1077 0x41010D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1078 0x41010D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1079 0x41010DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1080 0x41010E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1081 0x41010E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1082 0x41010E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1083 0x41010EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1084 0x41010F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1085 0x41010F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1086 0x41010F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1087 0x41010FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1088 0x4101100
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1089 0x4101104
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1090 0x4101108
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1091 0x410110C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1092 0x4101110
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1093 0x4101114
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1094 0x4101118
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1095 0x410111C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1096 0x4101120
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1097 0x4101124
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1098 0x4101128
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1099 0x410112C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1100 0x4101130
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1101 0x4101134
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1102 0x4101138
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1103 0x410113C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1104 0x4101140
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1105 0x4101144
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1106 0x4101148
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1107 0x410114C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1108 0x4101150
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1109 0x4101154
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1110 0x4101158
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1111 0x410115C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1112 0x4101160
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1113 0x4101164
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1114 0x4101168
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1115 0x410116C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1116 0x4101170
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1117 0x4101174
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1118 0x4101178
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1119 0x410117C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1120 0x4101180
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1121 0x4101184
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1122 0x4101188
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1123 0x410118C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1124 0x4101190
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1125 0x4101194
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1126 0x4101198
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1127 0x410119C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1128 0x41011A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1129 0x41011A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1130 0x41011A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1131 0x41011AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1132 0x41011B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1133 0x41011B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1134 0x41011B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1135 0x41011BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1136 0x41011C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1137 0x41011C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1138 0x41011C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1139 0x41011CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1140 0x41011D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1141 0x41011D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1142 0x41011D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1143 0x41011DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1144 0x41011E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1145 0x41011E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1146 0x41011E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1147 0x41011EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1148 0x41011F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1149 0x41011F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1150 0x41011F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1151 0x41011FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1152 0x4101200
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1153 0x4101204
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1154 0x4101208
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1155 0x410120C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1156 0x4101210
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1157 0x4101214
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1158 0x4101218
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1159 0x410121C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1160 0x4101220
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1161 0x4101224
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1162 0x4101228
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1163 0x410122C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1164 0x4101230
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1165 0x4101234
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1166 0x4101238
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1167 0x410123C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1168 0x4101240
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1169 0x4101244
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1170 0x4101248
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1171 0x410124C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1172 0x4101250
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1173 0x4101254
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1174 0x4101258
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1175 0x410125C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1176 0x4101260
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1177 0x4101264
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1178 0x4101268
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1179 0x410126C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1180 0x4101270
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1181 0x4101274
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1182 0x4101278
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1183 0x410127C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1184 0x4101280
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1185 0x4101284
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1186 0x4101288
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1187 0x410128C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1188 0x4101290
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1189 0x4101294
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1190 0x4101298
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1191 0x410129C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1192 0x41012A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1193 0x41012A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1194 0x41012A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1195 0x41012AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1196 0x41012B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1197 0x41012B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1198 0x41012B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1199 0x41012BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1200 0x41012C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1201 0x41012C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1202 0x41012C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1203 0x41012CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1204 0x41012D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1205 0x41012D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1206 0x41012D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1207 0x41012DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1208 0x41012E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1209 0x41012E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1210 0x41012E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1211 0x41012EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1212 0x41012F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1213 0x41012F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1214 0x41012F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1215 0x41012FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1216 0x4101300
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1217 0x4101304
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1218 0x4101308
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1219 0x410130C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1220 0x4101310
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1221 0x4101314
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1222 0x4101318
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1223 0x410131C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1224 0x4101320
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1225 0x4101324
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1226 0x4101328
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1227 0x410132C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1228 0x4101330
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1229 0x4101334
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1230 0x4101338
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1231 0x410133C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1232 0x4101340
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1233 0x4101344
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1234 0x4101348
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1235 0x410134C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1236 0x4101350
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1237 0x4101354
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1238 0x4101358
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1239 0x410135C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1240 0x4101360
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1241 0x4101364
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1242 0x4101368
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1243 0x410136C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1244 0x4101370
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1245 0x4101374
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1246 0x4101378
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1247 0x410137C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1248 0x4101380
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1249 0x4101384
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1250 0x4101388
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1251 0x410138C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1252 0x4101390
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1253 0x4101394
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1254 0x4101398
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1255 0x410139C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1256 0x41013A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1257 0x41013A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1258 0x41013A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1259 0x41013AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1260 0x41013B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1261 0x41013B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1262 0x41013B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1263 0x41013BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1264 0x41013C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1265 0x41013C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1266 0x41013C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1267 0x41013CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1268 0x41013D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1269 0x41013D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1270 0x41013D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1271 0x41013DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1272 0x41013E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1273 0x41013E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1274 0x41013E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1275 0x41013EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1276 0x41013F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1277 0x41013F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1278 0x41013F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1279 0x41013FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1280 0x4101400
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1281 0x4101404
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1282 0x4101408
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1283 0x410140C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1284 0x4101410
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1285 0x4101414
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1286 0x4101418
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1287 0x410141C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1288 0x4101420
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1289 0x4101424
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1290 0x4101428
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1291 0x410142C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1292 0x4101430
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1293 0x4101434
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1294 0x4101438
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1295 0x410143C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1296 0x4101440
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1297 0x4101444
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1298 0x4101448
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1299 0x410144C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1300 0x4101450
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1301 0x4101454
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1302 0x4101458
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1303 0x410145C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1304 0x4101460
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1305 0x4101464
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1306 0x4101468
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1307 0x410146C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1308 0x4101470
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1309 0x4101474
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1310 0x4101478
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1311 0x410147C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1312 0x4101480
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1313 0x4101484
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1314 0x4101488
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1315 0x410148C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1316 0x4101490
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1317 0x4101494
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1318 0x4101498
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1319 0x410149C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1320 0x41014A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1321 0x41014A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1322 0x41014A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1323 0x41014AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1324 0x41014B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1325 0x41014B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1326 0x41014B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1327 0x41014BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1328 0x41014C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1329 0x41014C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1330 0x41014C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1331 0x41014CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1332 0x41014D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1333 0x41014D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1334 0x41014D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1335 0x41014DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1336 0x41014E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1337 0x41014E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1338 0x41014E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1339 0x41014EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1340 0x41014F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1341 0x41014F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1342 0x41014F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1343 0x41014FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1344 0x4101500
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1345 0x4101504
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1346 0x4101508
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1347 0x410150C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1348 0x4101510
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1349 0x4101514
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1350 0x4101518
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1351 0x410151C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1352 0x4101520
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1353 0x4101524
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1354 0x4101528
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1355 0x410152C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1356 0x4101530
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1357 0x4101534
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1358 0x4101538
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1359 0x410153C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1360 0x4101540
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1361 0x4101544
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1362 0x4101548
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1363 0x410154C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1364 0x4101550
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1365 0x4101554
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1366 0x4101558
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1367 0x410155C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1368 0x4101560
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1369 0x4101564
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1370 0x4101568
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1371 0x410156C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1372 0x4101570
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1373 0x4101574
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1374 0x4101578
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1375 0x410157C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1376 0x4101580
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1377 0x4101584
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1378 0x4101588
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1379 0x410158C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1380 0x4101590
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1381 0x4101594
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1382 0x4101598
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1383 0x410159C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1384 0x41015A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1385 0x41015A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1386 0x41015A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1387 0x41015AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1388 0x41015B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1389 0x41015B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1390 0x41015B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1391 0x41015BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1392 0x41015C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1393 0x41015C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1394 0x41015C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1395 0x41015CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1396 0x41015D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1397 0x41015D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1398 0x41015D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1399 0x41015DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1400 0x41015E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1401 0x41015E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1402 0x41015E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1403 0x41015EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1404 0x41015F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1405 0x41015F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1406 0x41015F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1407 0x41015FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1408 0x4101600
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1409 0x4101604
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1410 0x4101608
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1411 0x410160C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1412 0x4101610
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1413 0x4101614
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1414 0x4101618
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1415 0x410161C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1416 0x4101620
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1417 0x4101624
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1418 0x4101628
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1419 0x410162C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1420 0x4101630
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1421 0x4101634
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1422 0x4101638
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1423 0x410163C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1424 0x4101640
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1425 0x4101644
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1426 0x4101648
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1427 0x410164C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1428 0x4101650
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1429 0x4101654
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1430 0x4101658
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1431 0x410165C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1432 0x4101660
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1433 0x4101664
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1434 0x4101668
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1435 0x410166C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1436 0x4101670
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1437 0x4101674
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1438 0x4101678
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1439 0x410167C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1440 0x4101680
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1441 0x4101684
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1442 0x4101688
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1443 0x410168C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1444 0x4101690
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1445 0x4101694
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1446 0x4101698
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1447 0x410169C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1448 0x41016A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1449 0x41016A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1450 0x41016A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1451 0x41016AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1452 0x41016B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1453 0x41016B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1454 0x41016B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1455 0x41016BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1456 0x41016C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1457 0x41016C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1458 0x41016C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1459 0x41016CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1460 0x41016D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1461 0x41016D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1462 0x41016D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1463 0x41016DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1464 0x41016E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1465 0x41016E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1466 0x41016E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1467 0x41016EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1468 0x41016F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1469 0x41016F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1470 0x41016F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1471 0x41016FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1472 0x4101700
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1473 0x4101704
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1474 0x4101708
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1475 0x410170C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1476 0x4101710
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1477 0x4101714
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1478 0x4101718
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1479 0x410171C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1480 0x4101720
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1481 0x4101724
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1482 0x4101728
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1483 0x410172C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1484 0x4101730
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1485 0x4101734
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1486 0x4101738
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1487 0x410173C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1488 0x4101740
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1489 0x4101744
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1490 0x4101748
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1491 0x410174C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1492 0x4101750
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1493 0x4101754
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1494 0x4101758
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1495 0x410175C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1496 0x4101760
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1497 0x4101764
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1498 0x4101768
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1499 0x410176C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1500 0x4101770
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1501 0x4101774
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1502 0x4101778
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1503 0x410177C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1504 0x4101780
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1505 0x4101784
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1506 0x4101788
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1507 0x410178C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1508 0x4101790
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1509 0x4101794
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1510 0x4101798
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1511 0x410179C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1512 0x41017A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1513 0x41017A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1514 0x41017A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1515 0x41017AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1516 0x41017B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1517 0x41017B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1518 0x41017B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1519 0x41017BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1520 0x41017C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1521 0x41017C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1522 0x41017C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1523 0x41017CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1524 0x41017D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1525 0x41017D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1526 0x41017D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1527 0x41017DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1528 0x41017E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1529 0x41017E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1530 0x41017E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1531 0x41017EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1532 0x41017F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1533 0x41017F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1534 0x41017F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1535 0x41017FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1536 0x4101800
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1537 0x4101804
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1538 0x4101808
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1539 0x410180C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1540 0x4101810
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1541 0x4101814
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1542 0x4101818
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1543 0x410181C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1544 0x4101820
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1545 0x4101824
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1546 0x4101828
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1547 0x410182C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1548 0x4101830
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1549 0x4101834
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1550 0x4101838
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1551 0x410183C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1552 0x4101840
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1553 0x4101844
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1554 0x4101848
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1555 0x410184C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1556 0x4101850
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1557 0x4101854
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1558 0x4101858
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1559 0x410185C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1560 0x4101860
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1561 0x4101864
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1562 0x4101868
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1563 0x410186C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1564 0x4101870
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1565 0x4101874
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1566 0x4101878
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1567 0x410187C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1568 0x4101880
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1569 0x4101884
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1570 0x4101888
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1571 0x410188C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1572 0x4101890
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1573 0x4101894
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1574 0x4101898
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1575 0x410189C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1576 0x41018A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1577 0x41018A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1578 0x41018A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1579 0x41018AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1580 0x41018B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1581 0x41018B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1582 0x41018B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1583 0x41018BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1584 0x41018C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1585 0x41018C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1586 0x41018C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1587 0x41018CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1588 0x41018D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1589 0x41018D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1590 0x41018D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1591 0x41018DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1592 0x41018E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1593 0x41018E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1594 0x41018E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1595 0x41018EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1596 0x41018F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1597 0x41018F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1598 0x41018F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1599 0x41018FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1600 0x4101900
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1601 0x4101904
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1602 0x4101908
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1603 0x410190C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1604 0x4101910
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1605 0x4101914
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1606 0x4101918
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1607 0x410191C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1608 0x4101920
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1609 0x4101924
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1610 0x4101928
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1611 0x410192C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1612 0x4101930
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1613 0x4101934
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1614 0x4101938
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1615 0x410193C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1616 0x4101940
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1617 0x4101944
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1618 0x4101948
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1619 0x410194C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1620 0x4101950
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1621 0x4101954
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1622 0x4101958
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1623 0x410195C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1624 0x4101960
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1625 0x4101964
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1626 0x4101968
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1627 0x410196C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1628 0x4101970
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1629 0x4101974
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1630 0x4101978
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1631 0x410197C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1632 0x4101980
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1633 0x4101984
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1634 0x4101988
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1635 0x410198C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1636 0x4101990
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1637 0x4101994
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1638 0x4101998
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1639 0x410199C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1640 0x41019A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1641 0x41019A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1642 0x41019A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1643 0x41019AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1644 0x41019B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1645 0x41019B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1646 0x41019B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1647 0x41019BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1648 0x41019C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1649 0x41019C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1650 0x41019C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1651 0x41019CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1652 0x41019D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1653 0x41019D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1654 0x41019D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1655 0x41019DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1656 0x41019E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1657 0x41019E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1658 0x41019E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1659 0x41019EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1660 0x41019F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1661 0x41019F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1662 0x41019F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1663 0x41019FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1664 0x4101A00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1665 0x4101A04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1666 0x4101A08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1667 0x4101A0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1668 0x4101A10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1669 0x4101A14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1670 0x4101A18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1671 0x4101A1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1672 0x4101A20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1673 0x4101A24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1674 0x4101A28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1675 0x4101A2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1676 0x4101A30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1677 0x4101A34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1678 0x4101A38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1679 0x4101A3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1680 0x4101A40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1681 0x4101A44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1682 0x4101A48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1683 0x4101A4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1684 0x4101A50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1685 0x4101A54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1686 0x4101A58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1687 0x4101A5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1688 0x4101A60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1689 0x4101A64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1690 0x4101A68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1691 0x4101A6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1692 0x4101A70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1693 0x4101A74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1694 0x4101A78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1695 0x4101A7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1696 0x4101A80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1697 0x4101A84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1698 0x4101A88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1699 0x4101A8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1700 0x4101A90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1701 0x4101A94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1702 0x4101A98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1703 0x4101A9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1704 0x4101AA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1705 0x4101AA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1706 0x4101AA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1707 0x4101AAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1708 0x4101AB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1709 0x4101AB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1710 0x4101AB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1711 0x4101ABC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1712 0x4101AC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1713 0x4101AC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1714 0x4101AC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1715 0x4101ACC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1716 0x4101AD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1717 0x4101AD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1718 0x4101AD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1719 0x4101ADC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1720 0x4101AE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1721 0x4101AE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1722 0x4101AE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1723 0x4101AEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1724 0x4101AF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1725 0x4101AF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1726 0x4101AF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1727 0x4101AFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1728 0x4101B00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1729 0x4101B04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1730 0x4101B08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1731 0x4101B0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1732 0x4101B10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1733 0x4101B14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1734 0x4101B18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1735 0x4101B1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1736 0x4101B20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1737 0x4101B24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1738 0x4101B28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1739 0x4101B2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1740 0x4101B30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1741 0x4101B34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1742 0x4101B38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1743 0x4101B3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1744 0x4101B40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1745 0x4101B44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1746 0x4101B48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1747 0x4101B4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1748 0x4101B50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1749 0x4101B54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1750 0x4101B58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1751 0x4101B5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1752 0x4101B60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1753 0x4101B64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1754 0x4101B68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1755 0x4101B6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1756 0x4101B70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1757 0x4101B74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1758 0x4101B78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1759 0x4101B7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1760 0x4101B80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1761 0x4101B84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1762 0x4101B88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1763 0x4101B8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1764 0x4101B90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1765 0x4101B94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1766 0x4101B98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1767 0x4101B9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1768 0x4101BA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1769 0x4101BA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1770 0x4101BA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1771 0x4101BAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1772 0x4101BB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1773 0x4101BB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1774 0x4101BB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1775 0x4101BBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1776 0x4101BC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1777 0x4101BC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1778 0x4101BC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1779 0x4101BCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1780 0x4101BD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1781 0x4101BD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1782 0x4101BD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1783 0x4101BDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1784 0x4101BE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1785 0x4101BE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1786 0x4101BE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1787 0x4101BEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1788 0x4101BF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1789 0x4101BF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1790 0x4101BF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1791 0x4101BFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1792 0x4101C00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1793 0x4101C04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1794 0x4101C08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1795 0x4101C0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1796 0x4101C10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1797 0x4101C14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1798 0x4101C18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1799 0x4101C1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1800 0x4101C20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1801 0x4101C24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1802 0x4101C28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1803 0x4101C2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1804 0x4101C30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1805 0x4101C34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1806 0x4101C38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1807 0x4101C3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1808 0x4101C40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1809 0x4101C44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1810 0x4101C48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1811 0x4101C4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1812 0x4101C50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1813 0x4101C54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1814 0x4101C58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1815 0x4101C5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1816 0x4101C60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1817 0x4101C64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1818 0x4101C68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1819 0x4101C6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1820 0x4101C70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1821 0x4101C74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1822 0x4101C78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1823 0x4101C7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1824 0x4101C80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1825 0x4101C84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1826 0x4101C88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1827 0x4101C8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1828 0x4101C90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1829 0x4101C94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1830 0x4101C98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1831 0x4101C9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1832 0x4101CA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1833 0x4101CA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1834 0x4101CA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1835 0x4101CAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1836 0x4101CB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1837 0x4101CB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1838 0x4101CB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1839 0x4101CBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1840 0x4101CC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1841 0x4101CC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1842 0x4101CC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1843 0x4101CCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1844 0x4101CD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1845 0x4101CD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1846 0x4101CD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1847 0x4101CDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1848 0x4101CE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1849 0x4101CE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1850 0x4101CE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1851 0x4101CEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1852 0x4101CF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1853 0x4101CF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1854 0x4101CF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1855 0x4101CFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1856 0x4101D00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1857 0x4101D04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1858 0x4101D08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1859 0x4101D0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1860 0x4101D10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1861 0x4101D14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1862 0x4101D18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1863 0x4101D1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1864 0x4101D20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1865 0x4101D24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1866 0x4101D28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1867 0x4101D2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1868 0x4101D30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1869 0x4101D34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1870 0x4101D38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1871 0x4101D3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1872 0x4101D40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1873 0x4101D44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1874 0x4101D48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1875 0x4101D4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1876 0x4101D50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1877 0x4101D54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1878 0x4101D58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1879 0x4101D5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1880 0x4101D60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1881 0x4101D64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1882 0x4101D68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1883 0x4101D6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1884 0x4101D70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1885 0x4101D74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1886 0x4101D78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1887 0x4101D7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1888 0x4101D80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1889 0x4101D84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1890 0x4101D88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1891 0x4101D8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1892 0x4101D90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1893 0x4101D94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1894 0x4101D98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1895 0x4101D9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1896 0x4101DA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1897 0x4101DA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1898 0x4101DA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1899 0x4101DAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1900 0x4101DB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1901 0x4101DB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1902 0x4101DB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1903 0x4101DBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1904 0x4101DC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1905 0x4101DC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1906 0x4101DC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1907 0x4101DCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1908 0x4101DD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1909 0x4101DD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1910 0x4101DD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1911 0x4101DDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1912 0x4101DE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1913 0x4101DE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1914 0x4101DE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1915 0x4101DEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1916 0x4101DF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1917 0x4101DF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1918 0x4101DF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1919 0x4101DFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1920 0x4101E00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1921 0x4101E04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1922 0x4101E08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1923 0x4101E0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1924 0x4101E10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1925 0x4101E14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1926 0x4101E18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1927 0x4101E1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1928 0x4101E20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1929 0x4101E24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1930 0x4101E28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1931 0x4101E2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1932 0x4101E30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1933 0x4101E34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1934 0x4101E38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1935 0x4101E3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1936 0x4101E40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1937 0x4101E44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1938 0x4101E48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1939 0x4101E4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1940 0x4101E50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1941 0x4101E54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1942 0x4101E58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1943 0x4101E5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1944 0x4101E60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1945 0x4101E64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1946 0x4101E68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1947 0x4101E6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1948 0x4101E70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1949 0x4101E74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1950 0x4101E78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1951 0x4101E7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1952 0x4101E80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1953 0x4101E84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1954 0x4101E88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1955 0x4101E8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1956 0x4101E90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1957 0x4101E94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1958 0x4101E98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1959 0x4101E9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1960 0x4101EA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1961 0x4101EA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1962 0x4101EA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1963 0x4101EAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1964 0x4101EB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1965 0x4101EB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1966 0x4101EB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1967 0x4101EBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1968 0x4101EC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1969 0x4101EC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1970 0x4101EC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1971 0x4101ECC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1972 0x4101ED0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1973 0x4101ED4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1974 0x4101ED8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1975 0x4101EDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1976 0x4101EE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1977 0x4101EE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1978 0x4101EE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1979 0x4101EEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1980 0x4101EF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1981 0x4101EF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1982 0x4101EF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1983 0x4101EFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1984 0x4101F00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1985 0x4101F04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1986 0x4101F08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1987 0x4101F0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1988 0x4101F10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1989 0x4101F14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1990 0x4101F18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1991 0x4101F1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1992 0x4101F20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1993 0x4101F24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1994 0x4101F28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1995 0x4101F2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1996 0x4101F30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1997 0x4101F34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1998 0x4101F38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_1999 0x4101F3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2000 0x4101F40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2001 0x4101F44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2002 0x4101F48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2003 0x4101F4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2004 0x4101F50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2005 0x4101F54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2006 0x4101F58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2007 0x4101F5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2008 0x4101F60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2009 0x4101F64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2010 0x4101F68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2011 0x4101F6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2012 0x4101F70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2013 0x4101F74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2014 0x4101F78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2015 0x4101F7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2016 0x4101F80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2017 0x4101F84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2018 0x4101F88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2019 0x4101F8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2020 0x4101F90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2021 0x4101F94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2022 0x4101F98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2023 0x4101F9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2024 0x4101FA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2025 0x4101FA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2026 0x4101FA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2027 0x4101FAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2028 0x4101FB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2029 0x4101FB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2030 0x4101FB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2031 0x4101FBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2032 0x4101FC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2033 0x4101FC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2034 0x4101FC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2035 0x4101FCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2036 0x4101FD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2037 0x4101FD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2038 0x4101FD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2039 0x4101FDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2040 0x4101FE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2041 0x4101FE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2042 0x4101FE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2043 0x4101FEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2044 0x4101FF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2045 0x4101FF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2046 0x4101FF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2047 0x4101FFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2048 0x4102000
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2049 0x4102004
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2050 0x4102008
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2051 0x410200C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2052 0x4102010
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2053 0x4102014
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2054 0x4102018
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2055 0x410201C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2056 0x4102020
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2057 0x4102024
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2058 0x4102028
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2059 0x410202C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2060 0x4102030
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2061 0x4102034
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2062 0x4102038
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2063 0x410203C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2064 0x4102040
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2065 0x4102044
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2066 0x4102048
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2067 0x410204C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2068 0x4102050
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2069 0x4102054
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2070 0x4102058
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2071 0x410205C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2072 0x4102060
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2073 0x4102064
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2074 0x4102068
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2075 0x410206C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2076 0x4102070
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2077 0x4102074
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2078 0x4102078
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2079 0x410207C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2080 0x4102080
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2081 0x4102084
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2082 0x4102088
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2083 0x410208C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2084 0x4102090
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2085 0x4102094
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2086 0x4102098
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2087 0x410209C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2088 0x41020A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2089 0x41020A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2090 0x41020A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2091 0x41020AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2092 0x41020B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2093 0x41020B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2094 0x41020B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2095 0x41020BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2096 0x41020C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2097 0x41020C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2098 0x41020C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2099 0x41020CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2100 0x41020D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2101 0x41020D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2102 0x41020D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2103 0x41020DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2104 0x41020E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2105 0x41020E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2106 0x41020E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2107 0x41020EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2108 0x41020F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2109 0x41020F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2110 0x41020F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2111 0x41020FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2112 0x4102100
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2113 0x4102104
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2114 0x4102108
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2115 0x410210C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2116 0x4102110
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2117 0x4102114
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2118 0x4102118
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2119 0x410211C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2120 0x4102120
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2121 0x4102124
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2122 0x4102128
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2123 0x410212C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2124 0x4102130
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2125 0x4102134
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2126 0x4102138
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2127 0x410213C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2128 0x4102140
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2129 0x4102144
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2130 0x4102148
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2131 0x410214C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2132 0x4102150
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2133 0x4102154
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2134 0x4102158
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2135 0x410215C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2136 0x4102160
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2137 0x4102164
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2138 0x4102168
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2139 0x410216C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2140 0x4102170
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2141 0x4102174
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2142 0x4102178
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2143 0x410217C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2144 0x4102180
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2145 0x4102184
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2146 0x4102188
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2147 0x410218C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2148 0x4102190
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2149 0x4102194
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2150 0x4102198
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2151 0x410219C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2152 0x41021A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2153 0x41021A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2154 0x41021A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2155 0x41021AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2156 0x41021B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2157 0x41021B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2158 0x41021B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2159 0x41021BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2160 0x41021C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2161 0x41021C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2162 0x41021C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2163 0x41021CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2164 0x41021D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2165 0x41021D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2166 0x41021D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2167 0x41021DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2168 0x41021E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2169 0x41021E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2170 0x41021E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2171 0x41021EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2172 0x41021F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2173 0x41021F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2174 0x41021F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2175 0x41021FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2176 0x4102200
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2177 0x4102204
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2178 0x4102208
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2179 0x410220C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2180 0x4102210
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2181 0x4102214
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2182 0x4102218
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2183 0x410221C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2184 0x4102220
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2185 0x4102224
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2186 0x4102228
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2187 0x410222C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2188 0x4102230
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2189 0x4102234
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2190 0x4102238
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2191 0x410223C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2192 0x4102240
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2193 0x4102244
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2194 0x4102248
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2195 0x410224C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2196 0x4102250
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2197 0x4102254
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2198 0x4102258
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2199 0x410225C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2200 0x4102260
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2201 0x4102264
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2202 0x4102268
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2203 0x410226C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2204 0x4102270
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2205 0x4102274
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2206 0x4102278
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2207 0x410227C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2208 0x4102280
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2209 0x4102284
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2210 0x4102288
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2211 0x410228C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2212 0x4102290
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2213 0x4102294
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2214 0x4102298
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2215 0x410229C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2216 0x41022A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2217 0x41022A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2218 0x41022A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2219 0x41022AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2220 0x41022B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2221 0x41022B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2222 0x41022B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2223 0x41022BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2224 0x41022C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2225 0x41022C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2226 0x41022C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2227 0x41022CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2228 0x41022D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2229 0x41022D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2230 0x41022D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2231 0x41022DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2232 0x41022E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2233 0x41022E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2234 0x41022E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2235 0x41022EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2236 0x41022F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2237 0x41022F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2238 0x41022F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2239 0x41022FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2240 0x4102300
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2241 0x4102304
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2242 0x4102308
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2243 0x410230C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2244 0x4102310
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2245 0x4102314
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2246 0x4102318
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2247 0x410231C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2248 0x4102320
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2249 0x4102324
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2250 0x4102328
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2251 0x410232C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2252 0x4102330
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2253 0x4102334
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2254 0x4102338
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2255 0x410233C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2256 0x4102340
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2257 0x4102344
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2258 0x4102348
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2259 0x410234C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2260 0x4102350
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2261 0x4102354
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2262 0x4102358
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2263 0x410235C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2264 0x4102360
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2265 0x4102364
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2266 0x4102368
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2267 0x410236C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2268 0x4102370
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2269 0x4102374
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2270 0x4102378
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2271 0x410237C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2272 0x4102380
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2273 0x4102384
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2274 0x4102388
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2275 0x410238C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2276 0x4102390
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2277 0x4102394
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2278 0x4102398
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2279 0x410239C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2280 0x41023A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2281 0x41023A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2282 0x41023A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2283 0x41023AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2284 0x41023B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2285 0x41023B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2286 0x41023B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2287 0x41023BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2288 0x41023C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2289 0x41023C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2290 0x41023C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2291 0x41023CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2292 0x41023D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2293 0x41023D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2294 0x41023D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2295 0x41023DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2296 0x41023E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2297 0x41023E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2298 0x41023E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2299 0x41023EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2300 0x41023F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2301 0x41023F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2302 0x41023F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2303 0x41023FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2304 0x4102400
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2305 0x4102404
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2306 0x4102408
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2307 0x410240C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2308 0x4102410
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2309 0x4102414
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2310 0x4102418
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2311 0x410241C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2312 0x4102420
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2313 0x4102424
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2314 0x4102428
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2315 0x410242C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2316 0x4102430
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2317 0x4102434
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2318 0x4102438
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2319 0x410243C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2320 0x4102440
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2321 0x4102444
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2322 0x4102448
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2323 0x410244C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2324 0x4102450
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2325 0x4102454
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2326 0x4102458
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2327 0x410245C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2328 0x4102460
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2329 0x4102464
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2330 0x4102468
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2331 0x410246C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2332 0x4102470
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2333 0x4102474
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2334 0x4102478
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2335 0x410247C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2336 0x4102480
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2337 0x4102484
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2338 0x4102488
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2339 0x410248C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2340 0x4102490
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2341 0x4102494
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2342 0x4102498
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2343 0x410249C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2344 0x41024A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2345 0x41024A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2346 0x41024A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2347 0x41024AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2348 0x41024B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2349 0x41024B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2350 0x41024B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2351 0x41024BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2352 0x41024C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2353 0x41024C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2354 0x41024C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2355 0x41024CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2356 0x41024D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2357 0x41024D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2358 0x41024D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2359 0x41024DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2360 0x41024E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2361 0x41024E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2362 0x41024E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2363 0x41024EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2364 0x41024F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2365 0x41024F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2366 0x41024F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2367 0x41024FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2368 0x4102500
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2369 0x4102504
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2370 0x4102508
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2371 0x410250C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2372 0x4102510
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2373 0x4102514
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2374 0x4102518
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2375 0x410251C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2376 0x4102520
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2377 0x4102524
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2378 0x4102528
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2379 0x410252C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2380 0x4102530
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2381 0x4102534
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2382 0x4102538
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2383 0x410253C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2384 0x4102540
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2385 0x4102544
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2386 0x4102548
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2387 0x410254C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2388 0x4102550
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2389 0x4102554
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2390 0x4102558
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2391 0x410255C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2392 0x4102560
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2393 0x4102564
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2394 0x4102568
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2395 0x410256C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2396 0x4102570
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2397 0x4102574
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2398 0x4102578
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2399 0x410257C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2400 0x4102580
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2401 0x4102584
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2402 0x4102588
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2403 0x410258C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2404 0x4102590
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2405 0x4102594
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2406 0x4102598
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2407 0x410259C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2408 0x41025A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2409 0x41025A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2410 0x41025A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2411 0x41025AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2412 0x41025B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2413 0x41025B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2414 0x41025B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2415 0x41025BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2416 0x41025C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2417 0x41025C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2418 0x41025C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2419 0x41025CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2420 0x41025D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2421 0x41025D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2422 0x41025D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2423 0x41025DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2424 0x41025E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2425 0x41025E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2426 0x41025E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2427 0x41025EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2428 0x41025F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2429 0x41025F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2430 0x41025F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2431 0x41025FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2432 0x4102600
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2433 0x4102604
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2434 0x4102608
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2435 0x410260C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2436 0x4102610
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2437 0x4102614
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2438 0x4102618
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2439 0x410261C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2440 0x4102620
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2441 0x4102624
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2442 0x4102628
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2443 0x410262C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2444 0x4102630
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2445 0x4102634
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2446 0x4102638
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2447 0x410263C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2448 0x4102640
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2449 0x4102644
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2450 0x4102648
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2451 0x410264C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2452 0x4102650
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2453 0x4102654
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2454 0x4102658
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2455 0x410265C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2456 0x4102660
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2457 0x4102664
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2458 0x4102668
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2459 0x410266C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2460 0x4102670
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2461 0x4102674
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2462 0x4102678
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2463 0x410267C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2464 0x4102680
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2465 0x4102684
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2466 0x4102688
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2467 0x410268C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2468 0x4102690
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2469 0x4102694
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2470 0x4102698
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2471 0x410269C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2472 0x41026A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2473 0x41026A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2474 0x41026A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2475 0x41026AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2476 0x41026B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2477 0x41026B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2478 0x41026B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2479 0x41026BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2480 0x41026C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2481 0x41026C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2482 0x41026C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2483 0x41026CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2484 0x41026D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2485 0x41026D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2486 0x41026D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2487 0x41026DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2488 0x41026E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2489 0x41026E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2490 0x41026E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2491 0x41026EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2492 0x41026F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2493 0x41026F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2494 0x41026F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2495 0x41026FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2496 0x4102700
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2497 0x4102704
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2498 0x4102708
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2499 0x410270C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2500 0x4102710
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2501 0x4102714
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2502 0x4102718
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2503 0x410271C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2504 0x4102720
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2505 0x4102724
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2506 0x4102728
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2507 0x410272C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2508 0x4102730
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2509 0x4102734
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2510 0x4102738
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2511 0x410273C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2512 0x4102740
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2513 0x4102744
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2514 0x4102748
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2515 0x410274C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2516 0x4102750
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2517 0x4102754
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2518 0x4102758
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2519 0x410275C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2520 0x4102760
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2521 0x4102764
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2522 0x4102768
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2523 0x410276C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2524 0x4102770
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2525 0x4102774
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2526 0x4102778
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2527 0x410277C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2528 0x4102780
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2529 0x4102784
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2530 0x4102788
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2531 0x410278C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2532 0x4102790
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2533 0x4102794
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2534 0x4102798
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2535 0x410279C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2536 0x41027A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2537 0x41027A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2538 0x41027A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2539 0x41027AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2540 0x41027B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2541 0x41027B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2542 0x41027B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2543 0x41027BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2544 0x41027C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2545 0x41027C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2546 0x41027C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2547 0x41027CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2548 0x41027D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2549 0x41027D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2550 0x41027D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2551 0x41027DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2552 0x41027E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2553 0x41027E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2554 0x41027E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2555 0x41027EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2556 0x41027F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2557 0x41027F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2558 0x41027F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2559 0x41027FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2560 0x4102800
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2561 0x4102804
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2562 0x4102808
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2563 0x410280C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2564 0x4102810
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2565 0x4102814
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2566 0x4102818
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2567 0x410281C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2568 0x4102820
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2569 0x4102824
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2570 0x4102828
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2571 0x410282C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2572 0x4102830
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2573 0x4102834
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2574 0x4102838
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2575 0x410283C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2576 0x4102840
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2577 0x4102844
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2578 0x4102848
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2579 0x410284C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2580 0x4102850
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2581 0x4102854
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2582 0x4102858
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2583 0x410285C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2584 0x4102860
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2585 0x4102864
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2586 0x4102868
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2587 0x410286C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2588 0x4102870
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2589 0x4102874
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2590 0x4102878
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2591 0x410287C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2592 0x4102880
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2593 0x4102884
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2594 0x4102888
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2595 0x410288C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2596 0x4102890
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2597 0x4102894
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2598 0x4102898
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2599 0x410289C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2600 0x41028A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2601 0x41028A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2602 0x41028A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2603 0x41028AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2604 0x41028B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2605 0x41028B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2606 0x41028B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2607 0x41028BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2608 0x41028C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2609 0x41028C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2610 0x41028C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2611 0x41028CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2612 0x41028D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2613 0x41028D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2614 0x41028D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2615 0x41028DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2616 0x41028E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2617 0x41028E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2618 0x41028E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2619 0x41028EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2620 0x41028F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2621 0x41028F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2622 0x41028F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2623 0x41028FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2624 0x4102900
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2625 0x4102904
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2626 0x4102908
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2627 0x410290C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2628 0x4102910
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2629 0x4102914
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2630 0x4102918
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2631 0x410291C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2632 0x4102920
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2633 0x4102924
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2634 0x4102928
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2635 0x410292C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2636 0x4102930
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2637 0x4102934
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2638 0x4102938
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2639 0x410293C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2640 0x4102940
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2641 0x4102944
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2642 0x4102948
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2643 0x410294C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2644 0x4102950
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2645 0x4102954
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2646 0x4102958
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2647 0x410295C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2648 0x4102960
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2649 0x4102964
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2650 0x4102968
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2651 0x410296C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2652 0x4102970
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2653 0x4102974
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2654 0x4102978
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2655 0x410297C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2656 0x4102980
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2657 0x4102984
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2658 0x4102988
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2659 0x410298C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2660 0x4102990
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2661 0x4102994
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2662 0x4102998
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2663 0x410299C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2664 0x41029A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2665 0x41029A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2666 0x41029A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2667 0x41029AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2668 0x41029B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2669 0x41029B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2670 0x41029B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2671 0x41029BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2672 0x41029C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2673 0x41029C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2674 0x41029C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2675 0x41029CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2676 0x41029D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2677 0x41029D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2678 0x41029D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2679 0x41029DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2680 0x41029E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2681 0x41029E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2682 0x41029E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2683 0x41029EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2684 0x41029F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2685 0x41029F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2686 0x41029F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2687 0x41029FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2688 0x4102A00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2689 0x4102A04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2690 0x4102A08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2691 0x4102A0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2692 0x4102A10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2693 0x4102A14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2694 0x4102A18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2695 0x4102A1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2696 0x4102A20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2697 0x4102A24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2698 0x4102A28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2699 0x4102A2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2700 0x4102A30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2701 0x4102A34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2702 0x4102A38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2703 0x4102A3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2704 0x4102A40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2705 0x4102A44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2706 0x4102A48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2707 0x4102A4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2708 0x4102A50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2709 0x4102A54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2710 0x4102A58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2711 0x4102A5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2712 0x4102A60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2713 0x4102A64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2714 0x4102A68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2715 0x4102A6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2716 0x4102A70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2717 0x4102A74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2718 0x4102A78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2719 0x4102A7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2720 0x4102A80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2721 0x4102A84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2722 0x4102A88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2723 0x4102A8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2724 0x4102A90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2725 0x4102A94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2726 0x4102A98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2727 0x4102A9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2728 0x4102AA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2729 0x4102AA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2730 0x4102AA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2731 0x4102AAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2732 0x4102AB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2733 0x4102AB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2734 0x4102AB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2735 0x4102ABC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2736 0x4102AC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2737 0x4102AC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2738 0x4102AC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2739 0x4102ACC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2740 0x4102AD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2741 0x4102AD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2742 0x4102AD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2743 0x4102ADC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2744 0x4102AE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2745 0x4102AE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2746 0x4102AE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2747 0x4102AEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2748 0x4102AF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2749 0x4102AF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2750 0x4102AF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2751 0x4102AFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2752 0x4102B00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2753 0x4102B04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2754 0x4102B08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2755 0x4102B0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2756 0x4102B10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2757 0x4102B14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2758 0x4102B18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2759 0x4102B1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2760 0x4102B20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2761 0x4102B24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2762 0x4102B28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2763 0x4102B2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2764 0x4102B30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2765 0x4102B34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2766 0x4102B38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2767 0x4102B3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2768 0x4102B40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2769 0x4102B44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2770 0x4102B48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2771 0x4102B4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2772 0x4102B50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2773 0x4102B54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2774 0x4102B58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2775 0x4102B5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2776 0x4102B60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2777 0x4102B64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2778 0x4102B68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2779 0x4102B6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2780 0x4102B70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2781 0x4102B74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2782 0x4102B78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2783 0x4102B7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2784 0x4102B80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2785 0x4102B84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2786 0x4102B88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2787 0x4102B8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2788 0x4102B90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2789 0x4102B94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2790 0x4102B98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2791 0x4102B9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2792 0x4102BA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2793 0x4102BA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2794 0x4102BA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2795 0x4102BAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2796 0x4102BB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2797 0x4102BB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2798 0x4102BB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2799 0x4102BBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2800 0x4102BC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2801 0x4102BC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2802 0x4102BC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2803 0x4102BCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2804 0x4102BD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2805 0x4102BD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2806 0x4102BD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2807 0x4102BDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2808 0x4102BE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2809 0x4102BE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2810 0x4102BE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2811 0x4102BEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2812 0x4102BF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2813 0x4102BF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2814 0x4102BF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2815 0x4102BFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2816 0x4102C00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2817 0x4102C04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2818 0x4102C08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2819 0x4102C0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2820 0x4102C10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2821 0x4102C14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2822 0x4102C18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2823 0x4102C1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2824 0x4102C20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2825 0x4102C24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2826 0x4102C28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2827 0x4102C2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2828 0x4102C30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2829 0x4102C34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2830 0x4102C38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2831 0x4102C3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2832 0x4102C40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2833 0x4102C44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2834 0x4102C48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2835 0x4102C4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2836 0x4102C50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2837 0x4102C54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2838 0x4102C58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2839 0x4102C5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2840 0x4102C60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2841 0x4102C64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2842 0x4102C68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2843 0x4102C6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2844 0x4102C70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2845 0x4102C74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2846 0x4102C78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2847 0x4102C7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2848 0x4102C80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2849 0x4102C84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2850 0x4102C88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2851 0x4102C8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2852 0x4102C90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2853 0x4102C94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2854 0x4102C98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2855 0x4102C9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2856 0x4102CA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2857 0x4102CA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2858 0x4102CA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2859 0x4102CAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2860 0x4102CB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2861 0x4102CB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2862 0x4102CB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2863 0x4102CBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2864 0x4102CC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2865 0x4102CC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2866 0x4102CC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2867 0x4102CCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2868 0x4102CD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2869 0x4102CD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2870 0x4102CD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2871 0x4102CDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2872 0x4102CE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2873 0x4102CE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2874 0x4102CE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2875 0x4102CEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2876 0x4102CF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2877 0x4102CF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2878 0x4102CF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2879 0x4102CFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2880 0x4102D00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2881 0x4102D04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2882 0x4102D08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2883 0x4102D0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2884 0x4102D10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2885 0x4102D14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2886 0x4102D18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2887 0x4102D1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2888 0x4102D20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2889 0x4102D24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2890 0x4102D28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2891 0x4102D2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2892 0x4102D30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2893 0x4102D34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2894 0x4102D38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2895 0x4102D3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2896 0x4102D40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2897 0x4102D44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2898 0x4102D48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2899 0x4102D4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2900 0x4102D50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2901 0x4102D54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2902 0x4102D58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2903 0x4102D5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2904 0x4102D60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2905 0x4102D64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2906 0x4102D68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2907 0x4102D6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2908 0x4102D70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2909 0x4102D74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2910 0x4102D78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2911 0x4102D7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2912 0x4102D80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2913 0x4102D84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2914 0x4102D88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2915 0x4102D8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2916 0x4102D90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2917 0x4102D94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2918 0x4102D98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2919 0x4102D9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2920 0x4102DA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2921 0x4102DA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2922 0x4102DA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2923 0x4102DAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2924 0x4102DB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2925 0x4102DB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2926 0x4102DB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2927 0x4102DBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2928 0x4102DC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2929 0x4102DC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2930 0x4102DC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2931 0x4102DCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2932 0x4102DD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2933 0x4102DD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2934 0x4102DD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2935 0x4102DDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2936 0x4102DE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2937 0x4102DE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2938 0x4102DE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2939 0x4102DEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2940 0x4102DF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2941 0x4102DF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2942 0x4102DF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2943 0x4102DFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2944 0x4102E00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2945 0x4102E04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2946 0x4102E08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2947 0x4102E0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2948 0x4102E10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2949 0x4102E14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2950 0x4102E18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2951 0x4102E1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2952 0x4102E20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2953 0x4102E24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2954 0x4102E28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2955 0x4102E2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2956 0x4102E30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2957 0x4102E34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2958 0x4102E38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2959 0x4102E3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2960 0x4102E40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2961 0x4102E44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2962 0x4102E48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2963 0x4102E4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2964 0x4102E50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2965 0x4102E54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2966 0x4102E58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2967 0x4102E5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2968 0x4102E60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2969 0x4102E64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2970 0x4102E68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2971 0x4102E6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2972 0x4102E70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2973 0x4102E74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2974 0x4102E78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2975 0x4102E7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2976 0x4102E80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2977 0x4102E84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2978 0x4102E88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2979 0x4102E8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2980 0x4102E90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2981 0x4102E94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2982 0x4102E98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2983 0x4102E9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2984 0x4102EA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2985 0x4102EA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2986 0x4102EA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2987 0x4102EAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2988 0x4102EB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2989 0x4102EB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2990 0x4102EB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2991 0x4102EBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2992 0x4102EC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2993 0x4102EC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2994 0x4102EC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2995 0x4102ECC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2996 0x4102ED0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2997 0x4102ED4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2998 0x4102ED8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_2999 0x4102EDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3000 0x4102EE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3001 0x4102EE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3002 0x4102EE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3003 0x4102EEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3004 0x4102EF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3005 0x4102EF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3006 0x4102EF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3007 0x4102EFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3008 0x4102F00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3009 0x4102F04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3010 0x4102F08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3011 0x4102F0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3012 0x4102F10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3013 0x4102F14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3014 0x4102F18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3015 0x4102F1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3016 0x4102F20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3017 0x4102F24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3018 0x4102F28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3019 0x4102F2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3020 0x4102F30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3021 0x4102F34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3022 0x4102F38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3023 0x4102F3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3024 0x4102F40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3025 0x4102F44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3026 0x4102F48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3027 0x4102F4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3028 0x4102F50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3029 0x4102F54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3030 0x4102F58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3031 0x4102F5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3032 0x4102F60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3033 0x4102F64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3034 0x4102F68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3035 0x4102F6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3036 0x4102F70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3037 0x4102F74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3038 0x4102F78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3039 0x4102F7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3040 0x4102F80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3041 0x4102F84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3042 0x4102F88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3043 0x4102F8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3044 0x4102F90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3045 0x4102F94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3046 0x4102F98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3047 0x4102F9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3048 0x4102FA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3049 0x4102FA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3050 0x4102FA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3051 0x4102FAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3052 0x4102FB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3053 0x4102FB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3054 0x4102FB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3055 0x4102FBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3056 0x4102FC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3057 0x4102FC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3058 0x4102FC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3059 0x4102FCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3060 0x4102FD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3061 0x4102FD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3062 0x4102FD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3063 0x4102FDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3064 0x4102FE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3065 0x4102FE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3066 0x4102FE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3067 0x4102FEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3068 0x4102FF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3069 0x4102FF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3070 0x4102FF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3071 0x4102FFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3072 0x4103000
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3073 0x4103004
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3074 0x4103008
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3075 0x410300C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3076 0x4103010
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3077 0x4103014
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3078 0x4103018
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3079 0x410301C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3080 0x4103020
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3081 0x4103024
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3082 0x4103028
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3083 0x410302C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3084 0x4103030
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3085 0x4103034
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3086 0x4103038
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3087 0x410303C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3088 0x4103040
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3089 0x4103044
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3090 0x4103048
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3091 0x410304C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3092 0x4103050
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3093 0x4103054
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3094 0x4103058
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3095 0x410305C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3096 0x4103060
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3097 0x4103064
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3098 0x4103068
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3099 0x410306C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3100 0x4103070
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3101 0x4103074
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3102 0x4103078
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3103 0x410307C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3104 0x4103080
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3105 0x4103084
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3106 0x4103088
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3107 0x410308C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3108 0x4103090
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3109 0x4103094
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3110 0x4103098
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3111 0x410309C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3112 0x41030A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3113 0x41030A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3114 0x41030A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3115 0x41030AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3116 0x41030B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3117 0x41030B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3118 0x41030B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3119 0x41030BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3120 0x41030C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3121 0x41030C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3122 0x41030C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3123 0x41030CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3124 0x41030D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3125 0x41030D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3126 0x41030D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3127 0x41030DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3128 0x41030E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3129 0x41030E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3130 0x41030E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3131 0x41030EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3132 0x41030F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3133 0x41030F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3134 0x41030F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3135 0x41030FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3136 0x4103100
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3137 0x4103104
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3138 0x4103108
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3139 0x410310C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3140 0x4103110
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3141 0x4103114
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3142 0x4103118
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3143 0x410311C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3144 0x4103120
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3145 0x4103124
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3146 0x4103128
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3147 0x410312C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3148 0x4103130
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3149 0x4103134
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3150 0x4103138
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3151 0x410313C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3152 0x4103140
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3153 0x4103144
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3154 0x4103148
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3155 0x410314C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3156 0x4103150
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3157 0x4103154
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3158 0x4103158
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3159 0x410315C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3160 0x4103160
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3161 0x4103164
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3162 0x4103168
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3163 0x410316C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3164 0x4103170
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3165 0x4103174
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3166 0x4103178
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3167 0x410317C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3168 0x4103180
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3169 0x4103184
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3170 0x4103188
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3171 0x410318C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3172 0x4103190
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3173 0x4103194
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3174 0x4103198
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3175 0x410319C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3176 0x41031A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3177 0x41031A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3178 0x41031A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3179 0x41031AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3180 0x41031B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3181 0x41031B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3182 0x41031B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3183 0x41031BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3184 0x41031C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3185 0x41031C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3186 0x41031C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3187 0x41031CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3188 0x41031D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3189 0x41031D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3190 0x41031D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3191 0x41031DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3192 0x41031E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3193 0x41031E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3194 0x41031E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3195 0x41031EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3196 0x41031F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3197 0x41031F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3198 0x41031F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3199 0x41031FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3200 0x4103200
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3201 0x4103204
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3202 0x4103208
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3203 0x410320C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3204 0x4103210
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3205 0x4103214
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3206 0x4103218
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3207 0x410321C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3208 0x4103220
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3209 0x4103224
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3210 0x4103228
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3211 0x410322C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3212 0x4103230
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3213 0x4103234
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3214 0x4103238
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3215 0x410323C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3216 0x4103240
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3217 0x4103244
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3218 0x4103248
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3219 0x410324C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3220 0x4103250
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3221 0x4103254
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3222 0x4103258
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3223 0x410325C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3224 0x4103260
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3225 0x4103264
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3226 0x4103268
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3227 0x410326C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3228 0x4103270
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3229 0x4103274
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3230 0x4103278
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3231 0x410327C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3232 0x4103280
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3233 0x4103284
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3234 0x4103288
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3235 0x410328C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3236 0x4103290
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3237 0x4103294
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3238 0x4103298
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3239 0x410329C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3240 0x41032A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3241 0x41032A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3242 0x41032A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3243 0x41032AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3244 0x41032B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3245 0x41032B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3246 0x41032B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3247 0x41032BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3248 0x41032C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3249 0x41032C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3250 0x41032C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3251 0x41032CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3252 0x41032D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3253 0x41032D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3254 0x41032D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3255 0x41032DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3256 0x41032E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3257 0x41032E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3258 0x41032E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3259 0x41032EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3260 0x41032F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3261 0x41032F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3262 0x41032F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3263 0x41032FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3264 0x4103300
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3265 0x4103304
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3266 0x4103308
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3267 0x410330C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3268 0x4103310
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3269 0x4103314
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3270 0x4103318
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3271 0x410331C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3272 0x4103320
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3273 0x4103324
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3274 0x4103328
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3275 0x410332C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3276 0x4103330
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3277 0x4103334
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3278 0x4103338
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3279 0x410333C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3280 0x4103340
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3281 0x4103344
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3282 0x4103348
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3283 0x410334C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3284 0x4103350
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3285 0x4103354
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3286 0x4103358
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3287 0x410335C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3288 0x4103360
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3289 0x4103364
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3290 0x4103368
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3291 0x410336C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3292 0x4103370
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3293 0x4103374
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3294 0x4103378
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3295 0x410337C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3296 0x4103380
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3297 0x4103384
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3298 0x4103388
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3299 0x410338C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3300 0x4103390
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3301 0x4103394
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3302 0x4103398
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3303 0x410339C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3304 0x41033A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3305 0x41033A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3306 0x41033A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3307 0x41033AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3308 0x41033B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3309 0x41033B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3310 0x41033B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3311 0x41033BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3312 0x41033C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3313 0x41033C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3314 0x41033C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3315 0x41033CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3316 0x41033D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3317 0x41033D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3318 0x41033D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3319 0x41033DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3320 0x41033E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3321 0x41033E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3322 0x41033E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3323 0x41033EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3324 0x41033F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3325 0x41033F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3326 0x41033F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3327 0x41033FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3328 0x4103400
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3329 0x4103404
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3330 0x4103408
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3331 0x410340C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3332 0x4103410
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3333 0x4103414
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3334 0x4103418
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3335 0x410341C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3336 0x4103420
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3337 0x4103424
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3338 0x4103428
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3339 0x410342C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3340 0x4103430
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3341 0x4103434
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3342 0x4103438
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3343 0x410343C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3344 0x4103440
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3345 0x4103444
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3346 0x4103448
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3347 0x410344C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3348 0x4103450
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3349 0x4103454
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3350 0x4103458
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3351 0x410345C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3352 0x4103460
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3353 0x4103464
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3354 0x4103468
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3355 0x410346C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3356 0x4103470
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3357 0x4103474
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3358 0x4103478
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3359 0x410347C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3360 0x4103480
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3361 0x4103484
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3362 0x4103488
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3363 0x410348C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3364 0x4103490
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3365 0x4103494
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3366 0x4103498
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3367 0x410349C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3368 0x41034A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3369 0x41034A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3370 0x41034A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3371 0x41034AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3372 0x41034B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3373 0x41034B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3374 0x41034B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3375 0x41034BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3376 0x41034C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3377 0x41034C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3378 0x41034C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3379 0x41034CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3380 0x41034D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3381 0x41034D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3382 0x41034D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3383 0x41034DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3384 0x41034E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3385 0x41034E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3386 0x41034E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3387 0x41034EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3388 0x41034F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3389 0x41034F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3390 0x41034F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3391 0x41034FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3392 0x4103500
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3393 0x4103504
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3394 0x4103508
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3395 0x410350C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3396 0x4103510
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3397 0x4103514
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3398 0x4103518
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3399 0x410351C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3400 0x4103520
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3401 0x4103524
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3402 0x4103528
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3403 0x410352C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3404 0x4103530
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3405 0x4103534
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3406 0x4103538
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3407 0x410353C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3408 0x4103540
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3409 0x4103544
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3410 0x4103548
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3411 0x410354C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3412 0x4103550
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3413 0x4103554
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3414 0x4103558
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3415 0x410355C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3416 0x4103560
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3417 0x4103564
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3418 0x4103568
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3419 0x410356C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3420 0x4103570
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3421 0x4103574
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3422 0x4103578
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3423 0x410357C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3424 0x4103580
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3425 0x4103584
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3426 0x4103588
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3427 0x410358C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3428 0x4103590
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3429 0x4103594
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3430 0x4103598
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3431 0x410359C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3432 0x41035A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3433 0x41035A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3434 0x41035A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3435 0x41035AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3436 0x41035B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3437 0x41035B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3438 0x41035B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3439 0x41035BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3440 0x41035C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3441 0x41035C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3442 0x41035C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3443 0x41035CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3444 0x41035D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3445 0x41035D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3446 0x41035D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3447 0x41035DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3448 0x41035E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3449 0x41035E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3450 0x41035E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3451 0x41035EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3452 0x41035F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3453 0x41035F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3454 0x41035F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3455 0x41035FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3456 0x4103600
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3457 0x4103604
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3458 0x4103608
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3459 0x410360C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3460 0x4103610
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3461 0x4103614
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3462 0x4103618
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3463 0x410361C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3464 0x4103620
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3465 0x4103624
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3466 0x4103628
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3467 0x410362C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3468 0x4103630
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3469 0x4103634
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3470 0x4103638
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3471 0x410363C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3472 0x4103640
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3473 0x4103644
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3474 0x4103648
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3475 0x410364C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3476 0x4103650
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3477 0x4103654
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3478 0x4103658
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3479 0x410365C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3480 0x4103660
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3481 0x4103664
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3482 0x4103668
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3483 0x410366C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3484 0x4103670
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3485 0x4103674
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3486 0x4103678
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3487 0x410367C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3488 0x4103680
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3489 0x4103684
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3490 0x4103688
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3491 0x410368C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3492 0x4103690
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3493 0x4103694
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3494 0x4103698
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3495 0x410369C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3496 0x41036A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3497 0x41036A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3498 0x41036A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3499 0x41036AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3500 0x41036B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3501 0x41036B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3502 0x41036B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3503 0x41036BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3504 0x41036C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3505 0x41036C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3506 0x41036C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3507 0x41036CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3508 0x41036D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3509 0x41036D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3510 0x41036D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3511 0x41036DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3512 0x41036E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3513 0x41036E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3514 0x41036E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3515 0x41036EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3516 0x41036F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3517 0x41036F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3518 0x41036F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3519 0x41036FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3520 0x4103700
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3521 0x4103704
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3522 0x4103708
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3523 0x410370C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3524 0x4103710
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3525 0x4103714
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3526 0x4103718
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3527 0x410371C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3528 0x4103720
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3529 0x4103724
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3530 0x4103728
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3531 0x410372C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3532 0x4103730
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3533 0x4103734
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3534 0x4103738
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3535 0x410373C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3536 0x4103740
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3537 0x4103744
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3538 0x4103748
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3539 0x410374C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3540 0x4103750
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3541 0x4103754
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3542 0x4103758
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3543 0x410375C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3544 0x4103760
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3545 0x4103764
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3546 0x4103768
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3547 0x410376C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3548 0x4103770
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3549 0x4103774
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3550 0x4103778
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3551 0x410377C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3552 0x4103780
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3553 0x4103784
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3554 0x4103788
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3555 0x410378C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3556 0x4103790
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3557 0x4103794
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3558 0x4103798
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3559 0x410379C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3560 0x41037A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3561 0x41037A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3562 0x41037A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3563 0x41037AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3564 0x41037B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3565 0x41037B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3566 0x41037B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3567 0x41037BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3568 0x41037C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3569 0x41037C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3570 0x41037C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3571 0x41037CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3572 0x41037D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3573 0x41037D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3574 0x41037D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3575 0x41037DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3576 0x41037E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3577 0x41037E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3578 0x41037E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3579 0x41037EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3580 0x41037F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3581 0x41037F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3582 0x41037F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3583 0x41037FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3584 0x4103800
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3585 0x4103804
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3586 0x4103808
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3587 0x410380C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3588 0x4103810
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3589 0x4103814
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3590 0x4103818
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3591 0x410381C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3592 0x4103820
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3593 0x4103824
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3594 0x4103828
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3595 0x410382C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3596 0x4103830
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3597 0x4103834
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3598 0x4103838
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3599 0x410383C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3600 0x4103840
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3601 0x4103844
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3602 0x4103848
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3603 0x410384C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3604 0x4103850
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3605 0x4103854
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3606 0x4103858
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3607 0x410385C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3608 0x4103860
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3609 0x4103864
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3610 0x4103868
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3611 0x410386C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3612 0x4103870
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3613 0x4103874
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3614 0x4103878
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3615 0x410387C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3616 0x4103880
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3617 0x4103884
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3618 0x4103888
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3619 0x410388C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3620 0x4103890
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3621 0x4103894
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3622 0x4103898
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3623 0x410389C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3624 0x41038A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3625 0x41038A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3626 0x41038A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3627 0x41038AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3628 0x41038B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3629 0x41038B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3630 0x41038B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3631 0x41038BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3632 0x41038C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3633 0x41038C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3634 0x41038C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3635 0x41038CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3636 0x41038D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3637 0x41038D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3638 0x41038D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3639 0x41038DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3640 0x41038E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3641 0x41038E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3642 0x41038E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3643 0x41038EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3644 0x41038F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3645 0x41038F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3646 0x41038F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3647 0x41038FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3648 0x4103900
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3649 0x4103904
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3650 0x4103908
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3651 0x410390C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3652 0x4103910
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3653 0x4103914
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3654 0x4103918
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3655 0x410391C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3656 0x4103920
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3657 0x4103924
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3658 0x4103928
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3659 0x410392C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3660 0x4103930
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3661 0x4103934
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3662 0x4103938
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3663 0x410393C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3664 0x4103940
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3665 0x4103944
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3666 0x4103948
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3667 0x410394C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3668 0x4103950
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3669 0x4103954
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3670 0x4103958
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3671 0x410395C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3672 0x4103960
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3673 0x4103964
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3674 0x4103968
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3675 0x410396C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3676 0x4103970
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3677 0x4103974
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3678 0x4103978
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3679 0x410397C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3680 0x4103980
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3681 0x4103984
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3682 0x4103988
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3683 0x410398C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3684 0x4103990
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3685 0x4103994
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3686 0x4103998
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3687 0x410399C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3688 0x41039A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3689 0x41039A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3690 0x41039A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3691 0x41039AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3692 0x41039B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3693 0x41039B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3694 0x41039B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3695 0x41039BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3696 0x41039C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3697 0x41039C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3698 0x41039C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3699 0x41039CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3700 0x41039D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3701 0x41039D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3702 0x41039D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3703 0x41039DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3704 0x41039E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3705 0x41039E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3706 0x41039E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3707 0x41039EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3708 0x41039F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3709 0x41039F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3710 0x41039F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3711 0x41039FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3712 0x4103A00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3713 0x4103A04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3714 0x4103A08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3715 0x4103A0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3716 0x4103A10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3717 0x4103A14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3718 0x4103A18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3719 0x4103A1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3720 0x4103A20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3721 0x4103A24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3722 0x4103A28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3723 0x4103A2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3724 0x4103A30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3725 0x4103A34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3726 0x4103A38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3727 0x4103A3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3728 0x4103A40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3729 0x4103A44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3730 0x4103A48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3731 0x4103A4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3732 0x4103A50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3733 0x4103A54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3734 0x4103A58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3735 0x4103A5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3736 0x4103A60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3737 0x4103A64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3738 0x4103A68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3739 0x4103A6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3740 0x4103A70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3741 0x4103A74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3742 0x4103A78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3743 0x4103A7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3744 0x4103A80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3745 0x4103A84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3746 0x4103A88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3747 0x4103A8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3748 0x4103A90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3749 0x4103A94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3750 0x4103A98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3751 0x4103A9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3752 0x4103AA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3753 0x4103AA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3754 0x4103AA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3755 0x4103AAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3756 0x4103AB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3757 0x4103AB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3758 0x4103AB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3759 0x4103ABC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3760 0x4103AC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3761 0x4103AC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3762 0x4103AC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3763 0x4103ACC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3764 0x4103AD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3765 0x4103AD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3766 0x4103AD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3767 0x4103ADC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3768 0x4103AE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3769 0x4103AE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3770 0x4103AE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3771 0x4103AEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3772 0x4103AF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3773 0x4103AF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3774 0x4103AF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3775 0x4103AFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3776 0x4103B00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3777 0x4103B04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3778 0x4103B08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3779 0x4103B0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3780 0x4103B10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3781 0x4103B14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3782 0x4103B18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3783 0x4103B1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3784 0x4103B20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3785 0x4103B24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3786 0x4103B28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3787 0x4103B2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3788 0x4103B30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3789 0x4103B34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3790 0x4103B38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3791 0x4103B3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3792 0x4103B40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3793 0x4103B44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3794 0x4103B48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3795 0x4103B4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3796 0x4103B50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3797 0x4103B54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3798 0x4103B58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3799 0x4103B5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3800 0x4103B60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3801 0x4103B64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3802 0x4103B68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3803 0x4103B6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3804 0x4103B70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3805 0x4103B74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3806 0x4103B78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3807 0x4103B7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3808 0x4103B80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3809 0x4103B84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3810 0x4103B88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3811 0x4103B8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3812 0x4103B90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3813 0x4103B94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3814 0x4103B98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3815 0x4103B9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3816 0x4103BA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3817 0x4103BA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3818 0x4103BA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3819 0x4103BAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3820 0x4103BB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3821 0x4103BB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3822 0x4103BB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3823 0x4103BBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3824 0x4103BC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3825 0x4103BC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3826 0x4103BC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3827 0x4103BCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3828 0x4103BD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3829 0x4103BD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3830 0x4103BD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3831 0x4103BDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3832 0x4103BE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3833 0x4103BE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3834 0x4103BE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3835 0x4103BEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3836 0x4103BF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3837 0x4103BF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3838 0x4103BF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3839 0x4103BFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3840 0x4103C00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3841 0x4103C04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3842 0x4103C08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3843 0x4103C0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3844 0x4103C10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3845 0x4103C14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3846 0x4103C18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3847 0x4103C1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3848 0x4103C20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3849 0x4103C24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3850 0x4103C28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3851 0x4103C2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3852 0x4103C30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3853 0x4103C34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3854 0x4103C38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3855 0x4103C3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3856 0x4103C40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3857 0x4103C44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3858 0x4103C48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3859 0x4103C4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3860 0x4103C50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3861 0x4103C54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3862 0x4103C58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3863 0x4103C5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3864 0x4103C60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3865 0x4103C64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3866 0x4103C68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3867 0x4103C6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3868 0x4103C70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3869 0x4103C74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3870 0x4103C78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3871 0x4103C7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3872 0x4103C80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3873 0x4103C84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3874 0x4103C88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3875 0x4103C8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3876 0x4103C90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3877 0x4103C94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3878 0x4103C98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3879 0x4103C9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3880 0x4103CA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3881 0x4103CA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3882 0x4103CA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3883 0x4103CAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3884 0x4103CB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3885 0x4103CB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3886 0x4103CB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3887 0x4103CBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3888 0x4103CC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3889 0x4103CC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3890 0x4103CC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3891 0x4103CCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3892 0x4103CD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3893 0x4103CD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3894 0x4103CD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3895 0x4103CDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3896 0x4103CE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3897 0x4103CE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3898 0x4103CE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3899 0x4103CEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3900 0x4103CF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3901 0x4103CF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3902 0x4103CF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3903 0x4103CFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3904 0x4103D00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3905 0x4103D04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3906 0x4103D08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3907 0x4103D0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3908 0x4103D10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3909 0x4103D14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3910 0x4103D18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3911 0x4103D1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3912 0x4103D20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3913 0x4103D24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3914 0x4103D28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3915 0x4103D2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3916 0x4103D30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3917 0x4103D34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3918 0x4103D38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3919 0x4103D3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3920 0x4103D40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3921 0x4103D44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3922 0x4103D48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3923 0x4103D4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3924 0x4103D50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3925 0x4103D54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3926 0x4103D58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3927 0x4103D5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3928 0x4103D60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3929 0x4103D64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3930 0x4103D68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3931 0x4103D6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3932 0x4103D70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3933 0x4103D74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3934 0x4103D78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3935 0x4103D7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3936 0x4103D80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3937 0x4103D84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3938 0x4103D88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3939 0x4103D8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3940 0x4103D90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3941 0x4103D94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3942 0x4103D98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3943 0x4103D9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3944 0x4103DA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3945 0x4103DA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3946 0x4103DA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3947 0x4103DAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3948 0x4103DB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3949 0x4103DB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3950 0x4103DB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3951 0x4103DBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3952 0x4103DC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3953 0x4103DC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3954 0x4103DC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3955 0x4103DCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3956 0x4103DD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3957 0x4103DD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3958 0x4103DD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3959 0x4103DDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3960 0x4103DE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3961 0x4103DE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3962 0x4103DE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3963 0x4103DEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3964 0x4103DF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3965 0x4103DF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3966 0x4103DF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3967 0x4103DFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3968 0x4103E00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3969 0x4103E04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3970 0x4103E08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3971 0x4103E0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3972 0x4103E10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3973 0x4103E14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3974 0x4103E18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3975 0x4103E1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3976 0x4103E20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3977 0x4103E24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3978 0x4103E28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3979 0x4103E2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3980 0x4103E30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3981 0x4103E34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3982 0x4103E38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3983 0x4103E3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3984 0x4103E40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3985 0x4103E44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3986 0x4103E48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3987 0x4103E4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3988 0x4103E50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3989 0x4103E54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3990 0x4103E58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3991 0x4103E5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3992 0x4103E60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3993 0x4103E64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3994 0x4103E68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3995 0x4103E6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3996 0x4103E70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3997 0x4103E74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3998 0x4103E78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_3999 0x4103E7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4000 0x4103E80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4001 0x4103E84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4002 0x4103E88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4003 0x4103E8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4004 0x4103E90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4005 0x4103E94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4006 0x4103E98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4007 0x4103E9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4008 0x4103EA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4009 0x4103EA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4010 0x4103EA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4011 0x4103EAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4012 0x4103EB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4013 0x4103EB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4014 0x4103EB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4015 0x4103EBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4016 0x4103EC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4017 0x4103EC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4018 0x4103EC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4019 0x4103ECC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4020 0x4103ED0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4021 0x4103ED4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4022 0x4103ED8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4023 0x4103EDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4024 0x4103EE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4025 0x4103EE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4026 0x4103EE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4027 0x4103EEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4028 0x4103EF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4029 0x4103EF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4030 0x4103EF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4031 0x4103EFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4032 0x4103F00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4033 0x4103F04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4034 0x4103F08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4035 0x4103F0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4036 0x4103F10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4037 0x4103F14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4038 0x4103F18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4039 0x4103F1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4040 0x4103F20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4041 0x4103F24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4042 0x4103F28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4043 0x4103F2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4044 0x4103F30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4045 0x4103F34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4046 0x4103F38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4047 0x4103F3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4048 0x4103F40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4049 0x4103F44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4050 0x4103F48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4051 0x4103F4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4052 0x4103F50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4053 0x4103F54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4054 0x4103F58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4055 0x4103F5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4056 0x4103F60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4057 0x4103F64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4058 0x4103F68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4059 0x4103F6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4060 0x4103F70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4061 0x4103F74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4062 0x4103F78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4063 0x4103F7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4064 0x4103F80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4065 0x4103F84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4066 0x4103F88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4067 0x4103F8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4068 0x4103F90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4069 0x4103F94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4070 0x4103F98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4071 0x4103F9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4072 0x4103FA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4073 0x4103FA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4074 0x4103FA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4075 0x4103FAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4076 0x4103FB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4077 0x4103FB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4078 0x4103FB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4079 0x4103FBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4080 0x4103FC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4081 0x4103FC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4082 0x4103FC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4083 0x4103FCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4084 0x4103FD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4085 0x4103FD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4086 0x4103FD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4087 0x4103FDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4088 0x4103FE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4089 0x4103FE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4090 0x4103FE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4091 0x4103FEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4092 0x4103FF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4093 0x4103FF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4094 0x4103FF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4095 0x4103FFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4096 0x4104000
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4097 0x4104004
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4098 0x4104008
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4099 0x410400C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4100 0x4104010
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4101 0x4104014
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4102 0x4104018
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4103 0x410401C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4104 0x4104020
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4105 0x4104024
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4106 0x4104028
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4107 0x410402C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4108 0x4104030
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4109 0x4104034
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4110 0x4104038
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4111 0x410403C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4112 0x4104040
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4113 0x4104044
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4114 0x4104048
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4115 0x410404C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4116 0x4104050
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4117 0x4104054
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4118 0x4104058
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4119 0x410405C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4120 0x4104060
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4121 0x4104064
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4122 0x4104068
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4123 0x410406C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4124 0x4104070
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4125 0x4104074
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4126 0x4104078
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4127 0x410407C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4128 0x4104080
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4129 0x4104084
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4130 0x4104088
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4131 0x410408C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4132 0x4104090
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4133 0x4104094
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4134 0x4104098
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4135 0x410409C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4136 0x41040A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4137 0x41040A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4138 0x41040A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4139 0x41040AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4140 0x41040B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4141 0x41040B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4142 0x41040B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4143 0x41040BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4144 0x41040C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4145 0x41040C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4146 0x41040C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4147 0x41040CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4148 0x41040D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4149 0x41040D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4150 0x41040D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4151 0x41040DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4152 0x41040E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4153 0x41040E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4154 0x41040E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4155 0x41040EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4156 0x41040F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4157 0x41040F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4158 0x41040F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4159 0x41040FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4160 0x4104100
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4161 0x4104104
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4162 0x4104108
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4163 0x410410C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4164 0x4104110
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4165 0x4104114
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4166 0x4104118
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4167 0x410411C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4168 0x4104120
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4169 0x4104124
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4170 0x4104128
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4171 0x410412C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4172 0x4104130
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4173 0x4104134
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4174 0x4104138
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4175 0x410413C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4176 0x4104140
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4177 0x4104144
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4178 0x4104148
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4179 0x410414C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4180 0x4104150
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4181 0x4104154
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4182 0x4104158
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4183 0x410415C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4184 0x4104160
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4185 0x4104164
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4186 0x4104168
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4187 0x410416C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4188 0x4104170
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4189 0x4104174
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4190 0x4104178
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4191 0x410417C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4192 0x4104180
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4193 0x4104184
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4194 0x4104188
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4195 0x410418C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4196 0x4104190
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4197 0x4104194
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4198 0x4104198
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4199 0x410419C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4200 0x41041A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4201 0x41041A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4202 0x41041A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4203 0x41041AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4204 0x41041B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4205 0x41041B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4206 0x41041B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4207 0x41041BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4208 0x41041C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4209 0x41041C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4210 0x41041C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4211 0x41041CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4212 0x41041D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4213 0x41041D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4214 0x41041D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4215 0x41041DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4216 0x41041E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4217 0x41041E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4218 0x41041E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4219 0x41041EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4220 0x41041F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4221 0x41041F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4222 0x41041F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4223 0x41041FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4224 0x4104200
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4225 0x4104204
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4226 0x4104208
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4227 0x410420C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4228 0x4104210
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4229 0x4104214
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4230 0x4104218
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4231 0x410421C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4232 0x4104220
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4233 0x4104224
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4234 0x4104228
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4235 0x410422C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4236 0x4104230
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4237 0x4104234
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4238 0x4104238
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4239 0x410423C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4240 0x4104240
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4241 0x4104244
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4242 0x4104248
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4243 0x410424C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4244 0x4104250
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4245 0x4104254
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4246 0x4104258
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4247 0x410425C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4248 0x4104260
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4249 0x4104264
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4250 0x4104268
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4251 0x410426C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4252 0x4104270
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4253 0x4104274
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4254 0x4104278
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4255 0x410427C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4256 0x4104280
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4257 0x4104284
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4258 0x4104288
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4259 0x410428C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4260 0x4104290
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4261 0x4104294
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4262 0x4104298
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4263 0x410429C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4264 0x41042A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4265 0x41042A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4266 0x41042A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4267 0x41042AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4268 0x41042B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4269 0x41042B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4270 0x41042B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4271 0x41042BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4272 0x41042C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4273 0x41042C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4274 0x41042C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4275 0x41042CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4276 0x41042D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4277 0x41042D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4278 0x41042D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4279 0x41042DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4280 0x41042E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4281 0x41042E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4282 0x41042E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4283 0x41042EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4284 0x41042F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4285 0x41042F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4286 0x41042F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4287 0x41042FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4288 0x4104300
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4289 0x4104304
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4290 0x4104308
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4291 0x410430C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4292 0x4104310
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4293 0x4104314
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4294 0x4104318
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4295 0x410431C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4296 0x4104320
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4297 0x4104324
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4298 0x4104328
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4299 0x410432C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4300 0x4104330
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4301 0x4104334
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4302 0x4104338
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4303 0x410433C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4304 0x4104340
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4305 0x4104344
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4306 0x4104348
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4307 0x410434C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4308 0x4104350
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4309 0x4104354
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4310 0x4104358
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4311 0x410435C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4312 0x4104360
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4313 0x4104364
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4314 0x4104368
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4315 0x410436C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4316 0x4104370
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4317 0x4104374
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4318 0x4104378
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4319 0x410437C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4320 0x4104380
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4321 0x4104384
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4322 0x4104388
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4323 0x410438C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4324 0x4104390
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4325 0x4104394
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4326 0x4104398
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4327 0x410439C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4328 0x41043A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4329 0x41043A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4330 0x41043A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4331 0x41043AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4332 0x41043B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4333 0x41043B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4334 0x41043B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4335 0x41043BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4336 0x41043C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4337 0x41043C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4338 0x41043C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4339 0x41043CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4340 0x41043D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4341 0x41043D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4342 0x41043D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4343 0x41043DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4344 0x41043E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4345 0x41043E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4346 0x41043E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4347 0x41043EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4348 0x41043F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4349 0x41043F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4350 0x41043F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4351 0x41043FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4352 0x4104400
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4353 0x4104404
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4354 0x4104408
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4355 0x410440C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4356 0x4104410
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4357 0x4104414
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4358 0x4104418
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4359 0x410441C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4360 0x4104420
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4361 0x4104424
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4362 0x4104428
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4363 0x410442C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4364 0x4104430
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4365 0x4104434
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4366 0x4104438
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4367 0x410443C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4368 0x4104440
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4369 0x4104444
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4370 0x4104448
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4371 0x410444C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4372 0x4104450
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4373 0x4104454
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4374 0x4104458
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4375 0x410445C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4376 0x4104460
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4377 0x4104464
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4378 0x4104468
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4379 0x410446C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4380 0x4104470
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4381 0x4104474
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4382 0x4104478
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4383 0x410447C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4384 0x4104480
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4385 0x4104484
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4386 0x4104488
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4387 0x410448C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4388 0x4104490
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4389 0x4104494
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4390 0x4104498
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4391 0x410449C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4392 0x41044A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4393 0x41044A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4394 0x41044A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4395 0x41044AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4396 0x41044B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4397 0x41044B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4398 0x41044B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4399 0x41044BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4400 0x41044C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4401 0x41044C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4402 0x41044C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4403 0x41044CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4404 0x41044D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4405 0x41044D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4406 0x41044D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4407 0x41044DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4408 0x41044E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4409 0x41044E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4410 0x41044E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4411 0x41044EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4412 0x41044F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4413 0x41044F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4414 0x41044F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4415 0x41044FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4416 0x4104500
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4417 0x4104504
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4418 0x4104508
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4419 0x410450C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4420 0x4104510
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4421 0x4104514
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4422 0x4104518
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4423 0x410451C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4424 0x4104520
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4425 0x4104524
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4426 0x4104528
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4427 0x410452C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4428 0x4104530
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4429 0x4104534
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4430 0x4104538
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4431 0x410453C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4432 0x4104540
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4433 0x4104544
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4434 0x4104548
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4435 0x410454C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4436 0x4104550
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4437 0x4104554
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4438 0x4104558
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4439 0x410455C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4440 0x4104560
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4441 0x4104564
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4442 0x4104568
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4443 0x410456C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4444 0x4104570
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4445 0x4104574
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4446 0x4104578
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4447 0x410457C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4448 0x4104580
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4449 0x4104584
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4450 0x4104588
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4451 0x410458C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4452 0x4104590
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4453 0x4104594
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4454 0x4104598
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4455 0x410459C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4456 0x41045A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4457 0x41045A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4458 0x41045A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4459 0x41045AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4460 0x41045B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4461 0x41045B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4462 0x41045B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4463 0x41045BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4464 0x41045C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4465 0x41045C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4466 0x41045C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4467 0x41045CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4468 0x41045D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4469 0x41045D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4470 0x41045D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4471 0x41045DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4472 0x41045E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4473 0x41045E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4474 0x41045E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4475 0x41045EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4476 0x41045F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4477 0x41045F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4478 0x41045F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4479 0x41045FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4480 0x4104600
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4481 0x4104604
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4482 0x4104608
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4483 0x410460C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4484 0x4104610
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4485 0x4104614
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4486 0x4104618
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4487 0x410461C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4488 0x4104620
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4489 0x4104624
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4490 0x4104628
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4491 0x410462C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4492 0x4104630
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4493 0x4104634
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4494 0x4104638
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4495 0x410463C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4496 0x4104640
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4497 0x4104644
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4498 0x4104648
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4499 0x410464C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4500 0x4104650
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4501 0x4104654
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4502 0x4104658
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4503 0x410465C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4504 0x4104660
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4505 0x4104664
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4506 0x4104668
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4507 0x410466C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4508 0x4104670
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4509 0x4104674
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4510 0x4104678
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4511 0x410467C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4512 0x4104680
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4513 0x4104684
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4514 0x4104688
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4515 0x410468C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4516 0x4104690
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4517 0x4104694
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4518 0x4104698
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4519 0x410469C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4520 0x41046A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4521 0x41046A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4522 0x41046A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4523 0x41046AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4524 0x41046B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4525 0x41046B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4526 0x41046B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4527 0x41046BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4528 0x41046C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4529 0x41046C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4530 0x41046C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4531 0x41046CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4532 0x41046D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4533 0x41046D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4534 0x41046D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4535 0x41046DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4536 0x41046E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4537 0x41046E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4538 0x41046E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4539 0x41046EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4540 0x41046F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4541 0x41046F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4542 0x41046F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4543 0x41046FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4544 0x4104700
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4545 0x4104704
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4546 0x4104708
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4547 0x410470C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4548 0x4104710
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4549 0x4104714
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4550 0x4104718
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4551 0x410471C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4552 0x4104720
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4553 0x4104724
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4554 0x4104728
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4555 0x410472C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4556 0x4104730
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4557 0x4104734
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4558 0x4104738
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4559 0x410473C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4560 0x4104740
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4561 0x4104744
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4562 0x4104748
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4563 0x410474C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4564 0x4104750
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4565 0x4104754
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4566 0x4104758
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4567 0x410475C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4568 0x4104760
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4569 0x4104764
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4570 0x4104768
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4571 0x410476C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4572 0x4104770
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4573 0x4104774
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4574 0x4104778
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4575 0x410477C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4576 0x4104780
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4577 0x4104784
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4578 0x4104788
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4579 0x410478C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4580 0x4104790
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4581 0x4104794
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4582 0x4104798
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4583 0x410479C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4584 0x41047A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4585 0x41047A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4586 0x41047A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4587 0x41047AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4588 0x41047B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4589 0x41047B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4590 0x41047B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4591 0x41047BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4592 0x41047C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4593 0x41047C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4594 0x41047C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4595 0x41047CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4596 0x41047D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4597 0x41047D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4598 0x41047D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4599 0x41047DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4600 0x41047E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4601 0x41047E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4602 0x41047E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4603 0x41047EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4604 0x41047F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4605 0x41047F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4606 0x41047F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4607 0x41047FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4608 0x4104800
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4609 0x4104804
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4610 0x4104808
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4611 0x410480C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4612 0x4104810
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4613 0x4104814
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4614 0x4104818
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4615 0x410481C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4616 0x4104820
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4617 0x4104824
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4618 0x4104828
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4619 0x410482C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4620 0x4104830
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4621 0x4104834
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4622 0x4104838
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4623 0x410483C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4624 0x4104840
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4625 0x4104844
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4626 0x4104848
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4627 0x410484C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4628 0x4104850
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4629 0x4104854
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4630 0x4104858
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4631 0x410485C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4632 0x4104860
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4633 0x4104864
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4634 0x4104868
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4635 0x410486C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4636 0x4104870
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4637 0x4104874
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4638 0x4104878
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4639 0x410487C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4640 0x4104880
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4641 0x4104884
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4642 0x4104888
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4643 0x410488C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4644 0x4104890
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4645 0x4104894
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4646 0x4104898
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4647 0x410489C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4648 0x41048A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4649 0x41048A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4650 0x41048A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4651 0x41048AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4652 0x41048B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4653 0x41048B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4654 0x41048B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4655 0x41048BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4656 0x41048C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4657 0x41048C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4658 0x41048C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4659 0x41048CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4660 0x41048D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4661 0x41048D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4662 0x41048D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4663 0x41048DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4664 0x41048E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4665 0x41048E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4666 0x41048E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4667 0x41048EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4668 0x41048F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4669 0x41048F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4670 0x41048F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4671 0x41048FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4672 0x4104900
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4673 0x4104904
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4674 0x4104908
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4675 0x410490C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4676 0x4104910
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4677 0x4104914
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4678 0x4104918
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4679 0x410491C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4680 0x4104920
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4681 0x4104924
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4682 0x4104928
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4683 0x410492C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4684 0x4104930
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4685 0x4104934
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4686 0x4104938
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4687 0x410493C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4688 0x4104940
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4689 0x4104944
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4690 0x4104948
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4691 0x410494C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4692 0x4104950
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4693 0x4104954
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4694 0x4104958
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4695 0x410495C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4696 0x4104960
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4697 0x4104964
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4698 0x4104968
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4699 0x410496C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4700 0x4104970
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4701 0x4104974
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4702 0x4104978
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4703 0x410497C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4704 0x4104980
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4705 0x4104984
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4706 0x4104988
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4707 0x410498C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4708 0x4104990
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4709 0x4104994
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4710 0x4104998
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4711 0x410499C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4712 0x41049A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4713 0x41049A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4714 0x41049A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4715 0x41049AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4716 0x41049B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4717 0x41049B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4718 0x41049B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4719 0x41049BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4720 0x41049C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4721 0x41049C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4722 0x41049C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4723 0x41049CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4724 0x41049D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4725 0x41049D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4726 0x41049D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4727 0x41049DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4728 0x41049E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4729 0x41049E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4730 0x41049E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4731 0x41049EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4732 0x41049F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4733 0x41049F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4734 0x41049F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4735 0x41049FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4736 0x4104A00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4737 0x4104A04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4738 0x4104A08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4739 0x4104A0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4740 0x4104A10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4741 0x4104A14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4742 0x4104A18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4743 0x4104A1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4744 0x4104A20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4745 0x4104A24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4746 0x4104A28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4747 0x4104A2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4748 0x4104A30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4749 0x4104A34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4750 0x4104A38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4751 0x4104A3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4752 0x4104A40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4753 0x4104A44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4754 0x4104A48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4755 0x4104A4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4756 0x4104A50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4757 0x4104A54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4758 0x4104A58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4759 0x4104A5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4760 0x4104A60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4761 0x4104A64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4762 0x4104A68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4763 0x4104A6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4764 0x4104A70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4765 0x4104A74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4766 0x4104A78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4767 0x4104A7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4768 0x4104A80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4769 0x4104A84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4770 0x4104A88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4771 0x4104A8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4772 0x4104A90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4773 0x4104A94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4774 0x4104A98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4775 0x4104A9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4776 0x4104AA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4777 0x4104AA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4778 0x4104AA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4779 0x4104AAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4780 0x4104AB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4781 0x4104AB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4782 0x4104AB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4783 0x4104ABC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4784 0x4104AC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4785 0x4104AC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4786 0x4104AC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4787 0x4104ACC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4788 0x4104AD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4789 0x4104AD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4790 0x4104AD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4791 0x4104ADC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4792 0x4104AE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4793 0x4104AE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4794 0x4104AE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4795 0x4104AEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4796 0x4104AF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4797 0x4104AF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4798 0x4104AF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4799 0x4104AFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4800 0x4104B00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4801 0x4104B04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4802 0x4104B08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4803 0x4104B0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4804 0x4104B10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4805 0x4104B14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4806 0x4104B18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4807 0x4104B1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4808 0x4104B20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4809 0x4104B24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4810 0x4104B28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4811 0x4104B2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4812 0x4104B30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4813 0x4104B34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4814 0x4104B38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4815 0x4104B3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4816 0x4104B40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4817 0x4104B44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4818 0x4104B48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4819 0x4104B4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4820 0x4104B50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4821 0x4104B54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4822 0x4104B58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4823 0x4104B5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4824 0x4104B60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4825 0x4104B64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4826 0x4104B68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4827 0x4104B6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4828 0x4104B70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4829 0x4104B74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4830 0x4104B78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4831 0x4104B7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4832 0x4104B80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4833 0x4104B84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4834 0x4104B88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4835 0x4104B8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4836 0x4104B90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4837 0x4104B94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4838 0x4104B98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4839 0x4104B9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4840 0x4104BA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4841 0x4104BA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4842 0x4104BA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4843 0x4104BAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4844 0x4104BB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4845 0x4104BB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4846 0x4104BB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4847 0x4104BBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4848 0x4104BC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4849 0x4104BC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4850 0x4104BC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4851 0x4104BCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4852 0x4104BD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4853 0x4104BD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4854 0x4104BD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4855 0x4104BDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4856 0x4104BE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4857 0x4104BE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4858 0x4104BE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4859 0x4104BEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4860 0x4104BF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4861 0x4104BF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4862 0x4104BF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4863 0x4104BFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4864 0x4104C00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4865 0x4104C04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4866 0x4104C08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4867 0x4104C0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4868 0x4104C10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4869 0x4104C14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4870 0x4104C18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4871 0x4104C1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4872 0x4104C20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4873 0x4104C24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4874 0x4104C28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4875 0x4104C2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4876 0x4104C30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4877 0x4104C34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4878 0x4104C38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4879 0x4104C3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4880 0x4104C40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4881 0x4104C44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4882 0x4104C48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4883 0x4104C4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4884 0x4104C50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4885 0x4104C54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4886 0x4104C58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4887 0x4104C5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4888 0x4104C60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4889 0x4104C64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4890 0x4104C68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4891 0x4104C6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4892 0x4104C70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4893 0x4104C74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4894 0x4104C78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4895 0x4104C7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4896 0x4104C80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4897 0x4104C84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4898 0x4104C88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4899 0x4104C8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4900 0x4104C90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4901 0x4104C94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4902 0x4104C98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4903 0x4104C9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4904 0x4104CA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4905 0x4104CA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4906 0x4104CA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4907 0x4104CAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4908 0x4104CB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4909 0x4104CB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4910 0x4104CB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4911 0x4104CBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4912 0x4104CC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4913 0x4104CC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4914 0x4104CC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4915 0x4104CCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4916 0x4104CD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4917 0x4104CD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4918 0x4104CD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4919 0x4104CDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4920 0x4104CE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4921 0x4104CE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4922 0x4104CE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4923 0x4104CEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4924 0x4104CF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4925 0x4104CF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4926 0x4104CF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4927 0x4104CFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4928 0x4104D00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4929 0x4104D04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4930 0x4104D08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4931 0x4104D0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4932 0x4104D10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4933 0x4104D14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4934 0x4104D18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4935 0x4104D1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4936 0x4104D20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4937 0x4104D24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4938 0x4104D28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4939 0x4104D2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4940 0x4104D30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4941 0x4104D34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4942 0x4104D38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4943 0x4104D3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4944 0x4104D40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4945 0x4104D44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4946 0x4104D48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4947 0x4104D4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4948 0x4104D50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4949 0x4104D54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4950 0x4104D58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4951 0x4104D5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4952 0x4104D60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4953 0x4104D64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4954 0x4104D68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4955 0x4104D6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4956 0x4104D70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4957 0x4104D74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4958 0x4104D78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4959 0x4104D7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4960 0x4104D80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4961 0x4104D84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4962 0x4104D88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4963 0x4104D8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4964 0x4104D90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4965 0x4104D94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4966 0x4104D98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4967 0x4104D9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4968 0x4104DA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4969 0x4104DA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4970 0x4104DA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4971 0x4104DAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4972 0x4104DB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4973 0x4104DB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4974 0x4104DB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4975 0x4104DBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4976 0x4104DC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4977 0x4104DC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4978 0x4104DC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4979 0x4104DCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4980 0x4104DD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4981 0x4104DD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4982 0x4104DD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4983 0x4104DDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4984 0x4104DE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4985 0x4104DE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4986 0x4104DE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4987 0x4104DEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4988 0x4104DF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4989 0x4104DF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4990 0x4104DF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4991 0x4104DFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4992 0x4104E00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4993 0x4104E04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4994 0x4104E08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4995 0x4104E0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4996 0x4104E10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4997 0x4104E14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4998 0x4104E18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_4999 0x4104E1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5000 0x4104E20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5001 0x4104E24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5002 0x4104E28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5003 0x4104E2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5004 0x4104E30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5005 0x4104E34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5006 0x4104E38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5007 0x4104E3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5008 0x4104E40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5009 0x4104E44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5010 0x4104E48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5011 0x4104E4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5012 0x4104E50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5013 0x4104E54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5014 0x4104E58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5015 0x4104E5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5016 0x4104E60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5017 0x4104E64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5018 0x4104E68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5019 0x4104E6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5020 0x4104E70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5021 0x4104E74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5022 0x4104E78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5023 0x4104E7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5024 0x4104E80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5025 0x4104E84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5026 0x4104E88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5027 0x4104E8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5028 0x4104E90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5029 0x4104E94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5030 0x4104E98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5031 0x4104E9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5032 0x4104EA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5033 0x4104EA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5034 0x4104EA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5035 0x4104EAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5036 0x4104EB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5037 0x4104EB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5038 0x4104EB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5039 0x4104EBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5040 0x4104EC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5041 0x4104EC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5042 0x4104EC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5043 0x4104ECC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5044 0x4104ED0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5045 0x4104ED4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5046 0x4104ED8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5047 0x4104EDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5048 0x4104EE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5049 0x4104EE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5050 0x4104EE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5051 0x4104EEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5052 0x4104EF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5053 0x4104EF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5054 0x4104EF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5055 0x4104EFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5056 0x4104F00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5057 0x4104F04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5058 0x4104F08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5059 0x4104F0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5060 0x4104F10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5061 0x4104F14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5062 0x4104F18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5063 0x4104F1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5064 0x4104F20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5065 0x4104F24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5066 0x4104F28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5067 0x4104F2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5068 0x4104F30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5069 0x4104F34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5070 0x4104F38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5071 0x4104F3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5072 0x4104F40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5073 0x4104F44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5074 0x4104F48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5075 0x4104F4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5076 0x4104F50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5077 0x4104F54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5078 0x4104F58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5079 0x4104F5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5080 0x4104F60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5081 0x4104F64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5082 0x4104F68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5083 0x4104F6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5084 0x4104F70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5085 0x4104F74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5086 0x4104F78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5087 0x4104F7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5088 0x4104F80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5089 0x4104F84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5090 0x4104F88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5091 0x4104F8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5092 0x4104F90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5093 0x4104F94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5094 0x4104F98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5095 0x4104F9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5096 0x4104FA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5097 0x4104FA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5098 0x4104FA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5099 0x4104FAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5100 0x4104FB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5101 0x4104FB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5102 0x4104FB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5103 0x4104FBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5104 0x4104FC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5105 0x4104FC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5106 0x4104FC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5107 0x4104FCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5108 0x4104FD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5109 0x4104FD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5110 0x4104FD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5111 0x4104FDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5112 0x4104FE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5113 0x4104FE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5114 0x4104FE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5115 0x4104FEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5116 0x4104FF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5117 0x4104FF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5118 0x4104FF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5119 0x4104FFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5120 0x4105000
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5121 0x4105004
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5122 0x4105008
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5123 0x410500C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5124 0x4105010
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5125 0x4105014
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5126 0x4105018
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5127 0x410501C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5128 0x4105020
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5129 0x4105024
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5130 0x4105028
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5131 0x410502C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5132 0x4105030
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5133 0x4105034
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5134 0x4105038
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5135 0x410503C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5136 0x4105040
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5137 0x4105044
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5138 0x4105048
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5139 0x410504C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5140 0x4105050
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5141 0x4105054
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5142 0x4105058
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5143 0x410505C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5144 0x4105060
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5145 0x4105064
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5146 0x4105068
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5147 0x410506C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5148 0x4105070
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5149 0x4105074
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5150 0x4105078
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5151 0x410507C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5152 0x4105080
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5153 0x4105084
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5154 0x4105088
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5155 0x410508C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5156 0x4105090
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5157 0x4105094
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5158 0x4105098
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5159 0x410509C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5160 0x41050A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5161 0x41050A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5162 0x41050A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5163 0x41050AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5164 0x41050B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5165 0x41050B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5166 0x41050B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5167 0x41050BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5168 0x41050C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5169 0x41050C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5170 0x41050C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5171 0x41050CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5172 0x41050D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5173 0x41050D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5174 0x41050D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5175 0x41050DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5176 0x41050E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5177 0x41050E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5178 0x41050E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5179 0x41050EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5180 0x41050F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5181 0x41050F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5182 0x41050F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5183 0x41050FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5184 0x4105100
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5185 0x4105104
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5186 0x4105108
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5187 0x410510C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5188 0x4105110
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5189 0x4105114
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5190 0x4105118
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5191 0x410511C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5192 0x4105120
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5193 0x4105124
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5194 0x4105128
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5195 0x410512C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5196 0x4105130
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5197 0x4105134
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5198 0x4105138
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5199 0x410513C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5200 0x4105140
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5201 0x4105144
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5202 0x4105148
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5203 0x410514C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5204 0x4105150
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5205 0x4105154
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5206 0x4105158
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5207 0x410515C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5208 0x4105160
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5209 0x4105164
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5210 0x4105168
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5211 0x410516C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5212 0x4105170
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5213 0x4105174
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5214 0x4105178
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5215 0x410517C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5216 0x4105180
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5217 0x4105184
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5218 0x4105188
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5219 0x410518C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5220 0x4105190
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5221 0x4105194
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5222 0x4105198
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5223 0x410519C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5224 0x41051A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5225 0x41051A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5226 0x41051A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5227 0x41051AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5228 0x41051B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5229 0x41051B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5230 0x41051B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5231 0x41051BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5232 0x41051C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5233 0x41051C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5234 0x41051C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5235 0x41051CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5236 0x41051D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5237 0x41051D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5238 0x41051D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5239 0x41051DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5240 0x41051E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5241 0x41051E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5242 0x41051E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5243 0x41051EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5244 0x41051F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5245 0x41051F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5246 0x41051F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5247 0x41051FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5248 0x4105200
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5249 0x4105204
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5250 0x4105208
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5251 0x410520C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5252 0x4105210
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5253 0x4105214
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5254 0x4105218
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5255 0x410521C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5256 0x4105220
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5257 0x4105224
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5258 0x4105228
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5259 0x410522C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5260 0x4105230
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5261 0x4105234
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5262 0x4105238
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5263 0x410523C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5264 0x4105240
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5265 0x4105244
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5266 0x4105248
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5267 0x410524C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5268 0x4105250
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5269 0x4105254
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5270 0x4105258
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5271 0x410525C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5272 0x4105260
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5273 0x4105264
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5274 0x4105268
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5275 0x410526C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5276 0x4105270
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5277 0x4105274
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5278 0x4105278
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5279 0x410527C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5280 0x4105280
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5281 0x4105284
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5282 0x4105288
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5283 0x410528C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5284 0x4105290
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5285 0x4105294
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5286 0x4105298
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5287 0x410529C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5288 0x41052A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5289 0x41052A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5290 0x41052A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5291 0x41052AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5292 0x41052B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5293 0x41052B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5294 0x41052B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5295 0x41052BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5296 0x41052C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5297 0x41052C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5298 0x41052C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5299 0x41052CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5300 0x41052D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5301 0x41052D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5302 0x41052D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5303 0x41052DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5304 0x41052E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5305 0x41052E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5306 0x41052E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5307 0x41052EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5308 0x41052F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5309 0x41052F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5310 0x41052F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5311 0x41052FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5312 0x4105300
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5313 0x4105304
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5314 0x4105308
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5315 0x410530C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5316 0x4105310
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5317 0x4105314
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5318 0x4105318
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5319 0x410531C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5320 0x4105320
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5321 0x4105324
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5322 0x4105328
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5323 0x410532C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5324 0x4105330
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5325 0x4105334
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5326 0x4105338
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5327 0x410533C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5328 0x4105340
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5329 0x4105344
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5330 0x4105348
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5331 0x410534C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5332 0x4105350
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5333 0x4105354
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5334 0x4105358
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5335 0x410535C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5336 0x4105360
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5337 0x4105364
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5338 0x4105368
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5339 0x410536C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5340 0x4105370
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5341 0x4105374
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5342 0x4105378
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5343 0x410537C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5344 0x4105380
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5345 0x4105384
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5346 0x4105388
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5347 0x410538C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5348 0x4105390
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5349 0x4105394
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5350 0x4105398
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5351 0x410539C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5352 0x41053A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5353 0x41053A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5354 0x41053A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5355 0x41053AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5356 0x41053B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5357 0x41053B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5358 0x41053B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5359 0x41053BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5360 0x41053C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5361 0x41053C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5362 0x41053C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5363 0x41053CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5364 0x41053D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5365 0x41053D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5366 0x41053D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5367 0x41053DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5368 0x41053E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5369 0x41053E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5370 0x41053E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5371 0x41053EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5372 0x41053F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5373 0x41053F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5374 0x41053F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5375 0x41053FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5376 0x4105400
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5377 0x4105404
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5378 0x4105408
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5379 0x410540C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5380 0x4105410
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5381 0x4105414
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5382 0x4105418
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5383 0x410541C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5384 0x4105420
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5385 0x4105424
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5386 0x4105428
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5387 0x410542C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5388 0x4105430
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5389 0x4105434
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5390 0x4105438
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5391 0x410543C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5392 0x4105440
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5393 0x4105444
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5394 0x4105448
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5395 0x410544C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5396 0x4105450
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5397 0x4105454
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5398 0x4105458
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5399 0x410545C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5400 0x4105460
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5401 0x4105464
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5402 0x4105468
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5403 0x410546C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5404 0x4105470
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5405 0x4105474
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5406 0x4105478
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5407 0x410547C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5408 0x4105480
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5409 0x4105484
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5410 0x4105488
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5411 0x410548C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5412 0x4105490
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5413 0x4105494
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5414 0x4105498
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5415 0x410549C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5416 0x41054A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5417 0x41054A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5418 0x41054A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5419 0x41054AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5420 0x41054B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5421 0x41054B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5422 0x41054B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5423 0x41054BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5424 0x41054C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5425 0x41054C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5426 0x41054C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5427 0x41054CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5428 0x41054D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5429 0x41054D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5430 0x41054D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5431 0x41054DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5432 0x41054E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5433 0x41054E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5434 0x41054E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5435 0x41054EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5436 0x41054F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5437 0x41054F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5438 0x41054F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5439 0x41054FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5440 0x4105500
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5441 0x4105504
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5442 0x4105508
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5443 0x410550C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5444 0x4105510
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5445 0x4105514
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5446 0x4105518
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5447 0x410551C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5448 0x4105520
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5449 0x4105524
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5450 0x4105528
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5451 0x410552C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5452 0x4105530
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5453 0x4105534
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5454 0x4105538
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5455 0x410553C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5456 0x4105540
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5457 0x4105544
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5458 0x4105548
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5459 0x410554C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5460 0x4105550
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5461 0x4105554
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5462 0x4105558
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5463 0x410555C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5464 0x4105560
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5465 0x4105564
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5466 0x4105568
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5467 0x410556C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5468 0x4105570
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5469 0x4105574
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5470 0x4105578
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5471 0x410557C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5472 0x4105580
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5473 0x4105584
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5474 0x4105588
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5475 0x410558C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5476 0x4105590
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5477 0x4105594
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5478 0x4105598
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5479 0x410559C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5480 0x41055A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5481 0x41055A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5482 0x41055A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5483 0x41055AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5484 0x41055B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5485 0x41055B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5486 0x41055B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5487 0x41055BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5488 0x41055C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5489 0x41055C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5490 0x41055C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5491 0x41055CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5492 0x41055D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5493 0x41055D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5494 0x41055D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5495 0x41055DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5496 0x41055E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5497 0x41055E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5498 0x41055E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5499 0x41055EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5500 0x41055F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5501 0x41055F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5502 0x41055F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5503 0x41055FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5504 0x4105600
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5505 0x4105604
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5506 0x4105608
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5507 0x410560C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5508 0x4105610
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5509 0x4105614
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5510 0x4105618
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5511 0x410561C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5512 0x4105620
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5513 0x4105624
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5514 0x4105628
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5515 0x410562C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5516 0x4105630
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5517 0x4105634
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5518 0x4105638
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5519 0x410563C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5520 0x4105640
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5521 0x4105644
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5522 0x4105648
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5523 0x410564C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5524 0x4105650
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5525 0x4105654
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5526 0x4105658
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5527 0x410565C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5528 0x4105660
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5529 0x4105664
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5530 0x4105668
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5531 0x410566C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5532 0x4105670
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5533 0x4105674
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5534 0x4105678
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5535 0x410567C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5536 0x4105680
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5537 0x4105684
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5538 0x4105688
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5539 0x410568C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5540 0x4105690
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5541 0x4105694
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5542 0x4105698
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5543 0x410569C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5544 0x41056A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5545 0x41056A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5546 0x41056A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5547 0x41056AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5548 0x41056B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5549 0x41056B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5550 0x41056B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5551 0x41056BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5552 0x41056C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5553 0x41056C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5554 0x41056C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5555 0x41056CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5556 0x41056D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5557 0x41056D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5558 0x41056D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5559 0x41056DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5560 0x41056E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5561 0x41056E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5562 0x41056E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5563 0x41056EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5564 0x41056F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5565 0x41056F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5566 0x41056F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5567 0x41056FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5568 0x4105700
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5569 0x4105704
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5570 0x4105708
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5571 0x410570C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5572 0x4105710
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5573 0x4105714
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5574 0x4105718
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5575 0x410571C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5576 0x4105720
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5577 0x4105724
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5578 0x4105728
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5579 0x410572C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5580 0x4105730
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5581 0x4105734
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5582 0x4105738
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5583 0x410573C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5584 0x4105740
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5585 0x4105744
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5586 0x4105748
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5587 0x410574C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5588 0x4105750
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5589 0x4105754
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5590 0x4105758
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5591 0x410575C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5592 0x4105760
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5593 0x4105764
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5594 0x4105768
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5595 0x410576C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5596 0x4105770
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5597 0x4105774
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5598 0x4105778
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5599 0x410577C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5600 0x4105780
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5601 0x4105784
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5602 0x4105788
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5603 0x410578C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5604 0x4105790
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5605 0x4105794
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5606 0x4105798
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5607 0x410579C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5608 0x41057A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5609 0x41057A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5610 0x41057A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5611 0x41057AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5612 0x41057B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5613 0x41057B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5614 0x41057B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5615 0x41057BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5616 0x41057C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5617 0x41057C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5618 0x41057C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5619 0x41057CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5620 0x41057D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5621 0x41057D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5622 0x41057D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5623 0x41057DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5624 0x41057E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5625 0x41057E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5626 0x41057E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5627 0x41057EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5628 0x41057F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5629 0x41057F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5630 0x41057F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5631 0x41057FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5632 0x4105800
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5633 0x4105804
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5634 0x4105808
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5635 0x410580C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5636 0x4105810
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5637 0x4105814
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5638 0x4105818
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5639 0x410581C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5640 0x4105820
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5641 0x4105824
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5642 0x4105828
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5643 0x410582C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5644 0x4105830
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5645 0x4105834
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5646 0x4105838
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5647 0x410583C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5648 0x4105840
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5649 0x4105844
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5650 0x4105848
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5651 0x410584C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5652 0x4105850
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5653 0x4105854
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5654 0x4105858
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5655 0x410585C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5656 0x4105860
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5657 0x4105864
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5658 0x4105868
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5659 0x410586C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5660 0x4105870
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5661 0x4105874
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5662 0x4105878
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5663 0x410587C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5664 0x4105880
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5665 0x4105884
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5666 0x4105888
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5667 0x410588C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5668 0x4105890
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5669 0x4105894
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5670 0x4105898
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5671 0x410589C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5672 0x41058A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5673 0x41058A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5674 0x41058A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5675 0x41058AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5676 0x41058B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5677 0x41058B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5678 0x41058B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5679 0x41058BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5680 0x41058C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5681 0x41058C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5682 0x41058C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5683 0x41058CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5684 0x41058D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5685 0x41058D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5686 0x41058D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5687 0x41058DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5688 0x41058E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5689 0x41058E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5690 0x41058E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5691 0x41058EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5692 0x41058F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5693 0x41058F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5694 0x41058F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5695 0x41058FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5696 0x4105900
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5697 0x4105904
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5698 0x4105908
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5699 0x410590C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5700 0x4105910
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5701 0x4105914
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5702 0x4105918
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5703 0x410591C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5704 0x4105920
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5705 0x4105924
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5706 0x4105928
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5707 0x410592C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5708 0x4105930
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5709 0x4105934
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5710 0x4105938
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5711 0x410593C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5712 0x4105940
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5713 0x4105944
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5714 0x4105948
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5715 0x410594C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5716 0x4105950
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5717 0x4105954
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5718 0x4105958
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5719 0x410595C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5720 0x4105960
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5721 0x4105964
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5722 0x4105968
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5723 0x410596C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5724 0x4105970
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5725 0x4105974
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5726 0x4105978
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5727 0x410597C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5728 0x4105980
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5729 0x4105984
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5730 0x4105988
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5731 0x410598C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5732 0x4105990
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5733 0x4105994
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5734 0x4105998
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5735 0x410599C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5736 0x41059A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5737 0x41059A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5738 0x41059A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5739 0x41059AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5740 0x41059B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5741 0x41059B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5742 0x41059B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5743 0x41059BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5744 0x41059C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5745 0x41059C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5746 0x41059C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5747 0x41059CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5748 0x41059D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5749 0x41059D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5750 0x41059D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5751 0x41059DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5752 0x41059E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5753 0x41059E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5754 0x41059E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5755 0x41059EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5756 0x41059F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5757 0x41059F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5758 0x41059F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5759 0x41059FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5760 0x4105A00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5761 0x4105A04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5762 0x4105A08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5763 0x4105A0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5764 0x4105A10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5765 0x4105A14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5766 0x4105A18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5767 0x4105A1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5768 0x4105A20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5769 0x4105A24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5770 0x4105A28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5771 0x4105A2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5772 0x4105A30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5773 0x4105A34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5774 0x4105A38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5775 0x4105A3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5776 0x4105A40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5777 0x4105A44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5778 0x4105A48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5779 0x4105A4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5780 0x4105A50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5781 0x4105A54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5782 0x4105A58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5783 0x4105A5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5784 0x4105A60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5785 0x4105A64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5786 0x4105A68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5787 0x4105A6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5788 0x4105A70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5789 0x4105A74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5790 0x4105A78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5791 0x4105A7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5792 0x4105A80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5793 0x4105A84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5794 0x4105A88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5795 0x4105A8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5796 0x4105A90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5797 0x4105A94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5798 0x4105A98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5799 0x4105A9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5800 0x4105AA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5801 0x4105AA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5802 0x4105AA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5803 0x4105AAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5804 0x4105AB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5805 0x4105AB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5806 0x4105AB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5807 0x4105ABC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5808 0x4105AC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5809 0x4105AC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5810 0x4105AC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5811 0x4105ACC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5812 0x4105AD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5813 0x4105AD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5814 0x4105AD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5815 0x4105ADC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5816 0x4105AE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5817 0x4105AE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5818 0x4105AE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5819 0x4105AEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5820 0x4105AF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5821 0x4105AF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5822 0x4105AF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5823 0x4105AFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5824 0x4105B00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5825 0x4105B04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5826 0x4105B08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5827 0x4105B0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5828 0x4105B10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5829 0x4105B14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5830 0x4105B18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5831 0x4105B1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5832 0x4105B20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5833 0x4105B24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5834 0x4105B28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5835 0x4105B2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5836 0x4105B30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5837 0x4105B34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5838 0x4105B38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5839 0x4105B3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5840 0x4105B40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5841 0x4105B44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5842 0x4105B48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5843 0x4105B4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5844 0x4105B50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5845 0x4105B54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5846 0x4105B58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5847 0x4105B5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5848 0x4105B60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5849 0x4105B64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5850 0x4105B68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5851 0x4105B6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5852 0x4105B70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5853 0x4105B74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5854 0x4105B78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5855 0x4105B7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5856 0x4105B80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5857 0x4105B84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5858 0x4105B88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5859 0x4105B8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5860 0x4105B90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5861 0x4105B94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5862 0x4105B98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5863 0x4105B9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5864 0x4105BA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5865 0x4105BA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5866 0x4105BA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5867 0x4105BAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5868 0x4105BB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5869 0x4105BB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5870 0x4105BB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5871 0x4105BBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5872 0x4105BC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5873 0x4105BC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5874 0x4105BC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5875 0x4105BCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5876 0x4105BD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5877 0x4105BD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5878 0x4105BD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5879 0x4105BDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5880 0x4105BE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5881 0x4105BE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5882 0x4105BE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5883 0x4105BEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5884 0x4105BF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5885 0x4105BF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5886 0x4105BF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5887 0x4105BFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5888 0x4105C00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5889 0x4105C04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5890 0x4105C08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5891 0x4105C0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5892 0x4105C10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5893 0x4105C14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5894 0x4105C18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5895 0x4105C1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5896 0x4105C20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5897 0x4105C24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5898 0x4105C28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5899 0x4105C2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5900 0x4105C30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5901 0x4105C34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5902 0x4105C38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5903 0x4105C3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5904 0x4105C40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5905 0x4105C44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5906 0x4105C48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5907 0x4105C4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5908 0x4105C50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5909 0x4105C54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5910 0x4105C58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5911 0x4105C5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5912 0x4105C60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5913 0x4105C64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5914 0x4105C68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5915 0x4105C6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5916 0x4105C70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5917 0x4105C74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5918 0x4105C78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5919 0x4105C7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5920 0x4105C80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5921 0x4105C84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5922 0x4105C88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5923 0x4105C8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5924 0x4105C90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5925 0x4105C94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5926 0x4105C98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5927 0x4105C9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5928 0x4105CA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5929 0x4105CA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5930 0x4105CA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5931 0x4105CAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5932 0x4105CB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5933 0x4105CB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5934 0x4105CB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5935 0x4105CBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5936 0x4105CC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5937 0x4105CC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5938 0x4105CC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5939 0x4105CCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5940 0x4105CD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5941 0x4105CD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5942 0x4105CD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5943 0x4105CDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5944 0x4105CE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5945 0x4105CE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5946 0x4105CE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5947 0x4105CEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5948 0x4105CF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5949 0x4105CF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5950 0x4105CF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5951 0x4105CFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5952 0x4105D00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5953 0x4105D04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5954 0x4105D08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5955 0x4105D0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5956 0x4105D10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5957 0x4105D14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5958 0x4105D18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5959 0x4105D1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5960 0x4105D20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5961 0x4105D24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5962 0x4105D28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5963 0x4105D2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5964 0x4105D30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5965 0x4105D34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5966 0x4105D38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5967 0x4105D3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5968 0x4105D40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5969 0x4105D44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5970 0x4105D48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5971 0x4105D4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5972 0x4105D50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5973 0x4105D54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5974 0x4105D58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5975 0x4105D5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5976 0x4105D60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5977 0x4105D64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5978 0x4105D68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5979 0x4105D6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5980 0x4105D70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5981 0x4105D74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5982 0x4105D78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5983 0x4105D7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5984 0x4105D80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5985 0x4105D84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5986 0x4105D88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5987 0x4105D8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5988 0x4105D90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5989 0x4105D94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5990 0x4105D98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5991 0x4105D9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5992 0x4105DA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5993 0x4105DA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5994 0x4105DA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5995 0x4105DAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5996 0x4105DB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5997 0x4105DB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5998 0x4105DB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_5999 0x4105DBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6000 0x4105DC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6001 0x4105DC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6002 0x4105DC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6003 0x4105DCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6004 0x4105DD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6005 0x4105DD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6006 0x4105DD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6007 0x4105DDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6008 0x4105DE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6009 0x4105DE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6010 0x4105DE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6011 0x4105DEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6012 0x4105DF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6013 0x4105DF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6014 0x4105DF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6015 0x4105DFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6016 0x4105E00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6017 0x4105E04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6018 0x4105E08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6019 0x4105E0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6020 0x4105E10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6021 0x4105E14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6022 0x4105E18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6023 0x4105E1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6024 0x4105E20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6025 0x4105E24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6026 0x4105E28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6027 0x4105E2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6028 0x4105E30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6029 0x4105E34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6030 0x4105E38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6031 0x4105E3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6032 0x4105E40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6033 0x4105E44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6034 0x4105E48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6035 0x4105E4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6036 0x4105E50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6037 0x4105E54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6038 0x4105E58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6039 0x4105E5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6040 0x4105E60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6041 0x4105E64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6042 0x4105E68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6043 0x4105E6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6044 0x4105E70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6045 0x4105E74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6046 0x4105E78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6047 0x4105E7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6048 0x4105E80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6049 0x4105E84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6050 0x4105E88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6051 0x4105E8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6052 0x4105E90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6053 0x4105E94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6054 0x4105E98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6055 0x4105E9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6056 0x4105EA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6057 0x4105EA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6058 0x4105EA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6059 0x4105EAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6060 0x4105EB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6061 0x4105EB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6062 0x4105EB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6063 0x4105EBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6064 0x4105EC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6065 0x4105EC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6066 0x4105EC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6067 0x4105ECC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6068 0x4105ED0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6069 0x4105ED4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6070 0x4105ED8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6071 0x4105EDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6072 0x4105EE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6073 0x4105EE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6074 0x4105EE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6075 0x4105EEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6076 0x4105EF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6077 0x4105EF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6078 0x4105EF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6079 0x4105EFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6080 0x4105F00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6081 0x4105F04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6082 0x4105F08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6083 0x4105F0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6084 0x4105F10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6085 0x4105F14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6086 0x4105F18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6087 0x4105F1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6088 0x4105F20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6089 0x4105F24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6090 0x4105F28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6091 0x4105F2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6092 0x4105F30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6093 0x4105F34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6094 0x4105F38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6095 0x4105F3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6096 0x4105F40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6097 0x4105F44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6098 0x4105F48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6099 0x4105F4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6100 0x4105F50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6101 0x4105F54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6102 0x4105F58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6103 0x4105F5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6104 0x4105F60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6105 0x4105F64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6106 0x4105F68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6107 0x4105F6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6108 0x4105F70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6109 0x4105F74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6110 0x4105F78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6111 0x4105F7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6112 0x4105F80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6113 0x4105F84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6114 0x4105F88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6115 0x4105F8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6116 0x4105F90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6117 0x4105F94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6118 0x4105F98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6119 0x4105F9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6120 0x4105FA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6121 0x4105FA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6122 0x4105FA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6123 0x4105FAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6124 0x4105FB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6125 0x4105FB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6126 0x4105FB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6127 0x4105FBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6128 0x4105FC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6129 0x4105FC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6130 0x4105FC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6131 0x4105FCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6132 0x4105FD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6133 0x4105FD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6134 0x4105FD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6135 0x4105FDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6136 0x4105FE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6137 0x4105FE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6138 0x4105FE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6139 0x4105FEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6140 0x4105FF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6141 0x4105FF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6142 0x4105FF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6143 0x4105FFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6144 0x4106000
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6145 0x4106004
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6146 0x4106008
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6147 0x410600C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6148 0x4106010
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6149 0x4106014
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6150 0x4106018
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6151 0x410601C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6152 0x4106020
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6153 0x4106024
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6154 0x4106028
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6155 0x410602C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6156 0x4106030
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6157 0x4106034
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6158 0x4106038
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6159 0x410603C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6160 0x4106040
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6161 0x4106044
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6162 0x4106048
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6163 0x410604C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6164 0x4106050
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6165 0x4106054
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6166 0x4106058
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6167 0x410605C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6168 0x4106060
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6169 0x4106064
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6170 0x4106068
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6171 0x410606C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6172 0x4106070
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6173 0x4106074
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6174 0x4106078
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6175 0x410607C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6176 0x4106080
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6177 0x4106084
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6178 0x4106088
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6179 0x410608C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6180 0x4106090
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6181 0x4106094
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6182 0x4106098
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6183 0x410609C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6184 0x41060A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6185 0x41060A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6186 0x41060A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6187 0x41060AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6188 0x41060B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6189 0x41060B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6190 0x41060B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6191 0x41060BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6192 0x41060C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6193 0x41060C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6194 0x41060C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6195 0x41060CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6196 0x41060D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6197 0x41060D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6198 0x41060D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6199 0x41060DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6200 0x41060E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6201 0x41060E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6202 0x41060E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6203 0x41060EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6204 0x41060F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6205 0x41060F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6206 0x41060F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6207 0x41060FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6208 0x4106100
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6209 0x4106104
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6210 0x4106108
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6211 0x410610C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6212 0x4106110
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6213 0x4106114
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6214 0x4106118
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6215 0x410611C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6216 0x4106120
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6217 0x4106124
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6218 0x4106128
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6219 0x410612C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6220 0x4106130
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6221 0x4106134
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6222 0x4106138
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6223 0x410613C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6224 0x4106140
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6225 0x4106144
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6226 0x4106148
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6227 0x410614C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6228 0x4106150
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6229 0x4106154
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6230 0x4106158
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6231 0x410615C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6232 0x4106160
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6233 0x4106164
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6234 0x4106168
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6235 0x410616C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6236 0x4106170
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6237 0x4106174
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6238 0x4106178
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6239 0x410617C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6240 0x4106180
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6241 0x4106184
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6242 0x4106188
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6243 0x410618C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6244 0x4106190
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6245 0x4106194
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6246 0x4106198
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6247 0x410619C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6248 0x41061A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6249 0x41061A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6250 0x41061A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6251 0x41061AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6252 0x41061B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6253 0x41061B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6254 0x41061B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6255 0x41061BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6256 0x41061C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6257 0x41061C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6258 0x41061C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6259 0x41061CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6260 0x41061D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6261 0x41061D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6262 0x41061D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6263 0x41061DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6264 0x41061E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6265 0x41061E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6266 0x41061E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6267 0x41061EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6268 0x41061F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6269 0x41061F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6270 0x41061F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6271 0x41061FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6272 0x4106200
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6273 0x4106204
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6274 0x4106208
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6275 0x410620C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6276 0x4106210
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6277 0x4106214
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6278 0x4106218
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6279 0x410621C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6280 0x4106220
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6281 0x4106224
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6282 0x4106228
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6283 0x410622C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6284 0x4106230
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6285 0x4106234
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6286 0x4106238
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6287 0x410623C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6288 0x4106240
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6289 0x4106244
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6290 0x4106248
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6291 0x410624C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6292 0x4106250
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6293 0x4106254
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6294 0x4106258
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6295 0x410625C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6296 0x4106260
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6297 0x4106264
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6298 0x4106268
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6299 0x410626C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6300 0x4106270
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6301 0x4106274
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6302 0x4106278
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6303 0x410627C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6304 0x4106280
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6305 0x4106284
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6306 0x4106288
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6307 0x410628C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6308 0x4106290
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6309 0x4106294
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6310 0x4106298
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6311 0x410629C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6312 0x41062A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6313 0x41062A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6314 0x41062A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6315 0x41062AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6316 0x41062B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6317 0x41062B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6318 0x41062B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6319 0x41062BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6320 0x41062C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6321 0x41062C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6322 0x41062C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6323 0x41062CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6324 0x41062D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6325 0x41062D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6326 0x41062D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6327 0x41062DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6328 0x41062E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6329 0x41062E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6330 0x41062E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6331 0x41062EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6332 0x41062F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6333 0x41062F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6334 0x41062F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6335 0x41062FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6336 0x4106300
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6337 0x4106304
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6338 0x4106308
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6339 0x410630C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6340 0x4106310
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6341 0x4106314
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6342 0x4106318
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6343 0x410631C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6344 0x4106320
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6345 0x4106324
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6346 0x4106328
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6347 0x410632C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6348 0x4106330
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6349 0x4106334
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6350 0x4106338
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6351 0x410633C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6352 0x4106340
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6353 0x4106344
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6354 0x4106348
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6355 0x410634C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6356 0x4106350
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6357 0x4106354
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6358 0x4106358
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6359 0x410635C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6360 0x4106360
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6361 0x4106364
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6362 0x4106368
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6363 0x410636C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6364 0x4106370
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6365 0x4106374
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6366 0x4106378
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6367 0x410637C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6368 0x4106380
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6369 0x4106384
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6370 0x4106388
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6371 0x410638C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6372 0x4106390
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6373 0x4106394
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6374 0x4106398
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6375 0x410639C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6376 0x41063A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6377 0x41063A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6378 0x41063A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6379 0x41063AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6380 0x41063B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6381 0x41063B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6382 0x41063B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6383 0x41063BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6384 0x41063C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6385 0x41063C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6386 0x41063C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6387 0x41063CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6388 0x41063D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6389 0x41063D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6390 0x41063D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6391 0x41063DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6392 0x41063E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6393 0x41063E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6394 0x41063E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6395 0x41063EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6396 0x41063F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6397 0x41063F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6398 0x41063F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6399 0x41063FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6400 0x4106400
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6401 0x4106404
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6402 0x4106408
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6403 0x410640C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6404 0x4106410
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6405 0x4106414
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6406 0x4106418
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6407 0x410641C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6408 0x4106420
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6409 0x4106424
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6410 0x4106428
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6411 0x410642C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6412 0x4106430
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6413 0x4106434
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6414 0x4106438
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6415 0x410643C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6416 0x4106440
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6417 0x4106444
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6418 0x4106448
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6419 0x410644C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6420 0x4106450
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6421 0x4106454
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6422 0x4106458
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6423 0x410645C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6424 0x4106460
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6425 0x4106464
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6426 0x4106468
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6427 0x410646C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6428 0x4106470
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6429 0x4106474
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6430 0x4106478
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6431 0x410647C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6432 0x4106480
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6433 0x4106484
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6434 0x4106488
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6435 0x410648C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6436 0x4106490
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6437 0x4106494
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6438 0x4106498
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6439 0x410649C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6440 0x41064A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6441 0x41064A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6442 0x41064A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6443 0x41064AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6444 0x41064B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6445 0x41064B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6446 0x41064B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6447 0x41064BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6448 0x41064C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6449 0x41064C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6450 0x41064C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6451 0x41064CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6452 0x41064D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6453 0x41064D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6454 0x41064D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6455 0x41064DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6456 0x41064E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6457 0x41064E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6458 0x41064E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6459 0x41064EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6460 0x41064F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6461 0x41064F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6462 0x41064F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6463 0x41064FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6464 0x4106500
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6465 0x4106504
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6466 0x4106508
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6467 0x410650C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6468 0x4106510
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6469 0x4106514
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6470 0x4106518
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6471 0x410651C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6472 0x4106520
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6473 0x4106524
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6474 0x4106528
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6475 0x410652C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6476 0x4106530
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6477 0x4106534
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6478 0x4106538
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6479 0x410653C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6480 0x4106540
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6481 0x4106544
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6482 0x4106548
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6483 0x410654C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6484 0x4106550
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6485 0x4106554
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6486 0x4106558
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6487 0x410655C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6488 0x4106560
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6489 0x4106564
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6490 0x4106568
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6491 0x410656C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6492 0x4106570
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6493 0x4106574
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6494 0x4106578
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6495 0x410657C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6496 0x4106580
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6497 0x4106584
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6498 0x4106588
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6499 0x410658C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6500 0x4106590
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6501 0x4106594
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6502 0x4106598
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6503 0x410659C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6504 0x41065A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6505 0x41065A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6506 0x41065A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6507 0x41065AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6508 0x41065B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6509 0x41065B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6510 0x41065B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6511 0x41065BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6512 0x41065C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6513 0x41065C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6514 0x41065C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6515 0x41065CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6516 0x41065D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6517 0x41065D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6518 0x41065D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6519 0x41065DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6520 0x41065E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6521 0x41065E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6522 0x41065E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6523 0x41065EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6524 0x41065F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6525 0x41065F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6526 0x41065F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6527 0x41065FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6528 0x4106600
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6529 0x4106604
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6530 0x4106608
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6531 0x410660C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6532 0x4106610
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6533 0x4106614
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6534 0x4106618
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6535 0x410661C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6536 0x4106620
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6537 0x4106624
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6538 0x4106628
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6539 0x410662C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6540 0x4106630
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6541 0x4106634
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6542 0x4106638
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6543 0x410663C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6544 0x4106640
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6545 0x4106644
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6546 0x4106648
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6547 0x410664C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6548 0x4106650
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6549 0x4106654
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6550 0x4106658
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6551 0x410665C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6552 0x4106660
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6553 0x4106664
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6554 0x4106668
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6555 0x410666C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6556 0x4106670
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6557 0x4106674
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6558 0x4106678
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6559 0x410667C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6560 0x4106680
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6561 0x4106684
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6562 0x4106688
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6563 0x410668C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6564 0x4106690
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6565 0x4106694
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6566 0x4106698
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6567 0x410669C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6568 0x41066A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6569 0x41066A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6570 0x41066A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6571 0x41066AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6572 0x41066B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6573 0x41066B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6574 0x41066B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6575 0x41066BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6576 0x41066C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6577 0x41066C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6578 0x41066C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6579 0x41066CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6580 0x41066D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6581 0x41066D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6582 0x41066D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6583 0x41066DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6584 0x41066E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6585 0x41066E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6586 0x41066E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6587 0x41066EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6588 0x41066F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6589 0x41066F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6590 0x41066F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6591 0x41066FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6592 0x4106700
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6593 0x4106704
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6594 0x4106708
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6595 0x410670C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6596 0x4106710
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6597 0x4106714
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6598 0x4106718
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6599 0x410671C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6600 0x4106720
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6601 0x4106724
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6602 0x4106728
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6603 0x410672C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6604 0x4106730
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6605 0x4106734
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6606 0x4106738
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6607 0x410673C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6608 0x4106740
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6609 0x4106744
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6610 0x4106748
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6611 0x410674C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6612 0x4106750
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6613 0x4106754
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6614 0x4106758
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6615 0x410675C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6616 0x4106760
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6617 0x4106764
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6618 0x4106768
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6619 0x410676C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6620 0x4106770
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6621 0x4106774
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6622 0x4106778
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6623 0x410677C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6624 0x4106780
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6625 0x4106784
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6626 0x4106788
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6627 0x410678C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6628 0x4106790
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6629 0x4106794
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6630 0x4106798
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6631 0x410679C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6632 0x41067A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6633 0x41067A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6634 0x41067A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6635 0x41067AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6636 0x41067B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6637 0x41067B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6638 0x41067B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6639 0x41067BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6640 0x41067C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6641 0x41067C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6642 0x41067C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6643 0x41067CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6644 0x41067D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6645 0x41067D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6646 0x41067D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6647 0x41067DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6648 0x41067E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6649 0x41067E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6650 0x41067E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6651 0x41067EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6652 0x41067F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6653 0x41067F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6654 0x41067F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6655 0x41067FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6656 0x4106800
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6657 0x4106804
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6658 0x4106808
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6659 0x410680C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6660 0x4106810
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6661 0x4106814
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6662 0x4106818
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6663 0x410681C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6664 0x4106820
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6665 0x4106824
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6666 0x4106828
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6667 0x410682C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6668 0x4106830
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6669 0x4106834
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6670 0x4106838
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6671 0x410683C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6672 0x4106840
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6673 0x4106844
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6674 0x4106848
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6675 0x410684C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6676 0x4106850
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6677 0x4106854
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6678 0x4106858
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6679 0x410685C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6680 0x4106860
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6681 0x4106864
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6682 0x4106868
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6683 0x410686C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6684 0x4106870
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6685 0x4106874
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6686 0x4106878
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6687 0x410687C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6688 0x4106880
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6689 0x4106884
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6690 0x4106888
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6691 0x410688C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6692 0x4106890
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6693 0x4106894
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6694 0x4106898
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6695 0x410689C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6696 0x41068A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6697 0x41068A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6698 0x41068A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6699 0x41068AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6700 0x41068B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6701 0x41068B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6702 0x41068B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6703 0x41068BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6704 0x41068C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6705 0x41068C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6706 0x41068C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6707 0x41068CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6708 0x41068D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6709 0x41068D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6710 0x41068D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6711 0x41068DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6712 0x41068E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6713 0x41068E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6714 0x41068E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6715 0x41068EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6716 0x41068F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6717 0x41068F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6718 0x41068F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6719 0x41068FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6720 0x4106900
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6721 0x4106904
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6722 0x4106908
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6723 0x410690C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6724 0x4106910
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6725 0x4106914
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6726 0x4106918
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6727 0x410691C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6728 0x4106920
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6729 0x4106924
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6730 0x4106928
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6731 0x410692C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6732 0x4106930
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6733 0x4106934
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6734 0x4106938
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6735 0x410693C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6736 0x4106940
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6737 0x4106944
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6738 0x4106948
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6739 0x410694C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6740 0x4106950
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6741 0x4106954
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6742 0x4106958
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6743 0x410695C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6744 0x4106960
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6745 0x4106964
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6746 0x4106968
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6747 0x410696C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6748 0x4106970
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6749 0x4106974
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6750 0x4106978
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6751 0x410697C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6752 0x4106980
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6753 0x4106984
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6754 0x4106988
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6755 0x410698C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6756 0x4106990
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6757 0x4106994
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6758 0x4106998
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6759 0x410699C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6760 0x41069A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6761 0x41069A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6762 0x41069A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6763 0x41069AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6764 0x41069B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6765 0x41069B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6766 0x41069B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6767 0x41069BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6768 0x41069C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6769 0x41069C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6770 0x41069C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6771 0x41069CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6772 0x41069D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6773 0x41069D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6774 0x41069D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6775 0x41069DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6776 0x41069E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6777 0x41069E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6778 0x41069E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6779 0x41069EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6780 0x41069F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6781 0x41069F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6782 0x41069F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6783 0x41069FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6784 0x4106A00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6785 0x4106A04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6786 0x4106A08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6787 0x4106A0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6788 0x4106A10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6789 0x4106A14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6790 0x4106A18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6791 0x4106A1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6792 0x4106A20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6793 0x4106A24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6794 0x4106A28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6795 0x4106A2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6796 0x4106A30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6797 0x4106A34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6798 0x4106A38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6799 0x4106A3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6800 0x4106A40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6801 0x4106A44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6802 0x4106A48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6803 0x4106A4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6804 0x4106A50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6805 0x4106A54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6806 0x4106A58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6807 0x4106A5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6808 0x4106A60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6809 0x4106A64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6810 0x4106A68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6811 0x4106A6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6812 0x4106A70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6813 0x4106A74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6814 0x4106A78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6815 0x4106A7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6816 0x4106A80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6817 0x4106A84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6818 0x4106A88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6819 0x4106A8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6820 0x4106A90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6821 0x4106A94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6822 0x4106A98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6823 0x4106A9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6824 0x4106AA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6825 0x4106AA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6826 0x4106AA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6827 0x4106AAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6828 0x4106AB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6829 0x4106AB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6830 0x4106AB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6831 0x4106ABC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6832 0x4106AC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6833 0x4106AC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6834 0x4106AC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6835 0x4106ACC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6836 0x4106AD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6837 0x4106AD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6838 0x4106AD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6839 0x4106ADC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6840 0x4106AE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6841 0x4106AE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6842 0x4106AE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6843 0x4106AEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6844 0x4106AF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6845 0x4106AF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6846 0x4106AF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6847 0x4106AFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6848 0x4106B00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6849 0x4106B04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6850 0x4106B08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6851 0x4106B0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6852 0x4106B10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6853 0x4106B14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6854 0x4106B18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6855 0x4106B1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6856 0x4106B20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6857 0x4106B24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6858 0x4106B28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6859 0x4106B2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6860 0x4106B30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6861 0x4106B34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6862 0x4106B38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6863 0x4106B3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6864 0x4106B40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6865 0x4106B44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6866 0x4106B48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6867 0x4106B4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6868 0x4106B50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6869 0x4106B54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6870 0x4106B58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6871 0x4106B5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6872 0x4106B60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6873 0x4106B64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6874 0x4106B68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6875 0x4106B6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6876 0x4106B70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6877 0x4106B74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6878 0x4106B78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6879 0x4106B7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6880 0x4106B80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6881 0x4106B84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6882 0x4106B88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6883 0x4106B8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6884 0x4106B90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6885 0x4106B94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6886 0x4106B98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6887 0x4106B9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6888 0x4106BA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6889 0x4106BA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6890 0x4106BA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6891 0x4106BAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6892 0x4106BB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6893 0x4106BB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6894 0x4106BB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6895 0x4106BBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6896 0x4106BC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6897 0x4106BC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6898 0x4106BC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6899 0x4106BCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6900 0x4106BD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6901 0x4106BD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6902 0x4106BD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6903 0x4106BDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6904 0x4106BE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6905 0x4106BE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6906 0x4106BE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6907 0x4106BEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6908 0x4106BF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6909 0x4106BF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6910 0x4106BF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6911 0x4106BFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6912 0x4106C00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6913 0x4106C04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6914 0x4106C08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6915 0x4106C0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6916 0x4106C10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6917 0x4106C14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6918 0x4106C18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6919 0x4106C1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6920 0x4106C20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6921 0x4106C24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6922 0x4106C28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6923 0x4106C2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6924 0x4106C30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6925 0x4106C34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6926 0x4106C38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6927 0x4106C3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6928 0x4106C40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6929 0x4106C44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6930 0x4106C48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6931 0x4106C4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6932 0x4106C50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6933 0x4106C54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6934 0x4106C58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6935 0x4106C5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6936 0x4106C60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6937 0x4106C64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6938 0x4106C68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6939 0x4106C6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6940 0x4106C70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6941 0x4106C74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6942 0x4106C78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6943 0x4106C7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6944 0x4106C80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6945 0x4106C84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6946 0x4106C88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6947 0x4106C8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6948 0x4106C90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6949 0x4106C94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6950 0x4106C98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6951 0x4106C9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6952 0x4106CA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6953 0x4106CA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6954 0x4106CA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6955 0x4106CAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6956 0x4106CB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6957 0x4106CB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6958 0x4106CB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6959 0x4106CBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6960 0x4106CC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6961 0x4106CC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6962 0x4106CC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6963 0x4106CCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6964 0x4106CD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6965 0x4106CD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6966 0x4106CD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6967 0x4106CDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6968 0x4106CE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6969 0x4106CE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6970 0x4106CE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6971 0x4106CEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6972 0x4106CF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6973 0x4106CF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6974 0x4106CF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6975 0x4106CFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6976 0x4106D00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6977 0x4106D04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6978 0x4106D08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6979 0x4106D0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6980 0x4106D10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6981 0x4106D14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6982 0x4106D18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6983 0x4106D1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6984 0x4106D20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6985 0x4106D24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6986 0x4106D28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6987 0x4106D2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6988 0x4106D30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6989 0x4106D34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6990 0x4106D38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6991 0x4106D3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6992 0x4106D40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6993 0x4106D44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6994 0x4106D48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6995 0x4106D4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6996 0x4106D50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6997 0x4106D54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6998 0x4106D58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_6999 0x4106D5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7000 0x4106D60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7001 0x4106D64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7002 0x4106D68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7003 0x4106D6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7004 0x4106D70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7005 0x4106D74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7006 0x4106D78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7007 0x4106D7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7008 0x4106D80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7009 0x4106D84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7010 0x4106D88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7011 0x4106D8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7012 0x4106D90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7013 0x4106D94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7014 0x4106D98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7015 0x4106D9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7016 0x4106DA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7017 0x4106DA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7018 0x4106DA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7019 0x4106DAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7020 0x4106DB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7021 0x4106DB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7022 0x4106DB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7023 0x4106DBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7024 0x4106DC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7025 0x4106DC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7026 0x4106DC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7027 0x4106DCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7028 0x4106DD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7029 0x4106DD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7030 0x4106DD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7031 0x4106DDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7032 0x4106DE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7033 0x4106DE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7034 0x4106DE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7035 0x4106DEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7036 0x4106DF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7037 0x4106DF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7038 0x4106DF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7039 0x4106DFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7040 0x4106E00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7041 0x4106E04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7042 0x4106E08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7043 0x4106E0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7044 0x4106E10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7045 0x4106E14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7046 0x4106E18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7047 0x4106E1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7048 0x4106E20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7049 0x4106E24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7050 0x4106E28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7051 0x4106E2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7052 0x4106E30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7053 0x4106E34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7054 0x4106E38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7055 0x4106E3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7056 0x4106E40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7057 0x4106E44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7058 0x4106E48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7059 0x4106E4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7060 0x4106E50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7061 0x4106E54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7062 0x4106E58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7063 0x4106E5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7064 0x4106E60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7065 0x4106E64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7066 0x4106E68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7067 0x4106E6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7068 0x4106E70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7069 0x4106E74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7070 0x4106E78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7071 0x4106E7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7072 0x4106E80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7073 0x4106E84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7074 0x4106E88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7075 0x4106E8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7076 0x4106E90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7077 0x4106E94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7078 0x4106E98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7079 0x4106E9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7080 0x4106EA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7081 0x4106EA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7082 0x4106EA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7083 0x4106EAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7084 0x4106EB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7085 0x4106EB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7086 0x4106EB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7087 0x4106EBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7088 0x4106EC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7089 0x4106EC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7090 0x4106EC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7091 0x4106ECC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7092 0x4106ED0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7093 0x4106ED4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7094 0x4106ED8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7095 0x4106EDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7096 0x4106EE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7097 0x4106EE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7098 0x4106EE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7099 0x4106EEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7100 0x4106EF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7101 0x4106EF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7102 0x4106EF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7103 0x4106EFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7104 0x4106F00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7105 0x4106F04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7106 0x4106F08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7107 0x4106F0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7108 0x4106F10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7109 0x4106F14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7110 0x4106F18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7111 0x4106F1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7112 0x4106F20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7113 0x4106F24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7114 0x4106F28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7115 0x4106F2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7116 0x4106F30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7117 0x4106F34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7118 0x4106F38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7119 0x4106F3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7120 0x4106F40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7121 0x4106F44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7122 0x4106F48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7123 0x4106F4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7124 0x4106F50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7125 0x4106F54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7126 0x4106F58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7127 0x4106F5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7128 0x4106F60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7129 0x4106F64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7130 0x4106F68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7131 0x4106F6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7132 0x4106F70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7133 0x4106F74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7134 0x4106F78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7135 0x4106F7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7136 0x4106F80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7137 0x4106F84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7138 0x4106F88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7139 0x4106F8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7140 0x4106F90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7141 0x4106F94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7142 0x4106F98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7143 0x4106F9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7144 0x4106FA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7145 0x4106FA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7146 0x4106FA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7147 0x4106FAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7148 0x4106FB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7149 0x4106FB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7150 0x4106FB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7151 0x4106FBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7152 0x4106FC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7153 0x4106FC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7154 0x4106FC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7155 0x4106FCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7156 0x4106FD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7157 0x4106FD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7158 0x4106FD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7159 0x4106FDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7160 0x4106FE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7161 0x4106FE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7162 0x4106FE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7163 0x4106FEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7164 0x4106FF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7165 0x4106FF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7166 0x4106FF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7167 0x4106FFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7168 0x4107000
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7169 0x4107004
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7170 0x4107008
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7171 0x410700C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7172 0x4107010
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7173 0x4107014
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7174 0x4107018
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7175 0x410701C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7176 0x4107020
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7177 0x4107024
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7178 0x4107028
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7179 0x410702C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7180 0x4107030
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7181 0x4107034
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7182 0x4107038
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7183 0x410703C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7184 0x4107040
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7185 0x4107044
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7186 0x4107048
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7187 0x410704C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7188 0x4107050
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7189 0x4107054
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7190 0x4107058
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7191 0x410705C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7192 0x4107060
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7193 0x4107064
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7194 0x4107068
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7195 0x410706C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7196 0x4107070
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7197 0x4107074
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7198 0x4107078
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7199 0x410707C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7200 0x4107080
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7201 0x4107084
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7202 0x4107088
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7203 0x410708C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7204 0x4107090
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7205 0x4107094
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7206 0x4107098
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7207 0x410709C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7208 0x41070A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7209 0x41070A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7210 0x41070A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7211 0x41070AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7212 0x41070B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7213 0x41070B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7214 0x41070B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7215 0x41070BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7216 0x41070C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7217 0x41070C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7218 0x41070C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7219 0x41070CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7220 0x41070D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7221 0x41070D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7222 0x41070D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7223 0x41070DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7224 0x41070E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7225 0x41070E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7226 0x41070E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7227 0x41070EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7228 0x41070F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7229 0x41070F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7230 0x41070F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7231 0x41070FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7232 0x4107100
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7233 0x4107104
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7234 0x4107108
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7235 0x410710C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7236 0x4107110
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7237 0x4107114
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7238 0x4107118
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7239 0x410711C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7240 0x4107120
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7241 0x4107124
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7242 0x4107128
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7243 0x410712C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7244 0x4107130
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7245 0x4107134
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7246 0x4107138
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7247 0x410713C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7248 0x4107140
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7249 0x4107144
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7250 0x4107148
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7251 0x410714C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7252 0x4107150
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7253 0x4107154
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7254 0x4107158
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7255 0x410715C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7256 0x4107160
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7257 0x4107164
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7258 0x4107168
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7259 0x410716C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7260 0x4107170
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7261 0x4107174
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7262 0x4107178
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7263 0x410717C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7264 0x4107180
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7265 0x4107184
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7266 0x4107188
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7267 0x410718C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7268 0x4107190
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7269 0x4107194
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7270 0x4107198
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7271 0x410719C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7272 0x41071A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7273 0x41071A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7274 0x41071A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7275 0x41071AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7276 0x41071B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7277 0x41071B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7278 0x41071B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7279 0x41071BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7280 0x41071C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7281 0x41071C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7282 0x41071C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7283 0x41071CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7284 0x41071D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7285 0x41071D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7286 0x41071D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7287 0x41071DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7288 0x41071E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7289 0x41071E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7290 0x41071E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7291 0x41071EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7292 0x41071F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7293 0x41071F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7294 0x41071F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7295 0x41071FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7296 0x4107200
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7297 0x4107204
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7298 0x4107208
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7299 0x410720C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7300 0x4107210
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7301 0x4107214
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7302 0x4107218
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7303 0x410721C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7304 0x4107220
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7305 0x4107224
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7306 0x4107228
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7307 0x410722C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7308 0x4107230
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7309 0x4107234
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7310 0x4107238
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7311 0x410723C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7312 0x4107240
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7313 0x4107244
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7314 0x4107248
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7315 0x410724C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7316 0x4107250
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7317 0x4107254
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7318 0x4107258
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7319 0x410725C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7320 0x4107260
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7321 0x4107264
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7322 0x4107268
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7323 0x410726C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7324 0x4107270
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7325 0x4107274
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7326 0x4107278
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7327 0x410727C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7328 0x4107280
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7329 0x4107284
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7330 0x4107288
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7331 0x410728C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7332 0x4107290
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7333 0x4107294
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7334 0x4107298
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7335 0x410729C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7336 0x41072A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7337 0x41072A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7338 0x41072A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7339 0x41072AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7340 0x41072B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7341 0x41072B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7342 0x41072B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7343 0x41072BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7344 0x41072C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7345 0x41072C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7346 0x41072C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7347 0x41072CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7348 0x41072D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7349 0x41072D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7350 0x41072D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7351 0x41072DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7352 0x41072E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7353 0x41072E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7354 0x41072E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7355 0x41072EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7356 0x41072F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7357 0x41072F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7358 0x41072F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7359 0x41072FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7360 0x4107300
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7361 0x4107304
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7362 0x4107308
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7363 0x410730C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7364 0x4107310
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7365 0x4107314
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7366 0x4107318
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7367 0x410731C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7368 0x4107320
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7369 0x4107324
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7370 0x4107328
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7371 0x410732C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7372 0x4107330
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7373 0x4107334
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7374 0x4107338
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7375 0x410733C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7376 0x4107340
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7377 0x4107344
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7378 0x4107348
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7379 0x410734C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7380 0x4107350
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7381 0x4107354
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7382 0x4107358
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7383 0x410735C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7384 0x4107360
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7385 0x4107364
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7386 0x4107368
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7387 0x410736C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7388 0x4107370
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7389 0x4107374
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7390 0x4107378
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7391 0x410737C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7392 0x4107380
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7393 0x4107384
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7394 0x4107388
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7395 0x410738C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7396 0x4107390
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7397 0x4107394
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7398 0x4107398
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7399 0x410739C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7400 0x41073A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7401 0x41073A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7402 0x41073A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7403 0x41073AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7404 0x41073B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7405 0x41073B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7406 0x41073B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7407 0x41073BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7408 0x41073C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7409 0x41073C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7410 0x41073C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7411 0x41073CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7412 0x41073D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7413 0x41073D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7414 0x41073D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7415 0x41073DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7416 0x41073E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7417 0x41073E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7418 0x41073E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7419 0x41073EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7420 0x41073F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7421 0x41073F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7422 0x41073F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7423 0x41073FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7424 0x4107400
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7425 0x4107404
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7426 0x4107408
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7427 0x410740C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7428 0x4107410
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7429 0x4107414
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7430 0x4107418
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7431 0x410741C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7432 0x4107420
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7433 0x4107424
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7434 0x4107428
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7435 0x410742C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7436 0x4107430
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7437 0x4107434
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7438 0x4107438
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7439 0x410743C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7440 0x4107440
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7441 0x4107444
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7442 0x4107448
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7443 0x410744C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7444 0x4107450
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7445 0x4107454
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7446 0x4107458
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7447 0x410745C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7448 0x4107460
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7449 0x4107464
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7450 0x4107468
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7451 0x410746C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7452 0x4107470
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7453 0x4107474
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7454 0x4107478
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7455 0x410747C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7456 0x4107480
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7457 0x4107484
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7458 0x4107488
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7459 0x410748C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7460 0x4107490
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7461 0x4107494
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7462 0x4107498
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7463 0x410749C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7464 0x41074A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7465 0x41074A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7466 0x41074A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7467 0x41074AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7468 0x41074B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7469 0x41074B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7470 0x41074B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7471 0x41074BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7472 0x41074C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7473 0x41074C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7474 0x41074C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7475 0x41074CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7476 0x41074D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7477 0x41074D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7478 0x41074D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7479 0x41074DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7480 0x41074E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7481 0x41074E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7482 0x41074E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7483 0x41074EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7484 0x41074F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7485 0x41074F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7486 0x41074F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7487 0x41074FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7488 0x4107500
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7489 0x4107504
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7490 0x4107508
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7491 0x410750C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7492 0x4107510
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7493 0x4107514
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7494 0x4107518
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7495 0x410751C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7496 0x4107520
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7497 0x4107524
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7498 0x4107528
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7499 0x410752C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7500 0x4107530
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7501 0x4107534
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7502 0x4107538
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7503 0x410753C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7504 0x4107540
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7505 0x4107544
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7506 0x4107548
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7507 0x410754C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7508 0x4107550
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7509 0x4107554
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7510 0x4107558
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7511 0x410755C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7512 0x4107560
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7513 0x4107564
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7514 0x4107568
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7515 0x410756C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7516 0x4107570
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7517 0x4107574
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7518 0x4107578
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7519 0x410757C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7520 0x4107580
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7521 0x4107584
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7522 0x4107588
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7523 0x410758C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7524 0x4107590
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7525 0x4107594
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7526 0x4107598
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7527 0x410759C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7528 0x41075A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7529 0x41075A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7530 0x41075A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7531 0x41075AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7532 0x41075B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7533 0x41075B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7534 0x41075B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7535 0x41075BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7536 0x41075C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7537 0x41075C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7538 0x41075C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7539 0x41075CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7540 0x41075D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7541 0x41075D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7542 0x41075D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7543 0x41075DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7544 0x41075E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7545 0x41075E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7546 0x41075E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7547 0x41075EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7548 0x41075F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7549 0x41075F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7550 0x41075F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7551 0x41075FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7552 0x4107600
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7553 0x4107604
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7554 0x4107608
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7555 0x410760C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7556 0x4107610
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7557 0x4107614
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7558 0x4107618
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7559 0x410761C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7560 0x4107620
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7561 0x4107624
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7562 0x4107628
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7563 0x410762C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7564 0x4107630
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7565 0x4107634
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7566 0x4107638
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7567 0x410763C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7568 0x4107640
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7569 0x4107644
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7570 0x4107648
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7571 0x410764C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7572 0x4107650
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7573 0x4107654
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7574 0x4107658
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7575 0x410765C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7576 0x4107660
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7577 0x4107664
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7578 0x4107668
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7579 0x410766C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7580 0x4107670
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7581 0x4107674
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7582 0x4107678
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7583 0x410767C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7584 0x4107680
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7585 0x4107684
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7586 0x4107688
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7587 0x410768C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7588 0x4107690
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7589 0x4107694
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7590 0x4107698
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7591 0x410769C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7592 0x41076A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7593 0x41076A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7594 0x41076A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7595 0x41076AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7596 0x41076B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7597 0x41076B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7598 0x41076B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7599 0x41076BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7600 0x41076C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7601 0x41076C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7602 0x41076C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7603 0x41076CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7604 0x41076D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7605 0x41076D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7606 0x41076D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7607 0x41076DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7608 0x41076E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7609 0x41076E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7610 0x41076E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7611 0x41076EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7612 0x41076F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7613 0x41076F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7614 0x41076F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7615 0x41076FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7616 0x4107700
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7617 0x4107704
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7618 0x4107708
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7619 0x410770C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7620 0x4107710
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7621 0x4107714
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7622 0x4107718
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7623 0x410771C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7624 0x4107720
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7625 0x4107724
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7626 0x4107728
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7627 0x410772C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7628 0x4107730
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7629 0x4107734
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7630 0x4107738
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7631 0x410773C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7632 0x4107740
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7633 0x4107744
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7634 0x4107748
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7635 0x410774C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7636 0x4107750
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7637 0x4107754
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7638 0x4107758
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7639 0x410775C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7640 0x4107760
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7641 0x4107764
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7642 0x4107768
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7643 0x410776C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7644 0x4107770
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7645 0x4107774
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7646 0x4107778
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7647 0x410777C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7648 0x4107780
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7649 0x4107784
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7650 0x4107788
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7651 0x410778C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7652 0x4107790
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7653 0x4107794
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7654 0x4107798
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7655 0x410779C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7656 0x41077A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7657 0x41077A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7658 0x41077A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7659 0x41077AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7660 0x41077B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7661 0x41077B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7662 0x41077B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7663 0x41077BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7664 0x41077C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7665 0x41077C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7666 0x41077C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7667 0x41077CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7668 0x41077D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7669 0x41077D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7670 0x41077D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7671 0x41077DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7672 0x41077E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7673 0x41077E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7674 0x41077E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7675 0x41077EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7676 0x41077F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7677 0x41077F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7678 0x41077F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7679 0x41077FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7680 0x4107800
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7681 0x4107804
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7682 0x4107808
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7683 0x410780C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7684 0x4107810
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7685 0x4107814
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7686 0x4107818
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7687 0x410781C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7688 0x4107820
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7689 0x4107824
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7690 0x4107828
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7691 0x410782C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7692 0x4107830
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7693 0x4107834
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7694 0x4107838
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7695 0x410783C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7696 0x4107840
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7697 0x4107844
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7698 0x4107848
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7699 0x410784C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7700 0x4107850
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7701 0x4107854
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7702 0x4107858
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7703 0x410785C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7704 0x4107860
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7705 0x4107864
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7706 0x4107868
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7707 0x410786C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7708 0x4107870
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7709 0x4107874
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7710 0x4107878
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7711 0x410787C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7712 0x4107880
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7713 0x4107884
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7714 0x4107888
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7715 0x410788C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7716 0x4107890
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7717 0x4107894
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7718 0x4107898
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7719 0x410789C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7720 0x41078A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7721 0x41078A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7722 0x41078A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7723 0x41078AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7724 0x41078B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7725 0x41078B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7726 0x41078B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7727 0x41078BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7728 0x41078C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7729 0x41078C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7730 0x41078C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7731 0x41078CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7732 0x41078D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7733 0x41078D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7734 0x41078D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7735 0x41078DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7736 0x41078E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7737 0x41078E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7738 0x41078E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7739 0x41078EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7740 0x41078F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7741 0x41078F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7742 0x41078F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7743 0x41078FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7744 0x4107900
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7745 0x4107904
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7746 0x4107908
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7747 0x410790C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7748 0x4107910
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7749 0x4107914
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7750 0x4107918
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7751 0x410791C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7752 0x4107920
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7753 0x4107924
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7754 0x4107928
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7755 0x410792C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7756 0x4107930
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7757 0x4107934
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7758 0x4107938
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7759 0x410793C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7760 0x4107940
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7761 0x4107944
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7762 0x4107948
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7763 0x410794C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7764 0x4107950
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7765 0x4107954
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7766 0x4107958
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7767 0x410795C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7768 0x4107960
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7769 0x4107964
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7770 0x4107968
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7771 0x410796C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7772 0x4107970
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7773 0x4107974
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7774 0x4107978
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7775 0x410797C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7776 0x4107980
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7777 0x4107984
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7778 0x4107988
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7779 0x410798C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7780 0x4107990
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7781 0x4107994
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7782 0x4107998
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7783 0x410799C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7784 0x41079A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7785 0x41079A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7786 0x41079A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7787 0x41079AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7788 0x41079B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7789 0x41079B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7790 0x41079B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7791 0x41079BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7792 0x41079C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7793 0x41079C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7794 0x41079C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7795 0x41079CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7796 0x41079D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7797 0x41079D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7798 0x41079D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7799 0x41079DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7800 0x41079E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7801 0x41079E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7802 0x41079E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7803 0x41079EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7804 0x41079F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7805 0x41079F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7806 0x41079F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7807 0x41079FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7808 0x4107A00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7809 0x4107A04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7810 0x4107A08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7811 0x4107A0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7812 0x4107A10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7813 0x4107A14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7814 0x4107A18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7815 0x4107A1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7816 0x4107A20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7817 0x4107A24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7818 0x4107A28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7819 0x4107A2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7820 0x4107A30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7821 0x4107A34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7822 0x4107A38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7823 0x4107A3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7824 0x4107A40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7825 0x4107A44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7826 0x4107A48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7827 0x4107A4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7828 0x4107A50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7829 0x4107A54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7830 0x4107A58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7831 0x4107A5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7832 0x4107A60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7833 0x4107A64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7834 0x4107A68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7835 0x4107A6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7836 0x4107A70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7837 0x4107A74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7838 0x4107A78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7839 0x4107A7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7840 0x4107A80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7841 0x4107A84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7842 0x4107A88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7843 0x4107A8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7844 0x4107A90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7845 0x4107A94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7846 0x4107A98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7847 0x4107A9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7848 0x4107AA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7849 0x4107AA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7850 0x4107AA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7851 0x4107AAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7852 0x4107AB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7853 0x4107AB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7854 0x4107AB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7855 0x4107ABC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7856 0x4107AC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7857 0x4107AC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7858 0x4107AC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7859 0x4107ACC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7860 0x4107AD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7861 0x4107AD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7862 0x4107AD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7863 0x4107ADC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7864 0x4107AE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7865 0x4107AE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7866 0x4107AE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7867 0x4107AEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7868 0x4107AF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7869 0x4107AF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7870 0x4107AF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7871 0x4107AFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7872 0x4107B00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7873 0x4107B04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7874 0x4107B08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7875 0x4107B0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7876 0x4107B10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7877 0x4107B14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7878 0x4107B18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7879 0x4107B1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7880 0x4107B20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7881 0x4107B24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7882 0x4107B28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7883 0x4107B2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7884 0x4107B30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7885 0x4107B34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7886 0x4107B38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7887 0x4107B3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7888 0x4107B40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7889 0x4107B44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7890 0x4107B48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7891 0x4107B4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7892 0x4107B50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7893 0x4107B54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7894 0x4107B58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7895 0x4107B5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7896 0x4107B60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7897 0x4107B64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7898 0x4107B68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7899 0x4107B6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7900 0x4107B70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7901 0x4107B74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7902 0x4107B78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7903 0x4107B7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7904 0x4107B80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7905 0x4107B84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7906 0x4107B88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7907 0x4107B8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7908 0x4107B90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7909 0x4107B94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7910 0x4107B98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7911 0x4107B9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7912 0x4107BA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7913 0x4107BA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7914 0x4107BA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7915 0x4107BAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7916 0x4107BB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7917 0x4107BB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7918 0x4107BB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7919 0x4107BBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7920 0x4107BC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7921 0x4107BC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7922 0x4107BC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7923 0x4107BCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7924 0x4107BD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7925 0x4107BD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7926 0x4107BD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7927 0x4107BDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7928 0x4107BE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7929 0x4107BE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7930 0x4107BE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7931 0x4107BEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7932 0x4107BF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7933 0x4107BF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7934 0x4107BF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7935 0x4107BFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7936 0x4107C00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7937 0x4107C04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7938 0x4107C08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7939 0x4107C0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7940 0x4107C10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7941 0x4107C14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7942 0x4107C18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7943 0x4107C1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7944 0x4107C20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7945 0x4107C24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7946 0x4107C28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7947 0x4107C2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7948 0x4107C30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7949 0x4107C34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7950 0x4107C38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7951 0x4107C3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7952 0x4107C40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7953 0x4107C44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7954 0x4107C48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7955 0x4107C4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7956 0x4107C50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7957 0x4107C54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7958 0x4107C58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7959 0x4107C5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7960 0x4107C60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7961 0x4107C64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7962 0x4107C68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7963 0x4107C6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7964 0x4107C70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7965 0x4107C74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7966 0x4107C78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7967 0x4107C7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7968 0x4107C80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7969 0x4107C84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7970 0x4107C88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7971 0x4107C8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7972 0x4107C90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7973 0x4107C94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7974 0x4107C98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7975 0x4107C9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7976 0x4107CA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7977 0x4107CA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7978 0x4107CA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7979 0x4107CAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7980 0x4107CB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7981 0x4107CB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7982 0x4107CB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7983 0x4107CBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7984 0x4107CC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7985 0x4107CC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7986 0x4107CC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7987 0x4107CCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7988 0x4107CD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7989 0x4107CD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7990 0x4107CD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7991 0x4107CDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7992 0x4107CE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7993 0x4107CE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7994 0x4107CE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7995 0x4107CEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7996 0x4107CF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7997 0x4107CF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7998 0x4107CF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_7999 0x4107CFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8000 0x4107D00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8001 0x4107D04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8002 0x4107D08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8003 0x4107D0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8004 0x4107D10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8005 0x4107D14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8006 0x4107D18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8007 0x4107D1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8008 0x4107D20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8009 0x4107D24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8010 0x4107D28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8011 0x4107D2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8012 0x4107D30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8013 0x4107D34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8014 0x4107D38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8015 0x4107D3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8016 0x4107D40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8017 0x4107D44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8018 0x4107D48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8019 0x4107D4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8020 0x4107D50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8021 0x4107D54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8022 0x4107D58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8023 0x4107D5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8024 0x4107D60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8025 0x4107D64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8026 0x4107D68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8027 0x4107D6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8028 0x4107D70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8029 0x4107D74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8030 0x4107D78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8031 0x4107D7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8032 0x4107D80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8033 0x4107D84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8034 0x4107D88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8035 0x4107D8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8036 0x4107D90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8037 0x4107D94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8038 0x4107D98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8039 0x4107D9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8040 0x4107DA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8041 0x4107DA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8042 0x4107DA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8043 0x4107DAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8044 0x4107DB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8045 0x4107DB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8046 0x4107DB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8047 0x4107DBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8048 0x4107DC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8049 0x4107DC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8050 0x4107DC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8051 0x4107DCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8052 0x4107DD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8053 0x4107DD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8054 0x4107DD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8055 0x4107DDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8056 0x4107DE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8057 0x4107DE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8058 0x4107DE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8059 0x4107DEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8060 0x4107DF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8061 0x4107DF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8062 0x4107DF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8063 0x4107DFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8064 0x4107E00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8065 0x4107E04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8066 0x4107E08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8067 0x4107E0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8068 0x4107E10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8069 0x4107E14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8070 0x4107E18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8071 0x4107E1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8072 0x4107E20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8073 0x4107E24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8074 0x4107E28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8075 0x4107E2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8076 0x4107E30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8077 0x4107E34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8078 0x4107E38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8079 0x4107E3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8080 0x4107E40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8081 0x4107E44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8082 0x4107E48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8083 0x4107E4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8084 0x4107E50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8085 0x4107E54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8086 0x4107E58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8087 0x4107E5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8088 0x4107E60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8089 0x4107E64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8090 0x4107E68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8091 0x4107E6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8092 0x4107E70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8093 0x4107E74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8094 0x4107E78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8095 0x4107E7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8096 0x4107E80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8097 0x4107E84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8098 0x4107E88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8099 0x4107E8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8100 0x4107E90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8101 0x4107E94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8102 0x4107E98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8103 0x4107E9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8104 0x4107EA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8105 0x4107EA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8106 0x4107EA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8107 0x4107EAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8108 0x4107EB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8109 0x4107EB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8110 0x4107EB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8111 0x4107EBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8112 0x4107EC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8113 0x4107EC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8114 0x4107EC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8115 0x4107ECC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8116 0x4107ED0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8117 0x4107ED4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8118 0x4107ED8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8119 0x4107EDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8120 0x4107EE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8121 0x4107EE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8122 0x4107EE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8123 0x4107EEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8124 0x4107EF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8125 0x4107EF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8126 0x4107EF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8127 0x4107EFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8128 0x4107F00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8129 0x4107F04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8130 0x4107F08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8131 0x4107F0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8132 0x4107F10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8133 0x4107F14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8134 0x4107F18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8135 0x4107F1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8136 0x4107F20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8137 0x4107F24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8138 0x4107F28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8139 0x4107F2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8140 0x4107F30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8141 0x4107F34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8142 0x4107F38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8143 0x4107F3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8144 0x4107F40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8145 0x4107F44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8146 0x4107F48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8147 0x4107F4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8148 0x4107F50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8149 0x4107F54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8150 0x4107F58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8151 0x4107F5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8152 0x4107F60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8153 0x4107F64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8154 0x4107F68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8155 0x4107F6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8156 0x4107F70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8157 0x4107F74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8158 0x4107F78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8159 0x4107F7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8160 0x4107F80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8161 0x4107F84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8162 0x4107F88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8163 0x4107F8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8164 0x4107F90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8165 0x4107F94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8166 0x4107F98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8167 0x4107F9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8168 0x4107FA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8169 0x4107FA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8170 0x4107FA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8171 0x4107FAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8172 0x4107FB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8173 0x4107FB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8174 0x4107FB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8175 0x4107FBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8176 0x4107FC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8177 0x4107FC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8178 0x4107FC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8179 0x4107FCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8180 0x4107FD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8181 0x4107FD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8182 0x4107FD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8183 0x4107FDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8184 0x4107FE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8185 0x4107FE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8186 0x4107FE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8187 0x4107FEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8188 0x4107FF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8189 0x4107FF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8190 0x4107FF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8191 0x4107FFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 0x4108000
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1 0x4108004
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2 0x4108008
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_3 0x410800C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_4 0x4108010
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_5 0x4108014
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_6 0x4108018
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_7 0x410801C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_8 0x4108020
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_9 0x4108024
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_10 0x4108028
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_11 0x410802C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_12 0x4108030
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_13 0x4108034
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_14 0x4108038
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_15 0x410803C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_16 0x4108040
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_17 0x4108044
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_18 0x4108048
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_19 0x410804C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_20 0x4108050
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_21 0x4108054
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_22 0x4108058
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_23 0x410805C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_24 0x4108060
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_25 0x4108064
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_26 0x4108068
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_27 0x410806C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_28 0x4108070
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_29 0x4108074
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_30 0x4108078
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_31 0x410807C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_32 0x4108080
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_33 0x4108084
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_34 0x4108088
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_35 0x410808C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_36 0x4108090
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_37 0x4108094
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_38 0x4108098
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_39 0x410809C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_40 0x41080A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_41 0x41080A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_42 0x41080A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_43 0x41080AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_44 0x41080B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_45 0x41080B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_46 0x41080B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_47 0x41080BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_48 0x41080C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_49 0x41080C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_50 0x41080C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_51 0x41080CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_52 0x41080D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_53 0x41080D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_54 0x41080D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_55 0x41080DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_56 0x41080E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_57 0x41080E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_58 0x41080E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_59 0x41080EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_60 0x41080F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_61 0x41080F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_62 0x41080F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_63 0x41080FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_64 0x4108100
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_65 0x4108104
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_66 0x4108108
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_67 0x410810C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_68 0x4108110
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_69 0x4108114
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_70 0x4108118
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_71 0x410811C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_72 0x4108120
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_73 0x4108124
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_74 0x4108128
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_75 0x410812C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_76 0x4108130
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_77 0x4108134
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_78 0x4108138
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_79 0x410813C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_80 0x4108140
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_81 0x4108144
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_82 0x4108148
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_83 0x410814C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_84 0x4108150
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_85 0x4108154
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_86 0x4108158
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_87 0x410815C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_88 0x4108160
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_89 0x4108164
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_90 0x4108168
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_91 0x410816C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_92 0x4108170
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_93 0x4108174
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_94 0x4108178
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_95 0x410817C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_96 0x4108180
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_97 0x4108184
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_98 0x4108188
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_99 0x410818C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_100 0x4108190
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_101 0x4108194
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_102 0x4108198
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_103 0x410819C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_104 0x41081A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_105 0x41081A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_106 0x41081A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_107 0x41081AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_108 0x41081B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_109 0x41081B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_110 0x41081B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_111 0x41081BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_112 0x41081C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_113 0x41081C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_114 0x41081C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_115 0x41081CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_116 0x41081D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_117 0x41081D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_118 0x41081D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_119 0x41081DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_120 0x41081E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_121 0x41081E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_122 0x41081E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_123 0x41081EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_124 0x41081F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_125 0x41081F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_126 0x41081F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_127 0x41081FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_128 0x4108200
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_129 0x4108204
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_130 0x4108208
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_131 0x410820C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_132 0x4108210
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_133 0x4108214
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_134 0x4108218
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_135 0x410821C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_136 0x4108220
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_137 0x4108224
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_138 0x4108228
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_139 0x410822C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_140 0x4108230
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_141 0x4108234
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_142 0x4108238
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_143 0x410823C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_144 0x4108240
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_145 0x4108244
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_146 0x4108248
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_147 0x410824C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_148 0x4108250
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_149 0x4108254
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_150 0x4108258
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_151 0x410825C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_152 0x4108260
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_153 0x4108264
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_154 0x4108268
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_155 0x410826C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_156 0x4108270
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_157 0x4108274
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_158 0x4108278
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_159 0x410827C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_160 0x4108280
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_161 0x4108284
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_162 0x4108288
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_163 0x410828C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_164 0x4108290
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_165 0x4108294
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_166 0x4108298
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_167 0x410829C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_168 0x41082A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_169 0x41082A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_170 0x41082A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_171 0x41082AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_172 0x41082B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_173 0x41082B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_174 0x41082B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_175 0x41082BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_176 0x41082C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_177 0x41082C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_178 0x41082C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_179 0x41082CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_180 0x41082D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_181 0x41082D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_182 0x41082D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_183 0x41082DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_184 0x41082E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_185 0x41082E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_186 0x41082E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_187 0x41082EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_188 0x41082F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_189 0x41082F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_190 0x41082F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_191 0x41082FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_192 0x4108300
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_193 0x4108304
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_194 0x4108308
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_195 0x410830C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_196 0x4108310
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_197 0x4108314
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_198 0x4108318
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_199 0x410831C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_200 0x4108320
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_201 0x4108324
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_202 0x4108328
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_203 0x410832C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_204 0x4108330
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_205 0x4108334
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_206 0x4108338
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_207 0x410833C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_208 0x4108340
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_209 0x4108344
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_210 0x4108348
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_211 0x410834C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_212 0x4108350
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_213 0x4108354
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_214 0x4108358
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_215 0x410835C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_216 0x4108360
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_217 0x4108364
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_218 0x4108368
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_219 0x410836C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_220 0x4108370
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_221 0x4108374
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_222 0x4108378
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_223 0x410837C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_224 0x4108380
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_225 0x4108384
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_226 0x4108388
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_227 0x410838C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_228 0x4108390
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_229 0x4108394
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_230 0x4108398
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_231 0x410839C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_232 0x41083A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_233 0x41083A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_234 0x41083A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_235 0x41083AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_236 0x41083B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_237 0x41083B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_238 0x41083B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_239 0x41083BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_240 0x41083C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_241 0x41083C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_242 0x41083C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_243 0x41083CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_244 0x41083D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_245 0x41083D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_246 0x41083D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_247 0x41083DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_248 0x41083E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_249 0x41083E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_250 0x41083E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_251 0x41083EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_252 0x41083F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_253 0x41083F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_254 0x41083F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_255 0x41083FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_256 0x4108400
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_257 0x4108404
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_258 0x4108408
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_259 0x410840C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_260 0x4108410
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_261 0x4108414
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_262 0x4108418
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_263 0x410841C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_264 0x4108420
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_265 0x4108424
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_266 0x4108428
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_267 0x410842C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_268 0x4108430
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_269 0x4108434
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_270 0x4108438
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_271 0x410843C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_272 0x4108440
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_273 0x4108444
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_274 0x4108448
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_275 0x410844C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_276 0x4108450
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_277 0x4108454
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_278 0x4108458
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_279 0x410845C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_280 0x4108460
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_281 0x4108464
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_282 0x4108468
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_283 0x410846C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_284 0x4108470
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_285 0x4108474
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_286 0x4108478
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_287 0x410847C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_288 0x4108480
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_289 0x4108484
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_290 0x4108488
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_291 0x410848C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_292 0x4108490
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_293 0x4108494
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_294 0x4108498
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_295 0x410849C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_296 0x41084A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_297 0x41084A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_298 0x41084A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_299 0x41084AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_300 0x41084B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_301 0x41084B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_302 0x41084B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_303 0x41084BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_304 0x41084C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_305 0x41084C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_306 0x41084C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_307 0x41084CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_308 0x41084D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_309 0x41084D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_310 0x41084D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_311 0x41084DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_312 0x41084E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_313 0x41084E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_314 0x41084E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_315 0x41084EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_316 0x41084F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_317 0x41084F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_318 0x41084F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_319 0x41084FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_320 0x4108500
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_321 0x4108504
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_322 0x4108508
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_323 0x410850C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_324 0x4108510
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_325 0x4108514
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_326 0x4108518
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_327 0x410851C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_328 0x4108520
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_329 0x4108524
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_330 0x4108528
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_331 0x410852C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_332 0x4108530
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_333 0x4108534
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_334 0x4108538
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_335 0x410853C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_336 0x4108540
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_337 0x4108544
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_338 0x4108548
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_339 0x410854C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_340 0x4108550
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_341 0x4108554
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_342 0x4108558
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_343 0x410855C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_344 0x4108560
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_345 0x4108564
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_346 0x4108568
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_347 0x410856C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_348 0x4108570
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_349 0x4108574
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_350 0x4108578
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_351 0x410857C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_352 0x4108580
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_353 0x4108584
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_354 0x4108588
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_355 0x410858C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_356 0x4108590
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_357 0x4108594
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_358 0x4108598
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_359 0x410859C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_360 0x41085A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_361 0x41085A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_362 0x41085A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_363 0x41085AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_364 0x41085B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_365 0x41085B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_366 0x41085B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_367 0x41085BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_368 0x41085C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_369 0x41085C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_370 0x41085C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_371 0x41085CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_372 0x41085D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_373 0x41085D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_374 0x41085D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_375 0x41085DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_376 0x41085E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_377 0x41085E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_378 0x41085E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_379 0x41085EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_380 0x41085F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_381 0x41085F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_382 0x41085F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_383 0x41085FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_384 0x4108600
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_385 0x4108604
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_386 0x4108608
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_387 0x410860C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_388 0x4108610
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_389 0x4108614
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_390 0x4108618
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_391 0x410861C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_392 0x4108620
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_393 0x4108624
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_394 0x4108628
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_395 0x410862C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_396 0x4108630
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_397 0x4108634
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_398 0x4108638
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_399 0x410863C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_400 0x4108640
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_401 0x4108644
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_402 0x4108648
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_403 0x410864C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_404 0x4108650
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_405 0x4108654
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_406 0x4108658
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_407 0x410865C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_408 0x4108660
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_409 0x4108664
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_410 0x4108668
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_411 0x410866C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_412 0x4108670
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_413 0x4108674
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_414 0x4108678
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_415 0x410867C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_416 0x4108680
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_417 0x4108684
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_418 0x4108688
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_419 0x410868C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_420 0x4108690
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_421 0x4108694
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_422 0x4108698
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_423 0x410869C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_424 0x41086A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_425 0x41086A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_426 0x41086A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_427 0x41086AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_428 0x41086B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_429 0x41086B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_430 0x41086B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_431 0x41086BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_432 0x41086C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_433 0x41086C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_434 0x41086C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_435 0x41086CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_436 0x41086D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_437 0x41086D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_438 0x41086D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_439 0x41086DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_440 0x41086E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_441 0x41086E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_442 0x41086E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_443 0x41086EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_444 0x41086F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_445 0x41086F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_446 0x41086F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_447 0x41086FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_448 0x4108700
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_449 0x4108704
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_450 0x4108708
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_451 0x410870C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_452 0x4108710
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_453 0x4108714
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_454 0x4108718
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_455 0x410871C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_456 0x4108720
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_457 0x4108724
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_458 0x4108728
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_459 0x410872C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_460 0x4108730
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_461 0x4108734
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_462 0x4108738
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_463 0x410873C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_464 0x4108740
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_465 0x4108744
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_466 0x4108748
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_467 0x410874C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_468 0x4108750
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_469 0x4108754
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_470 0x4108758
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_471 0x410875C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_472 0x4108760
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_473 0x4108764
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_474 0x4108768
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_475 0x410876C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_476 0x4108770
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_477 0x4108774
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_478 0x4108778
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_479 0x410877C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_480 0x4108780
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_481 0x4108784
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_482 0x4108788
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_483 0x410878C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_484 0x4108790
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_485 0x4108794
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_486 0x4108798
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_487 0x410879C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_488 0x41087A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_489 0x41087A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_490 0x41087A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_491 0x41087AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_492 0x41087B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_493 0x41087B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_494 0x41087B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_495 0x41087BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_496 0x41087C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_497 0x41087C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_498 0x41087C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_499 0x41087CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_500 0x41087D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_501 0x41087D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_502 0x41087D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_503 0x41087DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_504 0x41087E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_505 0x41087E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_506 0x41087E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_507 0x41087EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_508 0x41087F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_509 0x41087F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_510 0x41087F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_511 0x41087FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_512 0x4108800
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_513 0x4108804
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_514 0x4108808
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_515 0x410880C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_516 0x4108810
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_517 0x4108814
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_518 0x4108818
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_519 0x410881C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_520 0x4108820
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_521 0x4108824
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_522 0x4108828
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_523 0x410882C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_524 0x4108830
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_525 0x4108834
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_526 0x4108838
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_527 0x410883C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_528 0x4108840
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_529 0x4108844
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_530 0x4108848
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_531 0x410884C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_532 0x4108850
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_533 0x4108854
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_534 0x4108858
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_535 0x410885C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_536 0x4108860
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_537 0x4108864
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_538 0x4108868
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_539 0x410886C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_540 0x4108870
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_541 0x4108874
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_542 0x4108878
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_543 0x410887C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_544 0x4108880
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_545 0x4108884
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_546 0x4108888
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_547 0x410888C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_548 0x4108890
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_549 0x4108894
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_550 0x4108898
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_551 0x410889C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_552 0x41088A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_553 0x41088A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_554 0x41088A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_555 0x41088AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_556 0x41088B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_557 0x41088B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_558 0x41088B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_559 0x41088BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_560 0x41088C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_561 0x41088C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_562 0x41088C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_563 0x41088CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_564 0x41088D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_565 0x41088D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_566 0x41088D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_567 0x41088DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_568 0x41088E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_569 0x41088E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_570 0x41088E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_571 0x41088EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_572 0x41088F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_573 0x41088F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_574 0x41088F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_575 0x41088FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_576 0x4108900
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_577 0x4108904
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_578 0x4108908
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_579 0x410890C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_580 0x4108910
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_581 0x4108914
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_582 0x4108918
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_583 0x410891C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_584 0x4108920
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_585 0x4108924
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_586 0x4108928
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_587 0x410892C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_588 0x4108930
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_589 0x4108934
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_590 0x4108938
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_591 0x410893C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_592 0x4108940
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_593 0x4108944
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_594 0x4108948
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_595 0x410894C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_596 0x4108950
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_597 0x4108954
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_598 0x4108958
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_599 0x410895C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_600 0x4108960
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_601 0x4108964
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_602 0x4108968
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_603 0x410896C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_604 0x4108970
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_605 0x4108974
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_606 0x4108978
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_607 0x410897C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_608 0x4108980
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_609 0x4108984
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_610 0x4108988
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_611 0x410898C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_612 0x4108990
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_613 0x4108994
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_614 0x4108998
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_615 0x410899C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_616 0x41089A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_617 0x41089A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_618 0x41089A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_619 0x41089AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_620 0x41089B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_621 0x41089B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_622 0x41089B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_623 0x41089BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_624 0x41089C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_625 0x41089C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_626 0x41089C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_627 0x41089CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_628 0x41089D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_629 0x41089D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_630 0x41089D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_631 0x41089DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_632 0x41089E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_633 0x41089E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_634 0x41089E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_635 0x41089EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_636 0x41089F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_637 0x41089F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_638 0x41089F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_639 0x41089FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_640 0x4108A00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_641 0x4108A04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_642 0x4108A08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_643 0x4108A0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_644 0x4108A10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_645 0x4108A14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_646 0x4108A18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_647 0x4108A1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_648 0x4108A20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_649 0x4108A24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_650 0x4108A28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_651 0x4108A2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_652 0x4108A30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_653 0x4108A34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_654 0x4108A38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_655 0x4108A3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_656 0x4108A40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_657 0x4108A44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_658 0x4108A48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_659 0x4108A4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_660 0x4108A50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_661 0x4108A54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_662 0x4108A58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_663 0x4108A5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_664 0x4108A60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_665 0x4108A64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_666 0x4108A68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_667 0x4108A6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_668 0x4108A70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_669 0x4108A74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_670 0x4108A78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_671 0x4108A7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_672 0x4108A80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_673 0x4108A84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_674 0x4108A88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_675 0x4108A8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_676 0x4108A90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_677 0x4108A94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_678 0x4108A98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_679 0x4108A9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_680 0x4108AA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_681 0x4108AA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_682 0x4108AA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_683 0x4108AAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_684 0x4108AB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_685 0x4108AB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_686 0x4108AB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_687 0x4108ABC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_688 0x4108AC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_689 0x4108AC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_690 0x4108AC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_691 0x4108ACC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_692 0x4108AD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_693 0x4108AD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_694 0x4108AD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_695 0x4108ADC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_696 0x4108AE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_697 0x4108AE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_698 0x4108AE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_699 0x4108AEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_700 0x4108AF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_701 0x4108AF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_702 0x4108AF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_703 0x4108AFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_704 0x4108B00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_705 0x4108B04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_706 0x4108B08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_707 0x4108B0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_708 0x4108B10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_709 0x4108B14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_710 0x4108B18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_711 0x4108B1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_712 0x4108B20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_713 0x4108B24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_714 0x4108B28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_715 0x4108B2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_716 0x4108B30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_717 0x4108B34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_718 0x4108B38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_719 0x4108B3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_720 0x4108B40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_721 0x4108B44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_722 0x4108B48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_723 0x4108B4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_724 0x4108B50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_725 0x4108B54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_726 0x4108B58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_727 0x4108B5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_728 0x4108B60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_729 0x4108B64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_730 0x4108B68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_731 0x4108B6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_732 0x4108B70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_733 0x4108B74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_734 0x4108B78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_735 0x4108B7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_736 0x4108B80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_737 0x4108B84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_738 0x4108B88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_739 0x4108B8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_740 0x4108B90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_741 0x4108B94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_742 0x4108B98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_743 0x4108B9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_744 0x4108BA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_745 0x4108BA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_746 0x4108BA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_747 0x4108BAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_748 0x4108BB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_749 0x4108BB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_750 0x4108BB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_751 0x4108BBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_752 0x4108BC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_753 0x4108BC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_754 0x4108BC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_755 0x4108BCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_756 0x4108BD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_757 0x4108BD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_758 0x4108BD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_759 0x4108BDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_760 0x4108BE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_761 0x4108BE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_762 0x4108BE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_763 0x4108BEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_764 0x4108BF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_765 0x4108BF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_766 0x4108BF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_767 0x4108BFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_768 0x4108C00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_769 0x4108C04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_770 0x4108C08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_771 0x4108C0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_772 0x4108C10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_773 0x4108C14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_774 0x4108C18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_775 0x4108C1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_776 0x4108C20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_777 0x4108C24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_778 0x4108C28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_779 0x4108C2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_780 0x4108C30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_781 0x4108C34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_782 0x4108C38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_783 0x4108C3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_784 0x4108C40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_785 0x4108C44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_786 0x4108C48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_787 0x4108C4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_788 0x4108C50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_789 0x4108C54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_790 0x4108C58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_791 0x4108C5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_792 0x4108C60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_793 0x4108C64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_794 0x4108C68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_795 0x4108C6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_796 0x4108C70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_797 0x4108C74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_798 0x4108C78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_799 0x4108C7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_800 0x4108C80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_801 0x4108C84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_802 0x4108C88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_803 0x4108C8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_804 0x4108C90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_805 0x4108C94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_806 0x4108C98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_807 0x4108C9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_808 0x4108CA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_809 0x4108CA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_810 0x4108CA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_811 0x4108CAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_812 0x4108CB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_813 0x4108CB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_814 0x4108CB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_815 0x4108CBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_816 0x4108CC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_817 0x4108CC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_818 0x4108CC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_819 0x4108CCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_820 0x4108CD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_821 0x4108CD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_822 0x4108CD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_823 0x4108CDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_824 0x4108CE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_825 0x4108CE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_826 0x4108CE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_827 0x4108CEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_828 0x4108CF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_829 0x4108CF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_830 0x4108CF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_831 0x4108CFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_832 0x4108D00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_833 0x4108D04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_834 0x4108D08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_835 0x4108D0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_836 0x4108D10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_837 0x4108D14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_838 0x4108D18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_839 0x4108D1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_840 0x4108D20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_841 0x4108D24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_842 0x4108D28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_843 0x4108D2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_844 0x4108D30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_845 0x4108D34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_846 0x4108D38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_847 0x4108D3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_848 0x4108D40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_849 0x4108D44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_850 0x4108D48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_851 0x4108D4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_852 0x4108D50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_853 0x4108D54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_854 0x4108D58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_855 0x4108D5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_856 0x4108D60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_857 0x4108D64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_858 0x4108D68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_859 0x4108D6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_860 0x4108D70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_861 0x4108D74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_862 0x4108D78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_863 0x4108D7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_864 0x4108D80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_865 0x4108D84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_866 0x4108D88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_867 0x4108D8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_868 0x4108D90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_869 0x4108D94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_870 0x4108D98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_871 0x4108D9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_872 0x4108DA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_873 0x4108DA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_874 0x4108DA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_875 0x4108DAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_876 0x4108DB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_877 0x4108DB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_878 0x4108DB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_879 0x4108DBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_880 0x4108DC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_881 0x4108DC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_882 0x4108DC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_883 0x4108DCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_884 0x4108DD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_885 0x4108DD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_886 0x4108DD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_887 0x4108DDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_888 0x4108DE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_889 0x4108DE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_890 0x4108DE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_891 0x4108DEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_892 0x4108DF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_893 0x4108DF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_894 0x4108DF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_895 0x4108DFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_896 0x4108E00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_897 0x4108E04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_898 0x4108E08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_899 0x4108E0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_900 0x4108E10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_901 0x4108E14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_902 0x4108E18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_903 0x4108E1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_904 0x4108E20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_905 0x4108E24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_906 0x4108E28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_907 0x4108E2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_908 0x4108E30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_909 0x4108E34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_910 0x4108E38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_911 0x4108E3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_912 0x4108E40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_913 0x4108E44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_914 0x4108E48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_915 0x4108E4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_916 0x4108E50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_917 0x4108E54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_918 0x4108E58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_919 0x4108E5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_920 0x4108E60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_921 0x4108E64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_922 0x4108E68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_923 0x4108E6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_924 0x4108E70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_925 0x4108E74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_926 0x4108E78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_927 0x4108E7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_928 0x4108E80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_929 0x4108E84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_930 0x4108E88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_931 0x4108E8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_932 0x4108E90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_933 0x4108E94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_934 0x4108E98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_935 0x4108E9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_936 0x4108EA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_937 0x4108EA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_938 0x4108EA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_939 0x4108EAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_940 0x4108EB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_941 0x4108EB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_942 0x4108EB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_943 0x4108EBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_944 0x4108EC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_945 0x4108EC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_946 0x4108EC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_947 0x4108ECC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_948 0x4108ED0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_949 0x4108ED4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_950 0x4108ED8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_951 0x4108EDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_952 0x4108EE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_953 0x4108EE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_954 0x4108EE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_955 0x4108EEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_956 0x4108EF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_957 0x4108EF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_958 0x4108EF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_959 0x4108EFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_960 0x4108F00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_961 0x4108F04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_962 0x4108F08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_963 0x4108F0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_964 0x4108F10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_965 0x4108F14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_966 0x4108F18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_967 0x4108F1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_968 0x4108F20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_969 0x4108F24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_970 0x4108F28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_971 0x4108F2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_972 0x4108F30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_973 0x4108F34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_974 0x4108F38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_975 0x4108F3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_976 0x4108F40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_977 0x4108F44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_978 0x4108F48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_979 0x4108F4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_980 0x4108F50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_981 0x4108F54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_982 0x4108F58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_983 0x4108F5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_984 0x4108F60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_985 0x4108F64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_986 0x4108F68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_987 0x4108F6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_988 0x4108F70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_989 0x4108F74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_990 0x4108F78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_991 0x4108F7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_992 0x4108F80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_993 0x4108F84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_994 0x4108F88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_995 0x4108F8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_996 0x4108F90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_997 0x4108F94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_998 0x4108F98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_999 0x4108F9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1000 0x4108FA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1001 0x4108FA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1002 0x4108FA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1003 0x4108FAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1004 0x4108FB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1005 0x4108FB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1006 0x4108FB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1007 0x4108FBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1008 0x4108FC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1009 0x4108FC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1010 0x4108FC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1011 0x4108FCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1012 0x4108FD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1013 0x4108FD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1014 0x4108FD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1015 0x4108FDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1016 0x4108FE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1017 0x4108FE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1018 0x4108FE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1019 0x4108FEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1020 0x4108FF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1021 0x4108FF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1022 0x4108FF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1023 0x4108FFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1024 0x4109000
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1025 0x4109004
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1026 0x4109008
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1027 0x410900C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1028 0x4109010
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1029 0x4109014
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1030 0x4109018
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1031 0x410901C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1032 0x4109020
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1033 0x4109024
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1034 0x4109028
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1035 0x410902C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1036 0x4109030
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1037 0x4109034
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1038 0x4109038
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1039 0x410903C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1040 0x4109040
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1041 0x4109044
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1042 0x4109048
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1043 0x410904C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1044 0x4109050
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1045 0x4109054
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1046 0x4109058
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1047 0x410905C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1048 0x4109060
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1049 0x4109064
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1050 0x4109068
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1051 0x410906C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1052 0x4109070
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1053 0x4109074
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1054 0x4109078
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1055 0x410907C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1056 0x4109080
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1057 0x4109084
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1058 0x4109088
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1059 0x410908C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1060 0x4109090
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1061 0x4109094
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1062 0x4109098
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1063 0x410909C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1064 0x41090A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1065 0x41090A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1066 0x41090A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1067 0x41090AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1068 0x41090B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1069 0x41090B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1070 0x41090B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1071 0x41090BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1072 0x41090C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1073 0x41090C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1074 0x41090C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1075 0x41090CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1076 0x41090D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1077 0x41090D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1078 0x41090D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1079 0x41090DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1080 0x41090E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1081 0x41090E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1082 0x41090E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1083 0x41090EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1084 0x41090F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1085 0x41090F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1086 0x41090F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1087 0x41090FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1088 0x4109100
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1089 0x4109104
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1090 0x4109108
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1091 0x410910C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1092 0x4109110
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1093 0x4109114
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1094 0x4109118
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1095 0x410911C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1096 0x4109120
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1097 0x4109124
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1098 0x4109128
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1099 0x410912C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1100 0x4109130
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1101 0x4109134
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1102 0x4109138
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1103 0x410913C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1104 0x4109140
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1105 0x4109144
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1106 0x4109148
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1107 0x410914C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1108 0x4109150
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1109 0x4109154
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1110 0x4109158
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1111 0x410915C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1112 0x4109160
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1113 0x4109164
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1114 0x4109168
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1115 0x410916C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1116 0x4109170
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1117 0x4109174
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1118 0x4109178
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1119 0x410917C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1120 0x4109180
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1121 0x4109184
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1122 0x4109188
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1123 0x410918C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1124 0x4109190
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1125 0x4109194
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1126 0x4109198
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1127 0x410919C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1128 0x41091A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1129 0x41091A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1130 0x41091A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1131 0x41091AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1132 0x41091B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1133 0x41091B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1134 0x41091B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1135 0x41091BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1136 0x41091C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1137 0x41091C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1138 0x41091C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1139 0x41091CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1140 0x41091D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1141 0x41091D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1142 0x41091D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1143 0x41091DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1144 0x41091E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1145 0x41091E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1146 0x41091E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1147 0x41091EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1148 0x41091F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1149 0x41091F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1150 0x41091F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1151 0x41091FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1152 0x4109200
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1153 0x4109204
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1154 0x4109208
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1155 0x410920C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1156 0x4109210
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1157 0x4109214
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1158 0x4109218
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1159 0x410921C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1160 0x4109220
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1161 0x4109224
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1162 0x4109228
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1163 0x410922C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1164 0x4109230
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1165 0x4109234
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1166 0x4109238
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1167 0x410923C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1168 0x4109240
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1169 0x4109244
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1170 0x4109248
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1171 0x410924C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1172 0x4109250
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1173 0x4109254
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1174 0x4109258
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1175 0x410925C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1176 0x4109260
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1177 0x4109264
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1178 0x4109268
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1179 0x410926C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1180 0x4109270
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1181 0x4109274
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1182 0x4109278
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1183 0x410927C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1184 0x4109280
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1185 0x4109284
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1186 0x4109288
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1187 0x410928C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1188 0x4109290
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1189 0x4109294
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1190 0x4109298
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1191 0x410929C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1192 0x41092A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1193 0x41092A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1194 0x41092A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1195 0x41092AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1196 0x41092B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1197 0x41092B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1198 0x41092B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1199 0x41092BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1200 0x41092C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1201 0x41092C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1202 0x41092C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1203 0x41092CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1204 0x41092D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1205 0x41092D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1206 0x41092D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1207 0x41092DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1208 0x41092E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1209 0x41092E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1210 0x41092E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1211 0x41092EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1212 0x41092F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1213 0x41092F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1214 0x41092F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1215 0x41092FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1216 0x4109300
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1217 0x4109304
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1218 0x4109308
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1219 0x410930C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1220 0x4109310
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1221 0x4109314
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1222 0x4109318
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1223 0x410931C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1224 0x4109320
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1225 0x4109324
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1226 0x4109328
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1227 0x410932C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1228 0x4109330
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1229 0x4109334
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1230 0x4109338
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1231 0x410933C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1232 0x4109340
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1233 0x4109344
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1234 0x4109348
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1235 0x410934C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1236 0x4109350
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1237 0x4109354
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1238 0x4109358
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1239 0x410935C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1240 0x4109360
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1241 0x4109364
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1242 0x4109368
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1243 0x410936C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1244 0x4109370
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1245 0x4109374
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1246 0x4109378
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1247 0x410937C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1248 0x4109380
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1249 0x4109384
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1250 0x4109388
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1251 0x410938C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1252 0x4109390
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1253 0x4109394
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1254 0x4109398
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1255 0x410939C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1256 0x41093A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1257 0x41093A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1258 0x41093A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1259 0x41093AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1260 0x41093B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1261 0x41093B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1262 0x41093B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1263 0x41093BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1264 0x41093C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1265 0x41093C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1266 0x41093C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1267 0x41093CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1268 0x41093D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1269 0x41093D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1270 0x41093D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1271 0x41093DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1272 0x41093E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1273 0x41093E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1274 0x41093E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1275 0x41093EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1276 0x41093F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1277 0x41093F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1278 0x41093F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1279 0x41093FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1280 0x4109400
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1281 0x4109404
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1282 0x4109408
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1283 0x410940C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1284 0x4109410
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1285 0x4109414
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1286 0x4109418
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1287 0x410941C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1288 0x4109420
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1289 0x4109424
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1290 0x4109428
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1291 0x410942C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1292 0x4109430
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1293 0x4109434
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1294 0x4109438
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1295 0x410943C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1296 0x4109440
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1297 0x4109444
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1298 0x4109448
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1299 0x410944C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1300 0x4109450
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1301 0x4109454
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1302 0x4109458
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1303 0x410945C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1304 0x4109460
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1305 0x4109464
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1306 0x4109468
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1307 0x410946C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1308 0x4109470
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1309 0x4109474
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1310 0x4109478
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1311 0x410947C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1312 0x4109480
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1313 0x4109484
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1314 0x4109488
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1315 0x410948C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1316 0x4109490
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1317 0x4109494
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1318 0x4109498
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1319 0x410949C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1320 0x41094A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1321 0x41094A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1322 0x41094A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1323 0x41094AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1324 0x41094B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1325 0x41094B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1326 0x41094B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1327 0x41094BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1328 0x41094C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1329 0x41094C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1330 0x41094C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1331 0x41094CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1332 0x41094D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1333 0x41094D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1334 0x41094D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1335 0x41094DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1336 0x41094E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1337 0x41094E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1338 0x41094E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1339 0x41094EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1340 0x41094F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1341 0x41094F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1342 0x41094F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1343 0x41094FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1344 0x4109500
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1345 0x4109504
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1346 0x4109508
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1347 0x410950C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1348 0x4109510
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1349 0x4109514
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1350 0x4109518
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1351 0x410951C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1352 0x4109520
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1353 0x4109524
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1354 0x4109528
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1355 0x410952C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1356 0x4109530
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1357 0x4109534
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1358 0x4109538
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1359 0x410953C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1360 0x4109540
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1361 0x4109544
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1362 0x4109548
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1363 0x410954C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1364 0x4109550
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1365 0x4109554
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1366 0x4109558
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1367 0x410955C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1368 0x4109560
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1369 0x4109564
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1370 0x4109568
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1371 0x410956C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1372 0x4109570
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1373 0x4109574
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1374 0x4109578
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1375 0x410957C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1376 0x4109580
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1377 0x4109584
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1378 0x4109588
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1379 0x410958C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1380 0x4109590
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1381 0x4109594
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1382 0x4109598
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1383 0x410959C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1384 0x41095A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1385 0x41095A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1386 0x41095A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1387 0x41095AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1388 0x41095B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1389 0x41095B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1390 0x41095B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1391 0x41095BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1392 0x41095C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1393 0x41095C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1394 0x41095C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1395 0x41095CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1396 0x41095D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1397 0x41095D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1398 0x41095D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1399 0x41095DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1400 0x41095E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1401 0x41095E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1402 0x41095E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1403 0x41095EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1404 0x41095F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1405 0x41095F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1406 0x41095F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1407 0x41095FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1408 0x4109600
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1409 0x4109604
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1410 0x4109608
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1411 0x410960C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1412 0x4109610
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1413 0x4109614
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1414 0x4109618
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1415 0x410961C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1416 0x4109620
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1417 0x4109624
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1418 0x4109628
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1419 0x410962C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1420 0x4109630
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1421 0x4109634
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1422 0x4109638
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1423 0x410963C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1424 0x4109640
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1425 0x4109644
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1426 0x4109648
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1427 0x410964C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1428 0x4109650
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1429 0x4109654
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1430 0x4109658
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1431 0x410965C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1432 0x4109660
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1433 0x4109664
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1434 0x4109668
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1435 0x410966C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1436 0x4109670
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1437 0x4109674
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1438 0x4109678
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1439 0x410967C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1440 0x4109680
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1441 0x4109684
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1442 0x4109688
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1443 0x410968C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1444 0x4109690
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1445 0x4109694
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1446 0x4109698
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1447 0x410969C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1448 0x41096A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1449 0x41096A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1450 0x41096A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1451 0x41096AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1452 0x41096B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1453 0x41096B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1454 0x41096B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1455 0x41096BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1456 0x41096C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1457 0x41096C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1458 0x41096C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1459 0x41096CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1460 0x41096D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1461 0x41096D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1462 0x41096D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1463 0x41096DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1464 0x41096E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1465 0x41096E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1466 0x41096E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1467 0x41096EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1468 0x41096F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1469 0x41096F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1470 0x41096F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1471 0x41096FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1472 0x4109700
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1473 0x4109704
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1474 0x4109708
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1475 0x410970C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1476 0x4109710
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1477 0x4109714
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1478 0x4109718
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1479 0x410971C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1480 0x4109720
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1481 0x4109724
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1482 0x4109728
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1483 0x410972C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1484 0x4109730
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1485 0x4109734
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1486 0x4109738
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1487 0x410973C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1488 0x4109740
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1489 0x4109744
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1490 0x4109748
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1491 0x410974C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1492 0x4109750
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1493 0x4109754
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1494 0x4109758
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1495 0x410975C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1496 0x4109760
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1497 0x4109764
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1498 0x4109768
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1499 0x410976C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1500 0x4109770
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1501 0x4109774
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1502 0x4109778
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1503 0x410977C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1504 0x4109780
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1505 0x4109784
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1506 0x4109788
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1507 0x410978C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1508 0x4109790
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1509 0x4109794
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1510 0x4109798
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1511 0x410979C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1512 0x41097A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1513 0x41097A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1514 0x41097A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1515 0x41097AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1516 0x41097B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1517 0x41097B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1518 0x41097B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1519 0x41097BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1520 0x41097C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1521 0x41097C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1522 0x41097C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1523 0x41097CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1524 0x41097D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1525 0x41097D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1526 0x41097D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1527 0x41097DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1528 0x41097E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1529 0x41097E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1530 0x41097E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1531 0x41097EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1532 0x41097F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1533 0x41097F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1534 0x41097F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1535 0x41097FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1536 0x4109800
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1537 0x4109804
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1538 0x4109808
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1539 0x410980C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1540 0x4109810
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1541 0x4109814
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1542 0x4109818
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1543 0x410981C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1544 0x4109820
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1545 0x4109824
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1546 0x4109828
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1547 0x410982C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1548 0x4109830
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1549 0x4109834
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1550 0x4109838
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1551 0x410983C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1552 0x4109840
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1553 0x4109844
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1554 0x4109848
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1555 0x410984C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1556 0x4109850
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1557 0x4109854
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1558 0x4109858
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1559 0x410985C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1560 0x4109860
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1561 0x4109864
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1562 0x4109868
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1563 0x410986C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1564 0x4109870
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1565 0x4109874
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1566 0x4109878
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1567 0x410987C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1568 0x4109880
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1569 0x4109884
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1570 0x4109888
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1571 0x410988C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1572 0x4109890
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1573 0x4109894
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1574 0x4109898
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1575 0x410989C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1576 0x41098A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1577 0x41098A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1578 0x41098A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1579 0x41098AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1580 0x41098B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1581 0x41098B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1582 0x41098B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1583 0x41098BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1584 0x41098C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1585 0x41098C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1586 0x41098C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1587 0x41098CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1588 0x41098D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1589 0x41098D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1590 0x41098D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1591 0x41098DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1592 0x41098E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1593 0x41098E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1594 0x41098E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1595 0x41098EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1596 0x41098F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1597 0x41098F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1598 0x41098F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1599 0x41098FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1600 0x4109900
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1601 0x4109904
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1602 0x4109908
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1603 0x410990C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1604 0x4109910
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1605 0x4109914
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1606 0x4109918
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1607 0x410991C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1608 0x4109920
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1609 0x4109924
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1610 0x4109928
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1611 0x410992C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1612 0x4109930
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1613 0x4109934
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1614 0x4109938
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1615 0x410993C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1616 0x4109940
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1617 0x4109944
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1618 0x4109948
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1619 0x410994C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1620 0x4109950
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1621 0x4109954
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1622 0x4109958
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1623 0x410995C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1624 0x4109960
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1625 0x4109964
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1626 0x4109968
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1627 0x410996C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1628 0x4109970
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1629 0x4109974
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1630 0x4109978
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1631 0x410997C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1632 0x4109980
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1633 0x4109984
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1634 0x4109988
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1635 0x410998C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1636 0x4109990
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1637 0x4109994
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1638 0x4109998
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1639 0x410999C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1640 0x41099A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1641 0x41099A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1642 0x41099A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1643 0x41099AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1644 0x41099B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1645 0x41099B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1646 0x41099B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1647 0x41099BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1648 0x41099C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1649 0x41099C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1650 0x41099C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1651 0x41099CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1652 0x41099D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1653 0x41099D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1654 0x41099D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1655 0x41099DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1656 0x41099E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1657 0x41099E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1658 0x41099E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1659 0x41099EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1660 0x41099F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1661 0x41099F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1662 0x41099F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1663 0x41099FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1664 0x4109A00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1665 0x4109A04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1666 0x4109A08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1667 0x4109A0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1668 0x4109A10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1669 0x4109A14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1670 0x4109A18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1671 0x4109A1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1672 0x4109A20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1673 0x4109A24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1674 0x4109A28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1675 0x4109A2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1676 0x4109A30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1677 0x4109A34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1678 0x4109A38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1679 0x4109A3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1680 0x4109A40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1681 0x4109A44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1682 0x4109A48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1683 0x4109A4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1684 0x4109A50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1685 0x4109A54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1686 0x4109A58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1687 0x4109A5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1688 0x4109A60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1689 0x4109A64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1690 0x4109A68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1691 0x4109A6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1692 0x4109A70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1693 0x4109A74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1694 0x4109A78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1695 0x4109A7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1696 0x4109A80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1697 0x4109A84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1698 0x4109A88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1699 0x4109A8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1700 0x4109A90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1701 0x4109A94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1702 0x4109A98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1703 0x4109A9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1704 0x4109AA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1705 0x4109AA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1706 0x4109AA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1707 0x4109AAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1708 0x4109AB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1709 0x4109AB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1710 0x4109AB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1711 0x4109ABC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1712 0x4109AC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1713 0x4109AC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1714 0x4109AC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1715 0x4109ACC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1716 0x4109AD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1717 0x4109AD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1718 0x4109AD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1719 0x4109ADC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1720 0x4109AE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1721 0x4109AE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1722 0x4109AE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1723 0x4109AEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1724 0x4109AF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1725 0x4109AF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1726 0x4109AF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1727 0x4109AFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1728 0x4109B00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1729 0x4109B04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1730 0x4109B08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1731 0x4109B0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1732 0x4109B10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1733 0x4109B14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1734 0x4109B18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1735 0x4109B1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1736 0x4109B20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1737 0x4109B24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1738 0x4109B28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1739 0x4109B2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1740 0x4109B30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1741 0x4109B34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1742 0x4109B38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1743 0x4109B3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1744 0x4109B40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1745 0x4109B44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1746 0x4109B48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1747 0x4109B4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1748 0x4109B50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1749 0x4109B54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1750 0x4109B58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1751 0x4109B5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1752 0x4109B60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1753 0x4109B64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1754 0x4109B68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1755 0x4109B6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1756 0x4109B70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1757 0x4109B74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1758 0x4109B78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1759 0x4109B7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1760 0x4109B80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1761 0x4109B84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1762 0x4109B88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1763 0x4109B8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1764 0x4109B90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1765 0x4109B94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1766 0x4109B98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1767 0x4109B9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1768 0x4109BA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1769 0x4109BA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1770 0x4109BA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1771 0x4109BAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1772 0x4109BB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1773 0x4109BB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1774 0x4109BB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1775 0x4109BBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1776 0x4109BC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1777 0x4109BC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1778 0x4109BC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1779 0x4109BCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1780 0x4109BD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1781 0x4109BD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1782 0x4109BD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1783 0x4109BDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1784 0x4109BE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1785 0x4109BE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1786 0x4109BE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1787 0x4109BEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1788 0x4109BF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1789 0x4109BF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1790 0x4109BF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1791 0x4109BFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1792 0x4109C00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1793 0x4109C04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1794 0x4109C08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1795 0x4109C0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1796 0x4109C10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1797 0x4109C14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1798 0x4109C18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1799 0x4109C1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1800 0x4109C20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1801 0x4109C24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1802 0x4109C28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1803 0x4109C2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1804 0x4109C30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1805 0x4109C34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1806 0x4109C38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1807 0x4109C3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1808 0x4109C40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1809 0x4109C44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1810 0x4109C48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1811 0x4109C4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1812 0x4109C50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1813 0x4109C54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1814 0x4109C58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1815 0x4109C5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1816 0x4109C60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1817 0x4109C64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1818 0x4109C68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1819 0x4109C6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1820 0x4109C70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1821 0x4109C74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1822 0x4109C78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1823 0x4109C7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1824 0x4109C80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1825 0x4109C84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1826 0x4109C88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1827 0x4109C8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1828 0x4109C90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1829 0x4109C94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1830 0x4109C98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1831 0x4109C9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1832 0x4109CA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1833 0x4109CA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1834 0x4109CA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1835 0x4109CAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1836 0x4109CB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1837 0x4109CB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1838 0x4109CB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1839 0x4109CBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1840 0x4109CC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1841 0x4109CC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1842 0x4109CC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1843 0x4109CCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1844 0x4109CD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1845 0x4109CD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1846 0x4109CD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1847 0x4109CDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1848 0x4109CE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1849 0x4109CE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1850 0x4109CE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1851 0x4109CEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1852 0x4109CF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1853 0x4109CF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1854 0x4109CF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1855 0x4109CFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1856 0x4109D00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1857 0x4109D04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1858 0x4109D08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1859 0x4109D0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1860 0x4109D10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1861 0x4109D14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1862 0x4109D18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1863 0x4109D1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1864 0x4109D20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1865 0x4109D24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1866 0x4109D28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1867 0x4109D2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1868 0x4109D30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1869 0x4109D34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1870 0x4109D38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1871 0x4109D3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1872 0x4109D40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1873 0x4109D44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1874 0x4109D48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1875 0x4109D4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1876 0x4109D50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1877 0x4109D54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1878 0x4109D58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1879 0x4109D5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1880 0x4109D60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1881 0x4109D64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1882 0x4109D68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1883 0x4109D6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1884 0x4109D70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1885 0x4109D74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1886 0x4109D78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1887 0x4109D7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1888 0x4109D80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1889 0x4109D84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1890 0x4109D88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1891 0x4109D8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1892 0x4109D90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1893 0x4109D94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1894 0x4109D98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1895 0x4109D9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1896 0x4109DA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1897 0x4109DA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1898 0x4109DA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1899 0x4109DAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1900 0x4109DB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1901 0x4109DB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1902 0x4109DB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1903 0x4109DBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1904 0x4109DC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1905 0x4109DC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1906 0x4109DC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1907 0x4109DCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1908 0x4109DD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1909 0x4109DD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1910 0x4109DD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1911 0x4109DDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1912 0x4109DE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1913 0x4109DE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1914 0x4109DE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1915 0x4109DEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1916 0x4109DF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1917 0x4109DF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1918 0x4109DF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1919 0x4109DFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1920 0x4109E00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1921 0x4109E04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1922 0x4109E08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1923 0x4109E0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1924 0x4109E10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1925 0x4109E14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1926 0x4109E18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1927 0x4109E1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1928 0x4109E20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1929 0x4109E24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1930 0x4109E28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1931 0x4109E2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1932 0x4109E30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1933 0x4109E34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1934 0x4109E38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1935 0x4109E3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1936 0x4109E40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1937 0x4109E44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1938 0x4109E48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1939 0x4109E4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1940 0x4109E50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1941 0x4109E54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1942 0x4109E58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1943 0x4109E5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1944 0x4109E60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1945 0x4109E64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1946 0x4109E68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1947 0x4109E6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1948 0x4109E70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1949 0x4109E74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1950 0x4109E78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1951 0x4109E7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1952 0x4109E80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1953 0x4109E84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1954 0x4109E88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1955 0x4109E8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1956 0x4109E90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1957 0x4109E94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1958 0x4109E98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1959 0x4109E9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1960 0x4109EA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1961 0x4109EA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1962 0x4109EA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1963 0x4109EAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1964 0x4109EB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1965 0x4109EB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1966 0x4109EB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1967 0x4109EBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1968 0x4109EC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1969 0x4109EC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1970 0x4109EC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1971 0x4109ECC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1972 0x4109ED0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1973 0x4109ED4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1974 0x4109ED8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1975 0x4109EDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1976 0x4109EE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1977 0x4109EE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1978 0x4109EE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1979 0x4109EEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1980 0x4109EF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1981 0x4109EF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1982 0x4109EF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1983 0x4109EFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1984 0x4109F00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1985 0x4109F04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1986 0x4109F08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1987 0x4109F0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1988 0x4109F10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1989 0x4109F14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1990 0x4109F18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1991 0x4109F1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1992 0x4109F20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1993 0x4109F24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1994 0x4109F28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1995 0x4109F2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1996 0x4109F30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1997 0x4109F34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1998 0x4109F38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_1999 0x4109F3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2000 0x4109F40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2001 0x4109F44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2002 0x4109F48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2003 0x4109F4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2004 0x4109F50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2005 0x4109F54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2006 0x4109F58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2007 0x4109F5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2008 0x4109F60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2009 0x4109F64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2010 0x4109F68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2011 0x4109F6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2012 0x4109F70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2013 0x4109F74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2014 0x4109F78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2015 0x4109F7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2016 0x4109F80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2017 0x4109F84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2018 0x4109F88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2019 0x4109F8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2020 0x4109F90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2021 0x4109F94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2022 0x4109F98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2023 0x4109F9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2024 0x4109FA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2025 0x4109FA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2026 0x4109FA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2027 0x4109FAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2028 0x4109FB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2029 0x4109FB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2030 0x4109FB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2031 0x4109FBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2032 0x4109FC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2033 0x4109FC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2034 0x4109FC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2035 0x4109FCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2036 0x4109FD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2037 0x4109FD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2038 0x4109FD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2039 0x4109FDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2040 0x4109FE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2041 0x4109FE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2042 0x4109FE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2043 0x4109FEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2044 0x4109FF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2045 0x4109FF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2046 0x4109FF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_2047 0x4109FFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_0 0x410A000
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1 0x410A004
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2 0x410A008
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_3 0x410A00C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_4 0x410A010
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_5 0x410A014
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_6 0x410A018
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_7 0x410A01C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_8 0x410A020
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_9 0x410A024
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_10 0x410A028
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_11 0x410A02C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_12 0x410A030
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_13 0x410A034
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_14 0x410A038
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_15 0x410A03C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_16 0x410A040
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_17 0x410A044
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_18 0x410A048
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_19 0x410A04C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_20 0x410A050
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_21 0x410A054
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_22 0x410A058
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_23 0x410A05C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_24 0x410A060
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_25 0x410A064
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_26 0x410A068
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_27 0x410A06C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_28 0x410A070
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_29 0x410A074
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_30 0x410A078
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_31 0x410A07C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_32 0x410A080
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_33 0x410A084
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_34 0x410A088
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_35 0x410A08C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_36 0x410A090
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_37 0x410A094
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_38 0x410A098
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_39 0x410A09C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_40 0x410A0A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_41 0x410A0A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_42 0x410A0A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_43 0x410A0AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_44 0x410A0B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_45 0x410A0B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_46 0x410A0B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_47 0x410A0BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_48 0x410A0C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_49 0x410A0C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_50 0x410A0C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_51 0x410A0CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_52 0x410A0D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_53 0x410A0D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_54 0x410A0D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_55 0x410A0DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_56 0x410A0E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_57 0x410A0E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_58 0x410A0E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_59 0x410A0EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_60 0x410A0F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_61 0x410A0F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_62 0x410A0F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_63 0x410A0FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_64 0x410A100
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_65 0x410A104
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_66 0x410A108
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_67 0x410A10C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_68 0x410A110
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_69 0x410A114
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_70 0x410A118
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_71 0x410A11C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_72 0x410A120
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_73 0x410A124
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_74 0x410A128
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_75 0x410A12C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_76 0x410A130
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_77 0x410A134
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_78 0x410A138
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_79 0x410A13C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_80 0x410A140
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_81 0x410A144
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_82 0x410A148
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_83 0x410A14C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_84 0x410A150
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_85 0x410A154
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_86 0x410A158
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_87 0x410A15C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_88 0x410A160
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_89 0x410A164
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_90 0x410A168
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_91 0x410A16C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_92 0x410A170
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_93 0x410A174
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_94 0x410A178
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_95 0x410A17C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_96 0x410A180
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_97 0x410A184
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_98 0x410A188
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_99 0x410A18C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_100 0x410A190
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_101 0x410A194
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_102 0x410A198
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_103 0x410A19C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_104 0x410A1A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_105 0x410A1A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_106 0x410A1A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_107 0x410A1AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_108 0x410A1B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_109 0x410A1B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_110 0x410A1B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_111 0x410A1BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_112 0x410A1C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_113 0x410A1C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_114 0x410A1C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_115 0x410A1CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_116 0x410A1D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_117 0x410A1D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_118 0x410A1D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_119 0x410A1DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_120 0x410A1E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_121 0x410A1E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_122 0x410A1E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_123 0x410A1EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_124 0x410A1F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_125 0x410A1F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_126 0x410A1F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_127 0x410A1FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_128 0x410A200
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_129 0x410A204
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_130 0x410A208
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_131 0x410A20C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_132 0x410A210
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_133 0x410A214
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_134 0x410A218
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_135 0x410A21C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_136 0x410A220
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_137 0x410A224
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_138 0x410A228
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_139 0x410A22C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_140 0x410A230
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_141 0x410A234
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_142 0x410A238
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_143 0x410A23C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_144 0x410A240
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_145 0x410A244
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_146 0x410A248
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_147 0x410A24C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_148 0x410A250
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_149 0x410A254
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_150 0x410A258
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_151 0x410A25C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_152 0x410A260
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_153 0x410A264
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_154 0x410A268
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_155 0x410A26C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_156 0x410A270
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_157 0x410A274
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_158 0x410A278
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_159 0x410A27C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_160 0x410A280
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_161 0x410A284
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_162 0x410A288
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_163 0x410A28C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_164 0x410A290
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_165 0x410A294
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_166 0x410A298
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_167 0x410A29C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_168 0x410A2A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_169 0x410A2A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_170 0x410A2A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_171 0x410A2AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_172 0x410A2B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_173 0x410A2B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_174 0x410A2B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_175 0x410A2BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_176 0x410A2C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_177 0x410A2C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_178 0x410A2C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_179 0x410A2CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_180 0x410A2D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_181 0x410A2D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_182 0x410A2D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_183 0x410A2DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_184 0x410A2E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_185 0x410A2E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_186 0x410A2E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_187 0x410A2EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_188 0x410A2F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_189 0x410A2F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_190 0x410A2F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_191 0x410A2FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_192 0x410A300
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_193 0x410A304
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_194 0x410A308
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_195 0x410A30C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_196 0x410A310
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_197 0x410A314
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_198 0x410A318
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_199 0x410A31C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_200 0x410A320
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_201 0x410A324
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_202 0x410A328
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_203 0x410A32C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_204 0x410A330
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_205 0x410A334
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_206 0x410A338
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_207 0x410A33C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_208 0x410A340
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_209 0x410A344
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_210 0x410A348
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_211 0x410A34C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_212 0x410A350
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_213 0x410A354
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_214 0x410A358
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_215 0x410A35C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_216 0x410A360
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_217 0x410A364
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_218 0x410A368
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_219 0x410A36C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_220 0x410A370
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_221 0x410A374
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_222 0x410A378
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_223 0x410A37C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_224 0x410A380
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_225 0x410A384
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_226 0x410A388
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_227 0x410A38C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_228 0x410A390
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_229 0x410A394
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_230 0x410A398
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_231 0x410A39C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_232 0x410A3A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_233 0x410A3A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_234 0x410A3A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_235 0x410A3AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_236 0x410A3B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_237 0x410A3B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_238 0x410A3B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_239 0x410A3BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_240 0x410A3C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_241 0x410A3C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_242 0x410A3C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_243 0x410A3CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_244 0x410A3D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_245 0x410A3D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_246 0x410A3D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_247 0x410A3DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_248 0x410A3E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_249 0x410A3E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_250 0x410A3E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_251 0x410A3EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_252 0x410A3F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_253 0x410A3F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_254 0x410A3F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_255 0x410A3FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_256 0x410A400
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_257 0x410A404
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_258 0x410A408
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_259 0x410A40C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_260 0x410A410
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_261 0x410A414
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_262 0x410A418
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_263 0x410A41C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_264 0x410A420
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_265 0x410A424
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_266 0x410A428
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_267 0x410A42C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_268 0x410A430
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_269 0x410A434
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_270 0x410A438
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_271 0x410A43C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_272 0x410A440
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_273 0x410A444
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_274 0x410A448
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_275 0x410A44C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_276 0x410A450
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_277 0x410A454
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_278 0x410A458
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_279 0x410A45C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_280 0x410A460
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_281 0x410A464
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_282 0x410A468
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_283 0x410A46C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_284 0x410A470
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_285 0x410A474
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_286 0x410A478
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_287 0x410A47C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_288 0x410A480
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_289 0x410A484
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_290 0x410A488
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_291 0x410A48C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_292 0x410A490
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_293 0x410A494
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_294 0x410A498
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_295 0x410A49C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_296 0x410A4A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_297 0x410A4A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_298 0x410A4A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_299 0x410A4AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_300 0x410A4B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_301 0x410A4B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_302 0x410A4B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_303 0x410A4BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_304 0x410A4C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_305 0x410A4C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_306 0x410A4C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_307 0x410A4CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_308 0x410A4D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_309 0x410A4D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_310 0x410A4D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_311 0x410A4DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_312 0x410A4E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_313 0x410A4E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_314 0x410A4E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_315 0x410A4EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_316 0x410A4F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_317 0x410A4F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_318 0x410A4F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_319 0x410A4FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_320 0x410A500
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_321 0x410A504
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_322 0x410A508
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_323 0x410A50C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_324 0x410A510
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_325 0x410A514
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_326 0x410A518
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_327 0x410A51C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_328 0x410A520
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_329 0x410A524
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_330 0x410A528
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_331 0x410A52C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_332 0x410A530
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_333 0x410A534
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_334 0x410A538
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_335 0x410A53C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_336 0x410A540
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_337 0x410A544
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_338 0x410A548
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_339 0x410A54C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_340 0x410A550
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_341 0x410A554
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_342 0x410A558
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_343 0x410A55C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_344 0x410A560
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_345 0x410A564
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_346 0x410A568
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_347 0x410A56C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_348 0x410A570
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_349 0x410A574
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_350 0x410A578
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_351 0x410A57C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_352 0x410A580
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_353 0x410A584
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_354 0x410A588
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_355 0x410A58C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_356 0x410A590
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_357 0x410A594
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_358 0x410A598
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_359 0x410A59C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_360 0x410A5A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_361 0x410A5A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_362 0x410A5A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_363 0x410A5AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_364 0x410A5B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_365 0x410A5B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_366 0x410A5B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_367 0x410A5BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_368 0x410A5C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_369 0x410A5C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_370 0x410A5C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_371 0x410A5CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_372 0x410A5D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_373 0x410A5D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_374 0x410A5D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_375 0x410A5DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_376 0x410A5E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_377 0x410A5E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_378 0x410A5E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_379 0x410A5EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_380 0x410A5F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_381 0x410A5F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_382 0x410A5F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_383 0x410A5FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_384 0x410A600
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_385 0x410A604
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_386 0x410A608
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_387 0x410A60C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_388 0x410A610
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_389 0x410A614
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_390 0x410A618
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_391 0x410A61C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_392 0x410A620
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_393 0x410A624
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_394 0x410A628
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_395 0x410A62C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_396 0x410A630
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_397 0x410A634
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_398 0x410A638
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_399 0x410A63C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_400 0x410A640
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_401 0x410A644
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_402 0x410A648
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_403 0x410A64C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_404 0x410A650
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_405 0x410A654
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_406 0x410A658
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_407 0x410A65C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_408 0x410A660
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_409 0x410A664
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_410 0x410A668
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_411 0x410A66C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_412 0x410A670
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_413 0x410A674
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_414 0x410A678
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_415 0x410A67C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_416 0x410A680
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_417 0x410A684
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_418 0x410A688
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_419 0x410A68C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_420 0x410A690
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_421 0x410A694
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_422 0x410A698
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_423 0x410A69C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_424 0x410A6A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_425 0x410A6A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_426 0x410A6A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_427 0x410A6AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_428 0x410A6B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_429 0x410A6B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_430 0x410A6B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_431 0x410A6BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_432 0x410A6C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_433 0x410A6C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_434 0x410A6C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_435 0x410A6CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_436 0x410A6D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_437 0x410A6D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_438 0x410A6D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_439 0x410A6DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_440 0x410A6E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_441 0x410A6E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_442 0x410A6E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_443 0x410A6EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_444 0x410A6F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_445 0x410A6F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_446 0x410A6F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_447 0x410A6FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_448 0x410A700
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_449 0x410A704
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_450 0x410A708
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_451 0x410A70C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_452 0x410A710
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_453 0x410A714
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_454 0x410A718
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_455 0x410A71C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_456 0x410A720
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_457 0x410A724
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_458 0x410A728
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_459 0x410A72C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_460 0x410A730
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_461 0x410A734
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_462 0x410A738
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_463 0x410A73C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_464 0x410A740
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_465 0x410A744
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_466 0x410A748
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_467 0x410A74C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_468 0x410A750
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_469 0x410A754
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_470 0x410A758
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_471 0x410A75C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_472 0x410A760
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_473 0x410A764
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_474 0x410A768
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_475 0x410A76C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_476 0x410A770
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_477 0x410A774
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_478 0x410A778
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_479 0x410A77C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_480 0x410A780
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_481 0x410A784
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_482 0x410A788
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_483 0x410A78C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_484 0x410A790
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_485 0x410A794
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_486 0x410A798
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_487 0x410A79C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_488 0x410A7A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_489 0x410A7A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_490 0x410A7A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_491 0x410A7AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_492 0x410A7B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_493 0x410A7B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_494 0x410A7B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_495 0x410A7BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_496 0x410A7C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_497 0x410A7C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_498 0x410A7C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_499 0x410A7CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_500 0x410A7D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_501 0x410A7D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_502 0x410A7D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_503 0x410A7DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_504 0x410A7E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_505 0x410A7E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_506 0x410A7E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_507 0x410A7EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_508 0x410A7F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_509 0x410A7F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_510 0x410A7F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_511 0x410A7FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_512 0x410A800
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_513 0x410A804
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_514 0x410A808
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_515 0x410A80C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_516 0x410A810
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_517 0x410A814
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_518 0x410A818
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_519 0x410A81C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_520 0x410A820
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_521 0x410A824
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_522 0x410A828
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_523 0x410A82C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_524 0x410A830
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_525 0x410A834
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_526 0x410A838
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_527 0x410A83C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_528 0x410A840
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_529 0x410A844
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_530 0x410A848
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_531 0x410A84C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_532 0x410A850
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_533 0x410A854
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_534 0x410A858
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_535 0x410A85C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_536 0x410A860
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_537 0x410A864
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_538 0x410A868
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_539 0x410A86C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_540 0x410A870
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_541 0x410A874
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_542 0x410A878
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_543 0x410A87C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_544 0x410A880
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_545 0x410A884
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_546 0x410A888
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_547 0x410A88C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_548 0x410A890
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_549 0x410A894
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_550 0x410A898
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_551 0x410A89C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_552 0x410A8A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_553 0x410A8A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_554 0x410A8A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_555 0x410A8AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_556 0x410A8B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_557 0x410A8B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_558 0x410A8B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_559 0x410A8BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_560 0x410A8C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_561 0x410A8C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_562 0x410A8C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_563 0x410A8CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_564 0x410A8D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_565 0x410A8D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_566 0x410A8D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_567 0x410A8DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_568 0x410A8E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_569 0x410A8E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_570 0x410A8E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_571 0x410A8EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_572 0x410A8F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_573 0x410A8F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_574 0x410A8F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_575 0x410A8FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_576 0x410A900
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_577 0x410A904
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_578 0x410A908
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_579 0x410A90C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_580 0x410A910
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_581 0x410A914
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_582 0x410A918
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_583 0x410A91C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_584 0x410A920
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_585 0x410A924
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_586 0x410A928
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_587 0x410A92C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_588 0x410A930
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_589 0x410A934
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_590 0x410A938
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_591 0x410A93C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_592 0x410A940
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_593 0x410A944
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_594 0x410A948
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_595 0x410A94C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_596 0x410A950
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_597 0x410A954
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_598 0x410A958
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_599 0x410A95C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_600 0x410A960
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_601 0x410A964
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_602 0x410A968
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_603 0x410A96C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_604 0x410A970
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_605 0x410A974
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_606 0x410A978
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_607 0x410A97C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_608 0x410A980
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_609 0x410A984
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_610 0x410A988
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_611 0x410A98C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_612 0x410A990
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_613 0x410A994
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_614 0x410A998
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_615 0x410A99C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_616 0x410A9A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_617 0x410A9A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_618 0x410A9A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_619 0x410A9AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_620 0x410A9B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_621 0x410A9B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_622 0x410A9B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_623 0x410A9BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_624 0x410A9C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_625 0x410A9C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_626 0x410A9C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_627 0x410A9CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_628 0x410A9D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_629 0x410A9D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_630 0x410A9D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_631 0x410A9DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_632 0x410A9E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_633 0x410A9E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_634 0x410A9E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_635 0x410A9EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_636 0x410A9F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_637 0x410A9F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_638 0x410A9F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_639 0x410A9FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_640 0x410AA00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_641 0x410AA04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_642 0x410AA08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_643 0x410AA0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_644 0x410AA10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_645 0x410AA14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_646 0x410AA18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_647 0x410AA1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_648 0x410AA20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_649 0x410AA24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_650 0x410AA28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_651 0x410AA2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_652 0x410AA30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_653 0x410AA34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_654 0x410AA38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_655 0x410AA3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_656 0x410AA40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_657 0x410AA44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_658 0x410AA48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_659 0x410AA4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_660 0x410AA50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_661 0x410AA54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_662 0x410AA58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_663 0x410AA5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_664 0x410AA60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_665 0x410AA64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_666 0x410AA68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_667 0x410AA6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_668 0x410AA70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_669 0x410AA74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_670 0x410AA78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_671 0x410AA7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_672 0x410AA80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_673 0x410AA84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_674 0x410AA88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_675 0x410AA8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_676 0x410AA90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_677 0x410AA94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_678 0x410AA98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_679 0x410AA9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_680 0x410AAA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_681 0x410AAA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_682 0x410AAA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_683 0x410AAAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_684 0x410AAB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_685 0x410AAB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_686 0x410AAB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_687 0x410AABC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_688 0x410AAC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_689 0x410AAC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_690 0x410AAC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_691 0x410AACC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_692 0x410AAD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_693 0x410AAD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_694 0x410AAD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_695 0x410AADC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_696 0x410AAE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_697 0x410AAE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_698 0x410AAE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_699 0x410AAEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_700 0x410AAF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_701 0x410AAF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_702 0x410AAF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_703 0x410AAFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_704 0x410AB00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_705 0x410AB04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_706 0x410AB08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_707 0x410AB0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_708 0x410AB10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_709 0x410AB14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_710 0x410AB18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_711 0x410AB1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_712 0x410AB20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_713 0x410AB24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_714 0x410AB28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_715 0x410AB2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_716 0x410AB30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_717 0x410AB34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_718 0x410AB38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_719 0x410AB3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_720 0x410AB40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_721 0x410AB44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_722 0x410AB48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_723 0x410AB4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_724 0x410AB50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_725 0x410AB54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_726 0x410AB58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_727 0x410AB5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_728 0x410AB60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_729 0x410AB64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_730 0x410AB68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_731 0x410AB6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_732 0x410AB70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_733 0x410AB74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_734 0x410AB78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_735 0x410AB7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_736 0x410AB80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_737 0x410AB84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_738 0x410AB88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_739 0x410AB8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_740 0x410AB90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_741 0x410AB94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_742 0x410AB98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_743 0x410AB9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_744 0x410ABA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_745 0x410ABA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_746 0x410ABA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_747 0x410ABAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_748 0x410ABB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_749 0x410ABB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_750 0x410ABB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_751 0x410ABBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_752 0x410ABC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_753 0x410ABC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_754 0x410ABC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_755 0x410ABCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_756 0x410ABD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_757 0x410ABD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_758 0x410ABD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_759 0x410ABDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_760 0x410ABE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_761 0x410ABE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_762 0x410ABE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_763 0x410ABEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_764 0x410ABF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_765 0x410ABF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_766 0x410ABF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_767 0x410ABFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_768 0x410AC00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_769 0x410AC04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_770 0x410AC08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_771 0x410AC0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_772 0x410AC10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_773 0x410AC14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_774 0x410AC18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_775 0x410AC1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_776 0x410AC20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_777 0x410AC24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_778 0x410AC28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_779 0x410AC2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_780 0x410AC30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_781 0x410AC34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_782 0x410AC38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_783 0x410AC3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_784 0x410AC40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_785 0x410AC44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_786 0x410AC48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_787 0x410AC4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_788 0x410AC50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_789 0x410AC54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_790 0x410AC58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_791 0x410AC5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_792 0x410AC60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_793 0x410AC64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_794 0x410AC68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_795 0x410AC6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_796 0x410AC70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_797 0x410AC74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_798 0x410AC78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_799 0x410AC7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_800 0x410AC80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_801 0x410AC84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_802 0x410AC88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_803 0x410AC8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_804 0x410AC90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_805 0x410AC94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_806 0x410AC98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_807 0x410AC9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_808 0x410ACA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_809 0x410ACA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_810 0x410ACA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_811 0x410ACAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_812 0x410ACB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_813 0x410ACB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_814 0x410ACB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_815 0x410ACBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_816 0x410ACC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_817 0x410ACC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_818 0x410ACC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_819 0x410ACCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_820 0x410ACD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_821 0x410ACD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_822 0x410ACD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_823 0x410ACDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_824 0x410ACE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_825 0x410ACE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_826 0x410ACE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_827 0x410ACEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_828 0x410ACF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_829 0x410ACF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_830 0x410ACF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_831 0x410ACFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_832 0x410AD00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_833 0x410AD04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_834 0x410AD08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_835 0x410AD0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_836 0x410AD10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_837 0x410AD14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_838 0x410AD18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_839 0x410AD1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_840 0x410AD20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_841 0x410AD24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_842 0x410AD28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_843 0x410AD2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_844 0x410AD30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_845 0x410AD34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_846 0x410AD38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_847 0x410AD3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_848 0x410AD40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_849 0x410AD44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_850 0x410AD48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_851 0x410AD4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_852 0x410AD50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_853 0x410AD54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_854 0x410AD58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_855 0x410AD5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_856 0x410AD60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_857 0x410AD64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_858 0x410AD68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_859 0x410AD6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_860 0x410AD70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_861 0x410AD74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_862 0x410AD78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_863 0x410AD7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_864 0x410AD80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_865 0x410AD84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_866 0x410AD88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_867 0x410AD8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_868 0x410AD90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_869 0x410AD94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_870 0x410AD98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_871 0x410AD9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_872 0x410ADA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_873 0x410ADA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_874 0x410ADA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_875 0x410ADAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_876 0x410ADB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_877 0x410ADB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_878 0x410ADB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_879 0x410ADBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_880 0x410ADC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_881 0x410ADC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_882 0x410ADC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_883 0x410ADCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_884 0x410ADD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_885 0x410ADD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_886 0x410ADD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_887 0x410ADDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_888 0x410ADE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_889 0x410ADE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_890 0x410ADE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_891 0x410ADEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_892 0x410ADF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_893 0x410ADF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_894 0x410ADF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_895 0x410ADFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_896 0x410AE00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_897 0x410AE04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_898 0x410AE08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_899 0x410AE0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_900 0x410AE10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_901 0x410AE14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_902 0x410AE18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_903 0x410AE1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_904 0x410AE20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_905 0x410AE24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_906 0x410AE28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_907 0x410AE2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_908 0x410AE30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_909 0x410AE34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_910 0x410AE38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_911 0x410AE3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_912 0x410AE40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_913 0x410AE44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_914 0x410AE48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_915 0x410AE4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_916 0x410AE50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_917 0x410AE54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_918 0x410AE58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_919 0x410AE5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_920 0x410AE60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_921 0x410AE64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_922 0x410AE68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_923 0x410AE6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_924 0x410AE70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_925 0x410AE74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_926 0x410AE78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_927 0x410AE7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_928 0x410AE80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_929 0x410AE84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_930 0x410AE88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_931 0x410AE8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_932 0x410AE90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_933 0x410AE94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_934 0x410AE98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_935 0x410AE9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_936 0x410AEA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_937 0x410AEA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_938 0x410AEA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_939 0x410AEAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_940 0x410AEB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_941 0x410AEB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_942 0x410AEB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_943 0x410AEBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_944 0x410AEC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_945 0x410AEC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_946 0x410AEC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_947 0x410AECC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_948 0x410AED0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_949 0x410AED4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_950 0x410AED8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_951 0x410AEDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_952 0x410AEE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_953 0x410AEE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_954 0x410AEE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_955 0x410AEEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_956 0x410AEF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_957 0x410AEF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_958 0x410AEF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_959 0x410AEFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_960 0x410AF00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_961 0x410AF04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_962 0x410AF08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_963 0x410AF0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_964 0x410AF10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_965 0x410AF14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_966 0x410AF18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_967 0x410AF1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_968 0x410AF20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_969 0x410AF24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_970 0x410AF28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_971 0x410AF2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_972 0x410AF30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_973 0x410AF34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_974 0x410AF38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_975 0x410AF3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_976 0x410AF40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_977 0x410AF44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_978 0x410AF48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_979 0x410AF4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_980 0x410AF50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_981 0x410AF54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_982 0x410AF58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_983 0x410AF5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_984 0x410AF60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_985 0x410AF64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_986 0x410AF68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_987 0x410AF6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_988 0x410AF70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_989 0x410AF74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_990 0x410AF78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_991 0x410AF7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_992 0x410AF80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_993 0x410AF84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_994 0x410AF88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_995 0x410AF8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_996 0x410AF90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_997 0x410AF94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_998 0x410AF98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_999 0x410AF9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1000 0x410AFA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1001 0x410AFA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1002 0x410AFA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1003 0x410AFAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1004 0x410AFB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1005 0x410AFB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1006 0x410AFB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1007 0x410AFBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1008 0x410AFC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1009 0x410AFC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1010 0x410AFC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1011 0x410AFCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1012 0x410AFD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1013 0x410AFD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1014 0x410AFD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1015 0x410AFDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1016 0x410AFE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1017 0x410AFE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1018 0x410AFE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1019 0x410AFEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1020 0x410AFF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1021 0x410AFF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1022 0x410AFF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1023 0x410AFFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1024 0x410B000
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1025 0x410B004
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1026 0x410B008
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1027 0x410B00C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1028 0x410B010
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1029 0x410B014
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1030 0x410B018
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1031 0x410B01C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1032 0x410B020
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1033 0x410B024
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1034 0x410B028
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1035 0x410B02C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1036 0x410B030
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1037 0x410B034
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1038 0x410B038
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1039 0x410B03C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1040 0x410B040
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1041 0x410B044
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1042 0x410B048
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1043 0x410B04C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1044 0x410B050
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1045 0x410B054
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1046 0x410B058
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1047 0x410B05C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1048 0x410B060
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1049 0x410B064
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1050 0x410B068
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1051 0x410B06C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1052 0x410B070
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1053 0x410B074
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1054 0x410B078
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1055 0x410B07C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1056 0x410B080
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1057 0x410B084
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1058 0x410B088
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1059 0x410B08C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1060 0x410B090
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1061 0x410B094
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1062 0x410B098
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1063 0x410B09C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1064 0x410B0A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1065 0x410B0A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1066 0x410B0A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1067 0x410B0AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1068 0x410B0B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1069 0x410B0B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1070 0x410B0B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1071 0x410B0BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1072 0x410B0C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1073 0x410B0C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1074 0x410B0C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1075 0x410B0CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1076 0x410B0D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1077 0x410B0D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1078 0x410B0D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1079 0x410B0DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1080 0x410B0E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1081 0x410B0E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1082 0x410B0E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1083 0x410B0EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1084 0x410B0F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1085 0x410B0F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1086 0x410B0F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1087 0x410B0FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1088 0x410B100
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1089 0x410B104
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1090 0x410B108
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1091 0x410B10C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1092 0x410B110
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1093 0x410B114
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1094 0x410B118
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1095 0x410B11C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1096 0x410B120
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1097 0x410B124
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1098 0x410B128
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1099 0x410B12C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1100 0x410B130
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1101 0x410B134
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1102 0x410B138
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1103 0x410B13C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1104 0x410B140
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1105 0x410B144
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1106 0x410B148
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1107 0x410B14C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1108 0x410B150
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1109 0x410B154
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1110 0x410B158
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1111 0x410B15C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1112 0x410B160
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1113 0x410B164
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1114 0x410B168
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1115 0x410B16C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1116 0x410B170
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1117 0x410B174
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1118 0x410B178
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1119 0x410B17C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1120 0x410B180
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1121 0x410B184
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1122 0x410B188
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1123 0x410B18C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1124 0x410B190
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1125 0x410B194
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1126 0x410B198
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1127 0x410B19C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1128 0x410B1A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1129 0x410B1A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1130 0x410B1A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1131 0x410B1AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1132 0x410B1B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1133 0x410B1B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1134 0x410B1B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1135 0x410B1BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1136 0x410B1C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1137 0x410B1C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1138 0x410B1C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1139 0x410B1CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1140 0x410B1D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1141 0x410B1D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1142 0x410B1D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1143 0x410B1DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1144 0x410B1E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1145 0x410B1E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1146 0x410B1E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1147 0x410B1EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1148 0x410B1F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1149 0x410B1F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1150 0x410B1F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1151 0x410B1FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1152 0x410B200
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1153 0x410B204
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1154 0x410B208
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1155 0x410B20C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1156 0x410B210
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1157 0x410B214
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1158 0x410B218
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1159 0x410B21C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1160 0x410B220
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1161 0x410B224
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1162 0x410B228
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1163 0x410B22C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1164 0x410B230
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1165 0x410B234
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1166 0x410B238
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1167 0x410B23C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1168 0x410B240
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1169 0x410B244
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1170 0x410B248
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1171 0x410B24C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1172 0x410B250
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1173 0x410B254
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1174 0x410B258
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1175 0x410B25C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1176 0x410B260
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1177 0x410B264
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1178 0x410B268
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1179 0x410B26C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1180 0x410B270
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1181 0x410B274
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1182 0x410B278
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1183 0x410B27C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1184 0x410B280
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1185 0x410B284
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1186 0x410B288
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1187 0x410B28C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1188 0x410B290
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1189 0x410B294
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1190 0x410B298
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1191 0x410B29C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1192 0x410B2A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1193 0x410B2A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1194 0x410B2A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1195 0x410B2AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1196 0x410B2B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1197 0x410B2B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1198 0x410B2B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1199 0x410B2BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1200 0x410B2C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1201 0x410B2C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1202 0x410B2C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1203 0x410B2CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1204 0x410B2D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1205 0x410B2D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1206 0x410B2D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1207 0x410B2DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1208 0x410B2E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1209 0x410B2E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1210 0x410B2E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1211 0x410B2EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1212 0x410B2F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1213 0x410B2F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1214 0x410B2F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1215 0x410B2FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1216 0x410B300
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1217 0x410B304
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1218 0x410B308
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1219 0x410B30C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1220 0x410B310
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1221 0x410B314
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1222 0x410B318
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1223 0x410B31C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1224 0x410B320
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1225 0x410B324
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1226 0x410B328
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1227 0x410B32C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1228 0x410B330
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1229 0x410B334
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1230 0x410B338
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1231 0x410B33C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1232 0x410B340
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1233 0x410B344
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1234 0x410B348
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1235 0x410B34C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1236 0x410B350
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1237 0x410B354
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1238 0x410B358
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1239 0x410B35C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1240 0x410B360
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1241 0x410B364
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1242 0x410B368
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1243 0x410B36C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1244 0x410B370
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1245 0x410B374
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1246 0x410B378
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1247 0x410B37C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1248 0x410B380
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1249 0x410B384
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1250 0x410B388
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1251 0x410B38C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1252 0x410B390
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1253 0x410B394
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1254 0x410B398
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1255 0x410B39C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1256 0x410B3A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1257 0x410B3A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1258 0x410B3A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1259 0x410B3AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1260 0x410B3B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1261 0x410B3B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1262 0x410B3B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1263 0x410B3BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1264 0x410B3C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1265 0x410B3C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1266 0x410B3C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1267 0x410B3CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1268 0x410B3D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1269 0x410B3D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1270 0x410B3D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1271 0x410B3DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1272 0x410B3E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1273 0x410B3E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1274 0x410B3E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1275 0x410B3EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1276 0x410B3F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1277 0x410B3F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1278 0x410B3F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1279 0x410B3FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1280 0x410B400
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1281 0x410B404
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1282 0x410B408
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1283 0x410B40C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1284 0x410B410
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1285 0x410B414
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1286 0x410B418
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1287 0x410B41C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1288 0x410B420
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1289 0x410B424
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1290 0x410B428
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1291 0x410B42C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1292 0x410B430
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1293 0x410B434
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1294 0x410B438
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1295 0x410B43C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1296 0x410B440
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1297 0x410B444
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1298 0x410B448
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1299 0x410B44C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1300 0x410B450
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1301 0x410B454
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1302 0x410B458
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1303 0x410B45C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1304 0x410B460
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1305 0x410B464
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1306 0x410B468
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1307 0x410B46C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1308 0x410B470
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1309 0x410B474
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1310 0x410B478
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1311 0x410B47C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1312 0x410B480
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1313 0x410B484
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1314 0x410B488
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1315 0x410B48C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1316 0x410B490
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1317 0x410B494
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1318 0x410B498
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1319 0x410B49C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1320 0x410B4A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1321 0x410B4A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1322 0x410B4A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1323 0x410B4AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1324 0x410B4B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1325 0x410B4B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1326 0x410B4B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1327 0x410B4BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1328 0x410B4C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1329 0x410B4C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1330 0x410B4C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1331 0x410B4CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1332 0x410B4D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1333 0x410B4D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1334 0x410B4D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1335 0x410B4DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1336 0x410B4E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1337 0x410B4E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1338 0x410B4E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1339 0x410B4EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1340 0x410B4F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1341 0x410B4F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1342 0x410B4F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1343 0x410B4FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1344 0x410B500
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1345 0x410B504
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1346 0x410B508
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1347 0x410B50C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1348 0x410B510
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1349 0x410B514
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1350 0x410B518
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1351 0x410B51C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1352 0x410B520
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1353 0x410B524
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1354 0x410B528
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1355 0x410B52C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1356 0x410B530
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1357 0x410B534
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1358 0x410B538
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1359 0x410B53C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1360 0x410B540
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1361 0x410B544
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1362 0x410B548
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1363 0x410B54C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1364 0x410B550
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1365 0x410B554
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1366 0x410B558
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1367 0x410B55C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1368 0x410B560
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1369 0x410B564
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1370 0x410B568
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1371 0x410B56C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1372 0x410B570
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1373 0x410B574
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1374 0x410B578
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1375 0x410B57C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1376 0x410B580
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1377 0x410B584
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1378 0x410B588
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1379 0x410B58C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1380 0x410B590
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1381 0x410B594
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1382 0x410B598
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1383 0x410B59C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1384 0x410B5A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1385 0x410B5A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1386 0x410B5A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1387 0x410B5AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1388 0x410B5B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1389 0x410B5B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1390 0x410B5B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1391 0x410B5BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1392 0x410B5C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1393 0x410B5C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1394 0x410B5C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1395 0x410B5CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1396 0x410B5D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1397 0x410B5D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1398 0x410B5D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1399 0x410B5DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1400 0x410B5E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1401 0x410B5E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1402 0x410B5E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1403 0x410B5EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1404 0x410B5F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1405 0x410B5F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1406 0x410B5F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1407 0x410B5FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1408 0x410B600
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1409 0x410B604
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1410 0x410B608
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1411 0x410B60C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1412 0x410B610
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1413 0x410B614
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1414 0x410B618
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1415 0x410B61C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1416 0x410B620
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1417 0x410B624
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1418 0x410B628
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1419 0x410B62C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1420 0x410B630
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1421 0x410B634
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1422 0x410B638
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1423 0x410B63C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1424 0x410B640
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1425 0x410B644
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1426 0x410B648
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1427 0x410B64C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1428 0x410B650
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1429 0x410B654
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1430 0x410B658
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1431 0x410B65C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1432 0x410B660
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1433 0x410B664
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1434 0x410B668
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1435 0x410B66C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1436 0x410B670
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1437 0x410B674
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1438 0x410B678
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1439 0x410B67C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1440 0x410B680
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1441 0x410B684
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1442 0x410B688
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1443 0x410B68C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1444 0x410B690
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1445 0x410B694
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1446 0x410B698
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1447 0x410B69C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1448 0x410B6A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1449 0x410B6A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1450 0x410B6A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1451 0x410B6AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1452 0x410B6B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1453 0x410B6B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1454 0x410B6B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1455 0x410B6BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1456 0x410B6C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1457 0x410B6C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1458 0x410B6C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1459 0x410B6CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1460 0x410B6D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1461 0x410B6D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1462 0x410B6D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1463 0x410B6DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1464 0x410B6E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1465 0x410B6E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1466 0x410B6E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1467 0x410B6EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1468 0x410B6F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1469 0x410B6F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1470 0x410B6F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1471 0x410B6FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1472 0x410B700
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1473 0x410B704
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1474 0x410B708
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1475 0x410B70C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1476 0x410B710
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1477 0x410B714
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1478 0x410B718
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1479 0x410B71C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1480 0x410B720
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1481 0x410B724
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1482 0x410B728
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1483 0x410B72C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1484 0x410B730
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1485 0x410B734
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1486 0x410B738
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1487 0x410B73C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1488 0x410B740
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1489 0x410B744
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1490 0x410B748
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1491 0x410B74C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1492 0x410B750
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1493 0x410B754
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1494 0x410B758
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1495 0x410B75C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1496 0x410B760
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1497 0x410B764
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1498 0x410B768
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1499 0x410B76C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1500 0x410B770
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1501 0x410B774
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1502 0x410B778
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1503 0x410B77C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1504 0x410B780
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1505 0x410B784
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1506 0x410B788
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1507 0x410B78C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1508 0x410B790
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1509 0x410B794
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1510 0x410B798
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1511 0x410B79C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1512 0x410B7A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1513 0x410B7A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1514 0x410B7A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1515 0x410B7AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1516 0x410B7B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1517 0x410B7B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1518 0x410B7B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1519 0x410B7BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1520 0x410B7C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1521 0x410B7C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1522 0x410B7C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1523 0x410B7CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1524 0x410B7D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1525 0x410B7D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1526 0x410B7D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1527 0x410B7DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1528 0x410B7E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1529 0x410B7E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1530 0x410B7E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1531 0x410B7EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1532 0x410B7F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1533 0x410B7F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1534 0x410B7F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1535 0x410B7FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1536 0x410B800
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1537 0x410B804
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1538 0x410B808
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1539 0x410B80C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1540 0x410B810
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1541 0x410B814
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1542 0x410B818
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1543 0x410B81C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1544 0x410B820
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1545 0x410B824
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1546 0x410B828
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1547 0x410B82C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1548 0x410B830
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1549 0x410B834
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1550 0x410B838
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1551 0x410B83C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1552 0x410B840
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1553 0x410B844
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1554 0x410B848
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1555 0x410B84C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1556 0x410B850
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1557 0x410B854
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1558 0x410B858
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1559 0x410B85C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1560 0x410B860
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1561 0x410B864
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1562 0x410B868
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1563 0x410B86C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1564 0x410B870
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1565 0x410B874
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1566 0x410B878
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1567 0x410B87C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1568 0x410B880
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1569 0x410B884
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1570 0x410B888
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1571 0x410B88C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1572 0x410B890
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1573 0x410B894
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1574 0x410B898
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1575 0x410B89C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1576 0x410B8A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1577 0x410B8A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1578 0x410B8A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1579 0x410B8AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1580 0x410B8B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1581 0x410B8B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1582 0x410B8B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1583 0x410B8BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1584 0x410B8C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1585 0x410B8C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1586 0x410B8C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1587 0x410B8CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1588 0x410B8D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1589 0x410B8D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1590 0x410B8D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1591 0x410B8DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1592 0x410B8E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1593 0x410B8E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1594 0x410B8E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1595 0x410B8EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1596 0x410B8F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1597 0x410B8F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1598 0x410B8F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1599 0x410B8FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1600 0x410B900
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1601 0x410B904
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1602 0x410B908
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1603 0x410B90C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1604 0x410B910
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1605 0x410B914
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1606 0x410B918
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1607 0x410B91C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1608 0x410B920
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1609 0x410B924
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1610 0x410B928
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1611 0x410B92C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1612 0x410B930
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1613 0x410B934
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1614 0x410B938
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1615 0x410B93C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1616 0x410B940
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1617 0x410B944
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1618 0x410B948
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1619 0x410B94C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1620 0x410B950
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1621 0x410B954
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1622 0x410B958
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1623 0x410B95C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1624 0x410B960
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1625 0x410B964
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1626 0x410B968
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1627 0x410B96C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1628 0x410B970
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1629 0x410B974
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1630 0x410B978
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1631 0x410B97C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1632 0x410B980
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1633 0x410B984
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1634 0x410B988
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1635 0x410B98C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1636 0x410B990
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1637 0x410B994
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1638 0x410B998
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1639 0x410B99C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1640 0x410B9A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1641 0x410B9A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1642 0x410B9A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1643 0x410B9AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1644 0x410B9B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1645 0x410B9B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1646 0x410B9B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1647 0x410B9BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1648 0x410B9C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1649 0x410B9C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1650 0x410B9C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1651 0x410B9CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1652 0x410B9D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1653 0x410B9D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1654 0x410B9D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1655 0x410B9DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1656 0x410B9E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1657 0x410B9E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1658 0x410B9E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1659 0x410B9EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1660 0x410B9F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1661 0x410B9F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1662 0x410B9F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1663 0x410B9FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1664 0x410BA00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1665 0x410BA04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1666 0x410BA08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1667 0x410BA0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1668 0x410BA10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1669 0x410BA14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1670 0x410BA18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1671 0x410BA1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1672 0x410BA20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1673 0x410BA24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1674 0x410BA28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1675 0x410BA2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1676 0x410BA30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1677 0x410BA34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1678 0x410BA38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1679 0x410BA3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1680 0x410BA40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1681 0x410BA44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1682 0x410BA48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1683 0x410BA4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1684 0x410BA50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1685 0x410BA54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1686 0x410BA58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1687 0x410BA5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1688 0x410BA60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1689 0x410BA64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1690 0x410BA68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1691 0x410BA6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1692 0x410BA70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1693 0x410BA74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1694 0x410BA78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1695 0x410BA7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1696 0x410BA80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1697 0x410BA84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1698 0x410BA88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1699 0x410BA8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1700 0x410BA90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1701 0x410BA94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1702 0x410BA98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1703 0x410BA9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1704 0x410BAA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1705 0x410BAA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1706 0x410BAA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1707 0x410BAAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1708 0x410BAB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1709 0x410BAB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1710 0x410BAB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1711 0x410BABC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1712 0x410BAC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1713 0x410BAC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1714 0x410BAC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1715 0x410BACC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1716 0x410BAD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1717 0x410BAD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1718 0x410BAD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1719 0x410BADC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1720 0x410BAE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1721 0x410BAE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1722 0x410BAE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1723 0x410BAEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1724 0x410BAF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1725 0x410BAF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1726 0x410BAF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1727 0x410BAFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1728 0x410BB00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1729 0x410BB04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1730 0x410BB08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1731 0x410BB0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1732 0x410BB10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1733 0x410BB14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1734 0x410BB18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1735 0x410BB1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1736 0x410BB20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1737 0x410BB24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1738 0x410BB28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1739 0x410BB2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1740 0x410BB30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1741 0x410BB34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1742 0x410BB38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1743 0x410BB3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1744 0x410BB40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1745 0x410BB44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1746 0x410BB48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1747 0x410BB4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1748 0x410BB50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1749 0x410BB54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1750 0x410BB58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1751 0x410BB5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1752 0x410BB60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1753 0x410BB64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1754 0x410BB68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1755 0x410BB6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1756 0x410BB70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1757 0x410BB74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1758 0x410BB78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1759 0x410BB7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1760 0x410BB80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1761 0x410BB84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1762 0x410BB88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1763 0x410BB8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1764 0x410BB90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1765 0x410BB94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1766 0x410BB98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1767 0x410BB9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1768 0x410BBA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1769 0x410BBA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1770 0x410BBA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1771 0x410BBAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1772 0x410BBB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1773 0x410BBB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1774 0x410BBB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1775 0x410BBBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1776 0x410BBC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1777 0x410BBC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1778 0x410BBC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1779 0x410BBCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1780 0x410BBD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1781 0x410BBD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1782 0x410BBD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1783 0x410BBDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1784 0x410BBE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1785 0x410BBE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1786 0x410BBE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1787 0x410BBEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1788 0x410BBF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1789 0x410BBF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1790 0x410BBF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1791 0x410BBFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1792 0x410BC00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1793 0x410BC04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1794 0x410BC08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1795 0x410BC0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1796 0x410BC10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1797 0x410BC14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1798 0x410BC18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1799 0x410BC1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1800 0x410BC20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1801 0x410BC24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1802 0x410BC28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1803 0x410BC2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1804 0x410BC30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1805 0x410BC34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1806 0x410BC38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1807 0x410BC3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1808 0x410BC40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1809 0x410BC44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1810 0x410BC48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1811 0x410BC4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1812 0x410BC50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1813 0x410BC54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1814 0x410BC58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1815 0x410BC5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1816 0x410BC60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1817 0x410BC64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1818 0x410BC68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1819 0x410BC6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1820 0x410BC70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1821 0x410BC74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1822 0x410BC78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1823 0x410BC7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1824 0x410BC80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1825 0x410BC84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1826 0x410BC88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1827 0x410BC8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1828 0x410BC90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1829 0x410BC94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1830 0x410BC98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1831 0x410BC9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1832 0x410BCA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1833 0x410BCA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1834 0x410BCA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1835 0x410BCAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1836 0x410BCB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1837 0x410BCB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1838 0x410BCB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1839 0x410BCBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1840 0x410BCC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1841 0x410BCC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1842 0x410BCC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1843 0x410BCCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1844 0x410BCD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1845 0x410BCD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1846 0x410BCD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1847 0x410BCDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1848 0x410BCE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1849 0x410BCE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1850 0x410BCE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1851 0x410BCEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1852 0x410BCF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1853 0x410BCF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1854 0x410BCF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1855 0x410BCFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1856 0x410BD00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1857 0x410BD04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1858 0x410BD08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1859 0x410BD0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1860 0x410BD10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1861 0x410BD14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1862 0x410BD18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1863 0x410BD1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1864 0x410BD20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1865 0x410BD24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1866 0x410BD28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1867 0x410BD2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1868 0x410BD30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1869 0x410BD34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1870 0x410BD38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1871 0x410BD3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1872 0x410BD40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1873 0x410BD44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1874 0x410BD48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1875 0x410BD4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1876 0x410BD50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1877 0x410BD54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1878 0x410BD58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1879 0x410BD5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1880 0x410BD60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1881 0x410BD64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1882 0x410BD68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1883 0x410BD6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1884 0x410BD70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1885 0x410BD74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1886 0x410BD78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1887 0x410BD7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1888 0x410BD80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1889 0x410BD84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1890 0x410BD88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1891 0x410BD8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1892 0x410BD90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1893 0x410BD94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1894 0x410BD98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1895 0x410BD9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1896 0x410BDA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1897 0x410BDA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1898 0x410BDA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1899 0x410BDAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1900 0x410BDB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1901 0x410BDB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1902 0x410BDB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1903 0x410BDBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1904 0x410BDC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1905 0x410BDC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1906 0x410BDC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1907 0x410BDCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1908 0x410BDD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1909 0x410BDD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1910 0x410BDD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1911 0x410BDDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1912 0x410BDE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1913 0x410BDE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1914 0x410BDE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1915 0x410BDEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1916 0x410BDF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1917 0x410BDF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1918 0x410BDF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1919 0x410BDFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1920 0x410BE00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1921 0x410BE04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1922 0x410BE08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1923 0x410BE0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1924 0x410BE10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1925 0x410BE14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1926 0x410BE18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1927 0x410BE1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1928 0x410BE20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1929 0x410BE24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1930 0x410BE28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1931 0x410BE2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1932 0x410BE30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1933 0x410BE34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1934 0x410BE38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1935 0x410BE3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1936 0x410BE40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1937 0x410BE44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1938 0x410BE48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1939 0x410BE4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1940 0x410BE50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1941 0x410BE54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1942 0x410BE58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1943 0x410BE5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1944 0x410BE60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1945 0x410BE64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1946 0x410BE68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1947 0x410BE6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1948 0x410BE70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1949 0x410BE74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1950 0x410BE78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1951 0x410BE7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1952 0x410BE80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1953 0x410BE84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1954 0x410BE88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1955 0x410BE8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1956 0x410BE90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1957 0x410BE94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1958 0x410BE98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1959 0x410BE9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1960 0x410BEA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1961 0x410BEA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1962 0x410BEA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1963 0x410BEAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1964 0x410BEB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1965 0x410BEB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1966 0x410BEB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1967 0x410BEBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1968 0x410BEC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1969 0x410BEC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1970 0x410BEC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1971 0x410BECC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1972 0x410BED0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1973 0x410BED4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1974 0x410BED8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1975 0x410BEDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1976 0x410BEE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1977 0x410BEE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1978 0x410BEE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1979 0x410BEEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1980 0x410BEF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1981 0x410BEF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1982 0x410BEF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1983 0x410BEFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1984 0x410BF00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1985 0x410BF04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1986 0x410BF08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1987 0x410BF0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1988 0x410BF10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1989 0x410BF14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1990 0x410BF18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1991 0x410BF1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1992 0x410BF20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1993 0x410BF24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1994 0x410BF28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1995 0x410BF2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1996 0x410BF30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1997 0x410BF34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1998 0x410BF38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_1999 0x410BF3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2000 0x410BF40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2001 0x410BF44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2002 0x410BF48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2003 0x410BF4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2004 0x410BF50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2005 0x410BF54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2006 0x410BF58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2007 0x410BF5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2008 0x410BF60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2009 0x410BF64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2010 0x410BF68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2011 0x410BF6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2012 0x410BF70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2013 0x410BF74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2014 0x410BF78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2015 0x410BF7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2016 0x410BF80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2017 0x410BF84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2018 0x410BF88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2019 0x410BF8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2020 0x410BF90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2021 0x410BF94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2022 0x410BF98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2023 0x410BF9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2024 0x410BFA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2025 0x410BFA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2026 0x410BFA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2027 0x410BFAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2028 0x410BFB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2029 0x410BFB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2030 0x410BFB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2031 0x410BFBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2032 0x410BFC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2033 0x410BFC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2034 0x410BFC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2035 0x410BFCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2036 0x410BFD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2037 0x410BFD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2038 0x410BFD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2039 0x410BFDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2040 0x410BFE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2041 0x410BFE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2042 0x410BFE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2043 0x410BFEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2044 0x410BFF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2045 0x410BFF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2046 0x410BFF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_2047 0x410BFFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_0 0x410C000
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1 0x410C004
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2 0x410C008
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_3 0x410C00C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_4 0x410C010
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_5 0x410C014
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_6 0x410C018
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_7 0x410C01C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_8 0x410C020
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_9 0x410C024
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_10 0x410C028
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_11 0x410C02C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_12 0x410C030
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_13 0x410C034
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_14 0x410C038
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_15 0x410C03C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_16 0x410C040
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_17 0x410C044
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_18 0x410C048
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_19 0x410C04C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_20 0x410C050
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_21 0x410C054
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_22 0x410C058
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_23 0x410C05C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_24 0x410C060
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_25 0x410C064
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_26 0x410C068
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_27 0x410C06C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_28 0x410C070
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_29 0x410C074
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_30 0x410C078
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_31 0x410C07C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_32 0x410C080
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_33 0x410C084
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_34 0x410C088
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_35 0x410C08C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_36 0x410C090
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_37 0x410C094
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_38 0x410C098
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_39 0x410C09C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_40 0x410C0A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_41 0x410C0A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_42 0x410C0A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_43 0x410C0AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_44 0x410C0B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_45 0x410C0B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_46 0x410C0B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_47 0x410C0BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_48 0x410C0C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_49 0x410C0C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_50 0x410C0C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_51 0x410C0CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_52 0x410C0D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_53 0x410C0D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_54 0x410C0D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_55 0x410C0DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_56 0x410C0E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_57 0x410C0E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_58 0x410C0E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_59 0x410C0EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_60 0x410C0F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_61 0x410C0F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_62 0x410C0F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_63 0x410C0FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_64 0x410C100
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_65 0x410C104
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_66 0x410C108
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_67 0x410C10C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_68 0x410C110
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_69 0x410C114
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_70 0x410C118
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_71 0x410C11C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_72 0x410C120
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_73 0x410C124
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_74 0x410C128
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_75 0x410C12C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_76 0x410C130
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_77 0x410C134
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_78 0x410C138
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_79 0x410C13C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_80 0x410C140
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_81 0x410C144
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_82 0x410C148
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_83 0x410C14C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_84 0x410C150
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_85 0x410C154
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_86 0x410C158
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_87 0x410C15C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_88 0x410C160
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_89 0x410C164
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_90 0x410C168
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_91 0x410C16C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_92 0x410C170
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_93 0x410C174
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_94 0x410C178
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_95 0x410C17C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_96 0x410C180
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_97 0x410C184
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_98 0x410C188
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_99 0x410C18C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_100 0x410C190
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_101 0x410C194
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_102 0x410C198
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_103 0x410C19C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_104 0x410C1A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_105 0x410C1A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_106 0x410C1A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_107 0x410C1AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_108 0x410C1B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_109 0x410C1B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_110 0x410C1B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_111 0x410C1BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_112 0x410C1C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_113 0x410C1C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_114 0x410C1C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_115 0x410C1CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_116 0x410C1D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_117 0x410C1D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_118 0x410C1D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_119 0x410C1DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_120 0x410C1E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_121 0x410C1E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_122 0x410C1E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_123 0x410C1EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_124 0x410C1F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_125 0x410C1F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_126 0x410C1F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_127 0x410C1FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_128 0x410C200
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_129 0x410C204
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_130 0x410C208
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_131 0x410C20C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_132 0x410C210
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_133 0x410C214
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_134 0x410C218
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_135 0x410C21C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_136 0x410C220
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_137 0x410C224
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_138 0x410C228
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_139 0x410C22C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_140 0x410C230
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_141 0x410C234
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_142 0x410C238
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_143 0x410C23C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_144 0x410C240
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_145 0x410C244
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_146 0x410C248
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_147 0x410C24C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_148 0x410C250
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_149 0x410C254
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_150 0x410C258
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_151 0x410C25C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_152 0x410C260
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_153 0x410C264
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_154 0x410C268
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_155 0x410C26C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_156 0x410C270
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_157 0x410C274
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_158 0x410C278
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_159 0x410C27C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_160 0x410C280
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_161 0x410C284
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_162 0x410C288
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_163 0x410C28C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_164 0x410C290
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_165 0x410C294
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_166 0x410C298
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_167 0x410C29C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_168 0x410C2A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_169 0x410C2A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_170 0x410C2A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_171 0x410C2AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_172 0x410C2B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_173 0x410C2B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_174 0x410C2B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_175 0x410C2BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_176 0x410C2C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_177 0x410C2C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_178 0x410C2C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_179 0x410C2CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_180 0x410C2D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_181 0x410C2D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_182 0x410C2D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_183 0x410C2DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_184 0x410C2E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_185 0x410C2E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_186 0x410C2E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_187 0x410C2EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_188 0x410C2F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_189 0x410C2F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_190 0x410C2F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_191 0x410C2FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_192 0x410C300
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_193 0x410C304
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_194 0x410C308
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_195 0x410C30C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_196 0x410C310
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_197 0x410C314
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_198 0x410C318
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_199 0x410C31C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_200 0x410C320
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_201 0x410C324
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_202 0x410C328
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_203 0x410C32C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_204 0x410C330
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_205 0x410C334
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_206 0x410C338
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_207 0x410C33C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_208 0x410C340
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_209 0x410C344
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_210 0x410C348
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_211 0x410C34C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_212 0x410C350
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_213 0x410C354
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_214 0x410C358
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_215 0x410C35C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_216 0x410C360
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_217 0x410C364
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_218 0x410C368
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_219 0x410C36C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_220 0x410C370
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_221 0x410C374
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_222 0x410C378
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_223 0x410C37C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_224 0x410C380
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_225 0x410C384
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_226 0x410C388
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_227 0x410C38C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_228 0x410C390
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_229 0x410C394
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_230 0x410C398
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_231 0x410C39C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_232 0x410C3A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_233 0x410C3A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_234 0x410C3A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_235 0x410C3AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_236 0x410C3B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_237 0x410C3B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_238 0x410C3B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_239 0x410C3BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_240 0x410C3C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_241 0x410C3C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_242 0x410C3C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_243 0x410C3CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_244 0x410C3D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_245 0x410C3D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_246 0x410C3D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_247 0x410C3DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_248 0x410C3E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_249 0x410C3E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_250 0x410C3E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_251 0x410C3EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_252 0x410C3F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_253 0x410C3F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_254 0x410C3F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_255 0x410C3FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_256 0x410C400
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_257 0x410C404
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_258 0x410C408
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_259 0x410C40C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_260 0x410C410
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_261 0x410C414
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_262 0x410C418
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_263 0x410C41C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_264 0x410C420
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_265 0x410C424
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_266 0x410C428
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_267 0x410C42C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_268 0x410C430
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_269 0x410C434
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_270 0x410C438
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_271 0x410C43C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_272 0x410C440
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_273 0x410C444
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_274 0x410C448
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_275 0x410C44C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_276 0x410C450
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_277 0x410C454
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_278 0x410C458
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_279 0x410C45C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_280 0x410C460
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_281 0x410C464
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_282 0x410C468
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_283 0x410C46C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_284 0x410C470
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_285 0x410C474
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_286 0x410C478
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_287 0x410C47C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_288 0x410C480
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_289 0x410C484
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_290 0x410C488
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_291 0x410C48C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_292 0x410C490
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_293 0x410C494
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_294 0x410C498
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_295 0x410C49C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_296 0x410C4A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_297 0x410C4A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_298 0x410C4A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_299 0x410C4AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_300 0x410C4B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_301 0x410C4B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_302 0x410C4B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_303 0x410C4BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_304 0x410C4C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_305 0x410C4C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_306 0x410C4C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_307 0x410C4CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_308 0x410C4D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_309 0x410C4D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_310 0x410C4D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_311 0x410C4DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_312 0x410C4E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_313 0x410C4E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_314 0x410C4E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_315 0x410C4EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_316 0x410C4F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_317 0x410C4F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_318 0x410C4F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_319 0x410C4FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_320 0x410C500
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_321 0x410C504
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_322 0x410C508
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_323 0x410C50C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_324 0x410C510
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_325 0x410C514
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_326 0x410C518
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_327 0x410C51C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_328 0x410C520
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_329 0x410C524
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_330 0x410C528
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_331 0x410C52C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_332 0x410C530
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_333 0x410C534
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_334 0x410C538
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_335 0x410C53C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_336 0x410C540
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_337 0x410C544
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_338 0x410C548
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_339 0x410C54C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_340 0x410C550
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_341 0x410C554
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_342 0x410C558
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_343 0x410C55C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_344 0x410C560
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_345 0x410C564
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_346 0x410C568
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_347 0x410C56C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_348 0x410C570
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_349 0x410C574
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_350 0x410C578
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_351 0x410C57C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_352 0x410C580
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_353 0x410C584
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_354 0x410C588
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_355 0x410C58C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_356 0x410C590
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_357 0x410C594
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_358 0x410C598
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_359 0x410C59C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_360 0x410C5A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_361 0x410C5A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_362 0x410C5A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_363 0x410C5AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_364 0x410C5B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_365 0x410C5B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_366 0x410C5B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_367 0x410C5BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_368 0x410C5C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_369 0x410C5C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_370 0x410C5C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_371 0x410C5CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_372 0x410C5D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_373 0x410C5D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_374 0x410C5D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_375 0x410C5DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_376 0x410C5E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_377 0x410C5E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_378 0x410C5E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_379 0x410C5EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_380 0x410C5F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_381 0x410C5F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_382 0x410C5F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_383 0x410C5FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_384 0x410C600
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_385 0x410C604
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_386 0x410C608
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_387 0x410C60C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_388 0x410C610
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_389 0x410C614
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_390 0x410C618
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_391 0x410C61C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_392 0x410C620
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_393 0x410C624
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_394 0x410C628
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_395 0x410C62C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_396 0x410C630
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_397 0x410C634
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_398 0x410C638
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_399 0x410C63C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_400 0x410C640
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_401 0x410C644
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_402 0x410C648
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_403 0x410C64C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_404 0x410C650
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_405 0x410C654
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_406 0x410C658
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_407 0x410C65C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_408 0x410C660
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_409 0x410C664
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_410 0x410C668
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_411 0x410C66C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_412 0x410C670
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_413 0x410C674
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_414 0x410C678
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_415 0x410C67C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_416 0x410C680
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_417 0x410C684
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_418 0x410C688
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_419 0x410C68C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_420 0x410C690
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_421 0x410C694
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_422 0x410C698
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_423 0x410C69C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_424 0x410C6A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_425 0x410C6A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_426 0x410C6A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_427 0x410C6AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_428 0x410C6B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_429 0x410C6B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_430 0x410C6B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_431 0x410C6BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_432 0x410C6C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_433 0x410C6C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_434 0x410C6C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_435 0x410C6CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_436 0x410C6D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_437 0x410C6D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_438 0x410C6D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_439 0x410C6DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_440 0x410C6E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_441 0x410C6E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_442 0x410C6E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_443 0x410C6EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_444 0x410C6F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_445 0x410C6F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_446 0x410C6F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_447 0x410C6FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_448 0x410C700
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_449 0x410C704
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_450 0x410C708
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_451 0x410C70C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_452 0x410C710
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_453 0x410C714
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_454 0x410C718
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_455 0x410C71C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_456 0x410C720
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_457 0x410C724
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_458 0x410C728
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_459 0x410C72C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_460 0x410C730
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_461 0x410C734
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_462 0x410C738
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_463 0x410C73C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_464 0x410C740
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_465 0x410C744
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_466 0x410C748
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_467 0x410C74C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_468 0x410C750
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_469 0x410C754
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_470 0x410C758
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_471 0x410C75C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_472 0x410C760
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_473 0x410C764
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_474 0x410C768
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_475 0x410C76C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_476 0x410C770
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_477 0x410C774
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_478 0x410C778
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_479 0x410C77C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_480 0x410C780
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_481 0x410C784
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_482 0x410C788
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_483 0x410C78C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_484 0x410C790
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_485 0x410C794
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_486 0x410C798
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_487 0x410C79C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_488 0x410C7A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_489 0x410C7A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_490 0x410C7A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_491 0x410C7AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_492 0x410C7B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_493 0x410C7B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_494 0x410C7B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_495 0x410C7BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_496 0x410C7C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_497 0x410C7C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_498 0x410C7C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_499 0x410C7CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_500 0x410C7D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_501 0x410C7D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_502 0x410C7D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_503 0x410C7DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_504 0x410C7E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_505 0x410C7E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_506 0x410C7E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_507 0x410C7EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_508 0x410C7F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_509 0x410C7F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_510 0x410C7F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_511 0x410C7FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_512 0x410C800
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_513 0x410C804
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_514 0x410C808
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_515 0x410C80C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_516 0x410C810
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_517 0x410C814
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_518 0x410C818
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_519 0x410C81C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_520 0x410C820
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_521 0x410C824
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_522 0x410C828
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_523 0x410C82C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_524 0x410C830
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_525 0x410C834
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_526 0x410C838
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_527 0x410C83C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_528 0x410C840
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_529 0x410C844
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_530 0x410C848
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_531 0x410C84C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_532 0x410C850
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_533 0x410C854
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_534 0x410C858
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_535 0x410C85C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_536 0x410C860
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_537 0x410C864
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_538 0x410C868
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_539 0x410C86C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_540 0x410C870
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_541 0x410C874
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_542 0x410C878
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_543 0x410C87C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_544 0x410C880
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_545 0x410C884
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_546 0x410C888
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_547 0x410C88C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_548 0x410C890
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_549 0x410C894
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_550 0x410C898
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_551 0x410C89C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_552 0x410C8A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_553 0x410C8A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_554 0x410C8A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_555 0x410C8AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_556 0x410C8B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_557 0x410C8B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_558 0x410C8B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_559 0x410C8BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_560 0x410C8C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_561 0x410C8C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_562 0x410C8C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_563 0x410C8CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_564 0x410C8D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_565 0x410C8D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_566 0x410C8D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_567 0x410C8DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_568 0x410C8E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_569 0x410C8E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_570 0x410C8E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_571 0x410C8EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_572 0x410C8F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_573 0x410C8F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_574 0x410C8F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_575 0x410C8FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_576 0x410C900
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_577 0x410C904
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_578 0x410C908
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_579 0x410C90C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_580 0x410C910
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_581 0x410C914
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_582 0x410C918
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_583 0x410C91C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_584 0x410C920
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_585 0x410C924
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_586 0x410C928
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_587 0x410C92C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_588 0x410C930
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_589 0x410C934
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_590 0x410C938
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_591 0x410C93C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_592 0x410C940
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_593 0x410C944
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_594 0x410C948
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_595 0x410C94C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_596 0x410C950
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_597 0x410C954
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_598 0x410C958
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_599 0x410C95C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_600 0x410C960
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_601 0x410C964
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_602 0x410C968
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_603 0x410C96C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_604 0x410C970
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_605 0x410C974
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_606 0x410C978
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_607 0x410C97C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_608 0x410C980
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_609 0x410C984
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_610 0x410C988
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_611 0x410C98C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_612 0x410C990
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_613 0x410C994
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_614 0x410C998
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_615 0x410C99C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_616 0x410C9A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_617 0x410C9A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_618 0x410C9A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_619 0x410C9AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_620 0x410C9B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_621 0x410C9B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_622 0x410C9B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_623 0x410C9BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_624 0x410C9C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_625 0x410C9C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_626 0x410C9C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_627 0x410C9CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_628 0x410C9D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_629 0x410C9D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_630 0x410C9D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_631 0x410C9DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_632 0x410C9E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_633 0x410C9E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_634 0x410C9E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_635 0x410C9EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_636 0x410C9F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_637 0x410C9F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_638 0x410C9F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_639 0x410C9FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_640 0x410CA00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_641 0x410CA04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_642 0x410CA08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_643 0x410CA0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_644 0x410CA10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_645 0x410CA14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_646 0x410CA18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_647 0x410CA1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_648 0x410CA20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_649 0x410CA24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_650 0x410CA28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_651 0x410CA2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_652 0x410CA30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_653 0x410CA34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_654 0x410CA38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_655 0x410CA3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_656 0x410CA40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_657 0x410CA44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_658 0x410CA48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_659 0x410CA4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_660 0x410CA50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_661 0x410CA54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_662 0x410CA58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_663 0x410CA5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_664 0x410CA60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_665 0x410CA64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_666 0x410CA68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_667 0x410CA6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_668 0x410CA70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_669 0x410CA74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_670 0x410CA78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_671 0x410CA7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_672 0x410CA80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_673 0x410CA84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_674 0x410CA88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_675 0x410CA8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_676 0x410CA90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_677 0x410CA94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_678 0x410CA98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_679 0x410CA9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_680 0x410CAA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_681 0x410CAA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_682 0x410CAA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_683 0x410CAAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_684 0x410CAB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_685 0x410CAB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_686 0x410CAB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_687 0x410CABC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_688 0x410CAC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_689 0x410CAC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_690 0x410CAC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_691 0x410CACC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_692 0x410CAD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_693 0x410CAD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_694 0x410CAD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_695 0x410CADC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_696 0x410CAE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_697 0x410CAE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_698 0x410CAE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_699 0x410CAEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_700 0x410CAF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_701 0x410CAF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_702 0x410CAF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_703 0x410CAFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_704 0x410CB00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_705 0x410CB04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_706 0x410CB08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_707 0x410CB0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_708 0x410CB10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_709 0x410CB14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_710 0x410CB18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_711 0x410CB1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_712 0x410CB20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_713 0x410CB24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_714 0x410CB28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_715 0x410CB2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_716 0x410CB30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_717 0x410CB34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_718 0x410CB38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_719 0x410CB3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_720 0x410CB40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_721 0x410CB44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_722 0x410CB48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_723 0x410CB4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_724 0x410CB50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_725 0x410CB54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_726 0x410CB58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_727 0x410CB5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_728 0x410CB60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_729 0x410CB64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_730 0x410CB68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_731 0x410CB6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_732 0x410CB70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_733 0x410CB74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_734 0x410CB78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_735 0x410CB7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_736 0x410CB80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_737 0x410CB84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_738 0x410CB88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_739 0x410CB8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_740 0x410CB90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_741 0x410CB94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_742 0x410CB98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_743 0x410CB9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_744 0x410CBA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_745 0x410CBA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_746 0x410CBA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_747 0x410CBAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_748 0x410CBB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_749 0x410CBB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_750 0x410CBB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_751 0x410CBBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_752 0x410CBC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_753 0x410CBC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_754 0x410CBC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_755 0x410CBCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_756 0x410CBD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_757 0x410CBD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_758 0x410CBD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_759 0x410CBDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_760 0x410CBE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_761 0x410CBE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_762 0x410CBE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_763 0x410CBEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_764 0x410CBF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_765 0x410CBF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_766 0x410CBF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_767 0x410CBFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_768 0x410CC00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_769 0x410CC04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_770 0x410CC08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_771 0x410CC0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_772 0x410CC10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_773 0x410CC14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_774 0x410CC18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_775 0x410CC1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_776 0x410CC20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_777 0x410CC24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_778 0x410CC28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_779 0x410CC2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_780 0x410CC30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_781 0x410CC34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_782 0x410CC38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_783 0x410CC3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_784 0x410CC40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_785 0x410CC44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_786 0x410CC48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_787 0x410CC4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_788 0x410CC50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_789 0x410CC54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_790 0x410CC58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_791 0x410CC5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_792 0x410CC60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_793 0x410CC64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_794 0x410CC68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_795 0x410CC6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_796 0x410CC70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_797 0x410CC74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_798 0x410CC78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_799 0x410CC7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_800 0x410CC80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_801 0x410CC84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_802 0x410CC88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_803 0x410CC8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_804 0x410CC90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_805 0x410CC94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_806 0x410CC98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_807 0x410CC9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_808 0x410CCA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_809 0x410CCA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_810 0x410CCA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_811 0x410CCAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_812 0x410CCB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_813 0x410CCB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_814 0x410CCB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_815 0x410CCBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_816 0x410CCC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_817 0x410CCC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_818 0x410CCC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_819 0x410CCCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_820 0x410CCD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_821 0x410CCD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_822 0x410CCD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_823 0x410CCDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_824 0x410CCE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_825 0x410CCE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_826 0x410CCE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_827 0x410CCEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_828 0x410CCF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_829 0x410CCF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_830 0x410CCF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_831 0x410CCFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_832 0x410CD00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_833 0x410CD04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_834 0x410CD08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_835 0x410CD0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_836 0x410CD10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_837 0x410CD14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_838 0x410CD18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_839 0x410CD1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_840 0x410CD20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_841 0x410CD24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_842 0x410CD28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_843 0x410CD2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_844 0x410CD30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_845 0x410CD34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_846 0x410CD38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_847 0x410CD3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_848 0x410CD40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_849 0x410CD44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_850 0x410CD48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_851 0x410CD4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_852 0x410CD50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_853 0x410CD54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_854 0x410CD58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_855 0x410CD5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_856 0x410CD60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_857 0x410CD64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_858 0x410CD68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_859 0x410CD6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_860 0x410CD70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_861 0x410CD74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_862 0x410CD78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_863 0x410CD7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_864 0x410CD80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_865 0x410CD84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_866 0x410CD88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_867 0x410CD8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_868 0x410CD90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_869 0x410CD94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_870 0x410CD98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_871 0x410CD9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_872 0x410CDA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_873 0x410CDA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_874 0x410CDA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_875 0x410CDAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_876 0x410CDB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_877 0x410CDB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_878 0x410CDB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_879 0x410CDBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_880 0x410CDC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_881 0x410CDC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_882 0x410CDC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_883 0x410CDCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_884 0x410CDD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_885 0x410CDD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_886 0x410CDD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_887 0x410CDDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_888 0x410CDE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_889 0x410CDE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_890 0x410CDE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_891 0x410CDEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_892 0x410CDF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_893 0x410CDF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_894 0x410CDF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_895 0x410CDFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_896 0x410CE00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_897 0x410CE04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_898 0x410CE08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_899 0x410CE0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_900 0x410CE10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_901 0x410CE14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_902 0x410CE18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_903 0x410CE1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_904 0x410CE20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_905 0x410CE24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_906 0x410CE28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_907 0x410CE2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_908 0x410CE30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_909 0x410CE34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_910 0x410CE38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_911 0x410CE3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_912 0x410CE40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_913 0x410CE44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_914 0x410CE48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_915 0x410CE4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_916 0x410CE50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_917 0x410CE54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_918 0x410CE58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_919 0x410CE5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_920 0x410CE60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_921 0x410CE64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_922 0x410CE68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_923 0x410CE6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_924 0x410CE70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_925 0x410CE74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_926 0x410CE78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_927 0x410CE7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_928 0x410CE80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_929 0x410CE84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_930 0x410CE88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_931 0x410CE8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_932 0x410CE90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_933 0x410CE94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_934 0x410CE98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_935 0x410CE9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_936 0x410CEA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_937 0x410CEA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_938 0x410CEA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_939 0x410CEAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_940 0x410CEB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_941 0x410CEB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_942 0x410CEB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_943 0x410CEBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_944 0x410CEC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_945 0x410CEC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_946 0x410CEC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_947 0x410CECC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_948 0x410CED0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_949 0x410CED4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_950 0x410CED8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_951 0x410CEDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_952 0x410CEE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_953 0x410CEE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_954 0x410CEE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_955 0x410CEEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_956 0x410CEF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_957 0x410CEF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_958 0x410CEF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_959 0x410CEFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_960 0x410CF00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_961 0x410CF04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_962 0x410CF08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_963 0x410CF0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_964 0x410CF10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_965 0x410CF14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_966 0x410CF18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_967 0x410CF1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_968 0x410CF20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_969 0x410CF24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_970 0x410CF28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_971 0x410CF2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_972 0x410CF30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_973 0x410CF34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_974 0x410CF38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_975 0x410CF3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_976 0x410CF40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_977 0x410CF44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_978 0x410CF48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_979 0x410CF4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_980 0x410CF50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_981 0x410CF54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_982 0x410CF58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_983 0x410CF5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_984 0x410CF60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_985 0x410CF64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_986 0x410CF68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_987 0x410CF6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_988 0x410CF70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_989 0x410CF74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_990 0x410CF78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_991 0x410CF7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_992 0x410CF80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_993 0x410CF84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_994 0x410CF88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_995 0x410CF8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_996 0x410CF90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_997 0x410CF94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_998 0x410CF98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_999 0x410CF9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1000 0x410CFA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1001 0x410CFA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1002 0x410CFA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1003 0x410CFAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1004 0x410CFB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1005 0x410CFB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1006 0x410CFB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1007 0x410CFBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1008 0x410CFC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1009 0x410CFC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1010 0x410CFC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1011 0x410CFCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1012 0x410CFD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1013 0x410CFD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1014 0x410CFD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1015 0x410CFDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1016 0x410CFE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1017 0x410CFE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1018 0x410CFE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1019 0x410CFEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1020 0x410CFF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1021 0x410CFF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1022 0x410CFF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1023 0x410CFFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1024 0x410D000
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1025 0x410D004
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1026 0x410D008
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1027 0x410D00C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1028 0x410D010
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1029 0x410D014
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1030 0x410D018
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1031 0x410D01C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1032 0x410D020
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1033 0x410D024
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1034 0x410D028
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1035 0x410D02C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1036 0x410D030
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1037 0x410D034
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1038 0x410D038
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1039 0x410D03C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1040 0x410D040
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1041 0x410D044
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1042 0x410D048
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1043 0x410D04C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1044 0x410D050
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1045 0x410D054
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1046 0x410D058
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1047 0x410D05C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1048 0x410D060
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1049 0x410D064
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1050 0x410D068
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1051 0x410D06C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1052 0x410D070
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1053 0x410D074
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1054 0x410D078
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1055 0x410D07C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1056 0x410D080
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1057 0x410D084
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1058 0x410D088
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1059 0x410D08C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1060 0x410D090
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1061 0x410D094
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1062 0x410D098
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1063 0x410D09C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1064 0x410D0A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1065 0x410D0A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1066 0x410D0A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1067 0x410D0AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1068 0x410D0B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1069 0x410D0B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1070 0x410D0B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1071 0x410D0BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1072 0x410D0C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1073 0x410D0C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1074 0x410D0C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1075 0x410D0CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1076 0x410D0D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1077 0x410D0D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1078 0x410D0D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1079 0x410D0DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1080 0x410D0E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1081 0x410D0E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1082 0x410D0E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1083 0x410D0EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1084 0x410D0F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1085 0x410D0F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1086 0x410D0F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1087 0x410D0FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1088 0x410D100
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1089 0x410D104
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1090 0x410D108
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1091 0x410D10C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1092 0x410D110
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1093 0x410D114
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1094 0x410D118
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1095 0x410D11C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1096 0x410D120
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1097 0x410D124
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1098 0x410D128
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1099 0x410D12C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1100 0x410D130
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1101 0x410D134
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1102 0x410D138
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1103 0x410D13C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1104 0x410D140
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1105 0x410D144
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1106 0x410D148
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1107 0x410D14C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1108 0x410D150
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1109 0x410D154
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1110 0x410D158
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1111 0x410D15C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1112 0x410D160
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1113 0x410D164
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1114 0x410D168
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1115 0x410D16C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1116 0x410D170
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1117 0x410D174
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1118 0x410D178
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1119 0x410D17C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1120 0x410D180
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1121 0x410D184
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1122 0x410D188
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1123 0x410D18C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1124 0x410D190
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1125 0x410D194
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1126 0x410D198
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1127 0x410D19C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1128 0x410D1A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1129 0x410D1A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1130 0x410D1A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1131 0x410D1AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1132 0x410D1B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1133 0x410D1B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1134 0x410D1B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1135 0x410D1BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1136 0x410D1C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1137 0x410D1C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1138 0x410D1C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1139 0x410D1CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1140 0x410D1D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1141 0x410D1D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1142 0x410D1D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1143 0x410D1DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1144 0x410D1E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1145 0x410D1E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1146 0x410D1E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1147 0x410D1EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1148 0x410D1F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1149 0x410D1F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1150 0x410D1F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1151 0x410D1FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1152 0x410D200
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1153 0x410D204
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1154 0x410D208
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1155 0x410D20C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1156 0x410D210
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1157 0x410D214
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1158 0x410D218
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1159 0x410D21C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1160 0x410D220
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1161 0x410D224
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1162 0x410D228
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1163 0x410D22C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1164 0x410D230
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1165 0x410D234
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1166 0x410D238
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1167 0x410D23C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1168 0x410D240
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1169 0x410D244
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1170 0x410D248
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1171 0x410D24C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1172 0x410D250
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1173 0x410D254
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1174 0x410D258
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1175 0x410D25C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1176 0x410D260
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1177 0x410D264
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1178 0x410D268
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1179 0x410D26C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1180 0x410D270
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1181 0x410D274
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1182 0x410D278
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1183 0x410D27C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1184 0x410D280
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1185 0x410D284
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1186 0x410D288
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1187 0x410D28C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1188 0x410D290
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1189 0x410D294
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1190 0x410D298
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1191 0x410D29C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1192 0x410D2A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1193 0x410D2A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1194 0x410D2A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1195 0x410D2AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1196 0x410D2B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1197 0x410D2B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1198 0x410D2B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1199 0x410D2BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1200 0x410D2C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1201 0x410D2C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1202 0x410D2C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1203 0x410D2CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1204 0x410D2D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1205 0x410D2D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1206 0x410D2D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1207 0x410D2DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1208 0x410D2E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1209 0x410D2E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1210 0x410D2E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1211 0x410D2EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1212 0x410D2F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1213 0x410D2F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1214 0x410D2F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1215 0x410D2FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1216 0x410D300
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1217 0x410D304
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1218 0x410D308
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1219 0x410D30C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1220 0x410D310
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1221 0x410D314
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1222 0x410D318
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1223 0x410D31C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1224 0x410D320
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1225 0x410D324
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1226 0x410D328
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1227 0x410D32C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1228 0x410D330
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1229 0x410D334
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1230 0x410D338
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1231 0x410D33C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1232 0x410D340
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1233 0x410D344
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1234 0x410D348
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1235 0x410D34C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1236 0x410D350
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1237 0x410D354
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1238 0x410D358
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1239 0x410D35C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1240 0x410D360
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1241 0x410D364
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1242 0x410D368
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1243 0x410D36C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1244 0x410D370
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1245 0x410D374
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1246 0x410D378
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1247 0x410D37C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1248 0x410D380
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1249 0x410D384
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1250 0x410D388
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1251 0x410D38C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1252 0x410D390
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1253 0x410D394
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1254 0x410D398
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1255 0x410D39C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1256 0x410D3A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1257 0x410D3A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1258 0x410D3A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1259 0x410D3AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1260 0x410D3B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1261 0x410D3B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1262 0x410D3B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1263 0x410D3BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1264 0x410D3C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1265 0x410D3C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1266 0x410D3C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1267 0x410D3CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1268 0x410D3D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1269 0x410D3D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1270 0x410D3D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1271 0x410D3DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1272 0x410D3E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1273 0x410D3E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1274 0x410D3E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1275 0x410D3EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1276 0x410D3F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1277 0x410D3F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1278 0x410D3F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1279 0x410D3FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1280 0x410D400
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1281 0x410D404
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1282 0x410D408
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1283 0x410D40C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1284 0x410D410
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1285 0x410D414
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1286 0x410D418
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1287 0x410D41C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1288 0x410D420
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1289 0x410D424
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1290 0x410D428
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1291 0x410D42C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1292 0x410D430
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1293 0x410D434
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1294 0x410D438
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1295 0x410D43C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1296 0x410D440
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1297 0x410D444
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1298 0x410D448
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1299 0x410D44C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1300 0x410D450
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1301 0x410D454
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1302 0x410D458
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1303 0x410D45C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1304 0x410D460
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1305 0x410D464
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1306 0x410D468
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1307 0x410D46C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1308 0x410D470
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1309 0x410D474
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1310 0x410D478
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1311 0x410D47C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1312 0x410D480
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1313 0x410D484
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1314 0x410D488
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1315 0x410D48C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1316 0x410D490
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1317 0x410D494
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1318 0x410D498
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1319 0x410D49C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1320 0x410D4A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1321 0x410D4A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1322 0x410D4A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1323 0x410D4AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1324 0x410D4B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1325 0x410D4B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1326 0x410D4B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1327 0x410D4BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1328 0x410D4C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1329 0x410D4C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1330 0x410D4C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1331 0x410D4CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1332 0x410D4D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1333 0x410D4D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1334 0x410D4D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1335 0x410D4DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1336 0x410D4E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1337 0x410D4E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1338 0x410D4E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1339 0x410D4EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1340 0x410D4F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1341 0x410D4F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1342 0x410D4F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1343 0x410D4FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1344 0x410D500
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1345 0x410D504
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1346 0x410D508
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1347 0x410D50C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1348 0x410D510
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1349 0x410D514
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1350 0x410D518
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1351 0x410D51C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1352 0x410D520
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1353 0x410D524
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1354 0x410D528
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1355 0x410D52C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1356 0x410D530
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1357 0x410D534
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1358 0x410D538
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1359 0x410D53C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1360 0x410D540
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1361 0x410D544
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1362 0x410D548
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1363 0x410D54C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1364 0x410D550
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1365 0x410D554
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1366 0x410D558
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1367 0x410D55C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1368 0x410D560
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1369 0x410D564
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1370 0x410D568
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1371 0x410D56C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1372 0x410D570
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1373 0x410D574
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1374 0x410D578
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1375 0x410D57C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1376 0x410D580
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1377 0x410D584
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1378 0x410D588
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1379 0x410D58C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1380 0x410D590
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1381 0x410D594
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1382 0x410D598
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1383 0x410D59C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1384 0x410D5A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1385 0x410D5A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1386 0x410D5A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1387 0x410D5AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1388 0x410D5B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1389 0x410D5B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1390 0x410D5B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1391 0x410D5BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1392 0x410D5C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1393 0x410D5C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1394 0x410D5C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1395 0x410D5CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1396 0x410D5D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1397 0x410D5D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1398 0x410D5D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1399 0x410D5DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1400 0x410D5E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1401 0x410D5E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1402 0x410D5E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1403 0x410D5EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1404 0x410D5F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1405 0x410D5F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1406 0x410D5F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1407 0x410D5FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1408 0x410D600
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1409 0x410D604
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1410 0x410D608
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1411 0x410D60C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1412 0x410D610
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1413 0x410D614
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1414 0x410D618
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1415 0x410D61C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1416 0x410D620
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1417 0x410D624
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1418 0x410D628
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1419 0x410D62C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1420 0x410D630
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1421 0x410D634
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1422 0x410D638
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1423 0x410D63C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1424 0x410D640
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1425 0x410D644
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1426 0x410D648
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1427 0x410D64C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1428 0x410D650
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1429 0x410D654
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1430 0x410D658
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1431 0x410D65C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1432 0x410D660
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1433 0x410D664
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1434 0x410D668
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1435 0x410D66C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1436 0x410D670
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1437 0x410D674
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1438 0x410D678
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1439 0x410D67C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1440 0x410D680
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1441 0x410D684
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1442 0x410D688
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1443 0x410D68C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1444 0x410D690
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1445 0x410D694
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1446 0x410D698
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1447 0x410D69C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1448 0x410D6A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1449 0x410D6A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1450 0x410D6A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1451 0x410D6AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1452 0x410D6B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1453 0x410D6B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1454 0x410D6B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1455 0x410D6BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1456 0x410D6C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1457 0x410D6C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1458 0x410D6C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1459 0x410D6CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1460 0x410D6D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1461 0x410D6D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1462 0x410D6D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1463 0x410D6DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1464 0x410D6E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1465 0x410D6E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1466 0x410D6E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1467 0x410D6EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1468 0x410D6F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1469 0x410D6F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1470 0x410D6F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1471 0x410D6FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1472 0x410D700
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1473 0x410D704
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1474 0x410D708
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1475 0x410D70C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1476 0x410D710
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1477 0x410D714
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1478 0x410D718
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1479 0x410D71C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1480 0x410D720
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1481 0x410D724
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1482 0x410D728
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1483 0x410D72C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1484 0x410D730
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1485 0x410D734
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1486 0x410D738
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1487 0x410D73C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1488 0x410D740
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1489 0x410D744
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1490 0x410D748
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1491 0x410D74C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1492 0x410D750
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1493 0x410D754
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1494 0x410D758
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1495 0x410D75C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1496 0x410D760
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1497 0x410D764
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1498 0x410D768
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1499 0x410D76C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1500 0x410D770
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1501 0x410D774
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1502 0x410D778
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1503 0x410D77C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1504 0x410D780
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1505 0x410D784
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1506 0x410D788
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1507 0x410D78C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1508 0x410D790
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1509 0x410D794
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1510 0x410D798
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1511 0x410D79C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1512 0x410D7A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1513 0x410D7A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1514 0x410D7A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1515 0x410D7AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1516 0x410D7B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1517 0x410D7B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1518 0x410D7B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1519 0x410D7BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1520 0x410D7C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1521 0x410D7C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1522 0x410D7C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1523 0x410D7CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1524 0x410D7D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1525 0x410D7D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1526 0x410D7D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1527 0x410D7DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1528 0x410D7E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1529 0x410D7E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1530 0x410D7E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1531 0x410D7EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1532 0x410D7F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1533 0x410D7F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1534 0x410D7F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1535 0x410D7FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1536 0x410D800
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1537 0x410D804
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1538 0x410D808
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1539 0x410D80C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1540 0x410D810
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1541 0x410D814
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1542 0x410D818
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1543 0x410D81C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1544 0x410D820
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1545 0x410D824
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1546 0x410D828
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1547 0x410D82C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1548 0x410D830
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1549 0x410D834
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1550 0x410D838
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1551 0x410D83C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1552 0x410D840
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1553 0x410D844
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1554 0x410D848
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1555 0x410D84C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1556 0x410D850
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1557 0x410D854
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1558 0x410D858
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1559 0x410D85C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1560 0x410D860
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1561 0x410D864
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1562 0x410D868
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1563 0x410D86C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1564 0x410D870
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1565 0x410D874
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1566 0x410D878
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1567 0x410D87C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1568 0x410D880
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1569 0x410D884
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1570 0x410D888
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1571 0x410D88C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1572 0x410D890
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1573 0x410D894
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1574 0x410D898
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1575 0x410D89C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1576 0x410D8A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1577 0x410D8A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1578 0x410D8A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1579 0x410D8AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1580 0x410D8B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1581 0x410D8B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1582 0x410D8B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1583 0x410D8BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1584 0x410D8C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1585 0x410D8C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1586 0x410D8C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1587 0x410D8CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1588 0x410D8D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1589 0x410D8D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1590 0x410D8D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1591 0x410D8DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1592 0x410D8E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1593 0x410D8E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1594 0x410D8E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1595 0x410D8EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1596 0x410D8F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1597 0x410D8F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1598 0x410D8F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1599 0x410D8FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1600 0x410D900
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1601 0x410D904
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1602 0x410D908
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1603 0x410D90C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1604 0x410D910
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1605 0x410D914
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1606 0x410D918
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1607 0x410D91C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1608 0x410D920
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1609 0x410D924
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1610 0x410D928
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1611 0x410D92C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1612 0x410D930
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1613 0x410D934
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1614 0x410D938
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1615 0x410D93C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1616 0x410D940
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1617 0x410D944
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1618 0x410D948
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1619 0x410D94C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1620 0x410D950
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1621 0x410D954
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1622 0x410D958
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1623 0x410D95C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1624 0x410D960
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1625 0x410D964
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1626 0x410D968
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1627 0x410D96C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1628 0x410D970
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1629 0x410D974
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1630 0x410D978
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1631 0x410D97C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1632 0x410D980
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1633 0x410D984
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1634 0x410D988
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1635 0x410D98C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1636 0x410D990
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1637 0x410D994
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1638 0x410D998
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1639 0x410D99C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1640 0x410D9A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1641 0x410D9A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1642 0x410D9A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1643 0x410D9AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1644 0x410D9B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1645 0x410D9B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1646 0x410D9B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1647 0x410D9BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1648 0x410D9C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1649 0x410D9C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1650 0x410D9C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1651 0x410D9CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1652 0x410D9D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1653 0x410D9D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1654 0x410D9D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1655 0x410D9DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1656 0x410D9E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1657 0x410D9E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1658 0x410D9E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1659 0x410D9EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1660 0x410D9F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1661 0x410D9F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1662 0x410D9F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1663 0x410D9FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1664 0x410DA00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1665 0x410DA04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1666 0x410DA08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1667 0x410DA0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1668 0x410DA10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1669 0x410DA14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1670 0x410DA18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1671 0x410DA1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1672 0x410DA20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1673 0x410DA24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1674 0x410DA28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1675 0x410DA2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1676 0x410DA30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1677 0x410DA34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1678 0x410DA38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1679 0x410DA3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1680 0x410DA40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1681 0x410DA44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1682 0x410DA48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1683 0x410DA4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1684 0x410DA50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1685 0x410DA54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1686 0x410DA58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1687 0x410DA5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1688 0x410DA60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1689 0x410DA64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1690 0x410DA68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1691 0x410DA6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1692 0x410DA70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1693 0x410DA74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1694 0x410DA78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1695 0x410DA7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1696 0x410DA80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1697 0x410DA84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1698 0x410DA88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1699 0x410DA8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1700 0x410DA90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1701 0x410DA94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1702 0x410DA98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1703 0x410DA9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1704 0x410DAA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1705 0x410DAA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1706 0x410DAA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1707 0x410DAAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1708 0x410DAB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1709 0x410DAB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1710 0x410DAB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1711 0x410DABC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1712 0x410DAC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1713 0x410DAC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1714 0x410DAC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1715 0x410DACC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1716 0x410DAD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1717 0x410DAD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1718 0x410DAD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1719 0x410DADC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1720 0x410DAE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1721 0x410DAE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1722 0x410DAE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1723 0x410DAEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1724 0x410DAF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1725 0x410DAF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1726 0x410DAF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1727 0x410DAFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1728 0x410DB00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1729 0x410DB04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1730 0x410DB08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1731 0x410DB0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1732 0x410DB10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1733 0x410DB14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1734 0x410DB18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1735 0x410DB1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1736 0x410DB20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1737 0x410DB24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1738 0x410DB28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1739 0x410DB2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1740 0x410DB30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1741 0x410DB34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1742 0x410DB38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1743 0x410DB3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1744 0x410DB40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1745 0x410DB44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1746 0x410DB48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1747 0x410DB4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1748 0x410DB50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1749 0x410DB54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1750 0x410DB58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1751 0x410DB5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1752 0x410DB60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1753 0x410DB64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1754 0x410DB68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1755 0x410DB6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1756 0x410DB70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1757 0x410DB74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1758 0x410DB78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1759 0x410DB7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1760 0x410DB80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1761 0x410DB84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1762 0x410DB88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1763 0x410DB8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1764 0x410DB90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1765 0x410DB94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1766 0x410DB98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1767 0x410DB9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1768 0x410DBA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1769 0x410DBA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1770 0x410DBA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1771 0x410DBAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1772 0x410DBB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1773 0x410DBB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1774 0x410DBB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1775 0x410DBBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1776 0x410DBC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1777 0x410DBC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1778 0x410DBC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1779 0x410DBCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1780 0x410DBD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1781 0x410DBD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1782 0x410DBD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1783 0x410DBDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1784 0x410DBE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1785 0x410DBE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1786 0x410DBE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1787 0x410DBEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1788 0x410DBF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1789 0x410DBF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1790 0x410DBF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1791 0x410DBFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1792 0x410DC00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1793 0x410DC04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1794 0x410DC08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1795 0x410DC0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1796 0x410DC10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1797 0x410DC14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1798 0x410DC18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1799 0x410DC1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1800 0x410DC20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1801 0x410DC24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1802 0x410DC28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1803 0x410DC2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1804 0x410DC30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1805 0x410DC34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1806 0x410DC38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1807 0x410DC3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1808 0x410DC40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1809 0x410DC44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1810 0x410DC48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1811 0x410DC4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1812 0x410DC50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1813 0x410DC54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1814 0x410DC58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1815 0x410DC5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1816 0x410DC60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1817 0x410DC64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1818 0x410DC68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1819 0x410DC6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1820 0x410DC70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1821 0x410DC74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1822 0x410DC78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1823 0x410DC7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1824 0x410DC80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1825 0x410DC84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1826 0x410DC88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1827 0x410DC8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1828 0x410DC90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1829 0x410DC94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1830 0x410DC98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1831 0x410DC9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1832 0x410DCA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1833 0x410DCA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1834 0x410DCA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1835 0x410DCAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1836 0x410DCB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1837 0x410DCB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1838 0x410DCB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1839 0x410DCBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1840 0x410DCC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1841 0x410DCC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1842 0x410DCC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1843 0x410DCCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1844 0x410DCD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1845 0x410DCD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1846 0x410DCD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1847 0x410DCDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1848 0x410DCE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1849 0x410DCE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1850 0x410DCE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1851 0x410DCEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1852 0x410DCF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1853 0x410DCF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1854 0x410DCF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1855 0x410DCFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1856 0x410DD00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1857 0x410DD04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1858 0x410DD08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1859 0x410DD0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1860 0x410DD10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1861 0x410DD14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1862 0x410DD18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1863 0x410DD1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1864 0x410DD20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1865 0x410DD24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1866 0x410DD28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1867 0x410DD2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1868 0x410DD30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1869 0x410DD34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1870 0x410DD38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1871 0x410DD3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1872 0x410DD40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1873 0x410DD44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1874 0x410DD48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1875 0x410DD4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1876 0x410DD50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1877 0x410DD54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1878 0x410DD58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1879 0x410DD5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1880 0x410DD60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1881 0x410DD64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1882 0x410DD68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1883 0x410DD6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1884 0x410DD70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1885 0x410DD74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1886 0x410DD78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1887 0x410DD7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1888 0x410DD80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1889 0x410DD84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1890 0x410DD88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1891 0x410DD8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1892 0x410DD90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1893 0x410DD94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1894 0x410DD98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1895 0x410DD9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1896 0x410DDA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1897 0x410DDA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1898 0x410DDA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1899 0x410DDAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1900 0x410DDB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1901 0x410DDB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1902 0x410DDB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1903 0x410DDBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1904 0x410DDC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1905 0x410DDC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1906 0x410DDC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1907 0x410DDCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1908 0x410DDD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1909 0x410DDD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1910 0x410DDD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1911 0x410DDDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1912 0x410DDE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1913 0x410DDE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1914 0x410DDE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1915 0x410DDEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1916 0x410DDF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1917 0x410DDF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1918 0x410DDF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1919 0x410DDFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1920 0x410DE00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1921 0x410DE04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1922 0x410DE08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1923 0x410DE0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1924 0x410DE10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1925 0x410DE14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1926 0x410DE18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1927 0x410DE1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1928 0x410DE20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1929 0x410DE24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1930 0x410DE28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1931 0x410DE2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1932 0x410DE30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1933 0x410DE34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1934 0x410DE38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1935 0x410DE3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1936 0x410DE40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1937 0x410DE44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1938 0x410DE48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1939 0x410DE4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1940 0x410DE50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1941 0x410DE54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1942 0x410DE58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1943 0x410DE5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1944 0x410DE60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1945 0x410DE64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1946 0x410DE68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1947 0x410DE6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1948 0x410DE70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1949 0x410DE74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1950 0x410DE78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1951 0x410DE7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1952 0x410DE80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1953 0x410DE84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1954 0x410DE88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1955 0x410DE8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1956 0x410DE90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1957 0x410DE94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1958 0x410DE98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1959 0x410DE9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1960 0x410DEA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1961 0x410DEA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1962 0x410DEA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1963 0x410DEAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1964 0x410DEB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1965 0x410DEB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1966 0x410DEB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1967 0x410DEBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1968 0x410DEC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1969 0x410DEC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1970 0x410DEC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1971 0x410DECC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1972 0x410DED0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1973 0x410DED4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1974 0x410DED8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1975 0x410DEDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1976 0x410DEE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1977 0x410DEE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1978 0x410DEE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1979 0x410DEEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1980 0x410DEF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1981 0x410DEF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1982 0x410DEF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1983 0x410DEFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1984 0x410DF00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1985 0x410DF04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1986 0x410DF08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1987 0x410DF0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1988 0x410DF10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1989 0x410DF14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1990 0x410DF18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1991 0x410DF1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1992 0x410DF20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1993 0x410DF24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1994 0x410DF28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1995 0x410DF2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1996 0x410DF30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1997 0x410DF34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1998 0x410DF38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_1999 0x410DF3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2000 0x410DF40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2001 0x410DF44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2002 0x410DF48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2003 0x410DF4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2004 0x410DF50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2005 0x410DF54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2006 0x410DF58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2007 0x410DF5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2008 0x410DF60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2009 0x410DF64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2010 0x410DF68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2011 0x410DF6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2012 0x410DF70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2013 0x410DF74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2014 0x410DF78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2015 0x410DF7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2016 0x410DF80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2017 0x410DF84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2018 0x410DF88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2019 0x410DF8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2020 0x410DF90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2021 0x410DF94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2022 0x410DF98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2023 0x410DF9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2024 0x410DFA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2025 0x410DFA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2026 0x410DFA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2027 0x410DFAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2028 0x410DFB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2029 0x410DFB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2030 0x410DFB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2031 0x410DFBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2032 0x410DFC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2033 0x410DFC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2034 0x410DFC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2035 0x410DFCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2036 0x410DFD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2037 0x410DFD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2038 0x410DFD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2039 0x410DFDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2040 0x410DFE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2041 0x410DFE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2042 0x410DFE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2043 0x410DFEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2044 0x410DFF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2045 0x410DFF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2046 0x410DFF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_2047 0x410DFFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_0 0x410E000
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1 0x410E004
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2 0x410E008
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_3 0x410E00C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_4 0x410E010
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_5 0x410E014
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_6 0x410E018
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_7 0x410E01C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_8 0x410E020
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_9 0x410E024
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_10 0x410E028
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_11 0x410E02C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_12 0x410E030
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_13 0x410E034
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_14 0x410E038
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_15 0x410E03C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_16 0x410E040
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_17 0x410E044
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_18 0x410E048
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_19 0x410E04C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_20 0x410E050
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_21 0x410E054
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_22 0x410E058
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_23 0x410E05C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_24 0x410E060
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_25 0x410E064
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_26 0x410E068
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_27 0x410E06C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_28 0x410E070
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_29 0x410E074
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_30 0x410E078
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_31 0x410E07C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_32 0x410E080
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_33 0x410E084
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_34 0x410E088
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_35 0x410E08C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_36 0x410E090
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_37 0x410E094
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_38 0x410E098
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_39 0x410E09C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_40 0x410E0A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_41 0x410E0A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_42 0x410E0A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_43 0x410E0AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_44 0x410E0B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_45 0x410E0B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_46 0x410E0B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_47 0x410E0BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_48 0x410E0C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_49 0x410E0C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_50 0x410E0C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_51 0x410E0CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_52 0x410E0D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_53 0x410E0D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_54 0x410E0D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_55 0x410E0DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_56 0x410E0E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_57 0x410E0E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_58 0x410E0E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_59 0x410E0EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_60 0x410E0F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_61 0x410E0F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_62 0x410E0F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_63 0x410E0FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_64 0x410E100
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_65 0x410E104
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_66 0x410E108
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_67 0x410E10C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_68 0x410E110
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_69 0x410E114
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_70 0x410E118
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_71 0x410E11C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_72 0x410E120
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_73 0x410E124
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_74 0x410E128
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_75 0x410E12C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_76 0x410E130
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_77 0x410E134
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_78 0x410E138
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_79 0x410E13C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_80 0x410E140
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_81 0x410E144
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_82 0x410E148
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_83 0x410E14C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_84 0x410E150
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_85 0x410E154
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_86 0x410E158
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_87 0x410E15C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_88 0x410E160
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_89 0x410E164
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_90 0x410E168
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_91 0x410E16C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_92 0x410E170
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_93 0x410E174
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_94 0x410E178
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_95 0x410E17C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_96 0x410E180
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_97 0x410E184
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_98 0x410E188
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_99 0x410E18C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_100 0x410E190
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_101 0x410E194
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_102 0x410E198
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_103 0x410E19C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_104 0x410E1A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_105 0x410E1A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_106 0x410E1A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_107 0x410E1AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_108 0x410E1B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_109 0x410E1B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_110 0x410E1B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_111 0x410E1BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_112 0x410E1C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_113 0x410E1C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_114 0x410E1C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_115 0x410E1CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_116 0x410E1D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_117 0x410E1D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_118 0x410E1D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_119 0x410E1DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_120 0x410E1E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_121 0x410E1E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_122 0x410E1E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_123 0x410E1EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_124 0x410E1F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_125 0x410E1F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_126 0x410E1F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_127 0x410E1FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_128 0x410E200
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_129 0x410E204
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_130 0x410E208
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_131 0x410E20C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_132 0x410E210
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_133 0x410E214
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_134 0x410E218
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_135 0x410E21C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_136 0x410E220
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_137 0x410E224
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_138 0x410E228
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_139 0x410E22C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_140 0x410E230
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_141 0x410E234
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_142 0x410E238
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_143 0x410E23C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_144 0x410E240
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_145 0x410E244
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_146 0x410E248
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_147 0x410E24C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_148 0x410E250
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_149 0x410E254
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_150 0x410E258
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_151 0x410E25C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_152 0x410E260
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_153 0x410E264
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_154 0x410E268
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_155 0x410E26C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_156 0x410E270
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_157 0x410E274
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_158 0x410E278
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_159 0x410E27C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_160 0x410E280
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_161 0x410E284
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_162 0x410E288
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_163 0x410E28C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_164 0x410E290
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_165 0x410E294
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_166 0x410E298
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_167 0x410E29C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_168 0x410E2A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_169 0x410E2A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_170 0x410E2A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_171 0x410E2AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_172 0x410E2B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_173 0x410E2B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_174 0x410E2B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_175 0x410E2BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_176 0x410E2C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_177 0x410E2C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_178 0x410E2C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_179 0x410E2CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_180 0x410E2D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_181 0x410E2D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_182 0x410E2D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_183 0x410E2DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_184 0x410E2E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_185 0x410E2E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_186 0x410E2E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_187 0x410E2EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_188 0x410E2F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_189 0x410E2F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_190 0x410E2F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_191 0x410E2FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_192 0x410E300
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_193 0x410E304
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_194 0x410E308
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_195 0x410E30C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_196 0x410E310
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_197 0x410E314
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_198 0x410E318
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_199 0x410E31C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_200 0x410E320
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_201 0x410E324
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_202 0x410E328
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_203 0x410E32C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_204 0x410E330
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_205 0x410E334
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_206 0x410E338
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_207 0x410E33C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_208 0x410E340
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_209 0x410E344
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_210 0x410E348
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_211 0x410E34C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_212 0x410E350
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_213 0x410E354
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_214 0x410E358
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_215 0x410E35C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_216 0x410E360
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_217 0x410E364
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_218 0x410E368
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_219 0x410E36C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_220 0x410E370
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_221 0x410E374
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_222 0x410E378
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_223 0x410E37C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_224 0x410E380
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_225 0x410E384
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_226 0x410E388
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_227 0x410E38C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_228 0x410E390
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_229 0x410E394
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_230 0x410E398
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_231 0x410E39C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_232 0x410E3A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_233 0x410E3A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_234 0x410E3A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_235 0x410E3AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_236 0x410E3B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_237 0x410E3B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_238 0x410E3B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_239 0x410E3BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_240 0x410E3C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_241 0x410E3C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_242 0x410E3C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_243 0x410E3CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_244 0x410E3D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_245 0x410E3D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_246 0x410E3D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_247 0x410E3DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_248 0x410E3E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_249 0x410E3E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_250 0x410E3E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_251 0x410E3EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_252 0x410E3F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_253 0x410E3F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_254 0x410E3F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_255 0x410E3FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_256 0x410E400
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_257 0x410E404
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_258 0x410E408
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_259 0x410E40C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_260 0x410E410
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_261 0x410E414
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_262 0x410E418
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_263 0x410E41C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_264 0x410E420
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_265 0x410E424
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_266 0x410E428
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_267 0x410E42C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_268 0x410E430
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_269 0x410E434
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_270 0x410E438
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_271 0x410E43C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_272 0x410E440
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_273 0x410E444
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_274 0x410E448
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_275 0x410E44C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_276 0x410E450
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_277 0x410E454
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_278 0x410E458
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_279 0x410E45C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_280 0x410E460
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_281 0x410E464
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_282 0x410E468
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_283 0x410E46C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_284 0x410E470
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_285 0x410E474
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_286 0x410E478
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_287 0x410E47C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_288 0x410E480
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_289 0x410E484
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_290 0x410E488
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_291 0x410E48C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_292 0x410E490
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_293 0x410E494
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_294 0x410E498
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_295 0x410E49C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_296 0x410E4A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_297 0x410E4A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_298 0x410E4A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_299 0x410E4AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_300 0x410E4B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_301 0x410E4B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_302 0x410E4B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_303 0x410E4BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_304 0x410E4C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_305 0x410E4C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_306 0x410E4C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_307 0x410E4CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_308 0x410E4D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_309 0x410E4D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_310 0x410E4D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_311 0x410E4DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_312 0x410E4E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_313 0x410E4E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_314 0x410E4E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_315 0x410E4EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_316 0x410E4F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_317 0x410E4F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_318 0x410E4F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_319 0x410E4FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_320 0x410E500
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_321 0x410E504
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_322 0x410E508
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_323 0x410E50C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_324 0x410E510
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_325 0x410E514
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_326 0x410E518
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_327 0x410E51C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_328 0x410E520
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_329 0x410E524
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_330 0x410E528
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_331 0x410E52C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_332 0x410E530
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_333 0x410E534
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_334 0x410E538
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_335 0x410E53C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_336 0x410E540
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_337 0x410E544
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_338 0x410E548
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_339 0x410E54C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_340 0x410E550
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_341 0x410E554
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_342 0x410E558
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_343 0x410E55C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_344 0x410E560
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_345 0x410E564
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_346 0x410E568
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_347 0x410E56C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_348 0x410E570
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_349 0x410E574
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_350 0x410E578
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_351 0x410E57C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_352 0x410E580
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_353 0x410E584
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_354 0x410E588
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_355 0x410E58C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_356 0x410E590
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_357 0x410E594
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_358 0x410E598
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_359 0x410E59C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_360 0x410E5A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_361 0x410E5A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_362 0x410E5A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_363 0x410E5AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_364 0x410E5B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_365 0x410E5B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_366 0x410E5B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_367 0x410E5BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_368 0x410E5C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_369 0x410E5C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_370 0x410E5C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_371 0x410E5CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_372 0x410E5D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_373 0x410E5D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_374 0x410E5D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_375 0x410E5DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_376 0x410E5E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_377 0x410E5E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_378 0x410E5E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_379 0x410E5EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_380 0x410E5F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_381 0x410E5F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_382 0x410E5F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_383 0x410E5FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_384 0x410E600
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_385 0x410E604
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_386 0x410E608
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_387 0x410E60C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_388 0x410E610
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_389 0x410E614
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_390 0x410E618
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_391 0x410E61C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_392 0x410E620
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_393 0x410E624
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_394 0x410E628
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_395 0x410E62C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_396 0x410E630
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_397 0x410E634
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_398 0x410E638
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_399 0x410E63C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_400 0x410E640
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_401 0x410E644
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_402 0x410E648
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_403 0x410E64C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_404 0x410E650
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_405 0x410E654
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_406 0x410E658
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_407 0x410E65C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_408 0x410E660
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_409 0x410E664
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_410 0x410E668
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_411 0x410E66C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_412 0x410E670
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_413 0x410E674
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_414 0x410E678
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_415 0x410E67C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_416 0x410E680
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_417 0x410E684
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_418 0x410E688
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_419 0x410E68C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_420 0x410E690
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_421 0x410E694
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_422 0x410E698
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_423 0x410E69C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_424 0x410E6A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_425 0x410E6A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_426 0x410E6A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_427 0x410E6AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_428 0x410E6B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_429 0x410E6B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_430 0x410E6B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_431 0x410E6BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_432 0x410E6C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_433 0x410E6C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_434 0x410E6C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_435 0x410E6CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_436 0x410E6D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_437 0x410E6D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_438 0x410E6D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_439 0x410E6DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_440 0x410E6E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_441 0x410E6E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_442 0x410E6E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_443 0x410E6EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_444 0x410E6F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_445 0x410E6F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_446 0x410E6F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_447 0x410E6FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_448 0x410E700
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_449 0x410E704
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_450 0x410E708
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_451 0x410E70C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_452 0x410E710
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_453 0x410E714
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_454 0x410E718
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_455 0x410E71C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_456 0x410E720
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_457 0x410E724
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_458 0x410E728
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_459 0x410E72C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_460 0x410E730
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_461 0x410E734
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_462 0x410E738
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_463 0x410E73C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_464 0x410E740
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_465 0x410E744
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_466 0x410E748
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_467 0x410E74C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_468 0x410E750
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_469 0x410E754
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_470 0x410E758
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_471 0x410E75C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_472 0x410E760
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_473 0x410E764
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_474 0x410E768
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_475 0x410E76C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_476 0x410E770
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_477 0x410E774
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_478 0x410E778
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_479 0x410E77C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_480 0x410E780
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_481 0x410E784
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_482 0x410E788
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_483 0x410E78C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_484 0x410E790
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_485 0x410E794
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_486 0x410E798
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_487 0x410E79C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_488 0x410E7A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_489 0x410E7A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_490 0x410E7A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_491 0x410E7AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_492 0x410E7B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_493 0x410E7B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_494 0x410E7B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_495 0x410E7BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_496 0x410E7C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_497 0x410E7C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_498 0x410E7C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_499 0x410E7CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_500 0x410E7D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_501 0x410E7D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_502 0x410E7D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_503 0x410E7DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_504 0x410E7E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_505 0x410E7E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_506 0x410E7E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_507 0x410E7EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_508 0x410E7F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_509 0x410E7F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_510 0x410E7F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_511 0x410E7FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_512 0x410E800
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_513 0x410E804
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_514 0x410E808
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_515 0x410E80C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_516 0x410E810
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_517 0x410E814
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_518 0x410E818
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_519 0x410E81C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_520 0x410E820
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_521 0x410E824
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_522 0x410E828
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_523 0x410E82C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_524 0x410E830
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_525 0x410E834
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_526 0x410E838
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_527 0x410E83C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_528 0x410E840
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_529 0x410E844
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_530 0x410E848
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_531 0x410E84C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_532 0x410E850
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_533 0x410E854
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_534 0x410E858
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_535 0x410E85C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_536 0x410E860
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_537 0x410E864
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_538 0x410E868
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_539 0x410E86C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_540 0x410E870
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_541 0x410E874
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_542 0x410E878
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_543 0x410E87C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_544 0x410E880
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_545 0x410E884
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_546 0x410E888
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_547 0x410E88C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_548 0x410E890
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_549 0x410E894
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_550 0x410E898
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_551 0x410E89C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_552 0x410E8A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_553 0x410E8A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_554 0x410E8A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_555 0x410E8AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_556 0x410E8B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_557 0x410E8B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_558 0x410E8B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_559 0x410E8BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_560 0x410E8C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_561 0x410E8C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_562 0x410E8C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_563 0x410E8CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_564 0x410E8D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_565 0x410E8D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_566 0x410E8D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_567 0x410E8DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_568 0x410E8E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_569 0x410E8E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_570 0x410E8E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_571 0x410E8EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_572 0x410E8F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_573 0x410E8F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_574 0x410E8F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_575 0x410E8FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_576 0x410E900
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_577 0x410E904
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_578 0x410E908
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_579 0x410E90C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_580 0x410E910
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_581 0x410E914
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_582 0x410E918
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_583 0x410E91C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_584 0x410E920
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_585 0x410E924
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_586 0x410E928
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_587 0x410E92C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_588 0x410E930
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_589 0x410E934
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_590 0x410E938
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_591 0x410E93C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_592 0x410E940
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_593 0x410E944
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_594 0x410E948
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_595 0x410E94C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_596 0x410E950
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_597 0x410E954
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_598 0x410E958
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_599 0x410E95C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_600 0x410E960
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_601 0x410E964
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_602 0x410E968
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_603 0x410E96C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_604 0x410E970
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_605 0x410E974
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_606 0x410E978
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_607 0x410E97C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_608 0x410E980
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_609 0x410E984
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_610 0x410E988
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_611 0x410E98C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_612 0x410E990
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_613 0x410E994
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_614 0x410E998
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_615 0x410E99C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_616 0x410E9A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_617 0x410E9A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_618 0x410E9A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_619 0x410E9AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_620 0x410E9B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_621 0x410E9B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_622 0x410E9B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_623 0x410E9BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_624 0x410E9C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_625 0x410E9C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_626 0x410E9C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_627 0x410E9CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_628 0x410E9D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_629 0x410E9D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_630 0x410E9D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_631 0x410E9DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_632 0x410E9E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_633 0x410E9E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_634 0x410E9E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_635 0x410E9EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_636 0x410E9F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_637 0x410E9F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_638 0x410E9F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_639 0x410E9FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_640 0x410EA00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_641 0x410EA04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_642 0x410EA08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_643 0x410EA0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_644 0x410EA10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_645 0x410EA14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_646 0x410EA18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_647 0x410EA1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_648 0x410EA20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_649 0x410EA24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_650 0x410EA28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_651 0x410EA2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_652 0x410EA30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_653 0x410EA34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_654 0x410EA38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_655 0x410EA3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_656 0x410EA40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_657 0x410EA44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_658 0x410EA48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_659 0x410EA4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_660 0x410EA50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_661 0x410EA54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_662 0x410EA58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_663 0x410EA5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_664 0x410EA60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_665 0x410EA64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_666 0x410EA68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_667 0x410EA6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_668 0x410EA70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_669 0x410EA74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_670 0x410EA78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_671 0x410EA7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_672 0x410EA80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_673 0x410EA84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_674 0x410EA88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_675 0x410EA8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_676 0x410EA90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_677 0x410EA94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_678 0x410EA98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_679 0x410EA9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_680 0x410EAA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_681 0x410EAA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_682 0x410EAA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_683 0x410EAAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_684 0x410EAB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_685 0x410EAB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_686 0x410EAB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_687 0x410EABC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_688 0x410EAC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_689 0x410EAC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_690 0x410EAC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_691 0x410EACC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_692 0x410EAD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_693 0x410EAD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_694 0x410EAD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_695 0x410EADC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_696 0x410EAE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_697 0x410EAE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_698 0x410EAE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_699 0x410EAEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_700 0x410EAF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_701 0x410EAF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_702 0x410EAF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_703 0x410EAFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_704 0x410EB00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_705 0x410EB04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_706 0x410EB08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_707 0x410EB0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_708 0x410EB10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_709 0x410EB14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_710 0x410EB18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_711 0x410EB1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_712 0x410EB20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_713 0x410EB24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_714 0x410EB28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_715 0x410EB2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_716 0x410EB30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_717 0x410EB34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_718 0x410EB38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_719 0x410EB3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_720 0x410EB40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_721 0x410EB44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_722 0x410EB48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_723 0x410EB4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_724 0x410EB50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_725 0x410EB54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_726 0x410EB58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_727 0x410EB5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_728 0x410EB60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_729 0x410EB64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_730 0x410EB68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_731 0x410EB6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_732 0x410EB70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_733 0x410EB74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_734 0x410EB78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_735 0x410EB7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_736 0x410EB80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_737 0x410EB84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_738 0x410EB88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_739 0x410EB8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_740 0x410EB90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_741 0x410EB94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_742 0x410EB98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_743 0x410EB9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_744 0x410EBA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_745 0x410EBA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_746 0x410EBA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_747 0x410EBAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_748 0x410EBB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_749 0x410EBB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_750 0x410EBB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_751 0x410EBBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_752 0x410EBC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_753 0x410EBC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_754 0x410EBC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_755 0x410EBCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_756 0x410EBD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_757 0x410EBD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_758 0x410EBD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_759 0x410EBDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_760 0x410EBE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_761 0x410EBE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_762 0x410EBE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_763 0x410EBEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_764 0x410EBF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_765 0x410EBF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_766 0x410EBF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_767 0x410EBFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_768 0x410EC00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_769 0x410EC04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_770 0x410EC08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_771 0x410EC0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_772 0x410EC10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_773 0x410EC14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_774 0x410EC18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_775 0x410EC1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_776 0x410EC20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_777 0x410EC24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_778 0x410EC28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_779 0x410EC2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_780 0x410EC30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_781 0x410EC34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_782 0x410EC38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_783 0x410EC3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_784 0x410EC40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_785 0x410EC44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_786 0x410EC48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_787 0x410EC4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_788 0x410EC50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_789 0x410EC54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_790 0x410EC58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_791 0x410EC5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_792 0x410EC60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_793 0x410EC64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_794 0x410EC68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_795 0x410EC6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_796 0x410EC70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_797 0x410EC74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_798 0x410EC78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_799 0x410EC7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_800 0x410EC80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_801 0x410EC84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_802 0x410EC88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_803 0x410EC8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_804 0x410EC90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_805 0x410EC94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_806 0x410EC98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_807 0x410EC9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_808 0x410ECA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_809 0x410ECA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_810 0x410ECA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_811 0x410ECAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_812 0x410ECB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_813 0x410ECB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_814 0x410ECB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_815 0x410ECBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_816 0x410ECC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_817 0x410ECC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_818 0x410ECC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_819 0x410ECCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_820 0x410ECD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_821 0x410ECD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_822 0x410ECD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_823 0x410ECDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_824 0x410ECE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_825 0x410ECE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_826 0x410ECE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_827 0x410ECEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_828 0x410ECF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_829 0x410ECF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_830 0x410ECF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_831 0x410ECFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_832 0x410ED00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_833 0x410ED04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_834 0x410ED08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_835 0x410ED0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_836 0x410ED10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_837 0x410ED14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_838 0x410ED18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_839 0x410ED1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_840 0x410ED20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_841 0x410ED24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_842 0x410ED28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_843 0x410ED2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_844 0x410ED30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_845 0x410ED34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_846 0x410ED38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_847 0x410ED3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_848 0x410ED40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_849 0x410ED44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_850 0x410ED48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_851 0x410ED4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_852 0x410ED50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_853 0x410ED54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_854 0x410ED58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_855 0x410ED5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_856 0x410ED60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_857 0x410ED64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_858 0x410ED68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_859 0x410ED6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_860 0x410ED70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_861 0x410ED74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_862 0x410ED78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_863 0x410ED7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_864 0x410ED80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_865 0x410ED84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_866 0x410ED88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_867 0x410ED8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_868 0x410ED90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_869 0x410ED94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_870 0x410ED98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_871 0x410ED9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_872 0x410EDA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_873 0x410EDA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_874 0x410EDA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_875 0x410EDAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_876 0x410EDB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_877 0x410EDB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_878 0x410EDB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_879 0x410EDBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_880 0x410EDC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_881 0x410EDC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_882 0x410EDC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_883 0x410EDCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_884 0x410EDD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_885 0x410EDD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_886 0x410EDD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_887 0x410EDDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_888 0x410EDE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_889 0x410EDE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_890 0x410EDE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_891 0x410EDEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_892 0x410EDF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_893 0x410EDF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_894 0x410EDF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_895 0x410EDFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_896 0x410EE00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_897 0x410EE04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_898 0x410EE08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_899 0x410EE0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_900 0x410EE10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_901 0x410EE14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_902 0x410EE18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_903 0x410EE1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_904 0x410EE20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_905 0x410EE24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_906 0x410EE28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_907 0x410EE2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_908 0x410EE30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_909 0x410EE34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_910 0x410EE38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_911 0x410EE3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_912 0x410EE40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_913 0x410EE44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_914 0x410EE48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_915 0x410EE4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_916 0x410EE50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_917 0x410EE54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_918 0x410EE58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_919 0x410EE5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_920 0x410EE60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_921 0x410EE64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_922 0x410EE68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_923 0x410EE6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_924 0x410EE70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_925 0x410EE74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_926 0x410EE78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_927 0x410EE7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_928 0x410EE80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_929 0x410EE84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_930 0x410EE88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_931 0x410EE8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_932 0x410EE90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_933 0x410EE94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_934 0x410EE98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_935 0x410EE9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_936 0x410EEA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_937 0x410EEA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_938 0x410EEA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_939 0x410EEAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_940 0x410EEB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_941 0x410EEB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_942 0x410EEB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_943 0x410EEBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_944 0x410EEC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_945 0x410EEC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_946 0x410EEC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_947 0x410EECC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_948 0x410EED0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_949 0x410EED4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_950 0x410EED8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_951 0x410EEDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_952 0x410EEE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_953 0x410EEE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_954 0x410EEE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_955 0x410EEEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_956 0x410EEF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_957 0x410EEF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_958 0x410EEF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_959 0x410EEFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_960 0x410EF00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_961 0x410EF04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_962 0x410EF08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_963 0x410EF0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_964 0x410EF10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_965 0x410EF14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_966 0x410EF18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_967 0x410EF1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_968 0x410EF20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_969 0x410EF24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_970 0x410EF28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_971 0x410EF2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_972 0x410EF30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_973 0x410EF34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_974 0x410EF38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_975 0x410EF3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_976 0x410EF40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_977 0x410EF44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_978 0x410EF48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_979 0x410EF4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_980 0x410EF50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_981 0x410EF54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_982 0x410EF58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_983 0x410EF5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_984 0x410EF60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_985 0x410EF64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_986 0x410EF68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_987 0x410EF6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_988 0x410EF70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_989 0x410EF74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_990 0x410EF78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_991 0x410EF7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_992 0x410EF80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_993 0x410EF84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_994 0x410EF88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_995 0x410EF8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_996 0x410EF90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_997 0x410EF94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_998 0x410EF98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_999 0x410EF9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1000 0x410EFA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1001 0x410EFA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1002 0x410EFA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1003 0x410EFAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1004 0x410EFB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1005 0x410EFB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1006 0x410EFB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1007 0x410EFBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1008 0x410EFC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1009 0x410EFC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1010 0x410EFC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1011 0x410EFCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1012 0x410EFD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1013 0x410EFD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1014 0x410EFD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1015 0x410EFDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1016 0x410EFE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1017 0x410EFE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1018 0x410EFE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1019 0x410EFEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1020 0x410EFF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1021 0x410EFF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1022 0x410EFF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1023 0x410EFFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1024 0x410F000
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1025 0x410F004
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1026 0x410F008
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1027 0x410F00C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1028 0x410F010
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1029 0x410F014
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1030 0x410F018
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1031 0x410F01C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1032 0x410F020
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1033 0x410F024
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1034 0x410F028
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1035 0x410F02C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1036 0x410F030
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1037 0x410F034
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1038 0x410F038
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1039 0x410F03C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1040 0x410F040
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1041 0x410F044
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1042 0x410F048
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1043 0x410F04C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1044 0x410F050
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1045 0x410F054
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1046 0x410F058
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1047 0x410F05C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1048 0x410F060
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1049 0x410F064
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1050 0x410F068
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1051 0x410F06C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1052 0x410F070
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1053 0x410F074
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1054 0x410F078
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1055 0x410F07C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1056 0x410F080
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1057 0x410F084
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1058 0x410F088
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1059 0x410F08C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1060 0x410F090
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1061 0x410F094
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1062 0x410F098
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1063 0x410F09C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1064 0x410F0A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1065 0x410F0A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1066 0x410F0A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1067 0x410F0AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1068 0x410F0B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1069 0x410F0B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1070 0x410F0B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1071 0x410F0BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1072 0x410F0C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1073 0x410F0C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1074 0x410F0C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1075 0x410F0CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1076 0x410F0D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1077 0x410F0D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1078 0x410F0D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1079 0x410F0DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1080 0x410F0E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1081 0x410F0E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1082 0x410F0E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1083 0x410F0EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1084 0x410F0F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1085 0x410F0F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1086 0x410F0F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1087 0x410F0FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1088 0x410F100
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1089 0x410F104
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1090 0x410F108
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1091 0x410F10C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1092 0x410F110
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1093 0x410F114
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1094 0x410F118
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1095 0x410F11C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1096 0x410F120
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1097 0x410F124
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1098 0x410F128
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1099 0x410F12C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1100 0x410F130
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1101 0x410F134
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1102 0x410F138
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1103 0x410F13C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1104 0x410F140
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1105 0x410F144
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1106 0x410F148
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1107 0x410F14C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1108 0x410F150
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1109 0x410F154
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1110 0x410F158
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1111 0x410F15C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1112 0x410F160
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1113 0x410F164
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1114 0x410F168
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1115 0x410F16C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1116 0x410F170
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1117 0x410F174
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1118 0x410F178
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1119 0x410F17C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1120 0x410F180
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1121 0x410F184
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1122 0x410F188
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1123 0x410F18C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1124 0x410F190
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1125 0x410F194
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1126 0x410F198
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1127 0x410F19C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1128 0x410F1A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1129 0x410F1A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1130 0x410F1A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1131 0x410F1AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1132 0x410F1B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1133 0x410F1B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1134 0x410F1B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1135 0x410F1BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1136 0x410F1C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1137 0x410F1C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1138 0x410F1C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1139 0x410F1CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1140 0x410F1D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1141 0x410F1D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1142 0x410F1D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1143 0x410F1DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1144 0x410F1E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1145 0x410F1E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1146 0x410F1E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1147 0x410F1EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1148 0x410F1F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1149 0x410F1F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1150 0x410F1F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1151 0x410F1FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1152 0x410F200
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1153 0x410F204
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1154 0x410F208
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1155 0x410F20C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1156 0x410F210
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1157 0x410F214
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1158 0x410F218
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1159 0x410F21C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1160 0x410F220
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1161 0x410F224
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1162 0x410F228
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1163 0x410F22C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1164 0x410F230
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1165 0x410F234
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1166 0x410F238
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1167 0x410F23C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1168 0x410F240
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1169 0x410F244
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1170 0x410F248
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1171 0x410F24C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1172 0x410F250
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1173 0x410F254
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1174 0x410F258
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1175 0x410F25C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1176 0x410F260
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1177 0x410F264
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1178 0x410F268
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1179 0x410F26C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1180 0x410F270
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1181 0x410F274
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1182 0x410F278
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1183 0x410F27C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1184 0x410F280
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1185 0x410F284
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1186 0x410F288
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1187 0x410F28C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1188 0x410F290
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1189 0x410F294
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1190 0x410F298
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1191 0x410F29C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1192 0x410F2A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1193 0x410F2A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1194 0x410F2A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1195 0x410F2AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1196 0x410F2B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1197 0x410F2B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1198 0x410F2B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1199 0x410F2BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1200 0x410F2C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1201 0x410F2C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1202 0x410F2C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1203 0x410F2CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1204 0x410F2D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1205 0x410F2D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1206 0x410F2D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1207 0x410F2DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1208 0x410F2E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1209 0x410F2E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1210 0x410F2E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1211 0x410F2EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1212 0x410F2F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1213 0x410F2F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1214 0x410F2F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1215 0x410F2FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1216 0x410F300
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1217 0x410F304
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1218 0x410F308
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1219 0x410F30C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1220 0x410F310
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1221 0x410F314
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1222 0x410F318
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1223 0x410F31C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1224 0x410F320
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1225 0x410F324
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1226 0x410F328
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1227 0x410F32C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1228 0x410F330
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1229 0x410F334
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1230 0x410F338
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1231 0x410F33C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1232 0x410F340
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1233 0x410F344
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1234 0x410F348
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1235 0x410F34C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1236 0x410F350
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1237 0x410F354
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1238 0x410F358
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1239 0x410F35C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1240 0x410F360
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1241 0x410F364
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1242 0x410F368
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1243 0x410F36C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1244 0x410F370
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1245 0x410F374
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1246 0x410F378
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1247 0x410F37C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1248 0x410F380
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1249 0x410F384
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1250 0x410F388
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1251 0x410F38C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1252 0x410F390
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1253 0x410F394
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1254 0x410F398
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1255 0x410F39C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1256 0x410F3A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1257 0x410F3A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1258 0x410F3A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1259 0x410F3AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1260 0x410F3B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1261 0x410F3B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1262 0x410F3B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1263 0x410F3BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1264 0x410F3C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1265 0x410F3C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1266 0x410F3C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1267 0x410F3CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1268 0x410F3D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1269 0x410F3D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1270 0x410F3D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1271 0x410F3DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1272 0x410F3E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1273 0x410F3E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1274 0x410F3E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1275 0x410F3EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1276 0x410F3F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1277 0x410F3F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1278 0x410F3F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1279 0x410F3FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1280 0x410F400
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1281 0x410F404
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1282 0x410F408
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1283 0x410F40C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1284 0x410F410
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1285 0x410F414
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1286 0x410F418
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1287 0x410F41C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1288 0x410F420
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1289 0x410F424
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1290 0x410F428
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1291 0x410F42C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1292 0x410F430
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1293 0x410F434
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1294 0x410F438
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1295 0x410F43C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1296 0x410F440
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1297 0x410F444
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1298 0x410F448
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1299 0x410F44C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1300 0x410F450
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1301 0x410F454
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1302 0x410F458
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1303 0x410F45C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1304 0x410F460
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1305 0x410F464
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1306 0x410F468
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1307 0x410F46C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1308 0x410F470
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1309 0x410F474
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1310 0x410F478
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1311 0x410F47C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1312 0x410F480
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1313 0x410F484
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1314 0x410F488
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1315 0x410F48C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1316 0x410F490
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1317 0x410F494
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1318 0x410F498
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1319 0x410F49C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1320 0x410F4A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1321 0x410F4A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1322 0x410F4A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1323 0x410F4AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1324 0x410F4B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1325 0x410F4B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1326 0x410F4B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1327 0x410F4BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1328 0x410F4C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1329 0x410F4C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1330 0x410F4C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1331 0x410F4CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1332 0x410F4D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1333 0x410F4D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1334 0x410F4D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1335 0x410F4DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1336 0x410F4E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1337 0x410F4E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1338 0x410F4E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1339 0x410F4EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1340 0x410F4F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1341 0x410F4F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1342 0x410F4F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1343 0x410F4FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1344 0x410F500
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1345 0x410F504
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1346 0x410F508
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1347 0x410F50C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1348 0x410F510
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1349 0x410F514
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1350 0x410F518
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1351 0x410F51C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1352 0x410F520
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1353 0x410F524
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1354 0x410F528
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1355 0x410F52C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1356 0x410F530
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1357 0x410F534
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1358 0x410F538
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1359 0x410F53C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1360 0x410F540
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1361 0x410F544
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1362 0x410F548
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1363 0x410F54C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1364 0x410F550
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1365 0x410F554
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1366 0x410F558
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1367 0x410F55C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1368 0x410F560
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1369 0x410F564
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1370 0x410F568
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1371 0x410F56C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1372 0x410F570
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1373 0x410F574
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1374 0x410F578
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1375 0x410F57C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1376 0x410F580
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1377 0x410F584
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1378 0x410F588
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1379 0x410F58C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1380 0x410F590
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1381 0x410F594
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1382 0x410F598
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1383 0x410F59C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1384 0x410F5A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1385 0x410F5A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1386 0x410F5A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1387 0x410F5AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1388 0x410F5B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1389 0x410F5B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1390 0x410F5B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1391 0x410F5BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1392 0x410F5C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1393 0x410F5C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1394 0x410F5C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1395 0x410F5CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1396 0x410F5D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1397 0x410F5D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1398 0x410F5D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1399 0x410F5DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1400 0x410F5E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1401 0x410F5E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1402 0x410F5E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1403 0x410F5EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1404 0x410F5F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1405 0x410F5F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1406 0x410F5F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1407 0x410F5FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1408 0x410F600
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1409 0x410F604
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1410 0x410F608
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1411 0x410F60C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1412 0x410F610
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1413 0x410F614
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1414 0x410F618
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1415 0x410F61C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1416 0x410F620
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1417 0x410F624
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1418 0x410F628
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1419 0x410F62C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1420 0x410F630
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1421 0x410F634
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1422 0x410F638
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1423 0x410F63C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1424 0x410F640
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1425 0x410F644
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1426 0x410F648
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1427 0x410F64C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1428 0x410F650
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1429 0x410F654
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1430 0x410F658
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1431 0x410F65C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1432 0x410F660
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1433 0x410F664
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1434 0x410F668
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1435 0x410F66C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1436 0x410F670
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1437 0x410F674
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1438 0x410F678
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1439 0x410F67C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1440 0x410F680
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1441 0x410F684
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1442 0x410F688
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1443 0x410F68C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1444 0x410F690
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1445 0x410F694
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1446 0x410F698
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1447 0x410F69C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1448 0x410F6A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1449 0x410F6A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1450 0x410F6A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1451 0x410F6AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1452 0x410F6B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1453 0x410F6B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1454 0x410F6B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1455 0x410F6BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1456 0x410F6C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1457 0x410F6C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1458 0x410F6C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1459 0x410F6CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1460 0x410F6D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1461 0x410F6D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1462 0x410F6D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1463 0x410F6DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1464 0x410F6E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1465 0x410F6E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1466 0x410F6E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1467 0x410F6EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1468 0x410F6F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1469 0x410F6F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1470 0x410F6F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1471 0x410F6FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1472 0x410F700
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1473 0x410F704
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1474 0x410F708
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1475 0x410F70C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1476 0x410F710
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1477 0x410F714
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1478 0x410F718
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1479 0x410F71C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1480 0x410F720
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1481 0x410F724
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1482 0x410F728
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1483 0x410F72C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1484 0x410F730
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1485 0x410F734
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1486 0x410F738
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1487 0x410F73C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1488 0x410F740
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1489 0x410F744
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1490 0x410F748
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1491 0x410F74C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1492 0x410F750
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1493 0x410F754
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1494 0x410F758
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1495 0x410F75C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1496 0x410F760
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1497 0x410F764
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1498 0x410F768
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1499 0x410F76C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1500 0x410F770
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1501 0x410F774
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1502 0x410F778
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1503 0x410F77C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1504 0x410F780
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1505 0x410F784
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1506 0x410F788
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1507 0x410F78C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1508 0x410F790
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1509 0x410F794
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1510 0x410F798
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1511 0x410F79C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1512 0x410F7A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1513 0x410F7A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1514 0x410F7A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1515 0x410F7AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1516 0x410F7B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1517 0x410F7B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1518 0x410F7B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1519 0x410F7BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1520 0x410F7C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1521 0x410F7C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1522 0x410F7C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1523 0x410F7CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1524 0x410F7D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1525 0x410F7D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1526 0x410F7D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1527 0x410F7DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1528 0x410F7E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1529 0x410F7E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1530 0x410F7E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1531 0x410F7EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1532 0x410F7F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1533 0x410F7F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1534 0x410F7F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1535 0x410F7FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1536 0x410F800
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1537 0x410F804
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1538 0x410F808
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1539 0x410F80C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1540 0x410F810
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1541 0x410F814
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1542 0x410F818
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1543 0x410F81C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1544 0x410F820
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1545 0x410F824
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1546 0x410F828
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1547 0x410F82C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1548 0x410F830
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1549 0x410F834
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1550 0x410F838
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1551 0x410F83C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1552 0x410F840
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1553 0x410F844
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1554 0x410F848
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1555 0x410F84C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1556 0x410F850
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1557 0x410F854
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1558 0x410F858
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1559 0x410F85C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1560 0x410F860
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1561 0x410F864
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1562 0x410F868
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1563 0x410F86C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1564 0x410F870
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1565 0x410F874
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1566 0x410F878
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1567 0x410F87C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1568 0x410F880
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1569 0x410F884
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1570 0x410F888
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1571 0x410F88C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1572 0x410F890
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1573 0x410F894
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1574 0x410F898
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1575 0x410F89C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1576 0x410F8A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1577 0x410F8A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1578 0x410F8A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1579 0x410F8AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1580 0x410F8B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1581 0x410F8B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1582 0x410F8B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1583 0x410F8BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1584 0x410F8C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1585 0x410F8C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1586 0x410F8C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1587 0x410F8CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1588 0x410F8D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1589 0x410F8D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1590 0x410F8D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1591 0x410F8DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1592 0x410F8E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1593 0x410F8E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1594 0x410F8E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1595 0x410F8EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1596 0x410F8F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1597 0x410F8F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1598 0x410F8F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1599 0x410F8FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1600 0x410F900
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1601 0x410F904
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1602 0x410F908
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1603 0x410F90C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1604 0x410F910
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1605 0x410F914
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1606 0x410F918
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1607 0x410F91C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1608 0x410F920
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1609 0x410F924
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1610 0x410F928
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1611 0x410F92C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1612 0x410F930
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1613 0x410F934
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1614 0x410F938
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1615 0x410F93C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1616 0x410F940
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1617 0x410F944
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1618 0x410F948
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1619 0x410F94C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1620 0x410F950
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1621 0x410F954
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1622 0x410F958
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1623 0x410F95C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1624 0x410F960
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1625 0x410F964
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1626 0x410F968
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1627 0x410F96C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1628 0x410F970
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1629 0x410F974
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1630 0x410F978
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1631 0x410F97C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1632 0x410F980
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1633 0x410F984
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1634 0x410F988
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1635 0x410F98C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1636 0x410F990
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1637 0x410F994
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1638 0x410F998
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1639 0x410F99C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1640 0x410F9A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1641 0x410F9A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1642 0x410F9A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1643 0x410F9AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1644 0x410F9B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1645 0x410F9B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1646 0x410F9B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1647 0x410F9BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1648 0x410F9C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1649 0x410F9C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1650 0x410F9C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1651 0x410F9CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1652 0x410F9D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1653 0x410F9D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1654 0x410F9D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1655 0x410F9DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1656 0x410F9E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1657 0x410F9E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1658 0x410F9E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1659 0x410F9EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1660 0x410F9F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1661 0x410F9F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1662 0x410F9F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1663 0x410F9FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1664 0x410FA00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1665 0x410FA04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1666 0x410FA08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1667 0x410FA0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1668 0x410FA10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1669 0x410FA14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1670 0x410FA18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1671 0x410FA1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1672 0x410FA20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1673 0x410FA24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1674 0x410FA28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1675 0x410FA2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1676 0x410FA30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1677 0x410FA34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1678 0x410FA38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1679 0x410FA3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1680 0x410FA40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1681 0x410FA44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1682 0x410FA48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1683 0x410FA4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1684 0x410FA50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1685 0x410FA54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1686 0x410FA58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1687 0x410FA5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1688 0x410FA60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1689 0x410FA64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1690 0x410FA68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1691 0x410FA6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1692 0x410FA70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1693 0x410FA74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1694 0x410FA78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1695 0x410FA7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1696 0x410FA80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1697 0x410FA84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1698 0x410FA88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1699 0x410FA8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1700 0x410FA90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1701 0x410FA94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1702 0x410FA98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1703 0x410FA9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1704 0x410FAA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1705 0x410FAA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1706 0x410FAA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1707 0x410FAAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1708 0x410FAB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1709 0x410FAB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1710 0x410FAB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1711 0x410FABC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1712 0x410FAC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1713 0x410FAC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1714 0x410FAC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1715 0x410FACC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1716 0x410FAD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1717 0x410FAD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1718 0x410FAD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1719 0x410FADC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1720 0x410FAE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1721 0x410FAE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1722 0x410FAE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1723 0x410FAEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1724 0x410FAF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1725 0x410FAF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1726 0x410FAF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1727 0x410FAFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1728 0x410FB00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1729 0x410FB04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1730 0x410FB08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1731 0x410FB0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1732 0x410FB10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1733 0x410FB14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1734 0x410FB18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1735 0x410FB1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1736 0x410FB20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1737 0x410FB24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1738 0x410FB28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1739 0x410FB2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1740 0x410FB30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1741 0x410FB34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1742 0x410FB38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1743 0x410FB3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1744 0x410FB40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1745 0x410FB44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1746 0x410FB48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1747 0x410FB4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1748 0x410FB50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1749 0x410FB54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1750 0x410FB58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1751 0x410FB5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1752 0x410FB60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1753 0x410FB64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1754 0x410FB68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1755 0x410FB6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1756 0x410FB70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1757 0x410FB74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1758 0x410FB78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1759 0x410FB7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1760 0x410FB80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1761 0x410FB84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1762 0x410FB88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1763 0x410FB8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1764 0x410FB90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1765 0x410FB94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1766 0x410FB98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1767 0x410FB9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1768 0x410FBA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1769 0x410FBA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1770 0x410FBA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1771 0x410FBAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1772 0x410FBB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1773 0x410FBB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1774 0x410FBB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1775 0x410FBBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1776 0x410FBC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1777 0x410FBC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1778 0x410FBC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1779 0x410FBCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1780 0x410FBD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1781 0x410FBD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1782 0x410FBD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1783 0x410FBDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1784 0x410FBE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1785 0x410FBE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1786 0x410FBE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1787 0x410FBEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1788 0x410FBF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1789 0x410FBF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1790 0x410FBF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1791 0x410FBFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1792 0x410FC00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1793 0x410FC04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1794 0x410FC08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1795 0x410FC0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1796 0x410FC10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1797 0x410FC14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1798 0x410FC18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1799 0x410FC1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1800 0x410FC20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1801 0x410FC24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1802 0x410FC28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1803 0x410FC2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1804 0x410FC30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1805 0x410FC34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1806 0x410FC38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1807 0x410FC3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1808 0x410FC40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1809 0x410FC44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1810 0x410FC48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1811 0x410FC4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1812 0x410FC50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1813 0x410FC54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1814 0x410FC58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1815 0x410FC5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1816 0x410FC60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1817 0x410FC64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1818 0x410FC68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1819 0x410FC6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1820 0x410FC70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1821 0x410FC74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1822 0x410FC78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1823 0x410FC7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1824 0x410FC80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1825 0x410FC84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1826 0x410FC88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1827 0x410FC8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1828 0x410FC90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1829 0x410FC94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1830 0x410FC98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1831 0x410FC9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1832 0x410FCA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1833 0x410FCA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1834 0x410FCA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1835 0x410FCAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1836 0x410FCB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1837 0x410FCB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1838 0x410FCB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1839 0x410FCBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1840 0x410FCC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1841 0x410FCC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1842 0x410FCC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1843 0x410FCCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1844 0x410FCD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1845 0x410FCD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1846 0x410FCD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1847 0x410FCDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1848 0x410FCE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1849 0x410FCE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1850 0x410FCE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1851 0x410FCEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1852 0x410FCF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1853 0x410FCF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1854 0x410FCF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1855 0x410FCFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1856 0x410FD00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1857 0x410FD04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1858 0x410FD08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1859 0x410FD0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1860 0x410FD10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1861 0x410FD14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1862 0x410FD18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1863 0x410FD1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1864 0x410FD20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1865 0x410FD24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1866 0x410FD28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1867 0x410FD2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1868 0x410FD30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1869 0x410FD34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1870 0x410FD38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1871 0x410FD3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1872 0x410FD40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1873 0x410FD44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1874 0x410FD48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1875 0x410FD4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1876 0x410FD50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1877 0x410FD54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1878 0x410FD58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1879 0x410FD5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1880 0x410FD60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1881 0x410FD64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1882 0x410FD68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1883 0x410FD6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1884 0x410FD70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1885 0x410FD74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1886 0x410FD78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1887 0x410FD7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1888 0x410FD80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1889 0x410FD84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1890 0x410FD88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1891 0x410FD8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1892 0x410FD90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1893 0x410FD94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1894 0x410FD98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1895 0x410FD9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1896 0x410FDA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1897 0x410FDA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1898 0x410FDA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1899 0x410FDAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1900 0x410FDB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1901 0x410FDB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1902 0x410FDB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1903 0x410FDBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1904 0x410FDC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1905 0x410FDC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1906 0x410FDC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1907 0x410FDCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1908 0x410FDD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1909 0x410FDD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1910 0x410FDD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1911 0x410FDDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1912 0x410FDE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1913 0x410FDE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1914 0x410FDE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1915 0x410FDEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1916 0x410FDF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1917 0x410FDF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1918 0x410FDF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1919 0x410FDFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1920 0x410FE00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1921 0x410FE04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1922 0x410FE08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1923 0x410FE0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1924 0x410FE10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1925 0x410FE14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1926 0x410FE18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1927 0x410FE1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1928 0x410FE20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1929 0x410FE24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1930 0x410FE28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1931 0x410FE2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1932 0x410FE30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1933 0x410FE34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1934 0x410FE38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1935 0x410FE3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1936 0x410FE40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1937 0x410FE44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1938 0x410FE48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1939 0x410FE4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1940 0x410FE50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1941 0x410FE54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1942 0x410FE58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1943 0x410FE5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1944 0x410FE60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1945 0x410FE64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1946 0x410FE68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1947 0x410FE6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1948 0x410FE70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1949 0x410FE74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1950 0x410FE78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1951 0x410FE7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1952 0x410FE80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1953 0x410FE84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1954 0x410FE88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1955 0x410FE8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1956 0x410FE90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1957 0x410FE94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1958 0x410FE98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1959 0x410FE9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1960 0x410FEA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1961 0x410FEA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1962 0x410FEA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1963 0x410FEAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1964 0x410FEB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1965 0x410FEB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1966 0x410FEB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1967 0x410FEBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1968 0x410FEC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1969 0x410FEC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1970 0x410FEC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1971 0x410FECC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1972 0x410FED0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1973 0x410FED4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1974 0x410FED8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1975 0x410FEDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1976 0x410FEE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1977 0x410FEE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1978 0x410FEE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1979 0x410FEEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1980 0x410FEF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1981 0x410FEF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1982 0x410FEF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1983 0x410FEFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1984 0x410FF00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1985 0x410FF04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1986 0x410FF08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1987 0x410FF0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1988 0x410FF10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1989 0x410FF14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1990 0x410FF18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1991 0x410FF1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1992 0x410FF20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1993 0x410FF24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1994 0x410FF28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1995 0x410FF2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1996 0x410FF30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1997 0x410FF34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1998 0x410FF38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_1999 0x410FF3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2000 0x410FF40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2001 0x410FF44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2002 0x410FF48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2003 0x410FF4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2004 0x410FF50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2005 0x410FF54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2006 0x410FF58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2007 0x410FF5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2008 0x410FF60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2009 0x410FF64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2010 0x410FF68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2011 0x410FF6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2012 0x410FF70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2013 0x410FF74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2014 0x410FF78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2015 0x410FF7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2016 0x410FF80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2017 0x410FF84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2018 0x410FF88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2019 0x410FF8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2020 0x410FF90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2021 0x410FF94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2022 0x410FF98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2023 0x410FF9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2024 0x410FFA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2025 0x410FFA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2026 0x410FFA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2027 0x410FFAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2028 0x410FFB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2029 0x410FFB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2030 0x410FFB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2031 0x410FFBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2032 0x410FFC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2033 0x410FFC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2034 0x410FFC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2035 0x410FFCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2036 0x410FFD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2037 0x410FFD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2038 0x410FFD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2039 0x410FFDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2040 0x410FFE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2041 0x410FFE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2042 0x410FFE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2043 0x410FFEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2044 0x410FFF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2045 0x410FFF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2046 0x410FFF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_2047 0x410FFFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_0 0x4110000
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1 0x4110004
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2 0x4110008
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_3 0x411000C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_4 0x4110010
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_5 0x4110014
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_6 0x4110018
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_7 0x411001C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_8 0x4110020
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_9 0x4110024
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_10 0x4110028
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_11 0x411002C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_12 0x4110030
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_13 0x4110034
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_14 0x4110038
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_15 0x411003C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_16 0x4110040
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_17 0x4110044
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_18 0x4110048
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_19 0x411004C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_20 0x4110050
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_21 0x4110054
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_22 0x4110058
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_23 0x411005C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_24 0x4110060
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_25 0x4110064
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_26 0x4110068
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_27 0x411006C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_28 0x4110070
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_29 0x4110074
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_30 0x4110078
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_31 0x411007C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_32 0x4110080
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_33 0x4110084
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_34 0x4110088
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_35 0x411008C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_36 0x4110090
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_37 0x4110094
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_38 0x4110098
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_39 0x411009C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_40 0x41100A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_41 0x41100A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_42 0x41100A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_43 0x41100AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_44 0x41100B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_45 0x41100B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_46 0x41100B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_47 0x41100BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_48 0x41100C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_49 0x41100C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_50 0x41100C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_51 0x41100CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_52 0x41100D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_53 0x41100D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_54 0x41100D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_55 0x41100DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_56 0x41100E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_57 0x41100E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_58 0x41100E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_59 0x41100EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_60 0x41100F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_61 0x41100F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_62 0x41100F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_63 0x41100FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_64 0x4110100
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_65 0x4110104
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_66 0x4110108
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_67 0x411010C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_68 0x4110110
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_69 0x4110114
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_70 0x4110118
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_71 0x411011C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_72 0x4110120
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_73 0x4110124
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_74 0x4110128
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_75 0x411012C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_76 0x4110130
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_77 0x4110134
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_78 0x4110138
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_79 0x411013C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_80 0x4110140
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_81 0x4110144
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_82 0x4110148
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_83 0x411014C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_84 0x4110150
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_85 0x4110154
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_86 0x4110158
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_87 0x411015C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_88 0x4110160
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_89 0x4110164
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_90 0x4110168
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_91 0x411016C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_92 0x4110170
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_93 0x4110174
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_94 0x4110178
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_95 0x411017C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_96 0x4110180
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_97 0x4110184
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_98 0x4110188
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_99 0x411018C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_100 0x4110190
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_101 0x4110194
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_102 0x4110198
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_103 0x411019C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_104 0x41101A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_105 0x41101A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_106 0x41101A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_107 0x41101AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_108 0x41101B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_109 0x41101B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_110 0x41101B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_111 0x41101BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_112 0x41101C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_113 0x41101C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_114 0x41101C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_115 0x41101CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_116 0x41101D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_117 0x41101D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_118 0x41101D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_119 0x41101DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_120 0x41101E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_121 0x41101E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_122 0x41101E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_123 0x41101EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_124 0x41101F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_125 0x41101F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_126 0x41101F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_127 0x41101FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_128 0x4110200
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_129 0x4110204
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_130 0x4110208
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_131 0x411020C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_132 0x4110210
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_133 0x4110214
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_134 0x4110218
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_135 0x411021C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_136 0x4110220
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_137 0x4110224
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_138 0x4110228
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_139 0x411022C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_140 0x4110230
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_141 0x4110234
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_142 0x4110238
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_143 0x411023C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_144 0x4110240
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_145 0x4110244
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_146 0x4110248
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_147 0x411024C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_148 0x4110250
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_149 0x4110254
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_150 0x4110258
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_151 0x411025C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_152 0x4110260
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_153 0x4110264
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_154 0x4110268
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_155 0x411026C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_156 0x4110270
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_157 0x4110274
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_158 0x4110278
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_159 0x411027C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_160 0x4110280
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_161 0x4110284
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_162 0x4110288
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_163 0x411028C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_164 0x4110290
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_165 0x4110294
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_166 0x4110298
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_167 0x411029C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_168 0x41102A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_169 0x41102A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_170 0x41102A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_171 0x41102AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_172 0x41102B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_173 0x41102B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_174 0x41102B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_175 0x41102BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_176 0x41102C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_177 0x41102C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_178 0x41102C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_179 0x41102CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_180 0x41102D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_181 0x41102D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_182 0x41102D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_183 0x41102DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_184 0x41102E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_185 0x41102E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_186 0x41102E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_187 0x41102EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_188 0x41102F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_189 0x41102F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_190 0x41102F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_191 0x41102FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_192 0x4110300
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_193 0x4110304
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_194 0x4110308
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_195 0x411030C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_196 0x4110310
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_197 0x4110314
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_198 0x4110318
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_199 0x411031C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_200 0x4110320
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_201 0x4110324
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_202 0x4110328
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_203 0x411032C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_204 0x4110330
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_205 0x4110334
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_206 0x4110338
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_207 0x411033C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_208 0x4110340
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_209 0x4110344
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_210 0x4110348
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_211 0x411034C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_212 0x4110350
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_213 0x4110354
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_214 0x4110358
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_215 0x411035C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_216 0x4110360
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_217 0x4110364
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_218 0x4110368
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_219 0x411036C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_220 0x4110370
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_221 0x4110374
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_222 0x4110378
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_223 0x411037C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_224 0x4110380
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_225 0x4110384
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_226 0x4110388
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_227 0x411038C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_228 0x4110390
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_229 0x4110394
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_230 0x4110398
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_231 0x411039C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_232 0x41103A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_233 0x41103A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_234 0x41103A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_235 0x41103AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_236 0x41103B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_237 0x41103B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_238 0x41103B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_239 0x41103BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_240 0x41103C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_241 0x41103C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_242 0x41103C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_243 0x41103CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_244 0x41103D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_245 0x41103D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_246 0x41103D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_247 0x41103DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_248 0x41103E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_249 0x41103E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_250 0x41103E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_251 0x41103EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_252 0x41103F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_253 0x41103F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_254 0x41103F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_255 0x41103FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_256 0x4110400
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_257 0x4110404
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_258 0x4110408
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_259 0x411040C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_260 0x4110410
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_261 0x4110414
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_262 0x4110418
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_263 0x411041C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_264 0x4110420
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_265 0x4110424
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_266 0x4110428
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_267 0x411042C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_268 0x4110430
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_269 0x4110434
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_270 0x4110438
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_271 0x411043C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_272 0x4110440
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_273 0x4110444
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_274 0x4110448
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_275 0x411044C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_276 0x4110450
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_277 0x4110454
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_278 0x4110458
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_279 0x411045C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_280 0x4110460
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_281 0x4110464
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_282 0x4110468
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_283 0x411046C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_284 0x4110470
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_285 0x4110474
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_286 0x4110478
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_287 0x411047C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_288 0x4110480
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_289 0x4110484
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_290 0x4110488
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_291 0x411048C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_292 0x4110490
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_293 0x4110494
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_294 0x4110498
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_295 0x411049C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_296 0x41104A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_297 0x41104A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_298 0x41104A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_299 0x41104AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_300 0x41104B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_301 0x41104B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_302 0x41104B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_303 0x41104BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_304 0x41104C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_305 0x41104C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_306 0x41104C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_307 0x41104CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_308 0x41104D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_309 0x41104D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_310 0x41104D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_311 0x41104DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_312 0x41104E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_313 0x41104E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_314 0x41104E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_315 0x41104EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_316 0x41104F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_317 0x41104F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_318 0x41104F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_319 0x41104FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_320 0x4110500
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_321 0x4110504
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_322 0x4110508
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_323 0x411050C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_324 0x4110510
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_325 0x4110514
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_326 0x4110518
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_327 0x411051C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_328 0x4110520
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_329 0x4110524
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_330 0x4110528
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_331 0x411052C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_332 0x4110530
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_333 0x4110534
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_334 0x4110538
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_335 0x411053C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_336 0x4110540
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_337 0x4110544
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_338 0x4110548
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_339 0x411054C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_340 0x4110550
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_341 0x4110554
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_342 0x4110558
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_343 0x411055C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_344 0x4110560
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_345 0x4110564
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_346 0x4110568
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_347 0x411056C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_348 0x4110570
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_349 0x4110574
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_350 0x4110578
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_351 0x411057C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_352 0x4110580
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_353 0x4110584
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_354 0x4110588
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_355 0x411058C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_356 0x4110590
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_357 0x4110594
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_358 0x4110598
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_359 0x411059C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_360 0x41105A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_361 0x41105A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_362 0x41105A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_363 0x41105AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_364 0x41105B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_365 0x41105B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_366 0x41105B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_367 0x41105BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_368 0x41105C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_369 0x41105C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_370 0x41105C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_371 0x41105CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_372 0x41105D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_373 0x41105D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_374 0x41105D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_375 0x41105DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_376 0x41105E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_377 0x41105E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_378 0x41105E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_379 0x41105EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_380 0x41105F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_381 0x41105F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_382 0x41105F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_383 0x41105FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_384 0x4110600
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_385 0x4110604
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_386 0x4110608
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_387 0x411060C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_388 0x4110610
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_389 0x4110614
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_390 0x4110618
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_391 0x411061C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_392 0x4110620
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_393 0x4110624
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_394 0x4110628
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_395 0x411062C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_396 0x4110630
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_397 0x4110634
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_398 0x4110638
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_399 0x411063C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_400 0x4110640
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_401 0x4110644
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_402 0x4110648
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_403 0x411064C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_404 0x4110650
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_405 0x4110654
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_406 0x4110658
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_407 0x411065C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_408 0x4110660
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_409 0x4110664
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_410 0x4110668
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_411 0x411066C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_412 0x4110670
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_413 0x4110674
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_414 0x4110678
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_415 0x411067C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_416 0x4110680
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_417 0x4110684
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_418 0x4110688
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_419 0x411068C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_420 0x4110690
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_421 0x4110694
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_422 0x4110698
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_423 0x411069C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_424 0x41106A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_425 0x41106A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_426 0x41106A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_427 0x41106AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_428 0x41106B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_429 0x41106B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_430 0x41106B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_431 0x41106BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_432 0x41106C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_433 0x41106C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_434 0x41106C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_435 0x41106CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_436 0x41106D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_437 0x41106D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_438 0x41106D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_439 0x41106DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_440 0x41106E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_441 0x41106E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_442 0x41106E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_443 0x41106EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_444 0x41106F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_445 0x41106F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_446 0x41106F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_447 0x41106FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_448 0x4110700
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_449 0x4110704
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_450 0x4110708
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_451 0x411070C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_452 0x4110710
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_453 0x4110714
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_454 0x4110718
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_455 0x411071C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_456 0x4110720
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_457 0x4110724
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_458 0x4110728
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_459 0x411072C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_460 0x4110730
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_461 0x4110734
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_462 0x4110738
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_463 0x411073C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_464 0x4110740
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_465 0x4110744
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_466 0x4110748
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_467 0x411074C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_468 0x4110750
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_469 0x4110754
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_470 0x4110758
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_471 0x411075C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_472 0x4110760
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_473 0x4110764
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_474 0x4110768
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_475 0x411076C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_476 0x4110770
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_477 0x4110774
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_478 0x4110778
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_479 0x411077C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_480 0x4110780
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_481 0x4110784
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_482 0x4110788
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_483 0x411078C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_484 0x4110790
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_485 0x4110794
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_486 0x4110798
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_487 0x411079C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_488 0x41107A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_489 0x41107A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_490 0x41107A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_491 0x41107AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_492 0x41107B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_493 0x41107B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_494 0x41107B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_495 0x41107BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_496 0x41107C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_497 0x41107C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_498 0x41107C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_499 0x41107CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_500 0x41107D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_501 0x41107D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_502 0x41107D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_503 0x41107DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_504 0x41107E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_505 0x41107E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_506 0x41107E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_507 0x41107EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_508 0x41107F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_509 0x41107F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_510 0x41107F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_511 0x41107FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_512 0x4110800
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_513 0x4110804
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_514 0x4110808
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_515 0x411080C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_516 0x4110810
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_517 0x4110814
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_518 0x4110818
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_519 0x411081C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_520 0x4110820
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_521 0x4110824
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_522 0x4110828
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_523 0x411082C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_524 0x4110830
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_525 0x4110834
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_526 0x4110838
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_527 0x411083C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_528 0x4110840
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_529 0x4110844
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_530 0x4110848
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_531 0x411084C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_532 0x4110850
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_533 0x4110854
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_534 0x4110858
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_535 0x411085C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_536 0x4110860
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_537 0x4110864
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_538 0x4110868
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_539 0x411086C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_540 0x4110870
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_541 0x4110874
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_542 0x4110878
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_543 0x411087C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_544 0x4110880
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_545 0x4110884
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_546 0x4110888
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_547 0x411088C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_548 0x4110890
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_549 0x4110894
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_550 0x4110898
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_551 0x411089C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_552 0x41108A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_553 0x41108A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_554 0x41108A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_555 0x41108AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_556 0x41108B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_557 0x41108B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_558 0x41108B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_559 0x41108BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_560 0x41108C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_561 0x41108C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_562 0x41108C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_563 0x41108CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_564 0x41108D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_565 0x41108D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_566 0x41108D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_567 0x41108DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_568 0x41108E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_569 0x41108E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_570 0x41108E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_571 0x41108EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_572 0x41108F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_573 0x41108F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_574 0x41108F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_575 0x41108FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_576 0x4110900
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_577 0x4110904
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_578 0x4110908
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_579 0x411090C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_580 0x4110910
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_581 0x4110914
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_582 0x4110918
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_583 0x411091C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_584 0x4110920
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_585 0x4110924
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_586 0x4110928
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_587 0x411092C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_588 0x4110930
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_589 0x4110934
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_590 0x4110938
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_591 0x411093C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_592 0x4110940
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_593 0x4110944
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_594 0x4110948
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_595 0x411094C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_596 0x4110950
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_597 0x4110954
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_598 0x4110958
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_599 0x411095C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_600 0x4110960
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_601 0x4110964
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_602 0x4110968
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_603 0x411096C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_604 0x4110970
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_605 0x4110974
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_606 0x4110978
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_607 0x411097C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_608 0x4110980
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_609 0x4110984
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_610 0x4110988
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_611 0x411098C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_612 0x4110990
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_613 0x4110994
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_614 0x4110998
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_615 0x411099C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_616 0x41109A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_617 0x41109A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_618 0x41109A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_619 0x41109AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_620 0x41109B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_621 0x41109B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_622 0x41109B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_623 0x41109BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_624 0x41109C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_625 0x41109C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_626 0x41109C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_627 0x41109CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_628 0x41109D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_629 0x41109D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_630 0x41109D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_631 0x41109DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_632 0x41109E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_633 0x41109E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_634 0x41109E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_635 0x41109EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_636 0x41109F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_637 0x41109F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_638 0x41109F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_639 0x41109FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_640 0x4110A00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_641 0x4110A04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_642 0x4110A08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_643 0x4110A0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_644 0x4110A10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_645 0x4110A14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_646 0x4110A18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_647 0x4110A1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_648 0x4110A20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_649 0x4110A24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_650 0x4110A28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_651 0x4110A2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_652 0x4110A30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_653 0x4110A34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_654 0x4110A38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_655 0x4110A3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_656 0x4110A40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_657 0x4110A44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_658 0x4110A48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_659 0x4110A4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_660 0x4110A50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_661 0x4110A54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_662 0x4110A58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_663 0x4110A5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_664 0x4110A60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_665 0x4110A64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_666 0x4110A68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_667 0x4110A6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_668 0x4110A70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_669 0x4110A74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_670 0x4110A78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_671 0x4110A7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_672 0x4110A80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_673 0x4110A84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_674 0x4110A88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_675 0x4110A8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_676 0x4110A90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_677 0x4110A94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_678 0x4110A98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_679 0x4110A9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_680 0x4110AA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_681 0x4110AA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_682 0x4110AA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_683 0x4110AAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_684 0x4110AB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_685 0x4110AB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_686 0x4110AB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_687 0x4110ABC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_688 0x4110AC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_689 0x4110AC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_690 0x4110AC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_691 0x4110ACC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_692 0x4110AD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_693 0x4110AD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_694 0x4110AD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_695 0x4110ADC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_696 0x4110AE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_697 0x4110AE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_698 0x4110AE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_699 0x4110AEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_700 0x4110AF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_701 0x4110AF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_702 0x4110AF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_703 0x4110AFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_704 0x4110B00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_705 0x4110B04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_706 0x4110B08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_707 0x4110B0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_708 0x4110B10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_709 0x4110B14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_710 0x4110B18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_711 0x4110B1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_712 0x4110B20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_713 0x4110B24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_714 0x4110B28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_715 0x4110B2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_716 0x4110B30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_717 0x4110B34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_718 0x4110B38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_719 0x4110B3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_720 0x4110B40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_721 0x4110B44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_722 0x4110B48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_723 0x4110B4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_724 0x4110B50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_725 0x4110B54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_726 0x4110B58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_727 0x4110B5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_728 0x4110B60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_729 0x4110B64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_730 0x4110B68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_731 0x4110B6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_732 0x4110B70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_733 0x4110B74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_734 0x4110B78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_735 0x4110B7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_736 0x4110B80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_737 0x4110B84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_738 0x4110B88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_739 0x4110B8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_740 0x4110B90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_741 0x4110B94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_742 0x4110B98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_743 0x4110B9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_744 0x4110BA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_745 0x4110BA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_746 0x4110BA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_747 0x4110BAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_748 0x4110BB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_749 0x4110BB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_750 0x4110BB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_751 0x4110BBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_752 0x4110BC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_753 0x4110BC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_754 0x4110BC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_755 0x4110BCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_756 0x4110BD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_757 0x4110BD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_758 0x4110BD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_759 0x4110BDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_760 0x4110BE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_761 0x4110BE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_762 0x4110BE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_763 0x4110BEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_764 0x4110BF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_765 0x4110BF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_766 0x4110BF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_767 0x4110BFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_768 0x4110C00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_769 0x4110C04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_770 0x4110C08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_771 0x4110C0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_772 0x4110C10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_773 0x4110C14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_774 0x4110C18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_775 0x4110C1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_776 0x4110C20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_777 0x4110C24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_778 0x4110C28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_779 0x4110C2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_780 0x4110C30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_781 0x4110C34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_782 0x4110C38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_783 0x4110C3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_784 0x4110C40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_785 0x4110C44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_786 0x4110C48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_787 0x4110C4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_788 0x4110C50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_789 0x4110C54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_790 0x4110C58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_791 0x4110C5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_792 0x4110C60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_793 0x4110C64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_794 0x4110C68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_795 0x4110C6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_796 0x4110C70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_797 0x4110C74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_798 0x4110C78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_799 0x4110C7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_800 0x4110C80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_801 0x4110C84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_802 0x4110C88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_803 0x4110C8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_804 0x4110C90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_805 0x4110C94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_806 0x4110C98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_807 0x4110C9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_808 0x4110CA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_809 0x4110CA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_810 0x4110CA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_811 0x4110CAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_812 0x4110CB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_813 0x4110CB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_814 0x4110CB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_815 0x4110CBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_816 0x4110CC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_817 0x4110CC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_818 0x4110CC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_819 0x4110CCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_820 0x4110CD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_821 0x4110CD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_822 0x4110CD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_823 0x4110CDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_824 0x4110CE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_825 0x4110CE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_826 0x4110CE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_827 0x4110CEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_828 0x4110CF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_829 0x4110CF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_830 0x4110CF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_831 0x4110CFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_832 0x4110D00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_833 0x4110D04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_834 0x4110D08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_835 0x4110D0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_836 0x4110D10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_837 0x4110D14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_838 0x4110D18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_839 0x4110D1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_840 0x4110D20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_841 0x4110D24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_842 0x4110D28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_843 0x4110D2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_844 0x4110D30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_845 0x4110D34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_846 0x4110D38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_847 0x4110D3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_848 0x4110D40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_849 0x4110D44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_850 0x4110D48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_851 0x4110D4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_852 0x4110D50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_853 0x4110D54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_854 0x4110D58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_855 0x4110D5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_856 0x4110D60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_857 0x4110D64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_858 0x4110D68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_859 0x4110D6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_860 0x4110D70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_861 0x4110D74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_862 0x4110D78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_863 0x4110D7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_864 0x4110D80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_865 0x4110D84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_866 0x4110D88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_867 0x4110D8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_868 0x4110D90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_869 0x4110D94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_870 0x4110D98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_871 0x4110D9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_872 0x4110DA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_873 0x4110DA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_874 0x4110DA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_875 0x4110DAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_876 0x4110DB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_877 0x4110DB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_878 0x4110DB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_879 0x4110DBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_880 0x4110DC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_881 0x4110DC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_882 0x4110DC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_883 0x4110DCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_884 0x4110DD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_885 0x4110DD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_886 0x4110DD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_887 0x4110DDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_888 0x4110DE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_889 0x4110DE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_890 0x4110DE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_891 0x4110DEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_892 0x4110DF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_893 0x4110DF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_894 0x4110DF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_895 0x4110DFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_896 0x4110E00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_897 0x4110E04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_898 0x4110E08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_899 0x4110E0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_900 0x4110E10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_901 0x4110E14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_902 0x4110E18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_903 0x4110E1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_904 0x4110E20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_905 0x4110E24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_906 0x4110E28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_907 0x4110E2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_908 0x4110E30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_909 0x4110E34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_910 0x4110E38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_911 0x4110E3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_912 0x4110E40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_913 0x4110E44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_914 0x4110E48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_915 0x4110E4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_916 0x4110E50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_917 0x4110E54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_918 0x4110E58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_919 0x4110E5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_920 0x4110E60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_921 0x4110E64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_922 0x4110E68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_923 0x4110E6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_924 0x4110E70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_925 0x4110E74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_926 0x4110E78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_927 0x4110E7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_928 0x4110E80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_929 0x4110E84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_930 0x4110E88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_931 0x4110E8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_932 0x4110E90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_933 0x4110E94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_934 0x4110E98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_935 0x4110E9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_936 0x4110EA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_937 0x4110EA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_938 0x4110EA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_939 0x4110EAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_940 0x4110EB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_941 0x4110EB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_942 0x4110EB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_943 0x4110EBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_944 0x4110EC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_945 0x4110EC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_946 0x4110EC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_947 0x4110ECC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_948 0x4110ED0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_949 0x4110ED4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_950 0x4110ED8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_951 0x4110EDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_952 0x4110EE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_953 0x4110EE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_954 0x4110EE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_955 0x4110EEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_956 0x4110EF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_957 0x4110EF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_958 0x4110EF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_959 0x4110EFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_960 0x4110F00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_961 0x4110F04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_962 0x4110F08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_963 0x4110F0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_964 0x4110F10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_965 0x4110F14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_966 0x4110F18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_967 0x4110F1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_968 0x4110F20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_969 0x4110F24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_970 0x4110F28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_971 0x4110F2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_972 0x4110F30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_973 0x4110F34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_974 0x4110F38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_975 0x4110F3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_976 0x4110F40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_977 0x4110F44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_978 0x4110F48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_979 0x4110F4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_980 0x4110F50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_981 0x4110F54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_982 0x4110F58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_983 0x4110F5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_984 0x4110F60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_985 0x4110F64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_986 0x4110F68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_987 0x4110F6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_988 0x4110F70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_989 0x4110F74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_990 0x4110F78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_991 0x4110F7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_992 0x4110F80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_993 0x4110F84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_994 0x4110F88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_995 0x4110F8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_996 0x4110F90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_997 0x4110F94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_998 0x4110F98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_999 0x4110F9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1000 0x4110FA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1001 0x4110FA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1002 0x4110FA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1003 0x4110FAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1004 0x4110FB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1005 0x4110FB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1006 0x4110FB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1007 0x4110FBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1008 0x4110FC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1009 0x4110FC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1010 0x4110FC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1011 0x4110FCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1012 0x4110FD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1013 0x4110FD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1014 0x4110FD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1015 0x4110FDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1016 0x4110FE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1017 0x4110FE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1018 0x4110FE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1019 0x4110FEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1020 0x4110FF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1021 0x4110FF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1022 0x4110FF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1023 0x4110FFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1024 0x4111000
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1025 0x4111004
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1026 0x4111008
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1027 0x411100C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1028 0x4111010
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1029 0x4111014
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1030 0x4111018
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1031 0x411101C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1032 0x4111020
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1033 0x4111024
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1034 0x4111028
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1035 0x411102C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1036 0x4111030
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1037 0x4111034
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1038 0x4111038
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1039 0x411103C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1040 0x4111040
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1041 0x4111044
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1042 0x4111048
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1043 0x411104C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1044 0x4111050
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1045 0x4111054
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1046 0x4111058
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1047 0x411105C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1048 0x4111060
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1049 0x4111064
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1050 0x4111068
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1051 0x411106C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1052 0x4111070
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1053 0x4111074
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1054 0x4111078
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1055 0x411107C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1056 0x4111080
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1057 0x4111084
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1058 0x4111088
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1059 0x411108C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1060 0x4111090
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1061 0x4111094
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1062 0x4111098
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1063 0x411109C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1064 0x41110A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1065 0x41110A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1066 0x41110A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1067 0x41110AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1068 0x41110B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1069 0x41110B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1070 0x41110B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1071 0x41110BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1072 0x41110C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1073 0x41110C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1074 0x41110C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1075 0x41110CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1076 0x41110D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1077 0x41110D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1078 0x41110D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1079 0x41110DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1080 0x41110E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1081 0x41110E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1082 0x41110E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1083 0x41110EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1084 0x41110F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1085 0x41110F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1086 0x41110F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1087 0x41110FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1088 0x4111100
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1089 0x4111104
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1090 0x4111108
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1091 0x411110C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1092 0x4111110
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1093 0x4111114
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1094 0x4111118
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1095 0x411111C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1096 0x4111120
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1097 0x4111124
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1098 0x4111128
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1099 0x411112C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1100 0x4111130
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1101 0x4111134
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1102 0x4111138
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1103 0x411113C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1104 0x4111140
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1105 0x4111144
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1106 0x4111148
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1107 0x411114C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1108 0x4111150
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1109 0x4111154
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1110 0x4111158
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1111 0x411115C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1112 0x4111160
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1113 0x4111164
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1114 0x4111168
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1115 0x411116C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1116 0x4111170
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1117 0x4111174
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1118 0x4111178
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1119 0x411117C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1120 0x4111180
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1121 0x4111184
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1122 0x4111188
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1123 0x411118C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1124 0x4111190
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1125 0x4111194
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1126 0x4111198
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1127 0x411119C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1128 0x41111A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1129 0x41111A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1130 0x41111A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1131 0x41111AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1132 0x41111B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1133 0x41111B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1134 0x41111B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1135 0x41111BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1136 0x41111C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1137 0x41111C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1138 0x41111C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1139 0x41111CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1140 0x41111D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1141 0x41111D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1142 0x41111D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1143 0x41111DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1144 0x41111E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1145 0x41111E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1146 0x41111E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1147 0x41111EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1148 0x41111F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1149 0x41111F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1150 0x41111F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1151 0x41111FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1152 0x4111200
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1153 0x4111204
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1154 0x4111208
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1155 0x411120C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1156 0x4111210
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1157 0x4111214
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1158 0x4111218
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1159 0x411121C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1160 0x4111220
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1161 0x4111224
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1162 0x4111228
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1163 0x411122C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1164 0x4111230
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1165 0x4111234
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1166 0x4111238
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1167 0x411123C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1168 0x4111240
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1169 0x4111244
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1170 0x4111248
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1171 0x411124C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1172 0x4111250
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1173 0x4111254
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1174 0x4111258
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1175 0x411125C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1176 0x4111260
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1177 0x4111264
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1178 0x4111268
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1179 0x411126C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1180 0x4111270
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1181 0x4111274
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1182 0x4111278
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1183 0x411127C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1184 0x4111280
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1185 0x4111284
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1186 0x4111288
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1187 0x411128C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1188 0x4111290
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1189 0x4111294
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1190 0x4111298
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1191 0x411129C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1192 0x41112A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1193 0x41112A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1194 0x41112A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1195 0x41112AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1196 0x41112B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1197 0x41112B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1198 0x41112B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1199 0x41112BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1200 0x41112C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1201 0x41112C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1202 0x41112C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1203 0x41112CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1204 0x41112D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1205 0x41112D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1206 0x41112D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1207 0x41112DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1208 0x41112E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1209 0x41112E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1210 0x41112E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1211 0x41112EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1212 0x41112F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1213 0x41112F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1214 0x41112F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1215 0x41112FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1216 0x4111300
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1217 0x4111304
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1218 0x4111308
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1219 0x411130C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1220 0x4111310
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1221 0x4111314
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1222 0x4111318
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1223 0x411131C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1224 0x4111320
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1225 0x4111324
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1226 0x4111328
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1227 0x411132C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1228 0x4111330
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1229 0x4111334
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1230 0x4111338
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1231 0x411133C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1232 0x4111340
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1233 0x4111344
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1234 0x4111348
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1235 0x411134C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1236 0x4111350
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1237 0x4111354
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1238 0x4111358
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1239 0x411135C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1240 0x4111360
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1241 0x4111364
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1242 0x4111368
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1243 0x411136C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1244 0x4111370
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1245 0x4111374
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1246 0x4111378
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1247 0x411137C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1248 0x4111380
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1249 0x4111384
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1250 0x4111388
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1251 0x411138C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1252 0x4111390
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1253 0x4111394
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1254 0x4111398
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1255 0x411139C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1256 0x41113A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1257 0x41113A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1258 0x41113A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1259 0x41113AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1260 0x41113B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1261 0x41113B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1262 0x41113B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1263 0x41113BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1264 0x41113C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1265 0x41113C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1266 0x41113C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1267 0x41113CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1268 0x41113D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1269 0x41113D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1270 0x41113D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1271 0x41113DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1272 0x41113E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1273 0x41113E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1274 0x41113E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1275 0x41113EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1276 0x41113F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1277 0x41113F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1278 0x41113F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1279 0x41113FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1280 0x4111400
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1281 0x4111404
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1282 0x4111408
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1283 0x411140C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1284 0x4111410
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1285 0x4111414
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1286 0x4111418
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1287 0x411141C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1288 0x4111420
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1289 0x4111424
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1290 0x4111428
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1291 0x411142C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1292 0x4111430
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1293 0x4111434
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1294 0x4111438
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1295 0x411143C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1296 0x4111440
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1297 0x4111444
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1298 0x4111448
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1299 0x411144C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1300 0x4111450
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1301 0x4111454
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1302 0x4111458
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1303 0x411145C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1304 0x4111460
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1305 0x4111464
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1306 0x4111468
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1307 0x411146C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1308 0x4111470
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1309 0x4111474
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1310 0x4111478
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1311 0x411147C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1312 0x4111480
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1313 0x4111484
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1314 0x4111488
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1315 0x411148C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1316 0x4111490
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1317 0x4111494
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1318 0x4111498
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1319 0x411149C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1320 0x41114A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1321 0x41114A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1322 0x41114A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1323 0x41114AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1324 0x41114B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1325 0x41114B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1326 0x41114B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1327 0x41114BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1328 0x41114C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1329 0x41114C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1330 0x41114C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1331 0x41114CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1332 0x41114D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1333 0x41114D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1334 0x41114D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1335 0x41114DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1336 0x41114E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1337 0x41114E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1338 0x41114E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1339 0x41114EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1340 0x41114F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1341 0x41114F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1342 0x41114F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1343 0x41114FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1344 0x4111500
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1345 0x4111504
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1346 0x4111508
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1347 0x411150C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1348 0x4111510
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1349 0x4111514
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1350 0x4111518
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1351 0x411151C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1352 0x4111520
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1353 0x4111524
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1354 0x4111528
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1355 0x411152C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1356 0x4111530
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1357 0x4111534
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1358 0x4111538
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1359 0x411153C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1360 0x4111540
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1361 0x4111544
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1362 0x4111548
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1363 0x411154C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1364 0x4111550
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1365 0x4111554
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1366 0x4111558
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1367 0x411155C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1368 0x4111560
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1369 0x4111564
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1370 0x4111568
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1371 0x411156C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1372 0x4111570
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1373 0x4111574
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1374 0x4111578
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1375 0x411157C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1376 0x4111580
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1377 0x4111584
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1378 0x4111588
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1379 0x411158C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1380 0x4111590
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1381 0x4111594
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1382 0x4111598
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1383 0x411159C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1384 0x41115A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1385 0x41115A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1386 0x41115A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1387 0x41115AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1388 0x41115B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1389 0x41115B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1390 0x41115B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1391 0x41115BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1392 0x41115C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1393 0x41115C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1394 0x41115C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1395 0x41115CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1396 0x41115D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1397 0x41115D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1398 0x41115D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1399 0x41115DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1400 0x41115E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1401 0x41115E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1402 0x41115E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1403 0x41115EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1404 0x41115F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1405 0x41115F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1406 0x41115F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1407 0x41115FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1408 0x4111600
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1409 0x4111604
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1410 0x4111608
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1411 0x411160C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1412 0x4111610
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1413 0x4111614
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1414 0x4111618
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1415 0x411161C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1416 0x4111620
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1417 0x4111624
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1418 0x4111628
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1419 0x411162C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1420 0x4111630
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1421 0x4111634
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1422 0x4111638
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1423 0x411163C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1424 0x4111640
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1425 0x4111644
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1426 0x4111648
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1427 0x411164C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1428 0x4111650
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1429 0x4111654
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1430 0x4111658
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1431 0x411165C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1432 0x4111660
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1433 0x4111664
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1434 0x4111668
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1435 0x411166C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1436 0x4111670
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1437 0x4111674
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1438 0x4111678
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1439 0x411167C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1440 0x4111680
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1441 0x4111684
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1442 0x4111688
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1443 0x411168C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1444 0x4111690
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1445 0x4111694
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1446 0x4111698
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1447 0x411169C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1448 0x41116A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1449 0x41116A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1450 0x41116A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1451 0x41116AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1452 0x41116B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1453 0x41116B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1454 0x41116B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1455 0x41116BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1456 0x41116C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1457 0x41116C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1458 0x41116C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1459 0x41116CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1460 0x41116D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1461 0x41116D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1462 0x41116D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1463 0x41116DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1464 0x41116E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1465 0x41116E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1466 0x41116E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1467 0x41116EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1468 0x41116F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1469 0x41116F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1470 0x41116F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1471 0x41116FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1472 0x4111700
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1473 0x4111704
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1474 0x4111708
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1475 0x411170C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1476 0x4111710
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1477 0x4111714
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1478 0x4111718
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1479 0x411171C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1480 0x4111720
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1481 0x4111724
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1482 0x4111728
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1483 0x411172C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1484 0x4111730
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1485 0x4111734
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1486 0x4111738
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1487 0x411173C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1488 0x4111740
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1489 0x4111744
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1490 0x4111748
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1491 0x411174C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1492 0x4111750
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1493 0x4111754
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1494 0x4111758
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1495 0x411175C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1496 0x4111760
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1497 0x4111764
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1498 0x4111768
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1499 0x411176C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1500 0x4111770
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1501 0x4111774
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1502 0x4111778
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1503 0x411177C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1504 0x4111780
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1505 0x4111784
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1506 0x4111788
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1507 0x411178C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1508 0x4111790
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1509 0x4111794
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1510 0x4111798
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1511 0x411179C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1512 0x41117A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1513 0x41117A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1514 0x41117A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1515 0x41117AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1516 0x41117B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1517 0x41117B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1518 0x41117B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1519 0x41117BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1520 0x41117C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1521 0x41117C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1522 0x41117C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1523 0x41117CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1524 0x41117D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1525 0x41117D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1526 0x41117D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1527 0x41117DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1528 0x41117E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1529 0x41117E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1530 0x41117E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1531 0x41117EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1532 0x41117F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1533 0x41117F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1534 0x41117F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1535 0x41117FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1536 0x4111800
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1537 0x4111804
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1538 0x4111808
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1539 0x411180C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1540 0x4111810
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1541 0x4111814
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1542 0x4111818
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1543 0x411181C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1544 0x4111820
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1545 0x4111824
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1546 0x4111828
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1547 0x411182C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1548 0x4111830
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1549 0x4111834
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1550 0x4111838
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1551 0x411183C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1552 0x4111840
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1553 0x4111844
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1554 0x4111848
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1555 0x411184C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1556 0x4111850
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1557 0x4111854
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1558 0x4111858
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1559 0x411185C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1560 0x4111860
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1561 0x4111864
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1562 0x4111868
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1563 0x411186C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1564 0x4111870
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1565 0x4111874
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1566 0x4111878
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1567 0x411187C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1568 0x4111880
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1569 0x4111884
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1570 0x4111888
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1571 0x411188C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1572 0x4111890
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1573 0x4111894
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1574 0x4111898
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1575 0x411189C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1576 0x41118A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1577 0x41118A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1578 0x41118A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1579 0x41118AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1580 0x41118B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1581 0x41118B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1582 0x41118B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1583 0x41118BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1584 0x41118C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1585 0x41118C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1586 0x41118C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1587 0x41118CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1588 0x41118D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1589 0x41118D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1590 0x41118D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1591 0x41118DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1592 0x41118E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1593 0x41118E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1594 0x41118E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1595 0x41118EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1596 0x41118F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1597 0x41118F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1598 0x41118F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1599 0x41118FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1600 0x4111900
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1601 0x4111904
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1602 0x4111908
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1603 0x411190C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1604 0x4111910
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1605 0x4111914
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1606 0x4111918
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1607 0x411191C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1608 0x4111920
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1609 0x4111924
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1610 0x4111928
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1611 0x411192C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1612 0x4111930
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1613 0x4111934
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1614 0x4111938
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1615 0x411193C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1616 0x4111940
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1617 0x4111944
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1618 0x4111948
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1619 0x411194C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1620 0x4111950
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1621 0x4111954
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1622 0x4111958
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1623 0x411195C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1624 0x4111960
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1625 0x4111964
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1626 0x4111968
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1627 0x411196C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1628 0x4111970
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1629 0x4111974
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1630 0x4111978
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1631 0x411197C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1632 0x4111980
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1633 0x4111984
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1634 0x4111988
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1635 0x411198C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1636 0x4111990
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1637 0x4111994
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1638 0x4111998
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1639 0x411199C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1640 0x41119A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1641 0x41119A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1642 0x41119A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1643 0x41119AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1644 0x41119B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1645 0x41119B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1646 0x41119B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1647 0x41119BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1648 0x41119C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1649 0x41119C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1650 0x41119C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1651 0x41119CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1652 0x41119D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1653 0x41119D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1654 0x41119D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1655 0x41119DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1656 0x41119E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1657 0x41119E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1658 0x41119E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1659 0x41119EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1660 0x41119F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1661 0x41119F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1662 0x41119F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1663 0x41119FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1664 0x4111A00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1665 0x4111A04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1666 0x4111A08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1667 0x4111A0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1668 0x4111A10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1669 0x4111A14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1670 0x4111A18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1671 0x4111A1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1672 0x4111A20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1673 0x4111A24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1674 0x4111A28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1675 0x4111A2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1676 0x4111A30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1677 0x4111A34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1678 0x4111A38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1679 0x4111A3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1680 0x4111A40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1681 0x4111A44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1682 0x4111A48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1683 0x4111A4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1684 0x4111A50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1685 0x4111A54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1686 0x4111A58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1687 0x4111A5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1688 0x4111A60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1689 0x4111A64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1690 0x4111A68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1691 0x4111A6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1692 0x4111A70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1693 0x4111A74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1694 0x4111A78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1695 0x4111A7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1696 0x4111A80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1697 0x4111A84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1698 0x4111A88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1699 0x4111A8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1700 0x4111A90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1701 0x4111A94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1702 0x4111A98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1703 0x4111A9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1704 0x4111AA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1705 0x4111AA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1706 0x4111AA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1707 0x4111AAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1708 0x4111AB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1709 0x4111AB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1710 0x4111AB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1711 0x4111ABC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1712 0x4111AC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1713 0x4111AC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1714 0x4111AC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1715 0x4111ACC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1716 0x4111AD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1717 0x4111AD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1718 0x4111AD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1719 0x4111ADC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1720 0x4111AE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1721 0x4111AE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1722 0x4111AE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1723 0x4111AEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1724 0x4111AF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1725 0x4111AF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1726 0x4111AF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1727 0x4111AFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1728 0x4111B00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1729 0x4111B04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1730 0x4111B08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1731 0x4111B0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1732 0x4111B10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1733 0x4111B14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1734 0x4111B18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1735 0x4111B1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1736 0x4111B20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1737 0x4111B24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1738 0x4111B28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1739 0x4111B2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1740 0x4111B30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1741 0x4111B34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1742 0x4111B38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1743 0x4111B3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1744 0x4111B40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1745 0x4111B44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1746 0x4111B48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1747 0x4111B4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1748 0x4111B50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1749 0x4111B54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1750 0x4111B58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1751 0x4111B5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1752 0x4111B60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1753 0x4111B64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1754 0x4111B68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1755 0x4111B6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1756 0x4111B70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1757 0x4111B74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1758 0x4111B78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1759 0x4111B7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1760 0x4111B80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1761 0x4111B84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1762 0x4111B88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1763 0x4111B8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1764 0x4111B90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1765 0x4111B94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1766 0x4111B98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1767 0x4111B9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1768 0x4111BA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1769 0x4111BA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1770 0x4111BA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1771 0x4111BAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1772 0x4111BB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1773 0x4111BB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1774 0x4111BB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1775 0x4111BBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1776 0x4111BC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1777 0x4111BC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1778 0x4111BC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1779 0x4111BCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1780 0x4111BD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1781 0x4111BD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1782 0x4111BD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1783 0x4111BDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1784 0x4111BE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1785 0x4111BE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1786 0x4111BE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1787 0x4111BEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1788 0x4111BF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1789 0x4111BF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1790 0x4111BF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1791 0x4111BFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1792 0x4111C00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1793 0x4111C04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1794 0x4111C08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1795 0x4111C0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1796 0x4111C10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1797 0x4111C14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1798 0x4111C18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1799 0x4111C1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1800 0x4111C20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1801 0x4111C24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1802 0x4111C28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1803 0x4111C2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1804 0x4111C30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1805 0x4111C34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1806 0x4111C38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1807 0x4111C3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1808 0x4111C40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1809 0x4111C44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1810 0x4111C48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1811 0x4111C4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1812 0x4111C50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1813 0x4111C54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1814 0x4111C58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1815 0x4111C5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1816 0x4111C60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1817 0x4111C64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1818 0x4111C68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1819 0x4111C6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1820 0x4111C70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1821 0x4111C74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1822 0x4111C78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1823 0x4111C7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1824 0x4111C80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1825 0x4111C84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1826 0x4111C88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1827 0x4111C8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1828 0x4111C90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1829 0x4111C94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1830 0x4111C98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1831 0x4111C9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1832 0x4111CA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1833 0x4111CA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1834 0x4111CA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1835 0x4111CAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1836 0x4111CB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1837 0x4111CB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1838 0x4111CB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1839 0x4111CBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1840 0x4111CC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1841 0x4111CC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1842 0x4111CC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1843 0x4111CCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1844 0x4111CD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1845 0x4111CD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1846 0x4111CD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1847 0x4111CDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1848 0x4111CE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1849 0x4111CE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1850 0x4111CE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1851 0x4111CEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1852 0x4111CF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1853 0x4111CF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1854 0x4111CF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1855 0x4111CFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1856 0x4111D00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1857 0x4111D04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1858 0x4111D08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1859 0x4111D0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1860 0x4111D10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1861 0x4111D14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1862 0x4111D18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1863 0x4111D1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1864 0x4111D20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1865 0x4111D24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1866 0x4111D28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1867 0x4111D2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1868 0x4111D30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1869 0x4111D34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1870 0x4111D38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1871 0x4111D3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1872 0x4111D40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1873 0x4111D44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1874 0x4111D48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1875 0x4111D4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1876 0x4111D50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1877 0x4111D54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1878 0x4111D58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1879 0x4111D5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1880 0x4111D60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1881 0x4111D64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1882 0x4111D68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1883 0x4111D6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1884 0x4111D70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1885 0x4111D74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1886 0x4111D78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1887 0x4111D7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1888 0x4111D80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1889 0x4111D84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1890 0x4111D88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1891 0x4111D8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1892 0x4111D90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1893 0x4111D94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1894 0x4111D98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1895 0x4111D9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1896 0x4111DA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1897 0x4111DA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1898 0x4111DA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1899 0x4111DAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1900 0x4111DB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1901 0x4111DB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1902 0x4111DB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1903 0x4111DBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1904 0x4111DC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1905 0x4111DC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1906 0x4111DC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1907 0x4111DCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1908 0x4111DD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1909 0x4111DD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1910 0x4111DD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1911 0x4111DDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1912 0x4111DE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1913 0x4111DE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1914 0x4111DE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1915 0x4111DEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1916 0x4111DF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1917 0x4111DF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1918 0x4111DF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1919 0x4111DFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1920 0x4111E00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1921 0x4111E04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1922 0x4111E08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1923 0x4111E0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1924 0x4111E10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1925 0x4111E14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1926 0x4111E18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1927 0x4111E1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1928 0x4111E20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1929 0x4111E24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1930 0x4111E28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1931 0x4111E2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1932 0x4111E30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1933 0x4111E34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1934 0x4111E38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1935 0x4111E3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1936 0x4111E40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1937 0x4111E44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1938 0x4111E48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1939 0x4111E4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1940 0x4111E50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1941 0x4111E54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1942 0x4111E58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1943 0x4111E5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1944 0x4111E60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1945 0x4111E64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1946 0x4111E68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1947 0x4111E6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1948 0x4111E70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1949 0x4111E74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1950 0x4111E78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1951 0x4111E7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1952 0x4111E80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1953 0x4111E84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1954 0x4111E88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1955 0x4111E8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1956 0x4111E90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1957 0x4111E94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1958 0x4111E98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1959 0x4111E9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1960 0x4111EA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1961 0x4111EA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1962 0x4111EA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1963 0x4111EAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1964 0x4111EB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1965 0x4111EB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1966 0x4111EB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1967 0x4111EBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1968 0x4111EC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1969 0x4111EC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1970 0x4111EC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1971 0x4111ECC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1972 0x4111ED0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1973 0x4111ED4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1974 0x4111ED8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1975 0x4111EDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1976 0x4111EE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1977 0x4111EE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1978 0x4111EE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1979 0x4111EEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1980 0x4111EF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1981 0x4111EF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1982 0x4111EF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1983 0x4111EFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1984 0x4111F00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1985 0x4111F04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1986 0x4111F08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1987 0x4111F0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1988 0x4111F10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1989 0x4111F14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1990 0x4111F18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1991 0x4111F1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1992 0x4111F20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1993 0x4111F24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1994 0x4111F28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1995 0x4111F2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1996 0x4111F30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1997 0x4111F34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1998 0x4111F38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_1999 0x4111F3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2000 0x4111F40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2001 0x4111F44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2002 0x4111F48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2003 0x4111F4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2004 0x4111F50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2005 0x4111F54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2006 0x4111F58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2007 0x4111F5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2008 0x4111F60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2009 0x4111F64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2010 0x4111F68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2011 0x4111F6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2012 0x4111F70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2013 0x4111F74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2014 0x4111F78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2015 0x4111F7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2016 0x4111F80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2017 0x4111F84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2018 0x4111F88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2019 0x4111F8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2020 0x4111F90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2021 0x4111F94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2022 0x4111F98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2023 0x4111F9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2024 0x4111FA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2025 0x4111FA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2026 0x4111FA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2027 0x4111FAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2028 0x4111FB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2029 0x4111FB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2030 0x4111FB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2031 0x4111FBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2032 0x4111FC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2033 0x4111FC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2034 0x4111FC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2035 0x4111FCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2036 0x4111FD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2037 0x4111FD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2038 0x4111FD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2039 0x4111FDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2040 0x4111FE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2041 0x4111FE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2042 0x4111FE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2043 0x4111FEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2044 0x4111FF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2045 0x4111FF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2046 0x4111FF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_2047 0x4111FFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_0 0x4112000
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1 0x4112004
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2 0x4112008
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_3 0x411200C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_4 0x4112010
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_5 0x4112014
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_6 0x4112018
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_7 0x411201C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_8 0x4112020
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_9 0x4112024
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_10 0x4112028
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_11 0x411202C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_12 0x4112030
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_13 0x4112034
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_14 0x4112038
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_15 0x411203C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_16 0x4112040
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_17 0x4112044
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_18 0x4112048
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_19 0x411204C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_20 0x4112050
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_21 0x4112054
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_22 0x4112058
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_23 0x411205C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_24 0x4112060
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_25 0x4112064
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_26 0x4112068
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_27 0x411206C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_28 0x4112070
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_29 0x4112074
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_30 0x4112078
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_31 0x411207C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_32 0x4112080
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_33 0x4112084
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_34 0x4112088
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_35 0x411208C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_36 0x4112090
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_37 0x4112094
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_38 0x4112098
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_39 0x411209C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_40 0x41120A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_41 0x41120A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_42 0x41120A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_43 0x41120AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_44 0x41120B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_45 0x41120B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_46 0x41120B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_47 0x41120BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_48 0x41120C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_49 0x41120C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_50 0x41120C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_51 0x41120CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_52 0x41120D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_53 0x41120D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_54 0x41120D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_55 0x41120DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_56 0x41120E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_57 0x41120E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_58 0x41120E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_59 0x41120EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_60 0x41120F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_61 0x41120F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_62 0x41120F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_63 0x41120FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_64 0x4112100
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_65 0x4112104
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_66 0x4112108
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_67 0x411210C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_68 0x4112110
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_69 0x4112114
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_70 0x4112118
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_71 0x411211C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_72 0x4112120
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_73 0x4112124
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_74 0x4112128
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_75 0x411212C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_76 0x4112130
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_77 0x4112134
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_78 0x4112138
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_79 0x411213C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_80 0x4112140
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_81 0x4112144
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_82 0x4112148
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_83 0x411214C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_84 0x4112150
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_85 0x4112154
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_86 0x4112158
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_87 0x411215C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_88 0x4112160
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_89 0x4112164
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_90 0x4112168
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_91 0x411216C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_92 0x4112170
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_93 0x4112174
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_94 0x4112178
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_95 0x411217C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_96 0x4112180
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_97 0x4112184
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_98 0x4112188
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_99 0x411218C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_100 0x4112190
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_101 0x4112194
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_102 0x4112198
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_103 0x411219C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_104 0x41121A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_105 0x41121A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_106 0x41121A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_107 0x41121AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_108 0x41121B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_109 0x41121B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_110 0x41121B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_111 0x41121BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_112 0x41121C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_113 0x41121C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_114 0x41121C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_115 0x41121CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_116 0x41121D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_117 0x41121D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_118 0x41121D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_119 0x41121DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_120 0x41121E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_121 0x41121E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_122 0x41121E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_123 0x41121EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_124 0x41121F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_125 0x41121F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_126 0x41121F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_127 0x41121FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_128 0x4112200
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_129 0x4112204
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_130 0x4112208
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_131 0x411220C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_132 0x4112210
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_133 0x4112214
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_134 0x4112218
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_135 0x411221C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_136 0x4112220
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_137 0x4112224
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_138 0x4112228
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_139 0x411222C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_140 0x4112230
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_141 0x4112234
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_142 0x4112238
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_143 0x411223C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_144 0x4112240
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_145 0x4112244
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_146 0x4112248
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_147 0x411224C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_148 0x4112250
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_149 0x4112254
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_150 0x4112258
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_151 0x411225C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_152 0x4112260
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_153 0x4112264
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_154 0x4112268
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_155 0x411226C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_156 0x4112270
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_157 0x4112274
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_158 0x4112278
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_159 0x411227C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_160 0x4112280
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_161 0x4112284
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_162 0x4112288
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_163 0x411228C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_164 0x4112290
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_165 0x4112294
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_166 0x4112298
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_167 0x411229C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_168 0x41122A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_169 0x41122A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_170 0x41122A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_171 0x41122AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_172 0x41122B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_173 0x41122B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_174 0x41122B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_175 0x41122BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_176 0x41122C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_177 0x41122C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_178 0x41122C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_179 0x41122CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_180 0x41122D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_181 0x41122D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_182 0x41122D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_183 0x41122DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_184 0x41122E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_185 0x41122E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_186 0x41122E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_187 0x41122EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_188 0x41122F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_189 0x41122F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_190 0x41122F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_191 0x41122FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_192 0x4112300
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_193 0x4112304
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_194 0x4112308
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_195 0x411230C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_196 0x4112310
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_197 0x4112314
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_198 0x4112318
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_199 0x411231C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_200 0x4112320
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_201 0x4112324
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_202 0x4112328
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_203 0x411232C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_204 0x4112330
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_205 0x4112334
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_206 0x4112338
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_207 0x411233C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_208 0x4112340
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_209 0x4112344
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_210 0x4112348
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_211 0x411234C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_212 0x4112350
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_213 0x4112354
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_214 0x4112358
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_215 0x411235C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_216 0x4112360
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_217 0x4112364
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_218 0x4112368
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_219 0x411236C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_220 0x4112370
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_221 0x4112374
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_222 0x4112378
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_223 0x411237C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_224 0x4112380
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_225 0x4112384
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_226 0x4112388
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_227 0x411238C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_228 0x4112390
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_229 0x4112394
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_230 0x4112398
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_231 0x411239C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_232 0x41123A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_233 0x41123A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_234 0x41123A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_235 0x41123AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_236 0x41123B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_237 0x41123B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_238 0x41123B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_239 0x41123BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_240 0x41123C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_241 0x41123C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_242 0x41123C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_243 0x41123CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_244 0x41123D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_245 0x41123D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_246 0x41123D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_247 0x41123DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_248 0x41123E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_249 0x41123E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_250 0x41123E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_251 0x41123EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_252 0x41123F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_253 0x41123F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_254 0x41123F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_255 0x41123FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_256 0x4112400
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_257 0x4112404
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_258 0x4112408
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_259 0x411240C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_260 0x4112410
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_261 0x4112414
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_262 0x4112418
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_263 0x411241C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_264 0x4112420
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_265 0x4112424
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_266 0x4112428
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_267 0x411242C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_268 0x4112430
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_269 0x4112434
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_270 0x4112438
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_271 0x411243C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_272 0x4112440
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_273 0x4112444
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_274 0x4112448
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_275 0x411244C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_276 0x4112450
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_277 0x4112454
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_278 0x4112458
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_279 0x411245C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_280 0x4112460
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_281 0x4112464
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_282 0x4112468
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_283 0x411246C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_284 0x4112470
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_285 0x4112474
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_286 0x4112478
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_287 0x411247C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_288 0x4112480
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_289 0x4112484
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_290 0x4112488
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_291 0x411248C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_292 0x4112490
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_293 0x4112494
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_294 0x4112498
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_295 0x411249C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_296 0x41124A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_297 0x41124A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_298 0x41124A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_299 0x41124AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_300 0x41124B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_301 0x41124B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_302 0x41124B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_303 0x41124BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_304 0x41124C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_305 0x41124C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_306 0x41124C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_307 0x41124CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_308 0x41124D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_309 0x41124D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_310 0x41124D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_311 0x41124DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_312 0x41124E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_313 0x41124E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_314 0x41124E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_315 0x41124EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_316 0x41124F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_317 0x41124F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_318 0x41124F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_319 0x41124FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_320 0x4112500
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_321 0x4112504
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_322 0x4112508
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_323 0x411250C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_324 0x4112510
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_325 0x4112514
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_326 0x4112518
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_327 0x411251C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_328 0x4112520
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_329 0x4112524
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_330 0x4112528
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_331 0x411252C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_332 0x4112530
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_333 0x4112534
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_334 0x4112538
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_335 0x411253C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_336 0x4112540
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_337 0x4112544
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_338 0x4112548
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_339 0x411254C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_340 0x4112550
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_341 0x4112554
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_342 0x4112558
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_343 0x411255C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_344 0x4112560
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_345 0x4112564
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_346 0x4112568
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_347 0x411256C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_348 0x4112570
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_349 0x4112574
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_350 0x4112578
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_351 0x411257C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_352 0x4112580
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_353 0x4112584
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_354 0x4112588
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_355 0x411258C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_356 0x4112590
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_357 0x4112594
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_358 0x4112598
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_359 0x411259C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_360 0x41125A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_361 0x41125A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_362 0x41125A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_363 0x41125AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_364 0x41125B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_365 0x41125B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_366 0x41125B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_367 0x41125BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_368 0x41125C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_369 0x41125C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_370 0x41125C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_371 0x41125CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_372 0x41125D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_373 0x41125D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_374 0x41125D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_375 0x41125DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_376 0x41125E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_377 0x41125E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_378 0x41125E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_379 0x41125EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_380 0x41125F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_381 0x41125F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_382 0x41125F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_383 0x41125FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_384 0x4112600
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_385 0x4112604
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_386 0x4112608
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_387 0x411260C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_388 0x4112610
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_389 0x4112614
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_390 0x4112618
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_391 0x411261C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_392 0x4112620
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_393 0x4112624
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_394 0x4112628
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_395 0x411262C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_396 0x4112630
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_397 0x4112634
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_398 0x4112638
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_399 0x411263C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_400 0x4112640
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_401 0x4112644
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_402 0x4112648
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_403 0x411264C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_404 0x4112650
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_405 0x4112654
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_406 0x4112658
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_407 0x411265C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_408 0x4112660
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_409 0x4112664
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_410 0x4112668
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_411 0x411266C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_412 0x4112670
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_413 0x4112674
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_414 0x4112678
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_415 0x411267C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_416 0x4112680
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_417 0x4112684
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_418 0x4112688
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_419 0x411268C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_420 0x4112690
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_421 0x4112694
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_422 0x4112698
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_423 0x411269C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_424 0x41126A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_425 0x41126A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_426 0x41126A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_427 0x41126AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_428 0x41126B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_429 0x41126B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_430 0x41126B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_431 0x41126BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_432 0x41126C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_433 0x41126C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_434 0x41126C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_435 0x41126CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_436 0x41126D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_437 0x41126D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_438 0x41126D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_439 0x41126DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_440 0x41126E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_441 0x41126E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_442 0x41126E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_443 0x41126EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_444 0x41126F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_445 0x41126F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_446 0x41126F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_447 0x41126FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_448 0x4112700
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_449 0x4112704
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_450 0x4112708
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_451 0x411270C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_452 0x4112710
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_453 0x4112714
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_454 0x4112718
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_455 0x411271C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_456 0x4112720
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_457 0x4112724
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_458 0x4112728
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_459 0x411272C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_460 0x4112730
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_461 0x4112734
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_462 0x4112738
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_463 0x411273C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_464 0x4112740
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_465 0x4112744
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_466 0x4112748
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_467 0x411274C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_468 0x4112750
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_469 0x4112754
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_470 0x4112758
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_471 0x411275C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_472 0x4112760
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_473 0x4112764
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_474 0x4112768
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_475 0x411276C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_476 0x4112770
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_477 0x4112774
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_478 0x4112778
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_479 0x411277C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_480 0x4112780
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_481 0x4112784
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_482 0x4112788
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_483 0x411278C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_484 0x4112790
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_485 0x4112794
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_486 0x4112798
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_487 0x411279C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_488 0x41127A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_489 0x41127A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_490 0x41127A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_491 0x41127AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_492 0x41127B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_493 0x41127B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_494 0x41127B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_495 0x41127BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_496 0x41127C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_497 0x41127C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_498 0x41127C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_499 0x41127CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_500 0x41127D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_501 0x41127D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_502 0x41127D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_503 0x41127DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_504 0x41127E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_505 0x41127E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_506 0x41127E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_507 0x41127EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_508 0x41127F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_509 0x41127F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_510 0x41127F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_511 0x41127FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_512 0x4112800
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_513 0x4112804
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_514 0x4112808
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_515 0x411280C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_516 0x4112810
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_517 0x4112814
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_518 0x4112818
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_519 0x411281C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_520 0x4112820
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_521 0x4112824
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_522 0x4112828
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_523 0x411282C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_524 0x4112830
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_525 0x4112834
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_526 0x4112838
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_527 0x411283C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_528 0x4112840
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_529 0x4112844
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_530 0x4112848
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_531 0x411284C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_532 0x4112850
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_533 0x4112854
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_534 0x4112858
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_535 0x411285C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_536 0x4112860
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_537 0x4112864
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_538 0x4112868
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_539 0x411286C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_540 0x4112870
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_541 0x4112874
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_542 0x4112878
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_543 0x411287C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_544 0x4112880
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_545 0x4112884
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_546 0x4112888
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_547 0x411288C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_548 0x4112890
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_549 0x4112894
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_550 0x4112898
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_551 0x411289C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_552 0x41128A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_553 0x41128A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_554 0x41128A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_555 0x41128AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_556 0x41128B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_557 0x41128B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_558 0x41128B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_559 0x41128BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_560 0x41128C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_561 0x41128C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_562 0x41128C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_563 0x41128CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_564 0x41128D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_565 0x41128D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_566 0x41128D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_567 0x41128DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_568 0x41128E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_569 0x41128E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_570 0x41128E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_571 0x41128EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_572 0x41128F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_573 0x41128F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_574 0x41128F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_575 0x41128FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_576 0x4112900
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_577 0x4112904
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_578 0x4112908
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_579 0x411290C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_580 0x4112910
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_581 0x4112914
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_582 0x4112918
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_583 0x411291C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_584 0x4112920
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_585 0x4112924
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_586 0x4112928
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_587 0x411292C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_588 0x4112930
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_589 0x4112934
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_590 0x4112938
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_591 0x411293C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_592 0x4112940
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_593 0x4112944
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_594 0x4112948
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_595 0x411294C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_596 0x4112950
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_597 0x4112954
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_598 0x4112958
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_599 0x411295C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_600 0x4112960
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_601 0x4112964
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_602 0x4112968
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_603 0x411296C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_604 0x4112970
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_605 0x4112974
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_606 0x4112978
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_607 0x411297C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_608 0x4112980
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_609 0x4112984
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_610 0x4112988
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_611 0x411298C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_612 0x4112990
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_613 0x4112994
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_614 0x4112998
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_615 0x411299C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_616 0x41129A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_617 0x41129A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_618 0x41129A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_619 0x41129AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_620 0x41129B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_621 0x41129B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_622 0x41129B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_623 0x41129BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_624 0x41129C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_625 0x41129C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_626 0x41129C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_627 0x41129CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_628 0x41129D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_629 0x41129D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_630 0x41129D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_631 0x41129DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_632 0x41129E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_633 0x41129E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_634 0x41129E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_635 0x41129EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_636 0x41129F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_637 0x41129F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_638 0x41129F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_639 0x41129FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_640 0x4112A00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_641 0x4112A04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_642 0x4112A08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_643 0x4112A0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_644 0x4112A10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_645 0x4112A14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_646 0x4112A18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_647 0x4112A1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_648 0x4112A20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_649 0x4112A24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_650 0x4112A28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_651 0x4112A2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_652 0x4112A30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_653 0x4112A34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_654 0x4112A38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_655 0x4112A3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_656 0x4112A40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_657 0x4112A44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_658 0x4112A48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_659 0x4112A4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_660 0x4112A50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_661 0x4112A54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_662 0x4112A58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_663 0x4112A5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_664 0x4112A60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_665 0x4112A64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_666 0x4112A68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_667 0x4112A6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_668 0x4112A70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_669 0x4112A74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_670 0x4112A78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_671 0x4112A7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_672 0x4112A80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_673 0x4112A84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_674 0x4112A88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_675 0x4112A8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_676 0x4112A90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_677 0x4112A94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_678 0x4112A98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_679 0x4112A9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_680 0x4112AA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_681 0x4112AA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_682 0x4112AA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_683 0x4112AAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_684 0x4112AB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_685 0x4112AB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_686 0x4112AB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_687 0x4112ABC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_688 0x4112AC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_689 0x4112AC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_690 0x4112AC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_691 0x4112ACC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_692 0x4112AD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_693 0x4112AD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_694 0x4112AD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_695 0x4112ADC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_696 0x4112AE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_697 0x4112AE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_698 0x4112AE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_699 0x4112AEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_700 0x4112AF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_701 0x4112AF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_702 0x4112AF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_703 0x4112AFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_704 0x4112B00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_705 0x4112B04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_706 0x4112B08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_707 0x4112B0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_708 0x4112B10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_709 0x4112B14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_710 0x4112B18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_711 0x4112B1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_712 0x4112B20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_713 0x4112B24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_714 0x4112B28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_715 0x4112B2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_716 0x4112B30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_717 0x4112B34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_718 0x4112B38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_719 0x4112B3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_720 0x4112B40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_721 0x4112B44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_722 0x4112B48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_723 0x4112B4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_724 0x4112B50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_725 0x4112B54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_726 0x4112B58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_727 0x4112B5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_728 0x4112B60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_729 0x4112B64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_730 0x4112B68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_731 0x4112B6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_732 0x4112B70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_733 0x4112B74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_734 0x4112B78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_735 0x4112B7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_736 0x4112B80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_737 0x4112B84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_738 0x4112B88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_739 0x4112B8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_740 0x4112B90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_741 0x4112B94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_742 0x4112B98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_743 0x4112B9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_744 0x4112BA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_745 0x4112BA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_746 0x4112BA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_747 0x4112BAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_748 0x4112BB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_749 0x4112BB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_750 0x4112BB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_751 0x4112BBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_752 0x4112BC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_753 0x4112BC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_754 0x4112BC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_755 0x4112BCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_756 0x4112BD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_757 0x4112BD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_758 0x4112BD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_759 0x4112BDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_760 0x4112BE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_761 0x4112BE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_762 0x4112BE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_763 0x4112BEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_764 0x4112BF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_765 0x4112BF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_766 0x4112BF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_767 0x4112BFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_768 0x4112C00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_769 0x4112C04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_770 0x4112C08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_771 0x4112C0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_772 0x4112C10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_773 0x4112C14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_774 0x4112C18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_775 0x4112C1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_776 0x4112C20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_777 0x4112C24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_778 0x4112C28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_779 0x4112C2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_780 0x4112C30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_781 0x4112C34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_782 0x4112C38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_783 0x4112C3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_784 0x4112C40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_785 0x4112C44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_786 0x4112C48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_787 0x4112C4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_788 0x4112C50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_789 0x4112C54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_790 0x4112C58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_791 0x4112C5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_792 0x4112C60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_793 0x4112C64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_794 0x4112C68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_795 0x4112C6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_796 0x4112C70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_797 0x4112C74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_798 0x4112C78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_799 0x4112C7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_800 0x4112C80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_801 0x4112C84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_802 0x4112C88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_803 0x4112C8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_804 0x4112C90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_805 0x4112C94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_806 0x4112C98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_807 0x4112C9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_808 0x4112CA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_809 0x4112CA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_810 0x4112CA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_811 0x4112CAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_812 0x4112CB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_813 0x4112CB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_814 0x4112CB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_815 0x4112CBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_816 0x4112CC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_817 0x4112CC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_818 0x4112CC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_819 0x4112CCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_820 0x4112CD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_821 0x4112CD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_822 0x4112CD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_823 0x4112CDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_824 0x4112CE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_825 0x4112CE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_826 0x4112CE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_827 0x4112CEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_828 0x4112CF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_829 0x4112CF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_830 0x4112CF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_831 0x4112CFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_832 0x4112D00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_833 0x4112D04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_834 0x4112D08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_835 0x4112D0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_836 0x4112D10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_837 0x4112D14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_838 0x4112D18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_839 0x4112D1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_840 0x4112D20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_841 0x4112D24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_842 0x4112D28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_843 0x4112D2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_844 0x4112D30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_845 0x4112D34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_846 0x4112D38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_847 0x4112D3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_848 0x4112D40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_849 0x4112D44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_850 0x4112D48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_851 0x4112D4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_852 0x4112D50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_853 0x4112D54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_854 0x4112D58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_855 0x4112D5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_856 0x4112D60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_857 0x4112D64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_858 0x4112D68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_859 0x4112D6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_860 0x4112D70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_861 0x4112D74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_862 0x4112D78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_863 0x4112D7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_864 0x4112D80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_865 0x4112D84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_866 0x4112D88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_867 0x4112D8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_868 0x4112D90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_869 0x4112D94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_870 0x4112D98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_871 0x4112D9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_872 0x4112DA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_873 0x4112DA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_874 0x4112DA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_875 0x4112DAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_876 0x4112DB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_877 0x4112DB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_878 0x4112DB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_879 0x4112DBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_880 0x4112DC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_881 0x4112DC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_882 0x4112DC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_883 0x4112DCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_884 0x4112DD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_885 0x4112DD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_886 0x4112DD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_887 0x4112DDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_888 0x4112DE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_889 0x4112DE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_890 0x4112DE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_891 0x4112DEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_892 0x4112DF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_893 0x4112DF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_894 0x4112DF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_895 0x4112DFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_896 0x4112E00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_897 0x4112E04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_898 0x4112E08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_899 0x4112E0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_900 0x4112E10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_901 0x4112E14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_902 0x4112E18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_903 0x4112E1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_904 0x4112E20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_905 0x4112E24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_906 0x4112E28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_907 0x4112E2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_908 0x4112E30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_909 0x4112E34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_910 0x4112E38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_911 0x4112E3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_912 0x4112E40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_913 0x4112E44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_914 0x4112E48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_915 0x4112E4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_916 0x4112E50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_917 0x4112E54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_918 0x4112E58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_919 0x4112E5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_920 0x4112E60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_921 0x4112E64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_922 0x4112E68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_923 0x4112E6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_924 0x4112E70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_925 0x4112E74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_926 0x4112E78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_927 0x4112E7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_928 0x4112E80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_929 0x4112E84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_930 0x4112E88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_931 0x4112E8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_932 0x4112E90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_933 0x4112E94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_934 0x4112E98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_935 0x4112E9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_936 0x4112EA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_937 0x4112EA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_938 0x4112EA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_939 0x4112EAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_940 0x4112EB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_941 0x4112EB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_942 0x4112EB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_943 0x4112EBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_944 0x4112EC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_945 0x4112EC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_946 0x4112EC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_947 0x4112ECC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_948 0x4112ED0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_949 0x4112ED4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_950 0x4112ED8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_951 0x4112EDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_952 0x4112EE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_953 0x4112EE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_954 0x4112EE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_955 0x4112EEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_956 0x4112EF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_957 0x4112EF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_958 0x4112EF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_959 0x4112EFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_960 0x4112F00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_961 0x4112F04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_962 0x4112F08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_963 0x4112F0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_964 0x4112F10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_965 0x4112F14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_966 0x4112F18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_967 0x4112F1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_968 0x4112F20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_969 0x4112F24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_970 0x4112F28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_971 0x4112F2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_972 0x4112F30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_973 0x4112F34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_974 0x4112F38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_975 0x4112F3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_976 0x4112F40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_977 0x4112F44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_978 0x4112F48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_979 0x4112F4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_980 0x4112F50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_981 0x4112F54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_982 0x4112F58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_983 0x4112F5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_984 0x4112F60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_985 0x4112F64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_986 0x4112F68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_987 0x4112F6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_988 0x4112F70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_989 0x4112F74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_990 0x4112F78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_991 0x4112F7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_992 0x4112F80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_993 0x4112F84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_994 0x4112F88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_995 0x4112F8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_996 0x4112F90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_997 0x4112F94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_998 0x4112F98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_999 0x4112F9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1000 0x4112FA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1001 0x4112FA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1002 0x4112FA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1003 0x4112FAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1004 0x4112FB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1005 0x4112FB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1006 0x4112FB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1007 0x4112FBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1008 0x4112FC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1009 0x4112FC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1010 0x4112FC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1011 0x4112FCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1012 0x4112FD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1013 0x4112FD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1014 0x4112FD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1015 0x4112FDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1016 0x4112FE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1017 0x4112FE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1018 0x4112FE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1019 0x4112FEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1020 0x4112FF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1021 0x4112FF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1022 0x4112FF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1023 0x4112FFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1024 0x4113000
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1025 0x4113004
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1026 0x4113008
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1027 0x411300C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1028 0x4113010
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1029 0x4113014
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1030 0x4113018
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1031 0x411301C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1032 0x4113020
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1033 0x4113024
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1034 0x4113028
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1035 0x411302C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1036 0x4113030
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1037 0x4113034
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1038 0x4113038
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1039 0x411303C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1040 0x4113040
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1041 0x4113044
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1042 0x4113048
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1043 0x411304C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1044 0x4113050
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1045 0x4113054
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1046 0x4113058
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1047 0x411305C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1048 0x4113060
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1049 0x4113064
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1050 0x4113068
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1051 0x411306C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1052 0x4113070
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1053 0x4113074
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1054 0x4113078
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1055 0x411307C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1056 0x4113080
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1057 0x4113084
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1058 0x4113088
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1059 0x411308C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1060 0x4113090
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1061 0x4113094
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1062 0x4113098
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1063 0x411309C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1064 0x41130A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1065 0x41130A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1066 0x41130A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1067 0x41130AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1068 0x41130B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1069 0x41130B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1070 0x41130B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1071 0x41130BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1072 0x41130C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1073 0x41130C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1074 0x41130C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1075 0x41130CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1076 0x41130D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1077 0x41130D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1078 0x41130D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1079 0x41130DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1080 0x41130E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1081 0x41130E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1082 0x41130E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1083 0x41130EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1084 0x41130F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1085 0x41130F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1086 0x41130F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1087 0x41130FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1088 0x4113100
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1089 0x4113104
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1090 0x4113108
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1091 0x411310C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1092 0x4113110
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1093 0x4113114
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1094 0x4113118
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1095 0x411311C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1096 0x4113120
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1097 0x4113124
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1098 0x4113128
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1099 0x411312C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1100 0x4113130
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1101 0x4113134
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1102 0x4113138
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1103 0x411313C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1104 0x4113140
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1105 0x4113144
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1106 0x4113148
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1107 0x411314C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1108 0x4113150
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1109 0x4113154
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1110 0x4113158
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1111 0x411315C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1112 0x4113160
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1113 0x4113164
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1114 0x4113168
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1115 0x411316C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1116 0x4113170
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1117 0x4113174
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1118 0x4113178
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1119 0x411317C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1120 0x4113180
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1121 0x4113184
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1122 0x4113188
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1123 0x411318C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1124 0x4113190
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1125 0x4113194
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1126 0x4113198
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1127 0x411319C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1128 0x41131A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1129 0x41131A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1130 0x41131A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1131 0x41131AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1132 0x41131B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1133 0x41131B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1134 0x41131B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1135 0x41131BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1136 0x41131C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1137 0x41131C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1138 0x41131C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1139 0x41131CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1140 0x41131D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1141 0x41131D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1142 0x41131D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1143 0x41131DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1144 0x41131E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1145 0x41131E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1146 0x41131E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1147 0x41131EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1148 0x41131F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1149 0x41131F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1150 0x41131F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1151 0x41131FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1152 0x4113200
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1153 0x4113204
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1154 0x4113208
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1155 0x411320C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1156 0x4113210
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1157 0x4113214
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1158 0x4113218
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1159 0x411321C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1160 0x4113220
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1161 0x4113224
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1162 0x4113228
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1163 0x411322C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1164 0x4113230
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1165 0x4113234
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1166 0x4113238
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1167 0x411323C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1168 0x4113240
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1169 0x4113244
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1170 0x4113248
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1171 0x411324C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1172 0x4113250
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1173 0x4113254
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1174 0x4113258
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1175 0x411325C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1176 0x4113260
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1177 0x4113264
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1178 0x4113268
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1179 0x411326C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1180 0x4113270
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1181 0x4113274
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1182 0x4113278
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1183 0x411327C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1184 0x4113280
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1185 0x4113284
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1186 0x4113288
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1187 0x411328C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1188 0x4113290
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1189 0x4113294
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1190 0x4113298
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1191 0x411329C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1192 0x41132A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1193 0x41132A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1194 0x41132A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1195 0x41132AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1196 0x41132B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1197 0x41132B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1198 0x41132B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1199 0x41132BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1200 0x41132C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1201 0x41132C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1202 0x41132C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1203 0x41132CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1204 0x41132D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1205 0x41132D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1206 0x41132D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1207 0x41132DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1208 0x41132E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1209 0x41132E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1210 0x41132E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1211 0x41132EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1212 0x41132F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1213 0x41132F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1214 0x41132F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1215 0x41132FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1216 0x4113300
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1217 0x4113304
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1218 0x4113308
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1219 0x411330C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1220 0x4113310
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1221 0x4113314
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1222 0x4113318
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1223 0x411331C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1224 0x4113320
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1225 0x4113324
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1226 0x4113328
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1227 0x411332C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1228 0x4113330
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1229 0x4113334
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1230 0x4113338
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1231 0x411333C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1232 0x4113340
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1233 0x4113344
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1234 0x4113348
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1235 0x411334C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1236 0x4113350
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1237 0x4113354
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1238 0x4113358
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1239 0x411335C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1240 0x4113360
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1241 0x4113364
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1242 0x4113368
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1243 0x411336C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1244 0x4113370
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1245 0x4113374
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1246 0x4113378
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1247 0x411337C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1248 0x4113380
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1249 0x4113384
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1250 0x4113388
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1251 0x411338C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1252 0x4113390
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1253 0x4113394
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1254 0x4113398
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1255 0x411339C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1256 0x41133A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1257 0x41133A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1258 0x41133A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1259 0x41133AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1260 0x41133B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1261 0x41133B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1262 0x41133B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1263 0x41133BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1264 0x41133C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1265 0x41133C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1266 0x41133C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1267 0x41133CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1268 0x41133D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1269 0x41133D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1270 0x41133D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1271 0x41133DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1272 0x41133E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1273 0x41133E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1274 0x41133E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1275 0x41133EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1276 0x41133F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1277 0x41133F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1278 0x41133F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1279 0x41133FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1280 0x4113400
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1281 0x4113404
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1282 0x4113408
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1283 0x411340C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1284 0x4113410
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1285 0x4113414
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1286 0x4113418
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1287 0x411341C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1288 0x4113420
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1289 0x4113424
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1290 0x4113428
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1291 0x411342C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1292 0x4113430
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1293 0x4113434
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1294 0x4113438
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1295 0x411343C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1296 0x4113440
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1297 0x4113444
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1298 0x4113448
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1299 0x411344C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1300 0x4113450
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1301 0x4113454
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1302 0x4113458
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1303 0x411345C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1304 0x4113460
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1305 0x4113464
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1306 0x4113468
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1307 0x411346C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1308 0x4113470
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1309 0x4113474
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1310 0x4113478
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1311 0x411347C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1312 0x4113480
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1313 0x4113484
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1314 0x4113488
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1315 0x411348C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1316 0x4113490
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1317 0x4113494
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1318 0x4113498
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1319 0x411349C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1320 0x41134A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1321 0x41134A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1322 0x41134A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1323 0x41134AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1324 0x41134B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1325 0x41134B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1326 0x41134B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1327 0x41134BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1328 0x41134C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1329 0x41134C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1330 0x41134C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1331 0x41134CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1332 0x41134D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1333 0x41134D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1334 0x41134D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1335 0x41134DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1336 0x41134E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1337 0x41134E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1338 0x41134E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1339 0x41134EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1340 0x41134F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1341 0x41134F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1342 0x41134F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1343 0x41134FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1344 0x4113500
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1345 0x4113504
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1346 0x4113508
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1347 0x411350C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1348 0x4113510
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1349 0x4113514
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1350 0x4113518
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1351 0x411351C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1352 0x4113520
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1353 0x4113524
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1354 0x4113528
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1355 0x411352C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1356 0x4113530
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1357 0x4113534
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1358 0x4113538
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1359 0x411353C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1360 0x4113540
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1361 0x4113544
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1362 0x4113548
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1363 0x411354C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1364 0x4113550
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1365 0x4113554
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1366 0x4113558
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1367 0x411355C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1368 0x4113560
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1369 0x4113564
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1370 0x4113568
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1371 0x411356C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1372 0x4113570
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1373 0x4113574
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1374 0x4113578
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1375 0x411357C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1376 0x4113580
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1377 0x4113584
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1378 0x4113588
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1379 0x411358C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1380 0x4113590
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1381 0x4113594
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1382 0x4113598
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1383 0x411359C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1384 0x41135A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1385 0x41135A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1386 0x41135A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1387 0x41135AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1388 0x41135B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1389 0x41135B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1390 0x41135B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1391 0x41135BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1392 0x41135C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1393 0x41135C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1394 0x41135C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1395 0x41135CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1396 0x41135D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1397 0x41135D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1398 0x41135D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1399 0x41135DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1400 0x41135E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1401 0x41135E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1402 0x41135E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1403 0x41135EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1404 0x41135F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1405 0x41135F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1406 0x41135F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1407 0x41135FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1408 0x4113600
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1409 0x4113604
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1410 0x4113608
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1411 0x411360C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1412 0x4113610
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1413 0x4113614
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1414 0x4113618
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1415 0x411361C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1416 0x4113620
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1417 0x4113624
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1418 0x4113628
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1419 0x411362C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1420 0x4113630
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1421 0x4113634
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1422 0x4113638
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1423 0x411363C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1424 0x4113640
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1425 0x4113644
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1426 0x4113648
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1427 0x411364C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1428 0x4113650
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1429 0x4113654
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1430 0x4113658
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1431 0x411365C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1432 0x4113660
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1433 0x4113664
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1434 0x4113668
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1435 0x411366C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1436 0x4113670
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1437 0x4113674
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1438 0x4113678
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1439 0x411367C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1440 0x4113680
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1441 0x4113684
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1442 0x4113688
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1443 0x411368C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1444 0x4113690
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1445 0x4113694
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1446 0x4113698
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1447 0x411369C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1448 0x41136A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1449 0x41136A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1450 0x41136A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1451 0x41136AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1452 0x41136B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1453 0x41136B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1454 0x41136B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1455 0x41136BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1456 0x41136C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1457 0x41136C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1458 0x41136C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1459 0x41136CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1460 0x41136D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1461 0x41136D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1462 0x41136D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1463 0x41136DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1464 0x41136E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1465 0x41136E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1466 0x41136E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1467 0x41136EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1468 0x41136F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1469 0x41136F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1470 0x41136F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1471 0x41136FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1472 0x4113700
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1473 0x4113704
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1474 0x4113708
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1475 0x411370C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1476 0x4113710
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1477 0x4113714
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1478 0x4113718
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1479 0x411371C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1480 0x4113720
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1481 0x4113724
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1482 0x4113728
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1483 0x411372C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1484 0x4113730
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1485 0x4113734
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1486 0x4113738
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1487 0x411373C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1488 0x4113740
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1489 0x4113744
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1490 0x4113748
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1491 0x411374C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1492 0x4113750
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1493 0x4113754
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1494 0x4113758
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1495 0x411375C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1496 0x4113760
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1497 0x4113764
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1498 0x4113768
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1499 0x411376C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1500 0x4113770
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1501 0x4113774
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1502 0x4113778
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1503 0x411377C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1504 0x4113780
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1505 0x4113784
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1506 0x4113788
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1507 0x411378C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1508 0x4113790
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1509 0x4113794
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1510 0x4113798
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1511 0x411379C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1512 0x41137A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1513 0x41137A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1514 0x41137A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1515 0x41137AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1516 0x41137B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1517 0x41137B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1518 0x41137B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1519 0x41137BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1520 0x41137C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1521 0x41137C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1522 0x41137C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1523 0x41137CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1524 0x41137D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1525 0x41137D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1526 0x41137D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1527 0x41137DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1528 0x41137E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1529 0x41137E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1530 0x41137E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1531 0x41137EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1532 0x41137F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1533 0x41137F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1534 0x41137F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1535 0x41137FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1536 0x4113800
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1537 0x4113804
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1538 0x4113808
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1539 0x411380C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1540 0x4113810
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1541 0x4113814
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1542 0x4113818
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1543 0x411381C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1544 0x4113820
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1545 0x4113824
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1546 0x4113828
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1547 0x411382C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1548 0x4113830
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1549 0x4113834
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1550 0x4113838
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1551 0x411383C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1552 0x4113840
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1553 0x4113844
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1554 0x4113848
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1555 0x411384C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1556 0x4113850
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1557 0x4113854
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1558 0x4113858
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1559 0x411385C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1560 0x4113860
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1561 0x4113864
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1562 0x4113868
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1563 0x411386C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1564 0x4113870
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1565 0x4113874
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1566 0x4113878
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1567 0x411387C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1568 0x4113880
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1569 0x4113884
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1570 0x4113888
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1571 0x411388C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1572 0x4113890
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1573 0x4113894
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1574 0x4113898
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1575 0x411389C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1576 0x41138A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1577 0x41138A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1578 0x41138A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1579 0x41138AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1580 0x41138B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1581 0x41138B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1582 0x41138B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1583 0x41138BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1584 0x41138C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1585 0x41138C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1586 0x41138C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1587 0x41138CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1588 0x41138D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1589 0x41138D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1590 0x41138D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1591 0x41138DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1592 0x41138E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1593 0x41138E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1594 0x41138E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1595 0x41138EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1596 0x41138F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1597 0x41138F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1598 0x41138F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1599 0x41138FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1600 0x4113900
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1601 0x4113904
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1602 0x4113908
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1603 0x411390C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1604 0x4113910
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1605 0x4113914
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1606 0x4113918
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1607 0x411391C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1608 0x4113920
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1609 0x4113924
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1610 0x4113928
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1611 0x411392C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1612 0x4113930
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1613 0x4113934
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1614 0x4113938
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1615 0x411393C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1616 0x4113940
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1617 0x4113944
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1618 0x4113948
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1619 0x411394C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1620 0x4113950
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1621 0x4113954
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1622 0x4113958
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1623 0x411395C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1624 0x4113960
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1625 0x4113964
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1626 0x4113968
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1627 0x411396C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1628 0x4113970
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1629 0x4113974
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1630 0x4113978
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1631 0x411397C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1632 0x4113980
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1633 0x4113984
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1634 0x4113988
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1635 0x411398C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1636 0x4113990
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1637 0x4113994
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1638 0x4113998
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1639 0x411399C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1640 0x41139A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1641 0x41139A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1642 0x41139A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1643 0x41139AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1644 0x41139B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1645 0x41139B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1646 0x41139B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1647 0x41139BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1648 0x41139C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1649 0x41139C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1650 0x41139C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1651 0x41139CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1652 0x41139D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1653 0x41139D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1654 0x41139D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1655 0x41139DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1656 0x41139E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1657 0x41139E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1658 0x41139E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1659 0x41139EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1660 0x41139F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1661 0x41139F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1662 0x41139F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1663 0x41139FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1664 0x4113A00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1665 0x4113A04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1666 0x4113A08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1667 0x4113A0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1668 0x4113A10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1669 0x4113A14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1670 0x4113A18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1671 0x4113A1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1672 0x4113A20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1673 0x4113A24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1674 0x4113A28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1675 0x4113A2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1676 0x4113A30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1677 0x4113A34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1678 0x4113A38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1679 0x4113A3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1680 0x4113A40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1681 0x4113A44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1682 0x4113A48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1683 0x4113A4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1684 0x4113A50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1685 0x4113A54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1686 0x4113A58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1687 0x4113A5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1688 0x4113A60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1689 0x4113A64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1690 0x4113A68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1691 0x4113A6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1692 0x4113A70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1693 0x4113A74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1694 0x4113A78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1695 0x4113A7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1696 0x4113A80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1697 0x4113A84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1698 0x4113A88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1699 0x4113A8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1700 0x4113A90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1701 0x4113A94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1702 0x4113A98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1703 0x4113A9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1704 0x4113AA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1705 0x4113AA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1706 0x4113AA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1707 0x4113AAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1708 0x4113AB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1709 0x4113AB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1710 0x4113AB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1711 0x4113ABC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1712 0x4113AC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1713 0x4113AC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1714 0x4113AC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1715 0x4113ACC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1716 0x4113AD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1717 0x4113AD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1718 0x4113AD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1719 0x4113ADC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1720 0x4113AE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1721 0x4113AE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1722 0x4113AE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1723 0x4113AEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1724 0x4113AF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1725 0x4113AF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1726 0x4113AF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1727 0x4113AFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1728 0x4113B00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1729 0x4113B04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1730 0x4113B08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1731 0x4113B0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1732 0x4113B10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1733 0x4113B14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1734 0x4113B18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1735 0x4113B1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1736 0x4113B20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1737 0x4113B24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1738 0x4113B28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1739 0x4113B2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1740 0x4113B30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1741 0x4113B34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1742 0x4113B38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1743 0x4113B3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1744 0x4113B40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1745 0x4113B44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1746 0x4113B48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1747 0x4113B4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1748 0x4113B50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1749 0x4113B54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1750 0x4113B58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1751 0x4113B5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1752 0x4113B60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1753 0x4113B64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1754 0x4113B68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1755 0x4113B6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1756 0x4113B70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1757 0x4113B74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1758 0x4113B78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1759 0x4113B7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1760 0x4113B80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1761 0x4113B84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1762 0x4113B88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1763 0x4113B8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1764 0x4113B90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1765 0x4113B94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1766 0x4113B98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1767 0x4113B9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1768 0x4113BA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1769 0x4113BA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1770 0x4113BA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1771 0x4113BAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1772 0x4113BB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1773 0x4113BB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1774 0x4113BB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1775 0x4113BBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1776 0x4113BC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1777 0x4113BC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1778 0x4113BC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1779 0x4113BCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1780 0x4113BD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1781 0x4113BD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1782 0x4113BD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1783 0x4113BDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1784 0x4113BE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1785 0x4113BE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1786 0x4113BE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1787 0x4113BEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1788 0x4113BF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1789 0x4113BF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1790 0x4113BF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1791 0x4113BFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1792 0x4113C00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1793 0x4113C04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1794 0x4113C08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1795 0x4113C0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1796 0x4113C10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1797 0x4113C14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1798 0x4113C18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1799 0x4113C1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1800 0x4113C20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1801 0x4113C24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1802 0x4113C28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1803 0x4113C2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1804 0x4113C30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1805 0x4113C34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1806 0x4113C38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1807 0x4113C3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1808 0x4113C40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1809 0x4113C44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1810 0x4113C48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1811 0x4113C4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1812 0x4113C50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1813 0x4113C54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1814 0x4113C58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1815 0x4113C5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1816 0x4113C60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1817 0x4113C64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1818 0x4113C68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1819 0x4113C6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1820 0x4113C70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1821 0x4113C74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1822 0x4113C78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1823 0x4113C7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1824 0x4113C80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1825 0x4113C84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1826 0x4113C88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1827 0x4113C8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1828 0x4113C90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1829 0x4113C94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1830 0x4113C98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1831 0x4113C9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1832 0x4113CA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1833 0x4113CA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1834 0x4113CA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1835 0x4113CAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1836 0x4113CB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1837 0x4113CB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1838 0x4113CB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1839 0x4113CBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1840 0x4113CC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1841 0x4113CC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1842 0x4113CC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1843 0x4113CCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1844 0x4113CD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1845 0x4113CD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1846 0x4113CD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1847 0x4113CDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1848 0x4113CE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1849 0x4113CE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1850 0x4113CE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1851 0x4113CEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1852 0x4113CF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1853 0x4113CF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1854 0x4113CF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1855 0x4113CFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1856 0x4113D00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1857 0x4113D04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1858 0x4113D08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1859 0x4113D0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1860 0x4113D10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1861 0x4113D14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1862 0x4113D18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1863 0x4113D1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1864 0x4113D20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1865 0x4113D24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1866 0x4113D28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1867 0x4113D2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1868 0x4113D30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1869 0x4113D34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1870 0x4113D38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1871 0x4113D3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1872 0x4113D40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1873 0x4113D44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1874 0x4113D48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1875 0x4113D4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1876 0x4113D50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1877 0x4113D54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1878 0x4113D58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1879 0x4113D5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1880 0x4113D60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1881 0x4113D64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1882 0x4113D68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1883 0x4113D6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1884 0x4113D70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1885 0x4113D74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1886 0x4113D78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1887 0x4113D7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1888 0x4113D80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1889 0x4113D84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1890 0x4113D88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1891 0x4113D8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1892 0x4113D90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1893 0x4113D94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1894 0x4113D98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1895 0x4113D9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1896 0x4113DA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1897 0x4113DA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1898 0x4113DA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1899 0x4113DAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1900 0x4113DB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1901 0x4113DB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1902 0x4113DB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1903 0x4113DBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1904 0x4113DC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1905 0x4113DC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1906 0x4113DC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1907 0x4113DCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1908 0x4113DD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1909 0x4113DD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1910 0x4113DD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1911 0x4113DDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1912 0x4113DE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1913 0x4113DE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1914 0x4113DE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1915 0x4113DEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1916 0x4113DF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1917 0x4113DF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1918 0x4113DF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1919 0x4113DFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1920 0x4113E00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1921 0x4113E04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1922 0x4113E08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1923 0x4113E0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1924 0x4113E10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1925 0x4113E14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1926 0x4113E18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1927 0x4113E1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1928 0x4113E20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1929 0x4113E24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1930 0x4113E28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1931 0x4113E2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1932 0x4113E30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1933 0x4113E34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1934 0x4113E38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1935 0x4113E3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1936 0x4113E40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1937 0x4113E44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1938 0x4113E48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1939 0x4113E4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1940 0x4113E50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1941 0x4113E54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1942 0x4113E58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1943 0x4113E5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1944 0x4113E60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1945 0x4113E64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1946 0x4113E68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1947 0x4113E6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1948 0x4113E70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1949 0x4113E74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1950 0x4113E78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1951 0x4113E7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1952 0x4113E80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1953 0x4113E84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1954 0x4113E88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1955 0x4113E8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1956 0x4113E90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1957 0x4113E94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1958 0x4113E98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1959 0x4113E9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1960 0x4113EA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1961 0x4113EA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1962 0x4113EA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1963 0x4113EAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1964 0x4113EB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1965 0x4113EB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1966 0x4113EB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1967 0x4113EBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1968 0x4113EC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1969 0x4113EC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1970 0x4113EC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1971 0x4113ECC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1972 0x4113ED0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1973 0x4113ED4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1974 0x4113ED8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1975 0x4113EDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1976 0x4113EE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1977 0x4113EE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1978 0x4113EE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1979 0x4113EEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1980 0x4113EF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1981 0x4113EF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1982 0x4113EF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1983 0x4113EFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1984 0x4113F00
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1985 0x4113F04
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1986 0x4113F08
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1987 0x4113F0C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1988 0x4113F10
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1989 0x4113F14
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1990 0x4113F18
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1991 0x4113F1C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1992 0x4113F20
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1993 0x4113F24
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1994 0x4113F28
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1995 0x4113F2C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1996 0x4113F30
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1997 0x4113F34
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1998 0x4113F38
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_1999 0x4113F3C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2000 0x4113F40
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2001 0x4113F44
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2002 0x4113F48
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2003 0x4113F4C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2004 0x4113F50
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2005 0x4113F54
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2006 0x4113F58
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2007 0x4113F5C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2008 0x4113F60
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2009 0x4113F64
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2010 0x4113F68
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2011 0x4113F6C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2012 0x4113F70
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2013 0x4113F74
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2014 0x4113F78
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2015 0x4113F7C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2016 0x4113F80
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2017 0x4113F84
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2018 0x4113F88
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2019 0x4113F8C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2020 0x4113F90
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2021 0x4113F94
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2022 0x4113F98
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2023 0x4113F9C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2024 0x4113FA0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2025 0x4113FA4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2026 0x4113FA8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2027 0x4113FAC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2028 0x4113FB0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2029 0x4113FB4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2030 0x4113FB8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2031 0x4113FBC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2032 0x4113FC0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2033 0x4113FC4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2034 0x4113FC8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2035 0x4113FCC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2036 0x4113FD0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2037 0x4113FD4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2038 0x4113FD8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2039 0x4113FDC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2040 0x4113FE0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2041 0x4113FE4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2042 0x4113FE8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2043 0x4113FEC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2044 0x4113FF0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2045 0x4113FF4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2046 0x4113FF8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2047 0x4113FFC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_0 0x4114000
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_1 0x4114004
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_2 0x4114008
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_3 0x411400C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_4 0x4114010
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_5 0x4114014
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_6 0x4114018
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_7 0x411401C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_8 0x4114020
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_9 0x4114024
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_10 0x4114028
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_11 0x411402C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_12 0x4114030
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_13 0x4114034
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_14 0x4114038
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_15 0x411403C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_16 0x4114040
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_17 0x4114044
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_18 0x4114048
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_19 0x411404C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_20 0x4114050
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_21 0x4114054
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_22 0x4114058
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_23 0x411405C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_24 0x4114060
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_25 0x4114064
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_26 0x4114068
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_27 0x411406C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_28 0x4114070
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_29 0x4114074
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_30 0x4114078
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_31 0x411407C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_32 0x4114080
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_33 0x4114084
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_34 0x4114088
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_35 0x411408C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_36 0x4114090
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_37 0x4114094
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_38 0x4114098
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_39 0x411409C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_40 0x41140A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_41 0x41140A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_42 0x41140A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_43 0x41140AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_44 0x41140B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_45 0x41140B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_46 0x41140B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_47 0x41140BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_48 0x41140C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_49 0x41140C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_50 0x41140C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_51 0x41140CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_52 0x41140D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_53 0x41140D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_54 0x41140D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_55 0x41140DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_56 0x41140E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_57 0x41140E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_58 0x41140E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_59 0x41140EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_60 0x41140F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_61 0x41140F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_62 0x41140F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_63 0x41140FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_64 0x4114100
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_65 0x4114104
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_66 0x4114108
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_67 0x411410C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_68 0x4114110
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_69 0x4114114
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_70 0x4114118
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_71 0x411411C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_72 0x4114120
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_73 0x4114124
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_74 0x4114128
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_75 0x411412C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_76 0x4114130
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_77 0x4114134
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_78 0x4114138
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_79 0x411413C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_80 0x4114140
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_81 0x4114144
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_82 0x4114148
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_83 0x411414C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_84 0x4114150
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_85 0x4114154
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_86 0x4114158
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_87 0x411415C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_88 0x4114160
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_89 0x4114164
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_90 0x4114168
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_91 0x411416C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_92 0x4114170
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_93 0x4114174
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_94 0x4114178
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_95 0x411417C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_96 0x4114180
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_97 0x4114184
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_98 0x4114188
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_99 0x411418C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_100 0x4114190
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_101 0x4114194
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_102 0x4114198
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_103 0x411419C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_104 0x41141A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_105 0x41141A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_106 0x41141A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_107 0x41141AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_108 0x41141B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_109 0x41141B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_110 0x41141B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_111 0x41141BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_112 0x41141C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_113 0x41141C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_114 0x41141C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_115 0x41141CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_116 0x41141D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_117 0x41141D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_118 0x41141D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_119 0x41141DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_120 0x41141E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_121 0x41141E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_122 0x41141E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_123 0x41141EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_124 0x41141F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_125 0x41141F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_126 0x41141F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_127 0x41141FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_128 0x4114200
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_129 0x4114204
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_130 0x4114208
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_131 0x411420C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_132 0x4114210
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_133 0x4114214
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_134 0x4114218
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_135 0x411421C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_136 0x4114220
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_137 0x4114224
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_138 0x4114228
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_139 0x411422C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_140 0x4114230
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_141 0x4114234
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_142 0x4114238
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_143 0x411423C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_144 0x4114240
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_145 0x4114244
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_146 0x4114248
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_147 0x411424C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_148 0x4114250
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_149 0x4114254
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_150 0x4114258
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_151 0x411425C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_152 0x4114260
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_153 0x4114264
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_154 0x4114268
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_155 0x411426C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_156 0x4114270
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_157 0x4114274
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_158 0x4114278
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_159 0x411427C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_160 0x4114280
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_161 0x4114284
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_162 0x4114288
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_163 0x411428C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_164 0x4114290
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_165 0x4114294
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_166 0x4114298
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_167 0x411429C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_168 0x41142A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_169 0x41142A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_170 0x41142A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_171 0x41142AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_172 0x41142B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_173 0x41142B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_174 0x41142B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_175 0x41142BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_176 0x41142C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_177 0x41142C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_178 0x41142C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_179 0x41142CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_180 0x41142D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_181 0x41142D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_182 0x41142D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_183 0x41142DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_184 0x41142E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_185 0x41142E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_186 0x41142E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_187 0x41142EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_188 0x41142F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_189 0x41142F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_190 0x41142F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_191 0x41142FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_192 0x4114300
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_193 0x4114304
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_194 0x4114308
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_195 0x411430C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_196 0x4114310
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_197 0x4114314
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_198 0x4114318
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_199 0x411431C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_200 0x4114320
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_201 0x4114324
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_202 0x4114328
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_203 0x411432C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_204 0x4114330
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_205 0x4114334
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_206 0x4114338
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_207 0x411433C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_208 0x4114340
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_209 0x4114344
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_210 0x4114348
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_211 0x411434C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_212 0x4114350
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_213 0x4114354
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_214 0x4114358
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_215 0x411435C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_216 0x4114360
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_217 0x4114364
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_218 0x4114368
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_219 0x411436C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_220 0x4114370
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_221 0x4114374
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_222 0x4114378
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_223 0x411437C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_224 0x4114380
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_225 0x4114384
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_226 0x4114388
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_227 0x411438C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_228 0x4114390
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_229 0x4114394
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_230 0x4114398
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_231 0x411439C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_232 0x41143A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_233 0x41143A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_234 0x41143A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_235 0x41143AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_236 0x41143B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_237 0x41143B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_238 0x41143B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_239 0x41143BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_240 0x41143C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_241 0x41143C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_242 0x41143C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_243 0x41143CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_244 0x41143D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_245 0x41143D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_246 0x41143D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_247 0x41143DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_248 0x41143E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_249 0x41143E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_250 0x41143E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_251 0x41143EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_252 0x41143F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_253 0x41143F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_254 0x41143F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_255 0x41143FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_256 0x4114400
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_257 0x4114404
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_258 0x4114408
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_259 0x411440C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_260 0x4114410
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_261 0x4114414
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_262 0x4114418
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_263 0x411441C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_264 0x4114420
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_265 0x4114424
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_266 0x4114428
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_267 0x411442C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_268 0x4114430
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_269 0x4114434
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_270 0x4114438
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_271 0x411443C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_272 0x4114440
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_273 0x4114444
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_274 0x4114448
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_275 0x411444C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_276 0x4114450
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_277 0x4114454
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_278 0x4114458
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_279 0x411445C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_280 0x4114460
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_281 0x4114464
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_282 0x4114468
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_283 0x411446C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_284 0x4114470
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_285 0x4114474
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_286 0x4114478
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_287 0x411447C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_288 0x4114480
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_289 0x4114484
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_290 0x4114488
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_291 0x411448C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_292 0x4114490
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_293 0x4114494
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_294 0x4114498
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_295 0x411449C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_296 0x41144A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_297 0x41144A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_298 0x41144A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_299 0x41144AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_300 0x41144B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_301 0x41144B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_302 0x41144B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_303 0x41144BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_304 0x41144C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_305 0x41144C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_306 0x41144C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_307 0x41144CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_308 0x41144D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_309 0x41144D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_310 0x41144D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_311 0x41144DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_312 0x41144E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_313 0x41144E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_314 0x41144E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_315 0x41144EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_316 0x41144F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_317 0x41144F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_318 0x41144F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_319 0x41144FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_320 0x4114500
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_321 0x4114504
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_322 0x4114508
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_323 0x411450C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_324 0x4114510
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_325 0x4114514
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_326 0x4114518
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_327 0x411451C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_328 0x4114520
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_329 0x4114524
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_330 0x4114528
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_331 0x411452C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_332 0x4114530
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_333 0x4114534
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_334 0x4114538
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_335 0x411453C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_336 0x4114540
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_337 0x4114544
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_338 0x4114548
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_339 0x411454C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_340 0x4114550
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_341 0x4114554
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_342 0x4114558
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_343 0x411455C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_344 0x4114560
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_345 0x4114564
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_346 0x4114568
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_347 0x411456C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_348 0x4114570
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_349 0x4114574
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_350 0x4114578
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_351 0x411457C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_352 0x4114580
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_353 0x4114584
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_354 0x4114588
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_355 0x411458C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_356 0x4114590
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_357 0x4114594
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_358 0x4114598
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_359 0x411459C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_360 0x41145A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_361 0x41145A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_362 0x41145A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_363 0x41145AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_364 0x41145B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_365 0x41145B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_366 0x41145B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_367 0x41145BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_368 0x41145C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_369 0x41145C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_370 0x41145C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_371 0x41145CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_372 0x41145D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_373 0x41145D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_374 0x41145D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_375 0x41145DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_376 0x41145E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_377 0x41145E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_378 0x41145E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_379 0x41145EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_380 0x41145F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_381 0x41145F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_382 0x41145F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_383 0x41145FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_384 0x4114600
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_385 0x4114604
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_386 0x4114608
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_387 0x411460C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_388 0x4114610
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_389 0x4114614
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_390 0x4114618
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_391 0x411461C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_392 0x4114620
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_393 0x4114624
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_394 0x4114628
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_395 0x411462C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_396 0x4114630
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_397 0x4114634
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_398 0x4114638
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_399 0x411463C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_400 0x4114640
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_401 0x4114644
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_402 0x4114648
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_403 0x411464C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_404 0x4114650
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_405 0x4114654
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_406 0x4114658
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_407 0x411465C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_408 0x4114660
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_409 0x4114664
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_410 0x4114668
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_411 0x411466C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_412 0x4114670
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_413 0x4114674
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_414 0x4114678
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_415 0x411467C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_416 0x4114680
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_417 0x4114684
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_418 0x4114688
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_419 0x411468C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_420 0x4114690
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_421 0x4114694
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_422 0x4114698
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_423 0x411469C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_424 0x41146A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_425 0x41146A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_426 0x41146A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_427 0x41146AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_428 0x41146B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_429 0x41146B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_430 0x41146B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_431 0x41146BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_432 0x41146C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_433 0x41146C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_434 0x41146C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_435 0x41146CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_436 0x41146D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_437 0x41146D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_438 0x41146D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_439 0x41146DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_440 0x41146E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_441 0x41146E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_442 0x41146E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_443 0x41146EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_444 0x41146F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_445 0x41146F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_446 0x41146F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_447 0x41146FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_448 0x4114700
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_449 0x4114704
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_450 0x4114708
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_451 0x411470C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_452 0x4114710
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_453 0x4114714
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_454 0x4114718
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_455 0x411471C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_456 0x4114720
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_457 0x4114724
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_458 0x4114728
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_459 0x411472C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_460 0x4114730
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_461 0x4114734
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_462 0x4114738
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_463 0x411473C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_464 0x4114740
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_465 0x4114744
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_466 0x4114748
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_467 0x411474C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_468 0x4114750
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_469 0x4114754
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_470 0x4114758
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_471 0x411475C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_472 0x4114760
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_473 0x4114764
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_474 0x4114768
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_475 0x411476C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_476 0x4114770
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_477 0x4114774
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_478 0x4114778
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_479 0x411477C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_480 0x4114780
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_481 0x4114784
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_482 0x4114788
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_483 0x411478C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_484 0x4114790
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_485 0x4114794
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_486 0x4114798
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_487 0x411479C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_488 0x41147A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_489 0x41147A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_490 0x41147A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_491 0x41147AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_492 0x41147B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_493 0x41147B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_494 0x41147B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_495 0x41147BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_496 0x41147C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_497 0x41147C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_498 0x41147C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_499 0x41147CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_500 0x41147D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_501 0x41147D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_502 0x41147D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_503 0x41147DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_504 0x41147E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_505 0x41147E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_506 0x41147E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_507 0x41147EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_508 0x41147F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_509 0x41147F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_510 0x41147F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_511 0x41147FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_512 0x4114800
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_513 0x4114804
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_514 0x4114808
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_515 0x411480C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_516 0x4114810
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_517 0x4114814
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_518 0x4114818
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_519 0x411481C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_520 0x4114820
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_521 0x4114824
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_522 0x4114828
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_523 0x411482C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_524 0x4114830
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_525 0x4114834
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_526 0x4114838
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_527 0x411483C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_528 0x4114840
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_529 0x4114844
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_530 0x4114848
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_531 0x411484C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_532 0x4114850
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_533 0x4114854
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_534 0x4114858
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_535 0x411485C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_536 0x4114860
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_537 0x4114864
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_538 0x4114868
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_539 0x411486C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_540 0x4114870
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_541 0x4114874
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_542 0x4114878
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_543 0x411487C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_544 0x4114880
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_545 0x4114884
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_546 0x4114888
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_547 0x411488C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_548 0x4114890
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_549 0x4114894
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_550 0x4114898
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_551 0x411489C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_552 0x41148A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_553 0x41148A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_554 0x41148A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_555 0x41148AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_556 0x41148B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_557 0x41148B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_558 0x41148B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_559 0x41148BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_560 0x41148C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_561 0x41148C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_562 0x41148C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_563 0x41148CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_564 0x41148D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_565 0x41148D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_566 0x41148D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_567 0x41148DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_568 0x41148E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_569 0x41148E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_570 0x41148E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_571 0x41148EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_572 0x41148F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_573 0x41148F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_574 0x41148F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_575 0x41148FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_576 0x4114900
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_577 0x4114904
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_578 0x4114908
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_579 0x411490C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_580 0x4114910
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_581 0x4114914
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_582 0x4114918
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_583 0x411491C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_584 0x4114920
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_585 0x4114924
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_586 0x4114928
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_587 0x411492C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_588 0x4114930
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_589 0x4114934
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_590 0x4114938
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_591 0x411493C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_592 0x4114940
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_593 0x4114944
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_594 0x4114948
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_595 0x411494C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_596 0x4114950
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_597 0x4114954
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_598 0x4114958
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_599 0x411495C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_600 0x4114960
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_601 0x4114964
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_602 0x4114968
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_603 0x411496C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_604 0x4114970
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_605 0x4114974
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_606 0x4114978
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_607 0x411497C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_608 0x4114980
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_609 0x4114984
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_610 0x4114988
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_611 0x411498C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_612 0x4114990
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_613 0x4114994
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_614 0x4114998
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_615 0x411499C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_616 0x41149A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_617 0x41149A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_618 0x41149A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_619 0x41149AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_620 0x41149B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_621 0x41149B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_622 0x41149B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_623 0x41149BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_624 0x41149C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_625 0x41149C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_626 0x41149C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_627 0x41149CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_628 0x41149D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_629 0x41149D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_630 0x41149D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_631 0x41149DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_632 0x41149E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_633 0x41149E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_634 0x41149E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_635 0x41149EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_636 0x41149F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_637 0x41149F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_638 0x41149F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_639 0x41149FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_0 0x4115000
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_1 0x4115004
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_2 0x4115008
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_3 0x411500C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_4 0x4115010
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_5 0x4115014
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_6 0x4115018
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_7 0x411501C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_8 0x4115020
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_9 0x4115024
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_10 0x4115028
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_11 0x411502C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_12 0x4115030
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_13 0x4115034
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_14 0x4115038
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_15 0x411503C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_16 0x4115040
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_17 0x4115044
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_18 0x4115048
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_19 0x411504C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_20 0x4115050
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_21 0x4115054
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_22 0x4115058
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_23 0x411505C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_24 0x4115060
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_25 0x4115064
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_26 0x4115068
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_27 0x411506C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_28 0x4115070
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_29 0x4115074
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_30 0x4115078
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_31 0x411507C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_32 0x4115080
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_33 0x4115084
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_34 0x4115088
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_35 0x411508C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_36 0x4115090
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_37 0x4115094
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_38 0x4115098
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_39 0x411509C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_40 0x41150A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_41 0x41150A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_42 0x41150A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_43 0x41150AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_44 0x41150B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_45 0x41150B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_46 0x41150B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_47 0x41150BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_48 0x41150C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_49 0x41150C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_50 0x41150C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_51 0x41150CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_52 0x41150D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_53 0x41150D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_54 0x41150D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_55 0x41150DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_56 0x41150E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_57 0x41150E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_58 0x41150E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_59 0x41150EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_60 0x41150F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_61 0x41150F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_62 0x41150F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_63 0x41150FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_64 0x4115100
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_65 0x4115104
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_66 0x4115108
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_67 0x411510C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_68 0x4115110
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_69 0x4115114
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_70 0x4115118
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_71 0x411511C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_72 0x4115120
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_73 0x4115124
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_74 0x4115128
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_75 0x411512C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_76 0x4115130
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_77 0x4115134
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_78 0x4115138
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_79 0x411513C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_80 0x4115140
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_81 0x4115144
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_82 0x4115148
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_83 0x411514C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_84 0x4115150
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_85 0x4115154
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_86 0x4115158
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_87 0x411515C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_88 0x4115160
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_89 0x4115164
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_90 0x4115168
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_91 0x411516C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_92 0x4115170
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_93 0x4115174
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_94 0x4115178
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_95 0x411517C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_96 0x4115180
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_97 0x4115184
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_98 0x4115188
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_99 0x411518C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_100 0x4115190
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_101 0x4115194
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_102 0x4115198
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_103 0x411519C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_104 0x41151A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_105 0x41151A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_106 0x41151A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_107 0x41151AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_108 0x41151B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_109 0x41151B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_110 0x41151B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_111 0x41151BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_112 0x41151C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_113 0x41151C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_114 0x41151C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_115 0x41151CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_116 0x41151D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_117 0x41151D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_118 0x41151D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_119 0x41151DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_120 0x41151E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_121 0x41151E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_122 0x41151E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_123 0x41151EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_124 0x41151F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_125 0x41151F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_126 0x41151F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_127 0x41151FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_128 0x4115200
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_129 0x4115204
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_130 0x4115208
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_131 0x411520C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_132 0x4115210
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_133 0x4115214
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_134 0x4115218
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_135 0x411521C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_136 0x4115220
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_137 0x4115224
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_138 0x4115228
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_139 0x411522C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_140 0x4115230
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_141 0x4115234
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_142 0x4115238
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_143 0x411523C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_144 0x4115240
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_145 0x4115244
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_146 0x4115248
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_147 0x411524C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_148 0x4115250
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_149 0x4115254
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_150 0x4115258
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_151 0x411525C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_152 0x4115260
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_153 0x4115264
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_154 0x4115268
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_155 0x411526C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_156 0x4115270
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_157 0x4115274
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_158 0x4115278
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_159 0x411527C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_160 0x4115280
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_161 0x4115284
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_162 0x4115288
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_163 0x411528C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_164 0x4115290
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_165 0x4115294
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_166 0x4115298
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_167 0x411529C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_168 0x41152A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_169 0x41152A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_170 0x41152A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_171 0x41152AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_172 0x41152B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_173 0x41152B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_174 0x41152B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_175 0x41152BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_176 0x41152C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_177 0x41152C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_178 0x41152C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_179 0x41152CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_180 0x41152D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_181 0x41152D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_182 0x41152D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_183 0x41152DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_184 0x41152E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_185 0x41152E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_186 0x41152E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_187 0x41152EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_188 0x41152F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_189 0x41152F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_190 0x41152F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_191 0x41152FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_192 0x4115300
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_193 0x4115304
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_194 0x4115308
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_195 0x411530C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_196 0x4115310
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_197 0x4115314
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_198 0x4115318
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_199 0x411531C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_200 0x4115320
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_201 0x4115324
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_202 0x4115328
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_203 0x411532C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_204 0x4115330
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_205 0x4115334
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_206 0x4115338
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_207 0x411533C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_208 0x4115340
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_209 0x4115344
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_210 0x4115348
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_211 0x411534C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_212 0x4115350
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_213 0x4115354
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_214 0x4115358
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_215 0x411535C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_216 0x4115360
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_217 0x4115364
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_218 0x4115368
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_219 0x411536C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_220 0x4115370
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_221 0x4115374
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_222 0x4115378
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_223 0x411537C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_224 0x4115380
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_225 0x4115384
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_226 0x4115388
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_227 0x411538C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_228 0x4115390
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_229 0x4115394
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_230 0x4115398
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_231 0x411539C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_232 0x41153A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_233 0x41153A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_234 0x41153A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_235 0x41153AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_236 0x41153B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_237 0x41153B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_238 0x41153B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_239 0x41153BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_240 0x41153C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_241 0x41153C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_242 0x41153C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_243 0x41153CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_244 0x41153D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_245 0x41153D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_246 0x41153D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_247 0x41153DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_248 0x41153E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_249 0x41153E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_250 0x41153E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_251 0x41153EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_252 0x41153F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_253 0x41153F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_254 0x41153F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_255 0x41153FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_256 0x4115400
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_257 0x4115404
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_258 0x4115408
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_259 0x411540C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_260 0x4115410
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_261 0x4115414
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_262 0x4115418
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_263 0x411541C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_264 0x4115420
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_265 0x4115424
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_266 0x4115428
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_267 0x411542C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_268 0x4115430
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_269 0x4115434
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_270 0x4115438
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_271 0x411543C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_272 0x4115440
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_273 0x4115444
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_274 0x4115448
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_275 0x411544C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_276 0x4115450
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_277 0x4115454
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_278 0x4115458
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_279 0x411545C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_280 0x4115460
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_281 0x4115464
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_282 0x4115468
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_283 0x411546C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_284 0x4115470
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_285 0x4115474
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_286 0x4115478
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_287 0x411547C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_288 0x4115480
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_289 0x4115484
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_290 0x4115488
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_291 0x411548C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_292 0x4115490
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_293 0x4115494
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_294 0x4115498
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_295 0x411549C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_296 0x41154A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_297 0x41154A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_298 0x41154A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_299 0x41154AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_300 0x41154B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_301 0x41154B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_302 0x41154B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_303 0x41154BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_304 0x41154C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_305 0x41154C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_306 0x41154C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_307 0x41154CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_308 0x41154D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_309 0x41154D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_310 0x41154D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_311 0x41154DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_312 0x41154E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_313 0x41154E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_314 0x41154E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_315 0x41154EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_316 0x41154F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_317 0x41154F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_318 0x41154F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_319 0x41154FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_320 0x4115500
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_321 0x4115504
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_322 0x4115508
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_323 0x411550C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_324 0x4115510
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_325 0x4115514
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_326 0x4115518
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_327 0x411551C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_328 0x4115520
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_329 0x4115524
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_330 0x4115528
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_331 0x411552C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_332 0x4115530
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_333 0x4115534
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_334 0x4115538
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_335 0x411553C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_336 0x4115540
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_337 0x4115544
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_338 0x4115548
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_339 0x411554C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_340 0x4115550
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_341 0x4115554
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_342 0x4115558
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_343 0x411555C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_344 0x4115560
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_345 0x4115564
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_346 0x4115568
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_347 0x411556C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_348 0x4115570
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_349 0x4115574
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_350 0x4115578
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_351 0x411557C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_352 0x4115580
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_353 0x4115584
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_354 0x4115588
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_355 0x411558C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_356 0x4115590
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_357 0x4115594
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_358 0x4115598
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_359 0x411559C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_360 0x41155A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_361 0x41155A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_362 0x41155A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_363 0x41155AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_364 0x41155B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_365 0x41155B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_366 0x41155B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_367 0x41155BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_368 0x41155C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_369 0x41155C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_370 0x41155C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_371 0x41155CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_372 0x41155D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_373 0x41155D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_374 0x41155D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_375 0x41155DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_376 0x41155E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_377 0x41155E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_378 0x41155E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_379 0x41155EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_380 0x41155F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_381 0x41155F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_382 0x41155F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_383 0x41155FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_384 0x4115600
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_385 0x4115604
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_386 0x4115608
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_387 0x411560C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_388 0x4115610
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_389 0x4115614
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_390 0x4115618
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_391 0x411561C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_392 0x4115620
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_393 0x4115624
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_394 0x4115628
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_395 0x411562C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_396 0x4115630
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_397 0x4115634
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_398 0x4115638
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_399 0x411563C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_400 0x4115640
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_401 0x4115644
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_402 0x4115648
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_403 0x411564C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_404 0x4115650
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_405 0x4115654
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_406 0x4115658
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_407 0x411565C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_408 0x4115660
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_409 0x4115664
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_410 0x4115668
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_411 0x411566C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_412 0x4115670
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_413 0x4115674
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_414 0x4115678
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_415 0x411567C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_416 0x4115680
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_417 0x4115684
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_418 0x4115688
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_419 0x411568C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_420 0x4115690
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_421 0x4115694
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_422 0x4115698
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_423 0x411569C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_424 0x41156A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_425 0x41156A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_426 0x41156A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_427 0x41156AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_428 0x41156B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_429 0x41156B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_430 0x41156B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_431 0x41156BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_432 0x41156C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_433 0x41156C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_434 0x41156C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_435 0x41156CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_436 0x41156D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_437 0x41156D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_438 0x41156D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_439 0x41156DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_440 0x41156E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_441 0x41156E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_442 0x41156E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_443 0x41156EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_444 0x41156F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_445 0x41156F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_446 0x41156F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_447 0x41156FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_448 0x4115700
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_449 0x4115704
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_450 0x4115708
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_451 0x411570C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_452 0x4115710
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_453 0x4115714
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_454 0x4115718
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_455 0x411571C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_456 0x4115720
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_457 0x4115724
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_458 0x4115728
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_459 0x411572C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_460 0x4115730
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_461 0x4115734
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_462 0x4115738
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_463 0x411573C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_464 0x4115740
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_465 0x4115744
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_466 0x4115748
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_467 0x411574C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_468 0x4115750
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_469 0x4115754
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_470 0x4115758
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_471 0x411575C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_472 0x4115760
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_473 0x4115764
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_474 0x4115768
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_475 0x411576C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_476 0x4115770
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_477 0x4115774
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_478 0x4115778
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_479 0x411577C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_480 0x4115780
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_481 0x4115784
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_482 0x4115788
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_483 0x411578C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_484 0x4115790
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_485 0x4115794
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_486 0x4115798
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_487 0x411579C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_488 0x41157A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_489 0x41157A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_490 0x41157A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_491 0x41157AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_492 0x41157B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_493 0x41157B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_494 0x41157B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_495 0x41157BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_496 0x41157C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_497 0x41157C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_498 0x41157C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_499 0x41157CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_500 0x41157D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_501 0x41157D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_502 0x41157D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_503 0x41157DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_504 0x41157E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_505 0x41157E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_506 0x41157E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_507 0x41157EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_508 0x41157F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_509 0x41157F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_510 0x41157F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_511 0x41157FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_512 0x4115800
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_513 0x4115804
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_514 0x4115808
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_515 0x411580C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_516 0x4115810
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_517 0x4115814
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_518 0x4115818
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_519 0x411581C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_520 0x4115820
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_521 0x4115824
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_522 0x4115828
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_523 0x411582C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_524 0x4115830
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_525 0x4115834
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_526 0x4115838
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_527 0x411583C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_528 0x4115840
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_529 0x4115844
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_530 0x4115848
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_531 0x411584C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_532 0x4115850
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_533 0x4115854
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_534 0x4115858
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_535 0x411585C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_536 0x4115860
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_537 0x4115864
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_538 0x4115868
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_539 0x411586C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_540 0x4115870
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_541 0x4115874
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_542 0x4115878
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_543 0x411587C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_544 0x4115880
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_545 0x4115884
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_546 0x4115888
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_547 0x411588C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_548 0x4115890
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_549 0x4115894
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_550 0x4115898
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_551 0x411589C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_552 0x41158A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_553 0x41158A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_554 0x41158A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_555 0x41158AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_556 0x41158B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_557 0x41158B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_558 0x41158B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_559 0x41158BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_560 0x41158C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_561 0x41158C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_562 0x41158C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_563 0x41158CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_564 0x41158D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_565 0x41158D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_566 0x41158D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_567 0x41158DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_568 0x41158E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_569 0x41158E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_570 0x41158E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_571 0x41158EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_572 0x41158F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_573 0x41158F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_574 0x41158F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_575 0x41158FC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_576 0x4115900
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_577 0x4115904
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_578 0x4115908
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_579 0x411590C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_580 0x4115910
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_581 0x4115914
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_582 0x4115918
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_583 0x411591C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_584 0x4115920
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_585 0x4115924
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_586 0x4115928
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_587 0x411592C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_588 0x4115930
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_589 0x4115934
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_590 0x4115938
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_591 0x411593C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_592 0x4115940
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_593 0x4115944
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_594 0x4115948
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_595 0x411594C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_596 0x4115950
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_597 0x4115954
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_598 0x4115958
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_599 0x411595C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_600 0x4115960
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_601 0x4115964
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_602 0x4115968
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_603 0x411596C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_604 0x4115970
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_605 0x4115974
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_606 0x4115978
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_607 0x411597C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_608 0x4115980
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_609 0x4115984
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_610 0x4115988
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_611 0x411598C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_612 0x4115990
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_613 0x4115994
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_614 0x4115998
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_615 0x411599C
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_616 0x41159A0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_617 0x41159A4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_618 0x41159A8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_619 0x41159AC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_620 0x41159B0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_621 0x41159B4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_622 0x41159B8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_623 0x41159BC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_624 0x41159C0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_625 0x41159C4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_626 0x41159C8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_627 0x41159CC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_628 0x41159D0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_629 0x41159D4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_630 0x41159D8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_631 0x41159DC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_632 0x41159E0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_633 0x41159E4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_634 0x41159E8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_635 0x41159EC
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_636 0x41159F0
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_637 0x41159F4
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_638 0x41159F8
+
+#define mmDCORE0_SYNC_MNGR_OBJS_SM_PRIV_639 0x41159FC
+
+#endif /* ASIC_REG_DCORE0_SYNC_MNGR_OBJS_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_axuser_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_axuser_regs.h
new file mode 100644
index 000000000000..2d4a22680a23
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_axuser_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_TPC0_CFG_AXUSER_REGS_H_
+#define ASIC_REG_DCORE0_TPC0_CFG_AXUSER_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_TPC0_CFG_AXUSER
+ *   (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define mmDCORE0_TPC0_CFG_AXUSER_HB_ASID 0x400BE00
+
+#define mmDCORE0_TPC0_CFG_AXUSER_HB_MMU_BP 0x400BE04
+
+#define mmDCORE0_TPC0_CFG_AXUSER_HB_STRONG_ORDER 0x400BE08
+
+#define mmDCORE0_TPC0_CFG_AXUSER_HB_NO_SNOOP 0x400BE0C
+
+#define mmDCORE0_TPC0_CFG_AXUSER_HB_WR_REDUCTION 0x400BE10
+
+#define mmDCORE0_TPC0_CFG_AXUSER_HB_RD_ATOMIC 0x400BE14
+
+#define mmDCORE0_TPC0_CFG_AXUSER_HB_QOS 0x400BE18
+
+#define mmDCORE0_TPC0_CFG_AXUSER_HB_RSVD 0x400BE1C
+
+#define mmDCORE0_TPC0_CFG_AXUSER_HB_EMEM_CPAGE 0x400BE20
+
+#define mmDCORE0_TPC0_CFG_AXUSER_HB_CORE 0x400BE24
+
+#define mmDCORE0_TPC0_CFG_AXUSER_E2E_COORD 0x400BE28
+
+#define mmDCORE0_TPC0_CFG_AXUSER_HB_WR_OVRD_LO 0x400BE30
+
+#define mmDCORE0_TPC0_CFG_AXUSER_HB_WR_OVRD_HI 0x400BE34
+
+#define mmDCORE0_TPC0_CFG_AXUSER_HB_RD_OVRD_LO 0x400BE38
+
+#define mmDCORE0_TPC0_CFG_AXUSER_HB_RD_OVRD_HI 0x400BE3C
+
+#define mmDCORE0_TPC0_CFG_AXUSER_LB_COORD 0x400BE40
+
+#define mmDCORE0_TPC0_CFG_AXUSER_LB_LOCK 0x400BE44
+
+#define mmDCORE0_TPC0_CFG_AXUSER_LB_RSVD 0x400BE48
+
+#define mmDCORE0_TPC0_CFG_AXUSER_LB_OVRD 0x400BE4C
+
+#endif /* ASIC_REG_DCORE0_TPC0_CFG_AXUSER_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_kernel_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_kernel_regs.h
new file mode 100644
index 000000000000..cdab39debd2c
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_kernel_regs.h
@@ -0,0 +1,129 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_TPC0_CFG_KERNEL_REGS_H_
+#define ASIC_REG_DCORE0_TPC0_CFG_KERNEL_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_TPC0_CFG_KERNEL
+ *   (Prototype: TPC_NON_TENSOR_DESCRIPTOR)
+ *****************************************
+ */
+
+#define mmDCORE0_TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0x400B508
+
+#define mmDCORE0_TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0x400B50C
+
+#define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_DIM_0 0x400B510
+
+#define mmDCORE0_TPC0_CFG_KERNEL_TID_SIZE_DIM_0 0x400B514
+
+#define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_DIM_1 0x400B518
+
+#define mmDCORE0_TPC0_CFG_KERNEL_TID_SIZE_DIM_1 0x400B51C
+
+#define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_DIM_2 0x400B520
+
+#define mmDCORE0_TPC0_CFG_KERNEL_TID_SIZE_DIM_2 0x400B524
+
+#define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_DIM_3 0x400B528
+
+#define mmDCORE0_TPC0_CFG_KERNEL_TID_SIZE_DIM_3 0x400B52C
+
+#define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_DIM_4 0x400B530
+
+#define mmDCORE0_TPC0_CFG_KERNEL_TID_SIZE_DIM_4 0x400B534
+
+#define mmDCORE0_TPC0_CFG_KERNEL_KERNEL_CONFIG 0x400B538
+
+#define mmDCORE0_TPC0_CFG_KERNEL_KERNEL_ID 0x400B53C
+
+#define mmDCORE0_TPC0_CFG_KERNEL_POWER_LOOP 0x400B540
+
+#define mmDCORE0_TPC0_CFG_KERNEL_SRF_0 0x400B544
+
+#define mmDCORE0_TPC0_CFG_KERNEL_SRF_1 0x400B548
+
+#define mmDCORE0_TPC0_CFG_KERNEL_SRF_2 0x400B54C
+
+#define mmDCORE0_TPC0_CFG_KERNEL_SRF_3 0x400B550
+
+#define mmDCORE0_TPC0_CFG_KERNEL_SRF_4 0x400B554
+
+#define mmDCORE0_TPC0_CFG_KERNEL_SRF_5 0x400B558
+
+#define mmDCORE0_TPC0_CFG_KERNEL_SRF_6 0x400B55C
+
+#define mmDCORE0_TPC0_CFG_KERNEL_SRF_7 0x400B560
+
+#define mmDCORE0_TPC0_CFG_KERNEL_SRF_8 0x400B564
+
+#define mmDCORE0_TPC0_CFG_KERNEL_SRF_9 0x400B568
+
+#define mmDCORE0_TPC0_CFG_KERNEL_SRF_10 0x400B56C
+
+#define mmDCORE0_TPC0_CFG_KERNEL_SRF_11 0x400B570
+
+#define mmDCORE0_TPC0_CFG_KERNEL_SRF_12 0x400B574
+
+#define mmDCORE0_TPC0_CFG_KERNEL_SRF_13 0x400B578
+
+#define mmDCORE0_TPC0_CFG_KERNEL_SRF_14 0x400B57C
+
+#define mmDCORE0_TPC0_CFG_KERNEL_SRF_15 0x400B580
+
+#define mmDCORE0_TPC0_CFG_KERNEL_SRF_16 0x400B584
+
+#define mmDCORE0_TPC0_CFG_KERNEL_SRF_17 0x400B588
+
+#define mmDCORE0_TPC0_CFG_KERNEL_SRF_18 0x400B58C
+
+#define mmDCORE0_TPC0_CFG_KERNEL_SRF_19 0x400B590
+
+#define mmDCORE0_TPC0_CFG_KERNEL_SRF_20 0x400B594
+
+#define mmDCORE0_TPC0_CFG_KERNEL_SRF_21 0x400B598
+
+#define mmDCORE0_TPC0_CFG_KERNEL_SRF_22 0x400B59C
+
+#define mmDCORE0_TPC0_CFG_KERNEL_SRF_23 0x400B5A0
+
+#define mmDCORE0_TPC0_CFG_KERNEL_SRF_24 0x400B5A4
+
+#define mmDCORE0_TPC0_CFG_KERNEL_SRF_25 0x400B5A8
+
+#define mmDCORE0_TPC0_CFG_KERNEL_SRF_26 0x400B5AC
+
+#define mmDCORE0_TPC0_CFG_KERNEL_SRF_27 0x400B5B0
+
+#define mmDCORE0_TPC0_CFG_KERNEL_SRF_28 0x400B5B4
+
+#define mmDCORE0_TPC0_CFG_KERNEL_SRF_29 0x400B5B8
+
+#define mmDCORE0_TPC0_CFG_KERNEL_SRF_30 0x400B5BC
+
+#define mmDCORE0_TPC0_CFG_KERNEL_SRF_31 0x400B5C0
+
+#define mmDCORE0_TPC0_CFG_KERNEL_KERNEL_ID_INC 0x400B5C4
+
+#define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_SIZE_HIGH_DIM_0 0x400B5C8
+
+#define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_SIZE_HIGH_DIM_1 0x400B5CC
+
+#define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_SIZE_HIGH_DIM_2 0x400B5D0
+
+#define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_SIZE_HIGH_DIM_3 0x400B5D4
+
+#define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_SIZE_HIGH_DIM_4 0x400B5D8
+
+#endif /* ASIC_REG_DCORE0_TPC0_CFG_KERNEL_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_kernel_tensor_0_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_kernel_tensor_0_regs.h
new file mode 100644
index 000000000000..4ef1c1edc5f7
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_kernel_tensor_0_regs.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_TPC0_CFG_KERNEL_TENSOR_0_REGS_H_
+#define ASIC_REG_DCORE0_TPC0_CFG_KERNEL_TENSOR_0_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_TPC0_CFG_KERNEL_TENSOR_0
+ *   (Prototype: TPC_TENSOR)
+ *****************************************
+ */
+
+#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0x400B000
+
+#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0x400B004
+
+#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0x400B008
+
+#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0x400B00C
+
+#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0x400B010
+
+#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0x400B014
+
+#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0x400B018
+
+#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0x400B01C
+
+#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0x400B020
+
+#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0x400B024
+
+#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0x400B028
+
+#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0x400B02C
+
+#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0x400B030
+
+#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0x400B034
+
+#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_PREF_STRIDE 0x400B038
+
+#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_STRIDE_HIGH 0x400B03C
+
+#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_STRIDE_HIGH 0x400B040
+
+#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_STRIDE_HIGH 0x400B044
+
+#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_STRIDE_HIGH 0x400B048
+
+#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_STRIDE_HIGH 0x400B04C
+
+#endif /* ASIC_REG_DCORE0_TPC0_CFG_KERNEL_TENSOR_0_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_masks.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_masks.h
new file mode 100644
index 000000000000..cdecbd0f9d84
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_masks.h
@@ -0,0 +1,509 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_TPC0_CFG_MASKS_H_
+#define ASIC_REG_DCORE0_TPC0_CFG_MASKS_H_
+
+/*
+ *****************************************
+ *   DCORE0_TPC0_CFG
+ *   (Prototype: TPC)
+ *****************************************
+ */
+
+/* DCORE0_TPC0_CFG_TPC_COUNT */
+#define DCORE0_TPC0_CFG_TPC_COUNT_V_SHIFT 0
+#define DCORE0_TPC0_CFG_TPC_COUNT_V_MASK 0xFFFFFFFF
+
+/* DCORE0_TPC0_CFG_TPC_ID */
+#define DCORE0_TPC0_CFG_TPC_ID_V_SHIFT 0
+#define DCORE0_TPC0_CFG_TPC_ID_V_MASK 0xFFFFFFFF
+
+/* DCORE0_TPC0_CFG_STALL_ON_ERR */
+#define DCORE0_TPC0_CFG_STALL_ON_ERR_V_SHIFT 0
+#define DCORE0_TPC0_CFG_STALL_ON_ERR_V_MASK 0x1
+
+/* DCORE0_TPC0_CFG_CLK_EN */
+#define DCORE0_TPC0_CFG_CLK_EN_LBW_CFG_DIS_SHIFT 0
+#define DCORE0_TPC0_CFG_CLK_EN_LBW_CFG_DIS_MASK 0x1
+#define DCORE0_TPC0_CFG_CLK_EN_DBG_CFG_DIS_SHIFT 4
+#define DCORE0_TPC0_CFG_CLK_EN_DBG_CFG_DIS_MASK 0x10
+
+/* DCORE0_TPC0_CFG_IQ_RL_EN */
+#define DCORE0_TPC0_CFG_IQ_RL_EN_V_SHIFT 0
+#define DCORE0_TPC0_CFG_IQ_RL_EN_V_MASK 0x1
+
+/* DCORE0_TPC0_CFG_IQ_RL_SAT */
+#define DCORE0_TPC0_CFG_IQ_RL_SAT_V_SHIFT 0
+#define DCORE0_TPC0_CFG_IQ_RL_SAT_V_MASK 0xFF
+
+/* DCORE0_TPC0_CFG_IQ_RL_RST_TOKEN */
+#define DCORE0_TPC0_CFG_IQ_RL_RST_TOKEN_V_SHIFT 0
+#define DCORE0_TPC0_CFG_IQ_RL_RST_TOKEN_V_MASK 0xFF
+
+/* DCORE0_TPC0_CFG_IQ_RL_TIMEOUT */
+#define DCORE0_TPC0_CFG_IQ_RL_TIMEOUT_V_SHIFT 0
+#define DCORE0_TPC0_CFG_IQ_RL_TIMEOUT_V_MASK 0xFF
+
+/* DCORE0_TPC0_CFG_TSB_CFG_MTRR_2 */
+#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_2_PHY_BASE_ADD_LO_SHIFT 0
+#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_2_PHY_BASE_ADD_LO_MASK 0xFFFFFF
+
+/* DCORE0_TPC0_CFG_IQ_LBW_CLK_EN */
+#define DCORE0_TPC0_CFG_IQ_LBW_CLK_EN_V_SHIFT 0
+#define DCORE0_TPC0_CFG_IQ_LBW_CLK_EN_V_MASK 0x1
+
+/* DCORE0_TPC0_CFG_TPC_LOCK_VALUE */
+#define DCORE0_TPC0_CFG_TPC_LOCK_VALUE_VALUE_SHIFT 0
+#define DCORE0_TPC0_CFG_TPC_LOCK_VALUE_VALUE_MASK 0xFFFFFFFF
+
+/* DCORE0_TPC0_CFG_TPC_LOCK */
+#define DCORE0_TPC0_CFG_TPC_LOCK_LOCK_SHIFT 0
+#define DCORE0_TPC0_CFG_TPC_LOCK_LOCK_MASK 0x1
+
+/* DCORE0_TPC0_CFG_CGU_SB */
+#define DCORE0_TPC0_CFG_CGU_SB_TSB_DISABLE_SHIFT 0
+#define DCORE0_TPC0_CFG_CGU_SB_TSB_DISABLE_MASK 0x1
+
+/* DCORE0_TPC0_CFG_CGU_CNT */
+#define DCORE0_TPC0_CFG_CGU_CNT_DCACHE_DISABLE_SHIFT 0
+#define DCORE0_TPC0_CFG_CGU_CNT_DCACHE_DISABLE_MASK 0x1
+#define DCORE0_TPC0_CFG_CGU_CNT_WQ_DISABLE_SHIFT 1
+#define DCORE0_TPC0_CFG_CGU_CNT_WQ_DISABLE_MASK 0x2
+#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_0_DISABLE_SHIFT 2
+#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_0_DISABLE_MASK 0x4
+#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_1_DISABLE_SHIFT 3
+#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_1_DISABLE_MASK 0x8
+#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_2_DISABLE_SHIFT 4
+#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_2_DISABLE_MASK 0x10
+#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_3_DISABLE_SHIFT 5
+#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_3_DISABLE_MASK 0x20
+#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_4_DISABLE_SHIFT 6
+#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_4_DISABLE_MASK 0x40
+#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_0_DISABLE_SHIFT 7
+#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_0_DISABLE_MASK 0x80
+#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_1_DISABLE_SHIFT 8
+#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_1_DISABLE_MASK 0x100
+#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_2_DISABLE_SHIFT 9
+#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_2_DISABLE_MASK 0x200
+#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_3_DISABLE_SHIFT 10
+#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_3_DISABLE_MASK 0x400
+#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_4_DISABLE_SHIFT 11
+#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_4_DISABLE_MASK 0x800
+#define DCORE0_TPC0_CFG_CGU_CNT_MSAC_DISABLE_SHIFT 12
+#define DCORE0_TPC0_CFG_CGU_CNT_MSAC_DISABLE_MASK 0x1000
+#define DCORE0_TPC0_CFG_CGU_CNT_CONV_DISABLE_SHIFT 13
+#define DCORE0_TPC0_CFG_CGU_CNT_CONV_DISABLE_MASK 0x2000
+#define DCORE0_TPC0_CFG_CGU_CNT_NEARBYINT_DISABLE_SHIFT 14
+#define DCORE0_TPC0_CFG_CGU_CNT_NEARBYINT_DISABLE_MASK 0x4000
+#define DCORE0_TPC0_CFG_CGU_CNT_CMP_DISABLE_SHIFT 15
+#define DCORE0_TPC0_CFG_CGU_CNT_CMP_DISABLE_MASK 0x8000
+#define DCORE0_TPC0_CFG_CGU_CNT_FP_MAC_DISABLE_SHIFT 16
+#define DCORE0_TPC0_CFG_CGU_CNT_FP_MAC_DISABLE_MASK 0x10000
+#define DCORE0_TPC0_CFG_CGU_CNT_SOPS_SRC_A_D2_DISABLE_SHIFT 17
+#define DCORE0_TPC0_CFG_CGU_CNT_SOPS_SRC_A_D2_DISABLE_MASK 0x20000
+#define DCORE0_TPC0_CFG_CGU_CNT_SOPS_SRC_B_D2_DISABLE_SHIFT 18
+#define DCORE0_TPC0_CFG_CGU_CNT_SOPS_SRC_B_D2_DISABLE_MASK 0x40000
+#define DCORE0_TPC0_CFG_CGU_CNT_SOPS_SRC_E_D2_DISABLE_SHIFT 19
+#define DCORE0_TPC0_CFG_CGU_CNT_SOPS_SRC_E_D2_DISABLE_MASK 0x80000
+#define DCORE0_TPC0_CFG_CGU_CNT_SOPS_FMA_SRC_C_E1_DISABLE_SHIFT 20
+#define DCORE0_TPC0_CFG_CGU_CNT_SOPS_FMA_SRC_C_E1_DISABLE_MASK 0x100000
+#define DCORE0_TPC0_CFG_CGU_CNT_LD_SOPS_SRC_A_D2_DISABLE_SHIFT 21
+#define DCORE0_TPC0_CFG_CGU_CNT_LD_SOPS_SRC_A_D2_DISABLE_MASK 0x200000
+#define DCORE0_TPC0_CFG_CGU_CNT_ST_SOPS_SRC_A_D2_DISABLE_SHIFT 22
+#define DCORE0_TPC0_CFG_CGU_CNT_ST_SOPS_SRC_A_D2_DISABLE_MASK 0x400000
+#define DCORE0_TPC0_CFG_CGU_CNT_FP_ADDSUB_DISABLE_SHIFT 23
+#define DCORE0_TPC0_CFG_CGU_CNT_FP_ADDSUB_DISABLE_MASK 0x800000
+
+/* DCORE0_TPC0_CFG_CGU_CPE */
+#define DCORE0_TPC0_CFG_CGU_CPE_NEARBYINT_DISABLE_SHIFT 0
+#define DCORE0_TPC0_CFG_CGU_CPE_NEARBYINT_DISABLE_MASK 0x1
+#define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_A_DISABLE_SHIFT 1
+#define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_A_DISABLE_MASK 0x2
+#define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_B_DISABLE_SHIFT 2
+#define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_B_DISABLE_MASK 0x4
+#define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_E_DISABLE_SHIFT 3
+#define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_E_DISABLE_MASK 0x8
+#define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_D_DISABLE_SHIFT 4
+#define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_D_DISABLE_MASK 0x10
+#define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_C_DISABLE_SHIFT 5
+#define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_C_DISABLE_MASK 0x20
+#define DCORE0_TPC0_CFG_CGU_CPE_LD_SOPS_SRC_A_DISABLE_SHIFT 6
+#define DCORE0_TPC0_CFG_CGU_CPE_LD_SOPS_SRC_A_DISABLE_MASK 0x40
+#define DCORE0_TPC0_CFG_CGU_CPE_MSAC_DISABLE_SHIFT 7
+#define DCORE0_TPC0_CFG_CGU_CPE_MSAC_DISABLE_MASK 0x80
+#define DCORE0_TPC0_CFG_CGU_CPE_ADDSUB_DISABLE_SHIFT 8
+#define DCORE0_TPC0_CFG_CGU_CPE_ADDSUB_DISABLE_MASK 0x100
+#define DCORE0_TPC0_CFG_CGU_CPE_SHIFT_DISABLE_SHIFT 9
+#define DCORE0_TPC0_CFG_CGU_CPE_SHIFT_DISABLE_MASK 0x200
+#define DCORE0_TPC0_CFG_CGU_CPE_GLE_DISABLE_SHIFT 10
+#define DCORE0_TPC0_CFG_CGU_CPE_GLE_DISABLE_MASK 0x400
+#define DCORE0_TPC0_CFG_CGU_CPE_CMP_DISABLE_SHIFT 11
+#define DCORE0_TPC0_CFG_CGU_CPE_CMP_DISABLE_MASK 0x800
+#define DCORE0_TPC0_CFG_CGU_CPE_CONV_DISABLE_SHIFT 12
+#define DCORE0_TPC0_CFG_CGU_CPE_CONV_DISABLE_MASK 0x1000
+#define DCORE0_TPC0_CFG_CGU_CPE_SB_DISABLE_SHIFT 13
+#define DCORE0_TPC0_CFG_CGU_CPE_SB_DISABLE_MASK 0x2000
+#define DCORE0_TPC0_CFG_CGU_CPE_TBUF_DISABLE_SHIFT 14
+#define DCORE0_TPC0_CFG_CGU_CPE_TBUF_DISABLE_MASK 0x4000
+#define DCORE0_TPC0_CFG_CGU_CPE_ST_G_DISABLE_SHIFT 15
+#define DCORE0_TPC0_CFG_CGU_CPE_ST_G_DISABLE_MASK 0x8000
+#define DCORE0_TPC0_CFG_CGU_CPE_FP_MAC_0_DISABLE_SHIFT 16
+#define DCORE0_TPC0_CFG_CGU_CPE_FP_MAC_0_DISABLE_MASK 0x10000
+#define DCORE0_TPC0_CFG_CGU_CPE_FP_MAC_1_DISABLE_SHIFT 17
+#define DCORE0_TPC0_CFG_CGU_CPE_FP_MAC_1_DISABLE_MASK 0x20000
+#define DCORE0_TPC0_CFG_CGU_CPE_FP_ADDSUB_DISABLE_SHIFT 18
+#define DCORE0_TPC0_CFG_CGU_CPE_FP_ADDSUB_DISABLE_MASK 0x40000
+#define DCORE0_TPC0_CFG_CGU_CPE_ST_SOPS_SRC_C_DISABLE_SHIFT 19
+#define DCORE0_TPC0_CFG_CGU_CPE_ST_SOPS_SRC_C_DISABLE_MASK 0x80000
+
+/* DCORE0_TPC0_CFG_FP16_FTZ_IN */
+#define DCORE0_TPC0_CFG_FP16_FTZ_IN_MODE_SHIFT 0
+#define DCORE0_TPC0_CFG_FP16_FTZ_IN_MODE_MASK 0x1
+
+/* DCORE0_TPC0_CFG_DCACHE_CFG */
+#define DCORE0_TPC0_CFG_DCACHE_CFG_G_PREF_DIS_SHIFT 0
+#define DCORE0_TPC0_CFG_DCACHE_CFG_G_PREF_DIS_MASK 0x1
+#define DCORE0_TPC0_CFG_DCACHE_CFG_G_PREF_VLD_CLR_SHIFT 1
+#define DCORE0_TPC0_CFG_DCACHE_CFG_G_PREF_VLD_CLR_MASK 0x2
+#define DCORE0_TPC0_CFG_DCACHE_CFG_HALT_FLUSH_SHIFT 2
+#define DCORE0_TPC0_CFG_DCACHE_CFG_HALT_FLUSH_MASK 0x4
+#define DCORE0_TPC0_CFG_DCACHE_CFG_DEALIGN_DIS_SHIFT 3
+#define DCORE0_TPC0_CFG_DCACHE_CFG_DEALIGN_DIS_MASK 0x8
+
+/* DCORE0_TPC0_CFG_E2E_CRDT_TOP */
+#define DCORE0_TPC0_CFG_E2E_CRDT_TOP_FORCE_EN_SHIFT 0
+#define DCORE0_TPC0_CFG_E2E_CRDT_TOP_FORCE_EN_MASK 0x1
+#define DCORE0_TPC0_CFG_E2E_CRDT_TOP_Y_X_FORCE_SHIFT 4
+#define DCORE0_TPC0_CFG_E2E_CRDT_TOP_Y_X_FORCE_MASK 0x1FF0
+
+/* DCORE0_TPC0_CFG_TPC_DCACHE_L0CD */
+#define DCORE0_TPC0_CFG_TPC_DCACHE_L0CD_VAL_SHIFT 0
+#define DCORE0_TPC0_CFG_TPC_DCACHE_L0CD_VAL_MASK 0x1
+
+/* DCORE0_TPC0_CFG_TPC_SB_L0CD */
+#define DCORE0_TPC0_CFG_TPC_SB_L0CD_VAL_SHIFT 0
+#define DCORE0_TPC0_CFG_TPC_SB_L0CD_VAL_MASK 0x1
+
+/* DCORE0_TPC0_CFG_CONV_ROUND_CSR */
+#define DCORE0_TPC0_CFG_CONV_ROUND_CSR_MODE_SHIFT 0
+#define DCORE0_TPC0_CFG_CONV_ROUND_CSR_MODE_MASK 0x7
+
+/* DCORE0_TPC0_CFG_TSB_OCCUPANCY */
+#define DCORE0_TPC0_CFG_TSB_OCCUPANCY_V_SHIFT 0
+#define DCORE0_TPC0_CFG_TSB_OCCUPANCY_V_MASK 0xFFFFFFFF
+
+/* DCORE0_TPC0_CFG_ARB_QNT_HBW_WEIGHT */
+#define DCORE0_TPC0_CFG_ARB_QNT_HBW_WEIGHT_AR_SHIFT 0
+#define DCORE0_TPC0_CFG_ARB_QNT_HBW_WEIGHT_AR_MASK 0xFFF
+#define DCORE0_TPC0_CFG_ARB_QNT_HBW_WEIGHT_AW_SHIFT 12
+#define DCORE0_TPC0_CFG_ARB_QNT_HBW_WEIGHT_AW_MASK 0xFF000
+
+/* DCORE0_TPC0_CFG_ARB_QNT_LBW_WEIGHT */
+#define DCORE0_TPC0_CFG_ARB_QNT_LBW_WEIGHT_AW_SHIFT 0
+#define DCORE0_TPC0_CFG_ARB_QNT_LBW_WEIGHT_AW_MASK 0xFF
+#define DCORE0_TPC0_CFG_ARB_QNT_LBW_WEIGHT_AR_SHIFT 8
+#define DCORE0_TPC0_CFG_ARB_QNT_LBW_WEIGHT_AR_MASK 0xFF00
+
+/* DCORE0_TPC0_CFG_ARB_CNT_HBW_WEIGHT */
+#define DCORE0_TPC0_CFG_ARB_CNT_HBW_WEIGHT_AR_SHIFT 0
+#define DCORE0_TPC0_CFG_ARB_CNT_HBW_WEIGHT_AR_MASK 0xFFF
+#define DCORE0_TPC0_CFG_ARB_CNT_HBW_WEIGHT_AW_SHIFT 12
+#define DCORE0_TPC0_CFG_ARB_CNT_HBW_WEIGHT_AW_MASK 0xFFF000
+
+/* DCORE0_TPC0_CFG_ARB_CNT_LBW_WEIGHT */
+#define DCORE0_TPC0_CFG_ARB_CNT_LBW_WEIGHT_AR_SHIFT 0
+#define DCORE0_TPC0_CFG_ARB_CNT_LBW_WEIGHT_AR_MASK 0xFF
+#define DCORE0_TPC0_CFG_ARB_CNT_LBW_WEIGHT_AW_SHIFT 8
+#define DCORE0_TPC0_CFG_ARB_CNT_LBW_WEIGHT_AW_MASK 0xFFF00
+
+/* DCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_LO */
+#define DCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_LO_V_SHIFT 0
+#define DCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_LO_V_MASK 0xFFFFFFFF
+
+/* DCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_HI */
+#define DCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_HI_V_SHIFT 0
+#define DCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_HI_V_MASK 0xFFFFFFFF
+
+/* DCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_LO */
+#define DCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_LO_V_SHIFT 0
+#define DCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_LO_V_MASK 0xFFFFFFFF
+
+/* DCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_HI */
+#define DCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_HI_V_SHIFT 0
+#define DCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_HI_V_MASK 0xFFFFFFFF
+
+/* DCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_LO */
+#define DCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_LO_V_SHIFT 0
+#define DCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_LO_V_MASK 0xFFFFFFFF
+
+/* DCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_HI */
+#define DCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_HI_V_SHIFT 0
+#define DCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_HI_V_MASK 0xFFFFFFFF
+
+/* DCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_LO */
+#define DCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_LO_V_SHIFT 0
+#define DCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_LO_V_MASK 0xFFFFFFFF
+
+/* DCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_HI */
+#define DCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_HI_V_SHIFT 0
+#define DCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_HI_V_MASK 0xFFFFFFFF
+
+/* DCORE0_TPC0_CFG_SPE_LFSR_POLYNOM */
+#define DCORE0_TPC0_CFG_SPE_LFSR_POLYNOM_V_SHIFT 0
+#define DCORE0_TPC0_CFG_SPE_LFSR_POLYNOM_V_MASK 0xFFFFFFFF
+
+/* DCORE0_TPC0_CFG_TSB_CFG_MTRR_GLBL */
+#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_GLBL_EN_SHIFT 0
+#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_GLBL_EN_MASK 0x1
+#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_GLBL_DEFAULT_MEMORY_TYPE_SHIFT 4
+#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_GLBL_DEFAULT_MEMORY_TYPE_MASK 0x10
+
+/* DCORE0_TPC0_CFG_TSB_CFG_MTRR */
+#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_VALID_SHIFT 0
+#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_VALID_MASK 0x1
+#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_MEMORY_TYPE_SHIFT 4
+#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_MEMORY_TYPE_MASK 0x10
+#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_PHY_BASE_ADD_SHIFT 8
+#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_PHY_BASE_ADD_MASK 0xFFFF00
+
+/* DCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO */
+#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO_V_SHIFT 0
+#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO_V_MASK 0xFFFFFFFF
+
+/* DCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI */
+#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI_V_SHIFT 0
+#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI_V_MASK 0xFF
+
+/* DCORE0_TPC0_CFG_FP8_143_BIAS */
+#define DCORE0_TPC0_CFG_FP8_143_BIAS_BIAS_143_SHIFT 0
+#define DCORE0_TPC0_CFG_FP8_143_BIAS_BIAS_143_MASK 0xF
+
+/* DCORE0_TPC0_CFG_ROUND_CSR */
+#define DCORE0_TPC0_CFG_ROUND_CSR_MODE_SHIFT 0
+#define DCORE0_TPC0_CFG_ROUND_CSR_MODE_MASK 0x7
+
+/* DCORE0_TPC0_CFG_HB_PROT */
+#define DCORE0_TPC0_CFG_HB_PROT_AWPROT_SHIFT 0
+#define DCORE0_TPC0_CFG_HB_PROT_AWPROT_MASK 0x7
+#define DCORE0_TPC0_CFG_HB_PROT_ARPROT_SHIFT 3
+#define DCORE0_TPC0_CFG_HB_PROT_ARPROT_MASK 0x38
+
+/* DCORE0_TPC0_CFG_LB_PROT */
+#define DCORE0_TPC0_CFG_LB_PROT_AWPROT_SHIFT 0
+#define DCORE0_TPC0_CFG_LB_PROT_AWPROT_MASK 0x7
+#define DCORE0_TPC0_CFG_LB_PROT_ARPROT_SHIFT 3
+#define DCORE0_TPC0_CFG_LB_PROT_ARPROT_MASK 0x38
+
+/* DCORE0_TPC0_CFG_SEMAPHORE */
+#define DCORE0_TPC0_CFG_SEMAPHORE_V_SHIFT 0
+#define DCORE0_TPC0_CFG_SEMAPHORE_V_MASK 0xFFFFFFFF
+
+/* DCORE0_TPC0_CFG_VFLAGS */
+#define DCORE0_TPC0_CFG_VFLAGS_V_SHIFT 0
+#define DCORE0_TPC0_CFG_VFLAGS_V_MASK 0x7F
+
+/* DCORE0_TPC0_CFG_SFLAGS */
+#define DCORE0_TPC0_CFG_SFLAGS_V_SHIFT 0
+#define DCORE0_TPC0_CFG_SFLAGS_V_MASK 0x7F
+
+/* DCORE0_TPC0_CFG_LFSR_POLYNOM */
+#define DCORE0_TPC0_CFG_LFSR_POLYNOM_V_SHIFT 0
+#define DCORE0_TPC0_CFG_LFSR_POLYNOM_V_MASK 0xFFFFFFFF
+
+/* DCORE0_TPC0_CFG_STATUS */
+#define DCORE0_TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_SHIFT 1
+#define DCORE0_TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_MASK 0x2
+#define DCORE0_TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_SHIFT 2
+#define DCORE0_TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK 0x4
+#define DCORE0_TPC0_CFG_STATUS_IQ_EMPTY_SHIFT 3
+#define DCORE0_TPC0_CFG_STATUS_IQ_EMPTY_MASK 0x8
+#define DCORE0_TPC0_CFG_STATUS_SB_EMPTY_SHIFT 5
+#define DCORE0_TPC0_CFG_STATUS_SB_EMPTY_MASK 0x20
+#define DCORE0_TPC0_CFG_STATUS_QM_IDLE_SHIFT 6
+#define DCORE0_TPC0_CFG_STATUS_QM_IDLE_MASK 0x40
+#define DCORE0_TPC0_CFG_STATUS_QM_RDY_SHIFT 7
+#define DCORE0_TPC0_CFG_STATUS_QM_RDY_MASK 0x80
+
+/* DCORE0_TPC0_CFG_CFG_BASE_ADDRESS_HIGH */
+#define DCORE0_TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_SHIFT 0
+#define DCORE0_TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF
+
+/* DCORE0_TPC0_CFG_CFG_SUBTRACT_VALUE */
+#define DCORE0_TPC0_CFG_CFG_SUBTRACT_VALUE_V_SHIFT 0
+#define DCORE0_TPC0_CFG_CFG_SUBTRACT_VALUE_V_MASK 0xFFFFFFFF
+
+/* DCORE0_TPC0_CFG_SM_BASE_ADDRESS_HIGH */
+#define DCORE0_TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_SHIFT 0
+#define DCORE0_TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF
+
+/* DCORE0_TPC0_CFG_TPC_CMD */
+#define DCORE0_TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_SHIFT 0
+#define DCORE0_TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_MASK 0x1
+#define DCORE0_TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_SHIFT 1
+#define DCORE0_TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_MASK 0x2
+#define DCORE0_TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_SHIFT 2
+#define DCORE0_TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_MASK 0x4
+#define DCORE0_TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_SHIFT 3
+#define DCORE0_TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_MASK 0x8
+#define DCORE0_TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_SHIFT 4
+#define DCORE0_TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_MASK 0x10
+#define DCORE0_TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_SHIFT 5
+#define DCORE0_TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_MASK 0x20
+#define DCORE0_TPC0_CFG_TPC_CMD_QMAN_STOP_SHIFT 6
+#define DCORE0_TPC0_CFG_TPC_CMD_QMAN_STOP_MASK 0x40
+
+/* DCORE0_TPC0_CFG_TPC_EXECUTE */
+#define DCORE0_TPC0_CFG_TPC_EXECUTE_V_SHIFT 0
+#define DCORE0_TPC0_CFG_TPC_EXECUTE_V_MASK 0x1
+
+/* DCORE0_TPC0_CFG_TPC_STALL */
+#define DCORE0_TPC0_CFG_TPC_STALL_V_SHIFT 0
+#define DCORE0_TPC0_CFG_TPC_STALL_V_MASK 0x1
+
+/* DCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_LOW */
+#define DCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_SHIFT 0
+#define DCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_MASK 0xFFFFFFFF
+
+/* DCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH */
+#define DCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_SHIFT 0
+#define DCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_MASK 0xFFFFFFFF
+
+/* DCORE0_TPC0_CFG_RD_RATE_LIMIT */
+#define DCORE0_TPC0_CFG_RD_RATE_LIMIT_ENABLE_SHIFT 0
+#define DCORE0_TPC0_CFG_RD_RATE_LIMIT_ENABLE_MASK 0x1
+#define DCORE0_TPC0_CFG_RD_RATE_LIMIT_SATURATION_SHIFT 1
+#define DCORE0_TPC0_CFG_RD_RATE_LIMIT_SATURATION_MASK 0x1FE
+#define DCORE0_TPC0_CFG_RD_RATE_LIMIT_TIMEOUT_SHIFT 9
+#define DCORE0_TPC0_CFG_RD_RATE_LIMIT_TIMEOUT_MASK 0x1FE00
+
+/* DCORE0_TPC0_CFG_WR_RATE_LIMIT */
+#define DCORE0_TPC0_CFG_WR_RATE_LIMIT_ENABLE_SHIFT 0
+#define DCORE0_TPC0_CFG_WR_RATE_LIMIT_ENABLE_MASK 0x1
+#define DCORE0_TPC0_CFG_WR_RATE_LIMIT_SATURATION_SHIFT 1
+#define DCORE0_TPC0_CFG_WR_RATE_LIMIT_SATURATION_MASK 0x1FE
+#define DCORE0_TPC0_CFG_WR_RATE_LIMIT_TIMEOUT_SHIFT 9
+#define DCORE0_TPC0_CFG_WR_RATE_LIMIT_TIMEOUT_MASK 0x1FE00
+
+/* DCORE0_TPC0_CFG_MSS_CONFIG */
+#define DCORE0_TPC0_CFG_MSS_CONFIG_AWCACHE_SHIFT 0
+#define DCORE0_TPC0_CFG_MSS_CONFIG_AWCACHE_MASK 0xF
+#define DCORE0_TPC0_CFG_MSS_CONFIG_ARCACHE_SHIFT 4
+#define DCORE0_TPC0_CFG_MSS_CONFIG_ARCACHE_MASK 0xF0
+#define DCORE0_TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_SHIFT 8
+#define DCORE0_TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_MASK 0x300
+#define DCORE0_TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_SHIFT 10
+#define DCORE0_TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_MASK 0x400
+#define DCORE0_TPC0_CFG_MSS_CONFIG_DCACHE_PREFETCH_DIS_SHIFT 11
+#define DCORE0_TPC0_CFG_MSS_CONFIG_DCACHE_PREFETCH_DIS_MASK 0x800
+
+/* DCORE0_TPC0_CFG_TPC_INTR_CAUSE */
+#define DCORE0_TPC0_CFG_TPC_INTR_CAUSE_CAUSE_SHIFT 0
+#define DCORE0_TPC0_CFG_TPC_INTR_CAUSE_CAUSE_MASK 0xFFFFFFFF
+
+/* DCORE0_TPC0_CFG_TPC_INTR_MASK */
+#define DCORE0_TPC0_CFG_TPC_INTR_MASK_MASK_SHIFT 0
+#define DCORE0_TPC0_CFG_TPC_INTR_MASK_MASK_MASK 0xFFFFFFFF
+
+/* DCORE0_TPC0_CFG_WQ_CREDITS */
+#define DCORE0_TPC0_CFG_WQ_CREDITS_ST_G_SHIFT 0
+#define DCORE0_TPC0_CFG_WQ_CREDITS_ST_G_MASK 0xF
+#define DCORE0_TPC0_CFG_WQ_CREDITS_KERNEL_FIFO_SHIFT 4
+#define DCORE0_TPC0_CFG_WQ_CREDITS_KERNEL_FIFO_MASK 0x70
+
+/* DCORE0_TPC0_CFG_OPCODE_EXEC */
+#define DCORE0_TPC0_CFG_OPCODE_EXEC_SPU_OP_SHIFT 0
+#define DCORE0_TPC0_CFG_OPCODE_EXEC_SPU_OP_MASK 0x7F
+#define DCORE0_TPC0_CFG_OPCODE_EXEC_SPU_EN_SHIFT 7
+#define DCORE0_TPC0_CFG_OPCODE_EXEC_SPU_EN_MASK 0x80
+#define DCORE0_TPC0_CFG_OPCODE_EXEC_VPU_OP_SHIFT 8
+#define DCORE0_TPC0_CFG_OPCODE_EXEC_VPU_OP_MASK 0x7F00
+#define DCORE0_TPC0_CFG_OPCODE_EXEC_VPU_EN_SHIFT 15
+#define DCORE0_TPC0_CFG_OPCODE_EXEC_VPU_EN_MASK 0x8000
+#define DCORE0_TPC0_CFG_OPCODE_EXEC_LD_OP_SHIFT 16
+#define DCORE0_TPC0_CFG_OPCODE_EXEC_LD_OP_MASK 0x7F0000
+#define DCORE0_TPC0_CFG_OPCODE_EXEC_LD_EN_SHIFT 23
+#define DCORE0_TPC0_CFG_OPCODE_EXEC_LD_EN_MASK 0x800000
+#define DCORE0_TPC0_CFG_OPCODE_EXEC_ST_OP_SHIFT 24
+#define DCORE0_TPC0_CFG_OPCODE_EXEC_ST_OP_MASK 0x7F000000
+#define DCORE0_TPC0_CFG_OPCODE_EXEC_ST_EN_SHIFT 31
+#define DCORE0_TPC0_CFG_OPCODE_EXEC_ST_EN_MASK 0x80000000
+
+/* DCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO */
+#define DCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO_V_SHIFT 0
+#define DCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO_V_MASK 0xFFFFFFFF
+
+/* DCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI */
+#define DCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI_V_SHIFT 0
+#define DCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI_V_MASK 0xFFFFFFFF
+
+/* DCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO */
+#define DCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO_V_SHIFT 0
+#define DCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO_V_MASK 0xFFFFFFFF
+
+/* DCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI */
+#define DCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI_V_SHIFT 0
+#define DCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI_V_MASK 0xFFFFFFFF
+
+/* DCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO */
+#define DCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO_V_SHIFT 0
+#define DCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO_V_MASK 0xFFFFFFFF
+
+/* DCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI */
+#define DCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI_V_SHIFT 0
+#define DCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI_V_MASK 0xFFFFFFFF
+
+/* DCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO */
+#define DCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO_V_SHIFT 0
+#define DCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO_V_MASK 0xFFFFFFFF
+
+/* DCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI */
+#define DCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI_V_SHIFT 0
+#define DCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI_V_MASK 0xFFFFFFFF
+
+/* DCORE0_TPC0_CFG_TSB_CFG_MAX_SIZE */
+#define DCORE0_TPC0_CFG_TSB_CFG_MAX_SIZE_DATA_SHIFT 0
+#define DCORE0_TPC0_CFG_TSB_CFG_MAX_SIZE_DATA_MASK 0xFFFF
+#define DCORE0_TPC0_CFG_TSB_CFG_MAX_SIZE_MD_SHIFT 16
+#define DCORE0_TPC0_CFG_TSB_CFG_MAX_SIZE_MD_MASK 0xFFFF0000
+
+/* DCORE0_TPC0_CFG_TSB_CFG */
+#define DCORE0_TPC0_CFG_TSB_CFG_CACHE_DISABLE_SHIFT 0
+#define DCORE0_TPC0_CFG_TSB_CFG_CACHE_DISABLE_MASK 0x1
+#define DCORE0_TPC0_CFG_TSB_CFG_MAX_OS_SHIFT 1
+#define DCORE0_TPC0_CFG_TSB_CFG_MAX_OS_MASK 0x1FFFE
+#define DCORE0_TPC0_CFG_TSB_CFG_ENABLE_CGATE_SHIFT 17
+#define DCORE0_TPC0_CFG_TSB_CFG_ENABLE_CGATE_MASK 0x20000
+
+/* DCORE0_TPC0_CFG_TSB_INFLIGHT_CNTR */
+#define DCORE0_TPC0_CFG_TSB_INFLIGHT_CNTR_V_SHIFT 0
+#define DCORE0_TPC0_CFG_TSB_INFLIGHT_CNTR_V_MASK 0xFFFFFFFF
+
+/* DCORE0_TPC0_CFG_WQ_INFLIGHT_CNTR */
+#define DCORE0_TPC0_CFG_WQ_INFLIGHT_CNTR_HBW_SHIFT 0
+#define DCORE0_TPC0_CFG_WQ_INFLIGHT_CNTR_HBW_MASK 0xFFFF
+#define DCORE0_TPC0_CFG_WQ_INFLIGHT_CNTR_LBW_SHIFT 16
+#define DCORE0_TPC0_CFG_WQ_INFLIGHT_CNTR_LBW_MASK 0x1FF0000
+
+/* DCORE0_TPC0_CFG_WQ_LBW_TOTAL_CNTR */
+#define DCORE0_TPC0_CFG_WQ_LBW_TOTAL_CNTR_V_SHIFT 0
+#define DCORE0_TPC0_CFG_WQ_LBW_TOTAL_CNTR_V_MASK 0xFFFFFFFF
+
+/* DCORE0_TPC0_CFG_WQ_HBW_TOTAL_CNTR */
+#define DCORE0_TPC0_CFG_WQ_HBW_TOTAL_CNTR_V_SHIFT 0
+#define DCORE0_TPC0_CFG_WQ_HBW_TOTAL_CNTR_V_MASK 0xFFFFFFFF
+
+/* DCORE0_TPC0_CFG_IRQ_OCCOUPY_CNTR */
+#define DCORE0_TPC0_CFG_IRQ_OCCOUPY_CNTR_V_SHIFT 0
+#define DCORE0_TPC0_CFG_IRQ_OCCOUPY_CNTR_V_MASK 0xFFFFFFFF
+
+#endif /* ASIC_REG_DCORE0_TPC0_CFG_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_regs.h
new file mode 100644
index 000000000000..4cd9e26a150f
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_regs.h
@@ -0,0 +1,129 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_TPC0_CFG_QM_REGS_H_
+#define ASIC_REG_DCORE0_TPC0_CFG_QM_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_TPC0_CFG_QM
+ *   (Prototype: TPC_NON_TENSOR_DESCRIPTOR)
+ *****************************************
+ */
+
+#define mmDCORE0_TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0x400BAE4
+
+#define mmDCORE0_TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0x400BAE8
+
+#define mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_0 0x400BAEC
+
+#define mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_0 0x400BAF0
+
+#define mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_1 0x400BAF4
+
+#define mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_1 0x400BAF8
+
+#define mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_2 0x400BAFC
+
+#define mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_2 0x400BB00
+
+#define mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_3 0x400BB04
+
+#define mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_3 0x400BB08
+
+#define mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_4 0x400BB0C
+
+#define mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_4 0x400BB10
+
+#define mmDCORE0_TPC0_CFG_QM_KERNEL_CONFIG 0x400BB14
+
+#define mmDCORE0_TPC0_CFG_QM_KERNEL_ID 0x400BB18
+
+#define mmDCORE0_TPC0_CFG_QM_POWER_LOOP 0x400BB1C
+
+#define mmDCORE0_TPC0_CFG_QM_SRF_0 0x400BB20
+
+#define mmDCORE0_TPC0_CFG_QM_SRF_1 0x400BB24
+
+#define mmDCORE0_TPC0_CFG_QM_SRF_2 0x400BB28
+
+#define mmDCORE0_TPC0_CFG_QM_SRF_3 0x400BB2C
+
+#define mmDCORE0_TPC0_CFG_QM_SRF_4 0x400BB30
+
+#define mmDCORE0_TPC0_CFG_QM_SRF_5 0x400BB34
+
+#define mmDCORE0_TPC0_CFG_QM_SRF_6 0x400BB38
+
+#define mmDCORE0_TPC0_CFG_QM_SRF_7 0x400BB3C
+
+#define mmDCORE0_TPC0_CFG_QM_SRF_8 0x400BB40
+
+#define mmDCORE0_TPC0_CFG_QM_SRF_9 0x400BB44
+
+#define mmDCORE0_TPC0_CFG_QM_SRF_10 0x400BB48
+
+#define mmDCORE0_TPC0_CFG_QM_SRF_11 0x400BB4C
+
+#define mmDCORE0_TPC0_CFG_QM_SRF_12 0x400BB50
+
+#define mmDCORE0_TPC0_CFG_QM_SRF_13 0x400BB54
+
+#define mmDCORE0_TPC0_CFG_QM_SRF_14 0x400BB58
+
+#define mmDCORE0_TPC0_CFG_QM_SRF_15 0x400BB5C
+
+#define mmDCORE0_TPC0_CFG_QM_SRF_16 0x400BB60
+
+#define mmDCORE0_TPC0_CFG_QM_SRF_17 0x400BB64
+
+#define mmDCORE0_TPC0_CFG_QM_SRF_18 0x400BB68
+
+#define mmDCORE0_TPC0_CFG_QM_SRF_19 0x400BB6C
+
+#define mmDCORE0_TPC0_CFG_QM_SRF_20 0x400BB70
+
+#define mmDCORE0_TPC0_CFG_QM_SRF_21 0x400BB74
+
+#define mmDCORE0_TPC0_CFG_QM_SRF_22 0x400BB78
+
+#define mmDCORE0_TPC0_CFG_QM_SRF_23 0x400BB7C
+
+#define mmDCORE0_TPC0_CFG_QM_SRF_24 0x400BB80
+
+#define mmDCORE0_TPC0_CFG_QM_SRF_25 0x400BB84
+
+#define mmDCORE0_TPC0_CFG_QM_SRF_26 0x400BB88
+
+#define mmDCORE0_TPC0_CFG_QM_SRF_27 0x400BB8C
+
+#define mmDCORE0_TPC0_CFG_QM_SRF_28 0x400BB90
+
+#define mmDCORE0_TPC0_CFG_QM_SRF_29 0x400BB94
+
+#define mmDCORE0_TPC0_CFG_QM_SRF_30 0x400BB98
+
+#define mmDCORE0_TPC0_CFG_QM_SRF_31 0x400BB9C
+
+#define mmDCORE0_TPC0_CFG_QM_KERNEL_ID_INC 0x400BBA0
+
+#define mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_0 0x400BBA4
+
+#define mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_1 0x400BBA8
+
+#define mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_2 0x400BBAC
+
+#define mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_3 0x400BBB0
+
+#define mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_4 0x400BBB4
+
+#endif /* ASIC_REG_DCORE0_TPC0_CFG_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_sync_object_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_sync_object_regs.h
new file mode 100644
index 000000000000..8da278a3f3fe
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_sync_object_regs.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_TPC0_CFG_QM_SYNC_OBJECT_REGS_H_
+#define ASIC_REG_DCORE0_TPC0_CFG_QM_SYNC_OBJECT_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_TPC0_CFG_QM_SYNC_OBJECT
+ *   (Prototype: SYNC_OBJECT)
+ *****************************************
+ */
+
+#define mmDCORE0_TPC0_CFG_QM_SYNC_OBJECT_MESSAGE 0x400BADC
+
+#define mmDCORE0_TPC0_CFG_QM_SYNC_OBJECT_ADDR 0x400BAE0
+
+#endif /* ASIC_REG_DCORE0_TPC0_CFG_QM_SYNC_OBJECT_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_tensor_0_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_tensor_0_regs.h
new file mode 100644
index 000000000000..2e4ff06e4858
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_tensor_0_regs.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_TPC0_CFG_QM_TENSOR_0_REGS_H_
+#define ASIC_REG_DCORE0_TPC0_CFG_QM_TENSOR_0_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_TPC0_CFG_QM_TENSOR_0
+ *   (Prototype: TPC_TENSOR)
+ *****************************************
+ */
+
+#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0x400B5DC
+
+#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0x400B5E0
+
+#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_PADDING_VALUE 0x400B5E4
+
+#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG 0x400B5E8
+
+#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE 0x400B5EC
+
+#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE 0x400B5F0
+
+#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE 0x400B5F4
+
+#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE 0x400B5F8
+
+#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE 0x400B5FC
+
+#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE 0x400B600
+
+#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE 0x400B604
+
+#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE 0x400B608
+
+#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE 0x400B60C
+
+#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE 0x400B610
+
+#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_PREF_STRIDE 0x400B614
+
+#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_STRIDE_HIGH 0x400B618
+
+#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_STRIDE_HIGH 0x400B61C
+
+#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_STRIDE_HIGH 0x400B620
+
+#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_STRIDE_HIGH 0x400B624
+
+#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_STRIDE_HIGH 0x400B628
+
+#endif /* ASIC_REG_DCORE0_TPC0_CFG_QM_TENSOR_0_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_regs.h
new file mode 100644
index 000000000000..4d48f0c6880b
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_regs.h
@@ -0,0 +1,229 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_TPC0_CFG_REGS_H_
+#define ASIC_REG_DCORE0_TPC0_CFG_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_TPC0_CFG
+ *   (Prototype: TPC)
+ *****************************************
+ */
+
+#define mmDCORE0_TPC0_CFG_TPC_COUNT 0x400BC18
+
+#define mmDCORE0_TPC0_CFG_TPC_ID 0x400BC1C
+
+#define mmDCORE0_TPC0_CFG_STALL_ON_ERR 0x400BC20
+
+#define mmDCORE0_TPC0_CFG_CLK_EN 0x400BC24
+
+#define mmDCORE0_TPC0_CFG_IQ_RL_EN 0x400BC28
+
+#define mmDCORE0_TPC0_CFG_IQ_RL_SAT 0x400BC2C
+
+#define mmDCORE0_TPC0_CFG_IQ_RL_RST_TOKEN 0x400BC30
+
+#define mmDCORE0_TPC0_CFG_IQ_RL_TIMEOUT 0x400BC34
+
+#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_0 0x400BC38
+
+#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_1 0x400BC3C
+
+#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_2 0x400BC40
+
+#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_3 0x400BC44
+
+#define mmDCORE0_TPC0_CFG_IQ_LBW_CLK_EN 0x400BC48
+
+#define mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_0 0x400BC4C
+
+#define mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_1 0x400BC50
+
+#define mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_2 0x400BC54
+
+#define mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_3 0x400BC58
+
+#define mmDCORE0_TPC0_CFG_TPC_LOCK_0 0x400BC5C
+
+#define mmDCORE0_TPC0_CFG_TPC_LOCK_1 0x400BC60
+
+#define mmDCORE0_TPC0_CFG_TPC_LOCK_2 0x400BC64
+
+#define mmDCORE0_TPC0_CFG_TPC_LOCK_3 0x400BC68
+
+#define mmDCORE0_TPC0_CFG_CGU_SB 0x400BC6C
+
+#define mmDCORE0_TPC0_CFG_CGU_CNT 0x400BC70
+
+#define mmDCORE0_TPC0_CFG_CGU_CPE_0 0x400BC74
+
+#define mmDCORE0_TPC0_CFG_CGU_CPE_1 0x400BC78
+
+#define mmDCORE0_TPC0_CFG_CGU_CPE_2 0x400BC7C
+
+#define mmDCORE0_TPC0_CFG_CGU_CPE_3 0x400BC80
+
+#define mmDCORE0_TPC0_CFG_CGU_CPE_4 0x400BC84
+
+#define mmDCORE0_TPC0_CFG_CGU_CPE_5 0x400BC88
+
+#define mmDCORE0_TPC0_CFG_CGU_CPE_6 0x400BC8C
+
+#define mmDCORE0_TPC0_CFG_CGU_CPE_7 0x400BC90
+
+#define mmDCORE0_TPC0_CFG_FP16_FTZ_IN 0x400BC94
+
+#define mmDCORE0_TPC0_CFG_DCACHE_CFG 0x400BC98
+
+#define mmDCORE0_TPC0_CFG_E2E_CRDT_TOP 0x400BC9C
+
+#define mmDCORE0_TPC0_CFG_TPC_DCACHE_L0CD 0x400BCA0
+
+#define mmDCORE0_TPC0_CFG_TPC_SB_L0CD 0x400BCA4
+
+#define mmDCORE0_TPC0_CFG_CONV_ROUND_CSR 0x400BCA8
+
+#define mmDCORE0_TPC0_CFG_TSB_OCCUPANCY 0x400BCAC
+
+#define mmDCORE0_TPC0_CFG_ARB_QNT_HBW_WEIGHT 0x400BCB0
+
+#define mmDCORE0_TPC0_CFG_ARB_QNT_LBW_WEIGHT 0x400BCB4
+
+#define mmDCORE0_TPC0_CFG_ARB_CNT_HBW_WEIGHT 0x400BCB8
+
+#define mmDCORE0_TPC0_CFG_ARB_CNT_LBW_WEIGHT 0x400BCBC
+
+#define mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_LO 0x400BCC0
+
+#define mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_HI 0x400BCC4
+
+#define mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_LO 0x400BCC8
+
+#define mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_HI 0x400BCCC
+
+#define mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_LO 0x400BCD0
+
+#define mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_HI 0x400BCD4
+
+#define mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_LO 0x400BCD8
+
+#define mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_HI 0x400BCDC
+
+#define mmDCORE0_TPC0_CFG_SPE_LFSR_POLYNOM 0x400BCE0
+
+#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_GLBL 0x400BCE4
+
+#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_0 0x400BCE8
+
+#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_1 0x400BCEC
+
+#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2 0x400BCF0
+
+#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_3 0x400BCF4
+
+#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO_0 0x400BCF8
+
+#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO_1 0x400BCFC
+
+#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO_2 0x400BD00
+
+#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO_3 0x400BD04
+
+#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI_0 0x400BD08
+
+#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI_1 0x400BD0C
+
+#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI_2 0x400BD10
+
+#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI_3 0x400BD14
+
+#define mmDCORE0_TPC0_CFG_FP8_143_BIAS 0x400BD64
+
+#define mmDCORE0_TPC0_CFG_ROUND_CSR 0x400BD68
+
+#define mmDCORE0_TPC0_CFG_HB_PROT 0x400BD6C
+
+#define mmDCORE0_TPC0_CFG_LB_PROT 0x400BD70
+
+#define mmDCORE0_TPC0_CFG_SEMAPHORE 0x400BD74
+
+#define mmDCORE0_TPC0_CFG_VFLAGS 0x400BD78
+
+#define mmDCORE0_TPC0_CFG_SFLAGS 0x400BD7C
+
+#define mmDCORE0_TPC0_CFG_LFSR_POLYNOM 0x400BD80
+
+#define mmDCORE0_TPC0_CFG_STATUS 0x400BD84
+
+#define mmDCORE0_TPC0_CFG_CFG_BASE_ADDRESS_HIGH 0x400BD88
+
+#define mmDCORE0_TPC0_CFG_CFG_SUBTRACT_VALUE 0x400BD8C
+
+#define mmDCORE0_TPC0_CFG_SM_BASE_ADDRESS_HIGH 0x400BD90
+
+#define mmDCORE0_TPC0_CFG_TPC_CMD 0x400BD94
+
+#define mmDCORE0_TPC0_CFG_TPC_EXECUTE 0x400BD98
+
+#define mmDCORE0_TPC0_CFG_TPC_STALL 0x400BD9C
+
+#define mmDCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_LOW 0x400BDA0
+
+#define mmDCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH 0x400BDA4
+
+#define mmDCORE0_TPC0_CFG_RD_RATE_LIMIT 0x400BDA8
+
+#define mmDCORE0_TPC0_CFG_WR_RATE_LIMIT 0x400BDAC
+
+#define mmDCORE0_TPC0_CFG_MSS_CONFIG 0x400BDB0
+
+#define mmDCORE0_TPC0_CFG_TPC_INTR_CAUSE 0x400BDB4
+
+#define mmDCORE0_TPC0_CFG_TPC_INTR_MASK 0x400BDB8
+
+#define mmDCORE0_TPC0_CFG_WQ_CREDITS 0x400BDBC
+
+#define mmDCORE0_TPC0_CFG_OPCODE_EXEC 0x400BDC0
+
+#define mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO 0x400BDC4
+
+#define mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI 0x400BDC8
+
+#define mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO 0x400BDCC
+
+#define mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI 0x400BDD0
+
+#define mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO 0x400BDD4
+
+#define mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI 0x400BDD8
+
+#define mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO 0x400BDDC
+
+#define mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI 0x400BDE0
+
+#define mmDCORE0_TPC0_CFG_TSB_CFG_MAX_SIZE 0x400BDE4
+
+#define mmDCORE0_TPC0_CFG_TSB_CFG 0x400BDE8
+
+#define mmDCORE0_TPC0_CFG_TSB_INFLIGHT_CNTR 0x400BDEC
+
+#define mmDCORE0_TPC0_CFG_WQ_INFLIGHT_CNTR 0x400BDF0
+
+#define mmDCORE0_TPC0_CFG_WQ_LBW_TOTAL_CNTR 0x400BDF4
+
+#define mmDCORE0_TPC0_CFG_WQ_HBW_TOTAL_CNTR 0x400BDF8
+
+#define mmDCORE0_TPC0_CFG_IRQ_OCCOUPY_CNTR 0x400BDFC
+
+#endif /* ASIC_REG_DCORE0_TPC0_CFG_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_special_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_special_regs.h
new file mode 100644
index 000000000000..76ab8a1a7f31
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_special_regs.h
@@ -0,0 +1,185 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_TPC0_CFG_SPECIAL_REGS_H_
+#define ASIC_REG_DCORE0_TPC0_CFG_SPECIAL_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_TPC0_CFG_SPECIAL
+ *   (Prototype: SPECIAL_REGS)
+ *****************************************
+ */
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_0 0x400BE80
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_1 0x400BE84
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_2 0x400BE88
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_3 0x400BE8C
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_4 0x400BE90
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_5 0x400BE94
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_6 0x400BE98
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_7 0x400BE9C
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_8 0x400BEA0
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_9 0x400BEA4
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_10 0x400BEA8
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_11 0x400BEAC
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_12 0x400BEB0
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_13 0x400BEB4
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_14 0x400BEB8
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_15 0x400BEBC
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_16 0x400BEC0
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_17 0x400BEC4
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_18 0x400BEC8
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_19 0x400BECC
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_20 0x400BED0
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_21 0x400BED4
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_22 0x400BED8
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_23 0x400BEDC
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_24 0x400BEE0
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_25 0x400BEE4
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_26 0x400BEE8
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_27 0x400BEEC
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_28 0x400BEF0
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_29 0x400BEF4
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_30 0x400BEF8
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_31 0x400BEFC
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_GW_DATA 0x400BF00
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_GW_REQ 0x400BF04
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_NUMOF 0x400BF0C
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_SEL 0x400BF10
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_CTL 0x400BF14
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_ERR_MASK 0x400BF18
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_GLBL_ERR_MASK 0x400BF1C
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_ERR_STS 0x400BF20
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_ERR_ADDR 0x400BF24
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_RM 0x400BF28
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_ERR_MASK 0x400BF40
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_ERR_ADDR 0x400BF44
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_ERR_CAUSE 0x400BF48
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_0 0x400BF60
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_1 0x400BF64
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_2 0x400BF68
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_3 0x400BF6C
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_0 0x400BF80
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_1 0x400BF84
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_2 0x400BF88
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_3 0x400BF8C
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_4 0x400BF90
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_5 0x400BF94
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_6 0x400BF98
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_7 0x400BF9C
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_8 0x400BFA0
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_9 0x400BFA4
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_10 0x400BFA8
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_11 0x400BFAC
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_12 0x400BFB0
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_13 0x400BFB4
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_14 0x400BFB8
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_15 0x400BFBC
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_16 0x400BFC0
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_17 0x400BFC4
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_18 0x400BFC8
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_19 0x400BFCC
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_20 0x400BFD0
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_21 0x400BFD4
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_22 0x400BFD8
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_23 0x400BFDC
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_24 0x400BFE0
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_25 0x400BFE4
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_26 0x400BFE8
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_27 0x400BFEC
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_28 0x400BFF0
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_29 0x400BFF4
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_30 0x400BFF8
+
+#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_31 0x400BFFC
+
+#endif /* ASIC_REG_DCORE0_TPC0_CFG_SPECIAL_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_busmon_0_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_busmon_0_regs.h
new file mode 100644
index 000000000000..f07da4a24f06
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_busmon_0_regs.h
@@ -0,0 +1,163 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_TPC0_EML_BUSMON_0_REGS_H_
+#define ASIC_REG_DCORE0_TPC0_EML_BUSMON_0_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_TPC0_EML_BUSMON_0
+ *   (Prototype: BMON)
+ *****************************************
+ */
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_CR 0x7000
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_REG_RESET 0x7004
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_INT_CLR 0x7008
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_TRIG_TH 0x700C
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S0 0x7020
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S0 0x7024
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_E0 0x7028
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_E0 0x702C
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S1 0x7030
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S1 0x7034
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_E1 0x7038
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_E1 0x703C
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S2 0x7040
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S2 0x7044
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_E2 0x7048
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_E2 0x704C
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S3 0x7050
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S3 0x7054
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_E3 0x7058
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_E3 0x705C
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_REDUCTION 0x7060
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_IDL 0x7070
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_IDH 0x7074
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_IDENL 0x7078
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_IDENH 0x707C
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_LATENCY_SMP 0x7090
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_ATTR 0x7100
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_ATTREN 0x7104
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_USRENL 0x7108
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_USRL 0x710C
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_USRENH 0x7120
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_USRH 0x7124
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_CAPTURE 0x7200
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_RELEASE 0x7204
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_WIN_CAPTURE 0x7208
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_BW_WIN 0x720C
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_MATCH_CNT_SOD 0x7220
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_MATCH_CNT_WIN 0x7224
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_CYCCNT_L 0x7228
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_CYCCNT_H 0x722C
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_MAXLAT_SOD 0x7304
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_MINLAT_SOD 0x7308
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_MAXBW_SOD 0x7310
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_MINBW_SOD 0x7314
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_MAXOS_SOD 0x7320
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_MINOS_SOD 0x7324
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_SNAPSHOT 0x7400
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_SNAPSHOT 0x7404
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_IDL_SNAPSHOT 0x7408
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_IDH_SNAPSHOT 0x740C
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_ATTR_SNAPSHOT 0x7410
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_STM_TRC 0x7420
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_STM_TRC_DROP 0x7424
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_DEVARCH 0x7FBC
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_PMDEVID2 0x7FC0
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_PMDEVID1 0x7FC4
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_PMDEVID 0x7FC8
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_DEVTYPE 0x7FCC
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_PIDR4 0x7FD0
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_PIDR5 0x7FD4
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_PIDR6 0x7FD8
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_PIDR7 0x7FDC
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_PIDR0 0x7FE0
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_PIDR1 0x7FE4
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_PIDR2 0x7FE8
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_PIDR3 0x7FEC
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_CIDR0 0x7FF0
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_CIDR1 0x7FF4
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_CIDR2 0x7FF8
+
+#define mmDCORE0_TPC0_EML_BUSMON_0_CIDR3 0x7FFC
+
+#endif /* ASIC_REG_DCORE0_TPC0_EML_BUSMON_0_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_etf_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_etf_regs.h
new file mode 100644
index 000000000000..aee9cbc78c3d
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_etf_regs.h
@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_TPC0_EML_ETF_REGS_H_
+#define ASIC_REG_DCORE0_TPC0_EML_ETF_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_TPC0_EML_ETF
+ *   (Prototype: ETF_1KB)
+ *****************************************
+ */
+
+#define mmDCORE0_TPC0_EML_ETF_RSZ 0x2004
+
+#define mmDCORE0_TPC0_EML_ETF_STS 0x200C
+
+#define mmDCORE0_TPC0_EML_ETF_RRD 0x2010
+
+#define mmDCORE0_TPC0_EML_ETF_RRP 0x2014
+
+#define mmDCORE0_TPC0_EML_ETF_RWP 0x2018
+
+#define mmDCORE0_TPC0_EML_ETF_TRG 0x201C
+
+#define mmDCORE0_TPC0_EML_ETF_CTL 0x2020
+
+#define mmDCORE0_TPC0_EML_ETF_RWD 0x2024
+
+#define mmDCORE0_TPC0_EML_ETF_MODE 0x2028
+
+#define mmDCORE0_TPC0_EML_ETF_LBUFLEVEL 0x202C
+
+#define mmDCORE0_TPC0_EML_ETF_CBUFLEVEL 0x2030
+
+#define mmDCORE0_TPC0_EML_ETF_BUFWM 0x2034
+
+#define mmDCORE0_TPC0_EML_ETF_FFSR 0x2300
+
+#define mmDCORE0_TPC0_EML_ETF_FFCR 0x2304
+
+#define mmDCORE0_TPC0_EML_ETF_PSCR 0x2308
+
+#define mmDCORE0_TPC0_EML_ETF_ITATBMDATA0 0x2ED0
+
+#define mmDCORE0_TPC0_EML_ETF_ITATBMCTR2 0x2ED4
+
+#define mmDCORE0_TPC0_EML_ETF_ITATBMCTR1 0x2ED8
+
+#define mmDCORE0_TPC0_EML_ETF_ITATBMCTR0 0x2EDC
+
+#define mmDCORE0_TPC0_EML_ETF_ITMISCOP0 0x2EE0
+
+#define mmDCORE0_TPC0_EML_ETF_ITTRFLIN 0x2EE8
+
+#define mmDCORE0_TPC0_EML_ETF_ITATBDATA0 0x2EEC
+
+#define mmDCORE0_TPC0_EML_ETF_ITATBCTR2 0x2EF0
+
+#define mmDCORE0_TPC0_EML_ETF_ITATBCTR1 0x2EF4
+
+#define mmDCORE0_TPC0_EML_ETF_ITATBCTR0 0x2EF8
+
+#define mmDCORE0_TPC0_EML_ETF_ITCTRL 0x2F00
+
+#define mmDCORE0_TPC0_EML_ETF_CLAIMSET 0x2FA0
+
+#define mmDCORE0_TPC0_EML_ETF_CLAIMCLR 0x2FA4
+
+#define mmDCORE0_TPC0_EML_ETF_LAR 0x2FB0
+
+#define mmDCORE0_TPC0_EML_ETF_LSR 0x2FB4
+
+#define mmDCORE0_TPC0_EML_ETF_AUTHSTATUS 0x2FB8
+
+#define mmDCORE0_TPC0_EML_ETF_DEVID 0x2FC8
+
+#define mmDCORE0_TPC0_EML_ETF_DEVTYPE 0x2FCC
+
+#define mmDCORE0_TPC0_EML_ETF_PERIPHID4 0x2FD0
+
+#define mmDCORE0_TPC0_EML_ETF_PERIPHID5 0x2FD4
+
+#define mmDCORE0_TPC0_EML_ETF_PERIPHID6 0x2FD8
+
+#define mmDCORE0_TPC0_EML_ETF_PERIPHID7 0x2FDC
+
+#define mmDCORE0_TPC0_EML_ETF_PERIPHID0 0x2FE0
+
+#define mmDCORE0_TPC0_EML_ETF_PERIPHID1 0x2FE4
+
+#define mmDCORE0_TPC0_EML_ETF_PERIPHID2 0x2FE8
+
+#define mmDCORE0_TPC0_EML_ETF_PERIPHID3 0x2FEC
+
+#define mmDCORE0_TPC0_EML_ETF_COMPID0 0x2FF0
+
+#define mmDCORE0_TPC0_EML_ETF_COMPID1 0x2FF4
+
+#define mmDCORE0_TPC0_EML_ETF_COMPID2 0x2FF8
+
+#define mmDCORE0_TPC0_EML_ETF_COMPID3 0x2FFC
+
+#endif /* ASIC_REG_DCORE0_TPC0_EML_ETF_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_funnel_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_funnel_regs.h
new file mode 100644
index 000000000000..dee670b666ee
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_funnel_regs.h
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_TPC0_EML_FUNNEL_REGS_H_
+#define ASIC_REG_DCORE0_TPC0_EML_FUNNEL_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_TPC0_EML_FUNNEL
+ *   (Prototype: FUNNEL_2X1)
+ *****************************************
+ */
+
+#define mmDCORE0_TPC0_EML_FUNNEL_CTRL_REG 0x6000
+
+#define mmDCORE0_TPC0_EML_FUNNEL_PRIORITY_CTRL_REG 0x6004
+
+#define mmDCORE0_TPC0_EML_FUNNEL_ITATBDATA0 0x6EEC
+
+#define mmDCORE0_TPC0_EML_FUNNEL_ITATBCTR2 0x6EF0
+
+#define mmDCORE0_TPC0_EML_FUNNEL_ITATBCTR1 0x6EF4
+
+#define mmDCORE0_TPC0_EML_FUNNEL_ITATBCTR0 0x6EF8
+
+#define mmDCORE0_TPC0_EML_FUNNEL_ITCTRL 0x6F00
+
+#define mmDCORE0_TPC0_EML_FUNNEL_CLAIMSET 0x6FA0
+
+#define mmDCORE0_TPC0_EML_FUNNEL_CLAIMCLR 0x6FA4
+
+#define mmDCORE0_TPC0_EML_FUNNEL_LOCKACCESS 0x6FB0
+
+#define mmDCORE0_TPC0_EML_FUNNEL_LOCKSTATUS 0x6FB4
+
+#define mmDCORE0_TPC0_EML_FUNNEL_AUTHSTATUS 0x6FB8
+
+#define mmDCORE0_TPC0_EML_FUNNEL_DEVID 0x6FC8
+
+#define mmDCORE0_TPC0_EML_FUNNEL_DEVTYPE 0x6FCC
+
+#define mmDCORE0_TPC0_EML_FUNNEL_PIDR4 0x6FD0
+
+#define mmDCORE0_TPC0_EML_FUNNEL_PERIPHID5 0x6FD4
+
+#define mmDCORE0_TPC0_EML_FUNNEL_PERIPHID6 0x6FD8
+
+#define mmDCORE0_TPC0_EML_FUNNEL_PERIPHID7 0x6FDC
+
+#define mmDCORE0_TPC0_EML_FUNNEL_PIDR0 0x6FE0
+
+#define mmDCORE0_TPC0_EML_FUNNEL_PIDR1 0x6FE4
+
+#define mmDCORE0_TPC0_EML_FUNNEL_PIDR2 0x6FE8
+
+#define mmDCORE0_TPC0_EML_FUNNEL_PIDR3 0x6FEC
+
+#define mmDCORE0_TPC0_EML_FUNNEL_CID0 0x6FF0
+
+#define mmDCORE0_TPC0_EML_FUNNEL_CID1 0x6FF4
+
+#define mmDCORE0_TPC0_EML_FUNNEL_CID2 0x6FF8
+
+#define mmDCORE0_TPC0_EML_FUNNEL_CID3 0x6FFC
+
+#endif /* ASIC_REG_DCORE0_TPC0_EML_FUNNEL_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_spmu_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_spmu_regs.h
new file mode 100644
index 000000000000..580ae57476bd
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_spmu_regs.h
@@ -0,0 +1,151 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_TPC0_EML_SPMU_REGS_H_
+#define ASIC_REG_DCORE0_TPC0_EML_SPMU_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_TPC0_EML_SPMU
+ *   (Prototype: SPMU)
+ *****************************************
+ */
+
+#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR0_EL0 0x1000
+
+#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR1_EL0 0x1008
+
+#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR2_EL0 0x1010
+
+#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR3_EL0 0x1018
+
+#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR4_EL0 0x1020
+
+#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR5_EL0 0x1028
+
+#define mmDCORE0_TPC0_EML_SPMU_PMCCNTR_L_EL0 0x10F8
+
+#define mmDCORE0_TPC0_EML_SPMU_PMCCNTR_H_EL0 0x10FC
+
+#define mmDCORE0_TPC0_EML_SPMU_PMTRC 0x1200
+
+#define mmDCORE0_TPC0_EML_SPMU_TRC_CTRL_HOST 0x1204
+
+#define mmDCORE0_TPC0_EML_SPMU_TRC_STAT_HOST 0x1208
+
+#define mmDCORE0_TPC0_EML_SPMU_TRC_EN_HOST 0x120C
+
+#define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER0_EL0 0x1400
+
+#define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER1_EL0 0x1404
+
+#define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER2_EL0 0x1408
+
+#define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER3_EL0 0x140C
+
+#define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER4_EL0 0x1410
+
+#define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER5_EL0 0x1414
+
+#define mmDCORE0_TPC0_EML_SPMU_PMSSR 0x1610
+
+#define mmDCORE0_TPC0_EML_SPMU_PMOVSSR 0x1614
+
+#define mmDCORE0_TPC0_EML_SPMU_PMCCNTSR_L 0x1618
+
+#define mmDCORE0_TPC0_EML_SPMU_PMCCNTSR_H 0x161C
+
+#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR0 0x1620
+
+#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR1 0x1624
+
+#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR2 0x1628
+
+#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR3 0x162C
+
+#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR4 0x1630
+
+#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR5 0x1634
+
+#define mmDCORE0_TPC0_EML_SPMU_PMSCR 0x16F0
+
+#define mmDCORE0_TPC0_EML_SPMU_PMSRR 0x16F4
+
+#define mmDCORE0_TPC0_EML_SPMU_PMCNTENSET_EL0 0x1C00
+
+#define mmDCORE0_TPC0_EML_SPMU_PMCNTENCLR_EL0 0x1C20
+
+#define mmDCORE0_TPC0_EML_SPMU_PMINTENSET_EL1 0x1C40
+
+#define mmDCORE0_TPC0_EML_SPMU_PMINTENCLR_EL1 0x1C60
+
+#define mmDCORE0_TPC0_EML_SPMU_PMOVSCLR_EL0 0x1C80
+
+#define mmDCORE0_TPC0_EML_SPMU_PMSWINC_EL0 0x1CA0
+
+#define mmDCORE0_TPC0_EML_SPMU_PMOVSSET_EL0 0x1CC0
+
+#define mmDCORE0_TPC0_EML_SPMU_PMCFGR 0x1E00
+
+#define mmDCORE0_TPC0_EML_SPMU_PMCR_EL0 0x1E04
+
+#define mmDCORE0_TPC0_EML_SPMU_PMITCTRL 0x1F00
+
+#define mmDCORE0_TPC0_EML_SPMU_PMCLAIMSET 0x1FA0
+
+#define mmDCORE0_TPC0_EML_SPMU_PMCLAIMCLR 0x1FA4
+
+#define mmDCORE0_TPC0_EML_SPMU_PMDEVAFF0 0x1FA8
+
+#define mmDCORE0_TPC0_EML_SPMU_PMDEVAFF1 0x1FAC
+
+#define mmDCORE0_TPC0_EML_SPMU_PMLAR 0x1FB0
+
+#define mmDCORE0_TPC0_EML_SPMU_PMLSR 0x1FB4
+
+#define mmDCORE0_TPC0_EML_SPMU_PMAUTHSTATUS 0x1FB8
+
+#define mmDCORE0_TPC0_EML_SPMU_PMDEVARCH 0x1FBC
+
+#define mmDCORE0_TPC0_EML_SPMU_PMDEVID2 0x1FC0
+
+#define mmDCORE0_TPC0_EML_SPMU_PMDEVID1 0x1FC4
+
+#define mmDCORE0_TPC0_EML_SPMU_PMDEVID 0x1FC8
+
+#define mmDCORE0_TPC0_EML_SPMU_PMDEVTYPE 0x1FCC
+
+#define mmDCORE0_TPC0_EML_SPMU_PMPIDR4 0x1FD0
+
+#define mmDCORE0_TPC0_EML_SPMU_PMPIDR5 0x1FD4
+
+#define mmDCORE0_TPC0_EML_SPMU_PMPIDR6 0x1FD8
+
+#define mmDCORE0_TPC0_EML_SPMU_PMPIDR7 0x1FDC
+
+#define mmDCORE0_TPC0_EML_SPMU_PMPIDR0 0x1FE0
+
+#define mmDCORE0_TPC0_EML_SPMU_PMPIDR1 0x1FE4
+
+#define mmDCORE0_TPC0_EML_SPMU_PMPIDR2 0x1FE8
+
+#define mmDCORE0_TPC0_EML_SPMU_PMPIDR3 0x1FEC
+
+#define mmDCORE0_TPC0_EML_SPMU_PMCIDR0 0x1FF0
+
+#define mmDCORE0_TPC0_EML_SPMU_PMCIDR1 0x1FF4
+
+#define mmDCORE0_TPC0_EML_SPMU_PMCIDR2 0x1FF8
+
+#define mmDCORE0_TPC0_EML_SPMU_PMCIDR3 0x1FFC
+
+#endif /* ASIC_REG_DCORE0_TPC0_EML_SPMU_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_stm_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_stm_regs.h
new file mode 100644
index 000000000000..91686c563fe5
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_stm_regs.h
@@ -0,0 +1,131 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_TPC0_EML_STM_REGS_H_
+#define ASIC_REG_DCORE0_TPC0_EML_STM_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_TPC0_EML_STM
+ *   (Prototype: STM)
+ *****************************************
+ */
+
+#define mmDCORE0_TPC0_EML_STM_STMDMASTARTR 0x3C04
+
+#define mmDCORE0_TPC0_EML_STM_STMDMASTOPR 0x3C08
+
+#define mmDCORE0_TPC0_EML_STM_STMDMASTATR 0x3C0C
+
+#define mmDCORE0_TPC0_EML_STM_STMDMACTLR 0x3C10
+
+#define mmDCORE0_TPC0_EML_STM_STMDMAIDR 0x3CFC
+
+#define mmDCORE0_TPC0_EML_STM_STMHEER 0x3D00
+
+#define mmDCORE0_TPC0_EML_STM_STMHETER 0x3D20
+
+#define mmDCORE0_TPC0_EML_STM_STMHEBSR 0x3D60
+
+#define mmDCORE0_TPC0_EML_STM_STMHEMCR 0x3D64
+
+#define mmDCORE0_TPC0_EML_STM_STMHEEXTMUXR 0x3D68
+
+#define mmDCORE0_TPC0_EML_STM_STMHEMASTR 0x3DF4
+
+#define mmDCORE0_TPC0_EML_STM_STMHEFEAT1R 0x3DF8
+
+#define mmDCORE0_TPC0_EML_STM_STMHEIDR 0x3DFC
+
+#define mmDCORE0_TPC0_EML_STM_STMSPER 0x3E00
+
+#define mmDCORE0_TPC0_EML_STM_STMSPTER 0x3E20
+
+#define mmDCORE0_TPC0_EML_STM_STMSPSCR 0x3E60
+
+#define mmDCORE0_TPC0_EML_STM_STMSPMSCR 0x3E64
+
+#define mmDCORE0_TPC0_EML_STM_STMSPOVERRIDER 0x3E68
+
+#define mmDCORE0_TPC0_EML_STM_STMSPMOVERRIDER 0x3E6C
+
+#define mmDCORE0_TPC0_EML_STM_STMSPTRIGCSR 0x3E70
+
+#define mmDCORE0_TPC0_EML_STM_STMTCSR 0x3E80
+
+#define mmDCORE0_TPC0_EML_STM_STMTSSTIMR 0x3E84
+
+#define mmDCORE0_TPC0_EML_STM_STMTSFREQR 0x3E8C
+
+#define mmDCORE0_TPC0_EML_STM_STMSYNCR 0x3E90
+
+#define mmDCORE0_TPC0_EML_STM_STMAUXCR 0x3E94
+
+#define mmDCORE0_TPC0_EML_STM_STMFEAT1R 0x3EA0
+
+#define mmDCORE0_TPC0_EML_STM_STMFEAT2R 0x3EA4
+
+#define mmDCORE0_TPC0_EML_STM_STMFEAT3R 0x3EA8
+
+#define mmDCORE0_TPC0_EML_STM_STMITTRIGGER 0x3EE8
+
+#define mmDCORE0_TPC0_EML_STM_STMITATBDATA0 0x3EEC
+
+#define mmDCORE0_TPC0_EML_STM_STMITATBCTR2 0x3EF0
+
+#define mmDCORE0_TPC0_EML_STM_STMITATBID 0x3EF4
+
+#define mmDCORE0_TPC0_EML_STM_STMITATBCTR0 0x3EF8
+
+#define mmDCORE0_TPC0_EML_STM_STMITCTRL 0x3F00
+
+#define mmDCORE0_TPC0_EML_STM_STMCLAIMSET 0x3FA0
+
+#define mmDCORE0_TPC0_EML_STM_STMCLAIMCLR 0x3FA4
+
+#define mmDCORE0_TPC0_EML_STM_STMLAR 0x3FB0
+
+#define mmDCORE0_TPC0_EML_STM_STMLSR 0x3FB4
+
+#define mmDCORE0_TPC0_EML_STM_STMAUTHSTATUS 0x3FB8
+
+#define mmDCORE0_TPC0_EML_STM_STMDEVARCH 0x3FBC
+
+#define mmDCORE0_TPC0_EML_STM_STMDEVID 0x3FC8
+
+#define mmDCORE0_TPC0_EML_STM_STMDEVTYPE 0x3FCC
+
+#define mmDCORE0_TPC0_EML_STM_STMPIDR4 0x3FD0
+
+#define mmDCORE0_TPC0_EML_STM_STMPIDR5 0x3FD4
+
+#define mmDCORE0_TPC0_EML_STM_STMPIDR6 0x3FD8
+
+#define mmDCORE0_TPC0_EML_STM_STMPIDR7 0x3FDC
+
+#define mmDCORE0_TPC0_EML_STM_STMPIDR0 0x3FE0
+
+#define mmDCORE0_TPC0_EML_STM_STMPIDR1 0x3FE4
+
+#define mmDCORE0_TPC0_EML_STM_STMPIDR2 0x3FE8
+
+#define mmDCORE0_TPC0_EML_STM_STMPIDR3 0x3FEC
+
+#define mmDCORE0_TPC0_EML_STM_STMCIDR0 0x3FF0
+
+#define mmDCORE0_TPC0_EML_STM_STMCIDR1 0x3FF4
+
+#define mmDCORE0_TPC0_EML_STM_STMCIDR2 0x3FF8
+
+#define mmDCORE0_TPC0_EML_STM_STMCIDR3 0x3FFC
+
+#endif /* ASIC_REG_DCORE0_TPC0_EML_STM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_arc_aux_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_arc_aux_regs.h
new file mode 100644
index 000000000000..e007dabc5382
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_arc_aux_regs.h
@@ -0,0 +1,591 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_TPC0_QM_ARC_AUX_REGS_H_
+#define ASIC_REG_DCORE0_TPC0_QM_ARC_AUX_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_TPC0_QM_ARC_AUX
+ *   (Prototype: QMAN_ARC_AUX)
+ *****************************************
+ */
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_RUN_HALT_REQ 0x4008100
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_RUN_HALT_ACK 0x4008104
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_RST_VEC_ADDR 0x4008108
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DBG_MODE 0x400810C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CLUSTER_NUM 0x4008110
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_NUM 0x4008114
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_WAKE_UP_EVENT 0x4008118
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_SYS_ADDR_BASE 0x400811C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CTI_AP_STS 0x4008120
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CTI_CFG_MUX_SEL 0x4008124
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_RST 0x4008128
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_RST_REQ 0x400812C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_SRAM_LSB_ADDR 0x4008130
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_SRAM_MSB_ADDR 0x4008134
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_PCIE_LSB_ADDR 0x4008138
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_PCIE_MSB_ADDR 0x400813C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CFG_LSB_ADDR 0x4008140
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CFG_MSB_ADDR 0x4008144
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_HBM0_LSB_ADDR 0x4008150
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_HBM0_MSB_ADDR 0x4008154
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_HBM1_LSB_ADDR 0x4008158
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_HBM1_MSB_ADDR 0x400815C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_HBM2_LSB_ADDR 0x4008160
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_HBM2_MSB_ADDR 0x4008164
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_HBM3_LSB_ADDR 0x4008168
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_HBM3_MSB_ADDR 0x400816C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_HBM0_OFFSET 0x4008170
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_HBM1_OFFSET 0x4008174
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_HBM2_OFFSET 0x4008178
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_HBM3_OFFSET 0x400817C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_0 0x4008180
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_1 0x4008184
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_2 0x4008188
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_3 0x400818C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_4 0x4008190
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_5 0x4008194
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_6 0x4008198
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_0 0x400819C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_1 0x40081A0
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_2 0x40081A4
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_3 0x40081A8
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_4 0x40081AC
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_5 0x40081B0
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_6 0x40081B4
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_CBU_AWCACHE_OVR 0x40081B8
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_LBU_AWCACHE_OVR 0x40081BC
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_0 0x40081C0
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_1 0x40081C4
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_2 0x40081C8
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_3 0x40081CC
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_4 0x40081D0
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_5 0x40081D4
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_6 0x40081D8
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_7 0x40081DC
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_0 0x40081E0
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_1 0x40081E4
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_2 0x40081E8
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_3 0x40081EC
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_4 0x40081F0
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_5 0x40081F4
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_6 0x40081F8
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_7 0x40081FC
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_0 0x4008200
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_1 0x4008204
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_2 0x4008208
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_3 0x400820C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_4 0x4008210
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_5 0x4008214
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_6 0x4008218
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_7 0x400821C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_8 0x4008220
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_9 0x4008224
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_10 0x4008228
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_11 0x400822C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_12 0x4008230
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_13 0x4008234
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_14 0x4008238
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_15 0x400823C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_IRQ_INTR_MASK_0 0x4008280
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_IRQ_INTR_MASK_1 0x4008284
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_SEI_INTR_STS 0x4008290
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_SEI_INTR_CLR 0x4008294
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_SEI_INTR_MASK 0x4008298
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_EXCPTN_CAUSE 0x400829C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_SEI_INTR_HALT_EN 0x40082A0
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_SEI_INTR_HALT_MASK 0x40082A4
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_SEI_INTR_HALT_MASK 0x40082A8
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REI_INTR_STS 0x40082B0
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REI_INTR_CLR 0x40082B4
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REI_INTR_MASK 0x40082B8
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_ECC_ERR_ADDR 0x40082BC
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_ECC_SYNDROME 0x40082C0
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_I_CACHE_ECC_ERR_ADDR 0x40082C4
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_I_CACHE_ECC_SYNDROME 0x40082C8
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_D_CACHE_ECC_ERR_ADDR 0x40082CC
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_D_CACHE_ECC_SYNDROME 0x40082D0
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_LBW_TRMINATE_AWADDR_ERR 0x40082E0
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_LBW_TRMINATE_ARADDR_ERR 0x40082E4
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CFG_LBW_TERMINATE_BRESP 0x40082E8
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CFG_LBW_TERMINATE_RRESP 0x40082EC
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CFG_LBW_TERMINATE_AXLEN 0x40082F0
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CFG_LBW_TERMINATE_AXSIZE 0x40082F4
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_0 0x4008300
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_1 0x4008304
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_2 0x4008308
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_3 0x400830C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_4 0x4008310
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_5 0x4008314
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_6 0x4008318
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_7 0x400831C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_TOTAL_CBU_WR_CNT 0x4008320
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_INFLIGHT_CBU_WR_CNT 0x4008324
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_TOTAL_CBU_RD_CNT 0x4008328
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_INFLIGHT_CBU_RD_CNT 0x400832C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_TOTAL_LBU_WR_CNT 0x4008330
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_INFLIGHT_LBU_WR_CNT 0x4008334
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_TOTAL_LBU_RD_CNT 0x4008338
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT 0x400833C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_ARUSER_OVR 0x4008350
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_ARUSER_OVR_EN 0x4008354
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_AWUSER_OVR 0x4008358
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_AWUSER_OVR_EN 0x400835C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_ARUSER_MSB_OVR 0x4008360
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_ARUSER_MSB_OVR_EN 0x4008364
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_AWUSER_MSB_OVR 0x4008368
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_AWUSER_MSB_OVR_EN 0x400836C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_AXCACHE_OVR 0x4008370
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_LOCK_OVR 0x4008374
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_PROT_OVR 0x4008378
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_MAX_OUTSTANDING 0x400837C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_EARLY_BRESP_EN 0x4008380
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORCE_RSP_OK 0x4008384
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_NO_WR_INFLIGHT 0x400838C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_SEI_INTR_ID 0x4008390
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_LBU_ARUSER_OVR 0x4008400
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_LBU_ARUSER_OVR_EN 0x4008404
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_LBU_AWUSER_OVR 0x4008408
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_LBU_AWUSER_OVR_EN 0x400840C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_LBU_AXCACHE_OVR 0x4008420
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_LBU_LOCK_OVR 0x4008424
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_LBU_PROT_OVR 0x4008428
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_LBU_MAX_OUTSTANDING 0x400842C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_LBU_EARLY_BRESP_EN 0x4008430
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_LBU_FORCE_RSP_OK 0x4008434
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_LBU_NO_WR_INFLIGHT 0x400843C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_LBU_SEI_INTR_ID 0x4008440
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0 0x4008500
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_1 0x4008504
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_2 0x4008508
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_3 0x400850C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_4 0x4008510
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_5 0x4008514
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_6 0x4008518
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_7 0x400851C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_0 0x4008520
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_1 0x4008524
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_2 0x4008528
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_3 0x400852C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_4 0x4008530
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_5 0x4008534
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_6 0x4008538
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_7 0x400853C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_0 0x4008540
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_1 0x4008544
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_2 0x4008548
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_3 0x400854C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_4 0x4008550
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_5 0x4008554
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_6 0x4008558
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_7 0x400855C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_0 0x4008560
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_1 0x4008564
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_2 0x4008568
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_3 0x400856C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_4 0x4008570
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_5 0x4008574
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_6 0x4008578
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_7 0x400857C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_0 0x4008580
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_1 0x4008584
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_2 0x4008588
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_3 0x400858C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_4 0x4008590
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_5 0x4008594
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_6 0x4008598
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_7 0x400859C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_0 0x40085A0
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_1 0x40085A4
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_2 0x40085A8
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_3 0x40085AC
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_4 0x40085B0
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_5 0x40085B4
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_6 0x40085B8
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_7 0x40085BC
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_0 0x40085C0
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_1 0x40085C4
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_2 0x40085C8
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_3 0x40085CC
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_4 0x40085D0
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_5 0x40085D4
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_6 0x40085D8
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_7 0x40085DC
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_Q_VLD_ENTRY_MASK 0x40085E0
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_NIC_Q_VLD_ENTRY_MASK 0x40085E4
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_DROP_EN 0x4008620
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_WARN_MSG 0x4008624
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG 0x4008628
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_GEN_AXI_AWPROT 0x4008630
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_GEN_AXI_AWUSER 0x4008634
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_GEN_AXI_AWBURST 0x4008638
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_GEN_AXI_AWLOCK 0x400863C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_GEN_AXI_AWCACHE 0x4008640
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_WRR_ARB_WEIGHT 0x4008644
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_FULL_CFG 0x4008648
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT 0x400864C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_CQ_IFIFO_SHADOW_CI 0x4008650
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_ARC_CQ_IFIFO_SHADOW_CI 0x4008654
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_CQ_SHADOW_CI 0x4008658
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI 0x400865C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_AUX2APB_PROT 0x4008700
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_LBW_FORK_WIN_EN 0x4008704
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR0 0x4008708
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK0 0x400870C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR1 0x4008710
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK1 0x4008714
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR0 0x4008718
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK0 0x400871C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR1 0x4008720
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK1 0x4008724
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR0 0x4008728
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR1 0x400872C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_ACC_ENGS_LBW_FORK_MASK 0x4008730
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_DUP_ENG_LBW_FORK_ADDR 0x4008734
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_ACP_ENG_LBW_FORK_ADDR 0x4008738
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_ACC_ENGS_VIRTUAL_ADDR 0x400873C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_WIN_EN 0x4008740
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_LSB 0x4008750
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_MSB 0x4008754
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_LSB 0x4008758
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_MSB 0x400875C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_LSB 0x4008760
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_MSB 0x4008764
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_LSB 0x4008768
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_MSB 0x400876C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_LSB 0x4008770
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_MSB 0x4008774
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_LSB 0x4008778
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_MSB 0x400877C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_LSB 0x4008780
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_MSB 0x4008784
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_LSB 0x4008788
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_MSB 0x400878C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_TRMINATE_ARADDR_LSB 0x4008790
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CBU_TRMINATE_ARADDR_MSB 0x4008794
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CFG_CBU_TERMINATE_BRESP 0x4008798
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CFG_CBU_TERMINATE_RRESP 0x400879C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_0 0x4008800
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_1 0x4008804
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_2 0x4008808
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_3 0x400880C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_4 0x4008810
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_5 0x4008814
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_6 0x4008818
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_7 0x400881C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_8 0x4008820
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_9 0x4008824
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_10 0x4008828
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_11 0x400882C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_12 0x4008830
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_13 0x4008834
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_14 0x4008838
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_15 0x400883C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_TRMINATE_AWADDR_ERR 0x4008840
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_TRMINATE_ARADDR_ERR 0x4008844
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CFG_DCCM_TERMINATE_BRESP 0x4008848
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CFG_DCCM_TERMINATE_RRESP 0x400884C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CFG_DCCM_TERMINATE_EN 0x4008850
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_CFG_DCCM_SECURE_REGION 0x4008854
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT 0x4008900
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_AXI_ORDERING_CTL 0x4008904
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR_MSK 0x4008908
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR 0x400890C
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_ACC_ENGS_BUSER 0x4008910
+
+#define mmDCORE0_TPC0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN 0x4008920
+
+#endif /* ASIC_REG_DCORE0_TPC0_QM_ARC_AUX_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_axuser_nonsecured_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_axuser_nonsecured_regs.h
new file mode 100644
index 000000000000..149b85f5f045
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_axuser_nonsecured_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_TPC0_QM_AXUSER_NONSECURED_REGS_H_
+#define ASIC_REG_DCORE0_TPC0_QM_AXUSER_NONSECURED_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_TPC0_QM_AXUSER_NONSECURED
+ *   (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_ASID 0x400AB80
+
+#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_MMU_BP 0x400AB84
+
+#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_STRONG_ORDER 0x400AB88
+
+#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_NO_SNOOP 0x400AB8C
+
+#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_WR_REDUCTION 0x400AB90
+
+#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_RD_ATOMIC 0x400AB94
+
+#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_QOS 0x400AB98
+
+#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_RSVD 0x400AB9C
+
+#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_EMEM_CPAGE 0x400ABA0
+
+#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_CORE 0x400ABA4
+
+#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_E2E_COORD 0x400ABA8
+
+#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_WR_OVRD_LO 0x400ABB0
+
+#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_WR_OVRD_HI 0x400ABB4
+
+#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_RD_OVRD_LO 0x400ABB8
+
+#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_HB_RD_OVRD_HI 0x400ABBC
+
+#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_LB_COORD 0x400ABC0
+
+#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_LB_LOCK 0x400ABC4
+
+#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_LB_RSVD 0x400ABC8
+
+#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_LB_OVRD 0x400ABCC
+
+#endif /* ASIC_REG_DCORE0_TPC0_QM_AXUSER_NONSECURED_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_cgm_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_cgm_regs.h
new file mode 100644
index 000000000000..d4aad1875ad6
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_cgm_regs.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_TPC0_QM_CGM_REGS_H_
+#define ASIC_REG_DCORE0_TPC0_QM_CGM_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_TPC0_QM_CGM
+ *   (Prototype: QMAN_CGM)
+ *****************************************
+ */
+
+#define mmDCORE0_TPC0_QM_CGM_CFG 0x400AD80
+
+#define mmDCORE0_TPC0_QM_CGM_STS 0x400AD84
+
+#define mmDCORE0_TPC0_QM_CGM_CFG1 0x400AD88
+
+#endif /* ASIC_REG_DCORE0_TPC0_QM_CGM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_regs.h
new file mode 100644
index 000000000000..cca8683cbca1
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_regs.h
@@ -0,0 +1,1057 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_TPC0_QM_REGS_H_
+#define ASIC_REG_DCORE0_TPC0_QM_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_TPC0_QM
+ *   (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmDCORE0_TPC0_QM_GLBL_CFG0 0x400A000
+
+#define mmDCORE0_TPC0_QM_GLBL_CFG1 0x400A004
+
+#define mmDCORE0_TPC0_QM_GLBL_CFG2 0x400A008
+
+#define mmDCORE0_TPC0_QM_GLBL_ERR_CFG 0x400A00C
+
+#define mmDCORE0_TPC0_QM_GLBL_ERR_CFG1 0x400A010
+
+#define mmDCORE0_TPC0_QM_GLBL_ERR_ARC_HALT_EN 0x400A014
+
+#define mmDCORE0_TPC0_QM_GLBL_AXCACHE 0x400A018
+
+#define mmDCORE0_TPC0_QM_GLBL_STS0 0x400A01C
+
+#define mmDCORE0_TPC0_QM_GLBL_STS1 0x400A020
+
+#define mmDCORE0_TPC0_QM_GLBL_ERR_STS_0 0x400A024
+
+#define mmDCORE0_TPC0_QM_GLBL_ERR_STS_1 0x400A028
+
+#define mmDCORE0_TPC0_QM_GLBL_ERR_STS_2 0x400A02C
+
+#define mmDCORE0_TPC0_QM_GLBL_ERR_STS_3 0x400A030
+
+#define mmDCORE0_TPC0_QM_GLBL_ERR_STS_4 0x400A034
+
+#define mmDCORE0_TPC0_QM_GLBL_ERR_MSG_EN_0 0x400A038
+
+#define mmDCORE0_TPC0_QM_GLBL_ERR_MSG_EN_1 0x400A03C
+
+#define mmDCORE0_TPC0_QM_GLBL_ERR_MSG_EN_2 0x400A040
+
+#define mmDCORE0_TPC0_QM_GLBL_ERR_MSG_EN_3 0x400A044
+
+#define mmDCORE0_TPC0_QM_GLBL_ERR_MSG_EN_4 0x400A048
+
+#define mmDCORE0_TPC0_QM_GLBL_PROT 0x400A04C
+
+#define mmDCORE0_TPC0_QM_PQ_BASE_LO_0 0x400A050
+
+#define mmDCORE0_TPC0_QM_PQ_BASE_LO_1 0x400A054
+
+#define mmDCORE0_TPC0_QM_PQ_BASE_LO_2 0x400A058
+
+#define mmDCORE0_TPC0_QM_PQ_BASE_LO_3 0x400A05C
+
+#define mmDCORE0_TPC0_QM_PQ_BASE_HI_0 0x400A060
+
+#define mmDCORE0_TPC0_QM_PQ_BASE_HI_1 0x400A064
+
+#define mmDCORE0_TPC0_QM_PQ_BASE_HI_2 0x400A068
+
+#define mmDCORE0_TPC0_QM_PQ_BASE_HI_3 0x400A06C
+
+#define mmDCORE0_TPC0_QM_PQ_SIZE_0 0x400A070
+
+#define mmDCORE0_TPC0_QM_PQ_SIZE_1 0x400A074
+
+#define mmDCORE0_TPC0_QM_PQ_SIZE_2 0x400A078
+
+#define mmDCORE0_TPC0_QM_PQ_SIZE_3 0x400A07C
+
+#define mmDCORE0_TPC0_QM_PQ_PI_0 0x400A080
+
+#define mmDCORE0_TPC0_QM_PQ_PI_1 0x400A084
+
+#define mmDCORE0_TPC0_QM_PQ_PI_2 0x400A088
+
+#define mmDCORE0_TPC0_QM_PQ_PI_3 0x400A08C
+
+#define mmDCORE0_TPC0_QM_PQ_CI_0 0x400A090
+
+#define mmDCORE0_TPC0_QM_PQ_CI_1 0x400A094
+
+#define mmDCORE0_TPC0_QM_PQ_CI_2 0x400A098
+
+#define mmDCORE0_TPC0_QM_PQ_CI_3 0x400A09C
+
+#define mmDCORE0_TPC0_QM_PQ_CFG0_0 0x400A0A0
+
+#define mmDCORE0_TPC0_QM_PQ_CFG0_1 0x400A0A4
+
+#define mmDCORE0_TPC0_QM_PQ_CFG0_2 0x400A0A8
+
+#define mmDCORE0_TPC0_QM_PQ_CFG0_3 0x400A0AC
+
+#define mmDCORE0_TPC0_QM_PQ_CFG1_0 0x400A0B0
+
+#define mmDCORE0_TPC0_QM_PQ_CFG1_1 0x400A0B4
+
+#define mmDCORE0_TPC0_QM_PQ_CFG1_2 0x400A0B8
+
+#define mmDCORE0_TPC0_QM_PQ_CFG1_3 0x400A0BC
+
+#define mmDCORE0_TPC0_QM_PQ_STS0_0 0x400A0C0
+
+#define mmDCORE0_TPC0_QM_PQ_STS0_1 0x400A0C4
+
+#define mmDCORE0_TPC0_QM_PQ_STS0_2 0x400A0C8
+
+#define mmDCORE0_TPC0_QM_PQ_STS0_3 0x400A0CC
+
+#define mmDCORE0_TPC0_QM_PQ_STS1_0 0x400A0D0
+
+#define mmDCORE0_TPC0_QM_PQ_STS1_1 0x400A0D4
+
+#define mmDCORE0_TPC0_QM_PQ_STS1_2 0x400A0D8
+
+#define mmDCORE0_TPC0_QM_PQ_STS1_3 0x400A0DC
+
+#define mmDCORE0_TPC0_QM_CQ_CFG0_0 0x400A0E0
+
+#define mmDCORE0_TPC0_QM_CQ_CFG0_1 0x400A0E4
+
+#define mmDCORE0_TPC0_QM_CQ_CFG0_2 0x400A0E8
+
+#define mmDCORE0_TPC0_QM_CQ_CFG0_3 0x400A0EC
+
+#define mmDCORE0_TPC0_QM_CQ_CFG0_4 0x400A0F0
+
+#define mmDCORE0_TPC0_QM_CQ_STS0_0 0x400A0F4
+
+#define mmDCORE0_TPC0_QM_CQ_STS0_1 0x400A0F8
+
+#define mmDCORE0_TPC0_QM_CQ_STS0_2 0x400A0FC
+
+#define mmDCORE0_TPC0_QM_CQ_STS0_3 0x400A100
+
+#define mmDCORE0_TPC0_QM_CQ_STS0_4 0x400A104
+
+#define mmDCORE0_TPC0_QM_CQ_CFG1_0 0x400A108
+
+#define mmDCORE0_TPC0_QM_CQ_CFG1_1 0x400A10C
+
+#define mmDCORE0_TPC0_QM_CQ_CFG1_2 0x400A110
+
+#define mmDCORE0_TPC0_QM_CQ_CFG1_3 0x400A114
+
+#define mmDCORE0_TPC0_QM_CQ_CFG1_4 0x400A118
+
+#define mmDCORE0_TPC0_QM_CQ_STS1_0 0x400A11C
+
+#define mmDCORE0_TPC0_QM_CQ_STS1_1 0x400A120
+
+#define mmDCORE0_TPC0_QM_CQ_STS1_2 0x400A124
+
+#define mmDCORE0_TPC0_QM_CQ_STS1_3 0x400A128
+
+#define mmDCORE0_TPC0_QM_CQ_STS1_4 0x400A12C
+
+#define mmDCORE0_TPC0_QM_CQ_PTR_LO_0 0x400A150
+
+#define mmDCORE0_TPC0_QM_CQ_PTR_HI_0 0x400A154
+
+#define mmDCORE0_TPC0_QM_CQ_TSIZE_0 0x400A158
+
+#define mmDCORE0_TPC0_QM_CQ_CTL_0 0x400A15C
+
+#define mmDCORE0_TPC0_QM_CQ_PTR_LO_1 0x400A160
+
+#define mmDCORE0_TPC0_QM_CQ_PTR_HI_1 0x400A164
+
+#define mmDCORE0_TPC0_QM_CQ_TSIZE_1 0x400A168
+
+#define mmDCORE0_TPC0_QM_CQ_CTL_1 0x400A16C
+
+#define mmDCORE0_TPC0_QM_CQ_PTR_LO_2 0x400A170
+
+#define mmDCORE0_TPC0_QM_CQ_PTR_HI_2 0x400A174
+
+#define mmDCORE0_TPC0_QM_CQ_TSIZE_2 0x400A178
+
+#define mmDCORE0_TPC0_QM_CQ_CTL_2 0x400A17C
+
+#define mmDCORE0_TPC0_QM_CQ_PTR_LO_3 0x400A180
+
+#define mmDCORE0_TPC0_QM_CQ_PTR_HI_3 0x400A184
+
+#define mmDCORE0_TPC0_QM_CQ_TSIZE_3 0x400A188
+
+#define mmDCORE0_TPC0_QM_CQ_CTL_3 0x400A18C
+
+#define mmDCORE0_TPC0_QM_CQ_PTR_LO_4 0x400A190
+
+#define mmDCORE0_TPC0_QM_CQ_PTR_HI_4 0x400A194
+
+#define mmDCORE0_TPC0_QM_CQ_TSIZE_4 0x400A198
+
+#define mmDCORE0_TPC0_QM_CQ_CTL_4 0x400A19C
+
+#define mmDCORE0_TPC0_QM_CQ_TSIZE_STS_0 0x400A1A0
+
+#define mmDCORE0_TPC0_QM_CQ_TSIZE_STS_1 0x400A1A4
+
+#define mmDCORE0_TPC0_QM_CQ_TSIZE_STS_2 0x400A1A8
+
+#define mmDCORE0_TPC0_QM_CQ_TSIZE_STS_3 0x400A1AC
+
+#define mmDCORE0_TPC0_QM_CQ_TSIZE_STS_4 0x400A1B0
+
+#define mmDCORE0_TPC0_QM_CQ_PTR_LO_STS_0 0x400A1B4
+
+#define mmDCORE0_TPC0_QM_CQ_PTR_LO_STS_1 0x400A1B8
+
+#define mmDCORE0_TPC0_QM_CQ_PTR_LO_STS_2 0x400A1BC
+
+#define mmDCORE0_TPC0_QM_CQ_PTR_LO_STS_3 0x400A1C0
+
+#define mmDCORE0_TPC0_QM_CQ_PTR_LO_STS_4 0x400A1C4
+
+#define mmDCORE0_TPC0_QM_CQ_PTR_HI_STS_0 0x400A1C8
+
+#define mmDCORE0_TPC0_QM_CQ_PTR_HI_STS_1 0x400A1CC
+
+#define mmDCORE0_TPC0_QM_CQ_PTR_HI_STS_2 0x400A1D0
+
+#define mmDCORE0_TPC0_QM_CQ_PTR_HI_STS_3 0x400A1D4
+
+#define mmDCORE0_TPC0_QM_CQ_PTR_HI_STS_4 0x400A1D8
+
+#define mmDCORE0_TPC0_QM_CQ_IFIFO_STS_0 0x400A1DC
+
+#define mmDCORE0_TPC0_QM_CQ_IFIFO_STS_1 0x400A1E0
+
+#define mmDCORE0_TPC0_QM_CQ_IFIFO_STS_2 0x400A1E4
+
+#define mmDCORE0_TPC0_QM_CQ_IFIFO_STS_3 0x400A1E8
+
+#define mmDCORE0_TPC0_QM_CQ_IFIFO_STS_4 0x400A1EC
+
+#define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_0 0x400A1F0
+
+#define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_1 0x400A1F4
+
+#define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_2 0x400A1F8
+
+#define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_3 0x400A1FC
+
+#define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_4 0x400A200
+
+#define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_0 0x400A204
+
+#define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_1 0x400A208
+
+#define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_2 0x400A20C
+
+#define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_3 0x400A210
+
+#define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_4 0x400A214
+
+#define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_0 0x400A218
+
+#define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_1 0x400A21C
+
+#define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_2 0x400A220
+
+#define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_3 0x400A224
+
+#define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_4 0x400A228
+
+#define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_0 0x400A22C
+
+#define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_1 0x400A230
+
+#define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_2 0x400A234
+
+#define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_3 0x400A238
+
+#define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_4 0x400A23C
+
+#define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_0 0x400A240
+
+#define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_1 0x400A244
+
+#define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_2 0x400A248
+
+#define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_3 0x400A24C
+
+#define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_4 0x400A250
+
+#define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_0 0x400A254
+
+#define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_1 0x400A258
+
+#define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_2 0x400A25C
+
+#define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_3 0x400A260
+
+#define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_4 0x400A264
+
+#define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_0 0x400A268
+
+#define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_1 0x400A26C
+
+#define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_2 0x400A270
+
+#define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_3 0x400A274
+
+#define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_4 0x400A278
+
+#define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_0 0x400A27C
+
+#define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_1 0x400A280
+
+#define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_2 0x400A284
+
+#define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_3 0x400A288
+
+#define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_4 0x400A28C
+
+#define mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_0 0x400A290
+
+#define mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_1 0x400A294
+
+#define mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_2 0x400A298
+
+#define mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_3 0x400A29C
+
+#define mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_4 0x400A2A0
+
+#define mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_0 0x400A2A4
+
+#define mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_1 0x400A2A8
+
+#define mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_2 0x400A2AC
+
+#define mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_3 0x400A2B0
+
+#define mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_4 0x400A2B4
+
+#define mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_0 0x400A2B8
+
+#define mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_1 0x400A2BC
+
+#define mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_2 0x400A2C0
+
+#define mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_3 0x400A2C4
+
+#define mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_4 0x400A2C8
+
+#define mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_0 0x400A2CC
+
+#define mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_1 0x400A2D0
+
+#define mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_2 0x400A2D4
+
+#define mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_3 0x400A2D8
+
+#define mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_4 0x400A2DC
+
+#define mmDCORE0_TPC0_QM_CP_FENCE0_CNT_0 0x400A2E0
+
+#define mmDCORE0_TPC0_QM_CP_FENCE0_CNT_1 0x400A2E4
+
+#define mmDCORE0_TPC0_QM_CP_FENCE0_CNT_2 0x400A2E8
+
+#define mmDCORE0_TPC0_QM_CP_FENCE0_CNT_3 0x400A2EC
+
+#define mmDCORE0_TPC0_QM_CP_FENCE0_CNT_4 0x400A2F0
+
+#define mmDCORE0_TPC0_QM_CP_FENCE1_CNT_0 0x400A2F4
+
+#define mmDCORE0_TPC0_QM_CP_FENCE1_CNT_1 0x400A2F8
+
+#define mmDCORE0_TPC0_QM_CP_FENCE1_CNT_2 0x400A2FC
+
+#define mmDCORE0_TPC0_QM_CP_FENCE1_CNT_3 0x400A300
+
+#define mmDCORE0_TPC0_QM_CP_FENCE1_CNT_4 0x400A304
+
+#define mmDCORE0_TPC0_QM_CP_FENCE2_CNT_0 0x400A308
+
+#define mmDCORE0_TPC0_QM_CP_FENCE2_CNT_1 0x400A30C
+
+#define mmDCORE0_TPC0_QM_CP_FENCE2_CNT_2 0x400A310
+
+#define mmDCORE0_TPC0_QM_CP_FENCE2_CNT_3 0x400A314
+
+#define mmDCORE0_TPC0_QM_CP_FENCE2_CNT_4 0x400A318
+
+#define mmDCORE0_TPC0_QM_CP_FENCE3_CNT_0 0x400A31C
+
+#define mmDCORE0_TPC0_QM_CP_FENCE3_CNT_1 0x400A320
+
+#define mmDCORE0_TPC0_QM_CP_FENCE3_CNT_2 0x400A324
+
+#define mmDCORE0_TPC0_QM_CP_FENCE3_CNT_3 0x400A328
+
+#define mmDCORE0_TPC0_QM_CP_FENCE3_CNT_4 0x400A32C
+
+#define mmDCORE0_TPC0_QM_CP_BARRIER_CFG 0x400A330
+
+#define mmDCORE0_TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0x400A334
+
+#define mmDCORE0_TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET 0x400A338
+
+#define mmDCORE0_TPC0_QM_CP_LDMA_TSIZE_OFFSET 0x400A33C
+
+#define mmDCORE0_TPC0_QM_CP_CQ_PTR_LO_OFFSET_0 0x400A340
+
+#define mmDCORE0_TPC0_QM_CP_CQ_PTR_LO_OFFSET_1 0x400A344
+
+#define mmDCORE0_TPC0_QM_CP_CQ_PTR_LO_OFFSET_2 0x400A348
+
+#define mmDCORE0_TPC0_QM_CP_CQ_PTR_LO_OFFSET_3 0x400A34C
+
+#define mmDCORE0_TPC0_QM_CP_CQ_PTR_LO_OFFSET_4 0x400A350
+
+#define mmDCORE0_TPC0_QM_CP_STS_0 0x400A368
+
+#define mmDCORE0_TPC0_QM_CP_STS_1 0x400A36C
+
+#define mmDCORE0_TPC0_QM_CP_STS_2 0x400A370
+
+#define mmDCORE0_TPC0_QM_CP_STS_3 0x400A374
+
+#define mmDCORE0_TPC0_QM_CP_STS_4 0x400A378
+
+#define mmDCORE0_TPC0_QM_CP_CURRENT_INST_LO_0 0x400A37C
+
+#define mmDCORE0_TPC0_QM_CP_CURRENT_INST_LO_1 0x400A380
+
+#define mmDCORE0_TPC0_QM_CP_CURRENT_INST_LO_2 0x400A384
+
+#define mmDCORE0_TPC0_QM_CP_CURRENT_INST_LO_3 0x400A388
+
+#define mmDCORE0_TPC0_QM_CP_CURRENT_INST_LO_4 0x400A38C
+
+#define mmDCORE0_TPC0_QM_CP_CURRENT_INST_HI_0 0x400A390
+
+#define mmDCORE0_TPC0_QM_CP_CURRENT_INST_HI_1 0x400A394
+
+#define mmDCORE0_TPC0_QM_CP_CURRENT_INST_HI_2 0x400A398
+
+#define mmDCORE0_TPC0_QM_CP_CURRENT_INST_HI_3 0x400A39C
+
+#define mmDCORE0_TPC0_QM_CP_CURRENT_INST_HI_4 0x400A3A0
+
+#define mmDCORE0_TPC0_QM_CP_PRED_0 0x400A3A4
+
+#define mmDCORE0_TPC0_QM_CP_PRED_1 0x400A3A8
+
+#define mmDCORE0_TPC0_QM_CP_PRED_2 0x400A3AC
+
+#define mmDCORE0_TPC0_QM_CP_PRED_3 0x400A3B0
+
+#define mmDCORE0_TPC0_QM_CP_PRED_4 0x400A3B4
+
+#define mmDCORE0_TPC0_QM_CP_PRED_UPEN_0 0x400A3B8
+
+#define mmDCORE0_TPC0_QM_CP_PRED_UPEN_1 0x400A3BC
+
+#define mmDCORE0_TPC0_QM_CP_PRED_UPEN_2 0x400A3C0
+
+#define mmDCORE0_TPC0_QM_CP_PRED_UPEN_3 0x400A3C4
+
+#define mmDCORE0_TPC0_QM_CP_PRED_UPEN_4 0x400A3C8
+
+#define mmDCORE0_TPC0_QM_CP_DBG_0_0 0x400A3CC
+
+#define mmDCORE0_TPC0_QM_CP_DBG_0_1 0x400A3D0
+
+#define mmDCORE0_TPC0_QM_CP_DBG_0_2 0x400A3D4
+
+#define mmDCORE0_TPC0_QM_CP_DBG_0_3 0x400A3D8
+
+#define mmDCORE0_TPC0_QM_CP_DBG_0_4 0x400A3DC
+
+#define mmDCORE0_TPC0_QM_CP_CPDMA_UP_CRED_0 0x400A3E0
+
+#define mmDCORE0_TPC0_QM_CP_CPDMA_UP_CRED_1 0x400A3E4
+
+#define mmDCORE0_TPC0_QM_CP_CPDMA_UP_CRED_2 0x400A3E8
+
+#define mmDCORE0_TPC0_QM_CP_CPDMA_UP_CRED_3 0x400A3EC
+
+#define mmDCORE0_TPC0_QM_CP_CPDMA_UP_CRED_4 0x400A3F0
+
+#define mmDCORE0_TPC0_QM_CP_IN_DATA_LO_0 0x400A3F4
+
+#define mmDCORE0_TPC0_QM_CP_IN_DATA_LO_1 0x400A3F8
+
+#define mmDCORE0_TPC0_QM_CP_IN_DATA_LO_2 0x400A3FC
+
+#define mmDCORE0_TPC0_QM_CP_IN_DATA_LO_3 0x400A400
+
+#define mmDCORE0_TPC0_QM_CP_IN_DATA_LO_4 0x400A404
+
+#define mmDCORE0_TPC0_QM_CP_IN_DATA_HI_0 0x400A408
+
+#define mmDCORE0_TPC0_QM_CP_IN_DATA_HI_1 0x400A40C
+
+#define mmDCORE0_TPC0_QM_CP_IN_DATA_HI_2 0x400A410
+
+#define mmDCORE0_TPC0_QM_CP_IN_DATA_HI_3 0x400A414
+
+#define mmDCORE0_TPC0_QM_CP_IN_DATA_HI_4 0x400A418
+
+#define mmDCORE0_TPC0_QM_PQC_HBW_BASE_LO_0 0x400A41C
+
+#define mmDCORE0_TPC0_QM_PQC_HBW_BASE_LO_1 0x400A420
+
+#define mmDCORE0_TPC0_QM_PQC_HBW_BASE_LO_2 0x400A424
+
+#define mmDCORE0_TPC0_QM_PQC_HBW_BASE_LO_3 0x400A428
+
+#define mmDCORE0_TPC0_QM_PQC_HBW_BASE_HI_0 0x400A42C
+
+#define mmDCORE0_TPC0_QM_PQC_HBW_BASE_HI_1 0x400A430
+
+#define mmDCORE0_TPC0_QM_PQC_HBW_BASE_HI_2 0x400A434
+
+#define mmDCORE0_TPC0_QM_PQC_HBW_BASE_HI_3 0x400A438
+
+#define mmDCORE0_TPC0_QM_PQC_SIZE_0 0x400A43C
+
+#define mmDCORE0_TPC0_QM_PQC_SIZE_1 0x400A440
+
+#define mmDCORE0_TPC0_QM_PQC_SIZE_2 0x400A444
+
+#define mmDCORE0_TPC0_QM_PQC_SIZE_3 0x400A448
+
+#define mmDCORE0_TPC0_QM_PQC_PI_0 0x400A44C
+
+#define mmDCORE0_TPC0_QM_PQC_PI_1 0x400A450
+
+#define mmDCORE0_TPC0_QM_PQC_PI_2 0x400A454
+
+#define mmDCORE0_TPC0_QM_PQC_PI_3 0x400A458
+
+#define mmDCORE0_TPC0_QM_PQC_LBW_WDATA_0 0x400A45C
+
+#define mmDCORE0_TPC0_QM_PQC_LBW_WDATA_1 0x400A460
+
+#define mmDCORE0_TPC0_QM_PQC_LBW_WDATA_2 0x400A464
+
+#define mmDCORE0_TPC0_QM_PQC_LBW_WDATA_3 0x400A468
+
+#define mmDCORE0_TPC0_QM_PQC_LBW_BASE_LO_0 0x400A46C
+
+#define mmDCORE0_TPC0_QM_PQC_LBW_BASE_LO_1 0x400A470
+
+#define mmDCORE0_TPC0_QM_PQC_LBW_BASE_LO_2 0x400A474
+
+#define mmDCORE0_TPC0_QM_PQC_LBW_BASE_LO_3 0x400A478
+
+#define mmDCORE0_TPC0_QM_PQC_LBW_BASE_HI_0 0x400A47C
+
+#define mmDCORE0_TPC0_QM_PQC_LBW_BASE_HI_1 0x400A480
+
+#define mmDCORE0_TPC0_QM_PQC_LBW_BASE_HI_2 0x400A484
+
+#define mmDCORE0_TPC0_QM_PQC_LBW_BASE_HI_3 0x400A488
+
+#define mmDCORE0_TPC0_QM_PQC_CFG 0x400A48C
+
+#define mmDCORE0_TPC0_QM_PQC_SECURE_PUSH_IND 0x400A490
+
+#define mmDCORE0_TPC0_QM_ARB_MASK 0x400A4A0
+
+#define mmDCORE0_TPC0_QM_ARB_CFG_0 0x400A4A4
+
+#define mmDCORE0_TPC0_QM_ARB_CHOICE_Q_PUSH 0x400A4A8
+
+#define mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_0 0x400A4AC
+
+#define mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_1 0x400A4B0
+
+#define mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_2 0x400A4B4
+
+#define mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_3 0x400A4B8
+
+#define mmDCORE0_TPC0_QM_ARB_CFG_1 0x400A4BC
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_0 0x400A4C0
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_1 0x400A4C4
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_2 0x400A4C8
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_3 0x400A4CC
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_4 0x400A4D0
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_5 0x400A4D4
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_6 0x400A4D8
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_7 0x400A4DC
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_8 0x400A4E0
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_9 0x400A4E4
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_10 0x400A4E8
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_11 0x400A4EC
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_12 0x400A4F0
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_13 0x400A4F4
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_14 0x400A4F8
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_15 0x400A4FC
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_16 0x400A500
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_17 0x400A504
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_18 0x400A508
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_19 0x400A50C
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_20 0x400A510
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_21 0x400A514
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_22 0x400A518
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_23 0x400A51C
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_24 0x400A520
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_25 0x400A524
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_26 0x400A528
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_27 0x400A52C
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_28 0x400A530
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_29 0x400A534
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_30 0x400A538
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_31 0x400A53C
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_32 0x400A540
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_33 0x400A544
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_34 0x400A548
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_35 0x400A54C
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_36 0x400A550
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_37 0x400A554
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_38 0x400A558
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_39 0x400A55C
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_40 0x400A560
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_41 0x400A564
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_42 0x400A568
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_43 0x400A56C
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_44 0x400A570
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_45 0x400A574
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_46 0x400A578
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_47 0x400A57C
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_48 0x400A580
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_49 0x400A584
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_50 0x400A588
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_51 0x400A58C
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_52 0x400A590
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_53 0x400A594
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_54 0x400A598
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_55 0x400A59C
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_56 0x400A5A0
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_57 0x400A5A4
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_58 0x400A5A8
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_59 0x400A5AC
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_60 0x400A5B0
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_61 0x400A5B4
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_62 0x400A5B8
+
+#define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_63 0x400A5BC
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CRED_INC 0x400A5E0
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_0 0x400A5E4
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_1 0x400A5E8
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_2 0x400A5EC
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_3 0x400A5F0
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_4 0x400A5F4
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_5 0x400A5F8
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_6 0x400A5FC
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_7 0x400A600
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_8 0x400A604
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_9 0x400A608
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_10 0x400A60C
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_11 0x400A610
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_12 0x400A614
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_13 0x400A618
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_14 0x400A61C
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_15 0x400A620
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_16 0x400A624
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_17 0x400A628
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_18 0x400A62C
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_19 0x400A630
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_20 0x400A634
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_21 0x400A638
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_22 0x400A63C
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_23 0x400A640
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_24 0x400A644
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_25 0x400A648
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_26 0x400A64C
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_27 0x400A650
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_28 0x400A654
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_29 0x400A658
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_30 0x400A65C
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_31 0x400A660
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_32 0x400A664
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_33 0x400A668
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_34 0x400A66C
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_35 0x400A670
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_36 0x400A674
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_37 0x400A678
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_38 0x400A67C
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_39 0x400A680
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_40 0x400A684
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_41 0x400A688
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_42 0x400A68C
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_43 0x400A690
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_44 0x400A694
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_45 0x400A698
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_46 0x400A69C
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_47 0x400A6A0
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_48 0x400A6A4
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_49 0x400A6A8
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_50 0x400A6AC
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_51 0x400A6B0
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_52 0x400A6B4
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_53 0x400A6B8
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_54 0x400A6BC
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_55 0x400A6C0
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_56 0x400A6C4
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_57 0x400A6C8
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_58 0x400A6CC
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_59 0x400A6D0
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_60 0x400A6D4
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_61 0x400A6D8
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_62 0x400A6DC
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_63 0x400A6E0
+
+#define mmDCORE0_TPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x400A704
+
+#define mmDCORE0_TPC0_QM_ARB_MST_SLAVE_EN 0x400A708
+
+#define mmDCORE0_TPC0_QM_ARB_MST_SLAVE_EN_1 0x400A70C
+
+#define mmDCORE0_TPC0_QM_ARB_SLV_CHOICE_WDT 0x400A710
+
+#define mmDCORE0_TPC0_QM_ARB_SLV_ID 0x400A714
+
+#define mmDCORE0_TPC0_QM_ARB_MST_QUIET_PER 0x400A718
+
+#define mmDCORE0_TPC0_QM_ARB_MSG_MAX_INFLIGHT 0x400A744
+
+#define mmDCORE0_TPC0_QM_ARB_BASE_LO 0x400A754
+
+#define mmDCORE0_TPC0_QM_ARB_BASE_HI 0x400A758
+
+#define mmDCORE0_TPC0_QM_ARB_STATE_STS 0x400A780
+
+#define mmDCORE0_TPC0_QM_ARB_CHOICE_FULLNESS_STS 0x400A784
+
+#define mmDCORE0_TPC0_QM_ARB_MSG_STS 0x400A788
+
+#define mmDCORE0_TPC0_QM_ARB_SLV_CHOICE_Q_HEAD 0x400A78C
+
+#define mmDCORE0_TPC0_QM_ARB_ERR_CAUSE 0x400A79C
+
+#define mmDCORE0_TPC0_QM_ARB_ERR_MSG_EN 0x400A7A0
+
+#define mmDCORE0_TPC0_QM_ARB_ERR_STS_DRP 0x400A7A8
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CRED_STS 0x400A7B0
+
+#define mmDCORE0_TPC0_QM_ARB_MST_CRED_STS_1 0x400A7B4
+
+#define mmDCORE0_TPC0_QM_CSMR_STRICT_PRIO_CFG 0x400A7FC
+
+#define mmDCORE0_TPC0_QM_ARC_CQ_CFG0 0x400A800
+
+#define mmDCORE0_TPC0_QM_ARC_CQ_CFG1 0x400A804
+
+#define mmDCORE0_TPC0_QM_ARC_CQ_PTR_LO 0x400A808
+
+#define mmDCORE0_TPC0_QM_ARC_CQ_PTR_HI 0x400A80C
+
+#define mmDCORE0_TPC0_QM_ARC_CQ_TSIZE 0x400A810
+
+#define mmDCORE0_TPC0_QM_ARC_CQ_CTL 0x400A814
+
+#define mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_STS 0x400A81C
+
+#define mmDCORE0_TPC0_QM_ARC_CQ_STS0 0x400A820
+
+#define mmDCORE0_TPC0_QM_ARC_CQ_STS1 0x400A824
+
+#define mmDCORE0_TPC0_QM_ARC_CQ_TSIZE_STS 0x400A828
+
+#define mmDCORE0_TPC0_QM_ARC_CQ_PTR_LO_STS 0x400A82C
+
+#define mmDCORE0_TPC0_QM_ARC_CQ_PTR_HI_STS 0x400A830
+
+#define mmDCORE0_TPC0_QM_CP_WR_ARC_ADDR_HI 0x400A834
+
+#define mmDCORE0_TPC0_QM_CP_WR_ARC_ADDR_LO 0x400A838
+
+#define mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_MSG_BASE_HI 0x400A83C
+
+#define mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_MSG_BASE_LO 0x400A840
+
+#define mmDCORE0_TPC0_QM_ARC_CQ_CTL_MSG_BASE_HI 0x400A844
+
+#define mmDCORE0_TPC0_QM_ARC_CQ_CTL_MSG_BASE_LO 0x400A848
+
+#define mmDCORE0_TPC0_QM_CQ_IFIFO_MSG_BASE_HI 0x400A84C
+
+#define mmDCORE0_TPC0_QM_CQ_IFIFO_MSG_BASE_LO 0x400A850
+
+#define mmDCORE0_TPC0_QM_CQ_CTL_MSG_BASE_HI 0x400A854
+
+#define mmDCORE0_TPC0_QM_CQ_CTL_MSG_BASE_LO 0x400A858
+
+#define mmDCORE0_TPC0_QM_ADDR_OVRD 0x400A85C
+
+#define mmDCORE0_TPC0_QM_CQ_IFIFO_CI_0 0x400A860
+
+#define mmDCORE0_TPC0_QM_CQ_IFIFO_CI_1 0x400A864
+
+#define mmDCORE0_TPC0_QM_CQ_IFIFO_CI_2 0x400A868
+
+#define mmDCORE0_TPC0_QM_CQ_IFIFO_CI_3 0x400A86C
+
+#define mmDCORE0_TPC0_QM_CQ_IFIFO_CI_4 0x400A870
+
+#define mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_CI 0x400A874
+
+#define mmDCORE0_TPC0_QM_CQ_CTL_CI_0 0x400A878
+
+#define mmDCORE0_TPC0_QM_CQ_CTL_CI_1 0x400A87C
+
+#define mmDCORE0_TPC0_QM_CQ_CTL_CI_2 0x400A880
+
+#define mmDCORE0_TPC0_QM_CQ_CTL_CI_3 0x400A884
+
+#define mmDCORE0_TPC0_QM_CQ_CTL_CI_4 0x400A888
+
+#define mmDCORE0_TPC0_QM_ARC_CQ_CTL_CI 0x400A88C
+
+#define mmDCORE0_TPC0_QM_CP_CFG 0x400A890
+
+#define mmDCORE0_TPC0_QM_CP_EXT_SWITCH 0x400A894
+
+#define mmDCORE0_TPC0_QM_CP_SWITCH_WD_SET 0x400A898
+
+#define mmDCORE0_TPC0_QM_CP_SWITCH_WD 0x400A89C
+
+#define mmDCORE0_TPC0_QM_ARC_LB_ADDR_BASE_LO 0x400A8A4
+
+#define mmDCORE0_TPC0_QM_ARC_LB_ADDR_BASE_HI 0x400A8A8
+
+#define mmDCORE0_TPC0_QM_ENGINE_BASE_ADDR_HI 0x400A8AC
+
+#define mmDCORE0_TPC0_QM_ENGINE_BASE_ADDR_LO 0x400A8B0
+
+#define mmDCORE0_TPC0_QM_ENGINE_ADDR_RANGE_SIZE 0x400A8B4
+
+#define mmDCORE0_TPC0_QM_QM_ARC_AUX_BASE_ADDR_HI 0x400A8B8
+
+#define mmDCORE0_TPC0_QM_QM_ARC_AUX_BASE_ADDR_LO 0x400A8BC
+
+#define mmDCORE0_TPC0_QM_QM_BASE_ADDR_HI 0x400A8C0
+
+#define mmDCORE0_TPC0_QM_QM_BASE_ADDR_LO 0x400A8C4
+
+#define mmDCORE0_TPC0_QM_ARC_PQC_SECURE_PUSH_IND 0x400A8C8
+
+#define mmDCORE0_TPC0_QM_PQC_STS_0_0 0x400A8D0
+
+#define mmDCORE0_TPC0_QM_PQC_STS_0_1 0x400A8D4
+
+#define mmDCORE0_TPC0_QM_PQC_STS_0_2 0x400A8D8
+
+#define mmDCORE0_TPC0_QM_PQC_STS_0_3 0x400A8DC
+
+#define mmDCORE0_TPC0_QM_PQC_STS_1_0 0x400A8E0
+
+#define mmDCORE0_TPC0_QM_PQC_STS_1_1 0x400A8E4
+
+#define mmDCORE0_TPC0_QM_PQC_STS_1_2 0x400A8E8
+
+#define mmDCORE0_TPC0_QM_PQC_STS_1_3 0x400A8EC
+
+#define mmDCORE0_TPC0_QM_SEI_STATUS 0x400A8F0
+
+#define mmDCORE0_TPC0_QM_SEI_MASK 0x400A8F4
+
+#define mmDCORE0_TPC0_QM_GLBL_ERR_ADDR_LO 0x400AD00
+
+#define mmDCORE0_TPC0_QM_GLBL_ERR_ADDR_HI 0x400AD04
+
+#define mmDCORE0_TPC0_QM_GLBL_ERR_WDATA 0x400AD08
+
+#define mmDCORE0_TPC0_QM_L2H_MASK_LO 0x400AD14
+
+#define mmDCORE0_TPC0_QM_L2H_MASK_HI 0x400AD18
+
+#define mmDCORE0_TPC0_QM_L2H_CMPR_LO 0x400AD1C
+
+#define mmDCORE0_TPC0_QM_L2H_CMPR_HI 0x400AD20
+
+#define mmDCORE0_TPC0_QM_LOCAL_RANGE_BASE 0x400AD24
+
+#define mmDCORE0_TPC0_QM_LOCAL_RANGE_SIZE 0x400AD28
+
+#define mmDCORE0_TPC0_QM_HBW_RD_RATE_LIM_CFG_1 0x400AD30
+
+#define mmDCORE0_TPC0_QM_LBW_WR_RATE_LIM_CFG_0 0x400AD34
+
+#define mmDCORE0_TPC0_QM_LBW_WR_RATE_LIM_CFG_1 0x400AD38
+
+#define mmDCORE0_TPC0_QM_HBW_RD_RATE_LIM_CFG_0 0x400AD3C
+
+#define mmDCORE0_TPC0_QM_IND_GW_APB_CFG 0x400AD40
+
+#define mmDCORE0_TPC0_QM_IND_GW_APB_WDATA 0x400AD44
+
+#define mmDCORE0_TPC0_QM_IND_GW_APB_RDATA 0x400AD48
+
+#define mmDCORE0_TPC0_QM_IND_GW_APB_STATUS 0x400AD4C
+
+#define mmDCORE0_TPC0_QM_PERF_CNT_FREE_LO 0x400AD60
+
+#define mmDCORE0_TPC0_QM_PERF_CNT_FREE_HI 0x400AD64
+
+#define mmDCORE0_TPC0_QM_PERF_CNT_IDLE_LO 0x400AD68
+
+#define mmDCORE0_TPC0_QM_PERF_CNT_IDLE_HI 0x400AD6C
+
+#define mmDCORE0_TPC0_QM_PERF_CNT_CFG 0x400AD70
+
+#endif /* ASIC_REG_DCORE0_TPC0_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_dec_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_dec_regs.h
new file mode 100644
index 000000000000..e68667cc795a
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_dec_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_REGS_H_
+#define ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC
+ *   (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_ASID 0x41E3C00
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_MMU_BP 0x41E3C04
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_STRONG_ORDER 0x41E3C08
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_NO_SNOOP 0x41E3C0C
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_WR_REDUCTION 0x41E3C10
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_RD_ATOMIC 0x41E3C14
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_QOS 0x41E3C18
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_RSVD 0x41E3C1C
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_EMEM_CPAGE 0x41E3C20
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_CORE 0x41E3C24
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_E2E_COORD 0x41E3C28
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_WR_OVRD_LO 0x41E3C30
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_WR_OVRD_HI 0x41E3C34
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_RD_OVRD_LO 0x41E3C38
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_RD_OVRD_HI 0x41E3C3C
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_LB_COORD 0x41E3C40
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_LB_LOCK 0x41E3C44
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_LB_RSVD 0x41E3C48
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_LB_OVRD 0x41E3C4C
+
+#endif /* ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h
new file mode 100644
index 000000000000..f7ffdcbd1a76
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_REGS_H_
+#define ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM
+ *   (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_ASID 0x41E3B00
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_MMU_BP 0x41E3B04
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_STRONG_ORDER 0x41E3B08
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_NO_SNOOP 0x41E3B0C
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_WR_REDUCTION 0x41E3B10
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_RD_ATOMIC 0x41E3B14
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_QOS 0x41E3B18
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_RSVD 0x41E3B1C
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_EMEM_CPAGE 0x41E3B20
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_CORE 0x41E3B24
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_E2E_COORD 0x41E3B28
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_WR_OVRD_LO 0x41E3B30
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_WR_OVRD_HI 0x41E3B34
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_RD_OVRD_LO 0x41E3B38
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_RD_OVRD_HI 0x41E3B3C
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_LB_COORD 0x41E3B40
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_LB_LOCK 0x41E3B44
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_LB_RSVD 0x41E3B48
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_LB_OVRD 0x41E3B4C
+
+#endif /* ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h
new file mode 100644
index 000000000000..4c1bb5306cba
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_REGS_H_
+#define ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C
+ *   (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_ASID 0x41E3900
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_MMU_BP 0x41E3904
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_STRONG_ORDER 0x41E3908
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_NO_SNOOP 0x41E390C
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_WR_REDUCTION 0x41E3910
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_RD_ATOMIC 0x41E3914
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_QOS 0x41E3918
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_RSVD 0x41E391C
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_EMEM_CPAGE 0x41E3920
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_CORE 0x41E3924
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_E2E_COORD 0x41E3928
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_WR_OVRD_LO 0x41E3930
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_WR_OVRD_HI 0x41E3934
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_RD_OVRD_LO 0x41E3938
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_RD_OVRD_HI 0x41E393C
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_LB_COORD 0x41E3940
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_LB_LOCK 0x41E3944
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_LB_RSVD 0x41E3948
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_LB_OVRD 0x41E394C
+
+#endif /* ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h
new file mode 100644
index 000000000000..e413905ffe25
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_REGS_H_
+#define ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM
+ *   (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_ASID 0x41E3A00
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_MMU_BP 0x41E3A04
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_STRONG_ORDER 0x41E3A08
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_NO_SNOOP 0x41E3A0C
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_WR_REDUCTION 0x41E3A10
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_RD_ATOMIC 0x41E3A14
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_QOS 0x41E3A18
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_RSVD 0x41E3A1C
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_EMEM_CPAGE 0x41E3A20
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_CORE 0x41E3A24
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_E2E_COORD 0x41E3A28
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_WR_OVRD_LO 0x41E3A30
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_WR_OVRD_HI 0x41E3A34
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_RD_OVRD_LO 0x41E3A38
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_RD_OVRD_HI 0x41E3A3C
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_LB_COORD 0x41E3A40
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_LB_LOCK 0x41E3A44
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_LB_RSVD 0x41E3A48
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_LB_OVRD 0x41E3A4C
+
+#endif /* ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h
new file mode 100644
index 000000000000..bce75ac6e279
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_REGS_H_
+#define ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD
+ *   (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_ASID 0x41E3800
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_MMU_BP 0x41E3804
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_STRONG_ORDER 0x41E3808
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_NO_SNOOP 0x41E380C
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_WR_REDUCTION 0x41E3810
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_RD_ATOMIC 0x41E3814
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_QOS 0x41E3818
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_RSVD 0x41E381C
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_EMEM_CPAGE 0x41E3820
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_CORE 0x41E3824
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_E2E_COORD 0x41E3828
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_WR_OVRD_LO 0x41E3830
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_WR_OVRD_HI 0x41E3834
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_RD_OVRD_LO 0x41E3838
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_RD_OVRD_HI 0x41E383C
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_LB_COORD 0x41E3840
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_LB_LOCK 0x41E3844
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_LB_RSVD 0x41E3848
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_LB_OVRD 0x41E384C
+
+#endif /* ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_masks.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_masks.h
new file mode 100644
index 000000000000..1c02f3dfdb6e
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_masks.h
@@ -0,0 +1,579 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_MASKS_H_
+#define ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_MASKS_H_
+
+/*
+ *****************************************
+ *   DCORE0_VDEC0_BRDG_CTRL
+ *   (Prototype: VDEC_BRDG_CTRL)
+ *****************************************
+ */
+
+/* DCORE0_VDEC0_BRDG_CTRL_CGM_DISABLE */
+#define DCORE0_VDEC0_BRDG_CTRL_CGM_DISABLE_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_CGM_DISABLE_VAL_MASK 0x1
+
+/* DCORE0_VDEC0_BRDG_CTRL_IDLE_MASK */
+#define DCORE0_VDEC0_BRDG_CTRL_IDLE_MASK_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_IDLE_MASK_VAL_MASK 0x7
+
+/* DCORE0_VDEC0_BRDG_CTRL_APB_CGM_CNT */
+#define DCORE0_VDEC0_BRDG_CTRL_APB_CGM_CNT_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_APB_CGM_CNT_VAL_MASK 0xFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT */
+#define DCORE0_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT_VAL_MASK 0xFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_GRACEFUL */
+#define DCORE0_VDEC0_BRDG_CTRL_GRACEFUL_STOP_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_GRACEFUL_STOP_MASK 0x1
+#define DCORE0_VDEC0_BRDG_CTRL_GRACEFUL_PEND_SHIFT 4
+#define DCORE0_VDEC0_BRDG_CTRL_GRACEFUL_PEND_MASK 0x10
+
+/* DCORE0_VDEC0_BRDG_CTRL_IDLE_CGM_CNT */
+#define DCORE0_VDEC0_BRDG_CTRL_IDLE_CGM_CNT_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_IDLE_CGM_CNT_VAL_MASK 0xFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR */
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_VCD_HBW_SEI_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_VCD_HBW_SEI_MASK 0x1
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_L2C_HBW_SEI_SHIFT 1
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_L2C_HBW_SEI_MASK 0x2
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_NRM_HBW_SEI_SHIFT 2
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_NRM_HBW_SEI_MASK 0x4
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_ABNRM_HBW_SEI_SHIFT 3
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_ABNRM_HBW_SEI_MASK 0x8
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_VCD_LBW_SEI_SHIFT 4
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_VCD_LBW_SEI_MASK 0x10
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_L2C_LBW_SEI_SHIFT 5
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_L2C_LBW_SEI_MASK 0x20
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_NRM_LBW_SEI_SHIFT 6
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_NRM_LBW_SEI_MASK 0x40
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_ABNRM_LBW_SEI_SHIFT 7
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_ABNRM_LBW_SEI_MASK 0x80
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_VCD_LBW_SEI_SHIFT 8
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_VCD_LBW_SEI_MASK 0x100
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_L2C_LBW_SEI_SHIFT 9
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_L2C_LBW_SEI_MASK 0x200
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_NRM_LBW_SEI_SHIFT 10
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_NRM_LBW_SEI_MASK 0x400
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_ABNRM_LBW_SEI_SHIFT 11
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_ABNRM_LBW_SEI_MASK 0x800
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_DEC_SEI_SHIFT 12
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_DEC_SEI_MASK 0x1000
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_DEC_APB_SEI_SHIFT 13
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_DEC_APB_SEI_MASK 0x2000
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_TRC_APB_SEI_SHIFT 14
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_TRC_APB_SEI_MASK 0x4000
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_MSTR_IF_SEI_SHIFT 15
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_MSTR_IF_SEI_MASK 0x8000
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_AXI_SPLIT_BRESP_ERR_SEI_SHIFT 16
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_AXI_SPLIT_BRESP_ERR_SEI_MASK 0x10000
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_HBW_AXI_WR_VIOL_SEI_SHIFT 17
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_HBW_AXI_WR_VIOL_SEI_MASK 0x20000
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_HBW_AXI_RD_VIOL_SEI_SHIFT 18
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_HBW_AXI_RD_VIOL_SEI_MASK 0x40000
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_AXI_WR_VIOL_SEI_SHIFT 19
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_AXI_WR_VIOL_SEI_MASK 0x80000
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_AXI_RD_VIOL_SEI_SHIFT 20
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_AXI_RD_VIOL_SEI_MASK 0x100000
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_VCD_SPI_SHIFT 21
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_VCD_SPI_MASK 0x200000
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_L2C_SPI_SHIFT 22
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_L2C_SPI_MASK 0x400000
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_NRM_SPI_SHIFT 23
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_NRM_SPI_MASK 0x800000
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_ABNRM_SPI_SHIFT 24
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_ABNRM_SPI_MASK 0x1000000
+
+/* DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE */
+#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWLEN_GT_31_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWLEN_GT_31_MASK 0x1
+#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWLOCK_VIOL_SHIFT 1
+#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWLOCK_VIOL_MASK 0x2
+#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWBURST_VIOL_SHIFT 2
+#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWBURST_VIOL_MASK 0x4
+#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWADDR_SIZE_ALIGN_VIOL_SHIFT 3
+#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWADDR_SIZE_ALIGN_VIOL_MASK 0x8
+#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWSIZE_VIOL_SHIFT 4
+#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWSIZE_VIOL_MASK 0x10
+#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARLEN_GT_31_SHIFT 5
+#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARLEN_GT_31_MASK 0x20
+#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARLOCK_VIOL_SHIFT 6
+#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARLOCK_VIOL_MASK 0x40
+#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARBURST_VIOL_SHIFT 7
+#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARBURST_VIOL_MASK 0x80
+#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARADDR_SIZE_ALIGN_VIOL_SHIFT 8
+#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARADDR_SIZE_ALIGN_VIOL_MASK 0x100
+#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARSIZE_VIOL_SHIFT 9
+#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARSIZE_VIOL_MASK 0x200
+
+/* DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE */
+#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_READ_ACCESS_VIOL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_READ_ACCESS_VIOL_MASK 0x1
+#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWLOCK_VIOL_SHIFT 1
+#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWLOCK_VIOL_MASK 0x2
+#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWADDR_ALIGN_VIOL_SHIFT 2
+#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWADDR_ALIGN_VIOL_MASK 0x4
+#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWSIZE_VIOL_SHIFT 3
+#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWSIZE_VIOL_MASK 0x8
+#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWLEN_VIOL_SHIFT 4
+#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWLEN_VIOL_MASK 0x10
+#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_WSTRB_VIOL_SHIFT 5
+#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_WSTRB_VIOL_MASK 0x20
+
+/* DCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM */
+#define DCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_HBW_AW_VIOL_CLR_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_HBW_AW_VIOL_CLR_MASK 0x1
+#define DCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_HBW_AR_VIOL_CLR_SHIFT 1
+#define DCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_HBW_AR_VIOL_CLR_MASK 0x2
+#define DCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_LBW_AW_VIOL_CLR_SHIFT 2
+#define DCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_LBW_AW_VIOL_CLR_MASK 0x4
+
+/* DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MASK */
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MASK_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MASK_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_MASK */
+#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_MASK_MASK_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_MASK_MASK_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_MASK */
+#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_MASK_MASK_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_MASK_MASK_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_VCD_GIC_INTR_MASK */
+#define DCORE0_VDEC0_BRDG_CTRL_VCD_GIC_INTR_MASK_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_VCD_GIC_INTR_MASK_VAL_MASK 0x1
+
+/* DCORE0_VDEC0_BRDG_CTRL_L2C_GIC_INTR_MASK */
+#define DCORE0_VDEC0_BRDG_CTRL_L2C_GIC_INTR_MASK_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_L2C_GIC_INTR_MASK_VAL_MASK 0x1
+
+/* DCORE0_VDEC0_BRDG_CTRL_NRM_GIC_INTR_MASK */
+#define DCORE0_VDEC0_BRDG_CTRL_NRM_GIC_INTR_MASK_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_NRM_GIC_INTR_MASK_VAL_MASK 0x1
+
+/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_GIC_INTR_MASK */
+#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_GIC_INTR_MASK_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_GIC_INTR_MASK_VAL_MASK 0x1
+
+/* DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_AWPROT */
+#define DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_AWPROT_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_AWPROT_VAL_MASK 0x7
+
+/* DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_ARPROT */
+#define DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_ARPROT_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_ARPROT_VAL_MASK 0x7
+
+/* DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_AWPROT */
+#define DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_AWPROT_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_AWPROT_VAL_MASK 0x7
+
+/* DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_ARPROT */
+#define DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_ARPROT_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_ARPROT_VAL_MASK 0x7
+
+/* DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_AWPROT */
+#define DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_AWPROT_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_AWPROT_VAL_MASK 0x7
+
+/* DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_ARPROT */
+#define DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_ARPROT_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_ARPROT_VAL_MASK 0x7
+
+/* DCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE */
+#define DCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_HBW_LEGAL_AWSIZE_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_HBW_LEGAL_AWSIZE_MASK 0x7
+#define DCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_HBW_LEGAL_ARSIZE_SHIFT 3
+#define DCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_HBW_LEGAL_ARSIZE_MASK 0x38
+#define DCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_LBW_LEGAL_AWSIZE_SHIFT 6
+#define DCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_LBW_LEGAL_AWSIZE_MASK 0x1C0
+
+/* DCORE0_VDEC0_BRDG_CTRL_ARC_MSG_MASK */
+#define DCORE0_VDEC0_BRDG_CTRL_ARC_MSG_MASK_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_ARC_MSG_MASK_VAL_MASK 0x1
+
+/* DCORE0_VDEC0_BRDG_CTRL_ARC_START_LBW_WDATA */
+#define DCORE0_VDEC0_BRDG_CTRL_ARC_START_LBW_WDATA_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_ARC_START_LBW_WDATA_VAL_MASK 0xFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_ARC_FINISH_LBW_WDATA */
+#define DCORE0_VDEC0_BRDG_CTRL_ARC_FINISH_LBW_WDATA_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_ARC_FINISH_LBW_WDATA_VAL_MASK 0xFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_SEL */
+#define DCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_SEL_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_SEL_VAL_MASK 0x7
+
+/* DCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_ADDR */
+#define DCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_ADDR_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_ADDR_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_L */
+#define DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_L_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_L_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_H */
+#define DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_H_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_H_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_L */
+#define DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_L_IND_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_L_IND_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_H */
+#define DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_H_IND_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_H_IND_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_L */
+#define DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_L_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_L_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_H */
+#define DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_H_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_H_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_L */
+#define DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_L_IND_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_L_IND_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_H */
+#define DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_H_IND_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_H_IND_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_STAT_CNTR_EN */
+#define DCORE0_VDEC0_BRDG_CTRL_STAT_CNTR_EN_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_STAT_CNTR_EN_VAL_MASK 0x1
+
+/* DCORE0_VDEC0_BRDG_CTRL_VCD_INTR_MASK */
+#define DCORE0_VDEC0_BRDG_CTRL_VCD_INTR_MASK_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_VCD_INTR_MASK_VAL_MASK 0x1
+
+/* DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK */
+#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_APB_WR_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_APB_WR_MASK 0x1
+#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_APB_RD_SHIFT 1
+#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_APB_RD_MASK 0x2
+#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_LBW_SHIFT 2
+#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_LBW_MASK 0x4
+
+/* DCORE0_VDEC0_BRDG_CTRL_VCD_WAIT_CNTR */
+#define DCORE0_VDEC0_BRDG_CTRL_VCD_WAIT_CNTR_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_VCD_WAIT_CNTR_VAL_MASK 0xFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_WAIT_CNTR */
+#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_WAIT_CNTR_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_STAT_VCD_WAIT_CNTR */
+#define DCORE0_VDEC0_BRDG_CTRL_STAT_VCD_WAIT_CNTR_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_STAT_VCD_WAIT_CNTR_VAL_MASK 0xFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_STAT_VCD_MSIX_WAIT_CNTR */
+#define DCORE0_VDEC0_BRDG_CTRL_STAT_VCD_MSIX_WAIT_CNTR_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_STAT_VCD_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_VCD_SWREG1_ADDR */
+#define DCORE0_VDEC0_BRDG_CTRL_VCD_SWREG1_ADDR_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_VCD_SWREG1_ADDR_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_ADDR */
+#define DCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_ADDR_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_ADDR_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_DATA */
+#define DCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_DATA_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_DATA_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWPROT */
+#define DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWPROT_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWPROT_VAL_MASK 0x7
+
+/* DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_L */
+#define DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_L_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_L_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_H */
+#define DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_H_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_H_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWPROT */
+#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWPROT_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWPROT_VAL_MASK 0x7
+
+/* DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWADDR */
+#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWADDR_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWADDR_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_WDATA */
+#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_WDATA_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_WDATA_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_L2C_INTR_MASK */
+#define DCORE0_VDEC0_BRDG_CTRL_L2C_INTR_MASK_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_L2C_INTR_MASK_VAL_MASK 0x1
+
+/* DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK */
+#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_APB_WR_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_APB_WR_MASK 0x1
+#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_APB_RD_SHIFT 1
+#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_APB_RD_MASK 0x2
+#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_LBW_SHIFT 2
+#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_LBW_MASK 0x4
+
+/* DCORE0_VDEC0_BRDG_CTRL_L2C_WAIT_CNTR */
+#define DCORE0_VDEC0_BRDG_CTRL_L2C_WAIT_CNTR_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_L2C_WAIT_CNTR_VAL_MASK 0xFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_WAIT_CNTR */
+#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_WAIT_CNTR_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_STAT_L2C_WAIT_CNTR */
+#define DCORE0_VDEC0_BRDG_CTRL_STAT_L2C_WAIT_CNTR_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_STAT_L2C_WAIT_CNTR_VAL_MASK 0xFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_STAT_L2C_MSIX_WAIT_CNTR */
+#define DCORE0_VDEC0_BRDG_CTRL_STAT_L2C_MSIX_WAIT_CNTR_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_STAT_L2C_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_L2C_SWREG1_ADDR */
+#define DCORE0_VDEC0_BRDG_CTRL_L2C_SWREG1_ADDR_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_L2C_SWREG1_ADDR_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_ADDR */
+#define DCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_ADDR_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_ADDR_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_DATA */
+#define DCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_DATA_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_DATA_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWPROT */
+#define DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWPROT_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWPROT_VAL_MASK 0x7
+
+/* DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_L */
+#define DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_L_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_L_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_H */
+#define DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_H_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_H_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWPROT */
+#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWPROT_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWPROT_VAL_MASK 0x7
+
+/* DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWADDR */
+#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWADDR_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWADDR_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_WDATA */
+#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_WDATA_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_WDATA_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_NRM_INTR_MASK */
+#define DCORE0_VDEC0_BRDG_CTRL_NRM_INTR_MASK_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_NRM_INTR_MASK_VAL_MASK 0x1
+
+/* DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK */
+#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_APB_WR_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_APB_WR_MASK 0x1
+#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_APB_RD_SHIFT 1
+#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_APB_RD_MASK 0x2
+#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_LBW_SHIFT 2
+#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_LBW_MASK 0x4
+
+/* DCORE0_VDEC0_BRDG_CTRL_NRM_WAIT_CNTR */
+#define DCORE0_VDEC0_BRDG_CTRL_NRM_WAIT_CNTR_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_NRM_WAIT_CNTR_VAL_MASK 0xFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_WAIT_CNTR */
+#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_WAIT_CNTR_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_STAT_NRM_WAIT_CNTR */
+#define DCORE0_VDEC0_BRDG_CTRL_STAT_NRM_WAIT_CNTR_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_STAT_NRM_WAIT_CNTR_VAL_MASK 0xFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_STAT_NRM_MSIX_WAIT_CNTR */
+#define DCORE0_VDEC0_BRDG_CTRL_STAT_NRM_MSIX_WAIT_CNTR_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_STAT_NRM_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_NRM_SWREG1_ADDR */
+#define DCORE0_VDEC0_BRDG_CTRL_NRM_SWREG1_ADDR_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_NRM_SWREG1_ADDR_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_ADDR */
+#define DCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_ADDR_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_ADDR_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_DATA */
+#define DCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_DATA_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_DATA_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWPROT */
+#define DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWPROT_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWPROT_VAL_MASK 0x7
+
+/* DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_L */
+#define DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_L_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_L_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_H */
+#define DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_H_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_H_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWPROT */
+#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWPROT_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWPROT_VAL_MASK 0x7
+
+/* DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR */
+#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA */
+#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_INTR_MASK */
+#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_INTR_MASK_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_INTR_MASK_VAL_MASK 0x1
+
+/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK */
+#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_APB_WR_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_APB_WR_MASK 0x1
+#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_APB_RD_SHIFT 1
+#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_APB_RD_MASK 0x2
+#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_LBW_SHIFT 2
+#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_LBW_MASK 0x4
+
+/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_WAIT_CNTR */
+#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_WAIT_CNTR_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_WAIT_CNTR_VAL_MASK 0xFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_WAIT_CNTR */
+#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_WAIT_CNTR_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_WAIT_CNTR */
+#define DCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_WAIT_CNTR_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_WAIT_CNTR_VAL_MASK 0xFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_MSIX_WAIT_CNTR */
+#define DCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_MSIX_WAIT_CNTR_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_SWREG1_ADDR */
+#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_SWREG1_ADDR_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_SWREG1_ADDR_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_ADDR */
+#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_ADDR_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_ADDR_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_DATA */
+#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_DATA_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_DATA_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWPROT */
+#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWPROT_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWPROT_VAL_MASK 0x7
+
+/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_L */
+#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_L_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_L_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_H */
+#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_H_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_H_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWPROT */
+#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWPROT_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWPROT_VAL_MASK 0x7
+
+/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR */
+#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA */
+#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_BRESP_ERR_ID */
+#define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_BRESP_ERR_ID_ID_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_BRESP_ERR_ID_ID_MASK 0xFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG */
+#define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_FORCE_RESP_OK_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_FORCE_RESP_OK_MASK 0x1
+#define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_FORCE_WR_BUF_SHIFT 1
+#define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_FORCE_WR_BUF_MASK 0x2
+#define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_NUM_RD_OS_SHIFT 8
+#define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_NUM_RD_OS_MASK 0xFF00
+#define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_NUM_WR_OS_SHIFT 16
+#define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_NUM_WR_OS_MASK 0xFF0000
+
+/* DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_NO_WR_INFLIGHT */
+#define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_NO_WR_INFLIGHT_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_NO_WR_INFLIGHT_VAL_MASK 0x1
+
+/* DCORE0_VDEC0_BRDG_CTRL_HWEVENT_MASK */
+#define DCORE0_VDEC0_BRDG_CTRL_HWEVENT_MASK_MASK_SHIFT 1
+#define DCORE0_VDEC0_BRDG_CTRL_HWEVENT_MASK_MASK_MASK 0x2
+
+/* DCORE0_VDEC0_BRDG_CTRL_HWEVENT_CNTXT */
+#define DCORE0_VDEC0_BRDG_CTRL_HWEVENT_CNTXT_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_HWEVENT_CNTXT_VAL_MASK 0xFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_LBW_SLV_TERM_ERR_RESP */
+#define DCORE0_VDEC0_BRDG_CTRL_LBW_SLV_TERM_ERR_RESP_ERR_RESP_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_LBW_SLV_TERM_ERR_RESP_ERR_RESP_MASK 0x3
+
+/* DCORE0_VDEC0_BRDG_CTRL_LBW_MSTR_TERM_ERR_RESP */
+#define DCORE0_VDEC0_BRDG_CTRL_LBW_MSTR_TERM_ERR_RESP_ERR_RESP_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_LBW_MSTR_TERM_ERR_RESP_ERR_RESP_MASK 0x3
+
+/* DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP */
+#define DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP_WR_ERR_RESP_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP_WR_ERR_RESP_MASK 0x3
+#define DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP_RD_ERR_RESP_SHIFT 2
+#define DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP_RD_ERR_RESP_MASK 0xC
+
+/* DCORE0_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS */
+#define DCORE0_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS_AW_STA_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS_AW_STA_MASK 0x1
+#define DCORE0_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS_AR_STA_SHIFT 1
+#define DCORE0_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS_AR_STA_MASK 0x2
+
+/* DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_L */
+#define DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_L_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_L_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_H */
+#define DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_H_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_H_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_L */
+#define DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_L_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_L_VAL_MASK 0xFFFFFFFF
+
+/* DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_H */
+#define DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_H_VAL_SHIFT 0
+#define DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_H_VAL_MASK 0xFFFFFFFF
+
+#endif /* ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_regs.h
new file mode 100644
index 000000000000..d2844307a6bf
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_regs.h
@@ -0,0 +1,245 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_REGS_H_
+#define ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_VDEC0_BRDG_CTRL
+ *   (Prototype: VDEC_BRDG_CTRL)
+ *****************************************
+ */
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_CGM_DISABLE 0x41E3100
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_IDLE_MASK 0x41E3104
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_APB_CGM_CNT 0x41E3108
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT 0x41E310C
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_GRACEFUL 0x41E3110
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_IDLE_CGM_CNT 0x41E3114
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR 0x41E3120
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE 0x41E3124
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE 0x41E3128
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM 0x41E312C
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MASK 0x41E3130
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_MASK 0x41E3134
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_MASK 0x41E3138
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_GIC_INTR_MASK 0x41E3160
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_GIC_INTR_MASK 0x41E3170
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_GIC_INTR_MASK 0x41E3180
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_GIC_INTR_MASK 0x41E3190
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_HBW_AWPROT 0x41E31A0
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_HBW_ARPROT 0x41E31A4
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_LBW_AWPROT 0x41E31B0
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_LBW_ARPROT 0x41E31B4
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_AWPROT 0x41E31C0
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_ARPROT 0x41E31C4
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE 0x41E31D0
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_ARC_MSG_MASK 0x41E3200
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_ARC_START_LBW_WDATA 0x41E3230
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_ARC_FINISH_LBW_WDATA 0x41E3260
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_SEL 0x41E3270
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_ADDR 0x41E3280
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_L 0x41E3290
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_H 0x41E3294
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_L 0x41E32A0
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_H 0x41E32A4
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_L 0x41E32B0
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_H 0x41E32B4
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_L 0x41E32C0
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_H 0x41E32C4
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_STAT_CNTR_EN 0x41E32D0
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_INTR_MASK 0x41E3300
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK 0x41E3310
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_WAIT_CNTR 0x41E3320
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_WAIT_CNTR 0x41E3330
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_STAT_VCD_WAIT_CNTR 0x41E3334
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_STAT_VCD_MSIX_WAIT_CNTR 0x41E3338
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_SWREG1_ADDR 0x41E3340
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_ADDR 0x41E3350
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_DATA 0x41E3360
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWPROT 0x41E3380
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_L 0x41E3390
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_H 0x41E3394
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWPROT 0x41E33C0
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWADDR 0x41E33D0
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_WDATA 0x41E33E0
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_INTR_MASK 0x41E3400
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK 0x41E3410
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_WAIT_CNTR 0x41E3420
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_WAIT_CNTR 0x41E3430
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_STAT_L2C_WAIT_CNTR 0x41E3434
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_STAT_L2C_MSIX_WAIT_CNTR 0x41E3438
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_SWREG1_ADDR 0x41E3440
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_ADDR 0x41E3450
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_DATA 0x41E3460
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWPROT 0x41E3480
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_L 0x41E3490
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_H 0x41E3494
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWPROT 0x41E34C0
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWADDR 0x41E34D0
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_WDATA 0x41E34E0
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_INTR_MASK 0x41E3500
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK 0x41E3510
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_WAIT_CNTR 0x41E3520
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_WAIT_CNTR 0x41E3530
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_STAT_NRM_WAIT_CNTR 0x41E3534
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_STAT_NRM_MSIX_WAIT_CNTR 0x41E3538
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_SWREG1_ADDR 0x41E3540
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_ADDR 0x41E3550
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_DATA 0x41E3560
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWPROT 0x41E3580
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_L 0x41E3590
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_H 0x41E3594
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWPROT 0x41E35C0
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR 0x41E35D0
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA 0x41E35E0
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_INTR_MASK 0x41E3600
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK 0x41E3610
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_WAIT_CNTR 0x41E3620
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_WAIT_CNTR 0x41E3630
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_WAIT_CNTR 0x41E3634
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_MSIX_WAIT_CNTR 0x41E3638
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_SWREG1_ADDR 0x41E3640
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_ADDR 0x41E3650
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_DATA 0x41E3660
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWPROT 0x41E3680
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_L 0x41E3690
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_H 0x41E3694
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWPROT 0x41E36C0
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR 0x41E36D0
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA 0x41E36E0
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_BRESP_ERR_ID 0x41E3700
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG 0x41E3704
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_NO_WR_INFLIGHT 0x41E3708
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_HWEVENT_MASK 0x41E370C
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_HWEVENT_CNTXT 0x41E3714
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_LBW_SLV_TERM_ERR_RESP 0x41E3718
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_LBW_MSTR_TERM_ERR_RESP 0x41E371C
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP 0x41E3720
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS 0x41E3724
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_L 0x41E3728
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_H 0x41E372C
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_L 0x41E3730
+
+#define mmDCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_H 0x41E3734
+
+#endif /* ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_ctrl_special_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_ctrl_special_regs.h
new file mode 100644
index 000000000000..89b522b12998
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_ctrl_special_regs.h
@@ -0,0 +1,185 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_VDEC0_CTRL_SPECIAL_REGS_H_
+#define ASIC_REG_DCORE0_VDEC0_CTRL_SPECIAL_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_VDEC0_CTRL_SPECIAL
+ *   (Prototype: SPECIAL_REGS)
+ *****************************************
+ */
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_0 0x41E4E80
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_1 0x41E4E84
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_2 0x41E4E88
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_3 0x41E4E8C
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_4 0x41E4E90
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_5 0x41E4E94
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_6 0x41E4E98
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_7 0x41E4E9C
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_8 0x41E4EA0
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_9 0x41E4EA4
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_10 0x41E4EA8
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_11 0x41E4EAC
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_12 0x41E4EB0
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_13 0x41E4EB4
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_14 0x41E4EB8
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_15 0x41E4EBC
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_16 0x41E4EC0
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_17 0x41E4EC4
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_18 0x41E4EC8
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_19 0x41E4ECC
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_20 0x41E4ED0
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_21 0x41E4ED4
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_22 0x41E4ED8
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_23 0x41E4EDC
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_24 0x41E4EE0
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_25 0x41E4EE4
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_26 0x41E4EE8
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_27 0x41E4EEC
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_28 0x41E4EF0
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_29 0x41E4EF4
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_30 0x41E4EF8
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_PRIV_31 0x41E4EFC
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_MEM_GW_DATA 0x41E4F00
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_MEM_GW_REQ 0x41E4F04
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_MEM_NUMOF 0x41E4F0C
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_MEM_ECC_SEL 0x41E4F10
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_MEM_ECC_CTL 0x41E4F14
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_MEM_ECC_ERR_MASK 0x41E4F18
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_MEM_ECC_GLBL_ERR_MASK 0x41E4F1C
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_MEM_ECC_ERR_STS 0x41E4F20
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_MEM_ECC_ERR_ADDR 0x41E4F24
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_MEM_RM 0x41E4F28
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_ERR_MASK 0x41E4F40
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_ERR_ADDR 0x41E4F44
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_ERR_CAUSE 0x41E4F48
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SPARE_0 0x41E4F60
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SPARE_1 0x41E4F64
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SPARE_2 0x41E4F68
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SPARE_3 0x41E4F6C
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_0 0x41E4F80
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_1 0x41E4F84
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_2 0x41E4F88
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_3 0x41E4F8C
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_4 0x41E4F90
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_5 0x41E4F94
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_6 0x41E4F98
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_7 0x41E4F9C
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_8 0x41E4FA0
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_9 0x41E4FA4
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_10 0x41E4FA8
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_11 0x41E4FAC
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_12 0x41E4FB0
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_13 0x41E4FB4
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_14 0x41E4FB8
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_15 0x41E4FBC
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_16 0x41E4FC0
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_17 0x41E4FC4
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_18 0x41E4FC8
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_19 0x41E4FCC
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_20 0x41E4FD0
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_21 0x41E4FD4
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_22 0x41E4FD8
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_23 0x41E4FDC
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_24 0x41E4FE0
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_25 0x41E4FE4
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_26 0x41E4FE8
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_27 0x41E4FEC
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_28 0x41E4FF0
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_29 0x41E4FF4
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_30 0x41E4FF8
+
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_GLBL_SEC_31 0x41E4FFC
+
+#endif /* ASIC_REG_DCORE0_VDEC0_CTRL_SPECIAL_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore1_mme_ctrl_lo_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore1_mme_ctrl_lo_regs.h
new file mode 100644
index 000000000000..622613dc76fb
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore1_mme_ctrl_lo_regs.h
@@ -0,0 +1,163 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE1_MME_CTRL_LO_REGS_H_
+#define ASIC_REG_DCORE1_MME_CTRL_LO_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE1_MME_CTRL_LO
+ *   (Prototype: MME_CTRL_LO)
+ *****************************************
+ */
+
+#define mmDCORE1_MME_CTRL_LO_ARCH_STATUS 0x42CB000
+
+#define mmDCORE1_MME_CTRL_LO_CMD 0x42CB004
+
+#define mmDCORE1_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0 0x42CB148
+
+#define mmDCORE1_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0 0x42CB14C
+
+#define mmDCORE1_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0 0x42CB150
+
+#define mmDCORE1_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1 0x42CB154
+
+#define mmDCORE1_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1 0x42CB158
+
+#define mmDCORE1_MME_CTRL_LO_ARCH_A_SS 0x42CB224
+
+#define mmDCORE1_MME_CTRL_LO_ARCH_B_SS 0x42CB228
+
+#define mmDCORE1_MME_CTRL_LO_ARCH_COUT_SS 0x42CB27C
+
+#define mmDCORE1_MME_CTRL_LO_QM_STALL 0x42CB400
+
+#define mmDCORE1_MME_CTRL_LO_LOG_SHADOW_LO 0x42CB404
+
+#define mmDCORE1_MME_CTRL_LO_LOG_SHADOW_HI 0x42CB408
+
+#define mmDCORE1_MME_CTRL_LO_SYNC_OBJECT_FIFO_TH 0x42CB40C
+
+#define mmDCORE1_MME_CTRL_LO_REDUN 0x42CB410
+
+#define mmDCORE1_MME_CTRL_LO_EUS_LOCAL_FIFO_TH 0x42CB414
+
+#define mmDCORE1_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0 0x42CB418
+
+#define mmDCORE1_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1 0x42CB41C
+
+#define mmDCORE1_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16 0x42CB420
+
+#define mmDCORE1_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8 0x42CB424
+
+#define mmDCORE1_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32 0x42CB428
+
+#define mmDCORE1_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I 0x42CB42C
+
+#define mmDCORE1_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32 0x42CB430
+
+#define mmDCORE1_MME_CTRL_LO_PCU_RL_DESC0 0x42CB434
+
+#define mmDCORE1_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE 0x42CB438
+
+#define mmDCORE1_MME_CTRL_LO_PCU_RL_TH 0x42CB43C
+
+#define mmDCORE1_MME_CTRL_LO_PCU_RL_MIN 0x42CB440
+
+#define mmDCORE1_MME_CTRL_LO_PCU_RL_CTRL_EN 0x42CB444
+
+#define mmDCORE1_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE 0x42CB448
+
+#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_A_BF16 0x42CB44C
+
+#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_B_BF16 0x42CB450
+
+#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_A_FP16 0x42CB454
+
+#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_B_FP16 0x42CB458
+
+#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_F8 0x42CB45C
+
+#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_A_FP32_ODD 0x42CB460
+
+#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_A_FP32_EVEN 0x42CB464
+
+#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_B_FP32_ODD 0x42CB468
+
+#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_B_FP32_EVEN 0x42CB46C
+
+#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_A_TF32_ODD 0x42CB470
+
+#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_A_TF32_EVEN 0x42CB474
+
+#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_B_TF32_ODD 0x42CB478
+
+#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_B_TF32_EVEN 0x42CB47C
+
+#define mmDCORE1_MME_CTRL_LO_PROT 0x42CB480
+
+#define mmDCORE1_MME_CTRL_LO_EU 0x42CB484
+
+#define mmDCORE1_MME_CTRL_LO_SBTE 0x42CB488
+
+#define mmDCORE1_MME_CTRL_LO_AGU_SM_INFLIGHT_CNTR 0x42CB48C
+
+#define mmDCORE1_MME_CTRL_LO_AGU_SM_TOTAL_CNTR 0x42CB490
+
+#define mmDCORE1_MME_CTRL_LO_PCU_RL_SAT_SEC 0x42CB494
+
+#define mmDCORE1_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN32 0x42CB498
+
+#define mmDCORE1_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN33 0x42CB49C
+
+#define mmDCORE1_MME_CTRL_LO_EU_ISOLATION_DIS 0x42CB4A0
+
+#define mmDCORE1_MME_CTRL_LO_QM_SLV_CLK_EN 0x42CB4A4
+
+#define mmDCORE1_MME_CTRL_LO_HBW_CLK_ENABLER_DIS 0x42CB4A8
+
+#define mmDCORE1_MME_CTRL_LO_AGU 0x42CB4AC
+
+#define mmDCORE1_MME_CTRL_LO_QM 0x42CB4B0
+
+#define mmDCORE1_MME_CTRL_LO_EARLY_RELEASE_STATUS 0x42CB4B4
+
+#define mmDCORE1_MME_CTRL_LO_INTR_CAUSE 0x42CB4B8
+
+#define mmDCORE1_MME_CTRL_LO_INTR_MASK 0x42CB4BC
+
+#define mmDCORE1_MME_CTRL_LO_INTR_CLEAR 0x42CB4C0
+
+#define mmDCORE1_MME_CTRL_LO_REDUN_PSOC_SEL_SEC 0x42CB4C4
+
+#define mmDCORE1_MME_CTRL_LO_BIST 0x42CB4C8
+
+#define mmDCORE1_MME_CTRL_LO_EU_RL_ENABLE 0x42CB4CC
+
+#define mmDCORE1_MME_CTRL_LO_EU_RL_TOKEN_SEL 0x42CB4D0
+
+#define mmDCORE1_MME_CTRL_LO_EU_RL_CFG 0x42CB4D4
+
+#define mmDCORE1_MME_CTRL_LO_PCU_DBG_DW0 0x42CB4D8
+
+#define mmDCORE1_MME_CTRL_LO_PCU_DBG_DW1 0x42CB4DC
+
+#define mmDCORE1_MME_CTRL_LO_PCU_DBG_DW2 0x42CB4E0
+
+#define mmDCORE1_MME_CTRL_LO_PCU_DBG_DW3 0x42CB4E4
+
+#define mmDCORE1_MME_CTRL_LO_PCU_DBG_WKL_ID 0x42CB4E8
+
+#define mmDCORE1_MME_CTRL_LO_ETF_MEM_WRAP_RM 0x42CB4EC
+
+#endif /* ASIC_REG_DCORE1_MME_CTRL_LO_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore1_sync_mngr_glbl_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore1_sync_mngr_glbl_regs.h
new file mode 100644
index 000000000000..3d3802755814
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore1_sync_mngr_glbl_regs.h
@@ -0,0 +1,1203 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE1_SYNC_MNGR_GLBL_REGS_H_
+#define ASIC_REG_DCORE1_SYNC_MNGR_GLBL_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE1_SYNC_MNGR_GLBL
+ *   (Prototype: SOB_GLBL)
+ *****************************************
+ */
+
+#define mmDCORE1_SYNC_MNGR_GLBL_SM_SEI_MASK 0x431E000
+
+#define mmDCORE1_SYNC_MNGR_GLBL_SM_SEI_CAUSE 0x431E004
+
+#define mmDCORE1_SYNC_MNGR_GLBL_L2H_CPMR_L 0x431E008
+
+#define mmDCORE1_SYNC_MNGR_GLBL_L2H_CPMR_H 0x431E00C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_L2H_MASK_L 0x431E020
+
+#define mmDCORE1_SYNC_MNGR_GLBL_L2H_MASK_H 0x431E024
+
+#define mmDCORE1_SYNC_MNGR_GLBL_ASID_SEC 0x431E030
+
+#define mmDCORE1_SYNC_MNGR_GLBL_ASID_PRIV_ONLY 0x431E034
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DELAY 0x431E038
+
+#define mmDCORE1_SYNC_MNGR_GLBL_PI_SIZE 0x431E03C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_SOB_ONLY 0x431E040
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INTR 0x431E044
+
+#define mmDCORE1_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV 0x431E048
+
+#define mmDCORE1_SYNC_MNGR_GLBL_PI_INC_MODE_SIZE 0x431E04C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_0 0x431E050
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_1 0x431E054
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_2 0x431E058
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_3 0x431E05C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_4 0x431E060
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_5 0x431E064
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_6 0x431E068
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_7 0x431E06C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_8 0x431E070
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_9 0x431E074
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_10 0x431E078
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_11 0x431E07C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_12 0x431E080
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_13 0x431E084
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_14 0x431E088
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_15 0x431E08C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_16 0x431E090
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_17 0x431E094
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_18 0x431E098
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_19 0x431E09C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_20 0x431E0A0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_21 0x431E0A4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_22 0x431E0A8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_23 0x431E0AC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_24 0x431E0B0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_25 0x431E0B4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_26 0x431E0B8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_27 0x431E0BC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_28 0x431E0C0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_29 0x431E0C4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_30 0x431E0C8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_31 0x431E0CC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_32 0x431E0D0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_33 0x431E0D4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_34 0x431E0D8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_35 0x431E0DC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_36 0x431E0E0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_37 0x431E0E4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_38 0x431E0E8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_39 0x431E0EC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_40 0x431E0F0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_41 0x431E0F4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_42 0x431E0F8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_43 0x431E0FC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_44 0x431E100
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_45 0x431E104
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_46 0x431E108
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_47 0x431E10C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_48 0x431E110
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_49 0x431E114
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_50 0x431E118
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_51 0x431E11C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_52 0x431E120
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_53 0x431E124
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_54 0x431E128
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_55 0x431E12C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_56 0x431E130
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_57 0x431E134
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_58 0x431E138
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_59 0x431E13C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_60 0x431E140
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_61 0x431E144
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_62 0x431E148
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_63 0x431E14C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_0 0x431E150
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_1 0x431E154
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_2 0x431E158
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_3 0x431E15C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_4 0x431E160
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_5 0x431E164
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_6 0x431E168
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_7 0x431E16C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_8 0x431E170
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_9 0x431E174
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_10 0x431E178
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_11 0x431E17C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_12 0x431E180
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_13 0x431E184
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_14 0x431E188
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_15 0x431E18C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_16 0x431E190
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_17 0x431E194
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_18 0x431E198
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_19 0x431E19C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_20 0x431E1A0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_21 0x431E1A4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_22 0x431E1A8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_23 0x431E1AC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_24 0x431E1B0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_25 0x431E1B4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_26 0x431E1B8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_27 0x431E1BC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_28 0x431E1C0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_29 0x431E1C4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_30 0x431E1C8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_31 0x431E1CC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_32 0x431E1D0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_33 0x431E1D4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_34 0x431E1D8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_35 0x431E1DC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_36 0x431E1E0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_37 0x431E1E4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_38 0x431E1E8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_39 0x431E1EC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_40 0x431E1F0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_41 0x431E1F4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_42 0x431E1F8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_43 0x431E1FC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_44 0x431E200
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_45 0x431E204
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_46 0x431E208
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_47 0x431E20C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_48 0x431E210
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_49 0x431E214
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_50 0x431E218
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_51 0x431E21C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_52 0x431E220
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_53 0x431E224
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_54 0x431E228
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_55 0x431E22C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_56 0x431E230
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_57 0x431E234
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_58 0x431E238
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_59 0x431E23C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_60 0x431E240
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_61 0x431E244
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_62 0x431E248
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_63 0x431E24C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_0 0x431E250
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_1 0x431E254
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_2 0x431E258
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_3 0x431E25C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_4 0x431E260
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_5 0x431E264
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_6 0x431E268
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_7 0x431E26C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_8 0x431E270
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_9 0x431E274
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_10 0x431E278
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_11 0x431E27C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_12 0x431E280
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_13 0x431E284
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_14 0x431E288
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_15 0x431E28C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_16 0x431E290
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_17 0x431E294
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_18 0x431E298
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_19 0x431E29C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_20 0x431E2A0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_21 0x431E2A4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_22 0x431E2A8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_23 0x431E2AC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_24 0x431E2B0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_25 0x431E2B4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_26 0x431E2B8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_27 0x431E2BC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_28 0x431E2C0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_29 0x431E2C4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_30 0x431E2C8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_31 0x431E2CC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_32 0x431E2D0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_33 0x431E2D4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_34 0x431E2D8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_35 0x431E2DC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_36 0x431E2E0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_37 0x431E2E4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_38 0x431E2E8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_39 0x431E2EC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_40 0x431E2F0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_41 0x431E2F4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_42 0x431E2F8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_43 0x431E2FC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_44 0x431E300
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_45 0x431E304
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_46 0x431E308
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_47 0x431E30C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_48 0x431E310
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_49 0x431E314
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_50 0x431E318
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_51 0x431E31C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_52 0x431E320
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_53 0x431E324
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_54 0x431E328
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_55 0x431E32C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_56 0x431E330
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_57 0x431E334
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_58 0x431E338
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_59 0x431E33C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_60 0x431E340
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_61 0x431E344
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_62 0x431E348
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_63 0x431E34C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_0 0x431E350
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_1 0x431E354
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_2 0x431E358
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_3 0x431E35C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_4 0x431E360
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_5 0x431E364
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_6 0x431E368
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_7 0x431E36C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_8 0x431E370
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_9 0x431E374
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_10 0x431E378
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_11 0x431E37C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_12 0x431E380
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_13 0x431E384
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_14 0x431E388
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_15 0x431E38C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_16 0x431E390
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_17 0x431E394
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_18 0x431E398
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_19 0x431E39C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_20 0x431E3A0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_21 0x431E3A4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_22 0x431E3A8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_23 0x431E3AC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_24 0x431E3B0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_25 0x431E3B4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_26 0x431E3B8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_27 0x431E3BC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_28 0x431E3C0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_29 0x431E3C4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_30 0x431E3C8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_31 0x431E3CC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_32 0x431E3D0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_33 0x431E3D4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_34 0x431E3D8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_35 0x431E3DC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_36 0x431E3E0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_37 0x431E3E4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_38 0x431E3E8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_39 0x431E3EC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_40 0x431E3F0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_41 0x431E3F4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_42 0x431E3F8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_43 0x431E3FC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_44 0x431E400
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_45 0x431E404
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_46 0x431E408
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_47 0x431E40C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_48 0x431E410
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_49 0x431E414
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_50 0x431E418
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_51 0x431E41C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_52 0x431E420
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_53 0x431E424
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_54 0x431E428
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_55 0x431E42C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_56 0x431E430
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_57 0x431E434
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_58 0x431E438
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_59 0x431E43C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_60 0x431E440
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_61 0x431E444
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_62 0x431E448
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_63 0x431E44C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_0 0x431E450
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_1 0x431E454
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_2 0x431E458
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_3 0x431E45C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_4 0x431E460
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_5 0x431E464
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_6 0x431E468
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_7 0x431E46C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_8 0x431E470
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_9 0x431E474
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_10 0x431E478
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_11 0x431E47C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_12 0x431E480
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_13 0x431E484
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_14 0x431E488
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_15 0x431E48C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_16 0x431E490
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_17 0x431E494
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_18 0x431E498
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_19 0x431E49C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_20 0x431E4A0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_21 0x431E4A4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_22 0x431E4A8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_23 0x431E4AC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_24 0x431E4B0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_25 0x431E4B4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_26 0x431E4B8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_27 0x431E4BC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_28 0x431E4C0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_29 0x431E4C4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_30 0x431E4C8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_31 0x431E4CC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_32 0x431E4D0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_33 0x431E4D4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_34 0x431E4D8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_35 0x431E4DC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_36 0x431E4E0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_37 0x431E4E4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_38 0x431E4E8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_39 0x431E4EC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_40 0x431E4F0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_41 0x431E4F4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_42 0x431E4F8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_43 0x431E4FC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_44 0x431E500
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_45 0x431E504
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_46 0x431E508
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_47 0x431E50C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_48 0x431E510
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_49 0x431E514
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_50 0x431E518
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_51 0x431E51C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_52 0x431E520
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_53 0x431E524
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_54 0x431E528
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_55 0x431E52C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_56 0x431E530
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_57 0x431E534
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_58 0x431E538
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_59 0x431E53C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_60 0x431E540
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_61 0x431E544
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_62 0x431E548
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_63 0x431E54C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_0 0x431E550
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_1 0x431E554
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_2 0x431E558
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_3 0x431E55C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_4 0x431E560
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_5 0x431E564
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_6 0x431E568
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_7 0x431E56C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_8 0x431E570
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_9 0x431E574
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_10 0x431E578
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_11 0x431E57C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_12 0x431E580
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_13 0x431E584
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_14 0x431E588
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_15 0x431E58C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_16 0x431E590
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_17 0x431E594
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_18 0x431E598
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_19 0x431E59C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_20 0x431E5A0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_21 0x431E5A4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_22 0x431E5A8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_23 0x431E5AC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_24 0x431E5B0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_25 0x431E5B4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_26 0x431E5B8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_27 0x431E5BC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_28 0x431E5C0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_29 0x431E5C4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_30 0x431E5C8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_31 0x431E5CC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_32 0x431E5D0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_33 0x431E5D4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_34 0x431E5D8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_35 0x431E5DC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_36 0x431E5E0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_37 0x431E5E4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_38 0x431E5E8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_39 0x431E5EC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_40 0x431E5F0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_41 0x431E5F4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_42 0x431E5F8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_43 0x431E5FC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_44 0x431E600
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_45 0x431E604
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_46 0x431E608
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_47 0x431E60C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_48 0x431E610
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_49 0x431E614
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_50 0x431E618
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_51 0x431E61C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_52 0x431E620
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_53 0x431E624
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_54 0x431E628
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_55 0x431E62C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_56 0x431E630
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_57 0x431E634
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_58 0x431E638
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_59 0x431E63C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_60 0x431E640
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_61 0x431E644
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_62 0x431E648
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_63 0x431E64C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_0 0x431E650
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_1 0x431E654
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_2 0x431E658
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_3 0x431E65C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_4 0x431E660
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_5 0x431E664
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_6 0x431E668
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_7 0x431E66C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_8 0x431E670
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_9 0x431E674
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_10 0x431E678
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_11 0x431E67C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_12 0x431E680
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_13 0x431E684
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_14 0x431E688
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_15 0x431E68C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_16 0x431E690
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_17 0x431E694
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_18 0x431E698
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_19 0x431E69C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_20 0x431E6A0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_21 0x431E6A4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_22 0x431E6A8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_23 0x431E6AC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_24 0x431E6B0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_25 0x431E6B4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_26 0x431E6B8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_27 0x431E6BC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_28 0x431E6C0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_29 0x431E6C4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_30 0x431E6C8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_31 0x431E6CC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_32 0x431E6D0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_33 0x431E6D4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_34 0x431E6D8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_35 0x431E6DC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_36 0x431E6E0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_37 0x431E6E4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_38 0x431E6E8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_39 0x431E6EC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_40 0x431E6F0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_41 0x431E6F4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_42 0x431E6F8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_43 0x431E6FC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_44 0x431E700
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_45 0x431E704
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_46 0x431E708
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_47 0x431E70C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_48 0x431E710
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_49 0x431E714
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_50 0x431E718
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_51 0x431E71C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_52 0x431E720
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_53 0x431E724
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_54 0x431E728
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_55 0x431E72C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_56 0x431E730
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_57 0x431E734
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_58 0x431E738
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_59 0x431E73C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_60 0x431E740
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_61 0x431E744
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_62 0x431E748
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_63 0x431E74C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_0 0x431E750
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_1 0x431E754
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_2 0x431E758
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_3 0x431E75C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_4 0x431E760
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_5 0x431E764
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_6 0x431E768
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_7 0x431E76C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_8 0x431E770
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_9 0x431E774
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_10 0x431E778
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_11 0x431E77C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_12 0x431E780
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_13 0x431E784
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_14 0x431E788
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_15 0x431E78C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_16 0x431E790
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_17 0x431E794
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_18 0x431E798
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_19 0x431E79C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_20 0x431E7A0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_21 0x431E7A4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_22 0x431E7A8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_23 0x431E7AC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_24 0x431E7B0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_25 0x431E7B4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_26 0x431E7B8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_27 0x431E7BC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_28 0x431E7C0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_29 0x431E7C4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_30 0x431E7C8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_31 0x431E7CC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_32 0x431E7D0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_33 0x431E7D4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_34 0x431E7D8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_35 0x431E7DC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_36 0x431E7E0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_37 0x431E7E4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_38 0x431E7E8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_39 0x431E7EC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_40 0x431E7F0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_41 0x431E7F4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_42 0x431E7F8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_43 0x431E7FC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_44 0x431E800
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_45 0x431E804
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_46 0x431E808
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_47 0x431E80C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_48 0x431E810
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_49 0x431E814
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_50 0x431E818
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_51 0x431E81C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_52 0x431E820
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_53 0x431E824
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_54 0x431E828
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_55 0x431E82C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_56 0x431E830
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_57 0x431E834
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_58 0x431E838
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_59 0x431E83C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_60 0x431E840
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_61 0x431E844
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_62 0x431E848
+
+#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_63 0x431E84C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_0 0x431E850
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_1 0x431E854
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_2 0x431E858
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_3 0x431E85C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_4 0x431E860
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_5 0x431E864
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_6 0x431E868
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_7 0x431E86C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_8 0x431E870
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_9 0x431E874
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_10 0x431E878
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_11 0x431E87C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_12 0x431E880
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_13 0x431E884
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_14 0x431E888
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_15 0x431E88C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_16 0x431E890
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_17 0x431E894
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_18 0x431E898
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_19 0x431E89C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_20 0x431E8A0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_21 0x431E8A4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_22 0x431E8A8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_23 0x431E8AC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_24 0x431E8B0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_25 0x431E8B4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_26 0x431E8B8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_27 0x431E8BC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_28 0x431E8C0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_29 0x431E8C4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_30 0x431E8C8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_31 0x431E8CC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_32 0x431E8D0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_33 0x431E8D4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_34 0x431E8D8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_35 0x431E8DC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_36 0x431E8E0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_37 0x431E8E4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_38 0x431E8E8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_39 0x431E8EC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_40 0x431E8F0
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_41 0x431E8F4
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_42 0x431E8F8
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_43 0x431E8FC
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_44 0x431E900
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_45 0x431E904
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_46 0x431E908
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_47 0x431E90C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_48 0x431E910
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_49 0x431E914
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_50 0x431E918
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_51 0x431E91C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_52 0x431E920
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_53 0x431E924
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_54 0x431E928
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_55 0x431E92C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_56 0x431E930
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_57 0x431E934
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_58 0x431E938
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_59 0x431E93C
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_60 0x431E940
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_61 0x431E944
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_62 0x431E948
+
+#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_63 0x431E94C
+
+#endif /* ASIC_REG_DCORE1_SYNC_MNGR_GLBL_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore3_mme_ctrl_lo_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore3_mme_ctrl_lo_regs.h
new file mode 100644
index 000000000000..b06469f5a279
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore3_mme_ctrl_lo_regs.h
@@ -0,0 +1,163 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE3_MME_CTRL_LO_REGS_H_
+#define ASIC_REG_DCORE3_MME_CTRL_LO_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE3_MME_CTRL_LO
+ *   (Prototype: MME_CTRL_LO)
+ *****************************************
+ */
+
+#define mmDCORE3_MME_CTRL_LO_ARCH_STATUS 0x46CB000
+
+#define mmDCORE3_MME_CTRL_LO_CMD 0x46CB004
+
+#define mmDCORE3_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0 0x46CB148
+
+#define mmDCORE3_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0 0x46CB14C
+
+#define mmDCORE3_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0 0x46CB150
+
+#define mmDCORE3_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1 0x46CB154
+
+#define mmDCORE3_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1 0x46CB158
+
+#define mmDCORE3_MME_CTRL_LO_ARCH_A_SS 0x46CB224
+
+#define mmDCORE3_MME_CTRL_LO_ARCH_B_SS 0x46CB228
+
+#define mmDCORE3_MME_CTRL_LO_ARCH_COUT_SS 0x46CB27C
+
+#define mmDCORE3_MME_CTRL_LO_QM_STALL 0x46CB400
+
+#define mmDCORE3_MME_CTRL_LO_LOG_SHADOW_LO 0x46CB404
+
+#define mmDCORE3_MME_CTRL_LO_LOG_SHADOW_HI 0x46CB408
+
+#define mmDCORE3_MME_CTRL_LO_SYNC_OBJECT_FIFO_TH 0x46CB40C
+
+#define mmDCORE3_MME_CTRL_LO_REDUN 0x46CB410
+
+#define mmDCORE3_MME_CTRL_LO_EUS_LOCAL_FIFO_TH 0x46CB414
+
+#define mmDCORE3_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0 0x46CB418
+
+#define mmDCORE3_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1 0x46CB41C
+
+#define mmDCORE3_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16 0x46CB420
+
+#define mmDCORE3_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8 0x46CB424
+
+#define mmDCORE3_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32 0x46CB428
+
+#define mmDCORE3_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I 0x46CB42C
+
+#define mmDCORE3_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32 0x46CB430
+
+#define mmDCORE3_MME_CTRL_LO_PCU_RL_DESC0 0x46CB434
+
+#define mmDCORE3_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE 0x46CB438
+
+#define mmDCORE3_MME_CTRL_LO_PCU_RL_TH 0x46CB43C
+
+#define mmDCORE3_MME_CTRL_LO_PCU_RL_MIN 0x46CB440
+
+#define mmDCORE3_MME_CTRL_LO_PCU_RL_CTRL_EN 0x46CB444
+
+#define mmDCORE3_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE 0x46CB448
+
+#define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_A_BF16 0x46CB44C
+
+#define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_B_BF16 0x46CB450
+
+#define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_A_FP16 0x46CB454
+
+#define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_B_FP16 0x46CB458
+
+#define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_F8 0x46CB45C
+
+#define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_A_FP32_ODD 0x46CB460
+
+#define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_A_FP32_EVEN 0x46CB464
+
+#define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_B_FP32_ODD 0x46CB468
+
+#define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_B_FP32_EVEN 0x46CB46C
+
+#define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_A_TF32_ODD 0x46CB470
+
+#define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_A_TF32_EVEN 0x46CB474
+
+#define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_B_TF32_ODD 0x46CB478
+
+#define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_B_TF32_EVEN 0x46CB47C
+
+#define mmDCORE3_MME_CTRL_LO_PROT 0x46CB480
+
+#define mmDCORE3_MME_CTRL_LO_EU 0x46CB484
+
+#define mmDCORE3_MME_CTRL_LO_SBTE 0x46CB488
+
+#define mmDCORE3_MME_CTRL_LO_AGU_SM_INFLIGHT_CNTR 0x46CB48C
+
+#define mmDCORE3_MME_CTRL_LO_AGU_SM_TOTAL_CNTR 0x46CB490
+
+#define mmDCORE3_MME_CTRL_LO_PCU_RL_SAT_SEC 0x46CB494
+
+#define mmDCORE3_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN32 0x46CB498
+
+#define mmDCORE3_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN33 0x46CB49C
+
+#define mmDCORE3_MME_CTRL_LO_EU_ISOLATION_DIS 0x46CB4A0
+
+#define mmDCORE3_MME_CTRL_LO_QM_SLV_CLK_EN 0x46CB4A4
+
+#define mmDCORE3_MME_CTRL_LO_HBW_CLK_ENABLER_DIS 0x46CB4A8
+
+#define mmDCORE3_MME_CTRL_LO_AGU 0x46CB4AC
+
+#define mmDCORE3_MME_CTRL_LO_QM 0x46CB4B0
+
+#define mmDCORE3_MME_CTRL_LO_EARLY_RELEASE_STATUS 0x46CB4B4
+
+#define mmDCORE3_MME_CTRL_LO_INTR_CAUSE 0x46CB4B8
+
+#define mmDCORE3_MME_CTRL_LO_INTR_MASK 0x46CB4BC
+
+#define mmDCORE3_MME_CTRL_LO_INTR_CLEAR 0x46CB4C0
+
+#define mmDCORE3_MME_CTRL_LO_REDUN_PSOC_SEL_SEC 0x46CB4C4
+
+#define mmDCORE3_MME_CTRL_LO_BIST 0x46CB4C8
+
+#define mmDCORE3_MME_CTRL_LO_EU_RL_ENABLE 0x46CB4CC
+
+#define mmDCORE3_MME_CTRL_LO_EU_RL_TOKEN_SEL 0x46CB4D0
+
+#define mmDCORE3_MME_CTRL_LO_EU_RL_CFG 0x46CB4D4
+
+#define mmDCORE3_MME_CTRL_LO_PCU_DBG_DW0 0x46CB4D8
+
+#define mmDCORE3_MME_CTRL_LO_PCU_DBG_DW1 0x46CB4DC
+
+#define mmDCORE3_MME_CTRL_LO_PCU_DBG_DW2 0x46CB4E0
+
+#define mmDCORE3_MME_CTRL_LO_PCU_DBG_DW3 0x46CB4E4
+
+#define mmDCORE3_MME_CTRL_LO_PCU_DBG_WKL_ID 0x46CB4E8
+
+#define mmDCORE3_MME_CTRL_LO_ETF_MEM_WRAP_RM 0x46CB4EC
+
+#endif /* ASIC_REG_DCORE3_MME_CTRL_LO_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_blocks_linux_driver.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_blocks_linux_driver.h
new file mode 100644
index 000000000000..3caee4515ad6
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_blocks_linux_driver.h
@@ -0,0 +1,45067 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef GAUDI2_BLOCKS_LINUX_DRIVER_H_
+#define GAUDI2_BLOCKS_LINUX_DRIVER_H_
+
+#define mmDCORE0_TPC0_ROM_TABLE_BASE 0x0ull
+#define DCORE0_TPC0_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE0_TPC0_ROM_TABLE_SECTION 0x1000
+#define mmDCORE0_TPC0_EML_SPMU_BASE 0x1000ull
+#define DCORE0_TPC0_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_TPC0_EML_SPMU_SECTION 0x1000
+#define mmDCORE0_TPC0_EML_ETF_BASE 0x2000ull
+#define DCORE0_TPC0_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE0_TPC0_EML_ETF_SECTION 0x1000
+#define mmDCORE0_TPC0_EML_STM_BASE 0x3000ull
+#define DCORE0_TPC0_EML_STM_MAX_OFFSET 0x1000
+#define DCORE0_TPC0_EML_STM_SECTION 0x2000
+#define mmDCORE0_TPC0_EML_CTI_BASE 0x5000ull
+#define DCORE0_TPC0_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE0_TPC0_EML_CTI_SECTION 0x1000
+#define mmDCORE0_TPC0_EML_FUNNEL_BASE 0x6000ull
+#define DCORE0_TPC0_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_TPC0_EML_FUNNEL_SECTION 0x1000
+#define mmDCORE0_TPC0_EML_BUSMON_0_BASE 0x7000ull
+#define DCORE0_TPC0_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE0_TPC0_EML_BUSMON_0_SECTION 0x1000
+#define mmDCORE0_TPC0_EML_BUSMON_1_BASE 0x8000ull
+#define DCORE0_TPC0_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE0_TPC0_EML_BUSMON_1_SECTION 0x1000
+#define mmDCORE0_TPC0_EML_BUSMON_2_BASE 0x9000ull
+#define DCORE0_TPC0_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE0_TPC0_EML_BUSMON_2_SECTION 0x1000
+#define mmDCORE0_TPC0_EML_BUSMON_3_BASE 0xA000ull
+#define DCORE0_TPC0_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE0_TPC0_EML_BUSMON_3_SECTION 0x1000
+#define mmDCORE0_TPC0_QM_ARC_RTT_BASE 0xB000ull
+#define DCORE0_TPC0_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE0_TPC0_QM_ARC_RTT_SECTION 0x35000
+#define mmDCORE0_TPC0_EML_CFG_BASE 0x40000ull
+#define DCORE0_TPC0_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC0_EML_CFG_SECTION 0xE800
+#define mmDCORE0_TPC0_EML_CFG_SPECIAL_BASE 0x40E80ull
+#define DCORE0_TPC0_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC0_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x41000ull
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC0_EML_TPC_CFG_BASE 0x41000ull
+#define DCORE0_TPC0_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC0_EML_TPC_CFG_SECTION 0x5000
+#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x41050ull
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x410A0ull
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x410F0ull
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x41140ull
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x41190ull
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x411E0ull
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x41230ull
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x41280ull
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x412D0ull
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x41320ull
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x41370ull
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x413C0ull
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x41410ull
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x41460ull
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x414B0ull
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x41500ull
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_BASE 0x41508ull
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_0_BASE 0x415DCull
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_1_BASE 0x4162Cull
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_2_BASE 0x4167Cull
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_3_BASE 0x416CCull
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_4_BASE 0x4171Cull
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_5_BASE 0x4176Cull
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_6_BASE 0x417BCull
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_7_BASE 0x4180Cull
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_8_BASE 0x4185Cull
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_9_BASE 0x418ACull
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_10_BASE 0x418FCull
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_11_BASE 0x4194Cull
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_12_BASE 0x4199Cull
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_13_BASE 0x419ECull
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_14_BASE 0x41A3Cull
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_15_BASE 0x41A8Cull
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE0_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x41ADCull
+#define DCORE0_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE0_TPC0_EML_TPC_CFG_QM_BASE 0x41AE4ull
+#define DCORE0_TPC0_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE0_TPC0_EML_TPC_CFG_QM_SECTION 0x31C0
+#define mmDCORE0_TPC0_EML_TPC_CFG_AXUSER_BASE 0x41E00ull
+#define DCORE0_TPC0_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE0_TPC0_EML_TPC_CFG_SPECIAL_BASE 0x41E80ull
+#define DCORE0_TPC0_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC0_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC0_EML_QM_DCCM_BASE 0x42000ull
+#define DCORE0_TPC0_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE0_TPC0_EML_QM_DCCM_SECTION 0x8000
+#define mmDCORE0_TPC0_EML_QM_ARCAUX_BASE 0x4A000ull
+#define DCORE0_TPC0_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE0_TPC0_EML_QM_ARCAUX_SECTION 0xE800
+#define mmDCORE0_TPC0_EML_QM_ARCAUX_SPECIAL_BASE 0x4AE80ull
+#define DCORE0_TPC0_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC0_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define mmDCORE0_TPC0_EML_TPC_QM_BASE 0x4C000ull
+#define DCORE0_TPC0_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE0_TPC0_EML_TPC_QM_SECTION 0x9000
+#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x4C900ull
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x4C908ull
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x4C910ull
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x4C918ull
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x4C920ull
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x4C928ull
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x4C930ull
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x4C938ull
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x4C940ull
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x4C948ull
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x4C950ull
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x4C958ull
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x4C960ull
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x4C968ull
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x4C970ull
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x4C978ull
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE0_TPC0_EML_TPC_QM_AXUSER_SECURED_BASE 0x4CB00ull
+#define DCORE0_TPC0_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE0_TPC0_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x4CB80ull
+#define DCORE0_TPC0_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE0_TPC0_EML_TPC_QM_DBG_HBW_BASE 0x4CC00ull
+#define DCORE0_TPC0_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC0_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_TPC0_EML_TPC_QM_DBG_LBW_BASE 0x4CC80ull
+#define DCORE0_TPC0_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC0_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE0_TPC0_EML_TPC_QM_CGM_BASE 0x4CD80ull
+#define DCORE0_TPC0_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE0_TPC0_EML_TPC_QM_CGM_SECTION 0x1000
+#define mmDCORE0_TPC0_EML_TPC_QM_SPECIAL_BASE 0x4CE80ull
+#define DCORE0_TPC0_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC0_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define mmDCORE0_TPC0_EML_CS_BASE 0x1FF000ull
+#define DCORE0_TPC0_EML_CS_MAX_OFFSET 0x1000
+#define DCORE0_TPC0_EML_CS_SECTION 0x1000
+#define mmDCORE0_TPC1_ROM_TABLE_BASE 0x200000ull
+#define DCORE0_TPC1_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE0_TPC1_ROM_TABLE_SECTION 0x1000
+#define mmDCORE0_TPC1_EML_SPMU_BASE 0x201000ull
+#define DCORE0_TPC1_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_TPC1_EML_SPMU_SECTION 0x1000
+#define mmDCORE0_TPC1_EML_ETF_BASE 0x202000ull
+#define DCORE0_TPC1_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE0_TPC1_EML_ETF_SECTION 0x1000
+#define mmDCORE0_TPC1_EML_STM_BASE 0x203000ull
+#define DCORE0_TPC1_EML_STM_MAX_OFFSET 0x1000
+#define DCORE0_TPC1_EML_STM_SECTION 0x2000
+#define mmDCORE0_TPC1_EML_CTI_BASE 0x205000ull
+#define DCORE0_TPC1_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE0_TPC1_EML_CTI_SECTION 0x1000
+#define mmDCORE0_TPC1_EML_FUNNEL_BASE 0x206000ull
+#define DCORE0_TPC1_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_TPC1_EML_FUNNEL_SECTION 0x1000
+#define mmDCORE0_TPC1_EML_BUSMON_0_BASE 0x207000ull
+#define DCORE0_TPC1_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE0_TPC1_EML_BUSMON_0_SECTION 0x1000
+#define mmDCORE0_TPC1_EML_BUSMON_1_BASE 0x208000ull
+#define DCORE0_TPC1_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE0_TPC1_EML_BUSMON_1_SECTION 0x1000
+#define mmDCORE0_TPC1_EML_BUSMON_2_BASE 0x209000ull
+#define DCORE0_TPC1_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE0_TPC1_EML_BUSMON_2_SECTION 0x1000
+#define mmDCORE0_TPC1_EML_BUSMON_3_BASE 0x20A000ull
+#define DCORE0_TPC1_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE0_TPC1_EML_BUSMON_3_SECTION 0x1000
+#define mmDCORE0_TPC1_QM_ARC_RTT_BASE 0x20B000ull
+#define DCORE0_TPC1_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE0_TPC1_QM_ARC_RTT_SECTION 0x35000
+#define mmDCORE0_TPC1_EML_CFG_BASE 0x240000ull
+#define DCORE0_TPC1_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC1_EML_CFG_SECTION 0xE800
+#define mmDCORE0_TPC1_EML_CFG_SPECIAL_BASE 0x240E80ull
+#define DCORE0_TPC1_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC1_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x241000ull
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC1_EML_TPC_CFG_BASE 0x241000ull
+#define DCORE0_TPC1_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC1_EML_TPC_CFG_SECTION 0x5000
+#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x241050ull
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x2410A0ull
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x2410F0ull
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x241140ull
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x241190ull
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x2411E0ull
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x241230ull
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x241280ull
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x2412D0ull
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x241320ull
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x241370ull
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x2413C0ull
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x241410ull
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x241460ull
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x2414B0ull
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x241500ull
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_BASE 0x241508ull
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_0_BASE 0x2415DCull
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_1_BASE 0x24162Cull
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_2_BASE 0x24167Cull
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_3_BASE 0x2416CCull
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_4_BASE 0x24171Cull
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_5_BASE 0x24176Cull
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_6_BASE 0x2417BCull
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_7_BASE 0x24180Cull
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_8_BASE 0x24185Cull
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_9_BASE 0x2418ACull
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_10_BASE 0x2418FCull
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_11_BASE 0x24194Cull
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_12_BASE 0x24199Cull
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_13_BASE 0x2419ECull
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_14_BASE 0x241A3Cull
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_15_BASE 0x241A8Cull
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE0_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x241ADCull
+#define DCORE0_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE0_TPC1_EML_TPC_CFG_QM_BASE 0x241AE4ull
+#define DCORE0_TPC1_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE0_TPC1_EML_TPC_CFG_QM_SECTION 0x31C0
+#define mmDCORE0_TPC1_EML_TPC_CFG_AXUSER_BASE 0x241E00ull
+#define DCORE0_TPC1_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE0_TPC1_EML_TPC_CFG_SPECIAL_BASE 0x241E80ull
+#define DCORE0_TPC1_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC1_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC1_EML_QM_DCCM_BASE 0x242000ull
+#define DCORE0_TPC1_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE0_TPC1_EML_QM_DCCM_SECTION 0x8000
+#define mmDCORE0_TPC1_EML_QM_ARCAUX_BASE 0x24A000ull
+#define DCORE0_TPC1_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE0_TPC1_EML_QM_ARCAUX_SECTION 0xE800
+#define mmDCORE0_TPC1_EML_QM_ARCAUX_SPECIAL_BASE 0x24AE80ull
+#define DCORE0_TPC1_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC1_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define mmDCORE0_TPC1_EML_TPC_QM_BASE 0x24C000ull
+#define DCORE0_TPC1_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE0_TPC1_EML_TPC_QM_SECTION 0x9000
+#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x24C900ull
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x24C908ull
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x24C910ull
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x24C918ull
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x24C920ull
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x24C928ull
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x24C930ull
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x24C938ull
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x24C940ull
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x24C948ull
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x24C950ull
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x24C958ull
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x24C960ull
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x24C968ull
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x24C970ull
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x24C978ull
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE0_TPC1_EML_TPC_QM_AXUSER_SECURED_BASE 0x24CB00ull
+#define DCORE0_TPC1_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE0_TPC1_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x24CB80ull
+#define DCORE0_TPC1_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE0_TPC1_EML_TPC_QM_DBG_HBW_BASE 0x24CC00ull
+#define DCORE0_TPC1_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC1_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_TPC1_EML_TPC_QM_DBG_LBW_BASE 0x24CC80ull
+#define DCORE0_TPC1_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC1_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE0_TPC1_EML_TPC_QM_CGM_BASE 0x24CD80ull
+#define DCORE0_TPC1_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE0_TPC1_EML_TPC_QM_CGM_SECTION 0x1000
+#define mmDCORE0_TPC1_EML_TPC_QM_SPECIAL_BASE 0x24CE80ull
+#define DCORE0_TPC1_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC1_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define mmDCORE0_TPC1_EML_CS_BASE 0x3FF000ull
+#define DCORE0_TPC1_EML_CS_MAX_OFFSET 0x1000
+#define DCORE0_TPC1_EML_CS_SECTION 0x1000
+#define mmDCORE0_TPC2_ROM_TABLE_BASE 0x400000ull
+#define DCORE0_TPC2_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE0_TPC2_ROM_TABLE_SECTION 0x1000
+#define mmDCORE0_TPC2_EML_SPMU_BASE 0x401000ull
+#define DCORE0_TPC2_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_TPC2_EML_SPMU_SECTION 0x1000
+#define mmDCORE0_TPC2_EML_ETF_BASE 0x402000ull
+#define DCORE0_TPC2_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE0_TPC2_EML_ETF_SECTION 0x1000
+#define mmDCORE0_TPC2_EML_STM_BASE 0x403000ull
+#define DCORE0_TPC2_EML_STM_MAX_OFFSET 0x1000
+#define DCORE0_TPC2_EML_STM_SECTION 0x2000
+#define mmDCORE0_TPC2_EML_CTI_BASE 0x405000ull
+#define DCORE0_TPC2_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE0_TPC2_EML_CTI_SECTION 0x1000
+#define mmDCORE0_TPC2_EML_FUNNEL_BASE 0x406000ull
+#define DCORE0_TPC2_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_TPC2_EML_FUNNEL_SECTION 0x1000
+#define mmDCORE0_TPC2_EML_BUSMON_0_BASE 0x407000ull
+#define DCORE0_TPC2_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE0_TPC2_EML_BUSMON_0_SECTION 0x1000
+#define mmDCORE0_TPC2_EML_BUSMON_1_BASE 0x408000ull
+#define DCORE0_TPC2_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE0_TPC2_EML_BUSMON_1_SECTION 0x1000
+#define mmDCORE0_TPC2_EML_BUSMON_2_BASE 0x409000ull
+#define DCORE0_TPC2_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE0_TPC2_EML_BUSMON_2_SECTION 0x1000
+#define mmDCORE0_TPC2_EML_BUSMON_3_BASE 0x40A000ull
+#define DCORE0_TPC2_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE0_TPC2_EML_BUSMON_3_SECTION 0x1000
+#define mmDCORE0_TPC2_QM_ARC_RTT_BASE 0x40B000ull
+#define DCORE0_TPC2_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE0_TPC2_QM_ARC_RTT_SECTION 0x35000
+#define mmDCORE0_TPC2_EML_CFG_BASE 0x440000ull
+#define DCORE0_TPC2_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC2_EML_CFG_SECTION 0xE800
+#define mmDCORE0_TPC2_EML_CFG_SPECIAL_BASE 0x440E80ull
+#define DCORE0_TPC2_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC2_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x441000ull
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC2_EML_TPC_CFG_BASE 0x441000ull
+#define DCORE0_TPC2_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC2_EML_TPC_CFG_SECTION 0x5000
+#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x441050ull
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x4410A0ull
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x4410F0ull
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x441140ull
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x441190ull
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x4411E0ull
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x441230ull
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x441280ull
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x4412D0ull
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x441320ull
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x441370ull
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x4413C0ull
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x441410ull
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x441460ull
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x4414B0ull
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x441500ull
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_BASE 0x441508ull
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_0_BASE 0x4415DCull
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_1_BASE 0x44162Cull
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_2_BASE 0x44167Cull
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_3_BASE 0x4416CCull
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_4_BASE 0x44171Cull
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_5_BASE 0x44176Cull
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_6_BASE 0x4417BCull
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_7_BASE 0x44180Cull
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_8_BASE 0x44185Cull
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_9_BASE 0x4418ACull
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_10_BASE 0x4418FCull
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_11_BASE 0x44194Cull
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_12_BASE 0x44199Cull
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_13_BASE 0x4419ECull
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_14_BASE 0x441A3Cull
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_15_BASE 0x441A8Cull
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE0_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x441ADCull
+#define DCORE0_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE0_TPC2_EML_TPC_CFG_QM_BASE 0x441AE4ull
+#define DCORE0_TPC2_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE0_TPC2_EML_TPC_CFG_QM_SECTION 0x31C0
+#define mmDCORE0_TPC2_EML_TPC_CFG_AXUSER_BASE 0x441E00ull
+#define DCORE0_TPC2_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE0_TPC2_EML_TPC_CFG_SPECIAL_BASE 0x441E80ull
+#define DCORE0_TPC2_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC2_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC2_EML_QM_DCCM_BASE 0x442000ull
+#define DCORE0_TPC2_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE0_TPC2_EML_QM_DCCM_SECTION 0x8000
+#define mmDCORE0_TPC2_EML_QM_ARCAUX_BASE 0x44A000ull
+#define DCORE0_TPC2_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE0_TPC2_EML_QM_ARCAUX_SECTION 0xE800
+#define mmDCORE0_TPC2_EML_QM_ARCAUX_SPECIAL_BASE 0x44AE80ull
+#define DCORE0_TPC2_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC2_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define mmDCORE0_TPC2_EML_TPC_QM_BASE 0x44C000ull
+#define DCORE0_TPC2_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE0_TPC2_EML_TPC_QM_SECTION 0x9000
+#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x44C900ull
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x44C908ull
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x44C910ull
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x44C918ull
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x44C920ull
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x44C928ull
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x44C930ull
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x44C938ull
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x44C940ull
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x44C948ull
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x44C950ull
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x44C958ull
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x44C960ull
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x44C968ull
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x44C970ull
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x44C978ull
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE0_TPC2_EML_TPC_QM_AXUSER_SECURED_BASE 0x44CB00ull
+#define DCORE0_TPC2_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE0_TPC2_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x44CB80ull
+#define DCORE0_TPC2_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE0_TPC2_EML_TPC_QM_DBG_HBW_BASE 0x44CC00ull
+#define DCORE0_TPC2_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC2_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_TPC2_EML_TPC_QM_DBG_LBW_BASE 0x44CC80ull
+#define DCORE0_TPC2_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC2_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE0_TPC2_EML_TPC_QM_CGM_BASE 0x44CD80ull
+#define DCORE0_TPC2_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE0_TPC2_EML_TPC_QM_CGM_SECTION 0x1000
+#define mmDCORE0_TPC2_EML_TPC_QM_SPECIAL_BASE 0x44CE80ull
+#define DCORE0_TPC2_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC2_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define mmDCORE0_TPC2_EML_CS_BASE 0x5FF000ull
+#define DCORE0_TPC2_EML_CS_MAX_OFFSET 0x1000
+#define DCORE0_TPC2_EML_CS_SECTION 0x1000
+#define mmDCORE0_TPC3_ROM_TABLE_BASE 0x600000ull
+#define DCORE0_TPC3_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE0_TPC3_ROM_TABLE_SECTION 0x1000
+#define mmDCORE0_TPC3_EML_SPMU_BASE 0x601000ull
+#define DCORE0_TPC3_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_TPC3_EML_SPMU_SECTION 0x1000
+#define mmDCORE0_TPC3_EML_ETF_BASE 0x602000ull
+#define DCORE0_TPC3_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE0_TPC3_EML_ETF_SECTION 0x1000
+#define mmDCORE0_TPC3_EML_STM_BASE 0x603000ull
+#define DCORE0_TPC3_EML_STM_MAX_OFFSET 0x1000
+#define DCORE0_TPC3_EML_STM_SECTION 0x2000
+#define mmDCORE0_TPC3_EML_CTI_BASE 0x605000ull
+#define DCORE0_TPC3_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE0_TPC3_EML_CTI_SECTION 0x1000
+#define mmDCORE0_TPC3_EML_FUNNEL_BASE 0x606000ull
+#define DCORE0_TPC3_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_TPC3_EML_FUNNEL_SECTION 0x1000
+#define mmDCORE0_TPC3_EML_BUSMON_0_BASE 0x607000ull
+#define DCORE0_TPC3_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE0_TPC3_EML_BUSMON_0_SECTION 0x1000
+#define mmDCORE0_TPC3_EML_BUSMON_1_BASE 0x608000ull
+#define DCORE0_TPC3_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE0_TPC3_EML_BUSMON_1_SECTION 0x1000
+#define mmDCORE0_TPC3_EML_BUSMON_2_BASE 0x609000ull
+#define DCORE0_TPC3_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE0_TPC3_EML_BUSMON_2_SECTION 0x1000
+#define mmDCORE0_TPC3_EML_BUSMON_3_BASE 0x60A000ull
+#define DCORE0_TPC3_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE0_TPC3_EML_BUSMON_3_SECTION 0x1000
+#define mmDCORE0_TPC3_QM_ARC_RTT_BASE 0x60B000ull
+#define DCORE0_TPC3_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE0_TPC3_QM_ARC_RTT_SECTION 0x35000
+#define mmDCORE0_TPC3_EML_CFG_BASE 0x640000ull
+#define DCORE0_TPC3_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC3_EML_CFG_SECTION 0xE800
+#define mmDCORE0_TPC3_EML_CFG_SPECIAL_BASE 0x640E80ull
+#define DCORE0_TPC3_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC3_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x641000ull
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC3_EML_TPC_CFG_BASE 0x641000ull
+#define DCORE0_TPC3_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC3_EML_TPC_CFG_SECTION 0x5000
+#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x641050ull
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x6410A0ull
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x6410F0ull
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x641140ull
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x641190ull
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x6411E0ull
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x641230ull
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x641280ull
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x6412D0ull
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x641320ull
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x641370ull
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x6413C0ull
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x641410ull
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x641460ull
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x6414B0ull
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x641500ull
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_BASE 0x641508ull
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_0_BASE 0x6415DCull
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_1_BASE 0x64162Cull
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_2_BASE 0x64167Cull
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_3_BASE 0x6416CCull
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_4_BASE 0x64171Cull
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_5_BASE 0x64176Cull
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_6_BASE 0x6417BCull
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_7_BASE 0x64180Cull
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_8_BASE 0x64185Cull
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_9_BASE 0x6418ACull
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_10_BASE 0x6418FCull
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_11_BASE 0x64194Cull
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_12_BASE 0x64199Cull
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_13_BASE 0x6419ECull
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_14_BASE 0x641A3Cull
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_15_BASE 0x641A8Cull
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE0_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x641ADCull
+#define DCORE0_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE0_TPC3_EML_TPC_CFG_QM_BASE 0x641AE4ull
+#define DCORE0_TPC3_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE0_TPC3_EML_TPC_CFG_QM_SECTION 0x31C0
+#define mmDCORE0_TPC3_EML_TPC_CFG_AXUSER_BASE 0x641E00ull
+#define DCORE0_TPC3_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE0_TPC3_EML_TPC_CFG_SPECIAL_BASE 0x641E80ull
+#define DCORE0_TPC3_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC3_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC3_EML_QM_DCCM_BASE 0x642000ull
+#define DCORE0_TPC3_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE0_TPC3_EML_QM_DCCM_SECTION 0x8000
+#define mmDCORE0_TPC3_EML_QM_ARCAUX_BASE 0x64A000ull
+#define DCORE0_TPC3_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE0_TPC3_EML_QM_ARCAUX_SECTION 0xE800
+#define mmDCORE0_TPC3_EML_QM_ARCAUX_SPECIAL_BASE 0x64AE80ull
+#define DCORE0_TPC3_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC3_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define mmDCORE0_TPC3_EML_TPC_QM_BASE 0x64C000ull
+#define DCORE0_TPC3_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE0_TPC3_EML_TPC_QM_SECTION 0x9000
+#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x64C900ull
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x64C908ull
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x64C910ull
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x64C918ull
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x64C920ull
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x64C928ull
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x64C930ull
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x64C938ull
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x64C940ull
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x64C948ull
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x64C950ull
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x64C958ull
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x64C960ull
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x64C968ull
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x64C970ull
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x64C978ull
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE0_TPC3_EML_TPC_QM_AXUSER_SECURED_BASE 0x64CB00ull
+#define DCORE0_TPC3_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE0_TPC3_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x64CB80ull
+#define DCORE0_TPC3_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE0_TPC3_EML_TPC_QM_DBG_HBW_BASE 0x64CC00ull
+#define DCORE0_TPC3_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC3_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_TPC3_EML_TPC_QM_DBG_LBW_BASE 0x64CC80ull
+#define DCORE0_TPC3_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC3_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE0_TPC3_EML_TPC_QM_CGM_BASE 0x64CD80ull
+#define DCORE0_TPC3_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE0_TPC3_EML_TPC_QM_CGM_SECTION 0x1000
+#define mmDCORE0_TPC3_EML_TPC_QM_SPECIAL_BASE 0x64CE80ull
+#define DCORE0_TPC3_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC3_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define mmDCORE0_TPC3_EML_CS_BASE 0x7FF000ull
+#define DCORE0_TPC3_EML_CS_MAX_OFFSET 0x1000
+#define DCORE0_TPC3_EML_CS_SECTION 0x1000
+#define mmDCORE0_TPC4_ROM_TABLE_BASE 0x800000ull
+#define DCORE0_TPC4_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE0_TPC4_ROM_TABLE_SECTION 0x1000
+#define mmDCORE0_TPC4_EML_SPMU_BASE 0x801000ull
+#define DCORE0_TPC4_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_TPC4_EML_SPMU_SECTION 0x1000
+#define mmDCORE0_TPC4_EML_ETF_BASE 0x802000ull
+#define DCORE0_TPC4_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE0_TPC4_EML_ETF_SECTION 0x1000
+#define mmDCORE0_TPC4_EML_STM_BASE 0x803000ull
+#define DCORE0_TPC4_EML_STM_MAX_OFFSET 0x1000
+#define DCORE0_TPC4_EML_STM_SECTION 0x2000
+#define mmDCORE0_TPC4_EML_CTI_BASE 0x805000ull
+#define DCORE0_TPC4_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE0_TPC4_EML_CTI_SECTION 0x1000
+#define mmDCORE0_TPC4_EML_FUNNEL_BASE 0x806000ull
+#define DCORE0_TPC4_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_TPC4_EML_FUNNEL_SECTION 0x1000
+#define mmDCORE0_TPC4_EML_BUSMON_0_BASE 0x807000ull
+#define DCORE0_TPC4_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE0_TPC4_EML_BUSMON_0_SECTION 0x1000
+#define mmDCORE0_TPC4_EML_BUSMON_1_BASE 0x808000ull
+#define DCORE0_TPC4_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE0_TPC4_EML_BUSMON_1_SECTION 0x1000
+#define mmDCORE0_TPC4_EML_BUSMON_2_BASE 0x809000ull
+#define DCORE0_TPC4_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE0_TPC4_EML_BUSMON_2_SECTION 0x1000
+#define mmDCORE0_TPC4_EML_BUSMON_3_BASE 0x80A000ull
+#define DCORE0_TPC4_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE0_TPC4_EML_BUSMON_3_SECTION 0x1000
+#define mmDCORE0_TPC4_QM_ARC_RTT_BASE 0x80B000ull
+#define DCORE0_TPC4_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE0_TPC4_QM_ARC_RTT_SECTION 0x35000
+#define mmDCORE0_TPC4_EML_CFG_BASE 0x840000ull
+#define DCORE0_TPC4_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC4_EML_CFG_SECTION 0xE800
+#define mmDCORE0_TPC4_EML_CFG_SPECIAL_BASE 0x840E80ull
+#define DCORE0_TPC4_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC4_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x841000ull
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC4_EML_TPC_CFG_BASE 0x841000ull
+#define DCORE0_TPC4_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC4_EML_TPC_CFG_SECTION 0x5000
+#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x841050ull
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x8410A0ull
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x8410F0ull
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x841140ull
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x841190ull
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x8411E0ull
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x841230ull
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x841280ull
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x8412D0ull
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x841320ull
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x841370ull
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x8413C0ull
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x841410ull
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x841460ull
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x8414B0ull
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x841500ull
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_BASE 0x841508ull
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_0_BASE 0x8415DCull
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_1_BASE 0x84162Cull
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_2_BASE 0x84167Cull
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_3_BASE 0x8416CCull
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_4_BASE 0x84171Cull
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_5_BASE 0x84176Cull
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_6_BASE 0x8417BCull
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_7_BASE 0x84180Cull
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_8_BASE 0x84185Cull
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_9_BASE 0x8418ACull
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_10_BASE 0x8418FCull
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_11_BASE 0x84194Cull
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_12_BASE 0x84199Cull
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_13_BASE 0x8419ECull
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_14_BASE 0x841A3Cull
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_15_BASE 0x841A8Cull
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE0_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x841ADCull
+#define DCORE0_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE0_TPC4_EML_TPC_CFG_QM_BASE 0x841AE4ull
+#define DCORE0_TPC4_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE0_TPC4_EML_TPC_CFG_QM_SECTION 0x31C0
+#define mmDCORE0_TPC4_EML_TPC_CFG_AXUSER_BASE 0x841E00ull
+#define DCORE0_TPC4_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE0_TPC4_EML_TPC_CFG_SPECIAL_BASE 0x841E80ull
+#define DCORE0_TPC4_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC4_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC4_EML_QM_DCCM_BASE 0x842000ull
+#define DCORE0_TPC4_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE0_TPC4_EML_QM_DCCM_SECTION 0x8000
+#define mmDCORE0_TPC4_EML_QM_ARCAUX_BASE 0x84A000ull
+#define DCORE0_TPC4_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE0_TPC4_EML_QM_ARCAUX_SECTION 0xE800
+#define mmDCORE0_TPC4_EML_QM_ARCAUX_SPECIAL_BASE 0x84AE80ull
+#define DCORE0_TPC4_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC4_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define mmDCORE0_TPC4_EML_TPC_QM_BASE 0x84C000ull
+#define DCORE0_TPC4_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE0_TPC4_EML_TPC_QM_SECTION 0x9000
+#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x84C900ull
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x84C908ull
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x84C910ull
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x84C918ull
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x84C920ull
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x84C928ull
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x84C930ull
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x84C938ull
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x84C940ull
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x84C948ull
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x84C950ull
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x84C958ull
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x84C960ull
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x84C968ull
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x84C970ull
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x84C978ull
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE0_TPC4_EML_TPC_QM_AXUSER_SECURED_BASE 0x84CB00ull
+#define DCORE0_TPC4_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE0_TPC4_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x84CB80ull
+#define DCORE0_TPC4_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE0_TPC4_EML_TPC_QM_DBG_HBW_BASE 0x84CC00ull
+#define DCORE0_TPC4_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC4_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_TPC4_EML_TPC_QM_DBG_LBW_BASE 0x84CC80ull
+#define DCORE0_TPC4_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC4_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE0_TPC4_EML_TPC_QM_CGM_BASE 0x84CD80ull
+#define DCORE0_TPC4_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE0_TPC4_EML_TPC_QM_CGM_SECTION 0x1000
+#define mmDCORE0_TPC4_EML_TPC_QM_SPECIAL_BASE 0x84CE80ull
+#define DCORE0_TPC4_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC4_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define mmDCORE0_TPC4_EML_CS_BASE 0x9FF000ull
+#define DCORE0_TPC4_EML_CS_MAX_OFFSET 0x1000
+#define DCORE0_TPC4_EML_CS_SECTION 0x1000
+#define mmDCORE0_TPC5_ROM_TABLE_BASE 0xA00000ull
+#define DCORE0_TPC5_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE0_TPC5_ROM_TABLE_SECTION 0x1000
+#define mmDCORE0_TPC5_EML_SPMU_BASE 0xA01000ull
+#define DCORE0_TPC5_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_TPC5_EML_SPMU_SECTION 0x1000
+#define mmDCORE0_TPC5_EML_ETF_BASE 0xA02000ull
+#define DCORE0_TPC5_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE0_TPC5_EML_ETF_SECTION 0x1000
+#define mmDCORE0_TPC5_EML_STM_BASE 0xA03000ull
+#define DCORE0_TPC5_EML_STM_MAX_OFFSET 0x1000
+#define DCORE0_TPC5_EML_STM_SECTION 0x2000
+#define mmDCORE0_TPC5_EML_CTI_BASE 0xA05000ull
+#define DCORE0_TPC5_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE0_TPC5_EML_CTI_SECTION 0x1000
+#define mmDCORE0_TPC5_EML_FUNNEL_BASE 0xA06000ull
+#define DCORE0_TPC5_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_TPC5_EML_FUNNEL_SECTION 0x1000
+#define mmDCORE0_TPC5_EML_BUSMON_0_BASE 0xA07000ull
+#define DCORE0_TPC5_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE0_TPC5_EML_BUSMON_0_SECTION 0x1000
+#define mmDCORE0_TPC5_EML_BUSMON_1_BASE 0xA08000ull
+#define DCORE0_TPC5_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE0_TPC5_EML_BUSMON_1_SECTION 0x1000
+#define mmDCORE0_TPC5_EML_BUSMON_2_BASE 0xA09000ull
+#define DCORE0_TPC5_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE0_TPC5_EML_BUSMON_2_SECTION 0x1000
+#define mmDCORE0_TPC5_EML_BUSMON_3_BASE 0xA0A000ull
+#define DCORE0_TPC5_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE0_TPC5_EML_BUSMON_3_SECTION 0x1000
+#define mmDCORE0_TPC5_QM_ARC_RTT_BASE 0xA0B000ull
+#define DCORE0_TPC5_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE0_TPC5_QM_ARC_RTT_SECTION 0x35000
+#define mmDCORE0_TPC5_EML_CFG_BASE 0xA40000ull
+#define DCORE0_TPC5_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC5_EML_CFG_SECTION 0xE800
+#define mmDCORE0_TPC5_EML_CFG_SPECIAL_BASE 0xA40E80ull
+#define DCORE0_TPC5_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC5_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0xA41000ull
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC5_EML_TPC_CFG_BASE 0xA41000ull
+#define DCORE0_TPC5_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC5_EML_TPC_CFG_SECTION 0x5000
+#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0xA41050ull
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0xA410A0ull
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0xA410F0ull
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0xA41140ull
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0xA41190ull
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0xA411E0ull
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0xA41230ull
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0xA41280ull
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0xA412D0ull
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0xA41320ull
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0xA41370ull
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0xA413C0ull
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0xA41410ull
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0xA41460ull
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0xA414B0ull
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0xA41500ull
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_BASE 0xA41508ull
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_0_BASE 0xA415DCull
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_1_BASE 0xA4162Cull
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_2_BASE 0xA4167Cull
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_3_BASE 0xA416CCull
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_4_BASE 0xA4171Cull
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_5_BASE 0xA4176Cull
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_6_BASE 0xA417BCull
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_7_BASE 0xA4180Cull
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_8_BASE 0xA4185Cull
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_9_BASE 0xA418ACull
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_10_BASE 0xA418FCull
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_11_BASE 0xA4194Cull
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_12_BASE 0xA4199Cull
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_13_BASE 0xA419ECull
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_14_BASE 0xA41A3Cull
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_15_BASE 0xA41A8Cull
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE0_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0xA41ADCull
+#define DCORE0_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE0_TPC5_EML_TPC_CFG_QM_BASE 0xA41AE4ull
+#define DCORE0_TPC5_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE0_TPC5_EML_TPC_CFG_QM_SECTION 0x31C0
+#define mmDCORE0_TPC5_EML_TPC_CFG_AXUSER_BASE 0xA41E00ull
+#define DCORE0_TPC5_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE0_TPC5_EML_TPC_CFG_SPECIAL_BASE 0xA41E80ull
+#define DCORE0_TPC5_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC5_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC5_EML_QM_DCCM_BASE 0xA42000ull
+#define DCORE0_TPC5_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE0_TPC5_EML_QM_DCCM_SECTION 0x8000
+#define mmDCORE0_TPC5_EML_QM_ARCAUX_BASE 0xA4A000ull
+#define DCORE0_TPC5_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE0_TPC5_EML_QM_ARCAUX_SECTION 0xE800
+#define mmDCORE0_TPC5_EML_QM_ARCAUX_SPECIAL_BASE 0xA4AE80ull
+#define DCORE0_TPC5_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC5_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define mmDCORE0_TPC5_EML_TPC_QM_BASE 0xA4C000ull
+#define DCORE0_TPC5_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE0_TPC5_EML_TPC_QM_SECTION 0x9000
+#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0xA4C900ull
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0xA4C908ull
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0xA4C910ull
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0xA4C918ull
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0xA4C920ull
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0xA4C928ull
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0xA4C930ull
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0xA4C938ull
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0xA4C940ull
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0xA4C948ull
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0xA4C950ull
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0xA4C958ull
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0xA4C960ull
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0xA4C968ull
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0xA4C970ull
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0xA4C978ull
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE0_TPC5_EML_TPC_QM_AXUSER_SECURED_BASE 0xA4CB00ull
+#define DCORE0_TPC5_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE0_TPC5_EML_TPC_QM_AXUSER_NONSECURED_BASE 0xA4CB80ull
+#define DCORE0_TPC5_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE0_TPC5_EML_TPC_QM_DBG_HBW_BASE 0xA4CC00ull
+#define DCORE0_TPC5_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC5_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_TPC5_EML_TPC_QM_DBG_LBW_BASE 0xA4CC80ull
+#define DCORE0_TPC5_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC5_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE0_TPC5_EML_TPC_QM_CGM_BASE 0xA4CD80ull
+#define DCORE0_TPC5_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE0_TPC5_EML_TPC_QM_CGM_SECTION 0x1000
+#define mmDCORE0_TPC5_EML_TPC_QM_SPECIAL_BASE 0xA4CE80ull
+#define DCORE0_TPC5_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC5_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define mmDCORE0_TPC5_EML_CS_BASE 0xBFF000ull
+#define DCORE0_TPC5_EML_CS_MAX_OFFSET 0x1000
+#define DCORE0_TPC5_EML_CS_SECTION 0x1000
+#define mmDCORE0_TPC6_ROM_TABLE_BASE 0xC00000ull
+#define DCORE0_TPC6_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE0_TPC6_ROM_TABLE_SECTION 0x1000
+#define mmDCORE0_TPC6_EML_SPMU_BASE 0xC01000ull
+#define DCORE0_TPC6_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_TPC6_EML_SPMU_SECTION 0x1000
+#define mmDCORE0_TPC6_EML_ETF_BASE 0xC02000ull
+#define DCORE0_TPC6_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE0_TPC6_EML_ETF_SECTION 0x1000
+#define mmDCORE0_TPC6_EML_STM_BASE 0xC03000ull
+#define DCORE0_TPC6_EML_STM_MAX_OFFSET 0x1000
+#define DCORE0_TPC6_EML_STM_SECTION 0x2000
+#define mmDCORE0_TPC6_EML_CTI_BASE 0xC05000ull
+#define DCORE0_TPC6_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE0_TPC6_EML_CTI_SECTION 0x1000
+#define mmDCORE0_TPC6_EML_FUNNEL_BASE 0xC06000ull
+#define DCORE0_TPC6_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_TPC6_EML_FUNNEL_SECTION 0x1000
+#define mmDCORE0_TPC6_EML_BUSMON_0_BASE 0xC07000ull
+#define DCORE0_TPC6_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE0_TPC6_EML_BUSMON_0_SECTION 0x1000
+#define mmDCORE0_TPC6_EML_BUSMON_1_BASE 0xC08000ull
+#define DCORE0_TPC6_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE0_TPC6_EML_BUSMON_1_SECTION 0x1000
+#define mmDCORE0_TPC6_EML_BUSMON_2_BASE 0xC09000ull
+#define DCORE0_TPC6_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE0_TPC6_EML_BUSMON_2_SECTION 0x1000
+#define mmDCORE0_TPC6_EML_BUSMON_3_BASE 0xC0A000ull
+#define DCORE0_TPC6_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE0_TPC6_EML_BUSMON_3_SECTION 0x1000
+#define mmDCORE0_TPC6_QM_ARC_RTT_BASE 0xC0B000ull
+#define DCORE0_TPC6_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE0_TPC6_QM_ARC_RTT_SECTION 0x35000
+#define mmDCORE0_TPC6_EML_CFG_BASE 0xC40000ull
+#define DCORE0_TPC6_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC6_EML_CFG_SECTION 0xE800
+#define mmDCORE0_TPC6_EML_CFG_SPECIAL_BASE 0xC40E80ull
+#define DCORE0_TPC6_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC6_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0xC41000ull
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC6_EML_TPC_CFG_BASE 0xC41000ull
+#define DCORE0_TPC6_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC6_EML_TPC_CFG_SECTION 0x5000
+#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0xC41050ull
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0xC410A0ull
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0xC410F0ull
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0xC41140ull
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0xC41190ull
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0xC411E0ull
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0xC41230ull
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0xC41280ull
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0xC412D0ull
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0xC41320ull
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0xC41370ull
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0xC413C0ull
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0xC41410ull
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0xC41460ull
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0xC414B0ull
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0xC41500ull
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_BASE 0xC41508ull
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_0_BASE 0xC415DCull
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_1_BASE 0xC4162Cull
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_2_BASE 0xC4167Cull
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_3_BASE 0xC416CCull
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_4_BASE 0xC4171Cull
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_5_BASE 0xC4176Cull
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_6_BASE 0xC417BCull
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_7_BASE 0xC4180Cull
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_8_BASE 0xC4185Cull
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_9_BASE 0xC418ACull
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_10_BASE 0xC418FCull
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_11_BASE 0xC4194Cull
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_12_BASE 0xC4199Cull
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_13_BASE 0xC419ECull
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_14_BASE 0xC41A3Cull
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_15_BASE 0xC41A8Cull
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE0_TPC6_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0xC41ADCull
+#define DCORE0_TPC6_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE0_TPC6_EML_TPC_CFG_QM_BASE 0xC41AE4ull
+#define DCORE0_TPC6_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE0_TPC6_EML_TPC_CFG_QM_SECTION 0x31C0
+#define mmDCORE0_TPC6_EML_TPC_CFG_AXUSER_BASE 0xC41E00ull
+#define DCORE0_TPC6_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE0_TPC6_EML_TPC_CFG_SPECIAL_BASE 0xC41E80ull
+#define DCORE0_TPC6_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC6_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC6_EML_QM_DCCM_BASE 0xC42000ull
+#define DCORE0_TPC6_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE0_TPC6_EML_QM_DCCM_SECTION 0x8000
+#define mmDCORE0_TPC6_EML_QM_ARCAUX_BASE 0xC4A000ull
+#define DCORE0_TPC6_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE0_TPC6_EML_QM_ARCAUX_SECTION 0xE800
+#define mmDCORE0_TPC6_EML_QM_ARCAUX_SPECIAL_BASE 0xC4AE80ull
+#define DCORE0_TPC6_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC6_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define mmDCORE0_TPC6_EML_TPC_QM_BASE 0xC4C000ull
+#define DCORE0_TPC6_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE0_TPC6_EML_TPC_QM_SECTION 0x9000
+#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0xC4C900ull
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0xC4C908ull
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0xC4C910ull
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0xC4C918ull
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0xC4C920ull
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0xC4C928ull
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0xC4C930ull
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0xC4C938ull
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0xC4C940ull
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0xC4C948ull
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0xC4C950ull
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0xC4C958ull
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0xC4C960ull
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0xC4C968ull
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0xC4C970ull
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0xC4C978ull
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE0_TPC6_EML_TPC_QM_AXUSER_SECURED_BASE 0xC4CB00ull
+#define DCORE0_TPC6_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE0_TPC6_EML_TPC_QM_AXUSER_NONSECURED_BASE 0xC4CB80ull
+#define DCORE0_TPC6_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE0_TPC6_EML_TPC_QM_DBG_HBW_BASE 0xC4CC00ull
+#define DCORE0_TPC6_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC6_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_TPC6_EML_TPC_QM_DBG_LBW_BASE 0xC4CC80ull
+#define DCORE0_TPC6_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC6_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE0_TPC6_EML_TPC_QM_CGM_BASE 0xC4CD80ull
+#define DCORE0_TPC6_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE0_TPC6_EML_TPC_QM_CGM_SECTION 0x1000
+#define mmDCORE0_TPC6_EML_TPC_QM_SPECIAL_BASE 0xC4CE80ull
+#define DCORE0_TPC6_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC6_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define mmDCORE0_TPC6_EML_CS_BASE 0xDFF000ull
+#define DCORE0_TPC6_EML_CS_MAX_OFFSET 0x1000
+#define DCORE0_TPC6_EML_CS_SECTION 0x201000
+#define mmDCORE1_TPC0_ROM_TABLE_BASE 0x1000000ull
+#define DCORE1_TPC0_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE1_TPC0_ROM_TABLE_SECTION 0x1000
+#define mmDCORE1_TPC0_EML_SPMU_BASE 0x1001000ull
+#define DCORE1_TPC0_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_TPC0_EML_SPMU_SECTION 0x1000
+#define mmDCORE1_TPC0_EML_ETF_BASE 0x1002000ull
+#define DCORE1_TPC0_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE1_TPC0_EML_ETF_SECTION 0x1000
+#define mmDCORE1_TPC0_EML_STM_BASE 0x1003000ull
+#define DCORE1_TPC0_EML_STM_MAX_OFFSET 0x1000
+#define DCORE1_TPC0_EML_STM_SECTION 0x2000
+#define mmDCORE1_TPC0_EML_CTI_BASE 0x1005000ull
+#define DCORE1_TPC0_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE1_TPC0_EML_CTI_SECTION 0x1000
+#define mmDCORE1_TPC0_EML_FUNNEL_BASE 0x1006000ull
+#define DCORE1_TPC0_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_TPC0_EML_FUNNEL_SECTION 0x1000
+#define mmDCORE1_TPC0_EML_BUSMON_0_BASE 0x1007000ull
+#define DCORE1_TPC0_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE1_TPC0_EML_BUSMON_0_SECTION 0x1000
+#define mmDCORE1_TPC0_EML_BUSMON_1_BASE 0x1008000ull
+#define DCORE1_TPC0_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE1_TPC0_EML_BUSMON_1_SECTION 0x1000
+#define mmDCORE1_TPC0_EML_BUSMON_2_BASE 0x1009000ull
+#define DCORE1_TPC0_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE1_TPC0_EML_BUSMON_2_SECTION 0x1000
+#define mmDCORE1_TPC0_EML_BUSMON_3_BASE 0x100A000ull
+#define DCORE1_TPC0_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE1_TPC0_EML_BUSMON_3_SECTION 0x1000
+#define mmDCORE1_TPC0_QM_ARC_RTT_BASE 0x100B000ull
+#define DCORE1_TPC0_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE1_TPC0_QM_ARC_RTT_SECTION 0x35000
+#define mmDCORE1_TPC0_EML_CFG_BASE 0x1040000ull
+#define DCORE1_TPC0_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE1_TPC0_EML_CFG_SECTION 0xE800
+#define mmDCORE1_TPC0_EML_CFG_SPECIAL_BASE 0x1040E80ull
+#define DCORE1_TPC0_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC0_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1041000ull
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE1_TPC0_EML_TPC_CFG_BASE 0x1041000ull
+#define DCORE1_TPC0_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE1_TPC0_EML_TPC_CFG_SECTION 0x5000
+#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1041050ull
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x10410A0ull
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x10410F0ull
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1041140ull
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1041190ull
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x10411E0ull
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1041230ull
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1041280ull
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x10412D0ull
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1041320ull
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1041370ull
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x10413C0ull
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1041410ull
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1041460ull
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x10414B0ull
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1041500ull
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_BASE 0x1041508ull
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_0_BASE 0x10415DCull
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_1_BASE 0x104162Cull
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_2_BASE 0x104167Cull
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_3_BASE 0x10416CCull
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_4_BASE 0x104171Cull
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_5_BASE 0x104176Cull
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_6_BASE 0x10417BCull
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_7_BASE 0x104180Cull
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_8_BASE 0x104185Cull
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_9_BASE 0x10418ACull
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_10_BASE 0x10418FCull
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_11_BASE 0x104194Cull
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_12_BASE 0x104199Cull
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_13_BASE 0x10419ECull
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1041A3Cull
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1041A8Cull
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE1_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1041ADCull
+#define DCORE1_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE1_TPC0_EML_TPC_CFG_QM_BASE 0x1041AE4ull
+#define DCORE1_TPC0_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE1_TPC0_EML_TPC_CFG_QM_SECTION 0x31C0
+#define mmDCORE1_TPC0_EML_TPC_CFG_AXUSER_BASE 0x1041E00ull
+#define DCORE1_TPC0_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE1_TPC0_EML_TPC_CFG_SPECIAL_BASE 0x1041E80ull
+#define DCORE1_TPC0_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC0_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE1_TPC0_EML_QM_DCCM_BASE 0x1042000ull
+#define DCORE1_TPC0_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE1_TPC0_EML_QM_DCCM_SECTION 0x8000
+#define mmDCORE1_TPC0_EML_QM_ARCAUX_BASE 0x104A000ull
+#define DCORE1_TPC0_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE1_TPC0_EML_QM_ARCAUX_SECTION 0xE800
+#define mmDCORE1_TPC0_EML_QM_ARCAUX_SPECIAL_BASE 0x104AE80ull
+#define DCORE1_TPC0_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC0_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define mmDCORE1_TPC0_EML_TPC_QM_BASE 0x104C000ull
+#define DCORE1_TPC0_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE1_TPC0_EML_TPC_QM_SECTION 0x9000
+#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x104C900ull
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x104C908ull
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x104C910ull
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x104C918ull
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x104C920ull
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x104C928ull
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x104C930ull
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x104C938ull
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x104C940ull
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x104C948ull
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x104C950ull
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x104C958ull
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x104C960ull
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x104C968ull
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x104C970ull
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x104C978ull
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE1_TPC0_EML_TPC_QM_AXUSER_SECURED_BASE 0x104CB00ull
+#define DCORE1_TPC0_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE1_TPC0_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x104CB80ull
+#define DCORE1_TPC0_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE1_TPC0_EML_TPC_QM_DBG_HBW_BASE 0x104CC00ull
+#define DCORE1_TPC0_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC0_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_TPC0_EML_TPC_QM_DBG_LBW_BASE 0x104CC80ull
+#define DCORE1_TPC0_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC0_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE1_TPC0_EML_TPC_QM_CGM_BASE 0x104CD80ull
+#define DCORE1_TPC0_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE1_TPC0_EML_TPC_QM_CGM_SECTION 0x1000
+#define mmDCORE1_TPC0_EML_TPC_QM_SPECIAL_BASE 0x104CE80ull
+#define DCORE1_TPC0_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC0_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define mmDCORE1_TPC0_EML_CS_BASE 0x11FF000ull
+#define DCORE1_TPC0_EML_CS_MAX_OFFSET 0x1000
+#define DCORE1_TPC0_EML_CS_SECTION 0x1000
+#define mmDCORE1_TPC1_ROM_TABLE_BASE 0x1200000ull
+#define DCORE1_TPC1_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE1_TPC1_ROM_TABLE_SECTION 0x1000
+#define mmDCORE1_TPC1_EML_SPMU_BASE 0x1201000ull
+#define DCORE1_TPC1_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_TPC1_EML_SPMU_SECTION 0x1000
+#define mmDCORE1_TPC1_EML_ETF_BASE 0x1202000ull
+#define DCORE1_TPC1_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE1_TPC1_EML_ETF_SECTION 0x1000
+#define mmDCORE1_TPC1_EML_STM_BASE 0x1203000ull
+#define DCORE1_TPC1_EML_STM_MAX_OFFSET 0x1000
+#define DCORE1_TPC1_EML_STM_SECTION 0x2000
+#define mmDCORE1_TPC1_EML_CTI_BASE 0x1205000ull
+#define DCORE1_TPC1_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE1_TPC1_EML_CTI_SECTION 0x1000
+#define mmDCORE1_TPC1_EML_FUNNEL_BASE 0x1206000ull
+#define DCORE1_TPC1_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_TPC1_EML_FUNNEL_SECTION 0x1000
+#define mmDCORE1_TPC1_EML_BUSMON_0_BASE 0x1207000ull
+#define DCORE1_TPC1_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE1_TPC1_EML_BUSMON_0_SECTION 0x1000
+#define mmDCORE1_TPC1_EML_BUSMON_1_BASE 0x1208000ull
+#define DCORE1_TPC1_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE1_TPC1_EML_BUSMON_1_SECTION 0x1000
+#define mmDCORE1_TPC1_EML_BUSMON_2_BASE 0x1209000ull
+#define DCORE1_TPC1_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE1_TPC1_EML_BUSMON_2_SECTION 0x1000
+#define mmDCORE1_TPC1_EML_BUSMON_3_BASE 0x120A000ull
+#define DCORE1_TPC1_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE1_TPC1_EML_BUSMON_3_SECTION 0x1000
+#define mmDCORE1_TPC1_QM_ARC_RTT_BASE 0x120B000ull
+#define DCORE1_TPC1_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE1_TPC1_QM_ARC_RTT_SECTION 0x35000
+#define mmDCORE1_TPC1_EML_CFG_BASE 0x1240000ull
+#define DCORE1_TPC1_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE1_TPC1_EML_CFG_SECTION 0xE800
+#define mmDCORE1_TPC1_EML_CFG_SPECIAL_BASE 0x1240E80ull
+#define DCORE1_TPC1_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC1_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1241000ull
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE1_TPC1_EML_TPC_CFG_BASE 0x1241000ull
+#define DCORE1_TPC1_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE1_TPC1_EML_TPC_CFG_SECTION 0x5000
+#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1241050ull
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x12410A0ull
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x12410F0ull
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1241140ull
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1241190ull
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x12411E0ull
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1241230ull
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1241280ull
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x12412D0ull
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1241320ull
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1241370ull
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x12413C0ull
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1241410ull
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1241460ull
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x12414B0ull
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1241500ull
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_BASE 0x1241508ull
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_0_BASE 0x12415DCull
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_1_BASE 0x124162Cull
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_2_BASE 0x124167Cull
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_3_BASE 0x12416CCull
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_4_BASE 0x124171Cull
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_5_BASE 0x124176Cull
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_6_BASE 0x12417BCull
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_7_BASE 0x124180Cull
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_8_BASE 0x124185Cull
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_9_BASE 0x12418ACull
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_10_BASE 0x12418FCull
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_11_BASE 0x124194Cull
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_12_BASE 0x124199Cull
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_13_BASE 0x12419ECull
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1241A3Cull
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1241A8Cull
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE1_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1241ADCull
+#define DCORE1_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE1_TPC1_EML_TPC_CFG_QM_BASE 0x1241AE4ull
+#define DCORE1_TPC1_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE1_TPC1_EML_TPC_CFG_QM_SECTION 0x31C0
+#define mmDCORE1_TPC1_EML_TPC_CFG_AXUSER_BASE 0x1241E00ull
+#define DCORE1_TPC1_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE1_TPC1_EML_TPC_CFG_SPECIAL_BASE 0x1241E80ull
+#define DCORE1_TPC1_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC1_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE1_TPC1_EML_QM_DCCM_BASE 0x1242000ull
+#define DCORE1_TPC1_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE1_TPC1_EML_QM_DCCM_SECTION 0x8000
+#define mmDCORE1_TPC1_EML_QM_ARCAUX_BASE 0x124A000ull
+#define DCORE1_TPC1_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE1_TPC1_EML_QM_ARCAUX_SECTION 0xE800
+#define mmDCORE1_TPC1_EML_QM_ARCAUX_SPECIAL_BASE 0x124AE80ull
+#define DCORE1_TPC1_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC1_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define mmDCORE1_TPC1_EML_TPC_QM_BASE 0x124C000ull
+#define DCORE1_TPC1_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE1_TPC1_EML_TPC_QM_SECTION 0x9000
+#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x124C900ull
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x124C908ull
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x124C910ull
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x124C918ull
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x124C920ull
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x124C928ull
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x124C930ull
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x124C938ull
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x124C940ull
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x124C948ull
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x124C950ull
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x124C958ull
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x124C960ull
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x124C968ull
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x124C970ull
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x124C978ull
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE1_TPC1_EML_TPC_QM_AXUSER_SECURED_BASE 0x124CB00ull
+#define DCORE1_TPC1_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE1_TPC1_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x124CB80ull
+#define DCORE1_TPC1_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE1_TPC1_EML_TPC_QM_DBG_HBW_BASE 0x124CC00ull
+#define DCORE1_TPC1_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC1_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_TPC1_EML_TPC_QM_DBG_LBW_BASE 0x124CC80ull
+#define DCORE1_TPC1_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC1_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE1_TPC1_EML_TPC_QM_CGM_BASE 0x124CD80ull
+#define DCORE1_TPC1_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE1_TPC1_EML_TPC_QM_CGM_SECTION 0x1000
+#define mmDCORE1_TPC1_EML_TPC_QM_SPECIAL_BASE 0x124CE80ull
+#define DCORE1_TPC1_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC1_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define mmDCORE1_TPC1_EML_CS_BASE 0x13FF000ull
+#define DCORE1_TPC1_EML_CS_MAX_OFFSET 0x1000
+#define DCORE1_TPC1_EML_CS_SECTION 0x1000
+#define mmDCORE1_TPC2_ROM_TABLE_BASE 0x1400000ull
+#define DCORE1_TPC2_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE1_TPC2_ROM_TABLE_SECTION 0x1000
+#define mmDCORE1_TPC2_EML_SPMU_BASE 0x1401000ull
+#define DCORE1_TPC2_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_TPC2_EML_SPMU_SECTION 0x1000
+#define mmDCORE1_TPC2_EML_ETF_BASE 0x1402000ull
+#define DCORE1_TPC2_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE1_TPC2_EML_ETF_SECTION 0x1000
+#define mmDCORE1_TPC2_EML_STM_BASE 0x1403000ull
+#define DCORE1_TPC2_EML_STM_MAX_OFFSET 0x1000
+#define DCORE1_TPC2_EML_STM_SECTION 0x2000
+#define mmDCORE1_TPC2_EML_CTI_BASE 0x1405000ull
+#define DCORE1_TPC2_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE1_TPC2_EML_CTI_SECTION 0x1000
+#define mmDCORE1_TPC2_EML_FUNNEL_BASE 0x1406000ull
+#define DCORE1_TPC2_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_TPC2_EML_FUNNEL_SECTION 0x1000
+#define mmDCORE1_TPC2_EML_BUSMON_0_BASE 0x1407000ull
+#define DCORE1_TPC2_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE1_TPC2_EML_BUSMON_0_SECTION 0x1000
+#define mmDCORE1_TPC2_EML_BUSMON_1_BASE 0x1408000ull
+#define DCORE1_TPC2_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE1_TPC2_EML_BUSMON_1_SECTION 0x1000
+#define mmDCORE1_TPC2_EML_BUSMON_2_BASE 0x1409000ull
+#define DCORE1_TPC2_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE1_TPC2_EML_BUSMON_2_SECTION 0x1000
+#define mmDCORE1_TPC2_EML_BUSMON_3_BASE 0x140A000ull
+#define DCORE1_TPC2_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE1_TPC2_EML_BUSMON_3_SECTION 0x1000
+#define mmDCORE1_TPC2_QM_ARC_RTT_BASE 0x140B000ull
+#define DCORE1_TPC2_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE1_TPC2_QM_ARC_RTT_SECTION 0x35000
+#define mmDCORE1_TPC2_EML_CFG_BASE 0x1440000ull
+#define DCORE1_TPC2_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE1_TPC2_EML_CFG_SECTION 0xE800
+#define mmDCORE1_TPC2_EML_CFG_SPECIAL_BASE 0x1440E80ull
+#define DCORE1_TPC2_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC2_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1441000ull
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE1_TPC2_EML_TPC_CFG_BASE 0x1441000ull
+#define DCORE1_TPC2_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE1_TPC2_EML_TPC_CFG_SECTION 0x5000
+#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1441050ull
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x14410A0ull
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x14410F0ull
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1441140ull
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1441190ull
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x14411E0ull
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1441230ull
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1441280ull
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x14412D0ull
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1441320ull
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1441370ull
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x14413C0ull
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1441410ull
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1441460ull
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x14414B0ull
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1441500ull
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_BASE 0x1441508ull
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_0_BASE 0x14415DCull
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_1_BASE 0x144162Cull
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_2_BASE 0x144167Cull
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_3_BASE 0x14416CCull
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_4_BASE 0x144171Cull
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_5_BASE 0x144176Cull
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_6_BASE 0x14417BCull
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_7_BASE 0x144180Cull
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_8_BASE 0x144185Cull
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_9_BASE 0x14418ACull
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_10_BASE 0x14418FCull
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_11_BASE 0x144194Cull
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_12_BASE 0x144199Cull
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_13_BASE 0x14419ECull
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1441A3Cull
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1441A8Cull
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE1_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1441ADCull
+#define DCORE1_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE1_TPC2_EML_TPC_CFG_QM_BASE 0x1441AE4ull
+#define DCORE1_TPC2_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE1_TPC2_EML_TPC_CFG_QM_SECTION 0x31C0
+#define mmDCORE1_TPC2_EML_TPC_CFG_AXUSER_BASE 0x1441E00ull
+#define DCORE1_TPC2_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE1_TPC2_EML_TPC_CFG_SPECIAL_BASE 0x1441E80ull
+#define DCORE1_TPC2_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC2_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE1_TPC2_EML_QM_DCCM_BASE 0x1442000ull
+#define DCORE1_TPC2_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE1_TPC2_EML_QM_DCCM_SECTION 0x8000
+#define mmDCORE1_TPC2_EML_QM_ARCAUX_BASE 0x144A000ull
+#define DCORE1_TPC2_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE1_TPC2_EML_QM_ARCAUX_SECTION 0xE800
+#define mmDCORE1_TPC2_EML_QM_ARCAUX_SPECIAL_BASE 0x144AE80ull
+#define DCORE1_TPC2_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC2_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define mmDCORE1_TPC2_EML_TPC_QM_BASE 0x144C000ull
+#define DCORE1_TPC2_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE1_TPC2_EML_TPC_QM_SECTION 0x9000
+#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x144C900ull
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x144C908ull
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x144C910ull
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x144C918ull
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x144C920ull
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x144C928ull
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x144C930ull
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x144C938ull
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x144C940ull
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x144C948ull
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x144C950ull
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x144C958ull
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x144C960ull
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x144C968ull
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x144C970ull
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x144C978ull
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE1_TPC2_EML_TPC_QM_AXUSER_SECURED_BASE 0x144CB00ull
+#define DCORE1_TPC2_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE1_TPC2_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x144CB80ull
+#define DCORE1_TPC2_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE1_TPC2_EML_TPC_QM_DBG_HBW_BASE 0x144CC00ull
+#define DCORE1_TPC2_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC2_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_TPC2_EML_TPC_QM_DBG_LBW_BASE 0x144CC80ull
+#define DCORE1_TPC2_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC2_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE1_TPC2_EML_TPC_QM_CGM_BASE 0x144CD80ull
+#define DCORE1_TPC2_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE1_TPC2_EML_TPC_QM_CGM_SECTION 0x1000
+#define mmDCORE1_TPC2_EML_TPC_QM_SPECIAL_BASE 0x144CE80ull
+#define DCORE1_TPC2_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC2_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define mmDCORE1_TPC2_EML_CS_BASE 0x15FF000ull
+#define DCORE1_TPC2_EML_CS_MAX_OFFSET 0x1000
+#define DCORE1_TPC2_EML_CS_SECTION 0x1000
+#define mmDCORE1_TPC3_ROM_TABLE_BASE 0x1600000ull
+#define DCORE1_TPC3_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE1_TPC3_ROM_TABLE_SECTION 0x1000
+#define mmDCORE1_TPC3_EML_SPMU_BASE 0x1601000ull
+#define DCORE1_TPC3_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_TPC3_EML_SPMU_SECTION 0x1000
+#define mmDCORE1_TPC3_EML_ETF_BASE 0x1602000ull
+#define DCORE1_TPC3_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE1_TPC3_EML_ETF_SECTION 0x1000
+#define mmDCORE1_TPC3_EML_STM_BASE 0x1603000ull
+#define DCORE1_TPC3_EML_STM_MAX_OFFSET 0x1000
+#define DCORE1_TPC3_EML_STM_SECTION 0x2000
+#define mmDCORE1_TPC3_EML_CTI_BASE 0x1605000ull
+#define DCORE1_TPC3_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE1_TPC3_EML_CTI_SECTION 0x1000
+#define mmDCORE1_TPC3_EML_FUNNEL_BASE 0x1606000ull
+#define DCORE1_TPC3_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_TPC3_EML_FUNNEL_SECTION 0x1000
+#define mmDCORE1_TPC3_EML_BUSMON_0_BASE 0x1607000ull
+#define DCORE1_TPC3_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE1_TPC3_EML_BUSMON_0_SECTION 0x1000
+#define mmDCORE1_TPC3_EML_BUSMON_1_BASE 0x1608000ull
+#define DCORE1_TPC3_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE1_TPC3_EML_BUSMON_1_SECTION 0x1000
+#define mmDCORE1_TPC3_EML_BUSMON_2_BASE 0x1609000ull
+#define DCORE1_TPC3_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE1_TPC3_EML_BUSMON_2_SECTION 0x1000
+#define mmDCORE1_TPC3_EML_BUSMON_3_BASE 0x160A000ull
+#define DCORE1_TPC3_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE1_TPC3_EML_BUSMON_3_SECTION 0x1000
+#define mmDCORE1_TPC3_QM_ARC_RTT_BASE 0x160B000ull
+#define DCORE1_TPC3_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE1_TPC3_QM_ARC_RTT_SECTION 0x35000
+#define mmDCORE1_TPC3_EML_CFG_BASE 0x1640000ull
+#define DCORE1_TPC3_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE1_TPC3_EML_CFG_SECTION 0xE800
+#define mmDCORE1_TPC3_EML_CFG_SPECIAL_BASE 0x1640E80ull
+#define DCORE1_TPC3_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC3_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1641000ull
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE1_TPC3_EML_TPC_CFG_BASE 0x1641000ull
+#define DCORE1_TPC3_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE1_TPC3_EML_TPC_CFG_SECTION 0x5000
+#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1641050ull
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x16410A0ull
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x16410F0ull
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1641140ull
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1641190ull
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x16411E0ull
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1641230ull
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1641280ull
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x16412D0ull
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1641320ull
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1641370ull
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x16413C0ull
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1641410ull
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1641460ull
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x16414B0ull
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1641500ull
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_BASE 0x1641508ull
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_0_BASE 0x16415DCull
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_1_BASE 0x164162Cull
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_2_BASE 0x164167Cull
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_3_BASE 0x16416CCull
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_4_BASE 0x164171Cull
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_5_BASE 0x164176Cull
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_6_BASE 0x16417BCull
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_7_BASE 0x164180Cull
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_8_BASE 0x164185Cull
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_9_BASE 0x16418ACull
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_10_BASE 0x16418FCull
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_11_BASE 0x164194Cull
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_12_BASE 0x164199Cull
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_13_BASE 0x16419ECull
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1641A3Cull
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1641A8Cull
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE1_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1641ADCull
+#define DCORE1_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE1_TPC3_EML_TPC_CFG_QM_BASE 0x1641AE4ull
+#define DCORE1_TPC3_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE1_TPC3_EML_TPC_CFG_QM_SECTION 0x31C0
+#define mmDCORE1_TPC3_EML_TPC_CFG_AXUSER_BASE 0x1641E00ull
+#define DCORE1_TPC3_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE1_TPC3_EML_TPC_CFG_SPECIAL_BASE 0x1641E80ull
+#define DCORE1_TPC3_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC3_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE1_TPC3_EML_QM_DCCM_BASE 0x1642000ull
+#define DCORE1_TPC3_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE1_TPC3_EML_QM_DCCM_SECTION 0x8000
+#define mmDCORE1_TPC3_EML_QM_ARCAUX_BASE 0x164A000ull
+#define DCORE1_TPC3_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE1_TPC3_EML_QM_ARCAUX_SECTION 0xE800
+#define mmDCORE1_TPC3_EML_QM_ARCAUX_SPECIAL_BASE 0x164AE80ull
+#define DCORE1_TPC3_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC3_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define mmDCORE1_TPC3_EML_TPC_QM_BASE 0x164C000ull
+#define DCORE1_TPC3_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE1_TPC3_EML_TPC_QM_SECTION 0x9000
+#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x164C900ull
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x164C908ull
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x164C910ull
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x164C918ull
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x164C920ull
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x164C928ull
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x164C930ull
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x164C938ull
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x164C940ull
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x164C948ull
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x164C950ull
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x164C958ull
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x164C960ull
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x164C968ull
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x164C970ull
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x164C978ull
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE1_TPC3_EML_TPC_QM_AXUSER_SECURED_BASE 0x164CB00ull
+#define DCORE1_TPC3_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE1_TPC3_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x164CB80ull
+#define DCORE1_TPC3_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE1_TPC3_EML_TPC_QM_DBG_HBW_BASE 0x164CC00ull
+#define DCORE1_TPC3_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC3_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_TPC3_EML_TPC_QM_DBG_LBW_BASE 0x164CC80ull
+#define DCORE1_TPC3_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC3_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE1_TPC3_EML_TPC_QM_CGM_BASE 0x164CD80ull
+#define DCORE1_TPC3_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE1_TPC3_EML_TPC_QM_CGM_SECTION 0x1000
+#define mmDCORE1_TPC3_EML_TPC_QM_SPECIAL_BASE 0x164CE80ull
+#define DCORE1_TPC3_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC3_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define mmDCORE1_TPC3_EML_CS_BASE 0x17FF000ull
+#define DCORE1_TPC3_EML_CS_MAX_OFFSET 0x1000
+#define DCORE1_TPC3_EML_CS_SECTION 0x1000
+#define mmDCORE1_TPC4_ROM_TABLE_BASE 0x1800000ull
+#define DCORE1_TPC4_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE1_TPC4_ROM_TABLE_SECTION 0x1000
+#define mmDCORE1_TPC4_EML_SPMU_BASE 0x1801000ull
+#define DCORE1_TPC4_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_TPC4_EML_SPMU_SECTION 0x1000
+#define mmDCORE1_TPC4_EML_ETF_BASE 0x1802000ull
+#define DCORE1_TPC4_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE1_TPC4_EML_ETF_SECTION 0x1000
+#define mmDCORE1_TPC4_EML_STM_BASE 0x1803000ull
+#define DCORE1_TPC4_EML_STM_MAX_OFFSET 0x1000
+#define DCORE1_TPC4_EML_STM_SECTION 0x2000
+#define mmDCORE1_TPC4_EML_CTI_BASE 0x1805000ull
+#define DCORE1_TPC4_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE1_TPC4_EML_CTI_SECTION 0x1000
+#define mmDCORE1_TPC4_EML_FUNNEL_BASE 0x1806000ull
+#define DCORE1_TPC4_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_TPC4_EML_FUNNEL_SECTION 0x1000
+#define mmDCORE1_TPC4_EML_BUSMON_0_BASE 0x1807000ull
+#define DCORE1_TPC4_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE1_TPC4_EML_BUSMON_0_SECTION 0x1000
+#define mmDCORE1_TPC4_EML_BUSMON_1_BASE 0x1808000ull
+#define DCORE1_TPC4_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE1_TPC4_EML_BUSMON_1_SECTION 0x1000
+#define mmDCORE1_TPC4_EML_BUSMON_2_BASE 0x1809000ull
+#define DCORE1_TPC4_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE1_TPC4_EML_BUSMON_2_SECTION 0x1000
+#define mmDCORE1_TPC4_EML_BUSMON_3_BASE 0x180A000ull
+#define DCORE1_TPC4_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE1_TPC4_EML_BUSMON_3_SECTION 0x1000
+#define mmDCORE1_TPC4_QM_ARC_RTT_BASE 0x180B000ull
+#define DCORE1_TPC4_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE1_TPC4_QM_ARC_RTT_SECTION 0x35000
+#define mmDCORE1_TPC4_EML_CFG_BASE 0x1840000ull
+#define DCORE1_TPC4_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE1_TPC4_EML_CFG_SECTION 0xE800
+#define mmDCORE1_TPC4_EML_CFG_SPECIAL_BASE 0x1840E80ull
+#define DCORE1_TPC4_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC4_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1841000ull
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE1_TPC4_EML_TPC_CFG_BASE 0x1841000ull
+#define DCORE1_TPC4_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE1_TPC4_EML_TPC_CFG_SECTION 0x5000
+#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1841050ull
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x18410A0ull
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x18410F0ull
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1841140ull
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1841190ull
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x18411E0ull
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1841230ull
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1841280ull
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x18412D0ull
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1841320ull
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1841370ull
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x18413C0ull
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1841410ull
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1841460ull
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x18414B0ull
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1841500ull
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_BASE 0x1841508ull
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_0_BASE 0x18415DCull
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_1_BASE 0x184162Cull
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_2_BASE 0x184167Cull
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_3_BASE 0x18416CCull
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_4_BASE 0x184171Cull
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_5_BASE 0x184176Cull
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_6_BASE 0x18417BCull
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_7_BASE 0x184180Cull
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_8_BASE 0x184185Cull
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_9_BASE 0x18418ACull
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_10_BASE 0x18418FCull
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_11_BASE 0x184194Cull
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_12_BASE 0x184199Cull
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_13_BASE 0x18419ECull
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1841A3Cull
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1841A8Cull
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE1_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1841ADCull
+#define DCORE1_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE1_TPC4_EML_TPC_CFG_QM_BASE 0x1841AE4ull
+#define DCORE1_TPC4_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE1_TPC4_EML_TPC_CFG_QM_SECTION 0x31C0
+#define mmDCORE1_TPC4_EML_TPC_CFG_AXUSER_BASE 0x1841E00ull
+#define DCORE1_TPC4_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE1_TPC4_EML_TPC_CFG_SPECIAL_BASE 0x1841E80ull
+#define DCORE1_TPC4_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC4_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE1_TPC4_EML_QM_DCCM_BASE 0x1842000ull
+#define DCORE1_TPC4_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE1_TPC4_EML_QM_DCCM_SECTION 0x8000
+#define mmDCORE1_TPC4_EML_QM_ARCAUX_BASE 0x184A000ull
+#define DCORE1_TPC4_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE1_TPC4_EML_QM_ARCAUX_SECTION 0xE800
+#define mmDCORE1_TPC4_EML_QM_ARCAUX_SPECIAL_BASE 0x184AE80ull
+#define DCORE1_TPC4_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC4_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define mmDCORE1_TPC4_EML_TPC_QM_BASE 0x184C000ull
+#define DCORE1_TPC4_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE1_TPC4_EML_TPC_QM_SECTION 0x9000
+#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x184C900ull
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x184C908ull
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x184C910ull
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x184C918ull
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x184C920ull
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x184C928ull
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x184C930ull
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x184C938ull
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x184C940ull
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x184C948ull
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x184C950ull
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x184C958ull
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x184C960ull
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x184C968ull
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x184C970ull
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x184C978ull
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE1_TPC4_EML_TPC_QM_AXUSER_SECURED_BASE 0x184CB00ull
+#define DCORE1_TPC4_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE1_TPC4_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x184CB80ull
+#define DCORE1_TPC4_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE1_TPC4_EML_TPC_QM_DBG_HBW_BASE 0x184CC00ull
+#define DCORE1_TPC4_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC4_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_TPC4_EML_TPC_QM_DBG_LBW_BASE 0x184CC80ull
+#define DCORE1_TPC4_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC4_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE1_TPC4_EML_TPC_QM_CGM_BASE 0x184CD80ull
+#define DCORE1_TPC4_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE1_TPC4_EML_TPC_QM_CGM_SECTION 0x1000
+#define mmDCORE1_TPC4_EML_TPC_QM_SPECIAL_BASE 0x184CE80ull
+#define DCORE1_TPC4_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC4_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define mmDCORE1_TPC4_EML_CS_BASE 0x19FF000ull
+#define DCORE1_TPC4_EML_CS_MAX_OFFSET 0x1000
+#define DCORE1_TPC4_EML_CS_SECTION 0x1000
+#define mmDCORE1_TPC5_ROM_TABLE_BASE 0x1A00000ull
+#define DCORE1_TPC5_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE1_TPC5_ROM_TABLE_SECTION 0x1000
+#define mmDCORE1_TPC5_EML_SPMU_BASE 0x1A01000ull
+#define DCORE1_TPC5_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_TPC5_EML_SPMU_SECTION 0x1000
+#define mmDCORE1_TPC5_EML_ETF_BASE 0x1A02000ull
+#define DCORE1_TPC5_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE1_TPC5_EML_ETF_SECTION 0x1000
+#define mmDCORE1_TPC5_EML_STM_BASE 0x1A03000ull
+#define DCORE1_TPC5_EML_STM_MAX_OFFSET 0x1000
+#define DCORE1_TPC5_EML_STM_SECTION 0x2000
+#define mmDCORE1_TPC5_EML_CTI_BASE 0x1A05000ull
+#define DCORE1_TPC5_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE1_TPC5_EML_CTI_SECTION 0x1000
+#define mmDCORE1_TPC5_EML_FUNNEL_BASE 0x1A06000ull
+#define DCORE1_TPC5_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_TPC5_EML_FUNNEL_SECTION 0x1000
+#define mmDCORE1_TPC5_EML_BUSMON_0_BASE 0x1A07000ull
+#define DCORE1_TPC5_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE1_TPC5_EML_BUSMON_0_SECTION 0x1000
+#define mmDCORE1_TPC5_EML_BUSMON_1_BASE 0x1A08000ull
+#define DCORE1_TPC5_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE1_TPC5_EML_BUSMON_1_SECTION 0x1000
+#define mmDCORE1_TPC5_EML_BUSMON_2_BASE 0x1A09000ull
+#define DCORE1_TPC5_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE1_TPC5_EML_BUSMON_2_SECTION 0x1000
+#define mmDCORE1_TPC5_EML_BUSMON_3_BASE 0x1A0A000ull
+#define DCORE1_TPC5_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE1_TPC5_EML_BUSMON_3_SECTION 0x1000
+#define mmDCORE1_TPC5_QM_ARC_RTT_BASE 0x1A0B000ull
+#define DCORE1_TPC5_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE1_TPC5_QM_ARC_RTT_SECTION 0x35000
+#define mmDCORE1_TPC5_EML_CFG_BASE 0x1A40000ull
+#define DCORE1_TPC5_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE1_TPC5_EML_CFG_SECTION 0xE800
+#define mmDCORE1_TPC5_EML_CFG_SPECIAL_BASE 0x1A40E80ull
+#define DCORE1_TPC5_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC5_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1A41000ull
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE1_TPC5_EML_TPC_CFG_BASE 0x1A41000ull
+#define DCORE1_TPC5_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE1_TPC5_EML_TPC_CFG_SECTION 0x5000
+#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1A41050ull
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x1A410A0ull
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x1A410F0ull
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1A41140ull
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1A41190ull
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x1A411E0ull
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1A41230ull
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1A41280ull
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x1A412D0ull
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1A41320ull
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1A41370ull
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x1A413C0ull
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1A41410ull
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1A41460ull
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x1A414B0ull
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1A41500ull
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_BASE 0x1A41508ull
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_0_BASE 0x1A415DCull
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_1_BASE 0x1A4162Cull
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_2_BASE 0x1A4167Cull
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_3_BASE 0x1A416CCull
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_4_BASE 0x1A4171Cull
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_5_BASE 0x1A4176Cull
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_6_BASE 0x1A417BCull
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_7_BASE 0x1A4180Cull
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_8_BASE 0x1A4185Cull
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_9_BASE 0x1A418ACull
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_10_BASE 0x1A418FCull
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_11_BASE 0x1A4194Cull
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_12_BASE 0x1A4199Cull
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_13_BASE 0x1A419ECull
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1A41A3Cull
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1A41A8Cull
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE1_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1A41ADCull
+#define DCORE1_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE1_TPC5_EML_TPC_CFG_QM_BASE 0x1A41AE4ull
+#define DCORE1_TPC5_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE1_TPC5_EML_TPC_CFG_QM_SECTION 0x31C0
+#define mmDCORE1_TPC5_EML_TPC_CFG_AXUSER_BASE 0x1A41E00ull
+#define DCORE1_TPC5_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE1_TPC5_EML_TPC_CFG_SPECIAL_BASE 0x1A41E80ull
+#define DCORE1_TPC5_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC5_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE1_TPC5_EML_QM_DCCM_BASE 0x1A42000ull
+#define DCORE1_TPC5_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE1_TPC5_EML_QM_DCCM_SECTION 0x8000
+#define mmDCORE1_TPC5_EML_QM_ARCAUX_BASE 0x1A4A000ull
+#define DCORE1_TPC5_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE1_TPC5_EML_QM_ARCAUX_SECTION 0xE800
+#define mmDCORE1_TPC5_EML_QM_ARCAUX_SPECIAL_BASE 0x1A4AE80ull
+#define DCORE1_TPC5_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC5_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define mmDCORE1_TPC5_EML_TPC_QM_BASE 0x1A4C000ull
+#define DCORE1_TPC5_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE1_TPC5_EML_TPC_QM_SECTION 0x9000
+#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1A4C900ull
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1A4C908ull
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1A4C910ull
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1A4C918ull
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1A4C920ull
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1A4C928ull
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1A4C930ull
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1A4C938ull
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1A4C940ull
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1A4C948ull
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x1A4C950ull
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x1A4C958ull
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x1A4C960ull
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x1A4C968ull
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x1A4C970ull
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x1A4C978ull
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE1_TPC5_EML_TPC_QM_AXUSER_SECURED_BASE 0x1A4CB00ull
+#define DCORE1_TPC5_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE1_TPC5_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x1A4CB80ull
+#define DCORE1_TPC5_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE1_TPC5_EML_TPC_QM_DBG_HBW_BASE 0x1A4CC00ull
+#define DCORE1_TPC5_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC5_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_TPC5_EML_TPC_QM_DBG_LBW_BASE 0x1A4CC80ull
+#define DCORE1_TPC5_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC5_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE1_TPC5_EML_TPC_QM_CGM_BASE 0x1A4CD80ull
+#define DCORE1_TPC5_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE1_TPC5_EML_TPC_QM_CGM_SECTION 0x1000
+#define mmDCORE1_TPC5_EML_TPC_QM_SPECIAL_BASE 0x1A4CE80ull
+#define DCORE1_TPC5_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC5_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define mmDCORE1_TPC5_EML_CS_BASE 0x1BFF000ull
+#define DCORE1_TPC5_EML_CS_MAX_OFFSET 0x1000
+#define DCORE1_TPC5_EML_CS_SECTION 0x401000
+#define mmDCORE2_TPC0_ROM_TABLE_BASE 0x2000000ull
+#define DCORE2_TPC0_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE2_TPC0_ROM_TABLE_SECTION 0x1000
+#define mmDCORE2_TPC0_EML_SPMU_BASE 0x2001000ull
+#define DCORE2_TPC0_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_TPC0_EML_SPMU_SECTION 0x1000
+#define mmDCORE2_TPC0_EML_ETF_BASE 0x2002000ull
+#define DCORE2_TPC0_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE2_TPC0_EML_ETF_SECTION 0x1000
+#define mmDCORE2_TPC0_EML_STM_BASE 0x2003000ull
+#define DCORE2_TPC0_EML_STM_MAX_OFFSET 0x1000
+#define DCORE2_TPC0_EML_STM_SECTION 0x2000
+#define mmDCORE2_TPC0_EML_CTI_BASE 0x2005000ull
+#define DCORE2_TPC0_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE2_TPC0_EML_CTI_SECTION 0x1000
+#define mmDCORE2_TPC0_EML_FUNNEL_BASE 0x2006000ull
+#define DCORE2_TPC0_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_TPC0_EML_FUNNEL_SECTION 0x1000
+#define mmDCORE2_TPC0_EML_BUSMON_0_BASE 0x2007000ull
+#define DCORE2_TPC0_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE2_TPC0_EML_BUSMON_0_SECTION 0x1000
+#define mmDCORE2_TPC0_EML_BUSMON_1_BASE 0x2008000ull
+#define DCORE2_TPC0_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE2_TPC0_EML_BUSMON_1_SECTION 0x1000
+#define mmDCORE2_TPC0_EML_BUSMON_2_BASE 0x2009000ull
+#define DCORE2_TPC0_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE2_TPC0_EML_BUSMON_2_SECTION 0x1000
+#define mmDCORE2_TPC0_EML_BUSMON_3_BASE 0x200A000ull
+#define DCORE2_TPC0_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE2_TPC0_EML_BUSMON_3_SECTION 0x1000
+#define mmDCORE2_TPC0_QM_ARC_RTT_BASE 0x200B000ull
+#define DCORE2_TPC0_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE2_TPC0_QM_ARC_RTT_SECTION 0x35000
+#define mmDCORE2_TPC0_EML_CFG_BASE 0x2040000ull
+#define DCORE2_TPC0_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE2_TPC0_EML_CFG_SECTION 0xE800
+#define mmDCORE2_TPC0_EML_CFG_SPECIAL_BASE 0x2040E80ull
+#define DCORE2_TPC0_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC0_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x2041000ull
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE2_TPC0_EML_TPC_CFG_BASE 0x2041000ull
+#define DCORE2_TPC0_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE2_TPC0_EML_TPC_CFG_SECTION 0x5000
+#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x2041050ull
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x20410A0ull
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x20410F0ull
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x2041140ull
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x2041190ull
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x20411E0ull
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x2041230ull
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x2041280ull
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x20412D0ull
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x2041320ull
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x2041370ull
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x20413C0ull
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x2041410ull
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x2041460ull
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x20414B0ull
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x2041500ull
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_BASE 0x2041508ull
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_0_BASE 0x20415DCull
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_1_BASE 0x204162Cull
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_2_BASE 0x204167Cull
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_3_BASE 0x20416CCull
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_4_BASE 0x204171Cull
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_5_BASE 0x204176Cull
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_6_BASE 0x20417BCull
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_7_BASE 0x204180Cull
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_8_BASE 0x204185Cull
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_9_BASE 0x20418ACull
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_10_BASE 0x20418FCull
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_11_BASE 0x204194Cull
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_12_BASE 0x204199Cull
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_13_BASE 0x20419ECull
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_14_BASE 0x2041A3Cull
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_15_BASE 0x2041A8Cull
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE2_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x2041ADCull
+#define DCORE2_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE2_TPC0_EML_TPC_CFG_QM_BASE 0x2041AE4ull
+#define DCORE2_TPC0_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE2_TPC0_EML_TPC_CFG_QM_SECTION 0x31C0
+#define mmDCORE2_TPC0_EML_TPC_CFG_AXUSER_BASE 0x2041E00ull
+#define DCORE2_TPC0_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE2_TPC0_EML_TPC_CFG_SPECIAL_BASE 0x2041E80ull
+#define DCORE2_TPC0_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC0_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE2_TPC0_EML_QM_DCCM_BASE 0x2042000ull
+#define DCORE2_TPC0_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE2_TPC0_EML_QM_DCCM_SECTION 0x8000
+#define mmDCORE2_TPC0_EML_QM_ARCAUX_BASE 0x204A000ull
+#define DCORE2_TPC0_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE2_TPC0_EML_QM_ARCAUX_SECTION 0xE800
+#define mmDCORE2_TPC0_EML_QM_ARCAUX_SPECIAL_BASE 0x204AE80ull
+#define DCORE2_TPC0_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC0_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define mmDCORE2_TPC0_EML_TPC_QM_BASE 0x204C000ull
+#define DCORE2_TPC0_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE2_TPC0_EML_TPC_QM_SECTION 0x9000
+#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x204C900ull
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x204C908ull
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x204C910ull
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x204C918ull
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x204C920ull
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x204C928ull
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x204C930ull
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x204C938ull
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x204C940ull
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x204C948ull
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x204C950ull
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x204C958ull
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x204C960ull
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x204C968ull
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x204C970ull
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x204C978ull
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE2_TPC0_EML_TPC_QM_AXUSER_SECURED_BASE 0x204CB00ull
+#define DCORE2_TPC0_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE2_TPC0_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x204CB80ull
+#define DCORE2_TPC0_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE2_TPC0_EML_TPC_QM_DBG_HBW_BASE 0x204CC00ull
+#define DCORE2_TPC0_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC0_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_TPC0_EML_TPC_QM_DBG_LBW_BASE 0x204CC80ull
+#define DCORE2_TPC0_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC0_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE2_TPC0_EML_TPC_QM_CGM_BASE 0x204CD80ull
+#define DCORE2_TPC0_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE2_TPC0_EML_TPC_QM_CGM_SECTION 0x1000
+#define mmDCORE2_TPC0_EML_TPC_QM_SPECIAL_BASE 0x204CE80ull
+#define DCORE2_TPC0_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC0_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define mmDCORE2_TPC0_EML_CS_BASE 0x21FF000ull
+#define DCORE2_TPC0_EML_CS_MAX_OFFSET 0x1000
+#define DCORE2_TPC0_EML_CS_SECTION 0x1000
+#define mmDCORE2_TPC1_ROM_TABLE_BASE 0x2200000ull
+#define DCORE2_TPC1_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE2_TPC1_ROM_TABLE_SECTION 0x1000
+#define mmDCORE2_TPC1_EML_SPMU_BASE 0x2201000ull
+#define DCORE2_TPC1_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_TPC1_EML_SPMU_SECTION 0x1000
+#define mmDCORE2_TPC1_EML_ETF_BASE 0x2202000ull
+#define DCORE2_TPC1_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE2_TPC1_EML_ETF_SECTION 0x1000
+#define mmDCORE2_TPC1_EML_STM_BASE 0x2203000ull
+#define DCORE2_TPC1_EML_STM_MAX_OFFSET 0x1000
+#define DCORE2_TPC1_EML_STM_SECTION 0x2000
+#define mmDCORE2_TPC1_EML_CTI_BASE 0x2205000ull
+#define DCORE2_TPC1_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE2_TPC1_EML_CTI_SECTION 0x1000
+#define mmDCORE2_TPC1_EML_FUNNEL_BASE 0x2206000ull
+#define DCORE2_TPC1_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_TPC1_EML_FUNNEL_SECTION 0x1000
+#define mmDCORE2_TPC1_EML_BUSMON_0_BASE 0x2207000ull
+#define DCORE2_TPC1_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE2_TPC1_EML_BUSMON_0_SECTION 0x1000
+#define mmDCORE2_TPC1_EML_BUSMON_1_BASE 0x2208000ull
+#define DCORE2_TPC1_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE2_TPC1_EML_BUSMON_1_SECTION 0x1000
+#define mmDCORE2_TPC1_EML_BUSMON_2_BASE 0x2209000ull
+#define DCORE2_TPC1_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE2_TPC1_EML_BUSMON_2_SECTION 0x1000
+#define mmDCORE2_TPC1_EML_BUSMON_3_BASE 0x220A000ull
+#define DCORE2_TPC1_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE2_TPC1_EML_BUSMON_3_SECTION 0x1000
+#define mmDCORE2_TPC1_QM_ARC_RTT_BASE 0x220B000ull
+#define DCORE2_TPC1_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE2_TPC1_QM_ARC_RTT_SECTION 0x35000
+#define mmDCORE2_TPC1_EML_CFG_BASE 0x2240000ull
+#define DCORE2_TPC1_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE2_TPC1_EML_CFG_SECTION 0xE800
+#define mmDCORE2_TPC1_EML_CFG_SPECIAL_BASE 0x2240E80ull
+#define DCORE2_TPC1_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC1_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x2241000ull
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE2_TPC1_EML_TPC_CFG_BASE 0x2241000ull
+#define DCORE2_TPC1_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE2_TPC1_EML_TPC_CFG_SECTION 0x5000
+#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x2241050ull
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x22410A0ull
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x22410F0ull
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x2241140ull
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x2241190ull
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x22411E0ull
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x2241230ull
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x2241280ull
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x22412D0ull
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x2241320ull
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x2241370ull
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x22413C0ull
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x2241410ull
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x2241460ull
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x22414B0ull
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x2241500ull
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_BASE 0x2241508ull
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_0_BASE 0x22415DCull
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_1_BASE 0x224162Cull
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_2_BASE 0x224167Cull
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_3_BASE 0x22416CCull
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_4_BASE 0x224171Cull
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_5_BASE 0x224176Cull
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_6_BASE 0x22417BCull
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_7_BASE 0x224180Cull
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_8_BASE 0x224185Cull
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_9_BASE 0x22418ACull
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_10_BASE 0x22418FCull
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_11_BASE 0x224194Cull
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_12_BASE 0x224199Cull
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_13_BASE 0x22419ECull
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_14_BASE 0x2241A3Cull
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_15_BASE 0x2241A8Cull
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE2_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x2241ADCull
+#define DCORE2_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE2_TPC1_EML_TPC_CFG_QM_BASE 0x2241AE4ull
+#define DCORE2_TPC1_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE2_TPC1_EML_TPC_CFG_QM_SECTION 0x31C0
+#define mmDCORE2_TPC1_EML_TPC_CFG_AXUSER_BASE 0x2241E00ull
+#define DCORE2_TPC1_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE2_TPC1_EML_TPC_CFG_SPECIAL_BASE 0x2241E80ull
+#define DCORE2_TPC1_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC1_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE2_TPC1_EML_QM_DCCM_BASE 0x2242000ull
+#define DCORE2_TPC1_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE2_TPC1_EML_QM_DCCM_SECTION 0x8000
+#define mmDCORE2_TPC1_EML_QM_ARCAUX_BASE 0x224A000ull
+#define DCORE2_TPC1_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE2_TPC1_EML_QM_ARCAUX_SECTION 0xE800
+#define mmDCORE2_TPC1_EML_QM_ARCAUX_SPECIAL_BASE 0x224AE80ull
+#define DCORE2_TPC1_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC1_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define mmDCORE2_TPC1_EML_TPC_QM_BASE 0x224C000ull
+#define DCORE2_TPC1_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE2_TPC1_EML_TPC_QM_SECTION 0x9000
+#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x224C900ull
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x224C908ull
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x224C910ull
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x224C918ull
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x224C920ull
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x224C928ull
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x224C930ull
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x224C938ull
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x224C940ull
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x224C948ull
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x224C950ull
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x224C958ull
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x224C960ull
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x224C968ull
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x224C970ull
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x224C978ull
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE2_TPC1_EML_TPC_QM_AXUSER_SECURED_BASE 0x224CB00ull
+#define DCORE2_TPC1_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE2_TPC1_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x224CB80ull
+#define DCORE2_TPC1_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE2_TPC1_EML_TPC_QM_DBG_HBW_BASE 0x224CC00ull
+#define DCORE2_TPC1_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC1_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_TPC1_EML_TPC_QM_DBG_LBW_BASE 0x224CC80ull
+#define DCORE2_TPC1_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC1_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE2_TPC1_EML_TPC_QM_CGM_BASE 0x224CD80ull
+#define DCORE2_TPC1_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE2_TPC1_EML_TPC_QM_CGM_SECTION 0x1000
+#define mmDCORE2_TPC1_EML_TPC_QM_SPECIAL_BASE 0x224CE80ull
+#define DCORE2_TPC1_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC1_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define mmDCORE2_TPC1_EML_CS_BASE 0x23FF000ull
+#define DCORE2_TPC1_EML_CS_MAX_OFFSET 0x1000
+#define DCORE2_TPC1_EML_CS_SECTION 0x1000
+#define mmDCORE2_TPC2_ROM_TABLE_BASE 0x2400000ull
+#define DCORE2_TPC2_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE2_TPC2_ROM_TABLE_SECTION 0x1000
+#define mmDCORE2_TPC2_EML_SPMU_BASE 0x2401000ull
+#define DCORE2_TPC2_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_TPC2_EML_SPMU_SECTION 0x1000
+#define mmDCORE2_TPC2_EML_ETF_BASE 0x2402000ull
+#define DCORE2_TPC2_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE2_TPC2_EML_ETF_SECTION 0x1000
+#define mmDCORE2_TPC2_EML_STM_BASE 0x2403000ull
+#define DCORE2_TPC2_EML_STM_MAX_OFFSET 0x1000
+#define DCORE2_TPC2_EML_STM_SECTION 0x2000
+#define mmDCORE2_TPC2_EML_CTI_BASE 0x2405000ull
+#define DCORE2_TPC2_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE2_TPC2_EML_CTI_SECTION 0x1000
+#define mmDCORE2_TPC2_EML_FUNNEL_BASE 0x2406000ull
+#define DCORE2_TPC2_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_TPC2_EML_FUNNEL_SECTION 0x1000
+#define mmDCORE2_TPC2_EML_BUSMON_0_BASE 0x2407000ull
+#define DCORE2_TPC2_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE2_TPC2_EML_BUSMON_0_SECTION 0x1000
+#define mmDCORE2_TPC2_EML_BUSMON_1_BASE 0x2408000ull
+#define DCORE2_TPC2_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE2_TPC2_EML_BUSMON_1_SECTION 0x1000
+#define mmDCORE2_TPC2_EML_BUSMON_2_BASE 0x2409000ull
+#define DCORE2_TPC2_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE2_TPC2_EML_BUSMON_2_SECTION 0x1000
+#define mmDCORE2_TPC2_EML_BUSMON_3_BASE 0x240A000ull
+#define DCORE2_TPC2_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE2_TPC2_EML_BUSMON_3_SECTION 0x1000
+#define mmDCORE2_TPC2_QM_ARC_RTT_BASE 0x240B000ull
+#define DCORE2_TPC2_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE2_TPC2_QM_ARC_RTT_SECTION 0x35000
+#define mmDCORE2_TPC2_EML_CFG_BASE 0x2440000ull
+#define DCORE2_TPC2_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE2_TPC2_EML_CFG_SECTION 0xE800
+#define mmDCORE2_TPC2_EML_CFG_SPECIAL_BASE 0x2440E80ull
+#define DCORE2_TPC2_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC2_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x2441000ull
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE2_TPC2_EML_TPC_CFG_BASE 0x2441000ull
+#define DCORE2_TPC2_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE2_TPC2_EML_TPC_CFG_SECTION 0x5000
+#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x2441050ull
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x24410A0ull
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x24410F0ull
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x2441140ull
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x2441190ull
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x24411E0ull
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x2441230ull
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x2441280ull
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x24412D0ull
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x2441320ull
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x2441370ull
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x24413C0ull
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x2441410ull
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x2441460ull
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x24414B0ull
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x2441500ull
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_BASE 0x2441508ull
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_0_BASE 0x24415DCull
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_1_BASE 0x244162Cull
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_2_BASE 0x244167Cull
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_3_BASE 0x24416CCull
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_4_BASE 0x244171Cull
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_5_BASE 0x244176Cull
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_6_BASE 0x24417BCull
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_7_BASE 0x244180Cull
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_8_BASE 0x244185Cull
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_9_BASE 0x24418ACull
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_10_BASE 0x24418FCull
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_11_BASE 0x244194Cull
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_12_BASE 0x244199Cull
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_13_BASE 0x24419ECull
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_14_BASE 0x2441A3Cull
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_15_BASE 0x2441A8Cull
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE2_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x2441ADCull
+#define DCORE2_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE2_TPC2_EML_TPC_CFG_QM_BASE 0x2441AE4ull
+#define DCORE2_TPC2_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE2_TPC2_EML_TPC_CFG_QM_SECTION 0x31C0
+#define mmDCORE2_TPC2_EML_TPC_CFG_AXUSER_BASE 0x2441E00ull
+#define DCORE2_TPC2_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE2_TPC2_EML_TPC_CFG_SPECIAL_BASE 0x2441E80ull
+#define DCORE2_TPC2_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC2_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE2_TPC2_EML_QM_DCCM_BASE 0x2442000ull
+#define DCORE2_TPC2_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE2_TPC2_EML_QM_DCCM_SECTION 0x8000
+#define mmDCORE2_TPC2_EML_QM_ARCAUX_BASE 0x244A000ull
+#define DCORE2_TPC2_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE2_TPC2_EML_QM_ARCAUX_SECTION 0xE800
+#define mmDCORE2_TPC2_EML_QM_ARCAUX_SPECIAL_BASE 0x244AE80ull
+#define DCORE2_TPC2_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC2_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define mmDCORE2_TPC2_EML_TPC_QM_BASE 0x244C000ull
+#define DCORE2_TPC2_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE2_TPC2_EML_TPC_QM_SECTION 0x9000
+#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x244C900ull
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x244C908ull
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x244C910ull
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x244C918ull
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x244C920ull
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x244C928ull
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x244C930ull
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x244C938ull
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x244C940ull
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x244C948ull
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x244C950ull
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x244C958ull
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x244C960ull
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x244C968ull
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x244C970ull
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x244C978ull
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE2_TPC2_EML_TPC_QM_AXUSER_SECURED_BASE 0x244CB00ull
+#define DCORE2_TPC2_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE2_TPC2_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x244CB80ull
+#define DCORE2_TPC2_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE2_TPC2_EML_TPC_QM_DBG_HBW_BASE 0x244CC00ull
+#define DCORE2_TPC2_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC2_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_TPC2_EML_TPC_QM_DBG_LBW_BASE 0x244CC80ull
+#define DCORE2_TPC2_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC2_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE2_TPC2_EML_TPC_QM_CGM_BASE 0x244CD80ull
+#define DCORE2_TPC2_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE2_TPC2_EML_TPC_QM_CGM_SECTION 0x1000
+#define mmDCORE2_TPC2_EML_TPC_QM_SPECIAL_BASE 0x244CE80ull
+#define DCORE2_TPC2_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC2_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define mmDCORE2_TPC2_EML_CS_BASE 0x25FF000ull
+#define DCORE2_TPC2_EML_CS_MAX_OFFSET 0x1000
+#define DCORE2_TPC2_EML_CS_SECTION 0x1000
+#define mmDCORE2_TPC3_ROM_TABLE_BASE 0x2600000ull
+#define DCORE2_TPC3_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE2_TPC3_ROM_TABLE_SECTION 0x1000
+#define mmDCORE2_TPC3_EML_SPMU_BASE 0x2601000ull
+#define DCORE2_TPC3_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_TPC3_EML_SPMU_SECTION 0x1000
+#define mmDCORE2_TPC3_EML_ETF_BASE 0x2602000ull
+#define DCORE2_TPC3_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE2_TPC3_EML_ETF_SECTION 0x1000
+#define mmDCORE2_TPC3_EML_STM_BASE 0x2603000ull
+#define DCORE2_TPC3_EML_STM_MAX_OFFSET 0x1000
+#define DCORE2_TPC3_EML_STM_SECTION 0x2000
+#define mmDCORE2_TPC3_EML_CTI_BASE 0x2605000ull
+#define DCORE2_TPC3_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE2_TPC3_EML_CTI_SECTION 0x1000
+#define mmDCORE2_TPC3_EML_FUNNEL_BASE 0x2606000ull
+#define DCORE2_TPC3_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_TPC3_EML_FUNNEL_SECTION 0x1000
+#define mmDCORE2_TPC3_EML_BUSMON_0_BASE 0x2607000ull
+#define DCORE2_TPC3_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE2_TPC3_EML_BUSMON_0_SECTION 0x1000
+#define mmDCORE2_TPC3_EML_BUSMON_1_BASE 0x2608000ull
+#define DCORE2_TPC3_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE2_TPC3_EML_BUSMON_1_SECTION 0x1000
+#define mmDCORE2_TPC3_EML_BUSMON_2_BASE 0x2609000ull
+#define DCORE2_TPC3_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE2_TPC3_EML_BUSMON_2_SECTION 0x1000
+#define mmDCORE2_TPC3_EML_BUSMON_3_BASE 0x260A000ull
+#define DCORE2_TPC3_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE2_TPC3_EML_BUSMON_3_SECTION 0x1000
+#define mmDCORE2_TPC3_QM_ARC_RTT_BASE 0x260B000ull
+#define DCORE2_TPC3_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE2_TPC3_QM_ARC_RTT_SECTION 0x35000
+#define mmDCORE2_TPC3_EML_CFG_BASE 0x2640000ull
+#define DCORE2_TPC3_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE2_TPC3_EML_CFG_SECTION 0xE800
+#define mmDCORE2_TPC3_EML_CFG_SPECIAL_BASE 0x2640E80ull
+#define DCORE2_TPC3_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC3_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x2641000ull
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE2_TPC3_EML_TPC_CFG_BASE 0x2641000ull
+#define DCORE2_TPC3_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE2_TPC3_EML_TPC_CFG_SECTION 0x5000
+#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x2641050ull
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x26410A0ull
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x26410F0ull
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x2641140ull
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x2641190ull
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x26411E0ull
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x2641230ull
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x2641280ull
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x26412D0ull
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x2641320ull
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x2641370ull
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x26413C0ull
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x2641410ull
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x2641460ull
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x26414B0ull
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x2641500ull
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_BASE 0x2641508ull
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_0_BASE 0x26415DCull
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_1_BASE 0x264162Cull
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_2_BASE 0x264167Cull
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_3_BASE 0x26416CCull
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_4_BASE 0x264171Cull
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_5_BASE 0x264176Cull
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_6_BASE 0x26417BCull
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_7_BASE 0x264180Cull
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_8_BASE 0x264185Cull
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_9_BASE 0x26418ACull
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_10_BASE 0x26418FCull
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_11_BASE 0x264194Cull
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_12_BASE 0x264199Cull
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_13_BASE 0x26419ECull
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_14_BASE 0x2641A3Cull
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_15_BASE 0x2641A8Cull
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE2_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x2641ADCull
+#define DCORE2_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE2_TPC3_EML_TPC_CFG_QM_BASE 0x2641AE4ull
+#define DCORE2_TPC3_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE2_TPC3_EML_TPC_CFG_QM_SECTION 0x31C0
+#define mmDCORE2_TPC3_EML_TPC_CFG_AXUSER_BASE 0x2641E00ull
+#define DCORE2_TPC3_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE2_TPC3_EML_TPC_CFG_SPECIAL_BASE 0x2641E80ull
+#define DCORE2_TPC3_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC3_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE2_TPC3_EML_QM_DCCM_BASE 0x2642000ull
+#define DCORE2_TPC3_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE2_TPC3_EML_QM_DCCM_SECTION 0x8000
+#define mmDCORE2_TPC3_EML_QM_ARCAUX_BASE 0x264A000ull
+#define DCORE2_TPC3_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE2_TPC3_EML_QM_ARCAUX_SECTION 0xE800
+#define mmDCORE2_TPC3_EML_QM_ARCAUX_SPECIAL_BASE 0x264AE80ull
+#define DCORE2_TPC3_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC3_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define mmDCORE2_TPC3_EML_TPC_QM_BASE 0x264C000ull
+#define DCORE2_TPC3_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE2_TPC3_EML_TPC_QM_SECTION 0x9000
+#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x264C900ull
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x264C908ull
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x264C910ull
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x264C918ull
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x264C920ull
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x264C928ull
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x264C930ull
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x264C938ull
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x264C940ull
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x264C948ull
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x264C950ull
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x264C958ull
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x264C960ull
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x264C968ull
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x264C970ull
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x264C978ull
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE2_TPC3_EML_TPC_QM_AXUSER_SECURED_BASE 0x264CB00ull
+#define DCORE2_TPC3_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE2_TPC3_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x264CB80ull
+#define DCORE2_TPC3_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE2_TPC3_EML_TPC_QM_DBG_HBW_BASE 0x264CC00ull
+#define DCORE2_TPC3_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC3_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_TPC3_EML_TPC_QM_DBG_LBW_BASE 0x264CC80ull
+#define DCORE2_TPC3_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC3_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE2_TPC3_EML_TPC_QM_CGM_BASE 0x264CD80ull
+#define DCORE2_TPC3_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE2_TPC3_EML_TPC_QM_CGM_SECTION 0x1000
+#define mmDCORE2_TPC3_EML_TPC_QM_SPECIAL_BASE 0x264CE80ull
+#define DCORE2_TPC3_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC3_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define mmDCORE2_TPC3_EML_CS_BASE 0x27FF000ull
+#define DCORE2_TPC3_EML_CS_MAX_OFFSET 0x1000
+#define DCORE2_TPC3_EML_CS_SECTION 0x1000
+#define mmDCORE2_TPC4_ROM_TABLE_BASE 0x2800000ull
+#define DCORE2_TPC4_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE2_TPC4_ROM_TABLE_SECTION 0x1000
+#define mmDCORE2_TPC4_EML_SPMU_BASE 0x2801000ull
+#define DCORE2_TPC4_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_TPC4_EML_SPMU_SECTION 0x1000
+#define mmDCORE2_TPC4_EML_ETF_BASE 0x2802000ull
+#define DCORE2_TPC4_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE2_TPC4_EML_ETF_SECTION 0x1000
+#define mmDCORE2_TPC4_EML_STM_BASE 0x2803000ull
+#define DCORE2_TPC4_EML_STM_MAX_OFFSET 0x1000
+#define DCORE2_TPC4_EML_STM_SECTION 0x2000
+#define mmDCORE2_TPC4_EML_CTI_BASE 0x2805000ull
+#define DCORE2_TPC4_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE2_TPC4_EML_CTI_SECTION 0x1000
+#define mmDCORE2_TPC4_EML_FUNNEL_BASE 0x2806000ull
+#define DCORE2_TPC4_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_TPC4_EML_FUNNEL_SECTION 0x1000
+#define mmDCORE2_TPC4_EML_BUSMON_0_BASE 0x2807000ull
+#define DCORE2_TPC4_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE2_TPC4_EML_BUSMON_0_SECTION 0x1000
+#define mmDCORE2_TPC4_EML_BUSMON_1_BASE 0x2808000ull
+#define DCORE2_TPC4_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE2_TPC4_EML_BUSMON_1_SECTION 0x1000
+#define mmDCORE2_TPC4_EML_BUSMON_2_BASE 0x2809000ull
+#define DCORE2_TPC4_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE2_TPC4_EML_BUSMON_2_SECTION 0x1000
+#define mmDCORE2_TPC4_EML_BUSMON_3_BASE 0x280A000ull
+#define DCORE2_TPC4_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE2_TPC4_EML_BUSMON_3_SECTION 0x1000
+#define mmDCORE2_TPC4_QM_ARC_RTT_BASE 0x280B000ull
+#define DCORE2_TPC4_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE2_TPC4_QM_ARC_RTT_SECTION 0x35000
+#define mmDCORE2_TPC4_EML_CFG_BASE 0x2840000ull
+#define DCORE2_TPC4_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE2_TPC4_EML_CFG_SECTION 0xE800
+#define mmDCORE2_TPC4_EML_CFG_SPECIAL_BASE 0x2840E80ull
+#define DCORE2_TPC4_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC4_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x2841000ull
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE2_TPC4_EML_TPC_CFG_BASE 0x2841000ull
+#define DCORE2_TPC4_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE2_TPC4_EML_TPC_CFG_SECTION 0x5000
+#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x2841050ull
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x28410A0ull
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x28410F0ull
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x2841140ull
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x2841190ull
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x28411E0ull
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x2841230ull
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x2841280ull
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x28412D0ull
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x2841320ull
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x2841370ull
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x28413C0ull
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x2841410ull
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x2841460ull
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x28414B0ull
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x2841500ull
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_BASE 0x2841508ull
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_0_BASE 0x28415DCull
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_1_BASE 0x284162Cull
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_2_BASE 0x284167Cull
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_3_BASE 0x28416CCull
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_4_BASE 0x284171Cull
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_5_BASE 0x284176Cull
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_6_BASE 0x28417BCull
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_7_BASE 0x284180Cull
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_8_BASE 0x284185Cull
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_9_BASE 0x28418ACull
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_10_BASE 0x28418FCull
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_11_BASE 0x284194Cull
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_12_BASE 0x284199Cull
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_13_BASE 0x28419ECull
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_14_BASE 0x2841A3Cull
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_15_BASE 0x2841A8Cull
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE2_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x2841ADCull
+#define DCORE2_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE2_TPC4_EML_TPC_CFG_QM_BASE 0x2841AE4ull
+#define DCORE2_TPC4_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE2_TPC4_EML_TPC_CFG_QM_SECTION 0x31C0
+#define mmDCORE2_TPC4_EML_TPC_CFG_AXUSER_BASE 0x2841E00ull
+#define DCORE2_TPC4_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE2_TPC4_EML_TPC_CFG_SPECIAL_BASE 0x2841E80ull
+#define DCORE2_TPC4_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC4_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE2_TPC4_EML_QM_DCCM_BASE 0x2842000ull
+#define DCORE2_TPC4_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE2_TPC4_EML_QM_DCCM_SECTION 0x8000
+#define mmDCORE2_TPC4_EML_QM_ARCAUX_BASE 0x284A000ull
+#define DCORE2_TPC4_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE2_TPC4_EML_QM_ARCAUX_SECTION 0xE800
+#define mmDCORE2_TPC4_EML_QM_ARCAUX_SPECIAL_BASE 0x284AE80ull
+#define DCORE2_TPC4_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC4_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define mmDCORE2_TPC4_EML_TPC_QM_BASE 0x284C000ull
+#define DCORE2_TPC4_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE2_TPC4_EML_TPC_QM_SECTION 0x9000
+#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x284C900ull
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x284C908ull
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x284C910ull
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x284C918ull
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x284C920ull
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x284C928ull
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x284C930ull
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x284C938ull
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x284C940ull
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x284C948ull
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x284C950ull
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x284C958ull
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x284C960ull
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x284C968ull
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x284C970ull
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x284C978ull
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE2_TPC4_EML_TPC_QM_AXUSER_SECURED_BASE 0x284CB00ull
+#define DCORE2_TPC4_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE2_TPC4_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x284CB80ull
+#define DCORE2_TPC4_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE2_TPC4_EML_TPC_QM_DBG_HBW_BASE 0x284CC00ull
+#define DCORE2_TPC4_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC4_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_TPC4_EML_TPC_QM_DBG_LBW_BASE 0x284CC80ull
+#define DCORE2_TPC4_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC4_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE2_TPC4_EML_TPC_QM_CGM_BASE 0x284CD80ull
+#define DCORE2_TPC4_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE2_TPC4_EML_TPC_QM_CGM_SECTION 0x1000
+#define mmDCORE2_TPC4_EML_TPC_QM_SPECIAL_BASE 0x284CE80ull
+#define DCORE2_TPC4_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC4_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define mmDCORE2_TPC4_EML_CS_BASE 0x29FF000ull
+#define DCORE2_TPC4_EML_CS_MAX_OFFSET 0x1000
+#define DCORE2_TPC4_EML_CS_SECTION 0x1000
+#define mmDCORE2_TPC5_ROM_TABLE_BASE 0x2A00000ull
+#define DCORE2_TPC5_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE2_TPC5_ROM_TABLE_SECTION 0x1000
+#define mmDCORE2_TPC5_EML_SPMU_BASE 0x2A01000ull
+#define DCORE2_TPC5_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_TPC5_EML_SPMU_SECTION 0x1000
+#define mmDCORE2_TPC5_EML_ETF_BASE 0x2A02000ull
+#define DCORE2_TPC5_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE2_TPC5_EML_ETF_SECTION 0x1000
+#define mmDCORE2_TPC5_EML_STM_BASE 0x2A03000ull
+#define DCORE2_TPC5_EML_STM_MAX_OFFSET 0x1000
+#define DCORE2_TPC5_EML_STM_SECTION 0x2000
+#define mmDCORE2_TPC5_EML_CTI_BASE 0x2A05000ull
+#define DCORE2_TPC5_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE2_TPC5_EML_CTI_SECTION 0x1000
+#define mmDCORE2_TPC5_EML_FUNNEL_BASE 0x2A06000ull
+#define DCORE2_TPC5_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_TPC5_EML_FUNNEL_SECTION 0x1000
+#define mmDCORE2_TPC5_EML_BUSMON_0_BASE 0x2A07000ull
+#define DCORE2_TPC5_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE2_TPC5_EML_BUSMON_0_SECTION 0x1000
+#define mmDCORE2_TPC5_EML_BUSMON_1_BASE 0x2A08000ull
+#define DCORE2_TPC5_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE2_TPC5_EML_BUSMON_1_SECTION 0x1000
+#define mmDCORE2_TPC5_EML_BUSMON_2_BASE 0x2A09000ull
+#define DCORE2_TPC5_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE2_TPC5_EML_BUSMON_2_SECTION 0x1000
+#define mmDCORE2_TPC5_EML_BUSMON_3_BASE 0x2A0A000ull
+#define DCORE2_TPC5_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE2_TPC5_EML_BUSMON_3_SECTION 0x1000
+#define mmDCORE2_TPC5_QM_ARC_RTT_BASE 0x2A0B000ull
+#define DCORE2_TPC5_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE2_TPC5_QM_ARC_RTT_SECTION 0x35000
+#define mmDCORE2_TPC5_EML_CFG_BASE 0x2A40000ull
+#define DCORE2_TPC5_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE2_TPC5_EML_CFG_SECTION 0xE800
+#define mmDCORE2_TPC5_EML_CFG_SPECIAL_BASE 0x2A40E80ull
+#define DCORE2_TPC5_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC5_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x2A41000ull
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE2_TPC5_EML_TPC_CFG_BASE 0x2A41000ull
+#define DCORE2_TPC5_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE2_TPC5_EML_TPC_CFG_SECTION 0x5000
+#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x2A41050ull
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x2A410A0ull
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x2A410F0ull
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x2A41140ull
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x2A41190ull
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x2A411E0ull
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x2A41230ull
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x2A41280ull
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x2A412D0ull
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x2A41320ull
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x2A41370ull
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x2A413C0ull
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x2A41410ull
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x2A41460ull
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x2A414B0ull
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x2A41500ull
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_BASE 0x2A41508ull
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_0_BASE 0x2A415DCull
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_1_BASE 0x2A4162Cull
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_2_BASE 0x2A4167Cull
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_3_BASE 0x2A416CCull
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_4_BASE 0x2A4171Cull
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_5_BASE 0x2A4176Cull
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_6_BASE 0x2A417BCull
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_7_BASE 0x2A4180Cull
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_8_BASE 0x2A4185Cull
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_9_BASE 0x2A418ACull
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_10_BASE 0x2A418FCull
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_11_BASE 0x2A4194Cull
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_12_BASE 0x2A4199Cull
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_13_BASE 0x2A419ECull
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_14_BASE 0x2A41A3Cull
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_15_BASE 0x2A41A8Cull
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE2_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x2A41ADCull
+#define DCORE2_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE2_TPC5_EML_TPC_CFG_QM_BASE 0x2A41AE4ull
+#define DCORE2_TPC5_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE2_TPC5_EML_TPC_CFG_QM_SECTION 0x31C0
+#define mmDCORE2_TPC5_EML_TPC_CFG_AXUSER_BASE 0x2A41E00ull
+#define DCORE2_TPC5_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE2_TPC5_EML_TPC_CFG_SPECIAL_BASE 0x2A41E80ull
+#define DCORE2_TPC5_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC5_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE2_TPC5_EML_QM_DCCM_BASE 0x2A42000ull
+#define DCORE2_TPC5_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE2_TPC5_EML_QM_DCCM_SECTION 0x8000
+#define mmDCORE2_TPC5_EML_QM_ARCAUX_BASE 0x2A4A000ull
+#define DCORE2_TPC5_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE2_TPC5_EML_QM_ARCAUX_SECTION 0xE800
+#define mmDCORE2_TPC5_EML_QM_ARCAUX_SPECIAL_BASE 0x2A4AE80ull
+#define DCORE2_TPC5_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC5_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define mmDCORE2_TPC5_EML_TPC_QM_BASE 0x2A4C000ull
+#define DCORE2_TPC5_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE2_TPC5_EML_TPC_QM_SECTION 0x9000
+#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x2A4C900ull
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x2A4C908ull
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x2A4C910ull
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x2A4C918ull
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x2A4C920ull
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x2A4C928ull
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x2A4C930ull
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x2A4C938ull
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x2A4C940ull
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x2A4C948ull
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x2A4C950ull
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x2A4C958ull
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x2A4C960ull
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x2A4C968ull
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x2A4C970ull
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x2A4C978ull
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE2_TPC5_EML_TPC_QM_AXUSER_SECURED_BASE 0x2A4CB00ull
+#define DCORE2_TPC5_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE2_TPC5_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x2A4CB80ull
+#define DCORE2_TPC5_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE2_TPC5_EML_TPC_QM_DBG_HBW_BASE 0x2A4CC00ull
+#define DCORE2_TPC5_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC5_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_TPC5_EML_TPC_QM_DBG_LBW_BASE 0x2A4CC80ull
+#define DCORE2_TPC5_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC5_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE2_TPC5_EML_TPC_QM_CGM_BASE 0x2A4CD80ull
+#define DCORE2_TPC5_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE2_TPC5_EML_TPC_QM_CGM_SECTION 0x1000
+#define mmDCORE2_TPC5_EML_TPC_QM_SPECIAL_BASE 0x2A4CE80ull
+#define DCORE2_TPC5_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC5_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define mmDCORE2_TPC5_EML_CS_BASE 0x2BFF000ull
+#define DCORE2_TPC5_EML_CS_MAX_OFFSET 0x1000
+#define DCORE2_TPC5_EML_CS_SECTION 0x401000
+#define mmDCORE3_TPC0_ROM_TABLE_BASE 0x3000000ull
+#define DCORE3_TPC0_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE3_TPC0_ROM_TABLE_SECTION 0x1000
+#define mmDCORE3_TPC0_EML_SPMU_BASE 0x3001000ull
+#define DCORE3_TPC0_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_TPC0_EML_SPMU_SECTION 0x1000
+#define mmDCORE3_TPC0_EML_ETF_BASE 0x3002000ull
+#define DCORE3_TPC0_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE3_TPC0_EML_ETF_SECTION 0x1000
+#define mmDCORE3_TPC0_EML_STM_BASE 0x3003000ull
+#define DCORE3_TPC0_EML_STM_MAX_OFFSET 0x1000
+#define DCORE3_TPC0_EML_STM_SECTION 0x2000
+#define mmDCORE3_TPC0_EML_CTI_BASE 0x3005000ull
+#define DCORE3_TPC0_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE3_TPC0_EML_CTI_SECTION 0x1000
+#define mmDCORE3_TPC0_EML_FUNNEL_BASE 0x3006000ull
+#define DCORE3_TPC0_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_TPC0_EML_FUNNEL_SECTION 0x1000
+#define mmDCORE3_TPC0_EML_BUSMON_0_BASE 0x3007000ull
+#define DCORE3_TPC0_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE3_TPC0_EML_BUSMON_0_SECTION 0x1000
+#define mmDCORE3_TPC0_EML_BUSMON_1_BASE 0x3008000ull
+#define DCORE3_TPC0_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE3_TPC0_EML_BUSMON_1_SECTION 0x1000
+#define mmDCORE3_TPC0_EML_BUSMON_2_BASE 0x3009000ull
+#define DCORE3_TPC0_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE3_TPC0_EML_BUSMON_2_SECTION 0x1000
+#define mmDCORE3_TPC0_EML_BUSMON_3_BASE 0x300A000ull
+#define DCORE3_TPC0_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE3_TPC0_EML_BUSMON_3_SECTION 0x1000
+#define mmDCORE3_TPC0_QM_ARC_RTT_BASE 0x300B000ull
+#define DCORE3_TPC0_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE3_TPC0_QM_ARC_RTT_SECTION 0x35000
+#define mmDCORE3_TPC0_EML_CFG_BASE 0x3040000ull
+#define DCORE3_TPC0_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE3_TPC0_EML_CFG_SECTION 0xE800
+#define mmDCORE3_TPC0_EML_CFG_SPECIAL_BASE 0x3040E80ull
+#define DCORE3_TPC0_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC0_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x3041000ull
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE3_TPC0_EML_TPC_CFG_BASE 0x3041000ull
+#define DCORE3_TPC0_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE3_TPC0_EML_TPC_CFG_SECTION 0x5000
+#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x3041050ull
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x30410A0ull
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x30410F0ull
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x3041140ull
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x3041190ull
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x30411E0ull
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x3041230ull
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x3041280ull
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x30412D0ull
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x3041320ull
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x3041370ull
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x30413C0ull
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x3041410ull
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x3041460ull
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x30414B0ull
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x3041500ull
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_BASE 0x3041508ull
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_0_BASE 0x30415DCull
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_1_BASE 0x304162Cull
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_2_BASE 0x304167Cull
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_3_BASE 0x30416CCull
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_4_BASE 0x304171Cull
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_5_BASE 0x304176Cull
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_6_BASE 0x30417BCull
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_7_BASE 0x304180Cull
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_8_BASE 0x304185Cull
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_9_BASE 0x30418ACull
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_10_BASE 0x30418FCull
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_11_BASE 0x304194Cull
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_12_BASE 0x304199Cull
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_13_BASE 0x30419ECull
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_14_BASE 0x3041A3Cull
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_15_BASE 0x3041A8Cull
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE3_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x3041ADCull
+#define DCORE3_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE3_TPC0_EML_TPC_CFG_QM_BASE 0x3041AE4ull
+#define DCORE3_TPC0_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE3_TPC0_EML_TPC_CFG_QM_SECTION 0x31C0
+#define mmDCORE3_TPC0_EML_TPC_CFG_AXUSER_BASE 0x3041E00ull
+#define DCORE3_TPC0_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE3_TPC0_EML_TPC_CFG_SPECIAL_BASE 0x3041E80ull
+#define DCORE3_TPC0_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC0_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE3_TPC0_EML_QM_DCCM_BASE 0x3042000ull
+#define DCORE3_TPC0_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE3_TPC0_EML_QM_DCCM_SECTION 0x8000
+#define mmDCORE3_TPC0_EML_QM_ARCAUX_BASE 0x304A000ull
+#define DCORE3_TPC0_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE3_TPC0_EML_QM_ARCAUX_SECTION 0xE800
+#define mmDCORE3_TPC0_EML_QM_ARCAUX_SPECIAL_BASE 0x304AE80ull
+#define DCORE3_TPC0_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC0_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define mmDCORE3_TPC0_EML_TPC_QM_BASE 0x304C000ull
+#define DCORE3_TPC0_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE3_TPC0_EML_TPC_QM_SECTION 0x9000
+#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x304C900ull
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x304C908ull
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x304C910ull
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x304C918ull
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x304C920ull
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x304C928ull
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x304C930ull
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x304C938ull
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x304C940ull
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x304C948ull
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x304C950ull
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x304C958ull
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x304C960ull
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x304C968ull
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x304C970ull
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x304C978ull
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE3_TPC0_EML_TPC_QM_AXUSER_SECURED_BASE 0x304CB00ull
+#define DCORE3_TPC0_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE3_TPC0_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x304CB80ull
+#define DCORE3_TPC0_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE3_TPC0_EML_TPC_QM_DBG_HBW_BASE 0x304CC00ull
+#define DCORE3_TPC0_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC0_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_TPC0_EML_TPC_QM_DBG_LBW_BASE 0x304CC80ull
+#define DCORE3_TPC0_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC0_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE3_TPC0_EML_TPC_QM_CGM_BASE 0x304CD80ull
+#define DCORE3_TPC0_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE3_TPC0_EML_TPC_QM_CGM_SECTION 0x1000
+#define mmDCORE3_TPC0_EML_TPC_QM_SPECIAL_BASE 0x304CE80ull
+#define DCORE3_TPC0_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC0_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define mmDCORE3_TPC0_EML_CS_BASE 0x31FF000ull
+#define DCORE3_TPC0_EML_CS_MAX_OFFSET 0x1000
+#define DCORE3_TPC0_EML_CS_SECTION 0x1000
+#define mmDCORE3_TPC1_ROM_TABLE_BASE 0x3200000ull
+#define DCORE3_TPC1_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE3_TPC1_ROM_TABLE_SECTION 0x1000
+#define mmDCORE3_TPC1_EML_SPMU_BASE 0x3201000ull
+#define DCORE3_TPC1_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_TPC1_EML_SPMU_SECTION 0x1000
+#define mmDCORE3_TPC1_EML_ETF_BASE 0x3202000ull
+#define DCORE3_TPC1_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE3_TPC1_EML_ETF_SECTION 0x1000
+#define mmDCORE3_TPC1_EML_STM_BASE 0x3203000ull
+#define DCORE3_TPC1_EML_STM_MAX_OFFSET 0x1000
+#define DCORE3_TPC1_EML_STM_SECTION 0x2000
+#define mmDCORE3_TPC1_EML_CTI_BASE 0x3205000ull
+#define DCORE3_TPC1_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE3_TPC1_EML_CTI_SECTION 0x1000
+#define mmDCORE3_TPC1_EML_FUNNEL_BASE 0x3206000ull
+#define DCORE3_TPC1_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_TPC1_EML_FUNNEL_SECTION 0x1000
+#define mmDCORE3_TPC1_EML_BUSMON_0_BASE 0x3207000ull
+#define DCORE3_TPC1_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE3_TPC1_EML_BUSMON_0_SECTION 0x1000
+#define mmDCORE3_TPC1_EML_BUSMON_1_BASE 0x3208000ull
+#define DCORE3_TPC1_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE3_TPC1_EML_BUSMON_1_SECTION 0x1000
+#define mmDCORE3_TPC1_EML_BUSMON_2_BASE 0x3209000ull
+#define DCORE3_TPC1_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE3_TPC1_EML_BUSMON_2_SECTION 0x1000
+#define mmDCORE3_TPC1_EML_BUSMON_3_BASE 0x320A000ull
+#define DCORE3_TPC1_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE3_TPC1_EML_BUSMON_3_SECTION 0x1000
+#define mmDCORE3_TPC1_QM_ARC_RTT_BASE 0x320B000ull
+#define DCORE3_TPC1_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE3_TPC1_QM_ARC_RTT_SECTION 0x35000
+#define mmDCORE3_TPC1_EML_CFG_BASE 0x3240000ull
+#define DCORE3_TPC1_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE3_TPC1_EML_CFG_SECTION 0xE800
+#define mmDCORE3_TPC1_EML_CFG_SPECIAL_BASE 0x3240E80ull
+#define DCORE3_TPC1_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC1_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x3241000ull
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE3_TPC1_EML_TPC_CFG_BASE 0x3241000ull
+#define DCORE3_TPC1_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE3_TPC1_EML_TPC_CFG_SECTION 0x5000
+#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x3241050ull
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x32410A0ull
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x32410F0ull
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x3241140ull
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x3241190ull
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x32411E0ull
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x3241230ull
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x3241280ull
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x32412D0ull
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x3241320ull
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x3241370ull
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x32413C0ull
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x3241410ull
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x3241460ull
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x32414B0ull
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x3241500ull
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_BASE 0x3241508ull
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_0_BASE 0x32415DCull
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_1_BASE 0x324162Cull
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_2_BASE 0x324167Cull
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_3_BASE 0x32416CCull
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_4_BASE 0x324171Cull
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_5_BASE 0x324176Cull
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_6_BASE 0x32417BCull
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_7_BASE 0x324180Cull
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_8_BASE 0x324185Cull
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_9_BASE 0x32418ACull
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_10_BASE 0x32418FCull
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_11_BASE 0x324194Cull
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_12_BASE 0x324199Cull
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_13_BASE 0x32419ECull
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_14_BASE 0x3241A3Cull
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_15_BASE 0x3241A8Cull
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE3_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x3241ADCull
+#define DCORE3_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE3_TPC1_EML_TPC_CFG_QM_BASE 0x3241AE4ull
+#define DCORE3_TPC1_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE3_TPC1_EML_TPC_CFG_QM_SECTION 0x31C0
+#define mmDCORE3_TPC1_EML_TPC_CFG_AXUSER_BASE 0x3241E00ull
+#define DCORE3_TPC1_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE3_TPC1_EML_TPC_CFG_SPECIAL_BASE 0x3241E80ull
+#define DCORE3_TPC1_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC1_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE3_TPC1_EML_QM_DCCM_BASE 0x3242000ull
+#define DCORE3_TPC1_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE3_TPC1_EML_QM_DCCM_SECTION 0x8000
+#define mmDCORE3_TPC1_EML_QM_ARCAUX_BASE 0x324A000ull
+#define DCORE3_TPC1_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE3_TPC1_EML_QM_ARCAUX_SECTION 0xE800
+#define mmDCORE3_TPC1_EML_QM_ARCAUX_SPECIAL_BASE 0x324AE80ull
+#define DCORE3_TPC1_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC1_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define mmDCORE3_TPC1_EML_TPC_QM_BASE 0x324C000ull
+#define DCORE3_TPC1_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE3_TPC1_EML_TPC_QM_SECTION 0x9000
+#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x324C900ull
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x324C908ull
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x324C910ull
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x324C918ull
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x324C920ull
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x324C928ull
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x324C930ull
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x324C938ull
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x324C940ull
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x324C948ull
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x324C950ull
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x324C958ull
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x324C960ull
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x324C968ull
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x324C970ull
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x324C978ull
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE3_TPC1_EML_TPC_QM_AXUSER_SECURED_BASE 0x324CB00ull
+#define DCORE3_TPC1_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE3_TPC1_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x324CB80ull
+#define DCORE3_TPC1_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE3_TPC1_EML_TPC_QM_DBG_HBW_BASE 0x324CC00ull
+#define DCORE3_TPC1_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC1_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_TPC1_EML_TPC_QM_DBG_LBW_BASE 0x324CC80ull
+#define DCORE3_TPC1_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC1_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE3_TPC1_EML_TPC_QM_CGM_BASE 0x324CD80ull
+#define DCORE3_TPC1_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE3_TPC1_EML_TPC_QM_CGM_SECTION 0x1000
+#define mmDCORE3_TPC1_EML_TPC_QM_SPECIAL_BASE 0x324CE80ull
+#define DCORE3_TPC1_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC1_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define mmDCORE3_TPC1_EML_CS_BASE 0x33FF000ull
+#define DCORE3_TPC1_EML_CS_MAX_OFFSET 0x1000
+#define DCORE3_TPC1_EML_CS_SECTION 0x1000
+#define mmDCORE3_TPC2_ROM_TABLE_BASE 0x3400000ull
+#define DCORE3_TPC2_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE3_TPC2_ROM_TABLE_SECTION 0x1000
+#define mmDCORE3_TPC2_EML_SPMU_BASE 0x3401000ull
+#define DCORE3_TPC2_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_TPC2_EML_SPMU_SECTION 0x1000
+#define mmDCORE3_TPC2_EML_ETF_BASE 0x3402000ull
+#define DCORE3_TPC2_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE3_TPC2_EML_ETF_SECTION 0x1000
+#define mmDCORE3_TPC2_EML_STM_BASE 0x3403000ull
+#define DCORE3_TPC2_EML_STM_MAX_OFFSET 0x1000
+#define DCORE3_TPC2_EML_STM_SECTION 0x2000
+#define mmDCORE3_TPC2_EML_CTI_BASE 0x3405000ull
+#define DCORE3_TPC2_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE3_TPC2_EML_CTI_SECTION 0x1000
+#define mmDCORE3_TPC2_EML_FUNNEL_BASE 0x3406000ull
+#define DCORE3_TPC2_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_TPC2_EML_FUNNEL_SECTION 0x1000
+#define mmDCORE3_TPC2_EML_BUSMON_0_BASE 0x3407000ull
+#define DCORE3_TPC2_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE3_TPC2_EML_BUSMON_0_SECTION 0x1000
+#define mmDCORE3_TPC2_EML_BUSMON_1_BASE 0x3408000ull
+#define DCORE3_TPC2_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE3_TPC2_EML_BUSMON_1_SECTION 0x1000
+#define mmDCORE3_TPC2_EML_BUSMON_2_BASE 0x3409000ull
+#define DCORE3_TPC2_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE3_TPC2_EML_BUSMON_2_SECTION 0x1000
+#define mmDCORE3_TPC2_EML_BUSMON_3_BASE 0x340A000ull
+#define DCORE3_TPC2_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE3_TPC2_EML_BUSMON_3_SECTION 0x1000
+#define mmDCORE3_TPC2_QM_ARC_RTT_BASE 0x340B000ull
+#define DCORE3_TPC2_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE3_TPC2_QM_ARC_RTT_SECTION 0x35000
+#define mmDCORE3_TPC2_EML_CFG_BASE 0x3440000ull
+#define DCORE3_TPC2_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE3_TPC2_EML_CFG_SECTION 0xE800
+#define mmDCORE3_TPC2_EML_CFG_SPECIAL_BASE 0x3440E80ull
+#define DCORE3_TPC2_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC2_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x3441000ull
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE3_TPC2_EML_TPC_CFG_BASE 0x3441000ull
+#define DCORE3_TPC2_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE3_TPC2_EML_TPC_CFG_SECTION 0x5000
+#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x3441050ull
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x34410A0ull
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x34410F0ull
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x3441140ull
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x3441190ull
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x34411E0ull
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x3441230ull
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x3441280ull
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x34412D0ull
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x3441320ull
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x3441370ull
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x34413C0ull
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x3441410ull
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x3441460ull
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x34414B0ull
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x3441500ull
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_BASE 0x3441508ull
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_0_BASE 0x34415DCull
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_1_BASE 0x344162Cull
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_2_BASE 0x344167Cull
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_3_BASE 0x34416CCull
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_4_BASE 0x344171Cull
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_5_BASE 0x344176Cull
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_6_BASE 0x34417BCull
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_7_BASE 0x344180Cull
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_8_BASE 0x344185Cull
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_9_BASE 0x34418ACull
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_10_BASE 0x34418FCull
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_11_BASE 0x344194Cull
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_12_BASE 0x344199Cull
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_13_BASE 0x34419ECull
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_14_BASE 0x3441A3Cull
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_15_BASE 0x3441A8Cull
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE3_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x3441ADCull
+#define DCORE3_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE3_TPC2_EML_TPC_CFG_QM_BASE 0x3441AE4ull
+#define DCORE3_TPC2_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE3_TPC2_EML_TPC_CFG_QM_SECTION 0x31C0
+#define mmDCORE3_TPC2_EML_TPC_CFG_AXUSER_BASE 0x3441E00ull
+#define DCORE3_TPC2_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE3_TPC2_EML_TPC_CFG_SPECIAL_BASE 0x3441E80ull
+#define DCORE3_TPC2_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC2_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE3_TPC2_EML_QM_DCCM_BASE 0x3442000ull
+#define DCORE3_TPC2_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE3_TPC2_EML_QM_DCCM_SECTION 0x8000
+#define mmDCORE3_TPC2_EML_QM_ARCAUX_BASE 0x344A000ull
+#define DCORE3_TPC2_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE3_TPC2_EML_QM_ARCAUX_SECTION 0xE800
+#define mmDCORE3_TPC2_EML_QM_ARCAUX_SPECIAL_BASE 0x344AE80ull
+#define DCORE3_TPC2_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC2_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define mmDCORE3_TPC2_EML_TPC_QM_BASE 0x344C000ull
+#define DCORE3_TPC2_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE3_TPC2_EML_TPC_QM_SECTION 0x9000
+#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x344C900ull
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x344C908ull
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x344C910ull
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x344C918ull
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x344C920ull
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x344C928ull
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x344C930ull
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x344C938ull
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x344C940ull
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x344C948ull
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x344C950ull
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x344C958ull
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x344C960ull
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x344C968ull
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x344C970ull
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x344C978ull
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE3_TPC2_EML_TPC_QM_AXUSER_SECURED_BASE 0x344CB00ull
+#define DCORE3_TPC2_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE3_TPC2_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x344CB80ull
+#define DCORE3_TPC2_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE3_TPC2_EML_TPC_QM_DBG_HBW_BASE 0x344CC00ull
+#define DCORE3_TPC2_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC2_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_TPC2_EML_TPC_QM_DBG_LBW_BASE 0x344CC80ull
+#define DCORE3_TPC2_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC2_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE3_TPC2_EML_TPC_QM_CGM_BASE 0x344CD80ull
+#define DCORE3_TPC2_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE3_TPC2_EML_TPC_QM_CGM_SECTION 0x1000
+#define mmDCORE3_TPC2_EML_TPC_QM_SPECIAL_BASE 0x344CE80ull
+#define DCORE3_TPC2_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC2_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define mmDCORE3_TPC2_EML_CS_BASE 0x35FF000ull
+#define DCORE3_TPC2_EML_CS_MAX_OFFSET 0x1000
+#define DCORE3_TPC2_EML_CS_SECTION 0x1000
+#define mmDCORE3_TPC3_ROM_TABLE_BASE 0x3600000ull
+#define DCORE3_TPC3_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE3_TPC3_ROM_TABLE_SECTION 0x1000
+#define mmDCORE3_TPC3_EML_SPMU_BASE 0x3601000ull
+#define DCORE3_TPC3_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_TPC3_EML_SPMU_SECTION 0x1000
+#define mmDCORE3_TPC3_EML_ETF_BASE 0x3602000ull
+#define DCORE3_TPC3_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE3_TPC3_EML_ETF_SECTION 0x1000
+#define mmDCORE3_TPC3_EML_STM_BASE 0x3603000ull
+#define DCORE3_TPC3_EML_STM_MAX_OFFSET 0x1000
+#define DCORE3_TPC3_EML_STM_SECTION 0x2000
+#define mmDCORE3_TPC3_EML_CTI_BASE 0x3605000ull
+#define DCORE3_TPC3_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE3_TPC3_EML_CTI_SECTION 0x1000
+#define mmDCORE3_TPC3_EML_FUNNEL_BASE 0x3606000ull
+#define DCORE3_TPC3_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_TPC3_EML_FUNNEL_SECTION 0x1000
+#define mmDCORE3_TPC3_EML_BUSMON_0_BASE 0x3607000ull
+#define DCORE3_TPC3_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE3_TPC3_EML_BUSMON_0_SECTION 0x1000
+#define mmDCORE3_TPC3_EML_BUSMON_1_BASE 0x3608000ull
+#define DCORE3_TPC3_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE3_TPC3_EML_BUSMON_1_SECTION 0x1000
+#define mmDCORE3_TPC3_EML_BUSMON_2_BASE 0x3609000ull
+#define DCORE3_TPC3_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE3_TPC3_EML_BUSMON_2_SECTION 0x1000
+#define mmDCORE3_TPC3_EML_BUSMON_3_BASE 0x360A000ull
+#define DCORE3_TPC3_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE3_TPC3_EML_BUSMON_3_SECTION 0x1000
+#define mmDCORE3_TPC3_QM_ARC_RTT_BASE 0x360B000ull
+#define DCORE3_TPC3_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE3_TPC3_QM_ARC_RTT_SECTION 0x35000
+#define mmDCORE3_TPC3_EML_CFG_BASE 0x3640000ull
+#define DCORE3_TPC3_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE3_TPC3_EML_CFG_SECTION 0xE800
+#define mmDCORE3_TPC3_EML_CFG_SPECIAL_BASE 0x3640E80ull
+#define DCORE3_TPC3_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC3_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x3641000ull
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE3_TPC3_EML_TPC_CFG_BASE 0x3641000ull
+#define DCORE3_TPC3_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE3_TPC3_EML_TPC_CFG_SECTION 0x5000
+#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x3641050ull
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x36410A0ull
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x36410F0ull
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x3641140ull
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x3641190ull
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x36411E0ull
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x3641230ull
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x3641280ull
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x36412D0ull
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x3641320ull
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x3641370ull
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x36413C0ull
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x3641410ull
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x3641460ull
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x36414B0ull
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x3641500ull
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_BASE 0x3641508ull
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_0_BASE 0x36415DCull
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_1_BASE 0x364162Cull
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_2_BASE 0x364167Cull
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_3_BASE 0x36416CCull
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_4_BASE 0x364171Cull
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_5_BASE 0x364176Cull
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_6_BASE 0x36417BCull
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_7_BASE 0x364180Cull
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_8_BASE 0x364185Cull
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_9_BASE 0x36418ACull
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_10_BASE 0x36418FCull
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_11_BASE 0x364194Cull
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_12_BASE 0x364199Cull
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_13_BASE 0x36419ECull
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_14_BASE 0x3641A3Cull
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_15_BASE 0x3641A8Cull
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE3_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x3641ADCull
+#define DCORE3_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE3_TPC3_EML_TPC_CFG_QM_BASE 0x3641AE4ull
+#define DCORE3_TPC3_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE3_TPC3_EML_TPC_CFG_QM_SECTION 0x31C0
+#define mmDCORE3_TPC3_EML_TPC_CFG_AXUSER_BASE 0x3641E00ull
+#define DCORE3_TPC3_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE3_TPC3_EML_TPC_CFG_SPECIAL_BASE 0x3641E80ull
+#define DCORE3_TPC3_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC3_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE3_TPC3_EML_QM_DCCM_BASE 0x3642000ull
+#define DCORE3_TPC3_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE3_TPC3_EML_QM_DCCM_SECTION 0x8000
+#define mmDCORE3_TPC3_EML_QM_ARCAUX_BASE 0x364A000ull
+#define DCORE3_TPC3_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE3_TPC3_EML_QM_ARCAUX_SECTION 0xE800
+#define mmDCORE3_TPC3_EML_QM_ARCAUX_SPECIAL_BASE 0x364AE80ull
+#define DCORE3_TPC3_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC3_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define mmDCORE3_TPC3_EML_TPC_QM_BASE 0x364C000ull
+#define DCORE3_TPC3_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE3_TPC3_EML_TPC_QM_SECTION 0x9000
+#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x364C900ull
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x364C908ull
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x364C910ull
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x364C918ull
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x364C920ull
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x364C928ull
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x364C930ull
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x364C938ull
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x364C940ull
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x364C948ull
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x364C950ull
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x364C958ull
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x364C960ull
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x364C968ull
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x364C970ull
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x364C978ull
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE3_TPC3_EML_TPC_QM_AXUSER_SECURED_BASE 0x364CB00ull
+#define DCORE3_TPC3_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE3_TPC3_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x364CB80ull
+#define DCORE3_TPC3_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE3_TPC3_EML_TPC_QM_DBG_HBW_BASE 0x364CC00ull
+#define DCORE3_TPC3_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC3_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_TPC3_EML_TPC_QM_DBG_LBW_BASE 0x364CC80ull
+#define DCORE3_TPC3_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC3_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE3_TPC3_EML_TPC_QM_CGM_BASE 0x364CD80ull
+#define DCORE3_TPC3_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE3_TPC3_EML_TPC_QM_CGM_SECTION 0x1000
+#define mmDCORE3_TPC3_EML_TPC_QM_SPECIAL_BASE 0x364CE80ull
+#define DCORE3_TPC3_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC3_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define mmDCORE3_TPC3_EML_CS_BASE 0x37FF000ull
+#define DCORE3_TPC3_EML_CS_MAX_OFFSET 0x1000
+#define DCORE3_TPC3_EML_CS_SECTION 0x1000
+#define mmDCORE3_TPC4_ROM_TABLE_BASE 0x3800000ull
+#define DCORE3_TPC4_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE3_TPC4_ROM_TABLE_SECTION 0x1000
+#define mmDCORE3_TPC4_EML_SPMU_BASE 0x3801000ull
+#define DCORE3_TPC4_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_TPC4_EML_SPMU_SECTION 0x1000
+#define mmDCORE3_TPC4_EML_ETF_BASE 0x3802000ull
+#define DCORE3_TPC4_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE3_TPC4_EML_ETF_SECTION 0x1000
+#define mmDCORE3_TPC4_EML_STM_BASE 0x3803000ull
+#define DCORE3_TPC4_EML_STM_MAX_OFFSET 0x1000
+#define DCORE3_TPC4_EML_STM_SECTION 0x2000
+#define mmDCORE3_TPC4_EML_CTI_BASE 0x3805000ull
+#define DCORE3_TPC4_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE3_TPC4_EML_CTI_SECTION 0x1000
+#define mmDCORE3_TPC4_EML_FUNNEL_BASE 0x3806000ull
+#define DCORE3_TPC4_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_TPC4_EML_FUNNEL_SECTION 0x1000
+#define mmDCORE3_TPC4_EML_BUSMON_0_BASE 0x3807000ull
+#define DCORE3_TPC4_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE3_TPC4_EML_BUSMON_0_SECTION 0x1000
+#define mmDCORE3_TPC4_EML_BUSMON_1_BASE 0x3808000ull
+#define DCORE3_TPC4_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE3_TPC4_EML_BUSMON_1_SECTION 0x1000
+#define mmDCORE3_TPC4_EML_BUSMON_2_BASE 0x3809000ull
+#define DCORE3_TPC4_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE3_TPC4_EML_BUSMON_2_SECTION 0x1000
+#define mmDCORE3_TPC4_EML_BUSMON_3_BASE 0x380A000ull
+#define DCORE3_TPC4_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE3_TPC4_EML_BUSMON_3_SECTION 0x1000
+#define mmDCORE3_TPC4_QM_ARC_RTT_BASE 0x380B000ull
+#define DCORE3_TPC4_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE3_TPC4_QM_ARC_RTT_SECTION 0x35000
+#define mmDCORE3_TPC4_EML_CFG_BASE 0x3840000ull
+#define DCORE3_TPC4_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE3_TPC4_EML_CFG_SECTION 0xE800
+#define mmDCORE3_TPC4_EML_CFG_SPECIAL_BASE 0x3840E80ull
+#define DCORE3_TPC4_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC4_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x3841000ull
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE3_TPC4_EML_TPC_CFG_BASE 0x3841000ull
+#define DCORE3_TPC4_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE3_TPC4_EML_TPC_CFG_SECTION 0x5000
+#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x3841050ull
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x38410A0ull
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x38410F0ull
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x3841140ull
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x3841190ull
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x38411E0ull
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x3841230ull
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x3841280ull
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x38412D0ull
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x3841320ull
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x3841370ull
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x38413C0ull
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x3841410ull
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x3841460ull
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x38414B0ull
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x3841500ull
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_BASE 0x3841508ull
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_0_BASE 0x38415DCull
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_1_BASE 0x384162Cull
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_2_BASE 0x384167Cull
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_3_BASE 0x38416CCull
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_4_BASE 0x384171Cull
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_5_BASE 0x384176Cull
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_6_BASE 0x38417BCull
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_7_BASE 0x384180Cull
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_8_BASE 0x384185Cull
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_9_BASE 0x38418ACull
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_10_BASE 0x38418FCull
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_11_BASE 0x384194Cull
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_12_BASE 0x384199Cull
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_13_BASE 0x38419ECull
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_14_BASE 0x3841A3Cull
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_15_BASE 0x3841A8Cull
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE3_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x3841ADCull
+#define DCORE3_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE3_TPC4_EML_TPC_CFG_QM_BASE 0x3841AE4ull
+#define DCORE3_TPC4_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE3_TPC4_EML_TPC_CFG_QM_SECTION 0x31C0
+#define mmDCORE3_TPC4_EML_TPC_CFG_AXUSER_BASE 0x3841E00ull
+#define DCORE3_TPC4_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE3_TPC4_EML_TPC_CFG_SPECIAL_BASE 0x3841E80ull
+#define DCORE3_TPC4_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC4_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE3_TPC4_EML_QM_DCCM_BASE 0x3842000ull
+#define DCORE3_TPC4_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE3_TPC4_EML_QM_DCCM_SECTION 0x8000
+#define mmDCORE3_TPC4_EML_QM_ARCAUX_BASE 0x384A000ull
+#define DCORE3_TPC4_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE3_TPC4_EML_QM_ARCAUX_SECTION 0xE800
+#define mmDCORE3_TPC4_EML_QM_ARCAUX_SPECIAL_BASE 0x384AE80ull
+#define DCORE3_TPC4_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC4_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define mmDCORE3_TPC4_EML_TPC_QM_BASE 0x384C000ull
+#define DCORE3_TPC4_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE3_TPC4_EML_TPC_QM_SECTION 0x9000
+#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x384C900ull
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x384C908ull
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x384C910ull
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x384C918ull
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x384C920ull
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x384C928ull
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x384C930ull
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x384C938ull
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x384C940ull
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x384C948ull
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x384C950ull
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x384C958ull
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x384C960ull
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x384C968ull
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x384C970ull
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x384C978ull
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE3_TPC4_EML_TPC_QM_AXUSER_SECURED_BASE 0x384CB00ull
+#define DCORE3_TPC4_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE3_TPC4_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x384CB80ull
+#define DCORE3_TPC4_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE3_TPC4_EML_TPC_QM_DBG_HBW_BASE 0x384CC00ull
+#define DCORE3_TPC4_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC4_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_TPC4_EML_TPC_QM_DBG_LBW_BASE 0x384CC80ull
+#define DCORE3_TPC4_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC4_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE3_TPC4_EML_TPC_QM_CGM_BASE 0x384CD80ull
+#define DCORE3_TPC4_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE3_TPC4_EML_TPC_QM_CGM_SECTION 0x1000
+#define mmDCORE3_TPC4_EML_TPC_QM_SPECIAL_BASE 0x384CE80ull
+#define DCORE3_TPC4_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC4_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define mmDCORE3_TPC4_EML_CS_BASE 0x39FF000ull
+#define DCORE3_TPC4_EML_CS_MAX_OFFSET 0x1000
+#define DCORE3_TPC4_EML_CS_SECTION 0x1000
+#define mmDCORE3_TPC5_ROM_TABLE_BASE 0x3A00000ull
+#define DCORE3_TPC5_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE3_TPC5_ROM_TABLE_SECTION 0x1000
+#define mmDCORE3_TPC5_EML_SPMU_BASE 0x3A01000ull
+#define DCORE3_TPC5_EML_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_TPC5_EML_SPMU_SECTION 0x1000
+#define mmDCORE3_TPC5_EML_ETF_BASE 0x3A02000ull
+#define DCORE3_TPC5_EML_ETF_MAX_OFFSET 0x1000
+#define DCORE3_TPC5_EML_ETF_SECTION 0x1000
+#define mmDCORE3_TPC5_EML_STM_BASE 0x3A03000ull
+#define DCORE3_TPC5_EML_STM_MAX_OFFSET 0x1000
+#define DCORE3_TPC5_EML_STM_SECTION 0x2000
+#define mmDCORE3_TPC5_EML_CTI_BASE 0x3A05000ull
+#define DCORE3_TPC5_EML_CTI_MAX_OFFSET 0x1000
+#define DCORE3_TPC5_EML_CTI_SECTION 0x1000
+#define mmDCORE3_TPC5_EML_FUNNEL_BASE 0x3A06000ull
+#define DCORE3_TPC5_EML_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_TPC5_EML_FUNNEL_SECTION 0x1000
+#define mmDCORE3_TPC5_EML_BUSMON_0_BASE 0x3A07000ull
+#define DCORE3_TPC5_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define DCORE3_TPC5_EML_BUSMON_0_SECTION 0x1000
+#define mmDCORE3_TPC5_EML_BUSMON_1_BASE 0x3A08000ull
+#define DCORE3_TPC5_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define DCORE3_TPC5_EML_BUSMON_1_SECTION 0x1000
+#define mmDCORE3_TPC5_EML_BUSMON_2_BASE 0x3A09000ull
+#define DCORE3_TPC5_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define DCORE3_TPC5_EML_BUSMON_2_SECTION 0x1000
+#define mmDCORE3_TPC5_EML_BUSMON_3_BASE 0x3A0A000ull
+#define DCORE3_TPC5_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define DCORE3_TPC5_EML_BUSMON_3_SECTION 0x1000
+#define mmDCORE3_TPC5_QM_ARC_RTT_BASE 0x3A0B000ull
+#define DCORE3_TPC5_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE3_TPC5_QM_ARC_RTT_SECTION 0x35000
+#define mmDCORE3_TPC5_EML_CFG_BASE 0x3A40000ull
+#define DCORE3_TPC5_EML_CFG_MAX_OFFSET 0x1000
+#define DCORE3_TPC5_EML_CFG_SECTION 0xE800
+#define mmDCORE3_TPC5_EML_CFG_SPECIAL_BASE 0x3A40E80ull
+#define DCORE3_TPC5_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC5_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x3A41000ull
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE3_TPC5_EML_TPC_CFG_BASE 0x3A41000ull
+#define DCORE3_TPC5_EML_TPC_CFG_MAX_OFFSET 0x1000
+#define DCORE3_TPC5_EML_TPC_CFG_SECTION 0x5000
+#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x3A41050ull
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x3A410A0ull
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x3A410F0ull
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x3A41140ull
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x3A41190ull
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x3A411E0ull
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x3A41230ull
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x3A41280ull
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x3A412D0ull
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x3A41320ull
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x3A41370ull
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x3A413C0ull
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x3A41410ull
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x3A41460ull
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x3A414B0ull
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x3A41500ull
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_BASE 0x3A41508ull
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_0_BASE 0x3A415DCull
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_1_BASE 0x3A4162Cull
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_2_BASE 0x3A4167Cull
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_3_BASE 0x3A416CCull
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_4_BASE 0x3A4171Cull
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_5_BASE 0x3A4176Cull
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_6_BASE 0x3A417BCull
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_7_BASE 0x3A4180Cull
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_8_BASE 0x3A4185Cull
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_9_BASE 0x3A418ACull
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_10_BASE 0x3A418FCull
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_11_BASE 0x3A4194Cull
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_12_BASE 0x3A4199Cull
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_13_BASE 0x3A419ECull
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_14_BASE 0x3A41A3Cull
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_15_BASE 0x3A41A8Cull
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE3_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x3A41ADCull
+#define DCORE3_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE3_TPC5_EML_TPC_CFG_QM_BASE 0x3A41AE4ull
+#define DCORE3_TPC5_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE3_TPC5_EML_TPC_CFG_QM_SECTION 0x31C0
+#define mmDCORE3_TPC5_EML_TPC_CFG_AXUSER_BASE 0x3A41E00ull
+#define DCORE3_TPC5_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE3_TPC5_EML_TPC_CFG_SPECIAL_BASE 0x3A41E80ull
+#define DCORE3_TPC5_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC5_EML_TPC_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE3_TPC5_EML_QM_DCCM_BASE 0x3A42000ull
+#define DCORE3_TPC5_EML_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE3_TPC5_EML_QM_DCCM_SECTION 0x8000
+#define mmDCORE3_TPC5_EML_QM_ARCAUX_BASE 0x3A4A000ull
+#define DCORE3_TPC5_EML_QM_ARCAUX_MAX_OFFSET 0x1000
+#define DCORE3_TPC5_EML_QM_ARCAUX_SECTION 0xE800
+#define mmDCORE3_TPC5_EML_QM_ARCAUX_SPECIAL_BASE 0x3A4AE80ull
+#define DCORE3_TPC5_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC5_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
+#define mmDCORE3_TPC5_EML_TPC_QM_BASE 0x3A4C000ull
+#define DCORE3_TPC5_EML_TPC_QM_MAX_OFFSET 0x1000
+#define DCORE3_TPC5_EML_TPC_QM_SECTION 0x9000
+#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x3A4C900ull
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x3A4C908ull
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x3A4C910ull
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x3A4C918ull
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x3A4C920ull
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x3A4C928ull
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x3A4C930ull
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x3A4C938ull
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x3A4C940ull
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x3A4C948ull
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x3A4C950ull
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x3A4C958ull
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x3A4C960ull
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x3A4C968ull
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x3A4C970ull
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x3A4C978ull
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE3_TPC5_EML_TPC_QM_AXUSER_SECURED_BASE 0x3A4CB00ull
+#define DCORE3_TPC5_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE3_TPC5_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x3A4CB80ull
+#define DCORE3_TPC5_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE3_TPC5_EML_TPC_QM_DBG_HBW_BASE 0x3A4CC00ull
+#define DCORE3_TPC5_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC5_EML_TPC_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_TPC5_EML_TPC_QM_DBG_LBW_BASE 0x3A4CC80ull
+#define DCORE3_TPC5_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC5_EML_TPC_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE3_TPC5_EML_TPC_QM_CGM_BASE 0x3A4CD80ull
+#define DCORE3_TPC5_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE3_TPC5_EML_TPC_QM_CGM_SECTION 0x1000
+#define mmDCORE3_TPC5_EML_TPC_QM_SPECIAL_BASE 0x3A4CE80ull
+#define DCORE3_TPC5_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC5_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
+#define mmDCORE3_TPC5_EML_CS_BASE 0x3BFF000ull
+#define DCORE3_TPC5_EML_CS_MAX_OFFSET 0x1000
+#define DCORE3_TPC5_EML_CS_SECTION 0x401000
+#define mmDCORE0_TPC0_QM_DCCM_BASE 0x4000000ull
+#define DCORE0_TPC0_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE0_TPC0_QM_DCCM_SECTION 0x8000
+#define mmDCORE0_TPC0_QM_ARC_AUX_BASE 0x4008000ull
+#define DCORE0_TPC0_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE0_TPC0_QM_ARC_AUX_SECTION 0xE800
+#define mmDCORE0_TPC0_QM_ARC_AUX_SPECIAL_BASE 0x4008E80ull
+#define DCORE0_TPC0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC0_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define mmDCORE0_TPC0_QM_BASE 0x400A000ull
+#define DCORE0_TPC0_QM_MAX_OFFSET 0x1000
+#define DCORE0_TPC0_QM_SECTION 0x9000
+#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x400A900ull
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x400A908ull
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x400A910ull
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x400A918ull
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x400A920ull
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x400A928ull
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x400A930ull
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x400A938ull
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x400A940ull
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x400A948ull
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x400A950ull
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x400A958ull
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x400A960ull
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x400A968ull
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x400A970ull
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x400A978ull
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE0_TPC0_QM_AXUSER_SECURED_BASE 0x400AB00ull
+#define DCORE0_TPC0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_BASE 0x400AB80ull
+#define DCORE0_TPC0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE0_TPC0_QM_DBG_HBW_BASE 0x400AC00ull
+#define DCORE0_TPC0_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC0_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_TPC0_QM_DBG_LBW_BASE 0x400AC80ull
+#define DCORE0_TPC0_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC0_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE0_TPC0_QM_CGM_BASE 0x400AD80ull
+#define DCORE0_TPC0_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE0_TPC0_QM_CGM_SECTION 0x1000
+#define mmDCORE0_TPC0_QM_SPECIAL_BASE 0x400AE80ull
+#define DCORE0_TPC0_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC0_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE 0x400B000ull
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC0_CFG_BASE 0x400B000ull
+#define DCORE0_TPC0_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC0_CFG_SECTION 0x5000
+#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_1_BASE 0x400B050ull
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_2_BASE 0x400B0A0ull
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_3_BASE 0x400B0F0ull
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_4_BASE 0x400B140ull
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_5_BASE 0x400B190ull
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_6_BASE 0x400B1E0ull
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_7_BASE 0x400B230ull
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_8_BASE 0x400B280ull
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_9_BASE 0x400B2D0ull
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_10_BASE 0x400B320ull
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_11_BASE 0x400B370ull
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_12_BASE 0x400B3C0ull
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_13_BASE 0x400B410ull
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_14_BASE 0x400B460ull
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_15_BASE 0x400B4B0ull
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE0_TPC0_CFG_KERNEL_SYNC_OBJECT_BASE 0x400B500ull
+#define DCORE0_TPC0_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE0_TPC0_CFG_KERNEL_BASE 0x400B508ull
+#define DCORE0_TPC0_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE0_TPC0_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE 0x400B5DCull
+#define DCORE0_TPC0_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE0_TPC0_CFG_QM_TENSOR_1_BASE 0x400B62Cull
+#define DCORE0_TPC0_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE0_TPC0_CFG_QM_TENSOR_2_BASE 0x400B67Cull
+#define DCORE0_TPC0_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE0_TPC0_CFG_QM_TENSOR_3_BASE 0x400B6CCull
+#define DCORE0_TPC0_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE0_TPC0_CFG_QM_TENSOR_4_BASE 0x400B71Cull
+#define DCORE0_TPC0_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE0_TPC0_CFG_QM_TENSOR_5_BASE 0x400B76Cull
+#define DCORE0_TPC0_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE0_TPC0_CFG_QM_TENSOR_6_BASE 0x400B7BCull
+#define DCORE0_TPC0_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE0_TPC0_CFG_QM_TENSOR_7_BASE 0x400B80Cull
+#define DCORE0_TPC0_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE0_TPC0_CFG_QM_TENSOR_8_BASE 0x400B85Cull
+#define DCORE0_TPC0_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE0_TPC0_CFG_QM_TENSOR_9_BASE 0x400B8ACull
+#define DCORE0_TPC0_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE0_TPC0_CFG_QM_TENSOR_10_BASE 0x400B8FCull
+#define DCORE0_TPC0_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE0_TPC0_CFG_QM_TENSOR_11_BASE 0x400B94Cull
+#define DCORE0_TPC0_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE0_TPC0_CFG_QM_TENSOR_12_BASE 0x400B99Cull
+#define DCORE0_TPC0_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE0_TPC0_CFG_QM_TENSOR_13_BASE 0x400B9ECull
+#define DCORE0_TPC0_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE0_TPC0_CFG_QM_TENSOR_14_BASE 0x400BA3Cull
+#define DCORE0_TPC0_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE0_TPC0_CFG_QM_TENSOR_15_BASE 0x400BA8Cull
+#define DCORE0_TPC0_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE0_TPC0_CFG_QM_SYNC_OBJECT_BASE 0x400BADCull
+#define DCORE0_TPC0_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE0_TPC0_CFG_QM_BASE 0x400BAE4ull
+#define DCORE0_TPC0_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE0_TPC0_CFG_QM_SECTION 0x31C0
+#define mmDCORE0_TPC0_CFG_AXUSER_BASE 0x400BE00ull
+#define DCORE0_TPC0_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE0_TPC0_CFG_SPECIAL_BASE 0x400BE80ull
+#define DCORE0_TPC0_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC0_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC0_MSTR_IF_RR_SHRD_HBW_BASE 0x400C000ull
+#define DCORE0_TPC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_TPC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE0_TPC0_MSTR_IF_RR_PRVT_HBW_BASE 0x400C200ull
+#define DCORE0_TPC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_TPC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE0_TPC0_MSTR_IF_RR_SHRD_LBW_BASE 0x400C400ull
+#define DCORE0_TPC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_TPC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE0_TPC0_MSTR_IF_RR_PRVT_LBW_BASE 0x400C600ull
+#define DCORE0_TPC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_TPC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE0_TPC0_MSTR_IF_E2E_CRDT_BASE 0x400C800ull
+#define DCORE0_TPC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_TPC0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE0_TPC0_MSTR_IF_AXUSER_BASE 0x400CA80ull
+#define DCORE0_TPC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC0_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE0_TPC0_MSTR_IF_DBG_HBW_BASE 0x400CB00ull
+#define DCORE0_TPC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_TPC0_MSTR_IF_DBG_LBW_BASE 0x400CB80ull
+#define DCORE0_TPC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE0_TPC0_MSTR_IF_CORE_HBW_BASE 0x400CC00ull
+#define DCORE0_TPC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_TPC0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE0_TPC0_MSTR_IF_CORE_LBW_BASE 0x400CD80ull
+#define DCORE0_TPC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_TPC0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE0_TPC0_MSTR_IF_SPECIAL_BASE 0x400CE80ull
+#define DCORE0_TPC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC0_MSTR_IF_SPECIAL_SECTION 0x3180
+#define mmDCORE0_TPC1_QM_DCCM_BASE 0x4010000ull
+#define DCORE0_TPC1_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE0_TPC1_QM_DCCM_SECTION 0x8000
+#define mmDCORE0_TPC1_QM_ARC_AUX_BASE 0x4018000ull
+#define DCORE0_TPC1_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE0_TPC1_QM_ARC_AUX_SECTION 0xE800
+#define mmDCORE0_TPC1_QM_ARC_AUX_SPECIAL_BASE 0x4018E80ull
+#define DCORE0_TPC1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC1_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define mmDCORE0_TPC1_QM_BASE 0x401A000ull
+#define DCORE0_TPC1_QM_MAX_OFFSET 0x1000
+#define DCORE0_TPC1_QM_SECTION 0x9000
+#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x401A900ull
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x401A908ull
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x401A910ull
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x401A918ull
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x401A920ull
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x401A928ull
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x401A930ull
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x401A938ull
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x401A940ull
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x401A948ull
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x401A950ull
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x401A958ull
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x401A960ull
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x401A968ull
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x401A970ull
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x401A978ull
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE0_TPC1_QM_AXUSER_SECURED_BASE 0x401AB00ull
+#define DCORE0_TPC1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE0_TPC1_QM_AXUSER_NONSECURED_BASE 0x401AB80ull
+#define DCORE0_TPC1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE0_TPC1_QM_DBG_HBW_BASE 0x401AC00ull
+#define DCORE0_TPC1_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC1_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_TPC1_QM_DBG_LBW_BASE 0x401AC80ull
+#define DCORE0_TPC1_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC1_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE0_TPC1_QM_CGM_BASE 0x401AD80ull
+#define DCORE0_TPC1_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE0_TPC1_QM_CGM_SECTION 0x1000
+#define mmDCORE0_TPC1_QM_SPECIAL_BASE 0x401AE80ull
+#define DCORE0_TPC1_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC1_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_0_BASE 0x401B000ull
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC1_CFG_BASE 0x401B000ull
+#define DCORE0_TPC1_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC1_CFG_SECTION 0x5000
+#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_1_BASE 0x401B050ull
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_2_BASE 0x401B0A0ull
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_3_BASE 0x401B0F0ull
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_4_BASE 0x401B140ull
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_5_BASE 0x401B190ull
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_6_BASE 0x401B1E0ull
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_7_BASE 0x401B230ull
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_8_BASE 0x401B280ull
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_9_BASE 0x401B2D0ull
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_10_BASE 0x401B320ull
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_11_BASE 0x401B370ull
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_12_BASE 0x401B3C0ull
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_13_BASE 0x401B410ull
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_14_BASE 0x401B460ull
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_15_BASE 0x401B4B0ull
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE0_TPC1_CFG_KERNEL_SYNC_OBJECT_BASE 0x401B500ull
+#define DCORE0_TPC1_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE0_TPC1_CFG_KERNEL_BASE 0x401B508ull
+#define DCORE0_TPC1_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE0_TPC1_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE0_TPC1_CFG_QM_TENSOR_0_BASE 0x401B5DCull
+#define DCORE0_TPC1_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE0_TPC1_CFG_QM_TENSOR_1_BASE 0x401B62Cull
+#define DCORE0_TPC1_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE0_TPC1_CFG_QM_TENSOR_2_BASE 0x401B67Cull
+#define DCORE0_TPC1_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE0_TPC1_CFG_QM_TENSOR_3_BASE 0x401B6CCull
+#define DCORE0_TPC1_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE0_TPC1_CFG_QM_TENSOR_4_BASE 0x401B71Cull
+#define DCORE0_TPC1_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE0_TPC1_CFG_QM_TENSOR_5_BASE 0x401B76Cull
+#define DCORE0_TPC1_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE0_TPC1_CFG_QM_TENSOR_6_BASE 0x401B7BCull
+#define DCORE0_TPC1_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE0_TPC1_CFG_QM_TENSOR_7_BASE 0x401B80Cull
+#define DCORE0_TPC1_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE0_TPC1_CFG_QM_TENSOR_8_BASE 0x401B85Cull
+#define DCORE0_TPC1_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE0_TPC1_CFG_QM_TENSOR_9_BASE 0x401B8ACull
+#define DCORE0_TPC1_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE0_TPC1_CFG_QM_TENSOR_10_BASE 0x401B8FCull
+#define DCORE0_TPC1_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE0_TPC1_CFG_QM_TENSOR_11_BASE 0x401B94Cull
+#define DCORE0_TPC1_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE0_TPC1_CFG_QM_TENSOR_12_BASE 0x401B99Cull
+#define DCORE0_TPC1_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE0_TPC1_CFG_QM_TENSOR_13_BASE 0x401B9ECull
+#define DCORE0_TPC1_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE0_TPC1_CFG_QM_TENSOR_14_BASE 0x401BA3Cull
+#define DCORE0_TPC1_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE0_TPC1_CFG_QM_TENSOR_15_BASE 0x401BA8Cull
+#define DCORE0_TPC1_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE0_TPC1_CFG_QM_SYNC_OBJECT_BASE 0x401BADCull
+#define DCORE0_TPC1_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE0_TPC1_CFG_QM_BASE 0x401BAE4ull
+#define DCORE0_TPC1_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE0_TPC1_CFG_QM_SECTION 0x31C0
+#define mmDCORE0_TPC1_CFG_AXUSER_BASE 0x401BE00ull
+#define DCORE0_TPC1_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE0_TPC1_CFG_SPECIAL_BASE 0x401BE80ull
+#define DCORE0_TPC1_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC1_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC1_MSTR_IF_RR_SHRD_HBW_BASE 0x401C000ull
+#define DCORE0_TPC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_TPC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE0_TPC1_MSTR_IF_RR_PRVT_HBW_BASE 0x401C200ull
+#define DCORE0_TPC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_TPC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE0_TPC1_MSTR_IF_RR_SHRD_LBW_BASE 0x401C400ull
+#define DCORE0_TPC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_TPC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE0_TPC1_MSTR_IF_RR_PRVT_LBW_BASE 0x401C600ull
+#define DCORE0_TPC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_TPC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE0_TPC1_MSTR_IF_E2E_CRDT_BASE 0x401C800ull
+#define DCORE0_TPC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_TPC1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE0_TPC1_MSTR_IF_AXUSER_BASE 0x401CA80ull
+#define DCORE0_TPC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC1_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE0_TPC1_MSTR_IF_DBG_HBW_BASE 0x401CB00ull
+#define DCORE0_TPC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_TPC1_MSTR_IF_DBG_LBW_BASE 0x401CB80ull
+#define DCORE0_TPC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE0_TPC1_MSTR_IF_CORE_HBW_BASE 0x401CC00ull
+#define DCORE0_TPC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_TPC1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE0_TPC1_MSTR_IF_CORE_LBW_BASE 0x401CD80ull
+#define DCORE0_TPC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_TPC1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE0_TPC1_MSTR_IF_SPECIAL_BASE 0x401CE80ull
+#define DCORE0_TPC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC1_MSTR_IF_SPECIAL_SECTION 0x3180
+#define mmDCORE0_TPC2_QM_DCCM_BASE 0x4020000ull
+#define DCORE0_TPC2_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE0_TPC2_QM_DCCM_SECTION 0x8000
+#define mmDCORE0_TPC2_QM_ARC_AUX_BASE 0x4028000ull
+#define DCORE0_TPC2_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE0_TPC2_QM_ARC_AUX_SECTION 0xE800
+#define mmDCORE0_TPC2_QM_ARC_AUX_SPECIAL_BASE 0x4028E80ull
+#define DCORE0_TPC2_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC2_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define mmDCORE0_TPC2_QM_BASE 0x402A000ull
+#define DCORE0_TPC2_QM_MAX_OFFSET 0x1000
+#define DCORE0_TPC2_QM_SECTION 0x9000
+#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR0_BASE 0x402A900ull
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR1_BASE 0x402A908ull
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR2_BASE 0x402A910ull
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR3_BASE 0x402A918ull
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR4_BASE 0x402A920ull
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR5_BASE 0x402A928ull
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR6_BASE 0x402A930ull
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR7_BASE 0x402A938ull
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR8_BASE 0x402A940ull
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR9_BASE 0x402A948ull
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR10_BASE 0x402A950ull
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR11_BASE 0x402A958ull
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR12_BASE 0x402A960ull
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR13_BASE 0x402A968ull
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR14_BASE 0x402A970ull
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR15_BASE 0x402A978ull
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE0_TPC2_QM_AXUSER_SECURED_BASE 0x402AB00ull
+#define DCORE0_TPC2_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE0_TPC2_QM_AXUSER_NONSECURED_BASE 0x402AB80ull
+#define DCORE0_TPC2_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE0_TPC2_QM_DBG_HBW_BASE 0x402AC00ull
+#define DCORE0_TPC2_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC2_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_TPC2_QM_DBG_LBW_BASE 0x402AC80ull
+#define DCORE0_TPC2_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC2_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE0_TPC2_QM_CGM_BASE 0x402AD80ull
+#define DCORE0_TPC2_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE0_TPC2_QM_CGM_SECTION 0x1000
+#define mmDCORE0_TPC2_QM_SPECIAL_BASE 0x402AE80ull
+#define DCORE0_TPC2_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC2_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_0_BASE 0x402B000ull
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC2_CFG_BASE 0x402B000ull
+#define DCORE0_TPC2_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC2_CFG_SECTION 0x5000
+#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_1_BASE 0x402B050ull
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_2_BASE 0x402B0A0ull
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_3_BASE 0x402B0F0ull
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_4_BASE 0x402B140ull
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_5_BASE 0x402B190ull
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_6_BASE 0x402B1E0ull
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_7_BASE 0x402B230ull
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_8_BASE 0x402B280ull
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_9_BASE 0x402B2D0ull
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_10_BASE 0x402B320ull
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_11_BASE 0x402B370ull
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_12_BASE 0x402B3C0ull
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_13_BASE 0x402B410ull
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_14_BASE 0x402B460ull
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_15_BASE 0x402B4B0ull
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE0_TPC2_CFG_KERNEL_SYNC_OBJECT_BASE 0x402B500ull
+#define DCORE0_TPC2_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE0_TPC2_CFG_KERNEL_BASE 0x402B508ull
+#define DCORE0_TPC2_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE0_TPC2_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE0_TPC2_CFG_QM_TENSOR_0_BASE 0x402B5DCull
+#define DCORE0_TPC2_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE0_TPC2_CFG_QM_TENSOR_1_BASE 0x402B62Cull
+#define DCORE0_TPC2_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE0_TPC2_CFG_QM_TENSOR_2_BASE 0x402B67Cull
+#define DCORE0_TPC2_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE0_TPC2_CFG_QM_TENSOR_3_BASE 0x402B6CCull
+#define DCORE0_TPC2_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE0_TPC2_CFG_QM_TENSOR_4_BASE 0x402B71Cull
+#define DCORE0_TPC2_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE0_TPC2_CFG_QM_TENSOR_5_BASE 0x402B76Cull
+#define DCORE0_TPC2_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE0_TPC2_CFG_QM_TENSOR_6_BASE 0x402B7BCull
+#define DCORE0_TPC2_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE0_TPC2_CFG_QM_TENSOR_7_BASE 0x402B80Cull
+#define DCORE0_TPC2_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE0_TPC2_CFG_QM_TENSOR_8_BASE 0x402B85Cull
+#define DCORE0_TPC2_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE0_TPC2_CFG_QM_TENSOR_9_BASE 0x402B8ACull
+#define DCORE0_TPC2_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE0_TPC2_CFG_QM_TENSOR_10_BASE 0x402B8FCull
+#define DCORE0_TPC2_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE0_TPC2_CFG_QM_TENSOR_11_BASE 0x402B94Cull
+#define DCORE0_TPC2_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE0_TPC2_CFG_QM_TENSOR_12_BASE 0x402B99Cull
+#define DCORE0_TPC2_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE0_TPC2_CFG_QM_TENSOR_13_BASE 0x402B9ECull
+#define DCORE0_TPC2_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE0_TPC2_CFG_QM_TENSOR_14_BASE 0x402BA3Cull
+#define DCORE0_TPC2_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE0_TPC2_CFG_QM_TENSOR_15_BASE 0x402BA8Cull
+#define DCORE0_TPC2_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE0_TPC2_CFG_QM_SYNC_OBJECT_BASE 0x402BADCull
+#define DCORE0_TPC2_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE0_TPC2_CFG_QM_BASE 0x402BAE4ull
+#define DCORE0_TPC2_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE0_TPC2_CFG_QM_SECTION 0x31C0
+#define mmDCORE0_TPC2_CFG_AXUSER_BASE 0x402BE00ull
+#define DCORE0_TPC2_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE0_TPC2_CFG_SPECIAL_BASE 0x402BE80ull
+#define DCORE0_TPC2_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC2_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC2_MSTR_IF_RR_SHRD_HBW_BASE 0x402C000ull
+#define DCORE0_TPC2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_TPC2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE0_TPC2_MSTR_IF_RR_PRVT_HBW_BASE 0x402C200ull
+#define DCORE0_TPC2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_TPC2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE0_TPC2_MSTR_IF_RR_SHRD_LBW_BASE 0x402C400ull
+#define DCORE0_TPC2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_TPC2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE0_TPC2_MSTR_IF_RR_PRVT_LBW_BASE 0x402C600ull
+#define DCORE0_TPC2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_TPC2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE0_TPC2_MSTR_IF_E2E_CRDT_BASE 0x402C800ull
+#define DCORE0_TPC2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_TPC2_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE0_TPC2_MSTR_IF_AXUSER_BASE 0x402CA80ull
+#define DCORE0_TPC2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC2_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE0_TPC2_MSTR_IF_DBG_HBW_BASE 0x402CB00ull
+#define DCORE0_TPC2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC2_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_TPC2_MSTR_IF_DBG_LBW_BASE 0x402CB80ull
+#define DCORE0_TPC2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC2_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE0_TPC2_MSTR_IF_CORE_HBW_BASE 0x402CC00ull
+#define DCORE0_TPC2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_TPC2_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE0_TPC2_MSTR_IF_CORE_LBW_BASE 0x402CD80ull
+#define DCORE0_TPC2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_TPC2_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE0_TPC2_MSTR_IF_SPECIAL_BASE 0x402CE80ull
+#define DCORE0_TPC2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC2_MSTR_IF_SPECIAL_SECTION 0x3180
+#define mmDCORE0_TPC3_QM_DCCM_BASE 0x4030000ull
+#define DCORE0_TPC3_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE0_TPC3_QM_DCCM_SECTION 0x8000
+#define mmDCORE0_TPC3_QM_ARC_AUX_BASE 0x4038000ull
+#define DCORE0_TPC3_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE0_TPC3_QM_ARC_AUX_SECTION 0xE800
+#define mmDCORE0_TPC3_QM_ARC_AUX_SPECIAL_BASE 0x4038E80ull
+#define DCORE0_TPC3_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC3_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define mmDCORE0_TPC3_QM_BASE 0x403A000ull
+#define DCORE0_TPC3_QM_MAX_OFFSET 0x1000
+#define DCORE0_TPC3_QM_SECTION 0x9000
+#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR0_BASE 0x403A900ull
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR1_BASE 0x403A908ull
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR2_BASE 0x403A910ull
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR3_BASE 0x403A918ull
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR4_BASE 0x403A920ull
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR5_BASE 0x403A928ull
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR6_BASE 0x403A930ull
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR7_BASE 0x403A938ull
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR8_BASE 0x403A940ull
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR9_BASE 0x403A948ull
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR10_BASE 0x403A950ull
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR11_BASE 0x403A958ull
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR12_BASE 0x403A960ull
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR13_BASE 0x403A968ull
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR14_BASE 0x403A970ull
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR15_BASE 0x403A978ull
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE0_TPC3_QM_AXUSER_SECURED_BASE 0x403AB00ull
+#define DCORE0_TPC3_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE0_TPC3_QM_AXUSER_NONSECURED_BASE 0x403AB80ull
+#define DCORE0_TPC3_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE0_TPC3_QM_DBG_HBW_BASE 0x403AC00ull
+#define DCORE0_TPC3_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC3_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_TPC3_QM_DBG_LBW_BASE 0x403AC80ull
+#define DCORE0_TPC3_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC3_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE0_TPC3_QM_CGM_BASE 0x403AD80ull
+#define DCORE0_TPC3_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE0_TPC3_QM_CGM_SECTION 0x1000
+#define mmDCORE0_TPC3_QM_SPECIAL_BASE 0x403AE80ull
+#define DCORE0_TPC3_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC3_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_0_BASE 0x403B000ull
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC3_CFG_BASE 0x403B000ull
+#define DCORE0_TPC3_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC3_CFG_SECTION 0x5000
+#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_1_BASE 0x403B050ull
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_2_BASE 0x403B0A0ull
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_3_BASE 0x403B0F0ull
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_4_BASE 0x403B140ull
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_5_BASE 0x403B190ull
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_6_BASE 0x403B1E0ull
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_7_BASE 0x403B230ull
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_8_BASE 0x403B280ull
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_9_BASE 0x403B2D0ull
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_10_BASE 0x403B320ull
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_11_BASE 0x403B370ull
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_12_BASE 0x403B3C0ull
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_13_BASE 0x403B410ull
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_14_BASE 0x403B460ull
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_15_BASE 0x403B4B0ull
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE0_TPC3_CFG_KERNEL_SYNC_OBJECT_BASE 0x403B500ull
+#define DCORE0_TPC3_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE0_TPC3_CFG_KERNEL_BASE 0x403B508ull
+#define DCORE0_TPC3_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE0_TPC3_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE0_TPC3_CFG_QM_TENSOR_0_BASE 0x403B5DCull
+#define DCORE0_TPC3_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE0_TPC3_CFG_QM_TENSOR_1_BASE 0x403B62Cull
+#define DCORE0_TPC3_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE0_TPC3_CFG_QM_TENSOR_2_BASE 0x403B67Cull
+#define DCORE0_TPC3_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE0_TPC3_CFG_QM_TENSOR_3_BASE 0x403B6CCull
+#define DCORE0_TPC3_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE0_TPC3_CFG_QM_TENSOR_4_BASE 0x403B71Cull
+#define DCORE0_TPC3_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE0_TPC3_CFG_QM_TENSOR_5_BASE 0x403B76Cull
+#define DCORE0_TPC3_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE0_TPC3_CFG_QM_TENSOR_6_BASE 0x403B7BCull
+#define DCORE0_TPC3_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE0_TPC3_CFG_QM_TENSOR_7_BASE 0x403B80Cull
+#define DCORE0_TPC3_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE0_TPC3_CFG_QM_TENSOR_8_BASE 0x403B85Cull
+#define DCORE0_TPC3_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE0_TPC3_CFG_QM_TENSOR_9_BASE 0x403B8ACull
+#define DCORE0_TPC3_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE0_TPC3_CFG_QM_TENSOR_10_BASE 0x403B8FCull
+#define DCORE0_TPC3_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE0_TPC3_CFG_QM_TENSOR_11_BASE 0x403B94Cull
+#define DCORE0_TPC3_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE0_TPC3_CFG_QM_TENSOR_12_BASE 0x403B99Cull
+#define DCORE0_TPC3_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE0_TPC3_CFG_QM_TENSOR_13_BASE 0x403B9ECull
+#define DCORE0_TPC3_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE0_TPC3_CFG_QM_TENSOR_14_BASE 0x403BA3Cull
+#define DCORE0_TPC3_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE0_TPC3_CFG_QM_TENSOR_15_BASE 0x403BA8Cull
+#define DCORE0_TPC3_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE0_TPC3_CFG_QM_SYNC_OBJECT_BASE 0x403BADCull
+#define DCORE0_TPC3_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE0_TPC3_CFG_QM_BASE 0x403BAE4ull
+#define DCORE0_TPC3_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE0_TPC3_CFG_QM_SECTION 0x31C0
+#define mmDCORE0_TPC3_CFG_AXUSER_BASE 0x403BE00ull
+#define DCORE0_TPC3_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE0_TPC3_CFG_SPECIAL_BASE 0x403BE80ull
+#define DCORE0_TPC3_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC3_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC3_MSTR_IF_RR_SHRD_HBW_BASE 0x403C000ull
+#define DCORE0_TPC3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_TPC3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE0_TPC3_MSTR_IF_RR_PRVT_HBW_BASE 0x403C200ull
+#define DCORE0_TPC3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_TPC3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE0_TPC3_MSTR_IF_RR_SHRD_LBW_BASE 0x403C400ull
+#define DCORE0_TPC3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_TPC3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE0_TPC3_MSTR_IF_RR_PRVT_LBW_BASE 0x403C600ull
+#define DCORE0_TPC3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_TPC3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE0_TPC3_MSTR_IF_E2E_CRDT_BASE 0x403C800ull
+#define DCORE0_TPC3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_TPC3_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE0_TPC3_MSTR_IF_AXUSER_BASE 0x403CA80ull
+#define DCORE0_TPC3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC3_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE0_TPC3_MSTR_IF_DBG_HBW_BASE 0x403CB00ull
+#define DCORE0_TPC3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC3_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_TPC3_MSTR_IF_DBG_LBW_BASE 0x403CB80ull
+#define DCORE0_TPC3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC3_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE0_TPC3_MSTR_IF_CORE_HBW_BASE 0x403CC00ull
+#define DCORE0_TPC3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_TPC3_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE0_TPC3_MSTR_IF_CORE_LBW_BASE 0x403CD80ull
+#define DCORE0_TPC3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_TPC3_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE0_TPC3_MSTR_IF_SPECIAL_BASE 0x403CE80ull
+#define DCORE0_TPC3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC3_MSTR_IF_SPECIAL_SECTION 0x3180
+#define mmDCORE0_TPC4_QM_DCCM_BASE 0x4040000ull
+#define DCORE0_TPC4_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE0_TPC4_QM_DCCM_SECTION 0x8000
+#define mmDCORE0_TPC4_QM_ARC_AUX_BASE 0x4048000ull
+#define DCORE0_TPC4_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE0_TPC4_QM_ARC_AUX_SECTION 0xE800
+#define mmDCORE0_TPC4_QM_ARC_AUX_SPECIAL_BASE 0x4048E80ull
+#define DCORE0_TPC4_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC4_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define mmDCORE0_TPC4_QM_BASE 0x404A000ull
+#define DCORE0_TPC4_QM_MAX_OFFSET 0x1000
+#define DCORE0_TPC4_QM_SECTION 0x9000
+#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR0_BASE 0x404A900ull
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR1_BASE 0x404A908ull
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR2_BASE 0x404A910ull
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR3_BASE 0x404A918ull
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR4_BASE 0x404A920ull
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR5_BASE 0x404A928ull
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR6_BASE 0x404A930ull
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR7_BASE 0x404A938ull
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR8_BASE 0x404A940ull
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR9_BASE 0x404A948ull
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR10_BASE 0x404A950ull
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR11_BASE 0x404A958ull
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR12_BASE 0x404A960ull
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR13_BASE 0x404A968ull
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR14_BASE 0x404A970ull
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR15_BASE 0x404A978ull
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE0_TPC4_QM_AXUSER_SECURED_BASE 0x404AB00ull
+#define DCORE0_TPC4_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE0_TPC4_QM_AXUSER_NONSECURED_BASE 0x404AB80ull
+#define DCORE0_TPC4_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE0_TPC4_QM_DBG_HBW_BASE 0x404AC00ull
+#define DCORE0_TPC4_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC4_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_TPC4_QM_DBG_LBW_BASE 0x404AC80ull
+#define DCORE0_TPC4_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC4_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE0_TPC4_QM_CGM_BASE 0x404AD80ull
+#define DCORE0_TPC4_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE0_TPC4_QM_CGM_SECTION 0x1000
+#define mmDCORE0_TPC4_QM_SPECIAL_BASE 0x404AE80ull
+#define DCORE0_TPC4_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC4_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_0_BASE 0x404B000ull
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC4_CFG_BASE 0x404B000ull
+#define DCORE0_TPC4_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC4_CFG_SECTION 0x5000
+#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_1_BASE 0x404B050ull
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_2_BASE 0x404B0A0ull
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_3_BASE 0x404B0F0ull
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_4_BASE 0x404B140ull
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_5_BASE 0x404B190ull
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_6_BASE 0x404B1E0ull
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_7_BASE 0x404B230ull
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_8_BASE 0x404B280ull
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_9_BASE 0x404B2D0ull
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_10_BASE 0x404B320ull
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_11_BASE 0x404B370ull
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_12_BASE 0x404B3C0ull
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_13_BASE 0x404B410ull
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_14_BASE 0x404B460ull
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_15_BASE 0x404B4B0ull
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE0_TPC4_CFG_KERNEL_SYNC_OBJECT_BASE 0x404B500ull
+#define DCORE0_TPC4_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE0_TPC4_CFG_KERNEL_BASE 0x404B508ull
+#define DCORE0_TPC4_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE0_TPC4_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE0_TPC4_CFG_QM_TENSOR_0_BASE 0x404B5DCull
+#define DCORE0_TPC4_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE0_TPC4_CFG_QM_TENSOR_1_BASE 0x404B62Cull
+#define DCORE0_TPC4_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE0_TPC4_CFG_QM_TENSOR_2_BASE 0x404B67Cull
+#define DCORE0_TPC4_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE0_TPC4_CFG_QM_TENSOR_3_BASE 0x404B6CCull
+#define DCORE0_TPC4_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE0_TPC4_CFG_QM_TENSOR_4_BASE 0x404B71Cull
+#define DCORE0_TPC4_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE0_TPC4_CFG_QM_TENSOR_5_BASE 0x404B76Cull
+#define DCORE0_TPC4_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE0_TPC4_CFG_QM_TENSOR_6_BASE 0x404B7BCull
+#define DCORE0_TPC4_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE0_TPC4_CFG_QM_TENSOR_7_BASE 0x404B80Cull
+#define DCORE0_TPC4_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE0_TPC4_CFG_QM_TENSOR_8_BASE 0x404B85Cull
+#define DCORE0_TPC4_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE0_TPC4_CFG_QM_TENSOR_9_BASE 0x404B8ACull
+#define DCORE0_TPC4_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE0_TPC4_CFG_QM_TENSOR_10_BASE 0x404B8FCull
+#define DCORE0_TPC4_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE0_TPC4_CFG_QM_TENSOR_11_BASE 0x404B94Cull
+#define DCORE0_TPC4_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE0_TPC4_CFG_QM_TENSOR_12_BASE 0x404B99Cull
+#define DCORE0_TPC4_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE0_TPC4_CFG_QM_TENSOR_13_BASE 0x404B9ECull
+#define DCORE0_TPC4_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE0_TPC4_CFG_QM_TENSOR_14_BASE 0x404BA3Cull
+#define DCORE0_TPC4_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE0_TPC4_CFG_QM_TENSOR_15_BASE 0x404BA8Cull
+#define DCORE0_TPC4_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE0_TPC4_CFG_QM_SYNC_OBJECT_BASE 0x404BADCull
+#define DCORE0_TPC4_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE0_TPC4_CFG_QM_BASE 0x404BAE4ull
+#define DCORE0_TPC4_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE0_TPC4_CFG_QM_SECTION 0x31C0
+#define mmDCORE0_TPC4_CFG_AXUSER_BASE 0x404BE00ull
+#define DCORE0_TPC4_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE0_TPC4_CFG_SPECIAL_BASE 0x404BE80ull
+#define DCORE0_TPC4_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC4_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC4_MSTR_IF_RR_SHRD_HBW_BASE 0x404C000ull
+#define DCORE0_TPC4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_TPC4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE0_TPC4_MSTR_IF_RR_PRVT_HBW_BASE 0x404C200ull
+#define DCORE0_TPC4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_TPC4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE0_TPC4_MSTR_IF_RR_SHRD_LBW_BASE 0x404C400ull
+#define DCORE0_TPC4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_TPC4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE0_TPC4_MSTR_IF_RR_PRVT_LBW_BASE 0x404C600ull
+#define DCORE0_TPC4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_TPC4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE0_TPC4_MSTR_IF_E2E_CRDT_BASE 0x404C800ull
+#define DCORE0_TPC4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_TPC4_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE0_TPC4_MSTR_IF_AXUSER_BASE 0x404CA80ull
+#define DCORE0_TPC4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC4_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE0_TPC4_MSTR_IF_DBG_HBW_BASE 0x404CB00ull
+#define DCORE0_TPC4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC4_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_TPC4_MSTR_IF_DBG_LBW_BASE 0x404CB80ull
+#define DCORE0_TPC4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC4_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE0_TPC4_MSTR_IF_CORE_HBW_BASE 0x404CC00ull
+#define DCORE0_TPC4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_TPC4_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE0_TPC4_MSTR_IF_CORE_LBW_BASE 0x404CD80ull
+#define DCORE0_TPC4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_TPC4_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE0_TPC4_MSTR_IF_SPECIAL_BASE 0x404CE80ull
+#define DCORE0_TPC4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC4_MSTR_IF_SPECIAL_SECTION 0x3180
+#define mmDCORE0_TPC5_QM_DCCM_BASE 0x4050000ull
+#define DCORE0_TPC5_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE0_TPC5_QM_DCCM_SECTION 0x8000
+#define mmDCORE0_TPC5_QM_ARC_AUX_BASE 0x4058000ull
+#define DCORE0_TPC5_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE0_TPC5_QM_ARC_AUX_SECTION 0xE800
+#define mmDCORE0_TPC5_QM_ARC_AUX_SPECIAL_BASE 0x4058E80ull
+#define DCORE0_TPC5_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC5_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define mmDCORE0_TPC5_QM_BASE 0x405A000ull
+#define DCORE0_TPC5_QM_MAX_OFFSET 0x1000
+#define DCORE0_TPC5_QM_SECTION 0x9000
+#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR0_BASE 0x405A900ull
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR1_BASE 0x405A908ull
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR2_BASE 0x405A910ull
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR3_BASE 0x405A918ull
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR4_BASE 0x405A920ull
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR5_BASE 0x405A928ull
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR6_BASE 0x405A930ull
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR7_BASE 0x405A938ull
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR8_BASE 0x405A940ull
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR9_BASE 0x405A948ull
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR10_BASE 0x405A950ull
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR11_BASE 0x405A958ull
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR12_BASE 0x405A960ull
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR13_BASE 0x405A968ull
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR14_BASE 0x405A970ull
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR15_BASE 0x405A978ull
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE0_TPC5_QM_AXUSER_SECURED_BASE 0x405AB00ull
+#define DCORE0_TPC5_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE0_TPC5_QM_AXUSER_NONSECURED_BASE 0x405AB80ull
+#define DCORE0_TPC5_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE0_TPC5_QM_DBG_HBW_BASE 0x405AC00ull
+#define DCORE0_TPC5_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC5_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_TPC5_QM_DBG_LBW_BASE 0x405AC80ull
+#define DCORE0_TPC5_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC5_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE0_TPC5_QM_CGM_BASE 0x405AD80ull
+#define DCORE0_TPC5_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE0_TPC5_QM_CGM_SECTION 0x1000
+#define mmDCORE0_TPC5_QM_SPECIAL_BASE 0x405AE80ull
+#define DCORE0_TPC5_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC5_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_0_BASE 0x405B000ull
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC5_CFG_BASE 0x405B000ull
+#define DCORE0_TPC5_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC5_CFG_SECTION 0x5000
+#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_1_BASE 0x405B050ull
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_2_BASE 0x405B0A0ull
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_3_BASE 0x405B0F0ull
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_4_BASE 0x405B140ull
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_5_BASE 0x405B190ull
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_6_BASE 0x405B1E0ull
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_7_BASE 0x405B230ull
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_8_BASE 0x405B280ull
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_9_BASE 0x405B2D0ull
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_10_BASE 0x405B320ull
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_11_BASE 0x405B370ull
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_12_BASE 0x405B3C0ull
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_13_BASE 0x405B410ull
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_14_BASE 0x405B460ull
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_15_BASE 0x405B4B0ull
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE0_TPC5_CFG_KERNEL_SYNC_OBJECT_BASE 0x405B500ull
+#define DCORE0_TPC5_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE0_TPC5_CFG_KERNEL_BASE 0x405B508ull
+#define DCORE0_TPC5_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE0_TPC5_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE0_TPC5_CFG_QM_TENSOR_0_BASE 0x405B5DCull
+#define DCORE0_TPC5_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE0_TPC5_CFG_QM_TENSOR_1_BASE 0x405B62Cull
+#define DCORE0_TPC5_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE0_TPC5_CFG_QM_TENSOR_2_BASE 0x405B67Cull
+#define DCORE0_TPC5_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE0_TPC5_CFG_QM_TENSOR_3_BASE 0x405B6CCull
+#define DCORE0_TPC5_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE0_TPC5_CFG_QM_TENSOR_4_BASE 0x405B71Cull
+#define DCORE0_TPC5_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE0_TPC5_CFG_QM_TENSOR_5_BASE 0x405B76Cull
+#define DCORE0_TPC5_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE0_TPC5_CFG_QM_TENSOR_6_BASE 0x405B7BCull
+#define DCORE0_TPC5_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE0_TPC5_CFG_QM_TENSOR_7_BASE 0x405B80Cull
+#define DCORE0_TPC5_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE0_TPC5_CFG_QM_TENSOR_8_BASE 0x405B85Cull
+#define DCORE0_TPC5_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE0_TPC5_CFG_QM_TENSOR_9_BASE 0x405B8ACull
+#define DCORE0_TPC5_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE0_TPC5_CFG_QM_TENSOR_10_BASE 0x405B8FCull
+#define DCORE0_TPC5_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE0_TPC5_CFG_QM_TENSOR_11_BASE 0x405B94Cull
+#define DCORE0_TPC5_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE0_TPC5_CFG_QM_TENSOR_12_BASE 0x405B99Cull
+#define DCORE0_TPC5_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE0_TPC5_CFG_QM_TENSOR_13_BASE 0x405B9ECull
+#define DCORE0_TPC5_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE0_TPC5_CFG_QM_TENSOR_14_BASE 0x405BA3Cull
+#define DCORE0_TPC5_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE0_TPC5_CFG_QM_TENSOR_15_BASE 0x405BA8Cull
+#define DCORE0_TPC5_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE0_TPC5_CFG_QM_SYNC_OBJECT_BASE 0x405BADCull
+#define DCORE0_TPC5_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE0_TPC5_CFG_QM_BASE 0x405BAE4ull
+#define DCORE0_TPC5_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE0_TPC5_CFG_QM_SECTION 0x31C0
+#define mmDCORE0_TPC5_CFG_AXUSER_BASE 0x405BE00ull
+#define DCORE0_TPC5_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE0_TPC5_CFG_SPECIAL_BASE 0x405BE80ull
+#define DCORE0_TPC5_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC5_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC5_MSTR_IF_RR_SHRD_HBW_BASE 0x405C000ull
+#define DCORE0_TPC5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_TPC5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE0_TPC5_MSTR_IF_RR_PRVT_HBW_BASE 0x405C200ull
+#define DCORE0_TPC5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_TPC5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE0_TPC5_MSTR_IF_RR_SHRD_LBW_BASE 0x405C400ull
+#define DCORE0_TPC5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_TPC5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE0_TPC5_MSTR_IF_RR_PRVT_LBW_BASE 0x405C600ull
+#define DCORE0_TPC5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_TPC5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE0_TPC5_MSTR_IF_E2E_CRDT_BASE 0x405C800ull
+#define DCORE0_TPC5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_TPC5_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE0_TPC5_MSTR_IF_AXUSER_BASE 0x405CA80ull
+#define DCORE0_TPC5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC5_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE0_TPC5_MSTR_IF_DBG_HBW_BASE 0x405CB00ull
+#define DCORE0_TPC5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC5_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_TPC5_MSTR_IF_DBG_LBW_BASE 0x405CB80ull
+#define DCORE0_TPC5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC5_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE0_TPC5_MSTR_IF_CORE_HBW_BASE 0x405CC00ull
+#define DCORE0_TPC5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_TPC5_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE0_TPC5_MSTR_IF_CORE_LBW_BASE 0x405CD80ull
+#define DCORE0_TPC5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_TPC5_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE0_TPC5_MSTR_IF_SPECIAL_BASE 0x405CE80ull
+#define DCORE0_TPC5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC5_MSTR_IF_SPECIAL_SECTION 0x3180
+#define mmDCORE0_TPC6_QM_DCCM_BASE 0x4060000ull
+#define DCORE0_TPC6_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE0_TPC6_QM_DCCM_SECTION 0x8000
+#define mmDCORE0_TPC6_QM_ARC_AUX_BASE 0x4068000ull
+#define DCORE0_TPC6_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE0_TPC6_QM_ARC_AUX_SECTION 0xE800
+#define mmDCORE0_TPC6_QM_ARC_AUX_SPECIAL_BASE 0x4068E80ull
+#define DCORE0_TPC6_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC6_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define mmDCORE0_TPC6_QM_BASE 0x406A000ull
+#define DCORE0_TPC6_QM_MAX_OFFSET 0x1000
+#define DCORE0_TPC6_QM_SECTION 0x9000
+#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR0_BASE 0x406A900ull
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR1_BASE 0x406A908ull
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR2_BASE 0x406A910ull
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR3_BASE 0x406A918ull
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR4_BASE 0x406A920ull
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR5_BASE 0x406A928ull
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR6_BASE 0x406A930ull
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR7_BASE 0x406A938ull
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR8_BASE 0x406A940ull
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR9_BASE 0x406A948ull
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR10_BASE 0x406A950ull
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR11_BASE 0x406A958ull
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR12_BASE 0x406A960ull
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR13_BASE 0x406A968ull
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR14_BASE 0x406A970ull
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR15_BASE 0x406A978ull
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE0_TPC6_QM_AXUSER_SECURED_BASE 0x406AB00ull
+#define DCORE0_TPC6_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE0_TPC6_QM_AXUSER_NONSECURED_BASE 0x406AB80ull
+#define DCORE0_TPC6_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE0_TPC6_QM_DBG_HBW_BASE 0x406AC00ull
+#define DCORE0_TPC6_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC6_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_TPC6_QM_DBG_LBW_BASE 0x406AC80ull
+#define DCORE0_TPC6_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC6_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE0_TPC6_QM_CGM_BASE 0x406AD80ull
+#define DCORE0_TPC6_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE0_TPC6_QM_CGM_SECTION 0x1000
+#define mmDCORE0_TPC6_QM_SPECIAL_BASE 0x406AE80ull
+#define DCORE0_TPC6_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC6_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_0_BASE 0x406B000ull
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC6_CFG_BASE 0x406B000ull
+#define DCORE0_TPC6_CFG_MAX_OFFSET 0x1000
+#define DCORE0_TPC6_CFG_SECTION 0x5000
+#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_1_BASE 0x406B050ull
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_2_BASE 0x406B0A0ull
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_3_BASE 0x406B0F0ull
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_4_BASE 0x406B140ull
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_5_BASE 0x406B190ull
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_6_BASE 0x406B1E0ull
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_7_BASE 0x406B230ull
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_8_BASE 0x406B280ull
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_9_BASE 0x406B2D0ull
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_10_BASE 0x406B320ull
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_11_BASE 0x406B370ull
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_12_BASE 0x406B3C0ull
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_13_BASE 0x406B410ull
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_14_BASE 0x406B460ull
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_15_BASE 0x406B4B0ull
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE0_TPC6_CFG_KERNEL_SYNC_OBJECT_BASE 0x406B500ull
+#define DCORE0_TPC6_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE0_TPC6_CFG_KERNEL_BASE 0x406B508ull
+#define DCORE0_TPC6_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE0_TPC6_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE0_TPC6_CFG_QM_TENSOR_0_BASE 0x406B5DCull
+#define DCORE0_TPC6_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE0_TPC6_CFG_QM_TENSOR_1_BASE 0x406B62Cull
+#define DCORE0_TPC6_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE0_TPC6_CFG_QM_TENSOR_2_BASE 0x406B67Cull
+#define DCORE0_TPC6_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE0_TPC6_CFG_QM_TENSOR_3_BASE 0x406B6CCull
+#define DCORE0_TPC6_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE0_TPC6_CFG_QM_TENSOR_4_BASE 0x406B71Cull
+#define DCORE0_TPC6_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE0_TPC6_CFG_QM_TENSOR_5_BASE 0x406B76Cull
+#define DCORE0_TPC6_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE0_TPC6_CFG_QM_TENSOR_6_BASE 0x406B7BCull
+#define DCORE0_TPC6_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE0_TPC6_CFG_QM_TENSOR_7_BASE 0x406B80Cull
+#define DCORE0_TPC6_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE0_TPC6_CFG_QM_TENSOR_8_BASE 0x406B85Cull
+#define DCORE0_TPC6_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE0_TPC6_CFG_QM_TENSOR_9_BASE 0x406B8ACull
+#define DCORE0_TPC6_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE0_TPC6_CFG_QM_TENSOR_10_BASE 0x406B8FCull
+#define DCORE0_TPC6_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE0_TPC6_CFG_QM_TENSOR_11_BASE 0x406B94Cull
+#define DCORE0_TPC6_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE0_TPC6_CFG_QM_TENSOR_12_BASE 0x406B99Cull
+#define DCORE0_TPC6_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE0_TPC6_CFG_QM_TENSOR_13_BASE 0x406B9ECull
+#define DCORE0_TPC6_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE0_TPC6_CFG_QM_TENSOR_14_BASE 0x406BA3Cull
+#define DCORE0_TPC6_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE0_TPC6_CFG_QM_TENSOR_15_BASE 0x406BA8Cull
+#define DCORE0_TPC6_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE0_TPC6_CFG_QM_SYNC_OBJECT_BASE 0x406BADCull
+#define DCORE0_TPC6_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE0_TPC6_CFG_QM_BASE 0x406BAE4ull
+#define DCORE0_TPC6_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE0_TPC6_CFG_QM_SECTION 0x31C0
+#define mmDCORE0_TPC6_CFG_AXUSER_BASE 0x406BE00ull
+#define DCORE0_TPC6_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE0_TPC6_CFG_SPECIAL_BASE 0x406BE80ull
+#define DCORE0_TPC6_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC6_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC6_MSTR_IF_RR_SHRD_HBW_BASE 0x406C000ull
+#define DCORE0_TPC6_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_TPC6_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE0_TPC6_MSTR_IF_RR_PRVT_HBW_BASE 0x406C200ull
+#define DCORE0_TPC6_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_TPC6_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE0_TPC6_MSTR_IF_RR_SHRD_LBW_BASE 0x406C400ull
+#define DCORE0_TPC6_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_TPC6_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE0_TPC6_MSTR_IF_RR_PRVT_LBW_BASE 0x406C600ull
+#define DCORE0_TPC6_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_TPC6_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE0_TPC6_MSTR_IF_E2E_CRDT_BASE 0x406C800ull
+#define DCORE0_TPC6_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_TPC6_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE0_TPC6_MSTR_IF_AXUSER_BASE 0x406CA80ull
+#define DCORE0_TPC6_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_TPC6_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE0_TPC6_MSTR_IF_DBG_HBW_BASE 0x406CB00ull
+#define DCORE0_TPC6_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC6_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_TPC6_MSTR_IF_DBG_LBW_BASE 0x406CB80ull
+#define DCORE0_TPC6_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_TPC6_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE0_TPC6_MSTR_IF_CORE_HBW_BASE 0x406CC00ull
+#define DCORE0_TPC6_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_TPC6_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE0_TPC6_MSTR_IF_CORE_LBW_BASE 0x406CD80ull
+#define DCORE0_TPC6_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_TPC6_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE0_TPC6_MSTR_IF_SPECIAL_BASE 0x406CE80ull
+#define DCORE0_TPC6_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC6_MSTR_IF_SPECIAL_SECTION 0x13180
+#define mmDCORE0_HMMU0_MMU_BASE 0x4080000ull
+#define DCORE0_HMMU0_MMU_MAX_OFFSET 0x1000
+#define DCORE0_HMMU0_MMU_SECTION 0xE800
+#define mmDCORE0_HMMU0_MMU_SPECIAL_BASE 0x4080E80ull
+#define DCORE0_HMMU0_MMU_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HMMU0_MMU_SPECIAL_SECTION 0x1800
+#define mmDCORE0_HMMU0_STLB_BASE 0x4081000ull
+#define DCORE0_HMMU0_STLB_MAX_OFFSET 0x1000
+#define DCORE0_HMMU0_STLB_SECTION 0xE800
+#define mmDCORE0_HMMU0_STLB_SPECIAL_BASE 0x4081E80ull
+#define DCORE0_HMMU0_STLB_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HMMU0_STLB_SPECIAL_SECTION 0x1180
+#define mmDCORE0_HMMU0_SCRAMB_OUT_BASE 0x4083000ull
+#define DCORE0_HMMU0_SCRAMB_OUT_MAX_OFFSET 0x1000
+#define DCORE0_HMMU0_SCRAMB_OUT_SECTION 0xE800
+#define mmDCORE0_HMMU0_SCRAMB_OUT_SPECIAL_BASE 0x4083E80ull
+#define DCORE0_HMMU0_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HMMU0_SCRAMB_OUT_SPECIAL_SECTION 0x1800
+#define mmDCORE0_HMMU0_MSTR_IF_RR_SHRD_HBW_BASE 0x4084000ull
+#define DCORE0_HMMU0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_HMMU0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE0_HMMU0_MSTR_IF_RR_PRVT_HBW_BASE 0x4084200ull
+#define DCORE0_HMMU0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_HMMU0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE0_HMMU0_MSTR_IF_RR_SHRD_LBW_BASE 0x4084400ull
+#define DCORE0_HMMU0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_HMMU0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE0_HMMU0_MSTR_IF_RR_PRVT_LBW_BASE 0x4084600ull
+#define DCORE0_HMMU0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_HMMU0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE0_HMMU0_MSTR_IF_E2E_CRDT_BASE 0x4084800ull
+#define DCORE0_HMMU0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_HMMU0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE0_HMMU0_MSTR_IF_AXUSER_BASE 0x4084A80ull
+#define DCORE0_HMMU0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_HMMU0_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE0_HMMU0_MSTR_IF_DBG_HBW_BASE 0x4084B00ull
+#define DCORE0_HMMU0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_HMMU0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_HMMU0_MSTR_IF_DBG_LBW_BASE 0x4084B80ull
+#define DCORE0_HMMU0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_HMMU0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE0_HMMU0_MSTR_IF_CORE_HBW_BASE 0x4084C00ull
+#define DCORE0_HMMU0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_HMMU0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE0_HMMU0_MSTR_IF_CORE_LBW_BASE 0x4084D80ull
+#define DCORE0_HMMU0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_HMMU0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE0_HMMU0_MSTR_IF_SPECIAL_BASE 0x4084E80ull
+#define DCORE0_HMMU0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HMMU0_MSTR_IF_SPECIAL_SECTION 0xB180
+#define mmDCORE0_HMMU1_MMU_BASE 0x4090000ull
+#define DCORE0_HMMU1_MMU_MAX_OFFSET 0x1000
+#define DCORE0_HMMU1_MMU_SECTION 0xE800
+#define mmDCORE0_HMMU1_MMU_SPECIAL_BASE 0x4090E80ull
+#define DCORE0_HMMU1_MMU_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HMMU1_MMU_SPECIAL_SECTION 0x1800
+#define mmDCORE0_HMMU1_STLB_BASE 0x4091000ull
+#define DCORE0_HMMU1_STLB_MAX_OFFSET 0x1000
+#define DCORE0_HMMU1_STLB_SECTION 0xE800
+#define mmDCORE0_HMMU1_STLB_SPECIAL_BASE 0x4091E80ull
+#define DCORE0_HMMU1_STLB_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HMMU1_STLB_SPECIAL_SECTION 0x1180
+#define mmDCORE0_HMMU1_SCRAMB_OUT_BASE 0x4093000ull
+#define DCORE0_HMMU1_SCRAMB_OUT_MAX_OFFSET 0x1000
+#define DCORE0_HMMU1_SCRAMB_OUT_SECTION 0xE800
+#define mmDCORE0_HMMU1_SCRAMB_OUT_SPECIAL_BASE 0x4093E80ull
+#define DCORE0_HMMU1_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HMMU1_SCRAMB_OUT_SPECIAL_SECTION 0x1800
+#define mmDCORE0_HMMU1_MSTR_IF_RR_SHRD_HBW_BASE 0x4094000ull
+#define DCORE0_HMMU1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_HMMU1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE0_HMMU1_MSTR_IF_RR_PRVT_HBW_BASE 0x4094200ull
+#define DCORE0_HMMU1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_HMMU1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE0_HMMU1_MSTR_IF_RR_SHRD_LBW_BASE 0x4094400ull
+#define DCORE0_HMMU1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_HMMU1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE0_HMMU1_MSTR_IF_RR_PRVT_LBW_BASE 0x4094600ull
+#define DCORE0_HMMU1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_HMMU1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE0_HMMU1_MSTR_IF_E2E_CRDT_BASE 0x4094800ull
+#define DCORE0_HMMU1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_HMMU1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE0_HMMU1_MSTR_IF_AXUSER_BASE 0x4094A80ull
+#define DCORE0_HMMU1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_HMMU1_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE0_HMMU1_MSTR_IF_DBG_HBW_BASE 0x4094B00ull
+#define DCORE0_HMMU1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_HMMU1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_HMMU1_MSTR_IF_DBG_LBW_BASE 0x4094B80ull
+#define DCORE0_HMMU1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_HMMU1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE0_HMMU1_MSTR_IF_CORE_HBW_BASE 0x4094C00ull
+#define DCORE0_HMMU1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_HMMU1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE0_HMMU1_MSTR_IF_CORE_LBW_BASE 0x4094D80ull
+#define DCORE0_HMMU1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_HMMU1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE0_HMMU1_MSTR_IF_SPECIAL_BASE 0x4094E80ull
+#define DCORE0_HMMU1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HMMU1_MSTR_IF_SPECIAL_SECTION 0xB180
+#define mmDCORE0_HMMU2_MMU_BASE 0x40A0000ull
+#define DCORE0_HMMU2_MMU_MAX_OFFSET 0x1000
+#define DCORE0_HMMU2_MMU_SECTION 0xE800
+#define mmDCORE0_HMMU2_MMU_SPECIAL_BASE 0x40A0E80ull
+#define DCORE0_HMMU2_MMU_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HMMU2_MMU_SPECIAL_SECTION 0x1800
+#define mmDCORE0_HMMU2_STLB_BASE 0x40A1000ull
+#define DCORE0_HMMU2_STLB_MAX_OFFSET 0x1000
+#define DCORE0_HMMU2_STLB_SECTION 0xE800
+#define mmDCORE0_HMMU2_STLB_SPECIAL_BASE 0x40A1E80ull
+#define DCORE0_HMMU2_STLB_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HMMU2_STLB_SPECIAL_SECTION 0x1180
+#define mmDCORE0_HMMU2_SCRAMB_OUT_BASE 0x40A3000ull
+#define DCORE0_HMMU2_SCRAMB_OUT_MAX_OFFSET 0x1000
+#define DCORE0_HMMU2_SCRAMB_OUT_SECTION 0xE800
+#define mmDCORE0_HMMU2_SCRAMB_OUT_SPECIAL_BASE 0x40A3E80ull
+#define DCORE0_HMMU2_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HMMU2_SCRAMB_OUT_SPECIAL_SECTION 0x1800
+#define mmDCORE0_HMMU2_MSTR_IF_RR_SHRD_HBW_BASE 0x40A4000ull
+#define DCORE0_HMMU2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_HMMU2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE0_HMMU2_MSTR_IF_RR_PRVT_HBW_BASE 0x40A4200ull
+#define DCORE0_HMMU2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_HMMU2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE0_HMMU2_MSTR_IF_RR_SHRD_LBW_BASE 0x40A4400ull
+#define DCORE0_HMMU2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_HMMU2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE0_HMMU2_MSTR_IF_RR_PRVT_LBW_BASE 0x40A4600ull
+#define DCORE0_HMMU2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_HMMU2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE0_HMMU2_MSTR_IF_E2E_CRDT_BASE 0x40A4800ull
+#define DCORE0_HMMU2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_HMMU2_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE0_HMMU2_MSTR_IF_AXUSER_BASE 0x40A4A80ull
+#define DCORE0_HMMU2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_HMMU2_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE0_HMMU2_MSTR_IF_DBG_HBW_BASE 0x40A4B00ull
+#define DCORE0_HMMU2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_HMMU2_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_HMMU2_MSTR_IF_DBG_LBW_BASE 0x40A4B80ull
+#define DCORE0_HMMU2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_HMMU2_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE0_HMMU2_MSTR_IF_CORE_HBW_BASE 0x40A4C00ull
+#define DCORE0_HMMU2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_HMMU2_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE0_HMMU2_MSTR_IF_CORE_LBW_BASE 0x40A4D80ull
+#define DCORE0_HMMU2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_HMMU2_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE0_HMMU2_MSTR_IF_SPECIAL_BASE 0x40A4E80ull
+#define DCORE0_HMMU2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HMMU2_MSTR_IF_SPECIAL_SECTION 0xB180
+#define mmDCORE0_HMMU3_MMU_BASE 0x40B0000ull
+#define DCORE0_HMMU3_MMU_MAX_OFFSET 0x1000
+#define DCORE0_HMMU3_MMU_SECTION 0xE800
+#define mmDCORE0_HMMU3_MMU_SPECIAL_BASE 0x40B0E80ull
+#define DCORE0_HMMU3_MMU_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HMMU3_MMU_SPECIAL_SECTION 0x1800
+#define mmDCORE0_HMMU3_STLB_BASE 0x40B1000ull
+#define DCORE0_HMMU3_STLB_MAX_OFFSET 0x1000
+#define DCORE0_HMMU3_STLB_SECTION 0xE800
+#define mmDCORE0_HMMU3_STLB_SPECIAL_BASE 0x40B1E80ull
+#define DCORE0_HMMU3_STLB_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HMMU3_STLB_SPECIAL_SECTION 0x1180
+#define mmDCORE0_HMMU3_SCRAMB_OUT_BASE 0x40B3000ull
+#define DCORE0_HMMU3_SCRAMB_OUT_MAX_OFFSET 0x1000
+#define DCORE0_HMMU3_SCRAMB_OUT_SECTION 0xE800
+#define mmDCORE0_HMMU3_SCRAMB_OUT_SPECIAL_BASE 0x40B3E80ull
+#define DCORE0_HMMU3_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HMMU3_SCRAMB_OUT_SPECIAL_SECTION 0x1800
+#define mmDCORE0_HMMU3_MSTR_IF_RR_SHRD_HBW_BASE 0x40B4000ull
+#define DCORE0_HMMU3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_HMMU3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE0_HMMU3_MSTR_IF_RR_PRVT_HBW_BASE 0x40B4200ull
+#define DCORE0_HMMU3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_HMMU3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE0_HMMU3_MSTR_IF_RR_SHRD_LBW_BASE 0x40B4400ull
+#define DCORE0_HMMU3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_HMMU3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE0_HMMU3_MSTR_IF_RR_PRVT_LBW_BASE 0x40B4600ull
+#define DCORE0_HMMU3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_HMMU3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE0_HMMU3_MSTR_IF_E2E_CRDT_BASE 0x40B4800ull
+#define DCORE0_HMMU3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_HMMU3_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE0_HMMU3_MSTR_IF_AXUSER_BASE 0x40B4A80ull
+#define DCORE0_HMMU3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_HMMU3_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE0_HMMU3_MSTR_IF_DBG_HBW_BASE 0x40B4B00ull
+#define DCORE0_HMMU3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_HMMU3_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_HMMU3_MSTR_IF_DBG_LBW_BASE 0x40B4B80ull
+#define DCORE0_HMMU3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_HMMU3_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE0_HMMU3_MSTR_IF_CORE_HBW_BASE 0x40B4C00ull
+#define DCORE0_HMMU3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_HMMU3_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE0_HMMU3_MSTR_IF_CORE_LBW_BASE 0x40B4D80ull
+#define DCORE0_HMMU3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_HMMU3_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE0_HMMU3_MSTR_IF_SPECIAL_BASE 0x40B4E80ull
+#define DCORE0_HMMU3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HMMU3_MSTR_IF_SPECIAL_SECTION 0xB180
+#define mmDCORE0_MME_QM_ARC_DCCM_BASE 0x40C0000ull
+#define DCORE0_MME_QM_ARC_DCCM_MAX_OFFSET 0x4000
+#define DCORE0_MME_QM_ARC_DCCM_SECTION 0x8000
+#define mmDCORE0_MME_QM_ARC_AUX_BASE 0x40C8000ull
+#define DCORE0_MME_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE0_MME_QM_ARC_AUX_SECTION 0xE800
+#define mmDCORE0_MME_QM_ARC_AUX_SPECIAL_BASE 0x40C8E80ull
+#define DCORE0_MME_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_QM_ARC_AUX_SPECIAL_SECTION 0x1800
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_BASE 0x40C9000ull
+#define DCORE0_MME_QM_ARC_DUP_ENG_MAX_OFFSET 0x1000
+#define DCORE0_MME_QM_ARC_DUP_ENG_SECTION 0x9000
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_BASE 0x40C9900ull
+#define DCORE0_MME_QM_ARC_DUP_ENG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_MME_QM_ARC_DUP_ENG_AXUSER_SECTION 0x5800
+#define mmDCORE0_MME_QM_ARC_DUP_ENG_SPECIAL_BASE 0x40C9E80ull
+#define DCORE0_MME_QM_ARC_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_QM_ARC_DUP_ENG_SPECIAL_SECTION 0x1800
+#define mmDCORE0_MME_QM_BASE 0x40CA000ull
+#define DCORE0_MME_QM_MAX_OFFSET 0x1000
+#define DCORE0_MME_QM_SECTION 0x9000
+#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR0_BASE 0x40CA900ull
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR1_BASE 0x40CA908ull
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR2_BASE 0x40CA910ull
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR3_BASE 0x40CA918ull
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR4_BASE 0x40CA920ull
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR5_BASE 0x40CA928ull
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR6_BASE 0x40CA930ull
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR7_BASE 0x40CA938ull
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR8_BASE 0x40CA940ull
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR9_BASE 0x40CA948ull
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR10_BASE 0x40CA950ull
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR11_BASE 0x40CA958ull
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR12_BASE 0x40CA960ull
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR13_BASE 0x40CA968ull
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR14_BASE 0x40CA970ull
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR15_BASE 0x40CA978ull
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE0_MME_QM_AXUSER_SECURED_BASE 0x40CAB00ull
+#define DCORE0_MME_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE0_MME_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE0_MME_QM_AXUSER_NONSECURED_BASE 0x40CAB80ull
+#define DCORE0_MME_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE0_MME_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE0_MME_QM_DBG_HBW_BASE 0x40CAC00ull
+#define DCORE0_MME_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_MME_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_MME_QM_DBG_LBW_BASE 0x40CAC80ull
+#define DCORE0_MME_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_MME_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE0_MME_QM_CGM_BASE 0x40CAD80ull
+#define DCORE0_MME_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE0_MME_QM_CGM_SECTION 0x1000
+#define mmDCORE0_MME_QM_SPECIAL_BASE 0x40CAE80ull
+#define DCORE0_MME_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE0_MME_CTRL_LO_BASE 0x40CB000ull
+#define DCORE0_MME_CTRL_LO_MAX_OFFSET 0x1000
+#define DCORE0_MME_CTRL_LO_SECTION 0x8000
+#define mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_BASE 0x40CB008ull
+#define DCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_MAX_OFFSET 0x2000
+#define DCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_SECTION 0x2000
+#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BASE 0x40CB028ull
+#define DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_MAX_OFFSET 0x1800
+#define DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_SECTION 0x1800
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_BASE 0x40CB040ull
+#define DCORE0_MME_CTRL_LO_ARCH_TENSOR_A_MAX_OFFSET 0x5800
+#define DCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SECTION 0x5800
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_BASE 0x40CB098ull
+#define DCORE0_MME_CTRL_LO_ARCH_TENSOR_B_MAX_OFFSET 0x5800
+#define DCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SECTION 0x5800
+#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_BASE 0x40CB0F0ull
+#define DCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_MAX_OFFSET 0x5800
+#define DCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SECTION 0x6C00
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_BASE 0x40CB15Cull
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_BASE 0x40CB170ull
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_BASE 0x40CB184ull
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_BASE 0x40CB198ull
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_BASE 0x40CB1ACull
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_BASE 0x40CB1C0ull
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_BASE 0x40CB1D4ull
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_BASE 0x40CB1E8ull
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_BASE 0x40CB1FCull
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_BASE 0x40CB210ull
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_SECTION 0x1C00
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_BASE 0x40CB22Cull
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_BASE 0x40CB240ull
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_BASE 0x40CB254ull
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_BASE 0x40CB268ull
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_SECTION 0x1800
+#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_BASE 0x40CB280ull
+#define DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_MAX_OFFSET 0x6000
+#define DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SECTION 0xB800
+#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_BASE 0x40CBE00ull
+#define DCORE0_MME_CTRL_LO_MME_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_MME_CTRL_LO_MME_AXUSER_SECTION 0x8000
+#define mmDCORE0_MME_CTRL_LO_SPECIAL_BASE 0x40CBE80ull
+#define DCORE0_MME_CTRL_LO_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_CTRL_LO_SPECIAL_SECTION 0x1800
+#define mmDCORE0_MME_CTRL_HI_BASE 0x40CC000ull
+#define DCORE0_MME_CTRL_HI_MAX_OFFSET 0x1000
+#define DCORE0_MME_CTRL_HI_SECTION 0x8000
+#define mmDCORE0_MME_CTRL_HI_SHADOW_0_BASE_ADDR_BASE 0x40CC008ull
+#define DCORE0_MME_CTRL_HI_SHADOW_0_BASE_ADDR_MAX_OFFSET 0x2000
+#define DCORE0_MME_CTRL_HI_SHADOW_0_BASE_ADDR_SECTION 0x2000
+#define mmDCORE0_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_BASE 0x40CC028ull
+#define DCORE0_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_MAX_OFFSET 0x1800
+#define DCORE0_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_SECTION 0x1800
+#define mmDCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_A_BASE 0x40CC040ull
+#define DCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_A_MAX_OFFSET 0x5800
+#define DCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_A_SECTION 0x5800
+#define mmDCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_B_BASE 0x40CC098ull
+#define DCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_B_MAX_OFFSET 0x5800
+#define DCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_B_SECTION 0x5800
+#define mmDCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_BASE 0x40CC0F0ull
+#define DCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_MAX_OFFSET 0x5800
+#define DCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_SECTION 0x6C00
+#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_BASE 0x40CC15Cull
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_BASE 0x40CC170ull
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_BASE 0x40CC184ull
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_BASE 0x40CC198ull
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_BASE 0x40CC1ACull
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_BASE 0x40CC1C0ull
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_BASE 0x40CC1D4ull
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_BASE 0x40CC1E8ull
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_BASE 0x40CC1FCull
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_BASE 0x40CC210ull
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_SECTION 0x1C00
+#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_BASE 0x40CC22Cull
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_BASE 0x40CC240ull
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_BASE 0x40CC254ull
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_BASE 0x40CC268ull
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_SECTION 0x1800
+#define mmDCORE0_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_BASE 0x40CC280ull
+#define DCORE0_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_MAX_OFFSET 0x6000
+#define DCORE0_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_SECTION 0x8800
+#define mmDCORE0_MME_CTRL_HI_SHADOW_1_BASE_ADDR_BASE 0x40CC308ull
+#define DCORE0_MME_CTRL_HI_SHADOW_1_BASE_ADDR_MAX_OFFSET 0x2000
+#define DCORE0_MME_CTRL_HI_SHADOW_1_BASE_ADDR_SECTION 0x2000
+#define mmDCORE0_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_BASE 0x40CC328ull
+#define DCORE0_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_MAX_OFFSET 0x1800
+#define DCORE0_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_SECTION 0x1800
+#define mmDCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_A_BASE 0x40CC340ull
+#define DCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_A_MAX_OFFSET 0x5800
+#define DCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_A_SECTION 0x5800
+#define mmDCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_B_BASE 0x40CC398ull
+#define DCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_B_MAX_OFFSET 0x5800
+#define DCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_B_SECTION 0x5800
+#define mmDCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_BASE 0x40CC3F0ull
+#define DCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_MAX_OFFSET 0x5800
+#define DCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_SECTION 0x6C00
+#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_BASE 0x40CC45Cull
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_BASE 0x40CC470ull
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_BASE 0x40CC484ull
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_BASE 0x40CC498ull
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_BASE 0x40CC4ACull
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_BASE 0x40CC4C0ull
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_BASE 0x40CC4D4ull
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_BASE 0x40CC4E8ull
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_BASE 0x40CC4FCull
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_BASE 0x40CC510ull
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_SECTION 0x1C00
+#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_BASE 0x40CC52Cull
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_BASE 0x40CC540ull
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_BASE 0x40CC554ull
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_BASE 0x40CC568ull
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_SECTION 0x1800
+#define mmDCORE0_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_BASE 0x40CC580ull
+#define DCORE0_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_MAX_OFFSET 0x6000
+#define DCORE0_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_SECTION 0x8800
+#define mmDCORE0_MME_CTRL_HI_SHADOW_2_BASE_ADDR_BASE 0x40CC608ull
+#define DCORE0_MME_CTRL_HI_SHADOW_2_BASE_ADDR_MAX_OFFSET 0x2000
+#define DCORE0_MME_CTRL_HI_SHADOW_2_BASE_ADDR_SECTION 0x2000
+#define mmDCORE0_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_BASE 0x40CC628ull
+#define DCORE0_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_MAX_OFFSET 0x1800
+#define DCORE0_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_SECTION 0x1800
+#define mmDCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_A_BASE 0x40CC640ull
+#define DCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_A_MAX_OFFSET 0x5800
+#define DCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_A_SECTION 0x5800
+#define mmDCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_B_BASE 0x40CC698ull
+#define DCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_B_MAX_OFFSET 0x5800
+#define DCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_B_SECTION 0x5800
+#define mmDCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_BASE 0x40CC6F0ull
+#define DCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_MAX_OFFSET 0x5800
+#define DCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_SECTION 0x6C00
+#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_BASE 0x40CC75Cull
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_BASE 0x40CC770ull
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_BASE 0x40CC784ull
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_BASE 0x40CC798ull
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_BASE 0x40CC7ACull
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_BASE 0x40CC7C0ull
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_BASE 0x40CC7D4ull
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_BASE 0x40CC7E8ull
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_BASE 0x40CC7FCull
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_BASE 0x40CC810ull
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_SECTION 0x1C00
+#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_BASE 0x40CC82Cull
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_BASE 0x40CC840ull
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_BASE 0x40CC854ull
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_BASE 0x40CC868ull
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_SECTION 0x1800
+#define mmDCORE0_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_BASE 0x40CC880ull
+#define DCORE0_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_MAX_OFFSET 0x6000
+#define DCORE0_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_SECTION 0x8800
+#define mmDCORE0_MME_CTRL_HI_SHADOW_3_BASE_ADDR_BASE 0x40CC908ull
+#define DCORE0_MME_CTRL_HI_SHADOW_3_BASE_ADDR_MAX_OFFSET 0x2000
+#define DCORE0_MME_CTRL_HI_SHADOW_3_BASE_ADDR_SECTION 0x2000
+#define mmDCORE0_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_BASE 0x40CC928ull
+#define DCORE0_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_MAX_OFFSET 0x1800
+#define DCORE0_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_SECTION 0x1800
+#define mmDCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_A_BASE 0x40CC940ull
+#define DCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_A_MAX_OFFSET 0x5800
+#define DCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_A_SECTION 0x5800
+#define mmDCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_B_BASE 0x40CC998ull
+#define DCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_B_MAX_OFFSET 0x5800
+#define DCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_B_SECTION 0x5800
+#define mmDCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_BASE 0x40CC9F0ull
+#define DCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_MAX_OFFSET 0x5800
+#define DCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_SECTION 0x6C00
+#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_BASE 0x40CCA5Cull
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_BASE 0x40CCA70ull
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_BASE 0x40CCA84ull
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_BASE 0x40CCA98ull
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_BASE 0x40CCAACull
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_BASE 0x40CCAC0ull
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_BASE 0x40CCAD4ull
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_BASE 0x40CCAE8ull
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_BASE 0x40CCAFCull
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_BASE 0x40CCB10ull
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_SECTION 0x1C00
+#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_BASE 0x40CCB2Cull
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_BASE 0x40CCB40ull
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_BASE 0x40CCB54ull
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_SECTION 0x1400
+#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_BASE 0x40CCB68ull
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_SECTION 0x1800
+#define mmDCORE0_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_BASE 0x40CCB80ull
+#define DCORE0_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_MAX_OFFSET 0x6000
+#define DCORE0_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_SECTION 0x3000
+#define mmDCORE0_MME_CTRL_HI_SPECIAL_BASE 0x40CCE80ull
+#define DCORE0_MME_CTRL_HI_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_CTRL_HI_SPECIAL_SECTION 0x1800
+#define mmDCORE0_MME_EU_BIST_BASE 0x40CD000ull
+#define DCORE0_MME_EU_BIST_MAX_OFFSET 0x1000
+#define DCORE0_MME_EU_BIST_SECTION 0xE800
+#define mmDCORE0_MME_EU_BIST_SPECIAL_BASE 0x40CDE80ull
+#define DCORE0_MME_EU_BIST_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_EU_BIST_SPECIAL_SECTION 0x1800
+#define mmDCORE0_MME_CTRL_MSTR_IF_RR_SHRD_HBW_BASE 0x40CE000ull
+#define DCORE0_MME_CTRL_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_MME_CTRL_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE0_MME_CTRL_MSTR_IF_RR_PRVT_HBW_BASE 0x40CE200ull
+#define DCORE0_MME_CTRL_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_MME_CTRL_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE0_MME_CTRL_MSTR_IF_RR_SHRD_LBW_BASE 0x40CE400ull
+#define DCORE0_MME_CTRL_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_MME_CTRL_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE0_MME_CTRL_MSTR_IF_RR_PRVT_LBW_BASE 0x40CE600ull
+#define DCORE0_MME_CTRL_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_MME_CTRL_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE0_MME_CTRL_MSTR_IF_E2E_CRDT_BASE 0x40CE800ull
+#define DCORE0_MME_CTRL_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_MME_CTRL_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE0_MME_CTRL_MSTR_IF_AXUSER_BASE 0x40CEA80ull
+#define DCORE0_MME_CTRL_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_MME_CTRL_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE0_MME_CTRL_MSTR_IF_DBG_HBW_BASE 0x40CEB00ull
+#define DCORE0_MME_CTRL_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_MME_CTRL_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_MME_CTRL_MSTR_IF_DBG_LBW_BASE 0x40CEB80ull
+#define DCORE0_MME_CTRL_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_MME_CTRL_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE0_MME_CTRL_MSTR_IF_CORE_HBW_BASE 0x40CEC00ull
+#define DCORE0_MME_CTRL_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_MME_CTRL_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE0_MME_CTRL_MSTR_IF_CORE_LBW_BASE 0x40CED80ull
+#define DCORE0_MME_CTRL_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_MME_CTRL_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE0_MME_CTRL_MSTR_IF_SPECIAL_BASE 0x40CEE80ull
+#define DCORE0_MME_CTRL_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_CTRL_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_BASE 0x40CF000ull
+#define DCORE0_MME_QM_ARC_ACP_ENG_MAX_OFFSET 0x1000
+#define DCORE0_MME_QM_ARC_ACP_ENG_SECTION 0xE800
+#define mmDCORE0_MME_QM_ARC_ACP_ENG_SPECIAL_BASE 0x40CFE80ull
+#define DCORE0_MME_QM_ARC_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_QM_ARC_ACP_ENG_SPECIAL_SECTION 0x1800
+#define mmDCORE0_MME_SBTE0_BASE 0x40D0000ull
+#define DCORE0_MME_SBTE0_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE0_SECTION 0xE800
+#define mmDCORE0_MME_SBTE0_SPECIAL_BASE 0x40D0E80ull
+#define DCORE0_MME_SBTE0_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_SBTE0_SPECIAL_SECTION 0x1800
+#define mmDCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_BASE 0x40D1000ull
+#define DCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE0_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_BASE 0x40D1200ull
+#define DCORE0_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_BASE 0x40D1400ull
+#define DCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE0_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_BASE 0x40D1600ull
+#define DCORE0_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE0_MME_SBTE0_MSTR_IF_E2E_CRDT_BASE 0x40D1800ull
+#define DCORE0_MME_SBTE0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_MME_SBTE0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_BASE 0x40D1A80ull
+#define DCORE0_MME_SBTE0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_MME_SBTE0_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE0_MME_SBTE0_MSTR_IF_DBG_HBW_BASE 0x40D1B00ull
+#define DCORE0_MME_SBTE0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_MME_SBTE0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_MME_SBTE0_MSTR_IF_DBG_LBW_BASE 0x40D1B80ull
+#define DCORE0_MME_SBTE0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_MME_SBTE0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE0_MME_SBTE0_MSTR_IF_CORE_HBW_BASE 0x40D1C00ull
+#define DCORE0_MME_SBTE0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_MME_SBTE0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE0_MME_SBTE0_MSTR_IF_CORE_LBW_BASE 0x40D1D80ull
+#define DCORE0_MME_SBTE0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_MME_SBTE0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE0_MME_SBTE0_MSTR_IF_SPECIAL_BASE 0x40D1E80ull
+#define DCORE0_MME_SBTE0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_SBTE0_MSTR_IF_SPECIAL_SECTION 0x6180
+#define mmDCORE0_MME_SBTE1_BASE 0x40D8000ull
+#define DCORE0_MME_SBTE1_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE1_SECTION 0xE800
+#define mmDCORE0_MME_SBTE1_SPECIAL_BASE 0x40D8E80ull
+#define DCORE0_MME_SBTE1_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_SBTE1_SPECIAL_SECTION 0x1800
+#define mmDCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_BASE 0x40D9000ull
+#define DCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE0_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_BASE 0x40D9200ull
+#define DCORE0_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_BASE 0x40D9400ull
+#define DCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE0_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_BASE 0x40D9600ull
+#define DCORE0_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE0_MME_SBTE1_MSTR_IF_E2E_CRDT_BASE 0x40D9800ull
+#define DCORE0_MME_SBTE1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_MME_SBTE1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE0_MME_SBTE1_MSTR_IF_AXUSER_BASE 0x40D9A80ull
+#define DCORE0_MME_SBTE1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_MME_SBTE1_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE0_MME_SBTE1_MSTR_IF_DBG_HBW_BASE 0x40D9B00ull
+#define DCORE0_MME_SBTE1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_MME_SBTE1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_MME_SBTE1_MSTR_IF_DBG_LBW_BASE 0x40D9B80ull
+#define DCORE0_MME_SBTE1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_MME_SBTE1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE0_MME_SBTE1_MSTR_IF_CORE_HBW_BASE 0x40D9C00ull
+#define DCORE0_MME_SBTE1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_MME_SBTE1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE0_MME_SBTE1_MSTR_IF_CORE_LBW_BASE 0x40D9D80ull
+#define DCORE0_MME_SBTE1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_MME_SBTE1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE0_MME_SBTE1_MSTR_IF_SPECIAL_BASE 0x40D9E80ull
+#define DCORE0_MME_SBTE1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_SBTE1_MSTR_IF_SPECIAL_SECTION 0x6180
+#define mmDCORE0_MME_SBTE2_BASE 0x40E0000ull
+#define DCORE0_MME_SBTE2_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE2_SECTION 0xE800
+#define mmDCORE0_MME_SBTE2_SPECIAL_BASE 0x40E0E80ull
+#define DCORE0_MME_SBTE2_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_SBTE2_SPECIAL_SECTION 0x1800
+#define mmDCORE0_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_BASE 0x40E1000ull
+#define DCORE0_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE0_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_BASE 0x40E1200ull
+#define DCORE0_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE0_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_BASE 0x40E1400ull
+#define DCORE0_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE0_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_BASE 0x40E1600ull
+#define DCORE0_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE0_MME_SBTE2_MSTR_IF_E2E_CRDT_BASE 0x40E1800ull
+#define DCORE0_MME_SBTE2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_MME_SBTE2_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE0_MME_SBTE2_MSTR_IF_AXUSER_BASE 0x40E1A80ull
+#define DCORE0_MME_SBTE2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_MME_SBTE2_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE0_MME_SBTE2_MSTR_IF_DBG_HBW_BASE 0x40E1B00ull
+#define DCORE0_MME_SBTE2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_MME_SBTE2_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_MME_SBTE2_MSTR_IF_DBG_LBW_BASE 0x40E1B80ull
+#define DCORE0_MME_SBTE2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_MME_SBTE2_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE0_MME_SBTE2_MSTR_IF_CORE_HBW_BASE 0x40E1C00ull
+#define DCORE0_MME_SBTE2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_MME_SBTE2_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE0_MME_SBTE2_MSTR_IF_CORE_LBW_BASE 0x40E1D80ull
+#define DCORE0_MME_SBTE2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_MME_SBTE2_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE0_MME_SBTE2_MSTR_IF_SPECIAL_BASE 0x40E1E80ull
+#define DCORE0_MME_SBTE2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_SBTE2_MSTR_IF_SPECIAL_SECTION 0x6180
+#define mmDCORE0_MME_SBTE3_BASE 0x40E8000ull
+#define DCORE0_MME_SBTE3_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE3_SECTION 0xE800
+#define mmDCORE0_MME_SBTE3_SPECIAL_BASE 0x40E8E80ull
+#define DCORE0_MME_SBTE3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_SBTE3_SPECIAL_SECTION 0x1800
+#define mmDCORE0_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_BASE 0x40E9000ull
+#define DCORE0_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE0_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_BASE 0x40E9200ull
+#define DCORE0_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE0_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_BASE 0x40E9400ull
+#define DCORE0_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE0_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_BASE 0x40E9600ull
+#define DCORE0_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE0_MME_SBTE3_MSTR_IF_E2E_CRDT_BASE 0x40E9800ull
+#define DCORE0_MME_SBTE3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_MME_SBTE3_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE0_MME_SBTE3_MSTR_IF_AXUSER_BASE 0x40E9A80ull
+#define DCORE0_MME_SBTE3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_MME_SBTE3_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE0_MME_SBTE3_MSTR_IF_DBG_HBW_BASE 0x40E9B00ull
+#define DCORE0_MME_SBTE3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_MME_SBTE3_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_MME_SBTE3_MSTR_IF_DBG_LBW_BASE 0x40E9B80ull
+#define DCORE0_MME_SBTE3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_MME_SBTE3_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE0_MME_SBTE3_MSTR_IF_CORE_HBW_BASE 0x40E9C00ull
+#define DCORE0_MME_SBTE3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_MME_SBTE3_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE0_MME_SBTE3_MSTR_IF_CORE_LBW_BASE 0x40E9D80ull
+#define DCORE0_MME_SBTE3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_MME_SBTE3_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE0_MME_SBTE3_MSTR_IF_SPECIAL_BASE 0x40E9E80ull
+#define DCORE0_MME_SBTE3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_SBTE3_MSTR_IF_SPECIAL_SECTION 0x6180
+#define mmDCORE0_MME_SBTE4_BASE 0x40F0000ull
+#define DCORE0_MME_SBTE4_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE4_SECTION 0xE800
+#define mmDCORE0_MME_SBTE4_SPECIAL_BASE 0x40F0E80ull
+#define DCORE0_MME_SBTE4_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_SBTE4_SPECIAL_SECTION 0x1800
+#define mmDCORE0_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_BASE 0x40F1000ull
+#define DCORE0_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE0_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_BASE 0x40F1200ull
+#define DCORE0_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE0_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_BASE 0x40F1400ull
+#define DCORE0_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE0_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_BASE 0x40F1600ull
+#define DCORE0_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE0_MME_SBTE4_MSTR_IF_E2E_CRDT_BASE 0x40F1800ull
+#define DCORE0_MME_SBTE4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_MME_SBTE4_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE0_MME_SBTE4_MSTR_IF_AXUSER_BASE 0x40F1A80ull
+#define DCORE0_MME_SBTE4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_MME_SBTE4_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE0_MME_SBTE4_MSTR_IF_DBG_HBW_BASE 0x40F1B00ull
+#define DCORE0_MME_SBTE4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_MME_SBTE4_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_MME_SBTE4_MSTR_IF_DBG_LBW_BASE 0x40F1B80ull
+#define DCORE0_MME_SBTE4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_MME_SBTE4_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE0_MME_SBTE4_MSTR_IF_CORE_HBW_BASE 0x40F1C00ull
+#define DCORE0_MME_SBTE4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_MME_SBTE4_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE0_MME_SBTE4_MSTR_IF_CORE_LBW_BASE 0x40F1D80ull
+#define DCORE0_MME_SBTE4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_MME_SBTE4_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE0_MME_SBTE4_MSTR_IF_SPECIAL_BASE 0x40F1E80ull
+#define DCORE0_MME_SBTE4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_SBTE4_MSTR_IF_SPECIAL_SECTION 0x6180
+#define mmDCORE0_MME_ACC_BASE 0x40F8000ull
+#define DCORE0_MME_ACC_MAX_OFFSET 0x1000
+#define DCORE0_MME_ACC_SECTION 0xE800
+#define mmDCORE0_MME_ACC_SPECIAL_BASE 0x40F8E80ull
+#define DCORE0_MME_ACC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_ACC_SPECIAL_SECTION 0x1800
+#define mmDCORE0_MME_WB0_MSTR_IF_RR_SHRD_HBW_BASE 0x40F9000ull
+#define DCORE0_MME_WB0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_MME_WB0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE0_MME_WB0_MSTR_IF_RR_PRVT_HBW_BASE 0x40F9200ull
+#define DCORE0_MME_WB0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_MME_WB0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE0_MME_WB0_MSTR_IF_RR_SHRD_LBW_BASE 0x40F9400ull
+#define DCORE0_MME_WB0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_MME_WB0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE0_MME_WB0_MSTR_IF_RR_PRVT_LBW_BASE 0x40F9600ull
+#define DCORE0_MME_WB0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_MME_WB0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE0_MME_WB0_MSTR_IF_E2E_CRDT_BASE 0x40F9800ull
+#define DCORE0_MME_WB0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_MME_WB0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_BASE 0x40F9A80ull
+#define DCORE0_MME_WB0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_MME_WB0_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE0_MME_WB0_MSTR_IF_DBG_HBW_BASE 0x40F9B00ull
+#define DCORE0_MME_WB0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_MME_WB0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_MME_WB0_MSTR_IF_DBG_LBW_BASE 0x40F9B80ull
+#define DCORE0_MME_WB0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_MME_WB0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE0_MME_WB0_MSTR_IF_CORE_HBW_BASE 0x40F9C00ull
+#define DCORE0_MME_WB0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_MME_WB0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE0_MME_WB0_MSTR_IF_CORE_LBW_BASE 0x40F9D80ull
+#define DCORE0_MME_WB0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_MME_WB0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE0_MME_WB0_MSTR_IF_SPECIAL_BASE 0x40F9E80ull
+#define DCORE0_MME_WB0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_WB0_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE0_MME_WB1_MSTR_IF_RR_SHRD_HBW_BASE 0x40FA000ull
+#define DCORE0_MME_WB1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_MME_WB1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE0_MME_WB1_MSTR_IF_RR_PRVT_HBW_BASE 0x40FA200ull
+#define DCORE0_MME_WB1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_MME_WB1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE0_MME_WB1_MSTR_IF_RR_SHRD_LBW_BASE 0x40FA400ull
+#define DCORE0_MME_WB1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_MME_WB1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE0_MME_WB1_MSTR_IF_RR_PRVT_LBW_BASE 0x40FA600ull
+#define DCORE0_MME_WB1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_MME_WB1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE0_MME_WB1_MSTR_IF_E2E_CRDT_BASE 0x40FA800ull
+#define DCORE0_MME_WB1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_MME_WB1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE0_MME_WB1_MSTR_IF_AXUSER_BASE 0x40FAA80ull
+#define DCORE0_MME_WB1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_MME_WB1_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE0_MME_WB1_MSTR_IF_DBG_HBW_BASE 0x40FAB00ull
+#define DCORE0_MME_WB1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_MME_WB1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_MME_WB1_MSTR_IF_DBG_LBW_BASE 0x40FAB80ull
+#define DCORE0_MME_WB1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_MME_WB1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE0_MME_WB1_MSTR_IF_CORE_HBW_BASE 0x40FAC00ull
+#define DCORE0_MME_WB1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_MME_WB1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE0_MME_WB1_MSTR_IF_CORE_LBW_BASE 0x40FAD80ull
+#define DCORE0_MME_WB1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_MME_WB1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE0_MME_WB1_MSTR_IF_SPECIAL_BASE 0x40FAE80ull
+#define DCORE0_MME_WB1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_MME_WB1_MSTR_IF_SPECIAL_SECTION 0x5180
+#define mmDCORE0_SYNC_MNGR_OBJS_BASE 0x4100000ull
+#define DCORE0_SYNC_MNGR_OBJS_MAX_OFFSET 0x15A00
+#define DCORE0_SYNC_MNGR_OBJS_SECTION 0x1E000
+#define mmDCORE0_SYNC_MNGR_GLBL_BASE 0x411E000ull
+#define DCORE0_SYNC_MNGR_GLBL_MAX_OFFSET 0x1000
+#define DCORE0_SYNC_MNGR_GLBL_SECTION 0xE800
+#define mmDCORE0_SYNC_MNGR_GLBL_SPECIAL_BASE 0x411EE80ull
+#define DCORE0_SYNC_MNGR_GLBL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SYNC_MNGR_GLBL_SPECIAL_SECTION 0x1800
+#define mmDCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_BASE 0x411F000ull
+#define DCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_BASE 0x411F200ull
+#define DCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_BASE 0x411F400ull
+#define DCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_BASE 0x411F600ull
+#define DCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE0_SYNC_MNGR_MSTR_IF_E2E_CRDT_BASE 0x411F800ull
+#define DCORE0_SYNC_MNGR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_SYNC_MNGR_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_BASE 0x411FA80ull
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE0_SYNC_MNGR_MSTR_IF_DBG_HBW_BASE 0x411FB00ull
+#define DCORE0_SYNC_MNGR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_SYNC_MNGR_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_SYNC_MNGR_MSTR_IF_DBG_LBW_BASE 0x411FB80ull
+#define DCORE0_SYNC_MNGR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_SYNC_MNGR_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE0_SYNC_MNGR_MSTR_IF_CORE_HBW_BASE 0x411FC00ull
+#define DCORE0_SYNC_MNGR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_SYNC_MNGR_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE0_SYNC_MNGR_MSTR_IF_CORE_LBW_BASE 0x411FD80ull
+#define DCORE0_SYNC_MNGR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_SYNC_MNGR_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE0_SYNC_MNGR_MSTR_IF_SPECIAL_BASE 0x411FE80ull
+#define DCORE0_SYNC_MNGR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SYNC_MNGR_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE0_HIF0_BASE 0x4120000ull
+#define DCORE0_HIF0_MAX_OFFSET 0x1000
+#define DCORE0_HIF0_SECTION 0xE800
+#define mmDCORE0_HIF0_SPECIAL_BASE 0x4120E80ull
+#define DCORE0_HIF0_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HIF0_SPECIAL_SECTION 0x3180
+#define mmDCORE0_HIF1_BASE 0x4124000ull
+#define DCORE0_HIF1_MAX_OFFSET 0x1000
+#define DCORE0_HIF1_SECTION 0xE800
+#define mmDCORE0_HIF1_SPECIAL_BASE 0x4124E80ull
+#define DCORE0_HIF1_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HIF1_SPECIAL_SECTION 0x3180
+#define mmDCORE0_HIF2_BASE 0x4128000ull
+#define DCORE0_HIF2_MAX_OFFSET 0x1000
+#define DCORE0_HIF2_SECTION 0xE800
+#define mmDCORE0_HIF2_SPECIAL_BASE 0x4128E80ull
+#define DCORE0_HIF2_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HIF2_SPECIAL_SECTION 0x3180
+#define mmDCORE0_HIF3_BASE 0x412C000ull
+#define DCORE0_HIF3_MAX_OFFSET 0x1000
+#define DCORE0_HIF3_SECTION 0xE800
+#define mmDCORE0_HIF3_SPECIAL_BASE 0x412CE80ull
+#define DCORE0_HIF3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HIF3_SPECIAL_SECTION 0x13180
+#define mmDCORE0_RTR0_CTRL_BASE 0x4140000ull
+#define DCORE0_RTR0_CTRL_MAX_OFFSET 0x1000
+#define DCORE0_RTR0_CTRL_SECTION 0xE800
+#define mmDCORE0_RTR0_CTRL_SPECIAL_BASE 0x4140E80ull
+#define DCORE0_RTR0_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR0_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE0_RTR0_H3_BASE 0x4141000ull
+#define DCORE0_RTR0_H3_MAX_OFFSET 0x1000
+#define DCORE0_RTR0_H3_SECTION 0xE800
+#define mmDCORE0_RTR0_H3_SPECIAL_BASE 0x4141E80ull
+#define DCORE0_RTR0_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR0_H3_SPECIAL_SECTION 0x1800
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE 0x4142000ull
+#define DCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_BASE 0x4142200ull
+#define DCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE 0x4142400ull
+#define DCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_BASE 0x4142600ull
+#define DCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE0_RTR0_MSTR_IF_E2E_CRDT_BASE 0x4142800ull
+#define DCORE0_RTR0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_RTR0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE0_RTR0_MSTR_IF_AXUSER_BASE 0x4142A80ull
+#define DCORE0_RTR0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_RTR0_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE0_RTR0_MSTR_IF_DBG_HBW_BASE 0x4142B00ull
+#define DCORE0_RTR0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_RTR0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_RTR0_MSTR_IF_DBG_LBW_BASE 0x4142B80ull
+#define DCORE0_RTR0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_RTR0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE0_RTR0_MSTR_IF_CORE_HBW_BASE 0x4142C00ull
+#define DCORE0_RTR0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_RTR0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE0_RTR0_MSTR_IF_CORE_LBW_BASE 0x4142D80ull
+#define DCORE0_RTR0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_RTR0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE0_RTR0_MSTR_IF_SPECIAL_BASE 0x4142E80ull
+#define DCORE0_RTR0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR0_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE0_RTR0_ADD_DEC_HBW_BASE 0x4143000ull
+#define DCORE0_RTR0_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE0_RTR0_ADD_DEC_HBW_SECTION 0x4000
+#define mmDCORE0_RTR0_ADD_DEC_LBW_BASE 0x4143400ull
+#define DCORE0_RTR0_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE0_RTR0_ADD_DEC_LBW_SECTION 0xA800
+#define mmDCORE0_RTR0_ADD_DEC_SPECIAL_BASE 0x4143E80ull
+#define DCORE0_RTR0_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR0_ADD_DEC_SPECIAL_SECTION 0x1800
+#define mmDCORE0_RTR0_BASE 0x4144000ull
+#define DCORE0_RTR0_MAX_OFFSET 0x1000
+#define DCORE0_RTR0_SECTION 0x3000
+#define mmDCORE0_RTR0_HBW_RD_RQ_LL_STAT_BASE 0x4144300ull
+#define DCORE0_RTR0_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR0_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR0_HBW_RD_RS_LL_STAT_BASE 0x4144340ull
+#define DCORE0_RTR0_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR0_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR0_HBW_WR_RQ_LL_STAT_BASE 0x4144380ull
+#define DCORE0_RTR0_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR0_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR0_HBW_WR_RS_LL_STAT_BASE 0x41443C0ull
+#define DCORE0_RTR0_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR0_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR0_LBW_RD_RQ_LL_STAT_BASE 0x4144400ull
+#define DCORE0_RTR0_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR0_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR0_LBW_RD_RS_LL_STAT_BASE 0x4144440ull
+#define DCORE0_RTR0_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR0_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR0_LBW_WR_RQ_LL_STAT_BASE 0x4144480ull
+#define DCORE0_RTR0_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR0_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR0_LBW_WR_RS_LL_STAT_BASE 0x41444C0ull
+#define DCORE0_RTR0_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR0_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR0_HBW_MFIFO_BASE 0x4144500ull
+#define DCORE0_RTR0_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE0_RTR0_HBW_MFIFO_SECTION 0x4000
+#define mmDCORE0_RTR0_E2E_RD_LL_STAT_BASE 0x4144540ull
+#define DCORE0_RTR0_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR0_E2E_RD_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR0_E2E_WR_LL_STAT_BASE 0x4144580ull
+#define DCORE0_RTR0_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR0_E2E_WR_LL_STAT_SECTION 0x8000
+#define mmDCORE0_RTR0_RTR_HBW_XACT_STAT_BASE 0x4144600ull
+#define DCORE0_RTR0_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR0_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE0_RTR0_RTR_LBW_XACT_STAT_BASE 0x4144680ull
+#define DCORE0_RTR0_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR0_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE0_RTR0_RTR_E2E_XACT_STAT_BASE 0x4144700ull
+#define DCORE0_RTR0_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR0_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define mmDCORE0_RTR0_SPECIAL_BASE 0x4144E80ull
+#define DCORE0_RTR0_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR0_SPECIAL_SECTION 0x1800
+#define mmDCORE0_RTR0_DBG_ADDR_BASE 0x4145000ull
+#define DCORE0_RTR0_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE0_RTR0_DBG_ADDR_SECTION 0xE800
+#define mmDCORE0_RTR0_DBG_ADDR_SPECIAL_BASE 0x4145E80ull
+#define DCORE0_RTR0_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR0_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define mmDCORE0_RTR1_CTRL_BASE 0x4148000ull
+#define DCORE0_RTR1_CTRL_MAX_OFFSET 0x1000
+#define DCORE0_RTR1_CTRL_SECTION 0xE800
+#define mmDCORE0_RTR1_CTRL_SPECIAL_BASE 0x4148E80ull
+#define DCORE0_RTR1_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR1_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE0_RTR1_H3_BASE 0x4149000ull
+#define DCORE0_RTR1_H3_MAX_OFFSET 0x1000
+#define DCORE0_RTR1_H3_SECTION 0xE800
+#define mmDCORE0_RTR1_H3_SPECIAL_BASE 0x4149E80ull
+#define DCORE0_RTR1_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR1_H3_SPECIAL_SECTION 0x1800
+#define mmDCORE0_RTR1_MSTR_IF_RR_SHRD_HBW_BASE 0x414A000ull
+#define DCORE0_RTR1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_RTR1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE0_RTR1_MSTR_IF_RR_PRVT_HBW_BASE 0x414A200ull
+#define DCORE0_RTR1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_RTR1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE0_RTR1_MSTR_IF_RR_SHRD_LBW_BASE 0x414A400ull
+#define DCORE0_RTR1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_RTR1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE0_RTR1_MSTR_IF_RR_PRVT_LBW_BASE 0x414A600ull
+#define DCORE0_RTR1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_RTR1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE0_RTR1_MSTR_IF_E2E_CRDT_BASE 0x414A800ull
+#define DCORE0_RTR1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_RTR1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE0_RTR1_MSTR_IF_AXUSER_BASE 0x414AA80ull
+#define DCORE0_RTR1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_RTR1_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE0_RTR1_MSTR_IF_DBG_HBW_BASE 0x414AB00ull
+#define DCORE0_RTR1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_RTR1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_RTR1_MSTR_IF_DBG_LBW_BASE 0x414AB80ull
+#define DCORE0_RTR1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_RTR1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE0_RTR1_MSTR_IF_CORE_HBW_BASE 0x414AC00ull
+#define DCORE0_RTR1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_RTR1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE0_RTR1_MSTR_IF_CORE_LBW_BASE 0x414AD80ull
+#define DCORE0_RTR1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_RTR1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE0_RTR1_MSTR_IF_SPECIAL_BASE 0x414AE80ull
+#define DCORE0_RTR1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR1_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE0_RTR1_ADD_DEC_HBW_BASE 0x414B000ull
+#define DCORE0_RTR1_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE0_RTR1_ADD_DEC_HBW_SECTION 0x4000
+#define mmDCORE0_RTR1_ADD_DEC_LBW_BASE 0x414B400ull
+#define DCORE0_RTR1_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE0_RTR1_ADD_DEC_LBW_SECTION 0xA800
+#define mmDCORE0_RTR1_ADD_DEC_SPECIAL_BASE 0x414BE80ull
+#define DCORE0_RTR1_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR1_ADD_DEC_SPECIAL_SECTION 0x1800
+#define mmDCORE0_RTR1_BASE 0x414C000ull
+#define DCORE0_RTR1_MAX_OFFSET 0x1000
+#define DCORE0_RTR1_SECTION 0x3000
+#define mmDCORE0_RTR1_HBW_RD_RQ_LL_STAT_BASE 0x414C300ull
+#define DCORE0_RTR1_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR1_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR1_HBW_RD_RS_LL_STAT_BASE 0x414C340ull
+#define DCORE0_RTR1_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR1_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR1_HBW_WR_RQ_LL_STAT_BASE 0x414C380ull
+#define DCORE0_RTR1_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR1_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR1_HBW_WR_RS_LL_STAT_BASE 0x414C3C0ull
+#define DCORE0_RTR1_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR1_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR1_LBW_RD_RQ_LL_STAT_BASE 0x414C400ull
+#define DCORE0_RTR1_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR1_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR1_LBW_RD_RS_LL_STAT_BASE 0x414C440ull
+#define DCORE0_RTR1_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR1_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR1_LBW_WR_RQ_LL_STAT_BASE 0x414C480ull
+#define DCORE0_RTR1_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR1_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR1_LBW_WR_RS_LL_STAT_BASE 0x414C4C0ull
+#define DCORE0_RTR1_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR1_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR1_HBW_MFIFO_BASE 0x414C500ull
+#define DCORE0_RTR1_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE0_RTR1_HBW_MFIFO_SECTION 0x4000
+#define mmDCORE0_RTR1_E2E_RD_LL_STAT_BASE 0x414C540ull
+#define DCORE0_RTR1_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR1_E2E_RD_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR1_E2E_WR_LL_STAT_BASE 0x414C580ull
+#define DCORE0_RTR1_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR1_E2E_WR_LL_STAT_SECTION 0x8000
+#define mmDCORE0_RTR1_RTR_HBW_XACT_STAT_BASE 0x414C600ull
+#define DCORE0_RTR1_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR1_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE0_RTR1_RTR_LBW_XACT_STAT_BASE 0x414C680ull
+#define DCORE0_RTR1_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR1_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE0_RTR1_RTR_E2E_XACT_STAT_BASE 0x414C700ull
+#define DCORE0_RTR1_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR1_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define mmDCORE0_RTR1_SPECIAL_BASE 0x414CE80ull
+#define DCORE0_RTR1_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR1_SPECIAL_SECTION 0x1800
+#define mmDCORE0_RTR1_DBG_ADDR_BASE 0x414D000ull
+#define DCORE0_RTR1_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE0_RTR1_DBG_ADDR_SECTION 0xE800
+#define mmDCORE0_RTR1_DBG_ADDR_SPECIAL_BASE 0x414DE80ull
+#define DCORE0_RTR1_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR1_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define mmDCORE0_RTR2_CTRL_BASE 0x4150000ull
+#define DCORE0_RTR2_CTRL_MAX_OFFSET 0x1000
+#define DCORE0_RTR2_CTRL_SECTION 0xE800
+#define mmDCORE0_RTR2_CTRL_SPECIAL_BASE 0x4150E80ull
+#define DCORE0_RTR2_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR2_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE0_RTR2_H3_BASE 0x4151000ull
+#define DCORE0_RTR2_H3_MAX_OFFSET 0x1000
+#define DCORE0_RTR2_H3_SECTION 0xE800
+#define mmDCORE0_RTR2_H3_SPECIAL_BASE 0x4151E80ull
+#define DCORE0_RTR2_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR2_H3_SPECIAL_SECTION 0x1800
+#define mmDCORE0_RTR2_MSTR_IF_RR_SHRD_HBW_BASE 0x4152000ull
+#define DCORE0_RTR2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_RTR2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE0_RTR2_MSTR_IF_RR_PRVT_HBW_BASE 0x4152200ull
+#define DCORE0_RTR2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_RTR2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE0_RTR2_MSTR_IF_RR_SHRD_LBW_BASE 0x4152400ull
+#define DCORE0_RTR2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_RTR2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE0_RTR2_MSTR_IF_RR_PRVT_LBW_BASE 0x4152600ull
+#define DCORE0_RTR2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_RTR2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE0_RTR2_MSTR_IF_E2E_CRDT_BASE 0x4152800ull
+#define DCORE0_RTR2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_RTR2_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE0_RTR2_MSTR_IF_AXUSER_BASE 0x4152A80ull
+#define DCORE0_RTR2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_RTR2_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE0_RTR2_MSTR_IF_DBG_HBW_BASE 0x4152B00ull
+#define DCORE0_RTR2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_RTR2_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_RTR2_MSTR_IF_DBG_LBW_BASE 0x4152B80ull
+#define DCORE0_RTR2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_RTR2_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE0_RTR2_MSTR_IF_CORE_HBW_BASE 0x4152C00ull
+#define DCORE0_RTR2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_RTR2_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE0_RTR2_MSTR_IF_CORE_LBW_BASE 0x4152D80ull
+#define DCORE0_RTR2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_RTR2_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE0_RTR2_MSTR_IF_SPECIAL_BASE 0x4152E80ull
+#define DCORE0_RTR2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR2_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE0_RTR2_ADD_DEC_HBW_BASE 0x4153000ull
+#define DCORE0_RTR2_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE0_RTR2_ADD_DEC_HBW_SECTION 0x4000
+#define mmDCORE0_RTR2_ADD_DEC_LBW_BASE 0x4153400ull
+#define DCORE0_RTR2_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE0_RTR2_ADD_DEC_LBW_SECTION 0xA800
+#define mmDCORE0_RTR2_ADD_DEC_SPECIAL_BASE 0x4153E80ull
+#define DCORE0_RTR2_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR2_ADD_DEC_SPECIAL_SECTION 0x1800
+#define mmDCORE0_RTR2_BASE 0x4154000ull
+#define DCORE0_RTR2_MAX_OFFSET 0x1000
+#define DCORE0_RTR2_SECTION 0x3000
+#define mmDCORE0_RTR2_HBW_RD_RQ_LL_STAT_BASE 0x4154300ull
+#define DCORE0_RTR2_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR2_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR2_HBW_RD_RS_LL_STAT_BASE 0x4154340ull
+#define DCORE0_RTR2_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR2_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR2_HBW_WR_RQ_LL_STAT_BASE 0x4154380ull
+#define DCORE0_RTR2_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR2_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR2_HBW_WR_RS_LL_STAT_BASE 0x41543C0ull
+#define DCORE0_RTR2_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR2_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR2_LBW_RD_RQ_LL_STAT_BASE 0x4154400ull
+#define DCORE0_RTR2_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR2_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR2_LBW_RD_RS_LL_STAT_BASE 0x4154440ull
+#define DCORE0_RTR2_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR2_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR2_LBW_WR_RQ_LL_STAT_BASE 0x4154480ull
+#define DCORE0_RTR2_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR2_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR2_LBW_WR_RS_LL_STAT_BASE 0x41544C0ull
+#define DCORE0_RTR2_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR2_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR2_HBW_MFIFO_BASE 0x4154500ull
+#define DCORE0_RTR2_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE0_RTR2_HBW_MFIFO_SECTION 0x4000
+#define mmDCORE0_RTR2_E2E_RD_LL_STAT_BASE 0x4154540ull
+#define DCORE0_RTR2_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR2_E2E_RD_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR2_E2E_WR_LL_STAT_BASE 0x4154580ull
+#define DCORE0_RTR2_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR2_E2E_WR_LL_STAT_SECTION 0x8000
+#define mmDCORE0_RTR2_RTR_HBW_XACT_STAT_BASE 0x4154600ull
+#define DCORE0_RTR2_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR2_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE0_RTR2_RTR_LBW_XACT_STAT_BASE 0x4154680ull
+#define DCORE0_RTR2_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR2_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE0_RTR2_RTR_E2E_XACT_STAT_BASE 0x4154700ull
+#define DCORE0_RTR2_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR2_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define mmDCORE0_RTR2_SPECIAL_BASE 0x4154E80ull
+#define DCORE0_RTR2_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR2_SPECIAL_SECTION 0x1800
+#define mmDCORE0_RTR2_DBG_ADDR_BASE 0x4155000ull
+#define DCORE0_RTR2_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE0_RTR2_DBG_ADDR_SECTION 0xE800
+#define mmDCORE0_RTR2_DBG_ADDR_SPECIAL_BASE 0x4155E80ull
+#define DCORE0_RTR2_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR2_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define mmDCORE0_RTR3_CTRL_BASE 0x4158000ull
+#define DCORE0_RTR3_CTRL_MAX_OFFSET 0x1000
+#define DCORE0_RTR3_CTRL_SECTION 0xE800
+#define mmDCORE0_RTR3_CTRL_SPECIAL_BASE 0x4158E80ull
+#define DCORE0_RTR3_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR3_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE0_RTR3_H3_BASE 0x4159000ull
+#define DCORE0_RTR3_H3_MAX_OFFSET 0x1000
+#define DCORE0_RTR3_H3_SECTION 0xE800
+#define mmDCORE0_RTR3_H3_SPECIAL_BASE 0x4159E80ull
+#define DCORE0_RTR3_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR3_H3_SPECIAL_SECTION 0x1800
+#define mmDCORE0_RTR3_MSTR_IF_RR_SHRD_HBW_BASE 0x415A000ull
+#define DCORE0_RTR3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_RTR3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE0_RTR3_MSTR_IF_RR_PRVT_HBW_BASE 0x415A200ull
+#define DCORE0_RTR3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_RTR3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE0_RTR3_MSTR_IF_RR_SHRD_LBW_BASE 0x415A400ull
+#define DCORE0_RTR3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_RTR3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE0_RTR3_MSTR_IF_RR_PRVT_LBW_BASE 0x415A600ull
+#define DCORE0_RTR3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_RTR3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE0_RTR3_MSTR_IF_E2E_CRDT_BASE 0x415A800ull
+#define DCORE0_RTR3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_RTR3_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE0_RTR3_MSTR_IF_AXUSER_BASE 0x415AA80ull
+#define DCORE0_RTR3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_RTR3_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE0_RTR3_MSTR_IF_DBG_HBW_BASE 0x415AB00ull
+#define DCORE0_RTR3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_RTR3_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_RTR3_MSTR_IF_DBG_LBW_BASE 0x415AB80ull
+#define DCORE0_RTR3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_RTR3_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE0_RTR3_MSTR_IF_CORE_HBW_BASE 0x415AC00ull
+#define DCORE0_RTR3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_RTR3_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE0_RTR3_MSTR_IF_CORE_LBW_BASE 0x415AD80ull
+#define DCORE0_RTR3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_RTR3_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE0_RTR3_MSTR_IF_SPECIAL_BASE 0x415AE80ull
+#define DCORE0_RTR3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR3_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE0_RTR3_ADD_DEC_HBW_BASE 0x415B000ull
+#define DCORE0_RTR3_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE0_RTR3_ADD_DEC_HBW_SECTION 0x4000
+#define mmDCORE0_RTR3_ADD_DEC_LBW_BASE 0x415B400ull
+#define DCORE0_RTR3_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE0_RTR3_ADD_DEC_LBW_SECTION 0xA800
+#define mmDCORE0_RTR3_ADD_DEC_SPECIAL_BASE 0x415BE80ull
+#define DCORE0_RTR3_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR3_ADD_DEC_SPECIAL_SECTION 0x1800
+#define mmDCORE0_RTR3_BASE 0x415C000ull
+#define DCORE0_RTR3_MAX_OFFSET 0x1000
+#define DCORE0_RTR3_SECTION 0x3000
+#define mmDCORE0_RTR3_HBW_RD_RQ_LL_STAT_BASE 0x415C300ull
+#define DCORE0_RTR3_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR3_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR3_HBW_RD_RS_LL_STAT_BASE 0x415C340ull
+#define DCORE0_RTR3_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR3_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR3_HBW_WR_RQ_LL_STAT_BASE 0x415C380ull
+#define DCORE0_RTR3_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR3_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR3_HBW_WR_RS_LL_STAT_BASE 0x415C3C0ull
+#define DCORE0_RTR3_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR3_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR3_LBW_RD_RQ_LL_STAT_BASE 0x415C400ull
+#define DCORE0_RTR3_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR3_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR3_LBW_RD_RS_LL_STAT_BASE 0x415C440ull
+#define DCORE0_RTR3_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR3_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR3_LBW_WR_RQ_LL_STAT_BASE 0x415C480ull
+#define DCORE0_RTR3_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR3_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR3_LBW_WR_RS_LL_STAT_BASE 0x415C4C0ull
+#define DCORE0_RTR3_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR3_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR3_HBW_MFIFO_BASE 0x415C500ull
+#define DCORE0_RTR3_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE0_RTR3_HBW_MFIFO_SECTION 0x4000
+#define mmDCORE0_RTR3_E2E_RD_LL_STAT_BASE 0x415C540ull
+#define DCORE0_RTR3_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR3_E2E_RD_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR3_E2E_WR_LL_STAT_BASE 0x415C580ull
+#define DCORE0_RTR3_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR3_E2E_WR_LL_STAT_SECTION 0x8000
+#define mmDCORE0_RTR3_RTR_HBW_XACT_STAT_BASE 0x415C600ull
+#define DCORE0_RTR3_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR3_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE0_RTR3_RTR_LBW_XACT_STAT_BASE 0x415C680ull
+#define DCORE0_RTR3_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR3_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE0_RTR3_RTR_E2E_XACT_STAT_BASE 0x415C700ull
+#define DCORE0_RTR3_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR3_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define mmDCORE0_RTR3_SPECIAL_BASE 0x415CE80ull
+#define DCORE0_RTR3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR3_SPECIAL_SECTION 0x1800
+#define mmDCORE0_RTR3_DBG_ADDR_BASE 0x415D000ull
+#define DCORE0_RTR3_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE0_RTR3_DBG_ADDR_SECTION 0xE800
+#define mmDCORE0_RTR3_DBG_ADDR_SPECIAL_BASE 0x415DE80ull
+#define DCORE0_RTR3_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR3_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define mmDCORE0_RTR4_CTRL_BASE 0x4160000ull
+#define DCORE0_RTR4_CTRL_MAX_OFFSET 0x1000
+#define DCORE0_RTR4_CTRL_SECTION 0xE800
+#define mmDCORE0_RTR4_CTRL_SPECIAL_BASE 0x4160E80ull
+#define DCORE0_RTR4_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR4_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE0_RTR4_H3_BASE 0x4161000ull
+#define DCORE0_RTR4_H3_MAX_OFFSET 0x1000
+#define DCORE0_RTR4_H3_SECTION 0xE800
+#define mmDCORE0_RTR4_H3_SPECIAL_BASE 0x4161E80ull
+#define DCORE0_RTR4_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR4_H3_SPECIAL_SECTION 0x1800
+#define mmDCORE0_RTR4_MSTR_IF_RR_SHRD_HBW_BASE 0x4162000ull
+#define DCORE0_RTR4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_RTR4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE0_RTR4_MSTR_IF_RR_PRVT_HBW_BASE 0x4162200ull
+#define DCORE0_RTR4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_RTR4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE0_RTR4_MSTR_IF_RR_SHRD_LBW_BASE 0x4162400ull
+#define DCORE0_RTR4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_RTR4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE0_RTR4_MSTR_IF_RR_PRVT_LBW_BASE 0x4162600ull
+#define DCORE0_RTR4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_RTR4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE0_RTR4_MSTR_IF_E2E_CRDT_BASE 0x4162800ull
+#define DCORE0_RTR4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_RTR4_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE0_RTR4_MSTR_IF_AXUSER_BASE 0x4162A80ull
+#define DCORE0_RTR4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_RTR4_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE0_RTR4_MSTR_IF_DBG_HBW_BASE 0x4162B00ull
+#define DCORE0_RTR4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_RTR4_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_RTR4_MSTR_IF_DBG_LBW_BASE 0x4162B80ull
+#define DCORE0_RTR4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_RTR4_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE0_RTR4_MSTR_IF_CORE_HBW_BASE 0x4162C00ull
+#define DCORE0_RTR4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_RTR4_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE0_RTR4_MSTR_IF_CORE_LBW_BASE 0x4162D80ull
+#define DCORE0_RTR4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_RTR4_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE0_RTR4_MSTR_IF_SPECIAL_BASE 0x4162E80ull
+#define DCORE0_RTR4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR4_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE0_RTR4_ADD_DEC_HBW_BASE 0x4163000ull
+#define DCORE0_RTR4_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE0_RTR4_ADD_DEC_HBW_SECTION 0x4000
+#define mmDCORE0_RTR4_ADD_DEC_LBW_BASE 0x4163400ull
+#define DCORE0_RTR4_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE0_RTR4_ADD_DEC_LBW_SECTION 0xA800
+#define mmDCORE0_RTR4_ADD_DEC_SPECIAL_BASE 0x4163E80ull
+#define DCORE0_RTR4_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR4_ADD_DEC_SPECIAL_SECTION 0x1800
+#define mmDCORE0_RTR4_BASE 0x4164000ull
+#define DCORE0_RTR4_MAX_OFFSET 0x1000
+#define DCORE0_RTR4_SECTION 0x3000
+#define mmDCORE0_RTR4_HBW_RD_RQ_LL_STAT_BASE 0x4164300ull
+#define DCORE0_RTR4_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR4_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR4_HBW_RD_RS_LL_STAT_BASE 0x4164340ull
+#define DCORE0_RTR4_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR4_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR4_HBW_WR_RQ_LL_STAT_BASE 0x4164380ull
+#define DCORE0_RTR4_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR4_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR4_HBW_WR_RS_LL_STAT_BASE 0x41643C0ull
+#define DCORE0_RTR4_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR4_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR4_LBW_RD_RQ_LL_STAT_BASE 0x4164400ull
+#define DCORE0_RTR4_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR4_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR4_LBW_RD_RS_LL_STAT_BASE 0x4164440ull
+#define DCORE0_RTR4_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR4_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR4_LBW_WR_RQ_LL_STAT_BASE 0x4164480ull
+#define DCORE0_RTR4_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR4_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR4_LBW_WR_RS_LL_STAT_BASE 0x41644C0ull
+#define DCORE0_RTR4_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR4_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR4_HBW_MFIFO_BASE 0x4164500ull
+#define DCORE0_RTR4_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE0_RTR4_HBW_MFIFO_SECTION 0x4000
+#define mmDCORE0_RTR4_E2E_RD_LL_STAT_BASE 0x4164540ull
+#define DCORE0_RTR4_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR4_E2E_RD_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR4_E2E_WR_LL_STAT_BASE 0x4164580ull
+#define DCORE0_RTR4_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR4_E2E_WR_LL_STAT_SECTION 0x8000
+#define mmDCORE0_RTR4_RTR_HBW_XACT_STAT_BASE 0x4164600ull
+#define DCORE0_RTR4_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR4_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE0_RTR4_RTR_LBW_XACT_STAT_BASE 0x4164680ull
+#define DCORE0_RTR4_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR4_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE0_RTR4_RTR_E2E_XACT_STAT_BASE 0x4164700ull
+#define DCORE0_RTR4_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR4_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define mmDCORE0_RTR4_SPECIAL_BASE 0x4164E80ull
+#define DCORE0_RTR4_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR4_SPECIAL_SECTION 0x1800
+#define mmDCORE0_RTR4_DBG_ADDR_BASE 0x4165000ull
+#define DCORE0_RTR4_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE0_RTR4_DBG_ADDR_SECTION 0xE800
+#define mmDCORE0_RTR4_DBG_ADDR_SPECIAL_BASE 0x4165E80ull
+#define DCORE0_RTR4_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR4_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define mmDCORE0_RTR5_CTRL_BASE 0x4168000ull
+#define DCORE0_RTR5_CTRL_MAX_OFFSET 0x1000
+#define DCORE0_RTR5_CTRL_SECTION 0xE800
+#define mmDCORE0_RTR5_CTRL_SPECIAL_BASE 0x4168E80ull
+#define DCORE0_RTR5_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR5_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE0_RTR5_H3_BASE 0x4169000ull
+#define DCORE0_RTR5_H3_MAX_OFFSET 0x1000
+#define DCORE0_RTR5_H3_SECTION 0xE800
+#define mmDCORE0_RTR5_H3_SPECIAL_BASE 0x4169E80ull
+#define DCORE0_RTR5_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR5_H3_SPECIAL_SECTION 0x1800
+#define mmDCORE0_RTR5_MSTR_IF_RR_SHRD_HBW_BASE 0x416A000ull
+#define DCORE0_RTR5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_RTR5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE0_RTR5_MSTR_IF_RR_PRVT_HBW_BASE 0x416A200ull
+#define DCORE0_RTR5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_RTR5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE0_RTR5_MSTR_IF_RR_SHRD_LBW_BASE 0x416A400ull
+#define DCORE0_RTR5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_RTR5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE0_RTR5_MSTR_IF_RR_PRVT_LBW_BASE 0x416A600ull
+#define DCORE0_RTR5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_RTR5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE0_RTR5_MSTR_IF_E2E_CRDT_BASE 0x416A800ull
+#define DCORE0_RTR5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_RTR5_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE0_RTR5_MSTR_IF_AXUSER_BASE 0x416AA80ull
+#define DCORE0_RTR5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_RTR5_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE0_RTR5_MSTR_IF_DBG_HBW_BASE 0x416AB00ull
+#define DCORE0_RTR5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_RTR5_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_RTR5_MSTR_IF_DBG_LBW_BASE 0x416AB80ull
+#define DCORE0_RTR5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_RTR5_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE0_RTR5_MSTR_IF_CORE_HBW_BASE 0x416AC00ull
+#define DCORE0_RTR5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_RTR5_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE0_RTR5_MSTR_IF_CORE_LBW_BASE 0x416AD80ull
+#define DCORE0_RTR5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_RTR5_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE0_RTR5_MSTR_IF_SPECIAL_BASE 0x416AE80ull
+#define DCORE0_RTR5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR5_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE0_RTR5_ADD_DEC_HBW_BASE 0x416B000ull
+#define DCORE0_RTR5_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE0_RTR5_ADD_DEC_HBW_SECTION 0x4000
+#define mmDCORE0_RTR5_ADD_DEC_LBW_BASE 0x416B400ull
+#define DCORE0_RTR5_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE0_RTR5_ADD_DEC_LBW_SECTION 0xA800
+#define mmDCORE0_RTR5_ADD_DEC_SPECIAL_BASE 0x416BE80ull
+#define DCORE0_RTR5_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR5_ADD_DEC_SPECIAL_SECTION 0x1800
+#define mmDCORE0_RTR5_BASE 0x416C000ull
+#define DCORE0_RTR5_MAX_OFFSET 0x1000
+#define DCORE0_RTR5_SECTION 0x3000
+#define mmDCORE0_RTR5_HBW_RD_RQ_LL_STAT_BASE 0x416C300ull
+#define DCORE0_RTR5_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR5_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR5_HBW_RD_RS_LL_STAT_BASE 0x416C340ull
+#define DCORE0_RTR5_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR5_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR5_HBW_WR_RQ_LL_STAT_BASE 0x416C380ull
+#define DCORE0_RTR5_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR5_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR5_HBW_WR_RS_LL_STAT_BASE 0x416C3C0ull
+#define DCORE0_RTR5_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR5_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR5_LBW_RD_RQ_LL_STAT_BASE 0x416C400ull
+#define DCORE0_RTR5_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR5_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR5_LBW_RD_RS_LL_STAT_BASE 0x416C440ull
+#define DCORE0_RTR5_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR5_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR5_LBW_WR_RQ_LL_STAT_BASE 0x416C480ull
+#define DCORE0_RTR5_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR5_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR5_LBW_WR_RS_LL_STAT_BASE 0x416C4C0ull
+#define DCORE0_RTR5_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR5_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR5_HBW_MFIFO_BASE 0x416C500ull
+#define DCORE0_RTR5_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE0_RTR5_HBW_MFIFO_SECTION 0x4000
+#define mmDCORE0_RTR5_E2E_RD_LL_STAT_BASE 0x416C540ull
+#define DCORE0_RTR5_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR5_E2E_RD_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR5_E2E_WR_LL_STAT_BASE 0x416C580ull
+#define DCORE0_RTR5_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR5_E2E_WR_LL_STAT_SECTION 0x8000
+#define mmDCORE0_RTR5_RTR_HBW_XACT_STAT_BASE 0x416C600ull
+#define DCORE0_RTR5_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR5_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE0_RTR5_RTR_LBW_XACT_STAT_BASE 0x416C680ull
+#define DCORE0_RTR5_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR5_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE0_RTR5_RTR_E2E_XACT_STAT_BASE 0x416C700ull
+#define DCORE0_RTR5_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR5_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define mmDCORE0_RTR5_SPECIAL_BASE 0x416CE80ull
+#define DCORE0_RTR5_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR5_SPECIAL_SECTION 0x1800
+#define mmDCORE0_RTR5_DBG_ADDR_BASE 0x416D000ull
+#define DCORE0_RTR5_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE0_RTR5_DBG_ADDR_SECTION 0xE800
+#define mmDCORE0_RTR5_DBG_ADDR_SPECIAL_BASE 0x416DE80ull
+#define DCORE0_RTR5_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR5_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define mmDCORE0_RTR6_CTRL_BASE 0x4170000ull
+#define DCORE0_RTR6_CTRL_MAX_OFFSET 0x1000
+#define DCORE0_RTR6_CTRL_SECTION 0xE800
+#define mmDCORE0_RTR6_CTRL_SPECIAL_BASE 0x4170E80ull
+#define DCORE0_RTR6_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR6_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE0_RTR6_H3_BASE 0x4171000ull
+#define DCORE0_RTR6_H3_MAX_OFFSET 0x1000
+#define DCORE0_RTR6_H3_SECTION 0xE800
+#define mmDCORE0_RTR6_H3_SPECIAL_BASE 0x4171E80ull
+#define DCORE0_RTR6_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR6_H3_SPECIAL_SECTION 0x1800
+#define mmDCORE0_RTR6_MSTR_IF_RR_SHRD_HBW_BASE 0x4172000ull
+#define DCORE0_RTR6_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_RTR6_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE0_RTR6_MSTR_IF_RR_PRVT_HBW_BASE 0x4172200ull
+#define DCORE0_RTR6_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_RTR6_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE0_RTR6_MSTR_IF_RR_SHRD_LBW_BASE 0x4172400ull
+#define DCORE0_RTR6_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_RTR6_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE0_RTR6_MSTR_IF_RR_PRVT_LBW_BASE 0x4172600ull
+#define DCORE0_RTR6_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_RTR6_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE0_RTR6_MSTR_IF_E2E_CRDT_BASE 0x4172800ull
+#define DCORE0_RTR6_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_RTR6_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE0_RTR6_MSTR_IF_AXUSER_BASE 0x4172A80ull
+#define DCORE0_RTR6_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_RTR6_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE0_RTR6_MSTR_IF_DBG_HBW_BASE 0x4172B00ull
+#define DCORE0_RTR6_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_RTR6_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_RTR6_MSTR_IF_DBG_LBW_BASE 0x4172B80ull
+#define DCORE0_RTR6_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_RTR6_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE0_RTR6_MSTR_IF_CORE_HBW_BASE 0x4172C00ull
+#define DCORE0_RTR6_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_RTR6_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE0_RTR6_MSTR_IF_CORE_LBW_BASE 0x4172D80ull
+#define DCORE0_RTR6_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_RTR6_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE0_RTR6_MSTR_IF_SPECIAL_BASE 0x4172E80ull
+#define DCORE0_RTR6_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR6_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE0_RTR6_ADD_DEC_HBW_BASE 0x4173000ull
+#define DCORE0_RTR6_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE0_RTR6_ADD_DEC_HBW_SECTION 0x4000
+#define mmDCORE0_RTR6_ADD_DEC_LBW_BASE 0x4173400ull
+#define DCORE0_RTR6_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE0_RTR6_ADD_DEC_LBW_SECTION 0xA800
+#define mmDCORE0_RTR6_ADD_DEC_SPECIAL_BASE 0x4173E80ull
+#define DCORE0_RTR6_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR6_ADD_DEC_SPECIAL_SECTION 0x1800
+#define mmDCORE0_RTR6_BASE 0x4174000ull
+#define DCORE0_RTR6_MAX_OFFSET 0x1000
+#define DCORE0_RTR6_SECTION 0x3000
+#define mmDCORE0_RTR6_HBW_RD_RQ_LL_STAT_BASE 0x4174300ull
+#define DCORE0_RTR6_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR6_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR6_HBW_RD_RS_LL_STAT_BASE 0x4174340ull
+#define DCORE0_RTR6_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR6_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR6_HBW_WR_RQ_LL_STAT_BASE 0x4174380ull
+#define DCORE0_RTR6_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR6_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR6_HBW_WR_RS_LL_STAT_BASE 0x41743C0ull
+#define DCORE0_RTR6_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR6_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR6_LBW_RD_RQ_LL_STAT_BASE 0x4174400ull
+#define DCORE0_RTR6_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR6_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR6_LBW_RD_RS_LL_STAT_BASE 0x4174440ull
+#define DCORE0_RTR6_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR6_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR6_LBW_WR_RQ_LL_STAT_BASE 0x4174480ull
+#define DCORE0_RTR6_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR6_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR6_LBW_WR_RS_LL_STAT_BASE 0x41744C0ull
+#define DCORE0_RTR6_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR6_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR6_HBW_MFIFO_BASE 0x4174500ull
+#define DCORE0_RTR6_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE0_RTR6_HBW_MFIFO_SECTION 0x4000
+#define mmDCORE0_RTR6_E2E_RD_LL_STAT_BASE 0x4174540ull
+#define DCORE0_RTR6_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR6_E2E_RD_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR6_E2E_WR_LL_STAT_BASE 0x4174580ull
+#define DCORE0_RTR6_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR6_E2E_WR_LL_STAT_SECTION 0x8000
+#define mmDCORE0_RTR6_RTR_HBW_XACT_STAT_BASE 0x4174600ull
+#define DCORE0_RTR6_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR6_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE0_RTR6_RTR_LBW_XACT_STAT_BASE 0x4174680ull
+#define DCORE0_RTR6_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR6_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE0_RTR6_RTR_E2E_XACT_STAT_BASE 0x4174700ull
+#define DCORE0_RTR6_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR6_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define mmDCORE0_RTR6_SPECIAL_BASE 0x4174E80ull
+#define DCORE0_RTR6_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR6_SPECIAL_SECTION 0x1800
+#define mmDCORE0_RTR6_DBG_ADDR_BASE 0x4175000ull
+#define DCORE0_RTR6_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE0_RTR6_DBG_ADDR_SECTION 0xE800
+#define mmDCORE0_RTR6_DBG_ADDR_SPECIAL_BASE 0x4175E80ull
+#define DCORE0_RTR6_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR6_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define mmDCORE0_RTR7_CTRL_BASE 0x4178000ull
+#define DCORE0_RTR7_CTRL_MAX_OFFSET 0x1000
+#define DCORE0_RTR7_CTRL_SECTION 0xE800
+#define mmDCORE0_RTR7_CTRL_SPECIAL_BASE 0x4178E80ull
+#define DCORE0_RTR7_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR7_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE0_RTR7_H3_BASE 0x4179000ull
+#define DCORE0_RTR7_H3_MAX_OFFSET 0x1000
+#define DCORE0_RTR7_H3_SECTION 0xE800
+#define mmDCORE0_RTR7_H3_SPECIAL_BASE 0x4179E80ull
+#define DCORE0_RTR7_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR7_H3_SPECIAL_SECTION 0x1800
+#define mmDCORE0_RTR7_MSTR_IF_RR_SHRD_HBW_BASE 0x417A000ull
+#define DCORE0_RTR7_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_RTR7_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE0_RTR7_MSTR_IF_RR_PRVT_HBW_BASE 0x417A200ull
+#define DCORE0_RTR7_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_RTR7_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE0_RTR7_MSTR_IF_RR_SHRD_LBW_BASE 0x417A400ull
+#define DCORE0_RTR7_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_RTR7_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE0_RTR7_MSTR_IF_RR_PRVT_LBW_BASE 0x417A600ull
+#define DCORE0_RTR7_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_RTR7_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE0_RTR7_MSTR_IF_E2E_CRDT_BASE 0x417A800ull
+#define DCORE0_RTR7_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_RTR7_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE0_RTR7_MSTR_IF_AXUSER_BASE 0x417AA80ull
+#define DCORE0_RTR7_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_RTR7_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE0_RTR7_MSTR_IF_DBG_HBW_BASE 0x417AB00ull
+#define DCORE0_RTR7_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_RTR7_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_RTR7_MSTR_IF_DBG_LBW_BASE 0x417AB80ull
+#define DCORE0_RTR7_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_RTR7_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE0_RTR7_MSTR_IF_CORE_HBW_BASE 0x417AC00ull
+#define DCORE0_RTR7_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_RTR7_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE0_RTR7_MSTR_IF_CORE_LBW_BASE 0x417AD80ull
+#define DCORE0_RTR7_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_RTR7_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE0_RTR7_MSTR_IF_SPECIAL_BASE 0x417AE80ull
+#define DCORE0_RTR7_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR7_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE0_RTR7_ADD_DEC_HBW_BASE 0x417B000ull
+#define DCORE0_RTR7_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE0_RTR7_ADD_DEC_HBW_SECTION 0x4000
+#define mmDCORE0_RTR7_ADD_DEC_LBW_BASE 0x417B400ull
+#define DCORE0_RTR7_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE0_RTR7_ADD_DEC_LBW_SECTION 0xA800
+#define mmDCORE0_RTR7_ADD_DEC_SPECIAL_BASE 0x417BE80ull
+#define DCORE0_RTR7_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR7_ADD_DEC_SPECIAL_SECTION 0x1800
+#define mmDCORE0_RTR7_BASE 0x417C000ull
+#define DCORE0_RTR7_MAX_OFFSET 0x1000
+#define DCORE0_RTR7_SECTION 0x3000
+#define mmDCORE0_RTR7_HBW_RD_RQ_LL_STAT_BASE 0x417C300ull
+#define DCORE0_RTR7_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR7_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR7_HBW_RD_RS_LL_STAT_BASE 0x417C340ull
+#define DCORE0_RTR7_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR7_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR7_HBW_WR_RQ_LL_STAT_BASE 0x417C380ull
+#define DCORE0_RTR7_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR7_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR7_HBW_WR_RS_LL_STAT_BASE 0x417C3C0ull
+#define DCORE0_RTR7_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR7_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR7_LBW_RD_RQ_LL_STAT_BASE 0x417C400ull
+#define DCORE0_RTR7_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR7_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR7_LBW_RD_RS_LL_STAT_BASE 0x417C440ull
+#define DCORE0_RTR7_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR7_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR7_LBW_WR_RQ_LL_STAT_BASE 0x417C480ull
+#define DCORE0_RTR7_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR7_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR7_LBW_WR_RS_LL_STAT_BASE 0x417C4C0ull
+#define DCORE0_RTR7_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR7_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR7_HBW_MFIFO_BASE 0x417C500ull
+#define DCORE0_RTR7_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE0_RTR7_HBW_MFIFO_SECTION 0x4000
+#define mmDCORE0_RTR7_E2E_RD_LL_STAT_BASE 0x417C540ull
+#define DCORE0_RTR7_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR7_E2E_RD_LL_STAT_SECTION 0x4000
+#define mmDCORE0_RTR7_E2E_WR_LL_STAT_BASE 0x417C580ull
+#define DCORE0_RTR7_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE0_RTR7_E2E_WR_LL_STAT_SECTION 0x8000
+#define mmDCORE0_RTR7_RTR_HBW_XACT_STAT_BASE 0x417C600ull
+#define DCORE0_RTR7_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR7_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE0_RTR7_RTR_LBW_XACT_STAT_BASE 0x417C680ull
+#define DCORE0_RTR7_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR7_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE0_RTR7_RTR_E2E_XACT_STAT_BASE 0x417C700ull
+#define DCORE0_RTR7_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE0_RTR7_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define mmDCORE0_RTR7_SPECIAL_BASE 0x417CE80ull
+#define DCORE0_RTR7_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR7_SPECIAL_SECTION 0x1800
+#define mmDCORE0_RTR7_DBG_ADDR_BASE 0x417D000ull
+#define DCORE0_RTR7_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE0_RTR7_DBG_ADDR_SECTION 0xE800
+#define mmDCORE0_RTR7_DBG_ADDR_SPECIAL_BASE 0x417DE80ull
+#define DCORE0_RTR7_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_RTR7_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define mmDCORE0_SRAM0_BANK_BASE 0x4180000ull
+#define DCORE0_SRAM0_BANK_MAX_OFFSET 0x1000
+#define DCORE0_SRAM0_BANK_SECTION 0xE800
+#define mmDCORE0_SRAM0_BANK_SPECIAL_BASE 0x4180E80ull
+#define DCORE0_SRAM0_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM0_BANK_SPECIAL_SECTION 0x1800
+#define mmDCORE0_SRAM0_RTR_BASE 0x4181000ull
+#define DCORE0_SRAM0_RTR_MAX_OFFSET 0x1000
+#define DCORE0_SRAM0_RTR_SECTION 0xE800
+#define mmDCORE0_SRAM0_RTR_SPECIAL_BASE 0x4181E80ull
+#define DCORE0_SRAM0_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM0_RTR_SPECIAL_SECTION 0x1800
+#define mmDCORE0_SRAM0_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4182000ull
+#define DCORE0_SRAM0_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM0_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM0_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4182100ull
+#define DCORE0_SRAM0_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM0_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4182200ull
+#define DCORE0_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4182300ull
+#define DCORE0_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM0_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4182400ull
+#define DCORE0_SRAM0_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM0_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM0_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4182500ull
+#define DCORE0_SRAM0_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM0_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM0_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4182600ull
+#define DCORE0_SRAM0_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM0_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4182700ull
+#define DCORE0_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4182780ull
+#define DCORE0_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4182800ull
+#define DCORE0_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4182880ull
+#define DCORE0_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4182900ull
+#define DCORE0_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4182980ull
+#define DCORE0_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4182A00ull
+#define DCORE0_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4182A80ull
+#define DCORE0_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define mmDCORE0_SRAM0_DBG_CNT_SPECIAL_BASE 0x4182E80ull
+#define DCORE0_SRAM0_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM0_DBG_CNT_SPECIAL_SECTION 0x5180
+#define mmDCORE0_SRAM1_BANK_BASE 0x4188000ull
+#define DCORE0_SRAM1_BANK_MAX_OFFSET 0x1000
+#define DCORE0_SRAM1_BANK_SECTION 0xE800
+#define mmDCORE0_SRAM1_BANK_SPECIAL_BASE 0x4188E80ull
+#define DCORE0_SRAM1_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM1_BANK_SPECIAL_SECTION 0x1800
+#define mmDCORE0_SRAM1_RTR_BASE 0x4189000ull
+#define DCORE0_SRAM1_RTR_MAX_OFFSET 0x1000
+#define DCORE0_SRAM1_RTR_SECTION 0xE800
+#define mmDCORE0_SRAM1_RTR_SPECIAL_BASE 0x4189E80ull
+#define DCORE0_SRAM1_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM1_RTR_SPECIAL_SECTION 0x1800
+#define mmDCORE0_SRAM1_DBG_CNT_N_HBW_DBG_CNT_BASE 0x418A000ull
+#define DCORE0_SRAM1_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM1_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM1_DBG_CNT_S_HBW_DBG_CNT_BASE 0x418A100ull
+#define DCORE0_SRAM1_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM1_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x418A200ull
+#define DCORE0_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x418A300ull
+#define DCORE0_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM1_DBG_CNT_N_LBW_DBG_CNT_BASE 0x418A400ull
+#define DCORE0_SRAM1_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM1_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM1_DBG_CNT_S_LBW_DBG_CNT_BASE 0x418A500ull
+#define DCORE0_SRAM1_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM1_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM1_DBG_CNT_L_LBW_DBG_CNT_BASE 0x418A600ull
+#define DCORE0_SRAM1_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM1_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x418A700ull
+#define DCORE0_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x418A780ull
+#define DCORE0_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x418A800ull
+#define DCORE0_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x418A880ull
+#define DCORE0_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x418A900ull
+#define DCORE0_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x418A980ull
+#define DCORE0_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x418AA00ull
+#define DCORE0_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x418AA80ull
+#define DCORE0_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define mmDCORE0_SRAM1_DBG_CNT_SPECIAL_BASE 0x418AE80ull
+#define DCORE0_SRAM1_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM1_DBG_CNT_SPECIAL_SECTION 0x5180
+#define mmDCORE0_SRAM2_BANK_BASE 0x4190000ull
+#define DCORE0_SRAM2_BANK_MAX_OFFSET 0x1000
+#define DCORE0_SRAM2_BANK_SECTION 0xE800
+#define mmDCORE0_SRAM2_BANK_SPECIAL_BASE 0x4190E80ull
+#define DCORE0_SRAM2_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM2_BANK_SPECIAL_SECTION 0x1800
+#define mmDCORE0_SRAM2_RTR_BASE 0x4191000ull
+#define DCORE0_SRAM2_RTR_MAX_OFFSET 0x1000
+#define DCORE0_SRAM2_RTR_SECTION 0xE800
+#define mmDCORE0_SRAM2_RTR_SPECIAL_BASE 0x4191E80ull
+#define DCORE0_SRAM2_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM2_RTR_SPECIAL_SECTION 0x1800
+#define mmDCORE0_SRAM2_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4192000ull
+#define DCORE0_SRAM2_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM2_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM2_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4192100ull
+#define DCORE0_SRAM2_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM2_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4192200ull
+#define DCORE0_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4192300ull
+#define DCORE0_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM2_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4192400ull
+#define DCORE0_SRAM2_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM2_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM2_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4192500ull
+#define DCORE0_SRAM2_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM2_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM2_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4192600ull
+#define DCORE0_SRAM2_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM2_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4192700ull
+#define DCORE0_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4192780ull
+#define DCORE0_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4192800ull
+#define DCORE0_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4192880ull
+#define DCORE0_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4192900ull
+#define DCORE0_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4192980ull
+#define DCORE0_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4192A00ull
+#define DCORE0_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4192A80ull
+#define DCORE0_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define mmDCORE0_SRAM2_DBG_CNT_SPECIAL_BASE 0x4192E80ull
+#define DCORE0_SRAM2_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM2_DBG_CNT_SPECIAL_SECTION 0x5180
+#define mmDCORE0_SRAM3_BANK_BASE 0x4198000ull
+#define DCORE0_SRAM3_BANK_MAX_OFFSET 0x1000
+#define DCORE0_SRAM3_BANK_SECTION 0xE800
+#define mmDCORE0_SRAM3_BANK_SPECIAL_BASE 0x4198E80ull
+#define DCORE0_SRAM3_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM3_BANK_SPECIAL_SECTION 0x1800
+#define mmDCORE0_SRAM3_RTR_BASE 0x4199000ull
+#define DCORE0_SRAM3_RTR_MAX_OFFSET 0x1000
+#define DCORE0_SRAM3_RTR_SECTION 0xE800
+#define mmDCORE0_SRAM3_RTR_SPECIAL_BASE 0x4199E80ull
+#define DCORE0_SRAM3_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM3_RTR_SPECIAL_SECTION 0x1800
+#define mmDCORE0_SRAM3_DBG_CNT_N_HBW_DBG_CNT_BASE 0x419A000ull
+#define DCORE0_SRAM3_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM3_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM3_DBG_CNT_S_HBW_DBG_CNT_BASE 0x419A100ull
+#define DCORE0_SRAM3_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM3_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x419A200ull
+#define DCORE0_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x419A300ull
+#define DCORE0_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM3_DBG_CNT_N_LBW_DBG_CNT_BASE 0x419A400ull
+#define DCORE0_SRAM3_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM3_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM3_DBG_CNT_S_LBW_DBG_CNT_BASE 0x419A500ull
+#define DCORE0_SRAM3_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM3_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM3_DBG_CNT_L_LBW_DBG_CNT_BASE 0x419A600ull
+#define DCORE0_SRAM3_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM3_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x419A700ull
+#define DCORE0_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x419A780ull
+#define DCORE0_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x419A800ull
+#define DCORE0_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x419A880ull
+#define DCORE0_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x419A900ull
+#define DCORE0_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x419A980ull
+#define DCORE0_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x419AA00ull
+#define DCORE0_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x419AA80ull
+#define DCORE0_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define mmDCORE0_SRAM3_DBG_CNT_SPECIAL_BASE 0x419AE80ull
+#define DCORE0_SRAM3_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM3_DBG_CNT_SPECIAL_SECTION 0x5180
+#define mmDCORE0_SRAM4_BANK_BASE 0x41A0000ull
+#define DCORE0_SRAM4_BANK_MAX_OFFSET 0x1000
+#define DCORE0_SRAM4_BANK_SECTION 0xE800
+#define mmDCORE0_SRAM4_BANK_SPECIAL_BASE 0x41A0E80ull
+#define DCORE0_SRAM4_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM4_BANK_SPECIAL_SECTION 0x1800
+#define mmDCORE0_SRAM4_RTR_BASE 0x41A1000ull
+#define DCORE0_SRAM4_RTR_MAX_OFFSET 0x1000
+#define DCORE0_SRAM4_RTR_SECTION 0xE800
+#define mmDCORE0_SRAM4_RTR_SPECIAL_BASE 0x41A1E80ull
+#define DCORE0_SRAM4_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM4_RTR_SPECIAL_SECTION 0x1800
+#define mmDCORE0_SRAM4_DBG_CNT_N_HBW_DBG_CNT_BASE 0x41A2000ull
+#define DCORE0_SRAM4_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM4_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM4_DBG_CNT_S_HBW_DBG_CNT_BASE 0x41A2100ull
+#define DCORE0_SRAM4_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM4_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x41A2200ull
+#define DCORE0_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x41A2300ull
+#define DCORE0_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM4_DBG_CNT_N_LBW_DBG_CNT_BASE 0x41A2400ull
+#define DCORE0_SRAM4_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM4_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM4_DBG_CNT_S_LBW_DBG_CNT_BASE 0x41A2500ull
+#define DCORE0_SRAM4_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM4_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM4_DBG_CNT_L_LBW_DBG_CNT_BASE 0x41A2600ull
+#define DCORE0_SRAM4_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM4_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x41A2700ull
+#define DCORE0_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x41A2780ull
+#define DCORE0_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x41A2800ull
+#define DCORE0_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x41A2880ull
+#define DCORE0_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x41A2900ull
+#define DCORE0_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x41A2980ull
+#define DCORE0_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x41A2A00ull
+#define DCORE0_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x41A2A80ull
+#define DCORE0_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define mmDCORE0_SRAM4_DBG_CNT_SPECIAL_BASE 0x41A2E80ull
+#define DCORE0_SRAM4_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM4_DBG_CNT_SPECIAL_SECTION 0x5180
+#define mmDCORE0_SRAM5_BANK_BASE 0x41A8000ull
+#define DCORE0_SRAM5_BANK_MAX_OFFSET 0x1000
+#define DCORE0_SRAM5_BANK_SECTION 0xE800
+#define mmDCORE0_SRAM5_BANK_SPECIAL_BASE 0x41A8E80ull
+#define DCORE0_SRAM5_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM5_BANK_SPECIAL_SECTION 0x1800
+#define mmDCORE0_SRAM5_RTR_BASE 0x41A9000ull
+#define DCORE0_SRAM5_RTR_MAX_OFFSET 0x1000
+#define DCORE0_SRAM5_RTR_SECTION 0xE800
+#define mmDCORE0_SRAM5_RTR_SPECIAL_BASE 0x41A9E80ull
+#define DCORE0_SRAM5_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM5_RTR_SPECIAL_SECTION 0x1800
+#define mmDCORE0_SRAM5_DBG_CNT_N_HBW_DBG_CNT_BASE 0x41AA000ull
+#define DCORE0_SRAM5_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM5_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM5_DBG_CNT_S_HBW_DBG_CNT_BASE 0x41AA100ull
+#define DCORE0_SRAM5_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM5_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x41AA200ull
+#define DCORE0_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x41AA300ull
+#define DCORE0_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM5_DBG_CNT_N_LBW_DBG_CNT_BASE 0x41AA400ull
+#define DCORE0_SRAM5_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM5_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM5_DBG_CNT_S_LBW_DBG_CNT_BASE 0x41AA500ull
+#define DCORE0_SRAM5_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM5_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM5_DBG_CNT_L_LBW_DBG_CNT_BASE 0x41AA600ull
+#define DCORE0_SRAM5_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM5_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x41AA700ull
+#define DCORE0_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x41AA780ull
+#define DCORE0_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x41AA800ull
+#define DCORE0_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x41AA880ull
+#define DCORE0_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x41AA900ull
+#define DCORE0_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x41AA980ull
+#define DCORE0_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x41AAA00ull
+#define DCORE0_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x41AAA80ull
+#define DCORE0_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define mmDCORE0_SRAM5_DBG_CNT_SPECIAL_BASE 0x41AAE80ull
+#define DCORE0_SRAM5_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM5_DBG_CNT_SPECIAL_SECTION 0x5180
+#define mmDCORE0_SRAM6_BANK_BASE 0x41B0000ull
+#define DCORE0_SRAM6_BANK_MAX_OFFSET 0x1000
+#define DCORE0_SRAM6_BANK_SECTION 0xE800
+#define mmDCORE0_SRAM6_BANK_SPECIAL_BASE 0x41B0E80ull
+#define DCORE0_SRAM6_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM6_BANK_SPECIAL_SECTION 0x1800
+#define mmDCORE0_SRAM6_RTR_BASE 0x41B1000ull
+#define DCORE0_SRAM6_RTR_MAX_OFFSET 0x1000
+#define DCORE0_SRAM6_RTR_SECTION 0xE800
+#define mmDCORE0_SRAM6_RTR_SPECIAL_BASE 0x41B1E80ull
+#define DCORE0_SRAM6_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM6_RTR_SPECIAL_SECTION 0x1800
+#define mmDCORE0_SRAM6_DBG_CNT_N_HBW_DBG_CNT_BASE 0x41B2000ull
+#define DCORE0_SRAM6_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM6_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM6_DBG_CNT_S_HBW_DBG_CNT_BASE 0x41B2100ull
+#define DCORE0_SRAM6_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM6_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x41B2200ull
+#define DCORE0_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x41B2300ull
+#define DCORE0_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM6_DBG_CNT_N_LBW_DBG_CNT_BASE 0x41B2400ull
+#define DCORE0_SRAM6_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM6_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM6_DBG_CNT_S_LBW_DBG_CNT_BASE 0x41B2500ull
+#define DCORE0_SRAM6_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM6_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM6_DBG_CNT_L_LBW_DBG_CNT_BASE 0x41B2600ull
+#define DCORE0_SRAM6_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM6_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x41B2700ull
+#define DCORE0_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x41B2780ull
+#define DCORE0_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x41B2800ull
+#define DCORE0_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x41B2880ull
+#define DCORE0_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x41B2900ull
+#define DCORE0_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x41B2980ull
+#define DCORE0_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x41B2A00ull
+#define DCORE0_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x41B2A80ull
+#define DCORE0_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define mmDCORE0_SRAM6_DBG_CNT_SPECIAL_BASE 0x41B2E80ull
+#define DCORE0_SRAM6_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM6_DBG_CNT_SPECIAL_SECTION 0x5180
+#define mmDCORE0_SRAM7_BANK_BASE 0x41B8000ull
+#define DCORE0_SRAM7_BANK_MAX_OFFSET 0x1000
+#define DCORE0_SRAM7_BANK_SECTION 0xE800
+#define mmDCORE0_SRAM7_BANK_SPECIAL_BASE 0x41B8E80ull
+#define DCORE0_SRAM7_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM7_BANK_SPECIAL_SECTION 0x1800
+#define mmDCORE0_SRAM7_RTR_BASE 0x41B9000ull
+#define DCORE0_SRAM7_RTR_MAX_OFFSET 0x1000
+#define DCORE0_SRAM7_RTR_SECTION 0xE800
+#define mmDCORE0_SRAM7_RTR_SPECIAL_BASE 0x41B9E80ull
+#define DCORE0_SRAM7_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM7_RTR_SPECIAL_SECTION 0x1800
+#define mmDCORE0_SRAM7_DBG_CNT_N_HBW_DBG_CNT_BASE 0x41BA000ull
+#define DCORE0_SRAM7_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM7_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM7_DBG_CNT_S_HBW_DBG_CNT_BASE 0x41BA100ull
+#define DCORE0_SRAM7_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM7_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x41BA200ull
+#define DCORE0_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x41BA300ull
+#define DCORE0_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM7_DBG_CNT_N_LBW_DBG_CNT_BASE 0x41BA400ull
+#define DCORE0_SRAM7_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM7_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM7_DBG_CNT_S_LBW_DBG_CNT_BASE 0x41BA500ull
+#define DCORE0_SRAM7_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM7_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM7_DBG_CNT_L_LBW_DBG_CNT_BASE 0x41BA600ull
+#define DCORE0_SRAM7_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE0_SRAM7_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE0_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x41BA700ull
+#define DCORE0_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x41BA780ull
+#define DCORE0_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x41BA800ull
+#define DCORE0_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x41BA880ull
+#define DCORE0_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x41BA900ull
+#define DCORE0_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x41BA980ull
+#define DCORE0_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x41BAA00ull
+#define DCORE0_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE0_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x41BAA80ull
+#define DCORE0_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE0_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define mmDCORE0_SRAM7_DBG_CNT_SPECIAL_BASE 0x41BAE80ull
+#define DCORE0_SRAM7_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_SRAM7_DBG_CNT_SPECIAL_SECTION 0x5180
+#define mmDCORE0_EDMA0_QM_DCCM_BASE 0x41C0000ull
+#define DCORE0_EDMA0_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE0_EDMA0_QM_DCCM_SECTION 0x8000
+#define mmDCORE0_EDMA0_QM_ARC_AUX_BASE 0x41C8000ull
+#define DCORE0_EDMA0_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE0_EDMA0_QM_ARC_AUX_SECTION 0xE800
+#define mmDCORE0_EDMA0_QM_ARC_AUX_SPECIAL_BASE 0x41C8E80ull
+#define DCORE0_EDMA0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_EDMA0_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define mmDCORE0_EDMA0_QM_BASE 0x41CA000ull
+#define DCORE0_EDMA0_QM_MAX_OFFSET 0x1000
+#define DCORE0_EDMA0_QM_SECTION 0x9000
+#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x41CA900ull
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x41CA908ull
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x41CA910ull
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x41CA918ull
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x41CA920ull
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x41CA928ull
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x41CA930ull
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x41CA938ull
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x41CA940ull
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x41CA948ull
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x41CA950ull
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x41CA958ull
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x41CA960ull
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x41CA968ull
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x41CA970ull
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x41CA978ull
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE0_EDMA0_QM_AXUSER_SECURED_BASE 0x41CAB00ull
+#define DCORE0_EDMA0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE0_EDMA0_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_BASE 0x41CAB80ull
+#define DCORE0_EDMA0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE0_EDMA0_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE0_EDMA0_QM_DBG_HBW_BASE 0x41CAC00ull
+#define DCORE0_EDMA0_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_EDMA0_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_EDMA0_QM_DBG_LBW_BASE 0x41CAC80ull
+#define DCORE0_EDMA0_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_EDMA0_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE0_EDMA0_QM_CGM_BASE 0x41CAD80ull
+#define DCORE0_EDMA0_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE0_EDMA0_QM_CGM_SECTION 0x1000
+#define mmDCORE0_EDMA0_QM_SPECIAL_BASE 0x41CAE80ull
+#define DCORE0_EDMA0_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_EDMA0_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE0_EDMA0_CORE_BASE 0x41CB000ull
+#define DCORE0_EDMA0_CORE_MAX_OFFSET 0x1000
+#define DCORE0_EDMA0_CORE_SECTION 0x8000
+#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_BASE 0x41CB800ull
+#define DCORE0_EDMA0_CORE_CTX_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_EDMA0_CORE_CTX_AXUSER_SECTION 0x6000
+#define mmDCORE0_EDMA0_CORE_CTX_BASE 0x41CB860ull
+#define DCORE0_EDMA0_CORE_CTX_MAX_OFFSET 0x9000
+#define DCORE0_EDMA0_CORE_CTX_SECTION 0x5A00
+#define mmDCORE0_EDMA0_CORE_KDMA_CGM_BASE 0x41CBE00ull
+#define DCORE0_EDMA0_CORE_KDMA_CGM_MAX_OFFSET 0xC000
+#define DCORE0_EDMA0_CORE_KDMA_CGM_SECTION 0x8000
+#define mmDCORE0_EDMA0_CORE_SPECIAL_BASE 0x41CBE80ull
+#define DCORE0_EDMA0_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_EDMA0_CORE_SPECIAL_SECTION 0x1800
+#define mmDCORE0_EDMA0_MSTR_IF_RR_SHRD_HBW_BASE 0x41CC000ull
+#define DCORE0_EDMA0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_EDMA0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE0_EDMA0_MSTR_IF_RR_PRVT_HBW_BASE 0x41CC200ull
+#define DCORE0_EDMA0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_EDMA0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE0_EDMA0_MSTR_IF_RR_SHRD_LBW_BASE 0x41CC400ull
+#define DCORE0_EDMA0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_EDMA0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE0_EDMA0_MSTR_IF_RR_PRVT_LBW_BASE 0x41CC600ull
+#define DCORE0_EDMA0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_EDMA0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE0_EDMA0_MSTR_IF_E2E_CRDT_BASE 0x41CC800ull
+#define DCORE0_EDMA0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_EDMA0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE0_EDMA0_MSTR_IF_AXUSER_BASE 0x41CCA80ull
+#define DCORE0_EDMA0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_EDMA0_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE0_EDMA0_MSTR_IF_DBG_HBW_BASE 0x41CCB00ull
+#define DCORE0_EDMA0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_EDMA0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_EDMA0_MSTR_IF_DBG_LBW_BASE 0x41CCB80ull
+#define DCORE0_EDMA0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_EDMA0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE0_EDMA0_MSTR_IF_CORE_HBW_BASE 0x41CCC00ull
+#define DCORE0_EDMA0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_EDMA0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE0_EDMA0_MSTR_IF_CORE_LBW_BASE 0x41CCD80ull
+#define DCORE0_EDMA0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_EDMA0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE0_EDMA0_MSTR_IF_SPECIAL_BASE 0x41CCE80ull
+#define DCORE0_EDMA0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_EDMA0_MSTR_IF_SPECIAL_SECTION 0x3180
+#define mmDCORE0_EDMA1_QM_DCCM_BASE 0x41D0000ull
+#define DCORE0_EDMA1_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE0_EDMA1_QM_DCCM_SECTION 0x8000
+#define mmDCORE0_EDMA1_QM_ARC_AUX_BASE 0x41D8000ull
+#define DCORE0_EDMA1_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE0_EDMA1_QM_ARC_AUX_SECTION 0xE800
+#define mmDCORE0_EDMA1_QM_ARC_AUX_SPECIAL_BASE 0x41D8E80ull
+#define DCORE0_EDMA1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_EDMA1_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define mmDCORE0_EDMA1_QM_BASE 0x41DA000ull
+#define DCORE0_EDMA1_QM_MAX_OFFSET 0x1000
+#define DCORE0_EDMA1_QM_SECTION 0x9000
+#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x41DA900ull
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x41DA908ull
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x41DA910ull
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x41DA918ull
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x41DA920ull
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x41DA928ull
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x41DA930ull
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x41DA938ull
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x41DA940ull
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x41DA948ull
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x41DA950ull
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x41DA958ull
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x41DA960ull
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x41DA968ull
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x41DA970ull
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x41DA978ull
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE0_EDMA1_QM_AXUSER_SECURED_BASE 0x41DAB00ull
+#define DCORE0_EDMA1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE0_EDMA1_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_BASE 0x41DAB80ull
+#define DCORE0_EDMA1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE0_EDMA1_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE0_EDMA1_QM_DBG_HBW_BASE 0x41DAC00ull
+#define DCORE0_EDMA1_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_EDMA1_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_EDMA1_QM_DBG_LBW_BASE 0x41DAC80ull
+#define DCORE0_EDMA1_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_EDMA1_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE0_EDMA1_QM_CGM_BASE 0x41DAD80ull
+#define DCORE0_EDMA1_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE0_EDMA1_QM_CGM_SECTION 0x1000
+#define mmDCORE0_EDMA1_QM_SPECIAL_BASE 0x41DAE80ull
+#define DCORE0_EDMA1_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_EDMA1_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE0_EDMA1_CORE_BASE 0x41DB000ull
+#define DCORE0_EDMA1_CORE_MAX_OFFSET 0x1000
+#define DCORE0_EDMA1_CORE_SECTION 0x8000
+#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_BASE 0x41DB800ull
+#define DCORE0_EDMA1_CORE_CTX_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_EDMA1_CORE_CTX_AXUSER_SECTION 0x6000
+#define mmDCORE0_EDMA1_CORE_CTX_BASE 0x41DB860ull
+#define DCORE0_EDMA1_CORE_CTX_MAX_OFFSET 0x9000
+#define DCORE0_EDMA1_CORE_CTX_SECTION 0x5A00
+#define mmDCORE0_EDMA1_CORE_KDMA_CGM_BASE 0x41DBE00ull
+#define DCORE0_EDMA1_CORE_KDMA_CGM_MAX_OFFSET 0xC000
+#define DCORE0_EDMA1_CORE_KDMA_CGM_SECTION 0x8000
+#define mmDCORE0_EDMA1_CORE_SPECIAL_BASE 0x41DBE80ull
+#define DCORE0_EDMA1_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_EDMA1_CORE_SPECIAL_SECTION 0x1800
+#define mmDCORE0_EDMA1_MSTR_IF_RR_SHRD_HBW_BASE 0x41DC000ull
+#define DCORE0_EDMA1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_EDMA1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE0_EDMA1_MSTR_IF_RR_PRVT_HBW_BASE 0x41DC200ull
+#define DCORE0_EDMA1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_EDMA1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE0_EDMA1_MSTR_IF_RR_SHRD_LBW_BASE 0x41DC400ull
+#define DCORE0_EDMA1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_EDMA1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE0_EDMA1_MSTR_IF_RR_PRVT_LBW_BASE 0x41DC600ull
+#define DCORE0_EDMA1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_EDMA1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE0_EDMA1_MSTR_IF_E2E_CRDT_BASE 0x41DC800ull
+#define DCORE0_EDMA1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_EDMA1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE0_EDMA1_MSTR_IF_AXUSER_BASE 0x41DCA80ull
+#define DCORE0_EDMA1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_EDMA1_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE0_EDMA1_MSTR_IF_DBG_HBW_BASE 0x41DCB00ull
+#define DCORE0_EDMA1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_EDMA1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_EDMA1_MSTR_IF_DBG_LBW_BASE 0x41DCB80ull
+#define DCORE0_EDMA1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_EDMA1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE0_EDMA1_MSTR_IF_CORE_HBW_BASE 0x41DCC00ull
+#define DCORE0_EDMA1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_EDMA1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE0_EDMA1_MSTR_IF_CORE_LBW_BASE 0x41DCD80ull
+#define DCORE0_EDMA1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_EDMA1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE0_EDMA1_MSTR_IF_SPECIAL_BASE 0x41DCE80ull
+#define DCORE0_EDMA1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_EDMA1_MSTR_IF_SPECIAL_SECTION 0x3180
+#define mmDCORE0_DEC0_CMD_BASE 0x41E0000ull
+#define DCORE0_DEC0_CMD_MAX_OFFSET 0x1100
+#define DCORE0_DEC0_CMD_SECTION 0x1000
+#define mmDCORE0_DEC0_VSI_BASE 0x41E1000ull
+#define DCORE0_DEC0_VSI_MAX_OFFSET 0x6FC0
+#define DCORE0_DEC0_VSI_SECTION 0x1000
+#define mmDCORE0_DEC0_L2C_BASE 0x41E2000ull
+#define DCORE0_DEC0_L2C_MAX_OFFSET 0x39C0
+#define DCORE0_DEC0_L2C_SECTION 0x1000
+#define mmDCORE0_VDEC0_BRDG_CTRL_BASE 0x41E3000ull
+#define DCORE0_VDEC0_BRDG_CTRL_MAX_OFFSET 0x1000
+#define DCORE0_VDEC0_BRDG_CTRL_SECTION 0x8000
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x41E3800ull
+#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000
+#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x41E3900ull
+#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000
+#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x41E3A00ull
+#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000
+#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x41E3B00ull
+#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000
+#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000
+#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_BASE 0x41E3C00ull
+#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000
+#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800
+#define mmDCORE0_VDEC0_BRDG_CTRL_SPECIAL_BASE 0x41E3E80ull
+#define DCORE0_VDEC0_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_VDEC0_BRDG_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE0_VDEC0_CTRL_BASE 0x41E4000ull
+#define DCORE0_VDEC0_CTRL_MAX_OFFSET 0x1000
+#define DCORE0_VDEC0_CTRL_SECTION 0xE800
+#define mmDCORE0_VDEC0_CTRL_SPECIAL_BASE 0x41E4E80ull
+#define DCORE0_VDEC0_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_VDEC0_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE0_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE 0x41E5000ull
+#define DCORE0_VDEC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_VDEC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE0_VDEC0_MSTR_IF_RR_PRVT_HBW_BASE 0x41E5200ull
+#define DCORE0_VDEC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_VDEC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE0_VDEC0_MSTR_IF_RR_SHRD_LBW_BASE 0x41E5400ull
+#define DCORE0_VDEC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_VDEC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE0_VDEC0_MSTR_IF_RR_PRVT_LBW_BASE 0x41E5600ull
+#define DCORE0_VDEC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_VDEC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE0_VDEC0_MSTR_IF_E2E_CRDT_BASE 0x41E5800ull
+#define DCORE0_VDEC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_VDEC0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE0_VDEC0_MSTR_IF_AXUSER_BASE 0x41E5A80ull
+#define DCORE0_VDEC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_VDEC0_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE0_VDEC0_MSTR_IF_DBG_HBW_BASE 0x41E5B00ull
+#define DCORE0_VDEC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_VDEC0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_VDEC0_MSTR_IF_DBG_LBW_BASE 0x41E5B80ull
+#define DCORE0_VDEC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_VDEC0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE0_VDEC0_MSTR_IF_CORE_HBW_BASE 0x41E5C00ull
+#define DCORE0_VDEC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_VDEC0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE0_VDEC0_MSTR_IF_CORE_LBW_BASE 0x41E5D80ull
+#define DCORE0_VDEC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_VDEC0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE0_VDEC0_MSTR_IF_SPECIAL_BASE 0x41E5E80ull
+#define DCORE0_VDEC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_VDEC0_MSTR_IF_SPECIAL_SECTION 0xA180
+#define mmDCORE0_DEC1_CMD_BASE 0x41F0000ull
+#define DCORE0_DEC1_CMD_MAX_OFFSET 0x1100
+#define DCORE0_DEC1_CMD_SECTION 0x1000
+#define mmDCORE0_DEC1_VSI_BASE 0x41F1000ull
+#define DCORE0_DEC1_VSI_MAX_OFFSET 0x6FC0
+#define DCORE0_DEC1_VSI_SECTION 0x1000
+#define mmDCORE0_DEC1_L2C_BASE 0x41F2000ull
+#define DCORE0_DEC1_L2C_MAX_OFFSET 0x39C0
+#define DCORE0_DEC1_L2C_SECTION 0x1000
+#define mmDCORE0_VDEC1_BRDG_CTRL_BASE 0x41F3000ull
+#define DCORE0_VDEC1_BRDG_CTRL_MAX_OFFSET 0x1000
+#define DCORE0_VDEC1_BRDG_CTRL_SECTION 0x8000
+#define mmDCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x41F3800ull
+#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000
+#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000
+#define mmDCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x41F3900ull
+#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000
+#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000
+#define mmDCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x41F3A00ull
+#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000
+#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000
+#define mmDCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x41F3B00ull
+#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000
+#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000
+#define mmDCORE0_VDEC1_BRDG_CTRL_AXUSER_DEC_BASE 0x41F3C00ull
+#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000
+#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800
+#define mmDCORE0_VDEC1_BRDG_CTRL_SPECIAL_BASE 0x41F3E80ull
+#define DCORE0_VDEC1_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_VDEC1_BRDG_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE0_VDEC1_CTRL_BASE 0x41F4000ull
+#define DCORE0_VDEC1_CTRL_MAX_OFFSET 0x1000
+#define DCORE0_VDEC1_CTRL_SECTION 0xE800
+#define mmDCORE0_VDEC1_CTRL_SPECIAL_BASE 0x41F4E80ull
+#define DCORE0_VDEC1_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_VDEC1_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE0_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE 0x41F5000ull
+#define DCORE0_VDEC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_VDEC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE0_VDEC1_MSTR_IF_RR_PRVT_HBW_BASE 0x41F5200ull
+#define DCORE0_VDEC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE0_VDEC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE0_VDEC1_MSTR_IF_RR_SHRD_LBW_BASE 0x41F5400ull
+#define DCORE0_VDEC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_VDEC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE0_VDEC1_MSTR_IF_RR_PRVT_LBW_BASE 0x41F5600ull
+#define DCORE0_VDEC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE0_VDEC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE0_VDEC1_MSTR_IF_E2E_CRDT_BASE 0x41F5800ull
+#define DCORE0_VDEC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE0_VDEC1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE0_VDEC1_MSTR_IF_AXUSER_BASE 0x41F5A80ull
+#define DCORE0_VDEC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE0_VDEC1_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE0_VDEC1_MSTR_IF_DBG_HBW_BASE 0x41F5B00ull
+#define DCORE0_VDEC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE0_VDEC1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE0_VDEC1_MSTR_IF_DBG_LBW_BASE 0x41F5B80ull
+#define DCORE0_VDEC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE0_VDEC1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE0_VDEC1_MSTR_IF_CORE_HBW_BASE 0x41F5C00ull
+#define DCORE0_VDEC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE0_VDEC1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE0_VDEC1_MSTR_IF_CORE_LBW_BASE 0x41F5D80ull
+#define DCORE0_VDEC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE0_VDEC1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE0_VDEC1_MSTR_IF_SPECIAL_BASE 0x41F5E80ull
+#define DCORE0_VDEC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_VDEC1_MSTR_IF_SPECIAL_SECTION 0xA180
+#define mmDCORE1_TPC0_QM_DCCM_BASE 0x4200000ull
+#define DCORE1_TPC0_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE1_TPC0_QM_DCCM_SECTION 0x8000
+#define mmDCORE1_TPC0_QM_ARC_AUX_BASE 0x4208000ull
+#define DCORE1_TPC0_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE1_TPC0_QM_ARC_AUX_SECTION 0xE800
+#define mmDCORE1_TPC0_QM_ARC_AUX_SPECIAL_BASE 0x4208E80ull
+#define DCORE1_TPC0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC0_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define mmDCORE1_TPC0_QM_BASE 0x420A000ull
+#define DCORE1_TPC0_QM_MAX_OFFSET 0x1000
+#define DCORE1_TPC0_QM_SECTION 0x9000
+#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x420A900ull
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x420A908ull
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x420A910ull
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x420A918ull
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x420A920ull
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x420A928ull
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x420A930ull
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x420A938ull
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x420A940ull
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x420A948ull
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x420A950ull
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x420A958ull
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x420A960ull
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x420A968ull
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x420A970ull
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x420A978ull
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE1_TPC0_QM_AXUSER_SECURED_BASE 0x420AB00ull
+#define DCORE1_TPC0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE1_TPC0_QM_AXUSER_NONSECURED_BASE 0x420AB80ull
+#define DCORE1_TPC0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE1_TPC0_QM_DBG_HBW_BASE 0x420AC00ull
+#define DCORE1_TPC0_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC0_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_TPC0_QM_DBG_LBW_BASE 0x420AC80ull
+#define DCORE1_TPC0_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC0_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE1_TPC0_QM_CGM_BASE 0x420AD80ull
+#define DCORE1_TPC0_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE1_TPC0_QM_CGM_SECTION 0x1000
+#define mmDCORE1_TPC0_QM_SPECIAL_BASE 0x420AE80ull
+#define DCORE1_TPC0_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC0_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_0_BASE 0x420B000ull
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE1_TPC0_CFG_BASE 0x420B000ull
+#define DCORE1_TPC0_CFG_MAX_OFFSET 0x1000
+#define DCORE1_TPC0_CFG_SECTION 0x5000
+#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_1_BASE 0x420B050ull
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_2_BASE 0x420B0A0ull
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_3_BASE 0x420B0F0ull
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_4_BASE 0x420B140ull
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_5_BASE 0x420B190ull
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_6_BASE 0x420B1E0ull
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_7_BASE 0x420B230ull
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_8_BASE 0x420B280ull
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_9_BASE 0x420B2D0ull
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_10_BASE 0x420B320ull
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_11_BASE 0x420B370ull
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_12_BASE 0x420B3C0ull
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_13_BASE 0x420B410ull
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_14_BASE 0x420B460ull
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_15_BASE 0x420B4B0ull
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE1_TPC0_CFG_KERNEL_SYNC_OBJECT_BASE 0x420B500ull
+#define DCORE1_TPC0_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE1_TPC0_CFG_KERNEL_BASE 0x420B508ull
+#define DCORE1_TPC0_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE1_TPC0_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE1_TPC0_CFG_QM_TENSOR_0_BASE 0x420B5DCull
+#define DCORE1_TPC0_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE1_TPC0_CFG_QM_TENSOR_1_BASE 0x420B62Cull
+#define DCORE1_TPC0_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE1_TPC0_CFG_QM_TENSOR_2_BASE 0x420B67Cull
+#define DCORE1_TPC0_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE1_TPC0_CFG_QM_TENSOR_3_BASE 0x420B6CCull
+#define DCORE1_TPC0_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE1_TPC0_CFG_QM_TENSOR_4_BASE 0x420B71Cull
+#define DCORE1_TPC0_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE1_TPC0_CFG_QM_TENSOR_5_BASE 0x420B76Cull
+#define DCORE1_TPC0_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE1_TPC0_CFG_QM_TENSOR_6_BASE 0x420B7BCull
+#define DCORE1_TPC0_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE1_TPC0_CFG_QM_TENSOR_7_BASE 0x420B80Cull
+#define DCORE1_TPC0_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE1_TPC0_CFG_QM_TENSOR_8_BASE 0x420B85Cull
+#define DCORE1_TPC0_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE1_TPC0_CFG_QM_TENSOR_9_BASE 0x420B8ACull
+#define DCORE1_TPC0_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE1_TPC0_CFG_QM_TENSOR_10_BASE 0x420B8FCull
+#define DCORE1_TPC0_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE1_TPC0_CFG_QM_TENSOR_11_BASE 0x420B94Cull
+#define DCORE1_TPC0_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE1_TPC0_CFG_QM_TENSOR_12_BASE 0x420B99Cull
+#define DCORE1_TPC0_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE1_TPC0_CFG_QM_TENSOR_13_BASE 0x420B9ECull
+#define DCORE1_TPC0_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE1_TPC0_CFG_QM_TENSOR_14_BASE 0x420BA3Cull
+#define DCORE1_TPC0_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE1_TPC0_CFG_QM_TENSOR_15_BASE 0x420BA8Cull
+#define DCORE1_TPC0_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE1_TPC0_CFG_QM_SYNC_OBJECT_BASE 0x420BADCull
+#define DCORE1_TPC0_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE1_TPC0_CFG_QM_BASE 0x420BAE4ull
+#define DCORE1_TPC0_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE1_TPC0_CFG_QM_SECTION 0x31C0
+#define mmDCORE1_TPC0_CFG_AXUSER_BASE 0x420BE00ull
+#define DCORE1_TPC0_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE1_TPC0_CFG_SPECIAL_BASE 0x420BE80ull
+#define DCORE1_TPC0_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC0_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE1_TPC0_MSTR_IF_RR_SHRD_HBW_BASE 0x420C000ull
+#define DCORE1_TPC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_TPC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE1_TPC0_MSTR_IF_RR_PRVT_HBW_BASE 0x420C200ull
+#define DCORE1_TPC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_TPC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE1_TPC0_MSTR_IF_RR_SHRD_LBW_BASE 0x420C400ull
+#define DCORE1_TPC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_TPC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE1_TPC0_MSTR_IF_RR_PRVT_LBW_BASE 0x420C600ull
+#define DCORE1_TPC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_TPC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE1_TPC0_MSTR_IF_E2E_CRDT_BASE 0x420C800ull
+#define DCORE1_TPC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_TPC0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE1_TPC0_MSTR_IF_AXUSER_BASE 0x420CA80ull
+#define DCORE1_TPC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_TPC0_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE1_TPC0_MSTR_IF_DBG_HBW_BASE 0x420CB00ull
+#define DCORE1_TPC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_TPC0_MSTR_IF_DBG_LBW_BASE 0x420CB80ull
+#define DCORE1_TPC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE1_TPC0_MSTR_IF_CORE_HBW_BASE 0x420CC00ull
+#define DCORE1_TPC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_TPC0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE1_TPC0_MSTR_IF_CORE_LBW_BASE 0x420CD80ull
+#define DCORE1_TPC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_TPC0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE1_TPC0_MSTR_IF_SPECIAL_BASE 0x420CE80ull
+#define DCORE1_TPC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC0_MSTR_IF_SPECIAL_SECTION 0x3180
+#define mmDCORE1_TPC1_QM_DCCM_BASE 0x4210000ull
+#define DCORE1_TPC1_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE1_TPC1_QM_DCCM_SECTION 0x8000
+#define mmDCORE1_TPC1_QM_ARC_AUX_BASE 0x4218000ull
+#define DCORE1_TPC1_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE1_TPC1_QM_ARC_AUX_SECTION 0xE800
+#define mmDCORE1_TPC1_QM_ARC_AUX_SPECIAL_BASE 0x4218E80ull
+#define DCORE1_TPC1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC1_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define mmDCORE1_TPC1_QM_BASE 0x421A000ull
+#define DCORE1_TPC1_QM_MAX_OFFSET 0x1000
+#define DCORE1_TPC1_QM_SECTION 0x9000
+#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x421A900ull
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x421A908ull
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x421A910ull
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x421A918ull
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x421A920ull
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x421A928ull
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x421A930ull
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x421A938ull
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x421A940ull
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x421A948ull
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x421A950ull
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x421A958ull
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x421A960ull
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x421A968ull
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x421A970ull
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x421A978ull
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE1_TPC1_QM_AXUSER_SECURED_BASE 0x421AB00ull
+#define DCORE1_TPC1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE1_TPC1_QM_AXUSER_NONSECURED_BASE 0x421AB80ull
+#define DCORE1_TPC1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE1_TPC1_QM_DBG_HBW_BASE 0x421AC00ull
+#define DCORE1_TPC1_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC1_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_TPC1_QM_DBG_LBW_BASE 0x421AC80ull
+#define DCORE1_TPC1_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC1_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE1_TPC1_QM_CGM_BASE 0x421AD80ull
+#define DCORE1_TPC1_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE1_TPC1_QM_CGM_SECTION 0x1000
+#define mmDCORE1_TPC1_QM_SPECIAL_BASE 0x421AE80ull
+#define DCORE1_TPC1_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC1_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_0_BASE 0x421B000ull
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE1_TPC1_CFG_BASE 0x421B000ull
+#define DCORE1_TPC1_CFG_MAX_OFFSET 0x1000
+#define DCORE1_TPC1_CFG_SECTION 0x5000
+#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_1_BASE 0x421B050ull
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_2_BASE 0x421B0A0ull
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_3_BASE 0x421B0F0ull
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_4_BASE 0x421B140ull
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_5_BASE 0x421B190ull
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_6_BASE 0x421B1E0ull
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_7_BASE 0x421B230ull
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_8_BASE 0x421B280ull
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_9_BASE 0x421B2D0ull
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_10_BASE 0x421B320ull
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_11_BASE 0x421B370ull
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_12_BASE 0x421B3C0ull
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_13_BASE 0x421B410ull
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_14_BASE 0x421B460ull
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_15_BASE 0x421B4B0ull
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE1_TPC1_CFG_KERNEL_SYNC_OBJECT_BASE 0x421B500ull
+#define DCORE1_TPC1_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE1_TPC1_CFG_KERNEL_BASE 0x421B508ull
+#define DCORE1_TPC1_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE1_TPC1_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE1_TPC1_CFG_QM_TENSOR_0_BASE 0x421B5DCull
+#define DCORE1_TPC1_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE1_TPC1_CFG_QM_TENSOR_1_BASE 0x421B62Cull
+#define DCORE1_TPC1_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE1_TPC1_CFG_QM_TENSOR_2_BASE 0x421B67Cull
+#define DCORE1_TPC1_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE1_TPC1_CFG_QM_TENSOR_3_BASE 0x421B6CCull
+#define DCORE1_TPC1_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE1_TPC1_CFG_QM_TENSOR_4_BASE 0x421B71Cull
+#define DCORE1_TPC1_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE1_TPC1_CFG_QM_TENSOR_5_BASE 0x421B76Cull
+#define DCORE1_TPC1_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE1_TPC1_CFG_QM_TENSOR_6_BASE 0x421B7BCull
+#define DCORE1_TPC1_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE1_TPC1_CFG_QM_TENSOR_7_BASE 0x421B80Cull
+#define DCORE1_TPC1_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE1_TPC1_CFG_QM_TENSOR_8_BASE 0x421B85Cull
+#define DCORE1_TPC1_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE1_TPC1_CFG_QM_TENSOR_9_BASE 0x421B8ACull
+#define DCORE1_TPC1_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE1_TPC1_CFG_QM_TENSOR_10_BASE 0x421B8FCull
+#define DCORE1_TPC1_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE1_TPC1_CFG_QM_TENSOR_11_BASE 0x421B94Cull
+#define DCORE1_TPC1_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE1_TPC1_CFG_QM_TENSOR_12_BASE 0x421B99Cull
+#define DCORE1_TPC1_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE1_TPC1_CFG_QM_TENSOR_13_BASE 0x421B9ECull
+#define DCORE1_TPC1_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE1_TPC1_CFG_QM_TENSOR_14_BASE 0x421BA3Cull
+#define DCORE1_TPC1_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE1_TPC1_CFG_QM_TENSOR_15_BASE 0x421BA8Cull
+#define DCORE1_TPC1_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE1_TPC1_CFG_QM_SYNC_OBJECT_BASE 0x421BADCull
+#define DCORE1_TPC1_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE1_TPC1_CFG_QM_BASE 0x421BAE4ull
+#define DCORE1_TPC1_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE1_TPC1_CFG_QM_SECTION 0x31C0
+#define mmDCORE1_TPC1_CFG_AXUSER_BASE 0x421BE00ull
+#define DCORE1_TPC1_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE1_TPC1_CFG_SPECIAL_BASE 0x421BE80ull
+#define DCORE1_TPC1_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC1_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE1_TPC1_MSTR_IF_RR_SHRD_HBW_BASE 0x421C000ull
+#define DCORE1_TPC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_TPC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE1_TPC1_MSTR_IF_RR_PRVT_HBW_BASE 0x421C200ull
+#define DCORE1_TPC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_TPC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE1_TPC1_MSTR_IF_RR_SHRD_LBW_BASE 0x421C400ull
+#define DCORE1_TPC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_TPC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE1_TPC1_MSTR_IF_RR_PRVT_LBW_BASE 0x421C600ull
+#define DCORE1_TPC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_TPC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE1_TPC1_MSTR_IF_E2E_CRDT_BASE 0x421C800ull
+#define DCORE1_TPC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_TPC1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE1_TPC1_MSTR_IF_AXUSER_BASE 0x421CA80ull
+#define DCORE1_TPC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_TPC1_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE1_TPC1_MSTR_IF_DBG_HBW_BASE 0x421CB00ull
+#define DCORE1_TPC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_TPC1_MSTR_IF_DBG_LBW_BASE 0x421CB80ull
+#define DCORE1_TPC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE1_TPC1_MSTR_IF_CORE_HBW_BASE 0x421CC00ull
+#define DCORE1_TPC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_TPC1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE1_TPC1_MSTR_IF_CORE_LBW_BASE 0x421CD80ull
+#define DCORE1_TPC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_TPC1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE1_TPC1_MSTR_IF_SPECIAL_BASE 0x421CE80ull
+#define DCORE1_TPC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC1_MSTR_IF_SPECIAL_SECTION 0x3180
+#define mmDCORE1_TPC2_QM_DCCM_BASE 0x4220000ull
+#define DCORE1_TPC2_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE1_TPC2_QM_DCCM_SECTION 0x8000
+#define mmDCORE1_TPC2_QM_ARC_AUX_BASE 0x4228000ull
+#define DCORE1_TPC2_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE1_TPC2_QM_ARC_AUX_SECTION 0xE800
+#define mmDCORE1_TPC2_QM_ARC_AUX_SPECIAL_BASE 0x4228E80ull
+#define DCORE1_TPC2_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC2_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define mmDCORE1_TPC2_QM_BASE 0x422A000ull
+#define DCORE1_TPC2_QM_MAX_OFFSET 0x1000
+#define DCORE1_TPC2_QM_SECTION 0x9000
+#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR0_BASE 0x422A900ull
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR1_BASE 0x422A908ull
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR2_BASE 0x422A910ull
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR3_BASE 0x422A918ull
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR4_BASE 0x422A920ull
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR5_BASE 0x422A928ull
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR6_BASE 0x422A930ull
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR7_BASE 0x422A938ull
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR8_BASE 0x422A940ull
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR9_BASE 0x422A948ull
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR10_BASE 0x422A950ull
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR11_BASE 0x422A958ull
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR12_BASE 0x422A960ull
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR13_BASE 0x422A968ull
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR14_BASE 0x422A970ull
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR15_BASE 0x422A978ull
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE1_TPC2_QM_AXUSER_SECURED_BASE 0x422AB00ull
+#define DCORE1_TPC2_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE1_TPC2_QM_AXUSER_NONSECURED_BASE 0x422AB80ull
+#define DCORE1_TPC2_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE1_TPC2_QM_DBG_HBW_BASE 0x422AC00ull
+#define DCORE1_TPC2_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC2_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_TPC2_QM_DBG_LBW_BASE 0x422AC80ull
+#define DCORE1_TPC2_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC2_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE1_TPC2_QM_CGM_BASE 0x422AD80ull
+#define DCORE1_TPC2_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE1_TPC2_QM_CGM_SECTION 0x1000
+#define mmDCORE1_TPC2_QM_SPECIAL_BASE 0x422AE80ull
+#define DCORE1_TPC2_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC2_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_0_BASE 0x422B000ull
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE1_TPC2_CFG_BASE 0x422B000ull
+#define DCORE1_TPC2_CFG_MAX_OFFSET 0x1000
+#define DCORE1_TPC2_CFG_SECTION 0x5000
+#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_1_BASE 0x422B050ull
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_2_BASE 0x422B0A0ull
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_3_BASE 0x422B0F0ull
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_4_BASE 0x422B140ull
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_5_BASE 0x422B190ull
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_6_BASE 0x422B1E0ull
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_7_BASE 0x422B230ull
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_8_BASE 0x422B280ull
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_9_BASE 0x422B2D0ull
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_10_BASE 0x422B320ull
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_11_BASE 0x422B370ull
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_12_BASE 0x422B3C0ull
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_13_BASE 0x422B410ull
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_14_BASE 0x422B460ull
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_15_BASE 0x422B4B0ull
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE1_TPC2_CFG_KERNEL_SYNC_OBJECT_BASE 0x422B500ull
+#define DCORE1_TPC2_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE1_TPC2_CFG_KERNEL_BASE 0x422B508ull
+#define DCORE1_TPC2_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE1_TPC2_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE1_TPC2_CFG_QM_TENSOR_0_BASE 0x422B5DCull
+#define DCORE1_TPC2_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE1_TPC2_CFG_QM_TENSOR_1_BASE 0x422B62Cull
+#define DCORE1_TPC2_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE1_TPC2_CFG_QM_TENSOR_2_BASE 0x422B67Cull
+#define DCORE1_TPC2_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE1_TPC2_CFG_QM_TENSOR_3_BASE 0x422B6CCull
+#define DCORE1_TPC2_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE1_TPC2_CFG_QM_TENSOR_4_BASE 0x422B71Cull
+#define DCORE1_TPC2_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE1_TPC2_CFG_QM_TENSOR_5_BASE 0x422B76Cull
+#define DCORE1_TPC2_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE1_TPC2_CFG_QM_TENSOR_6_BASE 0x422B7BCull
+#define DCORE1_TPC2_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE1_TPC2_CFG_QM_TENSOR_7_BASE 0x422B80Cull
+#define DCORE1_TPC2_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE1_TPC2_CFG_QM_TENSOR_8_BASE 0x422B85Cull
+#define DCORE1_TPC2_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE1_TPC2_CFG_QM_TENSOR_9_BASE 0x422B8ACull
+#define DCORE1_TPC2_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE1_TPC2_CFG_QM_TENSOR_10_BASE 0x422B8FCull
+#define DCORE1_TPC2_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE1_TPC2_CFG_QM_TENSOR_11_BASE 0x422B94Cull
+#define DCORE1_TPC2_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE1_TPC2_CFG_QM_TENSOR_12_BASE 0x422B99Cull
+#define DCORE1_TPC2_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE1_TPC2_CFG_QM_TENSOR_13_BASE 0x422B9ECull
+#define DCORE1_TPC2_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE1_TPC2_CFG_QM_TENSOR_14_BASE 0x422BA3Cull
+#define DCORE1_TPC2_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE1_TPC2_CFG_QM_TENSOR_15_BASE 0x422BA8Cull
+#define DCORE1_TPC2_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE1_TPC2_CFG_QM_SYNC_OBJECT_BASE 0x422BADCull
+#define DCORE1_TPC2_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE1_TPC2_CFG_QM_BASE 0x422BAE4ull
+#define DCORE1_TPC2_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE1_TPC2_CFG_QM_SECTION 0x31C0
+#define mmDCORE1_TPC2_CFG_AXUSER_BASE 0x422BE00ull
+#define DCORE1_TPC2_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE1_TPC2_CFG_SPECIAL_BASE 0x422BE80ull
+#define DCORE1_TPC2_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC2_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE1_TPC2_MSTR_IF_RR_SHRD_HBW_BASE 0x422C000ull
+#define DCORE1_TPC2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_TPC2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE1_TPC2_MSTR_IF_RR_PRVT_HBW_BASE 0x422C200ull
+#define DCORE1_TPC2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_TPC2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE1_TPC2_MSTR_IF_RR_SHRD_LBW_BASE 0x422C400ull
+#define DCORE1_TPC2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_TPC2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE1_TPC2_MSTR_IF_RR_PRVT_LBW_BASE 0x422C600ull
+#define DCORE1_TPC2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_TPC2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE1_TPC2_MSTR_IF_E2E_CRDT_BASE 0x422C800ull
+#define DCORE1_TPC2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_TPC2_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE1_TPC2_MSTR_IF_AXUSER_BASE 0x422CA80ull
+#define DCORE1_TPC2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_TPC2_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE1_TPC2_MSTR_IF_DBG_HBW_BASE 0x422CB00ull
+#define DCORE1_TPC2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC2_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_TPC2_MSTR_IF_DBG_LBW_BASE 0x422CB80ull
+#define DCORE1_TPC2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC2_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE1_TPC2_MSTR_IF_CORE_HBW_BASE 0x422CC00ull
+#define DCORE1_TPC2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_TPC2_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE1_TPC2_MSTR_IF_CORE_LBW_BASE 0x422CD80ull
+#define DCORE1_TPC2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_TPC2_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE1_TPC2_MSTR_IF_SPECIAL_BASE 0x422CE80ull
+#define DCORE1_TPC2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC2_MSTR_IF_SPECIAL_SECTION 0x3180
+#define mmDCORE1_TPC3_QM_DCCM_BASE 0x4230000ull
+#define DCORE1_TPC3_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE1_TPC3_QM_DCCM_SECTION 0x8000
+#define mmDCORE1_TPC3_QM_ARC_AUX_BASE 0x4238000ull
+#define DCORE1_TPC3_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE1_TPC3_QM_ARC_AUX_SECTION 0xE800
+#define mmDCORE1_TPC3_QM_ARC_AUX_SPECIAL_BASE 0x4238E80ull
+#define DCORE1_TPC3_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC3_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define mmDCORE1_TPC3_QM_BASE 0x423A000ull
+#define DCORE1_TPC3_QM_MAX_OFFSET 0x1000
+#define DCORE1_TPC3_QM_SECTION 0x9000
+#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR0_BASE 0x423A900ull
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR1_BASE 0x423A908ull
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR2_BASE 0x423A910ull
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR3_BASE 0x423A918ull
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR4_BASE 0x423A920ull
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR5_BASE 0x423A928ull
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR6_BASE 0x423A930ull
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR7_BASE 0x423A938ull
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR8_BASE 0x423A940ull
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR9_BASE 0x423A948ull
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR10_BASE 0x423A950ull
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR11_BASE 0x423A958ull
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR12_BASE 0x423A960ull
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR13_BASE 0x423A968ull
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR14_BASE 0x423A970ull
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR15_BASE 0x423A978ull
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE1_TPC3_QM_AXUSER_SECURED_BASE 0x423AB00ull
+#define DCORE1_TPC3_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE1_TPC3_QM_AXUSER_NONSECURED_BASE 0x423AB80ull
+#define DCORE1_TPC3_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE1_TPC3_QM_DBG_HBW_BASE 0x423AC00ull
+#define DCORE1_TPC3_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC3_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_TPC3_QM_DBG_LBW_BASE 0x423AC80ull
+#define DCORE1_TPC3_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC3_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE1_TPC3_QM_CGM_BASE 0x423AD80ull
+#define DCORE1_TPC3_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE1_TPC3_QM_CGM_SECTION 0x1000
+#define mmDCORE1_TPC3_QM_SPECIAL_BASE 0x423AE80ull
+#define DCORE1_TPC3_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC3_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_0_BASE 0x423B000ull
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE1_TPC3_CFG_BASE 0x423B000ull
+#define DCORE1_TPC3_CFG_MAX_OFFSET 0x1000
+#define DCORE1_TPC3_CFG_SECTION 0x5000
+#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_1_BASE 0x423B050ull
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_2_BASE 0x423B0A0ull
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_3_BASE 0x423B0F0ull
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_4_BASE 0x423B140ull
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_5_BASE 0x423B190ull
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_6_BASE 0x423B1E0ull
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_7_BASE 0x423B230ull
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_8_BASE 0x423B280ull
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_9_BASE 0x423B2D0ull
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_10_BASE 0x423B320ull
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_11_BASE 0x423B370ull
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_12_BASE 0x423B3C0ull
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_13_BASE 0x423B410ull
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_14_BASE 0x423B460ull
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_15_BASE 0x423B4B0ull
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE1_TPC3_CFG_KERNEL_SYNC_OBJECT_BASE 0x423B500ull
+#define DCORE1_TPC3_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE1_TPC3_CFG_KERNEL_BASE 0x423B508ull
+#define DCORE1_TPC3_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE1_TPC3_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE1_TPC3_CFG_QM_TENSOR_0_BASE 0x423B5DCull
+#define DCORE1_TPC3_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE1_TPC3_CFG_QM_TENSOR_1_BASE 0x423B62Cull
+#define DCORE1_TPC3_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE1_TPC3_CFG_QM_TENSOR_2_BASE 0x423B67Cull
+#define DCORE1_TPC3_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE1_TPC3_CFG_QM_TENSOR_3_BASE 0x423B6CCull
+#define DCORE1_TPC3_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE1_TPC3_CFG_QM_TENSOR_4_BASE 0x423B71Cull
+#define DCORE1_TPC3_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE1_TPC3_CFG_QM_TENSOR_5_BASE 0x423B76Cull
+#define DCORE1_TPC3_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE1_TPC3_CFG_QM_TENSOR_6_BASE 0x423B7BCull
+#define DCORE1_TPC3_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE1_TPC3_CFG_QM_TENSOR_7_BASE 0x423B80Cull
+#define DCORE1_TPC3_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE1_TPC3_CFG_QM_TENSOR_8_BASE 0x423B85Cull
+#define DCORE1_TPC3_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE1_TPC3_CFG_QM_TENSOR_9_BASE 0x423B8ACull
+#define DCORE1_TPC3_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE1_TPC3_CFG_QM_TENSOR_10_BASE 0x423B8FCull
+#define DCORE1_TPC3_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE1_TPC3_CFG_QM_TENSOR_11_BASE 0x423B94Cull
+#define DCORE1_TPC3_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE1_TPC3_CFG_QM_TENSOR_12_BASE 0x423B99Cull
+#define DCORE1_TPC3_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE1_TPC3_CFG_QM_TENSOR_13_BASE 0x423B9ECull
+#define DCORE1_TPC3_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE1_TPC3_CFG_QM_TENSOR_14_BASE 0x423BA3Cull
+#define DCORE1_TPC3_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE1_TPC3_CFG_QM_TENSOR_15_BASE 0x423BA8Cull
+#define DCORE1_TPC3_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE1_TPC3_CFG_QM_SYNC_OBJECT_BASE 0x423BADCull
+#define DCORE1_TPC3_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE1_TPC3_CFG_QM_BASE 0x423BAE4ull
+#define DCORE1_TPC3_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE1_TPC3_CFG_QM_SECTION 0x31C0
+#define mmDCORE1_TPC3_CFG_AXUSER_BASE 0x423BE00ull
+#define DCORE1_TPC3_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE1_TPC3_CFG_SPECIAL_BASE 0x423BE80ull
+#define DCORE1_TPC3_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC3_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE1_TPC3_MSTR_IF_RR_SHRD_HBW_BASE 0x423C000ull
+#define DCORE1_TPC3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_TPC3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE1_TPC3_MSTR_IF_RR_PRVT_HBW_BASE 0x423C200ull
+#define DCORE1_TPC3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_TPC3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE1_TPC3_MSTR_IF_RR_SHRD_LBW_BASE 0x423C400ull
+#define DCORE1_TPC3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_TPC3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE1_TPC3_MSTR_IF_RR_PRVT_LBW_BASE 0x423C600ull
+#define DCORE1_TPC3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_TPC3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE1_TPC3_MSTR_IF_E2E_CRDT_BASE 0x423C800ull
+#define DCORE1_TPC3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_TPC3_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE1_TPC3_MSTR_IF_AXUSER_BASE 0x423CA80ull
+#define DCORE1_TPC3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_TPC3_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE1_TPC3_MSTR_IF_DBG_HBW_BASE 0x423CB00ull
+#define DCORE1_TPC3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC3_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_TPC3_MSTR_IF_DBG_LBW_BASE 0x423CB80ull
+#define DCORE1_TPC3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC3_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE1_TPC3_MSTR_IF_CORE_HBW_BASE 0x423CC00ull
+#define DCORE1_TPC3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_TPC3_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE1_TPC3_MSTR_IF_CORE_LBW_BASE 0x423CD80ull
+#define DCORE1_TPC3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_TPC3_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE1_TPC3_MSTR_IF_SPECIAL_BASE 0x423CE80ull
+#define DCORE1_TPC3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC3_MSTR_IF_SPECIAL_SECTION 0x3180
+#define mmDCORE1_TPC4_QM_DCCM_BASE 0x4240000ull
+#define DCORE1_TPC4_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE1_TPC4_QM_DCCM_SECTION 0x8000
+#define mmDCORE1_TPC4_QM_ARC_AUX_BASE 0x4248000ull
+#define DCORE1_TPC4_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE1_TPC4_QM_ARC_AUX_SECTION 0xE800
+#define mmDCORE1_TPC4_QM_ARC_AUX_SPECIAL_BASE 0x4248E80ull
+#define DCORE1_TPC4_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC4_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define mmDCORE1_TPC4_QM_BASE 0x424A000ull
+#define DCORE1_TPC4_QM_MAX_OFFSET 0x1000
+#define DCORE1_TPC4_QM_SECTION 0x9000
+#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR0_BASE 0x424A900ull
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR1_BASE 0x424A908ull
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR2_BASE 0x424A910ull
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR3_BASE 0x424A918ull
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR4_BASE 0x424A920ull
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR5_BASE 0x424A928ull
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR6_BASE 0x424A930ull
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR7_BASE 0x424A938ull
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR8_BASE 0x424A940ull
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR9_BASE 0x424A948ull
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR10_BASE 0x424A950ull
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR11_BASE 0x424A958ull
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR12_BASE 0x424A960ull
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR13_BASE 0x424A968ull
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR14_BASE 0x424A970ull
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR15_BASE 0x424A978ull
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE1_TPC4_QM_AXUSER_SECURED_BASE 0x424AB00ull
+#define DCORE1_TPC4_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE1_TPC4_QM_AXUSER_NONSECURED_BASE 0x424AB80ull
+#define DCORE1_TPC4_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE1_TPC4_QM_DBG_HBW_BASE 0x424AC00ull
+#define DCORE1_TPC4_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC4_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_TPC4_QM_DBG_LBW_BASE 0x424AC80ull
+#define DCORE1_TPC4_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC4_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE1_TPC4_QM_CGM_BASE 0x424AD80ull
+#define DCORE1_TPC4_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE1_TPC4_QM_CGM_SECTION 0x1000
+#define mmDCORE1_TPC4_QM_SPECIAL_BASE 0x424AE80ull
+#define DCORE1_TPC4_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC4_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_0_BASE 0x424B000ull
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE1_TPC4_CFG_BASE 0x424B000ull
+#define DCORE1_TPC4_CFG_MAX_OFFSET 0x1000
+#define DCORE1_TPC4_CFG_SECTION 0x5000
+#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_1_BASE 0x424B050ull
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_2_BASE 0x424B0A0ull
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_3_BASE 0x424B0F0ull
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_4_BASE 0x424B140ull
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_5_BASE 0x424B190ull
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_6_BASE 0x424B1E0ull
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_7_BASE 0x424B230ull
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_8_BASE 0x424B280ull
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_9_BASE 0x424B2D0ull
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_10_BASE 0x424B320ull
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_11_BASE 0x424B370ull
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_12_BASE 0x424B3C0ull
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_13_BASE 0x424B410ull
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_14_BASE 0x424B460ull
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_15_BASE 0x424B4B0ull
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE1_TPC4_CFG_KERNEL_SYNC_OBJECT_BASE 0x424B500ull
+#define DCORE1_TPC4_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE1_TPC4_CFG_KERNEL_BASE 0x424B508ull
+#define DCORE1_TPC4_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE1_TPC4_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE1_TPC4_CFG_QM_TENSOR_0_BASE 0x424B5DCull
+#define DCORE1_TPC4_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE1_TPC4_CFG_QM_TENSOR_1_BASE 0x424B62Cull
+#define DCORE1_TPC4_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE1_TPC4_CFG_QM_TENSOR_2_BASE 0x424B67Cull
+#define DCORE1_TPC4_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE1_TPC4_CFG_QM_TENSOR_3_BASE 0x424B6CCull
+#define DCORE1_TPC4_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE1_TPC4_CFG_QM_TENSOR_4_BASE 0x424B71Cull
+#define DCORE1_TPC4_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE1_TPC4_CFG_QM_TENSOR_5_BASE 0x424B76Cull
+#define DCORE1_TPC4_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE1_TPC4_CFG_QM_TENSOR_6_BASE 0x424B7BCull
+#define DCORE1_TPC4_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE1_TPC4_CFG_QM_TENSOR_7_BASE 0x424B80Cull
+#define DCORE1_TPC4_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE1_TPC4_CFG_QM_TENSOR_8_BASE 0x424B85Cull
+#define DCORE1_TPC4_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE1_TPC4_CFG_QM_TENSOR_9_BASE 0x424B8ACull
+#define DCORE1_TPC4_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE1_TPC4_CFG_QM_TENSOR_10_BASE 0x424B8FCull
+#define DCORE1_TPC4_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE1_TPC4_CFG_QM_TENSOR_11_BASE 0x424B94Cull
+#define DCORE1_TPC4_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE1_TPC4_CFG_QM_TENSOR_12_BASE 0x424B99Cull
+#define DCORE1_TPC4_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE1_TPC4_CFG_QM_TENSOR_13_BASE 0x424B9ECull
+#define DCORE1_TPC4_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE1_TPC4_CFG_QM_TENSOR_14_BASE 0x424BA3Cull
+#define DCORE1_TPC4_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE1_TPC4_CFG_QM_TENSOR_15_BASE 0x424BA8Cull
+#define DCORE1_TPC4_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE1_TPC4_CFG_QM_SYNC_OBJECT_BASE 0x424BADCull
+#define DCORE1_TPC4_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE1_TPC4_CFG_QM_BASE 0x424BAE4ull
+#define DCORE1_TPC4_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE1_TPC4_CFG_QM_SECTION 0x31C0
+#define mmDCORE1_TPC4_CFG_AXUSER_BASE 0x424BE00ull
+#define DCORE1_TPC4_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE1_TPC4_CFG_SPECIAL_BASE 0x424BE80ull
+#define DCORE1_TPC4_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC4_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE1_TPC4_MSTR_IF_RR_SHRD_HBW_BASE 0x424C000ull
+#define DCORE1_TPC4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_TPC4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE1_TPC4_MSTR_IF_RR_PRVT_HBW_BASE 0x424C200ull
+#define DCORE1_TPC4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_TPC4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE1_TPC4_MSTR_IF_RR_SHRD_LBW_BASE 0x424C400ull
+#define DCORE1_TPC4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_TPC4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE1_TPC4_MSTR_IF_RR_PRVT_LBW_BASE 0x424C600ull
+#define DCORE1_TPC4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_TPC4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE1_TPC4_MSTR_IF_E2E_CRDT_BASE 0x424C800ull
+#define DCORE1_TPC4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_TPC4_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE1_TPC4_MSTR_IF_AXUSER_BASE 0x424CA80ull
+#define DCORE1_TPC4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_TPC4_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE1_TPC4_MSTR_IF_DBG_HBW_BASE 0x424CB00ull
+#define DCORE1_TPC4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC4_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_TPC4_MSTR_IF_DBG_LBW_BASE 0x424CB80ull
+#define DCORE1_TPC4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC4_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE1_TPC4_MSTR_IF_CORE_HBW_BASE 0x424CC00ull
+#define DCORE1_TPC4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_TPC4_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE1_TPC4_MSTR_IF_CORE_LBW_BASE 0x424CD80ull
+#define DCORE1_TPC4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_TPC4_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE1_TPC4_MSTR_IF_SPECIAL_BASE 0x424CE80ull
+#define DCORE1_TPC4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC4_MSTR_IF_SPECIAL_SECTION 0x3180
+#define mmDCORE1_TPC5_QM_DCCM_BASE 0x4250000ull
+#define DCORE1_TPC5_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE1_TPC5_QM_DCCM_SECTION 0x8000
+#define mmDCORE1_TPC5_QM_ARC_AUX_BASE 0x4258000ull
+#define DCORE1_TPC5_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE1_TPC5_QM_ARC_AUX_SECTION 0xE800
+#define mmDCORE1_TPC5_QM_ARC_AUX_SPECIAL_BASE 0x4258E80ull
+#define DCORE1_TPC5_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC5_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define mmDCORE1_TPC5_QM_BASE 0x425A000ull
+#define DCORE1_TPC5_QM_MAX_OFFSET 0x1000
+#define DCORE1_TPC5_QM_SECTION 0x9000
+#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR0_BASE 0x425A900ull
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR1_BASE 0x425A908ull
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR2_BASE 0x425A910ull
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR3_BASE 0x425A918ull
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR4_BASE 0x425A920ull
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR5_BASE 0x425A928ull
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR6_BASE 0x425A930ull
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR7_BASE 0x425A938ull
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR8_BASE 0x425A940ull
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR9_BASE 0x425A948ull
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR10_BASE 0x425A950ull
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR11_BASE 0x425A958ull
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR12_BASE 0x425A960ull
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR13_BASE 0x425A968ull
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR14_BASE 0x425A970ull
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR15_BASE 0x425A978ull
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE1_TPC5_QM_AXUSER_SECURED_BASE 0x425AB00ull
+#define DCORE1_TPC5_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE1_TPC5_QM_AXUSER_NONSECURED_BASE 0x425AB80ull
+#define DCORE1_TPC5_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE1_TPC5_QM_DBG_HBW_BASE 0x425AC00ull
+#define DCORE1_TPC5_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC5_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_TPC5_QM_DBG_LBW_BASE 0x425AC80ull
+#define DCORE1_TPC5_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC5_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE1_TPC5_QM_CGM_BASE 0x425AD80ull
+#define DCORE1_TPC5_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE1_TPC5_QM_CGM_SECTION 0x1000
+#define mmDCORE1_TPC5_QM_SPECIAL_BASE 0x425AE80ull
+#define DCORE1_TPC5_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC5_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_0_BASE 0x425B000ull
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE1_TPC5_CFG_BASE 0x425B000ull
+#define DCORE1_TPC5_CFG_MAX_OFFSET 0x1000
+#define DCORE1_TPC5_CFG_SECTION 0x5000
+#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_1_BASE 0x425B050ull
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_2_BASE 0x425B0A0ull
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_3_BASE 0x425B0F0ull
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_4_BASE 0x425B140ull
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_5_BASE 0x425B190ull
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_6_BASE 0x425B1E0ull
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_7_BASE 0x425B230ull
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_8_BASE 0x425B280ull
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_9_BASE 0x425B2D0ull
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_10_BASE 0x425B320ull
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_11_BASE 0x425B370ull
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_12_BASE 0x425B3C0ull
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_13_BASE 0x425B410ull
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_14_BASE 0x425B460ull
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_15_BASE 0x425B4B0ull
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE1_TPC5_CFG_KERNEL_SYNC_OBJECT_BASE 0x425B500ull
+#define DCORE1_TPC5_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE1_TPC5_CFG_KERNEL_BASE 0x425B508ull
+#define DCORE1_TPC5_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE1_TPC5_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE1_TPC5_CFG_QM_TENSOR_0_BASE 0x425B5DCull
+#define DCORE1_TPC5_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE1_TPC5_CFG_QM_TENSOR_1_BASE 0x425B62Cull
+#define DCORE1_TPC5_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE1_TPC5_CFG_QM_TENSOR_2_BASE 0x425B67Cull
+#define DCORE1_TPC5_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE1_TPC5_CFG_QM_TENSOR_3_BASE 0x425B6CCull
+#define DCORE1_TPC5_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE1_TPC5_CFG_QM_TENSOR_4_BASE 0x425B71Cull
+#define DCORE1_TPC5_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE1_TPC5_CFG_QM_TENSOR_5_BASE 0x425B76Cull
+#define DCORE1_TPC5_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE1_TPC5_CFG_QM_TENSOR_6_BASE 0x425B7BCull
+#define DCORE1_TPC5_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE1_TPC5_CFG_QM_TENSOR_7_BASE 0x425B80Cull
+#define DCORE1_TPC5_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE1_TPC5_CFG_QM_TENSOR_8_BASE 0x425B85Cull
+#define DCORE1_TPC5_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE1_TPC5_CFG_QM_TENSOR_9_BASE 0x425B8ACull
+#define DCORE1_TPC5_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE1_TPC5_CFG_QM_TENSOR_10_BASE 0x425B8FCull
+#define DCORE1_TPC5_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE1_TPC5_CFG_QM_TENSOR_11_BASE 0x425B94Cull
+#define DCORE1_TPC5_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE1_TPC5_CFG_QM_TENSOR_12_BASE 0x425B99Cull
+#define DCORE1_TPC5_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE1_TPC5_CFG_QM_TENSOR_13_BASE 0x425B9ECull
+#define DCORE1_TPC5_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE1_TPC5_CFG_QM_TENSOR_14_BASE 0x425BA3Cull
+#define DCORE1_TPC5_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE1_TPC5_CFG_QM_TENSOR_15_BASE 0x425BA8Cull
+#define DCORE1_TPC5_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE1_TPC5_CFG_QM_SYNC_OBJECT_BASE 0x425BADCull
+#define DCORE1_TPC5_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE1_TPC5_CFG_QM_BASE 0x425BAE4ull
+#define DCORE1_TPC5_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE1_TPC5_CFG_QM_SECTION 0x31C0
+#define mmDCORE1_TPC5_CFG_AXUSER_BASE 0x425BE00ull
+#define DCORE1_TPC5_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE1_TPC5_CFG_SPECIAL_BASE 0x425BE80ull
+#define DCORE1_TPC5_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC5_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE1_TPC5_MSTR_IF_RR_SHRD_HBW_BASE 0x425C000ull
+#define DCORE1_TPC5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_TPC5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE1_TPC5_MSTR_IF_RR_PRVT_HBW_BASE 0x425C200ull
+#define DCORE1_TPC5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_TPC5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE1_TPC5_MSTR_IF_RR_SHRD_LBW_BASE 0x425C400ull
+#define DCORE1_TPC5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_TPC5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE1_TPC5_MSTR_IF_RR_PRVT_LBW_BASE 0x425C600ull
+#define DCORE1_TPC5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_TPC5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE1_TPC5_MSTR_IF_E2E_CRDT_BASE 0x425C800ull
+#define DCORE1_TPC5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_TPC5_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE1_TPC5_MSTR_IF_AXUSER_BASE 0x425CA80ull
+#define DCORE1_TPC5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_TPC5_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE1_TPC5_MSTR_IF_DBG_HBW_BASE 0x425CB00ull
+#define DCORE1_TPC5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC5_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_TPC5_MSTR_IF_DBG_LBW_BASE 0x425CB80ull
+#define DCORE1_TPC5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_TPC5_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE1_TPC5_MSTR_IF_CORE_HBW_BASE 0x425CC00ull
+#define DCORE1_TPC5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_TPC5_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE1_TPC5_MSTR_IF_CORE_LBW_BASE 0x425CD80ull
+#define DCORE1_TPC5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_TPC5_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE1_TPC5_MSTR_IF_SPECIAL_BASE 0x425CE80ull
+#define DCORE1_TPC5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC5_MSTR_IF_SPECIAL_SECTION 0x23180
+#define mmDCORE1_HMMU0_MMU_BASE 0x4280000ull
+#define DCORE1_HMMU0_MMU_MAX_OFFSET 0x1000
+#define DCORE1_HMMU0_MMU_SECTION 0xE800
+#define mmDCORE1_HMMU0_MMU_SPECIAL_BASE 0x4280E80ull
+#define DCORE1_HMMU0_MMU_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HMMU0_MMU_SPECIAL_SECTION 0x1800
+#define mmDCORE1_HMMU0_STLB_BASE 0x4281000ull
+#define DCORE1_HMMU0_STLB_MAX_OFFSET 0x1000
+#define DCORE1_HMMU0_STLB_SECTION 0xE800
+#define mmDCORE1_HMMU0_STLB_SPECIAL_BASE 0x4281E80ull
+#define DCORE1_HMMU0_STLB_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HMMU0_STLB_SPECIAL_SECTION 0x1180
+#define mmDCORE1_HMMU0_SCRAMB_OUT_BASE 0x4283000ull
+#define DCORE1_HMMU0_SCRAMB_OUT_MAX_OFFSET 0x1000
+#define DCORE1_HMMU0_SCRAMB_OUT_SECTION 0xE800
+#define mmDCORE1_HMMU0_SCRAMB_OUT_SPECIAL_BASE 0x4283E80ull
+#define DCORE1_HMMU0_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HMMU0_SCRAMB_OUT_SPECIAL_SECTION 0x1800
+#define mmDCORE1_HMMU0_MSTR_IF_RR_SHRD_HBW_BASE 0x4284000ull
+#define DCORE1_HMMU0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_HMMU0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE1_HMMU0_MSTR_IF_RR_PRVT_HBW_BASE 0x4284200ull
+#define DCORE1_HMMU0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_HMMU0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE1_HMMU0_MSTR_IF_RR_SHRD_LBW_BASE 0x4284400ull
+#define DCORE1_HMMU0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_HMMU0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE1_HMMU0_MSTR_IF_RR_PRVT_LBW_BASE 0x4284600ull
+#define DCORE1_HMMU0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_HMMU0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE1_HMMU0_MSTR_IF_E2E_CRDT_BASE 0x4284800ull
+#define DCORE1_HMMU0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_HMMU0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE1_HMMU0_MSTR_IF_AXUSER_BASE 0x4284A80ull
+#define DCORE1_HMMU0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_HMMU0_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE1_HMMU0_MSTR_IF_DBG_HBW_BASE 0x4284B00ull
+#define DCORE1_HMMU0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_HMMU0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_HMMU0_MSTR_IF_DBG_LBW_BASE 0x4284B80ull
+#define DCORE1_HMMU0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_HMMU0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE1_HMMU0_MSTR_IF_CORE_HBW_BASE 0x4284C00ull
+#define DCORE1_HMMU0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_HMMU0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE1_HMMU0_MSTR_IF_CORE_LBW_BASE 0x4284D80ull
+#define DCORE1_HMMU0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_HMMU0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE1_HMMU0_MSTR_IF_SPECIAL_BASE 0x4284E80ull
+#define DCORE1_HMMU0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HMMU0_MSTR_IF_SPECIAL_SECTION 0xB180
+#define mmDCORE1_HMMU1_MMU_BASE 0x4290000ull
+#define DCORE1_HMMU1_MMU_MAX_OFFSET 0x1000
+#define DCORE1_HMMU1_MMU_SECTION 0xE800
+#define mmDCORE1_HMMU1_MMU_SPECIAL_BASE 0x4290E80ull
+#define DCORE1_HMMU1_MMU_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HMMU1_MMU_SPECIAL_SECTION 0x1800
+#define mmDCORE1_HMMU1_STLB_BASE 0x4291000ull
+#define DCORE1_HMMU1_STLB_MAX_OFFSET 0x1000
+#define DCORE1_HMMU1_STLB_SECTION 0xE800
+#define mmDCORE1_HMMU1_STLB_SPECIAL_BASE 0x4291E80ull
+#define DCORE1_HMMU1_STLB_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HMMU1_STLB_SPECIAL_SECTION 0x1180
+#define mmDCORE1_HMMU1_SCRAMB_OUT_BASE 0x4293000ull
+#define DCORE1_HMMU1_SCRAMB_OUT_MAX_OFFSET 0x1000
+#define DCORE1_HMMU1_SCRAMB_OUT_SECTION 0xE800
+#define mmDCORE1_HMMU1_SCRAMB_OUT_SPECIAL_BASE 0x4293E80ull
+#define DCORE1_HMMU1_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HMMU1_SCRAMB_OUT_SPECIAL_SECTION 0x1800
+#define mmDCORE1_HMMU1_MSTR_IF_RR_SHRD_HBW_BASE 0x4294000ull
+#define DCORE1_HMMU1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_HMMU1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE1_HMMU1_MSTR_IF_RR_PRVT_HBW_BASE 0x4294200ull
+#define DCORE1_HMMU1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_HMMU1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE1_HMMU1_MSTR_IF_RR_SHRD_LBW_BASE 0x4294400ull
+#define DCORE1_HMMU1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_HMMU1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE1_HMMU1_MSTR_IF_RR_PRVT_LBW_BASE 0x4294600ull
+#define DCORE1_HMMU1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_HMMU1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE1_HMMU1_MSTR_IF_E2E_CRDT_BASE 0x4294800ull
+#define DCORE1_HMMU1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_HMMU1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE1_HMMU1_MSTR_IF_AXUSER_BASE 0x4294A80ull
+#define DCORE1_HMMU1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_HMMU1_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE1_HMMU1_MSTR_IF_DBG_HBW_BASE 0x4294B00ull
+#define DCORE1_HMMU1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_HMMU1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_HMMU1_MSTR_IF_DBG_LBW_BASE 0x4294B80ull
+#define DCORE1_HMMU1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_HMMU1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE1_HMMU1_MSTR_IF_CORE_HBW_BASE 0x4294C00ull
+#define DCORE1_HMMU1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_HMMU1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE1_HMMU1_MSTR_IF_CORE_LBW_BASE 0x4294D80ull
+#define DCORE1_HMMU1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_HMMU1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE1_HMMU1_MSTR_IF_SPECIAL_BASE 0x4294E80ull
+#define DCORE1_HMMU1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HMMU1_MSTR_IF_SPECIAL_SECTION 0xB180
+#define mmDCORE1_HMMU2_MMU_BASE 0x42A0000ull
+#define DCORE1_HMMU2_MMU_MAX_OFFSET 0x1000
+#define DCORE1_HMMU2_MMU_SECTION 0xE800
+#define mmDCORE1_HMMU2_MMU_SPECIAL_BASE 0x42A0E80ull
+#define DCORE1_HMMU2_MMU_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HMMU2_MMU_SPECIAL_SECTION 0x1800
+#define mmDCORE1_HMMU2_STLB_BASE 0x42A1000ull
+#define DCORE1_HMMU2_STLB_MAX_OFFSET 0x1000
+#define DCORE1_HMMU2_STLB_SECTION 0xE800
+#define mmDCORE1_HMMU2_STLB_SPECIAL_BASE 0x42A1E80ull
+#define DCORE1_HMMU2_STLB_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HMMU2_STLB_SPECIAL_SECTION 0x1180
+#define mmDCORE1_HMMU2_SCRAMB_OUT_BASE 0x42A3000ull
+#define DCORE1_HMMU2_SCRAMB_OUT_MAX_OFFSET 0x1000
+#define DCORE1_HMMU2_SCRAMB_OUT_SECTION 0xE800
+#define mmDCORE1_HMMU2_SCRAMB_OUT_SPECIAL_BASE 0x42A3E80ull
+#define DCORE1_HMMU2_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HMMU2_SCRAMB_OUT_SPECIAL_SECTION 0x1800
+#define mmDCORE1_HMMU2_MSTR_IF_RR_SHRD_HBW_BASE 0x42A4000ull
+#define DCORE1_HMMU2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_HMMU2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE1_HMMU2_MSTR_IF_RR_PRVT_HBW_BASE 0x42A4200ull
+#define DCORE1_HMMU2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_HMMU2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE1_HMMU2_MSTR_IF_RR_SHRD_LBW_BASE 0x42A4400ull
+#define DCORE1_HMMU2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_HMMU2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE1_HMMU2_MSTR_IF_RR_PRVT_LBW_BASE 0x42A4600ull
+#define DCORE1_HMMU2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_HMMU2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE1_HMMU2_MSTR_IF_E2E_CRDT_BASE 0x42A4800ull
+#define DCORE1_HMMU2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_HMMU2_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE1_HMMU2_MSTR_IF_AXUSER_BASE 0x42A4A80ull
+#define DCORE1_HMMU2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_HMMU2_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE1_HMMU2_MSTR_IF_DBG_HBW_BASE 0x42A4B00ull
+#define DCORE1_HMMU2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_HMMU2_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_HMMU2_MSTR_IF_DBG_LBW_BASE 0x42A4B80ull
+#define DCORE1_HMMU2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_HMMU2_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE1_HMMU2_MSTR_IF_CORE_HBW_BASE 0x42A4C00ull
+#define DCORE1_HMMU2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_HMMU2_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE1_HMMU2_MSTR_IF_CORE_LBW_BASE 0x42A4D80ull
+#define DCORE1_HMMU2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_HMMU2_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE1_HMMU2_MSTR_IF_SPECIAL_BASE 0x42A4E80ull
+#define DCORE1_HMMU2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HMMU2_MSTR_IF_SPECIAL_SECTION 0xB180
+#define mmDCORE1_HMMU3_MMU_BASE 0x42B0000ull
+#define DCORE1_HMMU3_MMU_MAX_OFFSET 0x1000
+#define DCORE1_HMMU3_MMU_SECTION 0xE800
+#define mmDCORE1_HMMU3_MMU_SPECIAL_BASE 0x42B0E80ull
+#define DCORE1_HMMU3_MMU_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HMMU3_MMU_SPECIAL_SECTION 0x1800
+#define mmDCORE1_HMMU3_STLB_BASE 0x42B1000ull
+#define DCORE1_HMMU3_STLB_MAX_OFFSET 0x1000
+#define DCORE1_HMMU3_STLB_SECTION 0xE800
+#define mmDCORE1_HMMU3_STLB_SPECIAL_BASE 0x42B1E80ull
+#define DCORE1_HMMU3_STLB_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HMMU3_STLB_SPECIAL_SECTION 0x1180
+#define mmDCORE1_HMMU3_SCRAMB_OUT_BASE 0x42B3000ull
+#define DCORE1_HMMU3_SCRAMB_OUT_MAX_OFFSET 0x1000
+#define DCORE1_HMMU3_SCRAMB_OUT_SECTION 0xE800
+#define mmDCORE1_HMMU3_SCRAMB_OUT_SPECIAL_BASE 0x42B3E80ull
+#define DCORE1_HMMU3_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HMMU3_SCRAMB_OUT_SPECIAL_SECTION 0x1800
+#define mmDCORE1_HMMU3_MSTR_IF_RR_SHRD_HBW_BASE 0x42B4000ull
+#define DCORE1_HMMU3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_HMMU3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE1_HMMU3_MSTR_IF_RR_PRVT_HBW_BASE 0x42B4200ull
+#define DCORE1_HMMU3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_HMMU3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE1_HMMU3_MSTR_IF_RR_SHRD_LBW_BASE 0x42B4400ull
+#define DCORE1_HMMU3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_HMMU3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE1_HMMU3_MSTR_IF_RR_PRVT_LBW_BASE 0x42B4600ull
+#define DCORE1_HMMU3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_HMMU3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE1_HMMU3_MSTR_IF_E2E_CRDT_BASE 0x42B4800ull
+#define DCORE1_HMMU3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_HMMU3_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE1_HMMU3_MSTR_IF_AXUSER_BASE 0x42B4A80ull
+#define DCORE1_HMMU3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_HMMU3_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE1_HMMU3_MSTR_IF_DBG_HBW_BASE 0x42B4B00ull
+#define DCORE1_HMMU3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_HMMU3_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_HMMU3_MSTR_IF_DBG_LBW_BASE 0x42B4B80ull
+#define DCORE1_HMMU3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_HMMU3_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE1_HMMU3_MSTR_IF_CORE_HBW_BASE 0x42B4C00ull
+#define DCORE1_HMMU3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_HMMU3_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE1_HMMU3_MSTR_IF_CORE_LBW_BASE 0x42B4D80ull
+#define DCORE1_HMMU3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_HMMU3_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE1_HMMU3_MSTR_IF_SPECIAL_BASE 0x42B4E80ull
+#define DCORE1_HMMU3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HMMU3_MSTR_IF_SPECIAL_SECTION 0xB180
+#define mmDCORE1_MME_QM_ARC_DCCM_BASE 0x42C0000ull
+#define DCORE1_MME_QM_ARC_DCCM_MAX_OFFSET 0x4000
+#define DCORE1_MME_QM_ARC_DCCM_SECTION 0x8000
+#define mmDCORE1_MME_QM_ARC_AUX_BASE 0x42C8000ull
+#define DCORE1_MME_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE1_MME_QM_ARC_AUX_SECTION 0xE800
+#define mmDCORE1_MME_QM_ARC_AUX_SPECIAL_BASE 0x42C8E80ull
+#define DCORE1_MME_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_QM_ARC_AUX_SPECIAL_SECTION 0x1800
+#define mmDCORE1_MME_QM_ARC_DUP_ENG_BASE 0x42C9000ull
+#define DCORE1_MME_QM_ARC_DUP_ENG_MAX_OFFSET 0x1000
+#define DCORE1_MME_QM_ARC_DUP_ENG_SECTION 0x9000
+#define mmDCORE1_MME_QM_ARC_DUP_ENG_AXUSER_BASE 0x42C9900ull
+#define DCORE1_MME_QM_ARC_DUP_ENG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_MME_QM_ARC_DUP_ENG_AXUSER_SECTION 0x5800
+#define mmDCORE1_MME_QM_ARC_DUP_ENG_SPECIAL_BASE 0x42C9E80ull
+#define DCORE1_MME_QM_ARC_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_QM_ARC_DUP_ENG_SPECIAL_SECTION 0x1800
+#define mmDCORE1_MME_QM_BASE 0x42CA000ull
+#define DCORE1_MME_QM_MAX_OFFSET 0x1000
+#define DCORE1_MME_QM_SECTION 0x9000
+#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR0_BASE 0x42CA900ull
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR1_BASE 0x42CA908ull
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR2_BASE 0x42CA910ull
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR3_BASE 0x42CA918ull
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR4_BASE 0x42CA920ull
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR5_BASE 0x42CA928ull
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR6_BASE 0x42CA930ull
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR7_BASE 0x42CA938ull
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR8_BASE 0x42CA940ull
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR9_BASE 0x42CA948ull
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR10_BASE 0x42CA950ull
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR11_BASE 0x42CA958ull
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR12_BASE 0x42CA960ull
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR13_BASE 0x42CA968ull
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR14_BASE 0x42CA970ull
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR15_BASE 0x42CA978ull
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE1_MME_QM_AXUSER_SECURED_BASE 0x42CAB00ull
+#define DCORE1_MME_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE1_MME_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE1_MME_QM_AXUSER_NONSECURED_BASE 0x42CAB80ull
+#define DCORE1_MME_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE1_MME_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE1_MME_QM_DBG_HBW_BASE 0x42CAC00ull
+#define DCORE1_MME_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_MME_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_MME_QM_DBG_LBW_BASE 0x42CAC80ull
+#define DCORE1_MME_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_MME_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE1_MME_QM_CGM_BASE 0x42CAD80ull
+#define DCORE1_MME_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE1_MME_QM_CGM_SECTION 0x1000
+#define mmDCORE1_MME_QM_SPECIAL_BASE 0x42CAE80ull
+#define DCORE1_MME_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE1_MME_CTRL_LO_BASE 0x42CB000ull
+#define DCORE1_MME_CTRL_LO_MAX_OFFSET 0x1000
+#define DCORE1_MME_CTRL_LO_SECTION 0x8000
+#define mmDCORE1_MME_CTRL_LO_ARCH_BASE_ADDR_BASE 0x42CB008ull
+#define DCORE1_MME_CTRL_LO_ARCH_BASE_ADDR_MAX_OFFSET 0x2000
+#define DCORE1_MME_CTRL_LO_ARCH_BASE_ADDR_SECTION 0x2000
+#define mmDCORE1_MME_CTRL_LO_ARCH_NON_TENSOR_START_BASE 0x42CB028ull
+#define DCORE1_MME_CTRL_LO_ARCH_NON_TENSOR_START_MAX_OFFSET 0x1800
+#define DCORE1_MME_CTRL_LO_ARCH_NON_TENSOR_START_SECTION 0x1800
+#define mmDCORE1_MME_CTRL_LO_ARCH_TENSOR_A_BASE 0x42CB040ull
+#define DCORE1_MME_CTRL_LO_ARCH_TENSOR_A_MAX_OFFSET 0x5800
+#define DCORE1_MME_CTRL_LO_ARCH_TENSOR_A_SECTION 0x5800
+#define mmDCORE1_MME_CTRL_LO_ARCH_TENSOR_B_BASE 0x42CB098ull
+#define DCORE1_MME_CTRL_LO_ARCH_TENSOR_B_MAX_OFFSET 0x5800
+#define DCORE1_MME_CTRL_LO_ARCH_TENSOR_B_SECTION 0x5800
+#define mmDCORE1_MME_CTRL_LO_ARCH_TENSOR_COUT_BASE 0x42CB0F0ull
+#define DCORE1_MME_CTRL_LO_ARCH_TENSOR_COUT_MAX_OFFSET 0x5800
+#define DCORE1_MME_CTRL_LO_ARCH_TENSOR_COUT_SECTION 0x6C00
+#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_BASE 0x42CB15Cull
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_BASE 0x42CB170ull
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_BASE 0x42CB184ull
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_BASE 0x42CB198ull
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_BASE 0x42CB1ACull
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_BASE 0x42CB1C0ull
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_BASE 0x42CB1D4ull
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_BASE 0x42CB1E8ull
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_BASE 0x42CB1FCull
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_BASE 0x42CB210ull
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_SECTION 0x1C00
+#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_BASE 0x42CB22Cull
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_BASE 0x42CB240ull
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_BASE 0x42CB254ull
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_BASE 0x42CB268ull
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_SECTION 0x1800
+#define mmDCORE1_MME_CTRL_LO_ARCH_NON_TENSOR_END_BASE 0x42CB280ull
+#define DCORE1_MME_CTRL_LO_ARCH_NON_TENSOR_END_MAX_OFFSET 0x6000
+#define DCORE1_MME_CTRL_LO_ARCH_NON_TENSOR_END_SECTION 0xB800
+#define mmDCORE1_MME_CTRL_LO_MME_AXUSER_BASE 0x42CBE00ull
+#define DCORE1_MME_CTRL_LO_MME_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_MME_CTRL_LO_MME_AXUSER_SECTION 0x8000
+#define mmDCORE1_MME_CTRL_LO_SPECIAL_BASE 0x42CBE80ull
+#define DCORE1_MME_CTRL_LO_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_CTRL_LO_SPECIAL_SECTION 0x1800
+#define mmDCORE1_MME_CTRL_HI_BASE 0x42CC000ull
+#define DCORE1_MME_CTRL_HI_MAX_OFFSET 0x1000
+#define DCORE1_MME_CTRL_HI_SECTION 0x8000
+#define mmDCORE1_MME_CTRL_HI_SHADOW_0_BASE_ADDR_BASE 0x42CC008ull
+#define DCORE1_MME_CTRL_HI_SHADOW_0_BASE_ADDR_MAX_OFFSET 0x2000
+#define DCORE1_MME_CTRL_HI_SHADOW_0_BASE_ADDR_SECTION 0x2000
+#define mmDCORE1_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_BASE 0x42CC028ull
+#define DCORE1_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_MAX_OFFSET 0x1800
+#define DCORE1_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_SECTION 0x1800
+#define mmDCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_A_BASE 0x42CC040ull
+#define DCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_A_MAX_OFFSET 0x5800
+#define DCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_A_SECTION 0x5800
+#define mmDCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_B_BASE 0x42CC098ull
+#define DCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_B_MAX_OFFSET 0x5800
+#define DCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_B_SECTION 0x5800
+#define mmDCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_BASE 0x42CC0F0ull
+#define DCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_MAX_OFFSET 0x5800
+#define DCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_SECTION 0x6C00
+#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_BASE 0x42CC15Cull
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_BASE 0x42CC170ull
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_BASE 0x42CC184ull
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_BASE 0x42CC198ull
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_BASE 0x42CC1ACull
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_BASE 0x42CC1C0ull
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_BASE 0x42CC1D4ull
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_BASE 0x42CC1E8ull
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_BASE 0x42CC1FCull
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_BASE 0x42CC210ull
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_SECTION 0x1C00
+#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_BASE 0x42CC22Cull
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_BASE 0x42CC240ull
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_BASE 0x42CC254ull
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_BASE 0x42CC268ull
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_SECTION 0x1800
+#define mmDCORE1_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_BASE 0x42CC280ull
+#define DCORE1_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_MAX_OFFSET 0x6000
+#define DCORE1_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_SECTION 0x8800
+#define mmDCORE1_MME_CTRL_HI_SHADOW_1_BASE_ADDR_BASE 0x42CC308ull
+#define DCORE1_MME_CTRL_HI_SHADOW_1_BASE_ADDR_MAX_OFFSET 0x2000
+#define DCORE1_MME_CTRL_HI_SHADOW_1_BASE_ADDR_SECTION 0x2000
+#define mmDCORE1_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_BASE 0x42CC328ull
+#define DCORE1_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_MAX_OFFSET 0x1800
+#define DCORE1_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_SECTION 0x1800
+#define mmDCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_A_BASE 0x42CC340ull
+#define DCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_A_MAX_OFFSET 0x5800
+#define DCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_A_SECTION 0x5800
+#define mmDCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_B_BASE 0x42CC398ull
+#define DCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_B_MAX_OFFSET 0x5800
+#define DCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_B_SECTION 0x5800
+#define mmDCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_BASE 0x42CC3F0ull
+#define DCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_MAX_OFFSET 0x5800
+#define DCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_SECTION 0x6C00
+#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_BASE 0x42CC45Cull
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_BASE 0x42CC470ull
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_BASE 0x42CC484ull
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_BASE 0x42CC498ull
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_BASE 0x42CC4ACull
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_BASE 0x42CC4C0ull
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_BASE 0x42CC4D4ull
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_BASE 0x42CC4E8ull
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_BASE 0x42CC4FCull
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_BASE 0x42CC510ull
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_SECTION 0x1C00
+#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_BASE 0x42CC52Cull
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_BASE 0x42CC540ull
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_BASE 0x42CC554ull
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_BASE 0x42CC568ull
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_SECTION 0x1800
+#define mmDCORE1_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_BASE 0x42CC580ull
+#define DCORE1_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_MAX_OFFSET 0x6000
+#define DCORE1_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_SECTION 0x8800
+#define mmDCORE1_MME_CTRL_HI_SHADOW_2_BASE_ADDR_BASE 0x42CC608ull
+#define DCORE1_MME_CTRL_HI_SHADOW_2_BASE_ADDR_MAX_OFFSET 0x2000
+#define DCORE1_MME_CTRL_HI_SHADOW_2_BASE_ADDR_SECTION 0x2000
+#define mmDCORE1_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_BASE 0x42CC628ull
+#define DCORE1_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_MAX_OFFSET 0x1800
+#define DCORE1_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_SECTION 0x1800
+#define mmDCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_A_BASE 0x42CC640ull
+#define DCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_A_MAX_OFFSET 0x5800
+#define DCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_A_SECTION 0x5800
+#define mmDCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_B_BASE 0x42CC698ull
+#define DCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_B_MAX_OFFSET 0x5800
+#define DCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_B_SECTION 0x5800
+#define mmDCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_BASE 0x42CC6F0ull
+#define DCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_MAX_OFFSET 0x5800
+#define DCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_SECTION 0x6C00
+#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_BASE 0x42CC75Cull
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_BASE 0x42CC770ull
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_BASE 0x42CC784ull
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_BASE 0x42CC798ull
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_BASE 0x42CC7ACull
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_BASE 0x42CC7C0ull
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_BASE 0x42CC7D4ull
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_BASE 0x42CC7E8ull
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_BASE 0x42CC7FCull
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_BASE 0x42CC810ull
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_SECTION 0x1C00
+#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_BASE 0x42CC82Cull
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_BASE 0x42CC840ull
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_BASE 0x42CC854ull
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_BASE 0x42CC868ull
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_SECTION 0x1800
+#define mmDCORE1_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_BASE 0x42CC880ull
+#define DCORE1_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_MAX_OFFSET 0x6000
+#define DCORE1_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_SECTION 0x8800
+#define mmDCORE1_MME_CTRL_HI_SHADOW_3_BASE_ADDR_BASE 0x42CC908ull
+#define DCORE1_MME_CTRL_HI_SHADOW_3_BASE_ADDR_MAX_OFFSET 0x2000
+#define DCORE1_MME_CTRL_HI_SHADOW_3_BASE_ADDR_SECTION 0x2000
+#define mmDCORE1_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_BASE 0x42CC928ull
+#define DCORE1_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_MAX_OFFSET 0x1800
+#define DCORE1_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_SECTION 0x1800
+#define mmDCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_A_BASE 0x42CC940ull
+#define DCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_A_MAX_OFFSET 0x5800
+#define DCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_A_SECTION 0x5800
+#define mmDCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_B_BASE 0x42CC998ull
+#define DCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_B_MAX_OFFSET 0x5800
+#define DCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_B_SECTION 0x5800
+#define mmDCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_BASE 0x42CC9F0ull
+#define DCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_MAX_OFFSET 0x5800
+#define DCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_SECTION 0x6C00
+#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_BASE 0x42CCA5Cull
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_BASE 0x42CCA70ull
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_BASE 0x42CCA84ull
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_BASE 0x42CCA98ull
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_BASE 0x42CCAACull
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_BASE 0x42CCAC0ull
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_BASE 0x42CCAD4ull
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_BASE 0x42CCAE8ull
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_BASE 0x42CCAFCull
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_BASE 0x42CCB10ull
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_SECTION 0x1C00
+#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_BASE 0x42CCB2Cull
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_BASE 0x42CCB40ull
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_BASE 0x42CCB54ull
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_SECTION 0x1400
+#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_BASE 0x42CCB68ull
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_SECTION 0x1800
+#define mmDCORE1_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_BASE 0x42CCB80ull
+#define DCORE1_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_MAX_OFFSET 0x6000
+#define DCORE1_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_SECTION 0x3000
+#define mmDCORE1_MME_CTRL_HI_SPECIAL_BASE 0x42CCE80ull
+#define DCORE1_MME_CTRL_HI_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_CTRL_HI_SPECIAL_SECTION 0x1800
+#define mmDCORE1_MME_EU_BIST_BASE 0x42CD000ull
+#define DCORE1_MME_EU_BIST_MAX_OFFSET 0x1000
+#define DCORE1_MME_EU_BIST_SECTION 0xE800
+#define mmDCORE1_MME_EU_BIST_SPECIAL_BASE 0x42CDE80ull
+#define DCORE1_MME_EU_BIST_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_EU_BIST_SPECIAL_SECTION 0x1800
+#define mmDCORE1_MME_CTRL_MSTR_IF_RR_SHRD_HBW_BASE 0x42CE000ull
+#define DCORE1_MME_CTRL_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_MME_CTRL_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE1_MME_CTRL_MSTR_IF_RR_PRVT_HBW_BASE 0x42CE200ull
+#define DCORE1_MME_CTRL_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_MME_CTRL_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE1_MME_CTRL_MSTR_IF_RR_SHRD_LBW_BASE 0x42CE400ull
+#define DCORE1_MME_CTRL_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_MME_CTRL_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE1_MME_CTRL_MSTR_IF_RR_PRVT_LBW_BASE 0x42CE600ull
+#define DCORE1_MME_CTRL_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_MME_CTRL_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE1_MME_CTRL_MSTR_IF_E2E_CRDT_BASE 0x42CE800ull
+#define DCORE1_MME_CTRL_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_MME_CTRL_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE1_MME_CTRL_MSTR_IF_AXUSER_BASE 0x42CEA80ull
+#define DCORE1_MME_CTRL_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_MME_CTRL_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE1_MME_CTRL_MSTR_IF_DBG_HBW_BASE 0x42CEB00ull
+#define DCORE1_MME_CTRL_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_MME_CTRL_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_MME_CTRL_MSTR_IF_DBG_LBW_BASE 0x42CEB80ull
+#define DCORE1_MME_CTRL_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_MME_CTRL_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE1_MME_CTRL_MSTR_IF_CORE_HBW_BASE 0x42CEC00ull
+#define DCORE1_MME_CTRL_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_MME_CTRL_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE1_MME_CTRL_MSTR_IF_CORE_LBW_BASE 0x42CED80ull
+#define DCORE1_MME_CTRL_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_MME_CTRL_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE1_MME_CTRL_MSTR_IF_SPECIAL_BASE 0x42CEE80ull
+#define DCORE1_MME_CTRL_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_CTRL_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE1_MME_QM_ARC_ACP_ENG_BASE 0x42CF000ull
+#define DCORE1_MME_QM_ARC_ACP_ENG_MAX_OFFSET 0x1000
+#define DCORE1_MME_QM_ARC_ACP_ENG_SECTION 0xE800
+#define mmDCORE1_MME_QM_ARC_ACP_ENG_SPECIAL_BASE 0x42CFE80ull
+#define DCORE1_MME_QM_ARC_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_QM_ARC_ACP_ENG_SPECIAL_SECTION 0x1800
+#define mmDCORE1_MME_SBTE0_BASE 0x42D0000ull
+#define DCORE1_MME_SBTE0_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE0_SECTION 0xE800
+#define mmDCORE1_MME_SBTE0_SPECIAL_BASE 0x42D0E80ull
+#define DCORE1_MME_SBTE0_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_SBTE0_SPECIAL_SECTION 0x1800
+#define mmDCORE1_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_BASE 0x42D1000ull
+#define DCORE1_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE1_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_BASE 0x42D1200ull
+#define DCORE1_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE1_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_BASE 0x42D1400ull
+#define DCORE1_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE1_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_BASE 0x42D1600ull
+#define DCORE1_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE1_MME_SBTE0_MSTR_IF_E2E_CRDT_BASE 0x42D1800ull
+#define DCORE1_MME_SBTE0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_MME_SBTE0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE1_MME_SBTE0_MSTR_IF_AXUSER_BASE 0x42D1A80ull
+#define DCORE1_MME_SBTE0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_MME_SBTE0_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE1_MME_SBTE0_MSTR_IF_DBG_HBW_BASE 0x42D1B00ull
+#define DCORE1_MME_SBTE0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_MME_SBTE0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_MME_SBTE0_MSTR_IF_DBG_LBW_BASE 0x42D1B80ull
+#define DCORE1_MME_SBTE0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_MME_SBTE0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE1_MME_SBTE0_MSTR_IF_CORE_HBW_BASE 0x42D1C00ull
+#define DCORE1_MME_SBTE0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_MME_SBTE0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE1_MME_SBTE0_MSTR_IF_CORE_LBW_BASE 0x42D1D80ull
+#define DCORE1_MME_SBTE0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_MME_SBTE0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE1_MME_SBTE0_MSTR_IF_SPECIAL_BASE 0x42D1E80ull
+#define DCORE1_MME_SBTE0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_SBTE0_MSTR_IF_SPECIAL_SECTION 0x6180
+#define mmDCORE1_MME_SBTE1_BASE 0x42D8000ull
+#define DCORE1_MME_SBTE1_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE1_SECTION 0xE800
+#define mmDCORE1_MME_SBTE1_SPECIAL_BASE 0x42D8E80ull
+#define DCORE1_MME_SBTE1_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_SBTE1_SPECIAL_SECTION 0x1800
+#define mmDCORE1_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_BASE 0x42D9000ull
+#define DCORE1_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE1_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_BASE 0x42D9200ull
+#define DCORE1_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE1_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_BASE 0x42D9400ull
+#define DCORE1_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE1_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_BASE 0x42D9600ull
+#define DCORE1_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE1_MME_SBTE1_MSTR_IF_E2E_CRDT_BASE 0x42D9800ull
+#define DCORE1_MME_SBTE1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_MME_SBTE1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE1_MME_SBTE1_MSTR_IF_AXUSER_BASE 0x42D9A80ull
+#define DCORE1_MME_SBTE1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_MME_SBTE1_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE1_MME_SBTE1_MSTR_IF_DBG_HBW_BASE 0x42D9B00ull
+#define DCORE1_MME_SBTE1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_MME_SBTE1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_MME_SBTE1_MSTR_IF_DBG_LBW_BASE 0x42D9B80ull
+#define DCORE1_MME_SBTE1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_MME_SBTE1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE1_MME_SBTE1_MSTR_IF_CORE_HBW_BASE 0x42D9C00ull
+#define DCORE1_MME_SBTE1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_MME_SBTE1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE1_MME_SBTE1_MSTR_IF_CORE_LBW_BASE 0x42D9D80ull
+#define DCORE1_MME_SBTE1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_MME_SBTE1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE1_MME_SBTE1_MSTR_IF_SPECIAL_BASE 0x42D9E80ull
+#define DCORE1_MME_SBTE1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_SBTE1_MSTR_IF_SPECIAL_SECTION 0x6180
+#define mmDCORE1_MME_SBTE2_BASE 0x42E0000ull
+#define DCORE1_MME_SBTE2_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE2_SECTION 0xE800
+#define mmDCORE1_MME_SBTE2_SPECIAL_BASE 0x42E0E80ull
+#define DCORE1_MME_SBTE2_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_SBTE2_SPECIAL_SECTION 0x1800
+#define mmDCORE1_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_BASE 0x42E1000ull
+#define DCORE1_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE1_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_BASE 0x42E1200ull
+#define DCORE1_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE1_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_BASE 0x42E1400ull
+#define DCORE1_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE1_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_BASE 0x42E1600ull
+#define DCORE1_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE1_MME_SBTE2_MSTR_IF_E2E_CRDT_BASE 0x42E1800ull
+#define DCORE1_MME_SBTE2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_MME_SBTE2_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE1_MME_SBTE2_MSTR_IF_AXUSER_BASE 0x42E1A80ull
+#define DCORE1_MME_SBTE2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_MME_SBTE2_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE1_MME_SBTE2_MSTR_IF_DBG_HBW_BASE 0x42E1B00ull
+#define DCORE1_MME_SBTE2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_MME_SBTE2_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_MME_SBTE2_MSTR_IF_DBG_LBW_BASE 0x42E1B80ull
+#define DCORE1_MME_SBTE2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_MME_SBTE2_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE1_MME_SBTE2_MSTR_IF_CORE_HBW_BASE 0x42E1C00ull
+#define DCORE1_MME_SBTE2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_MME_SBTE2_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE1_MME_SBTE2_MSTR_IF_CORE_LBW_BASE 0x42E1D80ull
+#define DCORE1_MME_SBTE2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_MME_SBTE2_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE1_MME_SBTE2_MSTR_IF_SPECIAL_BASE 0x42E1E80ull
+#define DCORE1_MME_SBTE2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_SBTE2_MSTR_IF_SPECIAL_SECTION 0x6180
+#define mmDCORE1_MME_SBTE3_BASE 0x42E8000ull
+#define DCORE1_MME_SBTE3_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE3_SECTION 0xE800
+#define mmDCORE1_MME_SBTE3_SPECIAL_BASE 0x42E8E80ull
+#define DCORE1_MME_SBTE3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_SBTE3_SPECIAL_SECTION 0x1800
+#define mmDCORE1_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_BASE 0x42E9000ull
+#define DCORE1_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE1_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_BASE 0x42E9200ull
+#define DCORE1_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE1_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_BASE 0x42E9400ull
+#define DCORE1_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE1_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_BASE 0x42E9600ull
+#define DCORE1_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE1_MME_SBTE3_MSTR_IF_E2E_CRDT_BASE 0x42E9800ull
+#define DCORE1_MME_SBTE3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_MME_SBTE3_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE1_MME_SBTE3_MSTR_IF_AXUSER_BASE 0x42E9A80ull
+#define DCORE1_MME_SBTE3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_MME_SBTE3_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE1_MME_SBTE3_MSTR_IF_DBG_HBW_BASE 0x42E9B00ull
+#define DCORE1_MME_SBTE3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_MME_SBTE3_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_MME_SBTE3_MSTR_IF_DBG_LBW_BASE 0x42E9B80ull
+#define DCORE1_MME_SBTE3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_MME_SBTE3_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE1_MME_SBTE3_MSTR_IF_CORE_HBW_BASE 0x42E9C00ull
+#define DCORE1_MME_SBTE3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_MME_SBTE3_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE1_MME_SBTE3_MSTR_IF_CORE_LBW_BASE 0x42E9D80ull
+#define DCORE1_MME_SBTE3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_MME_SBTE3_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE1_MME_SBTE3_MSTR_IF_SPECIAL_BASE 0x42E9E80ull
+#define DCORE1_MME_SBTE3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_SBTE3_MSTR_IF_SPECIAL_SECTION 0x6180
+#define mmDCORE1_MME_SBTE4_BASE 0x42F0000ull
+#define DCORE1_MME_SBTE4_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE4_SECTION 0xE800
+#define mmDCORE1_MME_SBTE4_SPECIAL_BASE 0x42F0E80ull
+#define DCORE1_MME_SBTE4_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_SBTE4_SPECIAL_SECTION 0x1800
+#define mmDCORE1_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_BASE 0x42F1000ull
+#define DCORE1_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE1_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_BASE 0x42F1200ull
+#define DCORE1_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE1_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_BASE 0x42F1400ull
+#define DCORE1_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE1_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_BASE 0x42F1600ull
+#define DCORE1_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE1_MME_SBTE4_MSTR_IF_E2E_CRDT_BASE 0x42F1800ull
+#define DCORE1_MME_SBTE4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_MME_SBTE4_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE1_MME_SBTE4_MSTR_IF_AXUSER_BASE 0x42F1A80ull
+#define DCORE1_MME_SBTE4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_MME_SBTE4_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE1_MME_SBTE4_MSTR_IF_DBG_HBW_BASE 0x42F1B00ull
+#define DCORE1_MME_SBTE4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_MME_SBTE4_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_MME_SBTE4_MSTR_IF_DBG_LBW_BASE 0x42F1B80ull
+#define DCORE1_MME_SBTE4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_MME_SBTE4_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE1_MME_SBTE4_MSTR_IF_CORE_HBW_BASE 0x42F1C00ull
+#define DCORE1_MME_SBTE4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_MME_SBTE4_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE1_MME_SBTE4_MSTR_IF_CORE_LBW_BASE 0x42F1D80ull
+#define DCORE1_MME_SBTE4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_MME_SBTE4_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE1_MME_SBTE4_MSTR_IF_SPECIAL_BASE 0x42F1E80ull
+#define DCORE1_MME_SBTE4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_SBTE4_MSTR_IF_SPECIAL_SECTION 0x6180
+#define mmDCORE1_MME_ACC_BASE 0x42F8000ull
+#define DCORE1_MME_ACC_MAX_OFFSET 0x1000
+#define DCORE1_MME_ACC_SECTION 0xE800
+#define mmDCORE1_MME_ACC_SPECIAL_BASE 0x42F8E80ull
+#define DCORE1_MME_ACC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_ACC_SPECIAL_SECTION 0x1800
+#define mmDCORE1_MME_WB0_MSTR_IF_RR_SHRD_HBW_BASE 0x42F9000ull
+#define DCORE1_MME_WB0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_MME_WB0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE1_MME_WB0_MSTR_IF_RR_PRVT_HBW_BASE 0x42F9200ull
+#define DCORE1_MME_WB0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_MME_WB0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE1_MME_WB0_MSTR_IF_RR_SHRD_LBW_BASE 0x42F9400ull
+#define DCORE1_MME_WB0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_MME_WB0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE1_MME_WB0_MSTR_IF_RR_PRVT_LBW_BASE 0x42F9600ull
+#define DCORE1_MME_WB0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_MME_WB0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE1_MME_WB0_MSTR_IF_E2E_CRDT_BASE 0x42F9800ull
+#define DCORE1_MME_WB0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_MME_WB0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE1_MME_WB0_MSTR_IF_AXUSER_BASE 0x42F9A80ull
+#define DCORE1_MME_WB0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_MME_WB0_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE1_MME_WB0_MSTR_IF_DBG_HBW_BASE 0x42F9B00ull
+#define DCORE1_MME_WB0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_MME_WB0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_MME_WB0_MSTR_IF_DBG_LBW_BASE 0x42F9B80ull
+#define DCORE1_MME_WB0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_MME_WB0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE1_MME_WB0_MSTR_IF_CORE_HBW_BASE 0x42F9C00ull
+#define DCORE1_MME_WB0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_MME_WB0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE1_MME_WB0_MSTR_IF_CORE_LBW_BASE 0x42F9D80ull
+#define DCORE1_MME_WB0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_MME_WB0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE1_MME_WB0_MSTR_IF_SPECIAL_BASE 0x42F9E80ull
+#define DCORE1_MME_WB0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_WB0_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE1_MME_WB1_MSTR_IF_RR_SHRD_HBW_BASE 0x42FA000ull
+#define DCORE1_MME_WB1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_MME_WB1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE1_MME_WB1_MSTR_IF_RR_PRVT_HBW_BASE 0x42FA200ull
+#define DCORE1_MME_WB1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_MME_WB1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE1_MME_WB1_MSTR_IF_RR_SHRD_LBW_BASE 0x42FA400ull
+#define DCORE1_MME_WB1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_MME_WB1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE1_MME_WB1_MSTR_IF_RR_PRVT_LBW_BASE 0x42FA600ull
+#define DCORE1_MME_WB1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_MME_WB1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE1_MME_WB1_MSTR_IF_E2E_CRDT_BASE 0x42FA800ull
+#define DCORE1_MME_WB1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_MME_WB1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE1_MME_WB1_MSTR_IF_AXUSER_BASE 0x42FAA80ull
+#define DCORE1_MME_WB1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_MME_WB1_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE1_MME_WB1_MSTR_IF_DBG_HBW_BASE 0x42FAB00ull
+#define DCORE1_MME_WB1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_MME_WB1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_MME_WB1_MSTR_IF_DBG_LBW_BASE 0x42FAB80ull
+#define DCORE1_MME_WB1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_MME_WB1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE1_MME_WB1_MSTR_IF_CORE_HBW_BASE 0x42FAC00ull
+#define DCORE1_MME_WB1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_MME_WB1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE1_MME_WB1_MSTR_IF_CORE_LBW_BASE 0x42FAD80ull
+#define DCORE1_MME_WB1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_MME_WB1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE1_MME_WB1_MSTR_IF_SPECIAL_BASE 0x42FAE80ull
+#define DCORE1_MME_WB1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_MME_WB1_MSTR_IF_SPECIAL_SECTION 0x5180
+#define mmDCORE1_SYNC_MNGR_OBJS_BASE 0x4300000ull
+#define DCORE1_SYNC_MNGR_OBJS_MAX_OFFSET 0x15A00
+#define DCORE1_SYNC_MNGR_OBJS_SECTION 0x1E000
+#define mmDCORE1_SYNC_MNGR_GLBL_BASE 0x431E000ull
+#define DCORE1_SYNC_MNGR_GLBL_MAX_OFFSET 0x1000
+#define DCORE1_SYNC_MNGR_GLBL_SECTION 0xE800
+#define mmDCORE1_SYNC_MNGR_GLBL_SPECIAL_BASE 0x431EE80ull
+#define DCORE1_SYNC_MNGR_GLBL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SYNC_MNGR_GLBL_SPECIAL_SECTION 0x1800
+#define mmDCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_BASE 0x431F000ull
+#define DCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_BASE 0x431F200ull
+#define DCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_BASE 0x431F400ull
+#define DCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_BASE 0x431F600ull
+#define DCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE1_SYNC_MNGR_MSTR_IF_E2E_CRDT_BASE 0x431F800ull
+#define DCORE1_SYNC_MNGR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_SYNC_MNGR_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE1_SYNC_MNGR_MSTR_IF_AXUSER_BASE 0x431FA80ull
+#define DCORE1_SYNC_MNGR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_SYNC_MNGR_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE1_SYNC_MNGR_MSTR_IF_DBG_HBW_BASE 0x431FB00ull
+#define DCORE1_SYNC_MNGR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_SYNC_MNGR_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_SYNC_MNGR_MSTR_IF_DBG_LBW_BASE 0x431FB80ull
+#define DCORE1_SYNC_MNGR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_SYNC_MNGR_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE1_SYNC_MNGR_MSTR_IF_CORE_HBW_BASE 0x431FC00ull
+#define DCORE1_SYNC_MNGR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_SYNC_MNGR_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE1_SYNC_MNGR_MSTR_IF_CORE_LBW_BASE 0x431FD80ull
+#define DCORE1_SYNC_MNGR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_SYNC_MNGR_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE1_SYNC_MNGR_MSTR_IF_SPECIAL_BASE 0x431FE80ull
+#define DCORE1_SYNC_MNGR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SYNC_MNGR_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE1_HIF0_BASE 0x4320000ull
+#define DCORE1_HIF0_MAX_OFFSET 0x1000
+#define DCORE1_HIF0_SECTION 0xE800
+#define mmDCORE1_HIF0_SPECIAL_BASE 0x4320E80ull
+#define DCORE1_HIF0_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HIF0_SPECIAL_SECTION 0x3180
+#define mmDCORE1_HIF1_BASE 0x4324000ull
+#define DCORE1_HIF1_MAX_OFFSET 0x1000
+#define DCORE1_HIF1_SECTION 0xE800
+#define mmDCORE1_HIF1_SPECIAL_BASE 0x4324E80ull
+#define DCORE1_HIF1_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HIF1_SPECIAL_SECTION 0x3180
+#define mmDCORE1_HIF2_BASE 0x4328000ull
+#define DCORE1_HIF2_MAX_OFFSET 0x1000
+#define DCORE1_HIF2_SECTION 0xE800
+#define mmDCORE1_HIF2_SPECIAL_BASE 0x4328E80ull
+#define DCORE1_HIF2_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HIF2_SPECIAL_SECTION 0x3180
+#define mmDCORE1_HIF3_BASE 0x432C000ull
+#define DCORE1_HIF3_MAX_OFFSET 0x1000
+#define DCORE1_HIF3_SECTION 0xE800
+#define mmDCORE1_HIF3_SPECIAL_BASE 0x432CE80ull
+#define DCORE1_HIF3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HIF3_SPECIAL_SECTION 0x13180
+#define mmDCORE1_RTR0_CTRL_BASE 0x4340000ull
+#define DCORE1_RTR0_CTRL_MAX_OFFSET 0x1000
+#define DCORE1_RTR0_CTRL_SECTION 0xE800
+#define mmDCORE1_RTR0_CTRL_SPECIAL_BASE 0x4340E80ull
+#define DCORE1_RTR0_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR0_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE1_RTR0_H3_BASE 0x4341000ull
+#define DCORE1_RTR0_H3_MAX_OFFSET 0x1000
+#define DCORE1_RTR0_H3_SECTION 0xE800
+#define mmDCORE1_RTR0_H3_SPECIAL_BASE 0x4341E80ull
+#define DCORE1_RTR0_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR0_H3_SPECIAL_SECTION 0x1800
+#define mmDCORE1_RTR0_MSTR_IF_RR_SHRD_HBW_BASE 0x4342000ull
+#define DCORE1_RTR0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_RTR0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE1_RTR0_MSTR_IF_RR_PRVT_HBW_BASE 0x4342200ull
+#define DCORE1_RTR0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_RTR0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE1_RTR0_MSTR_IF_RR_SHRD_LBW_BASE 0x4342400ull
+#define DCORE1_RTR0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_RTR0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE1_RTR0_MSTR_IF_RR_PRVT_LBW_BASE 0x4342600ull
+#define DCORE1_RTR0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_RTR0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE1_RTR0_MSTR_IF_E2E_CRDT_BASE 0x4342800ull
+#define DCORE1_RTR0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_RTR0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE1_RTR0_MSTR_IF_AXUSER_BASE 0x4342A80ull
+#define DCORE1_RTR0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_RTR0_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE1_RTR0_MSTR_IF_DBG_HBW_BASE 0x4342B00ull
+#define DCORE1_RTR0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_RTR0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_RTR0_MSTR_IF_DBG_LBW_BASE 0x4342B80ull
+#define DCORE1_RTR0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_RTR0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE1_RTR0_MSTR_IF_CORE_HBW_BASE 0x4342C00ull
+#define DCORE1_RTR0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_RTR0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE1_RTR0_MSTR_IF_CORE_LBW_BASE 0x4342D80ull
+#define DCORE1_RTR0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_RTR0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE1_RTR0_MSTR_IF_SPECIAL_BASE 0x4342E80ull
+#define DCORE1_RTR0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR0_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE1_RTR0_ADD_DEC_HBW_BASE 0x4343000ull
+#define DCORE1_RTR0_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE1_RTR0_ADD_DEC_HBW_SECTION 0x4000
+#define mmDCORE1_RTR0_ADD_DEC_LBW_BASE 0x4343400ull
+#define DCORE1_RTR0_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE1_RTR0_ADD_DEC_LBW_SECTION 0xA800
+#define mmDCORE1_RTR0_ADD_DEC_SPECIAL_BASE 0x4343E80ull
+#define DCORE1_RTR0_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR0_ADD_DEC_SPECIAL_SECTION 0x1800
+#define mmDCORE1_RTR0_BASE 0x4344000ull
+#define DCORE1_RTR0_MAX_OFFSET 0x1000
+#define DCORE1_RTR0_SECTION 0x3000
+#define mmDCORE1_RTR0_HBW_RD_RQ_LL_STAT_BASE 0x4344300ull
+#define DCORE1_RTR0_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR0_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR0_HBW_RD_RS_LL_STAT_BASE 0x4344340ull
+#define DCORE1_RTR0_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR0_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR0_HBW_WR_RQ_LL_STAT_BASE 0x4344380ull
+#define DCORE1_RTR0_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR0_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR0_HBW_WR_RS_LL_STAT_BASE 0x43443C0ull
+#define DCORE1_RTR0_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR0_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR0_LBW_RD_RQ_LL_STAT_BASE 0x4344400ull
+#define DCORE1_RTR0_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR0_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR0_LBW_RD_RS_LL_STAT_BASE 0x4344440ull
+#define DCORE1_RTR0_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR0_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR0_LBW_WR_RQ_LL_STAT_BASE 0x4344480ull
+#define DCORE1_RTR0_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR0_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR0_LBW_WR_RS_LL_STAT_BASE 0x43444C0ull
+#define DCORE1_RTR0_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR0_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR0_HBW_MFIFO_BASE 0x4344500ull
+#define DCORE1_RTR0_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE1_RTR0_HBW_MFIFO_SECTION 0x4000
+#define mmDCORE1_RTR0_E2E_RD_LL_STAT_BASE 0x4344540ull
+#define DCORE1_RTR0_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR0_E2E_RD_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR0_E2E_WR_LL_STAT_BASE 0x4344580ull
+#define DCORE1_RTR0_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR0_E2E_WR_LL_STAT_SECTION 0x8000
+#define mmDCORE1_RTR0_RTR_HBW_XACT_STAT_BASE 0x4344600ull
+#define DCORE1_RTR0_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR0_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE1_RTR0_RTR_LBW_XACT_STAT_BASE 0x4344680ull
+#define DCORE1_RTR0_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR0_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE1_RTR0_RTR_E2E_XACT_STAT_BASE 0x4344700ull
+#define DCORE1_RTR0_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR0_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define mmDCORE1_RTR0_SPECIAL_BASE 0x4344E80ull
+#define DCORE1_RTR0_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR0_SPECIAL_SECTION 0x1800
+#define mmDCORE1_RTR0_DBG_ADDR_BASE 0x4345000ull
+#define DCORE1_RTR0_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE1_RTR0_DBG_ADDR_SECTION 0xE800
+#define mmDCORE1_RTR0_DBG_ADDR_SPECIAL_BASE 0x4345E80ull
+#define DCORE1_RTR0_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR0_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define mmDCORE1_RTR1_CTRL_BASE 0x4348000ull
+#define DCORE1_RTR1_CTRL_MAX_OFFSET 0x1000
+#define DCORE1_RTR1_CTRL_SECTION 0xE800
+#define mmDCORE1_RTR1_CTRL_SPECIAL_BASE 0x4348E80ull
+#define DCORE1_RTR1_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR1_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE1_RTR1_H3_BASE 0x4349000ull
+#define DCORE1_RTR1_H3_MAX_OFFSET 0x1000
+#define DCORE1_RTR1_H3_SECTION 0xE800
+#define mmDCORE1_RTR1_H3_SPECIAL_BASE 0x4349E80ull
+#define DCORE1_RTR1_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR1_H3_SPECIAL_SECTION 0x1800
+#define mmDCORE1_RTR1_MSTR_IF_RR_SHRD_HBW_BASE 0x434A000ull
+#define DCORE1_RTR1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_RTR1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE1_RTR1_MSTR_IF_RR_PRVT_HBW_BASE 0x434A200ull
+#define DCORE1_RTR1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_RTR1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE1_RTR1_MSTR_IF_RR_SHRD_LBW_BASE 0x434A400ull
+#define DCORE1_RTR1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_RTR1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE1_RTR1_MSTR_IF_RR_PRVT_LBW_BASE 0x434A600ull
+#define DCORE1_RTR1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_RTR1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE1_RTR1_MSTR_IF_E2E_CRDT_BASE 0x434A800ull
+#define DCORE1_RTR1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_RTR1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE1_RTR1_MSTR_IF_AXUSER_BASE 0x434AA80ull
+#define DCORE1_RTR1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_RTR1_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE1_RTR1_MSTR_IF_DBG_HBW_BASE 0x434AB00ull
+#define DCORE1_RTR1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_RTR1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_RTR1_MSTR_IF_DBG_LBW_BASE 0x434AB80ull
+#define DCORE1_RTR1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_RTR1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE1_RTR1_MSTR_IF_CORE_HBW_BASE 0x434AC00ull
+#define DCORE1_RTR1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_RTR1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE1_RTR1_MSTR_IF_CORE_LBW_BASE 0x434AD80ull
+#define DCORE1_RTR1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_RTR1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE1_RTR1_MSTR_IF_SPECIAL_BASE 0x434AE80ull
+#define DCORE1_RTR1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR1_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE1_RTR1_ADD_DEC_HBW_BASE 0x434B000ull
+#define DCORE1_RTR1_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE1_RTR1_ADD_DEC_HBW_SECTION 0x4000
+#define mmDCORE1_RTR1_ADD_DEC_LBW_BASE 0x434B400ull
+#define DCORE1_RTR1_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE1_RTR1_ADD_DEC_LBW_SECTION 0xA800
+#define mmDCORE1_RTR1_ADD_DEC_SPECIAL_BASE 0x434BE80ull
+#define DCORE1_RTR1_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR1_ADD_DEC_SPECIAL_SECTION 0x1800
+#define mmDCORE1_RTR1_BASE 0x434C000ull
+#define DCORE1_RTR1_MAX_OFFSET 0x1000
+#define DCORE1_RTR1_SECTION 0x3000
+#define mmDCORE1_RTR1_HBW_RD_RQ_LL_STAT_BASE 0x434C300ull
+#define DCORE1_RTR1_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR1_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR1_HBW_RD_RS_LL_STAT_BASE 0x434C340ull
+#define DCORE1_RTR1_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR1_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR1_HBW_WR_RQ_LL_STAT_BASE 0x434C380ull
+#define DCORE1_RTR1_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR1_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR1_HBW_WR_RS_LL_STAT_BASE 0x434C3C0ull
+#define DCORE1_RTR1_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR1_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR1_LBW_RD_RQ_LL_STAT_BASE 0x434C400ull
+#define DCORE1_RTR1_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR1_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR1_LBW_RD_RS_LL_STAT_BASE 0x434C440ull
+#define DCORE1_RTR1_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR1_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR1_LBW_WR_RQ_LL_STAT_BASE 0x434C480ull
+#define DCORE1_RTR1_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR1_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR1_LBW_WR_RS_LL_STAT_BASE 0x434C4C0ull
+#define DCORE1_RTR1_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR1_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR1_HBW_MFIFO_BASE 0x434C500ull
+#define DCORE1_RTR1_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE1_RTR1_HBW_MFIFO_SECTION 0x4000
+#define mmDCORE1_RTR1_E2E_RD_LL_STAT_BASE 0x434C540ull
+#define DCORE1_RTR1_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR1_E2E_RD_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR1_E2E_WR_LL_STAT_BASE 0x434C580ull
+#define DCORE1_RTR1_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR1_E2E_WR_LL_STAT_SECTION 0x8000
+#define mmDCORE1_RTR1_RTR_HBW_XACT_STAT_BASE 0x434C600ull
+#define DCORE1_RTR1_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR1_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE1_RTR1_RTR_LBW_XACT_STAT_BASE 0x434C680ull
+#define DCORE1_RTR1_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR1_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE1_RTR1_RTR_E2E_XACT_STAT_BASE 0x434C700ull
+#define DCORE1_RTR1_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR1_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define mmDCORE1_RTR1_SPECIAL_BASE 0x434CE80ull
+#define DCORE1_RTR1_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR1_SPECIAL_SECTION 0x1800
+#define mmDCORE1_RTR1_DBG_ADDR_BASE 0x434D000ull
+#define DCORE1_RTR1_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE1_RTR1_DBG_ADDR_SECTION 0xE800
+#define mmDCORE1_RTR1_DBG_ADDR_SPECIAL_BASE 0x434DE80ull
+#define DCORE1_RTR1_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR1_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define mmDCORE1_RTR2_CTRL_BASE 0x4350000ull
+#define DCORE1_RTR2_CTRL_MAX_OFFSET 0x1000
+#define DCORE1_RTR2_CTRL_SECTION 0xE800
+#define mmDCORE1_RTR2_CTRL_SPECIAL_BASE 0x4350E80ull
+#define DCORE1_RTR2_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR2_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE1_RTR2_H3_BASE 0x4351000ull
+#define DCORE1_RTR2_H3_MAX_OFFSET 0x1000
+#define DCORE1_RTR2_H3_SECTION 0xE800
+#define mmDCORE1_RTR2_H3_SPECIAL_BASE 0x4351E80ull
+#define DCORE1_RTR2_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR2_H3_SPECIAL_SECTION 0x1800
+#define mmDCORE1_RTR2_MSTR_IF_RR_SHRD_HBW_BASE 0x4352000ull
+#define DCORE1_RTR2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_RTR2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE1_RTR2_MSTR_IF_RR_PRVT_HBW_BASE 0x4352200ull
+#define DCORE1_RTR2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_RTR2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE1_RTR2_MSTR_IF_RR_SHRD_LBW_BASE 0x4352400ull
+#define DCORE1_RTR2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_RTR2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE1_RTR2_MSTR_IF_RR_PRVT_LBW_BASE 0x4352600ull
+#define DCORE1_RTR2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_RTR2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE1_RTR2_MSTR_IF_E2E_CRDT_BASE 0x4352800ull
+#define DCORE1_RTR2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_RTR2_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE1_RTR2_MSTR_IF_AXUSER_BASE 0x4352A80ull
+#define DCORE1_RTR2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_RTR2_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE1_RTR2_MSTR_IF_DBG_HBW_BASE 0x4352B00ull
+#define DCORE1_RTR2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_RTR2_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_RTR2_MSTR_IF_DBG_LBW_BASE 0x4352B80ull
+#define DCORE1_RTR2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_RTR2_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE1_RTR2_MSTR_IF_CORE_HBW_BASE 0x4352C00ull
+#define DCORE1_RTR2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_RTR2_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE1_RTR2_MSTR_IF_CORE_LBW_BASE 0x4352D80ull
+#define DCORE1_RTR2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_RTR2_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE1_RTR2_MSTR_IF_SPECIAL_BASE 0x4352E80ull
+#define DCORE1_RTR2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR2_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE1_RTR2_ADD_DEC_HBW_BASE 0x4353000ull
+#define DCORE1_RTR2_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE1_RTR2_ADD_DEC_HBW_SECTION 0x4000
+#define mmDCORE1_RTR2_ADD_DEC_LBW_BASE 0x4353400ull
+#define DCORE1_RTR2_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE1_RTR2_ADD_DEC_LBW_SECTION 0xA800
+#define mmDCORE1_RTR2_ADD_DEC_SPECIAL_BASE 0x4353E80ull
+#define DCORE1_RTR2_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR2_ADD_DEC_SPECIAL_SECTION 0x1800
+#define mmDCORE1_RTR2_BASE 0x4354000ull
+#define DCORE1_RTR2_MAX_OFFSET 0x1000
+#define DCORE1_RTR2_SECTION 0x3000
+#define mmDCORE1_RTR2_HBW_RD_RQ_LL_STAT_BASE 0x4354300ull
+#define DCORE1_RTR2_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR2_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR2_HBW_RD_RS_LL_STAT_BASE 0x4354340ull
+#define DCORE1_RTR2_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR2_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR2_HBW_WR_RQ_LL_STAT_BASE 0x4354380ull
+#define DCORE1_RTR2_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR2_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR2_HBW_WR_RS_LL_STAT_BASE 0x43543C0ull
+#define DCORE1_RTR2_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR2_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR2_LBW_RD_RQ_LL_STAT_BASE 0x4354400ull
+#define DCORE1_RTR2_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR2_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR2_LBW_RD_RS_LL_STAT_BASE 0x4354440ull
+#define DCORE1_RTR2_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR2_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR2_LBW_WR_RQ_LL_STAT_BASE 0x4354480ull
+#define DCORE1_RTR2_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR2_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR2_LBW_WR_RS_LL_STAT_BASE 0x43544C0ull
+#define DCORE1_RTR2_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR2_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR2_HBW_MFIFO_BASE 0x4354500ull
+#define DCORE1_RTR2_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE1_RTR2_HBW_MFIFO_SECTION 0x4000
+#define mmDCORE1_RTR2_E2E_RD_LL_STAT_BASE 0x4354540ull
+#define DCORE1_RTR2_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR2_E2E_RD_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR2_E2E_WR_LL_STAT_BASE 0x4354580ull
+#define DCORE1_RTR2_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR2_E2E_WR_LL_STAT_SECTION 0x8000
+#define mmDCORE1_RTR2_RTR_HBW_XACT_STAT_BASE 0x4354600ull
+#define DCORE1_RTR2_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR2_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE1_RTR2_RTR_LBW_XACT_STAT_BASE 0x4354680ull
+#define DCORE1_RTR2_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR2_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE1_RTR2_RTR_E2E_XACT_STAT_BASE 0x4354700ull
+#define DCORE1_RTR2_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR2_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define mmDCORE1_RTR2_SPECIAL_BASE 0x4354E80ull
+#define DCORE1_RTR2_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR2_SPECIAL_SECTION 0x1800
+#define mmDCORE1_RTR2_DBG_ADDR_BASE 0x4355000ull
+#define DCORE1_RTR2_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE1_RTR2_DBG_ADDR_SECTION 0xE800
+#define mmDCORE1_RTR2_DBG_ADDR_SPECIAL_BASE 0x4355E80ull
+#define DCORE1_RTR2_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR2_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define mmDCORE1_RTR3_CTRL_BASE 0x4358000ull
+#define DCORE1_RTR3_CTRL_MAX_OFFSET 0x1000
+#define DCORE1_RTR3_CTRL_SECTION 0xE800
+#define mmDCORE1_RTR3_CTRL_SPECIAL_BASE 0x4358E80ull
+#define DCORE1_RTR3_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR3_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE1_RTR3_H3_BASE 0x4359000ull
+#define DCORE1_RTR3_H3_MAX_OFFSET 0x1000
+#define DCORE1_RTR3_H3_SECTION 0xE800
+#define mmDCORE1_RTR3_H3_SPECIAL_BASE 0x4359E80ull
+#define DCORE1_RTR3_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR3_H3_SPECIAL_SECTION 0x1800
+#define mmDCORE1_RTR3_MSTR_IF_RR_SHRD_HBW_BASE 0x435A000ull
+#define DCORE1_RTR3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_RTR3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE1_RTR3_MSTR_IF_RR_PRVT_HBW_BASE 0x435A200ull
+#define DCORE1_RTR3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_RTR3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE1_RTR3_MSTR_IF_RR_SHRD_LBW_BASE 0x435A400ull
+#define DCORE1_RTR3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_RTR3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE1_RTR3_MSTR_IF_RR_PRVT_LBW_BASE 0x435A600ull
+#define DCORE1_RTR3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_RTR3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE1_RTR3_MSTR_IF_E2E_CRDT_BASE 0x435A800ull
+#define DCORE1_RTR3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_RTR3_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE1_RTR3_MSTR_IF_AXUSER_BASE 0x435AA80ull
+#define DCORE1_RTR3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_RTR3_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE1_RTR3_MSTR_IF_DBG_HBW_BASE 0x435AB00ull
+#define DCORE1_RTR3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_RTR3_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_RTR3_MSTR_IF_DBG_LBW_BASE 0x435AB80ull
+#define DCORE1_RTR3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_RTR3_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE1_RTR3_MSTR_IF_CORE_HBW_BASE 0x435AC00ull
+#define DCORE1_RTR3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_RTR3_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE1_RTR3_MSTR_IF_CORE_LBW_BASE 0x435AD80ull
+#define DCORE1_RTR3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_RTR3_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE1_RTR3_MSTR_IF_SPECIAL_BASE 0x435AE80ull
+#define DCORE1_RTR3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR3_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE1_RTR3_ADD_DEC_HBW_BASE 0x435B000ull
+#define DCORE1_RTR3_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE1_RTR3_ADD_DEC_HBW_SECTION 0x4000
+#define mmDCORE1_RTR3_ADD_DEC_LBW_BASE 0x435B400ull
+#define DCORE1_RTR3_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE1_RTR3_ADD_DEC_LBW_SECTION 0xA800
+#define mmDCORE1_RTR3_ADD_DEC_SPECIAL_BASE 0x435BE80ull
+#define DCORE1_RTR3_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR3_ADD_DEC_SPECIAL_SECTION 0x1800
+#define mmDCORE1_RTR3_BASE 0x435C000ull
+#define DCORE1_RTR3_MAX_OFFSET 0x1000
+#define DCORE1_RTR3_SECTION 0x3000
+#define mmDCORE1_RTR3_HBW_RD_RQ_LL_STAT_BASE 0x435C300ull
+#define DCORE1_RTR3_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR3_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR3_HBW_RD_RS_LL_STAT_BASE 0x435C340ull
+#define DCORE1_RTR3_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR3_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR3_HBW_WR_RQ_LL_STAT_BASE 0x435C380ull
+#define DCORE1_RTR3_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR3_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR3_HBW_WR_RS_LL_STAT_BASE 0x435C3C0ull
+#define DCORE1_RTR3_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR3_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR3_LBW_RD_RQ_LL_STAT_BASE 0x435C400ull
+#define DCORE1_RTR3_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR3_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR3_LBW_RD_RS_LL_STAT_BASE 0x435C440ull
+#define DCORE1_RTR3_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR3_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR3_LBW_WR_RQ_LL_STAT_BASE 0x435C480ull
+#define DCORE1_RTR3_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR3_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR3_LBW_WR_RS_LL_STAT_BASE 0x435C4C0ull
+#define DCORE1_RTR3_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR3_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR3_HBW_MFIFO_BASE 0x435C500ull
+#define DCORE1_RTR3_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE1_RTR3_HBW_MFIFO_SECTION 0x4000
+#define mmDCORE1_RTR3_E2E_RD_LL_STAT_BASE 0x435C540ull
+#define DCORE1_RTR3_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR3_E2E_RD_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR3_E2E_WR_LL_STAT_BASE 0x435C580ull
+#define DCORE1_RTR3_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR3_E2E_WR_LL_STAT_SECTION 0x8000
+#define mmDCORE1_RTR3_RTR_HBW_XACT_STAT_BASE 0x435C600ull
+#define DCORE1_RTR3_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR3_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE1_RTR3_RTR_LBW_XACT_STAT_BASE 0x435C680ull
+#define DCORE1_RTR3_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR3_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE1_RTR3_RTR_E2E_XACT_STAT_BASE 0x435C700ull
+#define DCORE1_RTR3_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR3_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define mmDCORE1_RTR3_SPECIAL_BASE 0x435CE80ull
+#define DCORE1_RTR3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR3_SPECIAL_SECTION 0x1800
+#define mmDCORE1_RTR3_DBG_ADDR_BASE 0x435D000ull
+#define DCORE1_RTR3_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE1_RTR3_DBG_ADDR_SECTION 0xE800
+#define mmDCORE1_RTR3_DBG_ADDR_SPECIAL_BASE 0x435DE80ull
+#define DCORE1_RTR3_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR3_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define mmDCORE1_RTR4_CTRL_BASE 0x4360000ull
+#define DCORE1_RTR4_CTRL_MAX_OFFSET 0x1000
+#define DCORE1_RTR4_CTRL_SECTION 0xE800
+#define mmDCORE1_RTR4_CTRL_SPECIAL_BASE 0x4360E80ull
+#define DCORE1_RTR4_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR4_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE1_RTR4_H3_BASE 0x4361000ull
+#define DCORE1_RTR4_H3_MAX_OFFSET 0x1000
+#define DCORE1_RTR4_H3_SECTION 0xE800
+#define mmDCORE1_RTR4_H3_SPECIAL_BASE 0x4361E80ull
+#define DCORE1_RTR4_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR4_H3_SPECIAL_SECTION 0x1800
+#define mmDCORE1_RTR4_MSTR_IF_RR_SHRD_HBW_BASE 0x4362000ull
+#define DCORE1_RTR4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_RTR4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE1_RTR4_MSTR_IF_RR_PRVT_HBW_BASE 0x4362200ull
+#define DCORE1_RTR4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_RTR4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE1_RTR4_MSTR_IF_RR_SHRD_LBW_BASE 0x4362400ull
+#define DCORE1_RTR4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_RTR4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE1_RTR4_MSTR_IF_RR_PRVT_LBW_BASE 0x4362600ull
+#define DCORE1_RTR4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_RTR4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE1_RTR4_MSTR_IF_E2E_CRDT_BASE 0x4362800ull
+#define DCORE1_RTR4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_RTR4_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE1_RTR4_MSTR_IF_AXUSER_BASE 0x4362A80ull
+#define DCORE1_RTR4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_RTR4_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE1_RTR4_MSTR_IF_DBG_HBW_BASE 0x4362B00ull
+#define DCORE1_RTR4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_RTR4_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_RTR4_MSTR_IF_DBG_LBW_BASE 0x4362B80ull
+#define DCORE1_RTR4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_RTR4_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE1_RTR4_MSTR_IF_CORE_HBW_BASE 0x4362C00ull
+#define DCORE1_RTR4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_RTR4_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE1_RTR4_MSTR_IF_CORE_LBW_BASE 0x4362D80ull
+#define DCORE1_RTR4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_RTR4_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE1_RTR4_MSTR_IF_SPECIAL_BASE 0x4362E80ull
+#define DCORE1_RTR4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR4_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE1_RTR4_ADD_DEC_HBW_BASE 0x4363000ull
+#define DCORE1_RTR4_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE1_RTR4_ADD_DEC_HBW_SECTION 0x4000
+#define mmDCORE1_RTR4_ADD_DEC_LBW_BASE 0x4363400ull
+#define DCORE1_RTR4_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE1_RTR4_ADD_DEC_LBW_SECTION 0xA800
+#define mmDCORE1_RTR4_ADD_DEC_SPECIAL_BASE 0x4363E80ull
+#define DCORE1_RTR4_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR4_ADD_DEC_SPECIAL_SECTION 0x1800
+#define mmDCORE1_RTR4_BASE 0x4364000ull
+#define DCORE1_RTR4_MAX_OFFSET 0x1000
+#define DCORE1_RTR4_SECTION 0x3000
+#define mmDCORE1_RTR4_HBW_RD_RQ_LL_STAT_BASE 0x4364300ull
+#define DCORE1_RTR4_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR4_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR4_HBW_RD_RS_LL_STAT_BASE 0x4364340ull
+#define DCORE1_RTR4_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR4_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR4_HBW_WR_RQ_LL_STAT_BASE 0x4364380ull
+#define DCORE1_RTR4_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR4_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR4_HBW_WR_RS_LL_STAT_BASE 0x43643C0ull
+#define DCORE1_RTR4_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR4_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR4_LBW_RD_RQ_LL_STAT_BASE 0x4364400ull
+#define DCORE1_RTR4_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR4_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR4_LBW_RD_RS_LL_STAT_BASE 0x4364440ull
+#define DCORE1_RTR4_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR4_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR4_LBW_WR_RQ_LL_STAT_BASE 0x4364480ull
+#define DCORE1_RTR4_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR4_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR4_LBW_WR_RS_LL_STAT_BASE 0x43644C0ull
+#define DCORE1_RTR4_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR4_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR4_HBW_MFIFO_BASE 0x4364500ull
+#define DCORE1_RTR4_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE1_RTR4_HBW_MFIFO_SECTION 0x4000
+#define mmDCORE1_RTR4_E2E_RD_LL_STAT_BASE 0x4364540ull
+#define DCORE1_RTR4_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR4_E2E_RD_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR4_E2E_WR_LL_STAT_BASE 0x4364580ull
+#define DCORE1_RTR4_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR4_E2E_WR_LL_STAT_SECTION 0x8000
+#define mmDCORE1_RTR4_RTR_HBW_XACT_STAT_BASE 0x4364600ull
+#define DCORE1_RTR4_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR4_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE1_RTR4_RTR_LBW_XACT_STAT_BASE 0x4364680ull
+#define DCORE1_RTR4_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR4_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE1_RTR4_RTR_E2E_XACT_STAT_BASE 0x4364700ull
+#define DCORE1_RTR4_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR4_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define mmDCORE1_RTR4_SPECIAL_BASE 0x4364E80ull
+#define DCORE1_RTR4_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR4_SPECIAL_SECTION 0x1800
+#define mmDCORE1_RTR4_DBG_ADDR_BASE 0x4365000ull
+#define DCORE1_RTR4_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE1_RTR4_DBG_ADDR_SECTION 0xE800
+#define mmDCORE1_RTR4_DBG_ADDR_SPECIAL_BASE 0x4365E80ull
+#define DCORE1_RTR4_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR4_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define mmDCORE1_RTR5_CTRL_BASE 0x4368000ull
+#define DCORE1_RTR5_CTRL_MAX_OFFSET 0x1000
+#define DCORE1_RTR5_CTRL_SECTION 0xE800
+#define mmDCORE1_RTR5_CTRL_SPECIAL_BASE 0x4368E80ull
+#define DCORE1_RTR5_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR5_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE1_RTR5_H3_BASE 0x4369000ull
+#define DCORE1_RTR5_H3_MAX_OFFSET 0x1000
+#define DCORE1_RTR5_H3_SECTION 0xE800
+#define mmDCORE1_RTR5_H3_SPECIAL_BASE 0x4369E80ull
+#define DCORE1_RTR5_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR5_H3_SPECIAL_SECTION 0x1800
+#define mmDCORE1_RTR5_MSTR_IF_RR_SHRD_HBW_BASE 0x436A000ull
+#define DCORE1_RTR5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_RTR5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE1_RTR5_MSTR_IF_RR_PRVT_HBW_BASE 0x436A200ull
+#define DCORE1_RTR5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_RTR5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE1_RTR5_MSTR_IF_RR_SHRD_LBW_BASE 0x436A400ull
+#define DCORE1_RTR5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_RTR5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE1_RTR5_MSTR_IF_RR_PRVT_LBW_BASE 0x436A600ull
+#define DCORE1_RTR5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_RTR5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE1_RTR5_MSTR_IF_E2E_CRDT_BASE 0x436A800ull
+#define DCORE1_RTR5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_RTR5_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE1_RTR5_MSTR_IF_AXUSER_BASE 0x436AA80ull
+#define DCORE1_RTR5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_RTR5_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE1_RTR5_MSTR_IF_DBG_HBW_BASE 0x436AB00ull
+#define DCORE1_RTR5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_RTR5_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_RTR5_MSTR_IF_DBG_LBW_BASE 0x436AB80ull
+#define DCORE1_RTR5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_RTR5_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE1_RTR5_MSTR_IF_CORE_HBW_BASE 0x436AC00ull
+#define DCORE1_RTR5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_RTR5_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE1_RTR5_MSTR_IF_CORE_LBW_BASE 0x436AD80ull
+#define DCORE1_RTR5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_RTR5_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE1_RTR5_MSTR_IF_SPECIAL_BASE 0x436AE80ull
+#define DCORE1_RTR5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR5_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE1_RTR5_ADD_DEC_HBW_BASE 0x436B000ull
+#define DCORE1_RTR5_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE1_RTR5_ADD_DEC_HBW_SECTION 0x4000
+#define mmDCORE1_RTR5_ADD_DEC_LBW_BASE 0x436B400ull
+#define DCORE1_RTR5_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE1_RTR5_ADD_DEC_LBW_SECTION 0xA800
+#define mmDCORE1_RTR5_ADD_DEC_SPECIAL_BASE 0x436BE80ull
+#define DCORE1_RTR5_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR5_ADD_DEC_SPECIAL_SECTION 0x1800
+#define mmDCORE1_RTR5_BASE 0x436C000ull
+#define DCORE1_RTR5_MAX_OFFSET 0x1000
+#define DCORE1_RTR5_SECTION 0x3000
+#define mmDCORE1_RTR5_HBW_RD_RQ_LL_STAT_BASE 0x436C300ull
+#define DCORE1_RTR5_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR5_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR5_HBW_RD_RS_LL_STAT_BASE 0x436C340ull
+#define DCORE1_RTR5_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR5_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR5_HBW_WR_RQ_LL_STAT_BASE 0x436C380ull
+#define DCORE1_RTR5_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR5_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR5_HBW_WR_RS_LL_STAT_BASE 0x436C3C0ull
+#define DCORE1_RTR5_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR5_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR5_LBW_RD_RQ_LL_STAT_BASE 0x436C400ull
+#define DCORE1_RTR5_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR5_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR5_LBW_RD_RS_LL_STAT_BASE 0x436C440ull
+#define DCORE1_RTR5_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR5_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR5_LBW_WR_RQ_LL_STAT_BASE 0x436C480ull
+#define DCORE1_RTR5_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR5_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR5_LBW_WR_RS_LL_STAT_BASE 0x436C4C0ull
+#define DCORE1_RTR5_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR5_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR5_HBW_MFIFO_BASE 0x436C500ull
+#define DCORE1_RTR5_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE1_RTR5_HBW_MFIFO_SECTION 0x4000
+#define mmDCORE1_RTR5_E2E_RD_LL_STAT_BASE 0x436C540ull
+#define DCORE1_RTR5_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR5_E2E_RD_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR5_E2E_WR_LL_STAT_BASE 0x436C580ull
+#define DCORE1_RTR5_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR5_E2E_WR_LL_STAT_SECTION 0x8000
+#define mmDCORE1_RTR5_RTR_HBW_XACT_STAT_BASE 0x436C600ull
+#define DCORE1_RTR5_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR5_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE1_RTR5_RTR_LBW_XACT_STAT_BASE 0x436C680ull
+#define DCORE1_RTR5_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR5_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE1_RTR5_RTR_E2E_XACT_STAT_BASE 0x436C700ull
+#define DCORE1_RTR5_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR5_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define mmDCORE1_RTR5_SPECIAL_BASE 0x436CE80ull
+#define DCORE1_RTR5_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR5_SPECIAL_SECTION 0x1800
+#define mmDCORE1_RTR5_DBG_ADDR_BASE 0x436D000ull
+#define DCORE1_RTR5_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE1_RTR5_DBG_ADDR_SECTION 0xE800
+#define mmDCORE1_RTR5_DBG_ADDR_SPECIAL_BASE 0x436DE80ull
+#define DCORE1_RTR5_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR5_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define mmDCORE1_RTR6_CTRL_BASE 0x4370000ull
+#define DCORE1_RTR6_CTRL_MAX_OFFSET 0x1000
+#define DCORE1_RTR6_CTRL_SECTION 0xE800
+#define mmDCORE1_RTR6_CTRL_SPECIAL_BASE 0x4370E80ull
+#define DCORE1_RTR6_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR6_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE1_RTR6_H3_BASE 0x4371000ull
+#define DCORE1_RTR6_H3_MAX_OFFSET 0x1000
+#define DCORE1_RTR6_H3_SECTION 0xE800
+#define mmDCORE1_RTR6_H3_SPECIAL_BASE 0x4371E80ull
+#define DCORE1_RTR6_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR6_H3_SPECIAL_SECTION 0x1800
+#define mmDCORE1_RTR6_MSTR_IF_RR_SHRD_HBW_BASE 0x4372000ull
+#define DCORE1_RTR6_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_RTR6_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE1_RTR6_MSTR_IF_RR_PRVT_HBW_BASE 0x4372200ull
+#define DCORE1_RTR6_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_RTR6_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE1_RTR6_MSTR_IF_RR_SHRD_LBW_BASE 0x4372400ull
+#define DCORE1_RTR6_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_RTR6_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE1_RTR6_MSTR_IF_RR_PRVT_LBW_BASE 0x4372600ull
+#define DCORE1_RTR6_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_RTR6_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE1_RTR6_MSTR_IF_E2E_CRDT_BASE 0x4372800ull
+#define DCORE1_RTR6_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_RTR6_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE1_RTR6_MSTR_IF_AXUSER_BASE 0x4372A80ull
+#define DCORE1_RTR6_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_RTR6_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE1_RTR6_MSTR_IF_DBG_HBW_BASE 0x4372B00ull
+#define DCORE1_RTR6_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_RTR6_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_RTR6_MSTR_IF_DBG_LBW_BASE 0x4372B80ull
+#define DCORE1_RTR6_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_RTR6_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE1_RTR6_MSTR_IF_CORE_HBW_BASE 0x4372C00ull
+#define DCORE1_RTR6_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_RTR6_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE1_RTR6_MSTR_IF_CORE_LBW_BASE 0x4372D80ull
+#define DCORE1_RTR6_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_RTR6_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE1_RTR6_MSTR_IF_SPECIAL_BASE 0x4372E80ull
+#define DCORE1_RTR6_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR6_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE1_RTR6_ADD_DEC_HBW_BASE 0x4373000ull
+#define DCORE1_RTR6_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE1_RTR6_ADD_DEC_HBW_SECTION 0x4000
+#define mmDCORE1_RTR6_ADD_DEC_LBW_BASE 0x4373400ull
+#define DCORE1_RTR6_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE1_RTR6_ADD_DEC_LBW_SECTION 0xA800
+#define mmDCORE1_RTR6_ADD_DEC_SPECIAL_BASE 0x4373E80ull
+#define DCORE1_RTR6_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR6_ADD_DEC_SPECIAL_SECTION 0x1800
+#define mmDCORE1_RTR6_BASE 0x4374000ull
+#define DCORE1_RTR6_MAX_OFFSET 0x1000
+#define DCORE1_RTR6_SECTION 0x3000
+#define mmDCORE1_RTR6_HBW_RD_RQ_LL_STAT_BASE 0x4374300ull
+#define DCORE1_RTR6_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR6_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR6_HBW_RD_RS_LL_STAT_BASE 0x4374340ull
+#define DCORE1_RTR6_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR6_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR6_HBW_WR_RQ_LL_STAT_BASE 0x4374380ull
+#define DCORE1_RTR6_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR6_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR6_HBW_WR_RS_LL_STAT_BASE 0x43743C0ull
+#define DCORE1_RTR6_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR6_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR6_LBW_RD_RQ_LL_STAT_BASE 0x4374400ull
+#define DCORE1_RTR6_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR6_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR6_LBW_RD_RS_LL_STAT_BASE 0x4374440ull
+#define DCORE1_RTR6_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR6_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR6_LBW_WR_RQ_LL_STAT_BASE 0x4374480ull
+#define DCORE1_RTR6_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR6_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR6_LBW_WR_RS_LL_STAT_BASE 0x43744C0ull
+#define DCORE1_RTR6_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR6_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR6_HBW_MFIFO_BASE 0x4374500ull
+#define DCORE1_RTR6_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE1_RTR6_HBW_MFIFO_SECTION 0x4000
+#define mmDCORE1_RTR6_E2E_RD_LL_STAT_BASE 0x4374540ull
+#define DCORE1_RTR6_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR6_E2E_RD_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR6_E2E_WR_LL_STAT_BASE 0x4374580ull
+#define DCORE1_RTR6_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR6_E2E_WR_LL_STAT_SECTION 0x8000
+#define mmDCORE1_RTR6_RTR_HBW_XACT_STAT_BASE 0x4374600ull
+#define DCORE1_RTR6_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR6_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE1_RTR6_RTR_LBW_XACT_STAT_BASE 0x4374680ull
+#define DCORE1_RTR6_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR6_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE1_RTR6_RTR_E2E_XACT_STAT_BASE 0x4374700ull
+#define DCORE1_RTR6_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR6_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define mmDCORE1_RTR6_SPECIAL_BASE 0x4374E80ull
+#define DCORE1_RTR6_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR6_SPECIAL_SECTION 0x1800
+#define mmDCORE1_RTR6_DBG_ADDR_BASE 0x4375000ull
+#define DCORE1_RTR6_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE1_RTR6_DBG_ADDR_SECTION 0xE800
+#define mmDCORE1_RTR6_DBG_ADDR_SPECIAL_BASE 0x4375E80ull
+#define DCORE1_RTR6_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR6_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define mmDCORE1_RTR7_CTRL_BASE 0x4378000ull
+#define DCORE1_RTR7_CTRL_MAX_OFFSET 0x1000
+#define DCORE1_RTR7_CTRL_SECTION 0xE800
+#define mmDCORE1_RTR7_CTRL_SPECIAL_BASE 0x4378E80ull
+#define DCORE1_RTR7_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR7_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE1_RTR7_H3_BASE 0x4379000ull
+#define DCORE1_RTR7_H3_MAX_OFFSET 0x1000
+#define DCORE1_RTR7_H3_SECTION 0xE800
+#define mmDCORE1_RTR7_H3_SPECIAL_BASE 0x4379E80ull
+#define DCORE1_RTR7_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR7_H3_SPECIAL_SECTION 0x1800
+#define mmDCORE1_RTR7_MSTR_IF_RR_SHRD_HBW_BASE 0x437A000ull
+#define DCORE1_RTR7_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_RTR7_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE1_RTR7_MSTR_IF_RR_PRVT_HBW_BASE 0x437A200ull
+#define DCORE1_RTR7_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_RTR7_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE1_RTR7_MSTR_IF_RR_SHRD_LBW_BASE 0x437A400ull
+#define DCORE1_RTR7_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_RTR7_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE1_RTR7_MSTR_IF_RR_PRVT_LBW_BASE 0x437A600ull
+#define DCORE1_RTR7_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_RTR7_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE1_RTR7_MSTR_IF_E2E_CRDT_BASE 0x437A800ull
+#define DCORE1_RTR7_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_RTR7_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE1_RTR7_MSTR_IF_AXUSER_BASE 0x437AA80ull
+#define DCORE1_RTR7_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_RTR7_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE1_RTR7_MSTR_IF_DBG_HBW_BASE 0x437AB00ull
+#define DCORE1_RTR7_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_RTR7_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_RTR7_MSTR_IF_DBG_LBW_BASE 0x437AB80ull
+#define DCORE1_RTR7_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_RTR7_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE1_RTR7_MSTR_IF_CORE_HBW_BASE 0x437AC00ull
+#define DCORE1_RTR7_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_RTR7_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE1_RTR7_MSTR_IF_CORE_LBW_BASE 0x437AD80ull
+#define DCORE1_RTR7_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_RTR7_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE1_RTR7_MSTR_IF_SPECIAL_BASE 0x437AE80ull
+#define DCORE1_RTR7_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR7_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE1_RTR7_ADD_DEC_HBW_BASE 0x437B000ull
+#define DCORE1_RTR7_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE1_RTR7_ADD_DEC_HBW_SECTION 0x4000
+#define mmDCORE1_RTR7_ADD_DEC_LBW_BASE 0x437B400ull
+#define DCORE1_RTR7_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE1_RTR7_ADD_DEC_LBW_SECTION 0xA800
+#define mmDCORE1_RTR7_ADD_DEC_SPECIAL_BASE 0x437BE80ull
+#define DCORE1_RTR7_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR7_ADD_DEC_SPECIAL_SECTION 0x1800
+#define mmDCORE1_RTR7_BASE 0x437C000ull
+#define DCORE1_RTR7_MAX_OFFSET 0x1000
+#define DCORE1_RTR7_SECTION 0x3000
+#define mmDCORE1_RTR7_HBW_RD_RQ_LL_STAT_BASE 0x437C300ull
+#define DCORE1_RTR7_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR7_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR7_HBW_RD_RS_LL_STAT_BASE 0x437C340ull
+#define DCORE1_RTR7_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR7_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR7_HBW_WR_RQ_LL_STAT_BASE 0x437C380ull
+#define DCORE1_RTR7_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR7_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR7_HBW_WR_RS_LL_STAT_BASE 0x437C3C0ull
+#define DCORE1_RTR7_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR7_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR7_LBW_RD_RQ_LL_STAT_BASE 0x437C400ull
+#define DCORE1_RTR7_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR7_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR7_LBW_RD_RS_LL_STAT_BASE 0x437C440ull
+#define DCORE1_RTR7_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR7_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR7_LBW_WR_RQ_LL_STAT_BASE 0x437C480ull
+#define DCORE1_RTR7_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR7_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR7_LBW_WR_RS_LL_STAT_BASE 0x437C4C0ull
+#define DCORE1_RTR7_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR7_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR7_HBW_MFIFO_BASE 0x437C500ull
+#define DCORE1_RTR7_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE1_RTR7_HBW_MFIFO_SECTION 0x4000
+#define mmDCORE1_RTR7_E2E_RD_LL_STAT_BASE 0x437C540ull
+#define DCORE1_RTR7_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR7_E2E_RD_LL_STAT_SECTION 0x4000
+#define mmDCORE1_RTR7_E2E_WR_LL_STAT_BASE 0x437C580ull
+#define DCORE1_RTR7_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE1_RTR7_E2E_WR_LL_STAT_SECTION 0x8000
+#define mmDCORE1_RTR7_RTR_HBW_XACT_STAT_BASE 0x437C600ull
+#define DCORE1_RTR7_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR7_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE1_RTR7_RTR_LBW_XACT_STAT_BASE 0x437C680ull
+#define DCORE1_RTR7_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR7_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE1_RTR7_RTR_E2E_XACT_STAT_BASE 0x437C700ull
+#define DCORE1_RTR7_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE1_RTR7_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define mmDCORE1_RTR7_SPECIAL_BASE 0x437CE80ull
+#define DCORE1_RTR7_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR7_SPECIAL_SECTION 0x1800
+#define mmDCORE1_RTR7_DBG_ADDR_BASE 0x437D000ull
+#define DCORE1_RTR7_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE1_RTR7_DBG_ADDR_SECTION 0xE800
+#define mmDCORE1_RTR7_DBG_ADDR_SPECIAL_BASE 0x437DE80ull
+#define DCORE1_RTR7_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_RTR7_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define mmDCORE1_SRAM0_BANK_BASE 0x4380000ull
+#define DCORE1_SRAM0_BANK_MAX_OFFSET 0x1000
+#define DCORE1_SRAM0_BANK_SECTION 0xE800
+#define mmDCORE1_SRAM0_BANK_SPECIAL_BASE 0x4380E80ull
+#define DCORE1_SRAM0_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM0_BANK_SPECIAL_SECTION 0x1800
+#define mmDCORE1_SRAM0_RTR_BASE 0x4381000ull
+#define DCORE1_SRAM0_RTR_MAX_OFFSET 0x1000
+#define DCORE1_SRAM0_RTR_SECTION 0xE800
+#define mmDCORE1_SRAM0_RTR_SPECIAL_BASE 0x4381E80ull
+#define DCORE1_SRAM0_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM0_RTR_SPECIAL_SECTION 0x1800
+#define mmDCORE1_SRAM0_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4382000ull
+#define DCORE1_SRAM0_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM0_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM0_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4382100ull
+#define DCORE1_SRAM0_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM0_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4382200ull
+#define DCORE1_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4382300ull
+#define DCORE1_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM0_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4382400ull
+#define DCORE1_SRAM0_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM0_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM0_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4382500ull
+#define DCORE1_SRAM0_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM0_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM0_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4382600ull
+#define DCORE1_SRAM0_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM0_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4382700ull
+#define DCORE1_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4382780ull
+#define DCORE1_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4382800ull
+#define DCORE1_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4382880ull
+#define DCORE1_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4382900ull
+#define DCORE1_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4382980ull
+#define DCORE1_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4382A00ull
+#define DCORE1_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4382A80ull
+#define DCORE1_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define mmDCORE1_SRAM0_DBG_CNT_SPECIAL_BASE 0x4382E80ull
+#define DCORE1_SRAM0_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM0_DBG_CNT_SPECIAL_SECTION 0x5180
+#define mmDCORE1_SRAM1_BANK_BASE 0x4388000ull
+#define DCORE1_SRAM1_BANK_MAX_OFFSET 0x1000
+#define DCORE1_SRAM1_BANK_SECTION 0xE800
+#define mmDCORE1_SRAM1_BANK_SPECIAL_BASE 0x4388E80ull
+#define DCORE1_SRAM1_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM1_BANK_SPECIAL_SECTION 0x1800
+#define mmDCORE1_SRAM1_RTR_BASE 0x4389000ull
+#define DCORE1_SRAM1_RTR_MAX_OFFSET 0x1000
+#define DCORE1_SRAM1_RTR_SECTION 0xE800
+#define mmDCORE1_SRAM1_RTR_SPECIAL_BASE 0x4389E80ull
+#define DCORE1_SRAM1_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM1_RTR_SPECIAL_SECTION 0x1800
+#define mmDCORE1_SRAM1_DBG_CNT_N_HBW_DBG_CNT_BASE 0x438A000ull
+#define DCORE1_SRAM1_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM1_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM1_DBG_CNT_S_HBW_DBG_CNT_BASE 0x438A100ull
+#define DCORE1_SRAM1_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM1_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x438A200ull
+#define DCORE1_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x438A300ull
+#define DCORE1_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM1_DBG_CNT_N_LBW_DBG_CNT_BASE 0x438A400ull
+#define DCORE1_SRAM1_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM1_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM1_DBG_CNT_S_LBW_DBG_CNT_BASE 0x438A500ull
+#define DCORE1_SRAM1_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM1_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM1_DBG_CNT_L_LBW_DBG_CNT_BASE 0x438A600ull
+#define DCORE1_SRAM1_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM1_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x438A700ull
+#define DCORE1_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x438A780ull
+#define DCORE1_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x438A800ull
+#define DCORE1_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x438A880ull
+#define DCORE1_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x438A900ull
+#define DCORE1_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x438A980ull
+#define DCORE1_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x438AA00ull
+#define DCORE1_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x438AA80ull
+#define DCORE1_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define mmDCORE1_SRAM1_DBG_CNT_SPECIAL_BASE 0x438AE80ull
+#define DCORE1_SRAM1_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM1_DBG_CNT_SPECIAL_SECTION 0x5180
+#define mmDCORE1_SRAM2_BANK_BASE 0x4390000ull
+#define DCORE1_SRAM2_BANK_MAX_OFFSET 0x1000
+#define DCORE1_SRAM2_BANK_SECTION 0xE800
+#define mmDCORE1_SRAM2_BANK_SPECIAL_BASE 0x4390E80ull
+#define DCORE1_SRAM2_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM2_BANK_SPECIAL_SECTION 0x1800
+#define mmDCORE1_SRAM2_RTR_BASE 0x4391000ull
+#define DCORE1_SRAM2_RTR_MAX_OFFSET 0x1000
+#define DCORE1_SRAM2_RTR_SECTION 0xE800
+#define mmDCORE1_SRAM2_RTR_SPECIAL_BASE 0x4391E80ull
+#define DCORE1_SRAM2_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM2_RTR_SPECIAL_SECTION 0x1800
+#define mmDCORE1_SRAM2_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4392000ull
+#define DCORE1_SRAM2_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM2_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM2_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4392100ull
+#define DCORE1_SRAM2_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM2_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4392200ull
+#define DCORE1_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4392300ull
+#define DCORE1_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM2_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4392400ull
+#define DCORE1_SRAM2_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM2_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM2_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4392500ull
+#define DCORE1_SRAM2_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM2_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM2_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4392600ull
+#define DCORE1_SRAM2_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM2_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4392700ull
+#define DCORE1_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4392780ull
+#define DCORE1_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4392800ull
+#define DCORE1_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4392880ull
+#define DCORE1_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4392900ull
+#define DCORE1_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4392980ull
+#define DCORE1_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4392A00ull
+#define DCORE1_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4392A80ull
+#define DCORE1_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define mmDCORE1_SRAM2_DBG_CNT_SPECIAL_BASE 0x4392E80ull
+#define DCORE1_SRAM2_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM2_DBG_CNT_SPECIAL_SECTION 0x5180
+#define mmDCORE1_SRAM3_BANK_BASE 0x4398000ull
+#define DCORE1_SRAM3_BANK_MAX_OFFSET 0x1000
+#define DCORE1_SRAM3_BANK_SECTION 0xE800
+#define mmDCORE1_SRAM3_BANK_SPECIAL_BASE 0x4398E80ull
+#define DCORE1_SRAM3_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM3_BANK_SPECIAL_SECTION 0x1800
+#define mmDCORE1_SRAM3_RTR_BASE 0x4399000ull
+#define DCORE1_SRAM3_RTR_MAX_OFFSET 0x1000
+#define DCORE1_SRAM3_RTR_SECTION 0xE800
+#define mmDCORE1_SRAM3_RTR_SPECIAL_BASE 0x4399E80ull
+#define DCORE1_SRAM3_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM3_RTR_SPECIAL_SECTION 0x1800
+#define mmDCORE1_SRAM3_DBG_CNT_N_HBW_DBG_CNT_BASE 0x439A000ull
+#define DCORE1_SRAM3_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM3_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM3_DBG_CNT_S_HBW_DBG_CNT_BASE 0x439A100ull
+#define DCORE1_SRAM3_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM3_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x439A200ull
+#define DCORE1_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x439A300ull
+#define DCORE1_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM3_DBG_CNT_N_LBW_DBG_CNT_BASE 0x439A400ull
+#define DCORE1_SRAM3_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM3_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM3_DBG_CNT_S_LBW_DBG_CNT_BASE 0x439A500ull
+#define DCORE1_SRAM3_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM3_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM3_DBG_CNT_L_LBW_DBG_CNT_BASE 0x439A600ull
+#define DCORE1_SRAM3_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM3_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x439A700ull
+#define DCORE1_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x439A780ull
+#define DCORE1_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x439A800ull
+#define DCORE1_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x439A880ull
+#define DCORE1_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x439A900ull
+#define DCORE1_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x439A980ull
+#define DCORE1_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x439AA00ull
+#define DCORE1_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x439AA80ull
+#define DCORE1_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define mmDCORE1_SRAM3_DBG_CNT_SPECIAL_BASE 0x439AE80ull
+#define DCORE1_SRAM3_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM3_DBG_CNT_SPECIAL_SECTION 0x5180
+#define mmDCORE1_SRAM4_BANK_BASE 0x43A0000ull
+#define DCORE1_SRAM4_BANK_MAX_OFFSET 0x1000
+#define DCORE1_SRAM4_BANK_SECTION 0xE800
+#define mmDCORE1_SRAM4_BANK_SPECIAL_BASE 0x43A0E80ull
+#define DCORE1_SRAM4_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM4_BANK_SPECIAL_SECTION 0x1800
+#define mmDCORE1_SRAM4_RTR_BASE 0x43A1000ull
+#define DCORE1_SRAM4_RTR_MAX_OFFSET 0x1000
+#define DCORE1_SRAM4_RTR_SECTION 0xE800
+#define mmDCORE1_SRAM4_RTR_SPECIAL_BASE 0x43A1E80ull
+#define DCORE1_SRAM4_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM4_RTR_SPECIAL_SECTION 0x1800
+#define mmDCORE1_SRAM4_DBG_CNT_N_HBW_DBG_CNT_BASE 0x43A2000ull
+#define DCORE1_SRAM4_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM4_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM4_DBG_CNT_S_HBW_DBG_CNT_BASE 0x43A2100ull
+#define DCORE1_SRAM4_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM4_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x43A2200ull
+#define DCORE1_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x43A2300ull
+#define DCORE1_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM4_DBG_CNT_N_LBW_DBG_CNT_BASE 0x43A2400ull
+#define DCORE1_SRAM4_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM4_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM4_DBG_CNT_S_LBW_DBG_CNT_BASE 0x43A2500ull
+#define DCORE1_SRAM4_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM4_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM4_DBG_CNT_L_LBW_DBG_CNT_BASE 0x43A2600ull
+#define DCORE1_SRAM4_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM4_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x43A2700ull
+#define DCORE1_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x43A2780ull
+#define DCORE1_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x43A2800ull
+#define DCORE1_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x43A2880ull
+#define DCORE1_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x43A2900ull
+#define DCORE1_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x43A2980ull
+#define DCORE1_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x43A2A00ull
+#define DCORE1_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x43A2A80ull
+#define DCORE1_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define mmDCORE1_SRAM4_DBG_CNT_SPECIAL_BASE 0x43A2E80ull
+#define DCORE1_SRAM4_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM4_DBG_CNT_SPECIAL_SECTION 0x5180
+#define mmDCORE1_SRAM5_BANK_BASE 0x43A8000ull
+#define DCORE1_SRAM5_BANK_MAX_OFFSET 0x1000
+#define DCORE1_SRAM5_BANK_SECTION 0xE800
+#define mmDCORE1_SRAM5_BANK_SPECIAL_BASE 0x43A8E80ull
+#define DCORE1_SRAM5_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM5_BANK_SPECIAL_SECTION 0x1800
+#define mmDCORE1_SRAM5_RTR_BASE 0x43A9000ull
+#define DCORE1_SRAM5_RTR_MAX_OFFSET 0x1000
+#define DCORE1_SRAM5_RTR_SECTION 0xE800
+#define mmDCORE1_SRAM5_RTR_SPECIAL_BASE 0x43A9E80ull
+#define DCORE1_SRAM5_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM5_RTR_SPECIAL_SECTION 0x1800
+#define mmDCORE1_SRAM5_DBG_CNT_N_HBW_DBG_CNT_BASE 0x43AA000ull
+#define DCORE1_SRAM5_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM5_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM5_DBG_CNT_S_HBW_DBG_CNT_BASE 0x43AA100ull
+#define DCORE1_SRAM5_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM5_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x43AA200ull
+#define DCORE1_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x43AA300ull
+#define DCORE1_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM5_DBG_CNT_N_LBW_DBG_CNT_BASE 0x43AA400ull
+#define DCORE1_SRAM5_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM5_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM5_DBG_CNT_S_LBW_DBG_CNT_BASE 0x43AA500ull
+#define DCORE1_SRAM5_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM5_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM5_DBG_CNT_L_LBW_DBG_CNT_BASE 0x43AA600ull
+#define DCORE1_SRAM5_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM5_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x43AA700ull
+#define DCORE1_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x43AA780ull
+#define DCORE1_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x43AA800ull
+#define DCORE1_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x43AA880ull
+#define DCORE1_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x43AA900ull
+#define DCORE1_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x43AA980ull
+#define DCORE1_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x43AAA00ull
+#define DCORE1_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x43AAA80ull
+#define DCORE1_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define mmDCORE1_SRAM5_DBG_CNT_SPECIAL_BASE 0x43AAE80ull
+#define DCORE1_SRAM5_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM5_DBG_CNT_SPECIAL_SECTION 0x5180
+#define mmDCORE1_SRAM6_BANK_BASE 0x43B0000ull
+#define DCORE1_SRAM6_BANK_MAX_OFFSET 0x1000
+#define DCORE1_SRAM6_BANK_SECTION 0xE800
+#define mmDCORE1_SRAM6_BANK_SPECIAL_BASE 0x43B0E80ull
+#define DCORE1_SRAM6_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM6_BANK_SPECIAL_SECTION 0x1800
+#define mmDCORE1_SRAM6_RTR_BASE 0x43B1000ull
+#define DCORE1_SRAM6_RTR_MAX_OFFSET 0x1000
+#define DCORE1_SRAM6_RTR_SECTION 0xE800
+#define mmDCORE1_SRAM6_RTR_SPECIAL_BASE 0x43B1E80ull
+#define DCORE1_SRAM6_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM6_RTR_SPECIAL_SECTION 0x1800
+#define mmDCORE1_SRAM6_DBG_CNT_N_HBW_DBG_CNT_BASE 0x43B2000ull
+#define DCORE1_SRAM6_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM6_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM6_DBG_CNT_S_HBW_DBG_CNT_BASE 0x43B2100ull
+#define DCORE1_SRAM6_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM6_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x43B2200ull
+#define DCORE1_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x43B2300ull
+#define DCORE1_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM6_DBG_CNT_N_LBW_DBG_CNT_BASE 0x43B2400ull
+#define DCORE1_SRAM6_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM6_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM6_DBG_CNT_S_LBW_DBG_CNT_BASE 0x43B2500ull
+#define DCORE1_SRAM6_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM6_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM6_DBG_CNT_L_LBW_DBG_CNT_BASE 0x43B2600ull
+#define DCORE1_SRAM6_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM6_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x43B2700ull
+#define DCORE1_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x43B2780ull
+#define DCORE1_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x43B2800ull
+#define DCORE1_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x43B2880ull
+#define DCORE1_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x43B2900ull
+#define DCORE1_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x43B2980ull
+#define DCORE1_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x43B2A00ull
+#define DCORE1_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x43B2A80ull
+#define DCORE1_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define mmDCORE1_SRAM6_DBG_CNT_SPECIAL_BASE 0x43B2E80ull
+#define DCORE1_SRAM6_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM6_DBG_CNT_SPECIAL_SECTION 0x5180
+#define mmDCORE1_SRAM7_BANK_BASE 0x43B8000ull
+#define DCORE1_SRAM7_BANK_MAX_OFFSET 0x1000
+#define DCORE1_SRAM7_BANK_SECTION 0xE800
+#define mmDCORE1_SRAM7_BANK_SPECIAL_BASE 0x43B8E80ull
+#define DCORE1_SRAM7_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM7_BANK_SPECIAL_SECTION 0x1800
+#define mmDCORE1_SRAM7_RTR_BASE 0x43B9000ull
+#define DCORE1_SRAM7_RTR_MAX_OFFSET 0x1000
+#define DCORE1_SRAM7_RTR_SECTION 0xE800
+#define mmDCORE1_SRAM7_RTR_SPECIAL_BASE 0x43B9E80ull
+#define DCORE1_SRAM7_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM7_RTR_SPECIAL_SECTION 0x1800
+#define mmDCORE1_SRAM7_DBG_CNT_N_HBW_DBG_CNT_BASE 0x43BA000ull
+#define DCORE1_SRAM7_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM7_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM7_DBG_CNT_S_HBW_DBG_CNT_BASE 0x43BA100ull
+#define DCORE1_SRAM7_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM7_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x43BA200ull
+#define DCORE1_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x43BA300ull
+#define DCORE1_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM7_DBG_CNT_N_LBW_DBG_CNT_BASE 0x43BA400ull
+#define DCORE1_SRAM7_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM7_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM7_DBG_CNT_S_LBW_DBG_CNT_BASE 0x43BA500ull
+#define DCORE1_SRAM7_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM7_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM7_DBG_CNT_L_LBW_DBG_CNT_BASE 0x43BA600ull
+#define DCORE1_SRAM7_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE1_SRAM7_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE1_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x43BA700ull
+#define DCORE1_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x43BA780ull
+#define DCORE1_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x43BA800ull
+#define DCORE1_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x43BA880ull
+#define DCORE1_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x43BA900ull
+#define DCORE1_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x43BA980ull
+#define DCORE1_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x43BAA00ull
+#define DCORE1_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE1_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x43BAA80ull
+#define DCORE1_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE1_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define mmDCORE1_SRAM7_DBG_CNT_SPECIAL_BASE 0x43BAE80ull
+#define DCORE1_SRAM7_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_SRAM7_DBG_CNT_SPECIAL_SECTION 0x5180
+#define mmDCORE1_EDMA0_QM_DCCM_BASE 0x43C0000ull
+#define DCORE1_EDMA0_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE1_EDMA0_QM_DCCM_SECTION 0x8000
+#define mmDCORE1_EDMA0_QM_ARC_AUX_BASE 0x43C8000ull
+#define DCORE1_EDMA0_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE1_EDMA0_QM_ARC_AUX_SECTION 0xE800
+#define mmDCORE1_EDMA0_QM_ARC_AUX_SPECIAL_BASE 0x43C8E80ull
+#define DCORE1_EDMA0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_EDMA0_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define mmDCORE1_EDMA0_QM_BASE 0x43CA000ull
+#define DCORE1_EDMA0_QM_MAX_OFFSET 0x1000
+#define DCORE1_EDMA0_QM_SECTION 0x9000
+#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x43CA900ull
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x43CA908ull
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x43CA910ull
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x43CA918ull
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x43CA920ull
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x43CA928ull
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x43CA930ull
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x43CA938ull
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x43CA940ull
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x43CA948ull
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x43CA950ull
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x43CA958ull
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x43CA960ull
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x43CA968ull
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x43CA970ull
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x43CA978ull
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE1_EDMA0_QM_AXUSER_SECURED_BASE 0x43CAB00ull
+#define DCORE1_EDMA0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE1_EDMA0_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE1_EDMA0_QM_AXUSER_NONSECURED_BASE 0x43CAB80ull
+#define DCORE1_EDMA0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE1_EDMA0_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE1_EDMA0_QM_DBG_HBW_BASE 0x43CAC00ull
+#define DCORE1_EDMA0_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_EDMA0_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_EDMA0_QM_DBG_LBW_BASE 0x43CAC80ull
+#define DCORE1_EDMA0_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_EDMA0_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE1_EDMA0_QM_CGM_BASE 0x43CAD80ull
+#define DCORE1_EDMA0_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE1_EDMA0_QM_CGM_SECTION 0x1000
+#define mmDCORE1_EDMA0_QM_SPECIAL_BASE 0x43CAE80ull
+#define DCORE1_EDMA0_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_EDMA0_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE1_EDMA0_CORE_BASE 0x43CB000ull
+#define DCORE1_EDMA0_CORE_MAX_OFFSET 0x1000
+#define DCORE1_EDMA0_CORE_SECTION 0x8000
+#define mmDCORE1_EDMA0_CORE_CTX_AXUSER_BASE 0x43CB800ull
+#define DCORE1_EDMA0_CORE_CTX_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_EDMA0_CORE_CTX_AXUSER_SECTION 0x6000
+#define mmDCORE1_EDMA0_CORE_CTX_BASE 0x43CB860ull
+#define DCORE1_EDMA0_CORE_CTX_MAX_OFFSET 0x9000
+#define DCORE1_EDMA0_CORE_CTX_SECTION 0x5A00
+#define mmDCORE1_EDMA0_CORE_KDMA_CGM_BASE 0x43CBE00ull
+#define DCORE1_EDMA0_CORE_KDMA_CGM_MAX_OFFSET 0xC000
+#define DCORE1_EDMA0_CORE_KDMA_CGM_SECTION 0x8000
+#define mmDCORE1_EDMA0_CORE_SPECIAL_BASE 0x43CBE80ull
+#define DCORE1_EDMA0_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_EDMA0_CORE_SPECIAL_SECTION 0x1800
+#define mmDCORE1_EDMA0_MSTR_IF_RR_SHRD_HBW_BASE 0x43CC000ull
+#define DCORE1_EDMA0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_EDMA0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE1_EDMA0_MSTR_IF_RR_PRVT_HBW_BASE 0x43CC200ull
+#define DCORE1_EDMA0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_EDMA0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE1_EDMA0_MSTR_IF_RR_SHRD_LBW_BASE 0x43CC400ull
+#define DCORE1_EDMA0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_EDMA0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE1_EDMA0_MSTR_IF_RR_PRVT_LBW_BASE 0x43CC600ull
+#define DCORE1_EDMA0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_EDMA0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE1_EDMA0_MSTR_IF_E2E_CRDT_BASE 0x43CC800ull
+#define DCORE1_EDMA0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_EDMA0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE1_EDMA0_MSTR_IF_AXUSER_BASE 0x43CCA80ull
+#define DCORE1_EDMA0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_EDMA0_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE1_EDMA0_MSTR_IF_DBG_HBW_BASE 0x43CCB00ull
+#define DCORE1_EDMA0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_EDMA0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_EDMA0_MSTR_IF_DBG_LBW_BASE 0x43CCB80ull
+#define DCORE1_EDMA0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_EDMA0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE1_EDMA0_MSTR_IF_CORE_HBW_BASE 0x43CCC00ull
+#define DCORE1_EDMA0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_EDMA0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE1_EDMA0_MSTR_IF_CORE_LBW_BASE 0x43CCD80ull
+#define DCORE1_EDMA0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_EDMA0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE1_EDMA0_MSTR_IF_SPECIAL_BASE 0x43CCE80ull
+#define DCORE1_EDMA0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_EDMA0_MSTR_IF_SPECIAL_SECTION 0x3180
+#define mmDCORE1_EDMA1_QM_DCCM_BASE 0x43D0000ull
+#define DCORE1_EDMA1_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE1_EDMA1_QM_DCCM_SECTION 0x8000
+#define mmDCORE1_EDMA1_QM_ARC_AUX_BASE 0x43D8000ull
+#define DCORE1_EDMA1_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE1_EDMA1_QM_ARC_AUX_SECTION 0xE800
+#define mmDCORE1_EDMA1_QM_ARC_AUX_SPECIAL_BASE 0x43D8E80ull
+#define DCORE1_EDMA1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_EDMA1_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define mmDCORE1_EDMA1_QM_BASE 0x43DA000ull
+#define DCORE1_EDMA1_QM_MAX_OFFSET 0x1000
+#define DCORE1_EDMA1_QM_SECTION 0x9000
+#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x43DA900ull
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x43DA908ull
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x43DA910ull
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x43DA918ull
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x43DA920ull
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x43DA928ull
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x43DA930ull
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x43DA938ull
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x43DA940ull
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x43DA948ull
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x43DA950ull
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x43DA958ull
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x43DA960ull
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x43DA968ull
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x43DA970ull
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x43DA978ull
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE1_EDMA1_QM_AXUSER_SECURED_BASE 0x43DAB00ull
+#define DCORE1_EDMA1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE1_EDMA1_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE1_EDMA1_QM_AXUSER_NONSECURED_BASE 0x43DAB80ull
+#define DCORE1_EDMA1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE1_EDMA1_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE1_EDMA1_QM_DBG_HBW_BASE 0x43DAC00ull
+#define DCORE1_EDMA1_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_EDMA1_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_EDMA1_QM_DBG_LBW_BASE 0x43DAC80ull
+#define DCORE1_EDMA1_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_EDMA1_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE1_EDMA1_QM_CGM_BASE 0x43DAD80ull
+#define DCORE1_EDMA1_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE1_EDMA1_QM_CGM_SECTION 0x1000
+#define mmDCORE1_EDMA1_QM_SPECIAL_BASE 0x43DAE80ull
+#define DCORE1_EDMA1_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_EDMA1_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE1_EDMA1_CORE_BASE 0x43DB000ull
+#define DCORE1_EDMA1_CORE_MAX_OFFSET 0x1000
+#define DCORE1_EDMA1_CORE_SECTION 0x8000
+#define mmDCORE1_EDMA1_CORE_CTX_AXUSER_BASE 0x43DB800ull
+#define DCORE1_EDMA1_CORE_CTX_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_EDMA1_CORE_CTX_AXUSER_SECTION 0x6000
+#define mmDCORE1_EDMA1_CORE_CTX_BASE 0x43DB860ull
+#define DCORE1_EDMA1_CORE_CTX_MAX_OFFSET 0x9000
+#define DCORE1_EDMA1_CORE_CTX_SECTION 0x5A00
+#define mmDCORE1_EDMA1_CORE_KDMA_CGM_BASE 0x43DBE00ull
+#define DCORE1_EDMA1_CORE_KDMA_CGM_MAX_OFFSET 0xC000
+#define DCORE1_EDMA1_CORE_KDMA_CGM_SECTION 0x8000
+#define mmDCORE1_EDMA1_CORE_SPECIAL_BASE 0x43DBE80ull
+#define DCORE1_EDMA1_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_EDMA1_CORE_SPECIAL_SECTION 0x1800
+#define mmDCORE1_EDMA1_MSTR_IF_RR_SHRD_HBW_BASE 0x43DC000ull
+#define DCORE1_EDMA1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_EDMA1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE1_EDMA1_MSTR_IF_RR_PRVT_HBW_BASE 0x43DC200ull
+#define DCORE1_EDMA1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_EDMA1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE1_EDMA1_MSTR_IF_RR_SHRD_LBW_BASE 0x43DC400ull
+#define DCORE1_EDMA1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_EDMA1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE1_EDMA1_MSTR_IF_RR_PRVT_LBW_BASE 0x43DC600ull
+#define DCORE1_EDMA1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_EDMA1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE1_EDMA1_MSTR_IF_E2E_CRDT_BASE 0x43DC800ull
+#define DCORE1_EDMA1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_EDMA1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE1_EDMA1_MSTR_IF_AXUSER_BASE 0x43DCA80ull
+#define DCORE1_EDMA1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_EDMA1_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE1_EDMA1_MSTR_IF_DBG_HBW_BASE 0x43DCB00ull
+#define DCORE1_EDMA1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_EDMA1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_EDMA1_MSTR_IF_DBG_LBW_BASE 0x43DCB80ull
+#define DCORE1_EDMA1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_EDMA1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE1_EDMA1_MSTR_IF_CORE_HBW_BASE 0x43DCC00ull
+#define DCORE1_EDMA1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_EDMA1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE1_EDMA1_MSTR_IF_CORE_LBW_BASE 0x43DCD80ull
+#define DCORE1_EDMA1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_EDMA1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE1_EDMA1_MSTR_IF_SPECIAL_BASE 0x43DCE80ull
+#define DCORE1_EDMA1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_EDMA1_MSTR_IF_SPECIAL_SECTION 0x3180
+#define mmDCORE1_DEC0_CMD_BASE 0x43E0000ull
+#define DCORE1_DEC0_CMD_MAX_OFFSET 0x1100
+#define DCORE1_DEC0_CMD_SECTION 0x1000
+#define mmDCORE1_DEC0_VSI_BASE 0x43E1000ull
+#define DCORE1_DEC0_VSI_MAX_OFFSET 0x6FC0
+#define DCORE1_DEC0_VSI_SECTION 0x1000
+#define mmDCORE1_DEC0_L2C_BASE 0x43E2000ull
+#define DCORE1_DEC0_L2C_MAX_OFFSET 0x39C0
+#define DCORE1_DEC0_L2C_SECTION 0x1000
+#define mmDCORE1_VDEC0_BRDG_CTRL_BASE 0x43E3000ull
+#define DCORE1_VDEC0_BRDG_CTRL_MAX_OFFSET 0x1000
+#define DCORE1_VDEC0_BRDG_CTRL_SECTION 0x8000
+#define mmDCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x43E3800ull
+#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000
+#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000
+#define mmDCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x43E3900ull
+#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000
+#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000
+#define mmDCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x43E3A00ull
+#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000
+#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000
+#define mmDCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x43E3B00ull
+#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000
+#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000
+#define mmDCORE1_VDEC0_BRDG_CTRL_AXUSER_DEC_BASE 0x43E3C00ull
+#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000
+#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800
+#define mmDCORE1_VDEC0_BRDG_CTRL_SPECIAL_BASE 0x43E3E80ull
+#define DCORE1_VDEC0_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_VDEC0_BRDG_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE1_VDEC0_CTRL_BASE 0x43E4000ull
+#define DCORE1_VDEC0_CTRL_MAX_OFFSET 0x1000
+#define DCORE1_VDEC0_CTRL_SECTION 0xE800
+#define mmDCORE1_VDEC0_CTRL_SPECIAL_BASE 0x43E4E80ull
+#define DCORE1_VDEC0_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_VDEC0_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE1_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE 0x43E5000ull
+#define DCORE1_VDEC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_VDEC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE1_VDEC0_MSTR_IF_RR_PRVT_HBW_BASE 0x43E5200ull
+#define DCORE1_VDEC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_VDEC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE1_VDEC0_MSTR_IF_RR_SHRD_LBW_BASE 0x43E5400ull
+#define DCORE1_VDEC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_VDEC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE1_VDEC0_MSTR_IF_RR_PRVT_LBW_BASE 0x43E5600ull
+#define DCORE1_VDEC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_VDEC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE1_VDEC0_MSTR_IF_E2E_CRDT_BASE 0x43E5800ull
+#define DCORE1_VDEC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_VDEC0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE1_VDEC0_MSTR_IF_AXUSER_BASE 0x43E5A80ull
+#define DCORE1_VDEC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_VDEC0_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE1_VDEC0_MSTR_IF_DBG_HBW_BASE 0x43E5B00ull
+#define DCORE1_VDEC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_VDEC0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_VDEC0_MSTR_IF_DBG_LBW_BASE 0x43E5B80ull
+#define DCORE1_VDEC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_VDEC0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE1_VDEC0_MSTR_IF_CORE_HBW_BASE 0x43E5C00ull
+#define DCORE1_VDEC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_VDEC0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE1_VDEC0_MSTR_IF_CORE_LBW_BASE 0x43E5D80ull
+#define DCORE1_VDEC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_VDEC0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE1_VDEC0_MSTR_IF_SPECIAL_BASE 0x43E5E80ull
+#define DCORE1_VDEC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_VDEC0_MSTR_IF_SPECIAL_SECTION 0xA180
+#define mmDCORE1_DEC1_CMD_BASE 0x43F0000ull
+#define DCORE1_DEC1_CMD_MAX_OFFSET 0x1100
+#define DCORE1_DEC1_CMD_SECTION 0x1000
+#define mmDCORE1_DEC1_VSI_BASE 0x43F1000ull
+#define DCORE1_DEC1_VSI_MAX_OFFSET 0x6FC0
+#define DCORE1_DEC1_VSI_SECTION 0x1000
+#define mmDCORE1_DEC1_L2C_BASE 0x43F2000ull
+#define DCORE1_DEC1_L2C_MAX_OFFSET 0x39C0
+#define DCORE1_DEC1_L2C_SECTION 0x1000
+#define mmDCORE1_VDEC1_BRDG_CTRL_BASE 0x43F3000ull
+#define DCORE1_VDEC1_BRDG_CTRL_MAX_OFFSET 0x1000
+#define DCORE1_VDEC1_BRDG_CTRL_SECTION 0x8000
+#define mmDCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x43F3800ull
+#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000
+#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000
+#define mmDCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x43F3900ull
+#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000
+#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000
+#define mmDCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x43F3A00ull
+#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000
+#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000
+#define mmDCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x43F3B00ull
+#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000
+#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000
+#define mmDCORE1_VDEC1_BRDG_CTRL_AXUSER_DEC_BASE 0x43F3C00ull
+#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000
+#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800
+#define mmDCORE1_VDEC1_BRDG_CTRL_SPECIAL_BASE 0x43F3E80ull
+#define DCORE1_VDEC1_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_VDEC1_BRDG_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE1_VDEC1_CTRL_BASE 0x43F4000ull
+#define DCORE1_VDEC1_CTRL_MAX_OFFSET 0x1000
+#define DCORE1_VDEC1_CTRL_SECTION 0xE800
+#define mmDCORE1_VDEC1_CTRL_SPECIAL_BASE 0x43F4E80ull
+#define DCORE1_VDEC1_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_VDEC1_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE1_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE 0x43F5000ull
+#define DCORE1_VDEC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_VDEC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE1_VDEC1_MSTR_IF_RR_PRVT_HBW_BASE 0x43F5200ull
+#define DCORE1_VDEC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE1_VDEC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE1_VDEC1_MSTR_IF_RR_SHRD_LBW_BASE 0x43F5400ull
+#define DCORE1_VDEC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_VDEC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE1_VDEC1_MSTR_IF_RR_PRVT_LBW_BASE 0x43F5600ull
+#define DCORE1_VDEC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE1_VDEC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE1_VDEC1_MSTR_IF_E2E_CRDT_BASE 0x43F5800ull
+#define DCORE1_VDEC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE1_VDEC1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE1_VDEC1_MSTR_IF_AXUSER_BASE 0x43F5A80ull
+#define DCORE1_VDEC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE1_VDEC1_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE1_VDEC1_MSTR_IF_DBG_HBW_BASE 0x43F5B00ull
+#define DCORE1_VDEC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE1_VDEC1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE1_VDEC1_MSTR_IF_DBG_LBW_BASE 0x43F5B80ull
+#define DCORE1_VDEC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE1_VDEC1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE1_VDEC1_MSTR_IF_CORE_HBW_BASE 0x43F5C00ull
+#define DCORE1_VDEC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE1_VDEC1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE1_VDEC1_MSTR_IF_CORE_LBW_BASE 0x43F5D80ull
+#define DCORE1_VDEC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE1_VDEC1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE1_VDEC1_MSTR_IF_SPECIAL_BASE 0x43F5E80ull
+#define DCORE1_VDEC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_VDEC1_MSTR_IF_SPECIAL_SECTION 0xA180
+#define mmDCORE2_TPC0_QM_DCCM_BASE 0x4400000ull
+#define DCORE2_TPC0_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE2_TPC0_QM_DCCM_SECTION 0x8000
+#define mmDCORE2_TPC0_QM_ARC_AUX_BASE 0x4408000ull
+#define DCORE2_TPC0_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE2_TPC0_QM_ARC_AUX_SECTION 0xE800
+#define mmDCORE2_TPC0_QM_ARC_AUX_SPECIAL_BASE 0x4408E80ull
+#define DCORE2_TPC0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC0_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define mmDCORE2_TPC0_QM_BASE 0x440A000ull
+#define DCORE2_TPC0_QM_MAX_OFFSET 0x1000
+#define DCORE2_TPC0_QM_SECTION 0x9000
+#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x440A900ull
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x440A908ull
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x440A910ull
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x440A918ull
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x440A920ull
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x440A928ull
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x440A930ull
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x440A938ull
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x440A940ull
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x440A948ull
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x440A950ull
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x440A958ull
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x440A960ull
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x440A968ull
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x440A970ull
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x440A978ull
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE2_TPC0_QM_AXUSER_SECURED_BASE 0x440AB00ull
+#define DCORE2_TPC0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE2_TPC0_QM_AXUSER_NONSECURED_BASE 0x440AB80ull
+#define DCORE2_TPC0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE2_TPC0_QM_DBG_HBW_BASE 0x440AC00ull
+#define DCORE2_TPC0_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC0_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_TPC0_QM_DBG_LBW_BASE 0x440AC80ull
+#define DCORE2_TPC0_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC0_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE2_TPC0_QM_CGM_BASE 0x440AD80ull
+#define DCORE2_TPC0_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE2_TPC0_QM_CGM_SECTION 0x1000
+#define mmDCORE2_TPC0_QM_SPECIAL_BASE 0x440AE80ull
+#define DCORE2_TPC0_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC0_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_0_BASE 0x440B000ull
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE2_TPC0_CFG_BASE 0x440B000ull
+#define DCORE2_TPC0_CFG_MAX_OFFSET 0x1000
+#define DCORE2_TPC0_CFG_SECTION 0x5000
+#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_1_BASE 0x440B050ull
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_2_BASE 0x440B0A0ull
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_3_BASE 0x440B0F0ull
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_4_BASE 0x440B140ull
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_5_BASE 0x440B190ull
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_6_BASE 0x440B1E0ull
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_7_BASE 0x440B230ull
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_8_BASE 0x440B280ull
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_9_BASE 0x440B2D0ull
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_10_BASE 0x440B320ull
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_11_BASE 0x440B370ull
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_12_BASE 0x440B3C0ull
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_13_BASE 0x440B410ull
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_14_BASE 0x440B460ull
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_15_BASE 0x440B4B0ull
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE2_TPC0_CFG_KERNEL_SYNC_OBJECT_BASE 0x440B500ull
+#define DCORE2_TPC0_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE2_TPC0_CFG_KERNEL_BASE 0x440B508ull
+#define DCORE2_TPC0_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE2_TPC0_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE2_TPC0_CFG_QM_TENSOR_0_BASE 0x440B5DCull
+#define DCORE2_TPC0_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE2_TPC0_CFG_QM_TENSOR_1_BASE 0x440B62Cull
+#define DCORE2_TPC0_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE2_TPC0_CFG_QM_TENSOR_2_BASE 0x440B67Cull
+#define DCORE2_TPC0_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE2_TPC0_CFG_QM_TENSOR_3_BASE 0x440B6CCull
+#define DCORE2_TPC0_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE2_TPC0_CFG_QM_TENSOR_4_BASE 0x440B71Cull
+#define DCORE2_TPC0_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE2_TPC0_CFG_QM_TENSOR_5_BASE 0x440B76Cull
+#define DCORE2_TPC0_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE2_TPC0_CFG_QM_TENSOR_6_BASE 0x440B7BCull
+#define DCORE2_TPC0_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE2_TPC0_CFG_QM_TENSOR_7_BASE 0x440B80Cull
+#define DCORE2_TPC0_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE2_TPC0_CFG_QM_TENSOR_8_BASE 0x440B85Cull
+#define DCORE2_TPC0_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE2_TPC0_CFG_QM_TENSOR_9_BASE 0x440B8ACull
+#define DCORE2_TPC0_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE2_TPC0_CFG_QM_TENSOR_10_BASE 0x440B8FCull
+#define DCORE2_TPC0_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE2_TPC0_CFG_QM_TENSOR_11_BASE 0x440B94Cull
+#define DCORE2_TPC0_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE2_TPC0_CFG_QM_TENSOR_12_BASE 0x440B99Cull
+#define DCORE2_TPC0_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE2_TPC0_CFG_QM_TENSOR_13_BASE 0x440B9ECull
+#define DCORE2_TPC0_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE2_TPC0_CFG_QM_TENSOR_14_BASE 0x440BA3Cull
+#define DCORE2_TPC0_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE2_TPC0_CFG_QM_TENSOR_15_BASE 0x440BA8Cull
+#define DCORE2_TPC0_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE2_TPC0_CFG_QM_SYNC_OBJECT_BASE 0x440BADCull
+#define DCORE2_TPC0_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE2_TPC0_CFG_QM_BASE 0x440BAE4ull
+#define DCORE2_TPC0_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE2_TPC0_CFG_QM_SECTION 0x31C0
+#define mmDCORE2_TPC0_CFG_AXUSER_BASE 0x440BE00ull
+#define DCORE2_TPC0_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE2_TPC0_CFG_SPECIAL_BASE 0x440BE80ull
+#define DCORE2_TPC0_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC0_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE2_TPC0_MSTR_IF_RR_SHRD_HBW_BASE 0x440C000ull
+#define DCORE2_TPC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_TPC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE2_TPC0_MSTR_IF_RR_PRVT_HBW_BASE 0x440C200ull
+#define DCORE2_TPC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_TPC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE2_TPC0_MSTR_IF_RR_SHRD_LBW_BASE 0x440C400ull
+#define DCORE2_TPC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_TPC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE2_TPC0_MSTR_IF_RR_PRVT_LBW_BASE 0x440C600ull
+#define DCORE2_TPC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_TPC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE2_TPC0_MSTR_IF_E2E_CRDT_BASE 0x440C800ull
+#define DCORE2_TPC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_TPC0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE2_TPC0_MSTR_IF_AXUSER_BASE 0x440CA80ull
+#define DCORE2_TPC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_TPC0_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE2_TPC0_MSTR_IF_DBG_HBW_BASE 0x440CB00ull
+#define DCORE2_TPC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_TPC0_MSTR_IF_DBG_LBW_BASE 0x440CB80ull
+#define DCORE2_TPC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE2_TPC0_MSTR_IF_CORE_HBW_BASE 0x440CC00ull
+#define DCORE2_TPC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_TPC0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE2_TPC0_MSTR_IF_CORE_LBW_BASE 0x440CD80ull
+#define DCORE2_TPC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_TPC0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE2_TPC0_MSTR_IF_SPECIAL_BASE 0x440CE80ull
+#define DCORE2_TPC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC0_MSTR_IF_SPECIAL_SECTION 0x3180
+#define mmDCORE2_TPC1_QM_DCCM_BASE 0x4410000ull
+#define DCORE2_TPC1_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE2_TPC1_QM_DCCM_SECTION 0x8000
+#define mmDCORE2_TPC1_QM_ARC_AUX_BASE 0x4418000ull
+#define DCORE2_TPC1_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE2_TPC1_QM_ARC_AUX_SECTION 0xE800
+#define mmDCORE2_TPC1_QM_ARC_AUX_SPECIAL_BASE 0x4418E80ull
+#define DCORE2_TPC1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC1_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define mmDCORE2_TPC1_QM_BASE 0x441A000ull
+#define DCORE2_TPC1_QM_MAX_OFFSET 0x1000
+#define DCORE2_TPC1_QM_SECTION 0x9000
+#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x441A900ull
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x441A908ull
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x441A910ull
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x441A918ull
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x441A920ull
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x441A928ull
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x441A930ull
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x441A938ull
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x441A940ull
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x441A948ull
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x441A950ull
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x441A958ull
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x441A960ull
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x441A968ull
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x441A970ull
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x441A978ull
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE2_TPC1_QM_AXUSER_SECURED_BASE 0x441AB00ull
+#define DCORE2_TPC1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE2_TPC1_QM_AXUSER_NONSECURED_BASE 0x441AB80ull
+#define DCORE2_TPC1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE2_TPC1_QM_DBG_HBW_BASE 0x441AC00ull
+#define DCORE2_TPC1_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC1_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_TPC1_QM_DBG_LBW_BASE 0x441AC80ull
+#define DCORE2_TPC1_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC1_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE2_TPC1_QM_CGM_BASE 0x441AD80ull
+#define DCORE2_TPC1_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE2_TPC1_QM_CGM_SECTION 0x1000
+#define mmDCORE2_TPC1_QM_SPECIAL_BASE 0x441AE80ull
+#define DCORE2_TPC1_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC1_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_0_BASE 0x441B000ull
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE2_TPC1_CFG_BASE 0x441B000ull
+#define DCORE2_TPC1_CFG_MAX_OFFSET 0x1000
+#define DCORE2_TPC1_CFG_SECTION 0x5000
+#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_1_BASE 0x441B050ull
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_2_BASE 0x441B0A0ull
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_3_BASE 0x441B0F0ull
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_4_BASE 0x441B140ull
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_5_BASE 0x441B190ull
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_6_BASE 0x441B1E0ull
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_7_BASE 0x441B230ull
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_8_BASE 0x441B280ull
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_9_BASE 0x441B2D0ull
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_10_BASE 0x441B320ull
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_11_BASE 0x441B370ull
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_12_BASE 0x441B3C0ull
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_13_BASE 0x441B410ull
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_14_BASE 0x441B460ull
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_15_BASE 0x441B4B0ull
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE2_TPC1_CFG_KERNEL_SYNC_OBJECT_BASE 0x441B500ull
+#define DCORE2_TPC1_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE2_TPC1_CFG_KERNEL_BASE 0x441B508ull
+#define DCORE2_TPC1_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE2_TPC1_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE2_TPC1_CFG_QM_TENSOR_0_BASE 0x441B5DCull
+#define DCORE2_TPC1_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE2_TPC1_CFG_QM_TENSOR_1_BASE 0x441B62Cull
+#define DCORE2_TPC1_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE2_TPC1_CFG_QM_TENSOR_2_BASE 0x441B67Cull
+#define DCORE2_TPC1_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE2_TPC1_CFG_QM_TENSOR_3_BASE 0x441B6CCull
+#define DCORE2_TPC1_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE2_TPC1_CFG_QM_TENSOR_4_BASE 0x441B71Cull
+#define DCORE2_TPC1_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE2_TPC1_CFG_QM_TENSOR_5_BASE 0x441B76Cull
+#define DCORE2_TPC1_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE2_TPC1_CFG_QM_TENSOR_6_BASE 0x441B7BCull
+#define DCORE2_TPC1_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE2_TPC1_CFG_QM_TENSOR_7_BASE 0x441B80Cull
+#define DCORE2_TPC1_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE2_TPC1_CFG_QM_TENSOR_8_BASE 0x441B85Cull
+#define DCORE2_TPC1_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE2_TPC1_CFG_QM_TENSOR_9_BASE 0x441B8ACull
+#define DCORE2_TPC1_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE2_TPC1_CFG_QM_TENSOR_10_BASE 0x441B8FCull
+#define DCORE2_TPC1_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE2_TPC1_CFG_QM_TENSOR_11_BASE 0x441B94Cull
+#define DCORE2_TPC1_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE2_TPC1_CFG_QM_TENSOR_12_BASE 0x441B99Cull
+#define DCORE2_TPC1_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE2_TPC1_CFG_QM_TENSOR_13_BASE 0x441B9ECull
+#define DCORE2_TPC1_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE2_TPC1_CFG_QM_TENSOR_14_BASE 0x441BA3Cull
+#define DCORE2_TPC1_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE2_TPC1_CFG_QM_TENSOR_15_BASE 0x441BA8Cull
+#define DCORE2_TPC1_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE2_TPC1_CFG_QM_SYNC_OBJECT_BASE 0x441BADCull
+#define DCORE2_TPC1_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE2_TPC1_CFG_QM_BASE 0x441BAE4ull
+#define DCORE2_TPC1_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE2_TPC1_CFG_QM_SECTION 0x31C0
+#define mmDCORE2_TPC1_CFG_AXUSER_BASE 0x441BE00ull
+#define DCORE2_TPC1_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE2_TPC1_CFG_SPECIAL_BASE 0x441BE80ull
+#define DCORE2_TPC1_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC1_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE2_TPC1_MSTR_IF_RR_SHRD_HBW_BASE 0x441C000ull
+#define DCORE2_TPC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_TPC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE2_TPC1_MSTR_IF_RR_PRVT_HBW_BASE 0x441C200ull
+#define DCORE2_TPC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_TPC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE2_TPC1_MSTR_IF_RR_SHRD_LBW_BASE 0x441C400ull
+#define DCORE2_TPC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_TPC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE2_TPC1_MSTR_IF_RR_PRVT_LBW_BASE 0x441C600ull
+#define DCORE2_TPC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_TPC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE2_TPC1_MSTR_IF_E2E_CRDT_BASE 0x441C800ull
+#define DCORE2_TPC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_TPC1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE2_TPC1_MSTR_IF_AXUSER_BASE 0x441CA80ull
+#define DCORE2_TPC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_TPC1_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE2_TPC1_MSTR_IF_DBG_HBW_BASE 0x441CB00ull
+#define DCORE2_TPC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_TPC1_MSTR_IF_DBG_LBW_BASE 0x441CB80ull
+#define DCORE2_TPC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE2_TPC1_MSTR_IF_CORE_HBW_BASE 0x441CC00ull
+#define DCORE2_TPC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_TPC1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE2_TPC1_MSTR_IF_CORE_LBW_BASE 0x441CD80ull
+#define DCORE2_TPC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_TPC1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE2_TPC1_MSTR_IF_SPECIAL_BASE 0x441CE80ull
+#define DCORE2_TPC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC1_MSTR_IF_SPECIAL_SECTION 0x3180
+#define mmDCORE2_TPC2_QM_DCCM_BASE 0x4420000ull
+#define DCORE2_TPC2_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE2_TPC2_QM_DCCM_SECTION 0x8000
+#define mmDCORE2_TPC2_QM_ARC_AUX_BASE 0x4428000ull
+#define DCORE2_TPC2_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE2_TPC2_QM_ARC_AUX_SECTION 0xE800
+#define mmDCORE2_TPC2_QM_ARC_AUX_SPECIAL_BASE 0x4428E80ull
+#define DCORE2_TPC2_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC2_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define mmDCORE2_TPC2_QM_BASE 0x442A000ull
+#define DCORE2_TPC2_QM_MAX_OFFSET 0x1000
+#define DCORE2_TPC2_QM_SECTION 0x9000
+#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR0_BASE 0x442A900ull
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR1_BASE 0x442A908ull
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR2_BASE 0x442A910ull
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR3_BASE 0x442A918ull
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR4_BASE 0x442A920ull
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR5_BASE 0x442A928ull
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR6_BASE 0x442A930ull
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR7_BASE 0x442A938ull
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR8_BASE 0x442A940ull
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR9_BASE 0x442A948ull
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR10_BASE 0x442A950ull
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR11_BASE 0x442A958ull
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR12_BASE 0x442A960ull
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR13_BASE 0x442A968ull
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR14_BASE 0x442A970ull
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR15_BASE 0x442A978ull
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE2_TPC2_QM_AXUSER_SECURED_BASE 0x442AB00ull
+#define DCORE2_TPC2_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE2_TPC2_QM_AXUSER_NONSECURED_BASE 0x442AB80ull
+#define DCORE2_TPC2_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE2_TPC2_QM_DBG_HBW_BASE 0x442AC00ull
+#define DCORE2_TPC2_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC2_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_TPC2_QM_DBG_LBW_BASE 0x442AC80ull
+#define DCORE2_TPC2_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC2_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE2_TPC2_QM_CGM_BASE 0x442AD80ull
+#define DCORE2_TPC2_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE2_TPC2_QM_CGM_SECTION 0x1000
+#define mmDCORE2_TPC2_QM_SPECIAL_BASE 0x442AE80ull
+#define DCORE2_TPC2_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC2_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_0_BASE 0x442B000ull
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE2_TPC2_CFG_BASE 0x442B000ull
+#define DCORE2_TPC2_CFG_MAX_OFFSET 0x1000
+#define DCORE2_TPC2_CFG_SECTION 0x5000
+#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_1_BASE 0x442B050ull
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_2_BASE 0x442B0A0ull
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_3_BASE 0x442B0F0ull
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_4_BASE 0x442B140ull
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_5_BASE 0x442B190ull
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_6_BASE 0x442B1E0ull
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_7_BASE 0x442B230ull
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_8_BASE 0x442B280ull
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_9_BASE 0x442B2D0ull
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_10_BASE 0x442B320ull
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_11_BASE 0x442B370ull
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_12_BASE 0x442B3C0ull
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_13_BASE 0x442B410ull
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_14_BASE 0x442B460ull
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_15_BASE 0x442B4B0ull
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE2_TPC2_CFG_KERNEL_SYNC_OBJECT_BASE 0x442B500ull
+#define DCORE2_TPC2_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE2_TPC2_CFG_KERNEL_BASE 0x442B508ull
+#define DCORE2_TPC2_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE2_TPC2_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE2_TPC2_CFG_QM_TENSOR_0_BASE 0x442B5DCull
+#define DCORE2_TPC2_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE2_TPC2_CFG_QM_TENSOR_1_BASE 0x442B62Cull
+#define DCORE2_TPC2_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE2_TPC2_CFG_QM_TENSOR_2_BASE 0x442B67Cull
+#define DCORE2_TPC2_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE2_TPC2_CFG_QM_TENSOR_3_BASE 0x442B6CCull
+#define DCORE2_TPC2_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE2_TPC2_CFG_QM_TENSOR_4_BASE 0x442B71Cull
+#define DCORE2_TPC2_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE2_TPC2_CFG_QM_TENSOR_5_BASE 0x442B76Cull
+#define DCORE2_TPC2_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE2_TPC2_CFG_QM_TENSOR_6_BASE 0x442B7BCull
+#define DCORE2_TPC2_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE2_TPC2_CFG_QM_TENSOR_7_BASE 0x442B80Cull
+#define DCORE2_TPC2_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE2_TPC2_CFG_QM_TENSOR_8_BASE 0x442B85Cull
+#define DCORE2_TPC2_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE2_TPC2_CFG_QM_TENSOR_9_BASE 0x442B8ACull
+#define DCORE2_TPC2_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE2_TPC2_CFG_QM_TENSOR_10_BASE 0x442B8FCull
+#define DCORE2_TPC2_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE2_TPC2_CFG_QM_TENSOR_11_BASE 0x442B94Cull
+#define DCORE2_TPC2_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE2_TPC2_CFG_QM_TENSOR_12_BASE 0x442B99Cull
+#define DCORE2_TPC2_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE2_TPC2_CFG_QM_TENSOR_13_BASE 0x442B9ECull
+#define DCORE2_TPC2_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE2_TPC2_CFG_QM_TENSOR_14_BASE 0x442BA3Cull
+#define DCORE2_TPC2_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE2_TPC2_CFG_QM_TENSOR_15_BASE 0x442BA8Cull
+#define DCORE2_TPC2_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE2_TPC2_CFG_QM_SYNC_OBJECT_BASE 0x442BADCull
+#define DCORE2_TPC2_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE2_TPC2_CFG_QM_BASE 0x442BAE4ull
+#define DCORE2_TPC2_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE2_TPC2_CFG_QM_SECTION 0x31C0
+#define mmDCORE2_TPC2_CFG_AXUSER_BASE 0x442BE00ull
+#define DCORE2_TPC2_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE2_TPC2_CFG_SPECIAL_BASE 0x442BE80ull
+#define DCORE2_TPC2_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC2_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE2_TPC2_MSTR_IF_RR_SHRD_HBW_BASE 0x442C000ull
+#define DCORE2_TPC2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_TPC2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE2_TPC2_MSTR_IF_RR_PRVT_HBW_BASE 0x442C200ull
+#define DCORE2_TPC2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_TPC2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE2_TPC2_MSTR_IF_RR_SHRD_LBW_BASE 0x442C400ull
+#define DCORE2_TPC2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_TPC2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE2_TPC2_MSTR_IF_RR_PRVT_LBW_BASE 0x442C600ull
+#define DCORE2_TPC2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_TPC2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE2_TPC2_MSTR_IF_E2E_CRDT_BASE 0x442C800ull
+#define DCORE2_TPC2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_TPC2_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE2_TPC2_MSTR_IF_AXUSER_BASE 0x442CA80ull
+#define DCORE2_TPC2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_TPC2_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE2_TPC2_MSTR_IF_DBG_HBW_BASE 0x442CB00ull
+#define DCORE2_TPC2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC2_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_TPC2_MSTR_IF_DBG_LBW_BASE 0x442CB80ull
+#define DCORE2_TPC2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC2_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE2_TPC2_MSTR_IF_CORE_HBW_BASE 0x442CC00ull
+#define DCORE2_TPC2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_TPC2_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE2_TPC2_MSTR_IF_CORE_LBW_BASE 0x442CD80ull
+#define DCORE2_TPC2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_TPC2_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE2_TPC2_MSTR_IF_SPECIAL_BASE 0x442CE80ull
+#define DCORE2_TPC2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC2_MSTR_IF_SPECIAL_SECTION 0x3180
+#define mmDCORE2_TPC3_QM_DCCM_BASE 0x4430000ull
+#define DCORE2_TPC3_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE2_TPC3_QM_DCCM_SECTION 0x8000
+#define mmDCORE2_TPC3_QM_ARC_AUX_BASE 0x4438000ull
+#define DCORE2_TPC3_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE2_TPC3_QM_ARC_AUX_SECTION 0xE800
+#define mmDCORE2_TPC3_QM_ARC_AUX_SPECIAL_BASE 0x4438E80ull
+#define DCORE2_TPC3_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC3_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define mmDCORE2_TPC3_QM_BASE 0x443A000ull
+#define DCORE2_TPC3_QM_MAX_OFFSET 0x1000
+#define DCORE2_TPC3_QM_SECTION 0x9000
+#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR0_BASE 0x443A900ull
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR1_BASE 0x443A908ull
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR2_BASE 0x443A910ull
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR3_BASE 0x443A918ull
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR4_BASE 0x443A920ull
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR5_BASE 0x443A928ull
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR6_BASE 0x443A930ull
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR7_BASE 0x443A938ull
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR8_BASE 0x443A940ull
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR9_BASE 0x443A948ull
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR10_BASE 0x443A950ull
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR11_BASE 0x443A958ull
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR12_BASE 0x443A960ull
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR13_BASE 0x443A968ull
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR14_BASE 0x443A970ull
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR15_BASE 0x443A978ull
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE2_TPC3_QM_AXUSER_SECURED_BASE 0x443AB00ull
+#define DCORE2_TPC3_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE2_TPC3_QM_AXUSER_NONSECURED_BASE 0x443AB80ull
+#define DCORE2_TPC3_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE2_TPC3_QM_DBG_HBW_BASE 0x443AC00ull
+#define DCORE2_TPC3_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC3_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_TPC3_QM_DBG_LBW_BASE 0x443AC80ull
+#define DCORE2_TPC3_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC3_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE2_TPC3_QM_CGM_BASE 0x443AD80ull
+#define DCORE2_TPC3_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE2_TPC3_QM_CGM_SECTION 0x1000
+#define mmDCORE2_TPC3_QM_SPECIAL_BASE 0x443AE80ull
+#define DCORE2_TPC3_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC3_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_0_BASE 0x443B000ull
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE2_TPC3_CFG_BASE 0x443B000ull
+#define DCORE2_TPC3_CFG_MAX_OFFSET 0x1000
+#define DCORE2_TPC3_CFG_SECTION 0x5000
+#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_1_BASE 0x443B050ull
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_2_BASE 0x443B0A0ull
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_3_BASE 0x443B0F0ull
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_4_BASE 0x443B140ull
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_5_BASE 0x443B190ull
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_6_BASE 0x443B1E0ull
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_7_BASE 0x443B230ull
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_8_BASE 0x443B280ull
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_9_BASE 0x443B2D0ull
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_10_BASE 0x443B320ull
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_11_BASE 0x443B370ull
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_12_BASE 0x443B3C0ull
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_13_BASE 0x443B410ull
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_14_BASE 0x443B460ull
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_15_BASE 0x443B4B0ull
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE2_TPC3_CFG_KERNEL_SYNC_OBJECT_BASE 0x443B500ull
+#define DCORE2_TPC3_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE2_TPC3_CFG_KERNEL_BASE 0x443B508ull
+#define DCORE2_TPC3_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE2_TPC3_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE2_TPC3_CFG_QM_TENSOR_0_BASE 0x443B5DCull
+#define DCORE2_TPC3_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE2_TPC3_CFG_QM_TENSOR_1_BASE 0x443B62Cull
+#define DCORE2_TPC3_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE2_TPC3_CFG_QM_TENSOR_2_BASE 0x443B67Cull
+#define DCORE2_TPC3_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE2_TPC3_CFG_QM_TENSOR_3_BASE 0x443B6CCull
+#define DCORE2_TPC3_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE2_TPC3_CFG_QM_TENSOR_4_BASE 0x443B71Cull
+#define DCORE2_TPC3_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE2_TPC3_CFG_QM_TENSOR_5_BASE 0x443B76Cull
+#define DCORE2_TPC3_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE2_TPC3_CFG_QM_TENSOR_6_BASE 0x443B7BCull
+#define DCORE2_TPC3_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE2_TPC3_CFG_QM_TENSOR_7_BASE 0x443B80Cull
+#define DCORE2_TPC3_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE2_TPC3_CFG_QM_TENSOR_8_BASE 0x443B85Cull
+#define DCORE2_TPC3_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE2_TPC3_CFG_QM_TENSOR_9_BASE 0x443B8ACull
+#define DCORE2_TPC3_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE2_TPC3_CFG_QM_TENSOR_10_BASE 0x443B8FCull
+#define DCORE2_TPC3_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE2_TPC3_CFG_QM_TENSOR_11_BASE 0x443B94Cull
+#define DCORE2_TPC3_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE2_TPC3_CFG_QM_TENSOR_12_BASE 0x443B99Cull
+#define DCORE2_TPC3_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE2_TPC3_CFG_QM_TENSOR_13_BASE 0x443B9ECull
+#define DCORE2_TPC3_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE2_TPC3_CFG_QM_TENSOR_14_BASE 0x443BA3Cull
+#define DCORE2_TPC3_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE2_TPC3_CFG_QM_TENSOR_15_BASE 0x443BA8Cull
+#define DCORE2_TPC3_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE2_TPC3_CFG_QM_SYNC_OBJECT_BASE 0x443BADCull
+#define DCORE2_TPC3_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE2_TPC3_CFG_QM_BASE 0x443BAE4ull
+#define DCORE2_TPC3_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE2_TPC3_CFG_QM_SECTION 0x31C0
+#define mmDCORE2_TPC3_CFG_AXUSER_BASE 0x443BE00ull
+#define DCORE2_TPC3_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE2_TPC3_CFG_SPECIAL_BASE 0x443BE80ull
+#define DCORE2_TPC3_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC3_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE2_TPC3_MSTR_IF_RR_SHRD_HBW_BASE 0x443C000ull
+#define DCORE2_TPC3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_TPC3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE2_TPC3_MSTR_IF_RR_PRVT_HBW_BASE 0x443C200ull
+#define DCORE2_TPC3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_TPC3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE2_TPC3_MSTR_IF_RR_SHRD_LBW_BASE 0x443C400ull
+#define DCORE2_TPC3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_TPC3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE2_TPC3_MSTR_IF_RR_PRVT_LBW_BASE 0x443C600ull
+#define DCORE2_TPC3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_TPC3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE2_TPC3_MSTR_IF_E2E_CRDT_BASE 0x443C800ull
+#define DCORE2_TPC3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_TPC3_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE2_TPC3_MSTR_IF_AXUSER_BASE 0x443CA80ull
+#define DCORE2_TPC3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_TPC3_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE2_TPC3_MSTR_IF_DBG_HBW_BASE 0x443CB00ull
+#define DCORE2_TPC3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC3_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_TPC3_MSTR_IF_DBG_LBW_BASE 0x443CB80ull
+#define DCORE2_TPC3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC3_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE2_TPC3_MSTR_IF_CORE_HBW_BASE 0x443CC00ull
+#define DCORE2_TPC3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_TPC3_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE2_TPC3_MSTR_IF_CORE_LBW_BASE 0x443CD80ull
+#define DCORE2_TPC3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_TPC3_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE2_TPC3_MSTR_IF_SPECIAL_BASE 0x443CE80ull
+#define DCORE2_TPC3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC3_MSTR_IF_SPECIAL_SECTION 0x3180
+#define mmDCORE2_TPC4_QM_DCCM_BASE 0x4440000ull
+#define DCORE2_TPC4_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE2_TPC4_QM_DCCM_SECTION 0x8000
+#define mmDCORE2_TPC4_QM_ARC_AUX_BASE 0x4448000ull
+#define DCORE2_TPC4_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE2_TPC4_QM_ARC_AUX_SECTION 0xE800
+#define mmDCORE2_TPC4_QM_ARC_AUX_SPECIAL_BASE 0x4448E80ull
+#define DCORE2_TPC4_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC4_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define mmDCORE2_TPC4_QM_BASE 0x444A000ull
+#define DCORE2_TPC4_QM_MAX_OFFSET 0x1000
+#define DCORE2_TPC4_QM_SECTION 0x9000
+#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR0_BASE 0x444A900ull
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR1_BASE 0x444A908ull
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR2_BASE 0x444A910ull
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR3_BASE 0x444A918ull
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR4_BASE 0x444A920ull
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR5_BASE 0x444A928ull
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR6_BASE 0x444A930ull
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR7_BASE 0x444A938ull
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR8_BASE 0x444A940ull
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR9_BASE 0x444A948ull
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR10_BASE 0x444A950ull
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR11_BASE 0x444A958ull
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR12_BASE 0x444A960ull
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR13_BASE 0x444A968ull
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR14_BASE 0x444A970ull
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR15_BASE 0x444A978ull
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE2_TPC4_QM_AXUSER_SECURED_BASE 0x444AB00ull
+#define DCORE2_TPC4_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE2_TPC4_QM_AXUSER_NONSECURED_BASE 0x444AB80ull
+#define DCORE2_TPC4_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE2_TPC4_QM_DBG_HBW_BASE 0x444AC00ull
+#define DCORE2_TPC4_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC4_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_TPC4_QM_DBG_LBW_BASE 0x444AC80ull
+#define DCORE2_TPC4_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC4_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE2_TPC4_QM_CGM_BASE 0x444AD80ull
+#define DCORE2_TPC4_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE2_TPC4_QM_CGM_SECTION 0x1000
+#define mmDCORE2_TPC4_QM_SPECIAL_BASE 0x444AE80ull
+#define DCORE2_TPC4_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC4_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_0_BASE 0x444B000ull
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE2_TPC4_CFG_BASE 0x444B000ull
+#define DCORE2_TPC4_CFG_MAX_OFFSET 0x1000
+#define DCORE2_TPC4_CFG_SECTION 0x5000
+#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_1_BASE 0x444B050ull
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_2_BASE 0x444B0A0ull
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_3_BASE 0x444B0F0ull
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_4_BASE 0x444B140ull
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_5_BASE 0x444B190ull
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_6_BASE 0x444B1E0ull
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_7_BASE 0x444B230ull
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_8_BASE 0x444B280ull
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_9_BASE 0x444B2D0ull
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_10_BASE 0x444B320ull
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_11_BASE 0x444B370ull
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_12_BASE 0x444B3C0ull
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_13_BASE 0x444B410ull
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_14_BASE 0x444B460ull
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_15_BASE 0x444B4B0ull
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE2_TPC4_CFG_KERNEL_SYNC_OBJECT_BASE 0x444B500ull
+#define DCORE2_TPC4_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE2_TPC4_CFG_KERNEL_BASE 0x444B508ull
+#define DCORE2_TPC4_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE2_TPC4_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE2_TPC4_CFG_QM_TENSOR_0_BASE 0x444B5DCull
+#define DCORE2_TPC4_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE2_TPC4_CFG_QM_TENSOR_1_BASE 0x444B62Cull
+#define DCORE2_TPC4_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE2_TPC4_CFG_QM_TENSOR_2_BASE 0x444B67Cull
+#define DCORE2_TPC4_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE2_TPC4_CFG_QM_TENSOR_3_BASE 0x444B6CCull
+#define DCORE2_TPC4_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE2_TPC4_CFG_QM_TENSOR_4_BASE 0x444B71Cull
+#define DCORE2_TPC4_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE2_TPC4_CFG_QM_TENSOR_5_BASE 0x444B76Cull
+#define DCORE2_TPC4_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE2_TPC4_CFG_QM_TENSOR_6_BASE 0x444B7BCull
+#define DCORE2_TPC4_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE2_TPC4_CFG_QM_TENSOR_7_BASE 0x444B80Cull
+#define DCORE2_TPC4_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE2_TPC4_CFG_QM_TENSOR_8_BASE 0x444B85Cull
+#define DCORE2_TPC4_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE2_TPC4_CFG_QM_TENSOR_9_BASE 0x444B8ACull
+#define DCORE2_TPC4_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE2_TPC4_CFG_QM_TENSOR_10_BASE 0x444B8FCull
+#define DCORE2_TPC4_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE2_TPC4_CFG_QM_TENSOR_11_BASE 0x444B94Cull
+#define DCORE2_TPC4_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE2_TPC4_CFG_QM_TENSOR_12_BASE 0x444B99Cull
+#define DCORE2_TPC4_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE2_TPC4_CFG_QM_TENSOR_13_BASE 0x444B9ECull
+#define DCORE2_TPC4_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE2_TPC4_CFG_QM_TENSOR_14_BASE 0x444BA3Cull
+#define DCORE2_TPC4_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE2_TPC4_CFG_QM_TENSOR_15_BASE 0x444BA8Cull
+#define DCORE2_TPC4_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE2_TPC4_CFG_QM_SYNC_OBJECT_BASE 0x444BADCull
+#define DCORE2_TPC4_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE2_TPC4_CFG_QM_BASE 0x444BAE4ull
+#define DCORE2_TPC4_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE2_TPC4_CFG_QM_SECTION 0x31C0
+#define mmDCORE2_TPC4_CFG_AXUSER_BASE 0x444BE00ull
+#define DCORE2_TPC4_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE2_TPC4_CFG_SPECIAL_BASE 0x444BE80ull
+#define DCORE2_TPC4_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC4_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE2_TPC4_MSTR_IF_RR_SHRD_HBW_BASE 0x444C000ull
+#define DCORE2_TPC4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_TPC4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE2_TPC4_MSTR_IF_RR_PRVT_HBW_BASE 0x444C200ull
+#define DCORE2_TPC4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_TPC4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE2_TPC4_MSTR_IF_RR_SHRD_LBW_BASE 0x444C400ull
+#define DCORE2_TPC4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_TPC4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE2_TPC4_MSTR_IF_RR_PRVT_LBW_BASE 0x444C600ull
+#define DCORE2_TPC4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_TPC4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE2_TPC4_MSTR_IF_E2E_CRDT_BASE 0x444C800ull
+#define DCORE2_TPC4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_TPC4_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE2_TPC4_MSTR_IF_AXUSER_BASE 0x444CA80ull
+#define DCORE2_TPC4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_TPC4_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE2_TPC4_MSTR_IF_DBG_HBW_BASE 0x444CB00ull
+#define DCORE2_TPC4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC4_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_TPC4_MSTR_IF_DBG_LBW_BASE 0x444CB80ull
+#define DCORE2_TPC4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC4_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE2_TPC4_MSTR_IF_CORE_HBW_BASE 0x444CC00ull
+#define DCORE2_TPC4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_TPC4_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE2_TPC4_MSTR_IF_CORE_LBW_BASE 0x444CD80ull
+#define DCORE2_TPC4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_TPC4_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE2_TPC4_MSTR_IF_SPECIAL_BASE 0x444CE80ull
+#define DCORE2_TPC4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC4_MSTR_IF_SPECIAL_SECTION 0x3180
+#define mmDCORE2_TPC5_QM_DCCM_BASE 0x4450000ull
+#define DCORE2_TPC5_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE2_TPC5_QM_DCCM_SECTION 0x8000
+#define mmDCORE2_TPC5_QM_ARC_AUX_BASE 0x4458000ull
+#define DCORE2_TPC5_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE2_TPC5_QM_ARC_AUX_SECTION 0xE800
+#define mmDCORE2_TPC5_QM_ARC_AUX_SPECIAL_BASE 0x4458E80ull
+#define DCORE2_TPC5_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC5_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define mmDCORE2_TPC5_QM_BASE 0x445A000ull
+#define DCORE2_TPC5_QM_MAX_OFFSET 0x1000
+#define DCORE2_TPC5_QM_SECTION 0x9000
+#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR0_BASE 0x445A900ull
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR1_BASE 0x445A908ull
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR2_BASE 0x445A910ull
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR3_BASE 0x445A918ull
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR4_BASE 0x445A920ull
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR5_BASE 0x445A928ull
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR6_BASE 0x445A930ull
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR7_BASE 0x445A938ull
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR8_BASE 0x445A940ull
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR9_BASE 0x445A948ull
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR10_BASE 0x445A950ull
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR11_BASE 0x445A958ull
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR12_BASE 0x445A960ull
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR13_BASE 0x445A968ull
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR14_BASE 0x445A970ull
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR15_BASE 0x445A978ull
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE2_TPC5_QM_AXUSER_SECURED_BASE 0x445AB00ull
+#define DCORE2_TPC5_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE2_TPC5_QM_AXUSER_NONSECURED_BASE 0x445AB80ull
+#define DCORE2_TPC5_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE2_TPC5_QM_DBG_HBW_BASE 0x445AC00ull
+#define DCORE2_TPC5_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC5_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_TPC5_QM_DBG_LBW_BASE 0x445AC80ull
+#define DCORE2_TPC5_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC5_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE2_TPC5_QM_CGM_BASE 0x445AD80ull
+#define DCORE2_TPC5_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE2_TPC5_QM_CGM_SECTION 0x1000
+#define mmDCORE2_TPC5_QM_SPECIAL_BASE 0x445AE80ull
+#define DCORE2_TPC5_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC5_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_0_BASE 0x445B000ull
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE2_TPC5_CFG_BASE 0x445B000ull
+#define DCORE2_TPC5_CFG_MAX_OFFSET 0x1000
+#define DCORE2_TPC5_CFG_SECTION 0x5000
+#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_1_BASE 0x445B050ull
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_2_BASE 0x445B0A0ull
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_3_BASE 0x445B0F0ull
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_4_BASE 0x445B140ull
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_5_BASE 0x445B190ull
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_6_BASE 0x445B1E0ull
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_7_BASE 0x445B230ull
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_8_BASE 0x445B280ull
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_9_BASE 0x445B2D0ull
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_10_BASE 0x445B320ull
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_11_BASE 0x445B370ull
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_12_BASE 0x445B3C0ull
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_13_BASE 0x445B410ull
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_14_BASE 0x445B460ull
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_15_BASE 0x445B4B0ull
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE2_TPC5_CFG_KERNEL_SYNC_OBJECT_BASE 0x445B500ull
+#define DCORE2_TPC5_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE2_TPC5_CFG_KERNEL_BASE 0x445B508ull
+#define DCORE2_TPC5_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE2_TPC5_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE2_TPC5_CFG_QM_TENSOR_0_BASE 0x445B5DCull
+#define DCORE2_TPC5_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE2_TPC5_CFG_QM_TENSOR_1_BASE 0x445B62Cull
+#define DCORE2_TPC5_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE2_TPC5_CFG_QM_TENSOR_2_BASE 0x445B67Cull
+#define DCORE2_TPC5_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE2_TPC5_CFG_QM_TENSOR_3_BASE 0x445B6CCull
+#define DCORE2_TPC5_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE2_TPC5_CFG_QM_TENSOR_4_BASE 0x445B71Cull
+#define DCORE2_TPC5_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE2_TPC5_CFG_QM_TENSOR_5_BASE 0x445B76Cull
+#define DCORE2_TPC5_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE2_TPC5_CFG_QM_TENSOR_6_BASE 0x445B7BCull
+#define DCORE2_TPC5_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE2_TPC5_CFG_QM_TENSOR_7_BASE 0x445B80Cull
+#define DCORE2_TPC5_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE2_TPC5_CFG_QM_TENSOR_8_BASE 0x445B85Cull
+#define DCORE2_TPC5_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE2_TPC5_CFG_QM_TENSOR_9_BASE 0x445B8ACull
+#define DCORE2_TPC5_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE2_TPC5_CFG_QM_TENSOR_10_BASE 0x445B8FCull
+#define DCORE2_TPC5_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE2_TPC5_CFG_QM_TENSOR_11_BASE 0x445B94Cull
+#define DCORE2_TPC5_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE2_TPC5_CFG_QM_TENSOR_12_BASE 0x445B99Cull
+#define DCORE2_TPC5_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE2_TPC5_CFG_QM_TENSOR_13_BASE 0x445B9ECull
+#define DCORE2_TPC5_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE2_TPC5_CFG_QM_TENSOR_14_BASE 0x445BA3Cull
+#define DCORE2_TPC5_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE2_TPC5_CFG_QM_TENSOR_15_BASE 0x445BA8Cull
+#define DCORE2_TPC5_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE2_TPC5_CFG_QM_SYNC_OBJECT_BASE 0x445BADCull
+#define DCORE2_TPC5_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE2_TPC5_CFG_QM_BASE 0x445BAE4ull
+#define DCORE2_TPC5_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE2_TPC5_CFG_QM_SECTION 0x31C0
+#define mmDCORE2_TPC5_CFG_AXUSER_BASE 0x445BE00ull
+#define DCORE2_TPC5_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE2_TPC5_CFG_SPECIAL_BASE 0x445BE80ull
+#define DCORE2_TPC5_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC5_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE2_TPC5_MSTR_IF_RR_SHRD_HBW_BASE 0x445C000ull
+#define DCORE2_TPC5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_TPC5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE2_TPC5_MSTR_IF_RR_PRVT_HBW_BASE 0x445C200ull
+#define DCORE2_TPC5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_TPC5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE2_TPC5_MSTR_IF_RR_SHRD_LBW_BASE 0x445C400ull
+#define DCORE2_TPC5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_TPC5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE2_TPC5_MSTR_IF_RR_PRVT_LBW_BASE 0x445C600ull
+#define DCORE2_TPC5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_TPC5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE2_TPC5_MSTR_IF_E2E_CRDT_BASE 0x445C800ull
+#define DCORE2_TPC5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_TPC5_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE2_TPC5_MSTR_IF_AXUSER_BASE 0x445CA80ull
+#define DCORE2_TPC5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_TPC5_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE2_TPC5_MSTR_IF_DBG_HBW_BASE 0x445CB00ull
+#define DCORE2_TPC5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC5_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_TPC5_MSTR_IF_DBG_LBW_BASE 0x445CB80ull
+#define DCORE2_TPC5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_TPC5_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE2_TPC5_MSTR_IF_CORE_HBW_BASE 0x445CC00ull
+#define DCORE2_TPC5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_TPC5_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE2_TPC5_MSTR_IF_CORE_LBW_BASE 0x445CD80ull
+#define DCORE2_TPC5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_TPC5_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE2_TPC5_MSTR_IF_SPECIAL_BASE 0x445CE80ull
+#define DCORE2_TPC5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC5_MSTR_IF_SPECIAL_SECTION 0x23180
+#define mmDCORE2_HMMU0_MMU_BASE 0x4480000ull
+#define DCORE2_HMMU0_MMU_MAX_OFFSET 0x1000
+#define DCORE2_HMMU0_MMU_SECTION 0xE800
+#define mmDCORE2_HMMU0_MMU_SPECIAL_BASE 0x4480E80ull
+#define DCORE2_HMMU0_MMU_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HMMU0_MMU_SPECIAL_SECTION 0x1800
+#define mmDCORE2_HMMU0_STLB_BASE 0x4481000ull
+#define DCORE2_HMMU0_STLB_MAX_OFFSET 0x1000
+#define DCORE2_HMMU0_STLB_SECTION 0xE800
+#define mmDCORE2_HMMU0_STLB_SPECIAL_BASE 0x4481E80ull
+#define DCORE2_HMMU0_STLB_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HMMU0_STLB_SPECIAL_SECTION 0x1180
+#define mmDCORE2_HMMU0_SCRAMB_OUT_BASE 0x4483000ull
+#define DCORE2_HMMU0_SCRAMB_OUT_MAX_OFFSET 0x1000
+#define DCORE2_HMMU0_SCRAMB_OUT_SECTION 0xE800
+#define mmDCORE2_HMMU0_SCRAMB_OUT_SPECIAL_BASE 0x4483E80ull
+#define DCORE2_HMMU0_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HMMU0_SCRAMB_OUT_SPECIAL_SECTION 0x1800
+#define mmDCORE2_HMMU0_MSTR_IF_RR_SHRD_HBW_BASE 0x4484000ull
+#define DCORE2_HMMU0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_HMMU0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE2_HMMU0_MSTR_IF_RR_PRVT_HBW_BASE 0x4484200ull
+#define DCORE2_HMMU0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_HMMU0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE2_HMMU0_MSTR_IF_RR_SHRD_LBW_BASE 0x4484400ull
+#define DCORE2_HMMU0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_HMMU0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE2_HMMU0_MSTR_IF_RR_PRVT_LBW_BASE 0x4484600ull
+#define DCORE2_HMMU0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_HMMU0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE2_HMMU0_MSTR_IF_E2E_CRDT_BASE 0x4484800ull
+#define DCORE2_HMMU0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_HMMU0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE2_HMMU0_MSTR_IF_AXUSER_BASE 0x4484A80ull
+#define DCORE2_HMMU0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_HMMU0_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE2_HMMU0_MSTR_IF_DBG_HBW_BASE 0x4484B00ull
+#define DCORE2_HMMU0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_HMMU0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_HMMU0_MSTR_IF_DBG_LBW_BASE 0x4484B80ull
+#define DCORE2_HMMU0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_HMMU0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE2_HMMU0_MSTR_IF_CORE_HBW_BASE 0x4484C00ull
+#define DCORE2_HMMU0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_HMMU0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE2_HMMU0_MSTR_IF_CORE_LBW_BASE 0x4484D80ull
+#define DCORE2_HMMU0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_HMMU0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE2_HMMU0_MSTR_IF_SPECIAL_BASE 0x4484E80ull
+#define DCORE2_HMMU0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HMMU0_MSTR_IF_SPECIAL_SECTION 0xB180
+#define mmDCORE2_HMMU1_MMU_BASE 0x4490000ull
+#define DCORE2_HMMU1_MMU_MAX_OFFSET 0x1000
+#define DCORE2_HMMU1_MMU_SECTION 0xE800
+#define mmDCORE2_HMMU1_MMU_SPECIAL_BASE 0x4490E80ull
+#define DCORE2_HMMU1_MMU_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HMMU1_MMU_SPECIAL_SECTION 0x1800
+#define mmDCORE2_HMMU1_STLB_BASE 0x4491000ull
+#define DCORE2_HMMU1_STLB_MAX_OFFSET 0x1000
+#define DCORE2_HMMU1_STLB_SECTION 0xE800
+#define mmDCORE2_HMMU1_STLB_SPECIAL_BASE 0x4491E80ull
+#define DCORE2_HMMU1_STLB_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HMMU1_STLB_SPECIAL_SECTION 0x1180
+#define mmDCORE2_HMMU1_SCRAMB_OUT_BASE 0x4493000ull
+#define DCORE2_HMMU1_SCRAMB_OUT_MAX_OFFSET 0x1000
+#define DCORE2_HMMU1_SCRAMB_OUT_SECTION 0xE800
+#define mmDCORE2_HMMU1_SCRAMB_OUT_SPECIAL_BASE 0x4493E80ull
+#define DCORE2_HMMU1_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HMMU1_SCRAMB_OUT_SPECIAL_SECTION 0x1800
+#define mmDCORE2_HMMU1_MSTR_IF_RR_SHRD_HBW_BASE 0x4494000ull
+#define DCORE2_HMMU1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_HMMU1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE2_HMMU1_MSTR_IF_RR_PRVT_HBW_BASE 0x4494200ull
+#define DCORE2_HMMU1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_HMMU1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE2_HMMU1_MSTR_IF_RR_SHRD_LBW_BASE 0x4494400ull
+#define DCORE2_HMMU1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_HMMU1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE2_HMMU1_MSTR_IF_RR_PRVT_LBW_BASE 0x4494600ull
+#define DCORE2_HMMU1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_HMMU1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE2_HMMU1_MSTR_IF_E2E_CRDT_BASE 0x4494800ull
+#define DCORE2_HMMU1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_HMMU1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE2_HMMU1_MSTR_IF_AXUSER_BASE 0x4494A80ull
+#define DCORE2_HMMU1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_HMMU1_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE2_HMMU1_MSTR_IF_DBG_HBW_BASE 0x4494B00ull
+#define DCORE2_HMMU1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_HMMU1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_HMMU1_MSTR_IF_DBG_LBW_BASE 0x4494B80ull
+#define DCORE2_HMMU1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_HMMU1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE2_HMMU1_MSTR_IF_CORE_HBW_BASE 0x4494C00ull
+#define DCORE2_HMMU1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_HMMU1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE2_HMMU1_MSTR_IF_CORE_LBW_BASE 0x4494D80ull
+#define DCORE2_HMMU1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_HMMU1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE2_HMMU1_MSTR_IF_SPECIAL_BASE 0x4494E80ull
+#define DCORE2_HMMU1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HMMU1_MSTR_IF_SPECIAL_SECTION 0xB180
+#define mmDCORE2_HMMU2_MMU_BASE 0x44A0000ull
+#define DCORE2_HMMU2_MMU_MAX_OFFSET 0x1000
+#define DCORE2_HMMU2_MMU_SECTION 0xE800
+#define mmDCORE2_HMMU2_MMU_SPECIAL_BASE 0x44A0E80ull
+#define DCORE2_HMMU2_MMU_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HMMU2_MMU_SPECIAL_SECTION 0x1800
+#define mmDCORE2_HMMU2_STLB_BASE 0x44A1000ull
+#define DCORE2_HMMU2_STLB_MAX_OFFSET 0x1000
+#define DCORE2_HMMU2_STLB_SECTION 0xE800
+#define mmDCORE2_HMMU2_STLB_SPECIAL_BASE 0x44A1E80ull
+#define DCORE2_HMMU2_STLB_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HMMU2_STLB_SPECIAL_SECTION 0x1180
+#define mmDCORE2_HMMU2_SCRAMB_OUT_BASE 0x44A3000ull
+#define DCORE2_HMMU2_SCRAMB_OUT_MAX_OFFSET 0x1000
+#define DCORE2_HMMU2_SCRAMB_OUT_SECTION 0xE800
+#define mmDCORE2_HMMU2_SCRAMB_OUT_SPECIAL_BASE 0x44A3E80ull
+#define DCORE2_HMMU2_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HMMU2_SCRAMB_OUT_SPECIAL_SECTION 0x1800
+#define mmDCORE2_HMMU2_MSTR_IF_RR_SHRD_HBW_BASE 0x44A4000ull
+#define DCORE2_HMMU2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_HMMU2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE2_HMMU2_MSTR_IF_RR_PRVT_HBW_BASE 0x44A4200ull
+#define DCORE2_HMMU2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_HMMU2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE2_HMMU2_MSTR_IF_RR_SHRD_LBW_BASE 0x44A4400ull
+#define DCORE2_HMMU2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_HMMU2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE2_HMMU2_MSTR_IF_RR_PRVT_LBW_BASE 0x44A4600ull
+#define DCORE2_HMMU2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_HMMU2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE2_HMMU2_MSTR_IF_E2E_CRDT_BASE 0x44A4800ull
+#define DCORE2_HMMU2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_HMMU2_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE2_HMMU2_MSTR_IF_AXUSER_BASE 0x44A4A80ull
+#define DCORE2_HMMU2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_HMMU2_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE2_HMMU2_MSTR_IF_DBG_HBW_BASE 0x44A4B00ull
+#define DCORE2_HMMU2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_HMMU2_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_HMMU2_MSTR_IF_DBG_LBW_BASE 0x44A4B80ull
+#define DCORE2_HMMU2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_HMMU2_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE2_HMMU2_MSTR_IF_CORE_HBW_BASE 0x44A4C00ull
+#define DCORE2_HMMU2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_HMMU2_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE2_HMMU2_MSTR_IF_CORE_LBW_BASE 0x44A4D80ull
+#define DCORE2_HMMU2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_HMMU2_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE2_HMMU2_MSTR_IF_SPECIAL_BASE 0x44A4E80ull
+#define DCORE2_HMMU2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HMMU2_MSTR_IF_SPECIAL_SECTION 0xB180
+#define mmDCORE2_HMMU3_MMU_BASE 0x44B0000ull
+#define DCORE2_HMMU3_MMU_MAX_OFFSET 0x1000
+#define DCORE2_HMMU3_MMU_SECTION 0xE800
+#define mmDCORE2_HMMU3_MMU_SPECIAL_BASE 0x44B0E80ull
+#define DCORE2_HMMU3_MMU_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HMMU3_MMU_SPECIAL_SECTION 0x1800
+#define mmDCORE2_HMMU3_STLB_BASE 0x44B1000ull
+#define DCORE2_HMMU3_STLB_MAX_OFFSET 0x1000
+#define DCORE2_HMMU3_STLB_SECTION 0xE800
+#define mmDCORE2_HMMU3_STLB_SPECIAL_BASE 0x44B1E80ull
+#define DCORE2_HMMU3_STLB_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HMMU3_STLB_SPECIAL_SECTION 0x1180
+#define mmDCORE2_HMMU3_SCRAMB_OUT_BASE 0x44B3000ull
+#define DCORE2_HMMU3_SCRAMB_OUT_MAX_OFFSET 0x1000
+#define DCORE2_HMMU3_SCRAMB_OUT_SECTION 0xE800
+#define mmDCORE2_HMMU3_SCRAMB_OUT_SPECIAL_BASE 0x44B3E80ull
+#define DCORE2_HMMU3_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HMMU3_SCRAMB_OUT_SPECIAL_SECTION 0x1800
+#define mmDCORE2_HMMU3_MSTR_IF_RR_SHRD_HBW_BASE 0x44B4000ull
+#define DCORE2_HMMU3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_HMMU3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE2_HMMU3_MSTR_IF_RR_PRVT_HBW_BASE 0x44B4200ull
+#define DCORE2_HMMU3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_HMMU3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE2_HMMU3_MSTR_IF_RR_SHRD_LBW_BASE 0x44B4400ull
+#define DCORE2_HMMU3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_HMMU3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE2_HMMU3_MSTR_IF_RR_PRVT_LBW_BASE 0x44B4600ull
+#define DCORE2_HMMU3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_HMMU3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE2_HMMU3_MSTR_IF_E2E_CRDT_BASE 0x44B4800ull
+#define DCORE2_HMMU3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_HMMU3_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE2_HMMU3_MSTR_IF_AXUSER_BASE 0x44B4A80ull
+#define DCORE2_HMMU3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_HMMU3_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE2_HMMU3_MSTR_IF_DBG_HBW_BASE 0x44B4B00ull
+#define DCORE2_HMMU3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_HMMU3_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_HMMU3_MSTR_IF_DBG_LBW_BASE 0x44B4B80ull
+#define DCORE2_HMMU3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_HMMU3_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE2_HMMU3_MSTR_IF_CORE_HBW_BASE 0x44B4C00ull
+#define DCORE2_HMMU3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_HMMU3_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE2_HMMU3_MSTR_IF_CORE_LBW_BASE 0x44B4D80ull
+#define DCORE2_HMMU3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_HMMU3_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE2_HMMU3_MSTR_IF_SPECIAL_BASE 0x44B4E80ull
+#define DCORE2_HMMU3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HMMU3_MSTR_IF_SPECIAL_SECTION 0xB180
+#define mmDCORE2_MME_QM_ARC_DCCM_BASE 0x44C0000ull
+#define DCORE2_MME_QM_ARC_DCCM_MAX_OFFSET 0x4000
+#define DCORE2_MME_QM_ARC_DCCM_SECTION 0x8000
+#define mmDCORE2_MME_QM_ARC_AUX_BASE 0x44C8000ull
+#define DCORE2_MME_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE2_MME_QM_ARC_AUX_SECTION 0xE800
+#define mmDCORE2_MME_QM_ARC_AUX_SPECIAL_BASE 0x44C8E80ull
+#define DCORE2_MME_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_QM_ARC_AUX_SPECIAL_SECTION 0x1800
+#define mmDCORE2_MME_QM_ARC_DUP_ENG_BASE 0x44C9000ull
+#define DCORE2_MME_QM_ARC_DUP_ENG_MAX_OFFSET 0x1000
+#define DCORE2_MME_QM_ARC_DUP_ENG_SECTION 0x9000
+#define mmDCORE2_MME_QM_ARC_DUP_ENG_AXUSER_BASE 0x44C9900ull
+#define DCORE2_MME_QM_ARC_DUP_ENG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_MME_QM_ARC_DUP_ENG_AXUSER_SECTION 0x5800
+#define mmDCORE2_MME_QM_ARC_DUP_ENG_SPECIAL_BASE 0x44C9E80ull
+#define DCORE2_MME_QM_ARC_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_QM_ARC_DUP_ENG_SPECIAL_SECTION 0x1800
+#define mmDCORE2_MME_QM_BASE 0x44CA000ull
+#define DCORE2_MME_QM_MAX_OFFSET 0x1000
+#define DCORE2_MME_QM_SECTION 0x9000
+#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR0_BASE 0x44CA900ull
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR1_BASE 0x44CA908ull
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR2_BASE 0x44CA910ull
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR3_BASE 0x44CA918ull
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR4_BASE 0x44CA920ull
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR5_BASE 0x44CA928ull
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR6_BASE 0x44CA930ull
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR7_BASE 0x44CA938ull
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR8_BASE 0x44CA940ull
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR9_BASE 0x44CA948ull
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR10_BASE 0x44CA950ull
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR11_BASE 0x44CA958ull
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR12_BASE 0x44CA960ull
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR13_BASE 0x44CA968ull
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR14_BASE 0x44CA970ull
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR15_BASE 0x44CA978ull
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE2_MME_QM_AXUSER_SECURED_BASE 0x44CAB00ull
+#define DCORE2_MME_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE2_MME_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE2_MME_QM_AXUSER_NONSECURED_BASE 0x44CAB80ull
+#define DCORE2_MME_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE2_MME_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE2_MME_QM_DBG_HBW_BASE 0x44CAC00ull
+#define DCORE2_MME_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_MME_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_MME_QM_DBG_LBW_BASE 0x44CAC80ull
+#define DCORE2_MME_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_MME_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE2_MME_QM_CGM_BASE 0x44CAD80ull
+#define DCORE2_MME_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE2_MME_QM_CGM_SECTION 0x1000
+#define mmDCORE2_MME_QM_SPECIAL_BASE 0x44CAE80ull
+#define DCORE2_MME_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE2_MME_CTRL_LO_BASE 0x44CB000ull
+#define DCORE2_MME_CTRL_LO_MAX_OFFSET 0x1000
+#define DCORE2_MME_CTRL_LO_SECTION 0x8000
+#define mmDCORE2_MME_CTRL_LO_ARCH_BASE_ADDR_BASE 0x44CB008ull
+#define DCORE2_MME_CTRL_LO_ARCH_BASE_ADDR_MAX_OFFSET 0x2000
+#define DCORE2_MME_CTRL_LO_ARCH_BASE_ADDR_SECTION 0x2000
+#define mmDCORE2_MME_CTRL_LO_ARCH_NON_TENSOR_START_BASE 0x44CB028ull
+#define DCORE2_MME_CTRL_LO_ARCH_NON_TENSOR_START_MAX_OFFSET 0x1800
+#define DCORE2_MME_CTRL_LO_ARCH_NON_TENSOR_START_SECTION 0x1800
+#define mmDCORE2_MME_CTRL_LO_ARCH_TENSOR_A_BASE 0x44CB040ull
+#define DCORE2_MME_CTRL_LO_ARCH_TENSOR_A_MAX_OFFSET 0x5800
+#define DCORE2_MME_CTRL_LO_ARCH_TENSOR_A_SECTION 0x5800
+#define mmDCORE2_MME_CTRL_LO_ARCH_TENSOR_B_BASE 0x44CB098ull
+#define DCORE2_MME_CTRL_LO_ARCH_TENSOR_B_MAX_OFFSET 0x5800
+#define DCORE2_MME_CTRL_LO_ARCH_TENSOR_B_SECTION 0x5800
+#define mmDCORE2_MME_CTRL_LO_ARCH_TENSOR_COUT_BASE 0x44CB0F0ull
+#define DCORE2_MME_CTRL_LO_ARCH_TENSOR_COUT_MAX_OFFSET 0x5800
+#define DCORE2_MME_CTRL_LO_ARCH_TENSOR_COUT_SECTION 0x6C00
+#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_BASE 0x44CB15Cull
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_BASE 0x44CB170ull
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_BASE 0x44CB184ull
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_BASE 0x44CB198ull
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_BASE 0x44CB1ACull
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_BASE 0x44CB1C0ull
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_BASE 0x44CB1D4ull
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_BASE 0x44CB1E8ull
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_BASE 0x44CB1FCull
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_BASE 0x44CB210ull
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_SECTION 0x1C00
+#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_BASE 0x44CB22Cull
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_BASE 0x44CB240ull
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_BASE 0x44CB254ull
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_BASE 0x44CB268ull
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_SECTION 0x1800
+#define mmDCORE2_MME_CTRL_LO_ARCH_NON_TENSOR_END_BASE 0x44CB280ull
+#define DCORE2_MME_CTRL_LO_ARCH_NON_TENSOR_END_MAX_OFFSET 0x6000
+#define DCORE2_MME_CTRL_LO_ARCH_NON_TENSOR_END_SECTION 0xB800
+#define mmDCORE2_MME_CTRL_LO_MME_AXUSER_BASE 0x44CBE00ull
+#define DCORE2_MME_CTRL_LO_MME_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_MME_CTRL_LO_MME_AXUSER_SECTION 0x8000
+#define mmDCORE2_MME_CTRL_LO_SPECIAL_BASE 0x44CBE80ull
+#define DCORE2_MME_CTRL_LO_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_CTRL_LO_SPECIAL_SECTION 0x1800
+#define mmDCORE2_MME_CTRL_HI_BASE 0x44CC000ull
+#define DCORE2_MME_CTRL_HI_MAX_OFFSET 0x1000
+#define DCORE2_MME_CTRL_HI_SECTION 0x8000
+#define mmDCORE2_MME_CTRL_HI_SHADOW_0_BASE_ADDR_BASE 0x44CC008ull
+#define DCORE2_MME_CTRL_HI_SHADOW_0_BASE_ADDR_MAX_OFFSET 0x2000
+#define DCORE2_MME_CTRL_HI_SHADOW_0_BASE_ADDR_SECTION 0x2000
+#define mmDCORE2_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_BASE 0x44CC028ull
+#define DCORE2_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_MAX_OFFSET 0x1800
+#define DCORE2_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_SECTION 0x1800
+#define mmDCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_A_BASE 0x44CC040ull
+#define DCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_A_MAX_OFFSET 0x5800
+#define DCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_A_SECTION 0x5800
+#define mmDCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_B_BASE 0x44CC098ull
+#define DCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_B_MAX_OFFSET 0x5800
+#define DCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_B_SECTION 0x5800
+#define mmDCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_BASE 0x44CC0F0ull
+#define DCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_MAX_OFFSET 0x5800
+#define DCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_SECTION 0x6C00
+#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_BASE 0x44CC15Cull
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_BASE 0x44CC170ull
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_BASE 0x44CC184ull
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_BASE 0x44CC198ull
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_BASE 0x44CC1ACull
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_BASE 0x44CC1C0ull
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_BASE 0x44CC1D4ull
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_BASE 0x44CC1E8ull
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_BASE 0x44CC1FCull
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_BASE 0x44CC210ull
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_SECTION 0x1C00
+#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_BASE 0x44CC22Cull
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_BASE 0x44CC240ull
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_BASE 0x44CC254ull
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_BASE 0x44CC268ull
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_SECTION 0x1800
+#define mmDCORE2_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_BASE 0x44CC280ull
+#define DCORE2_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_MAX_OFFSET 0x6000
+#define DCORE2_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_SECTION 0x8800
+#define mmDCORE2_MME_CTRL_HI_SHADOW_1_BASE_ADDR_BASE 0x44CC308ull
+#define DCORE2_MME_CTRL_HI_SHADOW_1_BASE_ADDR_MAX_OFFSET 0x2000
+#define DCORE2_MME_CTRL_HI_SHADOW_1_BASE_ADDR_SECTION 0x2000
+#define mmDCORE2_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_BASE 0x44CC328ull
+#define DCORE2_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_MAX_OFFSET 0x1800
+#define DCORE2_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_SECTION 0x1800
+#define mmDCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_A_BASE 0x44CC340ull
+#define DCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_A_MAX_OFFSET 0x5800
+#define DCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_A_SECTION 0x5800
+#define mmDCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_B_BASE 0x44CC398ull
+#define DCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_B_MAX_OFFSET 0x5800
+#define DCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_B_SECTION 0x5800
+#define mmDCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_BASE 0x44CC3F0ull
+#define DCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_MAX_OFFSET 0x5800
+#define DCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_SECTION 0x6C00
+#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_BASE 0x44CC45Cull
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_BASE 0x44CC470ull
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_BASE 0x44CC484ull
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_BASE 0x44CC498ull
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_BASE 0x44CC4ACull
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_BASE 0x44CC4C0ull
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_BASE 0x44CC4D4ull
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_BASE 0x44CC4E8ull
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_BASE 0x44CC4FCull
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_BASE 0x44CC510ull
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_SECTION 0x1C00
+#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_BASE 0x44CC52Cull
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_BASE 0x44CC540ull
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_BASE 0x44CC554ull
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_BASE 0x44CC568ull
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_SECTION 0x1800
+#define mmDCORE2_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_BASE 0x44CC580ull
+#define DCORE2_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_MAX_OFFSET 0x6000
+#define DCORE2_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_SECTION 0x8800
+#define mmDCORE2_MME_CTRL_HI_SHADOW_2_BASE_ADDR_BASE 0x44CC608ull
+#define DCORE2_MME_CTRL_HI_SHADOW_2_BASE_ADDR_MAX_OFFSET 0x2000
+#define DCORE2_MME_CTRL_HI_SHADOW_2_BASE_ADDR_SECTION 0x2000
+#define mmDCORE2_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_BASE 0x44CC628ull
+#define DCORE2_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_MAX_OFFSET 0x1800
+#define DCORE2_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_SECTION 0x1800
+#define mmDCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_A_BASE 0x44CC640ull
+#define DCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_A_MAX_OFFSET 0x5800
+#define DCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_A_SECTION 0x5800
+#define mmDCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_B_BASE 0x44CC698ull
+#define DCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_B_MAX_OFFSET 0x5800
+#define DCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_B_SECTION 0x5800
+#define mmDCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_BASE 0x44CC6F0ull
+#define DCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_MAX_OFFSET 0x5800
+#define DCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_SECTION 0x6C00
+#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_BASE 0x44CC75Cull
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_BASE 0x44CC770ull
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_BASE 0x44CC784ull
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_BASE 0x44CC798ull
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_BASE 0x44CC7ACull
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_BASE 0x44CC7C0ull
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_BASE 0x44CC7D4ull
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_BASE 0x44CC7E8ull
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_BASE 0x44CC7FCull
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_BASE 0x44CC810ull
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_SECTION 0x1C00
+#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_BASE 0x44CC82Cull
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_BASE 0x44CC840ull
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_BASE 0x44CC854ull
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_BASE 0x44CC868ull
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_SECTION 0x1800
+#define mmDCORE2_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_BASE 0x44CC880ull
+#define DCORE2_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_MAX_OFFSET 0x6000
+#define DCORE2_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_SECTION 0x8800
+#define mmDCORE2_MME_CTRL_HI_SHADOW_3_BASE_ADDR_BASE 0x44CC908ull
+#define DCORE2_MME_CTRL_HI_SHADOW_3_BASE_ADDR_MAX_OFFSET 0x2000
+#define DCORE2_MME_CTRL_HI_SHADOW_3_BASE_ADDR_SECTION 0x2000
+#define mmDCORE2_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_BASE 0x44CC928ull
+#define DCORE2_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_MAX_OFFSET 0x1800
+#define DCORE2_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_SECTION 0x1800
+#define mmDCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_A_BASE 0x44CC940ull
+#define DCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_A_MAX_OFFSET 0x5800
+#define DCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_A_SECTION 0x5800
+#define mmDCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_B_BASE 0x44CC998ull
+#define DCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_B_MAX_OFFSET 0x5800
+#define DCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_B_SECTION 0x5800
+#define mmDCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_BASE 0x44CC9F0ull
+#define DCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_MAX_OFFSET 0x5800
+#define DCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_SECTION 0x6C00
+#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_BASE 0x44CCA5Cull
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_BASE 0x44CCA70ull
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_BASE 0x44CCA84ull
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_BASE 0x44CCA98ull
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_BASE 0x44CCAACull
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_BASE 0x44CCAC0ull
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_BASE 0x44CCAD4ull
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_BASE 0x44CCAE8ull
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_BASE 0x44CCAFCull
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_BASE 0x44CCB10ull
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_SECTION 0x1C00
+#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_BASE 0x44CCB2Cull
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_BASE 0x44CCB40ull
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_BASE 0x44CCB54ull
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_SECTION 0x1400
+#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_BASE 0x44CCB68ull
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_SECTION 0x1800
+#define mmDCORE2_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_BASE 0x44CCB80ull
+#define DCORE2_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_MAX_OFFSET 0x6000
+#define DCORE2_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_SECTION 0x3000
+#define mmDCORE2_MME_CTRL_HI_SPECIAL_BASE 0x44CCE80ull
+#define DCORE2_MME_CTRL_HI_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_CTRL_HI_SPECIAL_SECTION 0x1800
+#define mmDCORE2_MME_EU_BIST_BASE 0x44CD000ull
+#define DCORE2_MME_EU_BIST_MAX_OFFSET 0x1000
+#define DCORE2_MME_EU_BIST_SECTION 0xE800
+#define mmDCORE2_MME_EU_BIST_SPECIAL_BASE 0x44CDE80ull
+#define DCORE2_MME_EU_BIST_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_EU_BIST_SPECIAL_SECTION 0x1800
+#define mmDCORE2_MME_CTRL_MSTR_IF_RR_SHRD_HBW_BASE 0x44CE000ull
+#define DCORE2_MME_CTRL_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_MME_CTRL_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE2_MME_CTRL_MSTR_IF_RR_PRVT_HBW_BASE 0x44CE200ull
+#define DCORE2_MME_CTRL_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_MME_CTRL_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE2_MME_CTRL_MSTR_IF_RR_SHRD_LBW_BASE 0x44CE400ull
+#define DCORE2_MME_CTRL_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_MME_CTRL_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE2_MME_CTRL_MSTR_IF_RR_PRVT_LBW_BASE 0x44CE600ull
+#define DCORE2_MME_CTRL_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_MME_CTRL_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE2_MME_CTRL_MSTR_IF_E2E_CRDT_BASE 0x44CE800ull
+#define DCORE2_MME_CTRL_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_MME_CTRL_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE2_MME_CTRL_MSTR_IF_AXUSER_BASE 0x44CEA80ull
+#define DCORE2_MME_CTRL_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_MME_CTRL_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE2_MME_CTRL_MSTR_IF_DBG_HBW_BASE 0x44CEB00ull
+#define DCORE2_MME_CTRL_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_MME_CTRL_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_MME_CTRL_MSTR_IF_DBG_LBW_BASE 0x44CEB80ull
+#define DCORE2_MME_CTRL_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_MME_CTRL_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE2_MME_CTRL_MSTR_IF_CORE_HBW_BASE 0x44CEC00ull
+#define DCORE2_MME_CTRL_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_MME_CTRL_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE2_MME_CTRL_MSTR_IF_CORE_LBW_BASE 0x44CED80ull
+#define DCORE2_MME_CTRL_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_MME_CTRL_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE2_MME_CTRL_MSTR_IF_SPECIAL_BASE 0x44CEE80ull
+#define DCORE2_MME_CTRL_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_CTRL_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE2_MME_QM_ARC_ACP_ENG_BASE 0x44CF000ull
+#define DCORE2_MME_QM_ARC_ACP_ENG_MAX_OFFSET 0x1000
+#define DCORE2_MME_QM_ARC_ACP_ENG_SECTION 0xE800
+#define mmDCORE2_MME_QM_ARC_ACP_ENG_SPECIAL_BASE 0x44CFE80ull
+#define DCORE2_MME_QM_ARC_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_QM_ARC_ACP_ENG_SPECIAL_SECTION 0x1800
+#define mmDCORE2_MME_SBTE0_BASE 0x44D0000ull
+#define DCORE2_MME_SBTE0_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE0_SECTION 0xE800
+#define mmDCORE2_MME_SBTE0_SPECIAL_BASE 0x44D0E80ull
+#define DCORE2_MME_SBTE0_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_SBTE0_SPECIAL_SECTION 0x1800
+#define mmDCORE2_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_BASE 0x44D1000ull
+#define DCORE2_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE2_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_BASE 0x44D1200ull
+#define DCORE2_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE2_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_BASE 0x44D1400ull
+#define DCORE2_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE2_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_BASE 0x44D1600ull
+#define DCORE2_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE2_MME_SBTE0_MSTR_IF_E2E_CRDT_BASE 0x44D1800ull
+#define DCORE2_MME_SBTE0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_MME_SBTE0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE2_MME_SBTE0_MSTR_IF_AXUSER_BASE 0x44D1A80ull
+#define DCORE2_MME_SBTE0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_MME_SBTE0_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE2_MME_SBTE0_MSTR_IF_DBG_HBW_BASE 0x44D1B00ull
+#define DCORE2_MME_SBTE0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_MME_SBTE0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_MME_SBTE0_MSTR_IF_DBG_LBW_BASE 0x44D1B80ull
+#define DCORE2_MME_SBTE0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_MME_SBTE0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE2_MME_SBTE0_MSTR_IF_CORE_HBW_BASE 0x44D1C00ull
+#define DCORE2_MME_SBTE0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_MME_SBTE0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE2_MME_SBTE0_MSTR_IF_CORE_LBW_BASE 0x44D1D80ull
+#define DCORE2_MME_SBTE0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_MME_SBTE0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE2_MME_SBTE0_MSTR_IF_SPECIAL_BASE 0x44D1E80ull
+#define DCORE2_MME_SBTE0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_SBTE0_MSTR_IF_SPECIAL_SECTION 0x6180
+#define mmDCORE2_MME_SBTE1_BASE 0x44D8000ull
+#define DCORE2_MME_SBTE1_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE1_SECTION 0xE800
+#define mmDCORE2_MME_SBTE1_SPECIAL_BASE 0x44D8E80ull
+#define DCORE2_MME_SBTE1_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_SBTE1_SPECIAL_SECTION 0x1800
+#define mmDCORE2_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_BASE 0x44D9000ull
+#define DCORE2_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE2_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_BASE 0x44D9200ull
+#define DCORE2_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE2_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_BASE 0x44D9400ull
+#define DCORE2_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE2_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_BASE 0x44D9600ull
+#define DCORE2_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE2_MME_SBTE1_MSTR_IF_E2E_CRDT_BASE 0x44D9800ull
+#define DCORE2_MME_SBTE1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_MME_SBTE1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE2_MME_SBTE1_MSTR_IF_AXUSER_BASE 0x44D9A80ull
+#define DCORE2_MME_SBTE1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_MME_SBTE1_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE2_MME_SBTE1_MSTR_IF_DBG_HBW_BASE 0x44D9B00ull
+#define DCORE2_MME_SBTE1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_MME_SBTE1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_MME_SBTE1_MSTR_IF_DBG_LBW_BASE 0x44D9B80ull
+#define DCORE2_MME_SBTE1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_MME_SBTE1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE2_MME_SBTE1_MSTR_IF_CORE_HBW_BASE 0x44D9C00ull
+#define DCORE2_MME_SBTE1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_MME_SBTE1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE2_MME_SBTE1_MSTR_IF_CORE_LBW_BASE 0x44D9D80ull
+#define DCORE2_MME_SBTE1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_MME_SBTE1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE2_MME_SBTE1_MSTR_IF_SPECIAL_BASE 0x44D9E80ull
+#define DCORE2_MME_SBTE1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_SBTE1_MSTR_IF_SPECIAL_SECTION 0x6180
+#define mmDCORE2_MME_SBTE2_BASE 0x44E0000ull
+#define DCORE2_MME_SBTE2_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE2_SECTION 0xE800
+#define mmDCORE2_MME_SBTE2_SPECIAL_BASE 0x44E0E80ull
+#define DCORE2_MME_SBTE2_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_SBTE2_SPECIAL_SECTION 0x1800
+#define mmDCORE2_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_BASE 0x44E1000ull
+#define DCORE2_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE2_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_BASE 0x44E1200ull
+#define DCORE2_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE2_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_BASE 0x44E1400ull
+#define DCORE2_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE2_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_BASE 0x44E1600ull
+#define DCORE2_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE2_MME_SBTE2_MSTR_IF_E2E_CRDT_BASE 0x44E1800ull
+#define DCORE2_MME_SBTE2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_MME_SBTE2_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE2_MME_SBTE2_MSTR_IF_AXUSER_BASE 0x44E1A80ull
+#define DCORE2_MME_SBTE2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_MME_SBTE2_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE2_MME_SBTE2_MSTR_IF_DBG_HBW_BASE 0x44E1B00ull
+#define DCORE2_MME_SBTE2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_MME_SBTE2_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_MME_SBTE2_MSTR_IF_DBG_LBW_BASE 0x44E1B80ull
+#define DCORE2_MME_SBTE2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_MME_SBTE2_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE2_MME_SBTE2_MSTR_IF_CORE_HBW_BASE 0x44E1C00ull
+#define DCORE2_MME_SBTE2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_MME_SBTE2_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE2_MME_SBTE2_MSTR_IF_CORE_LBW_BASE 0x44E1D80ull
+#define DCORE2_MME_SBTE2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_MME_SBTE2_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE2_MME_SBTE2_MSTR_IF_SPECIAL_BASE 0x44E1E80ull
+#define DCORE2_MME_SBTE2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_SBTE2_MSTR_IF_SPECIAL_SECTION 0x6180
+#define mmDCORE2_MME_SBTE3_BASE 0x44E8000ull
+#define DCORE2_MME_SBTE3_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE3_SECTION 0xE800
+#define mmDCORE2_MME_SBTE3_SPECIAL_BASE 0x44E8E80ull
+#define DCORE2_MME_SBTE3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_SBTE3_SPECIAL_SECTION 0x1800
+#define mmDCORE2_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_BASE 0x44E9000ull
+#define DCORE2_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE2_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_BASE 0x44E9200ull
+#define DCORE2_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE2_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_BASE 0x44E9400ull
+#define DCORE2_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE2_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_BASE 0x44E9600ull
+#define DCORE2_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE2_MME_SBTE3_MSTR_IF_E2E_CRDT_BASE 0x44E9800ull
+#define DCORE2_MME_SBTE3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_MME_SBTE3_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE2_MME_SBTE3_MSTR_IF_AXUSER_BASE 0x44E9A80ull
+#define DCORE2_MME_SBTE3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_MME_SBTE3_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE2_MME_SBTE3_MSTR_IF_DBG_HBW_BASE 0x44E9B00ull
+#define DCORE2_MME_SBTE3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_MME_SBTE3_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_MME_SBTE3_MSTR_IF_DBG_LBW_BASE 0x44E9B80ull
+#define DCORE2_MME_SBTE3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_MME_SBTE3_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE2_MME_SBTE3_MSTR_IF_CORE_HBW_BASE 0x44E9C00ull
+#define DCORE2_MME_SBTE3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_MME_SBTE3_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE2_MME_SBTE3_MSTR_IF_CORE_LBW_BASE 0x44E9D80ull
+#define DCORE2_MME_SBTE3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_MME_SBTE3_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE2_MME_SBTE3_MSTR_IF_SPECIAL_BASE 0x44E9E80ull
+#define DCORE2_MME_SBTE3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_SBTE3_MSTR_IF_SPECIAL_SECTION 0x6180
+#define mmDCORE2_MME_SBTE4_BASE 0x44F0000ull
+#define DCORE2_MME_SBTE4_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE4_SECTION 0xE800
+#define mmDCORE2_MME_SBTE4_SPECIAL_BASE 0x44F0E80ull
+#define DCORE2_MME_SBTE4_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_SBTE4_SPECIAL_SECTION 0x1800
+#define mmDCORE2_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_BASE 0x44F1000ull
+#define DCORE2_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE2_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_BASE 0x44F1200ull
+#define DCORE2_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE2_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_BASE 0x44F1400ull
+#define DCORE2_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE2_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_BASE 0x44F1600ull
+#define DCORE2_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE2_MME_SBTE4_MSTR_IF_E2E_CRDT_BASE 0x44F1800ull
+#define DCORE2_MME_SBTE4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_MME_SBTE4_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE2_MME_SBTE4_MSTR_IF_AXUSER_BASE 0x44F1A80ull
+#define DCORE2_MME_SBTE4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_MME_SBTE4_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE2_MME_SBTE4_MSTR_IF_DBG_HBW_BASE 0x44F1B00ull
+#define DCORE2_MME_SBTE4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_MME_SBTE4_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_MME_SBTE4_MSTR_IF_DBG_LBW_BASE 0x44F1B80ull
+#define DCORE2_MME_SBTE4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_MME_SBTE4_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE2_MME_SBTE4_MSTR_IF_CORE_HBW_BASE 0x44F1C00ull
+#define DCORE2_MME_SBTE4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_MME_SBTE4_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE2_MME_SBTE4_MSTR_IF_CORE_LBW_BASE 0x44F1D80ull
+#define DCORE2_MME_SBTE4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_MME_SBTE4_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE2_MME_SBTE4_MSTR_IF_SPECIAL_BASE 0x44F1E80ull
+#define DCORE2_MME_SBTE4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_SBTE4_MSTR_IF_SPECIAL_SECTION 0x6180
+#define mmDCORE2_MME_ACC_BASE 0x44F8000ull
+#define DCORE2_MME_ACC_MAX_OFFSET 0x1000
+#define DCORE2_MME_ACC_SECTION 0xE800
+#define mmDCORE2_MME_ACC_SPECIAL_BASE 0x44F8E80ull
+#define DCORE2_MME_ACC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_ACC_SPECIAL_SECTION 0x1800
+#define mmDCORE2_MME_WB0_MSTR_IF_RR_SHRD_HBW_BASE 0x44F9000ull
+#define DCORE2_MME_WB0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_MME_WB0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE2_MME_WB0_MSTR_IF_RR_PRVT_HBW_BASE 0x44F9200ull
+#define DCORE2_MME_WB0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_MME_WB0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE2_MME_WB0_MSTR_IF_RR_SHRD_LBW_BASE 0x44F9400ull
+#define DCORE2_MME_WB0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_MME_WB0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE2_MME_WB0_MSTR_IF_RR_PRVT_LBW_BASE 0x44F9600ull
+#define DCORE2_MME_WB0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_MME_WB0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE2_MME_WB0_MSTR_IF_E2E_CRDT_BASE 0x44F9800ull
+#define DCORE2_MME_WB0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_MME_WB0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE2_MME_WB0_MSTR_IF_AXUSER_BASE 0x44F9A80ull
+#define DCORE2_MME_WB0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_MME_WB0_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE2_MME_WB0_MSTR_IF_DBG_HBW_BASE 0x44F9B00ull
+#define DCORE2_MME_WB0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_MME_WB0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_MME_WB0_MSTR_IF_DBG_LBW_BASE 0x44F9B80ull
+#define DCORE2_MME_WB0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_MME_WB0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE2_MME_WB0_MSTR_IF_CORE_HBW_BASE 0x44F9C00ull
+#define DCORE2_MME_WB0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_MME_WB0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE2_MME_WB0_MSTR_IF_CORE_LBW_BASE 0x44F9D80ull
+#define DCORE2_MME_WB0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_MME_WB0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE2_MME_WB0_MSTR_IF_SPECIAL_BASE 0x44F9E80ull
+#define DCORE2_MME_WB0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_WB0_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE2_MME_WB1_MSTR_IF_RR_SHRD_HBW_BASE 0x44FA000ull
+#define DCORE2_MME_WB1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_MME_WB1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE2_MME_WB1_MSTR_IF_RR_PRVT_HBW_BASE 0x44FA200ull
+#define DCORE2_MME_WB1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_MME_WB1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE2_MME_WB1_MSTR_IF_RR_SHRD_LBW_BASE 0x44FA400ull
+#define DCORE2_MME_WB1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_MME_WB1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE2_MME_WB1_MSTR_IF_RR_PRVT_LBW_BASE 0x44FA600ull
+#define DCORE2_MME_WB1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_MME_WB1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE2_MME_WB1_MSTR_IF_E2E_CRDT_BASE 0x44FA800ull
+#define DCORE2_MME_WB1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_MME_WB1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE2_MME_WB1_MSTR_IF_AXUSER_BASE 0x44FAA80ull
+#define DCORE2_MME_WB1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_MME_WB1_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE2_MME_WB1_MSTR_IF_DBG_HBW_BASE 0x44FAB00ull
+#define DCORE2_MME_WB1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_MME_WB1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_MME_WB1_MSTR_IF_DBG_LBW_BASE 0x44FAB80ull
+#define DCORE2_MME_WB1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_MME_WB1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE2_MME_WB1_MSTR_IF_CORE_HBW_BASE 0x44FAC00ull
+#define DCORE2_MME_WB1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_MME_WB1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE2_MME_WB1_MSTR_IF_CORE_LBW_BASE 0x44FAD80ull
+#define DCORE2_MME_WB1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_MME_WB1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE2_MME_WB1_MSTR_IF_SPECIAL_BASE 0x44FAE80ull
+#define DCORE2_MME_WB1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_MME_WB1_MSTR_IF_SPECIAL_SECTION 0x5180
+#define mmDCORE2_SYNC_MNGR_OBJS_BASE 0x4500000ull
+#define DCORE2_SYNC_MNGR_OBJS_MAX_OFFSET 0x15A00
+#define DCORE2_SYNC_MNGR_OBJS_SECTION 0x1E000
+#define mmDCORE2_SYNC_MNGR_GLBL_BASE 0x451E000ull
+#define DCORE2_SYNC_MNGR_GLBL_MAX_OFFSET 0x1000
+#define DCORE2_SYNC_MNGR_GLBL_SECTION 0xE800
+#define mmDCORE2_SYNC_MNGR_GLBL_SPECIAL_BASE 0x451EE80ull
+#define DCORE2_SYNC_MNGR_GLBL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SYNC_MNGR_GLBL_SPECIAL_SECTION 0x1800
+#define mmDCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_BASE 0x451F000ull
+#define DCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_BASE 0x451F200ull
+#define DCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_BASE 0x451F400ull
+#define DCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_BASE 0x451F600ull
+#define DCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE2_SYNC_MNGR_MSTR_IF_E2E_CRDT_BASE 0x451F800ull
+#define DCORE2_SYNC_MNGR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_SYNC_MNGR_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE2_SYNC_MNGR_MSTR_IF_AXUSER_BASE 0x451FA80ull
+#define DCORE2_SYNC_MNGR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_SYNC_MNGR_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE2_SYNC_MNGR_MSTR_IF_DBG_HBW_BASE 0x451FB00ull
+#define DCORE2_SYNC_MNGR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_SYNC_MNGR_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_SYNC_MNGR_MSTR_IF_DBG_LBW_BASE 0x451FB80ull
+#define DCORE2_SYNC_MNGR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_SYNC_MNGR_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE2_SYNC_MNGR_MSTR_IF_CORE_HBW_BASE 0x451FC00ull
+#define DCORE2_SYNC_MNGR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_SYNC_MNGR_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE2_SYNC_MNGR_MSTR_IF_CORE_LBW_BASE 0x451FD80ull
+#define DCORE2_SYNC_MNGR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_SYNC_MNGR_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE2_SYNC_MNGR_MSTR_IF_SPECIAL_BASE 0x451FE80ull
+#define DCORE2_SYNC_MNGR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SYNC_MNGR_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE2_HIF0_BASE 0x4520000ull
+#define DCORE2_HIF0_MAX_OFFSET 0x1000
+#define DCORE2_HIF0_SECTION 0xE800
+#define mmDCORE2_HIF0_SPECIAL_BASE 0x4520E80ull
+#define DCORE2_HIF0_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HIF0_SPECIAL_SECTION 0x3180
+#define mmDCORE2_HIF1_BASE 0x4524000ull
+#define DCORE2_HIF1_MAX_OFFSET 0x1000
+#define DCORE2_HIF1_SECTION 0xE800
+#define mmDCORE2_HIF1_SPECIAL_BASE 0x4524E80ull
+#define DCORE2_HIF1_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HIF1_SPECIAL_SECTION 0x3180
+#define mmDCORE2_HIF2_BASE 0x4528000ull
+#define DCORE2_HIF2_MAX_OFFSET 0x1000
+#define DCORE2_HIF2_SECTION 0xE800
+#define mmDCORE2_HIF2_SPECIAL_BASE 0x4528E80ull
+#define DCORE2_HIF2_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HIF2_SPECIAL_SECTION 0x3180
+#define mmDCORE2_HIF3_BASE 0x452C000ull
+#define DCORE2_HIF3_MAX_OFFSET 0x1000
+#define DCORE2_HIF3_SECTION 0xE800
+#define mmDCORE2_HIF3_SPECIAL_BASE 0x452CE80ull
+#define DCORE2_HIF3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HIF3_SPECIAL_SECTION 0x13180
+#define mmDCORE2_RTR0_CTRL_BASE 0x4540000ull
+#define DCORE2_RTR0_CTRL_MAX_OFFSET 0x1000
+#define DCORE2_RTR0_CTRL_SECTION 0xE800
+#define mmDCORE2_RTR0_CTRL_SPECIAL_BASE 0x4540E80ull
+#define DCORE2_RTR0_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR0_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE2_RTR0_H3_BASE 0x4541000ull
+#define DCORE2_RTR0_H3_MAX_OFFSET 0x1000
+#define DCORE2_RTR0_H3_SECTION 0xE800
+#define mmDCORE2_RTR0_H3_SPECIAL_BASE 0x4541E80ull
+#define DCORE2_RTR0_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR0_H3_SPECIAL_SECTION 0x1800
+#define mmDCORE2_RTR0_MSTR_IF_RR_SHRD_HBW_BASE 0x4542000ull
+#define DCORE2_RTR0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_RTR0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE2_RTR0_MSTR_IF_RR_PRVT_HBW_BASE 0x4542200ull
+#define DCORE2_RTR0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_RTR0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE2_RTR0_MSTR_IF_RR_SHRD_LBW_BASE 0x4542400ull
+#define DCORE2_RTR0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_RTR0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE2_RTR0_MSTR_IF_RR_PRVT_LBW_BASE 0x4542600ull
+#define DCORE2_RTR0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_RTR0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE2_RTR0_MSTR_IF_E2E_CRDT_BASE 0x4542800ull
+#define DCORE2_RTR0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_RTR0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE2_RTR0_MSTR_IF_AXUSER_BASE 0x4542A80ull
+#define DCORE2_RTR0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_RTR0_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE2_RTR0_MSTR_IF_DBG_HBW_BASE 0x4542B00ull
+#define DCORE2_RTR0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_RTR0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_RTR0_MSTR_IF_DBG_LBW_BASE 0x4542B80ull
+#define DCORE2_RTR0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_RTR0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE2_RTR0_MSTR_IF_CORE_HBW_BASE 0x4542C00ull
+#define DCORE2_RTR0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_RTR0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE2_RTR0_MSTR_IF_CORE_LBW_BASE 0x4542D80ull
+#define DCORE2_RTR0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_RTR0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE2_RTR0_MSTR_IF_SPECIAL_BASE 0x4542E80ull
+#define DCORE2_RTR0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR0_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE2_RTR0_ADD_DEC_HBW_BASE 0x4543000ull
+#define DCORE2_RTR0_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE2_RTR0_ADD_DEC_HBW_SECTION 0x4000
+#define mmDCORE2_RTR0_ADD_DEC_LBW_BASE 0x4543400ull
+#define DCORE2_RTR0_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE2_RTR0_ADD_DEC_LBW_SECTION 0xA800
+#define mmDCORE2_RTR0_ADD_DEC_SPECIAL_BASE 0x4543E80ull
+#define DCORE2_RTR0_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR0_ADD_DEC_SPECIAL_SECTION 0x1800
+#define mmDCORE2_RTR0_BASE 0x4544000ull
+#define DCORE2_RTR0_MAX_OFFSET 0x1000
+#define DCORE2_RTR0_SECTION 0x3000
+#define mmDCORE2_RTR0_HBW_RD_RQ_LL_STAT_BASE 0x4544300ull
+#define DCORE2_RTR0_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR0_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR0_HBW_RD_RS_LL_STAT_BASE 0x4544340ull
+#define DCORE2_RTR0_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR0_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR0_HBW_WR_RQ_LL_STAT_BASE 0x4544380ull
+#define DCORE2_RTR0_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR0_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR0_HBW_WR_RS_LL_STAT_BASE 0x45443C0ull
+#define DCORE2_RTR0_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR0_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR0_LBW_RD_RQ_LL_STAT_BASE 0x4544400ull
+#define DCORE2_RTR0_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR0_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR0_LBW_RD_RS_LL_STAT_BASE 0x4544440ull
+#define DCORE2_RTR0_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR0_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR0_LBW_WR_RQ_LL_STAT_BASE 0x4544480ull
+#define DCORE2_RTR0_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR0_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR0_LBW_WR_RS_LL_STAT_BASE 0x45444C0ull
+#define DCORE2_RTR0_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR0_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR0_HBW_MFIFO_BASE 0x4544500ull
+#define DCORE2_RTR0_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE2_RTR0_HBW_MFIFO_SECTION 0x4000
+#define mmDCORE2_RTR0_E2E_RD_LL_STAT_BASE 0x4544540ull
+#define DCORE2_RTR0_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR0_E2E_RD_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR0_E2E_WR_LL_STAT_BASE 0x4544580ull
+#define DCORE2_RTR0_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR0_E2E_WR_LL_STAT_SECTION 0x8000
+#define mmDCORE2_RTR0_RTR_HBW_XACT_STAT_BASE 0x4544600ull
+#define DCORE2_RTR0_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR0_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE2_RTR0_RTR_LBW_XACT_STAT_BASE 0x4544680ull
+#define DCORE2_RTR0_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR0_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE2_RTR0_RTR_E2E_XACT_STAT_BASE 0x4544700ull
+#define DCORE2_RTR0_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR0_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define mmDCORE2_RTR0_SPECIAL_BASE 0x4544E80ull
+#define DCORE2_RTR0_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR0_SPECIAL_SECTION 0x1800
+#define mmDCORE2_RTR0_DBG_ADDR_BASE 0x4545000ull
+#define DCORE2_RTR0_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE2_RTR0_DBG_ADDR_SECTION 0xE800
+#define mmDCORE2_RTR0_DBG_ADDR_SPECIAL_BASE 0x4545E80ull
+#define DCORE2_RTR0_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR0_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define mmDCORE2_RTR1_CTRL_BASE 0x4548000ull
+#define DCORE2_RTR1_CTRL_MAX_OFFSET 0x1000
+#define DCORE2_RTR1_CTRL_SECTION 0xE800
+#define mmDCORE2_RTR1_CTRL_SPECIAL_BASE 0x4548E80ull
+#define DCORE2_RTR1_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR1_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE2_RTR1_H3_BASE 0x4549000ull
+#define DCORE2_RTR1_H3_MAX_OFFSET 0x1000
+#define DCORE2_RTR1_H3_SECTION 0xE800
+#define mmDCORE2_RTR1_H3_SPECIAL_BASE 0x4549E80ull
+#define DCORE2_RTR1_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR1_H3_SPECIAL_SECTION 0x1800
+#define mmDCORE2_RTR1_MSTR_IF_RR_SHRD_HBW_BASE 0x454A000ull
+#define DCORE2_RTR1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_RTR1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE2_RTR1_MSTR_IF_RR_PRVT_HBW_BASE 0x454A200ull
+#define DCORE2_RTR1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_RTR1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE2_RTR1_MSTR_IF_RR_SHRD_LBW_BASE 0x454A400ull
+#define DCORE2_RTR1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_RTR1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE2_RTR1_MSTR_IF_RR_PRVT_LBW_BASE 0x454A600ull
+#define DCORE2_RTR1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_RTR1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE2_RTR1_MSTR_IF_E2E_CRDT_BASE 0x454A800ull
+#define DCORE2_RTR1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_RTR1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE2_RTR1_MSTR_IF_AXUSER_BASE 0x454AA80ull
+#define DCORE2_RTR1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_RTR1_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE2_RTR1_MSTR_IF_DBG_HBW_BASE 0x454AB00ull
+#define DCORE2_RTR1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_RTR1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_RTR1_MSTR_IF_DBG_LBW_BASE 0x454AB80ull
+#define DCORE2_RTR1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_RTR1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE2_RTR1_MSTR_IF_CORE_HBW_BASE 0x454AC00ull
+#define DCORE2_RTR1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_RTR1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE2_RTR1_MSTR_IF_CORE_LBW_BASE 0x454AD80ull
+#define DCORE2_RTR1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_RTR1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE2_RTR1_MSTR_IF_SPECIAL_BASE 0x454AE80ull
+#define DCORE2_RTR1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR1_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE2_RTR1_ADD_DEC_HBW_BASE 0x454B000ull
+#define DCORE2_RTR1_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE2_RTR1_ADD_DEC_HBW_SECTION 0x4000
+#define mmDCORE2_RTR1_ADD_DEC_LBW_BASE 0x454B400ull
+#define DCORE2_RTR1_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE2_RTR1_ADD_DEC_LBW_SECTION 0xA800
+#define mmDCORE2_RTR1_ADD_DEC_SPECIAL_BASE 0x454BE80ull
+#define DCORE2_RTR1_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR1_ADD_DEC_SPECIAL_SECTION 0x1800
+#define mmDCORE2_RTR1_BASE 0x454C000ull
+#define DCORE2_RTR1_MAX_OFFSET 0x1000
+#define DCORE2_RTR1_SECTION 0x3000
+#define mmDCORE2_RTR1_HBW_RD_RQ_LL_STAT_BASE 0x454C300ull
+#define DCORE2_RTR1_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR1_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR1_HBW_RD_RS_LL_STAT_BASE 0x454C340ull
+#define DCORE2_RTR1_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR1_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR1_HBW_WR_RQ_LL_STAT_BASE 0x454C380ull
+#define DCORE2_RTR1_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR1_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR1_HBW_WR_RS_LL_STAT_BASE 0x454C3C0ull
+#define DCORE2_RTR1_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR1_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR1_LBW_RD_RQ_LL_STAT_BASE 0x454C400ull
+#define DCORE2_RTR1_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR1_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR1_LBW_RD_RS_LL_STAT_BASE 0x454C440ull
+#define DCORE2_RTR1_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR1_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR1_LBW_WR_RQ_LL_STAT_BASE 0x454C480ull
+#define DCORE2_RTR1_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR1_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR1_LBW_WR_RS_LL_STAT_BASE 0x454C4C0ull
+#define DCORE2_RTR1_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR1_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR1_HBW_MFIFO_BASE 0x454C500ull
+#define DCORE2_RTR1_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE2_RTR1_HBW_MFIFO_SECTION 0x4000
+#define mmDCORE2_RTR1_E2E_RD_LL_STAT_BASE 0x454C540ull
+#define DCORE2_RTR1_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR1_E2E_RD_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR1_E2E_WR_LL_STAT_BASE 0x454C580ull
+#define DCORE2_RTR1_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR1_E2E_WR_LL_STAT_SECTION 0x8000
+#define mmDCORE2_RTR1_RTR_HBW_XACT_STAT_BASE 0x454C600ull
+#define DCORE2_RTR1_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR1_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE2_RTR1_RTR_LBW_XACT_STAT_BASE 0x454C680ull
+#define DCORE2_RTR1_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR1_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE2_RTR1_RTR_E2E_XACT_STAT_BASE 0x454C700ull
+#define DCORE2_RTR1_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR1_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define mmDCORE2_RTR1_SPECIAL_BASE 0x454CE80ull
+#define DCORE2_RTR1_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR1_SPECIAL_SECTION 0x1800
+#define mmDCORE2_RTR1_DBG_ADDR_BASE 0x454D000ull
+#define DCORE2_RTR1_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE2_RTR1_DBG_ADDR_SECTION 0xE800
+#define mmDCORE2_RTR1_DBG_ADDR_SPECIAL_BASE 0x454DE80ull
+#define DCORE2_RTR1_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR1_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define mmDCORE2_RTR2_CTRL_BASE 0x4550000ull
+#define DCORE2_RTR2_CTRL_MAX_OFFSET 0x1000
+#define DCORE2_RTR2_CTRL_SECTION 0xE800
+#define mmDCORE2_RTR2_CTRL_SPECIAL_BASE 0x4550E80ull
+#define DCORE2_RTR2_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR2_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE2_RTR2_H3_BASE 0x4551000ull
+#define DCORE2_RTR2_H3_MAX_OFFSET 0x1000
+#define DCORE2_RTR2_H3_SECTION 0xE800
+#define mmDCORE2_RTR2_H3_SPECIAL_BASE 0x4551E80ull
+#define DCORE2_RTR2_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR2_H3_SPECIAL_SECTION 0x1800
+#define mmDCORE2_RTR2_MSTR_IF_RR_SHRD_HBW_BASE 0x4552000ull
+#define DCORE2_RTR2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_RTR2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE2_RTR2_MSTR_IF_RR_PRVT_HBW_BASE 0x4552200ull
+#define DCORE2_RTR2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_RTR2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE2_RTR2_MSTR_IF_RR_SHRD_LBW_BASE 0x4552400ull
+#define DCORE2_RTR2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_RTR2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE2_RTR2_MSTR_IF_RR_PRVT_LBW_BASE 0x4552600ull
+#define DCORE2_RTR2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_RTR2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE2_RTR2_MSTR_IF_E2E_CRDT_BASE 0x4552800ull
+#define DCORE2_RTR2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_RTR2_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE2_RTR2_MSTR_IF_AXUSER_BASE 0x4552A80ull
+#define DCORE2_RTR2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_RTR2_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE2_RTR2_MSTR_IF_DBG_HBW_BASE 0x4552B00ull
+#define DCORE2_RTR2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_RTR2_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_RTR2_MSTR_IF_DBG_LBW_BASE 0x4552B80ull
+#define DCORE2_RTR2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_RTR2_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE2_RTR2_MSTR_IF_CORE_HBW_BASE 0x4552C00ull
+#define DCORE2_RTR2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_RTR2_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE2_RTR2_MSTR_IF_CORE_LBW_BASE 0x4552D80ull
+#define DCORE2_RTR2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_RTR2_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE2_RTR2_MSTR_IF_SPECIAL_BASE 0x4552E80ull
+#define DCORE2_RTR2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR2_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE2_RTR2_ADD_DEC_HBW_BASE 0x4553000ull
+#define DCORE2_RTR2_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE2_RTR2_ADD_DEC_HBW_SECTION 0x4000
+#define mmDCORE2_RTR2_ADD_DEC_LBW_BASE 0x4553400ull
+#define DCORE2_RTR2_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE2_RTR2_ADD_DEC_LBW_SECTION 0xA800
+#define mmDCORE2_RTR2_ADD_DEC_SPECIAL_BASE 0x4553E80ull
+#define DCORE2_RTR2_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR2_ADD_DEC_SPECIAL_SECTION 0x1800
+#define mmDCORE2_RTR2_BASE 0x4554000ull
+#define DCORE2_RTR2_MAX_OFFSET 0x1000
+#define DCORE2_RTR2_SECTION 0x3000
+#define mmDCORE2_RTR2_HBW_RD_RQ_LL_STAT_BASE 0x4554300ull
+#define DCORE2_RTR2_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR2_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR2_HBW_RD_RS_LL_STAT_BASE 0x4554340ull
+#define DCORE2_RTR2_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR2_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR2_HBW_WR_RQ_LL_STAT_BASE 0x4554380ull
+#define DCORE2_RTR2_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR2_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR2_HBW_WR_RS_LL_STAT_BASE 0x45543C0ull
+#define DCORE2_RTR2_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR2_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR2_LBW_RD_RQ_LL_STAT_BASE 0x4554400ull
+#define DCORE2_RTR2_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR2_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR2_LBW_RD_RS_LL_STAT_BASE 0x4554440ull
+#define DCORE2_RTR2_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR2_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR2_LBW_WR_RQ_LL_STAT_BASE 0x4554480ull
+#define DCORE2_RTR2_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR2_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR2_LBW_WR_RS_LL_STAT_BASE 0x45544C0ull
+#define DCORE2_RTR2_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR2_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR2_HBW_MFIFO_BASE 0x4554500ull
+#define DCORE2_RTR2_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE2_RTR2_HBW_MFIFO_SECTION 0x4000
+#define mmDCORE2_RTR2_E2E_RD_LL_STAT_BASE 0x4554540ull
+#define DCORE2_RTR2_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR2_E2E_RD_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR2_E2E_WR_LL_STAT_BASE 0x4554580ull
+#define DCORE2_RTR2_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR2_E2E_WR_LL_STAT_SECTION 0x8000
+#define mmDCORE2_RTR2_RTR_HBW_XACT_STAT_BASE 0x4554600ull
+#define DCORE2_RTR2_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR2_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE2_RTR2_RTR_LBW_XACT_STAT_BASE 0x4554680ull
+#define DCORE2_RTR2_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR2_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE2_RTR2_RTR_E2E_XACT_STAT_BASE 0x4554700ull
+#define DCORE2_RTR2_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR2_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define mmDCORE2_RTR2_SPECIAL_BASE 0x4554E80ull
+#define DCORE2_RTR2_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR2_SPECIAL_SECTION 0x1800
+#define mmDCORE2_RTR2_DBG_ADDR_BASE 0x4555000ull
+#define DCORE2_RTR2_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE2_RTR2_DBG_ADDR_SECTION 0xE800
+#define mmDCORE2_RTR2_DBG_ADDR_SPECIAL_BASE 0x4555E80ull
+#define DCORE2_RTR2_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR2_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define mmDCORE2_RTR3_CTRL_BASE 0x4558000ull
+#define DCORE2_RTR3_CTRL_MAX_OFFSET 0x1000
+#define DCORE2_RTR3_CTRL_SECTION 0xE800
+#define mmDCORE2_RTR3_CTRL_SPECIAL_BASE 0x4558E80ull
+#define DCORE2_RTR3_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR3_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE2_RTR3_H3_BASE 0x4559000ull
+#define DCORE2_RTR3_H3_MAX_OFFSET 0x1000
+#define DCORE2_RTR3_H3_SECTION 0xE800
+#define mmDCORE2_RTR3_H3_SPECIAL_BASE 0x4559E80ull
+#define DCORE2_RTR3_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR3_H3_SPECIAL_SECTION 0x1800
+#define mmDCORE2_RTR3_MSTR_IF_RR_SHRD_HBW_BASE 0x455A000ull
+#define DCORE2_RTR3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_RTR3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE2_RTR3_MSTR_IF_RR_PRVT_HBW_BASE 0x455A200ull
+#define DCORE2_RTR3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_RTR3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE2_RTR3_MSTR_IF_RR_SHRD_LBW_BASE 0x455A400ull
+#define DCORE2_RTR3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_RTR3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE2_RTR3_MSTR_IF_RR_PRVT_LBW_BASE 0x455A600ull
+#define DCORE2_RTR3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_RTR3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE2_RTR3_MSTR_IF_E2E_CRDT_BASE 0x455A800ull
+#define DCORE2_RTR3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_RTR3_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE2_RTR3_MSTR_IF_AXUSER_BASE 0x455AA80ull
+#define DCORE2_RTR3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_RTR3_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE2_RTR3_MSTR_IF_DBG_HBW_BASE 0x455AB00ull
+#define DCORE2_RTR3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_RTR3_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_RTR3_MSTR_IF_DBG_LBW_BASE 0x455AB80ull
+#define DCORE2_RTR3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_RTR3_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE2_RTR3_MSTR_IF_CORE_HBW_BASE 0x455AC00ull
+#define DCORE2_RTR3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_RTR3_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE2_RTR3_MSTR_IF_CORE_LBW_BASE 0x455AD80ull
+#define DCORE2_RTR3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_RTR3_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE2_RTR3_MSTR_IF_SPECIAL_BASE 0x455AE80ull
+#define DCORE2_RTR3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR3_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE2_RTR3_ADD_DEC_HBW_BASE 0x455B000ull
+#define DCORE2_RTR3_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE2_RTR3_ADD_DEC_HBW_SECTION 0x4000
+#define mmDCORE2_RTR3_ADD_DEC_LBW_BASE 0x455B400ull
+#define DCORE2_RTR3_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE2_RTR3_ADD_DEC_LBW_SECTION 0xA800
+#define mmDCORE2_RTR3_ADD_DEC_SPECIAL_BASE 0x455BE80ull
+#define DCORE2_RTR3_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR3_ADD_DEC_SPECIAL_SECTION 0x1800
+#define mmDCORE2_RTR3_BASE 0x455C000ull
+#define DCORE2_RTR3_MAX_OFFSET 0x1000
+#define DCORE2_RTR3_SECTION 0x3000
+#define mmDCORE2_RTR3_HBW_RD_RQ_LL_STAT_BASE 0x455C300ull
+#define DCORE2_RTR3_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR3_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR3_HBW_RD_RS_LL_STAT_BASE 0x455C340ull
+#define DCORE2_RTR3_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR3_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR3_HBW_WR_RQ_LL_STAT_BASE 0x455C380ull
+#define DCORE2_RTR3_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR3_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR3_HBW_WR_RS_LL_STAT_BASE 0x455C3C0ull
+#define DCORE2_RTR3_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR3_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR3_LBW_RD_RQ_LL_STAT_BASE 0x455C400ull
+#define DCORE2_RTR3_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR3_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR3_LBW_RD_RS_LL_STAT_BASE 0x455C440ull
+#define DCORE2_RTR3_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR3_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR3_LBW_WR_RQ_LL_STAT_BASE 0x455C480ull
+#define DCORE2_RTR3_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR3_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR3_LBW_WR_RS_LL_STAT_BASE 0x455C4C0ull
+#define DCORE2_RTR3_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR3_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR3_HBW_MFIFO_BASE 0x455C500ull
+#define DCORE2_RTR3_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE2_RTR3_HBW_MFIFO_SECTION 0x4000
+#define mmDCORE2_RTR3_E2E_RD_LL_STAT_BASE 0x455C540ull
+#define DCORE2_RTR3_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR3_E2E_RD_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR3_E2E_WR_LL_STAT_BASE 0x455C580ull
+#define DCORE2_RTR3_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR3_E2E_WR_LL_STAT_SECTION 0x8000
+#define mmDCORE2_RTR3_RTR_HBW_XACT_STAT_BASE 0x455C600ull
+#define DCORE2_RTR3_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR3_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE2_RTR3_RTR_LBW_XACT_STAT_BASE 0x455C680ull
+#define DCORE2_RTR3_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR3_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE2_RTR3_RTR_E2E_XACT_STAT_BASE 0x455C700ull
+#define DCORE2_RTR3_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR3_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define mmDCORE2_RTR3_SPECIAL_BASE 0x455CE80ull
+#define DCORE2_RTR3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR3_SPECIAL_SECTION 0x1800
+#define mmDCORE2_RTR3_DBG_ADDR_BASE 0x455D000ull
+#define DCORE2_RTR3_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE2_RTR3_DBG_ADDR_SECTION 0xE800
+#define mmDCORE2_RTR3_DBG_ADDR_SPECIAL_BASE 0x455DE80ull
+#define DCORE2_RTR3_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR3_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define mmDCORE2_RTR4_CTRL_BASE 0x4560000ull
+#define DCORE2_RTR4_CTRL_MAX_OFFSET 0x1000
+#define DCORE2_RTR4_CTRL_SECTION 0xE800
+#define mmDCORE2_RTR4_CTRL_SPECIAL_BASE 0x4560E80ull
+#define DCORE2_RTR4_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR4_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE2_RTR4_H3_BASE 0x4561000ull
+#define DCORE2_RTR4_H3_MAX_OFFSET 0x1000
+#define DCORE2_RTR4_H3_SECTION 0xE800
+#define mmDCORE2_RTR4_H3_SPECIAL_BASE 0x4561E80ull
+#define DCORE2_RTR4_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR4_H3_SPECIAL_SECTION 0x1800
+#define mmDCORE2_RTR4_MSTR_IF_RR_SHRD_HBW_BASE 0x4562000ull
+#define DCORE2_RTR4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_RTR4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE2_RTR4_MSTR_IF_RR_PRVT_HBW_BASE 0x4562200ull
+#define DCORE2_RTR4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_RTR4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE2_RTR4_MSTR_IF_RR_SHRD_LBW_BASE 0x4562400ull
+#define DCORE2_RTR4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_RTR4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE2_RTR4_MSTR_IF_RR_PRVT_LBW_BASE 0x4562600ull
+#define DCORE2_RTR4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_RTR4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE2_RTR4_MSTR_IF_E2E_CRDT_BASE 0x4562800ull
+#define DCORE2_RTR4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_RTR4_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE2_RTR4_MSTR_IF_AXUSER_BASE 0x4562A80ull
+#define DCORE2_RTR4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_RTR4_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE2_RTR4_MSTR_IF_DBG_HBW_BASE 0x4562B00ull
+#define DCORE2_RTR4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_RTR4_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_RTR4_MSTR_IF_DBG_LBW_BASE 0x4562B80ull
+#define DCORE2_RTR4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_RTR4_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE2_RTR4_MSTR_IF_CORE_HBW_BASE 0x4562C00ull
+#define DCORE2_RTR4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_RTR4_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE2_RTR4_MSTR_IF_CORE_LBW_BASE 0x4562D80ull
+#define DCORE2_RTR4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_RTR4_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE2_RTR4_MSTR_IF_SPECIAL_BASE 0x4562E80ull
+#define DCORE2_RTR4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR4_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE2_RTR4_ADD_DEC_HBW_BASE 0x4563000ull
+#define DCORE2_RTR4_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE2_RTR4_ADD_DEC_HBW_SECTION 0x4000
+#define mmDCORE2_RTR4_ADD_DEC_LBW_BASE 0x4563400ull
+#define DCORE2_RTR4_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE2_RTR4_ADD_DEC_LBW_SECTION 0xA800
+#define mmDCORE2_RTR4_ADD_DEC_SPECIAL_BASE 0x4563E80ull
+#define DCORE2_RTR4_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR4_ADD_DEC_SPECIAL_SECTION 0x1800
+#define mmDCORE2_RTR4_BASE 0x4564000ull
+#define DCORE2_RTR4_MAX_OFFSET 0x1000
+#define DCORE2_RTR4_SECTION 0x3000
+#define mmDCORE2_RTR4_HBW_RD_RQ_LL_STAT_BASE 0x4564300ull
+#define DCORE2_RTR4_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR4_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR4_HBW_RD_RS_LL_STAT_BASE 0x4564340ull
+#define DCORE2_RTR4_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR4_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR4_HBW_WR_RQ_LL_STAT_BASE 0x4564380ull
+#define DCORE2_RTR4_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR4_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR4_HBW_WR_RS_LL_STAT_BASE 0x45643C0ull
+#define DCORE2_RTR4_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR4_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR4_LBW_RD_RQ_LL_STAT_BASE 0x4564400ull
+#define DCORE2_RTR4_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR4_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR4_LBW_RD_RS_LL_STAT_BASE 0x4564440ull
+#define DCORE2_RTR4_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR4_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR4_LBW_WR_RQ_LL_STAT_BASE 0x4564480ull
+#define DCORE2_RTR4_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR4_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR4_LBW_WR_RS_LL_STAT_BASE 0x45644C0ull
+#define DCORE2_RTR4_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR4_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR4_HBW_MFIFO_BASE 0x4564500ull
+#define DCORE2_RTR4_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE2_RTR4_HBW_MFIFO_SECTION 0x4000
+#define mmDCORE2_RTR4_E2E_RD_LL_STAT_BASE 0x4564540ull
+#define DCORE2_RTR4_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR4_E2E_RD_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR4_E2E_WR_LL_STAT_BASE 0x4564580ull
+#define DCORE2_RTR4_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR4_E2E_WR_LL_STAT_SECTION 0x8000
+#define mmDCORE2_RTR4_RTR_HBW_XACT_STAT_BASE 0x4564600ull
+#define DCORE2_RTR4_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR4_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE2_RTR4_RTR_LBW_XACT_STAT_BASE 0x4564680ull
+#define DCORE2_RTR4_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR4_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE2_RTR4_RTR_E2E_XACT_STAT_BASE 0x4564700ull
+#define DCORE2_RTR4_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR4_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define mmDCORE2_RTR4_SPECIAL_BASE 0x4564E80ull
+#define DCORE2_RTR4_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR4_SPECIAL_SECTION 0x1800
+#define mmDCORE2_RTR4_DBG_ADDR_BASE 0x4565000ull
+#define DCORE2_RTR4_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE2_RTR4_DBG_ADDR_SECTION 0xE800
+#define mmDCORE2_RTR4_DBG_ADDR_SPECIAL_BASE 0x4565E80ull
+#define DCORE2_RTR4_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR4_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define mmDCORE2_RTR5_CTRL_BASE 0x4568000ull
+#define DCORE2_RTR5_CTRL_MAX_OFFSET 0x1000
+#define DCORE2_RTR5_CTRL_SECTION 0xE800
+#define mmDCORE2_RTR5_CTRL_SPECIAL_BASE 0x4568E80ull
+#define DCORE2_RTR5_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR5_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE2_RTR5_H3_BASE 0x4569000ull
+#define DCORE2_RTR5_H3_MAX_OFFSET 0x1000
+#define DCORE2_RTR5_H3_SECTION 0xE800
+#define mmDCORE2_RTR5_H3_SPECIAL_BASE 0x4569E80ull
+#define DCORE2_RTR5_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR5_H3_SPECIAL_SECTION 0x1800
+#define mmDCORE2_RTR5_MSTR_IF_RR_SHRD_HBW_BASE 0x456A000ull
+#define DCORE2_RTR5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_RTR5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE2_RTR5_MSTR_IF_RR_PRVT_HBW_BASE 0x456A200ull
+#define DCORE2_RTR5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_RTR5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE2_RTR5_MSTR_IF_RR_SHRD_LBW_BASE 0x456A400ull
+#define DCORE2_RTR5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_RTR5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE2_RTR5_MSTR_IF_RR_PRVT_LBW_BASE 0x456A600ull
+#define DCORE2_RTR5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_RTR5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE2_RTR5_MSTR_IF_E2E_CRDT_BASE 0x456A800ull
+#define DCORE2_RTR5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_RTR5_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE2_RTR5_MSTR_IF_AXUSER_BASE 0x456AA80ull
+#define DCORE2_RTR5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_RTR5_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE2_RTR5_MSTR_IF_DBG_HBW_BASE 0x456AB00ull
+#define DCORE2_RTR5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_RTR5_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_RTR5_MSTR_IF_DBG_LBW_BASE 0x456AB80ull
+#define DCORE2_RTR5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_RTR5_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE2_RTR5_MSTR_IF_CORE_HBW_BASE 0x456AC00ull
+#define DCORE2_RTR5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_RTR5_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE2_RTR5_MSTR_IF_CORE_LBW_BASE 0x456AD80ull
+#define DCORE2_RTR5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_RTR5_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE2_RTR5_MSTR_IF_SPECIAL_BASE 0x456AE80ull
+#define DCORE2_RTR5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR5_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE2_RTR5_ADD_DEC_HBW_BASE 0x456B000ull
+#define DCORE2_RTR5_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE2_RTR5_ADD_DEC_HBW_SECTION 0x4000
+#define mmDCORE2_RTR5_ADD_DEC_LBW_BASE 0x456B400ull
+#define DCORE2_RTR5_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE2_RTR5_ADD_DEC_LBW_SECTION 0xA800
+#define mmDCORE2_RTR5_ADD_DEC_SPECIAL_BASE 0x456BE80ull
+#define DCORE2_RTR5_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR5_ADD_DEC_SPECIAL_SECTION 0x1800
+#define mmDCORE2_RTR5_BASE 0x456C000ull
+#define DCORE2_RTR5_MAX_OFFSET 0x1000
+#define DCORE2_RTR5_SECTION 0x3000
+#define mmDCORE2_RTR5_HBW_RD_RQ_LL_STAT_BASE 0x456C300ull
+#define DCORE2_RTR5_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR5_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR5_HBW_RD_RS_LL_STAT_BASE 0x456C340ull
+#define DCORE2_RTR5_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR5_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR5_HBW_WR_RQ_LL_STAT_BASE 0x456C380ull
+#define DCORE2_RTR5_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR5_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR5_HBW_WR_RS_LL_STAT_BASE 0x456C3C0ull
+#define DCORE2_RTR5_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR5_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR5_LBW_RD_RQ_LL_STAT_BASE 0x456C400ull
+#define DCORE2_RTR5_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR5_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR5_LBW_RD_RS_LL_STAT_BASE 0x456C440ull
+#define DCORE2_RTR5_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR5_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR5_LBW_WR_RQ_LL_STAT_BASE 0x456C480ull
+#define DCORE2_RTR5_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR5_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR5_LBW_WR_RS_LL_STAT_BASE 0x456C4C0ull
+#define DCORE2_RTR5_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR5_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR5_HBW_MFIFO_BASE 0x456C500ull
+#define DCORE2_RTR5_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE2_RTR5_HBW_MFIFO_SECTION 0x4000
+#define mmDCORE2_RTR5_E2E_RD_LL_STAT_BASE 0x456C540ull
+#define DCORE2_RTR5_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR5_E2E_RD_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR5_E2E_WR_LL_STAT_BASE 0x456C580ull
+#define DCORE2_RTR5_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR5_E2E_WR_LL_STAT_SECTION 0x8000
+#define mmDCORE2_RTR5_RTR_HBW_XACT_STAT_BASE 0x456C600ull
+#define DCORE2_RTR5_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR5_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE2_RTR5_RTR_LBW_XACT_STAT_BASE 0x456C680ull
+#define DCORE2_RTR5_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR5_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE2_RTR5_RTR_E2E_XACT_STAT_BASE 0x456C700ull
+#define DCORE2_RTR5_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR5_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define mmDCORE2_RTR5_SPECIAL_BASE 0x456CE80ull
+#define DCORE2_RTR5_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR5_SPECIAL_SECTION 0x1800
+#define mmDCORE2_RTR5_DBG_ADDR_BASE 0x456D000ull
+#define DCORE2_RTR5_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE2_RTR5_DBG_ADDR_SECTION 0xE800
+#define mmDCORE2_RTR5_DBG_ADDR_SPECIAL_BASE 0x456DE80ull
+#define DCORE2_RTR5_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR5_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define mmDCORE2_RTR6_CTRL_BASE 0x4570000ull
+#define DCORE2_RTR6_CTRL_MAX_OFFSET 0x1000
+#define DCORE2_RTR6_CTRL_SECTION 0xE800
+#define mmDCORE2_RTR6_CTRL_SPECIAL_BASE 0x4570E80ull
+#define DCORE2_RTR6_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR6_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE2_RTR6_H3_BASE 0x4571000ull
+#define DCORE2_RTR6_H3_MAX_OFFSET 0x1000
+#define DCORE2_RTR6_H3_SECTION 0xE800
+#define mmDCORE2_RTR6_H3_SPECIAL_BASE 0x4571E80ull
+#define DCORE2_RTR6_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR6_H3_SPECIAL_SECTION 0x1800
+#define mmDCORE2_RTR6_MSTR_IF_RR_SHRD_HBW_BASE 0x4572000ull
+#define DCORE2_RTR6_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_RTR6_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE2_RTR6_MSTR_IF_RR_PRVT_HBW_BASE 0x4572200ull
+#define DCORE2_RTR6_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_RTR6_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE2_RTR6_MSTR_IF_RR_SHRD_LBW_BASE 0x4572400ull
+#define DCORE2_RTR6_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_RTR6_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE2_RTR6_MSTR_IF_RR_PRVT_LBW_BASE 0x4572600ull
+#define DCORE2_RTR6_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_RTR6_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE2_RTR6_MSTR_IF_E2E_CRDT_BASE 0x4572800ull
+#define DCORE2_RTR6_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_RTR6_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE2_RTR6_MSTR_IF_AXUSER_BASE 0x4572A80ull
+#define DCORE2_RTR6_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_RTR6_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE2_RTR6_MSTR_IF_DBG_HBW_BASE 0x4572B00ull
+#define DCORE2_RTR6_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_RTR6_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_RTR6_MSTR_IF_DBG_LBW_BASE 0x4572B80ull
+#define DCORE2_RTR6_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_RTR6_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE2_RTR6_MSTR_IF_CORE_HBW_BASE 0x4572C00ull
+#define DCORE2_RTR6_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_RTR6_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE2_RTR6_MSTR_IF_CORE_LBW_BASE 0x4572D80ull
+#define DCORE2_RTR6_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_RTR6_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE2_RTR6_MSTR_IF_SPECIAL_BASE 0x4572E80ull
+#define DCORE2_RTR6_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR6_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE2_RTR6_ADD_DEC_HBW_BASE 0x4573000ull
+#define DCORE2_RTR6_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE2_RTR6_ADD_DEC_HBW_SECTION 0x4000
+#define mmDCORE2_RTR6_ADD_DEC_LBW_BASE 0x4573400ull
+#define DCORE2_RTR6_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE2_RTR6_ADD_DEC_LBW_SECTION 0xA800
+#define mmDCORE2_RTR6_ADD_DEC_SPECIAL_BASE 0x4573E80ull
+#define DCORE2_RTR6_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR6_ADD_DEC_SPECIAL_SECTION 0x1800
+#define mmDCORE2_RTR6_BASE 0x4574000ull
+#define DCORE2_RTR6_MAX_OFFSET 0x1000
+#define DCORE2_RTR6_SECTION 0x3000
+#define mmDCORE2_RTR6_HBW_RD_RQ_LL_STAT_BASE 0x4574300ull
+#define DCORE2_RTR6_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR6_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR6_HBW_RD_RS_LL_STAT_BASE 0x4574340ull
+#define DCORE2_RTR6_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR6_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR6_HBW_WR_RQ_LL_STAT_BASE 0x4574380ull
+#define DCORE2_RTR6_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR6_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR6_HBW_WR_RS_LL_STAT_BASE 0x45743C0ull
+#define DCORE2_RTR6_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR6_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR6_LBW_RD_RQ_LL_STAT_BASE 0x4574400ull
+#define DCORE2_RTR6_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR6_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR6_LBW_RD_RS_LL_STAT_BASE 0x4574440ull
+#define DCORE2_RTR6_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR6_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR6_LBW_WR_RQ_LL_STAT_BASE 0x4574480ull
+#define DCORE2_RTR6_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR6_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR6_LBW_WR_RS_LL_STAT_BASE 0x45744C0ull
+#define DCORE2_RTR6_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR6_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR6_HBW_MFIFO_BASE 0x4574500ull
+#define DCORE2_RTR6_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE2_RTR6_HBW_MFIFO_SECTION 0x4000
+#define mmDCORE2_RTR6_E2E_RD_LL_STAT_BASE 0x4574540ull
+#define DCORE2_RTR6_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR6_E2E_RD_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR6_E2E_WR_LL_STAT_BASE 0x4574580ull
+#define DCORE2_RTR6_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR6_E2E_WR_LL_STAT_SECTION 0x8000
+#define mmDCORE2_RTR6_RTR_HBW_XACT_STAT_BASE 0x4574600ull
+#define DCORE2_RTR6_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR6_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE2_RTR6_RTR_LBW_XACT_STAT_BASE 0x4574680ull
+#define DCORE2_RTR6_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR6_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE2_RTR6_RTR_E2E_XACT_STAT_BASE 0x4574700ull
+#define DCORE2_RTR6_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR6_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define mmDCORE2_RTR6_SPECIAL_BASE 0x4574E80ull
+#define DCORE2_RTR6_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR6_SPECIAL_SECTION 0x1800
+#define mmDCORE2_RTR6_DBG_ADDR_BASE 0x4575000ull
+#define DCORE2_RTR6_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE2_RTR6_DBG_ADDR_SECTION 0xE800
+#define mmDCORE2_RTR6_DBG_ADDR_SPECIAL_BASE 0x4575E80ull
+#define DCORE2_RTR6_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR6_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define mmDCORE2_RTR7_CTRL_BASE 0x4578000ull
+#define DCORE2_RTR7_CTRL_MAX_OFFSET 0x1000
+#define DCORE2_RTR7_CTRL_SECTION 0xE800
+#define mmDCORE2_RTR7_CTRL_SPECIAL_BASE 0x4578E80ull
+#define DCORE2_RTR7_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR7_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE2_RTR7_H3_BASE 0x4579000ull
+#define DCORE2_RTR7_H3_MAX_OFFSET 0x1000
+#define DCORE2_RTR7_H3_SECTION 0xE800
+#define mmDCORE2_RTR7_H3_SPECIAL_BASE 0x4579E80ull
+#define DCORE2_RTR7_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR7_H3_SPECIAL_SECTION 0x1800
+#define mmDCORE2_RTR7_MSTR_IF_RR_SHRD_HBW_BASE 0x457A000ull
+#define DCORE2_RTR7_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_RTR7_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE2_RTR7_MSTR_IF_RR_PRVT_HBW_BASE 0x457A200ull
+#define DCORE2_RTR7_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_RTR7_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE2_RTR7_MSTR_IF_RR_SHRD_LBW_BASE 0x457A400ull
+#define DCORE2_RTR7_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_RTR7_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE2_RTR7_MSTR_IF_RR_PRVT_LBW_BASE 0x457A600ull
+#define DCORE2_RTR7_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_RTR7_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE2_RTR7_MSTR_IF_E2E_CRDT_BASE 0x457A800ull
+#define DCORE2_RTR7_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_RTR7_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE2_RTR7_MSTR_IF_AXUSER_BASE 0x457AA80ull
+#define DCORE2_RTR7_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_RTR7_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE2_RTR7_MSTR_IF_DBG_HBW_BASE 0x457AB00ull
+#define DCORE2_RTR7_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_RTR7_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_RTR7_MSTR_IF_DBG_LBW_BASE 0x457AB80ull
+#define DCORE2_RTR7_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_RTR7_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE2_RTR7_MSTR_IF_CORE_HBW_BASE 0x457AC00ull
+#define DCORE2_RTR7_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_RTR7_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE2_RTR7_MSTR_IF_CORE_LBW_BASE 0x457AD80ull
+#define DCORE2_RTR7_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_RTR7_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE2_RTR7_MSTR_IF_SPECIAL_BASE 0x457AE80ull
+#define DCORE2_RTR7_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR7_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE2_RTR7_ADD_DEC_HBW_BASE 0x457B000ull
+#define DCORE2_RTR7_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE2_RTR7_ADD_DEC_HBW_SECTION 0x4000
+#define mmDCORE2_RTR7_ADD_DEC_LBW_BASE 0x457B400ull
+#define DCORE2_RTR7_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE2_RTR7_ADD_DEC_LBW_SECTION 0xA800
+#define mmDCORE2_RTR7_ADD_DEC_SPECIAL_BASE 0x457BE80ull
+#define DCORE2_RTR7_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR7_ADD_DEC_SPECIAL_SECTION 0x1800
+#define mmDCORE2_RTR7_BASE 0x457C000ull
+#define DCORE2_RTR7_MAX_OFFSET 0x1000
+#define DCORE2_RTR7_SECTION 0x3000
+#define mmDCORE2_RTR7_HBW_RD_RQ_LL_STAT_BASE 0x457C300ull
+#define DCORE2_RTR7_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR7_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR7_HBW_RD_RS_LL_STAT_BASE 0x457C340ull
+#define DCORE2_RTR7_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR7_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR7_HBW_WR_RQ_LL_STAT_BASE 0x457C380ull
+#define DCORE2_RTR7_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR7_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR7_HBW_WR_RS_LL_STAT_BASE 0x457C3C0ull
+#define DCORE2_RTR7_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR7_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR7_LBW_RD_RQ_LL_STAT_BASE 0x457C400ull
+#define DCORE2_RTR7_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR7_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR7_LBW_RD_RS_LL_STAT_BASE 0x457C440ull
+#define DCORE2_RTR7_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR7_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR7_LBW_WR_RQ_LL_STAT_BASE 0x457C480ull
+#define DCORE2_RTR7_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR7_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR7_LBW_WR_RS_LL_STAT_BASE 0x457C4C0ull
+#define DCORE2_RTR7_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR7_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR7_HBW_MFIFO_BASE 0x457C500ull
+#define DCORE2_RTR7_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE2_RTR7_HBW_MFIFO_SECTION 0x4000
+#define mmDCORE2_RTR7_E2E_RD_LL_STAT_BASE 0x457C540ull
+#define DCORE2_RTR7_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR7_E2E_RD_LL_STAT_SECTION 0x4000
+#define mmDCORE2_RTR7_E2E_WR_LL_STAT_BASE 0x457C580ull
+#define DCORE2_RTR7_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE2_RTR7_E2E_WR_LL_STAT_SECTION 0x8000
+#define mmDCORE2_RTR7_RTR_HBW_XACT_STAT_BASE 0x457C600ull
+#define DCORE2_RTR7_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR7_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE2_RTR7_RTR_LBW_XACT_STAT_BASE 0x457C680ull
+#define DCORE2_RTR7_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR7_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE2_RTR7_RTR_E2E_XACT_STAT_BASE 0x457C700ull
+#define DCORE2_RTR7_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE2_RTR7_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define mmDCORE2_RTR7_SPECIAL_BASE 0x457CE80ull
+#define DCORE2_RTR7_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR7_SPECIAL_SECTION 0x1800
+#define mmDCORE2_RTR7_DBG_ADDR_BASE 0x457D000ull
+#define DCORE2_RTR7_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE2_RTR7_DBG_ADDR_SECTION 0xE800
+#define mmDCORE2_RTR7_DBG_ADDR_SPECIAL_BASE 0x457DE80ull
+#define DCORE2_RTR7_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_RTR7_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define mmDCORE2_SRAM0_BANK_BASE 0x4580000ull
+#define DCORE2_SRAM0_BANK_MAX_OFFSET 0x1000
+#define DCORE2_SRAM0_BANK_SECTION 0xE800
+#define mmDCORE2_SRAM0_BANK_SPECIAL_BASE 0x4580E80ull
+#define DCORE2_SRAM0_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM0_BANK_SPECIAL_SECTION 0x1800
+#define mmDCORE2_SRAM0_RTR_BASE 0x4581000ull
+#define DCORE2_SRAM0_RTR_MAX_OFFSET 0x1000
+#define DCORE2_SRAM0_RTR_SECTION 0xE800
+#define mmDCORE2_SRAM0_RTR_SPECIAL_BASE 0x4581E80ull
+#define DCORE2_SRAM0_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM0_RTR_SPECIAL_SECTION 0x1800
+#define mmDCORE2_SRAM0_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4582000ull
+#define DCORE2_SRAM0_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM0_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM0_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4582100ull
+#define DCORE2_SRAM0_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM0_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4582200ull
+#define DCORE2_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4582300ull
+#define DCORE2_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM0_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4582400ull
+#define DCORE2_SRAM0_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM0_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM0_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4582500ull
+#define DCORE2_SRAM0_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM0_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM0_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4582600ull
+#define DCORE2_SRAM0_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM0_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4582700ull
+#define DCORE2_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4582780ull
+#define DCORE2_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4582800ull
+#define DCORE2_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4582880ull
+#define DCORE2_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4582900ull
+#define DCORE2_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4582980ull
+#define DCORE2_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4582A00ull
+#define DCORE2_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4582A80ull
+#define DCORE2_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define mmDCORE2_SRAM0_DBG_CNT_SPECIAL_BASE 0x4582E80ull
+#define DCORE2_SRAM0_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM0_DBG_CNT_SPECIAL_SECTION 0x5180
+#define mmDCORE2_SRAM1_BANK_BASE 0x4588000ull
+#define DCORE2_SRAM1_BANK_MAX_OFFSET 0x1000
+#define DCORE2_SRAM1_BANK_SECTION 0xE800
+#define mmDCORE2_SRAM1_BANK_SPECIAL_BASE 0x4588E80ull
+#define DCORE2_SRAM1_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM1_BANK_SPECIAL_SECTION 0x1800
+#define mmDCORE2_SRAM1_RTR_BASE 0x4589000ull
+#define DCORE2_SRAM1_RTR_MAX_OFFSET 0x1000
+#define DCORE2_SRAM1_RTR_SECTION 0xE800
+#define mmDCORE2_SRAM1_RTR_SPECIAL_BASE 0x4589E80ull
+#define DCORE2_SRAM1_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM1_RTR_SPECIAL_SECTION 0x1800
+#define mmDCORE2_SRAM1_DBG_CNT_N_HBW_DBG_CNT_BASE 0x458A000ull
+#define DCORE2_SRAM1_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM1_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM1_DBG_CNT_S_HBW_DBG_CNT_BASE 0x458A100ull
+#define DCORE2_SRAM1_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM1_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x458A200ull
+#define DCORE2_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x458A300ull
+#define DCORE2_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM1_DBG_CNT_N_LBW_DBG_CNT_BASE 0x458A400ull
+#define DCORE2_SRAM1_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM1_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM1_DBG_CNT_S_LBW_DBG_CNT_BASE 0x458A500ull
+#define DCORE2_SRAM1_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM1_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM1_DBG_CNT_L_LBW_DBG_CNT_BASE 0x458A600ull
+#define DCORE2_SRAM1_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM1_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x458A700ull
+#define DCORE2_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x458A780ull
+#define DCORE2_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x458A800ull
+#define DCORE2_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x458A880ull
+#define DCORE2_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x458A900ull
+#define DCORE2_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x458A980ull
+#define DCORE2_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x458AA00ull
+#define DCORE2_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x458AA80ull
+#define DCORE2_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define mmDCORE2_SRAM1_DBG_CNT_SPECIAL_BASE 0x458AE80ull
+#define DCORE2_SRAM1_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM1_DBG_CNT_SPECIAL_SECTION 0x5180
+#define mmDCORE2_SRAM2_BANK_BASE 0x4590000ull
+#define DCORE2_SRAM2_BANK_MAX_OFFSET 0x1000
+#define DCORE2_SRAM2_BANK_SECTION 0xE800
+#define mmDCORE2_SRAM2_BANK_SPECIAL_BASE 0x4590E80ull
+#define DCORE2_SRAM2_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM2_BANK_SPECIAL_SECTION 0x1800
+#define mmDCORE2_SRAM2_RTR_BASE 0x4591000ull
+#define DCORE2_SRAM2_RTR_MAX_OFFSET 0x1000
+#define DCORE2_SRAM2_RTR_SECTION 0xE800
+#define mmDCORE2_SRAM2_RTR_SPECIAL_BASE 0x4591E80ull
+#define DCORE2_SRAM2_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM2_RTR_SPECIAL_SECTION 0x1800
+#define mmDCORE2_SRAM2_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4592000ull
+#define DCORE2_SRAM2_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM2_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM2_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4592100ull
+#define DCORE2_SRAM2_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM2_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4592200ull
+#define DCORE2_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4592300ull
+#define DCORE2_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM2_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4592400ull
+#define DCORE2_SRAM2_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM2_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM2_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4592500ull
+#define DCORE2_SRAM2_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM2_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM2_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4592600ull
+#define DCORE2_SRAM2_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM2_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4592700ull
+#define DCORE2_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4592780ull
+#define DCORE2_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4592800ull
+#define DCORE2_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4592880ull
+#define DCORE2_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4592900ull
+#define DCORE2_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4592980ull
+#define DCORE2_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4592A00ull
+#define DCORE2_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4592A80ull
+#define DCORE2_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define mmDCORE2_SRAM2_DBG_CNT_SPECIAL_BASE 0x4592E80ull
+#define DCORE2_SRAM2_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM2_DBG_CNT_SPECIAL_SECTION 0x5180
+#define mmDCORE2_SRAM3_BANK_BASE 0x4598000ull
+#define DCORE2_SRAM3_BANK_MAX_OFFSET 0x1000
+#define DCORE2_SRAM3_BANK_SECTION 0xE800
+#define mmDCORE2_SRAM3_BANK_SPECIAL_BASE 0x4598E80ull
+#define DCORE2_SRAM3_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM3_BANK_SPECIAL_SECTION 0x1800
+#define mmDCORE2_SRAM3_RTR_BASE 0x4599000ull
+#define DCORE2_SRAM3_RTR_MAX_OFFSET 0x1000
+#define DCORE2_SRAM3_RTR_SECTION 0xE800
+#define mmDCORE2_SRAM3_RTR_SPECIAL_BASE 0x4599E80ull
+#define DCORE2_SRAM3_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM3_RTR_SPECIAL_SECTION 0x1800
+#define mmDCORE2_SRAM3_DBG_CNT_N_HBW_DBG_CNT_BASE 0x459A000ull
+#define DCORE2_SRAM3_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM3_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM3_DBG_CNT_S_HBW_DBG_CNT_BASE 0x459A100ull
+#define DCORE2_SRAM3_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM3_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x459A200ull
+#define DCORE2_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x459A300ull
+#define DCORE2_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM3_DBG_CNT_N_LBW_DBG_CNT_BASE 0x459A400ull
+#define DCORE2_SRAM3_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM3_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM3_DBG_CNT_S_LBW_DBG_CNT_BASE 0x459A500ull
+#define DCORE2_SRAM3_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM3_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM3_DBG_CNT_L_LBW_DBG_CNT_BASE 0x459A600ull
+#define DCORE2_SRAM3_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM3_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x459A700ull
+#define DCORE2_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x459A780ull
+#define DCORE2_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x459A800ull
+#define DCORE2_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x459A880ull
+#define DCORE2_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x459A900ull
+#define DCORE2_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x459A980ull
+#define DCORE2_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x459AA00ull
+#define DCORE2_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x459AA80ull
+#define DCORE2_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define mmDCORE2_SRAM3_DBG_CNT_SPECIAL_BASE 0x459AE80ull
+#define DCORE2_SRAM3_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM3_DBG_CNT_SPECIAL_SECTION 0x5180
+#define mmDCORE2_SRAM4_BANK_BASE 0x45A0000ull
+#define DCORE2_SRAM4_BANK_MAX_OFFSET 0x1000
+#define DCORE2_SRAM4_BANK_SECTION 0xE800
+#define mmDCORE2_SRAM4_BANK_SPECIAL_BASE 0x45A0E80ull
+#define DCORE2_SRAM4_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM4_BANK_SPECIAL_SECTION 0x1800
+#define mmDCORE2_SRAM4_RTR_BASE 0x45A1000ull
+#define DCORE2_SRAM4_RTR_MAX_OFFSET 0x1000
+#define DCORE2_SRAM4_RTR_SECTION 0xE800
+#define mmDCORE2_SRAM4_RTR_SPECIAL_BASE 0x45A1E80ull
+#define DCORE2_SRAM4_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM4_RTR_SPECIAL_SECTION 0x1800
+#define mmDCORE2_SRAM4_DBG_CNT_N_HBW_DBG_CNT_BASE 0x45A2000ull
+#define DCORE2_SRAM4_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM4_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM4_DBG_CNT_S_HBW_DBG_CNT_BASE 0x45A2100ull
+#define DCORE2_SRAM4_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM4_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x45A2200ull
+#define DCORE2_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x45A2300ull
+#define DCORE2_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM4_DBG_CNT_N_LBW_DBG_CNT_BASE 0x45A2400ull
+#define DCORE2_SRAM4_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM4_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM4_DBG_CNT_S_LBW_DBG_CNT_BASE 0x45A2500ull
+#define DCORE2_SRAM4_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM4_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM4_DBG_CNT_L_LBW_DBG_CNT_BASE 0x45A2600ull
+#define DCORE2_SRAM4_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM4_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x45A2700ull
+#define DCORE2_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x45A2780ull
+#define DCORE2_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x45A2800ull
+#define DCORE2_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x45A2880ull
+#define DCORE2_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x45A2900ull
+#define DCORE2_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x45A2980ull
+#define DCORE2_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x45A2A00ull
+#define DCORE2_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x45A2A80ull
+#define DCORE2_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define mmDCORE2_SRAM4_DBG_CNT_SPECIAL_BASE 0x45A2E80ull
+#define DCORE2_SRAM4_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM4_DBG_CNT_SPECIAL_SECTION 0x5180
+#define mmDCORE2_SRAM5_BANK_BASE 0x45A8000ull
+#define DCORE2_SRAM5_BANK_MAX_OFFSET 0x1000
+#define DCORE2_SRAM5_BANK_SECTION 0xE800
+#define mmDCORE2_SRAM5_BANK_SPECIAL_BASE 0x45A8E80ull
+#define DCORE2_SRAM5_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM5_BANK_SPECIAL_SECTION 0x1800
+#define mmDCORE2_SRAM5_RTR_BASE 0x45A9000ull
+#define DCORE2_SRAM5_RTR_MAX_OFFSET 0x1000
+#define DCORE2_SRAM5_RTR_SECTION 0xE800
+#define mmDCORE2_SRAM5_RTR_SPECIAL_BASE 0x45A9E80ull
+#define DCORE2_SRAM5_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM5_RTR_SPECIAL_SECTION 0x1800
+#define mmDCORE2_SRAM5_DBG_CNT_N_HBW_DBG_CNT_BASE 0x45AA000ull
+#define DCORE2_SRAM5_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM5_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM5_DBG_CNT_S_HBW_DBG_CNT_BASE 0x45AA100ull
+#define DCORE2_SRAM5_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM5_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x45AA200ull
+#define DCORE2_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x45AA300ull
+#define DCORE2_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM5_DBG_CNT_N_LBW_DBG_CNT_BASE 0x45AA400ull
+#define DCORE2_SRAM5_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM5_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM5_DBG_CNT_S_LBW_DBG_CNT_BASE 0x45AA500ull
+#define DCORE2_SRAM5_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM5_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM5_DBG_CNT_L_LBW_DBG_CNT_BASE 0x45AA600ull
+#define DCORE2_SRAM5_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM5_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x45AA700ull
+#define DCORE2_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x45AA780ull
+#define DCORE2_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x45AA800ull
+#define DCORE2_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x45AA880ull
+#define DCORE2_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x45AA900ull
+#define DCORE2_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x45AA980ull
+#define DCORE2_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x45AAA00ull
+#define DCORE2_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x45AAA80ull
+#define DCORE2_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define mmDCORE2_SRAM5_DBG_CNT_SPECIAL_BASE 0x45AAE80ull
+#define DCORE2_SRAM5_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM5_DBG_CNT_SPECIAL_SECTION 0x5180
+#define mmDCORE2_SRAM6_BANK_BASE 0x45B0000ull
+#define DCORE2_SRAM6_BANK_MAX_OFFSET 0x1000
+#define DCORE2_SRAM6_BANK_SECTION 0xE800
+#define mmDCORE2_SRAM6_BANK_SPECIAL_BASE 0x45B0E80ull
+#define DCORE2_SRAM6_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM6_BANK_SPECIAL_SECTION 0x1800
+#define mmDCORE2_SRAM6_RTR_BASE 0x45B1000ull
+#define DCORE2_SRAM6_RTR_MAX_OFFSET 0x1000
+#define DCORE2_SRAM6_RTR_SECTION 0xE800
+#define mmDCORE2_SRAM6_RTR_SPECIAL_BASE 0x45B1E80ull
+#define DCORE2_SRAM6_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM6_RTR_SPECIAL_SECTION 0x1800
+#define mmDCORE2_SRAM6_DBG_CNT_N_HBW_DBG_CNT_BASE 0x45B2000ull
+#define DCORE2_SRAM6_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM6_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM6_DBG_CNT_S_HBW_DBG_CNT_BASE 0x45B2100ull
+#define DCORE2_SRAM6_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM6_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x45B2200ull
+#define DCORE2_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x45B2300ull
+#define DCORE2_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM6_DBG_CNT_N_LBW_DBG_CNT_BASE 0x45B2400ull
+#define DCORE2_SRAM6_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM6_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM6_DBG_CNT_S_LBW_DBG_CNT_BASE 0x45B2500ull
+#define DCORE2_SRAM6_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM6_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM6_DBG_CNT_L_LBW_DBG_CNT_BASE 0x45B2600ull
+#define DCORE2_SRAM6_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM6_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x45B2700ull
+#define DCORE2_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x45B2780ull
+#define DCORE2_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x45B2800ull
+#define DCORE2_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x45B2880ull
+#define DCORE2_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x45B2900ull
+#define DCORE2_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x45B2980ull
+#define DCORE2_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x45B2A00ull
+#define DCORE2_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x45B2A80ull
+#define DCORE2_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define mmDCORE2_SRAM6_DBG_CNT_SPECIAL_BASE 0x45B2E80ull
+#define DCORE2_SRAM6_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM6_DBG_CNT_SPECIAL_SECTION 0x5180
+#define mmDCORE2_SRAM7_BANK_BASE 0x45B8000ull
+#define DCORE2_SRAM7_BANK_MAX_OFFSET 0x1000
+#define DCORE2_SRAM7_BANK_SECTION 0xE800
+#define mmDCORE2_SRAM7_BANK_SPECIAL_BASE 0x45B8E80ull
+#define DCORE2_SRAM7_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM7_BANK_SPECIAL_SECTION 0x1800
+#define mmDCORE2_SRAM7_RTR_BASE 0x45B9000ull
+#define DCORE2_SRAM7_RTR_MAX_OFFSET 0x1000
+#define DCORE2_SRAM7_RTR_SECTION 0xE800
+#define mmDCORE2_SRAM7_RTR_SPECIAL_BASE 0x45B9E80ull
+#define DCORE2_SRAM7_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM7_RTR_SPECIAL_SECTION 0x1800
+#define mmDCORE2_SRAM7_DBG_CNT_N_HBW_DBG_CNT_BASE 0x45BA000ull
+#define DCORE2_SRAM7_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM7_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM7_DBG_CNT_S_HBW_DBG_CNT_BASE 0x45BA100ull
+#define DCORE2_SRAM7_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM7_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x45BA200ull
+#define DCORE2_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x45BA300ull
+#define DCORE2_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM7_DBG_CNT_N_LBW_DBG_CNT_BASE 0x45BA400ull
+#define DCORE2_SRAM7_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM7_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM7_DBG_CNT_S_LBW_DBG_CNT_BASE 0x45BA500ull
+#define DCORE2_SRAM7_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM7_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM7_DBG_CNT_L_LBW_DBG_CNT_BASE 0x45BA600ull
+#define DCORE2_SRAM7_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE2_SRAM7_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE2_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x45BA700ull
+#define DCORE2_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x45BA780ull
+#define DCORE2_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x45BA800ull
+#define DCORE2_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x45BA880ull
+#define DCORE2_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x45BA900ull
+#define DCORE2_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x45BA980ull
+#define DCORE2_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x45BAA00ull
+#define DCORE2_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE2_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x45BAA80ull
+#define DCORE2_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE2_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define mmDCORE2_SRAM7_DBG_CNT_SPECIAL_BASE 0x45BAE80ull
+#define DCORE2_SRAM7_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_SRAM7_DBG_CNT_SPECIAL_SECTION 0x5180
+#define mmDCORE2_EDMA0_QM_DCCM_BASE 0x45C0000ull
+#define DCORE2_EDMA0_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE2_EDMA0_QM_DCCM_SECTION 0x8000
+#define mmDCORE2_EDMA0_QM_ARC_AUX_BASE 0x45C8000ull
+#define DCORE2_EDMA0_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE2_EDMA0_QM_ARC_AUX_SECTION 0xE800
+#define mmDCORE2_EDMA0_QM_ARC_AUX_SPECIAL_BASE 0x45C8E80ull
+#define DCORE2_EDMA0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_EDMA0_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define mmDCORE2_EDMA0_QM_BASE 0x45CA000ull
+#define DCORE2_EDMA0_QM_MAX_OFFSET 0x1000
+#define DCORE2_EDMA0_QM_SECTION 0x9000
+#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x45CA900ull
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x45CA908ull
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x45CA910ull
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x45CA918ull
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x45CA920ull
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x45CA928ull
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x45CA930ull
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x45CA938ull
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x45CA940ull
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x45CA948ull
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x45CA950ull
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x45CA958ull
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x45CA960ull
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x45CA968ull
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x45CA970ull
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x45CA978ull
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE2_EDMA0_QM_AXUSER_SECURED_BASE 0x45CAB00ull
+#define DCORE2_EDMA0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE2_EDMA0_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE2_EDMA0_QM_AXUSER_NONSECURED_BASE 0x45CAB80ull
+#define DCORE2_EDMA0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE2_EDMA0_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE2_EDMA0_QM_DBG_HBW_BASE 0x45CAC00ull
+#define DCORE2_EDMA0_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_EDMA0_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_EDMA0_QM_DBG_LBW_BASE 0x45CAC80ull
+#define DCORE2_EDMA0_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_EDMA0_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE2_EDMA0_QM_CGM_BASE 0x45CAD80ull
+#define DCORE2_EDMA0_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE2_EDMA0_QM_CGM_SECTION 0x1000
+#define mmDCORE2_EDMA0_QM_SPECIAL_BASE 0x45CAE80ull
+#define DCORE2_EDMA0_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_EDMA0_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE2_EDMA0_CORE_BASE 0x45CB000ull
+#define DCORE2_EDMA0_CORE_MAX_OFFSET 0x1000
+#define DCORE2_EDMA0_CORE_SECTION 0x8000
+#define mmDCORE2_EDMA0_CORE_CTX_AXUSER_BASE 0x45CB800ull
+#define DCORE2_EDMA0_CORE_CTX_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_EDMA0_CORE_CTX_AXUSER_SECTION 0x6000
+#define mmDCORE2_EDMA0_CORE_CTX_BASE 0x45CB860ull
+#define DCORE2_EDMA0_CORE_CTX_MAX_OFFSET 0x9000
+#define DCORE2_EDMA0_CORE_CTX_SECTION 0x5A00
+#define mmDCORE2_EDMA0_CORE_KDMA_CGM_BASE 0x45CBE00ull
+#define DCORE2_EDMA0_CORE_KDMA_CGM_MAX_OFFSET 0xC000
+#define DCORE2_EDMA0_CORE_KDMA_CGM_SECTION 0x8000
+#define mmDCORE2_EDMA0_CORE_SPECIAL_BASE 0x45CBE80ull
+#define DCORE2_EDMA0_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_EDMA0_CORE_SPECIAL_SECTION 0x1800
+#define mmDCORE2_EDMA0_MSTR_IF_RR_SHRD_HBW_BASE 0x45CC000ull
+#define DCORE2_EDMA0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_EDMA0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE2_EDMA0_MSTR_IF_RR_PRVT_HBW_BASE 0x45CC200ull
+#define DCORE2_EDMA0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_EDMA0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE2_EDMA0_MSTR_IF_RR_SHRD_LBW_BASE 0x45CC400ull
+#define DCORE2_EDMA0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_EDMA0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE2_EDMA0_MSTR_IF_RR_PRVT_LBW_BASE 0x45CC600ull
+#define DCORE2_EDMA0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_EDMA0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE2_EDMA0_MSTR_IF_E2E_CRDT_BASE 0x45CC800ull
+#define DCORE2_EDMA0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_EDMA0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE2_EDMA0_MSTR_IF_AXUSER_BASE 0x45CCA80ull
+#define DCORE2_EDMA0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_EDMA0_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE2_EDMA0_MSTR_IF_DBG_HBW_BASE 0x45CCB00ull
+#define DCORE2_EDMA0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_EDMA0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_EDMA0_MSTR_IF_DBG_LBW_BASE 0x45CCB80ull
+#define DCORE2_EDMA0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_EDMA0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE2_EDMA0_MSTR_IF_CORE_HBW_BASE 0x45CCC00ull
+#define DCORE2_EDMA0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_EDMA0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE2_EDMA0_MSTR_IF_CORE_LBW_BASE 0x45CCD80ull
+#define DCORE2_EDMA0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_EDMA0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE2_EDMA0_MSTR_IF_SPECIAL_BASE 0x45CCE80ull
+#define DCORE2_EDMA0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_EDMA0_MSTR_IF_SPECIAL_SECTION 0x3180
+#define mmDCORE2_EDMA1_QM_DCCM_BASE 0x45D0000ull
+#define DCORE2_EDMA1_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE2_EDMA1_QM_DCCM_SECTION 0x8000
+#define mmDCORE2_EDMA1_QM_ARC_AUX_BASE 0x45D8000ull
+#define DCORE2_EDMA1_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE2_EDMA1_QM_ARC_AUX_SECTION 0xE800
+#define mmDCORE2_EDMA1_QM_ARC_AUX_SPECIAL_BASE 0x45D8E80ull
+#define DCORE2_EDMA1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_EDMA1_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define mmDCORE2_EDMA1_QM_BASE 0x45DA000ull
+#define DCORE2_EDMA1_QM_MAX_OFFSET 0x1000
+#define DCORE2_EDMA1_QM_SECTION 0x9000
+#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x45DA900ull
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x45DA908ull
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x45DA910ull
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x45DA918ull
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x45DA920ull
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x45DA928ull
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x45DA930ull
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x45DA938ull
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x45DA940ull
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x45DA948ull
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x45DA950ull
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x45DA958ull
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x45DA960ull
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x45DA968ull
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x45DA970ull
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x45DA978ull
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE2_EDMA1_QM_AXUSER_SECURED_BASE 0x45DAB00ull
+#define DCORE2_EDMA1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE2_EDMA1_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE2_EDMA1_QM_AXUSER_NONSECURED_BASE 0x45DAB80ull
+#define DCORE2_EDMA1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE2_EDMA1_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE2_EDMA1_QM_DBG_HBW_BASE 0x45DAC00ull
+#define DCORE2_EDMA1_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_EDMA1_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_EDMA1_QM_DBG_LBW_BASE 0x45DAC80ull
+#define DCORE2_EDMA1_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_EDMA1_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE2_EDMA1_QM_CGM_BASE 0x45DAD80ull
+#define DCORE2_EDMA1_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE2_EDMA1_QM_CGM_SECTION 0x1000
+#define mmDCORE2_EDMA1_QM_SPECIAL_BASE 0x45DAE80ull
+#define DCORE2_EDMA1_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_EDMA1_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE2_EDMA1_CORE_BASE 0x45DB000ull
+#define DCORE2_EDMA1_CORE_MAX_OFFSET 0x1000
+#define DCORE2_EDMA1_CORE_SECTION 0x8000
+#define mmDCORE2_EDMA1_CORE_CTX_AXUSER_BASE 0x45DB800ull
+#define DCORE2_EDMA1_CORE_CTX_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_EDMA1_CORE_CTX_AXUSER_SECTION 0x6000
+#define mmDCORE2_EDMA1_CORE_CTX_BASE 0x45DB860ull
+#define DCORE2_EDMA1_CORE_CTX_MAX_OFFSET 0x9000
+#define DCORE2_EDMA1_CORE_CTX_SECTION 0x5A00
+#define mmDCORE2_EDMA1_CORE_KDMA_CGM_BASE 0x45DBE00ull
+#define DCORE2_EDMA1_CORE_KDMA_CGM_MAX_OFFSET 0xC000
+#define DCORE2_EDMA1_CORE_KDMA_CGM_SECTION 0x8000
+#define mmDCORE2_EDMA1_CORE_SPECIAL_BASE 0x45DBE80ull
+#define DCORE2_EDMA1_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_EDMA1_CORE_SPECIAL_SECTION 0x1800
+#define mmDCORE2_EDMA1_MSTR_IF_RR_SHRD_HBW_BASE 0x45DC000ull
+#define DCORE2_EDMA1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_EDMA1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE2_EDMA1_MSTR_IF_RR_PRVT_HBW_BASE 0x45DC200ull
+#define DCORE2_EDMA1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_EDMA1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE2_EDMA1_MSTR_IF_RR_SHRD_LBW_BASE 0x45DC400ull
+#define DCORE2_EDMA1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_EDMA1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE2_EDMA1_MSTR_IF_RR_PRVT_LBW_BASE 0x45DC600ull
+#define DCORE2_EDMA1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_EDMA1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE2_EDMA1_MSTR_IF_E2E_CRDT_BASE 0x45DC800ull
+#define DCORE2_EDMA1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_EDMA1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE2_EDMA1_MSTR_IF_AXUSER_BASE 0x45DCA80ull
+#define DCORE2_EDMA1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_EDMA1_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE2_EDMA1_MSTR_IF_DBG_HBW_BASE 0x45DCB00ull
+#define DCORE2_EDMA1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_EDMA1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_EDMA1_MSTR_IF_DBG_LBW_BASE 0x45DCB80ull
+#define DCORE2_EDMA1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_EDMA1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE2_EDMA1_MSTR_IF_CORE_HBW_BASE 0x45DCC00ull
+#define DCORE2_EDMA1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_EDMA1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE2_EDMA1_MSTR_IF_CORE_LBW_BASE 0x45DCD80ull
+#define DCORE2_EDMA1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_EDMA1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE2_EDMA1_MSTR_IF_SPECIAL_BASE 0x45DCE80ull
+#define DCORE2_EDMA1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_EDMA1_MSTR_IF_SPECIAL_SECTION 0x3180
+#define mmDCORE2_DEC0_CMD_BASE 0x45E0000ull
+#define DCORE2_DEC0_CMD_MAX_OFFSET 0x1100
+#define DCORE2_DEC0_CMD_SECTION 0x1000
+#define mmDCORE2_DEC0_VSI_BASE 0x45E1000ull
+#define DCORE2_DEC0_VSI_MAX_OFFSET 0x6FC0
+#define DCORE2_DEC0_VSI_SECTION 0x1000
+#define mmDCORE2_DEC0_L2C_BASE 0x45E2000ull
+#define DCORE2_DEC0_L2C_MAX_OFFSET 0x39C0
+#define DCORE2_DEC0_L2C_SECTION 0x1000
+#define mmDCORE2_VDEC0_BRDG_CTRL_BASE 0x45E3000ull
+#define DCORE2_VDEC0_BRDG_CTRL_MAX_OFFSET 0x1000
+#define DCORE2_VDEC0_BRDG_CTRL_SECTION 0x8000
+#define mmDCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x45E3800ull
+#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000
+#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000
+#define mmDCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x45E3900ull
+#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000
+#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000
+#define mmDCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x45E3A00ull
+#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000
+#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000
+#define mmDCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x45E3B00ull
+#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000
+#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000
+#define mmDCORE2_VDEC0_BRDG_CTRL_AXUSER_DEC_BASE 0x45E3C00ull
+#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000
+#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800
+#define mmDCORE2_VDEC0_BRDG_CTRL_SPECIAL_BASE 0x45E3E80ull
+#define DCORE2_VDEC0_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_VDEC0_BRDG_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE2_VDEC0_CTRL_BASE 0x45E4000ull
+#define DCORE2_VDEC0_CTRL_MAX_OFFSET 0x1000
+#define DCORE2_VDEC0_CTRL_SECTION 0xE800
+#define mmDCORE2_VDEC0_CTRL_SPECIAL_BASE 0x45E4E80ull
+#define DCORE2_VDEC0_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_VDEC0_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE2_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE 0x45E5000ull
+#define DCORE2_VDEC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_VDEC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE2_VDEC0_MSTR_IF_RR_PRVT_HBW_BASE 0x45E5200ull
+#define DCORE2_VDEC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_VDEC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE2_VDEC0_MSTR_IF_RR_SHRD_LBW_BASE 0x45E5400ull
+#define DCORE2_VDEC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_VDEC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE2_VDEC0_MSTR_IF_RR_PRVT_LBW_BASE 0x45E5600ull
+#define DCORE2_VDEC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_VDEC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE2_VDEC0_MSTR_IF_E2E_CRDT_BASE 0x45E5800ull
+#define DCORE2_VDEC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_VDEC0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE2_VDEC0_MSTR_IF_AXUSER_BASE 0x45E5A80ull
+#define DCORE2_VDEC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_VDEC0_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE2_VDEC0_MSTR_IF_DBG_HBW_BASE 0x45E5B00ull
+#define DCORE2_VDEC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_VDEC0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_VDEC0_MSTR_IF_DBG_LBW_BASE 0x45E5B80ull
+#define DCORE2_VDEC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_VDEC0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE2_VDEC0_MSTR_IF_CORE_HBW_BASE 0x45E5C00ull
+#define DCORE2_VDEC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_VDEC0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE2_VDEC0_MSTR_IF_CORE_LBW_BASE 0x45E5D80ull
+#define DCORE2_VDEC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_VDEC0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE2_VDEC0_MSTR_IF_SPECIAL_BASE 0x45E5E80ull
+#define DCORE2_VDEC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_VDEC0_MSTR_IF_SPECIAL_SECTION 0xA180
+#define mmDCORE2_DEC1_CMD_BASE 0x45F0000ull
+#define DCORE2_DEC1_CMD_MAX_OFFSET 0x1100
+#define DCORE2_DEC1_CMD_SECTION 0x1000
+#define mmDCORE2_DEC1_VSI_BASE 0x45F1000ull
+#define DCORE2_DEC1_VSI_MAX_OFFSET 0x6FC0
+#define DCORE2_DEC1_VSI_SECTION 0x1000
+#define mmDCORE2_DEC1_L2C_BASE 0x45F2000ull
+#define DCORE2_DEC1_L2C_MAX_OFFSET 0x39C0
+#define DCORE2_DEC1_L2C_SECTION 0x1000
+#define mmDCORE2_VDEC1_BRDG_CTRL_BASE 0x45F3000ull
+#define DCORE2_VDEC1_BRDG_CTRL_MAX_OFFSET 0x1000
+#define DCORE2_VDEC1_BRDG_CTRL_SECTION 0x8000
+#define mmDCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x45F3800ull
+#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000
+#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000
+#define mmDCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x45F3900ull
+#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000
+#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000
+#define mmDCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x45F3A00ull
+#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000
+#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000
+#define mmDCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x45F3B00ull
+#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000
+#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000
+#define mmDCORE2_VDEC1_BRDG_CTRL_AXUSER_DEC_BASE 0x45F3C00ull
+#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000
+#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800
+#define mmDCORE2_VDEC1_BRDG_CTRL_SPECIAL_BASE 0x45F3E80ull
+#define DCORE2_VDEC1_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_VDEC1_BRDG_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE2_VDEC1_CTRL_BASE 0x45F4000ull
+#define DCORE2_VDEC1_CTRL_MAX_OFFSET 0x1000
+#define DCORE2_VDEC1_CTRL_SECTION 0xE800
+#define mmDCORE2_VDEC1_CTRL_SPECIAL_BASE 0x45F4E80ull
+#define DCORE2_VDEC1_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_VDEC1_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE2_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE 0x45F5000ull
+#define DCORE2_VDEC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_VDEC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE2_VDEC1_MSTR_IF_RR_PRVT_HBW_BASE 0x45F5200ull
+#define DCORE2_VDEC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE2_VDEC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE2_VDEC1_MSTR_IF_RR_SHRD_LBW_BASE 0x45F5400ull
+#define DCORE2_VDEC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_VDEC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE2_VDEC1_MSTR_IF_RR_PRVT_LBW_BASE 0x45F5600ull
+#define DCORE2_VDEC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE2_VDEC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE2_VDEC1_MSTR_IF_E2E_CRDT_BASE 0x45F5800ull
+#define DCORE2_VDEC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE2_VDEC1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE2_VDEC1_MSTR_IF_AXUSER_BASE 0x45F5A80ull
+#define DCORE2_VDEC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE2_VDEC1_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE2_VDEC1_MSTR_IF_DBG_HBW_BASE 0x45F5B00ull
+#define DCORE2_VDEC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE2_VDEC1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE2_VDEC1_MSTR_IF_DBG_LBW_BASE 0x45F5B80ull
+#define DCORE2_VDEC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE2_VDEC1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE2_VDEC1_MSTR_IF_CORE_HBW_BASE 0x45F5C00ull
+#define DCORE2_VDEC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE2_VDEC1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE2_VDEC1_MSTR_IF_CORE_LBW_BASE 0x45F5D80ull
+#define DCORE2_VDEC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE2_VDEC1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE2_VDEC1_MSTR_IF_SPECIAL_BASE 0x45F5E80ull
+#define DCORE2_VDEC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_VDEC1_MSTR_IF_SPECIAL_SECTION 0xA180
+#define mmDCORE3_TPC0_QM_DCCM_BASE 0x4600000ull
+#define DCORE3_TPC0_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE3_TPC0_QM_DCCM_SECTION 0x8000
+#define mmDCORE3_TPC0_QM_ARC_AUX_BASE 0x4608000ull
+#define DCORE3_TPC0_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE3_TPC0_QM_ARC_AUX_SECTION 0xE800
+#define mmDCORE3_TPC0_QM_ARC_AUX_SPECIAL_BASE 0x4608E80ull
+#define DCORE3_TPC0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC0_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define mmDCORE3_TPC0_QM_BASE 0x460A000ull
+#define DCORE3_TPC0_QM_MAX_OFFSET 0x1000
+#define DCORE3_TPC0_QM_SECTION 0x9000
+#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x460A900ull
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x460A908ull
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x460A910ull
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x460A918ull
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x460A920ull
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x460A928ull
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x460A930ull
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x460A938ull
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x460A940ull
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x460A948ull
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x460A950ull
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x460A958ull
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x460A960ull
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x460A968ull
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x460A970ull
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x460A978ull
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE3_TPC0_QM_AXUSER_SECURED_BASE 0x460AB00ull
+#define DCORE3_TPC0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE3_TPC0_QM_AXUSER_NONSECURED_BASE 0x460AB80ull
+#define DCORE3_TPC0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE3_TPC0_QM_DBG_HBW_BASE 0x460AC00ull
+#define DCORE3_TPC0_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC0_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_TPC0_QM_DBG_LBW_BASE 0x460AC80ull
+#define DCORE3_TPC0_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC0_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE3_TPC0_QM_CGM_BASE 0x460AD80ull
+#define DCORE3_TPC0_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE3_TPC0_QM_CGM_SECTION 0x1000
+#define mmDCORE3_TPC0_QM_SPECIAL_BASE 0x460AE80ull
+#define DCORE3_TPC0_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC0_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_0_BASE 0x460B000ull
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE3_TPC0_CFG_BASE 0x460B000ull
+#define DCORE3_TPC0_CFG_MAX_OFFSET 0x1000
+#define DCORE3_TPC0_CFG_SECTION 0x5000
+#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_1_BASE 0x460B050ull
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_2_BASE 0x460B0A0ull
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_3_BASE 0x460B0F0ull
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_4_BASE 0x460B140ull
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_5_BASE 0x460B190ull
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_6_BASE 0x460B1E0ull
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_7_BASE 0x460B230ull
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_8_BASE 0x460B280ull
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_9_BASE 0x460B2D0ull
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_10_BASE 0x460B320ull
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_11_BASE 0x460B370ull
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_12_BASE 0x460B3C0ull
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_13_BASE 0x460B410ull
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_14_BASE 0x460B460ull
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_15_BASE 0x460B4B0ull
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE3_TPC0_CFG_KERNEL_SYNC_OBJECT_BASE 0x460B500ull
+#define DCORE3_TPC0_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE3_TPC0_CFG_KERNEL_BASE 0x460B508ull
+#define DCORE3_TPC0_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE3_TPC0_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE3_TPC0_CFG_QM_TENSOR_0_BASE 0x460B5DCull
+#define DCORE3_TPC0_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE3_TPC0_CFG_QM_TENSOR_1_BASE 0x460B62Cull
+#define DCORE3_TPC0_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE3_TPC0_CFG_QM_TENSOR_2_BASE 0x460B67Cull
+#define DCORE3_TPC0_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE3_TPC0_CFG_QM_TENSOR_3_BASE 0x460B6CCull
+#define DCORE3_TPC0_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE3_TPC0_CFG_QM_TENSOR_4_BASE 0x460B71Cull
+#define DCORE3_TPC0_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE3_TPC0_CFG_QM_TENSOR_5_BASE 0x460B76Cull
+#define DCORE3_TPC0_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE3_TPC0_CFG_QM_TENSOR_6_BASE 0x460B7BCull
+#define DCORE3_TPC0_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE3_TPC0_CFG_QM_TENSOR_7_BASE 0x460B80Cull
+#define DCORE3_TPC0_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE3_TPC0_CFG_QM_TENSOR_8_BASE 0x460B85Cull
+#define DCORE3_TPC0_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE3_TPC0_CFG_QM_TENSOR_9_BASE 0x460B8ACull
+#define DCORE3_TPC0_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE3_TPC0_CFG_QM_TENSOR_10_BASE 0x460B8FCull
+#define DCORE3_TPC0_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE3_TPC0_CFG_QM_TENSOR_11_BASE 0x460B94Cull
+#define DCORE3_TPC0_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE3_TPC0_CFG_QM_TENSOR_12_BASE 0x460B99Cull
+#define DCORE3_TPC0_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE3_TPC0_CFG_QM_TENSOR_13_BASE 0x460B9ECull
+#define DCORE3_TPC0_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE3_TPC0_CFG_QM_TENSOR_14_BASE 0x460BA3Cull
+#define DCORE3_TPC0_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE3_TPC0_CFG_QM_TENSOR_15_BASE 0x460BA8Cull
+#define DCORE3_TPC0_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE3_TPC0_CFG_QM_SYNC_OBJECT_BASE 0x460BADCull
+#define DCORE3_TPC0_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE3_TPC0_CFG_QM_BASE 0x460BAE4ull
+#define DCORE3_TPC0_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE3_TPC0_CFG_QM_SECTION 0x31C0
+#define mmDCORE3_TPC0_CFG_AXUSER_BASE 0x460BE00ull
+#define DCORE3_TPC0_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE3_TPC0_CFG_SPECIAL_BASE 0x460BE80ull
+#define DCORE3_TPC0_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC0_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE3_TPC0_MSTR_IF_RR_SHRD_HBW_BASE 0x460C000ull
+#define DCORE3_TPC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_TPC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE3_TPC0_MSTR_IF_RR_PRVT_HBW_BASE 0x460C200ull
+#define DCORE3_TPC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_TPC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE3_TPC0_MSTR_IF_RR_SHRD_LBW_BASE 0x460C400ull
+#define DCORE3_TPC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_TPC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE3_TPC0_MSTR_IF_RR_PRVT_LBW_BASE 0x460C600ull
+#define DCORE3_TPC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_TPC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE3_TPC0_MSTR_IF_E2E_CRDT_BASE 0x460C800ull
+#define DCORE3_TPC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_TPC0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE3_TPC0_MSTR_IF_AXUSER_BASE 0x460CA80ull
+#define DCORE3_TPC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_TPC0_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE3_TPC0_MSTR_IF_DBG_HBW_BASE 0x460CB00ull
+#define DCORE3_TPC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_TPC0_MSTR_IF_DBG_LBW_BASE 0x460CB80ull
+#define DCORE3_TPC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE3_TPC0_MSTR_IF_CORE_HBW_BASE 0x460CC00ull
+#define DCORE3_TPC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_TPC0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE3_TPC0_MSTR_IF_CORE_LBW_BASE 0x460CD80ull
+#define DCORE3_TPC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_TPC0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE3_TPC0_MSTR_IF_SPECIAL_BASE 0x460CE80ull
+#define DCORE3_TPC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC0_MSTR_IF_SPECIAL_SECTION 0x3180
+#define mmDCORE3_TPC1_QM_DCCM_BASE 0x4610000ull
+#define DCORE3_TPC1_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE3_TPC1_QM_DCCM_SECTION 0x8000
+#define mmDCORE3_TPC1_QM_ARC_AUX_BASE 0x4618000ull
+#define DCORE3_TPC1_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE3_TPC1_QM_ARC_AUX_SECTION 0xE800
+#define mmDCORE3_TPC1_QM_ARC_AUX_SPECIAL_BASE 0x4618E80ull
+#define DCORE3_TPC1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC1_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define mmDCORE3_TPC1_QM_BASE 0x461A000ull
+#define DCORE3_TPC1_QM_MAX_OFFSET 0x1000
+#define DCORE3_TPC1_QM_SECTION 0x9000
+#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x461A900ull
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x461A908ull
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x461A910ull
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x461A918ull
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x461A920ull
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x461A928ull
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x461A930ull
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x461A938ull
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x461A940ull
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x461A948ull
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x461A950ull
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x461A958ull
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x461A960ull
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x461A968ull
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x461A970ull
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x461A978ull
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE3_TPC1_QM_AXUSER_SECURED_BASE 0x461AB00ull
+#define DCORE3_TPC1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE3_TPC1_QM_AXUSER_NONSECURED_BASE 0x461AB80ull
+#define DCORE3_TPC1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE3_TPC1_QM_DBG_HBW_BASE 0x461AC00ull
+#define DCORE3_TPC1_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC1_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_TPC1_QM_DBG_LBW_BASE 0x461AC80ull
+#define DCORE3_TPC1_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC1_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE3_TPC1_QM_CGM_BASE 0x461AD80ull
+#define DCORE3_TPC1_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE3_TPC1_QM_CGM_SECTION 0x1000
+#define mmDCORE3_TPC1_QM_SPECIAL_BASE 0x461AE80ull
+#define DCORE3_TPC1_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC1_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_0_BASE 0x461B000ull
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE3_TPC1_CFG_BASE 0x461B000ull
+#define DCORE3_TPC1_CFG_MAX_OFFSET 0x1000
+#define DCORE3_TPC1_CFG_SECTION 0x5000
+#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_1_BASE 0x461B050ull
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_2_BASE 0x461B0A0ull
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_3_BASE 0x461B0F0ull
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_4_BASE 0x461B140ull
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_5_BASE 0x461B190ull
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_6_BASE 0x461B1E0ull
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_7_BASE 0x461B230ull
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_8_BASE 0x461B280ull
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_9_BASE 0x461B2D0ull
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_10_BASE 0x461B320ull
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_11_BASE 0x461B370ull
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_12_BASE 0x461B3C0ull
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_13_BASE 0x461B410ull
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_14_BASE 0x461B460ull
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_15_BASE 0x461B4B0ull
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE3_TPC1_CFG_KERNEL_SYNC_OBJECT_BASE 0x461B500ull
+#define DCORE3_TPC1_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE3_TPC1_CFG_KERNEL_BASE 0x461B508ull
+#define DCORE3_TPC1_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE3_TPC1_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE3_TPC1_CFG_QM_TENSOR_0_BASE 0x461B5DCull
+#define DCORE3_TPC1_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE3_TPC1_CFG_QM_TENSOR_1_BASE 0x461B62Cull
+#define DCORE3_TPC1_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE3_TPC1_CFG_QM_TENSOR_2_BASE 0x461B67Cull
+#define DCORE3_TPC1_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE3_TPC1_CFG_QM_TENSOR_3_BASE 0x461B6CCull
+#define DCORE3_TPC1_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE3_TPC1_CFG_QM_TENSOR_4_BASE 0x461B71Cull
+#define DCORE3_TPC1_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE3_TPC1_CFG_QM_TENSOR_5_BASE 0x461B76Cull
+#define DCORE3_TPC1_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE3_TPC1_CFG_QM_TENSOR_6_BASE 0x461B7BCull
+#define DCORE3_TPC1_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE3_TPC1_CFG_QM_TENSOR_7_BASE 0x461B80Cull
+#define DCORE3_TPC1_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE3_TPC1_CFG_QM_TENSOR_8_BASE 0x461B85Cull
+#define DCORE3_TPC1_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE3_TPC1_CFG_QM_TENSOR_9_BASE 0x461B8ACull
+#define DCORE3_TPC1_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE3_TPC1_CFG_QM_TENSOR_10_BASE 0x461B8FCull
+#define DCORE3_TPC1_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE3_TPC1_CFG_QM_TENSOR_11_BASE 0x461B94Cull
+#define DCORE3_TPC1_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE3_TPC1_CFG_QM_TENSOR_12_BASE 0x461B99Cull
+#define DCORE3_TPC1_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE3_TPC1_CFG_QM_TENSOR_13_BASE 0x461B9ECull
+#define DCORE3_TPC1_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE3_TPC1_CFG_QM_TENSOR_14_BASE 0x461BA3Cull
+#define DCORE3_TPC1_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE3_TPC1_CFG_QM_TENSOR_15_BASE 0x461BA8Cull
+#define DCORE3_TPC1_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE3_TPC1_CFG_QM_SYNC_OBJECT_BASE 0x461BADCull
+#define DCORE3_TPC1_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE3_TPC1_CFG_QM_BASE 0x461BAE4ull
+#define DCORE3_TPC1_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE3_TPC1_CFG_QM_SECTION 0x31C0
+#define mmDCORE3_TPC1_CFG_AXUSER_BASE 0x461BE00ull
+#define DCORE3_TPC1_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE3_TPC1_CFG_SPECIAL_BASE 0x461BE80ull
+#define DCORE3_TPC1_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC1_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE3_TPC1_MSTR_IF_RR_SHRD_HBW_BASE 0x461C000ull
+#define DCORE3_TPC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_TPC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE3_TPC1_MSTR_IF_RR_PRVT_HBW_BASE 0x461C200ull
+#define DCORE3_TPC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_TPC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE3_TPC1_MSTR_IF_RR_SHRD_LBW_BASE 0x461C400ull
+#define DCORE3_TPC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_TPC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE3_TPC1_MSTR_IF_RR_PRVT_LBW_BASE 0x461C600ull
+#define DCORE3_TPC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_TPC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE3_TPC1_MSTR_IF_E2E_CRDT_BASE 0x461C800ull
+#define DCORE3_TPC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_TPC1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE3_TPC1_MSTR_IF_AXUSER_BASE 0x461CA80ull
+#define DCORE3_TPC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_TPC1_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE3_TPC1_MSTR_IF_DBG_HBW_BASE 0x461CB00ull
+#define DCORE3_TPC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_TPC1_MSTR_IF_DBG_LBW_BASE 0x461CB80ull
+#define DCORE3_TPC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE3_TPC1_MSTR_IF_CORE_HBW_BASE 0x461CC00ull
+#define DCORE3_TPC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_TPC1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE3_TPC1_MSTR_IF_CORE_LBW_BASE 0x461CD80ull
+#define DCORE3_TPC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_TPC1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE3_TPC1_MSTR_IF_SPECIAL_BASE 0x461CE80ull
+#define DCORE3_TPC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC1_MSTR_IF_SPECIAL_SECTION 0x3180
+#define mmDCORE3_TPC2_QM_DCCM_BASE 0x4620000ull
+#define DCORE3_TPC2_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE3_TPC2_QM_DCCM_SECTION 0x8000
+#define mmDCORE3_TPC2_QM_ARC_AUX_BASE 0x4628000ull
+#define DCORE3_TPC2_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE3_TPC2_QM_ARC_AUX_SECTION 0xE800
+#define mmDCORE3_TPC2_QM_ARC_AUX_SPECIAL_BASE 0x4628E80ull
+#define DCORE3_TPC2_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC2_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define mmDCORE3_TPC2_QM_BASE 0x462A000ull
+#define DCORE3_TPC2_QM_MAX_OFFSET 0x1000
+#define DCORE3_TPC2_QM_SECTION 0x9000
+#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR0_BASE 0x462A900ull
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR1_BASE 0x462A908ull
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR2_BASE 0x462A910ull
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR3_BASE 0x462A918ull
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR4_BASE 0x462A920ull
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR5_BASE 0x462A928ull
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR6_BASE 0x462A930ull
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR7_BASE 0x462A938ull
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR8_BASE 0x462A940ull
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR9_BASE 0x462A948ull
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR10_BASE 0x462A950ull
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR11_BASE 0x462A958ull
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR12_BASE 0x462A960ull
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR13_BASE 0x462A968ull
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR14_BASE 0x462A970ull
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR15_BASE 0x462A978ull
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE3_TPC2_QM_AXUSER_SECURED_BASE 0x462AB00ull
+#define DCORE3_TPC2_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE3_TPC2_QM_AXUSER_NONSECURED_BASE 0x462AB80ull
+#define DCORE3_TPC2_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE3_TPC2_QM_DBG_HBW_BASE 0x462AC00ull
+#define DCORE3_TPC2_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC2_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_TPC2_QM_DBG_LBW_BASE 0x462AC80ull
+#define DCORE3_TPC2_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC2_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE3_TPC2_QM_CGM_BASE 0x462AD80ull
+#define DCORE3_TPC2_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE3_TPC2_QM_CGM_SECTION 0x1000
+#define mmDCORE3_TPC2_QM_SPECIAL_BASE 0x462AE80ull
+#define DCORE3_TPC2_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC2_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_0_BASE 0x462B000ull
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE3_TPC2_CFG_BASE 0x462B000ull
+#define DCORE3_TPC2_CFG_MAX_OFFSET 0x1000
+#define DCORE3_TPC2_CFG_SECTION 0x5000
+#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_1_BASE 0x462B050ull
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_2_BASE 0x462B0A0ull
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_3_BASE 0x462B0F0ull
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_4_BASE 0x462B140ull
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_5_BASE 0x462B190ull
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_6_BASE 0x462B1E0ull
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_7_BASE 0x462B230ull
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_8_BASE 0x462B280ull
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_9_BASE 0x462B2D0ull
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_10_BASE 0x462B320ull
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_11_BASE 0x462B370ull
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_12_BASE 0x462B3C0ull
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_13_BASE 0x462B410ull
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_14_BASE 0x462B460ull
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_15_BASE 0x462B4B0ull
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE3_TPC2_CFG_KERNEL_SYNC_OBJECT_BASE 0x462B500ull
+#define DCORE3_TPC2_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE3_TPC2_CFG_KERNEL_BASE 0x462B508ull
+#define DCORE3_TPC2_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE3_TPC2_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE3_TPC2_CFG_QM_TENSOR_0_BASE 0x462B5DCull
+#define DCORE3_TPC2_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE3_TPC2_CFG_QM_TENSOR_1_BASE 0x462B62Cull
+#define DCORE3_TPC2_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE3_TPC2_CFG_QM_TENSOR_2_BASE 0x462B67Cull
+#define DCORE3_TPC2_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE3_TPC2_CFG_QM_TENSOR_3_BASE 0x462B6CCull
+#define DCORE3_TPC2_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE3_TPC2_CFG_QM_TENSOR_4_BASE 0x462B71Cull
+#define DCORE3_TPC2_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE3_TPC2_CFG_QM_TENSOR_5_BASE 0x462B76Cull
+#define DCORE3_TPC2_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE3_TPC2_CFG_QM_TENSOR_6_BASE 0x462B7BCull
+#define DCORE3_TPC2_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE3_TPC2_CFG_QM_TENSOR_7_BASE 0x462B80Cull
+#define DCORE3_TPC2_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE3_TPC2_CFG_QM_TENSOR_8_BASE 0x462B85Cull
+#define DCORE3_TPC2_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE3_TPC2_CFG_QM_TENSOR_9_BASE 0x462B8ACull
+#define DCORE3_TPC2_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE3_TPC2_CFG_QM_TENSOR_10_BASE 0x462B8FCull
+#define DCORE3_TPC2_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE3_TPC2_CFG_QM_TENSOR_11_BASE 0x462B94Cull
+#define DCORE3_TPC2_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE3_TPC2_CFG_QM_TENSOR_12_BASE 0x462B99Cull
+#define DCORE3_TPC2_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE3_TPC2_CFG_QM_TENSOR_13_BASE 0x462B9ECull
+#define DCORE3_TPC2_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE3_TPC2_CFG_QM_TENSOR_14_BASE 0x462BA3Cull
+#define DCORE3_TPC2_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE3_TPC2_CFG_QM_TENSOR_15_BASE 0x462BA8Cull
+#define DCORE3_TPC2_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE3_TPC2_CFG_QM_SYNC_OBJECT_BASE 0x462BADCull
+#define DCORE3_TPC2_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE3_TPC2_CFG_QM_BASE 0x462BAE4ull
+#define DCORE3_TPC2_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE3_TPC2_CFG_QM_SECTION 0x31C0
+#define mmDCORE3_TPC2_CFG_AXUSER_BASE 0x462BE00ull
+#define DCORE3_TPC2_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE3_TPC2_CFG_SPECIAL_BASE 0x462BE80ull
+#define DCORE3_TPC2_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC2_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE3_TPC2_MSTR_IF_RR_SHRD_HBW_BASE 0x462C000ull
+#define DCORE3_TPC2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_TPC2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE3_TPC2_MSTR_IF_RR_PRVT_HBW_BASE 0x462C200ull
+#define DCORE3_TPC2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_TPC2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE3_TPC2_MSTR_IF_RR_SHRD_LBW_BASE 0x462C400ull
+#define DCORE3_TPC2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_TPC2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE3_TPC2_MSTR_IF_RR_PRVT_LBW_BASE 0x462C600ull
+#define DCORE3_TPC2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_TPC2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE3_TPC2_MSTR_IF_E2E_CRDT_BASE 0x462C800ull
+#define DCORE3_TPC2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_TPC2_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE3_TPC2_MSTR_IF_AXUSER_BASE 0x462CA80ull
+#define DCORE3_TPC2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_TPC2_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE3_TPC2_MSTR_IF_DBG_HBW_BASE 0x462CB00ull
+#define DCORE3_TPC2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC2_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_TPC2_MSTR_IF_DBG_LBW_BASE 0x462CB80ull
+#define DCORE3_TPC2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC2_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE3_TPC2_MSTR_IF_CORE_HBW_BASE 0x462CC00ull
+#define DCORE3_TPC2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_TPC2_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE3_TPC2_MSTR_IF_CORE_LBW_BASE 0x462CD80ull
+#define DCORE3_TPC2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_TPC2_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE3_TPC2_MSTR_IF_SPECIAL_BASE 0x462CE80ull
+#define DCORE3_TPC2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC2_MSTR_IF_SPECIAL_SECTION 0x3180
+#define mmDCORE3_TPC3_QM_DCCM_BASE 0x4630000ull
+#define DCORE3_TPC3_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE3_TPC3_QM_DCCM_SECTION 0x8000
+#define mmDCORE3_TPC3_QM_ARC_AUX_BASE 0x4638000ull
+#define DCORE3_TPC3_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE3_TPC3_QM_ARC_AUX_SECTION 0xE800
+#define mmDCORE3_TPC3_QM_ARC_AUX_SPECIAL_BASE 0x4638E80ull
+#define DCORE3_TPC3_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC3_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define mmDCORE3_TPC3_QM_BASE 0x463A000ull
+#define DCORE3_TPC3_QM_MAX_OFFSET 0x1000
+#define DCORE3_TPC3_QM_SECTION 0x9000
+#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR0_BASE 0x463A900ull
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR1_BASE 0x463A908ull
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR2_BASE 0x463A910ull
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR3_BASE 0x463A918ull
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR4_BASE 0x463A920ull
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR5_BASE 0x463A928ull
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR6_BASE 0x463A930ull
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR7_BASE 0x463A938ull
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR8_BASE 0x463A940ull
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR9_BASE 0x463A948ull
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR10_BASE 0x463A950ull
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR11_BASE 0x463A958ull
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR12_BASE 0x463A960ull
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR13_BASE 0x463A968ull
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR14_BASE 0x463A970ull
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR15_BASE 0x463A978ull
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE3_TPC3_QM_AXUSER_SECURED_BASE 0x463AB00ull
+#define DCORE3_TPC3_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE3_TPC3_QM_AXUSER_NONSECURED_BASE 0x463AB80ull
+#define DCORE3_TPC3_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE3_TPC3_QM_DBG_HBW_BASE 0x463AC00ull
+#define DCORE3_TPC3_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC3_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_TPC3_QM_DBG_LBW_BASE 0x463AC80ull
+#define DCORE3_TPC3_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC3_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE3_TPC3_QM_CGM_BASE 0x463AD80ull
+#define DCORE3_TPC3_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE3_TPC3_QM_CGM_SECTION 0x1000
+#define mmDCORE3_TPC3_QM_SPECIAL_BASE 0x463AE80ull
+#define DCORE3_TPC3_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC3_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_0_BASE 0x463B000ull
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE3_TPC3_CFG_BASE 0x463B000ull
+#define DCORE3_TPC3_CFG_MAX_OFFSET 0x1000
+#define DCORE3_TPC3_CFG_SECTION 0x5000
+#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_1_BASE 0x463B050ull
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_2_BASE 0x463B0A0ull
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_3_BASE 0x463B0F0ull
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_4_BASE 0x463B140ull
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_5_BASE 0x463B190ull
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_6_BASE 0x463B1E0ull
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_7_BASE 0x463B230ull
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_8_BASE 0x463B280ull
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_9_BASE 0x463B2D0ull
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_10_BASE 0x463B320ull
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_11_BASE 0x463B370ull
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_12_BASE 0x463B3C0ull
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_13_BASE 0x463B410ull
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_14_BASE 0x463B460ull
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_15_BASE 0x463B4B0ull
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE3_TPC3_CFG_KERNEL_SYNC_OBJECT_BASE 0x463B500ull
+#define DCORE3_TPC3_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE3_TPC3_CFG_KERNEL_BASE 0x463B508ull
+#define DCORE3_TPC3_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE3_TPC3_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE3_TPC3_CFG_QM_TENSOR_0_BASE 0x463B5DCull
+#define DCORE3_TPC3_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE3_TPC3_CFG_QM_TENSOR_1_BASE 0x463B62Cull
+#define DCORE3_TPC3_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE3_TPC3_CFG_QM_TENSOR_2_BASE 0x463B67Cull
+#define DCORE3_TPC3_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE3_TPC3_CFG_QM_TENSOR_3_BASE 0x463B6CCull
+#define DCORE3_TPC3_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE3_TPC3_CFG_QM_TENSOR_4_BASE 0x463B71Cull
+#define DCORE3_TPC3_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE3_TPC3_CFG_QM_TENSOR_5_BASE 0x463B76Cull
+#define DCORE3_TPC3_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE3_TPC3_CFG_QM_TENSOR_6_BASE 0x463B7BCull
+#define DCORE3_TPC3_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE3_TPC3_CFG_QM_TENSOR_7_BASE 0x463B80Cull
+#define DCORE3_TPC3_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE3_TPC3_CFG_QM_TENSOR_8_BASE 0x463B85Cull
+#define DCORE3_TPC3_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE3_TPC3_CFG_QM_TENSOR_9_BASE 0x463B8ACull
+#define DCORE3_TPC3_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE3_TPC3_CFG_QM_TENSOR_10_BASE 0x463B8FCull
+#define DCORE3_TPC3_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE3_TPC3_CFG_QM_TENSOR_11_BASE 0x463B94Cull
+#define DCORE3_TPC3_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE3_TPC3_CFG_QM_TENSOR_12_BASE 0x463B99Cull
+#define DCORE3_TPC3_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE3_TPC3_CFG_QM_TENSOR_13_BASE 0x463B9ECull
+#define DCORE3_TPC3_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE3_TPC3_CFG_QM_TENSOR_14_BASE 0x463BA3Cull
+#define DCORE3_TPC3_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE3_TPC3_CFG_QM_TENSOR_15_BASE 0x463BA8Cull
+#define DCORE3_TPC3_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE3_TPC3_CFG_QM_SYNC_OBJECT_BASE 0x463BADCull
+#define DCORE3_TPC3_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE3_TPC3_CFG_QM_BASE 0x463BAE4ull
+#define DCORE3_TPC3_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE3_TPC3_CFG_QM_SECTION 0x31C0
+#define mmDCORE3_TPC3_CFG_AXUSER_BASE 0x463BE00ull
+#define DCORE3_TPC3_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE3_TPC3_CFG_SPECIAL_BASE 0x463BE80ull
+#define DCORE3_TPC3_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC3_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE3_TPC3_MSTR_IF_RR_SHRD_HBW_BASE 0x463C000ull
+#define DCORE3_TPC3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_TPC3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE3_TPC3_MSTR_IF_RR_PRVT_HBW_BASE 0x463C200ull
+#define DCORE3_TPC3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_TPC3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE3_TPC3_MSTR_IF_RR_SHRD_LBW_BASE 0x463C400ull
+#define DCORE3_TPC3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_TPC3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE3_TPC3_MSTR_IF_RR_PRVT_LBW_BASE 0x463C600ull
+#define DCORE3_TPC3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_TPC3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE3_TPC3_MSTR_IF_E2E_CRDT_BASE 0x463C800ull
+#define DCORE3_TPC3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_TPC3_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE3_TPC3_MSTR_IF_AXUSER_BASE 0x463CA80ull
+#define DCORE3_TPC3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_TPC3_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE3_TPC3_MSTR_IF_DBG_HBW_BASE 0x463CB00ull
+#define DCORE3_TPC3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC3_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_TPC3_MSTR_IF_DBG_LBW_BASE 0x463CB80ull
+#define DCORE3_TPC3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC3_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE3_TPC3_MSTR_IF_CORE_HBW_BASE 0x463CC00ull
+#define DCORE3_TPC3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_TPC3_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE3_TPC3_MSTR_IF_CORE_LBW_BASE 0x463CD80ull
+#define DCORE3_TPC3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_TPC3_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE3_TPC3_MSTR_IF_SPECIAL_BASE 0x463CE80ull
+#define DCORE3_TPC3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC3_MSTR_IF_SPECIAL_SECTION 0x3180
+#define mmDCORE3_TPC4_QM_DCCM_BASE 0x4640000ull
+#define DCORE3_TPC4_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE3_TPC4_QM_DCCM_SECTION 0x8000
+#define mmDCORE3_TPC4_QM_ARC_AUX_BASE 0x4648000ull
+#define DCORE3_TPC4_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE3_TPC4_QM_ARC_AUX_SECTION 0xE800
+#define mmDCORE3_TPC4_QM_ARC_AUX_SPECIAL_BASE 0x4648E80ull
+#define DCORE3_TPC4_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC4_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define mmDCORE3_TPC4_QM_BASE 0x464A000ull
+#define DCORE3_TPC4_QM_MAX_OFFSET 0x1000
+#define DCORE3_TPC4_QM_SECTION 0x9000
+#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR0_BASE 0x464A900ull
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR1_BASE 0x464A908ull
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR2_BASE 0x464A910ull
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR3_BASE 0x464A918ull
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR4_BASE 0x464A920ull
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR5_BASE 0x464A928ull
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR6_BASE 0x464A930ull
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR7_BASE 0x464A938ull
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR8_BASE 0x464A940ull
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR9_BASE 0x464A948ull
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR10_BASE 0x464A950ull
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR11_BASE 0x464A958ull
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR12_BASE 0x464A960ull
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR13_BASE 0x464A968ull
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR14_BASE 0x464A970ull
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR15_BASE 0x464A978ull
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE3_TPC4_QM_AXUSER_SECURED_BASE 0x464AB00ull
+#define DCORE3_TPC4_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE3_TPC4_QM_AXUSER_NONSECURED_BASE 0x464AB80ull
+#define DCORE3_TPC4_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE3_TPC4_QM_DBG_HBW_BASE 0x464AC00ull
+#define DCORE3_TPC4_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC4_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_TPC4_QM_DBG_LBW_BASE 0x464AC80ull
+#define DCORE3_TPC4_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC4_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE3_TPC4_QM_CGM_BASE 0x464AD80ull
+#define DCORE3_TPC4_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE3_TPC4_QM_CGM_SECTION 0x1000
+#define mmDCORE3_TPC4_QM_SPECIAL_BASE 0x464AE80ull
+#define DCORE3_TPC4_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC4_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_0_BASE 0x464B000ull
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE3_TPC4_CFG_BASE 0x464B000ull
+#define DCORE3_TPC4_CFG_MAX_OFFSET 0x1000
+#define DCORE3_TPC4_CFG_SECTION 0x5000
+#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_1_BASE 0x464B050ull
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_2_BASE 0x464B0A0ull
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_3_BASE 0x464B0F0ull
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_4_BASE 0x464B140ull
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_5_BASE 0x464B190ull
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_6_BASE 0x464B1E0ull
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_7_BASE 0x464B230ull
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_8_BASE 0x464B280ull
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_9_BASE 0x464B2D0ull
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_10_BASE 0x464B320ull
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_11_BASE 0x464B370ull
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_12_BASE 0x464B3C0ull
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_13_BASE 0x464B410ull
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_14_BASE 0x464B460ull
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_15_BASE 0x464B4B0ull
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE3_TPC4_CFG_KERNEL_SYNC_OBJECT_BASE 0x464B500ull
+#define DCORE3_TPC4_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE3_TPC4_CFG_KERNEL_BASE 0x464B508ull
+#define DCORE3_TPC4_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE3_TPC4_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE3_TPC4_CFG_QM_TENSOR_0_BASE 0x464B5DCull
+#define DCORE3_TPC4_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE3_TPC4_CFG_QM_TENSOR_1_BASE 0x464B62Cull
+#define DCORE3_TPC4_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE3_TPC4_CFG_QM_TENSOR_2_BASE 0x464B67Cull
+#define DCORE3_TPC4_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE3_TPC4_CFG_QM_TENSOR_3_BASE 0x464B6CCull
+#define DCORE3_TPC4_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE3_TPC4_CFG_QM_TENSOR_4_BASE 0x464B71Cull
+#define DCORE3_TPC4_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE3_TPC4_CFG_QM_TENSOR_5_BASE 0x464B76Cull
+#define DCORE3_TPC4_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE3_TPC4_CFG_QM_TENSOR_6_BASE 0x464B7BCull
+#define DCORE3_TPC4_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE3_TPC4_CFG_QM_TENSOR_7_BASE 0x464B80Cull
+#define DCORE3_TPC4_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE3_TPC4_CFG_QM_TENSOR_8_BASE 0x464B85Cull
+#define DCORE3_TPC4_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE3_TPC4_CFG_QM_TENSOR_9_BASE 0x464B8ACull
+#define DCORE3_TPC4_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE3_TPC4_CFG_QM_TENSOR_10_BASE 0x464B8FCull
+#define DCORE3_TPC4_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE3_TPC4_CFG_QM_TENSOR_11_BASE 0x464B94Cull
+#define DCORE3_TPC4_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE3_TPC4_CFG_QM_TENSOR_12_BASE 0x464B99Cull
+#define DCORE3_TPC4_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE3_TPC4_CFG_QM_TENSOR_13_BASE 0x464B9ECull
+#define DCORE3_TPC4_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE3_TPC4_CFG_QM_TENSOR_14_BASE 0x464BA3Cull
+#define DCORE3_TPC4_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE3_TPC4_CFG_QM_TENSOR_15_BASE 0x464BA8Cull
+#define DCORE3_TPC4_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE3_TPC4_CFG_QM_SYNC_OBJECT_BASE 0x464BADCull
+#define DCORE3_TPC4_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE3_TPC4_CFG_QM_BASE 0x464BAE4ull
+#define DCORE3_TPC4_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE3_TPC4_CFG_QM_SECTION 0x31C0
+#define mmDCORE3_TPC4_CFG_AXUSER_BASE 0x464BE00ull
+#define DCORE3_TPC4_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE3_TPC4_CFG_SPECIAL_BASE 0x464BE80ull
+#define DCORE3_TPC4_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC4_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE3_TPC4_MSTR_IF_RR_SHRD_HBW_BASE 0x464C000ull
+#define DCORE3_TPC4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_TPC4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE3_TPC4_MSTR_IF_RR_PRVT_HBW_BASE 0x464C200ull
+#define DCORE3_TPC4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_TPC4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE3_TPC4_MSTR_IF_RR_SHRD_LBW_BASE 0x464C400ull
+#define DCORE3_TPC4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_TPC4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE3_TPC4_MSTR_IF_RR_PRVT_LBW_BASE 0x464C600ull
+#define DCORE3_TPC4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_TPC4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE3_TPC4_MSTR_IF_E2E_CRDT_BASE 0x464C800ull
+#define DCORE3_TPC4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_TPC4_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE3_TPC4_MSTR_IF_AXUSER_BASE 0x464CA80ull
+#define DCORE3_TPC4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_TPC4_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE3_TPC4_MSTR_IF_DBG_HBW_BASE 0x464CB00ull
+#define DCORE3_TPC4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC4_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_TPC4_MSTR_IF_DBG_LBW_BASE 0x464CB80ull
+#define DCORE3_TPC4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC4_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE3_TPC4_MSTR_IF_CORE_HBW_BASE 0x464CC00ull
+#define DCORE3_TPC4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_TPC4_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE3_TPC4_MSTR_IF_CORE_LBW_BASE 0x464CD80ull
+#define DCORE3_TPC4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_TPC4_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE3_TPC4_MSTR_IF_SPECIAL_BASE 0x464CE80ull
+#define DCORE3_TPC4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC4_MSTR_IF_SPECIAL_SECTION 0x3180
+#define mmDCORE3_TPC5_QM_DCCM_BASE 0x4650000ull
+#define DCORE3_TPC5_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE3_TPC5_QM_DCCM_SECTION 0x8000
+#define mmDCORE3_TPC5_QM_ARC_AUX_BASE 0x4658000ull
+#define DCORE3_TPC5_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE3_TPC5_QM_ARC_AUX_SECTION 0xE800
+#define mmDCORE3_TPC5_QM_ARC_AUX_SPECIAL_BASE 0x4658E80ull
+#define DCORE3_TPC5_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC5_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define mmDCORE3_TPC5_QM_BASE 0x465A000ull
+#define DCORE3_TPC5_QM_MAX_OFFSET 0x1000
+#define DCORE3_TPC5_QM_SECTION 0x9000
+#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR0_BASE 0x465A900ull
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR1_BASE 0x465A908ull
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR2_BASE 0x465A910ull
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR3_BASE 0x465A918ull
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR4_BASE 0x465A920ull
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR5_BASE 0x465A928ull
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR6_BASE 0x465A930ull
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR7_BASE 0x465A938ull
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR8_BASE 0x465A940ull
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR9_BASE 0x465A948ull
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR10_BASE 0x465A950ull
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR11_BASE 0x465A958ull
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR12_BASE 0x465A960ull
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR13_BASE 0x465A968ull
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR14_BASE 0x465A970ull
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR15_BASE 0x465A978ull
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE3_TPC5_QM_AXUSER_SECURED_BASE 0x465AB00ull
+#define DCORE3_TPC5_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE3_TPC5_QM_AXUSER_NONSECURED_BASE 0x465AB80ull
+#define DCORE3_TPC5_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE3_TPC5_QM_DBG_HBW_BASE 0x465AC00ull
+#define DCORE3_TPC5_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC5_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_TPC5_QM_DBG_LBW_BASE 0x465AC80ull
+#define DCORE3_TPC5_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC5_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE3_TPC5_QM_CGM_BASE 0x465AD80ull
+#define DCORE3_TPC5_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE3_TPC5_QM_CGM_SECTION 0x1000
+#define mmDCORE3_TPC5_QM_SPECIAL_BASE 0x465AE80ull
+#define DCORE3_TPC5_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC5_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_0_BASE 0x465B000ull
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE3_TPC5_CFG_BASE 0x465B000ull
+#define DCORE3_TPC5_CFG_MAX_OFFSET 0x1000
+#define DCORE3_TPC5_CFG_SECTION 0x5000
+#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_1_BASE 0x465B050ull
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_1_SECTION 0x5000
+#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_2_BASE 0x465B0A0ull
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_2_SECTION 0x5000
+#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_3_BASE 0x465B0F0ull
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_3_SECTION 0x5000
+#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_4_BASE 0x465B140ull
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_4_SECTION 0x5000
+#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_5_BASE 0x465B190ull
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_5_SECTION 0x5000
+#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_6_BASE 0x465B1E0ull
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_6_SECTION 0x5000
+#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_7_BASE 0x465B230ull
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_7_SECTION 0x5000
+#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_8_BASE 0x465B280ull
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_8_SECTION 0x5000
+#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_9_BASE 0x465B2D0ull
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_9_SECTION 0x5000
+#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_10_BASE 0x465B320ull
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_10_SECTION 0x5000
+#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_11_BASE 0x465B370ull
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_11_SECTION 0x5000
+#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_12_BASE 0x465B3C0ull
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_12_SECTION 0x5000
+#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_13_BASE 0x465B410ull
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_13_SECTION 0x5000
+#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_14_BASE 0x465B460ull
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_14_SECTION 0x5000
+#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_15_BASE 0x465B4B0ull
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_KERNEL_TENSOR_15_SECTION 0x5000
+#define mmDCORE3_TPC5_CFG_KERNEL_SYNC_OBJECT_BASE 0x465B500ull
+#define DCORE3_TPC5_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE3_TPC5_CFG_KERNEL_BASE 0x465B508ull
+#define DCORE3_TPC5_CFG_KERNEL_MAX_OFFSET 0xD400
+#define DCORE3_TPC5_CFG_KERNEL_SECTION 0xD400
+#define mmDCORE3_TPC5_CFG_QM_TENSOR_0_BASE 0x465B5DCull
+#define DCORE3_TPC5_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_0_SECTION 0x5000
+#define mmDCORE3_TPC5_CFG_QM_TENSOR_1_BASE 0x465B62Cull
+#define DCORE3_TPC5_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_1_SECTION 0x5000
+#define mmDCORE3_TPC5_CFG_QM_TENSOR_2_BASE 0x465B67Cull
+#define DCORE3_TPC5_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_2_SECTION 0x5000
+#define mmDCORE3_TPC5_CFG_QM_TENSOR_3_BASE 0x465B6CCull
+#define DCORE3_TPC5_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_3_SECTION 0x5000
+#define mmDCORE3_TPC5_CFG_QM_TENSOR_4_BASE 0x465B71Cull
+#define DCORE3_TPC5_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_4_SECTION 0x5000
+#define mmDCORE3_TPC5_CFG_QM_TENSOR_5_BASE 0x465B76Cull
+#define DCORE3_TPC5_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_5_SECTION 0x5000
+#define mmDCORE3_TPC5_CFG_QM_TENSOR_6_BASE 0x465B7BCull
+#define DCORE3_TPC5_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_6_SECTION 0x5000
+#define mmDCORE3_TPC5_CFG_QM_TENSOR_7_BASE 0x465B80Cull
+#define DCORE3_TPC5_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_7_SECTION 0x5000
+#define mmDCORE3_TPC5_CFG_QM_TENSOR_8_BASE 0x465B85Cull
+#define DCORE3_TPC5_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_8_SECTION 0x5000
+#define mmDCORE3_TPC5_CFG_QM_TENSOR_9_BASE 0x465B8ACull
+#define DCORE3_TPC5_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_9_SECTION 0x5000
+#define mmDCORE3_TPC5_CFG_QM_TENSOR_10_BASE 0x465B8FCull
+#define DCORE3_TPC5_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_10_SECTION 0x5000
+#define mmDCORE3_TPC5_CFG_QM_TENSOR_11_BASE 0x465B94Cull
+#define DCORE3_TPC5_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_11_SECTION 0x5000
+#define mmDCORE3_TPC5_CFG_QM_TENSOR_12_BASE 0x465B99Cull
+#define DCORE3_TPC5_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_12_SECTION 0x5000
+#define mmDCORE3_TPC5_CFG_QM_TENSOR_13_BASE 0x465B9ECull
+#define DCORE3_TPC5_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_13_SECTION 0x5000
+#define mmDCORE3_TPC5_CFG_QM_TENSOR_14_BASE 0x465BA3Cull
+#define DCORE3_TPC5_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_14_SECTION 0x5000
+#define mmDCORE3_TPC5_CFG_QM_TENSOR_15_BASE 0x465BA8Cull
+#define DCORE3_TPC5_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_QM_TENSOR_15_SECTION 0x5000
+#define mmDCORE3_TPC5_CFG_QM_SYNC_OBJECT_BASE 0x465BADCull
+#define DCORE3_TPC5_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_CFG_QM_SYNC_OBJECT_SECTION 0x8000
+#define mmDCORE3_TPC5_CFG_QM_BASE 0x465BAE4ull
+#define DCORE3_TPC5_CFG_QM_MAX_OFFSET 0xD400
+#define DCORE3_TPC5_CFG_QM_SECTION 0x31C0
+#define mmDCORE3_TPC5_CFG_AXUSER_BASE 0x465BE00ull
+#define DCORE3_TPC5_CFG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_CFG_AXUSER_SECTION 0x8000
+#define mmDCORE3_TPC5_CFG_SPECIAL_BASE 0x465BE80ull
+#define DCORE3_TPC5_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC5_CFG_SPECIAL_SECTION 0x1800
+#define mmDCORE3_TPC5_MSTR_IF_RR_SHRD_HBW_BASE 0x465C000ull
+#define DCORE3_TPC5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_TPC5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE3_TPC5_MSTR_IF_RR_PRVT_HBW_BASE 0x465C200ull
+#define DCORE3_TPC5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_TPC5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE3_TPC5_MSTR_IF_RR_SHRD_LBW_BASE 0x465C400ull
+#define DCORE3_TPC5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_TPC5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE3_TPC5_MSTR_IF_RR_PRVT_LBW_BASE 0x465C600ull
+#define DCORE3_TPC5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_TPC5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE3_TPC5_MSTR_IF_E2E_CRDT_BASE 0x465C800ull
+#define DCORE3_TPC5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_TPC5_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE3_TPC5_MSTR_IF_AXUSER_BASE 0x465CA80ull
+#define DCORE3_TPC5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_TPC5_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE3_TPC5_MSTR_IF_DBG_HBW_BASE 0x465CB00ull
+#define DCORE3_TPC5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC5_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_TPC5_MSTR_IF_DBG_LBW_BASE 0x465CB80ull
+#define DCORE3_TPC5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_TPC5_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE3_TPC5_MSTR_IF_CORE_HBW_BASE 0x465CC00ull
+#define DCORE3_TPC5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_TPC5_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE3_TPC5_MSTR_IF_CORE_LBW_BASE 0x465CD80ull
+#define DCORE3_TPC5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_TPC5_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE3_TPC5_MSTR_IF_SPECIAL_BASE 0x465CE80ull
+#define DCORE3_TPC5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC5_MSTR_IF_SPECIAL_SECTION 0x23180
+#define mmDCORE3_HMMU0_MMU_BASE 0x4680000ull
+#define DCORE3_HMMU0_MMU_MAX_OFFSET 0x1000
+#define DCORE3_HMMU0_MMU_SECTION 0xE800
+#define mmDCORE3_HMMU0_MMU_SPECIAL_BASE 0x4680E80ull
+#define DCORE3_HMMU0_MMU_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HMMU0_MMU_SPECIAL_SECTION 0x1800
+#define mmDCORE3_HMMU0_STLB_BASE 0x4681000ull
+#define DCORE3_HMMU0_STLB_MAX_OFFSET 0x1000
+#define DCORE3_HMMU0_STLB_SECTION 0xE800
+#define mmDCORE3_HMMU0_STLB_SPECIAL_BASE 0x4681E80ull
+#define DCORE3_HMMU0_STLB_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HMMU0_STLB_SPECIAL_SECTION 0x1180
+#define mmDCORE3_HMMU0_SCRAMB_OUT_BASE 0x4683000ull
+#define DCORE3_HMMU0_SCRAMB_OUT_MAX_OFFSET 0x1000
+#define DCORE3_HMMU0_SCRAMB_OUT_SECTION 0xE800
+#define mmDCORE3_HMMU0_SCRAMB_OUT_SPECIAL_BASE 0x4683E80ull
+#define DCORE3_HMMU0_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HMMU0_SCRAMB_OUT_SPECIAL_SECTION 0x1800
+#define mmDCORE3_HMMU0_MSTR_IF_RR_SHRD_HBW_BASE 0x4684000ull
+#define DCORE3_HMMU0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_HMMU0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE3_HMMU0_MSTR_IF_RR_PRVT_HBW_BASE 0x4684200ull
+#define DCORE3_HMMU0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_HMMU0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE3_HMMU0_MSTR_IF_RR_SHRD_LBW_BASE 0x4684400ull
+#define DCORE3_HMMU0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_HMMU0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE3_HMMU0_MSTR_IF_RR_PRVT_LBW_BASE 0x4684600ull
+#define DCORE3_HMMU0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_HMMU0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE3_HMMU0_MSTR_IF_E2E_CRDT_BASE 0x4684800ull
+#define DCORE3_HMMU0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_HMMU0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE3_HMMU0_MSTR_IF_AXUSER_BASE 0x4684A80ull
+#define DCORE3_HMMU0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_HMMU0_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE3_HMMU0_MSTR_IF_DBG_HBW_BASE 0x4684B00ull
+#define DCORE3_HMMU0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_HMMU0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_HMMU0_MSTR_IF_DBG_LBW_BASE 0x4684B80ull
+#define DCORE3_HMMU0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_HMMU0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE3_HMMU0_MSTR_IF_CORE_HBW_BASE 0x4684C00ull
+#define DCORE3_HMMU0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_HMMU0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE3_HMMU0_MSTR_IF_CORE_LBW_BASE 0x4684D80ull
+#define DCORE3_HMMU0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_HMMU0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE3_HMMU0_MSTR_IF_SPECIAL_BASE 0x4684E80ull
+#define DCORE3_HMMU0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HMMU0_MSTR_IF_SPECIAL_SECTION 0xB180
+#define mmDCORE3_HMMU1_MMU_BASE 0x4690000ull
+#define DCORE3_HMMU1_MMU_MAX_OFFSET 0x1000
+#define DCORE3_HMMU1_MMU_SECTION 0xE800
+#define mmDCORE3_HMMU1_MMU_SPECIAL_BASE 0x4690E80ull
+#define DCORE3_HMMU1_MMU_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HMMU1_MMU_SPECIAL_SECTION 0x1800
+#define mmDCORE3_HMMU1_STLB_BASE 0x4691000ull
+#define DCORE3_HMMU1_STLB_MAX_OFFSET 0x1000
+#define DCORE3_HMMU1_STLB_SECTION 0xE800
+#define mmDCORE3_HMMU1_STLB_SPECIAL_BASE 0x4691E80ull
+#define DCORE3_HMMU1_STLB_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HMMU1_STLB_SPECIAL_SECTION 0x1180
+#define mmDCORE3_HMMU1_SCRAMB_OUT_BASE 0x4693000ull
+#define DCORE3_HMMU1_SCRAMB_OUT_MAX_OFFSET 0x1000
+#define DCORE3_HMMU1_SCRAMB_OUT_SECTION 0xE800
+#define mmDCORE3_HMMU1_SCRAMB_OUT_SPECIAL_BASE 0x4693E80ull
+#define DCORE3_HMMU1_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HMMU1_SCRAMB_OUT_SPECIAL_SECTION 0x1800
+#define mmDCORE3_HMMU1_MSTR_IF_RR_SHRD_HBW_BASE 0x4694000ull
+#define DCORE3_HMMU1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_HMMU1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE3_HMMU1_MSTR_IF_RR_PRVT_HBW_BASE 0x4694200ull
+#define DCORE3_HMMU1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_HMMU1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE3_HMMU1_MSTR_IF_RR_SHRD_LBW_BASE 0x4694400ull
+#define DCORE3_HMMU1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_HMMU1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE3_HMMU1_MSTR_IF_RR_PRVT_LBW_BASE 0x4694600ull
+#define DCORE3_HMMU1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_HMMU1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE3_HMMU1_MSTR_IF_E2E_CRDT_BASE 0x4694800ull
+#define DCORE3_HMMU1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_HMMU1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE3_HMMU1_MSTR_IF_AXUSER_BASE 0x4694A80ull
+#define DCORE3_HMMU1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_HMMU1_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE3_HMMU1_MSTR_IF_DBG_HBW_BASE 0x4694B00ull
+#define DCORE3_HMMU1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_HMMU1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_HMMU1_MSTR_IF_DBG_LBW_BASE 0x4694B80ull
+#define DCORE3_HMMU1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_HMMU1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE3_HMMU1_MSTR_IF_CORE_HBW_BASE 0x4694C00ull
+#define DCORE3_HMMU1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_HMMU1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE3_HMMU1_MSTR_IF_CORE_LBW_BASE 0x4694D80ull
+#define DCORE3_HMMU1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_HMMU1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE3_HMMU1_MSTR_IF_SPECIAL_BASE 0x4694E80ull
+#define DCORE3_HMMU1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HMMU1_MSTR_IF_SPECIAL_SECTION 0xB180
+#define mmDCORE3_HMMU2_MMU_BASE 0x46A0000ull
+#define DCORE3_HMMU2_MMU_MAX_OFFSET 0x1000
+#define DCORE3_HMMU2_MMU_SECTION 0xE800
+#define mmDCORE3_HMMU2_MMU_SPECIAL_BASE 0x46A0E80ull
+#define DCORE3_HMMU2_MMU_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HMMU2_MMU_SPECIAL_SECTION 0x1800
+#define mmDCORE3_HMMU2_STLB_BASE 0x46A1000ull
+#define DCORE3_HMMU2_STLB_MAX_OFFSET 0x1000
+#define DCORE3_HMMU2_STLB_SECTION 0xE800
+#define mmDCORE3_HMMU2_STLB_SPECIAL_BASE 0x46A1E80ull
+#define DCORE3_HMMU2_STLB_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HMMU2_STLB_SPECIAL_SECTION 0x1180
+#define mmDCORE3_HMMU2_SCRAMB_OUT_BASE 0x46A3000ull
+#define DCORE3_HMMU2_SCRAMB_OUT_MAX_OFFSET 0x1000
+#define DCORE3_HMMU2_SCRAMB_OUT_SECTION 0xE800
+#define mmDCORE3_HMMU2_SCRAMB_OUT_SPECIAL_BASE 0x46A3E80ull
+#define DCORE3_HMMU2_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HMMU2_SCRAMB_OUT_SPECIAL_SECTION 0x1800
+#define mmDCORE3_HMMU2_MSTR_IF_RR_SHRD_HBW_BASE 0x46A4000ull
+#define DCORE3_HMMU2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_HMMU2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE3_HMMU2_MSTR_IF_RR_PRVT_HBW_BASE 0x46A4200ull
+#define DCORE3_HMMU2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_HMMU2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE3_HMMU2_MSTR_IF_RR_SHRD_LBW_BASE 0x46A4400ull
+#define DCORE3_HMMU2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_HMMU2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE3_HMMU2_MSTR_IF_RR_PRVT_LBW_BASE 0x46A4600ull
+#define DCORE3_HMMU2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_HMMU2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE3_HMMU2_MSTR_IF_E2E_CRDT_BASE 0x46A4800ull
+#define DCORE3_HMMU2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_HMMU2_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE3_HMMU2_MSTR_IF_AXUSER_BASE 0x46A4A80ull
+#define DCORE3_HMMU2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_HMMU2_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE3_HMMU2_MSTR_IF_DBG_HBW_BASE 0x46A4B00ull
+#define DCORE3_HMMU2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_HMMU2_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_HMMU2_MSTR_IF_DBG_LBW_BASE 0x46A4B80ull
+#define DCORE3_HMMU2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_HMMU2_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE3_HMMU2_MSTR_IF_CORE_HBW_BASE 0x46A4C00ull
+#define DCORE3_HMMU2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_HMMU2_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE3_HMMU2_MSTR_IF_CORE_LBW_BASE 0x46A4D80ull
+#define DCORE3_HMMU2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_HMMU2_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE3_HMMU2_MSTR_IF_SPECIAL_BASE 0x46A4E80ull
+#define DCORE3_HMMU2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HMMU2_MSTR_IF_SPECIAL_SECTION 0xB180
+#define mmDCORE3_HMMU3_MMU_BASE 0x46B0000ull
+#define DCORE3_HMMU3_MMU_MAX_OFFSET 0x1000
+#define DCORE3_HMMU3_MMU_SECTION 0xE800
+#define mmDCORE3_HMMU3_MMU_SPECIAL_BASE 0x46B0E80ull
+#define DCORE3_HMMU3_MMU_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HMMU3_MMU_SPECIAL_SECTION 0x1800
+#define mmDCORE3_HMMU3_STLB_BASE 0x46B1000ull
+#define DCORE3_HMMU3_STLB_MAX_OFFSET 0x1000
+#define DCORE3_HMMU3_STLB_SECTION 0xE800
+#define mmDCORE3_HMMU3_STLB_SPECIAL_BASE 0x46B1E80ull
+#define DCORE3_HMMU3_STLB_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HMMU3_STLB_SPECIAL_SECTION 0x1180
+#define mmDCORE3_HMMU3_SCRAMB_OUT_BASE 0x46B3000ull
+#define DCORE3_HMMU3_SCRAMB_OUT_MAX_OFFSET 0x1000
+#define DCORE3_HMMU3_SCRAMB_OUT_SECTION 0xE800
+#define mmDCORE3_HMMU3_SCRAMB_OUT_SPECIAL_BASE 0x46B3E80ull
+#define DCORE3_HMMU3_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HMMU3_SCRAMB_OUT_SPECIAL_SECTION 0x1800
+#define mmDCORE3_HMMU3_MSTR_IF_RR_SHRD_HBW_BASE 0x46B4000ull
+#define DCORE3_HMMU3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_HMMU3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE3_HMMU3_MSTR_IF_RR_PRVT_HBW_BASE 0x46B4200ull
+#define DCORE3_HMMU3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_HMMU3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE3_HMMU3_MSTR_IF_RR_SHRD_LBW_BASE 0x46B4400ull
+#define DCORE3_HMMU3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_HMMU3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE3_HMMU3_MSTR_IF_RR_PRVT_LBW_BASE 0x46B4600ull
+#define DCORE3_HMMU3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_HMMU3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE3_HMMU3_MSTR_IF_E2E_CRDT_BASE 0x46B4800ull
+#define DCORE3_HMMU3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_HMMU3_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE3_HMMU3_MSTR_IF_AXUSER_BASE 0x46B4A80ull
+#define DCORE3_HMMU3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_HMMU3_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE3_HMMU3_MSTR_IF_DBG_HBW_BASE 0x46B4B00ull
+#define DCORE3_HMMU3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_HMMU3_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_HMMU3_MSTR_IF_DBG_LBW_BASE 0x46B4B80ull
+#define DCORE3_HMMU3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_HMMU3_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE3_HMMU3_MSTR_IF_CORE_HBW_BASE 0x46B4C00ull
+#define DCORE3_HMMU3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_HMMU3_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE3_HMMU3_MSTR_IF_CORE_LBW_BASE 0x46B4D80ull
+#define DCORE3_HMMU3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_HMMU3_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE3_HMMU3_MSTR_IF_SPECIAL_BASE 0x46B4E80ull
+#define DCORE3_HMMU3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HMMU3_MSTR_IF_SPECIAL_SECTION 0xB180
+#define mmDCORE3_MME_QM_ARC_DCCM_BASE 0x46C0000ull
+#define DCORE3_MME_QM_ARC_DCCM_MAX_OFFSET 0x4000
+#define DCORE3_MME_QM_ARC_DCCM_SECTION 0x8000
+#define mmDCORE3_MME_QM_ARC_AUX_BASE 0x46C8000ull
+#define DCORE3_MME_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE3_MME_QM_ARC_AUX_SECTION 0xE800
+#define mmDCORE3_MME_QM_ARC_AUX_SPECIAL_BASE 0x46C8E80ull
+#define DCORE3_MME_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_QM_ARC_AUX_SPECIAL_SECTION 0x1800
+#define mmDCORE3_MME_QM_ARC_DUP_ENG_BASE 0x46C9000ull
+#define DCORE3_MME_QM_ARC_DUP_ENG_MAX_OFFSET 0x1000
+#define DCORE3_MME_QM_ARC_DUP_ENG_SECTION 0x9000
+#define mmDCORE3_MME_QM_ARC_DUP_ENG_AXUSER_BASE 0x46C9900ull
+#define DCORE3_MME_QM_ARC_DUP_ENG_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_MME_QM_ARC_DUP_ENG_AXUSER_SECTION 0x5800
+#define mmDCORE3_MME_QM_ARC_DUP_ENG_SPECIAL_BASE 0x46C9E80ull
+#define DCORE3_MME_QM_ARC_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_QM_ARC_DUP_ENG_SPECIAL_SECTION 0x1800
+#define mmDCORE3_MME_QM_BASE 0x46CA000ull
+#define DCORE3_MME_QM_MAX_OFFSET 0x1000
+#define DCORE3_MME_QM_SECTION 0x9000
+#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR0_BASE 0x46CA900ull
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR1_BASE 0x46CA908ull
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR2_BASE 0x46CA910ull
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR3_BASE 0x46CA918ull
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR4_BASE 0x46CA920ull
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR5_BASE 0x46CA928ull
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR6_BASE 0x46CA930ull
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR7_BASE 0x46CA938ull
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR8_BASE 0x46CA940ull
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR9_BASE 0x46CA948ull
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR10_BASE 0x46CA950ull
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR11_BASE 0x46CA958ull
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR12_BASE 0x46CA960ull
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR13_BASE 0x46CA968ull
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR14_BASE 0x46CA970ull
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR15_BASE 0x46CA978ull
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE3_MME_QM_AXUSER_SECURED_BASE 0x46CAB00ull
+#define DCORE3_MME_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE3_MME_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE3_MME_QM_AXUSER_NONSECURED_BASE 0x46CAB80ull
+#define DCORE3_MME_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE3_MME_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE3_MME_QM_DBG_HBW_BASE 0x46CAC00ull
+#define DCORE3_MME_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_MME_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_MME_QM_DBG_LBW_BASE 0x46CAC80ull
+#define DCORE3_MME_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_MME_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE3_MME_QM_CGM_BASE 0x46CAD80ull
+#define DCORE3_MME_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE3_MME_QM_CGM_SECTION 0x1000
+#define mmDCORE3_MME_QM_SPECIAL_BASE 0x46CAE80ull
+#define DCORE3_MME_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE3_MME_CTRL_LO_BASE 0x46CB000ull
+#define DCORE3_MME_CTRL_LO_MAX_OFFSET 0x1000
+#define DCORE3_MME_CTRL_LO_SECTION 0x8000
+#define mmDCORE3_MME_CTRL_LO_ARCH_BASE_ADDR_BASE 0x46CB008ull
+#define DCORE3_MME_CTRL_LO_ARCH_BASE_ADDR_MAX_OFFSET 0x2000
+#define DCORE3_MME_CTRL_LO_ARCH_BASE_ADDR_SECTION 0x2000
+#define mmDCORE3_MME_CTRL_LO_ARCH_NON_TENSOR_START_BASE 0x46CB028ull
+#define DCORE3_MME_CTRL_LO_ARCH_NON_TENSOR_START_MAX_OFFSET 0x1800
+#define DCORE3_MME_CTRL_LO_ARCH_NON_TENSOR_START_SECTION 0x1800
+#define mmDCORE3_MME_CTRL_LO_ARCH_TENSOR_A_BASE 0x46CB040ull
+#define DCORE3_MME_CTRL_LO_ARCH_TENSOR_A_MAX_OFFSET 0x5800
+#define DCORE3_MME_CTRL_LO_ARCH_TENSOR_A_SECTION 0x5800
+#define mmDCORE3_MME_CTRL_LO_ARCH_TENSOR_B_BASE 0x46CB098ull
+#define DCORE3_MME_CTRL_LO_ARCH_TENSOR_B_MAX_OFFSET 0x5800
+#define DCORE3_MME_CTRL_LO_ARCH_TENSOR_B_SECTION 0x5800
+#define mmDCORE3_MME_CTRL_LO_ARCH_TENSOR_COUT_BASE 0x46CB0F0ull
+#define DCORE3_MME_CTRL_LO_ARCH_TENSOR_COUT_MAX_OFFSET 0x5800
+#define DCORE3_MME_CTRL_LO_ARCH_TENSOR_COUT_SECTION 0x6C00
+#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_BASE 0x46CB15Cull
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_BASE 0x46CB170ull
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_BASE 0x46CB184ull
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_BASE 0x46CB198ull
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_BASE 0x46CB1ACull
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_BASE 0x46CB1C0ull
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_BASE 0x46CB1D4ull
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_BASE 0x46CB1E8ull
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_BASE 0x46CB1FCull
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_BASE 0x46CB210ull
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_SECTION 0x1C00
+#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_BASE 0x46CB22Cull
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_BASE 0x46CB240ull
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_BASE 0x46CB254ull
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_BASE 0x46CB268ull
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_SECTION 0x1800
+#define mmDCORE3_MME_CTRL_LO_ARCH_NON_TENSOR_END_BASE 0x46CB280ull
+#define DCORE3_MME_CTRL_LO_ARCH_NON_TENSOR_END_MAX_OFFSET 0x6000
+#define DCORE3_MME_CTRL_LO_ARCH_NON_TENSOR_END_SECTION 0xB800
+#define mmDCORE3_MME_CTRL_LO_MME_AXUSER_BASE 0x46CBE00ull
+#define DCORE3_MME_CTRL_LO_MME_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_MME_CTRL_LO_MME_AXUSER_SECTION 0x8000
+#define mmDCORE3_MME_CTRL_LO_SPECIAL_BASE 0x46CBE80ull
+#define DCORE3_MME_CTRL_LO_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_CTRL_LO_SPECIAL_SECTION 0x1800
+#define mmDCORE3_MME_CTRL_HI_BASE 0x46CC000ull
+#define DCORE3_MME_CTRL_HI_MAX_OFFSET 0x1000
+#define DCORE3_MME_CTRL_HI_SECTION 0x8000
+#define mmDCORE3_MME_CTRL_HI_SHADOW_0_BASE_ADDR_BASE 0x46CC008ull
+#define DCORE3_MME_CTRL_HI_SHADOW_0_BASE_ADDR_MAX_OFFSET 0x2000
+#define DCORE3_MME_CTRL_HI_SHADOW_0_BASE_ADDR_SECTION 0x2000
+#define mmDCORE3_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_BASE 0x46CC028ull
+#define DCORE3_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_MAX_OFFSET 0x1800
+#define DCORE3_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_SECTION 0x1800
+#define mmDCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_A_BASE 0x46CC040ull
+#define DCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_A_MAX_OFFSET 0x5800
+#define DCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_A_SECTION 0x5800
+#define mmDCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_B_BASE 0x46CC098ull
+#define DCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_B_MAX_OFFSET 0x5800
+#define DCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_B_SECTION 0x5800
+#define mmDCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_BASE 0x46CC0F0ull
+#define DCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_MAX_OFFSET 0x5800
+#define DCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_SECTION 0x6C00
+#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_BASE 0x46CC15Cull
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_BASE 0x46CC170ull
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_BASE 0x46CC184ull
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_BASE 0x46CC198ull
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_BASE 0x46CC1ACull
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_BASE 0x46CC1C0ull
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_BASE 0x46CC1D4ull
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_BASE 0x46CC1E8ull
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_BASE 0x46CC1FCull
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_BASE 0x46CC210ull
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_SECTION 0x1C00
+#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_BASE 0x46CC22Cull
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_BASE 0x46CC240ull
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_BASE 0x46CC254ull
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_BASE 0x46CC268ull
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_SECTION 0x1800
+#define mmDCORE3_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_BASE 0x46CC280ull
+#define DCORE3_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_MAX_OFFSET 0x6000
+#define DCORE3_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_SECTION 0x8800
+#define mmDCORE3_MME_CTRL_HI_SHADOW_1_BASE_ADDR_BASE 0x46CC308ull
+#define DCORE3_MME_CTRL_HI_SHADOW_1_BASE_ADDR_MAX_OFFSET 0x2000
+#define DCORE3_MME_CTRL_HI_SHADOW_1_BASE_ADDR_SECTION 0x2000
+#define mmDCORE3_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_BASE 0x46CC328ull
+#define DCORE3_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_MAX_OFFSET 0x1800
+#define DCORE3_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_SECTION 0x1800
+#define mmDCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_A_BASE 0x46CC340ull
+#define DCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_A_MAX_OFFSET 0x5800
+#define DCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_A_SECTION 0x5800
+#define mmDCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_B_BASE 0x46CC398ull
+#define DCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_B_MAX_OFFSET 0x5800
+#define DCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_B_SECTION 0x5800
+#define mmDCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_BASE 0x46CC3F0ull
+#define DCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_MAX_OFFSET 0x5800
+#define DCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_SECTION 0x6C00
+#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_BASE 0x46CC45Cull
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_BASE 0x46CC470ull
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_BASE 0x46CC484ull
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_BASE 0x46CC498ull
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_BASE 0x46CC4ACull
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_BASE 0x46CC4C0ull
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_BASE 0x46CC4D4ull
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_BASE 0x46CC4E8ull
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_BASE 0x46CC4FCull
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_BASE 0x46CC510ull
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_SECTION 0x1C00
+#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_BASE 0x46CC52Cull
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_BASE 0x46CC540ull
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_BASE 0x46CC554ull
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_BASE 0x46CC568ull
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_SECTION 0x1800
+#define mmDCORE3_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_BASE 0x46CC580ull
+#define DCORE3_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_MAX_OFFSET 0x6000
+#define DCORE3_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_SECTION 0x8800
+#define mmDCORE3_MME_CTRL_HI_SHADOW_2_BASE_ADDR_BASE 0x46CC608ull
+#define DCORE3_MME_CTRL_HI_SHADOW_2_BASE_ADDR_MAX_OFFSET 0x2000
+#define DCORE3_MME_CTRL_HI_SHADOW_2_BASE_ADDR_SECTION 0x2000
+#define mmDCORE3_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_BASE 0x46CC628ull
+#define DCORE3_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_MAX_OFFSET 0x1800
+#define DCORE3_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_SECTION 0x1800
+#define mmDCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_A_BASE 0x46CC640ull
+#define DCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_A_MAX_OFFSET 0x5800
+#define DCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_A_SECTION 0x5800
+#define mmDCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_B_BASE 0x46CC698ull
+#define DCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_B_MAX_OFFSET 0x5800
+#define DCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_B_SECTION 0x5800
+#define mmDCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_BASE 0x46CC6F0ull
+#define DCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_MAX_OFFSET 0x5800
+#define DCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_SECTION 0x6C00
+#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_BASE 0x46CC75Cull
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_BASE 0x46CC770ull
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_BASE 0x46CC784ull
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_BASE 0x46CC798ull
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_BASE 0x46CC7ACull
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_BASE 0x46CC7C0ull
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_BASE 0x46CC7D4ull
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_BASE 0x46CC7E8ull
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_BASE 0x46CC7FCull
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_BASE 0x46CC810ull
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_SECTION 0x1C00
+#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_BASE 0x46CC82Cull
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_BASE 0x46CC840ull
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_BASE 0x46CC854ull
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_BASE 0x46CC868ull
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_SECTION 0x1800
+#define mmDCORE3_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_BASE 0x46CC880ull
+#define DCORE3_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_MAX_OFFSET 0x6000
+#define DCORE3_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_SECTION 0x8800
+#define mmDCORE3_MME_CTRL_HI_SHADOW_3_BASE_ADDR_BASE 0x46CC908ull
+#define DCORE3_MME_CTRL_HI_SHADOW_3_BASE_ADDR_MAX_OFFSET 0x2000
+#define DCORE3_MME_CTRL_HI_SHADOW_3_BASE_ADDR_SECTION 0x2000
+#define mmDCORE3_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_BASE 0x46CC928ull
+#define DCORE3_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_MAX_OFFSET 0x1800
+#define DCORE3_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_SECTION 0x1800
+#define mmDCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_A_BASE 0x46CC940ull
+#define DCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_A_MAX_OFFSET 0x5800
+#define DCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_A_SECTION 0x5800
+#define mmDCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_B_BASE 0x46CC998ull
+#define DCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_B_MAX_OFFSET 0x5800
+#define DCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_B_SECTION 0x5800
+#define mmDCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_BASE 0x46CC9F0ull
+#define DCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_MAX_OFFSET 0x5800
+#define DCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_SECTION 0x6C00
+#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_BASE 0x46CCA5Cull
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_BASE 0x46CCA70ull
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_BASE 0x46CCA84ull
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_BASE 0x46CCA98ull
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_BASE 0x46CCAACull
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_BASE 0x46CCAC0ull
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_BASE 0x46CCAD4ull
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_BASE 0x46CCAE8ull
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_BASE 0x46CCAFCull
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_BASE 0x46CCB10ull
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_SECTION 0x1C00
+#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_BASE 0x46CCB2Cull
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_BASE 0x46CCB40ull
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_BASE 0x46CCB54ull
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_SECTION 0x1400
+#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_BASE 0x46CCB68ull
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_SECTION 0x1800
+#define mmDCORE3_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_BASE 0x46CCB80ull
+#define DCORE3_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_MAX_OFFSET 0x6000
+#define DCORE3_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_SECTION 0x3000
+#define mmDCORE3_MME_CTRL_HI_SPECIAL_BASE 0x46CCE80ull
+#define DCORE3_MME_CTRL_HI_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_CTRL_HI_SPECIAL_SECTION 0x1800
+#define mmDCORE3_MME_EU_BIST_BASE 0x46CD000ull
+#define DCORE3_MME_EU_BIST_MAX_OFFSET 0x1000
+#define DCORE3_MME_EU_BIST_SECTION 0xE800
+#define mmDCORE3_MME_EU_BIST_SPECIAL_BASE 0x46CDE80ull
+#define DCORE3_MME_EU_BIST_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_EU_BIST_SPECIAL_SECTION 0x1800
+#define mmDCORE3_MME_CTRL_MSTR_IF_RR_SHRD_HBW_BASE 0x46CE000ull
+#define DCORE3_MME_CTRL_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_MME_CTRL_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE3_MME_CTRL_MSTR_IF_RR_PRVT_HBW_BASE 0x46CE200ull
+#define DCORE3_MME_CTRL_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_MME_CTRL_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE3_MME_CTRL_MSTR_IF_RR_SHRD_LBW_BASE 0x46CE400ull
+#define DCORE3_MME_CTRL_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_MME_CTRL_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE3_MME_CTRL_MSTR_IF_RR_PRVT_LBW_BASE 0x46CE600ull
+#define DCORE3_MME_CTRL_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_MME_CTRL_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE3_MME_CTRL_MSTR_IF_E2E_CRDT_BASE 0x46CE800ull
+#define DCORE3_MME_CTRL_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_MME_CTRL_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE3_MME_CTRL_MSTR_IF_AXUSER_BASE 0x46CEA80ull
+#define DCORE3_MME_CTRL_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_MME_CTRL_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE3_MME_CTRL_MSTR_IF_DBG_HBW_BASE 0x46CEB00ull
+#define DCORE3_MME_CTRL_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_MME_CTRL_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_MME_CTRL_MSTR_IF_DBG_LBW_BASE 0x46CEB80ull
+#define DCORE3_MME_CTRL_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_MME_CTRL_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE3_MME_CTRL_MSTR_IF_CORE_HBW_BASE 0x46CEC00ull
+#define DCORE3_MME_CTRL_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_MME_CTRL_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE3_MME_CTRL_MSTR_IF_CORE_LBW_BASE 0x46CED80ull
+#define DCORE3_MME_CTRL_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_MME_CTRL_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE3_MME_CTRL_MSTR_IF_SPECIAL_BASE 0x46CEE80ull
+#define DCORE3_MME_CTRL_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_CTRL_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE3_MME_QM_ARC_ACP_ENG_BASE 0x46CF000ull
+#define DCORE3_MME_QM_ARC_ACP_ENG_MAX_OFFSET 0x1000
+#define DCORE3_MME_QM_ARC_ACP_ENG_SECTION 0xE800
+#define mmDCORE3_MME_QM_ARC_ACP_ENG_SPECIAL_BASE 0x46CFE80ull
+#define DCORE3_MME_QM_ARC_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_QM_ARC_ACP_ENG_SPECIAL_SECTION 0x1800
+#define mmDCORE3_MME_SBTE0_BASE 0x46D0000ull
+#define DCORE3_MME_SBTE0_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE0_SECTION 0xE800
+#define mmDCORE3_MME_SBTE0_SPECIAL_BASE 0x46D0E80ull
+#define DCORE3_MME_SBTE0_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_SBTE0_SPECIAL_SECTION 0x1800
+#define mmDCORE3_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_BASE 0x46D1000ull
+#define DCORE3_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE3_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_BASE 0x46D1200ull
+#define DCORE3_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE3_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_BASE 0x46D1400ull
+#define DCORE3_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE3_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_BASE 0x46D1600ull
+#define DCORE3_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE3_MME_SBTE0_MSTR_IF_E2E_CRDT_BASE 0x46D1800ull
+#define DCORE3_MME_SBTE0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_MME_SBTE0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE3_MME_SBTE0_MSTR_IF_AXUSER_BASE 0x46D1A80ull
+#define DCORE3_MME_SBTE0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_MME_SBTE0_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE3_MME_SBTE0_MSTR_IF_DBG_HBW_BASE 0x46D1B00ull
+#define DCORE3_MME_SBTE0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_MME_SBTE0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_MME_SBTE0_MSTR_IF_DBG_LBW_BASE 0x46D1B80ull
+#define DCORE3_MME_SBTE0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_MME_SBTE0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE3_MME_SBTE0_MSTR_IF_CORE_HBW_BASE 0x46D1C00ull
+#define DCORE3_MME_SBTE0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_MME_SBTE0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE3_MME_SBTE0_MSTR_IF_CORE_LBW_BASE 0x46D1D80ull
+#define DCORE3_MME_SBTE0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_MME_SBTE0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE3_MME_SBTE0_MSTR_IF_SPECIAL_BASE 0x46D1E80ull
+#define DCORE3_MME_SBTE0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_SBTE0_MSTR_IF_SPECIAL_SECTION 0x6180
+#define mmDCORE3_MME_SBTE1_BASE 0x46D8000ull
+#define DCORE3_MME_SBTE1_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE1_SECTION 0xE800
+#define mmDCORE3_MME_SBTE1_SPECIAL_BASE 0x46D8E80ull
+#define DCORE3_MME_SBTE1_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_SBTE1_SPECIAL_SECTION 0x1800
+#define mmDCORE3_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_BASE 0x46D9000ull
+#define DCORE3_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE3_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_BASE 0x46D9200ull
+#define DCORE3_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE3_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_BASE 0x46D9400ull
+#define DCORE3_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE3_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_BASE 0x46D9600ull
+#define DCORE3_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE3_MME_SBTE1_MSTR_IF_E2E_CRDT_BASE 0x46D9800ull
+#define DCORE3_MME_SBTE1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_MME_SBTE1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE3_MME_SBTE1_MSTR_IF_AXUSER_BASE 0x46D9A80ull
+#define DCORE3_MME_SBTE1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_MME_SBTE1_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE3_MME_SBTE1_MSTR_IF_DBG_HBW_BASE 0x46D9B00ull
+#define DCORE3_MME_SBTE1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_MME_SBTE1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_MME_SBTE1_MSTR_IF_DBG_LBW_BASE 0x46D9B80ull
+#define DCORE3_MME_SBTE1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_MME_SBTE1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE3_MME_SBTE1_MSTR_IF_CORE_HBW_BASE 0x46D9C00ull
+#define DCORE3_MME_SBTE1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_MME_SBTE1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE3_MME_SBTE1_MSTR_IF_CORE_LBW_BASE 0x46D9D80ull
+#define DCORE3_MME_SBTE1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_MME_SBTE1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE3_MME_SBTE1_MSTR_IF_SPECIAL_BASE 0x46D9E80ull
+#define DCORE3_MME_SBTE1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_SBTE1_MSTR_IF_SPECIAL_SECTION 0x6180
+#define mmDCORE3_MME_SBTE2_BASE 0x46E0000ull
+#define DCORE3_MME_SBTE2_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE2_SECTION 0xE800
+#define mmDCORE3_MME_SBTE2_SPECIAL_BASE 0x46E0E80ull
+#define DCORE3_MME_SBTE2_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_SBTE2_SPECIAL_SECTION 0x1800
+#define mmDCORE3_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_BASE 0x46E1000ull
+#define DCORE3_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE3_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_BASE 0x46E1200ull
+#define DCORE3_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE3_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_BASE 0x46E1400ull
+#define DCORE3_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE3_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_BASE 0x46E1600ull
+#define DCORE3_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE3_MME_SBTE2_MSTR_IF_E2E_CRDT_BASE 0x46E1800ull
+#define DCORE3_MME_SBTE2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_MME_SBTE2_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE3_MME_SBTE2_MSTR_IF_AXUSER_BASE 0x46E1A80ull
+#define DCORE3_MME_SBTE2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_MME_SBTE2_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE3_MME_SBTE2_MSTR_IF_DBG_HBW_BASE 0x46E1B00ull
+#define DCORE3_MME_SBTE2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_MME_SBTE2_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_MME_SBTE2_MSTR_IF_DBG_LBW_BASE 0x46E1B80ull
+#define DCORE3_MME_SBTE2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_MME_SBTE2_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE3_MME_SBTE2_MSTR_IF_CORE_HBW_BASE 0x46E1C00ull
+#define DCORE3_MME_SBTE2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_MME_SBTE2_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE3_MME_SBTE2_MSTR_IF_CORE_LBW_BASE 0x46E1D80ull
+#define DCORE3_MME_SBTE2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_MME_SBTE2_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE3_MME_SBTE2_MSTR_IF_SPECIAL_BASE 0x46E1E80ull
+#define DCORE3_MME_SBTE2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_SBTE2_MSTR_IF_SPECIAL_SECTION 0x6180
+#define mmDCORE3_MME_SBTE3_BASE 0x46E8000ull
+#define DCORE3_MME_SBTE3_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE3_SECTION 0xE800
+#define mmDCORE3_MME_SBTE3_SPECIAL_BASE 0x46E8E80ull
+#define DCORE3_MME_SBTE3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_SBTE3_SPECIAL_SECTION 0x1800
+#define mmDCORE3_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_BASE 0x46E9000ull
+#define DCORE3_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE3_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_BASE 0x46E9200ull
+#define DCORE3_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE3_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_BASE 0x46E9400ull
+#define DCORE3_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE3_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_BASE 0x46E9600ull
+#define DCORE3_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE3_MME_SBTE3_MSTR_IF_E2E_CRDT_BASE 0x46E9800ull
+#define DCORE3_MME_SBTE3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_MME_SBTE3_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE3_MME_SBTE3_MSTR_IF_AXUSER_BASE 0x46E9A80ull
+#define DCORE3_MME_SBTE3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_MME_SBTE3_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE3_MME_SBTE3_MSTR_IF_DBG_HBW_BASE 0x46E9B00ull
+#define DCORE3_MME_SBTE3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_MME_SBTE3_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_MME_SBTE3_MSTR_IF_DBG_LBW_BASE 0x46E9B80ull
+#define DCORE3_MME_SBTE3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_MME_SBTE3_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE3_MME_SBTE3_MSTR_IF_CORE_HBW_BASE 0x46E9C00ull
+#define DCORE3_MME_SBTE3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_MME_SBTE3_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE3_MME_SBTE3_MSTR_IF_CORE_LBW_BASE 0x46E9D80ull
+#define DCORE3_MME_SBTE3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_MME_SBTE3_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE3_MME_SBTE3_MSTR_IF_SPECIAL_BASE 0x46E9E80ull
+#define DCORE3_MME_SBTE3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_SBTE3_MSTR_IF_SPECIAL_SECTION 0x6180
+#define mmDCORE3_MME_SBTE4_BASE 0x46F0000ull
+#define DCORE3_MME_SBTE4_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE4_SECTION 0xE800
+#define mmDCORE3_MME_SBTE4_SPECIAL_BASE 0x46F0E80ull
+#define DCORE3_MME_SBTE4_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_SBTE4_SPECIAL_SECTION 0x1800
+#define mmDCORE3_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_BASE 0x46F1000ull
+#define DCORE3_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE3_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_BASE 0x46F1200ull
+#define DCORE3_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE3_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_BASE 0x46F1400ull
+#define DCORE3_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE3_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_BASE 0x46F1600ull
+#define DCORE3_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE3_MME_SBTE4_MSTR_IF_E2E_CRDT_BASE 0x46F1800ull
+#define DCORE3_MME_SBTE4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_MME_SBTE4_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE3_MME_SBTE4_MSTR_IF_AXUSER_BASE 0x46F1A80ull
+#define DCORE3_MME_SBTE4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_MME_SBTE4_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE3_MME_SBTE4_MSTR_IF_DBG_HBW_BASE 0x46F1B00ull
+#define DCORE3_MME_SBTE4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_MME_SBTE4_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_MME_SBTE4_MSTR_IF_DBG_LBW_BASE 0x46F1B80ull
+#define DCORE3_MME_SBTE4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_MME_SBTE4_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE3_MME_SBTE4_MSTR_IF_CORE_HBW_BASE 0x46F1C00ull
+#define DCORE3_MME_SBTE4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_MME_SBTE4_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE3_MME_SBTE4_MSTR_IF_CORE_LBW_BASE 0x46F1D80ull
+#define DCORE3_MME_SBTE4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_MME_SBTE4_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE3_MME_SBTE4_MSTR_IF_SPECIAL_BASE 0x46F1E80ull
+#define DCORE3_MME_SBTE4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_SBTE4_MSTR_IF_SPECIAL_SECTION 0x6180
+#define mmDCORE3_MME_ACC_BASE 0x46F8000ull
+#define DCORE3_MME_ACC_MAX_OFFSET 0x1000
+#define DCORE3_MME_ACC_SECTION 0xE800
+#define mmDCORE3_MME_ACC_SPECIAL_BASE 0x46F8E80ull
+#define DCORE3_MME_ACC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_ACC_SPECIAL_SECTION 0x1800
+#define mmDCORE3_MME_WB0_MSTR_IF_RR_SHRD_HBW_BASE 0x46F9000ull
+#define DCORE3_MME_WB0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_MME_WB0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE3_MME_WB0_MSTR_IF_RR_PRVT_HBW_BASE 0x46F9200ull
+#define DCORE3_MME_WB0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_MME_WB0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE3_MME_WB0_MSTR_IF_RR_SHRD_LBW_BASE 0x46F9400ull
+#define DCORE3_MME_WB0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_MME_WB0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE3_MME_WB0_MSTR_IF_RR_PRVT_LBW_BASE 0x46F9600ull
+#define DCORE3_MME_WB0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_MME_WB0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE3_MME_WB0_MSTR_IF_E2E_CRDT_BASE 0x46F9800ull
+#define DCORE3_MME_WB0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_MME_WB0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE3_MME_WB0_MSTR_IF_AXUSER_BASE 0x46F9A80ull
+#define DCORE3_MME_WB0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_MME_WB0_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE3_MME_WB0_MSTR_IF_DBG_HBW_BASE 0x46F9B00ull
+#define DCORE3_MME_WB0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_MME_WB0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_MME_WB0_MSTR_IF_DBG_LBW_BASE 0x46F9B80ull
+#define DCORE3_MME_WB0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_MME_WB0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE3_MME_WB0_MSTR_IF_CORE_HBW_BASE 0x46F9C00ull
+#define DCORE3_MME_WB0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_MME_WB0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE3_MME_WB0_MSTR_IF_CORE_LBW_BASE 0x46F9D80ull
+#define DCORE3_MME_WB0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_MME_WB0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE3_MME_WB0_MSTR_IF_SPECIAL_BASE 0x46F9E80ull
+#define DCORE3_MME_WB0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_WB0_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE3_MME_WB1_MSTR_IF_RR_SHRD_HBW_BASE 0x46FA000ull
+#define DCORE3_MME_WB1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_MME_WB1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE3_MME_WB1_MSTR_IF_RR_PRVT_HBW_BASE 0x46FA200ull
+#define DCORE3_MME_WB1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_MME_WB1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE3_MME_WB1_MSTR_IF_RR_SHRD_LBW_BASE 0x46FA400ull
+#define DCORE3_MME_WB1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_MME_WB1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE3_MME_WB1_MSTR_IF_RR_PRVT_LBW_BASE 0x46FA600ull
+#define DCORE3_MME_WB1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_MME_WB1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE3_MME_WB1_MSTR_IF_E2E_CRDT_BASE 0x46FA800ull
+#define DCORE3_MME_WB1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_MME_WB1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE3_MME_WB1_MSTR_IF_AXUSER_BASE 0x46FAA80ull
+#define DCORE3_MME_WB1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_MME_WB1_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE3_MME_WB1_MSTR_IF_DBG_HBW_BASE 0x46FAB00ull
+#define DCORE3_MME_WB1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_MME_WB1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_MME_WB1_MSTR_IF_DBG_LBW_BASE 0x46FAB80ull
+#define DCORE3_MME_WB1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_MME_WB1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE3_MME_WB1_MSTR_IF_CORE_HBW_BASE 0x46FAC00ull
+#define DCORE3_MME_WB1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_MME_WB1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE3_MME_WB1_MSTR_IF_CORE_LBW_BASE 0x46FAD80ull
+#define DCORE3_MME_WB1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_MME_WB1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE3_MME_WB1_MSTR_IF_SPECIAL_BASE 0x46FAE80ull
+#define DCORE3_MME_WB1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_MME_WB1_MSTR_IF_SPECIAL_SECTION 0x5180
+#define mmDCORE3_SYNC_MNGR_OBJS_BASE 0x4700000ull
+#define DCORE3_SYNC_MNGR_OBJS_MAX_OFFSET 0x15A00
+#define DCORE3_SYNC_MNGR_OBJS_SECTION 0x1E000
+#define mmDCORE3_SYNC_MNGR_GLBL_BASE 0x471E000ull
+#define DCORE3_SYNC_MNGR_GLBL_MAX_OFFSET 0x1000
+#define DCORE3_SYNC_MNGR_GLBL_SECTION 0xE800
+#define mmDCORE3_SYNC_MNGR_GLBL_SPECIAL_BASE 0x471EE80ull
+#define DCORE3_SYNC_MNGR_GLBL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SYNC_MNGR_GLBL_SPECIAL_SECTION 0x1800
+#define mmDCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_BASE 0x471F000ull
+#define DCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_BASE 0x471F200ull
+#define DCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_BASE 0x471F400ull
+#define DCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_BASE 0x471F600ull
+#define DCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE3_SYNC_MNGR_MSTR_IF_E2E_CRDT_BASE 0x471F800ull
+#define DCORE3_SYNC_MNGR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_SYNC_MNGR_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE3_SYNC_MNGR_MSTR_IF_AXUSER_BASE 0x471FA80ull
+#define DCORE3_SYNC_MNGR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_SYNC_MNGR_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE3_SYNC_MNGR_MSTR_IF_DBG_HBW_BASE 0x471FB00ull
+#define DCORE3_SYNC_MNGR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_SYNC_MNGR_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_SYNC_MNGR_MSTR_IF_DBG_LBW_BASE 0x471FB80ull
+#define DCORE3_SYNC_MNGR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_SYNC_MNGR_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE3_SYNC_MNGR_MSTR_IF_CORE_HBW_BASE 0x471FC00ull
+#define DCORE3_SYNC_MNGR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_SYNC_MNGR_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE3_SYNC_MNGR_MSTR_IF_CORE_LBW_BASE 0x471FD80ull
+#define DCORE3_SYNC_MNGR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_SYNC_MNGR_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE3_SYNC_MNGR_MSTR_IF_SPECIAL_BASE 0x471FE80ull
+#define DCORE3_SYNC_MNGR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SYNC_MNGR_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE3_HIF0_BASE 0x4720000ull
+#define DCORE3_HIF0_MAX_OFFSET 0x1000
+#define DCORE3_HIF0_SECTION 0xE800
+#define mmDCORE3_HIF0_SPECIAL_BASE 0x4720E80ull
+#define DCORE3_HIF0_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HIF0_SPECIAL_SECTION 0x3180
+#define mmDCORE3_HIF1_BASE 0x4724000ull
+#define DCORE3_HIF1_MAX_OFFSET 0x1000
+#define DCORE3_HIF1_SECTION 0xE800
+#define mmDCORE3_HIF1_SPECIAL_BASE 0x4724E80ull
+#define DCORE3_HIF1_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HIF1_SPECIAL_SECTION 0x3180
+#define mmDCORE3_HIF2_BASE 0x4728000ull
+#define DCORE3_HIF2_MAX_OFFSET 0x1000
+#define DCORE3_HIF2_SECTION 0xE800
+#define mmDCORE3_HIF2_SPECIAL_BASE 0x4728E80ull
+#define DCORE3_HIF2_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HIF2_SPECIAL_SECTION 0x3180
+#define mmDCORE3_HIF3_BASE 0x472C000ull
+#define DCORE3_HIF3_MAX_OFFSET 0x1000
+#define DCORE3_HIF3_SECTION 0xE800
+#define mmDCORE3_HIF3_SPECIAL_BASE 0x472CE80ull
+#define DCORE3_HIF3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HIF3_SPECIAL_SECTION 0x13180
+#define mmDCORE3_RTR0_CTRL_BASE 0x4740000ull
+#define DCORE3_RTR0_CTRL_MAX_OFFSET 0x1000
+#define DCORE3_RTR0_CTRL_SECTION 0xE800
+#define mmDCORE3_RTR0_CTRL_SPECIAL_BASE 0x4740E80ull
+#define DCORE3_RTR0_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR0_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE3_RTR0_H3_BASE 0x4741000ull
+#define DCORE3_RTR0_H3_MAX_OFFSET 0x1000
+#define DCORE3_RTR0_H3_SECTION 0xE800
+#define mmDCORE3_RTR0_H3_SPECIAL_BASE 0x4741E80ull
+#define DCORE3_RTR0_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR0_H3_SPECIAL_SECTION 0x1800
+#define mmDCORE3_RTR0_MSTR_IF_RR_SHRD_HBW_BASE 0x4742000ull
+#define DCORE3_RTR0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_RTR0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE3_RTR0_MSTR_IF_RR_PRVT_HBW_BASE 0x4742200ull
+#define DCORE3_RTR0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_RTR0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE3_RTR0_MSTR_IF_RR_SHRD_LBW_BASE 0x4742400ull
+#define DCORE3_RTR0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_RTR0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE3_RTR0_MSTR_IF_RR_PRVT_LBW_BASE 0x4742600ull
+#define DCORE3_RTR0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_RTR0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE3_RTR0_MSTR_IF_E2E_CRDT_BASE 0x4742800ull
+#define DCORE3_RTR0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_RTR0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE3_RTR0_MSTR_IF_AXUSER_BASE 0x4742A80ull
+#define DCORE3_RTR0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_RTR0_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE3_RTR0_MSTR_IF_DBG_HBW_BASE 0x4742B00ull
+#define DCORE3_RTR0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_RTR0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_RTR0_MSTR_IF_DBG_LBW_BASE 0x4742B80ull
+#define DCORE3_RTR0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_RTR0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE3_RTR0_MSTR_IF_CORE_HBW_BASE 0x4742C00ull
+#define DCORE3_RTR0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_RTR0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE3_RTR0_MSTR_IF_CORE_LBW_BASE 0x4742D80ull
+#define DCORE3_RTR0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_RTR0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE3_RTR0_MSTR_IF_SPECIAL_BASE 0x4742E80ull
+#define DCORE3_RTR0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR0_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE3_RTR0_ADD_DEC_HBW_BASE 0x4743000ull
+#define DCORE3_RTR0_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE3_RTR0_ADD_DEC_HBW_SECTION 0x4000
+#define mmDCORE3_RTR0_ADD_DEC_LBW_BASE 0x4743400ull
+#define DCORE3_RTR0_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE3_RTR0_ADD_DEC_LBW_SECTION 0xA800
+#define mmDCORE3_RTR0_ADD_DEC_SPECIAL_BASE 0x4743E80ull
+#define DCORE3_RTR0_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR0_ADD_DEC_SPECIAL_SECTION 0x1800
+#define mmDCORE3_RTR0_BASE 0x4744000ull
+#define DCORE3_RTR0_MAX_OFFSET 0x1000
+#define DCORE3_RTR0_SECTION 0x3000
+#define mmDCORE3_RTR0_HBW_RD_RQ_LL_STAT_BASE 0x4744300ull
+#define DCORE3_RTR0_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR0_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR0_HBW_RD_RS_LL_STAT_BASE 0x4744340ull
+#define DCORE3_RTR0_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR0_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR0_HBW_WR_RQ_LL_STAT_BASE 0x4744380ull
+#define DCORE3_RTR0_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR0_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR0_HBW_WR_RS_LL_STAT_BASE 0x47443C0ull
+#define DCORE3_RTR0_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR0_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR0_LBW_RD_RQ_LL_STAT_BASE 0x4744400ull
+#define DCORE3_RTR0_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR0_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR0_LBW_RD_RS_LL_STAT_BASE 0x4744440ull
+#define DCORE3_RTR0_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR0_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR0_LBW_WR_RQ_LL_STAT_BASE 0x4744480ull
+#define DCORE3_RTR0_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR0_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR0_LBW_WR_RS_LL_STAT_BASE 0x47444C0ull
+#define DCORE3_RTR0_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR0_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR0_HBW_MFIFO_BASE 0x4744500ull
+#define DCORE3_RTR0_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE3_RTR0_HBW_MFIFO_SECTION 0x4000
+#define mmDCORE3_RTR0_E2E_RD_LL_STAT_BASE 0x4744540ull
+#define DCORE3_RTR0_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR0_E2E_RD_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR0_E2E_WR_LL_STAT_BASE 0x4744580ull
+#define DCORE3_RTR0_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR0_E2E_WR_LL_STAT_SECTION 0x8000
+#define mmDCORE3_RTR0_RTR_HBW_XACT_STAT_BASE 0x4744600ull
+#define DCORE3_RTR0_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR0_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE3_RTR0_RTR_LBW_XACT_STAT_BASE 0x4744680ull
+#define DCORE3_RTR0_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR0_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE3_RTR0_RTR_E2E_XACT_STAT_BASE 0x4744700ull
+#define DCORE3_RTR0_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR0_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define mmDCORE3_RTR0_SPECIAL_BASE 0x4744E80ull
+#define DCORE3_RTR0_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR0_SPECIAL_SECTION 0x1800
+#define mmDCORE3_RTR0_DBG_ADDR_BASE 0x4745000ull
+#define DCORE3_RTR0_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE3_RTR0_DBG_ADDR_SECTION 0xE800
+#define mmDCORE3_RTR0_DBG_ADDR_SPECIAL_BASE 0x4745E80ull
+#define DCORE3_RTR0_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR0_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define mmDCORE3_RTR1_CTRL_BASE 0x4748000ull
+#define DCORE3_RTR1_CTRL_MAX_OFFSET 0x1000
+#define DCORE3_RTR1_CTRL_SECTION 0xE800
+#define mmDCORE3_RTR1_CTRL_SPECIAL_BASE 0x4748E80ull
+#define DCORE3_RTR1_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR1_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE3_RTR1_H3_BASE 0x4749000ull
+#define DCORE3_RTR1_H3_MAX_OFFSET 0x1000
+#define DCORE3_RTR1_H3_SECTION 0xE800
+#define mmDCORE3_RTR1_H3_SPECIAL_BASE 0x4749E80ull
+#define DCORE3_RTR1_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR1_H3_SPECIAL_SECTION 0x1800
+#define mmDCORE3_RTR1_MSTR_IF_RR_SHRD_HBW_BASE 0x474A000ull
+#define DCORE3_RTR1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_RTR1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE3_RTR1_MSTR_IF_RR_PRVT_HBW_BASE 0x474A200ull
+#define DCORE3_RTR1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_RTR1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE3_RTR1_MSTR_IF_RR_SHRD_LBW_BASE 0x474A400ull
+#define DCORE3_RTR1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_RTR1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE3_RTR1_MSTR_IF_RR_PRVT_LBW_BASE 0x474A600ull
+#define DCORE3_RTR1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_RTR1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE3_RTR1_MSTR_IF_E2E_CRDT_BASE 0x474A800ull
+#define DCORE3_RTR1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_RTR1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE3_RTR1_MSTR_IF_AXUSER_BASE 0x474AA80ull
+#define DCORE3_RTR1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_RTR1_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE3_RTR1_MSTR_IF_DBG_HBW_BASE 0x474AB00ull
+#define DCORE3_RTR1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_RTR1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_RTR1_MSTR_IF_DBG_LBW_BASE 0x474AB80ull
+#define DCORE3_RTR1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_RTR1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE3_RTR1_MSTR_IF_CORE_HBW_BASE 0x474AC00ull
+#define DCORE3_RTR1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_RTR1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE3_RTR1_MSTR_IF_CORE_LBW_BASE 0x474AD80ull
+#define DCORE3_RTR1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_RTR1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE3_RTR1_MSTR_IF_SPECIAL_BASE 0x474AE80ull
+#define DCORE3_RTR1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR1_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE3_RTR1_ADD_DEC_HBW_BASE 0x474B000ull
+#define DCORE3_RTR1_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE3_RTR1_ADD_DEC_HBW_SECTION 0x4000
+#define mmDCORE3_RTR1_ADD_DEC_LBW_BASE 0x474B400ull
+#define DCORE3_RTR1_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE3_RTR1_ADD_DEC_LBW_SECTION 0xA800
+#define mmDCORE3_RTR1_ADD_DEC_SPECIAL_BASE 0x474BE80ull
+#define DCORE3_RTR1_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR1_ADD_DEC_SPECIAL_SECTION 0x1800
+#define mmDCORE3_RTR1_BASE 0x474C000ull
+#define DCORE3_RTR1_MAX_OFFSET 0x1000
+#define DCORE3_RTR1_SECTION 0x3000
+#define mmDCORE3_RTR1_HBW_RD_RQ_LL_STAT_BASE 0x474C300ull
+#define DCORE3_RTR1_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR1_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR1_HBW_RD_RS_LL_STAT_BASE 0x474C340ull
+#define DCORE3_RTR1_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR1_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR1_HBW_WR_RQ_LL_STAT_BASE 0x474C380ull
+#define DCORE3_RTR1_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR1_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR1_HBW_WR_RS_LL_STAT_BASE 0x474C3C0ull
+#define DCORE3_RTR1_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR1_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR1_LBW_RD_RQ_LL_STAT_BASE 0x474C400ull
+#define DCORE3_RTR1_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR1_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR1_LBW_RD_RS_LL_STAT_BASE 0x474C440ull
+#define DCORE3_RTR1_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR1_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR1_LBW_WR_RQ_LL_STAT_BASE 0x474C480ull
+#define DCORE3_RTR1_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR1_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR1_LBW_WR_RS_LL_STAT_BASE 0x474C4C0ull
+#define DCORE3_RTR1_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR1_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR1_HBW_MFIFO_BASE 0x474C500ull
+#define DCORE3_RTR1_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE3_RTR1_HBW_MFIFO_SECTION 0x4000
+#define mmDCORE3_RTR1_E2E_RD_LL_STAT_BASE 0x474C540ull
+#define DCORE3_RTR1_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR1_E2E_RD_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR1_E2E_WR_LL_STAT_BASE 0x474C580ull
+#define DCORE3_RTR1_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR1_E2E_WR_LL_STAT_SECTION 0x8000
+#define mmDCORE3_RTR1_RTR_HBW_XACT_STAT_BASE 0x474C600ull
+#define DCORE3_RTR1_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR1_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE3_RTR1_RTR_LBW_XACT_STAT_BASE 0x474C680ull
+#define DCORE3_RTR1_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR1_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE3_RTR1_RTR_E2E_XACT_STAT_BASE 0x474C700ull
+#define DCORE3_RTR1_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR1_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define mmDCORE3_RTR1_SPECIAL_BASE 0x474CE80ull
+#define DCORE3_RTR1_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR1_SPECIAL_SECTION 0x1800
+#define mmDCORE3_RTR1_DBG_ADDR_BASE 0x474D000ull
+#define DCORE3_RTR1_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE3_RTR1_DBG_ADDR_SECTION 0xE800
+#define mmDCORE3_RTR1_DBG_ADDR_SPECIAL_BASE 0x474DE80ull
+#define DCORE3_RTR1_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR1_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define mmDCORE3_RTR2_CTRL_BASE 0x4750000ull
+#define DCORE3_RTR2_CTRL_MAX_OFFSET 0x1000
+#define DCORE3_RTR2_CTRL_SECTION 0xE800
+#define mmDCORE3_RTR2_CTRL_SPECIAL_BASE 0x4750E80ull
+#define DCORE3_RTR2_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR2_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE3_RTR2_H3_BASE 0x4751000ull
+#define DCORE3_RTR2_H3_MAX_OFFSET 0x1000
+#define DCORE3_RTR2_H3_SECTION 0xE800
+#define mmDCORE3_RTR2_H3_SPECIAL_BASE 0x4751E80ull
+#define DCORE3_RTR2_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR2_H3_SPECIAL_SECTION 0x1800
+#define mmDCORE3_RTR2_MSTR_IF_RR_SHRD_HBW_BASE 0x4752000ull
+#define DCORE3_RTR2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_RTR2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE3_RTR2_MSTR_IF_RR_PRVT_HBW_BASE 0x4752200ull
+#define DCORE3_RTR2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_RTR2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE3_RTR2_MSTR_IF_RR_SHRD_LBW_BASE 0x4752400ull
+#define DCORE3_RTR2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_RTR2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE3_RTR2_MSTR_IF_RR_PRVT_LBW_BASE 0x4752600ull
+#define DCORE3_RTR2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_RTR2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE3_RTR2_MSTR_IF_E2E_CRDT_BASE 0x4752800ull
+#define DCORE3_RTR2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_RTR2_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE3_RTR2_MSTR_IF_AXUSER_BASE 0x4752A80ull
+#define DCORE3_RTR2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_RTR2_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE3_RTR2_MSTR_IF_DBG_HBW_BASE 0x4752B00ull
+#define DCORE3_RTR2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_RTR2_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_RTR2_MSTR_IF_DBG_LBW_BASE 0x4752B80ull
+#define DCORE3_RTR2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_RTR2_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE3_RTR2_MSTR_IF_CORE_HBW_BASE 0x4752C00ull
+#define DCORE3_RTR2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_RTR2_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE3_RTR2_MSTR_IF_CORE_LBW_BASE 0x4752D80ull
+#define DCORE3_RTR2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_RTR2_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE3_RTR2_MSTR_IF_SPECIAL_BASE 0x4752E80ull
+#define DCORE3_RTR2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR2_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE3_RTR2_ADD_DEC_HBW_BASE 0x4753000ull
+#define DCORE3_RTR2_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE3_RTR2_ADD_DEC_HBW_SECTION 0x4000
+#define mmDCORE3_RTR2_ADD_DEC_LBW_BASE 0x4753400ull
+#define DCORE3_RTR2_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE3_RTR2_ADD_DEC_LBW_SECTION 0xA800
+#define mmDCORE3_RTR2_ADD_DEC_SPECIAL_BASE 0x4753E80ull
+#define DCORE3_RTR2_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR2_ADD_DEC_SPECIAL_SECTION 0x1800
+#define mmDCORE3_RTR2_BASE 0x4754000ull
+#define DCORE3_RTR2_MAX_OFFSET 0x1000
+#define DCORE3_RTR2_SECTION 0x3000
+#define mmDCORE3_RTR2_HBW_RD_RQ_LL_STAT_BASE 0x4754300ull
+#define DCORE3_RTR2_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR2_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR2_HBW_RD_RS_LL_STAT_BASE 0x4754340ull
+#define DCORE3_RTR2_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR2_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR2_HBW_WR_RQ_LL_STAT_BASE 0x4754380ull
+#define DCORE3_RTR2_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR2_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR2_HBW_WR_RS_LL_STAT_BASE 0x47543C0ull
+#define DCORE3_RTR2_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR2_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR2_LBW_RD_RQ_LL_STAT_BASE 0x4754400ull
+#define DCORE3_RTR2_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR2_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR2_LBW_RD_RS_LL_STAT_BASE 0x4754440ull
+#define DCORE3_RTR2_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR2_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR2_LBW_WR_RQ_LL_STAT_BASE 0x4754480ull
+#define DCORE3_RTR2_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR2_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR2_LBW_WR_RS_LL_STAT_BASE 0x47544C0ull
+#define DCORE3_RTR2_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR2_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR2_HBW_MFIFO_BASE 0x4754500ull
+#define DCORE3_RTR2_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE3_RTR2_HBW_MFIFO_SECTION 0x4000
+#define mmDCORE3_RTR2_E2E_RD_LL_STAT_BASE 0x4754540ull
+#define DCORE3_RTR2_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR2_E2E_RD_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR2_E2E_WR_LL_STAT_BASE 0x4754580ull
+#define DCORE3_RTR2_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR2_E2E_WR_LL_STAT_SECTION 0x8000
+#define mmDCORE3_RTR2_RTR_HBW_XACT_STAT_BASE 0x4754600ull
+#define DCORE3_RTR2_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR2_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE3_RTR2_RTR_LBW_XACT_STAT_BASE 0x4754680ull
+#define DCORE3_RTR2_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR2_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE3_RTR2_RTR_E2E_XACT_STAT_BASE 0x4754700ull
+#define DCORE3_RTR2_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR2_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define mmDCORE3_RTR2_SPECIAL_BASE 0x4754E80ull
+#define DCORE3_RTR2_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR2_SPECIAL_SECTION 0x1800
+#define mmDCORE3_RTR2_DBG_ADDR_BASE 0x4755000ull
+#define DCORE3_RTR2_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE3_RTR2_DBG_ADDR_SECTION 0xE800
+#define mmDCORE3_RTR2_DBG_ADDR_SPECIAL_BASE 0x4755E80ull
+#define DCORE3_RTR2_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR2_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define mmDCORE3_RTR3_CTRL_BASE 0x4758000ull
+#define DCORE3_RTR3_CTRL_MAX_OFFSET 0x1000
+#define DCORE3_RTR3_CTRL_SECTION 0xE800
+#define mmDCORE3_RTR3_CTRL_SPECIAL_BASE 0x4758E80ull
+#define DCORE3_RTR3_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR3_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE3_RTR3_H3_BASE 0x4759000ull
+#define DCORE3_RTR3_H3_MAX_OFFSET 0x1000
+#define DCORE3_RTR3_H3_SECTION 0xE800
+#define mmDCORE3_RTR3_H3_SPECIAL_BASE 0x4759E80ull
+#define DCORE3_RTR3_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR3_H3_SPECIAL_SECTION 0x1800
+#define mmDCORE3_RTR3_MSTR_IF_RR_SHRD_HBW_BASE 0x475A000ull
+#define DCORE3_RTR3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_RTR3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE3_RTR3_MSTR_IF_RR_PRVT_HBW_BASE 0x475A200ull
+#define DCORE3_RTR3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_RTR3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE3_RTR3_MSTR_IF_RR_SHRD_LBW_BASE 0x475A400ull
+#define DCORE3_RTR3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_RTR3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE3_RTR3_MSTR_IF_RR_PRVT_LBW_BASE 0x475A600ull
+#define DCORE3_RTR3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_RTR3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE3_RTR3_MSTR_IF_E2E_CRDT_BASE 0x475A800ull
+#define DCORE3_RTR3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_RTR3_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE3_RTR3_MSTR_IF_AXUSER_BASE 0x475AA80ull
+#define DCORE3_RTR3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_RTR3_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE3_RTR3_MSTR_IF_DBG_HBW_BASE 0x475AB00ull
+#define DCORE3_RTR3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_RTR3_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_RTR3_MSTR_IF_DBG_LBW_BASE 0x475AB80ull
+#define DCORE3_RTR3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_RTR3_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE3_RTR3_MSTR_IF_CORE_HBW_BASE 0x475AC00ull
+#define DCORE3_RTR3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_RTR3_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE3_RTR3_MSTR_IF_CORE_LBW_BASE 0x475AD80ull
+#define DCORE3_RTR3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_RTR3_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE3_RTR3_MSTR_IF_SPECIAL_BASE 0x475AE80ull
+#define DCORE3_RTR3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR3_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE3_RTR3_ADD_DEC_HBW_BASE 0x475B000ull
+#define DCORE3_RTR3_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE3_RTR3_ADD_DEC_HBW_SECTION 0x4000
+#define mmDCORE3_RTR3_ADD_DEC_LBW_BASE 0x475B400ull
+#define DCORE3_RTR3_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE3_RTR3_ADD_DEC_LBW_SECTION 0xA800
+#define mmDCORE3_RTR3_ADD_DEC_SPECIAL_BASE 0x475BE80ull
+#define DCORE3_RTR3_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR3_ADD_DEC_SPECIAL_SECTION 0x1800
+#define mmDCORE3_RTR3_BASE 0x475C000ull
+#define DCORE3_RTR3_MAX_OFFSET 0x1000
+#define DCORE3_RTR3_SECTION 0x3000
+#define mmDCORE3_RTR3_HBW_RD_RQ_LL_STAT_BASE 0x475C300ull
+#define DCORE3_RTR3_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR3_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR3_HBW_RD_RS_LL_STAT_BASE 0x475C340ull
+#define DCORE3_RTR3_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR3_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR3_HBW_WR_RQ_LL_STAT_BASE 0x475C380ull
+#define DCORE3_RTR3_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR3_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR3_HBW_WR_RS_LL_STAT_BASE 0x475C3C0ull
+#define DCORE3_RTR3_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR3_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR3_LBW_RD_RQ_LL_STAT_BASE 0x475C400ull
+#define DCORE3_RTR3_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR3_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR3_LBW_RD_RS_LL_STAT_BASE 0x475C440ull
+#define DCORE3_RTR3_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR3_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR3_LBW_WR_RQ_LL_STAT_BASE 0x475C480ull
+#define DCORE3_RTR3_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR3_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR3_LBW_WR_RS_LL_STAT_BASE 0x475C4C0ull
+#define DCORE3_RTR3_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR3_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR3_HBW_MFIFO_BASE 0x475C500ull
+#define DCORE3_RTR3_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE3_RTR3_HBW_MFIFO_SECTION 0x4000
+#define mmDCORE3_RTR3_E2E_RD_LL_STAT_BASE 0x475C540ull
+#define DCORE3_RTR3_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR3_E2E_RD_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR3_E2E_WR_LL_STAT_BASE 0x475C580ull
+#define DCORE3_RTR3_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR3_E2E_WR_LL_STAT_SECTION 0x8000
+#define mmDCORE3_RTR3_RTR_HBW_XACT_STAT_BASE 0x475C600ull
+#define DCORE3_RTR3_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR3_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE3_RTR3_RTR_LBW_XACT_STAT_BASE 0x475C680ull
+#define DCORE3_RTR3_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR3_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE3_RTR3_RTR_E2E_XACT_STAT_BASE 0x475C700ull
+#define DCORE3_RTR3_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR3_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define mmDCORE3_RTR3_SPECIAL_BASE 0x475CE80ull
+#define DCORE3_RTR3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR3_SPECIAL_SECTION 0x1800
+#define mmDCORE3_RTR3_DBG_ADDR_BASE 0x475D000ull
+#define DCORE3_RTR3_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE3_RTR3_DBG_ADDR_SECTION 0xE800
+#define mmDCORE3_RTR3_DBG_ADDR_SPECIAL_BASE 0x475DE80ull
+#define DCORE3_RTR3_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR3_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define mmDCORE3_RTR4_CTRL_BASE 0x4760000ull
+#define DCORE3_RTR4_CTRL_MAX_OFFSET 0x1000
+#define DCORE3_RTR4_CTRL_SECTION 0xE800
+#define mmDCORE3_RTR4_CTRL_SPECIAL_BASE 0x4760E80ull
+#define DCORE3_RTR4_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR4_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE3_RTR4_H3_BASE 0x4761000ull
+#define DCORE3_RTR4_H3_MAX_OFFSET 0x1000
+#define DCORE3_RTR4_H3_SECTION 0xE800
+#define mmDCORE3_RTR4_H3_SPECIAL_BASE 0x4761E80ull
+#define DCORE3_RTR4_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR4_H3_SPECIAL_SECTION 0x1800
+#define mmDCORE3_RTR4_MSTR_IF_RR_SHRD_HBW_BASE 0x4762000ull
+#define DCORE3_RTR4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_RTR4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE3_RTR4_MSTR_IF_RR_PRVT_HBW_BASE 0x4762200ull
+#define DCORE3_RTR4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_RTR4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE3_RTR4_MSTR_IF_RR_SHRD_LBW_BASE 0x4762400ull
+#define DCORE3_RTR4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_RTR4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE3_RTR4_MSTR_IF_RR_PRVT_LBW_BASE 0x4762600ull
+#define DCORE3_RTR4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_RTR4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE3_RTR4_MSTR_IF_E2E_CRDT_BASE 0x4762800ull
+#define DCORE3_RTR4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_RTR4_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE3_RTR4_MSTR_IF_AXUSER_BASE 0x4762A80ull
+#define DCORE3_RTR4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_RTR4_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE3_RTR4_MSTR_IF_DBG_HBW_BASE 0x4762B00ull
+#define DCORE3_RTR4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_RTR4_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_RTR4_MSTR_IF_DBG_LBW_BASE 0x4762B80ull
+#define DCORE3_RTR4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_RTR4_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE3_RTR4_MSTR_IF_CORE_HBW_BASE 0x4762C00ull
+#define DCORE3_RTR4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_RTR4_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE3_RTR4_MSTR_IF_CORE_LBW_BASE 0x4762D80ull
+#define DCORE3_RTR4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_RTR4_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE3_RTR4_MSTR_IF_SPECIAL_BASE 0x4762E80ull
+#define DCORE3_RTR4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR4_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE3_RTR4_ADD_DEC_HBW_BASE 0x4763000ull
+#define DCORE3_RTR4_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE3_RTR4_ADD_DEC_HBW_SECTION 0x4000
+#define mmDCORE3_RTR4_ADD_DEC_LBW_BASE 0x4763400ull
+#define DCORE3_RTR4_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE3_RTR4_ADD_DEC_LBW_SECTION 0xA800
+#define mmDCORE3_RTR4_ADD_DEC_SPECIAL_BASE 0x4763E80ull
+#define DCORE3_RTR4_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR4_ADD_DEC_SPECIAL_SECTION 0x1800
+#define mmDCORE3_RTR4_BASE 0x4764000ull
+#define DCORE3_RTR4_MAX_OFFSET 0x1000
+#define DCORE3_RTR4_SECTION 0x3000
+#define mmDCORE3_RTR4_HBW_RD_RQ_LL_STAT_BASE 0x4764300ull
+#define DCORE3_RTR4_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR4_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR4_HBW_RD_RS_LL_STAT_BASE 0x4764340ull
+#define DCORE3_RTR4_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR4_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR4_HBW_WR_RQ_LL_STAT_BASE 0x4764380ull
+#define DCORE3_RTR4_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR4_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR4_HBW_WR_RS_LL_STAT_BASE 0x47643C0ull
+#define DCORE3_RTR4_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR4_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR4_LBW_RD_RQ_LL_STAT_BASE 0x4764400ull
+#define DCORE3_RTR4_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR4_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR4_LBW_RD_RS_LL_STAT_BASE 0x4764440ull
+#define DCORE3_RTR4_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR4_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR4_LBW_WR_RQ_LL_STAT_BASE 0x4764480ull
+#define DCORE3_RTR4_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR4_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR4_LBW_WR_RS_LL_STAT_BASE 0x47644C0ull
+#define DCORE3_RTR4_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR4_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR4_HBW_MFIFO_BASE 0x4764500ull
+#define DCORE3_RTR4_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE3_RTR4_HBW_MFIFO_SECTION 0x4000
+#define mmDCORE3_RTR4_E2E_RD_LL_STAT_BASE 0x4764540ull
+#define DCORE3_RTR4_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR4_E2E_RD_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR4_E2E_WR_LL_STAT_BASE 0x4764580ull
+#define DCORE3_RTR4_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR4_E2E_WR_LL_STAT_SECTION 0x8000
+#define mmDCORE3_RTR4_RTR_HBW_XACT_STAT_BASE 0x4764600ull
+#define DCORE3_RTR4_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR4_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE3_RTR4_RTR_LBW_XACT_STAT_BASE 0x4764680ull
+#define DCORE3_RTR4_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR4_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE3_RTR4_RTR_E2E_XACT_STAT_BASE 0x4764700ull
+#define DCORE3_RTR4_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR4_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define mmDCORE3_RTR4_SPECIAL_BASE 0x4764E80ull
+#define DCORE3_RTR4_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR4_SPECIAL_SECTION 0x1800
+#define mmDCORE3_RTR4_DBG_ADDR_BASE 0x4765000ull
+#define DCORE3_RTR4_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE3_RTR4_DBG_ADDR_SECTION 0xE800
+#define mmDCORE3_RTR4_DBG_ADDR_SPECIAL_BASE 0x4765E80ull
+#define DCORE3_RTR4_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR4_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define mmDCORE3_RTR5_CTRL_BASE 0x4768000ull
+#define DCORE3_RTR5_CTRL_MAX_OFFSET 0x1000
+#define DCORE3_RTR5_CTRL_SECTION 0xE800
+#define mmDCORE3_RTR5_CTRL_SPECIAL_BASE 0x4768E80ull
+#define DCORE3_RTR5_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR5_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE3_RTR5_H3_BASE 0x4769000ull
+#define DCORE3_RTR5_H3_MAX_OFFSET 0x1000
+#define DCORE3_RTR5_H3_SECTION 0xE800
+#define mmDCORE3_RTR5_H3_SPECIAL_BASE 0x4769E80ull
+#define DCORE3_RTR5_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR5_H3_SPECIAL_SECTION 0x1800
+#define mmDCORE3_RTR5_MSTR_IF_RR_SHRD_HBW_BASE 0x476A000ull
+#define DCORE3_RTR5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_RTR5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE3_RTR5_MSTR_IF_RR_PRVT_HBW_BASE 0x476A200ull
+#define DCORE3_RTR5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_RTR5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE3_RTR5_MSTR_IF_RR_SHRD_LBW_BASE 0x476A400ull
+#define DCORE3_RTR5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_RTR5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE3_RTR5_MSTR_IF_RR_PRVT_LBW_BASE 0x476A600ull
+#define DCORE3_RTR5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_RTR5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE3_RTR5_MSTR_IF_E2E_CRDT_BASE 0x476A800ull
+#define DCORE3_RTR5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_RTR5_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE3_RTR5_MSTR_IF_AXUSER_BASE 0x476AA80ull
+#define DCORE3_RTR5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_RTR5_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE3_RTR5_MSTR_IF_DBG_HBW_BASE 0x476AB00ull
+#define DCORE3_RTR5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_RTR5_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_RTR5_MSTR_IF_DBG_LBW_BASE 0x476AB80ull
+#define DCORE3_RTR5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_RTR5_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE3_RTR5_MSTR_IF_CORE_HBW_BASE 0x476AC00ull
+#define DCORE3_RTR5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_RTR5_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE3_RTR5_MSTR_IF_CORE_LBW_BASE 0x476AD80ull
+#define DCORE3_RTR5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_RTR5_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE3_RTR5_MSTR_IF_SPECIAL_BASE 0x476AE80ull
+#define DCORE3_RTR5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR5_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE3_RTR5_ADD_DEC_HBW_BASE 0x476B000ull
+#define DCORE3_RTR5_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE3_RTR5_ADD_DEC_HBW_SECTION 0x4000
+#define mmDCORE3_RTR5_ADD_DEC_LBW_BASE 0x476B400ull
+#define DCORE3_RTR5_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE3_RTR5_ADD_DEC_LBW_SECTION 0xA800
+#define mmDCORE3_RTR5_ADD_DEC_SPECIAL_BASE 0x476BE80ull
+#define DCORE3_RTR5_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR5_ADD_DEC_SPECIAL_SECTION 0x1800
+#define mmDCORE3_RTR5_BASE 0x476C000ull
+#define DCORE3_RTR5_MAX_OFFSET 0x1000
+#define DCORE3_RTR5_SECTION 0x3000
+#define mmDCORE3_RTR5_HBW_RD_RQ_LL_STAT_BASE 0x476C300ull
+#define DCORE3_RTR5_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR5_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR5_HBW_RD_RS_LL_STAT_BASE 0x476C340ull
+#define DCORE3_RTR5_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR5_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR5_HBW_WR_RQ_LL_STAT_BASE 0x476C380ull
+#define DCORE3_RTR5_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR5_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR5_HBW_WR_RS_LL_STAT_BASE 0x476C3C0ull
+#define DCORE3_RTR5_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR5_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR5_LBW_RD_RQ_LL_STAT_BASE 0x476C400ull
+#define DCORE3_RTR5_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR5_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR5_LBW_RD_RS_LL_STAT_BASE 0x476C440ull
+#define DCORE3_RTR5_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR5_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR5_LBW_WR_RQ_LL_STAT_BASE 0x476C480ull
+#define DCORE3_RTR5_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR5_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR5_LBW_WR_RS_LL_STAT_BASE 0x476C4C0ull
+#define DCORE3_RTR5_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR5_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR5_HBW_MFIFO_BASE 0x476C500ull
+#define DCORE3_RTR5_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE3_RTR5_HBW_MFIFO_SECTION 0x4000
+#define mmDCORE3_RTR5_E2E_RD_LL_STAT_BASE 0x476C540ull
+#define DCORE3_RTR5_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR5_E2E_RD_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR5_E2E_WR_LL_STAT_BASE 0x476C580ull
+#define DCORE3_RTR5_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR5_E2E_WR_LL_STAT_SECTION 0x8000
+#define mmDCORE3_RTR5_RTR_HBW_XACT_STAT_BASE 0x476C600ull
+#define DCORE3_RTR5_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR5_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE3_RTR5_RTR_LBW_XACT_STAT_BASE 0x476C680ull
+#define DCORE3_RTR5_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR5_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE3_RTR5_RTR_E2E_XACT_STAT_BASE 0x476C700ull
+#define DCORE3_RTR5_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR5_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define mmDCORE3_RTR5_SPECIAL_BASE 0x476CE80ull
+#define DCORE3_RTR5_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR5_SPECIAL_SECTION 0x1800
+#define mmDCORE3_RTR5_DBG_ADDR_BASE 0x476D000ull
+#define DCORE3_RTR5_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE3_RTR5_DBG_ADDR_SECTION 0xE800
+#define mmDCORE3_RTR5_DBG_ADDR_SPECIAL_BASE 0x476DE80ull
+#define DCORE3_RTR5_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR5_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define mmDCORE3_RTR6_CTRL_BASE 0x4770000ull
+#define DCORE3_RTR6_CTRL_MAX_OFFSET 0x1000
+#define DCORE3_RTR6_CTRL_SECTION 0xE800
+#define mmDCORE3_RTR6_CTRL_SPECIAL_BASE 0x4770E80ull
+#define DCORE3_RTR6_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR6_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE3_RTR6_H3_BASE 0x4771000ull
+#define DCORE3_RTR6_H3_MAX_OFFSET 0x1000
+#define DCORE3_RTR6_H3_SECTION 0xE800
+#define mmDCORE3_RTR6_H3_SPECIAL_BASE 0x4771E80ull
+#define DCORE3_RTR6_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR6_H3_SPECIAL_SECTION 0x1800
+#define mmDCORE3_RTR6_MSTR_IF_RR_SHRD_HBW_BASE 0x4772000ull
+#define DCORE3_RTR6_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_RTR6_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE3_RTR6_MSTR_IF_RR_PRVT_HBW_BASE 0x4772200ull
+#define DCORE3_RTR6_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_RTR6_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE3_RTR6_MSTR_IF_RR_SHRD_LBW_BASE 0x4772400ull
+#define DCORE3_RTR6_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_RTR6_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE3_RTR6_MSTR_IF_RR_PRVT_LBW_BASE 0x4772600ull
+#define DCORE3_RTR6_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_RTR6_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE3_RTR6_MSTR_IF_E2E_CRDT_BASE 0x4772800ull
+#define DCORE3_RTR6_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_RTR6_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE3_RTR6_MSTR_IF_AXUSER_BASE 0x4772A80ull
+#define DCORE3_RTR6_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_RTR6_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE3_RTR6_MSTR_IF_DBG_HBW_BASE 0x4772B00ull
+#define DCORE3_RTR6_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_RTR6_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_RTR6_MSTR_IF_DBG_LBW_BASE 0x4772B80ull
+#define DCORE3_RTR6_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_RTR6_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE3_RTR6_MSTR_IF_CORE_HBW_BASE 0x4772C00ull
+#define DCORE3_RTR6_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_RTR6_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE3_RTR6_MSTR_IF_CORE_LBW_BASE 0x4772D80ull
+#define DCORE3_RTR6_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_RTR6_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE3_RTR6_MSTR_IF_SPECIAL_BASE 0x4772E80ull
+#define DCORE3_RTR6_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR6_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE3_RTR6_ADD_DEC_HBW_BASE 0x4773000ull
+#define DCORE3_RTR6_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE3_RTR6_ADD_DEC_HBW_SECTION 0x4000
+#define mmDCORE3_RTR6_ADD_DEC_LBW_BASE 0x4773400ull
+#define DCORE3_RTR6_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE3_RTR6_ADD_DEC_LBW_SECTION 0xA800
+#define mmDCORE3_RTR6_ADD_DEC_SPECIAL_BASE 0x4773E80ull
+#define DCORE3_RTR6_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR6_ADD_DEC_SPECIAL_SECTION 0x1800
+#define mmDCORE3_RTR6_BASE 0x4774000ull
+#define DCORE3_RTR6_MAX_OFFSET 0x1000
+#define DCORE3_RTR6_SECTION 0x3000
+#define mmDCORE3_RTR6_HBW_RD_RQ_LL_STAT_BASE 0x4774300ull
+#define DCORE3_RTR6_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR6_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR6_HBW_RD_RS_LL_STAT_BASE 0x4774340ull
+#define DCORE3_RTR6_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR6_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR6_HBW_WR_RQ_LL_STAT_BASE 0x4774380ull
+#define DCORE3_RTR6_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR6_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR6_HBW_WR_RS_LL_STAT_BASE 0x47743C0ull
+#define DCORE3_RTR6_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR6_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR6_LBW_RD_RQ_LL_STAT_BASE 0x4774400ull
+#define DCORE3_RTR6_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR6_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR6_LBW_RD_RS_LL_STAT_BASE 0x4774440ull
+#define DCORE3_RTR6_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR6_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR6_LBW_WR_RQ_LL_STAT_BASE 0x4774480ull
+#define DCORE3_RTR6_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR6_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR6_LBW_WR_RS_LL_STAT_BASE 0x47744C0ull
+#define DCORE3_RTR6_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR6_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR6_HBW_MFIFO_BASE 0x4774500ull
+#define DCORE3_RTR6_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE3_RTR6_HBW_MFIFO_SECTION 0x4000
+#define mmDCORE3_RTR6_E2E_RD_LL_STAT_BASE 0x4774540ull
+#define DCORE3_RTR6_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR6_E2E_RD_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR6_E2E_WR_LL_STAT_BASE 0x4774580ull
+#define DCORE3_RTR6_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR6_E2E_WR_LL_STAT_SECTION 0x8000
+#define mmDCORE3_RTR6_RTR_HBW_XACT_STAT_BASE 0x4774600ull
+#define DCORE3_RTR6_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR6_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE3_RTR6_RTR_LBW_XACT_STAT_BASE 0x4774680ull
+#define DCORE3_RTR6_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR6_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE3_RTR6_RTR_E2E_XACT_STAT_BASE 0x4774700ull
+#define DCORE3_RTR6_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR6_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define mmDCORE3_RTR6_SPECIAL_BASE 0x4774E80ull
+#define DCORE3_RTR6_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR6_SPECIAL_SECTION 0x1800
+#define mmDCORE3_RTR6_DBG_ADDR_BASE 0x4775000ull
+#define DCORE3_RTR6_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE3_RTR6_DBG_ADDR_SECTION 0xE800
+#define mmDCORE3_RTR6_DBG_ADDR_SPECIAL_BASE 0x4775E80ull
+#define DCORE3_RTR6_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR6_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define mmDCORE3_RTR7_CTRL_BASE 0x4778000ull
+#define DCORE3_RTR7_CTRL_MAX_OFFSET 0x1000
+#define DCORE3_RTR7_CTRL_SECTION 0xE800
+#define mmDCORE3_RTR7_CTRL_SPECIAL_BASE 0x4778E80ull
+#define DCORE3_RTR7_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR7_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE3_RTR7_H3_BASE 0x4779000ull
+#define DCORE3_RTR7_H3_MAX_OFFSET 0x1000
+#define DCORE3_RTR7_H3_SECTION 0xE800
+#define mmDCORE3_RTR7_H3_SPECIAL_BASE 0x4779E80ull
+#define DCORE3_RTR7_H3_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR7_H3_SPECIAL_SECTION 0x1800
+#define mmDCORE3_RTR7_MSTR_IF_RR_SHRD_HBW_BASE 0x477A000ull
+#define DCORE3_RTR7_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_RTR7_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE3_RTR7_MSTR_IF_RR_PRVT_HBW_BASE 0x477A200ull
+#define DCORE3_RTR7_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_RTR7_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE3_RTR7_MSTR_IF_RR_SHRD_LBW_BASE 0x477A400ull
+#define DCORE3_RTR7_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_RTR7_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE3_RTR7_MSTR_IF_RR_PRVT_LBW_BASE 0x477A600ull
+#define DCORE3_RTR7_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_RTR7_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE3_RTR7_MSTR_IF_E2E_CRDT_BASE 0x477A800ull
+#define DCORE3_RTR7_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_RTR7_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE3_RTR7_MSTR_IF_AXUSER_BASE 0x477AA80ull
+#define DCORE3_RTR7_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_RTR7_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE3_RTR7_MSTR_IF_DBG_HBW_BASE 0x477AB00ull
+#define DCORE3_RTR7_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_RTR7_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_RTR7_MSTR_IF_DBG_LBW_BASE 0x477AB80ull
+#define DCORE3_RTR7_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_RTR7_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE3_RTR7_MSTR_IF_CORE_HBW_BASE 0x477AC00ull
+#define DCORE3_RTR7_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_RTR7_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE3_RTR7_MSTR_IF_CORE_LBW_BASE 0x477AD80ull
+#define DCORE3_RTR7_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_RTR7_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE3_RTR7_MSTR_IF_SPECIAL_BASE 0x477AE80ull
+#define DCORE3_RTR7_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR7_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmDCORE3_RTR7_ADD_DEC_HBW_BASE 0x477B000ull
+#define DCORE3_RTR7_ADD_DEC_HBW_MAX_OFFSET 0x4000
+#define DCORE3_RTR7_ADD_DEC_HBW_SECTION 0x4000
+#define mmDCORE3_RTR7_ADD_DEC_LBW_BASE 0x477B400ull
+#define DCORE3_RTR7_ADD_DEC_LBW_MAX_OFFSET 0xA600
+#define DCORE3_RTR7_ADD_DEC_LBW_SECTION 0xA800
+#define mmDCORE3_RTR7_ADD_DEC_SPECIAL_BASE 0x477BE80ull
+#define DCORE3_RTR7_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR7_ADD_DEC_SPECIAL_SECTION 0x1800
+#define mmDCORE3_RTR7_BASE 0x477C000ull
+#define DCORE3_RTR7_MAX_OFFSET 0x1000
+#define DCORE3_RTR7_SECTION 0x3000
+#define mmDCORE3_RTR7_HBW_RD_RQ_LL_STAT_BASE 0x477C300ull
+#define DCORE3_RTR7_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR7_HBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR7_HBW_RD_RS_LL_STAT_BASE 0x477C340ull
+#define DCORE3_RTR7_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR7_HBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR7_HBW_WR_RQ_LL_STAT_BASE 0x477C380ull
+#define DCORE3_RTR7_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR7_HBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR7_HBW_WR_RS_LL_STAT_BASE 0x477C3C0ull
+#define DCORE3_RTR7_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR7_HBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR7_LBW_RD_RQ_LL_STAT_BASE 0x477C400ull
+#define DCORE3_RTR7_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR7_LBW_RD_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR7_LBW_RD_RS_LL_STAT_BASE 0x477C440ull
+#define DCORE3_RTR7_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR7_LBW_RD_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR7_LBW_WR_RQ_LL_STAT_BASE 0x477C480ull
+#define DCORE3_RTR7_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR7_LBW_WR_RQ_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR7_LBW_WR_RS_LL_STAT_BASE 0x477C4C0ull
+#define DCORE3_RTR7_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR7_LBW_WR_RS_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR7_HBW_MFIFO_BASE 0x477C500ull
+#define DCORE3_RTR7_HBW_MFIFO_MAX_OFFSET 0x3000
+#define DCORE3_RTR7_HBW_MFIFO_SECTION 0x4000
+#define mmDCORE3_RTR7_E2E_RD_LL_STAT_BASE 0x477C540ull
+#define DCORE3_RTR7_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR7_E2E_RD_LL_STAT_SECTION 0x4000
+#define mmDCORE3_RTR7_E2E_WR_LL_STAT_BASE 0x477C580ull
+#define DCORE3_RTR7_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
+#define DCORE3_RTR7_E2E_WR_LL_STAT_SECTION 0x8000
+#define mmDCORE3_RTR7_RTR_HBW_XACT_STAT_BASE 0x477C600ull
+#define DCORE3_RTR7_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR7_RTR_HBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE3_RTR7_RTR_LBW_XACT_STAT_BASE 0x477C680ull
+#define DCORE3_RTR7_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR7_RTR_LBW_XACT_STAT_SECTION 0x8000
+#define mmDCORE3_RTR7_RTR_E2E_XACT_STAT_BASE 0x477C700ull
+#define DCORE3_RTR7_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
+#define DCORE3_RTR7_RTR_E2E_XACT_STAT_SECTION 0x7800
+#define mmDCORE3_RTR7_SPECIAL_BASE 0x477CE80ull
+#define DCORE3_RTR7_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR7_SPECIAL_SECTION 0x1800
+#define mmDCORE3_RTR7_DBG_ADDR_BASE 0x477D000ull
+#define DCORE3_RTR7_DBG_ADDR_MAX_OFFSET 0x1000
+#define DCORE3_RTR7_DBG_ADDR_SECTION 0xE800
+#define mmDCORE3_RTR7_DBG_ADDR_SPECIAL_BASE 0x477DE80ull
+#define DCORE3_RTR7_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_RTR7_DBG_ADDR_SPECIAL_SECTION 0x2180
+#define mmDCORE3_SRAM0_BANK_BASE 0x4780000ull
+#define DCORE3_SRAM0_BANK_MAX_OFFSET 0x1000
+#define DCORE3_SRAM0_BANK_SECTION 0xE800
+#define mmDCORE3_SRAM0_BANK_SPECIAL_BASE 0x4780E80ull
+#define DCORE3_SRAM0_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM0_BANK_SPECIAL_SECTION 0x1800
+#define mmDCORE3_SRAM0_RTR_BASE 0x4781000ull
+#define DCORE3_SRAM0_RTR_MAX_OFFSET 0x1000
+#define DCORE3_SRAM0_RTR_SECTION 0xE800
+#define mmDCORE3_SRAM0_RTR_SPECIAL_BASE 0x4781E80ull
+#define DCORE3_SRAM0_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM0_RTR_SPECIAL_SECTION 0x1800
+#define mmDCORE3_SRAM0_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4782000ull
+#define DCORE3_SRAM0_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM0_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM0_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4782100ull
+#define DCORE3_SRAM0_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM0_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4782200ull
+#define DCORE3_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4782300ull
+#define DCORE3_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM0_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4782400ull
+#define DCORE3_SRAM0_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM0_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM0_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4782500ull
+#define DCORE3_SRAM0_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM0_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM0_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4782600ull
+#define DCORE3_SRAM0_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM0_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4782700ull
+#define DCORE3_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4782780ull
+#define DCORE3_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4782800ull
+#define DCORE3_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4782880ull
+#define DCORE3_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4782900ull
+#define DCORE3_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4782980ull
+#define DCORE3_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4782A00ull
+#define DCORE3_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4782A80ull
+#define DCORE3_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define mmDCORE3_SRAM0_DBG_CNT_SPECIAL_BASE 0x4782E80ull
+#define DCORE3_SRAM0_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM0_DBG_CNT_SPECIAL_SECTION 0x5180
+#define mmDCORE3_SRAM1_BANK_BASE 0x4788000ull
+#define DCORE3_SRAM1_BANK_MAX_OFFSET 0x1000
+#define DCORE3_SRAM1_BANK_SECTION 0xE800
+#define mmDCORE3_SRAM1_BANK_SPECIAL_BASE 0x4788E80ull
+#define DCORE3_SRAM1_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM1_BANK_SPECIAL_SECTION 0x1800
+#define mmDCORE3_SRAM1_RTR_BASE 0x4789000ull
+#define DCORE3_SRAM1_RTR_MAX_OFFSET 0x1000
+#define DCORE3_SRAM1_RTR_SECTION 0xE800
+#define mmDCORE3_SRAM1_RTR_SPECIAL_BASE 0x4789E80ull
+#define DCORE3_SRAM1_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM1_RTR_SPECIAL_SECTION 0x1800
+#define mmDCORE3_SRAM1_DBG_CNT_N_HBW_DBG_CNT_BASE 0x478A000ull
+#define DCORE3_SRAM1_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM1_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM1_DBG_CNT_S_HBW_DBG_CNT_BASE 0x478A100ull
+#define DCORE3_SRAM1_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM1_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x478A200ull
+#define DCORE3_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x478A300ull
+#define DCORE3_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM1_DBG_CNT_N_LBW_DBG_CNT_BASE 0x478A400ull
+#define DCORE3_SRAM1_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM1_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM1_DBG_CNT_S_LBW_DBG_CNT_BASE 0x478A500ull
+#define DCORE3_SRAM1_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM1_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM1_DBG_CNT_L_LBW_DBG_CNT_BASE 0x478A600ull
+#define DCORE3_SRAM1_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM1_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x478A700ull
+#define DCORE3_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x478A780ull
+#define DCORE3_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x478A800ull
+#define DCORE3_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x478A880ull
+#define DCORE3_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x478A900ull
+#define DCORE3_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x478A980ull
+#define DCORE3_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x478AA00ull
+#define DCORE3_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x478AA80ull
+#define DCORE3_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define mmDCORE3_SRAM1_DBG_CNT_SPECIAL_BASE 0x478AE80ull
+#define DCORE3_SRAM1_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM1_DBG_CNT_SPECIAL_SECTION 0x5180
+#define mmDCORE3_SRAM2_BANK_BASE 0x4790000ull
+#define DCORE3_SRAM2_BANK_MAX_OFFSET 0x1000
+#define DCORE3_SRAM2_BANK_SECTION 0xE800
+#define mmDCORE3_SRAM2_BANK_SPECIAL_BASE 0x4790E80ull
+#define DCORE3_SRAM2_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM2_BANK_SPECIAL_SECTION 0x1800
+#define mmDCORE3_SRAM2_RTR_BASE 0x4791000ull
+#define DCORE3_SRAM2_RTR_MAX_OFFSET 0x1000
+#define DCORE3_SRAM2_RTR_SECTION 0xE800
+#define mmDCORE3_SRAM2_RTR_SPECIAL_BASE 0x4791E80ull
+#define DCORE3_SRAM2_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM2_RTR_SPECIAL_SECTION 0x1800
+#define mmDCORE3_SRAM2_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4792000ull
+#define DCORE3_SRAM2_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM2_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM2_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4792100ull
+#define DCORE3_SRAM2_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM2_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4792200ull
+#define DCORE3_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4792300ull
+#define DCORE3_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM2_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4792400ull
+#define DCORE3_SRAM2_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM2_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM2_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4792500ull
+#define DCORE3_SRAM2_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM2_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM2_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4792600ull
+#define DCORE3_SRAM2_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM2_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4792700ull
+#define DCORE3_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4792780ull
+#define DCORE3_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4792800ull
+#define DCORE3_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4792880ull
+#define DCORE3_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4792900ull
+#define DCORE3_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4792980ull
+#define DCORE3_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4792A00ull
+#define DCORE3_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4792A80ull
+#define DCORE3_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define mmDCORE3_SRAM2_DBG_CNT_SPECIAL_BASE 0x4792E80ull
+#define DCORE3_SRAM2_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM2_DBG_CNT_SPECIAL_SECTION 0x5180
+#define mmDCORE3_SRAM3_BANK_BASE 0x4798000ull
+#define DCORE3_SRAM3_BANK_MAX_OFFSET 0x1000
+#define DCORE3_SRAM3_BANK_SECTION 0xE800
+#define mmDCORE3_SRAM3_BANK_SPECIAL_BASE 0x4798E80ull
+#define DCORE3_SRAM3_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM3_BANK_SPECIAL_SECTION 0x1800
+#define mmDCORE3_SRAM3_RTR_BASE 0x4799000ull
+#define DCORE3_SRAM3_RTR_MAX_OFFSET 0x1000
+#define DCORE3_SRAM3_RTR_SECTION 0xE800
+#define mmDCORE3_SRAM3_RTR_SPECIAL_BASE 0x4799E80ull
+#define DCORE3_SRAM3_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM3_RTR_SPECIAL_SECTION 0x1800
+#define mmDCORE3_SRAM3_DBG_CNT_N_HBW_DBG_CNT_BASE 0x479A000ull
+#define DCORE3_SRAM3_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM3_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM3_DBG_CNT_S_HBW_DBG_CNT_BASE 0x479A100ull
+#define DCORE3_SRAM3_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM3_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x479A200ull
+#define DCORE3_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x479A300ull
+#define DCORE3_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM3_DBG_CNT_N_LBW_DBG_CNT_BASE 0x479A400ull
+#define DCORE3_SRAM3_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM3_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM3_DBG_CNT_S_LBW_DBG_CNT_BASE 0x479A500ull
+#define DCORE3_SRAM3_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM3_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM3_DBG_CNT_L_LBW_DBG_CNT_BASE 0x479A600ull
+#define DCORE3_SRAM3_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM3_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x479A700ull
+#define DCORE3_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x479A780ull
+#define DCORE3_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x479A800ull
+#define DCORE3_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x479A880ull
+#define DCORE3_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x479A900ull
+#define DCORE3_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x479A980ull
+#define DCORE3_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x479AA00ull
+#define DCORE3_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x479AA80ull
+#define DCORE3_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define mmDCORE3_SRAM3_DBG_CNT_SPECIAL_BASE 0x479AE80ull
+#define DCORE3_SRAM3_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM3_DBG_CNT_SPECIAL_SECTION 0x5180
+#define mmDCORE3_SRAM4_BANK_BASE 0x47A0000ull
+#define DCORE3_SRAM4_BANK_MAX_OFFSET 0x1000
+#define DCORE3_SRAM4_BANK_SECTION 0xE800
+#define mmDCORE3_SRAM4_BANK_SPECIAL_BASE 0x47A0E80ull
+#define DCORE3_SRAM4_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM4_BANK_SPECIAL_SECTION 0x1800
+#define mmDCORE3_SRAM4_RTR_BASE 0x47A1000ull
+#define DCORE3_SRAM4_RTR_MAX_OFFSET 0x1000
+#define DCORE3_SRAM4_RTR_SECTION 0xE800
+#define mmDCORE3_SRAM4_RTR_SPECIAL_BASE 0x47A1E80ull
+#define DCORE3_SRAM4_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM4_RTR_SPECIAL_SECTION 0x1800
+#define mmDCORE3_SRAM4_DBG_CNT_N_HBW_DBG_CNT_BASE 0x47A2000ull
+#define DCORE3_SRAM4_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM4_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM4_DBG_CNT_S_HBW_DBG_CNT_BASE 0x47A2100ull
+#define DCORE3_SRAM4_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM4_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x47A2200ull
+#define DCORE3_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x47A2300ull
+#define DCORE3_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM4_DBG_CNT_N_LBW_DBG_CNT_BASE 0x47A2400ull
+#define DCORE3_SRAM4_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM4_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM4_DBG_CNT_S_LBW_DBG_CNT_BASE 0x47A2500ull
+#define DCORE3_SRAM4_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM4_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM4_DBG_CNT_L_LBW_DBG_CNT_BASE 0x47A2600ull
+#define DCORE3_SRAM4_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM4_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x47A2700ull
+#define DCORE3_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x47A2780ull
+#define DCORE3_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x47A2800ull
+#define DCORE3_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x47A2880ull
+#define DCORE3_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x47A2900ull
+#define DCORE3_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x47A2980ull
+#define DCORE3_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x47A2A00ull
+#define DCORE3_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x47A2A80ull
+#define DCORE3_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define mmDCORE3_SRAM4_DBG_CNT_SPECIAL_BASE 0x47A2E80ull
+#define DCORE3_SRAM4_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM4_DBG_CNT_SPECIAL_SECTION 0x5180
+#define mmDCORE3_SRAM5_BANK_BASE 0x47A8000ull
+#define DCORE3_SRAM5_BANK_MAX_OFFSET 0x1000
+#define DCORE3_SRAM5_BANK_SECTION 0xE800
+#define mmDCORE3_SRAM5_BANK_SPECIAL_BASE 0x47A8E80ull
+#define DCORE3_SRAM5_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM5_BANK_SPECIAL_SECTION 0x1800
+#define mmDCORE3_SRAM5_RTR_BASE 0x47A9000ull
+#define DCORE3_SRAM5_RTR_MAX_OFFSET 0x1000
+#define DCORE3_SRAM5_RTR_SECTION 0xE800
+#define mmDCORE3_SRAM5_RTR_SPECIAL_BASE 0x47A9E80ull
+#define DCORE3_SRAM5_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM5_RTR_SPECIAL_SECTION 0x1800
+#define mmDCORE3_SRAM5_DBG_CNT_N_HBW_DBG_CNT_BASE 0x47AA000ull
+#define DCORE3_SRAM5_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM5_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM5_DBG_CNT_S_HBW_DBG_CNT_BASE 0x47AA100ull
+#define DCORE3_SRAM5_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM5_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x47AA200ull
+#define DCORE3_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x47AA300ull
+#define DCORE3_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM5_DBG_CNT_N_LBW_DBG_CNT_BASE 0x47AA400ull
+#define DCORE3_SRAM5_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM5_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM5_DBG_CNT_S_LBW_DBG_CNT_BASE 0x47AA500ull
+#define DCORE3_SRAM5_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM5_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM5_DBG_CNT_L_LBW_DBG_CNT_BASE 0x47AA600ull
+#define DCORE3_SRAM5_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM5_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x47AA700ull
+#define DCORE3_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x47AA780ull
+#define DCORE3_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x47AA800ull
+#define DCORE3_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x47AA880ull
+#define DCORE3_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x47AA900ull
+#define DCORE3_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x47AA980ull
+#define DCORE3_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x47AAA00ull
+#define DCORE3_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x47AAA80ull
+#define DCORE3_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define mmDCORE3_SRAM5_DBG_CNT_SPECIAL_BASE 0x47AAE80ull
+#define DCORE3_SRAM5_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM5_DBG_CNT_SPECIAL_SECTION 0x5180
+#define mmDCORE3_SRAM6_BANK_BASE 0x47B0000ull
+#define DCORE3_SRAM6_BANK_MAX_OFFSET 0x1000
+#define DCORE3_SRAM6_BANK_SECTION 0xE800
+#define mmDCORE3_SRAM6_BANK_SPECIAL_BASE 0x47B0E80ull
+#define DCORE3_SRAM6_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM6_BANK_SPECIAL_SECTION 0x1800
+#define mmDCORE3_SRAM6_RTR_BASE 0x47B1000ull
+#define DCORE3_SRAM6_RTR_MAX_OFFSET 0x1000
+#define DCORE3_SRAM6_RTR_SECTION 0xE800
+#define mmDCORE3_SRAM6_RTR_SPECIAL_BASE 0x47B1E80ull
+#define DCORE3_SRAM6_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM6_RTR_SPECIAL_SECTION 0x1800
+#define mmDCORE3_SRAM6_DBG_CNT_N_HBW_DBG_CNT_BASE 0x47B2000ull
+#define DCORE3_SRAM6_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM6_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM6_DBG_CNT_S_HBW_DBG_CNT_BASE 0x47B2100ull
+#define DCORE3_SRAM6_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM6_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x47B2200ull
+#define DCORE3_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x47B2300ull
+#define DCORE3_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM6_DBG_CNT_N_LBW_DBG_CNT_BASE 0x47B2400ull
+#define DCORE3_SRAM6_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM6_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM6_DBG_CNT_S_LBW_DBG_CNT_BASE 0x47B2500ull
+#define DCORE3_SRAM6_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM6_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM6_DBG_CNT_L_LBW_DBG_CNT_BASE 0x47B2600ull
+#define DCORE3_SRAM6_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM6_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x47B2700ull
+#define DCORE3_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x47B2780ull
+#define DCORE3_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x47B2800ull
+#define DCORE3_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x47B2880ull
+#define DCORE3_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x47B2900ull
+#define DCORE3_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x47B2980ull
+#define DCORE3_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x47B2A00ull
+#define DCORE3_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x47B2A80ull
+#define DCORE3_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define mmDCORE3_SRAM6_DBG_CNT_SPECIAL_BASE 0x47B2E80ull
+#define DCORE3_SRAM6_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM6_DBG_CNT_SPECIAL_SECTION 0x5180
+#define mmDCORE3_SRAM7_BANK_BASE 0x47B8000ull
+#define DCORE3_SRAM7_BANK_MAX_OFFSET 0x1000
+#define DCORE3_SRAM7_BANK_SECTION 0xE800
+#define mmDCORE3_SRAM7_BANK_SPECIAL_BASE 0x47B8E80ull
+#define DCORE3_SRAM7_BANK_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM7_BANK_SPECIAL_SECTION 0x1800
+#define mmDCORE3_SRAM7_RTR_BASE 0x47B9000ull
+#define DCORE3_SRAM7_RTR_MAX_OFFSET 0x1000
+#define DCORE3_SRAM7_RTR_SECTION 0xE800
+#define mmDCORE3_SRAM7_RTR_SPECIAL_BASE 0x47B9E80ull
+#define DCORE3_SRAM7_RTR_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM7_RTR_SPECIAL_SECTION 0x1800
+#define mmDCORE3_SRAM7_DBG_CNT_N_HBW_DBG_CNT_BASE 0x47BA000ull
+#define DCORE3_SRAM7_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM7_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM7_DBG_CNT_S_HBW_DBG_CNT_BASE 0x47BA100ull
+#define DCORE3_SRAM7_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM7_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x47BA200ull
+#define DCORE3_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x47BA300ull
+#define DCORE3_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM7_DBG_CNT_N_LBW_DBG_CNT_BASE 0x47BA400ull
+#define DCORE3_SRAM7_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM7_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM7_DBG_CNT_S_LBW_DBG_CNT_BASE 0x47BA500ull
+#define DCORE3_SRAM7_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM7_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM7_DBG_CNT_L_LBW_DBG_CNT_BASE 0x47BA600ull
+#define DCORE3_SRAM7_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
+#define DCORE3_SRAM7_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
+#define mmDCORE3_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x47BA700ull
+#define DCORE3_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x47BA780ull
+#define DCORE3_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x47BA800ull
+#define DCORE3_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x47BA880ull
+#define DCORE3_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x47BA900ull
+#define DCORE3_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x47BA980ull
+#define DCORE3_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x47BAA00ull
+#define DCORE3_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
+#define mmDCORE3_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x47BAA80ull
+#define DCORE3_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
+#define DCORE3_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
+#define mmDCORE3_SRAM7_DBG_CNT_SPECIAL_BASE 0x47BAE80ull
+#define DCORE3_SRAM7_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_SRAM7_DBG_CNT_SPECIAL_SECTION 0x5180
+#define mmDCORE3_EDMA0_QM_DCCM_BASE 0x47C0000ull
+#define DCORE3_EDMA0_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE3_EDMA0_QM_DCCM_SECTION 0x8000
+#define mmDCORE3_EDMA0_QM_ARC_AUX_BASE 0x47C8000ull
+#define DCORE3_EDMA0_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE3_EDMA0_QM_ARC_AUX_SECTION 0xE800
+#define mmDCORE3_EDMA0_QM_ARC_AUX_SPECIAL_BASE 0x47C8E80ull
+#define DCORE3_EDMA0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_EDMA0_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define mmDCORE3_EDMA0_QM_BASE 0x47CA000ull
+#define DCORE3_EDMA0_QM_MAX_OFFSET 0x1000
+#define DCORE3_EDMA0_QM_SECTION 0x9000
+#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x47CA900ull
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x47CA908ull
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x47CA910ull
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x47CA918ull
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x47CA920ull
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x47CA928ull
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x47CA930ull
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x47CA938ull
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x47CA940ull
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x47CA948ull
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x47CA950ull
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x47CA958ull
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x47CA960ull
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x47CA968ull
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x47CA970ull
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x47CA978ull
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE3_EDMA0_QM_AXUSER_SECURED_BASE 0x47CAB00ull
+#define DCORE3_EDMA0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE3_EDMA0_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE3_EDMA0_QM_AXUSER_NONSECURED_BASE 0x47CAB80ull
+#define DCORE3_EDMA0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE3_EDMA0_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE3_EDMA0_QM_DBG_HBW_BASE 0x47CAC00ull
+#define DCORE3_EDMA0_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_EDMA0_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_EDMA0_QM_DBG_LBW_BASE 0x47CAC80ull
+#define DCORE3_EDMA0_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_EDMA0_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE3_EDMA0_QM_CGM_BASE 0x47CAD80ull
+#define DCORE3_EDMA0_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE3_EDMA0_QM_CGM_SECTION 0x1000
+#define mmDCORE3_EDMA0_QM_SPECIAL_BASE 0x47CAE80ull
+#define DCORE3_EDMA0_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_EDMA0_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE3_EDMA0_CORE_BASE 0x47CB000ull
+#define DCORE3_EDMA0_CORE_MAX_OFFSET 0x1000
+#define DCORE3_EDMA0_CORE_SECTION 0x8000
+#define mmDCORE3_EDMA0_CORE_CTX_AXUSER_BASE 0x47CB800ull
+#define DCORE3_EDMA0_CORE_CTX_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_EDMA0_CORE_CTX_AXUSER_SECTION 0x6000
+#define mmDCORE3_EDMA0_CORE_CTX_BASE 0x47CB860ull
+#define DCORE3_EDMA0_CORE_CTX_MAX_OFFSET 0x9000
+#define DCORE3_EDMA0_CORE_CTX_SECTION 0x5A00
+#define mmDCORE3_EDMA0_CORE_KDMA_CGM_BASE 0x47CBE00ull
+#define DCORE3_EDMA0_CORE_KDMA_CGM_MAX_OFFSET 0xC000
+#define DCORE3_EDMA0_CORE_KDMA_CGM_SECTION 0x8000
+#define mmDCORE3_EDMA0_CORE_SPECIAL_BASE 0x47CBE80ull
+#define DCORE3_EDMA0_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_EDMA0_CORE_SPECIAL_SECTION 0x1800
+#define mmDCORE3_EDMA0_MSTR_IF_RR_SHRD_HBW_BASE 0x47CC000ull
+#define DCORE3_EDMA0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_EDMA0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE3_EDMA0_MSTR_IF_RR_PRVT_HBW_BASE 0x47CC200ull
+#define DCORE3_EDMA0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_EDMA0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE3_EDMA0_MSTR_IF_RR_SHRD_LBW_BASE 0x47CC400ull
+#define DCORE3_EDMA0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_EDMA0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE3_EDMA0_MSTR_IF_RR_PRVT_LBW_BASE 0x47CC600ull
+#define DCORE3_EDMA0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_EDMA0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE3_EDMA0_MSTR_IF_E2E_CRDT_BASE 0x47CC800ull
+#define DCORE3_EDMA0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_EDMA0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE3_EDMA0_MSTR_IF_AXUSER_BASE 0x47CCA80ull
+#define DCORE3_EDMA0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_EDMA0_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE3_EDMA0_MSTR_IF_DBG_HBW_BASE 0x47CCB00ull
+#define DCORE3_EDMA0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_EDMA0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_EDMA0_MSTR_IF_DBG_LBW_BASE 0x47CCB80ull
+#define DCORE3_EDMA0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_EDMA0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE3_EDMA0_MSTR_IF_CORE_HBW_BASE 0x47CCC00ull
+#define DCORE3_EDMA0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_EDMA0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE3_EDMA0_MSTR_IF_CORE_LBW_BASE 0x47CCD80ull
+#define DCORE3_EDMA0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_EDMA0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE3_EDMA0_MSTR_IF_SPECIAL_BASE 0x47CCE80ull
+#define DCORE3_EDMA0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_EDMA0_MSTR_IF_SPECIAL_SECTION 0x3180
+#define mmDCORE3_EDMA1_QM_DCCM_BASE 0x47D0000ull
+#define DCORE3_EDMA1_QM_DCCM_MAX_OFFSET 0x4000
+#define DCORE3_EDMA1_QM_DCCM_SECTION 0x8000
+#define mmDCORE3_EDMA1_QM_ARC_AUX_BASE 0x47D8000ull
+#define DCORE3_EDMA1_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define DCORE3_EDMA1_QM_ARC_AUX_SECTION 0xE800
+#define mmDCORE3_EDMA1_QM_ARC_AUX_SPECIAL_BASE 0x47D8E80ull
+#define DCORE3_EDMA1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_EDMA1_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define mmDCORE3_EDMA1_QM_BASE 0x47DA000ull
+#define DCORE3_EDMA1_QM_MAX_OFFSET 0x1000
+#define DCORE3_EDMA1_QM_SECTION 0x9000
+#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x47DA900ull
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x47DA908ull
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x47DA910ull
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x47DA918ull
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x47DA920ull
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x47DA928ull
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x47DA930ull
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x47DA938ull
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x47DA940ull
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x47DA948ull
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x47DA950ull
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x47DA958ull
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x47DA960ull
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x47DA968ull
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x47DA970ull
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x47DA978ull
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmDCORE3_EDMA1_QM_AXUSER_SECURED_BASE 0x47DAB00ull
+#define DCORE3_EDMA1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define DCORE3_EDMA1_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmDCORE3_EDMA1_QM_AXUSER_NONSECURED_BASE 0x47DAB80ull
+#define DCORE3_EDMA1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define DCORE3_EDMA1_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmDCORE3_EDMA1_QM_DBG_HBW_BASE 0x47DAC00ull
+#define DCORE3_EDMA1_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_EDMA1_QM_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_EDMA1_QM_DBG_LBW_BASE 0x47DAC80ull
+#define DCORE3_EDMA1_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_EDMA1_QM_DBG_LBW_SECTION 0x1000
+#define mmDCORE3_EDMA1_QM_CGM_BASE 0x47DAD80ull
+#define DCORE3_EDMA1_QM_CGM_MAX_OFFSET 0xC000
+#define DCORE3_EDMA1_QM_CGM_SECTION 0x1000
+#define mmDCORE3_EDMA1_QM_SPECIAL_BASE 0x47DAE80ull
+#define DCORE3_EDMA1_QM_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_EDMA1_QM_SPECIAL_SECTION 0x1800
+#define mmDCORE3_EDMA1_CORE_BASE 0x47DB000ull
+#define DCORE3_EDMA1_CORE_MAX_OFFSET 0x1000
+#define DCORE3_EDMA1_CORE_SECTION 0x8000
+#define mmDCORE3_EDMA1_CORE_CTX_AXUSER_BASE 0x47DB800ull
+#define DCORE3_EDMA1_CORE_CTX_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_EDMA1_CORE_CTX_AXUSER_SECTION 0x6000
+#define mmDCORE3_EDMA1_CORE_CTX_BASE 0x47DB860ull
+#define DCORE3_EDMA1_CORE_CTX_MAX_OFFSET 0x9000
+#define DCORE3_EDMA1_CORE_CTX_SECTION 0x5A00
+#define mmDCORE3_EDMA1_CORE_KDMA_CGM_BASE 0x47DBE00ull
+#define DCORE3_EDMA1_CORE_KDMA_CGM_MAX_OFFSET 0xC000
+#define DCORE3_EDMA1_CORE_KDMA_CGM_SECTION 0x8000
+#define mmDCORE3_EDMA1_CORE_SPECIAL_BASE 0x47DBE80ull
+#define DCORE3_EDMA1_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_EDMA1_CORE_SPECIAL_SECTION 0x1800
+#define mmDCORE3_EDMA1_MSTR_IF_RR_SHRD_HBW_BASE 0x47DC000ull
+#define DCORE3_EDMA1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_EDMA1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE3_EDMA1_MSTR_IF_RR_PRVT_HBW_BASE 0x47DC200ull
+#define DCORE3_EDMA1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_EDMA1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE3_EDMA1_MSTR_IF_RR_SHRD_LBW_BASE 0x47DC400ull
+#define DCORE3_EDMA1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_EDMA1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE3_EDMA1_MSTR_IF_RR_PRVT_LBW_BASE 0x47DC600ull
+#define DCORE3_EDMA1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_EDMA1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE3_EDMA1_MSTR_IF_E2E_CRDT_BASE 0x47DC800ull
+#define DCORE3_EDMA1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_EDMA1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE3_EDMA1_MSTR_IF_AXUSER_BASE 0x47DCA80ull
+#define DCORE3_EDMA1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_EDMA1_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE3_EDMA1_MSTR_IF_DBG_HBW_BASE 0x47DCB00ull
+#define DCORE3_EDMA1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_EDMA1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_EDMA1_MSTR_IF_DBG_LBW_BASE 0x47DCB80ull
+#define DCORE3_EDMA1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_EDMA1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE3_EDMA1_MSTR_IF_CORE_HBW_BASE 0x47DCC00ull
+#define DCORE3_EDMA1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_EDMA1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE3_EDMA1_MSTR_IF_CORE_LBW_BASE 0x47DCD80ull
+#define DCORE3_EDMA1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_EDMA1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE3_EDMA1_MSTR_IF_SPECIAL_BASE 0x47DCE80ull
+#define DCORE3_EDMA1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_EDMA1_MSTR_IF_SPECIAL_SECTION 0x3180
+#define mmDCORE3_DEC0_CMD_BASE 0x47E0000ull
+#define DCORE3_DEC0_CMD_MAX_OFFSET 0x1100
+#define DCORE3_DEC0_CMD_SECTION 0x1000
+#define mmDCORE3_DEC0_VSI_BASE 0x47E1000ull
+#define DCORE3_DEC0_VSI_MAX_OFFSET 0x6FC0
+#define DCORE3_DEC0_VSI_SECTION 0x1000
+#define mmDCORE3_DEC0_L2C_BASE 0x47E2000ull
+#define DCORE3_DEC0_L2C_MAX_OFFSET 0x39C0
+#define DCORE3_DEC0_L2C_SECTION 0x1000
+#define mmDCORE3_VDEC0_BRDG_CTRL_BASE 0x47E3000ull
+#define DCORE3_VDEC0_BRDG_CTRL_MAX_OFFSET 0x1000
+#define DCORE3_VDEC0_BRDG_CTRL_SECTION 0x8000
+#define mmDCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x47E3800ull
+#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000
+#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000
+#define mmDCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x47E3900ull
+#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000
+#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000
+#define mmDCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x47E3A00ull
+#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000
+#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000
+#define mmDCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x47E3B00ull
+#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000
+#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000
+#define mmDCORE3_VDEC0_BRDG_CTRL_AXUSER_DEC_BASE 0x47E3C00ull
+#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000
+#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800
+#define mmDCORE3_VDEC0_BRDG_CTRL_SPECIAL_BASE 0x47E3E80ull
+#define DCORE3_VDEC0_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_VDEC0_BRDG_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE3_VDEC0_CTRL_BASE 0x47E4000ull
+#define DCORE3_VDEC0_CTRL_MAX_OFFSET 0x1000
+#define DCORE3_VDEC0_CTRL_SECTION 0xE800
+#define mmDCORE3_VDEC0_CTRL_SPECIAL_BASE 0x47E4E80ull
+#define DCORE3_VDEC0_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_VDEC0_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE3_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE 0x47E5000ull
+#define DCORE3_VDEC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_VDEC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE3_VDEC0_MSTR_IF_RR_PRVT_HBW_BASE 0x47E5200ull
+#define DCORE3_VDEC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_VDEC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE3_VDEC0_MSTR_IF_RR_SHRD_LBW_BASE 0x47E5400ull
+#define DCORE3_VDEC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_VDEC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE3_VDEC0_MSTR_IF_RR_PRVT_LBW_BASE 0x47E5600ull
+#define DCORE3_VDEC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_VDEC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE3_VDEC0_MSTR_IF_E2E_CRDT_BASE 0x47E5800ull
+#define DCORE3_VDEC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_VDEC0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE3_VDEC0_MSTR_IF_AXUSER_BASE 0x47E5A80ull
+#define DCORE3_VDEC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_VDEC0_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE3_VDEC0_MSTR_IF_DBG_HBW_BASE 0x47E5B00ull
+#define DCORE3_VDEC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_VDEC0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_VDEC0_MSTR_IF_DBG_LBW_BASE 0x47E5B80ull
+#define DCORE3_VDEC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_VDEC0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE3_VDEC0_MSTR_IF_CORE_HBW_BASE 0x47E5C00ull
+#define DCORE3_VDEC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_VDEC0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE3_VDEC0_MSTR_IF_CORE_LBW_BASE 0x47E5D80ull
+#define DCORE3_VDEC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_VDEC0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE3_VDEC0_MSTR_IF_SPECIAL_BASE 0x47E5E80ull
+#define DCORE3_VDEC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_VDEC0_MSTR_IF_SPECIAL_SECTION 0xA180
+#define mmDCORE3_DEC1_CMD_BASE 0x47F0000ull
+#define DCORE3_DEC1_CMD_MAX_OFFSET 0x1100
+#define DCORE3_DEC1_CMD_SECTION 0x1000
+#define mmDCORE3_DEC1_VSI_BASE 0x47F1000ull
+#define DCORE3_DEC1_VSI_MAX_OFFSET 0x6FC0
+#define DCORE3_DEC1_VSI_SECTION 0x1000
+#define mmDCORE3_DEC1_L2C_BASE 0x47F2000ull
+#define DCORE3_DEC1_L2C_MAX_OFFSET 0x39C0
+#define DCORE3_DEC1_L2C_SECTION 0x1000
+#define mmDCORE3_VDEC1_BRDG_CTRL_BASE 0x47F3000ull
+#define DCORE3_VDEC1_BRDG_CTRL_MAX_OFFSET 0x1000
+#define DCORE3_VDEC1_BRDG_CTRL_SECTION 0x8000
+#define mmDCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x47F3800ull
+#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000
+#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000
+#define mmDCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x47F3900ull
+#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000
+#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000
+#define mmDCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x47F3A00ull
+#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000
+#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000
+#define mmDCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x47F3B00ull
+#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000
+#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000
+#define mmDCORE3_VDEC1_BRDG_CTRL_AXUSER_DEC_BASE 0x47F3C00ull
+#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000
+#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800
+#define mmDCORE3_VDEC1_BRDG_CTRL_SPECIAL_BASE 0x47F3E80ull
+#define DCORE3_VDEC1_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_VDEC1_BRDG_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE3_VDEC1_CTRL_BASE 0x47F4000ull
+#define DCORE3_VDEC1_CTRL_MAX_OFFSET 0x1000
+#define DCORE3_VDEC1_CTRL_SECTION 0xE800
+#define mmDCORE3_VDEC1_CTRL_SPECIAL_BASE 0x47F4E80ull
+#define DCORE3_VDEC1_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_VDEC1_CTRL_SPECIAL_SECTION 0x1800
+#define mmDCORE3_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE 0x47F5000ull
+#define DCORE3_VDEC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_VDEC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmDCORE3_VDEC1_MSTR_IF_RR_PRVT_HBW_BASE 0x47F5200ull
+#define DCORE3_VDEC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define DCORE3_VDEC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmDCORE3_VDEC1_MSTR_IF_RR_SHRD_LBW_BASE 0x47F5400ull
+#define DCORE3_VDEC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_VDEC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmDCORE3_VDEC1_MSTR_IF_RR_PRVT_LBW_BASE 0x47F5600ull
+#define DCORE3_VDEC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define DCORE3_VDEC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmDCORE3_VDEC1_MSTR_IF_E2E_CRDT_BASE 0x47F5800ull
+#define DCORE3_VDEC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define DCORE3_VDEC1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmDCORE3_VDEC1_MSTR_IF_AXUSER_BASE 0x47F5A80ull
+#define DCORE3_VDEC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define DCORE3_VDEC1_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmDCORE3_VDEC1_MSTR_IF_DBG_HBW_BASE 0x47F5B00ull
+#define DCORE3_VDEC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define DCORE3_VDEC1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmDCORE3_VDEC1_MSTR_IF_DBG_LBW_BASE 0x47F5B80ull
+#define DCORE3_VDEC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define DCORE3_VDEC1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmDCORE3_VDEC1_MSTR_IF_CORE_HBW_BASE 0x47F5C00ull
+#define DCORE3_VDEC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define DCORE3_VDEC1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmDCORE3_VDEC1_MSTR_IF_CORE_LBW_BASE 0x47F5D80ull
+#define DCORE3_VDEC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define DCORE3_VDEC1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmDCORE3_VDEC1_MSTR_IF_SPECIAL_BASE 0x47F5E80ull
+#define DCORE3_VDEC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_VDEC1_MSTR_IF_SPECIAL_SECTION 0xA180
+#define mmGIC_BASE 0x4800000ull
+#define GIC_MAX_OFFSET 0x10000
+#define GIC_SECTION 0x401000
+#define mmPCIE_WRAP_BASE 0x4C01000ull
+#define PCIE_WRAP_MAX_OFFSET 0x1000
+#define PCIE_WRAP_SECTION 0xE800
+#define mmPCIE_WRAP_SPECIAL_BASE 0x4C01E80ull
+#define PCIE_WRAP_SPECIAL_MAX_OFFSET 0x1800
+#define PCIE_WRAP_SPECIAL_SECTION 0x1800
+#define mmPCIE_DBI_BASE 0x4C02000ull
+#define PCIE_DBI_MAX_OFFSET 0xC040
+#define PCIE_DBI_SECTION 0x2000
+#define mmPCIE_CORE_BASE 0x4C04000ull
+#define PCIE_CORE_MAX_OFFSET 0x1000
+#define PCIE_CORE_SECTION 0xE800
+#define mmPCIE_CORE_SPECIAL_BASE 0x4C04E80ull
+#define PCIE_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define PCIE_CORE_SPECIAL_SECTION 0x2180
+#define mmPCIE_AUX_BASE 0x4C07000ull
+#define PCIE_AUX_MAX_OFFSET 0x1000
+#define PCIE_AUX_SECTION 0xE800
+#define mmPCIE_AUX_SPECIAL_BASE 0x4C07E80ull
+#define PCIE_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define PCIE_AUX_SPECIAL_SECTION 0x8180
+#define mmPCIE_PHY_BASE 0x4C10000ull
+#define PCIE_PHY_MAX_OFFSET 0x1000
+#define PCIE_PHY_SECTION 0xE800
+#define mmPCIE_PHY_SPECIAL_BASE 0x4C10E80ull
+#define PCIE_PHY_SPECIAL_MAX_OFFSET 0x1800
+#define PCIE_PHY_SPECIAL_SECTION 0x2180
+#define mmPCIE_MSI_BASE 0x4C13000ull
+#define PCIE_MSI_MAX_OFFSET 0x8000
+#define PCIE_MSI_SECTION 0x1000
+#define mmPCIE_ELBI_RR_MSTR_IF_RR_SHRD_HBW_BASE 0x4C14000ull
+#define PCIE_ELBI_RR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define PCIE_ELBI_RR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmPCIE_ELBI_RR_MSTR_IF_RR_PRVT_HBW_BASE 0x4C14200ull
+#define PCIE_ELBI_RR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define PCIE_ELBI_RR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmPCIE_ELBI_RR_MSTR_IF_RR_SHRD_LBW_BASE 0x4C14400ull
+#define PCIE_ELBI_RR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define PCIE_ELBI_RR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmPCIE_ELBI_RR_MSTR_IF_RR_PRVT_LBW_BASE 0x4C14600ull
+#define PCIE_ELBI_RR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define PCIE_ELBI_RR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmPCIE_ELBI_RR_MSTR_IF_E2E_CRDT_BASE 0x4C14800ull
+#define PCIE_ELBI_RR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define PCIE_ELBI_RR_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmPCIE_ELBI_RR_MSTR_IF_AXUSER_BASE 0x4C14A80ull
+#define PCIE_ELBI_RR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define PCIE_ELBI_RR_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmPCIE_ELBI_RR_MSTR_IF_DBG_HBW_BASE 0x4C14B00ull
+#define PCIE_ELBI_RR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define PCIE_ELBI_RR_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmPCIE_ELBI_RR_MSTR_IF_DBG_LBW_BASE 0x4C14B80ull
+#define PCIE_ELBI_RR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define PCIE_ELBI_RR_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmPCIE_ELBI_RR_MSTR_IF_CORE_HBW_BASE 0x4C14C00ull
+#define PCIE_ELBI_RR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define PCIE_ELBI_RR_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmPCIE_ELBI_RR_MSTR_IF_CORE_LBW_BASE 0x4C14D80ull
+#define PCIE_ELBI_RR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define PCIE_ELBI_RR_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmPCIE_ELBI_RR_MSTR_IF_SPECIAL_BASE 0x4C14E80ull
+#define PCIE_ELBI_RR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define PCIE_ELBI_RR_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmPCIE_MSTR_RR_MSTR_IF_RR_SHRD_HBW_BASE 0x4C15000ull
+#define PCIE_MSTR_RR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define PCIE_MSTR_RR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmPCIE_MSTR_RR_MSTR_IF_RR_PRVT_HBW_BASE 0x4C15200ull
+#define PCIE_MSTR_RR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define PCIE_MSTR_RR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmPCIE_MSTR_RR_MSTR_IF_RR_SHRD_LBW_BASE 0x4C15400ull
+#define PCIE_MSTR_RR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define PCIE_MSTR_RR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmPCIE_MSTR_RR_MSTR_IF_RR_PRVT_LBW_BASE 0x4C15600ull
+#define PCIE_MSTR_RR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define PCIE_MSTR_RR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmPCIE_MSTR_RR_MSTR_IF_E2E_CRDT_BASE 0x4C15800ull
+#define PCIE_MSTR_RR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define PCIE_MSTR_RR_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmPCIE_MSTR_RR_MSTR_IF_AXUSER_BASE 0x4C15A80ull
+#define PCIE_MSTR_RR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define PCIE_MSTR_RR_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmPCIE_MSTR_RR_MSTR_IF_DBG_HBW_BASE 0x4C15B00ull
+#define PCIE_MSTR_RR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define PCIE_MSTR_RR_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmPCIE_MSTR_RR_MSTR_IF_DBG_LBW_BASE 0x4C15B80ull
+#define PCIE_MSTR_RR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define PCIE_MSTR_RR_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmPCIE_MSTR_RR_MSTR_IF_CORE_HBW_BASE 0x4C15C00ull
+#define PCIE_MSTR_RR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define PCIE_MSTR_RR_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmPCIE_MSTR_RR_MSTR_IF_CORE_LBW_BASE 0x4C15D80ull
+#define PCIE_MSTR_RR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define PCIE_MSTR_RR_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmPCIE_MSTR_RR_MSTR_IF_SPECIAL_BASE 0x4C15E80ull
+#define PCIE_MSTR_RR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define PCIE_MSTR_RR_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmPCIE_LBW_RR_MSTR_IF_RR_SHRD_HBW_BASE 0x4C16000ull
+#define PCIE_LBW_RR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define PCIE_LBW_RR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmPCIE_LBW_RR_MSTR_IF_RR_PRVT_HBW_BASE 0x4C16200ull
+#define PCIE_LBW_RR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define PCIE_LBW_RR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmPCIE_LBW_RR_MSTR_IF_RR_SHRD_LBW_BASE 0x4C16400ull
+#define PCIE_LBW_RR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define PCIE_LBW_RR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmPCIE_LBW_RR_MSTR_IF_RR_PRVT_LBW_BASE 0x4C16600ull
+#define PCIE_LBW_RR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define PCIE_LBW_RR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmPCIE_LBW_RR_MSTR_IF_E2E_CRDT_BASE 0x4C16800ull
+#define PCIE_LBW_RR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define PCIE_LBW_RR_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmPCIE_LBW_RR_MSTR_IF_AXUSER_BASE 0x4C16A80ull
+#define PCIE_LBW_RR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define PCIE_LBW_RR_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmPCIE_LBW_RR_MSTR_IF_DBG_HBW_BASE 0x4C16B00ull
+#define PCIE_LBW_RR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define PCIE_LBW_RR_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmPCIE_LBW_RR_MSTR_IF_DBG_LBW_BASE 0x4C16B80ull
+#define PCIE_LBW_RR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define PCIE_LBW_RR_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmPCIE_LBW_RR_MSTR_IF_CORE_HBW_BASE 0x4C16C00ull
+#define PCIE_LBW_RR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define PCIE_LBW_RR_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmPCIE_LBW_RR_MSTR_IF_CORE_LBW_BASE 0x4C16D80ull
+#define PCIE_LBW_RR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define PCIE_LBW_RR_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmPCIE_LBW_RR_MSTR_IF_SPECIAL_BASE 0x4C16E80ull
+#define PCIE_LBW_RR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define PCIE_LBW_RR_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmPCIE_MSIX_BASE 0x4C17000ull
+#define PCIE_MSIX_MAX_OFFSET 0x4000
+#define PCIE_MSIX_SECTION 0x29000
+#define mmPSOC_I2C_M0_BASE 0x4C40000ull
+#define PSOC_I2C_M0_MAX_OFFSET 0x1000
+#define PSOC_I2C_M0_SECTION 0x1000
+#define mmPSOC_I2C_M1_BASE 0x4C41000ull
+#define PSOC_I2C_M1_MAX_OFFSET 0x1000
+#define PSOC_I2C_M1_SECTION 0x1000
+#define mmPSOC_I2C_S_BASE 0x4C42000ull
+#define PSOC_I2C_S_MAX_OFFSET 0x1000
+#define PSOC_I2C_S_SECTION 0x1000
+#define mmPSOC_SPI_BASE 0x4C43000ull
+#define PSOC_SPI_MAX_OFFSET 0x1000
+#define PSOC_SPI_SECTION 0x1000
+#define mmPSOC_QSPI_BASE 0x4C44000ull
+#define PSOC_QSPI_MAX_OFFSET 0x1000
+#define PSOC_QSPI_SECTION 0x1000
+#define mmPSOC_UART_0_BASE 0x4C45000ull
+#define PSOC_UART_0_MAX_OFFSET 0x1000
+#define PSOC_UART_0_SECTION 0x1000
+#define mmPSOC_UART_1_BASE 0x4C46000ull
+#define PSOC_UART_1_MAX_OFFSET 0x1000
+#define PSOC_UART_1_SECTION 0x1000
+#define mmPSOC_TIMER_BASE 0x4C47000ull
+#define PSOC_TIMER_MAX_OFFSET 0x1000
+#define PSOC_TIMER_SECTION 0x1000
+#define mmPSOC_WDOG_BASE 0x4C48000ull
+#define PSOC_WDOG_MAX_OFFSET 0x1000
+#define PSOC_WDOG_SECTION 0x1000
+#define mmPSOC_TIMESTAMP_BASE 0x4C49000ull
+#define PSOC_TIMESTAMP_MAX_OFFSET 0x1000
+#define PSOC_TIMESTAMP_SECTION 0x1000
+#define mmPSOC_EFUSE_BASE 0x4C4A000ull
+#define PSOC_EFUSE_MAX_OFFSET 0x1000
+#define PSOC_EFUSE_SECTION 0xE800
+#define mmPSOC_EFUSE_SPECIAL_BASE 0x4C4AE80ull
+#define PSOC_EFUSE_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_EFUSE_SPECIAL_SECTION 0x1800
+#define mmPSOC_GLOBAL_CONF_BASE 0x4C4B000ull
+#define PSOC_GLOBAL_CONF_MAX_OFFSET 0x1000
+#define PSOC_GLOBAL_CONF_SECTION 0xE800
+#define mmPSOC_GLOBAL_CONF_SPECIAL_BASE 0x4C4BE80ull
+#define PSOC_GLOBAL_CONF_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_GLOBAL_CONF_SPECIAL_SECTION 0x1800
+#define mmPSOC_GPIO0_BASE 0x4C4C000ull
+#define PSOC_GPIO0_MAX_OFFSET 0x1000
+#define PSOC_GPIO0_SECTION 0x1000
+#define mmPSOC_GPIO1_BASE 0x4C4D000ull
+#define PSOC_GPIO1_MAX_OFFSET 0x1000
+#define PSOC_GPIO1_SECTION 0x1000
+#define mmPSOC_BTL_BASE 0x4C4E000ull
+#define PSOC_BTL_MAX_OFFSET 0x1000
+#define PSOC_BTL_SECTION 0xE800
+#define mmPSOC_BTL_SPECIAL_BASE 0x4C4EE80ull
+#define PSOC_BTL_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_BTL_SPECIAL_SECTION 0x1800
+#define mmPSOC_CS_TRACE_BASE 0x4C4F000ull
+#define PSOC_CS_TRACE_MAX_OFFSET 0x1000
+#define PSOC_CS_TRACE_SECTION 0xE800
+#define mmPSOC_CS_TRACE_SPECIAL_BASE 0x4C4FE80ull
+#define PSOC_CS_TRACE_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_CS_TRACE_SPECIAL_SECTION 0x1800
+#define mmPSOC_GPIO2_BASE 0x4C50000ull
+#define PSOC_GPIO2_MAX_OFFSET 0x1000
+#define PSOC_GPIO2_SECTION 0x1000
+#define mmPSOC_GPIO3_BASE 0x4C51000ull
+#define PSOC_GPIO3_MAX_OFFSET 0x1000
+#define PSOC_GPIO3_SECTION 0x2000
+#define mmPSOC_DFT_EFUSE_BASE 0x4C53000ull
+#define PSOC_DFT_EFUSE_MAX_OFFSET 0x1000
+#define PSOC_DFT_EFUSE_SECTION 0xE800
+#define mmPSOC_DFT_EFUSE_SPECIAL_BASE 0x4C53E80ull
+#define PSOC_DFT_EFUSE_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_DFT_EFUSE_SPECIAL_SECTION 0x1800
+#define mmPSOC_RPM_0_BASE 0x4C54000ull
+#define PSOC_RPM_0_MAX_OFFSET 0x1000
+#define PSOC_RPM_0_SECTION 0xE800
+#define mmPSOC_RPM_0_SPECIAL_BASE 0x4C54E80ull
+#define PSOC_RPM_0_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_RPM_0_SPECIAL_SECTION 0x1800
+#define mmPSOC_RPM_1_BASE 0x4C55000ull
+#define PSOC_RPM_1_MAX_OFFSET 0x1000
+#define PSOC_RPM_1_SECTION 0xE800
+#define mmPSOC_RPM_1_SPECIAL_BASE 0x4C55E80ull
+#define PSOC_RPM_1_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_RPM_1_SPECIAL_SECTION 0x1800
+#define mmPSOC_GPIO4_BASE 0x4C56000ull
+#define PSOC_GPIO4_MAX_OFFSET 0x1000
+#define PSOC_GPIO4_SECTION 0x1000
+#define mmPSOC_GPIO5_BASE 0x4C57000ull
+#define PSOC_GPIO5_MAX_OFFSET 0x1000
+#define PSOC_GPIO5_SECTION 0x1000
+#define mmPSOC_PID_BASE 0x4C58000ull
+#define PSOC_PID_MAX_OFFSET 0x1000
+#define PSOC_PID_SECTION 0xE800
+#define mmPSOC_PID_SPECIAL_BASE 0x4C58E80ull
+#define PSOC_PID_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_PID_SPECIAL_SECTION 0x1800
+#define mmPSOC_ARC0_CFG_BASE 0x4C59000ull
+#define PSOC_ARC0_CFG_MAX_OFFSET 0x1000
+#define PSOC_ARC0_CFG_SECTION 0xE800
+#define mmPSOC_ARC0_CFG_SPECIAL_BASE 0x4C59E80ull
+#define PSOC_ARC0_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_ARC0_CFG_SPECIAL_SECTION 0x1800
+#define mmPSOC_ARC0_MSTR_IF_RR_SHRD_HBW_BASE 0x4C5A000ull
+#define PSOC_ARC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define PSOC_ARC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmPSOC_ARC0_MSTR_IF_RR_PRVT_HBW_BASE 0x4C5A200ull
+#define PSOC_ARC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define PSOC_ARC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmPSOC_ARC0_MSTR_IF_RR_SHRD_LBW_BASE 0x4C5A400ull
+#define PSOC_ARC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define PSOC_ARC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmPSOC_ARC0_MSTR_IF_RR_PRVT_LBW_BASE 0x4C5A600ull
+#define PSOC_ARC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define PSOC_ARC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmPSOC_ARC0_MSTR_IF_E2E_CRDT_BASE 0x4C5A800ull
+#define PSOC_ARC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define PSOC_ARC0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmPSOC_ARC0_MSTR_IF_AXUSER_BASE 0x4C5AA80ull
+#define PSOC_ARC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define PSOC_ARC0_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmPSOC_ARC0_MSTR_IF_DBG_HBW_BASE 0x4C5AB00ull
+#define PSOC_ARC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define PSOC_ARC0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmPSOC_ARC0_MSTR_IF_DBG_LBW_BASE 0x4C5AB80ull
+#define PSOC_ARC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define PSOC_ARC0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmPSOC_ARC0_MSTR_IF_CORE_HBW_BASE 0x4C5AC00ull
+#define PSOC_ARC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define PSOC_ARC0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmPSOC_ARC0_MSTR_IF_CORE_LBW_BASE 0x4C5AD80ull
+#define PSOC_ARC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define PSOC_ARC0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmPSOC_ARC0_MSTR_IF_SPECIAL_BASE 0x4C5AE80ull
+#define PSOC_ARC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_ARC0_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmPSOC_ARC0_AUX_BASE 0x4C5B000ull
+#define PSOC_ARC0_AUX_MAX_OFFSET 0x1000
+#define PSOC_ARC0_AUX_SECTION 0xE800
+#define mmPSOC_ARC0_AUX_SPECIAL_BASE 0x4C5BE80ull
+#define PSOC_ARC0_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_ARC0_AUX_SPECIAL_SECTION 0x1800
+#define mmPSOC_ARC1_CFG_BASE 0x4C5C000ull
+#define PSOC_ARC1_CFG_MAX_OFFSET 0x1000
+#define PSOC_ARC1_CFG_SECTION 0xE800
+#define mmPSOC_ARC1_CFG_SPECIAL_BASE 0x4C5CE80ull
+#define PSOC_ARC1_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_ARC1_CFG_SPECIAL_SECTION 0x1800
+#define mmPSOC_ARC1_MSTR_IF_RR_SHRD_HBW_BASE 0x4C5D000ull
+#define PSOC_ARC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define PSOC_ARC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmPSOC_ARC1_MSTR_IF_RR_PRVT_HBW_BASE 0x4C5D200ull
+#define PSOC_ARC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define PSOC_ARC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmPSOC_ARC1_MSTR_IF_RR_SHRD_LBW_BASE 0x4C5D400ull
+#define PSOC_ARC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define PSOC_ARC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmPSOC_ARC1_MSTR_IF_RR_PRVT_LBW_BASE 0x4C5D600ull
+#define PSOC_ARC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define PSOC_ARC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmPSOC_ARC1_MSTR_IF_E2E_CRDT_BASE 0x4C5D800ull
+#define PSOC_ARC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define PSOC_ARC1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmPSOC_ARC1_MSTR_IF_AXUSER_BASE 0x4C5DA80ull
+#define PSOC_ARC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define PSOC_ARC1_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmPSOC_ARC1_MSTR_IF_DBG_HBW_BASE 0x4C5DB00ull
+#define PSOC_ARC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define PSOC_ARC1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmPSOC_ARC1_MSTR_IF_DBG_LBW_BASE 0x4C5DB80ull
+#define PSOC_ARC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define PSOC_ARC1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmPSOC_ARC1_MSTR_IF_CORE_HBW_BASE 0x4C5DC00ull
+#define PSOC_ARC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define PSOC_ARC1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmPSOC_ARC1_MSTR_IF_CORE_LBW_BASE 0x4C5DD80ull
+#define PSOC_ARC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define PSOC_ARC1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmPSOC_ARC1_MSTR_IF_SPECIAL_BASE 0x4C5DE80ull
+#define PSOC_ARC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_ARC1_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmPSOC_ARC1_AUX_BASE 0x4C5E000ull
+#define PSOC_ARC1_AUX_MAX_OFFSET 0x1000
+#define PSOC_ARC1_AUX_SECTION 0xE800
+#define mmPSOC_ARC1_AUX_SPECIAL_BASE 0x4C5EE80ull
+#define PSOC_ARC1_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_ARC1_AUX_SPECIAL_SECTION 0x1180
+#define mmPSOC_SECURITY_BASE 0x4C60000ull
+#define PSOC_SECURITY_MAX_OFFSET 0x1000
+#define PSOC_SECURITY_SECTION 0xE800
+#define mmPSOC_SECURITY_SPECIAL_BASE 0x4C60E80ull
+#define PSOC_SECURITY_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_SECURITY_SPECIAL_SECTION 0x1800
+#define mmJT_MSTR_IF_RR_SHRD_HBW_BASE 0x4C61000ull
+#define JT_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define JT_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmJT_MSTR_IF_RR_PRVT_HBW_BASE 0x4C61200ull
+#define JT_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define JT_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmJT_MSTR_IF_RR_SHRD_LBW_BASE 0x4C61400ull
+#define JT_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define JT_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmJT_MSTR_IF_RR_PRVT_LBW_BASE 0x4C61600ull
+#define JT_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define JT_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmJT_MSTR_IF_E2E_CRDT_BASE 0x4C61800ull
+#define JT_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define JT_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmJT_MSTR_IF_AXUSER_BASE 0x4C61A80ull
+#define JT_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define JT_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmJT_MSTR_IF_DBG_HBW_BASE 0x4C61B00ull
+#define JT_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define JT_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmJT_MSTR_IF_DBG_LBW_BASE 0x4C61B80ull
+#define JT_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define JT_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmJT_MSTR_IF_CORE_HBW_BASE 0x4C61C00ull
+#define JT_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define JT_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmJT_MSTR_IF_CORE_LBW_BASE 0x4C61D80ull
+#define JT_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define JT_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmJT_MSTR_IF_SPECIAL_BASE 0x4C61E80ull
+#define JT_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define JT_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmSMI_MSTR_IF_RR_SHRD_HBW_BASE 0x4C62000ull
+#define SMI_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define SMI_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmSMI_MSTR_IF_RR_PRVT_HBW_BASE 0x4C62200ull
+#define SMI_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define SMI_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmSMI_MSTR_IF_RR_SHRD_LBW_BASE 0x4C62400ull
+#define SMI_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define SMI_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmSMI_MSTR_IF_RR_PRVT_LBW_BASE 0x4C62600ull
+#define SMI_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define SMI_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmSMI_MSTR_IF_E2E_CRDT_BASE 0x4C62800ull
+#define SMI_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define SMI_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmSMI_MSTR_IF_AXUSER_BASE 0x4C62A80ull
+#define SMI_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define SMI_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmSMI_MSTR_IF_DBG_HBW_BASE 0x4C62B00ull
+#define SMI_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define SMI_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmSMI_MSTR_IF_DBG_LBW_BASE 0x4C62B80ull
+#define SMI_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define SMI_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmSMI_MSTR_IF_CORE_HBW_BASE 0x4C62C00ull
+#define SMI_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define SMI_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmSMI_MSTR_IF_CORE_LBW_BASE 0x4C62D80ull
+#define SMI_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define SMI_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmSMI_MSTR_IF_SPECIAL_BASE 0x4C62E80ull
+#define SMI_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define SMI_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmI2C_S_MSTR_IF_RR_SHRD_HBW_BASE 0x4C63000ull
+#define I2C_S_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define I2C_S_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmI2C_S_MSTR_IF_RR_PRVT_HBW_BASE 0x4C63200ull
+#define I2C_S_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define I2C_S_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmI2C_S_MSTR_IF_RR_SHRD_LBW_BASE 0x4C63400ull
+#define I2C_S_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define I2C_S_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmI2C_S_MSTR_IF_RR_PRVT_LBW_BASE 0x4C63600ull
+#define I2C_S_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define I2C_S_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmI2C_S_MSTR_IF_E2E_CRDT_BASE 0x4C63800ull
+#define I2C_S_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define I2C_S_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmI2C_S_MSTR_IF_AXUSER_BASE 0x4C63A80ull
+#define I2C_S_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define I2C_S_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmI2C_S_MSTR_IF_DBG_HBW_BASE 0x4C63B00ull
+#define I2C_S_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define I2C_S_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmI2C_S_MSTR_IF_DBG_LBW_BASE 0x4C63B80ull
+#define I2C_S_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define I2C_S_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmI2C_S_MSTR_IF_CORE_HBW_BASE 0x4C63C00ull
+#define I2C_S_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define I2C_S_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmI2C_S_MSTR_IF_CORE_LBW_BASE 0x4C63D80ull
+#define I2C_S_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define I2C_S_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmI2C_S_MSTR_IF_SPECIAL_BASE 0x4C63E80ull
+#define I2C_S_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define I2C_S_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmPSOC_SVID0_BASE 0x4C64000ull
+#define PSOC_SVID0_MAX_OFFSET 0x1000
+#define PSOC_SVID0_SECTION 0xE800
+#define mmPSOC_SVID0_SPECIAL_BASE 0x4C64E80ull
+#define PSOC_SVID0_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_SVID0_SPECIAL_SECTION 0x1800
+#define mmPSOC_SVID1_BASE 0x4C65000ull
+#define PSOC_SVID1_MAX_OFFSET 0x1000
+#define PSOC_SVID1_SECTION 0xE800
+#define mmPSOC_SVID1_SPECIAL_BASE 0x4C65E80ull
+#define PSOC_SVID1_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_SVID1_SPECIAL_SECTION 0x1800
+#define mmPSOC_SVID2_BASE 0x4C66000ull
+#define PSOC_SVID2_MAX_OFFSET 0x1000
+#define PSOC_SVID2_SECTION 0xE800
+#define mmPSOC_SVID2_SPECIAL_BASE 0x4C66E80ull
+#define PSOC_SVID2_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_SVID2_SPECIAL_SECTION 0x5180
+#define mmPSOC_MME_PLL_CTRL_BASE 0x4C6C000ull
+#define PSOC_MME_PLL_CTRL_MAX_OFFSET 0x3540
+#define PSOC_MME_PLL_CTRL_SECTION 0x3600
+#define mmPSOC_MME_PLL_ASIF_SLV_BASE 0x4C6C360ull
+#define PSOC_MME_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define PSOC_MME_PLL_ASIF_SLV_SECTION 0xA000
+#define mmPSOC_MME_PLL_DIV_0_RLX_BASE 0x4C6C400ull
+#define PSOC_MME_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define PSOC_MME_PLL_DIV_0_RLX_SECTION 0x4000
+#define mmPSOC_MME_PLL_DIV_1_RLX_BASE 0x4C6C800ull
+#define PSOC_MME_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define PSOC_MME_PLL_DIV_1_RLX_SECTION 0x2000
+#define mmPSOC_MME_PLL_DIV_2_RLX_BASE 0x4C6CA00ull
+#define PSOC_MME_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define PSOC_MME_PLL_DIV_2_RLX_SECTION 0x2000
+#define mmPSOC_MME_PLL_DIV_3_RLX_BASE 0x4C6CC00ull
+#define PSOC_MME_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define PSOC_MME_PLL_DIV_3_RLX_SECTION 0x2800
+#define mmPSOC_MME_PLL_SPECIAL_BASE 0x4C6CE80ull
+#define PSOC_MME_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_MME_PLL_SPECIAL_SECTION 0x1800
+#define mmPSOC_CPU_PLL_CTRL_BASE 0x4C6D000ull
+#define PSOC_CPU_PLL_CTRL_MAX_OFFSET 0x3540
+#define PSOC_CPU_PLL_CTRL_SECTION 0x3600
+#define mmPSOC_CPU_PLL_ASIF_SLV_BASE 0x4C6D360ull
+#define PSOC_CPU_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define PSOC_CPU_PLL_ASIF_SLV_SECTION 0xA000
+#define mmPSOC_CPU_PLL_DIV_0_RLX_BASE 0x4C6D400ull
+#define PSOC_CPU_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define PSOC_CPU_PLL_DIV_0_RLX_SECTION 0x4000
+#define mmPSOC_CPU_PLL_DIV_1_RLX_BASE 0x4C6D800ull
+#define PSOC_CPU_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define PSOC_CPU_PLL_DIV_1_RLX_SECTION 0x2000
+#define mmPSOC_CPU_PLL_DIV_2_RLX_BASE 0x4C6DA00ull
+#define PSOC_CPU_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define PSOC_CPU_PLL_DIV_2_RLX_SECTION 0x2000
+#define mmPSOC_CPU_PLL_DIV_3_RLX_BASE 0x4C6DC00ull
+#define PSOC_CPU_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define PSOC_CPU_PLL_DIV_3_RLX_SECTION 0x2800
+#define mmPSOC_CPU_PLL_SPECIAL_BASE 0x4C6DE80ull
+#define PSOC_CPU_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_CPU_PLL_SPECIAL_SECTION 0x1800
+#define mmPSOC_VID_PLL_CTRL_BASE 0x4C6E000ull
+#define PSOC_VID_PLL_CTRL_MAX_OFFSET 0x3540
+#define PSOC_VID_PLL_CTRL_SECTION 0x3600
+#define mmPSOC_VID_PLL_ASIF_SLV_BASE 0x4C6E360ull
+#define PSOC_VID_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define PSOC_VID_PLL_ASIF_SLV_SECTION 0xA000
+#define mmPSOC_VID_PLL_DIV_0_RLX_BASE 0x4C6E400ull
+#define PSOC_VID_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define PSOC_VID_PLL_DIV_0_RLX_SECTION 0x4000
+#define mmPSOC_VID_PLL_DIV_1_RLX_BASE 0x4C6E800ull
+#define PSOC_VID_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define PSOC_VID_PLL_DIV_1_RLX_SECTION 0x2000
+#define mmPSOC_VID_PLL_DIV_2_RLX_BASE 0x4C6EA00ull
+#define PSOC_VID_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define PSOC_VID_PLL_DIV_2_RLX_SECTION 0x2000
+#define mmPSOC_VID_PLL_DIV_3_RLX_BASE 0x4C6EC00ull
+#define PSOC_VID_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define PSOC_VID_PLL_DIV_3_RLX_SECTION 0x2800
+#define mmPSOC_VID_PLL_SPECIAL_BASE 0x4C6EE80ull
+#define PSOC_VID_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_VID_PLL_SPECIAL_SECTION 0x5180
+#define mmPSOC_RESET_CONF_BASE 0x4C74000ull
+#define PSOC_RESET_CONF_MAX_OFFSET 0x1000
+#define PSOC_RESET_CONF_SECTION 0xE800
+#define mmPSOC_RESET_CONF_SPECIAL_BASE 0x4C74E80ull
+#define PSOC_RESET_CONF_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_RESET_CONF_SPECIAL_SECTION 0x1800
+#define mmPSOC_DFT_APB_BASE 0x4C75000ull
+#define PSOC_DFT_APB_MAX_OFFSET 0x8000
+#define PSOC_DFT_APB_SECTION 0x1000
+#define mmPSOC_AVS0_BASE 0x4C76000ull
+#define PSOC_AVS0_MAX_OFFSET 0x1000
+#define PSOC_AVS0_SECTION 0xE800
+#define mmPSOC_AVS0_SPECIAL_BASE 0x4C76E80ull
+#define PSOC_AVS0_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_AVS0_SPECIAL_SECTION 0x1800
+#define mmPSOC_AVS1_BASE 0x4C77000ull
+#define PSOC_AVS1_MAX_OFFSET 0x1000
+#define PSOC_AVS1_SECTION 0xE800
+#define mmPSOC_AVS1_SPECIAL_BASE 0x4C77E80ull
+#define PSOC_AVS1_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_AVS1_SPECIAL_SECTION 0x1800
+#define mmPSOC_AVS2_BASE 0x4C78000ull
+#define PSOC_AVS2_MAX_OFFSET 0x1000
+#define PSOC_AVS2_SECTION 0xE800
+#define mmPSOC_AVS2_SPECIAL_BASE 0x4C78E80ull
+#define PSOC_AVS2_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_AVS2_SPECIAL_SECTION 0x1800
+#define mmPSOC_PWM0_BASE 0x4C79000ull
+#define PSOC_PWM0_MAX_OFFSET 0x1000
+#define PSOC_PWM0_SECTION 0xE800
+#define mmPSOC_PWM0_SPECIAL_BASE 0x4C79E80ull
+#define PSOC_PWM0_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_PWM0_SPECIAL_SECTION 0x1800
+#define mmPSOC_PWM1_BASE 0x4C7A000ull
+#define PSOC_PWM1_MAX_OFFSET 0x1000
+#define PSOC_PWM1_SECTION 0xE800
+#define mmPSOC_PWM1_SPECIAL_BASE 0x4C7AE80ull
+#define PSOC_PWM1_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_PWM1_SPECIAL_SECTION 0x1800
+#define mmSVID0_AC_BASE 0x4C7B000ull
+#define SVID0_AC_MAX_OFFSET 0x1000
+#define SVID0_AC_SECTION 0xE800
+#define mmSVID0_AC_SPECIAL_BASE 0x4C7BE80ull
+#define SVID0_AC_SPECIAL_MAX_OFFSET 0x1800
+#define SVID0_AC_SPECIAL_SECTION 0x1800
+#define mmSVID1_AC_BASE 0x4C7C000ull
+#define SVID1_AC_MAX_OFFSET 0x1000
+#define SVID1_AC_SECTION 0xE800
+#define mmSVID1_AC_SPECIAL_BASE 0x4C7CE80ull
+#define SVID1_AC_SPECIAL_MAX_OFFSET 0x1800
+#define SVID1_AC_SPECIAL_SECTION 0x1800
+#define mmSVID2_AC_BASE 0x4C7D000ull
+#define SVID2_AC_MAX_OFFSET 0x1000
+#define SVID2_AC_SECTION 0xE800
+#define mmSVID2_AC_SPECIAL_BASE 0x4C7DE80ull
+#define SVID2_AC_SPECIAL_MAX_OFFSET 0x1800
+#define SVID2_AC_SPECIAL_SECTION 0x1180
+#define mmPSOC_MSTR_IF_RR_SHRD_HBW_BASE 0x4C7F000ull
+#define PSOC_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define PSOC_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmPSOC_MSTR_IF_RR_PRVT_HBW_BASE 0x4C7F200ull
+#define PSOC_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define PSOC_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmPSOC_MSTR_IF_RR_SHRD_LBW_BASE 0x4C7F400ull
+#define PSOC_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define PSOC_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmPSOC_MSTR_IF_RR_PRVT_LBW_BASE 0x4C7F600ull
+#define PSOC_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define PSOC_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmPSOC_MSTR_IF_E2E_CRDT_BASE 0x4C7F800ull
+#define PSOC_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define PSOC_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmPSOC_MSTR_IF_AXUSER_BASE 0x4C7FA80ull
+#define PSOC_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define PSOC_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmPSOC_MSTR_IF_DBG_HBW_BASE 0x4C7FB00ull
+#define PSOC_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define PSOC_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmPSOC_MSTR_IF_DBG_LBW_BASE 0x4C7FB80ull
+#define PSOC_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define PSOC_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmPSOC_MSTR_IF_CORE_HBW_BASE 0x4C7FC00ull
+#define PSOC_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define PSOC_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmPSOC_MSTR_IF_CORE_LBW_BASE 0x4C7FD80ull
+#define PSOC_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define PSOC_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmPSOC_MSTR_IF_SPECIAL_BASE 0x4C7FE80ull
+#define PSOC_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define PSOC_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmPDMA0_QM_ARC_DCCM_BASE 0x4C80000ull
+#define PDMA0_QM_ARC_DCCM_MAX_OFFSET 0x4000
+#define PDMA0_QM_ARC_DCCM_SECTION 0x8000
+#define mmPDMA0_QM_ARC_AUX_BASE 0x4C88000ull
+#define PDMA0_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define PDMA0_QM_ARC_AUX_SECTION 0xE800
+#define mmPDMA0_QM_ARC_AUX_SPECIAL_BASE 0x4C88E80ull
+#define PDMA0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define PDMA0_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define mmPDMA0_QM_BASE 0x4C8A000ull
+#define PDMA0_QM_MAX_OFFSET 0x1000
+#define PDMA0_QM_SECTION 0x9000
+#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x4C8A900ull
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x4C8A908ull
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x4C8A910ull
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x4C8A918ull
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x4C8A920ull
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x4C8A928ull
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x4C8A930ull
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x4C8A938ull
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x4C8A940ull
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x4C8A948ull
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x4C8A950ull
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x4C8A958ull
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x4C8A960ull
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x4C8A968ull
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x4C8A970ull
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x4C8A978ull
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define PDMA0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmPDMA0_QM_AXUSER_SECURED_BASE 0x4C8AB00ull
+#define PDMA0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define PDMA0_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmPDMA0_QM_AXUSER_NONSECURED_BASE 0x4C8AB80ull
+#define PDMA0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define PDMA0_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmPDMA0_QM_DBG_HBW_BASE 0x4C8AC00ull
+#define PDMA0_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define PDMA0_QM_DBG_HBW_SECTION 0x8000
+#define mmPDMA0_QM_DBG_LBW_BASE 0x4C8AC80ull
+#define PDMA0_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define PDMA0_QM_DBG_LBW_SECTION 0x1000
+#define mmPDMA0_QM_CGM_BASE 0x4C8AD80ull
+#define PDMA0_QM_CGM_MAX_OFFSET 0xC000
+#define PDMA0_QM_CGM_SECTION 0x1000
+#define mmPDMA0_QM_SPECIAL_BASE 0x4C8AE80ull
+#define PDMA0_QM_SPECIAL_MAX_OFFSET 0x1800
+#define PDMA0_QM_SPECIAL_SECTION 0x1800
+#define mmPDMA0_CORE_BASE 0x4C8B000ull
+#define PDMA0_CORE_MAX_OFFSET 0x1000
+#define PDMA0_CORE_SECTION 0x8000
+#define mmPDMA0_CORE_CTX_AXUSER_BASE 0x4C8B800ull
+#define PDMA0_CORE_CTX_AXUSER_MAX_OFFSET 0x5000
+#define PDMA0_CORE_CTX_AXUSER_SECTION 0x6000
+#define mmPDMA0_CORE_CTX_BASE 0x4C8B860ull
+#define PDMA0_CORE_CTX_MAX_OFFSET 0x9000
+#define PDMA0_CORE_CTX_SECTION 0x5A00
+#define mmPDMA0_CORE_KDMA_CGM_BASE 0x4C8BE00ull
+#define PDMA0_CORE_KDMA_CGM_MAX_OFFSET 0xC000
+#define PDMA0_CORE_KDMA_CGM_SECTION 0x8000
+#define mmPDMA0_CORE_SPECIAL_BASE 0x4C8BE80ull
+#define PDMA0_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define PDMA0_CORE_SPECIAL_SECTION 0x1800
+#define mmPDMA0_MSTR_IF_RR_SHRD_HBW_BASE 0x4C8C000ull
+#define PDMA0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define PDMA0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmPDMA0_MSTR_IF_RR_PRVT_HBW_BASE 0x4C8C200ull
+#define PDMA0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define PDMA0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmPDMA0_MSTR_IF_RR_SHRD_LBW_BASE 0x4C8C400ull
+#define PDMA0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define PDMA0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmPDMA0_MSTR_IF_RR_PRVT_LBW_BASE 0x4C8C600ull
+#define PDMA0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define PDMA0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmPDMA0_MSTR_IF_E2E_CRDT_BASE 0x4C8C800ull
+#define PDMA0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define PDMA0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmPDMA0_MSTR_IF_AXUSER_BASE 0x4C8CA80ull
+#define PDMA0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define PDMA0_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmPDMA0_MSTR_IF_DBG_HBW_BASE 0x4C8CB00ull
+#define PDMA0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define PDMA0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmPDMA0_MSTR_IF_DBG_LBW_BASE 0x4C8CB80ull
+#define PDMA0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define PDMA0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmPDMA0_MSTR_IF_CORE_HBW_BASE 0x4C8CC00ull
+#define PDMA0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define PDMA0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmPDMA0_MSTR_IF_CORE_LBW_BASE 0x4C8CD80ull
+#define PDMA0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define PDMA0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmPDMA0_MSTR_IF_SPECIAL_BASE 0x4C8CE80ull
+#define PDMA0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define PDMA0_MSTR_IF_SPECIAL_SECTION 0x3180
+#define mmPDMA1_QM_ARC_DCCM_BASE 0x4C90000ull
+#define PDMA1_QM_ARC_DCCM_MAX_OFFSET 0x4000
+#define PDMA1_QM_ARC_DCCM_SECTION 0x8000
+#define mmPDMA1_QM_ARC_AUX_BASE 0x4C98000ull
+#define PDMA1_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define PDMA1_QM_ARC_AUX_SECTION 0xE800
+#define mmPDMA1_QM_ARC_AUX_SPECIAL_BASE 0x4C98E80ull
+#define PDMA1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define PDMA1_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define mmPDMA1_QM_BASE 0x4C9A000ull
+#define PDMA1_QM_MAX_OFFSET 0x1000
+#define PDMA1_QM_SECTION 0x9000
+#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x4C9A900ull
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x4C9A908ull
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x4C9A910ull
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x4C9A918ull
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x4C9A920ull
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x4C9A928ull
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x4C9A930ull
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x4C9A938ull
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x4C9A940ull
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x4C9A948ull
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x4C9A950ull
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x4C9A958ull
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x4C9A960ull
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x4C9A968ull
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x4C9A970ull
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x4C9A978ull
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define PDMA1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmPDMA1_QM_AXUSER_SECURED_BASE 0x4C9AB00ull
+#define PDMA1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define PDMA1_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmPDMA1_QM_AXUSER_NONSECURED_BASE 0x4C9AB80ull
+#define PDMA1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define PDMA1_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmPDMA1_QM_DBG_HBW_BASE 0x4C9AC00ull
+#define PDMA1_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define PDMA1_QM_DBG_HBW_SECTION 0x8000
+#define mmPDMA1_QM_DBG_LBW_BASE 0x4C9AC80ull
+#define PDMA1_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define PDMA1_QM_DBG_LBW_SECTION 0x1000
+#define mmPDMA1_QM_CGM_BASE 0x4C9AD80ull
+#define PDMA1_QM_CGM_MAX_OFFSET 0xC000
+#define PDMA1_QM_CGM_SECTION 0x1000
+#define mmPDMA1_QM_SPECIAL_BASE 0x4C9AE80ull
+#define PDMA1_QM_SPECIAL_MAX_OFFSET 0x1800
+#define PDMA1_QM_SPECIAL_SECTION 0x1800
+#define mmPDMA1_CORE_BASE 0x4C9B000ull
+#define PDMA1_CORE_MAX_OFFSET 0x1000
+#define PDMA1_CORE_SECTION 0x8000
+#define mmPDMA1_CORE_CTX_AXUSER_BASE 0x4C9B800ull
+#define PDMA1_CORE_CTX_AXUSER_MAX_OFFSET 0x5000
+#define PDMA1_CORE_CTX_AXUSER_SECTION 0x6000
+#define mmPDMA1_CORE_CTX_BASE 0x4C9B860ull
+#define PDMA1_CORE_CTX_MAX_OFFSET 0x9000
+#define PDMA1_CORE_CTX_SECTION 0x5A00
+#define mmPDMA1_CORE_KDMA_CGM_BASE 0x4C9BE00ull
+#define PDMA1_CORE_KDMA_CGM_MAX_OFFSET 0xC000
+#define PDMA1_CORE_KDMA_CGM_SECTION 0x8000
+#define mmPDMA1_CORE_SPECIAL_BASE 0x4C9BE80ull
+#define PDMA1_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define PDMA1_CORE_SPECIAL_SECTION 0x1800
+#define mmPDMA1_MSTR_IF_RR_SHRD_HBW_BASE 0x4C9C000ull
+#define PDMA1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define PDMA1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmPDMA1_MSTR_IF_RR_PRVT_HBW_BASE 0x4C9C200ull
+#define PDMA1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define PDMA1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmPDMA1_MSTR_IF_RR_SHRD_LBW_BASE 0x4C9C400ull
+#define PDMA1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define PDMA1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmPDMA1_MSTR_IF_RR_PRVT_LBW_BASE 0x4C9C600ull
+#define PDMA1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define PDMA1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmPDMA1_MSTR_IF_E2E_CRDT_BASE 0x4C9C800ull
+#define PDMA1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define PDMA1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmPDMA1_MSTR_IF_AXUSER_BASE 0x4C9CA80ull
+#define PDMA1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define PDMA1_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmPDMA1_MSTR_IF_DBG_HBW_BASE 0x4C9CB00ull
+#define PDMA1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define PDMA1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmPDMA1_MSTR_IF_DBG_LBW_BASE 0x4C9CB80ull
+#define PDMA1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define PDMA1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmPDMA1_MSTR_IF_CORE_HBW_BASE 0x4C9CC00ull
+#define PDMA1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define PDMA1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmPDMA1_MSTR_IF_CORE_LBW_BASE 0x4C9CD80ull
+#define PDMA1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define PDMA1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmPDMA1_MSTR_IF_SPECIAL_BASE 0x4C9CE80ull
+#define PDMA1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define PDMA1_MSTR_IF_SPECIAL_SECTION 0x23180
+#define mmCPU_CA53_CFG_BASE 0x4CC0000ull
+#define CPU_CA53_CFG_MAX_OFFSET 0x1000
+#define CPU_CA53_CFG_SECTION 0xE800
+#define mmCPU_CA53_CFG_SPECIAL_BASE 0x4CC0E80ull
+#define CPU_CA53_CFG_SPECIAL_MAX_OFFSET 0x1800
+#define CPU_CA53_CFG_SPECIAL_SECTION 0x1800
+#define mmCPU_IF_BASE 0x4CC1000ull
+#define CPU_IF_MAX_OFFSET 0x1000
+#define CPU_IF_SECTION 0xE800
+#define mmCPU_IF_SPECIAL_BASE 0x4CC1E80ull
+#define CPU_IF_SPECIAL_MAX_OFFSET 0x1800
+#define CPU_IF_SPECIAL_SECTION 0x1800
+#define mmCPU_TIMESTAMP_BASE 0x4CC2000ull
+#define CPU_TIMESTAMP_MAX_OFFSET 0x1000
+#define CPU_TIMESTAMP_SECTION 0x1000
+#define mmCPU_MSTR_IF_RR_SHRD_HBW_BASE 0x4CC3000ull
+#define CPU_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define CPU_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmCPU_MSTR_IF_RR_PRVT_HBW_BASE 0x4CC3200ull
+#define CPU_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define CPU_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmCPU_MSTR_IF_RR_SHRD_LBW_BASE 0x4CC3400ull
+#define CPU_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define CPU_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmCPU_MSTR_IF_RR_PRVT_LBW_BASE 0x4CC3600ull
+#define CPU_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define CPU_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmCPU_MSTR_IF_E2E_CRDT_BASE 0x4CC3800ull
+#define CPU_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define CPU_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmCPU_MSTR_IF_AXUSER_BASE 0x4CC3A80ull
+#define CPU_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define CPU_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmCPU_MSTR_IF_DBG_HBW_BASE 0x4CC3B00ull
+#define CPU_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define CPU_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmCPU_MSTR_IF_DBG_LBW_BASE 0x4CC3B80ull
+#define CPU_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define CPU_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmCPU_MSTR_IF_CORE_HBW_BASE 0x4CC3C00ull
+#define CPU_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define CPU_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmCPU_MSTR_IF_CORE_LBW_BASE 0x4CC3D80ull
+#define CPU_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define CPU_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmCPU_MSTR_IF_SPECIAL_BASE 0x4CC3E80ull
+#define CPU_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define CPU_MSTR_IF_SPECIAL_SECTION 0x3C180
+#define mmPMMU_HBW_MMU_BASE 0x4D00000ull
+#define PMMU_HBW_MMU_MAX_OFFSET 0x1000
+#define PMMU_HBW_MMU_SECTION 0xE800
+#define mmPMMU_HBW_MMU_SPECIAL_BASE 0x4D00E80ull
+#define PMMU_HBW_MMU_SPECIAL_MAX_OFFSET 0x1800
+#define PMMU_HBW_MMU_SPECIAL_SECTION 0x1800
+#define mmPMMU_HBW_STLB_BASE 0x4D01000ull
+#define PMMU_HBW_STLB_MAX_OFFSET 0x1000
+#define PMMU_HBW_STLB_SECTION 0xE800
+#define mmPMMU_HBW_STLB_SPECIAL_BASE 0x4D01E80ull
+#define PMMU_HBW_STLB_SPECIAL_MAX_OFFSET 0x1800
+#define PMMU_HBW_STLB_SPECIAL_SECTION 0x1800
+#define mmPMMU_HBW_MSTR_IF_RR_SHRD_HBW_BASE 0x4D02000ull
+#define PMMU_HBW_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define PMMU_HBW_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmPMMU_HBW_MSTR_IF_RR_PRVT_HBW_BASE 0x4D02200ull
+#define PMMU_HBW_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define PMMU_HBW_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmPMMU_HBW_MSTR_IF_RR_SHRD_LBW_BASE 0x4D02400ull
+#define PMMU_HBW_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define PMMU_HBW_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmPMMU_HBW_MSTR_IF_RR_PRVT_LBW_BASE 0x4D02600ull
+#define PMMU_HBW_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define PMMU_HBW_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmPMMU_HBW_MSTR_IF_E2E_CRDT_BASE 0x4D02800ull
+#define PMMU_HBW_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define PMMU_HBW_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmPMMU_HBW_MSTR_IF_AXUSER_BASE 0x4D02A80ull
+#define PMMU_HBW_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define PMMU_HBW_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmPMMU_HBW_MSTR_IF_DBG_HBW_BASE 0x4D02B00ull
+#define PMMU_HBW_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define PMMU_HBW_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmPMMU_HBW_MSTR_IF_DBG_LBW_BASE 0x4D02B80ull
+#define PMMU_HBW_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define PMMU_HBW_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmPMMU_HBW_MSTR_IF_CORE_HBW_BASE 0x4D02C00ull
+#define PMMU_HBW_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define PMMU_HBW_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmPMMU_HBW_MSTR_IF_CORE_LBW_BASE 0x4D02D80ull
+#define PMMU_HBW_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define PMMU_HBW_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmPMMU_HBW_MSTR_IF_SPECIAL_BASE 0x4D02E80ull
+#define PMMU_HBW_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define PMMU_HBW_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmPMMU_PIF_BASE 0x4D03000ull
+#define PMMU_PIF_MAX_OFFSET 0x1000
+#define PMMU_PIF_SECTION 0xE800
+#define mmPMMU_PIF_SPECIAL_BASE 0x4D03E80ull
+#define PMMU_PIF_SPECIAL_MAX_OFFSET 0x1800
+#define PMMU_PIF_SPECIAL_SECTION 0x1800
+#define mmPMMU_MME_PLL_CTRL_BASE 0x4D04000ull
+#define PMMU_MME_PLL_CTRL_MAX_OFFSET 0x3540
+#define PMMU_MME_PLL_CTRL_SECTION 0x3600
+#define mmPMMU_MME_PLL_ASIF_SLV_BASE 0x4D04360ull
+#define PMMU_MME_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define PMMU_MME_PLL_ASIF_SLV_SECTION 0xA000
+#define mmPMMU_MME_PLL_DIV_0_RLX_BASE 0x4D04400ull
+#define PMMU_MME_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define PMMU_MME_PLL_DIV_0_RLX_SECTION 0x4000
+#define mmPMMU_MME_PLL_DIV_1_RLX_BASE 0x4D04800ull
+#define PMMU_MME_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define PMMU_MME_PLL_DIV_1_RLX_SECTION 0x2000
+#define mmPMMU_MME_PLL_DIV_2_RLX_BASE 0x4D04A00ull
+#define PMMU_MME_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define PMMU_MME_PLL_DIV_2_RLX_SECTION 0x2000
+#define mmPMMU_MME_PLL_DIV_3_RLX_BASE 0x4D04C00ull
+#define PMMU_MME_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define PMMU_MME_PLL_DIV_3_RLX_SECTION 0x2800
+#define mmPMMU_MME_PLL_SPECIAL_BASE 0x4D04E80ull
+#define PMMU_MME_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define PMMU_MME_PLL_SPECIAL_SECTION 0x1800
+#define mmPMMU_VID_PLL_CTRL_BASE 0x4D05000ull
+#define PMMU_VID_PLL_CTRL_MAX_OFFSET 0x3540
+#define PMMU_VID_PLL_CTRL_SECTION 0x3600
+#define mmPMMU_VID_PLL_ASIF_SLV_BASE 0x4D05360ull
+#define PMMU_VID_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define PMMU_VID_PLL_ASIF_SLV_SECTION 0xA000
+#define mmPMMU_VID_PLL_DIV_0_RLX_BASE 0x4D05400ull
+#define PMMU_VID_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define PMMU_VID_PLL_DIV_0_RLX_SECTION 0x4000
+#define mmPMMU_VID_PLL_DIV_1_RLX_BASE 0x4D05800ull
+#define PMMU_VID_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define PMMU_VID_PLL_DIV_1_RLX_SECTION 0x2000
+#define mmPMMU_VID_PLL_DIV_2_RLX_BASE 0x4D05A00ull
+#define PMMU_VID_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define PMMU_VID_PLL_DIV_2_RLX_SECTION 0x2000
+#define mmPMMU_VID_PLL_DIV_3_RLX_BASE 0x4D05C00ull
+#define PMMU_VID_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define PMMU_VID_PLL_DIV_3_RLX_SECTION 0x2800
+#define mmPMMU_VID_PLL_SPECIAL_BASE 0x4D05E80ull
+#define PMMU_VID_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define PMMU_VID_PLL_SPECIAL_SECTION 0x3A180
+#define mmXBAR_MID_0_BASE 0x4D40000ull
+#define XBAR_MID_0_MAX_OFFSET 0x1000
+#define XBAR_MID_0_SECTION 0xE800
+#define mmXBAR_MID_0_SPECIAL_BASE 0x4D40E80ull
+#define XBAR_MID_0_SPECIAL_MAX_OFFSET 0x1800
+#define XBAR_MID_0_SPECIAL_SECTION 0x1800
+#define mmDCORE0_XBAR_DMA_PLL_CTRL_BASE 0x4D41000ull
+#define DCORE0_XBAR_DMA_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE0_XBAR_DMA_PLL_CTRL_SECTION 0x3600
+#define mmDCORE0_XBAR_DMA_PLL_ASIF_SLV_BASE 0x4D41360ull
+#define DCORE0_XBAR_DMA_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE0_XBAR_DMA_PLL_ASIF_SLV_SECTION 0xA000
+#define mmDCORE0_XBAR_DMA_PLL_DIV_0_RLX_BASE 0x4D41400ull
+#define DCORE0_XBAR_DMA_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE0_XBAR_DMA_PLL_DIV_0_RLX_SECTION 0x4000
+#define mmDCORE0_XBAR_DMA_PLL_DIV_1_RLX_BASE 0x4D41800ull
+#define DCORE0_XBAR_DMA_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE0_XBAR_DMA_PLL_DIV_1_RLX_SECTION 0x2000
+#define mmDCORE0_XBAR_DMA_PLL_DIV_2_RLX_BASE 0x4D41A00ull
+#define DCORE0_XBAR_DMA_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE0_XBAR_DMA_PLL_DIV_2_RLX_SECTION 0x2000
+#define mmDCORE0_XBAR_DMA_PLL_DIV_3_RLX_BASE 0x4D41C00ull
+#define DCORE0_XBAR_DMA_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE0_XBAR_DMA_PLL_DIV_3_RLX_SECTION 0x2800
+#define mmDCORE0_XBAR_DMA_PLL_SPECIAL_BASE 0x4D41E80ull
+#define DCORE0_XBAR_DMA_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_XBAR_DMA_PLL_SPECIAL_SECTION 0x1800
+#define mmDCORE0_XBAR_MMU_PLL_CTRL_BASE 0x4D42000ull
+#define DCORE0_XBAR_MMU_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE0_XBAR_MMU_PLL_CTRL_SECTION 0x3600
+#define mmDCORE0_XBAR_MMU_PLL_ASIF_SLV_BASE 0x4D42360ull
+#define DCORE0_XBAR_MMU_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE0_XBAR_MMU_PLL_ASIF_SLV_SECTION 0xA000
+#define mmDCORE0_XBAR_MMU_PLL_DIV_0_RLX_BASE 0x4D42400ull
+#define DCORE0_XBAR_MMU_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE0_XBAR_MMU_PLL_DIV_0_RLX_SECTION 0x4000
+#define mmDCORE0_XBAR_MMU_PLL_DIV_1_RLX_BASE 0x4D42800ull
+#define DCORE0_XBAR_MMU_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE0_XBAR_MMU_PLL_DIV_1_RLX_SECTION 0x2000
+#define mmDCORE0_XBAR_MMU_PLL_DIV_2_RLX_BASE 0x4D42A00ull
+#define DCORE0_XBAR_MMU_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE0_XBAR_MMU_PLL_DIV_2_RLX_SECTION 0x2000
+#define mmDCORE0_XBAR_MMU_PLL_DIV_3_RLX_BASE 0x4D42C00ull
+#define DCORE0_XBAR_MMU_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE0_XBAR_MMU_PLL_DIV_3_RLX_SECTION 0x2800
+#define mmDCORE0_XBAR_MMU_PLL_SPECIAL_BASE 0x4D42E80ull
+#define DCORE0_XBAR_MMU_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_XBAR_MMU_PLL_SPECIAL_SECTION 0x1800
+#define mmDCORE0_XBAR_IF_PLL_CTRL_BASE 0x4D43000ull
+#define DCORE0_XBAR_IF_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE0_XBAR_IF_PLL_CTRL_SECTION 0x3600
+#define mmDCORE0_XBAR_IF_PLL_ASIF_SLV_BASE 0x4D43360ull
+#define DCORE0_XBAR_IF_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE0_XBAR_IF_PLL_ASIF_SLV_SECTION 0xA000
+#define mmDCORE0_XBAR_IF_PLL_DIV_0_RLX_BASE 0x4D43400ull
+#define DCORE0_XBAR_IF_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE0_XBAR_IF_PLL_DIV_0_RLX_SECTION 0x4000
+#define mmDCORE0_XBAR_IF_PLL_DIV_1_RLX_BASE 0x4D43800ull
+#define DCORE0_XBAR_IF_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE0_XBAR_IF_PLL_DIV_1_RLX_SECTION 0x2000
+#define mmDCORE0_XBAR_IF_PLL_DIV_2_RLX_BASE 0x4D43A00ull
+#define DCORE0_XBAR_IF_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE0_XBAR_IF_PLL_DIV_2_RLX_SECTION 0x2000
+#define mmDCORE0_XBAR_IF_PLL_DIV_3_RLX_BASE 0x4D43C00ull
+#define DCORE0_XBAR_IF_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE0_XBAR_IF_PLL_DIV_3_RLX_SECTION 0x2800
+#define mmDCORE0_XBAR_IF_PLL_SPECIAL_BASE 0x4D43E80ull
+#define DCORE0_XBAR_IF_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_XBAR_IF_PLL_SPECIAL_SECTION 0x1800
+#define mmDCORE0_XBAR_MESH_PLL_CTRL_BASE 0x4D44000ull
+#define DCORE0_XBAR_MESH_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE0_XBAR_MESH_PLL_CTRL_SECTION 0x3600
+#define mmDCORE0_XBAR_MESH_PLL_ASIF_SLV_BASE 0x4D44360ull
+#define DCORE0_XBAR_MESH_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE0_XBAR_MESH_PLL_ASIF_SLV_SECTION 0xA000
+#define mmDCORE0_XBAR_MESH_PLL_DIV_0_RLX_BASE 0x4D44400ull
+#define DCORE0_XBAR_MESH_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE0_XBAR_MESH_PLL_DIV_0_RLX_SECTION 0x4000
+#define mmDCORE0_XBAR_MESH_PLL_DIV_1_RLX_BASE 0x4D44800ull
+#define DCORE0_XBAR_MESH_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE0_XBAR_MESH_PLL_DIV_1_RLX_SECTION 0x2000
+#define mmDCORE0_XBAR_MESH_PLL_DIV_2_RLX_BASE 0x4D44A00ull
+#define DCORE0_XBAR_MESH_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE0_XBAR_MESH_PLL_DIV_2_RLX_SECTION 0x2000
+#define mmDCORE0_XBAR_MESH_PLL_DIV_3_RLX_BASE 0x4D44C00ull
+#define DCORE0_XBAR_MESH_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE0_XBAR_MESH_PLL_DIV_3_RLX_SECTION 0x2800
+#define mmDCORE0_XBAR_MESH_PLL_SPECIAL_BASE 0x4D44E80ull
+#define DCORE0_XBAR_MESH_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_XBAR_MESH_PLL_SPECIAL_SECTION 0x3180
+#define mmXBAR_EDGE_0_BASE 0x4D48000ull
+#define XBAR_EDGE_0_MAX_OFFSET 0x1000
+#define XBAR_EDGE_0_SECTION 0xE800
+#define mmXBAR_EDGE_0_SPECIAL_BASE 0x4D48E80ull
+#define XBAR_EDGE_0_SPECIAL_MAX_OFFSET 0x1800
+#define XBAR_EDGE_0_SPECIAL_SECTION 0x7180
+#define mmXBAR_MID_1_BASE 0x4D50000ull
+#define XBAR_MID_1_MAX_OFFSET 0x1000
+#define XBAR_MID_1_SECTION 0xE800
+#define mmXBAR_MID_1_SPECIAL_BASE 0x4D50E80ull
+#define XBAR_MID_1_SPECIAL_MAX_OFFSET 0x1800
+#define XBAR_MID_1_SPECIAL_SECTION 0x1800
+#define mmDCORE1_XBAR_DMA_PLL_CTRL_BASE 0x4D51000ull
+#define DCORE1_XBAR_DMA_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE1_XBAR_DMA_PLL_CTRL_SECTION 0x3600
+#define mmDCORE1_XBAR_DMA_PLL_ASIF_SLV_BASE 0x4D51360ull
+#define DCORE1_XBAR_DMA_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE1_XBAR_DMA_PLL_ASIF_SLV_SECTION 0xA000
+#define mmDCORE1_XBAR_DMA_PLL_DIV_0_RLX_BASE 0x4D51400ull
+#define DCORE1_XBAR_DMA_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE1_XBAR_DMA_PLL_DIV_0_RLX_SECTION 0x4000
+#define mmDCORE1_XBAR_DMA_PLL_DIV_1_RLX_BASE 0x4D51800ull
+#define DCORE1_XBAR_DMA_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE1_XBAR_DMA_PLL_DIV_1_RLX_SECTION 0x2000
+#define mmDCORE1_XBAR_DMA_PLL_DIV_2_RLX_BASE 0x4D51A00ull
+#define DCORE1_XBAR_DMA_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE1_XBAR_DMA_PLL_DIV_2_RLX_SECTION 0x2000
+#define mmDCORE1_XBAR_DMA_PLL_DIV_3_RLX_BASE 0x4D51C00ull
+#define DCORE1_XBAR_DMA_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE1_XBAR_DMA_PLL_DIV_3_RLX_SECTION 0x2800
+#define mmDCORE1_XBAR_DMA_PLL_SPECIAL_BASE 0x4D51E80ull
+#define DCORE1_XBAR_DMA_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_XBAR_DMA_PLL_SPECIAL_SECTION 0x1800
+#define mmDCORE1_XBAR_MMU_PLL_CTRL_BASE 0x4D52000ull
+#define DCORE1_XBAR_MMU_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE1_XBAR_MMU_PLL_CTRL_SECTION 0x3600
+#define mmDCORE1_XBAR_MMU_PLL_ASIF_SLV_BASE 0x4D52360ull
+#define DCORE1_XBAR_MMU_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE1_XBAR_MMU_PLL_ASIF_SLV_SECTION 0xA000
+#define mmDCORE1_XBAR_MMU_PLL_DIV_0_RLX_BASE 0x4D52400ull
+#define DCORE1_XBAR_MMU_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE1_XBAR_MMU_PLL_DIV_0_RLX_SECTION 0x4000
+#define mmDCORE1_XBAR_MMU_PLL_DIV_1_RLX_BASE 0x4D52800ull
+#define DCORE1_XBAR_MMU_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE1_XBAR_MMU_PLL_DIV_1_RLX_SECTION 0x2000
+#define mmDCORE1_XBAR_MMU_PLL_DIV_2_RLX_BASE 0x4D52A00ull
+#define DCORE1_XBAR_MMU_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE1_XBAR_MMU_PLL_DIV_2_RLX_SECTION 0x2000
+#define mmDCORE1_XBAR_MMU_PLL_DIV_3_RLX_BASE 0x4D52C00ull
+#define DCORE1_XBAR_MMU_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE1_XBAR_MMU_PLL_DIV_3_RLX_SECTION 0x2800
+#define mmDCORE1_XBAR_MMU_PLL_SPECIAL_BASE 0x4D52E80ull
+#define DCORE1_XBAR_MMU_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_XBAR_MMU_PLL_SPECIAL_SECTION 0x1800
+#define mmDCORE1_XBAR_IF_PLL_CTRL_BASE 0x4D53000ull
+#define DCORE1_XBAR_IF_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE1_XBAR_IF_PLL_CTRL_SECTION 0x3600
+#define mmDCORE1_XBAR_IF_PLL_ASIF_SLV_BASE 0x4D53360ull
+#define DCORE1_XBAR_IF_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE1_XBAR_IF_PLL_ASIF_SLV_SECTION 0xA000
+#define mmDCORE1_XBAR_IF_PLL_DIV_0_RLX_BASE 0x4D53400ull
+#define DCORE1_XBAR_IF_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE1_XBAR_IF_PLL_DIV_0_RLX_SECTION 0x4000
+#define mmDCORE1_XBAR_IF_PLL_DIV_1_RLX_BASE 0x4D53800ull
+#define DCORE1_XBAR_IF_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE1_XBAR_IF_PLL_DIV_1_RLX_SECTION 0x2000
+#define mmDCORE1_XBAR_IF_PLL_DIV_2_RLX_BASE 0x4D53A00ull
+#define DCORE1_XBAR_IF_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE1_XBAR_IF_PLL_DIV_2_RLX_SECTION 0x2000
+#define mmDCORE1_XBAR_IF_PLL_DIV_3_RLX_BASE 0x4D53C00ull
+#define DCORE1_XBAR_IF_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE1_XBAR_IF_PLL_DIV_3_RLX_SECTION 0x2800
+#define mmDCORE1_XBAR_IF_PLL_SPECIAL_BASE 0x4D53E80ull
+#define DCORE1_XBAR_IF_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_XBAR_IF_PLL_SPECIAL_SECTION 0x1800
+#define mmDCORE1_XBAR_MESH_PLL_CTRL_BASE 0x4D54000ull
+#define DCORE1_XBAR_MESH_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE1_XBAR_MESH_PLL_CTRL_SECTION 0x3600
+#define mmDCORE1_XBAR_MESH_PLL_ASIF_SLV_BASE 0x4D54360ull
+#define DCORE1_XBAR_MESH_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE1_XBAR_MESH_PLL_ASIF_SLV_SECTION 0xA000
+#define mmDCORE1_XBAR_MESH_PLL_DIV_0_RLX_BASE 0x4D54400ull
+#define DCORE1_XBAR_MESH_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE1_XBAR_MESH_PLL_DIV_0_RLX_SECTION 0x4000
+#define mmDCORE1_XBAR_MESH_PLL_DIV_1_RLX_BASE 0x4D54800ull
+#define DCORE1_XBAR_MESH_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE1_XBAR_MESH_PLL_DIV_1_RLX_SECTION 0x2000
+#define mmDCORE1_XBAR_MESH_PLL_DIV_2_RLX_BASE 0x4D54A00ull
+#define DCORE1_XBAR_MESH_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE1_XBAR_MESH_PLL_DIV_2_RLX_SECTION 0x2000
+#define mmDCORE1_XBAR_MESH_PLL_DIV_3_RLX_BASE 0x4D54C00ull
+#define DCORE1_XBAR_MESH_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE1_XBAR_MESH_PLL_DIV_3_RLX_SECTION 0x2800
+#define mmDCORE1_XBAR_MESH_PLL_SPECIAL_BASE 0x4D54E80ull
+#define DCORE1_XBAR_MESH_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_XBAR_MESH_PLL_SPECIAL_SECTION 0x1800
+#define mmDCORE1_XBAR_HBM_PLL_CTRL_BASE 0x4D55000ull
+#define DCORE1_XBAR_HBM_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE1_XBAR_HBM_PLL_CTRL_SECTION 0x3600
+#define mmDCORE1_XBAR_HBM_PLL_ASIF_SLV_BASE 0x4D55360ull
+#define DCORE1_XBAR_HBM_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE1_XBAR_HBM_PLL_ASIF_SLV_SECTION 0xA000
+#define mmDCORE1_XBAR_HBM_PLL_DIV_0_RLX_BASE 0x4D55400ull
+#define DCORE1_XBAR_HBM_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE1_XBAR_HBM_PLL_DIV_0_RLX_SECTION 0x4000
+#define mmDCORE1_XBAR_HBM_PLL_DIV_1_RLX_BASE 0x4D55800ull
+#define DCORE1_XBAR_HBM_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE1_XBAR_HBM_PLL_DIV_1_RLX_SECTION 0x2000
+#define mmDCORE1_XBAR_HBM_PLL_DIV_2_RLX_BASE 0x4D55A00ull
+#define DCORE1_XBAR_HBM_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE1_XBAR_HBM_PLL_DIV_2_RLX_SECTION 0x2000
+#define mmDCORE1_XBAR_HBM_PLL_DIV_3_RLX_BASE 0x4D55C00ull
+#define DCORE1_XBAR_HBM_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE1_XBAR_HBM_PLL_DIV_3_RLX_SECTION 0x2800
+#define mmDCORE1_XBAR_HBM_PLL_SPECIAL_BASE 0x4D55E80ull
+#define DCORE1_XBAR_HBM_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_XBAR_HBM_PLL_SPECIAL_SECTION 0x2180
+#define mmXBAR_EDGE_1_BASE 0x4D58000ull
+#define XBAR_EDGE_1_MAX_OFFSET 0x1000
+#define XBAR_EDGE_1_SECTION 0xE800
+#define mmXBAR_EDGE_1_SPECIAL_BASE 0x4D58E80ull
+#define XBAR_EDGE_1_SPECIAL_MAX_OFFSET 0x1800
+#define XBAR_EDGE_1_SPECIAL_SECTION 0x7180
+#define mmXBAR_MID_2_BASE 0x4D60000ull
+#define XBAR_MID_2_MAX_OFFSET 0x1000
+#define XBAR_MID_2_SECTION 0xE800
+#define mmXBAR_MID_2_SPECIAL_BASE 0x4D60E80ull
+#define XBAR_MID_2_SPECIAL_MAX_OFFSET 0x1800
+#define XBAR_MID_2_SPECIAL_SECTION 0x1800
+#define mmDCORE2_XBAR_DMA_PLL_CTRL_BASE 0x4D61000ull
+#define DCORE2_XBAR_DMA_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE2_XBAR_DMA_PLL_CTRL_SECTION 0x3600
+#define mmDCORE2_XBAR_DMA_PLL_ASIF_SLV_BASE 0x4D61360ull
+#define DCORE2_XBAR_DMA_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE2_XBAR_DMA_PLL_ASIF_SLV_SECTION 0xA000
+#define mmDCORE2_XBAR_DMA_PLL_DIV_0_RLX_BASE 0x4D61400ull
+#define DCORE2_XBAR_DMA_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE2_XBAR_DMA_PLL_DIV_0_RLX_SECTION 0x4000
+#define mmDCORE2_XBAR_DMA_PLL_DIV_1_RLX_BASE 0x4D61800ull
+#define DCORE2_XBAR_DMA_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE2_XBAR_DMA_PLL_DIV_1_RLX_SECTION 0x2000
+#define mmDCORE2_XBAR_DMA_PLL_DIV_2_RLX_BASE 0x4D61A00ull
+#define DCORE2_XBAR_DMA_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE2_XBAR_DMA_PLL_DIV_2_RLX_SECTION 0x2000
+#define mmDCORE2_XBAR_DMA_PLL_DIV_3_RLX_BASE 0x4D61C00ull
+#define DCORE2_XBAR_DMA_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE2_XBAR_DMA_PLL_DIV_3_RLX_SECTION 0x2800
+#define mmDCORE2_XBAR_DMA_PLL_SPECIAL_BASE 0x4D61E80ull
+#define DCORE2_XBAR_DMA_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_XBAR_DMA_PLL_SPECIAL_SECTION 0x1800
+#define mmDCORE2_XBAR_MMU_PLL_CTRL_BASE 0x4D62000ull
+#define DCORE2_XBAR_MMU_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE2_XBAR_MMU_PLL_CTRL_SECTION 0x3600
+#define mmDCORE2_XBAR_MMU_PLL_ASIF_SLV_BASE 0x4D62360ull
+#define DCORE2_XBAR_MMU_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE2_XBAR_MMU_PLL_ASIF_SLV_SECTION 0xA000
+#define mmDCORE2_XBAR_MMU_PLL_DIV_0_RLX_BASE 0x4D62400ull
+#define DCORE2_XBAR_MMU_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE2_XBAR_MMU_PLL_DIV_0_RLX_SECTION 0x4000
+#define mmDCORE2_XBAR_MMU_PLL_DIV_1_RLX_BASE 0x4D62800ull
+#define DCORE2_XBAR_MMU_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE2_XBAR_MMU_PLL_DIV_1_RLX_SECTION 0x2000
+#define mmDCORE2_XBAR_MMU_PLL_DIV_2_RLX_BASE 0x4D62A00ull
+#define DCORE2_XBAR_MMU_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE2_XBAR_MMU_PLL_DIV_2_RLX_SECTION 0x2000
+#define mmDCORE2_XBAR_MMU_PLL_DIV_3_RLX_BASE 0x4D62C00ull
+#define DCORE2_XBAR_MMU_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE2_XBAR_MMU_PLL_DIV_3_RLX_SECTION 0x2800
+#define mmDCORE2_XBAR_MMU_PLL_SPECIAL_BASE 0x4D62E80ull
+#define DCORE2_XBAR_MMU_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_XBAR_MMU_PLL_SPECIAL_SECTION 0x1800
+#define mmDCORE2_XBAR_IF_PLL_CTRL_BASE 0x4D63000ull
+#define DCORE2_XBAR_IF_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE2_XBAR_IF_PLL_CTRL_SECTION 0x3600
+#define mmDCORE2_XBAR_IF_PLL_ASIF_SLV_BASE 0x4D63360ull
+#define DCORE2_XBAR_IF_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE2_XBAR_IF_PLL_ASIF_SLV_SECTION 0xA000
+#define mmDCORE2_XBAR_IF_PLL_DIV_0_RLX_BASE 0x4D63400ull
+#define DCORE2_XBAR_IF_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE2_XBAR_IF_PLL_DIV_0_RLX_SECTION 0x4000
+#define mmDCORE2_XBAR_IF_PLL_DIV_1_RLX_BASE 0x4D63800ull
+#define DCORE2_XBAR_IF_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE2_XBAR_IF_PLL_DIV_1_RLX_SECTION 0x2000
+#define mmDCORE2_XBAR_IF_PLL_DIV_2_RLX_BASE 0x4D63A00ull
+#define DCORE2_XBAR_IF_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE2_XBAR_IF_PLL_DIV_2_RLX_SECTION 0x2000
+#define mmDCORE2_XBAR_IF_PLL_DIV_3_RLX_BASE 0x4D63C00ull
+#define DCORE2_XBAR_IF_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE2_XBAR_IF_PLL_DIV_3_RLX_SECTION 0x2800
+#define mmDCORE2_XBAR_IF_PLL_SPECIAL_BASE 0x4D63E80ull
+#define DCORE2_XBAR_IF_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_XBAR_IF_PLL_SPECIAL_SECTION 0x1800
+#define mmDCORE2_XBAR_BANK_PLL_CTRL_BASE 0x4D64000ull
+#define DCORE2_XBAR_BANK_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE2_XBAR_BANK_PLL_CTRL_SECTION 0x3600
+#define mmDCORE2_XBAR_BANK_PLL_ASIF_SLV_BASE 0x4D64360ull
+#define DCORE2_XBAR_BANK_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE2_XBAR_BANK_PLL_ASIF_SLV_SECTION 0xA000
+#define mmDCORE2_XBAR_BANK_PLL_DIV_0_RLX_BASE 0x4D64400ull
+#define DCORE2_XBAR_BANK_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE2_XBAR_BANK_PLL_DIV_0_RLX_SECTION 0x4000
+#define mmDCORE2_XBAR_BANK_PLL_DIV_1_RLX_BASE 0x4D64800ull
+#define DCORE2_XBAR_BANK_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE2_XBAR_BANK_PLL_DIV_1_RLX_SECTION 0x2000
+#define mmDCORE2_XBAR_BANK_PLL_DIV_2_RLX_BASE 0x4D64A00ull
+#define DCORE2_XBAR_BANK_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE2_XBAR_BANK_PLL_DIV_2_RLX_SECTION 0x2000
+#define mmDCORE2_XBAR_BANK_PLL_DIV_3_RLX_BASE 0x4D64C00ull
+#define DCORE2_XBAR_BANK_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE2_XBAR_BANK_PLL_DIV_3_RLX_SECTION 0x2800
+#define mmDCORE2_XBAR_BANK_PLL_SPECIAL_BASE 0x4D64E80ull
+#define DCORE2_XBAR_BANK_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_XBAR_BANK_PLL_SPECIAL_SECTION 0x1800
+#define mmDCORE2_XBAR_HBM_PLL_CTRL_BASE 0x4D65000ull
+#define DCORE2_XBAR_HBM_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE2_XBAR_HBM_PLL_CTRL_SECTION 0x3600
+#define mmDCORE2_XBAR_HBM_PLL_ASIF_SLV_BASE 0x4D65360ull
+#define DCORE2_XBAR_HBM_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE2_XBAR_HBM_PLL_ASIF_SLV_SECTION 0xA000
+#define mmDCORE2_XBAR_HBM_PLL_DIV_0_RLX_BASE 0x4D65400ull
+#define DCORE2_XBAR_HBM_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE2_XBAR_HBM_PLL_DIV_0_RLX_SECTION 0x4000
+#define mmDCORE2_XBAR_HBM_PLL_DIV_1_RLX_BASE 0x4D65800ull
+#define DCORE2_XBAR_HBM_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE2_XBAR_HBM_PLL_DIV_1_RLX_SECTION 0x2000
+#define mmDCORE2_XBAR_HBM_PLL_DIV_2_RLX_BASE 0x4D65A00ull
+#define DCORE2_XBAR_HBM_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE2_XBAR_HBM_PLL_DIV_2_RLX_SECTION 0x2000
+#define mmDCORE2_XBAR_HBM_PLL_DIV_3_RLX_BASE 0x4D65C00ull
+#define DCORE2_XBAR_HBM_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE2_XBAR_HBM_PLL_DIV_3_RLX_SECTION 0x2800
+#define mmDCORE2_XBAR_HBM_PLL_SPECIAL_BASE 0x4D65E80ull
+#define DCORE2_XBAR_HBM_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_XBAR_HBM_PLL_SPECIAL_SECTION 0x2180
+#define mmXBAR_EDGE_2_BASE 0x4D68000ull
+#define XBAR_EDGE_2_MAX_OFFSET 0x1000
+#define XBAR_EDGE_2_SECTION 0xE800
+#define mmXBAR_EDGE_2_SPECIAL_BASE 0x4D68E80ull
+#define XBAR_EDGE_2_SPECIAL_MAX_OFFSET 0x1800
+#define XBAR_EDGE_2_SPECIAL_SECTION 0x7180
+#define mmXBAR_MID_3_BASE 0x4D70000ull
+#define XBAR_MID_3_MAX_OFFSET 0x1000
+#define XBAR_MID_3_SECTION 0xE800
+#define mmXBAR_MID_3_SPECIAL_BASE 0x4D70E80ull
+#define XBAR_MID_3_SPECIAL_MAX_OFFSET 0x1800
+#define XBAR_MID_3_SPECIAL_SECTION 0x1800
+#define mmDCORE3_XBAR_DMA_PLL_CTRL_BASE 0x4D71000ull
+#define DCORE3_XBAR_DMA_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE3_XBAR_DMA_PLL_CTRL_SECTION 0x3600
+#define mmDCORE3_XBAR_DMA_PLL_ASIF_SLV_BASE 0x4D71360ull
+#define DCORE3_XBAR_DMA_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE3_XBAR_DMA_PLL_ASIF_SLV_SECTION 0xA000
+#define mmDCORE3_XBAR_DMA_PLL_DIV_0_RLX_BASE 0x4D71400ull
+#define DCORE3_XBAR_DMA_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE3_XBAR_DMA_PLL_DIV_0_RLX_SECTION 0x4000
+#define mmDCORE3_XBAR_DMA_PLL_DIV_1_RLX_BASE 0x4D71800ull
+#define DCORE3_XBAR_DMA_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE3_XBAR_DMA_PLL_DIV_1_RLX_SECTION 0x2000
+#define mmDCORE3_XBAR_DMA_PLL_DIV_2_RLX_BASE 0x4D71A00ull
+#define DCORE3_XBAR_DMA_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE3_XBAR_DMA_PLL_DIV_2_RLX_SECTION 0x2000
+#define mmDCORE3_XBAR_DMA_PLL_DIV_3_RLX_BASE 0x4D71C00ull
+#define DCORE3_XBAR_DMA_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE3_XBAR_DMA_PLL_DIV_3_RLX_SECTION 0x2800
+#define mmDCORE3_XBAR_DMA_PLL_SPECIAL_BASE 0x4D71E80ull
+#define DCORE3_XBAR_DMA_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_XBAR_DMA_PLL_SPECIAL_SECTION 0x1800
+#define mmDCORE3_XBAR_MMU_PLL_CTRL_BASE 0x4D72000ull
+#define DCORE3_XBAR_MMU_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE3_XBAR_MMU_PLL_CTRL_SECTION 0x3600
+#define mmDCORE3_XBAR_MMU_PLL_ASIF_SLV_BASE 0x4D72360ull
+#define DCORE3_XBAR_MMU_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE3_XBAR_MMU_PLL_ASIF_SLV_SECTION 0xA000
+#define mmDCORE3_XBAR_MMU_PLL_DIV_0_RLX_BASE 0x4D72400ull
+#define DCORE3_XBAR_MMU_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE3_XBAR_MMU_PLL_DIV_0_RLX_SECTION 0x4000
+#define mmDCORE3_XBAR_MMU_PLL_DIV_1_RLX_BASE 0x4D72800ull
+#define DCORE3_XBAR_MMU_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE3_XBAR_MMU_PLL_DIV_1_RLX_SECTION 0x2000
+#define mmDCORE3_XBAR_MMU_PLL_DIV_2_RLX_BASE 0x4D72A00ull
+#define DCORE3_XBAR_MMU_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE3_XBAR_MMU_PLL_DIV_2_RLX_SECTION 0x2000
+#define mmDCORE3_XBAR_MMU_PLL_DIV_3_RLX_BASE 0x4D72C00ull
+#define DCORE3_XBAR_MMU_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE3_XBAR_MMU_PLL_DIV_3_RLX_SECTION 0x2800
+#define mmDCORE3_XBAR_MMU_PLL_SPECIAL_BASE 0x4D72E80ull
+#define DCORE3_XBAR_MMU_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_XBAR_MMU_PLL_SPECIAL_SECTION 0x1800
+#define mmDCORE3_XBAR_IF_PLL_CTRL_BASE 0x4D73000ull
+#define DCORE3_XBAR_IF_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE3_XBAR_IF_PLL_CTRL_SECTION 0x3600
+#define mmDCORE3_XBAR_IF_PLL_ASIF_SLV_BASE 0x4D73360ull
+#define DCORE3_XBAR_IF_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE3_XBAR_IF_PLL_ASIF_SLV_SECTION 0xA000
+#define mmDCORE3_XBAR_IF_PLL_DIV_0_RLX_BASE 0x4D73400ull
+#define DCORE3_XBAR_IF_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE3_XBAR_IF_PLL_DIV_0_RLX_SECTION 0x4000
+#define mmDCORE3_XBAR_IF_PLL_DIV_1_RLX_BASE 0x4D73800ull
+#define DCORE3_XBAR_IF_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE3_XBAR_IF_PLL_DIV_1_RLX_SECTION 0x2000
+#define mmDCORE3_XBAR_IF_PLL_DIV_2_RLX_BASE 0x4D73A00ull
+#define DCORE3_XBAR_IF_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE3_XBAR_IF_PLL_DIV_2_RLX_SECTION 0x2000
+#define mmDCORE3_XBAR_IF_PLL_DIV_3_RLX_BASE 0x4D73C00ull
+#define DCORE3_XBAR_IF_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE3_XBAR_IF_PLL_DIV_3_RLX_SECTION 0x2800
+#define mmDCORE3_XBAR_IF_PLL_SPECIAL_BASE 0x4D73E80ull
+#define DCORE3_XBAR_IF_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_XBAR_IF_PLL_SPECIAL_SECTION 0x1800
+#define mmDCORE3_XBAR_BANK_PLL_CTRL_BASE 0x4D74000ull
+#define DCORE3_XBAR_BANK_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE3_XBAR_BANK_PLL_CTRL_SECTION 0x3600
+#define mmDCORE3_XBAR_BANK_PLL_ASIF_SLV_BASE 0x4D74360ull
+#define DCORE3_XBAR_BANK_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE3_XBAR_BANK_PLL_ASIF_SLV_SECTION 0xA000
+#define mmDCORE3_XBAR_BANK_PLL_DIV_0_RLX_BASE 0x4D74400ull
+#define DCORE3_XBAR_BANK_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE3_XBAR_BANK_PLL_DIV_0_RLX_SECTION 0x4000
+#define mmDCORE3_XBAR_BANK_PLL_DIV_1_RLX_BASE 0x4D74800ull
+#define DCORE3_XBAR_BANK_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE3_XBAR_BANK_PLL_DIV_1_RLX_SECTION 0x2000
+#define mmDCORE3_XBAR_BANK_PLL_DIV_2_RLX_BASE 0x4D74A00ull
+#define DCORE3_XBAR_BANK_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE3_XBAR_BANK_PLL_DIV_2_RLX_SECTION 0x2000
+#define mmDCORE3_XBAR_BANK_PLL_DIV_3_RLX_BASE 0x4D74C00ull
+#define DCORE3_XBAR_BANK_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE3_XBAR_BANK_PLL_DIV_3_RLX_SECTION 0x2800
+#define mmDCORE3_XBAR_BANK_PLL_SPECIAL_BASE 0x4D74E80ull
+#define DCORE3_XBAR_BANK_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_XBAR_BANK_PLL_SPECIAL_SECTION 0x3180
+#define mmXBAR_EDGE_3_BASE 0x4D78000ull
+#define XBAR_EDGE_3_MAX_OFFSET 0x1000
+#define XBAR_EDGE_3_SECTION 0xE800
+#define mmXBAR_EDGE_3_SPECIAL_BASE 0x4D78E80ull
+#define XBAR_EDGE_3_SPECIAL_MAX_OFFSET 0x1800
+#define XBAR_EDGE_3_SPECIAL_SECTION 0x7180
+#define mmPCIE_PMA_0_BASE 0x4D80000ull
+#define PCIE_PMA_0_MAX_OFFSET 0x40000
+#define PCIE_PMA_0_SECTION 0x40000
+#define mmPCIE_PMA_1_BASE 0x4DC0000ull
+#define PCIE_PMA_1_MAX_OFFSET 0x40000
+#define PCIE_PMA_1_SECTION 0x40000
+#define mmROT0_QM_ARC_DCCM_BASE 0x4E00000ull
+#define ROT0_QM_ARC_DCCM_MAX_OFFSET 0x4000
+#define ROT0_QM_ARC_DCCM_SECTION 0x8000
+#define mmROT0_QM_ARC_AUX_BASE 0x4E08000ull
+#define ROT0_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define ROT0_QM_ARC_AUX_SECTION 0xE800
+#define mmROT0_QM_ARC_AUX_SPECIAL_BASE 0x4E08E80ull
+#define ROT0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define ROT0_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define mmROT0_QM_BASE 0x4E0A000ull
+#define ROT0_QM_MAX_OFFSET 0x1000
+#define ROT0_QM_SECTION 0x9000
+#define mmROT0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x4E0A900ull
+#define ROT0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmROT0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x4E0A908ull
+#define ROT0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmROT0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x4E0A910ull
+#define ROT0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmROT0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x4E0A918ull
+#define ROT0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmROT0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x4E0A920ull
+#define ROT0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmROT0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x4E0A928ull
+#define ROT0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmROT0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x4E0A930ull
+#define ROT0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmROT0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x4E0A938ull
+#define ROT0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmROT0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x4E0A940ull
+#define ROT0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmROT0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x4E0A948ull
+#define ROT0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmROT0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x4E0A950ull
+#define ROT0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmROT0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x4E0A958ull
+#define ROT0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmROT0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x4E0A960ull
+#define ROT0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmROT0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x4E0A968ull
+#define ROT0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmROT0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x4E0A970ull
+#define ROT0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmROT0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x4E0A978ull
+#define ROT0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define ROT0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmROT0_QM_AXUSER_SECURED_BASE 0x4E0AB00ull
+#define ROT0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define ROT0_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmROT0_QM_AXUSER_NONSECURED_BASE 0x4E0AB80ull
+#define ROT0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define ROT0_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmROT0_QM_DBG_HBW_BASE 0x4E0AC00ull
+#define ROT0_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define ROT0_QM_DBG_HBW_SECTION 0x8000
+#define mmROT0_QM_DBG_LBW_BASE 0x4E0AC80ull
+#define ROT0_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define ROT0_QM_DBG_LBW_SECTION 0x1000
+#define mmROT0_QM_CGM_BASE 0x4E0AD80ull
+#define ROT0_QM_CGM_MAX_OFFSET 0xC000
+#define ROT0_QM_CGM_SECTION 0x1000
+#define mmROT0_QM_SPECIAL_BASE 0x4E0AE80ull
+#define ROT0_QM_SPECIAL_MAX_OFFSET 0x1800
+#define ROT0_QM_SPECIAL_SECTION 0x1800
+#define mmROT0_BASE 0x4E0B000ull
+#define ROT0_MAX_OFFSET 0x1000
+#define ROT0_SECTION 0x1000
+#define mmROT0_DESC_BASE 0x4E0B100ull
+#define ROT0_DESC_MAX_OFFSET 0x1080
+#define ROT0_DESC_SECTION 0xD800
+#define mmROT0_SPECIAL_BASE 0x4E0BE80ull
+#define ROT0_SPECIAL_MAX_OFFSET 0x1800
+#define ROT0_SPECIAL_SECTION 0x1800
+#define mmROT0_MSTR_IF_RR_SHRD_HBW_BASE 0x4E0C000ull
+#define ROT0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define ROT0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmROT0_MSTR_IF_RR_PRVT_HBW_BASE 0x4E0C200ull
+#define ROT0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define ROT0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmROT0_MSTR_IF_RR_SHRD_LBW_BASE 0x4E0C400ull
+#define ROT0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define ROT0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmROT0_MSTR_IF_RR_PRVT_LBW_BASE 0x4E0C600ull
+#define ROT0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define ROT0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmROT0_MSTR_IF_E2E_CRDT_BASE 0x4E0C800ull
+#define ROT0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define ROT0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmROT0_MSTR_IF_AXUSER_BASE 0x4E0CA80ull
+#define ROT0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define ROT0_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmROT0_MSTR_IF_DBG_HBW_BASE 0x4E0CB00ull
+#define ROT0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define ROT0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmROT0_MSTR_IF_DBG_LBW_BASE 0x4E0CB80ull
+#define ROT0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define ROT0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmROT0_MSTR_IF_CORE_HBW_BASE 0x4E0CC00ull
+#define ROT0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define ROT0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmROT0_MSTR_IF_CORE_LBW_BASE 0x4E0CD80ull
+#define ROT0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define ROT0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmROT0_MSTR_IF_SPECIAL_BASE 0x4E0CE80ull
+#define ROT0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define ROT0_MSTR_IF_SPECIAL_SECTION 0x3180
+#define mmROT1_QM_ARC_DCCM_BASE 0x4E10000ull
+#define ROT1_QM_ARC_DCCM_MAX_OFFSET 0x4000
+#define ROT1_QM_ARC_DCCM_SECTION 0x8000
+#define mmROT1_QM_ARC_AUX_BASE 0x4E18000ull
+#define ROT1_QM_ARC_AUX_MAX_OFFSET 0x1000
+#define ROT1_QM_ARC_AUX_SECTION 0xE800
+#define mmROT1_QM_ARC_AUX_SPECIAL_BASE 0x4E18E80ull
+#define ROT1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define ROT1_QM_ARC_AUX_SPECIAL_SECTION 0x1180
+#define mmROT1_QM_BASE 0x4E1A000ull
+#define ROT1_QM_MAX_OFFSET 0x1000
+#define ROT1_QM_SECTION 0x9000
+#define mmROT1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x4E1A900ull
+#define ROT1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmROT1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x4E1A908ull
+#define ROT1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmROT1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x4E1A910ull
+#define ROT1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmROT1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x4E1A918ull
+#define ROT1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmROT1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x4E1A920ull
+#define ROT1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmROT1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x4E1A928ull
+#define ROT1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmROT1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x4E1A930ull
+#define ROT1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmROT1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x4E1A938ull
+#define ROT1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmROT1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x4E1A940ull
+#define ROT1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmROT1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x4E1A948ull
+#define ROT1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmROT1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x4E1A950ull
+#define ROT1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmROT1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x4E1A958ull
+#define ROT1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmROT1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x4E1A960ull
+#define ROT1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmROT1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x4E1A968ull
+#define ROT1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmROT1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x4E1A970ull
+#define ROT1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmROT1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x4E1A978ull
+#define ROT1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define ROT1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmROT1_QM_AXUSER_SECURED_BASE 0x4E1AB00ull
+#define ROT1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define ROT1_QM_AXUSER_SECURED_SECTION 0x8000
+#define mmROT1_QM_AXUSER_NONSECURED_BASE 0x4E1AB80ull
+#define ROT1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define ROT1_QM_AXUSER_NONSECURED_SECTION 0x8000
+#define mmROT1_QM_DBG_HBW_BASE 0x4E1AC00ull
+#define ROT1_QM_DBG_HBW_MAX_OFFSET 0x5800
+#define ROT1_QM_DBG_HBW_SECTION 0x8000
+#define mmROT1_QM_DBG_LBW_BASE 0x4E1AC80ull
+#define ROT1_QM_DBG_LBW_MAX_OFFSET 0x5800
+#define ROT1_QM_DBG_LBW_SECTION 0x1000
+#define mmROT1_QM_CGM_BASE 0x4E1AD80ull
+#define ROT1_QM_CGM_MAX_OFFSET 0xC000
+#define ROT1_QM_CGM_SECTION 0x1000
+#define mmROT1_QM_SPECIAL_BASE 0x4E1AE80ull
+#define ROT1_QM_SPECIAL_MAX_OFFSET 0x1800
+#define ROT1_QM_SPECIAL_SECTION 0x1800
+#define mmROT1_BASE 0x4E1B000ull
+#define ROT1_MAX_OFFSET 0x1000
+#define ROT1_SECTION 0x1000
+#define mmROT1_DESC_BASE 0x4E1B100ull
+#define ROT1_DESC_MAX_OFFSET 0x1080
+#define ROT1_DESC_SECTION 0xD800
+#define mmROT1_SPECIAL_BASE 0x4E1BE80ull
+#define ROT1_SPECIAL_MAX_OFFSET 0x1800
+#define ROT1_SPECIAL_SECTION 0x1800
+#define mmROT1_MSTR_IF_RR_SHRD_HBW_BASE 0x4E1C000ull
+#define ROT1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define ROT1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmROT1_MSTR_IF_RR_PRVT_HBW_BASE 0x4E1C200ull
+#define ROT1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define ROT1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmROT1_MSTR_IF_RR_SHRD_LBW_BASE 0x4E1C400ull
+#define ROT1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define ROT1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmROT1_MSTR_IF_RR_PRVT_LBW_BASE 0x4E1C600ull
+#define ROT1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define ROT1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmROT1_MSTR_IF_E2E_CRDT_BASE 0x4E1C800ull
+#define ROT1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define ROT1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmROT1_MSTR_IF_AXUSER_BASE 0x4E1CA80ull
+#define ROT1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define ROT1_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmROT1_MSTR_IF_DBG_HBW_BASE 0x4E1CB00ull
+#define ROT1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define ROT1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmROT1_MSTR_IF_DBG_LBW_BASE 0x4E1CB80ull
+#define ROT1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define ROT1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmROT1_MSTR_IF_CORE_HBW_BASE 0x4E1CC00ull
+#define ROT1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define ROT1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmROT1_MSTR_IF_CORE_LBW_BASE 0x4E1CD80ull
+#define ROT1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define ROT1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmROT1_MSTR_IF_SPECIAL_BASE 0x4E1CE80ull
+#define ROT1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define ROT1_MSTR_IF_SPECIAL_SECTION 0x23180
+#define mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE 0x4E40000ull
+#define SFT0_HBW_RTR_IF0_RTR_CTRL_MAX_OFFSET 0x1000
+#define SFT0_HBW_RTR_IF0_RTR_CTRL_SECTION 0xE800
+#define mmSFT0_HBW_RTR_IF0_RTR_CTRL_SPECIAL_BASE 0x4E40E80ull
+#define SFT0_HBW_RTR_IF0_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define SFT0_HBW_RTR_IF0_RTR_CTRL_SPECIAL_SECTION 0x1800
+#define mmSFT0_HBW_RTR_IF0_RTR_H3_BASE 0x4E41000ull
+#define SFT0_HBW_RTR_IF0_RTR_H3_MAX_OFFSET 0x1000
+#define SFT0_HBW_RTR_IF0_RTR_H3_SECTION 0xE800
+#define mmSFT0_HBW_RTR_IF0_RTR_H3_SPECIAL_BASE 0x4E41E80ull
+#define SFT0_HBW_RTR_IF0_RTR_H3_SPECIAL_MAX_OFFSET 0x1800
+#define SFT0_HBW_RTR_IF0_RTR_H3_SPECIAL_SECTION 0x1800
+#define mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE 0x4E42000ull
+#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_BASE 0x4E42200ull
+#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_BASE 0x4E42400ull
+#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_BASE 0x4E42600ull
+#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmSFT0_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_BASE 0x4E42800ull
+#define SFT0_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define SFT0_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmSFT0_HBW_RTR_IF0_MSTR_IF_AXUSER_BASE 0x4E42A80ull
+#define SFT0_HBW_RTR_IF0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define SFT0_HBW_RTR_IF0_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmSFT0_HBW_RTR_IF0_MSTR_IF_DBG_HBW_BASE 0x4E42B00ull
+#define SFT0_HBW_RTR_IF0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define SFT0_HBW_RTR_IF0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmSFT0_HBW_RTR_IF0_MSTR_IF_DBG_LBW_BASE 0x4E42B80ull
+#define SFT0_HBW_RTR_IF0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define SFT0_HBW_RTR_IF0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmSFT0_HBW_RTR_IF0_MSTR_IF_CORE_HBW_BASE 0x4E42C00ull
+#define SFT0_HBW_RTR_IF0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define SFT0_HBW_RTR_IF0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmSFT0_HBW_RTR_IF0_MSTR_IF_CORE_LBW_BASE 0x4E42D80ull
+#define SFT0_HBW_RTR_IF0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define SFT0_HBW_RTR_IF0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmSFT0_HBW_RTR_IF0_MSTR_IF_SPECIAL_BASE 0x4E42E80ull
+#define SFT0_HBW_RTR_IF0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define SFT0_HBW_RTR_IF0_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmSFT0_HBW_RTR_IF0_ADDR_DEC_HBW_BASE 0x4E43000ull
+#define SFT0_HBW_RTR_IF0_ADDR_DEC_HBW_MAX_OFFSET 0x4000
+#define SFT0_HBW_RTR_IF0_ADDR_DEC_HBW_SECTION 0x4000
+#define mmSFT0_HBW_RTR_IF0_ADDR_DEC_LBW_BASE 0x4E43400ull
+#define SFT0_HBW_RTR_IF0_ADDR_DEC_LBW_MAX_OFFSET 0xA600
+#define SFT0_HBW_RTR_IF0_ADDR_DEC_LBW_SECTION 0xA800
+#define mmSFT0_HBW_RTR_IF0_ADDR_DEC_SPECIAL_BASE 0x4E43E80ull
+#define SFT0_HBW_RTR_IF0_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define SFT0_HBW_RTR_IF0_ADDR_DEC_SPECIAL_SECTION 0x1800
+#define mmSFT0_HBW_RTR_IF1_RTR_CTRL_BASE 0x4E44000ull
+#define SFT0_HBW_RTR_IF1_RTR_CTRL_MAX_OFFSET 0x1000
+#define SFT0_HBW_RTR_IF1_RTR_CTRL_SECTION 0xE800
+#define mmSFT0_HBW_RTR_IF1_RTR_CTRL_SPECIAL_BASE 0x4E44E80ull
+#define SFT0_HBW_RTR_IF1_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define SFT0_HBW_RTR_IF1_RTR_CTRL_SPECIAL_SECTION 0x1800
+#define mmSFT0_HBW_RTR_IF1_RTR_H3_BASE 0x4E45000ull
+#define SFT0_HBW_RTR_IF1_RTR_H3_MAX_OFFSET 0x1000
+#define SFT0_HBW_RTR_IF1_RTR_H3_SECTION 0xE800
+#define mmSFT0_HBW_RTR_IF1_RTR_H3_SPECIAL_BASE 0x4E45E80ull
+#define SFT0_HBW_RTR_IF1_RTR_H3_SPECIAL_MAX_OFFSET 0x1800
+#define SFT0_HBW_RTR_IF1_RTR_H3_SPECIAL_SECTION 0x1800
+#define mmSFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE 0x4E46000ull
+#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmSFT0_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_BASE 0x4E46200ull
+#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmSFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_BASE 0x4E46400ull
+#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmSFT0_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_BASE 0x4E46600ull
+#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmSFT0_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_BASE 0x4E46800ull
+#define SFT0_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define SFT0_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmSFT0_HBW_RTR_IF1_MSTR_IF_AXUSER_BASE 0x4E46A80ull
+#define SFT0_HBW_RTR_IF1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define SFT0_HBW_RTR_IF1_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmSFT0_HBW_RTR_IF1_MSTR_IF_DBG_HBW_BASE 0x4E46B00ull
+#define SFT0_HBW_RTR_IF1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define SFT0_HBW_RTR_IF1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmSFT0_HBW_RTR_IF1_MSTR_IF_DBG_LBW_BASE 0x4E46B80ull
+#define SFT0_HBW_RTR_IF1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define SFT0_HBW_RTR_IF1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmSFT0_HBW_RTR_IF1_MSTR_IF_CORE_HBW_BASE 0x4E46C00ull
+#define SFT0_HBW_RTR_IF1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define SFT0_HBW_RTR_IF1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmSFT0_HBW_RTR_IF1_MSTR_IF_CORE_LBW_BASE 0x4E46D80ull
+#define SFT0_HBW_RTR_IF1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define SFT0_HBW_RTR_IF1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmSFT0_HBW_RTR_IF1_MSTR_IF_SPECIAL_BASE 0x4E46E80ull
+#define SFT0_HBW_RTR_IF1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define SFT0_HBW_RTR_IF1_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmSFT0_HBW_RTR_IF1_ADDR_DEC_HBW_BASE 0x4E47000ull
+#define SFT0_HBW_RTR_IF1_ADDR_DEC_HBW_MAX_OFFSET 0x4000
+#define SFT0_HBW_RTR_IF1_ADDR_DEC_HBW_SECTION 0x4000
+#define mmSFT0_HBW_RTR_IF1_ADDR_DEC_LBW_BASE 0x4E47400ull
+#define SFT0_HBW_RTR_IF1_ADDR_DEC_LBW_MAX_OFFSET 0xA600
+#define SFT0_HBW_RTR_IF1_ADDR_DEC_LBW_SECTION 0xA800
+#define mmSFT0_HBW_RTR_IF1_ADDR_DEC_SPECIAL_BASE 0x4E47E80ull
+#define SFT0_HBW_RTR_IF1_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define SFT0_HBW_RTR_IF1_ADDR_DEC_SPECIAL_SECTION 0x1800
+#define mmSFT0_LBW_RTR_IF_RTR_CTRL_BASE 0x4E48000ull
+#define SFT0_LBW_RTR_IF_RTR_CTRL_MAX_OFFSET 0x1000
+#define SFT0_LBW_RTR_IF_RTR_CTRL_SECTION 0xE800
+#define mmSFT0_LBW_RTR_IF_RTR_CTRL_SPECIAL_BASE 0x4E48E80ull
+#define SFT0_LBW_RTR_IF_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define SFT0_LBW_RTR_IF_RTR_CTRL_SPECIAL_SECTION 0x1800
+#define mmSFT0_LBW_RTR_IF_RTR_H3_BASE 0x4E49000ull
+#define SFT0_LBW_RTR_IF_RTR_H3_MAX_OFFSET 0x1000
+#define SFT0_LBW_RTR_IF_RTR_H3_SECTION 0xE800
+#define mmSFT0_LBW_RTR_IF_RTR_H3_SPECIAL_BASE 0x4E49E80ull
+#define SFT0_LBW_RTR_IF_RTR_H3_SPECIAL_MAX_OFFSET 0x1800
+#define SFT0_LBW_RTR_IF_RTR_H3_SPECIAL_SECTION 0x1800
+#define mmSFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE 0x4E4A000ull
+#define SFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define SFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmSFT0_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_BASE 0x4E4A200ull
+#define SFT0_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define SFT0_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmSFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_BASE 0x4E4A400ull
+#define SFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define SFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmSFT0_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_BASE 0x4E4A600ull
+#define SFT0_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define SFT0_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmSFT0_LBW_RTR_IF_MSTR_IF_E2E_CRDT_BASE 0x4E4A800ull
+#define SFT0_LBW_RTR_IF_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define SFT0_LBW_RTR_IF_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmSFT0_LBW_RTR_IF_MSTR_IF_AXUSER_BASE 0x4E4AA80ull
+#define SFT0_LBW_RTR_IF_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define SFT0_LBW_RTR_IF_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmSFT0_LBW_RTR_IF_MSTR_IF_DBG_HBW_BASE 0x4E4AB00ull
+#define SFT0_LBW_RTR_IF_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define SFT0_LBW_RTR_IF_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmSFT0_LBW_RTR_IF_MSTR_IF_DBG_LBW_BASE 0x4E4AB80ull
+#define SFT0_LBW_RTR_IF_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define SFT0_LBW_RTR_IF_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmSFT0_LBW_RTR_IF_MSTR_IF_CORE_HBW_BASE 0x4E4AC00ull
+#define SFT0_LBW_RTR_IF_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define SFT0_LBW_RTR_IF_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmSFT0_LBW_RTR_IF_MSTR_IF_CORE_LBW_BASE 0x4E4AD80ull
+#define SFT0_LBW_RTR_IF_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define SFT0_LBW_RTR_IF_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmSFT0_LBW_RTR_IF_MSTR_IF_SPECIAL_BASE 0x4E4AE80ull
+#define SFT0_LBW_RTR_IF_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define SFT0_LBW_RTR_IF_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmSFT0_LBW_RTR_IF_ADDR_DEC_HBW_BASE 0x4E4B000ull
+#define SFT0_LBW_RTR_IF_ADDR_DEC_HBW_MAX_OFFSET 0x4000
+#define SFT0_LBW_RTR_IF_ADDR_DEC_HBW_SECTION 0x4000
+#define mmSFT0_LBW_RTR_IF_ADDR_DEC_LBW_BASE 0x4E4B400ull
+#define SFT0_LBW_RTR_IF_ADDR_DEC_LBW_MAX_OFFSET 0xA600
+#define SFT0_LBW_RTR_IF_ADDR_DEC_LBW_SECTION 0xA800
+#define mmSFT0_LBW_RTR_IF_ADDR_DEC_SPECIAL_BASE 0x4E4BE80ull
+#define SFT0_LBW_RTR_IF_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define SFT0_LBW_RTR_IF_ADDR_DEC_SPECIAL_SECTION 0x1800
+#define mmSFT0_BASE 0x4E4C000ull
+#define SFT0_MAX_OFFSET 0x1000
+#define SFT0_SECTION 0xE800
+#define mmSFT0_SPECIAL_BASE 0x4E4CE80ull
+#define SFT0_SPECIAL_MAX_OFFSET 0x1800
+#define SFT0_SPECIAL_SECTION 0x3180
+#define mmSFT1_HBW_RTR_IF0_RTR_CTRL_BASE 0x4E50000ull
+#define SFT1_HBW_RTR_IF0_RTR_CTRL_MAX_OFFSET 0x1000
+#define SFT1_HBW_RTR_IF0_RTR_CTRL_SECTION 0xE800
+#define mmSFT1_HBW_RTR_IF0_RTR_CTRL_SPECIAL_BASE 0x4E50E80ull
+#define SFT1_HBW_RTR_IF0_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define SFT1_HBW_RTR_IF0_RTR_CTRL_SPECIAL_SECTION 0x1800
+#define mmSFT1_HBW_RTR_IF0_RTR_H3_BASE 0x4E51000ull
+#define SFT1_HBW_RTR_IF0_RTR_H3_MAX_OFFSET 0x1000
+#define SFT1_HBW_RTR_IF0_RTR_H3_SECTION 0xE800
+#define mmSFT1_HBW_RTR_IF0_RTR_H3_SPECIAL_BASE 0x4E51E80ull
+#define SFT1_HBW_RTR_IF0_RTR_H3_SPECIAL_MAX_OFFSET 0x1800
+#define SFT1_HBW_RTR_IF0_RTR_H3_SPECIAL_SECTION 0x1800
+#define mmSFT1_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE 0x4E52000ull
+#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmSFT1_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_BASE 0x4E52200ull
+#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmSFT1_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_BASE 0x4E52400ull
+#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmSFT1_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_BASE 0x4E52600ull
+#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmSFT1_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_BASE 0x4E52800ull
+#define SFT1_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define SFT1_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmSFT1_HBW_RTR_IF0_MSTR_IF_AXUSER_BASE 0x4E52A80ull
+#define SFT1_HBW_RTR_IF0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define SFT1_HBW_RTR_IF0_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmSFT1_HBW_RTR_IF0_MSTR_IF_DBG_HBW_BASE 0x4E52B00ull
+#define SFT1_HBW_RTR_IF0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define SFT1_HBW_RTR_IF0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmSFT1_HBW_RTR_IF0_MSTR_IF_DBG_LBW_BASE 0x4E52B80ull
+#define SFT1_HBW_RTR_IF0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define SFT1_HBW_RTR_IF0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmSFT1_HBW_RTR_IF0_MSTR_IF_CORE_HBW_BASE 0x4E52C00ull
+#define SFT1_HBW_RTR_IF0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define SFT1_HBW_RTR_IF0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmSFT1_HBW_RTR_IF0_MSTR_IF_CORE_LBW_BASE 0x4E52D80ull
+#define SFT1_HBW_RTR_IF0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define SFT1_HBW_RTR_IF0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmSFT1_HBW_RTR_IF0_MSTR_IF_SPECIAL_BASE 0x4E52E80ull
+#define SFT1_HBW_RTR_IF0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define SFT1_HBW_RTR_IF0_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmSFT1_HBW_RTR_IF0_ADDR_DEC_HBW_BASE 0x4E53000ull
+#define SFT1_HBW_RTR_IF0_ADDR_DEC_HBW_MAX_OFFSET 0x4000
+#define SFT1_HBW_RTR_IF0_ADDR_DEC_HBW_SECTION 0x4000
+#define mmSFT1_HBW_RTR_IF0_ADDR_DEC_LBW_BASE 0x4E53400ull
+#define SFT1_HBW_RTR_IF0_ADDR_DEC_LBW_MAX_OFFSET 0xA600
+#define SFT1_HBW_RTR_IF0_ADDR_DEC_LBW_SECTION 0xA800
+#define mmSFT1_HBW_RTR_IF0_ADDR_DEC_SPECIAL_BASE 0x4E53E80ull
+#define SFT1_HBW_RTR_IF0_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define SFT1_HBW_RTR_IF0_ADDR_DEC_SPECIAL_SECTION 0x1800
+#define mmSFT1_HBW_RTR_IF1_RTR_CTRL_BASE 0x4E54000ull
+#define SFT1_HBW_RTR_IF1_RTR_CTRL_MAX_OFFSET 0x1000
+#define SFT1_HBW_RTR_IF1_RTR_CTRL_SECTION 0xE800
+#define mmSFT1_HBW_RTR_IF1_RTR_CTRL_SPECIAL_BASE 0x4E54E80ull
+#define SFT1_HBW_RTR_IF1_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define SFT1_HBW_RTR_IF1_RTR_CTRL_SPECIAL_SECTION 0x1800
+#define mmSFT1_HBW_RTR_IF1_RTR_H3_BASE 0x4E55000ull
+#define SFT1_HBW_RTR_IF1_RTR_H3_MAX_OFFSET 0x1000
+#define SFT1_HBW_RTR_IF1_RTR_H3_SECTION 0xE800
+#define mmSFT1_HBW_RTR_IF1_RTR_H3_SPECIAL_BASE 0x4E55E80ull
+#define SFT1_HBW_RTR_IF1_RTR_H3_SPECIAL_MAX_OFFSET 0x1800
+#define SFT1_HBW_RTR_IF1_RTR_H3_SPECIAL_SECTION 0x1800
+#define mmSFT1_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE 0x4E56000ull
+#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmSFT1_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_BASE 0x4E56200ull
+#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmSFT1_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_BASE 0x4E56400ull
+#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmSFT1_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_BASE 0x4E56600ull
+#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmSFT1_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_BASE 0x4E56800ull
+#define SFT1_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define SFT1_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmSFT1_HBW_RTR_IF1_MSTR_IF_AXUSER_BASE 0x4E56A80ull
+#define SFT1_HBW_RTR_IF1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define SFT1_HBW_RTR_IF1_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmSFT1_HBW_RTR_IF1_MSTR_IF_DBG_HBW_BASE 0x4E56B00ull
+#define SFT1_HBW_RTR_IF1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define SFT1_HBW_RTR_IF1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmSFT1_HBW_RTR_IF1_MSTR_IF_DBG_LBW_BASE 0x4E56B80ull
+#define SFT1_HBW_RTR_IF1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define SFT1_HBW_RTR_IF1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmSFT1_HBW_RTR_IF1_MSTR_IF_CORE_HBW_BASE 0x4E56C00ull
+#define SFT1_HBW_RTR_IF1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define SFT1_HBW_RTR_IF1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmSFT1_HBW_RTR_IF1_MSTR_IF_CORE_LBW_BASE 0x4E56D80ull
+#define SFT1_HBW_RTR_IF1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define SFT1_HBW_RTR_IF1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmSFT1_HBW_RTR_IF1_MSTR_IF_SPECIAL_BASE 0x4E56E80ull
+#define SFT1_HBW_RTR_IF1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define SFT1_HBW_RTR_IF1_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmSFT1_HBW_RTR_IF1_ADDR_DEC_HBW_BASE 0x4E57000ull
+#define SFT1_HBW_RTR_IF1_ADDR_DEC_HBW_MAX_OFFSET 0x4000
+#define SFT1_HBW_RTR_IF1_ADDR_DEC_HBW_SECTION 0x4000
+#define mmSFT1_HBW_RTR_IF1_ADDR_DEC_LBW_BASE 0x4E57400ull
+#define SFT1_HBW_RTR_IF1_ADDR_DEC_LBW_MAX_OFFSET 0xA600
+#define SFT1_HBW_RTR_IF1_ADDR_DEC_LBW_SECTION 0xA800
+#define mmSFT1_HBW_RTR_IF1_ADDR_DEC_SPECIAL_BASE 0x4E57E80ull
+#define SFT1_HBW_RTR_IF1_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define SFT1_HBW_RTR_IF1_ADDR_DEC_SPECIAL_SECTION 0x1800
+#define mmSFT1_LBW_RTR_IF_RTR_CTRL_BASE 0x4E58000ull
+#define SFT1_LBW_RTR_IF_RTR_CTRL_MAX_OFFSET 0x1000
+#define SFT1_LBW_RTR_IF_RTR_CTRL_SECTION 0xE800
+#define mmSFT1_LBW_RTR_IF_RTR_CTRL_SPECIAL_BASE 0x4E58E80ull
+#define SFT1_LBW_RTR_IF_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define SFT1_LBW_RTR_IF_RTR_CTRL_SPECIAL_SECTION 0x1800
+#define mmSFT1_LBW_RTR_IF_RTR_H3_BASE 0x4E59000ull
+#define SFT1_LBW_RTR_IF_RTR_H3_MAX_OFFSET 0x1000
+#define SFT1_LBW_RTR_IF_RTR_H3_SECTION 0xE800
+#define mmSFT1_LBW_RTR_IF_RTR_H3_SPECIAL_BASE 0x4E59E80ull
+#define SFT1_LBW_RTR_IF_RTR_H3_SPECIAL_MAX_OFFSET 0x1800
+#define SFT1_LBW_RTR_IF_RTR_H3_SPECIAL_SECTION 0x1800
+#define mmSFT1_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE 0x4E5A000ull
+#define SFT1_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define SFT1_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmSFT1_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_BASE 0x4E5A200ull
+#define SFT1_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define SFT1_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmSFT1_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_BASE 0x4E5A400ull
+#define SFT1_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define SFT1_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmSFT1_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_BASE 0x4E5A600ull
+#define SFT1_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define SFT1_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmSFT1_LBW_RTR_IF_MSTR_IF_E2E_CRDT_BASE 0x4E5A800ull
+#define SFT1_LBW_RTR_IF_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define SFT1_LBW_RTR_IF_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmSFT1_LBW_RTR_IF_MSTR_IF_AXUSER_BASE 0x4E5AA80ull
+#define SFT1_LBW_RTR_IF_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define SFT1_LBW_RTR_IF_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmSFT1_LBW_RTR_IF_MSTR_IF_DBG_HBW_BASE 0x4E5AB00ull
+#define SFT1_LBW_RTR_IF_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define SFT1_LBW_RTR_IF_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmSFT1_LBW_RTR_IF_MSTR_IF_DBG_LBW_BASE 0x4E5AB80ull
+#define SFT1_LBW_RTR_IF_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define SFT1_LBW_RTR_IF_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmSFT1_LBW_RTR_IF_MSTR_IF_CORE_HBW_BASE 0x4E5AC00ull
+#define SFT1_LBW_RTR_IF_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define SFT1_LBW_RTR_IF_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmSFT1_LBW_RTR_IF_MSTR_IF_CORE_LBW_BASE 0x4E5AD80ull
+#define SFT1_LBW_RTR_IF_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define SFT1_LBW_RTR_IF_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmSFT1_LBW_RTR_IF_MSTR_IF_SPECIAL_BASE 0x4E5AE80ull
+#define SFT1_LBW_RTR_IF_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define SFT1_LBW_RTR_IF_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmSFT1_LBW_RTR_IF_ADDR_DEC_HBW_BASE 0x4E5B000ull
+#define SFT1_LBW_RTR_IF_ADDR_DEC_HBW_MAX_OFFSET 0x4000
+#define SFT1_LBW_RTR_IF_ADDR_DEC_HBW_SECTION 0x4000
+#define mmSFT1_LBW_RTR_IF_ADDR_DEC_LBW_BASE 0x4E5B400ull
+#define SFT1_LBW_RTR_IF_ADDR_DEC_LBW_MAX_OFFSET 0xA600
+#define SFT1_LBW_RTR_IF_ADDR_DEC_LBW_SECTION 0xA800
+#define mmSFT1_LBW_RTR_IF_ADDR_DEC_SPECIAL_BASE 0x4E5BE80ull
+#define SFT1_LBW_RTR_IF_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define SFT1_LBW_RTR_IF_ADDR_DEC_SPECIAL_SECTION 0x1800
+#define mmSFT1_BASE 0x4E5C000ull
+#define SFT1_MAX_OFFSET 0x1000
+#define SFT1_SECTION 0xE800
+#define mmSFT1_SPECIAL_BASE 0x4E5CE80ull
+#define SFT1_SPECIAL_MAX_OFFSET 0x1800
+#define SFT1_SPECIAL_SECTION 0x3180
+#define mmSFT2_HBW_RTR_IF0_RTR_CTRL_BASE 0x4E60000ull
+#define SFT2_HBW_RTR_IF0_RTR_CTRL_MAX_OFFSET 0x1000
+#define SFT2_HBW_RTR_IF0_RTR_CTRL_SECTION 0xE800
+#define mmSFT2_HBW_RTR_IF0_RTR_CTRL_SPECIAL_BASE 0x4E60E80ull
+#define SFT2_HBW_RTR_IF0_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define SFT2_HBW_RTR_IF0_RTR_CTRL_SPECIAL_SECTION 0x1800
+#define mmSFT2_HBW_RTR_IF0_RTR_H3_BASE 0x4E61000ull
+#define SFT2_HBW_RTR_IF0_RTR_H3_MAX_OFFSET 0x1000
+#define SFT2_HBW_RTR_IF0_RTR_H3_SECTION 0xE800
+#define mmSFT2_HBW_RTR_IF0_RTR_H3_SPECIAL_BASE 0x4E61E80ull
+#define SFT2_HBW_RTR_IF0_RTR_H3_SPECIAL_MAX_OFFSET 0x1800
+#define SFT2_HBW_RTR_IF0_RTR_H3_SPECIAL_SECTION 0x1800
+#define mmSFT2_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE 0x4E62000ull
+#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmSFT2_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_BASE 0x4E62200ull
+#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmSFT2_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_BASE 0x4E62400ull
+#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmSFT2_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_BASE 0x4E62600ull
+#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmSFT2_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_BASE 0x4E62800ull
+#define SFT2_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define SFT2_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmSFT2_HBW_RTR_IF0_MSTR_IF_AXUSER_BASE 0x4E62A80ull
+#define SFT2_HBW_RTR_IF0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define SFT2_HBW_RTR_IF0_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmSFT2_HBW_RTR_IF0_MSTR_IF_DBG_HBW_BASE 0x4E62B00ull
+#define SFT2_HBW_RTR_IF0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define SFT2_HBW_RTR_IF0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmSFT2_HBW_RTR_IF0_MSTR_IF_DBG_LBW_BASE 0x4E62B80ull
+#define SFT2_HBW_RTR_IF0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define SFT2_HBW_RTR_IF0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmSFT2_HBW_RTR_IF0_MSTR_IF_CORE_HBW_BASE 0x4E62C00ull
+#define SFT2_HBW_RTR_IF0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define SFT2_HBW_RTR_IF0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmSFT2_HBW_RTR_IF0_MSTR_IF_CORE_LBW_BASE 0x4E62D80ull
+#define SFT2_HBW_RTR_IF0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define SFT2_HBW_RTR_IF0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmSFT2_HBW_RTR_IF0_MSTR_IF_SPECIAL_BASE 0x4E62E80ull
+#define SFT2_HBW_RTR_IF0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define SFT2_HBW_RTR_IF0_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmSFT2_HBW_RTR_IF0_ADDR_DEC_HBW_BASE 0x4E63000ull
+#define SFT2_HBW_RTR_IF0_ADDR_DEC_HBW_MAX_OFFSET 0x4000
+#define SFT2_HBW_RTR_IF0_ADDR_DEC_HBW_SECTION 0x4000
+#define mmSFT2_HBW_RTR_IF0_ADDR_DEC_LBW_BASE 0x4E63400ull
+#define SFT2_HBW_RTR_IF0_ADDR_DEC_LBW_MAX_OFFSET 0xA600
+#define SFT2_HBW_RTR_IF0_ADDR_DEC_LBW_SECTION 0xA800
+#define mmSFT2_HBW_RTR_IF0_ADDR_DEC_SPECIAL_BASE 0x4E63E80ull
+#define SFT2_HBW_RTR_IF0_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define SFT2_HBW_RTR_IF0_ADDR_DEC_SPECIAL_SECTION 0x1800
+#define mmSFT2_HBW_RTR_IF1_RTR_CTRL_BASE 0x4E64000ull
+#define SFT2_HBW_RTR_IF1_RTR_CTRL_MAX_OFFSET 0x1000
+#define SFT2_HBW_RTR_IF1_RTR_CTRL_SECTION 0xE800
+#define mmSFT2_HBW_RTR_IF1_RTR_CTRL_SPECIAL_BASE 0x4E64E80ull
+#define SFT2_HBW_RTR_IF1_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define SFT2_HBW_RTR_IF1_RTR_CTRL_SPECIAL_SECTION 0x1800
+#define mmSFT2_HBW_RTR_IF1_RTR_H3_BASE 0x4E65000ull
+#define SFT2_HBW_RTR_IF1_RTR_H3_MAX_OFFSET 0x1000
+#define SFT2_HBW_RTR_IF1_RTR_H3_SECTION 0xE800
+#define mmSFT2_HBW_RTR_IF1_RTR_H3_SPECIAL_BASE 0x4E65E80ull
+#define SFT2_HBW_RTR_IF1_RTR_H3_SPECIAL_MAX_OFFSET 0x1800
+#define SFT2_HBW_RTR_IF1_RTR_H3_SPECIAL_SECTION 0x1800
+#define mmSFT2_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE 0x4E66000ull
+#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmSFT2_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_BASE 0x4E66200ull
+#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmSFT2_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_BASE 0x4E66400ull
+#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmSFT2_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_BASE 0x4E66600ull
+#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmSFT2_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_BASE 0x4E66800ull
+#define SFT2_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define SFT2_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmSFT2_HBW_RTR_IF1_MSTR_IF_AXUSER_BASE 0x4E66A80ull
+#define SFT2_HBW_RTR_IF1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define SFT2_HBW_RTR_IF1_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmSFT2_HBW_RTR_IF1_MSTR_IF_DBG_HBW_BASE 0x4E66B00ull
+#define SFT2_HBW_RTR_IF1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define SFT2_HBW_RTR_IF1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmSFT2_HBW_RTR_IF1_MSTR_IF_DBG_LBW_BASE 0x4E66B80ull
+#define SFT2_HBW_RTR_IF1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define SFT2_HBW_RTR_IF1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmSFT2_HBW_RTR_IF1_MSTR_IF_CORE_HBW_BASE 0x4E66C00ull
+#define SFT2_HBW_RTR_IF1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define SFT2_HBW_RTR_IF1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmSFT2_HBW_RTR_IF1_MSTR_IF_CORE_LBW_BASE 0x4E66D80ull
+#define SFT2_HBW_RTR_IF1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define SFT2_HBW_RTR_IF1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmSFT2_HBW_RTR_IF1_MSTR_IF_SPECIAL_BASE 0x4E66E80ull
+#define SFT2_HBW_RTR_IF1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define SFT2_HBW_RTR_IF1_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmSFT2_HBW_RTR_IF1_ADDR_DEC_HBW_BASE 0x4E67000ull
+#define SFT2_HBW_RTR_IF1_ADDR_DEC_HBW_MAX_OFFSET 0x4000
+#define SFT2_HBW_RTR_IF1_ADDR_DEC_HBW_SECTION 0x4000
+#define mmSFT2_HBW_RTR_IF1_ADDR_DEC_LBW_BASE 0x4E67400ull
+#define SFT2_HBW_RTR_IF1_ADDR_DEC_LBW_MAX_OFFSET 0xA600
+#define SFT2_HBW_RTR_IF1_ADDR_DEC_LBW_SECTION 0xA800
+#define mmSFT2_HBW_RTR_IF1_ADDR_DEC_SPECIAL_BASE 0x4E67E80ull
+#define SFT2_HBW_RTR_IF1_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define SFT2_HBW_RTR_IF1_ADDR_DEC_SPECIAL_SECTION 0x1800
+#define mmSFT2_LBW_RTR_IF_RTR_CTRL_BASE 0x4E68000ull
+#define SFT2_LBW_RTR_IF_RTR_CTRL_MAX_OFFSET 0x1000
+#define SFT2_LBW_RTR_IF_RTR_CTRL_SECTION 0xE800
+#define mmSFT2_LBW_RTR_IF_RTR_CTRL_SPECIAL_BASE 0x4E68E80ull
+#define SFT2_LBW_RTR_IF_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define SFT2_LBW_RTR_IF_RTR_CTRL_SPECIAL_SECTION 0x1800
+#define mmSFT2_LBW_RTR_IF_RTR_H3_BASE 0x4E69000ull
+#define SFT2_LBW_RTR_IF_RTR_H3_MAX_OFFSET 0x1000
+#define SFT2_LBW_RTR_IF_RTR_H3_SECTION 0xE800
+#define mmSFT2_LBW_RTR_IF_RTR_H3_SPECIAL_BASE 0x4E69E80ull
+#define SFT2_LBW_RTR_IF_RTR_H3_SPECIAL_MAX_OFFSET 0x1800
+#define SFT2_LBW_RTR_IF_RTR_H3_SPECIAL_SECTION 0x1800
+#define mmSFT2_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE 0x4E6A000ull
+#define SFT2_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define SFT2_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmSFT2_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_BASE 0x4E6A200ull
+#define SFT2_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define SFT2_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmSFT2_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_BASE 0x4E6A400ull
+#define SFT2_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define SFT2_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmSFT2_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_BASE 0x4E6A600ull
+#define SFT2_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define SFT2_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmSFT2_LBW_RTR_IF_MSTR_IF_E2E_CRDT_BASE 0x4E6A800ull
+#define SFT2_LBW_RTR_IF_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define SFT2_LBW_RTR_IF_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmSFT2_LBW_RTR_IF_MSTR_IF_AXUSER_BASE 0x4E6AA80ull
+#define SFT2_LBW_RTR_IF_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define SFT2_LBW_RTR_IF_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmSFT2_LBW_RTR_IF_MSTR_IF_DBG_HBW_BASE 0x4E6AB00ull
+#define SFT2_LBW_RTR_IF_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define SFT2_LBW_RTR_IF_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmSFT2_LBW_RTR_IF_MSTR_IF_DBG_LBW_BASE 0x4E6AB80ull
+#define SFT2_LBW_RTR_IF_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define SFT2_LBW_RTR_IF_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmSFT2_LBW_RTR_IF_MSTR_IF_CORE_HBW_BASE 0x4E6AC00ull
+#define SFT2_LBW_RTR_IF_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define SFT2_LBW_RTR_IF_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmSFT2_LBW_RTR_IF_MSTR_IF_CORE_LBW_BASE 0x4E6AD80ull
+#define SFT2_LBW_RTR_IF_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define SFT2_LBW_RTR_IF_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmSFT2_LBW_RTR_IF_MSTR_IF_SPECIAL_BASE 0x4E6AE80ull
+#define SFT2_LBW_RTR_IF_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define SFT2_LBW_RTR_IF_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmSFT2_LBW_RTR_IF_ADDR_DEC_HBW_BASE 0x4E6B000ull
+#define SFT2_LBW_RTR_IF_ADDR_DEC_HBW_MAX_OFFSET 0x4000
+#define SFT2_LBW_RTR_IF_ADDR_DEC_HBW_SECTION 0x4000
+#define mmSFT2_LBW_RTR_IF_ADDR_DEC_LBW_BASE 0x4E6B400ull
+#define SFT2_LBW_RTR_IF_ADDR_DEC_LBW_MAX_OFFSET 0xA600
+#define SFT2_LBW_RTR_IF_ADDR_DEC_LBW_SECTION 0xA800
+#define mmSFT2_LBW_RTR_IF_ADDR_DEC_SPECIAL_BASE 0x4E6BE80ull
+#define SFT2_LBW_RTR_IF_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define SFT2_LBW_RTR_IF_ADDR_DEC_SPECIAL_SECTION 0x1800
+#define mmSFT2_BASE 0x4E6C000ull
+#define SFT2_MAX_OFFSET 0x1000
+#define SFT2_SECTION 0xE800
+#define mmSFT2_SPECIAL_BASE 0x4E6CE80ull
+#define SFT2_SPECIAL_MAX_OFFSET 0x1800
+#define SFT2_SPECIAL_SECTION 0x3180
+#define mmSFT3_HBW_RTR_IF0_RTR_CTRL_BASE 0x4E70000ull
+#define SFT3_HBW_RTR_IF0_RTR_CTRL_MAX_OFFSET 0x1000
+#define SFT3_HBW_RTR_IF0_RTR_CTRL_SECTION 0xE800
+#define mmSFT3_HBW_RTR_IF0_RTR_CTRL_SPECIAL_BASE 0x4E70E80ull
+#define SFT3_HBW_RTR_IF0_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define SFT3_HBW_RTR_IF0_RTR_CTRL_SPECIAL_SECTION 0x1800
+#define mmSFT3_HBW_RTR_IF0_RTR_H3_BASE 0x4E71000ull
+#define SFT3_HBW_RTR_IF0_RTR_H3_MAX_OFFSET 0x1000
+#define SFT3_HBW_RTR_IF0_RTR_H3_SECTION 0xE800
+#define mmSFT3_HBW_RTR_IF0_RTR_H3_SPECIAL_BASE 0x4E71E80ull
+#define SFT3_HBW_RTR_IF0_RTR_H3_SPECIAL_MAX_OFFSET 0x1800
+#define SFT3_HBW_RTR_IF0_RTR_H3_SPECIAL_SECTION 0x1800
+#define mmSFT3_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE 0x4E72000ull
+#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmSFT3_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_BASE 0x4E72200ull
+#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmSFT3_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_BASE 0x4E72400ull
+#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmSFT3_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_BASE 0x4E72600ull
+#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmSFT3_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_BASE 0x4E72800ull
+#define SFT3_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define SFT3_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmSFT3_HBW_RTR_IF0_MSTR_IF_AXUSER_BASE 0x4E72A80ull
+#define SFT3_HBW_RTR_IF0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define SFT3_HBW_RTR_IF0_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmSFT3_HBW_RTR_IF0_MSTR_IF_DBG_HBW_BASE 0x4E72B00ull
+#define SFT3_HBW_RTR_IF0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define SFT3_HBW_RTR_IF0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmSFT3_HBW_RTR_IF0_MSTR_IF_DBG_LBW_BASE 0x4E72B80ull
+#define SFT3_HBW_RTR_IF0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define SFT3_HBW_RTR_IF0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmSFT3_HBW_RTR_IF0_MSTR_IF_CORE_HBW_BASE 0x4E72C00ull
+#define SFT3_HBW_RTR_IF0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define SFT3_HBW_RTR_IF0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmSFT3_HBW_RTR_IF0_MSTR_IF_CORE_LBW_BASE 0x4E72D80ull
+#define SFT3_HBW_RTR_IF0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define SFT3_HBW_RTR_IF0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmSFT3_HBW_RTR_IF0_MSTR_IF_SPECIAL_BASE 0x4E72E80ull
+#define SFT3_HBW_RTR_IF0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define SFT3_HBW_RTR_IF0_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmSFT3_HBW_RTR_IF0_ADDR_DEC_HBW_BASE 0x4E73000ull
+#define SFT3_HBW_RTR_IF0_ADDR_DEC_HBW_MAX_OFFSET 0x4000
+#define SFT3_HBW_RTR_IF0_ADDR_DEC_HBW_SECTION 0x4000
+#define mmSFT3_HBW_RTR_IF0_ADDR_DEC_LBW_BASE 0x4E73400ull
+#define SFT3_HBW_RTR_IF0_ADDR_DEC_LBW_MAX_OFFSET 0xA600
+#define SFT3_HBW_RTR_IF0_ADDR_DEC_LBW_SECTION 0xA800
+#define mmSFT3_HBW_RTR_IF0_ADDR_DEC_SPECIAL_BASE 0x4E73E80ull
+#define SFT3_HBW_RTR_IF0_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define SFT3_HBW_RTR_IF0_ADDR_DEC_SPECIAL_SECTION 0x1800
+#define mmSFT3_HBW_RTR_IF1_RTR_CTRL_BASE 0x4E74000ull
+#define SFT3_HBW_RTR_IF1_RTR_CTRL_MAX_OFFSET 0x1000
+#define SFT3_HBW_RTR_IF1_RTR_CTRL_SECTION 0xE800
+#define mmSFT3_HBW_RTR_IF1_RTR_CTRL_SPECIAL_BASE 0x4E74E80ull
+#define SFT3_HBW_RTR_IF1_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define SFT3_HBW_RTR_IF1_RTR_CTRL_SPECIAL_SECTION 0x1800
+#define mmSFT3_HBW_RTR_IF1_RTR_H3_BASE 0x4E75000ull
+#define SFT3_HBW_RTR_IF1_RTR_H3_MAX_OFFSET 0x1000
+#define SFT3_HBW_RTR_IF1_RTR_H3_SECTION 0xE800
+#define mmSFT3_HBW_RTR_IF1_RTR_H3_SPECIAL_BASE 0x4E75E80ull
+#define SFT3_HBW_RTR_IF1_RTR_H3_SPECIAL_MAX_OFFSET 0x1800
+#define SFT3_HBW_RTR_IF1_RTR_H3_SPECIAL_SECTION 0x1800
+#define mmSFT3_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE 0x4E76000ull
+#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmSFT3_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_BASE 0x4E76200ull
+#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmSFT3_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_BASE 0x4E76400ull
+#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmSFT3_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_BASE 0x4E76600ull
+#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmSFT3_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_BASE 0x4E76800ull
+#define SFT3_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define SFT3_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmSFT3_HBW_RTR_IF1_MSTR_IF_AXUSER_BASE 0x4E76A80ull
+#define SFT3_HBW_RTR_IF1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define SFT3_HBW_RTR_IF1_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmSFT3_HBW_RTR_IF1_MSTR_IF_DBG_HBW_BASE 0x4E76B00ull
+#define SFT3_HBW_RTR_IF1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define SFT3_HBW_RTR_IF1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmSFT3_HBW_RTR_IF1_MSTR_IF_DBG_LBW_BASE 0x4E76B80ull
+#define SFT3_HBW_RTR_IF1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define SFT3_HBW_RTR_IF1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmSFT3_HBW_RTR_IF1_MSTR_IF_CORE_HBW_BASE 0x4E76C00ull
+#define SFT3_HBW_RTR_IF1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define SFT3_HBW_RTR_IF1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmSFT3_HBW_RTR_IF1_MSTR_IF_CORE_LBW_BASE 0x4E76D80ull
+#define SFT3_HBW_RTR_IF1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define SFT3_HBW_RTR_IF1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmSFT3_HBW_RTR_IF1_MSTR_IF_SPECIAL_BASE 0x4E76E80ull
+#define SFT3_HBW_RTR_IF1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define SFT3_HBW_RTR_IF1_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmSFT3_HBW_RTR_IF1_ADDR_DEC_HBW_BASE 0x4E77000ull
+#define SFT3_HBW_RTR_IF1_ADDR_DEC_HBW_MAX_OFFSET 0x4000
+#define SFT3_HBW_RTR_IF1_ADDR_DEC_HBW_SECTION 0x4000
+#define mmSFT3_HBW_RTR_IF1_ADDR_DEC_LBW_BASE 0x4E77400ull
+#define SFT3_HBW_RTR_IF1_ADDR_DEC_LBW_MAX_OFFSET 0xA600
+#define SFT3_HBW_RTR_IF1_ADDR_DEC_LBW_SECTION 0xA800
+#define mmSFT3_HBW_RTR_IF1_ADDR_DEC_SPECIAL_BASE 0x4E77E80ull
+#define SFT3_HBW_RTR_IF1_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define SFT3_HBW_RTR_IF1_ADDR_DEC_SPECIAL_SECTION 0x1800
+#define mmSFT3_LBW_RTR_IF_RTR_CTRL_BASE 0x4E78000ull
+#define SFT3_LBW_RTR_IF_RTR_CTRL_MAX_OFFSET 0x1000
+#define SFT3_LBW_RTR_IF_RTR_CTRL_SECTION 0xE800
+#define mmSFT3_LBW_RTR_IF_RTR_CTRL_SPECIAL_BASE 0x4E78E80ull
+#define SFT3_LBW_RTR_IF_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define SFT3_LBW_RTR_IF_RTR_CTRL_SPECIAL_SECTION 0x1800
+#define mmSFT3_LBW_RTR_IF_RTR_H3_BASE 0x4E79000ull
+#define SFT3_LBW_RTR_IF_RTR_H3_MAX_OFFSET 0x1000
+#define SFT3_LBW_RTR_IF_RTR_H3_SECTION 0xE800
+#define mmSFT3_LBW_RTR_IF_RTR_H3_SPECIAL_BASE 0x4E79E80ull
+#define SFT3_LBW_RTR_IF_RTR_H3_SPECIAL_MAX_OFFSET 0x1800
+#define SFT3_LBW_RTR_IF_RTR_H3_SPECIAL_SECTION 0x1800
+#define mmSFT3_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE 0x4E7A000ull
+#define SFT3_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define SFT3_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmSFT3_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_BASE 0x4E7A200ull
+#define SFT3_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define SFT3_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmSFT3_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_BASE 0x4E7A400ull
+#define SFT3_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define SFT3_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmSFT3_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_BASE 0x4E7A600ull
+#define SFT3_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define SFT3_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmSFT3_LBW_RTR_IF_MSTR_IF_E2E_CRDT_BASE 0x4E7A800ull
+#define SFT3_LBW_RTR_IF_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define SFT3_LBW_RTR_IF_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmSFT3_LBW_RTR_IF_MSTR_IF_AXUSER_BASE 0x4E7AA80ull
+#define SFT3_LBW_RTR_IF_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define SFT3_LBW_RTR_IF_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmSFT3_LBW_RTR_IF_MSTR_IF_DBG_HBW_BASE 0x4E7AB00ull
+#define SFT3_LBW_RTR_IF_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define SFT3_LBW_RTR_IF_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmSFT3_LBW_RTR_IF_MSTR_IF_DBG_LBW_BASE 0x4E7AB80ull
+#define SFT3_LBW_RTR_IF_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define SFT3_LBW_RTR_IF_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmSFT3_LBW_RTR_IF_MSTR_IF_CORE_HBW_BASE 0x4E7AC00ull
+#define SFT3_LBW_RTR_IF_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define SFT3_LBW_RTR_IF_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmSFT3_LBW_RTR_IF_MSTR_IF_CORE_LBW_BASE 0x4E7AD80ull
+#define SFT3_LBW_RTR_IF_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define SFT3_LBW_RTR_IF_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmSFT3_LBW_RTR_IF_MSTR_IF_SPECIAL_BASE 0x4E7AE80ull
+#define SFT3_LBW_RTR_IF_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define SFT3_LBW_RTR_IF_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmSFT3_LBW_RTR_IF_ADDR_DEC_HBW_BASE 0x4E7B000ull
+#define SFT3_LBW_RTR_IF_ADDR_DEC_HBW_MAX_OFFSET 0x4000
+#define SFT3_LBW_RTR_IF_ADDR_DEC_HBW_SECTION 0x4000
+#define mmSFT3_LBW_RTR_IF_ADDR_DEC_LBW_BASE 0x4E7B400ull
+#define SFT3_LBW_RTR_IF_ADDR_DEC_LBW_MAX_OFFSET 0xA600
+#define SFT3_LBW_RTR_IF_ADDR_DEC_LBW_SECTION 0xA800
+#define mmSFT3_LBW_RTR_IF_ADDR_DEC_SPECIAL_BASE 0x4E7BE80ull
+#define SFT3_LBW_RTR_IF_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800
+#define SFT3_LBW_RTR_IF_ADDR_DEC_SPECIAL_SECTION 0x1800
+#define mmSFT3_BASE 0x4E7C000ull
+#define SFT3_MAX_OFFSET 0x1000
+#define SFT3_SECTION 0xE800
+#define mmSFT3_SPECIAL_BASE 0x4E7CE80ull
+#define SFT3_SPECIAL_MAX_OFFSET 0x1800
+#define SFT3_SPECIAL_SECTION 0x4180
+#define mmARC_FARM_FARM_BASE 0x4E81000ull
+#define ARC_FARM_FARM_MAX_OFFSET 0x1000
+#define ARC_FARM_FARM_SECTION 0xE800
+#define mmARC_FARM_FARM_SPECIAL_BASE 0x4E81E80ull
+#define ARC_FARM_FARM_SPECIAL_MAX_OFFSET 0x1800
+#define ARC_FARM_FARM_SPECIAL_SECTION 0x1800
+#define mmARC_FARM_FARM_MSTR_IF_RR_SHRD_HBW_BASE 0x4E82000ull
+#define ARC_FARM_FARM_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define ARC_FARM_FARM_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmARC_FARM_FARM_MSTR_IF_RR_PRVT_HBW_BASE 0x4E82200ull
+#define ARC_FARM_FARM_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define ARC_FARM_FARM_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmARC_FARM_FARM_MSTR_IF_RR_SHRD_LBW_BASE 0x4E82400ull
+#define ARC_FARM_FARM_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define ARC_FARM_FARM_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmARC_FARM_FARM_MSTR_IF_RR_PRVT_LBW_BASE 0x4E82600ull
+#define ARC_FARM_FARM_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define ARC_FARM_FARM_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmARC_FARM_FARM_MSTR_IF_E2E_CRDT_BASE 0x4E82800ull
+#define ARC_FARM_FARM_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define ARC_FARM_FARM_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmARC_FARM_FARM_MSTR_IF_AXUSER_BASE 0x4E82A80ull
+#define ARC_FARM_FARM_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define ARC_FARM_FARM_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmARC_FARM_FARM_MSTR_IF_DBG_HBW_BASE 0x4E82B00ull
+#define ARC_FARM_FARM_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define ARC_FARM_FARM_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmARC_FARM_FARM_MSTR_IF_DBG_LBW_BASE 0x4E82B80ull
+#define ARC_FARM_FARM_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define ARC_FARM_FARM_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmARC_FARM_FARM_MSTR_IF_CORE_HBW_BASE 0x4E82C00ull
+#define ARC_FARM_FARM_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define ARC_FARM_FARM_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmARC_FARM_FARM_MSTR_IF_CORE_LBW_BASE 0x4E82D80ull
+#define ARC_FARM_FARM_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define ARC_FARM_FARM_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmARC_FARM_FARM_MSTR_IF_SPECIAL_BASE 0x4E82E80ull
+#define ARC_FARM_FARM_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define ARC_FARM_FARM_MSTR_IF_SPECIAL_SECTION 0x5180
+#define mmARC_FARM_ARC0_AUX_BASE 0x4E88000ull
+#define ARC_FARM_ARC0_AUX_MAX_OFFSET 0x1000
+#define ARC_FARM_ARC0_AUX_SECTION 0xE800
+#define mmARC_FARM_ARC0_AUX_SPECIAL_BASE 0x4E88E80ull
+#define ARC_FARM_ARC0_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define ARC_FARM_ARC0_AUX_SPECIAL_SECTION 0x1800
+#define mmARC_FARM_ARC0_DUP_ENG_BASE 0x4E89000ull
+#define ARC_FARM_ARC0_DUP_ENG_MAX_OFFSET 0x1000
+#define ARC_FARM_ARC0_DUP_ENG_SECTION 0x9000
+#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_BASE 0x4E89900ull
+#define ARC_FARM_ARC0_DUP_ENG_AXUSER_MAX_OFFSET 0x5000
+#define ARC_FARM_ARC0_DUP_ENG_AXUSER_SECTION 0x5800
+#define mmARC_FARM_ARC0_DUP_ENG_SPECIAL_BASE 0x4E89E80ull
+#define ARC_FARM_ARC0_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800
+#define ARC_FARM_ARC0_DUP_ENG_SPECIAL_SECTION 0x1180
+#define mmARC_FARM_KDMA_BASE 0x4E8B000ull
+#define ARC_FARM_KDMA_MAX_OFFSET 0x1000
+#define ARC_FARM_KDMA_SECTION 0x8000
+#define mmARC_FARM_KDMA_CTX_AXUSER_BASE 0x4E8B800ull
+#define ARC_FARM_KDMA_CTX_AXUSER_MAX_OFFSET 0x5000
+#define ARC_FARM_KDMA_CTX_AXUSER_SECTION 0x6000
+#define mmARC_FARM_KDMA_CTX_BASE 0x4E8B860ull
+#define ARC_FARM_KDMA_CTX_MAX_OFFSET 0x9000
+#define ARC_FARM_KDMA_CTX_SECTION 0x5A00
+#define mmARC_FARM_KDMA_KDMA_CGM_BASE 0x4E8BE00ull
+#define ARC_FARM_KDMA_KDMA_CGM_MAX_OFFSET 0xC000
+#define ARC_FARM_KDMA_KDMA_CGM_SECTION 0x8000
+#define mmARC_FARM_KDMA_SPECIAL_BASE 0x4E8BE80ull
+#define ARC_FARM_KDMA_SPECIAL_MAX_OFFSET 0x1800
+#define ARC_FARM_KDMA_SPECIAL_SECTION 0x1800
+#define mmARC_FARM_KDMA_MSTR_IF_RR_SHRD_HBW_BASE 0x4E8C000ull
+#define ARC_FARM_KDMA_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define ARC_FARM_KDMA_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmARC_FARM_KDMA_MSTR_IF_RR_PRVT_HBW_BASE 0x4E8C200ull
+#define ARC_FARM_KDMA_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define ARC_FARM_KDMA_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmARC_FARM_KDMA_MSTR_IF_RR_SHRD_LBW_BASE 0x4E8C400ull
+#define ARC_FARM_KDMA_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define ARC_FARM_KDMA_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmARC_FARM_KDMA_MSTR_IF_RR_PRVT_LBW_BASE 0x4E8C600ull
+#define ARC_FARM_KDMA_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define ARC_FARM_KDMA_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmARC_FARM_KDMA_MSTR_IF_E2E_CRDT_BASE 0x4E8C800ull
+#define ARC_FARM_KDMA_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define ARC_FARM_KDMA_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmARC_FARM_KDMA_MSTR_IF_AXUSER_BASE 0x4E8CA80ull
+#define ARC_FARM_KDMA_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define ARC_FARM_KDMA_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmARC_FARM_KDMA_MSTR_IF_DBG_HBW_BASE 0x4E8CB00ull
+#define ARC_FARM_KDMA_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define ARC_FARM_KDMA_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmARC_FARM_KDMA_MSTR_IF_DBG_LBW_BASE 0x4E8CB80ull
+#define ARC_FARM_KDMA_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define ARC_FARM_KDMA_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmARC_FARM_KDMA_MSTR_IF_CORE_HBW_BASE 0x4E8CC00ull
+#define ARC_FARM_KDMA_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define ARC_FARM_KDMA_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmARC_FARM_KDMA_MSTR_IF_CORE_LBW_BASE 0x4E8CD80ull
+#define ARC_FARM_KDMA_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define ARC_FARM_KDMA_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmARC_FARM_KDMA_MSTR_IF_SPECIAL_BASE 0x4E8CE80ull
+#define ARC_FARM_KDMA_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define ARC_FARM_KDMA_MSTR_IF_SPECIAL_SECTION 0x2180
+#define mmARC_FARM_ARC0_ACP_ENG_BASE 0x4E8F000ull
+#define ARC_FARM_ARC0_ACP_ENG_MAX_OFFSET 0x1000
+#define ARC_FARM_ARC0_ACP_ENG_SECTION 0xE800
+#define mmARC_FARM_ARC0_ACP_ENG_SPECIAL_BASE 0x4E8FE80ull
+#define ARC_FARM_ARC0_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800
+#define ARC_FARM_ARC0_ACP_ENG_SPECIAL_SECTION 0x1800
+#define mmARC_FARM_ARC0_DCCM0_BASE 0x4E90000ull
+#define ARC_FARM_ARC0_DCCM0_MAX_OFFSET 0x4000
+#define ARC_FARM_ARC0_DCCM0_SECTION 0x8000
+#define mmARC_FARM_ARC0_DCCM1_BASE 0x4E98000ull
+#define ARC_FARM_ARC0_DCCM1_MAX_OFFSET 0x4000
+#define ARC_FARM_ARC0_DCCM1_SECTION 0x10000
+#define mmARC_FARM_ARC1_AUX_BASE 0x4EA8000ull
+#define ARC_FARM_ARC1_AUX_MAX_OFFSET 0x1000
+#define ARC_FARM_ARC1_AUX_SECTION 0xE800
+#define mmARC_FARM_ARC1_AUX_SPECIAL_BASE 0x4EA8E80ull
+#define ARC_FARM_ARC1_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define ARC_FARM_ARC1_AUX_SPECIAL_SECTION 0x1800
+#define mmARC_FARM_ARC1_DUP_ENG_BASE 0x4EA9000ull
+#define ARC_FARM_ARC1_DUP_ENG_MAX_OFFSET 0x1000
+#define ARC_FARM_ARC1_DUP_ENG_SECTION 0x9000
+#define mmARC_FARM_ARC1_DUP_ENG_AXUSER_BASE 0x4EA9900ull
+#define ARC_FARM_ARC1_DUP_ENG_AXUSER_MAX_OFFSET 0x5000
+#define ARC_FARM_ARC1_DUP_ENG_AXUSER_SECTION 0x5800
+#define mmARC_FARM_ARC1_DUP_ENG_SPECIAL_BASE 0x4EA9E80ull
+#define ARC_FARM_ARC1_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800
+#define ARC_FARM_ARC1_DUP_ENG_SPECIAL_SECTION 0x5180
+#define mmARC_FARM_ARC1_ACP_ENG_BASE 0x4EAF000ull
+#define ARC_FARM_ARC1_ACP_ENG_MAX_OFFSET 0x1000
+#define ARC_FARM_ARC1_ACP_ENG_SECTION 0xE800
+#define mmARC_FARM_ARC1_ACP_ENG_SPECIAL_BASE 0x4EAFE80ull
+#define ARC_FARM_ARC1_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800
+#define ARC_FARM_ARC1_ACP_ENG_SPECIAL_SECTION 0x1800
+#define mmARC_FARM_ARC1_DCCM0_BASE 0x4EB0000ull
+#define ARC_FARM_ARC1_DCCM0_MAX_OFFSET 0x4000
+#define ARC_FARM_ARC1_DCCM0_SECTION 0x8000
+#define mmARC_FARM_ARC1_DCCM1_BASE 0x4EB8000ull
+#define ARC_FARM_ARC1_DCCM1_MAX_OFFSET 0x4000
+#define ARC_FARM_ARC1_DCCM1_SECTION 0x10000
+#define mmARC_FARM_ARC2_AUX_BASE 0x4EC8000ull
+#define ARC_FARM_ARC2_AUX_MAX_OFFSET 0x1000
+#define ARC_FARM_ARC2_AUX_SECTION 0xE800
+#define mmARC_FARM_ARC2_AUX_SPECIAL_BASE 0x4EC8E80ull
+#define ARC_FARM_ARC2_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define ARC_FARM_ARC2_AUX_SPECIAL_SECTION 0x1800
+#define mmARC_FARM_ARC2_DUP_ENG_BASE 0x4EC9000ull
+#define ARC_FARM_ARC2_DUP_ENG_MAX_OFFSET 0x1000
+#define ARC_FARM_ARC2_DUP_ENG_SECTION 0x9000
+#define mmARC_FARM_ARC2_DUP_ENG_AXUSER_BASE 0x4EC9900ull
+#define ARC_FARM_ARC2_DUP_ENG_AXUSER_MAX_OFFSET 0x5000
+#define ARC_FARM_ARC2_DUP_ENG_AXUSER_SECTION 0x5800
+#define mmARC_FARM_ARC2_DUP_ENG_SPECIAL_BASE 0x4EC9E80ull
+#define ARC_FARM_ARC2_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800
+#define ARC_FARM_ARC2_DUP_ENG_SPECIAL_SECTION 0x5180
+#define mmARC_FARM_ARC2_ACP_ENG_BASE 0x4ECF000ull
+#define ARC_FARM_ARC2_ACP_ENG_MAX_OFFSET 0x1000
+#define ARC_FARM_ARC2_ACP_ENG_SECTION 0xE800
+#define mmARC_FARM_ARC2_ACP_ENG_SPECIAL_BASE 0x4ECFE80ull
+#define ARC_FARM_ARC2_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800
+#define ARC_FARM_ARC2_ACP_ENG_SPECIAL_SECTION 0x1800
+#define mmARC_FARM_ARC2_DCCM0_BASE 0x4ED0000ull
+#define ARC_FARM_ARC2_DCCM0_MAX_OFFSET 0x4000
+#define ARC_FARM_ARC2_DCCM0_SECTION 0x8000
+#define mmARC_FARM_ARC2_DCCM1_BASE 0x4ED8000ull
+#define ARC_FARM_ARC2_DCCM1_MAX_OFFSET 0x4000
+#define ARC_FARM_ARC2_DCCM1_SECTION 0x10000
+#define mmARC_FARM_ARC3_AUX_BASE 0x4EE8000ull
+#define ARC_FARM_ARC3_AUX_MAX_OFFSET 0x1000
+#define ARC_FARM_ARC3_AUX_SECTION 0xE800
+#define mmARC_FARM_ARC3_AUX_SPECIAL_BASE 0x4EE8E80ull
+#define ARC_FARM_ARC3_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define ARC_FARM_ARC3_AUX_SPECIAL_SECTION 0x1800
+#define mmARC_FARM_ARC3_DUP_ENG_BASE 0x4EE9000ull
+#define ARC_FARM_ARC3_DUP_ENG_MAX_OFFSET 0x1000
+#define ARC_FARM_ARC3_DUP_ENG_SECTION 0x9000
+#define mmARC_FARM_ARC3_DUP_ENG_AXUSER_BASE 0x4EE9900ull
+#define ARC_FARM_ARC3_DUP_ENG_AXUSER_MAX_OFFSET 0x5000
+#define ARC_FARM_ARC3_DUP_ENG_AXUSER_SECTION 0x5800
+#define mmARC_FARM_ARC3_DUP_ENG_SPECIAL_BASE 0x4EE9E80ull
+#define ARC_FARM_ARC3_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800
+#define ARC_FARM_ARC3_DUP_ENG_SPECIAL_SECTION 0x5180
+#define mmARC_FARM_ARC3_ACP_ENG_BASE 0x4EEF000ull
+#define ARC_FARM_ARC3_ACP_ENG_MAX_OFFSET 0x1000
+#define ARC_FARM_ARC3_ACP_ENG_SECTION 0xE800
+#define mmARC_FARM_ARC3_ACP_ENG_SPECIAL_BASE 0x4EEFE80ull
+#define ARC_FARM_ARC3_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800
+#define ARC_FARM_ARC3_ACP_ENG_SPECIAL_SECTION 0x1800
+#define mmARC_FARM_ARC3_DCCM0_BASE 0x4EF0000ull
+#define ARC_FARM_ARC3_DCCM0_MAX_OFFSET 0x4000
+#define ARC_FARM_ARC3_DCCM0_SECTION 0x8000
+#define mmARC_FARM_ARC3_DCCM1_BASE 0x4EF8000ull
+#define ARC_FARM_ARC3_DCCM1_MAX_OFFSET 0x4000
+#define ARC_FARM_ARC3_DCCM1_SECTION 0x8000
+#define mmPCIE_DEC0_CMD_BASE 0x4F00000ull
+#define PCIE_DEC0_CMD_MAX_OFFSET 0x1100
+#define PCIE_DEC0_CMD_SECTION 0x1000
+#define mmPCIE_DEC0_VSI_BASE 0x4F01000ull
+#define PCIE_DEC0_VSI_MAX_OFFSET 0x6FC0
+#define PCIE_DEC0_VSI_SECTION 0x1000
+#define mmPCIE_DEC0_L2C_BASE 0x4F02000ull
+#define PCIE_DEC0_L2C_MAX_OFFSET 0x39C0
+#define PCIE_DEC0_L2C_SECTION 0x1000
+#define mmPCIE_VDEC0_BRDG_CTRL_BASE 0x4F03000ull
+#define PCIE_VDEC0_BRDG_CTRL_MAX_OFFSET 0x1000
+#define PCIE_VDEC0_BRDG_CTRL_SECTION 0x8000
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x4F03800ull
+#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000
+#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x4F03900ull
+#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000
+#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x4F03A00ull
+#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000
+#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x4F03B00ull
+#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000
+#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_BASE 0x4F03C00ull
+#define PCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000
+#define PCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800
+#define mmPCIE_VDEC0_BRDG_CTRL_SPECIAL_BASE 0x4F03E80ull
+#define PCIE_VDEC0_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define PCIE_VDEC0_BRDG_CTRL_SPECIAL_SECTION 0x1800
+#define mmPCIE_VDEC0_CTRL_BASE 0x4F04000ull
+#define PCIE_VDEC0_CTRL_MAX_OFFSET 0x1000
+#define PCIE_VDEC0_CTRL_SECTION 0xE800
+#define mmPCIE_VDEC0_CTRL_SPECIAL_BASE 0x4F04E80ull
+#define PCIE_VDEC0_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define PCIE_VDEC0_CTRL_SPECIAL_SECTION 0x1800
+#define mmPCIE_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE 0x4F05000ull
+#define PCIE_VDEC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define PCIE_VDEC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmPCIE_VDEC0_MSTR_IF_RR_PRVT_HBW_BASE 0x4F05200ull
+#define PCIE_VDEC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define PCIE_VDEC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmPCIE_VDEC0_MSTR_IF_RR_SHRD_LBW_BASE 0x4F05400ull
+#define PCIE_VDEC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define PCIE_VDEC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmPCIE_VDEC0_MSTR_IF_RR_PRVT_LBW_BASE 0x4F05600ull
+#define PCIE_VDEC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define PCIE_VDEC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmPCIE_VDEC0_MSTR_IF_E2E_CRDT_BASE 0x4F05800ull
+#define PCIE_VDEC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define PCIE_VDEC0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmPCIE_VDEC0_MSTR_IF_AXUSER_BASE 0x4F05A80ull
+#define PCIE_VDEC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define PCIE_VDEC0_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmPCIE_VDEC0_MSTR_IF_DBG_HBW_BASE 0x4F05B00ull
+#define PCIE_VDEC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define PCIE_VDEC0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmPCIE_VDEC0_MSTR_IF_DBG_LBW_BASE 0x4F05B80ull
+#define PCIE_VDEC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define PCIE_VDEC0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmPCIE_VDEC0_MSTR_IF_CORE_HBW_BASE 0x4F05C00ull
+#define PCIE_VDEC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define PCIE_VDEC0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmPCIE_VDEC0_MSTR_IF_CORE_LBW_BASE 0x4F05D80ull
+#define PCIE_VDEC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define PCIE_VDEC0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmPCIE_VDEC0_MSTR_IF_SPECIAL_BASE 0x4F05E80ull
+#define PCIE_VDEC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define PCIE_VDEC0_MSTR_IF_SPECIAL_SECTION 0xA180
+#define mmPCIE_DEC1_CMD_BASE 0x4F10000ull
+#define PCIE_DEC1_CMD_MAX_OFFSET 0x1100
+#define PCIE_DEC1_CMD_SECTION 0x1000
+#define mmPCIE_DEC1_VSI_BASE 0x4F11000ull
+#define PCIE_DEC1_VSI_MAX_OFFSET 0x6FC0
+#define PCIE_DEC1_VSI_SECTION 0x1000
+#define mmPCIE_DEC1_L2C_BASE 0x4F12000ull
+#define PCIE_DEC1_L2C_MAX_OFFSET 0x39C0
+#define PCIE_DEC1_L2C_SECTION 0x1000
+#define mmPCIE_VDEC1_BRDG_CTRL_BASE 0x4F13000ull
+#define PCIE_VDEC1_BRDG_CTRL_MAX_OFFSET 0x1000
+#define PCIE_VDEC1_BRDG_CTRL_SECTION 0x8000
+#define mmPCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x4F13800ull
+#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000
+#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000
+#define mmPCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x4F13900ull
+#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000
+#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000
+#define mmPCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x4F13A00ull
+#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000
+#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000
+#define mmPCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x4F13B00ull
+#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000
+#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000
+#define mmPCIE_VDEC1_BRDG_CTRL_AXUSER_DEC_BASE 0x4F13C00ull
+#define PCIE_VDEC1_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000
+#define PCIE_VDEC1_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800
+#define mmPCIE_VDEC1_BRDG_CTRL_SPECIAL_BASE 0x4F13E80ull
+#define PCIE_VDEC1_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define PCIE_VDEC1_BRDG_CTRL_SPECIAL_SECTION 0x1800
+#define mmPCIE_VDEC1_CTRL_BASE 0x4F14000ull
+#define PCIE_VDEC1_CTRL_MAX_OFFSET 0x1000
+#define PCIE_VDEC1_CTRL_SECTION 0xE800
+#define mmPCIE_VDEC1_CTRL_SPECIAL_BASE 0x4F14E80ull
+#define PCIE_VDEC1_CTRL_SPECIAL_MAX_OFFSET 0x1800
+#define PCIE_VDEC1_CTRL_SPECIAL_SECTION 0x1800
+#define mmPCIE_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE 0x4F15000ull
+#define PCIE_VDEC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define PCIE_VDEC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmPCIE_VDEC1_MSTR_IF_RR_PRVT_HBW_BASE 0x4F15200ull
+#define PCIE_VDEC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define PCIE_VDEC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmPCIE_VDEC1_MSTR_IF_RR_SHRD_LBW_BASE 0x4F15400ull
+#define PCIE_VDEC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define PCIE_VDEC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmPCIE_VDEC1_MSTR_IF_RR_PRVT_LBW_BASE 0x4F15600ull
+#define PCIE_VDEC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define PCIE_VDEC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmPCIE_VDEC1_MSTR_IF_E2E_CRDT_BASE 0x4F15800ull
+#define PCIE_VDEC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define PCIE_VDEC1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmPCIE_VDEC1_MSTR_IF_AXUSER_BASE 0x4F15A80ull
+#define PCIE_VDEC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define PCIE_VDEC1_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmPCIE_VDEC1_MSTR_IF_DBG_HBW_BASE 0x4F15B00ull
+#define PCIE_VDEC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define PCIE_VDEC1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmPCIE_VDEC1_MSTR_IF_DBG_LBW_BASE 0x4F15B80ull
+#define PCIE_VDEC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define PCIE_VDEC1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmPCIE_VDEC1_MSTR_IF_CORE_HBW_BASE 0x4F15C00ull
+#define PCIE_VDEC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define PCIE_VDEC1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmPCIE_VDEC1_MSTR_IF_CORE_LBW_BASE 0x4F15D80ull
+#define PCIE_VDEC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define PCIE_VDEC1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmPCIE_VDEC1_MSTR_IF_SPECIAL_BASE 0x4F15E80ull
+#define PCIE_VDEC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define PCIE_VDEC1_MSTR_IF_SPECIAL_SECTION 0x2A180
+#define mmDCORE0_XFT_BASE 0x4F40000ull
+#define DCORE0_XFT_MAX_OFFSET 0x1000
+#define DCORE0_XFT_SECTION 0xE800
+#define mmDCORE0_XFT_SPECIAL_BASE 0x4F40E80ull
+#define DCORE0_XFT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_XFT_SPECIAL_SECTION 0x1800
+#define mmDCORE0_HBM_PLL_CTRL_BASE 0x4F41000ull
+#define DCORE0_HBM_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE0_HBM_PLL_CTRL_SECTION 0x3600
+#define mmDCORE0_HBM_PLL_ASIF_SLV_BASE 0x4F41360ull
+#define DCORE0_HBM_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE0_HBM_PLL_ASIF_SLV_SECTION 0xA000
+#define mmDCORE0_HBM_PLL_DIV_0_RLX_BASE 0x4F41400ull
+#define DCORE0_HBM_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE0_HBM_PLL_DIV_0_RLX_SECTION 0x4000
+#define mmDCORE0_HBM_PLL_DIV_1_RLX_BASE 0x4F41800ull
+#define DCORE0_HBM_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE0_HBM_PLL_DIV_1_RLX_SECTION 0x2000
+#define mmDCORE0_HBM_PLL_DIV_2_RLX_BASE 0x4F41A00ull
+#define DCORE0_HBM_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE0_HBM_PLL_DIV_2_RLX_SECTION 0x2000
+#define mmDCORE0_HBM_PLL_DIV_3_RLX_BASE 0x4F41C00ull
+#define DCORE0_HBM_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE0_HBM_PLL_DIV_3_RLX_SECTION 0x2800
+#define mmDCORE0_HBM_PLL_SPECIAL_BASE 0x4F41E80ull
+#define DCORE0_HBM_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_HBM_PLL_SPECIAL_SECTION 0x1800
+#define mmDCORE0_TPC_PLL_CTRL_BASE 0x4F42000ull
+#define DCORE0_TPC_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE0_TPC_PLL_CTRL_SECTION 0x3600
+#define mmDCORE0_TPC_PLL_ASIF_SLV_BASE 0x4F42360ull
+#define DCORE0_TPC_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE0_TPC_PLL_ASIF_SLV_SECTION 0xA000
+#define mmDCORE0_TPC_PLL_DIV_0_RLX_BASE 0x4F42400ull
+#define DCORE0_TPC_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE0_TPC_PLL_DIV_0_RLX_SECTION 0x4000
+#define mmDCORE0_TPC_PLL_DIV_1_RLX_BASE 0x4F42800ull
+#define DCORE0_TPC_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE0_TPC_PLL_DIV_1_RLX_SECTION 0x2000
+#define mmDCORE0_TPC_PLL_DIV_2_RLX_BASE 0x4F42A00ull
+#define DCORE0_TPC_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE0_TPC_PLL_DIV_2_RLX_SECTION 0x2000
+#define mmDCORE0_TPC_PLL_DIV_3_RLX_BASE 0x4F42C00ull
+#define DCORE0_TPC_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE0_TPC_PLL_DIV_3_RLX_SECTION 0x2800
+#define mmDCORE0_TPC_PLL_SPECIAL_BASE 0x4F42E80ull
+#define DCORE0_TPC_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_TPC_PLL_SPECIAL_SECTION 0x1800
+#define mmDCORE0_PCI_PLL_CTRL_BASE 0x4F43000ull
+#define DCORE0_PCI_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE0_PCI_PLL_CTRL_SECTION 0x3600
+#define mmDCORE0_PCI_PLL_ASIF_SLV_BASE 0x4F43360ull
+#define DCORE0_PCI_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE0_PCI_PLL_ASIF_SLV_SECTION 0xA000
+#define mmDCORE0_PCI_PLL_DIV_0_RLX_BASE 0x4F43400ull
+#define DCORE0_PCI_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE0_PCI_PLL_DIV_0_RLX_SECTION 0x4000
+#define mmDCORE0_PCI_PLL_DIV_1_RLX_BASE 0x4F43800ull
+#define DCORE0_PCI_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE0_PCI_PLL_DIV_1_RLX_SECTION 0x2000
+#define mmDCORE0_PCI_PLL_DIV_2_RLX_BASE 0x4F43A00ull
+#define DCORE0_PCI_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE0_PCI_PLL_DIV_2_RLX_SECTION 0x2000
+#define mmDCORE0_PCI_PLL_DIV_3_RLX_BASE 0x4F43C00ull
+#define DCORE0_PCI_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE0_PCI_PLL_DIV_3_RLX_SECTION 0x2800
+#define mmDCORE0_PCI_PLL_SPECIAL_BASE 0x4F43E80ull
+#define DCORE0_PCI_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE0_PCI_PLL_SPECIAL_SECTION 0x1180
+#define mmDCORE0_TSTDVS_BASE 0x4F45000ull
+#define DCORE0_TSTDVS_MAX_OFFSET 0x7800
+#define DCORE0_TSTDVS_SECTION 0x1000
+#define mmDCORE0_TS_WRAP_BASE 0x4F46000ull
+#define DCORE0_TS_WRAP_MAX_OFFSET 0x2380
+#define DCORE0_TS_WRAP_SECTION 0x2000
+#define mmDCORE0_TS_WRAP_ASIF_SLV_BASE 0x4F46200ull
+#define DCORE0_TS_WRAP_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE0_TS_WRAP_ASIF_SLV_SECTION 0x9E00
+#define mmDCORE1_XFT_BASE 0x4F50000ull
+#define DCORE1_XFT_MAX_OFFSET 0x1000
+#define DCORE1_XFT_SECTION 0xE800
+#define mmDCORE1_XFT_SPECIAL_BASE 0x4F50E80ull
+#define DCORE1_XFT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_XFT_SPECIAL_SECTION 0x1800
+#define mmDCORE1_HBM_PLL_CTRL_BASE 0x4F51000ull
+#define DCORE1_HBM_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE1_HBM_PLL_CTRL_SECTION 0x3600
+#define mmDCORE1_HBM_PLL_ASIF_SLV_BASE 0x4F51360ull
+#define DCORE1_HBM_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE1_HBM_PLL_ASIF_SLV_SECTION 0xA000
+#define mmDCORE1_HBM_PLL_DIV_0_RLX_BASE 0x4F51400ull
+#define DCORE1_HBM_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE1_HBM_PLL_DIV_0_RLX_SECTION 0x4000
+#define mmDCORE1_HBM_PLL_DIV_1_RLX_BASE 0x4F51800ull
+#define DCORE1_HBM_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE1_HBM_PLL_DIV_1_RLX_SECTION 0x2000
+#define mmDCORE1_HBM_PLL_DIV_2_RLX_BASE 0x4F51A00ull
+#define DCORE1_HBM_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE1_HBM_PLL_DIV_2_RLX_SECTION 0x2000
+#define mmDCORE1_HBM_PLL_DIV_3_RLX_BASE 0x4F51C00ull
+#define DCORE1_HBM_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE1_HBM_PLL_DIV_3_RLX_SECTION 0x2800
+#define mmDCORE1_HBM_PLL_SPECIAL_BASE 0x4F51E80ull
+#define DCORE1_HBM_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_HBM_PLL_SPECIAL_SECTION 0x1800
+#define mmDCORE1_TPC_PLL_CTRL_BASE 0x4F52000ull
+#define DCORE1_TPC_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE1_TPC_PLL_CTRL_SECTION 0x3600
+#define mmDCORE1_TPC_PLL_ASIF_SLV_BASE 0x4F52360ull
+#define DCORE1_TPC_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE1_TPC_PLL_ASIF_SLV_SECTION 0xA000
+#define mmDCORE1_TPC_PLL_DIV_0_RLX_BASE 0x4F52400ull
+#define DCORE1_TPC_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE1_TPC_PLL_DIV_0_RLX_SECTION 0x4000
+#define mmDCORE1_TPC_PLL_DIV_1_RLX_BASE 0x4F52800ull
+#define DCORE1_TPC_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE1_TPC_PLL_DIV_1_RLX_SECTION 0x2000
+#define mmDCORE1_TPC_PLL_DIV_2_RLX_BASE 0x4F52A00ull
+#define DCORE1_TPC_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE1_TPC_PLL_DIV_2_RLX_SECTION 0x2000
+#define mmDCORE1_TPC_PLL_DIV_3_RLX_BASE 0x4F52C00ull
+#define DCORE1_TPC_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE1_TPC_PLL_DIV_3_RLX_SECTION 0x2800
+#define mmDCORE1_TPC_PLL_SPECIAL_BASE 0x4F52E80ull
+#define DCORE1_TPC_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_TPC_PLL_SPECIAL_SECTION 0x1800
+#define mmDCORE1_NIC_PLL_CTRL_BASE 0x4F53000ull
+#define DCORE1_NIC_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE1_NIC_PLL_CTRL_SECTION 0x3600
+#define mmDCORE1_NIC_PLL_ASIF_SLV_BASE 0x4F53360ull
+#define DCORE1_NIC_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE1_NIC_PLL_ASIF_SLV_SECTION 0xA000
+#define mmDCORE1_NIC_PLL_DIV_0_RLX_BASE 0x4F53400ull
+#define DCORE1_NIC_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE1_NIC_PLL_DIV_0_RLX_SECTION 0x4000
+#define mmDCORE1_NIC_PLL_DIV_1_RLX_BASE 0x4F53800ull
+#define DCORE1_NIC_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE1_NIC_PLL_DIV_1_RLX_SECTION 0x2000
+#define mmDCORE1_NIC_PLL_DIV_2_RLX_BASE 0x4F53A00ull
+#define DCORE1_NIC_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE1_NIC_PLL_DIV_2_RLX_SECTION 0x2000
+#define mmDCORE1_NIC_PLL_DIV_3_RLX_BASE 0x4F53C00ull
+#define DCORE1_NIC_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE1_NIC_PLL_DIV_3_RLX_SECTION 0x2800
+#define mmDCORE1_NIC_PLL_SPECIAL_BASE 0x4F53E80ull
+#define DCORE1_NIC_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE1_NIC_PLL_SPECIAL_SECTION 0x1180
+#define mmDCORE1_TSTDVS_BASE 0x4F55000ull
+#define DCORE1_TSTDVS_MAX_OFFSET 0x7800
+#define DCORE1_TSTDVS_SECTION 0x1000
+#define mmDCORE1_TS_WRAP_BASE 0x4F56000ull
+#define DCORE1_TS_WRAP_MAX_OFFSET 0x2380
+#define DCORE1_TS_WRAP_SECTION 0x2000
+#define mmDCORE1_TS_WRAP_ASIF_SLV_BASE 0x4F56200ull
+#define DCORE1_TS_WRAP_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE1_TS_WRAP_ASIF_SLV_SECTION 0x9E00
+#define mmDCORE2_XFT_BASE 0x4F60000ull
+#define DCORE2_XFT_MAX_OFFSET 0x1000
+#define DCORE2_XFT_SECTION 0xE800
+#define mmDCORE2_XFT_SPECIAL_BASE 0x4F60E80ull
+#define DCORE2_XFT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_XFT_SPECIAL_SECTION 0x1800
+#define mmDCORE2_HBM_PLL_CTRL_BASE 0x4F61000ull
+#define DCORE2_HBM_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE2_HBM_PLL_CTRL_SECTION 0x3600
+#define mmDCORE2_HBM_PLL_ASIF_SLV_BASE 0x4F61360ull
+#define DCORE2_HBM_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE2_HBM_PLL_ASIF_SLV_SECTION 0xA000
+#define mmDCORE2_HBM_PLL_DIV_0_RLX_BASE 0x4F61400ull
+#define DCORE2_HBM_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE2_HBM_PLL_DIV_0_RLX_SECTION 0x4000
+#define mmDCORE2_HBM_PLL_DIV_1_RLX_BASE 0x4F61800ull
+#define DCORE2_HBM_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE2_HBM_PLL_DIV_1_RLX_SECTION 0x2000
+#define mmDCORE2_HBM_PLL_DIV_2_RLX_BASE 0x4F61A00ull
+#define DCORE2_HBM_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE2_HBM_PLL_DIV_2_RLX_SECTION 0x2000
+#define mmDCORE2_HBM_PLL_DIV_3_RLX_BASE 0x4F61C00ull
+#define DCORE2_HBM_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE2_HBM_PLL_DIV_3_RLX_SECTION 0x2800
+#define mmDCORE2_HBM_PLL_SPECIAL_BASE 0x4F61E80ull
+#define DCORE2_HBM_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_HBM_PLL_SPECIAL_SECTION 0x1800
+#define mmDCORE2_TPC_PLL_CTRL_BASE 0x4F62000ull
+#define DCORE2_TPC_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE2_TPC_PLL_CTRL_SECTION 0x3600
+#define mmDCORE2_TPC_PLL_ASIF_SLV_BASE 0x4F62360ull
+#define DCORE2_TPC_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE2_TPC_PLL_ASIF_SLV_SECTION 0xA000
+#define mmDCORE2_TPC_PLL_DIV_0_RLX_BASE 0x4F62400ull
+#define DCORE2_TPC_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE2_TPC_PLL_DIV_0_RLX_SECTION 0x4000
+#define mmDCORE2_TPC_PLL_DIV_1_RLX_BASE 0x4F62800ull
+#define DCORE2_TPC_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE2_TPC_PLL_DIV_1_RLX_SECTION 0x2000
+#define mmDCORE2_TPC_PLL_DIV_2_RLX_BASE 0x4F62A00ull
+#define DCORE2_TPC_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE2_TPC_PLL_DIV_2_RLX_SECTION 0x2000
+#define mmDCORE2_TPC_PLL_DIV_3_RLX_BASE 0x4F62C00ull
+#define DCORE2_TPC_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE2_TPC_PLL_DIV_3_RLX_SECTION 0x2800
+#define mmDCORE2_TPC_PLL_SPECIAL_BASE 0x4F62E80ull
+#define DCORE2_TPC_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE2_TPC_PLL_SPECIAL_SECTION 0x2180
+#define mmDCORE2_TSTDVS_BASE 0x4F65000ull
+#define DCORE2_TSTDVS_MAX_OFFSET 0x7800
+#define DCORE2_TSTDVS_SECTION 0x1000
+#define mmDCORE2_TS_WRAP_BASE 0x4F66000ull
+#define DCORE2_TS_WRAP_MAX_OFFSET 0x2380
+#define DCORE2_TS_WRAP_SECTION 0x2000
+#define mmDCORE2_TS_WRAP_ASIF_SLV_BASE 0x4F66200ull
+#define DCORE2_TS_WRAP_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE2_TS_WRAP_ASIF_SLV_SECTION 0x9E00
+#define mmDCORE3_XFT_BASE 0x4F70000ull
+#define DCORE3_XFT_MAX_OFFSET 0x1000
+#define DCORE3_XFT_SECTION 0xE800
+#define mmDCORE3_XFT_SPECIAL_BASE 0x4F70E80ull
+#define DCORE3_XFT_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_XFT_SPECIAL_SECTION 0x1800
+#define mmDCORE3_HBM_PLL_CTRL_BASE 0x4F71000ull
+#define DCORE3_HBM_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE3_HBM_PLL_CTRL_SECTION 0x3600
+#define mmDCORE3_HBM_PLL_ASIF_SLV_BASE 0x4F71360ull
+#define DCORE3_HBM_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE3_HBM_PLL_ASIF_SLV_SECTION 0xA000
+#define mmDCORE3_HBM_PLL_DIV_0_RLX_BASE 0x4F71400ull
+#define DCORE3_HBM_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE3_HBM_PLL_DIV_0_RLX_SECTION 0x4000
+#define mmDCORE3_HBM_PLL_DIV_1_RLX_BASE 0x4F71800ull
+#define DCORE3_HBM_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE3_HBM_PLL_DIV_1_RLX_SECTION 0x2000
+#define mmDCORE3_HBM_PLL_DIV_2_RLX_BASE 0x4F71A00ull
+#define DCORE3_HBM_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE3_HBM_PLL_DIV_2_RLX_SECTION 0x2000
+#define mmDCORE3_HBM_PLL_DIV_3_RLX_BASE 0x4F71C00ull
+#define DCORE3_HBM_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE3_HBM_PLL_DIV_3_RLX_SECTION 0x2800
+#define mmDCORE3_HBM_PLL_SPECIAL_BASE 0x4F71E80ull
+#define DCORE3_HBM_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_HBM_PLL_SPECIAL_SECTION 0x1800
+#define mmDCORE3_TPC_PLL_CTRL_BASE 0x4F72000ull
+#define DCORE3_TPC_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE3_TPC_PLL_CTRL_SECTION 0x3600
+#define mmDCORE3_TPC_PLL_ASIF_SLV_BASE 0x4F72360ull
+#define DCORE3_TPC_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE3_TPC_PLL_ASIF_SLV_SECTION 0xA000
+#define mmDCORE3_TPC_PLL_DIV_0_RLX_BASE 0x4F72400ull
+#define DCORE3_TPC_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE3_TPC_PLL_DIV_0_RLX_SECTION 0x4000
+#define mmDCORE3_TPC_PLL_DIV_1_RLX_BASE 0x4F72800ull
+#define DCORE3_TPC_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE3_TPC_PLL_DIV_1_RLX_SECTION 0x2000
+#define mmDCORE3_TPC_PLL_DIV_2_RLX_BASE 0x4F72A00ull
+#define DCORE3_TPC_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE3_TPC_PLL_DIV_2_RLX_SECTION 0x2000
+#define mmDCORE3_TPC_PLL_DIV_3_RLX_BASE 0x4F72C00ull
+#define DCORE3_TPC_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE3_TPC_PLL_DIV_3_RLX_SECTION 0x2800
+#define mmDCORE3_TPC_PLL_SPECIAL_BASE 0x4F72E80ull
+#define DCORE3_TPC_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_TPC_PLL_SPECIAL_SECTION 0x1800
+#define mmDCORE3_NIC_PLL_CTRL_BASE 0x4F73000ull
+#define DCORE3_NIC_PLL_CTRL_MAX_OFFSET 0x3540
+#define DCORE3_NIC_PLL_CTRL_SECTION 0x3600
+#define mmDCORE3_NIC_PLL_ASIF_SLV_BASE 0x4F73360ull
+#define DCORE3_NIC_PLL_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE3_NIC_PLL_ASIF_SLV_SECTION 0xA000
+#define mmDCORE3_NIC_PLL_DIV_0_RLX_BASE 0x4F73400ull
+#define DCORE3_NIC_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
+#define DCORE3_NIC_PLL_DIV_0_RLX_SECTION 0x4000
+#define mmDCORE3_NIC_PLL_DIV_1_RLX_BASE 0x4F73800ull
+#define DCORE3_NIC_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
+#define DCORE3_NIC_PLL_DIV_1_RLX_SECTION 0x2000
+#define mmDCORE3_NIC_PLL_DIV_2_RLX_BASE 0x4F73A00ull
+#define DCORE3_NIC_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
+#define DCORE3_NIC_PLL_DIV_2_RLX_SECTION 0x2000
+#define mmDCORE3_NIC_PLL_DIV_3_RLX_BASE 0x4F73C00ull
+#define DCORE3_NIC_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
+#define DCORE3_NIC_PLL_DIV_3_RLX_SECTION 0x2800
+#define mmDCORE3_NIC_PLL_SPECIAL_BASE 0x4F73E80ull
+#define DCORE3_NIC_PLL_SPECIAL_MAX_OFFSET 0x1800
+#define DCORE3_NIC_PLL_SPECIAL_SECTION 0x1180
+#define mmDCORE3_TSTDVS_BASE 0x4F75000ull
+#define DCORE3_TSTDVS_MAX_OFFSET 0x7800
+#define DCORE3_TSTDVS_SECTION 0x1000
+#define mmDCORE3_TS_WRAP_BASE 0x4F76000ull
+#define DCORE3_TS_WRAP_MAX_OFFSET 0x2380
+#define DCORE3_TS_WRAP_SECTION 0x2000
+#define mmDCORE3_TS_WRAP_ASIF_SLV_BASE 0x4F76200ull
+#define DCORE3_TS_WRAP_ASIF_SLV_MAX_OFFSET 0x3800
+#define DCORE3_TS_WRAP_ASIF_SLV_SECTION 0x9E00
+#define mmPCIE_PMA_2_BASE 0x4F80000ull
+#define PCIE_PMA_2_MAX_OFFSET 0x40000
+#define PCIE_PMA_2_SECTION 0x40000
+#define mmPCIE_PMA_3_BASE 0x4FC0000ull
+#define PCIE_PMA_3_MAX_OFFSET 0x40000
+#define PCIE_PMA_3_SECTION 0x40000
+#define mmHBM0_MC0_BASE 0x5000000ull
+#define HBM0_MC0_MAX_OFFSET 0x1000
+#define HBM0_MC0_SECTION 0xE800
+#define mmHBM0_MC0_SPECIAL_BASE 0x5000E80ull
+#define HBM0_MC0_SPECIAL_MAX_OFFSET 0x1800
+#define HBM0_MC0_SPECIAL_SECTION 0x1800
+#define mmHBM0_MC0BIST0_BASE 0x5001000ull
+#define HBM0_MC0BIST0_MAX_OFFSET 0x1000
+#define HBM0_MC0BIST0_SECTION 0xE800
+#define mmHBM0_MC0BIST0_SPECIAL_BASE 0x5001E80ull
+#define HBM0_MC0BIST0_SPECIAL_MAX_OFFSET 0x1800
+#define HBM0_MC0BIST0_SPECIAL_SECTION 0x1800
+#define mmHBM0_MC0BIST1_BASE 0x5002000ull
+#define HBM0_MC0BIST1_MAX_OFFSET 0x1000
+#define HBM0_MC0BIST1_SECTION 0xE800
+#define mmHBM0_MC0BIST1_SPECIAL_BASE 0x5002E80ull
+#define HBM0_MC0BIST1_SPECIAL_MAX_OFFSET 0x1800
+#define HBM0_MC0BIST1_SPECIAL_SECTION 0x1800
+#define mmHBM0_MC0BIST2_BASE 0x5003000ull
+#define HBM0_MC0BIST2_MAX_OFFSET 0x1000
+#define HBM0_MC0BIST2_SECTION 0xE800
+#define mmHBM0_MC0BIST2_SPECIAL_BASE 0x5003E80ull
+#define HBM0_MC0BIST2_SPECIAL_MAX_OFFSET 0x1800
+#define HBM0_MC0BIST2_SPECIAL_SECTION 0x1800
+#define mmHBM0_MC0BIST3_BASE 0x5004000ull
+#define HBM0_MC0BIST3_MAX_OFFSET 0x1000
+#define HBM0_MC0BIST3_SECTION 0xE800
+#define mmHBM0_MC0BIST3_SPECIAL_BASE 0x5004E80ull
+#define HBM0_MC0BIST3_SPECIAL_MAX_OFFSET 0x1800
+#define HBM0_MC0BIST3_SPECIAL_SECTION 0x1800
+#define mmHBM0_MC0BIST4_BASE 0x5005000ull
+#define HBM0_MC0BIST4_MAX_OFFSET 0x1000
+#define HBM0_MC0BIST4_SECTION 0xE800
+#define mmHBM0_MC0BIST4_SPECIAL_BASE 0x5005E80ull
+#define HBM0_MC0BIST4_SPECIAL_MAX_OFFSET 0x1800
+#define HBM0_MC0BIST4_SPECIAL_SECTION 0x1800
+#define mmHBM0_MC0BIST5_BASE 0x5006000ull
+#define HBM0_MC0BIST5_MAX_OFFSET 0x1000
+#define HBM0_MC0BIST5_SECTION 0xE800
+#define mmHBM0_MC0BIST5_SPECIAL_BASE 0x5006E80ull
+#define HBM0_MC0BIST5_SPECIAL_MAX_OFFSET 0x1800
+#define HBM0_MC0BIST5_SPECIAL_SECTION 0x1800
+#define mmHBM0_MC0BIST6_BASE 0x5007000ull
+#define HBM0_MC0BIST6_MAX_OFFSET 0x1000
+#define HBM0_MC0BIST6_SECTION 0xE800
+#define mmHBM0_MC0BIST6_SPECIAL_BASE 0x5007E80ull
+#define HBM0_MC0BIST6_SPECIAL_MAX_OFFSET 0x1800
+#define HBM0_MC0BIST6_SPECIAL_SECTION 0x1800
+#define mmHBM0_MC0BIST7_BASE 0x5008000ull
+#define HBM0_MC0BIST7_MAX_OFFSET 0x1000
+#define HBM0_MC0BIST7_SECTION 0xE800
+#define mmHBM0_MC0BIST7_SPECIAL_BASE 0x5008E80ull
+#define HBM0_MC0BIST7_SPECIAL_MAX_OFFSET 0x1800
+#define HBM0_MC0BIST7_SPECIAL_SECTION 0x1800
+#define mmHBM0_MC0BIST8_MEM_BASE 0x5009000ull
+#define HBM0_MC0BIST8_MEM_MAX_OFFSET 0x1000
+#define HBM0_MC0BIST8_MEM_SECTION 0xE800
+#define mmHBM0_MC0BIST8_MEM_SPECIAL_BASE 0x5009E80ull
+#define HBM0_MC0BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800
+#define HBM0_MC0BIST8_MEM_SPECIAL_SECTION 0x16180
+#define mmHBM0_MC1_BASE 0x5020000ull
+#define HBM0_MC1_MAX_OFFSET 0x1000
+#define HBM0_MC1_SECTION 0xE800
+#define mmHBM0_MC1_SPECIAL_BASE 0x5020E80ull
+#define HBM0_MC1_SPECIAL_MAX_OFFSET 0x1800
+#define HBM0_MC1_SPECIAL_SECTION 0x1800
+#define mmHBM0_MC1BIST0_BASE 0x5021000ull
+#define HBM0_MC1BIST0_MAX_OFFSET 0x1000
+#define HBM0_MC1BIST0_SECTION 0xE800
+#define mmHBM0_MC1BIST0_SPECIAL_BASE 0x5021E80ull
+#define HBM0_MC1BIST0_SPECIAL_MAX_OFFSET 0x1800
+#define HBM0_MC1BIST0_SPECIAL_SECTION 0x1800
+#define mmHBM0_MC1BIST1_BASE 0x5022000ull
+#define HBM0_MC1BIST1_MAX_OFFSET 0x1000
+#define HBM0_MC1BIST1_SECTION 0xE800
+#define mmHBM0_MC1BIST1_SPECIAL_BASE 0x5022E80ull
+#define HBM0_MC1BIST1_SPECIAL_MAX_OFFSET 0x1800
+#define HBM0_MC1BIST1_SPECIAL_SECTION 0x1800
+#define mmHBM0_MC1BIST2_BASE 0x5023000ull
+#define HBM0_MC1BIST2_MAX_OFFSET 0x1000
+#define HBM0_MC1BIST2_SECTION 0xE800
+#define mmHBM0_MC1BIST2_SPECIAL_BASE 0x5023E80ull
+#define HBM0_MC1BIST2_SPECIAL_MAX_OFFSET 0x1800
+#define HBM0_MC1BIST2_SPECIAL_SECTION 0x1800
+#define mmHBM0_MC1BIST3_BASE 0x5024000ull
+#define HBM0_MC1BIST3_MAX_OFFSET 0x1000
+#define HBM0_MC1BIST3_SECTION 0xE800
+#define mmHBM0_MC1BIST3_SPECIAL_BASE 0x5024E80ull
+#define HBM0_MC1BIST3_SPECIAL_MAX_OFFSET 0x1800
+#define HBM0_MC1BIST3_SPECIAL_SECTION 0x1800
+#define mmHBM0_MC1BIST4_BASE 0x5025000ull
+#define HBM0_MC1BIST4_MAX_OFFSET 0x1000
+#define HBM0_MC1BIST4_SECTION 0xE800
+#define mmHBM0_MC1BIST4_SPECIAL_BASE 0x5025E80ull
+#define HBM0_MC1BIST4_SPECIAL_MAX_OFFSET 0x1800
+#define HBM0_MC1BIST4_SPECIAL_SECTION 0x1800
+#define mmHBM0_MC1BIST5_BASE 0x5026000ull
+#define HBM0_MC1BIST5_MAX_OFFSET 0x1000
+#define HBM0_MC1BIST5_SECTION 0xE800
+#define mmHBM0_MC1BIST5_SPECIAL_BASE 0x5026E80ull
+#define HBM0_MC1BIST5_SPECIAL_MAX_OFFSET 0x1800
+#define HBM0_MC1BIST5_SPECIAL_SECTION 0x1800
+#define mmHBM0_MC1BIST6_BASE 0x5027000ull
+#define HBM0_MC1BIST6_MAX_OFFSET 0x1000
+#define HBM0_MC1BIST6_SECTION 0xE800
+#define mmHBM0_MC1BIST6_SPECIAL_BASE 0x5027E80ull
+#define HBM0_MC1BIST6_SPECIAL_MAX_OFFSET 0x1800
+#define HBM0_MC1BIST6_SPECIAL_SECTION 0x1800
+#define mmHBM0_MC1BIST7_BASE 0x5028000ull
+#define HBM0_MC1BIST7_MAX_OFFSET 0x1000
+#define HBM0_MC1BIST7_SECTION 0xE800
+#define mmHBM0_MC1BIST7_SPECIAL_BASE 0x5028E80ull
+#define HBM0_MC1BIST7_SPECIAL_MAX_OFFSET 0x1800
+#define HBM0_MC1BIST7_SPECIAL_SECTION 0x1800
+#define mmHBM0_MC1BIST8_MEM_BASE 0x5029000ull
+#define HBM0_MC1BIST8_MEM_MAX_OFFSET 0x1000
+#define HBM0_MC1BIST8_MEM_SECTION 0xE800
+#define mmHBM0_MC1BIST8_MEM_SPECIAL_BASE 0x5029E80ull
+#define HBM0_MC1BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800
+#define HBM0_MC1BIST8_MEM_SPECIAL_SECTION 0x16180
+#define mmHBM0_PHY_BASE 0x5040000ull
+#define HBM0_PHY_MAX_OFFSET 0x4000
+#define HBM0_PHY_SECTION 0x40000
+#define mmHBM1_MC0_BASE 0x5080000ull
+#define HBM1_MC0_MAX_OFFSET 0x1000
+#define HBM1_MC0_SECTION 0xE800
+#define mmHBM1_MC0_SPECIAL_BASE 0x5080E80ull
+#define HBM1_MC0_SPECIAL_MAX_OFFSET 0x1800
+#define HBM1_MC0_SPECIAL_SECTION 0x1800
+#define mmHBM1_MC0BIST0_BASE 0x5081000ull
+#define HBM1_MC0BIST0_MAX_OFFSET 0x1000
+#define HBM1_MC0BIST0_SECTION 0xE800
+#define mmHBM1_MC0BIST0_SPECIAL_BASE 0x5081E80ull
+#define HBM1_MC0BIST0_SPECIAL_MAX_OFFSET 0x1800
+#define HBM1_MC0BIST0_SPECIAL_SECTION 0x1800
+#define mmHBM1_MC0BIST1_BASE 0x5082000ull
+#define HBM1_MC0BIST1_MAX_OFFSET 0x1000
+#define HBM1_MC0BIST1_SECTION 0xE800
+#define mmHBM1_MC0BIST1_SPECIAL_BASE 0x5082E80ull
+#define HBM1_MC0BIST1_SPECIAL_MAX_OFFSET 0x1800
+#define HBM1_MC0BIST1_SPECIAL_SECTION 0x1800
+#define mmHBM1_MC0BIST2_BASE 0x5083000ull
+#define HBM1_MC0BIST2_MAX_OFFSET 0x1000
+#define HBM1_MC0BIST2_SECTION 0xE800
+#define mmHBM1_MC0BIST2_SPECIAL_BASE 0x5083E80ull
+#define HBM1_MC0BIST2_SPECIAL_MAX_OFFSET 0x1800
+#define HBM1_MC0BIST2_SPECIAL_SECTION 0x1800
+#define mmHBM1_MC0BIST3_BASE 0x5084000ull
+#define HBM1_MC0BIST3_MAX_OFFSET 0x1000
+#define HBM1_MC0BIST3_SECTION 0xE800
+#define mmHBM1_MC0BIST3_SPECIAL_BASE 0x5084E80ull
+#define HBM1_MC0BIST3_SPECIAL_MAX_OFFSET 0x1800
+#define HBM1_MC0BIST3_SPECIAL_SECTION 0x1800
+#define mmHBM1_MC0BIST4_BASE 0x5085000ull
+#define HBM1_MC0BIST4_MAX_OFFSET 0x1000
+#define HBM1_MC0BIST4_SECTION 0xE800
+#define mmHBM1_MC0BIST4_SPECIAL_BASE 0x5085E80ull
+#define HBM1_MC0BIST4_SPECIAL_MAX_OFFSET 0x1800
+#define HBM1_MC0BIST4_SPECIAL_SECTION 0x1800
+#define mmHBM1_MC0BIST5_BASE 0x5086000ull
+#define HBM1_MC0BIST5_MAX_OFFSET 0x1000
+#define HBM1_MC0BIST5_SECTION 0xE800
+#define mmHBM1_MC0BIST5_SPECIAL_BASE 0x5086E80ull
+#define HBM1_MC0BIST5_SPECIAL_MAX_OFFSET 0x1800
+#define HBM1_MC0BIST5_SPECIAL_SECTION 0x1800
+#define mmHBM1_MC0BIST6_BASE 0x5087000ull
+#define HBM1_MC0BIST6_MAX_OFFSET 0x1000
+#define HBM1_MC0BIST6_SECTION 0xE800
+#define mmHBM1_MC0BIST6_SPECIAL_BASE 0x5087E80ull
+#define HBM1_MC0BIST6_SPECIAL_MAX_OFFSET 0x1800
+#define HBM1_MC0BIST6_SPECIAL_SECTION 0x1800
+#define mmHBM1_MC0BIST7_BASE 0x5088000ull
+#define HBM1_MC0BIST7_MAX_OFFSET 0x1000
+#define HBM1_MC0BIST7_SECTION 0xE800
+#define mmHBM1_MC0BIST7_SPECIAL_BASE 0x5088E80ull
+#define HBM1_MC0BIST7_SPECIAL_MAX_OFFSET 0x1800
+#define HBM1_MC0BIST7_SPECIAL_SECTION 0x1800
+#define mmHBM1_MC0BIST8_MEM_BASE 0x5089000ull
+#define HBM1_MC0BIST8_MEM_MAX_OFFSET 0x1000
+#define HBM1_MC0BIST8_MEM_SECTION 0xE800
+#define mmHBM1_MC0BIST8_MEM_SPECIAL_BASE 0x5089E80ull
+#define HBM1_MC0BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800
+#define HBM1_MC0BIST8_MEM_SPECIAL_SECTION 0x16180
+#define mmHBM1_MC1_BASE 0x50A0000ull
+#define HBM1_MC1_MAX_OFFSET 0x1000
+#define HBM1_MC1_SECTION 0xE800
+#define mmHBM1_MC1_SPECIAL_BASE 0x50A0E80ull
+#define HBM1_MC1_SPECIAL_MAX_OFFSET 0x1800
+#define HBM1_MC1_SPECIAL_SECTION 0x1800
+#define mmHBM1_MC1BIST0_BASE 0x50A1000ull
+#define HBM1_MC1BIST0_MAX_OFFSET 0x1000
+#define HBM1_MC1BIST0_SECTION 0xE800
+#define mmHBM1_MC1BIST0_SPECIAL_BASE 0x50A1E80ull
+#define HBM1_MC1BIST0_SPECIAL_MAX_OFFSET 0x1800
+#define HBM1_MC1BIST0_SPECIAL_SECTION 0x1800
+#define mmHBM1_MC1BIST1_BASE 0x50A2000ull
+#define HBM1_MC1BIST1_MAX_OFFSET 0x1000
+#define HBM1_MC1BIST1_SECTION 0xE800
+#define mmHBM1_MC1BIST1_SPECIAL_BASE 0x50A2E80ull
+#define HBM1_MC1BIST1_SPECIAL_MAX_OFFSET 0x1800
+#define HBM1_MC1BIST1_SPECIAL_SECTION 0x1800
+#define mmHBM1_MC1BIST2_BASE 0x50A3000ull
+#define HBM1_MC1BIST2_MAX_OFFSET 0x1000
+#define HBM1_MC1BIST2_SECTION 0xE800
+#define mmHBM1_MC1BIST2_SPECIAL_BASE 0x50A3E80ull
+#define HBM1_MC1BIST2_SPECIAL_MAX_OFFSET 0x1800
+#define HBM1_MC1BIST2_SPECIAL_SECTION 0x1800
+#define mmHBM1_MC1BIST3_BASE 0x50A4000ull
+#define HBM1_MC1BIST3_MAX_OFFSET 0x1000
+#define HBM1_MC1BIST3_SECTION 0xE800
+#define mmHBM1_MC1BIST3_SPECIAL_BASE 0x50A4E80ull
+#define HBM1_MC1BIST3_SPECIAL_MAX_OFFSET 0x1800
+#define HBM1_MC1BIST3_SPECIAL_SECTION 0x1800
+#define mmHBM1_MC1BIST4_BASE 0x50A5000ull
+#define HBM1_MC1BIST4_MAX_OFFSET 0x1000
+#define HBM1_MC1BIST4_SECTION 0xE800
+#define mmHBM1_MC1BIST4_SPECIAL_BASE 0x50A5E80ull
+#define HBM1_MC1BIST4_SPECIAL_MAX_OFFSET 0x1800
+#define HBM1_MC1BIST4_SPECIAL_SECTION 0x1800
+#define mmHBM1_MC1BIST5_BASE 0x50A6000ull
+#define HBM1_MC1BIST5_MAX_OFFSET 0x1000
+#define HBM1_MC1BIST5_SECTION 0xE800
+#define mmHBM1_MC1BIST5_SPECIAL_BASE 0x50A6E80ull
+#define HBM1_MC1BIST5_SPECIAL_MAX_OFFSET 0x1800
+#define HBM1_MC1BIST5_SPECIAL_SECTION 0x1800
+#define mmHBM1_MC1BIST6_BASE 0x50A7000ull
+#define HBM1_MC1BIST6_MAX_OFFSET 0x1000
+#define HBM1_MC1BIST6_SECTION 0xE800
+#define mmHBM1_MC1BIST6_SPECIAL_BASE 0x50A7E80ull
+#define HBM1_MC1BIST6_SPECIAL_MAX_OFFSET 0x1800
+#define HBM1_MC1BIST6_SPECIAL_SECTION 0x1800
+#define mmHBM1_MC1BIST7_BASE 0x50A8000ull
+#define HBM1_MC1BIST7_MAX_OFFSET 0x1000
+#define HBM1_MC1BIST7_SECTION 0xE800
+#define mmHBM1_MC1BIST7_SPECIAL_BASE 0x50A8E80ull
+#define HBM1_MC1BIST7_SPECIAL_MAX_OFFSET 0x1800
+#define HBM1_MC1BIST7_SPECIAL_SECTION 0x1800
+#define mmHBM1_MC1BIST8_MEM_BASE 0x50A9000ull
+#define HBM1_MC1BIST8_MEM_MAX_OFFSET 0x1000
+#define HBM1_MC1BIST8_MEM_SECTION 0xE800
+#define mmHBM1_MC1BIST8_MEM_SPECIAL_BASE 0x50A9E80ull
+#define HBM1_MC1BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800
+#define HBM1_MC1BIST8_MEM_SPECIAL_SECTION 0x16180
+#define mmHBM1_PHY_BASE 0x50C0000ull
+#define HBM1_PHY_MAX_OFFSET 0x4000
+#define HBM1_PHY_SECTION 0x40000
+#define mmHBM2_MC0_BASE 0x5100000ull
+#define HBM2_MC0_MAX_OFFSET 0x1000
+#define HBM2_MC0_SECTION 0xE800
+#define mmHBM2_MC0_SPECIAL_BASE 0x5100E80ull
+#define HBM2_MC0_SPECIAL_MAX_OFFSET 0x1800
+#define HBM2_MC0_SPECIAL_SECTION 0x1800
+#define mmHBM2_MC0BIST0_BASE 0x5101000ull
+#define HBM2_MC0BIST0_MAX_OFFSET 0x1000
+#define HBM2_MC0BIST0_SECTION 0xE800
+#define mmHBM2_MC0BIST0_SPECIAL_BASE 0x5101E80ull
+#define HBM2_MC0BIST0_SPECIAL_MAX_OFFSET 0x1800
+#define HBM2_MC0BIST0_SPECIAL_SECTION 0x1800
+#define mmHBM2_MC0BIST1_BASE 0x5102000ull
+#define HBM2_MC0BIST1_MAX_OFFSET 0x1000
+#define HBM2_MC0BIST1_SECTION 0xE800
+#define mmHBM2_MC0BIST1_SPECIAL_BASE 0x5102E80ull
+#define HBM2_MC0BIST1_SPECIAL_MAX_OFFSET 0x1800
+#define HBM2_MC0BIST1_SPECIAL_SECTION 0x1800
+#define mmHBM2_MC0BIST2_BASE 0x5103000ull
+#define HBM2_MC0BIST2_MAX_OFFSET 0x1000
+#define HBM2_MC0BIST2_SECTION 0xE800
+#define mmHBM2_MC0BIST2_SPECIAL_BASE 0x5103E80ull
+#define HBM2_MC0BIST2_SPECIAL_MAX_OFFSET 0x1800
+#define HBM2_MC0BIST2_SPECIAL_SECTION 0x1800
+#define mmHBM2_MC0BIST3_BASE 0x5104000ull
+#define HBM2_MC0BIST3_MAX_OFFSET 0x1000
+#define HBM2_MC0BIST3_SECTION 0xE800
+#define mmHBM2_MC0BIST3_SPECIAL_BASE 0x5104E80ull
+#define HBM2_MC0BIST3_SPECIAL_MAX_OFFSET 0x1800
+#define HBM2_MC0BIST3_SPECIAL_SECTION 0x1800
+#define mmHBM2_MC0BIST4_BASE 0x5105000ull
+#define HBM2_MC0BIST4_MAX_OFFSET 0x1000
+#define HBM2_MC0BIST4_SECTION 0xE800
+#define mmHBM2_MC0BIST4_SPECIAL_BASE 0x5105E80ull
+#define HBM2_MC0BIST4_SPECIAL_MAX_OFFSET 0x1800
+#define HBM2_MC0BIST4_SPECIAL_SECTION 0x1800
+#define mmHBM2_MC0BIST5_BASE 0x5106000ull
+#define HBM2_MC0BIST5_MAX_OFFSET 0x1000
+#define HBM2_MC0BIST5_SECTION 0xE800
+#define mmHBM2_MC0BIST5_SPECIAL_BASE 0x5106E80ull
+#define HBM2_MC0BIST5_SPECIAL_MAX_OFFSET 0x1800
+#define HBM2_MC0BIST5_SPECIAL_SECTION 0x1800
+#define mmHBM2_MC0BIST6_BASE 0x5107000ull
+#define HBM2_MC0BIST6_MAX_OFFSET 0x1000
+#define HBM2_MC0BIST6_SECTION 0xE800
+#define mmHBM2_MC0BIST6_SPECIAL_BASE 0x5107E80ull
+#define HBM2_MC0BIST6_SPECIAL_MAX_OFFSET 0x1800
+#define HBM2_MC0BIST6_SPECIAL_SECTION 0x1800
+#define mmHBM2_MC0BIST7_BASE 0x5108000ull
+#define HBM2_MC0BIST7_MAX_OFFSET 0x1000
+#define HBM2_MC0BIST7_SECTION 0xE800
+#define mmHBM2_MC0BIST7_SPECIAL_BASE 0x5108E80ull
+#define HBM2_MC0BIST7_SPECIAL_MAX_OFFSET 0x1800
+#define HBM2_MC0BIST7_SPECIAL_SECTION 0x1800
+#define mmHBM2_MC0BIST8_MEM_BASE 0x5109000ull
+#define HBM2_MC0BIST8_MEM_MAX_OFFSET 0x1000
+#define HBM2_MC0BIST8_MEM_SECTION 0xE800
+#define mmHBM2_MC0BIST8_MEM_SPECIAL_BASE 0x5109E80ull
+#define HBM2_MC0BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800
+#define HBM2_MC0BIST8_MEM_SPECIAL_SECTION 0x16180
+#define mmHBM2_MC1_BASE 0x5120000ull
+#define HBM2_MC1_MAX_OFFSET 0x1000
+#define HBM2_MC1_SECTION 0xE800
+#define mmHBM2_MC1_SPECIAL_BASE 0x5120E80ull
+#define HBM2_MC1_SPECIAL_MAX_OFFSET 0x1800
+#define HBM2_MC1_SPECIAL_SECTION 0x1800
+#define mmHBM2_MC1BIST0_BASE 0x5121000ull
+#define HBM2_MC1BIST0_MAX_OFFSET 0x1000
+#define HBM2_MC1BIST0_SECTION 0xE800
+#define mmHBM2_MC1BIST0_SPECIAL_BASE 0x5121E80ull
+#define HBM2_MC1BIST0_SPECIAL_MAX_OFFSET 0x1800
+#define HBM2_MC1BIST0_SPECIAL_SECTION 0x1800
+#define mmHBM2_MC1BIST1_BASE 0x5122000ull
+#define HBM2_MC1BIST1_MAX_OFFSET 0x1000
+#define HBM2_MC1BIST1_SECTION 0xE800
+#define mmHBM2_MC1BIST1_SPECIAL_BASE 0x5122E80ull
+#define HBM2_MC1BIST1_SPECIAL_MAX_OFFSET 0x1800
+#define HBM2_MC1BIST1_SPECIAL_SECTION 0x1800
+#define mmHBM2_MC1BIST2_BASE 0x5123000ull
+#define HBM2_MC1BIST2_MAX_OFFSET 0x1000
+#define HBM2_MC1BIST2_SECTION 0xE800
+#define mmHBM2_MC1BIST2_SPECIAL_BASE 0x5123E80ull
+#define HBM2_MC1BIST2_SPECIAL_MAX_OFFSET 0x1800
+#define HBM2_MC1BIST2_SPECIAL_SECTION 0x1800
+#define mmHBM2_MC1BIST3_BASE 0x5124000ull
+#define HBM2_MC1BIST3_MAX_OFFSET 0x1000
+#define HBM2_MC1BIST3_SECTION 0xE800
+#define mmHBM2_MC1BIST3_SPECIAL_BASE 0x5124E80ull
+#define HBM2_MC1BIST3_SPECIAL_MAX_OFFSET 0x1800
+#define HBM2_MC1BIST3_SPECIAL_SECTION 0x1800
+#define mmHBM2_MC1BIST4_BASE 0x5125000ull
+#define HBM2_MC1BIST4_MAX_OFFSET 0x1000
+#define HBM2_MC1BIST4_SECTION 0xE800
+#define mmHBM2_MC1BIST4_SPECIAL_BASE 0x5125E80ull
+#define HBM2_MC1BIST4_SPECIAL_MAX_OFFSET 0x1800
+#define HBM2_MC1BIST4_SPECIAL_SECTION 0x1800
+#define mmHBM2_MC1BIST5_BASE 0x5126000ull
+#define HBM2_MC1BIST5_MAX_OFFSET 0x1000
+#define HBM2_MC1BIST5_SECTION 0xE800
+#define mmHBM2_MC1BIST5_SPECIAL_BASE 0x5126E80ull
+#define HBM2_MC1BIST5_SPECIAL_MAX_OFFSET 0x1800
+#define HBM2_MC1BIST5_SPECIAL_SECTION 0x1800
+#define mmHBM2_MC1BIST6_BASE 0x5127000ull
+#define HBM2_MC1BIST6_MAX_OFFSET 0x1000
+#define HBM2_MC1BIST6_SECTION 0xE800
+#define mmHBM2_MC1BIST6_SPECIAL_BASE 0x5127E80ull
+#define HBM2_MC1BIST6_SPECIAL_MAX_OFFSET 0x1800
+#define HBM2_MC1BIST6_SPECIAL_SECTION 0x1800
+#define mmHBM2_MC1BIST7_BASE 0x5128000ull
+#define HBM2_MC1BIST7_MAX_OFFSET 0x1000
+#define HBM2_MC1BIST7_SECTION 0xE800
+#define mmHBM2_MC1BIST7_SPECIAL_BASE 0x5128E80ull
+#define HBM2_MC1BIST7_SPECIAL_MAX_OFFSET 0x1800
+#define HBM2_MC1BIST7_SPECIAL_SECTION 0x1800
+#define mmHBM2_MC1BIST8_MEM_BASE 0x5129000ull
+#define HBM2_MC1BIST8_MEM_MAX_OFFSET 0x1000
+#define HBM2_MC1BIST8_MEM_SECTION 0xE800
+#define mmHBM2_MC1BIST8_MEM_SPECIAL_BASE 0x5129E80ull
+#define HBM2_MC1BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800
+#define HBM2_MC1BIST8_MEM_SPECIAL_SECTION 0x16180
+#define mmHBM2_PHY_BASE 0x5140000ull
+#define HBM2_PHY_MAX_OFFSET 0x4000
+#define HBM2_PHY_SECTION 0x40000
+#define mmHBM3_MC0_BASE 0x5180000ull
+#define HBM3_MC0_MAX_OFFSET 0x1000
+#define HBM3_MC0_SECTION 0xE800
+#define mmHBM3_MC0_SPECIAL_BASE 0x5180E80ull
+#define HBM3_MC0_SPECIAL_MAX_OFFSET 0x1800
+#define HBM3_MC0_SPECIAL_SECTION 0x1800
+#define mmHBM3_MC0BIST0_BASE 0x5181000ull
+#define HBM3_MC0BIST0_MAX_OFFSET 0x1000
+#define HBM3_MC0BIST0_SECTION 0xE800
+#define mmHBM3_MC0BIST0_SPECIAL_BASE 0x5181E80ull
+#define HBM3_MC0BIST0_SPECIAL_MAX_OFFSET 0x1800
+#define HBM3_MC0BIST0_SPECIAL_SECTION 0x1800
+#define mmHBM3_MC0BIST1_BASE 0x5182000ull
+#define HBM3_MC0BIST1_MAX_OFFSET 0x1000
+#define HBM3_MC0BIST1_SECTION 0xE800
+#define mmHBM3_MC0BIST1_SPECIAL_BASE 0x5182E80ull
+#define HBM3_MC0BIST1_SPECIAL_MAX_OFFSET 0x1800
+#define HBM3_MC0BIST1_SPECIAL_SECTION 0x1800
+#define mmHBM3_MC0BIST2_BASE 0x5183000ull
+#define HBM3_MC0BIST2_MAX_OFFSET 0x1000
+#define HBM3_MC0BIST2_SECTION 0xE800
+#define mmHBM3_MC0BIST2_SPECIAL_BASE 0x5183E80ull
+#define HBM3_MC0BIST2_SPECIAL_MAX_OFFSET 0x1800
+#define HBM3_MC0BIST2_SPECIAL_SECTION 0x1800
+#define mmHBM3_MC0BIST3_BASE 0x5184000ull
+#define HBM3_MC0BIST3_MAX_OFFSET 0x1000
+#define HBM3_MC0BIST3_SECTION 0xE800
+#define mmHBM3_MC0BIST3_SPECIAL_BASE 0x5184E80ull
+#define HBM3_MC0BIST3_SPECIAL_MAX_OFFSET 0x1800
+#define HBM3_MC0BIST3_SPECIAL_SECTION 0x1800
+#define mmHBM3_MC0BIST4_BASE 0x5185000ull
+#define HBM3_MC0BIST4_MAX_OFFSET 0x1000
+#define HBM3_MC0BIST4_SECTION 0xE800
+#define mmHBM3_MC0BIST4_SPECIAL_BASE 0x5185E80ull
+#define HBM3_MC0BIST4_SPECIAL_MAX_OFFSET 0x1800
+#define HBM3_MC0BIST4_SPECIAL_SECTION 0x1800
+#define mmHBM3_MC0BIST5_BASE 0x5186000ull
+#define HBM3_MC0BIST5_MAX_OFFSET 0x1000
+#define HBM3_MC0BIST5_SECTION 0xE800
+#define mmHBM3_MC0BIST5_SPECIAL_BASE 0x5186E80ull
+#define HBM3_MC0BIST5_SPECIAL_MAX_OFFSET 0x1800
+#define HBM3_MC0BIST5_SPECIAL_SECTION 0x1800
+#define mmHBM3_MC0BIST6_BASE 0x5187000ull
+#define HBM3_MC0BIST6_MAX_OFFSET 0x1000
+#define HBM3_MC0BIST6_SECTION 0xE800
+#define mmHBM3_MC0BIST6_SPECIAL_BASE 0x5187E80ull
+#define HBM3_MC0BIST6_SPECIAL_MAX_OFFSET 0x1800
+#define HBM3_MC0BIST6_SPECIAL_SECTION 0x1800
+#define mmHBM3_MC0BIST7_BASE 0x5188000ull
+#define HBM3_MC0BIST7_MAX_OFFSET 0x1000
+#define HBM3_MC0BIST7_SECTION 0xE800
+#define mmHBM3_MC0BIST7_SPECIAL_BASE 0x5188E80ull
+#define HBM3_MC0BIST7_SPECIAL_MAX_OFFSET 0x1800
+#define HBM3_MC0BIST7_SPECIAL_SECTION 0x1800
+#define mmHBM3_MC0BIST8_MEM_BASE 0x5189000ull
+#define HBM3_MC0BIST8_MEM_MAX_OFFSET 0x1000
+#define HBM3_MC0BIST8_MEM_SECTION 0xE800
+#define mmHBM3_MC0BIST8_MEM_SPECIAL_BASE 0x5189E80ull
+#define HBM3_MC0BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800
+#define HBM3_MC0BIST8_MEM_SPECIAL_SECTION 0x16180
+#define mmHBM3_MC1_BASE 0x51A0000ull
+#define HBM3_MC1_MAX_OFFSET 0x1000
+#define HBM3_MC1_SECTION 0xE800
+#define mmHBM3_MC1_SPECIAL_BASE 0x51A0E80ull
+#define HBM3_MC1_SPECIAL_MAX_OFFSET 0x1800
+#define HBM3_MC1_SPECIAL_SECTION 0x1800
+#define mmHBM3_MC1BIST0_BASE 0x51A1000ull
+#define HBM3_MC1BIST0_MAX_OFFSET 0x1000
+#define HBM3_MC1BIST0_SECTION 0xE800
+#define mmHBM3_MC1BIST0_SPECIAL_BASE 0x51A1E80ull
+#define HBM3_MC1BIST0_SPECIAL_MAX_OFFSET 0x1800
+#define HBM3_MC1BIST0_SPECIAL_SECTION 0x1800
+#define mmHBM3_MC1BIST1_BASE 0x51A2000ull
+#define HBM3_MC1BIST1_MAX_OFFSET 0x1000
+#define HBM3_MC1BIST1_SECTION 0xE800
+#define mmHBM3_MC1BIST1_SPECIAL_BASE 0x51A2E80ull
+#define HBM3_MC1BIST1_SPECIAL_MAX_OFFSET 0x1800
+#define HBM3_MC1BIST1_SPECIAL_SECTION 0x1800
+#define mmHBM3_MC1BIST2_BASE 0x51A3000ull
+#define HBM3_MC1BIST2_MAX_OFFSET 0x1000
+#define HBM3_MC1BIST2_SECTION 0xE800
+#define mmHBM3_MC1BIST2_SPECIAL_BASE 0x51A3E80ull
+#define HBM3_MC1BIST2_SPECIAL_MAX_OFFSET 0x1800
+#define HBM3_MC1BIST2_SPECIAL_SECTION 0x1800
+#define mmHBM3_MC1BIST3_BASE 0x51A4000ull
+#define HBM3_MC1BIST3_MAX_OFFSET 0x1000
+#define HBM3_MC1BIST3_SECTION 0xE800
+#define mmHBM3_MC1BIST3_SPECIAL_BASE 0x51A4E80ull
+#define HBM3_MC1BIST3_SPECIAL_MAX_OFFSET 0x1800
+#define HBM3_MC1BIST3_SPECIAL_SECTION 0x1800
+#define mmHBM3_MC1BIST4_BASE 0x51A5000ull
+#define HBM3_MC1BIST4_MAX_OFFSET 0x1000
+#define HBM3_MC1BIST4_SECTION 0xE800
+#define mmHBM3_MC1BIST4_SPECIAL_BASE 0x51A5E80ull
+#define HBM3_MC1BIST4_SPECIAL_MAX_OFFSET 0x1800
+#define HBM3_MC1BIST4_SPECIAL_SECTION 0x1800
+#define mmHBM3_MC1BIST5_BASE 0x51A6000ull
+#define HBM3_MC1BIST5_MAX_OFFSET 0x1000
+#define HBM3_MC1BIST5_SECTION 0xE800
+#define mmHBM3_MC1BIST5_SPECIAL_BASE 0x51A6E80ull
+#define HBM3_MC1BIST5_SPECIAL_MAX_OFFSET 0x1800
+#define HBM3_MC1BIST5_SPECIAL_SECTION 0x1800
+#define mmHBM3_MC1BIST6_BASE 0x51A7000ull
+#define HBM3_MC1BIST6_MAX_OFFSET 0x1000
+#define HBM3_MC1BIST6_SECTION 0xE800
+#define mmHBM3_MC1BIST6_SPECIAL_BASE 0x51A7E80ull
+#define HBM3_MC1BIST6_SPECIAL_MAX_OFFSET 0x1800
+#define HBM3_MC1BIST6_SPECIAL_SECTION 0x1800
+#define mmHBM3_MC1BIST7_BASE 0x51A8000ull
+#define HBM3_MC1BIST7_MAX_OFFSET 0x1000
+#define HBM3_MC1BIST7_SECTION 0xE800
+#define mmHBM3_MC1BIST7_SPECIAL_BASE 0x51A8E80ull
+#define HBM3_MC1BIST7_SPECIAL_MAX_OFFSET 0x1800
+#define HBM3_MC1BIST7_SPECIAL_SECTION 0x1800
+#define mmHBM3_MC1BIST8_MEM_BASE 0x51A9000ull
+#define HBM3_MC1BIST8_MEM_MAX_OFFSET 0x1000
+#define HBM3_MC1BIST8_MEM_SECTION 0xE800
+#define mmHBM3_MC1BIST8_MEM_SPECIAL_BASE 0x51A9E80ull
+#define HBM3_MC1BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800
+#define HBM3_MC1BIST8_MEM_SPECIAL_SECTION 0x16180
+#define mmHBM3_PHY_BASE 0x51C0000ull
+#define HBM3_PHY_MAX_OFFSET 0x4000
+#define HBM3_PHY_SECTION 0x40000
+#define mmHBM4_MC0_BASE 0x5200000ull
+#define HBM4_MC0_MAX_OFFSET 0x1000
+#define HBM4_MC0_SECTION 0xE800
+#define mmHBM4_MC0_SPECIAL_BASE 0x5200E80ull
+#define HBM4_MC0_SPECIAL_MAX_OFFSET 0x1800
+#define HBM4_MC0_SPECIAL_SECTION 0x1800
+#define mmHBM4_MC0BIST0_BASE 0x5201000ull
+#define HBM4_MC0BIST0_MAX_OFFSET 0x1000
+#define HBM4_MC0BIST0_SECTION 0xE800
+#define mmHBM4_MC0BIST0_SPECIAL_BASE 0x5201E80ull
+#define HBM4_MC0BIST0_SPECIAL_MAX_OFFSET 0x1800
+#define HBM4_MC0BIST0_SPECIAL_SECTION 0x1800
+#define mmHBM4_MC0BIST1_BASE 0x5202000ull
+#define HBM4_MC0BIST1_MAX_OFFSET 0x1000
+#define HBM4_MC0BIST1_SECTION 0xE800
+#define mmHBM4_MC0BIST1_SPECIAL_BASE 0x5202E80ull
+#define HBM4_MC0BIST1_SPECIAL_MAX_OFFSET 0x1800
+#define HBM4_MC0BIST1_SPECIAL_SECTION 0x1800
+#define mmHBM4_MC0BIST2_BASE 0x5203000ull
+#define HBM4_MC0BIST2_MAX_OFFSET 0x1000
+#define HBM4_MC0BIST2_SECTION 0xE800
+#define mmHBM4_MC0BIST2_SPECIAL_BASE 0x5203E80ull
+#define HBM4_MC0BIST2_SPECIAL_MAX_OFFSET 0x1800
+#define HBM4_MC0BIST2_SPECIAL_SECTION 0x1800
+#define mmHBM4_MC0BIST3_BASE 0x5204000ull
+#define HBM4_MC0BIST3_MAX_OFFSET 0x1000
+#define HBM4_MC0BIST3_SECTION 0xE800
+#define mmHBM4_MC0BIST3_SPECIAL_BASE 0x5204E80ull
+#define HBM4_MC0BIST3_SPECIAL_MAX_OFFSET 0x1800
+#define HBM4_MC0BIST3_SPECIAL_SECTION 0x1800
+#define mmHBM4_MC0BIST4_BASE 0x5205000ull
+#define HBM4_MC0BIST4_MAX_OFFSET 0x1000
+#define HBM4_MC0BIST4_SECTION 0xE800
+#define mmHBM4_MC0BIST4_SPECIAL_BASE 0x5205E80ull
+#define HBM4_MC0BIST4_SPECIAL_MAX_OFFSET 0x1800
+#define HBM4_MC0BIST4_SPECIAL_SECTION 0x1800
+#define mmHBM4_MC0BIST5_BASE 0x5206000ull
+#define HBM4_MC0BIST5_MAX_OFFSET 0x1000
+#define HBM4_MC0BIST5_SECTION 0xE800
+#define mmHBM4_MC0BIST5_SPECIAL_BASE 0x5206E80ull
+#define HBM4_MC0BIST5_SPECIAL_MAX_OFFSET 0x1800
+#define HBM4_MC0BIST5_SPECIAL_SECTION 0x1800
+#define mmHBM4_MC0BIST6_BASE 0x5207000ull
+#define HBM4_MC0BIST6_MAX_OFFSET 0x1000
+#define HBM4_MC0BIST6_SECTION 0xE800
+#define mmHBM4_MC0BIST6_SPECIAL_BASE 0x5207E80ull
+#define HBM4_MC0BIST6_SPECIAL_MAX_OFFSET 0x1800
+#define HBM4_MC0BIST6_SPECIAL_SECTION 0x1800
+#define mmHBM4_MC0BIST7_BASE 0x5208000ull
+#define HBM4_MC0BIST7_MAX_OFFSET 0x1000
+#define HBM4_MC0BIST7_SECTION 0xE800
+#define mmHBM4_MC0BIST7_SPECIAL_BASE 0x5208E80ull
+#define HBM4_MC0BIST7_SPECIAL_MAX_OFFSET 0x1800
+#define HBM4_MC0BIST7_SPECIAL_SECTION 0x1800
+#define mmHBM4_MC0BIST8_MEM_BASE 0x5209000ull
+#define HBM4_MC0BIST8_MEM_MAX_OFFSET 0x1000
+#define HBM4_MC0BIST8_MEM_SECTION 0xE800
+#define mmHBM4_MC0BIST8_MEM_SPECIAL_BASE 0x5209E80ull
+#define HBM4_MC0BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800
+#define HBM4_MC0BIST8_MEM_SPECIAL_SECTION 0x16180
+#define mmHBM4_MC1_BASE 0x5220000ull
+#define HBM4_MC1_MAX_OFFSET 0x1000
+#define HBM4_MC1_SECTION 0xE800
+#define mmHBM4_MC1_SPECIAL_BASE 0x5220E80ull
+#define HBM4_MC1_SPECIAL_MAX_OFFSET 0x1800
+#define HBM4_MC1_SPECIAL_SECTION 0x1800
+#define mmHBM4_MC1BIST0_BASE 0x5221000ull
+#define HBM4_MC1BIST0_MAX_OFFSET 0x1000
+#define HBM4_MC1BIST0_SECTION 0xE800
+#define mmHBM4_MC1BIST0_SPECIAL_BASE 0x5221E80ull
+#define HBM4_MC1BIST0_SPECIAL_MAX_OFFSET 0x1800
+#define HBM4_MC1BIST0_SPECIAL_SECTION 0x1800
+#define mmHBM4_MC1BIST1_BASE 0x5222000ull
+#define HBM4_MC1BIST1_MAX_OFFSET 0x1000
+#define HBM4_MC1BIST1_SECTION 0xE800
+#define mmHBM4_MC1BIST1_SPECIAL_BASE 0x5222E80ull
+#define HBM4_MC1BIST1_SPECIAL_MAX_OFFSET 0x1800
+#define HBM4_MC1BIST1_SPECIAL_SECTION 0x1800
+#define mmHBM4_MC1BIST2_BASE 0x5223000ull
+#define HBM4_MC1BIST2_MAX_OFFSET 0x1000
+#define HBM4_MC1BIST2_SECTION 0xE800
+#define mmHBM4_MC1BIST2_SPECIAL_BASE 0x5223E80ull
+#define HBM4_MC1BIST2_SPECIAL_MAX_OFFSET 0x1800
+#define HBM4_MC1BIST2_SPECIAL_SECTION 0x1800
+#define mmHBM4_MC1BIST3_BASE 0x5224000ull
+#define HBM4_MC1BIST3_MAX_OFFSET 0x1000
+#define HBM4_MC1BIST3_SECTION 0xE800
+#define mmHBM4_MC1BIST3_SPECIAL_BASE 0x5224E80ull
+#define HBM4_MC1BIST3_SPECIAL_MAX_OFFSET 0x1800
+#define HBM4_MC1BIST3_SPECIAL_SECTION 0x1800
+#define mmHBM4_MC1BIST4_BASE 0x5225000ull
+#define HBM4_MC1BIST4_MAX_OFFSET 0x1000
+#define HBM4_MC1BIST4_SECTION 0xE800
+#define mmHBM4_MC1BIST4_SPECIAL_BASE 0x5225E80ull
+#define HBM4_MC1BIST4_SPECIAL_MAX_OFFSET 0x1800
+#define HBM4_MC1BIST4_SPECIAL_SECTION 0x1800
+#define mmHBM4_MC1BIST5_BASE 0x5226000ull
+#define HBM4_MC1BIST5_MAX_OFFSET 0x1000
+#define HBM4_MC1BIST5_SECTION 0xE800
+#define mmHBM4_MC1BIST5_SPECIAL_BASE 0x5226E80ull
+#define HBM4_MC1BIST5_SPECIAL_MAX_OFFSET 0x1800
+#define HBM4_MC1BIST5_SPECIAL_SECTION 0x1800
+#define mmHBM4_MC1BIST6_BASE 0x5227000ull
+#define HBM4_MC1BIST6_MAX_OFFSET 0x1000
+#define HBM4_MC1BIST6_SECTION 0xE800
+#define mmHBM4_MC1BIST6_SPECIAL_BASE 0x5227E80ull
+#define HBM4_MC1BIST6_SPECIAL_MAX_OFFSET 0x1800
+#define HBM4_MC1BIST6_SPECIAL_SECTION 0x1800
+#define mmHBM4_MC1BIST7_BASE 0x5228000ull
+#define HBM4_MC1BIST7_MAX_OFFSET 0x1000
+#define HBM4_MC1BIST7_SECTION 0xE800
+#define mmHBM4_MC1BIST7_SPECIAL_BASE 0x5228E80ull
+#define HBM4_MC1BIST7_SPECIAL_MAX_OFFSET 0x1800
+#define HBM4_MC1BIST7_SPECIAL_SECTION 0x1800
+#define mmHBM4_MC1BIST8_MEM_BASE 0x5229000ull
+#define HBM4_MC1BIST8_MEM_MAX_OFFSET 0x1000
+#define HBM4_MC1BIST8_MEM_SECTION 0xE800
+#define mmHBM4_MC1BIST8_MEM_SPECIAL_BASE 0x5229E80ull
+#define HBM4_MC1BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800
+#define HBM4_MC1BIST8_MEM_SPECIAL_SECTION 0x16180
+#define mmHBM4_PHY_BASE 0x5240000ull
+#define HBM4_PHY_MAX_OFFSET 0x4000
+#define HBM4_PHY_SECTION 0x40000
+#define mmHBM5_MC0_BASE 0x5280000ull
+#define HBM5_MC0_MAX_OFFSET 0x1000
+#define HBM5_MC0_SECTION 0xE800
+#define mmHBM5_MC0_SPECIAL_BASE 0x5280E80ull
+#define HBM5_MC0_SPECIAL_MAX_OFFSET 0x1800
+#define HBM5_MC0_SPECIAL_SECTION 0x1800
+#define mmHBM5_MC0BIST0_BASE 0x5281000ull
+#define HBM5_MC0BIST0_MAX_OFFSET 0x1000
+#define HBM5_MC0BIST0_SECTION 0xE800
+#define mmHBM5_MC0BIST0_SPECIAL_BASE 0x5281E80ull
+#define HBM5_MC0BIST0_SPECIAL_MAX_OFFSET 0x1800
+#define HBM5_MC0BIST0_SPECIAL_SECTION 0x1800
+#define mmHBM5_MC0BIST1_BASE 0x5282000ull
+#define HBM5_MC0BIST1_MAX_OFFSET 0x1000
+#define HBM5_MC0BIST1_SECTION 0xE800
+#define mmHBM5_MC0BIST1_SPECIAL_BASE 0x5282E80ull
+#define HBM5_MC0BIST1_SPECIAL_MAX_OFFSET 0x1800
+#define HBM5_MC0BIST1_SPECIAL_SECTION 0x1800
+#define mmHBM5_MC0BIST2_BASE 0x5283000ull
+#define HBM5_MC0BIST2_MAX_OFFSET 0x1000
+#define HBM5_MC0BIST2_SECTION 0xE800
+#define mmHBM5_MC0BIST2_SPECIAL_BASE 0x5283E80ull
+#define HBM5_MC0BIST2_SPECIAL_MAX_OFFSET 0x1800
+#define HBM5_MC0BIST2_SPECIAL_SECTION 0x1800
+#define mmHBM5_MC0BIST3_BASE 0x5284000ull
+#define HBM5_MC0BIST3_MAX_OFFSET 0x1000
+#define HBM5_MC0BIST3_SECTION 0xE800
+#define mmHBM5_MC0BIST3_SPECIAL_BASE 0x5284E80ull
+#define HBM5_MC0BIST3_SPECIAL_MAX_OFFSET 0x1800
+#define HBM5_MC0BIST3_SPECIAL_SECTION 0x1800
+#define mmHBM5_MC0BIST4_BASE 0x5285000ull
+#define HBM5_MC0BIST4_MAX_OFFSET 0x1000
+#define HBM5_MC0BIST4_SECTION 0xE800
+#define mmHBM5_MC0BIST4_SPECIAL_BASE 0x5285E80ull
+#define HBM5_MC0BIST4_SPECIAL_MAX_OFFSET 0x1800
+#define HBM5_MC0BIST4_SPECIAL_SECTION 0x1800
+#define mmHBM5_MC0BIST5_BASE 0x5286000ull
+#define HBM5_MC0BIST5_MAX_OFFSET 0x1000
+#define HBM5_MC0BIST5_SECTION 0xE800
+#define mmHBM5_MC0BIST5_SPECIAL_BASE 0x5286E80ull
+#define HBM5_MC0BIST5_SPECIAL_MAX_OFFSET 0x1800
+#define HBM5_MC0BIST5_SPECIAL_SECTION 0x1800
+#define mmHBM5_MC0BIST6_BASE 0x5287000ull
+#define HBM5_MC0BIST6_MAX_OFFSET 0x1000
+#define HBM5_MC0BIST6_SECTION 0xE800
+#define mmHBM5_MC0BIST6_SPECIAL_BASE 0x5287E80ull
+#define HBM5_MC0BIST6_SPECIAL_MAX_OFFSET 0x1800
+#define HBM5_MC0BIST6_SPECIAL_SECTION 0x1800
+#define mmHBM5_MC0BIST7_BASE 0x5288000ull
+#define HBM5_MC0BIST7_MAX_OFFSET 0x1000
+#define HBM5_MC0BIST7_SECTION 0xE800
+#define mmHBM5_MC0BIST7_SPECIAL_BASE 0x5288E80ull
+#define HBM5_MC0BIST7_SPECIAL_MAX_OFFSET 0x1800
+#define HBM5_MC0BIST7_SPECIAL_SECTION 0x1800
+#define mmHBM5_MC0BIST8_MEM_BASE 0x5289000ull
+#define HBM5_MC0BIST8_MEM_MAX_OFFSET 0x1000
+#define HBM5_MC0BIST8_MEM_SECTION 0xE800
+#define mmHBM5_MC0BIST8_MEM_SPECIAL_BASE 0x5289E80ull
+#define HBM5_MC0BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800
+#define HBM5_MC0BIST8_MEM_SPECIAL_SECTION 0x16180
+#define mmHBM5_MC1_BASE 0x52A0000ull
+#define HBM5_MC1_MAX_OFFSET 0x1000
+#define HBM5_MC1_SECTION 0xE800
+#define mmHBM5_MC1_SPECIAL_BASE 0x52A0E80ull
+#define HBM5_MC1_SPECIAL_MAX_OFFSET 0x1800
+#define HBM5_MC1_SPECIAL_SECTION 0x1800
+#define mmHBM5_MC1BIST0_BASE 0x52A1000ull
+#define HBM5_MC1BIST0_MAX_OFFSET 0x1000
+#define HBM5_MC1BIST0_SECTION 0xE800
+#define mmHBM5_MC1BIST0_SPECIAL_BASE 0x52A1E80ull
+#define HBM5_MC1BIST0_SPECIAL_MAX_OFFSET 0x1800
+#define HBM5_MC1BIST0_SPECIAL_SECTION 0x1800
+#define mmHBM5_MC1BIST1_BASE 0x52A2000ull
+#define HBM5_MC1BIST1_MAX_OFFSET 0x1000
+#define HBM5_MC1BIST1_SECTION 0xE800
+#define mmHBM5_MC1BIST1_SPECIAL_BASE 0x52A2E80ull
+#define HBM5_MC1BIST1_SPECIAL_MAX_OFFSET 0x1800
+#define HBM5_MC1BIST1_SPECIAL_SECTION 0x1800
+#define mmHBM5_MC1BIST2_BASE 0x52A3000ull
+#define HBM5_MC1BIST2_MAX_OFFSET 0x1000
+#define HBM5_MC1BIST2_SECTION 0xE800
+#define mmHBM5_MC1BIST2_SPECIAL_BASE 0x52A3E80ull
+#define HBM5_MC1BIST2_SPECIAL_MAX_OFFSET 0x1800
+#define HBM5_MC1BIST2_SPECIAL_SECTION 0x1800
+#define mmHBM5_MC1BIST3_BASE 0x52A4000ull
+#define HBM5_MC1BIST3_MAX_OFFSET 0x1000
+#define HBM5_MC1BIST3_SECTION 0xE800
+#define mmHBM5_MC1BIST3_SPECIAL_BASE 0x52A4E80ull
+#define HBM5_MC1BIST3_SPECIAL_MAX_OFFSET 0x1800
+#define HBM5_MC1BIST3_SPECIAL_SECTION 0x1800
+#define mmHBM5_MC1BIST4_BASE 0x52A5000ull
+#define HBM5_MC1BIST4_MAX_OFFSET 0x1000
+#define HBM5_MC1BIST4_SECTION 0xE800
+#define mmHBM5_MC1BIST4_SPECIAL_BASE 0x52A5E80ull
+#define HBM5_MC1BIST4_SPECIAL_MAX_OFFSET 0x1800
+#define HBM5_MC1BIST4_SPECIAL_SECTION 0x1800
+#define mmHBM5_MC1BIST5_BASE 0x52A6000ull
+#define HBM5_MC1BIST5_MAX_OFFSET 0x1000
+#define HBM5_MC1BIST5_SECTION 0xE800
+#define mmHBM5_MC1BIST5_SPECIAL_BASE 0x52A6E80ull
+#define HBM5_MC1BIST5_SPECIAL_MAX_OFFSET 0x1800
+#define HBM5_MC1BIST5_SPECIAL_SECTION 0x1800
+#define mmHBM5_MC1BIST6_BASE 0x52A7000ull
+#define HBM5_MC1BIST6_MAX_OFFSET 0x1000
+#define HBM5_MC1BIST6_SECTION 0xE800
+#define mmHBM5_MC1BIST6_SPECIAL_BASE 0x52A7E80ull
+#define HBM5_MC1BIST6_SPECIAL_MAX_OFFSET 0x1800
+#define HBM5_MC1BIST6_SPECIAL_SECTION 0x1800
+#define mmHBM5_MC1BIST7_BASE 0x52A8000ull
+#define HBM5_MC1BIST7_MAX_OFFSET 0x1000
+#define HBM5_MC1BIST7_SECTION 0xE800
+#define mmHBM5_MC1BIST7_SPECIAL_BASE 0x52A8E80ull
+#define HBM5_MC1BIST7_SPECIAL_MAX_OFFSET 0x1800
+#define HBM5_MC1BIST7_SPECIAL_SECTION 0x1800
+#define mmHBM5_MC1BIST8_MEM_BASE 0x52A9000ull
+#define HBM5_MC1BIST8_MEM_MAX_OFFSET 0x1000
+#define HBM5_MC1BIST8_MEM_SECTION 0xE800
+#define mmHBM5_MC1BIST8_MEM_SPECIAL_BASE 0x52A9E80ull
+#define HBM5_MC1BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800
+#define HBM5_MC1BIST8_MEM_SPECIAL_SECTION 0x16180
+#define mmHBM5_PHY_BASE 0x52C0000ull
+#define HBM5_PHY_MAX_OFFSET 0x4000
+#define HBM5_PHY_SECTION 0x140000
+#define mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5400000ull
+#define NIC0_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC0_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5400080ull
+#define NIC0_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5400100ull
+#define NIC0_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5400180ull
+#define NIC0_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC0_UMR0_0_SPECIAL_BASE 0x5400E80ull
+#define NIC0_UMR0_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR0_0_SPECIAL_SECTION 0x1800
+#define mmNIC0_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5401000ull
+#define NIC0_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC0_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5401080ull
+#define NIC0_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC0_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5401100ull
+#define NIC0_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC0_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5401180ull
+#define NIC0_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC0_UMR0_1_SPECIAL_BASE 0x5401E80ull
+#define NIC0_UMR0_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR0_1_SPECIAL_SECTION 0x1800
+#define mmNIC0_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5402000ull
+#define NIC0_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC0_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5402080ull
+#define NIC0_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC0_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5402100ull
+#define NIC0_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC0_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5402180ull
+#define NIC0_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC0_UMR0_2_SPECIAL_BASE 0x5402E80ull
+#define NIC0_UMR0_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR0_2_SPECIAL_SECTION 0x1800
+#define mmNIC0_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5403000ull
+#define NIC0_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC0_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5403080ull
+#define NIC0_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC0_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5403100ull
+#define NIC0_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC0_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5403180ull
+#define NIC0_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC0_UMR0_3_SPECIAL_BASE 0x5403E80ull
+#define NIC0_UMR0_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR0_3_SPECIAL_SECTION 0x1800
+#define mmNIC0_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5404000ull
+#define NIC0_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC0_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5404080ull
+#define NIC0_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC0_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5404100ull
+#define NIC0_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC0_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5404180ull
+#define NIC0_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC0_UMR0_4_SPECIAL_BASE 0x5404E80ull
+#define NIC0_UMR0_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR0_4_SPECIAL_SECTION 0x1800
+#define mmNIC0_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5405000ull
+#define NIC0_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC0_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5405080ull
+#define NIC0_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC0_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5405100ull
+#define NIC0_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC0_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5405180ull
+#define NIC0_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC0_UMR0_5_SPECIAL_BASE 0x5405E80ull
+#define NIC0_UMR0_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR0_5_SPECIAL_SECTION 0x1800
+#define mmNIC0_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5406000ull
+#define NIC0_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC0_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5406080ull
+#define NIC0_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC0_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5406100ull
+#define NIC0_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC0_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5406180ull
+#define NIC0_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC0_UMR0_6_SPECIAL_BASE 0x5406E80ull
+#define NIC0_UMR0_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR0_6_SPECIAL_SECTION 0x1800
+#define mmNIC0_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5407000ull
+#define NIC0_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC0_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5407080ull
+#define NIC0_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC0_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5407100ull
+#define NIC0_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC0_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5407180ull
+#define NIC0_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC0_UMR0_7_SPECIAL_BASE 0x5407E80ull
+#define NIC0_UMR0_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR0_7_SPECIAL_SECTION 0x1800
+#define mmNIC0_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5408000ull
+#define NIC0_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC0_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5408080ull
+#define NIC0_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC0_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5408100ull
+#define NIC0_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC0_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5408180ull
+#define NIC0_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC0_UMR0_8_SPECIAL_BASE 0x5408E80ull
+#define NIC0_UMR0_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR0_8_SPECIAL_SECTION 0x1800
+#define mmNIC0_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5409000ull
+#define NIC0_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC0_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5409080ull
+#define NIC0_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC0_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5409100ull
+#define NIC0_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC0_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5409180ull
+#define NIC0_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC0_UMR0_9_SPECIAL_BASE 0x5409E80ull
+#define NIC0_UMR0_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR0_9_SPECIAL_SECTION 0x1800
+#define mmNIC0_UMR0_10_UNSECURE_DOORBELL0_BASE 0x540A000ull
+#define NIC0_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC0_UMR0_10_UNSECURE_DOORBELL1_BASE 0x540A080ull
+#define NIC0_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC0_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x540A100ull
+#define NIC0_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC0_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x540A180ull
+#define NIC0_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC0_UMR0_10_SPECIAL_BASE 0x540AE80ull
+#define NIC0_UMR0_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR0_10_SPECIAL_SECTION 0x1800
+#define mmNIC0_UMR0_11_UNSECURE_DOORBELL0_BASE 0x540B000ull
+#define NIC0_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC0_UMR0_11_UNSECURE_DOORBELL1_BASE 0x540B080ull
+#define NIC0_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC0_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x540B100ull
+#define NIC0_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC0_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x540B180ull
+#define NIC0_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC0_UMR0_11_SPECIAL_BASE 0x540BE80ull
+#define NIC0_UMR0_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR0_11_SPECIAL_SECTION 0x1800
+#define mmNIC0_UMR0_12_UNSECURE_DOORBELL0_BASE 0x540C000ull
+#define NIC0_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC0_UMR0_12_UNSECURE_DOORBELL1_BASE 0x540C080ull
+#define NIC0_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC0_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x540C100ull
+#define NIC0_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC0_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x540C180ull
+#define NIC0_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC0_UMR0_12_SPECIAL_BASE 0x540CE80ull
+#define NIC0_UMR0_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR0_12_SPECIAL_SECTION 0x1800
+#define mmNIC0_UMR0_13_UNSECURE_DOORBELL0_BASE 0x540D000ull
+#define NIC0_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC0_UMR0_13_UNSECURE_DOORBELL1_BASE 0x540D080ull
+#define NIC0_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC0_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x540D100ull
+#define NIC0_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC0_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x540D180ull
+#define NIC0_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC0_UMR0_13_SPECIAL_BASE 0x540DE80ull
+#define NIC0_UMR0_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR0_13_SPECIAL_SECTION 0x1800
+#define mmNIC0_UMR0_14_UNSECURE_DOORBELL0_BASE 0x540E000ull
+#define NIC0_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC0_UMR0_14_UNSECURE_DOORBELL1_BASE 0x540E080ull
+#define NIC0_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC0_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x540E100ull
+#define NIC0_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC0_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x540E180ull
+#define NIC0_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC0_UMR0_14_SPECIAL_BASE 0x540EE80ull
+#define NIC0_UMR0_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR0_14_SPECIAL_SECTION 0x1180
+#define mmNIC0_QM_DCCM0_BASE 0x5410000ull
+#define NIC0_QM_DCCM0_MAX_OFFSET 0x4000
+#define NIC0_QM_DCCM0_SECTION 0x8000
+#define mmNIC0_QM_ARC_AUX0_BASE 0x5418000ull
+#define NIC0_QM_ARC_AUX0_MAX_OFFSET 0x1000
+#define NIC0_QM_ARC_AUX0_SECTION 0xE800
+#define mmNIC0_QM_ARC_AUX0_SPECIAL_BASE 0x5418E80ull
+#define NIC0_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_QM_ARC_AUX0_SPECIAL_SECTION 0x1180
+#define mmNIC0_QM0_BASE 0x541A000ull
+#define NIC0_QM0_MAX_OFFSET 0x1000
+#define NIC0_QM0_SECTION 0x9000
+#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x541A900ull
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x541A908ull
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x541A910ull
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x541A918ull
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x541A920ull
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x541A928ull
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x541A930ull
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x541A938ull
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x541A940ull
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x541A948ull
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x541A950ull
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x541A958ull
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x541A960ull
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x541A968ull
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x541A970ull
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x541A978ull
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC0_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmNIC0_QM0_AXUSER_SECURED_BASE 0x541AB00ull
+#define NIC0_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC0_QM0_AXUSER_SECURED_SECTION 0x8000
+#define mmNIC0_QM0_AXUSER_NONSECURED_BASE 0x541AB80ull
+#define NIC0_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC0_QM0_AXUSER_NONSECURED_SECTION 0x8000
+#define mmNIC0_QM0_DBG_HBW_BASE 0x541AC00ull
+#define NIC0_QM0_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC0_QM0_DBG_HBW_SECTION 0x8000
+#define mmNIC0_QM0_DBG_LBW_BASE 0x541AC80ull
+#define NIC0_QM0_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC0_QM0_DBG_LBW_SECTION 0x1000
+#define mmNIC0_QM0_CGM_BASE 0x541AD80ull
+#define NIC0_QM0_CGM_MAX_OFFSET 0xC000
+#define NIC0_QM0_CGM_SECTION 0x1000
+#define mmNIC0_QM0_SPECIAL_BASE 0x541AE80ull
+#define NIC0_QM0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_QM0_SPECIAL_SECTION 0x4180
+#define mmNIC0_QPC0_BASE 0x541F000ull
+#define NIC0_QPC0_MAX_OFFSET 0x1000
+#define NIC0_QPC0_SECTION 0x7200
+#define mmNIC0_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x541F720ull
+#define NIC0_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x541F728ull
+#define NIC0_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x541F730ull
+#define NIC0_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x541F738ull
+#define NIC0_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x541F740ull
+#define NIC0_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x541F748ull
+#define NIC0_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x541F750ull
+#define NIC0_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x541F758ull
+#define NIC0_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x541F760ull
+#define NIC0_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x541F768ull
+#define NIC0_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x541F770ull
+#define NIC0_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x541F778ull
+#define NIC0_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x541F780ull
+#define NIC0_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x541F788ull
+#define NIC0_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x541F790ull
+#define NIC0_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x541F798ull
+#define NIC0_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x541F7A0ull
+#define NIC0_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x541F7A8ull
+#define NIC0_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x541F7B0ull
+#define NIC0_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x541F7B8ull
+#define NIC0_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x541F7C0ull
+#define NIC0_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x541F7C8ull
+#define NIC0_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x541F7D0ull
+#define NIC0_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x541F7D8ull
+#define NIC0_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x541F7E0ull
+#define NIC0_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x541F7E8ull
+#define NIC0_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x541F7F0ull
+#define NIC0_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x541F7F8ull
+#define NIC0_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x541F800ull
+#define NIC0_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x541F808ull
+#define NIC0_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x541F810ull
+#define NIC0_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x541F818ull
+#define NIC0_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define mmNIC0_QPC0_AXUSER_CONG_QUE_BASE 0x541FB80ull
+#define NIC0_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC0_QPC0_AXUSER_CONG_QUE_SECTION 0x6000
+#define mmNIC0_QPC0_AXUSER_RXWQE_BASE 0x541FBE0ull
+#define NIC0_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC0_QPC0_AXUSER_RXWQE_SECTION 0x6000
+#define mmNIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x541FC40ull
+#define NIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define mmNIC0_QPC0_AXUSER_DB_FIFO_BASE 0x541FCA0ull
+#define NIC0_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC0_QPC0_AXUSER_DB_FIFO_SECTION 0x6000
+#define mmNIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x541FD00ull
+#define NIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define mmNIC0_QPC0_AXUSER_ERR_FIFO_BASE 0x541FD60ull
+#define NIC0_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC0_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000
+#define mmNIC0_QPC0_AXUSER_QPC_RESP_BASE 0x541FDC0ull
+#define NIC0_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC0_QPC0_AXUSER_QPC_RESP_SECTION 0x6000
+#define mmNIC0_QPC0_AXUSER_QPC_REQ_BASE 0x541FE20ull
+#define NIC0_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC0_QPC0_AXUSER_QPC_REQ_SECTION 0x6000
+#define mmNIC0_QPC0_SPECIAL_BASE 0x541FE80ull
+#define NIC0_QPC0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_QPC0_SPECIAL_SECTION 0x1800
+#define mmNIC0_UMR1_0_UNSECURE_DOORBELL0_BASE 0x5420000ull
+#define NIC0_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC0_UMR1_0_UNSECURE_DOORBELL1_BASE 0x5420080ull
+#define NIC0_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC0_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x5420100ull
+#define NIC0_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC0_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x5420180ull
+#define NIC0_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC0_UMR1_0_SPECIAL_BASE 0x5420E80ull
+#define NIC0_UMR1_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR1_0_SPECIAL_SECTION 0x1800
+#define mmNIC0_UMR1_1_UNSECURE_DOORBELL0_BASE 0x5421000ull
+#define NIC0_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC0_UMR1_1_UNSECURE_DOORBELL1_BASE 0x5421080ull
+#define NIC0_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC0_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x5421100ull
+#define NIC0_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC0_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x5421180ull
+#define NIC0_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC0_UMR1_1_SPECIAL_BASE 0x5421E80ull
+#define NIC0_UMR1_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR1_1_SPECIAL_SECTION 0x1800
+#define mmNIC0_UMR1_2_UNSECURE_DOORBELL0_BASE 0x5422000ull
+#define NIC0_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC0_UMR1_2_UNSECURE_DOORBELL1_BASE 0x5422080ull
+#define NIC0_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC0_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x5422100ull
+#define NIC0_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC0_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x5422180ull
+#define NIC0_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC0_UMR1_2_SPECIAL_BASE 0x5422E80ull
+#define NIC0_UMR1_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR1_2_SPECIAL_SECTION 0x1800
+#define mmNIC0_UMR1_3_UNSECURE_DOORBELL0_BASE 0x5423000ull
+#define NIC0_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC0_UMR1_3_UNSECURE_DOORBELL1_BASE 0x5423080ull
+#define NIC0_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC0_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x5423100ull
+#define NIC0_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC0_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x5423180ull
+#define NIC0_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC0_UMR1_3_SPECIAL_BASE 0x5423E80ull
+#define NIC0_UMR1_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR1_3_SPECIAL_SECTION 0x1800
+#define mmNIC0_UMR1_4_UNSECURE_DOORBELL0_BASE 0x5424000ull
+#define NIC0_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC0_UMR1_4_UNSECURE_DOORBELL1_BASE 0x5424080ull
+#define NIC0_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC0_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x5424100ull
+#define NIC0_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC0_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x5424180ull
+#define NIC0_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC0_UMR1_4_SPECIAL_BASE 0x5424E80ull
+#define NIC0_UMR1_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR1_4_SPECIAL_SECTION 0x1800
+#define mmNIC0_UMR1_5_UNSECURE_DOORBELL0_BASE 0x5425000ull
+#define NIC0_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC0_UMR1_5_UNSECURE_DOORBELL1_BASE 0x5425080ull
+#define NIC0_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC0_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x5425100ull
+#define NIC0_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC0_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x5425180ull
+#define NIC0_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC0_UMR1_5_SPECIAL_BASE 0x5425E80ull
+#define NIC0_UMR1_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR1_5_SPECIAL_SECTION 0x1800
+#define mmNIC0_UMR1_6_UNSECURE_DOORBELL0_BASE 0x5426000ull
+#define NIC0_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC0_UMR1_6_UNSECURE_DOORBELL1_BASE 0x5426080ull
+#define NIC0_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC0_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x5426100ull
+#define NIC0_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC0_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x5426180ull
+#define NIC0_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC0_UMR1_6_SPECIAL_BASE 0x5426E80ull
+#define NIC0_UMR1_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR1_6_SPECIAL_SECTION 0x1800
+#define mmNIC0_UMR1_7_UNSECURE_DOORBELL0_BASE 0x5427000ull
+#define NIC0_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC0_UMR1_7_UNSECURE_DOORBELL1_BASE 0x5427080ull
+#define NIC0_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC0_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x5427100ull
+#define NIC0_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC0_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x5427180ull
+#define NIC0_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC0_UMR1_7_SPECIAL_BASE 0x5427E80ull
+#define NIC0_UMR1_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR1_7_SPECIAL_SECTION 0x1800
+#define mmNIC0_UMR1_8_UNSECURE_DOORBELL0_BASE 0x5428000ull
+#define NIC0_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC0_UMR1_8_UNSECURE_DOORBELL1_BASE 0x5428080ull
+#define NIC0_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC0_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x5428100ull
+#define NIC0_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC0_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x5428180ull
+#define NIC0_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC0_UMR1_8_SPECIAL_BASE 0x5428E80ull
+#define NIC0_UMR1_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR1_8_SPECIAL_SECTION 0x1800
+#define mmNIC0_UMR1_9_UNSECURE_DOORBELL0_BASE 0x5429000ull
+#define NIC0_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC0_UMR1_9_UNSECURE_DOORBELL1_BASE 0x5429080ull
+#define NIC0_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC0_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x5429100ull
+#define NIC0_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC0_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x5429180ull
+#define NIC0_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC0_UMR1_9_SPECIAL_BASE 0x5429E80ull
+#define NIC0_UMR1_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR1_9_SPECIAL_SECTION 0x1800
+#define mmNIC0_UMR1_10_UNSECURE_DOORBELL0_BASE 0x542A000ull
+#define NIC0_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC0_UMR1_10_UNSECURE_DOORBELL1_BASE 0x542A080ull
+#define NIC0_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC0_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x542A100ull
+#define NIC0_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC0_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x542A180ull
+#define NIC0_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC0_UMR1_10_SPECIAL_BASE 0x542AE80ull
+#define NIC0_UMR1_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR1_10_SPECIAL_SECTION 0x1800
+#define mmNIC0_UMR1_11_UNSECURE_DOORBELL0_BASE 0x542B000ull
+#define NIC0_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC0_UMR1_11_UNSECURE_DOORBELL1_BASE 0x542B080ull
+#define NIC0_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC0_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x542B100ull
+#define NIC0_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC0_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x542B180ull
+#define NIC0_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC0_UMR1_11_SPECIAL_BASE 0x542BE80ull
+#define NIC0_UMR1_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR1_11_SPECIAL_SECTION 0x1800
+#define mmNIC0_UMR1_12_UNSECURE_DOORBELL0_BASE 0x542C000ull
+#define NIC0_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC0_UMR1_12_UNSECURE_DOORBELL1_BASE 0x542C080ull
+#define NIC0_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC0_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x542C100ull
+#define NIC0_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC0_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x542C180ull
+#define NIC0_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC0_UMR1_12_SPECIAL_BASE 0x542CE80ull
+#define NIC0_UMR1_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR1_12_SPECIAL_SECTION 0x1800
+#define mmNIC0_UMR1_13_UNSECURE_DOORBELL0_BASE 0x542D000ull
+#define NIC0_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC0_UMR1_13_UNSECURE_DOORBELL1_BASE 0x542D080ull
+#define NIC0_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC0_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x542D100ull
+#define NIC0_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC0_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x542D180ull
+#define NIC0_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC0_UMR1_13_SPECIAL_BASE 0x542DE80ull
+#define NIC0_UMR1_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR1_13_SPECIAL_SECTION 0x1800
+#define mmNIC0_UMR1_14_UNSECURE_DOORBELL0_BASE 0x542E000ull
+#define NIC0_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC0_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC0_UMR1_14_UNSECURE_DOORBELL1_BASE 0x542E080ull
+#define NIC0_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC0_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC0_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x542E100ull
+#define NIC0_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC0_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC0_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x542E180ull
+#define NIC0_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC0_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC0_UMR1_14_SPECIAL_BASE 0x542EE80ull
+#define NIC0_UMR1_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_UMR1_14_SPECIAL_SECTION 0x1180
+#define mmNIC0_QM_DCCM1_BASE 0x5430000ull
+#define NIC0_QM_DCCM1_MAX_OFFSET 0x4000
+#define NIC0_QM_DCCM1_SECTION 0x8000
+#define mmNIC0_QM_ARC_AUX1_BASE 0x5438000ull
+#define NIC0_QM_ARC_AUX1_MAX_OFFSET 0x1000
+#define NIC0_QM_ARC_AUX1_SECTION 0xE800
+#define mmNIC0_QM_ARC_AUX1_SPECIAL_BASE 0x5438E80ull
+#define NIC0_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_QM_ARC_AUX1_SPECIAL_SECTION 0x1180
+#define mmNIC0_QM1_BASE 0x543A000ull
+#define NIC0_QM1_MAX_OFFSET 0x1000
+#define NIC0_QM1_SECTION 0x9000
+#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x543A900ull
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x543A908ull
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x543A910ull
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x543A918ull
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x543A920ull
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x543A928ull
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x543A930ull
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x543A938ull
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x543A940ull
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x543A948ull
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x543A950ull
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x543A958ull
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x543A960ull
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x543A968ull
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x543A970ull
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x543A978ull
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC0_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmNIC0_QM1_AXUSER_SECURED_BASE 0x543AB00ull
+#define NIC0_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC0_QM1_AXUSER_SECURED_SECTION 0x8000
+#define mmNIC0_QM1_AXUSER_NONSECURED_BASE 0x543AB80ull
+#define NIC0_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC0_QM1_AXUSER_NONSECURED_SECTION 0x8000
+#define mmNIC0_QM1_DBG_HBW_BASE 0x543AC00ull
+#define NIC0_QM1_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC0_QM1_DBG_HBW_SECTION 0x8000
+#define mmNIC0_QM1_DBG_LBW_BASE 0x543AC80ull
+#define NIC0_QM1_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC0_QM1_DBG_LBW_SECTION 0x1000
+#define mmNIC0_QM1_CGM_BASE 0x543AD80ull
+#define NIC0_QM1_CGM_MAX_OFFSET 0xC000
+#define NIC0_QM1_CGM_SECTION 0x1000
+#define mmNIC0_QM1_SPECIAL_BASE 0x543AE80ull
+#define NIC0_QM1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_QM1_SPECIAL_SECTION 0x4180
+#define mmNIC0_QPC1_BASE 0x543F000ull
+#define NIC0_QPC1_MAX_OFFSET 0x1000
+#define NIC0_QPC1_SECTION 0x7200
+#define mmNIC0_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x543F720ull
+#define NIC0_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x543F728ull
+#define NIC0_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x543F730ull
+#define NIC0_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x543F738ull
+#define NIC0_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x543F740ull
+#define NIC0_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x543F748ull
+#define NIC0_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x543F750ull
+#define NIC0_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x543F758ull
+#define NIC0_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x543F760ull
+#define NIC0_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x543F768ull
+#define NIC0_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x543F770ull
+#define NIC0_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x543F778ull
+#define NIC0_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x543F780ull
+#define NIC0_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x543F788ull
+#define NIC0_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x543F790ull
+#define NIC0_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x543F798ull
+#define NIC0_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x543F7A0ull
+#define NIC0_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x543F7A8ull
+#define NIC0_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x543F7B0ull
+#define NIC0_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x543F7B8ull
+#define NIC0_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x543F7C0ull
+#define NIC0_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x543F7C8ull
+#define NIC0_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x543F7D0ull
+#define NIC0_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x543F7D8ull
+#define NIC0_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x543F7E0ull
+#define NIC0_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x543F7E8ull
+#define NIC0_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x543F7F0ull
+#define NIC0_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x543F7F8ull
+#define NIC0_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x543F800ull
+#define NIC0_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x543F808ull
+#define NIC0_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x543F810ull
+#define NIC0_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC0_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x543F818ull
+#define NIC0_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC0_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define mmNIC0_QPC1_AXUSER_CONG_QUE_BASE 0x543FB80ull
+#define NIC0_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC0_QPC1_AXUSER_CONG_QUE_SECTION 0x6000
+#define mmNIC0_QPC1_AXUSER_RXWQE_BASE 0x543FBE0ull
+#define NIC0_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC0_QPC1_AXUSER_RXWQE_SECTION 0x6000
+#define mmNIC0_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x543FC40ull
+#define NIC0_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC0_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define mmNIC0_QPC1_AXUSER_DB_FIFO_BASE 0x543FCA0ull
+#define NIC0_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC0_QPC1_AXUSER_DB_FIFO_SECTION 0x6000
+#define mmNIC0_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x543FD00ull
+#define NIC0_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC0_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define mmNIC0_QPC1_AXUSER_ERR_FIFO_BASE 0x543FD60ull
+#define NIC0_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC0_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000
+#define mmNIC0_QPC1_AXUSER_QPC_RESP_BASE 0x543FDC0ull
+#define NIC0_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC0_QPC1_AXUSER_QPC_RESP_SECTION 0x6000
+#define mmNIC0_QPC1_AXUSER_QPC_REQ_BASE 0x543FE20ull
+#define NIC0_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC0_QPC1_AXUSER_QPC_REQ_SECTION 0x6000
+#define mmNIC0_QPC1_SPECIAL_BASE 0x543FE80ull
+#define NIC0_QPC1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_QPC1_SPECIAL_SECTION 0x8180
+#define mmNIC0_TMR_BASE 0x5448000ull
+#define NIC0_TMR_MAX_OFFSET 0x1000
+#define NIC0_TMR_SECTION 0xD600
+#define mmNIC0_TMR_AXUSER_TMR_FREE_LIST_BASE 0x5448D60ull
+#define NIC0_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000
+#define NIC0_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000
+#define mmNIC0_TMR_AXUSER_TMR_FIFO_BASE 0x5448DC0ull
+#define NIC0_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000
+#define NIC0_TMR_AXUSER_TMR_FIFO_SECTION 0x6000
+#define mmNIC0_TMR_AXUSER_TMR_FSM_BASE 0x5448E20ull
+#define NIC0_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000
+#define NIC0_TMR_AXUSER_TMR_FSM_SECTION 0x6000
+#define mmNIC0_TMR_SPECIAL_BASE 0x5448E80ull
+#define NIC0_TMR_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_TMR_SPECIAL_SECTION 0x1800
+#define mmNIC0_RXB_CORE_BASE 0x5449000ull
+#define NIC0_RXB_CORE_MAX_OFFSET 0x1000
+#define NIC0_RXB_CORE_SECTION 0x6100
+#define mmNIC0_RXB_CORE_SCT_AWUSER_BASE 0x5449610ull
+#define NIC0_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000
+#define NIC0_RXB_CORE_SCT_AWUSER_SECTION 0x8700
+#define mmNIC0_RXB_CORE_SPECIAL_BASE 0x5449E80ull
+#define NIC0_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_RXB_CORE_SPECIAL_SECTION 0x1800
+#define mmNIC0_RXE0_BASE 0x544A000ull
+#define NIC0_RXE0_MAX_OFFSET 0x1000
+#define NIC0_RXE0_SECTION 0x9000
+#define mmNIC0_RXE0_WQE_ARUSER_BASE 0x544A900ull
+#define NIC0_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC0_RXE0_WQE_ARUSER_SECTION 0x5800
+#define mmNIC0_RXE0_SPECIAL_BASE 0x544AE80ull
+#define NIC0_RXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_RXE0_SPECIAL_SECTION 0x1800
+#define mmNIC0_RXE1_BASE 0x544B000ull
+#define NIC0_RXE1_MAX_OFFSET 0x1000
+#define NIC0_RXE1_SECTION 0x9000
+#define mmNIC0_RXE1_WQE_ARUSER_BASE 0x544B900ull
+#define NIC0_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC0_RXE1_WQE_ARUSER_SECTION 0x5800
+#define mmNIC0_RXE1_SPECIAL_BASE 0x544BE80ull
+#define NIC0_RXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_RXE1_SPECIAL_SECTION 0x1800
+#define mmNIC0_RXE0_AXUSER_AXUSER_CQ0_BASE 0x544C000ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define mmNIC0_RXE0_AXUSER_AXUSER_CQ1_BASE 0x544C050ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define mmNIC0_RXE0_AXUSER_AXUSER_CQ2_BASE 0x544C0A0ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define mmNIC0_RXE0_AXUSER_AXUSER_CQ3_BASE 0x544C0F0ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define mmNIC0_RXE0_AXUSER_AXUSER_CQ4_BASE 0x544C140ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define mmNIC0_RXE0_AXUSER_AXUSER_CQ5_BASE 0x544C190ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define mmNIC0_RXE0_AXUSER_AXUSER_CQ6_BASE 0x544C1E0ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define mmNIC0_RXE0_AXUSER_AXUSER_CQ7_BASE 0x544C230ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define mmNIC0_RXE0_AXUSER_AXUSER_CQ8_BASE 0x544C280ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define mmNIC0_RXE0_AXUSER_AXUSER_CQ9_BASE 0x544C2D0ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define mmNIC0_RXE0_AXUSER_AXUSER_CQ10_BASE 0x544C320ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define mmNIC0_RXE0_AXUSER_AXUSER_CQ11_BASE 0x544C370ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define mmNIC0_RXE0_AXUSER_AXUSER_CQ12_BASE 0x544C3C0ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define mmNIC0_RXE0_AXUSER_AXUSER_CQ13_BASE 0x544C410ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define mmNIC0_RXE0_AXUSER_AXUSER_CQ14_BASE 0x544C460ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define mmNIC0_RXE0_AXUSER_AXUSER_CQ15_BASE 0x544C4B0ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define mmNIC0_RXE0_AXUSER_AXUSER_CQ16_BASE 0x544C500ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define mmNIC0_RXE0_AXUSER_AXUSER_CQ17_BASE 0x544C550ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define mmNIC0_RXE0_AXUSER_AXUSER_CQ18_BASE 0x544C5A0ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define mmNIC0_RXE0_AXUSER_AXUSER_CQ19_BASE 0x544C5F0ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define mmNIC0_RXE0_AXUSER_AXUSER_CQ20_BASE 0x544C640ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define mmNIC0_RXE0_AXUSER_AXUSER_CQ21_BASE 0x544C690ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define mmNIC0_RXE0_AXUSER_AXUSER_CQ22_BASE 0x544C6E0ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define mmNIC0_RXE0_AXUSER_AXUSER_CQ23_BASE 0x544C730ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define mmNIC0_RXE0_AXUSER_AXUSER_CQ24_BASE 0x544C780ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define mmNIC0_RXE0_AXUSER_AXUSER_CQ25_BASE 0x544C7D0ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define mmNIC0_RXE0_AXUSER_AXUSER_CQ26_BASE 0x544C820ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define mmNIC0_RXE0_AXUSER_AXUSER_CQ27_BASE 0x544C870ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define mmNIC0_RXE0_AXUSER_AXUSER_CQ28_BASE 0x544C8C0ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define mmNIC0_RXE0_AXUSER_AXUSER_CQ29_BASE 0x544C910ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define mmNIC0_RXE0_AXUSER_AXUSER_CQ30_BASE 0x544C960ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define mmNIC0_RXE0_AXUSER_AXUSER_CQ31_BASE 0x544C9B0ull
+#define NIC0_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC0_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define mmNIC0_RXE0_AXUSER_SPECIAL_BASE 0x544CE80ull
+#define NIC0_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_RXE0_AXUSER_SPECIAL_SECTION 0x1800
+#define mmNIC0_RXE1_AXUSER_AXUSER_CQ0_BASE 0x544D000ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define mmNIC0_RXE1_AXUSER_AXUSER_CQ1_BASE 0x544D050ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define mmNIC0_RXE1_AXUSER_AXUSER_CQ2_BASE 0x544D0A0ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define mmNIC0_RXE1_AXUSER_AXUSER_CQ3_BASE 0x544D0F0ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define mmNIC0_RXE1_AXUSER_AXUSER_CQ4_BASE 0x544D140ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define mmNIC0_RXE1_AXUSER_AXUSER_CQ5_BASE 0x544D190ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define mmNIC0_RXE1_AXUSER_AXUSER_CQ6_BASE 0x544D1E0ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define mmNIC0_RXE1_AXUSER_AXUSER_CQ7_BASE 0x544D230ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define mmNIC0_RXE1_AXUSER_AXUSER_CQ8_BASE 0x544D280ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define mmNIC0_RXE1_AXUSER_AXUSER_CQ9_BASE 0x544D2D0ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define mmNIC0_RXE1_AXUSER_AXUSER_CQ10_BASE 0x544D320ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define mmNIC0_RXE1_AXUSER_AXUSER_CQ11_BASE 0x544D370ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define mmNIC0_RXE1_AXUSER_AXUSER_CQ12_BASE 0x544D3C0ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define mmNIC0_RXE1_AXUSER_AXUSER_CQ13_BASE 0x544D410ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define mmNIC0_RXE1_AXUSER_AXUSER_CQ14_BASE 0x544D460ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define mmNIC0_RXE1_AXUSER_AXUSER_CQ15_BASE 0x544D4B0ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define mmNIC0_RXE1_AXUSER_AXUSER_CQ16_BASE 0x544D500ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define mmNIC0_RXE1_AXUSER_AXUSER_CQ17_BASE 0x544D550ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define mmNIC0_RXE1_AXUSER_AXUSER_CQ18_BASE 0x544D5A0ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define mmNIC0_RXE1_AXUSER_AXUSER_CQ19_BASE 0x544D5F0ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define mmNIC0_RXE1_AXUSER_AXUSER_CQ20_BASE 0x544D640ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define mmNIC0_RXE1_AXUSER_AXUSER_CQ21_BASE 0x544D690ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define mmNIC0_RXE1_AXUSER_AXUSER_CQ22_BASE 0x544D6E0ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define mmNIC0_RXE1_AXUSER_AXUSER_CQ23_BASE 0x544D730ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define mmNIC0_RXE1_AXUSER_AXUSER_CQ24_BASE 0x544D780ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define mmNIC0_RXE1_AXUSER_AXUSER_CQ25_BASE 0x544D7D0ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define mmNIC0_RXE1_AXUSER_AXUSER_CQ26_BASE 0x544D820ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define mmNIC0_RXE1_AXUSER_AXUSER_CQ27_BASE 0x544D870ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define mmNIC0_RXE1_AXUSER_AXUSER_CQ28_BASE 0x544D8C0ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define mmNIC0_RXE1_AXUSER_AXUSER_CQ29_BASE 0x544D910ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define mmNIC0_RXE1_AXUSER_AXUSER_CQ30_BASE 0x544D960ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define mmNIC0_RXE1_AXUSER_AXUSER_CQ31_BASE 0x544D9B0ull
+#define NIC0_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC0_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define mmNIC0_RXE1_AXUSER_SPECIAL_BASE 0x544DE80ull
+#define NIC0_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_RXE1_AXUSER_SPECIAL_SECTION 0x2180
+#define mmNIC0_TXS0_BASE 0x5450000ull
+#define NIC0_TXS0_MAX_OFFSET 0x1000
+#define NIC0_TXS0_SECTION 0xE800
+#define mmNIC0_TXS0_SPECIAL_BASE 0x5450E80ull
+#define NIC0_TXS0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_TXS0_SPECIAL_SECTION 0x1800
+#define mmNIC0_TXS1_BASE 0x5451000ull
+#define NIC0_TXS1_MAX_OFFSET 0x1000
+#define NIC0_TXS1_SECTION 0xE800
+#define mmNIC0_TXS1_SPECIAL_BASE 0x5451E80ull
+#define NIC0_TXS1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_TXS1_SPECIAL_SECTION 0x1800
+#define mmNIC0_TXE0_BASE 0x5452000ull
+#define NIC0_TXE0_MAX_OFFSET 0x1000
+#define NIC0_TXE0_SECTION 0xE800
+#define mmNIC0_TXE0_SPECIAL_BASE 0x5452E80ull
+#define NIC0_TXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_TXE0_SPECIAL_SECTION 0x1800
+#define mmNIC0_TXE1_BASE 0x5453000ull
+#define NIC0_TXE1_MAX_OFFSET 0x1000
+#define NIC0_TXE1_SECTION 0xE800
+#define mmNIC0_TXE1_SPECIAL_BASE 0x5453E80ull
+#define NIC0_TXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_TXE1_SPECIAL_SECTION 0x1800
+#define mmNIC0_TXB_BASE 0x5454000ull
+#define NIC0_TXB_MAX_OFFSET 0x1000
+#define NIC0_TXB_SECTION 0xE800
+#define mmNIC0_TXB_SPECIAL_BASE 0x5454E80ull
+#define NIC0_TXB_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_TXB_SPECIAL_SECTION 0x1800
+#define mmNIC0_MSTR_IF_RR_SHRD_HBW_BASE 0x5455000ull
+#define NIC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define NIC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmNIC0_MSTR_IF_RR_PRVT_HBW_BASE 0x5455200ull
+#define NIC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define NIC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmNIC0_MSTR_IF_RR_SHRD_LBW_BASE 0x5455400ull
+#define NIC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define NIC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmNIC0_MSTR_IF_RR_PRVT_LBW_BASE 0x5455600ull
+#define NIC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define NIC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmNIC0_MSTR_IF_E2E_CRDT_BASE 0x5455800ull
+#define NIC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define NIC0_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmNIC0_MSTR_IF_AXUSER_BASE 0x5455A80ull
+#define NIC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define NIC0_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmNIC0_MSTR_IF_DBG_HBW_BASE 0x5455B00ull
+#define NIC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC0_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmNIC0_MSTR_IF_DBG_LBW_BASE 0x5455B80ull
+#define NIC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC0_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmNIC0_MSTR_IF_CORE_HBW_BASE 0x5455C00ull
+#define NIC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define NIC0_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmNIC0_MSTR_IF_CORE_LBW_BASE 0x5455D80ull
+#define NIC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define NIC0_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmNIC0_MSTR_IF_SPECIAL_BASE 0x5455E80ull
+#define NIC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmNIC0_TX_AXUSER_BASE 0x5456000ull
+#define NIC0_TX_AXUSER_MAX_OFFSET 0x5000
+#define NIC0_TX_AXUSER_SECTION 0x2000
+#define mmNIC0_SERDES0_BASE 0x5458000ull
+#define NIC0_SERDES0_MAX_OFFSET 0x3E40
+#define NIC0_SERDES0_SECTION 0x4000
+#define mmNIC0_SERDES1_BASE 0x545C000ull
+#define NIC0_SERDES1_MAX_OFFSET 0x3E40
+#define NIC0_SERDES1_SECTION 0x4000
+#define mmNIC0_PHY_BASE 0x5460000ull
+#define NIC0_PHY_MAX_OFFSET 0x1000
+#define NIC0_PHY_SECTION 0xE800
+#define mmNIC0_PHY_SPECIAL_BASE 0x5460E80ull
+#define NIC0_PHY_SPECIAL_MAX_OFFSET 0x1800
+#define NIC0_PHY_SPECIAL_SECTION 0x7180
+#define mmPRT0_MAC_AUX_BASE 0x5468000ull
+#define PRT0_MAC_AUX_MAX_OFFSET 0x1000
+#define PRT0_MAC_AUX_SECTION 0xE800
+#define mmPRT0_MAC_AUX_SPECIAL_BASE 0x5468E80ull
+#define PRT0_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define PRT0_MAC_AUX_SPECIAL_SECTION 0x1800
+#define mmPRT0_MAC_CORE_BASE 0x5469000ull
+#define PRT0_MAC_CORE_MAX_OFFSET 0x1000
+#define PRT0_MAC_CORE_SECTION 0xE800
+#define mmPRT0_MAC_CORE_SPECIAL_BASE 0x5469E80ull
+#define PRT0_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define PRT0_MAC_CORE_SPECIAL_SECTION 0x1800
+#define mmNIC0_MAC_RS_FEC_BASE 0x546A000ull
+#define NIC0_MAC_RS_FEC_MAX_OFFSET 0x2DC0
+#define NIC0_MAC_RS_FEC_SECTION 0x1000
+#define mmNIC0_MAC_GLOB_STAT_CONTROL_REG_BASE 0x546B000ull
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000
+#define NIC0_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000
+#define mmNIC0_MAC_GLOB_STAT_RX0_BASE 0x546B100ull
+#define NIC0_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00
+#define NIC0_MAC_GLOB_STAT_RX0_SECTION 0x8C00
+#define mmNIC0_MAC_GLOB_STAT_RX1_BASE 0x546B18Cull
+#define NIC0_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00
+#define NIC0_MAC_GLOB_STAT_RX1_SECTION 0x8C00
+#define mmNIC0_MAC_GLOB_STAT_RX2_BASE 0x546B218ull
+#define NIC0_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00
+#define NIC0_MAC_GLOB_STAT_RX2_SECTION 0x8C00
+#define mmNIC0_MAC_GLOB_STAT_RX3_BASE 0x546B2A4ull
+#define NIC0_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00
+#define NIC0_MAC_GLOB_STAT_RX3_SECTION 0x8C00
+#define mmNIC0_MAC_GLOB_STAT_TX0_BASE 0x546B330ull
+#define NIC0_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800
+#define NIC0_MAC_GLOB_STAT_TX0_SECTION 0x6800
+#define mmNIC0_MAC_GLOB_STAT_TX1_BASE 0x546B398ull
+#define NIC0_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800
+#define NIC0_MAC_GLOB_STAT_TX1_SECTION 0x6800
+#define mmNIC0_MAC_GLOB_STAT_TX2_BASE 0x546B400ull
+#define NIC0_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800
+#define NIC0_MAC_GLOB_STAT_TX2_SECTION 0x6800
+#define mmNIC0_MAC_GLOB_STAT_TX3_BASE 0x546B468ull
+#define NIC0_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800
+#define NIC0_MAC_GLOB_STAT_TX3_SECTION 0x3980
+#define mmNIC0_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x546B800ull
+#define NIC0_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0
+#define NIC0_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000
+#define mmNIC0_MAC_CH0_MAC_PCS_BASE 0x546C000ull
+#define NIC0_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC0_MAC_CH0_MAC_PCS_SECTION 0x4000
+#define mmNIC0_MAC_CH0_MAC_128_BASE 0x546C400ull
+#define NIC0_MAC_CH0_MAC_128_MAX_OFFSET 0xA400
+#define NIC0_MAC_CH0_MAC_128_SECTION 0x4000
+#define mmNIC0_MAC_CH0_MAC_AN_BASE 0x546C800ull
+#define NIC0_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400
+#define NIC0_MAC_CH0_MAC_AN_SECTION 0x8000
+#define mmNIC0_MAC_CH1_MAC_PCS_BASE 0x546D000ull
+#define NIC0_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC0_MAC_CH1_MAC_PCS_SECTION 0x4000
+#define mmNIC0_MAC_CH1_MAC_128_BASE 0x546D400ull
+#define NIC0_MAC_CH1_MAC_128_MAX_OFFSET 0xA400
+#define NIC0_MAC_CH1_MAC_128_SECTION 0x4000
+#define mmNIC0_MAC_CH1_MAC_AN_BASE 0x546D800ull
+#define NIC0_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400
+#define NIC0_MAC_CH1_MAC_AN_SECTION 0x8000
+#define mmNIC0_MAC_CH2_MAC_PCS_BASE 0x546E000ull
+#define NIC0_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC0_MAC_CH2_MAC_PCS_SECTION 0x4000
+#define mmNIC0_MAC_CH2_MAC_128_BASE 0x546E400ull
+#define NIC0_MAC_CH2_MAC_128_MAX_OFFSET 0xA400
+#define NIC0_MAC_CH2_MAC_128_SECTION 0x4000
+#define mmNIC0_MAC_CH2_MAC_AN_BASE 0x546E800ull
+#define NIC0_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400
+#define NIC0_MAC_CH2_MAC_AN_SECTION 0x8000
+#define mmNIC0_MAC_CH3_MAC_PCS_BASE 0x546F000ull
+#define NIC0_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC0_MAC_CH3_MAC_PCS_SECTION 0x4000
+#define mmNIC0_MAC_CH3_MAC_128_BASE 0x546F400ull
+#define NIC0_MAC_CH3_MAC_128_MAX_OFFSET 0xA400
+#define NIC0_MAC_CH3_MAC_128_SECTION 0x4000
+#define mmNIC0_MAC_CH3_MAC_AN_BASE 0x546F800ull
+#define NIC0_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400
+#define NIC0_MAC_CH3_MAC_AN_SECTION 0x10800
+#define mmNIC1_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5480000ull
+#define NIC1_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC1_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5480080ull
+#define NIC1_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC1_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5480100ull
+#define NIC1_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC1_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5480180ull
+#define NIC1_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC1_UMR0_0_SPECIAL_BASE 0x5480E80ull
+#define NIC1_UMR0_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR0_0_SPECIAL_SECTION 0x1800
+#define mmNIC1_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5481000ull
+#define NIC1_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC1_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5481080ull
+#define NIC1_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC1_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5481100ull
+#define NIC1_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC1_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5481180ull
+#define NIC1_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC1_UMR0_1_SPECIAL_BASE 0x5481E80ull
+#define NIC1_UMR0_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR0_1_SPECIAL_SECTION 0x1800
+#define mmNIC1_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5482000ull
+#define NIC1_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC1_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5482080ull
+#define NIC1_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC1_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5482100ull
+#define NIC1_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC1_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5482180ull
+#define NIC1_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC1_UMR0_2_SPECIAL_BASE 0x5482E80ull
+#define NIC1_UMR0_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR0_2_SPECIAL_SECTION 0x1800
+#define mmNIC1_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5483000ull
+#define NIC1_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC1_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5483080ull
+#define NIC1_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC1_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5483100ull
+#define NIC1_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC1_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5483180ull
+#define NIC1_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC1_UMR0_3_SPECIAL_BASE 0x5483E80ull
+#define NIC1_UMR0_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR0_3_SPECIAL_SECTION 0x1800
+#define mmNIC1_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5484000ull
+#define NIC1_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC1_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5484080ull
+#define NIC1_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC1_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5484100ull
+#define NIC1_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC1_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5484180ull
+#define NIC1_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC1_UMR0_4_SPECIAL_BASE 0x5484E80ull
+#define NIC1_UMR0_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR0_4_SPECIAL_SECTION 0x1800
+#define mmNIC1_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5485000ull
+#define NIC1_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC1_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5485080ull
+#define NIC1_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC1_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5485100ull
+#define NIC1_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC1_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5485180ull
+#define NIC1_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC1_UMR0_5_SPECIAL_BASE 0x5485E80ull
+#define NIC1_UMR0_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR0_5_SPECIAL_SECTION 0x1800
+#define mmNIC1_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5486000ull
+#define NIC1_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC1_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5486080ull
+#define NIC1_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC1_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5486100ull
+#define NIC1_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC1_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5486180ull
+#define NIC1_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC1_UMR0_6_SPECIAL_BASE 0x5486E80ull
+#define NIC1_UMR0_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR0_6_SPECIAL_SECTION 0x1800
+#define mmNIC1_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5487000ull
+#define NIC1_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC1_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5487080ull
+#define NIC1_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC1_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5487100ull
+#define NIC1_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC1_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5487180ull
+#define NIC1_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC1_UMR0_7_SPECIAL_BASE 0x5487E80ull
+#define NIC1_UMR0_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR0_7_SPECIAL_SECTION 0x1800
+#define mmNIC1_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5488000ull
+#define NIC1_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC1_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5488080ull
+#define NIC1_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC1_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5488100ull
+#define NIC1_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC1_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5488180ull
+#define NIC1_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC1_UMR0_8_SPECIAL_BASE 0x5488E80ull
+#define NIC1_UMR0_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR0_8_SPECIAL_SECTION 0x1800
+#define mmNIC1_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5489000ull
+#define NIC1_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC1_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5489080ull
+#define NIC1_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC1_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5489100ull
+#define NIC1_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC1_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5489180ull
+#define NIC1_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC1_UMR0_9_SPECIAL_BASE 0x5489E80ull
+#define NIC1_UMR0_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR0_9_SPECIAL_SECTION 0x1800
+#define mmNIC1_UMR0_10_UNSECURE_DOORBELL0_BASE 0x548A000ull
+#define NIC1_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC1_UMR0_10_UNSECURE_DOORBELL1_BASE 0x548A080ull
+#define NIC1_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC1_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x548A100ull
+#define NIC1_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC1_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x548A180ull
+#define NIC1_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC1_UMR0_10_SPECIAL_BASE 0x548AE80ull
+#define NIC1_UMR0_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR0_10_SPECIAL_SECTION 0x1800
+#define mmNIC1_UMR0_11_UNSECURE_DOORBELL0_BASE 0x548B000ull
+#define NIC1_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC1_UMR0_11_UNSECURE_DOORBELL1_BASE 0x548B080ull
+#define NIC1_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC1_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x548B100ull
+#define NIC1_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC1_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x548B180ull
+#define NIC1_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC1_UMR0_11_SPECIAL_BASE 0x548BE80ull
+#define NIC1_UMR0_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR0_11_SPECIAL_SECTION 0x1800
+#define mmNIC1_UMR0_12_UNSECURE_DOORBELL0_BASE 0x548C000ull
+#define NIC1_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC1_UMR0_12_UNSECURE_DOORBELL1_BASE 0x548C080ull
+#define NIC1_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC1_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x548C100ull
+#define NIC1_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC1_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x548C180ull
+#define NIC1_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC1_UMR0_12_SPECIAL_BASE 0x548CE80ull
+#define NIC1_UMR0_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR0_12_SPECIAL_SECTION 0x1800
+#define mmNIC1_UMR0_13_UNSECURE_DOORBELL0_BASE 0x548D000ull
+#define NIC1_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC1_UMR0_13_UNSECURE_DOORBELL1_BASE 0x548D080ull
+#define NIC1_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC1_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x548D100ull
+#define NIC1_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC1_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x548D180ull
+#define NIC1_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC1_UMR0_13_SPECIAL_BASE 0x548DE80ull
+#define NIC1_UMR0_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR0_13_SPECIAL_SECTION 0x1800
+#define mmNIC1_UMR0_14_UNSECURE_DOORBELL0_BASE 0x548E000ull
+#define NIC1_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC1_UMR0_14_UNSECURE_DOORBELL1_BASE 0x548E080ull
+#define NIC1_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC1_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x548E100ull
+#define NIC1_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC1_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x548E180ull
+#define NIC1_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC1_UMR0_14_SPECIAL_BASE 0x548EE80ull
+#define NIC1_UMR0_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR0_14_SPECIAL_SECTION 0x1180
+#define mmNIC1_QM_DCCM0_BASE 0x5490000ull
+#define NIC1_QM_DCCM0_MAX_OFFSET 0x4000
+#define NIC1_QM_DCCM0_SECTION 0x8000
+#define mmNIC1_QM_ARC_AUX0_BASE 0x5498000ull
+#define NIC1_QM_ARC_AUX0_MAX_OFFSET 0x1000
+#define NIC1_QM_ARC_AUX0_SECTION 0xE800
+#define mmNIC1_QM_ARC_AUX0_SPECIAL_BASE 0x5498E80ull
+#define NIC1_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_QM_ARC_AUX0_SPECIAL_SECTION 0x1180
+#define mmNIC1_QM0_BASE 0x549A000ull
+#define NIC1_QM0_MAX_OFFSET 0x1000
+#define NIC1_QM0_SECTION 0x9000
+#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x549A900ull
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x549A908ull
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x549A910ull
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x549A918ull
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x549A920ull
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x549A928ull
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x549A930ull
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x549A938ull
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x549A940ull
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x549A948ull
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x549A950ull
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x549A958ull
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x549A960ull
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x549A968ull
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x549A970ull
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x549A978ull
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC1_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmNIC1_QM0_AXUSER_SECURED_BASE 0x549AB00ull
+#define NIC1_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC1_QM0_AXUSER_SECURED_SECTION 0x8000
+#define mmNIC1_QM0_AXUSER_NONSECURED_BASE 0x549AB80ull
+#define NIC1_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC1_QM0_AXUSER_NONSECURED_SECTION 0x8000
+#define mmNIC1_QM0_DBG_HBW_BASE 0x549AC00ull
+#define NIC1_QM0_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC1_QM0_DBG_HBW_SECTION 0x8000
+#define mmNIC1_QM0_DBG_LBW_BASE 0x549AC80ull
+#define NIC1_QM0_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC1_QM0_DBG_LBW_SECTION 0x1000
+#define mmNIC1_QM0_CGM_BASE 0x549AD80ull
+#define NIC1_QM0_CGM_MAX_OFFSET 0xC000
+#define NIC1_QM0_CGM_SECTION 0x1000
+#define mmNIC1_QM0_SPECIAL_BASE 0x549AE80ull
+#define NIC1_QM0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_QM0_SPECIAL_SECTION 0x4180
+#define mmNIC1_QPC0_BASE 0x549F000ull
+#define NIC1_QPC0_MAX_OFFSET 0x1000
+#define NIC1_QPC0_SECTION 0x7200
+#define mmNIC1_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x549F720ull
+#define NIC1_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x549F728ull
+#define NIC1_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x549F730ull
+#define NIC1_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x549F738ull
+#define NIC1_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x549F740ull
+#define NIC1_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x549F748ull
+#define NIC1_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x549F750ull
+#define NIC1_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x549F758ull
+#define NIC1_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x549F760ull
+#define NIC1_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x549F768ull
+#define NIC1_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x549F770ull
+#define NIC1_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x549F778ull
+#define NIC1_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x549F780ull
+#define NIC1_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x549F788ull
+#define NIC1_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x549F790ull
+#define NIC1_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x549F798ull
+#define NIC1_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x549F7A0ull
+#define NIC1_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x549F7A8ull
+#define NIC1_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x549F7B0ull
+#define NIC1_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x549F7B8ull
+#define NIC1_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x549F7C0ull
+#define NIC1_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x549F7C8ull
+#define NIC1_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x549F7D0ull
+#define NIC1_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x549F7D8ull
+#define NIC1_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x549F7E0ull
+#define NIC1_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x549F7E8ull
+#define NIC1_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x549F7F0ull
+#define NIC1_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x549F7F8ull
+#define NIC1_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x549F800ull
+#define NIC1_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x549F808ull
+#define NIC1_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x549F810ull
+#define NIC1_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x549F818ull
+#define NIC1_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define mmNIC1_QPC0_AXUSER_CONG_QUE_BASE 0x549FB80ull
+#define NIC1_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC1_QPC0_AXUSER_CONG_QUE_SECTION 0x6000
+#define mmNIC1_QPC0_AXUSER_RXWQE_BASE 0x549FBE0ull
+#define NIC1_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC1_QPC0_AXUSER_RXWQE_SECTION 0x6000
+#define mmNIC1_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x549FC40ull
+#define NIC1_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC1_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define mmNIC1_QPC0_AXUSER_DB_FIFO_BASE 0x549FCA0ull
+#define NIC1_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC1_QPC0_AXUSER_DB_FIFO_SECTION 0x6000
+#define mmNIC1_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x549FD00ull
+#define NIC1_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC1_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define mmNIC1_QPC0_AXUSER_ERR_FIFO_BASE 0x549FD60ull
+#define NIC1_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC1_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000
+#define mmNIC1_QPC0_AXUSER_QPC_RESP_BASE 0x549FDC0ull
+#define NIC1_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC1_QPC0_AXUSER_QPC_RESP_SECTION 0x6000
+#define mmNIC1_QPC0_AXUSER_QPC_REQ_BASE 0x549FE20ull
+#define NIC1_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC1_QPC0_AXUSER_QPC_REQ_SECTION 0x6000
+#define mmNIC1_QPC0_SPECIAL_BASE 0x549FE80ull
+#define NIC1_QPC0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_QPC0_SPECIAL_SECTION 0x1800
+#define mmNIC1_UMR1_0_UNSECURE_DOORBELL0_BASE 0x54A0000ull
+#define NIC1_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC1_UMR1_0_UNSECURE_DOORBELL1_BASE 0x54A0080ull
+#define NIC1_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC1_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x54A0100ull
+#define NIC1_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC1_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x54A0180ull
+#define NIC1_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC1_UMR1_0_SPECIAL_BASE 0x54A0E80ull
+#define NIC1_UMR1_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR1_0_SPECIAL_SECTION 0x1800
+#define mmNIC1_UMR1_1_UNSECURE_DOORBELL0_BASE 0x54A1000ull
+#define NIC1_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC1_UMR1_1_UNSECURE_DOORBELL1_BASE 0x54A1080ull
+#define NIC1_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC1_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x54A1100ull
+#define NIC1_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC1_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x54A1180ull
+#define NIC1_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC1_UMR1_1_SPECIAL_BASE 0x54A1E80ull
+#define NIC1_UMR1_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR1_1_SPECIAL_SECTION 0x1800
+#define mmNIC1_UMR1_2_UNSECURE_DOORBELL0_BASE 0x54A2000ull
+#define NIC1_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC1_UMR1_2_UNSECURE_DOORBELL1_BASE 0x54A2080ull
+#define NIC1_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC1_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x54A2100ull
+#define NIC1_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC1_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x54A2180ull
+#define NIC1_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC1_UMR1_2_SPECIAL_BASE 0x54A2E80ull
+#define NIC1_UMR1_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR1_2_SPECIAL_SECTION 0x1800
+#define mmNIC1_UMR1_3_UNSECURE_DOORBELL0_BASE 0x54A3000ull
+#define NIC1_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC1_UMR1_3_UNSECURE_DOORBELL1_BASE 0x54A3080ull
+#define NIC1_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC1_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x54A3100ull
+#define NIC1_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC1_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x54A3180ull
+#define NIC1_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC1_UMR1_3_SPECIAL_BASE 0x54A3E80ull
+#define NIC1_UMR1_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR1_3_SPECIAL_SECTION 0x1800
+#define mmNIC1_UMR1_4_UNSECURE_DOORBELL0_BASE 0x54A4000ull
+#define NIC1_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC1_UMR1_4_UNSECURE_DOORBELL1_BASE 0x54A4080ull
+#define NIC1_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC1_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x54A4100ull
+#define NIC1_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC1_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x54A4180ull
+#define NIC1_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC1_UMR1_4_SPECIAL_BASE 0x54A4E80ull
+#define NIC1_UMR1_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR1_4_SPECIAL_SECTION 0x1800
+#define mmNIC1_UMR1_5_UNSECURE_DOORBELL0_BASE 0x54A5000ull
+#define NIC1_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC1_UMR1_5_UNSECURE_DOORBELL1_BASE 0x54A5080ull
+#define NIC1_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC1_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x54A5100ull
+#define NIC1_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC1_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x54A5180ull
+#define NIC1_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC1_UMR1_5_SPECIAL_BASE 0x54A5E80ull
+#define NIC1_UMR1_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR1_5_SPECIAL_SECTION 0x1800
+#define mmNIC1_UMR1_6_UNSECURE_DOORBELL0_BASE 0x54A6000ull
+#define NIC1_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC1_UMR1_6_UNSECURE_DOORBELL1_BASE 0x54A6080ull
+#define NIC1_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC1_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x54A6100ull
+#define NIC1_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC1_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x54A6180ull
+#define NIC1_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC1_UMR1_6_SPECIAL_BASE 0x54A6E80ull
+#define NIC1_UMR1_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR1_6_SPECIAL_SECTION 0x1800
+#define mmNIC1_UMR1_7_UNSECURE_DOORBELL0_BASE 0x54A7000ull
+#define NIC1_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC1_UMR1_7_UNSECURE_DOORBELL1_BASE 0x54A7080ull
+#define NIC1_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC1_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x54A7100ull
+#define NIC1_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC1_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x54A7180ull
+#define NIC1_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC1_UMR1_7_SPECIAL_BASE 0x54A7E80ull
+#define NIC1_UMR1_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR1_7_SPECIAL_SECTION 0x1800
+#define mmNIC1_UMR1_8_UNSECURE_DOORBELL0_BASE 0x54A8000ull
+#define NIC1_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC1_UMR1_8_UNSECURE_DOORBELL1_BASE 0x54A8080ull
+#define NIC1_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC1_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x54A8100ull
+#define NIC1_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC1_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x54A8180ull
+#define NIC1_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC1_UMR1_8_SPECIAL_BASE 0x54A8E80ull
+#define NIC1_UMR1_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR1_8_SPECIAL_SECTION 0x1800
+#define mmNIC1_UMR1_9_UNSECURE_DOORBELL0_BASE 0x54A9000ull
+#define NIC1_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC1_UMR1_9_UNSECURE_DOORBELL1_BASE 0x54A9080ull
+#define NIC1_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC1_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x54A9100ull
+#define NIC1_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC1_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x54A9180ull
+#define NIC1_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC1_UMR1_9_SPECIAL_BASE 0x54A9E80ull
+#define NIC1_UMR1_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR1_9_SPECIAL_SECTION 0x1800
+#define mmNIC1_UMR1_10_UNSECURE_DOORBELL0_BASE 0x54AA000ull
+#define NIC1_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC1_UMR1_10_UNSECURE_DOORBELL1_BASE 0x54AA080ull
+#define NIC1_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC1_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x54AA100ull
+#define NIC1_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC1_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x54AA180ull
+#define NIC1_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC1_UMR1_10_SPECIAL_BASE 0x54AAE80ull
+#define NIC1_UMR1_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR1_10_SPECIAL_SECTION 0x1800
+#define mmNIC1_UMR1_11_UNSECURE_DOORBELL0_BASE 0x54AB000ull
+#define NIC1_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC1_UMR1_11_UNSECURE_DOORBELL1_BASE 0x54AB080ull
+#define NIC1_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC1_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x54AB100ull
+#define NIC1_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC1_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x54AB180ull
+#define NIC1_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC1_UMR1_11_SPECIAL_BASE 0x54ABE80ull
+#define NIC1_UMR1_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR1_11_SPECIAL_SECTION 0x1800
+#define mmNIC1_UMR1_12_UNSECURE_DOORBELL0_BASE 0x54AC000ull
+#define NIC1_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC1_UMR1_12_UNSECURE_DOORBELL1_BASE 0x54AC080ull
+#define NIC1_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC1_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x54AC100ull
+#define NIC1_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC1_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x54AC180ull
+#define NIC1_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC1_UMR1_12_SPECIAL_BASE 0x54ACE80ull
+#define NIC1_UMR1_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR1_12_SPECIAL_SECTION 0x1800
+#define mmNIC1_UMR1_13_UNSECURE_DOORBELL0_BASE 0x54AD000ull
+#define NIC1_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC1_UMR1_13_UNSECURE_DOORBELL1_BASE 0x54AD080ull
+#define NIC1_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC1_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x54AD100ull
+#define NIC1_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC1_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x54AD180ull
+#define NIC1_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC1_UMR1_13_SPECIAL_BASE 0x54ADE80ull
+#define NIC1_UMR1_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR1_13_SPECIAL_SECTION 0x1800
+#define mmNIC1_UMR1_14_UNSECURE_DOORBELL0_BASE 0x54AE000ull
+#define NIC1_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC1_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC1_UMR1_14_UNSECURE_DOORBELL1_BASE 0x54AE080ull
+#define NIC1_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC1_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC1_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x54AE100ull
+#define NIC1_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC1_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC1_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x54AE180ull
+#define NIC1_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC1_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC1_UMR1_14_SPECIAL_BASE 0x54AEE80ull
+#define NIC1_UMR1_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_UMR1_14_SPECIAL_SECTION 0x1180
+#define mmNIC1_QM_DCCM1_BASE 0x54B0000ull
+#define NIC1_QM_DCCM1_MAX_OFFSET 0x4000
+#define NIC1_QM_DCCM1_SECTION 0x8000
+#define mmNIC1_QM_ARC_AUX1_BASE 0x54B8000ull
+#define NIC1_QM_ARC_AUX1_MAX_OFFSET 0x1000
+#define NIC1_QM_ARC_AUX1_SECTION 0xE800
+#define mmNIC1_QM_ARC_AUX1_SPECIAL_BASE 0x54B8E80ull
+#define NIC1_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_QM_ARC_AUX1_SPECIAL_SECTION 0x1180
+#define mmNIC1_QM1_BASE 0x54BA000ull
+#define NIC1_QM1_MAX_OFFSET 0x1000
+#define NIC1_QM1_SECTION 0x9000
+#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x54BA900ull
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x54BA908ull
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x54BA910ull
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x54BA918ull
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x54BA920ull
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x54BA928ull
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x54BA930ull
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x54BA938ull
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x54BA940ull
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x54BA948ull
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x54BA950ull
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x54BA958ull
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x54BA960ull
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x54BA968ull
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x54BA970ull
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x54BA978ull
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC1_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmNIC1_QM1_AXUSER_SECURED_BASE 0x54BAB00ull
+#define NIC1_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC1_QM1_AXUSER_SECURED_SECTION 0x8000
+#define mmNIC1_QM1_AXUSER_NONSECURED_BASE 0x54BAB80ull
+#define NIC1_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC1_QM1_AXUSER_NONSECURED_SECTION 0x8000
+#define mmNIC1_QM1_DBG_HBW_BASE 0x54BAC00ull
+#define NIC1_QM1_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC1_QM1_DBG_HBW_SECTION 0x8000
+#define mmNIC1_QM1_DBG_LBW_BASE 0x54BAC80ull
+#define NIC1_QM1_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC1_QM1_DBG_LBW_SECTION 0x1000
+#define mmNIC1_QM1_CGM_BASE 0x54BAD80ull
+#define NIC1_QM1_CGM_MAX_OFFSET 0xC000
+#define NIC1_QM1_CGM_SECTION 0x1000
+#define mmNIC1_QM1_SPECIAL_BASE 0x54BAE80ull
+#define NIC1_QM1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_QM1_SPECIAL_SECTION 0x4180
+#define mmNIC1_QPC1_BASE 0x54BF000ull
+#define NIC1_QPC1_MAX_OFFSET 0x1000
+#define NIC1_QPC1_SECTION 0x7200
+#define mmNIC1_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x54BF720ull
+#define NIC1_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x54BF728ull
+#define NIC1_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x54BF730ull
+#define NIC1_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x54BF738ull
+#define NIC1_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x54BF740ull
+#define NIC1_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x54BF748ull
+#define NIC1_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x54BF750ull
+#define NIC1_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x54BF758ull
+#define NIC1_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x54BF760ull
+#define NIC1_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x54BF768ull
+#define NIC1_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x54BF770ull
+#define NIC1_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x54BF778ull
+#define NIC1_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x54BF780ull
+#define NIC1_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x54BF788ull
+#define NIC1_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x54BF790ull
+#define NIC1_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x54BF798ull
+#define NIC1_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x54BF7A0ull
+#define NIC1_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x54BF7A8ull
+#define NIC1_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x54BF7B0ull
+#define NIC1_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x54BF7B8ull
+#define NIC1_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x54BF7C0ull
+#define NIC1_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x54BF7C8ull
+#define NIC1_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x54BF7D0ull
+#define NIC1_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x54BF7D8ull
+#define NIC1_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x54BF7E0ull
+#define NIC1_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x54BF7E8ull
+#define NIC1_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x54BF7F0ull
+#define NIC1_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x54BF7F8ull
+#define NIC1_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x54BF800ull
+#define NIC1_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x54BF808ull
+#define NIC1_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x54BF810ull
+#define NIC1_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC1_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x54BF818ull
+#define NIC1_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC1_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define mmNIC1_QPC1_AXUSER_CONG_QUE_BASE 0x54BFB80ull
+#define NIC1_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC1_QPC1_AXUSER_CONG_QUE_SECTION 0x6000
+#define mmNIC1_QPC1_AXUSER_RXWQE_BASE 0x54BFBE0ull
+#define NIC1_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC1_QPC1_AXUSER_RXWQE_SECTION 0x6000
+#define mmNIC1_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x54BFC40ull
+#define NIC1_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC1_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define mmNIC1_QPC1_AXUSER_DB_FIFO_BASE 0x54BFCA0ull
+#define NIC1_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC1_QPC1_AXUSER_DB_FIFO_SECTION 0x6000
+#define mmNIC1_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x54BFD00ull
+#define NIC1_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC1_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define mmNIC1_QPC1_AXUSER_ERR_FIFO_BASE 0x54BFD60ull
+#define NIC1_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC1_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000
+#define mmNIC1_QPC1_AXUSER_QPC_RESP_BASE 0x54BFDC0ull
+#define NIC1_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC1_QPC1_AXUSER_QPC_RESP_SECTION 0x6000
+#define mmNIC1_QPC1_AXUSER_QPC_REQ_BASE 0x54BFE20ull
+#define NIC1_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC1_QPC1_AXUSER_QPC_REQ_SECTION 0x6000
+#define mmNIC1_QPC1_SPECIAL_BASE 0x54BFE80ull
+#define NIC1_QPC1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_QPC1_SPECIAL_SECTION 0x8180
+#define mmNIC1_TMR_BASE 0x54C8000ull
+#define NIC1_TMR_MAX_OFFSET 0x1000
+#define NIC1_TMR_SECTION 0xD600
+#define mmNIC1_TMR_AXUSER_TMR_FREE_LIST_BASE 0x54C8D60ull
+#define NIC1_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000
+#define NIC1_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000
+#define mmNIC1_TMR_AXUSER_TMR_FIFO_BASE 0x54C8DC0ull
+#define NIC1_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000
+#define NIC1_TMR_AXUSER_TMR_FIFO_SECTION 0x6000
+#define mmNIC1_TMR_AXUSER_TMR_FSM_BASE 0x54C8E20ull
+#define NIC1_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000
+#define NIC1_TMR_AXUSER_TMR_FSM_SECTION 0x6000
+#define mmNIC1_TMR_SPECIAL_BASE 0x54C8E80ull
+#define NIC1_TMR_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_TMR_SPECIAL_SECTION 0x1800
+#define mmNIC1_RXB_CORE_BASE 0x54C9000ull
+#define NIC1_RXB_CORE_MAX_OFFSET 0x1000
+#define NIC1_RXB_CORE_SECTION 0x6100
+#define mmNIC1_RXB_CORE_SCT_AWUSER_BASE 0x54C9610ull
+#define NIC1_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000
+#define NIC1_RXB_CORE_SCT_AWUSER_SECTION 0x8700
+#define mmNIC1_RXB_CORE_SPECIAL_BASE 0x54C9E80ull
+#define NIC1_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_RXB_CORE_SPECIAL_SECTION 0x1800
+#define mmNIC1_RXE0_BASE 0x54CA000ull
+#define NIC1_RXE0_MAX_OFFSET 0x1000
+#define NIC1_RXE0_SECTION 0x9000
+#define mmNIC1_RXE0_WQE_ARUSER_BASE 0x54CA900ull
+#define NIC1_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC1_RXE0_WQE_ARUSER_SECTION 0x5800
+#define mmNIC1_RXE0_SPECIAL_BASE 0x54CAE80ull
+#define NIC1_RXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_RXE0_SPECIAL_SECTION 0x1800
+#define mmNIC1_RXE1_BASE 0x54CB000ull
+#define NIC1_RXE1_MAX_OFFSET 0x1000
+#define NIC1_RXE1_SECTION 0x9000
+#define mmNIC1_RXE1_WQE_ARUSER_BASE 0x54CB900ull
+#define NIC1_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC1_RXE1_WQE_ARUSER_SECTION 0x5800
+#define mmNIC1_RXE1_SPECIAL_BASE 0x54CBE80ull
+#define NIC1_RXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_RXE1_SPECIAL_SECTION 0x1800
+#define mmNIC1_RXE0_AXUSER_AXUSER_CQ0_BASE 0x54CC000ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define mmNIC1_RXE0_AXUSER_AXUSER_CQ1_BASE 0x54CC050ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define mmNIC1_RXE0_AXUSER_AXUSER_CQ2_BASE 0x54CC0A0ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define mmNIC1_RXE0_AXUSER_AXUSER_CQ3_BASE 0x54CC0F0ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define mmNIC1_RXE0_AXUSER_AXUSER_CQ4_BASE 0x54CC140ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define mmNIC1_RXE0_AXUSER_AXUSER_CQ5_BASE 0x54CC190ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define mmNIC1_RXE0_AXUSER_AXUSER_CQ6_BASE 0x54CC1E0ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define mmNIC1_RXE0_AXUSER_AXUSER_CQ7_BASE 0x54CC230ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define mmNIC1_RXE0_AXUSER_AXUSER_CQ8_BASE 0x54CC280ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define mmNIC1_RXE0_AXUSER_AXUSER_CQ9_BASE 0x54CC2D0ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define mmNIC1_RXE0_AXUSER_AXUSER_CQ10_BASE 0x54CC320ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define mmNIC1_RXE0_AXUSER_AXUSER_CQ11_BASE 0x54CC370ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define mmNIC1_RXE0_AXUSER_AXUSER_CQ12_BASE 0x54CC3C0ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define mmNIC1_RXE0_AXUSER_AXUSER_CQ13_BASE 0x54CC410ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define mmNIC1_RXE0_AXUSER_AXUSER_CQ14_BASE 0x54CC460ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define mmNIC1_RXE0_AXUSER_AXUSER_CQ15_BASE 0x54CC4B0ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define mmNIC1_RXE0_AXUSER_AXUSER_CQ16_BASE 0x54CC500ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define mmNIC1_RXE0_AXUSER_AXUSER_CQ17_BASE 0x54CC550ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define mmNIC1_RXE0_AXUSER_AXUSER_CQ18_BASE 0x54CC5A0ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define mmNIC1_RXE0_AXUSER_AXUSER_CQ19_BASE 0x54CC5F0ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define mmNIC1_RXE0_AXUSER_AXUSER_CQ20_BASE 0x54CC640ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define mmNIC1_RXE0_AXUSER_AXUSER_CQ21_BASE 0x54CC690ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define mmNIC1_RXE0_AXUSER_AXUSER_CQ22_BASE 0x54CC6E0ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define mmNIC1_RXE0_AXUSER_AXUSER_CQ23_BASE 0x54CC730ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define mmNIC1_RXE0_AXUSER_AXUSER_CQ24_BASE 0x54CC780ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define mmNIC1_RXE0_AXUSER_AXUSER_CQ25_BASE 0x54CC7D0ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define mmNIC1_RXE0_AXUSER_AXUSER_CQ26_BASE 0x54CC820ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define mmNIC1_RXE0_AXUSER_AXUSER_CQ27_BASE 0x54CC870ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define mmNIC1_RXE0_AXUSER_AXUSER_CQ28_BASE 0x54CC8C0ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define mmNIC1_RXE0_AXUSER_AXUSER_CQ29_BASE 0x54CC910ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define mmNIC1_RXE0_AXUSER_AXUSER_CQ30_BASE 0x54CC960ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define mmNIC1_RXE0_AXUSER_AXUSER_CQ31_BASE 0x54CC9B0ull
+#define NIC1_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC1_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define mmNIC1_RXE0_AXUSER_SPECIAL_BASE 0x54CCE80ull
+#define NIC1_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_RXE0_AXUSER_SPECIAL_SECTION 0x1800
+#define mmNIC1_RXE1_AXUSER_AXUSER_CQ0_BASE 0x54CD000ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define mmNIC1_RXE1_AXUSER_AXUSER_CQ1_BASE 0x54CD050ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define mmNIC1_RXE1_AXUSER_AXUSER_CQ2_BASE 0x54CD0A0ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define mmNIC1_RXE1_AXUSER_AXUSER_CQ3_BASE 0x54CD0F0ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define mmNIC1_RXE1_AXUSER_AXUSER_CQ4_BASE 0x54CD140ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define mmNIC1_RXE1_AXUSER_AXUSER_CQ5_BASE 0x54CD190ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define mmNIC1_RXE1_AXUSER_AXUSER_CQ6_BASE 0x54CD1E0ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define mmNIC1_RXE1_AXUSER_AXUSER_CQ7_BASE 0x54CD230ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define mmNIC1_RXE1_AXUSER_AXUSER_CQ8_BASE 0x54CD280ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define mmNIC1_RXE1_AXUSER_AXUSER_CQ9_BASE 0x54CD2D0ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define mmNIC1_RXE1_AXUSER_AXUSER_CQ10_BASE 0x54CD320ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define mmNIC1_RXE1_AXUSER_AXUSER_CQ11_BASE 0x54CD370ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define mmNIC1_RXE1_AXUSER_AXUSER_CQ12_BASE 0x54CD3C0ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define mmNIC1_RXE1_AXUSER_AXUSER_CQ13_BASE 0x54CD410ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define mmNIC1_RXE1_AXUSER_AXUSER_CQ14_BASE 0x54CD460ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define mmNIC1_RXE1_AXUSER_AXUSER_CQ15_BASE 0x54CD4B0ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define mmNIC1_RXE1_AXUSER_AXUSER_CQ16_BASE 0x54CD500ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define mmNIC1_RXE1_AXUSER_AXUSER_CQ17_BASE 0x54CD550ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define mmNIC1_RXE1_AXUSER_AXUSER_CQ18_BASE 0x54CD5A0ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define mmNIC1_RXE1_AXUSER_AXUSER_CQ19_BASE 0x54CD5F0ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define mmNIC1_RXE1_AXUSER_AXUSER_CQ20_BASE 0x54CD640ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define mmNIC1_RXE1_AXUSER_AXUSER_CQ21_BASE 0x54CD690ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define mmNIC1_RXE1_AXUSER_AXUSER_CQ22_BASE 0x54CD6E0ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define mmNIC1_RXE1_AXUSER_AXUSER_CQ23_BASE 0x54CD730ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define mmNIC1_RXE1_AXUSER_AXUSER_CQ24_BASE 0x54CD780ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define mmNIC1_RXE1_AXUSER_AXUSER_CQ25_BASE 0x54CD7D0ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define mmNIC1_RXE1_AXUSER_AXUSER_CQ26_BASE 0x54CD820ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define mmNIC1_RXE1_AXUSER_AXUSER_CQ27_BASE 0x54CD870ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define mmNIC1_RXE1_AXUSER_AXUSER_CQ28_BASE 0x54CD8C0ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define mmNIC1_RXE1_AXUSER_AXUSER_CQ29_BASE 0x54CD910ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define mmNIC1_RXE1_AXUSER_AXUSER_CQ30_BASE 0x54CD960ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define mmNIC1_RXE1_AXUSER_AXUSER_CQ31_BASE 0x54CD9B0ull
+#define NIC1_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC1_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define mmNIC1_RXE1_AXUSER_SPECIAL_BASE 0x54CDE80ull
+#define NIC1_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_RXE1_AXUSER_SPECIAL_SECTION 0x2180
+#define mmNIC1_TXS0_BASE 0x54D0000ull
+#define NIC1_TXS0_MAX_OFFSET 0x1000
+#define NIC1_TXS0_SECTION 0xE800
+#define mmNIC1_TXS0_SPECIAL_BASE 0x54D0E80ull
+#define NIC1_TXS0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_TXS0_SPECIAL_SECTION 0x1800
+#define mmNIC1_TXS1_BASE 0x54D1000ull
+#define NIC1_TXS1_MAX_OFFSET 0x1000
+#define NIC1_TXS1_SECTION 0xE800
+#define mmNIC1_TXS1_SPECIAL_BASE 0x54D1E80ull
+#define NIC1_TXS1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_TXS1_SPECIAL_SECTION 0x1800
+#define mmNIC1_TXE0_BASE 0x54D2000ull
+#define NIC1_TXE0_MAX_OFFSET 0x1000
+#define NIC1_TXE0_SECTION 0xE800
+#define mmNIC1_TXE0_SPECIAL_BASE 0x54D2E80ull
+#define NIC1_TXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_TXE0_SPECIAL_SECTION 0x1800
+#define mmNIC1_TXE1_BASE 0x54D3000ull
+#define NIC1_TXE1_MAX_OFFSET 0x1000
+#define NIC1_TXE1_SECTION 0xE800
+#define mmNIC1_TXE1_SPECIAL_BASE 0x54D3E80ull
+#define NIC1_TXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_TXE1_SPECIAL_SECTION 0x1800
+#define mmNIC1_TXB_BASE 0x54D4000ull
+#define NIC1_TXB_MAX_OFFSET 0x1000
+#define NIC1_TXB_SECTION 0xE800
+#define mmNIC1_TXB_SPECIAL_BASE 0x54D4E80ull
+#define NIC1_TXB_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_TXB_SPECIAL_SECTION 0x1800
+#define mmNIC1_MSTR_IF_RR_SHRD_HBW_BASE 0x54D5000ull
+#define NIC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define NIC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmNIC1_MSTR_IF_RR_PRVT_HBW_BASE 0x54D5200ull
+#define NIC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define NIC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmNIC1_MSTR_IF_RR_SHRD_LBW_BASE 0x54D5400ull
+#define NIC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define NIC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmNIC1_MSTR_IF_RR_PRVT_LBW_BASE 0x54D5600ull
+#define NIC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define NIC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmNIC1_MSTR_IF_E2E_CRDT_BASE 0x54D5800ull
+#define NIC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define NIC1_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmNIC1_MSTR_IF_AXUSER_BASE 0x54D5A80ull
+#define NIC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define NIC1_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmNIC1_MSTR_IF_DBG_HBW_BASE 0x54D5B00ull
+#define NIC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC1_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmNIC1_MSTR_IF_DBG_LBW_BASE 0x54D5B80ull
+#define NIC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC1_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmNIC1_MSTR_IF_CORE_HBW_BASE 0x54D5C00ull
+#define NIC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define NIC1_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmNIC1_MSTR_IF_CORE_LBW_BASE 0x54D5D80ull
+#define NIC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define NIC1_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmNIC1_MSTR_IF_SPECIAL_BASE 0x54D5E80ull
+#define NIC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmNIC1_TX_AXUSER_BASE 0x54D6000ull
+#define NIC1_TX_AXUSER_MAX_OFFSET 0x5000
+#define NIC1_TX_AXUSER_SECTION 0x2000
+#define mmNIC1_SERDES0_BASE 0x54D8000ull
+#define NIC1_SERDES0_MAX_OFFSET 0x3E40
+#define NIC1_SERDES0_SECTION 0x4000
+#define mmNIC1_SERDES1_BASE 0x54DC000ull
+#define NIC1_SERDES1_MAX_OFFSET 0x3E40
+#define NIC1_SERDES1_SECTION 0x4000
+#define mmNIC1_PHY_BASE 0x54E0000ull
+#define NIC1_PHY_MAX_OFFSET 0x1000
+#define NIC1_PHY_SECTION 0xE800
+#define mmNIC1_PHY_SPECIAL_BASE 0x54E0E80ull
+#define NIC1_PHY_SPECIAL_MAX_OFFSET 0x1800
+#define NIC1_PHY_SPECIAL_SECTION 0x7180
+#define mmPRT1_MAC_AUX_BASE 0x54E8000ull
+#define PRT1_MAC_AUX_MAX_OFFSET 0x1000
+#define PRT1_MAC_AUX_SECTION 0xE800
+#define mmPRT1_MAC_AUX_SPECIAL_BASE 0x54E8E80ull
+#define PRT1_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define PRT1_MAC_AUX_SPECIAL_SECTION 0x1800
+#define mmPRT1_MAC_CORE_BASE 0x54E9000ull
+#define PRT1_MAC_CORE_MAX_OFFSET 0x1000
+#define PRT1_MAC_CORE_SECTION 0xE800
+#define mmPRT1_MAC_CORE_SPECIAL_BASE 0x54E9E80ull
+#define PRT1_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define PRT1_MAC_CORE_SPECIAL_SECTION 0x1800
+#define mmNIC1_MAC_RS_FEC_BASE 0x54EA000ull
+#define NIC1_MAC_RS_FEC_MAX_OFFSET 0x2DC0
+#define NIC1_MAC_RS_FEC_SECTION 0x1000
+#define mmNIC1_MAC_GLOB_STAT_CONTROL_REG_BASE 0x54EB000ull
+#define NIC1_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000
+#define NIC1_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000
+#define mmNIC1_MAC_GLOB_STAT_RX0_BASE 0x54EB100ull
+#define NIC1_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00
+#define NIC1_MAC_GLOB_STAT_RX0_SECTION 0x8C00
+#define mmNIC1_MAC_GLOB_STAT_RX1_BASE 0x54EB18Cull
+#define NIC1_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00
+#define NIC1_MAC_GLOB_STAT_RX1_SECTION 0x8C00
+#define mmNIC1_MAC_GLOB_STAT_RX2_BASE 0x54EB218ull
+#define NIC1_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00
+#define NIC1_MAC_GLOB_STAT_RX2_SECTION 0x8C00
+#define mmNIC1_MAC_GLOB_STAT_RX3_BASE 0x54EB2A4ull
+#define NIC1_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00
+#define NIC1_MAC_GLOB_STAT_RX3_SECTION 0x8C00
+#define mmNIC1_MAC_GLOB_STAT_TX0_BASE 0x54EB330ull
+#define NIC1_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800
+#define NIC1_MAC_GLOB_STAT_TX0_SECTION 0x6800
+#define mmNIC1_MAC_GLOB_STAT_TX1_BASE 0x54EB398ull
+#define NIC1_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800
+#define NIC1_MAC_GLOB_STAT_TX1_SECTION 0x6800
+#define mmNIC1_MAC_GLOB_STAT_TX2_BASE 0x54EB400ull
+#define NIC1_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800
+#define NIC1_MAC_GLOB_STAT_TX2_SECTION 0x6800
+#define mmNIC1_MAC_GLOB_STAT_TX3_BASE 0x54EB468ull
+#define NIC1_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800
+#define NIC1_MAC_GLOB_STAT_TX3_SECTION 0x3980
+#define mmNIC1_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x54EB800ull
+#define NIC1_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0
+#define NIC1_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000
+#define mmNIC1_MAC_CH0_MAC_PCS_BASE 0x54EC000ull
+#define NIC1_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC1_MAC_CH0_MAC_PCS_SECTION 0x4000
+#define mmNIC1_MAC_CH0_MAC_128_BASE 0x54EC400ull
+#define NIC1_MAC_CH0_MAC_128_MAX_OFFSET 0xA400
+#define NIC1_MAC_CH0_MAC_128_SECTION 0x4000
+#define mmNIC1_MAC_CH0_MAC_AN_BASE 0x54EC800ull
+#define NIC1_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400
+#define NIC1_MAC_CH0_MAC_AN_SECTION 0x8000
+#define mmNIC1_MAC_CH1_MAC_PCS_BASE 0x54ED000ull
+#define NIC1_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC1_MAC_CH1_MAC_PCS_SECTION 0x4000
+#define mmNIC1_MAC_CH1_MAC_128_BASE 0x54ED400ull
+#define NIC1_MAC_CH1_MAC_128_MAX_OFFSET 0xA400
+#define NIC1_MAC_CH1_MAC_128_SECTION 0x4000
+#define mmNIC1_MAC_CH1_MAC_AN_BASE 0x54ED800ull
+#define NIC1_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400
+#define NIC1_MAC_CH1_MAC_AN_SECTION 0x8000
+#define mmNIC1_MAC_CH2_MAC_PCS_BASE 0x54EE000ull
+#define NIC1_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC1_MAC_CH2_MAC_PCS_SECTION 0x4000
+#define mmNIC1_MAC_CH2_MAC_128_BASE 0x54EE400ull
+#define NIC1_MAC_CH2_MAC_128_MAX_OFFSET 0xA400
+#define NIC1_MAC_CH2_MAC_128_SECTION 0x4000
+#define mmNIC1_MAC_CH2_MAC_AN_BASE 0x54EE800ull
+#define NIC1_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400
+#define NIC1_MAC_CH2_MAC_AN_SECTION 0x8000
+#define mmNIC1_MAC_CH3_MAC_PCS_BASE 0x54EF000ull
+#define NIC1_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC1_MAC_CH3_MAC_PCS_SECTION 0x4000
+#define mmNIC1_MAC_CH3_MAC_128_BASE 0x54EF400ull
+#define NIC1_MAC_CH3_MAC_128_MAX_OFFSET 0xA400
+#define NIC1_MAC_CH3_MAC_128_SECTION 0x4000
+#define mmNIC1_MAC_CH3_MAC_AN_BASE 0x54EF800ull
+#define NIC1_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400
+#define NIC1_MAC_CH3_MAC_AN_SECTION 0x10800
+#define mmNIC2_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5500000ull
+#define NIC2_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC2_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5500080ull
+#define NIC2_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC2_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5500100ull
+#define NIC2_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC2_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5500180ull
+#define NIC2_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC2_UMR0_0_SPECIAL_BASE 0x5500E80ull
+#define NIC2_UMR0_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR0_0_SPECIAL_SECTION 0x1800
+#define mmNIC2_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5501000ull
+#define NIC2_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC2_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5501080ull
+#define NIC2_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC2_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5501100ull
+#define NIC2_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC2_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5501180ull
+#define NIC2_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC2_UMR0_1_SPECIAL_BASE 0x5501E80ull
+#define NIC2_UMR0_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR0_1_SPECIAL_SECTION 0x1800
+#define mmNIC2_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5502000ull
+#define NIC2_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC2_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5502080ull
+#define NIC2_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC2_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5502100ull
+#define NIC2_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC2_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5502180ull
+#define NIC2_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC2_UMR0_2_SPECIAL_BASE 0x5502E80ull
+#define NIC2_UMR0_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR0_2_SPECIAL_SECTION 0x1800
+#define mmNIC2_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5503000ull
+#define NIC2_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC2_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5503080ull
+#define NIC2_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC2_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5503100ull
+#define NIC2_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC2_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5503180ull
+#define NIC2_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC2_UMR0_3_SPECIAL_BASE 0x5503E80ull
+#define NIC2_UMR0_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR0_3_SPECIAL_SECTION 0x1800
+#define mmNIC2_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5504000ull
+#define NIC2_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC2_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5504080ull
+#define NIC2_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC2_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5504100ull
+#define NIC2_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC2_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5504180ull
+#define NIC2_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC2_UMR0_4_SPECIAL_BASE 0x5504E80ull
+#define NIC2_UMR0_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR0_4_SPECIAL_SECTION 0x1800
+#define mmNIC2_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5505000ull
+#define NIC2_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC2_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5505080ull
+#define NIC2_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC2_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5505100ull
+#define NIC2_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC2_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5505180ull
+#define NIC2_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC2_UMR0_5_SPECIAL_BASE 0x5505E80ull
+#define NIC2_UMR0_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR0_5_SPECIAL_SECTION 0x1800
+#define mmNIC2_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5506000ull
+#define NIC2_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC2_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5506080ull
+#define NIC2_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC2_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5506100ull
+#define NIC2_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC2_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5506180ull
+#define NIC2_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC2_UMR0_6_SPECIAL_BASE 0x5506E80ull
+#define NIC2_UMR0_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR0_6_SPECIAL_SECTION 0x1800
+#define mmNIC2_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5507000ull
+#define NIC2_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC2_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5507080ull
+#define NIC2_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC2_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5507100ull
+#define NIC2_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC2_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5507180ull
+#define NIC2_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC2_UMR0_7_SPECIAL_BASE 0x5507E80ull
+#define NIC2_UMR0_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR0_7_SPECIAL_SECTION 0x1800
+#define mmNIC2_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5508000ull
+#define NIC2_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC2_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5508080ull
+#define NIC2_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC2_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5508100ull
+#define NIC2_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC2_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5508180ull
+#define NIC2_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC2_UMR0_8_SPECIAL_BASE 0x5508E80ull
+#define NIC2_UMR0_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR0_8_SPECIAL_SECTION 0x1800
+#define mmNIC2_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5509000ull
+#define NIC2_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC2_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5509080ull
+#define NIC2_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC2_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5509100ull
+#define NIC2_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC2_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5509180ull
+#define NIC2_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC2_UMR0_9_SPECIAL_BASE 0x5509E80ull
+#define NIC2_UMR0_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR0_9_SPECIAL_SECTION 0x1800
+#define mmNIC2_UMR0_10_UNSECURE_DOORBELL0_BASE 0x550A000ull
+#define NIC2_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC2_UMR0_10_UNSECURE_DOORBELL1_BASE 0x550A080ull
+#define NIC2_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC2_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x550A100ull
+#define NIC2_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC2_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x550A180ull
+#define NIC2_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC2_UMR0_10_SPECIAL_BASE 0x550AE80ull
+#define NIC2_UMR0_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR0_10_SPECIAL_SECTION 0x1800
+#define mmNIC2_UMR0_11_UNSECURE_DOORBELL0_BASE 0x550B000ull
+#define NIC2_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC2_UMR0_11_UNSECURE_DOORBELL1_BASE 0x550B080ull
+#define NIC2_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC2_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x550B100ull
+#define NIC2_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC2_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x550B180ull
+#define NIC2_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC2_UMR0_11_SPECIAL_BASE 0x550BE80ull
+#define NIC2_UMR0_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR0_11_SPECIAL_SECTION 0x1800
+#define mmNIC2_UMR0_12_UNSECURE_DOORBELL0_BASE 0x550C000ull
+#define NIC2_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC2_UMR0_12_UNSECURE_DOORBELL1_BASE 0x550C080ull
+#define NIC2_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC2_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x550C100ull
+#define NIC2_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC2_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x550C180ull
+#define NIC2_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC2_UMR0_12_SPECIAL_BASE 0x550CE80ull
+#define NIC2_UMR0_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR0_12_SPECIAL_SECTION 0x1800
+#define mmNIC2_UMR0_13_UNSECURE_DOORBELL0_BASE 0x550D000ull
+#define NIC2_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC2_UMR0_13_UNSECURE_DOORBELL1_BASE 0x550D080ull
+#define NIC2_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC2_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x550D100ull
+#define NIC2_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC2_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x550D180ull
+#define NIC2_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC2_UMR0_13_SPECIAL_BASE 0x550DE80ull
+#define NIC2_UMR0_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR0_13_SPECIAL_SECTION 0x1800
+#define mmNIC2_UMR0_14_UNSECURE_DOORBELL0_BASE 0x550E000ull
+#define NIC2_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC2_UMR0_14_UNSECURE_DOORBELL1_BASE 0x550E080ull
+#define NIC2_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC2_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x550E100ull
+#define NIC2_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC2_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x550E180ull
+#define NIC2_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC2_UMR0_14_SPECIAL_BASE 0x550EE80ull
+#define NIC2_UMR0_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR0_14_SPECIAL_SECTION 0x1180
+#define mmNIC2_QM_DCCM0_BASE 0x5510000ull
+#define NIC2_QM_DCCM0_MAX_OFFSET 0x4000
+#define NIC2_QM_DCCM0_SECTION 0x8000
+#define mmNIC2_QM_ARC_AUX0_BASE 0x5518000ull
+#define NIC2_QM_ARC_AUX0_MAX_OFFSET 0x1000
+#define NIC2_QM_ARC_AUX0_SECTION 0xE800
+#define mmNIC2_QM_ARC_AUX0_SPECIAL_BASE 0x5518E80ull
+#define NIC2_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_QM_ARC_AUX0_SPECIAL_SECTION 0x1180
+#define mmNIC2_QM0_BASE 0x551A000ull
+#define NIC2_QM0_MAX_OFFSET 0x1000
+#define NIC2_QM0_SECTION 0x9000
+#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x551A900ull
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x551A908ull
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x551A910ull
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x551A918ull
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x551A920ull
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x551A928ull
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x551A930ull
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x551A938ull
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x551A940ull
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x551A948ull
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x551A950ull
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x551A958ull
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x551A960ull
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x551A968ull
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x551A970ull
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x551A978ull
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC2_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmNIC2_QM0_AXUSER_SECURED_BASE 0x551AB00ull
+#define NIC2_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC2_QM0_AXUSER_SECURED_SECTION 0x8000
+#define mmNIC2_QM0_AXUSER_NONSECURED_BASE 0x551AB80ull
+#define NIC2_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC2_QM0_AXUSER_NONSECURED_SECTION 0x8000
+#define mmNIC2_QM0_DBG_HBW_BASE 0x551AC00ull
+#define NIC2_QM0_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC2_QM0_DBG_HBW_SECTION 0x8000
+#define mmNIC2_QM0_DBG_LBW_BASE 0x551AC80ull
+#define NIC2_QM0_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC2_QM0_DBG_LBW_SECTION 0x1000
+#define mmNIC2_QM0_CGM_BASE 0x551AD80ull
+#define NIC2_QM0_CGM_MAX_OFFSET 0xC000
+#define NIC2_QM0_CGM_SECTION 0x1000
+#define mmNIC2_QM0_SPECIAL_BASE 0x551AE80ull
+#define NIC2_QM0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_QM0_SPECIAL_SECTION 0x4180
+#define mmNIC2_QPC0_BASE 0x551F000ull
+#define NIC2_QPC0_MAX_OFFSET 0x1000
+#define NIC2_QPC0_SECTION 0x7200
+#define mmNIC2_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x551F720ull
+#define NIC2_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x551F728ull
+#define NIC2_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x551F730ull
+#define NIC2_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x551F738ull
+#define NIC2_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x551F740ull
+#define NIC2_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x551F748ull
+#define NIC2_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x551F750ull
+#define NIC2_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x551F758ull
+#define NIC2_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x551F760ull
+#define NIC2_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x551F768ull
+#define NIC2_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x551F770ull
+#define NIC2_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x551F778ull
+#define NIC2_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x551F780ull
+#define NIC2_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x551F788ull
+#define NIC2_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x551F790ull
+#define NIC2_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x551F798ull
+#define NIC2_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x551F7A0ull
+#define NIC2_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x551F7A8ull
+#define NIC2_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x551F7B0ull
+#define NIC2_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x551F7B8ull
+#define NIC2_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x551F7C0ull
+#define NIC2_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x551F7C8ull
+#define NIC2_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x551F7D0ull
+#define NIC2_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x551F7D8ull
+#define NIC2_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x551F7E0ull
+#define NIC2_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x551F7E8ull
+#define NIC2_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x551F7F0ull
+#define NIC2_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x551F7F8ull
+#define NIC2_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x551F800ull
+#define NIC2_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x551F808ull
+#define NIC2_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x551F810ull
+#define NIC2_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x551F818ull
+#define NIC2_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define mmNIC2_QPC0_AXUSER_CONG_QUE_BASE 0x551FB80ull
+#define NIC2_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC2_QPC0_AXUSER_CONG_QUE_SECTION 0x6000
+#define mmNIC2_QPC0_AXUSER_RXWQE_BASE 0x551FBE0ull
+#define NIC2_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC2_QPC0_AXUSER_RXWQE_SECTION 0x6000
+#define mmNIC2_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x551FC40ull
+#define NIC2_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC2_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define mmNIC2_QPC0_AXUSER_DB_FIFO_BASE 0x551FCA0ull
+#define NIC2_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC2_QPC0_AXUSER_DB_FIFO_SECTION 0x6000
+#define mmNIC2_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x551FD00ull
+#define NIC2_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC2_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define mmNIC2_QPC0_AXUSER_ERR_FIFO_BASE 0x551FD60ull
+#define NIC2_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC2_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000
+#define mmNIC2_QPC0_AXUSER_QPC_RESP_BASE 0x551FDC0ull
+#define NIC2_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC2_QPC0_AXUSER_QPC_RESP_SECTION 0x6000
+#define mmNIC2_QPC0_AXUSER_QPC_REQ_BASE 0x551FE20ull
+#define NIC2_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC2_QPC0_AXUSER_QPC_REQ_SECTION 0x6000
+#define mmNIC2_QPC0_SPECIAL_BASE 0x551FE80ull
+#define NIC2_QPC0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_QPC0_SPECIAL_SECTION 0x1800
+#define mmNIC2_UMR1_0_UNSECURE_DOORBELL0_BASE 0x5520000ull
+#define NIC2_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC2_UMR1_0_UNSECURE_DOORBELL1_BASE 0x5520080ull
+#define NIC2_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC2_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x5520100ull
+#define NIC2_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC2_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x5520180ull
+#define NIC2_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC2_UMR1_0_SPECIAL_BASE 0x5520E80ull
+#define NIC2_UMR1_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR1_0_SPECIAL_SECTION 0x1800
+#define mmNIC2_UMR1_1_UNSECURE_DOORBELL0_BASE 0x5521000ull
+#define NIC2_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC2_UMR1_1_UNSECURE_DOORBELL1_BASE 0x5521080ull
+#define NIC2_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC2_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x5521100ull
+#define NIC2_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC2_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x5521180ull
+#define NIC2_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC2_UMR1_1_SPECIAL_BASE 0x5521E80ull
+#define NIC2_UMR1_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR1_1_SPECIAL_SECTION 0x1800
+#define mmNIC2_UMR1_2_UNSECURE_DOORBELL0_BASE 0x5522000ull
+#define NIC2_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC2_UMR1_2_UNSECURE_DOORBELL1_BASE 0x5522080ull
+#define NIC2_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC2_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x5522100ull
+#define NIC2_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC2_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x5522180ull
+#define NIC2_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC2_UMR1_2_SPECIAL_BASE 0x5522E80ull
+#define NIC2_UMR1_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR1_2_SPECIAL_SECTION 0x1800
+#define mmNIC2_UMR1_3_UNSECURE_DOORBELL0_BASE 0x5523000ull
+#define NIC2_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC2_UMR1_3_UNSECURE_DOORBELL1_BASE 0x5523080ull
+#define NIC2_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC2_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x5523100ull
+#define NIC2_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC2_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x5523180ull
+#define NIC2_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC2_UMR1_3_SPECIAL_BASE 0x5523E80ull
+#define NIC2_UMR1_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR1_3_SPECIAL_SECTION 0x1800
+#define mmNIC2_UMR1_4_UNSECURE_DOORBELL0_BASE 0x5524000ull
+#define NIC2_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC2_UMR1_4_UNSECURE_DOORBELL1_BASE 0x5524080ull
+#define NIC2_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC2_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x5524100ull
+#define NIC2_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC2_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x5524180ull
+#define NIC2_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC2_UMR1_4_SPECIAL_BASE 0x5524E80ull
+#define NIC2_UMR1_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR1_4_SPECIAL_SECTION 0x1800
+#define mmNIC2_UMR1_5_UNSECURE_DOORBELL0_BASE 0x5525000ull
+#define NIC2_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC2_UMR1_5_UNSECURE_DOORBELL1_BASE 0x5525080ull
+#define NIC2_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC2_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x5525100ull
+#define NIC2_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC2_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x5525180ull
+#define NIC2_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC2_UMR1_5_SPECIAL_BASE 0x5525E80ull
+#define NIC2_UMR1_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR1_5_SPECIAL_SECTION 0x1800
+#define mmNIC2_UMR1_6_UNSECURE_DOORBELL0_BASE 0x5526000ull
+#define NIC2_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC2_UMR1_6_UNSECURE_DOORBELL1_BASE 0x5526080ull
+#define NIC2_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC2_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x5526100ull
+#define NIC2_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC2_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x5526180ull
+#define NIC2_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC2_UMR1_6_SPECIAL_BASE 0x5526E80ull
+#define NIC2_UMR1_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR1_6_SPECIAL_SECTION 0x1800
+#define mmNIC2_UMR1_7_UNSECURE_DOORBELL0_BASE 0x5527000ull
+#define NIC2_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC2_UMR1_7_UNSECURE_DOORBELL1_BASE 0x5527080ull
+#define NIC2_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC2_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x5527100ull
+#define NIC2_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC2_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x5527180ull
+#define NIC2_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC2_UMR1_7_SPECIAL_BASE 0x5527E80ull
+#define NIC2_UMR1_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR1_7_SPECIAL_SECTION 0x1800
+#define mmNIC2_UMR1_8_UNSECURE_DOORBELL0_BASE 0x5528000ull
+#define NIC2_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC2_UMR1_8_UNSECURE_DOORBELL1_BASE 0x5528080ull
+#define NIC2_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC2_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x5528100ull
+#define NIC2_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC2_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x5528180ull
+#define NIC2_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC2_UMR1_8_SPECIAL_BASE 0x5528E80ull
+#define NIC2_UMR1_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR1_8_SPECIAL_SECTION 0x1800
+#define mmNIC2_UMR1_9_UNSECURE_DOORBELL0_BASE 0x5529000ull
+#define NIC2_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC2_UMR1_9_UNSECURE_DOORBELL1_BASE 0x5529080ull
+#define NIC2_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC2_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x5529100ull
+#define NIC2_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC2_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x5529180ull
+#define NIC2_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC2_UMR1_9_SPECIAL_BASE 0x5529E80ull
+#define NIC2_UMR1_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR1_9_SPECIAL_SECTION 0x1800
+#define mmNIC2_UMR1_10_UNSECURE_DOORBELL0_BASE 0x552A000ull
+#define NIC2_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC2_UMR1_10_UNSECURE_DOORBELL1_BASE 0x552A080ull
+#define NIC2_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC2_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x552A100ull
+#define NIC2_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC2_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x552A180ull
+#define NIC2_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC2_UMR1_10_SPECIAL_BASE 0x552AE80ull
+#define NIC2_UMR1_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR1_10_SPECIAL_SECTION 0x1800
+#define mmNIC2_UMR1_11_UNSECURE_DOORBELL0_BASE 0x552B000ull
+#define NIC2_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC2_UMR1_11_UNSECURE_DOORBELL1_BASE 0x552B080ull
+#define NIC2_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC2_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x552B100ull
+#define NIC2_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC2_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x552B180ull
+#define NIC2_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC2_UMR1_11_SPECIAL_BASE 0x552BE80ull
+#define NIC2_UMR1_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR1_11_SPECIAL_SECTION 0x1800
+#define mmNIC2_UMR1_12_UNSECURE_DOORBELL0_BASE 0x552C000ull
+#define NIC2_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC2_UMR1_12_UNSECURE_DOORBELL1_BASE 0x552C080ull
+#define NIC2_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC2_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x552C100ull
+#define NIC2_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC2_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x552C180ull
+#define NIC2_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC2_UMR1_12_SPECIAL_BASE 0x552CE80ull
+#define NIC2_UMR1_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR1_12_SPECIAL_SECTION 0x1800
+#define mmNIC2_UMR1_13_UNSECURE_DOORBELL0_BASE 0x552D000ull
+#define NIC2_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC2_UMR1_13_UNSECURE_DOORBELL1_BASE 0x552D080ull
+#define NIC2_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC2_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x552D100ull
+#define NIC2_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC2_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x552D180ull
+#define NIC2_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC2_UMR1_13_SPECIAL_BASE 0x552DE80ull
+#define NIC2_UMR1_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR1_13_SPECIAL_SECTION 0x1800
+#define mmNIC2_UMR1_14_UNSECURE_DOORBELL0_BASE 0x552E000ull
+#define NIC2_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC2_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC2_UMR1_14_UNSECURE_DOORBELL1_BASE 0x552E080ull
+#define NIC2_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC2_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC2_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x552E100ull
+#define NIC2_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC2_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC2_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x552E180ull
+#define NIC2_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC2_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC2_UMR1_14_SPECIAL_BASE 0x552EE80ull
+#define NIC2_UMR1_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_UMR1_14_SPECIAL_SECTION 0x1180
+#define mmNIC2_QM_DCCM1_BASE 0x5530000ull
+#define NIC2_QM_DCCM1_MAX_OFFSET 0x4000
+#define NIC2_QM_DCCM1_SECTION 0x8000
+#define mmNIC2_QM_ARC_AUX1_BASE 0x5538000ull
+#define NIC2_QM_ARC_AUX1_MAX_OFFSET 0x1000
+#define NIC2_QM_ARC_AUX1_SECTION 0xE800
+#define mmNIC2_QM_ARC_AUX1_SPECIAL_BASE 0x5538E80ull
+#define NIC2_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_QM_ARC_AUX1_SPECIAL_SECTION 0x1180
+#define mmNIC2_QM1_BASE 0x553A000ull
+#define NIC2_QM1_MAX_OFFSET 0x1000
+#define NIC2_QM1_SECTION 0x9000
+#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x553A900ull
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x553A908ull
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x553A910ull
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x553A918ull
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x553A920ull
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x553A928ull
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x553A930ull
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x553A938ull
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x553A940ull
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x553A948ull
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x553A950ull
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x553A958ull
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x553A960ull
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x553A968ull
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x553A970ull
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x553A978ull
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC2_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmNIC2_QM1_AXUSER_SECURED_BASE 0x553AB00ull
+#define NIC2_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC2_QM1_AXUSER_SECURED_SECTION 0x8000
+#define mmNIC2_QM1_AXUSER_NONSECURED_BASE 0x553AB80ull
+#define NIC2_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC2_QM1_AXUSER_NONSECURED_SECTION 0x8000
+#define mmNIC2_QM1_DBG_HBW_BASE 0x553AC00ull
+#define NIC2_QM1_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC2_QM1_DBG_HBW_SECTION 0x8000
+#define mmNIC2_QM1_DBG_LBW_BASE 0x553AC80ull
+#define NIC2_QM1_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC2_QM1_DBG_LBW_SECTION 0x1000
+#define mmNIC2_QM1_CGM_BASE 0x553AD80ull
+#define NIC2_QM1_CGM_MAX_OFFSET 0xC000
+#define NIC2_QM1_CGM_SECTION 0x1000
+#define mmNIC2_QM1_SPECIAL_BASE 0x553AE80ull
+#define NIC2_QM1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_QM1_SPECIAL_SECTION 0x4180
+#define mmNIC2_QPC1_BASE 0x553F000ull
+#define NIC2_QPC1_MAX_OFFSET 0x1000
+#define NIC2_QPC1_SECTION 0x7200
+#define mmNIC2_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x553F720ull
+#define NIC2_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x553F728ull
+#define NIC2_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x553F730ull
+#define NIC2_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x553F738ull
+#define NIC2_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x553F740ull
+#define NIC2_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x553F748ull
+#define NIC2_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x553F750ull
+#define NIC2_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x553F758ull
+#define NIC2_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x553F760ull
+#define NIC2_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x553F768ull
+#define NIC2_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x553F770ull
+#define NIC2_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x553F778ull
+#define NIC2_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x553F780ull
+#define NIC2_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x553F788ull
+#define NIC2_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x553F790ull
+#define NIC2_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x553F798ull
+#define NIC2_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x553F7A0ull
+#define NIC2_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x553F7A8ull
+#define NIC2_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x553F7B0ull
+#define NIC2_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x553F7B8ull
+#define NIC2_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x553F7C0ull
+#define NIC2_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x553F7C8ull
+#define NIC2_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x553F7D0ull
+#define NIC2_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x553F7D8ull
+#define NIC2_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x553F7E0ull
+#define NIC2_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x553F7E8ull
+#define NIC2_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x553F7F0ull
+#define NIC2_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x553F7F8ull
+#define NIC2_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x553F800ull
+#define NIC2_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x553F808ull
+#define NIC2_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x553F810ull
+#define NIC2_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC2_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x553F818ull
+#define NIC2_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC2_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define mmNIC2_QPC1_AXUSER_CONG_QUE_BASE 0x553FB80ull
+#define NIC2_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC2_QPC1_AXUSER_CONG_QUE_SECTION 0x6000
+#define mmNIC2_QPC1_AXUSER_RXWQE_BASE 0x553FBE0ull
+#define NIC2_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC2_QPC1_AXUSER_RXWQE_SECTION 0x6000
+#define mmNIC2_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x553FC40ull
+#define NIC2_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC2_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define mmNIC2_QPC1_AXUSER_DB_FIFO_BASE 0x553FCA0ull
+#define NIC2_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC2_QPC1_AXUSER_DB_FIFO_SECTION 0x6000
+#define mmNIC2_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x553FD00ull
+#define NIC2_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC2_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define mmNIC2_QPC1_AXUSER_ERR_FIFO_BASE 0x553FD60ull
+#define NIC2_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC2_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000
+#define mmNIC2_QPC1_AXUSER_QPC_RESP_BASE 0x553FDC0ull
+#define NIC2_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC2_QPC1_AXUSER_QPC_RESP_SECTION 0x6000
+#define mmNIC2_QPC1_AXUSER_QPC_REQ_BASE 0x553FE20ull
+#define NIC2_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC2_QPC1_AXUSER_QPC_REQ_SECTION 0x6000
+#define mmNIC2_QPC1_SPECIAL_BASE 0x553FE80ull
+#define NIC2_QPC1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_QPC1_SPECIAL_SECTION 0x8180
+#define mmNIC2_TMR_BASE 0x5548000ull
+#define NIC2_TMR_MAX_OFFSET 0x1000
+#define NIC2_TMR_SECTION 0xD600
+#define mmNIC2_TMR_AXUSER_TMR_FREE_LIST_BASE 0x5548D60ull
+#define NIC2_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000
+#define NIC2_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000
+#define mmNIC2_TMR_AXUSER_TMR_FIFO_BASE 0x5548DC0ull
+#define NIC2_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000
+#define NIC2_TMR_AXUSER_TMR_FIFO_SECTION 0x6000
+#define mmNIC2_TMR_AXUSER_TMR_FSM_BASE 0x5548E20ull
+#define NIC2_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000
+#define NIC2_TMR_AXUSER_TMR_FSM_SECTION 0x6000
+#define mmNIC2_TMR_SPECIAL_BASE 0x5548E80ull
+#define NIC2_TMR_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_TMR_SPECIAL_SECTION 0x1800
+#define mmNIC2_RXB_CORE_BASE 0x5549000ull
+#define NIC2_RXB_CORE_MAX_OFFSET 0x1000
+#define NIC2_RXB_CORE_SECTION 0x6100
+#define mmNIC2_RXB_CORE_SCT_AWUSER_BASE 0x5549610ull
+#define NIC2_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000
+#define NIC2_RXB_CORE_SCT_AWUSER_SECTION 0x8700
+#define mmNIC2_RXB_CORE_SPECIAL_BASE 0x5549E80ull
+#define NIC2_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_RXB_CORE_SPECIAL_SECTION 0x1800
+#define mmNIC2_RXE0_BASE 0x554A000ull
+#define NIC2_RXE0_MAX_OFFSET 0x1000
+#define NIC2_RXE0_SECTION 0x9000
+#define mmNIC2_RXE0_WQE_ARUSER_BASE 0x554A900ull
+#define NIC2_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC2_RXE0_WQE_ARUSER_SECTION 0x5800
+#define mmNIC2_RXE0_SPECIAL_BASE 0x554AE80ull
+#define NIC2_RXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_RXE0_SPECIAL_SECTION 0x1800
+#define mmNIC2_RXE1_BASE 0x554B000ull
+#define NIC2_RXE1_MAX_OFFSET 0x1000
+#define NIC2_RXE1_SECTION 0x9000
+#define mmNIC2_RXE1_WQE_ARUSER_BASE 0x554B900ull
+#define NIC2_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC2_RXE1_WQE_ARUSER_SECTION 0x5800
+#define mmNIC2_RXE1_SPECIAL_BASE 0x554BE80ull
+#define NIC2_RXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_RXE1_SPECIAL_SECTION 0x1800
+#define mmNIC2_RXE0_AXUSER_AXUSER_CQ0_BASE 0x554C000ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define mmNIC2_RXE0_AXUSER_AXUSER_CQ1_BASE 0x554C050ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define mmNIC2_RXE0_AXUSER_AXUSER_CQ2_BASE 0x554C0A0ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define mmNIC2_RXE0_AXUSER_AXUSER_CQ3_BASE 0x554C0F0ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define mmNIC2_RXE0_AXUSER_AXUSER_CQ4_BASE 0x554C140ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define mmNIC2_RXE0_AXUSER_AXUSER_CQ5_BASE 0x554C190ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define mmNIC2_RXE0_AXUSER_AXUSER_CQ6_BASE 0x554C1E0ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define mmNIC2_RXE0_AXUSER_AXUSER_CQ7_BASE 0x554C230ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define mmNIC2_RXE0_AXUSER_AXUSER_CQ8_BASE 0x554C280ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define mmNIC2_RXE0_AXUSER_AXUSER_CQ9_BASE 0x554C2D0ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define mmNIC2_RXE0_AXUSER_AXUSER_CQ10_BASE 0x554C320ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define mmNIC2_RXE0_AXUSER_AXUSER_CQ11_BASE 0x554C370ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define mmNIC2_RXE0_AXUSER_AXUSER_CQ12_BASE 0x554C3C0ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define mmNIC2_RXE0_AXUSER_AXUSER_CQ13_BASE 0x554C410ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define mmNIC2_RXE0_AXUSER_AXUSER_CQ14_BASE 0x554C460ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define mmNIC2_RXE0_AXUSER_AXUSER_CQ15_BASE 0x554C4B0ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define mmNIC2_RXE0_AXUSER_AXUSER_CQ16_BASE 0x554C500ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define mmNIC2_RXE0_AXUSER_AXUSER_CQ17_BASE 0x554C550ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define mmNIC2_RXE0_AXUSER_AXUSER_CQ18_BASE 0x554C5A0ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define mmNIC2_RXE0_AXUSER_AXUSER_CQ19_BASE 0x554C5F0ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define mmNIC2_RXE0_AXUSER_AXUSER_CQ20_BASE 0x554C640ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define mmNIC2_RXE0_AXUSER_AXUSER_CQ21_BASE 0x554C690ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define mmNIC2_RXE0_AXUSER_AXUSER_CQ22_BASE 0x554C6E0ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define mmNIC2_RXE0_AXUSER_AXUSER_CQ23_BASE 0x554C730ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define mmNIC2_RXE0_AXUSER_AXUSER_CQ24_BASE 0x554C780ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define mmNIC2_RXE0_AXUSER_AXUSER_CQ25_BASE 0x554C7D0ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define mmNIC2_RXE0_AXUSER_AXUSER_CQ26_BASE 0x554C820ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define mmNIC2_RXE0_AXUSER_AXUSER_CQ27_BASE 0x554C870ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define mmNIC2_RXE0_AXUSER_AXUSER_CQ28_BASE 0x554C8C0ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define mmNIC2_RXE0_AXUSER_AXUSER_CQ29_BASE 0x554C910ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define mmNIC2_RXE0_AXUSER_AXUSER_CQ30_BASE 0x554C960ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define mmNIC2_RXE0_AXUSER_AXUSER_CQ31_BASE 0x554C9B0ull
+#define NIC2_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC2_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define mmNIC2_RXE0_AXUSER_SPECIAL_BASE 0x554CE80ull
+#define NIC2_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_RXE0_AXUSER_SPECIAL_SECTION 0x1800
+#define mmNIC2_RXE1_AXUSER_AXUSER_CQ0_BASE 0x554D000ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define mmNIC2_RXE1_AXUSER_AXUSER_CQ1_BASE 0x554D050ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define mmNIC2_RXE1_AXUSER_AXUSER_CQ2_BASE 0x554D0A0ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define mmNIC2_RXE1_AXUSER_AXUSER_CQ3_BASE 0x554D0F0ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define mmNIC2_RXE1_AXUSER_AXUSER_CQ4_BASE 0x554D140ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define mmNIC2_RXE1_AXUSER_AXUSER_CQ5_BASE 0x554D190ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define mmNIC2_RXE1_AXUSER_AXUSER_CQ6_BASE 0x554D1E0ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define mmNIC2_RXE1_AXUSER_AXUSER_CQ7_BASE 0x554D230ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define mmNIC2_RXE1_AXUSER_AXUSER_CQ8_BASE 0x554D280ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define mmNIC2_RXE1_AXUSER_AXUSER_CQ9_BASE 0x554D2D0ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define mmNIC2_RXE1_AXUSER_AXUSER_CQ10_BASE 0x554D320ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define mmNIC2_RXE1_AXUSER_AXUSER_CQ11_BASE 0x554D370ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define mmNIC2_RXE1_AXUSER_AXUSER_CQ12_BASE 0x554D3C0ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define mmNIC2_RXE1_AXUSER_AXUSER_CQ13_BASE 0x554D410ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define mmNIC2_RXE1_AXUSER_AXUSER_CQ14_BASE 0x554D460ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define mmNIC2_RXE1_AXUSER_AXUSER_CQ15_BASE 0x554D4B0ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define mmNIC2_RXE1_AXUSER_AXUSER_CQ16_BASE 0x554D500ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define mmNIC2_RXE1_AXUSER_AXUSER_CQ17_BASE 0x554D550ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define mmNIC2_RXE1_AXUSER_AXUSER_CQ18_BASE 0x554D5A0ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define mmNIC2_RXE1_AXUSER_AXUSER_CQ19_BASE 0x554D5F0ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define mmNIC2_RXE1_AXUSER_AXUSER_CQ20_BASE 0x554D640ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define mmNIC2_RXE1_AXUSER_AXUSER_CQ21_BASE 0x554D690ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define mmNIC2_RXE1_AXUSER_AXUSER_CQ22_BASE 0x554D6E0ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define mmNIC2_RXE1_AXUSER_AXUSER_CQ23_BASE 0x554D730ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define mmNIC2_RXE1_AXUSER_AXUSER_CQ24_BASE 0x554D780ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define mmNIC2_RXE1_AXUSER_AXUSER_CQ25_BASE 0x554D7D0ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define mmNIC2_RXE1_AXUSER_AXUSER_CQ26_BASE 0x554D820ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define mmNIC2_RXE1_AXUSER_AXUSER_CQ27_BASE 0x554D870ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define mmNIC2_RXE1_AXUSER_AXUSER_CQ28_BASE 0x554D8C0ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define mmNIC2_RXE1_AXUSER_AXUSER_CQ29_BASE 0x554D910ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define mmNIC2_RXE1_AXUSER_AXUSER_CQ30_BASE 0x554D960ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define mmNIC2_RXE1_AXUSER_AXUSER_CQ31_BASE 0x554D9B0ull
+#define NIC2_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC2_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define mmNIC2_RXE1_AXUSER_SPECIAL_BASE 0x554DE80ull
+#define NIC2_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_RXE1_AXUSER_SPECIAL_SECTION 0x2180
+#define mmNIC2_TXS0_BASE 0x5550000ull
+#define NIC2_TXS0_MAX_OFFSET 0x1000
+#define NIC2_TXS0_SECTION 0xE800
+#define mmNIC2_TXS0_SPECIAL_BASE 0x5550E80ull
+#define NIC2_TXS0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_TXS0_SPECIAL_SECTION 0x1800
+#define mmNIC2_TXS1_BASE 0x5551000ull
+#define NIC2_TXS1_MAX_OFFSET 0x1000
+#define NIC2_TXS1_SECTION 0xE800
+#define mmNIC2_TXS1_SPECIAL_BASE 0x5551E80ull
+#define NIC2_TXS1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_TXS1_SPECIAL_SECTION 0x1800
+#define mmNIC2_TXE0_BASE 0x5552000ull
+#define NIC2_TXE0_MAX_OFFSET 0x1000
+#define NIC2_TXE0_SECTION 0xE800
+#define mmNIC2_TXE0_SPECIAL_BASE 0x5552E80ull
+#define NIC2_TXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_TXE0_SPECIAL_SECTION 0x1800
+#define mmNIC2_TXE1_BASE 0x5553000ull
+#define NIC2_TXE1_MAX_OFFSET 0x1000
+#define NIC2_TXE1_SECTION 0xE800
+#define mmNIC2_TXE1_SPECIAL_BASE 0x5553E80ull
+#define NIC2_TXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_TXE1_SPECIAL_SECTION 0x1800
+#define mmNIC2_TXB_BASE 0x5554000ull
+#define NIC2_TXB_MAX_OFFSET 0x1000
+#define NIC2_TXB_SECTION 0xE800
+#define mmNIC2_TXB_SPECIAL_BASE 0x5554E80ull
+#define NIC2_TXB_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_TXB_SPECIAL_SECTION 0x1800
+#define mmNIC2_MSTR_IF_RR_SHRD_HBW_BASE 0x5555000ull
+#define NIC2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define NIC2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmNIC2_MSTR_IF_RR_PRVT_HBW_BASE 0x5555200ull
+#define NIC2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define NIC2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmNIC2_MSTR_IF_RR_SHRD_LBW_BASE 0x5555400ull
+#define NIC2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define NIC2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmNIC2_MSTR_IF_RR_PRVT_LBW_BASE 0x5555600ull
+#define NIC2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define NIC2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmNIC2_MSTR_IF_E2E_CRDT_BASE 0x5555800ull
+#define NIC2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define NIC2_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmNIC2_MSTR_IF_AXUSER_BASE 0x5555A80ull
+#define NIC2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define NIC2_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmNIC2_MSTR_IF_DBG_HBW_BASE 0x5555B00ull
+#define NIC2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC2_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmNIC2_MSTR_IF_DBG_LBW_BASE 0x5555B80ull
+#define NIC2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC2_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmNIC2_MSTR_IF_CORE_HBW_BASE 0x5555C00ull
+#define NIC2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define NIC2_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmNIC2_MSTR_IF_CORE_LBW_BASE 0x5555D80ull
+#define NIC2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define NIC2_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmNIC2_MSTR_IF_SPECIAL_BASE 0x5555E80ull
+#define NIC2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmNIC2_TX_AXUSER_BASE 0x5556000ull
+#define NIC2_TX_AXUSER_MAX_OFFSET 0x5000
+#define NIC2_TX_AXUSER_SECTION 0x2000
+#define mmNIC2_SERDES0_BASE 0x5558000ull
+#define NIC2_SERDES0_MAX_OFFSET 0x3E40
+#define NIC2_SERDES0_SECTION 0x4000
+#define mmNIC2_SERDES1_BASE 0x555C000ull
+#define NIC2_SERDES1_MAX_OFFSET 0x3E40
+#define NIC2_SERDES1_SECTION 0x4000
+#define mmNIC2_PHY_BASE 0x5560000ull
+#define NIC2_PHY_MAX_OFFSET 0x1000
+#define NIC2_PHY_SECTION 0xE800
+#define mmNIC2_PHY_SPECIAL_BASE 0x5560E80ull
+#define NIC2_PHY_SPECIAL_MAX_OFFSET 0x1800
+#define NIC2_PHY_SPECIAL_SECTION 0x7180
+#define mmPRT2_MAC_AUX_BASE 0x5568000ull
+#define PRT2_MAC_AUX_MAX_OFFSET 0x1000
+#define PRT2_MAC_AUX_SECTION 0xE800
+#define mmPRT2_MAC_AUX_SPECIAL_BASE 0x5568E80ull
+#define PRT2_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define PRT2_MAC_AUX_SPECIAL_SECTION 0x1800
+#define mmPRT2_MAC_CORE_BASE 0x5569000ull
+#define PRT2_MAC_CORE_MAX_OFFSET 0x1000
+#define PRT2_MAC_CORE_SECTION 0xE800
+#define mmPRT2_MAC_CORE_SPECIAL_BASE 0x5569E80ull
+#define PRT2_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define PRT2_MAC_CORE_SPECIAL_SECTION 0x1800
+#define mmNIC2_MAC_RS_FEC_BASE 0x556A000ull
+#define NIC2_MAC_RS_FEC_MAX_OFFSET 0x2DC0
+#define NIC2_MAC_RS_FEC_SECTION 0x1000
+#define mmNIC2_MAC_GLOB_STAT_CONTROL_REG_BASE 0x556B000ull
+#define NIC2_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000
+#define NIC2_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000
+#define mmNIC2_MAC_GLOB_STAT_RX0_BASE 0x556B100ull
+#define NIC2_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00
+#define NIC2_MAC_GLOB_STAT_RX0_SECTION 0x8C00
+#define mmNIC2_MAC_GLOB_STAT_RX1_BASE 0x556B18Cull
+#define NIC2_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00
+#define NIC2_MAC_GLOB_STAT_RX1_SECTION 0x8C00
+#define mmNIC2_MAC_GLOB_STAT_RX2_BASE 0x556B218ull
+#define NIC2_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00
+#define NIC2_MAC_GLOB_STAT_RX2_SECTION 0x8C00
+#define mmNIC2_MAC_GLOB_STAT_RX3_BASE 0x556B2A4ull
+#define NIC2_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00
+#define NIC2_MAC_GLOB_STAT_RX3_SECTION 0x8C00
+#define mmNIC2_MAC_GLOB_STAT_TX0_BASE 0x556B330ull
+#define NIC2_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800
+#define NIC2_MAC_GLOB_STAT_TX0_SECTION 0x6800
+#define mmNIC2_MAC_GLOB_STAT_TX1_BASE 0x556B398ull
+#define NIC2_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800
+#define NIC2_MAC_GLOB_STAT_TX1_SECTION 0x6800
+#define mmNIC2_MAC_GLOB_STAT_TX2_BASE 0x556B400ull
+#define NIC2_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800
+#define NIC2_MAC_GLOB_STAT_TX2_SECTION 0x6800
+#define mmNIC2_MAC_GLOB_STAT_TX3_BASE 0x556B468ull
+#define NIC2_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800
+#define NIC2_MAC_GLOB_STAT_TX3_SECTION 0x3980
+#define mmNIC2_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x556B800ull
+#define NIC2_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0
+#define NIC2_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000
+#define mmNIC2_MAC_CH0_MAC_PCS_BASE 0x556C000ull
+#define NIC2_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC2_MAC_CH0_MAC_PCS_SECTION 0x4000
+#define mmNIC2_MAC_CH0_MAC_128_BASE 0x556C400ull
+#define NIC2_MAC_CH0_MAC_128_MAX_OFFSET 0xA400
+#define NIC2_MAC_CH0_MAC_128_SECTION 0x4000
+#define mmNIC2_MAC_CH0_MAC_AN_BASE 0x556C800ull
+#define NIC2_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400
+#define NIC2_MAC_CH0_MAC_AN_SECTION 0x8000
+#define mmNIC2_MAC_CH1_MAC_PCS_BASE 0x556D000ull
+#define NIC2_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC2_MAC_CH1_MAC_PCS_SECTION 0x4000
+#define mmNIC2_MAC_CH1_MAC_128_BASE 0x556D400ull
+#define NIC2_MAC_CH1_MAC_128_MAX_OFFSET 0xA400
+#define NIC2_MAC_CH1_MAC_128_SECTION 0x4000
+#define mmNIC2_MAC_CH1_MAC_AN_BASE 0x556D800ull
+#define NIC2_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400
+#define NIC2_MAC_CH1_MAC_AN_SECTION 0x8000
+#define mmNIC2_MAC_CH2_MAC_PCS_BASE 0x556E000ull
+#define NIC2_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC2_MAC_CH2_MAC_PCS_SECTION 0x4000
+#define mmNIC2_MAC_CH2_MAC_128_BASE 0x556E400ull
+#define NIC2_MAC_CH2_MAC_128_MAX_OFFSET 0xA400
+#define NIC2_MAC_CH2_MAC_128_SECTION 0x4000
+#define mmNIC2_MAC_CH2_MAC_AN_BASE 0x556E800ull
+#define NIC2_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400
+#define NIC2_MAC_CH2_MAC_AN_SECTION 0x8000
+#define mmNIC2_MAC_CH3_MAC_PCS_BASE 0x556F000ull
+#define NIC2_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC2_MAC_CH3_MAC_PCS_SECTION 0x4000
+#define mmNIC2_MAC_CH3_MAC_128_BASE 0x556F400ull
+#define NIC2_MAC_CH3_MAC_128_MAX_OFFSET 0xA400
+#define NIC2_MAC_CH3_MAC_128_SECTION 0x4000
+#define mmNIC2_MAC_CH3_MAC_AN_BASE 0x556F800ull
+#define NIC2_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400
+#define NIC2_MAC_CH3_MAC_AN_SECTION 0x10800
+#define mmNIC3_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5580000ull
+#define NIC3_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC3_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5580080ull
+#define NIC3_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC3_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5580100ull
+#define NIC3_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC3_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5580180ull
+#define NIC3_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC3_UMR0_0_SPECIAL_BASE 0x5580E80ull
+#define NIC3_UMR0_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR0_0_SPECIAL_SECTION 0x1800
+#define mmNIC3_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5581000ull
+#define NIC3_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC3_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5581080ull
+#define NIC3_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC3_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5581100ull
+#define NIC3_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC3_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5581180ull
+#define NIC3_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC3_UMR0_1_SPECIAL_BASE 0x5581E80ull
+#define NIC3_UMR0_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR0_1_SPECIAL_SECTION 0x1800
+#define mmNIC3_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5582000ull
+#define NIC3_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC3_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5582080ull
+#define NIC3_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC3_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5582100ull
+#define NIC3_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC3_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5582180ull
+#define NIC3_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC3_UMR0_2_SPECIAL_BASE 0x5582E80ull
+#define NIC3_UMR0_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR0_2_SPECIAL_SECTION 0x1800
+#define mmNIC3_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5583000ull
+#define NIC3_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC3_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5583080ull
+#define NIC3_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC3_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5583100ull
+#define NIC3_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC3_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5583180ull
+#define NIC3_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC3_UMR0_3_SPECIAL_BASE 0x5583E80ull
+#define NIC3_UMR0_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR0_3_SPECIAL_SECTION 0x1800
+#define mmNIC3_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5584000ull
+#define NIC3_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC3_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5584080ull
+#define NIC3_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC3_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5584100ull
+#define NIC3_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC3_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5584180ull
+#define NIC3_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC3_UMR0_4_SPECIAL_BASE 0x5584E80ull
+#define NIC3_UMR0_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR0_4_SPECIAL_SECTION 0x1800
+#define mmNIC3_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5585000ull
+#define NIC3_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC3_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5585080ull
+#define NIC3_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC3_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5585100ull
+#define NIC3_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC3_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5585180ull
+#define NIC3_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC3_UMR0_5_SPECIAL_BASE 0x5585E80ull
+#define NIC3_UMR0_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR0_5_SPECIAL_SECTION 0x1800
+#define mmNIC3_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5586000ull
+#define NIC3_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC3_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5586080ull
+#define NIC3_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC3_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5586100ull
+#define NIC3_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC3_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5586180ull
+#define NIC3_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC3_UMR0_6_SPECIAL_BASE 0x5586E80ull
+#define NIC3_UMR0_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR0_6_SPECIAL_SECTION 0x1800
+#define mmNIC3_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5587000ull
+#define NIC3_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC3_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5587080ull
+#define NIC3_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC3_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5587100ull
+#define NIC3_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC3_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5587180ull
+#define NIC3_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC3_UMR0_7_SPECIAL_BASE 0x5587E80ull
+#define NIC3_UMR0_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR0_7_SPECIAL_SECTION 0x1800
+#define mmNIC3_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5588000ull
+#define NIC3_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC3_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5588080ull
+#define NIC3_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC3_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5588100ull
+#define NIC3_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC3_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5588180ull
+#define NIC3_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC3_UMR0_8_SPECIAL_BASE 0x5588E80ull
+#define NIC3_UMR0_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR0_8_SPECIAL_SECTION 0x1800
+#define mmNIC3_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5589000ull
+#define NIC3_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC3_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5589080ull
+#define NIC3_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC3_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5589100ull
+#define NIC3_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC3_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5589180ull
+#define NIC3_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC3_UMR0_9_SPECIAL_BASE 0x5589E80ull
+#define NIC3_UMR0_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR0_9_SPECIAL_SECTION 0x1800
+#define mmNIC3_UMR0_10_UNSECURE_DOORBELL0_BASE 0x558A000ull
+#define NIC3_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC3_UMR0_10_UNSECURE_DOORBELL1_BASE 0x558A080ull
+#define NIC3_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC3_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x558A100ull
+#define NIC3_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC3_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x558A180ull
+#define NIC3_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC3_UMR0_10_SPECIAL_BASE 0x558AE80ull
+#define NIC3_UMR0_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR0_10_SPECIAL_SECTION 0x1800
+#define mmNIC3_UMR0_11_UNSECURE_DOORBELL0_BASE 0x558B000ull
+#define NIC3_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC3_UMR0_11_UNSECURE_DOORBELL1_BASE 0x558B080ull
+#define NIC3_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC3_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x558B100ull
+#define NIC3_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC3_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x558B180ull
+#define NIC3_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC3_UMR0_11_SPECIAL_BASE 0x558BE80ull
+#define NIC3_UMR0_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR0_11_SPECIAL_SECTION 0x1800
+#define mmNIC3_UMR0_12_UNSECURE_DOORBELL0_BASE 0x558C000ull
+#define NIC3_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC3_UMR0_12_UNSECURE_DOORBELL1_BASE 0x558C080ull
+#define NIC3_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC3_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x558C100ull
+#define NIC3_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC3_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x558C180ull
+#define NIC3_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC3_UMR0_12_SPECIAL_BASE 0x558CE80ull
+#define NIC3_UMR0_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR0_12_SPECIAL_SECTION 0x1800
+#define mmNIC3_UMR0_13_UNSECURE_DOORBELL0_BASE 0x558D000ull
+#define NIC3_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC3_UMR0_13_UNSECURE_DOORBELL1_BASE 0x558D080ull
+#define NIC3_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC3_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x558D100ull
+#define NIC3_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC3_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x558D180ull
+#define NIC3_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC3_UMR0_13_SPECIAL_BASE 0x558DE80ull
+#define NIC3_UMR0_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR0_13_SPECIAL_SECTION 0x1800
+#define mmNIC3_UMR0_14_UNSECURE_DOORBELL0_BASE 0x558E000ull
+#define NIC3_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC3_UMR0_14_UNSECURE_DOORBELL1_BASE 0x558E080ull
+#define NIC3_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC3_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x558E100ull
+#define NIC3_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC3_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x558E180ull
+#define NIC3_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC3_UMR0_14_SPECIAL_BASE 0x558EE80ull
+#define NIC3_UMR0_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR0_14_SPECIAL_SECTION 0x1180
+#define mmNIC3_QM_DCCM0_BASE 0x5590000ull
+#define NIC3_QM_DCCM0_MAX_OFFSET 0x4000
+#define NIC3_QM_DCCM0_SECTION 0x8000
+#define mmNIC3_QM_ARC_AUX0_BASE 0x5598000ull
+#define NIC3_QM_ARC_AUX0_MAX_OFFSET 0x1000
+#define NIC3_QM_ARC_AUX0_SECTION 0xE800
+#define mmNIC3_QM_ARC_AUX0_SPECIAL_BASE 0x5598E80ull
+#define NIC3_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_QM_ARC_AUX0_SPECIAL_SECTION 0x1180
+#define mmNIC3_QM0_BASE 0x559A000ull
+#define NIC3_QM0_MAX_OFFSET 0x1000
+#define NIC3_QM0_SECTION 0x9000
+#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x559A900ull
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x559A908ull
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x559A910ull
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x559A918ull
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x559A920ull
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x559A928ull
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x559A930ull
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x559A938ull
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x559A940ull
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x559A948ull
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x559A950ull
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x559A958ull
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x559A960ull
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x559A968ull
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x559A970ull
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x559A978ull
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC3_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmNIC3_QM0_AXUSER_SECURED_BASE 0x559AB00ull
+#define NIC3_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC3_QM0_AXUSER_SECURED_SECTION 0x8000
+#define mmNIC3_QM0_AXUSER_NONSECURED_BASE 0x559AB80ull
+#define NIC3_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC3_QM0_AXUSER_NONSECURED_SECTION 0x8000
+#define mmNIC3_QM0_DBG_HBW_BASE 0x559AC00ull
+#define NIC3_QM0_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC3_QM0_DBG_HBW_SECTION 0x8000
+#define mmNIC3_QM0_DBG_LBW_BASE 0x559AC80ull
+#define NIC3_QM0_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC3_QM0_DBG_LBW_SECTION 0x1000
+#define mmNIC3_QM0_CGM_BASE 0x559AD80ull
+#define NIC3_QM0_CGM_MAX_OFFSET 0xC000
+#define NIC3_QM0_CGM_SECTION 0x1000
+#define mmNIC3_QM0_SPECIAL_BASE 0x559AE80ull
+#define NIC3_QM0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_QM0_SPECIAL_SECTION 0x4180
+#define mmNIC3_QPC0_BASE 0x559F000ull
+#define NIC3_QPC0_MAX_OFFSET 0x1000
+#define NIC3_QPC0_SECTION 0x7200
+#define mmNIC3_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x559F720ull
+#define NIC3_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x559F728ull
+#define NIC3_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x559F730ull
+#define NIC3_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x559F738ull
+#define NIC3_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x559F740ull
+#define NIC3_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x559F748ull
+#define NIC3_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x559F750ull
+#define NIC3_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x559F758ull
+#define NIC3_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x559F760ull
+#define NIC3_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x559F768ull
+#define NIC3_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x559F770ull
+#define NIC3_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x559F778ull
+#define NIC3_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x559F780ull
+#define NIC3_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x559F788ull
+#define NIC3_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x559F790ull
+#define NIC3_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x559F798ull
+#define NIC3_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x559F7A0ull
+#define NIC3_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x559F7A8ull
+#define NIC3_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x559F7B0ull
+#define NIC3_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x559F7B8ull
+#define NIC3_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x559F7C0ull
+#define NIC3_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x559F7C8ull
+#define NIC3_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x559F7D0ull
+#define NIC3_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x559F7D8ull
+#define NIC3_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x559F7E0ull
+#define NIC3_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x559F7E8ull
+#define NIC3_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x559F7F0ull
+#define NIC3_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x559F7F8ull
+#define NIC3_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x559F800ull
+#define NIC3_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x559F808ull
+#define NIC3_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x559F810ull
+#define NIC3_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x559F818ull
+#define NIC3_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define mmNIC3_QPC0_AXUSER_CONG_QUE_BASE 0x559FB80ull
+#define NIC3_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC3_QPC0_AXUSER_CONG_QUE_SECTION 0x6000
+#define mmNIC3_QPC0_AXUSER_RXWQE_BASE 0x559FBE0ull
+#define NIC3_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC3_QPC0_AXUSER_RXWQE_SECTION 0x6000
+#define mmNIC3_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x559FC40ull
+#define NIC3_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC3_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define mmNIC3_QPC0_AXUSER_DB_FIFO_BASE 0x559FCA0ull
+#define NIC3_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC3_QPC0_AXUSER_DB_FIFO_SECTION 0x6000
+#define mmNIC3_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x559FD00ull
+#define NIC3_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC3_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define mmNIC3_QPC0_AXUSER_ERR_FIFO_BASE 0x559FD60ull
+#define NIC3_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC3_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000
+#define mmNIC3_QPC0_AXUSER_QPC_RESP_BASE 0x559FDC0ull
+#define NIC3_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC3_QPC0_AXUSER_QPC_RESP_SECTION 0x6000
+#define mmNIC3_QPC0_AXUSER_QPC_REQ_BASE 0x559FE20ull
+#define NIC3_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC3_QPC0_AXUSER_QPC_REQ_SECTION 0x6000
+#define mmNIC3_QPC0_SPECIAL_BASE 0x559FE80ull
+#define NIC3_QPC0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_QPC0_SPECIAL_SECTION 0x1800
+#define mmNIC3_UMR1_0_UNSECURE_DOORBELL0_BASE 0x55A0000ull
+#define NIC3_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC3_UMR1_0_UNSECURE_DOORBELL1_BASE 0x55A0080ull
+#define NIC3_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC3_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x55A0100ull
+#define NIC3_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC3_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x55A0180ull
+#define NIC3_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC3_UMR1_0_SPECIAL_BASE 0x55A0E80ull
+#define NIC3_UMR1_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR1_0_SPECIAL_SECTION 0x1800
+#define mmNIC3_UMR1_1_UNSECURE_DOORBELL0_BASE 0x55A1000ull
+#define NIC3_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC3_UMR1_1_UNSECURE_DOORBELL1_BASE 0x55A1080ull
+#define NIC3_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC3_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x55A1100ull
+#define NIC3_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC3_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x55A1180ull
+#define NIC3_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC3_UMR1_1_SPECIAL_BASE 0x55A1E80ull
+#define NIC3_UMR1_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR1_1_SPECIAL_SECTION 0x1800
+#define mmNIC3_UMR1_2_UNSECURE_DOORBELL0_BASE 0x55A2000ull
+#define NIC3_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC3_UMR1_2_UNSECURE_DOORBELL1_BASE 0x55A2080ull
+#define NIC3_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC3_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x55A2100ull
+#define NIC3_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC3_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x55A2180ull
+#define NIC3_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC3_UMR1_2_SPECIAL_BASE 0x55A2E80ull
+#define NIC3_UMR1_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR1_2_SPECIAL_SECTION 0x1800
+#define mmNIC3_UMR1_3_UNSECURE_DOORBELL0_BASE 0x55A3000ull
+#define NIC3_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC3_UMR1_3_UNSECURE_DOORBELL1_BASE 0x55A3080ull
+#define NIC3_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC3_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x55A3100ull
+#define NIC3_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC3_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x55A3180ull
+#define NIC3_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC3_UMR1_3_SPECIAL_BASE 0x55A3E80ull
+#define NIC3_UMR1_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR1_3_SPECIAL_SECTION 0x1800
+#define mmNIC3_UMR1_4_UNSECURE_DOORBELL0_BASE 0x55A4000ull
+#define NIC3_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC3_UMR1_4_UNSECURE_DOORBELL1_BASE 0x55A4080ull
+#define NIC3_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC3_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x55A4100ull
+#define NIC3_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC3_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x55A4180ull
+#define NIC3_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC3_UMR1_4_SPECIAL_BASE 0x55A4E80ull
+#define NIC3_UMR1_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR1_4_SPECIAL_SECTION 0x1800
+#define mmNIC3_UMR1_5_UNSECURE_DOORBELL0_BASE 0x55A5000ull
+#define NIC3_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC3_UMR1_5_UNSECURE_DOORBELL1_BASE 0x55A5080ull
+#define NIC3_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC3_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x55A5100ull
+#define NIC3_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC3_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x55A5180ull
+#define NIC3_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC3_UMR1_5_SPECIAL_BASE 0x55A5E80ull
+#define NIC3_UMR1_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR1_5_SPECIAL_SECTION 0x1800
+#define mmNIC3_UMR1_6_UNSECURE_DOORBELL0_BASE 0x55A6000ull
+#define NIC3_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC3_UMR1_6_UNSECURE_DOORBELL1_BASE 0x55A6080ull
+#define NIC3_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC3_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x55A6100ull
+#define NIC3_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC3_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x55A6180ull
+#define NIC3_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC3_UMR1_6_SPECIAL_BASE 0x55A6E80ull
+#define NIC3_UMR1_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR1_6_SPECIAL_SECTION 0x1800
+#define mmNIC3_UMR1_7_UNSECURE_DOORBELL0_BASE 0x55A7000ull
+#define NIC3_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC3_UMR1_7_UNSECURE_DOORBELL1_BASE 0x55A7080ull
+#define NIC3_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC3_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x55A7100ull
+#define NIC3_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC3_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x55A7180ull
+#define NIC3_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC3_UMR1_7_SPECIAL_BASE 0x55A7E80ull
+#define NIC3_UMR1_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR1_7_SPECIAL_SECTION 0x1800
+#define mmNIC3_UMR1_8_UNSECURE_DOORBELL0_BASE 0x55A8000ull
+#define NIC3_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC3_UMR1_8_UNSECURE_DOORBELL1_BASE 0x55A8080ull
+#define NIC3_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC3_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x55A8100ull
+#define NIC3_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC3_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x55A8180ull
+#define NIC3_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC3_UMR1_8_SPECIAL_BASE 0x55A8E80ull
+#define NIC3_UMR1_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR1_8_SPECIAL_SECTION 0x1800
+#define mmNIC3_UMR1_9_UNSECURE_DOORBELL0_BASE 0x55A9000ull
+#define NIC3_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC3_UMR1_9_UNSECURE_DOORBELL1_BASE 0x55A9080ull
+#define NIC3_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC3_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x55A9100ull
+#define NIC3_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC3_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x55A9180ull
+#define NIC3_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC3_UMR1_9_SPECIAL_BASE 0x55A9E80ull
+#define NIC3_UMR1_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR1_9_SPECIAL_SECTION 0x1800
+#define mmNIC3_UMR1_10_UNSECURE_DOORBELL0_BASE 0x55AA000ull
+#define NIC3_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC3_UMR1_10_UNSECURE_DOORBELL1_BASE 0x55AA080ull
+#define NIC3_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC3_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x55AA100ull
+#define NIC3_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC3_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x55AA180ull
+#define NIC3_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC3_UMR1_10_SPECIAL_BASE 0x55AAE80ull
+#define NIC3_UMR1_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR1_10_SPECIAL_SECTION 0x1800
+#define mmNIC3_UMR1_11_UNSECURE_DOORBELL0_BASE 0x55AB000ull
+#define NIC3_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC3_UMR1_11_UNSECURE_DOORBELL1_BASE 0x55AB080ull
+#define NIC3_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC3_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x55AB100ull
+#define NIC3_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC3_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x55AB180ull
+#define NIC3_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC3_UMR1_11_SPECIAL_BASE 0x55ABE80ull
+#define NIC3_UMR1_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR1_11_SPECIAL_SECTION 0x1800
+#define mmNIC3_UMR1_12_UNSECURE_DOORBELL0_BASE 0x55AC000ull
+#define NIC3_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC3_UMR1_12_UNSECURE_DOORBELL1_BASE 0x55AC080ull
+#define NIC3_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC3_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x55AC100ull
+#define NIC3_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC3_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x55AC180ull
+#define NIC3_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC3_UMR1_12_SPECIAL_BASE 0x55ACE80ull
+#define NIC3_UMR1_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR1_12_SPECIAL_SECTION 0x1800
+#define mmNIC3_UMR1_13_UNSECURE_DOORBELL0_BASE 0x55AD000ull
+#define NIC3_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC3_UMR1_13_UNSECURE_DOORBELL1_BASE 0x55AD080ull
+#define NIC3_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC3_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x55AD100ull
+#define NIC3_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC3_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x55AD180ull
+#define NIC3_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC3_UMR1_13_SPECIAL_BASE 0x55ADE80ull
+#define NIC3_UMR1_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR1_13_SPECIAL_SECTION 0x1800
+#define mmNIC3_UMR1_14_UNSECURE_DOORBELL0_BASE 0x55AE000ull
+#define NIC3_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC3_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC3_UMR1_14_UNSECURE_DOORBELL1_BASE 0x55AE080ull
+#define NIC3_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC3_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC3_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x55AE100ull
+#define NIC3_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC3_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC3_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x55AE180ull
+#define NIC3_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC3_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC3_UMR1_14_SPECIAL_BASE 0x55AEE80ull
+#define NIC3_UMR1_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_UMR1_14_SPECIAL_SECTION 0x1180
+#define mmNIC3_QM_DCCM1_BASE 0x55B0000ull
+#define NIC3_QM_DCCM1_MAX_OFFSET 0x4000
+#define NIC3_QM_DCCM1_SECTION 0x8000
+#define mmNIC3_QM_ARC_AUX1_BASE 0x55B8000ull
+#define NIC3_QM_ARC_AUX1_MAX_OFFSET 0x1000
+#define NIC3_QM_ARC_AUX1_SECTION 0xE800
+#define mmNIC3_QM_ARC_AUX1_SPECIAL_BASE 0x55B8E80ull
+#define NIC3_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_QM_ARC_AUX1_SPECIAL_SECTION 0x1180
+#define mmNIC3_QM1_BASE 0x55BA000ull
+#define NIC3_QM1_MAX_OFFSET 0x1000
+#define NIC3_QM1_SECTION 0x9000
+#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x55BA900ull
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x55BA908ull
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x55BA910ull
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x55BA918ull
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x55BA920ull
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x55BA928ull
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x55BA930ull
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x55BA938ull
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x55BA940ull
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x55BA948ull
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x55BA950ull
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x55BA958ull
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x55BA960ull
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x55BA968ull
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x55BA970ull
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x55BA978ull
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC3_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmNIC3_QM1_AXUSER_SECURED_BASE 0x55BAB00ull
+#define NIC3_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC3_QM1_AXUSER_SECURED_SECTION 0x8000
+#define mmNIC3_QM1_AXUSER_NONSECURED_BASE 0x55BAB80ull
+#define NIC3_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC3_QM1_AXUSER_NONSECURED_SECTION 0x8000
+#define mmNIC3_QM1_DBG_HBW_BASE 0x55BAC00ull
+#define NIC3_QM1_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC3_QM1_DBG_HBW_SECTION 0x8000
+#define mmNIC3_QM1_DBG_LBW_BASE 0x55BAC80ull
+#define NIC3_QM1_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC3_QM1_DBG_LBW_SECTION 0x1000
+#define mmNIC3_QM1_CGM_BASE 0x55BAD80ull
+#define NIC3_QM1_CGM_MAX_OFFSET 0xC000
+#define NIC3_QM1_CGM_SECTION 0x1000
+#define mmNIC3_QM1_SPECIAL_BASE 0x55BAE80ull
+#define NIC3_QM1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_QM1_SPECIAL_SECTION 0x4180
+#define mmNIC3_QPC1_BASE 0x55BF000ull
+#define NIC3_QPC1_MAX_OFFSET 0x1000
+#define NIC3_QPC1_SECTION 0x7200
+#define mmNIC3_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x55BF720ull
+#define NIC3_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x55BF728ull
+#define NIC3_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x55BF730ull
+#define NIC3_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x55BF738ull
+#define NIC3_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x55BF740ull
+#define NIC3_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x55BF748ull
+#define NIC3_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x55BF750ull
+#define NIC3_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x55BF758ull
+#define NIC3_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x55BF760ull
+#define NIC3_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x55BF768ull
+#define NIC3_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x55BF770ull
+#define NIC3_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x55BF778ull
+#define NIC3_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x55BF780ull
+#define NIC3_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x55BF788ull
+#define NIC3_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x55BF790ull
+#define NIC3_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x55BF798ull
+#define NIC3_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x55BF7A0ull
+#define NIC3_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x55BF7A8ull
+#define NIC3_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x55BF7B0ull
+#define NIC3_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x55BF7B8ull
+#define NIC3_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x55BF7C0ull
+#define NIC3_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x55BF7C8ull
+#define NIC3_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x55BF7D0ull
+#define NIC3_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x55BF7D8ull
+#define NIC3_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x55BF7E0ull
+#define NIC3_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x55BF7E8ull
+#define NIC3_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x55BF7F0ull
+#define NIC3_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x55BF7F8ull
+#define NIC3_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x55BF800ull
+#define NIC3_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x55BF808ull
+#define NIC3_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x55BF810ull
+#define NIC3_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC3_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x55BF818ull
+#define NIC3_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC3_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define mmNIC3_QPC1_AXUSER_CONG_QUE_BASE 0x55BFB80ull
+#define NIC3_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC3_QPC1_AXUSER_CONG_QUE_SECTION 0x6000
+#define mmNIC3_QPC1_AXUSER_RXWQE_BASE 0x55BFBE0ull
+#define NIC3_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC3_QPC1_AXUSER_RXWQE_SECTION 0x6000
+#define mmNIC3_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x55BFC40ull
+#define NIC3_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC3_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define mmNIC3_QPC1_AXUSER_DB_FIFO_BASE 0x55BFCA0ull
+#define NIC3_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC3_QPC1_AXUSER_DB_FIFO_SECTION 0x6000
+#define mmNIC3_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x55BFD00ull
+#define NIC3_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC3_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define mmNIC3_QPC1_AXUSER_ERR_FIFO_BASE 0x55BFD60ull
+#define NIC3_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC3_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000
+#define mmNIC3_QPC1_AXUSER_QPC_RESP_BASE 0x55BFDC0ull
+#define NIC3_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC3_QPC1_AXUSER_QPC_RESP_SECTION 0x6000
+#define mmNIC3_QPC1_AXUSER_QPC_REQ_BASE 0x55BFE20ull
+#define NIC3_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC3_QPC1_AXUSER_QPC_REQ_SECTION 0x6000
+#define mmNIC3_QPC1_SPECIAL_BASE 0x55BFE80ull
+#define NIC3_QPC1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_QPC1_SPECIAL_SECTION 0x8180
+#define mmNIC3_TMR_BASE 0x55C8000ull
+#define NIC3_TMR_MAX_OFFSET 0x1000
+#define NIC3_TMR_SECTION 0xD600
+#define mmNIC3_TMR_AXUSER_TMR_FREE_LIST_BASE 0x55C8D60ull
+#define NIC3_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000
+#define NIC3_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000
+#define mmNIC3_TMR_AXUSER_TMR_FIFO_BASE 0x55C8DC0ull
+#define NIC3_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000
+#define NIC3_TMR_AXUSER_TMR_FIFO_SECTION 0x6000
+#define mmNIC3_TMR_AXUSER_TMR_FSM_BASE 0x55C8E20ull
+#define NIC3_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000
+#define NIC3_TMR_AXUSER_TMR_FSM_SECTION 0x6000
+#define mmNIC3_TMR_SPECIAL_BASE 0x55C8E80ull
+#define NIC3_TMR_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_TMR_SPECIAL_SECTION 0x1800
+#define mmNIC3_RXB_CORE_BASE 0x55C9000ull
+#define NIC3_RXB_CORE_MAX_OFFSET 0x1000
+#define NIC3_RXB_CORE_SECTION 0x6100
+#define mmNIC3_RXB_CORE_SCT_AWUSER_BASE 0x55C9610ull
+#define NIC3_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000
+#define NIC3_RXB_CORE_SCT_AWUSER_SECTION 0x8700
+#define mmNIC3_RXB_CORE_SPECIAL_BASE 0x55C9E80ull
+#define NIC3_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_RXB_CORE_SPECIAL_SECTION 0x1800
+#define mmNIC3_RXE0_BASE 0x55CA000ull
+#define NIC3_RXE0_MAX_OFFSET 0x1000
+#define NIC3_RXE0_SECTION 0x9000
+#define mmNIC3_RXE0_WQE_ARUSER_BASE 0x55CA900ull
+#define NIC3_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC3_RXE0_WQE_ARUSER_SECTION 0x5800
+#define mmNIC3_RXE0_SPECIAL_BASE 0x55CAE80ull
+#define NIC3_RXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_RXE0_SPECIAL_SECTION 0x1800
+#define mmNIC3_RXE1_BASE 0x55CB000ull
+#define NIC3_RXE1_MAX_OFFSET 0x1000
+#define NIC3_RXE1_SECTION 0x9000
+#define mmNIC3_RXE1_WQE_ARUSER_BASE 0x55CB900ull
+#define NIC3_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC3_RXE1_WQE_ARUSER_SECTION 0x5800
+#define mmNIC3_RXE1_SPECIAL_BASE 0x55CBE80ull
+#define NIC3_RXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_RXE1_SPECIAL_SECTION 0x1800
+#define mmNIC3_RXE0_AXUSER_AXUSER_CQ0_BASE 0x55CC000ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define mmNIC3_RXE0_AXUSER_AXUSER_CQ1_BASE 0x55CC050ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define mmNIC3_RXE0_AXUSER_AXUSER_CQ2_BASE 0x55CC0A0ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define mmNIC3_RXE0_AXUSER_AXUSER_CQ3_BASE 0x55CC0F0ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define mmNIC3_RXE0_AXUSER_AXUSER_CQ4_BASE 0x55CC140ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define mmNIC3_RXE0_AXUSER_AXUSER_CQ5_BASE 0x55CC190ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define mmNIC3_RXE0_AXUSER_AXUSER_CQ6_BASE 0x55CC1E0ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define mmNIC3_RXE0_AXUSER_AXUSER_CQ7_BASE 0x55CC230ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define mmNIC3_RXE0_AXUSER_AXUSER_CQ8_BASE 0x55CC280ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define mmNIC3_RXE0_AXUSER_AXUSER_CQ9_BASE 0x55CC2D0ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define mmNIC3_RXE0_AXUSER_AXUSER_CQ10_BASE 0x55CC320ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define mmNIC3_RXE0_AXUSER_AXUSER_CQ11_BASE 0x55CC370ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define mmNIC3_RXE0_AXUSER_AXUSER_CQ12_BASE 0x55CC3C0ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define mmNIC3_RXE0_AXUSER_AXUSER_CQ13_BASE 0x55CC410ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define mmNIC3_RXE0_AXUSER_AXUSER_CQ14_BASE 0x55CC460ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define mmNIC3_RXE0_AXUSER_AXUSER_CQ15_BASE 0x55CC4B0ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define mmNIC3_RXE0_AXUSER_AXUSER_CQ16_BASE 0x55CC500ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define mmNIC3_RXE0_AXUSER_AXUSER_CQ17_BASE 0x55CC550ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define mmNIC3_RXE0_AXUSER_AXUSER_CQ18_BASE 0x55CC5A0ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define mmNIC3_RXE0_AXUSER_AXUSER_CQ19_BASE 0x55CC5F0ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define mmNIC3_RXE0_AXUSER_AXUSER_CQ20_BASE 0x55CC640ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define mmNIC3_RXE0_AXUSER_AXUSER_CQ21_BASE 0x55CC690ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define mmNIC3_RXE0_AXUSER_AXUSER_CQ22_BASE 0x55CC6E0ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define mmNIC3_RXE0_AXUSER_AXUSER_CQ23_BASE 0x55CC730ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define mmNIC3_RXE0_AXUSER_AXUSER_CQ24_BASE 0x55CC780ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define mmNIC3_RXE0_AXUSER_AXUSER_CQ25_BASE 0x55CC7D0ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define mmNIC3_RXE0_AXUSER_AXUSER_CQ26_BASE 0x55CC820ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define mmNIC3_RXE0_AXUSER_AXUSER_CQ27_BASE 0x55CC870ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define mmNIC3_RXE0_AXUSER_AXUSER_CQ28_BASE 0x55CC8C0ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define mmNIC3_RXE0_AXUSER_AXUSER_CQ29_BASE 0x55CC910ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define mmNIC3_RXE0_AXUSER_AXUSER_CQ30_BASE 0x55CC960ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define mmNIC3_RXE0_AXUSER_AXUSER_CQ31_BASE 0x55CC9B0ull
+#define NIC3_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC3_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define mmNIC3_RXE0_AXUSER_SPECIAL_BASE 0x55CCE80ull
+#define NIC3_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_RXE0_AXUSER_SPECIAL_SECTION 0x1800
+#define mmNIC3_RXE1_AXUSER_AXUSER_CQ0_BASE 0x55CD000ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define mmNIC3_RXE1_AXUSER_AXUSER_CQ1_BASE 0x55CD050ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define mmNIC3_RXE1_AXUSER_AXUSER_CQ2_BASE 0x55CD0A0ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define mmNIC3_RXE1_AXUSER_AXUSER_CQ3_BASE 0x55CD0F0ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define mmNIC3_RXE1_AXUSER_AXUSER_CQ4_BASE 0x55CD140ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define mmNIC3_RXE1_AXUSER_AXUSER_CQ5_BASE 0x55CD190ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define mmNIC3_RXE1_AXUSER_AXUSER_CQ6_BASE 0x55CD1E0ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define mmNIC3_RXE1_AXUSER_AXUSER_CQ7_BASE 0x55CD230ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define mmNIC3_RXE1_AXUSER_AXUSER_CQ8_BASE 0x55CD280ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define mmNIC3_RXE1_AXUSER_AXUSER_CQ9_BASE 0x55CD2D0ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define mmNIC3_RXE1_AXUSER_AXUSER_CQ10_BASE 0x55CD320ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define mmNIC3_RXE1_AXUSER_AXUSER_CQ11_BASE 0x55CD370ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define mmNIC3_RXE1_AXUSER_AXUSER_CQ12_BASE 0x55CD3C0ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define mmNIC3_RXE1_AXUSER_AXUSER_CQ13_BASE 0x55CD410ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define mmNIC3_RXE1_AXUSER_AXUSER_CQ14_BASE 0x55CD460ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define mmNIC3_RXE1_AXUSER_AXUSER_CQ15_BASE 0x55CD4B0ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define mmNIC3_RXE1_AXUSER_AXUSER_CQ16_BASE 0x55CD500ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define mmNIC3_RXE1_AXUSER_AXUSER_CQ17_BASE 0x55CD550ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define mmNIC3_RXE1_AXUSER_AXUSER_CQ18_BASE 0x55CD5A0ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define mmNIC3_RXE1_AXUSER_AXUSER_CQ19_BASE 0x55CD5F0ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define mmNIC3_RXE1_AXUSER_AXUSER_CQ20_BASE 0x55CD640ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define mmNIC3_RXE1_AXUSER_AXUSER_CQ21_BASE 0x55CD690ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define mmNIC3_RXE1_AXUSER_AXUSER_CQ22_BASE 0x55CD6E0ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define mmNIC3_RXE1_AXUSER_AXUSER_CQ23_BASE 0x55CD730ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define mmNIC3_RXE1_AXUSER_AXUSER_CQ24_BASE 0x55CD780ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define mmNIC3_RXE1_AXUSER_AXUSER_CQ25_BASE 0x55CD7D0ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define mmNIC3_RXE1_AXUSER_AXUSER_CQ26_BASE 0x55CD820ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define mmNIC3_RXE1_AXUSER_AXUSER_CQ27_BASE 0x55CD870ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define mmNIC3_RXE1_AXUSER_AXUSER_CQ28_BASE 0x55CD8C0ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define mmNIC3_RXE1_AXUSER_AXUSER_CQ29_BASE 0x55CD910ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define mmNIC3_RXE1_AXUSER_AXUSER_CQ30_BASE 0x55CD960ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define mmNIC3_RXE1_AXUSER_AXUSER_CQ31_BASE 0x55CD9B0ull
+#define NIC3_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC3_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define mmNIC3_RXE1_AXUSER_SPECIAL_BASE 0x55CDE80ull
+#define NIC3_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_RXE1_AXUSER_SPECIAL_SECTION 0x2180
+#define mmNIC3_TXS0_BASE 0x55D0000ull
+#define NIC3_TXS0_MAX_OFFSET 0x1000
+#define NIC3_TXS0_SECTION 0xE800
+#define mmNIC3_TXS0_SPECIAL_BASE 0x55D0E80ull
+#define NIC3_TXS0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_TXS0_SPECIAL_SECTION 0x1800
+#define mmNIC3_TXS1_BASE 0x55D1000ull
+#define NIC3_TXS1_MAX_OFFSET 0x1000
+#define NIC3_TXS1_SECTION 0xE800
+#define mmNIC3_TXS1_SPECIAL_BASE 0x55D1E80ull
+#define NIC3_TXS1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_TXS1_SPECIAL_SECTION 0x1800
+#define mmNIC3_TXE0_BASE 0x55D2000ull
+#define NIC3_TXE0_MAX_OFFSET 0x1000
+#define NIC3_TXE0_SECTION 0xE800
+#define mmNIC3_TXE0_SPECIAL_BASE 0x55D2E80ull
+#define NIC3_TXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_TXE0_SPECIAL_SECTION 0x1800
+#define mmNIC3_TXE1_BASE 0x55D3000ull
+#define NIC3_TXE1_MAX_OFFSET 0x1000
+#define NIC3_TXE1_SECTION 0xE800
+#define mmNIC3_TXE1_SPECIAL_BASE 0x55D3E80ull
+#define NIC3_TXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_TXE1_SPECIAL_SECTION 0x1800
+#define mmNIC3_TXB_BASE 0x55D4000ull
+#define NIC3_TXB_MAX_OFFSET 0x1000
+#define NIC3_TXB_SECTION 0xE800
+#define mmNIC3_TXB_SPECIAL_BASE 0x55D4E80ull
+#define NIC3_TXB_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_TXB_SPECIAL_SECTION 0x1800
+#define mmNIC3_MSTR_IF_RR_SHRD_HBW_BASE 0x55D5000ull
+#define NIC3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define NIC3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmNIC3_MSTR_IF_RR_PRVT_HBW_BASE 0x55D5200ull
+#define NIC3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define NIC3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmNIC3_MSTR_IF_RR_SHRD_LBW_BASE 0x55D5400ull
+#define NIC3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define NIC3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmNIC3_MSTR_IF_RR_PRVT_LBW_BASE 0x55D5600ull
+#define NIC3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define NIC3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmNIC3_MSTR_IF_E2E_CRDT_BASE 0x55D5800ull
+#define NIC3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define NIC3_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmNIC3_MSTR_IF_AXUSER_BASE 0x55D5A80ull
+#define NIC3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define NIC3_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmNIC3_MSTR_IF_DBG_HBW_BASE 0x55D5B00ull
+#define NIC3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC3_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmNIC3_MSTR_IF_DBG_LBW_BASE 0x55D5B80ull
+#define NIC3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC3_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmNIC3_MSTR_IF_CORE_HBW_BASE 0x55D5C00ull
+#define NIC3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define NIC3_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmNIC3_MSTR_IF_CORE_LBW_BASE 0x55D5D80ull
+#define NIC3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define NIC3_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmNIC3_MSTR_IF_SPECIAL_BASE 0x55D5E80ull
+#define NIC3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmNIC3_TX_AXUSER_BASE 0x55D6000ull
+#define NIC3_TX_AXUSER_MAX_OFFSET 0x5000
+#define NIC3_TX_AXUSER_SECTION 0x2000
+#define mmNIC3_SERDES0_BASE 0x55D8000ull
+#define NIC3_SERDES0_MAX_OFFSET 0x3E40
+#define NIC3_SERDES0_SECTION 0x4000
+#define mmNIC3_SERDES1_BASE 0x55DC000ull
+#define NIC3_SERDES1_MAX_OFFSET 0x3E40
+#define NIC3_SERDES1_SECTION 0x4000
+#define mmNIC3_PHY_BASE 0x55E0000ull
+#define NIC3_PHY_MAX_OFFSET 0x1000
+#define NIC3_PHY_SECTION 0xE800
+#define mmNIC3_PHY_SPECIAL_BASE 0x55E0E80ull
+#define NIC3_PHY_SPECIAL_MAX_OFFSET 0x1800
+#define NIC3_PHY_SPECIAL_SECTION 0x7180
+#define mmPRT3_MAC_AUX_BASE 0x55E8000ull
+#define PRT3_MAC_AUX_MAX_OFFSET 0x1000
+#define PRT3_MAC_AUX_SECTION 0xE800
+#define mmPRT3_MAC_AUX_SPECIAL_BASE 0x55E8E80ull
+#define PRT3_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define PRT3_MAC_AUX_SPECIAL_SECTION 0x1800
+#define mmPRT3_MAC_CORE_BASE 0x55E9000ull
+#define PRT3_MAC_CORE_MAX_OFFSET 0x1000
+#define PRT3_MAC_CORE_SECTION 0xE800
+#define mmPRT3_MAC_CORE_SPECIAL_BASE 0x55E9E80ull
+#define PRT3_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define PRT3_MAC_CORE_SPECIAL_SECTION 0x1800
+#define mmNIC3_MAC_RS_FEC_BASE 0x55EA000ull
+#define NIC3_MAC_RS_FEC_MAX_OFFSET 0x2DC0
+#define NIC3_MAC_RS_FEC_SECTION 0x1000
+#define mmNIC3_MAC_GLOB_STAT_CONTROL_REG_BASE 0x55EB000ull
+#define NIC3_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000
+#define NIC3_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000
+#define mmNIC3_MAC_GLOB_STAT_RX0_BASE 0x55EB100ull
+#define NIC3_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00
+#define NIC3_MAC_GLOB_STAT_RX0_SECTION 0x8C00
+#define mmNIC3_MAC_GLOB_STAT_RX1_BASE 0x55EB18Cull
+#define NIC3_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00
+#define NIC3_MAC_GLOB_STAT_RX1_SECTION 0x8C00
+#define mmNIC3_MAC_GLOB_STAT_RX2_BASE 0x55EB218ull
+#define NIC3_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00
+#define NIC3_MAC_GLOB_STAT_RX2_SECTION 0x8C00
+#define mmNIC3_MAC_GLOB_STAT_RX3_BASE 0x55EB2A4ull
+#define NIC3_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00
+#define NIC3_MAC_GLOB_STAT_RX3_SECTION 0x8C00
+#define mmNIC3_MAC_GLOB_STAT_TX0_BASE 0x55EB330ull
+#define NIC3_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800
+#define NIC3_MAC_GLOB_STAT_TX0_SECTION 0x6800
+#define mmNIC3_MAC_GLOB_STAT_TX1_BASE 0x55EB398ull
+#define NIC3_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800
+#define NIC3_MAC_GLOB_STAT_TX1_SECTION 0x6800
+#define mmNIC3_MAC_GLOB_STAT_TX2_BASE 0x55EB400ull
+#define NIC3_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800
+#define NIC3_MAC_GLOB_STAT_TX2_SECTION 0x6800
+#define mmNIC3_MAC_GLOB_STAT_TX3_BASE 0x55EB468ull
+#define NIC3_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800
+#define NIC3_MAC_GLOB_STAT_TX3_SECTION 0x3980
+#define mmNIC3_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x55EB800ull
+#define NIC3_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0
+#define NIC3_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000
+#define mmNIC3_MAC_CH0_MAC_PCS_BASE 0x55EC000ull
+#define NIC3_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC3_MAC_CH0_MAC_PCS_SECTION 0x4000
+#define mmNIC3_MAC_CH0_MAC_128_BASE 0x55EC400ull
+#define NIC3_MAC_CH0_MAC_128_MAX_OFFSET 0xA400
+#define NIC3_MAC_CH0_MAC_128_SECTION 0x4000
+#define mmNIC3_MAC_CH0_MAC_AN_BASE 0x55EC800ull
+#define NIC3_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400
+#define NIC3_MAC_CH0_MAC_AN_SECTION 0x8000
+#define mmNIC3_MAC_CH1_MAC_PCS_BASE 0x55ED000ull
+#define NIC3_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC3_MAC_CH1_MAC_PCS_SECTION 0x4000
+#define mmNIC3_MAC_CH1_MAC_128_BASE 0x55ED400ull
+#define NIC3_MAC_CH1_MAC_128_MAX_OFFSET 0xA400
+#define NIC3_MAC_CH1_MAC_128_SECTION 0x4000
+#define mmNIC3_MAC_CH1_MAC_AN_BASE 0x55ED800ull
+#define NIC3_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400
+#define NIC3_MAC_CH1_MAC_AN_SECTION 0x8000
+#define mmNIC3_MAC_CH2_MAC_PCS_BASE 0x55EE000ull
+#define NIC3_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC3_MAC_CH2_MAC_PCS_SECTION 0x4000
+#define mmNIC3_MAC_CH2_MAC_128_BASE 0x55EE400ull
+#define NIC3_MAC_CH2_MAC_128_MAX_OFFSET 0xA400
+#define NIC3_MAC_CH2_MAC_128_SECTION 0x4000
+#define mmNIC3_MAC_CH2_MAC_AN_BASE 0x55EE800ull
+#define NIC3_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400
+#define NIC3_MAC_CH2_MAC_AN_SECTION 0x8000
+#define mmNIC3_MAC_CH3_MAC_PCS_BASE 0x55EF000ull
+#define NIC3_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC3_MAC_CH3_MAC_PCS_SECTION 0x4000
+#define mmNIC3_MAC_CH3_MAC_128_BASE 0x55EF400ull
+#define NIC3_MAC_CH3_MAC_128_MAX_OFFSET 0xA400
+#define NIC3_MAC_CH3_MAC_128_SECTION 0x4000
+#define mmNIC3_MAC_CH3_MAC_AN_BASE 0x55EF800ull
+#define NIC3_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400
+#define NIC3_MAC_CH3_MAC_AN_SECTION 0x10800
+#define mmNIC4_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5600000ull
+#define NIC4_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC4_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5600080ull
+#define NIC4_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC4_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5600100ull
+#define NIC4_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC4_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5600180ull
+#define NIC4_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC4_UMR0_0_SPECIAL_BASE 0x5600E80ull
+#define NIC4_UMR0_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR0_0_SPECIAL_SECTION 0x1800
+#define mmNIC4_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5601000ull
+#define NIC4_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC4_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5601080ull
+#define NIC4_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC4_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5601100ull
+#define NIC4_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC4_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5601180ull
+#define NIC4_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC4_UMR0_1_SPECIAL_BASE 0x5601E80ull
+#define NIC4_UMR0_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR0_1_SPECIAL_SECTION 0x1800
+#define mmNIC4_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5602000ull
+#define NIC4_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC4_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5602080ull
+#define NIC4_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC4_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5602100ull
+#define NIC4_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC4_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5602180ull
+#define NIC4_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC4_UMR0_2_SPECIAL_BASE 0x5602E80ull
+#define NIC4_UMR0_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR0_2_SPECIAL_SECTION 0x1800
+#define mmNIC4_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5603000ull
+#define NIC4_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC4_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5603080ull
+#define NIC4_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC4_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5603100ull
+#define NIC4_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC4_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5603180ull
+#define NIC4_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC4_UMR0_3_SPECIAL_BASE 0x5603E80ull
+#define NIC4_UMR0_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR0_3_SPECIAL_SECTION 0x1800
+#define mmNIC4_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5604000ull
+#define NIC4_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC4_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5604080ull
+#define NIC4_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC4_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5604100ull
+#define NIC4_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC4_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5604180ull
+#define NIC4_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC4_UMR0_4_SPECIAL_BASE 0x5604E80ull
+#define NIC4_UMR0_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR0_4_SPECIAL_SECTION 0x1800
+#define mmNIC4_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5605000ull
+#define NIC4_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC4_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5605080ull
+#define NIC4_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC4_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5605100ull
+#define NIC4_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC4_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5605180ull
+#define NIC4_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC4_UMR0_5_SPECIAL_BASE 0x5605E80ull
+#define NIC4_UMR0_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR0_5_SPECIAL_SECTION 0x1800
+#define mmNIC4_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5606000ull
+#define NIC4_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC4_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5606080ull
+#define NIC4_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC4_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5606100ull
+#define NIC4_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC4_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5606180ull
+#define NIC4_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC4_UMR0_6_SPECIAL_BASE 0x5606E80ull
+#define NIC4_UMR0_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR0_6_SPECIAL_SECTION 0x1800
+#define mmNIC4_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5607000ull
+#define NIC4_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC4_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5607080ull
+#define NIC4_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC4_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5607100ull
+#define NIC4_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC4_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5607180ull
+#define NIC4_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC4_UMR0_7_SPECIAL_BASE 0x5607E80ull
+#define NIC4_UMR0_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR0_7_SPECIAL_SECTION 0x1800
+#define mmNIC4_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5608000ull
+#define NIC4_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC4_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5608080ull
+#define NIC4_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC4_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5608100ull
+#define NIC4_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC4_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5608180ull
+#define NIC4_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC4_UMR0_8_SPECIAL_BASE 0x5608E80ull
+#define NIC4_UMR0_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR0_8_SPECIAL_SECTION 0x1800
+#define mmNIC4_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5609000ull
+#define NIC4_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC4_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5609080ull
+#define NIC4_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC4_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5609100ull
+#define NIC4_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC4_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5609180ull
+#define NIC4_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC4_UMR0_9_SPECIAL_BASE 0x5609E80ull
+#define NIC4_UMR0_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR0_9_SPECIAL_SECTION 0x1800
+#define mmNIC4_UMR0_10_UNSECURE_DOORBELL0_BASE 0x560A000ull
+#define NIC4_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC4_UMR0_10_UNSECURE_DOORBELL1_BASE 0x560A080ull
+#define NIC4_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC4_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x560A100ull
+#define NIC4_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC4_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x560A180ull
+#define NIC4_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC4_UMR0_10_SPECIAL_BASE 0x560AE80ull
+#define NIC4_UMR0_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR0_10_SPECIAL_SECTION 0x1800
+#define mmNIC4_UMR0_11_UNSECURE_DOORBELL0_BASE 0x560B000ull
+#define NIC4_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC4_UMR0_11_UNSECURE_DOORBELL1_BASE 0x560B080ull
+#define NIC4_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC4_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x560B100ull
+#define NIC4_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC4_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x560B180ull
+#define NIC4_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC4_UMR0_11_SPECIAL_BASE 0x560BE80ull
+#define NIC4_UMR0_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR0_11_SPECIAL_SECTION 0x1800
+#define mmNIC4_UMR0_12_UNSECURE_DOORBELL0_BASE 0x560C000ull
+#define NIC4_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC4_UMR0_12_UNSECURE_DOORBELL1_BASE 0x560C080ull
+#define NIC4_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC4_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x560C100ull
+#define NIC4_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC4_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x560C180ull
+#define NIC4_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC4_UMR0_12_SPECIAL_BASE 0x560CE80ull
+#define NIC4_UMR0_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR0_12_SPECIAL_SECTION 0x1800
+#define mmNIC4_UMR0_13_UNSECURE_DOORBELL0_BASE 0x560D000ull
+#define NIC4_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC4_UMR0_13_UNSECURE_DOORBELL1_BASE 0x560D080ull
+#define NIC4_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC4_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x560D100ull
+#define NIC4_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC4_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x560D180ull
+#define NIC4_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC4_UMR0_13_SPECIAL_BASE 0x560DE80ull
+#define NIC4_UMR0_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR0_13_SPECIAL_SECTION 0x1800
+#define mmNIC4_UMR0_14_UNSECURE_DOORBELL0_BASE 0x560E000ull
+#define NIC4_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC4_UMR0_14_UNSECURE_DOORBELL1_BASE 0x560E080ull
+#define NIC4_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC4_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x560E100ull
+#define NIC4_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC4_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x560E180ull
+#define NIC4_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC4_UMR0_14_SPECIAL_BASE 0x560EE80ull
+#define NIC4_UMR0_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR0_14_SPECIAL_SECTION 0x1180
+#define mmNIC4_QM_DCCM0_BASE 0x5610000ull
+#define NIC4_QM_DCCM0_MAX_OFFSET 0x4000
+#define NIC4_QM_DCCM0_SECTION 0x8000
+#define mmNIC4_QM_ARC_AUX0_BASE 0x5618000ull
+#define NIC4_QM_ARC_AUX0_MAX_OFFSET 0x1000
+#define NIC4_QM_ARC_AUX0_SECTION 0xE800
+#define mmNIC4_QM_ARC_AUX0_SPECIAL_BASE 0x5618E80ull
+#define NIC4_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_QM_ARC_AUX0_SPECIAL_SECTION 0x1180
+#define mmNIC4_QM0_BASE 0x561A000ull
+#define NIC4_QM0_MAX_OFFSET 0x1000
+#define NIC4_QM0_SECTION 0x9000
+#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x561A900ull
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x561A908ull
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x561A910ull
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x561A918ull
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x561A920ull
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x561A928ull
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x561A930ull
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x561A938ull
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x561A940ull
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x561A948ull
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x561A950ull
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x561A958ull
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x561A960ull
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x561A968ull
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x561A970ull
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x561A978ull
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC4_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmNIC4_QM0_AXUSER_SECURED_BASE 0x561AB00ull
+#define NIC4_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC4_QM0_AXUSER_SECURED_SECTION 0x8000
+#define mmNIC4_QM0_AXUSER_NONSECURED_BASE 0x561AB80ull
+#define NIC4_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC4_QM0_AXUSER_NONSECURED_SECTION 0x8000
+#define mmNIC4_QM0_DBG_HBW_BASE 0x561AC00ull
+#define NIC4_QM0_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC4_QM0_DBG_HBW_SECTION 0x8000
+#define mmNIC4_QM0_DBG_LBW_BASE 0x561AC80ull
+#define NIC4_QM0_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC4_QM0_DBG_LBW_SECTION 0x1000
+#define mmNIC4_QM0_CGM_BASE 0x561AD80ull
+#define NIC4_QM0_CGM_MAX_OFFSET 0xC000
+#define NIC4_QM0_CGM_SECTION 0x1000
+#define mmNIC4_QM0_SPECIAL_BASE 0x561AE80ull
+#define NIC4_QM0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_QM0_SPECIAL_SECTION 0x4180
+#define mmNIC4_QPC0_BASE 0x561F000ull
+#define NIC4_QPC0_MAX_OFFSET 0x1000
+#define NIC4_QPC0_SECTION 0x7200
+#define mmNIC4_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x561F720ull
+#define NIC4_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x561F728ull
+#define NIC4_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x561F730ull
+#define NIC4_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x561F738ull
+#define NIC4_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x561F740ull
+#define NIC4_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x561F748ull
+#define NIC4_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x561F750ull
+#define NIC4_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x561F758ull
+#define NIC4_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x561F760ull
+#define NIC4_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x561F768ull
+#define NIC4_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x561F770ull
+#define NIC4_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x561F778ull
+#define NIC4_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x561F780ull
+#define NIC4_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x561F788ull
+#define NIC4_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x561F790ull
+#define NIC4_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x561F798ull
+#define NIC4_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x561F7A0ull
+#define NIC4_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x561F7A8ull
+#define NIC4_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x561F7B0ull
+#define NIC4_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x561F7B8ull
+#define NIC4_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x561F7C0ull
+#define NIC4_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x561F7C8ull
+#define NIC4_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x561F7D0ull
+#define NIC4_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x561F7D8ull
+#define NIC4_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x561F7E0ull
+#define NIC4_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x561F7E8ull
+#define NIC4_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x561F7F0ull
+#define NIC4_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x561F7F8ull
+#define NIC4_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x561F800ull
+#define NIC4_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x561F808ull
+#define NIC4_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x561F810ull
+#define NIC4_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x561F818ull
+#define NIC4_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define mmNIC4_QPC0_AXUSER_CONG_QUE_BASE 0x561FB80ull
+#define NIC4_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC4_QPC0_AXUSER_CONG_QUE_SECTION 0x6000
+#define mmNIC4_QPC0_AXUSER_RXWQE_BASE 0x561FBE0ull
+#define NIC4_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC4_QPC0_AXUSER_RXWQE_SECTION 0x6000
+#define mmNIC4_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x561FC40ull
+#define NIC4_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC4_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define mmNIC4_QPC0_AXUSER_DB_FIFO_BASE 0x561FCA0ull
+#define NIC4_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC4_QPC0_AXUSER_DB_FIFO_SECTION 0x6000
+#define mmNIC4_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x561FD00ull
+#define NIC4_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC4_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define mmNIC4_QPC0_AXUSER_ERR_FIFO_BASE 0x561FD60ull
+#define NIC4_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC4_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000
+#define mmNIC4_QPC0_AXUSER_QPC_RESP_BASE 0x561FDC0ull
+#define NIC4_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC4_QPC0_AXUSER_QPC_RESP_SECTION 0x6000
+#define mmNIC4_QPC0_AXUSER_QPC_REQ_BASE 0x561FE20ull
+#define NIC4_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC4_QPC0_AXUSER_QPC_REQ_SECTION 0x6000
+#define mmNIC4_QPC0_SPECIAL_BASE 0x561FE80ull
+#define NIC4_QPC0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_QPC0_SPECIAL_SECTION 0x1800
+#define mmNIC4_UMR1_0_UNSECURE_DOORBELL0_BASE 0x5620000ull
+#define NIC4_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC4_UMR1_0_UNSECURE_DOORBELL1_BASE 0x5620080ull
+#define NIC4_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC4_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x5620100ull
+#define NIC4_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC4_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x5620180ull
+#define NIC4_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC4_UMR1_0_SPECIAL_BASE 0x5620E80ull
+#define NIC4_UMR1_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR1_0_SPECIAL_SECTION 0x1800
+#define mmNIC4_UMR1_1_UNSECURE_DOORBELL0_BASE 0x5621000ull
+#define NIC4_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC4_UMR1_1_UNSECURE_DOORBELL1_BASE 0x5621080ull
+#define NIC4_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC4_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x5621100ull
+#define NIC4_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC4_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x5621180ull
+#define NIC4_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC4_UMR1_1_SPECIAL_BASE 0x5621E80ull
+#define NIC4_UMR1_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR1_1_SPECIAL_SECTION 0x1800
+#define mmNIC4_UMR1_2_UNSECURE_DOORBELL0_BASE 0x5622000ull
+#define NIC4_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC4_UMR1_2_UNSECURE_DOORBELL1_BASE 0x5622080ull
+#define NIC4_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC4_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x5622100ull
+#define NIC4_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC4_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x5622180ull
+#define NIC4_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC4_UMR1_2_SPECIAL_BASE 0x5622E80ull
+#define NIC4_UMR1_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR1_2_SPECIAL_SECTION 0x1800
+#define mmNIC4_UMR1_3_UNSECURE_DOORBELL0_BASE 0x5623000ull
+#define NIC4_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC4_UMR1_3_UNSECURE_DOORBELL1_BASE 0x5623080ull
+#define NIC4_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC4_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x5623100ull
+#define NIC4_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC4_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x5623180ull
+#define NIC4_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC4_UMR1_3_SPECIAL_BASE 0x5623E80ull
+#define NIC4_UMR1_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR1_3_SPECIAL_SECTION 0x1800
+#define mmNIC4_UMR1_4_UNSECURE_DOORBELL0_BASE 0x5624000ull
+#define NIC4_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC4_UMR1_4_UNSECURE_DOORBELL1_BASE 0x5624080ull
+#define NIC4_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC4_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x5624100ull
+#define NIC4_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC4_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x5624180ull
+#define NIC4_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC4_UMR1_4_SPECIAL_BASE 0x5624E80ull
+#define NIC4_UMR1_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR1_4_SPECIAL_SECTION 0x1800
+#define mmNIC4_UMR1_5_UNSECURE_DOORBELL0_BASE 0x5625000ull
+#define NIC4_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC4_UMR1_5_UNSECURE_DOORBELL1_BASE 0x5625080ull
+#define NIC4_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC4_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x5625100ull
+#define NIC4_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC4_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x5625180ull
+#define NIC4_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC4_UMR1_5_SPECIAL_BASE 0x5625E80ull
+#define NIC4_UMR1_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR1_5_SPECIAL_SECTION 0x1800
+#define mmNIC4_UMR1_6_UNSECURE_DOORBELL0_BASE 0x5626000ull
+#define NIC4_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC4_UMR1_6_UNSECURE_DOORBELL1_BASE 0x5626080ull
+#define NIC4_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC4_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x5626100ull
+#define NIC4_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC4_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x5626180ull
+#define NIC4_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC4_UMR1_6_SPECIAL_BASE 0x5626E80ull
+#define NIC4_UMR1_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR1_6_SPECIAL_SECTION 0x1800
+#define mmNIC4_UMR1_7_UNSECURE_DOORBELL0_BASE 0x5627000ull
+#define NIC4_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC4_UMR1_7_UNSECURE_DOORBELL1_BASE 0x5627080ull
+#define NIC4_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC4_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x5627100ull
+#define NIC4_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC4_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x5627180ull
+#define NIC4_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC4_UMR1_7_SPECIAL_BASE 0x5627E80ull
+#define NIC4_UMR1_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR1_7_SPECIAL_SECTION 0x1800
+#define mmNIC4_UMR1_8_UNSECURE_DOORBELL0_BASE 0x5628000ull
+#define NIC4_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC4_UMR1_8_UNSECURE_DOORBELL1_BASE 0x5628080ull
+#define NIC4_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC4_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x5628100ull
+#define NIC4_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC4_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x5628180ull
+#define NIC4_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC4_UMR1_8_SPECIAL_BASE 0x5628E80ull
+#define NIC4_UMR1_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR1_8_SPECIAL_SECTION 0x1800
+#define mmNIC4_UMR1_9_UNSECURE_DOORBELL0_BASE 0x5629000ull
+#define NIC4_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC4_UMR1_9_UNSECURE_DOORBELL1_BASE 0x5629080ull
+#define NIC4_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC4_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x5629100ull
+#define NIC4_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC4_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x5629180ull
+#define NIC4_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC4_UMR1_9_SPECIAL_BASE 0x5629E80ull
+#define NIC4_UMR1_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR1_9_SPECIAL_SECTION 0x1800
+#define mmNIC4_UMR1_10_UNSECURE_DOORBELL0_BASE 0x562A000ull
+#define NIC4_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC4_UMR1_10_UNSECURE_DOORBELL1_BASE 0x562A080ull
+#define NIC4_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC4_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x562A100ull
+#define NIC4_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC4_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x562A180ull
+#define NIC4_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC4_UMR1_10_SPECIAL_BASE 0x562AE80ull
+#define NIC4_UMR1_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR1_10_SPECIAL_SECTION 0x1800
+#define mmNIC4_UMR1_11_UNSECURE_DOORBELL0_BASE 0x562B000ull
+#define NIC4_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC4_UMR1_11_UNSECURE_DOORBELL1_BASE 0x562B080ull
+#define NIC4_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC4_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x562B100ull
+#define NIC4_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC4_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x562B180ull
+#define NIC4_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC4_UMR1_11_SPECIAL_BASE 0x562BE80ull
+#define NIC4_UMR1_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR1_11_SPECIAL_SECTION 0x1800
+#define mmNIC4_UMR1_12_UNSECURE_DOORBELL0_BASE 0x562C000ull
+#define NIC4_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC4_UMR1_12_UNSECURE_DOORBELL1_BASE 0x562C080ull
+#define NIC4_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC4_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x562C100ull
+#define NIC4_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC4_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x562C180ull
+#define NIC4_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC4_UMR1_12_SPECIAL_BASE 0x562CE80ull
+#define NIC4_UMR1_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR1_12_SPECIAL_SECTION 0x1800
+#define mmNIC4_UMR1_13_UNSECURE_DOORBELL0_BASE 0x562D000ull
+#define NIC4_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC4_UMR1_13_UNSECURE_DOORBELL1_BASE 0x562D080ull
+#define NIC4_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC4_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x562D100ull
+#define NIC4_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC4_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x562D180ull
+#define NIC4_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC4_UMR1_13_SPECIAL_BASE 0x562DE80ull
+#define NIC4_UMR1_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR1_13_SPECIAL_SECTION 0x1800
+#define mmNIC4_UMR1_14_UNSECURE_DOORBELL0_BASE 0x562E000ull
+#define NIC4_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC4_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC4_UMR1_14_UNSECURE_DOORBELL1_BASE 0x562E080ull
+#define NIC4_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC4_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC4_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x562E100ull
+#define NIC4_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC4_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC4_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x562E180ull
+#define NIC4_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC4_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC4_UMR1_14_SPECIAL_BASE 0x562EE80ull
+#define NIC4_UMR1_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_UMR1_14_SPECIAL_SECTION 0x1180
+#define mmNIC4_QM_DCCM1_BASE 0x5630000ull
+#define NIC4_QM_DCCM1_MAX_OFFSET 0x4000
+#define NIC4_QM_DCCM1_SECTION 0x8000
+#define mmNIC4_QM_ARC_AUX1_BASE 0x5638000ull
+#define NIC4_QM_ARC_AUX1_MAX_OFFSET 0x1000
+#define NIC4_QM_ARC_AUX1_SECTION 0xE800
+#define mmNIC4_QM_ARC_AUX1_SPECIAL_BASE 0x5638E80ull
+#define NIC4_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_QM_ARC_AUX1_SPECIAL_SECTION 0x1180
+#define mmNIC4_QM1_BASE 0x563A000ull
+#define NIC4_QM1_MAX_OFFSET 0x1000
+#define NIC4_QM1_SECTION 0x9000
+#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x563A900ull
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x563A908ull
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x563A910ull
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x563A918ull
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x563A920ull
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x563A928ull
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x563A930ull
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x563A938ull
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x563A940ull
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x563A948ull
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x563A950ull
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x563A958ull
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x563A960ull
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x563A968ull
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x563A970ull
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x563A978ull
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC4_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmNIC4_QM1_AXUSER_SECURED_BASE 0x563AB00ull
+#define NIC4_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC4_QM1_AXUSER_SECURED_SECTION 0x8000
+#define mmNIC4_QM1_AXUSER_NONSECURED_BASE 0x563AB80ull
+#define NIC4_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC4_QM1_AXUSER_NONSECURED_SECTION 0x8000
+#define mmNIC4_QM1_DBG_HBW_BASE 0x563AC00ull
+#define NIC4_QM1_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC4_QM1_DBG_HBW_SECTION 0x8000
+#define mmNIC4_QM1_DBG_LBW_BASE 0x563AC80ull
+#define NIC4_QM1_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC4_QM1_DBG_LBW_SECTION 0x1000
+#define mmNIC4_QM1_CGM_BASE 0x563AD80ull
+#define NIC4_QM1_CGM_MAX_OFFSET 0xC000
+#define NIC4_QM1_CGM_SECTION 0x1000
+#define mmNIC4_QM1_SPECIAL_BASE 0x563AE80ull
+#define NIC4_QM1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_QM1_SPECIAL_SECTION 0x4180
+#define mmNIC4_QPC1_BASE 0x563F000ull
+#define NIC4_QPC1_MAX_OFFSET 0x1000
+#define NIC4_QPC1_SECTION 0x7200
+#define mmNIC4_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x563F720ull
+#define NIC4_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x563F728ull
+#define NIC4_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x563F730ull
+#define NIC4_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x563F738ull
+#define NIC4_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x563F740ull
+#define NIC4_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x563F748ull
+#define NIC4_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x563F750ull
+#define NIC4_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x563F758ull
+#define NIC4_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x563F760ull
+#define NIC4_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x563F768ull
+#define NIC4_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x563F770ull
+#define NIC4_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x563F778ull
+#define NIC4_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x563F780ull
+#define NIC4_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x563F788ull
+#define NIC4_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x563F790ull
+#define NIC4_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x563F798ull
+#define NIC4_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x563F7A0ull
+#define NIC4_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x563F7A8ull
+#define NIC4_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x563F7B0ull
+#define NIC4_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x563F7B8ull
+#define NIC4_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x563F7C0ull
+#define NIC4_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x563F7C8ull
+#define NIC4_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x563F7D0ull
+#define NIC4_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x563F7D8ull
+#define NIC4_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x563F7E0ull
+#define NIC4_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x563F7E8ull
+#define NIC4_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x563F7F0ull
+#define NIC4_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x563F7F8ull
+#define NIC4_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x563F800ull
+#define NIC4_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x563F808ull
+#define NIC4_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x563F810ull
+#define NIC4_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC4_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x563F818ull
+#define NIC4_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC4_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define mmNIC4_QPC1_AXUSER_CONG_QUE_BASE 0x563FB80ull
+#define NIC4_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC4_QPC1_AXUSER_CONG_QUE_SECTION 0x6000
+#define mmNIC4_QPC1_AXUSER_RXWQE_BASE 0x563FBE0ull
+#define NIC4_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC4_QPC1_AXUSER_RXWQE_SECTION 0x6000
+#define mmNIC4_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x563FC40ull
+#define NIC4_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC4_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define mmNIC4_QPC1_AXUSER_DB_FIFO_BASE 0x563FCA0ull
+#define NIC4_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC4_QPC1_AXUSER_DB_FIFO_SECTION 0x6000
+#define mmNIC4_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x563FD00ull
+#define NIC4_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC4_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define mmNIC4_QPC1_AXUSER_ERR_FIFO_BASE 0x563FD60ull
+#define NIC4_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC4_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000
+#define mmNIC4_QPC1_AXUSER_QPC_RESP_BASE 0x563FDC0ull
+#define NIC4_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC4_QPC1_AXUSER_QPC_RESP_SECTION 0x6000
+#define mmNIC4_QPC1_AXUSER_QPC_REQ_BASE 0x563FE20ull
+#define NIC4_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC4_QPC1_AXUSER_QPC_REQ_SECTION 0x6000
+#define mmNIC4_QPC1_SPECIAL_BASE 0x563FE80ull
+#define NIC4_QPC1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_QPC1_SPECIAL_SECTION 0x8180
+#define mmNIC4_TMR_BASE 0x5648000ull
+#define NIC4_TMR_MAX_OFFSET 0x1000
+#define NIC4_TMR_SECTION 0xD600
+#define mmNIC4_TMR_AXUSER_TMR_FREE_LIST_BASE 0x5648D60ull
+#define NIC4_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000
+#define NIC4_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000
+#define mmNIC4_TMR_AXUSER_TMR_FIFO_BASE 0x5648DC0ull
+#define NIC4_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000
+#define NIC4_TMR_AXUSER_TMR_FIFO_SECTION 0x6000
+#define mmNIC4_TMR_AXUSER_TMR_FSM_BASE 0x5648E20ull
+#define NIC4_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000
+#define NIC4_TMR_AXUSER_TMR_FSM_SECTION 0x6000
+#define mmNIC4_TMR_SPECIAL_BASE 0x5648E80ull
+#define NIC4_TMR_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_TMR_SPECIAL_SECTION 0x1800
+#define mmNIC4_RXB_CORE_BASE 0x5649000ull
+#define NIC4_RXB_CORE_MAX_OFFSET 0x1000
+#define NIC4_RXB_CORE_SECTION 0x6100
+#define mmNIC4_RXB_CORE_SCT_AWUSER_BASE 0x5649610ull
+#define NIC4_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000
+#define NIC4_RXB_CORE_SCT_AWUSER_SECTION 0x8700
+#define mmNIC4_RXB_CORE_SPECIAL_BASE 0x5649E80ull
+#define NIC4_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_RXB_CORE_SPECIAL_SECTION 0x1800
+#define mmNIC4_RXE0_BASE 0x564A000ull
+#define NIC4_RXE0_MAX_OFFSET 0x1000
+#define NIC4_RXE0_SECTION 0x9000
+#define mmNIC4_RXE0_WQE_ARUSER_BASE 0x564A900ull
+#define NIC4_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC4_RXE0_WQE_ARUSER_SECTION 0x5800
+#define mmNIC4_RXE0_SPECIAL_BASE 0x564AE80ull
+#define NIC4_RXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_RXE0_SPECIAL_SECTION 0x1800
+#define mmNIC4_RXE1_BASE 0x564B000ull
+#define NIC4_RXE1_MAX_OFFSET 0x1000
+#define NIC4_RXE1_SECTION 0x9000
+#define mmNIC4_RXE1_WQE_ARUSER_BASE 0x564B900ull
+#define NIC4_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC4_RXE1_WQE_ARUSER_SECTION 0x5800
+#define mmNIC4_RXE1_SPECIAL_BASE 0x564BE80ull
+#define NIC4_RXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_RXE1_SPECIAL_SECTION 0x1800
+#define mmNIC4_RXE0_AXUSER_AXUSER_CQ0_BASE 0x564C000ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define mmNIC4_RXE0_AXUSER_AXUSER_CQ1_BASE 0x564C050ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define mmNIC4_RXE0_AXUSER_AXUSER_CQ2_BASE 0x564C0A0ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define mmNIC4_RXE0_AXUSER_AXUSER_CQ3_BASE 0x564C0F0ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define mmNIC4_RXE0_AXUSER_AXUSER_CQ4_BASE 0x564C140ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define mmNIC4_RXE0_AXUSER_AXUSER_CQ5_BASE 0x564C190ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define mmNIC4_RXE0_AXUSER_AXUSER_CQ6_BASE 0x564C1E0ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define mmNIC4_RXE0_AXUSER_AXUSER_CQ7_BASE 0x564C230ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define mmNIC4_RXE0_AXUSER_AXUSER_CQ8_BASE 0x564C280ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define mmNIC4_RXE0_AXUSER_AXUSER_CQ9_BASE 0x564C2D0ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define mmNIC4_RXE0_AXUSER_AXUSER_CQ10_BASE 0x564C320ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define mmNIC4_RXE0_AXUSER_AXUSER_CQ11_BASE 0x564C370ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define mmNIC4_RXE0_AXUSER_AXUSER_CQ12_BASE 0x564C3C0ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define mmNIC4_RXE0_AXUSER_AXUSER_CQ13_BASE 0x564C410ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define mmNIC4_RXE0_AXUSER_AXUSER_CQ14_BASE 0x564C460ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define mmNIC4_RXE0_AXUSER_AXUSER_CQ15_BASE 0x564C4B0ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define mmNIC4_RXE0_AXUSER_AXUSER_CQ16_BASE 0x564C500ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define mmNIC4_RXE0_AXUSER_AXUSER_CQ17_BASE 0x564C550ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define mmNIC4_RXE0_AXUSER_AXUSER_CQ18_BASE 0x564C5A0ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define mmNIC4_RXE0_AXUSER_AXUSER_CQ19_BASE 0x564C5F0ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define mmNIC4_RXE0_AXUSER_AXUSER_CQ20_BASE 0x564C640ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define mmNIC4_RXE0_AXUSER_AXUSER_CQ21_BASE 0x564C690ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define mmNIC4_RXE0_AXUSER_AXUSER_CQ22_BASE 0x564C6E0ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define mmNIC4_RXE0_AXUSER_AXUSER_CQ23_BASE 0x564C730ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define mmNIC4_RXE0_AXUSER_AXUSER_CQ24_BASE 0x564C780ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define mmNIC4_RXE0_AXUSER_AXUSER_CQ25_BASE 0x564C7D0ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define mmNIC4_RXE0_AXUSER_AXUSER_CQ26_BASE 0x564C820ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define mmNIC4_RXE0_AXUSER_AXUSER_CQ27_BASE 0x564C870ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define mmNIC4_RXE0_AXUSER_AXUSER_CQ28_BASE 0x564C8C0ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define mmNIC4_RXE0_AXUSER_AXUSER_CQ29_BASE 0x564C910ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define mmNIC4_RXE0_AXUSER_AXUSER_CQ30_BASE 0x564C960ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define mmNIC4_RXE0_AXUSER_AXUSER_CQ31_BASE 0x564C9B0ull
+#define NIC4_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC4_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define mmNIC4_RXE0_AXUSER_SPECIAL_BASE 0x564CE80ull
+#define NIC4_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_RXE0_AXUSER_SPECIAL_SECTION 0x1800
+#define mmNIC4_RXE1_AXUSER_AXUSER_CQ0_BASE 0x564D000ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define mmNIC4_RXE1_AXUSER_AXUSER_CQ1_BASE 0x564D050ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define mmNIC4_RXE1_AXUSER_AXUSER_CQ2_BASE 0x564D0A0ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define mmNIC4_RXE1_AXUSER_AXUSER_CQ3_BASE 0x564D0F0ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define mmNIC4_RXE1_AXUSER_AXUSER_CQ4_BASE 0x564D140ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define mmNIC4_RXE1_AXUSER_AXUSER_CQ5_BASE 0x564D190ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define mmNIC4_RXE1_AXUSER_AXUSER_CQ6_BASE 0x564D1E0ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define mmNIC4_RXE1_AXUSER_AXUSER_CQ7_BASE 0x564D230ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define mmNIC4_RXE1_AXUSER_AXUSER_CQ8_BASE 0x564D280ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define mmNIC4_RXE1_AXUSER_AXUSER_CQ9_BASE 0x564D2D0ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define mmNIC4_RXE1_AXUSER_AXUSER_CQ10_BASE 0x564D320ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define mmNIC4_RXE1_AXUSER_AXUSER_CQ11_BASE 0x564D370ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define mmNIC4_RXE1_AXUSER_AXUSER_CQ12_BASE 0x564D3C0ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define mmNIC4_RXE1_AXUSER_AXUSER_CQ13_BASE 0x564D410ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define mmNIC4_RXE1_AXUSER_AXUSER_CQ14_BASE 0x564D460ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define mmNIC4_RXE1_AXUSER_AXUSER_CQ15_BASE 0x564D4B0ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define mmNIC4_RXE1_AXUSER_AXUSER_CQ16_BASE 0x564D500ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define mmNIC4_RXE1_AXUSER_AXUSER_CQ17_BASE 0x564D550ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define mmNIC4_RXE1_AXUSER_AXUSER_CQ18_BASE 0x564D5A0ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define mmNIC4_RXE1_AXUSER_AXUSER_CQ19_BASE 0x564D5F0ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define mmNIC4_RXE1_AXUSER_AXUSER_CQ20_BASE 0x564D640ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define mmNIC4_RXE1_AXUSER_AXUSER_CQ21_BASE 0x564D690ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define mmNIC4_RXE1_AXUSER_AXUSER_CQ22_BASE 0x564D6E0ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define mmNIC4_RXE1_AXUSER_AXUSER_CQ23_BASE 0x564D730ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define mmNIC4_RXE1_AXUSER_AXUSER_CQ24_BASE 0x564D780ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define mmNIC4_RXE1_AXUSER_AXUSER_CQ25_BASE 0x564D7D0ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define mmNIC4_RXE1_AXUSER_AXUSER_CQ26_BASE 0x564D820ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define mmNIC4_RXE1_AXUSER_AXUSER_CQ27_BASE 0x564D870ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define mmNIC4_RXE1_AXUSER_AXUSER_CQ28_BASE 0x564D8C0ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define mmNIC4_RXE1_AXUSER_AXUSER_CQ29_BASE 0x564D910ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define mmNIC4_RXE1_AXUSER_AXUSER_CQ30_BASE 0x564D960ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define mmNIC4_RXE1_AXUSER_AXUSER_CQ31_BASE 0x564D9B0ull
+#define NIC4_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC4_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define mmNIC4_RXE1_AXUSER_SPECIAL_BASE 0x564DE80ull
+#define NIC4_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_RXE1_AXUSER_SPECIAL_SECTION 0x2180
+#define mmNIC4_TXS0_BASE 0x5650000ull
+#define NIC4_TXS0_MAX_OFFSET 0x1000
+#define NIC4_TXS0_SECTION 0xE800
+#define mmNIC4_TXS0_SPECIAL_BASE 0x5650E80ull
+#define NIC4_TXS0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_TXS0_SPECIAL_SECTION 0x1800
+#define mmNIC4_TXS1_BASE 0x5651000ull
+#define NIC4_TXS1_MAX_OFFSET 0x1000
+#define NIC4_TXS1_SECTION 0xE800
+#define mmNIC4_TXS1_SPECIAL_BASE 0x5651E80ull
+#define NIC4_TXS1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_TXS1_SPECIAL_SECTION 0x1800
+#define mmNIC4_TXE0_BASE 0x5652000ull
+#define NIC4_TXE0_MAX_OFFSET 0x1000
+#define NIC4_TXE0_SECTION 0xE800
+#define mmNIC4_TXE0_SPECIAL_BASE 0x5652E80ull
+#define NIC4_TXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_TXE0_SPECIAL_SECTION 0x1800
+#define mmNIC4_TXE1_BASE 0x5653000ull
+#define NIC4_TXE1_MAX_OFFSET 0x1000
+#define NIC4_TXE1_SECTION 0xE800
+#define mmNIC4_TXE1_SPECIAL_BASE 0x5653E80ull
+#define NIC4_TXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_TXE1_SPECIAL_SECTION 0x1800
+#define mmNIC4_TXB_BASE 0x5654000ull
+#define NIC4_TXB_MAX_OFFSET 0x1000
+#define NIC4_TXB_SECTION 0xE800
+#define mmNIC4_TXB_SPECIAL_BASE 0x5654E80ull
+#define NIC4_TXB_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_TXB_SPECIAL_SECTION 0x1800
+#define mmNIC4_MSTR_IF_RR_SHRD_HBW_BASE 0x5655000ull
+#define NIC4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define NIC4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmNIC4_MSTR_IF_RR_PRVT_HBW_BASE 0x5655200ull
+#define NIC4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define NIC4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmNIC4_MSTR_IF_RR_SHRD_LBW_BASE 0x5655400ull
+#define NIC4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define NIC4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmNIC4_MSTR_IF_RR_PRVT_LBW_BASE 0x5655600ull
+#define NIC4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define NIC4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmNIC4_MSTR_IF_E2E_CRDT_BASE 0x5655800ull
+#define NIC4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define NIC4_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmNIC4_MSTR_IF_AXUSER_BASE 0x5655A80ull
+#define NIC4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define NIC4_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmNIC4_MSTR_IF_DBG_HBW_BASE 0x5655B00ull
+#define NIC4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC4_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmNIC4_MSTR_IF_DBG_LBW_BASE 0x5655B80ull
+#define NIC4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC4_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmNIC4_MSTR_IF_CORE_HBW_BASE 0x5655C00ull
+#define NIC4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define NIC4_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmNIC4_MSTR_IF_CORE_LBW_BASE 0x5655D80ull
+#define NIC4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define NIC4_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmNIC4_MSTR_IF_SPECIAL_BASE 0x5655E80ull
+#define NIC4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmNIC4_TX_AXUSER_BASE 0x5656000ull
+#define NIC4_TX_AXUSER_MAX_OFFSET 0x5000
+#define NIC4_TX_AXUSER_SECTION 0x2000
+#define mmNIC4_SERDES0_BASE 0x5658000ull
+#define NIC4_SERDES0_MAX_OFFSET 0x3E40
+#define NIC4_SERDES0_SECTION 0x4000
+#define mmNIC4_SERDES1_BASE 0x565C000ull
+#define NIC4_SERDES1_MAX_OFFSET 0x3E40
+#define NIC4_SERDES1_SECTION 0x4000
+#define mmNIC4_PHY_BASE 0x5660000ull
+#define NIC4_PHY_MAX_OFFSET 0x1000
+#define NIC4_PHY_SECTION 0xE800
+#define mmNIC4_PHY_SPECIAL_BASE 0x5660E80ull
+#define NIC4_PHY_SPECIAL_MAX_OFFSET 0x1800
+#define NIC4_PHY_SPECIAL_SECTION 0x7180
+#define mmPRT4_MAC_AUX_BASE 0x5668000ull
+#define PRT4_MAC_AUX_MAX_OFFSET 0x1000
+#define PRT4_MAC_AUX_SECTION 0xE800
+#define mmPRT4_MAC_AUX_SPECIAL_BASE 0x5668E80ull
+#define PRT4_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define PRT4_MAC_AUX_SPECIAL_SECTION 0x1800
+#define mmPRT4_MAC_CORE_BASE 0x5669000ull
+#define PRT4_MAC_CORE_MAX_OFFSET 0x1000
+#define PRT4_MAC_CORE_SECTION 0xE800
+#define mmPRT4_MAC_CORE_SPECIAL_BASE 0x5669E80ull
+#define PRT4_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define PRT4_MAC_CORE_SPECIAL_SECTION 0x1800
+#define mmNIC4_MAC_RS_FEC_BASE 0x566A000ull
+#define NIC4_MAC_RS_FEC_MAX_OFFSET 0x2DC0
+#define NIC4_MAC_RS_FEC_SECTION 0x1000
+#define mmNIC4_MAC_GLOB_STAT_CONTROL_REG_BASE 0x566B000ull
+#define NIC4_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000
+#define NIC4_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000
+#define mmNIC4_MAC_GLOB_STAT_RX0_BASE 0x566B100ull
+#define NIC4_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00
+#define NIC4_MAC_GLOB_STAT_RX0_SECTION 0x8C00
+#define mmNIC4_MAC_GLOB_STAT_RX1_BASE 0x566B18Cull
+#define NIC4_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00
+#define NIC4_MAC_GLOB_STAT_RX1_SECTION 0x8C00
+#define mmNIC4_MAC_GLOB_STAT_RX2_BASE 0x566B218ull
+#define NIC4_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00
+#define NIC4_MAC_GLOB_STAT_RX2_SECTION 0x8C00
+#define mmNIC4_MAC_GLOB_STAT_RX3_BASE 0x566B2A4ull
+#define NIC4_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00
+#define NIC4_MAC_GLOB_STAT_RX3_SECTION 0x8C00
+#define mmNIC4_MAC_GLOB_STAT_TX0_BASE 0x566B330ull
+#define NIC4_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800
+#define NIC4_MAC_GLOB_STAT_TX0_SECTION 0x6800
+#define mmNIC4_MAC_GLOB_STAT_TX1_BASE 0x566B398ull
+#define NIC4_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800
+#define NIC4_MAC_GLOB_STAT_TX1_SECTION 0x6800
+#define mmNIC4_MAC_GLOB_STAT_TX2_BASE 0x566B400ull
+#define NIC4_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800
+#define NIC4_MAC_GLOB_STAT_TX2_SECTION 0x6800
+#define mmNIC4_MAC_GLOB_STAT_TX3_BASE 0x566B468ull
+#define NIC4_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800
+#define NIC4_MAC_GLOB_STAT_TX3_SECTION 0x3980
+#define mmNIC4_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x566B800ull
+#define NIC4_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0
+#define NIC4_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000
+#define mmNIC4_MAC_CH0_MAC_PCS_BASE 0x566C000ull
+#define NIC4_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC4_MAC_CH0_MAC_PCS_SECTION 0x4000
+#define mmNIC4_MAC_CH0_MAC_128_BASE 0x566C400ull
+#define NIC4_MAC_CH0_MAC_128_MAX_OFFSET 0xA400
+#define NIC4_MAC_CH0_MAC_128_SECTION 0x4000
+#define mmNIC4_MAC_CH0_MAC_AN_BASE 0x566C800ull
+#define NIC4_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400
+#define NIC4_MAC_CH0_MAC_AN_SECTION 0x8000
+#define mmNIC4_MAC_CH1_MAC_PCS_BASE 0x566D000ull
+#define NIC4_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC4_MAC_CH1_MAC_PCS_SECTION 0x4000
+#define mmNIC4_MAC_CH1_MAC_128_BASE 0x566D400ull
+#define NIC4_MAC_CH1_MAC_128_MAX_OFFSET 0xA400
+#define NIC4_MAC_CH1_MAC_128_SECTION 0x4000
+#define mmNIC4_MAC_CH1_MAC_AN_BASE 0x566D800ull
+#define NIC4_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400
+#define NIC4_MAC_CH1_MAC_AN_SECTION 0x8000
+#define mmNIC4_MAC_CH2_MAC_PCS_BASE 0x566E000ull
+#define NIC4_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC4_MAC_CH2_MAC_PCS_SECTION 0x4000
+#define mmNIC4_MAC_CH2_MAC_128_BASE 0x566E400ull
+#define NIC4_MAC_CH2_MAC_128_MAX_OFFSET 0xA400
+#define NIC4_MAC_CH2_MAC_128_SECTION 0x4000
+#define mmNIC4_MAC_CH2_MAC_AN_BASE 0x566E800ull
+#define NIC4_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400
+#define NIC4_MAC_CH2_MAC_AN_SECTION 0x8000
+#define mmNIC4_MAC_CH3_MAC_PCS_BASE 0x566F000ull
+#define NIC4_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC4_MAC_CH3_MAC_PCS_SECTION 0x4000
+#define mmNIC4_MAC_CH3_MAC_128_BASE 0x566F400ull
+#define NIC4_MAC_CH3_MAC_128_MAX_OFFSET 0xA400
+#define NIC4_MAC_CH3_MAC_128_SECTION 0x4000
+#define mmNIC4_MAC_CH3_MAC_AN_BASE 0x566F800ull
+#define NIC4_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400
+#define NIC4_MAC_CH3_MAC_AN_SECTION 0x10800
+#define mmNIC5_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5680000ull
+#define NIC5_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC5_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5680080ull
+#define NIC5_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC5_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5680100ull
+#define NIC5_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC5_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5680180ull
+#define NIC5_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC5_UMR0_0_SPECIAL_BASE 0x5680E80ull
+#define NIC5_UMR0_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR0_0_SPECIAL_SECTION 0x1800
+#define mmNIC5_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5681000ull
+#define NIC5_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC5_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5681080ull
+#define NIC5_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC5_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5681100ull
+#define NIC5_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC5_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5681180ull
+#define NIC5_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC5_UMR0_1_SPECIAL_BASE 0x5681E80ull
+#define NIC5_UMR0_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR0_1_SPECIAL_SECTION 0x1800
+#define mmNIC5_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5682000ull
+#define NIC5_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC5_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5682080ull
+#define NIC5_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC5_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5682100ull
+#define NIC5_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC5_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5682180ull
+#define NIC5_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC5_UMR0_2_SPECIAL_BASE 0x5682E80ull
+#define NIC5_UMR0_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR0_2_SPECIAL_SECTION 0x1800
+#define mmNIC5_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5683000ull
+#define NIC5_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC5_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5683080ull
+#define NIC5_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC5_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5683100ull
+#define NIC5_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC5_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5683180ull
+#define NIC5_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC5_UMR0_3_SPECIAL_BASE 0x5683E80ull
+#define NIC5_UMR0_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR0_3_SPECIAL_SECTION 0x1800
+#define mmNIC5_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5684000ull
+#define NIC5_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC5_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5684080ull
+#define NIC5_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC5_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5684100ull
+#define NIC5_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC5_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5684180ull
+#define NIC5_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC5_UMR0_4_SPECIAL_BASE 0x5684E80ull
+#define NIC5_UMR0_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR0_4_SPECIAL_SECTION 0x1800
+#define mmNIC5_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5685000ull
+#define NIC5_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC5_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5685080ull
+#define NIC5_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC5_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5685100ull
+#define NIC5_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC5_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5685180ull
+#define NIC5_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC5_UMR0_5_SPECIAL_BASE 0x5685E80ull
+#define NIC5_UMR0_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR0_5_SPECIAL_SECTION 0x1800
+#define mmNIC5_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5686000ull
+#define NIC5_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC5_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5686080ull
+#define NIC5_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC5_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5686100ull
+#define NIC5_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC5_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5686180ull
+#define NIC5_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC5_UMR0_6_SPECIAL_BASE 0x5686E80ull
+#define NIC5_UMR0_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR0_6_SPECIAL_SECTION 0x1800
+#define mmNIC5_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5687000ull
+#define NIC5_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC5_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5687080ull
+#define NIC5_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC5_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5687100ull
+#define NIC5_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC5_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5687180ull
+#define NIC5_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC5_UMR0_7_SPECIAL_BASE 0x5687E80ull
+#define NIC5_UMR0_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR0_7_SPECIAL_SECTION 0x1800
+#define mmNIC5_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5688000ull
+#define NIC5_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC5_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5688080ull
+#define NIC5_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC5_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5688100ull
+#define NIC5_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC5_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5688180ull
+#define NIC5_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC5_UMR0_8_SPECIAL_BASE 0x5688E80ull
+#define NIC5_UMR0_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR0_8_SPECIAL_SECTION 0x1800
+#define mmNIC5_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5689000ull
+#define NIC5_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC5_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5689080ull
+#define NIC5_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC5_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5689100ull
+#define NIC5_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC5_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5689180ull
+#define NIC5_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC5_UMR0_9_SPECIAL_BASE 0x5689E80ull
+#define NIC5_UMR0_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR0_9_SPECIAL_SECTION 0x1800
+#define mmNIC5_UMR0_10_UNSECURE_DOORBELL0_BASE 0x568A000ull
+#define NIC5_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC5_UMR0_10_UNSECURE_DOORBELL1_BASE 0x568A080ull
+#define NIC5_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC5_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x568A100ull
+#define NIC5_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC5_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x568A180ull
+#define NIC5_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC5_UMR0_10_SPECIAL_BASE 0x568AE80ull
+#define NIC5_UMR0_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR0_10_SPECIAL_SECTION 0x1800
+#define mmNIC5_UMR0_11_UNSECURE_DOORBELL0_BASE 0x568B000ull
+#define NIC5_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC5_UMR0_11_UNSECURE_DOORBELL1_BASE 0x568B080ull
+#define NIC5_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC5_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x568B100ull
+#define NIC5_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC5_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x568B180ull
+#define NIC5_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC5_UMR0_11_SPECIAL_BASE 0x568BE80ull
+#define NIC5_UMR0_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR0_11_SPECIAL_SECTION 0x1800
+#define mmNIC5_UMR0_12_UNSECURE_DOORBELL0_BASE 0x568C000ull
+#define NIC5_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC5_UMR0_12_UNSECURE_DOORBELL1_BASE 0x568C080ull
+#define NIC5_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC5_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x568C100ull
+#define NIC5_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC5_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x568C180ull
+#define NIC5_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC5_UMR0_12_SPECIAL_BASE 0x568CE80ull
+#define NIC5_UMR0_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR0_12_SPECIAL_SECTION 0x1800
+#define mmNIC5_UMR0_13_UNSECURE_DOORBELL0_BASE 0x568D000ull
+#define NIC5_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC5_UMR0_13_UNSECURE_DOORBELL1_BASE 0x568D080ull
+#define NIC5_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC5_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x568D100ull
+#define NIC5_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC5_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x568D180ull
+#define NIC5_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC5_UMR0_13_SPECIAL_BASE 0x568DE80ull
+#define NIC5_UMR0_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR0_13_SPECIAL_SECTION 0x1800
+#define mmNIC5_UMR0_14_UNSECURE_DOORBELL0_BASE 0x568E000ull
+#define NIC5_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC5_UMR0_14_UNSECURE_DOORBELL1_BASE 0x568E080ull
+#define NIC5_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC5_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x568E100ull
+#define NIC5_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC5_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x568E180ull
+#define NIC5_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC5_UMR0_14_SPECIAL_BASE 0x568EE80ull
+#define NIC5_UMR0_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR0_14_SPECIAL_SECTION 0x1180
+#define mmNIC5_QM_DCCM0_BASE 0x5690000ull
+#define NIC5_QM_DCCM0_MAX_OFFSET 0x4000
+#define NIC5_QM_DCCM0_SECTION 0x8000
+#define mmNIC5_QM_ARC_AUX0_BASE 0x5698000ull
+#define NIC5_QM_ARC_AUX0_MAX_OFFSET 0x1000
+#define NIC5_QM_ARC_AUX0_SECTION 0xE800
+#define mmNIC5_QM_ARC_AUX0_SPECIAL_BASE 0x5698E80ull
+#define NIC5_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_QM_ARC_AUX0_SPECIAL_SECTION 0x1180
+#define mmNIC5_QM0_BASE 0x569A000ull
+#define NIC5_QM0_MAX_OFFSET 0x1000
+#define NIC5_QM0_SECTION 0x9000
+#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x569A900ull
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x569A908ull
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x569A910ull
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x569A918ull
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x569A920ull
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x569A928ull
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x569A930ull
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x569A938ull
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x569A940ull
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x569A948ull
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x569A950ull
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x569A958ull
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x569A960ull
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x569A968ull
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x569A970ull
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x569A978ull
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC5_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmNIC5_QM0_AXUSER_SECURED_BASE 0x569AB00ull
+#define NIC5_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC5_QM0_AXUSER_SECURED_SECTION 0x8000
+#define mmNIC5_QM0_AXUSER_NONSECURED_BASE 0x569AB80ull
+#define NIC5_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC5_QM0_AXUSER_NONSECURED_SECTION 0x8000
+#define mmNIC5_QM0_DBG_HBW_BASE 0x569AC00ull
+#define NIC5_QM0_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC5_QM0_DBG_HBW_SECTION 0x8000
+#define mmNIC5_QM0_DBG_LBW_BASE 0x569AC80ull
+#define NIC5_QM0_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC5_QM0_DBG_LBW_SECTION 0x1000
+#define mmNIC5_QM0_CGM_BASE 0x569AD80ull
+#define NIC5_QM0_CGM_MAX_OFFSET 0xC000
+#define NIC5_QM0_CGM_SECTION 0x1000
+#define mmNIC5_QM0_SPECIAL_BASE 0x569AE80ull
+#define NIC5_QM0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_QM0_SPECIAL_SECTION 0x4180
+#define mmNIC5_QPC0_BASE 0x569F000ull
+#define NIC5_QPC0_MAX_OFFSET 0x1000
+#define NIC5_QPC0_SECTION 0x7200
+#define mmNIC5_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x569F720ull
+#define NIC5_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x569F728ull
+#define NIC5_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x569F730ull
+#define NIC5_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x569F738ull
+#define NIC5_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x569F740ull
+#define NIC5_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x569F748ull
+#define NIC5_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x569F750ull
+#define NIC5_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x569F758ull
+#define NIC5_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x569F760ull
+#define NIC5_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x569F768ull
+#define NIC5_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x569F770ull
+#define NIC5_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x569F778ull
+#define NIC5_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x569F780ull
+#define NIC5_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x569F788ull
+#define NIC5_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x569F790ull
+#define NIC5_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x569F798ull
+#define NIC5_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x569F7A0ull
+#define NIC5_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x569F7A8ull
+#define NIC5_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x569F7B0ull
+#define NIC5_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x569F7B8ull
+#define NIC5_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x569F7C0ull
+#define NIC5_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x569F7C8ull
+#define NIC5_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x569F7D0ull
+#define NIC5_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x569F7D8ull
+#define NIC5_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x569F7E0ull
+#define NIC5_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x569F7E8ull
+#define NIC5_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x569F7F0ull
+#define NIC5_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x569F7F8ull
+#define NIC5_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x569F800ull
+#define NIC5_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x569F808ull
+#define NIC5_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x569F810ull
+#define NIC5_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x569F818ull
+#define NIC5_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define mmNIC5_QPC0_AXUSER_CONG_QUE_BASE 0x569FB80ull
+#define NIC5_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC5_QPC0_AXUSER_CONG_QUE_SECTION 0x6000
+#define mmNIC5_QPC0_AXUSER_RXWQE_BASE 0x569FBE0ull
+#define NIC5_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC5_QPC0_AXUSER_RXWQE_SECTION 0x6000
+#define mmNIC5_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x569FC40ull
+#define NIC5_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC5_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define mmNIC5_QPC0_AXUSER_DB_FIFO_BASE 0x569FCA0ull
+#define NIC5_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC5_QPC0_AXUSER_DB_FIFO_SECTION 0x6000
+#define mmNIC5_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x569FD00ull
+#define NIC5_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC5_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define mmNIC5_QPC0_AXUSER_ERR_FIFO_BASE 0x569FD60ull
+#define NIC5_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC5_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000
+#define mmNIC5_QPC0_AXUSER_QPC_RESP_BASE 0x569FDC0ull
+#define NIC5_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC5_QPC0_AXUSER_QPC_RESP_SECTION 0x6000
+#define mmNIC5_QPC0_AXUSER_QPC_REQ_BASE 0x569FE20ull
+#define NIC5_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC5_QPC0_AXUSER_QPC_REQ_SECTION 0x6000
+#define mmNIC5_QPC0_SPECIAL_BASE 0x569FE80ull
+#define NIC5_QPC0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_QPC0_SPECIAL_SECTION 0x1800
+#define mmNIC5_UMR1_0_UNSECURE_DOORBELL0_BASE 0x56A0000ull
+#define NIC5_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC5_UMR1_0_UNSECURE_DOORBELL1_BASE 0x56A0080ull
+#define NIC5_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC5_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x56A0100ull
+#define NIC5_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC5_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x56A0180ull
+#define NIC5_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC5_UMR1_0_SPECIAL_BASE 0x56A0E80ull
+#define NIC5_UMR1_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR1_0_SPECIAL_SECTION 0x1800
+#define mmNIC5_UMR1_1_UNSECURE_DOORBELL0_BASE 0x56A1000ull
+#define NIC5_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC5_UMR1_1_UNSECURE_DOORBELL1_BASE 0x56A1080ull
+#define NIC5_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC5_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x56A1100ull
+#define NIC5_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC5_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x56A1180ull
+#define NIC5_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC5_UMR1_1_SPECIAL_BASE 0x56A1E80ull
+#define NIC5_UMR1_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR1_1_SPECIAL_SECTION 0x1800
+#define mmNIC5_UMR1_2_UNSECURE_DOORBELL0_BASE 0x56A2000ull
+#define NIC5_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC5_UMR1_2_UNSECURE_DOORBELL1_BASE 0x56A2080ull
+#define NIC5_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC5_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x56A2100ull
+#define NIC5_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC5_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x56A2180ull
+#define NIC5_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC5_UMR1_2_SPECIAL_BASE 0x56A2E80ull
+#define NIC5_UMR1_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR1_2_SPECIAL_SECTION 0x1800
+#define mmNIC5_UMR1_3_UNSECURE_DOORBELL0_BASE 0x56A3000ull
+#define NIC5_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC5_UMR1_3_UNSECURE_DOORBELL1_BASE 0x56A3080ull
+#define NIC5_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC5_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x56A3100ull
+#define NIC5_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC5_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x56A3180ull
+#define NIC5_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC5_UMR1_3_SPECIAL_BASE 0x56A3E80ull
+#define NIC5_UMR1_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR1_3_SPECIAL_SECTION 0x1800
+#define mmNIC5_UMR1_4_UNSECURE_DOORBELL0_BASE 0x56A4000ull
+#define NIC5_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC5_UMR1_4_UNSECURE_DOORBELL1_BASE 0x56A4080ull
+#define NIC5_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC5_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x56A4100ull
+#define NIC5_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC5_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x56A4180ull
+#define NIC5_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC5_UMR1_4_SPECIAL_BASE 0x56A4E80ull
+#define NIC5_UMR1_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR1_4_SPECIAL_SECTION 0x1800
+#define mmNIC5_UMR1_5_UNSECURE_DOORBELL0_BASE 0x56A5000ull
+#define NIC5_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC5_UMR1_5_UNSECURE_DOORBELL1_BASE 0x56A5080ull
+#define NIC5_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC5_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x56A5100ull
+#define NIC5_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC5_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x56A5180ull
+#define NIC5_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC5_UMR1_5_SPECIAL_BASE 0x56A5E80ull
+#define NIC5_UMR1_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR1_5_SPECIAL_SECTION 0x1800
+#define mmNIC5_UMR1_6_UNSECURE_DOORBELL0_BASE 0x56A6000ull
+#define NIC5_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC5_UMR1_6_UNSECURE_DOORBELL1_BASE 0x56A6080ull
+#define NIC5_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC5_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x56A6100ull
+#define NIC5_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC5_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x56A6180ull
+#define NIC5_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC5_UMR1_6_SPECIAL_BASE 0x56A6E80ull
+#define NIC5_UMR1_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR1_6_SPECIAL_SECTION 0x1800
+#define mmNIC5_UMR1_7_UNSECURE_DOORBELL0_BASE 0x56A7000ull
+#define NIC5_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC5_UMR1_7_UNSECURE_DOORBELL1_BASE 0x56A7080ull
+#define NIC5_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC5_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x56A7100ull
+#define NIC5_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC5_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x56A7180ull
+#define NIC5_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC5_UMR1_7_SPECIAL_BASE 0x56A7E80ull
+#define NIC5_UMR1_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR1_7_SPECIAL_SECTION 0x1800
+#define mmNIC5_UMR1_8_UNSECURE_DOORBELL0_BASE 0x56A8000ull
+#define NIC5_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC5_UMR1_8_UNSECURE_DOORBELL1_BASE 0x56A8080ull
+#define NIC5_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC5_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x56A8100ull
+#define NIC5_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC5_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x56A8180ull
+#define NIC5_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC5_UMR1_8_SPECIAL_BASE 0x56A8E80ull
+#define NIC5_UMR1_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR1_8_SPECIAL_SECTION 0x1800
+#define mmNIC5_UMR1_9_UNSECURE_DOORBELL0_BASE 0x56A9000ull
+#define NIC5_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC5_UMR1_9_UNSECURE_DOORBELL1_BASE 0x56A9080ull
+#define NIC5_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC5_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x56A9100ull
+#define NIC5_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC5_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x56A9180ull
+#define NIC5_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC5_UMR1_9_SPECIAL_BASE 0x56A9E80ull
+#define NIC5_UMR1_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR1_9_SPECIAL_SECTION 0x1800
+#define mmNIC5_UMR1_10_UNSECURE_DOORBELL0_BASE 0x56AA000ull
+#define NIC5_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC5_UMR1_10_UNSECURE_DOORBELL1_BASE 0x56AA080ull
+#define NIC5_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC5_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x56AA100ull
+#define NIC5_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC5_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x56AA180ull
+#define NIC5_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC5_UMR1_10_SPECIAL_BASE 0x56AAE80ull
+#define NIC5_UMR1_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR1_10_SPECIAL_SECTION 0x1800
+#define mmNIC5_UMR1_11_UNSECURE_DOORBELL0_BASE 0x56AB000ull
+#define NIC5_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC5_UMR1_11_UNSECURE_DOORBELL1_BASE 0x56AB080ull
+#define NIC5_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC5_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x56AB100ull
+#define NIC5_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC5_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x56AB180ull
+#define NIC5_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC5_UMR1_11_SPECIAL_BASE 0x56ABE80ull
+#define NIC5_UMR1_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR1_11_SPECIAL_SECTION 0x1800
+#define mmNIC5_UMR1_12_UNSECURE_DOORBELL0_BASE 0x56AC000ull
+#define NIC5_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC5_UMR1_12_UNSECURE_DOORBELL1_BASE 0x56AC080ull
+#define NIC5_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC5_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x56AC100ull
+#define NIC5_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC5_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x56AC180ull
+#define NIC5_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC5_UMR1_12_SPECIAL_BASE 0x56ACE80ull
+#define NIC5_UMR1_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR1_12_SPECIAL_SECTION 0x1800
+#define mmNIC5_UMR1_13_UNSECURE_DOORBELL0_BASE 0x56AD000ull
+#define NIC5_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC5_UMR1_13_UNSECURE_DOORBELL1_BASE 0x56AD080ull
+#define NIC5_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC5_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x56AD100ull
+#define NIC5_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC5_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x56AD180ull
+#define NIC5_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC5_UMR1_13_SPECIAL_BASE 0x56ADE80ull
+#define NIC5_UMR1_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR1_13_SPECIAL_SECTION 0x1800
+#define mmNIC5_UMR1_14_UNSECURE_DOORBELL0_BASE 0x56AE000ull
+#define NIC5_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC5_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC5_UMR1_14_UNSECURE_DOORBELL1_BASE 0x56AE080ull
+#define NIC5_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC5_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC5_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x56AE100ull
+#define NIC5_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC5_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC5_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x56AE180ull
+#define NIC5_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC5_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC5_UMR1_14_SPECIAL_BASE 0x56AEE80ull
+#define NIC5_UMR1_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_UMR1_14_SPECIAL_SECTION 0x1180
+#define mmNIC5_QM_DCCM1_BASE 0x56B0000ull
+#define NIC5_QM_DCCM1_MAX_OFFSET 0x4000
+#define NIC5_QM_DCCM1_SECTION 0x8000
+#define mmNIC5_QM_ARC_AUX1_BASE 0x56B8000ull
+#define NIC5_QM_ARC_AUX1_MAX_OFFSET 0x1000
+#define NIC5_QM_ARC_AUX1_SECTION 0xE800
+#define mmNIC5_QM_ARC_AUX1_SPECIAL_BASE 0x56B8E80ull
+#define NIC5_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_QM_ARC_AUX1_SPECIAL_SECTION 0x1180
+#define mmNIC5_QM1_BASE 0x56BA000ull
+#define NIC5_QM1_MAX_OFFSET 0x1000
+#define NIC5_QM1_SECTION 0x9000
+#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x56BA900ull
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x56BA908ull
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x56BA910ull
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x56BA918ull
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x56BA920ull
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x56BA928ull
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x56BA930ull
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x56BA938ull
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x56BA940ull
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x56BA948ull
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x56BA950ull
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x56BA958ull
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x56BA960ull
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x56BA968ull
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x56BA970ull
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x56BA978ull
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC5_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmNIC5_QM1_AXUSER_SECURED_BASE 0x56BAB00ull
+#define NIC5_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC5_QM1_AXUSER_SECURED_SECTION 0x8000
+#define mmNIC5_QM1_AXUSER_NONSECURED_BASE 0x56BAB80ull
+#define NIC5_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC5_QM1_AXUSER_NONSECURED_SECTION 0x8000
+#define mmNIC5_QM1_DBG_HBW_BASE 0x56BAC00ull
+#define NIC5_QM1_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC5_QM1_DBG_HBW_SECTION 0x8000
+#define mmNIC5_QM1_DBG_LBW_BASE 0x56BAC80ull
+#define NIC5_QM1_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC5_QM1_DBG_LBW_SECTION 0x1000
+#define mmNIC5_QM1_CGM_BASE 0x56BAD80ull
+#define NIC5_QM1_CGM_MAX_OFFSET 0xC000
+#define NIC5_QM1_CGM_SECTION 0x1000
+#define mmNIC5_QM1_SPECIAL_BASE 0x56BAE80ull
+#define NIC5_QM1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_QM1_SPECIAL_SECTION 0x4180
+#define mmNIC5_QPC1_BASE 0x56BF000ull
+#define NIC5_QPC1_MAX_OFFSET 0x1000
+#define NIC5_QPC1_SECTION 0x7200
+#define mmNIC5_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x56BF720ull
+#define NIC5_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x56BF728ull
+#define NIC5_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x56BF730ull
+#define NIC5_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x56BF738ull
+#define NIC5_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x56BF740ull
+#define NIC5_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x56BF748ull
+#define NIC5_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x56BF750ull
+#define NIC5_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x56BF758ull
+#define NIC5_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x56BF760ull
+#define NIC5_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x56BF768ull
+#define NIC5_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x56BF770ull
+#define NIC5_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x56BF778ull
+#define NIC5_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x56BF780ull
+#define NIC5_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x56BF788ull
+#define NIC5_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x56BF790ull
+#define NIC5_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x56BF798ull
+#define NIC5_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x56BF7A0ull
+#define NIC5_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x56BF7A8ull
+#define NIC5_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x56BF7B0ull
+#define NIC5_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x56BF7B8ull
+#define NIC5_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x56BF7C0ull
+#define NIC5_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x56BF7C8ull
+#define NIC5_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x56BF7D0ull
+#define NIC5_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x56BF7D8ull
+#define NIC5_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x56BF7E0ull
+#define NIC5_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x56BF7E8ull
+#define NIC5_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x56BF7F0ull
+#define NIC5_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x56BF7F8ull
+#define NIC5_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x56BF800ull
+#define NIC5_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x56BF808ull
+#define NIC5_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x56BF810ull
+#define NIC5_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC5_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x56BF818ull
+#define NIC5_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC5_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define mmNIC5_QPC1_AXUSER_CONG_QUE_BASE 0x56BFB80ull
+#define NIC5_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC5_QPC1_AXUSER_CONG_QUE_SECTION 0x6000
+#define mmNIC5_QPC1_AXUSER_RXWQE_BASE 0x56BFBE0ull
+#define NIC5_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC5_QPC1_AXUSER_RXWQE_SECTION 0x6000
+#define mmNIC5_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x56BFC40ull
+#define NIC5_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC5_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define mmNIC5_QPC1_AXUSER_DB_FIFO_BASE 0x56BFCA0ull
+#define NIC5_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC5_QPC1_AXUSER_DB_FIFO_SECTION 0x6000
+#define mmNIC5_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x56BFD00ull
+#define NIC5_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC5_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define mmNIC5_QPC1_AXUSER_ERR_FIFO_BASE 0x56BFD60ull
+#define NIC5_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC5_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000
+#define mmNIC5_QPC1_AXUSER_QPC_RESP_BASE 0x56BFDC0ull
+#define NIC5_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC5_QPC1_AXUSER_QPC_RESP_SECTION 0x6000
+#define mmNIC5_QPC1_AXUSER_QPC_REQ_BASE 0x56BFE20ull
+#define NIC5_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC5_QPC1_AXUSER_QPC_REQ_SECTION 0x6000
+#define mmNIC5_QPC1_SPECIAL_BASE 0x56BFE80ull
+#define NIC5_QPC1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_QPC1_SPECIAL_SECTION 0x8180
+#define mmNIC5_TMR_BASE 0x56C8000ull
+#define NIC5_TMR_MAX_OFFSET 0x1000
+#define NIC5_TMR_SECTION 0xD600
+#define mmNIC5_TMR_AXUSER_TMR_FREE_LIST_BASE 0x56C8D60ull
+#define NIC5_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000
+#define NIC5_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000
+#define mmNIC5_TMR_AXUSER_TMR_FIFO_BASE 0x56C8DC0ull
+#define NIC5_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000
+#define NIC5_TMR_AXUSER_TMR_FIFO_SECTION 0x6000
+#define mmNIC5_TMR_AXUSER_TMR_FSM_BASE 0x56C8E20ull
+#define NIC5_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000
+#define NIC5_TMR_AXUSER_TMR_FSM_SECTION 0x6000
+#define mmNIC5_TMR_SPECIAL_BASE 0x56C8E80ull
+#define NIC5_TMR_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_TMR_SPECIAL_SECTION 0x1800
+#define mmNIC5_RXB_CORE_BASE 0x56C9000ull
+#define NIC5_RXB_CORE_MAX_OFFSET 0x1000
+#define NIC5_RXB_CORE_SECTION 0x6100
+#define mmNIC5_RXB_CORE_SCT_AWUSER_BASE 0x56C9610ull
+#define NIC5_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000
+#define NIC5_RXB_CORE_SCT_AWUSER_SECTION 0x8700
+#define mmNIC5_RXB_CORE_SPECIAL_BASE 0x56C9E80ull
+#define NIC5_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_RXB_CORE_SPECIAL_SECTION 0x1800
+#define mmNIC5_RXE0_BASE 0x56CA000ull
+#define NIC5_RXE0_MAX_OFFSET 0x1000
+#define NIC5_RXE0_SECTION 0x9000
+#define mmNIC5_RXE0_WQE_ARUSER_BASE 0x56CA900ull
+#define NIC5_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC5_RXE0_WQE_ARUSER_SECTION 0x5800
+#define mmNIC5_RXE0_SPECIAL_BASE 0x56CAE80ull
+#define NIC5_RXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_RXE0_SPECIAL_SECTION 0x1800
+#define mmNIC5_RXE1_BASE 0x56CB000ull
+#define NIC5_RXE1_MAX_OFFSET 0x1000
+#define NIC5_RXE1_SECTION 0x9000
+#define mmNIC5_RXE1_WQE_ARUSER_BASE 0x56CB900ull
+#define NIC5_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC5_RXE1_WQE_ARUSER_SECTION 0x5800
+#define mmNIC5_RXE1_SPECIAL_BASE 0x56CBE80ull
+#define NIC5_RXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_RXE1_SPECIAL_SECTION 0x1800
+#define mmNIC5_RXE0_AXUSER_AXUSER_CQ0_BASE 0x56CC000ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define mmNIC5_RXE0_AXUSER_AXUSER_CQ1_BASE 0x56CC050ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define mmNIC5_RXE0_AXUSER_AXUSER_CQ2_BASE 0x56CC0A0ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define mmNIC5_RXE0_AXUSER_AXUSER_CQ3_BASE 0x56CC0F0ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define mmNIC5_RXE0_AXUSER_AXUSER_CQ4_BASE 0x56CC140ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define mmNIC5_RXE0_AXUSER_AXUSER_CQ5_BASE 0x56CC190ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define mmNIC5_RXE0_AXUSER_AXUSER_CQ6_BASE 0x56CC1E0ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define mmNIC5_RXE0_AXUSER_AXUSER_CQ7_BASE 0x56CC230ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define mmNIC5_RXE0_AXUSER_AXUSER_CQ8_BASE 0x56CC280ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define mmNIC5_RXE0_AXUSER_AXUSER_CQ9_BASE 0x56CC2D0ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define mmNIC5_RXE0_AXUSER_AXUSER_CQ10_BASE 0x56CC320ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define mmNIC5_RXE0_AXUSER_AXUSER_CQ11_BASE 0x56CC370ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define mmNIC5_RXE0_AXUSER_AXUSER_CQ12_BASE 0x56CC3C0ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define mmNIC5_RXE0_AXUSER_AXUSER_CQ13_BASE 0x56CC410ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define mmNIC5_RXE0_AXUSER_AXUSER_CQ14_BASE 0x56CC460ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define mmNIC5_RXE0_AXUSER_AXUSER_CQ15_BASE 0x56CC4B0ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define mmNIC5_RXE0_AXUSER_AXUSER_CQ16_BASE 0x56CC500ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define mmNIC5_RXE0_AXUSER_AXUSER_CQ17_BASE 0x56CC550ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define mmNIC5_RXE0_AXUSER_AXUSER_CQ18_BASE 0x56CC5A0ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define mmNIC5_RXE0_AXUSER_AXUSER_CQ19_BASE 0x56CC5F0ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define mmNIC5_RXE0_AXUSER_AXUSER_CQ20_BASE 0x56CC640ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define mmNIC5_RXE0_AXUSER_AXUSER_CQ21_BASE 0x56CC690ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define mmNIC5_RXE0_AXUSER_AXUSER_CQ22_BASE 0x56CC6E0ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define mmNIC5_RXE0_AXUSER_AXUSER_CQ23_BASE 0x56CC730ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define mmNIC5_RXE0_AXUSER_AXUSER_CQ24_BASE 0x56CC780ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define mmNIC5_RXE0_AXUSER_AXUSER_CQ25_BASE 0x56CC7D0ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define mmNIC5_RXE0_AXUSER_AXUSER_CQ26_BASE 0x56CC820ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define mmNIC5_RXE0_AXUSER_AXUSER_CQ27_BASE 0x56CC870ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define mmNIC5_RXE0_AXUSER_AXUSER_CQ28_BASE 0x56CC8C0ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define mmNIC5_RXE0_AXUSER_AXUSER_CQ29_BASE 0x56CC910ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define mmNIC5_RXE0_AXUSER_AXUSER_CQ30_BASE 0x56CC960ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define mmNIC5_RXE0_AXUSER_AXUSER_CQ31_BASE 0x56CC9B0ull
+#define NIC5_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC5_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define mmNIC5_RXE0_AXUSER_SPECIAL_BASE 0x56CCE80ull
+#define NIC5_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_RXE0_AXUSER_SPECIAL_SECTION 0x1800
+#define mmNIC5_RXE1_AXUSER_AXUSER_CQ0_BASE 0x56CD000ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define mmNIC5_RXE1_AXUSER_AXUSER_CQ1_BASE 0x56CD050ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define mmNIC5_RXE1_AXUSER_AXUSER_CQ2_BASE 0x56CD0A0ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define mmNIC5_RXE1_AXUSER_AXUSER_CQ3_BASE 0x56CD0F0ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define mmNIC5_RXE1_AXUSER_AXUSER_CQ4_BASE 0x56CD140ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define mmNIC5_RXE1_AXUSER_AXUSER_CQ5_BASE 0x56CD190ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define mmNIC5_RXE1_AXUSER_AXUSER_CQ6_BASE 0x56CD1E0ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define mmNIC5_RXE1_AXUSER_AXUSER_CQ7_BASE 0x56CD230ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define mmNIC5_RXE1_AXUSER_AXUSER_CQ8_BASE 0x56CD280ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define mmNIC5_RXE1_AXUSER_AXUSER_CQ9_BASE 0x56CD2D0ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define mmNIC5_RXE1_AXUSER_AXUSER_CQ10_BASE 0x56CD320ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define mmNIC5_RXE1_AXUSER_AXUSER_CQ11_BASE 0x56CD370ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define mmNIC5_RXE1_AXUSER_AXUSER_CQ12_BASE 0x56CD3C0ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define mmNIC5_RXE1_AXUSER_AXUSER_CQ13_BASE 0x56CD410ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define mmNIC5_RXE1_AXUSER_AXUSER_CQ14_BASE 0x56CD460ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define mmNIC5_RXE1_AXUSER_AXUSER_CQ15_BASE 0x56CD4B0ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define mmNIC5_RXE1_AXUSER_AXUSER_CQ16_BASE 0x56CD500ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define mmNIC5_RXE1_AXUSER_AXUSER_CQ17_BASE 0x56CD550ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define mmNIC5_RXE1_AXUSER_AXUSER_CQ18_BASE 0x56CD5A0ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define mmNIC5_RXE1_AXUSER_AXUSER_CQ19_BASE 0x56CD5F0ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define mmNIC5_RXE1_AXUSER_AXUSER_CQ20_BASE 0x56CD640ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define mmNIC5_RXE1_AXUSER_AXUSER_CQ21_BASE 0x56CD690ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define mmNIC5_RXE1_AXUSER_AXUSER_CQ22_BASE 0x56CD6E0ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define mmNIC5_RXE1_AXUSER_AXUSER_CQ23_BASE 0x56CD730ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define mmNIC5_RXE1_AXUSER_AXUSER_CQ24_BASE 0x56CD780ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define mmNIC5_RXE1_AXUSER_AXUSER_CQ25_BASE 0x56CD7D0ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define mmNIC5_RXE1_AXUSER_AXUSER_CQ26_BASE 0x56CD820ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define mmNIC5_RXE1_AXUSER_AXUSER_CQ27_BASE 0x56CD870ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define mmNIC5_RXE1_AXUSER_AXUSER_CQ28_BASE 0x56CD8C0ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define mmNIC5_RXE1_AXUSER_AXUSER_CQ29_BASE 0x56CD910ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define mmNIC5_RXE1_AXUSER_AXUSER_CQ30_BASE 0x56CD960ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define mmNIC5_RXE1_AXUSER_AXUSER_CQ31_BASE 0x56CD9B0ull
+#define NIC5_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC5_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define mmNIC5_RXE1_AXUSER_SPECIAL_BASE 0x56CDE80ull
+#define NIC5_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_RXE1_AXUSER_SPECIAL_SECTION 0x2180
+#define mmNIC5_TXS0_BASE 0x56D0000ull
+#define NIC5_TXS0_MAX_OFFSET 0x1000
+#define NIC5_TXS0_SECTION 0xE800
+#define mmNIC5_TXS0_SPECIAL_BASE 0x56D0E80ull
+#define NIC5_TXS0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_TXS0_SPECIAL_SECTION 0x1800
+#define mmNIC5_TXS1_BASE 0x56D1000ull
+#define NIC5_TXS1_MAX_OFFSET 0x1000
+#define NIC5_TXS1_SECTION 0xE800
+#define mmNIC5_TXS1_SPECIAL_BASE 0x56D1E80ull
+#define NIC5_TXS1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_TXS1_SPECIAL_SECTION 0x1800
+#define mmNIC5_TXE0_BASE 0x56D2000ull
+#define NIC5_TXE0_MAX_OFFSET 0x1000
+#define NIC5_TXE0_SECTION 0xE800
+#define mmNIC5_TXE0_SPECIAL_BASE 0x56D2E80ull
+#define NIC5_TXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_TXE0_SPECIAL_SECTION 0x1800
+#define mmNIC5_TXE1_BASE 0x56D3000ull
+#define NIC5_TXE1_MAX_OFFSET 0x1000
+#define NIC5_TXE1_SECTION 0xE800
+#define mmNIC5_TXE1_SPECIAL_BASE 0x56D3E80ull
+#define NIC5_TXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_TXE1_SPECIAL_SECTION 0x1800
+#define mmNIC5_TXB_BASE 0x56D4000ull
+#define NIC5_TXB_MAX_OFFSET 0x1000
+#define NIC5_TXB_SECTION 0xE800
+#define mmNIC5_TXB_SPECIAL_BASE 0x56D4E80ull
+#define NIC5_TXB_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_TXB_SPECIAL_SECTION 0x1800
+#define mmNIC5_MSTR_IF_RR_SHRD_HBW_BASE 0x56D5000ull
+#define NIC5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define NIC5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmNIC5_MSTR_IF_RR_PRVT_HBW_BASE 0x56D5200ull
+#define NIC5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define NIC5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmNIC5_MSTR_IF_RR_SHRD_LBW_BASE 0x56D5400ull
+#define NIC5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define NIC5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmNIC5_MSTR_IF_RR_PRVT_LBW_BASE 0x56D5600ull
+#define NIC5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define NIC5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmNIC5_MSTR_IF_E2E_CRDT_BASE 0x56D5800ull
+#define NIC5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define NIC5_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmNIC5_MSTR_IF_AXUSER_BASE 0x56D5A80ull
+#define NIC5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define NIC5_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmNIC5_MSTR_IF_DBG_HBW_BASE 0x56D5B00ull
+#define NIC5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC5_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmNIC5_MSTR_IF_DBG_LBW_BASE 0x56D5B80ull
+#define NIC5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC5_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmNIC5_MSTR_IF_CORE_HBW_BASE 0x56D5C00ull
+#define NIC5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define NIC5_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmNIC5_MSTR_IF_CORE_LBW_BASE 0x56D5D80ull
+#define NIC5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define NIC5_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmNIC5_MSTR_IF_SPECIAL_BASE 0x56D5E80ull
+#define NIC5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmNIC5_TX_AXUSER_BASE 0x56D6000ull
+#define NIC5_TX_AXUSER_MAX_OFFSET 0x5000
+#define NIC5_TX_AXUSER_SECTION 0x2000
+#define mmNIC5_SERDES0_BASE 0x56D8000ull
+#define NIC5_SERDES0_MAX_OFFSET 0x3E40
+#define NIC5_SERDES0_SECTION 0x4000
+#define mmNIC5_SERDES1_BASE 0x56DC000ull
+#define NIC5_SERDES1_MAX_OFFSET 0x3E40
+#define NIC5_SERDES1_SECTION 0x4000
+#define mmNIC5_PHY_BASE 0x56E0000ull
+#define NIC5_PHY_MAX_OFFSET 0x1000
+#define NIC5_PHY_SECTION 0xE800
+#define mmNIC5_PHY_SPECIAL_BASE 0x56E0E80ull
+#define NIC5_PHY_SPECIAL_MAX_OFFSET 0x1800
+#define NIC5_PHY_SPECIAL_SECTION 0x7180
+#define mmPRT5_MAC_AUX_BASE 0x56E8000ull
+#define PRT5_MAC_AUX_MAX_OFFSET 0x1000
+#define PRT5_MAC_AUX_SECTION 0xE800
+#define mmPRT5_MAC_AUX_SPECIAL_BASE 0x56E8E80ull
+#define PRT5_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define PRT5_MAC_AUX_SPECIAL_SECTION 0x1800
+#define mmPRT5_MAC_CORE_BASE 0x56E9000ull
+#define PRT5_MAC_CORE_MAX_OFFSET 0x1000
+#define PRT5_MAC_CORE_SECTION 0xE800
+#define mmPRT5_MAC_CORE_SPECIAL_BASE 0x56E9E80ull
+#define PRT5_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define PRT5_MAC_CORE_SPECIAL_SECTION 0x1800
+#define mmNIC5_MAC_RS_FEC_BASE 0x56EA000ull
+#define NIC5_MAC_RS_FEC_MAX_OFFSET 0x2DC0
+#define NIC5_MAC_RS_FEC_SECTION 0x1000
+#define mmNIC5_MAC_GLOB_STAT_CONTROL_REG_BASE 0x56EB000ull
+#define NIC5_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000
+#define NIC5_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000
+#define mmNIC5_MAC_GLOB_STAT_RX0_BASE 0x56EB100ull
+#define NIC5_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00
+#define NIC5_MAC_GLOB_STAT_RX0_SECTION 0x8C00
+#define mmNIC5_MAC_GLOB_STAT_RX1_BASE 0x56EB18Cull
+#define NIC5_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00
+#define NIC5_MAC_GLOB_STAT_RX1_SECTION 0x8C00
+#define mmNIC5_MAC_GLOB_STAT_RX2_BASE 0x56EB218ull
+#define NIC5_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00
+#define NIC5_MAC_GLOB_STAT_RX2_SECTION 0x8C00
+#define mmNIC5_MAC_GLOB_STAT_RX3_BASE 0x56EB2A4ull
+#define NIC5_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00
+#define NIC5_MAC_GLOB_STAT_RX3_SECTION 0x8C00
+#define mmNIC5_MAC_GLOB_STAT_TX0_BASE 0x56EB330ull
+#define NIC5_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800
+#define NIC5_MAC_GLOB_STAT_TX0_SECTION 0x6800
+#define mmNIC5_MAC_GLOB_STAT_TX1_BASE 0x56EB398ull
+#define NIC5_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800
+#define NIC5_MAC_GLOB_STAT_TX1_SECTION 0x6800
+#define mmNIC5_MAC_GLOB_STAT_TX2_BASE 0x56EB400ull
+#define NIC5_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800
+#define NIC5_MAC_GLOB_STAT_TX2_SECTION 0x6800
+#define mmNIC5_MAC_GLOB_STAT_TX3_BASE 0x56EB468ull
+#define NIC5_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800
+#define NIC5_MAC_GLOB_STAT_TX3_SECTION 0x3980
+#define mmNIC5_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x56EB800ull
+#define NIC5_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0
+#define NIC5_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000
+#define mmNIC5_MAC_CH0_MAC_PCS_BASE 0x56EC000ull
+#define NIC5_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC5_MAC_CH0_MAC_PCS_SECTION 0x4000
+#define mmNIC5_MAC_CH0_MAC_128_BASE 0x56EC400ull
+#define NIC5_MAC_CH0_MAC_128_MAX_OFFSET 0xA400
+#define NIC5_MAC_CH0_MAC_128_SECTION 0x4000
+#define mmNIC5_MAC_CH0_MAC_AN_BASE 0x56EC800ull
+#define NIC5_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400
+#define NIC5_MAC_CH0_MAC_AN_SECTION 0x8000
+#define mmNIC5_MAC_CH1_MAC_PCS_BASE 0x56ED000ull
+#define NIC5_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC5_MAC_CH1_MAC_PCS_SECTION 0x4000
+#define mmNIC5_MAC_CH1_MAC_128_BASE 0x56ED400ull
+#define NIC5_MAC_CH1_MAC_128_MAX_OFFSET 0xA400
+#define NIC5_MAC_CH1_MAC_128_SECTION 0x4000
+#define mmNIC5_MAC_CH1_MAC_AN_BASE 0x56ED800ull
+#define NIC5_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400
+#define NIC5_MAC_CH1_MAC_AN_SECTION 0x8000
+#define mmNIC5_MAC_CH2_MAC_PCS_BASE 0x56EE000ull
+#define NIC5_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC5_MAC_CH2_MAC_PCS_SECTION 0x4000
+#define mmNIC5_MAC_CH2_MAC_128_BASE 0x56EE400ull
+#define NIC5_MAC_CH2_MAC_128_MAX_OFFSET 0xA400
+#define NIC5_MAC_CH2_MAC_128_SECTION 0x4000
+#define mmNIC5_MAC_CH2_MAC_AN_BASE 0x56EE800ull
+#define NIC5_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400
+#define NIC5_MAC_CH2_MAC_AN_SECTION 0x8000
+#define mmNIC5_MAC_CH3_MAC_PCS_BASE 0x56EF000ull
+#define NIC5_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC5_MAC_CH3_MAC_PCS_SECTION 0x4000
+#define mmNIC5_MAC_CH3_MAC_128_BASE 0x56EF400ull
+#define NIC5_MAC_CH3_MAC_128_MAX_OFFSET 0xA400
+#define NIC5_MAC_CH3_MAC_128_SECTION 0x4000
+#define mmNIC5_MAC_CH3_MAC_AN_BASE 0x56EF800ull
+#define NIC5_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400
+#define NIC5_MAC_CH3_MAC_AN_SECTION 0x10800
+#define mmNIC6_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5700000ull
+#define NIC6_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC6_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5700080ull
+#define NIC6_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC6_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5700100ull
+#define NIC6_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC6_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5700180ull
+#define NIC6_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC6_UMR0_0_SPECIAL_BASE 0x5700E80ull
+#define NIC6_UMR0_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR0_0_SPECIAL_SECTION 0x1800
+#define mmNIC6_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5701000ull
+#define NIC6_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC6_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5701080ull
+#define NIC6_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC6_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5701100ull
+#define NIC6_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC6_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5701180ull
+#define NIC6_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC6_UMR0_1_SPECIAL_BASE 0x5701E80ull
+#define NIC6_UMR0_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR0_1_SPECIAL_SECTION 0x1800
+#define mmNIC6_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5702000ull
+#define NIC6_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC6_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5702080ull
+#define NIC6_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC6_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5702100ull
+#define NIC6_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC6_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5702180ull
+#define NIC6_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC6_UMR0_2_SPECIAL_BASE 0x5702E80ull
+#define NIC6_UMR0_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR0_2_SPECIAL_SECTION 0x1800
+#define mmNIC6_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5703000ull
+#define NIC6_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC6_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5703080ull
+#define NIC6_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC6_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5703100ull
+#define NIC6_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC6_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5703180ull
+#define NIC6_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC6_UMR0_3_SPECIAL_BASE 0x5703E80ull
+#define NIC6_UMR0_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR0_3_SPECIAL_SECTION 0x1800
+#define mmNIC6_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5704000ull
+#define NIC6_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC6_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5704080ull
+#define NIC6_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC6_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5704100ull
+#define NIC6_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC6_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5704180ull
+#define NIC6_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC6_UMR0_4_SPECIAL_BASE 0x5704E80ull
+#define NIC6_UMR0_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR0_4_SPECIAL_SECTION 0x1800
+#define mmNIC6_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5705000ull
+#define NIC6_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC6_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5705080ull
+#define NIC6_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC6_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5705100ull
+#define NIC6_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC6_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5705180ull
+#define NIC6_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC6_UMR0_5_SPECIAL_BASE 0x5705E80ull
+#define NIC6_UMR0_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR0_5_SPECIAL_SECTION 0x1800
+#define mmNIC6_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5706000ull
+#define NIC6_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC6_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5706080ull
+#define NIC6_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC6_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5706100ull
+#define NIC6_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC6_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5706180ull
+#define NIC6_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC6_UMR0_6_SPECIAL_BASE 0x5706E80ull
+#define NIC6_UMR0_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR0_6_SPECIAL_SECTION 0x1800
+#define mmNIC6_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5707000ull
+#define NIC6_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC6_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5707080ull
+#define NIC6_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC6_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5707100ull
+#define NIC6_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC6_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5707180ull
+#define NIC6_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC6_UMR0_7_SPECIAL_BASE 0x5707E80ull
+#define NIC6_UMR0_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR0_7_SPECIAL_SECTION 0x1800
+#define mmNIC6_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5708000ull
+#define NIC6_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC6_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5708080ull
+#define NIC6_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC6_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5708100ull
+#define NIC6_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC6_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5708180ull
+#define NIC6_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC6_UMR0_8_SPECIAL_BASE 0x5708E80ull
+#define NIC6_UMR0_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR0_8_SPECIAL_SECTION 0x1800
+#define mmNIC6_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5709000ull
+#define NIC6_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC6_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5709080ull
+#define NIC6_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC6_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5709100ull
+#define NIC6_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC6_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5709180ull
+#define NIC6_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC6_UMR0_9_SPECIAL_BASE 0x5709E80ull
+#define NIC6_UMR0_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR0_9_SPECIAL_SECTION 0x1800
+#define mmNIC6_UMR0_10_UNSECURE_DOORBELL0_BASE 0x570A000ull
+#define NIC6_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC6_UMR0_10_UNSECURE_DOORBELL1_BASE 0x570A080ull
+#define NIC6_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC6_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x570A100ull
+#define NIC6_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC6_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x570A180ull
+#define NIC6_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC6_UMR0_10_SPECIAL_BASE 0x570AE80ull
+#define NIC6_UMR0_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR0_10_SPECIAL_SECTION 0x1800
+#define mmNIC6_UMR0_11_UNSECURE_DOORBELL0_BASE 0x570B000ull
+#define NIC6_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC6_UMR0_11_UNSECURE_DOORBELL1_BASE 0x570B080ull
+#define NIC6_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC6_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x570B100ull
+#define NIC6_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC6_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x570B180ull
+#define NIC6_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC6_UMR0_11_SPECIAL_BASE 0x570BE80ull
+#define NIC6_UMR0_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR0_11_SPECIAL_SECTION 0x1800
+#define mmNIC6_UMR0_12_UNSECURE_DOORBELL0_BASE 0x570C000ull
+#define NIC6_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC6_UMR0_12_UNSECURE_DOORBELL1_BASE 0x570C080ull
+#define NIC6_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC6_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x570C100ull
+#define NIC6_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC6_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x570C180ull
+#define NIC6_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC6_UMR0_12_SPECIAL_BASE 0x570CE80ull
+#define NIC6_UMR0_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR0_12_SPECIAL_SECTION 0x1800
+#define mmNIC6_UMR0_13_UNSECURE_DOORBELL0_BASE 0x570D000ull
+#define NIC6_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC6_UMR0_13_UNSECURE_DOORBELL1_BASE 0x570D080ull
+#define NIC6_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC6_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x570D100ull
+#define NIC6_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC6_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x570D180ull
+#define NIC6_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC6_UMR0_13_SPECIAL_BASE 0x570DE80ull
+#define NIC6_UMR0_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR0_13_SPECIAL_SECTION 0x1800
+#define mmNIC6_UMR0_14_UNSECURE_DOORBELL0_BASE 0x570E000ull
+#define NIC6_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC6_UMR0_14_UNSECURE_DOORBELL1_BASE 0x570E080ull
+#define NIC6_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC6_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x570E100ull
+#define NIC6_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC6_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x570E180ull
+#define NIC6_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC6_UMR0_14_SPECIAL_BASE 0x570EE80ull
+#define NIC6_UMR0_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR0_14_SPECIAL_SECTION 0x1180
+#define mmNIC6_QM_DCCM0_BASE 0x5710000ull
+#define NIC6_QM_DCCM0_MAX_OFFSET 0x4000
+#define NIC6_QM_DCCM0_SECTION 0x8000
+#define mmNIC6_QM_ARC_AUX0_BASE 0x5718000ull
+#define NIC6_QM_ARC_AUX0_MAX_OFFSET 0x1000
+#define NIC6_QM_ARC_AUX0_SECTION 0xE800
+#define mmNIC6_QM_ARC_AUX0_SPECIAL_BASE 0x5718E80ull
+#define NIC6_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_QM_ARC_AUX0_SPECIAL_SECTION 0x1180
+#define mmNIC6_QM0_BASE 0x571A000ull
+#define NIC6_QM0_MAX_OFFSET 0x1000
+#define NIC6_QM0_SECTION 0x9000
+#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x571A900ull
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x571A908ull
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x571A910ull
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x571A918ull
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x571A920ull
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x571A928ull
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x571A930ull
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x571A938ull
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x571A940ull
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x571A948ull
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x571A950ull
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x571A958ull
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x571A960ull
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x571A968ull
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x571A970ull
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x571A978ull
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC6_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmNIC6_QM0_AXUSER_SECURED_BASE 0x571AB00ull
+#define NIC6_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC6_QM0_AXUSER_SECURED_SECTION 0x8000
+#define mmNIC6_QM0_AXUSER_NONSECURED_BASE 0x571AB80ull
+#define NIC6_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC6_QM0_AXUSER_NONSECURED_SECTION 0x8000
+#define mmNIC6_QM0_DBG_HBW_BASE 0x571AC00ull
+#define NIC6_QM0_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC6_QM0_DBG_HBW_SECTION 0x8000
+#define mmNIC6_QM0_DBG_LBW_BASE 0x571AC80ull
+#define NIC6_QM0_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC6_QM0_DBG_LBW_SECTION 0x1000
+#define mmNIC6_QM0_CGM_BASE 0x571AD80ull
+#define NIC6_QM0_CGM_MAX_OFFSET 0xC000
+#define NIC6_QM0_CGM_SECTION 0x1000
+#define mmNIC6_QM0_SPECIAL_BASE 0x571AE80ull
+#define NIC6_QM0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_QM0_SPECIAL_SECTION 0x4180
+#define mmNIC6_QPC0_BASE 0x571F000ull
+#define NIC6_QPC0_MAX_OFFSET 0x1000
+#define NIC6_QPC0_SECTION 0x7200
+#define mmNIC6_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x571F720ull
+#define NIC6_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x571F728ull
+#define NIC6_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x571F730ull
+#define NIC6_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x571F738ull
+#define NIC6_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x571F740ull
+#define NIC6_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x571F748ull
+#define NIC6_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x571F750ull
+#define NIC6_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x571F758ull
+#define NIC6_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x571F760ull
+#define NIC6_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x571F768ull
+#define NIC6_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x571F770ull
+#define NIC6_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x571F778ull
+#define NIC6_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x571F780ull
+#define NIC6_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x571F788ull
+#define NIC6_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x571F790ull
+#define NIC6_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x571F798ull
+#define NIC6_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x571F7A0ull
+#define NIC6_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x571F7A8ull
+#define NIC6_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x571F7B0ull
+#define NIC6_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x571F7B8ull
+#define NIC6_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x571F7C0ull
+#define NIC6_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x571F7C8ull
+#define NIC6_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x571F7D0ull
+#define NIC6_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x571F7D8ull
+#define NIC6_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x571F7E0ull
+#define NIC6_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x571F7E8ull
+#define NIC6_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x571F7F0ull
+#define NIC6_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x571F7F8ull
+#define NIC6_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x571F800ull
+#define NIC6_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x571F808ull
+#define NIC6_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x571F810ull
+#define NIC6_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x571F818ull
+#define NIC6_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define mmNIC6_QPC0_AXUSER_CONG_QUE_BASE 0x571FB80ull
+#define NIC6_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC6_QPC0_AXUSER_CONG_QUE_SECTION 0x6000
+#define mmNIC6_QPC0_AXUSER_RXWQE_BASE 0x571FBE0ull
+#define NIC6_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC6_QPC0_AXUSER_RXWQE_SECTION 0x6000
+#define mmNIC6_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x571FC40ull
+#define NIC6_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC6_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define mmNIC6_QPC0_AXUSER_DB_FIFO_BASE 0x571FCA0ull
+#define NIC6_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC6_QPC0_AXUSER_DB_FIFO_SECTION 0x6000
+#define mmNIC6_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x571FD00ull
+#define NIC6_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC6_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define mmNIC6_QPC0_AXUSER_ERR_FIFO_BASE 0x571FD60ull
+#define NIC6_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC6_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000
+#define mmNIC6_QPC0_AXUSER_QPC_RESP_BASE 0x571FDC0ull
+#define NIC6_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC6_QPC0_AXUSER_QPC_RESP_SECTION 0x6000
+#define mmNIC6_QPC0_AXUSER_QPC_REQ_BASE 0x571FE20ull
+#define NIC6_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC6_QPC0_AXUSER_QPC_REQ_SECTION 0x6000
+#define mmNIC6_QPC0_SPECIAL_BASE 0x571FE80ull
+#define NIC6_QPC0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_QPC0_SPECIAL_SECTION 0x1800
+#define mmNIC6_UMR1_0_UNSECURE_DOORBELL0_BASE 0x5720000ull
+#define NIC6_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC6_UMR1_0_UNSECURE_DOORBELL1_BASE 0x5720080ull
+#define NIC6_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC6_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x5720100ull
+#define NIC6_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC6_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x5720180ull
+#define NIC6_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC6_UMR1_0_SPECIAL_BASE 0x5720E80ull
+#define NIC6_UMR1_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR1_0_SPECIAL_SECTION 0x1800
+#define mmNIC6_UMR1_1_UNSECURE_DOORBELL0_BASE 0x5721000ull
+#define NIC6_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC6_UMR1_1_UNSECURE_DOORBELL1_BASE 0x5721080ull
+#define NIC6_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC6_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x5721100ull
+#define NIC6_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC6_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x5721180ull
+#define NIC6_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC6_UMR1_1_SPECIAL_BASE 0x5721E80ull
+#define NIC6_UMR1_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR1_1_SPECIAL_SECTION 0x1800
+#define mmNIC6_UMR1_2_UNSECURE_DOORBELL0_BASE 0x5722000ull
+#define NIC6_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC6_UMR1_2_UNSECURE_DOORBELL1_BASE 0x5722080ull
+#define NIC6_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC6_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x5722100ull
+#define NIC6_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC6_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x5722180ull
+#define NIC6_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC6_UMR1_2_SPECIAL_BASE 0x5722E80ull
+#define NIC6_UMR1_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR1_2_SPECIAL_SECTION 0x1800
+#define mmNIC6_UMR1_3_UNSECURE_DOORBELL0_BASE 0x5723000ull
+#define NIC6_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC6_UMR1_3_UNSECURE_DOORBELL1_BASE 0x5723080ull
+#define NIC6_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC6_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x5723100ull
+#define NIC6_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC6_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x5723180ull
+#define NIC6_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC6_UMR1_3_SPECIAL_BASE 0x5723E80ull
+#define NIC6_UMR1_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR1_3_SPECIAL_SECTION 0x1800
+#define mmNIC6_UMR1_4_UNSECURE_DOORBELL0_BASE 0x5724000ull
+#define NIC6_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC6_UMR1_4_UNSECURE_DOORBELL1_BASE 0x5724080ull
+#define NIC6_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC6_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x5724100ull
+#define NIC6_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC6_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x5724180ull
+#define NIC6_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC6_UMR1_4_SPECIAL_BASE 0x5724E80ull
+#define NIC6_UMR1_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR1_4_SPECIAL_SECTION 0x1800
+#define mmNIC6_UMR1_5_UNSECURE_DOORBELL0_BASE 0x5725000ull
+#define NIC6_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC6_UMR1_5_UNSECURE_DOORBELL1_BASE 0x5725080ull
+#define NIC6_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC6_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x5725100ull
+#define NIC6_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC6_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x5725180ull
+#define NIC6_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC6_UMR1_5_SPECIAL_BASE 0x5725E80ull
+#define NIC6_UMR1_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR1_5_SPECIAL_SECTION 0x1800
+#define mmNIC6_UMR1_6_UNSECURE_DOORBELL0_BASE 0x5726000ull
+#define NIC6_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC6_UMR1_6_UNSECURE_DOORBELL1_BASE 0x5726080ull
+#define NIC6_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC6_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x5726100ull
+#define NIC6_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC6_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x5726180ull
+#define NIC6_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC6_UMR1_6_SPECIAL_BASE 0x5726E80ull
+#define NIC6_UMR1_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR1_6_SPECIAL_SECTION 0x1800
+#define mmNIC6_UMR1_7_UNSECURE_DOORBELL0_BASE 0x5727000ull
+#define NIC6_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC6_UMR1_7_UNSECURE_DOORBELL1_BASE 0x5727080ull
+#define NIC6_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC6_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x5727100ull
+#define NIC6_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC6_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x5727180ull
+#define NIC6_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC6_UMR1_7_SPECIAL_BASE 0x5727E80ull
+#define NIC6_UMR1_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR1_7_SPECIAL_SECTION 0x1800
+#define mmNIC6_UMR1_8_UNSECURE_DOORBELL0_BASE 0x5728000ull
+#define NIC6_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC6_UMR1_8_UNSECURE_DOORBELL1_BASE 0x5728080ull
+#define NIC6_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC6_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x5728100ull
+#define NIC6_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC6_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x5728180ull
+#define NIC6_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC6_UMR1_8_SPECIAL_BASE 0x5728E80ull
+#define NIC6_UMR1_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR1_8_SPECIAL_SECTION 0x1800
+#define mmNIC6_UMR1_9_UNSECURE_DOORBELL0_BASE 0x5729000ull
+#define NIC6_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC6_UMR1_9_UNSECURE_DOORBELL1_BASE 0x5729080ull
+#define NIC6_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC6_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x5729100ull
+#define NIC6_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC6_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x5729180ull
+#define NIC6_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC6_UMR1_9_SPECIAL_BASE 0x5729E80ull
+#define NIC6_UMR1_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR1_9_SPECIAL_SECTION 0x1800
+#define mmNIC6_UMR1_10_UNSECURE_DOORBELL0_BASE 0x572A000ull
+#define NIC6_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC6_UMR1_10_UNSECURE_DOORBELL1_BASE 0x572A080ull
+#define NIC6_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC6_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x572A100ull
+#define NIC6_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC6_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x572A180ull
+#define NIC6_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC6_UMR1_10_SPECIAL_BASE 0x572AE80ull
+#define NIC6_UMR1_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR1_10_SPECIAL_SECTION 0x1800
+#define mmNIC6_UMR1_11_UNSECURE_DOORBELL0_BASE 0x572B000ull
+#define NIC6_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC6_UMR1_11_UNSECURE_DOORBELL1_BASE 0x572B080ull
+#define NIC6_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC6_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x572B100ull
+#define NIC6_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC6_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x572B180ull
+#define NIC6_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC6_UMR1_11_SPECIAL_BASE 0x572BE80ull
+#define NIC6_UMR1_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR1_11_SPECIAL_SECTION 0x1800
+#define mmNIC6_UMR1_12_UNSECURE_DOORBELL0_BASE 0x572C000ull
+#define NIC6_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC6_UMR1_12_UNSECURE_DOORBELL1_BASE 0x572C080ull
+#define NIC6_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC6_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x572C100ull
+#define NIC6_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC6_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x572C180ull
+#define NIC6_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC6_UMR1_12_SPECIAL_BASE 0x572CE80ull
+#define NIC6_UMR1_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR1_12_SPECIAL_SECTION 0x1800
+#define mmNIC6_UMR1_13_UNSECURE_DOORBELL0_BASE 0x572D000ull
+#define NIC6_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC6_UMR1_13_UNSECURE_DOORBELL1_BASE 0x572D080ull
+#define NIC6_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC6_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x572D100ull
+#define NIC6_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC6_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x572D180ull
+#define NIC6_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC6_UMR1_13_SPECIAL_BASE 0x572DE80ull
+#define NIC6_UMR1_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR1_13_SPECIAL_SECTION 0x1800
+#define mmNIC6_UMR1_14_UNSECURE_DOORBELL0_BASE 0x572E000ull
+#define NIC6_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC6_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC6_UMR1_14_UNSECURE_DOORBELL1_BASE 0x572E080ull
+#define NIC6_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC6_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC6_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x572E100ull
+#define NIC6_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC6_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC6_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x572E180ull
+#define NIC6_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC6_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC6_UMR1_14_SPECIAL_BASE 0x572EE80ull
+#define NIC6_UMR1_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_UMR1_14_SPECIAL_SECTION 0x1180
+#define mmNIC6_QM_DCCM1_BASE 0x5730000ull
+#define NIC6_QM_DCCM1_MAX_OFFSET 0x4000
+#define NIC6_QM_DCCM1_SECTION 0x8000
+#define mmNIC6_QM_ARC_AUX1_BASE 0x5738000ull
+#define NIC6_QM_ARC_AUX1_MAX_OFFSET 0x1000
+#define NIC6_QM_ARC_AUX1_SECTION 0xE800
+#define mmNIC6_QM_ARC_AUX1_SPECIAL_BASE 0x5738E80ull
+#define NIC6_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_QM_ARC_AUX1_SPECIAL_SECTION 0x1180
+#define mmNIC6_QM1_BASE 0x573A000ull
+#define NIC6_QM1_MAX_OFFSET 0x1000
+#define NIC6_QM1_SECTION 0x9000
+#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x573A900ull
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x573A908ull
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x573A910ull
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x573A918ull
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x573A920ull
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x573A928ull
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x573A930ull
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x573A938ull
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x573A940ull
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x573A948ull
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x573A950ull
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x573A958ull
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x573A960ull
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x573A968ull
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x573A970ull
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x573A978ull
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC6_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmNIC6_QM1_AXUSER_SECURED_BASE 0x573AB00ull
+#define NIC6_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC6_QM1_AXUSER_SECURED_SECTION 0x8000
+#define mmNIC6_QM1_AXUSER_NONSECURED_BASE 0x573AB80ull
+#define NIC6_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC6_QM1_AXUSER_NONSECURED_SECTION 0x8000
+#define mmNIC6_QM1_DBG_HBW_BASE 0x573AC00ull
+#define NIC6_QM1_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC6_QM1_DBG_HBW_SECTION 0x8000
+#define mmNIC6_QM1_DBG_LBW_BASE 0x573AC80ull
+#define NIC6_QM1_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC6_QM1_DBG_LBW_SECTION 0x1000
+#define mmNIC6_QM1_CGM_BASE 0x573AD80ull
+#define NIC6_QM1_CGM_MAX_OFFSET 0xC000
+#define NIC6_QM1_CGM_SECTION 0x1000
+#define mmNIC6_QM1_SPECIAL_BASE 0x573AE80ull
+#define NIC6_QM1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_QM1_SPECIAL_SECTION 0x4180
+#define mmNIC6_QPC1_BASE 0x573F000ull
+#define NIC6_QPC1_MAX_OFFSET 0x1000
+#define NIC6_QPC1_SECTION 0x7200
+#define mmNIC6_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x573F720ull
+#define NIC6_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x573F728ull
+#define NIC6_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x573F730ull
+#define NIC6_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x573F738ull
+#define NIC6_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x573F740ull
+#define NIC6_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x573F748ull
+#define NIC6_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x573F750ull
+#define NIC6_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x573F758ull
+#define NIC6_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x573F760ull
+#define NIC6_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x573F768ull
+#define NIC6_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x573F770ull
+#define NIC6_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x573F778ull
+#define NIC6_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x573F780ull
+#define NIC6_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x573F788ull
+#define NIC6_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x573F790ull
+#define NIC6_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x573F798ull
+#define NIC6_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x573F7A0ull
+#define NIC6_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x573F7A8ull
+#define NIC6_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x573F7B0ull
+#define NIC6_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x573F7B8ull
+#define NIC6_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x573F7C0ull
+#define NIC6_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x573F7C8ull
+#define NIC6_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x573F7D0ull
+#define NIC6_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x573F7D8ull
+#define NIC6_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x573F7E0ull
+#define NIC6_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x573F7E8ull
+#define NIC6_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x573F7F0ull
+#define NIC6_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x573F7F8ull
+#define NIC6_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x573F800ull
+#define NIC6_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x573F808ull
+#define NIC6_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x573F810ull
+#define NIC6_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC6_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x573F818ull
+#define NIC6_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC6_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define mmNIC6_QPC1_AXUSER_CONG_QUE_BASE 0x573FB80ull
+#define NIC6_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC6_QPC1_AXUSER_CONG_QUE_SECTION 0x6000
+#define mmNIC6_QPC1_AXUSER_RXWQE_BASE 0x573FBE0ull
+#define NIC6_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC6_QPC1_AXUSER_RXWQE_SECTION 0x6000
+#define mmNIC6_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x573FC40ull
+#define NIC6_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC6_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define mmNIC6_QPC1_AXUSER_DB_FIFO_BASE 0x573FCA0ull
+#define NIC6_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC6_QPC1_AXUSER_DB_FIFO_SECTION 0x6000
+#define mmNIC6_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x573FD00ull
+#define NIC6_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC6_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define mmNIC6_QPC1_AXUSER_ERR_FIFO_BASE 0x573FD60ull
+#define NIC6_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC6_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000
+#define mmNIC6_QPC1_AXUSER_QPC_RESP_BASE 0x573FDC0ull
+#define NIC6_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC6_QPC1_AXUSER_QPC_RESP_SECTION 0x6000
+#define mmNIC6_QPC1_AXUSER_QPC_REQ_BASE 0x573FE20ull
+#define NIC6_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC6_QPC1_AXUSER_QPC_REQ_SECTION 0x6000
+#define mmNIC6_QPC1_SPECIAL_BASE 0x573FE80ull
+#define NIC6_QPC1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_QPC1_SPECIAL_SECTION 0x8180
+#define mmNIC6_TMR_BASE 0x5748000ull
+#define NIC6_TMR_MAX_OFFSET 0x1000
+#define NIC6_TMR_SECTION 0xD600
+#define mmNIC6_TMR_AXUSER_TMR_FREE_LIST_BASE 0x5748D60ull
+#define NIC6_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000
+#define NIC6_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000
+#define mmNIC6_TMR_AXUSER_TMR_FIFO_BASE 0x5748DC0ull
+#define NIC6_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000
+#define NIC6_TMR_AXUSER_TMR_FIFO_SECTION 0x6000
+#define mmNIC6_TMR_AXUSER_TMR_FSM_BASE 0x5748E20ull
+#define NIC6_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000
+#define NIC6_TMR_AXUSER_TMR_FSM_SECTION 0x6000
+#define mmNIC6_TMR_SPECIAL_BASE 0x5748E80ull
+#define NIC6_TMR_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_TMR_SPECIAL_SECTION 0x1800
+#define mmNIC6_RXB_CORE_BASE 0x5749000ull
+#define NIC6_RXB_CORE_MAX_OFFSET 0x1000
+#define NIC6_RXB_CORE_SECTION 0x6100
+#define mmNIC6_RXB_CORE_SCT_AWUSER_BASE 0x5749610ull
+#define NIC6_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000
+#define NIC6_RXB_CORE_SCT_AWUSER_SECTION 0x8700
+#define mmNIC6_RXB_CORE_SPECIAL_BASE 0x5749E80ull
+#define NIC6_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_RXB_CORE_SPECIAL_SECTION 0x1800
+#define mmNIC6_RXE0_BASE 0x574A000ull
+#define NIC6_RXE0_MAX_OFFSET 0x1000
+#define NIC6_RXE0_SECTION 0x9000
+#define mmNIC6_RXE0_WQE_ARUSER_BASE 0x574A900ull
+#define NIC6_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC6_RXE0_WQE_ARUSER_SECTION 0x5800
+#define mmNIC6_RXE0_SPECIAL_BASE 0x574AE80ull
+#define NIC6_RXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_RXE0_SPECIAL_SECTION 0x1800
+#define mmNIC6_RXE1_BASE 0x574B000ull
+#define NIC6_RXE1_MAX_OFFSET 0x1000
+#define NIC6_RXE1_SECTION 0x9000
+#define mmNIC6_RXE1_WQE_ARUSER_BASE 0x574B900ull
+#define NIC6_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC6_RXE1_WQE_ARUSER_SECTION 0x5800
+#define mmNIC6_RXE1_SPECIAL_BASE 0x574BE80ull
+#define NIC6_RXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_RXE1_SPECIAL_SECTION 0x1800
+#define mmNIC6_RXE0_AXUSER_AXUSER_CQ0_BASE 0x574C000ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define mmNIC6_RXE0_AXUSER_AXUSER_CQ1_BASE 0x574C050ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define mmNIC6_RXE0_AXUSER_AXUSER_CQ2_BASE 0x574C0A0ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define mmNIC6_RXE0_AXUSER_AXUSER_CQ3_BASE 0x574C0F0ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define mmNIC6_RXE0_AXUSER_AXUSER_CQ4_BASE 0x574C140ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define mmNIC6_RXE0_AXUSER_AXUSER_CQ5_BASE 0x574C190ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define mmNIC6_RXE0_AXUSER_AXUSER_CQ6_BASE 0x574C1E0ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define mmNIC6_RXE0_AXUSER_AXUSER_CQ7_BASE 0x574C230ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define mmNIC6_RXE0_AXUSER_AXUSER_CQ8_BASE 0x574C280ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define mmNIC6_RXE0_AXUSER_AXUSER_CQ9_BASE 0x574C2D0ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define mmNIC6_RXE0_AXUSER_AXUSER_CQ10_BASE 0x574C320ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define mmNIC6_RXE0_AXUSER_AXUSER_CQ11_BASE 0x574C370ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define mmNIC6_RXE0_AXUSER_AXUSER_CQ12_BASE 0x574C3C0ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define mmNIC6_RXE0_AXUSER_AXUSER_CQ13_BASE 0x574C410ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define mmNIC6_RXE0_AXUSER_AXUSER_CQ14_BASE 0x574C460ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define mmNIC6_RXE0_AXUSER_AXUSER_CQ15_BASE 0x574C4B0ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define mmNIC6_RXE0_AXUSER_AXUSER_CQ16_BASE 0x574C500ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define mmNIC6_RXE0_AXUSER_AXUSER_CQ17_BASE 0x574C550ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define mmNIC6_RXE0_AXUSER_AXUSER_CQ18_BASE 0x574C5A0ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define mmNIC6_RXE0_AXUSER_AXUSER_CQ19_BASE 0x574C5F0ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define mmNIC6_RXE0_AXUSER_AXUSER_CQ20_BASE 0x574C640ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define mmNIC6_RXE0_AXUSER_AXUSER_CQ21_BASE 0x574C690ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define mmNIC6_RXE0_AXUSER_AXUSER_CQ22_BASE 0x574C6E0ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define mmNIC6_RXE0_AXUSER_AXUSER_CQ23_BASE 0x574C730ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define mmNIC6_RXE0_AXUSER_AXUSER_CQ24_BASE 0x574C780ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define mmNIC6_RXE0_AXUSER_AXUSER_CQ25_BASE 0x574C7D0ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define mmNIC6_RXE0_AXUSER_AXUSER_CQ26_BASE 0x574C820ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define mmNIC6_RXE0_AXUSER_AXUSER_CQ27_BASE 0x574C870ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define mmNIC6_RXE0_AXUSER_AXUSER_CQ28_BASE 0x574C8C0ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define mmNIC6_RXE0_AXUSER_AXUSER_CQ29_BASE 0x574C910ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define mmNIC6_RXE0_AXUSER_AXUSER_CQ30_BASE 0x574C960ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define mmNIC6_RXE0_AXUSER_AXUSER_CQ31_BASE 0x574C9B0ull
+#define NIC6_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC6_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define mmNIC6_RXE0_AXUSER_SPECIAL_BASE 0x574CE80ull
+#define NIC6_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_RXE0_AXUSER_SPECIAL_SECTION 0x1800
+#define mmNIC6_RXE1_AXUSER_AXUSER_CQ0_BASE 0x574D000ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define mmNIC6_RXE1_AXUSER_AXUSER_CQ1_BASE 0x574D050ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define mmNIC6_RXE1_AXUSER_AXUSER_CQ2_BASE 0x574D0A0ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define mmNIC6_RXE1_AXUSER_AXUSER_CQ3_BASE 0x574D0F0ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define mmNIC6_RXE1_AXUSER_AXUSER_CQ4_BASE 0x574D140ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define mmNIC6_RXE1_AXUSER_AXUSER_CQ5_BASE 0x574D190ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define mmNIC6_RXE1_AXUSER_AXUSER_CQ6_BASE 0x574D1E0ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define mmNIC6_RXE1_AXUSER_AXUSER_CQ7_BASE 0x574D230ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define mmNIC6_RXE1_AXUSER_AXUSER_CQ8_BASE 0x574D280ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define mmNIC6_RXE1_AXUSER_AXUSER_CQ9_BASE 0x574D2D0ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define mmNIC6_RXE1_AXUSER_AXUSER_CQ10_BASE 0x574D320ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define mmNIC6_RXE1_AXUSER_AXUSER_CQ11_BASE 0x574D370ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define mmNIC6_RXE1_AXUSER_AXUSER_CQ12_BASE 0x574D3C0ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define mmNIC6_RXE1_AXUSER_AXUSER_CQ13_BASE 0x574D410ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define mmNIC6_RXE1_AXUSER_AXUSER_CQ14_BASE 0x574D460ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define mmNIC6_RXE1_AXUSER_AXUSER_CQ15_BASE 0x574D4B0ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define mmNIC6_RXE1_AXUSER_AXUSER_CQ16_BASE 0x574D500ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define mmNIC6_RXE1_AXUSER_AXUSER_CQ17_BASE 0x574D550ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define mmNIC6_RXE1_AXUSER_AXUSER_CQ18_BASE 0x574D5A0ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define mmNIC6_RXE1_AXUSER_AXUSER_CQ19_BASE 0x574D5F0ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define mmNIC6_RXE1_AXUSER_AXUSER_CQ20_BASE 0x574D640ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define mmNIC6_RXE1_AXUSER_AXUSER_CQ21_BASE 0x574D690ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define mmNIC6_RXE1_AXUSER_AXUSER_CQ22_BASE 0x574D6E0ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define mmNIC6_RXE1_AXUSER_AXUSER_CQ23_BASE 0x574D730ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define mmNIC6_RXE1_AXUSER_AXUSER_CQ24_BASE 0x574D780ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define mmNIC6_RXE1_AXUSER_AXUSER_CQ25_BASE 0x574D7D0ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define mmNIC6_RXE1_AXUSER_AXUSER_CQ26_BASE 0x574D820ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define mmNIC6_RXE1_AXUSER_AXUSER_CQ27_BASE 0x574D870ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define mmNIC6_RXE1_AXUSER_AXUSER_CQ28_BASE 0x574D8C0ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define mmNIC6_RXE1_AXUSER_AXUSER_CQ29_BASE 0x574D910ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define mmNIC6_RXE1_AXUSER_AXUSER_CQ30_BASE 0x574D960ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define mmNIC6_RXE1_AXUSER_AXUSER_CQ31_BASE 0x574D9B0ull
+#define NIC6_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC6_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define mmNIC6_RXE1_AXUSER_SPECIAL_BASE 0x574DE80ull
+#define NIC6_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_RXE1_AXUSER_SPECIAL_SECTION 0x2180
+#define mmNIC6_TXS0_BASE 0x5750000ull
+#define NIC6_TXS0_MAX_OFFSET 0x1000
+#define NIC6_TXS0_SECTION 0xE800
+#define mmNIC6_TXS0_SPECIAL_BASE 0x5750E80ull
+#define NIC6_TXS0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_TXS0_SPECIAL_SECTION 0x1800
+#define mmNIC6_TXS1_BASE 0x5751000ull
+#define NIC6_TXS1_MAX_OFFSET 0x1000
+#define NIC6_TXS1_SECTION 0xE800
+#define mmNIC6_TXS1_SPECIAL_BASE 0x5751E80ull
+#define NIC6_TXS1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_TXS1_SPECIAL_SECTION 0x1800
+#define mmNIC6_TXE0_BASE 0x5752000ull
+#define NIC6_TXE0_MAX_OFFSET 0x1000
+#define NIC6_TXE0_SECTION 0xE800
+#define mmNIC6_TXE0_SPECIAL_BASE 0x5752E80ull
+#define NIC6_TXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_TXE0_SPECIAL_SECTION 0x1800
+#define mmNIC6_TXE1_BASE 0x5753000ull
+#define NIC6_TXE1_MAX_OFFSET 0x1000
+#define NIC6_TXE1_SECTION 0xE800
+#define mmNIC6_TXE1_SPECIAL_BASE 0x5753E80ull
+#define NIC6_TXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_TXE1_SPECIAL_SECTION 0x1800
+#define mmNIC6_TXB_BASE 0x5754000ull
+#define NIC6_TXB_MAX_OFFSET 0x1000
+#define NIC6_TXB_SECTION 0xE800
+#define mmNIC6_TXB_SPECIAL_BASE 0x5754E80ull
+#define NIC6_TXB_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_TXB_SPECIAL_SECTION 0x1800
+#define mmNIC6_MSTR_IF_RR_SHRD_HBW_BASE 0x5755000ull
+#define NIC6_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define NIC6_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmNIC6_MSTR_IF_RR_PRVT_HBW_BASE 0x5755200ull
+#define NIC6_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define NIC6_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmNIC6_MSTR_IF_RR_SHRD_LBW_BASE 0x5755400ull
+#define NIC6_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define NIC6_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmNIC6_MSTR_IF_RR_PRVT_LBW_BASE 0x5755600ull
+#define NIC6_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define NIC6_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmNIC6_MSTR_IF_E2E_CRDT_BASE 0x5755800ull
+#define NIC6_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define NIC6_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmNIC6_MSTR_IF_AXUSER_BASE 0x5755A80ull
+#define NIC6_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define NIC6_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmNIC6_MSTR_IF_DBG_HBW_BASE 0x5755B00ull
+#define NIC6_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC6_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmNIC6_MSTR_IF_DBG_LBW_BASE 0x5755B80ull
+#define NIC6_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC6_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmNIC6_MSTR_IF_CORE_HBW_BASE 0x5755C00ull
+#define NIC6_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define NIC6_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmNIC6_MSTR_IF_CORE_LBW_BASE 0x5755D80ull
+#define NIC6_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define NIC6_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmNIC6_MSTR_IF_SPECIAL_BASE 0x5755E80ull
+#define NIC6_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmNIC6_TX_AXUSER_BASE 0x5756000ull
+#define NIC6_TX_AXUSER_MAX_OFFSET 0x5000
+#define NIC6_TX_AXUSER_SECTION 0x2000
+#define mmNIC6_SERDES0_BASE 0x5758000ull
+#define NIC6_SERDES0_MAX_OFFSET 0x3E40
+#define NIC6_SERDES0_SECTION 0x4000
+#define mmNIC6_SERDES1_BASE 0x575C000ull
+#define NIC6_SERDES1_MAX_OFFSET 0x3E40
+#define NIC6_SERDES1_SECTION 0x4000
+#define mmNIC6_PHY_BASE 0x5760000ull
+#define NIC6_PHY_MAX_OFFSET 0x1000
+#define NIC6_PHY_SECTION 0xE800
+#define mmNIC6_PHY_SPECIAL_BASE 0x5760E80ull
+#define NIC6_PHY_SPECIAL_MAX_OFFSET 0x1800
+#define NIC6_PHY_SPECIAL_SECTION 0x7180
+#define mmPRT6_MAC_AUX_BASE 0x5768000ull
+#define PRT6_MAC_AUX_MAX_OFFSET 0x1000
+#define PRT6_MAC_AUX_SECTION 0xE800
+#define mmPRT6_MAC_AUX_SPECIAL_BASE 0x5768E80ull
+#define PRT6_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define PRT6_MAC_AUX_SPECIAL_SECTION 0x1800
+#define mmPRT6_MAC_CORE_BASE 0x5769000ull
+#define PRT6_MAC_CORE_MAX_OFFSET 0x1000
+#define PRT6_MAC_CORE_SECTION 0xE800
+#define mmPRT6_MAC_CORE_SPECIAL_BASE 0x5769E80ull
+#define PRT6_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define PRT6_MAC_CORE_SPECIAL_SECTION 0x1800
+#define mmNIC6_MAC_RS_FEC_BASE 0x576A000ull
+#define NIC6_MAC_RS_FEC_MAX_OFFSET 0x2DC0
+#define NIC6_MAC_RS_FEC_SECTION 0x1000
+#define mmNIC6_MAC_GLOB_STAT_CONTROL_REG_BASE 0x576B000ull
+#define NIC6_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000
+#define NIC6_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000
+#define mmNIC6_MAC_GLOB_STAT_RX0_BASE 0x576B100ull
+#define NIC6_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00
+#define NIC6_MAC_GLOB_STAT_RX0_SECTION 0x8C00
+#define mmNIC6_MAC_GLOB_STAT_RX1_BASE 0x576B18Cull
+#define NIC6_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00
+#define NIC6_MAC_GLOB_STAT_RX1_SECTION 0x8C00
+#define mmNIC6_MAC_GLOB_STAT_RX2_BASE 0x576B218ull
+#define NIC6_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00
+#define NIC6_MAC_GLOB_STAT_RX2_SECTION 0x8C00
+#define mmNIC6_MAC_GLOB_STAT_RX3_BASE 0x576B2A4ull
+#define NIC6_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00
+#define NIC6_MAC_GLOB_STAT_RX3_SECTION 0x8C00
+#define mmNIC6_MAC_GLOB_STAT_TX0_BASE 0x576B330ull
+#define NIC6_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800
+#define NIC6_MAC_GLOB_STAT_TX0_SECTION 0x6800
+#define mmNIC6_MAC_GLOB_STAT_TX1_BASE 0x576B398ull
+#define NIC6_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800
+#define NIC6_MAC_GLOB_STAT_TX1_SECTION 0x6800
+#define mmNIC6_MAC_GLOB_STAT_TX2_BASE 0x576B400ull
+#define NIC6_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800
+#define NIC6_MAC_GLOB_STAT_TX2_SECTION 0x6800
+#define mmNIC6_MAC_GLOB_STAT_TX3_BASE 0x576B468ull
+#define NIC6_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800
+#define NIC6_MAC_GLOB_STAT_TX3_SECTION 0x3980
+#define mmNIC6_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x576B800ull
+#define NIC6_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0
+#define NIC6_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000
+#define mmNIC6_MAC_CH0_MAC_PCS_BASE 0x576C000ull
+#define NIC6_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC6_MAC_CH0_MAC_PCS_SECTION 0x4000
+#define mmNIC6_MAC_CH0_MAC_128_BASE 0x576C400ull
+#define NIC6_MAC_CH0_MAC_128_MAX_OFFSET 0xA400
+#define NIC6_MAC_CH0_MAC_128_SECTION 0x4000
+#define mmNIC6_MAC_CH0_MAC_AN_BASE 0x576C800ull
+#define NIC6_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400
+#define NIC6_MAC_CH0_MAC_AN_SECTION 0x8000
+#define mmNIC6_MAC_CH1_MAC_PCS_BASE 0x576D000ull
+#define NIC6_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC6_MAC_CH1_MAC_PCS_SECTION 0x4000
+#define mmNIC6_MAC_CH1_MAC_128_BASE 0x576D400ull
+#define NIC6_MAC_CH1_MAC_128_MAX_OFFSET 0xA400
+#define NIC6_MAC_CH1_MAC_128_SECTION 0x4000
+#define mmNIC6_MAC_CH1_MAC_AN_BASE 0x576D800ull
+#define NIC6_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400
+#define NIC6_MAC_CH1_MAC_AN_SECTION 0x8000
+#define mmNIC6_MAC_CH2_MAC_PCS_BASE 0x576E000ull
+#define NIC6_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC6_MAC_CH2_MAC_PCS_SECTION 0x4000
+#define mmNIC6_MAC_CH2_MAC_128_BASE 0x576E400ull
+#define NIC6_MAC_CH2_MAC_128_MAX_OFFSET 0xA400
+#define NIC6_MAC_CH2_MAC_128_SECTION 0x4000
+#define mmNIC6_MAC_CH2_MAC_AN_BASE 0x576E800ull
+#define NIC6_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400
+#define NIC6_MAC_CH2_MAC_AN_SECTION 0x8000
+#define mmNIC6_MAC_CH3_MAC_PCS_BASE 0x576F000ull
+#define NIC6_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC6_MAC_CH3_MAC_PCS_SECTION 0x4000
+#define mmNIC6_MAC_CH3_MAC_128_BASE 0x576F400ull
+#define NIC6_MAC_CH3_MAC_128_MAX_OFFSET 0xA400
+#define NIC6_MAC_CH3_MAC_128_SECTION 0x4000
+#define mmNIC6_MAC_CH3_MAC_AN_BASE 0x576F800ull
+#define NIC6_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400
+#define NIC6_MAC_CH3_MAC_AN_SECTION 0x10800
+#define mmNIC7_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5780000ull
+#define NIC7_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC7_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5780080ull
+#define NIC7_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC7_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5780100ull
+#define NIC7_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC7_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5780180ull
+#define NIC7_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC7_UMR0_0_SPECIAL_BASE 0x5780E80ull
+#define NIC7_UMR0_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR0_0_SPECIAL_SECTION 0x1800
+#define mmNIC7_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5781000ull
+#define NIC7_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC7_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5781080ull
+#define NIC7_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC7_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5781100ull
+#define NIC7_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC7_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5781180ull
+#define NIC7_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC7_UMR0_1_SPECIAL_BASE 0x5781E80ull
+#define NIC7_UMR0_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR0_1_SPECIAL_SECTION 0x1800
+#define mmNIC7_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5782000ull
+#define NIC7_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC7_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5782080ull
+#define NIC7_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC7_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5782100ull
+#define NIC7_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC7_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5782180ull
+#define NIC7_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC7_UMR0_2_SPECIAL_BASE 0x5782E80ull
+#define NIC7_UMR0_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR0_2_SPECIAL_SECTION 0x1800
+#define mmNIC7_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5783000ull
+#define NIC7_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC7_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5783080ull
+#define NIC7_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC7_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5783100ull
+#define NIC7_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC7_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5783180ull
+#define NIC7_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC7_UMR0_3_SPECIAL_BASE 0x5783E80ull
+#define NIC7_UMR0_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR0_3_SPECIAL_SECTION 0x1800
+#define mmNIC7_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5784000ull
+#define NIC7_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC7_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5784080ull
+#define NIC7_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC7_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5784100ull
+#define NIC7_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC7_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5784180ull
+#define NIC7_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC7_UMR0_4_SPECIAL_BASE 0x5784E80ull
+#define NIC7_UMR0_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR0_4_SPECIAL_SECTION 0x1800
+#define mmNIC7_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5785000ull
+#define NIC7_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC7_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5785080ull
+#define NIC7_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC7_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5785100ull
+#define NIC7_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC7_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5785180ull
+#define NIC7_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC7_UMR0_5_SPECIAL_BASE 0x5785E80ull
+#define NIC7_UMR0_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR0_5_SPECIAL_SECTION 0x1800
+#define mmNIC7_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5786000ull
+#define NIC7_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC7_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5786080ull
+#define NIC7_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC7_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5786100ull
+#define NIC7_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC7_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5786180ull
+#define NIC7_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC7_UMR0_6_SPECIAL_BASE 0x5786E80ull
+#define NIC7_UMR0_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR0_6_SPECIAL_SECTION 0x1800
+#define mmNIC7_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5787000ull
+#define NIC7_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC7_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5787080ull
+#define NIC7_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC7_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5787100ull
+#define NIC7_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC7_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5787180ull
+#define NIC7_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC7_UMR0_7_SPECIAL_BASE 0x5787E80ull
+#define NIC7_UMR0_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR0_7_SPECIAL_SECTION 0x1800
+#define mmNIC7_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5788000ull
+#define NIC7_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC7_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5788080ull
+#define NIC7_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC7_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5788100ull
+#define NIC7_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC7_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5788180ull
+#define NIC7_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC7_UMR0_8_SPECIAL_BASE 0x5788E80ull
+#define NIC7_UMR0_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR0_8_SPECIAL_SECTION 0x1800
+#define mmNIC7_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5789000ull
+#define NIC7_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC7_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5789080ull
+#define NIC7_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC7_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5789100ull
+#define NIC7_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC7_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5789180ull
+#define NIC7_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC7_UMR0_9_SPECIAL_BASE 0x5789E80ull
+#define NIC7_UMR0_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR0_9_SPECIAL_SECTION 0x1800
+#define mmNIC7_UMR0_10_UNSECURE_DOORBELL0_BASE 0x578A000ull
+#define NIC7_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC7_UMR0_10_UNSECURE_DOORBELL1_BASE 0x578A080ull
+#define NIC7_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC7_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x578A100ull
+#define NIC7_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC7_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x578A180ull
+#define NIC7_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC7_UMR0_10_SPECIAL_BASE 0x578AE80ull
+#define NIC7_UMR0_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR0_10_SPECIAL_SECTION 0x1800
+#define mmNIC7_UMR0_11_UNSECURE_DOORBELL0_BASE 0x578B000ull
+#define NIC7_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC7_UMR0_11_UNSECURE_DOORBELL1_BASE 0x578B080ull
+#define NIC7_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC7_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x578B100ull
+#define NIC7_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC7_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x578B180ull
+#define NIC7_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC7_UMR0_11_SPECIAL_BASE 0x578BE80ull
+#define NIC7_UMR0_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR0_11_SPECIAL_SECTION 0x1800
+#define mmNIC7_UMR0_12_UNSECURE_DOORBELL0_BASE 0x578C000ull
+#define NIC7_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC7_UMR0_12_UNSECURE_DOORBELL1_BASE 0x578C080ull
+#define NIC7_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC7_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x578C100ull
+#define NIC7_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC7_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x578C180ull
+#define NIC7_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC7_UMR0_12_SPECIAL_BASE 0x578CE80ull
+#define NIC7_UMR0_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR0_12_SPECIAL_SECTION 0x1800
+#define mmNIC7_UMR0_13_UNSECURE_DOORBELL0_BASE 0x578D000ull
+#define NIC7_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC7_UMR0_13_UNSECURE_DOORBELL1_BASE 0x578D080ull
+#define NIC7_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC7_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x578D100ull
+#define NIC7_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC7_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x578D180ull
+#define NIC7_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC7_UMR0_13_SPECIAL_BASE 0x578DE80ull
+#define NIC7_UMR0_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR0_13_SPECIAL_SECTION 0x1800
+#define mmNIC7_UMR0_14_UNSECURE_DOORBELL0_BASE 0x578E000ull
+#define NIC7_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC7_UMR0_14_UNSECURE_DOORBELL1_BASE 0x578E080ull
+#define NIC7_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC7_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x578E100ull
+#define NIC7_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC7_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x578E180ull
+#define NIC7_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC7_UMR0_14_SPECIAL_BASE 0x578EE80ull
+#define NIC7_UMR0_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR0_14_SPECIAL_SECTION 0x1180
+#define mmNIC7_QM_DCCM0_BASE 0x5790000ull
+#define NIC7_QM_DCCM0_MAX_OFFSET 0x4000
+#define NIC7_QM_DCCM0_SECTION 0x8000
+#define mmNIC7_QM_ARC_AUX0_BASE 0x5798000ull
+#define NIC7_QM_ARC_AUX0_MAX_OFFSET 0x1000
+#define NIC7_QM_ARC_AUX0_SECTION 0xE800
+#define mmNIC7_QM_ARC_AUX0_SPECIAL_BASE 0x5798E80ull
+#define NIC7_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_QM_ARC_AUX0_SPECIAL_SECTION 0x1180
+#define mmNIC7_QM0_BASE 0x579A000ull
+#define NIC7_QM0_MAX_OFFSET 0x1000
+#define NIC7_QM0_SECTION 0x9000
+#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x579A900ull
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x579A908ull
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x579A910ull
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x579A918ull
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x579A920ull
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x579A928ull
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x579A930ull
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x579A938ull
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x579A940ull
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x579A948ull
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x579A950ull
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x579A958ull
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x579A960ull
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x579A968ull
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x579A970ull
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x579A978ull
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC7_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmNIC7_QM0_AXUSER_SECURED_BASE 0x579AB00ull
+#define NIC7_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC7_QM0_AXUSER_SECURED_SECTION 0x8000
+#define mmNIC7_QM0_AXUSER_NONSECURED_BASE 0x579AB80ull
+#define NIC7_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC7_QM0_AXUSER_NONSECURED_SECTION 0x8000
+#define mmNIC7_QM0_DBG_HBW_BASE 0x579AC00ull
+#define NIC7_QM0_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC7_QM0_DBG_HBW_SECTION 0x8000
+#define mmNIC7_QM0_DBG_LBW_BASE 0x579AC80ull
+#define NIC7_QM0_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC7_QM0_DBG_LBW_SECTION 0x1000
+#define mmNIC7_QM0_CGM_BASE 0x579AD80ull
+#define NIC7_QM0_CGM_MAX_OFFSET 0xC000
+#define NIC7_QM0_CGM_SECTION 0x1000
+#define mmNIC7_QM0_SPECIAL_BASE 0x579AE80ull
+#define NIC7_QM0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_QM0_SPECIAL_SECTION 0x4180
+#define mmNIC7_QPC0_BASE 0x579F000ull
+#define NIC7_QPC0_MAX_OFFSET 0x1000
+#define NIC7_QPC0_SECTION 0x7200
+#define mmNIC7_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x579F720ull
+#define NIC7_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x579F728ull
+#define NIC7_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x579F730ull
+#define NIC7_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x579F738ull
+#define NIC7_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x579F740ull
+#define NIC7_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x579F748ull
+#define NIC7_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x579F750ull
+#define NIC7_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x579F758ull
+#define NIC7_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x579F760ull
+#define NIC7_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x579F768ull
+#define NIC7_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x579F770ull
+#define NIC7_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x579F778ull
+#define NIC7_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x579F780ull
+#define NIC7_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x579F788ull
+#define NIC7_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x579F790ull
+#define NIC7_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x579F798ull
+#define NIC7_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x579F7A0ull
+#define NIC7_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x579F7A8ull
+#define NIC7_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x579F7B0ull
+#define NIC7_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x579F7B8ull
+#define NIC7_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x579F7C0ull
+#define NIC7_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x579F7C8ull
+#define NIC7_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x579F7D0ull
+#define NIC7_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x579F7D8ull
+#define NIC7_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x579F7E0ull
+#define NIC7_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x579F7E8ull
+#define NIC7_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x579F7F0ull
+#define NIC7_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x579F7F8ull
+#define NIC7_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x579F800ull
+#define NIC7_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x579F808ull
+#define NIC7_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x579F810ull
+#define NIC7_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x579F818ull
+#define NIC7_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define mmNIC7_QPC0_AXUSER_CONG_QUE_BASE 0x579FB80ull
+#define NIC7_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC7_QPC0_AXUSER_CONG_QUE_SECTION 0x6000
+#define mmNIC7_QPC0_AXUSER_RXWQE_BASE 0x579FBE0ull
+#define NIC7_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC7_QPC0_AXUSER_RXWQE_SECTION 0x6000
+#define mmNIC7_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x579FC40ull
+#define NIC7_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC7_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define mmNIC7_QPC0_AXUSER_DB_FIFO_BASE 0x579FCA0ull
+#define NIC7_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC7_QPC0_AXUSER_DB_FIFO_SECTION 0x6000
+#define mmNIC7_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x579FD00ull
+#define NIC7_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC7_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define mmNIC7_QPC0_AXUSER_ERR_FIFO_BASE 0x579FD60ull
+#define NIC7_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC7_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000
+#define mmNIC7_QPC0_AXUSER_QPC_RESP_BASE 0x579FDC0ull
+#define NIC7_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC7_QPC0_AXUSER_QPC_RESP_SECTION 0x6000
+#define mmNIC7_QPC0_AXUSER_QPC_REQ_BASE 0x579FE20ull
+#define NIC7_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC7_QPC0_AXUSER_QPC_REQ_SECTION 0x6000
+#define mmNIC7_QPC0_SPECIAL_BASE 0x579FE80ull
+#define NIC7_QPC0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_QPC0_SPECIAL_SECTION 0x1800
+#define mmNIC7_UMR1_0_UNSECURE_DOORBELL0_BASE 0x57A0000ull
+#define NIC7_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC7_UMR1_0_UNSECURE_DOORBELL1_BASE 0x57A0080ull
+#define NIC7_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC7_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x57A0100ull
+#define NIC7_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC7_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x57A0180ull
+#define NIC7_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC7_UMR1_0_SPECIAL_BASE 0x57A0E80ull
+#define NIC7_UMR1_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR1_0_SPECIAL_SECTION 0x1800
+#define mmNIC7_UMR1_1_UNSECURE_DOORBELL0_BASE 0x57A1000ull
+#define NIC7_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC7_UMR1_1_UNSECURE_DOORBELL1_BASE 0x57A1080ull
+#define NIC7_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC7_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x57A1100ull
+#define NIC7_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC7_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x57A1180ull
+#define NIC7_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC7_UMR1_1_SPECIAL_BASE 0x57A1E80ull
+#define NIC7_UMR1_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR1_1_SPECIAL_SECTION 0x1800
+#define mmNIC7_UMR1_2_UNSECURE_DOORBELL0_BASE 0x57A2000ull
+#define NIC7_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC7_UMR1_2_UNSECURE_DOORBELL1_BASE 0x57A2080ull
+#define NIC7_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC7_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x57A2100ull
+#define NIC7_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC7_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x57A2180ull
+#define NIC7_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC7_UMR1_2_SPECIAL_BASE 0x57A2E80ull
+#define NIC7_UMR1_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR1_2_SPECIAL_SECTION 0x1800
+#define mmNIC7_UMR1_3_UNSECURE_DOORBELL0_BASE 0x57A3000ull
+#define NIC7_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC7_UMR1_3_UNSECURE_DOORBELL1_BASE 0x57A3080ull
+#define NIC7_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC7_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x57A3100ull
+#define NIC7_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC7_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x57A3180ull
+#define NIC7_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC7_UMR1_3_SPECIAL_BASE 0x57A3E80ull
+#define NIC7_UMR1_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR1_3_SPECIAL_SECTION 0x1800
+#define mmNIC7_UMR1_4_UNSECURE_DOORBELL0_BASE 0x57A4000ull
+#define NIC7_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC7_UMR1_4_UNSECURE_DOORBELL1_BASE 0x57A4080ull
+#define NIC7_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC7_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x57A4100ull
+#define NIC7_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC7_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x57A4180ull
+#define NIC7_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC7_UMR1_4_SPECIAL_BASE 0x57A4E80ull
+#define NIC7_UMR1_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR1_4_SPECIAL_SECTION 0x1800
+#define mmNIC7_UMR1_5_UNSECURE_DOORBELL0_BASE 0x57A5000ull
+#define NIC7_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC7_UMR1_5_UNSECURE_DOORBELL1_BASE 0x57A5080ull
+#define NIC7_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC7_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x57A5100ull
+#define NIC7_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC7_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x57A5180ull
+#define NIC7_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC7_UMR1_5_SPECIAL_BASE 0x57A5E80ull
+#define NIC7_UMR1_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR1_5_SPECIAL_SECTION 0x1800
+#define mmNIC7_UMR1_6_UNSECURE_DOORBELL0_BASE 0x57A6000ull
+#define NIC7_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC7_UMR1_6_UNSECURE_DOORBELL1_BASE 0x57A6080ull
+#define NIC7_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC7_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x57A6100ull
+#define NIC7_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC7_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x57A6180ull
+#define NIC7_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC7_UMR1_6_SPECIAL_BASE 0x57A6E80ull
+#define NIC7_UMR1_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR1_6_SPECIAL_SECTION 0x1800
+#define mmNIC7_UMR1_7_UNSECURE_DOORBELL0_BASE 0x57A7000ull
+#define NIC7_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC7_UMR1_7_UNSECURE_DOORBELL1_BASE 0x57A7080ull
+#define NIC7_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC7_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x57A7100ull
+#define NIC7_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC7_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x57A7180ull
+#define NIC7_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC7_UMR1_7_SPECIAL_BASE 0x57A7E80ull
+#define NIC7_UMR1_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR1_7_SPECIAL_SECTION 0x1800
+#define mmNIC7_UMR1_8_UNSECURE_DOORBELL0_BASE 0x57A8000ull
+#define NIC7_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC7_UMR1_8_UNSECURE_DOORBELL1_BASE 0x57A8080ull
+#define NIC7_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC7_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x57A8100ull
+#define NIC7_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC7_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x57A8180ull
+#define NIC7_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC7_UMR1_8_SPECIAL_BASE 0x57A8E80ull
+#define NIC7_UMR1_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR1_8_SPECIAL_SECTION 0x1800
+#define mmNIC7_UMR1_9_UNSECURE_DOORBELL0_BASE 0x57A9000ull
+#define NIC7_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC7_UMR1_9_UNSECURE_DOORBELL1_BASE 0x57A9080ull
+#define NIC7_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC7_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x57A9100ull
+#define NIC7_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC7_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x57A9180ull
+#define NIC7_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC7_UMR1_9_SPECIAL_BASE 0x57A9E80ull
+#define NIC7_UMR1_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR1_9_SPECIAL_SECTION 0x1800
+#define mmNIC7_UMR1_10_UNSECURE_DOORBELL0_BASE 0x57AA000ull
+#define NIC7_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC7_UMR1_10_UNSECURE_DOORBELL1_BASE 0x57AA080ull
+#define NIC7_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC7_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x57AA100ull
+#define NIC7_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC7_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x57AA180ull
+#define NIC7_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC7_UMR1_10_SPECIAL_BASE 0x57AAE80ull
+#define NIC7_UMR1_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR1_10_SPECIAL_SECTION 0x1800
+#define mmNIC7_UMR1_11_UNSECURE_DOORBELL0_BASE 0x57AB000ull
+#define NIC7_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC7_UMR1_11_UNSECURE_DOORBELL1_BASE 0x57AB080ull
+#define NIC7_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC7_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x57AB100ull
+#define NIC7_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC7_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x57AB180ull
+#define NIC7_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC7_UMR1_11_SPECIAL_BASE 0x57ABE80ull
+#define NIC7_UMR1_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR1_11_SPECIAL_SECTION 0x1800
+#define mmNIC7_UMR1_12_UNSECURE_DOORBELL0_BASE 0x57AC000ull
+#define NIC7_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC7_UMR1_12_UNSECURE_DOORBELL1_BASE 0x57AC080ull
+#define NIC7_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC7_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x57AC100ull
+#define NIC7_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC7_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x57AC180ull
+#define NIC7_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC7_UMR1_12_SPECIAL_BASE 0x57ACE80ull
+#define NIC7_UMR1_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR1_12_SPECIAL_SECTION 0x1800
+#define mmNIC7_UMR1_13_UNSECURE_DOORBELL0_BASE 0x57AD000ull
+#define NIC7_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC7_UMR1_13_UNSECURE_DOORBELL1_BASE 0x57AD080ull
+#define NIC7_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC7_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x57AD100ull
+#define NIC7_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC7_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x57AD180ull
+#define NIC7_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC7_UMR1_13_SPECIAL_BASE 0x57ADE80ull
+#define NIC7_UMR1_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR1_13_SPECIAL_SECTION 0x1800
+#define mmNIC7_UMR1_14_UNSECURE_DOORBELL0_BASE 0x57AE000ull
+#define NIC7_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC7_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC7_UMR1_14_UNSECURE_DOORBELL1_BASE 0x57AE080ull
+#define NIC7_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC7_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC7_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x57AE100ull
+#define NIC7_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC7_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC7_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x57AE180ull
+#define NIC7_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC7_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC7_UMR1_14_SPECIAL_BASE 0x57AEE80ull
+#define NIC7_UMR1_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_UMR1_14_SPECIAL_SECTION 0x1180
+#define mmNIC7_QM_DCCM1_BASE 0x57B0000ull
+#define NIC7_QM_DCCM1_MAX_OFFSET 0x4000
+#define NIC7_QM_DCCM1_SECTION 0x8000
+#define mmNIC7_QM_ARC_AUX1_BASE 0x57B8000ull
+#define NIC7_QM_ARC_AUX1_MAX_OFFSET 0x1000
+#define NIC7_QM_ARC_AUX1_SECTION 0xE800
+#define mmNIC7_QM_ARC_AUX1_SPECIAL_BASE 0x57B8E80ull
+#define NIC7_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_QM_ARC_AUX1_SPECIAL_SECTION 0x1180
+#define mmNIC7_QM1_BASE 0x57BA000ull
+#define NIC7_QM1_MAX_OFFSET 0x1000
+#define NIC7_QM1_SECTION 0x9000
+#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x57BA900ull
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x57BA908ull
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x57BA910ull
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x57BA918ull
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x57BA920ull
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x57BA928ull
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x57BA930ull
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x57BA938ull
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x57BA940ull
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x57BA948ull
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x57BA950ull
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x57BA958ull
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x57BA960ull
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x57BA968ull
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x57BA970ull
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x57BA978ull
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC7_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmNIC7_QM1_AXUSER_SECURED_BASE 0x57BAB00ull
+#define NIC7_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC7_QM1_AXUSER_SECURED_SECTION 0x8000
+#define mmNIC7_QM1_AXUSER_NONSECURED_BASE 0x57BAB80ull
+#define NIC7_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC7_QM1_AXUSER_NONSECURED_SECTION 0x8000
+#define mmNIC7_QM1_DBG_HBW_BASE 0x57BAC00ull
+#define NIC7_QM1_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC7_QM1_DBG_HBW_SECTION 0x8000
+#define mmNIC7_QM1_DBG_LBW_BASE 0x57BAC80ull
+#define NIC7_QM1_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC7_QM1_DBG_LBW_SECTION 0x1000
+#define mmNIC7_QM1_CGM_BASE 0x57BAD80ull
+#define NIC7_QM1_CGM_MAX_OFFSET 0xC000
+#define NIC7_QM1_CGM_SECTION 0x1000
+#define mmNIC7_QM1_SPECIAL_BASE 0x57BAE80ull
+#define NIC7_QM1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_QM1_SPECIAL_SECTION 0x4180
+#define mmNIC7_QPC1_BASE 0x57BF000ull
+#define NIC7_QPC1_MAX_OFFSET 0x1000
+#define NIC7_QPC1_SECTION 0x7200
+#define mmNIC7_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x57BF720ull
+#define NIC7_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x57BF728ull
+#define NIC7_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x57BF730ull
+#define NIC7_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x57BF738ull
+#define NIC7_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x57BF740ull
+#define NIC7_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x57BF748ull
+#define NIC7_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x57BF750ull
+#define NIC7_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x57BF758ull
+#define NIC7_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x57BF760ull
+#define NIC7_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x57BF768ull
+#define NIC7_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x57BF770ull
+#define NIC7_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x57BF778ull
+#define NIC7_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x57BF780ull
+#define NIC7_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x57BF788ull
+#define NIC7_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x57BF790ull
+#define NIC7_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x57BF798ull
+#define NIC7_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x57BF7A0ull
+#define NIC7_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x57BF7A8ull
+#define NIC7_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x57BF7B0ull
+#define NIC7_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x57BF7B8ull
+#define NIC7_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x57BF7C0ull
+#define NIC7_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x57BF7C8ull
+#define NIC7_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x57BF7D0ull
+#define NIC7_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x57BF7D8ull
+#define NIC7_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x57BF7E0ull
+#define NIC7_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x57BF7E8ull
+#define NIC7_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x57BF7F0ull
+#define NIC7_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x57BF7F8ull
+#define NIC7_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x57BF800ull
+#define NIC7_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x57BF808ull
+#define NIC7_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x57BF810ull
+#define NIC7_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC7_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x57BF818ull
+#define NIC7_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC7_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define mmNIC7_QPC1_AXUSER_CONG_QUE_BASE 0x57BFB80ull
+#define NIC7_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC7_QPC1_AXUSER_CONG_QUE_SECTION 0x6000
+#define mmNIC7_QPC1_AXUSER_RXWQE_BASE 0x57BFBE0ull
+#define NIC7_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC7_QPC1_AXUSER_RXWQE_SECTION 0x6000
+#define mmNIC7_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x57BFC40ull
+#define NIC7_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC7_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define mmNIC7_QPC1_AXUSER_DB_FIFO_BASE 0x57BFCA0ull
+#define NIC7_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC7_QPC1_AXUSER_DB_FIFO_SECTION 0x6000
+#define mmNIC7_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x57BFD00ull
+#define NIC7_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC7_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define mmNIC7_QPC1_AXUSER_ERR_FIFO_BASE 0x57BFD60ull
+#define NIC7_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC7_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000
+#define mmNIC7_QPC1_AXUSER_QPC_RESP_BASE 0x57BFDC0ull
+#define NIC7_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC7_QPC1_AXUSER_QPC_RESP_SECTION 0x6000
+#define mmNIC7_QPC1_AXUSER_QPC_REQ_BASE 0x57BFE20ull
+#define NIC7_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC7_QPC1_AXUSER_QPC_REQ_SECTION 0x6000
+#define mmNIC7_QPC1_SPECIAL_BASE 0x57BFE80ull
+#define NIC7_QPC1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_QPC1_SPECIAL_SECTION 0x8180
+#define mmNIC7_TMR_BASE 0x57C8000ull
+#define NIC7_TMR_MAX_OFFSET 0x1000
+#define NIC7_TMR_SECTION 0xD600
+#define mmNIC7_TMR_AXUSER_TMR_FREE_LIST_BASE 0x57C8D60ull
+#define NIC7_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000
+#define NIC7_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000
+#define mmNIC7_TMR_AXUSER_TMR_FIFO_BASE 0x57C8DC0ull
+#define NIC7_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000
+#define NIC7_TMR_AXUSER_TMR_FIFO_SECTION 0x6000
+#define mmNIC7_TMR_AXUSER_TMR_FSM_BASE 0x57C8E20ull
+#define NIC7_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000
+#define NIC7_TMR_AXUSER_TMR_FSM_SECTION 0x6000
+#define mmNIC7_TMR_SPECIAL_BASE 0x57C8E80ull
+#define NIC7_TMR_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_TMR_SPECIAL_SECTION 0x1800
+#define mmNIC7_RXB_CORE_BASE 0x57C9000ull
+#define NIC7_RXB_CORE_MAX_OFFSET 0x1000
+#define NIC7_RXB_CORE_SECTION 0x6100
+#define mmNIC7_RXB_CORE_SCT_AWUSER_BASE 0x57C9610ull
+#define NIC7_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000
+#define NIC7_RXB_CORE_SCT_AWUSER_SECTION 0x8700
+#define mmNIC7_RXB_CORE_SPECIAL_BASE 0x57C9E80ull
+#define NIC7_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_RXB_CORE_SPECIAL_SECTION 0x1800
+#define mmNIC7_RXE0_BASE 0x57CA000ull
+#define NIC7_RXE0_MAX_OFFSET 0x1000
+#define NIC7_RXE0_SECTION 0x9000
+#define mmNIC7_RXE0_WQE_ARUSER_BASE 0x57CA900ull
+#define NIC7_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC7_RXE0_WQE_ARUSER_SECTION 0x5800
+#define mmNIC7_RXE0_SPECIAL_BASE 0x57CAE80ull
+#define NIC7_RXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_RXE0_SPECIAL_SECTION 0x1800
+#define mmNIC7_RXE1_BASE 0x57CB000ull
+#define NIC7_RXE1_MAX_OFFSET 0x1000
+#define NIC7_RXE1_SECTION 0x9000
+#define mmNIC7_RXE1_WQE_ARUSER_BASE 0x57CB900ull
+#define NIC7_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC7_RXE1_WQE_ARUSER_SECTION 0x5800
+#define mmNIC7_RXE1_SPECIAL_BASE 0x57CBE80ull
+#define NIC7_RXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_RXE1_SPECIAL_SECTION 0x1800
+#define mmNIC7_RXE0_AXUSER_AXUSER_CQ0_BASE 0x57CC000ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define mmNIC7_RXE0_AXUSER_AXUSER_CQ1_BASE 0x57CC050ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define mmNIC7_RXE0_AXUSER_AXUSER_CQ2_BASE 0x57CC0A0ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define mmNIC7_RXE0_AXUSER_AXUSER_CQ3_BASE 0x57CC0F0ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define mmNIC7_RXE0_AXUSER_AXUSER_CQ4_BASE 0x57CC140ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define mmNIC7_RXE0_AXUSER_AXUSER_CQ5_BASE 0x57CC190ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define mmNIC7_RXE0_AXUSER_AXUSER_CQ6_BASE 0x57CC1E0ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define mmNIC7_RXE0_AXUSER_AXUSER_CQ7_BASE 0x57CC230ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define mmNIC7_RXE0_AXUSER_AXUSER_CQ8_BASE 0x57CC280ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define mmNIC7_RXE0_AXUSER_AXUSER_CQ9_BASE 0x57CC2D0ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define mmNIC7_RXE0_AXUSER_AXUSER_CQ10_BASE 0x57CC320ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define mmNIC7_RXE0_AXUSER_AXUSER_CQ11_BASE 0x57CC370ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define mmNIC7_RXE0_AXUSER_AXUSER_CQ12_BASE 0x57CC3C0ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define mmNIC7_RXE0_AXUSER_AXUSER_CQ13_BASE 0x57CC410ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define mmNIC7_RXE0_AXUSER_AXUSER_CQ14_BASE 0x57CC460ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define mmNIC7_RXE0_AXUSER_AXUSER_CQ15_BASE 0x57CC4B0ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define mmNIC7_RXE0_AXUSER_AXUSER_CQ16_BASE 0x57CC500ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define mmNIC7_RXE0_AXUSER_AXUSER_CQ17_BASE 0x57CC550ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define mmNIC7_RXE0_AXUSER_AXUSER_CQ18_BASE 0x57CC5A0ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define mmNIC7_RXE0_AXUSER_AXUSER_CQ19_BASE 0x57CC5F0ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define mmNIC7_RXE0_AXUSER_AXUSER_CQ20_BASE 0x57CC640ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define mmNIC7_RXE0_AXUSER_AXUSER_CQ21_BASE 0x57CC690ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define mmNIC7_RXE0_AXUSER_AXUSER_CQ22_BASE 0x57CC6E0ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define mmNIC7_RXE0_AXUSER_AXUSER_CQ23_BASE 0x57CC730ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define mmNIC7_RXE0_AXUSER_AXUSER_CQ24_BASE 0x57CC780ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define mmNIC7_RXE0_AXUSER_AXUSER_CQ25_BASE 0x57CC7D0ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define mmNIC7_RXE0_AXUSER_AXUSER_CQ26_BASE 0x57CC820ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define mmNIC7_RXE0_AXUSER_AXUSER_CQ27_BASE 0x57CC870ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define mmNIC7_RXE0_AXUSER_AXUSER_CQ28_BASE 0x57CC8C0ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define mmNIC7_RXE0_AXUSER_AXUSER_CQ29_BASE 0x57CC910ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define mmNIC7_RXE0_AXUSER_AXUSER_CQ30_BASE 0x57CC960ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define mmNIC7_RXE0_AXUSER_AXUSER_CQ31_BASE 0x57CC9B0ull
+#define NIC7_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC7_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define mmNIC7_RXE0_AXUSER_SPECIAL_BASE 0x57CCE80ull
+#define NIC7_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_RXE0_AXUSER_SPECIAL_SECTION 0x1800
+#define mmNIC7_RXE1_AXUSER_AXUSER_CQ0_BASE 0x57CD000ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define mmNIC7_RXE1_AXUSER_AXUSER_CQ1_BASE 0x57CD050ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define mmNIC7_RXE1_AXUSER_AXUSER_CQ2_BASE 0x57CD0A0ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define mmNIC7_RXE1_AXUSER_AXUSER_CQ3_BASE 0x57CD0F0ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define mmNIC7_RXE1_AXUSER_AXUSER_CQ4_BASE 0x57CD140ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define mmNIC7_RXE1_AXUSER_AXUSER_CQ5_BASE 0x57CD190ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define mmNIC7_RXE1_AXUSER_AXUSER_CQ6_BASE 0x57CD1E0ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define mmNIC7_RXE1_AXUSER_AXUSER_CQ7_BASE 0x57CD230ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define mmNIC7_RXE1_AXUSER_AXUSER_CQ8_BASE 0x57CD280ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define mmNIC7_RXE1_AXUSER_AXUSER_CQ9_BASE 0x57CD2D0ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define mmNIC7_RXE1_AXUSER_AXUSER_CQ10_BASE 0x57CD320ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define mmNIC7_RXE1_AXUSER_AXUSER_CQ11_BASE 0x57CD370ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define mmNIC7_RXE1_AXUSER_AXUSER_CQ12_BASE 0x57CD3C0ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define mmNIC7_RXE1_AXUSER_AXUSER_CQ13_BASE 0x57CD410ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define mmNIC7_RXE1_AXUSER_AXUSER_CQ14_BASE 0x57CD460ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define mmNIC7_RXE1_AXUSER_AXUSER_CQ15_BASE 0x57CD4B0ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define mmNIC7_RXE1_AXUSER_AXUSER_CQ16_BASE 0x57CD500ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define mmNIC7_RXE1_AXUSER_AXUSER_CQ17_BASE 0x57CD550ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define mmNIC7_RXE1_AXUSER_AXUSER_CQ18_BASE 0x57CD5A0ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define mmNIC7_RXE1_AXUSER_AXUSER_CQ19_BASE 0x57CD5F0ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define mmNIC7_RXE1_AXUSER_AXUSER_CQ20_BASE 0x57CD640ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define mmNIC7_RXE1_AXUSER_AXUSER_CQ21_BASE 0x57CD690ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define mmNIC7_RXE1_AXUSER_AXUSER_CQ22_BASE 0x57CD6E0ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define mmNIC7_RXE1_AXUSER_AXUSER_CQ23_BASE 0x57CD730ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define mmNIC7_RXE1_AXUSER_AXUSER_CQ24_BASE 0x57CD780ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define mmNIC7_RXE1_AXUSER_AXUSER_CQ25_BASE 0x57CD7D0ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define mmNIC7_RXE1_AXUSER_AXUSER_CQ26_BASE 0x57CD820ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define mmNIC7_RXE1_AXUSER_AXUSER_CQ27_BASE 0x57CD870ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define mmNIC7_RXE1_AXUSER_AXUSER_CQ28_BASE 0x57CD8C0ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define mmNIC7_RXE1_AXUSER_AXUSER_CQ29_BASE 0x57CD910ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define mmNIC7_RXE1_AXUSER_AXUSER_CQ30_BASE 0x57CD960ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define mmNIC7_RXE1_AXUSER_AXUSER_CQ31_BASE 0x57CD9B0ull
+#define NIC7_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC7_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define mmNIC7_RXE1_AXUSER_SPECIAL_BASE 0x57CDE80ull
+#define NIC7_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_RXE1_AXUSER_SPECIAL_SECTION 0x2180
+#define mmNIC7_TXS0_BASE 0x57D0000ull
+#define NIC7_TXS0_MAX_OFFSET 0x1000
+#define NIC7_TXS0_SECTION 0xE800
+#define mmNIC7_TXS0_SPECIAL_BASE 0x57D0E80ull
+#define NIC7_TXS0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_TXS0_SPECIAL_SECTION 0x1800
+#define mmNIC7_TXS1_BASE 0x57D1000ull
+#define NIC7_TXS1_MAX_OFFSET 0x1000
+#define NIC7_TXS1_SECTION 0xE800
+#define mmNIC7_TXS1_SPECIAL_BASE 0x57D1E80ull
+#define NIC7_TXS1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_TXS1_SPECIAL_SECTION 0x1800
+#define mmNIC7_TXE0_BASE 0x57D2000ull
+#define NIC7_TXE0_MAX_OFFSET 0x1000
+#define NIC7_TXE0_SECTION 0xE800
+#define mmNIC7_TXE0_SPECIAL_BASE 0x57D2E80ull
+#define NIC7_TXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_TXE0_SPECIAL_SECTION 0x1800
+#define mmNIC7_TXE1_BASE 0x57D3000ull
+#define NIC7_TXE1_MAX_OFFSET 0x1000
+#define NIC7_TXE1_SECTION 0xE800
+#define mmNIC7_TXE1_SPECIAL_BASE 0x57D3E80ull
+#define NIC7_TXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_TXE1_SPECIAL_SECTION 0x1800
+#define mmNIC7_TXB_BASE 0x57D4000ull
+#define NIC7_TXB_MAX_OFFSET 0x1000
+#define NIC7_TXB_SECTION 0xE800
+#define mmNIC7_TXB_SPECIAL_BASE 0x57D4E80ull
+#define NIC7_TXB_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_TXB_SPECIAL_SECTION 0x1800
+#define mmNIC7_MSTR_IF_RR_SHRD_HBW_BASE 0x57D5000ull
+#define NIC7_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define NIC7_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmNIC7_MSTR_IF_RR_PRVT_HBW_BASE 0x57D5200ull
+#define NIC7_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define NIC7_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmNIC7_MSTR_IF_RR_SHRD_LBW_BASE 0x57D5400ull
+#define NIC7_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define NIC7_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmNIC7_MSTR_IF_RR_PRVT_LBW_BASE 0x57D5600ull
+#define NIC7_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define NIC7_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmNIC7_MSTR_IF_E2E_CRDT_BASE 0x57D5800ull
+#define NIC7_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define NIC7_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmNIC7_MSTR_IF_AXUSER_BASE 0x57D5A80ull
+#define NIC7_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define NIC7_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmNIC7_MSTR_IF_DBG_HBW_BASE 0x57D5B00ull
+#define NIC7_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC7_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmNIC7_MSTR_IF_DBG_LBW_BASE 0x57D5B80ull
+#define NIC7_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC7_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmNIC7_MSTR_IF_CORE_HBW_BASE 0x57D5C00ull
+#define NIC7_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define NIC7_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmNIC7_MSTR_IF_CORE_LBW_BASE 0x57D5D80ull
+#define NIC7_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define NIC7_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmNIC7_MSTR_IF_SPECIAL_BASE 0x57D5E80ull
+#define NIC7_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmNIC7_TX_AXUSER_BASE 0x57D6000ull
+#define NIC7_TX_AXUSER_MAX_OFFSET 0x5000
+#define NIC7_TX_AXUSER_SECTION 0x2000
+#define mmNIC7_SERDES0_BASE 0x57D8000ull
+#define NIC7_SERDES0_MAX_OFFSET 0x3E40
+#define NIC7_SERDES0_SECTION 0x4000
+#define mmNIC7_SERDES1_BASE 0x57DC000ull
+#define NIC7_SERDES1_MAX_OFFSET 0x3E40
+#define NIC7_SERDES1_SECTION 0x4000
+#define mmNIC7_PHY_BASE 0x57E0000ull
+#define NIC7_PHY_MAX_OFFSET 0x1000
+#define NIC7_PHY_SECTION 0xE800
+#define mmNIC7_PHY_SPECIAL_BASE 0x57E0E80ull
+#define NIC7_PHY_SPECIAL_MAX_OFFSET 0x1800
+#define NIC7_PHY_SPECIAL_SECTION 0x7180
+#define mmPRT7_MAC_AUX_BASE 0x57E8000ull
+#define PRT7_MAC_AUX_MAX_OFFSET 0x1000
+#define PRT7_MAC_AUX_SECTION 0xE800
+#define mmPRT7_MAC_AUX_SPECIAL_BASE 0x57E8E80ull
+#define PRT7_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define PRT7_MAC_AUX_SPECIAL_SECTION 0x1800
+#define mmPRT7_MAC_CORE_BASE 0x57E9000ull
+#define PRT7_MAC_CORE_MAX_OFFSET 0x1000
+#define PRT7_MAC_CORE_SECTION 0xE800
+#define mmPRT7_MAC_CORE_SPECIAL_BASE 0x57E9E80ull
+#define PRT7_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define PRT7_MAC_CORE_SPECIAL_SECTION 0x1800
+#define mmNIC7_MAC_RS_FEC_BASE 0x57EA000ull
+#define NIC7_MAC_RS_FEC_MAX_OFFSET 0x2DC0
+#define NIC7_MAC_RS_FEC_SECTION 0x1000
+#define mmNIC7_MAC_GLOB_STAT_CONTROL_REG_BASE 0x57EB000ull
+#define NIC7_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000
+#define NIC7_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000
+#define mmNIC7_MAC_GLOB_STAT_RX0_BASE 0x57EB100ull
+#define NIC7_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00
+#define NIC7_MAC_GLOB_STAT_RX0_SECTION 0x8C00
+#define mmNIC7_MAC_GLOB_STAT_RX1_BASE 0x57EB18Cull
+#define NIC7_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00
+#define NIC7_MAC_GLOB_STAT_RX1_SECTION 0x8C00
+#define mmNIC7_MAC_GLOB_STAT_RX2_BASE 0x57EB218ull
+#define NIC7_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00
+#define NIC7_MAC_GLOB_STAT_RX2_SECTION 0x8C00
+#define mmNIC7_MAC_GLOB_STAT_RX3_BASE 0x57EB2A4ull
+#define NIC7_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00
+#define NIC7_MAC_GLOB_STAT_RX3_SECTION 0x8C00
+#define mmNIC7_MAC_GLOB_STAT_TX0_BASE 0x57EB330ull
+#define NIC7_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800
+#define NIC7_MAC_GLOB_STAT_TX0_SECTION 0x6800
+#define mmNIC7_MAC_GLOB_STAT_TX1_BASE 0x57EB398ull
+#define NIC7_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800
+#define NIC7_MAC_GLOB_STAT_TX1_SECTION 0x6800
+#define mmNIC7_MAC_GLOB_STAT_TX2_BASE 0x57EB400ull
+#define NIC7_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800
+#define NIC7_MAC_GLOB_STAT_TX2_SECTION 0x6800
+#define mmNIC7_MAC_GLOB_STAT_TX3_BASE 0x57EB468ull
+#define NIC7_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800
+#define NIC7_MAC_GLOB_STAT_TX3_SECTION 0x3980
+#define mmNIC7_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x57EB800ull
+#define NIC7_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0
+#define NIC7_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000
+#define mmNIC7_MAC_CH0_MAC_PCS_BASE 0x57EC000ull
+#define NIC7_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC7_MAC_CH0_MAC_PCS_SECTION 0x4000
+#define mmNIC7_MAC_CH0_MAC_128_BASE 0x57EC400ull
+#define NIC7_MAC_CH0_MAC_128_MAX_OFFSET 0xA400
+#define NIC7_MAC_CH0_MAC_128_SECTION 0x4000
+#define mmNIC7_MAC_CH0_MAC_AN_BASE 0x57EC800ull
+#define NIC7_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400
+#define NIC7_MAC_CH0_MAC_AN_SECTION 0x8000
+#define mmNIC7_MAC_CH1_MAC_PCS_BASE 0x57ED000ull
+#define NIC7_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC7_MAC_CH1_MAC_PCS_SECTION 0x4000
+#define mmNIC7_MAC_CH1_MAC_128_BASE 0x57ED400ull
+#define NIC7_MAC_CH1_MAC_128_MAX_OFFSET 0xA400
+#define NIC7_MAC_CH1_MAC_128_SECTION 0x4000
+#define mmNIC7_MAC_CH1_MAC_AN_BASE 0x57ED800ull
+#define NIC7_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400
+#define NIC7_MAC_CH1_MAC_AN_SECTION 0x8000
+#define mmNIC7_MAC_CH2_MAC_PCS_BASE 0x57EE000ull
+#define NIC7_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC7_MAC_CH2_MAC_PCS_SECTION 0x4000
+#define mmNIC7_MAC_CH2_MAC_128_BASE 0x57EE400ull
+#define NIC7_MAC_CH2_MAC_128_MAX_OFFSET 0xA400
+#define NIC7_MAC_CH2_MAC_128_SECTION 0x4000
+#define mmNIC7_MAC_CH2_MAC_AN_BASE 0x57EE800ull
+#define NIC7_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400
+#define NIC7_MAC_CH2_MAC_AN_SECTION 0x8000
+#define mmNIC7_MAC_CH3_MAC_PCS_BASE 0x57EF000ull
+#define NIC7_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC7_MAC_CH3_MAC_PCS_SECTION 0x4000
+#define mmNIC7_MAC_CH3_MAC_128_BASE 0x57EF400ull
+#define NIC7_MAC_CH3_MAC_128_MAX_OFFSET 0xA400
+#define NIC7_MAC_CH3_MAC_128_SECTION 0x4000
+#define mmNIC7_MAC_CH3_MAC_AN_BASE 0x57EF800ull
+#define NIC7_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400
+#define NIC7_MAC_CH3_MAC_AN_SECTION 0x10800
+#define mmNIC8_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5800000ull
+#define NIC8_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC8_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5800080ull
+#define NIC8_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC8_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5800100ull
+#define NIC8_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC8_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5800180ull
+#define NIC8_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC8_UMR0_0_SPECIAL_BASE 0x5800E80ull
+#define NIC8_UMR0_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR0_0_SPECIAL_SECTION 0x1800
+#define mmNIC8_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5801000ull
+#define NIC8_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC8_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5801080ull
+#define NIC8_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC8_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5801100ull
+#define NIC8_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC8_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5801180ull
+#define NIC8_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC8_UMR0_1_SPECIAL_BASE 0x5801E80ull
+#define NIC8_UMR0_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR0_1_SPECIAL_SECTION 0x1800
+#define mmNIC8_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5802000ull
+#define NIC8_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC8_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5802080ull
+#define NIC8_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC8_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5802100ull
+#define NIC8_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC8_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5802180ull
+#define NIC8_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC8_UMR0_2_SPECIAL_BASE 0x5802E80ull
+#define NIC8_UMR0_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR0_2_SPECIAL_SECTION 0x1800
+#define mmNIC8_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5803000ull
+#define NIC8_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC8_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5803080ull
+#define NIC8_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC8_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5803100ull
+#define NIC8_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC8_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5803180ull
+#define NIC8_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC8_UMR0_3_SPECIAL_BASE 0x5803E80ull
+#define NIC8_UMR0_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR0_3_SPECIAL_SECTION 0x1800
+#define mmNIC8_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5804000ull
+#define NIC8_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC8_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5804080ull
+#define NIC8_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC8_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5804100ull
+#define NIC8_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC8_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5804180ull
+#define NIC8_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC8_UMR0_4_SPECIAL_BASE 0x5804E80ull
+#define NIC8_UMR0_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR0_4_SPECIAL_SECTION 0x1800
+#define mmNIC8_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5805000ull
+#define NIC8_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC8_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5805080ull
+#define NIC8_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC8_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5805100ull
+#define NIC8_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC8_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5805180ull
+#define NIC8_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC8_UMR0_5_SPECIAL_BASE 0x5805E80ull
+#define NIC8_UMR0_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR0_5_SPECIAL_SECTION 0x1800
+#define mmNIC8_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5806000ull
+#define NIC8_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC8_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5806080ull
+#define NIC8_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC8_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5806100ull
+#define NIC8_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC8_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5806180ull
+#define NIC8_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC8_UMR0_6_SPECIAL_BASE 0x5806E80ull
+#define NIC8_UMR0_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR0_6_SPECIAL_SECTION 0x1800
+#define mmNIC8_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5807000ull
+#define NIC8_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC8_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5807080ull
+#define NIC8_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC8_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5807100ull
+#define NIC8_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC8_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5807180ull
+#define NIC8_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC8_UMR0_7_SPECIAL_BASE 0x5807E80ull
+#define NIC8_UMR0_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR0_7_SPECIAL_SECTION 0x1800
+#define mmNIC8_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5808000ull
+#define NIC8_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC8_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5808080ull
+#define NIC8_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC8_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5808100ull
+#define NIC8_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC8_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5808180ull
+#define NIC8_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC8_UMR0_8_SPECIAL_BASE 0x5808E80ull
+#define NIC8_UMR0_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR0_8_SPECIAL_SECTION 0x1800
+#define mmNIC8_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5809000ull
+#define NIC8_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC8_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5809080ull
+#define NIC8_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC8_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5809100ull
+#define NIC8_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC8_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5809180ull
+#define NIC8_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC8_UMR0_9_SPECIAL_BASE 0x5809E80ull
+#define NIC8_UMR0_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR0_9_SPECIAL_SECTION 0x1800
+#define mmNIC8_UMR0_10_UNSECURE_DOORBELL0_BASE 0x580A000ull
+#define NIC8_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC8_UMR0_10_UNSECURE_DOORBELL1_BASE 0x580A080ull
+#define NIC8_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC8_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x580A100ull
+#define NIC8_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC8_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x580A180ull
+#define NIC8_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC8_UMR0_10_SPECIAL_BASE 0x580AE80ull
+#define NIC8_UMR0_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR0_10_SPECIAL_SECTION 0x1800
+#define mmNIC8_UMR0_11_UNSECURE_DOORBELL0_BASE 0x580B000ull
+#define NIC8_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC8_UMR0_11_UNSECURE_DOORBELL1_BASE 0x580B080ull
+#define NIC8_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC8_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x580B100ull
+#define NIC8_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC8_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x580B180ull
+#define NIC8_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC8_UMR0_11_SPECIAL_BASE 0x580BE80ull
+#define NIC8_UMR0_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR0_11_SPECIAL_SECTION 0x1800
+#define mmNIC8_UMR0_12_UNSECURE_DOORBELL0_BASE 0x580C000ull
+#define NIC8_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC8_UMR0_12_UNSECURE_DOORBELL1_BASE 0x580C080ull
+#define NIC8_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC8_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x580C100ull
+#define NIC8_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC8_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x580C180ull
+#define NIC8_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC8_UMR0_12_SPECIAL_BASE 0x580CE80ull
+#define NIC8_UMR0_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR0_12_SPECIAL_SECTION 0x1800
+#define mmNIC8_UMR0_13_UNSECURE_DOORBELL0_BASE 0x580D000ull
+#define NIC8_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC8_UMR0_13_UNSECURE_DOORBELL1_BASE 0x580D080ull
+#define NIC8_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC8_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x580D100ull
+#define NIC8_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC8_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x580D180ull
+#define NIC8_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC8_UMR0_13_SPECIAL_BASE 0x580DE80ull
+#define NIC8_UMR0_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR0_13_SPECIAL_SECTION 0x1800
+#define mmNIC8_UMR0_14_UNSECURE_DOORBELL0_BASE 0x580E000ull
+#define NIC8_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC8_UMR0_14_UNSECURE_DOORBELL1_BASE 0x580E080ull
+#define NIC8_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC8_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x580E100ull
+#define NIC8_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC8_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x580E180ull
+#define NIC8_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC8_UMR0_14_SPECIAL_BASE 0x580EE80ull
+#define NIC8_UMR0_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR0_14_SPECIAL_SECTION 0x1180
+#define mmNIC8_QM_DCCM0_BASE 0x5810000ull
+#define NIC8_QM_DCCM0_MAX_OFFSET 0x4000
+#define NIC8_QM_DCCM0_SECTION 0x8000
+#define mmNIC8_QM_ARC_AUX0_BASE 0x5818000ull
+#define NIC8_QM_ARC_AUX0_MAX_OFFSET 0x1000
+#define NIC8_QM_ARC_AUX0_SECTION 0xE800
+#define mmNIC8_QM_ARC_AUX0_SPECIAL_BASE 0x5818E80ull
+#define NIC8_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_QM_ARC_AUX0_SPECIAL_SECTION 0x1180
+#define mmNIC8_QM0_BASE 0x581A000ull
+#define NIC8_QM0_MAX_OFFSET 0x1000
+#define NIC8_QM0_SECTION 0x9000
+#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x581A900ull
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x581A908ull
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x581A910ull
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x581A918ull
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x581A920ull
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x581A928ull
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x581A930ull
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x581A938ull
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x581A940ull
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x581A948ull
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x581A950ull
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x581A958ull
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x581A960ull
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x581A968ull
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x581A970ull
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x581A978ull
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC8_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmNIC8_QM0_AXUSER_SECURED_BASE 0x581AB00ull
+#define NIC8_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC8_QM0_AXUSER_SECURED_SECTION 0x8000
+#define mmNIC8_QM0_AXUSER_NONSECURED_BASE 0x581AB80ull
+#define NIC8_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC8_QM0_AXUSER_NONSECURED_SECTION 0x8000
+#define mmNIC8_QM0_DBG_HBW_BASE 0x581AC00ull
+#define NIC8_QM0_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC8_QM0_DBG_HBW_SECTION 0x8000
+#define mmNIC8_QM0_DBG_LBW_BASE 0x581AC80ull
+#define NIC8_QM0_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC8_QM0_DBG_LBW_SECTION 0x1000
+#define mmNIC8_QM0_CGM_BASE 0x581AD80ull
+#define NIC8_QM0_CGM_MAX_OFFSET 0xC000
+#define NIC8_QM0_CGM_SECTION 0x1000
+#define mmNIC8_QM0_SPECIAL_BASE 0x581AE80ull
+#define NIC8_QM0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_QM0_SPECIAL_SECTION 0x4180
+#define mmNIC8_QPC0_BASE 0x581F000ull
+#define NIC8_QPC0_MAX_OFFSET 0x1000
+#define NIC8_QPC0_SECTION 0x7200
+#define mmNIC8_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x581F720ull
+#define NIC8_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x581F728ull
+#define NIC8_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x581F730ull
+#define NIC8_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x581F738ull
+#define NIC8_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x581F740ull
+#define NIC8_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x581F748ull
+#define NIC8_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x581F750ull
+#define NIC8_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x581F758ull
+#define NIC8_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x581F760ull
+#define NIC8_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x581F768ull
+#define NIC8_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x581F770ull
+#define NIC8_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x581F778ull
+#define NIC8_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x581F780ull
+#define NIC8_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x581F788ull
+#define NIC8_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x581F790ull
+#define NIC8_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x581F798ull
+#define NIC8_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x581F7A0ull
+#define NIC8_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x581F7A8ull
+#define NIC8_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x581F7B0ull
+#define NIC8_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x581F7B8ull
+#define NIC8_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x581F7C0ull
+#define NIC8_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x581F7C8ull
+#define NIC8_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x581F7D0ull
+#define NIC8_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x581F7D8ull
+#define NIC8_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x581F7E0ull
+#define NIC8_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x581F7E8ull
+#define NIC8_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x581F7F0ull
+#define NIC8_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x581F7F8ull
+#define NIC8_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x581F800ull
+#define NIC8_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x581F808ull
+#define NIC8_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x581F810ull
+#define NIC8_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x581F818ull
+#define NIC8_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define mmNIC8_QPC0_AXUSER_CONG_QUE_BASE 0x581FB80ull
+#define NIC8_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC8_QPC0_AXUSER_CONG_QUE_SECTION 0x6000
+#define mmNIC8_QPC0_AXUSER_RXWQE_BASE 0x581FBE0ull
+#define NIC8_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC8_QPC0_AXUSER_RXWQE_SECTION 0x6000
+#define mmNIC8_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x581FC40ull
+#define NIC8_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC8_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define mmNIC8_QPC0_AXUSER_DB_FIFO_BASE 0x581FCA0ull
+#define NIC8_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC8_QPC0_AXUSER_DB_FIFO_SECTION 0x6000
+#define mmNIC8_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x581FD00ull
+#define NIC8_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC8_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define mmNIC8_QPC0_AXUSER_ERR_FIFO_BASE 0x581FD60ull
+#define NIC8_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC8_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000
+#define mmNIC8_QPC0_AXUSER_QPC_RESP_BASE 0x581FDC0ull
+#define NIC8_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC8_QPC0_AXUSER_QPC_RESP_SECTION 0x6000
+#define mmNIC8_QPC0_AXUSER_QPC_REQ_BASE 0x581FE20ull
+#define NIC8_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC8_QPC0_AXUSER_QPC_REQ_SECTION 0x6000
+#define mmNIC8_QPC0_SPECIAL_BASE 0x581FE80ull
+#define NIC8_QPC0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_QPC0_SPECIAL_SECTION 0x1800
+#define mmNIC8_UMR1_0_UNSECURE_DOORBELL0_BASE 0x5820000ull
+#define NIC8_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC8_UMR1_0_UNSECURE_DOORBELL1_BASE 0x5820080ull
+#define NIC8_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC8_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x5820100ull
+#define NIC8_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC8_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x5820180ull
+#define NIC8_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC8_UMR1_0_SPECIAL_BASE 0x5820E80ull
+#define NIC8_UMR1_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR1_0_SPECIAL_SECTION 0x1800
+#define mmNIC8_UMR1_1_UNSECURE_DOORBELL0_BASE 0x5821000ull
+#define NIC8_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC8_UMR1_1_UNSECURE_DOORBELL1_BASE 0x5821080ull
+#define NIC8_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC8_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x5821100ull
+#define NIC8_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC8_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x5821180ull
+#define NIC8_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC8_UMR1_1_SPECIAL_BASE 0x5821E80ull
+#define NIC8_UMR1_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR1_1_SPECIAL_SECTION 0x1800
+#define mmNIC8_UMR1_2_UNSECURE_DOORBELL0_BASE 0x5822000ull
+#define NIC8_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC8_UMR1_2_UNSECURE_DOORBELL1_BASE 0x5822080ull
+#define NIC8_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC8_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x5822100ull
+#define NIC8_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC8_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x5822180ull
+#define NIC8_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC8_UMR1_2_SPECIAL_BASE 0x5822E80ull
+#define NIC8_UMR1_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR1_2_SPECIAL_SECTION 0x1800
+#define mmNIC8_UMR1_3_UNSECURE_DOORBELL0_BASE 0x5823000ull
+#define NIC8_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC8_UMR1_3_UNSECURE_DOORBELL1_BASE 0x5823080ull
+#define NIC8_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC8_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x5823100ull
+#define NIC8_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC8_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x5823180ull
+#define NIC8_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC8_UMR1_3_SPECIAL_BASE 0x5823E80ull
+#define NIC8_UMR1_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR1_3_SPECIAL_SECTION 0x1800
+#define mmNIC8_UMR1_4_UNSECURE_DOORBELL0_BASE 0x5824000ull
+#define NIC8_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC8_UMR1_4_UNSECURE_DOORBELL1_BASE 0x5824080ull
+#define NIC8_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC8_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x5824100ull
+#define NIC8_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC8_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x5824180ull
+#define NIC8_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC8_UMR1_4_SPECIAL_BASE 0x5824E80ull
+#define NIC8_UMR1_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR1_4_SPECIAL_SECTION 0x1800
+#define mmNIC8_UMR1_5_UNSECURE_DOORBELL0_BASE 0x5825000ull
+#define NIC8_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC8_UMR1_5_UNSECURE_DOORBELL1_BASE 0x5825080ull
+#define NIC8_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC8_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x5825100ull
+#define NIC8_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC8_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x5825180ull
+#define NIC8_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC8_UMR1_5_SPECIAL_BASE 0x5825E80ull
+#define NIC8_UMR1_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR1_5_SPECIAL_SECTION 0x1800
+#define mmNIC8_UMR1_6_UNSECURE_DOORBELL0_BASE 0x5826000ull
+#define NIC8_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC8_UMR1_6_UNSECURE_DOORBELL1_BASE 0x5826080ull
+#define NIC8_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC8_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x5826100ull
+#define NIC8_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC8_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x5826180ull
+#define NIC8_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC8_UMR1_6_SPECIAL_BASE 0x5826E80ull
+#define NIC8_UMR1_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR1_6_SPECIAL_SECTION 0x1800
+#define mmNIC8_UMR1_7_UNSECURE_DOORBELL0_BASE 0x5827000ull
+#define NIC8_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC8_UMR1_7_UNSECURE_DOORBELL1_BASE 0x5827080ull
+#define NIC8_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC8_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x5827100ull
+#define NIC8_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC8_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x5827180ull
+#define NIC8_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC8_UMR1_7_SPECIAL_BASE 0x5827E80ull
+#define NIC8_UMR1_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR1_7_SPECIAL_SECTION 0x1800
+#define mmNIC8_UMR1_8_UNSECURE_DOORBELL0_BASE 0x5828000ull
+#define NIC8_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC8_UMR1_8_UNSECURE_DOORBELL1_BASE 0x5828080ull
+#define NIC8_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC8_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x5828100ull
+#define NIC8_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC8_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x5828180ull
+#define NIC8_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC8_UMR1_8_SPECIAL_BASE 0x5828E80ull
+#define NIC8_UMR1_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR1_8_SPECIAL_SECTION 0x1800
+#define mmNIC8_UMR1_9_UNSECURE_DOORBELL0_BASE 0x5829000ull
+#define NIC8_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC8_UMR1_9_UNSECURE_DOORBELL1_BASE 0x5829080ull
+#define NIC8_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC8_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x5829100ull
+#define NIC8_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC8_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x5829180ull
+#define NIC8_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC8_UMR1_9_SPECIAL_BASE 0x5829E80ull
+#define NIC8_UMR1_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR1_9_SPECIAL_SECTION 0x1800
+#define mmNIC8_UMR1_10_UNSECURE_DOORBELL0_BASE 0x582A000ull
+#define NIC8_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC8_UMR1_10_UNSECURE_DOORBELL1_BASE 0x582A080ull
+#define NIC8_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC8_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x582A100ull
+#define NIC8_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC8_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x582A180ull
+#define NIC8_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC8_UMR1_10_SPECIAL_BASE 0x582AE80ull
+#define NIC8_UMR1_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR1_10_SPECIAL_SECTION 0x1800
+#define mmNIC8_UMR1_11_UNSECURE_DOORBELL0_BASE 0x582B000ull
+#define NIC8_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC8_UMR1_11_UNSECURE_DOORBELL1_BASE 0x582B080ull
+#define NIC8_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC8_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x582B100ull
+#define NIC8_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC8_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x582B180ull
+#define NIC8_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC8_UMR1_11_SPECIAL_BASE 0x582BE80ull
+#define NIC8_UMR1_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR1_11_SPECIAL_SECTION 0x1800
+#define mmNIC8_UMR1_12_UNSECURE_DOORBELL0_BASE 0x582C000ull
+#define NIC8_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC8_UMR1_12_UNSECURE_DOORBELL1_BASE 0x582C080ull
+#define NIC8_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC8_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x582C100ull
+#define NIC8_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC8_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x582C180ull
+#define NIC8_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC8_UMR1_12_SPECIAL_BASE 0x582CE80ull
+#define NIC8_UMR1_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR1_12_SPECIAL_SECTION 0x1800
+#define mmNIC8_UMR1_13_UNSECURE_DOORBELL0_BASE 0x582D000ull
+#define NIC8_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC8_UMR1_13_UNSECURE_DOORBELL1_BASE 0x582D080ull
+#define NIC8_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC8_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x582D100ull
+#define NIC8_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC8_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x582D180ull
+#define NIC8_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC8_UMR1_13_SPECIAL_BASE 0x582DE80ull
+#define NIC8_UMR1_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR1_13_SPECIAL_SECTION 0x1800
+#define mmNIC8_UMR1_14_UNSECURE_DOORBELL0_BASE 0x582E000ull
+#define NIC8_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC8_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC8_UMR1_14_UNSECURE_DOORBELL1_BASE 0x582E080ull
+#define NIC8_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC8_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC8_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x582E100ull
+#define NIC8_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC8_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC8_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x582E180ull
+#define NIC8_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC8_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC8_UMR1_14_SPECIAL_BASE 0x582EE80ull
+#define NIC8_UMR1_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_UMR1_14_SPECIAL_SECTION 0x1180
+#define mmNIC8_QM_DCCM1_BASE 0x5830000ull
+#define NIC8_QM_DCCM1_MAX_OFFSET 0x4000
+#define NIC8_QM_DCCM1_SECTION 0x8000
+#define mmNIC8_QM_ARC_AUX1_BASE 0x5838000ull
+#define NIC8_QM_ARC_AUX1_MAX_OFFSET 0x1000
+#define NIC8_QM_ARC_AUX1_SECTION 0xE800
+#define mmNIC8_QM_ARC_AUX1_SPECIAL_BASE 0x5838E80ull
+#define NIC8_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_QM_ARC_AUX1_SPECIAL_SECTION 0x1180
+#define mmNIC8_QM1_BASE 0x583A000ull
+#define NIC8_QM1_MAX_OFFSET 0x1000
+#define NIC8_QM1_SECTION 0x9000
+#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x583A900ull
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x583A908ull
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x583A910ull
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x583A918ull
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x583A920ull
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x583A928ull
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x583A930ull
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x583A938ull
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x583A940ull
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x583A948ull
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x583A950ull
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x583A958ull
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x583A960ull
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x583A968ull
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x583A970ull
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x583A978ull
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC8_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmNIC8_QM1_AXUSER_SECURED_BASE 0x583AB00ull
+#define NIC8_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC8_QM1_AXUSER_SECURED_SECTION 0x8000
+#define mmNIC8_QM1_AXUSER_NONSECURED_BASE 0x583AB80ull
+#define NIC8_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC8_QM1_AXUSER_NONSECURED_SECTION 0x8000
+#define mmNIC8_QM1_DBG_HBW_BASE 0x583AC00ull
+#define NIC8_QM1_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC8_QM1_DBG_HBW_SECTION 0x8000
+#define mmNIC8_QM1_DBG_LBW_BASE 0x583AC80ull
+#define NIC8_QM1_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC8_QM1_DBG_LBW_SECTION 0x1000
+#define mmNIC8_QM1_CGM_BASE 0x583AD80ull
+#define NIC8_QM1_CGM_MAX_OFFSET 0xC000
+#define NIC8_QM1_CGM_SECTION 0x1000
+#define mmNIC8_QM1_SPECIAL_BASE 0x583AE80ull
+#define NIC8_QM1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_QM1_SPECIAL_SECTION 0x4180
+#define mmNIC8_QPC1_BASE 0x583F000ull
+#define NIC8_QPC1_MAX_OFFSET 0x1000
+#define NIC8_QPC1_SECTION 0x7200
+#define mmNIC8_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x583F720ull
+#define NIC8_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x583F728ull
+#define NIC8_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x583F730ull
+#define NIC8_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x583F738ull
+#define NIC8_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x583F740ull
+#define NIC8_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x583F748ull
+#define NIC8_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x583F750ull
+#define NIC8_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x583F758ull
+#define NIC8_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x583F760ull
+#define NIC8_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x583F768ull
+#define NIC8_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x583F770ull
+#define NIC8_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x583F778ull
+#define NIC8_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x583F780ull
+#define NIC8_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x583F788ull
+#define NIC8_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x583F790ull
+#define NIC8_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x583F798ull
+#define NIC8_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x583F7A0ull
+#define NIC8_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x583F7A8ull
+#define NIC8_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x583F7B0ull
+#define NIC8_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x583F7B8ull
+#define NIC8_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x583F7C0ull
+#define NIC8_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x583F7C8ull
+#define NIC8_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x583F7D0ull
+#define NIC8_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x583F7D8ull
+#define NIC8_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x583F7E0ull
+#define NIC8_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x583F7E8ull
+#define NIC8_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x583F7F0ull
+#define NIC8_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x583F7F8ull
+#define NIC8_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x583F800ull
+#define NIC8_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x583F808ull
+#define NIC8_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x583F810ull
+#define NIC8_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC8_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x583F818ull
+#define NIC8_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC8_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define mmNIC8_QPC1_AXUSER_CONG_QUE_BASE 0x583FB80ull
+#define NIC8_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC8_QPC1_AXUSER_CONG_QUE_SECTION 0x6000
+#define mmNIC8_QPC1_AXUSER_RXWQE_BASE 0x583FBE0ull
+#define NIC8_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC8_QPC1_AXUSER_RXWQE_SECTION 0x6000
+#define mmNIC8_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x583FC40ull
+#define NIC8_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC8_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define mmNIC8_QPC1_AXUSER_DB_FIFO_BASE 0x583FCA0ull
+#define NIC8_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC8_QPC1_AXUSER_DB_FIFO_SECTION 0x6000
+#define mmNIC8_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x583FD00ull
+#define NIC8_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC8_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define mmNIC8_QPC1_AXUSER_ERR_FIFO_BASE 0x583FD60ull
+#define NIC8_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC8_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000
+#define mmNIC8_QPC1_AXUSER_QPC_RESP_BASE 0x583FDC0ull
+#define NIC8_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC8_QPC1_AXUSER_QPC_RESP_SECTION 0x6000
+#define mmNIC8_QPC1_AXUSER_QPC_REQ_BASE 0x583FE20ull
+#define NIC8_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC8_QPC1_AXUSER_QPC_REQ_SECTION 0x6000
+#define mmNIC8_QPC1_SPECIAL_BASE 0x583FE80ull
+#define NIC8_QPC1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_QPC1_SPECIAL_SECTION 0x8180
+#define mmNIC8_TMR_BASE 0x5848000ull
+#define NIC8_TMR_MAX_OFFSET 0x1000
+#define NIC8_TMR_SECTION 0xD600
+#define mmNIC8_TMR_AXUSER_TMR_FREE_LIST_BASE 0x5848D60ull
+#define NIC8_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000
+#define NIC8_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000
+#define mmNIC8_TMR_AXUSER_TMR_FIFO_BASE 0x5848DC0ull
+#define NIC8_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000
+#define NIC8_TMR_AXUSER_TMR_FIFO_SECTION 0x6000
+#define mmNIC8_TMR_AXUSER_TMR_FSM_BASE 0x5848E20ull
+#define NIC8_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000
+#define NIC8_TMR_AXUSER_TMR_FSM_SECTION 0x6000
+#define mmNIC8_TMR_SPECIAL_BASE 0x5848E80ull
+#define NIC8_TMR_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_TMR_SPECIAL_SECTION 0x1800
+#define mmNIC8_RXB_CORE_BASE 0x5849000ull
+#define NIC8_RXB_CORE_MAX_OFFSET 0x1000
+#define NIC8_RXB_CORE_SECTION 0x6100
+#define mmNIC8_RXB_CORE_SCT_AWUSER_BASE 0x5849610ull
+#define NIC8_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000
+#define NIC8_RXB_CORE_SCT_AWUSER_SECTION 0x8700
+#define mmNIC8_RXB_CORE_SPECIAL_BASE 0x5849E80ull
+#define NIC8_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_RXB_CORE_SPECIAL_SECTION 0x1800
+#define mmNIC8_RXE0_BASE 0x584A000ull
+#define NIC8_RXE0_MAX_OFFSET 0x1000
+#define NIC8_RXE0_SECTION 0x9000
+#define mmNIC8_RXE0_WQE_ARUSER_BASE 0x584A900ull
+#define NIC8_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC8_RXE0_WQE_ARUSER_SECTION 0x5800
+#define mmNIC8_RXE0_SPECIAL_BASE 0x584AE80ull
+#define NIC8_RXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_RXE0_SPECIAL_SECTION 0x1800
+#define mmNIC8_RXE1_BASE 0x584B000ull
+#define NIC8_RXE1_MAX_OFFSET 0x1000
+#define NIC8_RXE1_SECTION 0x9000
+#define mmNIC8_RXE1_WQE_ARUSER_BASE 0x584B900ull
+#define NIC8_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC8_RXE1_WQE_ARUSER_SECTION 0x5800
+#define mmNIC8_RXE1_SPECIAL_BASE 0x584BE80ull
+#define NIC8_RXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_RXE1_SPECIAL_SECTION 0x1800
+#define mmNIC8_RXE0_AXUSER_AXUSER_CQ0_BASE 0x584C000ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define mmNIC8_RXE0_AXUSER_AXUSER_CQ1_BASE 0x584C050ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define mmNIC8_RXE0_AXUSER_AXUSER_CQ2_BASE 0x584C0A0ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define mmNIC8_RXE0_AXUSER_AXUSER_CQ3_BASE 0x584C0F0ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define mmNIC8_RXE0_AXUSER_AXUSER_CQ4_BASE 0x584C140ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define mmNIC8_RXE0_AXUSER_AXUSER_CQ5_BASE 0x584C190ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define mmNIC8_RXE0_AXUSER_AXUSER_CQ6_BASE 0x584C1E0ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define mmNIC8_RXE0_AXUSER_AXUSER_CQ7_BASE 0x584C230ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define mmNIC8_RXE0_AXUSER_AXUSER_CQ8_BASE 0x584C280ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define mmNIC8_RXE0_AXUSER_AXUSER_CQ9_BASE 0x584C2D0ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define mmNIC8_RXE0_AXUSER_AXUSER_CQ10_BASE 0x584C320ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define mmNIC8_RXE0_AXUSER_AXUSER_CQ11_BASE 0x584C370ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define mmNIC8_RXE0_AXUSER_AXUSER_CQ12_BASE 0x584C3C0ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define mmNIC8_RXE0_AXUSER_AXUSER_CQ13_BASE 0x584C410ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define mmNIC8_RXE0_AXUSER_AXUSER_CQ14_BASE 0x584C460ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define mmNIC8_RXE0_AXUSER_AXUSER_CQ15_BASE 0x584C4B0ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define mmNIC8_RXE0_AXUSER_AXUSER_CQ16_BASE 0x584C500ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define mmNIC8_RXE0_AXUSER_AXUSER_CQ17_BASE 0x584C550ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define mmNIC8_RXE0_AXUSER_AXUSER_CQ18_BASE 0x584C5A0ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define mmNIC8_RXE0_AXUSER_AXUSER_CQ19_BASE 0x584C5F0ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define mmNIC8_RXE0_AXUSER_AXUSER_CQ20_BASE 0x584C640ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define mmNIC8_RXE0_AXUSER_AXUSER_CQ21_BASE 0x584C690ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define mmNIC8_RXE0_AXUSER_AXUSER_CQ22_BASE 0x584C6E0ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define mmNIC8_RXE0_AXUSER_AXUSER_CQ23_BASE 0x584C730ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define mmNIC8_RXE0_AXUSER_AXUSER_CQ24_BASE 0x584C780ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define mmNIC8_RXE0_AXUSER_AXUSER_CQ25_BASE 0x584C7D0ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define mmNIC8_RXE0_AXUSER_AXUSER_CQ26_BASE 0x584C820ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define mmNIC8_RXE0_AXUSER_AXUSER_CQ27_BASE 0x584C870ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define mmNIC8_RXE0_AXUSER_AXUSER_CQ28_BASE 0x584C8C0ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define mmNIC8_RXE0_AXUSER_AXUSER_CQ29_BASE 0x584C910ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define mmNIC8_RXE0_AXUSER_AXUSER_CQ30_BASE 0x584C960ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define mmNIC8_RXE0_AXUSER_AXUSER_CQ31_BASE 0x584C9B0ull
+#define NIC8_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC8_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define mmNIC8_RXE0_AXUSER_SPECIAL_BASE 0x584CE80ull
+#define NIC8_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_RXE0_AXUSER_SPECIAL_SECTION 0x1800
+#define mmNIC8_RXE1_AXUSER_AXUSER_CQ0_BASE 0x584D000ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define mmNIC8_RXE1_AXUSER_AXUSER_CQ1_BASE 0x584D050ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define mmNIC8_RXE1_AXUSER_AXUSER_CQ2_BASE 0x584D0A0ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define mmNIC8_RXE1_AXUSER_AXUSER_CQ3_BASE 0x584D0F0ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define mmNIC8_RXE1_AXUSER_AXUSER_CQ4_BASE 0x584D140ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define mmNIC8_RXE1_AXUSER_AXUSER_CQ5_BASE 0x584D190ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define mmNIC8_RXE1_AXUSER_AXUSER_CQ6_BASE 0x584D1E0ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define mmNIC8_RXE1_AXUSER_AXUSER_CQ7_BASE 0x584D230ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define mmNIC8_RXE1_AXUSER_AXUSER_CQ8_BASE 0x584D280ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define mmNIC8_RXE1_AXUSER_AXUSER_CQ9_BASE 0x584D2D0ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define mmNIC8_RXE1_AXUSER_AXUSER_CQ10_BASE 0x584D320ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define mmNIC8_RXE1_AXUSER_AXUSER_CQ11_BASE 0x584D370ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define mmNIC8_RXE1_AXUSER_AXUSER_CQ12_BASE 0x584D3C0ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define mmNIC8_RXE1_AXUSER_AXUSER_CQ13_BASE 0x584D410ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define mmNIC8_RXE1_AXUSER_AXUSER_CQ14_BASE 0x584D460ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define mmNIC8_RXE1_AXUSER_AXUSER_CQ15_BASE 0x584D4B0ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define mmNIC8_RXE1_AXUSER_AXUSER_CQ16_BASE 0x584D500ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define mmNIC8_RXE1_AXUSER_AXUSER_CQ17_BASE 0x584D550ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define mmNIC8_RXE1_AXUSER_AXUSER_CQ18_BASE 0x584D5A0ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define mmNIC8_RXE1_AXUSER_AXUSER_CQ19_BASE 0x584D5F0ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define mmNIC8_RXE1_AXUSER_AXUSER_CQ20_BASE 0x584D640ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define mmNIC8_RXE1_AXUSER_AXUSER_CQ21_BASE 0x584D690ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define mmNIC8_RXE1_AXUSER_AXUSER_CQ22_BASE 0x584D6E0ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define mmNIC8_RXE1_AXUSER_AXUSER_CQ23_BASE 0x584D730ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define mmNIC8_RXE1_AXUSER_AXUSER_CQ24_BASE 0x584D780ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define mmNIC8_RXE1_AXUSER_AXUSER_CQ25_BASE 0x584D7D0ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define mmNIC8_RXE1_AXUSER_AXUSER_CQ26_BASE 0x584D820ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define mmNIC8_RXE1_AXUSER_AXUSER_CQ27_BASE 0x584D870ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define mmNIC8_RXE1_AXUSER_AXUSER_CQ28_BASE 0x584D8C0ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define mmNIC8_RXE1_AXUSER_AXUSER_CQ29_BASE 0x584D910ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define mmNIC8_RXE1_AXUSER_AXUSER_CQ30_BASE 0x584D960ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define mmNIC8_RXE1_AXUSER_AXUSER_CQ31_BASE 0x584D9B0ull
+#define NIC8_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC8_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define mmNIC8_RXE1_AXUSER_SPECIAL_BASE 0x584DE80ull
+#define NIC8_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_RXE1_AXUSER_SPECIAL_SECTION 0x2180
+#define mmNIC8_TXS0_BASE 0x5850000ull
+#define NIC8_TXS0_MAX_OFFSET 0x1000
+#define NIC8_TXS0_SECTION 0xE800
+#define mmNIC8_TXS0_SPECIAL_BASE 0x5850E80ull
+#define NIC8_TXS0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_TXS0_SPECIAL_SECTION 0x1800
+#define mmNIC8_TXS1_BASE 0x5851000ull
+#define NIC8_TXS1_MAX_OFFSET 0x1000
+#define NIC8_TXS1_SECTION 0xE800
+#define mmNIC8_TXS1_SPECIAL_BASE 0x5851E80ull
+#define NIC8_TXS1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_TXS1_SPECIAL_SECTION 0x1800
+#define mmNIC8_TXE0_BASE 0x5852000ull
+#define NIC8_TXE0_MAX_OFFSET 0x1000
+#define NIC8_TXE0_SECTION 0xE800
+#define mmNIC8_TXE0_SPECIAL_BASE 0x5852E80ull
+#define NIC8_TXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_TXE0_SPECIAL_SECTION 0x1800
+#define mmNIC8_TXE1_BASE 0x5853000ull
+#define NIC8_TXE1_MAX_OFFSET 0x1000
+#define NIC8_TXE1_SECTION 0xE800
+#define mmNIC8_TXE1_SPECIAL_BASE 0x5853E80ull
+#define NIC8_TXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_TXE1_SPECIAL_SECTION 0x1800
+#define mmNIC8_TXB_BASE 0x5854000ull
+#define NIC8_TXB_MAX_OFFSET 0x1000
+#define NIC8_TXB_SECTION 0xE800
+#define mmNIC8_TXB_SPECIAL_BASE 0x5854E80ull
+#define NIC8_TXB_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_TXB_SPECIAL_SECTION 0x1800
+#define mmNIC8_MSTR_IF_RR_SHRD_HBW_BASE 0x5855000ull
+#define NIC8_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define NIC8_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmNIC8_MSTR_IF_RR_PRVT_HBW_BASE 0x5855200ull
+#define NIC8_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define NIC8_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmNIC8_MSTR_IF_RR_SHRD_LBW_BASE 0x5855400ull
+#define NIC8_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define NIC8_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmNIC8_MSTR_IF_RR_PRVT_LBW_BASE 0x5855600ull
+#define NIC8_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define NIC8_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmNIC8_MSTR_IF_E2E_CRDT_BASE 0x5855800ull
+#define NIC8_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define NIC8_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmNIC8_MSTR_IF_AXUSER_BASE 0x5855A80ull
+#define NIC8_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define NIC8_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmNIC8_MSTR_IF_DBG_HBW_BASE 0x5855B00ull
+#define NIC8_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC8_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmNIC8_MSTR_IF_DBG_LBW_BASE 0x5855B80ull
+#define NIC8_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC8_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmNIC8_MSTR_IF_CORE_HBW_BASE 0x5855C00ull
+#define NIC8_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define NIC8_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmNIC8_MSTR_IF_CORE_LBW_BASE 0x5855D80ull
+#define NIC8_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define NIC8_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmNIC8_MSTR_IF_SPECIAL_BASE 0x5855E80ull
+#define NIC8_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmNIC8_TX_AXUSER_BASE 0x5856000ull
+#define NIC8_TX_AXUSER_MAX_OFFSET 0x5000
+#define NIC8_TX_AXUSER_SECTION 0x2000
+#define mmNIC8_SERDES0_BASE 0x5858000ull
+#define NIC8_SERDES0_MAX_OFFSET 0x3E40
+#define NIC8_SERDES0_SECTION 0x4000
+#define mmNIC8_SERDES1_BASE 0x585C000ull
+#define NIC8_SERDES1_MAX_OFFSET 0x3E40
+#define NIC8_SERDES1_SECTION 0x4000
+#define mmNIC8_PHY_BASE 0x5860000ull
+#define NIC8_PHY_MAX_OFFSET 0x1000
+#define NIC8_PHY_SECTION 0xE800
+#define mmNIC8_PHY_SPECIAL_BASE 0x5860E80ull
+#define NIC8_PHY_SPECIAL_MAX_OFFSET 0x1800
+#define NIC8_PHY_SPECIAL_SECTION 0x7180
+#define mmPRT8_MAC_AUX_BASE 0x5868000ull
+#define PRT8_MAC_AUX_MAX_OFFSET 0x1000
+#define PRT8_MAC_AUX_SECTION 0xE800
+#define mmPRT8_MAC_AUX_SPECIAL_BASE 0x5868E80ull
+#define PRT8_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define PRT8_MAC_AUX_SPECIAL_SECTION 0x1800
+#define mmPRT8_MAC_CORE_BASE 0x5869000ull
+#define PRT8_MAC_CORE_MAX_OFFSET 0x1000
+#define PRT8_MAC_CORE_SECTION 0xE800
+#define mmPRT8_MAC_CORE_SPECIAL_BASE 0x5869E80ull
+#define PRT8_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define PRT8_MAC_CORE_SPECIAL_SECTION 0x1800
+#define mmNIC8_MAC_RS_FEC_BASE 0x586A000ull
+#define NIC8_MAC_RS_FEC_MAX_OFFSET 0x2DC0
+#define NIC8_MAC_RS_FEC_SECTION 0x1000
+#define mmNIC8_MAC_GLOB_STAT_CONTROL_REG_BASE 0x586B000ull
+#define NIC8_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000
+#define NIC8_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000
+#define mmNIC8_MAC_GLOB_STAT_RX0_BASE 0x586B100ull
+#define NIC8_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00
+#define NIC8_MAC_GLOB_STAT_RX0_SECTION 0x8C00
+#define mmNIC8_MAC_GLOB_STAT_RX1_BASE 0x586B18Cull
+#define NIC8_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00
+#define NIC8_MAC_GLOB_STAT_RX1_SECTION 0x8C00
+#define mmNIC8_MAC_GLOB_STAT_RX2_BASE 0x586B218ull
+#define NIC8_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00
+#define NIC8_MAC_GLOB_STAT_RX2_SECTION 0x8C00
+#define mmNIC8_MAC_GLOB_STAT_RX3_BASE 0x586B2A4ull
+#define NIC8_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00
+#define NIC8_MAC_GLOB_STAT_RX3_SECTION 0x8C00
+#define mmNIC8_MAC_GLOB_STAT_TX0_BASE 0x586B330ull
+#define NIC8_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800
+#define NIC8_MAC_GLOB_STAT_TX0_SECTION 0x6800
+#define mmNIC8_MAC_GLOB_STAT_TX1_BASE 0x586B398ull
+#define NIC8_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800
+#define NIC8_MAC_GLOB_STAT_TX1_SECTION 0x6800
+#define mmNIC8_MAC_GLOB_STAT_TX2_BASE 0x586B400ull
+#define NIC8_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800
+#define NIC8_MAC_GLOB_STAT_TX2_SECTION 0x6800
+#define mmNIC8_MAC_GLOB_STAT_TX3_BASE 0x586B468ull
+#define NIC8_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800
+#define NIC8_MAC_GLOB_STAT_TX3_SECTION 0x3980
+#define mmNIC8_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x586B800ull
+#define NIC8_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0
+#define NIC8_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000
+#define mmNIC8_MAC_CH0_MAC_PCS_BASE 0x586C000ull
+#define NIC8_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC8_MAC_CH0_MAC_PCS_SECTION 0x4000
+#define mmNIC8_MAC_CH0_MAC_128_BASE 0x586C400ull
+#define NIC8_MAC_CH0_MAC_128_MAX_OFFSET 0xA400
+#define NIC8_MAC_CH0_MAC_128_SECTION 0x4000
+#define mmNIC8_MAC_CH0_MAC_AN_BASE 0x586C800ull
+#define NIC8_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400
+#define NIC8_MAC_CH0_MAC_AN_SECTION 0x8000
+#define mmNIC8_MAC_CH1_MAC_PCS_BASE 0x586D000ull
+#define NIC8_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC8_MAC_CH1_MAC_PCS_SECTION 0x4000
+#define mmNIC8_MAC_CH1_MAC_128_BASE 0x586D400ull
+#define NIC8_MAC_CH1_MAC_128_MAX_OFFSET 0xA400
+#define NIC8_MAC_CH1_MAC_128_SECTION 0x4000
+#define mmNIC8_MAC_CH1_MAC_AN_BASE 0x586D800ull
+#define NIC8_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400
+#define NIC8_MAC_CH1_MAC_AN_SECTION 0x8000
+#define mmNIC8_MAC_CH2_MAC_PCS_BASE 0x586E000ull
+#define NIC8_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC8_MAC_CH2_MAC_PCS_SECTION 0x4000
+#define mmNIC8_MAC_CH2_MAC_128_BASE 0x586E400ull
+#define NIC8_MAC_CH2_MAC_128_MAX_OFFSET 0xA400
+#define NIC8_MAC_CH2_MAC_128_SECTION 0x4000
+#define mmNIC8_MAC_CH2_MAC_AN_BASE 0x586E800ull
+#define NIC8_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400
+#define NIC8_MAC_CH2_MAC_AN_SECTION 0x8000
+#define mmNIC8_MAC_CH3_MAC_PCS_BASE 0x586F000ull
+#define NIC8_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC8_MAC_CH3_MAC_PCS_SECTION 0x4000
+#define mmNIC8_MAC_CH3_MAC_128_BASE 0x586F400ull
+#define NIC8_MAC_CH3_MAC_128_MAX_OFFSET 0xA400
+#define NIC8_MAC_CH3_MAC_128_SECTION 0x4000
+#define mmNIC8_MAC_CH3_MAC_AN_BASE 0x586F800ull
+#define NIC8_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400
+#define NIC8_MAC_CH3_MAC_AN_SECTION 0x10800
+#define mmNIC9_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5880000ull
+#define NIC9_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC9_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5880080ull
+#define NIC9_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC9_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5880100ull
+#define NIC9_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC9_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5880180ull
+#define NIC9_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC9_UMR0_0_SPECIAL_BASE 0x5880E80ull
+#define NIC9_UMR0_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR0_0_SPECIAL_SECTION 0x1800
+#define mmNIC9_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5881000ull
+#define NIC9_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC9_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5881080ull
+#define NIC9_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC9_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5881100ull
+#define NIC9_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC9_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5881180ull
+#define NIC9_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC9_UMR0_1_SPECIAL_BASE 0x5881E80ull
+#define NIC9_UMR0_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR0_1_SPECIAL_SECTION 0x1800
+#define mmNIC9_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5882000ull
+#define NIC9_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC9_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5882080ull
+#define NIC9_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC9_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5882100ull
+#define NIC9_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC9_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5882180ull
+#define NIC9_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC9_UMR0_2_SPECIAL_BASE 0x5882E80ull
+#define NIC9_UMR0_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR0_2_SPECIAL_SECTION 0x1800
+#define mmNIC9_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5883000ull
+#define NIC9_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC9_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5883080ull
+#define NIC9_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC9_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5883100ull
+#define NIC9_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC9_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5883180ull
+#define NIC9_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC9_UMR0_3_SPECIAL_BASE 0x5883E80ull
+#define NIC9_UMR0_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR0_3_SPECIAL_SECTION 0x1800
+#define mmNIC9_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5884000ull
+#define NIC9_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC9_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5884080ull
+#define NIC9_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC9_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5884100ull
+#define NIC9_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC9_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5884180ull
+#define NIC9_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC9_UMR0_4_SPECIAL_BASE 0x5884E80ull
+#define NIC9_UMR0_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR0_4_SPECIAL_SECTION 0x1800
+#define mmNIC9_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5885000ull
+#define NIC9_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC9_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5885080ull
+#define NIC9_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC9_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5885100ull
+#define NIC9_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC9_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5885180ull
+#define NIC9_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC9_UMR0_5_SPECIAL_BASE 0x5885E80ull
+#define NIC9_UMR0_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR0_5_SPECIAL_SECTION 0x1800
+#define mmNIC9_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5886000ull
+#define NIC9_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC9_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5886080ull
+#define NIC9_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC9_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5886100ull
+#define NIC9_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC9_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5886180ull
+#define NIC9_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC9_UMR0_6_SPECIAL_BASE 0x5886E80ull
+#define NIC9_UMR0_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR0_6_SPECIAL_SECTION 0x1800
+#define mmNIC9_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5887000ull
+#define NIC9_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC9_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5887080ull
+#define NIC9_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC9_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5887100ull
+#define NIC9_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC9_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5887180ull
+#define NIC9_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC9_UMR0_7_SPECIAL_BASE 0x5887E80ull
+#define NIC9_UMR0_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR0_7_SPECIAL_SECTION 0x1800
+#define mmNIC9_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5888000ull
+#define NIC9_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC9_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5888080ull
+#define NIC9_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC9_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5888100ull
+#define NIC9_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC9_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5888180ull
+#define NIC9_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC9_UMR0_8_SPECIAL_BASE 0x5888E80ull
+#define NIC9_UMR0_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR0_8_SPECIAL_SECTION 0x1800
+#define mmNIC9_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5889000ull
+#define NIC9_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC9_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5889080ull
+#define NIC9_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC9_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5889100ull
+#define NIC9_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC9_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5889180ull
+#define NIC9_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC9_UMR0_9_SPECIAL_BASE 0x5889E80ull
+#define NIC9_UMR0_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR0_9_SPECIAL_SECTION 0x1800
+#define mmNIC9_UMR0_10_UNSECURE_DOORBELL0_BASE 0x588A000ull
+#define NIC9_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC9_UMR0_10_UNSECURE_DOORBELL1_BASE 0x588A080ull
+#define NIC9_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC9_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x588A100ull
+#define NIC9_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC9_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x588A180ull
+#define NIC9_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC9_UMR0_10_SPECIAL_BASE 0x588AE80ull
+#define NIC9_UMR0_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR0_10_SPECIAL_SECTION 0x1800
+#define mmNIC9_UMR0_11_UNSECURE_DOORBELL0_BASE 0x588B000ull
+#define NIC9_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC9_UMR0_11_UNSECURE_DOORBELL1_BASE 0x588B080ull
+#define NIC9_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC9_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x588B100ull
+#define NIC9_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC9_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x588B180ull
+#define NIC9_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC9_UMR0_11_SPECIAL_BASE 0x588BE80ull
+#define NIC9_UMR0_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR0_11_SPECIAL_SECTION 0x1800
+#define mmNIC9_UMR0_12_UNSECURE_DOORBELL0_BASE 0x588C000ull
+#define NIC9_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC9_UMR0_12_UNSECURE_DOORBELL1_BASE 0x588C080ull
+#define NIC9_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC9_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x588C100ull
+#define NIC9_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC9_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x588C180ull
+#define NIC9_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC9_UMR0_12_SPECIAL_BASE 0x588CE80ull
+#define NIC9_UMR0_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR0_12_SPECIAL_SECTION 0x1800
+#define mmNIC9_UMR0_13_UNSECURE_DOORBELL0_BASE 0x588D000ull
+#define NIC9_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC9_UMR0_13_UNSECURE_DOORBELL1_BASE 0x588D080ull
+#define NIC9_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC9_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x588D100ull
+#define NIC9_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC9_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x588D180ull
+#define NIC9_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC9_UMR0_13_SPECIAL_BASE 0x588DE80ull
+#define NIC9_UMR0_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR0_13_SPECIAL_SECTION 0x1800
+#define mmNIC9_UMR0_14_UNSECURE_DOORBELL0_BASE 0x588E000ull
+#define NIC9_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC9_UMR0_14_UNSECURE_DOORBELL1_BASE 0x588E080ull
+#define NIC9_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC9_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x588E100ull
+#define NIC9_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC9_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x588E180ull
+#define NIC9_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC9_UMR0_14_SPECIAL_BASE 0x588EE80ull
+#define NIC9_UMR0_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR0_14_SPECIAL_SECTION 0x1180
+#define mmNIC9_QM_DCCM0_BASE 0x5890000ull
+#define NIC9_QM_DCCM0_MAX_OFFSET 0x4000
+#define NIC9_QM_DCCM0_SECTION 0x8000
+#define mmNIC9_QM_ARC_AUX0_BASE 0x5898000ull
+#define NIC9_QM_ARC_AUX0_MAX_OFFSET 0x1000
+#define NIC9_QM_ARC_AUX0_SECTION 0xE800
+#define mmNIC9_QM_ARC_AUX0_SPECIAL_BASE 0x5898E80ull
+#define NIC9_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_QM_ARC_AUX0_SPECIAL_SECTION 0x1180
+#define mmNIC9_QM0_BASE 0x589A000ull
+#define NIC9_QM0_MAX_OFFSET 0x1000
+#define NIC9_QM0_SECTION 0x9000
+#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x589A900ull
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x589A908ull
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x589A910ull
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x589A918ull
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x589A920ull
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x589A928ull
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x589A930ull
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x589A938ull
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x589A940ull
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x589A948ull
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x589A950ull
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x589A958ull
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x589A960ull
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x589A968ull
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x589A970ull
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x589A978ull
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC9_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmNIC9_QM0_AXUSER_SECURED_BASE 0x589AB00ull
+#define NIC9_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC9_QM0_AXUSER_SECURED_SECTION 0x8000
+#define mmNIC9_QM0_AXUSER_NONSECURED_BASE 0x589AB80ull
+#define NIC9_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC9_QM0_AXUSER_NONSECURED_SECTION 0x8000
+#define mmNIC9_QM0_DBG_HBW_BASE 0x589AC00ull
+#define NIC9_QM0_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC9_QM0_DBG_HBW_SECTION 0x8000
+#define mmNIC9_QM0_DBG_LBW_BASE 0x589AC80ull
+#define NIC9_QM0_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC9_QM0_DBG_LBW_SECTION 0x1000
+#define mmNIC9_QM0_CGM_BASE 0x589AD80ull
+#define NIC9_QM0_CGM_MAX_OFFSET 0xC000
+#define NIC9_QM0_CGM_SECTION 0x1000
+#define mmNIC9_QM0_SPECIAL_BASE 0x589AE80ull
+#define NIC9_QM0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_QM0_SPECIAL_SECTION 0x4180
+#define mmNIC9_QPC0_BASE 0x589F000ull
+#define NIC9_QPC0_MAX_OFFSET 0x1000
+#define NIC9_QPC0_SECTION 0x7200
+#define mmNIC9_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x589F720ull
+#define NIC9_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x589F728ull
+#define NIC9_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x589F730ull
+#define NIC9_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x589F738ull
+#define NIC9_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x589F740ull
+#define NIC9_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x589F748ull
+#define NIC9_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x589F750ull
+#define NIC9_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x589F758ull
+#define NIC9_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x589F760ull
+#define NIC9_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x589F768ull
+#define NIC9_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x589F770ull
+#define NIC9_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x589F778ull
+#define NIC9_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x589F780ull
+#define NIC9_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x589F788ull
+#define NIC9_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x589F790ull
+#define NIC9_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x589F798ull
+#define NIC9_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x589F7A0ull
+#define NIC9_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x589F7A8ull
+#define NIC9_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x589F7B0ull
+#define NIC9_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x589F7B8ull
+#define NIC9_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x589F7C0ull
+#define NIC9_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x589F7C8ull
+#define NIC9_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x589F7D0ull
+#define NIC9_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x589F7D8ull
+#define NIC9_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x589F7E0ull
+#define NIC9_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x589F7E8ull
+#define NIC9_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x589F7F0ull
+#define NIC9_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x589F7F8ull
+#define NIC9_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x589F800ull
+#define NIC9_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x589F808ull
+#define NIC9_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x589F810ull
+#define NIC9_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x589F818ull
+#define NIC9_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define mmNIC9_QPC0_AXUSER_CONG_QUE_BASE 0x589FB80ull
+#define NIC9_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC9_QPC0_AXUSER_CONG_QUE_SECTION 0x6000
+#define mmNIC9_QPC0_AXUSER_RXWQE_BASE 0x589FBE0ull
+#define NIC9_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC9_QPC0_AXUSER_RXWQE_SECTION 0x6000
+#define mmNIC9_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x589FC40ull
+#define NIC9_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC9_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define mmNIC9_QPC0_AXUSER_DB_FIFO_BASE 0x589FCA0ull
+#define NIC9_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC9_QPC0_AXUSER_DB_FIFO_SECTION 0x6000
+#define mmNIC9_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x589FD00ull
+#define NIC9_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC9_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define mmNIC9_QPC0_AXUSER_ERR_FIFO_BASE 0x589FD60ull
+#define NIC9_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC9_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000
+#define mmNIC9_QPC0_AXUSER_QPC_RESP_BASE 0x589FDC0ull
+#define NIC9_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC9_QPC0_AXUSER_QPC_RESP_SECTION 0x6000
+#define mmNIC9_QPC0_AXUSER_QPC_REQ_BASE 0x589FE20ull
+#define NIC9_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC9_QPC0_AXUSER_QPC_REQ_SECTION 0x6000
+#define mmNIC9_QPC0_SPECIAL_BASE 0x589FE80ull
+#define NIC9_QPC0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_QPC0_SPECIAL_SECTION 0x1800
+#define mmNIC9_UMR1_0_UNSECURE_DOORBELL0_BASE 0x58A0000ull
+#define NIC9_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC9_UMR1_0_UNSECURE_DOORBELL1_BASE 0x58A0080ull
+#define NIC9_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC9_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x58A0100ull
+#define NIC9_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC9_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x58A0180ull
+#define NIC9_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC9_UMR1_0_SPECIAL_BASE 0x58A0E80ull
+#define NIC9_UMR1_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR1_0_SPECIAL_SECTION 0x1800
+#define mmNIC9_UMR1_1_UNSECURE_DOORBELL0_BASE 0x58A1000ull
+#define NIC9_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC9_UMR1_1_UNSECURE_DOORBELL1_BASE 0x58A1080ull
+#define NIC9_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC9_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x58A1100ull
+#define NIC9_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC9_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x58A1180ull
+#define NIC9_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC9_UMR1_1_SPECIAL_BASE 0x58A1E80ull
+#define NIC9_UMR1_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR1_1_SPECIAL_SECTION 0x1800
+#define mmNIC9_UMR1_2_UNSECURE_DOORBELL0_BASE 0x58A2000ull
+#define NIC9_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC9_UMR1_2_UNSECURE_DOORBELL1_BASE 0x58A2080ull
+#define NIC9_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC9_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x58A2100ull
+#define NIC9_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC9_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x58A2180ull
+#define NIC9_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC9_UMR1_2_SPECIAL_BASE 0x58A2E80ull
+#define NIC9_UMR1_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR1_2_SPECIAL_SECTION 0x1800
+#define mmNIC9_UMR1_3_UNSECURE_DOORBELL0_BASE 0x58A3000ull
+#define NIC9_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC9_UMR1_3_UNSECURE_DOORBELL1_BASE 0x58A3080ull
+#define NIC9_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC9_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x58A3100ull
+#define NIC9_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC9_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x58A3180ull
+#define NIC9_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC9_UMR1_3_SPECIAL_BASE 0x58A3E80ull
+#define NIC9_UMR1_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR1_3_SPECIAL_SECTION 0x1800
+#define mmNIC9_UMR1_4_UNSECURE_DOORBELL0_BASE 0x58A4000ull
+#define NIC9_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC9_UMR1_4_UNSECURE_DOORBELL1_BASE 0x58A4080ull
+#define NIC9_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC9_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x58A4100ull
+#define NIC9_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC9_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x58A4180ull
+#define NIC9_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC9_UMR1_4_SPECIAL_BASE 0x58A4E80ull
+#define NIC9_UMR1_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR1_4_SPECIAL_SECTION 0x1800
+#define mmNIC9_UMR1_5_UNSECURE_DOORBELL0_BASE 0x58A5000ull
+#define NIC9_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC9_UMR1_5_UNSECURE_DOORBELL1_BASE 0x58A5080ull
+#define NIC9_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC9_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x58A5100ull
+#define NIC9_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC9_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x58A5180ull
+#define NIC9_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC9_UMR1_5_SPECIAL_BASE 0x58A5E80ull
+#define NIC9_UMR1_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR1_5_SPECIAL_SECTION 0x1800
+#define mmNIC9_UMR1_6_UNSECURE_DOORBELL0_BASE 0x58A6000ull
+#define NIC9_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC9_UMR1_6_UNSECURE_DOORBELL1_BASE 0x58A6080ull
+#define NIC9_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC9_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x58A6100ull
+#define NIC9_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC9_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x58A6180ull
+#define NIC9_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC9_UMR1_6_SPECIAL_BASE 0x58A6E80ull
+#define NIC9_UMR1_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR1_6_SPECIAL_SECTION 0x1800
+#define mmNIC9_UMR1_7_UNSECURE_DOORBELL0_BASE 0x58A7000ull
+#define NIC9_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC9_UMR1_7_UNSECURE_DOORBELL1_BASE 0x58A7080ull
+#define NIC9_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC9_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x58A7100ull
+#define NIC9_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC9_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x58A7180ull
+#define NIC9_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC9_UMR1_7_SPECIAL_BASE 0x58A7E80ull
+#define NIC9_UMR1_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR1_7_SPECIAL_SECTION 0x1800
+#define mmNIC9_UMR1_8_UNSECURE_DOORBELL0_BASE 0x58A8000ull
+#define NIC9_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC9_UMR1_8_UNSECURE_DOORBELL1_BASE 0x58A8080ull
+#define NIC9_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC9_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x58A8100ull
+#define NIC9_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC9_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x58A8180ull
+#define NIC9_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC9_UMR1_8_SPECIAL_BASE 0x58A8E80ull
+#define NIC9_UMR1_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR1_8_SPECIAL_SECTION 0x1800
+#define mmNIC9_UMR1_9_UNSECURE_DOORBELL0_BASE 0x58A9000ull
+#define NIC9_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC9_UMR1_9_UNSECURE_DOORBELL1_BASE 0x58A9080ull
+#define NIC9_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC9_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x58A9100ull
+#define NIC9_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC9_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x58A9180ull
+#define NIC9_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC9_UMR1_9_SPECIAL_BASE 0x58A9E80ull
+#define NIC9_UMR1_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR1_9_SPECIAL_SECTION 0x1800
+#define mmNIC9_UMR1_10_UNSECURE_DOORBELL0_BASE 0x58AA000ull
+#define NIC9_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC9_UMR1_10_UNSECURE_DOORBELL1_BASE 0x58AA080ull
+#define NIC9_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC9_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x58AA100ull
+#define NIC9_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC9_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x58AA180ull
+#define NIC9_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC9_UMR1_10_SPECIAL_BASE 0x58AAE80ull
+#define NIC9_UMR1_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR1_10_SPECIAL_SECTION 0x1800
+#define mmNIC9_UMR1_11_UNSECURE_DOORBELL0_BASE 0x58AB000ull
+#define NIC9_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC9_UMR1_11_UNSECURE_DOORBELL1_BASE 0x58AB080ull
+#define NIC9_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC9_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x58AB100ull
+#define NIC9_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC9_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x58AB180ull
+#define NIC9_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC9_UMR1_11_SPECIAL_BASE 0x58ABE80ull
+#define NIC9_UMR1_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR1_11_SPECIAL_SECTION 0x1800
+#define mmNIC9_UMR1_12_UNSECURE_DOORBELL0_BASE 0x58AC000ull
+#define NIC9_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC9_UMR1_12_UNSECURE_DOORBELL1_BASE 0x58AC080ull
+#define NIC9_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC9_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x58AC100ull
+#define NIC9_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC9_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x58AC180ull
+#define NIC9_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC9_UMR1_12_SPECIAL_BASE 0x58ACE80ull
+#define NIC9_UMR1_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR1_12_SPECIAL_SECTION 0x1800
+#define mmNIC9_UMR1_13_UNSECURE_DOORBELL0_BASE 0x58AD000ull
+#define NIC9_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC9_UMR1_13_UNSECURE_DOORBELL1_BASE 0x58AD080ull
+#define NIC9_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC9_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x58AD100ull
+#define NIC9_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC9_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x58AD180ull
+#define NIC9_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC9_UMR1_13_SPECIAL_BASE 0x58ADE80ull
+#define NIC9_UMR1_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR1_13_SPECIAL_SECTION 0x1800
+#define mmNIC9_UMR1_14_UNSECURE_DOORBELL0_BASE 0x58AE000ull
+#define NIC9_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC9_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC9_UMR1_14_UNSECURE_DOORBELL1_BASE 0x58AE080ull
+#define NIC9_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC9_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC9_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x58AE100ull
+#define NIC9_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC9_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC9_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x58AE180ull
+#define NIC9_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC9_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC9_UMR1_14_SPECIAL_BASE 0x58AEE80ull
+#define NIC9_UMR1_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_UMR1_14_SPECIAL_SECTION 0x1180
+#define mmNIC9_QM_DCCM1_BASE 0x58B0000ull
+#define NIC9_QM_DCCM1_MAX_OFFSET 0x4000
+#define NIC9_QM_DCCM1_SECTION 0x8000
+#define mmNIC9_QM_ARC_AUX1_BASE 0x58B8000ull
+#define NIC9_QM_ARC_AUX1_MAX_OFFSET 0x1000
+#define NIC9_QM_ARC_AUX1_SECTION 0xE800
+#define mmNIC9_QM_ARC_AUX1_SPECIAL_BASE 0x58B8E80ull
+#define NIC9_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_QM_ARC_AUX1_SPECIAL_SECTION 0x1180
+#define mmNIC9_QM1_BASE 0x58BA000ull
+#define NIC9_QM1_MAX_OFFSET 0x1000
+#define NIC9_QM1_SECTION 0x9000
+#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x58BA900ull
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x58BA908ull
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x58BA910ull
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x58BA918ull
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x58BA920ull
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x58BA928ull
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x58BA930ull
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x58BA938ull
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x58BA940ull
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x58BA948ull
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x58BA950ull
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x58BA958ull
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x58BA960ull
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x58BA968ull
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x58BA970ull
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x58BA978ull
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC9_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmNIC9_QM1_AXUSER_SECURED_BASE 0x58BAB00ull
+#define NIC9_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC9_QM1_AXUSER_SECURED_SECTION 0x8000
+#define mmNIC9_QM1_AXUSER_NONSECURED_BASE 0x58BAB80ull
+#define NIC9_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC9_QM1_AXUSER_NONSECURED_SECTION 0x8000
+#define mmNIC9_QM1_DBG_HBW_BASE 0x58BAC00ull
+#define NIC9_QM1_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC9_QM1_DBG_HBW_SECTION 0x8000
+#define mmNIC9_QM1_DBG_LBW_BASE 0x58BAC80ull
+#define NIC9_QM1_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC9_QM1_DBG_LBW_SECTION 0x1000
+#define mmNIC9_QM1_CGM_BASE 0x58BAD80ull
+#define NIC9_QM1_CGM_MAX_OFFSET 0xC000
+#define NIC9_QM1_CGM_SECTION 0x1000
+#define mmNIC9_QM1_SPECIAL_BASE 0x58BAE80ull
+#define NIC9_QM1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_QM1_SPECIAL_SECTION 0x4180
+#define mmNIC9_QPC1_BASE 0x58BF000ull
+#define NIC9_QPC1_MAX_OFFSET 0x1000
+#define NIC9_QPC1_SECTION 0x7200
+#define mmNIC9_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x58BF720ull
+#define NIC9_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x58BF728ull
+#define NIC9_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x58BF730ull
+#define NIC9_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x58BF738ull
+#define NIC9_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x58BF740ull
+#define NIC9_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x58BF748ull
+#define NIC9_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x58BF750ull
+#define NIC9_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x58BF758ull
+#define NIC9_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x58BF760ull
+#define NIC9_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x58BF768ull
+#define NIC9_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x58BF770ull
+#define NIC9_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x58BF778ull
+#define NIC9_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x58BF780ull
+#define NIC9_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x58BF788ull
+#define NIC9_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x58BF790ull
+#define NIC9_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x58BF798ull
+#define NIC9_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x58BF7A0ull
+#define NIC9_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x58BF7A8ull
+#define NIC9_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x58BF7B0ull
+#define NIC9_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x58BF7B8ull
+#define NIC9_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x58BF7C0ull
+#define NIC9_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x58BF7C8ull
+#define NIC9_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x58BF7D0ull
+#define NIC9_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x58BF7D8ull
+#define NIC9_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x58BF7E0ull
+#define NIC9_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x58BF7E8ull
+#define NIC9_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x58BF7F0ull
+#define NIC9_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x58BF7F8ull
+#define NIC9_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x58BF800ull
+#define NIC9_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x58BF808ull
+#define NIC9_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x58BF810ull
+#define NIC9_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC9_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x58BF818ull
+#define NIC9_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC9_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define mmNIC9_QPC1_AXUSER_CONG_QUE_BASE 0x58BFB80ull
+#define NIC9_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC9_QPC1_AXUSER_CONG_QUE_SECTION 0x6000
+#define mmNIC9_QPC1_AXUSER_RXWQE_BASE 0x58BFBE0ull
+#define NIC9_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC9_QPC1_AXUSER_RXWQE_SECTION 0x6000
+#define mmNIC9_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x58BFC40ull
+#define NIC9_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC9_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define mmNIC9_QPC1_AXUSER_DB_FIFO_BASE 0x58BFCA0ull
+#define NIC9_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC9_QPC1_AXUSER_DB_FIFO_SECTION 0x6000
+#define mmNIC9_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x58BFD00ull
+#define NIC9_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC9_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define mmNIC9_QPC1_AXUSER_ERR_FIFO_BASE 0x58BFD60ull
+#define NIC9_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC9_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000
+#define mmNIC9_QPC1_AXUSER_QPC_RESP_BASE 0x58BFDC0ull
+#define NIC9_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC9_QPC1_AXUSER_QPC_RESP_SECTION 0x6000
+#define mmNIC9_QPC1_AXUSER_QPC_REQ_BASE 0x58BFE20ull
+#define NIC9_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC9_QPC1_AXUSER_QPC_REQ_SECTION 0x6000
+#define mmNIC9_QPC1_SPECIAL_BASE 0x58BFE80ull
+#define NIC9_QPC1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_QPC1_SPECIAL_SECTION 0x8180
+#define mmNIC9_TMR_BASE 0x58C8000ull
+#define NIC9_TMR_MAX_OFFSET 0x1000
+#define NIC9_TMR_SECTION 0xD600
+#define mmNIC9_TMR_AXUSER_TMR_FREE_LIST_BASE 0x58C8D60ull
+#define NIC9_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000
+#define NIC9_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000
+#define mmNIC9_TMR_AXUSER_TMR_FIFO_BASE 0x58C8DC0ull
+#define NIC9_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000
+#define NIC9_TMR_AXUSER_TMR_FIFO_SECTION 0x6000
+#define mmNIC9_TMR_AXUSER_TMR_FSM_BASE 0x58C8E20ull
+#define NIC9_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000
+#define NIC9_TMR_AXUSER_TMR_FSM_SECTION 0x6000
+#define mmNIC9_TMR_SPECIAL_BASE 0x58C8E80ull
+#define NIC9_TMR_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_TMR_SPECIAL_SECTION 0x1800
+#define mmNIC9_RXB_CORE_BASE 0x58C9000ull
+#define NIC9_RXB_CORE_MAX_OFFSET 0x1000
+#define NIC9_RXB_CORE_SECTION 0x6100
+#define mmNIC9_RXB_CORE_SCT_AWUSER_BASE 0x58C9610ull
+#define NIC9_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000
+#define NIC9_RXB_CORE_SCT_AWUSER_SECTION 0x8700
+#define mmNIC9_RXB_CORE_SPECIAL_BASE 0x58C9E80ull
+#define NIC9_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_RXB_CORE_SPECIAL_SECTION 0x1800
+#define mmNIC9_RXE0_BASE 0x58CA000ull
+#define NIC9_RXE0_MAX_OFFSET 0x1000
+#define NIC9_RXE0_SECTION 0x9000
+#define mmNIC9_RXE0_WQE_ARUSER_BASE 0x58CA900ull
+#define NIC9_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC9_RXE0_WQE_ARUSER_SECTION 0x5800
+#define mmNIC9_RXE0_SPECIAL_BASE 0x58CAE80ull
+#define NIC9_RXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_RXE0_SPECIAL_SECTION 0x1800
+#define mmNIC9_RXE1_BASE 0x58CB000ull
+#define NIC9_RXE1_MAX_OFFSET 0x1000
+#define NIC9_RXE1_SECTION 0x9000
+#define mmNIC9_RXE1_WQE_ARUSER_BASE 0x58CB900ull
+#define NIC9_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC9_RXE1_WQE_ARUSER_SECTION 0x5800
+#define mmNIC9_RXE1_SPECIAL_BASE 0x58CBE80ull
+#define NIC9_RXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_RXE1_SPECIAL_SECTION 0x1800
+#define mmNIC9_RXE0_AXUSER_AXUSER_CQ0_BASE 0x58CC000ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define mmNIC9_RXE0_AXUSER_AXUSER_CQ1_BASE 0x58CC050ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define mmNIC9_RXE0_AXUSER_AXUSER_CQ2_BASE 0x58CC0A0ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define mmNIC9_RXE0_AXUSER_AXUSER_CQ3_BASE 0x58CC0F0ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define mmNIC9_RXE0_AXUSER_AXUSER_CQ4_BASE 0x58CC140ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define mmNIC9_RXE0_AXUSER_AXUSER_CQ5_BASE 0x58CC190ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define mmNIC9_RXE0_AXUSER_AXUSER_CQ6_BASE 0x58CC1E0ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define mmNIC9_RXE0_AXUSER_AXUSER_CQ7_BASE 0x58CC230ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define mmNIC9_RXE0_AXUSER_AXUSER_CQ8_BASE 0x58CC280ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define mmNIC9_RXE0_AXUSER_AXUSER_CQ9_BASE 0x58CC2D0ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define mmNIC9_RXE0_AXUSER_AXUSER_CQ10_BASE 0x58CC320ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define mmNIC9_RXE0_AXUSER_AXUSER_CQ11_BASE 0x58CC370ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define mmNIC9_RXE0_AXUSER_AXUSER_CQ12_BASE 0x58CC3C0ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define mmNIC9_RXE0_AXUSER_AXUSER_CQ13_BASE 0x58CC410ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define mmNIC9_RXE0_AXUSER_AXUSER_CQ14_BASE 0x58CC460ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define mmNIC9_RXE0_AXUSER_AXUSER_CQ15_BASE 0x58CC4B0ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define mmNIC9_RXE0_AXUSER_AXUSER_CQ16_BASE 0x58CC500ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define mmNIC9_RXE0_AXUSER_AXUSER_CQ17_BASE 0x58CC550ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define mmNIC9_RXE0_AXUSER_AXUSER_CQ18_BASE 0x58CC5A0ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define mmNIC9_RXE0_AXUSER_AXUSER_CQ19_BASE 0x58CC5F0ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define mmNIC9_RXE0_AXUSER_AXUSER_CQ20_BASE 0x58CC640ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define mmNIC9_RXE0_AXUSER_AXUSER_CQ21_BASE 0x58CC690ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define mmNIC9_RXE0_AXUSER_AXUSER_CQ22_BASE 0x58CC6E0ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define mmNIC9_RXE0_AXUSER_AXUSER_CQ23_BASE 0x58CC730ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define mmNIC9_RXE0_AXUSER_AXUSER_CQ24_BASE 0x58CC780ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define mmNIC9_RXE0_AXUSER_AXUSER_CQ25_BASE 0x58CC7D0ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define mmNIC9_RXE0_AXUSER_AXUSER_CQ26_BASE 0x58CC820ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define mmNIC9_RXE0_AXUSER_AXUSER_CQ27_BASE 0x58CC870ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define mmNIC9_RXE0_AXUSER_AXUSER_CQ28_BASE 0x58CC8C0ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define mmNIC9_RXE0_AXUSER_AXUSER_CQ29_BASE 0x58CC910ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define mmNIC9_RXE0_AXUSER_AXUSER_CQ30_BASE 0x58CC960ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define mmNIC9_RXE0_AXUSER_AXUSER_CQ31_BASE 0x58CC9B0ull
+#define NIC9_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC9_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define mmNIC9_RXE0_AXUSER_SPECIAL_BASE 0x58CCE80ull
+#define NIC9_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_RXE0_AXUSER_SPECIAL_SECTION 0x1800
+#define mmNIC9_RXE1_AXUSER_AXUSER_CQ0_BASE 0x58CD000ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define mmNIC9_RXE1_AXUSER_AXUSER_CQ1_BASE 0x58CD050ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define mmNIC9_RXE1_AXUSER_AXUSER_CQ2_BASE 0x58CD0A0ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define mmNIC9_RXE1_AXUSER_AXUSER_CQ3_BASE 0x58CD0F0ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define mmNIC9_RXE1_AXUSER_AXUSER_CQ4_BASE 0x58CD140ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define mmNIC9_RXE1_AXUSER_AXUSER_CQ5_BASE 0x58CD190ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define mmNIC9_RXE1_AXUSER_AXUSER_CQ6_BASE 0x58CD1E0ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define mmNIC9_RXE1_AXUSER_AXUSER_CQ7_BASE 0x58CD230ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define mmNIC9_RXE1_AXUSER_AXUSER_CQ8_BASE 0x58CD280ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define mmNIC9_RXE1_AXUSER_AXUSER_CQ9_BASE 0x58CD2D0ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define mmNIC9_RXE1_AXUSER_AXUSER_CQ10_BASE 0x58CD320ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define mmNIC9_RXE1_AXUSER_AXUSER_CQ11_BASE 0x58CD370ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define mmNIC9_RXE1_AXUSER_AXUSER_CQ12_BASE 0x58CD3C0ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define mmNIC9_RXE1_AXUSER_AXUSER_CQ13_BASE 0x58CD410ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define mmNIC9_RXE1_AXUSER_AXUSER_CQ14_BASE 0x58CD460ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define mmNIC9_RXE1_AXUSER_AXUSER_CQ15_BASE 0x58CD4B0ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define mmNIC9_RXE1_AXUSER_AXUSER_CQ16_BASE 0x58CD500ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define mmNIC9_RXE1_AXUSER_AXUSER_CQ17_BASE 0x58CD550ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define mmNIC9_RXE1_AXUSER_AXUSER_CQ18_BASE 0x58CD5A0ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define mmNIC9_RXE1_AXUSER_AXUSER_CQ19_BASE 0x58CD5F0ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define mmNIC9_RXE1_AXUSER_AXUSER_CQ20_BASE 0x58CD640ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define mmNIC9_RXE1_AXUSER_AXUSER_CQ21_BASE 0x58CD690ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define mmNIC9_RXE1_AXUSER_AXUSER_CQ22_BASE 0x58CD6E0ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define mmNIC9_RXE1_AXUSER_AXUSER_CQ23_BASE 0x58CD730ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define mmNIC9_RXE1_AXUSER_AXUSER_CQ24_BASE 0x58CD780ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define mmNIC9_RXE1_AXUSER_AXUSER_CQ25_BASE 0x58CD7D0ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define mmNIC9_RXE1_AXUSER_AXUSER_CQ26_BASE 0x58CD820ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define mmNIC9_RXE1_AXUSER_AXUSER_CQ27_BASE 0x58CD870ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define mmNIC9_RXE1_AXUSER_AXUSER_CQ28_BASE 0x58CD8C0ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define mmNIC9_RXE1_AXUSER_AXUSER_CQ29_BASE 0x58CD910ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define mmNIC9_RXE1_AXUSER_AXUSER_CQ30_BASE 0x58CD960ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define mmNIC9_RXE1_AXUSER_AXUSER_CQ31_BASE 0x58CD9B0ull
+#define NIC9_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC9_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define mmNIC9_RXE1_AXUSER_SPECIAL_BASE 0x58CDE80ull
+#define NIC9_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_RXE1_AXUSER_SPECIAL_SECTION 0x2180
+#define mmNIC9_TXS0_BASE 0x58D0000ull
+#define NIC9_TXS0_MAX_OFFSET 0x1000
+#define NIC9_TXS0_SECTION 0xE800
+#define mmNIC9_TXS0_SPECIAL_BASE 0x58D0E80ull
+#define NIC9_TXS0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_TXS0_SPECIAL_SECTION 0x1800
+#define mmNIC9_TXS1_BASE 0x58D1000ull
+#define NIC9_TXS1_MAX_OFFSET 0x1000
+#define NIC9_TXS1_SECTION 0xE800
+#define mmNIC9_TXS1_SPECIAL_BASE 0x58D1E80ull
+#define NIC9_TXS1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_TXS1_SPECIAL_SECTION 0x1800
+#define mmNIC9_TXE0_BASE 0x58D2000ull
+#define NIC9_TXE0_MAX_OFFSET 0x1000
+#define NIC9_TXE0_SECTION 0xE800
+#define mmNIC9_TXE0_SPECIAL_BASE 0x58D2E80ull
+#define NIC9_TXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_TXE0_SPECIAL_SECTION 0x1800
+#define mmNIC9_TXE1_BASE 0x58D3000ull
+#define NIC9_TXE1_MAX_OFFSET 0x1000
+#define NIC9_TXE1_SECTION 0xE800
+#define mmNIC9_TXE1_SPECIAL_BASE 0x58D3E80ull
+#define NIC9_TXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_TXE1_SPECIAL_SECTION 0x1800
+#define mmNIC9_TXB_BASE 0x58D4000ull
+#define NIC9_TXB_MAX_OFFSET 0x1000
+#define NIC9_TXB_SECTION 0xE800
+#define mmNIC9_TXB_SPECIAL_BASE 0x58D4E80ull
+#define NIC9_TXB_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_TXB_SPECIAL_SECTION 0x1800
+#define mmNIC9_MSTR_IF_RR_SHRD_HBW_BASE 0x58D5000ull
+#define NIC9_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define NIC9_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmNIC9_MSTR_IF_RR_PRVT_HBW_BASE 0x58D5200ull
+#define NIC9_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define NIC9_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmNIC9_MSTR_IF_RR_SHRD_LBW_BASE 0x58D5400ull
+#define NIC9_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define NIC9_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmNIC9_MSTR_IF_RR_PRVT_LBW_BASE 0x58D5600ull
+#define NIC9_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define NIC9_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmNIC9_MSTR_IF_E2E_CRDT_BASE 0x58D5800ull
+#define NIC9_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define NIC9_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmNIC9_MSTR_IF_AXUSER_BASE 0x58D5A80ull
+#define NIC9_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define NIC9_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmNIC9_MSTR_IF_DBG_HBW_BASE 0x58D5B00ull
+#define NIC9_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC9_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmNIC9_MSTR_IF_DBG_LBW_BASE 0x58D5B80ull
+#define NIC9_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC9_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmNIC9_MSTR_IF_CORE_HBW_BASE 0x58D5C00ull
+#define NIC9_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define NIC9_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmNIC9_MSTR_IF_CORE_LBW_BASE 0x58D5D80ull
+#define NIC9_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define NIC9_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmNIC9_MSTR_IF_SPECIAL_BASE 0x58D5E80ull
+#define NIC9_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmNIC9_TX_AXUSER_BASE 0x58D6000ull
+#define NIC9_TX_AXUSER_MAX_OFFSET 0x5000
+#define NIC9_TX_AXUSER_SECTION 0x2000
+#define mmNIC9_SERDES0_BASE 0x58D8000ull
+#define NIC9_SERDES0_MAX_OFFSET 0x3E40
+#define NIC9_SERDES0_SECTION 0x4000
+#define mmNIC9_SERDES1_BASE 0x58DC000ull
+#define NIC9_SERDES1_MAX_OFFSET 0x3E40
+#define NIC9_SERDES1_SECTION 0x4000
+#define mmNIC9_PHY_BASE 0x58E0000ull
+#define NIC9_PHY_MAX_OFFSET 0x1000
+#define NIC9_PHY_SECTION 0xE800
+#define mmNIC9_PHY_SPECIAL_BASE 0x58E0E80ull
+#define NIC9_PHY_SPECIAL_MAX_OFFSET 0x1800
+#define NIC9_PHY_SPECIAL_SECTION 0x7180
+#define mmPRT9_MAC_AUX_BASE 0x58E8000ull
+#define PRT9_MAC_AUX_MAX_OFFSET 0x1000
+#define PRT9_MAC_AUX_SECTION 0xE800
+#define mmPRT9_MAC_AUX_SPECIAL_BASE 0x58E8E80ull
+#define PRT9_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define PRT9_MAC_AUX_SPECIAL_SECTION 0x1800
+#define mmPRT9_MAC_CORE_BASE 0x58E9000ull
+#define PRT9_MAC_CORE_MAX_OFFSET 0x1000
+#define PRT9_MAC_CORE_SECTION 0xE800
+#define mmPRT9_MAC_CORE_SPECIAL_BASE 0x58E9E80ull
+#define PRT9_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define PRT9_MAC_CORE_SPECIAL_SECTION 0x1800
+#define mmNIC9_MAC_RS_FEC_BASE 0x58EA000ull
+#define NIC9_MAC_RS_FEC_MAX_OFFSET 0x2DC0
+#define NIC9_MAC_RS_FEC_SECTION 0x1000
+#define mmNIC9_MAC_GLOB_STAT_CONTROL_REG_BASE 0x58EB000ull
+#define NIC9_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000
+#define NIC9_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000
+#define mmNIC9_MAC_GLOB_STAT_RX0_BASE 0x58EB100ull
+#define NIC9_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00
+#define NIC9_MAC_GLOB_STAT_RX0_SECTION 0x8C00
+#define mmNIC9_MAC_GLOB_STAT_RX1_BASE 0x58EB18Cull
+#define NIC9_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00
+#define NIC9_MAC_GLOB_STAT_RX1_SECTION 0x8C00
+#define mmNIC9_MAC_GLOB_STAT_RX2_BASE 0x58EB218ull
+#define NIC9_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00
+#define NIC9_MAC_GLOB_STAT_RX2_SECTION 0x8C00
+#define mmNIC9_MAC_GLOB_STAT_RX3_BASE 0x58EB2A4ull
+#define NIC9_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00
+#define NIC9_MAC_GLOB_STAT_RX3_SECTION 0x8C00
+#define mmNIC9_MAC_GLOB_STAT_TX0_BASE 0x58EB330ull
+#define NIC9_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800
+#define NIC9_MAC_GLOB_STAT_TX0_SECTION 0x6800
+#define mmNIC9_MAC_GLOB_STAT_TX1_BASE 0x58EB398ull
+#define NIC9_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800
+#define NIC9_MAC_GLOB_STAT_TX1_SECTION 0x6800
+#define mmNIC9_MAC_GLOB_STAT_TX2_BASE 0x58EB400ull
+#define NIC9_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800
+#define NIC9_MAC_GLOB_STAT_TX2_SECTION 0x6800
+#define mmNIC9_MAC_GLOB_STAT_TX3_BASE 0x58EB468ull
+#define NIC9_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800
+#define NIC9_MAC_GLOB_STAT_TX3_SECTION 0x3980
+#define mmNIC9_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x58EB800ull
+#define NIC9_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0
+#define NIC9_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000
+#define mmNIC9_MAC_CH0_MAC_PCS_BASE 0x58EC000ull
+#define NIC9_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC9_MAC_CH0_MAC_PCS_SECTION 0x4000
+#define mmNIC9_MAC_CH0_MAC_128_BASE 0x58EC400ull
+#define NIC9_MAC_CH0_MAC_128_MAX_OFFSET 0xA400
+#define NIC9_MAC_CH0_MAC_128_SECTION 0x4000
+#define mmNIC9_MAC_CH0_MAC_AN_BASE 0x58EC800ull
+#define NIC9_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400
+#define NIC9_MAC_CH0_MAC_AN_SECTION 0x8000
+#define mmNIC9_MAC_CH1_MAC_PCS_BASE 0x58ED000ull
+#define NIC9_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC9_MAC_CH1_MAC_PCS_SECTION 0x4000
+#define mmNIC9_MAC_CH1_MAC_128_BASE 0x58ED400ull
+#define NIC9_MAC_CH1_MAC_128_MAX_OFFSET 0xA400
+#define NIC9_MAC_CH1_MAC_128_SECTION 0x4000
+#define mmNIC9_MAC_CH1_MAC_AN_BASE 0x58ED800ull
+#define NIC9_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400
+#define NIC9_MAC_CH1_MAC_AN_SECTION 0x8000
+#define mmNIC9_MAC_CH2_MAC_PCS_BASE 0x58EE000ull
+#define NIC9_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC9_MAC_CH2_MAC_PCS_SECTION 0x4000
+#define mmNIC9_MAC_CH2_MAC_128_BASE 0x58EE400ull
+#define NIC9_MAC_CH2_MAC_128_MAX_OFFSET 0xA400
+#define NIC9_MAC_CH2_MAC_128_SECTION 0x4000
+#define mmNIC9_MAC_CH2_MAC_AN_BASE 0x58EE800ull
+#define NIC9_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400
+#define NIC9_MAC_CH2_MAC_AN_SECTION 0x8000
+#define mmNIC9_MAC_CH3_MAC_PCS_BASE 0x58EF000ull
+#define NIC9_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC9_MAC_CH3_MAC_PCS_SECTION 0x4000
+#define mmNIC9_MAC_CH3_MAC_128_BASE 0x58EF400ull
+#define NIC9_MAC_CH3_MAC_128_MAX_OFFSET 0xA400
+#define NIC9_MAC_CH3_MAC_128_SECTION 0x4000
+#define mmNIC9_MAC_CH3_MAC_AN_BASE 0x58EF800ull
+#define NIC9_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400
+#define NIC9_MAC_CH3_MAC_AN_SECTION 0x10800
+#define mmNIC10_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5900000ull
+#define NIC10_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC10_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5900080ull
+#define NIC10_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC10_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5900100ull
+#define NIC10_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC10_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5900180ull
+#define NIC10_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC10_UMR0_0_SPECIAL_BASE 0x5900E80ull
+#define NIC10_UMR0_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR0_0_SPECIAL_SECTION 0x1800
+#define mmNIC10_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5901000ull
+#define NIC10_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC10_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5901080ull
+#define NIC10_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC10_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5901100ull
+#define NIC10_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC10_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5901180ull
+#define NIC10_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC10_UMR0_1_SPECIAL_BASE 0x5901E80ull
+#define NIC10_UMR0_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR0_1_SPECIAL_SECTION 0x1800
+#define mmNIC10_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5902000ull
+#define NIC10_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC10_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5902080ull
+#define NIC10_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC10_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5902100ull
+#define NIC10_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC10_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5902180ull
+#define NIC10_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC10_UMR0_2_SPECIAL_BASE 0x5902E80ull
+#define NIC10_UMR0_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR0_2_SPECIAL_SECTION 0x1800
+#define mmNIC10_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5903000ull
+#define NIC10_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC10_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5903080ull
+#define NIC10_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC10_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5903100ull
+#define NIC10_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC10_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5903180ull
+#define NIC10_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC10_UMR0_3_SPECIAL_BASE 0x5903E80ull
+#define NIC10_UMR0_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR0_3_SPECIAL_SECTION 0x1800
+#define mmNIC10_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5904000ull
+#define NIC10_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC10_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5904080ull
+#define NIC10_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC10_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5904100ull
+#define NIC10_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC10_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5904180ull
+#define NIC10_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC10_UMR0_4_SPECIAL_BASE 0x5904E80ull
+#define NIC10_UMR0_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR0_4_SPECIAL_SECTION 0x1800
+#define mmNIC10_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5905000ull
+#define NIC10_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC10_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5905080ull
+#define NIC10_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC10_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5905100ull
+#define NIC10_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC10_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5905180ull
+#define NIC10_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC10_UMR0_5_SPECIAL_BASE 0x5905E80ull
+#define NIC10_UMR0_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR0_5_SPECIAL_SECTION 0x1800
+#define mmNIC10_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5906000ull
+#define NIC10_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC10_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5906080ull
+#define NIC10_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC10_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5906100ull
+#define NIC10_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC10_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5906180ull
+#define NIC10_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC10_UMR0_6_SPECIAL_BASE 0x5906E80ull
+#define NIC10_UMR0_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR0_6_SPECIAL_SECTION 0x1800
+#define mmNIC10_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5907000ull
+#define NIC10_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC10_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5907080ull
+#define NIC10_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC10_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5907100ull
+#define NIC10_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC10_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5907180ull
+#define NIC10_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC10_UMR0_7_SPECIAL_BASE 0x5907E80ull
+#define NIC10_UMR0_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR0_7_SPECIAL_SECTION 0x1800
+#define mmNIC10_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5908000ull
+#define NIC10_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC10_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5908080ull
+#define NIC10_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC10_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5908100ull
+#define NIC10_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC10_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5908180ull
+#define NIC10_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC10_UMR0_8_SPECIAL_BASE 0x5908E80ull
+#define NIC10_UMR0_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR0_8_SPECIAL_SECTION 0x1800
+#define mmNIC10_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5909000ull
+#define NIC10_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC10_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5909080ull
+#define NIC10_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC10_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5909100ull
+#define NIC10_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC10_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5909180ull
+#define NIC10_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC10_UMR0_9_SPECIAL_BASE 0x5909E80ull
+#define NIC10_UMR0_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR0_9_SPECIAL_SECTION 0x1800
+#define mmNIC10_UMR0_10_UNSECURE_DOORBELL0_BASE 0x590A000ull
+#define NIC10_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC10_UMR0_10_UNSECURE_DOORBELL1_BASE 0x590A080ull
+#define NIC10_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC10_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x590A100ull
+#define NIC10_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC10_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x590A180ull
+#define NIC10_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC10_UMR0_10_SPECIAL_BASE 0x590AE80ull
+#define NIC10_UMR0_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR0_10_SPECIAL_SECTION 0x1800
+#define mmNIC10_UMR0_11_UNSECURE_DOORBELL0_BASE 0x590B000ull
+#define NIC10_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC10_UMR0_11_UNSECURE_DOORBELL1_BASE 0x590B080ull
+#define NIC10_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC10_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x590B100ull
+#define NIC10_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC10_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x590B180ull
+#define NIC10_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC10_UMR0_11_SPECIAL_BASE 0x590BE80ull
+#define NIC10_UMR0_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR0_11_SPECIAL_SECTION 0x1800
+#define mmNIC10_UMR0_12_UNSECURE_DOORBELL0_BASE 0x590C000ull
+#define NIC10_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC10_UMR0_12_UNSECURE_DOORBELL1_BASE 0x590C080ull
+#define NIC10_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC10_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x590C100ull
+#define NIC10_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC10_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x590C180ull
+#define NIC10_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC10_UMR0_12_SPECIAL_BASE 0x590CE80ull
+#define NIC10_UMR0_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR0_12_SPECIAL_SECTION 0x1800
+#define mmNIC10_UMR0_13_UNSECURE_DOORBELL0_BASE 0x590D000ull
+#define NIC10_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC10_UMR0_13_UNSECURE_DOORBELL1_BASE 0x590D080ull
+#define NIC10_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC10_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x590D100ull
+#define NIC10_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC10_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x590D180ull
+#define NIC10_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC10_UMR0_13_SPECIAL_BASE 0x590DE80ull
+#define NIC10_UMR0_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR0_13_SPECIAL_SECTION 0x1800
+#define mmNIC10_UMR0_14_UNSECURE_DOORBELL0_BASE 0x590E000ull
+#define NIC10_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC10_UMR0_14_UNSECURE_DOORBELL1_BASE 0x590E080ull
+#define NIC10_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC10_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x590E100ull
+#define NIC10_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC10_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x590E180ull
+#define NIC10_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC10_UMR0_14_SPECIAL_BASE 0x590EE80ull
+#define NIC10_UMR0_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR0_14_SPECIAL_SECTION 0x1180
+#define mmNIC10_QM_DCCM0_BASE 0x5910000ull
+#define NIC10_QM_DCCM0_MAX_OFFSET 0x4000
+#define NIC10_QM_DCCM0_SECTION 0x8000
+#define mmNIC10_QM_ARC_AUX0_BASE 0x5918000ull
+#define NIC10_QM_ARC_AUX0_MAX_OFFSET 0x1000
+#define NIC10_QM_ARC_AUX0_SECTION 0xE800
+#define mmNIC10_QM_ARC_AUX0_SPECIAL_BASE 0x5918E80ull
+#define NIC10_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_QM_ARC_AUX0_SPECIAL_SECTION 0x1180
+#define mmNIC10_QM0_BASE 0x591A000ull
+#define NIC10_QM0_MAX_OFFSET 0x1000
+#define NIC10_QM0_SECTION 0x9000
+#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x591A900ull
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x591A908ull
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x591A910ull
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x591A918ull
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x591A920ull
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x591A928ull
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x591A930ull
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x591A938ull
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x591A940ull
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x591A948ull
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x591A950ull
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x591A958ull
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x591A960ull
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x591A968ull
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x591A970ull
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x591A978ull
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC10_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmNIC10_QM0_AXUSER_SECURED_BASE 0x591AB00ull
+#define NIC10_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC10_QM0_AXUSER_SECURED_SECTION 0x8000
+#define mmNIC10_QM0_AXUSER_NONSECURED_BASE 0x591AB80ull
+#define NIC10_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC10_QM0_AXUSER_NONSECURED_SECTION 0x8000
+#define mmNIC10_QM0_DBG_HBW_BASE 0x591AC00ull
+#define NIC10_QM0_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC10_QM0_DBG_HBW_SECTION 0x8000
+#define mmNIC10_QM0_DBG_LBW_BASE 0x591AC80ull
+#define NIC10_QM0_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC10_QM0_DBG_LBW_SECTION 0x1000
+#define mmNIC10_QM0_CGM_BASE 0x591AD80ull
+#define NIC10_QM0_CGM_MAX_OFFSET 0xC000
+#define NIC10_QM0_CGM_SECTION 0x1000
+#define mmNIC10_QM0_SPECIAL_BASE 0x591AE80ull
+#define NIC10_QM0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_QM0_SPECIAL_SECTION 0x4180
+#define mmNIC10_QPC0_BASE 0x591F000ull
+#define NIC10_QPC0_MAX_OFFSET 0x1000
+#define NIC10_QPC0_SECTION 0x7200
+#define mmNIC10_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x591F720ull
+#define NIC10_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x591F728ull
+#define NIC10_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x591F730ull
+#define NIC10_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x591F738ull
+#define NIC10_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x591F740ull
+#define NIC10_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x591F748ull
+#define NIC10_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x591F750ull
+#define NIC10_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x591F758ull
+#define NIC10_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x591F760ull
+#define NIC10_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x591F768ull
+#define NIC10_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x591F770ull
+#define NIC10_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x591F778ull
+#define NIC10_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x591F780ull
+#define NIC10_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x591F788ull
+#define NIC10_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x591F790ull
+#define NIC10_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x591F798ull
+#define NIC10_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x591F7A0ull
+#define NIC10_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x591F7A8ull
+#define NIC10_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x591F7B0ull
+#define NIC10_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x591F7B8ull
+#define NIC10_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x591F7C0ull
+#define NIC10_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x591F7C8ull
+#define NIC10_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x591F7D0ull
+#define NIC10_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x591F7D8ull
+#define NIC10_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x591F7E0ull
+#define NIC10_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x591F7E8ull
+#define NIC10_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x591F7F0ull
+#define NIC10_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x591F7F8ull
+#define NIC10_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x591F800ull
+#define NIC10_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x591F808ull
+#define NIC10_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x591F810ull
+#define NIC10_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x591F818ull
+#define NIC10_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define mmNIC10_QPC0_AXUSER_CONG_QUE_BASE 0x591FB80ull
+#define NIC10_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC10_QPC0_AXUSER_CONG_QUE_SECTION 0x6000
+#define mmNIC10_QPC0_AXUSER_RXWQE_BASE 0x591FBE0ull
+#define NIC10_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC10_QPC0_AXUSER_RXWQE_SECTION 0x6000
+#define mmNIC10_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x591FC40ull
+#define NIC10_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC10_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define mmNIC10_QPC0_AXUSER_DB_FIFO_BASE 0x591FCA0ull
+#define NIC10_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC10_QPC0_AXUSER_DB_FIFO_SECTION 0x6000
+#define mmNIC10_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x591FD00ull
+#define NIC10_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC10_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define mmNIC10_QPC0_AXUSER_ERR_FIFO_BASE 0x591FD60ull
+#define NIC10_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC10_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000
+#define mmNIC10_QPC0_AXUSER_QPC_RESP_BASE 0x591FDC0ull
+#define NIC10_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC10_QPC0_AXUSER_QPC_RESP_SECTION 0x6000
+#define mmNIC10_QPC0_AXUSER_QPC_REQ_BASE 0x591FE20ull
+#define NIC10_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC10_QPC0_AXUSER_QPC_REQ_SECTION 0x6000
+#define mmNIC10_QPC0_SPECIAL_BASE 0x591FE80ull
+#define NIC10_QPC0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_QPC0_SPECIAL_SECTION 0x1800
+#define mmNIC10_UMR1_0_UNSECURE_DOORBELL0_BASE 0x5920000ull
+#define NIC10_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC10_UMR1_0_UNSECURE_DOORBELL1_BASE 0x5920080ull
+#define NIC10_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC10_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x5920100ull
+#define NIC10_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC10_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x5920180ull
+#define NIC10_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC10_UMR1_0_SPECIAL_BASE 0x5920E80ull
+#define NIC10_UMR1_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR1_0_SPECIAL_SECTION 0x1800
+#define mmNIC10_UMR1_1_UNSECURE_DOORBELL0_BASE 0x5921000ull
+#define NIC10_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC10_UMR1_1_UNSECURE_DOORBELL1_BASE 0x5921080ull
+#define NIC10_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC10_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x5921100ull
+#define NIC10_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC10_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x5921180ull
+#define NIC10_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC10_UMR1_1_SPECIAL_BASE 0x5921E80ull
+#define NIC10_UMR1_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR1_1_SPECIAL_SECTION 0x1800
+#define mmNIC10_UMR1_2_UNSECURE_DOORBELL0_BASE 0x5922000ull
+#define NIC10_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC10_UMR1_2_UNSECURE_DOORBELL1_BASE 0x5922080ull
+#define NIC10_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC10_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x5922100ull
+#define NIC10_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC10_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x5922180ull
+#define NIC10_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC10_UMR1_2_SPECIAL_BASE 0x5922E80ull
+#define NIC10_UMR1_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR1_2_SPECIAL_SECTION 0x1800
+#define mmNIC10_UMR1_3_UNSECURE_DOORBELL0_BASE 0x5923000ull
+#define NIC10_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC10_UMR1_3_UNSECURE_DOORBELL1_BASE 0x5923080ull
+#define NIC10_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC10_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x5923100ull
+#define NIC10_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC10_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x5923180ull
+#define NIC10_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC10_UMR1_3_SPECIAL_BASE 0x5923E80ull
+#define NIC10_UMR1_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR1_3_SPECIAL_SECTION 0x1800
+#define mmNIC10_UMR1_4_UNSECURE_DOORBELL0_BASE 0x5924000ull
+#define NIC10_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC10_UMR1_4_UNSECURE_DOORBELL1_BASE 0x5924080ull
+#define NIC10_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC10_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x5924100ull
+#define NIC10_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC10_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x5924180ull
+#define NIC10_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC10_UMR1_4_SPECIAL_BASE 0x5924E80ull
+#define NIC10_UMR1_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR1_4_SPECIAL_SECTION 0x1800
+#define mmNIC10_UMR1_5_UNSECURE_DOORBELL0_BASE 0x5925000ull
+#define NIC10_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC10_UMR1_5_UNSECURE_DOORBELL1_BASE 0x5925080ull
+#define NIC10_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC10_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x5925100ull
+#define NIC10_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC10_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x5925180ull
+#define NIC10_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC10_UMR1_5_SPECIAL_BASE 0x5925E80ull
+#define NIC10_UMR1_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR1_5_SPECIAL_SECTION 0x1800
+#define mmNIC10_UMR1_6_UNSECURE_DOORBELL0_BASE 0x5926000ull
+#define NIC10_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC10_UMR1_6_UNSECURE_DOORBELL1_BASE 0x5926080ull
+#define NIC10_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC10_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x5926100ull
+#define NIC10_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC10_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x5926180ull
+#define NIC10_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC10_UMR1_6_SPECIAL_BASE 0x5926E80ull
+#define NIC10_UMR1_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR1_6_SPECIAL_SECTION 0x1800
+#define mmNIC10_UMR1_7_UNSECURE_DOORBELL0_BASE 0x5927000ull
+#define NIC10_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC10_UMR1_7_UNSECURE_DOORBELL1_BASE 0x5927080ull
+#define NIC10_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC10_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x5927100ull
+#define NIC10_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC10_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x5927180ull
+#define NIC10_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC10_UMR1_7_SPECIAL_BASE 0x5927E80ull
+#define NIC10_UMR1_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR1_7_SPECIAL_SECTION 0x1800
+#define mmNIC10_UMR1_8_UNSECURE_DOORBELL0_BASE 0x5928000ull
+#define NIC10_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC10_UMR1_8_UNSECURE_DOORBELL1_BASE 0x5928080ull
+#define NIC10_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC10_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x5928100ull
+#define NIC10_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC10_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x5928180ull
+#define NIC10_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC10_UMR1_8_SPECIAL_BASE 0x5928E80ull
+#define NIC10_UMR1_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR1_8_SPECIAL_SECTION 0x1800
+#define mmNIC10_UMR1_9_UNSECURE_DOORBELL0_BASE 0x5929000ull
+#define NIC10_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC10_UMR1_9_UNSECURE_DOORBELL1_BASE 0x5929080ull
+#define NIC10_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC10_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x5929100ull
+#define NIC10_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC10_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x5929180ull
+#define NIC10_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC10_UMR1_9_SPECIAL_BASE 0x5929E80ull
+#define NIC10_UMR1_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR1_9_SPECIAL_SECTION 0x1800
+#define mmNIC10_UMR1_10_UNSECURE_DOORBELL0_BASE 0x592A000ull
+#define NIC10_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC10_UMR1_10_UNSECURE_DOORBELL1_BASE 0x592A080ull
+#define NIC10_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC10_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x592A100ull
+#define NIC10_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC10_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x592A180ull
+#define NIC10_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC10_UMR1_10_SPECIAL_BASE 0x592AE80ull
+#define NIC10_UMR1_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR1_10_SPECIAL_SECTION 0x1800
+#define mmNIC10_UMR1_11_UNSECURE_DOORBELL0_BASE 0x592B000ull
+#define NIC10_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC10_UMR1_11_UNSECURE_DOORBELL1_BASE 0x592B080ull
+#define NIC10_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC10_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x592B100ull
+#define NIC10_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC10_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x592B180ull
+#define NIC10_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC10_UMR1_11_SPECIAL_BASE 0x592BE80ull
+#define NIC10_UMR1_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR1_11_SPECIAL_SECTION 0x1800
+#define mmNIC10_UMR1_12_UNSECURE_DOORBELL0_BASE 0x592C000ull
+#define NIC10_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC10_UMR1_12_UNSECURE_DOORBELL1_BASE 0x592C080ull
+#define NIC10_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC10_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x592C100ull
+#define NIC10_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC10_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x592C180ull
+#define NIC10_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC10_UMR1_12_SPECIAL_BASE 0x592CE80ull
+#define NIC10_UMR1_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR1_12_SPECIAL_SECTION 0x1800
+#define mmNIC10_UMR1_13_UNSECURE_DOORBELL0_BASE 0x592D000ull
+#define NIC10_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC10_UMR1_13_UNSECURE_DOORBELL1_BASE 0x592D080ull
+#define NIC10_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC10_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x592D100ull
+#define NIC10_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC10_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x592D180ull
+#define NIC10_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC10_UMR1_13_SPECIAL_BASE 0x592DE80ull
+#define NIC10_UMR1_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR1_13_SPECIAL_SECTION 0x1800
+#define mmNIC10_UMR1_14_UNSECURE_DOORBELL0_BASE 0x592E000ull
+#define NIC10_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC10_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC10_UMR1_14_UNSECURE_DOORBELL1_BASE 0x592E080ull
+#define NIC10_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC10_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC10_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x592E100ull
+#define NIC10_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC10_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC10_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x592E180ull
+#define NIC10_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC10_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC10_UMR1_14_SPECIAL_BASE 0x592EE80ull
+#define NIC10_UMR1_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_UMR1_14_SPECIAL_SECTION 0x1180
+#define mmNIC10_QM_DCCM1_BASE 0x5930000ull
+#define NIC10_QM_DCCM1_MAX_OFFSET 0x4000
+#define NIC10_QM_DCCM1_SECTION 0x8000
+#define mmNIC10_QM_ARC_AUX1_BASE 0x5938000ull
+#define NIC10_QM_ARC_AUX1_MAX_OFFSET 0x1000
+#define NIC10_QM_ARC_AUX1_SECTION 0xE800
+#define mmNIC10_QM_ARC_AUX1_SPECIAL_BASE 0x5938E80ull
+#define NIC10_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_QM_ARC_AUX1_SPECIAL_SECTION 0x1180
+#define mmNIC10_QM1_BASE 0x593A000ull
+#define NIC10_QM1_MAX_OFFSET 0x1000
+#define NIC10_QM1_SECTION 0x9000
+#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x593A900ull
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x593A908ull
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x593A910ull
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x593A918ull
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x593A920ull
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x593A928ull
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x593A930ull
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x593A938ull
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x593A940ull
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x593A948ull
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x593A950ull
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x593A958ull
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x593A960ull
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x593A968ull
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x593A970ull
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x593A978ull
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC10_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmNIC10_QM1_AXUSER_SECURED_BASE 0x593AB00ull
+#define NIC10_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC10_QM1_AXUSER_SECURED_SECTION 0x8000
+#define mmNIC10_QM1_AXUSER_NONSECURED_BASE 0x593AB80ull
+#define NIC10_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC10_QM1_AXUSER_NONSECURED_SECTION 0x8000
+#define mmNIC10_QM1_DBG_HBW_BASE 0x593AC00ull
+#define NIC10_QM1_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC10_QM1_DBG_HBW_SECTION 0x8000
+#define mmNIC10_QM1_DBG_LBW_BASE 0x593AC80ull
+#define NIC10_QM1_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC10_QM1_DBG_LBW_SECTION 0x1000
+#define mmNIC10_QM1_CGM_BASE 0x593AD80ull
+#define NIC10_QM1_CGM_MAX_OFFSET 0xC000
+#define NIC10_QM1_CGM_SECTION 0x1000
+#define mmNIC10_QM1_SPECIAL_BASE 0x593AE80ull
+#define NIC10_QM1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_QM1_SPECIAL_SECTION 0x4180
+#define mmNIC10_QPC1_BASE 0x593F000ull
+#define NIC10_QPC1_MAX_OFFSET 0x1000
+#define NIC10_QPC1_SECTION 0x7200
+#define mmNIC10_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x593F720ull
+#define NIC10_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x593F728ull
+#define NIC10_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x593F730ull
+#define NIC10_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x593F738ull
+#define NIC10_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x593F740ull
+#define NIC10_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x593F748ull
+#define NIC10_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x593F750ull
+#define NIC10_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x593F758ull
+#define NIC10_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x593F760ull
+#define NIC10_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x593F768ull
+#define NIC10_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x593F770ull
+#define NIC10_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x593F778ull
+#define NIC10_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x593F780ull
+#define NIC10_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x593F788ull
+#define NIC10_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x593F790ull
+#define NIC10_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x593F798ull
+#define NIC10_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x593F7A0ull
+#define NIC10_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x593F7A8ull
+#define NIC10_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x593F7B0ull
+#define NIC10_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x593F7B8ull
+#define NIC10_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x593F7C0ull
+#define NIC10_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x593F7C8ull
+#define NIC10_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x593F7D0ull
+#define NIC10_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x593F7D8ull
+#define NIC10_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x593F7E0ull
+#define NIC10_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x593F7E8ull
+#define NIC10_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x593F7F0ull
+#define NIC10_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x593F7F8ull
+#define NIC10_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x593F800ull
+#define NIC10_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x593F808ull
+#define NIC10_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x593F810ull
+#define NIC10_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC10_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x593F818ull
+#define NIC10_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC10_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define mmNIC10_QPC1_AXUSER_CONG_QUE_BASE 0x593FB80ull
+#define NIC10_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC10_QPC1_AXUSER_CONG_QUE_SECTION 0x6000
+#define mmNIC10_QPC1_AXUSER_RXWQE_BASE 0x593FBE0ull
+#define NIC10_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC10_QPC1_AXUSER_RXWQE_SECTION 0x6000
+#define mmNIC10_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x593FC40ull
+#define NIC10_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC10_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define mmNIC10_QPC1_AXUSER_DB_FIFO_BASE 0x593FCA0ull
+#define NIC10_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC10_QPC1_AXUSER_DB_FIFO_SECTION 0x6000
+#define mmNIC10_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x593FD00ull
+#define NIC10_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC10_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define mmNIC10_QPC1_AXUSER_ERR_FIFO_BASE 0x593FD60ull
+#define NIC10_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC10_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000
+#define mmNIC10_QPC1_AXUSER_QPC_RESP_BASE 0x593FDC0ull
+#define NIC10_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC10_QPC1_AXUSER_QPC_RESP_SECTION 0x6000
+#define mmNIC10_QPC1_AXUSER_QPC_REQ_BASE 0x593FE20ull
+#define NIC10_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC10_QPC1_AXUSER_QPC_REQ_SECTION 0x6000
+#define mmNIC10_QPC1_SPECIAL_BASE 0x593FE80ull
+#define NIC10_QPC1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_QPC1_SPECIAL_SECTION 0x8180
+#define mmNIC10_TMR_BASE 0x5948000ull
+#define NIC10_TMR_MAX_OFFSET 0x1000
+#define NIC10_TMR_SECTION 0xD600
+#define mmNIC10_TMR_AXUSER_TMR_FREE_LIST_BASE 0x5948D60ull
+#define NIC10_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000
+#define NIC10_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000
+#define mmNIC10_TMR_AXUSER_TMR_FIFO_BASE 0x5948DC0ull
+#define NIC10_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000
+#define NIC10_TMR_AXUSER_TMR_FIFO_SECTION 0x6000
+#define mmNIC10_TMR_AXUSER_TMR_FSM_BASE 0x5948E20ull
+#define NIC10_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000
+#define NIC10_TMR_AXUSER_TMR_FSM_SECTION 0x6000
+#define mmNIC10_TMR_SPECIAL_BASE 0x5948E80ull
+#define NIC10_TMR_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_TMR_SPECIAL_SECTION 0x1800
+#define mmNIC10_RXB_CORE_BASE 0x5949000ull
+#define NIC10_RXB_CORE_MAX_OFFSET 0x1000
+#define NIC10_RXB_CORE_SECTION 0x6100
+#define mmNIC10_RXB_CORE_SCT_AWUSER_BASE 0x5949610ull
+#define NIC10_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000
+#define NIC10_RXB_CORE_SCT_AWUSER_SECTION 0x8700
+#define mmNIC10_RXB_CORE_SPECIAL_BASE 0x5949E80ull
+#define NIC10_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_RXB_CORE_SPECIAL_SECTION 0x1800
+#define mmNIC10_RXE0_BASE 0x594A000ull
+#define NIC10_RXE0_MAX_OFFSET 0x1000
+#define NIC10_RXE0_SECTION 0x9000
+#define mmNIC10_RXE0_WQE_ARUSER_BASE 0x594A900ull
+#define NIC10_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC10_RXE0_WQE_ARUSER_SECTION 0x5800
+#define mmNIC10_RXE0_SPECIAL_BASE 0x594AE80ull
+#define NIC10_RXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_RXE0_SPECIAL_SECTION 0x1800
+#define mmNIC10_RXE1_BASE 0x594B000ull
+#define NIC10_RXE1_MAX_OFFSET 0x1000
+#define NIC10_RXE1_SECTION 0x9000
+#define mmNIC10_RXE1_WQE_ARUSER_BASE 0x594B900ull
+#define NIC10_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC10_RXE1_WQE_ARUSER_SECTION 0x5800
+#define mmNIC10_RXE1_SPECIAL_BASE 0x594BE80ull
+#define NIC10_RXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_RXE1_SPECIAL_SECTION 0x1800
+#define mmNIC10_RXE0_AXUSER_AXUSER_CQ0_BASE 0x594C000ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define mmNIC10_RXE0_AXUSER_AXUSER_CQ1_BASE 0x594C050ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define mmNIC10_RXE0_AXUSER_AXUSER_CQ2_BASE 0x594C0A0ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define mmNIC10_RXE0_AXUSER_AXUSER_CQ3_BASE 0x594C0F0ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define mmNIC10_RXE0_AXUSER_AXUSER_CQ4_BASE 0x594C140ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define mmNIC10_RXE0_AXUSER_AXUSER_CQ5_BASE 0x594C190ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define mmNIC10_RXE0_AXUSER_AXUSER_CQ6_BASE 0x594C1E0ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define mmNIC10_RXE0_AXUSER_AXUSER_CQ7_BASE 0x594C230ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define mmNIC10_RXE0_AXUSER_AXUSER_CQ8_BASE 0x594C280ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define mmNIC10_RXE0_AXUSER_AXUSER_CQ9_BASE 0x594C2D0ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define mmNIC10_RXE0_AXUSER_AXUSER_CQ10_BASE 0x594C320ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define mmNIC10_RXE0_AXUSER_AXUSER_CQ11_BASE 0x594C370ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define mmNIC10_RXE0_AXUSER_AXUSER_CQ12_BASE 0x594C3C0ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define mmNIC10_RXE0_AXUSER_AXUSER_CQ13_BASE 0x594C410ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define mmNIC10_RXE0_AXUSER_AXUSER_CQ14_BASE 0x594C460ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define mmNIC10_RXE0_AXUSER_AXUSER_CQ15_BASE 0x594C4B0ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define mmNIC10_RXE0_AXUSER_AXUSER_CQ16_BASE 0x594C500ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define mmNIC10_RXE0_AXUSER_AXUSER_CQ17_BASE 0x594C550ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define mmNIC10_RXE0_AXUSER_AXUSER_CQ18_BASE 0x594C5A0ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define mmNIC10_RXE0_AXUSER_AXUSER_CQ19_BASE 0x594C5F0ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define mmNIC10_RXE0_AXUSER_AXUSER_CQ20_BASE 0x594C640ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define mmNIC10_RXE0_AXUSER_AXUSER_CQ21_BASE 0x594C690ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define mmNIC10_RXE0_AXUSER_AXUSER_CQ22_BASE 0x594C6E0ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define mmNIC10_RXE0_AXUSER_AXUSER_CQ23_BASE 0x594C730ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define mmNIC10_RXE0_AXUSER_AXUSER_CQ24_BASE 0x594C780ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define mmNIC10_RXE0_AXUSER_AXUSER_CQ25_BASE 0x594C7D0ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define mmNIC10_RXE0_AXUSER_AXUSER_CQ26_BASE 0x594C820ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define mmNIC10_RXE0_AXUSER_AXUSER_CQ27_BASE 0x594C870ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define mmNIC10_RXE0_AXUSER_AXUSER_CQ28_BASE 0x594C8C0ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define mmNIC10_RXE0_AXUSER_AXUSER_CQ29_BASE 0x594C910ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define mmNIC10_RXE0_AXUSER_AXUSER_CQ30_BASE 0x594C960ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define mmNIC10_RXE0_AXUSER_AXUSER_CQ31_BASE 0x594C9B0ull
+#define NIC10_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC10_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define mmNIC10_RXE0_AXUSER_SPECIAL_BASE 0x594CE80ull
+#define NIC10_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_RXE0_AXUSER_SPECIAL_SECTION 0x1800
+#define mmNIC10_RXE1_AXUSER_AXUSER_CQ0_BASE 0x594D000ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define mmNIC10_RXE1_AXUSER_AXUSER_CQ1_BASE 0x594D050ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define mmNIC10_RXE1_AXUSER_AXUSER_CQ2_BASE 0x594D0A0ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define mmNIC10_RXE1_AXUSER_AXUSER_CQ3_BASE 0x594D0F0ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define mmNIC10_RXE1_AXUSER_AXUSER_CQ4_BASE 0x594D140ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define mmNIC10_RXE1_AXUSER_AXUSER_CQ5_BASE 0x594D190ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define mmNIC10_RXE1_AXUSER_AXUSER_CQ6_BASE 0x594D1E0ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define mmNIC10_RXE1_AXUSER_AXUSER_CQ7_BASE 0x594D230ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define mmNIC10_RXE1_AXUSER_AXUSER_CQ8_BASE 0x594D280ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define mmNIC10_RXE1_AXUSER_AXUSER_CQ9_BASE 0x594D2D0ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define mmNIC10_RXE1_AXUSER_AXUSER_CQ10_BASE 0x594D320ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define mmNIC10_RXE1_AXUSER_AXUSER_CQ11_BASE 0x594D370ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define mmNIC10_RXE1_AXUSER_AXUSER_CQ12_BASE 0x594D3C0ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define mmNIC10_RXE1_AXUSER_AXUSER_CQ13_BASE 0x594D410ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define mmNIC10_RXE1_AXUSER_AXUSER_CQ14_BASE 0x594D460ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define mmNIC10_RXE1_AXUSER_AXUSER_CQ15_BASE 0x594D4B0ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define mmNIC10_RXE1_AXUSER_AXUSER_CQ16_BASE 0x594D500ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define mmNIC10_RXE1_AXUSER_AXUSER_CQ17_BASE 0x594D550ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define mmNIC10_RXE1_AXUSER_AXUSER_CQ18_BASE 0x594D5A0ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define mmNIC10_RXE1_AXUSER_AXUSER_CQ19_BASE 0x594D5F0ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define mmNIC10_RXE1_AXUSER_AXUSER_CQ20_BASE 0x594D640ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define mmNIC10_RXE1_AXUSER_AXUSER_CQ21_BASE 0x594D690ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define mmNIC10_RXE1_AXUSER_AXUSER_CQ22_BASE 0x594D6E0ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define mmNIC10_RXE1_AXUSER_AXUSER_CQ23_BASE 0x594D730ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define mmNIC10_RXE1_AXUSER_AXUSER_CQ24_BASE 0x594D780ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define mmNIC10_RXE1_AXUSER_AXUSER_CQ25_BASE 0x594D7D0ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define mmNIC10_RXE1_AXUSER_AXUSER_CQ26_BASE 0x594D820ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define mmNIC10_RXE1_AXUSER_AXUSER_CQ27_BASE 0x594D870ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define mmNIC10_RXE1_AXUSER_AXUSER_CQ28_BASE 0x594D8C0ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define mmNIC10_RXE1_AXUSER_AXUSER_CQ29_BASE 0x594D910ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define mmNIC10_RXE1_AXUSER_AXUSER_CQ30_BASE 0x594D960ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define mmNIC10_RXE1_AXUSER_AXUSER_CQ31_BASE 0x594D9B0ull
+#define NIC10_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC10_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define mmNIC10_RXE1_AXUSER_SPECIAL_BASE 0x594DE80ull
+#define NIC10_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_RXE1_AXUSER_SPECIAL_SECTION 0x2180
+#define mmNIC10_TXS0_BASE 0x5950000ull
+#define NIC10_TXS0_MAX_OFFSET 0x1000
+#define NIC10_TXS0_SECTION 0xE800
+#define mmNIC10_TXS0_SPECIAL_BASE 0x5950E80ull
+#define NIC10_TXS0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_TXS0_SPECIAL_SECTION 0x1800
+#define mmNIC10_TXS1_BASE 0x5951000ull
+#define NIC10_TXS1_MAX_OFFSET 0x1000
+#define NIC10_TXS1_SECTION 0xE800
+#define mmNIC10_TXS1_SPECIAL_BASE 0x5951E80ull
+#define NIC10_TXS1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_TXS1_SPECIAL_SECTION 0x1800
+#define mmNIC10_TXE0_BASE 0x5952000ull
+#define NIC10_TXE0_MAX_OFFSET 0x1000
+#define NIC10_TXE0_SECTION 0xE800
+#define mmNIC10_TXE0_SPECIAL_BASE 0x5952E80ull
+#define NIC10_TXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_TXE0_SPECIAL_SECTION 0x1800
+#define mmNIC10_TXE1_BASE 0x5953000ull
+#define NIC10_TXE1_MAX_OFFSET 0x1000
+#define NIC10_TXE1_SECTION 0xE800
+#define mmNIC10_TXE1_SPECIAL_BASE 0x5953E80ull
+#define NIC10_TXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_TXE1_SPECIAL_SECTION 0x1800
+#define mmNIC10_TXB_BASE 0x5954000ull
+#define NIC10_TXB_MAX_OFFSET 0x1000
+#define NIC10_TXB_SECTION 0xE800
+#define mmNIC10_TXB_SPECIAL_BASE 0x5954E80ull
+#define NIC10_TXB_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_TXB_SPECIAL_SECTION 0x1800
+#define mmNIC10_MSTR_IF_RR_SHRD_HBW_BASE 0x5955000ull
+#define NIC10_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define NIC10_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmNIC10_MSTR_IF_RR_PRVT_HBW_BASE 0x5955200ull
+#define NIC10_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define NIC10_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmNIC10_MSTR_IF_RR_SHRD_LBW_BASE 0x5955400ull
+#define NIC10_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define NIC10_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmNIC10_MSTR_IF_RR_PRVT_LBW_BASE 0x5955600ull
+#define NIC10_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define NIC10_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmNIC10_MSTR_IF_E2E_CRDT_BASE 0x5955800ull
+#define NIC10_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define NIC10_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmNIC10_MSTR_IF_AXUSER_BASE 0x5955A80ull
+#define NIC10_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define NIC10_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmNIC10_MSTR_IF_DBG_HBW_BASE 0x5955B00ull
+#define NIC10_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC10_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmNIC10_MSTR_IF_DBG_LBW_BASE 0x5955B80ull
+#define NIC10_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC10_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmNIC10_MSTR_IF_CORE_HBW_BASE 0x5955C00ull
+#define NIC10_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define NIC10_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmNIC10_MSTR_IF_CORE_LBW_BASE 0x5955D80ull
+#define NIC10_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define NIC10_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmNIC10_MSTR_IF_SPECIAL_BASE 0x5955E80ull
+#define NIC10_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmNIC10_TX_AXUSER_BASE 0x5956000ull
+#define NIC10_TX_AXUSER_MAX_OFFSET 0x5000
+#define NIC10_TX_AXUSER_SECTION 0x2000
+#define mmNIC10_SERDES0_BASE 0x5958000ull
+#define NIC10_SERDES0_MAX_OFFSET 0x3E40
+#define NIC10_SERDES0_SECTION 0x4000
+#define mmNIC10_SERDES1_BASE 0x595C000ull
+#define NIC10_SERDES1_MAX_OFFSET 0x3E40
+#define NIC10_SERDES1_SECTION 0x4000
+#define mmNIC10_PHY_BASE 0x5960000ull
+#define NIC10_PHY_MAX_OFFSET 0x1000
+#define NIC10_PHY_SECTION 0xE800
+#define mmNIC10_PHY_SPECIAL_BASE 0x5960E80ull
+#define NIC10_PHY_SPECIAL_MAX_OFFSET 0x1800
+#define NIC10_PHY_SPECIAL_SECTION 0x7180
+#define mmPRT10_MAC_AUX_BASE 0x5968000ull
+#define PRT10_MAC_AUX_MAX_OFFSET 0x1000
+#define PRT10_MAC_AUX_SECTION 0xE800
+#define mmPRT10_MAC_AUX_SPECIAL_BASE 0x5968E80ull
+#define PRT10_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define PRT10_MAC_AUX_SPECIAL_SECTION 0x1800
+#define mmPRT10_MAC_CORE_BASE 0x5969000ull
+#define PRT10_MAC_CORE_MAX_OFFSET 0x1000
+#define PRT10_MAC_CORE_SECTION 0xE800
+#define mmPRT10_MAC_CORE_SPECIAL_BASE 0x5969E80ull
+#define PRT10_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define PRT10_MAC_CORE_SPECIAL_SECTION 0x1800
+#define mmNIC10_MAC_RS_FEC_BASE 0x596A000ull
+#define NIC10_MAC_RS_FEC_MAX_OFFSET 0x2DC0
+#define NIC10_MAC_RS_FEC_SECTION 0x1000
+#define mmNIC10_MAC_GLOB_STAT_CONTROL_REG_BASE 0x596B000ull
+#define NIC10_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000
+#define NIC10_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000
+#define mmNIC10_MAC_GLOB_STAT_RX0_BASE 0x596B100ull
+#define NIC10_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00
+#define NIC10_MAC_GLOB_STAT_RX0_SECTION 0x8C00
+#define mmNIC10_MAC_GLOB_STAT_RX1_BASE 0x596B18Cull
+#define NIC10_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00
+#define NIC10_MAC_GLOB_STAT_RX1_SECTION 0x8C00
+#define mmNIC10_MAC_GLOB_STAT_RX2_BASE 0x596B218ull
+#define NIC10_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00
+#define NIC10_MAC_GLOB_STAT_RX2_SECTION 0x8C00
+#define mmNIC10_MAC_GLOB_STAT_RX3_BASE 0x596B2A4ull
+#define NIC10_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00
+#define NIC10_MAC_GLOB_STAT_RX3_SECTION 0x8C00
+#define mmNIC10_MAC_GLOB_STAT_TX0_BASE 0x596B330ull
+#define NIC10_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800
+#define NIC10_MAC_GLOB_STAT_TX0_SECTION 0x6800
+#define mmNIC10_MAC_GLOB_STAT_TX1_BASE 0x596B398ull
+#define NIC10_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800
+#define NIC10_MAC_GLOB_STAT_TX1_SECTION 0x6800
+#define mmNIC10_MAC_GLOB_STAT_TX2_BASE 0x596B400ull
+#define NIC10_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800
+#define NIC10_MAC_GLOB_STAT_TX2_SECTION 0x6800
+#define mmNIC10_MAC_GLOB_STAT_TX3_BASE 0x596B468ull
+#define NIC10_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800
+#define NIC10_MAC_GLOB_STAT_TX3_SECTION 0x3980
+#define mmNIC10_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x596B800ull
+#define NIC10_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0
+#define NIC10_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000
+#define mmNIC10_MAC_CH0_MAC_PCS_BASE 0x596C000ull
+#define NIC10_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC10_MAC_CH0_MAC_PCS_SECTION 0x4000
+#define mmNIC10_MAC_CH0_MAC_128_BASE 0x596C400ull
+#define NIC10_MAC_CH0_MAC_128_MAX_OFFSET 0xA400
+#define NIC10_MAC_CH0_MAC_128_SECTION 0x4000
+#define mmNIC10_MAC_CH0_MAC_AN_BASE 0x596C800ull
+#define NIC10_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400
+#define NIC10_MAC_CH0_MAC_AN_SECTION 0x8000
+#define mmNIC10_MAC_CH1_MAC_PCS_BASE 0x596D000ull
+#define NIC10_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC10_MAC_CH1_MAC_PCS_SECTION 0x4000
+#define mmNIC10_MAC_CH1_MAC_128_BASE 0x596D400ull
+#define NIC10_MAC_CH1_MAC_128_MAX_OFFSET 0xA400
+#define NIC10_MAC_CH1_MAC_128_SECTION 0x4000
+#define mmNIC10_MAC_CH1_MAC_AN_BASE 0x596D800ull
+#define NIC10_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400
+#define NIC10_MAC_CH1_MAC_AN_SECTION 0x8000
+#define mmNIC10_MAC_CH2_MAC_PCS_BASE 0x596E000ull
+#define NIC10_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC10_MAC_CH2_MAC_PCS_SECTION 0x4000
+#define mmNIC10_MAC_CH2_MAC_128_BASE 0x596E400ull
+#define NIC10_MAC_CH2_MAC_128_MAX_OFFSET 0xA400
+#define NIC10_MAC_CH2_MAC_128_SECTION 0x4000
+#define mmNIC10_MAC_CH2_MAC_AN_BASE 0x596E800ull
+#define NIC10_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400
+#define NIC10_MAC_CH2_MAC_AN_SECTION 0x8000
+#define mmNIC10_MAC_CH3_MAC_PCS_BASE 0x596F000ull
+#define NIC10_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC10_MAC_CH3_MAC_PCS_SECTION 0x4000
+#define mmNIC10_MAC_CH3_MAC_128_BASE 0x596F400ull
+#define NIC10_MAC_CH3_MAC_128_MAX_OFFSET 0xA400
+#define NIC10_MAC_CH3_MAC_128_SECTION 0x4000
+#define mmNIC10_MAC_CH3_MAC_AN_BASE 0x596F800ull
+#define NIC10_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400
+#define NIC10_MAC_CH3_MAC_AN_SECTION 0x10800
+#define mmNIC11_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5980000ull
+#define NIC11_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC11_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5980080ull
+#define NIC11_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC11_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5980100ull
+#define NIC11_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC11_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5980180ull
+#define NIC11_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC11_UMR0_0_SPECIAL_BASE 0x5980E80ull
+#define NIC11_UMR0_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR0_0_SPECIAL_SECTION 0x1800
+#define mmNIC11_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5981000ull
+#define NIC11_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC11_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5981080ull
+#define NIC11_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC11_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5981100ull
+#define NIC11_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC11_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5981180ull
+#define NIC11_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC11_UMR0_1_SPECIAL_BASE 0x5981E80ull
+#define NIC11_UMR0_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR0_1_SPECIAL_SECTION 0x1800
+#define mmNIC11_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5982000ull
+#define NIC11_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC11_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5982080ull
+#define NIC11_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC11_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5982100ull
+#define NIC11_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC11_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5982180ull
+#define NIC11_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC11_UMR0_2_SPECIAL_BASE 0x5982E80ull
+#define NIC11_UMR0_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR0_2_SPECIAL_SECTION 0x1800
+#define mmNIC11_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5983000ull
+#define NIC11_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC11_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5983080ull
+#define NIC11_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC11_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5983100ull
+#define NIC11_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC11_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5983180ull
+#define NIC11_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC11_UMR0_3_SPECIAL_BASE 0x5983E80ull
+#define NIC11_UMR0_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR0_3_SPECIAL_SECTION 0x1800
+#define mmNIC11_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5984000ull
+#define NIC11_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC11_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5984080ull
+#define NIC11_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC11_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5984100ull
+#define NIC11_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC11_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5984180ull
+#define NIC11_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC11_UMR0_4_SPECIAL_BASE 0x5984E80ull
+#define NIC11_UMR0_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR0_4_SPECIAL_SECTION 0x1800
+#define mmNIC11_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5985000ull
+#define NIC11_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC11_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5985080ull
+#define NIC11_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC11_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5985100ull
+#define NIC11_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC11_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5985180ull
+#define NIC11_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC11_UMR0_5_SPECIAL_BASE 0x5985E80ull
+#define NIC11_UMR0_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR0_5_SPECIAL_SECTION 0x1800
+#define mmNIC11_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5986000ull
+#define NIC11_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC11_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5986080ull
+#define NIC11_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC11_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5986100ull
+#define NIC11_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC11_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5986180ull
+#define NIC11_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC11_UMR0_6_SPECIAL_BASE 0x5986E80ull
+#define NIC11_UMR0_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR0_6_SPECIAL_SECTION 0x1800
+#define mmNIC11_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5987000ull
+#define NIC11_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC11_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5987080ull
+#define NIC11_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC11_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5987100ull
+#define NIC11_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC11_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5987180ull
+#define NIC11_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC11_UMR0_7_SPECIAL_BASE 0x5987E80ull
+#define NIC11_UMR0_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR0_7_SPECIAL_SECTION 0x1800
+#define mmNIC11_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5988000ull
+#define NIC11_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC11_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5988080ull
+#define NIC11_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC11_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5988100ull
+#define NIC11_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC11_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5988180ull
+#define NIC11_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC11_UMR0_8_SPECIAL_BASE 0x5988E80ull
+#define NIC11_UMR0_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR0_8_SPECIAL_SECTION 0x1800
+#define mmNIC11_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5989000ull
+#define NIC11_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC11_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5989080ull
+#define NIC11_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC11_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5989100ull
+#define NIC11_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC11_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5989180ull
+#define NIC11_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC11_UMR0_9_SPECIAL_BASE 0x5989E80ull
+#define NIC11_UMR0_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR0_9_SPECIAL_SECTION 0x1800
+#define mmNIC11_UMR0_10_UNSECURE_DOORBELL0_BASE 0x598A000ull
+#define NIC11_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC11_UMR0_10_UNSECURE_DOORBELL1_BASE 0x598A080ull
+#define NIC11_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC11_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x598A100ull
+#define NIC11_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC11_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x598A180ull
+#define NIC11_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC11_UMR0_10_SPECIAL_BASE 0x598AE80ull
+#define NIC11_UMR0_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR0_10_SPECIAL_SECTION 0x1800
+#define mmNIC11_UMR0_11_UNSECURE_DOORBELL0_BASE 0x598B000ull
+#define NIC11_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC11_UMR0_11_UNSECURE_DOORBELL1_BASE 0x598B080ull
+#define NIC11_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC11_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x598B100ull
+#define NIC11_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC11_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x598B180ull
+#define NIC11_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC11_UMR0_11_SPECIAL_BASE 0x598BE80ull
+#define NIC11_UMR0_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR0_11_SPECIAL_SECTION 0x1800
+#define mmNIC11_UMR0_12_UNSECURE_DOORBELL0_BASE 0x598C000ull
+#define NIC11_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC11_UMR0_12_UNSECURE_DOORBELL1_BASE 0x598C080ull
+#define NIC11_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC11_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x598C100ull
+#define NIC11_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC11_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x598C180ull
+#define NIC11_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC11_UMR0_12_SPECIAL_BASE 0x598CE80ull
+#define NIC11_UMR0_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR0_12_SPECIAL_SECTION 0x1800
+#define mmNIC11_UMR0_13_UNSECURE_DOORBELL0_BASE 0x598D000ull
+#define NIC11_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC11_UMR0_13_UNSECURE_DOORBELL1_BASE 0x598D080ull
+#define NIC11_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC11_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x598D100ull
+#define NIC11_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC11_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x598D180ull
+#define NIC11_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC11_UMR0_13_SPECIAL_BASE 0x598DE80ull
+#define NIC11_UMR0_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR0_13_SPECIAL_SECTION 0x1800
+#define mmNIC11_UMR0_14_UNSECURE_DOORBELL0_BASE 0x598E000ull
+#define NIC11_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC11_UMR0_14_UNSECURE_DOORBELL1_BASE 0x598E080ull
+#define NIC11_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC11_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x598E100ull
+#define NIC11_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC11_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x598E180ull
+#define NIC11_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC11_UMR0_14_SPECIAL_BASE 0x598EE80ull
+#define NIC11_UMR0_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR0_14_SPECIAL_SECTION 0x1180
+#define mmNIC11_QM_DCCM0_BASE 0x5990000ull
+#define NIC11_QM_DCCM0_MAX_OFFSET 0x4000
+#define NIC11_QM_DCCM0_SECTION 0x8000
+#define mmNIC11_QM_ARC_AUX0_BASE 0x5998000ull
+#define NIC11_QM_ARC_AUX0_MAX_OFFSET 0x1000
+#define NIC11_QM_ARC_AUX0_SECTION 0xE800
+#define mmNIC11_QM_ARC_AUX0_SPECIAL_BASE 0x5998E80ull
+#define NIC11_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_QM_ARC_AUX0_SPECIAL_SECTION 0x1180
+#define mmNIC11_QM0_BASE 0x599A000ull
+#define NIC11_QM0_MAX_OFFSET 0x1000
+#define NIC11_QM0_SECTION 0x9000
+#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x599A900ull
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x599A908ull
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x599A910ull
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x599A918ull
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x599A920ull
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x599A928ull
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x599A930ull
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x599A938ull
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x599A940ull
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x599A948ull
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x599A950ull
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x599A958ull
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x599A960ull
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x599A968ull
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x599A970ull
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x599A978ull
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC11_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmNIC11_QM0_AXUSER_SECURED_BASE 0x599AB00ull
+#define NIC11_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC11_QM0_AXUSER_SECURED_SECTION 0x8000
+#define mmNIC11_QM0_AXUSER_NONSECURED_BASE 0x599AB80ull
+#define NIC11_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC11_QM0_AXUSER_NONSECURED_SECTION 0x8000
+#define mmNIC11_QM0_DBG_HBW_BASE 0x599AC00ull
+#define NIC11_QM0_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC11_QM0_DBG_HBW_SECTION 0x8000
+#define mmNIC11_QM0_DBG_LBW_BASE 0x599AC80ull
+#define NIC11_QM0_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC11_QM0_DBG_LBW_SECTION 0x1000
+#define mmNIC11_QM0_CGM_BASE 0x599AD80ull
+#define NIC11_QM0_CGM_MAX_OFFSET 0xC000
+#define NIC11_QM0_CGM_SECTION 0x1000
+#define mmNIC11_QM0_SPECIAL_BASE 0x599AE80ull
+#define NIC11_QM0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_QM0_SPECIAL_SECTION 0x4180
+#define mmNIC11_QPC0_BASE 0x599F000ull
+#define NIC11_QPC0_MAX_OFFSET 0x1000
+#define NIC11_QPC0_SECTION 0x7200
+#define mmNIC11_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x599F720ull
+#define NIC11_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x599F728ull
+#define NIC11_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x599F730ull
+#define NIC11_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x599F738ull
+#define NIC11_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x599F740ull
+#define NIC11_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x599F748ull
+#define NIC11_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x599F750ull
+#define NIC11_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x599F758ull
+#define NIC11_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x599F760ull
+#define NIC11_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x599F768ull
+#define NIC11_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x599F770ull
+#define NIC11_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x599F778ull
+#define NIC11_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x599F780ull
+#define NIC11_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x599F788ull
+#define NIC11_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x599F790ull
+#define NIC11_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x599F798ull
+#define NIC11_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x599F7A0ull
+#define NIC11_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x599F7A8ull
+#define NIC11_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x599F7B0ull
+#define NIC11_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x599F7B8ull
+#define NIC11_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x599F7C0ull
+#define NIC11_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x599F7C8ull
+#define NIC11_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x599F7D0ull
+#define NIC11_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x599F7D8ull
+#define NIC11_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x599F7E0ull
+#define NIC11_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x599F7E8ull
+#define NIC11_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x599F7F0ull
+#define NIC11_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x599F7F8ull
+#define NIC11_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x599F800ull
+#define NIC11_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x599F808ull
+#define NIC11_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x599F810ull
+#define NIC11_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x599F818ull
+#define NIC11_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define mmNIC11_QPC0_AXUSER_CONG_QUE_BASE 0x599FB80ull
+#define NIC11_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC11_QPC0_AXUSER_CONG_QUE_SECTION 0x6000
+#define mmNIC11_QPC0_AXUSER_RXWQE_BASE 0x599FBE0ull
+#define NIC11_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC11_QPC0_AXUSER_RXWQE_SECTION 0x6000
+#define mmNIC11_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x599FC40ull
+#define NIC11_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC11_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define mmNIC11_QPC0_AXUSER_DB_FIFO_BASE 0x599FCA0ull
+#define NIC11_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC11_QPC0_AXUSER_DB_FIFO_SECTION 0x6000
+#define mmNIC11_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x599FD00ull
+#define NIC11_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC11_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define mmNIC11_QPC0_AXUSER_ERR_FIFO_BASE 0x599FD60ull
+#define NIC11_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC11_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000
+#define mmNIC11_QPC0_AXUSER_QPC_RESP_BASE 0x599FDC0ull
+#define NIC11_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC11_QPC0_AXUSER_QPC_RESP_SECTION 0x6000
+#define mmNIC11_QPC0_AXUSER_QPC_REQ_BASE 0x599FE20ull
+#define NIC11_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC11_QPC0_AXUSER_QPC_REQ_SECTION 0x6000
+#define mmNIC11_QPC0_SPECIAL_BASE 0x599FE80ull
+#define NIC11_QPC0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_QPC0_SPECIAL_SECTION 0x1800
+#define mmNIC11_UMR1_0_UNSECURE_DOORBELL0_BASE 0x59A0000ull
+#define NIC11_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC11_UMR1_0_UNSECURE_DOORBELL1_BASE 0x59A0080ull
+#define NIC11_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC11_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x59A0100ull
+#define NIC11_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC11_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x59A0180ull
+#define NIC11_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC11_UMR1_0_SPECIAL_BASE 0x59A0E80ull
+#define NIC11_UMR1_0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR1_0_SPECIAL_SECTION 0x1800
+#define mmNIC11_UMR1_1_UNSECURE_DOORBELL0_BASE 0x59A1000ull
+#define NIC11_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC11_UMR1_1_UNSECURE_DOORBELL1_BASE 0x59A1080ull
+#define NIC11_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC11_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x59A1100ull
+#define NIC11_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC11_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x59A1180ull
+#define NIC11_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC11_UMR1_1_SPECIAL_BASE 0x59A1E80ull
+#define NIC11_UMR1_1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR1_1_SPECIAL_SECTION 0x1800
+#define mmNIC11_UMR1_2_UNSECURE_DOORBELL0_BASE 0x59A2000ull
+#define NIC11_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC11_UMR1_2_UNSECURE_DOORBELL1_BASE 0x59A2080ull
+#define NIC11_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC11_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x59A2100ull
+#define NIC11_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC11_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x59A2180ull
+#define NIC11_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC11_UMR1_2_SPECIAL_BASE 0x59A2E80ull
+#define NIC11_UMR1_2_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR1_2_SPECIAL_SECTION 0x1800
+#define mmNIC11_UMR1_3_UNSECURE_DOORBELL0_BASE 0x59A3000ull
+#define NIC11_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC11_UMR1_3_UNSECURE_DOORBELL1_BASE 0x59A3080ull
+#define NIC11_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC11_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x59A3100ull
+#define NIC11_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC11_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x59A3180ull
+#define NIC11_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC11_UMR1_3_SPECIAL_BASE 0x59A3E80ull
+#define NIC11_UMR1_3_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR1_3_SPECIAL_SECTION 0x1800
+#define mmNIC11_UMR1_4_UNSECURE_DOORBELL0_BASE 0x59A4000ull
+#define NIC11_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC11_UMR1_4_UNSECURE_DOORBELL1_BASE 0x59A4080ull
+#define NIC11_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC11_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x59A4100ull
+#define NIC11_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC11_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x59A4180ull
+#define NIC11_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC11_UMR1_4_SPECIAL_BASE 0x59A4E80ull
+#define NIC11_UMR1_4_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR1_4_SPECIAL_SECTION 0x1800
+#define mmNIC11_UMR1_5_UNSECURE_DOORBELL0_BASE 0x59A5000ull
+#define NIC11_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC11_UMR1_5_UNSECURE_DOORBELL1_BASE 0x59A5080ull
+#define NIC11_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC11_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x59A5100ull
+#define NIC11_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC11_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x59A5180ull
+#define NIC11_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC11_UMR1_5_SPECIAL_BASE 0x59A5E80ull
+#define NIC11_UMR1_5_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR1_5_SPECIAL_SECTION 0x1800
+#define mmNIC11_UMR1_6_UNSECURE_DOORBELL0_BASE 0x59A6000ull
+#define NIC11_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC11_UMR1_6_UNSECURE_DOORBELL1_BASE 0x59A6080ull
+#define NIC11_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC11_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x59A6100ull
+#define NIC11_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC11_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x59A6180ull
+#define NIC11_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC11_UMR1_6_SPECIAL_BASE 0x59A6E80ull
+#define NIC11_UMR1_6_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR1_6_SPECIAL_SECTION 0x1800
+#define mmNIC11_UMR1_7_UNSECURE_DOORBELL0_BASE 0x59A7000ull
+#define NIC11_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC11_UMR1_7_UNSECURE_DOORBELL1_BASE 0x59A7080ull
+#define NIC11_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC11_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x59A7100ull
+#define NIC11_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC11_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x59A7180ull
+#define NIC11_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC11_UMR1_7_SPECIAL_BASE 0x59A7E80ull
+#define NIC11_UMR1_7_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR1_7_SPECIAL_SECTION 0x1800
+#define mmNIC11_UMR1_8_UNSECURE_DOORBELL0_BASE 0x59A8000ull
+#define NIC11_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC11_UMR1_8_UNSECURE_DOORBELL1_BASE 0x59A8080ull
+#define NIC11_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC11_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x59A8100ull
+#define NIC11_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC11_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x59A8180ull
+#define NIC11_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC11_UMR1_8_SPECIAL_BASE 0x59A8E80ull
+#define NIC11_UMR1_8_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR1_8_SPECIAL_SECTION 0x1800
+#define mmNIC11_UMR1_9_UNSECURE_DOORBELL0_BASE 0x59A9000ull
+#define NIC11_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC11_UMR1_9_UNSECURE_DOORBELL1_BASE 0x59A9080ull
+#define NIC11_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC11_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x59A9100ull
+#define NIC11_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC11_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x59A9180ull
+#define NIC11_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC11_UMR1_9_SPECIAL_BASE 0x59A9E80ull
+#define NIC11_UMR1_9_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR1_9_SPECIAL_SECTION 0x1800
+#define mmNIC11_UMR1_10_UNSECURE_DOORBELL0_BASE 0x59AA000ull
+#define NIC11_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC11_UMR1_10_UNSECURE_DOORBELL1_BASE 0x59AA080ull
+#define NIC11_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC11_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x59AA100ull
+#define NIC11_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC11_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x59AA180ull
+#define NIC11_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC11_UMR1_10_SPECIAL_BASE 0x59AAE80ull
+#define NIC11_UMR1_10_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR1_10_SPECIAL_SECTION 0x1800
+#define mmNIC11_UMR1_11_UNSECURE_DOORBELL0_BASE 0x59AB000ull
+#define NIC11_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC11_UMR1_11_UNSECURE_DOORBELL1_BASE 0x59AB080ull
+#define NIC11_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC11_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x59AB100ull
+#define NIC11_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC11_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x59AB180ull
+#define NIC11_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC11_UMR1_11_SPECIAL_BASE 0x59ABE80ull
+#define NIC11_UMR1_11_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR1_11_SPECIAL_SECTION 0x1800
+#define mmNIC11_UMR1_12_UNSECURE_DOORBELL0_BASE 0x59AC000ull
+#define NIC11_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC11_UMR1_12_UNSECURE_DOORBELL1_BASE 0x59AC080ull
+#define NIC11_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC11_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x59AC100ull
+#define NIC11_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC11_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x59AC180ull
+#define NIC11_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC11_UMR1_12_SPECIAL_BASE 0x59ACE80ull
+#define NIC11_UMR1_12_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR1_12_SPECIAL_SECTION 0x1800
+#define mmNIC11_UMR1_13_UNSECURE_DOORBELL0_BASE 0x59AD000ull
+#define NIC11_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC11_UMR1_13_UNSECURE_DOORBELL1_BASE 0x59AD080ull
+#define NIC11_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC11_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x59AD100ull
+#define NIC11_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC11_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x59AD180ull
+#define NIC11_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC11_UMR1_13_SPECIAL_BASE 0x59ADE80ull
+#define NIC11_UMR1_13_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR1_13_SPECIAL_SECTION 0x1800
+#define mmNIC11_UMR1_14_UNSECURE_DOORBELL0_BASE 0x59AE000ull
+#define NIC11_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
+#define NIC11_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000
+#define mmNIC11_UMR1_14_UNSECURE_DOORBELL1_BASE 0x59AE080ull
+#define NIC11_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
+#define NIC11_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000
+#define mmNIC11_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x59AE100ull
+#define NIC11_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
+#define NIC11_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
+#define mmNIC11_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x59AE180ull
+#define NIC11_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
+#define NIC11_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
+#define mmNIC11_UMR1_14_SPECIAL_BASE 0x59AEE80ull
+#define NIC11_UMR1_14_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_UMR1_14_SPECIAL_SECTION 0x1180
+#define mmNIC11_QM_DCCM1_BASE 0x59B0000ull
+#define NIC11_QM_DCCM1_MAX_OFFSET 0x4000
+#define NIC11_QM_DCCM1_SECTION 0x8000
+#define mmNIC11_QM_ARC_AUX1_BASE 0x59B8000ull
+#define NIC11_QM_ARC_AUX1_MAX_OFFSET 0x1000
+#define NIC11_QM_ARC_AUX1_SECTION 0xE800
+#define mmNIC11_QM_ARC_AUX1_SPECIAL_BASE 0x59B8E80ull
+#define NIC11_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_QM_ARC_AUX1_SPECIAL_SECTION 0x1180
+#define mmNIC11_QM1_BASE 0x59BA000ull
+#define NIC11_QM1_MAX_OFFSET 0x1000
+#define NIC11_QM1_SECTION 0x9000
+#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x59BA900ull
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
+#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x59BA908ull
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
+#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x59BA910ull
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
+#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x59BA918ull
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
+#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x59BA920ull
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
+#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x59BA928ull
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
+#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x59BA930ull
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
+#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x59BA938ull
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
+#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x59BA940ull
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
+#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x59BA948ull
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
+#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x59BA950ull
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
+#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x59BA958ull
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
+#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x59BA960ull
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
+#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x59BA968ull
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
+#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x59BA970ull
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
+#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x59BA978ull
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
+#define NIC11_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
+#define mmNIC11_QM1_AXUSER_SECURED_BASE 0x59BAB00ull
+#define NIC11_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000
+#define NIC11_QM1_AXUSER_SECURED_SECTION 0x8000
+#define mmNIC11_QM1_AXUSER_NONSECURED_BASE 0x59BAB80ull
+#define NIC11_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000
+#define NIC11_QM1_AXUSER_NONSECURED_SECTION 0x8000
+#define mmNIC11_QM1_DBG_HBW_BASE 0x59BAC00ull
+#define NIC11_QM1_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC11_QM1_DBG_HBW_SECTION 0x8000
+#define mmNIC11_QM1_DBG_LBW_BASE 0x59BAC80ull
+#define NIC11_QM1_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC11_QM1_DBG_LBW_SECTION 0x1000
+#define mmNIC11_QM1_CGM_BASE 0x59BAD80ull
+#define NIC11_QM1_CGM_MAX_OFFSET 0xC000
+#define NIC11_QM1_CGM_SECTION 0x1000
+#define mmNIC11_QM1_SPECIAL_BASE 0x59BAE80ull
+#define NIC11_QM1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_QM1_SPECIAL_SECTION 0x4180
+#define mmNIC11_QPC1_BASE 0x59BF000ull
+#define NIC11_QPC1_MAX_OFFSET 0x1000
+#define NIC11_QPC1_SECTION 0x7200
+#define mmNIC11_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x59BF720ull
+#define NIC11_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x59BF728ull
+#define NIC11_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x59BF730ull
+#define NIC11_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x59BF738ull
+#define NIC11_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x59BF740ull
+#define NIC11_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x59BF748ull
+#define NIC11_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x59BF750ull
+#define NIC11_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x59BF758ull
+#define NIC11_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x59BF760ull
+#define NIC11_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x59BF768ull
+#define NIC11_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x59BF770ull
+#define NIC11_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x59BF778ull
+#define NIC11_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x59BF780ull
+#define NIC11_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x59BF788ull
+#define NIC11_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x59BF790ull
+#define NIC11_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x59BF798ull
+#define NIC11_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x59BF7A0ull
+#define NIC11_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x59BF7A8ull
+#define NIC11_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x59BF7B0ull
+#define NIC11_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x59BF7B8ull
+#define NIC11_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x59BF7C0ull
+#define NIC11_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x59BF7C8ull
+#define NIC11_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x59BF7D0ull
+#define NIC11_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x59BF7D8ull
+#define NIC11_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x59BF7E0ull
+#define NIC11_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x59BF7E8ull
+#define NIC11_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x59BF7F0ull
+#define NIC11_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x59BF7F8ull
+#define NIC11_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x59BF800ull
+#define NIC11_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x59BF808ull
+#define NIC11_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x59BF810ull
+#define NIC11_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
+#define mmNIC11_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x59BF818ull
+#define NIC11_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
+#define NIC11_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
+#define mmNIC11_QPC1_AXUSER_CONG_QUE_BASE 0x59BFB80ull
+#define NIC11_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
+#define NIC11_QPC1_AXUSER_CONG_QUE_SECTION 0x6000
+#define mmNIC11_QPC1_AXUSER_RXWQE_BASE 0x59BFBE0ull
+#define NIC11_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000
+#define NIC11_QPC1_AXUSER_RXWQE_SECTION 0x6000
+#define mmNIC11_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x59BFC40ull
+#define NIC11_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
+#define NIC11_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
+#define mmNIC11_QPC1_AXUSER_DB_FIFO_BASE 0x59BFCA0ull
+#define NIC11_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
+#define NIC11_QPC1_AXUSER_DB_FIFO_SECTION 0x6000
+#define mmNIC11_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x59BFD00ull
+#define NIC11_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
+#define NIC11_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
+#define mmNIC11_QPC1_AXUSER_ERR_FIFO_BASE 0x59BFD60ull
+#define NIC11_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
+#define NIC11_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000
+#define mmNIC11_QPC1_AXUSER_QPC_RESP_BASE 0x59BFDC0ull
+#define NIC11_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
+#define NIC11_QPC1_AXUSER_QPC_RESP_SECTION 0x6000
+#define mmNIC11_QPC1_AXUSER_QPC_REQ_BASE 0x59BFE20ull
+#define NIC11_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
+#define NIC11_QPC1_AXUSER_QPC_REQ_SECTION 0x6000
+#define mmNIC11_QPC1_SPECIAL_BASE 0x59BFE80ull
+#define NIC11_QPC1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_QPC1_SPECIAL_SECTION 0x8180
+#define mmNIC11_TMR_BASE 0x59C8000ull
+#define NIC11_TMR_MAX_OFFSET 0x1000
+#define NIC11_TMR_SECTION 0xD600
+#define mmNIC11_TMR_AXUSER_TMR_FREE_LIST_BASE 0x59C8D60ull
+#define NIC11_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000
+#define NIC11_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000
+#define mmNIC11_TMR_AXUSER_TMR_FIFO_BASE 0x59C8DC0ull
+#define NIC11_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000
+#define NIC11_TMR_AXUSER_TMR_FIFO_SECTION 0x6000
+#define mmNIC11_TMR_AXUSER_TMR_FSM_BASE 0x59C8E20ull
+#define NIC11_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000
+#define NIC11_TMR_AXUSER_TMR_FSM_SECTION 0x6000
+#define mmNIC11_TMR_SPECIAL_BASE 0x59C8E80ull
+#define NIC11_TMR_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_TMR_SPECIAL_SECTION 0x1800
+#define mmNIC11_RXB_CORE_BASE 0x59C9000ull
+#define NIC11_RXB_CORE_MAX_OFFSET 0x1000
+#define NIC11_RXB_CORE_SECTION 0x6100
+#define mmNIC11_RXB_CORE_SCT_AWUSER_BASE 0x59C9610ull
+#define NIC11_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000
+#define NIC11_RXB_CORE_SCT_AWUSER_SECTION 0x8700
+#define mmNIC11_RXB_CORE_SPECIAL_BASE 0x59C9E80ull
+#define NIC11_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_RXB_CORE_SPECIAL_SECTION 0x1800
+#define mmNIC11_RXE0_BASE 0x59CA000ull
+#define NIC11_RXE0_MAX_OFFSET 0x1000
+#define NIC11_RXE0_SECTION 0x9000
+#define mmNIC11_RXE0_WQE_ARUSER_BASE 0x59CA900ull
+#define NIC11_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC11_RXE0_WQE_ARUSER_SECTION 0x5800
+#define mmNIC11_RXE0_SPECIAL_BASE 0x59CAE80ull
+#define NIC11_RXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_RXE0_SPECIAL_SECTION 0x1800
+#define mmNIC11_RXE1_BASE 0x59CB000ull
+#define NIC11_RXE1_MAX_OFFSET 0x1000
+#define NIC11_RXE1_SECTION 0x9000
+#define mmNIC11_RXE1_WQE_ARUSER_BASE 0x59CB900ull
+#define NIC11_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000
+#define NIC11_RXE1_WQE_ARUSER_SECTION 0x5800
+#define mmNIC11_RXE1_SPECIAL_BASE 0x59CBE80ull
+#define NIC11_RXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_RXE1_SPECIAL_SECTION 0x1800
+#define mmNIC11_RXE0_AXUSER_AXUSER_CQ0_BASE 0x59CC000ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define mmNIC11_RXE0_AXUSER_AXUSER_CQ1_BASE 0x59CC050ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define mmNIC11_RXE0_AXUSER_AXUSER_CQ2_BASE 0x59CC0A0ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define mmNIC11_RXE0_AXUSER_AXUSER_CQ3_BASE 0x59CC0F0ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define mmNIC11_RXE0_AXUSER_AXUSER_CQ4_BASE 0x59CC140ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define mmNIC11_RXE0_AXUSER_AXUSER_CQ5_BASE 0x59CC190ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define mmNIC11_RXE0_AXUSER_AXUSER_CQ6_BASE 0x59CC1E0ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define mmNIC11_RXE0_AXUSER_AXUSER_CQ7_BASE 0x59CC230ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define mmNIC11_RXE0_AXUSER_AXUSER_CQ8_BASE 0x59CC280ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define mmNIC11_RXE0_AXUSER_AXUSER_CQ9_BASE 0x59CC2D0ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define mmNIC11_RXE0_AXUSER_AXUSER_CQ10_BASE 0x59CC320ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define mmNIC11_RXE0_AXUSER_AXUSER_CQ11_BASE 0x59CC370ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define mmNIC11_RXE0_AXUSER_AXUSER_CQ12_BASE 0x59CC3C0ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define mmNIC11_RXE0_AXUSER_AXUSER_CQ13_BASE 0x59CC410ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define mmNIC11_RXE0_AXUSER_AXUSER_CQ14_BASE 0x59CC460ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define mmNIC11_RXE0_AXUSER_AXUSER_CQ15_BASE 0x59CC4B0ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define mmNIC11_RXE0_AXUSER_AXUSER_CQ16_BASE 0x59CC500ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define mmNIC11_RXE0_AXUSER_AXUSER_CQ17_BASE 0x59CC550ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define mmNIC11_RXE0_AXUSER_AXUSER_CQ18_BASE 0x59CC5A0ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define mmNIC11_RXE0_AXUSER_AXUSER_CQ19_BASE 0x59CC5F0ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define mmNIC11_RXE0_AXUSER_AXUSER_CQ20_BASE 0x59CC640ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define mmNIC11_RXE0_AXUSER_AXUSER_CQ21_BASE 0x59CC690ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define mmNIC11_RXE0_AXUSER_AXUSER_CQ22_BASE 0x59CC6E0ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define mmNIC11_RXE0_AXUSER_AXUSER_CQ23_BASE 0x59CC730ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define mmNIC11_RXE0_AXUSER_AXUSER_CQ24_BASE 0x59CC780ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define mmNIC11_RXE0_AXUSER_AXUSER_CQ25_BASE 0x59CC7D0ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define mmNIC11_RXE0_AXUSER_AXUSER_CQ26_BASE 0x59CC820ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define mmNIC11_RXE0_AXUSER_AXUSER_CQ27_BASE 0x59CC870ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define mmNIC11_RXE0_AXUSER_AXUSER_CQ28_BASE 0x59CC8C0ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define mmNIC11_RXE0_AXUSER_AXUSER_CQ29_BASE 0x59CC910ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define mmNIC11_RXE0_AXUSER_AXUSER_CQ30_BASE 0x59CC960ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define mmNIC11_RXE0_AXUSER_AXUSER_CQ31_BASE 0x59CC9B0ull
+#define NIC11_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC11_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define mmNIC11_RXE0_AXUSER_SPECIAL_BASE 0x59CCE80ull
+#define NIC11_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_RXE0_AXUSER_SPECIAL_SECTION 0x1800
+#define mmNIC11_RXE1_AXUSER_AXUSER_CQ0_BASE 0x59CD000ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000
+#define mmNIC11_RXE1_AXUSER_AXUSER_CQ1_BASE 0x59CD050ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000
+#define mmNIC11_RXE1_AXUSER_AXUSER_CQ2_BASE 0x59CD0A0ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000
+#define mmNIC11_RXE1_AXUSER_AXUSER_CQ3_BASE 0x59CD0F0ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000
+#define mmNIC11_RXE1_AXUSER_AXUSER_CQ4_BASE 0x59CD140ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000
+#define mmNIC11_RXE1_AXUSER_AXUSER_CQ5_BASE 0x59CD190ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000
+#define mmNIC11_RXE1_AXUSER_AXUSER_CQ6_BASE 0x59CD1E0ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000
+#define mmNIC11_RXE1_AXUSER_AXUSER_CQ7_BASE 0x59CD230ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000
+#define mmNIC11_RXE1_AXUSER_AXUSER_CQ8_BASE 0x59CD280ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000
+#define mmNIC11_RXE1_AXUSER_AXUSER_CQ9_BASE 0x59CD2D0ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000
+#define mmNIC11_RXE1_AXUSER_AXUSER_CQ10_BASE 0x59CD320ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000
+#define mmNIC11_RXE1_AXUSER_AXUSER_CQ11_BASE 0x59CD370ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000
+#define mmNIC11_RXE1_AXUSER_AXUSER_CQ12_BASE 0x59CD3C0ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000
+#define mmNIC11_RXE1_AXUSER_AXUSER_CQ13_BASE 0x59CD410ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000
+#define mmNIC11_RXE1_AXUSER_AXUSER_CQ14_BASE 0x59CD460ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000
+#define mmNIC11_RXE1_AXUSER_AXUSER_CQ15_BASE 0x59CD4B0ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000
+#define mmNIC11_RXE1_AXUSER_AXUSER_CQ16_BASE 0x59CD500ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000
+#define mmNIC11_RXE1_AXUSER_AXUSER_CQ17_BASE 0x59CD550ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000
+#define mmNIC11_RXE1_AXUSER_AXUSER_CQ18_BASE 0x59CD5A0ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000
+#define mmNIC11_RXE1_AXUSER_AXUSER_CQ19_BASE 0x59CD5F0ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000
+#define mmNIC11_RXE1_AXUSER_AXUSER_CQ20_BASE 0x59CD640ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000
+#define mmNIC11_RXE1_AXUSER_AXUSER_CQ21_BASE 0x59CD690ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000
+#define mmNIC11_RXE1_AXUSER_AXUSER_CQ22_BASE 0x59CD6E0ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000
+#define mmNIC11_RXE1_AXUSER_AXUSER_CQ23_BASE 0x59CD730ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000
+#define mmNIC11_RXE1_AXUSER_AXUSER_CQ24_BASE 0x59CD780ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000
+#define mmNIC11_RXE1_AXUSER_AXUSER_CQ25_BASE 0x59CD7D0ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000
+#define mmNIC11_RXE1_AXUSER_AXUSER_CQ26_BASE 0x59CD820ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000
+#define mmNIC11_RXE1_AXUSER_AXUSER_CQ27_BASE 0x59CD870ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000
+#define mmNIC11_RXE1_AXUSER_AXUSER_CQ28_BASE 0x59CD8C0ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000
+#define mmNIC11_RXE1_AXUSER_AXUSER_CQ29_BASE 0x59CD910ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000
+#define mmNIC11_RXE1_AXUSER_AXUSER_CQ30_BASE 0x59CD960ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000
+#define mmNIC11_RXE1_AXUSER_AXUSER_CQ31_BASE 0x59CD9B0ull
+#define NIC11_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
+#define NIC11_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00
+#define mmNIC11_RXE1_AXUSER_SPECIAL_BASE 0x59CDE80ull
+#define NIC11_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_RXE1_AXUSER_SPECIAL_SECTION 0x2180
+#define mmNIC11_TXS0_BASE 0x59D0000ull
+#define NIC11_TXS0_MAX_OFFSET 0x1000
+#define NIC11_TXS0_SECTION 0xE800
+#define mmNIC11_TXS0_SPECIAL_BASE 0x59D0E80ull
+#define NIC11_TXS0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_TXS0_SPECIAL_SECTION 0x1800
+#define mmNIC11_TXS1_BASE 0x59D1000ull
+#define NIC11_TXS1_MAX_OFFSET 0x1000
+#define NIC11_TXS1_SECTION 0xE800
+#define mmNIC11_TXS1_SPECIAL_BASE 0x59D1E80ull
+#define NIC11_TXS1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_TXS1_SPECIAL_SECTION 0x1800
+#define mmNIC11_TXE0_BASE 0x59D2000ull
+#define NIC11_TXE0_MAX_OFFSET 0x1000
+#define NIC11_TXE0_SECTION 0xE800
+#define mmNIC11_TXE0_SPECIAL_BASE 0x59D2E80ull
+#define NIC11_TXE0_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_TXE0_SPECIAL_SECTION 0x1800
+#define mmNIC11_TXE1_BASE 0x59D3000ull
+#define NIC11_TXE1_MAX_OFFSET 0x1000
+#define NIC11_TXE1_SECTION 0xE800
+#define mmNIC11_TXE1_SPECIAL_BASE 0x59D3E80ull
+#define NIC11_TXE1_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_TXE1_SPECIAL_SECTION 0x1800
+#define mmNIC11_TXB_BASE 0x59D4000ull
+#define NIC11_TXB_MAX_OFFSET 0x1000
+#define NIC11_TXB_SECTION 0xE800
+#define mmNIC11_TXB_SPECIAL_BASE 0x59D4E80ull
+#define NIC11_TXB_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_TXB_SPECIAL_SECTION 0x1800
+#define mmNIC11_MSTR_IF_RR_SHRD_HBW_BASE 0x59D5000ull
+#define NIC11_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
+#define NIC11_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
+#define mmNIC11_MSTR_IF_RR_PRVT_HBW_BASE 0x59D5200ull
+#define NIC11_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
+#define NIC11_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
+#define mmNIC11_MSTR_IF_RR_SHRD_LBW_BASE 0x59D5400ull
+#define NIC11_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
+#define NIC11_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
+#define mmNIC11_MSTR_IF_RR_PRVT_LBW_BASE 0x59D5600ull
+#define NIC11_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
+#define NIC11_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
+#define mmNIC11_MSTR_IF_E2E_CRDT_BASE 0x59D5800ull
+#define NIC11_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
+#define NIC11_MSTR_IF_E2E_CRDT_SECTION 0x2800
+#define mmNIC11_MSTR_IF_AXUSER_BASE 0x59D5A80ull
+#define NIC11_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
+#define NIC11_MSTR_IF_AXUSER_SECTION 0x8000
+#define mmNIC11_MSTR_IF_DBG_HBW_BASE 0x59D5B00ull
+#define NIC11_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
+#define NIC11_MSTR_IF_DBG_HBW_SECTION 0x8000
+#define mmNIC11_MSTR_IF_DBG_LBW_BASE 0x59D5B80ull
+#define NIC11_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
+#define NIC11_MSTR_IF_DBG_LBW_SECTION 0x8000
+#define mmNIC11_MSTR_IF_CORE_HBW_BASE 0x59D5C00ull
+#define NIC11_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
+#define NIC11_MSTR_IF_CORE_HBW_SECTION 0x1800
+#define mmNIC11_MSTR_IF_CORE_LBW_BASE 0x59D5D80ull
+#define NIC11_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
+#define NIC11_MSTR_IF_CORE_LBW_SECTION 0x1000
+#define mmNIC11_MSTR_IF_SPECIAL_BASE 0x59D5E80ull
+#define NIC11_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_MSTR_IF_SPECIAL_SECTION 0x1800
+#define mmNIC11_TX_AXUSER_BASE 0x59D6000ull
+#define NIC11_TX_AXUSER_MAX_OFFSET 0x5000
+#define NIC11_TX_AXUSER_SECTION 0x2000
+#define mmNIC11_SERDES0_BASE 0x59D8000ull
+#define NIC11_SERDES0_MAX_OFFSET 0x3E40
+#define NIC11_SERDES0_SECTION 0x4000
+#define mmNIC11_SERDES1_BASE 0x59DC000ull
+#define NIC11_SERDES1_MAX_OFFSET 0x3E40
+#define NIC11_SERDES1_SECTION 0x4000
+#define mmNIC11_PHY_BASE 0x59E0000ull
+#define NIC11_PHY_MAX_OFFSET 0x1000
+#define NIC11_PHY_SECTION 0xE800
+#define mmNIC11_PHY_SPECIAL_BASE 0x59E0E80ull
+#define NIC11_PHY_SPECIAL_MAX_OFFSET 0x1800
+#define NIC11_PHY_SPECIAL_SECTION 0x7180
+#define mmPRT11_MAC_AUX_BASE 0x59E8000ull
+#define PRT11_MAC_AUX_MAX_OFFSET 0x1000
+#define PRT11_MAC_AUX_SECTION 0xE800
+#define mmPRT11_MAC_AUX_SPECIAL_BASE 0x59E8E80ull
+#define PRT11_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800
+#define PRT11_MAC_AUX_SPECIAL_SECTION 0x1800
+#define mmPRT11_MAC_CORE_BASE 0x59E9000ull
+#define PRT11_MAC_CORE_MAX_OFFSET 0x1000
+#define PRT11_MAC_CORE_SECTION 0xE800
+#define mmPRT11_MAC_CORE_SPECIAL_BASE 0x59E9E80ull
+#define PRT11_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800
+#define PRT11_MAC_CORE_SPECIAL_SECTION 0x1800
+#define mmNIC11_MAC_RS_FEC_BASE 0x59EA000ull
+#define NIC11_MAC_RS_FEC_MAX_OFFSET 0x2DC0
+#define NIC11_MAC_RS_FEC_SECTION 0x1000
+#define mmNIC11_MAC_GLOB_STAT_CONTROL_REG_BASE 0x59EB000ull
+#define NIC11_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000
+#define NIC11_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000
+#define mmNIC11_MAC_GLOB_STAT_RX0_BASE 0x59EB100ull
+#define NIC11_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00
+#define NIC11_MAC_GLOB_STAT_RX0_SECTION 0x8C00
+#define mmNIC11_MAC_GLOB_STAT_RX1_BASE 0x59EB18Cull
+#define NIC11_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00
+#define NIC11_MAC_GLOB_STAT_RX1_SECTION 0x8C00
+#define mmNIC11_MAC_GLOB_STAT_RX2_BASE 0x59EB218ull
+#define NIC11_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00
+#define NIC11_MAC_GLOB_STAT_RX2_SECTION 0x8C00
+#define mmNIC11_MAC_GLOB_STAT_RX3_BASE 0x59EB2A4ull
+#define NIC11_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00
+#define NIC11_MAC_GLOB_STAT_RX3_SECTION 0x8C00
+#define mmNIC11_MAC_GLOB_STAT_TX0_BASE 0x59EB330ull
+#define NIC11_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800
+#define NIC11_MAC_GLOB_STAT_TX0_SECTION 0x6800
+#define mmNIC11_MAC_GLOB_STAT_TX1_BASE 0x59EB398ull
+#define NIC11_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800
+#define NIC11_MAC_GLOB_STAT_TX1_SECTION 0x6800
+#define mmNIC11_MAC_GLOB_STAT_TX2_BASE 0x59EB400ull
+#define NIC11_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800
+#define NIC11_MAC_GLOB_STAT_TX2_SECTION 0x6800
+#define mmNIC11_MAC_GLOB_STAT_TX3_BASE 0x59EB468ull
+#define NIC11_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800
+#define NIC11_MAC_GLOB_STAT_TX3_SECTION 0x3980
+#define mmNIC11_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x59EB800ull
+#define NIC11_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0
+#define NIC11_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000
+#define mmNIC11_MAC_CH0_MAC_PCS_BASE 0x59EC000ull
+#define NIC11_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC11_MAC_CH0_MAC_PCS_SECTION 0x4000
+#define mmNIC11_MAC_CH0_MAC_128_BASE 0x59EC400ull
+#define NIC11_MAC_CH0_MAC_128_MAX_OFFSET 0xA400
+#define NIC11_MAC_CH0_MAC_128_SECTION 0x4000
+#define mmNIC11_MAC_CH0_MAC_AN_BASE 0x59EC800ull
+#define NIC11_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400
+#define NIC11_MAC_CH0_MAC_AN_SECTION 0x8000
+#define mmNIC11_MAC_CH1_MAC_PCS_BASE 0x59ED000ull
+#define NIC11_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC11_MAC_CH1_MAC_PCS_SECTION 0x4000
+#define mmNIC11_MAC_CH1_MAC_128_BASE 0x59ED400ull
+#define NIC11_MAC_CH1_MAC_128_MAX_OFFSET 0xA400
+#define NIC11_MAC_CH1_MAC_128_SECTION 0x4000
+#define mmNIC11_MAC_CH1_MAC_AN_BASE 0x59ED800ull
+#define NIC11_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400
+#define NIC11_MAC_CH1_MAC_AN_SECTION 0x8000
+#define mmNIC11_MAC_CH2_MAC_PCS_BASE 0x59EE000ull
+#define NIC11_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC11_MAC_CH2_MAC_PCS_SECTION 0x4000
+#define mmNIC11_MAC_CH2_MAC_128_BASE 0x59EE400ull
+#define NIC11_MAC_CH2_MAC_128_MAX_OFFSET 0xA400
+#define NIC11_MAC_CH2_MAC_128_SECTION 0x4000
+#define mmNIC11_MAC_CH2_MAC_AN_BASE 0x59EE800ull
+#define NIC11_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400
+#define NIC11_MAC_CH2_MAC_AN_SECTION 0x8000
+#define mmNIC11_MAC_CH3_MAC_PCS_BASE 0x59EF000ull
+#define NIC11_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0
+#define NIC11_MAC_CH3_MAC_PCS_SECTION 0x4000
+#define mmNIC11_MAC_CH3_MAC_128_BASE 0x59EF400ull
+#define NIC11_MAC_CH3_MAC_128_MAX_OFFSET 0xA400
+#define NIC11_MAC_CH3_MAC_128_SECTION 0x4000
+#define mmNIC11_MAC_CH3_MAC_AN_BASE 0x59EF800ull
+#define NIC11_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400
+#define NIC11_MAC_CH3_MAC_AN_SECTION 0x610800
+#define mmDCORE0_ROM_TABLE_L_BASE 0x6000000ull
+#define DCORE0_ROM_TABLE_L_MAX_OFFSET 0x1000
+#define DCORE0_ROM_TABLE_L_SECTION 0x80000
+#define mmDCORE0_HMMU0_CS_ROM_TBL_BASE 0x6080000ull
+#define DCORE0_HMMU0_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE0_HMMU0_CS_ROM_TBL_SECTION 0x1000
+#define mmDCORE0_HMMU0_CS_STM_BASE 0x6081000ull
+#define DCORE0_HMMU0_CS_STM_MAX_OFFSET 0x1000
+#define DCORE0_HMMU0_CS_STM_SECTION 0x1000
+#define mmDCORE0_HMMU0_CS_CTI_BASE 0x6082000ull
+#define DCORE0_HMMU0_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE0_HMMU0_CS_CTI_SECTION 0x1000
+#define mmDCORE0_HMMU0_CS_ETF_BASE 0x6083000ull
+#define DCORE0_HMMU0_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE0_HMMU0_CS_ETF_SECTION 0x1000
+#define mmDCORE0_HMMU0_CS_SPMU_BASE 0x6084000ull
+#define DCORE0_HMMU0_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_HMMU0_CS_SPMU_SECTION 0x1000
+#define mmDCORE0_HMMU0_BMON_CTI_BASE 0x6085000ull
+#define DCORE0_HMMU0_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE0_HMMU0_BMON_CTI_SECTION 0x1000
+#define mmDCORE0_HMMU0_USER_CTI_BASE 0x6086000ull
+#define DCORE0_HMMU0_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE0_HMMU0_USER_CTI_SECTION 0x1000
+#define mmDCORE0_HMMU0_BMON_0_BASE 0x6087000ull
+#define DCORE0_HMMU0_BMON_0_MAX_OFFSET 0x1000
+#define DCORE0_HMMU0_BMON_0_SECTION 0x1000
+#define mmDCORE0_HMMU0_BMON_1_BASE 0x6088000ull
+#define DCORE0_HMMU0_BMON_1_MAX_OFFSET 0x1000
+#define DCORE0_HMMU0_BMON_1_SECTION 0x1000
+#define mmDCORE0_HMMU0_BMON_3_BASE 0x6089000ull
+#define DCORE0_HMMU0_BMON_3_MAX_OFFSET 0x1000
+#define DCORE0_HMMU0_BMON_3_SECTION 0x1000
+#define mmDCORE0_HMMU0_BMON_2_BASE 0x608A000ull
+#define DCORE0_HMMU0_BMON_2_MAX_OFFSET 0x1000
+#define DCORE0_HMMU0_BMON_2_SECTION 0x1000
+#define mmDCORE0_HMMU0_BMON_4_BASE 0x608B000ull
+#define DCORE0_HMMU0_BMON_4_MAX_OFFSET 0x1000
+#define DCORE0_HMMU0_BMON_4_SECTION 0x5000
+#define mmDCORE0_HMMU1_CS_ROM_TBL_BASE 0x6090000ull
+#define DCORE0_HMMU1_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE0_HMMU1_CS_ROM_TBL_SECTION 0x1000
+#define mmDCORE0_HMMU1_CS_STM_BASE 0x6091000ull
+#define DCORE0_HMMU1_CS_STM_MAX_OFFSET 0x1000
+#define DCORE0_HMMU1_CS_STM_SECTION 0x1000
+#define mmDCORE0_HMMU1_CS_CTI_BASE 0x6092000ull
+#define DCORE0_HMMU1_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE0_HMMU1_CS_CTI_SECTION 0x1000
+#define mmDCORE0_HMMU1_CS_ETF_BASE 0x6093000ull
+#define DCORE0_HMMU1_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE0_HMMU1_CS_ETF_SECTION 0x1000
+#define mmDCORE0_HMMU1_CS_SPMU_BASE 0x6094000ull
+#define DCORE0_HMMU1_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_HMMU1_CS_SPMU_SECTION 0x1000
+#define mmDCORE0_HMMU1_BMON_CTI_BASE 0x6095000ull
+#define DCORE0_HMMU1_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE0_HMMU1_BMON_CTI_SECTION 0x1000
+#define mmDCORE0_HMMU1_USER_CTI_BASE 0x6096000ull
+#define DCORE0_HMMU1_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE0_HMMU1_USER_CTI_SECTION 0x1000
+#define mmDCORE0_HMMU1_BMON_0_BASE 0x6097000ull
+#define DCORE0_HMMU1_BMON_0_MAX_OFFSET 0x1000
+#define DCORE0_HMMU1_BMON_0_SECTION 0x1000
+#define mmDCORE0_HMMU1_BMON_1_BASE 0x6098000ull
+#define DCORE0_HMMU1_BMON_1_MAX_OFFSET 0x1000
+#define DCORE0_HMMU1_BMON_1_SECTION 0x1000
+#define mmDCORE0_HMMU1_BMON_3_BASE 0x6099000ull
+#define DCORE0_HMMU1_BMON_3_MAX_OFFSET 0x1000
+#define DCORE0_HMMU1_BMON_3_SECTION 0x1000
+#define mmDCORE0_HMMU1_BMON_2_BASE 0x609A000ull
+#define DCORE0_HMMU1_BMON_2_MAX_OFFSET 0x1000
+#define DCORE0_HMMU1_BMON_2_SECTION 0x1000
+#define mmDCORE0_HMMU1_BMON_4_BASE 0x609B000ull
+#define DCORE0_HMMU1_BMON_4_MAX_OFFSET 0x1000
+#define DCORE0_HMMU1_BMON_4_SECTION 0x5000
+#define mmDCORE0_HMMU2_CS_ROM_TBL_BASE 0x60A0000ull
+#define DCORE0_HMMU2_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE0_HMMU2_CS_ROM_TBL_SECTION 0x1000
+#define mmDCORE0_HMMU2_CS_STM_BASE 0x60A1000ull
+#define DCORE0_HMMU2_CS_STM_MAX_OFFSET 0x1000
+#define DCORE0_HMMU2_CS_STM_SECTION 0x1000
+#define mmDCORE0_HMMU2_CS_CTI_BASE 0x60A2000ull
+#define DCORE0_HMMU2_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE0_HMMU2_CS_CTI_SECTION 0x1000
+#define mmDCORE0_HMMU2_CS_ETF_BASE 0x60A3000ull
+#define DCORE0_HMMU2_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE0_HMMU2_CS_ETF_SECTION 0x1000
+#define mmDCORE0_HMMU2_CS_SPMU_BASE 0x60A4000ull
+#define DCORE0_HMMU2_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_HMMU2_CS_SPMU_SECTION 0x1000
+#define mmDCORE0_HMMU2_BMON_CTI_BASE 0x60A5000ull
+#define DCORE0_HMMU2_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE0_HMMU2_BMON_CTI_SECTION 0x1000
+#define mmDCORE0_HMMU2_USER_CTI_BASE 0x60A6000ull
+#define DCORE0_HMMU2_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE0_HMMU2_USER_CTI_SECTION 0x1000
+#define mmDCORE0_HMMU2_BMON_0_BASE 0x60A7000ull
+#define DCORE0_HMMU2_BMON_0_MAX_OFFSET 0x1000
+#define DCORE0_HMMU2_BMON_0_SECTION 0x1000
+#define mmDCORE0_HMMU2_BMON_1_BASE 0x60A8000ull
+#define DCORE0_HMMU2_BMON_1_MAX_OFFSET 0x1000
+#define DCORE0_HMMU2_BMON_1_SECTION 0x1000
+#define mmDCORE0_HMMU2_BMON_3_BASE 0x60A9000ull
+#define DCORE0_HMMU2_BMON_3_MAX_OFFSET 0x1000
+#define DCORE0_HMMU2_BMON_3_SECTION 0x1000
+#define mmDCORE0_HMMU2_BMON_2_BASE 0x60AA000ull
+#define DCORE0_HMMU2_BMON_2_MAX_OFFSET 0x1000
+#define DCORE0_HMMU2_BMON_2_SECTION 0x1000
+#define mmDCORE0_HMMU2_BMON_4_BASE 0x60AB000ull
+#define DCORE0_HMMU2_BMON_4_MAX_OFFSET 0x1000
+#define DCORE0_HMMU2_BMON_4_SECTION 0x5000
+#define mmDCORE0_HMMU3_CS_ROM_TBL_BASE 0x60B0000ull
+#define DCORE0_HMMU3_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE0_HMMU3_CS_ROM_TBL_SECTION 0x1000
+#define mmDCORE0_HMMU3_CS_STM_BASE 0x60B1000ull
+#define DCORE0_HMMU3_CS_STM_MAX_OFFSET 0x1000
+#define DCORE0_HMMU3_CS_STM_SECTION 0x1000
+#define mmDCORE0_HMMU3_CS_CTI_BASE 0x60B2000ull
+#define DCORE0_HMMU3_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE0_HMMU3_CS_CTI_SECTION 0x1000
+#define mmDCORE0_HMMU3_CS_ETF_BASE 0x60B3000ull
+#define DCORE0_HMMU3_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE0_HMMU3_CS_ETF_SECTION 0x1000
+#define mmDCORE0_HMMU3_CS_SPMU_BASE 0x60B4000ull
+#define DCORE0_HMMU3_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_HMMU3_CS_SPMU_SECTION 0x1000
+#define mmDCORE0_HMMU3_BMON_CTI_BASE 0x60B5000ull
+#define DCORE0_HMMU3_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE0_HMMU3_BMON_CTI_SECTION 0x1000
+#define mmDCORE0_HMMU3_USER_CTI_BASE 0x60B6000ull
+#define DCORE0_HMMU3_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE0_HMMU3_USER_CTI_SECTION 0x1000
+#define mmDCORE0_HMMU3_BMON_0_BASE 0x60B7000ull
+#define DCORE0_HMMU3_BMON_0_MAX_OFFSET 0x1000
+#define DCORE0_HMMU3_BMON_0_SECTION 0x1000
+#define mmDCORE0_HMMU3_BMON_1_BASE 0x60B8000ull
+#define DCORE0_HMMU3_BMON_1_MAX_OFFSET 0x1000
+#define DCORE0_HMMU3_BMON_1_SECTION 0x1000
+#define mmDCORE0_HMMU3_BMON_3_BASE 0x60B9000ull
+#define DCORE0_HMMU3_BMON_3_MAX_OFFSET 0x1000
+#define DCORE0_HMMU3_BMON_3_SECTION 0x1000
+#define mmDCORE0_HMMU3_BMON_2_BASE 0x60BA000ull
+#define DCORE0_HMMU3_BMON_2_MAX_OFFSET 0x1000
+#define DCORE0_HMMU3_BMON_2_SECTION 0x1000
+#define mmDCORE0_HMMU3_BMON_4_BASE 0x60BB000ull
+#define DCORE0_HMMU3_BMON_4_MAX_OFFSET 0x1000
+#define DCORE0_HMMU3_BMON_4_SECTION 0x5000
+#define mmDCORE0_MME_CTRL_ROM_TABLE_BASE 0x60C0000ull
+#define DCORE0_MME_CTRL_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE0_MME_CTRL_ROM_TABLE_SECTION 0x1000
+#define mmDCORE0_MME_CTRL_STM_BASE 0x60C1000ull
+#define DCORE0_MME_CTRL_STM_MAX_OFFSET 0x1000
+#define DCORE0_MME_CTRL_STM_SECTION 0x1000
+#define mmDCORE0_MME_CTRL_CTI_BASE 0x60C2000ull
+#define DCORE0_MME_CTRL_CTI_MAX_OFFSET 0x1000
+#define DCORE0_MME_CTRL_CTI_SECTION 0x1000
+#define mmDCORE0_MME_CTRL_ETF_BASE 0x60C3000ull
+#define DCORE0_MME_CTRL_ETF_MAX_OFFSET 0x1000
+#define DCORE0_MME_CTRL_ETF_SECTION 0x1000
+#define mmDCORE0_MME_CTRL_SPMU_BASE 0x60C4000ull
+#define DCORE0_MME_CTRL_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_MME_CTRL_SPMU_SECTION 0x1000
+#define mmDCORE0_MME_CTRL_CTI0_BASE 0x60C5000ull
+#define DCORE0_MME_CTRL_CTI0_MAX_OFFSET 0x1000
+#define DCORE0_MME_CTRL_CTI0_SECTION 0x1000
+#define mmDCORE0_MME_CTRL_CTI1_BASE 0x60C6000ull
+#define DCORE0_MME_CTRL_CTI1_MAX_OFFSET 0x1000
+#define DCORE0_MME_CTRL_CTI1_SECTION 0x1000
+#define mmDCORE0_MME_CTRL_BMON0_BASE 0x60C7000ull
+#define DCORE0_MME_CTRL_BMON0_MAX_OFFSET 0x1000
+#define DCORE0_MME_CTRL_BMON0_SECTION 0x1000
+#define mmDCORE0_MME_CTRL_BMON1_BASE 0x60C8000ull
+#define DCORE0_MME_CTRL_BMON1_MAX_OFFSET 0x1000
+#define DCORE0_MME_CTRL_BMON1_SECTION 0x1000
+#define mmDCORE0_MME_CTRL_BMON2_BASE 0x60C9000ull
+#define DCORE0_MME_CTRL_BMON2_MAX_OFFSET 0x1000
+#define DCORE0_MME_CTRL_BMON2_SECTION 0x1000
+#define mmDCORE0_MME_CTRL_BMON3_BASE 0x60CA000ull
+#define DCORE0_MME_CTRL_BMON3_MAX_OFFSET 0x1000
+#define DCORE0_MME_CTRL_BMON3_SECTION 0x1000
+#define mmDCORE0_MME_CTRL_ARC_RTT_BASE 0x60CB000ull
+#define DCORE0_MME_CTRL_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE0_MME_CTRL_ARC_RTT_SECTION 0x5000
+#define mmDCORE0_MME_SBTE0_ROM_TBL_BASE 0x60D0000ull
+#define DCORE0_MME_SBTE0_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE0_ROM_TBL_SECTION 0x1000
+#define mmDCORE0_MME_SBTE0_STM_BASE 0x60D1000ull
+#define DCORE0_MME_SBTE0_STM_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE0_STM_SECTION 0x1000
+#define mmDCORE0_MME_SBTE0_CTI_BASE 0x60D2000ull
+#define DCORE0_MME_SBTE0_CTI_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE0_CTI_SECTION 0x1000
+#define mmDCORE0_MME_SBTE0_ETF_BASE 0x60D3000ull
+#define DCORE0_MME_SBTE0_ETF_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE0_ETF_SECTION 0x1000
+#define mmDCORE0_MME_SBTE0_SPMU_BASE 0x60D4000ull
+#define DCORE0_MME_SBTE0_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE0_SPMU_SECTION 0x1000
+#define mmDCORE0_MME_SBTE0_CTI0_BASE 0x60D5000ull
+#define DCORE0_MME_SBTE0_CTI0_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE0_CTI0_SECTION 0x1000
+#define mmDCORE0_MME_SBTE0_CTI1_BASE 0x60D6000ull
+#define DCORE0_MME_SBTE0_CTI1_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE0_CTI1_SECTION 0x1000
+#define mmDCORE0_MME_SBTE0_BMON0_BASE 0x60D7000ull
+#define DCORE0_MME_SBTE0_BMON0_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE0_BMON0_SECTION 0x1000
+#define mmDCORE0_MME_SBTE1_ROM_TBL_BASE 0x60D8000ull
+#define DCORE0_MME_SBTE1_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE1_ROM_TBL_SECTION 0x1000
+#define mmDCORE0_MME_SBTE1_STM_BASE 0x60D9000ull
+#define DCORE0_MME_SBTE1_STM_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE1_STM_SECTION 0x1000
+#define mmDCORE0_MME_SBTE1_CTI_BASE 0x60DA000ull
+#define DCORE0_MME_SBTE1_CTI_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE1_CTI_SECTION 0x1000
+#define mmDCORE0_MME_SBTE1_ETF_BASE 0x60DB000ull
+#define DCORE0_MME_SBTE1_ETF_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE1_ETF_SECTION 0x1000
+#define mmDCORE0_MME_SBTE1_SPMU_BASE 0x60DC000ull
+#define DCORE0_MME_SBTE1_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE1_SPMU_SECTION 0x1000
+#define mmDCORE0_MME_SBTE1_CTI0_BASE 0x60DD000ull
+#define DCORE0_MME_SBTE1_CTI0_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE1_CTI0_SECTION 0x1000
+#define mmDCORE0_MME_SBTE1_CTI1_BASE 0x60DE000ull
+#define DCORE0_MME_SBTE1_CTI1_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE1_CTI1_SECTION 0x1000
+#define mmDCORE0_MME_SBTE1_BMON0_BASE 0x60DF000ull
+#define DCORE0_MME_SBTE1_BMON0_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE1_BMON0_SECTION 0x1000
+#define mmDCORE0_MME_SBTE2_ROM_TBL_BASE 0x60E0000ull
+#define DCORE0_MME_SBTE2_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE2_ROM_TBL_SECTION 0x1000
+#define mmDCORE0_MME_SBTE2_STM_BASE 0x60E1000ull
+#define DCORE0_MME_SBTE2_STM_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE2_STM_SECTION 0x1000
+#define mmDCORE0_MME_SBTE2_CTI_BASE 0x60E2000ull
+#define DCORE0_MME_SBTE2_CTI_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE2_CTI_SECTION 0x1000
+#define mmDCORE0_MME_SBTE2_ETF_BASE 0x60E3000ull
+#define DCORE0_MME_SBTE2_ETF_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE2_ETF_SECTION 0x1000
+#define mmDCORE0_MME_SBTE2_SPMU_BASE 0x60E4000ull
+#define DCORE0_MME_SBTE2_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE2_SPMU_SECTION 0x1000
+#define mmDCORE0_MME_SBTE2_CTI0_BASE 0x60E5000ull
+#define DCORE0_MME_SBTE2_CTI0_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE2_CTI0_SECTION 0x1000
+#define mmDCORE0_MME_SBTE2_CTI1_BASE 0x60E6000ull
+#define DCORE0_MME_SBTE2_CTI1_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE2_CTI1_SECTION 0x1000
+#define mmDCORE0_MME_SBTE2_BMON0_BASE 0x60E7000ull
+#define DCORE0_MME_SBTE2_BMON0_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE2_BMON0_SECTION 0x1000
+#define mmDCORE0_MME_SBTE3_ROM_TBL_BASE 0x60E8000ull
+#define DCORE0_MME_SBTE3_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE3_ROM_TBL_SECTION 0x1000
+#define mmDCORE0_MME_SBTE3_STM_BASE 0x60E9000ull
+#define DCORE0_MME_SBTE3_STM_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE3_STM_SECTION 0x1000
+#define mmDCORE0_MME_SBTE3_CTI_BASE 0x60EA000ull
+#define DCORE0_MME_SBTE3_CTI_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE3_CTI_SECTION 0x1000
+#define mmDCORE0_MME_SBTE3_ETF_BASE 0x60EB000ull
+#define DCORE0_MME_SBTE3_ETF_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE3_ETF_SECTION 0x1000
+#define mmDCORE0_MME_SBTE3_SPMU_BASE 0x60EC000ull
+#define DCORE0_MME_SBTE3_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE3_SPMU_SECTION 0x1000
+#define mmDCORE0_MME_SBTE3_CTI0_BASE 0x60ED000ull
+#define DCORE0_MME_SBTE3_CTI0_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE3_CTI0_SECTION 0x1000
+#define mmDCORE0_MME_SBTE3_CTI1_BASE 0x60EE000ull
+#define DCORE0_MME_SBTE3_CTI1_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE3_CTI1_SECTION 0x1000
+#define mmDCORE0_MME_SBTE3_BMON0_BASE 0x60EF000ull
+#define DCORE0_MME_SBTE3_BMON0_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE3_BMON0_SECTION 0x1000
+#define mmDCORE0_MME_SBTE4_ROM_TBL_BASE 0x60F0000ull
+#define DCORE0_MME_SBTE4_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE4_ROM_TBL_SECTION 0x1000
+#define mmDCORE0_MME_SBTE4_STM_BASE 0x60F1000ull
+#define DCORE0_MME_SBTE4_STM_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE4_STM_SECTION 0x1000
+#define mmDCORE0_MME_SBTE4_CTI_BASE 0x60F2000ull
+#define DCORE0_MME_SBTE4_CTI_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE4_CTI_SECTION 0x1000
+#define mmDCORE0_MME_SBTE4_ETF_BASE 0x60F3000ull
+#define DCORE0_MME_SBTE4_ETF_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE4_ETF_SECTION 0x1000
+#define mmDCORE0_MME_SBTE4_SPMU_BASE 0x60F4000ull
+#define DCORE0_MME_SBTE4_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE4_SPMU_SECTION 0x1000
+#define mmDCORE0_MME_SBTE4_CTI0_BASE 0x60F5000ull
+#define DCORE0_MME_SBTE4_CTI0_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE4_CTI0_SECTION 0x1000
+#define mmDCORE0_MME_SBTE4_CTI1_BASE 0x60F6000ull
+#define DCORE0_MME_SBTE4_CTI1_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE4_CTI1_SECTION 0x1000
+#define mmDCORE0_MME_SBTE4_BMON0_BASE 0x60F7000ull
+#define DCORE0_MME_SBTE4_BMON0_MAX_OFFSET 0x1000
+#define DCORE0_MME_SBTE4_BMON0_SECTION 0x9000
+#define mmDCORE0_MME_ACC_CS_ROM_TBL_BASE 0x6100000ull
+#define DCORE0_MME_ACC_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE0_MME_ACC_CS_ROM_TBL_SECTION 0x1000
+#define mmDCORE0_MME_ACC_STM_BASE 0x6101000ull
+#define DCORE0_MME_ACC_STM_MAX_OFFSET 0x1000
+#define DCORE0_MME_ACC_STM_SECTION 0x1000
+#define mmDCORE0_MME_ACC_CTI_BASE 0x6102000ull
+#define DCORE0_MME_ACC_CTI_MAX_OFFSET 0x1000
+#define DCORE0_MME_ACC_CTI_SECTION 0x1000
+#define mmDCORE0_MME_ACC_ETF_BASE 0x6103000ull
+#define DCORE0_MME_ACC_ETF_MAX_OFFSET 0x1000
+#define DCORE0_MME_ACC_ETF_SECTION 0x1000
+#define mmDCORE0_MME_ACC_SPMU_BASE 0x6104000ull
+#define DCORE0_MME_ACC_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_MME_ACC_SPMU_SECTION 0x1000
+#define mmDCORE0_MME_ACC_CTI0_BASE 0x6105000ull
+#define DCORE0_MME_ACC_CTI0_MAX_OFFSET 0x1000
+#define DCORE0_MME_ACC_CTI0_SECTION 0x1000
+#define mmDCORE0_MME_ACC_CTI1_BASE 0x6106000ull
+#define DCORE0_MME_ACC_CTI1_MAX_OFFSET 0x1000
+#define DCORE0_MME_ACC_CTI1_SECTION 0x1000
+#define mmDCORE0_MME_ACC_BMON0_BASE 0x6107000ull
+#define DCORE0_MME_ACC_BMON0_MAX_OFFSET 0x1000
+#define DCORE0_MME_ACC_BMON0_SECTION 0x1000
+#define mmDCORE0_MME_ACC_BMON1_BASE 0x6108000ull
+#define DCORE0_MME_ACC_BMON1_MAX_OFFSET 0x1000
+#define DCORE0_MME_ACC_BMON1_SECTION 0x8000
+#define mmDCORE0_SM_CS_DBG_ROM_TBL_BASE 0x6110000ull
+#define DCORE0_SM_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE0_SM_CS_DBG_ROM_TBL_SECTION 0x1000
+#define mmDCORE0_SM_STM_BASE 0x6111000ull
+#define DCORE0_SM_STM_MAX_OFFSET 0x1000
+#define DCORE0_SM_STM_SECTION 0x1000
+#define mmDCORE0_SM_CTI_BASE 0x6112000ull
+#define DCORE0_SM_CTI_MAX_OFFSET 0x1000
+#define DCORE0_SM_CTI_SECTION 0x1000
+#define mmDCORE0_SM_ETF_BASE 0x6113000ull
+#define DCORE0_SM_ETF_MAX_OFFSET 0x1000
+#define DCORE0_SM_ETF_SECTION 0x1000
+#define mmDCORE0_SM_SPMU_BASE 0x6114000ull
+#define DCORE0_SM_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_SM_SPMU_SECTION 0x1000
+#define mmDCORE0_SM_BMON_CTI_BASE 0x6115000ull
+#define DCORE0_SM_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE0_SM_BMON_CTI_SECTION 0x1000
+#define mmDCORE0_SM_USER_CTI_BASE 0x6116000ull
+#define DCORE0_SM_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE0_SM_USER_CTI_SECTION 0x1000
+#define mmDCORE0_SM_BMON_BASE 0x6117000ull
+#define DCORE0_SM_BMON_MAX_OFFSET 0x1000
+#define DCORE0_SM_BMON_SECTION 0x1000
+#define mmDCORE0_SM_BMON1_BASE 0x6118000ull
+#define DCORE0_SM_BMON1_MAX_OFFSET 0x1000
+#define DCORE0_SM_BMON1_SECTION 0x18000
+#define mmDCORE0_XFT_FUNNEL_BASE 0x6130000ull
+#define DCORE0_XFT_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_XFT_FUNNEL_SECTION 0x8000
+#define mmDCORE0_TFT0_FUNNEL_BASE 0x6138000ull
+#define DCORE0_TFT0_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_TFT0_FUNNEL_SECTION 0x1000
+#define mmDCORE0_TFT1_FUNNEL_BASE 0x6139000ull
+#define DCORE0_TFT1_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_TFT1_FUNNEL_SECTION 0x1000
+#define mmDCORE0_TFT2_FUNNEL_BASE 0x613A000ull
+#define DCORE0_TFT2_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_TFT2_FUNNEL_SECTION 0x7000
+#define mmDCORE0_RTR0_FUNNEL_BASE 0x6141000ull
+#define DCORE0_RTR0_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_RTR0_FUNNEL_SECTION 0x8000
+#define mmDCORE0_RTR1_FUNNEL_BASE 0x6149000ull
+#define DCORE0_RTR1_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_RTR1_FUNNEL_SECTION 0x8000
+#define mmDCORE0_RTR2_FUNNEL_BASE 0x6151000ull
+#define DCORE0_RTR2_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_RTR2_FUNNEL_SECTION 0x8000
+#define mmDCORE0_RTR3_FUNNEL_BASE 0x6159000ull
+#define DCORE0_RTR3_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_RTR3_FUNNEL_SECTION 0x8000
+#define mmDCORE0_RTR4_FUNNEL_BASE 0x6161000ull
+#define DCORE0_RTR4_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_RTR4_FUNNEL_SECTION 0x4000
+#define mmDCORE0_MIF0_FUNNEL_BASE 0x6165000ull
+#define DCORE0_MIF0_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_MIF0_FUNNEL_SECTION 0x4000
+#define mmDCORE0_RTR5_FUNNEL_BASE 0x6169000ull
+#define DCORE0_RTR5_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_RTR5_FUNNEL_SECTION 0x4000
+#define mmDCORE0_MIF1_FUNNEL_BASE 0x616D000ull
+#define DCORE0_MIF1_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_MIF1_FUNNEL_SECTION 0x4000
+#define mmDCORE0_RTR6_FUNNEL_BASE 0x6171000ull
+#define DCORE0_RTR6_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_RTR6_FUNNEL_SECTION 0x4000
+#define mmDCORE0_MIF2_FUNNEL_BASE 0x6175000ull
+#define DCORE0_MIF2_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_MIF2_FUNNEL_SECTION 0x4000
+#define mmDCORE0_RTR7_FUNNEL_BASE 0x6179000ull
+#define DCORE0_RTR7_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_RTR7_FUNNEL_SECTION 0x4000
+#define mmDCORE0_MIF3_FUNNEL_BASE 0x617D000ull
+#define DCORE0_MIF3_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_MIF3_FUNNEL_SECTION 0x43000
+#define mmDCORE0_EDMA0_CS_ROM_TBL_BASE 0x61C0000ull
+#define DCORE0_EDMA0_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE0_EDMA0_CS_ROM_TBL_SECTION 0x1000
+#define mmDCORE0_EDMA0_CS_STM_BASE 0x61C1000ull
+#define DCORE0_EDMA0_CS_STM_MAX_OFFSET 0x1000
+#define DCORE0_EDMA0_CS_STM_SECTION 0x1000
+#define mmDCORE0_EDMA0_CS_CTI_BASE 0x61C2000ull
+#define DCORE0_EDMA0_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE0_EDMA0_CS_CTI_SECTION 0x1000
+#define mmDCORE0_EDMA0_CS_ETF_BASE 0x61C3000ull
+#define DCORE0_EDMA0_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE0_EDMA0_CS_ETF_SECTION 0x1000
+#define mmDCORE0_EDMA0_CS_SPMU_BASE 0x61C4000ull
+#define DCORE0_EDMA0_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_EDMA0_CS_SPMU_SECTION 0x1000
+#define mmDCORE0_EDMA0_BMON_CTI_BASE 0x61C5000ull
+#define DCORE0_EDMA0_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE0_EDMA0_BMON_CTI_SECTION 0x1000
+#define mmDCORE0_EDMA0_USER_CTI_BASE 0x61C6000ull
+#define DCORE0_EDMA0_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE0_EDMA0_USER_CTI_SECTION 0x1000
+#define mmDCORE0_EDMA0_BMON_0_BASE 0x61C7000ull
+#define DCORE0_EDMA0_BMON_0_MAX_OFFSET 0x1000
+#define DCORE0_EDMA0_BMON_0_SECTION 0x1000
+#define mmDCORE0_EDMA0_BMON_1_BASE 0x61C8000ull
+#define DCORE0_EDMA0_BMON_1_MAX_OFFSET 0x1000
+#define DCORE0_EDMA0_BMON_1_SECTION 0x1000
+#define mmDCORE0_EDMA0_QM_ARC_RTT_BASE 0x61C9000ull
+#define DCORE0_EDMA0_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE0_EDMA0_QM_ARC_RTT_SECTION 0x7000
+#define mmDCORE0_EDMA1_CS_ROM_TBL_BASE 0x61D0000ull
+#define DCORE0_EDMA1_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE0_EDMA1_CS_ROM_TBL_SECTION 0x1000
+#define mmDCORE0_EDMA1_CS_STM_BASE 0x61D1000ull
+#define DCORE0_EDMA1_CS_STM_MAX_OFFSET 0x1000
+#define DCORE0_EDMA1_CS_STM_SECTION 0x1000
+#define mmDCORE0_EDMA1_CS_CTI_BASE 0x61D2000ull
+#define DCORE0_EDMA1_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE0_EDMA1_CS_CTI_SECTION 0x1000
+#define mmDCORE0_EDMA1_CS_ETF_BASE 0x61D3000ull
+#define DCORE0_EDMA1_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE0_EDMA1_CS_ETF_SECTION 0x1000
+#define mmDCORE0_EDMA1_CS_SPMU_BASE 0x61D4000ull
+#define DCORE0_EDMA1_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_EDMA1_CS_SPMU_SECTION 0x1000
+#define mmDCORE0_EDMA1_BMON_CTI_BASE 0x61D5000ull
+#define DCORE0_EDMA1_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE0_EDMA1_BMON_CTI_SECTION 0x1000
+#define mmDCORE0_EDMA1_USER_CTI_BASE 0x61D6000ull
+#define DCORE0_EDMA1_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE0_EDMA1_USER_CTI_SECTION 0x1000
+#define mmDCORE0_EDMA1_BMON_0_BASE 0x61D7000ull
+#define DCORE0_EDMA1_BMON_0_MAX_OFFSET 0x1000
+#define DCORE0_EDMA1_BMON_0_SECTION 0x1000
+#define mmDCORE0_EDMA1_BMON_1_BASE 0x61D8000ull
+#define DCORE0_EDMA1_BMON_1_MAX_OFFSET 0x1000
+#define DCORE0_EDMA1_BMON_1_SECTION 0x1000
+#define mmDCORE0_EDMA1_QM_ARC_RTT_BASE 0x61D9000ull
+#define DCORE0_EDMA1_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE0_EDMA1_QM_ARC_RTT_SECTION 0x7000
+#define mmDCORE0_VDEC0_CS_ROM_TBL_BASE 0x61E0000ull
+#define DCORE0_VDEC0_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE0_VDEC0_CS_ROM_TBL_SECTION 0x1000
+#define mmDCORE0_VDEC0_CS_STM_BASE 0x61E1000ull
+#define DCORE0_VDEC0_CS_STM_MAX_OFFSET 0x1000
+#define DCORE0_VDEC0_CS_STM_SECTION 0x1000
+#define mmDCORE0_VDEC0_CS_CTI_BASE 0x61E2000ull
+#define DCORE0_VDEC0_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE0_VDEC0_CS_CTI_SECTION 0x1000
+#define mmDCORE0_VDEC0_CS_ETF_BASE 0x61E3000ull
+#define DCORE0_VDEC0_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE0_VDEC0_CS_ETF_SECTION 0x1000
+#define mmDCORE0_VDEC0_CS_SPMU_BASE 0x61E4000ull
+#define DCORE0_VDEC0_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_VDEC0_CS_SPMU_SECTION 0x1000
+#define mmDCORE0_VDEC0_BMON_CTI_BASE 0x61E5000ull
+#define DCORE0_VDEC0_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE0_VDEC0_BMON_CTI_SECTION 0x1000
+#define mmDCORE0_VDEC0_USER_CTI_BASE 0x61E6000ull
+#define DCORE0_VDEC0_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE0_VDEC0_USER_CTI_SECTION 0x1000
+#define mmDCORE0_VDEC0_BMON_0_BASE 0x61E7000ull
+#define DCORE0_VDEC0_BMON_0_MAX_OFFSET 0x1000
+#define DCORE0_VDEC0_BMON_0_SECTION 0x1000
+#define mmDCORE0_VDEC0_BMON_1_BASE 0x61E8000ull
+#define DCORE0_VDEC0_BMON_1_MAX_OFFSET 0x1000
+#define DCORE0_VDEC0_BMON_1_SECTION 0x1000
+#define mmDCORE0_VDEC0_BMON_2_BASE 0x61E9000ull
+#define DCORE0_VDEC0_BMON_2_MAX_OFFSET 0x1000
+#define DCORE0_VDEC0_BMON_2_SECTION 0x7000
+#define mmDCORE0_VDEC1_CS_ROM_TBL_BASE 0x61F0000ull
+#define DCORE0_VDEC1_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE0_VDEC1_CS_ROM_TBL_SECTION 0x1000
+#define mmDCORE0_VDEC1_CS_STM_BASE 0x61F1000ull
+#define DCORE0_VDEC1_CS_STM_MAX_OFFSET 0x1000
+#define DCORE0_VDEC1_CS_STM_SECTION 0x1000
+#define mmDCORE0_VDEC1_CS_CTI_BASE 0x61F2000ull
+#define DCORE0_VDEC1_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE0_VDEC1_CS_CTI_SECTION 0x1000
+#define mmDCORE0_VDEC1_CS_ETF_BASE 0x61F3000ull
+#define DCORE0_VDEC1_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE0_VDEC1_CS_ETF_SECTION 0x1000
+#define mmDCORE0_VDEC1_CS_SPMU_BASE 0x61F4000ull
+#define DCORE0_VDEC1_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE0_VDEC1_CS_SPMU_SECTION 0x1000
+#define mmDCORE0_VDEC1_BMON_CTI_BASE 0x61F5000ull
+#define DCORE0_VDEC1_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE0_VDEC1_BMON_CTI_SECTION 0x1000
+#define mmDCORE0_VDEC1_USER_CTI_BASE 0x61F6000ull
+#define DCORE0_VDEC1_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE0_VDEC1_USER_CTI_SECTION 0x1000
+#define mmDCORE0_VDEC1_BMON_0_BASE 0x61F7000ull
+#define DCORE0_VDEC1_BMON_0_MAX_OFFSET 0x1000
+#define DCORE0_VDEC1_BMON_0_SECTION 0x1000
+#define mmDCORE0_VDEC1_BMON_1_BASE 0x61F8000ull
+#define DCORE0_VDEC1_BMON_1_MAX_OFFSET 0x1000
+#define DCORE0_VDEC1_BMON_1_SECTION 0x1000
+#define mmDCORE0_VDEC1_BMON_2_BASE 0x61F9000ull
+#define DCORE0_VDEC1_BMON_2_MAX_OFFSET 0x1000
+#define DCORE0_VDEC1_BMON_2_SECTION 0x7000
+#define mmDCORE1_ROM_TABLE_L_BASE 0x6200000ull
+#define DCORE1_ROM_TABLE_L_MAX_OFFSET 0x1000
+#define DCORE1_ROM_TABLE_L_SECTION 0x80000
+#define mmDCORE1_HMMU0_CS_ROM_TBL_BASE 0x6280000ull
+#define DCORE1_HMMU0_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE1_HMMU0_CS_ROM_TBL_SECTION 0x1000
+#define mmDCORE1_HMMU0_CS_STM_BASE 0x6281000ull
+#define DCORE1_HMMU0_CS_STM_MAX_OFFSET 0x1000
+#define DCORE1_HMMU0_CS_STM_SECTION 0x1000
+#define mmDCORE1_HMMU0_CS_CTI_BASE 0x6282000ull
+#define DCORE1_HMMU0_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE1_HMMU0_CS_CTI_SECTION 0x1000
+#define mmDCORE1_HMMU0_CS_ETF_BASE 0x6283000ull
+#define DCORE1_HMMU0_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE1_HMMU0_CS_ETF_SECTION 0x1000
+#define mmDCORE1_HMMU0_CS_SPMU_BASE 0x6284000ull
+#define DCORE1_HMMU0_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_HMMU0_CS_SPMU_SECTION 0x1000
+#define mmDCORE1_HMMU0_BMON_CTI_BASE 0x6285000ull
+#define DCORE1_HMMU0_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE1_HMMU0_BMON_CTI_SECTION 0x1000
+#define mmDCORE1_HMMU0_USER_CTI_BASE 0x6286000ull
+#define DCORE1_HMMU0_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE1_HMMU0_USER_CTI_SECTION 0x1000
+#define mmDCORE1_HMMU0_BMON_0_BASE 0x6287000ull
+#define DCORE1_HMMU0_BMON_0_MAX_OFFSET 0x1000
+#define DCORE1_HMMU0_BMON_0_SECTION 0x1000
+#define mmDCORE1_HMMU0_BMON_1_BASE 0x6288000ull
+#define DCORE1_HMMU0_BMON_1_MAX_OFFSET 0x1000
+#define DCORE1_HMMU0_BMON_1_SECTION 0x1000
+#define mmDCORE1_HMMU0_BMON_3_BASE 0x6289000ull
+#define DCORE1_HMMU0_BMON_3_MAX_OFFSET 0x1000
+#define DCORE1_HMMU0_BMON_3_SECTION 0x1000
+#define mmDCORE1_HMMU0_BMON_2_BASE 0x628A000ull
+#define DCORE1_HMMU0_BMON_2_MAX_OFFSET 0x1000
+#define DCORE1_HMMU0_BMON_2_SECTION 0x1000
+#define mmDCORE1_HMMU0_BMON_4_BASE 0x628B000ull
+#define DCORE1_HMMU0_BMON_4_MAX_OFFSET 0x1000
+#define DCORE1_HMMU0_BMON_4_SECTION 0x5000
+#define mmDCORE1_HMMU1_CS_ROM_TBL_BASE 0x6290000ull
+#define DCORE1_HMMU1_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE1_HMMU1_CS_ROM_TBL_SECTION 0x1000
+#define mmDCORE1_HMMU1_CS_STM_BASE 0x6291000ull
+#define DCORE1_HMMU1_CS_STM_MAX_OFFSET 0x1000
+#define DCORE1_HMMU1_CS_STM_SECTION 0x1000
+#define mmDCORE1_HMMU1_CS_CTI_BASE 0x6292000ull
+#define DCORE1_HMMU1_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE1_HMMU1_CS_CTI_SECTION 0x1000
+#define mmDCORE1_HMMU1_CS_ETF_BASE 0x6293000ull
+#define DCORE1_HMMU1_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE1_HMMU1_CS_ETF_SECTION 0x1000
+#define mmDCORE1_HMMU1_CS_SPMU_BASE 0x6294000ull
+#define DCORE1_HMMU1_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_HMMU1_CS_SPMU_SECTION 0x1000
+#define mmDCORE1_HMMU1_BMON_CTI_BASE 0x6295000ull
+#define DCORE1_HMMU1_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE1_HMMU1_BMON_CTI_SECTION 0x1000
+#define mmDCORE1_HMMU1_USER_CTI_BASE 0x6296000ull
+#define DCORE1_HMMU1_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE1_HMMU1_USER_CTI_SECTION 0x1000
+#define mmDCORE1_HMMU1_BMON_0_BASE 0x6297000ull
+#define DCORE1_HMMU1_BMON_0_MAX_OFFSET 0x1000
+#define DCORE1_HMMU1_BMON_0_SECTION 0x1000
+#define mmDCORE1_HMMU1_BMON_1_BASE 0x6298000ull
+#define DCORE1_HMMU1_BMON_1_MAX_OFFSET 0x1000
+#define DCORE1_HMMU1_BMON_1_SECTION 0x1000
+#define mmDCORE1_HMMU1_BMON_3_BASE 0x6299000ull
+#define DCORE1_HMMU1_BMON_3_MAX_OFFSET 0x1000
+#define DCORE1_HMMU1_BMON_3_SECTION 0x1000
+#define mmDCORE1_HMMU1_BMON_2_BASE 0x629A000ull
+#define DCORE1_HMMU1_BMON_2_MAX_OFFSET 0x1000
+#define DCORE1_HMMU1_BMON_2_SECTION 0x1000
+#define mmDCORE1_HMMU1_BMON_4_BASE 0x629B000ull
+#define DCORE1_HMMU1_BMON_4_MAX_OFFSET 0x1000
+#define DCORE1_HMMU1_BMON_4_SECTION 0x5000
+#define mmDCORE1_HMMU2_CS_ROM_TBL_BASE 0x62A0000ull
+#define DCORE1_HMMU2_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE1_HMMU2_CS_ROM_TBL_SECTION 0x1000
+#define mmDCORE1_HMMU2_CS_STM_BASE 0x62A1000ull
+#define DCORE1_HMMU2_CS_STM_MAX_OFFSET 0x1000
+#define DCORE1_HMMU2_CS_STM_SECTION 0x1000
+#define mmDCORE1_HMMU2_CS_CTI_BASE 0x62A2000ull
+#define DCORE1_HMMU2_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE1_HMMU2_CS_CTI_SECTION 0x1000
+#define mmDCORE1_HMMU2_CS_ETF_BASE 0x62A3000ull
+#define DCORE1_HMMU2_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE1_HMMU2_CS_ETF_SECTION 0x1000
+#define mmDCORE1_HMMU2_CS_SPMU_BASE 0x62A4000ull
+#define DCORE1_HMMU2_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_HMMU2_CS_SPMU_SECTION 0x1000
+#define mmDCORE1_HMMU2_BMON_CTI_BASE 0x62A5000ull
+#define DCORE1_HMMU2_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE1_HMMU2_BMON_CTI_SECTION 0x1000
+#define mmDCORE1_HMMU2_USER_CTI_BASE 0x62A6000ull
+#define DCORE1_HMMU2_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE1_HMMU2_USER_CTI_SECTION 0x1000
+#define mmDCORE1_HMMU2_BMON_0_BASE 0x62A7000ull
+#define DCORE1_HMMU2_BMON_0_MAX_OFFSET 0x1000
+#define DCORE1_HMMU2_BMON_0_SECTION 0x1000
+#define mmDCORE1_HMMU2_BMON_1_BASE 0x62A8000ull
+#define DCORE1_HMMU2_BMON_1_MAX_OFFSET 0x1000
+#define DCORE1_HMMU2_BMON_1_SECTION 0x1000
+#define mmDCORE1_HMMU2_BMON_3_BASE 0x62A9000ull
+#define DCORE1_HMMU2_BMON_3_MAX_OFFSET 0x1000
+#define DCORE1_HMMU2_BMON_3_SECTION 0x1000
+#define mmDCORE1_HMMU2_BMON_2_BASE 0x62AA000ull
+#define DCORE1_HMMU2_BMON_2_MAX_OFFSET 0x1000
+#define DCORE1_HMMU2_BMON_2_SECTION 0x1000
+#define mmDCORE1_HMMU2_BMON_4_BASE 0x62AB000ull
+#define DCORE1_HMMU2_BMON_4_MAX_OFFSET 0x1000
+#define DCORE1_HMMU2_BMON_4_SECTION 0x5000
+#define mmDCORE1_HMMU3_CS_ROM_TBL_BASE 0x62B0000ull
+#define DCORE1_HMMU3_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE1_HMMU3_CS_ROM_TBL_SECTION 0x1000
+#define mmDCORE1_HMMU3_CS_STM_BASE 0x62B1000ull
+#define DCORE1_HMMU3_CS_STM_MAX_OFFSET 0x1000
+#define DCORE1_HMMU3_CS_STM_SECTION 0x1000
+#define mmDCORE1_HMMU3_CS_CTI_BASE 0x62B2000ull
+#define DCORE1_HMMU3_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE1_HMMU3_CS_CTI_SECTION 0x1000
+#define mmDCORE1_HMMU3_CS_ETF_BASE 0x62B3000ull
+#define DCORE1_HMMU3_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE1_HMMU3_CS_ETF_SECTION 0x1000
+#define mmDCORE1_HMMU3_CS_SPMU_BASE 0x62B4000ull
+#define DCORE1_HMMU3_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_HMMU3_CS_SPMU_SECTION 0x1000
+#define mmDCORE1_HMMU3_BMON_CTI_BASE 0x62B5000ull
+#define DCORE1_HMMU3_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE1_HMMU3_BMON_CTI_SECTION 0x1000
+#define mmDCORE1_HMMU3_USER_CTI_BASE 0x62B6000ull
+#define DCORE1_HMMU3_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE1_HMMU3_USER_CTI_SECTION 0x1000
+#define mmDCORE1_HMMU3_BMON_0_BASE 0x62B7000ull
+#define DCORE1_HMMU3_BMON_0_MAX_OFFSET 0x1000
+#define DCORE1_HMMU3_BMON_0_SECTION 0x1000
+#define mmDCORE1_HMMU3_BMON_1_BASE 0x62B8000ull
+#define DCORE1_HMMU3_BMON_1_MAX_OFFSET 0x1000
+#define DCORE1_HMMU3_BMON_1_SECTION 0x1000
+#define mmDCORE1_HMMU3_BMON_3_BASE 0x62B9000ull
+#define DCORE1_HMMU3_BMON_3_MAX_OFFSET 0x1000
+#define DCORE1_HMMU3_BMON_3_SECTION 0x1000
+#define mmDCORE1_HMMU3_BMON_2_BASE 0x62BA000ull
+#define DCORE1_HMMU3_BMON_2_MAX_OFFSET 0x1000
+#define DCORE1_HMMU3_BMON_2_SECTION 0x1000
+#define mmDCORE1_HMMU3_BMON_4_BASE 0x62BB000ull
+#define DCORE1_HMMU3_BMON_4_MAX_OFFSET 0x1000
+#define DCORE1_HMMU3_BMON_4_SECTION 0x5000
+#define mmDCORE1_MME_CTRL_ROM_TABLE_BASE 0x62C0000ull
+#define DCORE1_MME_CTRL_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE1_MME_CTRL_ROM_TABLE_SECTION 0x1000
+#define mmDCORE1_MME_CTRL_STM_BASE 0x62C1000ull
+#define DCORE1_MME_CTRL_STM_MAX_OFFSET 0x1000
+#define DCORE1_MME_CTRL_STM_SECTION 0x1000
+#define mmDCORE1_MME_CTRL_CTI_BASE 0x62C2000ull
+#define DCORE1_MME_CTRL_CTI_MAX_OFFSET 0x1000
+#define DCORE1_MME_CTRL_CTI_SECTION 0x1000
+#define mmDCORE1_MME_CTRL_ETF_BASE 0x62C3000ull
+#define DCORE1_MME_CTRL_ETF_MAX_OFFSET 0x1000
+#define DCORE1_MME_CTRL_ETF_SECTION 0x1000
+#define mmDCORE1_MME_CTRL_SPMU_BASE 0x62C4000ull
+#define DCORE1_MME_CTRL_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_MME_CTRL_SPMU_SECTION 0x1000
+#define mmDCORE1_MME_CTRL_CTI0_BASE 0x62C5000ull
+#define DCORE1_MME_CTRL_CTI0_MAX_OFFSET 0x1000
+#define DCORE1_MME_CTRL_CTI0_SECTION 0x1000
+#define mmDCORE1_MME_CTRL_CTI1_BASE 0x62C6000ull
+#define DCORE1_MME_CTRL_CTI1_MAX_OFFSET 0x1000
+#define DCORE1_MME_CTRL_CTI1_SECTION 0x1000
+#define mmDCORE1_MME_CTRL_BMON0_BASE 0x62C7000ull
+#define DCORE1_MME_CTRL_BMON0_MAX_OFFSET 0x1000
+#define DCORE1_MME_CTRL_BMON0_SECTION 0x1000
+#define mmDCORE1_MME_CTRL_BMON1_BASE 0x62C8000ull
+#define DCORE1_MME_CTRL_BMON1_MAX_OFFSET 0x1000
+#define DCORE1_MME_CTRL_BMON1_SECTION 0x1000
+#define mmDCORE1_MME_CTRL_BMON2_BASE 0x62C9000ull
+#define DCORE1_MME_CTRL_BMON2_MAX_OFFSET 0x1000
+#define DCORE1_MME_CTRL_BMON2_SECTION 0x1000
+#define mmDCORE1_MME_CTRL_BMON3_BASE 0x62CA000ull
+#define DCORE1_MME_CTRL_BMON3_MAX_OFFSET 0x1000
+#define DCORE1_MME_CTRL_BMON3_SECTION 0x1000
+#define mmDCORE1_MME_CTRL_ARC_RTT_BASE 0x62CB000ull
+#define DCORE1_MME_CTRL_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE1_MME_CTRL_ARC_RTT_SECTION 0x5000
+#define mmDCORE1_MME_SBTE0_ROM_TBL_BASE 0x62D0000ull
+#define DCORE1_MME_SBTE0_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE0_ROM_TBL_SECTION 0x1000
+#define mmDCORE1_MME_SBTE0_STM_BASE 0x62D1000ull
+#define DCORE1_MME_SBTE0_STM_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE0_STM_SECTION 0x1000
+#define mmDCORE1_MME_SBTE0_CTI_BASE 0x62D2000ull
+#define DCORE1_MME_SBTE0_CTI_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE0_CTI_SECTION 0x1000
+#define mmDCORE1_MME_SBTE0_ETF_BASE 0x62D3000ull
+#define DCORE1_MME_SBTE0_ETF_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE0_ETF_SECTION 0x1000
+#define mmDCORE1_MME_SBTE0_SPMU_BASE 0x62D4000ull
+#define DCORE1_MME_SBTE0_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE0_SPMU_SECTION 0x1000
+#define mmDCORE1_MME_SBTE0_CTI0_BASE 0x62D5000ull
+#define DCORE1_MME_SBTE0_CTI0_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE0_CTI0_SECTION 0x1000
+#define mmDCORE1_MME_SBTE0_CTI1_BASE 0x62D6000ull
+#define DCORE1_MME_SBTE0_CTI1_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE0_CTI1_SECTION 0x1000
+#define mmDCORE1_MME_SBTE0_BMON0_BASE 0x62D7000ull
+#define DCORE1_MME_SBTE0_BMON0_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE0_BMON0_SECTION 0x1000
+#define mmDCORE1_MME_SBTE1_ROM_TBL_BASE 0x62D8000ull
+#define DCORE1_MME_SBTE1_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE1_ROM_TBL_SECTION 0x1000
+#define mmDCORE1_MME_SBTE1_STM_BASE 0x62D9000ull
+#define DCORE1_MME_SBTE1_STM_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE1_STM_SECTION 0x1000
+#define mmDCORE1_MME_SBTE1_CTI_BASE 0x62DA000ull
+#define DCORE1_MME_SBTE1_CTI_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE1_CTI_SECTION 0x1000
+#define mmDCORE1_MME_SBTE1_ETF_BASE 0x62DB000ull
+#define DCORE1_MME_SBTE1_ETF_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE1_ETF_SECTION 0x1000
+#define mmDCORE1_MME_SBTE1_SPMU_BASE 0x62DC000ull
+#define DCORE1_MME_SBTE1_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE1_SPMU_SECTION 0x1000
+#define mmDCORE1_MME_SBTE1_CTI0_BASE 0x62DD000ull
+#define DCORE1_MME_SBTE1_CTI0_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE1_CTI0_SECTION 0x1000
+#define mmDCORE1_MME_SBTE1_CTI1_BASE 0x62DE000ull
+#define DCORE1_MME_SBTE1_CTI1_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE1_CTI1_SECTION 0x1000
+#define mmDCORE1_MME_SBTE1_BMON0_BASE 0x62DF000ull
+#define DCORE1_MME_SBTE1_BMON0_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE1_BMON0_SECTION 0x1000
+#define mmDCORE1_MME_SBTE2_ROM_TBL_BASE 0x62E0000ull
+#define DCORE1_MME_SBTE2_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE2_ROM_TBL_SECTION 0x1000
+#define mmDCORE1_MME_SBTE2_STM_BASE 0x62E1000ull
+#define DCORE1_MME_SBTE2_STM_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE2_STM_SECTION 0x1000
+#define mmDCORE1_MME_SBTE2_CTI_BASE 0x62E2000ull
+#define DCORE1_MME_SBTE2_CTI_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE2_CTI_SECTION 0x1000
+#define mmDCORE1_MME_SBTE2_ETF_BASE 0x62E3000ull
+#define DCORE1_MME_SBTE2_ETF_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE2_ETF_SECTION 0x1000
+#define mmDCORE1_MME_SBTE2_SPMU_BASE 0x62E4000ull
+#define DCORE1_MME_SBTE2_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE2_SPMU_SECTION 0x1000
+#define mmDCORE1_MME_SBTE2_CTI0_BASE 0x62E5000ull
+#define DCORE1_MME_SBTE2_CTI0_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE2_CTI0_SECTION 0x1000
+#define mmDCORE1_MME_SBTE2_CTI1_BASE 0x62E6000ull
+#define DCORE1_MME_SBTE2_CTI1_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE2_CTI1_SECTION 0x1000
+#define mmDCORE1_MME_SBTE2_BMON0_BASE 0x62E7000ull
+#define DCORE1_MME_SBTE2_BMON0_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE2_BMON0_SECTION 0x1000
+#define mmDCORE1_MME_SBTE3_ROM_TBL_BASE 0x62E8000ull
+#define DCORE1_MME_SBTE3_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE3_ROM_TBL_SECTION 0x1000
+#define mmDCORE1_MME_SBTE3_STM_BASE 0x62E9000ull
+#define DCORE1_MME_SBTE3_STM_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE3_STM_SECTION 0x1000
+#define mmDCORE1_MME_SBTE3_CTI_BASE 0x62EA000ull
+#define DCORE1_MME_SBTE3_CTI_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE3_CTI_SECTION 0x1000
+#define mmDCORE1_MME_SBTE3_ETF_BASE 0x62EB000ull
+#define DCORE1_MME_SBTE3_ETF_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE3_ETF_SECTION 0x1000
+#define mmDCORE1_MME_SBTE3_SPMU_BASE 0x62EC000ull
+#define DCORE1_MME_SBTE3_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE3_SPMU_SECTION 0x1000
+#define mmDCORE1_MME_SBTE3_CTI0_BASE 0x62ED000ull
+#define DCORE1_MME_SBTE3_CTI0_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE3_CTI0_SECTION 0x1000
+#define mmDCORE1_MME_SBTE3_CTI1_BASE 0x62EE000ull
+#define DCORE1_MME_SBTE3_CTI1_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE3_CTI1_SECTION 0x1000
+#define mmDCORE1_MME_SBTE3_BMON0_BASE 0x62EF000ull
+#define DCORE1_MME_SBTE3_BMON0_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE3_BMON0_SECTION 0x1000
+#define mmDCORE1_MME_SBTE4_ROM_TBL_BASE 0x62F0000ull
+#define DCORE1_MME_SBTE4_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE4_ROM_TBL_SECTION 0x1000
+#define mmDCORE1_MME_SBTE4_STM_BASE 0x62F1000ull
+#define DCORE1_MME_SBTE4_STM_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE4_STM_SECTION 0x1000
+#define mmDCORE1_MME_SBTE4_CTI_BASE 0x62F2000ull
+#define DCORE1_MME_SBTE4_CTI_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE4_CTI_SECTION 0x1000
+#define mmDCORE1_MME_SBTE4_ETF_BASE 0x62F3000ull
+#define DCORE1_MME_SBTE4_ETF_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE4_ETF_SECTION 0x1000
+#define mmDCORE1_MME_SBTE4_SPMU_BASE 0x62F4000ull
+#define DCORE1_MME_SBTE4_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE4_SPMU_SECTION 0x1000
+#define mmDCORE1_MME_SBTE4_CTI0_BASE 0x62F5000ull
+#define DCORE1_MME_SBTE4_CTI0_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE4_CTI0_SECTION 0x1000
+#define mmDCORE1_MME_SBTE4_CTI1_BASE 0x62F6000ull
+#define DCORE1_MME_SBTE4_CTI1_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE4_CTI1_SECTION 0x1000
+#define mmDCORE1_MME_SBTE4_BMON0_BASE 0x62F7000ull
+#define DCORE1_MME_SBTE4_BMON0_MAX_OFFSET 0x1000
+#define DCORE1_MME_SBTE4_BMON0_SECTION 0x9000
+#define mmDCORE1_MME_ACC_CS_ROM_TBL_BASE 0x6300000ull
+#define DCORE1_MME_ACC_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE1_MME_ACC_CS_ROM_TBL_SECTION 0x1000
+#define mmDCORE1_MME_ACC_STM_BASE 0x6301000ull
+#define DCORE1_MME_ACC_STM_MAX_OFFSET 0x1000
+#define DCORE1_MME_ACC_STM_SECTION 0x1000
+#define mmDCORE1_MME_ACC_CTI_BASE 0x6302000ull
+#define DCORE1_MME_ACC_CTI_MAX_OFFSET 0x1000
+#define DCORE1_MME_ACC_CTI_SECTION 0x1000
+#define mmDCORE1_MME_ACC_ETF_BASE 0x6303000ull
+#define DCORE1_MME_ACC_ETF_MAX_OFFSET 0x1000
+#define DCORE1_MME_ACC_ETF_SECTION 0x1000
+#define mmDCORE1_MME_ACC_SPMU_BASE 0x6304000ull
+#define DCORE1_MME_ACC_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_MME_ACC_SPMU_SECTION 0x1000
+#define mmDCORE1_MME_ACC_CTI0_BASE 0x6305000ull
+#define DCORE1_MME_ACC_CTI0_MAX_OFFSET 0x1000
+#define DCORE1_MME_ACC_CTI0_SECTION 0x1000
+#define mmDCORE1_MME_ACC_CTI1_BASE 0x6306000ull
+#define DCORE1_MME_ACC_CTI1_MAX_OFFSET 0x1000
+#define DCORE1_MME_ACC_CTI1_SECTION 0x1000
+#define mmDCORE1_MME_ACC_BMON0_BASE 0x6307000ull
+#define DCORE1_MME_ACC_BMON0_MAX_OFFSET 0x1000
+#define DCORE1_MME_ACC_BMON0_SECTION 0x1000
+#define mmDCORE1_MME_ACC_BMON1_BASE 0x6308000ull
+#define DCORE1_MME_ACC_BMON1_MAX_OFFSET 0x1000
+#define DCORE1_MME_ACC_BMON1_SECTION 0x8000
+#define mmDCORE1_SM_CS_DBG_ROM_TBL_BASE 0x6310000ull
+#define DCORE1_SM_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE1_SM_CS_DBG_ROM_TBL_SECTION 0x1000
+#define mmDCORE1_SM_STM_BASE 0x6311000ull
+#define DCORE1_SM_STM_MAX_OFFSET 0x1000
+#define DCORE1_SM_STM_SECTION 0x1000
+#define mmDCORE1_SM_CTI_BASE 0x6312000ull
+#define DCORE1_SM_CTI_MAX_OFFSET 0x1000
+#define DCORE1_SM_CTI_SECTION 0x1000
+#define mmDCORE1_SM_ETF_BASE 0x6313000ull
+#define DCORE1_SM_ETF_MAX_OFFSET 0x1000
+#define DCORE1_SM_ETF_SECTION 0x1000
+#define mmDCORE1_SM_SPMU_BASE 0x6314000ull
+#define DCORE1_SM_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_SM_SPMU_SECTION 0x1000
+#define mmDCORE1_SM_BMON_CTI_BASE 0x6315000ull
+#define DCORE1_SM_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE1_SM_BMON_CTI_SECTION 0x1000
+#define mmDCORE1_SM_USER_CTI_BASE 0x6316000ull
+#define DCORE1_SM_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE1_SM_USER_CTI_SECTION 0x1000
+#define mmDCORE1_SM_BMON_BASE 0x6317000ull
+#define DCORE1_SM_BMON_MAX_OFFSET 0x1000
+#define DCORE1_SM_BMON_SECTION 0x1000
+#define mmDCORE1_SM_BMON1_BASE 0x6318000ull
+#define DCORE1_SM_BMON1_MAX_OFFSET 0x1000
+#define DCORE1_SM_BMON1_SECTION 0x18000
+#define mmDCORE1_XFT_FUNNEL_BASE 0x6330000ull
+#define DCORE1_XFT_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_XFT_FUNNEL_SECTION 0x8000
+#define mmDCORE1_TFT0_FUNNEL_BASE 0x6338000ull
+#define DCORE1_TFT0_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_TFT0_FUNNEL_SECTION 0x1000
+#define mmDCORE1_TFT1_FUNNEL_BASE 0x6339000ull
+#define DCORE1_TFT1_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_TFT1_FUNNEL_SECTION 0x1000
+#define mmDCORE1_TFT2_FUNNEL_BASE 0x633A000ull
+#define DCORE1_TFT2_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_TFT2_FUNNEL_SECTION 0x7000
+#define mmDCORE1_RTR0_FUNNEL_BASE 0x6341000ull
+#define DCORE1_RTR0_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_RTR0_FUNNEL_SECTION 0x4000
+#define mmDCORE1_MIF0_FUNNEL_BASE 0x6345000ull
+#define DCORE1_MIF0_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_MIF0_FUNNEL_SECTION 0x4000
+#define mmDCORE1_RTR1_FUNNEL_BASE 0x6349000ull
+#define DCORE1_RTR1_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_RTR1_FUNNEL_SECTION 0x4000
+#define mmDCORE1_MIF1_FUNNEL_BASE 0x634D000ull
+#define DCORE1_MIF1_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_MIF1_FUNNEL_SECTION 0x4000
+#define mmDCORE1_RTR2_FUNNEL_BASE 0x6351000ull
+#define DCORE1_RTR2_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_RTR2_FUNNEL_SECTION 0x4000
+#define mmDCORE1_MIF2_FUNNEL_BASE 0x6355000ull
+#define DCORE1_MIF2_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_MIF2_FUNNEL_SECTION 0x4000
+#define mmDCORE1_RTR3_FUNNEL_BASE 0x6359000ull
+#define DCORE1_RTR3_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_RTR3_FUNNEL_SECTION 0x4000
+#define mmDCORE1_MIF3_FUNNEL_BASE 0x635D000ull
+#define DCORE1_MIF3_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_MIF3_FUNNEL_SECTION 0x4000
+#define mmDCORE1_RTR4_FUNNEL_BASE 0x6361000ull
+#define DCORE1_RTR4_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_RTR4_FUNNEL_SECTION 0x8000
+#define mmDCORE1_RTR5_FUNNEL_BASE 0x6369000ull
+#define DCORE1_RTR5_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_RTR5_FUNNEL_SECTION 0x8000
+#define mmDCORE1_RTR6_FUNNEL_BASE 0x6371000ull
+#define DCORE1_RTR6_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_RTR6_FUNNEL_SECTION 0x8000
+#define mmDCORE1_RTR7_FUNNEL_BASE 0x6379000ull
+#define DCORE1_RTR7_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_RTR7_FUNNEL_SECTION 0x47000
+#define mmDCORE1_EDMA0_CS_ROM_TBL_BASE 0x63C0000ull
+#define DCORE1_EDMA0_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE1_EDMA0_CS_ROM_TBL_SECTION 0x1000
+#define mmDCORE1_EDMA0_CS_STM_BASE 0x63C1000ull
+#define DCORE1_EDMA0_CS_STM_MAX_OFFSET 0x1000
+#define DCORE1_EDMA0_CS_STM_SECTION 0x1000
+#define mmDCORE1_EDMA0_CS_CTI_BASE 0x63C2000ull
+#define DCORE1_EDMA0_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE1_EDMA0_CS_CTI_SECTION 0x1000
+#define mmDCORE1_EDMA0_CS_ETF_BASE 0x63C3000ull
+#define DCORE1_EDMA0_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE1_EDMA0_CS_ETF_SECTION 0x1000
+#define mmDCORE1_EDMA0_CS_SPMU_BASE 0x63C4000ull
+#define DCORE1_EDMA0_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_EDMA0_CS_SPMU_SECTION 0x1000
+#define mmDCORE1_EDMA0_BMON_CTI_BASE 0x63C5000ull
+#define DCORE1_EDMA0_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE1_EDMA0_BMON_CTI_SECTION 0x1000
+#define mmDCORE1_EDMA0_USER_CTI_BASE 0x63C6000ull
+#define DCORE1_EDMA0_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE1_EDMA0_USER_CTI_SECTION 0x1000
+#define mmDCORE1_EDMA0_BMON_0_BASE 0x63C7000ull
+#define DCORE1_EDMA0_BMON_0_MAX_OFFSET 0x1000
+#define DCORE1_EDMA0_BMON_0_SECTION 0x1000
+#define mmDCORE1_EDMA0_BMON_1_BASE 0x63C8000ull
+#define DCORE1_EDMA0_BMON_1_MAX_OFFSET 0x1000
+#define DCORE1_EDMA0_BMON_1_SECTION 0x1000
+#define mmDCORE1_EDMA0_QM_ARC_RTT_BASE 0x63C9000ull
+#define DCORE1_EDMA0_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE1_EDMA0_QM_ARC_RTT_SECTION 0x7000
+#define mmDCORE1_EDMA1_CS_ROM_TBL_BASE 0x63D0000ull
+#define DCORE1_EDMA1_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE1_EDMA1_CS_ROM_TBL_SECTION 0x1000
+#define mmDCORE1_EDMA1_CS_STM_BASE 0x63D1000ull
+#define DCORE1_EDMA1_CS_STM_MAX_OFFSET 0x1000
+#define DCORE1_EDMA1_CS_STM_SECTION 0x1000
+#define mmDCORE1_EDMA1_CS_CTI_BASE 0x63D2000ull
+#define DCORE1_EDMA1_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE1_EDMA1_CS_CTI_SECTION 0x1000
+#define mmDCORE1_EDMA1_CS_ETF_BASE 0x63D3000ull
+#define DCORE1_EDMA1_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE1_EDMA1_CS_ETF_SECTION 0x1000
+#define mmDCORE1_EDMA1_CS_SPMU_BASE 0x63D4000ull
+#define DCORE1_EDMA1_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_EDMA1_CS_SPMU_SECTION 0x1000
+#define mmDCORE1_EDMA1_BMON_CTI_BASE 0x63D5000ull
+#define DCORE1_EDMA1_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE1_EDMA1_BMON_CTI_SECTION 0x1000
+#define mmDCORE1_EDMA1_USER_CTI_BASE 0x63D6000ull
+#define DCORE1_EDMA1_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE1_EDMA1_USER_CTI_SECTION 0x1000
+#define mmDCORE1_EDMA1_BMON_0_BASE 0x63D7000ull
+#define DCORE1_EDMA1_BMON_0_MAX_OFFSET 0x1000
+#define DCORE1_EDMA1_BMON_0_SECTION 0x1000
+#define mmDCORE1_EDMA1_BMON_1_BASE 0x63D8000ull
+#define DCORE1_EDMA1_BMON_1_MAX_OFFSET 0x1000
+#define DCORE1_EDMA1_BMON_1_SECTION 0x1000
+#define mmDCORE1_EDMA1_QM_ARC_RTT_BASE 0x63D9000ull
+#define DCORE1_EDMA1_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE1_EDMA1_QM_ARC_RTT_SECTION 0x7000
+#define mmDCORE1_VDEC0_CS_ROM_TBL_BASE 0x63E0000ull
+#define DCORE1_VDEC0_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE1_VDEC0_CS_ROM_TBL_SECTION 0x1000
+#define mmDCORE1_VDEC0_CS_STM_BASE 0x63E1000ull
+#define DCORE1_VDEC0_CS_STM_MAX_OFFSET 0x1000
+#define DCORE1_VDEC0_CS_STM_SECTION 0x1000
+#define mmDCORE1_VDEC0_CS_CTI_BASE 0x63E2000ull
+#define DCORE1_VDEC0_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE1_VDEC0_CS_CTI_SECTION 0x1000
+#define mmDCORE1_VDEC0_CS_ETF_BASE 0x63E3000ull
+#define DCORE1_VDEC0_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE1_VDEC0_CS_ETF_SECTION 0x1000
+#define mmDCORE1_VDEC0_CS_SPMU_BASE 0x63E4000ull
+#define DCORE1_VDEC0_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_VDEC0_CS_SPMU_SECTION 0x1000
+#define mmDCORE1_VDEC0_BMON_CTI_BASE 0x63E5000ull
+#define DCORE1_VDEC0_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE1_VDEC0_BMON_CTI_SECTION 0x1000
+#define mmDCORE1_VDEC0_USER_CTI_BASE 0x63E6000ull
+#define DCORE1_VDEC0_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE1_VDEC0_USER_CTI_SECTION 0x1000
+#define mmDCORE1_VDEC0_BMON_0_BASE 0x63E7000ull
+#define DCORE1_VDEC0_BMON_0_MAX_OFFSET 0x1000
+#define DCORE1_VDEC0_BMON_0_SECTION 0x1000
+#define mmDCORE1_VDEC0_BMON_1_BASE 0x63E8000ull
+#define DCORE1_VDEC0_BMON_1_MAX_OFFSET 0x1000
+#define DCORE1_VDEC0_BMON_1_SECTION 0x1000
+#define mmDCORE1_VDEC0_BMON_2_BASE 0x63E9000ull
+#define DCORE1_VDEC0_BMON_2_MAX_OFFSET 0x1000
+#define DCORE1_VDEC0_BMON_2_SECTION 0x7000
+#define mmDCORE1_VDEC1_CS_ROM_TBL_BASE 0x63F0000ull
+#define DCORE1_VDEC1_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE1_VDEC1_CS_ROM_TBL_SECTION 0x1000
+#define mmDCORE1_VDEC1_CS_STM_BASE 0x63F1000ull
+#define DCORE1_VDEC1_CS_STM_MAX_OFFSET 0x1000
+#define DCORE1_VDEC1_CS_STM_SECTION 0x1000
+#define mmDCORE1_VDEC1_CS_CTI_BASE 0x63F2000ull
+#define DCORE1_VDEC1_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE1_VDEC1_CS_CTI_SECTION 0x1000
+#define mmDCORE1_VDEC1_CS_ETF_BASE 0x63F3000ull
+#define DCORE1_VDEC1_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE1_VDEC1_CS_ETF_SECTION 0x1000
+#define mmDCORE1_VDEC1_CS_SPMU_BASE 0x63F4000ull
+#define DCORE1_VDEC1_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE1_VDEC1_CS_SPMU_SECTION 0x1000
+#define mmDCORE1_VDEC1_BMON_CTI_BASE 0x63F5000ull
+#define DCORE1_VDEC1_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE1_VDEC1_BMON_CTI_SECTION 0x1000
+#define mmDCORE1_VDEC1_USER_CTI_BASE 0x63F6000ull
+#define DCORE1_VDEC1_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE1_VDEC1_USER_CTI_SECTION 0x1000
+#define mmDCORE1_VDEC1_BMON_0_BASE 0x63F7000ull
+#define DCORE1_VDEC1_BMON_0_MAX_OFFSET 0x1000
+#define DCORE1_VDEC1_BMON_0_SECTION 0x1000
+#define mmDCORE1_VDEC1_BMON_1_BASE 0x63F8000ull
+#define DCORE1_VDEC1_BMON_1_MAX_OFFSET 0x1000
+#define DCORE1_VDEC1_BMON_1_SECTION 0x1000
+#define mmDCORE1_VDEC1_BMON_2_BASE 0x63F9000ull
+#define DCORE1_VDEC1_BMON_2_MAX_OFFSET 0x1000
+#define DCORE1_VDEC1_BMON_2_SECTION 0x7000
+#define mmDCORE2_ROM_TABLE_L_BASE 0x6400000ull
+#define DCORE2_ROM_TABLE_L_MAX_OFFSET 0x1000
+#define DCORE2_ROM_TABLE_L_SECTION 0x80000
+#define mmDCORE2_HMMU0_CS_ROM_TBL_BASE 0x6480000ull
+#define DCORE2_HMMU0_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE2_HMMU0_CS_ROM_TBL_SECTION 0x1000
+#define mmDCORE2_HMMU0_CS_STM_BASE 0x6481000ull
+#define DCORE2_HMMU0_CS_STM_MAX_OFFSET 0x1000
+#define DCORE2_HMMU0_CS_STM_SECTION 0x1000
+#define mmDCORE2_HMMU0_CS_CTI_BASE 0x6482000ull
+#define DCORE2_HMMU0_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE2_HMMU0_CS_CTI_SECTION 0x1000
+#define mmDCORE2_HMMU0_CS_ETF_BASE 0x6483000ull
+#define DCORE2_HMMU0_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE2_HMMU0_CS_ETF_SECTION 0x1000
+#define mmDCORE2_HMMU0_CS_SPMU_BASE 0x6484000ull
+#define DCORE2_HMMU0_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_HMMU0_CS_SPMU_SECTION 0x1000
+#define mmDCORE2_HMMU0_BMON_CTI_BASE 0x6485000ull
+#define DCORE2_HMMU0_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE2_HMMU0_BMON_CTI_SECTION 0x1000
+#define mmDCORE2_HMMU0_USER_CTI_BASE 0x6486000ull
+#define DCORE2_HMMU0_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE2_HMMU0_USER_CTI_SECTION 0x1000
+#define mmDCORE2_HMMU0_BMON_0_BASE 0x6487000ull
+#define DCORE2_HMMU0_BMON_0_MAX_OFFSET 0x1000
+#define DCORE2_HMMU0_BMON_0_SECTION 0x1000
+#define mmDCORE2_HMMU0_BMON_1_BASE 0x6488000ull
+#define DCORE2_HMMU0_BMON_1_MAX_OFFSET 0x1000
+#define DCORE2_HMMU0_BMON_1_SECTION 0x1000
+#define mmDCORE2_HMMU0_BMON_3_BASE 0x6489000ull
+#define DCORE2_HMMU0_BMON_3_MAX_OFFSET 0x1000
+#define DCORE2_HMMU0_BMON_3_SECTION 0x1000
+#define mmDCORE2_HMMU0_BMON_2_BASE 0x648A000ull
+#define DCORE2_HMMU0_BMON_2_MAX_OFFSET 0x1000
+#define DCORE2_HMMU0_BMON_2_SECTION 0x1000
+#define mmDCORE2_HMMU0_BMON_4_BASE 0x648B000ull
+#define DCORE2_HMMU0_BMON_4_MAX_OFFSET 0x1000
+#define DCORE2_HMMU0_BMON_4_SECTION 0x5000
+#define mmDCORE2_HMMU1_CS_ROM_TBL_BASE 0x6490000ull
+#define DCORE2_HMMU1_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE2_HMMU1_CS_ROM_TBL_SECTION 0x1000
+#define mmDCORE2_HMMU1_CS_STM_BASE 0x6491000ull
+#define DCORE2_HMMU1_CS_STM_MAX_OFFSET 0x1000
+#define DCORE2_HMMU1_CS_STM_SECTION 0x1000
+#define mmDCORE2_HMMU1_CS_CTI_BASE 0x6492000ull
+#define DCORE2_HMMU1_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE2_HMMU1_CS_CTI_SECTION 0x1000
+#define mmDCORE2_HMMU1_CS_ETF_BASE 0x6493000ull
+#define DCORE2_HMMU1_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE2_HMMU1_CS_ETF_SECTION 0x1000
+#define mmDCORE2_HMMU1_CS_SPMU_BASE 0x6494000ull
+#define DCORE2_HMMU1_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_HMMU1_CS_SPMU_SECTION 0x1000
+#define mmDCORE2_HMMU1_BMON_CTI_BASE 0x6495000ull
+#define DCORE2_HMMU1_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE2_HMMU1_BMON_CTI_SECTION 0x1000
+#define mmDCORE2_HMMU1_USER_CTI_BASE 0x6496000ull
+#define DCORE2_HMMU1_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE2_HMMU1_USER_CTI_SECTION 0x1000
+#define mmDCORE2_HMMU1_BMON_0_BASE 0x6497000ull
+#define DCORE2_HMMU1_BMON_0_MAX_OFFSET 0x1000
+#define DCORE2_HMMU1_BMON_0_SECTION 0x1000
+#define mmDCORE2_HMMU1_BMON_1_BASE 0x6498000ull
+#define DCORE2_HMMU1_BMON_1_MAX_OFFSET 0x1000
+#define DCORE2_HMMU1_BMON_1_SECTION 0x1000
+#define mmDCORE2_HMMU1_BMON_3_BASE 0x6499000ull
+#define DCORE2_HMMU1_BMON_3_MAX_OFFSET 0x1000
+#define DCORE2_HMMU1_BMON_3_SECTION 0x1000
+#define mmDCORE2_HMMU1_BMON_2_BASE 0x649A000ull
+#define DCORE2_HMMU1_BMON_2_MAX_OFFSET 0x1000
+#define DCORE2_HMMU1_BMON_2_SECTION 0x1000
+#define mmDCORE2_HMMU1_BMON_4_BASE 0x649B000ull
+#define DCORE2_HMMU1_BMON_4_MAX_OFFSET 0x1000
+#define DCORE2_HMMU1_BMON_4_SECTION 0x5000
+#define mmDCORE2_HMMU2_CS_ROM_TBL_BASE 0x64A0000ull
+#define DCORE2_HMMU2_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE2_HMMU2_CS_ROM_TBL_SECTION 0x1000
+#define mmDCORE2_HMMU2_CS_STM_BASE 0x64A1000ull
+#define DCORE2_HMMU2_CS_STM_MAX_OFFSET 0x1000
+#define DCORE2_HMMU2_CS_STM_SECTION 0x1000
+#define mmDCORE2_HMMU2_CS_CTI_BASE 0x64A2000ull
+#define DCORE2_HMMU2_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE2_HMMU2_CS_CTI_SECTION 0x1000
+#define mmDCORE2_HMMU2_CS_ETF_BASE 0x64A3000ull
+#define DCORE2_HMMU2_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE2_HMMU2_CS_ETF_SECTION 0x1000
+#define mmDCORE2_HMMU2_CS_SPMU_BASE 0x64A4000ull
+#define DCORE2_HMMU2_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_HMMU2_CS_SPMU_SECTION 0x1000
+#define mmDCORE2_HMMU2_BMON_CTI_BASE 0x64A5000ull
+#define DCORE2_HMMU2_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE2_HMMU2_BMON_CTI_SECTION 0x1000
+#define mmDCORE2_HMMU2_USER_CTI_BASE 0x64A6000ull
+#define DCORE2_HMMU2_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE2_HMMU2_USER_CTI_SECTION 0x1000
+#define mmDCORE2_HMMU2_BMON_0_BASE 0x64A7000ull
+#define DCORE2_HMMU2_BMON_0_MAX_OFFSET 0x1000
+#define DCORE2_HMMU2_BMON_0_SECTION 0x1000
+#define mmDCORE2_HMMU2_BMON_1_BASE 0x64A8000ull
+#define DCORE2_HMMU2_BMON_1_MAX_OFFSET 0x1000
+#define DCORE2_HMMU2_BMON_1_SECTION 0x1000
+#define mmDCORE2_HMMU2_BMON_3_BASE 0x64A9000ull
+#define DCORE2_HMMU2_BMON_3_MAX_OFFSET 0x1000
+#define DCORE2_HMMU2_BMON_3_SECTION 0x1000
+#define mmDCORE2_HMMU2_BMON_2_BASE 0x64AA000ull
+#define DCORE2_HMMU2_BMON_2_MAX_OFFSET 0x1000
+#define DCORE2_HMMU2_BMON_2_SECTION 0x1000
+#define mmDCORE2_HMMU2_BMON_4_BASE 0x64AB000ull
+#define DCORE2_HMMU2_BMON_4_MAX_OFFSET 0x1000
+#define DCORE2_HMMU2_BMON_4_SECTION 0x5000
+#define mmDCORE2_HMMU3_CS_ROM_TBL_BASE 0x64B0000ull
+#define DCORE2_HMMU3_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE2_HMMU3_CS_ROM_TBL_SECTION 0x1000
+#define mmDCORE2_HMMU3_CS_STM_BASE 0x64B1000ull
+#define DCORE2_HMMU3_CS_STM_MAX_OFFSET 0x1000
+#define DCORE2_HMMU3_CS_STM_SECTION 0x1000
+#define mmDCORE2_HMMU3_CS_CTI_BASE 0x64B2000ull
+#define DCORE2_HMMU3_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE2_HMMU3_CS_CTI_SECTION 0x1000
+#define mmDCORE2_HMMU3_CS_ETF_BASE 0x64B3000ull
+#define DCORE2_HMMU3_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE2_HMMU3_CS_ETF_SECTION 0x1000
+#define mmDCORE2_HMMU3_CS_SPMU_BASE 0x64B4000ull
+#define DCORE2_HMMU3_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_HMMU3_CS_SPMU_SECTION 0x1000
+#define mmDCORE2_HMMU3_BMON_CTI_BASE 0x64B5000ull
+#define DCORE2_HMMU3_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE2_HMMU3_BMON_CTI_SECTION 0x1000
+#define mmDCORE2_HMMU3_USER_CTI_BASE 0x64B6000ull
+#define DCORE2_HMMU3_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE2_HMMU3_USER_CTI_SECTION 0x1000
+#define mmDCORE2_HMMU3_BMON_0_BASE 0x64B7000ull
+#define DCORE2_HMMU3_BMON_0_MAX_OFFSET 0x1000
+#define DCORE2_HMMU3_BMON_0_SECTION 0x1000
+#define mmDCORE2_HMMU3_BMON_1_BASE 0x64B8000ull
+#define DCORE2_HMMU3_BMON_1_MAX_OFFSET 0x1000
+#define DCORE2_HMMU3_BMON_1_SECTION 0x1000
+#define mmDCORE2_HMMU3_BMON_3_BASE 0x64B9000ull
+#define DCORE2_HMMU3_BMON_3_MAX_OFFSET 0x1000
+#define DCORE2_HMMU3_BMON_3_SECTION 0x1000
+#define mmDCORE2_HMMU3_BMON_2_BASE 0x64BA000ull
+#define DCORE2_HMMU3_BMON_2_MAX_OFFSET 0x1000
+#define DCORE2_HMMU3_BMON_2_SECTION 0x1000
+#define mmDCORE2_HMMU3_BMON_4_BASE 0x64BB000ull
+#define DCORE2_HMMU3_BMON_4_MAX_OFFSET 0x1000
+#define DCORE2_HMMU3_BMON_4_SECTION 0x5000
+#define mmDCORE2_MME_CTRL_ROM_TABLE_BASE 0x64C0000ull
+#define DCORE2_MME_CTRL_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE2_MME_CTRL_ROM_TABLE_SECTION 0x1000
+#define mmDCORE2_MME_CTRL_STM_BASE 0x64C1000ull
+#define DCORE2_MME_CTRL_STM_MAX_OFFSET 0x1000
+#define DCORE2_MME_CTRL_STM_SECTION 0x1000
+#define mmDCORE2_MME_CTRL_CTI_BASE 0x64C2000ull
+#define DCORE2_MME_CTRL_CTI_MAX_OFFSET 0x1000
+#define DCORE2_MME_CTRL_CTI_SECTION 0x1000
+#define mmDCORE2_MME_CTRL_ETF_BASE 0x64C3000ull
+#define DCORE2_MME_CTRL_ETF_MAX_OFFSET 0x1000
+#define DCORE2_MME_CTRL_ETF_SECTION 0x1000
+#define mmDCORE2_MME_CTRL_SPMU_BASE 0x64C4000ull
+#define DCORE2_MME_CTRL_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_MME_CTRL_SPMU_SECTION 0x1000
+#define mmDCORE2_MME_CTRL_CTI0_BASE 0x64C5000ull
+#define DCORE2_MME_CTRL_CTI0_MAX_OFFSET 0x1000
+#define DCORE2_MME_CTRL_CTI0_SECTION 0x1000
+#define mmDCORE2_MME_CTRL_CTI1_BASE 0x64C6000ull
+#define DCORE2_MME_CTRL_CTI1_MAX_OFFSET 0x1000
+#define DCORE2_MME_CTRL_CTI1_SECTION 0x1000
+#define mmDCORE2_MME_CTRL_BMON0_BASE 0x64C7000ull
+#define DCORE2_MME_CTRL_BMON0_MAX_OFFSET 0x1000
+#define DCORE2_MME_CTRL_BMON0_SECTION 0x1000
+#define mmDCORE2_MME_CTRL_BMON1_BASE 0x64C8000ull
+#define DCORE2_MME_CTRL_BMON1_MAX_OFFSET 0x1000
+#define DCORE2_MME_CTRL_BMON1_SECTION 0x1000
+#define mmDCORE2_MME_CTRL_BMON2_BASE 0x64C9000ull
+#define DCORE2_MME_CTRL_BMON2_MAX_OFFSET 0x1000
+#define DCORE2_MME_CTRL_BMON2_SECTION 0x1000
+#define mmDCORE2_MME_CTRL_BMON3_BASE 0x64CA000ull
+#define DCORE2_MME_CTRL_BMON3_MAX_OFFSET 0x1000
+#define DCORE2_MME_CTRL_BMON3_SECTION 0x1000
+#define mmDCORE2_MME_CTRL_ARC_RTT_BASE 0x64CB000ull
+#define DCORE2_MME_CTRL_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE2_MME_CTRL_ARC_RTT_SECTION 0x5000
+#define mmDCORE2_MME_SBTE0_ROM_TBL_BASE 0x64D0000ull
+#define DCORE2_MME_SBTE0_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE0_ROM_TBL_SECTION 0x1000
+#define mmDCORE2_MME_SBTE0_STM_BASE 0x64D1000ull
+#define DCORE2_MME_SBTE0_STM_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE0_STM_SECTION 0x1000
+#define mmDCORE2_MME_SBTE0_CTI_BASE 0x64D2000ull
+#define DCORE2_MME_SBTE0_CTI_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE0_CTI_SECTION 0x1000
+#define mmDCORE2_MME_SBTE0_ETF_BASE 0x64D3000ull
+#define DCORE2_MME_SBTE0_ETF_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE0_ETF_SECTION 0x1000
+#define mmDCORE2_MME_SBTE0_SPMU_BASE 0x64D4000ull
+#define DCORE2_MME_SBTE0_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE0_SPMU_SECTION 0x1000
+#define mmDCORE2_MME_SBTE0_CTI0_BASE 0x64D5000ull
+#define DCORE2_MME_SBTE0_CTI0_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE0_CTI0_SECTION 0x1000
+#define mmDCORE2_MME_SBTE0_CTI1_BASE 0x64D6000ull
+#define DCORE2_MME_SBTE0_CTI1_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE0_CTI1_SECTION 0x1000
+#define mmDCORE2_MME_SBTE0_BMON0_BASE 0x64D7000ull
+#define DCORE2_MME_SBTE0_BMON0_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE0_BMON0_SECTION 0x1000
+#define mmDCORE2_MME_SBTE1_ROM_TBL_BASE 0x64D8000ull
+#define DCORE2_MME_SBTE1_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE1_ROM_TBL_SECTION 0x1000
+#define mmDCORE2_MME_SBTE1_STM_BASE 0x64D9000ull
+#define DCORE2_MME_SBTE1_STM_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE1_STM_SECTION 0x1000
+#define mmDCORE2_MME_SBTE1_CTI_BASE 0x64DA000ull
+#define DCORE2_MME_SBTE1_CTI_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE1_CTI_SECTION 0x1000
+#define mmDCORE2_MME_SBTE1_ETF_BASE 0x64DB000ull
+#define DCORE2_MME_SBTE1_ETF_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE1_ETF_SECTION 0x1000
+#define mmDCORE2_MME_SBTE1_SPMU_BASE 0x64DC000ull
+#define DCORE2_MME_SBTE1_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE1_SPMU_SECTION 0x1000
+#define mmDCORE2_MME_SBTE1_CTI0_BASE 0x64DD000ull
+#define DCORE2_MME_SBTE1_CTI0_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE1_CTI0_SECTION 0x1000
+#define mmDCORE2_MME_SBTE1_CTI1_BASE 0x64DE000ull
+#define DCORE2_MME_SBTE1_CTI1_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE1_CTI1_SECTION 0x1000
+#define mmDCORE2_MME_SBTE1_BMON0_BASE 0x64DF000ull
+#define DCORE2_MME_SBTE1_BMON0_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE1_BMON0_SECTION 0x1000
+#define mmDCORE2_MME_SBTE2_ROM_TBL_BASE 0x64E0000ull
+#define DCORE2_MME_SBTE2_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE2_ROM_TBL_SECTION 0x1000
+#define mmDCORE2_MME_SBTE2_STM_BASE 0x64E1000ull
+#define DCORE2_MME_SBTE2_STM_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE2_STM_SECTION 0x1000
+#define mmDCORE2_MME_SBTE2_CTI_BASE 0x64E2000ull
+#define DCORE2_MME_SBTE2_CTI_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE2_CTI_SECTION 0x1000
+#define mmDCORE2_MME_SBTE2_ETF_BASE 0x64E3000ull
+#define DCORE2_MME_SBTE2_ETF_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE2_ETF_SECTION 0x1000
+#define mmDCORE2_MME_SBTE2_SPMU_BASE 0x64E4000ull
+#define DCORE2_MME_SBTE2_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE2_SPMU_SECTION 0x1000
+#define mmDCORE2_MME_SBTE2_CTI0_BASE 0x64E5000ull
+#define DCORE2_MME_SBTE2_CTI0_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE2_CTI0_SECTION 0x1000
+#define mmDCORE2_MME_SBTE2_CTI1_BASE 0x64E6000ull
+#define DCORE2_MME_SBTE2_CTI1_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE2_CTI1_SECTION 0x1000
+#define mmDCORE2_MME_SBTE2_BMON0_BASE 0x64E7000ull
+#define DCORE2_MME_SBTE2_BMON0_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE2_BMON0_SECTION 0x1000
+#define mmDCORE2_MME_SBTE3_ROM_TBL_BASE 0x64E8000ull
+#define DCORE2_MME_SBTE3_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE3_ROM_TBL_SECTION 0x1000
+#define mmDCORE2_MME_SBTE3_STM_BASE 0x64E9000ull
+#define DCORE2_MME_SBTE3_STM_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE3_STM_SECTION 0x1000
+#define mmDCORE2_MME_SBTE3_CTI_BASE 0x64EA000ull
+#define DCORE2_MME_SBTE3_CTI_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE3_CTI_SECTION 0x1000
+#define mmDCORE2_MME_SBTE3_ETF_BASE 0x64EB000ull
+#define DCORE2_MME_SBTE3_ETF_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE3_ETF_SECTION 0x1000
+#define mmDCORE2_MME_SBTE3_SPMU_BASE 0x64EC000ull
+#define DCORE2_MME_SBTE3_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE3_SPMU_SECTION 0x1000
+#define mmDCORE2_MME_SBTE3_CTI0_BASE 0x64ED000ull
+#define DCORE2_MME_SBTE3_CTI0_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE3_CTI0_SECTION 0x1000
+#define mmDCORE2_MME_SBTE3_CTI1_BASE 0x64EE000ull
+#define DCORE2_MME_SBTE3_CTI1_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE3_CTI1_SECTION 0x1000
+#define mmDCORE2_MME_SBTE3_BMON0_BASE 0x64EF000ull
+#define DCORE2_MME_SBTE3_BMON0_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE3_BMON0_SECTION 0x1000
+#define mmDCORE2_MME_SBTE4_ROM_TBL_BASE 0x64F0000ull
+#define DCORE2_MME_SBTE4_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE4_ROM_TBL_SECTION 0x1000
+#define mmDCORE2_MME_SBTE4_STM_BASE 0x64F1000ull
+#define DCORE2_MME_SBTE4_STM_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE4_STM_SECTION 0x1000
+#define mmDCORE2_MME_SBTE4_CTI_BASE 0x64F2000ull
+#define DCORE2_MME_SBTE4_CTI_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE4_CTI_SECTION 0x1000
+#define mmDCORE2_MME_SBTE4_ETF_BASE 0x64F3000ull
+#define DCORE2_MME_SBTE4_ETF_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE4_ETF_SECTION 0x1000
+#define mmDCORE2_MME_SBTE4_SPMU_BASE 0x64F4000ull
+#define DCORE2_MME_SBTE4_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE4_SPMU_SECTION 0x1000
+#define mmDCORE2_MME_SBTE4_CTI0_BASE 0x64F5000ull
+#define DCORE2_MME_SBTE4_CTI0_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE4_CTI0_SECTION 0x1000
+#define mmDCORE2_MME_SBTE4_CTI1_BASE 0x64F6000ull
+#define DCORE2_MME_SBTE4_CTI1_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE4_CTI1_SECTION 0x1000
+#define mmDCORE2_MME_SBTE4_BMON0_BASE 0x64F7000ull
+#define DCORE2_MME_SBTE4_BMON0_MAX_OFFSET 0x1000
+#define DCORE2_MME_SBTE4_BMON0_SECTION 0x9000
+#define mmDCORE2_MME_ACC_CS_ROM_TBL_BASE 0x6500000ull
+#define DCORE2_MME_ACC_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE2_MME_ACC_CS_ROM_TBL_SECTION 0x1000
+#define mmDCORE2_MME_ACC_STM_BASE 0x6501000ull
+#define DCORE2_MME_ACC_STM_MAX_OFFSET 0x1000
+#define DCORE2_MME_ACC_STM_SECTION 0x1000
+#define mmDCORE2_MME_ACC_CTI_BASE 0x6502000ull
+#define DCORE2_MME_ACC_CTI_MAX_OFFSET 0x1000
+#define DCORE2_MME_ACC_CTI_SECTION 0x1000
+#define mmDCORE2_MME_ACC_ETF_BASE 0x6503000ull
+#define DCORE2_MME_ACC_ETF_MAX_OFFSET 0x1000
+#define DCORE2_MME_ACC_ETF_SECTION 0x1000
+#define mmDCORE2_MME_ACC_SPMU_BASE 0x6504000ull
+#define DCORE2_MME_ACC_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_MME_ACC_SPMU_SECTION 0x1000
+#define mmDCORE2_MME_ACC_CTI0_BASE 0x6505000ull
+#define DCORE2_MME_ACC_CTI0_MAX_OFFSET 0x1000
+#define DCORE2_MME_ACC_CTI0_SECTION 0x1000
+#define mmDCORE2_MME_ACC_CTI1_BASE 0x6506000ull
+#define DCORE2_MME_ACC_CTI1_MAX_OFFSET 0x1000
+#define DCORE2_MME_ACC_CTI1_SECTION 0x1000
+#define mmDCORE2_MME_ACC_BMON0_BASE 0x6507000ull
+#define DCORE2_MME_ACC_BMON0_MAX_OFFSET 0x1000
+#define DCORE2_MME_ACC_BMON0_SECTION 0x1000
+#define mmDCORE2_MME_ACC_BMON1_BASE 0x6508000ull
+#define DCORE2_MME_ACC_BMON1_MAX_OFFSET 0x1000
+#define DCORE2_MME_ACC_BMON1_SECTION 0x8000
+#define mmDCORE2_SM_CS_DBG_ROM_TBL_BASE 0x6510000ull
+#define DCORE2_SM_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE2_SM_CS_DBG_ROM_TBL_SECTION 0x1000
+#define mmDCORE2_SM_STM_BASE 0x6511000ull
+#define DCORE2_SM_STM_MAX_OFFSET 0x1000
+#define DCORE2_SM_STM_SECTION 0x1000
+#define mmDCORE2_SM_CTI_BASE 0x6512000ull
+#define DCORE2_SM_CTI_MAX_OFFSET 0x1000
+#define DCORE2_SM_CTI_SECTION 0x1000
+#define mmDCORE2_SM_ETF_BASE 0x6513000ull
+#define DCORE2_SM_ETF_MAX_OFFSET 0x1000
+#define DCORE2_SM_ETF_SECTION 0x1000
+#define mmDCORE2_SM_SPMU_BASE 0x6514000ull
+#define DCORE2_SM_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_SM_SPMU_SECTION 0x1000
+#define mmDCORE2_SM_BMON_CTI_BASE 0x6515000ull
+#define DCORE2_SM_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE2_SM_BMON_CTI_SECTION 0x1000
+#define mmDCORE2_SM_USER_CTI_BASE 0x6516000ull
+#define DCORE2_SM_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE2_SM_USER_CTI_SECTION 0x1000
+#define mmDCORE2_SM_BMON_BASE 0x6517000ull
+#define DCORE2_SM_BMON_MAX_OFFSET 0x1000
+#define DCORE2_SM_BMON_SECTION 0x1000
+#define mmDCORE2_SM_BMON1_BASE 0x6518000ull
+#define DCORE2_SM_BMON1_MAX_OFFSET 0x1000
+#define DCORE2_SM_BMON1_SECTION 0x18000
+#define mmDCORE2_XFT_FUNNEL_BASE 0x6530000ull
+#define DCORE2_XFT_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_XFT_FUNNEL_SECTION 0x8000
+#define mmDCORE2_TFT0_FUNNEL_BASE 0x6538000ull
+#define DCORE2_TFT0_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_TFT0_FUNNEL_SECTION 0x1000
+#define mmDCORE2_TFT1_FUNNEL_BASE 0x6539000ull
+#define DCORE2_TFT1_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_TFT1_FUNNEL_SECTION 0x1000
+#define mmDCORE2_TFT2_FUNNEL_BASE 0x653A000ull
+#define DCORE2_TFT2_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_TFT2_FUNNEL_SECTION 0x7000
+#define mmDCORE2_RTR0_FUNNEL_BASE 0x6541000ull
+#define DCORE2_RTR0_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_RTR0_FUNNEL_SECTION 0x8000
+#define mmDCORE2_RTR1_FUNNEL_BASE 0x6549000ull
+#define DCORE2_RTR1_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_RTR1_FUNNEL_SECTION 0x8000
+#define mmDCORE2_RTR2_FUNNEL_BASE 0x6551000ull
+#define DCORE2_RTR2_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_RTR2_FUNNEL_SECTION 0x8000
+#define mmDCORE2_RTR3_FUNNEL_BASE 0x6559000ull
+#define DCORE2_RTR3_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_RTR3_FUNNEL_SECTION 0x8000
+#define mmDCORE2_RTR4_FUNNEL_BASE 0x6561000ull
+#define DCORE2_RTR4_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_RTR4_FUNNEL_SECTION 0x4000
+#define mmDCORE2_MIF0_FUNNEL_BASE 0x6565000ull
+#define DCORE2_MIF0_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_MIF0_FUNNEL_SECTION 0x4000
+#define mmDCORE2_RTR5_FUNNEL_BASE 0x6569000ull
+#define DCORE2_RTR5_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_RTR5_FUNNEL_SECTION 0x4000
+#define mmDCORE2_MIF1_FUNNEL_BASE 0x656D000ull
+#define DCORE2_MIF1_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_MIF1_FUNNEL_SECTION 0x4000
+#define mmDCORE2_RTR6_FUNNEL_BASE 0x6571000ull
+#define DCORE2_RTR6_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_RTR6_FUNNEL_SECTION 0x4000
+#define mmDCORE2_MIF2_FUNNEL_BASE 0x6575000ull
+#define DCORE2_MIF2_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_MIF2_FUNNEL_SECTION 0x4000
+#define mmDCORE2_RTR7_FUNNEL_BASE 0x6579000ull
+#define DCORE2_RTR7_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_RTR7_FUNNEL_SECTION 0x4000
+#define mmDCORE2_MIF3_FUNNEL_BASE 0x657D000ull
+#define DCORE2_MIF3_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_MIF3_FUNNEL_SECTION 0x43000
+#define mmDCORE2_EDMA0_CS_ROM_TBL_BASE 0x65C0000ull
+#define DCORE2_EDMA0_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE2_EDMA0_CS_ROM_TBL_SECTION 0x1000
+#define mmDCORE2_EDMA0_CS_STM_BASE 0x65C1000ull
+#define DCORE2_EDMA0_CS_STM_MAX_OFFSET 0x1000
+#define DCORE2_EDMA0_CS_STM_SECTION 0x1000
+#define mmDCORE2_EDMA0_CS_CTI_BASE 0x65C2000ull
+#define DCORE2_EDMA0_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE2_EDMA0_CS_CTI_SECTION 0x1000
+#define mmDCORE2_EDMA0_CS_ETF_BASE 0x65C3000ull
+#define DCORE2_EDMA0_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE2_EDMA0_CS_ETF_SECTION 0x1000
+#define mmDCORE2_EDMA0_CS_SPMU_BASE 0x65C4000ull
+#define DCORE2_EDMA0_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_EDMA0_CS_SPMU_SECTION 0x1000
+#define mmDCORE2_EDMA0_BMON_CTI_BASE 0x65C5000ull
+#define DCORE2_EDMA0_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE2_EDMA0_BMON_CTI_SECTION 0x1000
+#define mmDCORE2_EDMA0_USER_CTI_BASE 0x65C6000ull
+#define DCORE2_EDMA0_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE2_EDMA0_USER_CTI_SECTION 0x1000
+#define mmDCORE2_EDMA0_BMON_0_BASE 0x65C7000ull
+#define DCORE2_EDMA0_BMON_0_MAX_OFFSET 0x1000
+#define DCORE2_EDMA0_BMON_0_SECTION 0x1000
+#define mmDCORE2_EDMA0_BMON_1_BASE 0x65C8000ull
+#define DCORE2_EDMA0_BMON_1_MAX_OFFSET 0x1000
+#define DCORE2_EDMA0_BMON_1_SECTION 0x1000
+#define mmDCORE2_EDMA0_QM_ARC_RTT_BASE 0x65C9000ull
+#define DCORE2_EDMA0_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE2_EDMA0_QM_ARC_RTT_SECTION 0x7000
+#define mmDCORE2_EDMA1_CS_ROM_TBL_BASE 0x65D0000ull
+#define DCORE2_EDMA1_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE2_EDMA1_CS_ROM_TBL_SECTION 0x1000
+#define mmDCORE2_EDMA1_CS_STM_BASE 0x65D1000ull
+#define DCORE2_EDMA1_CS_STM_MAX_OFFSET 0x1000
+#define DCORE2_EDMA1_CS_STM_SECTION 0x1000
+#define mmDCORE2_EDMA1_CS_CTI_BASE 0x65D2000ull
+#define DCORE2_EDMA1_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE2_EDMA1_CS_CTI_SECTION 0x1000
+#define mmDCORE2_EDMA1_CS_ETF_BASE 0x65D3000ull
+#define DCORE2_EDMA1_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE2_EDMA1_CS_ETF_SECTION 0x1000
+#define mmDCORE2_EDMA1_CS_SPMU_BASE 0x65D4000ull
+#define DCORE2_EDMA1_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_EDMA1_CS_SPMU_SECTION 0x1000
+#define mmDCORE2_EDMA1_BMON_CTI_BASE 0x65D5000ull
+#define DCORE2_EDMA1_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE2_EDMA1_BMON_CTI_SECTION 0x1000
+#define mmDCORE2_EDMA1_USER_CTI_BASE 0x65D6000ull
+#define DCORE2_EDMA1_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE2_EDMA1_USER_CTI_SECTION 0x1000
+#define mmDCORE2_EDMA1_BMON_0_BASE 0x65D7000ull
+#define DCORE2_EDMA1_BMON_0_MAX_OFFSET 0x1000
+#define DCORE2_EDMA1_BMON_0_SECTION 0x1000
+#define mmDCORE2_EDMA1_BMON_1_BASE 0x65D8000ull
+#define DCORE2_EDMA1_BMON_1_MAX_OFFSET 0x1000
+#define DCORE2_EDMA1_BMON_1_SECTION 0x1000
+#define mmDCORE2_EDMA1_QM_ARC_RTT_BASE 0x65D9000ull
+#define DCORE2_EDMA1_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE2_EDMA1_QM_ARC_RTT_SECTION 0x7000
+#define mmDCORE2_VDEC0_CS_ROM_TBL_BASE 0x65E0000ull
+#define DCORE2_VDEC0_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE2_VDEC0_CS_ROM_TBL_SECTION 0x1000
+#define mmDCORE2_VDEC0_CS_STM_BASE 0x65E1000ull
+#define DCORE2_VDEC0_CS_STM_MAX_OFFSET 0x1000
+#define DCORE2_VDEC0_CS_STM_SECTION 0x1000
+#define mmDCORE2_VDEC0_CS_CTI_BASE 0x65E2000ull
+#define DCORE2_VDEC0_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE2_VDEC0_CS_CTI_SECTION 0x1000
+#define mmDCORE2_VDEC0_CS_ETF_BASE 0x65E3000ull
+#define DCORE2_VDEC0_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE2_VDEC0_CS_ETF_SECTION 0x1000
+#define mmDCORE2_VDEC0_CS_SPMU_BASE 0x65E4000ull
+#define DCORE2_VDEC0_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_VDEC0_CS_SPMU_SECTION 0x1000
+#define mmDCORE2_VDEC0_BMON_CTI_BASE 0x65E5000ull
+#define DCORE2_VDEC0_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE2_VDEC0_BMON_CTI_SECTION 0x1000
+#define mmDCORE2_VDEC0_USER_CTI_BASE 0x65E6000ull
+#define DCORE2_VDEC0_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE2_VDEC0_USER_CTI_SECTION 0x1000
+#define mmDCORE2_VDEC0_BMON_0_BASE 0x65E7000ull
+#define DCORE2_VDEC0_BMON_0_MAX_OFFSET 0x1000
+#define DCORE2_VDEC0_BMON_0_SECTION 0x1000
+#define mmDCORE2_VDEC0_BMON_1_BASE 0x65E8000ull
+#define DCORE2_VDEC0_BMON_1_MAX_OFFSET 0x1000
+#define DCORE2_VDEC0_BMON_1_SECTION 0x1000
+#define mmDCORE2_VDEC0_BMON_2_BASE 0x65E9000ull
+#define DCORE2_VDEC0_BMON_2_MAX_OFFSET 0x1000
+#define DCORE2_VDEC0_BMON_2_SECTION 0x7000
+#define mmDCORE2_VDEC1_CS_ROM_TBL_BASE 0x65F0000ull
+#define DCORE2_VDEC1_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE2_VDEC1_CS_ROM_TBL_SECTION 0x1000
+#define mmDCORE2_VDEC1_CS_STM_BASE 0x65F1000ull
+#define DCORE2_VDEC1_CS_STM_MAX_OFFSET 0x1000
+#define DCORE2_VDEC1_CS_STM_SECTION 0x1000
+#define mmDCORE2_VDEC1_CS_CTI_BASE 0x65F2000ull
+#define DCORE2_VDEC1_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE2_VDEC1_CS_CTI_SECTION 0x1000
+#define mmDCORE2_VDEC1_CS_ETF_BASE 0x65F3000ull
+#define DCORE2_VDEC1_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE2_VDEC1_CS_ETF_SECTION 0x1000
+#define mmDCORE2_VDEC1_CS_SPMU_BASE 0x65F4000ull
+#define DCORE2_VDEC1_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE2_VDEC1_CS_SPMU_SECTION 0x1000
+#define mmDCORE2_VDEC1_BMON_CTI_BASE 0x65F5000ull
+#define DCORE2_VDEC1_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE2_VDEC1_BMON_CTI_SECTION 0x1000
+#define mmDCORE2_VDEC1_USER_CTI_BASE 0x65F6000ull
+#define DCORE2_VDEC1_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE2_VDEC1_USER_CTI_SECTION 0x1000
+#define mmDCORE2_VDEC1_BMON_0_BASE 0x65F7000ull
+#define DCORE2_VDEC1_BMON_0_MAX_OFFSET 0x1000
+#define DCORE2_VDEC1_BMON_0_SECTION 0x1000
+#define mmDCORE2_VDEC1_BMON_1_BASE 0x65F8000ull
+#define DCORE2_VDEC1_BMON_1_MAX_OFFSET 0x1000
+#define DCORE2_VDEC1_BMON_1_SECTION 0x1000
+#define mmDCORE2_VDEC1_BMON_2_BASE 0x65F9000ull
+#define DCORE2_VDEC1_BMON_2_MAX_OFFSET 0x1000
+#define DCORE2_VDEC1_BMON_2_SECTION 0x7000
+#define mmDCORE3_ROM_TABLE_L_BASE 0x6600000ull
+#define DCORE3_ROM_TABLE_L_MAX_OFFSET 0x1000
+#define DCORE3_ROM_TABLE_L_SECTION 0x80000
+#define mmDCORE3_HMMU0_CS_ROM_TBL_BASE 0x6680000ull
+#define DCORE3_HMMU0_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE3_HMMU0_CS_ROM_TBL_SECTION 0x1000
+#define mmDCORE3_HMMU0_CS_STM_BASE 0x6681000ull
+#define DCORE3_HMMU0_CS_STM_MAX_OFFSET 0x1000
+#define DCORE3_HMMU0_CS_STM_SECTION 0x1000
+#define mmDCORE3_HMMU0_CS_CTI_BASE 0x6682000ull
+#define DCORE3_HMMU0_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE3_HMMU0_CS_CTI_SECTION 0x1000
+#define mmDCORE3_HMMU0_CS_ETF_BASE 0x6683000ull
+#define DCORE3_HMMU0_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE3_HMMU0_CS_ETF_SECTION 0x1000
+#define mmDCORE3_HMMU0_CS_SPMU_BASE 0x6684000ull
+#define DCORE3_HMMU0_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_HMMU0_CS_SPMU_SECTION 0x1000
+#define mmDCORE3_HMMU0_BMON_CTI_BASE 0x6685000ull
+#define DCORE3_HMMU0_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE3_HMMU0_BMON_CTI_SECTION 0x1000
+#define mmDCORE3_HMMU0_USER_CTI_BASE 0x6686000ull
+#define DCORE3_HMMU0_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE3_HMMU0_USER_CTI_SECTION 0x1000
+#define mmDCORE3_HMMU0_BMON_0_BASE 0x6687000ull
+#define DCORE3_HMMU0_BMON_0_MAX_OFFSET 0x1000
+#define DCORE3_HMMU0_BMON_0_SECTION 0x1000
+#define mmDCORE3_HMMU0_BMON_1_BASE 0x6688000ull
+#define DCORE3_HMMU0_BMON_1_MAX_OFFSET 0x1000
+#define DCORE3_HMMU0_BMON_1_SECTION 0x1000
+#define mmDCORE3_HMMU0_BMON_3_BASE 0x6689000ull
+#define DCORE3_HMMU0_BMON_3_MAX_OFFSET 0x1000
+#define DCORE3_HMMU0_BMON_3_SECTION 0x1000
+#define mmDCORE3_HMMU0_BMON_2_BASE 0x668A000ull
+#define DCORE3_HMMU0_BMON_2_MAX_OFFSET 0x1000
+#define DCORE3_HMMU0_BMON_2_SECTION 0x1000
+#define mmDCORE3_HMMU0_BMON_4_BASE 0x668B000ull
+#define DCORE3_HMMU0_BMON_4_MAX_OFFSET 0x1000
+#define DCORE3_HMMU0_BMON_4_SECTION 0x5000
+#define mmDCORE3_HMMU1_CS_ROM_TBL_BASE 0x6690000ull
+#define DCORE3_HMMU1_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE3_HMMU1_CS_ROM_TBL_SECTION 0x1000
+#define mmDCORE3_HMMU1_CS_STM_BASE 0x6691000ull
+#define DCORE3_HMMU1_CS_STM_MAX_OFFSET 0x1000
+#define DCORE3_HMMU1_CS_STM_SECTION 0x1000
+#define mmDCORE3_HMMU1_CS_CTI_BASE 0x6692000ull
+#define DCORE3_HMMU1_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE3_HMMU1_CS_CTI_SECTION 0x1000
+#define mmDCORE3_HMMU1_CS_ETF_BASE 0x6693000ull
+#define DCORE3_HMMU1_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE3_HMMU1_CS_ETF_SECTION 0x1000
+#define mmDCORE3_HMMU1_CS_SPMU_BASE 0x6694000ull
+#define DCORE3_HMMU1_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_HMMU1_CS_SPMU_SECTION 0x1000
+#define mmDCORE3_HMMU1_BMON_CTI_BASE 0x6695000ull
+#define DCORE3_HMMU1_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE3_HMMU1_BMON_CTI_SECTION 0x1000
+#define mmDCORE3_HMMU1_USER_CTI_BASE 0x6696000ull
+#define DCORE3_HMMU1_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE3_HMMU1_USER_CTI_SECTION 0x1000
+#define mmDCORE3_HMMU1_BMON_0_BASE 0x6697000ull
+#define DCORE3_HMMU1_BMON_0_MAX_OFFSET 0x1000
+#define DCORE3_HMMU1_BMON_0_SECTION 0x1000
+#define mmDCORE3_HMMU1_BMON_1_BASE 0x6698000ull
+#define DCORE3_HMMU1_BMON_1_MAX_OFFSET 0x1000
+#define DCORE3_HMMU1_BMON_1_SECTION 0x1000
+#define mmDCORE3_HMMU1_BMON_3_BASE 0x6699000ull
+#define DCORE3_HMMU1_BMON_3_MAX_OFFSET 0x1000
+#define DCORE3_HMMU1_BMON_3_SECTION 0x1000
+#define mmDCORE3_HMMU1_BMON_2_BASE 0x669A000ull
+#define DCORE3_HMMU1_BMON_2_MAX_OFFSET 0x1000
+#define DCORE3_HMMU1_BMON_2_SECTION 0x1000
+#define mmDCORE3_HMMU1_BMON_4_BASE 0x669B000ull
+#define DCORE3_HMMU1_BMON_4_MAX_OFFSET 0x1000
+#define DCORE3_HMMU1_BMON_4_SECTION 0x5000
+#define mmDCORE3_HMMU2_CS_ROM_TBL_BASE 0x66A0000ull
+#define DCORE3_HMMU2_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE3_HMMU2_CS_ROM_TBL_SECTION 0x1000
+#define mmDCORE3_HMMU2_CS_STM_BASE 0x66A1000ull
+#define DCORE3_HMMU2_CS_STM_MAX_OFFSET 0x1000
+#define DCORE3_HMMU2_CS_STM_SECTION 0x1000
+#define mmDCORE3_HMMU2_CS_CTI_BASE 0x66A2000ull
+#define DCORE3_HMMU2_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE3_HMMU2_CS_CTI_SECTION 0x1000
+#define mmDCORE3_HMMU2_CS_ETF_BASE 0x66A3000ull
+#define DCORE3_HMMU2_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE3_HMMU2_CS_ETF_SECTION 0x1000
+#define mmDCORE3_HMMU2_CS_SPMU_BASE 0x66A4000ull
+#define DCORE3_HMMU2_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_HMMU2_CS_SPMU_SECTION 0x1000
+#define mmDCORE3_HMMU2_BMON_CTI_BASE 0x66A5000ull
+#define DCORE3_HMMU2_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE3_HMMU2_BMON_CTI_SECTION 0x1000
+#define mmDCORE3_HMMU2_USER_CTI_BASE 0x66A6000ull
+#define DCORE3_HMMU2_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE3_HMMU2_USER_CTI_SECTION 0x1000
+#define mmDCORE3_HMMU2_BMON_0_BASE 0x66A7000ull
+#define DCORE3_HMMU2_BMON_0_MAX_OFFSET 0x1000
+#define DCORE3_HMMU2_BMON_0_SECTION 0x1000
+#define mmDCORE3_HMMU2_BMON_1_BASE 0x66A8000ull
+#define DCORE3_HMMU2_BMON_1_MAX_OFFSET 0x1000
+#define DCORE3_HMMU2_BMON_1_SECTION 0x1000
+#define mmDCORE3_HMMU2_BMON_3_BASE 0x66A9000ull
+#define DCORE3_HMMU2_BMON_3_MAX_OFFSET 0x1000
+#define DCORE3_HMMU2_BMON_3_SECTION 0x1000
+#define mmDCORE3_HMMU2_BMON_2_BASE 0x66AA000ull
+#define DCORE3_HMMU2_BMON_2_MAX_OFFSET 0x1000
+#define DCORE3_HMMU2_BMON_2_SECTION 0x1000
+#define mmDCORE3_HMMU2_BMON_4_BASE 0x66AB000ull
+#define DCORE3_HMMU2_BMON_4_MAX_OFFSET 0x1000
+#define DCORE3_HMMU2_BMON_4_SECTION 0x5000
+#define mmDCORE3_HMMU3_CS_ROM_TBL_BASE 0x66B0000ull
+#define DCORE3_HMMU3_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE3_HMMU3_CS_ROM_TBL_SECTION 0x1000
+#define mmDCORE3_HMMU3_CS_STM_BASE 0x66B1000ull
+#define DCORE3_HMMU3_CS_STM_MAX_OFFSET 0x1000
+#define DCORE3_HMMU3_CS_STM_SECTION 0x1000
+#define mmDCORE3_HMMU3_CS_CTI_BASE 0x66B2000ull
+#define DCORE3_HMMU3_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE3_HMMU3_CS_CTI_SECTION 0x1000
+#define mmDCORE3_HMMU3_CS_ETF_BASE 0x66B3000ull
+#define DCORE3_HMMU3_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE3_HMMU3_CS_ETF_SECTION 0x1000
+#define mmDCORE3_HMMU3_CS_SPMU_BASE 0x66B4000ull
+#define DCORE3_HMMU3_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_HMMU3_CS_SPMU_SECTION 0x1000
+#define mmDCORE3_HMMU3_BMON_CTI_BASE 0x66B5000ull
+#define DCORE3_HMMU3_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE3_HMMU3_BMON_CTI_SECTION 0x1000
+#define mmDCORE3_HMMU3_USER_CTI_BASE 0x66B6000ull
+#define DCORE3_HMMU3_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE3_HMMU3_USER_CTI_SECTION 0x1000
+#define mmDCORE3_HMMU3_BMON_0_BASE 0x66B7000ull
+#define DCORE3_HMMU3_BMON_0_MAX_OFFSET 0x1000
+#define DCORE3_HMMU3_BMON_0_SECTION 0x1000
+#define mmDCORE3_HMMU3_BMON_1_BASE 0x66B8000ull
+#define DCORE3_HMMU3_BMON_1_MAX_OFFSET 0x1000
+#define DCORE3_HMMU3_BMON_1_SECTION 0x1000
+#define mmDCORE3_HMMU3_BMON_3_BASE 0x66B9000ull
+#define DCORE3_HMMU3_BMON_3_MAX_OFFSET 0x1000
+#define DCORE3_HMMU3_BMON_3_SECTION 0x1000
+#define mmDCORE3_HMMU3_BMON_2_BASE 0x66BA000ull
+#define DCORE3_HMMU3_BMON_2_MAX_OFFSET 0x1000
+#define DCORE3_HMMU3_BMON_2_SECTION 0x1000
+#define mmDCORE3_HMMU3_BMON_4_BASE 0x66BB000ull
+#define DCORE3_HMMU3_BMON_4_MAX_OFFSET 0x1000
+#define DCORE3_HMMU3_BMON_4_SECTION 0x5000
+#define mmDCORE3_MME_CTRL_ROM_TABLE_BASE 0x66C0000ull
+#define DCORE3_MME_CTRL_ROM_TABLE_MAX_OFFSET 0x1000
+#define DCORE3_MME_CTRL_ROM_TABLE_SECTION 0x1000
+#define mmDCORE3_MME_CTRL_STM_BASE 0x66C1000ull
+#define DCORE3_MME_CTRL_STM_MAX_OFFSET 0x1000
+#define DCORE3_MME_CTRL_STM_SECTION 0x1000
+#define mmDCORE3_MME_CTRL_CTI_BASE 0x66C2000ull
+#define DCORE3_MME_CTRL_CTI_MAX_OFFSET 0x1000
+#define DCORE3_MME_CTRL_CTI_SECTION 0x1000
+#define mmDCORE3_MME_CTRL_ETF_BASE 0x66C3000ull
+#define DCORE3_MME_CTRL_ETF_MAX_OFFSET 0x1000
+#define DCORE3_MME_CTRL_ETF_SECTION 0x1000
+#define mmDCORE3_MME_CTRL_SPMU_BASE 0x66C4000ull
+#define DCORE3_MME_CTRL_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_MME_CTRL_SPMU_SECTION 0x1000
+#define mmDCORE3_MME_CTRL_CTI0_BASE 0x66C5000ull
+#define DCORE3_MME_CTRL_CTI0_MAX_OFFSET 0x1000
+#define DCORE3_MME_CTRL_CTI0_SECTION 0x1000
+#define mmDCORE3_MME_CTRL_CTI1_BASE 0x66C6000ull
+#define DCORE3_MME_CTRL_CTI1_MAX_OFFSET 0x1000
+#define DCORE3_MME_CTRL_CTI1_SECTION 0x1000
+#define mmDCORE3_MME_CTRL_BMON0_BASE 0x66C7000ull
+#define DCORE3_MME_CTRL_BMON0_MAX_OFFSET 0x1000
+#define DCORE3_MME_CTRL_BMON0_SECTION 0x1000
+#define mmDCORE3_MME_CTRL_BMON1_BASE 0x66C8000ull
+#define DCORE3_MME_CTRL_BMON1_MAX_OFFSET 0x1000
+#define DCORE3_MME_CTRL_BMON1_SECTION 0x1000
+#define mmDCORE3_MME_CTRL_BMON2_BASE 0x66C9000ull
+#define DCORE3_MME_CTRL_BMON2_MAX_OFFSET 0x1000
+#define DCORE3_MME_CTRL_BMON2_SECTION 0x1000
+#define mmDCORE3_MME_CTRL_BMON3_BASE 0x66CA000ull
+#define DCORE3_MME_CTRL_BMON3_MAX_OFFSET 0x1000
+#define DCORE3_MME_CTRL_BMON3_SECTION 0x1000
+#define mmDCORE3_MME_CTRL_ARC_RTT_BASE 0x66CB000ull
+#define DCORE3_MME_CTRL_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE3_MME_CTRL_ARC_RTT_SECTION 0x5000
+#define mmDCORE3_MME_SBTE0_ROM_TBL_BASE 0x66D0000ull
+#define DCORE3_MME_SBTE0_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE0_ROM_TBL_SECTION 0x1000
+#define mmDCORE3_MME_SBTE0_STM_BASE 0x66D1000ull
+#define DCORE3_MME_SBTE0_STM_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE0_STM_SECTION 0x1000
+#define mmDCORE3_MME_SBTE0_CTI_BASE 0x66D2000ull
+#define DCORE3_MME_SBTE0_CTI_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE0_CTI_SECTION 0x1000
+#define mmDCORE3_MME_SBTE0_ETF_BASE 0x66D3000ull
+#define DCORE3_MME_SBTE0_ETF_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE0_ETF_SECTION 0x1000
+#define mmDCORE3_MME_SBTE0_SPMU_BASE 0x66D4000ull
+#define DCORE3_MME_SBTE0_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE0_SPMU_SECTION 0x1000
+#define mmDCORE3_MME_SBTE0_CTI0_BASE 0x66D5000ull
+#define DCORE3_MME_SBTE0_CTI0_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE0_CTI0_SECTION 0x1000
+#define mmDCORE3_MME_SBTE0_CTI1_BASE 0x66D6000ull
+#define DCORE3_MME_SBTE0_CTI1_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE0_CTI1_SECTION 0x1000
+#define mmDCORE3_MME_SBTE0_BMON0_BASE 0x66D7000ull
+#define DCORE3_MME_SBTE0_BMON0_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE0_BMON0_SECTION 0x1000
+#define mmDCORE3_MME_SBTE1_ROM_TBL_BASE 0x66D8000ull
+#define DCORE3_MME_SBTE1_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE1_ROM_TBL_SECTION 0x1000
+#define mmDCORE3_MME_SBTE1_STM_BASE 0x66D9000ull
+#define DCORE3_MME_SBTE1_STM_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE1_STM_SECTION 0x1000
+#define mmDCORE3_MME_SBTE1_CTI_BASE 0x66DA000ull
+#define DCORE3_MME_SBTE1_CTI_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE1_CTI_SECTION 0x1000
+#define mmDCORE3_MME_SBTE1_ETF_BASE 0x66DB000ull
+#define DCORE3_MME_SBTE1_ETF_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE1_ETF_SECTION 0x1000
+#define mmDCORE3_MME_SBTE1_SPMU_BASE 0x66DC000ull
+#define DCORE3_MME_SBTE1_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE1_SPMU_SECTION 0x1000
+#define mmDCORE3_MME_SBTE1_CTI0_BASE 0x66DD000ull
+#define DCORE3_MME_SBTE1_CTI0_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE1_CTI0_SECTION 0x1000
+#define mmDCORE3_MME_SBTE1_CTI1_BASE 0x66DE000ull
+#define DCORE3_MME_SBTE1_CTI1_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE1_CTI1_SECTION 0x1000
+#define mmDCORE3_MME_SBTE1_BMON0_BASE 0x66DF000ull
+#define DCORE3_MME_SBTE1_BMON0_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE1_BMON0_SECTION 0x1000
+#define mmDCORE3_MME_SBTE2_ROM_TBL_BASE 0x66E0000ull
+#define DCORE3_MME_SBTE2_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE2_ROM_TBL_SECTION 0x1000
+#define mmDCORE3_MME_SBTE2_STM_BASE 0x66E1000ull
+#define DCORE3_MME_SBTE2_STM_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE2_STM_SECTION 0x1000
+#define mmDCORE3_MME_SBTE2_CTI_BASE 0x66E2000ull
+#define DCORE3_MME_SBTE2_CTI_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE2_CTI_SECTION 0x1000
+#define mmDCORE3_MME_SBTE2_ETF_BASE 0x66E3000ull
+#define DCORE3_MME_SBTE2_ETF_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE2_ETF_SECTION 0x1000
+#define mmDCORE3_MME_SBTE2_SPMU_BASE 0x66E4000ull
+#define DCORE3_MME_SBTE2_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE2_SPMU_SECTION 0x1000
+#define mmDCORE3_MME_SBTE2_CTI0_BASE 0x66E5000ull
+#define DCORE3_MME_SBTE2_CTI0_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE2_CTI0_SECTION 0x1000
+#define mmDCORE3_MME_SBTE2_CTI1_BASE 0x66E6000ull
+#define DCORE3_MME_SBTE2_CTI1_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE2_CTI1_SECTION 0x1000
+#define mmDCORE3_MME_SBTE2_BMON0_BASE 0x66E7000ull
+#define DCORE3_MME_SBTE2_BMON0_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE2_BMON0_SECTION 0x1000
+#define mmDCORE3_MME_SBTE3_ROM_TBL_BASE 0x66E8000ull
+#define DCORE3_MME_SBTE3_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE3_ROM_TBL_SECTION 0x1000
+#define mmDCORE3_MME_SBTE3_STM_BASE 0x66E9000ull
+#define DCORE3_MME_SBTE3_STM_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE3_STM_SECTION 0x1000
+#define mmDCORE3_MME_SBTE3_CTI_BASE 0x66EA000ull
+#define DCORE3_MME_SBTE3_CTI_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE3_CTI_SECTION 0x1000
+#define mmDCORE3_MME_SBTE3_ETF_BASE 0x66EB000ull
+#define DCORE3_MME_SBTE3_ETF_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE3_ETF_SECTION 0x1000
+#define mmDCORE3_MME_SBTE3_SPMU_BASE 0x66EC000ull
+#define DCORE3_MME_SBTE3_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE3_SPMU_SECTION 0x1000
+#define mmDCORE3_MME_SBTE3_CTI0_BASE 0x66ED000ull
+#define DCORE3_MME_SBTE3_CTI0_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE3_CTI0_SECTION 0x1000
+#define mmDCORE3_MME_SBTE3_CTI1_BASE 0x66EE000ull
+#define DCORE3_MME_SBTE3_CTI1_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE3_CTI1_SECTION 0x1000
+#define mmDCORE3_MME_SBTE3_BMON0_BASE 0x66EF000ull
+#define DCORE3_MME_SBTE3_BMON0_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE3_BMON0_SECTION 0x1000
+#define mmDCORE3_MME_SBTE4_ROM_TBL_BASE 0x66F0000ull
+#define DCORE3_MME_SBTE4_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE4_ROM_TBL_SECTION 0x1000
+#define mmDCORE3_MME_SBTE4_STM_BASE 0x66F1000ull
+#define DCORE3_MME_SBTE4_STM_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE4_STM_SECTION 0x1000
+#define mmDCORE3_MME_SBTE4_CTI_BASE 0x66F2000ull
+#define DCORE3_MME_SBTE4_CTI_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE4_CTI_SECTION 0x1000
+#define mmDCORE3_MME_SBTE4_ETF_BASE 0x66F3000ull
+#define DCORE3_MME_SBTE4_ETF_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE4_ETF_SECTION 0x1000
+#define mmDCORE3_MME_SBTE4_SPMU_BASE 0x66F4000ull
+#define DCORE3_MME_SBTE4_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE4_SPMU_SECTION 0x1000
+#define mmDCORE3_MME_SBTE4_CTI0_BASE 0x66F5000ull
+#define DCORE3_MME_SBTE4_CTI0_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE4_CTI0_SECTION 0x1000
+#define mmDCORE3_MME_SBTE4_CTI1_BASE 0x66F6000ull
+#define DCORE3_MME_SBTE4_CTI1_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE4_CTI1_SECTION 0x1000
+#define mmDCORE3_MME_SBTE4_BMON0_BASE 0x66F7000ull
+#define DCORE3_MME_SBTE4_BMON0_MAX_OFFSET 0x1000
+#define DCORE3_MME_SBTE4_BMON0_SECTION 0x9000
+#define mmDCORE3_MME_ACC_CS_ROM_TBL_BASE 0x6700000ull
+#define DCORE3_MME_ACC_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE3_MME_ACC_CS_ROM_TBL_SECTION 0x1000
+#define mmDCORE3_MME_ACC_STM_BASE 0x6701000ull
+#define DCORE3_MME_ACC_STM_MAX_OFFSET 0x1000
+#define DCORE3_MME_ACC_STM_SECTION 0x1000
+#define mmDCORE3_MME_ACC_CTI_BASE 0x6702000ull
+#define DCORE3_MME_ACC_CTI_MAX_OFFSET 0x1000
+#define DCORE3_MME_ACC_CTI_SECTION 0x1000
+#define mmDCORE3_MME_ACC_ETF_BASE 0x6703000ull
+#define DCORE3_MME_ACC_ETF_MAX_OFFSET 0x1000
+#define DCORE3_MME_ACC_ETF_SECTION 0x1000
+#define mmDCORE3_MME_ACC_SPMU_BASE 0x6704000ull
+#define DCORE3_MME_ACC_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_MME_ACC_SPMU_SECTION 0x1000
+#define mmDCORE3_MME_ACC_CTI0_BASE 0x6705000ull
+#define DCORE3_MME_ACC_CTI0_MAX_OFFSET 0x1000
+#define DCORE3_MME_ACC_CTI0_SECTION 0x1000
+#define mmDCORE3_MME_ACC_CTI1_BASE 0x6706000ull
+#define DCORE3_MME_ACC_CTI1_MAX_OFFSET 0x1000
+#define DCORE3_MME_ACC_CTI1_SECTION 0x1000
+#define mmDCORE3_MME_ACC_BMON0_BASE 0x6707000ull
+#define DCORE3_MME_ACC_BMON0_MAX_OFFSET 0x1000
+#define DCORE3_MME_ACC_BMON0_SECTION 0x1000
+#define mmDCORE3_MME_ACC_BMON1_BASE 0x6708000ull
+#define DCORE3_MME_ACC_BMON1_MAX_OFFSET 0x1000
+#define DCORE3_MME_ACC_BMON1_SECTION 0x8000
+#define mmDCORE3_SM_CS_DBG_ROM_TBL_BASE 0x6710000ull
+#define DCORE3_SM_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE3_SM_CS_DBG_ROM_TBL_SECTION 0x1000
+#define mmDCORE3_SM_STM_BASE 0x6711000ull
+#define DCORE3_SM_STM_MAX_OFFSET 0x1000
+#define DCORE3_SM_STM_SECTION 0x1000
+#define mmDCORE3_SM_CTI_BASE 0x6712000ull
+#define DCORE3_SM_CTI_MAX_OFFSET 0x1000
+#define DCORE3_SM_CTI_SECTION 0x1000
+#define mmDCORE3_SM_ETF_BASE 0x6713000ull
+#define DCORE3_SM_ETF_MAX_OFFSET 0x1000
+#define DCORE3_SM_ETF_SECTION 0x1000
+#define mmDCORE3_SM_SPMU_BASE 0x6714000ull
+#define DCORE3_SM_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_SM_SPMU_SECTION 0x1000
+#define mmDCORE3_SM_BMON_CTI_BASE 0x6715000ull
+#define DCORE3_SM_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE3_SM_BMON_CTI_SECTION 0x1000
+#define mmDCORE3_SM_USER_CTI_BASE 0x6716000ull
+#define DCORE3_SM_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE3_SM_USER_CTI_SECTION 0x1000
+#define mmDCORE3_SM_BMON_BASE 0x6717000ull
+#define DCORE3_SM_BMON_MAX_OFFSET 0x1000
+#define DCORE3_SM_BMON_SECTION 0x1000
+#define mmDCORE3_SM_BMON1_BASE 0x6718000ull
+#define DCORE3_SM_BMON1_MAX_OFFSET 0x1000
+#define DCORE3_SM_BMON1_SECTION 0x18000
+#define mmDCORE3_XFT_FUNNEL_BASE 0x6730000ull
+#define DCORE3_XFT_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_XFT_FUNNEL_SECTION 0x8000
+#define mmDCORE3_TFT0_FUNNEL_BASE 0x6738000ull
+#define DCORE3_TFT0_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_TFT0_FUNNEL_SECTION 0x1000
+#define mmDCORE3_TFT1_FUNNEL_BASE 0x6739000ull
+#define DCORE3_TFT1_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_TFT1_FUNNEL_SECTION 0x1000
+#define mmDCORE3_TFT2_FUNNEL_BASE 0x673A000ull
+#define DCORE3_TFT2_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_TFT2_FUNNEL_SECTION 0x7000
+#define mmDCORE3_RTR0_FUNNEL_BASE 0x6741000ull
+#define DCORE3_RTR0_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_RTR0_FUNNEL_SECTION 0x4000
+#define mmDCORE3_MIF0_FUNNEL_BASE 0x6745000ull
+#define DCORE3_MIF0_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_MIF0_FUNNEL_SECTION 0x4000
+#define mmDCORE3_RTR1_FUNNEL_BASE 0x6749000ull
+#define DCORE3_RTR1_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_RTR1_FUNNEL_SECTION 0x4000
+#define mmDCORE3_MIF1_FUNNEL_BASE 0x674D000ull
+#define DCORE3_MIF1_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_MIF1_FUNNEL_SECTION 0x4000
+#define mmDCORE3_RTR2_FUNNEL_BASE 0x6751000ull
+#define DCORE3_RTR2_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_RTR2_FUNNEL_SECTION 0x4000
+#define mmDCORE3_MIF2_FUNNEL_BASE 0x6755000ull
+#define DCORE3_MIF2_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_MIF2_FUNNEL_SECTION 0x4000
+#define mmDCORE3_RTR3_FUNNEL_BASE 0x6759000ull
+#define DCORE3_RTR3_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_RTR3_FUNNEL_SECTION 0x4000
+#define mmDCORE3_MIF3_FUNNEL_BASE 0x675D000ull
+#define DCORE3_MIF3_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_MIF3_FUNNEL_SECTION 0x4000
+#define mmDCORE3_RTR4_FUNNEL_BASE 0x6761000ull
+#define DCORE3_RTR4_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_RTR4_FUNNEL_SECTION 0x8000
+#define mmDCORE3_RTR5_FUNNEL_BASE 0x6769000ull
+#define DCORE3_RTR5_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_RTR5_FUNNEL_SECTION 0x8000
+#define mmDCORE3_RTR6_FUNNEL_BASE 0x6771000ull
+#define DCORE3_RTR6_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_RTR6_FUNNEL_SECTION 0x8000
+#define mmDCORE3_RTR7_FUNNEL_BASE 0x6779000ull
+#define DCORE3_RTR7_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_RTR7_FUNNEL_SECTION 0x47000
+#define mmDCORE3_EDMA0_CS_ROM_TBL_BASE 0x67C0000ull
+#define DCORE3_EDMA0_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE3_EDMA0_CS_ROM_TBL_SECTION 0x1000
+#define mmDCORE3_EDMA0_CS_STM_BASE 0x67C1000ull
+#define DCORE3_EDMA0_CS_STM_MAX_OFFSET 0x1000
+#define DCORE3_EDMA0_CS_STM_SECTION 0x1000
+#define mmDCORE3_EDMA0_CS_CTI_BASE 0x67C2000ull
+#define DCORE3_EDMA0_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE3_EDMA0_CS_CTI_SECTION 0x1000
+#define mmDCORE3_EDMA0_CS_ETF_BASE 0x67C3000ull
+#define DCORE3_EDMA0_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE3_EDMA0_CS_ETF_SECTION 0x1000
+#define mmDCORE3_EDMA0_CS_SPMU_BASE 0x67C4000ull
+#define DCORE3_EDMA0_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_EDMA0_CS_SPMU_SECTION 0x1000
+#define mmDCORE3_EDMA0_BMON_CTI_BASE 0x67C5000ull
+#define DCORE3_EDMA0_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE3_EDMA0_BMON_CTI_SECTION 0x1000
+#define mmDCORE3_EDMA0_USER_CTI_BASE 0x67C6000ull
+#define DCORE3_EDMA0_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE3_EDMA0_USER_CTI_SECTION 0x1000
+#define mmDCORE3_EDMA0_BMON_0_BASE 0x67C7000ull
+#define DCORE3_EDMA0_BMON_0_MAX_OFFSET 0x1000
+#define DCORE3_EDMA0_BMON_0_SECTION 0x1000
+#define mmDCORE3_EDMA0_BMON_1_BASE 0x67C8000ull
+#define DCORE3_EDMA0_BMON_1_MAX_OFFSET 0x1000
+#define DCORE3_EDMA0_BMON_1_SECTION 0x1000
+#define mmDCORE3_EDMA0_QM_ARC_RTT_BASE 0x67C9000ull
+#define DCORE3_EDMA0_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE3_EDMA0_QM_ARC_RTT_SECTION 0x7000
+#define mmDCORE3_EDMA1_CS_ROM_TBL_BASE 0x67D0000ull
+#define DCORE3_EDMA1_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE3_EDMA1_CS_ROM_TBL_SECTION 0x1000
+#define mmDCORE3_EDMA1_CS_STM_BASE 0x67D1000ull
+#define DCORE3_EDMA1_CS_STM_MAX_OFFSET 0x1000
+#define DCORE3_EDMA1_CS_STM_SECTION 0x1000
+#define mmDCORE3_EDMA1_CS_CTI_BASE 0x67D2000ull
+#define DCORE3_EDMA1_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE3_EDMA1_CS_CTI_SECTION 0x1000
+#define mmDCORE3_EDMA1_CS_ETF_BASE 0x67D3000ull
+#define DCORE3_EDMA1_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE3_EDMA1_CS_ETF_SECTION 0x1000
+#define mmDCORE3_EDMA1_CS_SPMU_BASE 0x67D4000ull
+#define DCORE3_EDMA1_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_EDMA1_CS_SPMU_SECTION 0x1000
+#define mmDCORE3_EDMA1_BMON_CTI_BASE 0x67D5000ull
+#define DCORE3_EDMA1_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE3_EDMA1_BMON_CTI_SECTION 0x1000
+#define mmDCORE3_EDMA1_USER_CTI_BASE 0x67D6000ull
+#define DCORE3_EDMA1_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE3_EDMA1_USER_CTI_SECTION 0x1000
+#define mmDCORE3_EDMA1_BMON_0_BASE 0x67D7000ull
+#define DCORE3_EDMA1_BMON_0_MAX_OFFSET 0x1000
+#define DCORE3_EDMA1_BMON_0_SECTION 0x1000
+#define mmDCORE3_EDMA1_BMON_1_BASE 0x67D8000ull
+#define DCORE3_EDMA1_BMON_1_MAX_OFFSET 0x1000
+#define DCORE3_EDMA1_BMON_1_SECTION 0x1000
+#define mmDCORE3_EDMA1_QM_ARC_RTT_BASE 0x67D9000ull
+#define DCORE3_EDMA1_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define DCORE3_EDMA1_QM_ARC_RTT_SECTION 0x7000
+#define mmDCORE3_VDEC0_CS_ROM_TBL_BASE 0x67E0000ull
+#define DCORE3_VDEC0_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE3_VDEC0_CS_ROM_TBL_SECTION 0x1000
+#define mmDCORE3_VDEC0_CS_STM_BASE 0x67E1000ull
+#define DCORE3_VDEC0_CS_STM_MAX_OFFSET 0x1000
+#define DCORE3_VDEC0_CS_STM_SECTION 0x1000
+#define mmDCORE3_VDEC0_CS_CTI_BASE 0x67E2000ull
+#define DCORE3_VDEC0_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE3_VDEC0_CS_CTI_SECTION 0x1000
+#define mmDCORE3_VDEC0_CS_ETF_BASE 0x67E3000ull
+#define DCORE3_VDEC0_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE3_VDEC0_CS_ETF_SECTION 0x1000
+#define mmDCORE3_VDEC0_CS_SPMU_BASE 0x67E4000ull
+#define DCORE3_VDEC0_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_VDEC0_CS_SPMU_SECTION 0x1000
+#define mmDCORE3_VDEC0_BMON_CTI_BASE 0x67E5000ull
+#define DCORE3_VDEC0_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE3_VDEC0_BMON_CTI_SECTION 0x1000
+#define mmDCORE3_VDEC0_USER_CTI_BASE 0x67E6000ull
+#define DCORE3_VDEC0_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE3_VDEC0_USER_CTI_SECTION 0x1000
+#define mmDCORE3_VDEC0_BMON_0_BASE 0x67E7000ull
+#define DCORE3_VDEC0_BMON_0_MAX_OFFSET 0x1000
+#define DCORE3_VDEC0_BMON_0_SECTION 0x1000
+#define mmDCORE3_VDEC0_BMON_1_BASE 0x67E8000ull
+#define DCORE3_VDEC0_BMON_1_MAX_OFFSET 0x1000
+#define DCORE3_VDEC0_BMON_1_SECTION 0x1000
+#define mmDCORE3_VDEC0_BMON_2_BASE 0x67E9000ull
+#define DCORE3_VDEC0_BMON_2_MAX_OFFSET 0x1000
+#define DCORE3_VDEC0_BMON_2_SECTION 0x7000
+#define mmDCORE3_VDEC1_CS_ROM_TBL_BASE 0x67F0000ull
+#define DCORE3_VDEC1_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define DCORE3_VDEC1_CS_ROM_TBL_SECTION 0x1000
+#define mmDCORE3_VDEC1_CS_STM_BASE 0x67F1000ull
+#define DCORE3_VDEC1_CS_STM_MAX_OFFSET 0x1000
+#define DCORE3_VDEC1_CS_STM_SECTION 0x1000
+#define mmDCORE3_VDEC1_CS_CTI_BASE 0x67F2000ull
+#define DCORE3_VDEC1_CS_CTI_MAX_OFFSET 0x1000
+#define DCORE3_VDEC1_CS_CTI_SECTION 0x1000
+#define mmDCORE3_VDEC1_CS_ETF_BASE 0x67F3000ull
+#define DCORE3_VDEC1_CS_ETF_MAX_OFFSET 0x1000
+#define DCORE3_VDEC1_CS_ETF_SECTION 0x1000
+#define mmDCORE3_VDEC1_CS_SPMU_BASE 0x67F4000ull
+#define DCORE3_VDEC1_CS_SPMU_MAX_OFFSET 0x1000
+#define DCORE3_VDEC1_CS_SPMU_SECTION 0x1000
+#define mmDCORE3_VDEC1_BMON_CTI_BASE 0x67F5000ull
+#define DCORE3_VDEC1_BMON_CTI_MAX_OFFSET 0x1000
+#define DCORE3_VDEC1_BMON_CTI_SECTION 0x1000
+#define mmDCORE3_VDEC1_USER_CTI_BASE 0x67F6000ull
+#define DCORE3_VDEC1_USER_CTI_MAX_OFFSET 0x1000
+#define DCORE3_VDEC1_USER_CTI_SECTION 0x1000
+#define mmDCORE3_VDEC1_BMON_0_BASE 0x67F7000ull
+#define DCORE3_VDEC1_BMON_0_MAX_OFFSET 0x1000
+#define DCORE3_VDEC1_BMON_0_SECTION 0x1000
+#define mmDCORE3_VDEC1_BMON_1_BASE 0x67F8000ull
+#define DCORE3_VDEC1_BMON_1_MAX_OFFSET 0x1000
+#define DCORE3_VDEC1_BMON_1_SECTION 0x1000
+#define mmDCORE3_VDEC1_BMON_2_BASE 0x67F9000ull
+#define DCORE3_VDEC1_BMON_2_MAX_OFFSET 0x1000
+#define DCORE3_VDEC1_BMON_2_SECTION 0x7000
+#define mmCA53_BASE 0x6800000ull
+#define CA53_MAX_OFFSET 0x141000
+#define CA53_SECTION 0x400000
+#define mmPCI_ROM_TABLE_BASE 0x6C00000ull
+#define PCI_ROM_TABLE_MAX_OFFSET 0x1000
+#define PCI_ROM_TABLE_SECTION 0x1000
+#define mmPCIE_STM_BASE 0x6C01000ull
+#define PCIE_STM_MAX_OFFSET 0x1000
+#define PCIE_STM_SECTION 0x1000
+#define mmPCIE_ETF_BASE 0x6C02000ull
+#define PCIE_ETF_MAX_OFFSET 0x1000
+#define PCIE_ETF_SECTION 0x1000
+#define mmPCIE_CTI_0_BASE 0x6C03000ull
+#define PCIE_CTI_0_MAX_OFFSET 0x1000
+#define PCIE_CTI_0_SECTION 0x1000
+#define mmPCIE_SPMU_BASE 0x6C04000ull
+#define PCIE_SPMU_MAX_OFFSET 0x1000
+#define PCIE_SPMU_SECTION 0x1000
+#define mmPCIE_CTI_1_BASE 0x6C05000ull
+#define PCIE_CTI_1_MAX_OFFSET 0x1000
+#define PCIE_CTI_1_SECTION 0x2000
+#define mmPCIE_BMON_MSTR_WR_BASE 0x6C07000ull
+#define PCIE_BMON_MSTR_WR_MAX_OFFSET 0x1000
+#define PCIE_BMON_MSTR_WR_SECTION 0x1000
+#define mmPCIE_BMON_MSTR_RD_BASE 0x6C08000ull
+#define PCIE_BMON_MSTR_RD_MAX_OFFSET 0x1000
+#define PCIE_BMON_MSTR_RD_SECTION 0x1000
+#define mmPCIE_BMON_SLV_WR_BASE 0x6C09000ull
+#define PCIE_BMON_SLV_WR_MAX_OFFSET 0x1000
+#define PCIE_BMON_SLV_WR_SECTION 0x1000
+#define mmPCIE_BMON_SLV_RD_BASE 0x6C0A000ull
+#define PCIE_BMON_SLV_RD_MAX_OFFSET 0x1000
+#define PCIE_BMON_SLV_RD_SECTION 0x36000
+#define mmTOP_ROM_TABLE_BASE 0x6C40000ull
+#define TOP_ROM_TABLE_MAX_OFFSET 0x1000
+#define TOP_ROM_TABLE_SECTION 0x1000
+#define mmPSOC_CTI_BASE 0x6C41000ull
+#define PSOC_CTI_MAX_OFFSET 0x1000
+#define PSOC_CTI_SECTION 0x1000
+#define mmPSOC_STM_BASE 0x6C42000ull
+#define PSOC_STM_MAX_OFFSET 0x1000
+#define PSOC_STM_SECTION 0x1000
+#define mmPSOC_FUNNEL_BASE 0x6C43000ull
+#define PSOC_FUNNEL_MAX_OFFSET 0x1000
+#define PSOC_FUNNEL_SECTION 0x1000
+#define mmPSOC_ETR_BASE 0x6C44000ull
+#define PSOC_ETR_MAX_OFFSET 0x1000
+#define PSOC_ETR_SECTION 0x1000
+#define mmPSOC_ETF_BASE 0x6C45000ull
+#define PSOC_ETF_MAX_OFFSET 0x1000
+#define PSOC_ETF_SECTION 0x1000
+#define mmPSOC_TS_CTI_BASE 0x6C46000ull
+#define PSOC_TS_CTI_MAX_OFFSET 0x1000
+#define PSOC_TS_CTI_SECTION 0xA000
+#define mmPSOC_ARC0_CS_DBG_ROM_TBL_BASE 0x6C50000ull
+#define PSOC_ARC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define PSOC_ARC0_CS_DBG_ROM_TBL_SECTION 0x1000
+#define mmPSOC_ARC0_CS_STM_BASE 0x6C51000ull
+#define PSOC_ARC0_CS_STM_MAX_OFFSET 0x1000
+#define PSOC_ARC0_CS_STM_SECTION 0x1000
+#define mmPSOC_ARC0_CS_CTI_BASE 0x6C52000ull
+#define PSOC_ARC0_CS_CTI_MAX_OFFSET 0x1000
+#define PSOC_ARC0_CS_CTI_SECTION 0x1000
+#define mmPSOC_ARC0_CS_ETF_BASE 0x6C53000ull
+#define PSOC_ARC0_CS_ETF_MAX_OFFSET 0x1000
+#define PSOC_ARC0_CS_ETF_SECTION 0x1000
+#define mmPSOC_ARC0_CS_SPMU_BASE 0x6C54000ull
+#define PSOC_ARC0_CS_SPMU_MAX_OFFSET 0x1000
+#define PSOC_ARC0_CS_SPMU_SECTION 0x1000
+#define mmPSOC_ARC0_BMON_CTI_BASE 0x6C55000ull
+#define PSOC_ARC0_BMON_CTI_MAX_OFFSET 0x1000
+#define PSOC_ARC0_BMON_CTI_SECTION 0x1000
+#define mmPSOC_ARC0_USER_CTI_BASE 0x6C56000ull
+#define PSOC_ARC0_USER_CTI_MAX_OFFSET 0x1000
+#define PSOC_ARC0_USER_CTI_SECTION 0x1000
+#define mmPSOC_ARC0_BMON_0_BASE 0x6C57000ull
+#define PSOC_ARC0_BMON_0_MAX_OFFSET 0x1000
+#define PSOC_ARC0_BMON_0_SECTION 0x1000
+#define mmPSOC_ARC0_BMON_1_BASE 0x6C58000ull
+#define PSOC_ARC0_BMON_1_MAX_OFFSET 0x1000
+#define PSOC_ARC0_BMON_1_SECTION 0x6000
+#define mmPSOC_ARC0_RTT_BASE 0x6C5E000ull
+#define PSOC_ARC0_RTT_MAX_OFFSET 0x1400
+#define PSOC_ARC0_RTT_SECTION 0x1000
+#define mmPSOC_ARC0_FUNNEL_BASE 0x6C5F000ull
+#define PSOC_ARC0_FUNNEL_MAX_OFFSET 0x1000
+#define PSOC_ARC0_FUNNEL_SECTION 0x1000
+#define mmPSOC_ARC1_CS_DBG_ROM_TBL_BASE 0x6C60000ull
+#define PSOC_ARC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define PSOC_ARC1_CS_DBG_ROM_TBL_SECTION 0x1000
+#define mmPSOC_ARC1_CS_STM_BASE 0x6C61000ull
+#define PSOC_ARC1_CS_STM_MAX_OFFSET 0x1000
+#define PSOC_ARC1_CS_STM_SECTION 0x1000
+#define mmPSOC_ARC1_CS_CTI_BASE 0x6C62000ull
+#define PSOC_ARC1_CS_CTI_MAX_OFFSET 0x1000
+#define PSOC_ARC1_CS_CTI_SECTION 0x1000
+#define mmPSOC_ARC1_CS_ETF_BASE 0x6C63000ull
+#define PSOC_ARC1_CS_ETF_MAX_OFFSET 0x1000
+#define PSOC_ARC1_CS_ETF_SECTION 0x1000
+#define mmPSOC_ARC1_CS_SPMU_BASE 0x6C64000ull
+#define PSOC_ARC1_CS_SPMU_MAX_OFFSET 0x1000
+#define PSOC_ARC1_CS_SPMU_SECTION 0x1000
+#define mmPSOC_ARC1_BMON_CTI_BASE 0x6C65000ull
+#define PSOC_ARC1_BMON_CTI_MAX_OFFSET 0x1000
+#define PSOC_ARC1_BMON_CTI_SECTION 0x1000
+#define mmPSOC_ARC1_USER_CTI_BASE 0x6C66000ull
+#define PSOC_ARC1_USER_CTI_MAX_OFFSET 0x1000
+#define PSOC_ARC1_USER_CTI_SECTION 0x1000
+#define mmPSOC_ARC1_BMON_0_BASE 0x6C67000ull
+#define PSOC_ARC1_BMON_0_MAX_OFFSET 0x1000
+#define PSOC_ARC1_BMON_0_SECTION 0x1000
+#define mmPSOC_ARC1_BMON_1_BASE 0x6C68000ull
+#define PSOC_ARC1_BMON_1_MAX_OFFSET 0x1000
+#define PSOC_ARC1_BMON_1_SECTION 0x6000
+#define mmPSOC_ARC1_RTT_BASE 0x6C6E000ull
+#define PSOC_ARC1_RTT_MAX_OFFSET 0x1400
+#define PSOC_ARC1_RTT_SECTION 0x1000
+#define mmPSOC_ARC1_FUNNEL_BASE 0x6C6F000ull
+#define PSOC_ARC1_FUNNEL_MAX_OFFSET 0x1000
+#define PSOC_ARC1_FUNNEL_SECTION 0x1000
+#define mmPSOC_ARC0_CTI0_BASE 0x6C70000ull
+#define PSOC_ARC0_CTI0_MAX_OFFSET 0x1000
+#define PSOC_ARC0_CTI0_SECTION 0x1000
+#define mmPSOC_ARC0_CTI1_BASE 0x6C71000ull
+#define PSOC_ARC0_CTI1_MAX_OFFSET 0x1000
+#define PSOC_ARC0_CTI1_SECTION 0x1000
+#define mmPSOC_ARC0_CTI2_BASE 0x6C72000ull
+#define PSOC_ARC0_CTI2_MAX_OFFSET 0x1000
+#define PSOC_ARC0_CTI2_SECTION 0x1000
+#define mmPSOC_ARC0_CTI3_BASE 0x6C73000ull
+#define PSOC_ARC0_CTI3_MAX_OFFSET 0x1000
+#define PSOC_ARC0_CTI3_SECTION 0x1000
+#define mmPSOC_ARC1_CTI0_BASE 0x6C74000ull
+#define PSOC_ARC1_CTI0_MAX_OFFSET 0x1000
+#define PSOC_ARC1_CTI0_SECTION 0x1000
+#define mmPSOC_ARC1_CTI1_BASE 0x6C75000ull
+#define PSOC_ARC1_CTI1_MAX_OFFSET 0x1000
+#define PSOC_ARC1_CTI1_SECTION 0x1000
+#define mmPSOC_ARC1_CTI2_BASE 0x6C76000ull
+#define PSOC_ARC1_CTI2_MAX_OFFSET 0x1000
+#define PSOC_ARC1_CTI2_SECTION 0x1000
+#define mmPSOC_ARC1_CTI3_BASE 0x6C77000ull
+#define PSOC_ARC1_CTI3_MAX_OFFSET 0x1000
+#define PSOC_ARC1_CTI3_SECTION 0x9000
+#define mmPDMA0_CS_ROM_TBL_BASE 0x6C80000ull
+#define PDMA0_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define PDMA0_CS_ROM_TBL_SECTION 0x1000
+#define mmPDMA0_CS_STM_BASE 0x6C81000ull
+#define PDMA0_CS_STM_MAX_OFFSET 0x1000
+#define PDMA0_CS_STM_SECTION 0x1000
+#define mmPDMA0_CS_CTI_BASE 0x6C82000ull
+#define PDMA0_CS_CTI_MAX_OFFSET 0x1000
+#define PDMA0_CS_CTI_SECTION 0x1000
+#define mmPDMA0_CS_ETF_BASE 0x6C83000ull
+#define PDMA0_CS_ETF_MAX_OFFSET 0x1000
+#define PDMA0_CS_ETF_SECTION 0x1000
+#define mmPDMA0_CS_SPMU_BASE 0x6C84000ull
+#define PDMA0_CS_SPMU_MAX_OFFSET 0x1000
+#define PDMA0_CS_SPMU_SECTION 0x1000
+#define mmPDMA0_BMON_CTI_BASE 0x6C85000ull
+#define PDMA0_BMON_CTI_MAX_OFFSET 0x1000
+#define PDMA0_BMON_CTI_SECTION 0x1000
+#define mmPDMA0_USER_CTI_BASE 0x6C86000ull
+#define PDMA0_USER_CTI_MAX_OFFSET 0x1000
+#define PDMA0_USER_CTI_SECTION 0x1000
+#define mmPDMA0_BMON_0_BASE 0x6C87000ull
+#define PDMA0_BMON_0_MAX_OFFSET 0x1000
+#define PDMA0_BMON_0_SECTION 0x1000
+#define mmPDMA0_BMON_1_BASE 0x6C88000ull
+#define PDMA0_BMON_1_MAX_OFFSET 0x1000
+#define PDMA0_BMON_1_SECTION 0x1000
+#define mmPDMA0_QM_ARC_RTT_BASE 0x6C89000ull
+#define PDMA0_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define PDMA0_QM_ARC_RTT_SECTION 0x7000
+#define mmPDMA1_CS_ROM_TBL_BASE 0x6C90000ull
+#define PDMA1_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define PDMA1_CS_ROM_TBL_SECTION 0x1000
+#define mmPDMA1_CS_STM_BASE 0x6C91000ull
+#define PDMA1_CS_STM_MAX_OFFSET 0x1000
+#define PDMA1_CS_STM_SECTION 0x1000
+#define mmPDMA1_CS_CTI_BASE 0x6C92000ull
+#define PDMA1_CS_CTI_MAX_OFFSET 0x1000
+#define PDMA1_CS_CTI_SECTION 0x1000
+#define mmPDMA1_CS_ETF_BASE 0x6C93000ull
+#define PDMA1_CS_ETF_MAX_OFFSET 0x1000
+#define PDMA1_CS_ETF_SECTION 0x1000
+#define mmPDMA1_CS_SPMU_BASE 0x6C94000ull
+#define PDMA1_CS_SPMU_MAX_OFFSET 0x1000
+#define PDMA1_CS_SPMU_SECTION 0x1000
+#define mmPDMA1_BMON_CTI_BASE 0x6C95000ull
+#define PDMA1_BMON_CTI_MAX_OFFSET 0x1000
+#define PDMA1_BMON_CTI_SECTION 0x1000
+#define mmPDMA1_USER_CTI_BASE 0x6C96000ull
+#define PDMA1_USER_CTI_MAX_OFFSET 0x1000
+#define PDMA1_USER_CTI_SECTION 0x1000
+#define mmPDMA1_BMON_0_BASE 0x6C97000ull
+#define PDMA1_BMON_0_MAX_OFFSET 0x1000
+#define PDMA1_BMON_0_SECTION 0x1000
+#define mmPDMA1_BMON_1_BASE 0x6C98000ull
+#define PDMA1_BMON_1_MAX_OFFSET 0x1000
+#define PDMA1_BMON_1_SECTION 0x1000
+#define mmPDMA1_QM_ARC_RTT_BASE 0x6C99000ull
+#define PDMA1_QM_ARC_RTT_MAX_OFFSET 0x1400
+#define PDMA1_QM_ARC_RTT_SECTION 0x7000
+#define mmXDMA_FUNNEL_BASE 0x6CA0000ull
+#define XDMA_FUNNEL_MAX_OFFSET 0x1000
+#define XDMA_FUNNEL_SECTION 0x21000
+#define mmCPU_ETF_0_BASE 0x6CC1000ull
+#define CPU_ETF_0_MAX_OFFSET 0x1000
+#define CPU_ETF_0_SECTION 0x1000
+#define mmCPU_ETF_1_BASE 0x6CC2000ull
+#define CPU_ETF_1_MAX_OFFSET 0x1000
+#define CPU_ETF_1_SECTION 0x2000
+#define mmCPU_CTI_BASE 0x6CC4000ull
+#define CPU_CTI_MAX_OFFSET 0x1000
+#define CPU_CTI_SECTION 0x1000
+#define mmCPU_FUNNEL_BASE 0x6CC5000ull
+#define CPU_FUNNEL_MAX_OFFSET 0x1000
+#define CPU_FUNNEL_SECTION 0x1000
+#define mmCPU_STM_BASE 0x6CC6000ull
+#define CPU_STM_MAX_OFFSET 0x1000
+#define CPU_STM_SECTION 0x1000
+#define mmCPU_CTI_TRACE_BASE 0x6CC7000ull
+#define CPU_CTI_TRACE_MAX_OFFSET 0x1000
+#define CPU_CTI_TRACE_SECTION 0x1000
+#define mmCPU_ETF_TRACE_BASE 0x6CC8000ull
+#define CPU_ETF_TRACE_MAX_OFFSET 0x1000
+#define CPU_ETF_TRACE_SECTION 0x1000
+#define mmCPU_WR_BMON_BASE 0x6CC9000ull
+#define CPU_WR_BMON_MAX_OFFSET 0x1000
+#define CPU_WR_BMON_SECTION 0x1000
+#define mmCPU_RD_BMON_BASE 0x6CCA000ull
+#define CPU_RD_BMON_MAX_OFFSET 0x1000
+#define CPU_RD_BMON_SECTION 0x36000
+#define mmPMMU_CS_DBG_ROM_TBL_BASE 0x6D00000ull
+#define PMMU_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define PMMU_CS_DBG_ROM_TBL_SECTION 0x1000
+#define mmPMMU_CS_STM_BASE 0x6D01000ull
+#define PMMU_CS_STM_MAX_OFFSET 0x1000
+#define PMMU_CS_STM_SECTION 0x1000
+#define mmPMMU_CS_CTI_BASE 0x6D02000ull
+#define PMMU_CS_CTI_MAX_OFFSET 0x1000
+#define PMMU_CS_CTI_SECTION 0x1000
+#define mmPMMU_CS_ETF_BASE 0x6D03000ull
+#define PMMU_CS_ETF_MAX_OFFSET 0x1000
+#define PMMU_CS_ETF_SECTION 0x1000
+#define mmPMMU_CS_SPMU_BASE 0x6D04000ull
+#define PMMU_CS_SPMU_MAX_OFFSET 0x1000
+#define PMMU_CS_SPMU_SECTION 0x1000
+#define mmPMMU_BMON_CTI_BASE 0x6D05000ull
+#define PMMU_BMON_CTI_MAX_OFFSET 0x1000
+#define PMMU_BMON_CTI_SECTION 0x1000
+#define mmPMMU_USER_CTI_BASE 0x6D06000ull
+#define PMMU_USER_CTI_MAX_OFFSET 0x1000
+#define PMMU_USER_CTI_SECTION 0x1000
+#define mmPMMU_BMON_0_BASE 0x6D07000ull
+#define PMMU_BMON_0_MAX_OFFSET 0x1000
+#define PMMU_BMON_0_SECTION 0x1000
+#define mmPMMU_BMON_1_BASE 0x6D08000ull
+#define PMMU_BMON_1_MAX_OFFSET 0x1000
+#define PMMU_BMON_1_SECTION 0x1000
+#define mmPMMU_BMON_2_BASE 0x6D09000ull
+#define PMMU_BMON_2_MAX_OFFSET 0x1000
+#define PMMU_BMON_2_SECTION 0x1000
+#define mmPMMU_BMON_3_BASE 0x6D0A000ull
+#define PMMU_BMON_3_MAX_OFFSET 0x1000
+#define PMMU_BMON_3_SECTION 0x1000
+#define mmPMMU_BMON_4_BASE 0x6D0B000ull
+#define PMMU_BMON_4_MAX_OFFSET 0x1000
+#define PMMU_BMON_4_SECTION 0x1000
+#define mmPMMU_FUNNEL_BASE 0x6D0C000ull
+#define PMMU_FUNNEL_MAX_OFFSET 0x1000
+#define PMMU_FUNNEL_SECTION 0x1000
+#define mmPMMU_FUNNEL_DEC_BASE 0x6D0D000ull
+#define PMMU_FUNNEL_DEC_MAX_OFFSET 0x1000
+#define PMMU_FUNNEL_DEC_SECTION 0x33000
+#define mmDCORE0_XBAR_MID_FUNNEL_BASE 0x6D40000ull
+#define DCORE0_XBAR_MID_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_XBAR_MID_FUNNEL_SECTION 0x8000
+#define mmDCORE0_XBAR_EDGE_FUNNEL_BASE 0x6D48000ull
+#define DCORE0_XBAR_EDGE_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE0_XBAR_EDGE_FUNNEL_SECTION 0x8000
+#define mmDCORE1_XBAR_MID_FUNNEL_BASE 0x6D50000ull
+#define DCORE1_XBAR_MID_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_XBAR_MID_FUNNEL_SECTION 0x8000
+#define mmDCORE1_XBAR_EDGE_FUNNEL_BASE 0x6D58000ull
+#define DCORE1_XBAR_EDGE_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE1_XBAR_EDGE_FUNNEL_SECTION 0x8000
+#define mmDCORE2_XBAR_MID_FUNNEL_BASE 0x6D60000ull
+#define DCORE2_XBAR_MID_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_XBAR_MID_FUNNEL_SECTION 0x8000
+#define mmDCORE2_XBAR_EDGE_FUNNEL_BASE 0x6D68000ull
+#define DCORE2_XBAR_EDGE_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE2_XBAR_EDGE_FUNNEL_SECTION 0x8000
+#define mmDCORE3_XBAR_MID_FUNNEL_BASE 0x6D70000ull
+#define DCORE3_XBAR_MID_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_XBAR_MID_FUNNEL_SECTION 0x8000
+#define mmDCORE3_XBAR_EDGE_FUNNEL_BASE 0x6D78000ull
+#define DCORE3_XBAR_EDGE_FUNNEL_MAX_OFFSET 0x1000
+#define DCORE3_XBAR_EDGE_FUNNEL_SECTION 0x88000
+#define mmROT0_CS_ROM_TBL_BASE 0x6E00000ull
+#define ROT0_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define ROT0_CS_ROM_TBL_SECTION 0x1000
+#define mmROT0_CS_STM_BASE 0x6E01000ull
+#define ROT0_CS_STM_MAX_OFFSET 0x1000
+#define ROT0_CS_STM_SECTION 0x1000
+#define mmROT0_CS_CTI_BASE 0x6E02000ull
+#define ROT0_CS_CTI_MAX_OFFSET 0x1000
+#define ROT0_CS_CTI_SECTION 0x1000
+#define mmROT0_CS_ETF_BASE 0x6E03000ull
+#define ROT0_CS_ETF_MAX_OFFSET 0x1000
+#define ROT0_CS_ETF_SECTION 0x1000
+#define mmROT0_CS_SPMU_BASE 0x6E04000ull
+#define ROT0_CS_SPMU_MAX_OFFSET 0x1000
+#define ROT0_CS_SPMU_SECTION 0x1000
+#define mmROT0_BMON_CTI_BASE 0x6E05000ull
+#define ROT0_BMON_CTI_MAX_OFFSET 0x1000
+#define ROT0_BMON_CTI_SECTION 0x1000
+#define mmROT0_USER_CTI_BASE 0x6E06000ull
+#define ROT0_USER_CTI_MAX_OFFSET 0x1000
+#define ROT0_USER_CTI_SECTION 0x1000
+#define mmROT0_BMON_0_BASE 0x6E07000ull
+#define ROT0_BMON_0_MAX_OFFSET 0x1000
+#define ROT0_BMON_0_SECTION 0x1000
+#define mmROT0_BMON_1_BASE 0x6E08000ull
+#define ROT0_BMON_1_MAX_OFFSET 0x1000
+#define ROT0_BMON_1_SECTION 0x1000
+#define mmROT0_BMON_2_BASE 0x6E09000ull
+#define ROT0_BMON_2_MAX_OFFSET 0x1000
+#define ROT0_BMON_2_SECTION 0x1000
+#define mmROT0_BMON_3_BASE 0x6E0A000ull
+#define ROT0_BMON_3_MAX_OFFSET 0x1000
+#define ROT0_BMON_3_SECTION 0x1000
+#define mmROT0_ARC_RTT_BASE 0x6E0B000ull
+#define ROT0_ARC_RTT_MAX_OFFSET 0x1400
+#define ROT0_ARC_RTT_SECTION 0x5000
+#define mmROT1_CS_ROM_TBL_BASE 0x6E10000ull
+#define ROT1_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define ROT1_CS_ROM_TBL_SECTION 0x1000
+#define mmROT1_CS_STM_BASE 0x6E11000ull
+#define ROT1_CS_STM_MAX_OFFSET 0x1000
+#define ROT1_CS_STM_SECTION 0x1000
+#define mmROT1_CS_CTI_BASE 0x6E12000ull
+#define ROT1_CS_CTI_MAX_OFFSET 0x1000
+#define ROT1_CS_CTI_SECTION 0x1000
+#define mmROT1_CS_ETF_BASE 0x6E13000ull
+#define ROT1_CS_ETF_MAX_OFFSET 0x1000
+#define ROT1_CS_ETF_SECTION 0x1000
+#define mmROT1_CS_SPMU_BASE 0x6E14000ull
+#define ROT1_CS_SPMU_MAX_OFFSET 0x1000
+#define ROT1_CS_SPMU_SECTION 0x1000
+#define mmROT1_BMON_CTI_BASE 0x6E15000ull
+#define ROT1_BMON_CTI_MAX_OFFSET 0x1000
+#define ROT1_BMON_CTI_SECTION 0x1000
+#define mmROT1_USER_CTI_BASE 0x6E16000ull
+#define ROT1_USER_CTI_MAX_OFFSET 0x1000
+#define ROT1_USER_CTI_SECTION 0x1000
+#define mmROT1_BMON_0_BASE 0x6E17000ull
+#define ROT1_BMON_0_MAX_OFFSET 0x1000
+#define ROT1_BMON_0_SECTION 0x1000
+#define mmROT1_BMON_1_BASE 0x6E18000ull
+#define ROT1_BMON_1_MAX_OFFSET 0x1000
+#define ROT1_BMON_1_SECTION 0x1000
+#define mmROT1_BMON_2_BASE 0x6E19000ull
+#define ROT1_BMON_2_MAX_OFFSET 0x1000
+#define ROT1_BMON_2_SECTION 0x1000
+#define mmROT1_BMON_3_BASE 0x6E1A000ull
+#define ROT1_BMON_3_MAX_OFFSET 0x1000
+#define ROT1_BMON_3_SECTION 0x1000
+#define mmROT1_ARC_RTT_BASE 0x6E1B000ull
+#define ROT1_ARC_RTT_MAX_OFFSET 0x1400
+#define ROT1_ARC_RTT_SECTION 0x65000
+#define mmARC_FARM_ARC0_RTT_BASE 0x6E80000ull
+#define ARC_FARM_ARC0_RTT_MAX_OFFSET 0x1400
+#define ARC_FARM_ARC0_RTT_SECTION 0x1000
+#define mmARC_FARM_ARC1_RTT_BASE 0x6E81000ull
+#define ARC_FARM_ARC1_RTT_MAX_OFFSET 0x1400
+#define ARC_FARM_ARC1_RTT_SECTION 0x1000
+#define mmARC_FARM_ARC2_RTT_BASE 0x6E82000ull
+#define ARC_FARM_ARC2_RTT_MAX_OFFSET 0x1400
+#define ARC_FARM_ARC2_RTT_SECTION 0x1000
+#define mmARC_FARM_ARC3_RTT_BASE 0x6E83000ull
+#define ARC_FARM_ARC3_RTT_MAX_OFFSET 0x1400
+#define ARC_FARM_ARC3_RTT_SECTION 0xD000
+#define mmARC_FARM_CS_ROM_TBL_BASE 0x6E90000ull
+#define ARC_FARM_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define ARC_FARM_CS_ROM_TBL_SECTION 0x1000
+#define mmARC_FARM_CS_STM_BASE 0x6E91000ull
+#define ARC_FARM_CS_STM_MAX_OFFSET 0x1000
+#define ARC_FARM_CS_STM_SECTION 0x1000
+#define mmARC_FARM_CS_CTI_BASE 0x6E92000ull
+#define ARC_FARM_CS_CTI_MAX_OFFSET 0x1000
+#define ARC_FARM_CS_CTI_SECTION 0x1000
+#define mmARC_FARM_CS_ETF_BASE 0x6E93000ull
+#define ARC_FARM_CS_ETF_MAX_OFFSET 0x1000
+#define ARC_FARM_CS_ETF_SECTION 0x1000
+#define mmARC_FARM_CS_SPMU_BASE 0x6E94000ull
+#define ARC_FARM_CS_SPMU_MAX_OFFSET 0x1000
+#define ARC_FARM_CS_SPMU_SECTION 0x1000
+#define mmARC_FARM_BMON_CTI_BASE 0x6E95000ull
+#define ARC_FARM_BMON_CTI_MAX_OFFSET 0x1000
+#define ARC_FARM_BMON_CTI_SECTION 0x1000
+#define mmARC_FARM_USER_CTI_BASE 0x6E96000ull
+#define ARC_FARM_USER_CTI_MAX_OFFSET 0x1000
+#define ARC_FARM_USER_CTI_SECTION 0x1000
+#define mmARC_FARM_BMON_0_BASE 0x6E97000ull
+#define ARC_FARM_BMON_0_MAX_OFFSET 0x1000
+#define ARC_FARM_BMON_0_SECTION 0x1000
+#define mmARC_FARM_BMON_1_BASE 0x6E98000ull
+#define ARC_FARM_BMON_1_MAX_OFFSET 0x1000
+#define ARC_FARM_BMON_1_SECTION 0x1000
+#define mmARC_FARM_BMON_2_BASE 0x6E99000ull
+#define ARC_FARM_BMON_2_MAX_OFFSET 0x1000
+#define ARC_FARM_BMON_2_SECTION 0x1000
+#define mmARC_FARM_BMON_3_BASE 0x6E9A000ull
+#define ARC_FARM_BMON_3_MAX_OFFSET 0x1000
+#define ARC_FARM_BMON_3_SECTION 0x1000
+#define mmARC_FARM_CTI_BASE 0x6E9B000ull
+#define ARC_FARM_CTI_MAX_OFFSET 0x1000
+#define ARC_FARM_CTI_SECTION 0x1000
+#define mmARC_FARM_FUNNEL_BASE 0x6E9C000ull
+#define ARC_FARM_FUNNEL_MAX_OFFSET 0x1000
+#define ARC_FARM_FUNNEL_SECTION 0x4000
+#define mmKDMA_CS_ROM_TBL_BASE 0x6EA0000ull
+#define KDMA_CS_ROM_TBL_MAX_OFFSET 0x1000
+#define KDMA_CS_ROM_TBL_SECTION 0x1000
+#define mmKDMA_CS_STM_BASE 0x6EA1000ull
+#define KDMA_CS_STM_MAX_OFFSET 0x1000
+#define KDMA_CS_STM_SECTION 0x1000
+#define mmKDMA_CS_CTI_BASE 0x6EA2000ull
+#define KDMA_CS_CTI_MAX_OFFSET 0x1000
+#define KDMA_CS_CTI_SECTION 0x1000
+#define mmKDMA_CS_ETF_BASE 0x6EA3000ull
+#define KDMA_CS_ETF_MAX_OFFSET 0x1000
+#define KDMA_CS_ETF_SECTION 0x1000
+#define mmKDMA_CS_SPMU_BASE 0x6EA4000ull
+#define KDMA_CS_SPMU_MAX_OFFSET 0x1000
+#define KDMA_CS_SPMU_SECTION 0x1000
+#define mmKDMA_BMON_CTI_BASE 0x6EA5000ull
+#define KDMA_BMON_CTI_MAX_OFFSET 0x1000
+#define KDMA_BMON_CTI_SECTION 0x1000
+#define mmKDMA_USER_CTI_BASE 0x6EA6000ull
+#define KDMA_USER_CTI_MAX_OFFSET 0x1000
+#define KDMA_USER_CTI_SECTION 0x1000
+#define mmKDMA_BMON_0_BASE 0x6EA7000ull
+#define KDMA_BMON_0_MAX_OFFSET 0x1000
+#define KDMA_BMON_0_SECTION 0x1000
+#define mmKDMA_BMON_1_BASE 0x6EA8000ull
+#define KDMA_BMON_1_MAX_OFFSET 0x1000
+#define KDMA_BMON_1_SECTION 0x1000
+#define mmKDMA_BMON_2_BASE 0x6EA9000ull
+#define KDMA_BMON_2_MAX_OFFSET 0x1000
+#define KDMA_BMON_2_SECTION 0x1000
+#define mmKDMA_BMON_3_BASE 0x6EAA000ull
+#define KDMA_BMON_3_MAX_OFFSET 0x1000
+#define KDMA_BMON_3_SECTION 0x56000
+#define mmPCIE_VDEC0_CS_DBG_ROM_TBL_BASE 0x6F00000ull
+#define PCIE_VDEC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define PCIE_VDEC0_CS_DBG_ROM_TBL_SECTION 0x1000
+#define mmPCIE_VDEC0_CS_STM_BASE 0x6F01000ull
+#define PCIE_VDEC0_CS_STM_MAX_OFFSET 0x1000
+#define PCIE_VDEC0_CS_STM_SECTION 0x1000
+#define mmPCIE_VDEC0_CS_CTI_BASE 0x6F02000ull
+#define PCIE_VDEC0_CS_CTI_MAX_OFFSET 0x1000
+#define PCIE_VDEC0_CS_CTI_SECTION 0x1000
+#define mmPCIE_VDEC0_CS_ETF_BASE 0x6F03000ull
+#define PCIE_VDEC0_CS_ETF_MAX_OFFSET 0x1000
+#define PCIE_VDEC0_CS_ETF_SECTION 0x1000
+#define mmPCIE_VDEC0_CS_SPMU_BASE 0x6F04000ull
+#define PCIE_VDEC0_CS_SPMU_MAX_OFFSET 0x1000
+#define PCIE_VDEC0_CS_SPMU_SECTION 0x1000
+#define mmPCIE_VDEC0_BMON_CTI_BASE 0x6F05000ull
+#define PCIE_VDEC0_BMON_CTI_MAX_OFFSET 0x1000
+#define PCIE_VDEC0_BMON_CTI_SECTION 0x1000
+#define mmPCIE_VDEC0_USER_CTI_BASE 0x6F06000ull
+#define PCIE_VDEC0_USER_CTI_MAX_OFFSET 0x1000
+#define PCIE_VDEC0_USER_CTI_SECTION 0x1000
+#define mmPCIE_VDEC0_BMON_0_BASE 0x6F07000ull
+#define PCIE_VDEC0_BMON_0_MAX_OFFSET 0x1000
+#define PCIE_VDEC0_BMON_0_SECTION 0x1000
+#define mmPCIE_VDEC0_BMON_1_BASE 0x6F08000ull
+#define PCIE_VDEC0_BMON_1_MAX_OFFSET 0x1000
+#define PCIE_VDEC0_BMON_1_SECTION 0x1000
+#define mmPCIE_VDEC0_BMON_2_BASE 0x6F09000ull
+#define PCIE_VDEC0_BMON_2_MAX_OFFSET 0x1000
+#define PCIE_VDEC0_BMON_2_SECTION 0x7000
+#define mmPCIE_VDEC1_CS_DBG_ROM_TBL_BASE 0x6F10000ull
+#define PCIE_VDEC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define PCIE_VDEC1_CS_DBG_ROM_TBL_SECTION 0x1000
+#define mmPCIE_VDEC1_CS_STM_BASE 0x6F11000ull
+#define PCIE_VDEC1_CS_STM_MAX_OFFSET 0x1000
+#define PCIE_VDEC1_CS_STM_SECTION 0x1000
+#define mmPCIE_VDEC1_CS_CTI_BASE 0x6F12000ull
+#define PCIE_VDEC1_CS_CTI_MAX_OFFSET 0x1000
+#define PCIE_VDEC1_CS_CTI_SECTION 0x1000
+#define mmPCIE_VDEC1_CS_ETF_BASE 0x6F13000ull
+#define PCIE_VDEC1_CS_ETF_MAX_OFFSET 0x1000
+#define PCIE_VDEC1_CS_ETF_SECTION 0x1000
+#define mmPCIE_VDEC1_CS_SPMU_BASE 0x6F14000ull
+#define PCIE_VDEC1_CS_SPMU_MAX_OFFSET 0x1000
+#define PCIE_VDEC1_CS_SPMU_SECTION 0x1000
+#define mmPCIE_VDEC1_BMON_CTI_BASE 0x6F15000ull
+#define PCIE_VDEC1_BMON_CTI_MAX_OFFSET 0x1000
+#define PCIE_VDEC1_BMON_CTI_SECTION 0x1000
+#define mmPCIE_VDEC1_USER_CTI_BASE 0x6F16000ull
+#define PCIE_VDEC1_USER_CTI_MAX_OFFSET 0x1000
+#define PCIE_VDEC1_USER_CTI_SECTION 0x1000
+#define mmPCIE_VDEC1_BMON_0_BASE 0x6F17000ull
+#define PCIE_VDEC1_BMON_0_MAX_OFFSET 0x1000
+#define PCIE_VDEC1_BMON_0_SECTION 0x1000
+#define mmPCIE_VDEC1_BMON_1_BASE 0x6F18000ull
+#define PCIE_VDEC1_BMON_1_MAX_OFFSET 0x1000
+#define PCIE_VDEC1_BMON_1_SECTION 0x1000
+#define mmPCIE_VDEC1_BMON_2_BASE 0x6F19000ull
+#define PCIE_VDEC1_BMON_2_MAX_OFFSET 0x1000
+#define PCIE_VDEC1_BMON_2_SECTION 0xF7000
+#define mmHBM0_MC0_CS_DBG_ROM_TBL_BASE 0x7010000ull
+#define HBM0_MC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define HBM0_MC0_CS_DBG_ROM_TBL_SECTION 0x1000
+#define mmHBM0_MC0_CS_STM_BASE 0x7011000ull
+#define HBM0_MC0_CS_STM_MAX_OFFSET 0x1000
+#define HBM0_MC0_CS_STM_SECTION 0x1000
+#define mmHBM0_MC0_CS_CTI_BASE 0x7012000ull
+#define HBM0_MC0_CS_CTI_MAX_OFFSET 0x1000
+#define HBM0_MC0_CS_CTI_SECTION 0x1000
+#define mmHBM0_MC0_CS_ETF_BASE 0x7013000ull
+#define HBM0_MC0_CS_ETF_MAX_OFFSET 0x1000
+#define HBM0_MC0_CS_ETF_SECTION 0x1000
+#define mmHBM0_MC0_CS_SPMU_BASE 0x7014000ull
+#define HBM0_MC0_CS_SPMU_MAX_OFFSET 0x1000
+#define HBM0_MC0_CS_SPMU_SECTION 0x1000
+#define mmHBM0_MC0_BMON_CTI_BASE 0x7015000ull
+#define HBM0_MC0_BMON_CTI_MAX_OFFSET 0x1000
+#define HBM0_MC0_BMON_CTI_SECTION 0x1000
+#define mmHBM0_MC0_USER_CTI_BASE 0x7016000ull
+#define HBM0_MC0_USER_CTI_MAX_OFFSET 0x1000
+#define HBM0_MC0_USER_CTI_SECTION 0xA000
+#define mmHBM0_MC0_FUNNEL_BASE 0x7020000ull
+#define HBM0_MC0_FUNNEL_MAX_OFFSET 0x1000
+#define HBM0_MC0_FUNNEL_SECTION 0x30000
+#define mmHBM0_MC1_CS_DBG_ROM_TBL_BASE 0x7050000ull
+#define HBM0_MC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define HBM0_MC1_CS_DBG_ROM_TBL_SECTION 0x1000
+#define mmHBM0_MC1_CS_STM_BASE 0x7051000ull
+#define HBM0_MC1_CS_STM_MAX_OFFSET 0x1000
+#define HBM0_MC1_CS_STM_SECTION 0x1000
+#define mmHBM0_MC1_CS_CTI_BASE 0x7052000ull
+#define HBM0_MC1_CS_CTI_MAX_OFFSET 0x1000
+#define HBM0_MC1_CS_CTI_SECTION 0x1000
+#define mmHBM0_MC1_CS_ETF_BASE 0x7053000ull
+#define HBM0_MC1_CS_ETF_MAX_OFFSET 0x1000
+#define HBM0_MC1_CS_ETF_SECTION 0x1000
+#define mmHBM0_MC1_CS_SPMU_BASE 0x7054000ull
+#define HBM0_MC1_CS_SPMU_MAX_OFFSET 0x1000
+#define HBM0_MC1_CS_SPMU_SECTION 0x1000
+#define mmHBM0_MC1_BMON_CTI_BASE 0x7055000ull
+#define HBM0_MC1_BMON_CTI_MAX_OFFSET 0x1000
+#define HBM0_MC1_BMON_CTI_SECTION 0x1000
+#define mmHBM0_MC1_USER_CTI_BASE 0x7056000ull
+#define HBM0_MC1_USER_CTI_MAX_OFFSET 0x1000
+#define HBM0_MC1_USER_CTI_SECTION 0xA000
+#define mmHBM0_MC1_FUNNEL_BASE 0x7060000ull
+#define HBM0_MC1_FUNNEL_MAX_OFFSET 0x1000
+#define HBM0_MC1_FUNNEL_SECTION 0x30000
+#define mmHBM1_MC0_CS_DBG_ROM_TBL_BASE 0x7090000ull
+#define HBM1_MC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define HBM1_MC0_CS_DBG_ROM_TBL_SECTION 0x1000
+#define mmHBM1_MC0_CS_STM_BASE 0x7091000ull
+#define HBM1_MC0_CS_STM_MAX_OFFSET 0x1000
+#define HBM1_MC0_CS_STM_SECTION 0x1000
+#define mmHBM1_MC0_CS_CTI_BASE 0x7092000ull
+#define HBM1_MC0_CS_CTI_MAX_OFFSET 0x1000
+#define HBM1_MC0_CS_CTI_SECTION 0x1000
+#define mmHBM1_MC0_CS_ETF_BASE 0x7093000ull
+#define HBM1_MC0_CS_ETF_MAX_OFFSET 0x1000
+#define HBM1_MC0_CS_ETF_SECTION 0x1000
+#define mmHBM1_MC0_CS_SPMU_BASE 0x7094000ull
+#define HBM1_MC0_CS_SPMU_MAX_OFFSET 0x1000
+#define HBM1_MC0_CS_SPMU_SECTION 0x1000
+#define mmHBM1_MC0_BMON_CTI_BASE 0x7095000ull
+#define HBM1_MC0_BMON_CTI_MAX_OFFSET 0x1000
+#define HBM1_MC0_BMON_CTI_SECTION 0x1000
+#define mmHBM1_MC0_USER_CTI_BASE 0x7096000ull
+#define HBM1_MC0_USER_CTI_MAX_OFFSET 0x1000
+#define HBM1_MC0_USER_CTI_SECTION 0xA000
+#define mmHBM1_MC0_FUNNEL_BASE 0x70A0000ull
+#define HBM1_MC0_FUNNEL_MAX_OFFSET 0x1000
+#define HBM1_MC0_FUNNEL_SECTION 0x30000
+#define mmHBM1_MC1_CS_DBG_ROM_TBL_BASE 0x70D0000ull
+#define HBM1_MC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define HBM1_MC1_CS_DBG_ROM_TBL_SECTION 0x1000
+#define mmHBM1_MC1_CS_STM_BASE 0x70D1000ull
+#define HBM1_MC1_CS_STM_MAX_OFFSET 0x1000
+#define HBM1_MC1_CS_STM_SECTION 0x1000
+#define mmHBM1_MC1_CS_CTI_BASE 0x70D2000ull
+#define HBM1_MC1_CS_CTI_MAX_OFFSET 0x1000
+#define HBM1_MC1_CS_CTI_SECTION 0x1000
+#define mmHBM1_MC1_CS_ETF_BASE 0x70D3000ull
+#define HBM1_MC1_CS_ETF_MAX_OFFSET 0x1000
+#define HBM1_MC1_CS_ETF_SECTION 0x1000
+#define mmHBM1_MC1_CS_SPMU_BASE 0x70D4000ull
+#define HBM1_MC1_CS_SPMU_MAX_OFFSET 0x1000
+#define HBM1_MC1_CS_SPMU_SECTION 0x1000
+#define mmHBM1_MC1_BMON_CTI_BASE 0x70D5000ull
+#define HBM1_MC1_BMON_CTI_MAX_OFFSET 0x1000
+#define HBM1_MC1_BMON_CTI_SECTION 0x1000
+#define mmHBM1_MC1_USER_CTI_BASE 0x70D6000ull
+#define HBM1_MC1_USER_CTI_MAX_OFFSET 0x1000
+#define HBM1_MC1_USER_CTI_SECTION 0xA000
+#define mmHBM1_MC1_FUNNEL_BASE 0x70E0000ull
+#define HBM1_MC1_FUNNEL_MAX_OFFSET 0x1000
+#define HBM1_MC1_FUNNEL_SECTION 0x30000
+#define mmHBM2_MC0_CS_DBG_ROM_TBL_BASE 0x7110000ull
+#define HBM2_MC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define HBM2_MC0_CS_DBG_ROM_TBL_SECTION 0x1000
+#define mmHBM2_MC0_CS_STM_BASE 0x7111000ull
+#define HBM2_MC0_CS_STM_MAX_OFFSET 0x1000
+#define HBM2_MC0_CS_STM_SECTION 0x1000
+#define mmHBM2_MC0_CS_CTI_BASE 0x7112000ull
+#define HBM2_MC0_CS_CTI_MAX_OFFSET 0x1000
+#define HBM2_MC0_CS_CTI_SECTION 0x1000
+#define mmHBM2_MC0_CS_ETF_BASE 0x7113000ull
+#define HBM2_MC0_CS_ETF_MAX_OFFSET 0x1000
+#define HBM2_MC0_CS_ETF_SECTION 0x1000
+#define mmHBM2_MC0_CS_SPMU_BASE 0x7114000ull
+#define HBM2_MC0_CS_SPMU_MAX_OFFSET 0x1000
+#define HBM2_MC0_CS_SPMU_SECTION 0x1000
+#define mmHBM2_MC0_BMON_CTI_BASE 0x7115000ull
+#define HBM2_MC0_BMON_CTI_MAX_OFFSET 0x1000
+#define HBM2_MC0_BMON_CTI_SECTION 0x1000
+#define mmHBM2_MC0_USER_CTI_BASE 0x7116000ull
+#define HBM2_MC0_USER_CTI_MAX_OFFSET 0x1000
+#define HBM2_MC0_USER_CTI_SECTION 0xA000
+#define mmHBM2_MC0_FUNNEL_BASE 0x7120000ull
+#define HBM2_MC0_FUNNEL_MAX_OFFSET 0x1000
+#define HBM2_MC0_FUNNEL_SECTION 0x30000
+#define mmHBM2_MC1_CS_DBG_ROM_TBL_BASE 0x7150000ull
+#define HBM2_MC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define HBM2_MC1_CS_DBG_ROM_TBL_SECTION 0x1000
+#define mmHBM2_MC1_CS_STM_BASE 0x7151000ull
+#define HBM2_MC1_CS_STM_MAX_OFFSET 0x1000
+#define HBM2_MC1_CS_STM_SECTION 0x1000
+#define mmHBM2_MC1_CS_CTI_BASE 0x7152000ull
+#define HBM2_MC1_CS_CTI_MAX_OFFSET 0x1000
+#define HBM2_MC1_CS_CTI_SECTION 0x1000
+#define mmHBM2_MC1_CS_ETF_BASE 0x7153000ull
+#define HBM2_MC1_CS_ETF_MAX_OFFSET 0x1000
+#define HBM2_MC1_CS_ETF_SECTION 0x1000
+#define mmHBM2_MC1_CS_SPMU_BASE 0x7154000ull
+#define HBM2_MC1_CS_SPMU_MAX_OFFSET 0x1000
+#define HBM2_MC1_CS_SPMU_SECTION 0x1000
+#define mmHBM2_MC1_BMON_CTI_BASE 0x7155000ull
+#define HBM2_MC1_BMON_CTI_MAX_OFFSET 0x1000
+#define HBM2_MC1_BMON_CTI_SECTION 0x1000
+#define mmHBM2_MC1_USER_CTI_BASE 0x7156000ull
+#define HBM2_MC1_USER_CTI_MAX_OFFSET 0x1000
+#define HBM2_MC1_USER_CTI_SECTION 0xA000
+#define mmHBM2_MC1_FUNNEL_BASE 0x7160000ull
+#define HBM2_MC1_FUNNEL_MAX_OFFSET 0x1000
+#define HBM2_MC1_FUNNEL_SECTION 0x30000
+#define mmHBM3_MC0_CS_DBG_ROM_TBL_BASE 0x7190000ull
+#define HBM3_MC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define HBM3_MC0_CS_DBG_ROM_TBL_SECTION 0x1000
+#define mmHBM3_MC0_CS_STM_BASE 0x7191000ull
+#define HBM3_MC0_CS_STM_MAX_OFFSET 0x1000
+#define HBM3_MC0_CS_STM_SECTION 0x1000
+#define mmHBM3_MC0_CS_CTI_BASE 0x7192000ull
+#define HBM3_MC0_CS_CTI_MAX_OFFSET 0x1000
+#define HBM3_MC0_CS_CTI_SECTION 0x1000
+#define mmHBM3_MC0_CS_ETF_BASE 0x7193000ull
+#define HBM3_MC0_CS_ETF_MAX_OFFSET 0x1000
+#define HBM3_MC0_CS_ETF_SECTION 0x1000
+#define mmHBM3_MC0_CS_SPMU_BASE 0x7194000ull
+#define HBM3_MC0_CS_SPMU_MAX_OFFSET 0x1000
+#define HBM3_MC0_CS_SPMU_SECTION 0x1000
+#define mmHBM3_MC0_BMON_CTI_BASE 0x7195000ull
+#define HBM3_MC0_BMON_CTI_MAX_OFFSET 0x1000
+#define HBM3_MC0_BMON_CTI_SECTION 0x1000
+#define mmHBM3_MC0_USER_CTI_BASE 0x7196000ull
+#define HBM3_MC0_USER_CTI_MAX_OFFSET 0x1000
+#define HBM3_MC0_USER_CTI_SECTION 0xA000
+#define mmHBM3_MC0_FUNNEL_BASE 0x71A0000ull
+#define HBM3_MC0_FUNNEL_MAX_OFFSET 0x1000
+#define HBM3_MC0_FUNNEL_SECTION 0x30000
+#define mmHBM3_MC1_CS_DBG_ROM_TBL_BASE 0x71D0000ull
+#define HBM3_MC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define HBM3_MC1_CS_DBG_ROM_TBL_SECTION 0x1000
+#define mmHBM3_MC1_CS_STM_BASE 0x71D1000ull
+#define HBM3_MC1_CS_STM_MAX_OFFSET 0x1000
+#define HBM3_MC1_CS_STM_SECTION 0x1000
+#define mmHBM3_MC1_CS_CTI_BASE 0x71D2000ull
+#define HBM3_MC1_CS_CTI_MAX_OFFSET 0x1000
+#define HBM3_MC1_CS_CTI_SECTION 0x1000
+#define mmHBM3_MC1_CS_ETF_BASE 0x71D3000ull
+#define HBM3_MC1_CS_ETF_MAX_OFFSET 0x1000
+#define HBM3_MC1_CS_ETF_SECTION 0x1000
+#define mmHBM3_MC1_CS_SPMU_BASE 0x71D4000ull
+#define HBM3_MC1_CS_SPMU_MAX_OFFSET 0x1000
+#define HBM3_MC1_CS_SPMU_SECTION 0x1000
+#define mmHBM3_MC1_BMON_CTI_BASE 0x71D5000ull
+#define HBM3_MC1_BMON_CTI_MAX_OFFSET 0x1000
+#define HBM3_MC1_BMON_CTI_SECTION 0x1000
+#define mmHBM3_MC1_USER_CTI_BASE 0x71D6000ull
+#define HBM3_MC1_USER_CTI_MAX_OFFSET 0x1000
+#define HBM3_MC1_USER_CTI_SECTION 0xA000
+#define mmHBM3_MC1_FUNNEL_BASE 0x71E0000ull
+#define HBM3_MC1_FUNNEL_MAX_OFFSET 0x1000
+#define HBM3_MC1_FUNNEL_SECTION 0x30000
+#define mmHBM4_MC0_CS_DBG_ROM_TBL_BASE 0x7210000ull
+#define HBM4_MC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define HBM4_MC0_CS_DBG_ROM_TBL_SECTION 0x1000
+#define mmHBM4_MC0_CS_STM_BASE 0x7211000ull
+#define HBM4_MC0_CS_STM_MAX_OFFSET 0x1000
+#define HBM4_MC0_CS_STM_SECTION 0x1000
+#define mmHBM4_MC0_CS_CTI_BASE 0x7212000ull
+#define HBM4_MC0_CS_CTI_MAX_OFFSET 0x1000
+#define HBM4_MC0_CS_CTI_SECTION 0x1000
+#define mmHBM4_MC0_CS_ETF_BASE 0x7213000ull
+#define HBM4_MC0_CS_ETF_MAX_OFFSET 0x1000
+#define HBM4_MC0_CS_ETF_SECTION 0x1000
+#define mmHBM4_MC0_CS_SPMU_BASE 0x7214000ull
+#define HBM4_MC0_CS_SPMU_MAX_OFFSET 0x1000
+#define HBM4_MC0_CS_SPMU_SECTION 0x1000
+#define mmHBM4_MC0_BMON_CTI_BASE 0x7215000ull
+#define HBM4_MC0_BMON_CTI_MAX_OFFSET 0x1000
+#define HBM4_MC0_BMON_CTI_SECTION 0x1000
+#define mmHBM4_MC0_USER_CTI_BASE 0x7216000ull
+#define HBM4_MC0_USER_CTI_MAX_OFFSET 0x1000
+#define HBM4_MC0_USER_CTI_SECTION 0xA000
+#define mmHBM4_MC0_FUNNEL_BASE 0x7220000ull
+#define HBM4_MC0_FUNNEL_MAX_OFFSET 0x1000
+#define HBM4_MC0_FUNNEL_SECTION 0x30000
+#define mmHBM4_MC1_CS_DBG_ROM_TBL_BASE 0x7250000ull
+#define HBM4_MC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define HBM4_MC1_CS_DBG_ROM_TBL_SECTION 0x1000
+#define mmHBM4_MC1_CS_STM_BASE 0x7251000ull
+#define HBM4_MC1_CS_STM_MAX_OFFSET 0x1000
+#define HBM4_MC1_CS_STM_SECTION 0x1000
+#define mmHBM4_MC1_CS_CTI_BASE 0x7252000ull
+#define HBM4_MC1_CS_CTI_MAX_OFFSET 0x1000
+#define HBM4_MC1_CS_CTI_SECTION 0x1000
+#define mmHBM4_MC1_CS_ETF_BASE 0x7253000ull
+#define HBM4_MC1_CS_ETF_MAX_OFFSET 0x1000
+#define HBM4_MC1_CS_ETF_SECTION 0x1000
+#define mmHBM4_MC1_CS_SPMU_BASE 0x7254000ull
+#define HBM4_MC1_CS_SPMU_MAX_OFFSET 0x1000
+#define HBM4_MC1_CS_SPMU_SECTION 0x1000
+#define mmHBM4_MC1_BMON_CTI_BASE 0x7255000ull
+#define HBM4_MC1_BMON_CTI_MAX_OFFSET 0x1000
+#define HBM4_MC1_BMON_CTI_SECTION 0x1000
+#define mmHBM4_MC1_USER_CTI_BASE 0x7256000ull
+#define HBM4_MC1_USER_CTI_MAX_OFFSET 0x1000
+#define HBM4_MC1_USER_CTI_SECTION 0xA000
+#define mmHBM4_MC1_FUNNEL_BASE 0x7260000ull
+#define HBM4_MC1_FUNNEL_MAX_OFFSET 0x1000
+#define HBM4_MC1_FUNNEL_SECTION 0x30000
+#define mmHBM5_MC0_CS_DBG_ROM_TBL_BASE 0x7290000ull
+#define HBM5_MC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define HBM5_MC0_CS_DBG_ROM_TBL_SECTION 0x1000
+#define mmHBM5_MC0_CS_STM_BASE 0x7291000ull
+#define HBM5_MC0_CS_STM_MAX_OFFSET 0x1000
+#define HBM5_MC0_CS_STM_SECTION 0x1000
+#define mmHBM5_MC0_CS_CTI_BASE 0x7292000ull
+#define HBM5_MC0_CS_CTI_MAX_OFFSET 0x1000
+#define HBM5_MC0_CS_CTI_SECTION 0x1000
+#define mmHBM5_MC0_CS_ETF_BASE 0x7293000ull
+#define HBM5_MC0_CS_ETF_MAX_OFFSET 0x1000
+#define HBM5_MC0_CS_ETF_SECTION 0x1000
+#define mmHBM5_MC0_CS_SPMU_BASE 0x7294000ull
+#define HBM5_MC0_CS_SPMU_MAX_OFFSET 0x1000
+#define HBM5_MC0_CS_SPMU_SECTION 0x1000
+#define mmHBM5_MC0_BMON_CTI_BASE 0x7295000ull
+#define HBM5_MC0_BMON_CTI_MAX_OFFSET 0x1000
+#define HBM5_MC0_BMON_CTI_SECTION 0x1000
+#define mmHBM5_MC0_USER_CTI_BASE 0x7296000ull
+#define HBM5_MC0_USER_CTI_MAX_OFFSET 0x1000
+#define HBM5_MC0_USER_CTI_SECTION 0xA000
+#define mmHBM5_MC0_FUNNEL_BASE 0x72A0000ull
+#define HBM5_MC0_FUNNEL_MAX_OFFSET 0x1000
+#define HBM5_MC0_FUNNEL_SECTION 0x30000
+#define mmHBM5_MC1_CS_DBG_ROM_TBL_BASE 0x72D0000ull
+#define HBM5_MC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
+#define HBM5_MC1_CS_DBG_ROM_TBL_SECTION 0x1000
+#define mmHBM5_MC1_CS_STM_BASE 0x72D1000ull
+#define HBM5_MC1_CS_STM_MAX_OFFSET 0x1000
+#define HBM5_MC1_CS_STM_SECTION 0x1000
+#define mmHBM5_MC1_CS_CTI_BASE 0x72D2000ull
+#define HBM5_MC1_CS_CTI_MAX_OFFSET 0x1000
+#define HBM5_MC1_CS_CTI_SECTION 0x1000
+#define mmHBM5_MC1_CS_ETF_BASE 0x72D3000ull
+#define HBM5_MC1_CS_ETF_MAX_OFFSET 0x1000
+#define HBM5_MC1_CS_ETF_SECTION 0x1000
+#define mmHBM5_MC1_CS_SPMU_BASE 0x72D4000ull
+#define HBM5_MC1_CS_SPMU_MAX_OFFSET 0x1000
+#define HBM5_MC1_CS_SPMU_SECTION 0x1000
+#define mmHBM5_MC1_BMON_CTI_BASE 0x72D5000ull
+#define HBM5_MC1_BMON_CTI_MAX_OFFSET 0x1000
+#define HBM5_MC1_BMON_CTI_SECTION 0x1000
+#define mmHBM5_MC1_USER_CTI_BASE 0x72D6000ull
+#define HBM5_MC1_USER_CTI_MAX_OFFSET 0x1000
+#define HBM5_MC1_USER_CTI_SECTION 0xA000
+#define mmHBM5_MC1_FUNNEL_BASE 0x72E0000ull
+#define HBM5_MC1_FUNNEL_MAX_OFFSET 0x1000
+#define HBM5_MC1_FUNNEL_SECTION 0x20000
+#define mmNIC0_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7300000ull
+#define NIC0_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000
+#define NIC0_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000
+#define mmNIC0_DBG_STM_0_BASE 0x7301000ull
+#define NIC0_DBG_STM_0_MAX_OFFSET 0x1000
+#define NIC0_DBG_STM_0_SECTION 0x1000
+#define mmNIC0_DBG_CTI_0_BASE 0x7302000ull
+#define NIC0_DBG_CTI_0_MAX_OFFSET 0x1000
+#define NIC0_DBG_CTI_0_SECTION 0x1000
+#define mmNIC0_DBG_ETF_0_BASE 0x7303000ull
+#define NIC0_DBG_ETF_0_MAX_OFFSET 0x1000
+#define NIC0_DBG_ETF_0_SECTION 0x1000
+#define mmNIC0_DBG_SPMU_0_BASE 0x7304000ull
+#define NIC0_DBG_SPMU_0_MAX_OFFSET 0x1000
+#define NIC0_DBG_SPMU_0_SECTION 0x1000
+#define mmNIC0_DBG_USER_CTI_0_BASE 0x7305000ull
+#define NIC0_DBG_USER_CTI_0_MAX_OFFSET 0x1000
+#define NIC0_DBG_USER_CTI_0_SECTION 0x1000
+#define mmNIC0_DBG_BMON_CTI_0_BASE 0x7306000ull
+#define NIC0_DBG_BMON_CTI_0_MAX_OFFSET 0x1000
+#define NIC0_DBG_BMON_CTI_0_SECTION 0x1000
+#define mmNIC0_DBG_BMON0_0_BASE 0x7307000ull
+#define NIC0_DBG_BMON0_0_MAX_OFFSET 0x1000
+#define NIC0_DBG_BMON0_0_SECTION 0x1000
+#define mmNIC0_DBG_BMON1_0_BASE 0x7308000ull
+#define NIC0_DBG_BMON1_0_MAX_OFFSET 0x1000
+#define NIC0_DBG_BMON1_0_SECTION 0x1000
+#define mmNIC0_DBG_BMON2_0_BASE 0x7309000ull
+#define NIC0_DBG_BMON2_0_MAX_OFFSET 0x1000
+#define NIC0_DBG_BMON2_0_SECTION 0x7000
+#define mmNIC0_DBG_ARC_RTT0_BASE 0x7310000ull
+#define NIC0_DBG_ARC_RTT0_MAX_OFFSET 0x1400
+#define NIC0_DBG_ARC_RTT0_SECTION 0x10000
+#define mmNIC0_DBG_CS_DBG_ROM_TABLE_1_BASE 0x7320000ull
+#define NIC0_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000
+#define NIC0_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000
+#define mmNIC0_DBG_STM_1_BASE 0x7321000ull
+#define NIC0_DBG_STM_1_MAX_OFFSET 0x1000
+#define NIC0_DBG_STM_1_SECTION 0x1000
+#define mmNIC0_DBG_CTI_1_BASE 0x7322000ull
+#define NIC0_DBG_CTI_1_MAX_OFFSET 0x1000
+#define NIC0_DBG_CTI_1_SECTION 0x1000
+#define mmNIC0_DBG_ETF_1_BASE 0x7323000ull
+#define NIC0_DBG_ETF_1_MAX_OFFSET 0x1000
+#define NIC0_DBG_ETF_1_SECTION 0x1000
+#define mmNIC0_DBG_SPMU_1_BASE 0x7324000ull
+#define NIC0_DBG_SPMU_1_MAX_OFFSET 0x1000
+#define NIC0_DBG_SPMU_1_SECTION 0x1000
+#define mmNIC0_DBG_USER_CTI_1_BASE 0x7325000ull
+#define NIC0_DBG_USER_CTI_1_MAX_OFFSET 0x1000
+#define NIC0_DBG_USER_CTI_1_SECTION 0x1000
+#define mmNIC0_DBG_BMON_CTI_1_BASE 0x7326000ull
+#define NIC0_DBG_BMON_CTI_1_MAX_OFFSET 0x1000
+#define NIC0_DBG_BMON_CTI_1_SECTION 0x1000
+#define mmNIC0_DBG_BMON0_1_BASE 0x7327000ull
+#define NIC0_DBG_BMON0_1_MAX_OFFSET 0x1000
+#define NIC0_DBG_BMON0_1_SECTION 0x1000
+#define mmNIC0_DBG_BMON1_1_BASE 0x7328000ull
+#define NIC0_DBG_BMON1_1_MAX_OFFSET 0x1000
+#define NIC0_DBG_BMON1_1_SECTION 0x1000
+#define mmNIC0_DBG_BMON2_1_BASE 0x7329000ull
+#define NIC0_DBG_BMON2_1_MAX_OFFSET 0x1000
+#define NIC0_DBG_BMON2_1_SECTION 0x7000
+#define mmNIC0_DBG_ARC_RTT1_BASE 0x7330000ull
+#define NIC0_DBG_ARC_RTT1_MAX_OFFSET 0x1400
+#define NIC0_DBG_ARC_RTT1_SECTION 0x8000
+#define mmNIC0_DBG_FUNNEL_TX_BASE 0x7338000ull
+#define NIC0_DBG_FUNNEL_TX_MAX_OFFSET 0x1000
+#define NIC0_DBG_FUNNEL_TX_SECTION 0x1000
+#define mmNIC0_DBG_FUNNEL_NCH_BASE 0x7339000ull
+#define NIC0_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000
+#define NIC0_DBG_FUNNEL_NCH_SECTION 0x7000
+#define mmNIC1_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7340000ull
+#define NIC1_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000
+#define NIC1_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000
+#define mmNIC1_DBG_STM_0_BASE 0x7341000ull
+#define NIC1_DBG_STM_0_MAX_OFFSET 0x1000
+#define NIC1_DBG_STM_0_SECTION 0x1000
+#define mmNIC1_DBG_CTI_0_BASE 0x7342000ull
+#define NIC1_DBG_CTI_0_MAX_OFFSET 0x1000
+#define NIC1_DBG_CTI_0_SECTION 0x1000
+#define mmNIC1_DBG_ETF_0_BASE 0x7343000ull
+#define NIC1_DBG_ETF_0_MAX_OFFSET 0x1000
+#define NIC1_DBG_ETF_0_SECTION 0x1000
+#define mmNIC1_DBG_SPMU_0_BASE 0x7344000ull
+#define NIC1_DBG_SPMU_0_MAX_OFFSET 0x1000
+#define NIC1_DBG_SPMU_0_SECTION 0x1000
+#define mmNIC1_DBG_USER_CTI_0_BASE 0x7345000ull
+#define NIC1_DBG_USER_CTI_0_MAX_OFFSET 0x1000
+#define NIC1_DBG_USER_CTI_0_SECTION 0x1000
+#define mmNIC1_DBG_BMON_CTI_0_BASE 0x7346000ull
+#define NIC1_DBG_BMON_CTI_0_MAX_OFFSET 0x1000
+#define NIC1_DBG_BMON_CTI_0_SECTION 0x1000
+#define mmNIC1_DBG_BMON0_0_BASE 0x7347000ull
+#define NIC1_DBG_BMON0_0_MAX_OFFSET 0x1000
+#define NIC1_DBG_BMON0_0_SECTION 0x1000
+#define mmNIC1_DBG_BMON1_0_BASE 0x7348000ull
+#define NIC1_DBG_BMON1_0_MAX_OFFSET 0x1000
+#define NIC1_DBG_BMON1_0_SECTION 0x1000
+#define mmNIC1_DBG_BMON2_0_BASE 0x7349000ull
+#define NIC1_DBG_BMON2_0_MAX_OFFSET 0x1000
+#define NIC1_DBG_BMON2_0_SECTION 0x7000
+#define mmNIC1_DBG_ARC_RTT0_BASE 0x7350000ull
+#define NIC1_DBG_ARC_RTT0_MAX_OFFSET 0x1400
+#define NIC1_DBG_ARC_RTT0_SECTION 0x10000
+#define mmNIC1_DBG_CS_DBG_ROM_TABLE_1_BASE 0x7360000ull
+#define NIC1_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000
+#define NIC1_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000
+#define mmNIC1_DBG_STM_1_BASE 0x7361000ull
+#define NIC1_DBG_STM_1_MAX_OFFSET 0x1000
+#define NIC1_DBG_STM_1_SECTION 0x1000
+#define mmNIC1_DBG_CTI_1_BASE 0x7362000ull
+#define NIC1_DBG_CTI_1_MAX_OFFSET 0x1000
+#define NIC1_DBG_CTI_1_SECTION 0x1000
+#define mmNIC1_DBG_ETF_1_BASE 0x7363000ull
+#define NIC1_DBG_ETF_1_MAX_OFFSET 0x1000
+#define NIC1_DBG_ETF_1_SECTION 0x1000
+#define mmNIC1_DBG_SPMU_1_BASE 0x7364000ull
+#define NIC1_DBG_SPMU_1_MAX_OFFSET 0x1000
+#define NIC1_DBG_SPMU_1_SECTION 0x1000
+#define mmNIC1_DBG_USER_CTI_1_BASE 0x7365000ull
+#define NIC1_DBG_USER_CTI_1_MAX_OFFSET 0x1000
+#define NIC1_DBG_USER_CTI_1_SECTION 0x1000
+#define mmNIC1_DBG_BMON_CTI_1_BASE 0x7366000ull
+#define NIC1_DBG_BMON_CTI_1_MAX_OFFSET 0x1000
+#define NIC1_DBG_BMON_CTI_1_SECTION 0x1000
+#define mmNIC1_DBG_BMON0_1_BASE 0x7367000ull
+#define NIC1_DBG_BMON0_1_MAX_OFFSET 0x1000
+#define NIC1_DBG_BMON0_1_SECTION 0x1000
+#define mmNIC1_DBG_BMON1_1_BASE 0x7368000ull
+#define NIC1_DBG_BMON1_1_MAX_OFFSET 0x1000
+#define NIC1_DBG_BMON1_1_SECTION 0x1000
+#define mmNIC1_DBG_BMON2_1_BASE 0x7369000ull
+#define NIC1_DBG_BMON2_1_MAX_OFFSET 0x1000
+#define NIC1_DBG_BMON2_1_SECTION 0x7000
+#define mmNIC1_DBG_ARC_RTT1_BASE 0x7370000ull
+#define NIC1_DBG_ARC_RTT1_MAX_OFFSET 0x1400
+#define NIC1_DBG_ARC_RTT1_SECTION 0x8000
+#define mmNIC1_DBG_FUNNEL_TX_BASE 0x7378000ull
+#define NIC1_DBG_FUNNEL_TX_MAX_OFFSET 0x1000
+#define NIC1_DBG_FUNNEL_TX_SECTION 0x1000
+#define mmNIC1_DBG_FUNNEL_NCH_BASE 0x7379000ull
+#define NIC1_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000
+#define NIC1_DBG_FUNNEL_NCH_SECTION 0x7000
+#define mmNIC2_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7380000ull
+#define NIC2_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000
+#define NIC2_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000
+#define mmNIC2_DBG_STM_0_BASE 0x7381000ull
+#define NIC2_DBG_STM_0_MAX_OFFSET 0x1000
+#define NIC2_DBG_STM_0_SECTION 0x1000
+#define mmNIC2_DBG_CTI_0_BASE 0x7382000ull
+#define NIC2_DBG_CTI_0_MAX_OFFSET 0x1000
+#define NIC2_DBG_CTI_0_SECTION 0x1000
+#define mmNIC2_DBG_ETF_0_BASE 0x7383000ull
+#define NIC2_DBG_ETF_0_MAX_OFFSET 0x1000
+#define NIC2_DBG_ETF_0_SECTION 0x1000
+#define mmNIC2_DBG_SPMU_0_BASE 0x7384000ull
+#define NIC2_DBG_SPMU_0_MAX_OFFSET 0x1000
+#define NIC2_DBG_SPMU_0_SECTION 0x1000
+#define mmNIC2_DBG_USER_CTI_0_BASE 0x7385000ull
+#define NIC2_DBG_USER_CTI_0_MAX_OFFSET 0x1000
+#define NIC2_DBG_USER_CTI_0_SECTION 0x1000
+#define mmNIC2_DBG_BMON_CTI_0_BASE 0x7386000ull
+#define NIC2_DBG_BMON_CTI_0_MAX_OFFSET 0x1000
+#define NIC2_DBG_BMON_CTI_0_SECTION 0x1000
+#define mmNIC2_DBG_BMON0_0_BASE 0x7387000ull
+#define NIC2_DBG_BMON0_0_MAX_OFFSET 0x1000
+#define NIC2_DBG_BMON0_0_SECTION 0x1000
+#define mmNIC2_DBG_BMON1_0_BASE 0x7388000ull
+#define NIC2_DBG_BMON1_0_MAX_OFFSET 0x1000
+#define NIC2_DBG_BMON1_0_SECTION 0x1000
+#define mmNIC2_DBG_BMON2_0_BASE 0x7389000ull
+#define NIC2_DBG_BMON2_0_MAX_OFFSET 0x1000
+#define NIC2_DBG_BMON2_0_SECTION 0x7000
+#define mmNIC2_DBG_ARC_RTT0_BASE 0x7390000ull
+#define NIC2_DBG_ARC_RTT0_MAX_OFFSET 0x1400
+#define NIC2_DBG_ARC_RTT0_SECTION 0x10000
+#define mmNIC2_DBG_CS_DBG_ROM_TABLE_1_BASE 0x73A0000ull
+#define NIC2_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000
+#define NIC2_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000
+#define mmNIC2_DBG_STM_1_BASE 0x73A1000ull
+#define NIC2_DBG_STM_1_MAX_OFFSET 0x1000
+#define NIC2_DBG_STM_1_SECTION 0x1000
+#define mmNIC2_DBG_CTI_1_BASE 0x73A2000ull
+#define NIC2_DBG_CTI_1_MAX_OFFSET 0x1000
+#define NIC2_DBG_CTI_1_SECTION 0x1000
+#define mmNIC2_DBG_ETF_1_BASE 0x73A3000ull
+#define NIC2_DBG_ETF_1_MAX_OFFSET 0x1000
+#define NIC2_DBG_ETF_1_SECTION 0x1000
+#define mmNIC2_DBG_SPMU_1_BASE 0x73A4000ull
+#define NIC2_DBG_SPMU_1_MAX_OFFSET 0x1000
+#define NIC2_DBG_SPMU_1_SECTION 0x1000
+#define mmNIC2_DBG_USER_CTI_1_BASE 0x73A5000ull
+#define NIC2_DBG_USER_CTI_1_MAX_OFFSET 0x1000
+#define NIC2_DBG_USER_CTI_1_SECTION 0x1000
+#define mmNIC2_DBG_BMON_CTI_1_BASE 0x73A6000ull
+#define NIC2_DBG_BMON_CTI_1_MAX_OFFSET 0x1000
+#define NIC2_DBG_BMON_CTI_1_SECTION 0x1000
+#define mmNIC2_DBG_BMON0_1_BASE 0x73A7000ull
+#define NIC2_DBG_BMON0_1_MAX_OFFSET 0x1000
+#define NIC2_DBG_BMON0_1_SECTION 0x1000
+#define mmNIC2_DBG_BMON1_1_BASE 0x73A8000ull
+#define NIC2_DBG_BMON1_1_MAX_OFFSET 0x1000
+#define NIC2_DBG_BMON1_1_SECTION 0x1000
+#define mmNIC2_DBG_BMON2_1_BASE 0x73A9000ull
+#define NIC2_DBG_BMON2_1_MAX_OFFSET 0x1000
+#define NIC2_DBG_BMON2_1_SECTION 0x7000
+#define mmNIC2_DBG_ARC_RTT1_BASE 0x73B0000ull
+#define NIC2_DBG_ARC_RTT1_MAX_OFFSET 0x1400
+#define NIC2_DBG_ARC_RTT1_SECTION 0x8000
+#define mmNIC2_DBG_FUNNEL_TX_BASE 0x73B8000ull
+#define NIC2_DBG_FUNNEL_TX_MAX_OFFSET 0x1000
+#define NIC2_DBG_FUNNEL_TX_SECTION 0x1000
+#define mmNIC2_DBG_FUNNEL_NCH_BASE 0x73B9000ull
+#define NIC2_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000
+#define NIC2_DBG_FUNNEL_NCH_SECTION 0x7000
+#define mmNIC3_DBG_CS_DBG_ROM_TABLE_0_BASE 0x73C0000ull
+#define NIC3_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000
+#define NIC3_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000
+#define mmNIC3_DBG_STM_0_BASE 0x73C1000ull
+#define NIC3_DBG_STM_0_MAX_OFFSET 0x1000
+#define NIC3_DBG_STM_0_SECTION 0x1000
+#define mmNIC3_DBG_CTI_0_BASE 0x73C2000ull
+#define NIC3_DBG_CTI_0_MAX_OFFSET 0x1000
+#define NIC3_DBG_CTI_0_SECTION 0x1000
+#define mmNIC3_DBG_ETF_0_BASE 0x73C3000ull
+#define NIC3_DBG_ETF_0_MAX_OFFSET 0x1000
+#define NIC3_DBG_ETF_0_SECTION 0x1000
+#define mmNIC3_DBG_SPMU_0_BASE 0x73C4000ull
+#define NIC3_DBG_SPMU_0_MAX_OFFSET 0x1000
+#define NIC3_DBG_SPMU_0_SECTION 0x1000
+#define mmNIC3_DBG_USER_CTI_0_BASE 0x73C5000ull
+#define NIC3_DBG_USER_CTI_0_MAX_OFFSET 0x1000
+#define NIC3_DBG_USER_CTI_0_SECTION 0x1000
+#define mmNIC3_DBG_BMON_CTI_0_BASE 0x73C6000ull
+#define NIC3_DBG_BMON_CTI_0_MAX_OFFSET 0x1000
+#define NIC3_DBG_BMON_CTI_0_SECTION 0x1000
+#define mmNIC3_DBG_BMON0_0_BASE 0x73C7000ull
+#define NIC3_DBG_BMON0_0_MAX_OFFSET 0x1000
+#define NIC3_DBG_BMON0_0_SECTION 0x1000
+#define mmNIC3_DBG_BMON1_0_BASE 0x73C8000ull
+#define NIC3_DBG_BMON1_0_MAX_OFFSET 0x1000
+#define NIC3_DBG_BMON1_0_SECTION 0x1000
+#define mmNIC3_DBG_BMON2_0_BASE 0x73C9000ull
+#define NIC3_DBG_BMON2_0_MAX_OFFSET 0x1000
+#define NIC3_DBG_BMON2_0_SECTION 0x7000
+#define mmNIC3_DBG_ARC_RTT0_BASE 0x73D0000ull
+#define NIC3_DBG_ARC_RTT0_MAX_OFFSET 0x1400
+#define NIC3_DBG_ARC_RTT0_SECTION 0x10000
+#define mmNIC3_DBG_CS_DBG_ROM_TABLE_1_BASE 0x73E0000ull
+#define NIC3_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000
+#define NIC3_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000
+#define mmNIC3_DBG_STM_1_BASE 0x73E1000ull
+#define NIC3_DBG_STM_1_MAX_OFFSET 0x1000
+#define NIC3_DBG_STM_1_SECTION 0x1000
+#define mmNIC3_DBG_CTI_1_BASE 0x73E2000ull
+#define NIC3_DBG_CTI_1_MAX_OFFSET 0x1000
+#define NIC3_DBG_CTI_1_SECTION 0x1000
+#define mmNIC3_DBG_ETF_1_BASE 0x73E3000ull
+#define NIC3_DBG_ETF_1_MAX_OFFSET 0x1000
+#define NIC3_DBG_ETF_1_SECTION 0x1000
+#define mmNIC3_DBG_SPMU_1_BASE 0x73E4000ull
+#define NIC3_DBG_SPMU_1_MAX_OFFSET 0x1000
+#define NIC3_DBG_SPMU_1_SECTION 0x1000
+#define mmNIC3_DBG_USER_CTI_1_BASE 0x73E5000ull
+#define NIC3_DBG_USER_CTI_1_MAX_OFFSET 0x1000
+#define NIC3_DBG_USER_CTI_1_SECTION 0x1000
+#define mmNIC3_DBG_BMON_CTI_1_BASE 0x73E6000ull
+#define NIC3_DBG_BMON_CTI_1_MAX_OFFSET 0x1000
+#define NIC3_DBG_BMON_CTI_1_SECTION 0x1000
+#define mmNIC3_DBG_BMON0_1_BASE 0x73E7000ull
+#define NIC3_DBG_BMON0_1_MAX_OFFSET 0x1000
+#define NIC3_DBG_BMON0_1_SECTION 0x1000
+#define mmNIC3_DBG_BMON1_1_BASE 0x73E8000ull
+#define NIC3_DBG_BMON1_1_MAX_OFFSET 0x1000
+#define NIC3_DBG_BMON1_1_SECTION 0x1000
+#define mmNIC3_DBG_BMON2_1_BASE 0x73E9000ull
+#define NIC3_DBG_BMON2_1_MAX_OFFSET 0x1000
+#define NIC3_DBG_BMON2_1_SECTION 0x7000
+#define mmNIC3_DBG_ARC_RTT1_BASE 0x73F0000ull
+#define NIC3_DBG_ARC_RTT1_MAX_OFFSET 0x1400
+#define NIC3_DBG_ARC_RTT1_SECTION 0x8000
+#define mmNIC3_DBG_FUNNEL_TX_BASE 0x73F8000ull
+#define NIC3_DBG_FUNNEL_TX_MAX_OFFSET 0x1000
+#define NIC3_DBG_FUNNEL_TX_SECTION 0x1000
+#define mmNIC3_DBG_FUNNEL_NCH_BASE 0x73F9000ull
+#define NIC3_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000
+#define NIC3_DBG_FUNNEL_NCH_SECTION 0x7000
+#define mmNIC4_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7400000ull
+#define NIC4_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000
+#define NIC4_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000
+#define mmNIC4_DBG_STM_0_BASE 0x7401000ull
+#define NIC4_DBG_STM_0_MAX_OFFSET 0x1000
+#define NIC4_DBG_STM_0_SECTION 0x1000
+#define mmNIC4_DBG_CTI_0_BASE 0x7402000ull
+#define NIC4_DBG_CTI_0_MAX_OFFSET 0x1000
+#define NIC4_DBG_CTI_0_SECTION 0x1000
+#define mmNIC4_DBG_ETF_0_BASE 0x7403000ull
+#define NIC4_DBG_ETF_0_MAX_OFFSET 0x1000
+#define NIC4_DBG_ETF_0_SECTION 0x1000
+#define mmNIC4_DBG_SPMU_0_BASE 0x7404000ull
+#define NIC4_DBG_SPMU_0_MAX_OFFSET 0x1000
+#define NIC4_DBG_SPMU_0_SECTION 0x1000
+#define mmNIC4_DBG_USER_CTI_0_BASE 0x7405000ull
+#define NIC4_DBG_USER_CTI_0_MAX_OFFSET 0x1000
+#define NIC4_DBG_USER_CTI_0_SECTION 0x1000
+#define mmNIC4_DBG_BMON_CTI_0_BASE 0x7406000ull
+#define NIC4_DBG_BMON_CTI_0_MAX_OFFSET 0x1000
+#define NIC4_DBG_BMON_CTI_0_SECTION 0x1000
+#define mmNIC4_DBG_BMON0_0_BASE 0x7407000ull
+#define NIC4_DBG_BMON0_0_MAX_OFFSET 0x1000
+#define NIC4_DBG_BMON0_0_SECTION 0x1000
+#define mmNIC4_DBG_BMON1_0_BASE 0x7408000ull
+#define NIC4_DBG_BMON1_0_MAX_OFFSET 0x1000
+#define NIC4_DBG_BMON1_0_SECTION 0x1000
+#define mmNIC4_DBG_BMON2_0_BASE 0x7409000ull
+#define NIC4_DBG_BMON2_0_MAX_OFFSET 0x1000
+#define NIC4_DBG_BMON2_0_SECTION 0x7000
+#define mmNIC4_DBG_ARC_RTT0_BASE 0x7410000ull
+#define NIC4_DBG_ARC_RTT0_MAX_OFFSET 0x1400
+#define NIC4_DBG_ARC_RTT0_SECTION 0x10000
+#define mmNIC4_DBG_CS_DBG_ROM_TABLE_1_BASE 0x7420000ull
+#define NIC4_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000
+#define NIC4_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000
+#define mmNIC4_DBG_STM_1_BASE 0x7421000ull
+#define NIC4_DBG_STM_1_MAX_OFFSET 0x1000
+#define NIC4_DBG_STM_1_SECTION 0x1000
+#define mmNIC4_DBG_CTI_1_BASE 0x7422000ull
+#define NIC4_DBG_CTI_1_MAX_OFFSET 0x1000
+#define NIC4_DBG_CTI_1_SECTION 0x1000
+#define mmNIC4_DBG_ETF_1_BASE 0x7423000ull
+#define NIC4_DBG_ETF_1_MAX_OFFSET 0x1000
+#define NIC4_DBG_ETF_1_SECTION 0x1000
+#define mmNIC4_DBG_SPMU_1_BASE 0x7424000ull
+#define NIC4_DBG_SPMU_1_MAX_OFFSET 0x1000
+#define NIC4_DBG_SPMU_1_SECTION 0x1000
+#define mmNIC4_DBG_USER_CTI_1_BASE 0x7425000ull
+#define NIC4_DBG_USER_CTI_1_MAX_OFFSET 0x1000
+#define NIC4_DBG_USER_CTI_1_SECTION 0x1000
+#define mmNIC4_DBG_BMON_CTI_1_BASE 0x7426000ull
+#define NIC4_DBG_BMON_CTI_1_MAX_OFFSET 0x1000
+#define NIC4_DBG_BMON_CTI_1_SECTION 0x1000
+#define mmNIC4_DBG_BMON0_1_BASE 0x7427000ull
+#define NIC4_DBG_BMON0_1_MAX_OFFSET 0x1000
+#define NIC4_DBG_BMON0_1_SECTION 0x1000
+#define mmNIC4_DBG_BMON1_1_BASE 0x7428000ull
+#define NIC4_DBG_BMON1_1_MAX_OFFSET 0x1000
+#define NIC4_DBG_BMON1_1_SECTION 0x1000
+#define mmNIC4_DBG_BMON2_1_BASE 0x7429000ull
+#define NIC4_DBG_BMON2_1_MAX_OFFSET 0x1000
+#define NIC4_DBG_BMON2_1_SECTION 0x7000
+#define mmNIC4_DBG_ARC_RTT1_BASE 0x7430000ull
+#define NIC4_DBG_ARC_RTT1_MAX_OFFSET 0x1400
+#define NIC4_DBG_ARC_RTT1_SECTION 0x8000
+#define mmNIC4_DBG_FUNNEL_TX_BASE 0x7438000ull
+#define NIC4_DBG_FUNNEL_TX_MAX_OFFSET 0x1000
+#define NIC4_DBG_FUNNEL_TX_SECTION 0x1000
+#define mmNIC4_DBG_FUNNEL_NCH_BASE 0x7439000ull
+#define NIC4_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000
+#define NIC4_DBG_FUNNEL_NCH_SECTION 0x7000
+#define mmNIC5_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7440000ull
+#define NIC5_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000
+#define NIC5_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000
+#define mmNIC5_DBG_STM_0_BASE 0x7441000ull
+#define NIC5_DBG_STM_0_MAX_OFFSET 0x1000
+#define NIC5_DBG_STM_0_SECTION 0x1000
+#define mmNIC5_DBG_CTI_0_BASE 0x7442000ull
+#define NIC5_DBG_CTI_0_MAX_OFFSET 0x1000
+#define NIC5_DBG_CTI_0_SECTION 0x1000
+#define mmNIC5_DBG_ETF_0_BASE 0x7443000ull
+#define NIC5_DBG_ETF_0_MAX_OFFSET 0x1000
+#define NIC5_DBG_ETF_0_SECTION 0x1000
+#define mmNIC5_DBG_SPMU_0_BASE 0x7444000ull
+#define NIC5_DBG_SPMU_0_MAX_OFFSET 0x1000
+#define NIC5_DBG_SPMU_0_SECTION 0x1000
+#define mmNIC5_DBG_USER_CTI_0_BASE 0x7445000ull
+#define NIC5_DBG_USER_CTI_0_MAX_OFFSET 0x1000
+#define NIC5_DBG_USER_CTI_0_SECTION 0x1000
+#define mmNIC5_DBG_BMON_CTI_0_BASE 0x7446000ull
+#define NIC5_DBG_BMON_CTI_0_MAX_OFFSET 0x1000
+#define NIC5_DBG_BMON_CTI_0_SECTION 0x1000
+#define mmNIC5_DBG_BMON0_0_BASE 0x7447000ull
+#define NIC5_DBG_BMON0_0_MAX_OFFSET 0x1000
+#define NIC5_DBG_BMON0_0_SECTION 0x1000
+#define mmNIC5_DBG_BMON1_0_BASE 0x7448000ull
+#define NIC5_DBG_BMON1_0_MAX_OFFSET 0x1000
+#define NIC5_DBG_BMON1_0_SECTION 0x1000
+#define mmNIC5_DBG_BMON2_0_BASE 0x7449000ull
+#define NIC5_DBG_BMON2_0_MAX_OFFSET 0x1000
+#define NIC5_DBG_BMON2_0_SECTION 0x7000
+#define mmNIC5_DBG_ARC_RTT0_BASE 0x7450000ull
+#define NIC5_DBG_ARC_RTT0_MAX_OFFSET 0x1400
+#define NIC5_DBG_ARC_RTT0_SECTION 0x10000
+#define mmNIC5_DBG_CS_DBG_ROM_TABLE_1_BASE 0x7460000ull
+#define NIC5_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000
+#define NIC5_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000
+#define mmNIC5_DBG_STM_1_BASE 0x7461000ull
+#define NIC5_DBG_STM_1_MAX_OFFSET 0x1000
+#define NIC5_DBG_STM_1_SECTION 0x1000
+#define mmNIC5_DBG_CTI_1_BASE 0x7462000ull
+#define NIC5_DBG_CTI_1_MAX_OFFSET 0x1000
+#define NIC5_DBG_CTI_1_SECTION 0x1000
+#define mmNIC5_DBG_ETF_1_BASE 0x7463000ull
+#define NIC5_DBG_ETF_1_MAX_OFFSET 0x1000
+#define NIC5_DBG_ETF_1_SECTION 0x1000
+#define mmNIC5_DBG_SPMU_1_BASE 0x7464000ull
+#define NIC5_DBG_SPMU_1_MAX_OFFSET 0x1000
+#define NIC5_DBG_SPMU_1_SECTION 0x1000
+#define mmNIC5_DBG_USER_CTI_1_BASE 0x7465000ull
+#define NIC5_DBG_USER_CTI_1_MAX_OFFSET 0x1000
+#define NIC5_DBG_USER_CTI_1_SECTION 0x1000
+#define mmNIC5_DBG_BMON_CTI_1_BASE 0x7466000ull
+#define NIC5_DBG_BMON_CTI_1_MAX_OFFSET 0x1000
+#define NIC5_DBG_BMON_CTI_1_SECTION 0x1000
+#define mmNIC5_DBG_BMON0_1_BASE 0x7467000ull
+#define NIC5_DBG_BMON0_1_MAX_OFFSET 0x1000
+#define NIC5_DBG_BMON0_1_SECTION 0x1000
+#define mmNIC5_DBG_BMON1_1_BASE 0x7468000ull
+#define NIC5_DBG_BMON1_1_MAX_OFFSET 0x1000
+#define NIC5_DBG_BMON1_1_SECTION 0x1000
+#define mmNIC5_DBG_BMON2_1_BASE 0x7469000ull
+#define NIC5_DBG_BMON2_1_MAX_OFFSET 0x1000
+#define NIC5_DBG_BMON2_1_SECTION 0x7000
+#define mmNIC5_DBG_ARC_RTT1_BASE 0x7470000ull
+#define NIC5_DBG_ARC_RTT1_MAX_OFFSET 0x1400
+#define NIC5_DBG_ARC_RTT1_SECTION 0x8000
+#define mmNIC5_DBG_FUNNEL_TX_BASE 0x7478000ull
+#define NIC5_DBG_FUNNEL_TX_MAX_OFFSET 0x1000
+#define NIC5_DBG_FUNNEL_TX_SECTION 0x1000
+#define mmNIC5_DBG_FUNNEL_NCH_BASE 0x7479000ull
+#define NIC5_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000
+#define NIC5_DBG_FUNNEL_NCH_SECTION 0x7000
+#define mmNIC6_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7480000ull
+#define NIC6_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000
+#define NIC6_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000
+#define mmNIC6_DBG_STM_0_BASE 0x7481000ull
+#define NIC6_DBG_STM_0_MAX_OFFSET 0x1000
+#define NIC6_DBG_STM_0_SECTION 0x1000
+#define mmNIC6_DBG_CTI_0_BASE 0x7482000ull
+#define NIC6_DBG_CTI_0_MAX_OFFSET 0x1000
+#define NIC6_DBG_CTI_0_SECTION 0x1000
+#define mmNIC6_DBG_ETF_0_BASE 0x7483000ull
+#define NIC6_DBG_ETF_0_MAX_OFFSET 0x1000
+#define NIC6_DBG_ETF_0_SECTION 0x1000
+#define mmNIC6_DBG_SPMU_0_BASE 0x7484000ull
+#define NIC6_DBG_SPMU_0_MAX_OFFSET 0x1000
+#define NIC6_DBG_SPMU_0_SECTION 0x1000
+#define mmNIC6_DBG_USER_CTI_0_BASE 0x7485000ull
+#define NIC6_DBG_USER_CTI_0_MAX_OFFSET 0x1000
+#define NIC6_DBG_USER_CTI_0_SECTION 0x1000
+#define mmNIC6_DBG_BMON_CTI_0_BASE 0x7486000ull
+#define NIC6_DBG_BMON_CTI_0_MAX_OFFSET 0x1000
+#define NIC6_DBG_BMON_CTI_0_SECTION 0x1000
+#define mmNIC6_DBG_BMON0_0_BASE 0x7487000ull
+#define NIC6_DBG_BMON0_0_MAX_OFFSET 0x1000
+#define NIC6_DBG_BMON0_0_SECTION 0x1000
+#define mmNIC6_DBG_BMON1_0_BASE 0x7488000ull
+#define NIC6_DBG_BMON1_0_MAX_OFFSET 0x1000
+#define NIC6_DBG_BMON1_0_SECTION 0x1000
+#define mmNIC6_DBG_BMON2_0_BASE 0x7489000ull
+#define NIC6_DBG_BMON2_0_MAX_OFFSET 0x1000
+#define NIC6_DBG_BMON2_0_SECTION 0x7000
+#define mmNIC6_DBG_ARC_RTT0_BASE 0x7490000ull
+#define NIC6_DBG_ARC_RTT0_MAX_OFFSET 0x1400
+#define NIC6_DBG_ARC_RTT0_SECTION 0x10000
+#define mmNIC6_DBG_CS_DBG_ROM_TABLE_1_BASE 0x74A0000ull
+#define NIC6_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000
+#define NIC6_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000
+#define mmNIC6_DBG_STM_1_BASE 0x74A1000ull
+#define NIC6_DBG_STM_1_MAX_OFFSET 0x1000
+#define NIC6_DBG_STM_1_SECTION 0x1000
+#define mmNIC6_DBG_CTI_1_BASE 0x74A2000ull
+#define NIC6_DBG_CTI_1_MAX_OFFSET 0x1000
+#define NIC6_DBG_CTI_1_SECTION 0x1000
+#define mmNIC6_DBG_ETF_1_BASE 0x74A3000ull
+#define NIC6_DBG_ETF_1_MAX_OFFSET 0x1000
+#define NIC6_DBG_ETF_1_SECTION 0x1000
+#define mmNIC6_DBG_SPMU_1_BASE 0x74A4000ull
+#define NIC6_DBG_SPMU_1_MAX_OFFSET 0x1000
+#define NIC6_DBG_SPMU_1_SECTION 0x1000
+#define mmNIC6_DBG_USER_CTI_1_BASE 0x74A5000ull
+#define NIC6_DBG_USER_CTI_1_MAX_OFFSET 0x1000
+#define NIC6_DBG_USER_CTI_1_SECTION 0x1000
+#define mmNIC6_DBG_BMON_CTI_1_BASE 0x74A6000ull
+#define NIC6_DBG_BMON_CTI_1_MAX_OFFSET 0x1000
+#define NIC6_DBG_BMON_CTI_1_SECTION 0x1000
+#define mmNIC6_DBG_BMON0_1_BASE 0x74A7000ull
+#define NIC6_DBG_BMON0_1_MAX_OFFSET 0x1000
+#define NIC6_DBG_BMON0_1_SECTION 0x1000
+#define mmNIC6_DBG_BMON1_1_BASE 0x74A8000ull
+#define NIC6_DBG_BMON1_1_MAX_OFFSET 0x1000
+#define NIC6_DBG_BMON1_1_SECTION 0x1000
+#define mmNIC6_DBG_BMON2_1_BASE 0x74A9000ull
+#define NIC6_DBG_BMON2_1_MAX_OFFSET 0x1000
+#define NIC6_DBG_BMON2_1_SECTION 0x7000
+#define mmNIC6_DBG_ARC_RTT1_BASE 0x74B0000ull
+#define NIC6_DBG_ARC_RTT1_MAX_OFFSET 0x1400
+#define NIC6_DBG_ARC_RTT1_SECTION 0x8000
+#define mmNIC6_DBG_FUNNEL_TX_BASE 0x74B8000ull
+#define NIC6_DBG_FUNNEL_TX_MAX_OFFSET 0x1000
+#define NIC6_DBG_FUNNEL_TX_SECTION 0x1000
+#define mmNIC6_DBG_FUNNEL_NCH_BASE 0x74B9000ull
+#define NIC6_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000
+#define NIC6_DBG_FUNNEL_NCH_SECTION 0x7000
+#define mmNIC7_DBG_CS_DBG_ROM_TABLE_0_BASE 0x74C0000ull
+#define NIC7_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000
+#define NIC7_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000
+#define mmNIC7_DBG_STM_0_BASE 0x74C1000ull
+#define NIC7_DBG_STM_0_MAX_OFFSET 0x1000
+#define NIC7_DBG_STM_0_SECTION 0x1000
+#define mmNIC7_DBG_CTI_0_BASE 0x74C2000ull
+#define NIC7_DBG_CTI_0_MAX_OFFSET 0x1000
+#define NIC7_DBG_CTI_0_SECTION 0x1000
+#define mmNIC7_DBG_ETF_0_BASE 0x74C3000ull
+#define NIC7_DBG_ETF_0_MAX_OFFSET 0x1000
+#define NIC7_DBG_ETF_0_SECTION 0x1000
+#define mmNIC7_DBG_SPMU_0_BASE 0x74C4000ull
+#define NIC7_DBG_SPMU_0_MAX_OFFSET 0x1000
+#define NIC7_DBG_SPMU_0_SECTION 0x1000
+#define mmNIC7_DBG_USER_CTI_0_BASE 0x74C5000ull
+#define NIC7_DBG_USER_CTI_0_MAX_OFFSET 0x1000
+#define NIC7_DBG_USER_CTI_0_SECTION 0x1000
+#define mmNIC7_DBG_BMON_CTI_0_BASE 0x74C6000ull
+#define NIC7_DBG_BMON_CTI_0_MAX_OFFSET 0x1000
+#define NIC7_DBG_BMON_CTI_0_SECTION 0x1000
+#define mmNIC7_DBG_BMON0_0_BASE 0x74C7000ull
+#define NIC7_DBG_BMON0_0_MAX_OFFSET 0x1000
+#define NIC7_DBG_BMON0_0_SECTION 0x1000
+#define mmNIC7_DBG_BMON1_0_BASE 0x74C8000ull
+#define NIC7_DBG_BMON1_0_MAX_OFFSET 0x1000
+#define NIC7_DBG_BMON1_0_SECTION 0x1000
+#define mmNIC7_DBG_BMON2_0_BASE 0x74C9000ull
+#define NIC7_DBG_BMON2_0_MAX_OFFSET 0x1000
+#define NIC7_DBG_BMON2_0_SECTION 0x7000
+#define mmNIC7_DBG_ARC_RTT0_BASE 0x74D0000ull
+#define NIC7_DBG_ARC_RTT0_MAX_OFFSET 0x1400
+#define NIC7_DBG_ARC_RTT0_SECTION 0x10000
+#define mmNIC7_DBG_CS_DBG_ROM_TABLE_1_BASE 0x74E0000ull
+#define NIC7_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000
+#define NIC7_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000
+#define mmNIC7_DBG_STM_1_BASE 0x74E1000ull
+#define NIC7_DBG_STM_1_MAX_OFFSET 0x1000
+#define NIC7_DBG_STM_1_SECTION 0x1000
+#define mmNIC7_DBG_CTI_1_BASE 0x74E2000ull
+#define NIC7_DBG_CTI_1_MAX_OFFSET 0x1000
+#define NIC7_DBG_CTI_1_SECTION 0x1000
+#define mmNIC7_DBG_ETF_1_BASE 0x74E3000ull
+#define NIC7_DBG_ETF_1_MAX_OFFSET 0x1000
+#define NIC7_DBG_ETF_1_SECTION 0x1000
+#define mmNIC7_DBG_SPMU_1_BASE 0x74E4000ull
+#define NIC7_DBG_SPMU_1_MAX_OFFSET 0x1000
+#define NIC7_DBG_SPMU_1_SECTION 0x1000
+#define mmNIC7_DBG_USER_CTI_1_BASE 0x74E5000ull
+#define NIC7_DBG_USER_CTI_1_MAX_OFFSET 0x1000
+#define NIC7_DBG_USER_CTI_1_SECTION 0x1000
+#define mmNIC7_DBG_BMON_CTI_1_BASE 0x74E6000ull
+#define NIC7_DBG_BMON_CTI_1_MAX_OFFSET 0x1000
+#define NIC7_DBG_BMON_CTI_1_SECTION 0x1000
+#define mmNIC7_DBG_BMON0_1_BASE 0x74E7000ull
+#define NIC7_DBG_BMON0_1_MAX_OFFSET 0x1000
+#define NIC7_DBG_BMON0_1_SECTION 0x1000
+#define mmNIC7_DBG_BMON1_1_BASE 0x74E8000ull
+#define NIC7_DBG_BMON1_1_MAX_OFFSET 0x1000
+#define NIC7_DBG_BMON1_1_SECTION 0x1000
+#define mmNIC7_DBG_BMON2_1_BASE 0x74E9000ull
+#define NIC7_DBG_BMON2_1_MAX_OFFSET 0x1000
+#define NIC7_DBG_BMON2_1_SECTION 0x7000
+#define mmNIC7_DBG_ARC_RTT1_BASE 0x74F0000ull
+#define NIC7_DBG_ARC_RTT1_MAX_OFFSET 0x1400
+#define NIC7_DBG_ARC_RTT1_SECTION 0x8000
+#define mmNIC7_DBG_FUNNEL_TX_BASE 0x74F8000ull
+#define NIC7_DBG_FUNNEL_TX_MAX_OFFSET 0x1000
+#define NIC7_DBG_FUNNEL_TX_SECTION 0x1000
+#define mmNIC7_DBG_FUNNEL_NCH_BASE 0x74F9000ull
+#define NIC7_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000
+#define NIC7_DBG_FUNNEL_NCH_SECTION 0x7000
+#define mmNIC8_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7500000ull
+#define NIC8_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000
+#define NIC8_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000
+#define mmNIC8_DBG_STM_0_BASE 0x7501000ull
+#define NIC8_DBG_STM_0_MAX_OFFSET 0x1000
+#define NIC8_DBG_STM_0_SECTION 0x1000
+#define mmNIC8_DBG_CTI_0_BASE 0x7502000ull
+#define NIC8_DBG_CTI_0_MAX_OFFSET 0x1000
+#define NIC8_DBG_CTI_0_SECTION 0x1000
+#define mmNIC8_DBG_ETF_0_BASE 0x7503000ull
+#define NIC8_DBG_ETF_0_MAX_OFFSET 0x1000
+#define NIC8_DBG_ETF_0_SECTION 0x1000
+#define mmNIC8_DBG_SPMU_0_BASE 0x7504000ull
+#define NIC8_DBG_SPMU_0_MAX_OFFSET 0x1000
+#define NIC8_DBG_SPMU_0_SECTION 0x1000
+#define mmNIC8_DBG_USER_CTI_0_BASE 0x7505000ull
+#define NIC8_DBG_USER_CTI_0_MAX_OFFSET 0x1000
+#define NIC8_DBG_USER_CTI_0_SECTION 0x1000
+#define mmNIC8_DBG_BMON_CTI_0_BASE 0x7506000ull
+#define NIC8_DBG_BMON_CTI_0_MAX_OFFSET 0x1000
+#define NIC8_DBG_BMON_CTI_0_SECTION 0x1000
+#define mmNIC8_DBG_BMON0_0_BASE 0x7507000ull
+#define NIC8_DBG_BMON0_0_MAX_OFFSET 0x1000
+#define NIC8_DBG_BMON0_0_SECTION 0x1000
+#define mmNIC8_DBG_BMON1_0_BASE 0x7508000ull
+#define NIC8_DBG_BMON1_0_MAX_OFFSET 0x1000
+#define NIC8_DBG_BMON1_0_SECTION 0x1000
+#define mmNIC8_DBG_BMON2_0_BASE 0x7509000ull
+#define NIC8_DBG_BMON2_0_MAX_OFFSET 0x1000
+#define NIC8_DBG_BMON2_0_SECTION 0x7000
+#define mmNIC8_DBG_ARC_RTT0_BASE 0x7510000ull
+#define NIC8_DBG_ARC_RTT0_MAX_OFFSET 0x1400
+#define NIC8_DBG_ARC_RTT0_SECTION 0x10000
+#define mmNIC8_DBG_CS_DBG_ROM_TABLE_1_BASE 0x7520000ull
+#define NIC8_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000
+#define NIC8_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000
+#define mmNIC8_DBG_STM_1_BASE 0x7521000ull
+#define NIC8_DBG_STM_1_MAX_OFFSET 0x1000
+#define NIC8_DBG_STM_1_SECTION 0x1000
+#define mmNIC8_DBG_CTI_1_BASE 0x7522000ull
+#define NIC8_DBG_CTI_1_MAX_OFFSET 0x1000
+#define NIC8_DBG_CTI_1_SECTION 0x1000
+#define mmNIC8_DBG_ETF_1_BASE 0x7523000ull
+#define NIC8_DBG_ETF_1_MAX_OFFSET 0x1000
+#define NIC8_DBG_ETF_1_SECTION 0x1000
+#define mmNIC8_DBG_SPMU_1_BASE 0x7524000ull
+#define NIC8_DBG_SPMU_1_MAX_OFFSET 0x1000
+#define NIC8_DBG_SPMU_1_SECTION 0x1000
+#define mmNIC8_DBG_USER_CTI_1_BASE 0x7525000ull
+#define NIC8_DBG_USER_CTI_1_MAX_OFFSET 0x1000
+#define NIC8_DBG_USER_CTI_1_SECTION 0x1000
+#define mmNIC8_DBG_BMON_CTI_1_BASE 0x7526000ull
+#define NIC8_DBG_BMON_CTI_1_MAX_OFFSET 0x1000
+#define NIC8_DBG_BMON_CTI_1_SECTION 0x1000
+#define mmNIC8_DBG_BMON0_1_BASE 0x7527000ull
+#define NIC8_DBG_BMON0_1_MAX_OFFSET 0x1000
+#define NIC8_DBG_BMON0_1_SECTION 0x1000
+#define mmNIC8_DBG_BMON1_1_BASE 0x7528000ull
+#define NIC8_DBG_BMON1_1_MAX_OFFSET 0x1000
+#define NIC8_DBG_BMON1_1_SECTION 0x1000
+#define mmNIC8_DBG_BMON2_1_BASE 0x7529000ull
+#define NIC8_DBG_BMON2_1_MAX_OFFSET 0x1000
+#define NIC8_DBG_BMON2_1_SECTION 0x7000
+#define mmNIC8_DBG_ARC_RTT1_BASE 0x7530000ull
+#define NIC8_DBG_ARC_RTT1_MAX_OFFSET 0x1400
+#define NIC8_DBG_ARC_RTT1_SECTION 0x8000
+#define mmNIC8_DBG_FUNNEL_TX_BASE 0x7538000ull
+#define NIC8_DBG_FUNNEL_TX_MAX_OFFSET 0x1000
+#define NIC8_DBG_FUNNEL_TX_SECTION 0x1000
+#define mmNIC8_DBG_FUNNEL_NCH_BASE 0x7539000ull
+#define NIC8_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000
+#define NIC8_DBG_FUNNEL_NCH_SECTION 0x7000
+#define mmNIC9_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7540000ull
+#define NIC9_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000
+#define NIC9_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000
+#define mmNIC9_DBG_STM_0_BASE 0x7541000ull
+#define NIC9_DBG_STM_0_MAX_OFFSET 0x1000
+#define NIC9_DBG_STM_0_SECTION 0x1000
+#define mmNIC9_DBG_CTI_0_BASE 0x7542000ull
+#define NIC9_DBG_CTI_0_MAX_OFFSET 0x1000
+#define NIC9_DBG_CTI_0_SECTION 0x1000
+#define mmNIC9_DBG_ETF_0_BASE 0x7543000ull
+#define NIC9_DBG_ETF_0_MAX_OFFSET 0x1000
+#define NIC9_DBG_ETF_0_SECTION 0x1000
+#define mmNIC9_DBG_SPMU_0_BASE 0x7544000ull
+#define NIC9_DBG_SPMU_0_MAX_OFFSET 0x1000
+#define NIC9_DBG_SPMU_0_SECTION 0x1000
+#define mmNIC9_DBG_USER_CTI_0_BASE 0x7545000ull
+#define NIC9_DBG_USER_CTI_0_MAX_OFFSET 0x1000
+#define NIC9_DBG_USER_CTI_0_SECTION 0x1000
+#define mmNIC9_DBG_BMON_CTI_0_BASE 0x7546000ull
+#define NIC9_DBG_BMON_CTI_0_MAX_OFFSET 0x1000
+#define NIC9_DBG_BMON_CTI_0_SECTION 0x1000
+#define mmNIC9_DBG_BMON0_0_BASE 0x7547000ull
+#define NIC9_DBG_BMON0_0_MAX_OFFSET 0x1000
+#define NIC9_DBG_BMON0_0_SECTION 0x1000
+#define mmNIC9_DBG_BMON1_0_BASE 0x7548000ull
+#define NIC9_DBG_BMON1_0_MAX_OFFSET 0x1000
+#define NIC9_DBG_BMON1_0_SECTION 0x1000
+#define mmNIC9_DBG_BMON2_0_BASE 0x7549000ull
+#define NIC9_DBG_BMON2_0_MAX_OFFSET 0x1000
+#define NIC9_DBG_BMON2_0_SECTION 0x7000
+#define mmNIC9_DBG_ARC_RTT0_BASE 0x7550000ull
+#define NIC9_DBG_ARC_RTT0_MAX_OFFSET 0x1400
+#define NIC9_DBG_ARC_RTT0_SECTION 0x10000
+#define mmNIC9_DBG_CS_DBG_ROM_TABLE_1_BASE 0x7560000ull
+#define NIC9_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000
+#define NIC9_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000
+#define mmNIC9_DBG_STM_1_BASE 0x7561000ull
+#define NIC9_DBG_STM_1_MAX_OFFSET 0x1000
+#define NIC9_DBG_STM_1_SECTION 0x1000
+#define mmNIC9_DBG_CTI_1_BASE 0x7562000ull
+#define NIC9_DBG_CTI_1_MAX_OFFSET 0x1000
+#define NIC9_DBG_CTI_1_SECTION 0x1000
+#define mmNIC9_DBG_ETF_1_BASE 0x7563000ull
+#define NIC9_DBG_ETF_1_MAX_OFFSET 0x1000
+#define NIC9_DBG_ETF_1_SECTION 0x1000
+#define mmNIC9_DBG_SPMU_1_BASE 0x7564000ull
+#define NIC9_DBG_SPMU_1_MAX_OFFSET 0x1000
+#define NIC9_DBG_SPMU_1_SECTION 0x1000
+#define mmNIC9_DBG_USER_CTI_1_BASE 0x7565000ull
+#define NIC9_DBG_USER_CTI_1_MAX_OFFSET 0x1000
+#define NIC9_DBG_USER_CTI_1_SECTION 0x1000
+#define mmNIC9_DBG_BMON_CTI_1_BASE 0x7566000ull
+#define NIC9_DBG_BMON_CTI_1_MAX_OFFSET 0x1000
+#define NIC9_DBG_BMON_CTI_1_SECTION 0x1000
+#define mmNIC9_DBG_BMON0_1_BASE 0x7567000ull
+#define NIC9_DBG_BMON0_1_MAX_OFFSET 0x1000
+#define NIC9_DBG_BMON0_1_SECTION 0x1000
+#define mmNIC9_DBG_BMON1_1_BASE 0x7568000ull
+#define NIC9_DBG_BMON1_1_MAX_OFFSET 0x1000
+#define NIC9_DBG_BMON1_1_SECTION 0x1000
+#define mmNIC9_DBG_BMON2_1_BASE 0x7569000ull
+#define NIC9_DBG_BMON2_1_MAX_OFFSET 0x1000
+#define NIC9_DBG_BMON2_1_SECTION 0x7000
+#define mmNIC9_DBG_ARC_RTT1_BASE 0x7570000ull
+#define NIC9_DBG_ARC_RTT1_MAX_OFFSET 0x1400
+#define NIC9_DBG_ARC_RTT1_SECTION 0x8000
+#define mmNIC9_DBG_FUNNEL_TX_BASE 0x7578000ull
+#define NIC9_DBG_FUNNEL_TX_MAX_OFFSET 0x1000
+#define NIC9_DBG_FUNNEL_TX_SECTION 0x1000
+#define mmNIC9_DBG_FUNNEL_NCH_BASE 0x7579000ull
+#define NIC9_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000
+#define NIC9_DBG_FUNNEL_NCH_SECTION 0x7000
+#define mmNIC10_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7580000ull
+#define NIC10_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000
+#define NIC10_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000
+#define mmNIC10_DBG_STM_0_BASE 0x7581000ull
+#define NIC10_DBG_STM_0_MAX_OFFSET 0x1000
+#define NIC10_DBG_STM_0_SECTION 0x1000
+#define mmNIC10_DBG_CTI_0_BASE 0x7582000ull
+#define NIC10_DBG_CTI_0_MAX_OFFSET 0x1000
+#define NIC10_DBG_CTI_0_SECTION 0x1000
+#define mmNIC10_DBG_ETF_0_BASE 0x7583000ull
+#define NIC10_DBG_ETF_0_MAX_OFFSET 0x1000
+#define NIC10_DBG_ETF_0_SECTION 0x1000
+#define mmNIC10_DBG_SPMU_0_BASE 0x7584000ull
+#define NIC10_DBG_SPMU_0_MAX_OFFSET 0x1000
+#define NIC10_DBG_SPMU_0_SECTION 0x1000
+#define mmNIC10_DBG_USER_CTI_0_BASE 0x7585000ull
+#define NIC10_DBG_USER_CTI_0_MAX_OFFSET 0x1000
+#define NIC10_DBG_USER_CTI_0_SECTION 0x1000
+#define mmNIC10_DBG_BMON_CTI_0_BASE 0x7586000ull
+#define NIC10_DBG_BMON_CTI_0_MAX_OFFSET 0x1000
+#define NIC10_DBG_BMON_CTI_0_SECTION 0x1000
+#define mmNIC10_DBG_BMON0_0_BASE 0x7587000ull
+#define NIC10_DBG_BMON0_0_MAX_OFFSET 0x1000
+#define NIC10_DBG_BMON0_0_SECTION 0x1000
+#define mmNIC10_DBG_BMON1_0_BASE 0x7588000ull
+#define NIC10_DBG_BMON1_0_MAX_OFFSET 0x1000
+#define NIC10_DBG_BMON1_0_SECTION 0x1000
+#define mmNIC10_DBG_BMON2_0_BASE 0x7589000ull
+#define NIC10_DBG_BMON2_0_MAX_OFFSET 0x1000
+#define NIC10_DBG_BMON2_0_SECTION 0x7000
+#define mmNIC10_DBG_ARC_RTT0_BASE 0x7590000ull
+#define NIC10_DBG_ARC_RTT0_MAX_OFFSET 0x1400
+#define NIC10_DBG_ARC_RTT0_SECTION 0x10000
+#define mmNIC10_DBG_CS_DBG_ROM_TABLE_1_BASE 0x75A0000ull
+#define NIC10_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000
+#define NIC10_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000
+#define mmNIC10_DBG_STM_1_BASE 0x75A1000ull
+#define NIC10_DBG_STM_1_MAX_OFFSET 0x1000
+#define NIC10_DBG_STM_1_SECTION 0x1000
+#define mmNIC10_DBG_CTI_1_BASE 0x75A2000ull
+#define NIC10_DBG_CTI_1_MAX_OFFSET 0x1000
+#define NIC10_DBG_CTI_1_SECTION 0x1000
+#define mmNIC10_DBG_ETF_1_BASE 0x75A3000ull
+#define NIC10_DBG_ETF_1_MAX_OFFSET 0x1000
+#define NIC10_DBG_ETF_1_SECTION 0x1000
+#define mmNIC10_DBG_SPMU_1_BASE 0x75A4000ull
+#define NIC10_DBG_SPMU_1_MAX_OFFSET 0x1000
+#define NIC10_DBG_SPMU_1_SECTION 0x1000
+#define mmNIC10_DBG_USER_CTI_1_BASE 0x75A5000ull
+#define NIC10_DBG_USER_CTI_1_MAX_OFFSET 0x1000
+#define NIC10_DBG_USER_CTI_1_SECTION 0x1000
+#define mmNIC10_DBG_BMON_CTI_1_BASE 0x75A6000ull
+#define NIC10_DBG_BMON_CTI_1_MAX_OFFSET 0x1000
+#define NIC10_DBG_BMON_CTI_1_SECTION 0x1000
+#define mmNIC10_DBG_BMON0_1_BASE 0x75A7000ull
+#define NIC10_DBG_BMON0_1_MAX_OFFSET 0x1000
+#define NIC10_DBG_BMON0_1_SECTION 0x1000
+#define mmNIC10_DBG_BMON1_1_BASE 0x75A8000ull
+#define NIC10_DBG_BMON1_1_MAX_OFFSET 0x1000
+#define NIC10_DBG_BMON1_1_SECTION 0x1000
+#define mmNIC10_DBG_BMON2_1_BASE 0x75A9000ull
+#define NIC10_DBG_BMON2_1_MAX_OFFSET 0x1000
+#define NIC10_DBG_BMON2_1_SECTION 0x7000
+#define mmNIC10_DBG_ARC_RTT1_BASE 0x75B0000ull
+#define NIC10_DBG_ARC_RTT1_MAX_OFFSET 0x1400
+#define NIC10_DBG_ARC_RTT1_SECTION 0x8000
+#define mmNIC10_DBG_FUNNEL_TX_BASE 0x75B8000ull
+#define NIC10_DBG_FUNNEL_TX_MAX_OFFSET 0x1000
+#define NIC10_DBG_FUNNEL_TX_SECTION 0x1000
+#define mmNIC10_DBG_FUNNEL_NCH_BASE 0x75B9000ull
+#define NIC10_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000
+#define NIC10_DBG_FUNNEL_NCH_SECTION 0x7000
+#define mmNIC11_DBG_CS_DBG_ROM_TABLE_0_BASE 0x75C0000ull
+#define NIC11_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000
+#define NIC11_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000
+#define mmNIC11_DBG_STM_0_BASE 0x75C1000ull
+#define NIC11_DBG_STM_0_MAX_OFFSET 0x1000
+#define NIC11_DBG_STM_0_SECTION 0x1000
+#define mmNIC11_DBG_CTI_0_BASE 0x75C2000ull
+#define NIC11_DBG_CTI_0_MAX_OFFSET 0x1000
+#define NIC11_DBG_CTI_0_SECTION 0x1000
+#define mmNIC11_DBG_ETF_0_BASE 0x75C3000ull
+#define NIC11_DBG_ETF_0_MAX_OFFSET 0x1000
+#define NIC11_DBG_ETF_0_SECTION 0x1000
+#define mmNIC11_DBG_SPMU_0_BASE 0x75C4000ull
+#define NIC11_DBG_SPMU_0_MAX_OFFSET 0x1000
+#define NIC11_DBG_SPMU_0_SECTION 0x1000
+#define mmNIC11_DBG_USER_CTI_0_BASE 0x75C5000ull
+#define NIC11_DBG_USER_CTI_0_MAX_OFFSET 0x1000
+#define NIC11_DBG_USER_CTI_0_SECTION 0x1000
+#define mmNIC11_DBG_BMON_CTI_0_BASE 0x75C6000ull
+#define NIC11_DBG_BMON_CTI_0_MAX_OFFSET 0x1000
+#define NIC11_DBG_BMON_CTI_0_SECTION 0x1000
+#define mmNIC11_DBG_BMON0_0_BASE 0x75C7000ull
+#define NIC11_DBG_BMON0_0_MAX_OFFSET 0x1000
+#define NIC11_DBG_BMON0_0_SECTION 0x1000
+#define mmNIC11_DBG_BMON1_0_BASE 0x75C8000ull
+#define NIC11_DBG_BMON1_0_MAX_OFFSET 0x1000
+#define NIC11_DBG_BMON1_0_SECTION 0x1000
+#define mmNIC11_DBG_BMON2_0_BASE 0x75C9000ull
+#define NIC11_DBG_BMON2_0_MAX_OFFSET 0x1000
+#define NIC11_DBG_BMON2_0_SECTION 0x7000
+#define mmNIC11_DBG_ARC_RTT0_BASE 0x75D0000ull
+#define NIC11_DBG_ARC_RTT0_MAX_OFFSET 0x1400
+#define NIC11_DBG_ARC_RTT0_SECTION 0x10000
+#define mmNIC11_DBG_CS_DBG_ROM_TABLE_1_BASE 0x75E0000ull
+#define NIC11_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000
+#define NIC11_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000
+#define mmNIC11_DBG_STM_1_BASE 0x75E1000ull
+#define NIC11_DBG_STM_1_MAX_OFFSET 0x1000
+#define NIC11_DBG_STM_1_SECTION 0x1000
+#define mmNIC11_DBG_CTI_1_BASE 0x75E2000ull
+#define NIC11_DBG_CTI_1_MAX_OFFSET 0x1000
+#define NIC11_DBG_CTI_1_SECTION 0x1000
+#define mmNIC11_DBG_ETF_1_BASE 0x75E3000ull
+#define NIC11_DBG_ETF_1_MAX_OFFSET 0x1000
+#define NIC11_DBG_ETF_1_SECTION 0x1000
+#define mmNIC11_DBG_SPMU_1_BASE 0x75E4000ull
+#define NIC11_DBG_SPMU_1_MAX_OFFSET 0x1000
+#define NIC11_DBG_SPMU_1_SECTION 0x1000
+#define mmNIC11_DBG_USER_CTI_1_BASE 0x75E5000ull
+#define NIC11_DBG_USER_CTI_1_MAX_OFFSET 0x1000
+#define NIC11_DBG_USER_CTI_1_SECTION 0x1000
+#define mmNIC11_DBG_BMON_CTI_1_BASE 0x75E6000ull
+#define NIC11_DBG_BMON_CTI_1_MAX_OFFSET 0x1000
+#define NIC11_DBG_BMON_CTI_1_SECTION 0x1000
+#define mmNIC11_DBG_BMON0_1_BASE 0x75E7000ull
+#define NIC11_DBG_BMON0_1_MAX_OFFSET 0x1000
+#define NIC11_DBG_BMON0_1_SECTION 0x1000
+#define mmNIC11_DBG_BMON1_1_BASE 0x75E8000ull
+#define NIC11_DBG_BMON1_1_MAX_OFFSET 0x1000
+#define NIC11_DBG_BMON1_1_SECTION 0x1000
+#define mmNIC11_DBG_BMON2_1_BASE 0x75E9000ull
+#define NIC11_DBG_BMON2_1_MAX_OFFSET 0x1000
+#define NIC11_DBG_BMON2_1_SECTION 0x7000
+#define mmNIC11_DBG_ARC_RTT1_BASE 0x75F0000ull
+#define NIC11_DBG_ARC_RTT1_MAX_OFFSET 0x1400
+#define NIC11_DBG_ARC_RTT1_SECTION 0x8000
+#define mmNIC11_DBG_FUNNEL_TX_BASE 0x75F8000ull
+#define NIC11_DBG_FUNNEL_TX_MAX_OFFSET 0x1000
+#define NIC11_DBG_FUNNEL_TX_SECTION 0x1000
+#define mmNIC11_DBG_FUNNEL_NCH_BASE 0x75F9000ull
+#define NIC11_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000
+
+#endif /* GAUDI2_BLOCKS_LINUX_DRIVER_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h
new file mode 100644
index 000000000000..d21fcd3880b4
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h
@@ -0,0 +1,572 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2023 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+#ifndef ASIC_REG_GAUDI2_REGS_H_
+#define ASIC_REG_GAUDI2_REGS_H_
+
+#include "gaudi2_blocks_linux_driver.h"
+#include "psoc_reset_conf_regs.h"
+#include "psoc_global_conf_regs.h"
+#include "cpu_if_regs.h"
+#include "pcie_aux_regs.h"
+#include "pcie_dbi_regs.h"
+#include "pcie_wrap_regs.h"
+#include "pmmu_hbw_stlb_regs.h"
+#include "psoc_timestamp_regs.h"
+#include "psoc_etr_regs.h"
+#include "xbar_edge_0_regs.h"
+#include "xbar_mid_0_regs.h"
+#include "arc_farm_kdma_regs.h"
+#include "arc_farm_kdma_ctx_regs.h"
+#include "arc_farm_kdma_kdma_cgm_regs.h"
+#include "arc_farm_arc0_aux_regs.h"
+#include "arc_farm_arc0_acp_eng_regs.h"
+#include "arc_farm_kdma_ctx_axuser_regs.h"
+#include "arc_farm_arc0_dup_eng_axuser_regs.h"
+#include "arc_farm_arc0_dup_eng_regs.h"
+#include "dcore0_sync_mngr_objs_regs.h"
+#include "dcore0_sync_mngr_glbl_regs.h"
+#include "dcore0_sync_mngr_mstr_if_axuser_regs.h"
+#include "dcore1_sync_mngr_glbl_regs.h"
+#include "pdma0_qm_arc_aux_regs.h"
+#include "pdma0_core_ctx_regs.h"
+#include "pdma0_core_regs.h"
+#include "pdma0_qm_axuser_secured_regs.h"
+#include "pdma0_qm_regs.h"
+#include "pdma0_qm_cgm_regs.h"
+#include "pdma0_core_ctx_axuser_regs.h"
+#include "pdma1_core_ctx_axuser_regs.h"
+#include "pdma0_qm_axuser_nonsecured_regs.h"
+#include "pdma1_qm_axuser_nonsecured_regs.h"
+#include "dcore0_tpc0_qm_regs.h"
+#include "dcore0_tpc0_qm_cgm_regs.h"
+#include "dcore0_tpc0_qm_axuser_nonsecured_regs.h"
+#include "dcore0_tpc0_qm_arc_aux_regs.h"
+#include "dcore0_tpc0_cfg_regs.h"
+#include "dcore0_tpc0_cfg_qm_regs.h"
+#include "dcore0_tpc0_cfg_axuser_regs.h"
+#include "dcore0_tpc0_cfg_qm_sync_object_regs.h"
+#include "dcore0_tpc0_cfg_kernel_regs.h"
+#include "dcore0_tpc0_cfg_kernel_tensor_0_regs.h"
+#include "dcore0_tpc0_cfg_qm_tensor_0_regs.h"
+#include "dcore0_tpc0_cfg_special_regs.h"
+#include "dcore0_tpc0_eml_funnel_regs.h"
+#include "dcore0_tpc0_eml_etf_regs.h"
+#include "dcore0_tpc0_eml_stm_regs.h"
+#include "dcore0_tpc0_eml_busmon_0_regs.h"
+#include "dcore0_tpc0_eml_spmu_regs.h"
+#include "pmmu_pif_regs.h"
+#include "dcore0_edma0_qm_cgm_regs.h"
+#include "dcore0_edma0_core_regs.h"
+#include "dcore0_edma0_qm_regs.h"
+#include "dcore0_edma0_qm_arc_aux_regs.h"
+#include "dcore0_edma0_core_ctx_regs.h"
+#include "dcore0_edma0_core_ctx_axuser_regs.h"
+#include "dcore0_edma0_qm_axuser_nonsecured_regs.h"
+#include "dcore0_edma1_core_ctx_axuser_regs.h"
+#include "dcore0_edma1_qm_axuser_nonsecured_regs.h"
+#include "dcore0_hmmu0_stlb_regs.h"
+#include "dcore0_hmmu0_mmu_regs.h"
+#include "rot0_qm_regs.h"
+#include "rot0_qm_cgm_regs.h"
+#include "rot0_qm_arc_aux_regs.h"
+#include "rot0_regs.h"
+#include "rot0_desc_regs.h"
+#include "rot0_qm_axuser_nonsecured_regs.h"
+#include "dcore0_rtr0_mstr_if_rr_prvt_hbw_regs.h"
+#include "dcore0_rtr0_mstr_if_rr_prvt_lbw_regs.h"
+#include "dcore0_rtr0_mstr_if_rr_shrd_hbw_regs.h"
+#include "dcore0_rtr0_mstr_if_rr_shrd_lbw_regs.h"
+#include "dcore0_rtr0_ctrl_regs.h"
+#include "dcore0_dec0_cmd_regs.h"
+#include "dcore0_vdec0_brdg_ctrl_regs.h"
+#include "dcore0_vdec0_brdg_ctrl_axuser_dec_regs.h"
+#include "dcore0_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h"
+#include "dcore0_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h"
+#include "dcore0_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h"
+#include "dcore0_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h"
+#include "dcore0_vdec0_ctrl_special_regs.h"
+#include "pcie_vdec0_brdg_ctrl_axuser_dec_regs.h"
+#include "pcie_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h"
+#include "pcie_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h"
+#include "pcie_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h"
+#include "pcie_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h"
+#include "pcie_dec0_cmd_regs.h"
+#include "pcie_vdec0_brdg_ctrl_regs.h"
+#include "pcie_vdec0_ctrl_special_regs.h"
+#include "dcore0_mme_qm_regs.h"
+#include "dcore0_mme_qm_arc_aux_regs.h"
+#include "dcore0_mme_qm_axuser_secured_regs.h"
+#include "dcore0_mme_qm_cgm_regs.h"
+#include "dcore0_mme_qm_arc_acp_eng_regs.h"
+#include "dcore0_mme_qm_axuser_nonsecured_regs.h"
+#include "dcore0_mme_qm_arc_dup_eng_regs.h"
+#include "dcore0_mme_qm_arc_dup_eng_axuser_regs.h"
+#include "dcore0_mme_sbte0_mstr_if_axuser_regs.h"
+#include "dcore0_mme_wb0_mstr_if_axuser_regs.h"
+#include "dcore0_mme_acc_regs.h"
+#include "dcore0_mme_ctrl_lo_regs.h"
+#include "dcore1_mme_ctrl_lo_regs.h"
+#include "dcore3_mme_ctrl_lo_regs.h"
+#include "dcore0_mme_ctrl_lo_mme_axuser_regs.h"
+#include "dcore0_mme_ctrl_lo_arch_agu_cout0_master_regs.h"
+#include "dcore0_mme_ctrl_lo_arch_agu_cout0_slave_regs.h"
+#include "dcore0_mme_ctrl_lo_arch_agu_cout1_master_regs.h"
+#include "dcore0_mme_ctrl_lo_arch_agu_cout1_slave_regs.h"
+#include "dcore0_mme_ctrl_lo_arch_agu_in0_master_regs.h"
+#include "dcore0_mme_ctrl_lo_arch_agu_in0_slave_regs.h"
+#include "dcore0_mme_ctrl_lo_arch_agu_in1_master_regs.h"
+#include "dcore0_mme_ctrl_lo_arch_agu_in1_slave_regs.h"
+#include "dcore0_mme_ctrl_lo_arch_agu_in2_master_regs.h"
+#include "dcore0_mme_ctrl_lo_arch_agu_in2_slave_regs.h"
+#include "dcore0_mme_ctrl_lo_arch_agu_in3_master_regs.h"
+#include "dcore0_mme_ctrl_lo_arch_agu_in3_slave_regs.h"
+#include "dcore0_mme_ctrl_lo_arch_agu_in4_master_regs.h"
+#include "dcore0_mme_ctrl_lo_arch_agu_in4_slave_regs.h"
+#include "dcore0_mme_ctrl_lo_arch_base_addr_regs.h"
+#include "dcore0_mme_ctrl_lo_arch_non_tensor_end_regs.h"
+#include "dcore0_mme_ctrl_lo_arch_non_tensor_start_regs.h"
+#include "dcore0_mme_ctrl_lo_arch_tensor_a_regs.h"
+#include "dcore0_mme_ctrl_lo_arch_tensor_b_regs.h"
+#include "dcore0_mme_ctrl_lo_arch_tensor_cout_regs.h"
+#include "pcie_wrap_special_regs.h"
+
+#include "pdma0_qm_masks.h"
+#include "pdma0_core_masks.h"
+#include "pdma0_core_special_masks.h"
+#include "psoc_global_conf_masks.h"
+#include "psoc_reset_conf_masks.h"
+#include "arc_farm_kdma_masks.h"
+#include "arc_farm_kdma_ctx_masks.h"
+#include "arc_farm_arc0_aux_masks.h"
+#include "arc_farm_kdma_ctx_axuser_masks.h"
+#include "dcore0_sync_mngr_objs_masks.h"
+#include "dcore0_sync_mngr_glbl_masks.h"
+#include "dcore0_sync_mngr_mstr_if_axuser_masks.h"
+#include "dcore0_tpc0_cfg_masks.h"
+#include "dcore0_mme_ctrl_lo_masks.h"
+#include "dcore0_mme_sbte0_masks.h"
+#include "dcore0_edma0_qm_masks.h"
+#include "dcore0_edma0_core_masks.h"
+#include "dcore0_hmmu0_stlb_masks.h"
+#include "dcore0_hmmu0_mmu_masks.h"
+#include "dcore0_dec0_cmd_masks.h"
+#include "dcore0_vdec0_brdg_ctrl_masks.h"
+#include "pcie_dec0_cmd_masks.h"
+#include "pcie_vdec0_brdg_ctrl_masks.h"
+#include "rot0_masks.h"
+#include "pmmu_hbw_stlb_masks.h"
+#include "psoc_etr_masks.h"
+
+#define mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR	0x4800040
+
+#define mmDCORE0_TPC0_EML_CFG_DBG_CNT		0x40000
+
+#define SM_OBJS_PROT_BITS_OFFS			0x14000
+
+#define DCORE_OFFSET			(mmDCORE1_TPC0_QM_BASE - mmDCORE0_TPC0_QM_BASE)
+#define DCORE_EDMA_OFFSET		(mmDCORE0_EDMA1_QM_BASE - mmDCORE0_EDMA0_QM_BASE)
+#define DCORE_TPC_OFFSET		(mmDCORE0_TPC1_QM_BASE - mmDCORE0_TPC0_QM_BASE)
+#define DCORE_DEC_OFFSET		(mmDCORE0_DEC1_VSI_BASE - mmDCORE0_DEC0_VSI_BASE)
+#define DCORE_HMMU_OFFSET		(mmDCORE0_HMMU1_MMU_BASE - mmDCORE0_HMMU0_MMU_BASE)
+#define NIC_QM_OFFSET			(mmNIC0_QM1_BASE - mmNIC0_QM0_BASE)
+#define PDMA_OFFSET			(mmPDMA1_QM_BASE - mmPDMA0_QM_BASE)
+#define ROT_OFFSET			(mmROT1_BASE - mmROT0_BASE)
+
+#define TPC_CFG_BASE_ADDRESS_HIGH_OFFSET \
+			(mmDCORE0_TPC0_CFG_CFG_BASE_ADDRESS_HIGH - mmDCORE0_TPC0_CFG_BASE)
+
+#define TPC_CFG_SM_BASE_ADDRESS_HIGH_OFFSET \
+			(mmDCORE0_TPC0_CFG_SM_BASE_ADDRESS_HIGH - mmDCORE0_TPC0_CFG_BASE)
+
+#define TPC_CFG_STALL_OFFSET		(mmDCORE0_TPC0_CFG_TPC_STALL - mmDCORE0_TPC0_CFG_BASE)
+#define TPC_CFG_STALL_ON_ERR_OFFSET	(mmDCORE0_TPC0_CFG_STALL_ON_ERR - mmDCORE0_TPC0_CFG_BASE)
+#define TPC_CFG_TPC_INTR_MASK_OFFSET	(mmDCORE0_TPC0_CFG_TPC_INTR_MASK - mmDCORE0_TPC0_CFG_BASE)
+#define TPC_CFG_MSS_CONFIG_OFFSET	(mmDCORE0_TPC0_CFG_MSS_CONFIG - mmDCORE0_TPC0_CFG_BASE)
+#define TPC_EML_CFG_DBG_CNT_OFFSET	(mmDCORE0_TPC0_EML_CFG_DBG_CNT - mmDCORE0_TPC0_EML_CFG_BASE)
+
+#define EDMA_CORE_CFG_STALL_OFFSET	(mmDCORE0_EDMA0_CORE_CFG_1 - mmDCORE0_EDMA0_CORE_BASE)
+#define MME_CTRL_LO_QM_STALL_OFFSET	(mmDCORE0_MME_CTRL_LO_QM_STALL - mmDCORE0_MME_CTRL_LO_BASE)
+#define MME_ACC_INTR_MASK_OFFSET	(mmDCORE0_MME_ACC_INTR_MASK - mmDCORE0_MME_ACC_BASE)
+#define MME_ACC_WR_AXI_AGG_COUT0_OFFSET	(mmDCORE0_MME_ACC_WR_AXI_AGG_COUT0 - mmDCORE0_MME_ACC_BASE)
+#define MME_ACC_WR_AXI_AGG_COUT1_OFFSET	(mmDCORE0_MME_ACC_WR_AXI_AGG_COUT1 - mmDCORE0_MME_ACC_BASE)
+#define MME_ACC_AP_LFSR_POLY_OFFSET	(mmDCORE0_MME_ACC_AP_LFSR_POLY - mmDCORE0_MME_ACC_BASE)
+#define MME_ACC_AP_LFSR_SEED_SEL_OFFSET	(mmDCORE0_MME_ACC_AP_LFSR_SEED_SEL - mmDCORE0_MME_ACC_BASE)
+#define MME_ACC_AP_LFSR_SEED_WDATA_OFFSET \
+	(mmDCORE0_MME_ACC_AP_LFSR_SEED_WDATA - mmDCORE0_MME_ACC_BASE)
+
+#define DMA_CORE_CFG_0_OFFSET		(mmARC_FARM_KDMA_CFG_0 - mmARC_FARM_KDMA_BASE)
+#define DMA_CORE_CFG_1_OFFSET		(mmARC_FARM_KDMA_CFG_1 - mmARC_FARM_KDMA_BASE)
+#define DMA_CORE_PROT_OFFSET		(mmARC_FARM_KDMA_PROT - mmARC_FARM_KDMA_BASE)
+#define DMA_CORE_ERRMSG_ADDR_LO_OFFSET	(mmARC_FARM_KDMA_ERRMSG_ADDR_LO - mmARC_FARM_KDMA_BASE)
+#define DMA_CORE_ERRMSG_ADDR_HI_OFFSET	(mmARC_FARM_KDMA_ERRMSG_ADDR_HI - mmARC_FARM_KDMA_BASE)
+#define DMA_CORE_ERRMSG_WDATA_OFFSET	(mmARC_FARM_KDMA_ERRMSG_WDATA - mmARC_FARM_KDMA_BASE)
+
+#define QM_PQ_BASE_LO_0_OFFSET		(mmPDMA0_QM_PQ_BASE_LO_0 - mmPDMA0_QM_BASE)
+#define QM_PQ_BASE_HI_0_OFFSET		(mmPDMA0_QM_PQ_BASE_HI_0 - mmPDMA0_QM_BASE)
+#define QM_PQ_SIZE_0_OFFSET		(mmPDMA0_QM_PQ_SIZE_0 - mmPDMA0_QM_BASE)
+#define QM_PQ_PI_0_OFFSET		(mmPDMA0_QM_PQ_PI_0 - mmPDMA0_QM_BASE)
+#define QM_PQ_CI_0_OFFSET		(mmPDMA0_QM_PQ_CI_0 - mmPDMA0_QM_BASE)
+#define QM_CP_FENCE0_CNT_0_OFFSET	(mmPDMA0_QM_CP_FENCE0_CNT_0 - mmPDMA0_QM_BASE)
+
+#define QM_CP_MSG_BASE0_ADDR_LO_0_OFFSET (mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 - mmPDMA0_QM_BASE)
+#define QM_CP_MSG_BASE0_ADDR_HI_0_OFFSET (mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 - mmPDMA0_QM_BASE)
+#define QM_CP_MSG_BASE1_ADDR_LO_0_OFFSET (mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 - mmPDMA0_QM_BASE)
+#define QM_CP_MSG_BASE1_ADDR_HI_0_OFFSET (mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 - mmPDMA0_QM_BASE)
+
+#define QM_CP_CFG_OFFSET		(mmPDMA0_QM_CP_CFG - mmPDMA0_QM_BASE)
+#define QM_PQC_HBW_BASE_LO_0_OFFSET	(mmPDMA0_QM_PQC_HBW_BASE_LO_0 - mmPDMA0_QM_BASE)
+#define QM_PQC_HBW_BASE_HI_0_OFFSET	(mmPDMA0_QM_PQC_HBW_BASE_HI_0 - mmPDMA0_QM_BASE)
+#define QM_PQC_SIZE_0_OFFSET		(mmPDMA0_QM_PQC_SIZE_0 - mmPDMA0_QM_BASE)
+#define QM_PQC_PI_0_OFFSET		(mmPDMA0_QM_PQC_PI_0 - mmPDMA0_QM_BASE)
+#define QM_PQC_LBW_WDATA_0_OFFSET	(mmPDMA0_QM_PQC_LBW_WDATA_0 - mmPDMA0_QM_BASE)
+#define QM_PQC_LBW_BASE_LO_0_OFFSET	(mmPDMA0_QM_PQC_LBW_BASE_LO_0 - mmPDMA0_QM_BASE)
+#define QM_PQC_LBW_BASE_HI_0_OFFSET	(mmPDMA0_QM_PQC_LBW_BASE_HI_0 - mmPDMA0_QM_BASE)
+#define QM_GLBL_ERR_ADDR_LO_OFFSET	(mmPDMA0_QM_GLBL_ERR_ADDR_LO - mmPDMA0_QM_BASE)
+#define QM_PQC_CFG_OFFSET		(mmPDMA0_QM_PQC_CFG - mmPDMA0_QM_BASE)
+#define QM_ARB_CFG_0_OFFSET		(mmPDMA0_QM_ARB_CFG_0 - mmPDMA0_QM_BASE)
+#define QM_GLBL_CFG0_OFFSET		(mmPDMA0_QM_GLBL_CFG0 -	mmPDMA0_QM_BASE)
+#define QM_GLBL_CFG1_OFFSET		(mmPDMA0_QM_GLBL_CFG1 - mmPDMA0_QM_BASE)
+#define QM_GLBL_CFG2_OFFSET		(mmPDMA0_QM_GLBL_CFG2 - mmPDMA0_QM_BASE)
+#define QM_GLBL_PROT_OFFSET		(mmPDMA0_QM_GLBL_PROT -	mmPDMA0_QM_BASE)
+#define QM_GLBL_ERR_CFG_OFFSET		(mmPDMA0_QM_GLBL_ERR_CFG - mmPDMA0_QM_BASE)
+#define QM_GLBL_ERR_CFG1_OFFSET		(mmPDMA0_QM_GLBL_ERR_CFG1 - mmPDMA0_QM_BASE)
+#define QM_GLBL_ERR_ADDR_HI_OFFSET	(mmPDMA0_QM_GLBL_ERR_ADDR_HI - mmPDMA0_QM_BASE)
+#define QM_GLBL_ERR_WDATA_OFFSET	(mmPDMA0_QM_GLBL_ERR_WDATA - mmPDMA0_QM_BASE)
+#define QM_ARB_ERR_MSG_EN_OFFSET	(mmPDMA0_QM_ARB_ERR_MSG_EN - mmPDMA0_QM_BASE)
+#define QM_ARB_SLV_CHOISE_WDT_OFFSET	(mmPDMA0_QM_ARB_SLV_CHOICE_WDT - mmPDMA0_QM_BASE)
+#define QM_FENCE2_OFFSET		(mmPDMA0_QM_CP_FENCE2_RDATA_0 - mmPDMA0_QM_BASE)
+#define QM_SEI_STATUS_OFFSET		(mmPDMA0_QM_SEI_STATUS - mmPDMA0_QM_BASE)
+
+#define QM_CQ_TSIZE_STS_4_OFFSET	(mmPDMA0_QM_CQ_TSIZE_STS_4 - mmPDMA0_QM_BASE)
+#define QM_CQ_PTR_LO_STS_4_OFFSET	(mmPDMA0_QM_CQ_PTR_LO_STS_4 - mmPDMA0_QM_BASE)
+#define QM_CQ_PTR_HI_STS_4_OFFSET	(mmPDMA0_QM_CQ_PTR_HI_STS_4 - mmPDMA0_QM_BASE)
+
+#define QM_ARC_CQ_TSIZE_STS_OFFSET	(mmPDMA0_QM_ARC_CQ_TSIZE_STS - mmPDMA0_QM_BASE)
+#define QM_ARC_CQ_PTR_LO_STS_OFFSET	(mmPDMA0_QM_ARC_CQ_PTR_LO_STS - mmPDMA0_QM_BASE)
+#define QM_ARC_CQ_PTR_HI_STS_OFFSET	(mmPDMA0_QM_ARC_CQ_PTR_HI_STS - mmPDMA0_QM_BASE)
+
+#define QM_CP_STS_4_OFFSET		(mmPDMA0_QM_CP_STS_4 - mmPDMA0_QM_BASE)
+#define QM_CP_CURRENT_INST_LO_4_OFFSET	(mmPDMA0_QM_CP_CURRENT_INST_LO_4 - mmPDMA0_QM_BASE)
+#define QM_CP_CURRENT_INST_HI_4_OFFSET	(mmPDMA0_QM_CP_CURRENT_INST_HI_4 - mmPDMA0_QM_BASE)
+
+#define SFT_OFFSET		(mmSFT1_HBW_RTR_IF0_RTR_H3_BASE - mmSFT0_HBW_RTR_IF0_RTR_H3_BASE)
+#define SFT_IF_RTR_OFFSET	(mmSFT0_HBW_RTR_IF1_RTR_H3_BASE - mmSFT0_HBW_RTR_IF0_RTR_H3_BASE)
+
+#define ARC_HALT_REQ_OFFSET	(mmARC_FARM_ARC0_AUX_RUN_HALT_REQ - mmARC_FARM_ARC0_AUX_BASE)
+#define ARC_HALT_ACK_OFFSET	(mmARC_FARM_ARC0_AUX_RUN_HALT_ACK - mmARC_FARM_ARC0_AUX_BASE)
+
+#define ARC_REGION_CFG_OFFSET(region) \
+	(mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_0 + (region * 4) - mmARC_FARM_ARC0_AUX_BASE)
+
+#define ARC_DCCM_UPPER_EN_OFFSET \
+	(mmARC_FARM_ARC0_AUX_MME_ARC_UPPER_DCCM_EN - mmARC_FARM_ARC0_AUX_BASE)
+
+#define PCIE_VDEC_OFFSET	\
+	(mmPCIE_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE - mmPCIE_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE)
+
+#define DCORE_MME_SBTE_OFFSET	\
+	(mmDCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_BASE)
+
+#define DCORE_MME_WB_OFFSET	\
+	(mmDCORE0_MME_WB1_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_MME_WB0_MSTR_IF_RR_SHRD_HBW_BASE)
+
+#define DCORE_RTR_OFFSET	\
+	(mmDCORE0_RTR1_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
+
+#define DCORE_VDEC_OFFSET	\
+	(mmDCORE0_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE)
+
+#define MMU_OFFSET(REG)			(REG - mmDCORE0_HMMU0_MMU_BASE)
+#define MMU_BYPASS_OFFSET		MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_BYPASS)
+#define MMU_SPI_SEI_MASK_OFFSET		MMU_OFFSET(mmDCORE0_HMMU0_MMU_SPI_SEI_MASK)
+#define MMU_SPI_SEI_CAUSE_OFFSET	MMU_OFFSET(mmDCORE0_HMMU0_MMU_SPI_SEI_CAUSE)
+#define MMU_ENABLE_OFFSET		MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_ENABLE)
+#define MMU_DDR_RANGE_REG_ENABLE	MMU_OFFSET(mmDCORE0_HMMU0_MMU_DDR_RANGE_REG_ENABLE)
+#define MMU_RR_SEC_MIN_63_32_0_OFFSET	MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_0)
+#define MMU_RR_SEC_MIN_31_0_0_OFFSET	MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_0)
+#define MMU_RR_SEC_MAX_63_32_0_OFFSET	MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_0)
+#define MMU_RR_SEC_MAX_31_0_0_OFFSET	MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_0)
+#define MMU_RR_PRIV_MIN_63_32_0_OFFSET	MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_0)
+#define MMU_RR_PRIV_MIN_31_0_0_OFFSET	MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_0)
+#define MMU_RR_PRIV_MAX_63_32_0_OFFSET	MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_0)
+#define MMU_RR_PRIV_MAX_31_0_0_OFFSET	MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_0)
+#define MMU_INTERRUPT_CLR_OFFSET	MMU_OFFSET(mmDCORE0_HMMU0_MMU_INTERRUPT_CLR)
+
+#define STLB_OFFSET(REG)		(REG - mmDCORE0_HMMU0_STLB_BASE)
+#define STLB_BUSY_OFFSET		STLB_OFFSET(mmDCORE0_HMMU0_STLB_BUSY)
+#define STLB_ASID_OFFSET		STLB_OFFSET(mmDCORE0_HMMU0_STLB_ASID)
+#define STLB_HOP0_PA43_12_OFFSET	STLB_OFFSET(mmDCORE0_HMMU0_STLB_HOP0_PA43_12)
+#define STLB_HOP0_PA63_44_OFFSET	STLB_OFFSET(mmDCORE0_HMMU0_STLB_HOP0_PA63_44)
+#define STLB_HOP_CONFIGURATION_OFFSET	STLB_OFFSET(mmDCORE0_HMMU0_STLB_HOP_CONFIGURATION)
+#define STLB_INV_ALL_START_OFFSET	STLB_OFFSET(mmDCORE0_HMMU0_STLB_INV_ALL_START)
+#define STLB_SRAM_INIT_OFFSET		STLB_OFFSET(mmDCORE0_HMMU0_STLB_SRAM_INIT)
+#define STLB_SET_THRESHOLD_HOP3_OFFSET	STLB_OFFSET(mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3)
+#define STLB_SET_THRESHOLD_HOP2_OFFSET	STLB_OFFSET(mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2)
+#define STLB_SET_THRESHOLD_HOP1_OFFSET	STLB_OFFSET(mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1)
+#define STLB_SET_THRESHOLD_HOP0_OFFSET	STLB_OFFSET(mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0)
+#define STLB_RANGE_INV_START_LSB_OFFSET	STLB_OFFSET(mmDCORE0_HMMU0_STLB_RANGE_INV_START_LSB)
+#define STLB_RANGE_INV_START_MSB_OFFSET	STLB_OFFSET(mmDCORE0_HMMU0_STLB_RANGE_INV_START_MSB)
+#define STLB_RANGE_INV_END_LSB_OFFSET	STLB_OFFSET(mmDCORE0_HMMU0_STLB_RANGE_INV_END_LSB)
+#define STLB_RANGE_INV_END_MSB_OFFSET	STLB_OFFSET(mmDCORE0_HMMU0_STLB_RANGE_INV_END_MSB)
+
+#define STLB_LL_LOOKUP_MASK_63_32_OFFSET	\
+			STLB_OFFSET(mmDCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_63_32)
+
+#define STLB_RANGE_CACHE_INVALIDATION_OFFSET	\
+			STLB_OFFSET(mmDCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION)
+
+/* RTR CTR RAZWI related offsets */
+#define RTR_MSTR_IF_OFFSET	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_RTR0_CTRL_BASE)
+
+#define RTR_LBW_MSTR_IF_OFFSET	\
+			(mmSFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_RTR0_CTRL_BASE)
+
+/* RAZWI captured hbw aw addr high */
+#define DEC_RAZWI_HBW_AW_ADDR_HI	\
+			(mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_HI_ADDR - mmDCORE0_RTR0_CTRL_BASE)
+
+/* RAZWI captured hbw aw addr low */
+#define DEC_RAZWI_HBW_AW_ADDR_LO	\
+			(mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_LO_ADDR - mmDCORE0_RTR0_CTRL_BASE)
+
+/* RAZWI captured hbw aw set */
+#define DEC_RAZWI_HBW_AW_SET		\
+			(mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_SET - mmDCORE0_RTR0_CTRL_BASE)
+
+/* RAZWI captured hbw ar addr high */
+#define DEC_RAZWI_HBW_AR_ADDR_HI \
+			(mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AR_HI_ADDR - mmDCORE0_RTR0_CTRL_BASE)
+
+/* RAZWI captured hbw ar addr low */
+#define DEC_RAZWI_HBW_AR_ADDR_LO	\
+			(mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AR_LO_ADDR - mmDCORE0_RTR0_CTRL_BASE)
+
+/* RAZWI captured hbw ar set */
+#define DEC_RAZWI_HBW_AR_SET		\
+			(mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AR_SET - mmDCORE0_RTR0_CTRL_BASE)
+
+/* RAZWI captured lbw aw addr */
+#define DEC_RAZWI_LBW_AW_ADDR		\
+			(mmDCORE0_RTR0_CTRL_DEC_RAZWI_LBW_AW_ADDR - mmDCORE0_RTR0_CTRL_BASE)
+
+/* RAZWI captured lbw aw set */
+#define DEC_RAZWI_LBW_AW_SET		\
+			(mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_SET - mmDCORE0_RTR0_CTRL_BASE)
+
+/* RAZWI captured lbw ar addr */
+#define DEC_RAZWI_LBW_AR_ADDR		\
+			(mmDCORE0_RTR0_CTRL_DEC_RAZWI_LBW_AR_ADDR - mmDCORE0_RTR0_CTRL_BASE)
+
+/* RAZWI captured lbw ar set */
+#define DEC_RAZWI_LBW_AR_SET		\
+			(mmDCORE0_RTR0_CTRL_DEC_RAZWI_LBW_AR_SET - mmDCORE0_RTR0_CTRL_BASE)
+
+/* RAZWI captured shared hbw aw addr high */
+#define RR_SHRD_HBW_AW_RAZWI_HI		\
+	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_HI - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
+
+/* RAZWI captured shared hbw aw addr low */
+#define RR_SHRD_HBW_AW_RAZWI_LO		\
+	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_LO - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
+
+/* RAZWI captured shared hbw ar addr high */
+#define RR_SHRD_HBW_AR_RAZWI_HI		\
+	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_HI - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
+
+/* RAZWI captured shared hbw ar addr low */
+#define RR_SHRD_HBW_AR_RAZWI_LO		\
+	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_LO - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
+
+/* RAZWI captured shared aw XY coordinates */
+#define RR_SHRD_HBW_AW_RAZWI_XY		\
+	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_XY - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
+
+/* RAZWI captured shared ar XY coordinates */
+#define RR_SHRD_HBW_AR_RAZWI_XY		\
+	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_XY - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
+
+/* RAZWI hbw shared occurred due to write access */
+#define RR_SHRD_HBW_AW_RAZWI_HAPPENED	\
+			(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_HAPPENED - \
+				mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
+
+/* RAZWI hbw shared occurred due to read access */
+#define RR_SHRD_HBW_AR_RAZWI_HAPPENED	\
+			(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_HAPPENED - \
+				mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
+
+/* RAZWI captured shared lbw aw addr */
+#define RR_SHRD_LBW_AW_RAZWI		\
+			(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AW_RAZWI - \
+					mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
+
+/* RAZWI captured shared lbw ar addr */
+#define RR_SHRD_LBW_AR_RAZWI		\
+			(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AR_RAZWI - \
+					mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
+
+/* RAZWI captured shared lbw aw XY coordinates */
+#define RR_SHRD_LBW_AW_RAZWI_XY		\
+			(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AW_RAZWI_XY - \
+					mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
+
+/* RAZWI captured shared lbw ar XY coordinates */
+#define RR_SHRD_LBW_AR_RAZWI_XY		\
+			(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AR_RAZWI_XY - \
+					mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
+
+/* RAZWI lbw shared occurred due to write access */
+#define RR_SHRD_LBW_AW_RAZWI_HAPPENED	\
+			(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AW_RAZWI_HAPPENED - \
+					mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
+
+/* RAZWI lbw shared occurred due to read access */
+#define RR_SHRD_LBW_AR_RAZWI_HAPPENED	\
+			(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AR_RAZWI_HAPPENED - \
+				mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
+
+#define BRDG_CTRL_BLOCK_OFFSET (mmDCORE0_VDEC0_BRDG_CTRL_BASE - mmDCORE0_DEC0_CMD_BASE)
+#define SPECIAL_BLOCK_OFFSET (mmDCORE0_VDEC0_BRDG_CTRL_SPECIAL_BASE - mmDCORE0_DEC0_CMD_BASE)
+#define SFT_DCORE_OFFSET (mmSFT1_HBW_RTR_IF0_RTR_CTRL_BASE - mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE)
+#define SFT_IF_OFFSET (mmSFT0_HBW_RTR_IF1_RTR_CTRL_BASE - mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE)
+
+#define BRDG_CTRL_NRM_MSIX_LBW_AWADDR	\
+	(mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR - mmDCORE0_VDEC0_BRDG_CTRL_BASE)
+
+#define BRDG_CTRL_NRM_MSIX_LBW_WDATA	\
+	(mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA - mmDCORE0_VDEC0_BRDG_CTRL_BASE)
+
+#define BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR	\
+	(mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR - mmDCORE0_VDEC0_BRDG_CTRL_BASE)
+
+#define BRDG_CTRL_ABNRM_MSIX_LBW_WDATA	\
+	(mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA - mmDCORE0_VDEC0_BRDG_CTRL_BASE)
+
+#define RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_0_OFFSET	\
+	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_0 - \
+			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
+
+#define RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_0_OFFSET	\
+	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_0 - \
+			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
+
+#define RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_0_OFFSET	\
+	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_0 - \
+			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
+
+#define RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_0_OFFSET	\
+	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_0 - \
+			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
+
+#define RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_0_OFFSET	\
+	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_0 - \
+			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
+
+#define RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_0_OFFSET	\
+	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_0 - \
+			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
+
+#define RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_0_OFFSET	\
+	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_0 - \
+			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
+
+#define RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_0_OFFSET	\
+	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_0 - \
+			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
+
+#define RR_SHRD_HBW_SEC_RANGE_MIN_HI_0_OFFSET	\
+	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_HI_0 - \
+			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
+
+#define RR_SHRD_HBW_SEC_RANGE_MIN_LO_0_OFFSET	\
+	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_LO_0 - \
+			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
+
+#define RR_SHRD_HBW_SEC_RANGE_MAX_HI_0_OFFSET	\
+	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_HI_0 - \
+			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
+
+#define RR_SHRD_HBW_SEC_RANGE_MAX_LO_0_OFFSET	\
+	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_LO_0 - \
+			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
+
+#define RR_SHRD_HBW_PRIV_RANGE_MIN_HI_0_OFFSET	\
+	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_HI_0 - \
+			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
+
+#define RR_SHRD_HBW_PRIV_RANGE_MIN_LO_0_OFFSET	\
+	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_LO_0 - \
+			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
+
+#define RR_SHRD_HBW_PRIV_RANGE_MAX_HI_0_OFFSET	\
+	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_HI_0 - \
+			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
+
+#define RR_SHRD_HBW_PRIV_RANGE_MAX_LO_0_OFFSET	\
+	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_LO_0 - \
+			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
+
+#define RR_LBW_SEC_RANGE_MIN_SHORT_0_OFFSET	\
+		(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_0 - \
+			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE)
+
+#define RR_LBW_SEC_RANGE_MAX_SHORT_0_OFFSET	\
+		(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_0 - \
+			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE)
+
+#define RR_LBW_PRIV_RANGE_MIN_SHORT_0_OFFSET	\
+		(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_0 - \
+			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE)
+
+#define RR_LBW_PRIV_RANGE_MAX_SHORT_0_OFFSET	\
+		(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_0 - \
+			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE)
+
+#define RR_LBW_SEC_RANGE_MIN_0_OFFSET	\
+		(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_0 - \
+			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE)
+
+#define RR_LBW_SEC_RANGE_MAX_0_OFFSET	\
+		(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_0 - \
+			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE)
+
+#define RR_LBW_PRIV_RANGE_MIN_0_OFFSET	\
+		(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_0 - \
+			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE)
+
+#define RR_LBW_PRIV_RANGE_MAX_0_OFFSET	\
+		(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_0 - \
+			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE)
+
+#define ARC_AUX_DCCM_QUEUE_PUSH_REG_0_OFFSET	\
+		(mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG_0 - mmARC_FARM_ARC0_AUX_BASE)
+
+#define MMU_STATIC_MULTI_PAGE_SIZE_OFFSET	\
+	(mmDCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE - mmDCORE0_HMMU0_MMU_BASE)
+
+#define HBM_MC_SPI_TEMP_PIN_CHG_MASK		BIT(0)
+#define HBM_MC_SPI_THR_ENG_MASK			BIT(1)
+#define HBM_MC_SPI_THR_DIS_ENG_MASK		BIT(2)
+#define HBM_MC_SPI_IEEE1500_COMP_MASK		BIT(3)
+#define HBM_MC_SPI_IEEE1500_PAUSED_MASK		BIT(4)
+
+#define ARC_FARM_OFFSET (mmARC_FARM_ARC1_AUX_BASE - mmARC_FARM_ARC0_AUX_BASE)
+
+#include "nic0_qpc0_regs.h"
+#include "nic0_qm0_regs.h"
+#include "nic0_qm_arc_aux0_regs.h"
+#include "nic0_qm0_cgm_regs.h"
+#include "nic0_umr0_0_completion_queue_ci_1_regs.h"
+#include "nic0_umr0_0_unsecure_doorbell0_regs.h"
+
+#define NIC_OFFSET		(mmNIC1_MSTR_IF_RR_SHRD_HBW_BASE - mmNIC0_MSTR_IF_RR_SHRD_HBW_BASE)
+
+#define NIC_UMR_OFFSET \
+	(mmNIC0_UMR0_1_UNSECURE_DOORBELL0_BASE - mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE)
+
+#endif /* ASIC_REG_GAUDI2_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_qm0_cgm_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_qm0_cgm_regs.h
new file mode 100644
index 000000000000..d49906a68511
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_qm0_cgm_regs.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_QM0_CGM_REGS_H_
+#define ASIC_REG_NIC0_QM0_CGM_REGS_H_
+
+/*
+ *****************************************
+ *   NIC0_QM0_CGM
+ *   (Prototype: QMAN_CGM)
+ *****************************************
+ */
+
+#define mmNIC0_QM0_CGM_CFG 0x541AD80
+
+#define mmNIC0_QM0_CGM_STS 0x541AD84
+
+#define mmNIC0_QM0_CGM_CFG1 0x541AD88
+
+#endif /* ASIC_REG_NIC0_QM0_CGM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_qm0_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_qm0_regs.h
new file mode 100644
index 000000000000..acb19c1cd4bd
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_qm0_regs.h
@@ -0,0 +1,1057 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_QM0_REGS_H_
+#define ASIC_REG_NIC0_QM0_REGS_H_
+
+/*
+ *****************************************
+ *   NIC0_QM0
+ *   (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmNIC0_QM0_GLBL_CFG0 0x541A000
+
+#define mmNIC0_QM0_GLBL_CFG1 0x541A004
+
+#define mmNIC0_QM0_GLBL_CFG2 0x541A008
+
+#define mmNIC0_QM0_GLBL_ERR_CFG 0x541A00C
+
+#define mmNIC0_QM0_GLBL_ERR_CFG1 0x541A010
+
+#define mmNIC0_QM0_GLBL_ERR_ARC_HALT_EN 0x541A014
+
+#define mmNIC0_QM0_GLBL_AXCACHE 0x541A018
+
+#define mmNIC0_QM0_GLBL_STS0 0x541A01C
+
+#define mmNIC0_QM0_GLBL_STS1 0x541A020
+
+#define mmNIC0_QM0_GLBL_ERR_STS_0 0x541A024
+
+#define mmNIC0_QM0_GLBL_ERR_STS_1 0x541A028
+
+#define mmNIC0_QM0_GLBL_ERR_STS_2 0x541A02C
+
+#define mmNIC0_QM0_GLBL_ERR_STS_3 0x541A030
+
+#define mmNIC0_QM0_GLBL_ERR_STS_4 0x541A034
+
+#define mmNIC0_QM0_GLBL_ERR_MSG_EN_0 0x541A038
+
+#define mmNIC0_QM0_GLBL_ERR_MSG_EN_1 0x541A03C
+
+#define mmNIC0_QM0_GLBL_ERR_MSG_EN_2 0x541A040
+
+#define mmNIC0_QM0_GLBL_ERR_MSG_EN_3 0x541A044
+
+#define mmNIC0_QM0_GLBL_ERR_MSG_EN_4 0x541A048
+
+#define mmNIC0_QM0_GLBL_PROT 0x541A04C
+
+#define mmNIC0_QM0_PQ_BASE_LO_0 0x541A050
+
+#define mmNIC0_QM0_PQ_BASE_LO_1 0x541A054
+
+#define mmNIC0_QM0_PQ_BASE_LO_2 0x541A058
+
+#define mmNIC0_QM0_PQ_BASE_LO_3 0x541A05C
+
+#define mmNIC0_QM0_PQ_BASE_HI_0 0x541A060
+
+#define mmNIC0_QM0_PQ_BASE_HI_1 0x541A064
+
+#define mmNIC0_QM0_PQ_BASE_HI_2 0x541A068
+
+#define mmNIC0_QM0_PQ_BASE_HI_3 0x541A06C
+
+#define mmNIC0_QM0_PQ_SIZE_0 0x541A070
+
+#define mmNIC0_QM0_PQ_SIZE_1 0x541A074
+
+#define mmNIC0_QM0_PQ_SIZE_2 0x541A078
+
+#define mmNIC0_QM0_PQ_SIZE_3 0x541A07C
+
+#define mmNIC0_QM0_PQ_PI_0 0x541A080
+
+#define mmNIC0_QM0_PQ_PI_1 0x541A084
+
+#define mmNIC0_QM0_PQ_PI_2 0x541A088
+
+#define mmNIC0_QM0_PQ_PI_3 0x541A08C
+
+#define mmNIC0_QM0_PQ_CI_0 0x541A090
+
+#define mmNIC0_QM0_PQ_CI_1 0x541A094
+
+#define mmNIC0_QM0_PQ_CI_2 0x541A098
+
+#define mmNIC0_QM0_PQ_CI_3 0x541A09C
+
+#define mmNIC0_QM0_PQ_CFG0_0 0x541A0A0
+
+#define mmNIC0_QM0_PQ_CFG0_1 0x541A0A4
+
+#define mmNIC0_QM0_PQ_CFG0_2 0x541A0A8
+
+#define mmNIC0_QM0_PQ_CFG0_3 0x541A0AC
+
+#define mmNIC0_QM0_PQ_CFG1_0 0x541A0B0
+
+#define mmNIC0_QM0_PQ_CFG1_1 0x541A0B4
+
+#define mmNIC0_QM0_PQ_CFG1_2 0x541A0B8
+
+#define mmNIC0_QM0_PQ_CFG1_3 0x541A0BC
+
+#define mmNIC0_QM0_PQ_STS0_0 0x541A0C0
+
+#define mmNIC0_QM0_PQ_STS0_1 0x541A0C4
+
+#define mmNIC0_QM0_PQ_STS0_2 0x541A0C8
+
+#define mmNIC0_QM0_PQ_STS0_3 0x541A0CC
+
+#define mmNIC0_QM0_PQ_STS1_0 0x541A0D0
+
+#define mmNIC0_QM0_PQ_STS1_1 0x541A0D4
+
+#define mmNIC0_QM0_PQ_STS1_2 0x541A0D8
+
+#define mmNIC0_QM0_PQ_STS1_3 0x541A0DC
+
+#define mmNIC0_QM0_CQ_CFG0_0 0x541A0E0
+
+#define mmNIC0_QM0_CQ_CFG0_1 0x541A0E4
+
+#define mmNIC0_QM0_CQ_CFG0_2 0x541A0E8
+
+#define mmNIC0_QM0_CQ_CFG0_3 0x541A0EC
+
+#define mmNIC0_QM0_CQ_CFG0_4 0x541A0F0
+
+#define mmNIC0_QM0_CQ_STS0_0 0x541A0F4
+
+#define mmNIC0_QM0_CQ_STS0_1 0x541A0F8
+
+#define mmNIC0_QM0_CQ_STS0_2 0x541A0FC
+
+#define mmNIC0_QM0_CQ_STS0_3 0x541A100
+
+#define mmNIC0_QM0_CQ_STS0_4 0x541A104
+
+#define mmNIC0_QM0_CQ_CFG1_0 0x541A108
+
+#define mmNIC0_QM0_CQ_CFG1_1 0x541A10C
+
+#define mmNIC0_QM0_CQ_CFG1_2 0x541A110
+
+#define mmNIC0_QM0_CQ_CFG1_3 0x541A114
+
+#define mmNIC0_QM0_CQ_CFG1_4 0x541A118
+
+#define mmNIC0_QM0_CQ_STS1_0 0x541A11C
+
+#define mmNIC0_QM0_CQ_STS1_1 0x541A120
+
+#define mmNIC0_QM0_CQ_STS1_2 0x541A124
+
+#define mmNIC0_QM0_CQ_STS1_3 0x541A128
+
+#define mmNIC0_QM0_CQ_STS1_4 0x541A12C
+
+#define mmNIC0_QM0_CQ_PTR_LO_0 0x541A150
+
+#define mmNIC0_QM0_CQ_PTR_HI_0 0x541A154
+
+#define mmNIC0_QM0_CQ_TSIZE_0 0x541A158
+
+#define mmNIC0_QM0_CQ_CTL_0 0x541A15C
+
+#define mmNIC0_QM0_CQ_PTR_LO_1 0x541A160
+
+#define mmNIC0_QM0_CQ_PTR_HI_1 0x541A164
+
+#define mmNIC0_QM0_CQ_TSIZE_1 0x541A168
+
+#define mmNIC0_QM0_CQ_CTL_1 0x541A16C
+
+#define mmNIC0_QM0_CQ_PTR_LO_2 0x541A170
+
+#define mmNIC0_QM0_CQ_PTR_HI_2 0x541A174
+
+#define mmNIC0_QM0_CQ_TSIZE_2 0x541A178
+
+#define mmNIC0_QM0_CQ_CTL_2 0x541A17C
+
+#define mmNIC0_QM0_CQ_PTR_LO_3 0x541A180
+
+#define mmNIC0_QM0_CQ_PTR_HI_3 0x541A184
+
+#define mmNIC0_QM0_CQ_TSIZE_3 0x541A188
+
+#define mmNIC0_QM0_CQ_CTL_3 0x541A18C
+
+#define mmNIC0_QM0_CQ_PTR_LO_4 0x541A190
+
+#define mmNIC0_QM0_CQ_PTR_HI_4 0x541A194
+
+#define mmNIC0_QM0_CQ_TSIZE_4 0x541A198
+
+#define mmNIC0_QM0_CQ_CTL_4 0x541A19C
+
+#define mmNIC0_QM0_CQ_TSIZE_STS_0 0x541A1A0
+
+#define mmNIC0_QM0_CQ_TSIZE_STS_1 0x541A1A4
+
+#define mmNIC0_QM0_CQ_TSIZE_STS_2 0x541A1A8
+
+#define mmNIC0_QM0_CQ_TSIZE_STS_3 0x541A1AC
+
+#define mmNIC0_QM0_CQ_TSIZE_STS_4 0x541A1B0
+
+#define mmNIC0_QM0_CQ_PTR_LO_STS_0 0x541A1B4
+
+#define mmNIC0_QM0_CQ_PTR_LO_STS_1 0x541A1B8
+
+#define mmNIC0_QM0_CQ_PTR_LO_STS_2 0x541A1BC
+
+#define mmNIC0_QM0_CQ_PTR_LO_STS_3 0x541A1C0
+
+#define mmNIC0_QM0_CQ_PTR_LO_STS_4 0x541A1C4
+
+#define mmNIC0_QM0_CQ_PTR_HI_STS_0 0x541A1C8
+
+#define mmNIC0_QM0_CQ_PTR_HI_STS_1 0x541A1CC
+
+#define mmNIC0_QM0_CQ_PTR_HI_STS_2 0x541A1D0
+
+#define mmNIC0_QM0_CQ_PTR_HI_STS_3 0x541A1D4
+
+#define mmNIC0_QM0_CQ_PTR_HI_STS_4 0x541A1D8
+
+#define mmNIC0_QM0_CQ_IFIFO_STS_0 0x541A1DC
+
+#define mmNIC0_QM0_CQ_IFIFO_STS_1 0x541A1E0
+
+#define mmNIC0_QM0_CQ_IFIFO_STS_2 0x541A1E4
+
+#define mmNIC0_QM0_CQ_IFIFO_STS_3 0x541A1E8
+
+#define mmNIC0_QM0_CQ_IFIFO_STS_4 0x541A1EC
+
+#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_0 0x541A1F0
+
+#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_1 0x541A1F4
+
+#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_2 0x541A1F8
+
+#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_3 0x541A1FC
+
+#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_4 0x541A200
+
+#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_0 0x541A204
+
+#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_1 0x541A208
+
+#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_2 0x541A20C
+
+#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_3 0x541A210
+
+#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_4 0x541A214
+
+#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_0 0x541A218
+
+#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_1 0x541A21C
+
+#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_2 0x541A220
+
+#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_3 0x541A224
+
+#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_4 0x541A228
+
+#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_0 0x541A22C
+
+#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_1 0x541A230
+
+#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_2 0x541A234
+
+#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_3 0x541A238
+
+#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_4 0x541A23C
+
+#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_0 0x541A240
+
+#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_1 0x541A244
+
+#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_2 0x541A248
+
+#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_3 0x541A24C
+
+#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_4 0x541A250
+
+#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_0 0x541A254
+
+#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_1 0x541A258
+
+#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_2 0x541A25C
+
+#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_3 0x541A260
+
+#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_4 0x541A264
+
+#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_0 0x541A268
+
+#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_1 0x541A26C
+
+#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_2 0x541A270
+
+#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_3 0x541A274
+
+#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_4 0x541A278
+
+#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_0 0x541A27C
+
+#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_1 0x541A280
+
+#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_2 0x541A284
+
+#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_3 0x541A288
+
+#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_4 0x541A28C
+
+#define mmNIC0_QM0_CP_FENCE0_RDATA_0 0x541A290
+
+#define mmNIC0_QM0_CP_FENCE0_RDATA_1 0x541A294
+
+#define mmNIC0_QM0_CP_FENCE0_RDATA_2 0x541A298
+
+#define mmNIC0_QM0_CP_FENCE0_RDATA_3 0x541A29C
+
+#define mmNIC0_QM0_CP_FENCE0_RDATA_4 0x541A2A0
+
+#define mmNIC0_QM0_CP_FENCE1_RDATA_0 0x541A2A4
+
+#define mmNIC0_QM0_CP_FENCE1_RDATA_1 0x541A2A8
+
+#define mmNIC0_QM0_CP_FENCE1_RDATA_2 0x541A2AC
+
+#define mmNIC0_QM0_CP_FENCE1_RDATA_3 0x541A2B0
+
+#define mmNIC0_QM0_CP_FENCE1_RDATA_4 0x541A2B4
+
+#define mmNIC0_QM0_CP_FENCE2_RDATA_0 0x541A2B8
+
+#define mmNIC0_QM0_CP_FENCE2_RDATA_1 0x541A2BC
+
+#define mmNIC0_QM0_CP_FENCE2_RDATA_2 0x541A2C0
+
+#define mmNIC0_QM0_CP_FENCE2_RDATA_3 0x541A2C4
+
+#define mmNIC0_QM0_CP_FENCE2_RDATA_4 0x541A2C8
+
+#define mmNIC0_QM0_CP_FENCE3_RDATA_0 0x541A2CC
+
+#define mmNIC0_QM0_CP_FENCE3_RDATA_1 0x541A2D0
+
+#define mmNIC0_QM0_CP_FENCE3_RDATA_2 0x541A2D4
+
+#define mmNIC0_QM0_CP_FENCE3_RDATA_3 0x541A2D8
+
+#define mmNIC0_QM0_CP_FENCE3_RDATA_4 0x541A2DC
+
+#define mmNIC0_QM0_CP_FENCE0_CNT_0 0x541A2E0
+
+#define mmNIC0_QM0_CP_FENCE0_CNT_1 0x541A2E4
+
+#define mmNIC0_QM0_CP_FENCE0_CNT_2 0x541A2E8
+
+#define mmNIC0_QM0_CP_FENCE0_CNT_3 0x541A2EC
+
+#define mmNIC0_QM0_CP_FENCE0_CNT_4 0x541A2F0
+
+#define mmNIC0_QM0_CP_FENCE1_CNT_0 0x541A2F4
+
+#define mmNIC0_QM0_CP_FENCE1_CNT_1 0x541A2F8
+
+#define mmNIC0_QM0_CP_FENCE1_CNT_2 0x541A2FC
+
+#define mmNIC0_QM0_CP_FENCE1_CNT_3 0x541A300
+
+#define mmNIC0_QM0_CP_FENCE1_CNT_4 0x541A304
+
+#define mmNIC0_QM0_CP_FENCE2_CNT_0 0x541A308
+
+#define mmNIC0_QM0_CP_FENCE2_CNT_1 0x541A30C
+
+#define mmNIC0_QM0_CP_FENCE2_CNT_2 0x541A310
+
+#define mmNIC0_QM0_CP_FENCE2_CNT_3 0x541A314
+
+#define mmNIC0_QM0_CP_FENCE2_CNT_4 0x541A318
+
+#define mmNIC0_QM0_CP_FENCE3_CNT_0 0x541A31C
+
+#define mmNIC0_QM0_CP_FENCE3_CNT_1 0x541A320
+
+#define mmNIC0_QM0_CP_FENCE3_CNT_2 0x541A324
+
+#define mmNIC0_QM0_CP_FENCE3_CNT_3 0x541A328
+
+#define mmNIC0_QM0_CP_FENCE3_CNT_4 0x541A32C
+
+#define mmNIC0_QM0_CP_BARRIER_CFG 0x541A330
+
+#define mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET 0x541A334
+
+#define mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET 0x541A338
+
+#define mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET 0x541A33C
+
+#define mmNIC0_QM0_CP_CQ_PTR_LO_OFFSET_0 0x541A340
+
+#define mmNIC0_QM0_CP_CQ_PTR_LO_OFFSET_1 0x541A344
+
+#define mmNIC0_QM0_CP_CQ_PTR_LO_OFFSET_2 0x541A348
+
+#define mmNIC0_QM0_CP_CQ_PTR_LO_OFFSET_3 0x541A34C
+
+#define mmNIC0_QM0_CP_CQ_PTR_LO_OFFSET_4 0x541A350
+
+#define mmNIC0_QM0_CP_STS_0 0x541A368
+
+#define mmNIC0_QM0_CP_STS_1 0x541A36C
+
+#define mmNIC0_QM0_CP_STS_2 0x541A370
+
+#define mmNIC0_QM0_CP_STS_3 0x541A374
+
+#define mmNIC0_QM0_CP_STS_4 0x541A378
+
+#define mmNIC0_QM0_CP_CURRENT_INST_LO_0 0x541A37C
+
+#define mmNIC0_QM0_CP_CURRENT_INST_LO_1 0x541A380
+
+#define mmNIC0_QM0_CP_CURRENT_INST_LO_2 0x541A384
+
+#define mmNIC0_QM0_CP_CURRENT_INST_LO_3 0x541A388
+
+#define mmNIC0_QM0_CP_CURRENT_INST_LO_4 0x541A38C
+
+#define mmNIC0_QM0_CP_CURRENT_INST_HI_0 0x541A390
+
+#define mmNIC0_QM0_CP_CURRENT_INST_HI_1 0x541A394
+
+#define mmNIC0_QM0_CP_CURRENT_INST_HI_2 0x541A398
+
+#define mmNIC0_QM0_CP_CURRENT_INST_HI_3 0x541A39C
+
+#define mmNIC0_QM0_CP_CURRENT_INST_HI_4 0x541A3A0
+
+#define mmNIC0_QM0_CP_PRED_0 0x541A3A4
+
+#define mmNIC0_QM0_CP_PRED_1 0x541A3A8
+
+#define mmNIC0_QM0_CP_PRED_2 0x541A3AC
+
+#define mmNIC0_QM0_CP_PRED_3 0x541A3B0
+
+#define mmNIC0_QM0_CP_PRED_4 0x541A3B4
+
+#define mmNIC0_QM0_CP_PRED_UPEN_0 0x541A3B8
+
+#define mmNIC0_QM0_CP_PRED_UPEN_1 0x541A3BC
+
+#define mmNIC0_QM0_CP_PRED_UPEN_2 0x541A3C0
+
+#define mmNIC0_QM0_CP_PRED_UPEN_3 0x541A3C4
+
+#define mmNIC0_QM0_CP_PRED_UPEN_4 0x541A3C8
+
+#define mmNIC0_QM0_CP_DBG_0_0 0x541A3CC
+
+#define mmNIC0_QM0_CP_DBG_0_1 0x541A3D0
+
+#define mmNIC0_QM0_CP_DBG_0_2 0x541A3D4
+
+#define mmNIC0_QM0_CP_DBG_0_3 0x541A3D8
+
+#define mmNIC0_QM0_CP_DBG_0_4 0x541A3DC
+
+#define mmNIC0_QM0_CP_CPDMA_UP_CRED_0 0x541A3E0
+
+#define mmNIC0_QM0_CP_CPDMA_UP_CRED_1 0x541A3E4
+
+#define mmNIC0_QM0_CP_CPDMA_UP_CRED_2 0x541A3E8
+
+#define mmNIC0_QM0_CP_CPDMA_UP_CRED_3 0x541A3EC
+
+#define mmNIC0_QM0_CP_CPDMA_UP_CRED_4 0x541A3F0
+
+#define mmNIC0_QM0_CP_IN_DATA_LO_0 0x541A3F4
+
+#define mmNIC0_QM0_CP_IN_DATA_LO_1 0x541A3F8
+
+#define mmNIC0_QM0_CP_IN_DATA_LO_2 0x541A3FC
+
+#define mmNIC0_QM0_CP_IN_DATA_LO_3 0x541A400
+
+#define mmNIC0_QM0_CP_IN_DATA_LO_4 0x541A404
+
+#define mmNIC0_QM0_CP_IN_DATA_HI_0 0x541A408
+
+#define mmNIC0_QM0_CP_IN_DATA_HI_1 0x541A40C
+
+#define mmNIC0_QM0_CP_IN_DATA_HI_2 0x541A410
+
+#define mmNIC0_QM0_CP_IN_DATA_HI_3 0x541A414
+
+#define mmNIC0_QM0_CP_IN_DATA_HI_4 0x541A418
+
+#define mmNIC0_QM0_PQC_HBW_BASE_LO_0 0x541A41C
+
+#define mmNIC0_QM0_PQC_HBW_BASE_LO_1 0x541A420
+
+#define mmNIC0_QM0_PQC_HBW_BASE_LO_2 0x541A424
+
+#define mmNIC0_QM0_PQC_HBW_BASE_LO_3 0x541A428
+
+#define mmNIC0_QM0_PQC_HBW_BASE_HI_0 0x541A42C
+
+#define mmNIC0_QM0_PQC_HBW_BASE_HI_1 0x541A430
+
+#define mmNIC0_QM0_PQC_HBW_BASE_HI_2 0x541A434
+
+#define mmNIC0_QM0_PQC_HBW_BASE_HI_3 0x541A438
+
+#define mmNIC0_QM0_PQC_SIZE_0 0x541A43C
+
+#define mmNIC0_QM0_PQC_SIZE_1 0x541A440
+
+#define mmNIC0_QM0_PQC_SIZE_2 0x541A444
+
+#define mmNIC0_QM0_PQC_SIZE_3 0x541A448
+
+#define mmNIC0_QM0_PQC_PI_0 0x541A44C
+
+#define mmNIC0_QM0_PQC_PI_1 0x541A450
+
+#define mmNIC0_QM0_PQC_PI_2 0x541A454
+
+#define mmNIC0_QM0_PQC_PI_3 0x541A458
+
+#define mmNIC0_QM0_PQC_LBW_WDATA_0 0x541A45C
+
+#define mmNIC0_QM0_PQC_LBW_WDATA_1 0x541A460
+
+#define mmNIC0_QM0_PQC_LBW_WDATA_2 0x541A464
+
+#define mmNIC0_QM0_PQC_LBW_WDATA_3 0x541A468
+
+#define mmNIC0_QM0_PQC_LBW_BASE_LO_0 0x541A46C
+
+#define mmNIC0_QM0_PQC_LBW_BASE_LO_1 0x541A470
+
+#define mmNIC0_QM0_PQC_LBW_BASE_LO_2 0x541A474
+
+#define mmNIC0_QM0_PQC_LBW_BASE_LO_3 0x541A478
+
+#define mmNIC0_QM0_PQC_LBW_BASE_HI_0 0x541A47C
+
+#define mmNIC0_QM0_PQC_LBW_BASE_HI_1 0x541A480
+
+#define mmNIC0_QM0_PQC_LBW_BASE_HI_2 0x541A484
+
+#define mmNIC0_QM0_PQC_LBW_BASE_HI_3 0x541A488
+
+#define mmNIC0_QM0_PQC_CFG 0x541A48C
+
+#define mmNIC0_QM0_PQC_SECURE_PUSH_IND 0x541A490
+
+#define mmNIC0_QM0_ARB_MASK 0x541A4A0
+
+#define mmNIC0_QM0_ARB_CFG_0 0x541A4A4
+
+#define mmNIC0_QM0_ARB_CHOICE_Q_PUSH 0x541A4A8
+
+#define mmNIC0_QM0_ARB_WRR_WEIGHT_0 0x541A4AC
+
+#define mmNIC0_QM0_ARB_WRR_WEIGHT_1 0x541A4B0
+
+#define mmNIC0_QM0_ARB_WRR_WEIGHT_2 0x541A4B4
+
+#define mmNIC0_QM0_ARB_WRR_WEIGHT_3 0x541A4B8
+
+#define mmNIC0_QM0_ARB_CFG_1 0x541A4BC
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_0 0x541A4C0
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_1 0x541A4C4
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_2 0x541A4C8
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_3 0x541A4CC
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_4 0x541A4D0
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_5 0x541A4D4
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_6 0x541A4D8
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_7 0x541A4DC
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_8 0x541A4E0
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_9 0x541A4E4
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_10 0x541A4E8
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_11 0x541A4EC
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_12 0x541A4F0
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_13 0x541A4F4
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_14 0x541A4F8
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_15 0x541A4FC
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_16 0x541A500
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_17 0x541A504
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_18 0x541A508
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_19 0x541A50C
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_20 0x541A510
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_21 0x541A514
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_22 0x541A518
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_23 0x541A51C
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_24 0x541A520
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_25 0x541A524
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_26 0x541A528
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_27 0x541A52C
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_28 0x541A530
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_29 0x541A534
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_30 0x541A538
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_31 0x541A53C
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_32 0x541A540
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_33 0x541A544
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_34 0x541A548
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_35 0x541A54C
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_36 0x541A550
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_37 0x541A554
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_38 0x541A558
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_39 0x541A55C
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_40 0x541A560
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_41 0x541A564
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_42 0x541A568
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_43 0x541A56C
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_44 0x541A570
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_45 0x541A574
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_46 0x541A578
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_47 0x541A57C
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_48 0x541A580
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_49 0x541A584
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_50 0x541A588
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_51 0x541A58C
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_52 0x541A590
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_53 0x541A594
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_54 0x541A598
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_55 0x541A59C
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_56 0x541A5A0
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_57 0x541A5A4
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_58 0x541A5A8
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_59 0x541A5AC
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_60 0x541A5B0
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_61 0x541A5B4
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_62 0x541A5B8
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_63 0x541A5BC
+
+#define mmNIC0_QM0_ARB_MST_CRED_INC 0x541A5E0
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_0 0x541A5E4
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_1 0x541A5E8
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_2 0x541A5EC
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_3 0x541A5F0
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_4 0x541A5F4
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_5 0x541A5F8
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_6 0x541A5FC
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_7 0x541A600
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_8 0x541A604
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_9 0x541A608
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_10 0x541A60C
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_11 0x541A610
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_12 0x541A614
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_13 0x541A618
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_14 0x541A61C
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_15 0x541A620
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_16 0x541A624
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_17 0x541A628
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_18 0x541A62C
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_19 0x541A630
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_20 0x541A634
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_21 0x541A638
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_22 0x541A63C
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_23 0x541A640
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_24 0x541A644
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_25 0x541A648
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_26 0x541A64C
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_27 0x541A650
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_28 0x541A654
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_29 0x541A658
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_30 0x541A65C
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_31 0x541A660
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_32 0x541A664
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_33 0x541A668
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_34 0x541A66C
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_35 0x541A670
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_36 0x541A674
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_37 0x541A678
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_38 0x541A67C
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_39 0x541A680
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_40 0x541A684
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_41 0x541A688
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_42 0x541A68C
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_43 0x541A690
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_44 0x541A694
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_45 0x541A698
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_46 0x541A69C
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_47 0x541A6A0
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_48 0x541A6A4
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_49 0x541A6A8
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_50 0x541A6AC
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_51 0x541A6B0
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_52 0x541A6B4
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_53 0x541A6B8
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_54 0x541A6BC
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_55 0x541A6C0
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_56 0x541A6C4
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_57 0x541A6C8
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_58 0x541A6CC
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_59 0x541A6D0
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_60 0x541A6D4
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_61 0x541A6D8
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_62 0x541A6DC
+
+#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_63 0x541A6E0
+
+#define mmNIC0_QM0_ARB_SLV_MASTER_INC_CRED_OFST 0x541A704
+
+#define mmNIC0_QM0_ARB_MST_SLAVE_EN 0x541A708
+
+#define mmNIC0_QM0_ARB_MST_SLAVE_EN_1 0x541A70C
+
+#define mmNIC0_QM0_ARB_SLV_CHOICE_WDT 0x541A710
+
+#define mmNIC0_QM0_ARB_SLV_ID 0x541A714
+
+#define mmNIC0_QM0_ARB_MST_QUIET_PER 0x541A718
+
+#define mmNIC0_QM0_ARB_MSG_MAX_INFLIGHT 0x541A744
+
+#define mmNIC0_QM0_ARB_BASE_LO 0x541A754
+
+#define mmNIC0_QM0_ARB_BASE_HI 0x541A758
+
+#define mmNIC0_QM0_ARB_STATE_STS 0x541A780
+
+#define mmNIC0_QM0_ARB_CHOICE_FULLNESS_STS 0x541A784
+
+#define mmNIC0_QM0_ARB_MSG_STS 0x541A788
+
+#define mmNIC0_QM0_ARB_SLV_CHOICE_Q_HEAD 0x541A78C
+
+#define mmNIC0_QM0_ARB_ERR_CAUSE 0x541A79C
+
+#define mmNIC0_QM0_ARB_ERR_MSG_EN 0x541A7A0
+
+#define mmNIC0_QM0_ARB_ERR_STS_DRP 0x541A7A8
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS 0x541A7B0
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_1 0x541A7B4
+
+#define mmNIC0_QM0_CSMR_STRICT_PRIO_CFG 0x541A7FC
+
+#define mmNIC0_QM0_ARC_CQ_CFG0 0x541A800
+
+#define mmNIC0_QM0_ARC_CQ_CFG1 0x541A804
+
+#define mmNIC0_QM0_ARC_CQ_PTR_LO 0x541A808
+
+#define mmNIC0_QM0_ARC_CQ_PTR_HI 0x541A80C
+
+#define mmNIC0_QM0_ARC_CQ_TSIZE 0x541A810
+
+#define mmNIC0_QM0_ARC_CQ_CTL 0x541A814
+
+#define mmNIC0_QM0_ARC_CQ_IFIFO_STS 0x541A81C
+
+#define mmNIC0_QM0_ARC_CQ_STS0 0x541A820
+
+#define mmNIC0_QM0_ARC_CQ_STS1 0x541A824
+
+#define mmNIC0_QM0_ARC_CQ_TSIZE_STS 0x541A828
+
+#define mmNIC0_QM0_ARC_CQ_PTR_LO_STS 0x541A82C
+
+#define mmNIC0_QM0_ARC_CQ_PTR_HI_STS 0x541A830
+
+#define mmNIC0_QM0_CP_WR_ARC_ADDR_HI 0x541A834
+
+#define mmNIC0_QM0_CP_WR_ARC_ADDR_LO 0x541A838
+
+#define mmNIC0_QM0_ARC_CQ_IFIFO_MSG_BASE_HI 0x541A83C
+
+#define mmNIC0_QM0_ARC_CQ_IFIFO_MSG_BASE_LO 0x541A840
+
+#define mmNIC0_QM0_ARC_CQ_CTL_MSG_BASE_HI 0x541A844
+
+#define mmNIC0_QM0_ARC_CQ_CTL_MSG_BASE_LO 0x541A848
+
+#define mmNIC0_QM0_CQ_IFIFO_MSG_BASE_HI 0x541A84C
+
+#define mmNIC0_QM0_CQ_IFIFO_MSG_BASE_LO 0x541A850
+
+#define mmNIC0_QM0_CQ_CTL_MSG_BASE_HI 0x541A854
+
+#define mmNIC0_QM0_CQ_CTL_MSG_BASE_LO 0x541A858
+
+#define mmNIC0_QM0_ADDR_OVRD 0x541A85C
+
+#define mmNIC0_QM0_CQ_IFIFO_CI_0 0x541A860
+
+#define mmNIC0_QM0_CQ_IFIFO_CI_1 0x541A864
+
+#define mmNIC0_QM0_CQ_IFIFO_CI_2 0x541A868
+
+#define mmNIC0_QM0_CQ_IFIFO_CI_3 0x541A86C
+
+#define mmNIC0_QM0_CQ_IFIFO_CI_4 0x541A870
+
+#define mmNIC0_QM0_ARC_CQ_IFIFO_CI 0x541A874
+
+#define mmNIC0_QM0_CQ_CTL_CI_0 0x541A878
+
+#define mmNIC0_QM0_CQ_CTL_CI_1 0x541A87C
+
+#define mmNIC0_QM0_CQ_CTL_CI_2 0x541A880
+
+#define mmNIC0_QM0_CQ_CTL_CI_3 0x541A884
+
+#define mmNIC0_QM0_CQ_CTL_CI_4 0x541A888
+
+#define mmNIC0_QM0_ARC_CQ_CTL_CI 0x541A88C
+
+#define mmNIC0_QM0_CP_CFG 0x541A890
+
+#define mmNIC0_QM0_CP_EXT_SWITCH 0x541A894
+
+#define mmNIC0_QM0_CP_SWITCH_WD_SET 0x541A898
+
+#define mmNIC0_QM0_CP_SWITCH_WD 0x541A89C
+
+#define mmNIC0_QM0_ARC_LB_ADDR_BASE_LO 0x541A8A4
+
+#define mmNIC0_QM0_ARC_LB_ADDR_BASE_HI 0x541A8A8
+
+#define mmNIC0_QM0_ENGINE_BASE_ADDR_HI 0x541A8AC
+
+#define mmNIC0_QM0_ENGINE_BASE_ADDR_LO 0x541A8B0
+
+#define mmNIC0_QM0_ENGINE_ADDR_RANGE_SIZE 0x541A8B4
+
+#define mmNIC0_QM0_QM_ARC_AUX_BASE_ADDR_HI 0x541A8B8
+
+#define mmNIC0_QM0_QM_ARC_AUX_BASE_ADDR_LO 0x541A8BC
+
+#define mmNIC0_QM0_QM_BASE_ADDR_HI 0x541A8C0
+
+#define mmNIC0_QM0_QM_BASE_ADDR_LO 0x541A8C4
+
+#define mmNIC0_QM0_ARC_PQC_SECURE_PUSH_IND 0x541A8C8
+
+#define mmNIC0_QM0_PQC_STS_0_0 0x541A8D0
+
+#define mmNIC0_QM0_PQC_STS_0_1 0x541A8D4
+
+#define mmNIC0_QM0_PQC_STS_0_2 0x541A8D8
+
+#define mmNIC0_QM0_PQC_STS_0_3 0x541A8DC
+
+#define mmNIC0_QM0_PQC_STS_1_0 0x541A8E0
+
+#define mmNIC0_QM0_PQC_STS_1_1 0x541A8E4
+
+#define mmNIC0_QM0_PQC_STS_1_2 0x541A8E8
+
+#define mmNIC0_QM0_PQC_STS_1_3 0x541A8EC
+
+#define mmNIC0_QM0_SEI_STATUS 0x541A8F0
+
+#define mmNIC0_QM0_SEI_MASK 0x541A8F4
+
+#define mmNIC0_QM0_GLBL_ERR_ADDR_LO 0x541AD00
+
+#define mmNIC0_QM0_GLBL_ERR_ADDR_HI 0x541AD04
+
+#define mmNIC0_QM0_GLBL_ERR_WDATA 0x541AD08
+
+#define mmNIC0_QM0_L2H_MASK_LO 0x541AD14
+
+#define mmNIC0_QM0_L2H_MASK_HI 0x541AD18
+
+#define mmNIC0_QM0_L2H_CMPR_LO 0x541AD1C
+
+#define mmNIC0_QM0_L2H_CMPR_HI 0x541AD20
+
+#define mmNIC0_QM0_LOCAL_RANGE_BASE 0x541AD24
+
+#define mmNIC0_QM0_LOCAL_RANGE_SIZE 0x541AD28
+
+#define mmNIC0_QM0_HBW_RD_RATE_LIM_CFG_1 0x541AD30
+
+#define mmNIC0_QM0_LBW_WR_RATE_LIM_CFG_0 0x541AD34
+
+#define mmNIC0_QM0_LBW_WR_RATE_LIM_CFG_1 0x541AD38
+
+#define mmNIC0_QM0_HBW_RD_RATE_LIM_CFG_0 0x541AD3C
+
+#define mmNIC0_QM0_IND_GW_APB_CFG 0x541AD40
+
+#define mmNIC0_QM0_IND_GW_APB_WDATA 0x541AD44
+
+#define mmNIC0_QM0_IND_GW_APB_RDATA 0x541AD48
+
+#define mmNIC0_QM0_IND_GW_APB_STATUS 0x541AD4C
+
+#define mmNIC0_QM0_PERF_CNT_FREE_LO 0x541AD60
+
+#define mmNIC0_QM0_PERF_CNT_FREE_HI 0x541AD64
+
+#define mmNIC0_QM0_PERF_CNT_IDLE_LO 0x541AD68
+
+#define mmNIC0_QM0_PERF_CNT_IDLE_HI 0x541AD6C
+
+#define mmNIC0_QM0_PERF_CNT_CFG 0x541AD70
+
+#endif /* ASIC_REG_NIC0_QM0_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_qm_arc_aux0_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_qm_arc_aux0_regs.h
new file mode 100644
index 000000000000..5f380a44dd21
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_qm_arc_aux0_regs.h
@@ -0,0 +1,591 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_QM_ARC_AUX0_REGS_H_
+#define ASIC_REG_NIC0_QM_ARC_AUX0_REGS_H_
+
+/*
+ *****************************************
+ *   NIC0_QM_ARC_AUX0
+ *   (Prototype: QMAN_ARC_AUX)
+ *****************************************
+ */
+
+#define mmNIC0_QM_ARC_AUX0_RUN_HALT_REQ 0x5418100
+
+#define mmNIC0_QM_ARC_AUX0_RUN_HALT_ACK 0x5418104
+
+#define mmNIC0_QM_ARC_AUX0_RST_VEC_ADDR 0x5418108
+
+#define mmNIC0_QM_ARC_AUX0_DBG_MODE 0x541810C
+
+#define mmNIC0_QM_ARC_AUX0_CLUSTER_NUM 0x5418110
+
+#define mmNIC0_QM_ARC_AUX0_ARC_NUM 0x5418114
+
+#define mmNIC0_QM_ARC_AUX0_WAKE_UP_EVENT 0x5418118
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_SYS_ADDR_BASE 0x541811C
+
+#define mmNIC0_QM_ARC_AUX0_CTI_AP_STS 0x5418120
+
+#define mmNIC0_QM_ARC_AUX0_CTI_CFG_MUX_SEL 0x5418124
+
+#define mmNIC0_QM_ARC_AUX0_ARC_RST 0x5418128
+
+#define mmNIC0_QM_ARC_AUX0_ARC_RST_REQ 0x541812C
+
+#define mmNIC0_QM_ARC_AUX0_SRAM_LSB_ADDR 0x5418130
+
+#define mmNIC0_QM_ARC_AUX0_SRAM_MSB_ADDR 0x5418134
+
+#define mmNIC0_QM_ARC_AUX0_PCIE_LSB_ADDR 0x5418138
+
+#define mmNIC0_QM_ARC_AUX0_PCIE_MSB_ADDR 0x541813C
+
+#define mmNIC0_QM_ARC_AUX0_CFG_LSB_ADDR 0x5418140
+
+#define mmNIC0_QM_ARC_AUX0_CFG_MSB_ADDR 0x5418144
+
+#define mmNIC0_QM_ARC_AUX0_HBM0_LSB_ADDR 0x5418150
+
+#define mmNIC0_QM_ARC_AUX0_HBM0_MSB_ADDR 0x5418154
+
+#define mmNIC0_QM_ARC_AUX0_HBM1_LSB_ADDR 0x5418158
+
+#define mmNIC0_QM_ARC_AUX0_HBM1_MSB_ADDR 0x541815C
+
+#define mmNIC0_QM_ARC_AUX0_HBM2_LSB_ADDR 0x5418160
+
+#define mmNIC0_QM_ARC_AUX0_HBM2_MSB_ADDR 0x5418164
+
+#define mmNIC0_QM_ARC_AUX0_HBM3_LSB_ADDR 0x5418168
+
+#define mmNIC0_QM_ARC_AUX0_HBM3_MSB_ADDR 0x541816C
+
+#define mmNIC0_QM_ARC_AUX0_HBM0_OFFSET 0x5418170
+
+#define mmNIC0_QM_ARC_AUX0_HBM1_OFFSET 0x5418174
+
+#define mmNIC0_QM_ARC_AUX0_HBM2_OFFSET 0x5418178
+
+#define mmNIC0_QM_ARC_AUX0_HBM3_OFFSET 0x541817C
+
+#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_0 0x5418180
+
+#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_1 0x5418184
+
+#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_2 0x5418188
+
+#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_3 0x541818C
+
+#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_4 0x5418190
+
+#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_5 0x5418194
+
+#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_6 0x5418198
+
+#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_MSB_ADDR_0 0x541819C
+
+#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_MSB_ADDR_1 0x54181A0
+
+#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_MSB_ADDR_2 0x54181A4
+
+#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_MSB_ADDR_3 0x54181A8
+
+#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_MSB_ADDR_4 0x54181AC
+
+#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_MSB_ADDR_5 0x54181B0
+
+#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_MSB_ADDR_6 0x54181B4
+
+#define mmNIC0_QM_ARC_AUX0_ARC_CBU_AWCACHE_OVR 0x54181B8
+
+#define mmNIC0_QM_ARC_AUX0_ARC_LBU_AWCACHE_OVR 0x54181BC
+
+#define mmNIC0_QM_ARC_AUX0_CONTEXT_ID_0 0x54181C0
+
+#define mmNIC0_QM_ARC_AUX0_CONTEXT_ID_1 0x54181C4
+
+#define mmNIC0_QM_ARC_AUX0_CONTEXT_ID_2 0x54181C8
+
+#define mmNIC0_QM_ARC_AUX0_CONTEXT_ID_3 0x54181CC
+
+#define mmNIC0_QM_ARC_AUX0_CONTEXT_ID_4 0x54181D0
+
+#define mmNIC0_QM_ARC_AUX0_CONTEXT_ID_5 0x54181D4
+
+#define mmNIC0_QM_ARC_AUX0_CONTEXT_ID_6 0x54181D8
+
+#define mmNIC0_QM_ARC_AUX0_CONTEXT_ID_7 0x54181DC
+
+#define mmNIC0_QM_ARC_AUX0_CID_OFFSET_0 0x54181E0
+
+#define mmNIC0_QM_ARC_AUX0_CID_OFFSET_1 0x54181E4
+
+#define mmNIC0_QM_ARC_AUX0_CID_OFFSET_2 0x54181E8
+
+#define mmNIC0_QM_ARC_AUX0_CID_OFFSET_3 0x54181EC
+
+#define mmNIC0_QM_ARC_AUX0_CID_OFFSET_4 0x54181F0
+
+#define mmNIC0_QM_ARC_AUX0_CID_OFFSET_5 0x54181F4
+
+#define mmNIC0_QM_ARC_AUX0_CID_OFFSET_6 0x54181F8
+
+#define mmNIC0_QM_ARC_AUX0_CID_OFFSET_7 0x54181FC
+
+#define mmNIC0_QM_ARC_AUX0_SW_INTR_0 0x5418200
+
+#define mmNIC0_QM_ARC_AUX0_SW_INTR_1 0x5418204
+
+#define mmNIC0_QM_ARC_AUX0_SW_INTR_2 0x5418208
+
+#define mmNIC0_QM_ARC_AUX0_SW_INTR_3 0x541820C
+
+#define mmNIC0_QM_ARC_AUX0_SW_INTR_4 0x5418210
+
+#define mmNIC0_QM_ARC_AUX0_SW_INTR_5 0x5418214
+
+#define mmNIC0_QM_ARC_AUX0_SW_INTR_6 0x5418218
+
+#define mmNIC0_QM_ARC_AUX0_SW_INTR_7 0x541821C
+
+#define mmNIC0_QM_ARC_AUX0_SW_INTR_8 0x5418220
+
+#define mmNIC0_QM_ARC_AUX0_SW_INTR_9 0x5418224
+
+#define mmNIC0_QM_ARC_AUX0_SW_INTR_10 0x5418228
+
+#define mmNIC0_QM_ARC_AUX0_SW_INTR_11 0x541822C
+
+#define mmNIC0_QM_ARC_AUX0_SW_INTR_12 0x5418230
+
+#define mmNIC0_QM_ARC_AUX0_SW_INTR_13 0x5418234
+
+#define mmNIC0_QM_ARC_AUX0_SW_INTR_14 0x5418238
+
+#define mmNIC0_QM_ARC_AUX0_SW_INTR_15 0x541823C
+
+#define mmNIC0_QM_ARC_AUX0_IRQ_INTR_MASK_0 0x5418280
+
+#define mmNIC0_QM_ARC_AUX0_IRQ_INTR_MASK_1 0x5418284
+
+#define mmNIC0_QM_ARC_AUX0_ARC_SEI_INTR_STS 0x5418290
+
+#define mmNIC0_QM_ARC_AUX0_ARC_SEI_INTR_CLR 0x5418294
+
+#define mmNIC0_QM_ARC_AUX0_ARC_SEI_INTR_MASK 0x5418298
+
+#define mmNIC0_QM_ARC_AUX0_ARC_EXCPTN_CAUSE 0x541829C
+
+#define mmNIC0_QM_ARC_AUX0_SEI_INTR_HALT_EN 0x54182A0
+
+#define mmNIC0_QM_ARC_AUX0_ARC_SEI_INTR_HALT_MASK 0x54182A4
+
+#define mmNIC0_QM_ARC_AUX0_QMAN_SEI_INTR_HALT_MASK 0x54182A8
+
+#define mmNIC0_QM_ARC_AUX0_ARC_REI_INTR_STS 0x54182B0
+
+#define mmNIC0_QM_ARC_AUX0_ARC_REI_INTR_CLR 0x54182B4
+
+#define mmNIC0_QM_ARC_AUX0_ARC_REI_INTR_MASK 0x54182B8
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_ECC_ERR_ADDR 0x54182BC
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_ECC_SYNDROME 0x54182C0
+
+#define mmNIC0_QM_ARC_AUX0_I_CACHE_ECC_ERR_ADDR 0x54182C4
+
+#define mmNIC0_QM_ARC_AUX0_I_CACHE_ECC_SYNDROME 0x54182C8
+
+#define mmNIC0_QM_ARC_AUX0_D_CACHE_ECC_ERR_ADDR 0x54182CC
+
+#define mmNIC0_QM_ARC_AUX0_D_CACHE_ECC_SYNDROME 0x54182D0
+
+#define mmNIC0_QM_ARC_AUX0_LBW_TRMINATE_AWADDR_ERR 0x54182E0
+
+#define mmNIC0_QM_ARC_AUX0_LBW_TRMINATE_ARADDR_ERR 0x54182E4
+
+#define mmNIC0_QM_ARC_AUX0_CFG_LBW_TERMINATE_BRESP 0x54182E8
+
+#define mmNIC0_QM_ARC_AUX0_CFG_LBW_TERMINATE_RRESP 0x54182EC
+
+#define mmNIC0_QM_ARC_AUX0_CFG_LBW_TERMINATE_AXLEN 0x54182F0
+
+#define mmNIC0_QM_ARC_AUX0_CFG_LBW_TERMINATE_AXSIZE 0x54182F4
+
+#define mmNIC0_QM_ARC_AUX0_SCRATCHPAD_0 0x5418300
+
+#define mmNIC0_QM_ARC_AUX0_SCRATCHPAD_1 0x5418304
+
+#define mmNIC0_QM_ARC_AUX0_SCRATCHPAD_2 0x5418308
+
+#define mmNIC0_QM_ARC_AUX0_SCRATCHPAD_3 0x541830C
+
+#define mmNIC0_QM_ARC_AUX0_SCRATCHPAD_4 0x5418310
+
+#define mmNIC0_QM_ARC_AUX0_SCRATCHPAD_5 0x5418314
+
+#define mmNIC0_QM_ARC_AUX0_SCRATCHPAD_6 0x5418318
+
+#define mmNIC0_QM_ARC_AUX0_SCRATCHPAD_7 0x541831C
+
+#define mmNIC0_QM_ARC_AUX0_TOTAL_CBU_WR_CNT 0x5418320
+
+#define mmNIC0_QM_ARC_AUX0_INFLIGHT_CBU_WR_CNT 0x5418324
+
+#define mmNIC0_QM_ARC_AUX0_TOTAL_CBU_RD_CNT 0x5418328
+
+#define mmNIC0_QM_ARC_AUX0_INFLIGHT_CBU_RD_CNT 0x541832C
+
+#define mmNIC0_QM_ARC_AUX0_TOTAL_LBU_WR_CNT 0x5418330
+
+#define mmNIC0_QM_ARC_AUX0_INFLIGHT_LBU_WR_CNT 0x5418334
+
+#define mmNIC0_QM_ARC_AUX0_TOTAL_LBU_RD_CNT 0x5418338
+
+#define mmNIC0_QM_ARC_AUX0_INFLIGHT_LBU_RD_CNT 0x541833C
+
+#define mmNIC0_QM_ARC_AUX0_CBU_ARUSER_OVR 0x5418350
+
+#define mmNIC0_QM_ARC_AUX0_CBU_ARUSER_OVR_EN 0x5418354
+
+#define mmNIC0_QM_ARC_AUX0_CBU_AWUSER_OVR 0x5418358
+
+#define mmNIC0_QM_ARC_AUX0_CBU_AWUSER_OVR_EN 0x541835C
+
+#define mmNIC0_QM_ARC_AUX0_CBU_ARUSER_MSB_OVR 0x5418360
+
+#define mmNIC0_QM_ARC_AUX0_CBU_ARUSER_MSB_OVR_EN 0x5418364
+
+#define mmNIC0_QM_ARC_AUX0_CBU_AWUSER_MSB_OVR 0x5418368
+
+#define mmNIC0_QM_ARC_AUX0_CBU_AWUSER_MSB_OVR_EN 0x541836C
+
+#define mmNIC0_QM_ARC_AUX0_CBU_AXCACHE_OVR 0x5418370
+
+#define mmNIC0_QM_ARC_AUX0_CBU_LOCK_OVR 0x5418374
+
+#define mmNIC0_QM_ARC_AUX0_CBU_PROT_OVR 0x5418378
+
+#define mmNIC0_QM_ARC_AUX0_CBU_MAX_OUTSTANDING 0x541837C
+
+#define mmNIC0_QM_ARC_AUX0_CBU_EARLY_BRESP_EN 0x5418380
+
+#define mmNIC0_QM_ARC_AUX0_CBU_FORCE_RSP_OK 0x5418384
+
+#define mmNIC0_QM_ARC_AUX0_CBU_NO_WR_INFLIGHT 0x541838C
+
+#define mmNIC0_QM_ARC_AUX0_CBU_SEI_INTR_ID 0x5418390
+
+#define mmNIC0_QM_ARC_AUX0_LBU_ARUSER_OVR 0x5418400
+
+#define mmNIC0_QM_ARC_AUX0_LBU_ARUSER_OVR_EN 0x5418404
+
+#define mmNIC0_QM_ARC_AUX0_LBU_AWUSER_OVR 0x5418408
+
+#define mmNIC0_QM_ARC_AUX0_LBU_AWUSER_OVR_EN 0x541840C
+
+#define mmNIC0_QM_ARC_AUX0_LBU_AXCACHE_OVR 0x5418420
+
+#define mmNIC0_QM_ARC_AUX0_LBU_LOCK_OVR 0x5418424
+
+#define mmNIC0_QM_ARC_AUX0_LBU_PROT_OVR 0x5418428
+
+#define mmNIC0_QM_ARC_AUX0_LBU_MAX_OUTSTANDING 0x541842C
+
+#define mmNIC0_QM_ARC_AUX0_LBU_EARLY_BRESP_EN 0x5418430
+
+#define mmNIC0_QM_ARC_AUX0_LBU_FORCE_RSP_OK 0x5418434
+
+#define mmNIC0_QM_ARC_AUX0_LBU_NO_WR_INFLIGHT 0x541843C
+
+#define mmNIC0_QM_ARC_AUX0_LBU_SEI_INTR_ID 0x5418440
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_0 0x5418500
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_1 0x5418504
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_2 0x5418508
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_3 0x541850C
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_4 0x5418510
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_5 0x5418514
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_6 0x5418518
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_7 0x541851C
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_SIZE_0 0x5418520
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_SIZE_1 0x5418524
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_SIZE_2 0x5418528
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_SIZE_3 0x541852C
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_SIZE_4 0x5418530
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_SIZE_5 0x5418534
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_SIZE_6 0x5418538
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_SIZE_7 0x541853C
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PI_0 0x5418540
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PI_1 0x5418544
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PI_2 0x5418548
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PI_3 0x541854C
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PI_4 0x5418550
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PI_5 0x5418554
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PI_6 0x5418558
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PI_7 0x541855C
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_CI_0 0x5418560
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_CI_1 0x5418564
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_CI_2 0x5418568
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_CI_3 0x541856C
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_CI_4 0x5418570
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_CI_5 0x5418574
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_CI_6 0x5418578
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_CI_7 0x541857C
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PUSH_REG_0 0x5418580
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PUSH_REG_1 0x5418584
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PUSH_REG_2 0x5418588
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PUSH_REG_3 0x541858C
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PUSH_REG_4 0x5418590
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PUSH_REG_5 0x5418594
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PUSH_REG_6 0x5418598
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PUSH_REG_7 0x541859C
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_MAX_OCCUPANCY_0 0x54185A0
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_MAX_OCCUPANCY_1 0x54185A4
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_MAX_OCCUPANCY_2 0x54185A8
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_MAX_OCCUPANCY_3 0x54185AC
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_MAX_OCCUPANCY_4 0x54185B0
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_MAX_OCCUPANCY_5 0x54185B4
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_MAX_OCCUPANCY_6 0x54185B8
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_MAX_OCCUPANCY_7 0x54185BC
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_VALID_ENTRIES_0 0x54185C0
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_VALID_ENTRIES_1 0x54185C4
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_VALID_ENTRIES_2 0x54185C8
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_VALID_ENTRIES_3 0x54185CC
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_VALID_ENTRIES_4 0x54185D0
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_VALID_ENTRIES_5 0x54185D4
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_VALID_ENTRIES_6 0x54185D8
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_VALID_ENTRIES_7 0x54185DC
+
+#define mmNIC0_QM_ARC_AUX0_GENERAL_Q_VLD_ENTRY_MASK 0x54185E0
+
+#define mmNIC0_QM_ARC_AUX0_NIC_Q_VLD_ENTRY_MASK 0x54185E4
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_DROP_EN 0x5418620
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_WARN_MSG 0x5418624
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_ALERT_MSG 0x5418628
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_GEN_AXI_AWPROT 0x5418630
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_GEN_AXI_AWUSER 0x5418634
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_GEN_AXI_AWBURST 0x5418638
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_GEN_AXI_AWLOCK 0x541863C
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_GEN_AXI_AWCACHE 0x5418640
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_WRR_ARB_WEIGHT 0x5418644
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_Q_PUSH_FIFO_FULL_CFG 0x5418648
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_Q_PUSH_FIFO_CNT 0x541864C
+
+#define mmNIC0_QM_ARC_AUX0_QMAN_CQ_IFIFO_SHADOW_CI 0x5418650
+
+#define mmNIC0_QM_ARC_AUX0_QMAN_ARC_CQ_IFIFO_SHADOW_CI 0x5418654
+
+#define mmNIC0_QM_ARC_AUX0_QMAN_CQ_SHADOW_CI 0x5418658
+
+#define mmNIC0_QM_ARC_AUX0_QMAN_ARC_CQ_SHADOW_CI 0x541865C
+
+#define mmNIC0_QM_ARC_AUX0_AUX2APB_PROT 0x5418700
+
+#define mmNIC0_QM_ARC_AUX0_LBW_FORK_WIN_EN 0x5418704
+
+#define mmNIC0_QM_ARC_AUX0_QMAN_LBW_FORK_BASE_ADDR0 0x5418708
+
+#define mmNIC0_QM_ARC_AUX0_QMAN_LBW_FORK_ADDR_MASK0 0x541870C
+
+#define mmNIC0_QM_ARC_AUX0_QMAN_LBW_FORK_BASE_ADDR1 0x5418710
+
+#define mmNIC0_QM_ARC_AUX0_QMAN_LBW_FORK_ADDR_MASK1 0x5418714
+
+#define mmNIC0_QM_ARC_AUX0_FARM_LBW_FORK_BASE_ADDR0 0x5418718
+
+#define mmNIC0_QM_ARC_AUX0_FARM_LBW_FORK_ADDR_MASK0 0x541871C
+
+#define mmNIC0_QM_ARC_AUX0_FARM_LBW_FORK_BASE_ADDR1 0x5418720
+
+#define mmNIC0_QM_ARC_AUX0_FARM_LBW_FORK_ADDR_MASK1 0x5418724
+
+#define mmNIC0_QM_ARC_AUX0_LBW_APB_FORK_MAX_ADDR0 0x5418728
+
+#define mmNIC0_QM_ARC_AUX0_LBW_APB_FORK_MAX_ADDR1 0x541872C
+
+#define mmNIC0_QM_ARC_AUX0_ARC_ACC_ENGS_LBW_FORK_MASK 0x5418730
+
+#define mmNIC0_QM_ARC_AUX0_ARC_DUP_ENG_LBW_FORK_ADDR 0x5418734
+
+#define mmNIC0_QM_ARC_AUX0_ARC_ACP_ENG_LBW_FORK_ADDR 0x5418738
+
+#define mmNIC0_QM_ARC_AUX0_ARC_ACC_ENGS_VIRTUAL_ADDR 0x541873C
+
+#define mmNIC0_QM_ARC_AUX0_CBU_FORK_WIN_EN 0x5418740
+
+#define mmNIC0_QM_ARC_AUX0_CBU_FORK_BASE_ADDR0_LSB 0x5418750
+
+#define mmNIC0_QM_ARC_AUX0_CBU_FORK_BASE_ADDR0_MSB 0x5418754
+
+#define mmNIC0_QM_ARC_AUX0_CBU_FORK_ADDR_MASK0_LSB 0x5418758
+
+#define mmNIC0_QM_ARC_AUX0_CBU_FORK_ADDR_MASK0_MSB 0x541875C
+
+#define mmNIC0_QM_ARC_AUX0_CBU_FORK_BASE_ADDR1_LSB 0x5418760
+
+#define mmNIC0_QM_ARC_AUX0_CBU_FORK_BASE_ADDR1_MSB 0x5418764
+
+#define mmNIC0_QM_ARC_AUX0_CBU_FORK_ADDR_MASK1_LSB 0x5418768
+
+#define mmNIC0_QM_ARC_AUX0_CBU_FORK_ADDR_MASK1_MSB 0x541876C
+
+#define mmNIC0_QM_ARC_AUX0_CBU_FORK_BASE_ADDR2_LSB 0x5418770
+
+#define mmNIC0_QM_ARC_AUX0_CBU_FORK_BASE_ADDR2_MSB 0x5418774
+
+#define mmNIC0_QM_ARC_AUX0_CBU_FORK_ADDR_MASK2_LSB 0x5418778
+
+#define mmNIC0_QM_ARC_AUX0_CBU_FORK_ADDR_MASK2_MSB 0x541877C
+
+#define mmNIC0_QM_ARC_AUX0_CBU_FORK_BASE_ADDR3_LSB 0x5418780
+
+#define mmNIC0_QM_ARC_AUX0_CBU_FORK_BASE_ADDR3_MSB 0x5418784
+
+#define mmNIC0_QM_ARC_AUX0_CBU_FORK_ADDR_MASK3_LSB 0x5418788
+
+#define mmNIC0_QM_ARC_AUX0_CBU_FORK_ADDR_MASK3_MSB 0x541878C
+
+#define mmNIC0_QM_ARC_AUX0_CBU_TRMINATE_ARADDR_LSB 0x5418790
+
+#define mmNIC0_QM_ARC_AUX0_CBU_TRMINATE_ARADDR_MSB 0x5418794
+
+#define mmNIC0_QM_ARC_AUX0_CFG_CBU_TERMINATE_BRESP 0x5418798
+
+#define mmNIC0_QM_ARC_AUX0_CFG_CBU_TERMINATE_RRESP 0x541879C
+
+#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_0 0x5418800
+
+#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_1 0x5418804
+
+#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_2 0x5418808
+
+#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_3 0x541880C
+
+#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_4 0x5418810
+
+#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_5 0x5418814
+
+#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_6 0x5418818
+
+#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_7 0x541881C
+
+#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_8 0x5418820
+
+#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_9 0x5418824
+
+#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_10 0x5418828
+
+#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_11 0x541882C
+
+#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_12 0x5418830
+
+#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_13 0x5418834
+
+#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_14 0x5418838
+
+#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_15 0x541883C
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_TRMINATE_AWADDR_ERR 0x5418840
+
+#define mmNIC0_QM_ARC_AUX0_DCCM_TRMINATE_ARADDR_ERR 0x5418844
+
+#define mmNIC0_QM_ARC_AUX0_CFG_DCCM_TERMINATE_BRESP 0x5418848
+
+#define mmNIC0_QM_ARC_AUX0_CFG_DCCM_TERMINATE_RRESP 0x541884C
+
+#define mmNIC0_QM_ARC_AUX0_CFG_DCCM_TERMINATE_EN 0x5418850
+
+#define mmNIC0_QM_ARC_AUX0_CFG_DCCM_SECURE_REGION 0x5418854
+
+#define mmNIC0_QM_ARC_AUX0_ARC_AXI_ORDERING_WR_IF_CNT 0x5418900
+
+#define mmNIC0_QM_ARC_AUX0_ARC_AXI_ORDERING_CTL 0x5418904
+
+#define mmNIC0_QM_ARC_AUX0_ARC_AXI_ORDERING_ADDR_MSK 0x5418908
+
+#define mmNIC0_QM_ARC_AUX0_ARC_AXI_ORDERING_ADDR 0x541890C
+
+#define mmNIC0_QM_ARC_AUX0_ARC_ACC_ENGS_BUSER 0x5418910
+
+#define mmNIC0_QM_ARC_AUX0_MME_ARC_UPPER_DCCM_EN 0x5418920
+
+#endif /* ASIC_REG_NIC0_QM_ARC_AUX0_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_qpc0_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_qpc0_regs.h
new file mode 100644
index 000000000000..eaee29da4244
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_qpc0_regs.h
@@ -0,0 +1,905 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_QPC0_REGS_H_
+#define ASIC_REG_NIC0_QPC0_REGS_H_
+
+/*
+ *****************************************
+ *   NIC0_QPC0
+ *   (Prototype: NIC_QPC)
+ *****************************************
+ */
+
+#define mmNIC0_QPC0_REQ_QPC_CACHE_INVALIDATE 0x541F000
+
+#define mmNIC0_QPC0_REQ_QPC_CACHE_INV_STATUS 0x541F004
+
+#define mmNIC0_QPC0_REQ_STATIC_CONFIG 0x541F008
+
+#define mmNIC0_QPC0_REQ_BASE_ADDRESS_63_32 0x541F00C
+
+#define mmNIC0_QPC0_REQ_BASE_ADDRESS_31_7 0x541F010
+
+#define mmNIC0_QPC0_REQ_CLEAN_LINK_LIST 0x541F014
+
+#define mmNIC0_QPC0_REQ_ERR_FIFO_PUSH_63_32 0x541F018
+
+#define mmNIC0_QPC0_REQ_ERR_FIFO_PUSH_31_0 0x541F01C
+
+#define mmNIC0_QPC0_REQ_ERR_QP_STATE_63_32 0x541F020
+
+#define mmNIC0_QPC0_REQ_ERR_QP_STATE_31_0 0x541F024
+
+#define mmNIC0_QPC0_RETRY_COUNT_MAX 0x541F028
+
+#define mmNIC0_QPC0_AXI_PROT 0x541F030
+
+#define mmNIC0_QPC0_RES_QPC_CACHE_INVALIDATE 0x541F034
+
+#define mmNIC0_QPC0_RES_QPC_CACHE_INV_STATUS 0x541F038
+
+#define mmNIC0_QPC0_RES_STATIC_CONFIG 0x541F03C
+
+#define mmNIC0_QPC0_RES_BASE_ADDRESS_63_32 0x541F040
+
+#define mmNIC0_QPC0_RES_BASE_ADDRESS_31_7 0x541F044
+
+#define mmNIC0_QPC0_RES_CLEAN_LINK_LIST 0x541F048
+
+#define mmNIC0_QPC0_ERR_FIFO_WRITE_INDEX 0x541F050
+
+#define mmNIC0_QPC0_ERR_FIFO_PRODUCER_INDEX 0x541F054
+
+#define mmNIC0_QPC0_ERR_FIFO_CONSUMER_INDEX 0x541F058
+
+#define mmNIC0_QPC0_ERR_FIFO_MASK 0x541F05C
+
+#define mmNIC0_QPC0_ERR_FIFO_CREDIT 0x541F060
+
+#define mmNIC0_QPC0_ERR_FIFO_CFG 0x541F064
+
+#define mmNIC0_QPC0_ERR_FIFO_INTR_MASK 0x541F068
+
+#define mmNIC0_QPC0_ERR_FIFO_BASE_ADDR_63_32 0x541F06C
+
+#define mmNIC0_QPC0_ERR_FIFO_BASE_ADDR_31_7 0x541F070
+
+#define mmNIC0_QPC0_GW_BUSY 0x541F080
+
+#define mmNIC0_QPC0_GW_CTRL 0x541F084
+
+#define mmNIC0_QPC0_GW_DATA_0 0x541F08C
+
+#define mmNIC0_QPC0_GW_DATA_1 0x541F090
+
+#define mmNIC0_QPC0_GW_DATA_2 0x541F094
+
+#define mmNIC0_QPC0_GW_DATA_3 0x541F098
+
+#define mmNIC0_QPC0_GW_DATA_4 0x541F09C
+
+#define mmNIC0_QPC0_GW_DATA_5 0x541F0A0
+
+#define mmNIC0_QPC0_GW_DATA_6 0x541F0A4
+
+#define mmNIC0_QPC0_GW_DATA_7 0x541F0A8
+
+#define mmNIC0_QPC0_GW_DATA_8 0x541F0AC
+
+#define mmNIC0_QPC0_GW_DATA_9 0x541F0B0
+
+#define mmNIC0_QPC0_GW_DATA_10 0x541F0B4
+
+#define mmNIC0_QPC0_GW_DATA_11 0x541F0B8
+
+#define mmNIC0_QPC0_GW_DATA_12 0x541F0BC
+
+#define mmNIC0_QPC0_GW_DATA_13 0x541F0C0
+
+#define mmNIC0_QPC0_GW_DATA_14 0x541F0C4
+
+#define mmNIC0_QPC0_GW_DATA_15 0x541F0C8
+
+#define mmNIC0_QPC0_GW_DATA_16 0x541F0CC
+
+#define mmNIC0_QPC0_GW_DATA_17 0x541F0D0
+
+#define mmNIC0_QPC0_GW_DATA_18 0x541F0D4
+
+#define mmNIC0_QPC0_GW_DATA_19 0x541F0D8
+
+#define mmNIC0_QPC0_GW_DATA_20 0x541F0DC
+
+#define mmNIC0_QPC0_GW_DATA_21 0x541F0E0
+
+#define mmNIC0_QPC0_GW_DATA_22 0x541F0E4
+
+#define mmNIC0_QPC0_GW_DATA_23 0x541F0E8
+
+#define mmNIC0_QPC0_GW_DATA_24 0x541F0EC
+
+#define mmNIC0_QPC0_GW_DATA_25 0x541F0F0
+
+#define mmNIC0_QPC0_GW_DATA_26 0x541F0F4
+
+#define mmNIC0_QPC0_GW_DATA_27 0x541F0F8
+
+#define mmNIC0_QPC0_GW_DATA_28 0x541F0FC
+
+#define mmNIC0_QPC0_GW_DATA_29 0x541F100
+
+#define mmNIC0_QPC0_GW_DATA_30 0x541F104
+
+#define mmNIC0_QPC0_GW_DATA_31 0x541F108
+
+#define mmNIC0_QPC0_GW_MASK_0 0x541F124
+
+#define mmNIC0_QPC0_GW_MASK_1 0x541F128
+
+#define mmNIC0_QPC0_GW_MASK_2 0x541F12C
+
+#define mmNIC0_QPC0_GW_MASK_3 0x541F130
+
+#define mmNIC0_QPC0_GW_MASK_4 0x541F134
+
+#define mmNIC0_QPC0_GW_MASK_5 0x541F138
+
+#define mmNIC0_QPC0_GW_MASK_6 0x541F13C
+
+#define mmNIC0_QPC0_GW_MASK_7 0x541F140
+
+#define mmNIC0_QPC0_GW_MASK_8 0x541F144
+
+#define mmNIC0_QPC0_GW_MASK_9 0x541F148
+
+#define mmNIC0_QPC0_GW_MASK_10 0x541F14C
+
+#define mmNIC0_QPC0_GW_MASK_11 0x541F150
+
+#define mmNIC0_QPC0_GW_MASK_12 0x541F154
+
+#define mmNIC0_QPC0_GW_MASK_13 0x541F158
+
+#define mmNIC0_QPC0_GW_MASK_14 0x541F15C
+
+#define mmNIC0_QPC0_GW_MASK_15 0x541F160
+
+#define mmNIC0_QPC0_GW_MASK_16 0x541F164
+
+#define mmNIC0_QPC0_GW_MASK_17 0x541F168
+
+#define mmNIC0_QPC0_GW_MASK_18 0x541F16C
+
+#define mmNIC0_QPC0_GW_MASK_19 0x541F170
+
+#define mmNIC0_QPC0_GW_MASK_20 0x541F174
+
+#define mmNIC0_QPC0_GW_MASK_21 0x541F178
+
+#define mmNIC0_QPC0_GW_MASK_22 0x541F17C
+
+#define mmNIC0_QPC0_GW_MASK_23 0x541F180
+
+#define mmNIC0_QPC0_GW_MASK_24 0x541F184
+
+#define mmNIC0_QPC0_GW_MASK_25 0x541F188
+
+#define mmNIC0_QPC0_GW_MASK_26 0x541F18C
+
+#define mmNIC0_QPC0_GW_MASK_27 0x541F190
+
+#define mmNIC0_QPC0_GW_MASK_28 0x541F194
+
+#define mmNIC0_QPC0_GW_MASK_29 0x541F198
+
+#define mmNIC0_QPC0_GW_MASK_30 0x541F19C
+
+#define mmNIC0_QPC0_GW_MASK_31 0x541F1A0
+
+#define mmNIC0_QPC0_CC_TIMEOUT 0x541F1B0
+
+#define mmNIC0_QPC0_CC_WINDOW_INC_EN 0x541F1FC
+
+#define mmNIC0_QPC0_CC_TICK_WRAP 0x541F200
+
+#define mmNIC0_QPC0_CC_ROLLBACK 0x541F204
+
+#define mmNIC0_QPC0_CC_MAX_WINDOW_SIZE 0x541F208
+
+#define mmNIC0_QPC0_CC_MIN_WINDOW_SIZE 0x541F20C
+
+#define mmNIC0_QPC0_CC_ALPHA_LINEAR_0 0x541F210
+
+#define mmNIC0_QPC0_CC_ALPHA_LINEAR_1 0x541F214
+
+#define mmNIC0_QPC0_CC_ALPHA_LINEAR_2 0x541F218
+
+#define mmNIC0_QPC0_CC_ALPHA_LINEAR_3 0x541F21C
+
+#define mmNIC0_QPC0_CC_ALPHA_LINEAR_4 0x541F220
+
+#define mmNIC0_QPC0_CC_ALPHA_LINEAR_5 0x541F224
+
+#define mmNIC0_QPC0_CC_ALPHA_LINEAR_6 0x541F228
+
+#define mmNIC0_QPC0_CC_ALPHA_LINEAR_7 0x541F22C
+
+#define mmNIC0_QPC0_CC_ALPHA_LINEAR_8 0x541F230
+
+#define mmNIC0_QPC0_CC_ALPHA_LINEAR_9 0x541F234
+
+#define mmNIC0_QPC0_CC_ALPHA_LINEAR_10 0x541F238
+
+#define mmNIC0_QPC0_CC_ALPHA_LINEAR_11 0x541F23C
+
+#define mmNIC0_QPC0_CC_ALPHA_LINEAR_12 0x541F240
+
+#define mmNIC0_QPC0_CC_ALPHA_LINEAR_13 0x541F244
+
+#define mmNIC0_QPC0_CC_ALPHA_LINEAR_14 0x541F248
+
+#define mmNIC0_QPC0_CC_ALPHA_LINEAR_15 0x541F24C
+
+#define mmNIC0_QPC0_CC_ALPHA_LOG_0 0x541F250
+
+#define mmNIC0_QPC0_CC_ALPHA_LOG_1 0x541F254
+
+#define mmNIC0_QPC0_CC_ALPHA_LOG_2 0x541F258
+
+#define mmNIC0_QPC0_CC_ALPHA_LOG_3 0x541F25C
+
+#define mmNIC0_QPC0_CC_ALPHA_LOG_4 0x541F260
+
+#define mmNIC0_QPC0_CC_ALPHA_LOG_5 0x541F264
+
+#define mmNIC0_QPC0_CC_ALPHA_LOG_6 0x541F268
+
+#define mmNIC0_QPC0_CC_ALPHA_LOG_7 0x541F26C
+
+#define mmNIC0_QPC0_CC_ALPHA_LOG_8 0x541F270
+
+#define mmNIC0_QPC0_CC_ALPHA_LOG_9 0x541F274
+
+#define mmNIC0_QPC0_CC_ALPHA_LOG_10 0x541F278
+
+#define mmNIC0_QPC0_CC_ALPHA_LOG_11 0x541F27C
+
+#define mmNIC0_QPC0_CC_ALPHA_LOG_12 0x541F280
+
+#define mmNIC0_QPC0_CC_ALPHA_LOG_13 0x541F284
+
+#define mmNIC0_QPC0_CC_ALPHA_LOG_14 0x541F288
+
+#define mmNIC0_QPC0_CC_ALPHA_LOG_15 0x541F28C
+
+#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_0 0x541F290
+
+#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_1 0x541F294
+
+#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_2 0x541F298
+
+#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_3 0x541F29C
+
+#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_4 0x541F2A0
+
+#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_5 0x541F2A4
+
+#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_6 0x541F2A8
+
+#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_7 0x541F2AC
+
+#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_8 0x541F2B0
+
+#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_9 0x541F2B4
+
+#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_10 0x541F2B8
+
+#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_11 0x541F2BC
+
+#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_12 0x541F2C0
+
+#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_13 0x541F2C4
+
+#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_14 0x541F2C8
+
+#define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_15 0x541F2CC
+
+#define mmNIC0_QPC0_CC_WINDOW_INC_0 0x541F2D0
+
+#define mmNIC0_QPC0_CC_WINDOW_INC_1 0x541F2D4
+
+#define mmNIC0_QPC0_CC_WINDOW_INC_2 0x541F2D8
+
+#define mmNIC0_QPC0_CC_WINDOW_INC_3 0x541F2DC
+
+#define mmNIC0_QPC0_CC_WINDOW_INC_4 0x541F2E0
+
+#define mmNIC0_QPC0_CC_WINDOW_INC_5 0x541F2E4
+
+#define mmNIC0_QPC0_CC_WINDOW_INC_6 0x541F2E8
+
+#define mmNIC0_QPC0_CC_WINDOW_INC_7 0x541F2EC
+
+#define mmNIC0_QPC0_CC_WINDOW_INC_8 0x541F2F0
+
+#define mmNIC0_QPC0_CC_WINDOW_INC_9 0x541F2F4
+
+#define mmNIC0_QPC0_CC_WINDOW_INC_10 0x541F2F8
+
+#define mmNIC0_QPC0_CC_WINDOW_INC_11 0x541F2FC
+
+#define mmNIC0_QPC0_CC_WINDOW_INC_12 0x541F300
+
+#define mmNIC0_QPC0_CC_WINDOW_INC_13 0x541F304
+
+#define mmNIC0_QPC0_CC_WINDOW_INC_14 0x541F308
+
+#define mmNIC0_QPC0_CC_WINDOW_INC_15 0x541F30C
+
+#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_0 0x541F310
+
+#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_1 0x541F314
+
+#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_2 0x541F318
+
+#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_3 0x541F31C
+
+#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_4 0x541F320
+
+#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_5 0x541F324
+
+#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_6 0x541F328
+
+#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_7 0x541F32C
+
+#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_8 0x541F330
+
+#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_9 0x541F334
+
+#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_10 0x541F338
+
+#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_11 0x541F33C
+
+#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_12 0x541F340
+
+#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_13 0x541F344
+
+#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_14 0x541F348
+
+#define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_15 0x541F34C
+
+#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_0 0x541F360
+
+#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_1 0x541F364
+
+#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_2 0x541F368
+
+#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_3 0x541F36C
+
+#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_4 0x541F370
+
+#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_5 0x541F374
+
+#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_6 0x541F378
+
+#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_7 0x541F37C
+
+#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_8 0x541F380
+
+#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_9 0x541F384
+
+#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_10 0x541F388
+
+#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_11 0x541F38C
+
+#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_12 0x541F390
+
+#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_13 0x541F394
+
+#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_14 0x541F398
+
+#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_15 0x541F39C
+
+#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_16 0x541F3A0
+
+#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_17 0x541F3A4
+
+#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_18 0x541F3A8
+
+#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_19 0x541F3AC
+
+#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_20 0x541F3B0
+
+#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_21 0x541F3B4
+
+#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_22 0x541F3B8
+
+#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_23 0x541F3BC
+
+#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_24 0x541F3C0
+
+#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_25 0x541F3C4
+
+#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_26 0x541F3C8
+
+#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_27 0x541F3CC
+
+#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_28 0x541F3D0
+
+#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_29 0x541F3D4
+
+#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_30 0x541F3D8
+
+#define mmNIC0_QPC0_DB_FIFO_USER_OVRD_31 0x541F3DC
+
+#define mmNIC0_QPC0_DB_FIFO_CFG_0 0x541F3E0
+
+#define mmNIC0_QPC0_DB_FIFO_CFG_1 0x541F3E4
+
+#define mmNIC0_QPC0_DB_FIFO_CFG_2 0x541F3E8
+
+#define mmNIC0_QPC0_DB_FIFO_CFG_3 0x541F3EC
+
+#define mmNIC0_QPC0_DB_FIFO_CFG_4 0x541F3F0
+
+#define mmNIC0_QPC0_DB_FIFO_CFG_5 0x541F3F4
+
+#define mmNIC0_QPC0_DB_FIFO_CFG_6 0x541F3F8
+
+#define mmNIC0_QPC0_DB_FIFO_CFG_7 0x541F3FC
+
+#define mmNIC0_QPC0_DB_FIFO_CFG_8 0x541F400
+
+#define mmNIC0_QPC0_DB_FIFO_CFG_9 0x541F404
+
+#define mmNIC0_QPC0_DB_FIFO_CFG_10 0x541F408
+
+#define mmNIC0_QPC0_DB_FIFO_CFG_11 0x541F40C
+
+#define mmNIC0_QPC0_DB_FIFO_CFG_12 0x541F410
+
+#define mmNIC0_QPC0_DB_FIFO_CFG_13 0x541F414
+
+#define mmNIC0_QPC0_DB_FIFO_CFG_14 0x541F418
+
+#define mmNIC0_QPC0_DB_FIFO_CFG_15 0x541F41C
+
+#define mmNIC0_QPC0_DB_FIFO_CFG_16 0x541F420
+
+#define mmNIC0_QPC0_DB_FIFO_CFG_17 0x541F424
+
+#define mmNIC0_QPC0_DB_FIFO_CFG_18 0x541F428
+
+#define mmNIC0_QPC0_DB_FIFO_CFG_19 0x541F42C
+
+#define mmNIC0_QPC0_DB_FIFO_CFG_20 0x541F430
+
+#define mmNIC0_QPC0_DB_FIFO_CFG_21 0x541F434
+
+#define mmNIC0_QPC0_DB_FIFO_CFG_22 0x541F438
+
+#define mmNIC0_QPC0_DB_FIFO_CFG_23 0x541F43C
+
+#define mmNIC0_QPC0_DB_FIFO_CFG_24 0x541F440
+
+#define mmNIC0_QPC0_DB_FIFO_CFG_25 0x541F444
+
+#define mmNIC0_QPC0_DB_FIFO_CFG_26 0x541F448
+
+#define mmNIC0_QPC0_DB_FIFO_CFG_27 0x541F44C
+
+#define mmNIC0_QPC0_DB_FIFO_CFG_28 0x541F450
+
+#define mmNIC0_QPC0_DB_FIFO_CFG_29 0x541F454
+
+#define mmNIC0_QPC0_DB_FIFO_CFG_30 0x541F458
+
+#define mmNIC0_QPC0_DB_FIFO_CFG_31 0x541F45C
+
+#define mmNIC0_QPC0_SECURED_DB_FIRST32 0x541F460
+
+#define mmNIC0_QPC0_SECURED_DB_SECOND32 0x541F464
+
+#define mmNIC0_QPC0_SECURED_DB_THIRD32 0x541F468
+
+#define mmNIC0_QPC0_SECURED_DB_FOURTH32 0x541F46C
+
+#define mmNIC0_QPC0_PRIVILEGE_DB_FIRST32 0x541F470
+
+#define mmNIC0_QPC0_PRIVILEGE_DB_SECOND32 0x541F474
+
+#define mmNIC0_QPC0_PRIVILEGE_DB_THIRD32 0x541F478
+
+#define mmNIC0_QPC0_PRIVILEGE_DB_FOURTH32 0x541F47C
+
+#define mmNIC0_QPC0_DBG_INDICATION 0x541F480
+
+#define mmNIC0_QPC0_WTD_WC_FSM 0x541F484
+
+#define mmNIC0_QPC0_WTD_SLICE_FSM 0x541F488
+
+#define mmNIC0_QPC0_REQ_TX_EMPTY_CNT 0x541F48C
+
+#define mmNIC0_QPC0_RES_TX_EMPTY_CNT 0x541F490
+
+#define mmNIC0_QPC0_NUM_ROLLBACKS 0x541F494
+
+#define mmNIC0_QPC0_LAST_QP_ROLLED_BACK 0x541F498
+
+#define mmNIC0_QPC0_NUM_TIMEOUTS 0x541F49C
+
+#define mmNIC0_QPC0_LAST_QP_TIMED_OUT 0x541F4A0
+
+#define mmNIC0_QPC0_WTD_SLICE_FSM_HI 0x541F4A4
+
+#define mmNIC0_QPC0_INTERRUPT_BASE_0 0x541F4B0
+
+#define mmNIC0_QPC0_INTERRUPT_BASE_1 0x541F4B4
+
+#define mmNIC0_QPC0_INTERRUPT_BASE_2 0x541F4B8
+
+#define mmNIC0_QPC0_INTERRUPT_BASE_3 0x541F4BC
+
+#define mmNIC0_QPC0_INTERRUPT_BASE_4 0x541F4C0
+
+#define mmNIC0_QPC0_INTERRUPT_BASE_5 0x541F4C4
+
+#define mmNIC0_QPC0_INTERRUPT_BASE_6 0x541F4C8
+
+#define mmNIC0_QPC0_INTERRUPT_BASE_7 0x541F4CC
+
+#define mmNIC0_QPC0_INTERRUPT_BASE_8 0x541F4D0
+
+#define mmNIC0_QPC0_INTERRUPT_BASE_9 0x541F4D4
+
+#define mmNIC0_QPC0_INTERRUPT_BASE_10 0x541F4D8
+
+#define mmNIC0_QPC0_INTERRUPT_DATA_0 0x541F4DC
+
+#define mmNIC0_QPC0_INTERRUPT_DATA_1 0x541F4E0
+
+#define mmNIC0_QPC0_INTERRUPT_DATA_2 0x541F4E4
+
+#define mmNIC0_QPC0_INTERRUPT_DATA_3 0x541F4E8
+
+#define mmNIC0_QPC0_INTERRUPT_DATA_4 0x541F4EC
+
+#define mmNIC0_QPC0_INTERRUPT_DATA_5 0x541F4F0
+
+#define mmNIC0_QPC0_INTERRUPT_DATA_6 0x541F4F4
+
+#define mmNIC0_QPC0_INTERRUPT_DATA_7 0x541F4F8
+
+#define mmNIC0_QPC0_INTERRUPT_DATA_8 0x541F4FC
+
+#define mmNIC0_QPC0_INTERRUPT_DATA_9 0x541F500
+
+#define mmNIC0_QPC0_INTERRUPT_DATA_10 0x541F504
+
+#define mmNIC0_QPC0_DBG_COUNT_SELECT_0 0x541F600
+
+#define mmNIC0_QPC0_DBG_COUNT_SELECT_1 0x541F604
+
+#define mmNIC0_QPC0_DBG_COUNT_SELECT_2 0x541F608
+
+#define mmNIC0_QPC0_DBG_COUNT_SELECT_3 0x541F60C
+
+#define mmNIC0_QPC0_DBG_COUNT_SELECT_4 0x541F610
+
+#define mmNIC0_QPC0_DBG_COUNT_SELECT_5 0x541F614
+
+#define mmNIC0_QPC0_DBG_COUNT_SELECT_6 0x541F618
+
+#define mmNIC0_QPC0_DBG_COUNT_SELECT_7 0x541F61C
+
+#define mmNIC0_QPC0_DBG_COUNT_SELECT_8 0x541F620
+
+#define mmNIC0_QPC0_DBG_COUNT_SELECT_9 0x541F624
+
+#define mmNIC0_QPC0_DBG_COUNT_SELECT_10 0x541F628
+
+#define mmNIC0_QPC0_DBG_COUNT_SELECT_11 0x541F62C
+
+#define mmNIC0_QPC0_DOORBELL_SECURITY 0x541F648
+
+#define mmNIC0_QPC0_DBG_CFG 0x541F64C
+
+#define mmNIC0_QPC0_RES_RING0_PI 0x541F650
+
+#define mmNIC0_QPC0_RES_RING0_CI 0x541F654
+
+#define mmNIC0_QPC0_RES_RING0_CFG 0x541F658
+
+#define mmNIC0_QPC0_RES_RING1_PI 0x541F65C
+
+#define mmNIC0_QPC0_RES_RING1_CI 0x541F660
+
+#define mmNIC0_QPC0_RES_RING1_CFG 0x541F664
+
+#define mmNIC0_QPC0_RES_RING2_PI 0x541F668
+
+#define mmNIC0_QPC0_RES_RING2_CI 0x541F66C
+
+#define mmNIC0_QPC0_RES_RING2_CFG 0x541F670
+
+#define mmNIC0_QPC0_RES_RING3_PI 0x541F674
+
+#define mmNIC0_QPC0_RES_RING3_CI 0x541F678
+
+#define mmNIC0_QPC0_RES_RING3_CFG 0x541F67C
+
+#define mmNIC0_QPC0_REQ_RING0_CI 0x541F680
+
+#define mmNIC0_QPC0_REQ_RING1_CI 0x541F684
+
+#define mmNIC0_QPC0_REQ_RING2_CI 0x541F688
+
+#define mmNIC0_QPC0_REQ_RING3_CI 0x541F68C
+
+#define mmNIC0_QPC0_INTERRUPT_CAUSE 0x541F690
+
+#define mmNIC0_QPC0_INTERRUPT_MASK 0x541F694
+
+#define mmNIC0_QPC0_INTERRUPT_CLR 0x541F698
+
+#define mmNIC0_QPC0_INTERRUPT_EN 0x541F69C
+
+#define mmNIC0_QPC0_INTERRUPT_CFG 0x541F6F0
+
+#define mmNIC0_QPC0_INTERRUPT_RESP_ERR_CAUSE 0x541F6F4
+
+#define mmNIC0_QPC0_INTERRUPT_RESP_ERR_MASK 0x541F6F8
+
+#define mmNIC0_QPC0_INTERRUPR_RESP_ERR_CLR 0x541F700
+
+#define mmNIC0_QPC0_TMR_GW_VALID 0x541F704
+
+#define mmNIC0_QPC0_TMR_GW_DATA0 0x541F708
+
+#define mmNIC0_QPC0_TMR_GW_DATA1 0x541F70C
+
+#define mmNIC0_QPC0_RNR_RETRY_COUNT_EN 0x541F710
+
+#define mmNIC0_QPC0_EVENT_QUE_BASE_ADDR_63_32 0x541F830
+
+#define mmNIC0_QPC0_EVENT_QUE_BASE_ADDR_31_7 0x541F834
+
+#define mmNIC0_QPC0_EVENT_QUE_LOG_SIZE 0x541F838
+
+#define mmNIC0_QPC0_EVENT_QUE_WRITE_INDEX 0x541F83C
+
+#define mmNIC0_QPC0_EVENT_QUE_PRODUCER_INDEX 0x541F840
+
+#define mmNIC0_QPC0_EVENT_QUE_PI_ADDR_63_32 0x541F844
+
+#define mmNIC0_QPC0_EVENT_QUE_PI_ADDR_31_7 0x541F848
+
+#define mmNIC0_QPC0_EVENT_QUE_CONSUMER_INDEX_CB 0x541F84C
+
+#define mmNIC0_QPC0_EVENT_QUE_CFG 0x541F850
+
+#define mmNIC0_QPC0_LBW_PROT 0x541F858
+
+#define mmNIC0_QPC0_MEM_WRITE_INIT 0x541F85C
+
+#define mmNIC0_QPC0_QMAN_DOORBELL 0x541F8E8
+
+#define mmNIC0_QPC0_QMAN_DOORBELL_QPN 0x541F8EC
+
+#define mmNIC0_QPC0_SECURED_CQ_NUMBER 0x541F8F0
+
+#define mmNIC0_QPC0_SECURED_CQ_CONSUMER_INDEX 0x541F8F4
+
+#define mmNIC0_QPC0_PRIVILEGE_CQ_NUMBER 0x541F8F8
+
+#define mmNIC0_QPC0_PRIVILEGE_CQ_CONSUMER_INDEX 0x541F8FC
+
+#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_63_32_0 0x541F900
+
+#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_63_32_1 0x541F904
+
+#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_63_32_2 0x541F908
+
+#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_63_32_3 0x541F90C
+
+#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_31_0_0 0x541F910
+
+#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_31_0_1 0x541F914
+
+#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_31_0_2 0x541F918
+
+#define mmNIC0_QPC0_TX_WQ_BASE_ADDR_31_0_3 0x541F91C
+
+#define mmNIC0_QPC0_LOG_MAX_TX_WQ_SIZE_0 0x541F920
+
+#define mmNIC0_QPC0_LOG_MAX_TX_WQ_SIZE_1 0x541F924
+
+#define mmNIC0_QPC0_LOG_MAX_TX_WQ_SIZE_2 0x541F928
+
+#define mmNIC0_QPC0_LOG_MAX_TX_WQ_SIZE_3 0x541F92C
+
+#define mmNIC0_QPC0_MMU_BYPASS_TX_WQ_0 0x541F930
+
+#define mmNIC0_QPC0_MMU_BYPASS_TX_WQ_1 0x541F934
+
+#define mmNIC0_QPC0_MMU_BYPASS_TX_WQ_2 0x541F938
+
+#define mmNIC0_QPC0_MMU_BYPASS_TX_WQ_3 0x541F93C
+
+#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_63_32_0 0x541F940
+
+#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_63_32_1 0x541F944
+
+#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_63_32_2 0x541F948
+
+#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_63_32_3 0x541F94C
+
+#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_31_0_0 0x541F950
+
+#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_31_0_1 0x541F954
+
+#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_31_0_2 0x541F958
+
+#define mmNIC0_QPC0_RX_WQ_BASE_ADDR_31_0_3 0x541F95C
+
+#define mmNIC0_QPC0_LOG_MAX_RX_WQ_SIZE_0 0x541F960
+
+#define mmNIC0_QPC0_LOG_MAX_RX_WQ_SIZE_1 0x541F964
+
+#define mmNIC0_QPC0_LOG_MAX_RX_WQ_SIZE_2 0x541F968
+
+#define mmNIC0_QPC0_LOG_MAX_RX_WQ_SIZE_3 0x541F96C
+
+#define mmNIC0_QPC0_MMU_BYPASS_RX_WQ_0 0x541F970
+
+#define mmNIC0_QPC0_MMU_BYPASS_RX_WQ_1 0x541F974
+
+#define mmNIC0_QPC0_MMU_BYPASS_RX_WQ_2 0x541F978
+
+#define mmNIC0_QPC0_MMU_BYPASS_RX_WQ_3 0x541F97C
+
+#define mmNIC0_QPC0_WQE_MEM_WRITE_AXI_PROT 0x541F980
+
+#define mmNIC0_QPC0_WQ_UPPER_THRESHOLD 0x541F984
+
+#define mmNIC0_QPC0_WQ_LOWER_THRESHOLD 0x541F988
+
+#define mmNIC0_QPC0_WQ_BP_2ARC_ADDR 0x541F98C
+
+#define mmNIC0_QPC0_WQ_BP_2QMAN_ADDR 0x541F990
+
+#define mmNIC0_QPC0_WTD_CONFIG 0x541F994
+
+#define mmNIC0_QPC0_REQTX_ERR_FIFO_PUSH_63_32 0x541F998
+
+#define mmNIC0_QPC0_REQTX_ERR_FIFO_PUSH_31_0 0x541F99C
+
+#define mmNIC0_QPC0_REQTX_ERR_QP_STATE_63_32 0x541F9A0
+
+#define mmNIC0_QPC0_REQTX_ERR_QP_STATE_31_0 0x541F9A4
+
+#define mmNIC0_QPC0_EVENT_QUE_CONSUMER_INDEX 0x541F9A8
+
+#define mmNIC0_QPC0_ARM_CQ_NUM 0x541F9AC
+
+#define mmNIC0_QPC0_ARM_CQ_INDEX 0x541F9B0
+
+#define mmNIC0_QPC0_QPC_CLOCK_GATE 0x541F9B4
+
+#define mmNIC0_QPC0_QPC_CLOCK_GATE_DIS 0x541F9B8
+
+#define mmNIC0_QPC0_CONG_QUE_BASE_ADDR_63_32 0x541F9BC
+
+#define mmNIC0_QPC0_CONG_QUE_BASE_ADDR_31_7 0x541F9C0
+
+#define mmNIC0_QPC0_CONG_QUE_LOG_SIZE 0x541F9C4
+
+#define mmNIC0_QPC0_CONG_QUE_WRITE_INDEX 0x541F9C8
+
+#define mmNIC0_QPC0_CONG_QUE_PRODUCER_INDEX 0x541F9CC
+
+#define mmNIC0_QPC0_CONG_QUE_PI_ADDR_63_32 0x541F9D0
+
+#define mmNIC0_QPC0_CONG_QUE_PI_ADDR_31_7 0x541F9D4
+
+#define mmNIC0_QPC0_CONG_QUE_CONSUMER_INDEX_CB 0x541F9D8
+
+#define mmNIC0_QPC0_CONG_QUE_CFG 0x541F9DC
+
+#define mmNIC0_QPC0_CONG_QUE_CONSUMER_INDEX 0x541F9E0
+
+#define mmNIC0_QPC0_LINEAR_WQE_STATIC_0 0x541FA00
+
+#define mmNIC0_QPC0_LINEAR_WQE_STATIC_1 0x541FA04
+
+#define mmNIC0_QPC0_LINEAR_WQE_STATIC_2 0x541FA08
+
+#define mmNIC0_QPC0_LINEAR_WQE_STATIC_3 0x541FA0C
+
+#define mmNIC0_QPC0_LINEAR_WQE_STATIC_4 0x541FA10
+
+#define mmNIC0_QPC0_LINEAR_WQE_STATIC_5 0x541FA14
+
+#define mmNIC0_QPC0_LINEAR_WQE_STATIC_6 0x541FA18
+
+#define mmNIC0_QPC0_LINEAR_WQE_STATIC_7 0x541FA1C
+
+#define mmNIC0_QPC0_LINEAR_WQE_STATIC_8 0x541FA20
+
+#define mmNIC0_QPC0_LINEAR_WQE_STATIC_9 0x541FA24
+
+#define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_0 0x541FA40
+
+#define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_1 0x541FA44
+
+#define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_2 0x541FA48
+
+#define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_3 0x541FA4C
+
+#define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_4 0x541FA50
+
+#define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_5 0x541FA54
+
+#define mmNIC0_QPC0_LINEAR_WQE_QPN 0x541FA58
+
+#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_0 0x541FA80
+
+#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_1 0x541FA84
+
+#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_2 0x541FA88
+
+#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_3 0x541FA8C
+
+#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_4 0x541FA90
+
+#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_5 0x541FA94
+
+#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_6 0x541FA98
+
+#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_7 0x541FA9C
+
+#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_8 0x541FAA0
+
+#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_9 0x541FAA4
+
+#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_10 0x541FAA8
+
+#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_11 0x541FAAC
+
+#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_12 0x541FAB0
+
+#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_13 0x541FAB4
+
+#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_14 0x541FAB8
+
+#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_15 0x541FABC
+
+#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_16 0x541FAC0
+
+#define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_17 0x541FAC4
+
+#define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_0 0x541FAE0
+
+#define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_1 0x541FAE4
+
+#define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_2 0x541FAE8
+
+#define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_3 0x541FAEC
+
+#define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_4 0x541FAF0
+
+#define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_5 0x541FAF4
+
+#define mmNIC0_QPC0_MULTI_STRIDE_WQE_QPN 0x541FAF8
+
+#endif /* ASIC_REG_NIC0_QPC0_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_umr0_0_completion_queue_ci_1_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_umr0_0_completion_queue_ci_1_regs.h
new file mode 100644
index 000000000000..2153319a50a0
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_umr0_0_completion_queue_ci_1_regs.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_UMR0_0_COMPLETION_QUEUE_CI_1_REGS_H_
+#define ASIC_REG_NIC0_UMR0_0_COMPLETION_QUEUE_CI_1_REGS_H_
+
+/*
+ *****************************************
+ *   NIC0_UMR0_0_COMPLETION_QUEUE_CI_1
+ *   (Prototype: COMPLETION_QUEUE_CI)
+ *****************************************
+ */
+
+#define mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_NUMBER 0x5400180
+
+#define mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX 0x5400184
+
+#endif /* ASIC_REG_NIC0_UMR0_0_COMPLETION_QUEUE_CI_1_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_umr0_0_unsecure_doorbell0_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_umr0_0_unsecure_doorbell0_regs.h
new file mode 100644
index 000000000000..de8eac74c2fb
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_umr0_0_unsecure_doorbell0_regs.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_UMR0_0_UNSECURE_DOORBELL0_REGS_H_
+#define ASIC_REG_NIC0_UMR0_0_UNSECURE_DOORBELL0_REGS_H_
+
+/*
+ *****************************************
+ *   NIC0_UMR0_0_UNSECURE_DOORBELL0
+ *   (Prototype: NIC_UNSEC_DBELL)
+ *****************************************
+ */
+
+#define mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 0x5400000
+
+#define mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_SECOND32 0x5400004
+
+#define mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_THIRD32 0x5400008
+
+#define mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FOURTH32 0x540000C
+
+#endif /* ASIC_REG_NIC0_UMR0_0_UNSECURE_DOORBELL0_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_aux_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_aux_regs.h
new file mode 100644
index 000000000000..44182fc18234
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_aux_regs.h
@@ -0,0 +1,293 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PCIE_AUX_REGS_H_
+#define ASIC_REG_PCIE_AUX_REGS_H_
+
+/*
+ *****************************************
+ *   PCIE_AUX
+ *   (Prototype: PCIE_AUX)
+ *****************************************
+ */
+
+#define mmPCIE_AUX_APB_TIMEOUT 0x4C07004
+
+#define mmPCIE_AUX_SW_GENERAL_PURPOSE_0 0x4C07008
+
+#define mmPCIE_AUX_SW_GENERAL_PURPOSE_1 0x4C0700C
+
+#define mmPCIE_AUX_SW_GENERAL_PURPOSE_2 0x4C07010
+
+#define mmPCIE_AUX_SW_GENERAL_PURPOSE_3 0x4C07014
+
+#define mmPCIE_AUX_SW_GENERAL_PURPOSE_4 0x4C07018
+
+#define mmPCIE_AUX_SW_GENERAL_PURPOSE_5 0x4C0701C
+
+#define mmPCIE_AUX_SW_GENERAL_PURPOSE_6 0x4C07020
+
+#define mmPCIE_AUX_SW_GENERAL_PURPOSE_7 0x4C07024
+
+#define mmPCIE_AUX_PHY_INIT 0x4C07100
+
+#define mmPCIE_AUX_LTR_MAX_LATENCY 0x4C07138
+
+#define mmPCIE_AUX_BAR0_START_L 0x4C07160
+
+#define mmPCIE_AUX_BAR0_START_H 0x4C07164
+
+#define mmPCIE_AUX_BAR1_START 0x4C07168
+
+#define mmPCIE_AUX_BAR2_START_L 0x4C0716C
+
+#define mmPCIE_AUX_BAR2_START_H 0x4C07170
+
+#define mmPCIE_AUX_BAR3_START 0x4C07174
+
+#define mmPCIE_AUX_BAR4_START_L 0x4C07178
+
+#define mmPCIE_AUX_BAR4_START_H 0x4C0717C
+
+#define mmPCIE_AUX_BAR5_START 0x4C07180
+
+#define mmPCIE_AUX_BAR0_LIMIT_L 0x4C07184
+
+#define mmPCIE_AUX_BAR0_LIMIT_H 0x4C07188
+
+#define mmPCIE_AUX_BAR1_LIMIT 0x4C0718C
+
+#define mmPCIE_AUX_BAR2_LIMIT_L 0x4C07190
+
+#define mmPCIE_AUX_BAR2_LIMIT_H 0x4C07194
+
+#define mmPCIE_AUX_BAR3_LIMIT 0x4C07198
+
+#define mmPCIE_AUX_BAR4_LIMIT_L 0x4C0719C
+
+#define mmPCIE_AUX_BAR4_LIMIT_H 0x4C07200
+
+#define mmPCIE_AUX_BAR5_LIMIT 0x4C07204
+
+#define mmPCIE_AUX_BUS_MASTER_EN 0x4C07208
+
+#define mmPCIE_AUX_MEM_SPACE_EN 0x4C0720C
+
+#define mmPCIE_AUX_MAX_RD_REQ_SIZE 0x4C07210
+
+#define mmPCIE_AUX_MAX_PAYLOAD_SIZE 0x4C07214
+
+#define mmPCIE_AUX_EXT_TAG_EN 0x4C07218
+
+#define mmPCIE_AUX_RCB 0x4C0721C
+
+#define mmPCIE_AUX_PM_NO_SOFT_RST 0x4C07220
+
+#define mmPCIE_AUX_PBUS_NUM 0x4C07224
+
+#define mmPCIE_AUX_PBUS_DEV_NUM 0x4C07228
+
+#define mmPCIE_AUX_NO_SNOOP_EN 0x4C0722C
+
+#define mmPCIE_AUX_RELAX_ORDER_EN 0x4C07230
+
+#define mmPCIE_AUX_HP_SLOT_CTRL_ACCESS 0x4C07234
+
+#define mmPCIE_AUX_DLL_STATE_CHGED_EN 0x4C07238
+
+#define mmPCIE_AUX_CMP_CPLED_INT_EN 0x4C0723C
+
+#define mmPCIE_AUX_HP_INT_EN 0x4C07340
+
+#define mmPCIE_AUX_PRE_DET_CHGEN_EN 0x4C07344
+
+#define mmPCIE_AUX_MRL_SENSOR_CHGED_EN 0x4C07348
+
+#define mmPCIE_AUX_PWR_FAULT_DET_EN 0x4C0734C
+
+#define mmPCIE_AUX_ATTEN_BUTTON_PRESSED_EN 0x4C07350
+
+#define mmPCIE_AUX_PF_FLR_ACTIVE 0x4C07360
+
+#define mmPCIE_AUX_PF_FLR_DONE 0x4C07364
+
+#define mmPCIE_AUX_FLR_INT 0x4C07390
+
+#define mmPCIE_AUX_FLR_CTRL 0x4C07394
+
+#define mmPCIE_AUX_LTR_M_EN 0x4C073B0
+
+#define mmPCIE_AUX_LTSSM_EN 0x4C07428
+
+#define mmPCIE_AUX_SYS_INTR 0x4C07440
+
+#define mmPCIE_AUX_INT_DISABLE 0x4C07444
+
+#define mmPCIE_AUX_SMLH_LINK_UP 0x4C07448
+
+#define mmPCIE_AUX_PM_CURR_STATE 0x4C07450
+
+#define mmPCIE_AUX_RDLH_LINK_UP 0x4C07458
+
+#define mmPCIE_AUX_BRDG_SLV_XFER_PENDING 0x4C0745C
+
+#define mmPCIE_AUX_BRDG_DBI_XFER_PENDING 0x4C07460
+
+#define mmPCIE_AUX_AUTO_SP_DIS 0x4C07478
+
+#define mmPCIE_AUX_DBI 0x4C07490
+
+#define mmPCIE_AUX_DBI_32 0x4C07494
+
+#define mmPCIE_AUX_DIAG_STATUS_BUS_0 0x4C074A4
+
+#define mmPCIE_AUX_DIAG_STATUS_BUS_1 0x4C074A8
+
+#define mmPCIE_AUX_DIAG_STATUS_BUS_2 0x4C074AC
+
+#define mmPCIE_AUX_DIAG_STATUS_BUS_3 0x4C074B0
+
+#define mmPCIE_AUX_DIAG_STATUS_BUS_4 0x4C074B4
+
+#define mmPCIE_AUX_DIAG_STATUS_BUS_5 0x4C074B8
+
+#define mmPCIE_AUX_DIAG_STATUS_BUS_6 0x4C074BC
+
+#define mmPCIE_AUX_DIAG_STATUS_BUS_7 0x4C074C0
+
+#define mmPCIE_AUX_DIAG_STATUS_BUS_8 0x4C074C4
+
+#define mmPCIE_AUX_DIAG_STATUS_BUS_9 0x4C074C8
+
+#define mmPCIE_AUX_DIAG_STATUS_BUS_10 0x4C074CC
+
+#define mmPCIE_AUX_DIAG_STATUS_BUS_11 0x4C074D0
+
+#define mmPCIE_AUX_DIAG_STATUS_BUS_12 0x4C074D4
+
+#define mmPCIE_AUX_DIAG_STATUS_BUS_13 0x4C074D8
+
+#define mmPCIE_AUX_DIAG_STATUS_BUS_14 0x4C074DC
+
+#define mmPCIE_AUX_DIAG_STATUS_BUS_15 0x4C074E0
+
+#define mmPCIE_AUX_DIAG_STATUS_BUS_16 0x4C074E4
+
+#define mmPCIE_AUX_DIAG_STATUS_BUS_17 0x4C074E8
+
+#define mmPCIE_AUX_DIAG_STATUS_BUS_18 0x4C074EC
+
+#define mmPCIE_AUX_DIAG_STATUS_BUS_19 0x4C074F0
+
+#define mmPCIE_AUX_DIAG_STATUS_BUS_20 0x4C074F4
+
+#define mmPCIE_AUX_DIAG_STATUS_BUS_21 0x4C074F8
+
+#define mmPCIE_AUX_DIAG_STATUS_BUS_22 0x4C074FC
+
+#define mmPCIE_AUX_DIAG_STATUS_BUS_23 0x4C07500
+
+#define mmPCIE_AUX_DIAG_STATUS_BUS_24 0x4C07504
+
+#define mmPCIE_AUX_DIAG_STATUS_BUS_25 0x4C07508
+
+#define mmPCIE_AUX_DIAG_STATUS_BUS_26 0x4C0750C
+
+#define mmPCIE_AUX_DIAG_STATUS_BUS_27 0x4C07510
+
+#define mmPCIE_AUX_DIAG_STATUS_BUS_28 0x4C07514
+
+#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_0 0x4C07640
+
+#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_1 0x4C07644
+
+#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_2 0x4C07648
+
+#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_3 0x4C0764C
+
+#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_4 0x4C07650
+
+#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_5 0x4C07654
+
+#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_6 0x4C07658
+
+#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_7 0x4C0765C
+
+#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_8 0x4C07660
+
+#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_9 0x4C07664
+
+#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_10 0x4C07668
+
+#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_11 0x4C0766C
+
+#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_12 0x4C07670
+
+#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_13 0x4C07674
+
+#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_14 0x4C07678
+
+#define mmPCIE_AUX_CDM_RAS_DES_EC_INFO_15 0x4C0767C
+
+#define mmPCIE_AUX_CDM_RAS_DES_SD_COMMON_0 0x4C07744
+
+#define mmPCIE_AUX_CDM_RAS_DES_SD_COMMON_1 0x4C07748
+
+#define mmPCIE_AUX_CDM_RAS_DES_SD_COMMON_2 0x4C0774C
+
+#define mmPCIE_AUX_APP_RAS_DES_TBA_CTRL 0x4C07774
+
+#define mmPCIE_AUX_PM_MASTER_STATE 0x4C07838
+
+#define mmPCIE_AUX_PM_SLAVE_STATE 0x4C0783C
+
+#define mmPCIE_AUX_PM_DSTATE 0x4C07840
+
+#define mmPCIE_AUX_PM_PME_EN 0x4C07844
+
+#define mmPCIE_AUX_PM_LINKST_IN_L0S 0x4C07848
+
+#define mmPCIE_AUX_PM_LINKST_IN_L1 0x4C0784C
+
+#define mmPCIE_AUX_PM_LINKST_IN_L2 0x4C07850
+
+#define mmPCIE_AUX_PM_LINKST_L2_EXIT 0x4C07854
+
+#define mmPCIE_AUX_PM_STATUS 0x4C07858
+
+#define mmPCIE_AUX_APP_READY_ENTER_L23 0x4C0785C
+
+#define mmPCIE_AUX_APP_XFER_PENDING 0x4C07860
+
+#define mmPCIE_AUX_APP_REQ_L1 0x4C07930
+
+#define mmPCIE_AUX_AUX_PM_EN 0x4C07934
+
+#define mmPCIE_AUX_APPS_PM_XMT_PME 0x4C07938
+
+#define mmPCIE_AUX_OUTBAND_PWRUP_CMD 0x4C07940
+
+#define mmPCIE_AUX_PERST 0x4C079B8
+
+#define mmPCIE_AUX_DBI_RO_WR_DISABLE 0x4C079BC
+
+#define mmPCIE_AUX_HOLD_PHY_RST 0x4C079C0
+
+#define mmPCIE_AUX_TLP_INTERNAL_ERR_REP 0x4C079C4
+
+#define mmPCIE_AUX_APP_SRIS_MODE 0x4C079C8
+
+#define mmPCIE_AUX_BUS_MSTR_EN_CLR_INTR 0x4C079CC
+
+#define mmPCIE_AUX_BUS_MSTR_EN_CLR_INTR_MASK 0x4C079D0
+
+#endif /* ASIC_REG_PCIE_AUX_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_dbi_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_dbi_regs.h
new file mode 100644
index 000000000000..2ee79d8e62d0
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_dbi_regs.h
@@ -0,0 +1,421 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PCIE_DBI_REGS_H_
+#define ASIC_REG_PCIE_DBI_REGS_H_
+
+/*
+ *****************************************
+ *   PCIE_DBI
+ *   (Prototype: PCIE_DBI)
+ *****************************************
+ */
+
+#define mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG 0x4C02000
+
+#define mmPCIE_DBI_STATUS_COMMAND_REG 0x4C02004
+
+#define mmPCIE_DBI_CLASS_CODE_REVISION_ID 0x4C02008
+
+#define mmPCIE_DBI_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG 0x4C0200C
+
+#define mmPCIE_DBI_BAR0_REG 0x4C02010
+
+#define mmPCIE_DBI_BAR1_REG 0x4C02014
+
+#define mmPCIE_DBI_BAR2_REG 0x4C02018
+
+#define mmPCIE_DBI_BAR3_REG 0x4C0201C
+
+#define mmPCIE_DBI_BAR4_REG 0x4C02020
+
+#define mmPCIE_DBI_BAR5_REG 0x4C02024
+
+#define mmPCIE_DBI_CARDBUS_CIS_PTR_REG 0x4C02028
+
+#define mmPCIE_DBI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG 0x4C0202C
+
+#define mmPCIE_DBI_EXP_ROM_BASE_ADDR_REG 0x4C02030
+
+#define mmPCIE_DBI_PCI_CAP_PTR_REG 0x4C02034
+
+#define mmPCIE_DBI_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG 0x4C0203C
+
+#define mmPCIE_DBI_CAP_ID_NXT_PTR_REG 0x4C02040
+
+#define mmPCIE_DBI_CON_STATUS_REG 0x4C02044
+
+#define mmPCIE_DBI_PCI_MSI_CAP_ID_NEXT_CTRL_REG 0x4C02050
+
+#define mmPCIE_DBI_MSI_CAP_OFF_04H_REG 0x4C02054
+
+#define mmPCIE_DBI_MSI_CAP_OFF_08H_REG 0x4C02058
+
+#define mmPCIE_DBI_MSI_CAP_OFF_0CH_REG 0x4C0205C
+
+#define mmPCIE_DBI_MSI_CAP_OFF_10H_REG 0x4C02060
+
+#define mmPCIE_DBI_MSI_CAP_OFF_14H_REG 0x4C02064
+
+#define mmPCIE_DBI_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG 0x4C02070
+
+#define mmPCIE_DBI_DEVICE_CAPABILITIES_REG 0x4C02074
+
+#define mmPCIE_DBI_DEVICE_CONTROL_DEVICE_STATUS 0x4C02078
+
+#define mmPCIE_DBI_LINK_CAPABILITIES_REG 0x4C0207C
+
+#define mmPCIE_DBI_LINK_CONTROL_LINK_STATUS_REG 0x4C02080
+
+#define mmPCIE_DBI_DEVICE_CAPABILITIES2_REG 0x4C02094
+
+#define mmPCIE_DBI_DEVICE_CONTROL2_DEVICE_STATUS2_REG 0x4C02098
+
+#define mmPCIE_DBI_LINK_CAPABILITIES2_REG 0x4C0209C
+
+#define mmPCIE_DBI_LINK_CONTROL2_LINK_STATUS2_REG 0x4C020A0
+
+#define mmPCIE_DBI_PCI_MSIX_CAP_ID_NEXT_CTRL_REG 0x4C020B0
+
+#define mmPCIE_DBI_MSIX_TABLE_OFFSET_REG 0x4C020B4
+
+#define mmPCIE_DBI_MSIX_PBA_OFFSET_REG 0x4C020B8
+
+#define mmPCIE_DBI_AER_EXT_CAP_HDR_OFF 0x4C02100
+
+#define mmPCIE_DBI_UNCORR_ERR_STATUS_OFF 0x4C02104
+
+#define mmPCIE_DBI_UNCORR_ERR_MASK_OFF 0x4C02108
+
+#define mmPCIE_DBI_UNCORR_ERR_SEV_OFF 0x4C0210C
+
+#define mmPCIE_DBI_CORR_ERR_STATUS_OFF 0x4C02110
+
+#define mmPCIE_DBI_CORR_ERR_MASK_OFF 0x4C02114
+
+#define mmPCIE_DBI_ADV_ERR_CAP_CTRL_OFF 0x4C02118
+
+#define mmPCIE_DBI_HDR_LOG_0_OFF 0x4C0211C
+
+#define mmPCIE_DBI_HDR_LOG_1_OFF 0x4C02120
+
+#define mmPCIE_DBI_HDR_LOG_2_OFF 0x4C02124
+
+#define mmPCIE_DBI_HDR_LOG_3_OFF 0x4C02128
+
+#define mmPCIE_DBI_TLP_PREFIX_LOG_1_OFF 0x4C02138
+
+#define mmPCIE_DBI_TLP_PREFIX_LOG_2_OFF 0x4C0213C
+
+#define mmPCIE_DBI_TLP_PREFIX_LOG_3_OFF 0x4C02140
+
+#define mmPCIE_DBI_TLP_PREFIX_LOG_4_OFF 0x4C02144
+
+#define mmPCIE_DBI_SPCIE_CAP_HEADER_REG 0x4C02148
+
+#define mmPCIE_DBI_LINK_CONTROL3_REG 0x4C0214C
+
+#define mmPCIE_DBI_LANE_ERR_STATUS_REG 0x4C02150
+
+#define mmPCIE_DBI_SPCIE_CAP_OFF_0CH_REG 0x4C02154
+
+#define mmPCIE_DBI_SPCIE_CAP_OFF_10H_REG 0x4C02158
+
+#define mmPCIE_DBI_SPCIE_CAP_OFF_14H_REG 0x4C0215C
+
+#define mmPCIE_DBI_SPCIE_CAP_OFF_18H_REG 0x4C02160
+
+#define mmPCIE_DBI_SPCIE_CAP_OFF_1CH_REG 0x4C02164
+
+#define mmPCIE_DBI_SPCIE_CAP_OFF_20H_REG 0x4C02168
+
+#define mmPCIE_DBI_SPCIE_CAP_OFF_24H_REG 0x4C0216C
+
+#define mmPCIE_DBI_SPCIE_CAP_OFF_28H_REG 0x4C02170
+
+#define mmPCIE_DBI_PL16G_EXT_CAP_HDR_REG 0x4C02178
+
+#define mmPCIE_DBI_PL16G_CAPABILITY_REG 0x4C0217C
+
+#define mmPCIE_DBI_PL16G_CONTROL_REG 0x4C02180
+
+#define mmPCIE_DBI_PL16G_STATUS_REG 0x4C02184
+
+#define mmPCIE_DBI_PL16G_LC_DPAR_STATUS_REG 0x4C02188
+
+#define mmPCIE_DBI_PL16G_FIRST_RETIMER_DPAR_STATUS_REG 0x4C0218C
+
+#define mmPCIE_DBI_PL16G_SECOND_RETIMER_DPAR_STATUS_REG 0x4C02190
+
+#define mmPCIE_DBI_PL16G_CAP_OFF_20H_REG 0x4C02198
+
+#define mmPCIE_DBI_PL16G_CAP_OFF_24H_REG 0x4C0219C
+
+#define mmPCIE_DBI_PL16G_CAP_OFF_28H_REG 0x4C021A0
+
+#define mmPCIE_DBI_PL16G_CAP_OFF_2CH_REG 0x4C021A4
+
+#define mmPCIE_DBI_MARGIN_EXT_CAP_HDR_REG 0x4C021A8
+
+#define mmPCIE_DBI_MARGIN_PORT_CAPABILITIES_STATUS_REG 0x4C021AC
+
+#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS0_REG 0x4C021B0
+
+#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS1_REG 0x4C021B4
+
+#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS2_REG 0x4C021B8
+
+#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS3_REG 0x4C021BC
+
+#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS4_REG 0x4C021C0
+
+#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS5_REG 0x4C021C4
+
+#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS6_REG 0x4C021C8
+
+#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS7_REG 0x4C021CC
+
+#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS8_REG 0x4C021D0
+
+#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS9_REG 0x4C021D4
+
+#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS10_REG 0x4C021D8
+
+#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS11_REG 0x4C021DC
+
+#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS12_REG 0x4C021E0
+
+#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS13_REG 0x4C021E4
+
+#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS14_REG 0x4C021E8
+
+#define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS15_REG 0x4C021EC
+
+#define mmPCIE_DBI_LTR_CAP_HDR_REG 0x4C021F0
+
+#define mmPCIE_DBI_LTR_LATENCY_REG 0x4C021F4
+
+#define mmPCIE_DBI_RAS_DES_CAP_HEADER_REG 0x4C021F8
+
+#define mmPCIE_DBI_VENDOR_SPECIFIC_HEADER_REG 0x4C021FC
+
+#define mmPCIE_DBI_EVENT_COUNTER_CONTROL_REG 0x4C02200
+
+#define mmPCIE_DBI_EVENT_COUNTER_DATA_REG 0x4C02204
+
+#define mmPCIE_DBI_TIME_BASED_ANALYSIS_CONTROL_REG 0x4C02208
+
+#define mmPCIE_DBI_TIME_BASED_ANALYSIS_DATA_REG 0x4C0220C
+
+#define mmPCIE_DBI_TIME_BASED_ANALYSIS_DATA_63_32_REG 0x4C02210
+
+#define mmPCIE_DBI_EINJ_ENABLE_REG 0x4C02228
+
+#define mmPCIE_DBI_EINJ0_CRC_REG 0x4C0222C
+
+#define mmPCIE_DBI_EINJ1_SEQNUM_REG 0x4C02230
+
+#define mmPCIE_DBI_EINJ2_DLLP_REG 0x4C02234
+
+#define mmPCIE_DBI_EINJ3_SYMBOL_REG 0x4C02238
+
+#define mmPCIE_DBI_EINJ4_FC_REG 0x4C0223C
+
+#define mmPCIE_DBI_EINJ5_SP_TLP_REG 0x4C02240
+
+#define mmPCIE_DBI_EINJ6_COMPARE_POINT_H0_REG 0x4C02244
+
+#define mmPCIE_DBI_EINJ6_COMPARE_POINT_H1_REG 0x4C02248
+
+#define mmPCIE_DBI_EINJ6_COMPARE_POINT_H2_REG 0x4C0224C
+
+#define mmPCIE_DBI_EINJ6_COMPARE_POINT_H3_REG 0x4C02250
+
+#define mmPCIE_DBI_EINJ6_COMPARE_VALUE_H0_REG 0x4C02254
+
+#define mmPCIE_DBI_EINJ6_COMPARE_VALUE_H1_REG 0x4C02258
+
+#define mmPCIE_DBI_EINJ6_COMPARE_VALUE_H2_REG 0x4C0225C
+
+#define mmPCIE_DBI_EINJ6_COMPARE_VALUE_H3_REG 0x4C02260
+
+#define mmPCIE_DBI_EINJ6_CHANGE_POINT_H0_REG 0x4C02264
+
+#define mmPCIE_DBI_EINJ6_CHANGE_POINT_H1_REG 0x4C02268
+
+#define mmPCIE_DBI_EINJ6_CHANGE_POINT_H2_REG 0x4C0226C
+
+#define mmPCIE_DBI_EINJ6_CHANGE_POINT_H3_REG 0x4C02270
+
+#define mmPCIE_DBI_EINJ6_CHANGE_VALUE_H0_REG 0x4C02274
+
+#define mmPCIE_DBI_EINJ6_CHANGE_VALUE_H1_REG 0x4C02278
+
+#define mmPCIE_DBI_EINJ6_CHANGE_VALUE_H2_REG 0x4C0227C
+
+#define mmPCIE_DBI_EINJ6_CHANGE_VALUE_H3_REG 0x4C02280
+
+#define mmPCIE_DBI_EINJ6_TLP_REG 0x4C02284
+
+#define mmPCIE_DBI_SD_CONTROL1_REG 0x4C02298
+
+#define mmPCIE_DBI_SD_CONTROL2_REG 0x4C0229C
+
+#define mmPCIE_DBI_SD_STATUS_L1LANE_REG 0x4C022A8
+
+#define mmPCIE_DBI_SD_STATUS_L1LTSSM_REG 0x4C022AC
+
+#define mmPCIE_DBI_SD_STATUS_PM_REG 0x4C022B0
+
+#define mmPCIE_DBI_SD_STATUS_L2_REG 0x4C022B4
+
+#define mmPCIE_DBI_SD_STATUS_L3FC_REG 0x4C022B8
+
+#define mmPCIE_DBI_SD_STATUS_L3_REG 0x4C022BC
+
+#define mmPCIE_DBI_SD_EQ_CONTROL1_REG 0x4C022C8
+
+#define mmPCIE_DBI_SD_EQ_CONTROL2_REG 0x4C022CC
+
+#define mmPCIE_DBI_SD_EQ_CONTROL3_REG 0x4C022D0
+
+#define mmPCIE_DBI_SD_EQ_STATUS1_REG 0x4C022D8
+
+#define mmPCIE_DBI_SD_EQ_STATUS2_REG 0x4C022DC
+
+#define mmPCIE_DBI_SD_EQ_STATUS3_REG 0x4C022E0
+
+#define mmPCIE_DBI_DATA_LINK_FEATURE_EXT_HDR_OFF 0x4C022F8
+
+#define mmPCIE_DBI_DATA_LINK_FEATURE_CAP_OFF 0x4C022FC
+
+#define mmPCIE_DBI_DATA_LINK_FEATURE_STATUS_OFF 0x4C02300
+
+#define mmPCIE_DBI_ACK_LATENCY_TIMER_OFF 0x4C02700
+
+#define mmPCIE_DBI_VENDOR_SPEC_DLLP_OFF 0x4C02704
+
+#define mmPCIE_DBI_PORT_FORCE_OFF 0x4C02708
+
+#define mmPCIE_DBI_ACK_F_ASPM_CTRL_OFF 0x4C0270C
+
+#define mmPCIE_DBI_PORT_LINK_CTRL_OFF 0x4C02710
+
+#define mmPCIE_DBI_LANE_SKEW_OFF 0x4C02714
+
+#define mmPCIE_DBI_TIMER_CTRL_MAX_FUNC_NUM_OFF 0x4C02718
+
+#define mmPCIE_DBI_SYMBOL_TIMER_FILTER_1_OFF 0x4C0271C
+
+#define mmPCIE_DBI_FILTER_MASK_2_OFF 0x4C02720
+
+#define mmPCIE_DBI_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF 0x4C02724
+
+#define mmPCIE_DBI_PL_DEBUG0_OFF 0x4C02728
+
+#define mmPCIE_DBI_PL_DEBUG1_OFF 0x4C0272C
+
+#define mmPCIE_DBI_TX_P_FC_CREDIT_STATUS_OFF 0x4C02730
+
+#define mmPCIE_DBI_TX_NP_FC_CREDIT_STATUS_OFF 0x4C02734
+
+#define mmPCIE_DBI_TX_CPL_FC_CREDIT_STATUS_OFF 0x4C02738
+
+#define mmPCIE_DBI_QUEUE_STATUS_OFF 0x4C0273C
+
+#define mmPCIE_DBI_VC_TX_ARBI_1_OFF 0x4C02740
+
+#define mmPCIE_DBI_VC_TX_ARBI_2_OFF 0x4C02744
+
+#define mmPCIE_DBI_VC0_P_RX_Q_CTRL_OFF 0x4C02748
+
+#define mmPCIE_DBI_VC0_NP_RX_Q_CTRL_OFF 0x4C0274C
+
+#define mmPCIE_DBI_VC0_CPL_RX_Q_CTRL_OFF 0x4C02750
+
+#define mmPCIE_DBI_GEN2_CTRL_OFF 0x4C0280C
+
+#define mmPCIE_DBI_PHY_STATUS_OFF 0x4C02810
+
+#define mmPCIE_DBI_PHY_CONTROL_OFF 0x4C02814
+
+#define mmPCIE_DBI_TRGT_MAP_CTRL_OFF 0x4C0281C
+
+#define mmPCIE_DBI_CLOCK_GATING_CTRL_OFF 0x4C0288C
+
+#define mmPCIE_DBI_GEN3_RELATED_OFF 0x4C02890
+
+#define mmPCIE_DBI_GEN3_EQ_CONTROL_OFF 0x4C028A8
+
+#define mmPCIE_DBI_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF 0x4C028AC
+
+#define mmPCIE_DBI_ORDER_RULE_CTRL_OFF 0x4C028B4
+
+#define mmPCIE_DBI_PIPE_LOOPBACK_CONTROL_OFF 0x4C028B8
+
+#define mmPCIE_DBI_MISC_CONTROL_1_OFF 0x4C028BC
+
+#define mmPCIE_DBI_MULTI_LANE_CONTROL_OFF 0x4C028C0
+
+#define mmPCIE_DBI_PHY_INTEROP_CTRL_OFF 0x4C028C4
+
+#define mmPCIE_DBI_TRGT_CPL_LUT_DELETE_ENTRY_OFF 0x4C028C8
+
+#define mmPCIE_DBI_LINK_FLUSH_CONTROL_OFF 0x4C028CC
+
+#define mmPCIE_DBI_AMBA_ERROR_RESPONSE_DEFAULT_OFF 0x4C028D0
+
+#define mmPCIE_DBI_AMBA_LINK_TIMEOUT_OFF 0x4C028D4
+
+#define mmPCIE_DBI_AMBA_ORDERING_CTRL_OFF 0x4C028D8
+
+#define mmPCIE_DBI_COHERENCY_CONTROL_1_OFF 0x4C028E0
+
+#define mmPCIE_DBI_COHERENCY_CONTROL_2_OFF 0x4C028E4
+
+#define mmPCIE_DBI_COHERENCY_CONTROL_3_OFF 0x4C028E8
+
+#define mmPCIE_DBI_AXI_MSTR_MSG_ADDR_LOW_OFF 0x4C028F0
+
+#define mmPCIE_DBI_AXI_MSTR_MSG_ADDR_HIGH_OFF 0x4C028F4
+
+#define mmPCIE_DBI_PCIE_VERSION_NUMBER_OFF 0x4C028F8
+
+#define mmPCIE_DBI_PCIE_VERSION_TYPE_OFF 0x4C028FC
+
+#define mmPCIE_DBI_MSIX_ADDRESS_MATCH_LOW_OFF 0x4C02940
+
+#define mmPCIE_DBI_MSIX_ADDRESS_MATCH_HIGH_OFF 0x4C02944
+
+#define mmPCIE_DBI_MSIX_DOORBELL_OFF 0x4C02948
+
+#define mmPCIE_DBI_MSIX_RAM_CTRL_OFF 0x4C0294C
+
+#define mmPCIE_DBI_PL_LTR_LATENCY_OFF 0x4C02B30
+
+#define mmPCIE_DBI_AUX_CLK_FREQ_OFF 0x4C02B40
+
+#define mmPCIE_DBI_POWERDOWN_CTRL_STATUS_OFF 0x4C02B48
+
+#define mmPCIE_DBI_PHY_VIEWPORT_CTLSTS_OFF 0x4C02B70
+
+#define mmPCIE_DBI_PHY_VIEWPORT_DATA_OFF 0x4C02B74
+
+#define mmPCIE_DBI_GEN4_LANE_MARGINING_1_OFF 0x4C02B80
+
+#define mmPCIE_DBI_GEN4_LANE_MARGINING_2_OFF 0x4C02B84
+
+#define mmPCIE_DBI_PIPE_RELATED_OFF 0x4C02B90
+
+#define mmPCIE_DBI_RX_SERIALIZATION_Q_CTRL_OFF 0x4C02C00
+
+#endif /* ASIC_REG_PCIE_DBI_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_dec0_cmd_masks.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_dec0_cmd_masks.h
new file mode 100644
index 000000000000..2b5af010c7a5
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_dec0_cmd_masks.h
@@ -0,0 +1,229 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PCIE_DEC0_CMD_MASKS_H_
+#define ASIC_REG_PCIE_DEC0_CMD_MASKS_H_
+
+/*
+ *****************************************
+ *   PCIE_DEC0_CMD
+ *   (Prototype: VSI_CMD)
+ *****************************************
+ */
+
+/* PCIE_DEC0_CMD_SWREG0 */
+#define PCIE_DEC0_CMD_SWREG0_SW_HW_VERSION_SHIFT 0
+#define PCIE_DEC0_CMD_SWREG0_SW_HW_VERSION_MASK 0xFFFF
+#define PCIE_DEC0_CMD_SWREG0_SW_HW_ID_SHIFT 16
+#define PCIE_DEC0_CMD_SWREG0_SW_HW_ID_MASK 0xFFFF0000
+
+/* PCIE_DEC0_CMD_SWREG1 */
+#define PCIE_DEC0_CMD_SWREG1_SW_HW_BUILDDATE_SHIFT 0
+#define PCIE_DEC0_CMD_SWREG1_SW_HW_BUILDDATE_MASK 0xFFFFFFFF
+
+/* PCIE_DEC0_CMD_SWREG2 */
+#define PCIE_DEC0_CMD_SWREG2_SW_EXT_NORM_INTR_SRC_SHIFT 0
+#define PCIE_DEC0_CMD_SWREG2_SW_EXT_NORM_INTR_SRC_MASK 0xFFFF
+#define PCIE_DEC0_CMD_SWREG2_SW_EXT_ABN_INTR_SRC_SHIFT 16
+#define PCIE_DEC0_CMD_SWREG2_SW_EXT_ABN_INTR_SRC_MASK 0xFFFF0000
+
+/* PCIE_DEC0_CMD_SWREG3 */
+#define PCIE_DEC0_CMD_SWREG3_SW_EXE_CMDBUF_COUNT_SHIFT 0
+#define PCIE_DEC0_CMD_SWREG3_SW_EXE_CMDBUF_COUNT_MASK 0xFFFFFFFF
+
+/* PCIE_DEC0_CMD_SWREG4 */
+#define PCIE_DEC0_CMD_SWREG4_SW_CMD_EXE_LSB_SHIFT 0
+#define PCIE_DEC0_CMD_SWREG4_SW_CMD_EXE_LSB_MASK 0xFFFFFFFF
+
+/* PCIE_DEC0_CMD_SWREG5 */
+#define PCIE_DEC0_CMD_SWREG5_SW_CMD_EXE_MSB_SHIFT 0
+#define PCIE_DEC0_CMD_SWREG5_SW_CMD_EXE_MSB_MASK 0xFFFFFFFF
+
+/* PCIE_DEC0_CMD_SWREG6 */
+#define PCIE_DEC0_CMD_SWREG6_SW_AXI_TOTALARLEN_SHIFT 0
+#define PCIE_DEC0_CMD_SWREG6_SW_AXI_TOTALARLEN_MASK 0xFFFFFFFF
+
+/* PCIE_DEC0_CMD_SWREG7 */
+#define PCIE_DEC0_CMD_SWREG7_SW_AXI_TOTALR_SHIFT 0
+#define PCIE_DEC0_CMD_SWREG7_SW_AXI_TOTALR_MASK 0xFFFFFFFF
+
+/* PCIE_DEC0_CMD_SWREG8 */
+#define PCIE_DEC0_CMD_SWREG8_SW_AXI_TOTALAR_SHIFT 0
+#define PCIE_DEC0_CMD_SWREG8_SW_AXI_TOTALAR_MASK 0xFFFFFFFF
+
+/* PCIE_DEC0_CMD_SWREG9 */
+#define PCIE_DEC0_CMD_SWREG9_SW_AXI_TOTALRLAST_SHIFT 0
+#define PCIE_DEC0_CMD_SWREG9_SW_AXI_TOTALRLAST_MASK 0xFFFFFFFF
+
+/* PCIE_DEC0_CMD_SWREG10 */
+#define PCIE_DEC0_CMD_SWREG10_SW_AXI_TOTALAWLEN_SHIFT 0
+#define PCIE_DEC0_CMD_SWREG10_SW_AXI_TOTALAWLEN_MASK 0xFFFFFFFF
+
+/* PCIE_DEC0_CMD_SWREG11 */
+#define PCIE_DEC0_CMD_SWREG11_SW_AXI_TOTALW_SHIFT 0
+#define PCIE_DEC0_CMD_SWREG11_SW_AXI_TOTALW_MASK 0xFFFFFFFF
+
+/* PCIE_DEC0_CMD_SWREG12 */
+#define PCIE_DEC0_CMD_SWREG12_SW_AXI_TOTALAW_SHIFT 0
+#define PCIE_DEC0_CMD_SWREG12_SW_AXI_TOTALAW_MASK 0xFFFFFFFF
+
+/* PCIE_DEC0_CMD_SWREG13 */
+#define PCIE_DEC0_CMD_SWREG13_SW_AXI_TOTALWLAST_SHIFT 0
+#define PCIE_DEC0_CMD_SWREG13_SW_AXI_TOTALWLAST_MASK 0xFFFFFFFF
+
+/* PCIE_DEC0_CMD_SWREG14 */
+#define PCIE_DEC0_CMD_SWREG14_SW_AXI_TOTALB_SHIFT 0
+#define PCIE_DEC0_CMD_SWREG14_SW_AXI_TOTALB_MASK 0xFFFFFFFF
+
+/* PCIE_DEC0_CMD_SWREG15 */
+#define PCIE_DEC0_CMD_SWREG15_SW_WORK_STATE_SHIFT 0
+#define PCIE_DEC0_CMD_SWREG15_SW_WORK_STATE_MASK 0x7
+#define PCIE_DEC0_CMD_SWREG15_RSV_SHIFT 3
+#define PCIE_DEC0_CMD_SWREG15_RSV_MASK 0x3FFFF8
+#define PCIE_DEC0_CMD_SWREG15_SW_AXI_BREADY_SHIFT 22
+#define PCIE_DEC0_CMD_SWREG15_SW_AXI_BREADY_MASK 0x400000
+#define PCIE_DEC0_CMD_SWREG15_SW_AXI_BVALID_SHIFT 23
+#define PCIE_DEC0_CMD_SWREG15_SW_AXI_BVALID_MASK 0x800000
+#define PCIE_DEC0_CMD_SWREG15_SW_AXI_WREADY_SHIFT 24
+#define PCIE_DEC0_CMD_SWREG15_SW_AXI_WREADY_MASK 0x1000000
+#define PCIE_DEC0_CMD_SWREG15_SW_AXI_WVALID_SHIFT 25
+#define PCIE_DEC0_CMD_SWREG15_SW_AXI_WVALID_MASK 0x2000000
+#define PCIE_DEC0_CMD_SWREG15_SW_AXI_AWREADY_SHIFT 26
+#define PCIE_DEC0_CMD_SWREG15_SW_AXI_AWREADY_MASK 0x4000000
+#define PCIE_DEC0_CMD_SWREG15_SW_AXI_AWVALID_SHIFT 27
+#define PCIE_DEC0_CMD_SWREG15_SW_AXI_AWVALID_MASK 0x8000000
+#define PCIE_DEC0_CMD_SWREG15_SW_AXI_RREADY_SHIFT 28
+#define PCIE_DEC0_CMD_SWREG15_SW_AXI_RREADY_MASK 0x10000000
+#define PCIE_DEC0_CMD_SWREG15_SW_AXI_RVALID_SHIFT 29
+#define PCIE_DEC0_CMD_SWREG15_SW_AXI_RVALID_MASK 0x20000000
+#define PCIE_DEC0_CMD_SWREG15_SW_AXI_ARREADY_SHIFT 30
+#define PCIE_DEC0_CMD_SWREG15_SW_AXI_ARREADY_MASK 0x40000000
+#define PCIE_DEC0_CMD_SWREG15_SW_AXI_ARVALID_SHIFT 31
+#define PCIE_DEC0_CMD_SWREG15_SW_AXI_ARVALID_MASK 0x80000000
+
+/* PCIE_DEC0_CMD_SWREG16 */
+#define PCIE_DEC0_CMD_SWREG16_SW_START_TRIGGER_SHIFT 0
+#define PCIE_DEC0_CMD_SWREG16_SW_START_TRIGGER_MASK 0x1
+#define PCIE_DEC0_CMD_SWREG16_SW_RESET_ALL_SHIFT 1
+#define PCIE_DEC0_CMD_SWREG16_SW_RESET_ALL_MASK 0x2
+#define PCIE_DEC0_CMD_SWREG16_SW_RESET_CORE_SHIFT 2
+#define PCIE_DEC0_CMD_SWREG16_SW_RESET_CORE_MASK 0x4
+#define PCIE_DEC0_CMD_SWREG16_SW_ABORT_MODE_SHIFT 3
+#define PCIE_DEC0_CMD_SWREG16_SW_ABORT_MODE_MASK 0x8
+#define PCIE_DEC0_CMD_SWREG16_SW_CORE_CLK_GATE_DISABLE_SHIFT 4
+#define PCIE_DEC0_CMD_SWREG16_SW_CORE_CLK_GATE_DISABLE_MASK 0x10
+#define PCIE_DEC0_CMD_SWREG16_SW_MASTER_OUT_CLK_GATE_DISABLE_SHIFT 5
+#define PCIE_DEC0_CMD_SWREG16_SW_MASTER_OUT_CLK_GATE_DISABLE_MASK 0x20
+#define PCIE_DEC0_CMD_SWREG16_SW_AXI_CLK_GATE_DISABLE_SHIFT 6
+#define PCIE_DEC0_CMD_SWREG16_SW_AXI_CLK_GATE_DISABLE_MASK 0x40
+#define PCIE_DEC0_CMD_SWREG16_RSV_SHIFT 7
+#define PCIE_DEC0_CMD_SWREG16_RSV_MASK 0xFFFFFF80
+
+/* PCIE_DEC0_CMD_SWREG17 */
+#define PCIE_DEC0_CMD_SWREG17_SW_IRQ_ENDCMD_SHIFT 0
+#define PCIE_DEC0_CMD_SWREG17_SW_IRQ_ENDCMD_MASK 0x1
+#define PCIE_DEC0_CMD_SWREG17_SW_IRQ_BUSERR_SHIFT 1
+#define PCIE_DEC0_CMD_SWREG17_SW_IRQ_BUSERR_MASK 0x2
+#define PCIE_DEC0_CMD_SWREG17_SW_IRQ_TIMEOUT_SHIFT 2
+#define PCIE_DEC0_CMD_SWREG17_SW_IRQ_TIMEOUT_MASK 0x4
+#define PCIE_DEC0_CMD_SWREG17_SW_IRQ_CMDERR_SHIFT 3
+#define PCIE_DEC0_CMD_SWREG17_SW_IRQ_CMDERR_MASK 0x8
+#define PCIE_DEC0_CMD_SWREG17_SW_IRQ_ABORT_SHIFT 4
+#define PCIE_DEC0_CMD_SWREG17_SW_IRQ_ABORT_MASK 0x10
+#define PCIE_DEC0_CMD_SWREG17_RSV_1_SHIFT 5
+#define PCIE_DEC0_CMD_SWREG17_RSV_1_MASK 0x20
+#define PCIE_DEC0_CMD_SWREG17_SW_IRQ_JMP_SHIFT 6
+#define PCIE_DEC0_CMD_SWREG17_SW_IRQ_JMP_MASK 0x40
+#define PCIE_DEC0_CMD_SWREG17_RSV_SHIFT 7
+#define PCIE_DEC0_CMD_SWREG17_RSV_MASK 0xFFFFFF80
+
+/* PCIE_DEC0_CMD_SWREG18 */
+#define PCIE_DEC0_CMD_SWREG18_SW_IRQ_ENDCMD_EN_SHIFT 0
+#define PCIE_DEC0_CMD_SWREG18_SW_IRQ_ENDCMD_EN_MASK 0x1
+#define PCIE_DEC0_CMD_SWREG18_SW_IRQ_BUSERR_EN_SHIFT 1
+#define PCIE_DEC0_CMD_SWREG18_SW_IRQ_BUSERR_EN_MASK 0x2
+#define PCIE_DEC0_CMD_SWREG18_SW_IRQ_TIMEOUT_EN_SHIFT 2
+#define PCIE_DEC0_CMD_SWREG18_SW_IRQ_TIMEOUT_EN_MASK 0x4
+#define PCIE_DEC0_CMD_SWREG18_SW_IRQ_CMDERR_EN_SHIFT 3
+#define PCIE_DEC0_CMD_SWREG18_SW_IRQ_CMDERR_EN_MASK 0x8
+#define PCIE_DEC0_CMD_SWREG18_SW_IRQ_ABORT_EN_SHIFT 4
+#define PCIE_DEC0_CMD_SWREG18_SW_IRQ_ABORT_EN_MASK 0x10
+#define PCIE_DEC0_CMD_SWREG18_RSV_1_SHIFT 5
+#define PCIE_DEC0_CMD_SWREG18_RSV_1_MASK 0x20
+#define PCIE_DEC0_CMD_SWREG18_SW_IRQ_JMP_EN_SHIFT 6
+#define PCIE_DEC0_CMD_SWREG18_SW_IRQ_JMP_EN_MASK 0x40
+#define PCIE_DEC0_CMD_SWREG18_RSV_SHIFT 7
+#define PCIE_DEC0_CMD_SWREG18_RSV_MASK 0xFFFFFF80
+
+/* PCIE_DEC0_CMD_SWREG19 */
+#define PCIE_DEC0_CMD_SWREG19_SW_TIMEOUT_CYCLES_SHIFT 0
+#define PCIE_DEC0_CMD_SWREG19_SW_TIMEOUT_CYCLES_MASK 0x7FFFFFFF
+#define PCIE_DEC0_CMD_SWREG19_SW_TIMEOUT_ENABLE_SHIFT 31
+#define PCIE_DEC0_CMD_SWREG19_SW_TIMEOUT_ENABLE_MASK 0x80000000
+
+/* PCIE_DEC0_CMD_SWREG20 */
+#define PCIE_DEC0_CMD_SWREG20_SW_CMDBUF_EXE_ADDR_LSB_SHIFT 0
+#define PCIE_DEC0_CMD_SWREG20_SW_CMDBUF_EXE_ADDR_LSB_MASK 0xFFFFFFFF
+
+/* PCIE_DEC0_CMD_SWREG21 */
+#define PCIE_DEC0_CMD_SWREG21_SW_CMDBUF_EXE_ADDR_MSB_SHIFT 0
+#define PCIE_DEC0_CMD_SWREG21_SW_CMDBUF_EXE_ADDR_MSB_MASK 0xFFFFFFFF
+
+/* PCIE_DEC0_CMD_SWREG22 */
+#define PCIE_DEC0_CMD_SWREG22_SW_CMDBUF_EXE_LENGTH_SHIFT 0
+#define PCIE_DEC0_CMD_SWREG22_SW_CMDBUF_EXE_LENGTH_MASK 0xFFFF
+#define PCIE_DEC0_CMD_SWREG22_RSV_SHIFT 16
+#define PCIE_DEC0_CMD_SWREG22_RSV_MASK 0xFFFF0000
+
+/* PCIE_DEC0_CMD_SWREG23 */
+#define PCIE_DEC0_CMD_SWREG23_SW_AXI_ID_WR_SHIFT 0
+#define PCIE_DEC0_CMD_SWREG23_SW_AXI_ID_WR_MASK 0xFF
+#define PCIE_DEC0_CMD_SWREG23_SW_AXI_ID_RD_SHIFT 8
+#define PCIE_DEC0_CMD_SWREG23_SW_AXI_ID_RD_MASK 0xFF00
+#define PCIE_DEC0_CMD_SWREG23_SW_MAX_BURST_LEN_SHIFT 16
+#define PCIE_DEC0_CMD_SWREG23_SW_MAX_BURST_LEN_MASK 0xFF0000
+#define PCIE_DEC0_CMD_SWREG23_RSV_SHIFT 24
+#define PCIE_DEC0_CMD_SWREG23_RSV_MASK 0xF000000
+#define PCIE_DEC0_CMD_SWREG23_SW_CMD_SWAP_SHIFT 28
+#define PCIE_DEC0_CMD_SWREG23_SW_CMD_SWAP_MASK 0xF0000000
+
+/* PCIE_DEC0_CMD_SWREG24 */
+#define PCIE_DEC0_CMD_SWREG24_SW_RDY_CMDBUF_COUNT_SHIFT 0
+#define PCIE_DEC0_CMD_SWREG24_SW_RDY_CMDBUF_COUNT_MASK 0xFFFFFFFF
+
+/* PCIE_DEC0_CMD_SWREG25 */
+#define PCIE_DEC0_CMD_SWREG25_SW_EXT_NORM_INTR_GATE_SHIFT 0
+#define PCIE_DEC0_CMD_SWREG25_SW_EXT_NORM_INTR_GATE_MASK 0xFFFF
+#define PCIE_DEC0_CMD_SWREG25_SW_EXT_ABN_INTR_GATE_SHIFT 16
+#define PCIE_DEC0_CMD_SWREG25_SW_EXT_ABN_INTR_GATE_MASK 0xFFFF0000
+
+/* PCIE_DEC0_CMD_SWREG26 */
+#define PCIE_DEC0_CMD_SWREG26_SW_CMDBUF_EXE_ID_SHIFT 0
+#define PCIE_DEC0_CMD_SWREG26_SW_CMDBUF_EXE_ID_MASK 0xFFFFFFFF
+
+/* PCIE_DEC0_CMD_SWREG64 */
+#define PCIE_DEC0_CMD_SWREG64_SW_DUMMY0_SHIFT 0
+#define PCIE_DEC0_CMD_SWREG64_SW_DUMMY0_MASK 0xFFFFFFFF
+
+/* PCIE_DEC0_CMD_SWREG65 */
+#define PCIE_DEC0_CMD_SWREG65_SW_DUMMY1_SHIFT 0
+#define PCIE_DEC0_CMD_SWREG65_SW_DUMMY1_MASK 0xFFFFFFFF
+
+/* PCIE_DEC0_CMD_SWREG66 */
+#define PCIE_DEC0_CMD_SWREG66_SW_DUMMY2_SHIFT 0
+#define PCIE_DEC0_CMD_SWREG66_SW_DUMMY2_MASK 0xFFFFFFFF
+
+/* PCIE_DEC0_CMD_SWREG67 */
+#define PCIE_DEC0_CMD_SWREG67_SW_DUMMY3_SHIFT 0
+#define PCIE_DEC0_CMD_SWREG67_SW_DUMMY3_MASK 0xFFFFFFFF
+
+#endif /* ASIC_REG_PCIE_DEC0_CMD_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_dec0_cmd_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_dec0_cmd_regs.h
new file mode 100644
index 000000000000..dc7d3f6a4b50
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_dec0_cmd_regs.h
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PCIE_DEC0_CMD_REGS_H_
+#define ASIC_REG_PCIE_DEC0_CMD_REGS_H_
+
+/*
+ *****************************************
+ *   PCIE_DEC0_CMD
+ *   (Prototype: VSI_CMD)
+ *****************************************
+ */
+
+#define mmPCIE_DEC0_CMD_SWREG0 0x4F00000
+
+#define mmPCIE_DEC0_CMD_SWREG1 0x4F00004
+
+#define mmPCIE_DEC0_CMD_SWREG2 0x4F00008
+
+#define mmPCIE_DEC0_CMD_SWREG3 0x4F0000C
+
+#define mmPCIE_DEC0_CMD_SWREG4 0x4F00010
+
+#define mmPCIE_DEC0_CMD_SWREG5 0x4F00014
+
+#define mmPCIE_DEC0_CMD_SWREG6 0x4F00018
+
+#define mmPCIE_DEC0_CMD_SWREG7 0x4F0001C
+
+#define mmPCIE_DEC0_CMD_SWREG8 0x4F00020
+
+#define mmPCIE_DEC0_CMD_SWREG9 0x4F00024
+
+#define mmPCIE_DEC0_CMD_SWREG10 0x4F00028
+
+#define mmPCIE_DEC0_CMD_SWREG11 0x4F0002C
+
+#define mmPCIE_DEC0_CMD_SWREG12 0x4F00030
+
+#define mmPCIE_DEC0_CMD_SWREG13 0x4F00034
+
+#define mmPCIE_DEC0_CMD_SWREG14 0x4F00038
+
+#define mmPCIE_DEC0_CMD_SWREG15 0x4F0003C
+
+#define mmPCIE_DEC0_CMD_SWREG16 0x4F00040
+
+#define mmPCIE_DEC0_CMD_SWREG17 0x4F00044
+
+#define mmPCIE_DEC0_CMD_SWREG18 0x4F00048
+
+#define mmPCIE_DEC0_CMD_SWREG19 0x4F0004C
+
+#define mmPCIE_DEC0_CMD_SWREG20 0x4F00050
+
+#define mmPCIE_DEC0_CMD_SWREG21 0x4F00054
+
+#define mmPCIE_DEC0_CMD_SWREG22 0x4F00058
+
+#define mmPCIE_DEC0_CMD_SWREG23 0x4F0005C
+
+#define mmPCIE_DEC0_CMD_SWREG24 0x4F00060
+
+#define mmPCIE_DEC0_CMD_SWREG25 0x4F00064
+
+#define mmPCIE_DEC0_CMD_SWREG26 0x4F00068
+
+#define mmPCIE_DEC0_CMD_SWREG64 0x4F00100
+
+#define mmPCIE_DEC0_CMD_SWREG65 0x4F00104
+
+#define mmPCIE_DEC0_CMD_SWREG66 0x4F00108
+
+#define mmPCIE_DEC0_CMD_SWREG67 0x4F0010C
+
+#endif /* ASIC_REG_PCIE_DEC0_CMD_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_dec_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_dec_regs.h
new file mode 100644
index 000000000000..242c6525bd71
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_dec_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_REGS_H_
+#define ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_REGS_H_
+
+/*
+ *****************************************
+ *   PCIE_VDEC0_BRDG_CTRL_AXUSER_DEC
+ *   (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_ASID 0x4F03C00
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_MMU_BP 0x4F03C04
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_STRONG_ORDER 0x4F03C08
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_NO_SNOOP 0x4F03C0C
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_WR_REDUCTION 0x4F03C10
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_RD_ATOMIC 0x4F03C14
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_QOS 0x4F03C18
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_RSVD 0x4F03C1C
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_EMEM_CPAGE 0x4F03C20
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_CORE 0x4F03C24
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_E2E_COORD 0x4F03C28
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_WR_OVRD_LO 0x4F03C30
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_WR_OVRD_HI 0x4F03C34
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_RD_OVRD_LO 0x4F03C38
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_RD_OVRD_HI 0x4F03C3C
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_LB_COORD 0x4F03C40
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_LB_LOCK 0x4F03C44
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_LB_RSVD 0x4F03C48
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_LB_OVRD 0x4F03C4C
+
+#endif /* ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h
new file mode 100644
index 000000000000..98d035463561
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_REGS_H_
+#define ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_REGS_H_
+
+/*
+ *****************************************
+ *   PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM
+ *   (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_ASID 0x4F03B00
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_MMU_BP 0x4F03B04
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_STRONG_ORDER 0x4F03B08
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_NO_SNOOP 0x4F03B0C
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_WR_REDUCTION 0x4F03B10
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_RD_ATOMIC 0x4F03B14
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_QOS 0x4F03B18
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_RSVD 0x4F03B1C
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_EMEM_CPAGE 0x4F03B20
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_CORE 0x4F03B24
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_E2E_COORD 0x4F03B28
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_WR_OVRD_LO 0x4F03B30
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_WR_OVRD_HI 0x4F03B34
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_RD_OVRD_LO 0x4F03B38
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_HB_RD_OVRD_HI 0x4F03B3C
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_LB_COORD 0x4F03B40
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_LB_LOCK 0x4F03B44
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_LB_RSVD 0x4F03B48
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_LB_OVRD 0x4F03B4C
+
+#endif /* ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h
new file mode 100644
index 000000000000..33ef37619417
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_REGS_H_
+#define ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_REGS_H_
+
+/*
+ *****************************************
+ *   PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C
+ *   (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_ASID 0x4F03900
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_MMU_BP 0x4F03904
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_STRONG_ORDER 0x4F03908
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_NO_SNOOP 0x4F0390C
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_WR_REDUCTION 0x4F03910
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_RD_ATOMIC 0x4F03914
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_QOS 0x4F03918
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_RSVD 0x4F0391C
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_EMEM_CPAGE 0x4F03920
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_CORE 0x4F03924
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_E2E_COORD 0x4F03928
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_WR_OVRD_LO 0x4F03930
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_WR_OVRD_HI 0x4F03934
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_RD_OVRD_LO 0x4F03938
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_HB_RD_OVRD_HI 0x4F0393C
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_LB_COORD 0x4F03940
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_LB_LOCK 0x4F03944
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_LB_RSVD 0x4F03948
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_LB_OVRD 0x4F0394C
+
+#endif /* ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h
new file mode 100644
index 000000000000..c4587d5d6406
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_REGS_H_
+#define ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_REGS_H_
+
+/*
+ *****************************************
+ *   PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM
+ *   (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_ASID 0x4F03A00
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_MMU_BP 0x4F03A04
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_STRONG_ORDER 0x4F03A08
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_NO_SNOOP 0x4F03A0C
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_WR_REDUCTION 0x4F03A10
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_RD_ATOMIC 0x4F03A14
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_QOS 0x4F03A18
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_RSVD 0x4F03A1C
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_EMEM_CPAGE 0x4F03A20
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_CORE 0x4F03A24
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_E2E_COORD 0x4F03A28
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_WR_OVRD_LO 0x4F03A30
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_WR_OVRD_HI 0x4F03A34
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_RD_OVRD_LO 0x4F03A38
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_HB_RD_OVRD_HI 0x4F03A3C
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_LB_COORD 0x4F03A40
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_LB_LOCK 0x4F03A44
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_LB_RSVD 0x4F03A48
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_LB_OVRD 0x4F03A4C
+
+#endif /* ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h
new file mode 100644
index 000000000000..35349ad375d0
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_REGS_H_
+#define ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_REGS_H_
+
+/*
+ *****************************************
+ *   PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD
+ *   (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_ASID 0x4F03800
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_MMU_BP 0x4F03804
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_STRONG_ORDER 0x4F03808
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_NO_SNOOP 0x4F0380C
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_WR_REDUCTION 0x4F03810
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_RD_ATOMIC 0x4F03814
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_QOS 0x4F03818
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_RSVD 0x4F0381C
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_EMEM_CPAGE 0x4F03820
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_CORE 0x4F03824
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_E2E_COORD 0x4F03828
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_WR_OVRD_LO 0x4F03830
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_WR_OVRD_HI 0x4F03834
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_RD_OVRD_LO 0x4F03838
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_HB_RD_OVRD_HI 0x4F0383C
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_LB_COORD 0x4F03840
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_LB_LOCK 0x4F03844
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_LB_RSVD 0x4F03848
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_LB_OVRD 0x4F0384C
+
+#endif /* ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_masks.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_masks.h
new file mode 100644
index 000000000000..7a96aebf08b3
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_masks.h
@@ -0,0 +1,579 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PCIE_VDEC0_BRDG_CTRL_MASKS_H_
+#define ASIC_REG_PCIE_VDEC0_BRDG_CTRL_MASKS_H_
+
+/*
+ *****************************************
+ *   PCIE_VDEC0_BRDG_CTRL
+ *   (Prototype: VDEC_BRDG_CTRL)
+ *****************************************
+ */
+
+/* PCIE_VDEC0_BRDG_CTRL_CGM_DISABLE */
+#define PCIE_VDEC0_BRDG_CTRL_CGM_DISABLE_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_CGM_DISABLE_VAL_MASK 0x1
+
+/* PCIE_VDEC0_BRDG_CTRL_IDLE_MASK */
+#define PCIE_VDEC0_BRDG_CTRL_IDLE_MASK_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_IDLE_MASK_VAL_MASK 0x7
+
+/* PCIE_VDEC0_BRDG_CTRL_APB_CGM_CNT */
+#define PCIE_VDEC0_BRDG_CTRL_APB_CGM_CNT_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_APB_CGM_CNT_VAL_MASK 0xFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT */
+#define PCIE_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT_VAL_MASK 0xFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_GRACEFUL */
+#define PCIE_VDEC0_BRDG_CTRL_GRACEFUL_STOP_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_GRACEFUL_STOP_MASK 0x1
+#define PCIE_VDEC0_BRDG_CTRL_GRACEFUL_PEND_SHIFT 4
+#define PCIE_VDEC0_BRDG_CTRL_GRACEFUL_PEND_MASK 0x10
+
+/* PCIE_VDEC0_BRDG_CTRL_IDLE_CGM_CNT */
+#define PCIE_VDEC0_BRDG_CTRL_IDLE_CGM_CNT_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_IDLE_CGM_CNT_VAL_MASK 0xFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR */
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_VCD_HBW_SEI_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_VCD_HBW_SEI_MASK 0x1
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_L2C_HBW_SEI_SHIFT 1
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_L2C_HBW_SEI_MASK 0x2
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_NRM_HBW_SEI_SHIFT 2
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_NRM_HBW_SEI_MASK 0x4
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_ABNRM_HBW_SEI_SHIFT 3
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_ABNRM_HBW_SEI_MASK 0x8
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_VCD_LBW_SEI_SHIFT 4
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_VCD_LBW_SEI_MASK 0x10
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_L2C_LBW_SEI_SHIFT 5
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_L2C_LBW_SEI_MASK 0x20
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_NRM_LBW_SEI_SHIFT 6
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_NRM_LBW_SEI_MASK 0x40
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_ABNRM_LBW_SEI_SHIFT 7
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_ABNRM_LBW_SEI_MASK 0x80
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_VCD_LBW_SEI_SHIFT 8
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_VCD_LBW_SEI_MASK 0x100
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_L2C_LBW_SEI_SHIFT 9
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_L2C_LBW_SEI_MASK 0x200
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_NRM_LBW_SEI_SHIFT 10
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_NRM_LBW_SEI_MASK 0x400
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_ABNRM_LBW_SEI_SHIFT 11
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_ABNRM_LBW_SEI_MASK 0x800
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_DEC_SEI_SHIFT 12
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_DEC_SEI_MASK 0x1000
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_DEC_APB_SEI_SHIFT 13
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_DEC_APB_SEI_MASK 0x2000
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_TRC_APB_SEI_SHIFT 14
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_TRC_APB_SEI_MASK 0x4000
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_MSTR_IF_SEI_SHIFT 15
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_MSTR_IF_SEI_MASK 0x8000
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_AXI_SPLIT_BRESP_ERR_SEI_SHIFT 16
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_AXI_SPLIT_BRESP_ERR_SEI_MASK 0x10000
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_HBW_AXI_WR_VIOL_SEI_SHIFT 17
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_HBW_AXI_WR_VIOL_SEI_MASK 0x20000
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_HBW_AXI_RD_VIOL_SEI_SHIFT 18
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_HBW_AXI_RD_VIOL_SEI_MASK 0x40000
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_AXI_WR_VIOL_SEI_SHIFT 19
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_AXI_WR_VIOL_SEI_MASK 0x80000
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_AXI_RD_VIOL_SEI_SHIFT 20
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_AXI_RD_VIOL_SEI_MASK 0x100000
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_VCD_SPI_SHIFT 21
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_VCD_SPI_MASK 0x200000
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_L2C_SPI_SHIFT 22
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_L2C_SPI_MASK 0x400000
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_NRM_SPI_SHIFT 23
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_NRM_SPI_MASK 0x800000
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_ABNRM_SPI_SHIFT 24
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_ABNRM_SPI_MASK 0x1000000
+
+/* PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE */
+#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWLEN_GT_31_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWLEN_GT_31_MASK 0x1
+#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWLOCK_VIOL_SHIFT 1
+#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWLOCK_VIOL_MASK 0x2
+#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWBURST_VIOL_SHIFT 2
+#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWBURST_VIOL_MASK 0x4
+#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWADDR_SIZE_ALIGN_VIOL_SHIFT 3
+#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWADDR_SIZE_ALIGN_VIOL_MASK 0x8
+#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWSIZE_VIOL_SHIFT 4
+#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWSIZE_VIOL_MASK 0x10
+#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARLEN_GT_31_SHIFT 5
+#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARLEN_GT_31_MASK 0x20
+#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARLOCK_VIOL_SHIFT 6
+#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARLOCK_VIOL_MASK 0x40
+#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARBURST_VIOL_SHIFT 7
+#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARBURST_VIOL_MASK 0x80
+#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARADDR_SIZE_ALIGN_VIOL_SHIFT 8
+#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARADDR_SIZE_ALIGN_VIOL_MASK 0x100
+#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARSIZE_VIOL_SHIFT 9
+#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARSIZE_VIOL_MASK 0x200
+
+/* PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE */
+#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_READ_ACCESS_VIOL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_READ_ACCESS_VIOL_MASK 0x1
+#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWLOCK_VIOL_SHIFT 1
+#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWLOCK_VIOL_MASK 0x2
+#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWADDR_ALIGN_VIOL_SHIFT 2
+#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWADDR_ALIGN_VIOL_MASK 0x4
+#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWSIZE_VIOL_SHIFT 3
+#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWSIZE_VIOL_MASK 0x8
+#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWLEN_VIOL_SHIFT 4
+#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWLEN_VIOL_MASK 0x10
+#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_WSTRB_VIOL_SHIFT 5
+#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_WSTRB_VIOL_MASK 0x20
+
+/* PCIE_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM */
+#define PCIE_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_HBW_AW_VIOL_CLR_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_HBW_AW_VIOL_CLR_MASK 0x1
+#define PCIE_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_HBW_AR_VIOL_CLR_SHIFT 1
+#define PCIE_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_HBW_AR_VIOL_CLR_MASK 0x2
+#define PCIE_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_LBW_AW_VIOL_CLR_SHIFT 2
+#define PCIE_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_LBW_AW_VIOL_CLR_MASK 0x4
+
+/* PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MASK */
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MASK_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MASK_VAL_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_MASK */
+#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_MASK_MASK_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_MASK_MASK_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_MASK */
+#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_MASK_MASK_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_MASK_MASK_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_VCD_GIC_INTR_MASK */
+#define PCIE_VDEC0_BRDG_CTRL_VCD_GIC_INTR_MASK_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_VCD_GIC_INTR_MASK_VAL_MASK 0x1
+
+/* PCIE_VDEC0_BRDG_CTRL_L2C_GIC_INTR_MASK */
+#define PCIE_VDEC0_BRDG_CTRL_L2C_GIC_INTR_MASK_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_L2C_GIC_INTR_MASK_VAL_MASK 0x1
+
+/* PCIE_VDEC0_BRDG_CTRL_NRM_GIC_INTR_MASK */
+#define PCIE_VDEC0_BRDG_CTRL_NRM_GIC_INTR_MASK_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_NRM_GIC_INTR_MASK_VAL_MASK 0x1
+
+/* PCIE_VDEC0_BRDG_CTRL_ABNRM_GIC_INTR_MASK */
+#define PCIE_VDEC0_BRDG_CTRL_ABNRM_GIC_INTR_MASK_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_ABNRM_GIC_INTR_MASK_VAL_MASK 0x1
+
+/* PCIE_VDEC0_BRDG_CTRL_DEC_HBW_AWPROT */
+#define PCIE_VDEC0_BRDG_CTRL_DEC_HBW_AWPROT_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_DEC_HBW_AWPROT_VAL_MASK 0x7
+
+/* PCIE_VDEC0_BRDG_CTRL_DEC_HBW_ARPROT */
+#define PCIE_VDEC0_BRDG_CTRL_DEC_HBW_ARPROT_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_DEC_HBW_ARPROT_VAL_MASK 0x7
+
+/* PCIE_VDEC0_BRDG_CTRL_DEC_LBW_AWPROT */
+#define PCIE_VDEC0_BRDG_CTRL_DEC_LBW_AWPROT_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_DEC_LBW_AWPROT_VAL_MASK 0x7
+
+/* PCIE_VDEC0_BRDG_CTRL_DEC_LBW_ARPROT */
+#define PCIE_VDEC0_BRDG_CTRL_DEC_LBW_ARPROT_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_DEC_LBW_ARPROT_VAL_MASK 0x7
+
+/* PCIE_VDEC0_BRDG_CTRL_DEC_LBW_SLV_AWPROT */
+#define PCIE_VDEC0_BRDG_CTRL_DEC_LBW_SLV_AWPROT_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_DEC_LBW_SLV_AWPROT_VAL_MASK 0x7
+
+/* PCIE_VDEC0_BRDG_CTRL_DEC_LBW_SLV_ARPROT */
+#define PCIE_VDEC0_BRDG_CTRL_DEC_LBW_SLV_ARPROT_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_DEC_LBW_SLV_ARPROT_VAL_MASK 0x7
+
+/* PCIE_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE */
+#define PCIE_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_HBW_LEGAL_AWSIZE_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_HBW_LEGAL_AWSIZE_MASK 0x7
+#define PCIE_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_HBW_LEGAL_ARSIZE_SHIFT 3
+#define PCIE_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_HBW_LEGAL_ARSIZE_MASK 0x38
+#define PCIE_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_LBW_LEGAL_AWSIZE_SHIFT 6
+#define PCIE_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_LBW_LEGAL_AWSIZE_MASK 0x1C0
+
+/* PCIE_VDEC0_BRDG_CTRL_ARC_MSG_MASK */
+#define PCIE_VDEC0_BRDG_CTRL_ARC_MSG_MASK_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_ARC_MSG_MASK_VAL_MASK 0x1
+
+/* PCIE_VDEC0_BRDG_CTRL_ARC_START_LBW_WDATA */
+#define PCIE_VDEC0_BRDG_CTRL_ARC_START_LBW_WDATA_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_ARC_START_LBW_WDATA_VAL_MASK 0xFF
+
+/* PCIE_VDEC0_BRDG_CTRL_ARC_FINISH_LBW_WDATA */
+#define PCIE_VDEC0_BRDG_CTRL_ARC_FINISH_LBW_WDATA_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_ARC_FINISH_LBW_WDATA_VAL_MASK 0xFF
+
+/* PCIE_VDEC0_BRDG_CTRL_HWEVENT_TRACE_SEL */
+#define PCIE_VDEC0_BRDG_CTRL_HWEVENT_TRACE_SEL_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_HWEVENT_TRACE_SEL_VAL_MASK 0x7
+
+/* PCIE_VDEC0_BRDG_CTRL_HWEVENT_TRACE_ADDR */
+#define PCIE_VDEC0_BRDG_CTRL_HWEVENT_TRACE_ADDR_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_HWEVENT_TRACE_ADDR_VAL_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_L */
+#define PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_L_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_L_VAL_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_H */
+#define PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_H_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_H_VAL_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_L */
+#define PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_L_IND_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_L_IND_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_H */
+#define PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_H_IND_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_H_IND_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_L */
+#define PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_L_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_L_VAL_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_H */
+#define PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_H_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_H_VAL_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_L */
+#define PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_L_IND_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_L_IND_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_H */
+#define PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_H_IND_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_H_IND_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_STAT_CNTR_EN */
+#define PCIE_VDEC0_BRDG_CTRL_STAT_CNTR_EN_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_STAT_CNTR_EN_VAL_MASK 0x1
+
+/* PCIE_VDEC0_BRDG_CTRL_VCD_INTR_MASK */
+#define PCIE_VDEC0_BRDG_CTRL_VCD_INTR_MASK_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_VCD_INTR_MASK_VAL_MASK 0x1
+
+/* PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK */
+#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_APB_WR_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_APB_WR_MASK 0x1
+#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_APB_RD_SHIFT 1
+#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_APB_RD_MASK 0x2
+#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_LBW_SHIFT 2
+#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_LBW_MASK 0x4
+
+/* PCIE_VDEC0_BRDG_CTRL_VCD_WAIT_CNTR */
+#define PCIE_VDEC0_BRDG_CTRL_VCD_WAIT_CNTR_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_VCD_WAIT_CNTR_VAL_MASK 0xFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_WAIT_CNTR */
+#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_WAIT_CNTR_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_STAT_VCD_WAIT_CNTR */
+#define PCIE_VDEC0_BRDG_CTRL_STAT_VCD_WAIT_CNTR_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_STAT_VCD_WAIT_CNTR_VAL_MASK 0xFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_STAT_VCD_MSIX_WAIT_CNTR */
+#define PCIE_VDEC0_BRDG_CTRL_STAT_VCD_MSIX_WAIT_CNTR_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_STAT_VCD_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_VCD_SWREG1_ADDR */
+#define PCIE_VDEC0_BRDG_CTRL_VCD_SWREG1_ADDR_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_VCD_SWREG1_ADDR_VAL_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_VCD_APB_WR_ADDR */
+#define PCIE_VDEC0_BRDG_CTRL_VCD_APB_WR_ADDR_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_VCD_APB_WR_ADDR_VAL_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_VCD_APB_WR_DATA */
+#define PCIE_VDEC0_BRDG_CTRL_VCD_APB_WR_DATA_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_VCD_APB_WR_DATA_VAL_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWPROT */
+#define PCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWPROT_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWPROT_VAL_MASK 0x7
+
+/* PCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_L */
+#define PCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_L_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_L_VAL_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_H */
+#define PCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_H_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_H_VAL_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWPROT */
+#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWPROT_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWPROT_VAL_MASK 0x7
+
+/* PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWADDR */
+#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWADDR_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWADDR_VAL_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_WDATA */
+#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_WDATA_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_WDATA_VAL_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_L2C_INTR_MASK */
+#define PCIE_VDEC0_BRDG_CTRL_L2C_INTR_MASK_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_L2C_INTR_MASK_VAL_MASK 0x1
+
+/* PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK */
+#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_APB_WR_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_APB_WR_MASK 0x1
+#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_APB_RD_SHIFT 1
+#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_APB_RD_MASK 0x2
+#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_LBW_SHIFT 2
+#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_LBW_MASK 0x4
+
+/* PCIE_VDEC0_BRDG_CTRL_L2C_WAIT_CNTR */
+#define PCIE_VDEC0_BRDG_CTRL_L2C_WAIT_CNTR_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_L2C_WAIT_CNTR_VAL_MASK 0xFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_WAIT_CNTR */
+#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_WAIT_CNTR_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_STAT_L2C_WAIT_CNTR */
+#define PCIE_VDEC0_BRDG_CTRL_STAT_L2C_WAIT_CNTR_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_STAT_L2C_WAIT_CNTR_VAL_MASK 0xFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_STAT_L2C_MSIX_WAIT_CNTR */
+#define PCIE_VDEC0_BRDG_CTRL_STAT_L2C_MSIX_WAIT_CNTR_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_STAT_L2C_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_L2C_SWREG1_ADDR */
+#define PCIE_VDEC0_BRDG_CTRL_L2C_SWREG1_ADDR_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_L2C_SWREG1_ADDR_VAL_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_L2C_APB_WR_ADDR */
+#define PCIE_VDEC0_BRDG_CTRL_L2C_APB_WR_ADDR_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_L2C_APB_WR_ADDR_VAL_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_L2C_APB_WR_DATA */
+#define PCIE_VDEC0_BRDG_CTRL_L2C_APB_WR_DATA_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_L2C_APB_WR_DATA_VAL_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWPROT */
+#define PCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWPROT_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWPROT_VAL_MASK 0x7
+
+/* PCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_L */
+#define PCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_L_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_L_VAL_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_H */
+#define PCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_H_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_H_VAL_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWPROT */
+#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWPROT_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWPROT_VAL_MASK 0x7
+
+/* PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWADDR */
+#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWADDR_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWADDR_VAL_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_WDATA */
+#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_WDATA_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_WDATA_VAL_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_NRM_INTR_MASK */
+#define PCIE_VDEC0_BRDG_CTRL_NRM_INTR_MASK_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_NRM_INTR_MASK_VAL_MASK 0x1
+
+/* PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK */
+#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_APB_WR_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_APB_WR_MASK 0x1
+#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_APB_RD_SHIFT 1
+#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_APB_RD_MASK 0x2
+#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_LBW_SHIFT 2
+#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_LBW_MASK 0x4
+
+/* PCIE_VDEC0_BRDG_CTRL_NRM_WAIT_CNTR */
+#define PCIE_VDEC0_BRDG_CTRL_NRM_WAIT_CNTR_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_NRM_WAIT_CNTR_VAL_MASK 0xFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_WAIT_CNTR */
+#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_WAIT_CNTR_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_STAT_NRM_WAIT_CNTR */
+#define PCIE_VDEC0_BRDG_CTRL_STAT_NRM_WAIT_CNTR_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_STAT_NRM_WAIT_CNTR_VAL_MASK 0xFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_STAT_NRM_MSIX_WAIT_CNTR */
+#define PCIE_VDEC0_BRDG_CTRL_STAT_NRM_MSIX_WAIT_CNTR_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_STAT_NRM_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_NRM_SWREG1_ADDR */
+#define PCIE_VDEC0_BRDG_CTRL_NRM_SWREG1_ADDR_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_NRM_SWREG1_ADDR_VAL_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_NRM_APB_WR_ADDR */
+#define PCIE_VDEC0_BRDG_CTRL_NRM_APB_WR_ADDR_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_NRM_APB_WR_ADDR_VAL_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_NRM_APB_WR_DATA */
+#define PCIE_VDEC0_BRDG_CTRL_NRM_APB_WR_DATA_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_NRM_APB_WR_DATA_VAL_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWPROT */
+#define PCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWPROT_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWPROT_VAL_MASK 0x7
+
+/* PCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_L */
+#define PCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_L_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_L_VAL_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_H */
+#define PCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_H_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_H_VAL_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWPROT */
+#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWPROT_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWPROT_VAL_MASK 0x7
+
+/* PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR */
+#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR_VAL_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA */
+#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA_VAL_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_ABNRM_INTR_MASK */
+#define PCIE_VDEC0_BRDG_CTRL_ABNRM_INTR_MASK_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_ABNRM_INTR_MASK_VAL_MASK 0x1
+
+/* PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK */
+#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_APB_WR_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_APB_WR_MASK 0x1
+#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_APB_RD_SHIFT 1
+#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_APB_RD_MASK 0x2
+#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_LBW_SHIFT 2
+#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_LBW_MASK 0x4
+
+/* PCIE_VDEC0_BRDG_CTRL_ABNRM_WAIT_CNTR */
+#define PCIE_VDEC0_BRDG_CTRL_ABNRM_WAIT_CNTR_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_ABNRM_WAIT_CNTR_VAL_MASK 0xFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_WAIT_CNTR */
+#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_WAIT_CNTR_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_STAT_ABNRM_WAIT_CNTR */
+#define PCIE_VDEC0_BRDG_CTRL_STAT_ABNRM_WAIT_CNTR_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_STAT_ABNRM_WAIT_CNTR_VAL_MASK 0xFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_STAT_ABNRM_MSIX_WAIT_CNTR */
+#define PCIE_VDEC0_BRDG_CTRL_STAT_ABNRM_MSIX_WAIT_CNTR_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_STAT_ABNRM_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_ABNRM_SWREG1_ADDR */
+#define PCIE_VDEC0_BRDG_CTRL_ABNRM_SWREG1_ADDR_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_ABNRM_SWREG1_ADDR_VAL_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_ABNRM_APB_WR_ADDR */
+#define PCIE_VDEC0_BRDG_CTRL_ABNRM_APB_WR_ADDR_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_ABNRM_APB_WR_ADDR_VAL_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_ABNRM_APB_WR_DATA */
+#define PCIE_VDEC0_BRDG_CTRL_ABNRM_APB_WR_DATA_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_ABNRM_APB_WR_DATA_VAL_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWPROT */
+#define PCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWPROT_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWPROT_VAL_MASK 0x7
+
+/* PCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_L */
+#define PCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_L_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_L_VAL_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_H */
+#define PCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_H_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_H_VAL_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWPROT */
+#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWPROT_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWPROT_VAL_MASK 0x7
+
+/* PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR */
+#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR_VAL_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA */
+#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA_VAL_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_BRESP_ERR_ID */
+#define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_BRESP_ERR_ID_ID_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_BRESP_ERR_ID_ID_MASK 0xFF
+
+/* PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG */
+#define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_FORCE_RESP_OK_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_FORCE_RESP_OK_MASK 0x1
+#define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_FORCE_WR_BUF_SHIFT 1
+#define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_FORCE_WR_BUF_MASK 0x2
+#define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_NUM_RD_OS_SHIFT 8
+#define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_NUM_RD_OS_MASK 0xFF00
+#define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_NUM_WR_OS_SHIFT 16
+#define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_NUM_WR_OS_MASK 0xFF0000
+
+/* PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_NO_WR_INFLIGHT */
+#define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_NO_WR_INFLIGHT_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_NO_WR_INFLIGHT_VAL_MASK 0x1
+
+/* PCIE_VDEC0_BRDG_CTRL_HWEVENT_MASK */
+#define PCIE_VDEC0_BRDG_CTRL_HWEVENT_MASK_MASK_SHIFT 1
+#define PCIE_VDEC0_BRDG_CTRL_HWEVENT_MASK_MASK_MASK 0x2
+
+/* PCIE_VDEC0_BRDG_CTRL_HWEVENT_CNTXT */
+#define PCIE_VDEC0_BRDG_CTRL_HWEVENT_CNTXT_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_HWEVENT_CNTXT_VAL_MASK 0xFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_LBW_SLV_TERM_ERR_RESP */
+#define PCIE_VDEC0_BRDG_CTRL_LBW_SLV_TERM_ERR_RESP_ERR_RESP_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_LBW_SLV_TERM_ERR_RESP_ERR_RESP_MASK 0x3
+
+/* PCIE_VDEC0_BRDG_CTRL_LBW_MSTR_TERM_ERR_RESP */
+#define PCIE_VDEC0_BRDG_CTRL_LBW_MSTR_TERM_ERR_RESP_ERR_RESP_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_LBW_MSTR_TERM_ERR_RESP_ERR_RESP_MASK 0x3
+
+/* PCIE_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP */
+#define PCIE_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP_WR_ERR_RESP_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP_WR_ERR_RESP_MASK 0x3
+#define PCIE_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP_RD_ERR_RESP_SHIFT 2
+#define PCIE_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP_RD_ERR_RESP_MASK 0xC
+
+/* PCIE_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS */
+#define PCIE_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS_AW_STA_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS_AW_STA_MASK 0x1
+#define PCIE_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS_AR_STA_SHIFT 1
+#define PCIE_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS_AR_STA_MASK 0x2
+
+/* PCIE_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_L */
+#define PCIE_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_L_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_L_VAL_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_H */
+#define PCIE_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_H_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_H_VAL_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_L */
+#define PCIE_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_L_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_L_VAL_MASK 0xFFFFFFFF
+
+/* PCIE_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_H */
+#define PCIE_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_H_VAL_SHIFT 0
+#define PCIE_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_H_VAL_MASK 0xFFFFFFFF
+
+#endif /* ASIC_REG_PCIE_VDEC0_BRDG_CTRL_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_regs.h
new file mode 100644
index 000000000000..c7badd212f2b
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_regs.h
@@ -0,0 +1,245 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PCIE_VDEC0_BRDG_CTRL_REGS_H_
+#define ASIC_REG_PCIE_VDEC0_BRDG_CTRL_REGS_H_
+
+/*
+ *****************************************
+ *   PCIE_VDEC0_BRDG_CTRL
+ *   (Prototype: VDEC_BRDG_CTRL)
+ *****************************************
+ */
+
+#define mmPCIE_VDEC0_BRDG_CTRL_CGM_DISABLE 0x4F03100
+
+#define mmPCIE_VDEC0_BRDG_CTRL_IDLE_MASK 0x4F03104
+
+#define mmPCIE_VDEC0_BRDG_CTRL_APB_CGM_CNT 0x4F03108
+
+#define mmPCIE_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT 0x4F0310C
+
+#define mmPCIE_VDEC0_BRDG_CTRL_GRACEFUL 0x4F03110
+
+#define mmPCIE_VDEC0_BRDG_CTRL_IDLE_CGM_CNT 0x4F03114
+
+#define mmPCIE_VDEC0_BRDG_CTRL_CAUSE_INTR 0x4F03120
+
+#define mmPCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE 0x4F03124
+
+#define mmPCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE 0x4F03128
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM 0x4F0312C
+
+#define mmPCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MASK 0x4F03130
+
+#define mmPCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_MASK 0x4F03134
+
+#define mmPCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_MASK 0x4F03138
+
+#define mmPCIE_VDEC0_BRDG_CTRL_VCD_GIC_INTR_MASK 0x4F03160
+
+#define mmPCIE_VDEC0_BRDG_CTRL_L2C_GIC_INTR_MASK 0x4F03170
+
+#define mmPCIE_VDEC0_BRDG_CTRL_NRM_GIC_INTR_MASK 0x4F03180
+
+#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_GIC_INTR_MASK 0x4F03190
+
+#define mmPCIE_VDEC0_BRDG_CTRL_DEC_HBW_AWPROT 0x4F031A0
+
+#define mmPCIE_VDEC0_BRDG_CTRL_DEC_HBW_ARPROT 0x4F031A4
+
+#define mmPCIE_VDEC0_BRDG_CTRL_DEC_LBW_AWPROT 0x4F031B0
+
+#define mmPCIE_VDEC0_BRDG_CTRL_DEC_LBW_ARPROT 0x4F031B4
+
+#define mmPCIE_VDEC0_BRDG_CTRL_DEC_LBW_SLV_AWPROT 0x4F031C0
+
+#define mmPCIE_VDEC0_BRDG_CTRL_DEC_LBW_SLV_ARPROT 0x4F031C4
+
+#define mmPCIE_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE 0x4F031D0
+
+#define mmPCIE_VDEC0_BRDG_CTRL_ARC_MSG_MASK 0x4F03200
+
+#define mmPCIE_VDEC0_BRDG_CTRL_ARC_START_LBW_WDATA 0x4F03230
+
+#define mmPCIE_VDEC0_BRDG_CTRL_ARC_FINISH_LBW_WDATA 0x4F03260
+
+#define mmPCIE_VDEC0_BRDG_CTRL_HWEVENT_TRACE_SEL 0x4F03270
+
+#define mmPCIE_VDEC0_BRDG_CTRL_HWEVENT_TRACE_ADDR 0x4F03280
+
+#define mmPCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_L 0x4F03290
+
+#define mmPCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_H 0x4F03294
+
+#define mmPCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_L 0x4F032A0
+
+#define mmPCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_H 0x4F032A4
+
+#define mmPCIE_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_L 0x4F032B0
+
+#define mmPCIE_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_H 0x4F032B4
+
+#define mmPCIE_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_L 0x4F032C0
+
+#define mmPCIE_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_H 0x4F032C4
+
+#define mmPCIE_VDEC0_BRDG_CTRL_STAT_CNTR_EN 0x4F032D0
+
+#define mmPCIE_VDEC0_BRDG_CTRL_VCD_INTR_MASK 0x4F03300
+
+#define mmPCIE_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK 0x4F03310
+
+#define mmPCIE_VDEC0_BRDG_CTRL_VCD_WAIT_CNTR 0x4F03320
+
+#define mmPCIE_VDEC0_BRDG_CTRL_VCD_MSIX_WAIT_CNTR 0x4F03330
+
+#define mmPCIE_VDEC0_BRDG_CTRL_STAT_VCD_WAIT_CNTR 0x4F03334
+
+#define mmPCIE_VDEC0_BRDG_CTRL_STAT_VCD_MSIX_WAIT_CNTR 0x4F03338
+
+#define mmPCIE_VDEC0_BRDG_CTRL_VCD_SWREG1_ADDR 0x4F03340
+
+#define mmPCIE_VDEC0_BRDG_CTRL_VCD_APB_WR_ADDR 0x4F03350
+
+#define mmPCIE_VDEC0_BRDG_CTRL_VCD_APB_WR_DATA 0x4F03360
+
+#define mmPCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWPROT 0x4F03380
+
+#define mmPCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_L 0x4F03390
+
+#define mmPCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_H 0x4F03394
+
+#define mmPCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWPROT 0x4F033C0
+
+#define mmPCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWADDR 0x4F033D0
+
+#define mmPCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_WDATA 0x4F033E0
+
+#define mmPCIE_VDEC0_BRDG_CTRL_L2C_INTR_MASK 0x4F03400
+
+#define mmPCIE_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK 0x4F03410
+
+#define mmPCIE_VDEC0_BRDG_CTRL_L2C_WAIT_CNTR 0x4F03420
+
+#define mmPCIE_VDEC0_BRDG_CTRL_L2C_MSIX_WAIT_CNTR 0x4F03430
+
+#define mmPCIE_VDEC0_BRDG_CTRL_STAT_L2C_WAIT_CNTR 0x4F03434
+
+#define mmPCIE_VDEC0_BRDG_CTRL_STAT_L2C_MSIX_WAIT_CNTR 0x4F03438
+
+#define mmPCIE_VDEC0_BRDG_CTRL_L2C_SWREG1_ADDR 0x4F03440
+
+#define mmPCIE_VDEC0_BRDG_CTRL_L2C_APB_WR_ADDR 0x4F03450
+
+#define mmPCIE_VDEC0_BRDG_CTRL_L2C_APB_WR_DATA 0x4F03460
+
+#define mmPCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWPROT 0x4F03480
+
+#define mmPCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_L 0x4F03490
+
+#define mmPCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_H 0x4F03494
+
+#define mmPCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWPROT 0x4F034C0
+
+#define mmPCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWADDR 0x4F034D0
+
+#define mmPCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_WDATA 0x4F034E0
+
+#define mmPCIE_VDEC0_BRDG_CTRL_NRM_INTR_MASK 0x4F03500
+
+#define mmPCIE_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK 0x4F03510
+
+#define mmPCIE_VDEC0_BRDG_CTRL_NRM_WAIT_CNTR 0x4F03520
+
+#define mmPCIE_VDEC0_BRDG_CTRL_NRM_MSIX_WAIT_CNTR 0x4F03530
+
+#define mmPCIE_VDEC0_BRDG_CTRL_STAT_NRM_WAIT_CNTR 0x4F03534
+
+#define mmPCIE_VDEC0_BRDG_CTRL_STAT_NRM_MSIX_WAIT_CNTR 0x4F03538
+
+#define mmPCIE_VDEC0_BRDG_CTRL_NRM_SWREG1_ADDR 0x4F03540
+
+#define mmPCIE_VDEC0_BRDG_CTRL_NRM_APB_WR_ADDR 0x4F03550
+
+#define mmPCIE_VDEC0_BRDG_CTRL_NRM_APB_WR_DATA 0x4F03560
+
+#define mmPCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWPROT 0x4F03580
+
+#define mmPCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_L 0x4F03590
+
+#define mmPCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_H 0x4F03594
+
+#define mmPCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWPROT 0x4F035C0
+
+#define mmPCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR 0x4F035D0
+
+#define mmPCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA 0x4F035E0
+
+#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_INTR_MASK 0x4F03600
+
+#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK 0x4F03610
+
+#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_WAIT_CNTR 0x4F03620
+
+#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_WAIT_CNTR 0x4F03630
+
+#define mmPCIE_VDEC0_BRDG_CTRL_STAT_ABNRM_WAIT_CNTR 0x4F03634
+
+#define mmPCIE_VDEC0_BRDG_CTRL_STAT_ABNRM_MSIX_WAIT_CNTR 0x4F03638
+
+#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_SWREG1_ADDR 0x4F03640
+
+#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_APB_WR_ADDR 0x4F03650
+
+#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_APB_WR_DATA 0x4F03660
+
+#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWPROT 0x4F03680
+
+#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_L 0x4F03690
+
+#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_H 0x4F03694
+
+#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWPROT 0x4F036C0
+
+#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR 0x4F036D0
+
+#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA 0x4F036E0
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_BRESP_ERR_ID 0x4F03700
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG 0x4F03704
+
+#define mmPCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_NO_WR_INFLIGHT 0x4F03708
+
+#define mmPCIE_VDEC0_BRDG_CTRL_HWEVENT_MASK 0x4F0370C
+
+#define mmPCIE_VDEC0_BRDG_CTRL_HWEVENT_CNTXT 0x4F03714
+
+#define mmPCIE_VDEC0_BRDG_CTRL_LBW_SLV_TERM_ERR_RESP 0x4F03718
+
+#define mmPCIE_VDEC0_BRDG_CTRL_LBW_MSTR_TERM_ERR_RESP 0x4F0371C
+
+#define mmPCIE_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP 0x4F03720
+
+#define mmPCIE_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS 0x4F03724
+
+#define mmPCIE_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_L 0x4F03728
+
+#define mmPCIE_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_H 0x4F0372C
+
+#define mmPCIE_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_L 0x4F03730
+
+#define mmPCIE_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_H 0x4F03734
+
+#endif /* ASIC_REG_PCIE_VDEC0_BRDG_CTRL_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_ctrl_special_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_ctrl_special_regs.h
new file mode 100644
index 000000000000..491b0cd935af
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_ctrl_special_regs.h
@@ -0,0 +1,185 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PCIE_VDEC0_CTRL_SPECIAL_REGS_H_
+#define ASIC_REG_PCIE_VDEC0_CTRL_SPECIAL_REGS_H_
+
+/*
+ *****************************************
+ *   PCIE_VDEC0_CTRL_SPECIAL
+ *   (Prototype: SPECIAL_REGS)
+ *****************************************
+ */
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_0 0x4F04E80
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_1 0x4F04E84
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_2 0x4F04E88
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_3 0x4F04E8C
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_4 0x4F04E90
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_5 0x4F04E94
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_6 0x4F04E98
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_7 0x4F04E9C
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_8 0x4F04EA0
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_9 0x4F04EA4
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_10 0x4F04EA8
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_11 0x4F04EAC
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_12 0x4F04EB0
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_13 0x4F04EB4
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_14 0x4F04EB8
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_15 0x4F04EBC
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_16 0x4F04EC0
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_17 0x4F04EC4
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_18 0x4F04EC8
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_19 0x4F04ECC
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_20 0x4F04ED0
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_21 0x4F04ED4
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_22 0x4F04ED8
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_23 0x4F04EDC
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_24 0x4F04EE0
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_25 0x4F04EE4
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_26 0x4F04EE8
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_27 0x4F04EEC
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_28 0x4F04EF0
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_29 0x4F04EF4
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_30 0x4F04EF8
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_31 0x4F04EFC
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_GW_DATA 0x4F04F00
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_GW_REQ 0x4F04F04
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_NUMOF 0x4F04F0C
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_ECC_SEL 0x4F04F10
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_ECC_CTL 0x4F04F14
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_ECC_ERR_MASK 0x4F04F18
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_ECC_GLBL_ERR_MASK 0x4F04F1C
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_ECC_ERR_STS 0x4F04F20
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_ECC_ERR_ADDR 0x4F04F24
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_RM 0x4F04F28
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_ERR_MASK 0x4F04F40
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_ERR_ADDR 0x4F04F44
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_ERR_CAUSE 0x4F04F48
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SPARE_0 0x4F04F60
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SPARE_1 0x4F04F64
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SPARE_2 0x4F04F68
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SPARE_3 0x4F04F6C
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_0 0x4F04F80
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_1 0x4F04F84
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_2 0x4F04F88
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_3 0x4F04F8C
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_4 0x4F04F90
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_5 0x4F04F94
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_6 0x4F04F98
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_7 0x4F04F9C
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_8 0x4F04FA0
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_9 0x4F04FA4
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_10 0x4F04FA8
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_11 0x4F04FAC
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_12 0x4F04FB0
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_13 0x4F04FB4
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_14 0x4F04FB8
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_15 0x4F04FBC
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_16 0x4F04FC0
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_17 0x4F04FC4
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_18 0x4F04FC8
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_19 0x4F04FCC
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_20 0x4F04FD0
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_21 0x4F04FD4
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_22 0x4F04FD8
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_23 0x4F04FDC
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_24 0x4F04FE0
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_25 0x4F04FE4
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_26 0x4F04FE8
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_27 0x4F04FEC
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_28 0x4F04FF0
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_29 0x4F04FF4
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_30 0x4F04FF8
+
+#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_31 0x4F04FFC
+
+#endif /* ASIC_REG_PCIE_VDEC0_CTRL_SPECIAL_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_wrap_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_wrap_regs.h
new file mode 100644
index 000000000000..a09422f2f281
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_wrap_regs.h
@@ -0,0 +1,601 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PCIE_WRAP_REGS_H_
+#define ASIC_REG_PCIE_WRAP_REGS_H_
+
+/*
+ *****************************************
+ *   PCIE_WRAP
+ *   (Prototype: PCIE_WRAP)
+ *****************************************
+ */
+
+#define mmPCIE_WRAP_INTR_GEN_MASK_MIN_ADDR_0 0x4C01000
+
+#define mmPCIE_WRAP_INTR_GEN_MASK_MIN_ADDR_1 0x4C01004
+
+#define mmPCIE_WRAP_INTR_GEN_MASK_MAX_ADDR_0 0x4C01008
+
+#define mmPCIE_WRAP_INTR_GEN_MASK_MAX_ADDR_1 0x4C0100C
+
+#define mmPCIE_WRAP_INTR_GEN_MASK_TIMER 0x4C01010
+
+#define mmPCIE_WRAP_INTR_GEN_MASK_CTRL 0x4C01014
+
+#define mmPCIE_WRAP_MSIX_DOORBELL_OFF_ADDR 0x4C01018
+
+#define mmPCIE_WRAP_MSIX_MASK_CTRL 0x4C0101C
+
+#define mmPCIE_WRAP_PHY_FW_SRAM_ADDR_L_0 0x4C01020
+
+#define mmPCIE_WRAP_PHY_FW_SRAM_ADDR_L_1 0x4C01024
+
+#define mmPCIE_WRAP_PHY_FW_SRAM_ADDR_H_0 0x4C01028
+
+#define mmPCIE_WRAP_PHY_FW_SRAM_ADDR_H_1 0x4C0102C
+
+#define mmPCIE_WRAP_PHY_FW_SRAM_CFG_ADDR 0x4C01030
+
+#define mmPCIE_WRAP_MSIX_GW 0x4C01034
+
+#define mmPCIE_WRAP_MSIX_GW_VEC 0x4C01038
+
+#define mmPCIE_WRAP_MSIX_GW_INTR 0x4C0103C
+
+#define mmPCIE_WRAP_MSIX_GW_TABLE_0 0x4C01040
+
+#define mmPCIE_WRAP_MSIX_GW_TABLE_1 0x4C01044
+
+#define mmPCIE_WRAP_MSIX_GW_TABLE_2 0x4C01048
+
+#define mmPCIE_WRAP_MSIX_GW_TABLE_3 0x4C0104C
+
+#define mmPCIE_WRAP_MSIX_GW_TABLE_4 0x4C01050
+
+#define mmPCIE_WRAP_MSIX_GW_TABLE_5 0x4C01054
+
+#define mmPCIE_WRAP_MSIX_GW_TABLE_6 0x4C01058
+
+#define mmPCIE_WRAP_MSIX_GW_TABLE_7 0x4C0105C
+
+#define mmPCIE_WRAP_MSIX_GW_TABLE_8 0x4C01060
+
+#define mmPCIE_WRAP_MSIX_GW_TABLE_9 0x4C01064
+
+#define mmPCIE_WRAP_MSIX_GW_TABLE_10 0x4C01068
+
+#define mmPCIE_WRAP_MSIX_GW_TABLE_11 0x4C0106C
+
+#define mmPCIE_WRAP_MSIX_GW_TABLE_12 0x4C01070
+
+#define mmPCIE_WRAP_MSIX_GW_TABLE_13 0x4C01074
+
+#define mmPCIE_WRAP_MSIX_GW_TABLE_14 0x4C01078
+
+#define mmPCIE_WRAP_MSIX_GW_TABLE_15 0x4C0107C
+
+#define mmPCIE_WRAP_VUART_RX_0 0x4C01100
+
+#define mmPCIE_WRAP_VUART_RX_1 0x4C01104
+
+#define mmPCIE_WRAP_VUART_RX_2 0x4C01108
+
+#define mmPCIE_WRAP_VUART_TX_0 0x4C0110C
+
+#define mmPCIE_WRAP_VUART_TX_1 0x4C01110
+
+#define mmPCIE_WRAP_VUART_TX_2 0x4C01114
+
+#define mmPCIE_WRAP_MSI_GW_BLOCK 0x4C01120
+
+#define mmPCIE_WRAP_PHY_FW_FSM_SIZE 0x4C0120C
+
+#define mmPCIE_WRAP_HOST_ACCESS_TERMINATION 0x4C01210
+
+#define mmPCIE_WRAP_ILLEGAL_LBW_REQ_CTRL 0x4C01214
+
+#define mmPCIE_WRAP_ILLEGAL_LBW_REQ_ADDR_0 0x4C01218
+
+#define mmPCIE_WRAP_ILLEGAL_LBW_REQ_ADDR_1 0x4C0121C
+
+#define mmPCIE_WRAP_ILLEGAL_LBW_REQ_INTR 0x4C01220
+
+#define mmPCIE_WRAP_OUTBOUND_ADDR_LSB 0x4C01224
+
+#define mmPCIE_WRAP_LBW_WSTRB_OVRD 0x4C01228
+
+#define mmPCIE_WRAP_LBW_GW_ADDR_0 0x4C01304
+
+#define mmPCIE_WRAP_LBW_GW_ADDR_1 0x4C01308
+
+#define mmPCIE_WRAP_LBW_GW_ADDR_2 0x4C0130C
+
+#define mmPCIE_WRAP_LBW_GW_ADDR_3 0x4C01310
+
+#define mmPCIE_WRAP_LBW_GW_ADDR_4 0x4C01314
+
+#define mmPCIE_WRAP_LBW_GW_ADDR_5 0x4C01318
+
+#define mmPCIE_WRAP_LBW_GW_ADDR_6 0x4C0131C
+
+#define mmPCIE_WRAP_LBW_GW_ADDR_7 0x4C01320
+
+#define mmPCIE_WRAP_LBW_GW_DATA_0 0x4C01324
+
+#define mmPCIE_WRAP_LBW_GW_DATA_1 0x4C01328
+
+#define mmPCIE_WRAP_LBW_GW_DATA_2 0x4C0132C
+
+#define mmPCIE_WRAP_LBW_GW_DATA_3 0x4C01330
+
+#define mmPCIE_WRAP_LBW_GW_DATA_4 0x4C01334
+
+#define mmPCIE_WRAP_LBW_GW_DATA_5 0x4C01338
+
+#define mmPCIE_WRAP_LBW_GW_DATA_6 0x4C0133C
+
+#define mmPCIE_WRAP_LBW_GW_DATA_7 0x4C01340
+
+#define mmPCIE_WRAP_LBW_GW_GO_0 0x4C01344
+
+#define mmPCIE_WRAP_LBW_GW_GO_1 0x4C01348
+
+#define mmPCIE_WRAP_LBW_GW_GO_2 0x4C0134C
+
+#define mmPCIE_WRAP_LBW_GW_GO_3 0x4C01350
+
+#define mmPCIE_WRAP_LBW_GW_GO_4 0x4C01354
+
+#define mmPCIE_WRAP_LBW_GW_GO_5 0x4C01358
+
+#define mmPCIE_WRAP_LBW_GW_GO_6 0x4C0135C
+
+#define mmPCIE_WRAP_LBW_GW_GO_7 0x4C01360
+
+#define mmPCIE_WRAP_LBW_GW_STATUS_0 0x4C01364
+
+#define mmPCIE_WRAP_LBW_GW_STATUS_1 0x4C01368
+
+#define mmPCIE_WRAP_LBW_GW_STATUS_2 0x4C0136C
+
+#define mmPCIE_WRAP_LBW_GW_STATUS_3 0x4C01370
+
+#define mmPCIE_WRAP_LBW_GW_STATUS_4 0x4C01374
+
+#define mmPCIE_WRAP_LBW_GW_STATUS_5 0x4C01378
+
+#define mmPCIE_WRAP_LBW_GW_STATUS_6 0x4C0137C
+
+#define mmPCIE_WRAP_LBW_GW_STATUS_7 0x4C01380
+
+#define mmPCIE_WRAP_OUTBOUND_OUTSTANDING 0x4C013F4
+
+#define mmPCIE_WRAP_MASK_REQ 0x4C01404
+
+#define mmPCIE_WRAP_ONE_IN_FLIGHT 0x4C01408
+
+#define mmPCIE_WRAP_IND_AWPROT 0x4C0140C
+
+#define mmPCIE_WRAP_SLV_AWMISC_INFO 0x4C01500
+
+#define mmPCIE_WRAP_SLV_AWMISC_INFO_HDR_34DW_0 0x4C01504
+
+#define mmPCIE_WRAP_SLV_AWMISC_INFO_HDR_34DW_1 0x4C01508
+
+#define mmPCIE_WRAP_SLV_AWMISC_INFO_P_TAG 0x4C0150C
+
+#define mmPCIE_WRAP_SLV_AWMISC_INFO_ATU_BYPAS 0x4C01510
+
+#define mmPCIE_WRAP_SLV_AWMISC_INFO_FUNC_NUM 0x4C01514
+
+#define mmPCIE_WRAP_SLV_AWMISC_INFO_VFUNC_ACT 0x4C01518
+
+#define mmPCIE_WRAP_SLV_AWMISC_INFO_VFUNC_NUM 0x4C0151C
+
+#define mmPCIE_WRAP_SLV_AWMISC_INFO_TLPPRFX 0x4C01520
+
+#define mmPCIE_WRAP_SLV_ARMISC_INFO 0x4C01524
+
+#define mmPCIE_WRAP_SLV_ARMISC_INFO_TLPPRFX 0x4C01528
+
+#define mmPCIE_WRAP_SLV_ARMISC_INFO_ATU_BYP 0x4C0152C
+
+#define mmPCIE_WRAP_SLV_ARMISC_INFO_FUNC_NUM 0x4C01530
+
+#define mmPCIE_WRAP_SLV_ARMISC_INFO_VFUNC_ACT 0x4C01534
+
+#define mmPCIE_WRAP_SLV_ARMISC_INFO_VFUNC_NUM 0x4C01538
+
+#define mmPCIE_WRAP_MESO_FIFO_CTRL_0 0x4C01640
+
+#define mmPCIE_WRAP_MESO_FIFO_CTRL_1 0x4C01644
+
+#define mmPCIE_WRAP_MESO_FIFO_W_LFSR_POLY_0 0x4C01648
+
+#define mmPCIE_WRAP_MESO_FIFO_W_LFSR_POLY_1 0x4C0164C
+
+#define mmPCIE_WRAP_MESO_FIFO_R_LFSR_POLY_0 0x4C01650
+
+#define mmPCIE_WRAP_MESO_FIFO_R_LFSR_POLY_1 0x4C01654
+
+#define mmPCIE_WRAP_MESO_FIFO_W_PUSH_CNT_0 0x4C01658
+
+#define mmPCIE_WRAP_MESO_FIFO_W_PUSH_CNT_1 0x4C0165C
+
+#define mmPCIE_WRAP_MESO_FIFO_W_BP_CNT_0 0x4C01660
+
+#define mmPCIE_WRAP_MESO_FIFO_W_BP_CNT_1 0x4C01664
+
+#define mmPCIE_WRAP_MESO_FIFO_R_ERR_CNT_0 0x4C01668
+
+#define mmPCIE_WRAP_MESO_FIFO_R_ERR_CNT_1 0x4C0166C
+
+#define mmPCIE_WRAP_MESO_FIFO_R_POP_CNT_0 0x4C01670
+
+#define mmPCIE_WRAP_MESO_FIFO_R_POP_CNT_1 0x4C01674
+
+#define mmPCIE_WRAP_MESO_FIFO_W_LFSR_0 0x4C01678
+
+#define mmPCIE_WRAP_MESO_FIFO_W_LFSR_1 0x4C0167C
+
+#define mmPCIE_WRAP_MESO_FIFO_R_LFSR_0 0x4C01680
+
+#define mmPCIE_WRAP_MESO_FIFO_R_LFSR_1 0x4C01684
+
+#define mmPCIE_WRAP_MESO_FIFO_W_PUSH_LFSR_0 0x4C01688
+
+#define mmPCIE_WRAP_MESO_FIFO_W_PUSH_LFSR_1 0x4C0168C
+
+#define mmPCIE_WRAP_MESO_FIFO_R_POP_LFSR_0 0x4C01690
+
+#define mmPCIE_WRAP_MESO_FIFO_R_POP_LFSR_1 0x4C01694
+
+#define mmPCIE_WRAP_MESO_FIFO_W_BP_PERIOD_0 0x4C01698
+
+#define mmPCIE_WRAP_MESO_FIFO_W_BP_PERIOD_1 0x4C0169C
+
+#define mmPCIE_WRAP_MESO_FIFO_R_BP_PERIOD_0 0x4C016A0
+
+#define mmPCIE_WRAP_MESO_FIFO_R_BP_PERIOD_1 0x4C016A4
+
+#define mmPCIE_WRAP_MESO_FIFO_W_USED_CNT_0 0x4C016A8
+
+#define mmPCIE_WRAP_MESO_FIFO_W_USED_CNT_1 0x4C016AC
+
+#define mmPCIE_WRAP_MESO_FIFO_R_USED_CNT_0 0x4C016B0
+
+#define mmPCIE_WRAP_MESO_FIFO_R_USED_CNT_1 0x4C016B4
+
+#define mmPCIE_WRAP_P2P_TABLE_0 0x4C01900
+
+#define mmPCIE_WRAP_P2P_TABLE_1 0x4C01904
+
+#define mmPCIE_WRAP_P2P_TABLE_2 0x4C01908
+
+#define mmPCIE_WRAP_P2P_TABLE_3 0x4C0190C
+
+#define mmPCIE_WRAP_P2P_TABLE_4 0x4C01910
+
+#define mmPCIE_WRAP_P2P_TABLE_5 0x4C01914
+
+#define mmPCIE_WRAP_P2P_TABLE_6 0x4C01918
+
+#define mmPCIE_WRAP_P2P_TABLE_7 0x4C0191C
+
+#define mmPCIE_WRAP_P2P_TABLE_8 0x4C01920
+
+#define mmPCIE_WRAP_P2P_TABLE_9 0x4C01924
+
+#define mmPCIE_WRAP_P2P_TABLE_10 0x4C01928
+
+#define mmPCIE_WRAP_P2P_TABLE_11 0x4C0192C
+
+#define mmPCIE_WRAP_P2P_TABLE_12 0x4C01930
+
+#define mmPCIE_WRAP_P2P_TABLE_13 0x4C01934
+
+#define mmPCIE_WRAP_P2P_TABLE_14 0x4C01938
+
+#define mmPCIE_WRAP_P2P_TABLE_15 0x4C0193C
+
+#define mmPCIE_WRAP_P2P_TABLE_16 0x4C01940
+
+#define mmPCIE_WRAP_P2P_TABLE_17 0x4C01944
+
+#define mmPCIE_WRAP_P2P_TABLE_18 0x4C01948
+
+#define mmPCIE_WRAP_P2P_TABLE_19 0x4C0194C
+
+#define mmPCIE_WRAP_P2P_TABLE_20 0x4C01950
+
+#define mmPCIE_WRAP_P2P_TABLE_21 0x4C01954
+
+#define mmPCIE_WRAP_P2P_TABLE_22 0x4C01958
+
+#define mmPCIE_WRAP_P2P_TABLE_23 0x4C0195C
+
+#define mmPCIE_WRAP_P2P_TABLE_24 0x4C01960
+
+#define mmPCIE_WRAP_P2P_TABLE_25 0x4C01964
+
+#define mmPCIE_WRAP_P2P_TABLE_26 0x4C01968
+
+#define mmPCIE_WRAP_P2P_TABLE_27 0x4C0196C
+
+#define mmPCIE_WRAP_P2P_TABLE_28 0x4C01970
+
+#define mmPCIE_WRAP_P2P_TABLE_29 0x4C01974
+
+#define mmPCIE_WRAP_P2P_TABLE_30 0x4C01978
+
+#define mmPCIE_WRAP_P2P_TABLE_31 0x4C0197C
+
+#define mmPCIE_WRAP_P2P_TABLE_32 0x4C01980
+
+#define mmPCIE_WRAP_P2P_TABLE_33 0x4C01984
+
+#define mmPCIE_WRAP_P2P_TABLE_34 0x4C01988
+
+#define mmPCIE_WRAP_P2P_TABLE_35 0x4C0198C
+
+#define mmPCIE_WRAP_P2P_TABLE_36 0x4C01990
+
+#define mmPCIE_WRAP_P2P_TABLE_37 0x4C01994
+
+#define mmPCIE_WRAP_P2P_TABLE_38 0x4C01998
+
+#define mmPCIE_WRAP_P2P_TABLE_39 0x4C0199C
+
+#define mmPCIE_WRAP_P2P_TABLE_40 0x4C019A0
+
+#define mmPCIE_WRAP_P2P_TABLE_41 0x4C019A4
+
+#define mmPCIE_WRAP_P2P_TABLE_42 0x4C019A8
+
+#define mmPCIE_WRAP_P2P_TABLE_43 0x4C019AC
+
+#define mmPCIE_WRAP_P2P_TABLE_44 0x4C019B0
+
+#define mmPCIE_WRAP_P2P_TABLE_45 0x4C019B4
+
+#define mmPCIE_WRAP_P2P_TABLE_46 0x4C019B8
+
+#define mmPCIE_WRAP_P2P_TABLE_47 0x4C019BC
+
+#define mmPCIE_WRAP_P2P_TABLE_48 0x4C019C0
+
+#define mmPCIE_WRAP_P2P_TABLE_49 0x4C019C4
+
+#define mmPCIE_WRAP_P2P_TABLE_50 0x4C019C8
+
+#define mmPCIE_WRAP_P2P_TABLE_51 0x4C019CC
+
+#define mmPCIE_WRAP_P2P_TABLE_52 0x4C019D0
+
+#define mmPCIE_WRAP_P2P_TABLE_53 0x4C019D4
+
+#define mmPCIE_WRAP_P2P_TABLE_54 0x4C019D8
+
+#define mmPCIE_WRAP_P2P_TABLE_55 0x4C019DC
+
+#define mmPCIE_WRAP_P2P_TABLE_56 0x4C019E0
+
+#define mmPCIE_WRAP_P2P_TABLE_57 0x4C019E4
+
+#define mmPCIE_WRAP_P2P_TABLE_58 0x4C019E8
+
+#define mmPCIE_WRAP_P2P_TABLE_59 0x4C019EC
+
+#define mmPCIE_WRAP_P2P_TABLE_60 0x4C019F0
+
+#define mmPCIE_WRAP_P2P_TABLE_61 0x4C019F4
+
+#define mmPCIE_WRAP_P2P_TABLE_62 0x4C019F8
+
+#define mmPCIE_WRAP_P2P_TABLE_63 0x4C019FC
+
+#define mmPCIE_WRAP_P2P_EN 0x4C01A00
+
+#define mmPCIE_WRAP_P2P_REQ_ID 0x4C01A04
+
+#define mmPCIE_WRAP_P2P_INTR 0x4C01A08
+
+#define mmPCIE_WRAP_P2P_TERMINATE_RESP 0x4C01A0C
+
+#define mmPCIE_WRAP_GIC_INTR_TERMINATE_CTRL 0x4C01A10
+
+#define mmPCIE_WRAP_GIC_INTR_TERMINATE_CNT 0x4C01A14
+
+#define mmPCIE_WRAP_CPU_HOT_RST 0x4C01AE0
+
+#define mmPCIE_WRAP_LBW_AXI_SPLIT_MAX_OUTSTAN 0x4C01B2C
+
+#define mmPCIE_WRAP_AXI_SPLIT_NO_WR_INFLIGHT 0x4C01B30
+
+#define mmPCIE_WRAP_PCIE_WR_BUF 0x4C01B34
+
+#define mmPCIE_WRAP_PCIE_CACHE_OVR 0x4C01B38
+
+#define mmPCIE_WRAP_PCIE_LOCK_OVR 0x4C01B3C
+
+#define mmPCIE_WRAP_PCIE_PROT_OVR 0x4C01B40
+
+#define mmPCIE_WRAP_PCIE_ARUSER_OVR_0 0x4C01B44
+
+#define mmPCIE_WRAP_PCIE_ARUSER_OVR_1 0x4C01B48
+
+#define mmPCIE_WRAP_PCIE_AWUSER_OVR_0 0x4C01B4C
+
+#define mmPCIE_WRAP_PCIE_AWUSER_OVR_1 0x4C01B50
+
+#define mmPCIE_WRAP_PCIE_ARUSER_OVR_EN_0 0x4C01B54
+
+#define mmPCIE_WRAP_PCIE_ARUSER_OVR_EN_1 0x4C01B58
+
+#define mmPCIE_WRAP_PCIE_AWUSER_OVR_EN_0 0x4C01B5C
+
+#define mmPCIE_WRAP_PCIE_AWUSER_OVR_EN_1 0x4C01B60
+
+#define mmPCIE_WRAP_PCIE_MAX_OUTSTAND 0x4C01B64
+
+#define mmPCIE_WRAP_PCIE_MST_IN 0x4C01B68
+
+#define mmPCIE_WRAP_PCIE_RSP_OK 0x4C01B6C
+
+#define mmPCIE_WRAP_AXI_SPLIT_INTR_0 0x4C01B70
+
+#define mmPCIE_WRAP_AXI_SPLIT_INTR_1 0x4C01B74
+
+#define mmPCIE_WRAP_AXI_DRAIN_MSTR_IF_CFG_0 0x4C01B7C
+
+#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_0 0x4C01B80
+
+#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_1 0x4C01B84
+
+#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_2 0x4C01B88
+
+#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_3 0x4C01B8C
+
+#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_4 0x4C01B90
+
+#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_5 0x4C01B94
+
+#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_6 0x4C01B98
+
+#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_7 0x4C01B9C
+
+#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_8 0x4C01BA0
+
+#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_9 0x4C01BA4
+
+#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_10 0x4C01BA8
+
+#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_11 0x4C01BAC
+
+#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_12 0x4C01BB0
+
+#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_13 0x4C01BB4
+
+#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_14 0x4C01BB8
+
+#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_15 0x4C01BBC
+
+#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_16 0x4C01BC0
+
+#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_17 0x4C01BC4
+
+#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_18 0x4C01BC8
+
+#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_19 0x4C01BCC
+
+#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_20 0x4C01BD0
+
+#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_21 0x4C01BD4
+
+#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_22 0x4C01BD8
+
+#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_23 0x4C01BDC
+
+#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_24 0x4C01BE0
+
+#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_25 0x4C01BE4
+
+#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_26 0x4C01BE8
+
+#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_27 0x4C01BEC
+
+#define mmPCIE_WRAP_AXI_DRAIN_EXTMEM_POLY_H3_28 0x4C01BF0
+
+#define mmPCIE_WRAP_AXI_DRAIN_ACTIVE 0x4C01D48
+
+#define mmPCIE_WRAP_AXI_DRAIN_IND 0x4C01D4C
+
+#define mmPCIE_WRAP_HBW_DRAIN_TIMEOUT 0x4C01D50
+
+#define mmPCIE_WRAP_HBW_DRAIN_CFG 0x4C01D54
+
+#define mmPCIE_WRAP_LBW_DRAIN_TIMEOUT 0x4C01D58
+
+#define mmPCIE_WRAP_LBW_DRAIN_CFG 0x4C01D5C
+
+#define mmPCIE_WRAP_LBW_DRAIN_DELAY_EN_CNT 0x4C01D60
+
+#define mmPCIE_WRAP_PHY_FW_FSM 0x4C01D64
+
+#define mmPCIE_WRAP_PCIE_PHY_BASE_ADDR_L 0x4C01D68
+
+#define mmPCIE_WRAP_PCIE_PHY_BASE_ADDR_H 0x4C01D6C
+
+#define mmPCIE_WRAP_PCIE_CORE_BASE_ADDR_L 0x4C01D70
+
+#define mmPCIE_WRAP_PCIE_CORE_BASE_ADDR_H 0x4C01D74
+
+#define mmPCIE_WRAP_SPMU_INTR 0x4C01DE4
+
+#define mmPCIE_WRAP_AXI_INTR 0x4C01DE8
+
+#define mmPCIE_WRAP_PCIE_IC_SEI_INTR_IND 0x4C01DEC
+
+#define mmPCIE_WRAP_PMMU_RTR_CFG 0x4C01DF0
+
+#define mmPCIE_WRAP_PSOC_RST_CTRL 0x4C01DF4
+
+#define mmPCIE_WRAP_PSOC_BOOT_MNG_DONE 0x4C01DF8
+
+#define mmPCIE_WRAP_ASID_MOD_CTRL 0x4C01DFC
+
+#define mmPCIE_WRAP_ASID_MOD_ADDR_L_0 0x4C01E00
+
+#define mmPCIE_WRAP_ASID_MOD_ADDR_L_1 0x4C01E04
+
+#define mmPCIE_WRAP_ASID_MOD_ADDR_H_0 0x4C01E08
+
+#define mmPCIE_WRAP_ASID_MOD_ADDR_H_1 0x4C01E0C
+
+#define mmPCIE_WRAP_CS_TRACE_AXI_CTRL 0x4C01E10
+
+#define mmPCIE_WRAP_FLR_FSM_CTRL 0x4C01E14
+
+#define mmPCIE_WRAP_HBW_DRAIN_WR_ADDR_0 0x4C01E18
+
+#define mmPCIE_WRAP_HBW_DRAIN_WR_ADDR_1 0x4C01E1C
+
+#define mmPCIE_WRAP_HBW_DRAIN_RD_ADDR_0 0x4C01E20
+
+#define mmPCIE_WRAP_HBW_DRAIN_RD_ADDR_1 0x4C01E24
+
+#define mmPCIE_WRAP_HBW_DRAIN_STAMP 0x4C01E28
+
+#define mmPCIE_WRAP_LBW_DRAIN_WR_ADDR_0 0x4C01E2C
+
+#define mmPCIE_WRAP_LBW_DRAIN_WR_ADDR_1 0x4C01E30
+
+#define mmPCIE_WRAP_LBW_DRAIN_RD_ADDR_0 0x4C01E34
+
+#define mmPCIE_WRAP_LBW_DRAIN_RD_ADDR_1 0x4C01E38
+
+#define mmPCIE_WRAP_LBW_DRAIN_STAMP 0x4C01E3C
+
+#define mmPCIE_WRAP_EXTMEM_HBM_LOC 0x4C01E40
+
+#define mmPCIE_WRAP_EXTMEM_PC_LOC 0x4C01E44
+
+#define mmPCIE_WRAP_EXTMEM_NONLIN_HBM 0x4C01E48
+
+#define mmPCIE_WRAP_EXTMEM_NONLIN_PC 0x4C01E4C
+
+#define mmPCIE_WRAP_EXTMEM_NONLIN_HBM_NUM 0x4C01E50
+
+#define mmPCIE_WRAP_EXTMEM_NONLIN_HBM_MAP 0x4C01E54
+
+#endif /* ASIC_REG_PCIE_WRAP_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_wrap_special_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_wrap_special_regs.h
new file mode 100644
index 000000000000..46558e7a7f63
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_wrap_special_regs.h
@@ -0,0 +1,185 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PCIE_WRAP_SPECIAL_REGS_H_
+#define ASIC_REG_PCIE_WRAP_SPECIAL_REGS_H_
+
+/*
+ *****************************************
+ *   PCIE_WRAP_SPECIAL
+ *   (Prototype: SPECIAL_REGS)
+ *****************************************
+ */
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_0 0x4C01E80
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_1 0x4C01E84
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_2 0x4C01E88
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_3 0x4C01E8C
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_4 0x4C01E90
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_5 0x4C01E94
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_6 0x4C01E98
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_7 0x4C01E9C
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_8 0x4C01EA0
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_9 0x4C01EA4
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_10 0x4C01EA8
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_11 0x4C01EAC
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_12 0x4C01EB0
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_13 0x4C01EB4
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_14 0x4C01EB8
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_15 0x4C01EBC
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_16 0x4C01EC0
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_17 0x4C01EC4
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_18 0x4C01EC8
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_19 0x4C01ECC
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_20 0x4C01ED0
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_21 0x4C01ED4
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_22 0x4C01ED8
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_23 0x4C01EDC
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_24 0x4C01EE0
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_25 0x4C01EE4
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_26 0x4C01EE8
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_27 0x4C01EEC
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_28 0x4C01EF0
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_29 0x4C01EF4
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_30 0x4C01EF8
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_31 0x4C01EFC
+
+#define mmPCIE_WRAP_SPECIAL_MEM_GW_DATA 0x4C01F00
+
+#define mmPCIE_WRAP_SPECIAL_MEM_GW_REQ 0x4C01F04
+
+#define mmPCIE_WRAP_SPECIAL_MEM_NUMOF 0x4C01F0C
+
+#define mmPCIE_WRAP_SPECIAL_MEM_ECC_SEL 0x4C01F10
+
+#define mmPCIE_WRAP_SPECIAL_MEM_ECC_CTL 0x4C01F14
+
+#define mmPCIE_WRAP_SPECIAL_MEM_ECC_ERR_MASK 0x4C01F18
+
+#define mmPCIE_WRAP_SPECIAL_MEM_ECC_GLBL_ERR_MASK 0x4C01F1C
+
+#define mmPCIE_WRAP_SPECIAL_MEM_ECC_ERR_STS 0x4C01F20
+
+#define mmPCIE_WRAP_SPECIAL_MEM_ECC_ERR_ADDR 0x4C01F24
+
+#define mmPCIE_WRAP_SPECIAL_MEM_RM 0x4C01F28
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_ERR_MASK 0x4C01F40
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_ERR_ADDR 0x4C01F44
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_ERR_CAUSE 0x4C01F48
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_SPARE_0 0x4C01F60
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_SPARE_1 0x4C01F64
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_SPARE_2 0x4C01F68
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_SPARE_3 0x4C01F6C
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_0 0x4C01F80
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_1 0x4C01F84
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_2 0x4C01F88
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_3 0x4C01F8C
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_4 0x4C01F90
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_5 0x4C01F94
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_6 0x4C01F98
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_7 0x4C01F9C
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_8 0x4C01FA0
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_9 0x4C01FA4
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_10 0x4C01FA8
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_11 0x4C01FAC
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_12 0x4C01FB0
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_13 0x4C01FB4
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_14 0x4C01FB8
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_15 0x4C01FBC
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_16 0x4C01FC0
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_17 0x4C01FC4
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_18 0x4C01FC8
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_19 0x4C01FCC
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_20 0x4C01FD0
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_21 0x4C01FD4
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_22 0x4C01FD8
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_23 0x4C01FDC
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_24 0x4C01FE0
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_25 0x4C01FE4
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_26 0x4C01FE8
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_27 0x4C01FEC
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_28 0x4C01FF0
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_29 0x4C01FF4
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_30 0x4C01FF8
+
+#define mmPCIE_WRAP_SPECIAL_GLBL_SEC_31 0x4C01FFC
+
+#endif /* ASIC_REG_PCIE_WRAP_SPECIAL_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_core_ctx_axuser_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_core_ctx_axuser_regs.h
new file mode 100644
index 000000000000..bacbe4c6fc3c
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_core_ctx_axuser_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PDMA0_CORE_CTX_AXUSER_REGS_H_
+#define ASIC_REG_PDMA0_CORE_CTX_AXUSER_REGS_H_
+
+/*
+ *****************************************
+ *   PDMA0_CORE_CTX_AXUSER
+ *   (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define mmPDMA0_CORE_CTX_AXUSER_HB_ASID 0x4C8B800
+
+#define mmPDMA0_CORE_CTX_AXUSER_HB_MMU_BP 0x4C8B804
+
+#define mmPDMA0_CORE_CTX_AXUSER_HB_STRONG_ORDER 0x4C8B808
+
+#define mmPDMA0_CORE_CTX_AXUSER_HB_NO_SNOOP 0x4C8B80C
+
+#define mmPDMA0_CORE_CTX_AXUSER_HB_WR_REDUCTION 0x4C8B810
+
+#define mmPDMA0_CORE_CTX_AXUSER_HB_RD_ATOMIC 0x4C8B814
+
+#define mmPDMA0_CORE_CTX_AXUSER_HB_QOS 0x4C8B818
+
+#define mmPDMA0_CORE_CTX_AXUSER_HB_RSVD 0x4C8B81C
+
+#define mmPDMA0_CORE_CTX_AXUSER_HB_EMEM_CPAGE 0x4C8B820
+
+#define mmPDMA0_CORE_CTX_AXUSER_HB_CORE 0x4C8B824
+
+#define mmPDMA0_CORE_CTX_AXUSER_E2E_COORD 0x4C8B828
+
+#define mmPDMA0_CORE_CTX_AXUSER_HB_WR_OVRD_LO 0x4C8B830
+
+#define mmPDMA0_CORE_CTX_AXUSER_HB_WR_OVRD_HI 0x4C8B834
+
+#define mmPDMA0_CORE_CTX_AXUSER_HB_RD_OVRD_LO 0x4C8B838
+
+#define mmPDMA0_CORE_CTX_AXUSER_HB_RD_OVRD_HI 0x4C8B83C
+
+#define mmPDMA0_CORE_CTX_AXUSER_LB_COORD 0x4C8B840
+
+#define mmPDMA0_CORE_CTX_AXUSER_LB_LOCK 0x4C8B844
+
+#define mmPDMA0_CORE_CTX_AXUSER_LB_RSVD 0x4C8B848
+
+#define mmPDMA0_CORE_CTX_AXUSER_LB_OVRD 0x4C8B84C
+
+#endif /* ASIC_REG_PDMA0_CORE_CTX_AXUSER_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_core_ctx_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_core_ctx_regs.h
new file mode 100644
index 000000000000..02b57f07cfaf
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_core_ctx_regs.h
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PDMA0_CORE_CTX_REGS_H_
+#define ASIC_REG_PDMA0_CORE_CTX_REGS_H_
+
+/*
+ *****************************************
+ *   PDMA0_CORE_CTX
+ *   (Prototype: DMA_CORE_CTX)
+ *****************************************
+ */
+
+#define mmPDMA0_CORE_CTX_RATE_LIM_TKN 0x4C8B860
+
+#define mmPDMA0_CORE_CTX_PWRLP 0x4C8B864
+
+#define mmPDMA0_CORE_CTX_TE_NUMROWS 0x4C8B868
+
+#define mmPDMA0_CORE_CTX_IDX 0x4C8B86C
+
+#define mmPDMA0_CORE_CTX_IDX_INC 0x4C8B870
+
+#define mmPDMA0_CORE_CTX_CTRL 0x4C8B874
+
+#define mmPDMA0_CORE_CTX_SRC_TSIZE_0 0x4C8B878
+
+#define mmPDMA0_CORE_CTX_SRC_TSIZE_1 0x4C8B87C
+
+#define mmPDMA0_CORE_CTX_SRC_STRIDE_1 0x4C8B880
+
+#define mmPDMA0_CORE_CTX_SRC_TSIZE_2 0x4C8B884
+
+#define mmPDMA0_CORE_CTX_SRC_STRIDE_2 0x4C8B888
+
+#define mmPDMA0_CORE_CTX_SRC_TSIZE_3 0x4C8B88C
+
+#define mmPDMA0_CORE_CTX_SRC_STRIDE_3 0x4C8B890
+
+#define mmPDMA0_CORE_CTX_SRC_TSIZE_4 0x4C8B894
+
+#define mmPDMA0_CORE_CTX_SRC_STRIDE_4 0x4C8B898
+
+#define mmPDMA0_CORE_CTX_DST_TSIZE_1 0x4C8B89C
+
+#define mmPDMA0_CORE_CTX_DST_STRIDE_1 0x4C8B8A0
+
+#define mmPDMA0_CORE_CTX_DST_TSIZE_2 0x4C8B8A4
+
+#define mmPDMA0_CORE_CTX_DST_STRIDE_2 0x4C8B8A8
+
+#define mmPDMA0_CORE_CTX_DST_TSIZE_3 0x4C8B8AC
+
+#define mmPDMA0_CORE_CTX_DST_STRIDE_3 0x4C8B8B0
+
+#define mmPDMA0_CORE_CTX_DST_TSIZE_4 0x4C8B8B4
+
+#define mmPDMA0_CORE_CTX_DST_STRIDE_4 0x4C8B8B8
+
+#define mmPDMA0_CORE_CTX_WR_COMP_ADDR_HI 0x4C8B8BC
+
+#define mmPDMA0_CORE_CTX_WR_COMP_ADDR_LO 0x4C8B8C0
+
+#define mmPDMA0_CORE_CTX_WR_COMP_WDATA 0x4C8B8C4
+
+#define mmPDMA0_CORE_CTX_SRC_OFFSET_LO 0x4C8B8C8
+
+#define mmPDMA0_CORE_CTX_SRC_OFFSET_HI 0x4C8B8CC
+
+#define mmPDMA0_CORE_CTX_DST_OFFSET_LO 0x4C8B8D0
+
+#define mmPDMA0_CORE_CTX_DST_OFFSET_HI 0x4C8B8D4
+
+#define mmPDMA0_CORE_CTX_SRC_BASE_LO 0x4C8B8D8
+
+#define mmPDMA0_CORE_CTX_SRC_BASE_HI 0x4C8B8DC
+
+#define mmPDMA0_CORE_CTX_DST_BASE_LO 0x4C8B8E0
+
+#define mmPDMA0_CORE_CTX_DST_BASE_HI 0x4C8B8E4
+
+#define mmPDMA0_CORE_CTX_DST_TSIZE_0 0x4C8B8E8
+
+#define mmPDMA0_CORE_CTX_COMMIT 0x4C8B8EC
+
+#endif /* ASIC_REG_PDMA0_CORE_CTX_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_core_masks.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_core_masks.h
new file mode 100644
index 000000000000..909cda03c246
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_core_masks.h
@@ -0,0 +1,415 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PDMA0_CORE_MASKS_H_
+#define ASIC_REG_PDMA0_CORE_MASKS_H_
+
+/*
+ *****************************************
+ *   PDMA0_CORE
+ *   (Prototype: DMA_CORE)
+ *****************************************
+ */
+
+/* PDMA0_CORE_CFG_0 */
+#define PDMA0_CORE_CFG_0_EN_SHIFT 0
+#define PDMA0_CORE_CFG_0_EN_MASK 0x1
+
+/* PDMA0_CORE_CFG_1 */
+#define PDMA0_CORE_CFG_1_HALT_SHIFT 0
+#define PDMA0_CORE_CFG_1_HALT_MASK 0x1
+#define PDMA0_CORE_CFG_1_FLUSH_SHIFT 1
+#define PDMA0_CORE_CFG_1_FLUSH_MASK 0x2
+
+/* PDMA0_CORE_PROT */
+#define PDMA0_CORE_PROT_VAL_SHIFT 0
+#define PDMA0_CORE_PROT_VAL_MASK 0x1
+#define PDMA0_CORE_PROT_ERR_VAL_SHIFT 1
+#define PDMA0_CORE_PROT_ERR_VAL_MASK 0x2
+
+/* PDMA0_CORE_CKG */
+#define PDMA0_CORE_CKG_HBW_RBUF_SHIFT 0
+#define PDMA0_CORE_CKG_HBW_RBUF_MASK 0x1
+#define PDMA0_CORE_CKG_LBW_RBUF_KDMA_SHIFT 1
+#define PDMA0_CORE_CKG_LBW_RBUF_KDMA_MASK 0x2
+#define PDMA0_CORE_CKG_TE_SHIFT 2
+#define PDMA0_CORE_CKG_TE_MASK 0x4
+
+/* PDMA0_CORE_RD_GLBL */
+#define PDMA0_CORE_RD_GLBL_LBW_VIA_HBW_SHIFT 0
+#define PDMA0_CORE_RD_GLBL_LBW_VIA_HBW_MASK 0x1
+#define PDMA0_CORE_RD_GLBL_HBW_FORCE_MISS_SHIFT 4
+#define PDMA0_CORE_RD_GLBL_HBW_FORCE_MISS_MASK 0x10
+#define PDMA0_CORE_RD_GLBL_LBW_FORCE_MISS_SHIFT 5
+#define PDMA0_CORE_RD_GLBL_LBW_FORCE_MISS_MASK 0x20
+
+/* PDMA0_CORE_RD_HBW_MAX_OUTSTAND */
+#define PDMA0_CORE_RD_HBW_MAX_OUTSTAND_VAL_SHIFT 0
+#define PDMA0_CORE_RD_HBW_MAX_OUTSTAND_VAL_MASK 0xFFF
+
+/* PDMA0_CORE_RD_HBW_MAX_SIZE */
+#define PDMA0_CORE_RD_HBW_MAX_SIZE_DATA_SHIFT 0
+#define PDMA0_CORE_RD_HBW_MAX_SIZE_DATA_MASK 0xFFF
+#define PDMA0_CORE_RD_HBW_MAX_SIZE_MD_SHIFT 16
+#define PDMA0_CORE_RD_HBW_MAX_SIZE_MD_MASK 0xFFF0000
+
+/* PDMA0_CORE_RD_HBW_ARCACHE */
+#define PDMA0_CORE_RD_HBW_ARCACHE_VAL_SHIFT 0
+#define PDMA0_CORE_RD_HBW_ARCACHE_VAL_MASK 0xF
+
+/* PDMA0_CORE_RD_HBW_INFLIGHTS */
+#define PDMA0_CORE_RD_HBW_INFLIGHTS_VAL_SHIFT 0
+#define PDMA0_CORE_RD_HBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_CORE_RD_HBW_RATE_LIM_CFG */
+#define PDMA0_CORE_RD_HBW_RATE_LIM_CFG_TOUT_SHIFT 0
+#define PDMA0_CORE_RD_HBW_RATE_LIM_CFG_TOUT_MASK 0xFF
+#define PDMA0_CORE_RD_HBW_RATE_LIM_CFG_SAT_SHIFT 16
+#define PDMA0_CORE_RD_HBW_RATE_LIM_CFG_SAT_MASK 0xFF0000
+#define PDMA0_CORE_RD_HBW_RATE_LIM_CFG_EN_SHIFT 31
+#define PDMA0_CORE_RD_HBW_RATE_LIM_CFG_EN_MASK 0x80000000
+
+/* PDMA0_CORE_RD_LBW_MAX_OUTSTAND */
+#define PDMA0_CORE_RD_LBW_MAX_OUTSTAND_VAL_SHIFT 0
+#define PDMA0_CORE_RD_LBW_MAX_OUTSTAND_VAL_MASK 0xFFF
+
+/* PDMA0_CORE_RD_LBW_MAX_SIZE */
+#define PDMA0_CORE_RD_LBW_MAX_SIZE_DATA_SHIFT 0
+#define PDMA0_CORE_RD_LBW_MAX_SIZE_DATA_MASK 0xFFF
+#define PDMA0_CORE_RD_LBW_MAX_SIZE_MD_SHIFT 16
+#define PDMA0_CORE_RD_LBW_MAX_SIZE_MD_MASK 0xFFF0000
+
+/* PDMA0_CORE_RD_LBW_ARCACHE */
+#define PDMA0_CORE_RD_LBW_ARCACHE_VAL_SHIFT 0
+#define PDMA0_CORE_RD_LBW_ARCACHE_VAL_MASK 0xF
+
+/* PDMA0_CORE_RD_LBW_INFLIGHTS */
+#define PDMA0_CORE_RD_LBW_INFLIGHTS_VAL_SHIFT 0
+#define PDMA0_CORE_RD_LBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_CORE_RD_LBW_RATE_LIM_CFG */
+#define PDMA0_CORE_RD_LBW_RATE_LIM_CFG_TOUT_SHIFT 0
+#define PDMA0_CORE_RD_LBW_RATE_LIM_CFG_TOUT_MASK 0xFF
+#define PDMA0_CORE_RD_LBW_RATE_LIM_CFG_SAT_SHIFT 16
+#define PDMA0_CORE_RD_LBW_RATE_LIM_CFG_SAT_MASK 0xFF0000
+#define PDMA0_CORE_RD_LBW_RATE_LIM_CFG_EN_SHIFT 31
+#define PDMA0_CORE_RD_LBW_RATE_LIM_CFG_EN_MASK 0x80000000
+
+/* PDMA0_CORE_WR_HBW_MAX_OUTSTAND */
+#define PDMA0_CORE_WR_HBW_MAX_OUTSTAND_VAL_SHIFT 0
+#define PDMA0_CORE_WR_HBW_MAX_OUTSTAND_VAL_MASK 0xFFFF
+
+/* PDMA0_CORE_WR_HBW_MAX_AWID */
+#define PDMA0_CORE_WR_HBW_MAX_AWID_VAL_SHIFT 0
+#define PDMA0_CORE_WR_HBW_MAX_AWID_VAL_MASK 0x3FFF
+
+/* PDMA0_CORE_WR_HBW_AWCACHE */
+#define PDMA0_CORE_WR_HBW_AWCACHE_VAL_SHIFT 0
+#define PDMA0_CORE_WR_HBW_AWCACHE_VAL_MASK 0xF
+
+/* PDMA0_CORE_WR_HBW_INFLIGHTS */
+#define PDMA0_CORE_WR_HBW_INFLIGHTS_VAL_SHIFT 0
+#define PDMA0_CORE_WR_HBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_CORE_WR_HBW_RATE_LIM_CFG */
+#define PDMA0_CORE_WR_HBW_RATE_LIM_CFG_TOUT_SHIFT 0
+#define PDMA0_CORE_WR_HBW_RATE_LIM_CFG_TOUT_MASK 0xFF
+#define PDMA0_CORE_WR_HBW_RATE_LIM_CFG_SAT_SHIFT 16
+#define PDMA0_CORE_WR_HBW_RATE_LIM_CFG_SAT_MASK 0xFF0000
+#define PDMA0_CORE_WR_HBW_RATE_LIM_CFG_EN_SHIFT 31
+#define PDMA0_CORE_WR_HBW_RATE_LIM_CFG_EN_MASK 0x80000000
+
+/* PDMA0_CORE_WR_LBW_MAX_OUTSTAND */
+#define PDMA0_CORE_WR_LBW_MAX_OUTSTAND_VAL_SHIFT 0
+#define PDMA0_CORE_WR_LBW_MAX_OUTSTAND_VAL_MASK 0xFFFF
+
+/* PDMA0_CORE_WR_LBW_MAX_AWID */
+#define PDMA0_CORE_WR_LBW_MAX_AWID_VAL_SHIFT 0
+#define PDMA0_CORE_WR_LBW_MAX_AWID_VAL_MASK 0x7F
+
+/* PDMA0_CORE_WR_LBW_AWCACHE */
+#define PDMA0_CORE_WR_LBW_AWCACHE_VAL_SHIFT 0
+#define PDMA0_CORE_WR_LBW_AWCACHE_VAL_MASK 0xF
+
+/* PDMA0_CORE_WR_LBW_INFLIGHTS */
+#define PDMA0_CORE_WR_LBW_INFLIGHTS_VAL_SHIFT 0
+#define PDMA0_CORE_WR_LBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_CORE_WR_LBW_RATE_LIM_CFG */
+#define PDMA0_CORE_WR_LBW_RATE_LIM_CFG_TOUT_SHIFT 0
+#define PDMA0_CORE_WR_LBW_RATE_LIM_CFG_TOUT_MASK 0xFF
+#define PDMA0_CORE_WR_LBW_RATE_LIM_CFG_SAT_SHIFT 16
+#define PDMA0_CORE_WR_LBW_RATE_LIM_CFG_SAT_MASK 0xFF0000
+#define PDMA0_CORE_WR_LBW_RATE_LIM_CFG_EN_SHIFT 31
+#define PDMA0_CORE_WR_LBW_RATE_LIM_CFG_EN_MASK 0x80000000
+
+/* PDMA0_CORE_WR_COMP_MAX_OUTSTAND */
+#define PDMA0_CORE_WR_COMP_MAX_OUTSTAND_VAL_SHIFT 0
+#define PDMA0_CORE_WR_COMP_MAX_OUTSTAND_VAL_MASK 0x1F
+
+/* PDMA0_CORE_WR_COMP_AWUSER */
+#define PDMA0_CORE_WR_COMP_AWUSER_VAL_SHIFT 0
+#define PDMA0_CORE_WR_COMP_AWUSER_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_CORE_ERR_CFG */
+#define PDMA0_CORE_ERR_CFG_ERR_MSG_EN_SHIFT 0
+#define PDMA0_CORE_ERR_CFG_ERR_MSG_EN_MASK 0x1
+#define PDMA0_CORE_ERR_CFG_STOP_ON_ERR_SHIFT 1
+#define PDMA0_CORE_ERR_CFG_STOP_ON_ERR_MASK 0x2
+
+/* PDMA0_CORE_ERR_CAUSE */
+#define PDMA0_CORE_ERR_CAUSE_HBW_RD_ERR_SHIFT 0
+#define PDMA0_CORE_ERR_CAUSE_HBW_RD_ERR_MASK 0x1
+#define PDMA0_CORE_ERR_CAUSE_HBW_WR_ERR_SHIFT 1
+#define PDMA0_CORE_ERR_CAUSE_HBW_WR_ERR_MASK 0x2
+#define PDMA0_CORE_ERR_CAUSE_LBW_MSG_WR_ERR_SHIFT 2
+#define PDMA0_CORE_ERR_CAUSE_LBW_MSG_WR_ERR_MASK 0x4
+#define PDMA0_CORE_ERR_CAUSE_DESC_OVF_SHIFT 3
+#define PDMA0_CORE_ERR_CAUSE_DESC_OVF_MASK 0x8
+#define PDMA0_CORE_ERR_CAUSE_LBW_RD_ERR_SHIFT 4
+#define PDMA0_CORE_ERR_CAUSE_LBW_RD_ERR_MASK 0x10
+#define PDMA0_CORE_ERR_CAUSE_LBW_WR_ERR_SHIFT 5
+#define PDMA0_CORE_ERR_CAUSE_LBW_WR_ERR_MASK 0x20
+#define PDMA0_CORE_ERR_CAUSE_TE_DESC_FIFO_OVFL_SHIFT 6
+#define PDMA0_CORE_ERR_CAUSE_TE_DESC_FIFO_OVFL_MASK 0x40
+#define PDMA0_CORE_ERR_CAUSE_LIN_DMA_COMMIT_CFG_ERR_SHIFT 7
+#define PDMA0_CORE_ERR_CAUSE_LIN_DMA_COMMIT_CFG_ERR_MASK 0x80
+
+/* PDMA0_CORE_ERRMSG_ADDR_LO */
+#define PDMA0_CORE_ERRMSG_ADDR_LO_VAL_SHIFT 0
+#define PDMA0_CORE_ERRMSG_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_CORE_ERRMSG_ADDR_HI */
+#define PDMA0_CORE_ERRMSG_ADDR_HI_VAL_SHIFT 0
+#define PDMA0_CORE_ERRMSG_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_CORE_ERRMSG_WDATA */
+#define PDMA0_CORE_ERRMSG_WDATA_VAL_SHIFT 0
+#define PDMA0_CORE_ERRMSG_WDATA_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_CORE_STS0 */
+#define PDMA0_CORE_STS0_RD_REQ_CNT_SHIFT 0
+#define PDMA0_CORE_STS0_RD_REQ_CNT_MASK 0x7FFF
+#define PDMA0_CORE_STS0_WR_REQ_CNT_SHIFT 16
+#define PDMA0_CORE_STS0_WR_REQ_CNT_MASK 0x7FFF0000
+#define PDMA0_CORE_STS0_BUSY_SHIFT 31
+#define PDMA0_CORE_STS0_BUSY_MASK 0x80000000
+
+/* PDMA0_CORE_STS1 */
+#define PDMA0_CORE_STS1_IS_HALT_SHIFT 0
+#define PDMA0_CORE_STS1_IS_HALT_MASK 0x1
+
+/* PDMA0_CORE_STS_RD_CTX_SEL */
+#define PDMA0_CORE_STS_RD_CTX_SEL_VAL_SHIFT 0
+#define PDMA0_CORE_STS_RD_CTX_SEL_VAL_MASK 0x7
+#define PDMA0_CORE_STS_RD_CTX_SEL_STRIDE_SHIFT 8
+#define PDMA0_CORE_STS_RD_CTX_SEL_STRIDE_MASK 0x100
+
+/* PDMA0_CORE_STS_RD_CTX_SIZE */
+#define PDMA0_CORE_STS_RD_CTX_SIZE_VAL_SHIFT 0
+#define PDMA0_CORE_STS_RD_CTX_SIZE_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_CORE_STS_RD_CTX_BASE_LO */
+#define PDMA0_CORE_STS_RD_CTX_BASE_LO_VAL_SHIFT 0
+#define PDMA0_CORE_STS_RD_CTX_BASE_LO_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_CORE_STS_RD_CTX_BASE_HI */
+#define PDMA0_CORE_STS_RD_CTX_BASE_HI_VAL_SHIFT 0
+#define PDMA0_CORE_STS_RD_CTX_BASE_HI_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_CORE_STS_RD_CTX_ID */
+#define PDMA0_CORE_STS_RD_CTX_ID_VAL_SHIFT 0
+#define PDMA0_CORE_STS_RD_CTX_ID_VAL_MASK 0xFFFF
+
+/* PDMA0_CORE_STS_RD_HB_AXI_ADDR_LO */
+#define PDMA0_CORE_STS_RD_HB_AXI_ADDR_LO_VAL_SHIFT 0
+#define PDMA0_CORE_STS_RD_HB_AXI_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_CORE_STS_RD_HB_AXI_ADDR_HI */
+#define PDMA0_CORE_STS_RD_HB_AXI_ADDR_HI_VAL_SHIFT 0
+#define PDMA0_CORE_STS_RD_HB_AXI_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_CORE_STS_RD_LB_AXI_ADDR */
+#define PDMA0_CORE_STS_RD_LB_AXI_ADDR_VAL_SHIFT 0
+#define PDMA0_CORE_STS_RD_LB_AXI_ADDR_VAL_MASK 0x3FFFFFF
+#define PDMA0_CORE_STS_RD_LB_AXI_ADDR_RDY_SHIFT 30
+#define PDMA0_CORE_STS_RD_LB_AXI_ADDR_RDY_MASK 0x40000000
+#define PDMA0_CORE_STS_RD_LB_AXI_ADDR_VLD_SHIFT 31
+#define PDMA0_CORE_STS_RD_LB_AXI_ADDR_VLD_MASK 0x80000000
+
+/* PDMA0_CORE_STS_WR_CTX_SEL */
+#define PDMA0_CORE_STS_WR_CTX_SEL_VAL_SHIFT 0
+#define PDMA0_CORE_STS_WR_CTX_SEL_VAL_MASK 0x7
+#define PDMA0_CORE_STS_WR_CTX_SEL_STRIDE_SHIFT 8
+#define PDMA0_CORE_STS_WR_CTX_SEL_STRIDE_MASK 0x100
+
+/* PDMA0_CORE_STS_WR_CTX_SIZE */
+#define PDMA0_CORE_STS_WR_CTX_SIZE_VAL_SHIFT 0
+#define PDMA0_CORE_STS_WR_CTX_SIZE_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_CORE_STS_WR_CTX_BASE_LO */
+#define PDMA0_CORE_STS_WR_CTX_BASE_LO_VAL_SHIFT 0
+#define PDMA0_CORE_STS_WR_CTX_BASE_LO_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_CORE_STS_WR_CTX_BASE_HI */
+#define PDMA0_CORE_STS_WR_CTX_BASE_HI_VAL_SHIFT 0
+#define PDMA0_CORE_STS_WR_CTX_BASE_HI_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_CORE_STS_WR_CTX_ID */
+#define PDMA0_CORE_STS_WR_CTX_ID_VAL_SHIFT 0
+#define PDMA0_CORE_STS_WR_CTX_ID_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_CORE_STS_WR_HB_AXI_ADDR_LO */
+#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_VAL_SHIFT 0
+#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_VAL_MASK 0x3FFFF
+#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_RDY_SHIFT 30
+#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_RDY_MASK 0x40000000
+#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_VLD_SHIFT 31
+#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_VLD_MASK 0x80000000
+
+/* PDMA0_CORE_STS_WR_HB_AXI_ADDR_HI */
+#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_VAL_SHIFT 0
+#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_VAL_MASK 0x3FFFF
+#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_RDY_SHIFT 30
+#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_RDY_MASK 0x40000000
+#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_VLD_SHIFT 31
+#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_VLD_MASK 0x80000000
+
+/* PDMA0_CORE_STS_WR_LB_AXI_ADDR */
+#define PDMA0_CORE_STS_WR_LB_AXI_ADDR_VAL_SHIFT 0
+#define PDMA0_CORE_STS_WR_LB_AXI_ADDR_VAL_MASK 0x3FFFFFF
+#define PDMA0_CORE_STS_WR_LB_AXI_ADDR_RDY_SHIFT 30
+#define PDMA0_CORE_STS_WR_LB_AXI_ADDR_RDY_MASK 0x40000000
+#define PDMA0_CORE_STS_WR_LB_AXI_ADDR_VLD_SHIFT 31
+#define PDMA0_CORE_STS_WR_LB_AXI_ADDR_VLD_MASK 0x80000000
+
+/* PDMA0_CORE_PWRLP_CFG */
+#define PDMA0_CORE_PWRLP_CFG_GLBL_EN_SHIFT 0
+#define PDMA0_CORE_PWRLP_CFG_GLBL_EN_MASK 0x1
+#define PDMA0_CORE_PWRLP_CFG_CLR_SHIFT 4
+#define PDMA0_CORE_PWRLP_CFG_CLR_MASK 0x10
+
+/* PDMA0_CORE_PWRLP_STS */
+#define PDMA0_CORE_PWRLP_STS_RLVL_SHIFT 0
+#define PDMA0_CORE_PWRLP_STS_RLVL_MASK 0x7F
+#define PDMA0_CORE_PWRLP_STS_WLVL_SHIFT 8
+#define PDMA0_CORE_PWRLP_STS_WLVL_MASK 0x7F00
+#define PDMA0_CORE_PWRLP_STS_RCNT_SHIFT 16
+#define PDMA0_CORE_PWRLP_STS_RCNT_MASK 0x7F0000
+#define PDMA0_CORE_PWRLP_STS_WCNT_SHIFT 23
+#define PDMA0_CORE_PWRLP_STS_WCNT_MASK 0x3F800000
+#define PDMA0_CORE_PWRLP_STS_RFULL_SHIFT 30
+#define PDMA0_CORE_PWRLP_STS_RFULL_MASK 0x40000000
+#define PDMA0_CORE_PWRLP_STS_WFULL_SHIFT 31
+#define PDMA0_CORE_PWRLP_STS_WFULL_MASK 0x80000000
+
+/* PDMA0_CORE_DBG_DESC_CNT */
+#define PDMA0_CORE_DBG_DESC_CNT_VAL_SHIFT 0
+#define PDMA0_CORE_DBG_DESC_CNT_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_CORE_DBG_STS */
+#define PDMA0_CORE_DBG_STS_RD_CTX_FULL_SHIFT 0
+#define PDMA0_CORE_DBG_STS_RD_CTX_FULL_MASK 0x1
+#define PDMA0_CORE_DBG_STS_WR_CTX_FULL_SHIFT 1
+#define PDMA0_CORE_DBG_STS_WR_CTX_FULL_MASK 0x2
+#define PDMA0_CORE_DBG_STS_WR_COMP_FULL_SHIFT 2
+#define PDMA0_CORE_DBG_STS_WR_COMP_FULL_MASK 0x4
+#define PDMA0_CORE_DBG_STS_RD_CTX_EMPTY_SHIFT 3
+#define PDMA0_CORE_DBG_STS_RD_CTX_EMPTY_MASK 0x8
+#define PDMA0_CORE_DBG_STS_WR_CTX_EMPTY_SHIFT 4
+#define PDMA0_CORE_DBG_STS_WR_CTX_EMPTY_MASK 0x10
+#define PDMA0_CORE_DBG_STS_WR_COMP_EMPTY_SHIFT 5
+#define PDMA0_CORE_DBG_STS_WR_COMP_EMPTY_MASK 0x20
+#define PDMA0_CORE_DBG_STS_TE_EMPTY_SHIFT 6
+#define PDMA0_CORE_DBG_STS_TE_EMPTY_MASK 0x40
+#define PDMA0_CORE_DBG_STS_TE_BUSY_SHIFT 7
+#define PDMA0_CORE_DBG_STS_TE_BUSY_MASK 0x80
+#define PDMA0_CORE_DBG_STS_GSKT_EMPTY_SHIFT 8
+#define PDMA0_CORE_DBG_STS_GSKT_EMPTY_MASK 0x100
+#define PDMA0_CORE_DBG_STS_GSKT_FULL_SHIFT 9
+#define PDMA0_CORE_DBG_STS_GSKT_FULL_MASK 0x200
+#define PDMA0_CORE_DBG_STS_RD_AGU_CS_SHIFT 10
+#define PDMA0_CORE_DBG_STS_RD_AGU_CS_MASK 0x400
+#define PDMA0_CORE_DBG_STS_WR_AGU_CS_SHIFT 11
+#define PDMA0_CORE_DBG_STS_WR_AGU_CS_MASK 0x800
+
+/* PDMA0_CORE_DBG_BUF_STS */
+#define PDMA0_CORE_DBG_BUF_STS_HBW_FULLNESS_SHIFT 0
+#define PDMA0_CORE_DBG_BUF_STS_HBW_FULLNESS_MASK 0xFFF
+#define PDMA0_CORE_DBG_BUF_STS_LBW_FULLNESS_SHIFT 16
+#define PDMA0_CORE_DBG_BUF_STS_LBW_FULLNESS_MASK 0xFFF0000
+
+/* PDMA0_CORE_DBG_RD_DESC_ID */
+#define PDMA0_CORE_DBG_RD_DESC_ID_VAL_SHIFT 0
+#define PDMA0_CORE_DBG_RD_DESC_ID_VAL_MASK 0xFFFF
+
+/* PDMA0_CORE_DBG_WR_DESC_ID */
+#define PDMA0_CORE_DBG_WR_DESC_ID_VAL_SHIFT 0
+#define PDMA0_CORE_DBG_WR_DESC_ID_VAL_MASK 0xFFFF
+
+/* PDMA0_CORE_APB_DMA_LBW_BASE */
+#define PDMA0_CORE_APB_DMA_LBW_BASE_VAL_SHIFT 0
+#define PDMA0_CORE_APB_DMA_LBW_BASE_VAL_MASK 0xFFFF
+
+/* PDMA0_CORE_APB_MSTR_IF_LBW_BASE */
+#define PDMA0_CORE_APB_MSTR_IF_LBW_BASE_VAL_SHIFT 0
+#define PDMA0_CORE_APB_MSTR_IF_LBW_BASE_VAL_MASK 0xFFFF
+
+/* PDMA0_CORE_E2E_CRED_ASYNC_CFG */
+#define PDMA0_CORE_E2E_CRED_ASYNC_CFG_Y_X_FORCE_SHIFT 0
+#define PDMA0_CORE_E2E_CRED_ASYNC_CFG_Y_X_FORCE_MASK 0x1FF
+#define PDMA0_CORE_E2E_CRED_ASYNC_CFG_FORCE_EN_SHIFT 9
+#define PDMA0_CORE_E2E_CRED_ASYNC_CFG_FORCE_EN_MASK 0x200
+
+/* PDMA0_CORE_DBG_APB_ENABLER */
+#define PDMA0_CORE_DBG_APB_ENABLER_DIS_SHIFT 0
+#define PDMA0_CORE_DBG_APB_ENABLER_DIS_MASK 0x1
+
+/* PDMA0_CORE_L2H_CMPR_LO */
+#define PDMA0_CORE_L2H_CMPR_LO_VAL_SHIFT 20
+#define PDMA0_CORE_L2H_CMPR_LO_VAL_MASK 0xFFF00000
+
+/* PDMA0_CORE_L2H_CMPR_HI */
+#define PDMA0_CORE_L2H_CMPR_HI_VAL_SHIFT 0
+#define PDMA0_CORE_L2H_CMPR_HI_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_CORE_L2H_MASK_LO */
+#define PDMA0_CORE_L2H_MASK_LO_VAL_SHIFT 20
+#define PDMA0_CORE_L2H_MASK_LO_VAL_MASK 0xFFF00000
+
+/* PDMA0_CORE_L2H_MASK_HI */
+#define PDMA0_CORE_L2H_MASK_HI_VAL_SHIFT 0
+#define PDMA0_CORE_L2H_MASK_HI_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_CORE_IDLE_IND_MASK */
+#define PDMA0_CORE_IDLE_IND_MASK_DESC_SHIFT 0
+#define PDMA0_CORE_IDLE_IND_MASK_DESC_MASK 0x1
+#define PDMA0_CORE_IDLE_IND_MASK_COMP_SHIFT 1
+#define PDMA0_CORE_IDLE_IND_MASK_COMP_MASK 0x2
+#define PDMA0_CORE_IDLE_IND_MASK_INSTAGE_SHIFT 2
+#define PDMA0_CORE_IDLE_IND_MASK_INSTAGE_MASK 0x4
+#define PDMA0_CORE_IDLE_IND_MASK_CORE_SHIFT 3
+#define PDMA0_CORE_IDLE_IND_MASK_CORE_MASK 0x8
+#define PDMA0_CORE_IDLE_IND_MASK_DESC_CNT_STS_SHIFT 8
+#define PDMA0_CORE_IDLE_IND_MASK_DESC_CNT_STS_MASK 0x1F00
+#define PDMA0_CORE_IDLE_IND_MASK_COMP_CNT_STS_SHIFT 16
+#define PDMA0_CORE_IDLE_IND_MASK_COMP_CNT_STS_MASK 0x1F0000
+#define PDMA0_CORE_IDLE_IND_MASK_INSTAGE_EMPTY_SHIFT 24
+#define PDMA0_CORE_IDLE_IND_MASK_INSTAGE_EMPTY_MASK 0x1000000
+#define PDMA0_CORE_IDLE_IND_MASK_CORE_IDLE_STS_SHIFT 25
+#define PDMA0_CORE_IDLE_IND_MASK_CORE_IDLE_STS_MASK 0x2000000
+
+/* PDMA0_CORE_APB_ENABLER */
+#define PDMA0_CORE_APB_ENABLER_DIS_SHIFT 0
+#define PDMA0_CORE_APB_ENABLER_DIS_MASK 0x1
+
+#endif /* ASIC_REG_PDMA0_CORE_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_core_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_core_regs.h
new file mode 100644
index 000000000000..84079b5077e2
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_core_regs.h
@@ -0,0 +1,157 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PDMA0_CORE_REGS_H_
+#define ASIC_REG_PDMA0_CORE_REGS_H_
+
+/*
+ *****************************************
+ *   PDMA0_CORE
+ *   (Prototype: DMA_CORE)
+ *****************************************
+ */
+
+#define mmPDMA0_CORE_CFG_0 0x4C8B000
+
+#define mmPDMA0_CORE_CFG_1 0x4C8B004
+
+#define mmPDMA0_CORE_PROT 0x4C8B008
+
+#define mmPDMA0_CORE_CKG 0x4C8B00C
+
+#define mmPDMA0_CORE_RD_GLBL 0x4C8B07C
+
+#define mmPDMA0_CORE_RD_HBW_MAX_OUTSTAND 0x4C8B080
+
+#define mmPDMA0_CORE_RD_HBW_MAX_SIZE 0x4C8B084
+
+#define mmPDMA0_CORE_RD_HBW_ARCACHE 0x4C8B088
+
+#define mmPDMA0_CORE_RD_HBW_INFLIGHTS 0x4C8B090
+
+#define mmPDMA0_CORE_RD_HBW_RATE_LIM_CFG 0x4C8B094
+
+#define mmPDMA0_CORE_RD_LBW_MAX_OUTSTAND 0x4C8B0C0
+
+#define mmPDMA0_CORE_RD_LBW_MAX_SIZE 0x4C8B0C4
+
+#define mmPDMA0_CORE_RD_LBW_ARCACHE 0x4C8B0C8
+
+#define mmPDMA0_CORE_RD_LBW_INFLIGHTS 0x4C8B0D0
+
+#define mmPDMA0_CORE_RD_LBW_RATE_LIM_CFG 0x4C8B0D4
+
+#define mmPDMA0_CORE_WR_HBW_MAX_OUTSTAND 0x4C8B100
+
+#define mmPDMA0_CORE_WR_HBW_MAX_AWID 0x4C8B104
+
+#define mmPDMA0_CORE_WR_HBW_AWCACHE 0x4C8B108
+
+#define mmPDMA0_CORE_WR_HBW_INFLIGHTS 0x4C8B10C
+
+#define mmPDMA0_CORE_WR_HBW_RATE_LIM_CFG 0x4C8B110
+
+#define mmPDMA0_CORE_WR_LBW_MAX_OUTSTAND 0x4C8B140
+
+#define mmPDMA0_CORE_WR_LBW_MAX_AWID 0x4C8B144
+
+#define mmPDMA0_CORE_WR_LBW_AWCACHE 0x4C8B148
+
+#define mmPDMA0_CORE_WR_LBW_INFLIGHTS 0x4C8B14C
+
+#define mmPDMA0_CORE_WR_LBW_RATE_LIM_CFG 0x4C8B150
+
+#define mmPDMA0_CORE_WR_COMP_MAX_OUTSTAND 0x4C8B180
+
+#define mmPDMA0_CORE_WR_COMP_AWUSER 0x4C8B184
+
+#define mmPDMA0_CORE_ERR_CFG 0x4C8B300
+
+#define mmPDMA0_CORE_ERR_CAUSE 0x4C8B304
+
+#define mmPDMA0_CORE_ERRMSG_ADDR_LO 0x4C8B308
+
+#define mmPDMA0_CORE_ERRMSG_ADDR_HI 0x4C8B30C
+
+#define mmPDMA0_CORE_ERRMSG_WDATA 0x4C8B310
+
+#define mmPDMA0_CORE_STS0 0x4C8B380
+
+#define mmPDMA0_CORE_STS1 0x4C8B384
+
+#define mmPDMA0_CORE_STS_RD_CTX_SEL 0x4C8B400
+
+#define mmPDMA0_CORE_STS_RD_CTX_SIZE 0x4C8B404
+
+#define mmPDMA0_CORE_STS_RD_CTX_BASE_LO 0x4C8B408
+
+#define mmPDMA0_CORE_STS_RD_CTX_BASE_HI 0x4C8B40C
+
+#define mmPDMA0_CORE_STS_RD_CTX_ID 0x4C8B410
+
+#define mmPDMA0_CORE_STS_RD_HB_AXI_ADDR_LO 0x4C8B414
+
+#define mmPDMA0_CORE_STS_RD_HB_AXI_ADDR_HI 0x4C8B418
+
+#define mmPDMA0_CORE_STS_RD_LB_AXI_ADDR 0x4C8B41C
+
+#define mmPDMA0_CORE_STS_WR_CTX_SEL 0x4C8B420
+
+#define mmPDMA0_CORE_STS_WR_CTX_SIZE 0x4C8B424
+
+#define mmPDMA0_CORE_STS_WR_CTX_BASE_LO 0x4C8B428
+
+#define mmPDMA0_CORE_STS_WR_CTX_BASE_HI 0x4C8B42C
+
+#define mmPDMA0_CORE_STS_WR_CTX_ID 0x4C8B430
+
+#define mmPDMA0_CORE_STS_WR_HB_AXI_ADDR_LO 0x4C8B434
+
+#define mmPDMA0_CORE_STS_WR_HB_AXI_ADDR_HI 0x4C8B438
+
+#define mmPDMA0_CORE_STS_WR_LB_AXI_ADDR 0x4C8B43C
+
+#define mmPDMA0_CORE_PWRLP_CFG 0x4C8B700
+
+#define mmPDMA0_CORE_PWRLP_STS 0x4C8B704
+
+#define mmPDMA0_CORE_DBG_DESC_CNT 0x4C8B710
+
+#define mmPDMA0_CORE_DBG_STS 0x4C8B714
+
+#define mmPDMA0_CORE_DBG_BUF_STS 0x4C8B718
+
+#define mmPDMA0_CORE_DBG_RD_DESC_ID 0x4C8B720
+
+#define mmPDMA0_CORE_DBG_WR_DESC_ID 0x4C8B724
+
+#define mmPDMA0_CORE_APB_DMA_LBW_BASE 0x4C8B728
+
+#define mmPDMA0_CORE_APB_MSTR_IF_LBW_BASE 0x4C8B72C
+
+#define mmPDMA0_CORE_E2E_CRED_ASYNC_CFG 0x4C8B730
+
+#define mmPDMA0_CORE_DBG_APB_ENABLER 0x4C8BE1C
+
+#define mmPDMA0_CORE_L2H_CMPR_LO 0x4C8BE20
+
+#define mmPDMA0_CORE_L2H_CMPR_HI 0x4C8BE24
+
+#define mmPDMA0_CORE_L2H_MASK_LO 0x4C8BE28
+
+#define mmPDMA0_CORE_L2H_MASK_HI 0x4C8BE2C
+
+#define mmPDMA0_CORE_IDLE_IND_MASK 0x4C8BE30
+
+#define mmPDMA0_CORE_APB_ENABLER 0x4C8BE34
+
+#endif /* ASIC_REG_PDMA0_CORE_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_core_special_masks.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_core_special_masks.h
new file mode 100644
index 000000000000..15d257e3830e
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_core_special_masks.h
@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PDMA0_CORE_SPECIAL_MASKS_H_
+#define ASIC_REG_PDMA0_CORE_SPECIAL_MASKS_H_
+
+/*
+ *****************************************
+ *   PDMA0_CORE_SPECIAL
+ *   (Prototype: SPECIAL_REGS)
+ *****************************************
+ */
+
+/* PDMA0_CORE_SPECIAL_GLBL_PRIV */
+#define PDMA0_CORE_SPECIAL_GLBL_PRIV_VAL_SHIFT 0
+#define PDMA0_CORE_SPECIAL_GLBL_PRIV_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_CORE_SPECIAL_MEM_GW_DATA */
+#define PDMA0_CORE_SPECIAL_MEM_GW_DATA_VAL_SHIFT 0
+#define PDMA0_CORE_SPECIAL_MEM_GW_DATA_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_CORE_SPECIAL_MEM_GW_REQ */
+#define PDMA0_CORE_SPECIAL_MEM_GW_REQ_ADDR_SHIFT 0
+#define PDMA0_CORE_SPECIAL_MEM_GW_REQ_ADDR_MASK 0x3FFFFF
+#define PDMA0_CORE_SPECIAL_MEM_GW_REQ_MID_SHIFT 22
+#define PDMA0_CORE_SPECIAL_MEM_GW_REQ_MID_MASK 0x3FC00000
+#define PDMA0_CORE_SPECIAL_MEM_GW_REQ_WNR_SHIFT 30
+#define PDMA0_CORE_SPECIAL_MEM_GW_REQ_WNR_MASK 0x40000000
+#define PDMA0_CORE_SPECIAL_MEM_GW_REQ_VLD_SHIFT 31
+#define PDMA0_CORE_SPECIAL_MEM_GW_REQ_VLD_MASK 0x80000000
+
+/* PDMA0_CORE_SPECIAL_MEM_NUMOF */
+#define PDMA0_CORE_SPECIAL_MEM_NUMOF_VAL_SHIFT 0
+#define PDMA0_CORE_SPECIAL_MEM_NUMOF_VAL_MASK 0xFF
+
+/* PDMA0_CORE_SPECIAL_MEM_ECC_SEL */
+#define PDMA0_CORE_SPECIAL_MEM_ECC_SEL_VAL_SHIFT 0
+#define PDMA0_CORE_SPECIAL_MEM_ECC_SEL_VAL_MASK 0xFF
+
+/* PDMA0_CORE_SPECIAL_MEM_ECC_CTL */
+#define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_SERR_INJ_SHIFT 0
+#define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_SERR_INJ_MASK 0x1
+#define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_DERR_INJ_SHIFT 1
+#define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_DERR_INJ_MASK 0x2
+#define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_SERR_CLR_SHIFT 2
+#define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_SERR_CLR_MASK 0x4
+#define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_DERR_CLR_SHIFT 3
+#define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_DERR_CLR_MASK 0x8
+
+/* PDMA0_CORE_SPECIAL_MEM_ECC_ERR_MASK */
+#define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_MASK_SERR_SHIFT 0
+#define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_MASK_SERR_MASK 0x1
+#define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_MASK_DERR_SHIFT 1
+#define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_MASK_DERR_MASK 0x2
+
+/* PDMA0_CORE_SPECIAL_MEM_ECC_GLBL_ERR_MASK */
+#define PDMA0_CORE_SPECIAL_MEM_ECC_GLBL_ERR_MASK_SERR_SHIFT 0
+#define PDMA0_CORE_SPECIAL_MEM_ECC_GLBL_ERR_MASK_SERR_MASK 0x1
+#define PDMA0_CORE_SPECIAL_MEM_ECC_GLBL_ERR_MASK_DERR_SHIFT 1
+#define PDMA0_CORE_SPECIAL_MEM_ECC_GLBL_ERR_MASK_DERR_MASK 0x2
+
+/* PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS */
+#define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS_SYND_SHIFT 0
+#define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS_SYND_MASK 0xFFFF
+#define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS_SERR_SHIFT 16
+#define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS_SERR_MASK 0x10000
+#define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS_DERR_SHIFT 17
+#define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS_DERR_MASK 0x20000
+
+/* PDMA0_CORE_SPECIAL_MEM_ECC_ERR_ADDR */
+#define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_ADDR_VAL_SHIFT 0
+#define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_ADDR_VAL_MASK 0xFFFF
+
+/* PDMA0_CORE_SPECIAL_MEM_RM */
+#define PDMA0_CORE_SPECIAL_MEM_RM_VAL_SHIFT 0
+#define PDMA0_CORE_SPECIAL_MEM_RM_VAL_MASK 0x3FFFFFFF
+
+/* PDMA0_CORE_SPECIAL_GLBL_ERR_MASK */
+#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_PRIV_RD_SHIFT 0
+#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_PRIV_RD_MASK 0x1
+#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_SEC_RD_SHIFT 1
+#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_SEC_RD_MASK 0x2
+#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_UNMAPPED_RD_SHIFT 2
+#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_UNMAPPED_RD_MASK 0x4
+#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_PRIV_WR_SHIFT 3
+#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_PRIV_WR_MASK 0x8
+#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_SEC_WR_SHIFT 4
+#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_SEC_WR_MASK 0x10
+#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_UNMAPPED_WR_SHIFT 5
+#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_UNMAPPED_WR_MASK 0x20
+#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_EXT_SEC_WR_SHIFT 16
+#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_EXT_SEC_WR_MASK 0x10000
+#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_EXT_UNMAPPED_WR_SHIFT 17
+#define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_EXT_UNMAPPED_WR_MASK 0x20000
+
+/* PDMA0_CORE_SPECIAL_GLBL_ERR_ADDR */
+#define PDMA0_CORE_SPECIAL_GLBL_ERR_ADDR_VAL_SHIFT 0
+#define PDMA0_CORE_SPECIAL_GLBL_ERR_ADDR_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE */
+#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD_SHIFT 0
+#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD_MASK 0x1
+#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD_SHIFT 1
+#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD_MASK 0x2
+#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD_SHIFT 2
+#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD_MASK 0x4
+#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR_SHIFT 3
+#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR_MASK 0x8
+#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR_SHIFT 4
+#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR_MASK 0x10
+#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR_SHIFT 5
+#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR_MASK 0x20
+#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR_SHIFT 16
+#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR_MASK 0x10000
+#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR_SHIFT 17
+#define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR_MASK 0x20000
+
+/* PDMA0_CORE_SPECIAL_GLBL_SPARE */
+#define PDMA0_CORE_SPECIAL_GLBL_SPARE_R_SHIFT 0
+#define PDMA0_CORE_SPECIAL_GLBL_SPARE_R_MASK 0xFFFFFFFF
+
+/* PDMA0_CORE_SPECIAL_GLBL_SEC */
+#define PDMA0_CORE_SPECIAL_GLBL_SEC_VAL_SHIFT 0
+#define PDMA0_CORE_SPECIAL_GLBL_SEC_VAL_MASK 0xFFFFFFFF
+
+#endif /* ASIC_REG_PDMA0_CORE_SPECIAL_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_qm_arc_aux_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_qm_arc_aux_regs.h
new file mode 100644
index 000000000000..9b1cb609d134
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_qm_arc_aux_regs.h
@@ -0,0 +1,591 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PDMA0_QM_ARC_AUX_REGS_H_
+#define ASIC_REG_PDMA0_QM_ARC_AUX_REGS_H_
+
+/*
+ *****************************************
+ *   PDMA0_QM_ARC_AUX
+ *   (Prototype: QMAN_ARC_AUX)
+ *****************************************
+ */
+
+#define mmPDMA0_QM_ARC_AUX_RUN_HALT_REQ 0x4C88100
+
+#define mmPDMA0_QM_ARC_AUX_RUN_HALT_ACK 0x4C88104
+
+#define mmPDMA0_QM_ARC_AUX_RST_VEC_ADDR 0x4C88108
+
+#define mmPDMA0_QM_ARC_AUX_DBG_MODE 0x4C8810C
+
+#define mmPDMA0_QM_ARC_AUX_CLUSTER_NUM 0x4C88110
+
+#define mmPDMA0_QM_ARC_AUX_ARC_NUM 0x4C88114
+
+#define mmPDMA0_QM_ARC_AUX_WAKE_UP_EVENT 0x4C88118
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_SYS_ADDR_BASE 0x4C8811C
+
+#define mmPDMA0_QM_ARC_AUX_CTI_AP_STS 0x4C88120
+
+#define mmPDMA0_QM_ARC_AUX_CTI_CFG_MUX_SEL 0x4C88124
+
+#define mmPDMA0_QM_ARC_AUX_ARC_RST 0x4C88128
+
+#define mmPDMA0_QM_ARC_AUX_ARC_RST_REQ 0x4C8812C
+
+#define mmPDMA0_QM_ARC_AUX_SRAM_LSB_ADDR 0x4C88130
+
+#define mmPDMA0_QM_ARC_AUX_SRAM_MSB_ADDR 0x4C88134
+
+#define mmPDMA0_QM_ARC_AUX_PCIE_LSB_ADDR 0x4C88138
+
+#define mmPDMA0_QM_ARC_AUX_PCIE_MSB_ADDR 0x4C8813C
+
+#define mmPDMA0_QM_ARC_AUX_CFG_LSB_ADDR 0x4C88140
+
+#define mmPDMA0_QM_ARC_AUX_CFG_MSB_ADDR 0x4C88144
+
+#define mmPDMA0_QM_ARC_AUX_HBM0_LSB_ADDR 0x4C88150
+
+#define mmPDMA0_QM_ARC_AUX_HBM0_MSB_ADDR 0x4C88154
+
+#define mmPDMA0_QM_ARC_AUX_HBM1_LSB_ADDR 0x4C88158
+
+#define mmPDMA0_QM_ARC_AUX_HBM1_MSB_ADDR 0x4C8815C
+
+#define mmPDMA0_QM_ARC_AUX_HBM2_LSB_ADDR 0x4C88160
+
+#define mmPDMA0_QM_ARC_AUX_HBM2_MSB_ADDR 0x4C88164
+
+#define mmPDMA0_QM_ARC_AUX_HBM3_LSB_ADDR 0x4C88168
+
+#define mmPDMA0_QM_ARC_AUX_HBM3_MSB_ADDR 0x4C8816C
+
+#define mmPDMA0_QM_ARC_AUX_HBM0_OFFSET 0x4C88170
+
+#define mmPDMA0_QM_ARC_AUX_HBM1_OFFSET 0x4C88174
+
+#define mmPDMA0_QM_ARC_AUX_HBM2_OFFSET 0x4C88178
+
+#define mmPDMA0_QM_ARC_AUX_HBM3_OFFSET 0x4C8817C
+
+#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_0 0x4C88180
+
+#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_1 0x4C88184
+
+#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_2 0x4C88188
+
+#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_3 0x4C8818C
+
+#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_4 0x4C88190
+
+#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_5 0x4C88194
+
+#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_6 0x4C88198
+
+#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_0 0x4C8819C
+
+#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_1 0x4C881A0
+
+#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_2 0x4C881A4
+
+#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_3 0x4C881A8
+
+#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_4 0x4C881AC
+
+#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_5 0x4C881B0
+
+#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_6 0x4C881B4
+
+#define mmPDMA0_QM_ARC_AUX_ARC_CBU_AWCACHE_OVR 0x4C881B8
+
+#define mmPDMA0_QM_ARC_AUX_ARC_LBU_AWCACHE_OVR 0x4C881BC
+
+#define mmPDMA0_QM_ARC_AUX_CONTEXT_ID_0 0x4C881C0
+
+#define mmPDMA0_QM_ARC_AUX_CONTEXT_ID_1 0x4C881C4
+
+#define mmPDMA0_QM_ARC_AUX_CONTEXT_ID_2 0x4C881C8
+
+#define mmPDMA0_QM_ARC_AUX_CONTEXT_ID_3 0x4C881CC
+
+#define mmPDMA0_QM_ARC_AUX_CONTEXT_ID_4 0x4C881D0
+
+#define mmPDMA0_QM_ARC_AUX_CONTEXT_ID_5 0x4C881D4
+
+#define mmPDMA0_QM_ARC_AUX_CONTEXT_ID_6 0x4C881D8
+
+#define mmPDMA0_QM_ARC_AUX_CONTEXT_ID_7 0x4C881DC
+
+#define mmPDMA0_QM_ARC_AUX_CID_OFFSET_0 0x4C881E0
+
+#define mmPDMA0_QM_ARC_AUX_CID_OFFSET_1 0x4C881E4
+
+#define mmPDMA0_QM_ARC_AUX_CID_OFFSET_2 0x4C881E8
+
+#define mmPDMA0_QM_ARC_AUX_CID_OFFSET_3 0x4C881EC
+
+#define mmPDMA0_QM_ARC_AUX_CID_OFFSET_4 0x4C881F0
+
+#define mmPDMA0_QM_ARC_AUX_CID_OFFSET_5 0x4C881F4
+
+#define mmPDMA0_QM_ARC_AUX_CID_OFFSET_6 0x4C881F8
+
+#define mmPDMA0_QM_ARC_AUX_CID_OFFSET_7 0x4C881FC
+
+#define mmPDMA0_QM_ARC_AUX_SW_INTR_0 0x4C88200
+
+#define mmPDMA0_QM_ARC_AUX_SW_INTR_1 0x4C88204
+
+#define mmPDMA0_QM_ARC_AUX_SW_INTR_2 0x4C88208
+
+#define mmPDMA0_QM_ARC_AUX_SW_INTR_3 0x4C8820C
+
+#define mmPDMA0_QM_ARC_AUX_SW_INTR_4 0x4C88210
+
+#define mmPDMA0_QM_ARC_AUX_SW_INTR_5 0x4C88214
+
+#define mmPDMA0_QM_ARC_AUX_SW_INTR_6 0x4C88218
+
+#define mmPDMA0_QM_ARC_AUX_SW_INTR_7 0x4C8821C
+
+#define mmPDMA0_QM_ARC_AUX_SW_INTR_8 0x4C88220
+
+#define mmPDMA0_QM_ARC_AUX_SW_INTR_9 0x4C88224
+
+#define mmPDMA0_QM_ARC_AUX_SW_INTR_10 0x4C88228
+
+#define mmPDMA0_QM_ARC_AUX_SW_INTR_11 0x4C8822C
+
+#define mmPDMA0_QM_ARC_AUX_SW_INTR_12 0x4C88230
+
+#define mmPDMA0_QM_ARC_AUX_SW_INTR_13 0x4C88234
+
+#define mmPDMA0_QM_ARC_AUX_SW_INTR_14 0x4C88238
+
+#define mmPDMA0_QM_ARC_AUX_SW_INTR_15 0x4C8823C
+
+#define mmPDMA0_QM_ARC_AUX_IRQ_INTR_MASK_0 0x4C88280
+
+#define mmPDMA0_QM_ARC_AUX_IRQ_INTR_MASK_1 0x4C88284
+
+#define mmPDMA0_QM_ARC_AUX_ARC_SEI_INTR_STS 0x4C88290
+
+#define mmPDMA0_QM_ARC_AUX_ARC_SEI_INTR_CLR 0x4C88294
+
+#define mmPDMA0_QM_ARC_AUX_ARC_SEI_INTR_MASK 0x4C88298
+
+#define mmPDMA0_QM_ARC_AUX_ARC_EXCPTN_CAUSE 0x4C8829C
+
+#define mmPDMA0_QM_ARC_AUX_SEI_INTR_HALT_EN 0x4C882A0
+
+#define mmPDMA0_QM_ARC_AUX_ARC_SEI_INTR_HALT_MASK 0x4C882A4
+
+#define mmPDMA0_QM_ARC_AUX_QMAN_SEI_INTR_HALT_MASK 0x4C882A8
+
+#define mmPDMA0_QM_ARC_AUX_ARC_REI_INTR_STS 0x4C882B0
+
+#define mmPDMA0_QM_ARC_AUX_ARC_REI_INTR_CLR 0x4C882B4
+
+#define mmPDMA0_QM_ARC_AUX_ARC_REI_INTR_MASK 0x4C882B8
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_ECC_ERR_ADDR 0x4C882BC
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_ECC_SYNDROME 0x4C882C0
+
+#define mmPDMA0_QM_ARC_AUX_I_CACHE_ECC_ERR_ADDR 0x4C882C4
+
+#define mmPDMA0_QM_ARC_AUX_I_CACHE_ECC_SYNDROME 0x4C882C8
+
+#define mmPDMA0_QM_ARC_AUX_D_CACHE_ECC_ERR_ADDR 0x4C882CC
+
+#define mmPDMA0_QM_ARC_AUX_D_CACHE_ECC_SYNDROME 0x4C882D0
+
+#define mmPDMA0_QM_ARC_AUX_LBW_TRMINATE_AWADDR_ERR 0x4C882E0
+
+#define mmPDMA0_QM_ARC_AUX_LBW_TRMINATE_ARADDR_ERR 0x4C882E4
+
+#define mmPDMA0_QM_ARC_AUX_CFG_LBW_TERMINATE_BRESP 0x4C882E8
+
+#define mmPDMA0_QM_ARC_AUX_CFG_LBW_TERMINATE_RRESP 0x4C882EC
+
+#define mmPDMA0_QM_ARC_AUX_CFG_LBW_TERMINATE_AXLEN 0x4C882F0
+
+#define mmPDMA0_QM_ARC_AUX_CFG_LBW_TERMINATE_AXSIZE 0x4C882F4
+
+#define mmPDMA0_QM_ARC_AUX_SCRATCHPAD_0 0x4C88300
+
+#define mmPDMA0_QM_ARC_AUX_SCRATCHPAD_1 0x4C88304
+
+#define mmPDMA0_QM_ARC_AUX_SCRATCHPAD_2 0x4C88308
+
+#define mmPDMA0_QM_ARC_AUX_SCRATCHPAD_3 0x4C8830C
+
+#define mmPDMA0_QM_ARC_AUX_SCRATCHPAD_4 0x4C88310
+
+#define mmPDMA0_QM_ARC_AUX_SCRATCHPAD_5 0x4C88314
+
+#define mmPDMA0_QM_ARC_AUX_SCRATCHPAD_6 0x4C88318
+
+#define mmPDMA0_QM_ARC_AUX_SCRATCHPAD_7 0x4C8831C
+
+#define mmPDMA0_QM_ARC_AUX_TOTAL_CBU_WR_CNT 0x4C88320
+
+#define mmPDMA0_QM_ARC_AUX_INFLIGHT_CBU_WR_CNT 0x4C88324
+
+#define mmPDMA0_QM_ARC_AUX_TOTAL_CBU_RD_CNT 0x4C88328
+
+#define mmPDMA0_QM_ARC_AUX_INFLIGHT_CBU_RD_CNT 0x4C8832C
+
+#define mmPDMA0_QM_ARC_AUX_TOTAL_LBU_WR_CNT 0x4C88330
+
+#define mmPDMA0_QM_ARC_AUX_INFLIGHT_LBU_WR_CNT 0x4C88334
+
+#define mmPDMA0_QM_ARC_AUX_TOTAL_LBU_RD_CNT 0x4C88338
+
+#define mmPDMA0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT 0x4C8833C
+
+#define mmPDMA0_QM_ARC_AUX_CBU_ARUSER_OVR 0x4C88350
+
+#define mmPDMA0_QM_ARC_AUX_CBU_ARUSER_OVR_EN 0x4C88354
+
+#define mmPDMA0_QM_ARC_AUX_CBU_AWUSER_OVR 0x4C88358
+
+#define mmPDMA0_QM_ARC_AUX_CBU_AWUSER_OVR_EN 0x4C8835C
+
+#define mmPDMA0_QM_ARC_AUX_CBU_ARUSER_MSB_OVR 0x4C88360
+
+#define mmPDMA0_QM_ARC_AUX_CBU_ARUSER_MSB_OVR_EN 0x4C88364
+
+#define mmPDMA0_QM_ARC_AUX_CBU_AWUSER_MSB_OVR 0x4C88368
+
+#define mmPDMA0_QM_ARC_AUX_CBU_AWUSER_MSB_OVR_EN 0x4C8836C
+
+#define mmPDMA0_QM_ARC_AUX_CBU_AXCACHE_OVR 0x4C88370
+
+#define mmPDMA0_QM_ARC_AUX_CBU_LOCK_OVR 0x4C88374
+
+#define mmPDMA0_QM_ARC_AUX_CBU_PROT_OVR 0x4C88378
+
+#define mmPDMA0_QM_ARC_AUX_CBU_MAX_OUTSTANDING 0x4C8837C
+
+#define mmPDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN 0x4C88380
+
+#define mmPDMA0_QM_ARC_AUX_CBU_FORCE_RSP_OK 0x4C88384
+
+#define mmPDMA0_QM_ARC_AUX_CBU_NO_WR_INFLIGHT 0x4C8838C
+
+#define mmPDMA0_QM_ARC_AUX_CBU_SEI_INTR_ID 0x4C88390
+
+#define mmPDMA0_QM_ARC_AUX_LBU_ARUSER_OVR 0x4C88400
+
+#define mmPDMA0_QM_ARC_AUX_LBU_ARUSER_OVR_EN 0x4C88404
+
+#define mmPDMA0_QM_ARC_AUX_LBU_AWUSER_OVR 0x4C88408
+
+#define mmPDMA0_QM_ARC_AUX_LBU_AWUSER_OVR_EN 0x4C8840C
+
+#define mmPDMA0_QM_ARC_AUX_LBU_AXCACHE_OVR 0x4C88420
+
+#define mmPDMA0_QM_ARC_AUX_LBU_LOCK_OVR 0x4C88424
+
+#define mmPDMA0_QM_ARC_AUX_LBU_PROT_OVR 0x4C88428
+
+#define mmPDMA0_QM_ARC_AUX_LBU_MAX_OUTSTANDING 0x4C8842C
+
+#define mmPDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN 0x4C88430
+
+#define mmPDMA0_QM_ARC_AUX_LBU_FORCE_RSP_OK 0x4C88434
+
+#define mmPDMA0_QM_ARC_AUX_LBU_NO_WR_INFLIGHT 0x4C8843C
+
+#define mmPDMA0_QM_ARC_AUX_LBU_SEI_INTR_ID 0x4C88440
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0 0x4C88500
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_1 0x4C88504
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_2 0x4C88508
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_3 0x4C8850C
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_4 0x4C88510
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_5 0x4C88514
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_6 0x4C88518
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_7 0x4C8851C
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_0 0x4C88520
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_1 0x4C88524
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_2 0x4C88528
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_3 0x4C8852C
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_4 0x4C88530
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_5 0x4C88534
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_6 0x4C88538
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_7 0x4C8853C
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_0 0x4C88540
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_1 0x4C88544
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_2 0x4C88548
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_3 0x4C8854C
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_4 0x4C88550
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_5 0x4C88554
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_6 0x4C88558
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_7 0x4C8855C
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_0 0x4C88560
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_1 0x4C88564
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_2 0x4C88568
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_3 0x4C8856C
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_4 0x4C88570
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_5 0x4C88574
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_6 0x4C88578
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_7 0x4C8857C
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_0 0x4C88580
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_1 0x4C88584
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_2 0x4C88588
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_3 0x4C8858C
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_4 0x4C88590
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_5 0x4C88594
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_6 0x4C88598
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_7 0x4C8859C
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_0 0x4C885A0
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_1 0x4C885A4
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_2 0x4C885A8
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_3 0x4C885AC
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_4 0x4C885B0
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_5 0x4C885B4
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_6 0x4C885B8
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_7 0x4C885BC
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_0 0x4C885C0
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_1 0x4C885C4
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_2 0x4C885C8
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_3 0x4C885CC
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_4 0x4C885D0
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_5 0x4C885D4
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_6 0x4C885D8
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_7 0x4C885DC
+
+#define mmPDMA0_QM_ARC_AUX_GENERAL_Q_VLD_ENTRY_MASK 0x4C885E0
+
+#define mmPDMA0_QM_ARC_AUX_NIC_Q_VLD_ENTRY_MASK 0x4C885E4
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_DROP_EN 0x4C88620
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_WARN_MSG 0x4C88624
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG 0x4C88628
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_GEN_AXI_AWPROT 0x4C88630
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_GEN_AXI_AWUSER 0x4C88634
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_GEN_AXI_AWBURST 0x4C88638
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_GEN_AXI_AWLOCK 0x4C8863C
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_GEN_AXI_AWCACHE 0x4C88640
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_WRR_ARB_WEIGHT 0x4C88644
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_FULL_CFG 0x4C88648
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT 0x4C8864C
+
+#define mmPDMA0_QM_ARC_AUX_QMAN_CQ_IFIFO_SHADOW_CI 0x4C88650
+
+#define mmPDMA0_QM_ARC_AUX_QMAN_ARC_CQ_IFIFO_SHADOW_CI 0x4C88654
+
+#define mmPDMA0_QM_ARC_AUX_QMAN_CQ_SHADOW_CI 0x4C88658
+
+#define mmPDMA0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI 0x4C8865C
+
+#define mmPDMA0_QM_ARC_AUX_AUX2APB_PROT 0x4C88700
+
+#define mmPDMA0_QM_ARC_AUX_LBW_FORK_WIN_EN 0x4C88704
+
+#define mmPDMA0_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR0 0x4C88708
+
+#define mmPDMA0_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK0 0x4C8870C
+
+#define mmPDMA0_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR1 0x4C88710
+
+#define mmPDMA0_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK1 0x4C88714
+
+#define mmPDMA0_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR0 0x4C88718
+
+#define mmPDMA0_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK0 0x4C8871C
+
+#define mmPDMA0_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR1 0x4C88720
+
+#define mmPDMA0_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK1 0x4C88724
+
+#define mmPDMA0_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR0 0x4C88728
+
+#define mmPDMA0_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR1 0x4C8872C
+
+#define mmPDMA0_QM_ARC_AUX_ARC_ACC_ENGS_LBW_FORK_MASK 0x4C88730
+
+#define mmPDMA0_QM_ARC_AUX_ARC_DUP_ENG_LBW_FORK_ADDR 0x4C88734
+
+#define mmPDMA0_QM_ARC_AUX_ARC_ACP_ENG_LBW_FORK_ADDR 0x4C88738
+
+#define mmPDMA0_QM_ARC_AUX_ARC_ACC_ENGS_VIRTUAL_ADDR 0x4C8873C
+
+#define mmPDMA0_QM_ARC_AUX_CBU_FORK_WIN_EN 0x4C88740
+
+#define mmPDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_LSB 0x4C88750
+
+#define mmPDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_MSB 0x4C88754
+
+#define mmPDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_LSB 0x4C88758
+
+#define mmPDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_MSB 0x4C8875C
+
+#define mmPDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_LSB 0x4C88760
+
+#define mmPDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_MSB 0x4C88764
+
+#define mmPDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_LSB 0x4C88768
+
+#define mmPDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_MSB 0x4C8876C
+
+#define mmPDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_LSB 0x4C88770
+
+#define mmPDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_MSB 0x4C88774
+
+#define mmPDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_LSB 0x4C88778
+
+#define mmPDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_MSB 0x4C8877C
+
+#define mmPDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_LSB 0x4C88780
+
+#define mmPDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_MSB 0x4C88784
+
+#define mmPDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_LSB 0x4C88788
+
+#define mmPDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_MSB 0x4C8878C
+
+#define mmPDMA0_QM_ARC_AUX_CBU_TRMINATE_ARADDR_LSB 0x4C88790
+
+#define mmPDMA0_QM_ARC_AUX_CBU_TRMINATE_ARADDR_MSB 0x4C88794
+
+#define mmPDMA0_QM_ARC_AUX_CFG_CBU_TERMINATE_BRESP 0x4C88798
+
+#define mmPDMA0_QM_ARC_AUX_CFG_CBU_TERMINATE_RRESP 0x4C8879C
+
+#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_0 0x4C88800
+
+#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_1 0x4C88804
+
+#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_2 0x4C88808
+
+#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_3 0x4C8880C
+
+#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_4 0x4C88810
+
+#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_5 0x4C88814
+
+#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_6 0x4C88818
+
+#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_7 0x4C8881C
+
+#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_8 0x4C88820
+
+#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_9 0x4C88824
+
+#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_10 0x4C88828
+
+#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_11 0x4C8882C
+
+#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_12 0x4C88830
+
+#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_13 0x4C88834
+
+#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_14 0x4C88838
+
+#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_15 0x4C8883C
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_TRMINATE_AWADDR_ERR 0x4C88840
+
+#define mmPDMA0_QM_ARC_AUX_DCCM_TRMINATE_ARADDR_ERR 0x4C88844
+
+#define mmPDMA0_QM_ARC_AUX_CFG_DCCM_TERMINATE_BRESP 0x4C88848
+
+#define mmPDMA0_QM_ARC_AUX_CFG_DCCM_TERMINATE_RRESP 0x4C8884C
+
+#define mmPDMA0_QM_ARC_AUX_CFG_DCCM_TERMINATE_EN 0x4C88850
+
+#define mmPDMA0_QM_ARC_AUX_CFG_DCCM_SECURE_REGION 0x4C88854
+
+#define mmPDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT 0x4C88900
+
+#define mmPDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_CTL 0x4C88904
+
+#define mmPDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR_MSK 0x4C88908
+
+#define mmPDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR 0x4C8890C
+
+#define mmPDMA0_QM_ARC_AUX_ARC_ACC_ENGS_BUSER 0x4C88910
+
+#define mmPDMA0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN 0x4C88920
+
+#endif /* ASIC_REG_PDMA0_QM_ARC_AUX_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_qm_axuser_nonsecured_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_qm_axuser_nonsecured_regs.h
new file mode 100644
index 000000000000..d2e0756ec5f2
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_qm_axuser_nonsecured_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PDMA0_QM_AXUSER_NONSECURED_REGS_H_
+#define ASIC_REG_PDMA0_QM_AXUSER_NONSECURED_REGS_H_
+
+/*
+ *****************************************
+ *   PDMA0_QM_AXUSER_NONSECURED
+ *   (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define mmPDMA0_QM_AXUSER_NONSECURED_HB_ASID 0x4C8AB80
+
+#define mmPDMA0_QM_AXUSER_NONSECURED_HB_MMU_BP 0x4C8AB84
+
+#define mmPDMA0_QM_AXUSER_NONSECURED_HB_STRONG_ORDER 0x4C8AB88
+
+#define mmPDMA0_QM_AXUSER_NONSECURED_HB_NO_SNOOP 0x4C8AB8C
+
+#define mmPDMA0_QM_AXUSER_NONSECURED_HB_WR_REDUCTION 0x4C8AB90
+
+#define mmPDMA0_QM_AXUSER_NONSECURED_HB_RD_ATOMIC 0x4C8AB94
+
+#define mmPDMA0_QM_AXUSER_NONSECURED_HB_QOS 0x4C8AB98
+
+#define mmPDMA0_QM_AXUSER_NONSECURED_HB_RSVD 0x4C8AB9C
+
+#define mmPDMA0_QM_AXUSER_NONSECURED_HB_EMEM_CPAGE 0x4C8ABA0
+
+#define mmPDMA0_QM_AXUSER_NONSECURED_HB_CORE 0x4C8ABA4
+
+#define mmPDMA0_QM_AXUSER_NONSECURED_E2E_COORD 0x4C8ABA8
+
+#define mmPDMA0_QM_AXUSER_NONSECURED_HB_WR_OVRD_LO 0x4C8ABB0
+
+#define mmPDMA0_QM_AXUSER_NONSECURED_HB_WR_OVRD_HI 0x4C8ABB4
+
+#define mmPDMA0_QM_AXUSER_NONSECURED_HB_RD_OVRD_LO 0x4C8ABB8
+
+#define mmPDMA0_QM_AXUSER_NONSECURED_HB_RD_OVRD_HI 0x4C8ABBC
+
+#define mmPDMA0_QM_AXUSER_NONSECURED_LB_COORD 0x4C8ABC0
+
+#define mmPDMA0_QM_AXUSER_NONSECURED_LB_LOCK 0x4C8ABC4
+
+#define mmPDMA0_QM_AXUSER_NONSECURED_LB_RSVD 0x4C8ABC8
+
+#define mmPDMA0_QM_AXUSER_NONSECURED_LB_OVRD 0x4C8ABCC
+
+#endif /* ASIC_REG_PDMA0_QM_AXUSER_NONSECURED_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_qm_axuser_secured_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_qm_axuser_secured_regs.h
new file mode 100644
index 000000000000..8bf0516b83f7
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_qm_axuser_secured_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PDMA0_QM_AXUSER_SECURED_REGS_H_
+#define ASIC_REG_PDMA0_QM_AXUSER_SECURED_REGS_H_
+
+/*
+ *****************************************
+ *   PDMA0_QM_AXUSER_SECURED
+ *   (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define mmPDMA0_QM_AXUSER_SECURED_HB_ASID 0x4C8AB00
+
+#define mmPDMA0_QM_AXUSER_SECURED_HB_MMU_BP 0x4C8AB04
+
+#define mmPDMA0_QM_AXUSER_SECURED_HB_STRONG_ORDER 0x4C8AB08
+
+#define mmPDMA0_QM_AXUSER_SECURED_HB_NO_SNOOP 0x4C8AB0C
+
+#define mmPDMA0_QM_AXUSER_SECURED_HB_WR_REDUCTION 0x4C8AB10
+
+#define mmPDMA0_QM_AXUSER_SECURED_HB_RD_ATOMIC 0x4C8AB14
+
+#define mmPDMA0_QM_AXUSER_SECURED_HB_QOS 0x4C8AB18
+
+#define mmPDMA0_QM_AXUSER_SECURED_HB_RSVD 0x4C8AB1C
+
+#define mmPDMA0_QM_AXUSER_SECURED_HB_EMEM_CPAGE 0x4C8AB20
+
+#define mmPDMA0_QM_AXUSER_SECURED_HB_CORE 0x4C8AB24
+
+#define mmPDMA0_QM_AXUSER_SECURED_E2E_COORD 0x4C8AB28
+
+#define mmPDMA0_QM_AXUSER_SECURED_HB_WR_OVRD_LO 0x4C8AB30
+
+#define mmPDMA0_QM_AXUSER_SECURED_HB_WR_OVRD_HI 0x4C8AB34
+
+#define mmPDMA0_QM_AXUSER_SECURED_HB_RD_OVRD_LO 0x4C8AB38
+
+#define mmPDMA0_QM_AXUSER_SECURED_HB_RD_OVRD_HI 0x4C8AB3C
+
+#define mmPDMA0_QM_AXUSER_SECURED_LB_COORD 0x4C8AB40
+
+#define mmPDMA0_QM_AXUSER_SECURED_LB_LOCK 0x4C8AB44
+
+#define mmPDMA0_QM_AXUSER_SECURED_LB_RSVD 0x4C8AB48
+
+#define mmPDMA0_QM_AXUSER_SECURED_LB_OVRD 0x4C8AB4C
+
+#endif /* ASIC_REG_PDMA0_QM_AXUSER_SECURED_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_qm_cgm_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_qm_cgm_regs.h
new file mode 100644
index 000000000000..96c0ce176e73
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_qm_cgm_regs.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PDMA0_QM_CGM_REGS_H_
+#define ASIC_REG_PDMA0_QM_CGM_REGS_H_
+
+/*
+ *****************************************
+ *   PDMA0_QM_CGM
+ *   (Prototype: QMAN_CGM)
+ *****************************************
+ */
+
+#define mmPDMA0_QM_CGM_CFG 0x4C8AD80
+
+#define mmPDMA0_QM_CGM_STS 0x4C8AD84
+
+#define mmPDMA0_QM_CGM_CFG1 0x4C8AD88
+
+#endif /* ASIC_REG_PDMA0_QM_CGM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_qm_masks.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_qm_masks.h
new file mode 100644
index 000000000000..b79cae8f5571
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_qm_masks.h
@@ -0,0 +1,1165 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PDMA0_QM_MASKS_H_
+#define ASIC_REG_PDMA0_QM_MASKS_H_
+
+/*
+ *****************************************
+ *   PDMA0_QM
+ *   (Prototype: QMAN)
+ *****************************************
+ */
+
+/* PDMA0_QM_GLBL_CFG0 */
+#define PDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
+#define PDMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
+#define PDMA0_QM_GLBL_CFG0_CQF_EN_SHIFT 4
+#define PDMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
+#define PDMA0_QM_GLBL_CFG0_CP_EN_SHIFT 9
+#define PDMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
+#define PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_SHIFT 14
+#define PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_MASK 0x4000
+
+/* PDMA0_QM_GLBL_CFG1 */
+#define PDMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
+#define PDMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
+#define PDMA0_QM_GLBL_CFG1_CQF_STOP_SHIFT 4
+#define PDMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
+#define PDMA0_QM_GLBL_CFG1_CP_STOP_SHIFT 9
+#define PDMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
+#define PDMA0_QM_GLBL_CFG1_PQF_FLUSH_SHIFT 16
+#define PDMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
+#define PDMA0_QM_GLBL_CFG1_CQF_FLUSH_SHIFT 20
+#define PDMA0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
+#define PDMA0_QM_GLBL_CFG1_CP_FLUSH_SHIFT 25
+#define PDMA0_QM_GLBL_CFG1_CP_FLUSH_MASK 0x3E000000
+
+/* PDMA0_QM_GLBL_CFG2 */
+#define PDMA0_QM_GLBL_CFG2_ARC_CQF_STOP_SHIFT 0
+#define PDMA0_QM_GLBL_CFG2_ARC_CQF_STOP_MASK 0x1
+#define PDMA0_QM_GLBL_CFG2_ARC_CQF_FLUSH_SHIFT 1
+#define PDMA0_QM_GLBL_CFG2_ARC_CQF_FLUSH_MASK 0x2
+#define PDMA0_QM_GLBL_CFG2_ARC_HBW_AWUSER_OVRD_SHIFT 4
+#define PDMA0_QM_GLBL_CFG2_ARC_HBW_AWUSER_OVRD_MASK 0x10
+#define PDMA0_QM_GLBL_CFG2_ARC_HBW_ARUSER_OVRD_SHIFT 5
+#define PDMA0_QM_GLBL_CFG2_ARC_HBW_ARUSER_OVRD_MASK 0x20
+#define PDMA0_QM_GLBL_CFG2_ARC_LBW_AWUSER_OVRD_SHIFT 6
+#define PDMA0_QM_GLBL_CFG2_ARC_LBW_AWUSER_OVRD_MASK 0x40
+#define PDMA0_QM_GLBL_CFG2_ARC_LBW_ARUSER_OVRD_SHIFT 7
+#define PDMA0_QM_GLBL_CFG2_ARC_LBW_ARUSER_OVRD_MASK 0x80
+#define PDMA0_QM_GLBL_CFG2_ARC_HBW_AWPROT_OVRD_SHIFT 8
+#define PDMA0_QM_GLBL_CFG2_ARC_HBW_AWPROT_OVRD_MASK 0x100
+#define PDMA0_QM_GLBL_CFG2_ARC_HBW_ARPROT_OVRD_SHIFT 9
+#define PDMA0_QM_GLBL_CFG2_ARC_HBW_ARPROT_OVRD_MASK 0x200
+#define PDMA0_QM_GLBL_CFG2_ARC_LBW_AWPROT_OVRD_SHIFT 10
+#define PDMA0_QM_GLBL_CFG2_ARC_LBW_AWPROT_OVRD_MASK 0x400
+#define PDMA0_QM_GLBL_CFG2_ARC_LBW_ARPROT_OVRD_SHIFT 11
+#define PDMA0_QM_GLBL_CFG2_ARC_LBW_ARPROT_OVRD_MASK 0x800
+#define PDMA0_QM_GLBL_CFG2_ARC_HBW_AWCACHE_OVRD_SHIFT 12
+#define PDMA0_QM_GLBL_CFG2_ARC_HBW_AWCACHE_OVRD_MASK 0x1000
+#define PDMA0_QM_GLBL_CFG2_ARC_HBW_ARCACHE_OVRD_SHIFT 13
+#define PDMA0_QM_GLBL_CFG2_ARC_HBW_ARCACHE_OVRD_MASK 0x2000
+#define PDMA0_QM_GLBL_CFG2_ARC_LBW_AWCACHE_OVRD_SHIFT 14
+#define PDMA0_QM_GLBL_CFG2_ARC_LBW_AWCACHE_OVRD_MASK 0x4000
+#define PDMA0_QM_GLBL_CFG2_ARC_LBW_ARCACHE_OVRD_SHIFT 15
+#define PDMA0_QM_GLBL_CFG2_ARC_LBW_ARCACHE_OVRD_MASK 0x8000
+#define PDMA0_QM_GLBL_CFG2_ARC_LBW_BUSER_OVRD_SHIFT 16
+#define PDMA0_QM_GLBL_CFG2_ARC_LBW_BUSER_OVRD_MASK 0x10000
+
+/* PDMA0_QM_GLBL_ERR_CFG */
+#define PDMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 0
+#define PDMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0xF
+#define PDMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4
+#define PDMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x1F0
+#define PDMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 9
+#define PDMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x3E00
+#define PDMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 16
+#define PDMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0xF0000
+#define PDMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 20
+#define PDMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x1F00000
+#define PDMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 25
+#define PDMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x3E000000
+#define PDMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT 31
+#define PDMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK 0x80000000
+
+/* PDMA0_QM_GLBL_ERR_CFG1 */
+#define PDMA0_QM_GLBL_ERR_CFG1_CQF_ERR_MSG_EN_SHIFT 0
+#define PDMA0_QM_GLBL_ERR_CFG1_CQF_ERR_MSG_EN_MASK 0x1
+#define PDMA0_QM_GLBL_ERR_CFG1_CQF_STOP_ON_ERR_SHIFT 1
+#define PDMA0_QM_GLBL_ERR_CFG1_CQF_STOP_ON_ERR_MASK 0x2
+#define PDMA0_QM_GLBL_ERR_CFG1_ARC_STOP_ON_ERR_SHIFT 2
+#define PDMA0_QM_GLBL_ERR_CFG1_ARC_STOP_ON_ERR_MASK 0x4
+
+/* PDMA0_QM_GLBL_ERR_ARC_HALT_EN */
+#define PDMA0_QM_GLBL_ERR_ARC_HALT_EN_ERR_IND_SHIFT 0
+#define PDMA0_QM_GLBL_ERR_ARC_HALT_EN_ERR_IND_MASK 0xFFFFFF
+
+/* PDMA0_QM_GLBL_AXCACHE */
+#define PDMA0_QM_GLBL_AXCACHE_HBW_AR_SHIFT 0
+#define PDMA0_QM_GLBL_AXCACHE_HBW_AR_MASK 0xF
+#define PDMA0_QM_GLBL_AXCACHE_HBW_AW_SHIFT 16
+#define PDMA0_QM_GLBL_AXCACHE_HBW_AW_MASK 0xF0000
+#define PDMA0_QM_GLBL_AXCACHE_LBW_AW_SHIFT 20
+#define PDMA0_QM_GLBL_AXCACHE_LBW_AW_MASK 0xF00000
+#define PDMA0_QM_GLBL_AXCACHE_LBW_AR_SHIFT 24
+#define PDMA0_QM_GLBL_AXCACHE_LBW_AR_MASK 0xF000000
+
+/* PDMA0_QM_GLBL_STS0 */
+#define PDMA0_QM_GLBL_STS0_PQF_IDLE_SHIFT 0
+#define PDMA0_QM_GLBL_STS0_PQF_IDLE_MASK 0xF
+#define PDMA0_QM_GLBL_STS0_CQF_IDLE_SHIFT 4
+#define PDMA0_QM_GLBL_STS0_CQF_IDLE_MASK 0x1F0
+#define PDMA0_QM_GLBL_STS0_CP_IDLE_SHIFT 9
+#define PDMA0_QM_GLBL_STS0_CP_IDLE_MASK 0x3E00
+#define PDMA0_QM_GLBL_STS0_PQF_IS_STOP_SHIFT 16
+#define PDMA0_QM_GLBL_STS0_PQF_IS_STOP_MASK 0xF0000
+#define PDMA0_QM_GLBL_STS0_CQF_IS_STOP_SHIFT 20
+#define PDMA0_QM_GLBL_STS0_CQF_IS_STOP_MASK 0x1F00000
+#define PDMA0_QM_GLBL_STS0_CP_IS_STOP_SHIFT 25
+#define PDMA0_QM_GLBL_STS0_CP_IS_STOP_MASK 0x3E000000
+#define PDMA0_QM_GLBL_STS0_ARB_IS_STOP_SHIFT 31
+#define PDMA0_QM_GLBL_STS0_ARB_IS_STOP_MASK 0x80000000
+
+/* PDMA0_QM_GLBL_STS1 */
+#define PDMA0_QM_GLBL_STS1_ARC_CQF_IDLE_SHIFT 0
+#define PDMA0_QM_GLBL_STS1_ARC_CQF_IDLE_MASK 0x1
+#define PDMA0_QM_GLBL_STS1_ARC_CQF_IS_STOP_SHIFT 1
+#define PDMA0_QM_GLBL_STS1_ARC_CQF_IS_STOP_MASK 0x2
+
+/* PDMA0_QM_GLBL_ERR_STS */
+#define PDMA0_QM_GLBL_ERR_STS_PQF_RD_ERR_SHIFT 0
+#define PDMA0_QM_GLBL_ERR_STS_PQF_RD_ERR_MASK 0x1
+#define PDMA0_QM_GLBL_ERR_STS_CQF_RD_ERR_SHIFT 1
+#define PDMA0_QM_GLBL_ERR_STS_CQF_RD_ERR_MASK 0x2
+#define PDMA0_QM_GLBL_ERR_STS_CP_RD_ERR_SHIFT 2
+#define PDMA0_QM_GLBL_ERR_STS_CP_RD_ERR_MASK 0x4
+#define PDMA0_QM_GLBL_ERR_STS_CP_UNDEF_CMD_ERR_SHIFT 3
+#define PDMA0_QM_GLBL_ERR_STS_CP_UNDEF_CMD_ERR_MASK 0x8
+#define PDMA0_QM_GLBL_ERR_STS_CP_STOP_OP_SHIFT 4
+#define PDMA0_QM_GLBL_ERR_STS_CP_STOP_OP_MASK 0x10
+#define PDMA0_QM_GLBL_ERR_STS_CP_MSG_WR_ERR_SHIFT 5
+#define PDMA0_QM_GLBL_ERR_STS_CP_MSG_WR_ERR_MASK 0x20
+#define PDMA0_QM_GLBL_ERR_STS_CP_WREG_ERR_SHIFT 6
+#define PDMA0_QM_GLBL_ERR_STS_CP_WREG_ERR_MASK 0x40
+#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE0_OVF_ERR_SHIFT 8
+#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE0_OVF_ERR_MASK 0x100
+#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE1_OVF_ERR_SHIFT 9
+#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE1_OVF_ERR_MASK 0x200
+#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE2_OVF_ERR_SHIFT 10
+#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE2_OVF_ERR_MASK 0x400
+#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE3_OVF_ERR_SHIFT 11
+#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE3_OVF_ERR_MASK 0x800
+#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE0_UDF_ERR_SHIFT 12
+#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE0_UDF_ERR_MASK 0x1000
+#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE1_UDF_ERR_SHIFT 13
+#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE1_UDF_ERR_MASK 0x2000
+#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE2_UDF_ERR_SHIFT 14
+#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE2_UDF_ERR_MASK 0x4000
+#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE3_UDF_ERR_SHIFT 15
+#define PDMA0_QM_GLBL_ERR_STS_CP_FENCE3_UDF_ERR_MASK 0x8000
+#define PDMA0_QM_GLBL_ERR_STS_CPDMA_UP_OVF_ERR_SHIFT 16
+#define PDMA0_QM_GLBL_ERR_STS_CPDMA_UP_OVF_ERR_MASK 0x10000
+#define PDMA0_QM_GLBL_ERR_STS_PQC_L2H_ERR_SHIFT 17
+#define PDMA0_QM_GLBL_ERR_STS_PQC_L2H_ERR_MASK 0x20000
+#define PDMA0_QM_GLBL_ERR_STS_RSVD_18_24_SHIFT 18
+#define PDMA0_QM_GLBL_ERR_STS_RSVD_18_24_MASK 0x1FC0000
+
+/* PDMA0_QM_GLBL_ERR_STS_4 */
+#define PDMA0_QM_GLBL_ERR_STS_4_RSVD0_SHIFT 0
+#define PDMA0_QM_GLBL_ERR_STS_4_RSVD0_MASK 0x1
+#define PDMA0_QM_GLBL_ERR_STS_4_CQF_RD_ERR_SHIFT 1
+#define PDMA0_QM_GLBL_ERR_STS_4_CQF_RD_ERR_MASK 0x2
+#define PDMA0_QM_GLBL_ERR_STS_4_CP_RD_ERR_SHIFT 2
+#define PDMA0_QM_GLBL_ERR_STS_4_CP_RD_ERR_MASK 0x4
+#define PDMA0_QM_GLBL_ERR_STS_4_CP_UNDEF_CMD_ERR_SHIFT 3
+#define PDMA0_QM_GLBL_ERR_STS_4_CP_UNDEF_CMD_ERR_MASK 0x8
+#define PDMA0_QM_GLBL_ERR_STS_4_CP_STOP_OP_SHIFT 4
+#define PDMA0_QM_GLBL_ERR_STS_4_CP_STOP_OP_MASK 0x10
+#define PDMA0_QM_GLBL_ERR_STS_4_CP_MSG_WR_ERR_SHIFT 5
+#define PDMA0_QM_GLBL_ERR_STS_4_CP_MSG_WR_ERR_MASK 0x20
+#define PDMA0_QM_GLBL_ERR_STS_4_CP_WREG_ERR_SHIFT 6
+#define PDMA0_QM_GLBL_ERR_STS_4_CP_WREG_ERR_MASK 0x40
+#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_OVF_ERR_SHIFT 8
+#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_OVF_ERR_MASK 0x100
+#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_OVF_ERR_SHIFT 9
+#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_OVF_ERR_MASK 0x200
+#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_OVF_ERR_SHIFT 10
+#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_OVF_ERR_MASK 0x400
+#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_OVF_ERR_SHIFT 11
+#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_OVF_ERR_MASK 0x800
+#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_UDF_ERR_SHIFT 12
+#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_UDF_ERR_MASK 0x1000
+#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_UDF_ERR_SHIFT 13
+#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_UDF_ERR_MASK 0x2000
+#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_UDF_ERR_SHIFT 14
+#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_UDF_ERR_MASK 0x4000
+#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_UDF_ERR_SHIFT 15
+#define PDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_UDF_ERR_MASK 0x8000
+#define PDMA0_QM_GLBL_ERR_STS_4_CPDMA_UP_OVF_ERR_SHIFT 16
+#define PDMA0_QM_GLBL_ERR_STS_4_CPDMA_UP_OVF_ERR_MASK 0x10000
+#define PDMA0_QM_GLBL_ERR_STS_4_RSVD17_SHIFT 17
+#define PDMA0_QM_GLBL_ERR_STS_4_RSVD17_MASK 0x20000
+#define PDMA0_QM_GLBL_ERR_STS_4_CQ_WR_IFIFO_CI_ERR_SHIFT 18
+#define PDMA0_QM_GLBL_ERR_STS_4_CQ_WR_IFIFO_CI_ERR_MASK 0x40000
+#define PDMA0_QM_GLBL_ERR_STS_4_CQ_WR_CTL_CI_ERR_SHIFT 19
+#define PDMA0_QM_GLBL_ERR_STS_4_CQ_WR_CTL_CI_ERR_MASK 0x80000
+#define PDMA0_QM_GLBL_ERR_STS_4_ARC_CQF_RD_ERR_SHIFT 20
+#define PDMA0_QM_GLBL_ERR_STS_4_ARC_CQF_RD_ERR_MASK 0x100000
+#define PDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_IFIFO_CI_ERR_SHIFT 21
+#define PDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_IFIFO_CI_ERR_MASK 0x200000
+#define PDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_CTL_CI_ERR_SHIFT 22
+#define PDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_CTL_CI_ERR_MASK 0x400000
+#define PDMA0_QM_GLBL_ERR_STS_4_ARC_AXI_ERR_SHIFT 23
+#define PDMA0_QM_GLBL_ERR_STS_4_ARC_AXI_ERR_MASK 0x800000
+#define PDMA0_QM_GLBL_ERR_STS_4_CP_SWITCH_WDT_ERR_SHIFT 24
+#define PDMA0_QM_GLBL_ERR_STS_4_CP_SWITCH_WDT_ERR_MASK 0x1000000
+
+/* PDMA0_QM_GLBL_ERR_MSG_EN */
+#define PDMA0_QM_GLBL_ERR_MSG_EN_PQF_RD_ERR_SHIFT 0
+#define PDMA0_QM_GLBL_ERR_MSG_EN_PQF_RD_ERR_MASK 0x1
+#define PDMA0_QM_GLBL_ERR_MSG_EN_CQF_RD_ERR_SHIFT 1
+#define PDMA0_QM_GLBL_ERR_MSG_EN_CQF_RD_ERR_MASK 0x2
+#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_RD_ERR_SHIFT 2
+#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_RD_ERR_MASK 0x4
+#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_UNDEF_CMD_ERR_SHIFT 3
+#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_UNDEF_CMD_ERR_MASK 0x8
+#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_STOP_OP_SHIFT 4
+#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_STOP_OP_MASK 0x10
+#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_MSG_WR_ERR_SHIFT 5
+#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_MSG_WR_ERR_MASK 0x20
+#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_WREG_ERR_SHIFT 6
+#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_WREG_ERR_MASK 0x40
+#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_OVF_ERR_SHIFT 8
+#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_OVF_ERR_MASK 0x100
+#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_OVF_ERR_SHIFT 9
+#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_OVF_ERR_MASK 0x200
+#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_OVF_ERR_SHIFT 10
+#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_OVF_ERR_MASK 0x400
+#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_OVF_ERR_SHIFT 11
+#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_OVF_ERR_MASK 0x800
+#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_UDF_ERR_SHIFT 12
+#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_UDF_ERR_MASK 0x1000
+#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_UDF_ERR_SHIFT 13
+#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_UDF_ERR_MASK 0x2000
+#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_UDF_ERR_SHIFT 14
+#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_UDF_ERR_MASK 0x4000
+#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_UDF_ERR_SHIFT 15
+#define PDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_UDF_ERR_MASK 0x8000
+#define PDMA0_QM_GLBL_ERR_MSG_EN_CPDMA_UP_OVF_ERR_SHIFT 16
+#define PDMA0_QM_GLBL_ERR_MSG_EN_CPDMA_UP_OVF_ERR_MASK 0x10000
+#define PDMA0_QM_GLBL_ERR_MSG_EN_PQC_L2H_ERR_SHIFT 17
+#define PDMA0_QM_GLBL_ERR_MSG_EN_PQC_L2H_ERR_MASK 0x20000
+#define PDMA0_QM_GLBL_ERR_MSG_EN_RSVD_18_24_SHIFT 18
+#define PDMA0_QM_GLBL_ERR_MSG_EN_RSVD_18_24_MASK 0x1FC0000
+
+/* PDMA0_QM_GLBL_ERR_MSG_EN_4 */
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD0_SHIFT 0
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD0_MASK 0x1
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CQF_RD_ERR_SHIFT 1
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CQF_RD_ERR_MASK 0x2
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_RD_ERR_SHIFT 2
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_RD_ERR_MASK 0x4
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_UNDEF_CMD_ERR_SHIFT 3
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_UNDEF_CMD_ERR_MASK 0x8
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_STOP_OP_SHIFT 4
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_STOP_OP_MASK 0x10
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_MSG_WR_ERR_SHIFT 5
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_MSG_WR_ERR_MASK 0x20
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_WREG_ERR_SHIFT 6
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_WREG_ERR_MASK 0x40
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_OVF_ERR_SHIFT 8
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_OVF_ERR_MASK 0x100
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_OVF_ERR_SHIFT 9
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_OVF_ERR_MASK 0x200
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_OVF_ERR_SHIFT 10
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_OVF_ERR_MASK 0x400
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_OVF_ERR_SHIFT 11
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_OVF_ERR_MASK 0x800
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_UDF_ERR_SHIFT 12
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_UDF_ERR_MASK 0x1000
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_UDF_ERR_SHIFT 13
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_UDF_ERR_MASK 0x2000
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_UDF_ERR_SHIFT 14
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_UDF_ERR_MASK 0x4000
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_UDF_ERR_SHIFT 15
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_UDF_ERR_MASK 0x8000
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CPDMA_UP_OVF_ERR_SHIFT 16
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CPDMA_UP_OVF_ERR_MASK 0x10000
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD17_SHIFT 17
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD17_MASK 0x20000
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_IFIFO_CI_ERR_SHIFT 18
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_IFIFO_CI_ERR_MASK 0x40000
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_CTL_CI_ERR_SHIFT 19
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_CTL_CI_ERR_MASK 0x80000
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQF_RD_ERR_SHIFT 20
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQF_RD_ERR_MASK 0x100000
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_IFIFO_CI_ERR_SHIFT 21
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_IFIFO_CI_ERR_MASK 0x200000
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_CTL_CI_ERR_SHIFT 22
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_CTL_CI_ERR_MASK 0x400000
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_AXI_ERR_SHIFT 23
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_AXI_ERR_MASK 0x800000
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_SWITCH_WDT_ERR_SHIFT 24
+#define PDMA0_QM_GLBL_ERR_MSG_EN_4_CP_SWITCH_WDT_ERR_MASK 0x1000000
+
+/* PDMA0_QM_GLBL_PROT */
+#define PDMA0_QM_GLBL_PROT_PQF_SHIFT 0
+#define PDMA0_QM_GLBL_PROT_PQF_MASK 0xF
+#define PDMA0_QM_GLBL_PROT_CQF_SHIFT 4
+#define PDMA0_QM_GLBL_PROT_CQF_MASK 0x1F0
+#define PDMA0_QM_GLBL_PROT_CP_SHIFT 9
+#define PDMA0_QM_GLBL_PROT_CP_MASK 0x3E00
+#define PDMA0_QM_GLBL_PROT_ERR_SHIFT 14
+#define PDMA0_QM_GLBL_PROT_ERR_MASK 0x4000
+#define PDMA0_QM_GLBL_PROT_ARB_SHIFT 15
+#define PDMA0_QM_GLBL_PROT_ARB_MASK 0x8000
+#define PDMA0_QM_GLBL_PROT_PQC_SHIFT 16
+#define PDMA0_QM_GLBL_PROT_PQC_MASK 0x10000
+#define PDMA0_QM_GLBL_PROT_CQ_IFIFO_MSG_SHIFT 17
+#define PDMA0_QM_GLBL_PROT_CQ_IFIFO_MSG_MASK 0x20000
+#define PDMA0_QM_GLBL_PROT_ARC_CQ_IFIFO_MSG_SHIFT 18
+#define PDMA0_QM_GLBL_PROT_ARC_CQ_IFIFO_MSG_MASK 0x40000
+#define PDMA0_QM_GLBL_PROT_CQ_CTL_MSG_SHIFT 19
+#define PDMA0_QM_GLBL_PROT_CQ_CTL_MSG_MASK 0x80000
+#define PDMA0_QM_GLBL_PROT_ARC_CQ_CTL_MSG_SHIFT 20
+#define PDMA0_QM_GLBL_PROT_ARC_CQ_CTL_MSG_MASK 0x100000
+#define PDMA0_QM_GLBL_PROT_CP_WR_ARC_SHIFT 21
+#define PDMA0_QM_GLBL_PROT_CP_WR_ARC_MASK 0x200000
+#define PDMA0_QM_GLBL_PROT_ARC_CQF_SHIFT 22
+#define PDMA0_QM_GLBL_PROT_ARC_CQF_MASK 0x400000
+#define PDMA0_QM_GLBL_PROT_ARC_CORE_SHIFT 23
+#define PDMA0_QM_GLBL_PROT_ARC_CORE_MASK 0x800000
+
+/* PDMA0_QM_PQ_BASE_LO */
+#define PDMA0_QM_PQ_BASE_LO_VAL_SHIFT 0
+#define PDMA0_QM_PQ_BASE_LO_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_PQ_BASE_HI */
+#define PDMA0_QM_PQ_BASE_HI_VAL_SHIFT 0
+#define PDMA0_QM_PQ_BASE_HI_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_PQ_SIZE */
+#define PDMA0_QM_PQ_SIZE_VAL_SHIFT 0
+#define PDMA0_QM_PQ_SIZE_VAL_MASK 0x1F
+
+/* PDMA0_QM_PQ_PI */
+#define PDMA0_QM_PQ_PI_VAL_SHIFT 0
+#define PDMA0_QM_PQ_PI_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_PQ_CI */
+#define PDMA0_QM_PQ_CI_VAL_SHIFT 0
+#define PDMA0_QM_PQ_CI_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_PQ_CFG0 */
+#define PDMA0_QM_PQ_CFG0_FORCE_STALL_SHIFT 0
+#define PDMA0_QM_PQ_CFG0_FORCE_STALL_MASK 0x1
+
+/* PDMA0_QM_PQ_CFG1 */
+#define PDMA0_QM_PQ_CFG1_CREDIT_LIM_SHIFT 0
+#define PDMA0_QM_PQ_CFG1_CREDIT_LIM_MASK 0xFF
+#define PDMA0_QM_PQ_CFG1_MAX_INFLIGHT_SHIFT 16
+#define PDMA0_QM_PQ_CFG1_MAX_INFLIGHT_MASK 0xFF0000
+
+/* PDMA0_QM_PQ_STS0 */
+#define PDMA0_QM_PQ_STS0_CREDIT_CNT_SHIFT 0
+#define PDMA0_QM_PQ_STS0_CREDIT_CNT_MASK 0xFF
+#define PDMA0_QM_PQ_STS0_FREE_CNT_SHIFT 8
+#define PDMA0_QM_PQ_STS0_FREE_CNT_MASK 0xFF00
+#define PDMA0_QM_PQ_STS0_INFLIGHT_CNT_SHIFT 16
+#define PDMA0_QM_PQ_STS0_INFLIGHT_CNT_MASK 0xFF0000
+
+/* PDMA0_QM_PQ_STS1 */
+#define PDMA0_QM_PQ_STS1_BUF_EMPTY_SHIFT 0
+#define PDMA0_QM_PQ_STS1_BUF_EMPTY_MASK 0x1
+#define PDMA0_QM_PQ_STS1_BUSY_SHIFT 1
+#define PDMA0_QM_PQ_STS1_BUSY_MASK 0x2
+
+/* PDMA0_QM_CQ_CFG0 */
+#define PDMA0_QM_CQ_CFG0_IF_B2B_EN_SHIFT 0
+#define PDMA0_QM_CQ_CFG0_IF_B2B_EN_MASK 0x1
+#define PDMA0_QM_CQ_CFG0_IF_MSG_EN_SHIFT 1
+#define PDMA0_QM_CQ_CFG0_IF_MSG_EN_MASK 0x2
+#define PDMA0_QM_CQ_CFG0_CTL_MSG_EN_SHIFT 2
+#define PDMA0_QM_CQ_CFG0_CTL_MSG_EN_MASK 0x4
+
+/* PDMA0_QM_CQ_STS0 */
+#define PDMA0_QM_CQ_STS0_CREDIT_CNT_SHIFT 0
+#define PDMA0_QM_CQ_STS0_CREDIT_CNT_MASK 0xFF
+#define PDMA0_QM_CQ_STS0_FREE_CNT_SHIFT 8
+#define PDMA0_QM_CQ_STS0_FREE_CNT_MASK 0xFF00
+#define PDMA0_QM_CQ_STS0_INFLIGHT_CNT_SHIFT 16
+#define PDMA0_QM_CQ_STS0_INFLIGHT_CNT_MASK 0xFF0000
+
+/* PDMA0_QM_CQ_CFG1 */
+#define PDMA0_QM_CQ_CFG1_CREDIT_LIM_SHIFT 0
+#define PDMA0_QM_CQ_CFG1_CREDIT_LIM_MASK 0xFF
+#define PDMA0_QM_CQ_CFG1_MAX_INFLIGHT_SHIFT 16
+#define PDMA0_QM_CQ_CFG1_MAX_INFLIGHT_MASK 0xFF0000
+
+/* PDMA0_QM_CQ_STS1 */
+#define PDMA0_QM_CQ_STS1_BUF_EMPTY_SHIFT 0
+#define PDMA0_QM_CQ_STS1_BUF_EMPTY_MASK 0x1
+#define PDMA0_QM_CQ_STS1_BUSY_SHIFT 1
+#define PDMA0_QM_CQ_STS1_BUSY_MASK 0x2
+
+/* PDMA0_QM_CQ_PTR_LO_0 */
+#define PDMA0_QM_CQ_PTR_LO_0_VAL_SHIFT 0
+#define PDMA0_QM_CQ_PTR_LO_0_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_CQ_PTR_HI_0 */
+#define PDMA0_QM_CQ_PTR_HI_0_VAL_SHIFT 0
+#define PDMA0_QM_CQ_PTR_HI_0_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_CQ_TSIZE_0 */
+#define PDMA0_QM_CQ_TSIZE_0_VAL_SHIFT 0
+#define PDMA0_QM_CQ_TSIZE_0_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_CQ_CTL_0 */
+#define PDMA0_QM_CQ_CTL_0_UP_SHIFT 28
+#define PDMA0_QM_CQ_CTL_0_UP_MASK 0xF0000000
+
+/* PDMA0_QM_CQ_PTR_LO_1 */
+#define PDMA0_QM_CQ_PTR_LO_1_VAL_SHIFT 0
+#define PDMA0_QM_CQ_PTR_LO_1_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_CQ_PTR_HI_1 */
+#define PDMA0_QM_CQ_PTR_HI_1_VAL_SHIFT 0
+#define PDMA0_QM_CQ_PTR_HI_1_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_CQ_TSIZE_1 */
+#define PDMA0_QM_CQ_TSIZE_1_VAL_SHIFT 0
+#define PDMA0_QM_CQ_TSIZE_1_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_CQ_CTL_1 */
+#define PDMA0_QM_CQ_CTL_1_UP_SHIFT 28
+#define PDMA0_QM_CQ_CTL_1_UP_MASK 0xF0000000
+
+/* PDMA0_QM_CQ_PTR_LO_2 */
+#define PDMA0_QM_CQ_PTR_LO_2_VAL_SHIFT 0
+#define PDMA0_QM_CQ_PTR_LO_2_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_CQ_PTR_HI_2 */
+#define PDMA0_QM_CQ_PTR_HI_2_VAL_SHIFT 0
+#define PDMA0_QM_CQ_PTR_HI_2_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_CQ_TSIZE_2 */
+#define PDMA0_QM_CQ_TSIZE_2_VAL_SHIFT 0
+#define PDMA0_QM_CQ_TSIZE_2_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_CQ_CTL_2 */
+#define PDMA0_QM_CQ_CTL_2_UP_SHIFT 28
+#define PDMA0_QM_CQ_CTL_2_UP_MASK 0xF0000000
+
+/* PDMA0_QM_CQ_PTR_LO_3 */
+#define PDMA0_QM_CQ_PTR_LO_3_VAL_SHIFT 0
+#define PDMA0_QM_CQ_PTR_LO_3_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_CQ_PTR_HI_3 */
+#define PDMA0_QM_CQ_PTR_HI_3_VAL_SHIFT 0
+#define PDMA0_QM_CQ_PTR_HI_3_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_CQ_TSIZE_3 */
+#define PDMA0_QM_CQ_TSIZE_3_VAL_SHIFT 0
+#define PDMA0_QM_CQ_TSIZE_3_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_CQ_CTL_3 */
+#define PDMA0_QM_CQ_CTL_3_UP_SHIFT 28
+#define PDMA0_QM_CQ_CTL_3_UP_MASK 0xF0000000
+
+/* PDMA0_QM_CQ_PTR_LO_4 */
+#define PDMA0_QM_CQ_PTR_LO_4_VAL_SHIFT 0
+#define PDMA0_QM_CQ_PTR_LO_4_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_CQ_PTR_HI_4 */
+#define PDMA0_QM_CQ_PTR_HI_4_VAL_SHIFT 0
+#define PDMA0_QM_CQ_PTR_HI_4_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_CQ_TSIZE_4 */
+#define PDMA0_QM_CQ_TSIZE_4_VAL_SHIFT 0
+#define PDMA0_QM_CQ_TSIZE_4_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_CQ_CTL_4 */
+#define PDMA0_QM_CQ_CTL_4_UP_SHIFT 28
+#define PDMA0_QM_CQ_CTL_4_UP_MASK 0xF0000000
+
+/* PDMA0_QM_CQ_TSIZE_STS */
+#define PDMA0_QM_CQ_TSIZE_STS_VAL_SHIFT 0
+#define PDMA0_QM_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_CQ_PTR_LO_STS */
+#define PDMA0_QM_CQ_PTR_LO_STS_VAL_SHIFT 0
+#define PDMA0_QM_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_CQ_PTR_HI_STS */
+#define PDMA0_QM_CQ_PTR_HI_STS_VAL_SHIFT 0
+#define PDMA0_QM_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_CQ_IFIFO_STS */
+#define PDMA0_QM_CQ_IFIFO_STS_CNT_SHIFT 0
+#define PDMA0_QM_CQ_IFIFO_STS_CNT_MASK 0x7
+#define PDMA0_QM_CQ_IFIFO_STS_RDY_SHIFT 4
+#define PDMA0_QM_CQ_IFIFO_STS_RDY_MASK 0x10
+#define PDMA0_QM_CQ_IFIFO_STS_CTL_STALL_SHIFT 8
+#define PDMA0_QM_CQ_IFIFO_STS_CTL_STALL_MASK 0x100
+
+/* PDMA0_QM_CP_MSG_BASE0_ADDR_LO */
+#define PDMA0_QM_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0
+#define PDMA0_QM_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_CP_MSG_BASE0_ADDR_HI */
+#define PDMA0_QM_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0
+#define PDMA0_QM_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_CP_MSG_BASE1_ADDR_LO */
+#define PDMA0_QM_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0
+#define PDMA0_QM_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_CP_MSG_BASE1_ADDR_HI */
+#define PDMA0_QM_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0
+#define PDMA0_QM_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_CP_MSG_BASE2_ADDR_LO */
+#define PDMA0_QM_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0
+#define PDMA0_QM_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_CP_MSG_BASE2_ADDR_HI */
+#define PDMA0_QM_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0
+#define PDMA0_QM_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_CP_MSG_BASE3_ADDR_LO */
+#define PDMA0_QM_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0
+#define PDMA0_QM_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_CP_MSG_BASE3_ADDR_HI */
+#define PDMA0_QM_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0
+#define PDMA0_QM_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_CP_FENCE0_RDATA */
+#define PDMA0_QM_CP_FENCE0_RDATA_INC_VAL_SHIFT 0
+#define PDMA0_QM_CP_FENCE0_RDATA_INC_VAL_MASK 0xF
+
+/* PDMA0_QM_CP_FENCE1_RDATA */
+#define PDMA0_QM_CP_FENCE1_RDATA_INC_VAL_SHIFT 0
+#define PDMA0_QM_CP_FENCE1_RDATA_INC_VAL_MASK 0xF
+
+/* PDMA0_QM_CP_FENCE2_RDATA */
+#define PDMA0_QM_CP_FENCE2_RDATA_INC_VAL_SHIFT 0
+#define PDMA0_QM_CP_FENCE2_RDATA_INC_VAL_MASK 0xF
+
+/* PDMA0_QM_CP_FENCE3_RDATA */
+#define PDMA0_QM_CP_FENCE3_RDATA_INC_VAL_SHIFT 0
+#define PDMA0_QM_CP_FENCE3_RDATA_INC_VAL_MASK 0xF
+
+/* PDMA0_QM_CP_FENCE0_CNT */
+#define PDMA0_QM_CP_FENCE0_CNT_VAL_SHIFT 0
+#define PDMA0_QM_CP_FENCE0_CNT_VAL_MASK 0x3FFF
+
+/* PDMA0_QM_CP_FENCE1_CNT */
+#define PDMA0_QM_CP_FENCE1_CNT_VAL_SHIFT 0
+#define PDMA0_QM_CP_FENCE1_CNT_VAL_MASK 0x3FFF
+
+/* PDMA0_QM_CP_FENCE2_CNT */
+#define PDMA0_QM_CP_FENCE2_CNT_VAL_SHIFT 0
+#define PDMA0_QM_CP_FENCE2_CNT_VAL_MASK 0x3FFF
+
+/* PDMA0_QM_CP_FENCE3_CNT */
+#define PDMA0_QM_CP_FENCE3_CNT_VAL_SHIFT 0
+#define PDMA0_QM_CP_FENCE3_CNT_VAL_MASK 0x3FFF
+
+/* PDMA0_QM_CP_BARRIER_CFG */
+#define PDMA0_QM_CP_BARRIER_CFG_EBGUARD_SHIFT 0
+#define PDMA0_QM_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF
+#define PDMA0_QM_CP_BARRIER_CFG_RBGUARD_SHIFT 16
+#define PDMA0_QM_CP_BARRIER_CFG_RBGUARD_MASK 0xF0000
+
+/* PDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET */
+#define PDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0
+#define PDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFF
+
+/* PDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET */
+#define PDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0
+#define PDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFF
+
+/* PDMA0_QM_CP_LDMA_TSIZE_OFFSET */
+#define PDMA0_QM_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0
+#define PDMA0_QM_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFF
+
+/* PDMA0_QM_CP_CQ_PTR_LO_OFFSET_0 */
+#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_0_VAL_SHIFT 0
+#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_0_VAL_MASK 0xFFFF
+
+/* PDMA0_QM_CP_CQ_PTR_LO_OFFSET_1 */
+#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_1_VAL_SHIFT 0
+#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_1_VAL_MASK 0xFFFF
+
+/* PDMA0_QM_CP_CQ_PTR_LO_OFFSET_2 */
+#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_2_VAL_SHIFT 0
+#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_2_VAL_MASK 0xFFFF
+
+/* PDMA0_QM_CP_CQ_PTR_LO_OFFSET_3 */
+#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_3_VAL_SHIFT 0
+#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_3_VAL_MASK 0xFFFF
+
+/* PDMA0_QM_CP_CQ_PTR_LO_OFFSET_4 */
+#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_4_VAL_SHIFT 0
+#define PDMA0_QM_CP_CQ_PTR_LO_OFFSET_4_VAL_MASK 0xFFFF
+
+/* PDMA0_QM_CP_STS */
+#define PDMA0_QM_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0
+#define PDMA0_QM_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFF
+#define PDMA0_QM_CP_STS_ERDY_SHIFT 8
+#define PDMA0_QM_CP_STS_ERDY_MASK 0x100
+#define PDMA0_QM_CP_STS_SWITCH_EN_SHIFT 9
+#define PDMA0_QM_CP_STS_SWITCH_EN_MASK 0x200
+#define PDMA0_QM_CP_STS_MRDY_SHIFT 10
+#define PDMA0_QM_CP_STS_MRDY_MASK 0x400
+#define PDMA0_QM_CP_STS_SW_STOP_SHIFT 11
+#define PDMA0_QM_CP_STS_SW_STOP_MASK 0x800
+#define PDMA0_QM_CP_STS_FENCE_ID_SHIFT 12
+#define PDMA0_QM_CP_STS_FENCE_ID_MASK 0x3000
+#define PDMA0_QM_CP_STS_FENCE_IN_PROGRESS_SHIFT 14
+#define PDMA0_QM_CP_STS_FENCE_IN_PROGRESS_MASK 0x4000
+#define PDMA0_QM_CP_STS_FENCE_TARGET_SHIFT 16
+#define PDMA0_QM_CP_STS_FENCE_TARGET_MASK 0x3FFF0000
+#define PDMA0_QM_CP_STS_CUR_CQ_SHIFT 30
+#define PDMA0_QM_CP_STS_CUR_CQ_MASK 0x40000000
+
+/* PDMA0_QM_CP_CURRENT_INST_LO */
+#define PDMA0_QM_CP_CURRENT_INST_LO_VAL_SHIFT 0
+#define PDMA0_QM_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_CP_CURRENT_INST_HI */
+#define PDMA0_QM_CP_CURRENT_INST_HI_VAL_SHIFT 0
+#define PDMA0_QM_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_CP_PRED */
+#define PDMA0_QM_CP_PRED_VAL_SHIFT 0
+#define PDMA0_QM_CP_PRED_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_CP_PRED_UPEN */
+#define PDMA0_QM_CP_PRED_UPEN_VAL_SHIFT 0
+#define PDMA0_QM_CP_PRED_UPEN_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_CP_DBG_0 */
+#define PDMA0_QM_CP_DBG_0_CS_SHIFT 0
+#define PDMA0_QM_CP_DBG_0_CS_MASK 0x1F
+#define PDMA0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_SHIFT 5
+#define PDMA0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_MASK 0x20
+#define PDMA0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_SHIFT 6
+#define PDMA0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_MASK 0x40
+#define PDMA0_QM_CP_DBG_0_MREB_STALL_SHIFT 7
+#define PDMA0_QM_CP_DBG_0_MREB_STALL_MASK 0x80
+#define PDMA0_QM_CP_DBG_0_STALL_SHIFT 8
+#define PDMA0_QM_CP_DBG_0_STALL_MASK 0x100
+
+/* PDMA0_QM_CP_CPDMA_UP_CRED */
+#define PDMA0_QM_CP_CPDMA_UP_CRED_TH_SHIFT 0
+#define PDMA0_QM_CP_CPDMA_UP_CRED_TH_MASK 0x3
+#define PDMA0_QM_CP_CPDMA_UP_CRED_VAL_SHIFT 8
+#define PDMA0_QM_CP_CPDMA_UP_CRED_VAL_MASK 0x300
+
+/* PDMA0_QM_CP_IN_DATA_LO */
+#define PDMA0_QM_CP_IN_DATA_LO_VAL_SHIFT 0
+#define PDMA0_QM_CP_IN_DATA_LO_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_CP_IN_DATA_HI */
+#define PDMA0_QM_CP_IN_DATA_HI_VAL_SHIFT 0
+#define PDMA0_QM_CP_IN_DATA_HI_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_PQC_HBW_BASE_LO */
+#define PDMA0_QM_PQC_HBW_BASE_LO_VAL_SHIFT 0
+#define PDMA0_QM_PQC_HBW_BASE_LO_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_PQC_HBW_BASE_HI */
+#define PDMA0_QM_PQC_HBW_BASE_HI_VAL_SHIFT 0
+#define PDMA0_QM_PQC_HBW_BASE_HI_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_PQC_SIZE */
+#define PDMA0_QM_PQC_SIZE_VAL_SHIFT 0
+#define PDMA0_QM_PQC_SIZE_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_PQC_PI */
+#define PDMA0_QM_PQC_PI_VAL_SHIFT 0
+#define PDMA0_QM_PQC_PI_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_PQC_LBW_WDATA */
+#define PDMA0_QM_PQC_LBW_WDATA_VAL_SHIFT 0
+#define PDMA0_QM_PQC_LBW_WDATA_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_PQC_LBW_BASE_LO */
+#define PDMA0_QM_PQC_LBW_BASE_LO_VAL_SHIFT 0
+#define PDMA0_QM_PQC_LBW_BASE_LO_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_PQC_LBW_BASE_HI */
+#define PDMA0_QM_PQC_LBW_BASE_HI_VAL_SHIFT 0
+#define PDMA0_QM_PQC_LBW_BASE_HI_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_PQC_CFG */
+#define PDMA0_QM_PQC_CFG_EN_SHIFT 0
+#define PDMA0_QM_PQC_CFG_EN_MASK 0x1
+#define PDMA0_QM_PQC_CFG_DIRECT_SHIFT 4
+#define PDMA0_QM_PQC_CFG_DIRECT_MASK 0x10
+
+/* PDMA0_QM_PQC_SECURE_PUSH_IND */
+#define PDMA0_QM_PQC_SECURE_PUSH_IND_CP_NUM_SHIFT 0
+#define PDMA0_QM_PQC_SECURE_PUSH_IND_CP_NUM_MASK 0x3
+
+/* PDMA0_QM_ARB_MASK */
+#define PDMA0_QM_ARB_MASK_VAL_SHIFT 0
+#define PDMA0_QM_ARB_MASK_VAL_MASK 0xF
+
+/* PDMA0_QM_ARB_CFG_0 */
+#define PDMA0_QM_ARB_CFG_0_PRIO_TYPE_SHIFT 0
+#define PDMA0_QM_ARB_CFG_0_PRIO_TYPE_MASK 0x1
+#define PDMA0_QM_ARB_CFG_0_IS_MASTER_SHIFT 4
+#define PDMA0_QM_ARB_CFG_0_IS_MASTER_MASK 0x10
+#define PDMA0_QM_ARB_CFG_0_EN_SHIFT 8
+#define PDMA0_QM_ARB_CFG_0_EN_MASK 0x100
+#define PDMA0_QM_ARB_CFG_0_MST_MSG_NOSTALL_SHIFT 9
+#define PDMA0_QM_ARB_CFG_0_MST_MSG_NOSTALL_MASK 0x200
+
+/* PDMA0_QM_ARB_CHOICE_Q_PUSH */
+#define PDMA0_QM_ARB_CHOICE_Q_PUSH_VAL_SHIFT 0
+#define PDMA0_QM_ARB_CHOICE_Q_PUSH_VAL_MASK 0x3
+
+/* PDMA0_QM_ARB_WRR_WEIGHT */
+#define PDMA0_QM_ARB_WRR_WEIGHT_VAL_SHIFT 0
+#define PDMA0_QM_ARB_WRR_WEIGHT_VAL_MASK 0xFF
+
+/* PDMA0_QM_ARB_CFG_1 */
+#define PDMA0_QM_ARB_CFG_1_CLR_SHIFT 0
+#define PDMA0_QM_ARB_CFG_1_CLR_MASK 0x1
+
+/* PDMA0_QM_ARB_MST_AVAIL_CRED */
+#define PDMA0_QM_ARB_MST_AVAIL_CRED_VAL_SHIFT 0
+#define PDMA0_QM_ARB_MST_AVAIL_CRED_VAL_MASK 0x7F
+
+/* PDMA0_QM_ARB_MST_CRED_INC */
+#define PDMA0_QM_ARB_MST_CRED_INC_VAL_SHIFT 0
+#define PDMA0_QM_ARB_MST_CRED_INC_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_ARB_MST_CHOICE_PUSH_OFST */
+#define PDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_VAL_SHIFT 0
+#define PDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST */
+#define PDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_SHIFT 0
+#define PDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_ARB_MST_SLAVE_EN */
+#define PDMA0_QM_ARB_MST_SLAVE_EN_VAL_SHIFT 0
+#define PDMA0_QM_ARB_MST_SLAVE_EN_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_ARB_MST_SLAVE_EN_1 */
+#define PDMA0_QM_ARB_MST_SLAVE_EN_1_VAL_SHIFT 0
+#define PDMA0_QM_ARB_MST_SLAVE_EN_1_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_ARB_SLV_CHOICE_WDT */
+#define PDMA0_QM_ARB_SLV_CHOICE_WDT_VAL_SHIFT 0
+#define PDMA0_QM_ARB_SLV_CHOICE_WDT_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_ARB_SLV_ID */
+#define PDMA0_QM_ARB_SLV_ID_VAL_SHIFT 0
+#define PDMA0_QM_ARB_SLV_ID_VAL_MASK 0x7F
+
+/* PDMA0_QM_ARB_MST_QUIET_PER */
+#define PDMA0_QM_ARB_MST_QUIET_PER_VAL_SHIFT 0
+#define PDMA0_QM_ARB_MST_QUIET_PER_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_ARB_MSG_MAX_INFLIGHT */
+#define PDMA0_QM_ARB_MSG_MAX_INFLIGHT_VAL_SHIFT 0
+#define PDMA0_QM_ARB_MSG_MAX_INFLIGHT_VAL_MASK 0x3F
+
+/* PDMA0_QM_ARB_BASE_LO */
+#define PDMA0_QM_ARB_BASE_LO_VAL_SHIFT 0
+#define PDMA0_QM_ARB_BASE_LO_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_ARB_BASE_HI */
+#define PDMA0_QM_ARB_BASE_HI_VAL_SHIFT 0
+#define PDMA0_QM_ARB_BASE_HI_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_ARB_STATE_STS */
+#define PDMA0_QM_ARB_STATE_STS_VAL_SHIFT 0
+#define PDMA0_QM_ARB_STATE_STS_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_ARB_CHOICE_FULLNESS_STS */
+#define PDMA0_QM_ARB_CHOICE_FULLNESS_STS_VAL_SHIFT 0
+#define PDMA0_QM_ARB_CHOICE_FULLNESS_STS_VAL_MASK 0x7F
+
+/* PDMA0_QM_ARB_MSG_STS */
+#define PDMA0_QM_ARB_MSG_STS_FULL_SHIFT 0
+#define PDMA0_QM_ARB_MSG_STS_FULL_MASK 0x1
+#define PDMA0_QM_ARB_MSG_STS_NO_INFLIGHT_SHIFT 1
+#define PDMA0_QM_ARB_MSG_STS_NO_INFLIGHT_MASK 0x2
+
+/* PDMA0_QM_ARB_SLV_CHOICE_Q_HEAD */
+#define PDMA0_QM_ARB_SLV_CHOICE_Q_HEAD_VAL_SHIFT 0
+#define PDMA0_QM_ARB_SLV_CHOICE_Q_HEAD_VAL_MASK 0x3
+
+/* PDMA0_QM_ARB_ERR_CAUSE */
+#define PDMA0_QM_ARB_ERR_CAUSE_CHOICE_OVF_SHIFT 0
+#define PDMA0_QM_ARB_ERR_CAUSE_CHOICE_OVF_MASK 0x1
+#define PDMA0_QM_ARB_ERR_CAUSE_CHOICE_WDT_SHIFT 1
+#define PDMA0_QM_ARB_ERR_CAUSE_CHOICE_WDT_MASK 0x2
+#define PDMA0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_SHIFT 2
+#define PDMA0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_MASK 0x4
+
+/* PDMA0_QM_ARB_ERR_MSG_EN */
+#define PDMA0_QM_ARB_ERR_MSG_EN_CHOICE_OVF_SHIFT 0
+#define PDMA0_QM_ARB_ERR_MSG_EN_CHOICE_OVF_MASK 0x1
+#define PDMA0_QM_ARB_ERR_MSG_EN_CHOICE_WDT_SHIFT 1
+#define PDMA0_QM_ARB_ERR_MSG_EN_CHOICE_WDT_MASK 0x2
+#define PDMA0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_SHIFT 2
+#define PDMA0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4
+
+/* PDMA0_QM_ARB_ERR_STS_DRP */
+#define PDMA0_QM_ARB_ERR_STS_DRP_VAL_SHIFT 0
+#define PDMA0_QM_ARB_ERR_STS_DRP_VAL_MASK 0x3
+
+/* PDMA0_QM_ARB_MST_CRED_STS */
+#define PDMA0_QM_ARB_MST_CRED_STS_VAL_SHIFT 0
+#define PDMA0_QM_ARB_MST_CRED_STS_VAL_MASK 0x7F
+#define PDMA0_QM_ARB_MST_CRED_STS_IDX_SHIFT 24
+#define PDMA0_QM_ARB_MST_CRED_STS_IDX_MASK 0x1F000000
+
+/* PDMA0_QM_ARB_MST_CRED_STS_1 */
+#define PDMA0_QM_ARB_MST_CRED_STS_1_VAL_SHIFT 0
+#define PDMA0_QM_ARB_MST_CRED_STS_1_VAL_MASK 0x7F
+#define PDMA0_QM_ARB_MST_CRED_STS_1_IDX_SHIFT 24
+#define PDMA0_QM_ARB_MST_CRED_STS_1_IDX_MASK 0x1F000000
+
+/* PDMA0_QM_CSMR_STRICT_PRIO_CFG */
+#define PDMA0_QM_CSMR_STRICT_PRIO_CFG_ARB_TYPE_SHIFT 0
+#define PDMA0_QM_CSMR_STRICT_PRIO_CFG_ARB_TYPE_MASK 0x1
+#define PDMA0_QM_CSMR_STRICT_PRIO_CFG_PER_ENTRY_SHIFT 4
+#define PDMA0_QM_CSMR_STRICT_PRIO_CFG_PER_ENTRY_MASK 0x10
+
+/* PDMA0_QM_ARC_CQ_CFG0 */
+#define PDMA0_QM_ARC_CQ_CFG0_IF_B2B_EN_SHIFT 0
+#define PDMA0_QM_ARC_CQ_CFG0_IF_B2B_EN_MASK 0x1
+#define PDMA0_QM_ARC_CQ_CFG0_IF_MSG_EN_SHIFT 1
+#define PDMA0_QM_ARC_CQ_CFG0_IF_MSG_EN_MASK 0x2
+#define PDMA0_QM_ARC_CQ_CFG0_CTL_MSG_EN_SHIFT 2
+#define PDMA0_QM_ARC_CQ_CFG0_CTL_MSG_EN_MASK 0x4
+
+/* PDMA0_QM_ARC_CQ_CFG1 */
+#define PDMA0_QM_ARC_CQ_CFG1_CREDIT_LIM_SHIFT 0
+#define PDMA0_QM_ARC_CQ_CFG1_CREDIT_LIM_MASK 0xFF
+#define PDMA0_QM_ARC_CQ_CFG1_MAX_INFLIGHT_SHIFT 16
+#define PDMA0_QM_ARC_CQ_CFG1_MAX_INFLIGHT_MASK 0xFF0000
+
+/* PDMA0_QM_ARC_CQ_PTR_LO */
+#define PDMA0_QM_ARC_CQ_PTR_LO_VAL_SHIFT 0
+#define PDMA0_QM_ARC_CQ_PTR_LO_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_ARC_CQ_PTR_HI */
+#define PDMA0_QM_ARC_CQ_PTR_HI_VAL_SHIFT 0
+#define PDMA0_QM_ARC_CQ_PTR_HI_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_ARC_CQ_TSIZE */
+#define PDMA0_QM_ARC_CQ_TSIZE_VAL_SHIFT 0
+#define PDMA0_QM_ARC_CQ_TSIZE_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_ARC_CQ_CTL */
+#define PDMA0_QM_ARC_CQ_CTL_UP_SHIFT 28
+#define PDMA0_QM_ARC_CQ_CTL_UP_MASK 0xF0000000
+
+/* PDMA0_QM_ARC_CQ_IFIFO_STS */
+#define PDMA0_QM_ARC_CQ_IFIFO_STS_CNT_SHIFT 0
+#define PDMA0_QM_ARC_CQ_IFIFO_STS_CNT_MASK 0x7
+#define PDMA0_QM_ARC_CQ_IFIFO_STS_RDY_SHIFT 4
+#define PDMA0_QM_ARC_CQ_IFIFO_STS_RDY_MASK 0x10
+#define PDMA0_QM_ARC_CQ_IFIFO_STS_CTL_STALL_SHIFT 8
+#define PDMA0_QM_ARC_CQ_IFIFO_STS_CTL_STALL_MASK 0x100
+
+/* PDMA0_QM_ARC_CQ_STS0 */
+#define PDMA0_QM_ARC_CQ_STS0_CREDIT_CNT_SHIFT 0
+#define PDMA0_QM_ARC_CQ_STS0_CREDIT_CNT_MASK 0xFF
+#define PDMA0_QM_ARC_CQ_STS0_FREE_CNT_SHIFT 8
+#define PDMA0_QM_ARC_CQ_STS0_FREE_CNT_MASK 0xFF00
+#define PDMA0_QM_ARC_CQ_STS0_INFLIGHT_CNT_SHIFT 16
+#define PDMA0_QM_ARC_CQ_STS0_INFLIGHT_CNT_MASK 0xFF0000
+
+/* PDMA0_QM_ARC_CQ_STS1 */
+#define PDMA0_QM_ARC_CQ_STS1_BUF_EMPTY_SHIFT 0
+#define PDMA0_QM_ARC_CQ_STS1_BUF_EMPTY_MASK 0x1
+#define PDMA0_QM_ARC_CQ_STS1_BUSY_SHIFT 1
+#define PDMA0_QM_ARC_CQ_STS1_BUSY_MASK 0x2
+
+/* PDMA0_QM_ARC_CQ_TSIZE_STS */
+#define PDMA0_QM_ARC_CQ_TSIZE_STS_VAL_SHIFT 0
+#define PDMA0_QM_ARC_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_ARC_CQ_PTR_LO_STS */
+#define PDMA0_QM_ARC_CQ_PTR_LO_STS_VAL_SHIFT 0
+#define PDMA0_QM_ARC_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_ARC_CQ_PTR_HI_STS */
+#define PDMA0_QM_ARC_CQ_PTR_HI_STS_VAL_SHIFT 0
+#define PDMA0_QM_ARC_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_CP_WR_ARC_ADDR_HI */
+#define PDMA0_QM_CP_WR_ARC_ADDR_HI_VAL_SHIFT 0
+#define PDMA0_QM_CP_WR_ARC_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_CP_WR_ARC_ADDR_LO */
+#define PDMA0_QM_CP_WR_ARC_ADDR_LO_VAL_SHIFT 0
+#define PDMA0_QM_CP_WR_ARC_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI */
+#define PDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI_VAL_SHIFT 0
+#define PDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO */
+#define PDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO_VAL_SHIFT 0
+#define PDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI */
+#define PDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI_VAL_SHIFT 0
+#define PDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO */
+#define PDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO_VAL_SHIFT 0
+#define PDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_CQ_IFIFO_MSG_BASE_HI */
+#define PDMA0_QM_CQ_IFIFO_MSG_BASE_HI_VAL_SHIFT 0
+#define PDMA0_QM_CQ_IFIFO_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_CQ_IFIFO_MSG_BASE_LO */
+#define PDMA0_QM_CQ_IFIFO_MSG_BASE_LO_VAL_SHIFT 0
+#define PDMA0_QM_CQ_IFIFO_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_CQ_CTL_MSG_BASE_HI */
+#define PDMA0_QM_CQ_CTL_MSG_BASE_HI_VAL_SHIFT 0
+#define PDMA0_QM_CQ_CTL_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_CQ_CTL_MSG_BASE_LO */
+#define PDMA0_QM_CQ_CTL_MSG_BASE_LO_VAL_SHIFT 0
+#define PDMA0_QM_CQ_CTL_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_ADDR_OVRD */
+#define PDMA0_QM_ADDR_OVRD_IDX_SHIFT 0
+#define PDMA0_QM_ADDR_OVRD_IDX_MASK 0xFF
+
+/* PDMA0_QM_CQ_IFIFO_CI */
+#define PDMA0_QM_CQ_IFIFO_CI_VAL_SHIFT 0
+#define PDMA0_QM_CQ_IFIFO_CI_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_ARC_CQ_IFIFO_CI */
+#define PDMA0_QM_ARC_CQ_IFIFO_CI_VAL_SHIFT 0
+#define PDMA0_QM_ARC_CQ_IFIFO_CI_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_CQ_CTL_CI */
+#define PDMA0_QM_CQ_CTL_CI_VAL_SHIFT 0
+#define PDMA0_QM_CQ_CTL_CI_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_ARC_CQ_CTL_CI */
+#define PDMA0_QM_ARC_CQ_CTL_CI_VAL_SHIFT 0
+#define PDMA0_QM_ARC_CQ_CTL_CI_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_CP_CFG */
+#define PDMA0_QM_CP_CFG_SWITCH_EN_SHIFT 0
+#define PDMA0_QM_CP_CFG_SWITCH_EN_MASK 0x1
+#define PDMA0_QM_CP_CFG_SWITCH_WD_EN_SHIFT 1
+#define PDMA0_QM_CP_CFG_SWITCH_WD_EN_MASK 0x2
+
+/* PDMA0_QM_CP_EXT_SWITCH */
+#define PDMA0_QM_CP_EXT_SWITCH_VAL_SHIFT 0
+#define PDMA0_QM_CP_EXT_SWITCH_VAL_MASK 0x1
+
+/* PDMA0_QM_CP_SWITCH_WD_SET */
+#define PDMA0_QM_CP_SWITCH_WD_SET_VAL_SHIFT 0
+#define PDMA0_QM_CP_SWITCH_WD_SET_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_CP_SWITCH_WD */
+#define PDMA0_QM_CP_SWITCH_WD_VAL_SHIFT 0
+#define PDMA0_QM_CP_SWITCH_WD_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_ARC_LB_ADDR_BASE_LO */
+#define PDMA0_QM_ARC_LB_ADDR_BASE_LO_VAL_SHIFT 0
+#define PDMA0_QM_ARC_LB_ADDR_BASE_LO_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_ARC_LB_ADDR_BASE_HI */
+#define PDMA0_QM_ARC_LB_ADDR_BASE_HI_VAL_SHIFT 0
+#define PDMA0_QM_ARC_LB_ADDR_BASE_HI_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_ENGINE_BASE_ADDR_HI */
+#define PDMA0_QM_ENGINE_BASE_ADDR_HI_VAL_SHIFT 0
+#define PDMA0_QM_ENGINE_BASE_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_ENGINE_BASE_ADDR_LO */
+#define PDMA0_QM_ENGINE_BASE_ADDR_LO_VAL_SHIFT 0
+#define PDMA0_QM_ENGINE_BASE_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_ENGINE_ADDR_RANGE_SIZE */
+#define PDMA0_QM_ENGINE_ADDR_RANGE_SIZE_VAL_SHIFT 0
+#define PDMA0_QM_ENGINE_ADDR_RANGE_SIZE_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI */
+#define PDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI_VAL_SHIFT 0
+#define PDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO */
+#define PDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO_VAL_SHIFT 0
+#define PDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_QM_BASE_ADDR_HI */
+#define PDMA0_QM_QM_BASE_ADDR_HI_VAL_SHIFT 0
+#define PDMA0_QM_QM_BASE_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_QM_BASE_ADDR_LO */
+#define PDMA0_QM_QM_BASE_ADDR_LO_VAL_SHIFT 0
+#define PDMA0_QM_QM_BASE_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_ARC_PQC_SECURE_PUSH_IND */
+#define PDMA0_QM_ARC_PQC_SECURE_PUSH_IND_CP_NUM_SHIFT 0
+#define PDMA0_QM_ARC_PQC_SECURE_PUSH_IND_CP_NUM_MASK 0x3
+
+/* PDMA0_QM_PQC_STS_0 */
+#define PDMA0_QM_PQC_STS_0_COMP_DATA_SHIFT 0
+#define PDMA0_QM_PQC_STS_0_COMP_DATA_MASK 0xFFFF
+#define PDMA0_QM_PQC_STS_0_COMP_OFST_SHIFT 16
+#define PDMA0_QM_PQC_STS_0_COMP_OFST_MASK 0xFFFF0000
+
+/* PDMA0_QM_PQC_STS_1 */
+#define PDMA0_QM_PQC_STS_1_COMP_FIFO_CNTR_SHIFT 0
+#define PDMA0_QM_PQC_STS_1_COMP_FIFO_CNTR_MASK 0xF
+#define PDMA0_QM_PQC_STS_1_COMP_FIFO_EMPTY_SHIFT 4
+#define PDMA0_QM_PQC_STS_1_COMP_FIFO_EMPTY_MASK 0x10
+#define PDMA0_QM_PQC_STS_1_COMP_FIFO_FULL_SHIFT 5
+#define PDMA0_QM_PQC_STS_1_COMP_FIFO_FULL_MASK 0x20
+
+/* PDMA0_QM_SEI_STATUS */
+#define PDMA0_QM_SEI_STATUS_QM_INT_SHIFT 0
+#define PDMA0_QM_SEI_STATUS_QM_INT_MASK 0x1
+#define PDMA0_QM_SEI_STATUS_ARC_INT_SHIFT 1
+#define PDMA0_QM_SEI_STATUS_ARC_INT_MASK 0x2
+
+/* PDMA0_QM_SEI_MASK */
+#define PDMA0_QM_SEI_MASK_QM_INT_SHIFT 0
+#define PDMA0_QM_SEI_MASK_QM_INT_MASK 0x1
+#define PDMA0_QM_SEI_MASK_ARC_INT_SHIFT 1
+#define PDMA0_QM_SEI_MASK_ARC_INT_MASK 0x2
+
+/* PDMA0_QM_GLBL_ERR_ADDR_LO */
+#define PDMA0_QM_GLBL_ERR_ADDR_LO_VAL_SHIFT 0
+#define PDMA0_QM_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_GLBL_ERR_ADDR_HI */
+#define PDMA0_QM_GLBL_ERR_ADDR_HI_VAL_SHIFT 0
+#define PDMA0_QM_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_GLBL_ERR_WDATA */
+#define PDMA0_QM_GLBL_ERR_WDATA_VAL_SHIFT 0
+#define PDMA0_QM_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_L2H_MASK_LO */
+#define PDMA0_QM_L2H_MASK_LO_VAL_SHIFT 20
+#define PDMA0_QM_L2H_MASK_LO_VAL_MASK 0xFFF00000
+
+/* PDMA0_QM_L2H_MASK_HI */
+#define PDMA0_QM_L2H_MASK_HI_VAL_SHIFT 0
+#define PDMA0_QM_L2H_MASK_HI_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_L2H_CMPR_LO */
+#define PDMA0_QM_L2H_CMPR_LO_VAL_SHIFT 20
+#define PDMA0_QM_L2H_CMPR_LO_VAL_MASK 0xFFF00000
+
+/* PDMA0_QM_L2H_CMPR_HI */
+#define PDMA0_QM_L2H_CMPR_HI_VAL_SHIFT 0
+#define PDMA0_QM_L2H_CMPR_HI_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_LOCAL_RANGE_BASE */
+#define PDMA0_QM_LOCAL_RANGE_BASE_VAL_SHIFT 0
+#define PDMA0_QM_LOCAL_RANGE_BASE_VAL_MASK 0xFFFF
+
+/* PDMA0_QM_LOCAL_RANGE_SIZE */
+#define PDMA0_QM_LOCAL_RANGE_SIZE_VAL_SHIFT 0
+#define PDMA0_QM_LOCAL_RANGE_SIZE_VAL_MASK 0xFFFF
+
+/* PDMA0_QM_HBW_RD_RATE_LIM_CFG_1 */
+#define PDMA0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_SHIFT 0
+#define PDMA0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_MASK 0xFF
+#define PDMA0_QM_HBW_RD_RATE_LIM_CFG_1_EN_SHIFT 31
+#define PDMA0_QM_HBW_RD_RATE_LIM_CFG_1_EN_MASK 0x80000000
+
+/* PDMA0_QM_LBW_WR_RATE_LIM_CFG_0 */
+#define PDMA0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0
+#define PDMA0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF
+#define PDMA0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_SHIFT 16
+#define PDMA0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_MASK 0xFF0000
+
+/* PDMA0_QM_LBW_WR_RATE_LIM_CFG_1 */
+#define PDMA0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_SHIFT 0
+#define PDMA0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_MASK 0xFF
+#define PDMA0_QM_LBW_WR_RATE_LIM_CFG_1_EN_SHIFT 31
+#define PDMA0_QM_LBW_WR_RATE_LIM_CFG_1_EN_MASK 0x80000000
+
+/* PDMA0_QM_HBW_RD_RATE_LIM_CFG_0 */
+#define PDMA0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0
+#define PDMA0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF
+#define PDMA0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_SHIFT 16
+#define PDMA0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_MASK 0xFF0000
+
+/* PDMA0_QM_IND_GW_APB_CFG */
+#define PDMA0_QM_IND_GW_APB_CFG_ADDR_SHIFT 0
+#define PDMA0_QM_IND_GW_APB_CFG_ADDR_MASK 0x7FFFFFFF
+#define PDMA0_QM_IND_GW_APB_CFG_CMD_SHIFT 31
+#define PDMA0_QM_IND_GW_APB_CFG_CMD_MASK 0x80000000
+
+/* PDMA0_QM_IND_GW_APB_WDATA */
+#define PDMA0_QM_IND_GW_APB_WDATA_VAL_SHIFT 0
+#define PDMA0_QM_IND_GW_APB_WDATA_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_IND_GW_APB_RDATA */
+#define PDMA0_QM_IND_GW_APB_RDATA_VAL_SHIFT 0
+#define PDMA0_QM_IND_GW_APB_RDATA_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_IND_GW_APB_STATUS */
+#define PDMA0_QM_IND_GW_APB_STATUS_RDY_SHIFT 0
+#define PDMA0_QM_IND_GW_APB_STATUS_RDY_MASK 0x1
+#define PDMA0_QM_IND_GW_APB_STATUS_ERR_SHIFT 1
+#define PDMA0_QM_IND_GW_APB_STATUS_ERR_MASK 0x2
+
+/* PDMA0_QM_PERF_CNT_FREE_LO */
+#define PDMA0_QM_PERF_CNT_FREE_LO_VAL_SHIFT 0
+#define PDMA0_QM_PERF_CNT_FREE_LO_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_PERF_CNT_FREE_HI */
+#define PDMA0_QM_PERF_CNT_FREE_HI_VAL_SHIFT 0
+#define PDMA0_QM_PERF_CNT_FREE_HI_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_PERF_CNT_IDLE_LO */
+#define PDMA0_QM_PERF_CNT_IDLE_LO_VAL_SHIFT 0
+#define PDMA0_QM_PERF_CNT_IDLE_LO_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_PERF_CNT_IDLE_HI */
+#define PDMA0_QM_PERF_CNT_IDLE_HI_VAL_SHIFT 0
+#define PDMA0_QM_PERF_CNT_IDLE_HI_VAL_MASK 0xFFFFFFFF
+
+/* PDMA0_QM_PERF_CNT_CFG */
+#define PDMA0_QM_PERF_CNT_CFG_PQ_MASK_SHIFT 0
+#define PDMA0_QM_PERF_CNT_CFG_PQ_MASK_MASK 0xF
+#define PDMA0_QM_PERF_CNT_CFG_CQ_MASK_SHIFT 8
+#define PDMA0_QM_PERF_CNT_CFG_CQ_MASK_MASK 0x1F00
+#define PDMA0_QM_PERF_CNT_CFG_CP_MASK_SHIFT 16
+#define PDMA0_QM_PERF_CNT_CFG_CP_MASK_MASK 0x1F0000
+#define PDMA0_QM_PERF_CNT_CFG_AGENT_MASK_SHIFT 24
+#define PDMA0_QM_PERF_CNT_CFG_AGENT_MASK_MASK 0x1000000
+#define PDMA0_QM_PERF_CNT_CFG_EN_FREE_SHIFT 30
+#define PDMA0_QM_PERF_CNT_CFG_EN_FREE_MASK 0x40000000
+#define PDMA0_QM_PERF_CNT_CFG_EN_IDLE_SHIFT 31
+#define PDMA0_QM_PERF_CNT_CFG_EN_IDLE_MASK 0x80000000
+
+#endif /* ASIC_REG_PDMA0_QM_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_qm_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_qm_regs.h
new file mode 100644
index 000000000000..77d803c938d4
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_qm_regs.h
@@ -0,0 +1,1057 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PDMA0_QM_REGS_H_
+#define ASIC_REG_PDMA0_QM_REGS_H_
+
+/*
+ *****************************************
+ *   PDMA0_QM
+ *   (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmPDMA0_QM_GLBL_CFG0 0x4C8A000
+
+#define mmPDMA0_QM_GLBL_CFG1 0x4C8A004
+
+#define mmPDMA0_QM_GLBL_CFG2 0x4C8A008
+
+#define mmPDMA0_QM_GLBL_ERR_CFG 0x4C8A00C
+
+#define mmPDMA0_QM_GLBL_ERR_CFG1 0x4C8A010
+
+#define mmPDMA0_QM_GLBL_ERR_ARC_HALT_EN 0x4C8A014
+
+#define mmPDMA0_QM_GLBL_AXCACHE 0x4C8A018
+
+#define mmPDMA0_QM_GLBL_STS0 0x4C8A01C
+
+#define mmPDMA0_QM_GLBL_STS1 0x4C8A020
+
+#define mmPDMA0_QM_GLBL_ERR_STS_0 0x4C8A024
+
+#define mmPDMA0_QM_GLBL_ERR_STS_1 0x4C8A028
+
+#define mmPDMA0_QM_GLBL_ERR_STS_2 0x4C8A02C
+
+#define mmPDMA0_QM_GLBL_ERR_STS_3 0x4C8A030
+
+#define mmPDMA0_QM_GLBL_ERR_STS_4 0x4C8A034
+
+#define mmPDMA0_QM_GLBL_ERR_MSG_EN_0 0x4C8A038
+
+#define mmPDMA0_QM_GLBL_ERR_MSG_EN_1 0x4C8A03C
+
+#define mmPDMA0_QM_GLBL_ERR_MSG_EN_2 0x4C8A040
+
+#define mmPDMA0_QM_GLBL_ERR_MSG_EN_3 0x4C8A044
+
+#define mmPDMA0_QM_GLBL_ERR_MSG_EN_4 0x4C8A048
+
+#define mmPDMA0_QM_GLBL_PROT 0x4C8A04C
+
+#define mmPDMA0_QM_PQ_BASE_LO_0 0x4C8A050
+
+#define mmPDMA0_QM_PQ_BASE_LO_1 0x4C8A054
+
+#define mmPDMA0_QM_PQ_BASE_LO_2 0x4C8A058
+
+#define mmPDMA0_QM_PQ_BASE_LO_3 0x4C8A05C
+
+#define mmPDMA0_QM_PQ_BASE_HI_0 0x4C8A060
+
+#define mmPDMA0_QM_PQ_BASE_HI_1 0x4C8A064
+
+#define mmPDMA0_QM_PQ_BASE_HI_2 0x4C8A068
+
+#define mmPDMA0_QM_PQ_BASE_HI_3 0x4C8A06C
+
+#define mmPDMA0_QM_PQ_SIZE_0 0x4C8A070
+
+#define mmPDMA0_QM_PQ_SIZE_1 0x4C8A074
+
+#define mmPDMA0_QM_PQ_SIZE_2 0x4C8A078
+
+#define mmPDMA0_QM_PQ_SIZE_3 0x4C8A07C
+
+#define mmPDMA0_QM_PQ_PI_0 0x4C8A080
+
+#define mmPDMA0_QM_PQ_PI_1 0x4C8A084
+
+#define mmPDMA0_QM_PQ_PI_2 0x4C8A088
+
+#define mmPDMA0_QM_PQ_PI_3 0x4C8A08C
+
+#define mmPDMA0_QM_PQ_CI_0 0x4C8A090
+
+#define mmPDMA0_QM_PQ_CI_1 0x4C8A094
+
+#define mmPDMA0_QM_PQ_CI_2 0x4C8A098
+
+#define mmPDMA0_QM_PQ_CI_3 0x4C8A09C
+
+#define mmPDMA0_QM_PQ_CFG0_0 0x4C8A0A0
+
+#define mmPDMA0_QM_PQ_CFG0_1 0x4C8A0A4
+
+#define mmPDMA0_QM_PQ_CFG0_2 0x4C8A0A8
+
+#define mmPDMA0_QM_PQ_CFG0_3 0x4C8A0AC
+
+#define mmPDMA0_QM_PQ_CFG1_0 0x4C8A0B0
+
+#define mmPDMA0_QM_PQ_CFG1_1 0x4C8A0B4
+
+#define mmPDMA0_QM_PQ_CFG1_2 0x4C8A0B8
+
+#define mmPDMA0_QM_PQ_CFG1_3 0x4C8A0BC
+
+#define mmPDMA0_QM_PQ_STS0_0 0x4C8A0C0
+
+#define mmPDMA0_QM_PQ_STS0_1 0x4C8A0C4
+
+#define mmPDMA0_QM_PQ_STS0_2 0x4C8A0C8
+
+#define mmPDMA0_QM_PQ_STS0_3 0x4C8A0CC
+
+#define mmPDMA0_QM_PQ_STS1_0 0x4C8A0D0
+
+#define mmPDMA0_QM_PQ_STS1_1 0x4C8A0D4
+
+#define mmPDMA0_QM_PQ_STS1_2 0x4C8A0D8
+
+#define mmPDMA0_QM_PQ_STS1_3 0x4C8A0DC
+
+#define mmPDMA0_QM_CQ_CFG0_0 0x4C8A0E0
+
+#define mmPDMA0_QM_CQ_CFG0_1 0x4C8A0E4
+
+#define mmPDMA0_QM_CQ_CFG0_2 0x4C8A0E8
+
+#define mmPDMA0_QM_CQ_CFG0_3 0x4C8A0EC
+
+#define mmPDMA0_QM_CQ_CFG0_4 0x4C8A0F0
+
+#define mmPDMA0_QM_CQ_STS0_0 0x4C8A0F4
+
+#define mmPDMA0_QM_CQ_STS0_1 0x4C8A0F8
+
+#define mmPDMA0_QM_CQ_STS0_2 0x4C8A0FC
+
+#define mmPDMA0_QM_CQ_STS0_3 0x4C8A100
+
+#define mmPDMA0_QM_CQ_STS0_4 0x4C8A104
+
+#define mmPDMA0_QM_CQ_CFG1_0 0x4C8A108
+
+#define mmPDMA0_QM_CQ_CFG1_1 0x4C8A10C
+
+#define mmPDMA0_QM_CQ_CFG1_2 0x4C8A110
+
+#define mmPDMA0_QM_CQ_CFG1_3 0x4C8A114
+
+#define mmPDMA0_QM_CQ_CFG1_4 0x4C8A118
+
+#define mmPDMA0_QM_CQ_STS1_0 0x4C8A11C
+
+#define mmPDMA0_QM_CQ_STS1_1 0x4C8A120
+
+#define mmPDMA0_QM_CQ_STS1_2 0x4C8A124
+
+#define mmPDMA0_QM_CQ_STS1_3 0x4C8A128
+
+#define mmPDMA0_QM_CQ_STS1_4 0x4C8A12C
+
+#define mmPDMA0_QM_CQ_PTR_LO_0 0x4C8A150
+
+#define mmPDMA0_QM_CQ_PTR_HI_0 0x4C8A154
+
+#define mmPDMA0_QM_CQ_TSIZE_0 0x4C8A158
+
+#define mmPDMA0_QM_CQ_CTL_0 0x4C8A15C
+
+#define mmPDMA0_QM_CQ_PTR_LO_1 0x4C8A160
+
+#define mmPDMA0_QM_CQ_PTR_HI_1 0x4C8A164
+
+#define mmPDMA0_QM_CQ_TSIZE_1 0x4C8A168
+
+#define mmPDMA0_QM_CQ_CTL_1 0x4C8A16C
+
+#define mmPDMA0_QM_CQ_PTR_LO_2 0x4C8A170
+
+#define mmPDMA0_QM_CQ_PTR_HI_2 0x4C8A174
+
+#define mmPDMA0_QM_CQ_TSIZE_2 0x4C8A178
+
+#define mmPDMA0_QM_CQ_CTL_2 0x4C8A17C
+
+#define mmPDMA0_QM_CQ_PTR_LO_3 0x4C8A180
+
+#define mmPDMA0_QM_CQ_PTR_HI_3 0x4C8A184
+
+#define mmPDMA0_QM_CQ_TSIZE_3 0x4C8A188
+
+#define mmPDMA0_QM_CQ_CTL_3 0x4C8A18C
+
+#define mmPDMA0_QM_CQ_PTR_LO_4 0x4C8A190
+
+#define mmPDMA0_QM_CQ_PTR_HI_4 0x4C8A194
+
+#define mmPDMA0_QM_CQ_TSIZE_4 0x4C8A198
+
+#define mmPDMA0_QM_CQ_CTL_4 0x4C8A19C
+
+#define mmPDMA0_QM_CQ_TSIZE_STS_0 0x4C8A1A0
+
+#define mmPDMA0_QM_CQ_TSIZE_STS_1 0x4C8A1A4
+
+#define mmPDMA0_QM_CQ_TSIZE_STS_2 0x4C8A1A8
+
+#define mmPDMA0_QM_CQ_TSIZE_STS_3 0x4C8A1AC
+
+#define mmPDMA0_QM_CQ_TSIZE_STS_4 0x4C8A1B0
+
+#define mmPDMA0_QM_CQ_PTR_LO_STS_0 0x4C8A1B4
+
+#define mmPDMA0_QM_CQ_PTR_LO_STS_1 0x4C8A1B8
+
+#define mmPDMA0_QM_CQ_PTR_LO_STS_2 0x4C8A1BC
+
+#define mmPDMA0_QM_CQ_PTR_LO_STS_3 0x4C8A1C0
+
+#define mmPDMA0_QM_CQ_PTR_LO_STS_4 0x4C8A1C4
+
+#define mmPDMA0_QM_CQ_PTR_HI_STS_0 0x4C8A1C8
+
+#define mmPDMA0_QM_CQ_PTR_HI_STS_1 0x4C8A1CC
+
+#define mmPDMA0_QM_CQ_PTR_HI_STS_2 0x4C8A1D0
+
+#define mmPDMA0_QM_CQ_PTR_HI_STS_3 0x4C8A1D4
+
+#define mmPDMA0_QM_CQ_PTR_HI_STS_4 0x4C8A1D8
+
+#define mmPDMA0_QM_CQ_IFIFO_STS_0 0x4C8A1DC
+
+#define mmPDMA0_QM_CQ_IFIFO_STS_1 0x4C8A1E0
+
+#define mmPDMA0_QM_CQ_IFIFO_STS_2 0x4C8A1E4
+
+#define mmPDMA0_QM_CQ_IFIFO_STS_3 0x4C8A1E8
+
+#define mmPDMA0_QM_CQ_IFIFO_STS_4 0x4C8A1EC
+
+#define mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 0x4C8A1F0
+
+#define mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_1 0x4C8A1F4
+
+#define mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_2 0x4C8A1F8
+
+#define mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_3 0x4C8A1FC
+
+#define mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_4 0x4C8A200
+
+#define mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 0x4C8A204
+
+#define mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_1 0x4C8A208
+
+#define mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_2 0x4C8A20C
+
+#define mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_3 0x4C8A210
+
+#define mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_4 0x4C8A214
+
+#define mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 0x4C8A218
+
+#define mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_1 0x4C8A21C
+
+#define mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_2 0x4C8A220
+
+#define mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_3 0x4C8A224
+
+#define mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_4 0x4C8A228
+
+#define mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 0x4C8A22C
+
+#define mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_1 0x4C8A230
+
+#define mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_2 0x4C8A234
+
+#define mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_3 0x4C8A238
+
+#define mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_4 0x4C8A23C
+
+#define mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_0 0x4C8A240
+
+#define mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_1 0x4C8A244
+
+#define mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_2 0x4C8A248
+
+#define mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_3 0x4C8A24C
+
+#define mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_4 0x4C8A250
+
+#define mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_0 0x4C8A254
+
+#define mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_1 0x4C8A258
+
+#define mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_2 0x4C8A25C
+
+#define mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_3 0x4C8A260
+
+#define mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_4 0x4C8A264
+
+#define mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_0 0x4C8A268
+
+#define mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_1 0x4C8A26C
+
+#define mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_2 0x4C8A270
+
+#define mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_3 0x4C8A274
+
+#define mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_4 0x4C8A278
+
+#define mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_0 0x4C8A27C
+
+#define mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_1 0x4C8A280
+
+#define mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_2 0x4C8A284
+
+#define mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_3 0x4C8A288
+
+#define mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_4 0x4C8A28C
+
+#define mmPDMA0_QM_CP_FENCE0_RDATA_0 0x4C8A290
+
+#define mmPDMA0_QM_CP_FENCE0_RDATA_1 0x4C8A294
+
+#define mmPDMA0_QM_CP_FENCE0_RDATA_2 0x4C8A298
+
+#define mmPDMA0_QM_CP_FENCE0_RDATA_3 0x4C8A29C
+
+#define mmPDMA0_QM_CP_FENCE0_RDATA_4 0x4C8A2A0
+
+#define mmPDMA0_QM_CP_FENCE1_RDATA_0 0x4C8A2A4
+
+#define mmPDMA0_QM_CP_FENCE1_RDATA_1 0x4C8A2A8
+
+#define mmPDMA0_QM_CP_FENCE1_RDATA_2 0x4C8A2AC
+
+#define mmPDMA0_QM_CP_FENCE1_RDATA_3 0x4C8A2B0
+
+#define mmPDMA0_QM_CP_FENCE1_RDATA_4 0x4C8A2B4
+
+#define mmPDMA0_QM_CP_FENCE2_RDATA_0 0x4C8A2B8
+
+#define mmPDMA0_QM_CP_FENCE2_RDATA_1 0x4C8A2BC
+
+#define mmPDMA0_QM_CP_FENCE2_RDATA_2 0x4C8A2C0
+
+#define mmPDMA0_QM_CP_FENCE2_RDATA_3 0x4C8A2C4
+
+#define mmPDMA0_QM_CP_FENCE2_RDATA_4 0x4C8A2C8
+
+#define mmPDMA0_QM_CP_FENCE3_RDATA_0 0x4C8A2CC
+
+#define mmPDMA0_QM_CP_FENCE3_RDATA_1 0x4C8A2D0
+
+#define mmPDMA0_QM_CP_FENCE3_RDATA_2 0x4C8A2D4
+
+#define mmPDMA0_QM_CP_FENCE3_RDATA_3 0x4C8A2D8
+
+#define mmPDMA0_QM_CP_FENCE3_RDATA_4 0x4C8A2DC
+
+#define mmPDMA0_QM_CP_FENCE0_CNT_0 0x4C8A2E0
+
+#define mmPDMA0_QM_CP_FENCE0_CNT_1 0x4C8A2E4
+
+#define mmPDMA0_QM_CP_FENCE0_CNT_2 0x4C8A2E8
+
+#define mmPDMA0_QM_CP_FENCE0_CNT_3 0x4C8A2EC
+
+#define mmPDMA0_QM_CP_FENCE0_CNT_4 0x4C8A2F0
+
+#define mmPDMA0_QM_CP_FENCE1_CNT_0 0x4C8A2F4
+
+#define mmPDMA0_QM_CP_FENCE1_CNT_1 0x4C8A2F8
+
+#define mmPDMA0_QM_CP_FENCE1_CNT_2 0x4C8A2FC
+
+#define mmPDMA0_QM_CP_FENCE1_CNT_3 0x4C8A300
+
+#define mmPDMA0_QM_CP_FENCE1_CNT_4 0x4C8A304
+
+#define mmPDMA0_QM_CP_FENCE2_CNT_0 0x4C8A308
+
+#define mmPDMA0_QM_CP_FENCE2_CNT_1 0x4C8A30C
+
+#define mmPDMA0_QM_CP_FENCE2_CNT_2 0x4C8A310
+
+#define mmPDMA0_QM_CP_FENCE2_CNT_3 0x4C8A314
+
+#define mmPDMA0_QM_CP_FENCE2_CNT_4 0x4C8A318
+
+#define mmPDMA0_QM_CP_FENCE3_CNT_0 0x4C8A31C
+
+#define mmPDMA0_QM_CP_FENCE3_CNT_1 0x4C8A320
+
+#define mmPDMA0_QM_CP_FENCE3_CNT_2 0x4C8A324
+
+#define mmPDMA0_QM_CP_FENCE3_CNT_3 0x4C8A328
+
+#define mmPDMA0_QM_CP_FENCE3_CNT_4 0x4C8A32C
+
+#define mmPDMA0_QM_CP_BARRIER_CFG 0x4C8A330
+
+#define mmPDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0x4C8A334
+
+#define mmPDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET 0x4C8A338
+
+#define mmPDMA0_QM_CP_LDMA_TSIZE_OFFSET 0x4C8A33C
+
+#define mmPDMA0_QM_CP_CQ_PTR_LO_OFFSET_0 0x4C8A340
+
+#define mmPDMA0_QM_CP_CQ_PTR_LO_OFFSET_1 0x4C8A344
+
+#define mmPDMA0_QM_CP_CQ_PTR_LO_OFFSET_2 0x4C8A348
+
+#define mmPDMA0_QM_CP_CQ_PTR_LO_OFFSET_3 0x4C8A34C
+
+#define mmPDMA0_QM_CP_CQ_PTR_LO_OFFSET_4 0x4C8A350
+
+#define mmPDMA0_QM_CP_STS_0 0x4C8A368
+
+#define mmPDMA0_QM_CP_STS_1 0x4C8A36C
+
+#define mmPDMA0_QM_CP_STS_2 0x4C8A370
+
+#define mmPDMA0_QM_CP_STS_3 0x4C8A374
+
+#define mmPDMA0_QM_CP_STS_4 0x4C8A378
+
+#define mmPDMA0_QM_CP_CURRENT_INST_LO_0 0x4C8A37C
+
+#define mmPDMA0_QM_CP_CURRENT_INST_LO_1 0x4C8A380
+
+#define mmPDMA0_QM_CP_CURRENT_INST_LO_2 0x4C8A384
+
+#define mmPDMA0_QM_CP_CURRENT_INST_LO_3 0x4C8A388
+
+#define mmPDMA0_QM_CP_CURRENT_INST_LO_4 0x4C8A38C
+
+#define mmPDMA0_QM_CP_CURRENT_INST_HI_0 0x4C8A390
+
+#define mmPDMA0_QM_CP_CURRENT_INST_HI_1 0x4C8A394
+
+#define mmPDMA0_QM_CP_CURRENT_INST_HI_2 0x4C8A398
+
+#define mmPDMA0_QM_CP_CURRENT_INST_HI_3 0x4C8A39C
+
+#define mmPDMA0_QM_CP_CURRENT_INST_HI_4 0x4C8A3A0
+
+#define mmPDMA0_QM_CP_PRED_0 0x4C8A3A4
+
+#define mmPDMA0_QM_CP_PRED_1 0x4C8A3A8
+
+#define mmPDMA0_QM_CP_PRED_2 0x4C8A3AC
+
+#define mmPDMA0_QM_CP_PRED_3 0x4C8A3B0
+
+#define mmPDMA0_QM_CP_PRED_4 0x4C8A3B4
+
+#define mmPDMA0_QM_CP_PRED_UPEN_0 0x4C8A3B8
+
+#define mmPDMA0_QM_CP_PRED_UPEN_1 0x4C8A3BC
+
+#define mmPDMA0_QM_CP_PRED_UPEN_2 0x4C8A3C0
+
+#define mmPDMA0_QM_CP_PRED_UPEN_3 0x4C8A3C4
+
+#define mmPDMA0_QM_CP_PRED_UPEN_4 0x4C8A3C8
+
+#define mmPDMA0_QM_CP_DBG_0_0 0x4C8A3CC
+
+#define mmPDMA0_QM_CP_DBG_0_1 0x4C8A3D0
+
+#define mmPDMA0_QM_CP_DBG_0_2 0x4C8A3D4
+
+#define mmPDMA0_QM_CP_DBG_0_3 0x4C8A3D8
+
+#define mmPDMA0_QM_CP_DBG_0_4 0x4C8A3DC
+
+#define mmPDMA0_QM_CP_CPDMA_UP_CRED_0 0x4C8A3E0
+
+#define mmPDMA0_QM_CP_CPDMA_UP_CRED_1 0x4C8A3E4
+
+#define mmPDMA0_QM_CP_CPDMA_UP_CRED_2 0x4C8A3E8
+
+#define mmPDMA0_QM_CP_CPDMA_UP_CRED_3 0x4C8A3EC
+
+#define mmPDMA0_QM_CP_CPDMA_UP_CRED_4 0x4C8A3F0
+
+#define mmPDMA0_QM_CP_IN_DATA_LO_0 0x4C8A3F4
+
+#define mmPDMA0_QM_CP_IN_DATA_LO_1 0x4C8A3F8
+
+#define mmPDMA0_QM_CP_IN_DATA_LO_2 0x4C8A3FC
+
+#define mmPDMA0_QM_CP_IN_DATA_LO_3 0x4C8A400
+
+#define mmPDMA0_QM_CP_IN_DATA_LO_4 0x4C8A404
+
+#define mmPDMA0_QM_CP_IN_DATA_HI_0 0x4C8A408
+
+#define mmPDMA0_QM_CP_IN_DATA_HI_1 0x4C8A40C
+
+#define mmPDMA0_QM_CP_IN_DATA_HI_2 0x4C8A410
+
+#define mmPDMA0_QM_CP_IN_DATA_HI_3 0x4C8A414
+
+#define mmPDMA0_QM_CP_IN_DATA_HI_4 0x4C8A418
+
+#define mmPDMA0_QM_PQC_HBW_BASE_LO_0 0x4C8A41C
+
+#define mmPDMA0_QM_PQC_HBW_BASE_LO_1 0x4C8A420
+
+#define mmPDMA0_QM_PQC_HBW_BASE_LO_2 0x4C8A424
+
+#define mmPDMA0_QM_PQC_HBW_BASE_LO_3 0x4C8A428
+
+#define mmPDMA0_QM_PQC_HBW_BASE_HI_0 0x4C8A42C
+
+#define mmPDMA0_QM_PQC_HBW_BASE_HI_1 0x4C8A430
+
+#define mmPDMA0_QM_PQC_HBW_BASE_HI_2 0x4C8A434
+
+#define mmPDMA0_QM_PQC_HBW_BASE_HI_3 0x4C8A438
+
+#define mmPDMA0_QM_PQC_SIZE_0 0x4C8A43C
+
+#define mmPDMA0_QM_PQC_SIZE_1 0x4C8A440
+
+#define mmPDMA0_QM_PQC_SIZE_2 0x4C8A444
+
+#define mmPDMA0_QM_PQC_SIZE_3 0x4C8A448
+
+#define mmPDMA0_QM_PQC_PI_0 0x4C8A44C
+
+#define mmPDMA0_QM_PQC_PI_1 0x4C8A450
+
+#define mmPDMA0_QM_PQC_PI_2 0x4C8A454
+
+#define mmPDMA0_QM_PQC_PI_3 0x4C8A458
+
+#define mmPDMA0_QM_PQC_LBW_WDATA_0 0x4C8A45C
+
+#define mmPDMA0_QM_PQC_LBW_WDATA_1 0x4C8A460
+
+#define mmPDMA0_QM_PQC_LBW_WDATA_2 0x4C8A464
+
+#define mmPDMA0_QM_PQC_LBW_WDATA_3 0x4C8A468
+
+#define mmPDMA0_QM_PQC_LBW_BASE_LO_0 0x4C8A46C
+
+#define mmPDMA0_QM_PQC_LBW_BASE_LO_1 0x4C8A470
+
+#define mmPDMA0_QM_PQC_LBW_BASE_LO_2 0x4C8A474
+
+#define mmPDMA0_QM_PQC_LBW_BASE_LO_3 0x4C8A478
+
+#define mmPDMA0_QM_PQC_LBW_BASE_HI_0 0x4C8A47C
+
+#define mmPDMA0_QM_PQC_LBW_BASE_HI_1 0x4C8A480
+
+#define mmPDMA0_QM_PQC_LBW_BASE_HI_2 0x4C8A484
+
+#define mmPDMA0_QM_PQC_LBW_BASE_HI_3 0x4C8A488
+
+#define mmPDMA0_QM_PQC_CFG 0x4C8A48C
+
+#define mmPDMA0_QM_PQC_SECURE_PUSH_IND 0x4C8A490
+
+#define mmPDMA0_QM_ARB_MASK 0x4C8A4A0
+
+#define mmPDMA0_QM_ARB_CFG_0 0x4C8A4A4
+
+#define mmPDMA0_QM_ARB_CHOICE_Q_PUSH 0x4C8A4A8
+
+#define mmPDMA0_QM_ARB_WRR_WEIGHT_0 0x4C8A4AC
+
+#define mmPDMA0_QM_ARB_WRR_WEIGHT_1 0x4C8A4B0
+
+#define mmPDMA0_QM_ARB_WRR_WEIGHT_2 0x4C8A4B4
+
+#define mmPDMA0_QM_ARB_WRR_WEIGHT_3 0x4C8A4B8
+
+#define mmPDMA0_QM_ARB_CFG_1 0x4C8A4BC
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_0 0x4C8A4C0
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_1 0x4C8A4C4
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_2 0x4C8A4C8
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_3 0x4C8A4CC
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_4 0x4C8A4D0
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_5 0x4C8A4D4
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_6 0x4C8A4D8
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_7 0x4C8A4DC
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_8 0x4C8A4E0
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_9 0x4C8A4E4
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_10 0x4C8A4E8
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_11 0x4C8A4EC
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_12 0x4C8A4F0
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_13 0x4C8A4F4
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_14 0x4C8A4F8
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_15 0x4C8A4FC
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_16 0x4C8A500
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_17 0x4C8A504
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_18 0x4C8A508
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_19 0x4C8A50C
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_20 0x4C8A510
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_21 0x4C8A514
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_22 0x4C8A518
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_23 0x4C8A51C
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_24 0x4C8A520
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_25 0x4C8A524
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_26 0x4C8A528
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_27 0x4C8A52C
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_28 0x4C8A530
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_29 0x4C8A534
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_30 0x4C8A538
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_31 0x4C8A53C
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_32 0x4C8A540
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_33 0x4C8A544
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_34 0x4C8A548
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_35 0x4C8A54C
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_36 0x4C8A550
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_37 0x4C8A554
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_38 0x4C8A558
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_39 0x4C8A55C
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_40 0x4C8A560
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_41 0x4C8A564
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_42 0x4C8A568
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_43 0x4C8A56C
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_44 0x4C8A570
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_45 0x4C8A574
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_46 0x4C8A578
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_47 0x4C8A57C
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_48 0x4C8A580
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_49 0x4C8A584
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_50 0x4C8A588
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_51 0x4C8A58C
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_52 0x4C8A590
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_53 0x4C8A594
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_54 0x4C8A598
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_55 0x4C8A59C
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_56 0x4C8A5A0
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_57 0x4C8A5A4
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_58 0x4C8A5A8
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_59 0x4C8A5AC
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_60 0x4C8A5B0
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_61 0x4C8A5B4
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_62 0x4C8A5B8
+
+#define mmPDMA0_QM_ARB_MST_AVAIL_CRED_63 0x4C8A5BC
+
+#define mmPDMA0_QM_ARB_MST_CRED_INC 0x4C8A5E0
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_0 0x4C8A5E4
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_1 0x4C8A5E8
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_2 0x4C8A5EC
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_3 0x4C8A5F0
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_4 0x4C8A5F4
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_5 0x4C8A5F8
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_6 0x4C8A5FC
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_7 0x4C8A600
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_8 0x4C8A604
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_9 0x4C8A608
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_10 0x4C8A60C
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_11 0x4C8A610
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_12 0x4C8A614
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_13 0x4C8A618
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_14 0x4C8A61C
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_15 0x4C8A620
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_16 0x4C8A624
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_17 0x4C8A628
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_18 0x4C8A62C
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_19 0x4C8A630
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_20 0x4C8A634
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_21 0x4C8A638
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_22 0x4C8A63C
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_23 0x4C8A640
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_24 0x4C8A644
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_25 0x4C8A648
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_26 0x4C8A64C
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_27 0x4C8A650
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_28 0x4C8A654
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_29 0x4C8A658
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_30 0x4C8A65C
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_31 0x4C8A660
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_32 0x4C8A664
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_33 0x4C8A668
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_34 0x4C8A66C
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_35 0x4C8A670
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_36 0x4C8A674
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_37 0x4C8A678
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_38 0x4C8A67C
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_39 0x4C8A680
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_40 0x4C8A684
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_41 0x4C8A688
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_42 0x4C8A68C
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_43 0x4C8A690
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_44 0x4C8A694
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_45 0x4C8A698
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_46 0x4C8A69C
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_47 0x4C8A6A0
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_48 0x4C8A6A4
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_49 0x4C8A6A8
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_50 0x4C8A6AC
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_51 0x4C8A6B0
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_52 0x4C8A6B4
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_53 0x4C8A6B8
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_54 0x4C8A6BC
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_55 0x4C8A6C0
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_56 0x4C8A6C4
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_57 0x4C8A6C8
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_58 0x4C8A6CC
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_59 0x4C8A6D0
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_60 0x4C8A6D4
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_61 0x4C8A6D8
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_62 0x4C8A6DC
+
+#define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_63 0x4C8A6E0
+
+#define mmPDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x4C8A704
+
+#define mmPDMA0_QM_ARB_MST_SLAVE_EN 0x4C8A708
+
+#define mmPDMA0_QM_ARB_MST_SLAVE_EN_1 0x4C8A70C
+
+#define mmPDMA0_QM_ARB_SLV_CHOICE_WDT 0x4C8A710
+
+#define mmPDMA0_QM_ARB_SLV_ID 0x4C8A714
+
+#define mmPDMA0_QM_ARB_MST_QUIET_PER 0x4C8A718
+
+#define mmPDMA0_QM_ARB_MSG_MAX_INFLIGHT 0x4C8A744
+
+#define mmPDMA0_QM_ARB_BASE_LO 0x4C8A754
+
+#define mmPDMA0_QM_ARB_BASE_HI 0x4C8A758
+
+#define mmPDMA0_QM_ARB_STATE_STS 0x4C8A780
+
+#define mmPDMA0_QM_ARB_CHOICE_FULLNESS_STS 0x4C8A784
+
+#define mmPDMA0_QM_ARB_MSG_STS 0x4C8A788
+
+#define mmPDMA0_QM_ARB_SLV_CHOICE_Q_HEAD 0x4C8A78C
+
+#define mmPDMA0_QM_ARB_ERR_CAUSE 0x4C8A79C
+
+#define mmPDMA0_QM_ARB_ERR_MSG_EN 0x4C8A7A0
+
+#define mmPDMA0_QM_ARB_ERR_STS_DRP 0x4C8A7A8
+
+#define mmPDMA0_QM_ARB_MST_CRED_STS 0x4C8A7B0
+
+#define mmPDMA0_QM_ARB_MST_CRED_STS_1 0x4C8A7B4
+
+#define mmPDMA0_QM_CSMR_STRICT_PRIO_CFG 0x4C8A7FC
+
+#define mmPDMA0_QM_ARC_CQ_CFG0 0x4C8A800
+
+#define mmPDMA0_QM_ARC_CQ_CFG1 0x4C8A804
+
+#define mmPDMA0_QM_ARC_CQ_PTR_LO 0x4C8A808
+
+#define mmPDMA0_QM_ARC_CQ_PTR_HI 0x4C8A80C
+
+#define mmPDMA0_QM_ARC_CQ_TSIZE 0x4C8A810
+
+#define mmPDMA0_QM_ARC_CQ_CTL 0x4C8A814
+
+#define mmPDMA0_QM_ARC_CQ_IFIFO_STS 0x4C8A81C
+
+#define mmPDMA0_QM_ARC_CQ_STS0 0x4C8A820
+
+#define mmPDMA0_QM_ARC_CQ_STS1 0x4C8A824
+
+#define mmPDMA0_QM_ARC_CQ_TSIZE_STS 0x4C8A828
+
+#define mmPDMA0_QM_ARC_CQ_PTR_LO_STS 0x4C8A82C
+
+#define mmPDMA0_QM_ARC_CQ_PTR_HI_STS 0x4C8A830
+
+#define mmPDMA0_QM_CP_WR_ARC_ADDR_HI 0x4C8A834
+
+#define mmPDMA0_QM_CP_WR_ARC_ADDR_LO 0x4C8A838
+
+#define mmPDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI 0x4C8A83C
+
+#define mmPDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO 0x4C8A840
+
+#define mmPDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI 0x4C8A844
+
+#define mmPDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO 0x4C8A848
+
+#define mmPDMA0_QM_CQ_IFIFO_MSG_BASE_HI 0x4C8A84C
+
+#define mmPDMA0_QM_CQ_IFIFO_MSG_BASE_LO 0x4C8A850
+
+#define mmPDMA0_QM_CQ_CTL_MSG_BASE_HI 0x4C8A854
+
+#define mmPDMA0_QM_CQ_CTL_MSG_BASE_LO 0x4C8A858
+
+#define mmPDMA0_QM_ADDR_OVRD 0x4C8A85C
+
+#define mmPDMA0_QM_CQ_IFIFO_CI_0 0x4C8A860
+
+#define mmPDMA0_QM_CQ_IFIFO_CI_1 0x4C8A864
+
+#define mmPDMA0_QM_CQ_IFIFO_CI_2 0x4C8A868
+
+#define mmPDMA0_QM_CQ_IFIFO_CI_3 0x4C8A86C
+
+#define mmPDMA0_QM_CQ_IFIFO_CI_4 0x4C8A870
+
+#define mmPDMA0_QM_ARC_CQ_IFIFO_CI 0x4C8A874
+
+#define mmPDMA0_QM_CQ_CTL_CI_0 0x4C8A878
+
+#define mmPDMA0_QM_CQ_CTL_CI_1 0x4C8A87C
+
+#define mmPDMA0_QM_CQ_CTL_CI_2 0x4C8A880
+
+#define mmPDMA0_QM_CQ_CTL_CI_3 0x4C8A884
+
+#define mmPDMA0_QM_CQ_CTL_CI_4 0x4C8A888
+
+#define mmPDMA0_QM_ARC_CQ_CTL_CI 0x4C8A88C
+
+#define mmPDMA0_QM_CP_CFG 0x4C8A890
+
+#define mmPDMA0_QM_CP_EXT_SWITCH 0x4C8A894
+
+#define mmPDMA0_QM_CP_SWITCH_WD_SET 0x4C8A898
+
+#define mmPDMA0_QM_CP_SWITCH_WD 0x4C8A89C
+
+#define mmPDMA0_QM_ARC_LB_ADDR_BASE_LO 0x4C8A8A4
+
+#define mmPDMA0_QM_ARC_LB_ADDR_BASE_HI 0x4C8A8A8
+
+#define mmPDMA0_QM_ENGINE_BASE_ADDR_HI 0x4C8A8AC
+
+#define mmPDMA0_QM_ENGINE_BASE_ADDR_LO 0x4C8A8B0
+
+#define mmPDMA0_QM_ENGINE_ADDR_RANGE_SIZE 0x4C8A8B4
+
+#define mmPDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI 0x4C8A8B8
+
+#define mmPDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO 0x4C8A8BC
+
+#define mmPDMA0_QM_QM_BASE_ADDR_HI 0x4C8A8C0
+
+#define mmPDMA0_QM_QM_BASE_ADDR_LO 0x4C8A8C4
+
+#define mmPDMA0_QM_ARC_PQC_SECURE_PUSH_IND 0x4C8A8C8
+
+#define mmPDMA0_QM_PQC_STS_0_0 0x4C8A8D0
+
+#define mmPDMA0_QM_PQC_STS_0_1 0x4C8A8D4
+
+#define mmPDMA0_QM_PQC_STS_0_2 0x4C8A8D8
+
+#define mmPDMA0_QM_PQC_STS_0_3 0x4C8A8DC
+
+#define mmPDMA0_QM_PQC_STS_1_0 0x4C8A8E0
+
+#define mmPDMA0_QM_PQC_STS_1_1 0x4C8A8E4
+
+#define mmPDMA0_QM_PQC_STS_1_2 0x4C8A8E8
+
+#define mmPDMA0_QM_PQC_STS_1_3 0x4C8A8EC
+
+#define mmPDMA0_QM_SEI_STATUS 0x4C8A8F0
+
+#define mmPDMA0_QM_SEI_MASK 0x4C8A8F4
+
+#define mmPDMA0_QM_GLBL_ERR_ADDR_LO 0x4C8AD00
+
+#define mmPDMA0_QM_GLBL_ERR_ADDR_HI 0x4C8AD04
+
+#define mmPDMA0_QM_GLBL_ERR_WDATA 0x4C8AD08
+
+#define mmPDMA0_QM_L2H_MASK_LO 0x4C8AD14
+
+#define mmPDMA0_QM_L2H_MASK_HI 0x4C8AD18
+
+#define mmPDMA0_QM_L2H_CMPR_LO 0x4C8AD1C
+
+#define mmPDMA0_QM_L2H_CMPR_HI 0x4C8AD20
+
+#define mmPDMA0_QM_LOCAL_RANGE_BASE 0x4C8AD24
+
+#define mmPDMA0_QM_LOCAL_RANGE_SIZE 0x4C8AD28
+
+#define mmPDMA0_QM_HBW_RD_RATE_LIM_CFG_1 0x4C8AD30
+
+#define mmPDMA0_QM_LBW_WR_RATE_LIM_CFG_0 0x4C8AD34
+
+#define mmPDMA0_QM_LBW_WR_RATE_LIM_CFG_1 0x4C8AD38
+
+#define mmPDMA0_QM_HBW_RD_RATE_LIM_CFG_0 0x4C8AD3C
+
+#define mmPDMA0_QM_IND_GW_APB_CFG 0x4C8AD40
+
+#define mmPDMA0_QM_IND_GW_APB_WDATA 0x4C8AD44
+
+#define mmPDMA0_QM_IND_GW_APB_RDATA 0x4C8AD48
+
+#define mmPDMA0_QM_IND_GW_APB_STATUS 0x4C8AD4C
+
+#define mmPDMA0_QM_PERF_CNT_FREE_LO 0x4C8AD60
+
+#define mmPDMA0_QM_PERF_CNT_FREE_HI 0x4C8AD64
+
+#define mmPDMA0_QM_PERF_CNT_IDLE_LO 0x4C8AD68
+
+#define mmPDMA0_QM_PERF_CNT_IDLE_HI 0x4C8AD6C
+
+#define mmPDMA0_QM_PERF_CNT_CFG 0x4C8AD70
+
+#endif /* ASIC_REG_PDMA0_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma1_core_ctx_axuser_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma1_core_ctx_axuser_regs.h
new file mode 100644
index 000000000000..ccc6dfd22dd7
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma1_core_ctx_axuser_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PDMA1_CORE_CTX_AXUSER_REGS_H_
+#define ASIC_REG_PDMA1_CORE_CTX_AXUSER_REGS_H_
+
+/*
+ *****************************************
+ *   PDMA1_CORE_CTX_AXUSER
+ *   (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define mmPDMA1_CORE_CTX_AXUSER_HB_ASID 0x4C9B800
+
+#define mmPDMA1_CORE_CTX_AXUSER_HB_MMU_BP 0x4C9B804
+
+#define mmPDMA1_CORE_CTX_AXUSER_HB_STRONG_ORDER 0x4C9B808
+
+#define mmPDMA1_CORE_CTX_AXUSER_HB_NO_SNOOP 0x4C9B80C
+
+#define mmPDMA1_CORE_CTX_AXUSER_HB_WR_REDUCTION 0x4C9B810
+
+#define mmPDMA1_CORE_CTX_AXUSER_HB_RD_ATOMIC 0x4C9B814
+
+#define mmPDMA1_CORE_CTX_AXUSER_HB_QOS 0x4C9B818
+
+#define mmPDMA1_CORE_CTX_AXUSER_HB_RSVD 0x4C9B81C
+
+#define mmPDMA1_CORE_CTX_AXUSER_HB_EMEM_CPAGE 0x4C9B820
+
+#define mmPDMA1_CORE_CTX_AXUSER_HB_CORE 0x4C9B824
+
+#define mmPDMA1_CORE_CTX_AXUSER_E2E_COORD 0x4C9B828
+
+#define mmPDMA1_CORE_CTX_AXUSER_HB_WR_OVRD_LO 0x4C9B830
+
+#define mmPDMA1_CORE_CTX_AXUSER_HB_WR_OVRD_HI 0x4C9B834
+
+#define mmPDMA1_CORE_CTX_AXUSER_HB_RD_OVRD_LO 0x4C9B838
+
+#define mmPDMA1_CORE_CTX_AXUSER_HB_RD_OVRD_HI 0x4C9B83C
+
+#define mmPDMA1_CORE_CTX_AXUSER_LB_COORD 0x4C9B840
+
+#define mmPDMA1_CORE_CTX_AXUSER_LB_LOCK 0x4C9B844
+
+#define mmPDMA1_CORE_CTX_AXUSER_LB_RSVD 0x4C9B848
+
+#define mmPDMA1_CORE_CTX_AXUSER_LB_OVRD 0x4C9B84C
+
+#endif /* ASIC_REG_PDMA1_CORE_CTX_AXUSER_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma1_qm_axuser_nonsecured_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma1_qm_axuser_nonsecured_regs.h
new file mode 100644
index 000000000000..5fd72d050fff
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma1_qm_axuser_nonsecured_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PDMA1_QM_AXUSER_NONSECURED_REGS_H_
+#define ASIC_REG_PDMA1_QM_AXUSER_NONSECURED_REGS_H_
+
+/*
+ *****************************************
+ *   PDMA1_QM_AXUSER_NONSECURED
+ *   (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define mmPDMA1_QM_AXUSER_NONSECURED_HB_ASID 0x4C9AB80
+
+#define mmPDMA1_QM_AXUSER_NONSECURED_HB_MMU_BP 0x4C9AB84
+
+#define mmPDMA1_QM_AXUSER_NONSECURED_HB_STRONG_ORDER 0x4C9AB88
+
+#define mmPDMA1_QM_AXUSER_NONSECURED_HB_NO_SNOOP 0x4C9AB8C
+
+#define mmPDMA1_QM_AXUSER_NONSECURED_HB_WR_REDUCTION 0x4C9AB90
+
+#define mmPDMA1_QM_AXUSER_NONSECURED_HB_RD_ATOMIC 0x4C9AB94
+
+#define mmPDMA1_QM_AXUSER_NONSECURED_HB_QOS 0x4C9AB98
+
+#define mmPDMA1_QM_AXUSER_NONSECURED_HB_RSVD 0x4C9AB9C
+
+#define mmPDMA1_QM_AXUSER_NONSECURED_HB_EMEM_CPAGE 0x4C9ABA0
+
+#define mmPDMA1_QM_AXUSER_NONSECURED_HB_CORE 0x4C9ABA4
+
+#define mmPDMA1_QM_AXUSER_NONSECURED_E2E_COORD 0x4C9ABA8
+
+#define mmPDMA1_QM_AXUSER_NONSECURED_HB_WR_OVRD_LO 0x4C9ABB0
+
+#define mmPDMA1_QM_AXUSER_NONSECURED_HB_WR_OVRD_HI 0x4C9ABB4
+
+#define mmPDMA1_QM_AXUSER_NONSECURED_HB_RD_OVRD_LO 0x4C9ABB8
+
+#define mmPDMA1_QM_AXUSER_NONSECURED_HB_RD_OVRD_HI 0x4C9ABBC
+
+#define mmPDMA1_QM_AXUSER_NONSECURED_LB_COORD 0x4C9ABC0
+
+#define mmPDMA1_QM_AXUSER_NONSECURED_LB_LOCK 0x4C9ABC4
+
+#define mmPDMA1_QM_AXUSER_NONSECURED_LB_RSVD 0x4C9ABC8
+
+#define mmPDMA1_QM_AXUSER_NONSECURED_LB_OVRD 0x4C9ABCC
+
+#endif /* ASIC_REG_PDMA1_QM_AXUSER_NONSECURED_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/pmmu_hbw_stlb_masks.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pmmu_hbw_stlb_masks.h
new file mode 100644
index 000000000000..b4f32632cd36
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pmmu_hbw_stlb_masks.h
@@ -0,0 +1,333 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PMMU_HBW_STLB_MASKS_H_
+#define ASIC_REG_PMMU_HBW_STLB_MASKS_H_
+
+/*
+ *****************************************
+ *   PMMU_HBW_STLB
+ *   (Prototype: STLB)
+ *****************************************
+ */
+
+/* PMMU_HBW_STLB_BUSY */
+#define PMMU_HBW_STLB_BUSY_BUSY_SHIFT 0
+#define PMMU_HBW_STLB_BUSY_BUSY_MASK 0xFFFFFFFF
+
+/* PMMU_HBW_STLB_ASID */
+#define PMMU_HBW_STLB_ASID_ASID_SHIFT 0
+#define PMMU_HBW_STLB_ASID_ASID_MASK 0x3FF
+
+/* PMMU_HBW_STLB_HOP0_PA43_12 */
+#define PMMU_HBW_STLB_HOP0_PA43_12_HOP0_PA43_12_SHIFT 0
+#define PMMU_HBW_STLB_HOP0_PA43_12_HOP0_PA43_12_MASK 0xFFFFFFFF
+
+/* PMMU_HBW_STLB_HOP0_PA63_44 */
+#define PMMU_HBW_STLB_HOP0_PA63_44_HOP0_PA63_44_SHIFT 0
+#define PMMU_HBW_STLB_HOP0_PA63_44_HOP0_PA63_44_MASK 0xFFFFF
+
+/* PMMU_HBW_STLB_CACHE_INV */
+#define PMMU_HBW_STLB_CACHE_INV_PRODUCER_INDEX_SHIFT 0
+#define PMMU_HBW_STLB_CACHE_INV_PRODUCER_INDEX_MASK 0xFF
+#define PMMU_HBW_STLB_CACHE_INV_INDEX_MASK_SHIFT 8
+#define PMMU_HBW_STLB_CACHE_INV_INDEX_MASK_MASK 0xFF00
+
+/* PMMU_HBW_STLB_CACHE_INV_BASE_39_8 */
+#define PMMU_HBW_STLB_CACHE_INV_BASE_39_8_PA_SHIFT 0
+#define PMMU_HBW_STLB_CACHE_INV_BASE_39_8_PA_MASK 0xFFFFFFFF
+
+/* PMMU_HBW_STLB_CACHE_INV_BASE_63_40 */
+#define PMMU_HBW_STLB_CACHE_INV_BASE_63_40_PA_SHIFT 0
+#define PMMU_HBW_STLB_CACHE_INV_BASE_63_40_PA_MASK 0xFFFFFF
+
+/* PMMU_HBW_STLB_STLB_FEATURE_EN */
+#define PMMU_HBW_STLB_STLB_FEATURE_EN_STLB_CTRL_MULTI_PAGE_SIZE_EN_SHIFT 0
+#define PMMU_HBW_STLB_STLB_FEATURE_EN_STLB_CTRL_MULTI_PAGE_SIZE_EN_MASK 0x1
+#define PMMU_HBW_STLB_STLB_FEATURE_EN_MULTI_PAGE_SIZE_EN_SHIFT 1
+#define PMMU_HBW_STLB_STLB_FEATURE_EN_MULTI_PAGE_SIZE_EN_MASK 0x2
+#define PMMU_HBW_STLB_STLB_FEATURE_EN_LOOKUP_EN_SHIFT 2
+#define PMMU_HBW_STLB_STLB_FEATURE_EN_LOOKUP_EN_MASK 0x4
+#define PMMU_HBW_STLB_STLB_FEATURE_EN_BYPASS_SHIFT 3
+#define PMMU_HBW_STLB_STLB_FEATURE_EN_BYPASS_MASK 0x8
+#define PMMU_HBW_STLB_STLB_FEATURE_EN_BANK_STOP_SHIFT 4
+#define PMMU_HBW_STLB_STLB_FEATURE_EN_BANK_STOP_MASK 0x10
+#define PMMU_HBW_STLB_STLB_FEATURE_EN_TRACE_EN_SHIFT 5
+#define PMMU_HBW_STLB_STLB_FEATURE_EN_TRACE_EN_MASK 0x20
+#define PMMU_HBW_STLB_STLB_FEATURE_EN_FOLLOWER_EN_SHIFT 6
+#define PMMU_HBW_STLB_STLB_FEATURE_EN_FOLLOWER_EN_MASK 0x40
+#define PMMU_HBW_STLB_STLB_FEATURE_EN_CACHING_EN_SHIFT 7
+#define PMMU_HBW_STLB_STLB_FEATURE_EN_CACHING_EN_MASK 0x1F80
+#define PMMU_HBW_STLB_STLB_FEATURE_EN_FOLLOWING_NUM_LIMIT_SHIFT 13
+#define PMMU_HBW_STLB_STLB_FEATURE_EN_FOLLOWING_NUM_LIMIT_MASK 0xE000
+
+/* PMMU_HBW_STLB_STLB_AXI_CACHE */
+#define PMMU_HBW_STLB_STLB_AXI_CACHE_STLB_CTRL_ARCACHE_SHIFT 0
+#define PMMU_HBW_STLB_STLB_AXI_CACHE_STLB_CTRL_ARCACHE_MASK 0xF
+#define PMMU_HBW_STLB_STLB_AXI_CACHE_STLB_CTRL_AWCACHE_SHIFT 4
+#define PMMU_HBW_STLB_STLB_AXI_CACHE_STLB_CTRL_AWCACHE_MASK 0xF0
+#define PMMU_HBW_STLB_STLB_AXI_CACHE_INV_ARCACHE_SHIFT 8
+#define PMMU_HBW_STLB_STLB_AXI_CACHE_INV_ARCACHE_MASK 0xF00
+
+/* PMMU_HBW_STLB_HOP_CONFIGURATION */
+#define PMMU_HBW_STLB_HOP_CONFIGURATION_FIRST_HOP_SHIFT 0
+#define PMMU_HBW_STLB_HOP_CONFIGURATION_FIRST_HOP_MASK 0x7
+#define PMMU_HBW_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_SMALL_P_SHIFT 4
+#define PMMU_HBW_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_SMALL_P_MASK 0x70
+#define PMMU_HBW_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_LARGE_P_SHIFT 8
+#define PMMU_HBW_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_LARGE_P_MASK 0x700
+#define PMMU_HBW_STLB_HOP_CONFIGURATION_LAST_HOP_SHIFT 12
+#define PMMU_HBW_STLB_HOP_CONFIGURATION_LAST_HOP_MASK 0x7000
+#define PMMU_HBW_STLB_HOP_CONFIGURATION_FOLLOWER_HOP_SHIFT 16
+#define PMMU_HBW_STLB_HOP_CONFIGURATION_FOLLOWER_HOP_MASK 0x70000
+#define PMMU_HBW_STLB_HOP_CONFIGURATION_ONLY_LARGE_PAGE_SHIFT 20
+#define PMMU_HBW_STLB_HOP_CONFIGURATION_ONLY_LARGE_PAGE_MASK 0x100000
+#define PMMU_HBW_STLB_HOP_CONFIGURATION_LARGE_PAGE_INDICATION_BIT_SHIFT 21
+#define PMMU_HBW_STLB_HOP_CONFIGURATION_LARGE_PAGE_INDICATION_BIT_MASK 0x7E00000
+
+/* PMMU_HBW_STLB_LINK_LIST_LOOKUP_MASK_63_32 */
+#define PMMU_HBW_STLB_LINK_LIST_LOOKUP_MASK_63_32_R_SHIFT 0
+#define PMMU_HBW_STLB_LINK_LIST_LOOKUP_MASK_63_32_R_MASK 0xFFFFFFFF
+
+/* PMMU_HBW_STLB_LINK_LIST_LOOKUP_MASK_31_0 */
+#define PMMU_HBW_STLB_LINK_LIST_LOOKUP_MASK_31_0_R_SHIFT 0
+#define PMMU_HBW_STLB_LINK_LIST_LOOKUP_MASK_31_0_R_MASK 0xFFFFFFFF
+
+/* PMMU_HBW_STLB_INV_ALL_START */
+#define PMMU_HBW_STLB_INV_ALL_START_R_SHIFT 0
+#define PMMU_HBW_STLB_INV_ALL_START_R_MASK 0x1
+
+/* PMMU_HBW_STLB_INV_ALL_SET */
+#define PMMU_HBW_STLB_INV_ALL_SET_R_SHIFT 0
+#define PMMU_HBW_STLB_INV_ALL_SET_R_MASK 0xFF
+
+/* PMMU_HBW_STLB_INV_PS */
+#define PMMU_HBW_STLB_INV_PS_R_SHIFT 0
+#define PMMU_HBW_STLB_INV_PS_R_MASK 0x3
+
+/* PMMU_HBW_STLB_INV_CONSUMER_INDEX */
+#define PMMU_HBW_STLB_INV_CONSUMER_INDEX_R_SHIFT 0
+#define PMMU_HBW_STLB_INV_CONSUMER_INDEX_R_MASK 0xFF
+
+/* PMMU_HBW_STLB_INV_HIT_COUNT */
+#define PMMU_HBW_STLB_INV_HIT_COUNT_R_SHIFT 0
+#define PMMU_HBW_STLB_INV_HIT_COUNT_R_MASK 0x7FF
+
+/* PMMU_HBW_STLB_INV_SET */
+#define PMMU_HBW_STLB_INV_SET_R_SHIFT 0
+#define PMMU_HBW_STLB_INV_SET_R_MASK 0xFF
+
+/* PMMU_HBW_STLB_SRAM_INIT */
+#define PMMU_HBW_STLB_SRAM_INIT_BUSY_TAG_SHIFT 0
+#define PMMU_HBW_STLB_SRAM_INIT_BUSY_TAG_MASK 0x3
+#define PMMU_HBW_STLB_SRAM_INIT_BUSY_SLICE_SHIFT 2
+#define PMMU_HBW_STLB_SRAM_INIT_BUSY_SLICE_MASK 0xC
+#define PMMU_HBW_STLB_SRAM_INIT_BUSY_DATA_SHIFT 4
+#define PMMU_HBW_STLB_SRAM_INIT_BUSY_DATA_MASK 0x10
+
+/* PMMU_HBW_STLB_MEM_CACHE_INVALIDATION */
+
+/* PMMU_HBW_STLB_MEM_CACHE_INV_STATUS */
+#define PMMU_HBW_STLB_MEM_CACHE_INV_STATUS_INVALIDATE_DONE_SHIFT 0
+#define PMMU_HBW_STLB_MEM_CACHE_INV_STATUS_INVALIDATE_DONE_MASK 0x1
+#define PMMU_HBW_STLB_MEM_CACHE_INV_STATUS_CACHE_IDLE_SHIFT 1
+#define PMMU_HBW_STLB_MEM_CACHE_INV_STATUS_CACHE_IDLE_MASK 0x2
+
+/* PMMU_HBW_STLB_MEM_CACHE_BASE_38_7 */
+#define PMMU_HBW_STLB_MEM_CACHE_BASE_38_7_R_SHIFT 0
+#define PMMU_HBW_STLB_MEM_CACHE_BASE_38_7_R_MASK 0xFFFFFFFF
+
+/* PMMU_HBW_STLB_MEM_CACHE_BASE_63_39 */
+#define PMMU_HBW_STLB_MEM_CACHE_BASE_63_39_R_SHIFT 0
+#define PMMU_HBW_STLB_MEM_CACHE_BASE_63_39_R_MASK 0x1FFFFFF
+
+/* PMMU_HBW_STLB_MEM_CACHE_CONFIG */
+#define PMMU_HBW_STLB_MEM_CACHE_CONFIG_CACHE_HOP_EN_SHIFT 0
+#define PMMU_HBW_STLB_MEM_CACHE_CONFIG_CACHE_HOP_EN_MASK 0x3F
+#define PMMU_HBW_STLB_MEM_CACHE_CONFIG_CACHE_HOP_PREFETCH_EN_SHIFT 6
+#define PMMU_HBW_STLB_MEM_CACHE_CONFIG_CACHE_HOP_PREFETCH_EN_MASK 0xFC0
+#define PMMU_HBW_STLB_MEM_CACHE_CONFIG_BYPASS_EN_SHIFT 12
+#define PMMU_HBW_STLB_MEM_CACHE_CONFIG_BYPASS_EN_MASK 0x1000
+#define PMMU_HBW_STLB_MEM_CACHE_CONFIG_RELEASE_INVALIDATE_SHIFT 13
+#define PMMU_HBW_STLB_MEM_CACHE_CONFIG_RELEASE_INVALIDATE_MASK 0x2000
+
+/* PMMU_HBW_STLB_SET_THRESHOLD_HOP5 */
+#define PMMU_HBW_STLB_SET_THRESHOLD_HOP5_MIN_SHIFT 0
+#define PMMU_HBW_STLB_SET_THRESHOLD_HOP5_MIN_MASK 0x1FF
+#define PMMU_HBW_STLB_SET_THRESHOLD_HOP5_MAX_SHIFT 9
+#define PMMU_HBW_STLB_SET_THRESHOLD_HOP5_MAX_MASK 0x3FE00
+#define PMMU_HBW_STLB_SET_THRESHOLD_HOP5_MASK_SHIFT 18
+#define PMMU_HBW_STLB_SET_THRESHOLD_HOP5_MASK_MASK 0x7FC0000
+
+/* PMMU_HBW_STLB_SET_THRESHOLD_HOP4 */
+#define PMMU_HBW_STLB_SET_THRESHOLD_HOP4_MIN_SHIFT 0
+#define PMMU_HBW_STLB_SET_THRESHOLD_HOP4_MIN_MASK 0x1FF
+#define PMMU_HBW_STLB_SET_THRESHOLD_HOP4_MAX_SHIFT 9
+#define PMMU_HBW_STLB_SET_THRESHOLD_HOP4_MAX_MASK 0x3FE00
+#define PMMU_HBW_STLB_SET_THRESHOLD_HOP4_MASK_SHIFT 18
+#define PMMU_HBW_STLB_SET_THRESHOLD_HOP4_MASK_MASK 0x7FC0000
+
+/* PMMU_HBW_STLB_SET_THRESHOLD_HOP3 */
+#define PMMU_HBW_STLB_SET_THRESHOLD_HOP3_MIN_SHIFT 0
+#define PMMU_HBW_STLB_SET_THRESHOLD_HOP3_MIN_MASK 0x1FF
+#define PMMU_HBW_STLB_SET_THRESHOLD_HOP3_MAX_SHIFT 9
+#define PMMU_HBW_STLB_SET_THRESHOLD_HOP3_MAX_MASK 0x3FE00
+#define PMMU_HBW_STLB_SET_THRESHOLD_HOP3_MASK_SHIFT 18
+#define PMMU_HBW_STLB_SET_THRESHOLD_HOP3_MASK_MASK 0x7FC0000
+
+/* PMMU_HBW_STLB_SET_THRESHOLD_HOP2 */
+#define PMMU_HBW_STLB_SET_THRESHOLD_HOP2_MIN_SHIFT 0
+#define PMMU_HBW_STLB_SET_THRESHOLD_HOP2_MIN_MASK 0x1FF
+#define PMMU_HBW_STLB_SET_THRESHOLD_HOP2_MAX_SHIFT 9
+#define PMMU_HBW_STLB_SET_THRESHOLD_HOP2_MAX_MASK 0x3FE00
+#define PMMU_HBW_STLB_SET_THRESHOLD_HOP2_MASK_SHIFT 18
+#define PMMU_HBW_STLB_SET_THRESHOLD_HOP2_MASK_MASK 0x7FC0000
+
+/* PMMU_HBW_STLB_SET_THRESHOLD_HOP1 */
+#define PMMU_HBW_STLB_SET_THRESHOLD_HOP1_MIN_SHIFT 0
+#define PMMU_HBW_STLB_SET_THRESHOLD_HOP1_MIN_MASK 0x1FF
+#define PMMU_HBW_STLB_SET_THRESHOLD_HOP1_MAX_SHIFT 9
+#define PMMU_HBW_STLB_SET_THRESHOLD_HOP1_MAX_MASK 0x3FE00
+#define PMMU_HBW_STLB_SET_THRESHOLD_HOP1_MASK_SHIFT 18
+#define PMMU_HBW_STLB_SET_THRESHOLD_HOP1_MASK_MASK 0x7FC0000
+
+/* PMMU_HBW_STLB_SET_THRESHOLD_HOP0 */
+#define PMMU_HBW_STLB_SET_THRESHOLD_HOP0_MIN_SHIFT 0
+#define PMMU_HBW_STLB_SET_THRESHOLD_HOP0_MIN_MASK 0x1FF
+#define PMMU_HBW_STLB_SET_THRESHOLD_HOP0_MAX_SHIFT 9
+#define PMMU_HBW_STLB_SET_THRESHOLD_HOP0_MAX_MASK 0x3FE00
+#define PMMU_HBW_STLB_SET_THRESHOLD_HOP0_MASK_SHIFT 18
+#define PMMU_HBW_STLB_SET_THRESHOLD_HOP0_MASK_MASK 0x7FC0000
+
+/* PMMU_HBW_STLB_MULTI_HIT_INTERRUPT_CLR */
+
+/* PMMU_HBW_STLB_MULTI_HIT_INTERRUPT_MASK */
+#define PMMU_HBW_STLB_MULTI_HIT_INTERRUPT_MASK_R_SHIFT 0
+#define PMMU_HBW_STLB_MULTI_HIT_INTERRUPT_MASK_R_MASK 0x1
+
+/* PMMU_HBW_STLB_MEM_L0_CACHE_CFG */
+#define PMMU_HBW_STLB_MEM_L0_CACHE_CFG_PLRU_EVICTION_SHIFT 0
+#define PMMU_HBW_STLB_MEM_L0_CACHE_CFG_PLRU_EVICTION_MASK 0x1
+#define PMMU_HBW_STLB_MEM_L0_CACHE_CFG_CACHE_STOP_SHIFT 1
+#define PMMU_HBW_STLB_MEM_L0_CACHE_CFG_CACHE_STOP_MASK 0x2
+#define PMMU_HBW_STLB_MEM_L0_CACHE_CFG_INV_WRITEBACK_SHIFT 2
+#define PMMU_HBW_STLB_MEM_L0_CACHE_CFG_INV_WRITEBACK_MASK 0x4
+
+/* PMMU_HBW_STLB_MEM_READ_ARPROT */
+#define PMMU_HBW_STLB_MEM_READ_ARPROT_R_SHIFT 0
+#define PMMU_HBW_STLB_MEM_READ_ARPROT_R_MASK 0x7
+
+/* PMMU_HBW_STLB_RANGE_CACHE_INVALIDATION */
+#define PMMU_HBW_STLB_RANGE_CACHE_INVALIDATION_RANGE_INVALIDATION_ENABLE_SHIFT 0
+#define PMMU_HBW_STLB_RANGE_CACHE_INVALIDATION_RANGE_INVALIDATION_ENABLE_MASK 0x1
+#define PMMU_HBW_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_EN_SHIFT 1
+#define PMMU_HBW_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_EN_MASK 0x2
+#define PMMU_HBW_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_SHIFT 2
+#define PMMU_HBW_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_MASK 0xFFC
+
+/* PMMU_HBW_STLB_RANGE_INV_START_LSB */
+#define PMMU_HBW_STLB_RANGE_INV_START_LSB_INV_START_LSB_SHIFT 0
+#define PMMU_HBW_STLB_RANGE_INV_START_LSB_INV_START_LSB_MASK 0xFFFFFFFF
+
+/* PMMU_HBW_STLB_RANGE_INV_START_MSB */
+#define PMMU_HBW_STLB_RANGE_INV_START_MSB_INV_START_MSB_SHIFT 0
+#define PMMU_HBW_STLB_RANGE_INV_START_MSB_INV_START_MSB_MASK 0xFFFFF
+
+/* PMMU_HBW_STLB_RANGE_INV_END_LSB */
+#define PMMU_HBW_STLB_RANGE_INV_END_LSB_INV_END_LSB_SHIFT 0
+#define PMMU_HBW_STLB_RANGE_INV_END_LSB_INV_END_LSB_MASK 0xFFFFFFFF
+
+/* PMMU_HBW_STLB_RANGE_INV_END_MSB */
+#define PMMU_HBW_STLB_RANGE_INV_END_MSB_INV_END_MSB_SHIFT 0
+#define PMMU_HBW_STLB_RANGE_INV_END_MSB_INV_END_MSB_MASK 0xFFFFF
+
+/* PMMU_HBW_STLB_ASID_SCRAMBLER_CTRL */
+#define PMMU_HBW_STLB_ASID_SCRAMBLER_CTRL_SCRAMBLER_SCRAM_EN_SHIFT 0
+#define PMMU_HBW_STLB_ASID_SCRAMBLER_CTRL_SCRAMBLER_SCRAM_EN_MASK 0x1
+
+/* PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_0 */
+#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_0_ASID_POLY_MATRIX_H3_SHIFT 0
+#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_0_ASID_POLY_MATRIX_H3_MASK 0x1FF
+
+/* PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_1 */
+#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_1_ASID_POLY_MATRIX_H3_SHIFT 0
+#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_1_ASID_POLY_MATRIX_H3_MASK 0x1FF
+
+/* PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_2 */
+#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_2_ASID_POLY_MATRIX_H3_SHIFT 0
+#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_2_ASID_POLY_MATRIX_H3_MASK 0x1FF
+
+/* PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_3 */
+#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_3_ASID_POLY_MATRIX_H3_SHIFT 0
+#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_3_ASID_POLY_MATRIX_H3_MASK 0x1FF
+
+/* PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_4 */
+#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_4_ASID_POLY_MATRIX_H3_SHIFT 0
+#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_4_ASID_POLY_MATRIX_H3_MASK 0x1FF
+
+/* PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_5 */
+#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_5_ASID_POLY_MATRIX_H3_SHIFT 0
+#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_5_ASID_POLY_MATRIX_H3_MASK 0x1FF
+
+/* PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_6 */
+#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_6_ASID_POLY_MATRIX_H3_SHIFT 0
+#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_6_ASID_POLY_MATRIX_H3_MASK 0x1FF
+
+/* PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_7 */
+#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_7_ASID_POLY_MATRIX_H3_SHIFT 0
+#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_7_ASID_POLY_MATRIX_H3_MASK 0x1FF
+
+/* PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_8 */
+#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_8_ASID_POLY_MATRIX_H3_SHIFT 0
+#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_8_ASID_POLY_MATRIX_H3_MASK 0x1FF
+
+/* PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_9 */
+#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_9_ASID_POLY_MATRIX_H3_SHIFT 0
+#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_9_ASID_POLY_MATRIX_H3_MASK 0x1FF
+
+/* PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_10 */
+#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_10_ASID_POLY_MATRIX_H3_SHIFT 0
+#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_10_ASID_POLY_MATRIX_H3_MASK 0x1FF
+
+/* PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_11 */
+#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_11_ASID_POLY_MATRIX_H3_SHIFT 0
+#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_11_ASID_POLY_MATRIX_H3_MASK 0x1FF
+
+/* PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_12 */
+#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_12_ASID_POLY_MATRIX_H3_SHIFT 0
+#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_12_ASID_POLY_MATRIX_H3_MASK 0x1FF
+
+/* PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_13 */
+#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_13_ASID_POLY_MATRIX_H3_SHIFT 0
+#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_13_ASID_POLY_MATRIX_H3_MASK 0x1FF
+
+/* PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_14 */
+#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_14_ASID_POLY_MATRIX_H3_SHIFT 0
+#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_14_ASID_POLY_MATRIX_H3_MASK 0x1FF
+
+/* PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_15 */
+#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_15_ASID_POLY_MATRIX_H3_SHIFT 0
+#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_15_ASID_POLY_MATRIX_H3_MASK 0x1FF
+
+/* PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_16 */
+#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_16_ASID_POLY_MATRIX_H3_SHIFT 0
+#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_16_ASID_POLY_MATRIX_H3_MASK 0x1FF
+
+/* PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_17 */
+#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_17_ASID_POLY_MATRIX_H3_SHIFT 0
+#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_17_ASID_POLY_MATRIX_H3_MASK 0x1FF
+
+/* PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_18 */
+#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_18_ASID_POLY_MATRIX_H3_SHIFT 0
+#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_18_ASID_POLY_MATRIX_H3_MASK 0x1FF
+
+#endif /* ASIC_REG_PMMU_HBW_STLB_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/pmmu_hbw_stlb_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pmmu_hbw_stlb_regs.h
new file mode 100644
index 000000000000..87c66c08e24a
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pmmu_hbw_stlb_regs.h
@@ -0,0 +1,141 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PMMU_HBW_STLB_REGS_H_
+#define ASIC_REG_PMMU_HBW_STLB_REGS_H_
+
+/*
+ *****************************************
+ *   PMMU_HBW_STLB
+ *   (Prototype: STLB)
+ *****************************************
+ */
+
+#define mmPMMU_HBW_STLB_BUSY 0x4D01000
+
+#define mmPMMU_HBW_STLB_ASID 0x4D01004
+
+#define mmPMMU_HBW_STLB_HOP0_PA43_12 0x4D01008
+
+#define mmPMMU_HBW_STLB_HOP0_PA63_44 0x4D0100C
+
+#define mmPMMU_HBW_STLB_CACHE_INV 0x4D01010
+
+#define mmPMMU_HBW_STLB_CACHE_INV_BASE_39_8 0x4D01014
+
+#define mmPMMU_HBW_STLB_CACHE_INV_BASE_63_40 0x4D01018
+
+#define mmPMMU_HBW_STLB_STLB_FEATURE_EN 0x4D0101C
+
+#define mmPMMU_HBW_STLB_STLB_AXI_CACHE 0x4D01020
+
+#define mmPMMU_HBW_STLB_HOP_CONFIGURATION 0x4D01024
+
+#define mmPMMU_HBW_STLB_LINK_LIST_LOOKUP_MASK_63_32 0x4D01028
+
+#define mmPMMU_HBW_STLB_LINK_LIST_LOOKUP_MASK_31_0 0x4D0102C
+
+#define mmPMMU_HBW_STLB_INV_ALL_START 0x4D01034
+
+#define mmPMMU_HBW_STLB_INV_ALL_SET 0x4D01038
+
+#define mmPMMU_HBW_STLB_INV_PS 0x4D0103C
+
+#define mmPMMU_HBW_STLB_INV_CONSUMER_INDEX 0x4D01040
+
+#define mmPMMU_HBW_STLB_INV_HIT_COUNT 0x4D01044
+
+#define mmPMMU_HBW_STLB_INV_SET 0x4D01048
+
+#define mmPMMU_HBW_STLB_SRAM_INIT 0x4D0104C
+
+#define mmPMMU_HBW_STLB_MEM_CACHE_INVALIDATION 0x4D01050
+
+#define mmPMMU_HBW_STLB_MEM_CACHE_INV_STATUS 0x4D01054
+
+#define mmPMMU_HBW_STLB_MEM_CACHE_BASE_38_7 0x4D01058
+
+#define mmPMMU_HBW_STLB_MEM_CACHE_BASE_63_39 0x4D0105C
+
+#define mmPMMU_HBW_STLB_MEM_CACHE_CONFIG 0x4D01060
+
+#define mmPMMU_HBW_STLB_SET_THRESHOLD_HOP5 0x4D01064
+
+#define mmPMMU_HBW_STLB_SET_THRESHOLD_HOP4 0x4D01068
+
+#define mmPMMU_HBW_STLB_SET_THRESHOLD_HOP3 0x4D0106C
+
+#define mmPMMU_HBW_STLB_SET_THRESHOLD_HOP2 0x4D01070
+
+#define mmPMMU_HBW_STLB_SET_THRESHOLD_HOP1 0x4D01074
+
+#define mmPMMU_HBW_STLB_SET_THRESHOLD_HOP0 0x4D01078
+
+#define mmPMMU_HBW_STLB_MULTI_HIT_INTERRUPT_CLR 0x4D0107C
+
+#define mmPMMU_HBW_STLB_MULTI_HIT_INTERRUPT_MASK 0x4D01080
+
+#define mmPMMU_HBW_STLB_MEM_L0_CACHE_CFG 0x4D01084
+
+#define mmPMMU_HBW_STLB_MEM_READ_ARPROT 0x4D01088
+
+#define mmPMMU_HBW_STLB_RANGE_CACHE_INVALIDATION 0x4D0108C
+
+#define mmPMMU_HBW_STLB_RANGE_INV_START_LSB 0x4D01090
+
+#define mmPMMU_HBW_STLB_RANGE_INV_START_MSB 0x4D01094
+
+#define mmPMMU_HBW_STLB_RANGE_INV_END_LSB 0x4D01098
+
+#define mmPMMU_HBW_STLB_RANGE_INV_END_MSB 0x4D0109C
+
+#define mmPMMU_HBW_STLB_ASID_SCRAMBLER_CTRL 0x4D01100
+
+#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_0 0x4D01104
+
+#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_1 0x4D01108
+
+#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_2 0x4D0110C
+
+#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_3 0x4D01110
+
+#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_4 0x4D01114
+
+#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_5 0x4D01118
+
+#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_6 0x4D0111C
+
+#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_7 0x4D01120
+
+#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_8 0x4D01124
+
+#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_9 0x4D01128
+
+#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_10 0x4D0112C
+
+#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_11 0x4D01130
+
+#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_12 0x4D01134
+
+#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_13 0x4D01138
+
+#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_14 0x4D0113C
+
+#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_15 0x4D01140
+
+#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_16 0x4D01144
+
+#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_17 0x4D01148
+
+#define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_18 0x4D0114C
+
+#endif /* ASIC_REG_PMMU_HBW_STLB_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/pmmu_pif_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pmmu_pif_regs.h
new file mode 100644
index 000000000000..dd12793734b4
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pmmu_pif_regs.h
@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PMMU_PIF_REGS_H_
+#define ASIC_REG_PMMU_PIF_REGS_H_
+
+/*
+ *****************************************
+ *   PMMU_PIF
+ *   (Prototype: PIF)
+ *****************************************
+ */
+
+#define mmPMMU_PIF_WR_CORE_CREDITS_THRESHOLD 0x4D03000
+
+#define mmPMMU_PIF_RD_CORE_CREDITS_THRESHOLD 0x4D03004
+
+#define mmPMMU_PIF_CORE_CREDITS_THRESHOLD 0x4D03008
+
+#define mmPMMU_PIF_CORE_SEPARATION_DISABLE 0x4D0300C
+
+#define mmPMMU_PIF_DISABLE_E2E_CREDITS 0x4D03010
+
+#define mmPMMU_PIF_RATE_LIMITER_ENABLE 0x4D03014
+
+#define mmPMMU_PIF_RATE_LIMITER_TOKEN_RESET 0x4D03018
+
+#define mmPMMU_PIF_RATE_LIMITER_SATURATION 0x4D0301C
+
+#define mmPMMU_PIF_RATE_LIMITER_TIMEOUT_LSB 0x4D03020
+
+#define mmPMMU_PIF_RATE_LIMITER_TIMEOUT_MSB 0x4D03024
+
+#define mmPMMU_PIF_ARB_TYPE 0x4D03028
+
+#define mmPMMU_PIF_CLOCK_GATE_CONFIG 0x4D0302C
+
+#define mmPMMU_PIF_CLOCK_GATE_ACTIVE 0x4D03030
+
+#define mmPMMU_PIF_SPI_INTERRUPT_CAUSE 0x4D03034
+
+#define mmPMMU_PIF_SPI_INTERRUPT_CAUSE_MASK 0x4D03038
+
+#define mmPMMU_PIF_SPI_INTERRUPT_REG 0x4D0303C
+
+#define mmPMMU_PIF_SPI_INTERRUPT_MASK 0x4D03040
+
+#define mmPMMU_PIF_SEI_INTERRUPT_CAUSE 0x4D03044
+
+#define mmPMMU_PIF_SEI_INTERRUPT_CAUSE_MASK 0x4D03048
+
+#define mmPMMU_PIF_SEI_INTERRUPT_REG 0x4D0304C
+
+#define mmPMMU_PIF_SEI_INTERRUPT_MASK 0x4D03050
+
+#define mmPMMU_PIF_DEBUG_BUFFER_CNT_CTRL 0x4D03054
+
+#define mmPMMU_PIF_DEBUG_WR_BUF_CNT 0x4D03058
+
+#define mmPMMU_PIF_DEBUG_RD_BUF_CNT 0x4D0305C
+
+#define mmPMMU_PIF_DEBUG_WR_CORE_BUF_CNT 0x4D03060
+
+#define mmPMMU_PIF_DEBUG_RD_CORE_BUF_CNT 0x4D03070
+
+#define mmPMMU_PIF_DEBUG_WR_BUF_FULL 0x4D03080
+
+#define mmPMMU_PIF_DEBUG_RD_BUF_FULL 0x4D03084
+
+#define mmPMMU_PIF_E2E_ROUTING_CFG 0x4D03090
+
+#define mmPMMU_PIF_E2E_ROUTING_CFG2 0x4D03094
+
+#define mmPMMU_PIF_SPI_INTERRUPT_CLEAR 0x4D03100
+
+#define mmPMMU_PIF_SEI_INTERRUPT_CLEAR 0x4D03104
+
+#define mmPMMU_PIF_BASE_ADDR_PMMU 0x4D03200
+
+#define mmPMMU_PIF_ADDR_MASK_PMMU 0x4D03204
+
+#define mmPMMU_PIF_BASE_ADDR_PCI0 0x4D03208
+
+#define mmPMMU_PIF_ADDR_MASK_PCI0 0x4D0320C
+
+#define mmPMMU_PIF_BASE_ADDR_PCI2 0x4D03210
+
+#define mmPMMU_PIF_ADDR_MASK_PCI1 0x4D03214
+
+#define mmPMMU_PIF_BASE_ADDR_PCI1 0x4D03218
+
+#define mmPMMU_PIF_ADDR_MASK_PCI2 0x4D0321C
+
+#define mmPMMU_PIF_BASE_ADDR_TPC 0x4D03220
+
+#define mmPMMU_PIF_ADDR_MASK_TPC 0x4D03224
+
+#define mmPMMU_PIF_BASE_ADDR_DEC0 0x4D03228
+
+#define mmPMMU_PIF_ADDR_MASK_DEC0 0x4D0322C
+
+#define mmPMMU_PIF_BASE_ADDR_DEC1 0x4D03230
+
+#define mmPMMU_PIF_ADDR_MASK_DEC1 0x4D03234
+
+#define mmPMMU_PIF_PMMU_DBG_BASE_ADDR 0x4D03300
+
+#define mmPMMU_PIF_PMMU_DBG_ADDR_MASK 0x4D03304
+
+#define mmPMMU_PIF_PCI_DBG_BASE_ADDR 0x4D03308
+
+#define mmPMMU_PIF_PCI_DBG_ADDR_MASK 0x4D0330C
+
+#define mmPMMU_PIF_DEC0_DBG_BASE_ADDR 0x4D03310
+
+#define mmPMMU_PIF_DEC0_DBG_ADDR_MASK 0x4D03314
+
+#define mmPMMU_PIF_DEC1_DBG_BASE_ADDR 0x4D03318
+
+#define mmPMMU_PIF_DEC1_DBG_ADDR_MASK 0x4D0331C
+
+#define mmPMMU_PIF_TPC_DBG_BASE_ADDR 0x4D03320
+
+#define mmPMMU_PIF_TPC_DBG_ADDR_MASK 0x4D03324
+
+#endif /* ASIC_REG_PMMU_PIF_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/psoc_etr_masks.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/psoc_etr_masks.h
new file mode 100644
index 000000000000..42e67c1059c4
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/psoc_etr_masks.h
@@ -0,0 +1,311 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PSOC_ETR_MASKS_H_
+#define ASIC_REG_PSOC_ETR_MASKS_H_
+
+/*
+ *****************************************
+ *   PSOC_ETR
+ *   (Prototype: ETR)
+ *****************************************
+ */
+
+/* PSOC_ETR_RSZ */
+#define PSOC_ETR_RSZ_RSZ_ETR_SHIFT 0
+#define PSOC_ETR_RSZ_RSZ_ETR_MASK 0x7FFFFFFF
+
+/* PSOC_ETR_STS */
+#define PSOC_ETR_STS_FULL_SHIFT 0
+#define PSOC_ETR_STS_FULL_MASK 0x1
+#define PSOC_ETR_STS_TRIGGERED_SHIFT 1
+#define PSOC_ETR_STS_TRIGGERED_MASK 0x2
+#define PSOC_ETR_STS_TMCREADY_SHIFT 2
+#define PSOC_ETR_STS_TMCREADY_MASK 0x4
+#define PSOC_ETR_STS_FTEMPTY_SHIFT 3
+#define PSOC_ETR_STS_FTEMPTY_MASK 0x8
+#define PSOC_ETR_STS_EMPTY_SHIFT 4
+#define PSOC_ETR_STS_EMPTY_MASK 0x10
+#define PSOC_ETR_STS_MEMERR_SHIFT 5
+#define PSOC_ETR_STS_MEMERR_MASK 0x20
+
+/* PSOC_ETR_RRD */
+#define PSOC_ETR_RRD_RRD_SHIFT 0
+#define PSOC_ETR_RRD_RRD_MASK 0xFFFFFFFF
+
+/* PSOC_ETR_RRP */
+#define PSOC_ETR_RRP_RRP_SHIFT 0
+#define PSOC_ETR_RRP_RRP_MASK 0xFFFFFFFF
+
+/* PSOC_ETR_RWP */
+#define PSOC_ETR_RWP_RWP_SHIFT 0
+#define PSOC_ETR_RWP_RWP_MASK 0xFFFFFFFF
+
+/* PSOC_ETR_TRG */
+#define PSOC_ETR_TRG_TRG_SHIFT 0
+#define PSOC_ETR_TRG_TRG_MASK 0xFFFFFFFF
+
+/* PSOC_ETR_CTL */
+#define PSOC_ETR_CTL_TRACECAPTEN_SHIFT 0
+#define PSOC_ETR_CTL_TRACECAPTEN_MASK 0x1
+
+/* PSOC_ETR_RWD */
+#define PSOC_ETR_RWD_RWD_SHIFT 0
+#define PSOC_ETR_RWD_RWD_MASK 0xFFFFFFFF
+
+/* PSOC_ETR_MODE */
+#define PSOC_ETR_MODE_MODE_SHIFT 0
+#define PSOC_ETR_MODE_MODE_MASK 0x3
+
+/* PSOC_ETR_LBUFLEVEL */
+#define PSOC_ETR_LBUFLEVEL_LBUFLEVEL_SHIFT 0
+#define PSOC_ETR_LBUFLEVEL_LBUFLEVEL_MASK 0x7FFFFFFF
+
+/* PSOC_ETR_CBUFLEVEL */
+#define PSOC_ETR_CBUFLEVEL_CBUFLEVEL_SHIFT 0
+#define PSOC_ETR_CBUFLEVEL_CBUFLEVEL_MASK 0x7FFFFFFF
+
+/* PSOC_ETR_BUFWM */
+#define PSOC_ETR_BUFWM_BUFWM_SHIFT 0
+#define PSOC_ETR_BUFWM_BUFWM_MASK 0x3FFFFFFF
+
+/* PSOC_ETR_RRPHI */
+#define PSOC_ETR_RRPHI_RRPHI_SHIFT 0
+#define PSOC_ETR_RRPHI_RRPHI_MASK 0xFF
+
+/* PSOC_ETR_RWPHI */
+#define PSOC_ETR_RWPHI_RWPHI_SHIFT 0
+#define PSOC_ETR_RWPHI_RWPHI_MASK 0xFF
+
+/* PSOC_ETR_AXICTL */
+#define PSOC_ETR_AXICTL_PROTCTRLBIT0_SHIFT 0
+#define PSOC_ETR_AXICTL_PROTCTRLBIT0_MASK 0x1
+#define PSOC_ETR_AXICTL_PROTCTRLBIT1_SHIFT 1
+#define PSOC_ETR_AXICTL_PROTCTRLBIT1_MASK 0x2
+#define PSOC_ETR_AXICTL_CACHECTRLBIT0_SHIFT 2
+#define PSOC_ETR_AXICTL_CACHECTRLBIT0_MASK 0x4
+#define PSOC_ETR_AXICTL_CACHECTRLBIT1_SHIFT 3
+#define PSOC_ETR_AXICTL_CACHECTRLBIT1_MASK 0x8
+#define PSOC_ETR_AXICTL_CACHECTRLBIT2_SHIFT 4
+#define PSOC_ETR_AXICTL_CACHECTRLBIT2_MASK 0x10
+#define PSOC_ETR_AXICTL_CACHECTRLBIT3_SHIFT 5
+#define PSOC_ETR_AXICTL_CACHECTRLBIT3_MASK 0x20
+#define PSOC_ETR_AXICTL_SCATTERGATHERMODE_SHIFT 7
+#define PSOC_ETR_AXICTL_SCATTERGATHERMODE_MASK 0x80
+#define PSOC_ETR_AXICTL_WRBURSTLEN_SHIFT 8
+#define PSOC_ETR_AXICTL_WRBURSTLEN_MASK 0xF00
+
+/* PSOC_ETR_DBALO */
+#define PSOC_ETR_DBALO_BUFADDRLO_SHIFT 0
+#define PSOC_ETR_DBALO_BUFADDRLO_MASK 0xFFFFFFFF
+
+/* PSOC_ETR_DBAHI */
+#define PSOC_ETR_DBAHI_BUFADDRHI_SHIFT 0
+#define PSOC_ETR_DBAHI_BUFADDRHI_MASK 0xFF
+
+/* PSOC_ETR_FFSR */
+#define PSOC_ETR_FFSR_FLINPROG_SHIFT 0
+#define PSOC_ETR_FFSR_FLINPROG_MASK 0x1
+#define PSOC_ETR_FFSR_FTSTOPPED_SHIFT 1
+#define PSOC_ETR_FFSR_FTSTOPPED_MASK 0x2
+
+/* PSOC_ETR_FFCR */
+#define PSOC_ETR_FFCR_ENFT_SHIFT 0
+#define PSOC_ETR_FFCR_ENFT_MASK 0x1
+#define PSOC_ETR_FFCR_ENTI_SHIFT 1
+#define PSOC_ETR_FFCR_ENTI_MASK 0x2
+#define PSOC_ETR_FFCR_FONFLIN_SHIFT 4
+#define PSOC_ETR_FFCR_FONFLIN_MASK 0x10
+#define PSOC_ETR_FFCR_FONTRIGEVT_SHIFT 5
+#define PSOC_ETR_FFCR_FONTRIGEVT_MASK 0x20
+#define PSOC_ETR_FFCR_FLUSHMAN_SHIFT 6
+#define PSOC_ETR_FFCR_FLUSHMAN_MASK 0x40
+#define PSOC_ETR_FFCR_TRIGONTRIGIN_SHIFT 8
+#define PSOC_ETR_FFCR_TRIGONTRIGIN_MASK 0x100
+#define PSOC_ETR_FFCR_TRIGONTRIGEVT_SHIFT 9
+#define PSOC_ETR_FFCR_TRIGONTRIGEVT_MASK 0x200
+#define PSOC_ETR_FFCR_TRIGONFL_SHIFT 10
+#define PSOC_ETR_FFCR_TRIGONFL_MASK 0x400
+#define PSOC_ETR_FFCR_STOPONFL_SHIFT 12
+#define PSOC_ETR_FFCR_STOPONFL_MASK 0x1000
+#define PSOC_ETR_FFCR_STOPONTRIGEVT_SHIFT 13
+#define PSOC_ETR_FFCR_STOPONTRIGEVT_MASK 0x2000
+
+/* PSOC_ETR_PSCR */
+#define PSOC_ETR_PSCR_PSCOUNT_SHIFT 0
+#define PSOC_ETR_PSCR_PSCOUNT_MASK 0x1F
+
+/* PSOC_ETR_ITMISCOP0 */
+#define PSOC_ETR_ITMISCOP0_ACQCOMP_SHIFT 0
+#define PSOC_ETR_ITMISCOP0_ACQCOMP_MASK 0x1
+#define PSOC_ETR_ITMISCOP0_FULL_SHIFT 1
+#define PSOC_ETR_ITMISCOP0_FULL_MASK 0x2
+
+/* PSOC_ETR_ITTRFLIN */
+#define PSOC_ETR_ITTRFLIN_TRIGIN_SHIFT 0
+#define PSOC_ETR_ITTRFLIN_TRIGIN_MASK 0x1
+#define PSOC_ETR_ITTRFLIN_FLUSHIN_SHIFT 1
+#define PSOC_ETR_ITTRFLIN_FLUSHIN_MASK 0x2
+
+/* PSOC_ETR_ITATBDATA0 */
+#define PSOC_ETR_ITATBDATA0_ATDATASBIT0_SHIFT 0
+#define PSOC_ETR_ITATBDATA0_ATDATASBIT0_MASK 0x1
+#define PSOC_ETR_ITATBDATA0_ATDATASBIT7_SHIFT 1
+#define PSOC_ETR_ITATBDATA0_ATDATASBIT7_MASK 0x2
+#define PSOC_ETR_ITATBDATA0_ATDATASBIT15_SHIFT 2
+#define PSOC_ETR_ITATBDATA0_ATDATASBIT15_MASK 0x4
+#define PSOC_ETR_ITATBDATA0_ATDATASBIT23_SHIFT 3
+#define PSOC_ETR_ITATBDATA0_ATDATASBIT23_MASK 0x8
+#define PSOC_ETR_ITATBDATA0_ATDATASBIT31_SHIFT 4
+#define PSOC_ETR_ITATBDATA0_ATDATASBIT31_MASK 0x10
+#define PSOC_ETR_ITATBDATA0_ATDATASBIT39_SHIFT 5
+#define PSOC_ETR_ITATBDATA0_ATDATASBIT39_MASK 0x20
+#define PSOC_ETR_ITATBDATA0_ATDATASBIT47_SHIFT 6
+#define PSOC_ETR_ITATBDATA0_ATDATASBIT47_MASK 0x40
+#define PSOC_ETR_ITATBDATA0_ATDATASBIT55_SHIFT 7
+#define PSOC_ETR_ITATBDATA0_ATDATASBIT55_MASK 0x80
+#define PSOC_ETR_ITATBDATA0_ATDATASBIT63_SHIFT 8
+#define PSOC_ETR_ITATBDATA0_ATDATASBIT63_MASK 0x100
+
+/* PSOC_ETR_ITATBCTR2 */
+#define PSOC_ETR_ITATBCTR2_ATREADYS_SHIFT 0
+#define PSOC_ETR_ITATBCTR2_ATREADYS_MASK 0x1
+#define PSOC_ETR_ITATBCTR2_AFVALIDS_SHIFT 1
+#define PSOC_ETR_ITATBCTR2_AFVALIDS_MASK 0x2
+#define PSOC_ETR_ITATBCTR2_SYNCREQS_SHIFT 2
+#define PSOC_ETR_ITATBCTR2_SYNCREQS_MASK 0x4
+
+/* PSOC_ETR_ITATBCTR1 */
+#define PSOC_ETR_ITATBCTR1_ATIDS_SHIFT 0
+#define PSOC_ETR_ITATBCTR1_ATIDS_MASK 0x7F
+
+/* PSOC_ETR_ITATBCTR0 */
+#define PSOC_ETR_ITATBCTR0_ATVALIDS_SHIFT 0
+#define PSOC_ETR_ITATBCTR0_ATVALIDS_MASK 0x1
+#define PSOC_ETR_ITATBCTR0_AFREADYS_SHIFT 1
+#define PSOC_ETR_ITATBCTR0_AFREADYS_MASK 0x2
+#define PSOC_ETR_ITATBCTR0_ATBYTESS_SHIFT 8
+#define PSOC_ETR_ITATBCTR0_ATBYTESS_MASK 0x700
+
+/* PSOC_ETR_ITCTRL */
+#define PSOC_ETR_ITCTRL_INTEGRATION_MODE_SHIFT 0
+#define PSOC_ETR_ITCTRL_INTEGRATION_MODE_MASK 0x1
+
+/* PSOC_ETR_CLAIMSET */
+#define PSOC_ETR_CLAIMSET_CLAIMSET_SHIFT 0
+#define PSOC_ETR_CLAIMSET_CLAIMSET_MASK 0xF
+
+/* PSOC_ETR_CLAIMCLR */
+#define PSOC_ETR_CLAIMCLR_CLAIMCLR_SHIFT 0
+#define PSOC_ETR_CLAIMCLR_CLAIMCLR_MASK 0xF
+
+/* PSOC_ETR_LAR */
+#define PSOC_ETR_LAR_ACCESS_W_SHIFT 0
+#define PSOC_ETR_LAR_ACCESS_W_MASK 0xFFFFFFFF
+
+/* PSOC_ETR_LSR */
+#define PSOC_ETR_LSR_LOCKEXIST_SHIFT 0
+#define PSOC_ETR_LSR_LOCKEXIST_MASK 0x1
+#define PSOC_ETR_LSR_LOCKGRANT_SHIFT 1
+#define PSOC_ETR_LSR_LOCKGRANT_MASK 0x2
+#define PSOC_ETR_LSR_LOCKTYPE_SHIFT 2
+#define PSOC_ETR_LSR_LOCKTYPE_MASK 0x4
+
+/* PSOC_ETR_AUTHSTATUS */
+#define PSOC_ETR_AUTHSTATUS_NSID_SHIFT 0
+#define PSOC_ETR_AUTHSTATUS_NSID_MASK 0x3
+#define PSOC_ETR_AUTHSTATUS_NSNID_SHIFT 2
+#define PSOC_ETR_AUTHSTATUS_NSNID_MASK 0xC
+#define PSOC_ETR_AUTHSTATUS_SID_SHIFT 4
+#define PSOC_ETR_AUTHSTATUS_SID_MASK 0x30
+#define PSOC_ETR_AUTHSTATUS_SNID_SHIFT 6
+#define PSOC_ETR_AUTHSTATUS_SNID_MASK 0xC0
+
+/* PSOC_ETR_DEVID */
+#define PSOC_ETR_DEVID_ATBINPORTCOUNT_SHIFT 0
+#define PSOC_ETR_DEVID_ATBINPORTCOUNT_MASK 0x1F
+#define PSOC_ETR_DEVID_CLKSCHEME_SHIFT 5
+#define PSOC_ETR_DEVID_CLKSCHEME_MASK 0x20
+#define PSOC_ETR_DEVID_CONFIGTYPE_SHIFT 6
+#define PSOC_ETR_DEVID_CONFIGTYPE_MASK 0xC0
+#define PSOC_ETR_DEVID_MEMWIDTH_SHIFT 8
+#define PSOC_ETR_DEVID_MEMWIDTH_MASK 0x700
+#define PSOC_ETR_DEVID_WBUF_DEPTH_SHIFT 11
+#define PSOC_ETR_DEVID_WBUF_DEPTH_MASK 0x3800
+
+/* PSOC_ETR_DEVTYPE */
+#define PSOC_ETR_DEVTYPE_MAJOR_TYPE_SHIFT 0
+#define PSOC_ETR_DEVTYPE_MAJOR_TYPE_MASK 0xF
+#define PSOC_ETR_DEVTYPE_SUB_TYPE_SHIFT 4
+#define PSOC_ETR_DEVTYPE_SUB_TYPE_MASK 0xF0
+
+/* PSOC_ETR_PERIPHID4 */
+#define PSOC_ETR_PERIPHID4_JEP106_CONT_SHIFT 0
+#define PSOC_ETR_PERIPHID4_JEP106_CONT_MASK 0xF
+#define PSOC_ETR_PERIPHID4_FOURKB_COUNT_SHIFT 4
+#define PSOC_ETR_PERIPHID4_FOURKB_COUNT_MASK 0xF0
+
+/* PSOC_ETR_PERIPHID5 */
+#define PSOC_ETR_PERIPHID5_PERIPHID5_SHIFT 0
+#define PSOC_ETR_PERIPHID5_PERIPHID5_MASK 0xFFFFFFFF
+
+/* PSOC_ETR_PERIPHID6 */
+#define PSOC_ETR_PERIPHID6_PERIPHID6_SHIFT 0
+#define PSOC_ETR_PERIPHID6_PERIPHID6_MASK 0xFFFFFFFF
+
+/* PSOC_ETR_PERIPHID7 */
+#define PSOC_ETR_PERIPHID7_PERIPHID7_SHIFT 0
+#define PSOC_ETR_PERIPHID7_PERIPHID7_MASK 0xFFFFFFFF
+
+/* PSOC_ETR_PERIPHID0 */
+#define PSOC_ETR_PERIPHID0_PART_NUMBER_BITS7TO0_SHIFT 0
+#define PSOC_ETR_PERIPHID0_PART_NUMBER_BITS7TO0_MASK 0xFF
+
+/* PSOC_ETR_PERIPHID1 */
+#define PSOC_ETR_PERIPHID1_PART_NUMBER_BITS11TO8_SHIFT 0
+#define PSOC_ETR_PERIPHID1_PART_NUMBER_BITS11TO8_MASK 0xF
+#define PSOC_ETR_PERIPHID1_JEP106_BITS3TO0_SHIFT 4
+#define PSOC_ETR_PERIPHID1_JEP106_BITS3TO0_MASK 0xF0
+
+/* PSOC_ETR_PERIPHID2 */
+#define PSOC_ETR_PERIPHID2_JEP106_BITS6TO4_SHIFT 0
+#define PSOC_ETR_PERIPHID2_JEP106_BITS6TO4_MASK 0x7
+#define PSOC_ETR_PERIPHID2_JEDEC_SHIFT 3
+#define PSOC_ETR_PERIPHID2_JEDEC_MASK 0x8
+#define PSOC_ETR_PERIPHID2_REVISION_SHIFT 4
+#define PSOC_ETR_PERIPHID2_REVISION_MASK 0xF0
+
+/* PSOC_ETR_PERIPHID3 */
+#define PSOC_ETR_PERIPHID3_CUSTOMER_MODIFIED_SHIFT 0
+#define PSOC_ETR_PERIPHID3_CUSTOMER_MODIFIED_MASK 0xF
+#define PSOC_ETR_PERIPHID3_REVAND_SHIFT 4
+#define PSOC_ETR_PERIPHID3_REVAND_MASK 0xF0
+
+/* PSOC_ETR_COMPID0 */
+#define PSOC_ETR_COMPID0_PREAMBLE_SHIFT 0
+#define PSOC_ETR_COMPID0_PREAMBLE_MASK 0xFF
+
+/* PSOC_ETR_COMPID1 */
+#define PSOC_ETR_COMPID1_PREAMBLE_SHIFT 0
+#define PSOC_ETR_COMPID1_PREAMBLE_MASK 0xF
+#define PSOC_ETR_COMPID1_F_CLASS_SHIFT 4
+#define PSOC_ETR_COMPID1_F_CLASS_MASK 0xF0
+
+/* PSOC_ETR_COMPID2 */
+#define PSOC_ETR_COMPID2_PREAMBLE_SHIFT 0
+#define PSOC_ETR_COMPID2_PREAMBLE_MASK 0xFF
+
+/* PSOC_ETR_COMPID3 */
+#define PSOC_ETR_COMPID3_PREAMBLE_SHIFT 0
+#define PSOC_ETR_COMPID3_PREAMBLE_MASK 0xFF
+
+#endif /* ASIC_REG_PSOC_ETR_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/psoc_etr_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/psoc_etr_regs.h
new file mode 100644
index 000000000000..980a3e0054c5
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/psoc_etr_regs.h
@@ -0,0 +1,115 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PSOC_ETR_REGS_H_
+#define ASIC_REG_PSOC_ETR_REGS_H_
+
+/*
+ *****************************************
+ *   PSOC_ETR
+ *   (Prototype: ETR)
+ *****************************************
+ */
+
+#define mmPSOC_ETR_RSZ 0x6C44004
+
+#define mmPSOC_ETR_STS 0x6C4400C
+
+#define mmPSOC_ETR_RRD 0x6C44010
+
+#define mmPSOC_ETR_RRP 0x6C44014
+
+#define mmPSOC_ETR_RWP 0x6C44018
+
+#define mmPSOC_ETR_TRG 0x6C4401C
+
+#define mmPSOC_ETR_CTL 0x6C44020
+
+#define mmPSOC_ETR_RWD 0x6C44024
+
+#define mmPSOC_ETR_MODE 0x6C44028
+
+#define mmPSOC_ETR_LBUFLEVEL 0x6C4402C
+
+#define mmPSOC_ETR_CBUFLEVEL 0x6C44030
+
+#define mmPSOC_ETR_BUFWM 0x6C44034
+
+#define mmPSOC_ETR_RRPHI 0x6C44038
+
+#define mmPSOC_ETR_RWPHI 0x6C4403C
+
+#define mmPSOC_ETR_AXICTL 0x6C44110
+
+#define mmPSOC_ETR_DBALO 0x6C44118
+
+#define mmPSOC_ETR_DBAHI 0x6C4411C
+
+#define mmPSOC_ETR_FFSR 0x6C44300
+
+#define mmPSOC_ETR_FFCR 0x6C44304
+
+#define mmPSOC_ETR_PSCR 0x6C44308
+
+#define mmPSOC_ETR_ITMISCOP0 0x6C44EE0
+
+#define mmPSOC_ETR_ITTRFLIN 0x6C44EE8
+
+#define mmPSOC_ETR_ITATBDATA0 0x6C44EEC
+
+#define mmPSOC_ETR_ITATBCTR2 0x6C44EF0
+
+#define mmPSOC_ETR_ITATBCTR1 0x6C44EF4
+
+#define mmPSOC_ETR_ITATBCTR0 0x6C44EF8
+
+#define mmPSOC_ETR_ITCTRL 0x6C44F00
+
+#define mmPSOC_ETR_CLAIMSET 0x6C44FA0
+
+#define mmPSOC_ETR_CLAIMCLR 0x6C44FA4
+
+#define mmPSOC_ETR_LAR 0x6C44FB0
+
+#define mmPSOC_ETR_LSR 0x6C44FB4
+
+#define mmPSOC_ETR_AUTHSTATUS 0x6C44FB8
+
+#define mmPSOC_ETR_DEVID 0x6C44FC8
+
+#define mmPSOC_ETR_DEVTYPE 0x6C44FCC
+
+#define mmPSOC_ETR_PERIPHID4 0x6C44FD0
+
+#define mmPSOC_ETR_PERIPHID5 0x6C44FD4
+
+#define mmPSOC_ETR_PERIPHID6 0x6C44FD8
+
+#define mmPSOC_ETR_PERIPHID7 0x6C44FDC
+
+#define mmPSOC_ETR_PERIPHID0 0x6C44FE0
+
+#define mmPSOC_ETR_PERIPHID1 0x6C44FE4
+
+#define mmPSOC_ETR_PERIPHID2 0x6C44FE8
+
+#define mmPSOC_ETR_PERIPHID3 0x6C44FEC
+
+#define mmPSOC_ETR_COMPID0 0x6C44FF0
+
+#define mmPSOC_ETR_COMPID1 0x6C44FF4
+
+#define mmPSOC_ETR_COMPID2 0x6C44FF8
+
+#define mmPSOC_ETR_COMPID3 0x6C44FFC
+
+#endif /* ASIC_REG_PSOC_ETR_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/psoc_global_conf_masks.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/psoc_global_conf_masks.h
new file mode 100644
index 000000000000..85a81e2cb546
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/psoc_global_conf_masks.h
@@ -0,0 +1,1397 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_
+#define ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_
+
+/*
+ *****************************************
+ *   PSOC_GLOBAL_CONF
+ *   (Prototype: GLOBAL_CONF)
+ *****************************************
+ */
+
+/* PSOC_GLOBAL_CONF_NON_RST_FLOPS */
+#define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_PCI_FW_FSM */
+#define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_SHIFT 0
+#define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START */
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_MASK 0x1
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_MNL_RST_IND_SHIFT 4
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_MNL_RST_IND_MASK 0x10
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_WD_RST_IND_SHIFT 5
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_WD_RST_IND_MASK 0x20
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_SW_RST_IND_SHIFT 6
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_SW_RST_IND_MASK 0x40
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_SOFT_RST_IND_SHIFT 7
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_SOFT_RST_IND_MASK 0x80
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_PRST_RST_IND_SHIFT 8
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_PRST_RST_IND_MASK 0x100
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_FLR_RST_IND_SHIFT 9
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_FLR_RST_IND_MASK 0x200
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_FW_RST_IND_SHIFT 10
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_FW_RST_IND_MASK 0x400
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_ECC_DERR_RST_IND_SHIFT 11
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_ECC_DERR_RST_IND_MASK 0x800
+
+/* PSOC_GLOBAL_CONF_BTM_FSM */
+#define PSOC_GLOBAL_CONF_BTM_FSM_STATE_SHIFT 0
+#define PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK 0x1F
+
+/* PSOC_GLOBAL_CONF_BTL_ROM_DELAY */
+#define PSOC_GLOBAL_CONF_BTL_ROM_DELAY_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_BTL_ROM_DELAY_VAL_MASK 0xFFFF
+
+/* PSOC_GLOBAL_CONF_SW_BTM_FSM */
+#define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_SHIFT 0
+#define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_MASK 0x1F
+
+/* PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM */
+#define PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM_CTRL_SHIFT 0
+#define PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM_CTRL_MASK 0x1F
+
+/* PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT */
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_QSPI_SPI */
+#define PSOC_GLOBAL_CONF_QSPI_SPI_SEL_SHIFT 0
+#define PSOC_GLOBAL_CONF_QSPI_SPI_SEL_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_SPI_MEM_EN */
+#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_SPI_SHIFT 0
+#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_SPI_MASK 0x1
+#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_QSPI_SHIFT 1
+#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_QSPI_MASK 0x2
+
+/* PSOC_GLOBAL_CONF_PRSTN */
+#define PSOC_GLOBAL_CONF_PRSTN_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_PRSTN_VAL_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_PCIE_EN */
+#define PSOC_GLOBAL_CONF_PCIE_EN_MASK_SHIFT 0
+#define PSOC_GLOBAL_CONF_PCIE_EN_MASK_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR */
+#define PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR_IND_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_SPI_IMG_STS */
+#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SPI_PRI_SHIFT 0
+#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SPI_PRI_MASK 0x3
+#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SPI_SEC_SHIFT 2
+#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SPI_SEC_MASK 0xC
+#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_PRI_SHIFT 4
+#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_PRI_MASK 0x30
+#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_SEC_SHIFT 6
+#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_SEC_MASK 0xC0
+#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCIE_PRI_SHIFT 8
+#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCIE_PRI_MASK 0x300
+#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCIE_SEC_SHIFT 10
+#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCIE_SEC_MASK 0xC00
+#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRE_SPI_PRI_SHIFT 12
+#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRE_SPI_PRI_MASK 0x3000
+#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRE_PRSTN_PRI_SHIFT 14
+#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRE_PRSTN_PRI_MASK 0xC000
+#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRE_SPI_SEC_SHIFT 16
+#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRE_SPI_SEC_MASK 0x30000
+#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRE_PRSTN_SEC_SHIFT 18
+#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRE_PRSTN_SEC_MASK 0xC0000
+
+/* PSOC_GLOBAL_CONF_BOOT_SEQ_FSM */
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_IDLE_SHIFT 0
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_IDLE_MASK 0x1
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_BOOT_INIT_SHIFT 1
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_BOOT_INIT_MASK 0x2
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRI_SHIFT 2
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRI_MASK 0x4
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_SEC_SHIFT 3
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_SEC_MASK 0x8
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRSTN_SHIFT 4
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRSTN_MASK 0x10
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PCIE_SHIFT 5
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PCIE_MASK 0x20
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_ROM_SHIFT 6
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_ROM_MASK 0x40
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_PCLK_READY_SHIFT 7
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_PCLK_READY_MASK 0x80
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_LTSSM_EN_SHIFT 8
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_LTSSM_EN_MASK 0x100
+
+/* PSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD */
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD_DONE_SHIFT 0
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD_DONE_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_QSPI_SPI_BOOTSEQ_RST */
+#define PSOC_GLOBAL_CONF_QSPI_SPI_BOOTSEQ_RST_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_QSPI_SPI_BOOTSEQ_RST_VAL_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_PHY_STABLE */
+#define PSOC_GLOBAL_CONF_PHY_STABLE_PRSTN_SHIFT 0
+#define PSOC_GLOBAL_CONF_PHY_STABLE_PRSTN_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_PRSTN_OVR */
+#define PSOC_GLOBAL_CONF_PRSTN_OVR_EN_SHIFT 0
+#define PSOC_GLOBAL_CONF_PRSTN_OVR_EN_MASK 0x1
+#define PSOC_GLOBAL_CONF_PRSTN_OVR_VAL_SHIFT 4
+#define PSOC_GLOBAL_CONF_PRSTN_OVR_VAL_MASK 0x10
+
+/* PSOC_GLOBAL_CONF_ETR_FLUSH */
+#define PSOC_GLOBAL_CONF_ETR_FLUSH_MASK_SHIFT 0
+#define PSOC_GLOBAL_CONF_ETR_FLUSH_MASK_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_ANY_RST */
+#define PSOC_GLOBAL_CONF_ANY_RST_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_ANY_RST_IND_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_COLD_RST_FLOPS */
+#define PSOC_GLOBAL_CONF_COLD_RST_FLOPS_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_COLD_RST_FLOPS_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_DIS_RAZWI_ERR */
+#define PSOC_GLOBAL_CONF_DIS_RAZWI_ERR_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_DIS_RAZWI_ERR_IND_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_PCIE_PHY_RST_N */
+#define PSOC_GLOBAL_CONF_PCIE_PHY_RST_N_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_PCIE_PHY_RST_N_IND_MASK 0x1
+#define PSOC_GLOBAL_CONF_PCIE_PHY_RST_N_CLK_DIS_SHIFT 16
+#define PSOC_GLOBAL_CONF_PCIE_PHY_RST_N_CLK_DIS_MASK 0x10000
+
+/* PSOC_GLOBAL_CONF_RAZWI_INTERRUPT */
+#define PSOC_GLOBAL_CONF_RAZWI_INTERRUPT_INTR_SHIFT 0
+#define PSOC_GLOBAL_CONF_RAZWI_INTERRUPT_INTR_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_RAZWI_MASK_INFO */
+#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_MASK_SHIFT 0
+#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_MASK_MASK 0x1
+#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_WAS_AR_SHIFT 1
+#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_WAS_AR_MASK 0x2
+#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_WAS_AW_SHIFT 2
+#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_WAS_AW_MASK 0x4
+#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_AXUSER_L_SHIFT 4
+#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_AXUSER_L_MASK 0x3FF0
+#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_AXUSER_H_SHIFT 16
+#define PSOC_GLOBAL_CONF_RAZWI_MASK_INFO_AXUSER_H_MASK 0xFFFF0000
+
+/* PSOC_GLOBAL_CONF_BTL_PROT */
+#define PSOC_GLOBAL_CONF_BTL_PROT_AR_SHIFT 0
+#define PSOC_GLOBAL_CONF_BTL_PROT_AR_MASK 0x7
+#define PSOC_GLOBAL_CONF_BTL_PROT_AW_SHIFT 4
+#define PSOC_GLOBAL_CONF_BTL_PROT_AW_MASK 0x70
+
+/* PSOC_GLOBAL_CONF_BTL_ADDR_EXT */
+#define PSOC_GLOBAL_CONF_BTL_ADDR_EXT_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_BTL_ADDR_EXT_VAL_MASK 0xFFFFF
+
+/* PSOC_GLOBAL_CONF_BOOT_SEQ_TO */
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_TO_MASK_SHIFT 0
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_TO_MASK_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_RESET_DELAYS */
+#define PSOC_GLOBAL_CONF_RESET_DELAYS_PRE_RESET_SHIFT 0
+#define PSOC_GLOBAL_CONF_RESET_DELAYS_PRE_RESET_MASK 0xFFFF
+#define PSOC_GLOBAL_CONF_RESET_DELAYS_GRAD_RESET_SHIFT 16
+#define PSOC_GLOBAL_CONF_RESET_DELAYS_GRAD_RESET_MASK 0xFFFF0000
+
+/* PSOC_GLOBAL_CONF_SCRATCHPAD */
+#define PSOC_GLOBAL_CONF_SCRATCHPAD_REG_SHIFT 0
+#define PSOC_GLOBAL_CONF_SCRATCHPAD_REG_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_SEMAPHORE */
+#define PSOC_GLOBAL_CONF_SEMAPHORE_REG_SHIFT 0
+#define PSOC_GLOBAL_CONF_SEMAPHORE_REG_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_CPU_BOOT_STATUS */
+#define PSOC_GLOBAL_CONF_CPU_BOOT_STATUS_CNTR_SHIFT 0
+#define PSOC_GLOBAL_CONF_CPU_BOOT_STATUS_CNTR_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_KMD_MSG_TO_CPU */
+#define PSOC_GLOBAL_CONF_KMD_MSG_TO_CPU_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_KMD_MSG_TO_CPU_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_SPL_SOURCE */
+#define PSOC_GLOBAL_CONF_SPL_SOURCE_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_SPL_SOURCE_VAL_MASK 0x7
+
+/* PSOC_GLOBAL_CONF_I2C_MSTR1_DBG */
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_S_GEN_SHIFT 0
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_S_GEN_MASK 0x1
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_P_GEN_SHIFT 1
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_P_GEN_MASK 0x2
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_DATA_SHIFT 2
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_DATA_MASK 0x4
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_SHIFT 3
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_MASK 0x8
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_RD_SHIFT 4
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_RD_MASK 0x10
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_WR_SHIFT 5
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_WR_MASK 0x20
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_HS_SHIFT 6
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_HS_MASK 0x40
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MASTER_ACT_SHIFT 7
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MASTER_ACT_MASK 0x80
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLAVE_ACT_SHIFT 8
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLAVE_ACT_MASK 0x100
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_10BIT_SHIFT 9
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_10BIT_MASK 0x200
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MST_CSTATE_SHIFT 10
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MST_CSTATE_MASK 0x7C00
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLV_CSTATE_SHIFT 15
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLV_CSTATE_MASK 0x78000
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_IC_EN_SHIFT 19
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_IC_EN_MASK 0x80000
+
+/* PSOC_GLOBAL_CONF_I2C_SLV */
+#define PSOC_GLOBAL_CONF_I2C_SLV_CPU_CTRL_SHIFT 0
+#define PSOC_GLOBAL_CONF_I2C_SLV_CPU_CTRL_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK */
+#define PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK_INTR_SHIFT 0
+#define PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK_INTR_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_TRACE_ADDR */
+#define PSOC_GLOBAL_CONF_TRACE_ADDR_MSB_SHIFT 0
+#define PSOC_GLOBAL_CONF_TRACE_ADDR_MSB_MASK 0xFFFFFF
+
+/* PSOC_GLOBAL_CONF_SMB_ALERT_CTRL */
+#define PSOC_GLOBAL_CONF_SMB_ALERT_CTRL_I2C_M0_ALERT_MASK_SHIFT 0
+#define PSOC_GLOBAL_CONF_SMB_ALERT_CTRL_I2C_M0_ALERT_MASK_MASK 0xFF
+#define PSOC_GLOBAL_CONF_SMB_ALERT_CTRL_I2C_M1_ALERT_MASK_SHIFT 8
+#define PSOC_GLOBAL_CONF_SMB_ALERT_CTRL_I2C_M1_ALERT_MASK_MASK 0xFF00
+#define PSOC_GLOBAL_CONF_SMB_ALERT_CTRL_I2C_SLV_ALERT_MASK_SHIFT 16
+#define PSOC_GLOBAL_CONF_SMB_ALERT_CTRL_I2C_SLV_ALERT_MASK_MASK 0xFF0000
+
+/* PSOC_GLOBAL_CONF_SMB_ALERT_INTR_CAUSE */
+#define PSOC_GLOBAL_CONF_SMB_ALERT_INTR_CAUSE_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_SMB_ALERT_INTR_CAUSE_VAL_MASK 0xFF
+
+/* PSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CLEAR */
+#define PSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CLEAR_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CLEAR_IND_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CTRL */
+#define PSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CTRL_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CTRL_IND_MASK 0x1
+#define PSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CTRL_MASK_SHIFT 4
+#define PSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CTRL_MASK_MASK 0x10
+
+/* PSOC_GLOBAL_CONF_TRACE_AXPROT */
+#define PSOC_GLOBAL_CONF_TRACE_AXPROT_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_TRACE_AXPROT_VAL_MASK 0x7
+
+/* PSOC_GLOBAL_CONF_TRACE_AWUSER */
+#define PSOC_GLOBAL_CONF_TRACE_AWUSER_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_TRACE_AWUSER_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_TRACE_ARUSER */
+#define PSOC_GLOBAL_CONF_TRACE_ARUSER_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_TRACE_ARUSER_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_BTL_STS */
+#define PSOC_GLOBAL_CONF_BTL_STS_DONE_SHIFT 0
+#define PSOC_GLOBAL_CONF_BTL_STS_DONE_MASK 0x1
+#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_SHIFT 4
+#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_MASK 0x10
+#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_CODE_SHIFT 8
+#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_CODE_MASK 0xF00
+
+/* PSOC_GLOBAL_CONF_TIMEOUT_INTR */
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_0_SHIFT 0
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_0_MASK 0x1
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_1_SHIFT 1
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_1_MASK 0x2
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_2_SHIFT 2
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_2_MASK 0x4
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_3_SHIFT 3
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_3_MASK 0x8
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_4_SHIFT 4
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_4_MASK 0x10
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_TIMER_SHIFT 5
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_TIMER_MASK 0x20
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_0_SHIFT 6
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_0_MASK 0x40
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_1_SHIFT 7
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_1_MASK 0x80
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_5_SHIFT 8
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_5_MASK 0x100
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_6_SHIFT 9
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_6_MASK 0x200
+
+/* PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR */
+#define PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR_IND_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_PERIPH_INTR */
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TX_SHIFT 0
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TX_MASK 0x1
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RX_SHIFT 1
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RX_MASK 0x2
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TXOVR_SHIFT 2
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TXOVR_MASK 0x4
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RXOVR_SHIFT 3
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RXOVR_MASK 0x8
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TX_SHIFT 4
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TX_MASK 0x10
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RX_SHIFT 5
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RX_MASK 0x20
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TXOVR_SHIFT 6
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TXOVR_MASK 0x40
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RXOVR_SHIFT 7
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RXOVR_MASK 0x80
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_SHIFT 12
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_MASK 0x1000
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_WAKEUP_SHIFT 13
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_WAKEUP_MASK 0x2000
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_MII_SHIFT 16
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_MII_MASK 0x10000
+
+/* PSOC_GLOBAL_CONF_COMB_PERIPH_INTR */
+#define PSOC_GLOBAL_CONF_COMB_PERIPH_INTR_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_COMB_PERIPH_INTR_IND_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_AXI_ERR_INTR */
+#define PSOC_GLOBAL_CONF_AXI_ERR_INTR_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_AXI_ERR_INTR_IND_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_ARC_WD_INTR */
+#define PSOC_GLOBAL_CONF_ARC_WD_INTR_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_ARC_WD_INTR_IND_MASK 0x3
+
+/* PSOC_GLOBAL_CONF_ARC_WD_INTR_MASK */
+#define PSOC_GLOBAL_CONF_ARC_WD_INTR_MASK_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_ARC_WD_INTR_MASK_VAL_MASK 0x3
+
+/* PSOC_GLOBAL_CONF_DBG_APB_CTRL */
+#define PSOC_GLOBAL_CONF_DBG_APB_CTRL_SEL_SHIFT 0
+#define PSOC_GLOBAL_CONF_DBG_APB_CTRL_SEL_MASK 0x1
+#define PSOC_GLOBAL_CONF_DBG_APB_CTRL_VAL_SHIFT 1
+#define PSOC_GLOBAL_CONF_DBG_APB_CTRL_VAL_MASK 0x2
+
+/* PSOC_GLOBAL_CONF_SPI_DMA_BAUDR */
+#define PSOC_GLOBAL_CONF_SPI_DMA_BAUDR_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_SPI_DMA_BAUDR_VAL_MASK 0xFFFF
+
+/* PSOC_GLOBAL_CONF_SPI_DMA_AWPROT */
+#define PSOC_GLOBAL_CONF_SPI_DMA_AWPROT_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_SPI_DMA_AWPROT_VAL_MASK 0x7
+
+/* PSOC_GLOBAL_CONF_SPI_DMA_AWUSER */
+#define PSOC_GLOBAL_CONF_SPI_DMA_AWUSER_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_SPI_DMA_AWUSER_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_SPI_DMA_CTRL */
+#define PSOC_GLOBAL_CONF_SPI_DMA_CTRL_EN_SHIFT 0
+#define PSOC_GLOBAL_CONF_SPI_DMA_CTRL_EN_MASK 0x1
+#define PSOC_GLOBAL_CONF_SPI_DMA_CTRL_DST_SRAM_SHIFT 1
+#define PSOC_GLOBAL_CONF_SPI_DMA_CTRL_DST_SRAM_MASK 0x2
+#define PSOC_GLOBAL_CONF_SPI_DMA_CTRL_MEM_SIZE_SHIFT 4
+#define PSOC_GLOBAL_CONF_SPI_DMA_CTRL_MEM_SIZE_MASK 0x3FFF0
+#define PSOC_GLOBAL_CONF_SPI_DMA_CTRL_ADDR_SHIFT 18
+#define PSOC_GLOBAL_CONF_SPI_DMA_CTRL_ADDR_MASK 0xFFFC0000
+
+/* PSOC_GLOBAL_CONF_SPI_DMA_STATUS */
+#define PSOC_GLOBAL_CONF_SPI_DMA_STATUS_DONE_SHIFT 0
+#define PSOC_GLOBAL_CONF_SPI_DMA_STATUS_DONE_MASK 0x1
+#define PSOC_GLOBAL_CONF_SPI_DMA_STATUS_ERROR_SHIFT 1
+#define PSOC_GLOBAL_CONF_SPI_DMA_STATUS_ERROR_MASK 0x2
+#define PSOC_GLOBAL_CONF_SPI_DMA_STATUS_COPIED_SHIFT 4
+#define PSOC_GLOBAL_CONF_SPI_DMA_STATUS_COPIED_MASK 0x3FFF0
+
+/* PSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_L */
+#define PSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_L_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_L_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_H */
+#define PSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_H_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_H_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL */
+#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_WEN_SHIFT 0
+#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_WEN_MASK 0x1
+#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_BYTE_SWAP_SHIFT 4
+#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_BYTE_SWAP_MASK 0x10
+#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_WRITE_CMD_SHIFT 8
+#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_WRITE_CMD_MASK 0xFF00
+#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_WREN_CMD_SHIFT 16
+#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_WREN_CMD_MASK 0xFF0000
+#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_WRDI_CMD_SHIFT 24
+#define PSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL_WRDI_CMD_MASK 0xFF000000
+
+/* PSOC_GLOBAL_CONF_SPI_WR_WO_CTRL */
+#define PSOC_GLOBAL_CONF_SPI_WR_WO_CTRL_EN_SHIFT 0
+#define PSOC_GLOBAL_CONF_SPI_WR_WO_CTRL_EN_MASK 0x1
+#define PSOC_GLOBAL_CONF_SPI_WR_WO_CTRL_RESP_ERR_SHIFT 1
+#define PSOC_GLOBAL_CONF_SPI_WR_WO_CTRL_RESP_ERR_MASK 0x2
+#define PSOC_GLOBAL_CONF_SPI_WR_WO_CTRL_SE_RANGE_SEL_SHIFT 4
+#define PSOC_GLOBAL_CONF_SPI_WR_WO_CTRL_SE_RANGE_SEL_MASK 0xFF0
+
+/* PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_L */
+#define PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_L_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_L_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_H */
+#define PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_H_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_H_VAL_MASK 0xFF
+
+/* PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_L */
+#define PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_L_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_L_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_H */
+#define PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_H_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_H_VAL_MASK 0xFF
+
+/* PSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_L */
+#define PSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_L_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_L_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_H */
+#define PSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_H_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_H_VAL_MASK 0xFF
+
+/* PSOC_GLOBAL_CONF_SPI_WR_WO_SE_STATUS */
+#define PSOC_GLOBAL_CONF_SPI_WR_WO_SE_STATUS_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_SPI_WR_WO_SE_STATUS_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_QSPI_WR_WO_SE_STATUS */
+#define PSOC_GLOBAL_CONF_QSPI_WR_WO_SE_STATUS_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_QSPI_WR_WO_SE_STATUS_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_SPI_WR_WO_ERR_ADDR */
+#define PSOC_GLOBAL_CONF_SPI_WR_WO_ERR_ADDR_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_SPI_WR_WO_ERR_ADDR_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_QSPI_WR_WO_ERR_ADDR */
+#define PSOC_GLOBAL_CONF_QSPI_WR_WO_ERR_ADDR_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_QSPI_WR_WO_ERR_ADDR_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_MASK */
+#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_MASK_QSPI_SHIFT 0
+#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_MASK_QSPI_MASK 0x1
+#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_MASK_SPI_SHIFT 1
+#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_MASK_SPI_MASK 0x2
+
+/* PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CAUSE */
+#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CAUSE_QSPI_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CAUSE_QSPI_IND_MASK 0x1
+#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CAUSE_SPI_IND_SHIFT 1
+#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CAUSE_SPI_IND_MASK 0x2
+
+/* PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CLEAR */
+#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CLEAR_QSPI_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CLEAR_QSPI_VAL_MASK 0x1
+#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CLEAR_SPI_VAL_SHIFT 1
+#define PSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CLEAR_SPI_VAL_MASK 0x2
+
+/* PSOC_GLOBAL_CONF_MSTR_IF */
+#define PSOC_GLOBAL_CONF_MSTR_IF_GRACEFULL_CLEAR_SHIFT 0
+#define PSOC_GLOBAL_CONF_MSTR_IF_GRACEFULL_CLEAR_MASK 0x1
+#define PSOC_GLOBAL_CONF_MSTR_IF_FORCE_BP_SHIFT 1
+#define PSOC_GLOBAL_CONF_MSTR_IF_FORCE_BP_MASK 0x2
+
+/* PSOC_GLOBAL_CONF_TARGETID */
+#define PSOC_GLOBAL_CONF_TARGETID_TDESIGNER_SHIFT 1
+#define PSOC_GLOBAL_CONF_TARGETID_TDESIGNER_MASK 0xFFE
+#define PSOC_GLOBAL_CONF_TARGETID_TPARTNO_SHIFT 16
+#define PSOC_GLOBAL_CONF_TARGETID_TPARTNO_MASK 0xFFF0000
+#define PSOC_GLOBAL_CONF_TARGETID_TREVISION_SHIFT 28
+#define PSOC_GLOBAL_CONF_TARGETID_TREVISION_MASK 0xF0000000
+
+/* PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL */
+#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_NUM_OS_RD_SHIFT 0
+#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_NUM_OS_RD_MASK 0xFF
+#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_NUM_OS_WR_SHIFT 8
+#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_NUM_OS_WR_MASK 0xFF00
+#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_FORCE_WR_BUF_SHIFT 16
+#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_FORCE_WR_BUF_MASK 0x10000
+
+/* PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2 */
+#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_AWCACHE_OVRD_EN_SHIFT 0
+#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_AWCACHE_OVRD_EN_MASK 0x1
+#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_AWCACHE_OVRD_VAL_SHIFT 4
+#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_AWCACHE_OVRD_VAL_MASK 0xF0
+#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_ARCACHE_OVRD_EN_SHIFT 8
+#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_ARCACHE_OVRD_EN_MASK 0x100
+#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_ARCACHE_OVRD_VAL_SHIFT 12
+#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_ARCACHE_OVRD_VAL_MASK 0xF000
+#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_NO_WR_INFLIGHT_SHIFT 16
+#define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_NO_WR_INFLIGHT_MASK 0x10000
+
+/* PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE */
+#define PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE_IND_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L */
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_RSVD_0_SHIFT 1
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_RSVD_0_MASK 0x2
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_MEM_REPAIR_CFG_SHIFT 2
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_MEM_REPAIR_CFG_MASK 0xC
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_CPOL_SHIFT 4
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_CPOL_MASK 0x10
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_CPHA_SHIFT 5
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_CPHA_MASK 0x20
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_BTL_EN_SHIFT 6
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_BTL_EN_MASK 0x40
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_BTL_ROM_EN_SHIFT 7
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_BTL_ROM_EN_MASK 0x80
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_DUMP_SEL_SHIFT 8
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_DUMP_SEL_MASK 0x3FFF00
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_RSVD_1_SHIFT 22
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_RSVD_1_MASK 0x400000
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_DUMP_DIS_SHIFT 23
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_DUMP_DIS_MASK 0x800000
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_I2C_SHIFT 24
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_I2C_MASK 0x1F000000
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_SPI_QSPI_SHIFT 29
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_SPI_QSPI_MASK 0x20000000
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_CPU_PLL_CFG_SHIFT 30
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L_CPU_PLL_CFG_MASK 0xC0000000
+
+/* PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H */
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H_SECURITY_BYPASS_SHIFT 0
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H_SECURITY_BYPASS_MASK 0x1
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H_SRIS_MODE_SHIFT 1
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H_SRIS_MODE_MASK 0x2
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H_I2C_SLV_ADDR_SHIFT 2
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H_I2C_SLV_ADDR_MASK 0x7C
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H_RERERVED_STRAP_SHIFT 7
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H_RERERVED_STRAP_MASK 0x380
+
+/* PSOC_GLOBAL_CONF_LEGACY_BOOT_STRAPS */
+#define PSOC_GLOBAL_CONF_LEGACY_BOOT_STRAPS_PCIE_EN_SHIFT 0
+#define PSOC_GLOBAL_CONF_LEGACY_BOOT_STRAPS_PCIE_EN_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_MEM_REPAIR_DIV */
+#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_EN_SHIFT 0
+#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_EN_MASK 0x1
+#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_VAL_SHIFT 8
+#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_VAL_MASK 0xFF00
+
+/* PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL */
+#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_SET_SHIFT 0
+#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_SET_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_MEM_REPAIR_STS */
+#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_IND_MASK 0x1
+#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_FAIL_SHIFT 4
+#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_FAIL_MASK 0x10
+
+/* PSOC_GLOBAL_CONF_OUTSTANT_TRANS */
+#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_RD_SHIFT 0
+#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_RD_MASK 0x1
+#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_WR_SHIFT 1
+#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_WR_MASK 0x2
+
+/* PSOC_GLOBAL_CONF_MASK_REQ */
+#define PSOC_GLOBAL_CONF_MASK_REQ_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_MASK_REQ_IND_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_BSAC_CTRL */
+#define PSOC_GLOBAL_CONF_BSAC_CTRL_ENABLE_SHIFT 0
+#define PSOC_GLOBAL_CONF_BSAC_CTRL_ENABLE_MASK 0x1
+#define PSOC_GLOBAL_CONF_BSAC_CTRL_HOLD_SHIFT 1
+#define PSOC_GLOBAL_CONF_BSAC_CTRL_HOLD_MASK 0x2
+#define PSOC_GLOBAL_CONF_BSAC_CTRL_DONE_SHIFT 4
+#define PSOC_GLOBAL_CONF_BSAC_CTRL_DONE_MASK 0x10
+#define PSOC_GLOBAL_CONF_BSAC_CTRL_STARTED_SHIFT 5
+#define PSOC_GLOBAL_CONF_BSAC_CTRL_STARTED_MASK 0x20
+#define PSOC_GLOBAL_CONF_BSAC_CTRL_APBERROR_SHIFT 6
+#define PSOC_GLOBAL_CONF_BSAC_CTRL_APBERROR_MASK 0x40
+#define PSOC_GLOBAL_CONF_BSAC_CTRL_FRF_SHIFT 8
+#define PSOC_GLOBAL_CONF_BSAC_CTRL_FRF_MASK 0x300
+#define PSOC_GLOBAL_CONF_BSAC_CTRL_TMOD_SHIFT 10
+#define PSOC_GLOBAL_CONF_BSAC_CTRL_TMOD_MASK 0xC00
+#define PSOC_GLOBAL_CONF_BSAC_CTRL_SPI_FRF_SHIFT 12
+#define PSOC_GLOBAL_CONF_BSAC_CTRL_SPI_FRF_MASK 0x3000
+
+/* PSOC_GLOBAL_CONF_BSAC_ADDR */
+#define PSOC_GLOBAL_CONF_BSAC_ADDR_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_BSAC_ADDR_VAL_MASK 0xFFFFFFF
+
+/* PSOC_GLOBAL_CONF_BSAC_DATA */
+#define PSOC_GLOBAL_CONF_BSAC_DATA_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_BSAC_DATA_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_BSAC_POLLING_CTRL */
+#define PSOC_GLOBAL_CONF_BSAC_POLLING_CTRL_ADDR_SHIFT 0
+#define PSOC_GLOBAL_CONF_BSAC_POLLING_CTRL_ADDR_MASK 0xFFFFFFF
+#define PSOC_GLOBAL_CONF_BSAC_POLLING_CTRL_ENABLE_SHIFT 28
+#define PSOC_GLOBAL_CONF_BSAC_POLLING_CTRL_ENABLE_MASK 0x10000000
+#define PSOC_GLOBAL_CONF_BSAC_POLLING_CTRL_DONE_SHIFT 29
+#define PSOC_GLOBAL_CONF_BSAC_POLLING_CTRL_DONE_MASK 0x20000000
+
+/* PSOC_GLOBAL_CONF_BSAC_POLLING_DATA */
+#define PSOC_GLOBAL_CONF_BSAC_POLLING_DATA_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_BSAC_POLLING_DATA_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_BSAC_POLLING_MASK */
+#define PSOC_GLOBAL_CONF_BSAC_POLLING_MASK_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_BSAC_POLLING_MASK_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_BTL_IMG */
+#define PSOC_GLOBAL_CONF_BTL_IMG_SPI_IMAGE_FLIP_SHIFT 0
+#define PSOC_GLOBAL_CONF_BTL_IMG_SPI_IMAGE_FLIP_MASK 0x1
+#define PSOC_GLOBAL_CONF_BTL_IMG_PRST_IMAGE_FLIP_SHIFT 1
+#define PSOC_GLOBAL_CONF_BTL_IMG_PRST_IMAGE_FLIP_MASK 0x2
+#define PSOC_GLOBAL_CONF_BTL_IMG_PCIE_IMAGE_FLIP_SHIFT 2
+#define PSOC_GLOBAL_CONF_BTL_IMG_PCIE_IMAGE_FLIP_MASK 0x4
+#define PSOC_GLOBAL_CONF_BTL_IMG_SW_RST_RUN_PCIE_IMAGE_SHIFT 4
+#define PSOC_GLOBAL_CONF_BTL_IMG_SW_RST_RUN_PCIE_IMAGE_MASK 0x10
+#define PSOC_GLOBAL_CONF_BTL_IMG_SOFT_RST_RUN_PCIE_IMAGE_SHIFT 5
+#define PSOC_GLOBAL_CONF_BTL_IMG_SOFT_RST_RUN_PCIE_IMAGE_MASK 0x20
+#define PSOC_GLOBAL_CONF_BTL_IMG_WD_RST_RUN_PCIE_IMAGE_SHIFT 6
+#define PSOC_GLOBAL_CONF_BTL_IMG_WD_RST_RUN_PCIE_IMAGE_MASK 0x40
+#define PSOC_GLOBAL_CONF_BTL_IMG_MNL_RST_RUN_PCIE_IMAGE_SHIFT 7
+#define PSOC_GLOBAL_CONF_BTL_IMG_MNL_RST_RUN_PCIE_IMAGE_MASK 0x80
+#define PSOC_GLOBAL_CONF_BTL_IMG_PRST_RUN_PCIE_IMAGE_SHIFT 8
+#define PSOC_GLOBAL_CONF_BTL_IMG_PRST_RUN_PCIE_IMAGE_MASK 0x100
+#define PSOC_GLOBAL_CONF_BTL_IMG_FLR_RST_RUN_PCIE_IMAGE_SHIFT 9
+#define PSOC_GLOBAL_CONF_BTL_IMG_FLR_RST_RUN_PCIE_IMAGE_MASK 0x200
+#define PSOC_GLOBAL_CONF_BTL_IMG_FW_RST_RUN_PCIE_IMAGE_SHIFT 10
+#define PSOC_GLOBAL_CONF_BTL_IMG_FW_RST_RUN_PCIE_IMAGE_MASK 0x400
+
+/* PSOC_GLOBAL_CONF_PRSTN_MASK */
+#define PSOC_GLOBAL_CONF_PRSTN_MASK_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_PRSTN_MASK_IND_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_WD_MASK */
+#define PSOC_GLOBAL_CONF_WD_MASK_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_WD_MASK_IND_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_RST_SRC */
+#define PSOC_GLOBAL_CONF_RST_SRC_COLD_RST_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_RST_SRC_COLD_RST_IND_MASK 0x1
+#define PSOC_GLOBAL_CONF_RST_SRC_MNL_RST_IND_SHIFT 1
+#define PSOC_GLOBAL_CONF_RST_SRC_MNL_RST_IND_MASK 0x2
+#define PSOC_GLOBAL_CONF_RST_SRC_PRSTN_RST_IND_SHIFT 2
+#define PSOC_GLOBAL_CONF_RST_SRC_PRSTN_RST_IND_MASK 0x4
+#define PSOC_GLOBAL_CONF_RST_SRC_SOFT_RST_IND_SHIFT 3
+#define PSOC_GLOBAL_CONF_RST_SRC_SOFT_RST_IND_MASK 0x8
+#define PSOC_GLOBAL_CONF_RST_SRC_WD_RST_IND_SHIFT 4
+#define PSOC_GLOBAL_CONF_RST_SRC_WD_RST_IND_MASK 0x10
+#define PSOC_GLOBAL_CONF_RST_SRC_FW_RST_IND_SHIFT 5
+#define PSOC_GLOBAL_CONF_RST_SRC_FW_RST_IND_MASK 0x20
+#define PSOC_GLOBAL_CONF_RST_SRC_SW_RST_IND_SHIFT 6
+#define PSOC_GLOBAL_CONF_RST_SRC_SW_RST_IND_MASK 0x40
+#define PSOC_GLOBAL_CONF_RST_SRC_FLR_RST_IND_SHIFT 7
+#define PSOC_GLOBAL_CONF_RST_SRC_FLR_RST_IND_MASK 0x80
+#define PSOC_GLOBAL_CONF_RST_SRC_ECC_DERR_RST_IND_SHIFT 8
+#define PSOC_GLOBAL_CONF_RST_SRC_ECC_DERR_RST_IND_MASK 0x100
+
+/* PSOC_GLOBAL_CONF_BOOT_STATE */
+#define PSOC_GLOBAL_CONF_BOOT_STATE_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_BOOT_STATE_VAL_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_RST_FROM_PCIE_CTRL */
+#define PSOC_GLOBAL_CONF_RST_FROM_PCIE_CTRL_SOFT_RST_MASK_SHIFT 0
+#define PSOC_GLOBAL_CONF_RST_FROM_PCIE_CTRL_SOFT_RST_MASK_MASK 0x1
+#define PSOC_GLOBAL_CONF_RST_FROM_PCIE_CTRL_SW_RST_MASK_SHIFT 4
+#define PSOC_GLOBAL_CONF_RST_FROM_PCIE_CTRL_SW_RST_MASK_MASK 0x10
+
+/* PSOC_GLOBAL_CONF_PAD_1V8_CFG */
+#define PSOC_GLOBAL_CONF_PAD_1V8_CFG_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_PAD_1V8_CFG_VAL_MASK 0x7F
+
+/* PSOC_GLOBAL_CONF_PAD_3V3_CFG */
+#define PSOC_GLOBAL_CONF_PAD_3V3_CFG_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_PAD_3V3_CFG_VAL_MASK 0x7F
+
+/* PSOC_GLOBAL_CONF_BNK3V3_MS */
+#define PSOC_GLOBAL_CONF_BNK3V3_MS_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_BNK3V3_MS_VAL_MASK 0x3
+
+/* PSOC_GLOBAL_CONF_TPC_ISO */
+#define PSOC_GLOBAL_CONF_TPC_ISO_ISO_EN_SHIFT 0
+#define PSOC_GLOBAL_CONF_TPC_ISO_ISO_EN_MASK 0x1FFFFFF
+
+/* PSOC_GLOBAL_CONF_VDEC_ISO */
+#define PSOC_GLOBAL_CONF_VDEC_ISO_ISO_EN_SHIFT 0
+#define PSOC_GLOBAL_CONF_VDEC_ISO_ISO_EN_MASK 0x3FF
+
+/* PSOC_GLOBAL_CONF_NIC_ISO */
+#define PSOC_GLOBAL_CONF_NIC_ISO_ISO_EN_SHIFT 0
+#define PSOC_GLOBAL_CONF_NIC_ISO_ISO_EN_MASK 0xFFF
+
+/* PSOC_GLOBAL_CONF_MME_ISO */
+#define PSOC_GLOBAL_CONF_MME_ISO_MME0_EU_RO_ISO_SHIFT 0
+#define PSOC_GLOBAL_CONF_MME_ISO_MME0_EU_RO_ISO_MASK 0x3F
+#define PSOC_GLOBAL_CONF_MME_ISO_MME1_EU_RO_ISO_SHIFT 6
+#define PSOC_GLOBAL_CONF_MME_ISO_MME1_EU_RO_ISO_MASK 0xFC0
+#define PSOC_GLOBAL_CONF_MME_ISO_MME2_EU_RO_ISO_SHIFT 12
+#define PSOC_GLOBAL_CONF_MME_ISO_MME2_EU_RO_ISO_MASK 0x3F000
+#define PSOC_GLOBAL_CONF_MME_ISO_MME3_EU_RO_ISO_SHIFT 18
+#define PSOC_GLOBAL_CONF_MME_ISO_MME3_EU_RO_ISO_MASK 0xFC0000
+
+/* PSOC_GLOBAL_CONF_EDMA_ISO */
+#define PSOC_GLOBAL_CONF_EDMA_ISO_ISO_EN_SHIFT 0
+#define PSOC_GLOBAL_CONF_EDMA_ISO_ISO_EN_MASK 0xFF
+
+/* PSOC_GLOBAL_CONF_HBM_ISO */
+#define PSOC_GLOBAL_CONF_HBM_ISO_HBM_TO_XBAR_SHIFT 0
+#define PSOC_GLOBAL_CONF_HBM_ISO_HBM_TO_XBAR_MASK 0xFFF
+#define PSOC_GLOBAL_CONF_HBM_ISO_HBM_TO_HCH_SHIFT 16
+#define PSOC_GLOBAL_CONF_HBM_ISO_HBM_TO_HCH_MASK 0x3F0000
+
+/* PSOC_GLOBAL_CONF_XBAR_EDGE_ISO */
+#define PSOC_GLOBAL_CONF_XBAR_EDGE_ISO_ISO_EN_SHIFT 0
+#define PSOC_GLOBAL_CONF_XBAR_EDGE_ISO_ISO_EN_MASK 0xF
+
+/* PSOC_GLOBAL_CONF_HIF_HMMU_ISO */
+#define PSOC_GLOBAL_CONF_HIF_HMMU_ISO_ISO_EN_SHIFT 0
+#define PSOC_GLOBAL_CONF_HIF_HMMU_ISO_ISO_EN_MASK 0xFFFF
+
+/* PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_STATUS */
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_STATUS_FAILED_SHIFT 0
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_STATUS_FAILED_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH */
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_LSB_ADDR_SHIFT 0
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_LSB_ADDR_MASK 0xFFF
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_PPROT_SHIFT 12
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_PPROT_MASK 0x7000
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_PWRITE_SHIFT 16
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_PWRITE_MASK 0x10000
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_FENCE_SHIFT 17
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_FENCE_MASK 0x20000
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_DROP_SHIFT 18
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_DROP_MASK 0x40000
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_DST_ID_SHIFT 20
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_DST_ID_MASK 0x3F00000
+
+/* PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_WR */
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_WR_PWDATA_SHIFT 0
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_REQ_WR_PWDATA_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_ASIF_MSTR_RES_STATUS */
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_RES_STATUS_RES_READY_SHIFT 0
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_RES_STATUS_RES_READY_MASK 0x1
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_RES_STATUS_PSLVERR_SHIFT 4
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_RES_STATUS_PSLVERR_MASK 0x10
+
+/* PSOC_GLOBAL_CONF_ASIF_MSTR_RES_POP */
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_RES_POP_PRDATA_SHIFT 0
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_RES_POP_PRDATA_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR */
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_REQ_BUFF_FULL_SHIFT 0
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_REQ_BUFF_FULL_MASK 0x1
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_RES_BUFF_FULL_SHIFT 1
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_RES_BUFF_FULL_MASK 0x2
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_REQ_ILLEGAL_SHIFT 2
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_REQ_ILLEGAL_MASK 0x4
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_RES_DATA_OVRN_SHIFT 3
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_RES_DATA_OVRN_MASK 0x8
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PSLVERR_SHIFT 4
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PSLVERR_MASK 0x10
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_RES_QUAL_OVRN_SHIFT 5
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_RES_QUAL_OVRN_MASK 0x20
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_POP_RES_WHILE_EMPTY_SHIFT 6
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_POP_RES_WHILE_EMPTY_MASK 0x40
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PUSH_REQ_WHILE_FULL_SHIFT 7
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PUSH_REQ_WHILE_FULL_MASK 0x80
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_RX_TIMEOUT_SHIFT 8
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_RX_TIMEOUT_MASK 0x100
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_TX_TIMEOUT_SHIFT 9
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_TX_TIMEOUT_MASK 0x200
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PSLVERR_ADDR_SHIFT 12
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PSLVERR_ADDR_MASK 0xFFF000
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PSLVERR_DST_ID_SHIFT 24
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PSLVERR_DST_ID_MASK 0x3F000000
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PSLVERR_DROP_SHIFT 31
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_PSLVERR_DROP_MASK 0x80000000
+
+/* PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK */
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_REQ_BUFF_FULL_SHIFT 0
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_REQ_BUFF_FULL_MASK 0x1
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RES_BUFF_FULL_SHIFT 1
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RES_BUFF_FULL_MASK 0x2
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_REQ_ILLEGAL_SHIFT 2
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_REQ_ILLEGAL_MASK 0x4
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RES_DATA_OVRN_SHIFT 3
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RES_DATA_OVRN_MASK 0x8
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_PSLVERR_SHIFT 4
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_PSLVERR_MASK 0x10
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RES_QUAL_OVRN_SHIFT 5
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RES_QUAL_OVRN_MASK 0x20
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_POP_RES_WHILE_EMPTY_SHIFT 6
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_POP_RES_WHILE_EMPTY_MASK 0x40
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_PUSH_REQ_WHILE_FULL_SHIFT 7
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_PUSH_REQ_WHILE_FULL_MASK 0x80
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RX_TIMEOUT_SHIFT 8
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RX_TIMEOUT_MASK 0x100
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_TX_TIMEOUT_SHIFT 9
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_TX_TIMEOUT_MASK 0x200
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RES_VALID_SHIFT 16
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RES_VALID_MASK 0x10000
+
+/* PSOC_GLOBAL_CONF_ASIF_MSTR_STATUS */
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_STATUS_REQ_LL_USED_SHIFT 0
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_STATUS_REQ_LL_USED_MASK 0x3F
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_STATUS_RES_LL_USED_SHIFT 8
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_STATUS_RES_LL_USED_MASK 0x1F00
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_STATUS_OTF_FIFO_USED_SHIFT 16
+#define PSOC_GLOBAL_CONF_ASIF_MSTR_STATUS_OTF_FIFO_USED_MASK 0x3F0000
+
+/* PSOC_GLOBAL_CONF_ASIF_CORE_CFG */
+#define PSOC_GLOBAL_CONF_ASIF_CORE_CFG_RISE_DELAY_SHIFT 0
+#define PSOC_GLOBAL_CONF_ASIF_CORE_CFG_RISE_DELAY_MASK 0x1F
+#define PSOC_GLOBAL_CONF_ASIF_CORE_CFG_FALL_DELAY_SHIFT 8
+#define PSOC_GLOBAL_CONF_ASIF_CORE_CFG_FALL_DELAY_MASK 0x1F00
+#define PSOC_GLOBAL_CONF_ASIF_CORE_CFG_DETECT_DELAY_SHIFT 16
+#define PSOC_GLOBAL_CONF_ASIF_CORE_CFG_DETECT_DELAY_MASK 0xF0000
+#define PSOC_GLOBAL_CONF_ASIF_CORE_CFG_FLUSH_DESIGN_SHIFT 31
+#define PSOC_GLOBAL_CONF_ASIF_CORE_CFG_FLUSH_DESIGN_MASK 0x80000000
+
+/* PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT */
+#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_RX_DATA_OVRN_CNT_SHIFT 0
+#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_RX_DATA_OVRN_CNT_MASK 0xF
+#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_RX_QUAL_OVRN_CNT_SHIFT 4
+#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_RX_QUAL_OVRN_CNT_MASK 0xF0
+#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_DETECT_CYCLES_CNT_SHIFT 8
+#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_DETECT_CYCLES_CNT_MASK 0xF00
+#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_RX_CNT_SHIFT 12
+#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_RX_CNT_MASK 0xF000
+#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_TX_CNT_SHIFT 16
+#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_TX_CNT_MASK 0xF0000
+#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_RX_FSM_SHIFT 20
+#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_RX_FSM_MASK 0xF00000
+#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_TX_FSM_SHIFT 24
+#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_TX_FSM_MASK 0xF000000
+
+/* PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR */
+#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_GLB_CLEAR_SHIFT 0
+#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_GLB_CLEAR_MASK 0x1
+#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_RX_DATA_OVRN_CLR_SHIFT 1
+#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_RX_DATA_OVRN_CLR_MASK 0x2
+#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_RX_QUAL_OVRN_CLR_SHIFT 2
+#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_RX_QUAL_OVRN_CLR_MASK 0x4
+#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_RX_CLR_SHIFT 3
+#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_RX_CLR_MASK 0x8
+#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_TX_CLR_SHIFT 4
+#define PSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR_TX_CLR_MASK 0x10
+
+/* PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG */
+#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_RX_TIMEOUT_EN_SHIFT 0
+#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_RX_TIMEOUT_EN_MASK 0x1
+#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_TX_TIMEOUT_EN_SHIFT 1
+#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_TX_TIMEOUT_EN_MASK 0x2
+#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_RX_TIMEOUT_RES_SHIFT 2
+#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_RX_TIMEOUT_RES_MASK 0x4
+#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_TX_TIMEOUT_RES_SHIFT 3
+#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_TX_TIMEOUT_RES_MASK 0x8
+#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_RX_TIMEOUT_VALUE_SHIFT 8
+#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_RX_TIMEOUT_VALUE_MASK 0x3FF00
+#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_TX_TIMEOUT_VALUE_SHIFT 20
+#define PSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG_TX_TIMEOUT_VALUE_MASK 0x3FF00000
+
+/* PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CAUSE */
+#define PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CAUSE_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CAUSE_IND_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CLEAR */
+#define PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CLEAR_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CLEAR_IND_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_MASK */
+#define PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_MASK_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_ASIF_FUNC_INTR_MASK_VAL_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_ASIF_ERR_INTR_CAUSE */
+#define PSOC_GLOBAL_CONF_ASIF_ERR_INTR_CAUSE_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_ASIF_ERR_INTR_CAUSE_IND_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_ASIF_ERR_INTR_CLEAR */
+#define PSOC_GLOBAL_CONF_ASIF_ERR_INTR_CLEAR_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_ASIF_ERR_INTR_CLEAR_IND_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_ASIF_ERR_INTR_MASK */
+#define PSOC_GLOBAL_CONF_ASIF_ERR_INTR_MASK_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_ASIF_ERR_INTR_MASK_VAL_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_PAD_DEFAULT */
+#define PSOC_GLOBAL_CONF_PAD_DEFAULT_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_PAD_DEFAULT_VAL_MASK 0xF
+
+/* PSOC_GLOBAL_CONF_PAD_SEL */
+#define PSOC_GLOBAL_CONF_PAD_SEL_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_PAD_SEL_VAL_MASK 0x3
+
+/* PSOC_GLOBAL_CONF_SMI_ACCESS_EN */
+#define PSOC_GLOBAL_CONF_SMI_ACCESS_EN_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_SMI_ACCESS_EN_VAL_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_SCRAM_EXTMEM_EN */
+#define PSOC_GLOBAL_CONF_SCRAM_EXTMEM_EN_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_SCRAM_EXTMEM_EN_VAL_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_SCRAM_PERM_SEL */
+#define PSOC_GLOBAL_CONF_SCRAM_PERM_SEL_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_SCRAM_PERM_SEL_VAL_MASK 0xF
+
+/* PSOC_GLOBAL_CONF_SCRAM_POLY_H3 */
+#define PSOC_GLOBAL_CONF_SCRAM_POLY_H3_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_SCRAM_POLY_H3_VAL_MASK 0x1FFFFFFF
+
+/* PSOC_GLOBAL_CONF_CORE_MODE */
+#define PSOC_GLOBAL_CONF_CORE_MODE_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_CORE_MODE_VAL_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_EXTMEM_ID_LOC */
+#define PSOC_GLOBAL_CONF_EXTMEM_ID_LOC_USER_SHRD_IND_LOC_SHIFT 24
+#define PSOC_GLOBAL_CONF_EXTMEM_ID_LOC_USER_SHRD_IND_LOC_MASK 0x3F000000
+
+/* PSOC_GLOBAL_CONF_LBW_USER_CTRL */
+#define PSOC_GLOBAL_CONF_LBW_USER_CTRL_EN_SHIFT 0
+#define PSOC_GLOBAL_CONF_LBW_USER_CTRL_EN_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_ADC_STM_ID */
+#define PSOC_GLOBAL_CONF_ADC_STM_ID_STM_MSTR_ID_SHIFT 0
+#define PSOC_GLOBAL_CONF_ADC_STM_ID_STM_MSTR_ID_MASK 0x3F
+
+/* PSOC_GLOBAL_CONF_ADC */
+#define PSOC_GLOBAL_CONF_ADC_INTR_SHIFT 0
+#define PSOC_GLOBAL_CONF_ADC_INTR_MASK 0xF
+
+/* PSOC_GLOBAL_CONF_ADC_INT_MASK */
+#define PSOC_GLOBAL_CONF_ADC_INT_MASK_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_ADC_INT_MASK_VAL_MASK 0xF
+
+/* PSOC_GLOBAL_CONF_ADC_CLK_FREQ */
+#define PSOC_GLOBAL_CONF_ADC_CLK_FREQ_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_ADC_CLK_FREQ_VAL_MASK 0xFF
+
+/* PSOC_GLOBAL_CONF_ADC_DELAY_FROM_START */
+#define PSOC_GLOBAL_CONF_ADC_DELAY_FROM_START_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_ADC_DELAY_FROM_START_VAL_MASK 0xFF
+
+/* PSOC_GLOBAL_CONF_ADC_SAMPLES */
+#define PSOC_GLOBAL_CONF_ADC_SAMPLES_DATA_SAMPLES_SHIFT 0
+#define PSOC_GLOBAL_CONF_ADC_SAMPLES_DATA_SAMPLES_MASK 0x1F
+#define PSOC_GLOBAL_CONF_ADC_SAMPLES_CLK_SAMPLES_SHIFT 8
+#define PSOC_GLOBAL_CONF_ADC_SAMPLES_CLK_SAMPLES_MASK 0x1F00
+
+/* PSOC_GLOBAL_CONF_ADC_TPH_CS */
+#define PSOC_GLOBAL_CONF_ADC_TPH_CS_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_ADC_TPH_CS_VAL_MASK 0xFF
+
+/* PSOC_GLOBAL_CONF_ADC_LSB_NMSB */
+#define PSOC_GLOBAL_CONF_ADC_LSB_NMSB_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_ADC_LSB_NMSB_VAL_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES */
+#define PSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES_VAL_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE */
+#define PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_VAL_MASK 0x1
+#define PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_CH_SEL_SHIFT 4
+#define PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_CH_SEL_MASK 0x30
+
+/* PSOC_GLOBAL_CONF_ADC_TDV_CSDO */
+#define PSOC_GLOBAL_CONF_ADC_TDV_CSDO_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_ADC_TDV_CSDO_VAL_MASK 0xFF
+
+/* PSOC_GLOBAL_CONF_ADC_PID_SEL */
+#define PSOC_GLOBAL_CONF_ADC_PID_SEL_ADC_SEL_SHIFT 0
+#define PSOC_GLOBAL_CONF_ADC_PID_SEL_ADC_SEL_MASK 0x3
+#define PSOC_GLOBAL_CONF_ADC_PID_SEL_CHANNEL_SEL_SHIFT 4
+#define PSOC_GLOBAL_CONF_ADC_PID_SEL_CHANNEL_SEL_MASK 0x30
+
+/* PSOC_GLOBAL_CONF_ADC_TSU_CSCK */
+#define PSOC_GLOBAL_CONF_ADC_TSU_CSCK_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_ADC_TSU_CSCK_VAL_MASK 0xFF
+
+/* PSOC_GLOBAL_CONF_ADC_CH_SEL */
+#define PSOC_GLOBAL_CONF_ADC_CH_SEL_SEL_DELAY_SHIFT 0
+#define PSOC_GLOBAL_CONF_ADC_CH_SEL_SEL_DELAY_MASK 0xFF
+#define PSOC_GLOBAL_CONF_ADC_CH_SEL_SEL_MAX_SHIFT 8
+#define PSOC_GLOBAL_CONF_ADC_CH_SEL_SEL_MAX_MASK 0x300
+
+/* PSOC_GLOBAL_CONF_ADC_WRITE_ADDR */
+#define PSOC_GLOBAL_CONF_ADC_WRITE_ADDR_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_ADC_WRITE_ADDR_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_ADC_CFG_DATA */
+#define PSOC_GLOBAL_CONF_ADC_CFG_DATA_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_ADC_CFG_DATA_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL */
+#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_AUX_WR_EN_SHIFT 0
+#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_AUX_WR_EN_MASK 0x1
+#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_WR_EN_SHIFT 1
+#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_WR_EN_MASK 0x2
+#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_GRNT_SHIFT 12
+#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_GRNT_MASK 0x1000
+#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_IS_DATA_SHIFT 13
+#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_IS_DATA_MASK 0x2000
+#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_IS_TS_SHIFT 14
+#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_IS_TS_MASK 0x4000
+#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_IS_MARKED_SHIFT 15
+#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_IS_MARKED_MASK 0x8000
+#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_CAUSE_TRIG_SHIFT 16
+#define PSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_STM_EV_CAUSE_TRIG_MASK 0x10000
+
+/* PSOC_GLOBAL_CONF_TERMINATE_READ_CTRL */
+#define PSOC_GLOBAL_CONF_TERMINATE_READ_CTRL_RRESP_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_TERMINATE_READ_CTRL_RRESP_VAL_MASK 0x3
+#define PSOC_GLOBAL_CONF_TERMINATE_READ_CTRL_WIN_EN_SHIFT 4
+#define PSOC_GLOBAL_CONF_TERMINATE_READ_CTRL_WIN_EN_MASK 0xF0
+
+/* PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_L */
+#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_L_VAL_SHIFT 12
+#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_L_VAL_MASK 0xFFFFF000
+
+/* PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_H */
+#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_H_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_H_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_L */
+#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_L_VAL_SHIFT 12
+#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_L_VAL_MASK 0xFFFFF000
+
+/* PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_H */
+#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_H_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_H_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_L */
+#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_L_VAL_SHIFT 12
+#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_L_VAL_MASK 0xFFFFF000
+
+/* PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_H */
+#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_H_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_H_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_L */
+#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_L_VAL_SHIFT 12
+#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_L_VAL_MASK 0xFFFFF000
+
+/* PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_H */
+#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_H_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_H_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_L */
+#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_L_VAL_SHIFT 12
+#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_L_VAL_MASK 0xFFFFF000
+
+/* PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_H */
+#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_H_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_H_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_L */
+#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_L_VAL_SHIFT 12
+#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_L_VAL_MASK 0xFFFFF000
+
+/* PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_H */
+#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_H_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_H_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_L */
+#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_L_VAL_SHIFT 12
+#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_L_VAL_MASK 0xFFFFF000
+
+/* PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_H */
+#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_H_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_H_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_L */
+#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_L_VAL_SHIFT 12
+#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_L_VAL_MASK 0xFFFFF000
+
+/* PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_H */
+#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_H_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_H_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_SCRATCHPAD_INIT_CTRL */
+#define PSOC_GLOBAL_CONF_SCRATCHPAD_INIT_CTRL_START_SHIFT 0
+#define PSOC_GLOBAL_CONF_SCRATCHPAD_INIT_CTRL_START_MASK 0x1
+#define PSOC_GLOBAL_CONF_SCRATCHPAD_INIT_CTRL_DONE_SHIFT 4
+#define PSOC_GLOBAL_CONF_SCRATCHPAD_INIT_CTRL_DONE_MASK 0x10
+
+/* PSOC_GLOBAL_CONF_RST_OUT_CTRL */
+#define PSOC_GLOBAL_CONF_RST_OUT_CTRL_CLR_SHIFT 0
+#define PSOC_GLOBAL_CONF_RST_OUT_CTRL_CLR_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_MEM_CPY_CTRL */
+#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL_EN_SHIFT 0
+#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL_EN_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_MEM_CPY_STATUS */
+#define PSOC_GLOBAL_CONF_MEM_CPY_STATUS_DONE_SHIFT 0
+#define PSOC_GLOBAL_CONF_MEM_CPY_STATUS_DONE_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_H */
+#define PSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_H_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_H_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_L */
+#define PSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_L_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_L_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_H */
+#define PSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_H_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_H_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_L */
+#define PSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_L_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_L_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_MEM_CPY_CTRL2 */
+#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL2_MEM_SIZE_SHIFT 0
+#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL2_MEM_SIZE_MASK 0xFFFF
+#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL2_WR_OS_SHIFT 16
+#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL2_WR_OS_MASK 0x3F0000
+#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL2_RD_OS_SHIFT 24
+#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL2_RD_OS_MASK 0x3F000000
+#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL2_USE_CONST_SHIFT 31
+#define PSOC_GLOBAL_CONF_MEM_CPY_CTRL2_USE_CONST_MASK 0x80000000
+
+/* PSOC_GLOBAL_CONF_MEM_CPY_CONST */
+#define PSOC_GLOBAL_CONF_MEM_CPY_CONST_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_MEM_CPY_CONST_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_H */
+#define PSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_H_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_H_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_L */
+#define PSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_L_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_L_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_AXI_SPLIT_CFG */
+#define PSOC_GLOBAL_CONF_AXI_SPLIT_CFG_FORCE_RESP_OK_SHIFT 0
+#define PSOC_GLOBAL_CONF_AXI_SPLIT_CFG_FORCE_RESP_OK_MASK 0x1
+#define PSOC_GLOBAL_CONF_AXI_SPLIT_CFG_FORCE_WR_BUF_SHIFT 1
+#define PSOC_GLOBAL_CONF_AXI_SPLIT_CFG_FORCE_WR_BUF_MASK 0x2
+#define PSOC_GLOBAL_CONF_AXI_SPLIT_CFG_NUM_RD_OS_SHIFT 8
+#define PSOC_GLOBAL_CONF_AXI_SPLIT_CFG_NUM_RD_OS_MASK 0xFF00
+#define PSOC_GLOBAL_CONF_AXI_SPLIT_CFG_NUM_WR_OS_SHIFT 16
+#define PSOC_GLOBAL_CONF_AXI_SPLIT_CFG_NUM_WR_OS_MASK 0xFF0000
+
+/* PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1 */
+#define PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1_OVRD_RD_EN_SHIFT 0
+#define PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1_OVRD_RD_EN_MASK 0x7
+#define PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1_OVRD_RD_VAL_SHIFT 8
+#define PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1_OVRD_RD_VAL_MASK 0x700
+#define PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1_OVRD_WR_EN_SHIFT 16
+#define PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1_OVRD_WR_EN_MASK 0x70000
+#define PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1_OVRD_WR_VAL_SHIFT 24
+#define PSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1_OVRD_WR_VAL_MASK 0x7000000
+
+/* PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG0 */
+#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG0_OVRD_RD_EN_31_0_SHIFT 0
+#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG0_OVRD_RD_EN_31_0_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG1 */
+#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG1_OVRD_RD_31_0_SHIFT 0
+#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG1_OVRD_RD_31_0_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG2 */
+#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG2_OVRD_WR_EN_31_0_SHIFT 0
+#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG2_OVRD_WR_EN_31_0_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG3 */
+#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG3_OVRD_WR_31_0_SHIFT 0
+#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG3_OVRD_WR_31_0_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4 */
+#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4_OVRD_RD_EN_39_32_SHIFT 0
+#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4_OVRD_RD_EN_39_32_MASK 0xFF
+#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4_OVRD_RD_39_32_SHIFT 8
+#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4_OVRD_RD_39_32_MASK 0xFF00
+#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4_OVRD_WR_EN_39_32_SHIFT 16
+#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4_OVRD_WR_EN_39_32_MASK 0xFF0000
+#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4_OVRD_WR_39_32_SHIFT 24
+#define PSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4_OVRD_WR_39_32_MASK 0xFF000000
+
+/* PSOC_GLOBAL_CONF_LBW_ARUSER_OVRD */
+#define PSOC_GLOBAL_CONF_LBW_ARUSER_OVRD_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_LBW_ARUSER_OVRD_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_LBW_ARUSER_OVRD_EN */
+#define PSOC_GLOBAL_CONF_LBW_ARUSER_OVRD_EN_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_LBW_ARUSER_OVRD_EN_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_LBW_AWUSER_OVRD */
+#define PSOC_GLOBAL_CONF_LBW_AWUSER_OVRD_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_LBW_AWUSER_OVRD_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_LBW_AWUSER_OVRD_EN */
+#define PSOC_GLOBAL_CONF_LBW_AWUSER_OVRD_EN_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_LBW_AWUSER_OVRD_EN_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2 */
+#define PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2_INTR_CAUSE_SHIFT 0
+#define PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2_INTR_CAUSE_MASK 0x1
+#define PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2_INTR_MASK_SHIFT 4
+#define PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2_INTR_MASK_MASK 0x10
+#define PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2_NO_WR_INFLIGHT_SHIFT 5
+#define PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2_NO_WR_INFLIGHT_MASK 0x20
+#define PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2_SEI_INTR_ID_SHIFT 8
+#define PSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2_SEI_INTR_ID_MASK 0x7FFFFF00
+
+/* PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2 */
+#define PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2_INTR_CAUSE_SHIFT 0
+#define PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2_INTR_CAUSE_MASK 0x1
+#define PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2_INTR_MASK_SHIFT 4
+#define PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2_INTR_MASK_MASK 0x10
+#define PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2_NO_WR_INFLIGHT_SHIFT 5
+#define PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2_NO_WR_INFLIGHT_MASK 0x20
+#define PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2_SEI_INTR_ID_SHIFT 8
+#define PSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2_SEI_INTR_ID_MASK 0xFFFFF00
+
+/* PSOC_GLOBAL_CONF_AXI_SPLIT_INTR_CLEAR */
+#define PSOC_GLOBAL_CONF_AXI_SPLIT_INTR_CLEAR_MAIN_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_AXI_SPLIT_INTR_CLEAR_MAIN_IND_MASK 0x1
+#define PSOC_GLOBAL_CONF_AXI_SPLIT_INTR_CLEAR_BOOTROM_IND_SHIFT 1
+#define PSOC_GLOBAL_CONF_AXI_SPLIT_INTR_CLEAR_BOOTROM_IND_MASK 0x2
+
+/* PSOC_GLOBAL_CONF_MEM_CPY_PROT */
+#define PSOC_GLOBAL_CONF_MEM_CPY_PROT_AR_SHIFT 0
+#define PSOC_GLOBAL_CONF_MEM_CPY_PROT_AR_MASK 0x7
+#define PSOC_GLOBAL_CONF_MEM_CPY_PROT_AW_SHIFT 4
+#define PSOC_GLOBAL_CONF_MEM_CPY_PROT_AW_MASK 0x70
+
+/* PSOC_GLOBAL_CONF_ISOLATE_INPUTS */
+#define PSOC_GLOBAL_CONF_ISOLATE_INPUTS_EN_SHIFT 0
+#define PSOC_GLOBAL_CONF_ISOLATE_INPUTS_EN_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_MESH_TO_BOOTROM_CTRL */
+#define PSOC_GLOBAL_CONF_MESH_TO_BOOTROM_CTRL_BLOCK_EN_SHIFT 0
+#define PSOC_GLOBAL_CONF_MESH_TO_BOOTROM_CTRL_BLOCK_EN_MASK 0x1
+#define PSOC_GLOBAL_CONF_MESH_TO_BOOTROM_CTRL_BLOCK_BRESP_SHIFT 1
+#define PSOC_GLOBAL_CONF_MESH_TO_BOOTROM_CTRL_BLOCK_BRESP_MASK 0x6
+#define PSOC_GLOBAL_CONF_MESH_TO_BOOTROM_CTRL_BLOCK_RRESP_SHIFT 5
+#define PSOC_GLOBAL_CONF_MESH_TO_BOOTROM_CTRL_BLOCK_RRESP_MASK 0x60
+
+/* PSOC_GLOBAL_CONF_ARC_JT_SEL */
+#define PSOC_GLOBAL_CONF_ARC_JT_SEL_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_ARC_JT_SEL_VAL_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_PLL_DUMP_CRTL */
+#define PSOC_GLOBAL_CONF_PLL_DUMP_CRTL_PLL_SEL_SHIFT 0
+#define PSOC_GLOBAL_CONF_PLL_DUMP_CRTL_PLL_SEL_MASK 0x3F
+#define PSOC_GLOBAL_CONF_PLL_DUMP_CRTL_BIT_SEL_SHIFT 8
+#define PSOC_GLOBAL_CONF_PLL_DUMP_CRTL_BIT_SEL_MASK 0xF00
+
+/* PSOC_GLOBAL_CONF_MEM_CPY_AXUSER */
+#define PSOC_GLOBAL_CONF_MEM_CPY_AXUSER_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_MEM_CPY_AXUSER_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_BTL_AXUSER */
+#define PSOC_GLOBAL_CONF_BTL_AXUSER_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_BTL_AXUSER_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0 */
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC0_SHIFT 0
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC0_MASK 0x3F
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC1_SHIFT 6
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC1_MASK 0xFC0
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC2_SHIFT 12
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC2_MASK 0x3F000
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC3_SHIFT 18
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC3_MASK 0xFC0000
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_HBM_LOC0_SHIFT 24
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_HBM_LOC0_MASK 0x3F000000
+
+/* PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1 */
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_ADDR_EXTMEM_HBM_LOC1_SHIFT 0
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_ADDR_EXTMEM_HBM_LOC1_MASK 0x3F
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_ADDR_EXTMEM_HBM_LOC2_SHIFT 6
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_ADDR_EXTMEM_HBM_LOC2_MASK 0xFC0
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_PC_EN_SHIFT 12
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_PC_EN_MASK 0x1000
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_CNT_EN_SHIFT 13
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_CNT_EN_MASK 0x2000
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_ALL_ADDR_EN_SHIFT 14
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_ALL_ADDR_EN_MASK 0x4000
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_ALL_ADDR_MASK_SHIFT 16
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_ALL_ADDR_MASK_MASK 0xFF0000
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_HBM_NUM_SHIFT 24
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_HBM_NUM_MASK 0x7000000
+
+/* PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2 */
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2_SCRAM_NONLIN_HBM_CNT_MASK_SHIFT 0
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2_SCRAM_NONLIN_HBM_CNT_MASK_MASK 0xFFFF
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2_SCRAM_NONLIN_EXTM_PC_MASK_SHIFT 16
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2_SCRAM_NONLIN_EXTM_PC_MASK_MASK 0xFFFF0000
+
+/* PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3 */
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP0_SHIFT 0
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP0_MASK 0x7
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP1_SHIFT 3
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP1_MASK 0x38
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP2_SHIFT 6
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP2_MASK 0x1C0
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP3_SHIFT 9
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP3_MASK 0xE00
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP4_SHIFT 12
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP4_MASK 0x7000
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP5_SHIFT 15
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP5_MASK 0x38000
+
+/* PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL */
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_EN_SHIFT 0
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_EN_MASK 0x1
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_AXI_RESP_SHIFT 4
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_AXI_RESP_MASK 0x30
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_DRAIN_HBW_SHIFT 8
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_DRAIN_HBW_MASK 0x100
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_DRAIN_LBW_SHIFT 9
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_DRAIN_LBW_MASK 0x200
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_INTR_MASK_HBW_SHIFT 12
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_INTR_MASK_HBW_MASK 0x1000
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_INTR_MASK_LBW_SHIFT 13
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_INTR_MASK_LBW_MASK 0x2000
+
+/* PSOC_GLOBAL_CONF_AXI_DRAIN_TIMEOUT */
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_TIMEOUT_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_TIMEOUT_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_AXI_DRAIN_INTR */
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_INTR_HBW_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_INTR_HBW_IND_MASK 0x1
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_INTR_LBW_IND_SHIFT 1
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_INTR_LBW_IND_MASK 0x2
+
+/* PSOC_GLOBAL_CONF_BTL_STOP_SPI_CLK */
+#define PSOC_GLOBAL_CONF_BTL_STOP_SPI_CLK_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_BTL_STOP_SPI_CLK_VAL_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_ECO_INTR_CAUSE */
+#define PSOC_GLOBAL_CONF_ECO_INTR_CAUSE_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_ECO_INTR_CAUSE_IND_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_ECO_INTR_CLEAR */
+#define PSOC_GLOBAL_CONF_ECO_INTR_CLEAR_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_ECO_INTR_CLEAR_IND_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_ECO_INTR_MASK */
+#define PSOC_GLOBAL_CONF_ECO_INTR_MASK_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_ECO_INTR_MASK_VAL_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_DFT_APB_CONTROL */
+#define PSOC_GLOBAL_CONF_DFT_APB_CONTROL_SPIF_MODE_SHIFT 0
+#define PSOC_GLOBAL_CONF_DFT_APB_CONTROL_SPIF_MODE_MASK 0x1
+#define PSOC_GLOBAL_CONF_DFT_APB_CONTROL_RESERVED_OUT_SHIFT 1
+#define PSOC_GLOBAL_CONF_DFT_APB_CONTROL_RESERVED_OUT_MASK 0xFFFE
+#define PSOC_GLOBAL_CONF_DFT_APB_CONTROL_RESERVED_IN_SHIFT 16
+#define PSOC_GLOBAL_CONF_DFT_APB_CONTROL_RESERVED_IN_MASK 0xFFFF0000
+
+#endif /* ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/psoc_global_conf_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/psoc_global_conf_regs.h
new file mode 100644
index 000000000000..48980fa8e37b
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/psoc_global_conf_regs.h
@@ -0,0 +1,1337 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_
+#define ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_
+
+/*
+ *****************************************
+ *   PSOC_GLOBAL_CONF
+ *   (Prototype: GLOBAL_CONF)
+ *****************************************
+ */
+
+#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_0 0x4C4B000
+
+#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_1 0x4C4B004
+
+#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_2 0x4C4B008
+
+#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_3 0x4C4B00C
+
+#define mmPSOC_GLOBAL_CONF_PCI_FW_FSM 0x4C4B020
+
+#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_RE_START 0x4C4B024
+
+#define mmPSOC_GLOBAL_CONF_BTM_FSM 0x4C4B028
+
+#define mmPSOC_GLOBAL_CONF_BTL_ROM_DELAY 0x4C4B02C
+
+#define mmPSOC_GLOBAL_CONF_SW_BTM_FSM 0x4C4B030
+
+#define mmPSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM 0x4C4B034
+
+#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT 0x4C4B038
+
+#define mmPSOC_GLOBAL_CONF_QSPI_SPI 0x4C4B03C
+
+#define mmPSOC_GLOBAL_CONF_SPI_MEM_EN 0x4C4B040
+
+#define mmPSOC_GLOBAL_CONF_PRSTN 0x4C4B044
+
+#define mmPSOC_GLOBAL_CONF_PCIE_EN 0x4C4B048
+
+#define mmPSOC_GLOBAL_CONF_PCIE_PRSTN_INTR 0x4C4B04C
+
+#define mmPSOC_GLOBAL_CONF_SPI_IMG_STS 0x4C4B050
+
+#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_FSM 0x4C4B054
+
+#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD 0x4C4B058
+
+#define mmPSOC_GLOBAL_CONF_QSPI_SPI_BOOTSEQ_RST 0x4C4B05C
+
+#define mmPSOC_GLOBAL_CONF_PHY_STABLE 0x4C4B060
+
+#define mmPSOC_GLOBAL_CONF_PRSTN_OVR 0x4C4B064
+
+#define mmPSOC_GLOBAL_CONF_ETR_FLUSH 0x4C4B068
+
+#define mmPSOC_GLOBAL_CONF_ANY_RST 0x4C4B06C
+
+#define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_0 0x4C4B070
+
+#define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_1 0x4C4B074
+
+#define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_2 0x4C4B078
+
+#define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_3 0x4C4B07C
+
+#define mmPSOC_GLOBAL_CONF_DIS_RAZWI_ERR 0x4C4B080
+
+#define mmPSOC_GLOBAL_CONF_PCIE_PHY_RST_N 0x4C4B084
+
+#define mmPSOC_GLOBAL_CONF_RAZWI_INTERRUPT 0x4C4B088
+
+#define mmPSOC_GLOBAL_CONF_RAZWI_MASK_INFO 0x4C4B08C
+
+#define mmPSOC_GLOBAL_CONF_BTL_PROT 0x4C4B090
+
+#define mmPSOC_GLOBAL_CONF_BTL_ADDR_EXT 0x4C4B094
+
+#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_TO 0x4C4B098
+
+#define mmPSOC_GLOBAL_CONF_RESET_DELAYS 0x4C4B09C
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_0 0x4C4B100
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_1 0x4C4B104
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_2 0x4C4B108
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_3 0x4C4B10C
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_4 0x4C4B110
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_5 0x4C4B114
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_6 0x4C4B118
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_7 0x4C4B11C
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_8 0x4C4B120
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_9 0x4C4B124
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_10 0x4C4B128
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_11 0x4C4B12C
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_12 0x4C4B130
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_13 0x4C4B134
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_14 0x4C4B138
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_15 0x4C4B13C
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_16 0x4C4B140
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_17 0x4C4B144
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_18 0x4C4B148
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_19 0x4C4B14C
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_20 0x4C4B150
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_21 0x4C4B154
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_22 0x4C4B158
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_23 0x4C4B15C
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_24 0x4C4B160
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_25 0x4C4B164
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_26 0x4C4B168
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_27 0x4C4B16C
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_28 0x4C4B170
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_29 0x4C4B174
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_30 0x4C4B178
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_31 0x4C4B17C
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_0 0x4C4B200
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_1 0x4C4B204
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_2 0x4C4B208
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_3 0x4C4B20C
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_4 0x4C4B210
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_5 0x4C4B214
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_6 0x4C4B218
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_7 0x4C4B21C
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_8 0x4C4B220
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_9 0x4C4B224
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_10 0x4C4B228
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_11 0x4C4B22C
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_12 0x4C4B230
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_13 0x4C4B234
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_14 0x4C4B238
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_15 0x4C4B23C
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_16 0x4C4B240
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_17 0x4C4B244
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_18 0x4C4B248
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_19 0x4C4B24C
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_20 0x4C4B250
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_21 0x4C4B254
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_22 0x4C4B258
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_23 0x4C4B25C
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_24 0x4C4B260
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_25 0x4C4B264
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_26 0x4C4B268
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_27 0x4C4B26C
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_28 0x4C4B270
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_29 0x4C4B274
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_30 0x4C4B278
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_31 0x4C4B27C
+
+#define mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS 0x4C4B300
+
+#define mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU 0x4C4B304
+
+#define mmPSOC_GLOBAL_CONF_SPL_SOURCE 0x4C4B308
+
+#define mmPSOC_GLOBAL_CONF_I2C_MSTR1_DBG 0x4C4B30C
+
+#define mmPSOC_GLOBAL_CONF_I2C_SLV 0x4C4B310
+
+#define mmPSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK 0x4C4B314
+
+#define mmPSOC_GLOBAL_CONF_TRACE_ADDR 0x4C4B320
+
+#define mmPSOC_GLOBAL_CONF_SMB_ALERT_CTRL 0x4C4B324
+
+#define mmPSOC_GLOBAL_CONF_SMB_ALERT_INTR_CAUSE 0x4C4B328
+
+#define mmPSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CLEAR 0x4C4B32C
+
+#define mmPSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CTRL 0x4C4B330
+
+#define mmPSOC_GLOBAL_CONF_TRACE_AXPROT 0x4C4B334
+
+#define mmPSOC_GLOBAL_CONF_TRACE_AWUSER 0x4C4B338
+
+#define mmPSOC_GLOBAL_CONF_TRACE_ARUSER 0x4C4B33C
+
+#define mmPSOC_GLOBAL_CONF_BTL_STS 0x4C4B340
+
+#define mmPSOC_GLOBAL_CONF_TIMEOUT_INTR 0x4C4B350
+
+#define mmPSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR 0x4C4B354
+
+#define mmPSOC_GLOBAL_CONF_PERIPH_INTR 0x4C4B358
+
+#define mmPSOC_GLOBAL_CONF_COMB_PERIPH_INTR 0x4C4B35C
+
+#define mmPSOC_GLOBAL_CONF_AXI_ERR_INTR 0x4C4B360
+
+#define mmPSOC_GLOBAL_CONF_ARC_WD_INTR 0x4C4B368
+
+#define mmPSOC_GLOBAL_CONF_ARC_WD_INTR_MASK 0x4C4B36C
+
+#define mmPSOC_GLOBAL_CONF_DBG_APB_CTRL 0x4C4B370
+
+#define mmPSOC_GLOBAL_CONF_SPI_DMA_BAUDR 0x4C4B374
+
+#define mmPSOC_GLOBAL_CONF_SPI_DMA_AWPROT 0x4C4B378
+
+#define mmPSOC_GLOBAL_CONF_SPI_DMA_AWUSER 0x4C4B37C
+
+#define mmPSOC_GLOBAL_CONF_SPI_DMA_CTRL 0x4C4B380
+
+#define mmPSOC_GLOBAL_CONF_SPI_DMA_STATUS 0x4C4B384
+
+#define mmPSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_L 0x4C4B388
+
+#define mmPSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_H 0x4C4B38C
+
+#define mmPSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL 0x4C4B3A0
+
+#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_CTRL 0x4C4B3B0
+
+#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_L 0x4C4B3B4
+
+#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_H 0x4C4B3B8
+
+#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_L 0x4C4B3BC
+
+#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_H 0x4C4B3C0
+
+#define mmPSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_L 0x4C4B3C4
+
+#define mmPSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_H 0x4C4B3CC
+
+#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_SE_STATUS 0x4C4B3D0
+
+#define mmPSOC_GLOBAL_CONF_QSPI_WR_WO_SE_STATUS 0x4C4B3D4
+
+#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_ERR_ADDR 0x4C4B3D8
+
+#define mmPSOC_GLOBAL_CONF_QSPI_WR_WO_ERR_ADDR 0x4C4B3DC
+
+#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_INTR_MASK 0x4C4B3E0
+
+#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CAUSE 0x4C4B3E4
+
+#define mmPSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CLEAR 0x4C4B3E8
+
+#define mmPSOC_GLOBAL_CONF_MSTR_IF 0x4C4B3F0
+
+#define mmPSOC_GLOBAL_CONF_TARGETID 0x4C4B400
+
+#define mmPSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_0 0x4C4B404
+
+#define mmPSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_1 0x4C4B408
+
+#define mmPSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_0 0x4C4B40C
+
+#define mmPSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_1 0x4C4B410
+
+#define mmPSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE 0x4C4B420
+
+#define mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L 0x4C4B430
+
+#define mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H 0x4C4B434
+
+#define mmPSOC_GLOBAL_CONF_LEGACY_BOOT_STRAPS 0x4C4B438
+
+#define mmPSOC_GLOBAL_CONF_MEM_REPAIR_DIV 0x4C4B44C
+
+#define mmPSOC_GLOBAL_CONF_MEM_REPAIR_CTRL 0x4C4B450
+
+#define mmPSOC_GLOBAL_CONF_MEM_REPAIR_STS 0x4C4B454
+
+#define mmPSOC_GLOBAL_CONF_OUTSTANT_TRANS 0x4C4B458
+
+#define mmPSOC_GLOBAL_CONF_MASK_REQ 0x4C4B45C
+
+#define mmPSOC_GLOBAL_CONF_BSAC_CTRL 0x4C4B4C0
+
+#define mmPSOC_GLOBAL_CONF_BSAC_ADDR 0x4C4B4C4
+
+#define mmPSOC_GLOBAL_CONF_BSAC_DATA 0x4C4B4C8
+
+#define mmPSOC_GLOBAL_CONF_BSAC_POLLING_CTRL 0x4C4B4CC
+
+#define mmPSOC_GLOBAL_CONF_BSAC_POLLING_DATA 0x4C4B4D0
+
+#define mmPSOC_GLOBAL_CONF_BSAC_POLLING_MASK 0x4C4B4D4
+
+#define mmPSOC_GLOBAL_CONF_BTL_IMG 0x4C4B4E0
+
+#define mmPSOC_GLOBAL_CONF_PRSTN_MASK 0x4C4B4E4
+
+#define mmPSOC_GLOBAL_CONF_WD_MASK 0x4C4B4E8
+
+#define mmPSOC_GLOBAL_CONF_RST_SRC 0x4C4B4F0
+
+#define mmPSOC_GLOBAL_CONF_BOOT_STATE 0x4C4B4F4
+
+#define mmPSOC_GLOBAL_CONF_RST_FROM_PCIE_CTRL 0x4C4B4F8
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_0 0x4C4B500
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_1 0x4C4B504
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_2 0x4C4B508
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_3 0x4C4B50C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_4 0x4C4B510
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_5 0x4C4B514
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_6 0x4C4B518
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_7 0x4C4B51C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_8 0x4C4B520
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_9 0x4C4B524
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_10 0x4C4B528
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_11 0x4C4B52C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_12 0x4C4B530
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_13 0x4C4B534
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_14 0x4C4B538
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_15 0x4C4B53C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_16 0x4C4B540
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_17 0x4C4B544
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_18 0x4C4B548
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_19 0x4C4B54C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_20 0x4C4B550
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_21 0x4C4B554
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_22 0x4C4B558
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_23 0x4C4B55C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_24 0x4C4B560
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_25 0x4C4B564
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_26 0x4C4B568
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_27 0x4C4B56C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_28 0x4C4B570
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_29 0x4C4B574
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_30 0x4C4B578
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_31 0x4C4B57C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_32 0x4C4B580
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_33 0x4C4B584
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_34 0x4C4B588
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_35 0x4C4B58C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_36 0x4C4B590
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_37 0x4C4B594
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_38 0x4C4B598
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_39 0x4C4B59C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_40 0x4C4B5A0
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_41 0x4C4B5A4
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_42 0x4C4B5A8
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_43 0x4C4B5AC
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_44 0x4C4B5B0
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_45 0x4C4B5B4
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_46 0x4C4B5B8
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_47 0x4C4B5BC
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_48 0x4C4B5C0
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_49 0x4C4B5C4
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_50 0x4C4B5C8
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_51 0x4C4B5CC
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_52 0x4C4B5D0
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_53 0x4C4B5D4
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_54 0x4C4B5D8
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_55 0x4C4B5DC
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_56 0x4C4B5E0
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_57 0x4C4B5E4
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_58 0x4C4B5E8
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_59 0x4C4B5EC
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_60 0x4C4B5F0
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_61 0x4C4B5F4
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_62 0x4C4B5F8
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_63 0x4C4B5FC
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_64 0x4C4B600
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_65 0x4C4B604
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_66 0x4C4B608
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_67 0x4C4B60C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_68 0x4C4B610
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_69 0x4C4B614
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_70 0x4C4B618
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_71 0x4C4B61C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_72 0x4C4B620
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_73 0x4C4B624
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_74 0x4C4B628
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_75 0x4C4B62C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_76 0x4C4B630
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_77 0x4C4B634
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_78 0x4C4B638
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_79 0x4C4B63C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_80 0x4C4B640
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_81 0x4C4B644
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_82 0x4C4B648
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_83 0x4C4B64C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_84 0x4C4B650
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_85 0x4C4B654
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_86 0x4C4B658
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_87 0x4C4B65C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_88 0x4C4B660
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_89 0x4C4B664
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_90 0x4C4B668
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_91 0x4C4B66C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_92 0x4C4B670
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_93 0x4C4B674
+
+#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_0 0x4C4B690
+
+#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_1 0x4C4B694
+
+#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_2 0x4C4B698
+
+#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_3 0x4C4B69C
+
+#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_4 0x4C4B6A0
+
+#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_5 0x4C4B6A4
+
+#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_6 0x4C4B6A8
+
+#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_7 0x4C4B6AC
+
+#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_8 0x4C4B6B0
+
+#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_9 0x4C4B6B4
+
+#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_10 0x4C4B6B8
+
+#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_11 0x4C4B6BC
+
+#define mmPSOC_GLOBAL_CONF_BNK3V3_MS 0x4C4B710
+
+#define mmPSOC_GLOBAL_CONF_TPC_ISO 0x4C4B760
+
+#define mmPSOC_GLOBAL_CONF_VDEC_ISO 0x4C4B764
+
+#define mmPSOC_GLOBAL_CONF_NIC_ISO 0x4C4B768
+
+#define mmPSOC_GLOBAL_CONF_MME_ISO 0x4C4B76C
+
+#define mmPSOC_GLOBAL_CONF_EDMA_ISO 0x4C4B770
+
+#define mmPSOC_GLOBAL_CONF_HBM_ISO 0x4C4B774
+
+#define mmPSOC_GLOBAL_CONF_XBAR_EDGE_ISO 0x4C4B778
+
+#define mmPSOC_GLOBAL_CONF_HIF_HMMU_ISO 0x4C4B77C
+
+#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_REQ_STATUS_0 0x4C4B780
+
+#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_REQ_STATUS_1 0x4C4B784
+
+#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_0 0x4C4B788
+
+#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_1 0x4C4B78C
+
+#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_REQ_WR_0 0x4C4B790
+
+#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_REQ_WR_1 0x4C4B794
+
+#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_RES_STATUS_0 0x4C4B798
+
+#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_RES_STATUS_1 0x4C4B79C
+
+#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_RES_POP_0 0x4C4B7A0
+
+#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_RES_POP_1 0x4C4B7A4
+
+#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_0 0x4C4B7A8
+
+#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_1 0x4C4B7AC
+
+#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_0 0x4C4B7B0
+
+#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_1 0x4C4B7B4
+
+#define mmPSOC_GLOBAL_CONF_ASIF_MSTR_STATUS 0x4C4B7B8
+
+#define mmPSOC_GLOBAL_CONF_ASIF_CORE_CFG 0x4C4B7C0
+
+#define mmPSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT 0x4C4B7C4
+
+#define mmPSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR 0x4C4B7C8
+
+#define mmPSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG 0x4C4B7CC
+
+#define mmPSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CAUSE_0 0x4C4B7D0
+
+#define mmPSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CAUSE_1 0x4C4B7D4
+
+#define mmPSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CLEAR_0 0x4C4B7D8
+
+#define mmPSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CLEAR_1 0x4C4B7DC
+
+#define mmPSOC_GLOBAL_CONF_ASIF_FUNC_INTR_MASK_0 0x4C4B7E0
+
+#define mmPSOC_GLOBAL_CONF_ASIF_FUNC_INTR_MASK_1 0x4C4B7E4
+
+#define mmPSOC_GLOBAL_CONF_ASIF_ERR_INTR_CAUSE_0 0x4C4B7E8
+
+#define mmPSOC_GLOBAL_CONF_ASIF_ERR_INTR_CAUSE_1 0x4C4B7EC
+
+#define mmPSOC_GLOBAL_CONF_ASIF_ERR_INTR_CLEAR_0 0x4C4B7F0
+
+#define mmPSOC_GLOBAL_CONF_ASIF_ERR_INTR_CLEAR_1 0x4C4B7F4
+
+#define mmPSOC_GLOBAL_CONF_ASIF_ERR_INTR_MASK_0 0x4C4B7F8
+
+#define mmPSOC_GLOBAL_CONF_ASIF_ERR_INTR_MASK_1 0x4C4B7FC
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_0 0x4C4B800
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_1 0x4C4B804
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_2 0x4C4B808
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_3 0x4C4B80C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_4 0x4C4B810
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_5 0x4C4B814
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_6 0x4C4B818
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_7 0x4C4B81C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_8 0x4C4B820
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_9 0x4C4B824
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_10 0x4C4B828
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_11 0x4C4B82C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_12 0x4C4B830
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_13 0x4C4B834
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_14 0x4C4B838
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_15 0x4C4B83C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_16 0x4C4B840
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_17 0x4C4B844
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_18 0x4C4B848
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_19 0x4C4B84C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_20 0x4C4B850
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_21 0x4C4B854
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_22 0x4C4B858
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_23 0x4C4B85C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_24 0x4C4B860
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_25 0x4C4B864
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_26 0x4C4B868
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_27 0x4C4B86C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_28 0x4C4B870
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_29 0x4C4B874
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_30 0x4C4B878
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_31 0x4C4B87C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_32 0x4C4B880
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_33 0x4C4B884
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_34 0x4C4B888
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_35 0x4C4B88C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_36 0x4C4B890
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_37 0x4C4B894
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_38 0x4C4B898
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_39 0x4C4B89C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_40 0x4C4B8A0
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_41 0x4C4B8A4
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_42 0x4C4B8A8
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_43 0x4C4B8AC
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_44 0x4C4B8B0
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_45 0x4C4B8B4
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_46 0x4C4B8B8
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_47 0x4C4B8BC
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_48 0x4C4B8C0
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_49 0x4C4B8C4
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_50 0x4C4B8C8
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_51 0x4C4B8CC
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_52 0x4C4B8D0
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_53 0x4C4B8D4
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_54 0x4C4B8D8
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_55 0x4C4B8DC
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_56 0x4C4B8E0
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_57 0x4C4B8E4
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_58 0x4C4B8E8
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_59 0x4C4B8EC
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_60 0x4C4B8F0
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_61 0x4C4B8F4
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_62 0x4C4B8F8
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_63 0x4C4B8FC
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_64 0x4C4B900
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_65 0x4C4B904
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_66 0x4C4B908
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_67 0x4C4B90C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_68 0x4C4B910
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_69 0x4C4B914
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_70 0x4C4B918
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_71 0x4C4B91C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_72 0x4C4B920
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_73 0x4C4B924
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_74 0x4C4B928
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_75 0x4C4B92C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_76 0x4C4B930
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_77 0x4C4B934
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_78 0x4C4B938
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_79 0x4C4B93C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_80 0x4C4B940
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_81 0x4C4B944
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_82 0x4C4B948
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_83 0x4C4B94C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_84 0x4C4B950
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_85 0x4C4B954
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_86 0x4C4B958
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_87 0x4C4B95C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_88 0x4C4B960
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_89 0x4C4B964
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_90 0x4C4B968
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_91 0x4C4B96C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_92 0x4C4B970
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_93 0x4C4B974
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_94 0x4C4B978
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_95 0x4C4B97C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_0 0x4C4B980
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_1 0x4C4B984
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_2 0x4C4B988
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_3 0x4C4B98C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_4 0x4C4B990
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_5 0x4C4B994
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_6 0x4C4B998
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_7 0x4C4B99C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_8 0x4C4B9A0
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_9 0x4C4B9A4
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_10 0x4C4B9A8
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_11 0x4C4B9AC
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_12 0x4C4B9B0
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_13 0x4C4B9B4
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_14 0x4C4B9B8
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_15 0x4C4B9BC
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_16 0x4C4B9C0
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_17 0x4C4B9C4
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_18 0x4C4B9C8
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_19 0x4C4B9CC
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_20 0x4C4B9D0
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_21 0x4C4B9D4
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_22 0x4C4B9D8
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_23 0x4C4B9DC
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_24 0x4C4B9E0
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_25 0x4C4B9E4
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_26 0x4C4B9E8
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_27 0x4C4B9EC
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_28 0x4C4B9F0
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_29 0x4C4B9F4
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_30 0x4C4B9F8
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_31 0x4C4B9FC
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_32 0x4C4BA00
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_33 0x4C4BA04
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_34 0x4C4BA08
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_35 0x4C4BA0C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_36 0x4C4BA10
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_37 0x4C4BA14
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_38 0x4C4BA18
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_39 0x4C4BA1C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_40 0x4C4BA20
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_41 0x4C4BA24
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_42 0x4C4BA28
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_43 0x4C4BA2C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_44 0x4C4BA30
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_45 0x4C4BA34
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_46 0x4C4BA38
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_47 0x4C4BA3C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_48 0x4C4BA40
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_49 0x4C4BA44
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_50 0x4C4BA48
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_51 0x4C4BA4C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_52 0x4C4BA50
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_53 0x4C4BA54
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_54 0x4C4BA58
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_55 0x4C4BA5C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_56 0x4C4BA60
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_57 0x4C4BA64
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_58 0x4C4BA68
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_59 0x4C4BA6C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_60 0x4C4BA70
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_61 0x4C4BA74
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_62 0x4C4BA78
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_63 0x4C4BA7C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_64 0x4C4BA80
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_65 0x4C4BA84
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_66 0x4C4BA88
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_67 0x4C4BA8C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_68 0x4C4BA90
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_69 0x4C4BA94
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_70 0x4C4BA98
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_71 0x4C4BA9C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_72 0x4C4BAA0
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_73 0x4C4BAA4
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_74 0x4C4BAA8
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_75 0x4C4BAAC
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_76 0x4C4BAB0
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_77 0x4C4BAB4
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_78 0x4C4BAB8
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_79 0x4C4BABC
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_80 0x4C4BAC0
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_81 0x4C4BAC4
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_82 0x4C4BAC8
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_83 0x4C4BACC
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_84 0x4C4BAD0
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_85 0x4C4BAD4
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_86 0x4C4BAD8
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_87 0x4C4BADC
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_88 0x4C4BAE0
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_89 0x4C4BAE4
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_90 0x4C4BAE8
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_91 0x4C4BAEC
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_92 0x4C4BAF0
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_93 0x4C4BAF4
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_94 0x4C4BAF8
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_95 0x4C4BAFC
+
+#define mmPSOC_GLOBAL_CONF_SMI_ACCESS_EN 0x4C4BB00
+
+#define mmPSOC_GLOBAL_CONF_SCRAM_EXTMEM_EN 0x4C4BB38
+
+#define mmPSOC_GLOBAL_CONF_SCRAM_PERM_SEL 0x4C4BB3C
+
+#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_0 0x4C4BB40
+
+#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_1 0x4C4BB44
+
+#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_2 0x4C4BB48
+
+#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_3 0x4C4BB4C
+
+#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_4 0x4C4BB50
+
+#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_5 0x4C4BB54
+
+#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_6 0x4C4BB58
+
+#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_7 0x4C4BB5C
+
+#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_8 0x4C4BB60
+
+#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_9 0x4C4BB64
+
+#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_10 0x4C4BB68
+
+#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_11 0x4C4BB6C
+
+#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_12 0x4C4BB70
+
+#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_13 0x4C4BB74
+
+#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_14 0x4C4BB78
+
+#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_15 0x4C4BB7C
+
+#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_16 0x4C4BB80
+
+#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_17 0x4C4BB84
+
+#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_18 0x4C4BB88
+
+#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_19 0x4C4BB8C
+
+#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_20 0x4C4BB90
+
+#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_21 0x4C4BB94
+
+#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_22 0x4C4BB98
+
+#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_23 0x4C4BB9C
+
+#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_24 0x4C4BBA0
+
+#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_25 0x4C4BBA4
+
+#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_26 0x4C4BBA8
+
+#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_27 0x4C4BBAC
+
+#define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_28 0x4C4BBB0
+
+#define mmPSOC_GLOBAL_CONF_CORE_MODE 0x4C4BBB4
+
+#define mmPSOC_GLOBAL_CONF_EXTMEM_ID_LOC 0x4C4BBB8
+
+#define mmPSOC_GLOBAL_CONF_LBW_USER_CTRL 0x4C4BBC0
+
+#define mmPSOC_GLOBAL_CONF_ADC_STM_ID 0x4C4BBFC
+
+#define mmPSOC_GLOBAL_CONF_ADC_0 0x4C4BC00
+
+#define mmPSOC_GLOBAL_CONF_ADC_1 0x4C4BC04
+
+#define mmPSOC_GLOBAL_CONF_ADC_INT_MASK_0 0x4C4BC10
+
+#define mmPSOC_GLOBAL_CONF_ADC_INT_MASK_1 0x4C4BC14
+
+#define mmPSOC_GLOBAL_CONF_ADC_CLK_FREQ_0 0x4C4BC20
+
+#define mmPSOC_GLOBAL_CONF_ADC_CLK_FREQ_1 0x4C4BC24
+
+#define mmPSOC_GLOBAL_CONF_ADC_DELAY_FROM_START_0 0x4C4BC30
+
+#define mmPSOC_GLOBAL_CONF_ADC_DELAY_FROM_START_1 0x4C4BC34
+
+#define mmPSOC_GLOBAL_CONF_ADC_SAMPLES_0 0x4C4BC40
+
+#define mmPSOC_GLOBAL_CONF_ADC_SAMPLES_1 0x4C4BC44
+
+#define mmPSOC_GLOBAL_CONF_ADC_TPH_CS_0 0x4C4BC50
+
+#define mmPSOC_GLOBAL_CONF_ADC_TPH_CS_1 0x4C4BC54
+
+#define mmPSOC_GLOBAL_CONF_ADC_LSB_NMSB_0 0x4C4BC60
+
+#define mmPSOC_GLOBAL_CONF_ADC_LSB_NMSB_1 0x4C4BC64
+
+#define mmPSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES_0 0x4C4BC70
+
+#define mmPSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES_1 0x4C4BC74
+
+#define mmPSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_0 0x4C4BC80
+
+#define mmPSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_1 0x4C4BC84
+
+#define mmPSOC_GLOBAL_CONF_ADC_TDV_CSDO_0 0x4C4BC90
+
+#define mmPSOC_GLOBAL_CONF_ADC_TDV_CSDO_1 0x4C4BC94
+
+#define mmPSOC_GLOBAL_CONF_ADC_PID_SEL 0x4C4BC98
+
+#define mmPSOC_GLOBAL_CONF_ADC_TSU_CSCK_0 0x4C4BCA0
+
+#define mmPSOC_GLOBAL_CONF_ADC_TSU_CSCK_1 0x4C4BCA4
+
+#define mmPSOC_GLOBAL_CONF_ADC_CH_SEL_0 0x4C4BCA8
+
+#define mmPSOC_GLOBAL_CONF_ADC_CH_SEL_1 0x4C4BCAC
+
+#define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_0 0x4C4BCC0
+
+#define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_1 0x4C4BCC4
+
+#define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_2 0x4C4BCC8
+
+#define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_3 0x4C4BCCC
+
+#define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_4 0x4C4BCD0
+
+#define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_5 0x4C4BCD4
+
+#define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_6 0x4C4BCD8
+
+#define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_7 0x4C4BCDC
+
+#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_0 0x4C4BCE0
+
+#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_1 0x4C4BCE4
+
+#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_2 0x4C4BCE8
+
+#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_3 0x4C4BCEC
+
+#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_4 0x4C4BCF0
+
+#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_5 0x4C4BCF4
+
+#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_6 0x4C4BCF8
+
+#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_7 0x4C4BCFC
+
+#define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_0 0x4C4BD00
+
+#define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_1 0x4C4BD04
+
+#define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_2 0x4C4BD08
+
+#define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_3 0x4C4BD0C
+
+#define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_4 0x4C4BD10
+
+#define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_5 0x4C4BD14
+
+#define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_6 0x4C4BD18
+
+#define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_7 0x4C4BD1C
+
+#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_CTRL 0x4C4BD24
+
+#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_L 0x4C4BD28
+
+#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_H 0x4C4BD2C
+
+#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_L 0x4C4BD30
+
+#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_H 0x4C4BD34
+
+#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_L 0x4C4BD38
+
+#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_H 0x4C4BD3C
+
+#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_L 0x4C4BD40
+
+#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_H 0x4C4BD44
+
+#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_L 0x4C4BD48
+
+#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_H 0x4C4BD4C
+
+#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_L 0x4C4BD50
+
+#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_H 0x4C4BD54
+
+#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_L 0x4C4BD58
+
+#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_H 0x4C4BD5C
+
+#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_L 0x4C4BD60
+
+#define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_H 0x4C4BD64
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_INIT_CTRL 0x4C4BD80
+
+#define mmPSOC_GLOBAL_CONF_RST_OUT_CTRL 0x4C4BD84
+
+#define mmPSOC_GLOBAL_CONF_MEM_CPY_CTRL 0x4C4BD90
+
+#define mmPSOC_GLOBAL_CONF_MEM_CPY_STATUS 0x4C4BD94
+
+#define mmPSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_H 0x4C4BD98
+
+#define mmPSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_L 0x4C4BD9C
+
+#define mmPSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_H 0x4C4BDA0
+
+#define mmPSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_L 0x4C4BDA4
+
+#define mmPSOC_GLOBAL_CONF_MEM_CPY_CTRL2 0x4C4BDA8
+
+#define mmPSOC_GLOBAL_CONF_MEM_CPY_CONST 0x4C4BDAC
+
+#define mmPSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_H 0x4C4BDB0
+
+#define mmPSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_L 0x4C4BDB4
+
+#define mmPSOC_GLOBAL_CONF_AXI_SPLIT_CFG 0x4C4BDC0
+
+#define mmPSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1 0x4C4BDC4
+
+#define mmPSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG0 0x4C4BDC8
+
+#define mmPSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG1 0x4C4BDCC
+
+#define mmPSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG2 0x4C4BDD0
+
+#define mmPSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG3 0x4C4BDD4
+
+#define mmPSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4 0x4C4BDD8
+
+#define mmPSOC_GLOBAL_CONF_LBW_ARUSER_OVRD 0x4C4BDE0
+
+#define mmPSOC_GLOBAL_CONF_LBW_ARUSER_OVRD_EN 0x4C4BDE4
+
+#define mmPSOC_GLOBAL_CONF_LBW_AWUSER_OVRD 0x4C4BDE8
+
+#define mmPSOC_GLOBAL_CONF_LBW_AWUSER_OVRD_EN 0x4C4BDEC
+
+#define mmPSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2 0x4C4BDF0
+
+#define mmPSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2 0x4C4BDF4
+
+#define mmPSOC_GLOBAL_CONF_AXI_SPLIT_INTR_CLEAR 0x4C4BDF8
+
+#define mmPSOC_GLOBAL_CONF_MEM_CPY_PROT 0x4C4BE08
+
+#define mmPSOC_GLOBAL_CONF_ISOLATE_INPUTS 0x4C4BE10
+
+#define mmPSOC_GLOBAL_CONF_MESH_TO_BOOTROM_CTRL 0x4C4BE14
+
+#define mmPSOC_GLOBAL_CONF_ARC_JT_SEL 0x4C4BE28
+
+#define mmPSOC_GLOBAL_CONF_PLL_DUMP_CRTL 0x4C4BE2C
+
+#define mmPSOC_GLOBAL_CONF_MEM_CPY_AXUSER 0x4C4BE30
+
+#define mmPSOC_GLOBAL_CONF_BTL_AXUSER 0x4C4BE34
+
+#define mmPSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0 0x4C4BE38
+
+#define mmPSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1 0x4C4BE40
+
+#define mmPSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2 0x4C4BE44
+
+#define mmPSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3 0x4C4BE48
+
+#define mmPSOC_GLOBAL_CONF_AXI_DRAIN_CTRL 0x4C4BE4C
+
+#define mmPSOC_GLOBAL_CONF_AXI_DRAIN_TIMEOUT 0x4C4BE50
+
+#define mmPSOC_GLOBAL_CONF_AXI_DRAIN_INTR 0x4C4BE54
+
+#define mmPSOC_GLOBAL_CONF_BTL_STOP_SPI_CLK 0x4C4BE58
+
+#define mmPSOC_GLOBAL_CONF_ECO_INTR_CAUSE 0x4C4BE60
+
+#define mmPSOC_GLOBAL_CONF_ECO_INTR_CLEAR 0x4C4BE64
+
+#define mmPSOC_GLOBAL_CONF_ECO_INTR_MASK 0x4C4BE68
+
+#define mmPSOC_GLOBAL_CONF_DFT_APB_CONTROL 0x4C4BE70
+
+#endif /* ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/psoc_reset_conf_masks.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/psoc_reset_conf_masks.h
new file mode 100644
index 000000000000..e0cf35226e7f
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/psoc_reset_conf_masks.h
@@ -0,0 +1,2321 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PSOC_RESET_CONF_MASKS_H_
+#define ASIC_REG_PSOC_RESET_CONF_MASKS_H_
+
+/*
+ *****************************************
+ *   PSOC_RESET_CONF
+ *   (Prototype: PSOC_RESET_CONF)
+ *****************************************
+ */
+
+/* PSOC_RESET_CONF_PSOC_PRSTN_RST_CFG */
+#define PSOC_RESET_CONF_PSOC_PRSTN_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PSOC_PRSTN_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PSOC_SOFT_RST_CFG */
+#define PSOC_RESET_CONF_PSOC_SOFT_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PSOC_SOFT_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PSOC_FW_RST_CFG */
+#define PSOC_RESET_CONF_PSOC_FW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PSOC_FW_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PSOC_WD_RST_CFG */
+#define PSOC_RESET_CONF_PSOC_WD_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PSOC_WD_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PSOC_MNL_RST_CFG */
+#define PSOC_RESET_CONF_PSOC_MNL_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PSOC_MNL_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PSOC_FLR_RST_CFG */
+#define PSOC_RESET_CONF_PSOC_FLR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PSOC_FLR_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PSOC_ECC_DERR_RST_CFG */
+#define PSOC_RESET_CONF_PSOC_ECC_DERR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PSOC_ECC_DERR_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PSOC_SW_RST_CFG */
+#define PSOC_RESET_CONF_PSOC_SW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PSOC_SW_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_CPU_PRSTN_RST_CFG */
+#define PSOC_RESET_CONF_CPU_PRSTN_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_CPU_PRSTN_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_CPU_SOFT_RST_CFG */
+#define PSOC_RESET_CONF_CPU_SOFT_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_CPU_SOFT_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_CPU_FW_RST_CFG */
+#define PSOC_RESET_CONF_CPU_FW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_CPU_FW_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_CPU_WD_RST_CFG */
+#define PSOC_RESET_CONF_CPU_WD_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_CPU_WD_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_CPU_MNL_RST_CFG */
+#define PSOC_RESET_CONF_CPU_MNL_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_CPU_MNL_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_CPU_FLR_RST_CFG */
+#define PSOC_RESET_CONF_CPU_FLR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_CPU_FLR_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_CPU_ECC_DERR_RST_CFG */
+#define PSOC_RESET_CONF_CPU_ECC_DERR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_CPU_ECC_DERR_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_CPU_SW_RST_CFG */
+#define PSOC_RESET_CONF_CPU_SW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_CPU_SW_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_ARC_PRSTN_RST_CFG */
+#define PSOC_RESET_CONF_ARC_PRSTN_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_ARC_PRSTN_RST_CFG_EN_MASK 0x3
+
+/* PSOC_RESET_CONF_ARC_SOFT_RST_CFG */
+#define PSOC_RESET_CONF_ARC_SOFT_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_ARC_SOFT_RST_CFG_EN_MASK 0x3
+
+/* PSOC_RESET_CONF_ARC_FW_RST_CFG */
+#define PSOC_RESET_CONF_ARC_FW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_ARC_FW_RST_CFG_EN_MASK 0x3
+
+/* PSOC_RESET_CONF_ARC_WD_RST_CFG */
+#define PSOC_RESET_CONF_ARC_WD_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_ARC_WD_RST_CFG_EN_MASK 0x3
+
+/* PSOC_RESET_CONF_ARC_MNL_RST_CFG */
+#define PSOC_RESET_CONF_ARC_MNL_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_ARC_MNL_RST_CFG_EN_MASK 0x3
+
+/* PSOC_RESET_CONF_ARC_FLR_RST_CFG */
+#define PSOC_RESET_CONF_ARC_FLR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_ARC_FLR_RST_CFG_EN_MASK 0x3
+
+/* PSOC_RESET_CONF_ARC_ECC_DERR_RST_CFG */
+#define PSOC_RESET_CONF_ARC_ECC_DERR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_ARC_ECC_DERR_RST_CFG_EN_MASK 0x3
+
+/* PSOC_RESET_CONF_ARC_SW_RST_CFG */
+#define PSOC_RESET_CONF_ARC_SW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_ARC_SW_RST_CFG_EN_MASK 0x3
+
+/* PSOC_RESET_CONF_SIF_PRSTN_RST_CFG */
+#define PSOC_RESET_CONF_SIF_PRSTN_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_SIF_PRSTN_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_SIF_SOFT_RST_CFG */
+#define PSOC_RESET_CONF_SIF_SOFT_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_SIF_SOFT_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_SIF_FW_RST_CFG */
+#define PSOC_RESET_CONF_SIF_FW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_SIF_FW_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_SIF_WD_RST_CFG */
+#define PSOC_RESET_CONF_SIF_WD_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_SIF_WD_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_SIF_MNL_RST_CFG */
+#define PSOC_RESET_CONF_SIF_MNL_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_SIF_MNL_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_SIF_FLR_RST_CFG */
+#define PSOC_RESET_CONF_SIF_FLR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_SIF_FLR_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_SIF_ECC_DERR_RST_CFG */
+#define PSOC_RESET_CONF_SIF_ECC_DERR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_SIF_ECC_DERR_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_SIF_SW_RST_CFG */
+#define PSOC_RESET_CONF_SIF_SW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_SIF_SW_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_SRAM_PRSTN_RST_CFG */
+#define PSOC_RESET_CONF_SRAM_PRSTN_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_SRAM_PRSTN_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_SRAM_SOFT_RST_CFG */
+#define PSOC_RESET_CONF_SRAM_SOFT_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_SRAM_SOFT_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_SRAM_FW_RST_CFG */
+#define PSOC_RESET_CONF_SRAM_FW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_SRAM_FW_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_SRAM_WD_RST_CFG */
+#define PSOC_RESET_CONF_SRAM_WD_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_SRAM_WD_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_SRAM_MNL_RST_CFG */
+#define PSOC_RESET_CONF_SRAM_MNL_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_SRAM_MNL_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_SRAM_FLR_RST_CFG */
+#define PSOC_RESET_CONF_SRAM_FLR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_SRAM_FLR_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_SRAM_ECC_DERR_RST_CFG */
+#define PSOC_RESET_CONF_SRAM_ECC_DERR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_SRAM_ECC_DERR_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_SRAM_SW_RST_CFG */
+#define PSOC_RESET_CONF_SRAM_SW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_SRAM_SW_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_PCIE_CTRL_PRSTN_RST_CFG */
+#define PSOC_RESET_CONF_PCIE_CTRL_PRSTN_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PCIE_CTRL_PRSTN_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PCIE_CTRL_SOFT_RST_CFG */
+#define PSOC_RESET_CONF_PCIE_CTRL_SOFT_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PCIE_CTRL_SOFT_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PCIE_CTRL_FW_RST_CFG */
+#define PSOC_RESET_CONF_PCIE_CTRL_FW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PCIE_CTRL_FW_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PCIE_CTRL_WD_RST_CFG */
+#define PSOC_RESET_CONF_PCIE_CTRL_WD_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PCIE_CTRL_WD_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PCIE_CTRL_MNL_RST_CFG */
+#define PSOC_RESET_CONF_PCIE_CTRL_MNL_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PCIE_CTRL_MNL_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PCIE_CTRL_FLR_RST_CFG */
+#define PSOC_RESET_CONF_PCIE_CTRL_FLR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PCIE_CTRL_FLR_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PCIE_CTRL_ECC_DERR_RST_CFG */
+#define PSOC_RESET_CONF_PCIE_CTRL_ECC_DERR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PCIE_CTRL_ECC_DERR_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PCIE_CTRL_SW_RST_CFG */
+#define PSOC_RESET_CONF_PCIE_CTRL_SW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PCIE_CTRL_SW_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PCIE_PHY_CFG_PRSTN_RST_CFG */
+#define PSOC_RESET_CONF_PCIE_PHY_CFG_PRSTN_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PCIE_PHY_CFG_PRSTN_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PCIE_PHY_CFG_SOFT_RST_CFG */
+#define PSOC_RESET_CONF_PCIE_PHY_CFG_SOFT_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PCIE_PHY_CFG_SOFT_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PCIE_PHY_CFG_FW_RST_CFG */
+#define PSOC_RESET_CONF_PCIE_PHY_CFG_FW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PCIE_PHY_CFG_FW_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PCIE_PHY_CFG_WD_RST_CFG */
+#define PSOC_RESET_CONF_PCIE_PHY_CFG_WD_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PCIE_PHY_CFG_WD_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PCIE_PHY_CFG_MNL_RST_CFG */
+#define PSOC_RESET_CONF_PCIE_PHY_CFG_MNL_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PCIE_PHY_CFG_MNL_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PCIE_PHY_CFG_FLR_RST_CFG */
+#define PSOC_RESET_CONF_PCIE_PHY_CFG_FLR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PCIE_PHY_CFG_FLR_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PCIE_PHY_CFG_ECC_DERR_RST_CFG */
+#define PSOC_RESET_CONF_PCIE_PHY_CFG_ECC_DERR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PCIE_PHY_CFG_ECC_DERR_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PCIE_PHY_CFG_SW_RST_CFG */
+#define PSOC_RESET_CONF_PCIE_PHY_CFG_SW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PCIE_PHY_CFG_SW_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PCIE_IF_PRSTN_RST_CFG */
+#define PSOC_RESET_CONF_PCIE_IF_PRSTN_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PCIE_IF_PRSTN_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PCIE_IF_SOFT_RST_CFG */
+#define PSOC_RESET_CONF_PCIE_IF_SOFT_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PCIE_IF_SOFT_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PCIE_IF_FW_RST_CFG */
+#define PSOC_RESET_CONF_PCIE_IF_FW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PCIE_IF_FW_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PCIE_IF_WD_RST_CFG */
+#define PSOC_RESET_CONF_PCIE_IF_WD_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PCIE_IF_WD_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PCIE_IF_MNL_RST_CFG */
+#define PSOC_RESET_CONF_PCIE_IF_MNL_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PCIE_IF_MNL_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PCIE_IF_FLR_RST_CFG */
+#define PSOC_RESET_CONF_PCIE_IF_FLR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PCIE_IF_FLR_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PCIE_IF_ECC_DERR_RST_CFG */
+#define PSOC_RESET_CONF_PCIE_IF_ECC_DERR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PCIE_IF_ECC_DERR_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PCIE_IF_SW_RST_CFG */
+#define PSOC_RESET_CONF_PCIE_IF_SW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PCIE_IF_SW_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_TPC_DIV_PRSTN_RST_CFG */
+#define PSOC_RESET_CONF_TPC_DIV_PRSTN_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_TPC_DIV_PRSTN_RST_CFG_EN_MASK 0x1F
+
+/* PSOC_RESET_CONF_TPC_DIV_SOFT_RST_CFG */
+#define PSOC_RESET_CONF_TPC_DIV_SOFT_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_TPC_DIV_SOFT_RST_CFG_EN_MASK 0x1F
+
+/* PSOC_RESET_CONF_TPC_DIV_FW_RST_CFG */
+#define PSOC_RESET_CONF_TPC_DIV_FW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_TPC_DIV_FW_RST_CFG_EN_MASK 0x1F
+
+/* PSOC_RESET_CONF_TPC_DIV_WD_RST_CFG */
+#define PSOC_RESET_CONF_TPC_DIV_WD_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_TPC_DIV_WD_RST_CFG_EN_MASK 0x1F
+
+/* PSOC_RESET_CONF_TPC_DIV_MNL_RST_CFG */
+#define PSOC_RESET_CONF_TPC_DIV_MNL_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_TPC_DIV_MNL_RST_CFG_EN_MASK 0x1F
+
+/* PSOC_RESET_CONF_TPC_DIV_FLR_RST_CFG */
+#define PSOC_RESET_CONF_TPC_DIV_FLR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_TPC_DIV_FLR_RST_CFG_EN_MASK 0x1F
+
+/* PSOC_RESET_CONF_TPC_DIV_ECC_DERR_RST_CFG */
+#define PSOC_RESET_CONF_TPC_DIV_ECC_DERR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_TPC_DIV_ECC_DERR_RST_CFG_EN_MASK 0x1F
+
+/* PSOC_RESET_CONF_TPC_DIV_SW_RST_CFG */
+#define PSOC_RESET_CONF_TPC_DIV_SW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_TPC_DIV_SW_RST_CFG_EN_MASK 0x1F
+
+/* PSOC_RESET_CONF_HBM_DIV_PRSTN_RST_CFG */
+#define PSOC_RESET_CONF_HBM_DIV_PRSTN_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_HBM_DIV_PRSTN_RST_CFG_EN_MASK 0x3F
+
+/* PSOC_RESET_CONF_HBM_DIV_SOFT_RST_CFG */
+#define PSOC_RESET_CONF_HBM_DIV_SOFT_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_HBM_DIV_SOFT_RST_CFG_EN_MASK 0x3F
+
+/* PSOC_RESET_CONF_HBM_DIV_FW_RST_CFG */
+#define PSOC_RESET_CONF_HBM_DIV_FW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_HBM_DIV_FW_RST_CFG_EN_MASK 0x3F
+
+/* PSOC_RESET_CONF_HBM_DIV_WD_RST_CFG */
+#define PSOC_RESET_CONF_HBM_DIV_WD_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_HBM_DIV_WD_RST_CFG_EN_MASK 0x3F
+
+/* PSOC_RESET_CONF_HBM_DIV_MNL_RST_CFG */
+#define PSOC_RESET_CONF_HBM_DIV_MNL_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_HBM_DIV_MNL_RST_CFG_EN_MASK 0x3F
+
+/* PSOC_RESET_CONF_HBM_DIV_FLR_RST_CFG */
+#define PSOC_RESET_CONF_HBM_DIV_FLR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_HBM_DIV_FLR_RST_CFG_EN_MASK 0x3F
+
+/* PSOC_RESET_CONF_HBM_DIV_ECC_DERR_RST_CFG */
+#define PSOC_RESET_CONF_HBM_DIV_ECC_DERR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_HBM_DIV_ECC_DERR_RST_CFG_EN_MASK 0x3F
+
+/* PSOC_RESET_CONF_HBM_DIV_SW_RST_CFG */
+#define PSOC_RESET_CONF_HBM_DIV_SW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_HBM_DIV_SW_RST_CFG_EN_MASK 0x3F
+
+/* PSOC_RESET_CONF_PMMU_PRSTN_RST_CFG */
+#define PSOC_RESET_CONF_PMMU_PRSTN_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PMMU_PRSTN_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PMMU_SOFT_RST_CFG */
+#define PSOC_RESET_CONF_PMMU_SOFT_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PMMU_SOFT_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PMMU_FW_RST_CFG */
+#define PSOC_RESET_CONF_PMMU_FW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PMMU_FW_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PMMU_WD_RST_CFG */
+#define PSOC_RESET_CONF_PMMU_WD_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PMMU_WD_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PMMU_MNL_RST_CFG */
+#define PSOC_RESET_CONF_PMMU_MNL_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PMMU_MNL_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PMMU_FLR_RST_CFG */
+#define PSOC_RESET_CONF_PMMU_FLR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PMMU_FLR_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PMMU_ECC_DERR_RST_CFG */
+#define PSOC_RESET_CONF_PMMU_ECC_DERR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PMMU_ECC_DERR_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PMMU_SW_RST_CFG */
+#define PSOC_RESET_CONF_PMMU_SW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PMMU_SW_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PM_PRSTN_RST_CFG */
+#define PSOC_RESET_CONF_PM_PRSTN_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PM_PRSTN_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_PM_SOFT_RST_CFG */
+#define PSOC_RESET_CONF_PM_SOFT_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PM_SOFT_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_PM_FW_RST_CFG */
+#define PSOC_RESET_CONF_PM_FW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PM_FW_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_PM_WD_RST_CFG */
+#define PSOC_RESET_CONF_PM_WD_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PM_WD_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_PM_MNL_RST_CFG */
+#define PSOC_RESET_CONF_PM_MNL_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PM_MNL_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_PM_FLR_RST_CFG */
+#define PSOC_RESET_CONF_PM_FLR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PM_FLR_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_PM_ECC_DERR_RST_CFG */
+#define PSOC_RESET_CONF_PM_ECC_DERR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PM_ECC_DERR_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_PM_SW_RST_CFG */
+#define PSOC_RESET_CONF_PM_SW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PM_SW_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_TS_PRSTN_RST_CFG */
+#define PSOC_RESET_CONF_TS_PRSTN_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_TS_PRSTN_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_TS_SOFT_RST_CFG */
+#define PSOC_RESET_CONF_TS_SOFT_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_TS_SOFT_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_TS_FW_RST_CFG */
+#define PSOC_RESET_CONF_TS_FW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_TS_FW_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_TS_WD_RST_CFG */
+#define PSOC_RESET_CONF_TS_WD_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_TS_WD_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_TS_MNL_RST_CFG */
+#define PSOC_RESET_CONF_TS_MNL_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_TS_MNL_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_TS_FLR_RST_CFG */
+#define PSOC_RESET_CONF_TS_FLR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_TS_FLR_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_TS_ECC_DERR_RST_CFG */
+#define PSOC_RESET_CONF_TS_ECC_DERR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_TS_ECC_DERR_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_TS_SW_RST_CFG */
+#define PSOC_RESET_CONF_TS_SW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_TS_SW_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_TS_IF_PRSTN_RST_CFG */
+#define PSOC_RESET_CONF_TS_IF_PRSTN_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_TS_IF_PRSTN_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_TS_IF_SOFT_RST_CFG */
+#define PSOC_RESET_CONF_TS_IF_SOFT_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_TS_IF_SOFT_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_TS_IF_FW_RST_CFG */
+#define PSOC_RESET_CONF_TS_IF_FW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_TS_IF_FW_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_TS_IF_WD_RST_CFG */
+#define PSOC_RESET_CONF_TS_IF_WD_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_TS_IF_WD_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_TS_IF_MNL_RST_CFG */
+#define PSOC_RESET_CONF_TS_IF_MNL_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_TS_IF_MNL_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_TS_IF_FLR_RST_CFG */
+#define PSOC_RESET_CONF_TS_IF_FLR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_TS_IF_FLR_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_TS_IF_ECC_DERR_RST_CFG */
+#define PSOC_RESET_CONF_TS_IF_ECC_DERR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_TS_IF_ECC_DERR_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_TS_IF_SW_RST_CFG */
+#define PSOC_RESET_CONF_TS_IF_SW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_TS_IF_SW_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_PLL_L_PRSTN_RST_CFG */
+#define PSOC_RESET_CONF_PLL_L_PRSTN_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PLL_L_PRSTN_RST_CFG_EN_MASK 0xFFFFFFFF
+
+/* PSOC_RESET_CONF_PLL_L_SOFT_RST_CFG */
+#define PSOC_RESET_CONF_PLL_L_SOFT_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PLL_L_SOFT_RST_CFG_EN_MASK 0xFFFFFFFF
+
+/* PSOC_RESET_CONF_PLL_L_FW_RST_CFG */
+#define PSOC_RESET_CONF_PLL_L_FW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PLL_L_FW_RST_CFG_EN_MASK 0xFFFFFFFF
+
+/* PSOC_RESET_CONF_PLL_L_WD_RST_CFG */
+#define PSOC_RESET_CONF_PLL_L_WD_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PLL_L_WD_RST_CFG_EN_MASK 0xFFFFFFFF
+
+/* PSOC_RESET_CONF_PLL_L_MNL_RST_CFG */
+#define PSOC_RESET_CONF_PLL_L_MNL_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PLL_L_MNL_RST_CFG_EN_MASK 0xFFFFFFFF
+
+/* PSOC_RESET_CONF_PLL_L_FLR_RST_CFG */
+#define PSOC_RESET_CONF_PLL_L_FLR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PLL_L_FLR_RST_CFG_EN_MASK 0xFFFFFFFF
+
+/* PSOC_RESET_CONF_PLL_L_ECC_DERR_RST_CFG */
+#define PSOC_RESET_CONF_PLL_L_ECC_DERR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PLL_L_ECC_DERR_RST_CFG_EN_MASK 0xFFFFFFFF
+
+/* PSOC_RESET_CONF_PLL_L_SW_RST_CFG */
+#define PSOC_RESET_CONF_PLL_L_SW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PLL_L_SW_RST_CFG_EN_MASK 0xFFFFFFFF
+
+/* PSOC_RESET_CONF_PLL_H_PRSTN_RST_CFG */
+#define PSOC_RESET_CONF_PLL_H_PRSTN_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PLL_H_PRSTN_RST_CFG_EN_MASK 0x3
+
+/* PSOC_RESET_CONF_PLL_H_SOFT_RST_CFG */
+#define PSOC_RESET_CONF_PLL_H_SOFT_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PLL_H_SOFT_RST_CFG_EN_MASK 0x3
+
+/* PSOC_RESET_CONF_PLL_H_FW_RST_CFG */
+#define PSOC_RESET_CONF_PLL_H_FW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PLL_H_FW_RST_CFG_EN_MASK 0x3
+
+/* PSOC_RESET_CONF_PLL_H_WD_RST_CFG */
+#define PSOC_RESET_CONF_PLL_H_WD_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PLL_H_WD_RST_CFG_EN_MASK 0x3
+
+/* PSOC_RESET_CONF_PLL_H_MNL_RST_CFG */
+#define PSOC_RESET_CONF_PLL_H_MNL_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PLL_H_MNL_RST_CFG_EN_MASK 0x3
+
+/* PSOC_RESET_CONF_PLL_H_FLR_RST_CFG */
+#define PSOC_RESET_CONF_PLL_H_FLR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PLL_H_FLR_RST_CFG_EN_MASK 0x3
+
+/* PSOC_RESET_CONF_PLL_H_ECC_DERR_RST_CFG */
+#define PSOC_RESET_CONF_PLL_H_ECC_DERR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PLL_H_ECC_DERR_RST_CFG_EN_MASK 0x3
+
+/* PSOC_RESET_CONF_PLL_H_SW_RST_CFG */
+#define PSOC_RESET_CONF_PLL_H_SW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PLL_H_SW_RST_CFG_EN_MASK 0x3
+
+/* PSOC_RESET_CONF_MME_EUS_PRSTN_RST_CFG */
+#define PSOC_RESET_CONF_MME_EUS_PRSTN_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_MME_EUS_PRSTN_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_MME_EUS_SOFT_RST_CFG */
+#define PSOC_RESET_CONF_MME_EUS_SOFT_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_MME_EUS_SOFT_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_MME_EUS_FW_RST_CFG */
+#define PSOC_RESET_CONF_MME_EUS_FW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_MME_EUS_FW_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_MME_EUS_WD_RST_CFG */
+#define PSOC_RESET_CONF_MME_EUS_WD_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_MME_EUS_WD_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_MME_EUS_MNL_RST_CFG */
+#define PSOC_RESET_CONF_MME_EUS_MNL_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_MME_EUS_MNL_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_MME_EUS_FLR_RST_CFG */
+#define PSOC_RESET_CONF_MME_EUS_FLR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_MME_EUS_FLR_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_MME_EUS_ECC_DERR_RST_CFG */
+#define PSOC_RESET_CONF_MME_EUS_ECC_DERR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_MME_EUS_ECC_DERR_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_MME_EUS_SW_RST_CFG */
+#define PSOC_RESET_CONF_MME_EUS_SW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_MME_EUS_SW_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_MSS_CLS_PRSTN_RST_CFG */
+#define PSOC_RESET_CONF_MSS_CLS_PRSTN_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_MSS_CLS_PRSTN_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_MSS_CLS_SOFT_RST_CFG */
+#define PSOC_RESET_CONF_MSS_CLS_SOFT_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_MSS_CLS_SOFT_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_MSS_CLS_FW_RST_CFG */
+#define PSOC_RESET_CONF_MSS_CLS_FW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_MSS_CLS_FW_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_MSS_CLS_WD_RST_CFG */
+#define PSOC_RESET_CONF_MSS_CLS_WD_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_MSS_CLS_WD_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_MSS_CLS_MNL_RST_CFG */
+#define PSOC_RESET_CONF_MSS_CLS_MNL_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_MSS_CLS_MNL_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_MSS_CLS_FLR_RST_CFG */
+#define PSOC_RESET_CONF_MSS_CLS_FLR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_MSS_CLS_FLR_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_MSS_CLS_ECC_DERR_RST_CFG */
+#define PSOC_RESET_CONF_MSS_CLS_ECC_DERR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_MSS_CLS_ECC_DERR_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_MSS_CLS_SW_RST_CFG */
+#define PSOC_RESET_CONF_MSS_CLS_SW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_MSS_CLS_SW_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_TPC_PRSTN_RST_CFG */
+#define PSOC_RESET_CONF_TPC_PRSTN_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_TPC_PRSTN_RST_CFG_EN_MASK 0x1FFFFFF
+
+/* PSOC_RESET_CONF_TPC_SOFT_RST_CFG */
+#define PSOC_RESET_CONF_TPC_SOFT_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_TPC_SOFT_RST_CFG_EN_MASK 0x1FFFFFF
+
+/* PSOC_RESET_CONF_TPC_FW_RST_CFG */
+#define PSOC_RESET_CONF_TPC_FW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_TPC_FW_RST_CFG_EN_MASK 0x1FFFFFF
+
+/* PSOC_RESET_CONF_TPC_WD_RST_CFG */
+#define PSOC_RESET_CONF_TPC_WD_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_TPC_WD_RST_CFG_EN_MASK 0x1FFFFFF
+
+/* PSOC_RESET_CONF_TPC_MNL_RST_CFG */
+#define PSOC_RESET_CONF_TPC_MNL_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_TPC_MNL_RST_CFG_EN_MASK 0x1FFFFFF
+
+/* PSOC_RESET_CONF_TPC_FLR_RST_CFG */
+#define PSOC_RESET_CONF_TPC_FLR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_TPC_FLR_RST_CFG_EN_MASK 0x1FFFFFF
+
+/* PSOC_RESET_CONF_TPC_ECC_DERR_RST_CFG */
+#define PSOC_RESET_CONF_TPC_ECC_DERR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_TPC_ECC_DERR_RST_CFG_EN_MASK 0x1FFFFFF
+
+/* PSOC_RESET_CONF_TPC_SW_RST_CFG */
+#define PSOC_RESET_CONF_TPC_SW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_TPC_SW_RST_CFG_EN_MASK 0x1FFFFFF
+
+/* PSOC_RESET_CONF_HIF_HMMU_PRSTN_RST_CFG */
+#define PSOC_RESET_CONF_HIF_HMMU_PRSTN_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_HIF_HMMU_PRSTN_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_HIF_HMMU_SOFT_RST_CFG */
+#define PSOC_RESET_CONF_HIF_HMMU_SOFT_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_HIF_HMMU_SOFT_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_HIF_HMMU_FW_RST_CFG */
+#define PSOC_RESET_CONF_HIF_HMMU_FW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_HIF_HMMU_FW_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_HIF_HMMU_WD_RST_CFG */
+#define PSOC_RESET_CONF_HIF_HMMU_WD_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_HIF_HMMU_WD_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_HIF_HMMU_MNL_RST_CFG */
+#define PSOC_RESET_CONF_HIF_HMMU_MNL_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_HIF_HMMU_MNL_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_HIF_HMMU_FLR_RST_CFG */
+#define PSOC_RESET_CONF_HIF_HMMU_FLR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_HIF_HMMU_FLR_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_HIF_HMMU_ECC_DERR_RST_CFG */
+#define PSOC_RESET_CONF_HIF_HMMU_ECC_DERR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_HIF_HMMU_ECC_DERR_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_HIF_HMMU_SW_RST_CFG */
+#define PSOC_RESET_CONF_HIF_HMMU_SW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_HIF_HMMU_SW_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_XBAR_PRSTN_RST_CFG */
+#define PSOC_RESET_CONF_XBAR_PRSTN_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_XBAR_PRSTN_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_XBAR_SOFT_RST_CFG */
+#define PSOC_RESET_CONF_XBAR_SOFT_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_XBAR_SOFT_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_XBAR_FW_RST_CFG */
+#define PSOC_RESET_CONF_XBAR_FW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_XBAR_FW_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_XBAR_WD_RST_CFG */
+#define PSOC_RESET_CONF_XBAR_WD_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_XBAR_WD_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_XBAR_MNL_RST_CFG */
+#define PSOC_RESET_CONF_XBAR_MNL_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_XBAR_MNL_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_XBAR_FLR_RST_CFG */
+#define PSOC_RESET_CONF_XBAR_FLR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_XBAR_FLR_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_XBAR_ECC_DERR_RST_CFG */
+#define PSOC_RESET_CONF_XBAR_ECC_DERR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_XBAR_ECC_DERR_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_XBAR_SW_RST_CFG */
+#define PSOC_RESET_CONF_XBAR_SW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_XBAR_SW_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_SFT_XFT_TFT_PRSTN_RST_CFG */
+#define PSOC_RESET_CONF_SFT_XFT_TFT_PRSTN_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_SFT_XFT_TFT_PRSTN_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_SFT_XFT_TFT_SOFT_RST_CFG */
+#define PSOC_RESET_CONF_SFT_XFT_TFT_SOFT_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_SFT_XFT_TFT_SOFT_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_SFT_XFT_TFT_FW_RST_CFG */
+#define PSOC_RESET_CONF_SFT_XFT_TFT_FW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_SFT_XFT_TFT_FW_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_SFT_XFT_TFT_WD_RST_CFG */
+#define PSOC_RESET_CONF_SFT_XFT_TFT_WD_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_SFT_XFT_TFT_WD_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_SFT_XFT_TFT_MNL_RST_CFG */
+#define PSOC_RESET_CONF_SFT_XFT_TFT_MNL_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_SFT_XFT_TFT_MNL_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_SFT_XFT_TFT_FLR_RST_CFG */
+#define PSOC_RESET_CONF_SFT_XFT_TFT_FLR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_SFT_XFT_TFT_FLR_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_SFT_XFT_TFT_ECC_DERR_RST_CFG */
+#define PSOC_RESET_CONF_SFT_XFT_TFT_ECC_DERR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_SFT_XFT_TFT_ECC_DERR_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_SFT_XFT_TFT_SW_RST_CFG */
+#define PSOC_RESET_CONF_SFT_XFT_TFT_SW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_SFT_XFT_TFT_SW_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_DDMA_PRSTN_RST_CFG */
+#define PSOC_RESET_CONF_DDMA_PRSTN_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_DDMA_PRSTN_RST_CFG_EN_MASK 0xFF
+
+/* PSOC_RESET_CONF_DDMA_SOFT_RST_CFG */
+#define PSOC_RESET_CONF_DDMA_SOFT_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_DDMA_SOFT_RST_CFG_EN_MASK 0xFF
+
+/* PSOC_RESET_CONF_DDMA_FW_RST_CFG */
+#define PSOC_RESET_CONF_DDMA_FW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_DDMA_FW_RST_CFG_EN_MASK 0xFF
+
+/* PSOC_RESET_CONF_DDMA_WD_RST_CFG */
+#define PSOC_RESET_CONF_DDMA_WD_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_DDMA_WD_RST_CFG_EN_MASK 0xFF
+
+/* PSOC_RESET_CONF_DDMA_MNL_RST_CFG */
+#define PSOC_RESET_CONF_DDMA_MNL_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_DDMA_MNL_RST_CFG_EN_MASK 0xFF
+
+/* PSOC_RESET_CONF_DDMA_FLR_RST_CFG */
+#define PSOC_RESET_CONF_DDMA_FLR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_DDMA_FLR_RST_CFG_EN_MASK 0xFF
+
+/* PSOC_RESET_CONF_DDMA_ECC_DERR_RST_CFG */
+#define PSOC_RESET_CONF_DDMA_ECC_DERR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_DDMA_ECC_DERR_RST_CFG_EN_MASK 0xFF
+
+/* PSOC_RESET_CONF_DDMA_SW_RST_CFG */
+#define PSOC_RESET_CONF_DDMA_SW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_DDMA_SW_RST_CFG_EN_MASK 0xFF
+
+/* PSOC_RESET_CONF_KDMA_PRSTN_RST_CFG */
+#define PSOC_RESET_CONF_KDMA_PRSTN_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_KDMA_PRSTN_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_KDMA_SOFT_RST_CFG */
+#define PSOC_RESET_CONF_KDMA_SOFT_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_KDMA_SOFT_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_KDMA_FW_RST_CFG */
+#define PSOC_RESET_CONF_KDMA_FW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_KDMA_FW_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_KDMA_WD_RST_CFG */
+#define PSOC_RESET_CONF_KDMA_WD_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_KDMA_WD_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_KDMA_MNL_RST_CFG */
+#define PSOC_RESET_CONF_KDMA_MNL_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_KDMA_MNL_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_KDMA_FLR_RST_CFG */
+#define PSOC_RESET_CONF_KDMA_FLR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_KDMA_FLR_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_KDMA_ECC_DERR_RST_CFG */
+#define PSOC_RESET_CONF_KDMA_ECC_DERR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_KDMA_ECC_DERR_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_KDMA_SW_RST_CFG */
+#define PSOC_RESET_CONF_KDMA_SW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_KDMA_SW_RST_CFG_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PDMA_PRSTN_RST_CFG */
+#define PSOC_RESET_CONF_PDMA_PRSTN_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PDMA_PRSTN_RST_CFG_EN_MASK 0x3
+
+/* PSOC_RESET_CONF_PDMA_SOFT_RST_CFG */
+#define PSOC_RESET_CONF_PDMA_SOFT_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PDMA_SOFT_RST_CFG_EN_MASK 0x3
+
+/* PSOC_RESET_CONF_PDMA_FW_RST_CFG */
+#define PSOC_RESET_CONF_PDMA_FW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PDMA_FW_RST_CFG_EN_MASK 0x3
+
+/* PSOC_RESET_CONF_PDMA_WD_RST_CFG */
+#define PSOC_RESET_CONF_PDMA_WD_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PDMA_WD_RST_CFG_EN_MASK 0x3
+
+/* PSOC_RESET_CONF_PDMA_MNL_RST_CFG */
+#define PSOC_RESET_CONF_PDMA_MNL_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PDMA_MNL_RST_CFG_EN_MASK 0x3
+
+/* PSOC_RESET_CONF_PDMA_FLR_RST_CFG */
+#define PSOC_RESET_CONF_PDMA_FLR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PDMA_FLR_RST_CFG_EN_MASK 0x3
+
+/* PSOC_RESET_CONF_PDMA_ECC_DERR_RST_CFG */
+#define PSOC_RESET_CONF_PDMA_ECC_DERR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PDMA_ECC_DERR_RST_CFG_EN_MASK 0x3
+
+/* PSOC_RESET_CONF_PDMA_SW_RST_CFG */
+#define PSOC_RESET_CONF_PDMA_SW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_PDMA_SW_RST_CFG_EN_MASK 0x3
+
+/* PSOC_RESET_CONF_ARC_SS_PRSTN_RST_CFG */
+#define PSOC_RESET_CONF_ARC_SS_PRSTN_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_ARC_SS_PRSTN_RST_CFG_EN_MASK 0x1F
+
+/* PSOC_RESET_CONF_ARC_SS_SOFT_RST_CFG */
+#define PSOC_RESET_CONF_ARC_SS_SOFT_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_ARC_SS_SOFT_RST_CFG_EN_MASK 0x1F
+
+/* PSOC_RESET_CONF_ARC_SS_FW_RST_CFG */
+#define PSOC_RESET_CONF_ARC_SS_FW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_ARC_SS_FW_RST_CFG_EN_MASK 0x1F
+
+/* PSOC_RESET_CONF_ARC_SS_WD_RST_CFG */
+#define PSOC_RESET_CONF_ARC_SS_WD_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_ARC_SS_WD_RST_CFG_EN_MASK 0x1F
+
+/* PSOC_RESET_CONF_ARC_SS_MNL_RST_CFG */
+#define PSOC_RESET_CONF_ARC_SS_MNL_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_ARC_SS_MNL_RST_CFG_EN_MASK 0x1F
+
+/* PSOC_RESET_CONF_ARC_SS_FLR_RST_CFG */
+#define PSOC_RESET_CONF_ARC_SS_FLR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_ARC_SS_FLR_RST_CFG_EN_MASK 0x1F
+
+/* PSOC_RESET_CONF_ARC_SS_ECC_DERR_RST_CFG */
+#define PSOC_RESET_CONF_ARC_SS_ECC_DERR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_ARC_SS_ECC_DERR_RST_CFG_EN_MASK 0x1F
+
+/* PSOC_RESET_CONF_ARC_SS_SW_RST_CFG */
+#define PSOC_RESET_CONF_ARC_SS_SW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_ARC_SS_SW_RST_CFG_EN_MASK 0x1F
+
+/* PSOC_RESET_CONF_ROTATOR_PRSTN_RST_CFG */
+#define PSOC_RESET_CONF_ROTATOR_PRSTN_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_ROTATOR_PRSTN_RST_CFG_EN_MASK 0x3
+
+/* PSOC_RESET_CONF_ROTATOR_SOFT_RST_CFG */
+#define PSOC_RESET_CONF_ROTATOR_SOFT_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_ROTATOR_SOFT_RST_CFG_EN_MASK 0x3
+
+/* PSOC_RESET_CONF_ROTATOR_FW_RST_CFG */
+#define PSOC_RESET_CONF_ROTATOR_FW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_ROTATOR_FW_RST_CFG_EN_MASK 0x3
+
+/* PSOC_RESET_CONF_ROTATOR_WD_RST_CFG */
+#define PSOC_RESET_CONF_ROTATOR_WD_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_ROTATOR_WD_RST_CFG_EN_MASK 0x3
+
+/* PSOC_RESET_CONF_ROTATOR_MNL_RST_CFG */
+#define PSOC_RESET_CONF_ROTATOR_MNL_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_ROTATOR_MNL_RST_CFG_EN_MASK 0x3
+
+/* PSOC_RESET_CONF_ROTATOR_FLR_RST_CFG */
+#define PSOC_RESET_CONF_ROTATOR_FLR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_ROTATOR_FLR_RST_CFG_EN_MASK 0x3
+
+/* PSOC_RESET_CONF_ROTATOR_ECC_DERR_RST_CFG */
+#define PSOC_RESET_CONF_ROTATOR_ECC_DERR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_ROTATOR_ECC_DERR_RST_CFG_EN_MASK 0x3
+
+/* PSOC_RESET_CONF_ROTATOR_SW_RST_CFG */
+#define PSOC_RESET_CONF_ROTATOR_SW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_ROTATOR_SW_RST_CFG_EN_MASK 0x3
+
+/* PSOC_RESET_CONF_SM_PRSTN_RST_CFG */
+#define PSOC_RESET_CONF_SM_PRSTN_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_SM_PRSTN_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_SM_SOFT_RST_CFG */
+#define PSOC_RESET_CONF_SM_SOFT_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_SM_SOFT_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_SM_FW_RST_CFG */
+#define PSOC_RESET_CONF_SM_FW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_SM_FW_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_SM_WD_RST_CFG */
+#define PSOC_RESET_CONF_SM_WD_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_SM_WD_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_SM_MNL_RST_CFG */
+#define PSOC_RESET_CONF_SM_MNL_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_SM_MNL_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_SM_FLR_RST_CFG */
+#define PSOC_RESET_CONF_SM_FLR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_SM_FLR_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_SM_ECC_DERR_RST_CFG */
+#define PSOC_RESET_CONF_SM_ECC_DERR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_SM_ECC_DERR_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_SM_SW_RST_CFG */
+#define PSOC_RESET_CONF_SM_SW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_SM_SW_RST_CFG_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_VIDEO_DEC_PRSTN_RST_CFG */
+#define PSOC_RESET_CONF_VIDEO_DEC_PRSTN_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_VIDEO_DEC_PRSTN_RST_CFG_EN_MASK 0x3FF
+
+/* PSOC_RESET_CONF_VIDEO_DEC_SOFT_RST_CFG */
+#define PSOC_RESET_CONF_VIDEO_DEC_SOFT_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_VIDEO_DEC_SOFT_RST_CFG_EN_MASK 0x3FF
+
+/* PSOC_RESET_CONF_VIDEO_DEC_FW_RST_CFG */
+#define PSOC_RESET_CONF_VIDEO_DEC_FW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_VIDEO_DEC_FW_RST_CFG_EN_MASK 0x3FF
+
+/* PSOC_RESET_CONF_VIDEO_DEC_WD_RST_CFG */
+#define PSOC_RESET_CONF_VIDEO_DEC_WD_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_VIDEO_DEC_WD_RST_CFG_EN_MASK 0x3FF
+
+/* PSOC_RESET_CONF_VIDEO_DEC_MNL_RST_CFG */
+#define PSOC_RESET_CONF_VIDEO_DEC_MNL_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_VIDEO_DEC_MNL_RST_CFG_EN_MASK 0x3FF
+
+/* PSOC_RESET_CONF_VIDEO_DEC_FLR_RST_CFG */
+#define PSOC_RESET_CONF_VIDEO_DEC_FLR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_VIDEO_DEC_FLR_RST_CFG_EN_MASK 0x3FF
+
+/* PSOC_RESET_CONF_VIDEO_DEC_ECC_DERR_RST_CFG */
+#define PSOC_RESET_CONF_VIDEO_DEC_ECC_DERR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_VIDEO_DEC_ECC_DERR_RST_CFG_EN_MASK 0x3FF
+
+/* PSOC_RESET_CONF_VIDEO_DEC_SW_RST_CFG */
+#define PSOC_RESET_CONF_VIDEO_DEC_SW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_VIDEO_DEC_SW_RST_CFG_EN_MASK 0x3FF
+
+/* PSOC_RESET_CONF_HBM_MC_PRSTN_RST_CFG */
+#define PSOC_RESET_CONF_HBM_MC_PRSTN_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_HBM_MC_PRSTN_RST_CFG_EN_MASK 0x3F
+
+/* PSOC_RESET_CONF_HBM_MC_SOFT_RST_CFG */
+#define PSOC_RESET_CONF_HBM_MC_SOFT_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_HBM_MC_SOFT_RST_CFG_EN_MASK 0x3F
+
+/* PSOC_RESET_CONF_HBM_MC_FW_RST_CFG */
+#define PSOC_RESET_CONF_HBM_MC_FW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_HBM_MC_FW_RST_CFG_EN_MASK 0x3F
+
+/* PSOC_RESET_CONF_HBM_MC_WD_RST_CFG */
+#define PSOC_RESET_CONF_HBM_MC_WD_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_HBM_MC_WD_RST_CFG_EN_MASK 0x3F
+
+/* PSOC_RESET_CONF_HBM_MC_MNL_RST_CFG */
+#define PSOC_RESET_CONF_HBM_MC_MNL_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_HBM_MC_MNL_RST_CFG_EN_MASK 0x3F
+
+/* PSOC_RESET_CONF_HBM_MC_FLR_RST_CFG */
+#define PSOC_RESET_CONF_HBM_MC_FLR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_HBM_MC_FLR_RST_CFG_EN_MASK 0x3F
+
+/* PSOC_RESET_CONF_HBM_MC_ECC_DERR_RST_CFG */
+#define PSOC_RESET_CONF_HBM_MC_ECC_DERR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_HBM_MC_ECC_DERR_RST_CFG_EN_MASK 0x3F
+
+/* PSOC_RESET_CONF_HBM_MC_SW_RST_CFG */
+#define PSOC_RESET_CONF_HBM_MC_SW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_HBM_MC_SW_RST_CFG_EN_MASK 0x3F
+
+/* PSOC_RESET_CONF_NIC_PRSTN_RST_CFG */
+#define PSOC_RESET_CONF_NIC_PRSTN_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_NIC_PRSTN_RST_CFG_EN_MASK 0xFFF
+
+/* PSOC_RESET_CONF_NIC_SOFT_RST_CFG */
+#define PSOC_RESET_CONF_NIC_SOFT_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_NIC_SOFT_RST_CFG_EN_MASK 0xFFF
+
+/* PSOC_RESET_CONF_NIC_FW_RST_CFG */
+#define PSOC_RESET_CONF_NIC_FW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_NIC_FW_RST_CFG_EN_MASK 0xFFF
+
+/* PSOC_RESET_CONF_NIC_WD_RST_CFG */
+#define PSOC_RESET_CONF_NIC_WD_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_NIC_WD_RST_CFG_EN_MASK 0xFFF
+
+/* PSOC_RESET_CONF_NIC_MNL_RST_CFG */
+#define PSOC_RESET_CONF_NIC_MNL_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_NIC_MNL_RST_CFG_EN_MASK 0xFFF
+
+/* PSOC_RESET_CONF_NIC_FLR_RST_CFG */
+#define PSOC_RESET_CONF_NIC_FLR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_NIC_FLR_RST_CFG_EN_MASK 0xFFF
+
+/* PSOC_RESET_CONF_NIC_ECC_DERR_RST_CFG */
+#define PSOC_RESET_CONF_NIC_ECC_DERR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_NIC_ECC_DERR_RST_CFG_EN_MASK 0xFFF
+
+/* PSOC_RESET_CONF_NIC_SW_RST_CFG */
+#define PSOC_RESET_CONF_NIC_SW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_NIC_SW_RST_CFG_EN_MASK 0xFFF
+
+/* PSOC_RESET_CONF_NIC_PRT_PRSTN_RST_CFG */
+#define PSOC_RESET_CONF_NIC_PRT_PRSTN_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_NIC_PRT_PRSTN_RST_CFG_EN_MASK 0xFFF
+
+/* PSOC_RESET_CONF_NIC_PRT_SOFT_RST_CFG */
+#define PSOC_RESET_CONF_NIC_PRT_SOFT_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_NIC_PRT_SOFT_RST_CFG_EN_MASK 0xFFF
+
+/* PSOC_RESET_CONF_NIC_PRT_FW_RST_CFG */
+#define PSOC_RESET_CONF_NIC_PRT_FW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_NIC_PRT_FW_RST_CFG_EN_MASK 0xFFF
+
+/* PSOC_RESET_CONF_NIC_PRT_WD_RST_CFG */
+#define PSOC_RESET_CONF_NIC_PRT_WD_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_NIC_PRT_WD_RST_CFG_EN_MASK 0xFFF
+
+/* PSOC_RESET_CONF_NIC_PRT_MNL_RST_CFG */
+#define PSOC_RESET_CONF_NIC_PRT_MNL_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_NIC_PRT_MNL_RST_CFG_EN_MASK 0xFFF
+
+/* PSOC_RESET_CONF_NIC_PRT_FLR_RST_CFG */
+#define PSOC_RESET_CONF_NIC_PRT_FLR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_NIC_PRT_FLR_RST_CFG_EN_MASK 0xFFF
+
+/* PSOC_RESET_CONF_NIC_PRT_ECC_DERR_RST_CFG */
+#define PSOC_RESET_CONF_NIC_PRT_ECC_DERR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_NIC_PRT_ECC_DERR_RST_CFG_EN_MASK 0xFFF
+
+/* PSOC_RESET_CONF_NIC_PRT_SW_RST_CFG */
+#define PSOC_RESET_CONF_NIC_PRT_SW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_NIC_PRT_SW_RST_CFG_EN_MASK 0xFFF
+
+/* PSOC_RESET_CONF_NIC_CH_PRSTN_RST_CFG */
+#define PSOC_RESET_CONF_NIC_CH_PRSTN_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_NIC_CH_PRSTN_RST_CFG_EN_MASK 0x7
+
+/* PSOC_RESET_CONF_NIC_CH_SOFT_RST_CFG */
+#define PSOC_RESET_CONF_NIC_CH_SOFT_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_NIC_CH_SOFT_RST_CFG_EN_MASK 0x7
+
+/* PSOC_RESET_CONF_NIC_CH_FW_RST_CFG */
+#define PSOC_RESET_CONF_NIC_CH_FW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_NIC_CH_FW_RST_CFG_EN_MASK 0x7
+
+/* PSOC_RESET_CONF_NIC_CH_WD_RST_CFG */
+#define PSOC_RESET_CONF_NIC_CH_WD_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_NIC_CH_WD_RST_CFG_EN_MASK 0x7
+
+/* PSOC_RESET_CONF_NIC_CH_MNL_RST_CFG */
+#define PSOC_RESET_CONF_NIC_CH_MNL_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_NIC_CH_MNL_RST_CFG_EN_MASK 0x7
+
+/* PSOC_RESET_CONF_NIC_CH_FLR_RST_CFG */
+#define PSOC_RESET_CONF_NIC_CH_FLR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_NIC_CH_FLR_RST_CFG_EN_MASK 0x7
+
+/* PSOC_RESET_CONF_NIC_CH_ECC_DERR_RST_CFG */
+#define PSOC_RESET_CONF_NIC_CH_ECC_DERR_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_NIC_CH_ECC_DERR_RST_CFG_EN_MASK 0x7
+
+/* PSOC_RESET_CONF_NIC_CH_SW_RST_CFG */
+#define PSOC_RESET_CONF_NIC_CH_SW_RST_CFG_EN_SHIFT 0
+#define PSOC_RESET_CONF_NIC_CH_SW_RST_CFG_EN_MASK 0x7
+
+/* PSOC_RESET_CONF_SOFT_RST */
+#define PSOC_RESET_CONF_SOFT_RST_IND_SHIFT 0
+#define PSOC_RESET_CONF_SOFT_RST_IND_MASK 0x1
+
+/* PSOC_RESET_CONF_SW_ALL_RST */
+#define PSOC_RESET_CONF_SW_ALL_RST_IND_SHIFT 0
+#define PSOC_RESET_CONF_SW_ALL_RST_IND_MASK 0x1
+
+/* PSOC_RESET_CONF_UNIT_RST_N */
+#define PSOC_RESET_CONF_UNIT_RST_N_IND_SHIFT 0
+#define PSOC_RESET_CONF_UNIT_RST_N_IND_MASK 0x1
+
+/* PSOC_RESET_CONF_PSOC_UNIT_RST */
+#define PSOC_RESET_CONF_PSOC_UNIT_RST_EN_SHIFT 0
+#define PSOC_RESET_CONF_PSOC_UNIT_RST_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_CPU_UNIT_RST */
+#define PSOC_RESET_CONF_CPU_UNIT_RST_EN_SHIFT 0
+#define PSOC_RESET_CONF_CPU_UNIT_RST_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_ARC_UNIT_RST */
+#define PSOC_RESET_CONF_ARC_UNIT_RST_EN_SHIFT 0
+#define PSOC_RESET_CONF_ARC_UNIT_RST_EN_MASK 0x3
+
+/* PSOC_RESET_CONF_SIF_UNIT_RST */
+#define PSOC_RESET_CONF_SIF_UNIT_RST_EN_SHIFT 0
+#define PSOC_RESET_CONF_SIF_UNIT_RST_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_SRAM_UNIT_RST */
+#define PSOC_RESET_CONF_SRAM_UNIT_RST_EN_SHIFT 0
+#define PSOC_RESET_CONF_SRAM_UNIT_RST_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_PCIE_CTRL_UNIT_RST */
+#define PSOC_RESET_CONF_PCIE_CTRL_UNIT_RST_EN_SHIFT 0
+#define PSOC_RESET_CONF_PCIE_CTRL_UNIT_RST_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PCIE_PHY_CFG_UNIT_RST */
+#define PSOC_RESET_CONF_PCIE_PHY_CFG_UNIT_RST_EN_SHIFT 0
+#define PSOC_RESET_CONF_PCIE_PHY_CFG_UNIT_RST_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PCIE_IF_UNIT_RST */
+#define PSOC_RESET_CONF_PCIE_IF_UNIT_RST_EN_SHIFT 0
+#define PSOC_RESET_CONF_PCIE_IF_UNIT_RST_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_TPC_DIV_UNIT_RST */
+#define PSOC_RESET_CONF_TPC_DIV_UNIT_RST_EN_SHIFT 0
+#define PSOC_RESET_CONF_TPC_DIV_UNIT_RST_EN_MASK 0x1F
+
+/* PSOC_RESET_CONF_HBM_DIV_UNIT_RST */
+#define PSOC_RESET_CONF_HBM_DIV_UNIT_RST_EN_SHIFT 0
+#define PSOC_RESET_CONF_HBM_DIV_UNIT_RST_EN_MASK 0x3F
+
+/* PSOC_RESET_CONF_PMMU_UNIT_RST */
+#define PSOC_RESET_CONF_PMMU_UNIT_RST_EN_SHIFT 0
+#define PSOC_RESET_CONF_PMMU_UNIT_RST_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PM_UNIT_RST */
+#define PSOC_RESET_CONF_PM_UNIT_RST_EN_SHIFT 0
+#define PSOC_RESET_CONF_PM_UNIT_RST_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_TS_UNIT_RST */
+#define PSOC_RESET_CONF_TS_UNIT_RST_EN_SHIFT 0
+#define PSOC_RESET_CONF_TS_UNIT_RST_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_TS_IF_UNIT_RST */
+#define PSOC_RESET_CONF_TS_IF_UNIT_RST_EN_SHIFT 0
+#define PSOC_RESET_CONF_TS_IF_UNIT_RST_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_PLL_L_UNIT_RST */
+#define PSOC_RESET_CONF_PLL_L_UNIT_RST_EN_SHIFT 0
+#define PSOC_RESET_CONF_PLL_L_UNIT_RST_EN_MASK 0xFFFFFFFF
+
+/* PSOC_RESET_CONF_PLL_H_UNIT_RST */
+#define PSOC_RESET_CONF_PLL_H_UNIT_RST_EN_SHIFT 0
+#define PSOC_RESET_CONF_PLL_H_UNIT_RST_EN_MASK 0x3
+
+/* PSOC_RESET_CONF_MME_EUS_UNIT_RST */
+#define PSOC_RESET_CONF_MME_EUS_UNIT_RST_EN_SHIFT 0
+#define PSOC_RESET_CONF_MME_EUS_UNIT_RST_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_MSS_CLS_UNIT_RST */
+#define PSOC_RESET_CONF_MSS_CLS_UNIT_RST_EN_SHIFT 0
+#define PSOC_RESET_CONF_MSS_CLS_UNIT_RST_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_TPC_UNIT_RST */
+#define PSOC_RESET_CONF_TPC_UNIT_RST_EN_SHIFT 0
+#define PSOC_RESET_CONF_TPC_UNIT_RST_EN_MASK 0x1FFFFFF
+
+/* PSOC_RESET_CONF_HIF_HMMU_UNIT_RST */
+#define PSOC_RESET_CONF_HIF_HMMU_UNIT_RST_EN_SHIFT 0
+#define PSOC_RESET_CONF_HIF_HMMU_UNIT_RST_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_XBAR_UNIT_RST */
+#define PSOC_RESET_CONF_XBAR_UNIT_RST_EN_SHIFT 0
+#define PSOC_RESET_CONF_XBAR_UNIT_RST_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_SFT_XFT_TFT_UNIT_RST */
+#define PSOC_RESET_CONF_SFT_XFT_TFT_UNIT_RST_EN_SHIFT 0
+#define PSOC_RESET_CONF_SFT_XFT_TFT_UNIT_RST_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_DDMA_UNIT_RST */
+#define PSOC_RESET_CONF_DDMA_UNIT_RST_EN_SHIFT 0
+#define PSOC_RESET_CONF_DDMA_UNIT_RST_EN_MASK 0xFF
+
+/* PSOC_RESET_CONF_KDMA_UNIT_RST */
+#define PSOC_RESET_CONF_KDMA_UNIT_RST_EN_SHIFT 0
+#define PSOC_RESET_CONF_KDMA_UNIT_RST_EN_MASK 0x1
+
+/* PSOC_RESET_CONF_PDMA_UNIT_RST */
+#define PSOC_RESET_CONF_PDMA_UNIT_RST_EN_SHIFT 0
+#define PSOC_RESET_CONF_PDMA_UNIT_RST_EN_MASK 0x3
+
+/* PSOC_RESET_CONF_ARC_SS_UNIT_RST */
+#define PSOC_RESET_CONF_ARC_SS_UNIT_RST_EN_SHIFT 0
+#define PSOC_RESET_CONF_ARC_SS_UNIT_RST_EN_MASK 0x1F
+
+/* PSOC_RESET_CONF_ROTATOR_UNIT_RST */
+#define PSOC_RESET_CONF_ROTATOR_UNIT_RST_EN_SHIFT 0
+#define PSOC_RESET_CONF_ROTATOR_UNIT_RST_EN_MASK 0x3
+
+/* PSOC_RESET_CONF_SM_UNIT_RST */
+#define PSOC_RESET_CONF_SM_UNIT_RST_EN_SHIFT 0
+#define PSOC_RESET_CONF_SM_UNIT_RST_EN_MASK 0xF
+
+/* PSOC_RESET_CONF_VIDEO_DEC_UNIT_RST */
+#define PSOC_RESET_CONF_VIDEO_DEC_UNIT_RST_EN_SHIFT 0
+#define PSOC_RESET_CONF_VIDEO_DEC_UNIT_RST_EN_MASK 0x3FF
+
+/* PSOC_RESET_CONF_HBM_MC_UNIT_RST */
+#define PSOC_RESET_CONF_HBM_MC_UNIT_RST_EN_SHIFT 0
+#define PSOC_RESET_CONF_HBM_MC_UNIT_RST_EN_MASK 0x3F
+
+/* PSOC_RESET_CONF_NIC_UNIT_RST */
+#define PSOC_RESET_CONF_NIC_UNIT_RST_EN_SHIFT 0
+#define PSOC_RESET_CONF_NIC_UNIT_RST_EN_MASK 0xFFF
+
+/* PSOC_RESET_CONF_NIC_PRT_UNIT_RST */
+#define PSOC_RESET_CONF_NIC_PRT_UNIT_RST_EN_SHIFT 0
+#define PSOC_RESET_CONF_NIC_PRT_UNIT_RST_EN_MASK 0xFFF
+
+/* PSOC_RESET_CONF_NIC_CH_UNIT_RST */
+#define PSOC_RESET_CONF_NIC_CH_UNIT_RST_EN_SHIFT 0
+#define PSOC_RESET_CONF_NIC_CH_UNIT_RST_EN_MASK 0x7
+
+/* PSOC_RESET_CONF_PSOC_0_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PSOC_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PSOC_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PSOC_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PSOC_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_CPU_0_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_CPU_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_CPU_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_CPU_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_CPU_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_ARC_0_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_ARC_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_ARC_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_ARC_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_ARC_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_ARC_1_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_ARC_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_ARC_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_ARC_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_ARC_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_SIF_0_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_SIF_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_SIF_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_SIF_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_SIF_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_SIF_1_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_SIF_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_SIF_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_SIF_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_SIF_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_SIF_2_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_SIF_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_SIF_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_SIF_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_SIF_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_SIF_3_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_SIF_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_SIF_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_SIF_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_SIF_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_SRAM_0_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_SRAM_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_SRAM_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_SRAM_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_SRAM_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_SRAM_1_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_SRAM_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_SRAM_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_SRAM_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_SRAM_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_SRAM_2_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_SRAM_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_SRAM_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_SRAM_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_SRAM_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_SRAM_3_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_SRAM_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_SRAM_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_SRAM_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_SRAM_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PCIE_CTRL_0_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PCIE_CTRL_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PCIE_CTRL_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PCIE_CTRL_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PCIE_CTRL_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PCIE_PHY_CFG_0_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PCIE_PHY_CFG_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PCIE_PHY_CFG_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PCIE_PHY_CFG_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PCIE_PHY_CFG_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PCIE_IF_0_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PCIE_IF_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PCIE_IF_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PCIE_IF_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PCIE_IF_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_TPC_DIV_0_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_TPC_DIV_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_TPC_DIV_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_TPC_DIV_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_TPC_DIV_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_TPC_DIV_1_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_TPC_DIV_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_TPC_DIV_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_TPC_DIV_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_TPC_DIV_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_TPC_DIV_2_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_TPC_DIV_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_TPC_DIV_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_TPC_DIV_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_TPC_DIV_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_TPC_DIV_3_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_TPC_DIV_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_TPC_DIV_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_TPC_DIV_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_TPC_DIV_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_TPC_DIV_4_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_TPC_DIV_4_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_TPC_DIV_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_TPC_DIV_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_TPC_DIV_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_HBM_DIV_0_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_HBM_DIV_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_HBM_DIV_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_HBM_DIV_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_HBM_DIV_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_HBM_DIV_1_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_HBM_DIV_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_HBM_DIV_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_HBM_DIV_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_HBM_DIV_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_HBM_DIV_2_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_HBM_DIV_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_HBM_DIV_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_HBM_DIV_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_HBM_DIV_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_HBM_DIV_3_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_HBM_DIV_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_HBM_DIV_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_HBM_DIV_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_HBM_DIV_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_HBM_DIV_4_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_HBM_DIV_4_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_HBM_DIV_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_HBM_DIV_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_HBM_DIV_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_HBM_DIV_5_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_HBM_DIV_5_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_HBM_DIV_5_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_HBM_DIV_5_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_HBM_DIV_5_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PMMU_0_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PMMU_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PMMU_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PMMU_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PMMU_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PM_0_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PM_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PM_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PM_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PM_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PM_1_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PM_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PM_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PM_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PM_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PM_2_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PM_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PM_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PM_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PM_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PM_3_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PM_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PM_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PM_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PM_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_TS_0_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_TS_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_TS_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_TS_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_TS_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_TS_1_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_TS_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_TS_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_TS_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_TS_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_TS_2_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_TS_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_TS_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_TS_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_TS_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_TS_3_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_TS_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_TS_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_TS_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_TS_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_TS_IF_0_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_TS_IF_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_TS_IF_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_TS_IF_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_TS_IF_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_TS_IF_1_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_TS_IF_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_TS_IF_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_TS_IF_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_TS_IF_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_TS_IF_2_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_TS_IF_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_TS_IF_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_TS_IF_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_TS_IF_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_TS_IF_3_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_TS_IF_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_TS_IF_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_TS_IF_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_TS_IF_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PLL_L_0_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PLL_L_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PLL_L_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PLL_L_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PLL_L_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PLL_L_1_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PLL_L_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PLL_L_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PLL_L_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PLL_L_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PLL_L_2_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PLL_L_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PLL_L_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PLL_L_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PLL_L_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PLL_L_3_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PLL_L_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PLL_L_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PLL_L_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PLL_L_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PLL_L_4_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PLL_L_4_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PLL_L_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PLL_L_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PLL_L_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PLL_L_5_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PLL_L_5_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PLL_L_5_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PLL_L_5_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PLL_L_5_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PLL_L_6_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PLL_L_6_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PLL_L_6_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PLL_L_6_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PLL_L_6_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PLL_L_7_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PLL_L_7_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PLL_L_7_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PLL_L_7_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PLL_L_7_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PLL_L_8_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PLL_L_8_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PLL_L_8_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PLL_L_8_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PLL_L_8_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PLL_L_9_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PLL_L_9_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PLL_L_9_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PLL_L_9_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PLL_L_9_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PLL_L_10_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PLL_L_10_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PLL_L_10_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PLL_L_10_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PLL_L_10_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PLL_L_11_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PLL_L_11_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PLL_L_11_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PLL_L_11_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PLL_L_11_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PLL_L_12_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PLL_L_12_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PLL_L_12_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PLL_L_12_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PLL_L_12_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PLL_L_13_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PLL_L_13_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PLL_L_13_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PLL_L_13_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PLL_L_13_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PLL_L_14_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PLL_L_14_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PLL_L_14_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PLL_L_14_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PLL_L_14_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PLL_L_15_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PLL_L_15_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PLL_L_15_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PLL_L_15_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PLL_L_15_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PLL_L_16_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PLL_L_16_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PLL_L_16_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PLL_L_16_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PLL_L_16_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PLL_L_17_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PLL_L_17_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PLL_L_17_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PLL_L_17_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PLL_L_17_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PLL_L_18_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PLL_L_18_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PLL_L_18_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PLL_L_18_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PLL_L_18_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PLL_L_19_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PLL_L_19_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PLL_L_19_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PLL_L_19_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PLL_L_19_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PLL_L_20_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PLL_L_20_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PLL_L_20_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PLL_L_20_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PLL_L_20_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PLL_L_21_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PLL_L_21_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PLL_L_21_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PLL_L_21_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PLL_L_21_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PLL_L_22_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PLL_L_22_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PLL_L_22_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PLL_L_22_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PLL_L_22_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PLL_L_23_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PLL_L_23_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PLL_L_23_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PLL_L_23_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PLL_L_23_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PLL_L_24_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PLL_L_24_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PLL_L_24_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PLL_L_24_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PLL_L_24_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PLL_L_25_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PLL_L_25_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PLL_L_25_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PLL_L_25_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PLL_L_25_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PLL_L_26_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PLL_L_26_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PLL_L_26_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PLL_L_26_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PLL_L_26_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PLL_L_27_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PLL_L_27_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PLL_L_27_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PLL_L_27_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PLL_L_27_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PLL_L_28_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PLL_L_28_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PLL_L_28_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PLL_L_28_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PLL_L_28_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PLL_L_29_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PLL_L_29_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PLL_L_29_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PLL_L_29_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PLL_L_29_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PLL_L_30_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PLL_L_30_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PLL_L_30_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PLL_L_30_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PLL_L_30_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PLL_L_31_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PLL_L_31_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PLL_L_31_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PLL_L_31_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PLL_L_31_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PLL_H_0_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PLL_H_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PLL_H_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PLL_H_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PLL_H_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PLL_H_1_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PLL_H_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PLL_H_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PLL_H_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PLL_H_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_MME_EUS_0_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_MME_EUS_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_MME_EUS_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_MME_EUS_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_MME_EUS_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_MME_EUS_1_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_MME_EUS_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_MME_EUS_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_MME_EUS_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_MME_EUS_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_MME_EUS_2_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_MME_EUS_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_MME_EUS_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_MME_EUS_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_MME_EUS_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_MME_EUS_3_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_MME_EUS_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_MME_EUS_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_MME_EUS_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_MME_EUS_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_MSS_CLS_0_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_MSS_CLS_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_MSS_CLS_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_MSS_CLS_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_MSS_CLS_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_MSS_CLS_1_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_MSS_CLS_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_MSS_CLS_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_MSS_CLS_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_MSS_CLS_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_MSS_CLS_2_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_MSS_CLS_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_MSS_CLS_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_MSS_CLS_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_MSS_CLS_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_MSS_CLS_3_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_MSS_CLS_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_MSS_CLS_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_MSS_CLS_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_MSS_CLS_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_TPC_0_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_TPC_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_TPC_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_TPC_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_TPC_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_TPC_1_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_TPC_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_TPC_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_TPC_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_TPC_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_TPC_2_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_TPC_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_TPC_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_TPC_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_TPC_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_TPC_3_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_TPC_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_TPC_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_TPC_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_TPC_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_TPC_4_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_TPC_4_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_TPC_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_TPC_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_TPC_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_TPC_5_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_TPC_5_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_TPC_5_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_TPC_5_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_TPC_5_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_TPC_6_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_TPC_6_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_TPC_6_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_TPC_6_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_TPC_6_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_TPC_7_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_TPC_7_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_TPC_7_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_TPC_7_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_TPC_7_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_TPC_8_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_TPC_8_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_TPC_8_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_TPC_8_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_TPC_8_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_TPC_9_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_TPC_9_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_TPC_9_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_TPC_9_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_TPC_9_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_TPC_10_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_TPC_10_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_TPC_10_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_TPC_10_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_TPC_10_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_TPC_11_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_TPC_11_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_TPC_11_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_TPC_11_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_TPC_11_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_TPC_12_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_TPC_12_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_TPC_12_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_TPC_12_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_TPC_12_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_TPC_13_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_TPC_13_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_TPC_13_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_TPC_13_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_TPC_13_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_TPC_14_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_TPC_14_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_TPC_14_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_TPC_14_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_TPC_14_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_TPC_15_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_TPC_15_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_TPC_15_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_TPC_15_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_TPC_15_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_TPC_16_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_TPC_16_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_TPC_16_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_TPC_16_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_TPC_16_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_TPC_17_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_TPC_17_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_TPC_17_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_TPC_17_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_TPC_17_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_TPC_18_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_TPC_18_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_TPC_18_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_TPC_18_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_TPC_18_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_TPC_19_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_TPC_19_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_TPC_19_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_TPC_19_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_TPC_19_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_TPC_20_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_TPC_20_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_TPC_20_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_TPC_20_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_TPC_20_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_TPC_21_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_TPC_21_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_TPC_21_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_TPC_21_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_TPC_21_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_TPC_22_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_TPC_22_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_TPC_22_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_TPC_22_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_TPC_22_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_TPC_23_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_TPC_23_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_TPC_23_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_TPC_23_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_TPC_23_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_TPC_24_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_TPC_24_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_TPC_24_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_TPC_24_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_TPC_24_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_HIF_HMMU_0_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_HIF_HMMU_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_HIF_HMMU_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_HIF_HMMU_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_HIF_HMMU_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_HIF_HMMU_1_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_HIF_HMMU_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_HIF_HMMU_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_HIF_HMMU_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_HIF_HMMU_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_HIF_HMMU_2_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_HIF_HMMU_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_HIF_HMMU_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_HIF_HMMU_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_HIF_HMMU_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_HIF_HMMU_3_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_HIF_HMMU_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_HIF_HMMU_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_HIF_HMMU_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_HIF_HMMU_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_XBAR_0_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_XBAR_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_XBAR_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_XBAR_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_XBAR_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_XBAR_1_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_XBAR_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_XBAR_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_XBAR_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_XBAR_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_XBAR_2_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_XBAR_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_XBAR_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_XBAR_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_XBAR_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_XBAR_3_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_XBAR_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_XBAR_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_XBAR_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_XBAR_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_SFT_XFT_TFT_0_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_SFT_XFT_TFT_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_SFT_XFT_TFT_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_SFT_XFT_TFT_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_SFT_XFT_TFT_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_SFT_XFT_TFT_1_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_SFT_XFT_TFT_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_SFT_XFT_TFT_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_SFT_XFT_TFT_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_SFT_XFT_TFT_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_SFT_XFT_TFT_2_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_SFT_XFT_TFT_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_SFT_XFT_TFT_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_SFT_XFT_TFT_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_SFT_XFT_TFT_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_SFT_XFT_TFT_3_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_SFT_XFT_TFT_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_SFT_XFT_TFT_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_SFT_XFT_TFT_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_SFT_XFT_TFT_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_DDMA_0_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_DDMA_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_DDMA_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_DDMA_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_DDMA_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_DDMA_1_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_DDMA_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_DDMA_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_DDMA_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_DDMA_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_DDMA_2_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_DDMA_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_DDMA_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_DDMA_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_DDMA_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_DDMA_3_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_DDMA_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_DDMA_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_DDMA_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_DDMA_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_DDMA_4_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_DDMA_4_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_DDMA_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_DDMA_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_DDMA_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_DDMA_5_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_DDMA_5_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_DDMA_5_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_DDMA_5_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_DDMA_5_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_DDMA_6_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_DDMA_6_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_DDMA_6_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_DDMA_6_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_DDMA_6_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_DDMA_7_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_DDMA_7_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_DDMA_7_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_DDMA_7_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_DDMA_7_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_KDMA_0_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_KDMA_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_KDMA_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_KDMA_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_KDMA_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PDMA_0_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PDMA_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PDMA_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PDMA_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PDMA_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_PDMA_1_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_PDMA_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_PDMA_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_PDMA_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_PDMA_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_ARC_SS_0_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_ARC_SS_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_ARC_SS_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_ARC_SS_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_ARC_SS_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_ARC_SS_1_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_ARC_SS_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_ARC_SS_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_ARC_SS_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_ARC_SS_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_ARC_SS_2_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_ARC_SS_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_ARC_SS_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_ARC_SS_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_ARC_SS_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_ARC_SS_3_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_ARC_SS_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_ARC_SS_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_ARC_SS_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_ARC_SS_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_ARC_SS_4_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_ARC_SS_4_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_ARC_SS_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_ARC_SS_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_ARC_SS_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_ROTATOR_0_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_ROTATOR_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_ROTATOR_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_ROTATOR_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_ROTATOR_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_ROTATOR_1_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_ROTATOR_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_ROTATOR_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_ROTATOR_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_ROTATOR_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_SM_0_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_SM_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_SM_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_SM_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_SM_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_SM_1_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_SM_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_SM_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_SM_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_SM_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_SM_2_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_SM_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_SM_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_SM_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_SM_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_SM_3_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_SM_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_SM_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_SM_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_SM_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_VIDEO_DEC_0_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_VIDEO_DEC_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_VIDEO_DEC_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_VIDEO_DEC_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_VIDEO_DEC_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_VIDEO_DEC_1_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_VIDEO_DEC_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_VIDEO_DEC_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_VIDEO_DEC_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_VIDEO_DEC_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_VIDEO_DEC_2_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_VIDEO_DEC_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_VIDEO_DEC_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_VIDEO_DEC_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_VIDEO_DEC_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_VIDEO_DEC_3_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_VIDEO_DEC_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_VIDEO_DEC_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_VIDEO_DEC_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_VIDEO_DEC_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_VIDEO_DEC_4_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_VIDEO_DEC_4_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_VIDEO_DEC_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_VIDEO_DEC_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_VIDEO_DEC_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_VIDEO_DEC_5_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_VIDEO_DEC_5_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_VIDEO_DEC_5_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_VIDEO_DEC_5_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_VIDEO_DEC_5_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_VIDEO_DEC_6_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_VIDEO_DEC_6_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_VIDEO_DEC_6_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_VIDEO_DEC_6_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_VIDEO_DEC_6_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_VIDEO_DEC_7_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_VIDEO_DEC_7_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_VIDEO_DEC_7_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_VIDEO_DEC_7_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_VIDEO_DEC_7_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_VIDEO_DEC_8_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_VIDEO_DEC_8_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_VIDEO_DEC_8_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_VIDEO_DEC_8_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_VIDEO_DEC_8_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_VIDEO_DEC_9_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_VIDEO_DEC_9_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_VIDEO_DEC_9_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_VIDEO_DEC_9_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_VIDEO_DEC_9_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_HBM_MC_0_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_HBM_MC_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_HBM_MC_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_HBM_MC_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_HBM_MC_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_HBM_MC_1_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_HBM_MC_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_HBM_MC_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_HBM_MC_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_HBM_MC_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_HBM_MC_2_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_HBM_MC_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_HBM_MC_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_HBM_MC_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_HBM_MC_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_HBM_MC_3_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_HBM_MC_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_HBM_MC_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_HBM_MC_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_HBM_MC_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_HBM_MC_4_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_HBM_MC_4_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_HBM_MC_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_HBM_MC_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_HBM_MC_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_HBM_MC_5_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_HBM_MC_5_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_HBM_MC_5_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_HBM_MC_5_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_HBM_MC_5_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_NIC_0_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_NIC_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_NIC_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_NIC_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_NIC_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_NIC_1_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_NIC_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_NIC_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_NIC_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_NIC_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_NIC_2_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_NIC_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_NIC_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_NIC_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_NIC_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_NIC_3_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_NIC_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_NIC_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_NIC_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_NIC_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_NIC_4_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_NIC_4_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_NIC_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_NIC_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_NIC_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_NIC_5_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_NIC_5_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_NIC_5_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_NIC_5_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_NIC_5_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_NIC_6_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_NIC_6_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_NIC_6_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_NIC_6_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_NIC_6_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_NIC_7_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_NIC_7_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_NIC_7_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_NIC_7_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_NIC_7_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_NIC_8_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_NIC_8_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_NIC_8_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_NIC_8_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_NIC_8_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_NIC_9_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_NIC_9_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_NIC_9_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_NIC_9_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_NIC_9_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_NIC_10_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_NIC_10_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_NIC_10_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_NIC_10_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_NIC_10_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_NIC_11_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_NIC_11_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_NIC_11_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_NIC_11_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_NIC_11_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_NIC_PRT_0_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_NIC_PRT_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_NIC_PRT_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_NIC_PRT_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_NIC_PRT_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_NIC_PRT_1_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_NIC_PRT_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_NIC_PRT_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_NIC_PRT_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_NIC_PRT_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_NIC_PRT_2_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_NIC_PRT_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_NIC_PRT_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_NIC_PRT_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_NIC_PRT_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_NIC_PRT_3_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_NIC_PRT_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_NIC_PRT_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_NIC_PRT_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_NIC_PRT_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_NIC_PRT_4_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_NIC_PRT_4_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_NIC_PRT_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_NIC_PRT_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_NIC_PRT_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_NIC_PRT_5_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_NIC_PRT_5_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_NIC_PRT_5_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_NIC_PRT_5_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_NIC_PRT_5_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_NIC_PRT_6_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_NIC_PRT_6_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_NIC_PRT_6_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_NIC_PRT_6_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_NIC_PRT_6_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_NIC_PRT_7_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_NIC_PRT_7_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_NIC_PRT_7_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_NIC_PRT_7_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_NIC_PRT_7_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_NIC_PRT_8_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_NIC_PRT_8_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_NIC_PRT_8_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_NIC_PRT_8_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_NIC_PRT_8_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_NIC_PRT_9_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_NIC_PRT_9_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_NIC_PRT_9_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_NIC_PRT_9_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_NIC_PRT_9_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_NIC_PRT_10_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_NIC_PRT_10_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_NIC_PRT_10_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_NIC_PRT_10_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_NIC_PRT_10_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_NIC_PRT_11_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_NIC_PRT_11_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_NIC_PRT_11_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_NIC_PRT_11_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_NIC_PRT_11_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_NIC_CH_0_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_NIC_CH_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_NIC_CH_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_NIC_CH_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_NIC_CH_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_NIC_CH_1_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_NIC_CH_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_NIC_CH_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_NIC_CH_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_NIC_CH_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+/* PSOC_RESET_CONF_NIC_CH_2_CLK_RST_CTRL */
+#define PSOC_RESET_CONF_NIC_CH_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
+#define PSOC_RESET_CONF_NIC_CH_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
+#define PSOC_RESET_CONF_NIC_CH_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
+#define PSOC_RESET_CONF_NIC_CH_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
+
+#endif /* ASIC_REG_PSOC_RESET_CONF_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/psoc_reset_conf_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/psoc_reset_conf_regs.h
new file mode 100644
index 000000000000..6a89624f01d1
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/psoc_reset_conf_regs.h
@@ -0,0 +1,989 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PSOC_RESET_CONF_REGS_H_
+#define ASIC_REG_PSOC_RESET_CONF_REGS_H_
+
+/*
+ *****************************************
+ *   PSOC_RESET_CONF
+ *   (Prototype: PSOC_RESET_CONF)
+ *****************************************
+ */
+
+#define mmPSOC_RESET_CONF_PSOC_PRSTN_RST_CFG 0x4C74000
+
+#define mmPSOC_RESET_CONF_PSOC_SOFT_RST_CFG 0x4C74004
+
+#define mmPSOC_RESET_CONF_PSOC_FW_RST_CFG 0x4C74008
+
+#define mmPSOC_RESET_CONF_PSOC_WD_RST_CFG 0x4C7400C
+
+#define mmPSOC_RESET_CONF_PSOC_MNL_RST_CFG 0x4C74010
+
+#define mmPSOC_RESET_CONF_PSOC_FLR_RST_CFG 0x4C74014
+
+#define mmPSOC_RESET_CONF_PSOC_ECC_DERR_RST_CFG 0x4C74018
+
+#define mmPSOC_RESET_CONF_PSOC_SW_RST_CFG 0x4C7401C
+
+#define mmPSOC_RESET_CONF_CPU_PRSTN_RST_CFG 0x4C74020
+
+#define mmPSOC_RESET_CONF_CPU_SOFT_RST_CFG 0x4C74024
+
+#define mmPSOC_RESET_CONF_CPU_FW_RST_CFG 0x4C74028
+
+#define mmPSOC_RESET_CONF_CPU_WD_RST_CFG 0x4C7402C
+
+#define mmPSOC_RESET_CONF_CPU_MNL_RST_CFG 0x4C74030
+
+#define mmPSOC_RESET_CONF_CPU_FLR_RST_CFG 0x4C74034
+
+#define mmPSOC_RESET_CONF_CPU_ECC_DERR_RST_CFG 0x4C74038
+
+#define mmPSOC_RESET_CONF_CPU_SW_RST_CFG 0x4C7403C
+
+#define mmPSOC_RESET_CONF_ARC_PRSTN_RST_CFG 0x4C74040
+
+#define mmPSOC_RESET_CONF_ARC_SOFT_RST_CFG 0x4C74044
+
+#define mmPSOC_RESET_CONF_ARC_FW_RST_CFG 0x4C74048
+
+#define mmPSOC_RESET_CONF_ARC_WD_RST_CFG 0x4C7404C
+
+#define mmPSOC_RESET_CONF_ARC_MNL_RST_CFG 0x4C74050
+
+#define mmPSOC_RESET_CONF_ARC_FLR_RST_CFG 0x4C74054
+
+#define mmPSOC_RESET_CONF_ARC_ECC_DERR_RST_CFG 0x4C74058
+
+#define mmPSOC_RESET_CONF_ARC_SW_RST_CFG 0x4C7405C
+
+#define mmPSOC_RESET_CONF_SIF_PRSTN_RST_CFG 0x4C74060
+
+#define mmPSOC_RESET_CONF_SIF_SOFT_RST_CFG 0x4C74064
+
+#define mmPSOC_RESET_CONF_SIF_FW_RST_CFG 0x4C74068
+
+#define mmPSOC_RESET_CONF_SIF_WD_RST_CFG 0x4C7406C
+
+#define mmPSOC_RESET_CONF_SIF_MNL_RST_CFG 0x4C74070
+
+#define mmPSOC_RESET_CONF_SIF_FLR_RST_CFG 0x4C74074
+
+#define mmPSOC_RESET_CONF_SIF_ECC_DERR_RST_CFG 0x4C74078
+
+#define mmPSOC_RESET_CONF_SIF_SW_RST_CFG 0x4C7407C
+
+#define mmPSOC_RESET_CONF_SRAM_PRSTN_RST_CFG 0x4C74080
+
+#define mmPSOC_RESET_CONF_SRAM_SOFT_RST_CFG 0x4C74084
+
+#define mmPSOC_RESET_CONF_SRAM_FW_RST_CFG 0x4C74088
+
+#define mmPSOC_RESET_CONF_SRAM_WD_RST_CFG 0x4C7408C
+
+#define mmPSOC_RESET_CONF_SRAM_MNL_RST_CFG 0x4C74090
+
+#define mmPSOC_RESET_CONF_SRAM_FLR_RST_CFG 0x4C74094
+
+#define mmPSOC_RESET_CONF_SRAM_ECC_DERR_RST_CFG 0x4C74098
+
+#define mmPSOC_RESET_CONF_SRAM_SW_RST_CFG 0x4C7409C
+
+#define mmPSOC_RESET_CONF_PCIE_CTRL_PRSTN_RST_CFG 0x4C740A0
+
+#define mmPSOC_RESET_CONF_PCIE_CTRL_SOFT_RST_CFG 0x4C740A4
+
+#define mmPSOC_RESET_CONF_PCIE_CTRL_FW_RST_CFG 0x4C740A8
+
+#define mmPSOC_RESET_CONF_PCIE_CTRL_WD_RST_CFG 0x4C740AC
+
+#define mmPSOC_RESET_CONF_PCIE_CTRL_MNL_RST_CFG 0x4C740B0
+
+#define mmPSOC_RESET_CONF_PCIE_CTRL_FLR_RST_CFG 0x4C740B4
+
+#define mmPSOC_RESET_CONF_PCIE_CTRL_ECC_DERR_RST_CFG 0x4C740B8
+
+#define mmPSOC_RESET_CONF_PCIE_CTRL_SW_RST_CFG 0x4C740BC
+
+#define mmPSOC_RESET_CONF_PCIE_PHY_CFG_PRSTN_RST_CFG 0x4C740C0
+
+#define mmPSOC_RESET_CONF_PCIE_PHY_CFG_SOFT_RST_CFG 0x4C740C4
+
+#define mmPSOC_RESET_CONF_PCIE_PHY_CFG_FW_RST_CFG 0x4C740C8
+
+#define mmPSOC_RESET_CONF_PCIE_PHY_CFG_WD_RST_CFG 0x4C740CC
+
+#define mmPSOC_RESET_CONF_PCIE_PHY_CFG_MNL_RST_CFG 0x4C740D0
+
+#define mmPSOC_RESET_CONF_PCIE_PHY_CFG_FLR_RST_CFG 0x4C740D4
+
+#define mmPSOC_RESET_CONF_PCIE_PHY_CFG_ECC_DERR_RST_CFG 0x4C740D8
+
+#define mmPSOC_RESET_CONF_PCIE_PHY_CFG_SW_RST_CFG 0x4C740DC
+
+#define mmPSOC_RESET_CONF_PCIE_IF_PRSTN_RST_CFG 0x4C740E0
+
+#define mmPSOC_RESET_CONF_PCIE_IF_SOFT_RST_CFG 0x4C740E4
+
+#define mmPSOC_RESET_CONF_PCIE_IF_FW_RST_CFG 0x4C740E8
+
+#define mmPSOC_RESET_CONF_PCIE_IF_WD_RST_CFG 0x4C740EC
+
+#define mmPSOC_RESET_CONF_PCIE_IF_MNL_RST_CFG 0x4C740F0
+
+#define mmPSOC_RESET_CONF_PCIE_IF_FLR_RST_CFG 0x4C740F4
+
+#define mmPSOC_RESET_CONF_PCIE_IF_ECC_DERR_RST_CFG 0x4C740F8
+
+#define mmPSOC_RESET_CONF_PCIE_IF_SW_RST_CFG 0x4C740FC
+
+#define mmPSOC_RESET_CONF_TPC_DIV_PRSTN_RST_CFG 0x4C74100
+
+#define mmPSOC_RESET_CONF_TPC_DIV_SOFT_RST_CFG 0x4C74104
+
+#define mmPSOC_RESET_CONF_TPC_DIV_FW_RST_CFG 0x4C74108
+
+#define mmPSOC_RESET_CONF_TPC_DIV_WD_RST_CFG 0x4C7410C
+
+#define mmPSOC_RESET_CONF_TPC_DIV_MNL_RST_CFG 0x4C74110
+
+#define mmPSOC_RESET_CONF_TPC_DIV_FLR_RST_CFG 0x4C74114
+
+#define mmPSOC_RESET_CONF_TPC_DIV_ECC_DERR_RST_CFG 0x4C74118
+
+#define mmPSOC_RESET_CONF_TPC_DIV_SW_RST_CFG 0x4C7411C
+
+#define mmPSOC_RESET_CONF_HBM_DIV_PRSTN_RST_CFG 0x4C74120
+
+#define mmPSOC_RESET_CONF_HBM_DIV_SOFT_RST_CFG 0x4C74124
+
+#define mmPSOC_RESET_CONF_HBM_DIV_FW_RST_CFG 0x4C74128
+
+#define mmPSOC_RESET_CONF_HBM_DIV_WD_RST_CFG 0x4C7412C
+
+#define mmPSOC_RESET_CONF_HBM_DIV_MNL_RST_CFG 0x4C74130
+
+#define mmPSOC_RESET_CONF_HBM_DIV_FLR_RST_CFG 0x4C74134
+
+#define mmPSOC_RESET_CONF_HBM_DIV_ECC_DERR_RST_CFG 0x4C74138
+
+#define mmPSOC_RESET_CONF_HBM_DIV_SW_RST_CFG 0x4C7413C
+
+#define mmPSOC_RESET_CONF_PMMU_PRSTN_RST_CFG 0x4C74140
+
+#define mmPSOC_RESET_CONF_PMMU_SOFT_RST_CFG 0x4C74144
+
+#define mmPSOC_RESET_CONF_PMMU_FW_RST_CFG 0x4C74148
+
+#define mmPSOC_RESET_CONF_PMMU_WD_RST_CFG 0x4C7414C
+
+#define mmPSOC_RESET_CONF_PMMU_MNL_RST_CFG 0x4C74150
+
+#define mmPSOC_RESET_CONF_PMMU_FLR_RST_CFG 0x4C74154
+
+#define mmPSOC_RESET_CONF_PMMU_ECC_DERR_RST_CFG 0x4C74158
+
+#define mmPSOC_RESET_CONF_PMMU_SW_RST_CFG 0x4C7415C
+
+#define mmPSOC_RESET_CONF_PM_PRSTN_RST_CFG 0x4C74160
+
+#define mmPSOC_RESET_CONF_PM_SOFT_RST_CFG 0x4C74164
+
+#define mmPSOC_RESET_CONF_PM_FW_RST_CFG 0x4C74168
+
+#define mmPSOC_RESET_CONF_PM_WD_RST_CFG 0x4C7416C
+
+#define mmPSOC_RESET_CONF_PM_MNL_RST_CFG 0x4C74170
+
+#define mmPSOC_RESET_CONF_PM_FLR_RST_CFG 0x4C74174
+
+#define mmPSOC_RESET_CONF_PM_ECC_DERR_RST_CFG 0x4C74178
+
+#define mmPSOC_RESET_CONF_PM_SW_RST_CFG 0x4C7417C
+
+#define mmPSOC_RESET_CONF_TS_PRSTN_RST_CFG 0x4C74180
+
+#define mmPSOC_RESET_CONF_TS_SOFT_RST_CFG 0x4C74184
+
+#define mmPSOC_RESET_CONF_TS_FW_RST_CFG 0x4C74188
+
+#define mmPSOC_RESET_CONF_TS_WD_RST_CFG 0x4C7418C
+
+#define mmPSOC_RESET_CONF_TS_MNL_RST_CFG 0x4C74190
+
+#define mmPSOC_RESET_CONF_TS_FLR_RST_CFG 0x4C74194
+
+#define mmPSOC_RESET_CONF_TS_ECC_DERR_RST_CFG 0x4C74198
+
+#define mmPSOC_RESET_CONF_TS_SW_RST_CFG 0x4C7419C
+
+#define mmPSOC_RESET_CONF_TS_IF_PRSTN_RST_CFG 0x4C741A0
+
+#define mmPSOC_RESET_CONF_TS_IF_SOFT_RST_CFG 0x4C741A4
+
+#define mmPSOC_RESET_CONF_TS_IF_FW_RST_CFG 0x4C741A8
+
+#define mmPSOC_RESET_CONF_TS_IF_WD_RST_CFG 0x4C741AC
+
+#define mmPSOC_RESET_CONF_TS_IF_MNL_RST_CFG 0x4C741B0
+
+#define mmPSOC_RESET_CONF_TS_IF_FLR_RST_CFG 0x4C741B4
+
+#define mmPSOC_RESET_CONF_TS_IF_ECC_DERR_RST_CFG 0x4C741B8
+
+#define mmPSOC_RESET_CONF_TS_IF_SW_RST_CFG 0x4C741BC
+
+#define mmPSOC_RESET_CONF_PLL_L_PRSTN_RST_CFG 0x4C741C0
+
+#define mmPSOC_RESET_CONF_PLL_L_SOFT_RST_CFG 0x4C741C4
+
+#define mmPSOC_RESET_CONF_PLL_L_FW_RST_CFG 0x4C741C8
+
+#define mmPSOC_RESET_CONF_PLL_L_WD_RST_CFG 0x4C741CC
+
+#define mmPSOC_RESET_CONF_PLL_L_MNL_RST_CFG 0x4C741D0
+
+#define mmPSOC_RESET_CONF_PLL_L_FLR_RST_CFG 0x4C741D4
+
+#define mmPSOC_RESET_CONF_PLL_L_ECC_DERR_RST_CFG 0x4C741D8
+
+#define mmPSOC_RESET_CONF_PLL_L_SW_RST_CFG 0x4C741DC
+
+#define mmPSOC_RESET_CONF_PLL_H_PRSTN_RST_CFG 0x4C741E0
+
+#define mmPSOC_RESET_CONF_PLL_H_SOFT_RST_CFG 0x4C741E4
+
+#define mmPSOC_RESET_CONF_PLL_H_FW_RST_CFG 0x4C741E8
+
+#define mmPSOC_RESET_CONF_PLL_H_WD_RST_CFG 0x4C741EC
+
+#define mmPSOC_RESET_CONF_PLL_H_MNL_RST_CFG 0x4C741F0
+
+#define mmPSOC_RESET_CONF_PLL_H_FLR_RST_CFG 0x4C741F4
+
+#define mmPSOC_RESET_CONF_PLL_H_ECC_DERR_RST_CFG 0x4C741F8
+
+#define mmPSOC_RESET_CONF_PLL_H_SW_RST_CFG 0x4C741FC
+
+#define mmPSOC_RESET_CONF_MME_EUS_PRSTN_RST_CFG 0x4C74200
+
+#define mmPSOC_RESET_CONF_MME_EUS_SOFT_RST_CFG 0x4C74204
+
+#define mmPSOC_RESET_CONF_MME_EUS_FW_RST_CFG 0x4C74208
+
+#define mmPSOC_RESET_CONF_MME_EUS_WD_RST_CFG 0x4C7420C
+
+#define mmPSOC_RESET_CONF_MME_EUS_MNL_RST_CFG 0x4C74210
+
+#define mmPSOC_RESET_CONF_MME_EUS_FLR_RST_CFG 0x4C74214
+
+#define mmPSOC_RESET_CONF_MME_EUS_ECC_DERR_RST_CFG 0x4C74218
+
+#define mmPSOC_RESET_CONF_MME_EUS_SW_RST_CFG 0x4C7421C
+
+#define mmPSOC_RESET_CONF_MSS_CLS_PRSTN_RST_CFG 0x4C74220
+
+#define mmPSOC_RESET_CONF_MSS_CLS_SOFT_RST_CFG 0x4C74224
+
+#define mmPSOC_RESET_CONF_MSS_CLS_FW_RST_CFG 0x4C74228
+
+#define mmPSOC_RESET_CONF_MSS_CLS_WD_RST_CFG 0x4C7422C
+
+#define mmPSOC_RESET_CONF_MSS_CLS_MNL_RST_CFG 0x4C74230
+
+#define mmPSOC_RESET_CONF_MSS_CLS_FLR_RST_CFG 0x4C74234
+
+#define mmPSOC_RESET_CONF_MSS_CLS_ECC_DERR_RST_CFG 0x4C74238
+
+#define mmPSOC_RESET_CONF_MSS_CLS_SW_RST_CFG 0x4C7423C
+
+#define mmPSOC_RESET_CONF_TPC_PRSTN_RST_CFG 0x4C74240
+
+#define mmPSOC_RESET_CONF_TPC_SOFT_RST_CFG 0x4C74244
+
+#define mmPSOC_RESET_CONF_TPC_FW_RST_CFG 0x4C74248
+
+#define mmPSOC_RESET_CONF_TPC_WD_RST_CFG 0x4C7424C
+
+#define mmPSOC_RESET_CONF_TPC_MNL_RST_CFG 0x4C74250
+
+#define mmPSOC_RESET_CONF_TPC_FLR_RST_CFG 0x4C74254
+
+#define mmPSOC_RESET_CONF_TPC_ECC_DERR_RST_CFG 0x4C74258
+
+#define mmPSOC_RESET_CONF_TPC_SW_RST_CFG 0x4C7425C
+
+#define mmPSOC_RESET_CONF_HIF_HMMU_PRSTN_RST_CFG 0x4C74260
+
+#define mmPSOC_RESET_CONF_HIF_HMMU_SOFT_RST_CFG 0x4C74264
+
+#define mmPSOC_RESET_CONF_HIF_HMMU_FW_RST_CFG 0x4C74268
+
+#define mmPSOC_RESET_CONF_HIF_HMMU_WD_RST_CFG 0x4C7426C
+
+#define mmPSOC_RESET_CONF_HIF_HMMU_MNL_RST_CFG 0x4C74270
+
+#define mmPSOC_RESET_CONF_HIF_HMMU_FLR_RST_CFG 0x4C74274
+
+#define mmPSOC_RESET_CONF_HIF_HMMU_ECC_DERR_RST_CFG 0x4C74278
+
+#define mmPSOC_RESET_CONF_HIF_HMMU_SW_RST_CFG 0x4C7427C
+
+#define mmPSOC_RESET_CONF_XBAR_PRSTN_RST_CFG 0x4C74280
+
+#define mmPSOC_RESET_CONF_XBAR_SOFT_RST_CFG 0x4C74284
+
+#define mmPSOC_RESET_CONF_XBAR_FW_RST_CFG 0x4C74288
+
+#define mmPSOC_RESET_CONF_XBAR_WD_RST_CFG 0x4C7428C
+
+#define mmPSOC_RESET_CONF_XBAR_MNL_RST_CFG 0x4C74290
+
+#define mmPSOC_RESET_CONF_XBAR_FLR_RST_CFG 0x4C74294
+
+#define mmPSOC_RESET_CONF_XBAR_ECC_DERR_RST_CFG 0x4C74298
+
+#define mmPSOC_RESET_CONF_XBAR_SW_RST_CFG 0x4C7429C
+
+#define mmPSOC_RESET_CONF_SFT_XFT_TFT_PRSTN_RST_CFG 0x4C742A0
+
+#define mmPSOC_RESET_CONF_SFT_XFT_TFT_SOFT_RST_CFG 0x4C742A4
+
+#define mmPSOC_RESET_CONF_SFT_XFT_TFT_FW_RST_CFG 0x4C742A8
+
+#define mmPSOC_RESET_CONF_SFT_XFT_TFT_WD_RST_CFG 0x4C742AC
+
+#define mmPSOC_RESET_CONF_SFT_XFT_TFT_MNL_RST_CFG 0x4C742B0
+
+#define mmPSOC_RESET_CONF_SFT_XFT_TFT_FLR_RST_CFG 0x4C742B4
+
+#define mmPSOC_RESET_CONF_SFT_XFT_TFT_ECC_DERR_RST_CFG 0x4C742B8
+
+#define mmPSOC_RESET_CONF_SFT_XFT_TFT_SW_RST_CFG 0x4C742BC
+
+#define mmPSOC_RESET_CONF_DDMA_PRSTN_RST_CFG 0x4C742C0
+
+#define mmPSOC_RESET_CONF_DDMA_SOFT_RST_CFG 0x4C742C4
+
+#define mmPSOC_RESET_CONF_DDMA_FW_RST_CFG 0x4C742C8
+
+#define mmPSOC_RESET_CONF_DDMA_WD_RST_CFG 0x4C742CC
+
+#define mmPSOC_RESET_CONF_DDMA_MNL_RST_CFG 0x4C742D0
+
+#define mmPSOC_RESET_CONF_DDMA_FLR_RST_CFG 0x4C742D4
+
+#define mmPSOC_RESET_CONF_DDMA_ECC_DERR_RST_CFG 0x4C742D8
+
+#define mmPSOC_RESET_CONF_DDMA_SW_RST_CFG 0x4C742DC
+
+#define mmPSOC_RESET_CONF_KDMA_PRSTN_RST_CFG 0x4C742E0
+
+#define mmPSOC_RESET_CONF_KDMA_SOFT_RST_CFG 0x4C742E4
+
+#define mmPSOC_RESET_CONF_KDMA_FW_RST_CFG 0x4C742E8
+
+#define mmPSOC_RESET_CONF_KDMA_WD_RST_CFG 0x4C742EC
+
+#define mmPSOC_RESET_CONF_KDMA_MNL_RST_CFG 0x4C742F0
+
+#define mmPSOC_RESET_CONF_KDMA_FLR_RST_CFG 0x4C742F4
+
+#define mmPSOC_RESET_CONF_KDMA_ECC_DERR_RST_CFG 0x4C742F8
+
+#define mmPSOC_RESET_CONF_KDMA_SW_RST_CFG 0x4C742FC
+
+#define mmPSOC_RESET_CONF_PDMA_PRSTN_RST_CFG 0x4C74300
+
+#define mmPSOC_RESET_CONF_PDMA_SOFT_RST_CFG 0x4C74304
+
+#define mmPSOC_RESET_CONF_PDMA_FW_RST_CFG 0x4C74308
+
+#define mmPSOC_RESET_CONF_PDMA_WD_RST_CFG 0x4C7430C
+
+#define mmPSOC_RESET_CONF_PDMA_MNL_RST_CFG 0x4C74310
+
+#define mmPSOC_RESET_CONF_PDMA_FLR_RST_CFG 0x4C74314
+
+#define mmPSOC_RESET_CONF_PDMA_ECC_DERR_RST_CFG 0x4C74318
+
+#define mmPSOC_RESET_CONF_PDMA_SW_RST_CFG 0x4C7431C
+
+#define mmPSOC_RESET_CONF_ARC_SS_PRSTN_RST_CFG 0x4C74320
+
+#define mmPSOC_RESET_CONF_ARC_SS_SOFT_RST_CFG 0x4C74324
+
+#define mmPSOC_RESET_CONF_ARC_SS_FW_RST_CFG 0x4C74328
+
+#define mmPSOC_RESET_CONF_ARC_SS_WD_RST_CFG 0x4C7432C
+
+#define mmPSOC_RESET_CONF_ARC_SS_MNL_RST_CFG 0x4C74330
+
+#define mmPSOC_RESET_CONF_ARC_SS_FLR_RST_CFG 0x4C74334
+
+#define mmPSOC_RESET_CONF_ARC_SS_ECC_DERR_RST_CFG 0x4C74338
+
+#define mmPSOC_RESET_CONF_ARC_SS_SW_RST_CFG 0x4C7433C
+
+#define mmPSOC_RESET_CONF_ROTATOR_PRSTN_RST_CFG 0x4C74340
+
+#define mmPSOC_RESET_CONF_ROTATOR_SOFT_RST_CFG 0x4C74344
+
+#define mmPSOC_RESET_CONF_ROTATOR_FW_RST_CFG 0x4C74348
+
+#define mmPSOC_RESET_CONF_ROTATOR_WD_RST_CFG 0x4C7434C
+
+#define mmPSOC_RESET_CONF_ROTATOR_MNL_RST_CFG 0x4C74350
+
+#define mmPSOC_RESET_CONF_ROTATOR_FLR_RST_CFG 0x4C74354
+
+#define mmPSOC_RESET_CONF_ROTATOR_ECC_DERR_RST_CFG 0x4C74358
+
+#define mmPSOC_RESET_CONF_ROTATOR_SW_RST_CFG 0x4C7435C
+
+#define mmPSOC_RESET_CONF_SM_PRSTN_RST_CFG 0x4C74360
+
+#define mmPSOC_RESET_CONF_SM_SOFT_RST_CFG 0x4C74364
+
+#define mmPSOC_RESET_CONF_SM_FW_RST_CFG 0x4C74368
+
+#define mmPSOC_RESET_CONF_SM_WD_RST_CFG 0x4C7436C
+
+#define mmPSOC_RESET_CONF_SM_MNL_RST_CFG 0x4C74370
+
+#define mmPSOC_RESET_CONF_SM_FLR_RST_CFG 0x4C74374
+
+#define mmPSOC_RESET_CONF_SM_ECC_DERR_RST_CFG 0x4C74378
+
+#define mmPSOC_RESET_CONF_SM_SW_RST_CFG 0x4C7437C
+
+#define mmPSOC_RESET_CONF_VIDEO_DEC_PRSTN_RST_CFG 0x4C74380
+
+#define mmPSOC_RESET_CONF_VIDEO_DEC_SOFT_RST_CFG 0x4C74384
+
+#define mmPSOC_RESET_CONF_VIDEO_DEC_FW_RST_CFG 0x4C74388
+
+#define mmPSOC_RESET_CONF_VIDEO_DEC_WD_RST_CFG 0x4C7438C
+
+#define mmPSOC_RESET_CONF_VIDEO_DEC_MNL_RST_CFG 0x4C74390
+
+#define mmPSOC_RESET_CONF_VIDEO_DEC_FLR_RST_CFG 0x4C74394
+
+#define mmPSOC_RESET_CONF_VIDEO_DEC_ECC_DERR_RST_CFG 0x4C74398
+
+#define mmPSOC_RESET_CONF_VIDEO_DEC_SW_RST_CFG 0x4C7439C
+
+#define mmPSOC_RESET_CONF_HBM_MC_PRSTN_RST_CFG 0x4C743A0
+
+#define mmPSOC_RESET_CONF_HBM_MC_SOFT_RST_CFG 0x4C743A4
+
+#define mmPSOC_RESET_CONF_HBM_MC_FW_RST_CFG 0x4C743A8
+
+#define mmPSOC_RESET_CONF_HBM_MC_WD_RST_CFG 0x4C743AC
+
+#define mmPSOC_RESET_CONF_HBM_MC_MNL_RST_CFG 0x4C743B0
+
+#define mmPSOC_RESET_CONF_HBM_MC_FLR_RST_CFG 0x4C743B4
+
+#define mmPSOC_RESET_CONF_HBM_MC_ECC_DERR_RST_CFG 0x4C743B8
+
+#define mmPSOC_RESET_CONF_HBM_MC_SW_RST_CFG 0x4C743BC
+
+#define mmPSOC_RESET_CONF_NIC_PRSTN_RST_CFG 0x4C743C0
+
+#define mmPSOC_RESET_CONF_NIC_SOFT_RST_CFG 0x4C743C4
+
+#define mmPSOC_RESET_CONF_NIC_FW_RST_CFG 0x4C743C8
+
+#define mmPSOC_RESET_CONF_NIC_WD_RST_CFG 0x4C743CC
+
+#define mmPSOC_RESET_CONF_NIC_MNL_RST_CFG 0x4C743D0
+
+#define mmPSOC_RESET_CONF_NIC_FLR_RST_CFG 0x4C743D4
+
+#define mmPSOC_RESET_CONF_NIC_ECC_DERR_RST_CFG 0x4C743D8
+
+#define mmPSOC_RESET_CONF_NIC_SW_RST_CFG 0x4C743DC
+
+#define mmPSOC_RESET_CONF_NIC_PRT_PRSTN_RST_CFG 0x4C743E0
+
+#define mmPSOC_RESET_CONF_NIC_PRT_SOFT_RST_CFG 0x4C743E4
+
+#define mmPSOC_RESET_CONF_NIC_PRT_FW_RST_CFG 0x4C743E8
+
+#define mmPSOC_RESET_CONF_NIC_PRT_WD_RST_CFG 0x4C743EC
+
+#define mmPSOC_RESET_CONF_NIC_PRT_MNL_RST_CFG 0x4C743F0
+
+#define mmPSOC_RESET_CONF_NIC_PRT_FLR_RST_CFG 0x4C743F4
+
+#define mmPSOC_RESET_CONF_NIC_PRT_ECC_DERR_RST_CFG 0x4C743F8
+
+#define mmPSOC_RESET_CONF_NIC_PRT_SW_RST_CFG 0x4C743FC
+
+#define mmPSOC_RESET_CONF_NIC_CH_PRSTN_RST_CFG 0x4C74400
+
+#define mmPSOC_RESET_CONF_NIC_CH_SOFT_RST_CFG 0x4C74404
+
+#define mmPSOC_RESET_CONF_NIC_CH_FW_RST_CFG 0x4C74408
+
+#define mmPSOC_RESET_CONF_NIC_CH_WD_RST_CFG 0x4C7440C
+
+#define mmPSOC_RESET_CONF_NIC_CH_MNL_RST_CFG 0x4C74410
+
+#define mmPSOC_RESET_CONF_NIC_CH_FLR_RST_CFG 0x4C74414
+
+#define mmPSOC_RESET_CONF_NIC_CH_ECC_DERR_RST_CFG 0x4C74418
+
+#define mmPSOC_RESET_CONF_NIC_CH_SW_RST_CFG 0x4C7441C
+
+#define mmPSOC_RESET_CONF_SOFT_RST 0x4C74800
+
+#define mmPSOC_RESET_CONF_SW_ALL_RST 0x4C74804
+
+#define mmPSOC_RESET_CONF_UNIT_RST_N 0x4C74808
+
+#define mmPSOC_RESET_CONF_PSOC_UNIT_RST 0x4C7480C
+
+#define mmPSOC_RESET_CONF_CPU_UNIT_RST 0x4C74810
+
+#define mmPSOC_RESET_CONF_ARC_UNIT_RST 0x4C74814
+
+#define mmPSOC_RESET_CONF_SIF_UNIT_RST 0x4C74818
+
+#define mmPSOC_RESET_CONF_SRAM_UNIT_RST 0x4C7481C
+
+#define mmPSOC_RESET_CONF_PCIE_CTRL_UNIT_RST 0x4C74820
+
+#define mmPSOC_RESET_CONF_PCIE_PHY_CFG_UNIT_RST 0x4C74824
+
+#define mmPSOC_RESET_CONF_PCIE_IF_UNIT_RST 0x4C74828
+
+#define mmPSOC_RESET_CONF_TPC_DIV_UNIT_RST 0x4C7482C
+
+#define mmPSOC_RESET_CONF_HBM_DIV_UNIT_RST 0x4C74830
+
+#define mmPSOC_RESET_CONF_PMMU_UNIT_RST 0x4C74834
+
+#define mmPSOC_RESET_CONF_PM_UNIT_RST 0x4C74838
+
+#define mmPSOC_RESET_CONF_TS_UNIT_RST 0x4C7483C
+
+#define mmPSOC_RESET_CONF_TS_IF_UNIT_RST 0x4C74840
+
+#define mmPSOC_RESET_CONF_PLL_L_UNIT_RST 0x4C74844
+
+#define mmPSOC_RESET_CONF_PLL_H_UNIT_RST 0x4C74848
+
+#define mmPSOC_RESET_CONF_MME_EUS_UNIT_RST 0x4C7484C
+
+#define mmPSOC_RESET_CONF_MSS_CLS_UNIT_RST 0x4C74850
+
+#define mmPSOC_RESET_CONF_TPC_UNIT_RST 0x4C74854
+
+#define mmPSOC_RESET_CONF_HIF_HMMU_UNIT_RST 0x4C74858
+
+#define mmPSOC_RESET_CONF_XBAR_UNIT_RST 0x4C7485C
+
+#define mmPSOC_RESET_CONF_SFT_XFT_TFT_UNIT_RST 0x4C74860
+
+#define mmPSOC_RESET_CONF_DDMA_UNIT_RST 0x4C74864
+
+#define mmPSOC_RESET_CONF_KDMA_UNIT_RST 0x4C74868
+
+#define mmPSOC_RESET_CONF_PDMA_UNIT_RST 0x4C7486C
+
+#define mmPSOC_RESET_CONF_ARC_SS_UNIT_RST 0x4C74870
+
+#define mmPSOC_RESET_CONF_ROTATOR_UNIT_RST 0x4C74874
+
+#define mmPSOC_RESET_CONF_SM_UNIT_RST 0x4C74878
+
+#define mmPSOC_RESET_CONF_VIDEO_DEC_UNIT_RST 0x4C7487C
+
+#define mmPSOC_RESET_CONF_HBM_MC_UNIT_RST 0x4C74880
+
+#define mmPSOC_RESET_CONF_NIC_UNIT_RST 0x4C74884
+
+#define mmPSOC_RESET_CONF_NIC_PRT_UNIT_RST 0x4C74888
+
+#define mmPSOC_RESET_CONF_NIC_CH_UNIT_RST 0x4C7488C
+
+#define mmPSOC_RESET_CONF_PSOC_0_CLK_RST_CTRL 0x4C74B00
+
+#define mmPSOC_RESET_CONF_CPU_0_CLK_RST_CTRL 0x4C74B04
+
+#define mmPSOC_RESET_CONF_ARC_0_CLK_RST_CTRL 0x4C74B08
+
+#define mmPSOC_RESET_CONF_ARC_1_CLK_RST_CTRL 0x4C74B0C
+
+#define mmPSOC_RESET_CONF_SIF_0_CLK_RST_CTRL 0x4C74B10
+
+#define mmPSOC_RESET_CONF_SIF_1_CLK_RST_CTRL 0x4C74B14
+
+#define mmPSOC_RESET_CONF_SIF_2_CLK_RST_CTRL 0x4C74B18
+
+#define mmPSOC_RESET_CONF_SIF_3_CLK_RST_CTRL 0x4C74B1C
+
+#define mmPSOC_RESET_CONF_SRAM_0_CLK_RST_CTRL 0x4C74B20
+
+#define mmPSOC_RESET_CONF_SRAM_1_CLK_RST_CTRL 0x4C74B24
+
+#define mmPSOC_RESET_CONF_SRAM_2_CLK_RST_CTRL 0x4C74B28
+
+#define mmPSOC_RESET_CONF_SRAM_3_CLK_RST_CTRL 0x4C74B2C
+
+#define mmPSOC_RESET_CONF_PCIE_CTRL_0_CLK_RST_CTRL 0x4C74B30
+
+#define mmPSOC_RESET_CONF_PCIE_PHY_CFG_0_CLK_RST_CTRL 0x4C74B34
+
+#define mmPSOC_RESET_CONF_PCIE_IF_0_CLK_RST_CTRL 0x4C74B38
+
+#define mmPSOC_RESET_CONF_TPC_DIV_0_CLK_RST_CTRL 0x4C74B3C
+
+#define mmPSOC_RESET_CONF_TPC_DIV_1_CLK_RST_CTRL 0x4C74B40
+
+#define mmPSOC_RESET_CONF_TPC_DIV_2_CLK_RST_CTRL 0x4C74B44
+
+#define mmPSOC_RESET_CONF_TPC_DIV_3_CLK_RST_CTRL 0x4C74B48
+
+#define mmPSOC_RESET_CONF_TPC_DIV_4_CLK_RST_CTRL 0x4C74B4C
+
+#define mmPSOC_RESET_CONF_HBM_DIV_0_CLK_RST_CTRL 0x4C74B50
+
+#define mmPSOC_RESET_CONF_HBM_DIV_1_CLK_RST_CTRL 0x4C74B54
+
+#define mmPSOC_RESET_CONF_HBM_DIV_2_CLK_RST_CTRL 0x4C74B58
+
+#define mmPSOC_RESET_CONF_HBM_DIV_3_CLK_RST_CTRL 0x4C74B5C
+
+#define mmPSOC_RESET_CONF_HBM_DIV_4_CLK_RST_CTRL 0x4C74B60
+
+#define mmPSOC_RESET_CONF_HBM_DIV_5_CLK_RST_CTRL 0x4C74B64
+
+#define mmPSOC_RESET_CONF_PMMU_0_CLK_RST_CTRL 0x4C74B68
+
+#define mmPSOC_RESET_CONF_PM_0_CLK_RST_CTRL 0x4C74B6C
+
+#define mmPSOC_RESET_CONF_PM_1_CLK_RST_CTRL 0x4C74B70
+
+#define mmPSOC_RESET_CONF_PM_2_CLK_RST_CTRL 0x4C74B74
+
+#define mmPSOC_RESET_CONF_PM_3_CLK_RST_CTRL 0x4C74B78
+
+#define mmPSOC_RESET_CONF_TS_0_CLK_RST_CTRL 0x4C74B7C
+
+#define mmPSOC_RESET_CONF_TS_1_CLK_RST_CTRL 0x4C74B80
+
+#define mmPSOC_RESET_CONF_TS_2_CLK_RST_CTRL 0x4C74B84
+
+#define mmPSOC_RESET_CONF_TS_3_CLK_RST_CTRL 0x4C74B88
+
+#define mmPSOC_RESET_CONF_TS_IF_0_CLK_RST_CTRL 0x4C74B8C
+
+#define mmPSOC_RESET_CONF_TS_IF_1_CLK_RST_CTRL 0x4C74B90
+
+#define mmPSOC_RESET_CONF_TS_IF_2_CLK_RST_CTRL 0x4C74B94
+
+#define mmPSOC_RESET_CONF_TS_IF_3_CLK_RST_CTRL 0x4C74B98
+
+#define mmPSOC_RESET_CONF_PLL_L_0_CLK_RST_CTRL 0x4C74B9C
+
+#define mmPSOC_RESET_CONF_PLL_L_1_CLK_RST_CTRL 0x4C74BA0
+
+#define mmPSOC_RESET_CONF_PLL_L_2_CLK_RST_CTRL 0x4C74BA4
+
+#define mmPSOC_RESET_CONF_PLL_L_3_CLK_RST_CTRL 0x4C74BA8
+
+#define mmPSOC_RESET_CONF_PLL_L_4_CLK_RST_CTRL 0x4C74BAC
+
+#define mmPSOC_RESET_CONF_PLL_L_5_CLK_RST_CTRL 0x4C74BB0
+
+#define mmPSOC_RESET_CONF_PLL_L_6_CLK_RST_CTRL 0x4C74BB4
+
+#define mmPSOC_RESET_CONF_PLL_L_7_CLK_RST_CTRL 0x4C74BB8
+
+#define mmPSOC_RESET_CONF_PLL_L_8_CLK_RST_CTRL 0x4C74BBC
+
+#define mmPSOC_RESET_CONF_PLL_L_9_CLK_RST_CTRL 0x4C74BC0
+
+#define mmPSOC_RESET_CONF_PLL_L_10_CLK_RST_CTRL 0x4C74BC4
+
+#define mmPSOC_RESET_CONF_PLL_L_11_CLK_RST_CTRL 0x4C74BC8
+
+#define mmPSOC_RESET_CONF_PLL_L_12_CLK_RST_CTRL 0x4C74BCC
+
+#define mmPSOC_RESET_CONF_PLL_L_13_CLK_RST_CTRL 0x4C74BD0
+
+#define mmPSOC_RESET_CONF_PLL_L_14_CLK_RST_CTRL 0x4C74BD4
+
+#define mmPSOC_RESET_CONF_PLL_L_15_CLK_RST_CTRL 0x4C74BD8
+
+#define mmPSOC_RESET_CONF_PLL_L_16_CLK_RST_CTRL 0x4C74BDC
+
+#define mmPSOC_RESET_CONF_PLL_L_17_CLK_RST_CTRL 0x4C74BE0
+
+#define mmPSOC_RESET_CONF_PLL_L_18_CLK_RST_CTRL 0x4C74BE4
+
+#define mmPSOC_RESET_CONF_PLL_L_19_CLK_RST_CTRL 0x4C74BE8
+
+#define mmPSOC_RESET_CONF_PLL_L_20_CLK_RST_CTRL 0x4C74BEC
+
+#define mmPSOC_RESET_CONF_PLL_L_21_CLK_RST_CTRL 0x4C74BF0
+
+#define mmPSOC_RESET_CONF_PLL_L_22_CLK_RST_CTRL 0x4C74BF4
+
+#define mmPSOC_RESET_CONF_PLL_L_23_CLK_RST_CTRL 0x4C74BF8
+
+#define mmPSOC_RESET_CONF_PLL_L_24_CLK_RST_CTRL 0x4C74BFC
+
+#define mmPSOC_RESET_CONF_PLL_L_25_CLK_RST_CTRL 0x4C74C00
+
+#define mmPSOC_RESET_CONF_PLL_L_26_CLK_RST_CTRL 0x4C74C04
+
+#define mmPSOC_RESET_CONF_PLL_L_27_CLK_RST_CTRL 0x4C74C08
+
+#define mmPSOC_RESET_CONF_PLL_L_28_CLK_RST_CTRL 0x4C74C0C
+
+#define mmPSOC_RESET_CONF_PLL_L_29_CLK_RST_CTRL 0x4C74C10
+
+#define mmPSOC_RESET_CONF_PLL_L_30_CLK_RST_CTRL 0x4C74C14
+
+#define mmPSOC_RESET_CONF_PLL_L_31_CLK_RST_CTRL 0x4C74C18
+
+#define mmPSOC_RESET_CONF_PLL_H_0_CLK_RST_CTRL 0x4C74C1C
+
+#define mmPSOC_RESET_CONF_PLL_H_1_CLK_RST_CTRL 0x4C74C20
+
+#define mmPSOC_RESET_CONF_MME_EUS_0_CLK_RST_CTRL 0x4C74C24
+
+#define mmPSOC_RESET_CONF_MME_EUS_1_CLK_RST_CTRL 0x4C74C28
+
+#define mmPSOC_RESET_CONF_MME_EUS_2_CLK_RST_CTRL 0x4C74C2C
+
+#define mmPSOC_RESET_CONF_MME_EUS_3_CLK_RST_CTRL 0x4C74C30
+
+#define mmPSOC_RESET_CONF_MSS_CLS_0_CLK_RST_CTRL 0x4C74C34
+
+#define mmPSOC_RESET_CONF_MSS_CLS_1_CLK_RST_CTRL 0x4C74C38
+
+#define mmPSOC_RESET_CONF_MSS_CLS_2_CLK_RST_CTRL 0x4C74C3C
+
+#define mmPSOC_RESET_CONF_MSS_CLS_3_CLK_RST_CTRL 0x4C74C40
+
+#define mmPSOC_RESET_CONF_TPC_0_CLK_RST_CTRL 0x4C74C44
+
+#define mmPSOC_RESET_CONF_TPC_1_CLK_RST_CTRL 0x4C74C48
+
+#define mmPSOC_RESET_CONF_TPC_2_CLK_RST_CTRL 0x4C74C4C
+
+#define mmPSOC_RESET_CONF_TPC_3_CLK_RST_CTRL 0x4C74C50
+
+#define mmPSOC_RESET_CONF_TPC_4_CLK_RST_CTRL 0x4C74C54
+
+#define mmPSOC_RESET_CONF_TPC_5_CLK_RST_CTRL 0x4C74C58
+
+#define mmPSOC_RESET_CONF_TPC_6_CLK_RST_CTRL 0x4C74C5C
+
+#define mmPSOC_RESET_CONF_TPC_7_CLK_RST_CTRL 0x4C74C60
+
+#define mmPSOC_RESET_CONF_TPC_8_CLK_RST_CTRL 0x4C74C64
+
+#define mmPSOC_RESET_CONF_TPC_9_CLK_RST_CTRL 0x4C74C68
+
+#define mmPSOC_RESET_CONF_TPC_10_CLK_RST_CTRL 0x4C74C6C
+
+#define mmPSOC_RESET_CONF_TPC_11_CLK_RST_CTRL 0x4C74C70
+
+#define mmPSOC_RESET_CONF_TPC_12_CLK_RST_CTRL 0x4C74C74
+
+#define mmPSOC_RESET_CONF_TPC_13_CLK_RST_CTRL 0x4C74C78
+
+#define mmPSOC_RESET_CONF_TPC_14_CLK_RST_CTRL 0x4C74C7C
+
+#define mmPSOC_RESET_CONF_TPC_15_CLK_RST_CTRL 0x4C74C80
+
+#define mmPSOC_RESET_CONF_TPC_16_CLK_RST_CTRL 0x4C74C84
+
+#define mmPSOC_RESET_CONF_TPC_17_CLK_RST_CTRL 0x4C74C88
+
+#define mmPSOC_RESET_CONF_TPC_18_CLK_RST_CTRL 0x4C74C8C
+
+#define mmPSOC_RESET_CONF_TPC_19_CLK_RST_CTRL 0x4C74C90
+
+#define mmPSOC_RESET_CONF_TPC_20_CLK_RST_CTRL 0x4C74C94
+
+#define mmPSOC_RESET_CONF_TPC_21_CLK_RST_CTRL 0x4C74C98
+
+#define mmPSOC_RESET_CONF_TPC_22_CLK_RST_CTRL 0x4C74C9C
+
+#define mmPSOC_RESET_CONF_TPC_23_CLK_RST_CTRL 0x4C74CA0
+
+#define mmPSOC_RESET_CONF_TPC_24_CLK_RST_CTRL 0x4C74CA4
+
+#define mmPSOC_RESET_CONF_HIF_HMMU_0_CLK_RST_CTRL 0x4C74CA8
+
+#define mmPSOC_RESET_CONF_HIF_HMMU_1_CLK_RST_CTRL 0x4C74CAC
+
+#define mmPSOC_RESET_CONF_HIF_HMMU_2_CLK_RST_CTRL 0x4C74CB0
+
+#define mmPSOC_RESET_CONF_HIF_HMMU_3_CLK_RST_CTRL 0x4C74CB4
+
+#define mmPSOC_RESET_CONF_XBAR_0_CLK_RST_CTRL 0x4C74CB8
+
+#define mmPSOC_RESET_CONF_XBAR_1_CLK_RST_CTRL 0x4C74CBC
+
+#define mmPSOC_RESET_CONF_XBAR_2_CLK_RST_CTRL 0x4C74CC0
+
+#define mmPSOC_RESET_CONF_XBAR_3_CLK_RST_CTRL 0x4C74CC4
+
+#define mmPSOC_RESET_CONF_SFT_XFT_TFT_0_CLK_RST_CTRL 0x4C74CC8
+
+#define mmPSOC_RESET_CONF_SFT_XFT_TFT_1_CLK_RST_CTRL 0x4C74CCC
+
+#define mmPSOC_RESET_CONF_SFT_XFT_TFT_2_CLK_RST_CTRL 0x4C74CD0
+
+#define mmPSOC_RESET_CONF_SFT_XFT_TFT_3_CLK_RST_CTRL 0x4C74CD4
+
+#define mmPSOC_RESET_CONF_DDMA_0_CLK_RST_CTRL 0x4C74CD8
+
+#define mmPSOC_RESET_CONF_DDMA_1_CLK_RST_CTRL 0x4C74CDC
+
+#define mmPSOC_RESET_CONF_DDMA_2_CLK_RST_CTRL 0x4C74CE0
+
+#define mmPSOC_RESET_CONF_DDMA_3_CLK_RST_CTRL 0x4C74CE4
+
+#define mmPSOC_RESET_CONF_DDMA_4_CLK_RST_CTRL 0x4C74CE8
+
+#define mmPSOC_RESET_CONF_DDMA_5_CLK_RST_CTRL 0x4C74CEC
+
+#define mmPSOC_RESET_CONF_DDMA_6_CLK_RST_CTRL 0x4C74CF0
+
+#define mmPSOC_RESET_CONF_DDMA_7_CLK_RST_CTRL 0x4C74CF4
+
+#define mmPSOC_RESET_CONF_KDMA_0_CLK_RST_CTRL 0x4C74CF8
+
+#define mmPSOC_RESET_CONF_PDMA_0_CLK_RST_CTRL 0x4C74CFC
+
+#define mmPSOC_RESET_CONF_PDMA_1_CLK_RST_CTRL 0x4C74D00
+
+#define mmPSOC_RESET_CONF_ARC_SS_0_CLK_RST_CTRL 0x4C74D04
+
+#define mmPSOC_RESET_CONF_ARC_SS_1_CLK_RST_CTRL 0x4C74D08
+
+#define mmPSOC_RESET_CONF_ARC_SS_2_CLK_RST_CTRL 0x4C74D0C
+
+#define mmPSOC_RESET_CONF_ARC_SS_3_CLK_RST_CTRL 0x4C74D10
+
+#define mmPSOC_RESET_CONF_ARC_SS_4_CLK_RST_CTRL 0x4C74D14
+
+#define mmPSOC_RESET_CONF_ROTATOR_0_CLK_RST_CTRL 0x4C74D18
+
+#define mmPSOC_RESET_CONF_ROTATOR_1_CLK_RST_CTRL 0x4C74D1C
+
+#define mmPSOC_RESET_CONF_SM_0_CLK_RST_CTRL 0x4C74D20
+
+#define mmPSOC_RESET_CONF_SM_1_CLK_RST_CTRL 0x4C74D24
+
+#define mmPSOC_RESET_CONF_SM_2_CLK_RST_CTRL 0x4C74D28
+
+#define mmPSOC_RESET_CONF_SM_3_CLK_RST_CTRL 0x4C74D2C
+
+#define mmPSOC_RESET_CONF_VIDEO_DEC_0_CLK_RST_CTRL 0x4C74D30
+
+#define mmPSOC_RESET_CONF_VIDEO_DEC_1_CLK_RST_CTRL 0x4C74D34
+
+#define mmPSOC_RESET_CONF_VIDEO_DEC_2_CLK_RST_CTRL 0x4C74D38
+
+#define mmPSOC_RESET_CONF_VIDEO_DEC_3_CLK_RST_CTRL 0x4C74D3C
+
+#define mmPSOC_RESET_CONF_VIDEO_DEC_4_CLK_RST_CTRL 0x4C74D40
+
+#define mmPSOC_RESET_CONF_VIDEO_DEC_5_CLK_RST_CTRL 0x4C74D44
+
+#define mmPSOC_RESET_CONF_VIDEO_DEC_6_CLK_RST_CTRL 0x4C74D48
+
+#define mmPSOC_RESET_CONF_VIDEO_DEC_7_CLK_RST_CTRL 0x4C74D4C
+
+#define mmPSOC_RESET_CONF_VIDEO_DEC_8_CLK_RST_CTRL 0x4C74D50
+
+#define mmPSOC_RESET_CONF_VIDEO_DEC_9_CLK_RST_CTRL 0x4C74D54
+
+#define mmPSOC_RESET_CONF_HBM_MC_0_CLK_RST_CTRL 0x4C74D58
+
+#define mmPSOC_RESET_CONF_HBM_MC_1_CLK_RST_CTRL 0x4C74D5C
+
+#define mmPSOC_RESET_CONF_HBM_MC_2_CLK_RST_CTRL 0x4C74D60
+
+#define mmPSOC_RESET_CONF_HBM_MC_3_CLK_RST_CTRL 0x4C74D64
+
+#define mmPSOC_RESET_CONF_HBM_MC_4_CLK_RST_CTRL 0x4C74D68
+
+#define mmPSOC_RESET_CONF_HBM_MC_5_CLK_RST_CTRL 0x4C74D6C
+
+#define mmPSOC_RESET_CONF_NIC_0_CLK_RST_CTRL 0x4C74D70
+
+#define mmPSOC_RESET_CONF_NIC_1_CLK_RST_CTRL 0x4C74D74
+
+#define mmPSOC_RESET_CONF_NIC_2_CLK_RST_CTRL 0x4C74D78
+
+#define mmPSOC_RESET_CONF_NIC_3_CLK_RST_CTRL 0x4C74D7C
+
+#define mmPSOC_RESET_CONF_NIC_4_CLK_RST_CTRL 0x4C74D80
+
+#define mmPSOC_RESET_CONF_NIC_5_CLK_RST_CTRL 0x4C74D84
+
+#define mmPSOC_RESET_CONF_NIC_6_CLK_RST_CTRL 0x4C74D88
+
+#define mmPSOC_RESET_CONF_NIC_7_CLK_RST_CTRL 0x4C74D8C
+
+#define mmPSOC_RESET_CONF_NIC_8_CLK_RST_CTRL 0x4C74D90
+
+#define mmPSOC_RESET_CONF_NIC_9_CLK_RST_CTRL 0x4C74D94
+
+#define mmPSOC_RESET_CONF_NIC_10_CLK_RST_CTRL 0x4C74D98
+
+#define mmPSOC_RESET_CONF_NIC_11_CLK_RST_CTRL 0x4C74D9C
+
+#define mmPSOC_RESET_CONF_NIC_PRT_0_CLK_RST_CTRL 0x4C74DA0
+
+#define mmPSOC_RESET_CONF_NIC_PRT_1_CLK_RST_CTRL 0x4C74DA4
+
+#define mmPSOC_RESET_CONF_NIC_PRT_2_CLK_RST_CTRL 0x4C74DA8
+
+#define mmPSOC_RESET_CONF_NIC_PRT_3_CLK_RST_CTRL 0x4C74DAC
+
+#define mmPSOC_RESET_CONF_NIC_PRT_4_CLK_RST_CTRL 0x4C74DB0
+
+#define mmPSOC_RESET_CONF_NIC_PRT_5_CLK_RST_CTRL 0x4C74DB4
+
+#define mmPSOC_RESET_CONF_NIC_PRT_6_CLK_RST_CTRL 0x4C74DB8
+
+#define mmPSOC_RESET_CONF_NIC_PRT_7_CLK_RST_CTRL 0x4C74DBC
+
+#define mmPSOC_RESET_CONF_NIC_PRT_8_CLK_RST_CTRL 0x4C74DC0
+
+#define mmPSOC_RESET_CONF_NIC_PRT_9_CLK_RST_CTRL 0x4C74DC4
+
+#define mmPSOC_RESET_CONF_NIC_PRT_10_CLK_RST_CTRL 0x4C74DC8
+
+#define mmPSOC_RESET_CONF_NIC_PRT_11_CLK_RST_CTRL 0x4C74DCC
+
+#define mmPSOC_RESET_CONF_NIC_CH_0_CLK_RST_CTRL 0x4C74DD0
+
+#define mmPSOC_RESET_CONF_NIC_CH_1_CLK_RST_CTRL 0x4C74DD4
+
+#define mmPSOC_RESET_CONF_NIC_CH_2_CLK_RST_CTRL 0x4C74DD8
+
+#endif /* ASIC_REG_PSOC_RESET_CONF_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/psoc_timestamp_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/psoc_timestamp_regs.h
new file mode 100644
index 000000000000..699becc28887
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/psoc_timestamp_regs.h
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PSOC_TIMESTAMP_REGS_H_
+#define ASIC_REG_PSOC_TIMESTAMP_REGS_H_
+
+/*
+ *****************************************
+ *   PSOC_TIMESTAMP
+ *   (Prototype: TIMESTAMP)
+ *****************************************
+ */
+
+#define mmPSOC_TIMESTAMP_CNTCR 0x4C49000
+
+#define mmPSOC_TIMESTAMP_CNTSR 0x4C49004
+
+#define mmPSOC_TIMESTAMP_CNTCVL 0x4C49008
+
+#define mmPSOC_TIMESTAMP_CNTCVU 0x4C4900C
+
+#define mmPSOC_TIMESTAMP_CNTFID0 0x4C49020
+
+#define mmPSOC_TIMESTAMP_PIDR4 0x4C49FD0
+
+#define mmPSOC_TIMESTAMP_PIDR5 0x4C49FD4
+
+#define mmPSOC_TIMESTAMP_PIDR6 0x4C49FD8
+
+#define mmPSOC_TIMESTAMP_PIDR7 0x4C49FDC
+
+#define mmPSOC_TIMESTAMP_PIDR0 0x4C49FE0
+
+#define mmPSOC_TIMESTAMP_PIDR1 0x4C49FE4
+
+#define mmPSOC_TIMESTAMP_PIDR2 0x4C49FE8
+
+#define mmPSOC_TIMESTAMP_PIDR3 0x4C49FEC
+
+#define mmPSOC_TIMESTAMP_CIDR0 0x4C49FF0
+
+#define mmPSOC_TIMESTAMP_CIDR1 0x4C49FF4
+
+#define mmPSOC_TIMESTAMP_CIDR2 0x4C49FF8
+
+#define mmPSOC_TIMESTAMP_CIDR3 0x4C49FFC
+
+#endif /* ASIC_REG_PSOC_TIMESTAMP_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/rot0_desc_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/rot0_desc_regs.h
new file mode 100644
index 000000000000..79320320ebcb
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/rot0_desc_regs.h
@@ -0,0 +1,155 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_ROT0_DESC_REGS_H_
+#define ASIC_REG_ROT0_DESC_REGS_H_
+
+/*
+ *****************************************
+ *   ROT0_DESC
+ *   (Prototype: ROT_DESC)
+ *****************************************
+ */
+
+#define mmROT0_DESC_CONTEXT_ID 0x4E0B100
+
+#define mmROT0_DESC_IN_IMG_START_ADDR_L 0x4E0B104
+
+#define mmROT0_DESC_IN_IMG_START_ADDR_H 0x4E0B108
+
+#define mmROT0_DESC_OUT_IMG_START_ADDR_L 0x4E0B10C
+
+#define mmROT0_DESC_OUT_IMG_START_ADDR_H 0x4E0B110
+
+#define mmROT0_DESC_CFG 0x4E0B114
+
+#define mmROT0_DESC_IM_READ_SLOPE 0x4E0B118
+
+#define mmROT0_DESC_SIN_D 0x4E0B11C
+
+#define mmROT0_DESC_COS_D 0x4E0B120
+
+#define mmROT0_DESC_IN_IMG 0x4E0B124
+
+#define mmROT0_DESC_IN_STRIDE 0x4E0B128
+
+#define mmROT0_DESC_IN_STRIPE 0x4E0B12C
+
+#define mmROT0_DESC_IN_CENTER 0x4E0B130
+
+#define mmROT0_DESC_OUT_IMG 0x4E0B134
+
+#define mmROT0_DESC_OUT_STRIDE 0x4E0B138
+
+#define mmROT0_DESC_OUT_STRIPE 0x4E0B13C
+
+#define mmROT0_DESC_OUT_CENTER 0x4E0B140
+
+#define mmROT0_DESC_BACKGROUND 0x4E0B144
+
+#define mmROT0_DESC_CPL_MSG_EN 0x4E0B148
+
+#define mmROT0_DESC_IDLE_STATE 0x4E0B14C
+
+#define mmROT0_DESC_CPL_MSG_ADDR 0x4E0B150
+
+#define mmROT0_DESC_CPL_MSG_DATA 0x4E0B154
+
+#define mmROT0_DESC_CPL_MSG_AWUSER 0x4E0B158
+
+#define mmROT0_DESC_X_I_START_OFFSET 0x4E0B15C
+
+#define mmROT0_DESC_X_I_START_OFFSET_FLIP 0x4E0B160
+
+#define mmROT0_DESC_X_I_FIRST 0x4E0B164
+
+#define mmROT0_DESC_Y_I_FIRST 0x4E0B168
+
+#define mmROT0_DESC_Y_I 0x4E0B16C
+
+#define mmROT0_DESC_OUT_STRIPE_SIZE 0x4E0B170
+
+#define mmROT0_DESC_RSB_CFG_0 0x4E0B174
+
+#define mmROT0_DESC_RSB_PAD_VAL 0x4E0B178
+
+#define mmROT0_DESC_HBW_ARUSER_HI 0x4E0B17C
+
+#define mmROT0_DESC_HBW_ARUSER_LO 0x4E0B180
+
+#define mmROT0_DESC_HBW_AWUSER_HI 0x4E0B184
+
+#define mmROT0_DESC_HBW_AWUSER_LO 0x4E0B188
+
+#define mmROT0_DESC_OWM_CFG 0x4E0B18C
+
+#define mmROT0_DESC_CTRL_CFG 0x4E0B190
+
+#define mmROT0_DESC_PIXEL_PAD 0x4E0B194
+
+#define mmROT0_DESC_PREC_SHIFT 0x4E0B198
+
+#define mmROT0_DESC_MAX_VAL 0x4E0B19C
+
+#define mmROT0_DESC_A0_M11 0x4E0B1A0
+
+#define mmROT0_DESC_A1_M12 0x4E0B1A4
+
+#define mmROT0_DESC_A2 0x4E0B1A8
+
+#define mmROT0_DESC_B0_M21 0x4E0B1AC
+
+#define mmROT0_DESC_B1_M22 0x4E0B1B0
+
+#define mmROT0_DESC_B2 0x4E0B1B4
+
+#define mmROT0_DESC_C0 0x4E0B1B8
+
+#define mmROT0_DESC_C1 0x4E0B1BC
+
+#define mmROT0_DESC_C2 0x4E0B1C0
+
+#define mmROT0_DESC_D0 0x4E0B1C4
+
+#define mmROT0_DESC_D1 0x4E0B1C8
+
+#define mmROT0_DESC_D2 0x4E0B1CC
+
+#define mmROT0_DESC_INV_PROC_SIZE_M_1 0x4E0B1D0
+
+#define mmROT0_DESC_MESH_IMG_START_ADDR_L 0x4E0B1D4
+
+#define mmROT0_DESC_MESH_IMG_START_ADDR_H 0x4E0B1D8
+
+#define mmROT0_DESC_MESH_IMG 0x4E0B1DC
+
+#define mmROT0_DESC_MESH_STRIDE 0x4E0B1E0
+
+#define mmROT0_DESC_MESH_STRIPE 0x4E0B1E4
+
+#define mmROT0_DESC_MESH_CTRL 0x4E0B1E8
+
+#define mmROT0_DESC_MESH_GH 0x4E0B1EC
+
+#define mmROT0_DESC_MESH_GV 0x4E0B1F0
+
+#define mmROT0_DESC_MRSB_CFG_0 0x4E0B1F4
+
+#define mmROT0_DESC_MRSB_PAD_VAL 0x4E0B1F8
+
+#define mmROT0_DESC_BUF_CFG 0x4E0B1FC
+
+#define mmROT0_DESC_CID_OFFSET 0x4E0B200
+
+#define mmROT0_DESC_PUSH_DESC 0x4E0B204
+
+#endif /* ASIC_REG_ROT0_DESC_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/rot0_masks.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/rot0_masks.h
new file mode 100644
index 000000000000..f2e739ede3d9
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/rot0_masks.h
@@ -0,0 +1,313 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_ROT0_MASKS_H_
+#define ASIC_REG_ROT0_MASKS_H_
+
+/*
+ *****************************************
+ *   ROT0
+ *   (Prototype: ROTATOR)
+ *****************************************
+ */
+
+/* ROT0_KMD_MODE */
+#define ROT0_KMD_MODE_EN_SHIFT 0
+#define ROT0_KMD_MODE_EN_MASK 0x1
+
+/* ROT0_CPL_QUEUE_EN */
+#define ROT0_CPL_QUEUE_EN_Q_EN_SHIFT 0
+#define ROT0_CPL_QUEUE_EN_Q_EN_MASK 0x1
+
+/* ROT0_CPL_QUEUE_ADDR_L */
+#define ROT0_CPL_QUEUE_ADDR_L_VAL_SHIFT 0
+#define ROT0_CPL_QUEUE_ADDR_L_VAL_MASK 0xFFFFFFFF
+
+/* ROT0_CPL_QUEUE_ADDR_H */
+#define ROT0_CPL_QUEUE_ADDR_H_VAL_SHIFT 0
+#define ROT0_CPL_QUEUE_ADDR_H_VAL_MASK 0xFFFFFFFF
+
+/* ROT0_CPL_QUEUE_DATA */
+#define ROT0_CPL_QUEUE_DATA_VAL_SHIFT 0
+#define ROT0_CPL_QUEUE_DATA_VAL_MASK 0xFFFFFFFF
+
+/* ROT0_CPL_QUEUE_AWUSER */
+#define ROT0_CPL_QUEUE_AWUSER_VAL_SHIFT 0
+#define ROT0_CPL_QUEUE_AWUSER_VAL_MASK 0xFFFFFFFF
+
+/* ROT0_CPL_QUEUE_AXI */
+#define ROT0_CPL_QUEUE_AXI_CACHE_SHIFT 0
+#define ROT0_CPL_QUEUE_AXI_CACHE_MASK 0xF
+#define ROT0_CPL_QUEUE_AXI_PROT_SHIFT 4
+#define ROT0_CPL_QUEUE_AXI_PROT_MASK 0x70
+
+/* ROT0_CPL_MSG_THRESHOLD */
+#define ROT0_CPL_MSG_THRESHOLD_VAL_SHIFT 0
+#define ROT0_CPL_MSG_THRESHOLD_VAL_MASK 0x3F
+
+/* ROT0_CPL_MSG_AXI */
+#define ROT0_CPL_MSG_AXI_CACHE_SHIFT 0
+#define ROT0_CPL_MSG_AXI_CACHE_MASK 0xF
+#define ROT0_CPL_MSG_AXI_PROT_SHIFT 4
+#define ROT0_CPL_MSG_AXI_PROT_MASK 0x70
+
+/* ROT0_AXI_WB */
+#define ROT0_AXI_WB_CACHE_SHIFT 0
+#define ROT0_AXI_WB_CACHE_MASK 0xF
+#define ROT0_AXI_WB_PROT_SHIFT 4
+#define ROT0_AXI_WB_PROT_MASK 0x70
+
+/* ROT0_ERR_CFG */
+#define ROT0_ERR_CFG_STOP_ON_ERR_SHIFT 0
+#define ROT0_ERR_CFG_STOP_ON_ERR_MASK 0x1
+
+/* ROT0_ERR_STATUS */
+#define ROT0_ERR_STATUS_ROT_HBW_RD_SHIFT 0
+#define ROT0_ERR_STATUS_ROT_HBW_RD_MASK 0x1
+#define ROT0_ERR_STATUS_ROT_HBW_WR_SHIFT 1
+#define ROT0_ERR_STATUS_ROT_HBW_WR_MASK 0x2
+#define ROT0_ERR_STATUS_QMAN_HBW_RD_SHIFT 2
+#define ROT0_ERR_STATUS_QMAN_HBW_RD_MASK 0x4
+#define ROT0_ERR_STATUS_QMAN_HBW_WR_SHIFT 3
+#define ROT0_ERR_STATUS_QMAN_HBW_WR_MASK 0x8
+#define ROT0_ERR_STATUS_ROT_LBW_WR_SHIFT 4
+#define ROT0_ERR_STATUS_ROT_LBW_WR_MASK 0x10
+
+/* ROT0_WBC_MAX_OUTSTANDING */
+#define ROT0_WBC_MAX_OUTSTANDING_VAL_SHIFT 0
+#define ROT0_WBC_MAX_OUTSTANDING_VAL_MASK 0xFFFF
+
+/* ROT0_WBC_RL */
+#define ROT0_WBC_RL_SATURATION_SHIFT 0
+#define ROT0_WBC_RL_SATURATION_MASK 0xFF
+#define ROT0_WBC_RL_TIMEOUT_SHIFT 8
+#define ROT0_WBC_RL_TIMEOUT_MASK 0xFF00
+#define ROT0_WBC_RL_RST_TOKEN_SHIFT 16
+#define ROT0_WBC_RL_RST_TOKEN_MASK 0xFF0000
+#define ROT0_WBC_RL_RATE_LIMITER_EN_SHIFT 24
+#define ROT0_WBC_RL_RATE_LIMITER_EN_MASK 0x1000000
+
+/* ROT0_WBC_INFLIGHTS */
+#define ROT0_WBC_INFLIGHTS_VAL_SHIFT 0
+#define ROT0_WBC_INFLIGHTS_VAL_MASK 0xFFFF
+
+/* ROT0_WBC_INFO */
+#define ROT0_WBC_INFO_EMPTY_SHIFT 0
+#define ROT0_WBC_INFO_EMPTY_MASK 0x1
+#define ROT0_WBC_INFO_AXI_IDLE_SHIFT 1
+#define ROT0_WBC_INFO_AXI_IDLE_MASK 0x2
+
+/* ROT0_WBC_MON */
+#define ROT0_WBC_MON_CNT_SHIFT 0
+#define ROT0_WBC_MON_CNT_MASK 0x1
+#define ROT0_WBC_MON_TS_SHIFT 8
+#define ROT0_WBC_MON_TS_MASK 0x300
+#define ROT0_WBC_MON_CONTEXT_ID_SHIFT 16
+#define ROT0_WBC_MON_CONTEXT_ID_MASK 0xFFFF0000
+
+/* ROT0_RSB_CAM_MAX_SIZE */
+#define ROT0_RSB_CAM_MAX_SIZE_DATA_SHIFT 0
+#define ROT0_RSB_CAM_MAX_SIZE_DATA_MASK 0xFFFF
+#define ROT0_RSB_CAM_MAX_SIZE_MD_SHIFT 16
+#define ROT0_RSB_CAM_MAX_SIZE_MD_MASK 0xFFFF0000
+
+/* ROT0_RSB_CFG */
+#define ROT0_RSB_CFG_CACHE_DISABLE_SHIFT 0
+#define ROT0_RSB_CFG_CACHE_DISABLE_MASK 0x1
+#define ROT0_RSB_CFG_ENABLE_CGATE_SHIFT 1
+#define ROT0_RSB_CFG_ENABLE_CGATE_MASK 0x2
+
+/* ROT0_RSB_MAX_OS */
+#define ROT0_RSB_MAX_OS_VAL_SHIFT 0
+#define ROT0_RSB_MAX_OS_VAL_MASK 0xFFFF
+
+/* ROT0_RSB_RL */
+#define ROT0_RSB_RL_SATURATION_SHIFT 0
+#define ROT0_RSB_RL_SATURATION_MASK 0xFF
+#define ROT0_RSB_RL_TIMEOUT_SHIFT 8
+#define ROT0_RSB_RL_TIMEOUT_MASK 0xFF00
+#define ROT0_RSB_RL_RST_TOKEN_SHIFT 16
+#define ROT0_RSB_RL_RST_TOKEN_MASK 0xFF0000
+#define ROT0_RSB_RL_RATE_LIMITER_EN_SHIFT 24
+#define ROT0_RSB_RL_RATE_LIMITER_EN_MASK 0x1000000
+
+/* ROT0_RSB_INFLIGHTS */
+#define ROT0_RSB_INFLIGHTS_VAL_SHIFT 0
+#define ROT0_RSB_INFLIGHTS_VAL_MASK 0xFFFFFFFF
+
+/* ROT0_RSB_OCCUPANCY */
+#define ROT0_RSB_OCCUPANCY_VAL_SHIFT 0
+#define ROT0_RSB_OCCUPANCY_VAL_MASK 0xFFFFFFFF
+
+/* ROT0_RSB_INFO */
+#define ROT0_RSB_INFO_EMPTY_SHIFT 0
+#define ROT0_RSB_INFO_EMPTY_MASK 0x1
+#define ROT0_RSB_INFO_AXI_IDLE_SHIFT 1
+#define ROT0_RSB_INFO_AXI_IDLE_MASK 0x2
+
+/* ROT0_RSB_MON */
+#define ROT0_RSB_MON_CNT_SHIFT 0
+#define ROT0_RSB_MON_CNT_MASK 0x1FFF
+#define ROT0_RSB_MON_TS_SHIFT 16
+#define ROT0_RSB_MON_TS_MASK 0x30000
+
+/* ROT0_RSB_MON_CONTEXT_ID */
+#define ROT0_RSB_MON_CONTEXT_ID_VAL_SHIFT 0
+#define ROT0_RSB_MON_CONTEXT_ID_VAL_MASK 0xFFFFFFFF
+
+/* ROT0_MSS_HALT */
+#define ROT0_MSS_HALT_VAL_SHIFT 0
+#define ROT0_MSS_HALT_VAL_MASK 0x7
+
+/* ROT0_MSS_SEI_STATUS */
+#define ROT0_MSS_SEI_STATUS_I0_SHIFT 0
+#define ROT0_MSS_SEI_STATUS_I0_MASK 0x1
+#define ROT0_MSS_SEI_STATUS_I1_SHIFT 1
+#define ROT0_MSS_SEI_STATUS_I1_MASK 0x2
+#define ROT0_MSS_SEI_STATUS_I2_SHIFT 2
+#define ROT0_MSS_SEI_STATUS_I2_MASK 0x4
+#define ROT0_MSS_SEI_STATUS_I3_SHIFT 3
+#define ROT0_MSS_SEI_STATUS_I3_MASK 0x8
+#define ROT0_MSS_SEI_STATUS_I4_SHIFT 4
+#define ROT0_MSS_SEI_STATUS_I4_MASK 0x10
+#define ROT0_MSS_SEI_STATUS_I5_SHIFT 5
+#define ROT0_MSS_SEI_STATUS_I5_MASK 0x20
+#define ROT0_MSS_SEI_STATUS_I6_SHIFT 6
+#define ROT0_MSS_SEI_STATUS_I6_MASK 0x40
+#define ROT0_MSS_SEI_STATUS_I7_SHIFT 7
+#define ROT0_MSS_SEI_STATUS_I7_MASK 0x80
+#define ROT0_MSS_SEI_STATUS_I8_SHIFT 8
+#define ROT0_MSS_SEI_STATUS_I8_MASK 0x100
+#define ROT0_MSS_SEI_STATUS_I9_SHIFT 9
+#define ROT0_MSS_SEI_STATUS_I9_MASK 0x200
+#define ROT0_MSS_SEI_STATUS_I10_SHIFT 10
+#define ROT0_MSS_SEI_STATUS_I10_MASK 0x400
+#define ROT0_MSS_SEI_STATUS_I11_SHIFT 11
+#define ROT0_MSS_SEI_STATUS_I11_MASK 0x800
+#define ROT0_MSS_SEI_STATUS_I12_SHIFT 12
+#define ROT0_MSS_SEI_STATUS_I12_MASK 0x1000
+#define ROT0_MSS_SEI_STATUS_I13_SHIFT 13
+#define ROT0_MSS_SEI_STATUS_I13_MASK 0x2000
+#define ROT0_MSS_SEI_STATUS_I14_SHIFT 14
+#define ROT0_MSS_SEI_STATUS_I14_MASK 0x4000
+#define ROT0_MSS_SEI_STATUS_I15_SHIFT 15
+#define ROT0_MSS_SEI_STATUS_I15_MASK 0x8000
+#define ROT0_MSS_SEI_STATUS_I16_SHIFT 16
+#define ROT0_MSS_SEI_STATUS_I16_MASK 0x10000
+#define ROT0_MSS_SEI_STATUS_I17_SHIFT 17
+#define ROT0_MSS_SEI_STATUS_I17_MASK 0x20000
+#define ROT0_MSS_SEI_STATUS_I18_SHIFT 18
+#define ROT0_MSS_SEI_STATUS_I18_MASK 0x40000
+#define ROT0_MSS_SEI_STATUS_I19_SHIFT 19
+#define ROT0_MSS_SEI_STATUS_I19_MASK 0x80000
+#define ROT0_MSS_SEI_STATUS_I20_SHIFT 20
+#define ROT0_MSS_SEI_STATUS_I20_MASK 0x100000
+#define ROT0_MSS_SEI_STATUS_I21_SHIFT 21
+#define ROT0_MSS_SEI_STATUS_I21_MASK 0x200000
+
+/* ROT0_MSS_SEI_MASK */
+#define ROT0_MSS_SEI_MASK_VAL_SHIFT 0
+#define ROT0_MSS_SEI_MASK_VAL_MASK 0x3FFFFF
+
+/* ROT0_MSS_SPI_STATUS */
+#define ROT0_MSS_SPI_STATUS_I0_SHIFT 0
+#define ROT0_MSS_SPI_STATUS_I0_MASK 0x1
+#define ROT0_MSS_SPI_STATUS_I1_SHIFT 1
+#define ROT0_MSS_SPI_STATUS_I1_MASK 0x2
+#define ROT0_MSS_SPI_STATUS_I2_SHIFT 2
+#define ROT0_MSS_SPI_STATUS_I2_MASK 0x4
+#define ROT0_MSS_SPI_STATUS_I3_SHIFT 3
+#define ROT0_MSS_SPI_STATUS_I3_MASK 0x8
+#define ROT0_MSS_SPI_STATUS_I4_SHIFT 4
+#define ROT0_MSS_SPI_STATUS_I4_MASK 0x10
+#define ROT0_MSS_SPI_STATUS_I5_SHIFT 5
+#define ROT0_MSS_SPI_STATUS_I5_MASK 0x20
+#define ROT0_MSS_SPI_STATUS_I6_SHIFT 6
+#define ROT0_MSS_SPI_STATUS_I6_MASK 0x40
+#define ROT0_MSS_SPI_STATUS_I7_SHIFT 7
+#define ROT0_MSS_SPI_STATUS_I7_MASK 0x80
+
+/* ROT0_MSS_SPI_MASK */
+#define ROT0_MSS_SPI_MASK_VAL_SHIFT 0
+#define ROT0_MSS_SPI_MASK_VAL_MASK 0xFF
+
+/* ROT0_DISABLE_PAD_CALC */
+#define ROT0_DISABLE_PAD_CALC_VAL_SHIFT 0
+#define ROT0_DISABLE_PAD_CALC_VAL_MASK 0x3
+
+/* ROT0_QMAN_CFG */
+#define ROT0_QMAN_CFG_FORCE_STOP_SHIFT 0
+#define ROT0_QMAN_CFG_FORCE_STOP_MASK 0x1
+
+/* ROT0_CLK_EN */
+#define ROT0_CLK_EN_LBW_CFG_DIS_SHIFT 0
+#define ROT0_CLK_EN_LBW_CFG_DIS_MASK 0x1
+#define ROT0_CLK_EN_DBG_CFG_DIS_SHIFT 4
+#define ROT0_CLK_EN_DBG_CFG_DIS_MASK 0x10
+#define ROT0_CLK_EN_SB_EMPTY_MASK_SHIFT 5
+#define ROT0_CLK_EN_SB_EMPTY_MASK_MASK 0x20
+
+/* ROT0_MRSB_CAM_MAX_SIZE */
+#define ROT0_MRSB_CAM_MAX_SIZE_DATA_SHIFT 0
+#define ROT0_MRSB_CAM_MAX_SIZE_DATA_MASK 0xFFFF
+#define ROT0_MRSB_CAM_MAX_SIZE_MD_SHIFT 16
+#define ROT0_MRSB_CAM_MAX_SIZE_MD_MASK 0xFFFF0000
+
+/* ROT0_MRSB_CFG */
+#define ROT0_MRSB_CFG_CACHE_DISABLE_SHIFT 0
+#define ROT0_MRSB_CFG_CACHE_DISABLE_MASK 0x1
+#define ROT0_MRSB_CFG_ENABLE_CGATE_SHIFT 1
+#define ROT0_MRSB_CFG_ENABLE_CGATE_MASK 0x2
+
+/* ROT0_MRSB_MAX_OS */
+#define ROT0_MRSB_MAX_OS_VAL_SHIFT 0
+#define ROT0_MRSB_MAX_OS_VAL_MASK 0xFFFF
+
+/* ROT0_MRSB_RL */
+#define ROT0_MRSB_RL_SATURATION_SHIFT 0
+#define ROT0_MRSB_RL_SATURATION_MASK 0xFF
+#define ROT0_MRSB_RL_TIMEOUT_SHIFT 8
+#define ROT0_MRSB_RL_TIMEOUT_MASK 0xFF00
+#define ROT0_MRSB_RL_RST_TOKEN_SHIFT 16
+#define ROT0_MRSB_RL_RST_TOKEN_MASK 0xFF0000
+#define ROT0_MRSB_RL_RATE_LIMITER_EN_SHIFT 24
+#define ROT0_MRSB_RL_RATE_LIMITER_EN_MASK 0x1000000
+
+/* ROT0_MRSB_INFLIGHTS */
+#define ROT0_MRSB_INFLIGHTS_VAL_SHIFT 0
+#define ROT0_MRSB_INFLIGHTS_VAL_MASK 0xFFFFFFFF
+
+/* ROT0_MRSB_OCCUPANCY */
+#define ROT0_MRSB_OCCUPANCY_VAL_SHIFT 0
+#define ROT0_MRSB_OCCUPANCY_VAL_MASK 0xFFFFFFFF
+
+/* ROT0_MRSB_INFO */
+#define ROT0_MRSB_INFO_EMPTY_SHIFT 0
+#define ROT0_MRSB_INFO_EMPTY_MASK 0x1
+#define ROT0_MRSB_INFO_AXI_IDLE_SHIFT 1
+#define ROT0_MRSB_INFO_AXI_IDLE_MASK 0x2
+
+/* ROT0_MRSB_MON */
+#define ROT0_MRSB_MON_CNT_SHIFT 0
+#define ROT0_MRSB_MON_CNT_MASK 0x1FFF
+#define ROT0_MRSB_MON_TS_SHIFT 16
+#define ROT0_MRSB_MON_TS_MASK 0x30000
+
+/* ROT0_MRSB_MON_CONTEXT_ID */
+#define ROT0_MRSB_MON_CONTEXT_ID_VAL_SHIFT 0
+#define ROT0_MRSB_MON_CONTEXT_ID_VAL_MASK 0xFFFFFFFF
+
+/* ROT0_MSS_STS */
+#define ROT0_MSS_STS_IS_HALT_SHIFT 0
+#define ROT0_MSS_STS_IS_HALT_MASK 0x1
+
+#endif /* ASIC_REG_ROT0_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/rot0_qm_arc_aux_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/rot0_qm_arc_aux_regs.h
new file mode 100644
index 000000000000..e83daa33d737
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/rot0_qm_arc_aux_regs.h
@@ -0,0 +1,591 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_ROT0_QM_ARC_AUX_REGS_H_
+#define ASIC_REG_ROT0_QM_ARC_AUX_REGS_H_
+
+/*
+ *****************************************
+ *   ROT0_QM_ARC_AUX
+ *   (Prototype: QMAN_ARC_AUX)
+ *****************************************
+ */
+
+#define mmROT0_QM_ARC_AUX_RUN_HALT_REQ 0x4E08100
+
+#define mmROT0_QM_ARC_AUX_RUN_HALT_ACK 0x4E08104
+
+#define mmROT0_QM_ARC_AUX_RST_VEC_ADDR 0x4E08108
+
+#define mmROT0_QM_ARC_AUX_DBG_MODE 0x4E0810C
+
+#define mmROT0_QM_ARC_AUX_CLUSTER_NUM 0x4E08110
+
+#define mmROT0_QM_ARC_AUX_ARC_NUM 0x4E08114
+
+#define mmROT0_QM_ARC_AUX_WAKE_UP_EVENT 0x4E08118
+
+#define mmROT0_QM_ARC_AUX_DCCM_SYS_ADDR_BASE 0x4E0811C
+
+#define mmROT0_QM_ARC_AUX_CTI_AP_STS 0x4E08120
+
+#define mmROT0_QM_ARC_AUX_CTI_CFG_MUX_SEL 0x4E08124
+
+#define mmROT0_QM_ARC_AUX_ARC_RST 0x4E08128
+
+#define mmROT0_QM_ARC_AUX_ARC_RST_REQ 0x4E0812C
+
+#define mmROT0_QM_ARC_AUX_SRAM_LSB_ADDR 0x4E08130
+
+#define mmROT0_QM_ARC_AUX_SRAM_MSB_ADDR 0x4E08134
+
+#define mmROT0_QM_ARC_AUX_PCIE_LSB_ADDR 0x4E08138
+
+#define mmROT0_QM_ARC_AUX_PCIE_MSB_ADDR 0x4E0813C
+
+#define mmROT0_QM_ARC_AUX_CFG_LSB_ADDR 0x4E08140
+
+#define mmROT0_QM_ARC_AUX_CFG_MSB_ADDR 0x4E08144
+
+#define mmROT0_QM_ARC_AUX_HBM0_LSB_ADDR 0x4E08150
+
+#define mmROT0_QM_ARC_AUX_HBM0_MSB_ADDR 0x4E08154
+
+#define mmROT0_QM_ARC_AUX_HBM1_LSB_ADDR 0x4E08158
+
+#define mmROT0_QM_ARC_AUX_HBM1_MSB_ADDR 0x4E0815C
+
+#define mmROT0_QM_ARC_AUX_HBM2_LSB_ADDR 0x4E08160
+
+#define mmROT0_QM_ARC_AUX_HBM2_MSB_ADDR 0x4E08164
+
+#define mmROT0_QM_ARC_AUX_HBM3_LSB_ADDR 0x4E08168
+
+#define mmROT0_QM_ARC_AUX_HBM3_MSB_ADDR 0x4E0816C
+
+#define mmROT0_QM_ARC_AUX_HBM0_OFFSET 0x4E08170
+
+#define mmROT0_QM_ARC_AUX_HBM1_OFFSET 0x4E08174
+
+#define mmROT0_QM_ARC_AUX_HBM2_OFFSET 0x4E08178
+
+#define mmROT0_QM_ARC_AUX_HBM3_OFFSET 0x4E0817C
+
+#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_0 0x4E08180
+
+#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_1 0x4E08184
+
+#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_2 0x4E08188
+
+#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_3 0x4E0818C
+
+#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_4 0x4E08190
+
+#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_5 0x4E08194
+
+#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_6 0x4E08198
+
+#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_0 0x4E0819C
+
+#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_1 0x4E081A0
+
+#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_2 0x4E081A4
+
+#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_3 0x4E081A8
+
+#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_4 0x4E081AC
+
+#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_5 0x4E081B0
+
+#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_6 0x4E081B4
+
+#define mmROT0_QM_ARC_AUX_ARC_CBU_AWCACHE_OVR 0x4E081B8
+
+#define mmROT0_QM_ARC_AUX_ARC_LBU_AWCACHE_OVR 0x4E081BC
+
+#define mmROT0_QM_ARC_AUX_CONTEXT_ID_0 0x4E081C0
+
+#define mmROT0_QM_ARC_AUX_CONTEXT_ID_1 0x4E081C4
+
+#define mmROT0_QM_ARC_AUX_CONTEXT_ID_2 0x4E081C8
+
+#define mmROT0_QM_ARC_AUX_CONTEXT_ID_3 0x4E081CC
+
+#define mmROT0_QM_ARC_AUX_CONTEXT_ID_4 0x4E081D0
+
+#define mmROT0_QM_ARC_AUX_CONTEXT_ID_5 0x4E081D4
+
+#define mmROT0_QM_ARC_AUX_CONTEXT_ID_6 0x4E081D8
+
+#define mmROT0_QM_ARC_AUX_CONTEXT_ID_7 0x4E081DC
+
+#define mmROT0_QM_ARC_AUX_CID_OFFSET_0 0x4E081E0
+
+#define mmROT0_QM_ARC_AUX_CID_OFFSET_1 0x4E081E4
+
+#define mmROT0_QM_ARC_AUX_CID_OFFSET_2 0x4E081E8
+
+#define mmROT0_QM_ARC_AUX_CID_OFFSET_3 0x4E081EC
+
+#define mmROT0_QM_ARC_AUX_CID_OFFSET_4 0x4E081F0
+
+#define mmROT0_QM_ARC_AUX_CID_OFFSET_5 0x4E081F4
+
+#define mmROT0_QM_ARC_AUX_CID_OFFSET_6 0x4E081F8
+
+#define mmROT0_QM_ARC_AUX_CID_OFFSET_7 0x4E081FC
+
+#define mmROT0_QM_ARC_AUX_SW_INTR_0 0x4E08200
+
+#define mmROT0_QM_ARC_AUX_SW_INTR_1 0x4E08204
+
+#define mmROT0_QM_ARC_AUX_SW_INTR_2 0x4E08208
+
+#define mmROT0_QM_ARC_AUX_SW_INTR_3 0x4E0820C
+
+#define mmROT0_QM_ARC_AUX_SW_INTR_4 0x4E08210
+
+#define mmROT0_QM_ARC_AUX_SW_INTR_5 0x4E08214
+
+#define mmROT0_QM_ARC_AUX_SW_INTR_6 0x4E08218
+
+#define mmROT0_QM_ARC_AUX_SW_INTR_7 0x4E0821C
+
+#define mmROT0_QM_ARC_AUX_SW_INTR_8 0x4E08220
+
+#define mmROT0_QM_ARC_AUX_SW_INTR_9 0x4E08224
+
+#define mmROT0_QM_ARC_AUX_SW_INTR_10 0x4E08228
+
+#define mmROT0_QM_ARC_AUX_SW_INTR_11 0x4E0822C
+
+#define mmROT0_QM_ARC_AUX_SW_INTR_12 0x4E08230
+
+#define mmROT0_QM_ARC_AUX_SW_INTR_13 0x4E08234
+
+#define mmROT0_QM_ARC_AUX_SW_INTR_14 0x4E08238
+
+#define mmROT0_QM_ARC_AUX_SW_INTR_15 0x4E0823C
+
+#define mmROT0_QM_ARC_AUX_IRQ_INTR_MASK_0 0x4E08280
+
+#define mmROT0_QM_ARC_AUX_IRQ_INTR_MASK_1 0x4E08284
+
+#define mmROT0_QM_ARC_AUX_ARC_SEI_INTR_STS 0x4E08290
+
+#define mmROT0_QM_ARC_AUX_ARC_SEI_INTR_CLR 0x4E08294
+
+#define mmROT0_QM_ARC_AUX_ARC_SEI_INTR_MASK 0x4E08298
+
+#define mmROT0_QM_ARC_AUX_ARC_EXCPTN_CAUSE 0x4E0829C
+
+#define mmROT0_QM_ARC_AUX_SEI_INTR_HALT_EN 0x4E082A0
+
+#define mmROT0_QM_ARC_AUX_ARC_SEI_INTR_HALT_MASK 0x4E082A4
+
+#define mmROT0_QM_ARC_AUX_QMAN_SEI_INTR_HALT_MASK 0x4E082A8
+
+#define mmROT0_QM_ARC_AUX_ARC_REI_INTR_STS 0x4E082B0
+
+#define mmROT0_QM_ARC_AUX_ARC_REI_INTR_CLR 0x4E082B4
+
+#define mmROT0_QM_ARC_AUX_ARC_REI_INTR_MASK 0x4E082B8
+
+#define mmROT0_QM_ARC_AUX_DCCM_ECC_ERR_ADDR 0x4E082BC
+
+#define mmROT0_QM_ARC_AUX_DCCM_ECC_SYNDROME 0x4E082C0
+
+#define mmROT0_QM_ARC_AUX_I_CACHE_ECC_ERR_ADDR 0x4E082C4
+
+#define mmROT0_QM_ARC_AUX_I_CACHE_ECC_SYNDROME 0x4E082C8
+
+#define mmROT0_QM_ARC_AUX_D_CACHE_ECC_ERR_ADDR 0x4E082CC
+
+#define mmROT0_QM_ARC_AUX_D_CACHE_ECC_SYNDROME 0x4E082D0
+
+#define mmROT0_QM_ARC_AUX_LBW_TRMINATE_AWADDR_ERR 0x4E082E0
+
+#define mmROT0_QM_ARC_AUX_LBW_TRMINATE_ARADDR_ERR 0x4E082E4
+
+#define mmROT0_QM_ARC_AUX_CFG_LBW_TERMINATE_BRESP 0x4E082E8
+
+#define mmROT0_QM_ARC_AUX_CFG_LBW_TERMINATE_RRESP 0x4E082EC
+
+#define mmROT0_QM_ARC_AUX_CFG_LBW_TERMINATE_AXLEN 0x4E082F0
+
+#define mmROT0_QM_ARC_AUX_CFG_LBW_TERMINATE_AXSIZE 0x4E082F4
+
+#define mmROT0_QM_ARC_AUX_SCRATCHPAD_0 0x4E08300
+
+#define mmROT0_QM_ARC_AUX_SCRATCHPAD_1 0x4E08304
+
+#define mmROT0_QM_ARC_AUX_SCRATCHPAD_2 0x4E08308
+
+#define mmROT0_QM_ARC_AUX_SCRATCHPAD_3 0x4E0830C
+
+#define mmROT0_QM_ARC_AUX_SCRATCHPAD_4 0x4E08310
+
+#define mmROT0_QM_ARC_AUX_SCRATCHPAD_5 0x4E08314
+
+#define mmROT0_QM_ARC_AUX_SCRATCHPAD_6 0x4E08318
+
+#define mmROT0_QM_ARC_AUX_SCRATCHPAD_7 0x4E0831C
+
+#define mmROT0_QM_ARC_AUX_TOTAL_CBU_WR_CNT 0x4E08320
+
+#define mmROT0_QM_ARC_AUX_INFLIGHT_CBU_WR_CNT 0x4E08324
+
+#define mmROT0_QM_ARC_AUX_TOTAL_CBU_RD_CNT 0x4E08328
+
+#define mmROT0_QM_ARC_AUX_INFLIGHT_CBU_RD_CNT 0x4E0832C
+
+#define mmROT0_QM_ARC_AUX_TOTAL_LBU_WR_CNT 0x4E08330
+
+#define mmROT0_QM_ARC_AUX_INFLIGHT_LBU_WR_CNT 0x4E08334
+
+#define mmROT0_QM_ARC_AUX_TOTAL_LBU_RD_CNT 0x4E08338
+
+#define mmROT0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT 0x4E0833C
+
+#define mmROT0_QM_ARC_AUX_CBU_ARUSER_OVR 0x4E08350
+
+#define mmROT0_QM_ARC_AUX_CBU_ARUSER_OVR_EN 0x4E08354
+
+#define mmROT0_QM_ARC_AUX_CBU_AWUSER_OVR 0x4E08358
+
+#define mmROT0_QM_ARC_AUX_CBU_AWUSER_OVR_EN 0x4E0835C
+
+#define mmROT0_QM_ARC_AUX_CBU_ARUSER_MSB_OVR 0x4E08360
+
+#define mmROT0_QM_ARC_AUX_CBU_ARUSER_MSB_OVR_EN 0x4E08364
+
+#define mmROT0_QM_ARC_AUX_CBU_AWUSER_MSB_OVR 0x4E08368
+
+#define mmROT0_QM_ARC_AUX_CBU_AWUSER_MSB_OVR_EN 0x4E0836C
+
+#define mmROT0_QM_ARC_AUX_CBU_AXCACHE_OVR 0x4E08370
+
+#define mmROT0_QM_ARC_AUX_CBU_LOCK_OVR 0x4E08374
+
+#define mmROT0_QM_ARC_AUX_CBU_PROT_OVR 0x4E08378
+
+#define mmROT0_QM_ARC_AUX_CBU_MAX_OUTSTANDING 0x4E0837C
+
+#define mmROT0_QM_ARC_AUX_CBU_EARLY_BRESP_EN 0x4E08380
+
+#define mmROT0_QM_ARC_AUX_CBU_FORCE_RSP_OK 0x4E08384
+
+#define mmROT0_QM_ARC_AUX_CBU_NO_WR_INFLIGHT 0x4E0838C
+
+#define mmROT0_QM_ARC_AUX_CBU_SEI_INTR_ID 0x4E08390
+
+#define mmROT0_QM_ARC_AUX_LBU_ARUSER_OVR 0x4E08400
+
+#define mmROT0_QM_ARC_AUX_LBU_ARUSER_OVR_EN 0x4E08404
+
+#define mmROT0_QM_ARC_AUX_LBU_AWUSER_OVR 0x4E08408
+
+#define mmROT0_QM_ARC_AUX_LBU_AWUSER_OVR_EN 0x4E0840C
+
+#define mmROT0_QM_ARC_AUX_LBU_AXCACHE_OVR 0x4E08420
+
+#define mmROT0_QM_ARC_AUX_LBU_LOCK_OVR 0x4E08424
+
+#define mmROT0_QM_ARC_AUX_LBU_PROT_OVR 0x4E08428
+
+#define mmROT0_QM_ARC_AUX_LBU_MAX_OUTSTANDING 0x4E0842C
+
+#define mmROT0_QM_ARC_AUX_LBU_EARLY_BRESP_EN 0x4E08430
+
+#define mmROT0_QM_ARC_AUX_LBU_FORCE_RSP_OK 0x4E08434
+
+#define mmROT0_QM_ARC_AUX_LBU_NO_WR_INFLIGHT 0x4E0843C
+
+#define mmROT0_QM_ARC_AUX_LBU_SEI_INTR_ID 0x4E08440
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0 0x4E08500
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_1 0x4E08504
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_2 0x4E08508
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_3 0x4E0850C
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_4 0x4E08510
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_5 0x4E08514
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_6 0x4E08518
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_7 0x4E0851C
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_SIZE_0 0x4E08520
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_SIZE_1 0x4E08524
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_SIZE_2 0x4E08528
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_SIZE_3 0x4E0852C
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_SIZE_4 0x4E08530
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_SIZE_5 0x4E08534
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_SIZE_6 0x4E08538
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_SIZE_7 0x4E0853C
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PI_0 0x4E08540
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PI_1 0x4E08544
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PI_2 0x4E08548
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PI_3 0x4E0854C
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PI_4 0x4E08550
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PI_5 0x4E08554
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PI_6 0x4E08558
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PI_7 0x4E0855C
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_CI_0 0x4E08560
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_CI_1 0x4E08564
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_CI_2 0x4E08568
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_CI_3 0x4E0856C
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_CI_4 0x4E08570
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_CI_5 0x4E08574
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_CI_6 0x4E08578
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_CI_7 0x4E0857C
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_0 0x4E08580
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_1 0x4E08584
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_2 0x4E08588
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_3 0x4E0858C
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_4 0x4E08590
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_5 0x4E08594
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_6 0x4E08598
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_7 0x4E0859C
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_0 0x4E085A0
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_1 0x4E085A4
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_2 0x4E085A8
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_3 0x4E085AC
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_4 0x4E085B0
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_5 0x4E085B4
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_6 0x4E085B8
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_7 0x4E085BC
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_0 0x4E085C0
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_1 0x4E085C4
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_2 0x4E085C8
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_3 0x4E085CC
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_4 0x4E085D0
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_5 0x4E085D4
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_6 0x4E085D8
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_7 0x4E085DC
+
+#define mmROT0_QM_ARC_AUX_GENERAL_Q_VLD_ENTRY_MASK 0x4E085E0
+
+#define mmROT0_QM_ARC_AUX_NIC_Q_VLD_ENTRY_MASK 0x4E085E4
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_DROP_EN 0x4E08620
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_WARN_MSG 0x4E08624
+
+#define mmROT0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG 0x4E08628
+
+#define mmROT0_QM_ARC_AUX_DCCM_GEN_AXI_AWPROT 0x4E08630
+
+#define mmROT0_QM_ARC_AUX_DCCM_GEN_AXI_AWUSER 0x4E08634
+
+#define mmROT0_QM_ARC_AUX_DCCM_GEN_AXI_AWBURST 0x4E08638
+
+#define mmROT0_QM_ARC_AUX_DCCM_GEN_AXI_AWLOCK 0x4E0863C
+
+#define mmROT0_QM_ARC_AUX_DCCM_GEN_AXI_AWCACHE 0x4E08640
+
+#define mmROT0_QM_ARC_AUX_DCCM_WRR_ARB_WEIGHT 0x4E08644
+
+#define mmROT0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_FULL_CFG 0x4E08648
+
+#define mmROT0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT 0x4E0864C
+
+#define mmROT0_QM_ARC_AUX_QMAN_CQ_IFIFO_SHADOW_CI 0x4E08650
+
+#define mmROT0_QM_ARC_AUX_QMAN_ARC_CQ_IFIFO_SHADOW_CI 0x4E08654
+
+#define mmROT0_QM_ARC_AUX_QMAN_CQ_SHADOW_CI 0x4E08658
+
+#define mmROT0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI 0x4E0865C
+
+#define mmROT0_QM_ARC_AUX_AUX2APB_PROT 0x4E08700
+
+#define mmROT0_QM_ARC_AUX_LBW_FORK_WIN_EN 0x4E08704
+
+#define mmROT0_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR0 0x4E08708
+
+#define mmROT0_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK0 0x4E0870C
+
+#define mmROT0_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR1 0x4E08710
+
+#define mmROT0_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK1 0x4E08714
+
+#define mmROT0_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR0 0x4E08718
+
+#define mmROT0_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK0 0x4E0871C
+
+#define mmROT0_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR1 0x4E08720
+
+#define mmROT0_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK1 0x4E08724
+
+#define mmROT0_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR0 0x4E08728
+
+#define mmROT0_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR1 0x4E0872C
+
+#define mmROT0_QM_ARC_AUX_ARC_ACC_ENGS_LBW_FORK_MASK 0x4E08730
+
+#define mmROT0_QM_ARC_AUX_ARC_DUP_ENG_LBW_FORK_ADDR 0x4E08734
+
+#define mmROT0_QM_ARC_AUX_ARC_ACP_ENG_LBW_FORK_ADDR 0x4E08738
+
+#define mmROT0_QM_ARC_AUX_ARC_ACC_ENGS_VIRTUAL_ADDR 0x4E0873C
+
+#define mmROT0_QM_ARC_AUX_CBU_FORK_WIN_EN 0x4E08740
+
+#define mmROT0_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_LSB 0x4E08750
+
+#define mmROT0_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_MSB 0x4E08754
+
+#define mmROT0_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_LSB 0x4E08758
+
+#define mmROT0_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_MSB 0x4E0875C
+
+#define mmROT0_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_LSB 0x4E08760
+
+#define mmROT0_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_MSB 0x4E08764
+
+#define mmROT0_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_LSB 0x4E08768
+
+#define mmROT0_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_MSB 0x4E0876C
+
+#define mmROT0_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_LSB 0x4E08770
+
+#define mmROT0_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_MSB 0x4E08774
+
+#define mmROT0_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_LSB 0x4E08778
+
+#define mmROT0_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_MSB 0x4E0877C
+
+#define mmROT0_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_LSB 0x4E08780
+
+#define mmROT0_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_MSB 0x4E08784
+
+#define mmROT0_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_LSB 0x4E08788
+
+#define mmROT0_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_MSB 0x4E0878C
+
+#define mmROT0_QM_ARC_AUX_CBU_TRMINATE_ARADDR_LSB 0x4E08790
+
+#define mmROT0_QM_ARC_AUX_CBU_TRMINATE_ARADDR_MSB 0x4E08794
+
+#define mmROT0_QM_ARC_AUX_CFG_CBU_TERMINATE_BRESP 0x4E08798
+
+#define mmROT0_QM_ARC_AUX_CFG_CBU_TERMINATE_RRESP 0x4E0879C
+
+#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_0 0x4E08800
+
+#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_1 0x4E08804
+
+#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_2 0x4E08808
+
+#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_3 0x4E0880C
+
+#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_4 0x4E08810
+
+#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_5 0x4E08814
+
+#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_6 0x4E08818
+
+#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_7 0x4E0881C
+
+#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_8 0x4E08820
+
+#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_9 0x4E08824
+
+#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_10 0x4E08828
+
+#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_11 0x4E0882C
+
+#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_12 0x4E08830
+
+#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_13 0x4E08834
+
+#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_14 0x4E08838
+
+#define mmROT0_QM_ARC_AUX_ARC_REGION_CFG_15 0x4E0883C
+
+#define mmROT0_QM_ARC_AUX_DCCM_TRMINATE_AWADDR_ERR 0x4E08840
+
+#define mmROT0_QM_ARC_AUX_DCCM_TRMINATE_ARADDR_ERR 0x4E08844
+
+#define mmROT0_QM_ARC_AUX_CFG_DCCM_TERMINATE_BRESP 0x4E08848
+
+#define mmROT0_QM_ARC_AUX_CFG_DCCM_TERMINATE_RRESP 0x4E0884C
+
+#define mmROT0_QM_ARC_AUX_CFG_DCCM_TERMINATE_EN 0x4E08850
+
+#define mmROT0_QM_ARC_AUX_CFG_DCCM_SECURE_REGION 0x4E08854
+
+#define mmROT0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT 0x4E08900
+
+#define mmROT0_QM_ARC_AUX_ARC_AXI_ORDERING_CTL 0x4E08904
+
+#define mmROT0_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR_MSK 0x4E08908
+
+#define mmROT0_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR 0x4E0890C
+
+#define mmROT0_QM_ARC_AUX_ARC_ACC_ENGS_BUSER 0x4E08910
+
+#define mmROT0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN 0x4E08920
+
+#endif /* ASIC_REG_ROT0_QM_ARC_AUX_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/rot0_qm_axuser_nonsecured_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/rot0_qm_axuser_nonsecured_regs.h
new file mode 100644
index 000000000000..8e040a2ef1c1
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/rot0_qm_axuser_nonsecured_regs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_ROT0_QM_AXUSER_NONSECURED_REGS_H_
+#define ASIC_REG_ROT0_QM_AXUSER_NONSECURED_REGS_H_
+
+/*
+ *****************************************
+ *   ROT0_QM_AXUSER_NONSECURED
+ *   (Prototype: AXUSER)
+ *****************************************
+ */
+
+#define mmROT0_QM_AXUSER_NONSECURED_HB_ASID 0x4E0AB80
+
+#define mmROT0_QM_AXUSER_NONSECURED_HB_MMU_BP 0x4E0AB84
+
+#define mmROT0_QM_AXUSER_NONSECURED_HB_STRONG_ORDER 0x4E0AB88
+
+#define mmROT0_QM_AXUSER_NONSECURED_HB_NO_SNOOP 0x4E0AB8C
+
+#define mmROT0_QM_AXUSER_NONSECURED_HB_WR_REDUCTION 0x4E0AB90
+
+#define mmROT0_QM_AXUSER_NONSECURED_HB_RD_ATOMIC 0x4E0AB94
+
+#define mmROT0_QM_AXUSER_NONSECURED_HB_QOS 0x4E0AB98
+
+#define mmROT0_QM_AXUSER_NONSECURED_HB_RSVD 0x4E0AB9C
+
+#define mmROT0_QM_AXUSER_NONSECURED_HB_EMEM_CPAGE 0x4E0ABA0
+
+#define mmROT0_QM_AXUSER_NONSECURED_HB_CORE 0x4E0ABA4
+
+#define mmROT0_QM_AXUSER_NONSECURED_E2E_COORD 0x4E0ABA8
+
+#define mmROT0_QM_AXUSER_NONSECURED_HB_WR_OVRD_LO 0x4E0ABB0
+
+#define mmROT0_QM_AXUSER_NONSECURED_HB_WR_OVRD_HI 0x4E0ABB4
+
+#define mmROT0_QM_AXUSER_NONSECURED_HB_RD_OVRD_LO 0x4E0ABB8
+
+#define mmROT0_QM_AXUSER_NONSECURED_HB_RD_OVRD_HI 0x4E0ABBC
+
+#define mmROT0_QM_AXUSER_NONSECURED_LB_COORD 0x4E0ABC0
+
+#define mmROT0_QM_AXUSER_NONSECURED_LB_LOCK 0x4E0ABC4
+
+#define mmROT0_QM_AXUSER_NONSECURED_LB_RSVD 0x4E0ABC8
+
+#define mmROT0_QM_AXUSER_NONSECURED_LB_OVRD 0x4E0ABCC
+
+#endif /* ASIC_REG_ROT0_QM_AXUSER_NONSECURED_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/rot0_qm_cgm_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/rot0_qm_cgm_regs.h
new file mode 100644
index 000000000000..077ae2347a3d
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/rot0_qm_cgm_regs.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_ROT0_QM_CGM_REGS_H_
+#define ASIC_REG_ROT0_QM_CGM_REGS_H_
+
+/*
+ *****************************************
+ *   ROT0_QM_CGM
+ *   (Prototype: QMAN_CGM)
+ *****************************************
+ */
+
+#define mmROT0_QM_CGM_CFG 0x4E0AD80
+
+#define mmROT0_QM_CGM_STS 0x4E0AD84
+
+#define mmROT0_QM_CGM_CFG1 0x4E0AD88
+
+#endif /* ASIC_REG_ROT0_QM_CGM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/rot0_qm_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/rot0_qm_regs.h
new file mode 100644
index 000000000000..de3c85510af2
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/rot0_qm_regs.h
@@ -0,0 +1,1057 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_ROT0_QM_REGS_H_
+#define ASIC_REG_ROT0_QM_REGS_H_
+
+/*
+ *****************************************
+ *   ROT0_QM
+ *   (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmROT0_QM_GLBL_CFG0 0x4E0A000
+
+#define mmROT0_QM_GLBL_CFG1 0x4E0A004
+
+#define mmROT0_QM_GLBL_CFG2 0x4E0A008
+
+#define mmROT0_QM_GLBL_ERR_CFG 0x4E0A00C
+
+#define mmROT0_QM_GLBL_ERR_CFG1 0x4E0A010
+
+#define mmROT0_QM_GLBL_ERR_ARC_HALT_EN 0x4E0A014
+
+#define mmROT0_QM_GLBL_AXCACHE 0x4E0A018
+
+#define mmROT0_QM_GLBL_STS0 0x4E0A01C
+
+#define mmROT0_QM_GLBL_STS1 0x4E0A020
+
+#define mmROT0_QM_GLBL_ERR_STS_0 0x4E0A024
+
+#define mmROT0_QM_GLBL_ERR_STS_1 0x4E0A028
+
+#define mmROT0_QM_GLBL_ERR_STS_2 0x4E0A02C
+
+#define mmROT0_QM_GLBL_ERR_STS_3 0x4E0A030
+
+#define mmROT0_QM_GLBL_ERR_STS_4 0x4E0A034
+
+#define mmROT0_QM_GLBL_ERR_MSG_EN_0 0x4E0A038
+
+#define mmROT0_QM_GLBL_ERR_MSG_EN_1 0x4E0A03C
+
+#define mmROT0_QM_GLBL_ERR_MSG_EN_2 0x4E0A040
+
+#define mmROT0_QM_GLBL_ERR_MSG_EN_3 0x4E0A044
+
+#define mmROT0_QM_GLBL_ERR_MSG_EN_4 0x4E0A048
+
+#define mmROT0_QM_GLBL_PROT 0x4E0A04C
+
+#define mmROT0_QM_PQ_BASE_LO_0 0x4E0A050
+
+#define mmROT0_QM_PQ_BASE_LO_1 0x4E0A054
+
+#define mmROT0_QM_PQ_BASE_LO_2 0x4E0A058
+
+#define mmROT0_QM_PQ_BASE_LO_3 0x4E0A05C
+
+#define mmROT0_QM_PQ_BASE_HI_0 0x4E0A060
+
+#define mmROT0_QM_PQ_BASE_HI_1 0x4E0A064
+
+#define mmROT0_QM_PQ_BASE_HI_2 0x4E0A068
+
+#define mmROT0_QM_PQ_BASE_HI_3 0x4E0A06C
+
+#define mmROT0_QM_PQ_SIZE_0 0x4E0A070
+
+#define mmROT0_QM_PQ_SIZE_1 0x4E0A074
+
+#define mmROT0_QM_PQ_SIZE_2 0x4E0A078
+
+#define mmROT0_QM_PQ_SIZE_3 0x4E0A07C
+
+#define mmROT0_QM_PQ_PI_0 0x4E0A080
+
+#define mmROT0_QM_PQ_PI_1 0x4E0A084
+
+#define mmROT0_QM_PQ_PI_2 0x4E0A088
+
+#define mmROT0_QM_PQ_PI_3 0x4E0A08C
+
+#define mmROT0_QM_PQ_CI_0 0x4E0A090
+
+#define mmROT0_QM_PQ_CI_1 0x4E0A094
+
+#define mmROT0_QM_PQ_CI_2 0x4E0A098
+
+#define mmROT0_QM_PQ_CI_3 0x4E0A09C
+
+#define mmROT0_QM_PQ_CFG0_0 0x4E0A0A0
+
+#define mmROT0_QM_PQ_CFG0_1 0x4E0A0A4
+
+#define mmROT0_QM_PQ_CFG0_2 0x4E0A0A8
+
+#define mmROT0_QM_PQ_CFG0_3 0x4E0A0AC
+
+#define mmROT0_QM_PQ_CFG1_0 0x4E0A0B0
+
+#define mmROT0_QM_PQ_CFG1_1 0x4E0A0B4
+
+#define mmROT0_QM_PQ_CFG1_2 0x4E0A0B8
+
+#define mmROT0_QM_PQ_CFG1_3 0x4E0A0BC
+
+#define mmROT0_QM_PQ_STS0_0 0x4E0A0C0
+
+#define mmROT0_QM_PQ_STS0_1 0x4E0A0C4
+
+#define mmROT0_QM_PQ_STS0_2 0x4E0A0C8
+
+#define mmROT0_QM_PQ_STS0_3 0x4E0A0CC
+
+#define mmROT0_QM_PQ_STS1_0 0x4E0A0D0
+
+#define mmROT0_QM_PQ_STS1_1 0x4E0A0D4
+
+#define mmROT0_QM_PQ_STS1_2 0x4E0A0D8
+
+#define mmROT0_QM_PQ_STS1_3 0x4E0A0DC
+
+#define mmROT0_QM_CQ_CFG0_0 0x4E0A0E0
+
+#define mmROT0_QM_CQ_CFG0_1 0x4E0A0E4
+
+#define mmROT0_QM_CQ_CFG0_2 0x4E0A0E8
+
+#define mmROT0_QM_CQ_CFG0_3 0x4E0A0EC
+
+#define mmROT0_QM_CQ_CFG0_4 0x4E0A0F0
+
+#define mmROT0_QM_CQ_STS0_0 0x4E0A0F4
+
+#define mmROT0_QM_CQ_STS0_1 0x4E0A0F8
+
+#define mmROT0_QM_CQ_STS0_2 0x4E0A0FC
+
+#define mmROT0_QM_CQ_STS0_3 0x4E0A100
+
+#define mmROT0_QM_CQ_STS0_4 0x4E0A104
+
+#define mmROT0_QM_CQ_CFG1_0 0x4E0A108
+
+#define mmROT0_QM_CQ_CFG1_1 0x4E0A10C
+
+#define mmROT0_QM_CQ_CFG1_2 0x4E0A110
+
+#define mmROT0_QM_CQ_CFG1_3 0x4E0A114
+
+#define mmROT0_QM_CQ_CFG1_4 0x4E0A118
+
+#define mmROT0_QM_CQ_STS1_0 0x4E0A11C
+
+#define mmROT0_QM_CQ_STS1_1 0x4E0A120
+
+#define mmROT0_QM_CQ_STS1_2 0x4E0A124
+
+#define mmROT0_QM_CQ_STS1_3 0x4E0A128
+
+#define mmROT0_QM_CQ_STS1_4 0x4E0A12C
+
+#define mmROT0_QM_CQ_PTR_LO_0 0x4E0A150
+
+#define mmROT0_QM_CQ_PTR_HI_0 0x4E0A154
+
+#define mmROT0_QM_CQ_TSIZE_0 0x4E0A158
+
+#define mmROT0_QM_CQ_CTL_0 0x4E0A15C
+
+#define mmROT0_QM_CQ_PTR_LO_1 0x4E0A160
+
+#define mmROT0_QM_CQ_PTR_HI_1 0x4E0A164
+
+#define mmROT0_QM_CQ_TSIZE_1 0x4E0A168
+
+#define mmROT0_QM_CQ_CTL_1 0x4E0A16C
+
+#define mmROT0_QM_CQ_PTR_LO_2 0x4E0A170
+
+#define mmROT0_QM_CQ_PTR_HI_2 0x4E0A174
+
+#define mmROT0_QM_CQ_TSIZE_2 0x4E0A178
+
+#define mmROT0_QM_CQ_CTL_2 0x4E0A17C
+
+#define mmROT0_QM_CQ_PTR_LO_3 0x4E0A180
+
+#define mmROT0_QM_CQ_PTR_HI_3 0x4E0A184
+
+#define mmROT0_QM_CQ_TSIZE_3 0x4E0A188
+
+#define mmROT0_QM_CQ_CTL_3 0x4E0A18C
+
+#define mmROT0_QM_CQ_PTR_LO_4 0x4E0A190
+
+#define mmROT0_QM_CQ_PTR_HI_4 0x4E0A194
+
+#define mmROT0_QM_CQ_TSIZE_4 0x4E0A198
+
+#define mmROT0_QM_CQ_CTL_4 0x4E0A19C
+
+#define mmROT0_QM_CQ_TSIZE_STS_0 0x4E0A1A0
+
+#define mmROT0_QM_CQ_TSIZE_STS_1 0x4E0A1A4
+
+#define mmROT0_QM_CQ_TSIZE_STS_2 0x4E0A1A8
+
+#define mmROT0_QM_CQ_TSIZE_STS_3 0x4E0A1AC
+
+#define mmROT0_QM_CQ_TSIZE_STS_4 0x4E0A1B0
+
+#define mmROT0_QM_CQ_PTR_LO_STS_0 0x4E0A1B4
+
+#define mmROT0_QM_CQ_PTR_LO_STS_1 0x4E0A1B8
+
+#define mmROT0_QM_CQ_PTR_LO_STS_2 0x4E0A1BC
+
+#define mmROT0_QM_CQ_PTR_LO_STS_3 0x4E0A1C0
+
+#define mmROT0_QM_CQ_PTR_LO_STS_4 0x4E0A1C4
+
+#define mmROT0_QM_CQ_PTR_HI_STS_0 0x4E0A1C8
+
+#define mmROT0_QM_CQ_PTR_HI_STS_1 0x4E0A1CC
+
+#define mmROT0_QM_CQ_PTR_HI_STS_2 0x4E0A1D0
+
+#define mmROT0_QM_CQ_PTR_HI_STS_3 0x4E0A1D4
+
+#define mmROT0_QM_CQ_PTR_HI_STS_4 0x4E0A1D8
+
+#define mmROT0_QM_CQ_IFIFO_STS_0 0x4E0A1DC
+
+#define mmROT0_QM_CQ_IFIFO_STS_1 0x4E0A1E0
+
+#define mmROT0_QM_CQ_IFIFO_STS_2 0x4E0A1E4
+
+#define mmROT0_QM_CQ_IFIFO_STS_3 0x4E0A1E8
+
+#define mmROT0_QM_CQ_IFIFO_STS_4 0x4E0A1EC
+
+#define mmROT0_QM_CP_MSG_BASE0_ADDR_LO_0 0x4E0A1F0
+
+#define mmROT0_QM_CP_MSG_BASE0_ADDR_LO_1 0x4E0A1F4
+
+#define mmROT0_QM_CP_MSG_BASE0_ADDR_LO_2 0x4E0A1F8
+
+#define mmROT0_QM_CP_MSG_BASE0_ADDR_LO_3 0x4E0A1FC
+
+#define mmROT0_QM_CP_MSG_BASE0_ADDR_LO_4 0x4E0A200
+
+#define mmROT0_QM_CP_MSG_BASE0_ADDR_HI_0 0x4E0A204
+
+#define mmROT0_QM_CP_MSG_BASE0_ADDR_HI_1 0x4E0A208
+
+#define mmROT0_QM_CP_MSG_BASE0_ADDR_HI_2 0x4E0A20C
+
+#define mmROT0_QM_CP_MSG_BASE0_ADDR_HI_3 0x4E0A210
+
+#define mmROT0_QM_CP_MSG_BASE0_ADDR_HI_4 0x4E0A214
+
+#define mmROT0_QM_CP_MSG_BASE1_ADDR_LO_0 0x4E0A218
+
+#define mmROT0_QM_CP_MSG_BASE1_ADDR_LO_1 0x4E0A21C
+
+#define mmROT0_QM_CP_MSG_BASE1_ADDR_LO_2 0x4E0A220
+
+#define mmROT0_QM_CP_MSG_BASE1_ADDR_LO_3 0x4E0A224
+
+#define mmROT0_QM_CP_MSG_BASE1_ADDR_LO_4 0x4E0A228
+
+#define mmROT0_QM_CP_MSG_BASE1_ADDR_HI_0 0x4E0A22C
+
+#define mmROT0_QM_CP_MSG_BASE1_ADDR_HI_1 0x4E0A230
+
+#define mmROT0_QM_CP_MSG_BASE1_ADDR_HI_2 0x4E0A234
+
+#define mmROT0_QM_CP_MSG_BASE1_ADDR_HI_3 0x4E0A238
+
+#define mmROT0_QM_CP_MSG_BASE1_ADDR_HI_4 0x4E0A23C
+
+#define mmROT0_QM_CP_MSG_BASE2_ADDR_LO_0 0x4E0A240
+
+#define mmROT0_QM_CP_MSG_BASE2_ADDR_LO_1 0x4E0A244
+
+#define mmROT0_QM_CP_MSG_BASE2_ADDR_LO_2 0x4E0A248
+
+#define mmROT0_QM_CP_MSG_BASE2_ADDR_LO_3 0x4E0A24C
+
+#define mmROT0_QM_CP_MSG_BASE2_ADDR_LO_4 0x4E0A250
+
+#define mmROT0_QM_CP_MSG_BASE2_ADDR_HI_0 0x4E0A254
+
+#define mmROT0_QM_CP_MSG_BASE2_ADDR_HI_1 0x4E0A258
+
+#define mmROT0_QM_CP_MSG_BASE2_ADDR_HI_2 0x4E0A25C
+
+#define mmROT0_QM_CP_MSG_BASE2_ADDR_HI_3 0x4E0A260
+
+#define mmROT0_QM_CP_MSG_BASE2_ADDR_HI_4 0x4E0A264
+
+#define mmROT0_QM_CP_MSG_BASE3_ADDR_LO_0 0x4E0A268
+
+#define mmROT0_QM_CP_MSG_BASE3_ADDR_LO_1 0x4E0A26C
+
+#define mmROT0_QM_CP_MSG_BASE3_ADDR_LO_2 0x4E0A270
+
+#define mmROT0_QM_CP_MSG_BASE3_ADDR_LO_3 0x4E0A274
+
+#define mmROT0_QM_CP_MSG_BASE3_ADDR_LO_4 0x4E0A278
+
+#define mmROT0_QM_CP_MSG_BASE3_ADDR_HI_0 0x4E0A27C
+
+#define mmROT0_QM_CP_MSG_BASE3_ADDR_HI_1 0x4E0A280
+
+#define mmROT0_QM_CP_MSG_BASE3_ADDR_HI_2 0x4E0A284
+
+#define mmROT0_QM_CP_MSG_BASE3_ADDR_HI_3 0x4E0A288
+
+#define mmROT0_QM_CP_MSG_BASE3_ADDR_HI_4 0x4E0A28C
+
+#define mmROT0_QM_CP_FENCE0_RDATA_0 0x4E0A290
+
+#define mmROT0_QM_CP_FENCE0_RDATA_1 0x4E0A294
+
+#define mmROT0_QM_CP_FENCE0_RDATA_2 0x4E0A298
+
+#define mmROT0_QM_CP_FENCE0_RDATA_3 0x4E0A29C
+
+#define mmROT0_QM_CP_FENCE0_RDATA_4 0x4E0A2A0
+
+#define mmROT0_QM_CP_FENCE1_RDATA_0 0x4E0A2A4
+
+#define mmROT0_QM_CP_FENCE1_RDATA_1 0x4E0A2A8
+
+#define mmROT0_QM_CP_FENCE1_RDATA_2 0x4E0A2AC
+
+#define mmROT0_QM_CP_FENCE1_RDATA_3 0x4E0A2B0
+
+#define mmROT0_QM_CP_FENCE1_RDATA_4 0x4E0A2B4
+
+#define mmROT0_QM_CP_FENCE2_RDATA_0 0x4E0A2B8
+
+#define mmROT0_QM_CP_FENCE2_RDATA_1 0x4E0A2BC
+
+#define mmROT0_QM_CP_FENCE2_RDATA_2 0x4E0A2C0
+
+#define mmROT0_QM_CP_FENCE2_RDATA_3 0x4E0A2C4
+
+#define mmROT0_QM_CP_FENCE2_RDATA_4 0x4E0A2C8
+
+#define mmROT0_QM_CP_FENCE3_RDATA_0 0x4E0A2CC
+
+#define mmROT0_QM_CP_FENCE3_RDATA_1 0x4E0A2D0
+
+#define mmROT0_QM_CP_FENCE3_RDATA_2 0x4E0A2D4
+
+#define mmROT0_QM_CP_FENCE3_RDATA_3 0x4E0A2D8
+
+#define mmROT0_QM_CP_FENCE3_RDATA_4 0x4E0A2DC
+
+#define mmROT0_QM_CP_FENCE0_CNT_0 0x4E0A2E0
+
+#define mmROT0_QM_CP_FENCE0_CNT_1 0x4E0A2E4
+
+#define mmROT0_QM_CP_FENCE0_CNT_2 0x4E0A2E8
+
+#define mmROT0_QM_CP_FENCE0_CNT_3 0x4E0A2EC
+
+#define mmROT0_QM_CP_FENCE0_CNT_4 0x4E0A2F0
+
+#define mmROT0_QM_CP_FENCE1_CNT_0 0x4E0A2F4
+
+#define mmROT0_QM_CP_FENCE1_CNT_1 0x4E0A2F8
+
+#define mmROT0_QM_CP_FENCE1_CNT_2 0x4E0A2FC
+
+#define mmROT0_QM_CP_FENCE1_CNT_3 0x4E0A300
+
+#define mmROT0_QM_CP_FENCE1_CNT_4 0x4E0A304
+
+#define mmROT0_QM_CP_FENCE2_CNT_0 0x4E0A308
+
+#define mmROT0_QM_CP_FENCE2_CNT_1 0x4E0A30C
+
+#define mmROT0_QM_CP_FENCE2_CNT_2 0x4E0A310
+
+#define mmROT0_QM_CP_FENCE2_CNT_3 0x4E0A314
+
+#define mmROT0_QM_CP_FENCE2_CNT_4 0x4E0A318
+
+#define mmROT0_QM_CP_FENCE3_CNT_0 0x4E0A31C
+
+#define mmROT0_QM_CP_FENCE3_CNT_1 0x4E0A320
+
+#define mmROT0_QM_CP_FENCE3_CNT_2 0x4E0A324
+
+#define mmROT0_QM_CP_FENCE3_CNT_3 0x4E0A328
+
+#define mmROT0_QM_CP_FENCE3_CNT_4 0x4E0A32C
+
+#define mmROT0_QM_CP_BARRIER_CFG 0x4E0A330
+
+#define mmROT0_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0x4E0A334
+
+#define mmROT0_QM_CP_LDMA_DST_BASE_LO_OFFSET 0x4E0A338
+
+#define mmROT0_QM_CP_LDMA_TSIZE_OFFSET 0x4E0A33C
+
+#define mmROT0_QM_CP_CQ_PTR_LO_OFFSET_0 0x4E0A340
+
+#define mmROT0_QM_CP_CQ_PTR_LO_OFFSET_1 0x4E0A344
+
+#define mmROT0_QM_CP_CQ_PTR_LO_OFFSET_2 0x4E0A348
+
+#define mmROT0_QM_CP_CQ_PTR_LO_OFFSET_3 0x4E0A34C
+
+#define mmROT0_QM_CP_CQ_PTR_LO_OFFSET_4 0x4E0A350
+
+#define mmROT0_QM_CP_STS_0 0x4E0A368
+
+#define mmROT0_QM_CP_STS_1 0x4E0A36C
+
+#define mmROT0_QM_CP_STS_2 0x4E0A370
+
+#define mmROT0_QM_CP_STS_3 0x4E0A374
+
+#define mmROT0_QM_CP_STS_4 0x4E0A378
+
+#define mmROT0_QM_CP_CURRENT_INST_LO_0 0x4E0A37C
+
+#define mmROT0_QM_CP_CURRENT_INST_LO_1 0x4E0A380
+
+#define mmROT0_QM_CP_CURRENT_INST_LO_2 0x4E0A384
+
+#define mmROT0_QM_CP_CURRENT_INST_LO_3 0x4E0A388
+
+#define mmROT0_QM_CP_CURRENT_INST_LO_4 0x4E0A38C
+
+#define mmROT0_QM_CP_CURRENT_INST_HI_0 0x4E0A390
+
+#define mmROT0_QM_CP_CURRENT_INST_HI_1 0x4E0A394
+
+#define mmROT0_QM_CP_CURRENT_INST_HI_2 0x4E0A398
+
+#define mmROT0_QM_CP_CURRENT_INST_HI_3 0x4E0A39C
+
+#define mmROT0_QM_CP_CURRENT_INST_HI_4 0x4E0A3A0
+
+#define mmROT0_QM_CP_PRED_0 0x4E0A3A4
+
+#define mmROT0_QM_CP_PRED_1 0x4E0A3A8
+
+#define mmROT0_QM_CP_PRED_2 0x4E0A3AC
+
+#define mmROT0_QM_CP_PRED_3 0x4E0A3B0
+
+#define mmROT0_QM_CP_PRED_4 0x4E0A3B4
+
+#define mmROT0_QM_CP_PRED_UPEN_0 0x4E0A3B8
+
+#define mmROT0_QM_CP_PRED_UPEN_1 0x4E0A3BC
+
+#define mmROT0_QM_CP_PRED_UPEN_2 0x4E0A3C0
+
+#define mmROT0_QM_CP_PRED_UPEN_3 0x4E0A3C4
+
+#define mmROT0_QM_CP_PRED_UPEN_4 0x4E0A3C8
+
+#define mmROT0_QM_CP_DBG_0_0 0x4E0A3CC
+
+#define mmROT0_QM_CP_DBG_0_1 0x4E0A3D0
+
+#define mmROT0_QM_CP_DBG_0_2 0x4E0A3D4
+
+#define mmROT0_QM_CP_DBG_0_3 0x4E0A3D8
+
+#define mmROT0_QM_CP_DBG_0_4 0x4E0A3DC
+
+#define mmROT0_QM_CP_CPDMA_UP_CRED_0 0x4E0A3E0
+
+#define mmROT0_QM_CP_CPDMA_UP_CRED_1 0x4E0A3E4
+
+#define mmROT0_QM_CP_CPDMA_UP_CRED_2 0x4E0A3E8
+
+#define mmROT0_QM_CP_CPDMA_UP_CRED_3 0x4E0A3EC
+
+#define mmROT0_QM_CP_CPDMA_UP_CRED_4 0x4E0A3F0
+
+#define mmROT0_QM_CP_IN_DATA_LO_0 0x4E0A3F4
+
+#define mmROT0_QM_CP_IN_DATA_LO_1 0x4E0A3F8
+
+#define mmROT0_QM_CP_IN_DATA_LO_2 0x4E0A3FC
+
+#define mmROT0_QM_CP_IN_DATA_LO_3 0x4E0A400
+
+#define mmROT0_QM_CP_IN_DATA_LO_4 0x4E0A404
+
+#define mmROT0_QM_CP_IN_DATA_HI_0 0x4E0A408
+
+#define mmROT0_QM_CP_IN_DATA_HI_1 0x4E0A40C
+
+#define mmROT0_QM_CP_IN_DATA_HI_2 0x4E0A410
+
+#define mmROT0_QM_CP_IN_DATA_HI_3 0x4E0A414
+
+#define mmROT0_QM_CP_IN_DATA_HI_4 0x4E0A418
+
+#define mmROT0_QM_PQC_HBW_BASE_LO_0 0x4E0A41C
+
+#define mmROT0_QM_PQC_HBW_BASE_LO_1 0x4E0A420
+
+#define mmROT0_QM_PQC_HBW_BASE_LO_2 0x4E0A424
+
+#define mmROT0_QM_PQC_HBW_BASE_LO_3 0x4E0A428
+
+#define mmROT0_QM_PQC_HBW_BASE_HI_0 0x4E0A42C
+
+#define mmROT0_QM_PQC_HBW_BASE_HI_1 0x4E0A430
+
+#define mmROT0_QM_PQC_HBW_BASE_HI_2 0x4E0A434
+
+#define mmROT0_QM_PQC_HBW_BASE_HI_3 0x4E0A438
+
+#define mmROT0_QM_PQC_SIZE_0 0x4E0A43C
+
+#define mmROT0_QM_PQC_SIZE_1 0x4E0A440
+
+#define mmROT0_QM_PQC_SIZE_2 0x4E0A444
+
+#define mmROT0_QM_PQC_SIZE_3 0x4E0A448
+
+#define mmROT0_QM_PQC_PI_0 0x4E0A44C
+
+#define mmROT0_QM_PQC_PI_1 0x4E0A450
+
+#define mmROT0_QM_PQC_PI_2 0x4E0A454
+
+#define mmROT0_QM_PQC_PI_3 0x4E0A458
+
+#define mmROT0_QM_PQC_LBW_WDATA_0 0x4E0A45C
+
+#define mmROT0_QM_PQC_LBW_WDATA_1 0x4E0A460
+
+#define mmROT0_QM_PQC_LBW_WDATA_2 0x4E0A464
+
+#define mmROT0_QM_PQC_LBW_WDATA_3 0x4E0A468
+
+#define mmROT0_QM_PQC_LBW_BASE_LO_0 0x4E0A46C
+
+#define mmROT0_QM_PQC_LBW_BASE_LO_1 0x4E0A470
+
+#define mmROT0_QM_PQC_LBW_BASE_LO_2 0x4E0A474
+
+#define mmROT0_QM_PQC_LBW_BASE_LO_3 0x4E0A478
+
+#define mmROT0_QM_PQC_LBW_BASE_HI_0 0x4E0A47C
+
+#define mmROT0_QM_PQC_LBW_BASE_HI_1 0x4E0A480
+
+#define mmROT0_QM_PQC_LBW_BASE_HI_2 0x4E0A484
+
+#define mmROT0_QM_PQC_LBW_BASE_HI_3 0x4E0A488
+
+#define mmROT0_QM_PQC_CFG 0x4E0A48C
+
+#define mmROT0_QM_PQC_SECURE_PUSH_IND 0x4E0A490
+
+#define mmROT0_QM_ARB_MASK 0x4E0A4A0
+
+#define mmROT0_QM_ARB_CFG_0 0x4E0A4A4
+
+#define mmROT0_QM_ARB_CHOICE_Q_PUSH 0x4E0A4A8
+
+#define mmROT0_QM_ARB_WRR_WEIGHT_0 0x4E0A4AC
+
+#define mmROT0_QM_ARB_WRR_WEIGHT_1 0x4E0A4B0
+
+#define mmROT0_QM_ARB_WRR_WEIGHT_2 0x4E0A4B4
+
+#define mmROT0_QM_ARB_WRR_WEIGHT_3 0x4E0A4B8
+
+#define mmROT0_QM_ARB_CFG_1 0x4E0A4BC
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_0 0x4E0A4C0
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_1 0x4E0A4C4
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_2 0x4E0A4C8
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_3 0x4E0A4CC
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_4 0x4E0A4D0
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_5 0x4E0A4D4
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_6 0x4E0A4D8
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_7 0x4E0A4DC
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_8 0x4E0A4E0
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_9 0x4E0A4E4
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_10 0x4E0A4E8
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_11 0x4E0A4EC
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_12 0x4E0A4F0
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_13 0x4E0A4F4
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_14 0x4E0A4F8
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_15 0x4E0A4FC
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_16 0x4E0A500
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_17 0x4E0A504
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_18 0x4E0A508
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_19 0x4E0A50C
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_20 0x4E0A510
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_21 0x4E0A514
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_22 0x4E0A518
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_23 0x4E0A51C
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_24 0x4E0A520
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_25 0x4E0A524
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_26 0x4E0A528
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_27 0x4E0A52C
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_28 0x4E0A530
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_29 0x4E0A534
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_30 0x4E0A538
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_31 0x4E0A53C
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_32 0x4E0A540
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_33 0x4E0A544
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_34 0x4E0A548
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_35 0x4E0A54C
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_36 0x4E0A550
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_37 0x4E0A554
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_38 0x4E0A558
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_39 0x4E0A55C
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_40 0x4E0A560
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_41 0x4E0A564
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_42 0x4E0A568
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_43 0x4E0A56C
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_44 0x4E0A570
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_45 0x4E0A574
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_46 0x4E0A578
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_47 0x4E0A57C
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_48 0x4E0A580
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_49 0x4E0A584
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_50 0x4E0A588
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_51 0x4E0A58C
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_52 0x4E0A590
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_53 0x4E0A594
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_54 0x4E0A598
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_55 0x4E0A59C
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_56 0x4E0A5A0
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_57 0x4E0A5A4
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_58 0x4E0A5A8
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_59 0x4E0A5AC
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_60 0x4E0A5B0
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_61 0x4E0A5B4
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_62 0x4E0A5B8
+
+#define mmROT0_QM_ARB_MST_AVAIL_CRED_63 0x4E0A5BC
+
+#define mmROT0_QM_ARB_MST_CRED_INC 0x4E0A5E0
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_0 0x4E0A5E4
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_1 0x4E0A5E8
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_2 0x4E0A5EC
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_3 0x4E0A5F0
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_4 0x4E0A5F4
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_5 0x4E0A5F8
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_6 0x4E0A5FC
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_7 0x4E0A600
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_8 0x4E0A604
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_9 0x4E0A608
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_10 0x4E0A60C
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_11 0x4E0A610
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_12 0x4E0A614
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_13 0x4E0A618
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_14 0x4E0A61C
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_15 0x4E0A620
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_16 0x4E0A624
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_17 0x4E0A628
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_18 0x4E0A62C
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_19 0x4E0A630
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_20 0x4E0A634
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_21 0x4E0A638
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_22 0x4E0A63C
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_23 0x4E0A640
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_24 0x4E0A644
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_25 0x4E0A648
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_26 0x4E0A64C
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_27 0x4E0A650
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_28 0x4E0A654
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_29 0x4E0A658
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_30 0x4E0A65C
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_31 0x4E0A660
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_32 0x4E0A664
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_33 0x4E0A668
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_34 0x4E0A66C
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_35 0x4E0A670
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_36 0x4E0A674
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_37 0x4E0A678
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_38 0x4E0A67C
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_39 0x4E0A680
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_40 0x4E0A684
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_41 0x4E0A688
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_42 0x4E0A68C
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_43 0x4E0A690
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_44 0x4E0A694
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_45 0x4E0A698
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_46 0x4E0A69C
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_47 0x4E0A6A0
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_48 0x4E0A6A4
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_49 0x4E0A6A8
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_50 0x4E0A6AC
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_51 0x4E0A6B0
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_52 0x4E0A6B4
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_53 0x4E0A6B8
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_54 0x4E0A6BC
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_55 0x4E0A6C0
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_56 0x4E0A6C4
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_57 0x4E0A6C8
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_58 0x4E0A6CC
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_59 0x4E0A6D0
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_60 0x4E0A6D4
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_61 0x4E0A6D8
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_62 0x4E0A6DC
+
+#define mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_63 0x4E0A6E0
+
+#define mmROT0_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x4E0A704
+
+#define mmROT0_QM_ARB_MST_SLAVE_EN 0x4E0A708
+
+#define mmROT0_QM_ARB_MST_SLAVE_EN_1 0x4E0A70C
+
+#define mmROT0_QM_ARB_SLV_CHOICE_WDT 0x4E0A710
+
+#define mmROT0_QM_ARB_SLV_ID 0x4E0A714
+
+#define mmROT0_QM_ARB_MST_QUIET_PER 0x4E0A718
+
+#define mmROT0_QM_ARB_MSG_MAX_INFLIGHT 0x4E0A744
+
+#define mmROT0_QM_ARB_BASE_LO 0x4E0A754
+
+#define mmROT0_QM_ARB_BASE_HI 0x4E0A758
+
+#define mmROT0_QM_ARB_STATE_STS 0x4E0A780
+
+#define mmROT0_QM_ARB_CHOICE_FULLNESS_STS 0x4E0A784
+
+#define mmROT0_QM_ARB_MSG_STS 0x4E0A788
+
+#define mmROT0_QM_ARB_SLV_CHOICE_Q_HEAD 0x4E0A78C
+
+#define mmROT0_QM_ARB_ERR_CAUSE 0x4E0A79C
+
+#define mmROT0_QM_ARB_ERR_MSG_EN 0x4E0A7A0
+
+#define mmROT0_QM_ARB_ERR_STS_DRP 0x4E0A7A8
+
+#define mmROT0_QM_ARB_MST_CRED_STS 0x4E0A7B0
+
+#define mmROT0_QM_ARB_MST_CRED_STS_1 0x4E0A7B4
+
+#define mmROT0_QM_CSMR_STRICT_PRIO_CFG 0x4E0A7FC
+
+#define mmROT0_QM_ARC_CQ_CFG0 0x4E0A800
+
+#define mmROT0_QM_ARC_CQ_CFG1 0x4E0A804
+
+#define mmROT0_QM_ARC_CQ_PTR_LO 0x4E0A808
+
+#define mmROT0_QM_ARC_CQ_PTR_HI 0x4E0A80C
+
+#define mmROT0_QM_ARC_CQ_TSIZE 0x4E0A810
+
+#define mmROT0_QM_ARC_CQ_CTL 0x4E0A814
+
+#define mmROT0_QM_ARC_CQ_IFIFO_STS 0x4E0A81C
+
+#define mmROT0_QM_ARC_CQ_STS0 0x4E0A820
+
+#define mmROT0_QM_ARC_CQ_STS1 0x4E0A824
+
+#define mmROT0_QM_ARC_CQ_TSIZE_STS 0x4E0A828
+
+#define mmROT0_QM_ARC_CQ_PTR_LO_STS 0x4E0A82C
+
+#define mmROT0_QM_ARC_CQ_PTR_HI_STS 0x4E0A830
+
+#define mmROT0_QM_CP_WR_ARC_ADDR_HI 0x4E0A834
+
+#define mmROT0_QM_CP_WR_ARC_ADDR_LO 0x4E0A838
+
+#define mmROT0_QM_ARC_CQ_IFIFO_MSG_BASE_HI 0x4E0A83C
+
+#define mmROT0_QM_ARC_CQ_IFIFO_MSG_BASE_LO 0x4E0A840
+
+#define mmROT0_QM_ARC_CQ_CTL_MSG_BASE_HI 0x4E0A844
+
+#define mmROT0_QM_ARC_CQ_CTL_MSG_BASE_LO 0x4E0A848
+
+#define mmROT0_QM_CQ_IFIFO_MSG_BASE_HI 0x4E0A84C
+
+#define mmROT0_QM_CQ_IFIFO_MSG_BASE_LO 0x4E0A850
+
+#define mmROT0_QM_CQ_CTL_MSG_BASE_HI 0x4E0A854
+
+#define mmROT0_QM_CQ_CTL_MSG_BASE_LO 0x4E0A858
+
+#define mmROT0_QM_ADDR_OVRD 0x4E0A85C
+
+#define mmROT0_QM_CQ_IFIFO_CI_0 0x4E0A860
+
+#define mmROT0_QM_CQ_IFIFO_CI_1 0x4E0A864
+
+#define mmROT0_QM_CQ_IFIFO_CI_2 0x4E0A868
+
+#define mmROT0_QM_CQ_IFIFO_CI_3 0x4E0A86C
+
+#define mmROT0_QM_CQ_IFIFO_CI_4 0x4E0A870
+
+#define mmROT0_QM_ARC_CQ_IFIFO_CI 0x4E0A874
+
+#define mmROT0_QM_CQ_CTL_CI_0 0x4E0A878
+
+#define mmROT0_QM_CQ_CTL_CI_1 0x4E0A87C
+
+#define mmROT0_QM_CQ_CTL_CI_2 0x4E0A880
+
+#define mmROT0_QM_CQ_CTL_CI_3 0x4E0A884
+
+#define mmROT0_QM_CQ_CTL_CI_4 0x4E0A888
+
+#define mmROT0_QM_ARC_CQ_CTL_CI 0x4E0A88C
+
+#define mmROT0_QM_CP_CFG 0x4E0A890
+
+#define mmROT0_QM_CP_EXT_SWITCH 0x4E0A894
+
+#define mmROT0_QM_CP_SWITCH_WD_SET 0x4E0A898
+
+#define mmROT0_QM_CP_SWITCH_WD 0x4E0A89C
+
+#define mmROT0_QM_ARC_LB_ADDR_BASE_LO 0x4E0A8A4
+
+#define mmROT0_QM_ARC_LB_ADDR_BASE_HI 0x4E0A8A8
+
+#define mmROT0_QM_ENGINE_BASE_ADDR_HI 0x4E0A8AC
+
+#define mmROT0_QM_ENGINE_BASE_ADDR_LO 0x4E0A8B0
+
+#define mmROT0_QM_ENGINE_ADDR_RANGE_SIZE 0x4E0A8B4
+
+#define mmROT0_QM_QM_ARC_AUX_BASE_ADDR_HI 0x4E0A8B8
+
+#define mmROT0_QM_QM_ARC_AUX_BASE_ADDR_LO 0x4E0A8BC
+
+#define mmROT0_QM_QM_BASE_ADDR_HI 0x4E0A8C0
+
+#define mmROT0_QM_QM_BASE_ADDR_LO 0x4E0A8C4
+
+#define mmROT0_QM_ARC_PQC_SECURE_PUSH_IND 0x4E0A8C8
+
+#define mmROT0_QM_PQC_STS_0_0 0x4E0A8D0
+
+#define mmROT0_QM_PQC_STS_0_1 0x4E0A8D4
+
+#define mmROT0_QM_PQC_STS_0_2 0x4E0A8D8
+
+#define mmROT0_QM_PQC_STS_0_3 0x4E0A8DC
+
+#define mmROT0_QM_PQC_STS_1_0 0x4E0A8E0
+
+#define mmROT0_QM_PQC_STS_1_1 0x4E0A8E4
+
+#define mmROT0_QM_PQC_STS_1_2 0x4E0A8E8
+
+#define mmROT0_QM_PQC_STS_1_3 0x4E0A8EC
+
+#define mmROT0_QM_SEI_STATUS 0x4E0A8F0
+
+#define mmROT0_QM_SEI_MASK 0x4E0A8F4
+
+#define mmROT0_QM_GLBL_ERR_ADDR_LO 0x4E0AD00
+
+#define mmROT0_QM_GLBL_ERR_ADDR_HI 0x4E0AD04
+
+#define mmROT0_QM_GLBL_ERR_WDATA 0x4E0AD08
+
+#define mmROT0_QM_L2H_MASK_LO 0x4E0AD14
+
+#define mmROT0_QM_L2H_MASK_HI 0x4E0AD18
+
+#define mmROT0_QM_L2H_CMPR_LO 0x4E0AD1C
+
+#define mmROT0_QM_L2H_CMPR_HI 0x4E0AD20
+
+#define mmROT0_QM_LOCAL_RANGE_BASE 0x4E0AD24
+
+#define mmROT0_QM_LOCAL_RANGE_SIZE 0x4E0AD28
+
+#define mmROT0_QM_HBW_RD_RATE_LIM_CFG_1 0x4E0AD30
+
+#define mmROT0_QM_LBW_WR_RATE_LIM_CFG_0 0x4E0AD34
+
+#define mmROT0_QM_LBW_WR_RATE_LIM_CFG_1 0x4E0AD38
+
+#define mmROT0_QM_HBW_RD_RATE_LIM_CFG_0 0x4E0AD3C
+
+#define mmROT0_QM_IND_GW_APB_CFG 0x4E0AD40
+
+#define mmROT0_QM_IND_GW_APB_WDATA 0x4E0AD44
+
+#define mmROT0_QM_IND_GW_APB_RDATA 0x4E0AD48
+
+#define mmROT0_QM_IND_GW_APB_STATUS 0x4E0AD4C
+
+#define mmROT0_QM_PERF_CNT_FREE_LO 0x4E0AD60
+
+#define mmROT0_QM_PERF_CNT_FREE_HI 0x4E0AD64
+
+#define mmROT0_QM_PERF_CNT_IDLE_LO 0x4E0AD68
+
+#define mmROT0_QM_PERF_CNT_IDLE_HI 0x4E0AD6C
+
+#define mmROT0_QM_PERF_CNT_CFG 0x4E0AD70
+
+#endif /* ASIC_REG_ROT0_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/rot0_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/rot0_regs.h
new file mode 100644
index 000000000000..7d85dc5559da
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/rot0_regs.h
@@ -0,0 +1,111 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_ROT0_REGS_H_
+#define ASIC_REG_ROT0_REGS_H_
+
+/*
+ *****************************************
+ *   ROT0
+ *   (Prototype: ROTATOR)
+ *****************************************
+ */
+
+#define mmROT0_KMD_MODE 0x4E0B000
+
+#define mmROT0_CPL_QUEUE_EN 0x4E0B004
+
+#define mmROT0_CPL_QUEUE_ADDR_L 0x4E0B008
+
+#define mmROT0_CPL_QUEUE_ADDR_H 0x4E0B00C
+
+#define mmROT0_CPL_QUEUE_DATA 0x4E0B010
+
+#define mmROT0_CPL_QUEUE_AWUSER 0x4E0B014
+
+#define mmROT0_CPL_QUEUE_AXI 0x4E0B018
+
+#define mmROT0_CPL_MSG_THRESHOLD 0x4E0B020
+
+#define mmROT0_CPL_MSG_AXI 0x4E0B024
+
+#define mmROT0_AXI_WB 0x4E0B028
+
+#define mmROT0_ERR_CFG 0x4E0B02C
+
+#define mmROT0_ERR_STATUS 0x4E0B030
+
+#define mmROT0_WBC_MAX_OUTSTANDING 0x4E0B038
+
+#define mmROT0_WBC_RL 0x4E0B03C
+
+#define mmROT0_WBC_INFLIGHTS 0x4E0B040
+
+#define mmROT0_WBC_INFO 0x4E0B044
+
+#define mmROT0_WBC_MON 0x4E0B048
+
+#define mmROT0_RSB_CAM_MAX_SIZE 0x4E0B04C
+
+#define mmROT0_RSB_CFG 0x4E0B050
+
+#define mmROT0_RSB_MAX_OS 0x4E0B054
+
+#define mmROT0_RSB_RL 0x4E0B058
+
+#define mmROT0_RSB_INFLIGHTS 0x4E0B05C
+
+#define mmROT0_RSB_OCCUPANCY 0x4E0B060
+
+#define mmROT0_RSB_INFO 0x4E0B064
+
+#define mmROT0_RSB_MON 0x4E0B068
+
+#define mmROT0_RSB_MON_CONTEXT_ID 0x4E0B06C
+
+#define mmROT0_MSS_HALT 0x4E0B070
+
+#define mmROT0_MSS_SEI_STATUS 0x4E0B074
+
+#define mmROT0_MSS_SEI_MASK 0x4E0B078
+
+#define mmROT0_MSS_SPI_STATUS 0x4E0B07C
+
+#define mmROT0_MSS_SPI_MASK 0x4E0B080
+
+#define mmROT0_DISABLE_PAD_CALC 0x4E0B084
+
+#define mmROT0_QMAN_CFG 0x4E0B088
+
+#define mmROT0_CLK_EN 0x4E0B08C
+
+#define mmROT0_MRSB_CAM_MAX_SIZE 0x4E0B090
+
+#define mmROT0_MRSB_CFG 0x4E0B094
+
+#define mmROT0_MRSB_MAX_OS 0x4E0B098
+
+#define mmROT0_MRSB_RL 0x4E0B09C
+
+#define mmROT0_MRSB_INFLIGHTS 0x4E0B0A0
+
+#define mmROT0_MRSB_OCCUPANCY 0x4E0B0A4
+
+#define mmROT0_MRSB_INFO 0x4E0B0A8
+
+#define mmROT0_MRSB_MON 0x4E0B0AC
+
+#define mmROT0_MRSB_MON_CONTEXT_ID 0x4E0B0B0
+
+#define mmROT0_MSS_STS 0x4E0B0B4
+
+#endif /* ASIC_REG_ROT0_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/xbar_edge_0_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/xbar_edge_0_regs.h
new file mode 100644
index 000000000000..e8aebd7f5f85
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/xbar_edge_0_regs.h
@@ -0,0 +1,199 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_XBAR_EDGE_0_REGS_H_
+#define ASIC_REG_XBAR_EDGE_0_REGS_H_
+
+/*
+ *****************************************
+ *   XBAR_EDGE_0
+ *   (Prototype: XBAR)
+ *****************************************
+ */
+
+#define mmXBAR_EDGE_0_LBW_HIF0_BASE_ADDR 0x4D48000
+
+#define mmXBAR_EDGE_0_LBW_HIF0_ADDR_MASK 0x4D48004
+
+#define mmXBAR_EDGE_0_LBW_HIF1_BASE_ADDR 0x4D48008
+
+#define mmXBAR_EDGE_0_LBW_HIF1_ADDR_MASK 0x4D4800C
+
+#define mmXBAR_EDGE_0_LBW_HMMU0_BASE_ADDR 0x4D48010
+
+#define mmXBAR_EDGE_0_LBW_HMMU0_ADDR_MASK 0x4D48014
+
+#define mmXBAR_EDGE_0_LBW_HMMU1_BASE_ADDR 0x4D48018
+
+#define mmXBAR_EDGE_0_LBW_HMMU1_ADDR_MASK 0x4D4801C
+
+#define mmXBAR_EDGE_0_LBW_EDMA_BASE_ADDR0 0x4D48020
+
+#define mmXBAR_EDGE_0_LBW_EDMA_ADDR_MASK0 0x4D48024
+
+#define mmXBAR_EDGE_0_LBW_EDMA_BASE_ADDR1 0x4D48028
+
+#define mmXBAR_EDGE_0_LBW_EDMA_ADDR_MASK1 0x4D4802C
+
+#define mmXBAR_EDGE_0_LBW_HBM_BASE_ADDR0 0x4D48030
+
+#define mmXBAR_EDGE_0_LBW_HBM_ADDR_MASK0 0x4D48034
+
+#define mmXBAR_EDGE_0_LBW_HBM_BASE_ADDR1 0x4D48038
+
+#define mmXBAR_EDGE_0_LBW_HBM_ADDR_MASK1 0x4D4803C
+
+#define mmXBAR_EDGE_0_LBW_XBAR_BASE_ADDR0 0x4D48040
+
+#define mmXBAR_EDGE_0_LBW_XBAR_ADDR_MASK0 0x4D48044
+
+#define mmXBAR_EDGE_0_LBW_XBAR_BASE_ADDR1 0x4D48048
+
+#define mmXBAR_EDGE_0_LBW_XBAR_ADDR_MASK1 0x4D4804C
+
+#define mmXBAR_EDGE_0_DBG_HIF0_BASE_ADDR 0x4D48080
+
+#define mmXBAR_EDGE_0_DBG_HIF0_ADDR_MASK 0x4D48084
+
+#define mmXBAR_EDGE_0_DBG_HIF1_BASE_ADDR 0x4D48088
+
+#define mmXBAR_EDGE_0_DBG_HIF1_ADDR_MASK 0x4D4808C
+
+#define mmXBAR_EDGE_0_DBG_HMMU0_BASE_ADDR 0x4D48090
+
+#define mmXBAR_EDGE_0_DBG_HMMU0_ADDR_MASK 0x4D48094
+
+#define mmXBAR_EDGE_0_DBG_HMMU1_BASE_ADDR 0x4D48098
+
+#define mmXBAR_EDGE_0_DBG_HMMU1_ADDR_MASK 0x4D4809C
+
+#define mmXBAR_EDGE_0_DBG_EDMA_BASE_ADDR0 0x4D480A0
+
+#define mmXBAR_EDGE_0_DBG_EDMA_ADDR_MASK0 0x4D480A4
+
+#define mmXBAR_EDGE_0_DBG_EDMA_BASE_ADDR1 0x4D480A8
+
+#define mmXBAR_EDGE_0_DBG_EDMA_ADDR_MASK1 0x4D480AC
+
+#define mmXBAR_EDGE_0_DBG_HBM_BASE_ADDR0 0x4D480B0
+
+#define mmXBAR_EDGE_0_DBG_HBM_ADDR_MASK0 0x4D480B4
+
+#define mmXBAR_EDGE_0_DBG_HBM_BASE_ADDR1 0x4D480B8
+
+#define mmXBAR_EDGE_0_DBG_HBM_ADDR_MASK1 0x4D480BC
+
+#define mmXBAR_EDGE_0_DBG_XBAR_BASE_ADDR0 0x4D480C0
+
+#define mmXBAR_EDGE_0_DBG_XBAR_ADDR_MASK0 0x4D480C4
+
+#define mmXBAR_EDGE_0_DBG_XBAR_BASE_ADDR1 0x4D480C8
+
+#define mmXBAR_EDGE_0_DBG_XBAR_ADDR_MASK1 0x4D480CC
+
+#define mmXBAR_EDGE_0_LBW_INTERNAL_ADDR_RGF 0x4D480D0
+
+#define mmXBAR_EDGE_0_DBG_INTERNAL_ADDR_FUN 0x4D480D4
+
+#define mmXBAR_EDGE_0_EMEM_HBM_BIT_LOCATION 0x4D48100
+
+#define mmXBAR_EDGE_0_EMEM_PC_BIT_LOCATION 0x4D48104
+
+#define mmXBAR_EDGE_0_HIF_WR_RS_CH_LOCATION 0x4D48108
+
+#define mmXBAR_EDGE_0_HBW_MST_ARB_WEIGHT 0x4D4810C
+
+#define mmXBAR_EDGE_0_MMU_PC_IDX_MAP_0 0x4D48110
+
+#define mmXBAR_EDGE_0_MMU_PC_IDX_MAP_1 0x4D48114
+
+#define mmXBAR_EDGE_0_MMU_RD_LL_ARB_0 0x4D48120
+
+#define mmXBAR_EDGE_0_MMU_RD_LL_ARB_1 0x4D48124
+
+#define mmXBAR_EDGE_0_MMU_WR_LL_ARB_0 0x4D48128
+
+#define mmXBAR_EDGE_0_MMU_WR_LL_ARB_1 0x4D4812C
+
+#define mmXBAR_EDGE_0_HBM_USER_RESP_OVR_0 0x4D48130
+
+#define mmXBAR_EDGE_0_HBM_USER_RESP_OVR_1 0x4D48134
+
+#define mmXBAR_EDGE_0_RL_RD_0 0x4D48140
+
+#define mmXBAR_EDGE_0_RL_RD_1 0x4D48144
+
+#define mmXBAR_EDGE_0_RL_RD_2 0x4D48148
+
+#define mmXBAR_EDGE_0_RL_RD_3 0x4D4814C
+
+#define mmXBAR_EDGE_0_RL_RD_4 0x4D48150
+
+#define mmXBAR_EDGE_0_RL_RD_5 0x4D48154
+
+#define mmXBAR_EDGE_0_RL_RD_6 0x4D48158
+
+#define mmXBAR_EDGE_0_RL_RD_7 0x4D4815C
+
+#define mmXBAR_EDGE_0_RL_RD_8 0x4D48160
+
+#define mmXBAR_EDGE_0_RL_RD_9 0x4D48164
+
+#define mmXBAR_EDGE_0_RL_RD_10 0x4D48168
+
+#define mmXBAR_EDGE_0_RL_RD_11 0x4D4816C
+
+#define mmXBAR_EDGE_0_RL_WR_0 0x4D48180
+
+#define mmXBAR_EDGE_0_RL_WR_1 0x4D48184
+
+#define mmXBAR_EDGE_0_RL_WR_2 0x4D48188
+
+#define mmXBAR_EDGE_0_RL_WR_3 0x4D4818C
+
+#define mmXBAR_EDGE_0_RL_WR_4 0x4D48190
+
+#define mmXBAR_EDGE_0_RL_WR_5 0x4D48194
+
+#define mmXBAR_EDGE_0_RL_WR_6 0x4D48198
+
+#define mmXBAR_EDGE_0_RL_WR_7 0x4D4819C
+
+#define mmXBAR_EDGE_0_RL_WR_8 0x4D481A0
+
+#define mmXBAR_EDGE_0_RL_WR_9 0x4D481A4
+
+#define mmXBAR_EDGE_0_RL_WR_10 0x4D481A8
+
+#define mmXBAR_EDGE_0_RL_WR_11 0x4D481AC
+
+#define mmXBAR_EDGE_0_E2E_CRDT_SLV_0 0x4D481B0
+
+#define mmXBAR_EDGE_0_E2E_CRDT_SLV_1 0x4D481B4
+
+#define mmXBAR_EDGE_0_E2E_CRDT_SLV_2 0x4D481B8
+
+#define mmXBAR_EDGE_0_E2E_CRDT_DEBUG 0x4D481BC
+
+#define mmXBAR_EDGE_0_UPSCALE 0x4D481C0
+
+#define mmXBAR_EDGE_0_DOWN_CONV 0x4D481C4
+
+#define mmXBAR_EDGE_0_DOWN_CONV_LFSR_EN 0x4D481D0
+
+#define mmXBAR_EDGE_0_DOWN_CONV_LFSR_SET_VLD 0x4D481D4
+
+#define mmXBAR_EDGE_0_DOWN_CONV_LFSR_SET_VALUE 0x4D481D8
+
+#define mmXBAR_EDGE_0_DOWN_CONV_LFSR_CFG_POLY 0x4D481DC
+
+#endif /* ASIC_REG_XBAR_EDGE_0_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/xbar_mid_0_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/xbar_mid_0_regs.h
new file mode 100644
index 000000000000..3d39d1a94851
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/xbar_mid_0_regs.h
@@ -0,0 +1,199 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_XBAR_MID_0_REGS_H_
+#define ASIC_REG_XBAR_MID_0_REGS_H_
+
+/*
+ *****************************************
+ *   XBAR_MID_0
+ *   (Prototype: XBAR)
+ *****************************************
+ */
+
+#define mmXBAR_MID_0_LBW_HIF0_BASE_ADDR 0x4D40000
+
+#define mmXBAR_MID_0_LBW_HIF0_ADDR_MASK 0x4D40004
+
+#define mmXBAR_MID_0_LBW_HIF1_BASE_ADDR 0x4D40008
+
+#define mmXBAR_MID_0_LBW_HIF1_ADDR_MASK 0x4D4000C
+
+#define mmXBAR_MID_0_LBW_HMMU0_BASE_ADDR 0x4D40010
+
+#define mmXBAR_MID_0_LBW_HMMU0_ADDR_MASK 0x4D40014
+
+#define mmXBAR_MID_0_LBW_HMMU1_BASE_ADDR 0x4D40018
+
+#define mmXBAR_MID_0_LBW_HMMU1_ADDR_MASK 0x4D4001C
+
+#define mmXBAR_MID_0_LBW_EDMA_BASE_ADDR0 0x4D40020
+
+#define mmXBAR_MID_0_LBW_EDMA_ADDR_MASK0 0x4D40024
+
+#define mmXBAR_MID_0_LBW_EDMA_BASE_ADDR1 0x4D40028
+
+#define mmXBAR_MID_0_LBW_EDMA_ADDR_MASK1 0x4D4002C
+
+#define mmXBAR_MID_0_LBW_HBM_BASE_ADDR0 0x4D40030
+
+#define mmXBAR_MID_0_LBW_HBM_ADDR_MASK0 0x4D40034
+
+#define mmXBAR_MID_0_LBW_HBM_BASE_ADDR1 0x4D40038
+
+#define mmXBAR_MID_0_LBW_HBM_ADDR_MASK1 0x4D4003C
+
+#define mmXBAR_MID_0_LBW_XBAR_BASE_ADDR0 0x4D40040
+
+#define mmXBAR_MID_0_LBW_XBAR_ADDR_MASK0 0x4D40044
+
+#define mmXBAR_MID_0_LBW_XBAR_BASE_ADDR1 0x4D40048
+
+#define mmXBAR_MID_0_LBW_XBAR_ADDR_MASK1 0x4D4004C
+
+#define mmXBAR_MID_0_DBG_HIF0_BASE_ADDR 0x4D40080
+
+#define mmXBAR_MID_0_DBG_HIF0_ADDR_MASK 0x4D40084
+
+#define mmXBAR_MID_0_DBG_HIF1_BASE_ADDR 0x4D40088
+
+#define mmXBAR_MID_0_DBG_HIF1_ADDR_MASK 0x4D4008C
+
+#define mmXBAR_MID_0_DBG_HMMU0_BASE_ADDR 0x4D40090
+
+#define mmXBAR_MID_0_DBG_HMMU0_ADDR_MASK 0x4D40094
+
+#define mmXBAR_MID_0_DBG_HMMU1_BASE_ADDR 0x4D40098
+
+#define mmXBAR_MID_0_DBG_HMMU1_ADDR_MASK 0x4D4009C
+
+#define mmXBAR_MID_0_DBG_EDMA_BASE_ADDR0 0x4D400A0
+
+#define mmXBAR_MID_0_DBG_EDMA_ADDR_MASK0 0x4D400A4
+
+#define mmXBAR_MID_0_DBG_EDMA_BASE_ADDR1 0x4D400A8
+
+#define mmXBAR_MID_0_DBG_EDMA_ADDR_MASK1 0x4D400AC
+
+#define mmXBAR_MID_0_DBG_HBM_BASE_ADDR0 0x4D400B0
+
+#define mmXBAR_MID_0_DBG_HBM_ADDR_MASK0 0x4D400B4
+
+#define mmXBAR_MID_0_DBG_HBM_BASE_ADDR1 0x4D400B8
+
+#define mmXBAR_MID_0_DBG_HBM_ADDR_MASK1 0x4D400BC
+
+#define mmXBAR_MID_0_DBG_XBAR_BASE_ADDR0 0x4D400C0
+
+#define mmXBAR_MID_0_DBG_XBAR_ADDR_MASK0 0x4D400C4
+
+#define mmXBAR_MID_0_DBG_XBAR_BASE_ADDR1 0x4D400C8
+
+#define mmXBAR_MID_0_DBG_XBAR_ADDR_MASK1 0x4D400CC
+
+#define mmXBAR_MID_0_LBW_INTERNAL_ADDR_RGF 0x4D400D0
+
+#define mmXBAR_MID_0_DBG_INTERNAL_ADDR_FUN 0x4D400D4
+
+#define mmXBAR_MID_0_EMEM_HBM_BIT_LOCATION 0x4D40100
+
+#define mmXBAR_MID_0_EMEM_PC_BIT_LOCATION 0x4D40104
+
+#define mmXBAR_MID_0_HIF_WR_RS_CH_LOCATION 0x4D40108
+
+#define mmXBAR_MID_0_HBW_MST_ARB_WEIGHT 0x4D4010C
+
+#define mmXBAR_MID_0_MMU_PC_IDX_MAP_0 0x4D40110
+
+#define mmXBAR_MID_0_MMU_PC_IDX_MAP_1 0x4D40114
+
+#define mmXBAR_MID_0_MMU_RD_LL_ARB_0 0x4D40120
+
+#define mmXBAR_MID_0_MMU_RD_LL_ARB_1 0x4D40124
+
+#define mmXBAR_MID_0_MMU_WR_LL_ARB_0 0x4D40128
+
+#define mmXBAR_MID_0_MMU_WR_LL_ARB_1 0x4D4012C
+
+#define mmXBAR_MID_0_HBM_USER_RESP_OVR_0 0x4D40130
+
+#define mmXBAR_MID_0_HBM_USER_RESP_OVR_1 0x4D40134
+
+#define mmXBAR_MID_0_RL_RD_0 0x4D40140
+
+#define mmXBAR_MID_0_RL_RD_1 0x4D40144
+
+#define mmXBAR_MID_0_RL_RD_2 0x4D40148
+
+#define mmXBAR_MID_0_RL_RD_3 0x4D4014C
+
+#define mmXBAR_MID_0_RL_RD_4 0x4D40150
+
+#define mmXBAR_MID_0_RL_RD_5 0x4D40154
+
+#define mmXBAR_MID_0_RL_RD_6 0x4D40158
+
+#define mmXBAR_MID_0_RL_RD_7 0x4D4015C
+
+#define mmXBAR_MID_0_RL_RD_8 0x4D40160
+
+#define mmXBAR_MID_0_RL_RD_9 0x4D40164
+
+#define mmXBAR_MID_0_RL_RD_10 0x4D40168
+
+#define mmXBAR_MID_0_RL_RD_11 0x4D4016C
+
+#define mmXBAR_MID_0_RL_WR_0 0x4D40180
+
+#define mmXBAR_MID_0_RL_WR_1 0x4D40184
+
+#define mmXBAR_MID_0_RL_WR_2 0x4D40188
+
+#define mmXBAR_MID_0_RL_WR_3 0x4D4018C
+
+#define mmXBAR_MID_0_RL_WR_4 0x4D40190
+
+#define mmXBAR_MID_0_RL_WR_5 0x4D40194
+
+#define mmXBAR_MID_0_RL_WR_6 0x4D40198
+
+#define mmXBAR_MID_0_RL_WR_7 0x4D4019C
+
+#define mmXBAR_MID_0_RL_WR_8 0x4D401A0
+
+#define mmXBAR_MID_0_RL_WR_9 0x4D401A4
+
+#define mmXBAR_MID_0_RL_WR_10 0x4D401A8
+
+#define mmXBAR_MID_0_RL_WR_11 0x4D401AC
+
+#define mmXBAR_MID_0_E2E_CRDT_SLV_0 0x4D401B0
+
+#define mmXBAR_MID_0_E2E_CRDT_SLV_1 0x4D401B4
+
+#define mmXBAR_MID_0_E2E_CRDT_SLV_2 0x4D401B8
+
+#define mmXBAR_MID_0_E2E_CRDT_DEBUG 0x4D401BC
+
+#define mmXBAR_MID_0_UPSCALE 0x4D401C0
+
+#define mmXBAR_MID_0_DOWN_CONV 0x4D401C4
+
+#define mmXBAR_MID_0_DOWN_CONV_LFSR_EN 0x4D401D0
+
+#define mmXBAR_MID_0_DOWN_CONV_LFSR_SET_VLD 0x4D401D4
+
+#define mmXBAR_MID_0_DOWN_CONV_LFSR_SET_VALUE 0x4D401D8
+
+#define mmXBAR_MID_0_DOWN_CONV_LFSR_CFG_POLY 0x4D401DC
+
+#endif /* ASIC_REG_XBAR_MID_0_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/gaudi2.h b/drivers/accel/habanalabs/include/gaudi2/gaudi2.h
new file mode 100644
index 000000000000..753d46a2836b
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/gaudi2.h
@@ -0,0 +1,125 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020-2022 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+#ifndef GAUDI2_H
+#define GAUDI2_H
+
+#define SRAM_CFG_BAR_ID		0
+#define MSIX_BAR_ID		2
+#define DRAM_BAR_ID		4
+
+/* Refers to CFG_REGION_SIZE, BAR0_RSRVD_SIZE and SRAM_SIZE */
+#define CFG_BAR_SIZE		0x10000000ull		/* 256MB */
+
+#define MSIX_BAR_SIZE		0x4000ull		/* 16KB */
+
+#define CFG_BASE		0x1000007FF8000000ull
+#define CFG_SIZE		0x8000000ull		/* 96MB CFG + 32MB DBG*/
+#define CFG_REGION_SIZE		0xC000000ull		/* 192MB */
+
+#define STM_FLASH_BASE_ADDR	0x1000007FF4000000ull	/* Not 256MB aligned */
+#define STM_FLASH_ALIGNED_OFF	0x4000000ull		/* 256 MB alignment */
+#define STM_FLASH_SIZE		0x2000000ull		/* 32MB */
+
+#define SPI_FLASH_BASE_ADDR	0x1000007FF6000000ull
+#define SPI_FLASH_SIZE		0x1000000ull		/* 16MB */
+
+#define SCRATCHPAD_SRAM_ADDR	0x1000007FF7FE0000ull
+#define SCRATCHPAD_SRAM_SIZE	0x10000ull		/* 64KB */
+
+#define PCIE_FW_SRAM_ADDR	0x1000007FF7FF0000ull
+#define PCIE_FW_SRAM_SIZE	0x8000			/* 32KB */
+
+#define BAR0_RSRVD_BASE_ADDR	0x1000FFFFFC000000ull
+#define BAR0_RSRVD_SIZE		0x1000000ull		/* 16MB */
+
+#define SRAM_BASE_ADDR		0x1000FFFFFD000000ull
+#define SRAM_SIZE		0x3000000ull		/* 48MB */
+
+#define DRAM_PHYS_BASE		0x1001000000000000ull
+
+/* every hint address is masked accordingly */
+#define DRAM_VA_HINT_MASK	0xFFFFFFFFFFFFull	/* 48bit mask */
+
+#define HOST_PHYS_BASE_0	0x0000000000000000ull
+#define HOST_PHYS_SIZE_0	0x0100000000000000ull	/* 64PB (56 bits) */
+
+#define HOST_PHYS_BASE_1	0xFF00000000000000ull
+#define HOST_PHYS_SIZE_1	0x0100000000000000ull	/* 64PB (56 bits) */
+
+#define RESERVED_VA_RANGE_FOR_ARC_ON_HBM_START	0x1001500000000000ull
+#define RESERVED_VA_RANGE_FOR_ARC_ON_HBM_END	0x10016FFFFFFFFFFFull
+
+#define RESERVED_VA_FOR_VIRTUAL_MSIX_DOORBELL_START	0xFFF077FFFFFF0000ull
+#define RESERVED_VA_FOR_VIRTUAL_MSIX_DOORBELL_END	0xFFF077FFFFFFFFFFull
+
+#define RESERVED_VA_RANGE_FOR_ARC_ON_HOST_START	0xFFF0780000000000ull
+#define RESERVED_VA_RANGE_FOR_ARC_ON_HOST_END	0xFFF07FFFFFFFFFFFull
+
+#define RESERVED_VA_RANGE_FOR_ARC_ON_HOST_HPAGE_START	0xFFF0F80000000000ull
+#define RESERVED_VA_RANGE_FOR_ARC_ON_HOST_HPAGE_END	0xFFF0FFFFFFFFFFFFull
+
+#define RESERVED_MSIX_UNEXPECTED_USER_ERROR_INTERRUPT	127
+
+#define GAUDI2_MSIX_ENTRIES	128
+
+#define QMAN_PQ_ENTRY_SIZE	16			/* Bytes */
+
+#define MAX_ASID		2
+
+#define NUM_ARC_CPUS			69
+
+/* Every ARC cpu in the system contains a single DCCM block
+ * except MME and Scheduler ARCs which contain 2 DCCM blocks
+ */
+#define ARC_DCCM_BLOCK_SIZE		0x8000
+
+#define NUM_OF_DCORES			4
+#define NUM_OF_SFT			4
+#define NUM_OF_PSOC_ARC			2
+#define NUM_OF_SCHEDULER_ARC		6
+
+#define NUM_OF_PQ_PER_QMAN		4
+#define NUM_OF_CQ_PER_QMAN		5
+#define NUM_OF_CP_PER_QMAN		5
+#define NUM_OF_EDMA_PER_DCORE		2
+#define NUM_OF_HIF_PER_DCORE		4
+#define NUM_OF_PDMA			2
+#define NUM_OF_TPC_PER_DCORE		6
+#define NUM_DCORE0_TPC			7
+#define NUM_DCORE1_TPC			NUM_OF_TPC_PER_DCORE
+#define NUM_DCORE2_TPC			NUM_OF_TPC_PER_DCORE
+#define NUM_DCORE3_TPC			NUM_OF_TPC_PER_DCORE
+#define NUM_OF_DEC_PER_DCORE		2
+#define NUM_OF_ROT			2
+#define NUM_OF_HMMU_PER_DCORE		4
+#define NUM_OF_MME_PER_DCORE		1
+#define NUM_OF_MME_SBTE_PER_DCORE	5
+#define NUM_OF_MME_WB_PER_DCORE		2
+#define NUM_OF_RTR_PER_DCORE		8
+#define NUM_OF_VDEC_PER_DCORE		2
+#define NUM_OF_IF_RTR_PER_SFT		3
+#define NUM_OF_PCIE_VDEC		2
+#define NUM_OF_ARC_FARMS_ARC		4
+#define NUM_OF_XBAR			4
+
+#define TPC_NUM_OF_KERNEL_TENSORS	16
+#define TPC_NUM_OF_QM_TENSORS		16
+
+#define MME_NUM_OF_LFSR_SEEDS		256
+
+#define NIC_NUMBER_OF_MACROS		12
+
+#define NIC_NUMBER_OF_QM_PER_MACRO	2
+
+#define NIC_NUMBER_OF_ENGINES		(NIC_NUMBER_OF_MACROS * 2)
+
+#define NIC_MAX_NUMBER_OF_PORTS		(NIC_NUMBER_OF_ENGINES * 2)
+
+#define DEVICE_CACHE_LINE_SIZE		128
+
+#endif /* GAUDI2_H */
diff --git a/drivers/accel/habanalabs/include/gaudi2/gaudi2_async_events.h b/drivers/accel/habanalabs/include/gaudi2/gaudi2_async_events.h
new file mode 100644
index 000000000000..a426410139af
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/gaudi2_async_events.h
@@ -0,0 +1,972 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2018-2022 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef __GAUDI2_ASYNC_EVENTS_H_
+#define __GAUDI2_ASYNC_EVENTS_H_
+
+enum gaudi2_async_event_id {
+	GAUDI2_EVENT_PCIE_CORE_SERR = 32,
+	GAUDI2_EVENT_PCIE_CORE_DERR = 33,
+	GAUDI2_EVENT_PCIE_IF_SERR = 34,
+	GAUDI2_EVENT_PCIE_IF_DERR = 35,
+	GAUDI2_EVENT_PCIE_PHY_SERR = 36,
+	GAUDI2_EVENT_PCIE_PHY_DERR = 37,
+	GAUDI2_EVENT_TPC0_ECC_SERR = 38,
+	GAUDI2_EVENT_TPC1_ECC_SERR = 39,
+	GAUDI2_EVENT_TPC2_ECC_SERR = 40,
+	GAUDI2_EVENT_TPC3_ECC_SERR = 41,
+	GAUDI2_EVENT_TPC4_ECC_SERR = 42,
+	GAUDI2_EVENT_TPC5_ECC_SERR = 43,
+	GAUDI2_EVENT_TPC6_ECC_SERR = 44,
+	GAUDI2_EVENT_TPC7_ECC_SERR = 45,
+	GAUDI2_EVENT_TPC8_ECC_SERR = 46,
+	GAUDI2_EVENT_TPC9_ECC_SERR = 47,
+	GAUDI2_EVENT_TPC10_ECC_SERR = 48,
+	GAUDI2_EVENT_TPC11_ECC_SERR = 49,
+	GAUDI2_EVENT_TPC12_ECC_SERR = 50,
+	GAUDI2_EVENT_TPC13_ECC_SERR = 51,
+	GAUDI2_EVENT_TPC14_ECC_SERR = 52,
+	GAUDI2_EVENT_TPC15_ECC_SERR = 53,
+	GAUDI2_EVENT_TPC16_ECC_SERR = 54,
+	GAUDI2_EVENT_TPC17_ECC_SERR = 55,
+	GAUDI2_EVENT_TPC18_ECC_SERR = 56,
+	GAUDI2_EVENT_TPC19_ECC_SERR = 57,
+	GAUDI2_EVENT_TPC20_ECC_SERR = 58,
+	GAUDI2_EVENT_TPC21_ECC_SERR = 59,
+	GAUDI2_EVENT_TPC22_ECC_SERR = 60,
+	GAUDI2_EVENT_TPC23_ECC_SERR = 61,
+	GAUDI2_EVENT_TPC24_ECC_SERR = 62,
+	GAUDI2_EVENT_TPC0_ECC_DERR = 63,
+	GAUDI2_EVENT_TPC1_ECC_DERR = 64,
+	GAUDI2_EVENT_TPC2_ECC_DERR = 65,
+	GAUDI2_EVENT_TPC3_ECC_DERR = 66,
+	GAUDI2_EVENT_TPC4_ECC_DERR = 67,
+	GAUDI2_EVENT_TPC5_ECC_DERR = 68,
+	GAUDI2_EVENT_TPC6_ECC_DERR = 69,
+	GAUDI2_EVENT_TPC7_ECC_DERR = 70,
+	GAUDI2_EVENT_TPC8_ECC_DERR = 71,
+	GAUDI2_EVENT_TPC9_ECC_DERR = 72,
+	GAUDI2_EVENT_TPC10_ECC_DERR = 73,
+	GAUDI2_EVENT_TPC11_ECC_DERR = 74,
+	GAUDI2_EVENT_TPC12_ECC_DERR = 75,
+	GAUDI2_EVENT_TPC13_ECC_DERR = 76,
+	GAUDI2_EVENT_TPC14_ECC_DERR = 77,
+	GAUDI2_EVENT_TPC15_ECC_DERR = 78,
+	GAUDI2_EVENT_TPC16_ECC_DERR = 79,
+	GAUDI2_EVENT_TPC17_ECC_DERR = 80,
+	GAUDI2_EVENT_TPC18_ECC_DERR = 81,
+	GAUDI2_EVENT_TPC19_ECC_DERR = 82,
+	GAUDI2_EVENT_TPC20_ECC_DERR = 83,
+	GAUDI2_EVENT_TPC21_ECC_DERR = 84,
+	GAUDI2_EVENT_TPC22_ECC_DERR = 85,
+	GAUDI2_EVENT_TPC23_ECC_DERR = 86,
+	GAUDI2_EVENT_TPC24_ECC_DERR = 87,
+	GAUDI2_EVENT_MME0_SBTE0_ECC_SERR = 88,
+	GAUDI2_EVENT_MME0_SBTE1_ECC_SERR = 89,
+	GAUDI2_EVENT_MME0_SBTE2_ECC_SERR = 90,
+	GAUDI2_EVENT_MME0_SBTE3_ECC_SERR = 91,
+	GAUDI2_EVENT_MME0_SBTE4_ECC_SERR = 92,
+	GAUDI2_EVENT_MME0_CTRL_ECC_SERR = 93,
+	GAUDI2_EVENT_MME0_WAP_ECC_SERR = 94,
+	GAUDI2_EVENT_MME1_SBTE0_ECC_SERR = 95,
+	GAUDI2_EVENT_MME1_SBTE1_ECC_SERR = 96,
+	GAUDI2_EVENT_MME1_SBTE2_ECC_SERR = 97,
+	GAUDI2_EVENT_MME1_SBTE3_ECC_SERR = 98,
+	GAUDI2_EVENT_MME1_SBTE4_ECC_SERR = 99,
+	GAUDI2_EVENT_MME1_CTRL_ECC_SERR = 100,
+	GAUDI2_EVENT_MME1_WAP_ECC_SERR = 101,
+	GAUDI2_EVENT_MME2_SBTE0_ECC_SERR = 102,
+	GAUDI2_EVENT_MME2_SBTE1_ECC_SERR = 103,
+	GAUDI2_EVENT_MME2_SBTE2_ECC_SERR = 104,
+	GAUDI2_EVENT_MME2_SBTE3_ECC_SERR = 105,
+	GAUDI2_EVENT_MME2_SBTE4_ECC_SERR = 106,
+	GAUDI2_EVENT_MME2_CTRL_ECC_SERR = 107,
+	GAUDI2_EVENT_MME2_WAP_ECC_SERR = 108,
+	GAUDI2_EVENT_MME3_SBTE0_ECC_SERR = 109,
+	GAUDI2_EVENT_MME3_SBTE1_ECC_SERR = 110,
+	GAUDI2_EVENT_MME3_SBTE2_ECC_SERR = 111,
+	GAUDI2_EVENT_MME3_SBTE3_ECC_SERR = 112,
+	GAUDI2_EVENT_MME3_SBTE4_ECC_SERR = 113,
+	GAUDI2_EVENT_MME3_CTRL_ECC_SERR = 114,
+	GAUDI2_EVENT_MME3_WAP_ECC_SERR = 115,
+	GAUDI2_EVENT_MME0_SBTE0_ECC_DERR = 116,
+	GAUDI2_EVENT_MME0_SBTE1_ECC_DERR = 117,
+	GAUDI2_EVENT_MME0_SBTE2_ECC_DERR = 118,
+	GAUDI2_EVENT_MME0_SBTE3_ECC_DERR = 119,
+	GAUDI2_EVENT_MME0_SBTE4_ECC_DERR = 120,
+	GAUDI2_EVENT_MME0_CTRL_ECC_DERR = 121,
+	GAUDI2_EVENT_MME0_WAP_ECC_DERR = 122,
+	GAUDI2_EVENT_MME1_SBTE0_ECC_DERR = 123,
+	GAUDI2_EVENT_MME1_SBTE1_ECC_DERR = 124,
+	GAUDI2_EVENT_MME1_SBTE2_ECC_DERR = 125,
+	GAUDI2_EVENT_MME1_SBTE3_ECC_DERR = 126,
+	GAUDI2_EVENT_MME1_SBTE4_ECC_DERR = 127,
+	GAUDI2_EVENT_MME1_CTRL_ECC_DERR = 128,
+	GAUDI2_EVENT_MME1_WAP_ECC_DERR = 129,
+	GAUDI2_EVENT_MME2_SBTE0_ECC_DERR = 130,
+	GAUDI2_EVENT_MME2_SBTE1_ECC_DERR = 131,
+	GAUDI2_EVENT_MME2_SBTE2_ECC_DERR = 132,
+	GAUDI2_EVENT_MME2_SBTE3_ECC_DERR = 133,
+	GAUDI2_EVENT_MME2_SBTE4_ECC_DERR = 134,
+	GAUDI2_EVENT_MME2_CTRL_ECC_DERR = 135,
+	GAUDI2_EVENT_MME2_WAP_ECC_DERR = 136,
+	GAUDI2_EVENT_MME3_SBTE0_ECC_DERR = 137,
+	GAUDI2_EVENT_MME3_SBTE1_ECC_DERR = 138,
+	GAUDI2_EVENT_MME3_SBTE2_ECC_DERR = 139,
+	GAUDI2_EVENT_MME3_SBTE3_ECC_DERR = 140,
+	GAUDI2_EVENT_MME3_SBTE4_ECC_DERR = 141,
+	GAUDI2_EVENT_MME3_CTRL_ECC_DERR = 142,
+	GAUDI2_EVENT_MME3_WAP_ECC_DERR = 143,
+	GAUDI2_EVENT_HDMA2_ECC_SERR = 144,
+	GAUDI2_EVENT_HDMA3_ECC_SERR = 145,
+	GAUDI2_EVENT_HDMA0_ECC_SERR = 146,
+	GAUDI2_EVENT_HDMA1_ECC_SERR = 147,
+	GAUDI2_EVENT_HDMA6_ECC_SERR = 148,
+	GAUDI2_EVENT_HDMA7_ECC_SERR = 149,
+	GAUDI2_EVENT_HDMA4_ECC_SERR = 150,
+	GAUDI2_EVENT_HDMA5_ECC_SERR = 151,
+	GAUDI2_EVENT_HDMA2_ECC_DERR = 152,
+	GAUDI2_EVENT_HDMA3_ECC_DERR = 153,
+	GAUDI2_EVENT_HDMA0_ECC_DERR = 154,
+	GAUDI2_EVENT_HDMA1_ECC_DERR = 155,
+	GAUDI2_EVENT_HDMA6_ECC_DERR = 156,
+	GAUDI2_EVENT_HDMA7_ECC_DERR = 157,
+	GAUDI2_EVENT_HDMA4_ECC_DERR = 158,
+	GAUDI2_EVENT_HDMA5_ECC_DERR = 159,
+	GAUDI2_EVENT_KDMA0_ECC_SERR = 160,
+	GAUDI2_EVENT_PDMA0_ECC_SERR = 161,
+	GAUDI2_EVENT_PDMA1_ECC_SERR = 162,
+	GAUDI2_EVENT_KDMA0_ECC_DERR = 163,
+	GAUDI2_EVENT_PDMA0_ECC_DERR = 164,
+	GAUDI2_EVENT_PDMA1_ECC_DERR = 165,
+	GAUDI2_EVENT_CPU_IF_ECC_SERR = 166,
+	GAUDI2_EVENT_CPU_IF_ECC_DERR = 167,
+	GAUDI2_EVENT_PSOC_MEM_SERR = 168,
+	GAUDI2_EVENT_PSOC_MEM_DERR = 169,
+	GAUDI2_EVENT_SRAM0_ECC_SERR = 170,
+	GAUDI2_EVENT_SRAM1_ECC_SERR = 171,
+	GAUDI2_EVENT_SRAM2_ECC_SERR = 172,
+	GAUDI2_EVENT_SRAM3_ECC_SERR = 173,
+	GAUDI2_EVENT_SRAM4_ECC_SERR = 174,
+	GAUDI2_EVENT_SRAM5_ECC_SERR = 175,
+	GAUDI2_EVENT_SRAM6_ECC_SERR = 176,
+	GAUDI2_EVENT_SRAM7_ECC_SERR = 177,
+	GAUDI2_EVENT_SRAM8_ECC_SERR = 178,
+	GAUDI2_EVENT_SRAM9_ECC_SERR = 179,
+	GAUDI2_EVENT_SRAM10_ECC_SERR = 180,
+	GAUDI2_EVENT_SRAM11_ECC_SERR = 181,
+	GAUDI2_EVENT_SRAM12_ECC_SERR = 182,
+	GAUDI2_EVENT_SRAM13_ECC_SERR = 183,
+	GAUDI2_EVENT_SRAM14_ECC_SERR = 184,
+	GAUDI2_EVENT_SRAM15_ECC_SERR = 185,
+	GAUDI2_EVENT_SRAM16_ECC_SERR = 186,
+	GAUDI2_EVENT_SRAM17_ECC_SERR = 187,
+	GAUDI2_EVENT_SRAM18_ECC_SERR = 188,
+	GAUDI2_EVENT_SRAM19_ECC_SERR = 189,
+	GAUDI2_EVENT_SRAM20_ECC_SERR = 190,
+	GAUDI2_EVENT_SRAM21_ECC_SERR = 191,
+	GAUDI2_EVENT_SRAM22_ECC_SERR = 192,
+	GAUDI2_EVENT_SRAM23_ECC_SERR = 193,
+	GAUDI2_EVENT_SRAM24_ECC_SERR = 194,
+	GAUDI2_EVENT_SRAM25_ECC_SERR = 195,
+	GAUDI2_EVENT_SRAM26_ECC_SERR = 196,
+	GAUDI2_EVENT_SRAM27_ECC_SERR = 197,
+	GAUDI2_EVENT_SRAM28_ECC_SERR = 198,
+	GAUDI2_EVENT_SRAM29_ECC_SERR = 199,
+	GAUDI2_EVENT_SRAM30_ECC_SERR = 200,
+	GAUDI2_EVENT_SRAM31_ECC_SERR = 201,
+	GAUDI2_EVENT_SRAM0_ECC_DERR = 202,
+	GAUDI2_EVENT_SRAM1_ECC_DERR = 203,
+	GAUDI2_EVENT_SRAM2_ECC_DERR = 204,
+	GAUDI2_EVENT_SRAM3_ECC_DERR = 205,
+	GAUDI2_EVENT_SRAM4_ECC_DERR = 206,
+	GAUDI2_EVENT_SRAM5_ECC_DERR = 207,
+	GAUDI2_EVENT_SRAM6_ECC_DERR = 208,
+	GAUDI2_EVENT_SRAM7_ECC_DERR = 209,
+	GAUDI2_EVENT_SRAM8_ECC_DERR = 210,
+	GAUDI2_EVENT_SRAM9_ECC_DERR = 211,
+	GAUDI2_EVENT_SRAM10_ECC_DERR = 212,
+	GAUDI2_EVENT_SRAM11_ECC_DERR = 213,
+	GAUDI2_EVENT_SRAM12_ECC_DERR = 214,
+	GAUDI2_EVENT_SRAM13_ECC_DERR = 215,
+	GAUDI2_EVENT_SRAM14_ECC_DERR = 216,
+	GAUDI2_EVENT_SRAM15_ECC_DERR = 217,
+	GAUDI2_EVENT_SRAM16_ECC_DERR = 218,
+	GAUDI2_EVENT_SRAM17_ECC_DERR = 219,
+	GAUDI2_EVENT_SRAM18_ECC_DERR = 220,
+	GAUDI2_EVENT_SRAM19_ECC_DERR = 221,
+	GAUDI2_EVENT_SRAM20_ECC_DERR = 222,
+	GAUDI2_EVENT_SRAM21_ECC_DERR = 223,
+	GAUDI2_EVENT_SRAM22_ECC_DERR = 224,
+	GAUDI2_EVENT_SRAM23_ECC_DERR = 225,
+	GAUDI2_EVENT_SRAM24_ECC_DERR = 226,
+	GAUDI2_EVENT_SRAM25_ECC_DERR = 227,
+	GAUDI2_EVENT_SRAM26_ECC_DERR = 228,
+	GAUDI2_EVENT_SRAM27_ECC_DERR = 229,
+	GAUDI2_EVENT_SRAM28_ECC_DERR = 230,
+	GAUDI2_EVENT_SRAM29_ECC_DERR = 231,
+	GAUDI2_EVENT_SRAM30_ECC_DERR = 232,
+	GAUDI2_EVENT_SRAM31_ECC_DERR = 233,
+	GAUDI2_EVENT_CPU_GIC500 = 234,
+	GAUDI2_EVENT_HBM_0_MC0_ECC_SERR = 235,
+	GAUDI2_EVENT_HBM_1_MC0_ECC_SERR = 236,
+	GAUDI2_EVENT_HBM_2_MC0_ECC_SERR = 237,
+	GAUDI2_EVENT_HBM_3_MC0_ECC_SERR = 238,
+	GAUDI2_EVENT_HBM_4_MC0_ECC_SERR = 239,
+	GAUDI2_EVENT_HBM_5_MC0_ECC_SERR = 240,
+	GAUDI2_EVENT_HBM_0_MC1_ECC_SERR = 241,
+	GAUDI2_EVENT_HBM_1_MC1_ECC_SERR = 242,
+	GAUDI2_EVENT_HBM_2_MC1_ECC_SERR = 243,
+	GAUDI2_EVENT_HBM_3_MC1_ECC_SERR = 244,
+	GAUDI2_EVENT_HBM_4_MC1_ECC_SERR = 245,
+	GAUDI2_EVENT_HBM_5_MC1_ECC_SERR = 246,
+	GAUDI2_EVENT_HBM_0_MC0_ECC_DERR = 247,
+	GAUDI2_EVENT_HBM_1_MC0_ECC_DERR = 248,
+	GAUDI2_EVENT_HBM_2_MC0_ECC_DERR = 249,
+	GAUDI2_EVENT_HBM_3_MC0_ECC_DERR = 250,
+	GAUDI2_EVENT_HBM_4_MC0_ECC_DERR = 251,
+	GAUDI2_EVENT_HBM_5_MC0_ECC_DERR = 252,
+	GAUDI2_EVENT_HBM_0_MC1_ECC_DERR = 253,
+	GAUDI2_EVENT_HBM_1_MC1_ECC_DERR = 254,
+	GAUDI2_EVENT_HBM_2_MC1_ECC_DERR = 255,
+	GAUDI2_EVENT_HBM_3_MC1_ECC_DERR = 256,
+	GAUDI2_EVENT_HBM_4_MC1_ECC_DERR = 257,
+	GAUDI2_EVENT_HBM_5_MC1_ECC_DERR = 258,
+	GAUDI2_EVENT_HMMU_0_ECC_SERR = 259,
+	GAUDI2_EVENT_HMMU_1_ECC_SERR = 260,
+	GAUDI2_EVENT_HMMU_2_ECC_SERR = 261,
+	GAUDI2_EVENT_HMMU_3_ECC_SERR = 262,
+	GAUDI2_EVENT_HMMU_8_ECC_SERR = 263,
+	GAUDI2_EVENT_HMMU_9_ECC_SERR = 264,
+	GAUDI2_EVENT_HMMU_10_ECC_SERR = 265,
+	GAUDI2_EVENT_HMMU_11_ECC_SERR = 266,
+	GAUDI2_EVENT_HMMU_7_ECC_SERR = 267,
+	GAUDI2_EVENT_HMMU_6_ECC_SERR = 268,
+	GAUDI2_EVENT_HMMU_5_ECC_SERR = 269,
+	GAUDI2_EVENT_HMMU_4_ECC_SERR = 270,
+	GAUDI2_EVENT_HMMU_15_ECC_SERR = 271,
+	GAUDI2_EVENT_HMMU_14_ECC_SERR = 272,
+	GAUDI2_EVENT_HMMU_13_ECC_SERR = 273,
+	GAUDI2_EVENT_HMMU_12_ECC_SERR = 274,
+	GAUDI2_EVENT_HMMU_0_ECC_DERR = 275,
+	GAUDI2_EVENT_HMMU_1_ECC_DERR = 276,
+	GAUDI2_EVENT_HMMU_2_ECC_DERR = 277,
+	GAUDI2_EVENT_HMMU_3_ECC_DERR = 278,
+	GAUDI2_EVENT_HMMU_8_ECC_DERR = 279,
+	GAUDI2_EVENT_HMMU_9_ECC_DERR = 280,
+	GAUDI2_EVENT_HMMU_10_ECC_DERR = 281,
+	GAUDI2_EVENT_HMMU_11_ECC_DERR = 282,
+	GAUDI2_EVENT_HMMU_7_ECC_DERR = 283,
+	GAUDI2_EVENT_HMMU_6_ECC_DERR = 284,
+	GAUDI2_EVENT_HMMU_5_ECC_DERR = 285,
+	GAUDI2_EVENT_HMMU_4_ECC_DERR = 286,
+	GAUDI2_EVENT_HMMU_15_ECC_DERR = 287,
+	GAUDI2_EVENT_HMMU_14_ECC_DERR = 288,
+	GAUDI2_EVENT_HMMU_13_ECC_DERR = 289,
+	GAUDI2_EVENT_HMMU_12_ECC_DERR = 290,
+	GAUDI2_EVENT_PMMU_ECC_SERR_0 = 291,
+	GAUDI2_EVENT_PMMU_ECC_DERR_0 = 292,
+	GAUDI2_EVENT_DEC0_VCD_ECC_SERR = 295,
+	GAUDI2_EVENT_DEC1_VCD_ECC_SERR = 296,
+	GAUDI2_EVENT_DEC2_VCD_ECC_SERR = 297,
+	GAUDI2_EVENT_DEC3_VCD_ECC_SERR = 298,
+	GAUDI2_EVENT_DEC4_VCD_ECC_SERR = 299,
+	GAUDI2_EVENT_DEC5_VCD_ECC_SERR = 300,
+	GAUDI2_EVENT_DEC6_VCD_ECC_SERR = 301,
+	GAUDI2_EVENT_DEC7_VCD_ECC_SERR = 302,
+	GAUDI2_EVENT_DEC8_VCD_ECC_SERR = 303,
+	GAUDI2_EVENT_DEC9_VCD_ECC_SERR = 304,
+	GAUDI2_EVENT_DEC0_L2C_ECC_SERR = 305,
+	GAUDI2_EVENT_DEC1_L2C_ECC_SERR = 306,
+	GAUDI2_EVENT_DEC2_L2C_ECC_SERR = 307,
+	GAUDI2_EVENT_DEC3_L2C_ECC_SERR = 308,
+	GAUDI2_EVENT_DEC4_L2C_ECC_SERR = 309,
+	GAUDI2_EVENT_DEC5_L2C_ECC_SERR = 310,
+	GAUDI2_EVENT_DEC6_L2C_ECC_SERR = 311,
+	GAUDI2_EVENT_DEC7_L2C_ECC_SERR = 312,
+	GAUDI2_EVENT_DEC8_L2C_ECC_SERR = 313,
+	GAUDI2_EVENT_DEC9_L2C_ECC_SERR = 314,
+	GAUDI2_EVENT_DEC0_VCD_ECC_DERR = 315,
+	GAUDI2_EVENT_DEC1_VCD_ECC_DERR = 316,
+	GAUDI2_EVENT_DEC2_VCD_ECC_DERR = 317,
+	GAUDI2_EVENT_DEC3_VCD_ECC_DERR = 318,
+	GAUDI2_EVENT_DEC4_VCD_ECC_DERR = 319,
+	GAUDI2_EVENT_DEC5_VCD_ECC_DERR = 320,
+	GAUDI2_EVENT_DEC6_VCD_ECC_DERR = 321,
+	GAUDI2_EVENT_DEC7_VCD_ECC_DERR = 322,
+	GAUDI2_EVENT_DEC8_VCD_ECC_DERR = 323,
+	GAUDI2_EVENT_DEC9_VCD_ECC_DERR = 324,
+	GAUDI2_EVENT_DEC0_L2C_ECC_DERR = 325,
+	GAUDI2_EVENT_DEC1_L2C_ECC_DERR = 326,
+	GAUDI2_EVENT_DEC2_L2C_ECC_DERR = 327,
+	GAUDI2_EVENT_DEC3_L2C_ECC_DERR = 328,
+	GAUDI2_EVENT_DEC4_L2C_ECC_DERR = 329,
+	GAUDI2_EVENT_DEC5_L2C_ECC_DERR = 330,
+	GAUDI2_EVENT_DEC6_L2C_ECC_DERR = 331,
+	GAUDI2_EVENT_DEC7_L2C_ECC_DERR = 332,
+	GAUDI2_EVENT_DEC8_L2C_ECC_DERR = 333,
+	GAUDI2_EVENT_DEC9_L2C_ECC_DERR = 334,
+	GAUDI2_EVENT_HIF0_ECC_SERR = 337,
+	GAUDI2_EVENT_HIF1_ECC_SERR = 338,
+	GAUDI2_EVENT_HIF2_ECC_SERR = 339,
+	GAUDI2_EVENT_HIF3_ECC_SERR = 340,
+	GAUDI2_EVENT_HIF8_ECC_SERR = 341,
+	GAUDI2_EVENT_HIF9_ECC_SERR = 342,
+	GAUDI2_EVENT_HIF10_ECC_SERR = 343,
+	GAUDI2_EVENT_HIF11_ECC_SERR = 344,
+	GAUDI2_EVENT_HIF7_ECC_SERR = 345,
+	GAUDI2_EVENT_HIF6_ECC_SERR = 346,
+	GAUDI2_EVENT_HIF5_ECC_SERR = 347,
+	GAUDI2_EVENT_HIF4_ECC_SERR = 348,
+	GAUDI2_EVENT_HIF15_ECC_SERR = 349,
+	GAUDI2_EVENT_HIF14_ECC_SERR = 350,
+	GAUDI2_EVENT_HIF13_ECC_SERR = 351,
+	GAUDI2_EVENT_HIF12_ECC_SERR = 352,
+	GAUDI2_EVENT_HIF0_ECC_DERR = 353,
+	GAUDI2_EVENT_HIF1_ECC_DERR = 354,
+	GAUDI2_EVENT_HIF2_ECC_DERR = 355,
+	GAUDI2_EVENT_HIF3_ECC_DERR = 356,
+	GAUDI2_EVENT_HIF8_ECC_DERR = 357,
+	GAUDI2_EVENT_HIF9_ECC_DERR = 358,
+	GAUDI2_EVENT_HIF10_ECC_DERR = 359,
+	GAUDI2_EVENT_HIF11_ECC_DERR = 360,
+	GAUDI2_EVENT_HIF7_ECC_DERR = 361,
+	GAUDI2_EVENT_HIF6_ECC_DERR = 362,
+	GAUDI2_EVENT_HIF5_ECC_DERR = 363,
+	GAUDI2_EVENT_HIF4_ECC_DERR = 364,
+	GAUDI2_EVENT_HIF15_ECC_DERR = 365,
+	GAUDI2_EVENT_HIF14_ECC_DERR = 366,
+	GAUDI2_EVENT_HIF13_ECC_DERR = 367,
+	GAUDI2_EVENT_HIF12_ECC_DERR = 368,
+	GAUDI2_EVENT_NIC0_ECC_SERR = 369,
+	GAUDI2_EVENT_NIC1_ECC_SERR = 370,
+	GAUDI2_EVENT_NIC2_ECC_SERR = 371,
+	GAUDI2_EVENT_NIC3_ECC_SERR = 372,
+	GAUDI2_EVENT_NIC4_ECC_SERR = 373,
+	GAUDI2_EVENT_NIC5_ECC_SERR = 374,
+	GAUDI2_EVENT_NIC6_ECC_SERR = 375,
+	GAUDI2_EVENT_NIC7_ECC_SERR = 376,
+	GAUDI2_EVENT_NIC8_ECC_SERR = 377,
+	GAUDI2_EVENT_NIC9_ECC_SERR = 378,
+	GAUDI2_EVENT_NIC10_ECC_SERR = 379,
+	GAUDI2_EVENT_NIC11_ECC_SERR = 380,
+	GAUDI2_EVENT_NIC0_ECC_DERR = 381,
+	GAUDI2_EVENT_NIC1_ECC_DERR = 382,
+	GAUDI2_EVENT_NIC2_ECC_DERR = 383,
+	GAUDI2_EVENT_NIC3_ECC_DERR = 384,
+	GAUDI2_EVENT_NIC4_ECC_DERR = 385,
+	GAUDI2_EVENT_NIC5_ECC_DERR = 386,
+	GAUDI2_EVENT_NIC6_ECC_DERR = 387,
+	GAUDI2_EVENT_NIC7_ECC_DERR = 388,
+	GAUDI2_EVENT_NIC8_ECC_DERR = 389,
+	GAUDI2_EVENT_NIC9_ECC_DERR = 390,
+	GAUDI2_EVENT_NIC10_ECC_DERR = 391,
+	GAUDI2_EVENT_NIC11_ECC_DERR = 392,
+	GAUDI2_EVENT_SM0_ECC_DERR = 393,
+	GAUDI2_EVENT_SM1_ECC_DERR = 394,
+	GAUDI2_EVENT_SM2_ECC_DERR = 395,
+	GAUDI2_EVENT_SM3_ECC_DERR = 396,
+	GAUDI2_EVENT_SM0_ECC_SERR = 397,
+	GAUDI2_EVENT_SM1_ECC_SERR = 398,
+	GAUDI2_EVENT_SM2_ECC_SERR = 399,
+	GAUDI2_EVENT_SM3_ECC_SERR = 400,
+	GAUDI2_EVENT_XBAR0_ECC_SERR = 401,
+	GAUDI2_EVENT_XBAR1_ECC_SERR = 402,
+	GAUDI2_EVENT_XBAR2_ECC_SERR = 403,
+	GAUDI2_EVENT_XBAR3_ECC_SERR = 404,
+	GAUDI2_EVENT_XBAR0_ECC_DERR = 405,
+	GAUDI2_EVENT_XBAR1_ECC_DERR = 406,
+	GAUDI2_EVENT_XBAR2_ECC_DERR = 407,
+	GAUDI2_EVENT_XBAR3_ECC_DERR = 408,
+	GAUDI2_EVENT_ARC0_ECC_SERR = 409,
+	GAUDI2_EVENT_ARC0_ECC_DERR = 410,
+	GAUDI2_EVENT_PCIE_BME_CLEARD = 411,
+	GAUDI2_EVENT_PCIE_ADDR_DEC_ERR = 412,
+	GAUDI2_EVENT_TPC0_AXI_ERR_RSP = 413,
+	GAUDI2_EVENT_TPC1_AXI_ERR_RSP = 414,
+	GAUDI2_EVENT_TPC2_AXI_ERR_RSP = 415,
+	GAUDI2_EVENT_TPC3_AXI_ERR_RSP = 416,
+	GAUDI2_EVENT_TPC4_AXI_ERR_RSP = 417,
+	GAUDI2_EVENT_TPC5_AXI_ERR_RSP = 418,
+	GAUDI2_EVENT_TPC6_AXI_ERR_RSP = 419,
+	GAUDI2_EVENT_TPC7_AXI_ERR_RSP = 420,
+	GAUDI2_EVENT_TPC8_AXI_ERR_RSP = 421,
+	GAUDI2_EVENT_TPC9_AXI_ERR_RSP = 422,
+	GAUDI2_EVENT_TPC10_AXI_ERR_RSP = 423,
+	GAUDI2_EVENT_TPC11_AXI_ERR_RSP = 424,
+	GAUDI2_EVENT_TPC12_AXI_ERR_RSP = 425,
+	GAUDI2_EVENT_TPC13_AXI_ERR_RSP = 426,
+	GAUDI2_EVENT_TPC14_AXI_ERR_RSP = 427,
+	GAUDI2_EVENT_TPC15_AXI_ERR_RSP = 428,
+	GAUDI2_EVENT_TPC16_AXI_ERR_RSP = 429,
+	GAUDI2_EVENT_TPC17_AXI_ERR_RSP = 430,
+	GAUDI2_EVENT_TPC18_AXI_ERR_RSP = 431,
+	GAUDI2_EVENT_TPC19_AXI_ERR_RSP = 432,
+	GAUDI2_EVENT_TPC20_AXI_ERR_RSP = 433,
+	GAUDI2_EVENT_TPC21_AXI_ERR_RSP = 434,
+	GAUDI2_EVENT_TPC22_AXI_ERR_RSP = 435,
+	GAUDI2_EVENT_TPC23_AXI_ERR_RSP = 436,
+	GAUDI2_EVENT_TPC24_AXI_ERR_RSP = 437,
+	GAUDI2_EVENT_CPU_AXI_ECC = 438,
+	GAUDI2_EVENT_CPU_L2_RAM_ECC = 439,
+	GAUDI2_EVENT_MME0_SBTE0_AXI_ERR_RSP = 440,
+	GAUDI2_EVENT_MME0_SBTE1_AXI_ERR_RSP = 441,
+	GAUDI2_EVENT_MME0_SBTE2_AXI_ERR_RSP = 442,
+	GAUDI2_EVENT_MME0_SBTE3_AXI_ERR_RSP = 443,
+	GAUDI2_EVENT_MME0_SBTE4_AXI_ERR_RSP = 444,
+	GAUDI2_EVENT_MME0_CTRL_AXI_ERROR_RESPONSE = 445,
+	GAUDI2_EVENT_MME0_QMAN_SW_ERROR = 446,
+	GAUDI2_EVENT_MME1_SBTE0_AXI_ERR_RSP = 447,
+	GAUDI2_EVENT_MME1_SBTE1_AXI_ERR_RSP = 448,
+	GAUDI2_EVENT_MME1_SBTE2_AXI_ERR_RSP = 449,
+	GAUDI2_EVENT_MME1_SBTE3_AXI_ERR_RSP = 450,
+	GAUDI2_EVENT_MME1_SBTE4_AXI_ERR_RSP = 451,
+	GAUDI2_EVENT_MME1_CTRL_AXI_ERROR_RESPONSE = 452,
+	GAUDI2_EVENT_MME1_QMAN_SW_ERROR = 453,
+	GAUDI2_EVENT_MME2_SBTE0_AXI_ERR_RSP = 454,
+	GAUDI2_EVENT_MME2_SBTE1_AXI_ERR_RSP = 455,
+	GAUDI2_EVENT_MME2_SBTE2_AXI_ERR_RSP = 456,
+	GAUDI2_EVENT_MME2_SBTE3_AXI_ERR_RSP = 457,
+	GAUDI2_EVENT_MME2_SBTE4_AXI_ERR_RSP = 458,
+	GAUDI2_EVENT_MME2_CTRL_AXI_ERROR_RESPONSE = 459,
+	GAUDI2_EVENT_MME2_QMAN_SW_ERROR = 460,
+	GAUDI2_EVENT_MME3_SBTE0_AXI_ERR_RSP = 461,
+	GAUDI2_EVENT_MME3_SBTE1_AXI_ERR_RSP = 462,
+	GAUDI2_EVENT_MME3_SBTE2_AXI_ERR_RSP = 463,
+	GAUDI2_EVENT_MME3_SBTE3_AXI_ERR_RSP = 464,
+	GAUDI2_EVENT_MME3_SBTE4_AXI_ERR_RSP = 465,
+	GAUDI2_EVENT_MME3_CTRL_AXI_ERROR_RESPONSE = 466,
+	GAUDI2_EVENT_MME3_QMAN_SW_ERROR = 467,
+	GAUDI2_EVENT_PSOC_MME_PLL_LOCK_ERR = 468,
+	GAUDI2_EVENT_PSOC_CPU_PLL_LOCK_ERR = 469,
+	GAUDI2_EVENT_DCORE3_TPC_PLL_LOCK_ERR = 470,
+	GAUDI2_EVENT_DCORE3_NIC_PLL_LOCK_ERR = 471,
+	GAUDI2_EVENT_DCORE3_XBAR_MMU_PLL_LOCK_ERR = 472,
+	GAUDI2_EVENT_DCORE3_XBAR_DMA_PLL_LOCK_ERR = 473,
+	GAUDI2_EVENT_DCORE3_XBAR_IF_PLL_LOCK_ERR = 474,
+	GAUDI2_EVENT_DCORE3_XBAR_BANK_PLL_LOCK_ERR = 475,
+	GAUDI2_EVENT_DCORE1_XBAR_MMU_PLL_LOCK_ERR = 476,
+	GAUDI2_EVENT_DCORE1_XBAR_DMA_PLL_LOCK_ERR = 477,
+	GAUDI2_EVENT_DCORE1_XBAR_IF_PLL_LOCK_ERR = 478,
+	GAUDI2_EVENT_DCORE1_XBAR_MESH_PLL_LOCK_ERR = 479,
+	GAUDI2_EVENT_DCORE1_TPC_PLL_LOCK_ERR = 480,
+	GAUDI2_EVENT_DCORE1_NIC_PLL_LOCK_ERR = 481,
+	GAUDI2_EVENT_PMMU_MME_PLL_LOCK_ERR = 482,
+	GAUDI2_EVENT_DCORE0_TPC_PLL_LOCK_ERR = 483,
+	GAUDI2_EVENT_DCORE0_PCI_PLL_LOCK_ERR = 484,
+	GAUDI2_EVENT_DCORE0_XBAR_MMU_PLL_LOCK_ERR = 485,
+	GAUDI2_EVENT_DCORE0_XBAR_DMA_PLL_LOCK_ERR = 486,
+	GAUDI2_EVENT_DCORE0_XBAR_IF_PLL_LOCK_ERR = 487,
+	GAUDI2_EVENT_DCORE0_XBAR_MESH_PLL_LOCK_ERR = 488,
+	GAUDI2_EVENT_DCORE2_XBAR_MMU_PLL_LOCK_ERR = 489,
+	GAUDI2_EVENT_DCORE2_XBAR_DMA_PLL_LOCK_ERR = 490,
+	GAUDI2_EVENT_DCORE2_XBAR_IF_PLL_LOCK_ERR = 491,
+	GAUDI2_EVENT_DCORE2_XBAR_BANK_PLL_LOCK_ERR = 492,
+	GAUDI2_EVENT_DCORE2_TPC_PLL_LOCK_ERR = 493,
+	GAUDI2_EVENT_PSOC_VID_PLL_LOCK_ERR = 494,
+	GAUDI2_EVENT_PMMU_VID_PLL_LOCK_ERR = 495,
+	GAUDI2_EVENT_DCORE3_HBM_PLL_LOCK_ERR = 496,
+	GAUDI2_EVENT_DCORE1_XBAR_HBM_PLL_LOCK_ERR = 497,
+	GAUDI2_EVENT_DCORE1_HBM_PLL_LOCK_ERR = 498,
+	GAUDI2_EVENT_DCORE0_HBM_PLL_LOCK_ERR = 499,
+	GAUDI2_EVENT_DCORE2_XBAR_HBM_PLL_LOCK_ERR = 500,
+	GAUDI2_EVENT_DCORE2_HBM_PLL_LOCK_ERR = 501,
+	GAUDI2_EVENT_CPU_AXI_ERR_RSP = 502,
+	GAUDI2_EVENT_HMMU_0_AXI_ERR_RSP = 503,
+	GAUDI2_EVENT_HMMU_1_AXI_ERR_RSP = 504,
+	GAUDI2_EVENT_HMMU_2_AXI_ERR_RSP = 505,
+	GAUDI2_EVENT_HMMU_3_AXI_ERR_RSP = 506,
+	GAUDI2_EVENT_HMMU_8_AXI_ERR_RSP = 507,
+	GAUDI2_EVENT_HMMU_9_AXI_ERR_RSP = 508,
+	GAUDI2_EVENT_HMMU_10_AXI_ERR_RSP = 509,
+	GAUDI2_EVENT_HMMU_11_AXI_ERR_RSP = 510,
+	GAUDI2_EVENT_HMMU_7_AXI_ERR_RSP = 511,
+	GAUDI2_EVENT_HMMU_6_AXI_ERR_RSP = 512,
+	GAUDI2_EVENT_HMMU_5_AXI_ERR_RSP = 513,
+	GAUDI2_EVENT_HMMU_4_AXI_ERR_RSP = 514,
+	GAUDI2_EVENT_HMMU_15_AXI_ERR_RSP = 515,
+	GAUDI2_EVENT_HMMU_14_AXI_ERR_RSP = 516,
+	GAUDI2_EVENT_HMMU_13_AXI_ERR_RSP = 517,
+	GAUDI2_EVENT_HMMU_12_AXI_ERR_RSP = 518,
+	GAUDI2_EVENT_PMMU_FATAL_0 = 519,
+	GAUDI2_EVENT_PMMU_AXI_ERR_RSP_0 = 520,
+	GAUDI2_EVENT_VM0_ALARM_A = 521,
+	GAUDI2_EVENT_VM0_ALARM_B = 522,
+	GAUDI2_EVENT_VM1_ALARM_A = 523,
+	GAUDI2_EVENT_VM1_ALARM_B = 524,
+	GAUDI2_EVENT_VM2_ALARM_A = 525,
+	GAUDI2_EVENT_VM2_ALARM_B = 526,
+	GAUDI2_EVENT_VM3_ALARM_A = 527,
+	GAUDI2_EVENT_VM3_ALARM_B = 528,
+	GAUDI2_EVENT_PSOC_AXI_ERR_RSP = 529,
+	GAUDI2_EVENT_PSOC_PRSTN_FALL = 530,
+	GAUDI2_EVENT_KDMA_CH0_AXI_ERR_RSP = 539,
+	GAUDI2_EVENT_PDMA_CH0_AXI_ERR_RSP = 540,
+	GAUDI2_EVENT_PDMA_CH1_AXI_ERR_RSP = 541,
+	GAUDI2_EVENT_HBM_CATTRIP_0 = 542,
+	GAUDI2_EVENT_HBM_CATTRIP_1 = 543,
+	GAUDI2_EVENT_HBM_CATTRIP_2 = 544,
+	GAUDI2_EVENT_HBM_CATTRIP_3 = 545,
+	GAUDI2_EVENT_HBM_CATTRIP_4 = 546,
+	GAUDI2_EVENT_HBM_CATTRIP_5 = 547,
+	GAUDI2_EVENT_HBM0_MC0_SEI_SEVERE = 548,
+	GAUDI2_EVENT_HBM0_MC0_SEI_NON_SEVERE = 549,
+	GAUDI2_EVENT_HBM0_MC1_SEI_SEVERE = 550,
+	GAUDI2_EVENT_HBM0_MC1_SEI_NON_SEVERE = 551,
+	GAUDI2_EVENT_HBM1_MC0_SEI_SEVERE = 552,
+	GAUDI2_EVENT_HBM1_MC0_SEI_NON_SEVERE = 553,
+	GAUDI2_EVENT_HBM1_MC1_SEI_SEVERE = 554,
+	GAUDI2_EVENT_HBM1_MC1_SEI_NON_SEVERE = 555,
+	GAUDI2_EVENT_HBM2_MC0_SEI_SEVERE = 556,
+	GAUDI2_EVENT_HBM2_MC0_SEI_NON_SEVERE = 557,
+	GAUDI2_EVENT_HBM2_MC1_SEI_SEVERE = 558,
+	GAUDI2_EVENT_HBM2_MC1_SEI_NON_SEVERE = 559,
+	GAUDI2_EVENT_HBM3_MC0_SEI_SEVERE = 560,
+	GAUDI2_EVENT_HBM3_MC0_SEI_NON_SEVERE = 561,
+	GAUDI2_EVENT_HBM3_MC1_SEI_SEVERE = 562,
+	GAUDI2_EVENT_HBM3_MC1_SEI_NON_SEVERE = 563,
+	GAUDI2_EVENT_HBM4_MC0_SEI_SEVERE = 564,
+	GAUDI2_EVENT_HBM4_MC0_SEI_NON_SEVERE = 565,
+	GAUDI2_EVENT_HBM4_MC1_SEI_SEVERE = 566,
+	GAUDI2_EVENT_HBM4_MC1_SEI_NON_SEVERE = 567,
+	GAUDI2_EVENT_HBM5_MC0_SEI_SEVERE = 568,
+	GAUDI2_EVENT_HBM5_MC0_SEI_NON_SEVERE = 569,
+	GAUDI2_EVENT_HBM5_MC1_SEI_SEVERE = 570,
+	GAUDI2_EVENT_HBM5_MC1_SEI_NON_SEVERE = 571,
+	GAUDI2_EVENT_DEC0_AXI_ERR_RSPONSE = 572,
+	GAUDI2_EVENT_DEC1_AXI_ERR_RSPONSE = 573,
+	GAUDI2_EVENT_DEC2_AXI_ERR_RSPONSE = 574,
+	GAUDI2_EVENT_DEC3_AXI_ERR_RSPONSE = 575,
+	GAUDI2_EVENT_DEC4_AXI_ERR_RSPONSE = 576,
+	GAUDI2_EVENT_DEC5_AXI_ERR_RSPONSE = 577,
+	GAUDI2_EVENT_DEC6_AXI_ERR_RSPONSE = 578,
+	GAUDI2_EVENT_DEC7_AXI_ERR_RSPONSE = 579,
+	GAUDI2_EVENT_DEC8_AXI_ERR_RSPONSE = 580,
+	GAUDI2_EVENT_DEC9_AXI_ERR_RSPONSE = 581,
+	GAUDI2_EVENT_HIF0_FATAL = 584,
+	GAUDI2_EVENT_HIF1_FATAL = 585,
+	GAUDI2_EVENT_HIF2_FATAL = 586,
+	GAUDI2_EVENT_HIF3_FATAL = 587,
+	GAUDI2_EVENT_HIF8_FATAL = 588,
+	GAUDI2_EVENT_HIF9_FATAL = 589,
+	GAUDI2_EVENT_HIF10_FATAL = 590,
+	GAUDI2_EVENT_HIF11_FATAL = 591,
+	GAUDI2_EVENT_HIF7_FATAL = 592,
+	GAUDI2_EVENT_HIF6_FATAL = 593,
+	GAUDI2_EVENT_HIF5_FATAL = 594,
+	GAUDI2_EVENT_HIF4_FATAL = 595,
+	GAUDI2_EVENT_HIF15_FATAL = 596,
+	GAUDI2_EVENT_HIF14_FATAL = 597,
+	GAUDI2_EVENT_HIF13_FATAL = 598,
+	GAUDI2_EVENT_HIF12_FATAL = 599,
+	GAUDI2_EVENT_NIC0_AXI_ERROR_RESPONSE = 600,
+	GAUDI2_EVENT_NIC1_AXI_ERROR_RESPONSE = 601,
+	GAUDI2_EVENT_NIC2_AXI_ERROR_RESPONSE = 602,
+	GAUDI2_EVENT_NIC3_AXI_ERROR_RESPONSE = 603,
+	GAUDI2_EVENT_NIC4_AXI_ERROR_RESPONSE = 604,
+	GAUDI2_EVENT_NIC5_AXI_ERROR_RESPONSE = 605,
+	GAUDI2_EVENT_NIC6_AXI_ERROR_RESPONSE = 606,
+	GAUDI2_EVENT_NIC7_AXI_ERROR_RESPONSE = 607,
+	GAUDI2_EVENT_NIC8_AXI_ERROR_RESPONSE = 608,
+	GAUDI2_EVENT_NIC9_AXI_ERROR_RESPONSE = 609,
+	GAUDI2_EVENT_NIC10_AXI_ERROR_RESPONSE = 610,
+	GAUDI2_EVENT_NIC11_AXI_ERROR_RESPONSE = 611,
+	GAUDI2_EVENT_SM0_AXI_ERROR_RESPONSE = 612,
+	GAUDI2_EVENT_SM1_AXI_ERROR_RESPONSE = 613,
+	GAUDI2_EVENT_SM2_AXI_ERROR_RESPONSE = 614,
+	GAUDI2_EVENT_SM3_AXI_ERROR_RESPONSE = 615,
+	GAUDI2_EVENT_ARC_AXI_ERROR_RESPONSE_0 = 616,
+	GAUDI2_EVENT_PCIE_PME_MSG_RECEIVED = 618,
+	GAUDI2_EVENT_PCIE_FLR_REQUESTED = 619,
+	GAUDI2_EVENT_PCIE_HOT_RESET_REQ = 620,
+	GAUDI2_EVENT_PCIE_PERST = 621,
+	GAUDI2_EVENT_PCIE_APB_TIMEOUT = 622,
+	GAUDI2_EVENT_PCIE_BM_D_P_WR = 623,
+	GAUDI2_EVENT_PCIE_BM_D_RD = 624,
+	GAUDI2_EVENT_PCIE_BM_U_P_WR = 625,
+	GAUDI2_EVENT_PCIE_BM_U_RD = 626,
+	GAUDI2_EVENT_PCIE_FATAL_ERR = 627,
+	GAUDI2_EVENT_PCIE_PERST_FAL = 628,
+	GAUDI2_EVENT_PCIE_VDM_READY = 629,
+	GAUDI2_EVENT_PCIE_VDM_ERROR = 630,
+	GAUDI2_EVENT_PCIE_P2P_MSIX = 631,
+	GAUDI2_EVENT_PCIE_DRAIN_COMPLETE = 632,
+	GAUDI2_EVENT_TPC0_BMON_SPMU = 633,
+	GAUDI2_EVENT_TPC0_KERNEL_ERR = 634,
+	GAUDI2_EVENT_TPC1_BMON_SPMU = 635,
+	GAUDI2_EVENT_TPC1_KERNEL_ERR = 636,
+	GAUDI2_EVENT_TPC2_BMON_SPMU = 637,
+	GAUDI2_EVENT_TPC2_KERNEL_ERR = 638,
+	GAUDI2_EVENT_TPC3_BMON_SPMU = 639,
+	GAUDI2_EVENT_TPC3_KERNEL_ERR = 640,
+	GAUDI2_EVENT_TPC4_BMON_SPMU = 641,
+	GAUDI2_EVENT_TPC4_KERNEL_ERR = 642,
+	GAUDI2_EVENT_TPC5_BMON_SPMU = 643,
+	GAUDI2_EVENT_TPC5_KERNEL_ERR = 644,
+	GAUDI2_EVENT_TPC6_BMON_SPMU = 645,
+	GAUDI2_EVENT_TPC6_KERNEL_ERR = 646,
+	GAUDI2_EVENT_TPC7_BMON_SPMU = 647,
+	GAUDI2_EVENT_TPC7_KERNEL_ERR = 648,
+	GAUDI2_EVENT_TPC8_BMON_SPMU = 649,
+	GAUDI2_EVENT_TPC8_KERNEL_ERR = 650,
+	GAUDI2_EVENT_TPC9_BMON_SPMU = 651,
+	GAUDI2_EVENT_TPC9_KERNEL_ERR = 652,
+	GAUDI2_EVENT_TPC10_BMON_SPMU = 653,
+	GAUDI2_EVENT_TPC10_KERNEL_ERR = 654,
+	GAUDI2_EVENT_TPC11_BMON_SPMU = 655,
+	GAUDI2_EVENT_TPC11_KERNEL_ERR = 656,
+	GAUDI2_EVENT_TPC12_BMON_SPMU = 657,
+	GAUDI2_EVENT_TPC12_KERNEL_ERR = 658,
+	GAUDI2_EVENT_TPC13_BMON_SPMU = 659,
+	GAUDI2_EVENT_TPC13_KERNEL_ERR = 660,
+	GAUDI2_EVENT_TPC14_BMON_SPMU = 661,
+	GAUDI2_EVENT_TPC14_KERNEL_ERR = 662,
+	GAUDI2_EVENT_TPC15_BMON_SPMU = 663,
+	GAUDI2_EVENT_TPC15_KERNEL_ERR = 664,
+	GAUDI2_EVENT_TPC16_BMON_SPMU = 665,
+	GAUDI2_EVENT_TPC16_KERNEL_ERR = 666,
+	GAUDI2_EVENT_TPC17_BMON_SPMU = 667,
+	GAUDI2_EVENT_TPC17_KERNEL_ERR = 668,
+	GAUDI2_EVENT_TPC18_BMON_SPMU = 669,
+	GAUDI2_EVENT_TPC18_KERNEL_ERR = 670,
+	GAUDI2_EVENT_TPC19_BMON_SPMU = 671,
+	GAUDI2_EVENT_TPC19_KERNEL_ERR = 672,
+	GAUDI2_EVENT_TPC20_BMON_SPMU = 673,
+	GAUDI2_EVENT_TPC20_KERNEL_ERR = 674,
+	GAUDI2_EVENT_TPC21_BMON_SPMU = 675,
+	GAUDI2_EVENT_TPC21_KERNEL_ERR = 676,
+	GAUDI2_EVENT_TPC22_BMON_SPMU = 677,
+	GAUDI2_EVENT_TPC22_KERNEL_ERR = 678,
+	GAUDI2_EVENT_TPC23_BMON_SPMU = 679,
+	GAUDI2_EVENT_TPC23_KERNEL_ERR = 680,
+	GAUDI2_EVENT_TPC24_BMON_SPMU = 681,
+	GAUDI2_EVENT_TPC24_KERNEL_ERR = 682,
+	GAUDI2_EVENT_MME0_SPI_BASE = 683,
+	GAUDI2_EVENT_MME0_CTRL_BMON_SPMU = 688,
+	GAUDI2_EVENT_MME0_SBTE_BMON_SPMU = 689,
+	GAUDI2_EVENT_MME0_WAP_BMON_SPMU = 690,
+	GAUDI2_EVENT_MME0_WAP_SOURCE_RESULT_INVALID = 691,
+	GAUDI2_EVENT_MME1_SPI_BASE = 692,
+	GAUDI2_EVENT_MME1_CTRL_BMON_SPMU = 697,
+	GAUDI2_EVENT_MME1_SBTE_BMON_SPMU = 698,
+	GAUDI2_EVENT_MME1_WAP_BMON_SPMU = 699,
+	GAUDI2_EVENT_MME1_WAP_SOURCE_RESULT_INVALID = 700,
+	GAUDI2_EVENT_MME2_SPI_BASE = 701,
+	GAUDI2_EVENT_MME2_CTRL_BMON_SPMU = 706,
+	GAUDI2_EVENT_MME2_SBTE_BMON_SPMU = 707,
+	GAUDI2_EVENT_MME2_WAP_BMON_SPMU = 708,
+	GAUDI2_EVENT_MME2_WAP_SOURCE_RESULT_INVALID = 709,
+	GAUDI2_EVENT_MME3_SPI_BASE = 710,
+	GAUDI2_EVENT_MME3_CTRL_BMON_SPMU = 715,
+	GAUDI2_EVENT_MME3_SBTE_BMON_SPMU = 716,
+	GAUDI2_EVENT_MME3_WAP_BMON_SPMU = 717,
+	GAUDI2_EVENT_MME3_WAP_SOURCE_RESULT_INVALID = 718,
+	GAUDI2_EVENT_HMMU0_SPI_BASE = 719,
+	GAUDI2_EVENT_HMMU0_PAGE_FAULT_OR_WR_PERM = 720,
+	GAUDI2_EVENT_HMMU0_SECURITY_ERROR = 721,
+	GAUDI2_EVENT_HMMU1_SPI_BASE = 722,
+	GAUDI2_EVENT_HMMU1_PAGE_FAULT_WR_PERM = 723,
+	GAUDI2_EVENT_HMMU1_SECURITY_ERROR = 724,
+	GAUDI2_EVENT_HMMU2_SPI_BASE = 725,
+	GAUDI2_EVENT_HMMU2_PAGE_FAULT_WR_PERM = 726,
+	GAUDI2_EVENT_HMMU2_SECURITY_ERROR = 727,
+	GAUDI2_EVENT_HMMU3_SPI_BASE = 728,
+	GAUDI2_EVENT_HMMU3_PAGE_FAULT_WR_PERM = 729,
+	GAUDI2_EVENT_HMMU3_SECURITY_ERROR = 730,
+	GAUDI2_EVENT_HMMU8_SPI_BASE = 731,
+	GAUDI2_EVENT_HMMU8_PAGE_FAULT_WR_PERM = 732,
+	GAUDI2_EVENT_HMMU8_SECURITY_ERROR = 733,
+	GAUDI2_EVENT_HMMU9_SPI_BASE = 734,
+	GAUDI2_EVENT_HMMU9_PAGE_FAULT_WR_PERM = 735,
+	GAUDI2_EVENT_HMMU9_SECURITY_ERROR = 736,
+	GAUDI2_EVENT_HMMU10_SPI_BASE = 737,
+	GAUDI2_EVENT_HMMU10_PAGE_FAULT_WR_PERM = 738,
+	GAUDI2_EVENT_HMMU10_SECURITY_ERROR = 739,
+	GAUDI2_EVENT_HMMU11_SPI_BASE = 740,
+	GAUDI2_EVENT_HMMU11_PAGE_FAULT_WR_PERM = 741,
+	GAUDI2_EVENT_HMMU11_SECURITY_ERROR = 742,
+	GAUDI2_EVENT_HMMU7_SPI_BASE = 743,
+	GAUDI2_EVENT_HMMU7_PAGE_FAULT_WR_PERM = 744,
+	GAUDI2_EVENT_HMMU7_SECURITY_ERROR = 745,
+	GAUDI2_EVENT_HMMU6_SPI_BASE = 746,
+	GAUDI2_EVENT_HMMU6_PAGE_FAULT_WR_PERM = 747,
+	GAUDI2_EVENT_HMMU6_SECURITY_ERROR = 748,
+	GAUDI2_EVENT_HMMU5_SPI_BASE = 749,
+	GAUDI2_EVENT_HMMU5_PAGE_FAULT_WR_PERM = 750,
+	GAUDI2_EVENT_HMMU5_SECURITY_ERROR = 751,
+	GAUDI2_EVENT_HMMU4_SPI_BASE = 752,
+	GAUDI2_EVENT_HMMU4_PAGE_FAULT_WR_PERM = 753,
+	GAUDI2_EVENT_HMMU4_SECURITY_ERROR = 754,
+	GAUDI2_EVENT_HMMU15_SPI_BASE = 755,
+	GAUDI2_EVENT_HMMU15_PAGE_FAULT_WR_PERM = 756,
+	GAUDI2_EVENT_HMMU15_SECURITY_ERROR = 757,
+	GAUDI2_EVENT_HMMU14_SPI_BASE = 758,
+	GAUDI2_EVENT_HMMU14_PAGE_FAULT_WR_PERM = 759,
+	GAUDI2_EVENT_HMMU14_SECURITY_ERROR = 760,
+	GAUDI2_EVENT_HMMU13_SPI_BASE = 761,
+	GAUDI2_EVENT_HMMU13_PAGE_FAULT_WR_PERM = 762,
+	GAUDI2_EVENT_HMMU13_SECURITY_ERROR = 763,
+	GAUDI2_EVENT_HMMU12_SPI_BASE = 764,
+	GAUDI2_EVENT_HMMU12_PAGE_FAULT_WR_PERM = 765,
+	GAUDI2_EVENT_HMMU12_SECURITY_ERROR = 766,
+	GAUDI2_EVENT_PMMU0_PAGE_FAULT_WR_PERM = 768,
+	GAUDI2_EVENT_PMMU0_SECURITY_ERROR = 769,
+	GAUDI2_EVENT_HDMA2_BM_SPMU = 770,
+	GAUDI2_EVENT_HDMA3_BM_SPMU = 772,
+	GAUDI2_EVENT_HDMA0_BM_SPMU = 774,
+	GAUDI2_EVENT_HDMA1_BM_SPMU = 776,
+	GAUDI2_EVENT_HDMA6_BM_SPMU = 778,
+	GAUDI2_EVENT_HDMA7_BM_SPMU = 780,
+	GAUDI2_EVENT_HDMA4_BM_SPMU = 782,
+	GAUDI2_EVENT_HDMA5_BM_SPMU = 784,
+	GAUDI2_EVENT_KDMA_BM_SPMU = 786,
+	GAUDI2_EVENT_PDMA0_BM_SPMU = 788,
+	GAUDI2_EVENT_PDMA1_BM_SPMU = 789,
+	GAUDI2_EVENT_HBM0_MC0_SPI = 790,
+	GAUDI2_EVENT_HBM0_MC1_SPI = 791,
+	GAUDI2_EVENT_HBM1_MC0_SPI = 792,
+	GAUDI2_EVENT_HBM1_MC1_SPI = 793,
+	GAUDI2_EVENT_HBM2_MC0_SPI = 794,
+	GAUDI2_EVENT_HBM2_MC1_SPI = 795,
+	GAUDI2_EVENT_HBM3_MC0_SPI = 796,
+	GAUDI2_EVENT_HBM3_MC1_SPI = 797,
+	GAUDI2_EVENT_HBM4_MC0_SPI = 798,
+	GAUDI2_EVENT_HBM4_MC1_SPI = 799,
+	GAUDI2_EVENT_HBM5_MC0_SPI = 800,
+	GAUDI2_EVENT_HBM5_MC1_SPI = 801,
+	GAUDI2_EVENT_CPU_BMON = 802,
+	GAUDI2_EVENT_CPU_BMON_1 = 803,
+	GAUDI2_EVENT_TS_A_SOUTH_0 = 804,
+	GAUDI2_EVENT_TS_A_NORTH_1 = 805,
+	GAUDI2_EVENT_TS_A_EAST_2 = 806,
+	GAUDI2_EVENT_TS_A_WEST_3 = 807,
+	GAUDI2_EVENT_PSOC0_GPIO_79_64 = 812,
+	GAUDI2_EVENT_PSOC1_GPIO_63_48 = 813,
+	GAUDI2_EVENT_PSOC2_GPIO_47_32 = 814,
+	GAUDI2_EVENT_PSOC3_GPIO_31_16 = 815,
+	GAUDI2_EVENT_PSOC4_GPIO_15_0 = 816,
+	GAUDI2_EVENT_PSOC58_RPM_READY = 870,
+	GAUDI2_EVENT_PSOC59_RPM_ERROR_OR_DRAIN = 871,
+	GAUDI2_EVENT_PSOC60_GPIO_95_80 = 872,
+	GAUDI2_EVENT_PSOC62_QSPI_INTERRUPT = 874,
+	GAUDI2_EVENT_PSOC63_RAZWI_OR_PID_MIN_MAX_INTERRUPT = 875,
+	GAUDI2_EVENT_PSOC64_ADC0_INTERRUPT = 876,
+	GAUDI2_EVENT_PSOC65_PID = 877,
+	GAUDI2_EVENT_PSOC66_IC_SLV_SMBALERT_DET_INTR = 878,
+	GAUDI2_EVENT_PSOC75_SVID0_PARITY_ERROR_INTERRUPT = 887,
+	GAUDI2_EVENT_PSOC76_SVID1_PARITY_ERROR_INTERRUPT = 888,
+	GAUDI2_EVENT_PSOC77_SVID_PARITY_ERROR_INTERRUPT = 889,
+	GAUDI2_EVENT_PSOC78_SVID0_READY_INTERRUPT = 890,
+	GAUDI2_EVENT_PSOC79_SVID1_READY_INTERRUPT = 891,
+	GAUDI2_EVENT_PSOC80_SVID2_READY_INTERRUPT = 892,
+	GAUDI2_EVENT_PSOC81_ADC1_INTERRUPT = 893,
+	GAUDI2_EVENT_PSOC82_SVID_COMBINED_ALERT_INTERRUPT = 894,
+	GAUDI2_EVENT_PSOC83_SPI_WARE_OUT_ATTACK_OR_ARP = 895,
+	GAUDI2_EVENT_DEC0_SPI = 896,
+	GAUDI2_EVENT_DEC0_BMON_SPMU = 897,
+	GAUDI2_EVENT_DEC1_SPI = 898,
+	GAUDI2_EVENT_DEC1_BMON_SPMU = 899,
+	GAUDI2_EVENT_DEC2_SPI = 900,
+	GAUDI2_EVENT_DEC2_BMON_SPMU = 901,
+	GAUDI2_EVENT_DEC3_SPI = 902,
+	GAUDI2_EVENT_DEC3_BMON_SPMU = 903,
+	GAUDI2_EVENT_DEC4_SPI = 904,
+	GAUDI2_EVENT_DEC4_BMON_SPMU = 905,
+	GAUDI2_EVENT_DEC5_SPI = 906,
+	GAUDI2_EVENT_DEC5_BMON_SPMU = 907,
+	GAUDI2_EVENT_DEC6_SPI = 908,
+	GAUDI2_EVENT_DEC6_BMON_SPMU = 909,
+	GAUDI2_EVENT_DEC7_SPI = 910,
+	GAUDI2_EVENT_DEC7_BMON_SPMU = 911,
+	GAUDI2_EVENT_DEC8_SPI = 912,
+	GAUDI2_EVENT_DEC8_BMON_SPMU = 913,
+	GAUDI2_EVENT_DEC9_SPI = 914,
+	GAUDI2_EVENT_DEC9_BMON_SPMU = 915,
+	GAUDI2_EVENT_HIF0_SPI_WARN = 918,
+	GAUDI2_EVENT_HIF1_SPI_WARN = 920,
+	GAUDI2_EVENT_HIF2_SPI_WARN = 922,
+	GAUDI2_EVENT_HIF3_SPI_WARN = 924,
+	GAUDI2_EVENT_HIF8_SPI_WARN = 926,
+	GAUDI2_EVENT_HIF9_SPI_WARN = 928,
+	GAUDI2_EVENT_HIF10_SPI_WARN = 930,
+	GAUDI2_EVENT_HIF11_SPI_WARN = 932,
+	GAUDI2_EVENT_HIF7_SPI_WARN = 934,
+	GAUDI2_EVENT_HIF6_SPI_WARN = 936,
+	GAUDI2_EVENT_HIF5_SPI_WARN = 938,
+	GAUDI2_EVENT_HIF4_SPI_WARN = 940,
+	GAUDI2_EVENT_HIF15_SPI_WARN = 942,
+	GAUDI2_EVENT_HIF14_SPI_WARN = 944,
+	GAUDI2_EVENT_HIF13_SPI_WARN = 946,
+	GAUDI2_EVENT_HIF12_SPI_WARN = 948,
+	GAUDI2_EVENT_NIC0_BMON_SPMU = 951,
+	GAUDI2_EVENT_NIC0_SW_ERROR = 952,
+	GAUDI2_EVENT_NIC1_BMON_SPMU = 955,
+	GAUDI2_EVENT_NIC1_SW_ERROR = 956,
+	GAUDI2_EVENT_NIC2_BMON_SPMU = 959,
+	GAUDI2_EVENT_NIC2_SW_ERROR = 960,
+	GAUDI2_EVENT_NIC3_BMON_SPMU = 963,
+	GAUDI2_EVENT_NIC3_SW_ERROR = 964,
+	GAUDI2_EVENT_NIC4_BMON_SPMU = 967,
+	GAUDI2_EVENT_NIC4_SW_ERROR = 968,
+	GAUDI2_EVENT_NIC5_BMON_SPMU = 971,
+	GAUDI2_EVENT_NIC5_SW_ERROR = 972,
+	GAUDI2_EVENT_NIC6_BMON_SPMU = 975,
+	GAUDI2_EVENT_NIC6_SW_ERROR = 976,
+	GAUDI2_EVENT_NIC7_BMON_SPMU = 979,
+	GAUDI2_EVENT_NIC7_SW_ERROR = 980,
+	GAUDI2_EVENT_NIC8_BMON_SPMU = 983,
+	GAUDI2_EVENT_NIC8_SW_ERROR = 984,
+	GAUDI2_EVENT_NIC9_BMON_SPMU = 987,
+	GAUDI2_EVENT_NIC9_SW_ERROR = 988,
+	GAUDI2_EVENT_NIC10_BMON_SPMU = 991,
+	GAUDI2_EVENT_NIC10_SW_ERROR = 992,
+	GAUDI2_EVENT_NIC11_BMON_SPMU = 995,
+	GAUDI2_EVENT_NIC11_SW_ERROR = 996,
+	GAUDI2_EVENT_ROTATOR0_SERR = 1118,
+	GAUDI2_EVENT_ROTATOR1_SERR = 1119,
+	GAUDI2_EVENT_ROTATOR0_DERR = 1120,
+	GAUDI2_EVENT_ROTATOR1_DERR = 1121,
+	GAUDI2_EVENT_ROTATOR0_AXI_ERROR_RESPONSE = 1122,
+	GAUDI2_EVENT_ROTATOR1_AXI_ERROR_RESPONSE = 1123,
+	GAUDI2_EVENT_ROTATOR0_BMON_SPMU = 1126,
+	GAUDI2_EVENT_ROTATOR1_BMON_SPMU = 1128,
+	GAUDI2_EVENT_SM0_BMON_SPMU = 1130,
+	GAUDI2_EVENT_SM1_BMON_SPMU = 1131,
+	GAUDI2_EVENT_SM2_BMON_SPMU = 1132,
+	GAUDI2_EVENT_SM3_BMON_SPMU = 1133,
+	GAUDI2_EVENT_PSOC_DMA_QM = 1174,
+	GAUDI2_EVENT_TPC0_QM = 1206,
+	GAUDI2_EVENT_TPC1_QM = 1207,
+	GAUDI2_EVENT_TPC2_QM = 1208,
+	GAUDI2_EVENT_TPC3_QM = 1209,
+	GAUDI2_EVENT_TPC4_QM = 1210,
+	GAUDI2_EVENT_TPC5_QM = 1211,
+	GAUDI2_EVENT_TPC6_QM = 1212,
+	GAUDI2_EVENT_TPC7_QM = 1213,
+	GAUDI2_EVENT_TPC8_QM = 1214,
+	GAUDI2_EVENT_TPC9_QM = 1215,
+	GAUDI2_EVENT_TPC10_QM = 1216,
+	GAUDI2_EVENT_TPC11_QM = 1217,
+	GAUDI2_EVENT_TPC12_QM = 1218,
+	GAUDI2_EVENT_TPC13_QM = 1219,
+	GAUDI2_EVENT_TPC14_QM = 1220,
+	GAUDI2_EVENT_TPC15_QM = 1221,
+	GAUDI2_EVENT_TPC16_QM = 1222,
+	GAUDI2_EVENT_TPC17_QM = 1223,
+	GAUDI2_EVENT_TPC18_QM = 1224,
+	GAUDI2_EVENT_TPC19_QM = 1225,
+	GAUDI2_EVENT_TPC20_QM = 1226,
+	GAUDI2_EVENT_TPC21_QM = 1227,
+	GAUDI2_EVENT_TPC22_QM = 1228,
+	GAUDI2_EVENT_TPC23_QM = 1229,
+	GAUDI2_EVENT_TPC24_QM = 1230,
+	GAUDI2_EVENT_MME0_QM = 1232,
+	GAUDI2_EVENT_MME1_QM = 1233,
+	GAUDI2_EVENT_MME2_QM = 1234,
+	GAUDI2_EVENT_MME3_QM = 1235,
+	GAUDI2_EVENT_HDMA2_QM = 1236,
+	GAUDI2_EVENT_HDMA3_QM = 1237,
+	GAUDI2_EVENT_HDMA0_QM = 1238,
+	GAUDI2_EVENT_HDMA1_QM = 1239,
+	GAUDI2_EVENT_HDMA6_QM = 1240,
+	GAUDI2_EVENT_HDMA7_QM = 1241,
+	GAUDI2_EVENT_HDMA4_QM = 1242,
+	GAUDI2_EVENT_HDMA5_QM = 1243,
+	GAUDI2_EVENT_PDMA0_QM = 1244,
+	GAUDI2_EVENT_PDMA1_QM = 1245,
+	GAUDI2_EVENT_CPU_PI_UPDATE = 1246,
+	GAUDI2_EVENT_CPU_HALT_MACHINE = 1247,
+	GAUDI2_EVENT_CPU_INTS_REGISTER = 1248,
+	GAUDI2_EVENT_ROTATOR0_ROT0_QM = 1249,
+	GAUDI2_EVENT_ROTATOR1_ROT1_QM = 1250,
+	GAUDI2_EVENT_CPU_SOFT_RESET = 1251,
+	GAUDI2_EVENT_CPU_CPLD_SHUTDOWN_CAUSE = 1252,
+	GAUDI2_EVENT_CPU_FIX_POWER_ENV_S = 1253,
+	GAUDI2_EVENT_CPU_FIX_POWER_ENV_E = 1254,
+	GAUDI2_EVENT_CPU_FIX_THERMAL_ENV_S = 1255,
+	GAUDI2_EVENT_CPU_FIX_THERMAL_ENV_E = 1256,
+	GAUDI2_EVENT_CPU_CPLD_SHUTDOWN_EVENT = 1257,
+	GAUDI2_EVENT_CPU_PKT_QUEUE_OUT_SYNC = 1258,
+	GAUDI2_EVENT_HDMA2_CORE = 1259,
+	GAUDI2_EVENT_HDMA3_CORE = 1260,
+	GAUDI2_EVENT_HDMA0_CORE = 1261,
+	GAUDI2_EVENT_HDMA1_CORE = 1262,
+	GAUDI2_EVENT_HDMA6_CORE = 1263,
+	GAUDI2_EVENT_HDMA7_CORE = 1264,
+	GAUDI2_EVENT_HDMA4_CORE = 1265,
+	GAUDI2_EVENT_HDMA5_CORE = 1266,
+	GAUDI2_EVENT_PDMA0_CORE = 1267,
+	GAUDI2_EVENT_PDMA1_CORE = 1268,
+	GAUDI2_EVENT_KDMA0_CORE = 1269,
+	GAUDI2_EVENT_NIC0_QM0 = 1270,
+	GAUDI2_EVENT_NIC0_QM1 = 1271,
+	GAUDI2_EVENT_NIC1_QM0 = 1272,
+	GAUDI2_EVENT_NIC1_QM1 = 1273,
+	GAUDI2_EVENT_NIC2_QM0 = 1274,
+	GAUDI2_EVENT_NIC2_QM1 = 1275,
+	GAUDI2_EVENT_NIC3_QM0 = 1276,
+	GAUDI2_EVENT_NIC3_QM1 = 1277,
+	GAUDI2_EVENT_NIC4_QM0 = 1278,
+	GAUDI2_EVENT_NIC4_QM1 = 1279,
+	GAUDI2_EVENT_NIC5_QM0 = 1280,
+	GAUDI2_EVENT_NIC5_QM1 = 1281,
+	GAUDI2_EVENT_NIC6_QM0 = 1282,
+	GAUDI2_EVENT_NIC6_QM1 = 1283,
+	GAUDI2_EVENT_NIC7_QM0 = 1284,
+	GAUDI2_EVENT_NIC7_QM1 = 1285,
+	GAUDI2_EVENT_NIC8_QM0 = 1286,
+	GAUDI2_EVENT_NIC8_QM1 = 1287,
+	GAUDI2_EVENT_NIC9_QM0 = 1288,
+	GAUDI2_EVENT_NIC9_QM1 = 1289,
+	GAUDI2_EVENT_NIC10_QM0 = 1290,
+	GAUDI2_EVENT_NIC10_QM1 = 1291,
+	GAUDI2_EVENT_NIC11_QM0 = 1292,
+	GAUDI2_EVENT_NIC11_QM1 = 1293,
+	GAUDI2_EVENT_CPU_PKT_SANITY_FAILED = 1294,
+	GAUDI2_EVENT_CPU0_STATUS_NIC0_ENG0 = 1295,
+	GAUDI2_EVENT_CPU0_STATUS_NIC0_ENG1 = 1296,
+	GAUDI2_EVENT_CPU1_STATUS_NIC1_ENG0 = 1297,
+	GAUDI2_EVENT_CPU1_STATUS_NIC1_ENG1 = 1298,
+	GAUDI2_EVENT_CPU2_STATUS_NIC2_ENG0 = 1299,
+	GAUDI2_EVENT_CPU2_STATUS_NIC2_ENG1 = 1300,
+	GAUDI2_EVENT_CPU3_STATUS_NIC3_ENG0 = 1301,
+	GAUDI2_EVENT_CPU3_STATUS_NIC3_ENG1 = 1302,
+	GAUDI2_EVENT_CPU4_STATUS_NIC4_ENG0 = 1303,
+	GAUDI2_EVENT_CPU4_STATUS_NIC4_ENG1 = 1304,
+	GAUDI2_EVENT_CPU5_STATUS_NIC5_ENG0 = 1305,
+	GAUDI2_EVENT_CPU5_STATUS_NIC5_ENG1 = 1306,
+	GAUDI2_EVENT_CPU6_STATUS_NIC6_ENG0 = 1307,
+	GAUDI2_EVENT_CPU6_STATUS_NIC6_ENG1 = 1308,
+	GAUDI2_EVENT_CPU7_STATUS_NIC7_ENG0 = 1309,
+	GAUDI2_EVENT_CPU7_STATUS_NIC7_ENG1 = 1310,
+	GAUDI2_EVENT_CPU8_STATUS_NIC8_ENG0 = 1311,
+	GAUDI2_EVENT_CPU8_STATUS_NIC8_ENG1 = 1312,
+	GAUDI2_EVENT_CPU9_STATUS_NIC9_ENG0 = 1313,
+	GAUDI2_EVENT_CPU9_STATUS_NIC9_ENG1 = 1314,
+	GAUDI2_EVENT_CPU10_STATUS_NIC10_ENG0 = 1315,
+	GAUDI2_EVENT_CPU10_STATUS_NIC10_ENG1 = 1316,
+	GAUDI2_EVENT_CPU11_STATUS_NIC11_ENG0 = 1317,
+	GAUDI2_EVENT_CPU11_STATUS_NIC11_ENG1 = 1318,
+	GAUDI2_EVENT_ARC_DCCM_FULL = 1319,
+	GAUDI2_EVENT_CPU_FP32_NOT_SUPPORTED = 1320,
+	GAUDI2_EVENT_CPU_DEV_RESET_REQ = 1321,
+	GAUDI2_EVENT_ARC_PWR_BRK_ENTRY = 1322,
+	GAUDI2_EVENT_ARC_PWR_BRK_EXT = 1323,
+	GAUDI2_EVENT_ARC_PWR_RD_MODE0 = 1324,
+	GAUDI2_EVENT_ARC_PWR_RD_MODE1 = 1325,
+	GAUDI2_EVENT_ARC_PWR_RD_MODE2 = 1326,
+	GAUDI2_EVENT_ARC_PWR_RD_MODE3 = 1327,
+	GAUDI2_EVENT_ARC_EQ_HEARTBEAT = 1328,
+	GAUDI2_EVENT_SIZE,
+};
+
+#endif /* __GAUDI2_ASYNC_EVENTS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/gaudi2_async_ids_map_extended.h b/drivers/accel/habanalabs/include/gaudi2/gaudi2_async_ids_map_extended.h
new file mode 100644
index 000000000000..82d639990cca
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/gaudi2_async_ids_map_extended.h
@@ -0,0 +1,2692 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2018-2022 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+enum event_reset_type {
+	EVENT_RESET_TYPE_NONE,
+	EVENT_RESET_TYPE_COMPUTE,
+	EVENT_RESET_TYPE_HARD,
+};
+
+#ifndef __GAUDI2_ASYNC_IDS_MAP_EVENTS_EXT_H_
+#define __GAUDI2_ASYNC_IDS_MAP_EVENTS_EXT_H_
+
+struct gaudi2_async_events_ids_map {
+	int fc_id;
+	int cpu_id;
+	int valid;
+	int msg;
+	int reset;
+	char name[64];
+};
+
+static struct gaudi2_async_events_ids_map gaudi2_irq_map_table[] = {
+	{ .fc_id = 0, .cpu_id = 0, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1, .cpu_id = 1, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 2, .cpu_id = 2, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 3, .cpu_id = 3, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 4, .cpu_id = 4, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 5, .cpu_id = 5, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 6, .cpu_id = 6, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 7, .cpu_id = 7, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 8, .cpu_id = 8, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 9, .cpu_id = 9, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 10, .cpu_id = 10, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 11, .cpu_id = 11, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 12, .cpu_id = 12, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 13, .cpu_id = 13, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 14, .cpu_id = 14, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 15, .cpu_id = 15, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 16, .cpu_id = 16, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 17, .cpu_id = 17, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 18, .cpu_id = 18, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 19, .cpu_id = 19, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 20, .cpu_id = 20, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 21, .cpu_id = 21, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 22, .cpu_id = 22, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 23, .cpu_id = 23, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 24, .cpu_id = 24, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 25, .cpu_id = 25, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 26, .cpu_id = 26, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 27, .cpu_id = 27, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 28, .cpu_id = 28, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 29, .cpu_id = 29, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 30, .cpu_id = 30, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 31, .cpu_id = 31, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 32, .cpu_id = 32, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "PCIE_CORE_SERR" },
+	{ .fc_id = 33, .cpu_id = 33, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "PCIE_CORE_DERR" },
+	{ .fc_id = 34, .cpu_id = 34, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "PCIE_IF_SERR" },
+	{ .fc_id = 35, .cpu_id = 35, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "PCIE_IF_DERR" },
+	{ .fc_id = 36, .cpu_id = 36, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "PCIE_PHY_SERR" },
+	{ .fc_id = 37, .cpu_id = 37, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "PCIE_PHY_DERR" },
+	{ .fc_id = 38, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC0_ECC_SERR" },
+	{ .fc_id = 39, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC1_ECC_SERR" },
+	{ .fc_id = 40, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC2_ECC_SERR" },
+	{ .fc_id = 41, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC3_ECC_SERR" },
+	{ .fc_id = 42, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC4_ECC_SERR" },
+	{ .fc_id = 43, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC5_ECC_SERR" },
+	{ .fc_id = 44, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC6_ECC_SERR" },
+	{ .fc_id = 45, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC7_ECC_SERR" },
+	{ .fc_id = 46, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC8_ECC_SERR" },
+	{ .fc_id = 47, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC9_ECC_SERR" },
+	{ .fc_id = 48, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC10_ECC_SERR" },
+	{ .fc_id = 49, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC11_ECC_SERR" },
+	{ .fc_id = 50, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC12_ECC_SERR" },
+	{ .fc_id = 51, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC13_ECC_SERR" },
+	{ .fc_id = 52, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC14_ECC_SERR" },
+	{ .fc_id = 53, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC15_ECC_SERR" },
+	{ .fc_id = 54, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC16_ECC_SERR" },
+	{ .fc_id = 55, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC17_ECC_SERR" },
+	{ .fc_id = 56, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC18_ECC_SERR" },
+	{ .fc_id = 57, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC19_ECC_SERR" },
+	{ .fc_id = 58, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC20_ECC_SERR" },
+	{ .fc_id = 59, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC21_ECC_SERR" },
+	{ .fc_id = 60, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC22_ECC_SERR" },
+	{ .fc_id = 61, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC23_ECC_SERR" },
+	{ .fc_id = 62, .cpu_id = 38, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC24_ECC_SERR" },
+	{ .fc_id = 63, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "TPC0_ECC_DERR" },
+	{ .fc_id = 64, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "TPC1_ECC_DERR" },
+	{ .fc_id = 65, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "TPC2_ECC_DERR" },
+	{ .fc_id = 66, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "TPC3_ECC_DERR" },
+	{ .fc_id = 67, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "TPC4_ECC_DERR" },
+	{ .fc_id = 68, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "TPC5_ECC_DERR" },
+	{ .fc_id = 69, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "TPC6_ECC_DERR" },
+	{ .fc_id = 70, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "TPC7_ECC_DERR" },
+	{ .fc_id = 71, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "TPC8_ECC_DERR" },
+	{ .fc_id = 72, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "TPC9_ECC_DERR" },
+	{ .fc_id = 73, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "TPC10_ECC_DERR" },
+	{ .fc_id = 74, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "TPC11_ECC_DERR" },
+	{ .fc_id = 75, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "TPC12_ECC_DERR" },
+	{ .fc_id = 76, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "TPC13_ECC_DERR" },
+	{ .fc_id = 77, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "TPC14_ECC_DERR" },
+	{ .fc_id = 78, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "TPC15_ECC_DERR" },
+	{ .fc_id = 79, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "TPC16_ECC_DERR" },
+	{ .fc_id = 80, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "TPC17_ECC_DERR" },
+	{ .fc_id = 81, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "TPC18_ECC_DERR" },
+	{ .fc_id = 82, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "TPC19_ECC_DERR" },
+	{ .fc_id = 83, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "TPC20_ECC_DERR" },
+	{ .fc_id = 84, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "TPC21_ECC_DERR" },
+	{ .fc_id = 85, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "TPC22_ECC_DERR" },
+	{ .fc_id = 86, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "TPC23_ECC_DERR" },
+	{ .fc_id = 87, .cpu_id = 39, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "TPC24_ECC_DERR" },
+	{ .fc_id = 88, .cpu_id = 40, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "MME0_SBTE0_ECC_SERR" },
+	{ .fc_id = 89, .cpu_id = 40, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "MME0_SBTE1_ECC_SERR" },
+	{ .fc_id = 90, .cpu_id = 40, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "MME0_SBTE2_ECC_SERR" },
+	{ .fc_id = 91, .cpu_id = 40, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "MME0_SBTE3_ECC_SERR" },
+	{ .fc_id = 92, .cpu_id = 40, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "MME0_SBTE4_ECC_SERR" },
+	{ .fc_id = 93, .cpu_id = 40, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "MME0_CTRL_ECC_SERR" },
+	{ .fc_id = 94, .cpu_id = 40, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "MME0_WAP_ECC_SERR" },
+	{ .fc_id = 95, .cpu_id = 41, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "MME1_SBTE0_ECC_SERR" },
+	{ .fc_id = 96, .cpu_id = 41, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "MME1_SBTE1_ECC_SERR" },
+	{ .fc_id = 97, .cpu_id = 41, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "MME1_SBTE2_ECC_SERR" },
+	{ .fc_id = 98, .cpu_id = 41, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "MME1_SBTE3_ECC_SERR" },
+	{ .fc_id = 99, .cpu_id = 41, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "MME1_SBTE4_ECC_SERR" },
+	{ .fc_id = 100, .cpu_id = 41, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "MME1_CTRL_ECC_SERR" },
+	{ .fc_id = 101, .cpu_id = 41, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "MME1_WAP_ECC_SERR" },
+	{ .fc_id = 102, .cpu_id = 42, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "MME2_SBTE0_ECC_SERR" },
+	{ .fc_id = 103, .cpu_id = 42, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "MME2_SBTE1_ECC_SERR" },
+	{ .fc_id = 104, .cpu_id = 42, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "MME2_SBTE2_ECC_SERR" },
+	{ .fc_id = 105, .cpu_id = 42, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "MME2_SBTE3_ECC_SERR" },
+	{ .fc_id = 106, .cpu_id = 42, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "MME2_SBTE4_ECC_SERR" },
+	{ .fc_id = 107, .cpu_id = 42, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "MME2_CTRL_ECC_SERR" },
+	{ .fc_id = 108, .cpu_id = 42, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "MME2_WAP_ECC_SERR" },
+	{ .fc_id = 109, .cpu_id = 43, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "MME3_SBTE0_ECC_SERR" },
+	{ .fc_id = 110, .cpu_id = 43, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "MME3_SBTE1_ECC_SERR" },
+	{ .fc_id = 111, .cpu_id = 43, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "MME3_SBTE2_ECC_SERR" },
+	{ .fc_id = 112, .cpu_id = 43, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "MME3_SBTE3_ECC_SERR" },
+	{ .fc_id = 113, .cpu_id = 43, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "MME3_SBTE4_ECC_SERR" },
+	{ .fc_id = 114, .cpu_id = 43, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "MME3_CTRL_ECC_SERR" },
+	{ .fc_id = 115, .cpu_id = 43, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "MME3_WAP_ECC_SERR" },
+	{ .fc_id = 116, .cpu_id = 44, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "MME0_SBTE0_ECC_DERR" },
+	{ .fc_id = 117, .cpu_id = 44, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "MME0_SBTE1_ECC_DERR" },
+	{ .fc_id = 118, .cpu_id = 44, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "MME0_SBTE2_ECC_DERR" },
+	{ .fc_id = 119, .cpu_id = 44, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "MME0_SBTE3_ECC_DERR" },
+	{ .fc_id = 120, .cpu_id = 44, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "MME0_SBTE4_ECC_DERR" },
+	{ .fc_id = 121, .cpu_id = 44, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "MME0_CTRL_ECC_DERR" },
+	{ .fc_id = 122, .cpu_id = 44, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "MME0_WAP_ECC_DERR" },
+	{ .fc_id = 123, .cpu_id = 45, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "MME1_SBTE0_ECC_DERR" },
+	{ .fc_id = 124, .cpu_id = 45, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "MME1_SBTE1_ECC_DERR" },
+	{ .fc_id = 125, .cpu_id = 45, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "MME1_SBTE2_ECC_DERR" },
+	{ .fc_id = 126, .cpu_id = 45, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "MME1_SBTE3_ECC_DERR" },
+	{ .fc_id = 127, .cpu_id = 45, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "MME1_SBTE4_ECC_DERR" },
+	{ .fc_id = 128, .cpu_id = 45, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "MME1_CTRL_ECC_DERR" },
+	{ .fc_id = 129, .cpu_id = 45, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "MME1_WAP_ECC_DERR" },
+	{ .fc_id = 130, .cpu_id = 46, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "MME2_SBTE0_ECC_DERR" },
+	{ .fc_id = 131, .cpu_id = 46, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "MME2_SBTE1_ECC_DERR" },
+	{ .fc_id = 132, .cpu_id = 46, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "MME2_SBTE2_ECC_DERR" },
+	{ .fc_id = 133, .cpu_id = 46, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "MME2_SBTE3_ECC_DERR" },
+	{ .fc_id = 134, .cpu_id = 46, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "MME2_SBTE4_ECC_DERR" },
+	{ .fc_id = 135, .cpu_id = 46, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "MME2_CTRL_ECC_DERR" },
+	{ .fc_id = 136, .cpu_id = 46, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "MME2_WAP_ECC_DERR" },
+	{ .fc_id = 137, .cpu_id = 47, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "MME3_SBTE0_ECC_DERR" },
+	{ .fc_id = 138, .cpu_id = 47, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "MME3_SBTE1_ECC_DERR" },
+	{ .fc_id = 139, .cpu_id = 47, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "MME3_SBTE2_ECC_DERR" },
+	{ .fc_id = 140, .cpu_id = 47, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "MME3_SBTE3_ECC_DERR" },
+	{ .fc_id = 141, .cpu_id = 47, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "MME3_SBTE4_ECC_DERR" },
+	{ .fc_id = 142, .cpu_id = 47, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "MME3_CTRL_ECC_DERR" },
+	{ .fc_id = 143, .cpu_id = 47, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "MME3_WAP_ECC_DERR" },
+	{ .fc_id = 144, .cpu_id = 48, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "EDMA2_ECC_SERR" },
+	{ .fc_id = 145, .cpu_id = 48, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "EDMA3_ECC_SERR" },
+	{ .fc_id = 146, .cpu_id = 48, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "EDMA0_ECC_SERR" },
+	{ .fc_id = 147, .cpu_id = 48, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "EDMA1_ECC_SERR" },
+	{ .fc_id = 148, .cpu_id = 48, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "EDMA6_ECC_SERR" },
+	{ .fc_id = 149, .cpu_id = 48, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "EDMA7_ECC_SERR" },
+	{ .fc_id = 150, .cpu_id = 48, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "EDMA4_ECC_SERR" },
+	{ .fc_id = 151, .cpu_id = 48, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "EDMA5_ECC_SERR" },
+	{ .fc_id = 152, .cpu_id = 49, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "EDMA2_ECC_DERR" },
+	{ .fc_id = 153, .cpu_id = 49, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "EDMA3_ECC_DERR" },
+	{ .fc_id = 154, .cpu_id = 49, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "EDMA0_ECC_DERR" },
+	{ .fc_id = 155, .cpu_id = 49, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "EDMA1_ECC_DERR" },
+	{ .fc_id = 156, .cpu_id = 49, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "EDMA6_ECC_DERR" },
+	{ .fc_id = 157, .cpu_id = 49, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "EDMA7_ECC_DERR" },
+	{ .fc_id = 158, .cpu_id = 49, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "EDMA4_ECC_DERR" },
+	{ .fc_id = 159, .cpu_id = 49, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "EDMA5_ECC_DERR" },
+	{ .fc_id = 160, .cpu_id = 50, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "KDMA0_ECC_SERR" },
+	{ .fc_id = 161, .cpu_id = 51, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "PDMA0_ECC_SERR" },
+	{ .fc_id = 162, .cpu_id = 51, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "PDMA1_ECC_SERR" },
+	{ .fc_id = 163, .cpu_id = 52, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "KDMA0_ECC_DERR" },
+	{ .fc_id = 164, .cpu_id = 53, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "PDMA0_ECC_DERR" },
+	{ .fc_id = 165, .cpu_id = 53, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "PDMA1_ECC_DERR" },
+	{ .fc_id = 166, .cpu_id = 54, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "CPU_IF_ECC_SERR" },
+	{ .fc_id = 167, .cpu_id = 55, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "CPU_IF_ECC_DERR" },
+	{ .fc_id = 168, .cpu_id = 56, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "PSOC_MEM_SERR" },
+	{ .fc_id = 169, .cpu_id = 57, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "PSOC_MEM_DERR" },
+	{ .fc_id = 170, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "SRAM0_ECC_SERR" },
+	{ .fc_id = 171, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "SRAM1_ECC_SERR" },
+	{ .fc_id = 172, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "SRAM2_ECC_SERR" },
+	{ .fc_id = 173, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "SRAM3_ECC_SERR" },
+	{ .fc_id = 174, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "SRAM4_ECC_SERR" },
+	{ .fc_id = 175, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "SRAM5_ECC_SERR" },
+	{ .fc_id = 176, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "SRAM6_ECC_SERR" },
+	{ .fc_id = 177, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "SRAM7_ECC_SERR" },
+	{ .fc_id = 178, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "SRAM8_ECC_SERR" },
+	{ .fc_id = 179, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "SRAM9_ECC_SERR" },
+	{ .fc_id = 180, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "SRAM10_ECC_SERR" },
+	{ .fc_id = 181, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "SRAM11_ECC_SERR" },
+	{ .fc_id = 182, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "SRAM12_ECC_SERR" },
+	{ .fc_id = 183, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "SRAM13_ECC_SERR" },
+	{ .fc_id = 184, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "SRAM14_ECC_SERR" },
+	{ .fc_id = 185, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "SRAM15_ECC_SERR" },
+	{ .fc_id = 186, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "SRAM16_ECC_SERR" },
+	{ .fc_id = 187, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "SRAM17_ECC_SERR" },
+	{ .fc_id = 188, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "SRAM18_ECC_SERR" },
+	{ .fc_id = 189, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "SRAM19_ECC_SERR" },
+	{ .fc_id = 190, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "SRAM20_ECC_SERR" },
+	{ .fc_id = 191, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "SRAM21_ECC_SERR" },
+	{ .fc_id = 192, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "SRAM22_ECC_SERR" },
+	{ .fc_id = 193, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "SRAM23_ECC_SERR" },
+	{ .fc_id = 194, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "SRAM24_ECC_SERR" },
+	{ .fc_id = 195, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "SRAM25_ECC_SERR" },
+	{ .fc_id = 196, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "SRAM26_ECC_SERR" },
+	{ .fc_id = 197, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "SRAM27_ECC_SERR" },
+	{ .fc_id = 198, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "SRAM28_ECC_SERR" },
+	{ .fc_id = 199, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "SRAM29_ECC_SERR" },
+	{ .fc_id = 200, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "SRAM30_ECC_SERR" },
+	{ .fc_id = 201, .cpu_id = 58, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "SRAM31_ECC_SERR" },
+	{ .fc_id = 202, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "SRAM0_ECC_DERR" },
+	{ .fc_id = 203, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "SRAM1_ECC_DERR" },
+	{ .fc_id = 204, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "SRAM2_ECC_DERR" },
+	{ .fc_id = 205, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "SRAM3_ECC_DERR" },
+	{ .fc_id = 206, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "SRAM4_ECC_DERR" },
+	{ .fc_id = 207, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "SRAM5_ECC_DERR" },
+	{ .fc_id = 208, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "SRAM6_ECC_DERR" },
+	{ .fc_id = 209, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "SRAM7_ECC_DERR" },
+	{ .fc_id = 210, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "SRAM8_ECC_DERR" },
+	{ .fc_id = 211, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "SRAM9_ECC_DERR" },
+	{ .fc_id = 212, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "SRAM10_ECC_DERR" },
+	{ .fc_id = 213, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "SRAM11_ECC_DERR" },
+	{ .fc_id = 214, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "SRAM12_ECC_DERR" },
+	{ .fc_id = 215, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "SRAM13_ECC_DERR" },
+	{ .fc_id = 216, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "SRAM14_ECC_DERR" },
+	{ .fc_id = 217, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "SRAM15_ECC_DERR" },
+	{ .fc_id = 218, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "SRAM16_ECC_DERR" },
+	{ .fc_id = 219, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "SRAM17_ECC_DERR" },
+	{ .fc_id = 220, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "SRAM18_ECC_DERR" },
+	{ .fc_id = 221, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "SRAM19_ECC_DERR" },
+	{ .fc_id = 222, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "SRAM20_ECC_DERR" },
+	{ .fc_id = 223, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "SRAM21_ECC_DERR" },
+	{ .fc_id = 224, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "SRAM22_ECC_DERR" },
+	{ .fc_id = 225, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "SRAM23_ECC_DERR" },
+	{ .fc_id = 226, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "SRAM24_ECC_DERR" },
+	{ .fc_id = 227, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "SRAM25_ECC_DERR" },
+	{ .fc_id = 228, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "SRAM26_ECC_DERR" },
+	{ .fc_id = 229, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "SRAM27_ECC_DERR" },
+	{ .fc_id = 230, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "SRAM28_ECC_DERR" },
+	{ .fc_id = 231, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "SRAM29_ECC_DERR" },
+	{ .fc_id = 232, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "SRAM30_ECC_DERR" },
+	{ .fc_id = 233, .cpu_id = 59, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "SRAM31_ECC_DERR" },
+	{ .fc_id = 234, .cpu_id = 60, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "GIC500" },
+	{ .fc_id = 235, .cpu_id = 61, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HBM_0_MC0_ECC_SERR" },
+	{ .fc_id = 236, .cpu_id = 61, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HBM_1_MC0_ECC_SERR" },
+	{ .fc_id = 237, .cpu_id = 61, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HBM_2_MC0_ECC_SERR" },
+	{ .fc_id = 238, .cpu_id = 61, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HBM_3_MC0_ECC_SERR" },
+	{ .fc_id = 239, .cpu_id = 61, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HBM_4_MC0_ECC_SERR" },
+	{ .fc_id = 240, .cpu_id = 61, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HBM_5_MC0_ECC_SERR" },
+	{ .fc_id = 241, .cpu_id = 61, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HBM_0_MC1_ECC_SERR" },
+	{ .fc_id = 242, .cpu_id = 61, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HBM_1_MC1_ECC_SERR" },
+	{ .fc_id = 243, .cpu_id = 61, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HBM_2_MC1_ECC_SERR" },
+	{ .fc_id = 244, .cpu_id = 61, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HBM_3_MC1_ECC_SERR" },
+	{ .fc_id = 245, .cpu_id = 61, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HBM_4_MC1_ECC_SERR" },
+	{ .fc_id = 246, .cpu_id = 61, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HBM_5_MC1_ECC_SERR" },
+	{ .fc_id = 247, .cpu_id = 62, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HBM_0_MC0_ECC_DERR" },
+	{ .fc_id = 248, .cpu_id = 62, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HBM_1_MC0_ECC_DERR" },
+	{ .fc_id = 249, .cpu_id = 62, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HBM_2_MC0_ECC_DERR" },
+	{ .fc_id = 250, .cpu_id = 62, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HBM_3_MC0_ECC_DERR" },
+	{ .fc_id = 251, .cpu_id = 62, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HBM_4_MC0_ECC_DERR" },
+	{ .fc_id = 252, .cpu_id = 62, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HBM_5_MC0_ECC_DERR" },
+	{ .fc_id = 253, .cpu_id = 62, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HBM_0_MC1_ECC_DERR" },
+	{ .fc_id = 254, .cpu_id = 62, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HBM_1_MC1_ECC_DERR" },
+	{ .fc_id = 255, .cpu_id = 62, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HBM_2_MC1_ECC_DERR" },
+	{ .fc_id = 256, .cpu_id = 62, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HBM_3_MC1_ECC_DERR" },
+	{ .fc_id = 257, .cpu_id = 62, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HBM_4_MC1_ECC_DERR" },
+	{ .fc_id = 258, .cpu_id = 62, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HBM_5_MC1_ECC_DERR" },
+	{ .fc_id = 259, .cpu_id = 63, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HMMU_0_ECC_SERR" },
+	{ .fc_id = 260, .cpu_id = 63, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HMMU_1_ECC_SERR" },
+	{ .fc_id = 261, .cpu_id = 63, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HMMU_2_ECC_SERR" },
+	{ .fc_id = 262, .cpu_id = 63, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HMMU_3_ECC_SERR" },
+	{ .fc_id = 263, .cpu_id = 63, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HMMU_8_ECC_SERR" },
+	{ .fc_id = 264, .cpu_id = 63, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HMMU_9_ECC_SERR" },
+	{ .fc_id = 265, .cpu_id = 63, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HMMU_10_ECC_SERR" },
+	{ .fc_id = 266, .cpu_id = 63, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HMMU_11_ECC_SERR" },
+	{ .fc_id = 267, .cpu_id = 63, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HMMU_7_ECC_SERR" },
+	{ .fc_id = 268, .cpu_id = 63, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HMMU_6_ECC_SERR" },
+	{ .fc_id = 269, .cpu_id = 63, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HMMU_5_ECC_SERR" },
+	{ .fc_id = 270, .cpu_id = 63, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HMMU_4_ECC_SERR" },
+	{ .fc_id = 271, .cpu_id = 63, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HMMU_15_ECC_SERR" },
+	{ .fc_id = 272, .cpu_id = 63, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HMMU_14_ECC_SERR" },
+	{ .fc_id = 273, .cpu_id = 63, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HMMU_13_ECC_SERR" },
+	{ .fc_id = 274, .cpu_id = 63, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HMMU_12_ECC_SERR" },
+	{ .fc_id = 275, .cpu_id = 64, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU_0_ECC_DERR" },
+	{ .fc_id = 276, .cpu_id = 64, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU_1_ECC_DERR" },
+	{ .fc_id = 277, .cpu_id = 64, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU_2_ECC_DERR" },
+	{ .fc_id = 278, .cpu_id = 64, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU_3_ECC_DERR" },
+	{ .fc_id = 279, .cpu_id = 64, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU_8_ECC_DERR" },
+	{ .fc_id = 280, .cpu_id = 64, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU_9_ECC_DERR" },
+	{ .fc_id = 281, .cpu_id = 64, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU_10_ECC_DERR" },
+	{ .fc_id = 282, .cpu_id = 64, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU_11_ECC_DERR" },
+	{ .fc_id = 283, .cpu_id = 64, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU_7_ECC_DERR" },
+	{ .fc_id = 284, .cpu_id = 64, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU_6_ECC_DERR" },
+	{ .fc_id = 285, .cpu_id = 64, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU_5_ECC_DERR" },
+	{ .fc_id = 286, .cpu_id = 64, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU_4_ECC_DERR" },
+	{ .fc_id = 287, .cpu_id = 64, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU_15_ECC_DERR" },
+	{ .fc_id = 288, .cpu_id = 64, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU_14_ECC_DERR" },
+	{ .fc_id = 289, .cpu_id = 64, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU_13_ECC_DERR" },
+	{ .fc_id = 290, .cpu_id = 64, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU_12_ECC_DERR" },
+	{ .fc_id = 291, .cpu_id = 65, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "PMMU_ECC_SERR" },
+	{ .fc_id = 292, .cpu_id = 66, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "PMMU_ECC_DERR" },
+	{ .fc_id = 293, .cpu_id = 67, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 294, .cpu_id = 68, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 295, .cpu_id = 69, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "DEC0_VCD_ECC_SERR" },
+	{ .fc_id = 296, .cpu_id = 69, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "DEC1_VCD_ECC_SERR" },
+	{ .fc_id = 297, .cpu_id = 69, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "DEC2_VCD_ECC_SERR" },
+	{ .fc_id = 298, .cpu_id = 69, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "DEC3_VCD_ECC_SERR" },
+	{ .fc_id = 299, .cpu_id = 69, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "DEC4_VCD_ECC_SERR" },
+	{ .fc_id = 300, .cpu_id = 69, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "DEC5_VCD_ECC_SERR" },
+	{ .fc_id = 301, .cpu_id = 69, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "DEC6_VCD_ECC_SERR" },
+	{ .fc_id = 302, .cpu_id = 69, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "DEC7_VCD_ECC_SERR" },
+	{ .fc_id = 303, .cpu_id = 69, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "DEC8_VCD_ECC_SERR" },
+	{ .fc_id = 304, .cpu_id = 69, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "DEC9_VCD_ECC_SERR" },
+	{ .fc_id = 305, .cpu_id = 69, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "DEC0_L2C_ECC_SERR" },
+	{ .fc_id = 306, .cpu_id = 69, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "DEC1_L2C_ECC_SERR" },
+	{ .fc_id = 307, .cpu_id = 69, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "DEC2_L2C_ECC_SERR" },
+	{ .fc_id = 308, .cpu_id = 69, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "DEC3_L2C_ECC_SERR" },
+	{ .fc_id = 309, .cpu_id = 69, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "DEC4_L2C_ECC_SERR" },
+	{ .fc_id = 310, .cpu_id = 69, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "DEC5_L2C_ECC_SERR" },
+	{ .fc_id = 311, .cpu_id = 69, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "DEC6_L2C_ECC_SERR" },
+	{ .fc_id = 312, .cpu_id = 69, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "DEC7_L2C_ECC_SERR" },
+	{ .fc_id = 313, .cpu_id = 69, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "DEC8_L2C_ECC_SERR" },
+	{ .fc_id = 314, .cpu_id = 69, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "DEC9_L2C_ECC_SERR" },
+	{ .fc_id = 315, .cpu_id = 70, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DEC0_VCD_ECC_DERR" },
+	{ .fc_id = 316, .cpu_id = 70, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DEC1_VCD_ECC_DERR" },
+	{ .fc_id = 317, .cpu_id = 70, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DEC2_VCD_ECC_DERR" },
+	{ .fc_id = 318, .cpu_id = 70, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DEC3_VCD_ECC_DERR" },
+	{ .fc_id = 319, .cpu_id = 70, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DEC4_VCD_ECC_DERR" },
+	{ .fc_id = 320, .cpu_id = 70, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DEC5_VCD_ECC_DERR" },
+	{ .fc_id = 321, .cpu_id = 70, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DEC6_VCD_ECC_DERR" },
+	{ .fc_id = 322, .cpu_id = 70, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DEC7_VCD_ECC_DERR" },
+	{ .fc_id = 323, .cpu_id = 70, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DEC8_VCD_ECC_DERR" },
+	{ .fc_id = 324, .cpu_id = 70, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DEC9_VCD_ECC_DERR" },
+	{ .fc_id = 325, .cpu_id = 70, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DEC0_L2C_ECC_DERR" },
+	{ .fc_id = 326, .cpu_id = 70, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DEC1_L2C_ECC_DERR" },
+	{ .fc_id = 327, .cpu_id = 70, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DEC2_L2C_ECC_DERR" },
+	{ .fc_id = 328, .cpu_id = 70, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DEC3_L2C_ECC_DERR" },
+	{ .fc_id = 329, .cpu_id = 70, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DEC4_L2C_ECC_DERR" },
+	{ .fc_id = 330, .cpu_id = 70, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DEC5_L2C_ECC_DERR" },
+	{ .fc_id = 331, .cpu_id = 70, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DEC6_L2C_ECC_DERR" },
+	{ .fc_id = 332, .cpu_id = 70, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DEC7_L2C_ECC_DERR" },
+	{ .fc_id = 333, .cpu_id = 70, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DEC8_L2C_ECC_DERR" },
+	{ .fc_id = 334, .cpu_id = 70, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DEC9_L2C_ECC_DERR" },
+	{ .fc_id = 335, .cpu_id = 71, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 336, .cpu_id = 72, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 337, .cpu_id = 73, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HIF0_ECC_SERR" },
+	{ .fc_id = 338, .cpu_id = 73, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HIF1_ECC_SERR" },
+	{ .fc_id = 339, .cpu_id = 73, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HIF2_ECC_SERR" },
+	{ .fc_id = 340, .cpu_id = 73, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HIF3_ECC_SERR" },
+	{ .fc_id = 341, .cpu_id = 73, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HIF8_ECC_SERR" },
+	{ .fc_id = 342, .cpu_id = 73, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HIF9_ECC_SERR" },
+	{ .fc_id = 343, .cpu_id = 73, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HIF10_ECC_SERR" },
+	{ .fc_id = 344, .cpu_id = 73, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HIF11_ECC_SERR" },
+	{ .fc_id = 345, .cpu_id = 73, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HIF7_ECC_SERR" },
+	{ .fc_id = 346, .cpu_id = 73, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HIF6_ECC_SERR" },
+	{ .fc_id = 347, .cpu_id = 73, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HIF5_ECC_SERR" },
+	{ .fc_id = 348, .cpu_id = 73, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HIF4_ECC_SERR" },
+	{ .fc_id = 349, .cpu_id = 73, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HIF15_ECC_SERR" },
+	{ .fc_id = 350, .cpu_id = 73, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HIF14_ECC_SERR" },
+	{ .fc_id = 351, .cpu_id = 73, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HIF13_ECC_SERR" },
+	{ .fc_id = 352, .cpu_id = 73, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HIF12_ECC_SERR" },
+	{ .fc_id = 353, .cpu_id = 74, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HIF0_ECC_DERR" },
+	{ .fc_id = 354, .cpu_id = 74, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HIF1_ECC_DERR" },
+	{ .fc_id = 355, .cpu_id = 74, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HIF2_ECC_DERR" },
+	{ .fc_id = 356, .cpu_id = 74, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HIF3_ECC_DERR" },
+	{ .fc_id = 357, .cpu_id = 74, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HIF8_ECC_DERR" },
+	{ .fc_id = 358, .cpu_id = 74, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HIF9_ECC_DERR" },
+	{ .fc_id = 359, .cpu_id = 74, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HIF10_ECC_DERR" },
+	{ .fc_id = 360, .cpu_id = 74, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HIF11_ECC_DERR" },
+	{ .fc_id = 361, .cpu_id = 74, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HIF7_ECC_DERR" },
+	{ .fc_id = 362, .cpu_id = 74, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HIF6_ECC_DERR" },
+	{ .fc_id = 363, .cpu_id = 74, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HIF5_ECC_DERR" },
+	{ .fc_id = 364, .cpu_id = 74, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HIF4_ECC_DERR" },
+	{ .fc_id = 365, .cpu_id = 74, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HIF15_ECC_DERR" },
+	{ .fc_id = 366, .cpu_id = 74, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HIF14_ECC_DERR" },
+	{ .fc_id = 367, .cpu_id = 74, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HIF13_ECC_DERR" },
+	{ .fc_id = 368, .cpu_id = 74, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HIF12_ECC_DERR" },
+	{ .fc_id = 369, .cpu_id = 75, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "NIC0_ECC_SERR" },
+	{ .fc_id = 370, .cpu_id = 75, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "NIC1_ECC_SERR" },
+	{ .fc_id = 371, .cpu_id = 75, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "NIC2_ECC_SERR" },
+	{ .fc_id = 372, .cpu_id = 75, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "NIC3_ECC_SERR" },
+	{ .fc_id = 373, .cpu_id = 75, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "NIC4_ECC_SERR" },
+	{ .fc_id = 374, .cpu_id = 75, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "NIC5_ECC_SERR" },
+	{ .fc_id = 375, .cpu_id = 75, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "NIC6_ECC_SERR" },
+	{ .fc_id = 376, .cpu_id = 75, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "NIC7_ECC_SERR" },
+	{ .fc_id = 377, .cpu_id = 75, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "NIC8_ECC_SERR" },
+	{ .fc_id = 378, .cpu_id = 75, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "NIC9_ECC_SERR" },
+	{ .fc_id = 379, .cpu_id = 75, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "NIC10_ECC_SERR" },
+	{ .fc_id = 380, .cpu_id = 75, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "NIC11_ECC_SERR" },
+	{ .fc_id = 381, .cpu_id = 76, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC0_ECC_DERR" },
+	{ .fc_id = 382, .cpu_id = 76, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC1_ECC_DERR" },
+	{ .fc_id = 383, .cpu_id = 76, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC2_ECC_DERR" },
+	{ .fc_id = 384, .cpu_id = 76, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC3_ECC_DERR" },
+	{ .fc_id = 385, .cpu_id = 76, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC4_ECC_DERR" },
+	{ .fc_id = 386, .cpu_id = 76, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC5_ECC_DERR" },
+	{ .fc_id = 387, .cpu_id = 76, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC6_ECC_DERR" },
+	{ .fc_id = 388, .cpu_id = 76, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC7_ECC_DERR" },
+	{ .fc_id = 389, .cpu_id = 76, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC8_ECC_DERR" },
+	{ .fc_id = 390, .cpu_id = 76, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC9_ECC_DERR" },
+	{ .fc_id = 391, .cpu_id = 76, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC10_ECC_DERR" },
+	{ .fc_id = 392, .cpu_id = 76, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC11_ECC_DERR" },
+	{ .fc_id = 393, .cpu_id = 77, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "SM0_ECC_DERR" },
+	{ .fc_id = 394, .cpu_id = 77, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "SM1_ECC_DERR" },
+	{ .fc_id = 395, .cpu_id = 77, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "SM2_ECC_DERR" },
+	{ .fc_id = 396, .cpu_id = 77, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "SM3_ECC_DERR" },
+	{ .fc_id = 397, .cpu_id = 78, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "SM0_ECC_SERR" },
+	{ .fc_id = 398, .cpu_id = 78, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "SM1_ECC_SERR" },
+	{ .fc_id = 399, .cpu_id = 78, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "SM2_ECC_SERR" },
+	{ .fc_id = 400, .cpu_id = 78, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "SM3_ECC_SERR" },
+	{ .fc_id = 401, .cpu_id = 79, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "XBAR0_ECC_SERR" },
+	{ .fc_id = 402, .cpu_id = 79, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "XBAR1_ECC_SERR" },
+	{ .fc_id = 403, .cpu_id = 79, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "XBAR2_ECC_SERR" },
+	{ .fc_id = 404, .cpu_id = 79, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "XBAR3_ECC_SERR" },
+	{ .fc_id = 405, .cpu_id = 80, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "XBAR0_ECC_DERR" },
+	{ .fc_id = 406, .cpu_id = 80, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "XBAR1_ECC_DERR" },
+	{ .fc_id = 407, .cpu_id = 80, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "XBAR2_ECC_DERR" },
+	{ .fc_id = 408, .cpu_id = 80, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "XBAR3_ECC_DERR" },
+	{ .fc_id = 409, .cpu_id = 81, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "ARC0_ECC_SERR" },
+	{ .fc_id = 410, .cpu_id = 82, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "ARC0_ECC_DERR" },
+	{ .fc_id = 411, .cpu_id = 83, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 412, .cpu_id = 84, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "PCIE_ADDR_DEC_ERR" },
+	{ .fc_id = 413, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE0_TPC0_AXI_ERR_RSP" },
+	{ .fc_id = 414, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE0_TPC1_AXI_ERR_RSP" },
+	{ .fc_id = 415, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE0_TPC2_AXI_ERR_RSP" },
+	{ .fc_id = 416, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE0_TPC3_AXI_ERR_RSP" },
+	{ .fc_id = 417, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE0_TPC4_AXI_ERR_RSP" },
+	{ .fc_id = 418, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE0_TPC5_AXI_ERR_RSP" },
+	{ .fc_id = 419, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE1_TPC0_AXI_ERR_RSP" },
+	{ .fc_id = 420, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE1_TPC1_AXI_ERR_RSP" },
+	{ .fc_id = 421, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE1_TPC2_AXI_ERR_RSP" },
+	{ .fc_id = 422, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE1_TPC3_AXI_ERR_RSP" },
+	{ .fc_id = 423, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE1_TPC4_AXI_ERR_RSP" },
+	{ .fc_id = 424, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE1_TPC5_AXI_ERR_RSP" },
+	{ .fc_id = 425, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE2_TPC0_AXI_ERR_RSP" },
+	{ .fc_id = 426, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE2_TPC1_AXI_ERR_RSP" },
+	{ .fc_id = 427, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE2_TPC2_AXI_ERR_RSP" },
+	{ .fc_id = 428, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE2_TPC3_AXI_ERR_RSP" },
+	{ .fc_id = 429, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE2_TPC4_AXI_ERR_RSP" },
+	{ .fc_id = 430, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE2_TPC5_AXI_ERR_RSP" },
+	{ .fc_id = 431, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE3_TPC0_AXI_ERR_RSP" },
+	{ .fc_id = 432, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE3_TPC1_AXI_ERR_RSP" },
+	{ .fc_id = 433, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE3_TPC2_AXI_ERR_RSP" },
+	{ .fc_id = 434, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE3_TPC3_AXI_ERR_RSP" },
+	{ .fc_id = 435, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE3_TPC4_AXI_ERR_RSP" },
+	{ .fc_id = 436, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE3_TPC5_AXI_ERR_RSP" },
+	{ .fc_id = 437, .cpu_id = 85, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE4_TPC0_AXI_ERR_RSP" },
+	{ .fc_id = 438, .cpu_id = 86, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "AXI_ECC" },
+	{ .fc_id = 439, .cpu_id = 87, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "L2_RAM_ECC" },
+	{ .fc_id = 440, .cpu_id = 88, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "MME0_SBTE0_AXI_ERR_RSP" },
+	{ .fc_id = 441, .cpu_id = 88, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "MME0_SBTE1_AXI_ERR_RSP" },
+	{ .fc_id = 442, .cpu_id = 88, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "MME0_SBTE2_AXI_ERR_RSP" },
+	{ .fc_id = 443, .cpu_id = 88, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "MME0_SBTE3_AXI_ERR_RSP" },
+	{ .fc_id = 444, .cpu_id = 88, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "MME0_SBTE4_AXI_ERR_RSP" },
+	{ .fc_id = 445, .cpu_id = 88, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "MME0_CTRL_AXI_ERROR_RESPONSE" },
+	{ .fc_id = 446, .cpu_id = 88, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "MME0_QMAN_SW_ERROR" },
+	{ .fc_id = 447, .cpu_id = 89, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "MME1_SBTE0_AXI_ERR_RSP" },
+	{ .fc_id = 448, .cpu_id = 89, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "MME1_SBTE1_AXI_ERR_RSP" },
+	{ .fc_id = 449, .cpu_id = 89, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "MME1_SBTE2_AXI_ERR_RSP" },
+	{ .fc_id = 450, .cpu_id = 89, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "MME1_SBTE3_AXI_ERR_RSP" },
+	{ .fc_id = 451, .cpu_id = 89, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "MME1_SBTE4_AXI_ERR_RSP" },
+	{ .fc_id = 452, .cpu_id = 89, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "MME1_CTRL_AXI_ERROR_RESPONSE" },
+	{ .fc_id = 453, .cpu_id = 89, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "MME1_QMAN_SW_ERROR" },
+	{ .fc_id = 454, .cpu_id = 90, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "MME2_SBTE0_AXI_ERR_RSP" },
+	{ .fc_id = 455, .cpu_id = 90, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "MME2_SBTE1_AXI_ERR_RSP" },
+	{ .fc_id = 456, .cpu_id = 90, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "MME2_SBTE2_AXI_ERR_RSP" },
+	{ .fc_id = 457, .cpu_id = 90, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "MME2_SBTE3_AXI_ERR_RSP" },
+	{ .fc_id = 458, .cpu_id = 90, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "MME2_SBTE4_AXI_ERR_RSP" },
+	{ .fc_id = 459, .cpu_id = 90, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "MME2_CTRL_AXI_ERROR_RESPONSE" },
+	{ .fc_id = 460, .cpu_id = 90, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "MME2_QMAN_SW_ERROR" },
+	{ .fc_id = 461, .cpu_id = 91, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "MME3_SBTE0_AXI_ERR_RSP" },
+	{ .fc_id = 462, .cpu_id = 91, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "MME3_SBTE1_AXI_ERR_RSP" },
+	{ .fc_id = 463, .cpu_id = 91, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "MME3_SBTE2_AXI_ERR_RSP" },
+	{ .fc_id = 464, .cpu_id = 91, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "MME3_SBTE3_AXI_ERR_RSP" },
+	{ .fc_id = 465, .cpu_id = 91, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "MME3_SBTE4_AXI_ERR_RSP" },
+	{ .fc_id = 466, .cpu_id = 91, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "MME3_CTRL_AXI_ERROR_RESPONSE" },
+	{ .fc_id = 467, .cpu_id = 91, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "MME3_QMAN_SW_ERROR" },
+	{ .fc_id = 468, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "PSOC_MME_PLL_LOCK_ERR" },
+	{ .fc_id = 469, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "PSOC_CPU_PLL_LOCK_ERR" },
+	{ .fc_id = 470, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DCORE3_TPC_PLL_LOCK_ERR" },
+	{ .fc_id = 471, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DCORE3_NIC_PLL_LOCK_ERR" },
+	{ .fc_id = 472, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DCORE3_XBAR_MMU_PLL_LOCK_ERR" },
+	{ .fc_id = 473, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DCORE3_XBAR_DMA_PLL_LOCK_ERR" },
+	{ .fc_id = 474, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DCORE3_XBAR_IF_PLL_LOCK_ERR" },
+	{ .fc_id = 475, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DCORE3_XBAR_BANK_PLL_LOCK_ERR" },
+	{ .fc_id = 476, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DCORE1_XBAR_MMU_PLL_LOCK_ERR" },
+	{ .fc_id = 477, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DCORE1_XBAR_DMA_PLL_LOCK_ERR" },
+	{ .fc_id = 478, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DCORE1_XBAR_IF_PLL_LOCK_ERR" },
+	{ .fc_id = 479, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DCORE1_XBAR_MESH_PLL_LOCK_ERR" },
+	{ .fc_id = 480, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DCORE1_TPC_PLL_LOCK_ERR" },
+	{ .fc_id = 481, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DCORE1_NIC_PLL_LOCK_ERR" },
+	{ .fc_id = 482, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "PMMU_MME_PLL_LOCK_ERR" },
+	{ .fc_id = 483, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DCORE0_TPC_PLL_LOCK_ERR" },
+	{ .fc_id = 484, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DCORE0_PCI_PLL_LOCK_ERR" },
+	{ .fc_id = 485, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DCORE0_XBAR_MMU_PLL_LOCK_ERR" },
+	{ .fc_id = 486, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DCORE0_XBAR_DMA_PLL_LOCK_ERR" },
+	{ .fc_id = 487, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DCORE0_XBAR_IF_PLL_LOCK_ERR" },
+	{ .fc_id = 488, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DCORE0_XBAR_MESH_PLL_LOCK_ERR" },
+	{ .fc_id = 489, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DCORE2_XBAR_MMU_PLL_LOCK_ERR" },
+	{ .fc_id = 490, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DCORE2_XBAR_DMA_PLL_LOCK_ERR" },
+	{ .fc_id = 491, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DCORE2_XBAR_IF_PLL_LOCK_ERR" },
+	{ .fc_id = 492, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DCORE2_XBAR_BANK_PLL_LOCK_ERR" },
+	{ .fc_id = 493, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DCORE2_TPC_PLL_LOCK_ERR" },
+	{ .fc_id = 494, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "PSOC_VID_PLL_LOCK_ERR" },
+	{ .fc_id = 495, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "PMMU_VID_PLL_LOCK_ERR" },
+	{ .fc_id = 496, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DCORE3_HBM_PLL_LOCK_ERR" },
+	{ .fc_id = 497, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DCORE1_XBAR_HBM_PLL_LOCK_ERR" },
+	{ .fc_id = 498, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DCORE1_HBM_PLL_LOCK_ERR" },
+	{ .fc_id = 499, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DCORE0_HBM_PLL_LOCK_ERR" },
+	{ .fc_id = 500, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DCORE2_XBAR_HBM_PLL_LOCK_ERR" },
+	{ .fc_id = 501, .cpu_id = 92, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DCORE2_HBM_PLL_LOCK_ERR" },
+	{ .fc_id = 502, .cpu_id = 93, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "CPU_AXI_ERR_RSP" },
+	{ .fc_id = 503, .cpu_id = 94, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU_0_AXI_ERR_RSP" },
+	{ .fc_id = 504, .cpu_id = 94, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU_1_AXI_ERR_RSP" },
+	{ .fc_id = 505, .cpu_id = 94, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU_2_AXI_ERR_RSP" },
+	{ .fc_id = 506, .cpu_id = 94, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU_3_AXI_ERR_RSP" },
+	{ .fc_id = 507, .cpu_id = 94, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU_8_AXI_ERR_RSP" },
+	{ .fc_id = 508, .cpu_id = 94, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU_9_AXI_ERR_RSP" },
+	{ .fc_id = 509, .cpu_id = 94, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU_10_AXI_ERR_RSP" },
+	{ .fc_id = 510, .cpu_id = 94, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU_11_AXI_ERR_RSP" },
+	{ .fc_id = 511, .cpu_id = 94, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU_7_AXI_ERR_RSP" },
+	{ .fc_id = 512, .cpu_id = 94, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU_6_AXI_ERR_RSP" },
+	{ .fc_id = 513, .cpu_id = 94, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU_5_AXI_ERR_RSP" },
+	{ .fc_id = 514, .cpu_id = 94, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU_4_AXI_ERR_RSP" },
+	{ .fc_id = 515, .cpu_id = 94, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU_15_AXI_ERR_RSP" },
+	{ .fc_id = 516, .cpu_id = 94, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU_14_AXI_ERR_RSP" },
+	{ .fc_id = 517, .cpu_id = 94, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU_13_AXI_ERR_RSP" },
+	{ .fc_id = 518, .cpu_id = 94, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU_12_AXI_ERR_RSP" },
+	{ .fc_id = 519, .cpu_id = 95, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "PMMU_FATAL" },
+	{ .fc_id = 520, .cpu_id = 96, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "PMMU_AXI_ERR_RSP" },
+	{ .fc_id = 521, .cpu_id = 97, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "VM0_ALARM_A" },
+	{ .fc_id = 522, .cpu_id = 98, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "VM0_ALARM_B" },
+	{ .fc_id = 523, .cpu_id = 99, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "VM1_ALARM_A" },
+	{ .fc_id = 524, .cpu_id = 100, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "VM1_ALARM_B" },
+	{ .fc_id = 525, .cpu_id = 101, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "VM2_ALARM_A" },
+	{ .fc_id = 526, .cpu_id = 102, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "VM2_ALARM_B" },
+	{ .fc_id = 527, .cpu_id = 103, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "VM3_ALARM_A" },
+	{ .fc_id = 528, .cpu_id = 104, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "VM3_ALARM_B" },
+	{ .fc_id = 529, .cpu_id = 105, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "PSOC_AXI_ERR_RSP" },
+	{ .fc_id = 530, .cpu_id = 106, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "PSOC_PRSTN_FALL" },
+	{ .fc_id = 531, .cpu_id = 107, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 532, .cpu_id = 107, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 533, .cpu_id = 107, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 534, .cpu_id = 107, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 535, .cpu_id = 107, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 536, .cpu_id = 107, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 537, .cpu_id = 107, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 538, .cpu_id = 107, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 539, .cpu_id = 108, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "KDMA_CH0_AXI_ERR_RSP" },
+	{ .fc_id = 540, .cpu_id = 109, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "PDMA_CH0_AXI_ERR_RSP" },
+	{ .fc_id = 541, .cpu_id = 109, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "PDMA_CH1_AXI_ERR_RSP" },
+	{ .fc_id = 542, .cpu_id = 110, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HBM_CATTRIP_0" },
+	{ .fc_id = 543, .cpu_id = 111, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HBM_CATTRIP_1" },
+	{ .fc_id = 544, .cpu_id = 112, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HBM_CATTRIP_2" },
+	{ .fc_id = 545, .cpu_id = 113, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HBM_CATTRIP_3" },
+	{ .fc_id = 546, .cpu_id = 114, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HBM_CATTRIP_4" },
+	{ .fc_id = 547, .cpu_id = 115, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HBM_CATTRIP_5" },
+	{ .fc_id = 548, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HBM0_MC0_SEI_SEVERE" },
+	{ .fc_id = 549, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HBM0_MC0_SEI_NON_SEVERE" },
+	{ .fc_id = 550, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HBM0_MC1_SEI_SEVERE" },
+	{ .fc_id = 551, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HBM0_MC1_SEI_NON_SEVERE" },
+	{ .fc_id = 552, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HBM1_MC0_SEI_SEVERE" },
+	{ .fc_id = 553, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HBM1_MC0_SEI_NON_SEVERE" },
+	{ .fc_id = 554, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HBM1_MC1_SEI_SEVERE" },
+	{ .fc_id = 555, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HBM1_MC1_SEI_NON_SEVERE" },
+	{ .fc_id = 556, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HBM2_MC0_SEI_SEVERE" },
+	{ .fc_id = 557, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HBM2_MC0_SEI_NON_SEVERE" },
+	{ .fc_id = 558, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HBM2_MC1_SEI_SEVERE" },
+	{ .fc_id = 559, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HBM2_MC1_SEI_NON_SEVERE" },
+	{ .fc_id = 560, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HBM3_MC0_SEI_SEVERE" },
+	{ .fc_id = 561, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HBM3_MC0_SEI_NON_SEVERE" },
+	{ .fc_id = 562, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HBM3_MC1_SEI_SEVERE" },
+	{ .fc_id = 563, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HBM3_MC1_SEI_NON_SEVERE" },
+	{ .fc_id = 564, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HBM4_MC0_SEI_SEVERE" },
+	{ .fc_id = 565, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HBM4_MC0_SEI_NON_SEVERE" },
+	{ .fc_id = 566, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HBM4_MC1_SEI_SEVERE" },
+	{ .fc_id = 567, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HBM4_MC1_SEI_NON_SEVERE" },
+	{ .fc_id = 568, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HBM5_MC0_SEI_SEVERE" },
+	{ .fc_id = 569, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HBM5_MC0_SEI_NON_SEVERE" },
+	{ .fc_id = 570, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HBM5_MC1_SEI_SEVERE" },
+	{ .fc_id = 571, .cpu_id = 116, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HBM5_MC1_SEI_NON_SEVERE" },
+	{ .fc_id = 572, .cpu_id = 117, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DEC0_AXI_ERR_RSPONSE" },
+	{ .fc_id = 573, .cpu_id = 117, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DEC1_AXI_ERR_RSPONSE" },
+	{ .fc_id = 574, .cpu_id = 117, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DEC2_AXI_ERR_RSPONSE" },
+	{ .fc_id = 575, .cpu_id = 117, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DEC3_AXI_ERR_RSPONSE" },
+	{ .fc_id = 576, .cpu_id = 117, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DEC4_AXI_ERR_RSPONSE" },
+	{ .fc_id = 577, .cpu_id = 117, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DEC5_AXI_ERR_RSPONSE" },
+	{ .fc_id = 578, .cpu_id = 117, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DEC6_AXI_ERR_RSPONSE" },
+	{ .fc_id = 579, .cpu_id = 117, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DEC7_AXI_ERR_RSPONSE" },
+	{ .fc_id = 580, .cpu_id = 117, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DEC8_AXI_ERR_RSPONSE" },
+	{ .fc_id = 581, .cpu_id = 117, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DEC9_AXI_ERR_RSPONSE" },
+	{ .fc_id = 582, .cpu_id = 118, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 583, .cpu_id = 119, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 584, .cpu_id = 120, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HIF0_FATAL" },
+	{ .fc_id = 585, .cpu_id = 120, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HIF1_FATAL" },
+	{ .fc_id = 586, .cpu_id = 120, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HIF2_FATAL" },
+	{ .fc_id = 587, .cpu_id = 120, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HIF3_FATAL" },
+	{ .fc_id = 588, .cpu_id = 120, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HIF8_FATAL" },
+	{ .fc_id = 589, .cpu_id = 120, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HIF9_FATAL" },
+	{ .fc_id = 590, .cpu_id = 120, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HIF10_FATAL" },
+	{ .fc_id = 591, .cpu_id = 120, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HIF11_FATAL" },
+	{ .fc_id = 592, .cpu_id = 120, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HIF7_FATAL" },
+	{ .fc_id = 593, .cpu_id = 120, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HIF6_FATAL" },
+	{ .fc_id = 594, .cpu_id = 120, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HIF5_FATAL" },
+	{ .fc_id = 595, .cpu_id = 120, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HIF4_FATAL" },
+	{ .fc_id = 596, .cpu_id = 120, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HIF15_FATAL" },
+	{ .fc_id = 597, .cpu_id = 120, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HIF14_FATAL" },
+	{ .fc_id = 598, .cpu_id = 120, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HIF13_FATAL" },
+	{ .fc_id = 599, .cpu_id = 120, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HIF12_FATAL" },
+	{ .fc_id = 600, .cpu_id = 121, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC0_AXI_ERROR_RESPONSE" },
+	{ .fc_id = 601, .cpu_id = 121, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC1_AXI_ERROR_RESPONSE" },
+	{ .fc_id = 602, .cpu_id = 121, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC2_AXI_ERROR_RESPONSE" },
+	{ .fc_id = 603, .cpu_id = 121, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC3_AXI_ERROR_RESPONSE" },
+	{ .fc_id = 604, .cpu_id = 121, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC4_AXI_ERROR_RESPONSE" },
+	{ .fc_id = 605, .cpu_id = 121, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC5_AXI_ERROR_RESPONSE" },
+	{ .fc_id = 606, .cpu_id = 121, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC6_AXI_ERROR_RESPONSE" },
+	{ .fc_id = 607, .cpu_id = 121, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC7_AXI_ERROR_RESPONSE" },
+	{ .fc_id = 608, .cpu_id = 121, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC8_AXI_ERROR_RESPONSE" },
+	{ .fc_id = 609, .cpu_id = 121, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC9_AXI_ERROR_RESPONSE" },
+	{ .fc_id = 610, .cpu_id = 121, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC10_AXI_ERROR_RESPONSE" },
+	{ .fc_id = 611, .cpu_id = 121, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC11_AXI_ERROR_RESPONSE" },
+	{ .fc_id = 612, .cpu_id = 122, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "SM0_AXI_ERROR_RESPONSE" },
+	{ .fc_id = 613, .cpu_id = 122, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "SM1_AXI_ERROR_RESPONSE" },
+	{ .fc_id = 614, .cpu_id = 122, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "SM2_AXI_ERROR_RESPONSE" },
+	{ .fc_id = 615, .cpu_id = 122, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "SM3_AXI_ERROR_RESPONSE" },
+	{ .fc_id = 616, .cpu_id = 123, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "ARC_AXI_ERROR_RESPONSE" },
+	{ .fc_id = 617, .cpu_id = 124, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 618, .cpu_id = 125, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 619, .cpu_id = 125, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "PCIE_FLR_REQUESTED" },
+	{ .fc_id = 620, .cpu_id = 125, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 621, .cpu_id = 125, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 622, .cpu_id = 125, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "PCIE_APB_TIMEOUT" },
+	{ .fc_id = 623, .cpu_id = 125, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 624, .cpu_id = 125, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 625, .cpu_id = 125, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 626, .cpu_id = 125, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 627, .cpu_id = 125, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "PCIE_FATAL_ERR" },
+	{ .fc_id = 628, .cpu_id = 125, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 629, .cpu_id = 126, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 630, .cpu_id = 127, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 631, .cpu_id = 128, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "PCIE_P2P_MSIX" },
+	{ .fc_id = 632, .cpu_id = 129, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "PCIE_DRAIN_COMPLETE" },
+	{ .fc_id = 633, .cpu_id = 130, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC0_BMON_SPMU" },
+	{ .fc_id = 634, .cpu_id = 131, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE0_TPC0_KERNEL_ERR" },
+	{ .fc_id = 635, .cpu_id = 132, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC1_BMON_SPMU" },
+	{ .fc_id = 636, .cpu_id = 133, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE0_TPC1_KERNEL_ERR" },
+	{ .fc_id = 637, .cpu_id = 134, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC2_BMON_SPMU" },
+	{ .fc_id = 638, .cpu_id = 135, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE0_TPC2_KERNEL_ERR" },
+	{ .fc_id = 639, .cpu_id = 136, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC3_BMON_SPMU" },
+	{ .fc_id = 640, .cpu_id = 137, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE0_TPC3_KERNEL_ERR" },
+	{ .fc_id = 641, .cpu_id = 138, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC4_BMON_SPMU" },
+	{ .fc_id = 642, .cpu_id = 139, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE0_TPC4_KERNEL_ERR" },
+	{ .fc_id = 643, .cpu_id = 140, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC5_BMON_SPMU" },
+	{ .fc_id = 644, .cpu_id = 141, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE0_TPC5_KERNEL_ERR" },
+	{ .fc_id = 645, .cpu_id = 150, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC6_BMON_SPMU" },
+	{ .fc_id = 646, .cpu_id = 151, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE1_TPC0_KERNEL_ERR" },
+	{ .fc_id = 647, .cpu_id = 152, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC7_BMON_SPMU" },
+	{ .fc_id = 648, .cpu_id = 153, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE1_TPC1_KERNEL_ERR" },
+	{ .fc_id = 649, .cpu_id = 146, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC8_BMON_SPMU" },
+	{ .fc_id = 650, .cpu_id = 147, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE1_TPC2_KERNEL_ERR" },
+	{ .fc_id = 651, .cpu_id = 148, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC9_BMON_SPMU" },
+	{ .fc_id = 652, .cpu_id = 149, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE1_TPC3_KERNEL_ERR" },
+	{ .fc_id = 653, .cpu_id = 142, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC10_BMON_SPMU" },
+	{ .fc_id = 654, .cpu_id = 143, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE1_TPC4_KERNEL_ERR" },
+	{ .fc_id = 655, .cpu_id = 144, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC11_BMON_SPMU" },
+	{ .fc_id = 656, .cpu_id = 145, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE1_TPC5_KERNEL_ERR" },
+	{ .fc_id = 657, .cpu_id = 162, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC12_BMON_SPMU" },
+	{ .fc_id = 658, .cpu_id = 163, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE2_TPC0_KERNEL_ERR" },
+	{ .fc_id = 659, .cpu_id = 164, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC13_BMON_SPMU" },
+	{ .fc_id = 660, .cpu_id = 165, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE2_TPC1_KERNEL_ERR" },
+	{ .fc_id = 661, .cpu_id = 158, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC14_BMON_SPMU" },
+	{ .fc_id = 662, .cpu_id = 159, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE2_TPC2_KERNEL_ERR" },
+	{ .fc_id = 663, .cpu_id = 160, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC15_BMON_SPMU" },
+	{ .fc_id = 664, .cpu_id = 161, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE2_TPC3_KERNEL_ERR" },
+	{ .fc_id = 665, .cpu_id = 154, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC16_BMON_SPMU" },
+	{ .fc_id = 666, .cpu_id = 155, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE2_TPC4_KERNEL_ERR" },
+	{ .fc_id = 667, .cpu_id = 156, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC17_BMON_SPMU" },
+	{ .fc_id = 668, .cpu_id = 157, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE2_TPC5_KERNEL_ERR" },
+	{ .fc_id = 669, .cpu_id = 166, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC18_BMON_SPMU" },
+	{ .fc_id = 670, .cpu_id = 167, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE3_TPC0_KERNEL_ERR" },
+	{ .fc_id = 671, .cpu_id = 168, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC19_BMON_SPMU" },
+	{ .fc_id = 672, .cpu_id = 169, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE3_TPC1_KERNEL_ERR" },
+	{ .fc_id = 673, .cpu_id = 170, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC20_BMON_SPMU" },
+	{ .fc_id = 674, .cpu_id = 171, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE3_TPC2_KERNEL_ERR" },
+	{ .fc_id = 675, .cpu_id = 172, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC21_BMON_SPMU" },
+	{ .fc_id = 676, .cpu_id = 173, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE3_TPC3_KERNEL_ERR" },
+	{ .fc_id = 677, .cpu_id = 174, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC22_BMON_SPMU" },
+	{ .fc_id = 678, .cpu_id = 175, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE3_TPC4_KERNEL_ERR" },
+	{ .fc_id = 679, .cpu_id = 176, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC23_BMON_SPMU" },
+	{ .fc_id = 680, .cpu_id = 177, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE3_TPC5_KERNEL_ERR" },
+	{ .fc_id = 681, .cpu_id = 178, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "TPC24_BMON_SPMU" },
+	{ .fc_id = 682, .cpu_id = 179, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE4_TPC0_KERNEL_ERR" },
+	{ .fc_id = 683, .cpu_id = 180, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 684, .cpu_id = 180, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 685, .cpu_id = 180, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 686, .cpu_id = 180, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 687, .cpu_id = 180, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 688, .cpu_id = 180, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "MME0_CTRL_BMON_SPMU" },
+	{ .fc_id = 689, .cpu_id = 180, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "MME0_SBTE_BMON_SPMU" },
+	{ .fc_id = 690, .cpu_id = 180, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "MME0_WAP_BMON_SPMU" },
+	{ .fc_id = 691, .cpu_id = 180, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "MME0_WAP_SOURCE_RESULT_INVALID" },
+	{ .fc_id = 692, .cpu_id = 181, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 693, .cpu_id = 181, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 694, .cpu_id = 181, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 695, .cpu_id = 181, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 696, .cpu_id = 181, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 697, .cpu_id = 181, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "MME1_CTRL_BMON_SPMU" },
+	{ .fc_id = 698, .cpu_id = 181, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "MME1_SBTE_BMON_SPMU" },
+	{ .fc_id = 699, .cpu_id = 181, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "MME1_WAP_BMON_SPMU" },
+	{ .fc_id = 700, .cpu_id = 181, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "MME1_WAP_SOURCE_RESULT_INVALID" },
+	{ .fc_id = 701, .cpu_id = 182, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 702, .cpu_id = 182, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 703, .cpu_id = 182, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 704, .cpu_id = 182, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 705, .cpu_id = 182, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 706, .cpu_id = 182, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "MME2_CTRL_BMON_SPMU" },
+	{ .fc_id = 707, .cpu_id = 182, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "MME2_SBTE_BMON_SPMU" },
+	{ .fc_id = 708, .cpu_id = 182, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "MME2_WAP_BMON_SPMU" },
+	{ .fc_id = 709, .cpu_id = 182, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "MME2_WAP_SOURCE_RESULT_INVALID" },
+	{ .fc_id = 710, .cpu_id = 183, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 711, .cpu_id = 183, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 712, .cpu_id = 183, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 713, .cpu_id = 183, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 714, .cpu_id = 183, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 715, .cpu_id = 183, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "MME3_CTRL_BMON_SPMU" },
+	{ .fc_id = 716, .cpu_id = 183, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "MME3_SBTE_BMON_SPMU" },
+	{ .fc_id = 717, .cpu_id = 183, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "MME3_WAP_BMON_SPMU" },
+	{ .fc_id = 718, .cpu_id = 183, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "MME3_WAP_SOURCE_RESULT_INVALID" },
+	{ .fc_id = 719, .cpu_id = 184, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 720, .cpu_id = 184, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HMMU0_PAGE_FAULT_OR_WR_PERM" },
+	{ .fc_id = 721, .cpu_id = 184, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU0_SECURITY_ERROR" },
+	{ .fc_id = 722, .cpu_id = 185, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 723, .cpu_id = 185, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HMMU1_PAGE_FAULT_WR_PERM" },
+	{ .fc_id = 724, .cpu_id = 185, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU1_SECURITY_ERROR" },
+	{ .fc_id = 725, .cpu_id = 186, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 726, .cpu_id = 186, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HMMU2_PAGE_FAULT_WR_PERM" },
+	{ .fc_id = 727, .cpu_id = 186, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU2_SECURITY_ERROR" },
+	{ .fc_id = 728, .cpu_id = 187, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 729, .cpu_id = 187, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HMMU3_PAGE_FAULT_WR_PERM" },
+	{ .fc_id = 730, .cpu_id = 187, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU3_SECURITY_ERROR" },
+	{ .fc_id = 731, .cpu_id = 188, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 732, .cpu_id = 188, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HMMU8_PAGE_FAULT_WR_PERM" },
+	{ .fc_id = 733, .cpu_id = 188, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU8_SECURITY_ERROR" },
+	{ .fc_id = 734, .cpu_id = 189, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 735, .cpu_id = 189, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HMMU9_PAGE_FAULT_WR_PERM" },
+	{ .fc_id = 736, .cpu_id = 189, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU9_SECURITY_ERROR" },
+	{ .fc_id = 737, .cpu_id = 190, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 738, .cpu_id = 190, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HMMU10_PAGE_FAULT_WR_PERM" },
+	{ .fc_id = 739, .cpu_id = 190, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU10_SECURITY_ERROR" },
+	{ .fc_id = 740, .cpu_id = 191, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 741, .cpu_id = 191, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HMMU11_PAGE_FAULT_WR_PERM" },
+	{ .fc_id = 742, .cpu_id = 191, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU11_SECURITY_ERROR" },
+	{ .fc_id = 743, .cpu_id = 192, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 744, .cpu_id = 192, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HMMU7_PAGE_FAULT_WR_PERM" },
+	{ .fc_id = 745, .cpu_id = 192, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU7_SECURITY_ERROR" },
+	{ .fc_id = 746, .cpu_id = 193, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 747, .cpu_id = 193, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HMMU6_PAGE_FAULT_WR_PERM" },
+	{ .fc_id = 748, .cpu_id = 193, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU6_SECURITY_ERROR" },
+	{ .fc_id = 749, .cpu_id = 194, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 750, .cpu_id = 194, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HMMU5_PAGE_FAULT_WR_PERM" },
+	{ .fc_id = 751, .cpu_id = 194, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU5_SECURITY_ERROR" },
+	{ .fc_id = 752, .cpu_id = 195, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 753, .cpu_id = 195, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HMMU4_PAGE_FAULT_WR_PERM" },
+	{ .fc_id = 754, .cpu_id = 195, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU4_SECURITY_ERROR" },
+	{ .fc_id = 755, .cpu_id = 196, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 756, .cpu_id = 196, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HMMU15_PAGE_FAULT_WR_PERM" },
+	{ .fc_id = 757, .cpu_id = 196, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU15_SECURITY_ERROR" },
+	{ .fc_id = 758, .cpu_id = 197, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 759, .cpu_id = 197, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HMMU14_PAGE_FAULT_WR_PERM" },
+	{ .fc_id = 760, .cpu_id = 197, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU14_SECURITY_ERROR" },
+	{ .fc_id = 761, .cpu_id = 198, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 762, .cpu_id = 198, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HMMU13_PAGE_FAULT_WR_PERM" },
+	{ .fc_id = 763, .cpu_id = 198, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU13_SECURITY_ERROR" },
+	{ .fc_id = 764, .cpu_id = 199, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 765, .cpu_id = 199, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HMMU12_PAGE_FAULT_WR_PERM" },
+	{ .fc_id = 766, .cpu_id = 199, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "HMMU12_SECURITY_ERROR" },
+	{ .fc_id = 767, .cpu_id = 200, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 768, .cpu_id = 201, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "PMMU0_PAGE_FAULT_WR_PERM" },
+	{ .fc_id = 769, .cpu_id = 202, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "PMMU0_SECURITY_ERROR" },
+	{ .fc_id = 770, .cpu_id = 203, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "EDMA2_BM_SPMU" },
+	{ .fc_id = 771, .cpu_id = 204, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 772, .cpu_id = 205, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "EDMA3_BM_SPMU" },
+	{ .fc_id = 773, .cpu_id = 206, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 774, .cpu_id = 207, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "EDMA0_BM_SPMU" },
+	{ .fc_id = 775, .cpu_id = 208, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 776, .cpu_id = 209, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "EDMA1_BM_SPMU" },
+	{ .fc_id = 777, .cpu_id = 210, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 778, .cpu_id = 211, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "EDMA6_BM_SPMU" },
+	{ .fc_id = 779, .cpu_id = 212, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 780, .cpu_id = 213, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "EDMA7_BM_SPMU" },
+	{ .fc_id = 781, .cpu_id = 214, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 782, .cpu_id = 215, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "EDMA4_BM_SPMU" },
+	{ .fc_id = 783, .cpu_id = 216, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 784, .cpu_id = 217, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "EDMA5_BM_SPMU" },
+	{ .fc_id = 785, .cpu_id = 218, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 786, .cpu_id = 219, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "KDMA_BM_SPMU" },
+	{ .fc_id = 787, .cpu_id = 220, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 788, .cpu_id = 221, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "PDMA0_BM_SPMU" },
+	{ .fc_id = 789, .cpu_id = 222, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "PDMA1_BM_SPMU" },
+	{ .fc_id = 790, .cpu_id = 223, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HBM0_MC0_SPI" },
+	{ .fc_id = 791, .cpu_id = 224, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HBM0_MC1_SPI" },
+	{ .fc_id = 792, .cpu_id = 225, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HBM1_MC0_SPI" },
+	{ .fc_id = 793, .cpu_id = 226, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HBM1_MC1_SPI" },
+	{ .fc_id = 794, .cpu_id = 227, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HBM2_MC0_SPI" },
+	{ .fc_id = 795, .cpu_id = 228, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HBM2_MC1_SPI" },
+	{ .fc_id = 796, .cpu_id = 229, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HBM3_MC0_SPI" },
+	{ .fc_id = 797, .cpu_id = 230, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HBM3_MC1_SPI" },
+	{ .fc_id = 798, .cpu_id = 231, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HBM4_MC0_SPI" },
+	{ .fc_id = 799, .cpu_id = 232, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HBM4_MC1_SPI" },
+	{ .fc_id = 800, .cpu_id = 233, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HBM5_MC0_SPI" },
+	{ .fc_id = 801, .cpu_id = 234, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HBM5_MC1_SPI" },
+	{ .fc_id = 802, .cpu_id = 235, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 803, .cpu_id = 236, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 804, .cpu_id = 237, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 805, .cpu_id = 238, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 806, .cpu_id = 239, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 807, .cpu_id = 240, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 808, .cpu_id = 241, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 809, .cpu_id = 242, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 810, .cpu_id = 243, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 811, .cpu_id = 244, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 812, .cpu_id = 245, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 813, .cpu_id = 246, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 814, .cpu_id = 247, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 815, .cpu_id = 248, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 816, .cpu_id = 249, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 817, .cpu_id = 250, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 818, .cpu_id = 251, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 819, .cpu_id = 252, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 820, .cpu_id = 253, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 821, .cpu_id = 254, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 822, .cpu_id = 255, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 823, .cpu_id = 256, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 824, .cpu_id = 257, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 825, .cpu_id = 258, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 826, .cpu_id = 259, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 827, .cpu_id = 260, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 828, .cpu_id = 261, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 829, .cpu_id = 262, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 830, .cpu_id = 263, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 831, .cpu_id = 264, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 832, .cpu_id = 265, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 833, .cpu_id = 266, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 834, .cpu_id = 267, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 835, .cpu_id = 268, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 836, .cpu_id = 269, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 837, .cpu_id = 270, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 838, .cpu_id = 271, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 839, .cpu_id = 272, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 840, .cpu_id = 273, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 841, .cpu_id = 274, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 842, .cpu_id = 275, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 843, .cpu_id = 276, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 844, .cpu_id = 277, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 845, .cpu_id = 278, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 846, .cpu_id = 279, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 847, .cpu_id = 280, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 848, .cpu_id = 281, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 849, .cpu_id = 282, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 850, .cpu_id = 283, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 851, .cpu_id = 284, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 852, .cpu_id = 285, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 853, .cpu_id = 286, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 854, .cpu_id = 287, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "" },
+	{ .fc_id = 855, .cpu_id = 288, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "" },
+	{ .fc_id = 856, .cpu_id = 289, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 857, .cpu_id = 290, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 858, .cpu_id = 291, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 859, .cpu_id = 292, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 860, .cpu_id = 293, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 861, .cpu_id = 294, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 862, .cpu_id = 295, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 863, .cpu_id = 296, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 864, .cpu_id = 297, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 865, .cpu_id = 298, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 866, .cpu_id = 299, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 867, .cpu_id = 300, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 868, .cpu_id = 301, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 869, .cpu_id = 302, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 870, .cpu_id = 303, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 871, .cpu_id = 304, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "RPM_ERROR_OR_DRAIN" },
+	{ .fc_id = 872, .cpu_id = 305, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 873, .cpu_id = 306, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 874, .cpu_id = 307, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 875, .cpu_id = 308, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "RAZWI_OR_PID_MIN_MAX_INTERRUPT" },
+	{ .fc_id = 876, .cpu_id = 309, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 877, .cpu_id = 310, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 878, .cpu_id = 311, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 879, .cpu_id = 312, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "" },
+	{ .fc_id = 880, .cpu_id = 313, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 881, .cpu_id = 314, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 882, .cpu_id = 315, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 883, .cpu_id = 316, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 884, .cpu_id = 317, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 885, .cpu_id = 318, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 886, .cpu_id = 319, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 887, .cpu_id = 320, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 888, .cpu_id = 321, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 889, .cpu_id = 322, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 890, .cpu_id = 323, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 891, .cpu_id = 324, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 892, .cpu_id = 325, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 893, .cpu_id = 326, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 894, .cpu_id = 327, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 895, .cpu_id = 328, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 896, .cpu_id = 329, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DEC0_SPI" },
+	{ .fc_id = 897, .cpu_id = 329, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "DEC0_BMON_SPMU" },
+	{ .fc_id = 898, .cpu_id = 330, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DEC1_SPI" },
+	{ .fc_id = 899, .cpu_id = 330, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "DEC1_BMON_SPMU" },
+	{ .fc_id = 900, .cpu_id = 331, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DEC2_SPI" },
+	{ .fc_id = 901, .cpu_id = 331, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "DEC2_BMON_SPMU" },
+	{ .fc_id = 902, .cpu_id = 332, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DEC3_SPI" },
+	{ .fc_id = 903, .cpu_id = 332, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "DEC3_BMON_SPMU" },
+	{ .fc_id = 904, .cpu_id = 333, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DEC4_SPI" },
+	{ .fc_id = 905, .cpu_id = 333, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "DEC4_BMON_SPMU" },
+	{ .fc_id = 906, .cpu_id = 334, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DEC5_SPI" },
+	{ .fc_id = 907, .cpu_id = 334, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "DEC5_BMON_SPMU" },
+	{ .fc_id = 908, .cpu_id = 335, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DEC6_SPI" },
+	{ .fc_id = 909, .cpu_id = 335, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "DEC6_BMON_SPMU" },
+	{ .fc_id = 910, .cpu_id = 336, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DEC7_SPI" },
+	{ .fc_id = 911, .cpu_id = 336, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "DEC7_BMON_SPMU" },
+	{ .fc_id = 912, .cpu_id = 337, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DEC8_SPI" },
+	{ .fc_id = 913, .cpu_id = 337, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "DEC8_BMON_SPMU" },
+	{ .fc_id = 914, .cpu_id = 338, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DEC9_SPI" },
+	{ .fc_id = 915, .cpu_id = 338, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "DEC9_BMON_SPMU" },
+	{ .fc_id = 916, .cpu_id = 339, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 917, .cpu_id = 340, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 918, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 919, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 920, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 921, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 922, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 923, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 924, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 925, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 926, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 927, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 928, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 929, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 930, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 931, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 932, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 933, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 934, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 935, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 936, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 937, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 938, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 939, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 940, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 941, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 942, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 943, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 944, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 945, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 946, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 947, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 948, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 949, .cpu_id = 341, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 950, .cpu_id = 342, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 951, .cpu_id = 343, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "NIC0_BMON_SPMU" },
+	{ .fc_id = 952, .cpu_id = 343, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "NIC0_SW_ERROR" },
+	{ .fc_id = 953, .cpu_id = 343, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 954, .cpu_id = 343, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 955, .cpu_id = 344, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "NIC1_BMON_SPMU" },
+	{ .fc_id = 956, .cpu_id = 344, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "NIC1_SW_ERROR" },
+	{ .fc_id = 957, .cpu_id = 344, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 958, .cpu_id = 344, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 959, .cpu_id = 345, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "NIC2_BMON_SPMU" },
+	{ .fc_id = 960, .cpu_id = 345, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "NIC2_SW_ERROR" },
+	{ .fc_id = 961, .cpu_id = 345, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 962, .cpu_id = 345, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 963, .cpu_id = 346, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "NIC3_BMON_SPMU" },
+	{ .fc_id = 964, .cpu_id = 346, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "NIC3_SW_ERROR" },
+	{ .fc_id = 965, .cpu_id = 346, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 966, .cpu_id = 346, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 967, .cpu_id = 347, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "NIC4_BMON_SPMU" },
+	{ .fc_id = 968, .cpu_id = 347, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "NIC4_SW_ERROR" },
+	{ .fc_id = 969, .cpu_id = 347, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 970, .cpu_id = 347, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 971, .cpu_id = 348, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "NIC5_BMON_SPMU" },
+	{ .fc_id = 972, .cpu_id = 348, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "NIC5_SW_ERROR" },
+	{ .fc_id = 973, .cpu_id = 348, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 974, .cpu_id = 348, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 975, .cpu_id = 349, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "NIC6_BMON_SPMU" },
+	{ .fc_id = 976, .cpu_id = 349, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "NIC6_SW_ERROR" },
+	{ .fc_id = 977, .cpu_id = 349, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 978, .cpu_id = 349, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 979, .cpu_id = 350, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "NIC7_BMON_SPMU" },
+	{ .fc_id = 980, .cpu_id = 350, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "NIC7_SW_ERROR" },
+	{ .fc_id = 981, .cpu_id = 350, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 982, .cpu_id = 350, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 983, .cpu_id = 351, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "NIC8_BMON_SPMU" },
+	{ .fc_id = 984, .cpu_id = 351, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "NIC8_SW_ERROR" },
+	{ .fc_id = 985, .cpu_id = 351, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 986, .cpu_id = 351, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 987, .cpu_id = 352, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "NIC9_BMON_SPMU" },
+	{ .fc_id = 988, .cpu_id = 352, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "NIC9_SW_ERROR" },
+	{ .fc_id = 989, .cpu_id = 352, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 990, .cpu_id = 352, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 991, .cpu_id = 353, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "NIC10_BMON_SPMU" },
+	{ .fc_id = 992, .cpu_id = 353, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "NIC10_SW_ERROR" },
+	{ .fc_id = 993, .cpu_id = 353, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 994, .cpu_id = 353, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 995, .cpu_id = 354, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "NIC11_BMON_SPMU" },
+	{ .fc_id = 996, .cpu_id = 354, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "NIC11_SW_ERROR" },
+	{ .fc_id = 997, .cpu_id = 354, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 998, .cpu_id = 354, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 999, .cpu_id = 355, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1000, .cpu_id = 356, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1001, .cpu_id = 357, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1002, .cpu_id = 358, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1003, .cpu_id = 359, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1004, .cpu_id = 360, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1005, .cpu_id = 361, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1006, .cpu_id = 362, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1007, .cpu_id = 363, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1008, .cpu_id = 368, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1009, .cpu_id = 369, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1010, .cpu_id = 366, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1011, .cpu_id = 367, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1012, .cpu_id = 364, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1013, .cpu_id = 365, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1014, .cpu_id = 374, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1015, .cpu_id = 375, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1016, .cpu_id = 372, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1017, .cpu_id = 373, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1018, .cpu_id = 370, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1019, .cpu_id = 371, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1020, .cpu_id = 376, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1021, .cpu_id = 377, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1022, .cpu_id = 378, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1023, .cpu_id = 379, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1024, .cpu_id = 380, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1025, .cpu_id = 381, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1026, .cpu_id = 382, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1027, .cpu_id = 383, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1028, .cpu_id = 384, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1029, .cpu_id = 385, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1030, .cpu_id = 386, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1031, .cpu_id = 387, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1032, .cpu_id = 388, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1033, .cpu_id = 389, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1034, .cpu_id = 390, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1035, .cpu_id = 391, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1036, .cpu_id = 392, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1037, .cpu_id = 393, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1038, .cpu_id = 394, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1039, .cpu_id = 395, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1040, .cpu_id = 396, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1041, .cpu_id = 397, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1042, .cpu_id = 398, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1043, .cpu_id = 399, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1044, .cpu_id = 400, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1045, .cpu_id = 401, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1046, .cpu_id = 402, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1047, .cpu_id = 403, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1048, .cpu_id = 404, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1049, .cpu_id = 405, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1050, .cpu_id = 406, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1051, .cpu_id = 407, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1052, .cpu_id = 408, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1053, .cpu_id = 409, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1054, .cpu_id = 410, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1055, .cpu_id = 411, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1056, .cpu_id = 412, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1057, .cpu_id = 413, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1058, .cpu_id = 414, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1059, .cpu_id = 414, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1060, .cpu_id = 414, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1061, .cpu_id = 414, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1062, .cpu_id = 414, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1063, .cpu_id = 414, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1064, .cpu_id = 414, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1065, .cpu_id = 414, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1066, .cpu_id = 414, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1067, .cpu_id = 414, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1068, .cpu_id = 415, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1069, .cpu_id = 416, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1070, .cpu_id = 416, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1071, .cpu_id = 416, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1072, .cpu_id = 416, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1073, .cpu_id = 416, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1074, .cpu_id = 416, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1075, .cpu_id = 416, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1076, .cpu_id = 416, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1077, .cpu_id = 416, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1078, .cpu_id = 416, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1079, .cpu_id = 416, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1080, .cpu_id = 416, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1081, .cpu_id = 416, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1082, .cpu_id = 416, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1083, .cpu_id = 416, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1084, .cpu_id = 416, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1085, .cpu_id = 417, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1086, .cpu_id = 417, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1087, .cpu_id = 417, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1088, .cpu_id = 417, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1089, .cpu_id = 417, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1090, .cpu_id = 417, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1091, .cpu_id = 417, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1092, .cpu_id = 417, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1093, .cpu_id = 417, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1094, .cpu_id = 417, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1095, .cpu_id = 417, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1096, .cpu_id = 417, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1097, .cpu_id = 417, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1098, .cpu_id = 417, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1099, .cpu_id = 417, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1100, .cpu_id = 417, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1101, .cpu_id = 418, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1102, .cpu_id = 419, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1103, .cpu_id = 420, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1104, .cpu_id = 421, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1105, .cpu_id = 422, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1106, .cpu_id = 422, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1107, .cpu_id = 422, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1108, .cpu_id = 422, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1109, .cpu_id = 422, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1110, .cpu_id = 422, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1111, .cpu_id = 422, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1112, .cpu_id = 422, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1113, .cpu_id = 422, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1114, .cpu_id = 422, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1115, .cpu_id = 422, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1116, .cpu_id = 422, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1117, .cpu_id = 423, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1118, .cpu_id = 424, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "ROTATOR0_SERR" },
+	{ .fc_id = 1119, .cpu_id = 425, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "ROTATOR1_SERR" },
+	{ .fc_id = 1120, .cpu_id = 426, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "ROTATOR0_DERR" },
+	{ .fc_id = 1121, .cpu_id = 427, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "ROTATOR1_DERR" },
+	{ .fc_id = 1122, .cpu_id = 428, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "ROTATOR0_AXI_ERROR_RESPONSE" },
+	{ .fc_id = 1123, .cpu_id = 429, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "ROTATOR1_AXI_ERROR_RESPONSE" },
+	{ .fc_id = 1124, .cpu_id = 430, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1125, .cpu_id = 431, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1126, .cpu_id = 432, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "ROTATOR0_BMON_SPMU" },
+	{ .fc_id = 1127, .cpu_id = 433, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1128, .cpu_id = 434, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "ROTATOR1_BMON_SPMU" },
+	{ .fc_id = 1129, .cpu_id = 435, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1130, .cpu_id = 436, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "SM0_BMON_SPMU" },
+	{ .fc_id = 1131, .cpu_id = 437, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "SM1_BMON_SPMU" },
+	{ .fc_id = 1132, .cpu_id = 438, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "SM2_BMON_SPMU" },
+	{ .fc_id = 1133, .cpu_id = 439, .valid = 1, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "SM3_BMON_SPMU" },
+	{ .fc_id = 1134, .cpu_id = 440, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1135, .cpu_id = 441, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1136, .cpu_id = 442, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1137, .cpu_id = 443, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1138, .cpu_id = 444, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1139, .cpu_id = 445, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1140, .cpu_id = 446, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1141, .cpu_id = 447, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1142, .cpu_id = 448, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1143, .cpu_id = 449, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1144, .cpu_id = 450, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1145, .cpu_id = 451, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1146, .cpu_id = 452, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1147, .cpu_id = 453, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1148, .cpu_id = 454, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1149, .cpu_id = 455, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1150, .cpu_id = 456, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1151, .cpu_id = 457, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1152, .cpu_id = 458, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1153, .cpu_id = 459, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1154, .cpu_id = 460, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1155, .cpu_id = 461, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1156, .cpu_id = 462, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1157, .cpu_id = 463, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1158, .cpu_id = 464, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1159, .cpu_id = 465, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1160, .cpu_id = 466, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1161, .cpu_id = 467, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1162, .cpu_id = 468, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1163, .cpu_id = 469, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1164, .cpu_id = 470, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1165, .cpu_id = 471, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1166, .cpu_id = 472, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1167, .cpu_id = 473, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1168, .cpu_id = 474, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1169, .cpu_id = 475, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1170, .cpu_id = 476, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1171, .cpu_id = 477, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1172, .cpu_id = 478, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1173, .cpu_id = 479, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1174, .cpu_id = 480, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "PSOC_DMA_QM" },
+	{ .fc_id = 1175, .cpu_id = 481, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1176, .cpu_id = 482, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1177, .cpu_id = 483, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1178, .cpu_id = 484, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1179, .cpu_id = 485, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1180, .cpu_id = 486, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1181, .cpu_id = 487, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1182, .cpu_id = 488, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1183, .cpu_id = 489, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1184, .cpu_id = 490, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1185, .cpu_id = 491, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1186, .cpu_id = 492, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1187, .cpu_id = 493, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1188, .cpu_id = 494, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1189, .cpu_id = 495, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1190, .cpu_id = 496, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1191, .cpu_id = 497, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1192, .cpu_id = 498, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1193, .cpu_id = 499, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1194, .cpu_id = 500, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1195, .cpu_id = 501, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1196, .cpu_id = 502, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1197, .cpu_id = 503, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1198, .cpu_id = 504, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1199, .cpu_id = 505, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1200, .cpu_id = 506, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1201, .cpu_id = 507, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1202, .cpu_id = 508, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1203, .cpu_id = 509, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1204, .cpu_id = 510, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1205, .cpu_id = 511, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1206, .cpu_id = 512, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE0_TPC0_QM" },
+	{ .fc_id = 1207, .cpu_id = 513, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE0_TPC1_QM" },
+	{ .fc_id = 1208, .cpu_id = 514, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE0_TPC2_QM" },
+	{ .fc_id = 1209, .cpu_id = 515, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE0_TPC3_QM" },
+	{ .fc_id = 1210, .cpu_id = 516, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE0_TPC4_QM" },
+	{ .fc_id = 1211, .cpu_id = 517, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE0_TPC5_QM" },
+	{ .fc_id = 1212, .cpu_id = 518, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE1_TPC0_QM" },
+	{ .fc_id = 1213, .cpu_id = 519, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE1_TPC1_QM" },
+	{ .fc_id = 1214, .cpu_id = 520, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE1_TPC2_QM" },
+	{ .fc_id = 1215, .cpu_id = 521, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE1_TPC3_QM" },
+	{ .fc_id = 1216, .cpu_id = 522, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE1_TPC4_QM" },
+	{ .fc_id = 1217, .cpu_id = 523, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE1_TPC5_QM" },
+	{ .fc_id = 1218, .cpu_id = 524, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE2_TPC0_QM" },
+	{ .fc_id = 1219, .cpu_id = 525, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE2_TPC1_QM" },
+	{ .fc_id = 1220, .cpu_id = 526, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE2_TPC2_QM" },
+	{ .fc_id = 1221, .cpu_id = 527, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE2_TPC3_QM" },
+	{ .fc_id = 1222, .cpu_id = 528, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE2_TPC4_QM" },
+	{ .fc_id = 1223, .cpu_id = 529, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE2_TPC5_QM" },
+	{ .fc_id = 1224, .cpu_id = 530, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE3_TPC0_QM" },
+	{ .fc_id = 1225, .cpu_id = 531, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE3_TPC1_QM" },
+	{ .fc_id = 1226, .cpu_id = 532, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE3_TPC2_QM" },
+	{ .fc_id = 1227, .cpu_id = 533, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE3_TPC3_QM" },
+	{ .fc_id = 1228, .cpu_id = 534, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE3_TPC4_QM" },
+	{ .fc_id = 1229, .cpu_id = 535, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE3_TPC5_QM" },
+	{ .fc_id = 1230, .cpu_id = 536, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "DCORE4_TPC0_QM" },
+	{ .fc_id = 1231, .cpu_id = 537, .valid = 0, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "" },
+	{ .fc_id = 1232, .cpu_id = 538, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "MME0_QM" },
+	{ .fc_id = 1233, .cpu_id = 539, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "MME1_QM" },
+	{ .fc_id = 1234, .cpu_id = 540, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "MME2_QM" },
+	{ .fc_id = 1235, .cpu_id = 541, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "MME3_QM" },
+	{ .fc_id = 1236, .cpu_id = 542, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "EDMA2_QM" },
+	{ .fc_id = 1237, .cpu_id = 543, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "EDMA3_QM" },
+	{ .fc_id = 1238, .cpu_id = 544, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "EDMA0_QM" },
+	{ .fc_id = 1239, .cpu_id = 545, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "EDMA1_QM" },
+	{ .fc_id = 1240, .cpu_id = 546, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "EDMA6_QM" },
+	{ .fc_id = 1241, .cpu_id = 547, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "EDMA7_QM" },
+	{ .fc_id = 1242, .cpu_id = 548, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "EDMA4_QM" },
+	{ .fc_id = 1243, .cpu_id = 549, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "EDMA5_QM" },
+	{ .fc_id = 1244, .cpu_id = 550, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "PDMA0_QM" },
+	{ .fc_id = 1245, .cpu_id = 551, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "PDMA1_QM" },
+	{ .fc_id = 1246, .cpu_id = 552, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "PI_UPDATE" },
+	{ .fc_id = 1247, .cpu_id = 553, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "HALT_MACHINE" },
+	{ .fc_id = 1248, .cpu_id = 554, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "INTS_REGISTER" },
+	{ .fc_id = 1249, .cpu_id = 555, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "ROT0_QM" },
+	{ .fc_id = 1250, .cpu_id = 556, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "ROT1_QM" },
+	{ .fc_id = 1251, .cpu_id = 557, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "SOFT_RESET" },
+	{ .fc_id = 1252, .cpu_id = 558, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "CPLD_SHUTDOWN_CAUSE" },
+	{ .fc_id = 1253, .cpu_id = 559, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "FIX_POWER_ENV_S" },
+	{ .fc_id = 1254, .cpu_id = 560, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "FIX_POWER_ENV_E" },
+	{ .fc_id = 1255, .cpu_id = 561, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "FIX_THERMAL_ENV_S" },
+	{ .fc_id = 1256, .cpu_id = 562, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "FIX_THERMAL_ENV_E" },
+	{ .fc_id = 1257, .cpu_id = 563, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "CPLD_SHUTDOWN_EVENT" },
+	{ .fc_id = 1258, .cpu_id = 564, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "PKT_QUEUE_OUT_SYNC" },
+	{ .fc_id = 1259, .cpu_id = 565, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "EDMA2_CORE" },
+	{ .fc_id = 1260, .cpu_id = 566, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "EDMA3_CORE" },
+	{ .fc_id = 1261, .cpu_id = 567, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "EDMA0_CORE" },
+	{ .fc_id = 1262, .cpu_id = 568, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "EDMA1_CORE" },
+	{ .fc_id = 1263, .cpu_id = 569, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "EDMA6_CORE" },
+	{ .fc_id = 1264, .cpu_id = 570, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "EDMA7_CORE" },
+	{ .fc_id = 1265, .cpu_id = 571, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "EDMA4_CORE" },
+	{ .fc_id = 1266, .cpu_id = 572, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "EDMA5_CORE" },
+	{ .fc_id = 1267, .cpu_id = 573, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "PDMA0_CORE" },
+	{ .fc_id = 1268, .cpu_id = 574, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "PDMA1_CORE" },
+	{ .fc_id = 1269, .cpu_id = 575, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "KDMA0_CORE" },
+	{ .fc_id = 1270, .cpu_id = 576, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC0_QM0" },
+	{ .fc_id = 1271, .cpu_id = 577, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC0_QM1" },
+	{ .fc_id = 1272, .cpu_id = 578, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC1_QM0" },
+	{ .fc_id = 1273, .cpu_id = 579, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC1_QM1" },
+	{ .fc_id = 1274, .cpu_id = 580, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC2_QM0" },
+	{ .fc_id = 1275, .cpu_id = 581, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC2_QM1" },
+	{ .fc_id = 1276, .cpu_id = 582, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC3_QM0" },
+	{ .fc_id = 1277, .cpu_id = 583, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC3_QM1" },
+	{ .fc_id = 1278, .cpu_id = 584, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC4_QM0" },
+	{ .fc_id = 1279, .cpu_id = 585, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC4_QM1" },
+	{ .fc_id = 1280, .cpu_id = 586, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC5_QM0" },
+	{ .fc_id = 1281, .cpu_id = 587, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC5_QM1" },
+	{ .fc_id = 1282, .cpu_id = 588, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC6_QM0" },
+	{ .fc_id = 1283, .cpu_id = 589, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC6_QM1" },
+	{ .fc_id = 1284, .cpu_id = 590, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC7_QM0" },
+	{ .fc_id = 1285, .cpu_id = 591, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC7_QM1" },
+	{ .fc_id = 1286, .cpu_id = 592, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC8_QM0" },
+	{ .fc_id = 1287, .cpu_id = 593, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC8_QM1" },
+	{ .fc_id = 1288, .cpu_id = 594, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC9_QM0" },
+	{ .fc_id = 1289, .cpu_id = 595, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC9_QM1" },
+	{ .fc_id = 1290, .cpu_id = 596, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC10_QM0" },
+	{ .fc_id = 1291, .cpu_id = 597, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC10_QM1" },
+	{ .fc_id = 1292, .cpu_id = 598, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC11_QM0" },
+	{ .fc_id = 1293, .cpu_id = 599, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "NIC11_QM1" },
+	{ .fc_id = 1294, .cpu_id = 600, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "CPU_PKT_SANITY_FAILED" },
+	{ .fc_id = 1295, .cpu_id = 601, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "STATUS_NIC0_ENG0" },
+	{ .fc_id = 1296, .cpu_id = 602, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "STATUS_NIC0_ENG1" },
+	{ .fc_id = 1297, .cpu_id = 603, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "STATUS_NIC1_ENG0" },
+	{ .fc_id = 1298, .cpu_id = 604, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "STATUS_NIC1_ENG1" },
+	{ .fc_id = 1299, .cpu_id = 605, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "STATUS_NIC2_ENG0" },
+	{ .fc_id = 1300, .cpu_id = 606, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "STATUS_NIC2_ENG1" },
+	{ .fc_id = 1301, .cpu_id = 607, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "STATUS_NIC3_ENG0" },
+	{ .fc_id = 1302, .cpu_id = 608, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "STATUS_NIC3_ENG1" },
+	{ .fc_id = 1303, .cpu_id = 609, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "STATUS_NIC4_ENG0" },
+	{ .fc_id = 1304, .cpu_id = 610, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "STATUS_NIC4_ENG1" },
+	{ .fc_id = 1305, .cpu_id = 611, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "STATUS_NIC5_ENG0" },
+	{ .fc_id = 1306, .cpu_id = 612, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "STATUS_NIC5_ENG1" },
+	{ .fc_id = 1307, .cpu_id = 613, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "STATUS_NIC6_ENG0" },
+	{ .fc_id = 1308, .cpu_id = 614, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "STATUS_NIC6_ENG1" },
+	{ .fc_id = 1309, .cpu_id = 615, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "STATUS_NIC7_ENG0" },
+	{ .fc_id = 1310, .cpu_id = 616, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "STATUS_NIC7_ENG1" },
+	{ .fc_id = 1311, .cpu_id = 617, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "STATUS_NIC8_ENG0" },
+	{ .fc_id = 1312, .cpu_id = 618, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "STATUS_NIC8_ENG1" },
+	{ .fc_id = 1313, .cpu_id = 619, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "STATUS_NIC9_ENG0" },
+	{ .fc_id = 1314, .cpu_id = 620, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "STATUS_NIC9_ENG1" },
+	{ .fc_id = 1315, .cpu_id = 621, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "STATUS_NIC10_ENG0" },
+	{ .fc_id = 1316, .cpu_id = 622, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "STATUS_NIC10_ENG1" },
+	{ .fc_id = 1317, .cpu_id = 623, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "STATUS_NIC11_ENG0" },
+	{ .fc_id = 1318, .cpu_id = 624, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "STATUS_NIC11_ENG1" },
+	{ .fc_id = 1319, .cpu_id = 625, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_COMPUTE,
+		 .name = "ARC_DCCM_FULL" },
+	{ .fc_id = 1320, .cpu_id = 626, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "FP32_NOT_SUPPORTED" },
+	{ .fc_id = 1321, .cpu_id = 627, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_HARD,
+		 .name = "DEV_RESET_REQ" },
+	{ .fc_id = 1322, .cpu_id = 628, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "PWR_BRK_ENTRY" },
+	{ .fc_id = 1323, .cpu_id = 629, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "PWR_BRK_EXT" },
+	{ .fc_id = 1324, .cpu_id = 630, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "PWR_RD_MODE0" },
+	{ .fc_id = 1325, .cpu_id = 631, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "PWR_RD_MODE1" },
+	{ .fc_id = 1326, .cpu_id = 632, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "PWR_RD_MODE2" },
+	{ .fc_id = 1327, .cpu_id = 633, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "PWR_RD_MODE3" },
+	{ .fc_id = 1328, .cpu_id = 634, .valid = 1, .msg = 1, .reset = EVENT_RESET_TYPE_NONE,
+		 .name = "EQ_HEARTBEAT" },
+};
+
+#endif /* __GAUDI2_ASYNC_IDS_MAP_EVENTS_EXT_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/gaudi2_coresight.h b/drivers/accel/habanalabs/include/gaudi2/gaudi2_coresight.h
new file mode 100644
index 000000000000..14f09d7758c7
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/gaudi2_coresight.h
@@ -0,0 +1,984 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef GAUDI2_CORESIGHT_H
+#define GAUDI2_CORESIGHT_H
+
+enum gaudi2_debug_stm_regs_index {
+	GAUDI2_STM_FIRST = 0,
+	GAUDI2_STM_DCORE0_TPC0_EML = GAUDI2_STM_FIRST,
+	GAUDI2_STM_DCORE0_TPC1_EML,
+	GAUDI2_STM_DCORE0_TPC2_EML,
+	GAUDI2_STM_DCORE0_TPC3_EML,
+	GAUDI2_STM_DCORE0_TPC4_EML,
+	GAUDI2_STM_DCORE0_TPC5_EML,
+	GAUDI2_STM_DCORE0_TPC6_EML,
+	GAUDI2_STM_DCORE1_TPC0_EML,
+	GAUDI2_STM_DCORE1_TPC1_EML,
+	GAUDI2_STM_DCORE1_TPC2_EML,
+	GAUDI2_STM_DCORE1_TPC3_EML,
+	GAUDI2_STM_DCORE1_TPC4_EML,
+	GAUDI2_STM_DCORE1_TPC5_EML,
+	GAUDI2_STM_DCORE2_TPC0_EML,
+	GAUDI2_STM_DCORE2_TPC1_EML,
+	GAUDI2_STM_DCORE2_TPC2_EML,
+	GAUDI2_STM_DCORE2_TPC3_EML,
+	GAUDI2_STM_DCORE2_TPC4_EML,
+	GAUDI2_STM_DCORE2_TPC5_EML,
+	GAUDI2_STM_DCORE3_TPC0_EML,
+	GAUDI2_STM_DCORE3_TPC1_EML,
+	GAUDI2_STM_DCORE3_TPC2_EML,
+	GAUDI2_STM_DCORE3_TPC3_EML,
+	GAUDI2_STM_DCORE3_TPC4_EML,
+	GAUDI2_STM_DCORE3_TPC5_EML,
+	GAUDI2_STM_DCORE0_HMMU0_CS,
+	GAUDI2_STM_DCORE0_HMMU1_CS,
+	GAUDI2_STM_DCORE0_HMMU2_CS,
+	GAUDI2_STM_DCORE0_HMMU3_CS,
+	GAUDI2_STM_DCORE0_MME_CTRL,
+	GAUDI2_STM_DCORE0_MME_SBTE0,
+	GAUDI2_STM_DCORE0_MME_SBTE1,
+	GAUDI2_STM_DCORE0_MME_SBTE2,
+	GAUDI2_STM_DCORE0_MME_SBTE3,
+	GAUDI2_STM_DCORE0_MME_SBTE4,
+	GAUDI2_STM_DCORE0_MME_ACC,
+	GAUDI2_STM_DCORE0_SM,
+	GAUDI2_STM_DCORE0_EDMA0_CS,
+	GAUDI2_STM_DCORE0_EDMA1_CS,
+	GAUDI2_STM_DCORE0_VDEC0_CS,
+	GAUDI2_STM_DCORE0_VDEC1_CS,
+	GAUDI2_STM_DCORE1_HMMU0_CS,
+	GAUDI2_STM_DCORE1_HMMU1_CS,
+	GAUDI2_STM_DCORE1_HMMU2_CS,
+	GAUDI2_STM_DCORE1_HMMU3_CS,
+	GAUDI2_STM_DCORE1_MME_CTRL,
+	GAUDI2_STM_DCORE1_MME_SBTE0,
+	GAUDI2_STM_DCORE1_MME_SBTE1,
+	GAUDI2_STM_DCORE1_MME_SBTE2,
+	GAUDI2_STM_DCORE1_MME_SBTE3,
+	GAUDI2_STM_DCORE1_MME_SBTE4,
+	GAUDI2_STM_DCORE1_MME_ACC,
+	GAUDI2_STM_DCORE1_SM,
+	GAUDI2_STM_DCORE1_EDMA0_CS,
+	GAUDI2_STM_DCORE1_EDMA1_CS,
+	GAUDI2_STM_DCORE1_VDEC0_CS,
+	GAUDI2_STM_DCORE1_VDEC1_CS,
+	GAUDI2_STM_DCORE2_HMMU0_CS,
+	GAUDI2_STM_DCORE2_HMMU1_CS,
+	GAUDI2_STM_DCORE2_HMMU2_CS,
+	GAUDI2_STM_DCORE2_HMMU3_CS,
+	GAUDI2_STM_DCORE2_MME_CTRL,
+	GAUDI2_STM_DCORE2_MME_SBTE0,
+	GAUDI2_STM_DCORE2_MME_SBTE1,
+	GAUDI2_STM_DCORE2_MME_SBTE2,
+	GAUDI2_STM_DCORE2_MME_SBTE3,
+	GAUDI2_STM_DCORE2_MME_SBTE4,
+	GAUDI2_STM_DCORE2_MME_ACC,
+	GAUDI2_STM_DCORE2_SM,
+	GAUDI2_STM_DCORE2_EDMA0_CS,
+	GAUDI2_STM_DCORE2_EDMA1_CS,
+	GAUDI2_STM_DCORE2_VDEC0_CS,
+	GAUDI2_STM_DCORE2_VDEC1_CS,
+	GAUDI2_STM_DCORE3_HMMU0_CS,
+	GAUDI2_STM_DCORE3_HMMU1_CS,
+	GAUDI2_STM_DCORE3_HMMU2_CS,
+	GAUDI2_STM_DCORE3_HMMU3_CS,
+	GAUDI2_STM_DCORE3_MME_CTRL,
+	GAUDI2_STM_DCORE3_MME_SBTE0,
+	GAUDI2_STM_DCORE3_MME_SBTE1,
+	GAUDI2_STM_DCORE3_MME_SBTE2,
+	GAUDI2_STM_DCORE3_MME_SBTE3,
+	GAUDI2_STM_DCORE3_MME_SBTE4,
+	GAUDI2_STM_DCORE3_MME_ACC,
+	GAUDI2_STM_DCORE3_SM,
+	GAUDI2_STM_DCORE3_EDMA0_CS,
+	GAUDI2_STM_DCORE3_EDMA1_CS,
+	GAUDI2_STM_DCORE3_VDEC0_CS,
+	GAUDI2_STM_DCORE3_VDEC1_CS,
+	GAUDI2_STM_PCIE,
+	GAUDI2_STM_PSOC,
+	GAUDI2_STM_PSOC_ARC0_CS,
+	GAUDI2_STM_PSOC_ARC1_CS,
+	GAUDI2_STM_PDMA0_CS,
+	GAUDI2_STM_PDMA1_CS,
+	GAUDI2_STM_CPU,
+	GAUDI2_STM_PMMU_CS,
+	GAUDI2_STM_ROT0_CS,
+	GAUDI2_STM_ROT1_CS,
+	GAUDI2_STM_ARC_FARM_CS,
+	GAUDI2_STM_KDMA_CS,
+	GAUDI2_STM_PCIE_VDEC0_CS,
+	GAUDI2_STM_PCIE_VDEC1_CS,
+	GAUDI2_STM_HBM0_MC0_CS,
+	GAUDI2_STM_HBM0_MC1_CS,
+	GAUDI2_STM_HBM1_MC0_CS,
+	GAUDI2_STM_HBM1_MC1_CS,
+	GAUDI2_STM_HBM2_MC0_CS,
+	GAUDI2_STM_HBM2_MC1_CS,
+	GAUDI2_STM_HBM3_MC0_CS,
+	GAUDI2_STM_HBM3_MC1_CS,
+	GAUDI2_STM_HBM4_MC0_CS,
+	GAUDI2_STM_HBM4_MC1_CS,
+	GAUDI2_STM_HBM5_MC0_CS,
+	GAUDI2_STM_HBM5_MC1_CS,
+	GAUDI2_STM_NIC0_DBG_0,
+	GAUDI2_STM_NIC0_DBG_1,
+	GAUDI2_STM_NIC1_DBG_0,
+	GAUDI2_STM_NIC1_DBG_1,
+	GAUDI2_STM_NIC2_DBG_0,
+	GAUDI2_STM_NIC2_DBG_1,
+	GAUDI2_STM_NIC3_DBG_0,
+	GAUDI2_STM_NIC3_DBG_1,
+	GAUDI2_STM_NIC4_DBG_0,
+	GAUDI2_STM_NIC4_DBG_1,
+	GAUDI2_STM_NIC5_DBG_0,
+	GAUDI2_STM_NIC5_DBG_1,
+	GAUDI2_STM_NIC6_DBG_0,
+	GAUDI2_STM_NIC6_DBG_1,
+	GAUDI2_STM_NIC7_DBG_0,
+	GAUDI2_STM_NIC7_DBG_1,
+	GAUDI2_STM_NIC8_DBG_0,
+	GAUDI2_STM_NIC8_DBG_1,
+	GAUDI2_STM_NIC9_DBG_0,
+	GAUDI2_STM_NIC9_DBG_1,
+	GAUDI2_STM_NIC10_DBG_0,
+	GAUDI2_STM_NIC10_DBG_1,
+	GAUDI2_STM_NIC11_DBG_0,
+	GAUDI2_STM_NIC11_DBG_1,
+	GAUDI2_STM_LAST = GAUDI2_STM_NIC11_DBG_1
+};
+
+enum gaudi2_debug_etf_regs_index {
+	GAUDI2_ETF_FIRST = 0,
+	GAUDI2_ETF_DCORE0_TPC0_EML = GAUDI2_ETF_FIRST,
+	GAUDI2_ETF_DCORE0_TPC1_EML,
+	GAUDI2_ETF_DCORE0_TPC2_EML,
+	GAUDI2_ETF_DCORE0_TPC3_EML,
+	GAUDI2_ETF_DCORE0_TPC4_EML,
+	GAUDI2_ETF_DCORE0_TPC5_EML,
+	GAUDI2_ETF_DCORE0_TPC6_EML,
+	GAUDI2_ETF_DCORE1_TPC0_EML,
+	GAUDI2_ETF_DCORE1_TPC1_EML,
+	GAUDI2_ETF_DCORE1_TPC2_EML,
+	GAUDI2_ETF_DCORE1_TPC3_EML,
+	GAUDI2_ETF_DCORE1_TPC4_EML,
+	GAUDI2_ETF_DCORE1_TPC5_EML,
+	GAUDI2_ETF_DCORE2_TPC0_EML,
+	GAUDI2_ETF_DCORE2_TPC1_EML,
+	GAUDI2_ETF_DCORE2_TPC2_EML,
+	GAUDI2_ETF_DCORE2_TPC3_EML,
+	GAUDI2_ETF_DCORE2_TPC4_EML,
+	GAUDI2_ETF_DCORE2_TPC5_EML,
+	GAUDI2_ETF_DCORE3_TPC0_EML,
+	GAUDI2_ETF_DCORE3_TPC1_EML,
+	GAUDI2_ETF_DCORE3_TPC2_EML,
+	GAUDI2_ETF_DCORE3_TPC3_EML,
+	GAUDI2_ETF_DCORE3_TPC4_EML,
+	GAUDI2_ETF_DCORE3_TPC5_EML,
+	GAUDI2_ETF_DCORE0_HMMU0_CS,
+	GAUDI2_ETF_DCORE0_HMMU1_CS,
+	GAUDI2_ETF_DCORE0_HMMU2_CS,
+	GAUDI2_ETF_DCORE0_HMMU3_CS,
+	GAUDI2_ETF_DCORE0_MME_CTRL,
+	GAUDI2_ETF_DCORE0_MME_SBTE0,
+	GAUDI2_ETF_DCORE0_MME_SBTE1,
+	GAUDI2_ETF_DCORE0_MME_SBTE2,
+	GAUDI2_ETF_DCORE0_MME_SBTE3,
+	GAUDI2_ETF_DCORE0_MME_SBTE4,
+	GAUDI2_ETF_DCORE0_MME_ACC,
+	GAUDI2_ETF_DCORE0_SM,
+	GAUDI2_ETF_DCORE0_EDMA0_CS,
+	GAUDI2_ETF_DCORE0_EDMA1_CS,
+	GAUDI2_ETF_DCORE0_VDEC0_CS,
+	GAUDI2_ETF_DCORE0_VDEC1_CS,
+	GAUDI2_ETF_DCORE1_HMMU0_CS,
+	GAUDI2_ETF_DCORE1_HMMU1_CS,
+	GAUDI2_ETF_DCORE1_HMMU2_CS,
+	GAUDI2_ETF_DCORE1_HMMU3_CS,
+	GAUDI2_ETF_DCORE1_MME_CTRL,
+	GAUDI2_ETF_DCORE1_MME_SBTE0,
+	GAUDI2_ETF_DCORE1_MME_SBTE1,
+	GAUDI2_ETF_DCORE1_MME_SBTE2,
+	GAUDI2_ETF_DCORE1_MME_SBTE3,
+	GAUDI2_ETF_DCORE1_MME_SBTE4,
+	GAUDI2_ETF_DCORE1_MME_ACC,
+	GAUDI2_ETF_DCORE1_SM,
+	GAUDI2_ETF_DCORE1_EDMA0_CS,
+	GAUDI2_ETF_DCORE1_EDMA1_CS,
+	GAUDI2_ETF_DCORE1_VDEC0_CS,
+	GAUDI2_ETF_DCORE1_VDEC1_CS,
+	GAUDI2_ETF_DCORE2_HMMU0_CS,
+	GAUDI2_ETF_DCORE2_HMMU1_CS,
+	GAUDI2_ETF_DCORE2_HMMU2_CS,
+	GAUDI2_ETF_DCORE2_HMMU3_CS,
+	GAUDI2_ETF_DCORE2_MME_CTRL,
+	GAUDI2_ETF_DCORE2_MME_SBTE0,
+	GAUDI2_ETF_DCORE2_MME_SBTE1,
+	GAUDI2_ETF_DCORE2_MME_SBTE2,
+	GAUDI2_ETF_DCORE2_MME_SBTE3,
+	GAUDI2_ETF_DCORE2_MME_SBTE4,
+	GAUDI2_ETF_DCORE2_MME_ACC,
+	GAUDI2_ETF_DCORE2_SM,
+	GAUDI2_ETF_DCORE2_EDMA0_CS,
+	GAUDI2_ETF_DCORE2_EDMA1_CS,
+	GAUDI2_ETF_DCORE2_VDEC0_CS,
+	GAUDI2_ETF_DCORE2_VDEC1_CS,
+	GAUDI2_ETF_DCORE3_HMMU0_CS,
+	GAUDI2_ETF_DCORE3_HMMU1_CS,
+	GAUDI2_ETF_DCORE3_HMMU2_CS,
+	GAUDI2_ETF_DCORE3_HMMU3_CS,
+	GAUDI2_ETF_DCORE3_MME_CTRL,
+	GAUDI2_ETF_DCORE3_MME_SBTE0,
+	GAUDI2_ETF_DCORE3_MME_SBTE1,
+	GAUDI2_ETF_DCORE3_MME_SBTE2,
+	GAUDI2_ETF_DCORE3_MME_SBTE3,
+	GAUDI2_ETF_DCORE3_MME_SBTE4,
+	GAUDI2_ETF_DCORE3_MME_ACC,
+	GAUDI2_ETF_DCORE3_SM,
+	GAUDI2_ETF_DCORE3_EDMA0_CS,
+	GAUDI2_ETF_DCORE3_EDMA1_CS,
+	GAUDI2_ETF_DCORE3_VDEC0_CS,
+	GAUDI2_ETF_DCORE3_VDEC1_CS,
+	GAUDI2_ETF_PCIE,
+	GAUDI2_ETF_PSOC,
+	GAUDI2_ETF_PSOC_ARC0_CS,
+	GAUDI2_ETF_PSOC_ARC1_CS,
+	GAUDI2_ETF_PDMA0_CS,
+	GAUDI2_ETF_PDMA1_CS,
+	GAUDI2_ETF_CPU_0,
+	GAUDI2_ETF_CPU_1,
+	GAUDI2_ETF_CPU_TRACE,
+	GAUDI2_ETF_PMMU_CS,
+	GAUDI2_ETF_ROT0_CS,
+	GAUDI2_ETF_ROT1_CS,
+	GAUDI2_ETF_ARC_FARM_CS,
+	GAUDI2_ETF_KDMA_CS,
+	GAUDI2_ETF_PCIE_VDEC0_CS,
+	GAUDI2_ETF_PCIE_VDEC1_CS,
+	GAUDI2_ETF_HBM0_MC0_CS,
+	GAUDI2_ETF_HBM0_MC1_CS,
+	GAUDI2_ETF_HBM1_MC0_CS,
+	GAUDI2_ETF_HBM1_MC1_CS,
+	GAUDI2_ETF_HBM2_MC0_CS,
+	GAUDI2_ETF_HBM2_MC1_CS,
+	GAUDI2_ETF_HBM3_MC0_CS,
+	GAUDI2_ETF_HBM3_MC1_CS,
+	GAUDI2_ETF_HBM4_MC0_CS,
+	GAUDI2_ETF_HBM4_MC1_CS,
+	GAUDI2_ETF_HBM5_MC0_CS,
+	GAUDI2_ETF_HBM5_MC1_CS,
+	GAUDI2_ETF_NIC0_DBG_0,
+	GAUDI2_ETF_NIC0_DBG_1,
+	GAUDI2_ETF_NIC1_DBG_0,
+	GAUDI2_ETF_NIC1_DBG_1,
+	GAUDI2_ETF_NIC2_DBG_0,
+	GAUDI2_ETF_NIC2_DBG_1,
+	GAUDI2_ETF_NIC3_DBG_0,
+	GAUDI2_ETF_NIC3_DBG_1,
+	GAUDI2_ETF_NIC4_DBG_0,
+	GAUDI2_ETF_NIC4_DBG_1,
+	GAUDI2_ETF_NIC5_DBG_0,
+	GAUDI2_ETF_NIC5_DBG_1,
+	GAUDI2_ETF_NIC6_DBG_0,
+	GAUDI2_ETF_NIC6_DBG_1,
+	GAUDI2_ETF_NIC7_DBG_0,
+	GAUDI2_ETF_NIC7_DBG_1,
+	GAUDI2_ETF_NIC8_DBG_0,
+	GAUDI2_ETF_NIC8_DBG_1,
+	GAUDI2_ETF_NIC9_DBG_0,
+	GAUDI2_ETF_NIC9_DBG_1,
+	GAUDI2_ETF_NIC10_DBG_0,
+	GAUDI2_ETF_NIC10_DBG_1,
+	GAUDI2_ETF_NIC11_DBG_0,
+	GAUDI2_ETF_NIC11_DBG_1,
+	GAUDI2_ETF_LAST = GAUDI2_ETF_NIC11_DBG_1
+};
+
+enum gaudi2_debug_funnel_regs_index {
+	GAUDI2_FUNNEL_FIRST = 0,
+	GAUDI2_FUNNEL_DCORE0_TPC0_EML = GAUDI2_FUNNEL_FIRST,
+	GAUDI2_FUNNEL_DCORE0_TPC1_EML,
+	GAUDI2_FUNNEL_DCORE0_TPC2_EML,
+	GAUDI2_FUNNEL_DCORE0_TPC3_EML,
+	GAUDI2_FUNNEL_DCORE0_TPC4_EML,
+	GAUDI2_FUNNEL_DCORE0_TPC5_EML,
+	GAUDI2_FUNNEL_DCORE0_TPC6_EML,
+	GAUDI2_FUNNEL_DCORE1_TPC0_EML,
+	GAUDI2_FUNNEL_DCORE1_TPC1_EML,
+	GAUDI2_FUNNEL_DCORE1_TPC2_EML,
+	GAUDI2_FUNNEL_DCORE1_TPC3_EML,
+	GAUDI2_FUNNEL_DCORE1_TPC4_EML,
+	GAUDI2_FUNNEL_DCORE1_TPC5_EML,
+	GAUDI2_FUNNEL_DCORE2_TPC0_EML,
+	GAUDI2_FUNNEL_DCORE2_TPC1_EML,
+	GAUDI2_FUNNEL_DCORE2_TPC2_EML,
+	GAUDI2_FUNNEL_DCORE2_TPC3_EML,
+	GAUDI2_FUNNEL_DCORE2_TPC4_EML,
+	GAUDI2_FUNNEL_DCORE2_TPC5_EML,
+	GAUDI2_FUNNEL_DCORE3_TPC0_EML,
+	GAUDI2_FUNNEL_DCORE3_TPC1_EML,
+	GAUDI2_FUNNEL_DCORE3_TPC2_EML,
+	GAUDI2_FUNNEL_DCORE3_TPC3_EML,
+	GAUDI2_FUNNEL_DCORE3_TPC4_EML,
+	GAUDI2_FUNNEL_DCORE3_TPC5_EML,
+	GAUDI2_FUNNEL_DCORE0_XFT,
+	GAUDI2_FUNNEL_DCORE0_TFT0,
+	GAUDI2_FUNNEL_DCORE0_TFT1,
+	GAUDI2_FUNNEL_DCORE0_TFT2,
+	GAUDI2_FUNNEL_DCORE0_RTR0,
+	GAUDI2_FUNNEL_DCORE0_RTR1,
+	GAUDI2_FUNNEL_DCORE0_RTR2,
+	GAUDI2_FUNNEL_DCORE0_RTR3,
+	GAUDI2_FUNNEL_DCORE0_RTR4,
+	GAUDI2_FUNNEL_DCORE0_MIF0,
+	GAUDI2_FUNNEL_DCORE0_RTR5,
+	GAUDI2_FUNNEL_DCORE0_MIF1,
+	GAUDI2_FUNNEL_DCORE0_RTR6,
+	GAUDI2_FUNNEL_DCORE0_MIF2,
+	GAUDI2_FUNNEL_DCORE0_RTR7,
+	GAUDI2_FUNNEL_DCORE0_MIF3,
+	GAUDI2_FUNNEL_DCORE1_XFT,
+	GAUDI2_FUNNEL_DCORE1_TFT0,
+	GAUDI2_FUNNEL_DCORE1_TFT1,
+	GAUDI2_FUNNEL_DCORE1_TFT2,
+	GAUDI2_FUNNEL_DCORE1_RTR0,
+	GAUDI2_FUNNEL_DCORE1_MIF0,
+	GAUDI2_FUNNEL_DCORE1_RTR1,
+	GAUDI2_FUNNEL_DCORE1_MIF1,
+	GAUDI2_FUNNEL_DCORE1_RTR2,
+	GAUDI2_FUNNEL_DCORE1_MIF2,
+	GAUDI2_FUNNEL_DCORE1_RTR3,
+	GAUDI2_FUNNEL_DCORE1_MIF3,
+	GAUDI2_FUNNEL_DCORE1_RTR4,
+	GAUDI2_FUNNEL_DCORE1_RTR5,
+	GAUDI2_FUNNEL_DCORE1_RTR6,
+	GAUDI2_FUNNEL_DCORE1_RTR7,
+	GAUDI2_FUNNEL_DCORE2_XFT,
+	GAUDI2_FUNNEL_DCORE2_TFT0,
+	GAUDI2_FUNNEL_DCORE2_TFT1,
+	GAUDI2_FUNNEL_DCORE2_TFT2,
+	GAUDI2_FUNNEL_DCORE2_RTR0,
+	GAUDI2_FUNNEL_DCORE2_RTR1,
+	GAUDI2_FUNNEL_DCORE2_RTR2,
+	GAUDI2_FUNNEL_DCORE2_RTR3,
+	GAUDI2_FUNNEL_DCORE2_RTR4,
+	GAUDI2_FUNNEL_DCORE2_MIF0,
+	GAUDI2_FUNNEL_DCORE2_RTR5,
+	GAUDI2_FUNNEL_DCORE2_MIF1,
+	GAUDI2_FUNNEL_DCORE2_RTR6,
+	GAUDI2_FUNNEL_DCORE2_MIF2,
+	GAUDI2_FUNNEL_DCORE2_RTR7,
+	GAUDI2_FUNNEL_DCORE2_MIF3,
+	GAUDI2_FUNNEL_DCORE3_XFT,
+	GAUDI2_FUNNEL_DCORE3_TFT0,
+	GAUDI2_FUNNEL_DCORE3_TFT1,
+	GAUDI2_FUNNEL_DCORE3_TFT2,
+	GAUDI2_FUNNEL_DCORE3_RTR0,
+	GAUDI2_FUNNEL_DCORE3_MIF0,
+	GAUDI2_FUNNEL_DCORE3_RTR1,
+	GAUDI2_FUNNEL_DCORE3_MIF1,
+	GAUDI2_FUNNEL_DCORE3_RTR2,
+	GAUDI2_FUNNEL_DCORE3_MIF2,
+	GAUDI2_FUNNEL_DCORE3_RTR3,
+	GAUDI2_FUNNEL_DCORE3_MIF3,
+	GAUDI2_FUNNEL_DCORE3_RTR4,
+	GAUDI2_FUNNEL_DCORE3_RTR5,
+	GAUDI2_FUNNEL_DCORE3_RTR6,
+	GAUDI2_FUNNEL_DCORE3_RTR7,
+	GAUDI2_FUNNEL_PSOC,
+	GAUDI2_FUNNEL_PSOC_ARC0,
+	GAUDI2_FUNNEL_PSOC_ARC1,
+	GAUDI2_FUNNEL_XDMA,
+	GAUDI2_FUNNEL_CPU,
+	GAUDI2_FUNNEL_PMMU,
+	GAUDI2_FUNNEL_PMMU_DEC,
+	GAUDI2_FUNNEL_DCORE0_XBAR_MID,
+	GAUDI2_FUNNEL_DCORE0_XBAR_EDGE,
+	GAUDI2_FUNNEL_DCORE1_XBAR_MID,
+	GAUDI2_FUNNEL_DCORE1_XBAR_EDGE,
+	GAUDI2_FUNNEL_DCORE2_XBAR_MID,
+	GAUDI2_FUNNEL_DCORE2_XBAR_EDGE,
+	GAUDI2_FUNNEL_DCORE3_XBAR_MID,
+	GAUDI2_FUNNEL_DCORE3_XBAR_EDGE,
+	GAUDI2_FUNNEL_ARC_FARM,
+	GAUDI2_FUNNEL_HBM0_MC0,
+	GAUDI2_FUNNEL_HBM0_MC1,
+	GAUDI2_FUNNEL_HBM1_MC0,
+	GAUDI2_FUNNEL_HBM1_MC1,
+	GAUDI2_FUNNEL_HBM2_MC0,
+	GAUDI2_FUNNEL_HBM2_MC1,
+	GAUDI2_FUNNEL_HBM3_MC0,
+	GAUDI2_FUNNEL_HBM3_MC1,
+	GAUDI2_FUNNEL_HBM4_MC0,
+	GAUDI2_FUNNEL_HBM4_MC1,
+	GAUDI2_FUNNEL_HBM5_MC0,
+	GAUDI2_FUNNEL_HBM5_MC1,
+	GAUDI2_FUNNEL_NIC0_DBG_TX,
+	GAUDI2_FUNNEL_NIC0_DBG_NCH,
+	GAUDI2_FUNNEL_NIC1_DBG_TX,
+	GAUDI2_FUNNEL_NIC1_DBG_NCH,
+	GAUDI2_FUNNEL_NIC2_DBG_TX,
+	GAUDI2_FUNNEL_NIC2_DBG_NCH,
+	GAUDI2_FUNNEL_NIC3_DBG_TX,
+	GAUDI2_FUNNEL_NIC3_DBG_NCH,
+	GAUDI2_FUNNEL_NIC4_DBG_TX,
+	GAUDI2_FUNNEL_NIC4_DBG_NCH,
+	GAUDI2_FUNNEL_NIC5_DBG_TX,
+	GAUDI2_FUNNEL_NIC5_DBG_NCH,
+	GAUDI2_FUNNEL_NIC6_DBG_TX,
+	GAUDI2_FUNNEL_NIC6_DBG_NCH,
+	GAUDI2_FUNNEL_NIC7_DBG_TX,
+	GAUDI2_FUNNEL_NIC7_DBG_NCH,
+	GAUDI2_FUNNEL_NIC8_DBG_TX,
+	GAUDI2_FUNNEL_NIC8_DBG_NCH,
+	GAUDI2_FUNNEL_NIC9_DBG_TX,
+	GAUDI2_FUNNEL_NIC9_DBG_NCH,
+	GAUDI2_FUNNEL_NIC10_DBG_TX,
+	GAUDI2_FUNNEL_NIC10_DBG_NCH,
+	GAUDI2_FUNNEL_NIC11_DBG_TX,
+	GAUDI2_FUNNEL_NIC11_DBG_NCH,
+	GAUDI2_FUNNEL_LAST = GAUDI2_FUNNEL_NIC11_DBG_NCH
+};
+
+enum gaudi2_debug_bmon_regs_index {
+	GAUDI2_BMON_FIRST = 0,
+	GAUDI2_BMON_DCORE0_TPC0_EML_0 = GAUDI2_BMON_FIRST,
+	GAUDI2_BMON_DCORE0_TPC0_EML_1,
+	GAUDI2_BMON_DCORE0_TPC0_EML_2,
+	GAUDI2_BMON_DCORE0_TPC0_EML_3,
+	GAUDI2_BMON_DCORE0_TPC1_EML_0,
+	GAUDI2_BMON_DCORE0_TPC1_EML_1,
+	GAUDI2_BMON_DCORE0_TPC1_EML_2,
+	GAUDI2_BMON_DCORE0_TPC1_EML_3,
+	GAUDI2_BMON_DCORE0_TPC2_EML_0,
+	GAUDI2_BMON_DCORE0_TPC2_EML_1,
+	GAUDI2_BMON_DCORE0_TPC2_EML_2,
+	GAUDI2_BMON_DCORE0_TPC2_EML_3,
+	GAUDI2_BMON_DCORE0_TPC3_EML_0,
+	GAUDI2_BMON_DCORE0_TPC3_EML_1,
+	GAUDI2_BMON_DCORE0_TPC3_EML_2,
+	GAUDI2_BMON_DCORE0_TPC3_EML_3,
+	GAUDI2_BMON_DCORE0_TPC4_EML_0,
+	GAUDI2_BMON_DCORE0_TPC4_EML_1,
+	GAUDI2_BMON_DCORE0_TPC4_EML_2,
+	GAUDI2_BMON_DCORE0_TPC4_EML_3,
+	GAUDI2_BMON_DCORE0_TPC5_EML_0,
+	GAUDI2_BMON_DCORE0_TPC5_EML_1,
+	GAUDI2_BMON_DCORE0_TPC5_EML_2,
+	GAUDI2_BMON_DCORE0_TPC5_EML_3,
+	GAUDI2_BMON_DCORE0_TPC6_EML_0,
+	GAUDI2_BMON_DCORE0_TPC6_EML_1,
+	GAUDI2_BMON_DCORE0_TPC6_EML_2,
+	GAUDI2_BMON_DCORE0_TPC6_EML_3,
+	GAUDI2_BMON_DCORE1_TPC0_EML_0,
+	GAUDI2_BMON_DCORE1_TPC0_EML_1,
+	GAUDI2_BMON_DCORE1_TPC0_EML_2,
+	GAUDI2_BMON_DCORE1_TPC0_EML_3,
+	GAUDI2_BMON_DCORE1_TPC1_EML_0,
+	GAUDI2_BMON_DCORE1_TPC1_EML_1,
+	GAUDI2_BMON_DCORE1_TPC1_EML_2,
+	GAUDI2_BMON_DCORE1_TPC1_EML_3,
+	GAUDI2_BMON_DCORE1_TPC2_EML_0,
+	GAUDI2_BMON_DCORE1_TPC2_EML_1,
+	GAUDI2_BMON_DCORE1_TPC2_EML_2,
+	GAUDI2_BMON_DCORE1_TPC2_EML_3,
+	GAUDI2_BMON_DCORE1_TPC3_EML_0,
+	GAUDI2_BMON_DCORE1_TPC3_EML_1,
+	GAUDI2_BMON_DCORE1_TPC3_EML_2,
+	GAUDI2_BMON_DCORE1_TPC3_EML_3,
+	GAUDI2_BMON_DCORE1_TPC4_EML_0,
+	GAUDI2_BMON_DCORE1_TPC4_EML_1,
+	GAUDI2_BMON_DCORE1_TPC4_EML_2,
+	GAUDI2_BMON_DCORE1_TPC4_EML_3,
+	GAUDI2_BMON_DCORE1_TPC5_EML_0,
+	GAUDI2_BMON_DCORE1_TPC5_EML_1,
+	GAUDI2_BMON_DCORE1_TPC5_EML_2,
+	GAUDI2_BMON_DCORE1_TPC5_EML_3,
+	GAUDI2_BMON_DCORE2_TPC0_EML_0,
+	GAUDI2_BMON_DCORE2_TPC0_EML_1,
+	GAUDI2_BMON_DCORE2_TPC0_EML_2,
+	GAUDI2_BMON_DCORE2_TPC0_EML_3,
+	GAUDI2_BMON_DCORE2_TPC1_EML_0,
+	GAUDI2_BMON_DCORE2_TPC1_EML_1,
+	GAUDI2_BMON_DCORE2_TPC1_EML_2,
+	GAUDI2_BMON_DCORE2_TPC1_EML_3,
+	GAUDI2_BMON_DCORE2_TPC2_EML_0,
+	GAUDI2_BMON_DCORE2_TPC2_EML_1,
+	GAUDI2_BMON_DCORE2_TPC2_EML_2,
+	GAUDI2_BMON_DCORE2_TPC2_EML_3,
+	GAUDI2_BMON_DCORE2_TPC3_EML_0,
+	GAUDI2_BMON_DCORE2_TPC3_EML_1,
+	GAUDI2_BMON_DCORE2_TPC3_EML_2,
+	GAUDI2_BMON_DCORE2_TPC3_EML_3,
+	GAUDI2_BMON_DCORE2_TPC4_EML_0,
+	GAUDI2_BMON_DCORE2_TPC4_EML_1,
+	GAUDI2_BMON_DCORE2_TPC4_EML_2,
+	GAUDI2_BMON_DCORE2_TPC4_EML_3,
+	GAUDI2_BMON_DCORE2_TPC5_EML_0,
+	GAUDI2_BMON_DCORE2_TPC5_EML_1,
+	GAUDI2_BMON_DCORE2_TPC5_EML_2,
+	GAUDI2_BMON_DCORE2_TPC5_EML_3,
+	GAUDI2_BMON_DCORE3_TPC0_EML_0,
+	GAUDI2_BMON_DCORE3_TPC0_EML_1,
+	GAUDI2_BMON_DCORE3_TPC0_EML_2,
+	GAUDI2_BMON_DCORE3_TPC0_EML_3,
+	GAUDI2_BMON_DCORE3_TPC1_EML_0,
+	GAUDI2_BMON_DCORE3_TPC1_EML_1,
+	GAUDI2_BMON_DCORE3_TPC1_EML_2,
+	GAUDI2_BMON_DCORE3_TPC1_EML_3,
+	GAUDI2_BMON_DCORE3_TPC2_EML_0,
+	GAUDI2_BMON_DCORE3_TPC2_EML_1,
+	GAUDI2_BMON_DCORE3_TPC2_EML_2,
+	GAUDI2_BMON_DCORE3_TPC2_EML_3,
+	GAUDI2_BMON_DCORE3_TPC3_EML_0,
+	GAUDI2_BMON_DCORE3_TPC3_EML_1,
+	GAUDI2_BMON_DCORE3_TPC3_EML_2,
+	GAUDI2_BMON_DCORE3_TPC3_EML_3,
+	GAUDI2_BMON_DCORE3_TPC4_EML_0,
+	GAUDI2_BMON_DCORE3_TPC4_EML_1,
+	GAUDI2_BMON_DCORE3_TPC4_EML_2,
+	GAUDI2_BMON_DCORE3_TPC4_EML_3,
+	GAUDI2_BMON_DCORE3_TPC5_EML_0,
+	GAUDI2_BMON_DCORE3_TPC5_EML_1,
+	GAUDI2_BMON_DCORE3_TPC5_EML_2,
+	GAUDI2_BMON_DCORE3_TPC5_EML_3,
+	GAUDI2_BMON_DCORE0_HMMU0_0,
+	GAUDI2_BMON_DCORE0_HMMU0_1,
+	GAUDI2_BMON_DCORE0_HMMU0_3,
+	GAUDI2_BMON_DCORE0_HMMU0_2,
+	GAUDI2_BMON_DCORE0_HMMU0_4,
+	GAUDI2_BMON_DCORE0_HMMU1_0,
+	GAUDI2_BMON_DCORE0_HMMU1_1,
+	GAUDI2_BMON_DCORE0_HMMU1_3,
+	GAUDI2_BMON_DCORE0_HMMU1_2,
+	GAUDI2_BMON_DCORE0_HMMU1_4,
+	GAUDI2_BMON_DCORE0_HMMU2_0,
+	GAUDI2_BMON_DCORE0_HMMU2_1,
+	GAUDI2_BMON_DCORE0_HMMU2_3,
+	GAUDI2_BMON_DCORE0_HMMU2_2,
+	GAUDI2_BMON_DCORE0_HMMU2_4,
+	GAUDI2_BMON_DCORE0_HMMU3_0,
+	GAUDI2_BMON_DCORE0_HMMU3_1,
+	GAUDI2_BMON_DCORE0_HMMU3_3,
+	GAUDI2_BMON_DCORE0_HMMU3_2,
+	GAUDI2_BMON_DCORE0_HMMU3_4,
+	GAUDI2_BMON_DCORE0_MME_CTRL_0,
+	GAUDI2_BMON_DCORE0_MME_CTRL_1,
+	GAUDI2_BMON_DCORE0_MME_CTRL_2,
+	GAUDI2_BMON_DCORE0_MME_CTRL_3,
+	GAUDI2_BMON_DCORE0_MME_SBTE0_0,
+	GAUDI2_BMON_DCORE0_MME_SBTE1_0,
+	GAUDI2_BMON_DCORE0_MME_SBTE2_0,
+	GAUDI2_BMON_DCORE0_MME_SBTE3_0,
+	GAUDI2_BMON_DCORE0_MME_SBTE4_0,
+	GAUDI2_BMON_DCORE0_MME_ACC_0,
+	GAUDI2_BMON_DCORE0_MME_ACC_1,
+	GAUDI2_BMON_DCORE0_SM,
+	GAUDI2_BMON_DCORE0_SM_1,
+	GAUDI2_BMON_DCORE0_EDMA0_0,
+	GAUDI2_BMON_DCORE0_EDMA0_1,
+	GAUDI2_BMON_DCORE0_EDMA1_0,
+	GAUDI2_BMON_DCORE0_EDMA1_1,
+	GAUDI2_BMON_DCORE0_VDEC0_0,
+	GAUDI2_BMON_DCORE0_VDEC0_1,
+	GAUDI2_BMON_DCORE0_VDEC0_2,
+	GAUDI2_BMON_DCORE0_VDEC1_0,
+	GAUDI2_BMON_DCORE0_VDEC1_1,
+	GAUDI2_BMON_DCORE0_VDEC1_2,
+	GAUDI2_BMON_DCORE1_HMMU0_0,
+	GAUDI2_BMON_DCORE1_HMMU0_1,
+	GAUDI2_BMON_DCORE1_HMMU0_3,
+	GAUDI2_BMON_DCORE1_HMMU0_2,
+	GAUDI2_BMON_DCORE1_HMMU0_4,
+	GAUDI2_BMON_DCORE1_HMMU1_0,
+	GAUDI2_BMON_DCORE1_HMMU1_1,
+	GAUDI2_BMON_DCORE1_HMMU1_3,
+	GAUDI2_BMON_DCORE1_HMMU1_2,
+	GAUDI2_BMON_DCORE1_HMMU1_4,
+	GAUDI2_BMON_DCORE1_HMMU2_0,
+	GAUDI2_BMON_DCORE1_HMMU2_1,
+	GAUDI2_BMON_DCORE1_HMMU2_3,
+	GAUDI2_BMON_DCORE1_HMMU2_2,
+	GAUDI2_BMON_DCORE1_HMMU2_4,
+	GAUDI2_BMON_DCORE1_HMMU3_0,
+	GAUDI2_BMON_DCORE1_HMMU3_1,
+	GAUDI2_BMON_DCORE1_HMMU3_3,
+	GAUDI2_BMON_DCORE1_HMMU3_2,
+	GAUDI2_BMON_DCORE1_HMMU3_4,
+	GAUDI2_BMON_DCORE1_MME_CTRL_0,
+	GAUDI2_BMON_DCORE1_MME_CTRL_1,
+	GAUDI2_BMON_DCORE1_MME_CTRL_2,
+	GAUDI2_BMON_DCORE1_MME_CTRL_3,
+	GAUDI2_BMON_DCORE1_MME_SBTE0_0,
+	GAUDI2_BMON_DCORE1_MME_SBTE1_0,
+	GAUDI2_BMON_DCORE1_MME_SBTE2_0,
+	GAUDI2_BMON_DCORE1_MME_SBTE3_0,
+	GAUDI2_BMON_DCORE1_MME_SBTE4_0,
+	GAUDI2_BMON_DCORE1_MME_ACC_0,
+	GAUDI2_BMON_DCORE1_MME_ACC_1,
+	GAUDI2_BMON_DCORE1_SM,
+	GAUDI2_BMON_DCORE1_SM_1,
+	GAUDI2_BMON_DCORE1_EDMA0_0,
+	GAUDI2_BMON_DCORE1_EDMA0_1,
+	GAUDI2_BMON_DCORE1_EDMA1_0,
+	GAUDI2_BMON_DCORE1_EDMA1_1,
+	GAUDI2_BMON_DCORE1_VDEC0_0,
+	GAUDI2_BMON_DCORE1_VDEC0_1,
+	GAUDI2_BMON_DCORE1_VDEC0_2,
+	GAUDI2_BMON_DCORE1_VDEC1_0,
+	GAUDI2_BMON_DCORE1_VDEC1_1,
+	GAUDI2_BMON_DCORE1_VDEC1_2,
+	GAUDI2_BMON_DCORE2_HMMU0_0,
+	GAUDI2_BMON_DCORE2_HMMU0_1,
+	GAUDI2_BMON_DCORE2_HMMU0_3,
+	GAUDI2_BMON_DCORE2_HMMU0_2,
+	GAUDI2_BMON_DCORE2_HMMU0_4,
+	GAUDI2_BMON_DCORE2_HMMU1_0,
+	GAUDI2_BMON_DCORE2_HMMU1_1,
+	GAUDI2_BMON_DCORE2_HMMU1_3,
+	GAUDI2_BMON_DCORE2_HMMU1_2,
+	GAUDI2_BMON_DCORE2_HMMU1_4,
+	GAUDI2_BMON_DCORE2_HMMU2_0,
+	GAUDI2_BMON_DCORE2_HMMU2_1,
+	GAUDI2_BMON_DCORE2_HMMU2_3,
+	GAUDI2_BMON_DCORE2_HMMU2_2,
+	GAUDI2_BMON_DCORE2_HMMU2_4,
+	GAUDI2_BMON_DCORE2_HMMU3_0,
+	GAUDI2_BMON_DCORE2_HMMU3_1,
+	GAUDI2_BMON_DCORE2_HMMU3_3,
+	GAUDI2_BMON_DCORE2_HMMU3_2,
+	GAUDI2_BMON_DCORE2_HMMU3_4,
+	GAUDI2_BMON_DCORE2_MME_CTRL_0,
+	GAUDI2_BMON_DCORE2_MME_CTRL_1,
+	GAUDI2_BMON_DCORE2_MME_CTRL_2,
+	GAUDI2_BMON_DCORE2_MME_CTRL_3,
+	GAUDI2_BMON_DCORE2_MME_SBTE0_0,
+	GAUDI2_BMON_DCORE2_MME_SBTE1_0,
+	GAUDI2_BMON_DCORE2_MME_SBTE2_0,
+	GAUDI2_BMON_DCORE2_MME_SBTE3_0,
+	GAUDI2_BMON_DCORE2_MME_SBTE4_0,
+	GAUDI2_BMON_DCORE2_MME_ACC_0,
+	GAUDI2_BMON_DCORE2_MME_ACC_1,
+	GAUDI2_BMON_DCORE2_SM,
+	GAUDI2_BMON_DCORE2_SM_1,
+	GAUDI2_BMON_DCORE2_EDMA0_0,
+	GAUDI2_BMON_DCORE2_EDMA0_1,
+	GAUDI2_BMON_DCORE2_EDMA1_0,
+	GAUDI2_BMON_DCORE2_EDMA1_1,
+	GAUDI2_BMON_DCORE2_VDEC0_0,
+	GAUDI2_BMON_DCORE2_VDEC0_1,
+	GAUDI2_BMON_DCORE2_VDEC0_2,
+	GAUDI2_BMON_DCORE2_VDEC1_0,
+	GAUDI2_BMON_DCORE2_VDEC1_1,
+	GAUDI2_BMON_DCORE2_VDEC1_2,
+	GAUDI2_BMON_DCORE3_HMMU0_0,
+	GAUDI2_BMON_DCORE3_HMMU0_1,
+	GAUDI2_BMON_DCORE3_HMMU0_3,
+	GAUDI2_BMON_DCORE3_HMMU0_2,
+	GAUDI2_BMON_DCORE3_HMMU0_4,
+	GAUDI2_BMON_DCORE3_HMMU1_0,
+	GAUDI2_BMON_DCORE3_HMMU1_1,
+	GAUDI2_BMON_DCORE3_HMMU1_3,
+	GAUDI2_BMON_DCORE3_HMMU1_2,
+	GAUDI2_BMON_DCORE3_HMMU1_4,
+	GAUDI2_BMON_DCORE3_HMMU2_0,
+	GAUDI2_BMON_DCORE3_HMMU2_1,
+	GAUDI2_BMON_DCORE3_HMMU2_3,
+	GAUDI2_BMON_DCORE3_HMMU2_2,
+	GAUDI2_BMON_DCORE3_HMMU2_4,
+	GAUDI2_BMON_DCORE3_HMMU3_0,
+	GAUDI2_BMON_DCORE3_HMMU3_1,
+	GAUDI2_BMON_DCORE3_HMMU3_3,
+	GAUDI2_BMON_DCORE3_HMMU3_2,
+	GAUDI2_BMON_DCORE3_HMMU3_4,
+	GAUDI2_BMON_DCORE3_MME_CTRL_0,
+	GAUDI2_BMON_DCORE3_MME_CTRL_1,
+	GAUDI2_BMON_DCORE3_MME_CTRL_2,
+	GAUDI2_BMON_DCORE3_MME_CTRL_3,
+	GAUDI2_BMON_DCORE3_MME_SBTE0_0,
+	GAUDI2_BMON_DCORE3_MME_SBTE1_0,
+	GAUDI2_BMON_DCORE3_MME_SBTE2_0,
+	GAUDI2_BMON_DCORE3_MME_SBTE3_0,
+	GAUDI2_BMON_DCORE3_MME_SBTE4_0,
+	GAUDI2_BMON_DCORE3_MME_ACC_0,
+	GAUDI2_BMON_DCORE3_MME_ACC_1,
+	GAUDI2_BMON_DCORE3_SM,
+	GAUDI2_BMON_DCORE3_SM_1,
+	GAUDI2_BMON_DCORE3_EDMA0_0,
+	GAUDI2_BMON_DCORE3_EDMA0_1,
+	GAUDI2_BMON_DCORE3_EDMA1_0,
+	GAUDI2_BMON_DCORE3_EDMA1_1,
+	GAUDI2_BMON_DCORE3_VDEC0_0,
+	GAUDI2_BMON_DCORE3_VDEC0_1,
+	GAUDI2_BMON_DCORE3_VDEC0_2,
+	GAUDI2_BMON_DCORE3_VDEC1_0,
+	GAUDI2_BMON_DCORE3_VDEC1_1,
+	GAUDI2_BMON_DCORE3_VDEC1_2,
+	GAUDI2_BMON_PCIE_MSTR_WR,
+	GAUDI2_BMON_PCIE_MSTR_RD,
+	GAUDI2_BMON_PCIE_SLV_WR,
+	GAUDI2_BMON_PCIE_SLV_RD,
+	GAUDI2_BMON_PSOC_ARC0_0,
+	GAUDI2_BMON_PSOC_ARC0_1,
+	GAUDI2_BMON_PSOC_ARC1_0,
+	GAUDI2_BMON_PSOC_ARC1_1,
+	GAUDI2_BMON_PDMA0_0,
+	GAUDI2_BMON_PDMA0_1,
+	GAUDI2_BMON_PDMA1_0,
+	GAUDI2_BMON_PDMA1_1,
+	GAUDI2_BMON_CPU_WR,
+	GAUDI2_BMON_CPU_RD,
+	GAUDI2_BMON_PMMU_0,
+	GAUDI2_BMON_PMMU_1,
+	GAUDI2_BMON_PMMU_2,
+	GAUDI2_BMON_PMMU_3,
+	GAUDI2_BMON_PMMU_4,
+	GAUDI2_BMON_ROT0_0,
+	GAUDI2_BMON_ROT0_1,
+	GAUDI2_BMON_ROT0_2,
+	GAUDI2_BMON_ROT0_3,
+	GAUDI2_BMON_ROT1_0,
+	GAUDI2_BMON_ROT1_1,
+	GAUDI2_BMON_ROT1_2,
+	GAUDI2_BMON_ROT1_3,
+	GAUDI2_BMON_ARC_FARM_0,
+	GAUDI2_BMON_ARC_FARM_1,
+	GAUDI2_BMON_ARC_FARM_2,
+	GAUDI2_BMON_ARC_FARM_3,
+	GAUDI2_BMON_KDMA_0,
+	GAUDI2_BMON_KDMA_1,
+	GAUDI2_BMON_KDMA_2,
+	GAUDI2_BMON_KDMA_3,
+	GAUDI2_BMON_PCIE_VDEC0_0,
+	GAUDI2_BMON_PCIE_VDEC0_1,
+	GAUDI2_BMON_PCIE_VDEC0_2,
+	GAUDI2_BMON_PCIE_VDEC1_0,
+	GAUDI2_BMON_PCIE_VDEC1_1,
+	GAUDI2_BMON_PCIE_VDEC1_2,
+	GAUDI2_BMON_NIC0_DBG_0_0,
+	GAUDI2_BMON_NIC0_DBG_1_0,
+	GAUDI2_BMON_NIC0_DBG_2_0,
+	GAUDI2_BMON_NIC0_DBG_0_1,
+	GAUDI2_BMON_NIC0_DBG_1_1,
+	GAUDI2_BMON_NIC0_DBG_2_1,
+	GAUDI2_BMON_NIC1_DBG_0_0,
+	GAUDI2_BMON_NIC1_DBG_1_0,
+	GAUDI2_BMON_NIC1_DBG_2_0,
+	GAUDI2_BMON_NIC1_DBG_0_1,
+	GAUDI2_BMON_NIC1_DBG_1_1,
+	GAUDI2_BMON_NIC1_DBG_2_1,
+	GAUDI2_BMON_NIC2_DBG_0_0,
+	GAUDI2_BMON_NIC2_DBG_1_0,
+	GAUDI2_BMON_NIC2_DBG_2_0,
+	GAUDI2_BMON_NIC2_DBG_0_1,
+	GAUDI2_BMON_NIC2_DBG_1_1,
+	GAUDI2_BMON_NIC2_DBG_2_1,
+	GAUDI2_BMON_NIC3_DBG_0_0,
+	GAUDI2_BMON_NIC3_DBG_1_0,
+	GAUDI2_BMON_NIC3_DBG_2_0,
+	GAUDI2_BMON_NIC3_DBG_0_1,
+	GAUDI2_BMON_NIC3_DBG_1_1,
+	GAUDI2_BMON_NIC3_DBG_2_1,
+	GAUDI2_BMON_NIC4_DBG_0_0,
+	GAUDI2_BMON_NIC4_DBG_1_0,
+	GAUDI2_BMON_NIC4_DBG_2_0,
+	GAUDI2_BMON_NIC4_DBG_0_1,
+	GAUDI2_BMON_NIC4_DBG_1_1,
+	GAUDI2_BMON_NIC4_DBG_2_1,
+	GAUDI2_BMON_NIC5_DBG_0_0,
+	GAUDI2_BMON_NIC5_DBG_1_0,
+	GAUDI2_BMON_NIC5_DBG_2_0,
+	GAUDI2_BMON_NIC5_DBG_0_1,
+	GAUDI2_BMON_NIC5_DBG_1_1,
+	GAUDI2_BMON_NIC5_DBG_2_1,
+	GAUDI2_BMON_NIC6_DBG_0_0,
+	GAUDI2_BMON_NIC6_DBG_1_0,
+	GAUDI2_BMON_NIC6_DBG_2_0,
+	GAUDI2_BMON_NIC6_DBG_0_1,
+	GAUDI2_BMON_NIC6_DBG_1_1,
+	GAUDI2_BMON_NIC6_DBG_2_1,
+	GAUDI2_BMON_NIC7_DBG_0_0,
+	GAUDI2_BMON_NIC7_DBG_1_0,
+	GAUDI2_BMON_NIC7_DBG_2_0,
+	GAUDI2_BMON_NIC7_DBG_0_1,
+	GAUDI2_BMON_NIC7_DBG_1_1,
+	GAUDI2_BMON_NIC7_DBG_2_1,
+	GAUDI2_BMON_NIC8_DBG_0_0,
+	GAUDI2_BMON_NIC8_DBG_1_0,
+	GAUDI2_BMON_NIC8_DBG_2_0,
+	GAUDI2_BMON_NIC8_DBG_0_1,
+	GAUDI2_BMON_NIC8_DBG_1_1,
+	GAUDI2_BMON_NIC8_DBG_2_1,
+	GAUDI2_BMON_NIC9_DBG_0_0,
+	GAUDI2_BMON_NIC9_DBG_1_0,
+	GAUDI2_BMON_NIC9_DBG_2_0,
+	GAUDI2_BMON_NIC9_DBG_0_1,
+	GAUDI2_BMON_NIC9_DBG_1_1,
+	GAUDI2_BMON_NIC9_DBG_2_1,
+	GAUDI2_BMON_NIC10_DBG_0_0,
+	GAUDI2_BMON_NIC10_DBG_1_0,
+	GAUDI2_BMON_NIC10_DBG_2_0,
+	GAUDI2_BMON_NIC10_DBG_0_1,
+	GAUDI2_BMON_NIC10_DBG_1_1,
+	GAUDI2_BMON_NIC10_DBG_2_1,
+	GAUDI2_BMON_NIC11_DBG_0_0,
+	GAUDI2_BMON_NIC11_DBG_1_0,
+	GAUDI2_BMON_NIC11_DBG_2_0,
+	GAUDI2_BMON_NIC11_DBG_0_1,
+	GAUDI2_BMON_NIC11_DBG_1_1,
+	GAUDI2_BMON_NIC11_DBG_2_1,
+	GAUDI2_BMON_LAST = GAUDI2_BMON_NIC11_DBG_2_1
+};
+
+enum gaudi2_debug_spmu_regs_index {
+	GAUDI2_SPMU_FIRST = 0,
+	GAUDI2_SPMU_DCORE0_TPC0_EML = GAUDI2_SPMU_FIRST,
+	GAUDI2_SPMU_DCORE0_TPC1_EML,
+	GAUDI2_SPMU_DCORE0_TPC2_EML,
+	GAUDI2_SPMU_DCORE0_TPC3_EML,
+	GAUDI2_SPMU_DCORE0_TPC4_EML,
+	GAUDI2_SPMU_DCORE0_TPC5_EML,
+	GAUDI2_SPMU_DCORE0_TPC6_EML,
+	GAUDI2_SPMU_DCORE1_TPC0_EML,
+	GAUDI2_SPMU_DCORE1_TPC1_EML,
+	GAUDI2_SPMU_DCORE1_TPC2_EML,
+	GAUDI2_SPMU_DCORE1_TPC3_EML,
+	GAUDI2_SPMU_DCORE1_TPC4_EML,
+	GAUDI2_SPMU_DCORE1_TPC5_EML,
+	GAUDI2_SPMU_DCORE2_TPC0_EML,
+	GAUDI2_SPMU_DCORE2_TPC1_EML,
+	GAUDI2_SPMU_DCORE2_TPC2_EML,
+	GAUDI2_SPMU_DCORE2_TPC3_EML,
+	GAUDI2_SPMU_DCORE2_TPC4_EML,
+	GAUDI2_SPMU_DCORE2_TPC5_EML,
+	GAUDI2_SPMU_DCORE3_TPC0_EML,
+	GAUDI2_SPMU_DCORE3_TPC1_EML,
+	GAUDI2_SPMU_DCORE3_TPC2_EML,
+	GAUDI2_SPMU_DCORE3_TPC3_EML,
+	GAUDI2_SPMU_DCORE3_TPC4_EML,
+	GAUDI2_SPMU_DCORE3_TPC5_EML,
+	GAUDI2_SPMU_DCORE0_HMMU0_CS,
+	GAUDI2_SPMU_DCORE0_HMMU1_CS,
+	GAUDI2_SPMU_DCORE0_HMMU2_CS,
+	GAUDI2_SPMU_DCORE0_HMMU3_CS,
+	GAUDI2_SPMU_DCORE0_MME_CTRL,
+	GAUDI2_SPMU_DCORE0_MME_SBTE0,
+	GAUDI2_SPMU_DCORE0_MME_SBTE1,
+	GAUDI2_SPMU_DCORE0_MME_SBTE2,
+	GAUDI2_SPMU_DCORE0_MME_SBTE3,
+	GAUDI2_SPMU_DCORE0_MME_SBTE4,
+	GAUDI2_SPMU_DCORE0_MME_ACC,
+	GAUDI2_SPMU_DCORE0_SM,
+	GAUDI2_SPMU_DCORE0_EDMA0_CS,
+	GAUDI2_SPMU_DCORE0_EDMA1_CS,
+	GAUDI2_SPMU_DCORE0_VDEC0_CS,
+	GAUDI2_SPMU_DCORE0_VDEC1_CS,
+	GAUDI2_SPMU_DCORE1_HMMU0_CS,
+	GAUDI2_SPMU_DCORE1_HMMU1_CS,
+	GAUDI2_SPMU_DCORE1_HMMU2_CS,
+	GAUDI2_SPMU_DCORE1_HMMU3_CS,
+	GAUDI2_SPMU_DCORE1_MME_CTRL,
+	GAUDI2_SPMU_DCORE1_MME_SBTE0,
+	GAUDI2_SPMU_DCORE1_MME_SBTE1,
+	GAUDI2_SPMU_DCORE1_MME_SBTE2,
+	GAUDI2_SPMU_DCORE1_MME_SBTE3,
+	GAUDI2_SPMU_DCORE1_MME_SBTE4,
+	GAUDI2_SPMU_DCORE1_MME_ACC,
+	GAUDI2_SPMU_DCORE1_SM,
+	GAUDI2_SPMU_DCORE1_EDMA0_CS,
+	GAUDI2_SPMU_DCORE1_EDMA1_CS,
+	GAUDI2_SPMU_DCORE1_VDEC0_CS,
+	GAUDI2_SPMU_DCORE1_VDEC1_CS,
+	GAUDI2_SPMU_DCORE2_HMMU0_CS,
+	GAUDI2_SPMU_DCORE2_HMMU1_CS,
+	GAUDI2_SPMU_DCORE2_HMMU2_CS,
+	GAUDI2_SPMU_DCORE2_HMMU3_CS,
+	GAUDI2_SPMU_DCORE2_MME_CTRL,
+	GAUDI2_SPMU_DCORE2_MME_SBTE0,
+	GAUDI2_SPMU_DCORE2_MME_SBTE1,
+	GAUDI2_SPMU_DCORE2_MME_SBTE2,
+	GAUDI2_SPMU_DCORE2_MME_SBTE3,
+	GAUDI2_SPMU_DCORE2_MME_SBTE4,
+	GAUDI2_SPMU_DCORE2_MME_ACC,
+	GAUDI2_SPMU_DCORE2_SM,
+	GAUDI2_SPMU_DCORE2_EDMA0_CS,
+	GAUDI2_SPMU_DCORE2_EDMA1_CS,
+	GAUDI2_SPMU_DCORE2_VDEC0_CS,
+	GAUDI2_SPMU_DCORE2_VDEC1_CS,
+	GAUDI2_SPMU_DCORE3_HMMU0_CS,
+	GAUDI2_SPMU_DCORE3_HMMU1_CS,
+	GAUDI2_SPMU_DCORE3_HMMU2_CS,
+	GAUDI2_SPMU_DCORE3_HMMU3_CS,
+	GAUDI2_SPMU_DCORE3_MME_CTRL,
+	GAUDI2_SPMU_DCORE3_MME_SBTE0,
+	GAUDI2_SPMU_DCORE3_MME_SBTE1,
+	GAUDI2_SPMU_DCORE3_MME_SBTE2,
+	GAUDI2_SPMU_DCORE3_MME_SBTE3,
+	GAUDI2_SPMU_DCORE3_MME_SBTE4,
+	GAUDI2_SPMU_DCORE3_MME_ACC,
+	GAUDI2_SPMU_DCORE3_SM,
+	GAUDI2_SPMU_DCORE3_EDMA0_CS,
+	GAUDI2_SPMU_DCORE3_EDMA1_CS,
+	GAUDI2_SPMU_DCORE3_VDEC0_CS,
+	GAUDI2_SPMU_DCORE3_VDEC1_CS,
+	GAUDI2_SPMU_PCIE,
+	GAUDI2_SPMU_PSOC_ARC0_CS,
+	GAUDI2_SPMU_PSOC_ARC1_CS,
+	GAUDI2_SPMU_PDMA0_CS,
+	GAUDI2_SPMU_PDMA1_CS,
+	GAUDI2_SPMU_PMMU_CS,
+	GAUDI2_SPMU_ROT0_CS,
+	GAUDI2_SPMU_ROT1_CS,
+	GAUDI2_SPMU_ARC_FARM_CS,
+	GAUDI2_SPMU_KDMA_CS,
+	GAUDI2_SPMU_PCIE_VDEC0_CS,
+	GAUDI2_SPMU_PCIE_VDEC1_CS,
+	GAUDI2_SPMU_HBM0_MC0_CS,
+	GAUDI2_SPMU_HBM0_MC1_CS,
+	GAUDI2_SPMU_HBM1_MC0_CS,
+	GAUDI2_SPMU_HBM1_MC1_CS,
+	GAUDI2_SPMU_HBM2_MC0_CS,
+	GAUDI2_SPMU_HBM2_MC1_CS,
+	GAUDI2_SPMU_HBM3_MC0_CS,
+	GAUDI2_SPMU_HBM3_MC1_CS,
+	GAUDI2_SPMU_HBM4_MC0_CS,
+	GAUDI2_SPMU_HBM4_MC1_CS,
+	GAUDI2_SPMU_HBM5_MC0_CS,
+	GAUDI2_SPMU_HBM5_MC1_CS,
+	GAUDI2_SPMU_NIC0_DBG_0,
+	GAUDI2_SPMU_NIC0_DBG_1,
+	GAUDI2_SPMU_NIC1_DBG_0,
+	GAUDI2_SPMU_NIC1_DBG_1,
+	GAUDI2_SPMU_NIC2_DBG_0,
+	GAUDI2_SPMU_NIC2_DBG_1,
+	GAUDI2_SPMU_NIC3_DBG_0,
+	GAUDI2_SPMU_NIC3_DBG_1,
+	GAUDI2_SPMU_NIC4_DBG_0,
+	GAUDI2_SPMU_NIC4_DBG_1,
+	GAUDI2_SPMU_NIC5_DBG_0,
+	GAUDI2_SPMU_NIC5_DBG_1,
+	GAUDI2_SPMU_NIC6_DBG_0,
+	GAUDI2_SPMU_NIC6_DBG_1,
+	GAUDI2_SPMU_NIC7_DBG_0,
+	GAUDI2_SPMU_NIC7_DBG_1,
+	GAUDI2_SPMU_NIC8_DBG_0,
+	GAUDI2_SPMU_NIC8_DBG_1,
+	GAUDI2_SPMU_NIC9_DBG_0,
+	GAUDI2_SPMU_NIC9_DBG_1,
+	GAUDI2_SPMU_NIC10_DBG_0,
+	GAUDI2_SPMU_NIC10_DBG_1,
+	GAUDI2_SPMU_NIC11_DBG_0,
+	GAUDI2_SPMU_NIC11_DBG_1,
+	GAUDI2_SPMU_LAST = GAUDI2_SPMU_NIC11_DBG_1
+};
+
+#endif /* GAUDI2_CORESIGHT_H */
diff --git a/drivers/accel/habanalabs/include/gaudi2/gaudi2_fw_if.h b/drivers/accel/habanalabs/include/gaudi2/gaudi2_fw_if.h
new file mode 100644
index 000000000000..6ea936c9594e
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/gaudi2_fw_if.h
@@ -0,0 +1,94 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2019-2021 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+#ifndef GAUDI2_FW_IF_H
+#define GAUDI2_FW_IF_H
+
+#define GAUDI2_EVENT_QUEUE_MSIX_IDX	0
+
+#define UBOOT_FW_OFFSET			0x100000	/* 1MB in SRAM */
+#define LINUX_FW_OFFSET			0x800000	/* 8BM in DDR */
+
+#define GAUDI2_PLL_FREQ_LOW		200000000 /* 200 MHz */
+
+#define GAUDI2_SP_SRAM_BASE_ADDR	0x27FE0000
+#define GAUDI2_MAILBOX_BASE_ADDR	0x27FE1800
+
+#define GAUDI2_NUM_MME			4
+
+#define NUM_OF_GPIOS_PER_PORT		16
+#define GAUDI2_WD_GPIO			(62 % NUM_OF_GPIOS_PER_PORT)
+
+#define GAUDI2_ARCPID_TX_MB_SIZE	0x1000
+#define GAUDI2_ARCPID_RX_MB_SIZE	0x400
+#define GAUDI2_ARM_TX_MB_SIZE		0x400
+#define GAUDI2_ARM_RX_MB_SIZE		0x1800
+
+#define GAUDI2_DCCM_BASE_ADDR		0x27020000
+
+#define GAUDI2_ARM_TX_MB_ADDR		GAUDI2_MAILBOX_BASE_ADDR
+
+#define GAUDI2_ARM_RX_MB_ADDR		(GAUDI2_ARM_TX_MB_ADDR + \
+					GAUDI2_ARM_TX_MB_SIZE)
+
+#define GAUDI2_ARCPID_TX_MB_ADDR	(GAUDI2_ARM_RX_MB_ADDR + GAUDI2_ARM_RX_MB_SIZE)
+
+#define GAUDI2_ARCPID_RX_MB_ADDR	(GAUDI2_ARCPID_TX_MB_ADDR + GAUDI2_ARCPID_TX_MB_SIZE)
+
+#define GAUDI2_ARM_TX_MB_OFFSET		(GAUDI2_ARM_TX_MB_ADDR - \
+					GAUDI2_SP_SRAM_BASE_ADDR)
+
+#define GAUDI2_ARM_RX_MB_OFFSET		(GAUDI2_ARM_RX_MB_ADDR - \
+					GAUDI2_SP_SRAM_BASE_ADDR)
+
+#define POWER_MODE_LEVELS	{	\
+	150000,		/* 00 */	\
+	250000,		/* 01 */	\
+	400000,		/* 10 */	\
+	/* 11: Normal mode */		\
+}
+
+enum gaudi2_fw_status {
+	GAUDI2_PID_STATUS_UP = 0x1,	/* PID on ARC0 is up */
+	GAUDI2_ARM_STATUS_UP = 0x2,	/* ARM Linux Boot complete */
+	GAUDI2_MGMT_STATUS_UP = 0x3,	/* ARC1 Mgmt is up */
+	GAUDI2_STATUS_LAST = 0xFF
+};
+
+enum gaudi2_rst_src {
+	HL_COLD_RST = 1,
+	HL_MANUAL_RST = 2,
+	HL_PRSTN_RST = 4,
+	HL_SOFT_RST = 8,
+	HL_WD_RST = 16,
+	HL_FW_ALL_RST = 32,
+	HL_SW_ALL_RST = 64,
+	HL_FLR_RST = 128,
+	HL_ECC_DERR_RST = 256
+};
+
+struct gaudi2_redundancy_ctx {
+	__le32 redundant_hbm;
+	__le32 redundant_edma;
+	__le32 redundant_tpc;
+	__le32 redundant_vdec;
+	__le64 hbm_mask;
+	__le64 edma_mask;
+	__le64 tpc_mask;
+	__le64 vdec_mask;
+	__le64 mme_mask;
+	__le64 nic_mask;
+	__le64 rtr_mask;
+	__le64 hmmu_hif_iso;
+	__le64 xbar_edge_iso;
+	__le64 hmmu_hif_mask;
+	__le64 xbar_edge_mask;
+	__u8 mme_pe_iso[GAUDI2_NUM_MME];
+	__le32 full_hbm_mode;	/* true on full (non binning hbm)*/
+} __packed;
+
+#endif /* GAUDI2_FW_IF_H */
diff --git a/drivers/accel/habanalabs/include/gaudi2/gaudi2_packets.h b/drivers/accel/habanalabs/include/gaudi2/gaudi2_packets.h
new file mode 100644
index 000000000000..a812f8503f90
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/gaudi2_packets.h
@@ -0,0 +1,197 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+#ifndef GAUDI2_PACKETS_H
+#define GAUDI2_PACKETS_H
+
+#include <linux/types.h>
+
+#define PACKET_HEADER_PACKET_ID_SHIFT		56
+#define PACKET_HEADER_PACKET_ID_MASK		0x1F00000000000000ull
+
+enum packet_id {
+	PACKET_WREG_32 = 0x1,
+	PACKET_WREG_BULK = 0x2,
+	PACKET_MSG_LONG = 0x3,
+	PACKET_MSG_SHORT = 0x4,
+	PACKET_CP_DMA = 0x5,
+	PACKET_REPEAT = 0x6,
+	PACKET_MSG_PROT = 0x7,
+	PACKET_FENCE = 0x8,
+	PACKET_LIN_DMA = 0x9,
+	PACKET_NOP = 0xA,
+	PACKET_STOP = 0xB,
+	PACKET_ARB_POINT = 0xC,
+	PACKET_WAIT = 0xD,
+	PACKET_CB_LIST = 0xE,
+	PACKET_LOAD_AND_EXE = 0xF,
+	PACKET_WRITE_ARC_STREAM = 0x10,
+	PACKET_LAST_READ_FROM_ARC = 0x11,
+	PACKET_WREG_64_SHORT = 0x12,
+	PACKET_WREG_64_LONG = 0x13,
+	MAX_PACKET_ID = (PACKET_HEADER_PACKET_ID_MASK >>
+				PACKET_HEADER_PACKET_ID_SHIFT) + 1
+};
+
+#define GAUDI2_PKT_CTL_OPCODE_SHIFT	24
+#define GAUDI2_PKT_CTL_OPCODE_MASK	0x1F000000
+
+#define GAUDI2_PKT_CTL_EB_SHIFT		29
+#define GAUDI2_PKT_CTL_EB_MASK		0x20000000
+
+#define GAUDI2_PKT_CTL_RB_SHIFT		30
+#define GAUDI2_PKT_CTL_RB_MASK		0x40000000
+
+#define GAUDI2_PKT_CTL_MB_SHIFT		31
+#define GAUDI2_PKT_CTL_MB_MASK		0x80000000
+
+/* All packets have, at least, an 8-byte header, which contains
+ * the packet type. The kernel driver uses the packet header for packet
+ * validation and to perform any necessary required preparation before
+ * sending them off to the hardware.
+ */
+struct gaudi2_packet {
+	__le64 header;
+	/* The rest of the packet data follows. Use the corresponding
+	 * packet_XXX struct to deference the data, based on packet type
+	 */
+	u8 contents[];
+};
+
+struct packet_nop {
+	__le32 reserved;
+	__le32 ctl;
+};
+
+struct packet_stop {
+	__le32 reserved;
+	__le32 ctl;
+};
+
+struct packet_wreg32 {
+	__le32 value;
+	__le32 ctl;
+};
+
+struct packet_wreg_bulk {
+	__le32 size64;
+	__le32 ctl;
+	__le64 values[]; /* data starts here */
+};
+
+struct packet_msg_long {
+	__le32 value;
+	__le32 ctl;
+	__le64 addr;
+};
+
+#define GAUDI2_PKT_SHORT_VAL_SOB_SYNC_VAL_SHIFT	0
+#define GAUDI2_PKT_SHORT_VAL_SOB_SYNC_VAL_MASK	0x00007FFF
+
+#define GAUDI2_PKT_SHORT_VAL_SOB_MOD_SHIFT	31
+#define GAUDI2_PKT_SHORT_VAL_SOB_MOD_MASK	0x80000000
+
+#define GAUDI2_PKT_SHORT_VAL_MON_SYNC_GID_SHIFT	0
+#define GAUDI2_PKT_SHORT_VAL_MON_SYNC_GID_MASK	0x000000FF
+
+#define GAUDI2_PKT_SHORT_VAL_MON_MASK_SHIFT	8
+#define GAUDI2_PKT_SHORT_VAL_MON_MASK_MASK	0x0000FF00
+
+#define GAUDI2_PKT_SHORT_VAL_MON_MODE_SHIFT	16
+#define GAUDI2_PKT_SHORT_VAL_MON_MODE_MASK	0x00010000
+
+#define GAUDI2_PKT_SHORT_VAL_MON_SYNC_VAL_SHIFT	17
+#define GAUDI2_PKT_SHORT_VAL_MON_SYNC_VAL_MASK	0xFFFE0000
+
+#define GAUDI2_PKT_SHORT_CTL_ADDR_SHIFT		0
+#define GAUDI2_PKT_SHORT_CTL_ADDR_MASK		0x0000FFFF
+
+#define GAUDI2_PKT_SHORT_CTL_BASE_SHIFT		22
+#define GAUDI2_PKT_SHORT_CTL_BASE_MASK		0x00C00000
+
+struct packet_msg_short {
+	__le32 value;
+	__le32 ctl;
+};
+
+struct packet_msg_prot {
+	__le32 value;
+	__le32 ctl;
+	__le64 addr;
+};
+
+#define GAUDI2_PKT_FENCE_CFG_DEC_VAL_SHIFT	0
+#define GAUDI2_PKT_FENCE_CFG_DEC_VAL_MASK	0x0000000F
+
+#define GAUDI2_PKT_FENCE_CFG_TARGET_VAL_SHIFT	16
+#define GAUDI2_PKT_FENCE_CFG_TARGET_VAL_MASK	0x00FF0000
+
+#define GAUDI2_PKT_FENCE_CFG_ID_SHIFT		30
+#define GAUDI2_PKT_FENCE_CFG_ID_MASK		0xC0000000
+
+#define GAUDI2_PKT_FENCE_CTL_PRED_SHIFT		0
+#define GAUDI2_PKT_FENCE_CTL_PRED_MASK		0x0000001F
+
+struct packet_fence {
+	__le32 cfg;
+	__le32 ctl;
+};
+
+#define GAUDI2_PKT_LIN_DMA_CTL_WRCOMP_SHIFT	0
+#define GAUDI2_PKT_LIN_DMA_CTL_WRCOMP_MASK	0x00000001
+
+#define GAUDI2_PKT_LIN_DMA_CTL_ENDIAN_SHIFT	1
+#define GAUDI2_PKT_LIN_DMA_CTL_ENDIAN_MASK	0x00000006
+
+#define GAUDI2_PKT_LIN_DMA_CTL_MEMSET_SHIFT	4
+#define GAUDI2_PKT_LIN_DMA_CTL_MEMSET_MASK	0x00000010
+
+#define GAUDI2_PKT_LIN_DMA_CTL_CONTEXT_ID_SHIFT	8
+#define GAUDI2_PKT_LIN_DMA_CTL_CONTEXT_ID_MASK	0x00FFFF00
+
+struct packet_lin_dma {
+	__le32 tsize;
+	__le32 ctl;
+	__le64 src_addr;
+	__le64 dst_addr;
+};
+
+struct packet_arb_point {
+	__le32 cfg;
+	__le32 ctl;
+};
+
+struct packet_repeat {
+	__le32 cfg;
+	__le32 ctl;
+};
+
+struct packet_wait {
+	__le32 cfg;
+	__le32 ctl;
+};
+
+struct packet_cb_list {
+	__le32 reserved;
+	__le32 ctl;
+	__le64 index_addr;
+	__le64 table_addr;
+};
+
+struct packet_load_and_exe {
+	__le32 cfg;
+	__le32 ctl;
+	__le64 src_addr;
+};
+
+struct packet_cp_dma {
+	__le32 tsize;
+	__le32 ctl;
+	__le64 src_addr;
+};
+
+#endif /* GAUDI2_PACKETS_H */
diff --git a/drivers/accel/habanalabs/include/gaudi2/gaudi2_reg_map.h b/drivers/accel/habanalabs/include/gaudi2/gaudi2_reg_map.h
new file mode 100644
index 000000000000..1e9c056e437d
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/gaudi2_reg_map.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+#ifndef GAUDI2_REG_MAP_H_
+#define GAUDI2_REG_MAP_H_
+
+/*
+ * PSOC scratch-pad registers
+ */
+#define mmHW_STATE				mmCPU_IF_KMD_HW_DIRTY_STATUS
+#define mmPID_STATUS_REG			mmPSOC_GLOBAL_CONF_SCRATCHPAD_1
+#define mmARM_STATUS_REG			mmPSOC_GLOBAL_CONF_SCRATCHPAD_2
+#define mmGIC_TPC_QM_IRQ_CTRL_POLL_REG		mmPSOC_GLOBAL_CONF_SCRATCHPAD_3
+#define mmGIC_MME_QM_IRQ_CTRL_POLL_REG		mmPSOC_GLOBAL_CONF_SCRATCHPAD_4
+#define mmGIC_DMA_QM_IRQ_CTRL_POLL_REG		mmPSOC_GLOBAL_CONF_SCRATCHPAD_5
+#define mmGIC_ROT_QM_IRQ_CTRL_POLL_REG		mmPSOC_GLOBAL_CONF_SCRATCHPAD_6
+#define mmGIC_NIC_QM_IRQ_CTRL_POLL_REG		mmPSOC_GLOBAL_CONF_SCRATCHPAD_7
+#define mmGIC_DMA_CR_IRQ_CTRL_POLL_REG		mmPSOC_GLOBAL_CONF_SCRATCHPAD_8
+#define mmGIC_HOST_PI_UPD_IRQ_POLL_REG		mmPSOC_GLOBAL_CONF_SCRATCHPAD_9
+#define mmGIC_HOST_HALT_IRQ_POLL_REG		mmPSOC_GLOBAL_CONF_SCRATCHPAD_10
+#define mmGIC_HOST_INTS_IRQ_POLL_REG		mmPSOC_GLOBAL_CONF_SCRATCHPAD_11
+#define mmGIC_HOST_SOFT_RST_IRQ_POLL_REG	mmPSOC_GLOBAL_CONF_SCRATCHPAD_12
+#define mmCPU_RST_STATUS_TO_HOST		mmPSOC_GLOBAL_CONF_SCRATCHPAD_14
+/*
+ *  Single scratchpad register used for all ARCs to notify dccm queue full event to FW.
+ *  So a new event would overwrite any unhandled previous event. In other words, incase
+ *  of multiple events before previous ones are handled, last one would be considered.
+ */
+#define mmENGINE_ARC_IRQ_CTRL_POLL_REG		mmPSOC_GLOBAL_CONF_SCRATCHPAD_15
+#define mmPID_CFG_REG				mmPSOC_GLOBAL_CONF_SCRATCHPAD_18
+#define mmGIC_RAZWI_STATUS_REG			mmPSOC_GLOBAL_CONF_SCRATCHPAD_19
+#define mmCPU_BOOT_DEV_STS0			mmPSOC_GLOBAL_CONF_SCRATCHPAD_20
+#define mmCPU_BOOT_DEV_STS1			mmPSOC_GLOBAL_CONF_SCRATCHPAD_21
+#define mmCPU_CMD_STATUS_TO_HOST		mmPSOC_GLOBAL_CONF_SCRATCHPAD_23
+#define mmCPU_BOOT_ERR0				mmPSOC_GLOBAL_CONF_SCRATCHPAD_24
+#define mmCPU_BOOT_ERR1				mmPSOC_GLOBAL_CONF_SCRATCHPAD_25
+#define mmUPD_STS				mmPSOC_GLOBAL_CONF_SCRATCHPAD_26
+#define mmUPD_CMD				mmPSOC_GLOBAL_CONF_SCRATCHPAD_27
+#define mmPPBOOT_VER_OFFSET			mmPSOC_GLOBAL_CONF_SCRATCHPAD_28
+#define mmRDWR_TEST				mmPSOC_GLOBAL_CONF_SCRATCHPAD_30
+#define mmBTL_ID				mmPSOC_GLOBAL_CONF_SCRATCHPAD_31
+#define mmRST_SRC				mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_0
+#define mmCOLD_RST_DATA				mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_2
+#define mmUPD_PENDING_STS			mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_3
+#define mmPID_CMD_REQ_REG			mmPSOC_PID_PID_CMD_0
+#define mmPID_CMD_REQ_REG_HI			mmPSOC_PID_PID_CMD_1
+#define mmPID_CMD_RSP_REG			mmPSOC_PID_PID_CMD_2
+#define mmPID_CMD_RSP_REG_HI			mmPSOC_PID_PID_CMD_3
+#define mmPID_CMD_TELEMETRY_REG_0		mmPSOC_PID_PID_CMD_4
+#define mmPID_CMD_TELEMETRY_REG_0_HI		mmPSOC_PID_PID_CMD_5
+#define mmPID_CMD_TELEMETRY_REG_1		mmPSOC_PID_PID_CMD_6
+#define mmPID_CMD_TELEMETRY_REG_1_HI		mmPSOC_PID_PID_CMD_7
+#define mmWD_GPIO_OUTSET_REG			mmPSOC_GPIO3_OUTENSET
+#define mmWD_GPIO_DATAOUT_REG			mmPSOC_GPIO3_DATAOUT
+#define mmSTM_PROFILER_SPE_REG			mmPSOC_STM_STMSPER
+
+/* Registers below are used to pass the boot_if data between ARM and ARC1 */
+#define mmARM_MSG_BOOT_ERR_SET			mmCPU_IF_SPECIAL_GLBL_SPARE_0
+#define mmARM_MSG_BOOT_ERR_CLR			mmCPU_IF_SPECIAL_GLBL_SPARE_1
+#define mmARM_MSG_BOOT_DEV_STS_SET		mmCPU_IF_SPECIAL_GLBL_SPARE_2
+#define mmARM_MSG_BOOT_DEV_STS_CLR		mmCPU_IF_SPECIAL_GLBL_SPARE_3
+#define mmMGMT_MSG_BOOT_ERR			mmCPU_MSTR_IF_SPECIAL_GLBL_SPARE_0
+#define mmMGMT_MSG_BOOT_DEV_STS			mmCPU_MSTR_IF_SPECIAL_GLBL_SPARE_1
+
+#endif /* GAUDI2_REG_MAP_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi2/gaudi2_special_blocks.h b/drivers/accel/habanalabs/include/gaudi2/gaudi2_special_blocks.h
new file mode 100644
index 000000000000..a55668f92dd1
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/gaudi2_special_blocks.h
@@ -0,0 +1,157 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2022 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ */
+
+/*
+ * This file was generated automatically.
+ * DON'T EDIT THIS FILE.
+ */
+
+#ifndef GAUDI2_SPECIAL_BLOCKS_H
+#define GAUDI2_SPECIAL_BLOCKS_H
+
+#define GAUDI2_SPECIAL_BLOCKS { \
+	{ GAUDI2_BLOCK_TYPE_TPC, 0xfc008000, 4, 6, 0, 0x200000, 0x10000, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_TPC, 0xfc00a000, 4, 6, 0, 0x200000, 0x10000, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_TPC, 0xfc00b000, 4, 6, 0, 0x200000, 0x10000, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_TPC, 0xfc00c000, 4, 6, 0, 0x200000, 0x10000, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_HMMU, 0xfc080000, 4, 4, 0, 0x200000, 0x10000, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_HMMU, 0xfc081000, 4, 4, 0, 0x200000, 0x10000, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_HMMU, 0xfc083000, 4, 4, 0, 0x200000, 0x10000, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_HMMU, 0xfc084000, 4, 4, 0, 0x200000, 0x10000, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_MME, 0xfc0c8000, 4, 0, 0, 0x200000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_MME, 0xfc0c9000, 4, 0, 0, 0x200000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_MME, 0xfc0ca000, 4, 0, 0, 0x200000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_MME, 0xfc0cb000, 4, 0, 0, 0x200000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_MME, 0xfc0cc000, 4, 0, 0, 0x200000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_EU_BIST, 0xfc0cd000, 4, 0, 0, 0x200000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_MME, 0xfc0ce000, 4, 0, 0, 0x200000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_MME, 0xfc0cf000, 4, 0, 0, 0x200000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_MME, 0xfc0d0000, 4, 5, 0, 0x200000, 0x8000, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_MME, 0xfc0d1000, 4, 5, 0, 0x200000, 0x8000, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_MME, 0xfc0f8000, 4, 0, 0, 0x200000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_MME, 0xfc0f9000, 4, 2, 0, 0x200000, 0x1000, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_SYNC_MNGR, 0xfc11e000, 4, 0, 0, 0x200000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_SYNC_MNGR, 0xfc11f000, 4, 0, 0, 0x200000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_HIF, 0xfc120000, 4, 4, 0, 0x200000, 0x4000, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_RTR, 0xfc140000, 4, 8, 0, 0x200000, 0x8000, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_RTR, 0xfc141000, 4, 8, 0, 0x200000, 0x8000, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_RTR, 0xfc142000, 4, 8, 0, 0x200000, 0x8000, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_RTR, 0xfc143000, 4, 8, 0, 0x200000, 0x8000, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_RTR, 0xfc144000, 4, 8, 0, 0x200000, 0x8000, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_RTR, 0xfc145000, 4, 8, 0, 0x200000, 0x8000, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_SRAM, 0xfc180000, 4, 8, 0, 0x200000, 0x8000, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_RTR, 0xfc181000, 4, 8, 0, 0x200000, 0x8000, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_SRAM, 0xfc182000, 4, 8, 0, 0x200000, 0x8000, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_EDMA, 0xfc1c8000, 4, 2, 0, 0x200000, 0x10000, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_EDMA, 0xfc1ca000, 4, 2, 0, 0x200000, 0x10000, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_EDMA, 0xfc1cb000, 4, 2, 0, 0x200000, 0x10000, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_EDMA, 0xfc1cc000, 4, 2, 0, 0x200000, 0x10000, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_DEC, 0xfc1e3000, 4, 2, 0, 0x200000, 0x10000, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_DEC, 0xfc1e4000, 4, 2, 0, 0x200000, 0x10000, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_DEC, 0xfc1e5000, 4, 2, 0, 0x200000, 0x10000, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PCIE, 0xfcc01000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PCIE, 0xfcc04000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PCIE, 0xfcc07000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PCIE, 0xfcc10000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PCIE, 0xfcc14000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PCIE, 0xfcc15000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PCIE, 0xfcc16000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PSOC, 0xfcc4a000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PSOC, 0xfcc4b000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PSOC, 0xfcc4e000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PSOC, 0xfcc4f000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PSOC, 0xfcc53000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PSOC, 0xfcc54000, 2, 0, 0, 0x1000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PSOC, 0xfcc58000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PSOC, 0xfcc59000, 2, 0, 0, 0x3000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PSOC, 0xfcc5a000, 2, 0, 0, 0x3000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PSOC, 0xfcc5b000, 2, 0, 0, 0x3000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PSOC, 0xfcc60000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PSOC, 0xfcc61000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PSOC, 0xfcc62000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PSOC, 0xfcc63000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PSOC, 0xfcc64000, 3, 0, 0, 0x1000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PLL, 0xfcc6c000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PLL, 0xfcc6d000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PLL, 0xfcc6e000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PSOC, 0xfcc74000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PSOC, 0xfcc76000, 3, 0, 0, 0x1000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PSOC, 0xfcc79000, 2, 0, 0, 0x1000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PSOC, 0xfcc7b000, 3, 0, 0, 0x1000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PSOC, 0xfcc7f000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PDMA, 0xfcc88000, 2, 0, 0, 0x10000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PDMA, 0xfcc8a000, 2, 0, 0, 0x10000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PDMA, 0xfcc8b000, 2, 0, 0, 0x10000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PDMA, 0xfcc8c000, 2, 0, 0, 0x10000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_CPU, 0xfccc0000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_CPU, 0xfccc1000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_CPU, 0xfccc3000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PMMU, 0xfcd00000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PMMU, 0xfcd01000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PMMU, 0xfcd02000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PMMU, 0xfcd03000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PLL, 0xfcd04000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PLL, 0xfcd05000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_XBAR, 0xfcd40000, 4, 0, 0, 0x10000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PLL, 0xfcd41000, 4, 0, 0, 0x10000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PLL, 0xfcd42000, 4, 0, 0, 0x10000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PLL, 0xfcd43000, 4, 0, 0, 0x10000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PLL, 0xfcd44000, 2, 0, 0, 0x10000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_XBAR, 0xfcd48000, 4, 0, 0, 0x10000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PLL, 0xfcd55000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PLL, 0xfcd64000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PLL, 0xfcd65000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PLL, 0xfcd74000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_ROT, 0xfce08000, 2, 0, 0, 0x10000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_ROT, 0xfce0a000, 2, 0, 0, 0x10000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_ROT, 0xfce0b000, 2, 0, 0, 0x10000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_ROT, 0xfce0c000, 2, 0, 0, 0x10000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_RTR, 0xfce40000, 4, 2, 0, 0x10000, 0x4000, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_RTR, 0xfce41000, 4, 2, 0, 0x10000, 0x4000, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_RTR, 0xfce42000, 4, 2, 0, 0x10000, 0x4000, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_RTR, 0xfce43000, 4, 2, 0, 0x10000, 0x4000, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_RTR, 0xfce48000, 4, 0, 0, 0x10000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_RTR, 0xfce49000, 4, 0, 0, 0x10000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_RTR, 0xfce4a000, 4, 0, 0, 0x10000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_RTR, 0xfce4b000, 4, 0, 0, 0x10000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_RTR, 0xfce4c000, 4, 0, 0, 0x10000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_ARC_FARM, 0xfce81000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_ARC_FARM, 0xfce82000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_ARC_FARM, 0xfce88000, 4, 0, 0, 0x20000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_ARC_FARM, 0xfce89000, 4, 0, 0, 0x20000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_ARC_FARM, 0xfce8b000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_ARC_FARM, 0xfce8c000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_ARC_FARM, 0xfce8f000, 4, 0, 0, 0x20000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_DEC, 0xfcf03000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_DEC, 0xfcf04000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_DEC, 0xfcf05000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_XFT, 0xfcf40000, 4, 0, 0, 0x10000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PLL, 0xfcf41000, 4, 0, 0, 0x10000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PLL, 0xfcf42000, 4, 0, 0, 0x10000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PLL, 0xfcf43000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PLL, 0xfcf53000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_PLL, 0xfcf73000, 1, 0, 0, 0x0, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_HBM, 0xfd000000, 6, 2, 0, 0x80000, 0x20000, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_HBM, 0xfd001000, 6, 2, 8, 0x80000, 0x20000, 0x1000 }, \
+	{ GAUDI2_BLOCK_TYPE_HBM, 0xfd009000, 6, 2, 0, 0x80000, 0x20000, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_NIC, 0xfd400000, 12, 2, 15, 0x80000, 0x20000, 0x1000 }, \
+	{ GAUDI2_BLOCK_TYPE_NIC, 0xfd418000, 12, 2, 0, 0x80000, 0x20000, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_NIC, 0xfd41a000, 12, 2, 0, 0x80000, 0x20000, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_NIC, 0xfd41f000, 12, 2, 0, 0x80000, 0x20000, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_NIC, 0xfd448000, 12, 0, 0, 0x80000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_NIC, 0xfd449000, 12, 0, 0, 0x80000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_NIC, 0xfd44a000, 12, 2, 0, 0x80000, 0x1000, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_NIC, 0xfd44c000, 12, 2, 0, 0x80000, 0x1000, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_NIC, 0xfd450000, 12, 2, 0, 0x80000, 0x1000, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_NIC, 0xfd452000, 12, 2, 0, 0x80000, 0x1000, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_NIC, 0xfd454000, 12, 0, 0, 0x80000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_NIC, 0xfd455000, 12, 0, 0, 0x80000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_NIC, 0xfd460000, 12, 0, 0, 0x80000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_NIC, 0xfd468000, 12, 0, 0, 0x80000, 0x0, 0x0 }, \
+	{ GAUDI2_BLOCK_TYPE_NIC, 0xfd469000, 12, 0, 0, 0x80000, 0x0, 0x0 }, \
+}
+
+#endif
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/cpu_ca53_cfg_masks.h b/drivers/accel/habanalabs/include/goya/asic_reg/cpu_ca53_cfg_masks.h
index 4e0dbbbbde20..4e0dbbbbde20 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/cpu_ca53_cfg_masks.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/cpu_ca53_cfg_masks.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/cpu_ca53_cfg_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/cpu_ca53_cfg_regs.h
index f3faf1aad91a..f3faf1aad91a 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/cpu_ca53_cfg_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/cpu_ca53_cfg_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/cpu_if_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/cpu_if_regs.h
index cf657918962a..cf657918962a 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/cpu_if_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/cpu_if_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/cpu_pll_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/cpu_pll_regs.h
index 8c8f9726d4b9..8c8f9726d4b9 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/cpu_pll_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/cpu_pll_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_0_masks.h b/drivers/accel/habanalabs/include/goya/asic_reg/dma_ch_0_masks.h
index 028143408401..028143408401 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_0_masks.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/dma_ch_0_masks.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_0_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/dma_ch_0_regs.h
index 0b246fe6ad04..0b246fe6ad04 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_0_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/dma_ch_0_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_1_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/dma_ch_1_regs.h
index 5449031722f2..5449031722f2 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_1_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/dma_ch_1_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_2_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/dma_ch_2_regs.h
index a4768521d18a..a4768521d18a 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_2_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/dma_ch_2_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_3_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/dma_ch_3_regs.h
index 619d01897ff8..619d01897ff8 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_3_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/dma_ch_3_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_4_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/dma_ch_4_regs.h
index 038617e163f1..038617e163f1 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_4_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/dma_ch_4_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_macro_masks.h b/drivers/accel/habanalabs/include/goya/asic_reg/dma_macro_masks.h
index f43b564af1be..f43b564af1be 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/dma_macro_masks.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/dma_macro_masks.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_macro_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/dma_macro_regs.h
index c3bfc1b8e3fd..c3bfc1b8e3fd 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/dma_macro_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/dma_macro_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_nrtr_masks.h b/drivers/accel/habanalabs/include/goya/asic_reg/dma_nrtr_masks.h
index bc977488c072..bc977488c072 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/dma_nrtr_masks.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/dma_nrtr_masks.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_nrtr_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/dma_nrtr_regs.h
index c4abc7ff1fc6..c4abc7ff1fc6 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/dma_nrtr_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/dma_nrtr_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_0_masks.h b/drivers/accel/habanalabs/include/goya/asic_reg/dma_qm_0_masks.h
index b17f72c31ab6..b17f72c31ab6 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_0_masks.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/dma_qm_0_masks.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_0_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/dma_qm_0_regs.h
index bf360b301154..bf360b301154 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_0_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/dma_qm_0_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_1_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/dma_qm_1_regs.h
index 51d432d05ac4..51d432d05ac4 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_1_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/dma_qm_1_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_2_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/dma_qm_2_regs.h
index 18fc0c2b6cc2..18fc0c2b6cc2 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_2_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/dma_qm_2_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_3_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/dma_qm_3_regs.h
index 6cf7204bf5cc..6cf7204bf5cc 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_3_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/dma_qm_3_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_4_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/dma_qm_4_regs.h
index 36fef2682875..36fef2682875 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/dma_qm_4_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/dma_qm_4_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/goya_blocks.h b/drivers/accel/habanalabs/include/goya/asic_reg/goya_blocks.h
index 85b15010cd7a..85b15010cd7a 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/goya_blocks.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/goya_blocks.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/goya_masks.h b/drivers/accel/habanalabs/include/goya/asic_reg/goya_masks.h
index 3c44ef3a23ed..9ff3cb245580 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/goya_masks.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/goya_masks.h
@@ -55,8 +55,7 @@
 	(1 << DMA_QM_0_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT) | \
 	(1 << DMA_QM_0_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \
 	(1 << DMA_QM_0_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \
-	(1 << DMA_QM_0_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT) | \
-	(1 << DMA_QM_0_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT))
+	(1 << DMA_QM_0_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT))
 
 #define QMAN_MME_ENABLE		(\
 	(1 << MME_QM_GLBL_CFG0_PQF_EN_SHIFT) | \
@@ -260,6 +259,9 @@
 #define DMA_QM_3_GLBL_CFG1_DMA_STOP_SHIFT DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT
 #define DMA_QM_4_GLBL_CFG1_DMA_STOP_SHIFT DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT
 
-#define PSOC_ETR_AXICTL_PROTCTRLBIT1_SHIFT                           1
+#define PSOC_ETR_AXICTL_PROTCTRLBIT1_SHIFT	1
+#define PSOC_ETR_AXICTL_PROTCTRLBIT0_MASK	0x1
+#define PSOC_ETR_AXICTL_PROTCTRLBIT1_MASK	0x2
+#define PSOC_ETR_AXICTL_WRBURSTLEN_MASK		0xF00
 
 #endif /* ASIC_REG_GOYA_MASKS_H_ */
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/goya_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/goya_regs.h
index fce490e6a231..ce65c9da5c60 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/goya_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/goya_regs.h
@@ -18,6 +18,7 @@
 #include "psoc_mme_pll_regs.h"
 #include "psoc_pci_pll_regs.h"
 #include "psoc_emmc_pll_regs.h"
+#include "psoc_timestamp_regs.h"
 #include "cpu_if_regs.h"
 #include "cpu_ca53_cfg_regs.h"
 #include "cpu_pll_regs.h"
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/ic_pll_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/ic_pll_regs.h
index 4ae7fed8b18c..4ae7fed8b18c 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/ic_pll_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/ic_pll_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mc_pll_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/mc_pll_regs.h
index 6d35d852798b..6d35d852798b 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/mc_pll_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/mc_pll_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mme1_rtr_masks.h b/drivers/accel/habanalabs/include/goya/asic_reg/mme1_rtr_masks.h
index 6c23f8b96e7e..6c23f8b96e7e 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/mme1_rtr_masks.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/mme1_rtr_masks.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mme1_rtr_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/mme1_rtr_regs.h
index 122e9d529939..122e9d529939 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/mme1_rtr_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/mme1_rtr_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mme2_rtr_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/mme2_rtr_regs.h
index 00ce2252bbfb..00ce2252bbfb 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/mme2_rtr_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/mme2_rtr_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mme3_rtr_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/mme3_rtr_regs.h
index 8e3eb7fd2070..8e3eb7fd2070 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/mme3_rtr_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/mme3_rtr_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mme4_rtr_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/mme4_rtr_regs.h
index 79b67bbc8567..79b67bbc8567 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/mme4_rtr_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/mme4_rtr_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mme5_rtr_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/mme5_rtr_regs.h
index 0ac3c37ce47f..0ac3c37ce47f 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/mme5_rtr_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/mme5_rtr_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mme6_rtr_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/mme6_rtr_regs.h
index 50c49cce72a6..50c49cce72a6 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/mme6_rtr_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/mme6_rtr_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mme_cmdq_masks.h b/drivers/accel/habanalabs/include/goya/asic_reg/mme_cmdq_masks.h
index fe7d95bdcef9..fe7d95bdcef9 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/mme_cmdq_masks.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/mme_cmdq_masks.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mme_cmdq_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/mme_cmdq_regs.h
index 5f8b85d2b4b1..5f8b85d2b4b1 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/mme_cmdq_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/mme_cmdq_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mme_masks.h b/drivers/accel/habanalabs/include/goya/asic_reg/mme_masks.h
index 1882c413cbe0..1882c413cbe0 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/mme_masks.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/mme_masks.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mme_qm_masks.h b/drivers/accel/habanalabs/include/goya/asic_reg/mme_qm_masks.h
index e464e381555c..e464e381555c 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/mme_qm_masks.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/mme_qm_masks.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mme_qm_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/mme_qm_regs.h
index 538708beffc9..538708beffc9 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/mme_qm_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/mme_qm_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mme_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/mme_regs.h
index 0396cbfd5c89..0396cbfd5c89 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/mme_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/mme_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mmu_masks.h b/drivers/accel/habanalabs/include/goya/asic_reg/mmu_masks.h
index c3e69062b135..c3e69062b135 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/mmu_masks.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/mmu_masks.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/mmu_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/mmu_regs.h
index 7ec81f12031e..7ec81f12031e 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/mmu_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/mmu_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/pci_nrtr_masks.h b/drivers/accel/habanalabs/include/goya/asic_reg/pci_nrtr_masks.h
index ceb59f2e28b3..ceb59f2e28b3 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/pci_nrtr_masks.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/pci_nrtr_masks.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/pci_nrtr_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/pci_nrtr_regs.h
index dd067f301ac2..dd067f301ac2 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/pci_nrtr_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/pci_nrtr_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/pcie_aux_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/pcie_aux_regs.h
index 35b1d8ac6f63..35b1d8ac6f63 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/pcie_aux_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/pcie_aux_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/pcie_wrap_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/pcie_wrap_regs.h
index d1e55aace4a0..d1e55aace4a0 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/pcie_wrap_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/pcie_wrap_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/psoc_emmc_pll_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/psoc_emmc_pll_regs.h
index 9271ea95ebe9..9271ea95ebe9 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/psoc_emmc_pll_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/psoc_emmc_pll_regs.h
diff --git a/drivers/accel/habanalabs/include/goya/asic_reg/psoc_etr_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/psoc_etr_regs.h
new file mode 100644
index 000000000000..b7c33e025db5
--- /dev/null
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/psoc_etr_regs.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PSOC_ETR_REGS_H_
+#define ASIC_REG_PSOC_ETR_REGS_H_
+
+/*
+ *****************************************
+ *   PSOC_ETR (Prototype: ETR)
+ *****************************************
+ */
+
+#define mmPSOC_ETR_RSZ                                               0x2C43004
+
+#define mmPSOC_ETR_STS                                               0x2C4300C
+
+#define mmPSOC_ETR_RRD                                               0x2C43010
+
+#define mmPSOC_ETR_RRP                                               0x2C43014
+
+#define mmPSOC_ETR_RWP                                               0x2C43018
+
+#define mmPSOC_ETR_TRG                                               0x2C4301C
+
+#define mmPSOC_ETR_CTL                                               0x2C43020
+
+#define mmPSOC_ETR_RWD                                               0x2C43024
+
+#define mmPSOC_ETR_MODE                                              0x2C43028
+
+#define mmPSOC_ETR_LBUFLEVEL                                         0x2C4302C
+
+#define mmPSOC_ETR_CBUFLEVEL                                         0x2C43030
+
+#define mmPSOC_ETR_BUFWM                                             0x2C43034
+
+#define mmPSOC_ETR_RRPHI                                             0x2C43038
+
+#define mmPSOC_ETR_RWPHI                                             0x2C4303C
+
+#define mmPSOC_ETR_AXICTL                                            0x2C43110
+
+#define mmPSOC_ETR_DBALO                                             0x2C43118
+
+#define mmPSOC_ETR_DBAHI                                             0x2C4311C
+
+#define mmPSOC_ETR_FFSR                                              0x2C43300
+
+#define mmPSOC_ETR_FFCR                                              0x2C43304
+
+#define mmPSOC_ETR_PSCR                                              0x2C43308
+
+#define mmPSOC_ETR_ITMISCOP0                                         0x2C43EE0
+
+#define mmPSOC_ETR_ITTRFLIN                                          0x2C43EE8
+
+#define mmPSOC_ETR_ITATBDATA0                                        0x2C43EEC
+
+#define mmPSOC_ETR_ITATBCTR2                                         0x2C43EF0
+
+#define mmPSOC_ETR_ITATBCTR1                                         0x2C43EF4
+
+#define mmPSOC_ETR_ITATBCTR0                                         0x2C43EF8
+
+#define mmPSOC_ETR_ITCTRL                                            0x2C43F00
+
+#define mmPSOC_ETR_CLAIMSET                                          0x2C43FA0
+
+#define mmPSOC_ETR_CLAIMCLR                                          0x2C43FA4
+
+#define mmPSOC_ETR_LAR                                               0x2C43FB0
+
+#define mmPSOC_ETR_LSR                                               0x2C43FB4
+
+#define mmPSOC_ETR_AUTHSTATUS                                        0x2C43FB8
+
+#define mmPSOC_ETR_DEVID                                             0x2C43FC8
+
+#define mmPSOC_ETR_DEVTYPE                                           0x2C43FCC
+
+#define mmPSOC_ETR_PERIPHID4                                         0x2C43FD0
+
+#define mmPSOC_ETR_PERIPHID5                                         0x2C43FD4
+
+#define mmPSOC_ETR_PERIPHID6                                         0x2C43FD8
+
+#define mmPSOC_ETR_PERIPHID7                                         0x2C43FDC
+
+#define mmPSOC_ETR_PERIPHID0                                         0x2C43FE0
+
+#define mmPSOC_ETR_PERIPHID1                                         0x2C43FE4
+
+#define mmPSOC_ETR_PERIPHID2                                         0x2C43FE8
+
+#define mmPSOC_ETR_PERIPHID3                                         0x2C43FEC
+
+#define mmPSOC_ETR_COMPID0                                           0x2C43FF0
+
+#define mmPSOC_ETR_COMPID1                                           0x2C43FF4
+
+#define mmPSOC_ETR_COMPID2                                           0x2C43FF8
+
+#define mmPSOC_ETR_COMPID3                                           0x2C43FFC
+
+#endif /* ASIC_REG_PSOC_ETR_REGS_H_ */
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/psoc_global_conf_masks.h b/drivers/accel/habanalabs/include/goya/asic_reg/psoc_global_conf_masks.h
index 324266653c9a..324266653c9a 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/psoc_global_conf_masks.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/psoc_global_conf_masks.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/psoc_global_conf_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/psoc_global_conf_regs.h
index 8141f422e712..8141f422e712 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/psoc_global_conf_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/psoc_global_conf_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/psoc_mme_pll_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/psoc_mme_pll_regs.h
index 4789ebb9c337..4789ebb9c337 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/psoc_mme_pll_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/psoc_mme_pll_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/psoc_pci_pll_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/psoc_pci_pll_regs.h
index 27a296ea6c3d..27a296ea6c3d 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/psoc_pci_pll_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/psoc_pci_pll_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/psoc_spi_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/psoc_spi_regs.h
index 66aee7fa6b1e..66aee7fa6b1e 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/psoc_spi_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/psoc_spi_regs.h
diff --git a/drivers/accel/habanalabs/include/goya/asic_reg/psoc_timestamp_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/psoc_timestamp_regs.h
new file mode 100644
index 000000000000..9ce24597d4b0
--- /dev/null
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/psoc_timestamp_regs.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_PSOC_TIMESTAMP_REGS_H_
+#define ASIC_REG_PSOC_TIMESTAMP_REGS_H_
+
+/*
+ *****************************************
+ *   PSOC_TIMESTAMP (Prototype: TIMESTAMP)
+ *****************************************
+ */
+
+#define mmPSOC_TIMESTAMP_CNTCR                                       0xC49000
+
+#define mmPSOC_TIMESTAMP_CNTSR                                       0xC49004
+
+#define mmPSOC_TIMESTAMP_CNTCVL                                      0xC49008
+
+#define mmPSOC_TIMESTAMP_CNTCVU                                      0xC4900C
+
+#define mmPSOC_TIMESTAMP_CNTFID0                                     0xC49020
+
+#define mmPSOC_TIMESTAMP_PIDR4                                       0xC49FD0
+
+#define mmPSOC_TIMESTAMP_PIDR5                                       0xC49FD4
+
+#define mmPSOC_TIMESTAMP_PIDR6                                       0xC49FD8
+
+#define mmPSOC_TIMESTAMP_PIDR7                                       0xC49FDC
+
+#define mmPSOC_TIMESTAMP_PIDR0                                       0xC49FE0
+
+#define mmPSOC_TIMESTAMP_PIDR1                                       0xC49FE4
+
+#define mmPSOC_TIMESTAMP_PIDR2                                       0xC49FE8
+
+#define mmPSOC_TIMESTAMP_PIDR3                                       0xC49FEC
+
+#define mmPSOC_TIMESTAMP_CIDR0                                       0xC49FF0
+
+#define mmPSOC_TIMESTAMP_CIDR1                                       0xC49FF4
+
+#define mmPSOC_TIMESTAMP_CIDR2                                       0xC49FF8
+
+#define mmPSOC_TIMESTAMP_CIDR3                                       0xC49FFC
+
+#endif /* ASIC_REG_PSOC_TIMESTAMP_REGS_H_ */
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x0_rtr_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/sram_y0_x0_rtr_regs.h
index 2ea1770b078f..2ea1770b078f 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x0_rtr_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/sram_y0_x0_rtr_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x1_rtr_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/sram_y0_x1_rtr_regs.h
index 37e0713efa73..37e0713efa73 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x1_rtr_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/sram_y0_x1_rtr_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x2_rtr_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/sram_y0_x2_rtr_regs.h
index d2572279a2b9..d2572279a2b9 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x2_rtr_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/sram_y0_x2_rtr_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x3_rtr_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/sram_y0_x3_rtr_regs.h
index 68c5b402c506..68c5b402c506 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x3_rtr_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/sram_y0_x3_rtr_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x4_rtr_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/sram_y0_x4_rtr_regs.h
index a42f1ba06d28..a42f1ba06d28 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/sram_y0_x4_rtr_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/sram_y0_x4_rtr_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/stlb_masks.h b/drivers/accel/habanalabs/include/goya/asic_reg/stlb_masks.h
index 94f2ed4a36bd..94f2ed4a36bd 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/stlb_masks.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/stlb_masks.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/stlb_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/stlb_regs.h
index 35013f65acd2..35013f65acd2 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/stlb_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/stlb_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_cfg_masks.h b/drivers/accel/habanalabs/include/goya/asic_reg/tpc0_cfg_masks.h
index 89c9507a512f..89c9507a512f 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_cfg_masks.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/tpc0_cfg_masks.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_cfg_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/tpc0_cfg_regs.h
index 7d71c4b73a5e..7d71c4b73a5e 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_cfg_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/tpc0_cfg_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_cmdq_masks.h b/drivers/accel/habanalabs/include/goya/asic_reg/tpc0_cmdq_masks.h
index 9395f2458771..9395f2458771 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_cmdq_masks.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/tpc0_cmdq_masks.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_cmdq_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/tpc0_cmdq_regs.h
index bc51df573bf0..bc51df573bf0 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_cmdq_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/tpc0_cmdq_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_eml_cfg_masks.h b/drivers/accel/habanalabs/include/goya/asic_reg/tpc0_eml_cfg_masks.h
index 553c6b6bd5ec..553c6b6bd5ec 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_eml_cfg_masks.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/tpc0_eml_cfg_masks.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_eml_cfg_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/tpc0_eml_cfg_regs.h
index 8495479c3659..8495479c3659 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_eml_cfg_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/tpc0_eml_cfg_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_nrtr_masks.h b/drivers/accel/habanalabs/include/goya/asic_reg/tpc0_nrtr_masks.h
index 43fafcf01041..43fafcf01041 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_nrtr_masks.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/tpc0_nrtr_masks.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_nrtr_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/tpc0_nrtr_regs.h
index ce3346dd2042..ce3346dd2042 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_nrtr_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/tpc0_nrtr_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_qm_masks.h b/drivers/accel/habanalabs/include/goya/asic_reg/tpc0_qm_masks.h
index 2e4b45947944..2e4b45947944 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_qm_masks.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/tpc0_qm_masks.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_qm_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/tpc0_qm_regs.h
index 4fa09eb88878..4fa09eb88878 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/tpc0_qm_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/tpc0_qm_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc1_cfg_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/tpc1_cfg_regs.h
index 928eef1808ae..928eef1808ae 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/tpc1_cfg_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/tpc1_cfg_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc1_cmdq_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/tpc1_cmdq_regs.h
index 30ae0f307328..30ae0f307328 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/tpc1_cmdq_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/tpc1_cmdq_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc1_qm_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/tpc1_qm_regs.h
index b95de4f95ba9..b95de4f95ba9 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/tpc1_qm_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/tpc1_qm_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc1_rtr_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/tpc1_rtr_regs.h
index 0f91e307879e..0f91e307879e 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/tpc1_rtr_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/tpc1_rtr_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc2_cfg_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/tpc2_cfg_regs.h
index 73421227f35b..73421227f35b 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/tpc2_cfg_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/tpc2_cfg_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc2_cmdq_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/tpc2_cmdq_regs.h
index 27b66bf2da9f..27b66bf2da9f 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/tpc2_cmdq_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/tpc2_cmdq_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc2_qm_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/tpc2_qm_regs.h
index 31e5b2f53905..31e5b2f53905 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/tpc2_qm_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/tpc2_qm_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc2_rtr_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/tpc2_rtr_regs.h
index 4eddeaa15d94..4eddeaa15d94 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/tpc2_rtr_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/tpc2_rtr_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc3_cfg_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/tpc3_cfg_regs.h
index ce573a1a8361..ce573a1a8361 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/tpc3_cfg_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/tpc3_cfg_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc3_cmdq_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/tpc3_cmdq_regs.h
index 11d81fca0a0f..11d81fca0a0f 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/tpc3_cmdq_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/tpc3_cmdq_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc3_qm_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/tpc3_qm_regs.h
index e41595a19e69..e41595a19e69 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/tpc3_qm_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/tpc3_qm_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc3_rtr_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/tpc3_rtr_regs.h
index 34a438b1efe5..34a438b1efe5 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/tpc3_rtr_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/tpc3_rtr_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc4_cfg_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/tpc4_cfg_regs.h
index d44caf0fc1bb..d44caf0fc1bb 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/tpc4_cfg_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/tpc4_cfg_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc4_cmdq_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/tpc4_cmdq_regs.h
index f13a6532961f..f13a6532961f 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/tpc4_cmdq_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/tpc4_cmdq_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc4_qm_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/tpc4_qm_regs.h
index db081fc17cfc..db081fc17cfc 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/tpc4_qm_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/tpc4_qm_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc4_rtr_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/tpc4_rtr_regs.h
index 8c5372303b28..8c5372303b28 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/tpc4_rtr_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/tpc4_rtr_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc5_cfg_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/tpc5_cfg_regs.h
index 5139fde71011..5139fde71011 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/tpc5_cfg_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/tpc5_cfg_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc5_cmdq_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/tpc5_cmdq_regs.h
index 1e7cd6e1e888..1e7cd6e1e888 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/tpc5_cmdq_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/tpc5_cmdq_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc5_qm_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/tpc5_qm_regs.h
index ac0d3820cd6b..ac0d3820cd6b 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/tpc5_qm_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/tpc5_qm_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc5_rtr_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/tpc5_rtr_regs.h
index 57f83bc3b17d..57f83bc3b17d 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/tpc5_rtr_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/tpc5_rtr_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc6_cfg_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/tpc6_cfg_regs.h
index 94e0191c06c1..94e0191c06c1 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/tpc6_cfg_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/tpc6_cfg_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc6_cmdq_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/tpc6_cmdq_regs.h
index 7a1a0e87b225..7a1a0e87b225 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/tpc6_cmdq_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/tpc6_cmdq_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc6_qm_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/tpc6_qm_regs.h
index 80fa0fe0f60f..80fa0fe0f60f 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/tpc6_qm_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/tpc6_qm_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc6_rtr_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/tpc6_rtr_regs.h
index d6cae8b8af66..d6cae8b8af66 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/tpc6_rtr_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/tpc6_rtr_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc7_cfg_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/tpc7_cfg_regs.h
index 234147adb779..234147adb779 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/tpc7_cfg_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/tpc7_cfg_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc7_cmdq_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/tpc7_cmdq_regs.h
index 4c160632fe7d..4c160632fe7d 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/tpc7_cmdq_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/tpc7_cmdq_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc7_nrtr_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/tpc7_nrtr_regs.h
index 0c13d4d167aa..0c13d4d167aa 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/tpc7_nrtr_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/tpc7_nrtr_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc7_qm_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/tpc7_qm_regs.h
index cbe11425bfb0..cbe11425bfb0 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/tpc7_qm_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/tpc7_qm_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/tpc_pll_regs.h b/drivers/accel/habanalabs/include/goya/asic_reg/tpc_pll_regs.h
index e25e19660a9d..e25e19660a9d 100644
--- a/drivers/misc/habanalabs/include/goya/asic_reg/tpc_pll_regs.h
+++ b/drivers/accel/habanalabs/include/goya/asic_reg/tpc_pll_regs.h
diff --git a/drivers/misc/habanalabs/include/goya/goya.h b/drivers/accel/habanalabs/include/goya/goya.h
index 43d241891e45..1b4ca435021d 100644
--- a/drivers/misc/habanalabs/include/goya/goya.h
+++ b/drivers/accel/habanalabs/include/goya/goya.h
@@ -30,7 +30,7 @@
 
 #define QMAN_PQ_ENTRY_SIZE	16			/* Bytes */
 
-#define MAX_ASID		1024
+#define MAX_ASID		2
 
 #define PROT_BITS_OFFS		0xF80
 
diff --git a/drivers/misc/habanalabs/include/goya/goya_async_events.h b/drivers/accel/habanalabs/include/goya/goya_async_events.h
index 5fb92362fc5f..09081401cb1d 100644
--- a/drivers/misc/habanalabs/include/goya/goya_async_events.h
+++ b/drivers/accel/habanalabs/include/goya/goya_async_events.h
@@ -188,6 +188,7 @@ enum goya_async_event_id {
 	GOYA_ASYNC_EVENT_ID_HALT_MACHINE = 485,
 	GOYA_ASYNC_EVENT_ID_INTS_REGISTER = 486,
 	GOYA_ASYNC_EVENT_ID_SOFT_RESET = 487,
+	GOYA_ASYNC_EVENT_PKT_QUEUE_OUT_SYNC = 506,
 	GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_S = 507,
 	GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_E = 508,
 	GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_S = 509,
diff --git a/drivers/misc/habanalabs/include/goya/goya_coresight.h b/drivers/accel/habanalabs/include/goya/goya_coresight.h
index 6e933c0ca5cd..6e933c0ca5cd 100644
--- a/drivers/misc/habanalabs/include/goya/goya_coresight.h
+++ b/drivers/accel/habanalabs/include/goya/goya_coresight.h
diff --git a/drivers/misc/habanalabs/include/goya/goya_fw_if.h b/drivers/accel/habanalabs/include/goya/goya_fw_if.h
index 0fa80fe9f6cc..bc05f86c73ac 100644
--- a/drivers/misc/habanalabs/include/goya/goya_fw_if.h
+++ b/drivers/accel/habanalabs/include/goya/goya_fw_if.h
@@ -15,16 +15,6 @@
 #define UBOOT_FW_OFFSET		0x100000		/* 1MB in SRAM */
 #define LINUX_FW_OFFSET		0x800000		/* 8MB in DDR */
 
-enum goya_pll_index {
-	CPU_PLL = 0,
-	IC_PLL,
-	MC_PLL,
-	MME_PLL,
-	PCI_PLL,
-	EMMC_PLL,
-	TPC_PLL
-};
-
 #define GOYA_PLL_FREQ_LOW		50000000 /* 50 MHz */
 
 #endif /* GOYA_FW_IF_H */
diff --git a/drivers/misc/habanalabs/include/goya/goya_packets.h b/drivers/accel/habanalabs/include/goya/goya_packets.h
index ef54bad20509..896799204fb0 100644
--- a/drivers/misc/habanalabs/include/goya/goya_packets.h
+++ b/drivers/accel/habanalabs/include/goya/goya_packets.h
@@ -28,18 +28,6 @@ enum packet_id {
 				PACKET_HEADER_PACKET_ID_SHIFT) + 1
 };
 
-enum goya_dma_direction {
-	DMA_HOST_TO_DRAM,
-	DMA_HOST_TO_SRAM,
-	DMA_DRAM_TO_SRAM,
-	DMA_SRAM_TO_DRAM,
-	DMA_SRAM_TO_HOST,
-	DMA_DRAM_TO_HOST,
-	DMA_DRAM_TO_DRAM,
-	DMA_SRAM_TO_SRAM,
-	DMA_ENUM_MAX
-};
-
 #define GOYA_PKT_CTL_OPCODE_SHIFT	24
 #define GOYA_PKT_CTL_OPCODE_MASK	0x1F000000
 
@@ -62,7 +50,7 @@ struct goya_packet {
 	/* The rest of the packet data follows. Use the corresponding
 	 * packet_XXX struct to deference the data, based on packet type
 	 */
-	u8 contents[0];
+	u8 contents[];
 };
 
 struct packet_nop {
@@ -86,7 +74,7 @@ struct packet_wreg32 {
 struct packet_wreg_bulk {
 	__le32 size64;
 	__le32 ctl;
-	__le64 values[0]; /* data starts here */
+	__le64 values[]; /* data starts here */
 };
 
 struct packet_msg_long {
diff --git a/drivers/accel/habanalabs/include/goya/goya_reg_map.h b/drivers/accel/habanalabs/include/goya/goya_reg_map.h
new file mode 100644
index 000000000000..f3ab282cafa4
--- /dev/null
+++ b/drivers/accel/habanalabs/include/goya/goya_reg_map.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2019 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+#ifndef GOYA_REG_MAP_H_
+#define GOYA_REG_MAP_H_
+
+/*
+ * PSOC scratch-pad registers
+ */
+#define mmCPU_PQ_BASE_ADDR_LOW		mmPSOC_GLOBAL_CONF_SCRATCHPAD_0
+#define mmCPU_PQ_BASE_ADDR_HIGH		mmPSOC_GLOBAL_CONF_SCRATCHPAD_1
+#define mmCPU_EQ_BASE_ADDR_LOW		mmPSOC_GLOBAL_CONF_SCRATCHPAD_2
+#define mmCPU_EQ_BASE_ADDR_HIGH		mmPSOC_GLOBAL_CONF_SCRATCHPAD_3
+#define mmCPU_EQ_LENGTH			mmPSOC_GLOBAL_CONF_SCRATCHPAD_4
+#define mmCPU_PQ_LENGTH			mmPSOC_GLOBAL_CONF_SCRATCHPAD_5
+#define mmCPU_EQ_CI			mmPSOC_GLOBAL_CONF_SCRATCHPAD_6
+#define mmCPU_PQ_INIT_STATUS		mmPSOC_GLOBAL_CONF_SCRATCHPAD_7
+#define mmCPU_CQ_BASE_ADDR_LOW		mmPSOC_GLOBAL_CONF_SCRATCHPAD_8
+#define mmCPU_CQ_BASE_ADDR_HIGH		mmPSOC_GLOBAL_CONF_SCRATCHPAD_9
+#define mmCPU_CQ_LENGTH			mmPSOC_GLOBAL_CONF_SCRATCHPAD_10
+#define mmCPU_BOOT_DEV_STS0		mmPSOC_GLOBAL_CONF_SCRATCHPAD_20
+#define mmCPU_BOOT_DEV_STS1		mmPSOC_GLOBAL_CONF_SCRATCHPAD_21
+#define mmFUSE_VER_OFFSET		mmPSOC_GLOBAL_CONF_SCRATCHPAD_22
+#define mmCPU_CMD_STATUS_TO_HOST	mmPSOC_GLOBAL_CONF_SCRATCHPAD_23
+#define mmCPU_BOOT_ERR0			mmPSOC_GLOBAL_CONF_SCRATCHPAD_24
+#define mmCPU_BOOT_ERR1			mmPSOC_GLOBAL_CONF_SCRATCHPAD_25
+#define mmUPD_STS			mmPSOC_GLOBAL_CONF_SCRATCHPAD_26
+#define mmUPD_CMD			mmPSOC_GLOBAL_CONF_SCRATCHPAD_27
+#define mmPREBOOT_VER_OFFSET		mmPSOC_GLOBAL_CONF_SCRATCHPAD_28
+#define mmUBOOT_VER_OFFSET		mmPSOC_GLOBAL_CONF_SCRATCHPAD_29
+#define mmRDWR_TEST			mmPSOC_GLOBAL_CONF_SCRATCHPAD_30
+#define mmBTL_ID			mmPSOC_GLOBAL_CONF_SCRATCHPAD_31
+
+#define mmHW_STATE			mmPSOC_GLOBAL_CONF_APP_STATUS
+#define mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS	mmPSOC_GLOBAL_CONF_WARM_REBOOT
+#define mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU	mmPSOC_GLOBAL_CONF_UBOOT_MAGIC
+#define mmUPD_PENDING_STS		mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_3
+
+#endif /* GOYA_REG_MAP_H_ */
diff --git a/drivers/accel/habanalabs/include/hw_ip/mmu/mmu_general.h b/drivers/accel/habanalabs/include/hw_ip/mmu/mmu_general.h
new file mode 100644
index 000000000000..b4a5e95be354
--- /dev/null
+++ b/drivers/accel/habanalabs/include/hw_ip/mmu/mmu_general.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+#ifndef INCLUDE_MMU_GENERAL_H_
+#define INCLUDE_MMU_GENERAL_H_
+
+#define PAGE_SHIFT_4KB			12
+#define PAGE_SHIFT_64KB			16
+#define PAGE_SHIFT_2MB			21
+#define PAGE_SHIFT_16MB			24
+#define PAGE_SHIFT_64MB			26
+#define PAGE_SHIFT_1GB			30
+#define PAGE_SIZE_4KB			_BITUL(PAGE_SHIFT_4KB)
+#define PAGE_SIZE_64KB			_BITUL(PAGE_SHIFT_64KB)
+#define PAGE_SIZE_2MB			_BITUL(PAGE_SHIFT_2MB)
+#define PAGE_SIZE_16MB			_BITUL(PAGE_SHIFT_16MB)
+#define PAGE_SIZE_64MB			_BITUL(PAGE_SHIFT_64MB)
+#define PAGE_SIZE_1GB			_BITUL(PAGE_SHIFT_1GB)
+
+#define PAGE_PRESENT_MASK		0x0000000000001ull
+#define SWAP_OUT_MASK			0x0000000000004ull
+#define LAST_MASK			0x0000000000800ull
+#define FLAGS_MASK			0x0000000000FFFull
+
+#define MMU_ARCH_3_HOPS			3
+#define MMU_ARCH_4_HOPS			4
+#define MMU_ARCH_5_HOPS			5
+#define MMU_ARCH_6_HOPS			6
+
+#define HOP_PHYS_ADDR_MASK		(~FLAGS_MASK)
+
+#define HL_PTE_SIZE			sizeof(u64)
+
+/* definitions for HOP with 512 PTE entries */
+#define HOP_PTE_ENTRIES_512		512
+#define HOP_TABLE_SIZE_512_PTE		(HOP_PTE_ENTRIES_512 * HL_PTE_SIZE)
+#define HOP0_512_PTE_TABLES_TOTAL_SIZE	(HOP_TABLE_SIZE_512_PTE * MAX_ASID)
+
+#define MMU_HOP0_PA43_12_SHIFT		12
+#define MMU_HOP0_PA49_44_SHIFT		(12 + 32)
+#define MMU_HOP0_PA63_44_SHIFT		(12 + 32)
+
+#define MMU_CONFIG_TIMEOUT_USEC		2000 /* 2 ms */
+
+enum mmu_hop_num {
+	MMU_HOP0,
+	MMU_HOP1,
+	MMU_HOP2,
+	MMU_HOP3,
+	MMU_HOP4,
+	MMU_HOP5,
+	MMU_HOP_MAX,
+};
+
+#endif /* INCLUDE_MMU_GENERAL_H_ */
diff --git a/drivers/accel/habanalabs/include/hw_ip/mmu/mmu_v1_0.h b/drivers/accel/habanalabs/include/hw_ip/mmu/mmu_v1_0.h
new file mode 100644
index 000000000000..86511002e367
--- /dev/null
+++ b/drivers/accel/habanalabs/include/hw_ip/mmu/mmu_v1_0.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+#ifndef INCLUDE_MMU_V1_0_H_
+#define INCLUDE_MMU_V1_0_H_
+
+#define MMU_V1_0_HOP0_MASK		0x3000000000000ull
+#define MMU_V1_0_HOP1_MASK		0x0FF8000000000ull
+#define MMU_V1_0_HOP2_MASK		0x0007FC0000000ull
+#define MMU_V1_0_HOP3_MASK		0x000003FE00000ull
+#define MMU_V1_0_HOP4_MASK		0x00000001FF000ull
+
+#define MMU_V1_0_HOP0_SHIFT		48
+#define MMU_V1_0_HOP1_SHIFT		39
+#define MMU_V1_0_HOP2_SHIFT		30
+#define MMU_V1_0_HOP3_SHIFT		21
+#define MMU_V1_0_HOP4_SHIFT		12
+
+#define MMU_HOP0_PA43_12		0x490004
+#define MMU_HOP0_PA49_44		0x490008
+#define MMU_ASID_BUSY			0x490000
+
+#endif /* INCLUDE_MMU_V1_0_H_ */
diff --git a/drivers/accel/habanalabs/include/hw_ip/mmu/mmu_v1_1.h b/drivers/accel/habanalabs/include/hw_ip/mmu/mmu_v1_1.h
new file mode 100644
index 000000000000..9c727a5d47b4
--- /dev/null
+++ b/drivers/accel/habanalabs/include/hw_ip/mmu/mmu_v1_1.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+#ifndef INCLUDE_MMU_V1_1_H_
+#define INCLUDE_MMU_V1_1_H_
+
+#define MMU_V1_1_HOP0_MASK		0x3000000000000ull
+#define MMU_V1_1_HOP1_MASK		0x0FF8000000000ull
+#define MMU_V1_1_HOP2_MASK		0x0007FC0000000ull
+#define MMU_V1_1_HOP3_MASK		0x000003FE00000ull
+#define MMU_V1_1_HOP4_MASK		0x00000001FF000ull
+
+#define MMU_V1_1_HOP0_SHIFT		48
+#define MMU_V1_1_HOP1_SHIFT		39
+#define MMU_V1_1_HOP2_SHIFT		30
+#define MMU_V1_1_HOP3_SHIFT		21
+#define MMU_V1_1_HOP4_SHIFT		12
+
+#define MMU_ASID			0xC12004
+#define MMU_HOP0_PA43_12		0xC12008
+#define MMU_HOP0_PA49_44		0xC1200C
+#define MMU_BUSY			0xC12000
+
+#endif /* INCLUDE_MMU_V1_1_H_ */
diff --git a/drivers/accel/habanalabs/include/hw_ip/mmu/mmu_v2_0.h b/drivers/accel/habanalabs/include/hw_ip/mmu/mmu_v2_0.h
new file mode 100644
index 000000000000..cd7bf25d2da9
--- /dev/null
+++ b/drivers/accel/habanalabs/include/hw_ip/mmu/mmu_v2_0.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2019 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+#ifndef INCLUDE_MMU_V2_0_H_
+#define INCLUDE_MMU_V2_0_H_
+
+#define HOP0_MASK_4K			0xFE00000000000000ull
+#define HOP1_MASK_4K			0x01FF000000000000ull
+#define HOP2_MASK_4K			0x0000FF8000000000ull
+#define HOP3_MASK_4K			0x0000007FC0000000ull
+#define HOP4_MASK_4K			0x000000003FE00000ull
+#define HOP5_MASK_4K			0x00000000001FF000ull
+
+#define HOP0_MASK_64K			0xFF00000000000000ull
+#define HOP1_MASK_64K			0x00FF000000000000ull
+#define HOP2_MASK_64K			0x0000FF0000000000ull
+#define HOP3_MASK_64K			0x000000FF00000000ull
+#define HOP4_MASK_64K			0x00000000FF000000ull
+#define HOP5_MASK_64K			0x0000000000FF0000ull
+
+#define HOP0_SHIFT_4K			57
+#define HOP1_SHIFT_4K			48
+#define HOP2_SHIFT_4K			39
+#define HOP3_SHIFT_4K			30
+#define HOP4_SHIFT_4K			21
+#define HOP5_SHIFT_4K			12
+
+#define HOP0_SHIFT_64K			56
+#define HOP1_SHIFT_64K			48
+#define HOP2_SHIFT_64K			40
+#define HOP3_SHIFT_64K			32
+#define HOP4_SHIFT_64K			24
+#define HOP5_SHIFT_64K			16
+
+#define DHOP0_MASK			HOP0_MASK_4K
+#define DHOP1_MASK			HOP1_MASK_4K
+#define DHOP2_MASK			HOP2_MASK_4K
+#define DHOP3_MASK			HOP3_MASK_4K
+#define DHOP4_MASK			0x000003C000000ull
+
+#define DHOP0_SHIFT			HOP0_SHIFT_4K
+#define DHOP1_SHIFT			HOP1_SHIFT_4K
+#define DHOP2_SHIFT			HOP2_SHIFT_4K
+#define DHOP3_SHIFT			HOP3_SHIFT_4K
+#define DHOP4_SHIFT			26
+
+#endif /* INCLUDE_MMU_V2_0_H_ */
diff --git a/drivers/misc/habanalabs/include/hw_ip/pci/pci_general.h b/drivers/accel/habanalabs/include/hw_ip/pci/pci_general.h
index d232081d4e0f..a75faa00197f 100644
--- a/drivers/misc/habanalabs/include/hw_ip/pci/pci_general.h
+++ b/drivers/accel/habanalabs/include/hw_ip/pci/pci_general.h
@@ -20,4 +20,13 @@
 #define PCI_CONFIG_ELBI_STS_MASK	(PCI_CONFIG_ELBI_STS_ERR | \
 					PCI_CONFIG_ELBI_STS_DONE)
 
+enum hl_revision_id {
+	/* PCI revision ID 0 is not legal */
+	REV_ID_INVALID				= 0x00,
+	REV_ID_A				= 0x01,
+	REV_ID_B				= 0x02,
+	REV_ID_C				= 0x03,
+	REV_ID_D				= 0x04
+};
+
 #endif /* INCLUDE_PCI_GENERAL_H_ */
diff --git a/drivers/accel/ivpu/Kconfig b/drivers/accel/ivpu/Kconfig
new file mode 100644
index 000000000000..9e055b5ce03d
--- /dev/null
+++ b/drivers/accel/ivpu/Kconfig
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config DRM_ACCEL_IVPU
+	tristate "Intel NPU (Neural Processing Unit)"
+	depends on DRM_ACCEL
+	depends on X86_64 && !UML
+	depends on PCI && PCI_MSI
+	select FW_LOADER
+	select DRM_GEM_SHMEM_HELPER
+	select GENERIC_ALLOCATOR
+	select WANT_DEV_COREDUMP
+	help
+	  Choose this option if you have a system with an 14th generation
+	  Intel CPU (Meteor Lake) or newer. Intel NPU (formerly called Intel VPU)
+	  is a CPU-integrated inference accelerator for Computer Vision
+	  and Deep Learning applications.
+
+	  If "M" is selected, the module will be called intel_vpu.
+
+config DRM_ACCEL_IVPU_DEBUG
+	bool "Intel NPU debug mode"
+	depends on DRM_ACCEL_IVPU
+	help
+	  Choose this option to enable additional
+	  debug features for the Intel NPU driver:
+	  - Always print debug messages regardless of dyndbg config,
+	  - Enable unsafe module params.
diff --git a/drivers/accel/ivpu/Makefile b/drivers/accel/ivpu/Makefile
new file mode 100644
index 000000000000..dbf76b8a5b4c
--- /dev/null
+++ b/drivers/accel/ivpu/Makefile
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-only
+# Copyright (C) 2023-2024 Intel Corporation
+
+intel_vpu-y := \
+	ivpu_drv.o \
+	ivpu_fw.o \
+	ivpu_fw_log.o \
+	ivpu_gem.o \
+	ivpu_gem_userptr.o \
+	ivpu_hw.o \
+	ivpu_hw_btrs.o \
+	ivpu_hw_ip.o \
+	ivpu_ipc.o \
+	ivpu_job.o \
+	ivpu_jsm_msg.o \
+	ivpu_mmu.o \
+	ivpu_mmu_context.o \
+	ivpu_ms.o \
+	ivpu_pm.o \
+	ivpu_sysfs.o \
+	ivpu_trace_points.o
+
+intel_vpu-$(CONFIG_DEBUG_FS) += ivpu_debugfs.o
+intel_vpu-$(CONFIG_DEV_COREDUMP) += ivpu_coredump.o
+
+obj-$(CONFIG_DRM_ACCEL_IVPU) += intel_vpu.o
+
+subdir-ccflags-$(CONFIG_DRM_ACCEL_IVPU_DEBUG) += -DDEBUG
+
+CFLAGS_ivpu_trace_points.o = -I$(src)
diff --git a/drivers/accel/ivpu/ivpu_coredump.c b/drivers/accel/ivpu/ivpu_coredump.c
new file mode 100644
index 000000000000..16ad0c30818c
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_coredump.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020-2024 Intel Corporation
+ */
+
+#include <linux/devcoredump.h>
+#include <linux/firmware.h>
+
+#include "ivpu_coredump.h"
+#include "ivpu_fw.h"
+#include "ivpu_gem.h"
+#include "vpu_boot_api.h"
+
+#define CRASH_DUMP_HEADER "Intel NPU crash dump"
+#define CRASH_DUMP_HEADERS_SIZE SZ_4K
+
+void ivpu_dev_coredump(struct ivpu_device *vdev)
+{
+	struct drm_print_iterator pi = {};
+	struct drm_printer p;
+	size_t coredump_size;
+	char *coredump;
+
+	coredump_size = CRASH_DUMP_HEADERS_SIZE + FW_VERSION_HEADER_SIZE +
+			ivpu_bo_size(vdev->fw->mem_log_crit) + ivpu_bo_size(vdev->fw->mem_log_verb);
+	coredump = vmalloc(coredump_size);
+	if (!coredump)
+		return;
+
+	pi.data = coredump;
+	pi.remain = coredump_size;
+	p = drm_coredump_printer(&pi);
+
+	drm_printf(&p, "%s\n", CRASH_DUMP_HEADER);
+	drm_printf(&p, "FW version: %s\n", vdev->fw->version);
+	ivpu_fw_log_print(vdev, false, &p);
+
+	dev_coredumpv(vdev->drm.dev, coredump, pi.offset, GFP_KERNEL);
+}
diff --git a/drivers/accel/ivpu/ivpu_coredump.h b/drivers/accel/ivpu/ivpu_coredump.h
new file mode 100644
index 000000000000..8efb09d02441
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_coredump.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2020-2024 Intel Corporation
+ */
+
+#ifndef __IVPU_COREDUMP_H__
+#define __IVPU_COREDUMP_H__
+
+#include <drm/drm_print.h>
+
+#include "ivpu_drv.h"
+#include "ivpu_fw_log.h"
+
+#ifdef CONFIG_DEV_COREDUMP
+void ivpu_dev_coredump(struct ivpu_device *vdev);
+#else
+static inline void ivpu_dev_coredump(struct ivpu_device *vdev)
+{
+	struct drm_printer p = drm_info_printer(vdev->drm.dev);
+
+	ivpu_fw_log_print(vdev, false, &p);
+}
+#endif
+
+#endif /* __IVPU_COREDUMP_H__ */
diff --git a/drivers/accel/ivpu/ivpu_debugfs.c b/drivers/accel/ivpu/ivpu_debugfs.c
new file mode 100644
index 000000000000..3bd85ee6c26b
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_debugfs.c
@@ -0,0 +1,512 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020-2024 Intel Corporation
+ */
+
+#include <linux/debugfs.h>
+#include <linux/fault-inject.h>
+
+#include <drm/drm_debugfs.h>
+#include <drm/drm_file.h>
+#include <drm/drm_print.h>
+
+#include <uapi/drm/ivpu_accel.h>
+
+#include "ivpu_debugfs.h"
+#include "ivpu_drv.h"
+#include "ivpu_fw.h"
+#include "ivpu_fw_log.h"
+#include "ivpu_gem.h"
+#include "ivpu_hw.h"
+#include "ivpu_jsm_msg.h"
+#include "ivpu_pm.h"
+
+static inline struct ivpu_device *seq_to_ivpu(struct seq_file *s)
+{
+	struct drm_debugfs_entry *entry = s->private;
+
+	return to_ivpu_device(entry->dev);
+}
+
+static int bo_list_show(struct seq_file *s, void *v)
+{
+	struct drm_printer p = drm_seq_file_printer(s);
+	struct ivpu_device *vdev = seq_to_ivpu(s);
+
+	ivpu_bo_list(&vdev->drm, &p);
+
+	return 0;
+}
+
+static int fw_name_show(struct seq_file *s, void *v)
+{
+	struct ivpu_device *vdev = seq_to_ivpu(s);
+
+	seq_printf(s, "%s\n", vdev->fw->name);
+	return 0;
+}
+
+static int fw_version_show(struct seq_file *s, void *v)
+{
+	struct ivpu_device *vdev = seq_to_ivpu(s);
+
+	seq_printf(s, "%s\n", vdev->fw->version);
+	return 0;
+}
+
+static int fw_trace_capability_show(struct seq_file *s, void *v)
+{
+	struct ivpu_device *vdev = seq_to_ivpu(s);
+	u64 trace_hw_component_mask;
+	u32 trace_destination_mask;
+	int ret;
+
+	ret = ivpu_jsm_trace_get_capability(vdev, &trace_destination_mask,
+					    &trace_hw_component_mask);
+	if (!ret) {
+		seq_printf(s,
+			   "trace_destination_mask:  %#18x\n"
+			   "trace_hw_component_mask: %#18llx\n",
+			   trace_destination_mask, trace_hw_component_mask);
+	}
+	return 0;
+}
+
+static int fw_trace_config_show(struct seq_file *s, void *v)
+{
+	struct ivpu_device *vdev = seq_to_ivpu(s);
+	/**
+	 * WA: VPU_JSM_MSG_TRACE_GET_CONFIG command is not working yet,
+	 * so we use values from vdev->fw instead of calling ivpu_jsm_trace_get_config()
+	 */
+	u32 trace_level = vdev->fw->trace_level;
+	u32 trace_destination_mask = vdev->fw->trace_destination_mask;
+	u64 trace_hw_component_mask = vdev->fw->trace_hw_component_mask;
+
+	seq_printf(s,
+		   "trace_level:             %#18x\n"
+		   "trace_destination_mask:  %#18x\n"
+		   "trace_hw_component_mask: %#18llx\n",
+		   trace_level, trace_destination_mask, trace_hw_component_mask);
+
+	return 0;
+}
+
+static int last_bootmode_show(struct seq_file *s, void *v)
+{
+	struct ivpu_device *vdev = seq_to_ivpu(s);
+
+	seq_printf(s, "%s\n", (vdev->pm->is_warmboot) ? "warmboot" : "coldboot");
+
+	return 0;
+}
+
+static int reset_counter_show(struct seq_file *s, void *v)
+{
+	struct ivpu_device *vdev = seq_to_ivpu(s);
+
+	seq_printf(s, "%d\n", atomic_read(&vdev->pm->reset_counter));
+	return 0;
+}
+
+static int reset_pending_show(struct seq_file *s, void *v)
+{
+	struct ivpu_device *vdev = seq_to_ivpu(s);
+
+	seq_printf(s, "%d\n", atomic_read(&vdev->pm->reset_pending));
+	return 0;
+}
+
+static int firewall_irq_counter_show(struct seq_file *s, void *v)
+{
+	struct ivpu_device *vdev = seq_to_ivpu(s);
+
+	seq_printf(s, "%d\n", atomic_read(&vdev->hw->firewall_irq_counter));
+	return 0;
+}
+
+static const struct drm_debugfs_info vdev_debugfs_list[] = {
+	{"bo_list", bo_list_show, 0},
+	{"fw_name", fw_name_show, 0},
+	{"fw_version", fw_version_show, 0},
+	{"fw_trace_capability", fw_trace_capability_show, 0},
+	{"fw_trace_config", fw_trace_config_show, 0},
+	{"last_bootmode", last_bootmode_show, 0},
+	{"reset_counter", reset_counter_show, 0},
+	{"reset_pending", reset_pending_show, 0},
+	{"firewall_irq_counter", firewall_irq_counter_show, 0},
+};
+
+static int dvfs_mode_get(void *data, u64 *dvfs_mode)
+{
+	struct ivpu_device *vdev = (struct ivpu_device *)data;
+
+	*dvfs_mode = vdev->fw->dvfs_mode;
+	return 0;
+}
+
+static int dvfs_mode_set(void *data, u64 dvfs_mode)
+{
+	struct ivpu_device *vdev = (struct ivpu_device *)data;
+
+	vdev->fw->dvfs_mode = (u32)dvfs_mode;
+	return pci_try_reset_function(to_pci_dev(vdev->drm.dev));
+}
+
+DEFINE_DEBUGFS_ATTRIBUTE(dvfs_mode_fops, dvfs_mode_get, dvfs_mode_set, "%llu\n");
+
+static ssize_t
+fw_dyndbg_fops_write(struct file *file, const char __user *user_buf, size_t size, loff_t *pos)
+{
+	struct ivpu_device *vdev = file->private_data;
+	char buffer[VPU_DYNDBG_CMD_MAX_LEN] = {};
+	int ret;
+
+	if (size >= VPU_DYNDBG_CMD_MAX_LEN)
+		return -EINVAL;
+
+	ret = strncpy_from_user(buffer, user_buf, size);
+	if (ret < 0)
+		return ret;
+
+	ivpu_jsm_dyndbg_control(vdev, buffer, size);
+	return size;
+}
+
+static const struct file_operations fw_dyndbg_fops = {
+	.owner = THIS_MODULE,
+	.open = simple_open,
+	.write = fw_dyndbg_fops_write,
+};
+
+static int fw_log_show(struct seq_file *s, void *v)
+{
+	struct ivpu_device *vdev = s->private;
+	struct drm_printer p = drm_seq_file_printer(s);
+
+	ivpu_fw_log_print(vdev, true, &p);
+	return 0;
+}
+
+static int fw_log_fops_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, fw_log_show, inode->i_private);
+}
+
+static ssize_t
+fw_log_fops_write(struct file *file, const char __user *user_buf, size_t size, loff_t *pos)
+{
+	struct seq_file *s = file->private_data;
+	struct ivpu_device *vdev = s->private;
+
+	if (!size)
+		return -EINVAL;
+
+	ivpu_fw_log_mark_read(vdev);
+	return size;
+}
+
+static const struct file_operations fw_log_fops = {
+	.owner = THIS_MODULE,
+	.open = fw_log_fops_open,
+	.write = fw_log_fops_write,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+};
+
+static ssize_t
+fw_profiling_freq_fops_write(struct file *file, const char __user *user_buf,
+			     size_t size, loff_t *pos)
+{
+	struct ivpu_device *vdev = file->private_data;
+	bool enable;
+	int ret;
+
+	ret = kstrtobool_from_user(user_buf, size, &enable);
+	if (ret < 0)
+		return ret;
+
+	ivpu_hw_profiling_freq_drive(vdev, enable);
+
+	ret = pci_try_reset_function(to_pci_dev(vdev->drm.dev));
+	if (ret)
+		return ret;
+
+	return size;
+}
+
+static const struct file_operations fw_profiling_freq_fops = {
+	.owner = THIS_MODULE,
+	.open = simple_open,
+	.write = fw_profiling_freq_fops_write,
+};
+
+static ssize_t
+fw_trace_destination_mask_fops_write(struct file *file, const char __user *user_buf,
+				     size_t size, loff_t *pos)
+{
+	struct ivpu_device *vdev = file->private_data;
+	struct ivpu_fw_info *fw = vdev->fw;
+	u32 trace_destination_mask;
+	int ret;
+
+	ret = kstrtou32_from_user(user_buf, size, 0, &trace_destination_mask);
+	if (ret < 0)
+		return ret;
+
+	fw->trace_destination_mask = trace_destination_mask;
+
+	ivpu_jsm_trace_set_config(vdev, fw->trace_level, trace_destination_mask,
+				  fw->trace_hw_component_mask);
+
+	return size;
+}
+
+static const struct file_operations fw_trace_destination_mask_fops = {
+	.owner = THIS_MODULE,
+	.open = simple_open,
+	.write = fw_trace_destination_mask_fops_write,
+};
+
+static ssize_t
+fw_trace_hw_comp_mask_fops_write(struct file *file, const char __user *user_buf,
+				 size_t size, loff_t *pos)
+{
+	struct ivpu_device *vdev = file->private_data;
+	struct ivpu_fw_info *fw = vdev->fw;
+	u64 trace_hw_component_mask;
+	int ret;
+
+	ret = kstrtou64_from_user(user_buf, size, 0, &trace_hw_component_mask);
+	if (ret < 0)
+		return ret;
+
+	fw->trace_hw_component_mask = trace_hw_component_mask;
+
+	ivpu_jsm_trace_set_config(vdev, fw->trace_level, fw->trace_destination_mask,
+				  trace_hw_component_mask);
+
+	return size;
+}
+
+static const struct file_operations fw_trace_hw_comp_mask_fops = {
+	.owner = THIS_MODULE,
+	.open = simple_open,
+	.write = fw_trace_hw_comp_mask_fops_write,
+};
+
+static ssize_t
+fw_trace_level_fops_write(struct file *file, const char __user *user_buf, size_t size, loff_t *pos)
+{
+	struct ivpu_device *vdev = file->private_data;
+	struct ivpu_fw_info *fw = vdev->fw;
+	u32 trace_level;
+	int ret;
+
+	ret = kstrtou32_from_user(user_buf, size, 0, &trace_level);
+	if (ret < 0)
+		return ret;
+
+	fw->trace_level = trace_level;
+
+	ivpu_jsm_trace_set_config(vdev, trace_level, fw->trace_destination_mask,
+				  fw->trace_hw_component_mask);
+
+	return size;
+}
+
+static const struct file_operations fw_trace_level_fops = {
+	.owner = THIS_MODULE,
+	.open = simple_open,
+	.write = fw_trace_level_fops_write,
+};
+
+static ssize_t
+ivpu_force_recovery_fn(struct file *file, const char __user *user_buf, size_t size, loff_t *pos)
+{
+	struct ivpu_device *vdev = file->private_data;
+	int ret;
+
+	if (!size)
+		return -EINVAL;
+
+	ret = ivpu_rpm_get(vdev);
+	if (ret < 0)
+		return ret;
+
+	ivpu_pm_trigger_recovery(vdev, "debugfs");
+	flush_work(&vdev->pm->recovery_work);
+	ivpu_rpm_put(vdev);
+	return size;
+}
+
+static const struct file_operations ivpu_force_recovery_fops = {
+	.owner = THIS_MODULE,
+	.open = simple_open,
+	.write = ivpu_force_recovery_fn,
+};
+
+static int ivpu_reset_engine_fn(void *data, u64 val)
+{
+	struct ivpu_device *vdev = (struct ivpu_device *)data;
+
+	return ivpu_jsm_reset_engine(vdev, (u32)val);
+}
+
+DEFINE_DEBUGFS_ATTRIBUTE(ivpu_reset_engine_fops, NULL, ivpu_reset_engine_fn, "0x%02llx\n");
+
+static int ivpu_resume_engine_fn(void *data, u64 val)
+{
+	struct ivpu_device *vdev = (struct ivpu_device *)data;
+
+	return ivpu_jsm_hws_resume_engine(vdev, (u32)val);
+}
+
+DEFINE_DEBUGFS_ATTRIBUTE(ivpu_resume_engine_fops, NULL, ivpu_resume_engine_fn, "0x%02llx\n");
+
+static int dct_active_get(void *data, u64 *active_percent)
+{
+	struct ivpu_device *vdev = data;
+
+	*active_percent = vdev->pm->dct_active_percent;
+
+	return 0;
+}
+
+static int dct_active_set(void *data, u64 active_percent)
+{
+	struct ivpu_device *vdev = data;
+	int ret;
+
+	if (active_percent > 100)
+		return -EINVAL;
+
+	ret = ivpu_rpm_get(vdev);
+	if (ret < 0)
+		return ret;
+
+	if (active_percent)
+		ret = ivpu_pm_dct_enable(vdev, active_percent);
+	else
+		ret = ivpu_pm_dct_disable(vdev);
+
+	ivpu_rpm_put(vdev);
+
+	return ret;
+}
+
+DEFINE_DEBUGFS_ATTRIBUTE(ivpu_dct_fops, dct_active_get, dct_active_set, "%llu\n");
+
+static void print_priority_band(struct seq_file *s, struct ivpu_hw_info *hw,
+				int band, const char *name)
+{
+	seq_printf(s, "%-9s: grace_period %9u process_grace_period %9u process_quantum %9u\n",
+		   name,
+		   hw->hws.grace_period[band],
+		   hw->hws.process_grace_period[band],
+		   hw->hws.process_quantum[band]);
+}
+
+static int priority_bands_show(struct seq_file *s, void *v)
+{
+	struct ivpu_device *vdev = s->private;
+	struct ivpu_hw_info *hw = vdev->hw;
+
+	print_priority_band(s, hw, VPU_JOB_SCHEDULING_PRIORITY_BAND_IDLE, "Idle");
+	print_priority_band(s, hw, VPU_JOB_SCHEDULING_PRIORITY_BAND_NORMAL, "Normal");
+	print_priority_band(s, hw, VPU_JOB_SCHEDULING_PRIORITY_BAND_FOCUS, "Focus");
+	print_priority_band(s, hw, VPU_JOB_SCHEDULING_PRIORITY_BAND_REALTIME, "Realtime");
+
+	return 0;
+}
+
+static int priority_bands_fops_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, priority_bands_show, inode->i_private);
+}
+
+static ssize_t
+priority_bands_fops_write(struct file *file, const char __user *user_buf, size_t size, loff_t *pos)
+{
+	struct seq_file *s = file->private_data;
+	struct ivpu_device *vdev = s->private;
+	char buf[64];
+	u32 grace_period;
+	u32 process_grace_period;
+	u32 process_quantum;
+	u32 band;
+	int ret;
+
+	if (size >= sizeof(buf))
+		return -EINVAL;
+
+	ret = simple_write_to_buffer(buf, sizeof(buf) - 1, pos, user_buf, size);
+	if (ret < 0)
+		return ret;
+
+	buf[ret] = '\0';
+	ret = sscanf(buf, "%u %u %u %u", &band, &grace_period, &process_grace_period,
+		     &process_quantum);
+	if (ret != 4)
+		return -EINVAL;
+
+	if (band >= VPU_JOB_SCHEDULING_PRIORITY_BAND_COUNT)
+		return -EINVAL;
+
+	vdev->hw->hws.grace_period[band] = grace_period;
+	vdev->hw->hws.process_grace_period[band] = process_grace_period;
+	vdev->hw->hws.process_quantum[band] = process_quantum;
+
+	return size;
+}
+
+static const struct file_operations ivpu_hws_priority_bands_fops = {
+	.owner = THIS_MODULE,
+	.open = priority_bands_fops_open,
+	.write = priority_bands_fops_write,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+};
+
+void ivpu_debugfs_init(struct ivpu_device *vdev)
+{
+	struct dentry *debugfs_root = vdev->drm.debugfs_root;
+
+	drm_debugfs_add_files(&vdev->drm, vdev_debugfs_list, ARRAY_SIZE(vdev_debugfs_list));
+
+	debugfs_create_file("force_recovery", 0200, debugfs_root, vdev,
+			    &ivpu_force_recovery_fops);
+
+	debugfs_create_file("dvfs_mode", 0644, debugfs_root, vdev,
+			    &dvfs_mode_fops);
+
+	debugfs_create_file("fw_dyndbg", 0200, debugfs_root, vdev,
+			    &fw_dyndbg_fops);
+	debugfs_create_file("fw_log", 0644, debugfs_root, vdev,
+			    &fw_log_fops);
+	debugfs_create_file("fw_trace_destination_mask", 0200, debugfs_root, vdev,
+			    &fw_trace_destination_mask_fops);
+	debugfs_create_file("fw_trace_hw_comp_mask", 0200, debugfs_root, vdev,
+			    &fw_trace_hw_comp_mask_fops);
+	debugfs_create_file("fw_trace_level", 0200, debugfs_root, vdev,
+			    &fw_trace_level_fops);
+	debugfs_create_file("hws_priority_bands", 0200, debugfs_root, vdev,
+			    &ivpu_hws_priority_bands_fops);
+
+	debugfs_create_file("reset_engine", 0200, debugfs_root, vdev,
+			    &ivpu_reset_engine_fops);
+	debugfs_create_file("resume_engine", 0200, debugfs_root, vdev,
+			    &ivpu_resume_engine_fops);
+
+	if (ivpu_hw_ip_gen(vdev) >= IVPU_HW_IP_40XX) {
+		debugfs_create_file("fw_profiling_freq_drive", 0200,
+				    debugfs_root, vdev, &fw_profiling_freq_fops);
+		debugfs_create_file("dct", 0644, debugfs_root, vdev, &ivpu_dct_fops);
+	}
+
+#ifdef CONFIG_FAULT_INJECTION
+	fault_create_debugfs_attr("fail_hw", debugfs_root, &ivpu_hw_failure);
+#endif
+}
diff --git a/drivers/accel/ivpu/ivpu_debugfs.h b/drivers/accel/ivpu/ivpu_debugfs.h
new file mode 100644
index 000000000000..49ae9ea78287
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_debugfs.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2020-2023 Intel Corporation
+ */
+
+#ifndef __IVPU_DEBUGFS_H__
+#define __IVPU_DEBUGFS_H__
+
+struct ivpu_device;
+
+#if defined(CONFIG_DEBUG_FS)
+void ivpu_debugfs_init(struct ivpu_device *vdev);
+#else
+static inline void ivpu_debugfs_init(struct ivpu_device *vdev) { }
+#endif
+
+#endif /* __IVPU_DEBUGFS_H__ */
diff --git a/drivers/accel/ivpu/ivpu_drv.c b/drivers/accel/ivpu/ivpu_drv.c
new file mode 100644
index 000000000000..3d6fccdefdd6
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_drv.c
@@ -0,0 +1,785 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020-2025 Intel Corporation
+ */
+
+#include <linux/firmware.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/pm_runtime.h>
+#include <linux/workqueue.h>
+#include <generated/utsrelease.h>
+
+#include <drm/drm_accel.h>
+#include <drm/drm_file.h>
+#include <drm/drm_gem.h>
+#include <drm/drm_ioctl.h>
+#include <drm/drm_prime.h>
+
+#include "ivpu_coredump.h"
+#include "ivpu_debugfs.h"
+#include "ivpu_drv.h"
+#include "ivpu_fw.h"
+#include "ivpu_fw_log.h"
+#include "ivpu_gem.h"
+#include "ivpu_hw.h"
+#include "ivpu_ipc.h"
+#include "ivpu_job.h"
+#include "ivpu_jsm_msg.h"
+#include "ivpu_mmu.h"
+#include "ivpu_mmu_context.h"
+#include "ivpu_ms.h"
+#include "ivpu_pm.h"
+#include "ivpu_sysfs.h"
+#include "vpu_boot_api.h"
+
+#ifndef DRIVER_VERSION_STR
+#define DRIVER_VERSION_STR "1.0.0 " UTS_RELEASE
+#endif
+
+int ivpu_dbg_mask;
+module_param_named(dbg_mask, ivpu_dbg_mask, int, 0644);
+MODULE_PARM_DESC(dbg_mask, "Driver debug mask. See IVPU_DBG_* macros.");
+
+int ivpu_test_mode;
+#if IS_ENABLED(CONFIG_DRM_ACCEL_IVPU_DEBUG)
+module_param_named_unsafe(test_mode, ivpu_test_mode, int, 0644);
+MODULE_PARM_DESC(test_mode, "Test mode mask. See IVPU_TEST_MODE_* macros.");
+#endif
+
+u8 ivpu_pll_min_ratio;
+module_param_named(pll_min_ratio, ivpu_pll_min_ratio, byte, 0644);
+MODULE_PARM_DESC(pll_min_ratio, "Minimum PLL ratio used to set NPU frequency");
+
+u8 ivpu_pll_max_ratio = U8_MAX;
+module_param_named(pll_max_ratio, ivpu_pll_max_ratio, byte, 0644);
+MODULE_PARM_DESC(pll_max_ratio, "Maximum PLL ratio used to set NPU frequency");
+
+int ivpu_sched_mode = IVPU_SCHED_MODE_AUTO;
+module_param_named(sched_mode, ivpu_sched_mode, int, 0444);
+MODULE_PARM_DESC(sched_mode, "Scheduler mode: -1 - Use default scheduler, 0 - Use OS scheduler (supported on 27XX - 50XX), 1 - Use HW scheduler");
+
+bool ivpu_disable_mmu_cont_pages;
+module_param_named(disable_mmu_cont_pages, ivpu_disable_mmu_cont_pages, bool, 0444);
+MODULE_PARM_DESC(disable_mmu_cont_pages, "Disable MMU contiguous pages optimization");
+
+bool ivpu_force_snoop;
+module_param_named(force_snoop, ivpu_force_snoop, bool, 0444);
+MODULE_PARM_DESC(force_snoop, "Force snooping for NPU host memory access");
+
+struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv)
+{
+	struct ivpu_device *vdev = file_priv->vdev;
+
+	kref_get(&file_priv->ref);
+
+	ivpu_dbg(vdev, KREF, "file_priv get: ctx %u refcount %u\n",
+		 file_priv->ctx.id, kref_read(&file_priv->ref));
+
+	return file_priv;
+}
+
+static void file_priv_unbind(struct ivpu_device *vdev, struct ivpu_file_priv *file_priv)
+{
+	mutex_lock(&file_priv->lock);
+	if (file_priv->bound) {
+		ivpu_dbg(vdev, FILE, "file_priv unbind: ctx %u\n", file_priv->ctx.id);
+
+		ivpu_cmdq_release_all_locked(file_priv);
+		ivpu_bo_unbind_all_bos_from_context(vdev, &file_priv->ctx);
+		ivpu_mmu_context_fini(vdev, &file_priv->ctx);
+		file_priv->bound = false;
+		drm_WARN_ON(&vdev->drm, !xa_erase_irq(&vdev->context_xa, file_priv->ctx.id));
+	}
+	mutex_unlock(&file_priv->lock);
+}
+
+static void file_priv_release(struct kref *ref)
+{
+	struct ivpu_file_priv *file_priv = container_of(ref, struct ivpu_file_priv, ref);
+	struct ivpu_device *vdev = file_priv->vdev;
+
+	ivpu_dbg(vdev, FILE, "file_priv release: ctx %u bound %d\n",
+		 file_priv->ctx.id, (bool)file_priv->bound);
+
+	pm_runtime_get_sync(vdev->drm.dev);
+	mutex_lock(&vdev->context_list_lock);
+	file_priv_unbind(vdev, file_priv);
+	drm_WARN_ON(&vdev->drm, !xa_empty(&file_priv->cmdq_xa));
+	xa_destroy(&file_priv->cmdq_xa);
+	mutex_unlock(&vdev->context_list_lock);
+	pm_runtime_put_autosuspend(vdev->drm.dev);
+
+	mutex_destroy(&file_priv->ms_lock);
+	mutex_destroy(&file_priv->lock);
+	kfree(file_priv);
+}
+
+void ivpu_file_priv_put(struct ivpu_file_priv **link)
+{
+	struct ivpu_file_priv *file_priv = *link;
+	struct ivpu_device *vdev = file_priv->vdev;
+
+	ivpu_dbg(vdev, KREF, "file_priv put: ctx %u refcount %u\n",
+		 file_priv->ctx.id, kref_read(&file_priv->ref));
+
+	*link = NULL;
+	kref_put(&file_priv->ref, file_priv_release);
+}
+
+bool ivpu_is_capable(struct ivpu_device *vdev, u32 capability)
+{
+	switch (capability) {
+	case DRM_IVPU_CAP_METRIC_STREAMER:
+		return true;
+	case DRM_IVPU_CAP_DMA_MEMORY_RANGE:
+		return true;
+	case DRM_IVPU_CAP_BO_CREATE_FROM_USERPTR:
+		return true;
+	case DRM_IVPU_CAP_MANAGE_CMDQ:
+		return vdev->fw->sched_mode == VPU_SCHEDULING_MODE_HW;
+	default:
+		return false;
+	}
+}
+
+static int ivpu_get_param_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
+{
+	struct ivpu_file_priv *file_priv = file->driver_priv;
+	struct ivpu_device *vdev = file_priv->vdev;
+	struct pci_dev *pdev = to_pci_dev(vdev->drm.dev);
+	struct drm_ivpu_param *args = data;
+	int ret = 0;
+	int idx;
+
+	if (!drm_dev_enter(dev, &idx))
+		return -ENODEV;
+
+	switch (args->param) {
+	case DRM_IVPU_PARAM_DEVICE_ID:
+		args->value = pdev->device;
+		break;
+	case DRM_IVPU_PARAM_DEVICE_REVISION:
+		args->value = pdev->revision;
+		break;
+	case DRM_IVPU_PARAM_PLATFORM_TYPE:
+		args->value = vdev->platform;
+		break;
+	case DRM_IVPU_PARAM_CORE_CLOCK_RATE:
+		args->value = ivpu_hw_dpu_max_freq_get(vdev);
+		break;
+	case DRM_IVPU_PARAM_NUM_CONTEXTS:
+		args->value = ivpu_get_context_count(vdev);
+		break;
+	case DRM_IVPU_PARAM_CONTEXT_BASE_ADDRESS:
+		args->value = vdev->hw->ranges.user.start;
+		break;
+	case DRM_IVPU_PARAM_CONTEXT_ID:
+		args->value = file_priv->ctx.id;
+		break;
+	case DRM_IVPU_PARAM_FW_API_VERSION:
+		if (args->index < VPU_FW_API_VER_NUM) {
+			struct vpu_firmware_header *fw_hdr;
+
+			fw_hdr = (struct vpu_firmware_header *)vdev->fw->file->data;
+			args->value = fw_hdr->api_version[args->index];
+		} else {
+			ret = -EINVAL;
+		}
+		break;
+	case DRM_IVPU_PARAM_ENGINE_HEARTBEAT:
+		ret = ivpu_jsm_get_heartbeat(vdev, args->index, &args->value);
+		break;
+	case DRM_IVPU_PARAM_UNIQUE_INFERENCE_ID:
+		args->value = (u64)atomic64_inc_return(&vdev->unique_id_counter);
+		break;
+	case DRM_IVPU_PARAM_TILE_CONFIG:
+		args->value = vdev->hw->tile_fuse;
+		break;
+	case DRM_IVPU_PARAM_SKU:
+		args->value = vdev->hw->sku;
+		break;
+	case DRM_IVPU_PARAM_CAPABILITIES:
+		args->value = ivpu_is_capable(vdev, args->index);
+		break;
+	case DRM_IVPU_PARAM_PREEMPT_BUFFER_SIZE:
+		args->value = ivpu_fw_preempt_buf_size(vdev);
+		break;
+	default:
+		ret = -EINVAL;
+		break;
+	}
+
+	drm_dev_exit(idx);
+	return ret;
+}
+
+static int ivpu_set_param_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
+{
+	struct drm_ivpu_param *args = data;
+	int ret = 0;
+
+	switch (args->param) {
+	default:
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static int ivpu_open(struct drm_device *dev, struct drm_file *file)
+{
+	struct ivpu_device *vdev = to_ivpu_device(dev);
+	struct ivpu_file_priv *file_priv;
+	u32 ctx_id;
+	int idx, ret;
+
+	if (!drm_dev_enter(dev, &idx))
+		return -ENODEV;
+
+	file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
+	if (!file_priv) {
+		ret = -ENOMEM;
+		goto err_dev_exit;
+	}
+
+	INIT_LIST_HEAD(&file_priv->ms_instance_list);
+
+	file_priv->vdev = vdev;
+	file_priv->bound = true;
+	kref_init(&file_priv->ref);
+	mutex_init(&file_priv->lock);
+	mutex_init(&file_priv->ms_lock);
+
+	mutex_lock(&vdev->context_list_lock);
+
+	ret = xa_alloc_irq(&vdev->context_xa, &ctx_id, file_priv,
+			   vdev->context_xa_limit, GFP_KERNEL);
+	if (ret) {
+		ivpu_err(vdev, "Failed to allocate context id: %d\n", ret);
+		goto err_unlock;
+	}
+
+	ivpu_mmu_context_init(vdev, &file_priv->ctx, ctx_id);
+
+	file_priv->job_limit.min = FIELD_PREP(IVPU_JOB_ID_CONTEXT_MASK, (file_priv->ctx.id - 1));
+	file_priv->job_limit.max = file_priv->job_limit.min | IVPU_JOB_ID_JOB_MASK;
+
+	xa_init_flags(&file_priv->cmdq_xa, XA_FLAGS_ALLOC1);
+	file_priv->cmdq_limit.min = IVPU_CMDQ_MIN_ID;
+	file_priv->cmdq_limit.max = IVPU_CMDQ_MAX_ID;
+
+	mutex_unlock(&vdev->context_list_lock);
+	drm_dev_exit(idx);
+
+	file->driver_priv = file_priv;
+
+	ivpu_dbg(vdev, FILE, "file_priv create: ctx %u process %s pid %d\n",
+		 ctx_id, current->comm, task_pid_nr(current));
+
+	return 0;
+
+err_unlock:
+	mutex_unlock(&vdev->context_list_lock);
+	mutex_destroy(&file_priv->ms_lock);
+	mutex_destroy(&file_priv->lock);
+	kfree(file_priv);
+err_dev_exit:
+	drm_dev_exit(idx);
+	return ret;
+}
+
+static void ivpu_postclose(struct drm_device *dev, struct drm_file *file)
+{
+	struct ivpu_file_priv *file_priv = file->driver_priv;
+	struct ivpu_device *vdev = to_ivpu_device(dev);
+
+	ivpu_dbg(vdev, FILE, "file_priv close: ctx %u process %s pid %d\n",
+		 file_priv->ctx.id, current->comm, task_pid_nr(current));
+
+	ivpu_ms_cleanup(file_priv);
+	ivpu_file_priv_put(&file_priv);
+}
+
+static const struct drm_ioctl_desc ivpu_drm_ioctls[] = {
+	DRM_IOCTL_DEF_DRV(IVPU_GET_PARAM, ivpu_get_param_ioctl, 0),
+	DRM_IOCTL_DEF_DRV(IVPU_SET_PARAM, ivpu_set_param_ioctl, 0),
+	DRM_IOCTL_DEF_DRV(IVPU_BO_CREATE, ivpu_bo_create_ioctl, 0),
+	DRM_IOCTL_DEF_DRV(IVPU_BO_INFO, ivpu_bo_info_ioctl, 0),
+	DRM_IOCTL_DEF_DRV(IVPU_SUBMIT, ivpu_submit_ioctl, 0),
+	DRM_IOCTL_DEF_DRV(IVPU_BO_WAIT, ivpu_bo_wait_ioctl, 0),
+	DRM_IOCTL_DEF_DRV(IVPU_METRIC_STREAMER_START, ivpu_ms_start_ioctl, 0),
+	DRM_IOCTL_DEF_DRV(IVPU_METRIC_STREAMER_GET_DATA, ivpu_ms_get_data_ioctl, 0),
+	DRM_IOCTL_DEF_DRV(IVPU_METRIC_STREAMER_STOP, ivpu_ms_stop_ioctl, 0),
+	DRM_IOCTL_DEF_DRV(IVPU_METRIC_STREAMER_GET_INFO, ivpu_ms_get_info_ioctl, 0),
+	DRM_IOCTL_DEF_DRV(IVPU_CMDQ_CREATE, ivpu_cmdq_create_ioctl, 0),
+	DRM_IOCTL_DEF_DRV(IVPU_CMDQ_DESTROY, ivpu_cmdq_destroy_ioctl, 0),
+	DRM_IOCTL_DEF_DRV(IVPU_CMDQ_SUBMIT, ivpu_cmdq_submit_ioctl, 0),
+	DRM_IOCTL_DEF_DRV(IVPU_BO_CREATE_FROM_USERPTR, ivpu_bo_create_from_userptr_ioctl, 0),
+};
+
+static int ivpu_wait_for_ready(struct ivpu_device *vdev)
+{
+	struct ivpu_ipc_consumer cons;
+	struct ivpu_ipc_hdr ipc_hdr;
+	unsigned long timeout;
+	int ret;
+
+	if (ivpu_test_mode & IVPU_TEST_MODE_FW_TEST)
+		return 0;
+
+	ivpu_ipc_consumer_add(vdev, &cons, IVPU_IPC_CHAN_BOOT_MSG, NULL);
+
+	timeout = jiffies + msecs_to_jiffies(vdev->timeout.boot);
+	while (1) {
+		ivpu_ipc_irq_handler(vdev);
+		ret = ivpu_ipc_receive(vdev, &cons, &ipc_hdr, NULL, 0);
+		if (ret != -ETIMEDOUT || time_after_eq(jiffies, timeout))
+			break;
+
+		cond_resched();
+	}
+
+	ivpu_ipc_consumer_del(vdev, &cons);
+
+	if (!ret && ipc_hdr.data_addr != IVPU_IPC_BOOT_MSG_DATA_ADDR) {
+		ivpu_err(vdev, "Invalid NPU ready message: 0x%x\n",
+			 ipc_hdr.data_addr);
+		return -EIO;
+	}
+
+	if (!ret)
+		ivpu_dbg(vdev, PM, "NPU ready message received successfully\n");
+
+	return ret;
+}
+
+static int ivpu_hw_sched_init(struct ivpu_device *vdev)
+{
+	int ret = 0;
+
+	if (vdev->fw->sched_mode == VPU_SCHEDULING_MODE_HW) {
+		ret = ivpu_jsm_hws_setup_priority_bands(vdev);
+		if (ret) {
+			ivpu_err(vdev, "Failed to enable hw scheduler: %d", ret);
+			return ret;
+		}
+	}
+
+	return ret;
+}
+
+/**
+ * ivpu_boot() - Start VPU firmware
+ * @vdev: VPU device
+ *
+ * This function is paired with ivpu_shutdown() but it doesn't power up the
+ * VPU because power up has to be called very early in ivpu_probe().
+ */
+int ivpu_boot(struct ivpu_device *vdev)
+{
+	int ret;
+
+	drm_WARN_ON(&vdev->drm, atomic_read(&vdev->job_timeout_counter));
+	drm_WARN_ON(&vdev->drm, !xa_empty(&vdev->submitted_jobs_xa));
+
+	ivpu_fw_boot_params_setup(vdev, ivpu_bo_vaddr(vdev->fw->mem_bp));
+
+	ret = ivpu_hw_boot_fw(vdev);
+	if (ret) {
+		ivpu_err(vdev, "Failed to start the firmware: %d\n", ret);
+		return ret;
+	}
+
+	ret = ivpu_wait_for_ready(vdev);
+	if (ret) {
+		ivpu_err(vdev, "Failed to boot the firmware: %d\n", ret);
+		goto err_diagnose_failure;
+	}
+
+	ivpu_hw_irq_clear(vdev);
+	enable_irq(vdev->irq);
+	ivpu_hw_irq_enable(vdev);
+	ivpu_ipc_enable(vdev);
+
+	if (ivpu_fw_is_cold_boot(vdev)) {
+		ret = ivpu_pm_dct_init(vdev);
+		if (ret)
+			goto err_disable_ipc;
+
+		ret = ivpu_hw_sched_init(vdev);
+		if (ret)
+			goto err_disable_ipc;
+	}
+
+	return 0;
+
+err_disable_ipc:
+	ivpu_ipc_disable(vdev);
+	ivpu_hw_irq_disable(vdev);
+	disable_irq(vdev->irq);
+err_diagnose_failure:
+	ivpu_hw_diagnose_failure(vdev);
+	ivpu_mmu_evtq_dump(vdev);
+	ivpu_dev_coredump(vdev);
+	return ret;
+}
+
+void ivpu_prepare_for_reset(struct ivpu_device *vdev)
+{
+	ivpu_hw_irq_disable(vdev);
+	disable_irq(vdev->irq);
+	flush_work(&vdev->irq_ipc_work);
+	flush_work(&vdev->irq_dct_work);
+	flush_work(&vdev->context_abort_work);
+	ivpu_ipc_disable(vdev);
+	ivpu_mmu_disable(vdev);
+}
+
+int ivpu_shutdown(struct ivpu_device *vdev)
+{
+	int ret;
+
+	/* Save PCI state before powering down as it sometimes gets corrupted if NPU hangs */
+	pci_save_state(to_pci_dev(vdev->drm.dev));
+
+	ret = ivpu_hw_power_down(vdev);
+	if (ret)
+		ivpu_warn(vdev, "Failed to power down HW: %d\n", ret);
+
+	pci_set_power_state(to_pci_dev(vdev->drm.dev), PCI_D3hot);
+
+	return ret;
+}
+
+static const struct file_operations ivpu_fops = {
+	.owner		= THIS_MODULE,
+	DRM_ACCEL_FOPS,
+#ifdef CONFIG_PROC_FS
+	.show_fdinfo = drm_show_fdinfo,
+#endif
+};
+
+static const struct drm_driver driver = {
+	.driver_features = DRIVER_GEM | DRIVER_COMPUTE_ACCEL,
+
+	.open = ivpu_open,
+	.postclose = ivpu_postclose,
+
+	.gem_create_object = ivpu_gem_create_object,
+	.gem_prime_import = ivpu_gem_prime_import,
+
+	.ioctls = ivpu_drm_ioctls,
+	.num_ioctls = ARRAY_SIZE(ivpu_drm_ioctls),
+	.fops = &ivpu_fops,
+#ifdef CONFIG_PROC_FS
+	.show_fdinfo = drm_show_memory_stats,
+#endif
+
+	.name = DRIVER_NAME,
+	.desc = DRIVER_DESC,
+
+	.major = 1,
+};
+
+static int ivpu_irq_init(struct ivpu_device *vdev)
+{
+	struct pci_dev *pdev = to_pci_dev(vdev->drm.dev);
+	int ret;
+
+	ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI | PCI_IRQ_MSIX);
+	if (ret < 0) {
+		ivpu_err(vdev, "Failed to allocate a MSI IRQ: %d\n", ret);
+		return ret;
+	}
+
+	INIT_WORK(&vdev->irq_ipc_work, ivpu_ipc_irq_work_fn);
+	INIT_WORK(&vdev->irq_dct_work, ivpu_pm_irq_dct_work_fn);
+	INIT_WORK(&vdev->context_abort_work, ivpu_context_abort_work_fn);
+
+	ivpu_irq_handlers_init(vdev);
+
+	vdev->irq = pci_irq_vector(pdev, 0);
+
+	ret = devm_request_irq(vdev->drm.dev, vdev->irq, ivpu_hw_irq_handler,
+			       IRQF_NO_AUTOEN, DRIVER_NAME, vdev);
+	if (ret)
+		ivpu_err(vdev, "Failed to request an IRQ %d\n", ret);
+
+	return ret;
+}
+
+static int ivpu_pci_init(struct ivpu_device *vdev)
+{
+	struct pci_dev *pdev = to_pci_dev(vdev->drm.dev);
+	struct resource *bar0 = &pdev->resource[0];
+	struct resource *bar4 = &pdev->resource[4];
+	int ret;
+
+	ivpu_dbg(vdev, MISC, "Mapping BAR0 (RegV) %pR\n", bar0);
+	vdev->regv = devm_ioremap_resource(vdev->drm.dev, bar0);
+	if (IS_ERR(vdev->regv)) {
+		ivpu_err(vdev, "Failed to map bar 0: %pe\n", vdev->regv);
+		return PTR_ERR(vdev->regv);
+	}
+
+	ivpu_dbg(vdev, MISC, "Mapping BAR4 (RegB) %pR\n", bar4);
+	vdev->regb = devm_ioremap_resource(vdev->drm.dev, bar4);
+	if (IS_ERR(vdev->regb)) {
+		ivpu_err(vdev, "Failed to map bar 4: %pe\n", vdev->regb);
+		return PTR_ERR(vdev->regb);
+	}
+
+	ret = dma_set_mask_and_coherent(vdev->drm.dev, DMA_BIT_MASK(vdev->hw->dma_bits));
+	if (ret) {
+		ivpu_err(vdev, "Failed to set DMA mask: %d\n", ret);
+		return ret;
+	}
+	dma_set_max_seg_size(vdev->drm.dev, UINT_MAX);
+
+	/* Clear any pending errors */
+	pcie_capability_clear_word(pdev, PCI_EXP_DEVSTA, 0x3f);
+
+	/* NPU does not require 10m D3hot delay */
+	pdev->d3hot_delay = 0;
+
+	ret = pcim_enable_device(pdev);
+	if (ret) {
+		ivpu_err(vdev, "Failed to enable PCI device: %d\n", ret);
+		return ret;
+	}
+
+	pci_set_master(pdev);
+
+	return 0;
+}
+
+static int ivpu_dev_init(struct ivpu_device *vdev)
+{
+	int ret;
+
+	vdev->hw = drmm_kzalloc(&vdev->drm, sizeof(*vdev->hw), GFP_KERNEL);
+	if (!vdev->hw)
+		return -ENOMEM;
+
+	vdev->mmu = drmm_kzalloc(&vdev->drm, sizeof(*vdev->mmu), GFP_KERNEL);
+	if (!vdev->mmu)
+		return -ENOMEM;
+
+	vdev->fw = drmm_kzalloc(&vdev->drm, sizeof(*vdev->fw), GFP_KERNEL);
+	if (!vdev->fw)
+		return -ENOMEM;
+
+	vdev->ipc = drmm_kzalloc(&vdev->drm, sizeof(*vdev->ipc), GFP_KERNEL);
+	if (!vdev->ipc)
+		return -ENOMEM;
+
+	vdev->pm = drmm_kzalloc(&vdev->drm, sizeof(*vdev->pm), GFP_KERNEL);
+	if (!vdev->pm)
+		return -ENOMEM;
+
+	if (ivpu_hw_ip_gen(vdev) >= IVPU_HW_IP_40XX)
+		vdev->hw->dma_bits = 48;
+	else
+		vdev->hw->dma_bits = 38;
+
+	vdev->platform = IVPU_PLATFORM_INVALID;
+	vdev->context_xa_limit.min = IVPU_USER_CONTEXT_MIN_SSID;
+	vdev->context_xa_limit.max = IVPU_USER_CONTEXT_MAX_SSID;
+	atomic64_set(&vdev->unique_id_counter, 0);
+	atomic_set(&vdev->job_timeout_counter, 0);
+	xa_init_flags(&vdev->context_xa, XA_FLAGS_ALLOC | XA_FLAGS_LOCK_IRQ);
+	xa_init_flags(&vdev->submitted_jobs_xa, XA_FLAGS_ALLOC1);
+	xa_init_flags(&vdev->db_xa, XA_FLAGS_ALLOC1);
+	INIT_LIST_HEAD(&vdev->bo_list);
+
+	vdev->db_limit.min = IVPU_MIN_DB;
+	vdev->db_limit.max = IVPU_MAX_DB;
+
+	ret = drmm_mutex_init(&vdev->drm, &vdev->context_list_lock);
+	if (ret)
+		goto err_xa_destroy;
+
+	ret = drmm_mutex_init(&vdev->drm, &vdev->submitted_jobs_lock);
+	if (ret)
+		goto err_xa_destroy;
+
+	ret = drmm_mutex_init(&vdev->drm, &vdev->bo_list_lock);
+	if (ret)
+		goto err_xa_destroy;
+
+	ret = ivpu_pci_init(vdev);
+	if (ret)
+		goto err_xa_destroy;
+
+	ret = ivpu_irq_init(vdev);
+	if (ret)
+		goto err_xa_destroy;
+
+	/* Init basic HW info based on buttress registers which are accessible before power up */
+	ret = ivpu_hw_init(vdev);
+	if (ret)
+		goto err_xa_destroy;
+
+	/* Power up early so the rest of init code can access VPU registers */
+	ret = ivpu_hw_power_up(vdev);
+	if (ret)
+		goto err_shutdown;
+
+	ivpu_mmu_global_context_init(vdev);
+
+	ret = ivpu_mmu_init(vdev);
+	if (ret)
+		goto err_mmu_gctx_fini;
+
+	ret = ivpu_mmu_reserved_context_init(vdev);
+	if (ret)
+		goto err_mmu_gctx_fini;
+
+	ret = ivpu_fw_init(vdev);
+	if (ret)
+		goto err_mmu_rctx_fini;
+
+	ret = ivpu_ipc_init(vdev);
+	if (ret)
+		goto err_fw_fini;
+
+	ivpu_pm_init(vdev);
+
+	ret = ivpu_boot(vdev);
+	if (ret)
+		goto err_ipc_fini;
+
+	ivpu_job_done_consumer_init(vdev);
+	ivpu_pm_enable(vdev);
+
+	return 0;
+
+err_ipc_fini:
+	ivpu_ipc_fini(vdev);
+err_fw_fini:
+	ivpu_fw_fini(vdev);
+err_mmu_rctx_fini:
+	ivpu_mmu_reserved_context_fini(vdev);
+err_mmu_gctx_fini:
+	ivpu_mmu_global_context_fini(vdev);
+err_shutdown:
+	ivpu_shutdown(vdev);
+err_xa_destroy:
+	xa_destroy(&vdev->db_xa);
+	xa_destroy(&vdev->submitted_jobs_xa);
+	xa_destroy(&vdev->context_xa);
+	return ret;
+}
+
+static void ivpu_bo_unbind_all_user_contexts(struct ivpu_device *vdev)
+{
+	struct ivpu_file_priv *file_priv;
+	unsigned long ctx_id;
+
+	mutex_lock(&vdev->context_list_lock);
+
+	xa_for_each(&vdev->context_xa, ctx_id, file_priv)
+		file_priv_unbind(vdev, file_priv);
+
+	mutex_unlock(&vdev->context_list_lock);
+}
+
+static void ivpu_dev_fini(struct ivpu_device *vdev)
+{
+	ivpu_jobs_abort_all(vdev);
+	ivpu_pm_disable_recovery(vdev);
+	ivpu_pm_disable(vdev);
+	ivpu_prepare_for_reset(vdev);
+	ivpu_shutdown(vdev);
+
+	ivpu_ms_cleanup_all(vdev);
+	ivpu_job_done_consumer_fini(vdev);
+	ivpu_bo_unbind_all_user_contexts(vdev);
+
+	ivpu_ipc_fini(vdev);
+	ivpu_fw_fini(vdev);
+	ivpu_mmu_reserved_context_fini(vdev);
+	ivpu_mmu_global_context_fini(vdev);
+
+	drm_WARN_ON(&vdev->drm, !xa_empty(&vdev->db_xa));
+	xa_destroy(&vdev->db_xa);
+	drm_WARN_ON(&vdev->drm, !xa_empty(&vdev->submitted_jobs_xa));
+	xa_destroy(&vdev->submitted_jobs_xa);
+	drm_WARN_ON(&vdev->drm, !xa_empty(&vdev->context_xa));
+	xa_destroy(&vdev->context_xa);
+}
+
+static struct pci_device_id ivpu_pci_ids[] = {
+	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_MTL) },
+	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_ARL) },
+	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_LNL) },
+	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_PTL_P) },
+	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_WCL) },
+	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_NVL) },
+	{ }
+};
+MODULE_DEVICE_TABLE(pci, ivpu_pci_ids);
+
+static int ivpu_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+{
+	struct ivpu_device *vdev;
+	int ret;
+
+	vdev = devm_drm_dev_alloc(&pdev->dev, &driver, struct ivpu_device, drm);
+	if (IS_ERR(vdev))
+		return PTR_ERR(vdev);
+
+	pci_set_drvdata(pdev, vdev);
+
+	ret = ivpu_dev_init(vdev);
+	if (ret)
+		return ret;
+
+	ivpu_debugfs_init(vdev);
+	ivpu_sysfs_init(vdev);
+
+	ret = drm_dev_register(&vdev->drm, 0);
+	if (ret) {
+		dev_err(&pdev->dev, "Failed to register DRM device: %d\n", ret);
+		ivpu_dev_fini(vdev);
+	}
+
+	return ret;
+}
+
+static void ivpu_remove(struct pci_dev *pdev)
+{
+	struct ivpu_device *vdev = pci_get_drvdata(pdev);
+
+	drm_dev_unplug(&vdev->drm);
+	ivpu_dev_fini(vdev);
+}
+
+static const struct dev_pm_ops ivpu_drv_pci_pm = {
+	SET_SYSTEM_SLEEP_PM_OPS(ivpu_pm_suspend_cb, ivpu_pm_resume_cb)
+	SET_RUNTIME_PM_OPS(ivpu_pm_runtime_suspend_cb, ivpu_pm_runtime_resume_cb, NULL)
+};
+
+static const struct pci_error_handlers ivpu_drv_pci_err = {
+	.reset_prepare = ivpu_pm_reset_prepare_cb,
+	.reset_done = ivpu_pm_reset_done_cb,
+};
+
+static struct pci_driver ivpu_pci_driver = {
+	.name = KBUILD_MODNAME,
+	.id_table = ivpu_pci_ids,
+	.probe = ivpu_probe,
+	.remove = ivpu_remove,
+	.driver = {
+		.pm = &ivpu_drv_pci_pm,
+	},
+	.err_handler = &ivpu_drv_pci_err,
+};
+
+module_pci_driver(ivpu_pci_driver);
+
+MODULE_AUTHOR("Intel Corporation");
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_LICENSE("GPL and additional rights");
+MODULE_VERSION(DRIVER_VERSION_STR);
diff --git a/drivers/accel/ivpu/ivpu_drv.h b/drivers/accel/ivpu/ivpu_drv.h
new file mode 100644
index 000000000000..5b34b6f50e69
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_drv.h
@@ -0,0 +1,316 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2020-2025 Intel Corporation
+ */
+
+#ifndef __IVPU_DRV_H__
+#define __IVPU_DRV_H__
+
+#include <drm/drm_device.h>
+#include <drm/drm_drv.h>
+#include <drm/drm_managed.h>
+#include <drm/drm_mm.h>
+#include <drm/drm_print.h>
+
+#include <linux/pci.h>
+#include <linux/xarray.h>
+#include <uapi/drm/ivpu_accel.h>
+
+#include "ivpu_mmu_context.h"
+#include "ivpu_ipc.h"
+
+#define DRIVER_NAME "intel_vpu"
+#define DRIVER_DESC "Driver for Intel NPU (Neural Processing Unit)"
+
+#define PCI_DEVICE_ID_MTL	0x7d1d
+#define PCI_DEVICE_ID_ARL	0xad1d
+#define PCI_DEVICE_ID_LNL	0x643e
+#define PCI_DEVICE_ID_PTL_P	0xb03e
+#define PCI_DEVICE_ID_WCL	0xfd3e
+#define PCI_DEVICE_ID_NVL	0xd71d
+
+#define IVPU_HW_IP_37XX 37
+#define IVPU_HW_IP_40XX 40
+#define IVPU_HW_IP_50XX 50
+#define IVPU_HW_IP_60XX 60
+
+#define IVPU_HW_IP_REV_LNL_B0 4
+
+#define IVPU_HW_BTRS_MTL 1
+#define IVPU_HW_BTRS_LNL 2
+
+#define IVPU_GLOBAL_CONTEXT_MMU_SSID   0
+/* SSID 1 is used by the VPU to represent reserved context */
+#define IVPU_RESERVED_CONTEXT_MMU_SSID 1
+#define IVPU_USER_CONTEXT_MIN_SSID     2
+#define IVPU_USER_CONTEXT_MAX_SSID     (IVPU_USER_CONTEXT_MIN_SSID + 63)
+
+#define IVPU_MIN_DB 1
+#define IVPU_MAX_DB 255
+
+#define IVPU_JOB_ID_JOB_MASK		GENMASK(7, 0)
+#define IVPU_JOB_ID_CONTEXT_MASK	GENMASK(31, 8)
+
+#define IVPU_NUM_PRIORITIES    4
+#define IVPU_NUM_CMDQS_PER_CTX (IVPU_NUM_PRIORITIES)
+
+#define IVPU_CMDQ_MIN_ID 1
+#define IVPU_CMDQ_MAX_ID 255
+
+#define IVPU_PLATFORM_SILICON 0
+#define IVPU_PLATFORM_SIMICS  2
+#define IVPU_PLATFORM_FPGA    3
+#define IVPU_PLATFORM_HSLE    4
+#define IVPU_PLATFORM_INVALID 8
+
+#define IVPU_SCHED_MODE_AUTO -1
+
+#define IVPU_DBG_REG	 BIT(0)
+#define IVPU_DBG_IRQ	 BIT(1)
+#define IVPU_DBG_MMU	 BIT(2)
+#define IVPU_DBG_FILE	 BIT(3)
+#define IVPU_DBG_MISC	 BIT(4)
+#define IVPU_DBG_FW_BOOT BIT(5)
+#define IVPU_DBG_PM	 BIT(6)
+#define IVPU_DBG_IPC	 BIT(7)
+#define IVPU_DBG_BO	 BIT(8)
+#define IVPU_DBG_JOB	 BIT(9)
+#define IVPU_DBG_JSM	 BIT(10)
+#define IVPU_DBG_KREF	 BIT(11)
+#define IVPU_DBG_RPM	 BIT(12)
+#define IVPU_DBG_MMU_MAP BIT(13)
+#define IVPU_DBG_IOCTL   BIT(14)
+
+#define ivpu_err(vdev, fmt, ...) \
+	drm_err(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
+
+#define ivpu_err_ratelimited(vdev, fmt, ...) \
+	drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
+
+#define ivpu_warn(vdev, fmt, ...) \
+	drm_warn(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
+
+#define ivpu_warn_ratelimited(vdev, fmt, ...) \
+	drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
+
+#define ivpu_info(vdev, fmt, ...) drm_info(&(vdev)->drm, fmt, ##__VA_ARGS__)
+
+#define ivpu_dbg(vdev, type, fmt, args...) do {                                \
+	if (unlikely(IVPU_DBG_##type & ivpu_dbg_mask))                         \
+		dev_dbg((vdev)->drm.dev, "[%s] " fmt, #type, ##args);          \
+} while (0)
+
+#define IVPU_WA(wa_name) (vdev->wa.wa_name)
+
+#define IVPU_PRINT_WA(wa_name) do {					\
+	if (IVPU_WA(wa_name))						\
+		ivpu_dbg(vdev, MISC, "Using WA: " #wa_name "\n");	\
+} while (0)
+
+struct ivpu_wa_table {
+	bool punit_disabled;
+	bool clear_runtime_mem;
+	bool interrupt_clear_with_0;
+	bool disable_clock_relinquish;
+	bool disable_d0i3_msg;
+	bool wp0_during_power_up;
+	bool disable_d0i2;
+};
+
+struct ivpu_hw_info;
+struct ivpu_mmu_info;
+struct ivpu_fw_info;
+struct ivpu_ipc_info;
+struct ivpu_pm_info;
+
+struct ivpu_device {
+	struct drm_device drm;
+	void __iomem *regb;
+	void __iomem *regv;
+	u32 platform;
+	u32 irq;
+
+	struct ivpu_wa_table wa;
+	struct ivpu_hw_info *hw;
+	struct ivpu_mmu_info *mmu;
+	struct ivpu_fw_info *fw;
+	struct ivpu_ipc_info *ipc;
+	struct ivpu_pm_info *pm;
+
+	struct ivpu_mmu_context gctx;
+	struct ivpu_mmu_context rctx;
+	struct mutex context_list_lock; /* Protects user context addition/removal */
+	struct xarray context_xa;
+	struct xa_limit context_xa_limit;
+
+	struct xarray db_xa;
+	struct xa_limit db_limit;
+	u32 db_next;
+
+	struct work_struct irq_ipc_work;
+	struct work_struct irq_dct_work;
+	struct work_struct context_abort_work;
+
+	struct mutex bo_list_lock; /* Protects bo_list */
+	struct list_head bo_list;
+
+	struct mutex submitted_jobs_lock; /* Protects submitted_jobs */
+	struct xarray submitted_jobs_xa;
+	struct ivpu_ipc_consumer job_done_consumer;
+	atomic_t job_timeout_counter;
+
+	atomic64_t unique_id_counter;
+
+	ktime_t busy_start_ts;
+	ktime_t busy_time;
+
+	struct {
+		int boot;
+		int jsm;
+		int tdr;
+		int inference;
+		int autosuspend;
+		int d0i3_entry_msg;
+		int state_dump_msg;
+	} timeout;
+};
+
+/*
+ * file_priv has its own refcount (ref) that allows user space to close the fd
+ * without blocking even if VPU is still processing some jobs.
+ */
+struct ivpu_file_priv {
+	struct kref ref;
+	struct ivpu_device *vdev;
+	struct mutex lock; /* Protects cmdq */
+	struct xarray cmdq_xa;
+	struct ivpu_mmu_context ctx;
+	struct mutex ms_lock; /* Protects ms_instance_list, ms_info_bo */
+	struct list_head ms_instance_list;
+	struct ivpu_bo *ms_info_bo;
+	struct xa_limit job_limit;
+	u32 job_id_next;
+	struct xa_limit cmdq_limit;
+	u32 cmdq_id_next;
+	bool has_mmu_faults;
+	bool bound;
+	bool aborted;
+};
+
+extern int ivpu_dbg_mask;
+extern u8 ivpu_pll_min_ratio;
+extern u8 ivpu_pll_max_ratio;
+extern int ivpu_sched_mode;
+extern bool ivpu_disable_mmu_cont_pages;
+extern bool ivpu_force_snoop;
+
+#define IVPU_TEST_MODE_FW_TEST            BIT(0)
+#define IVPU_TEST_MODE_NULL_HW            BIT(1)
+#define IVPU_TEST_MODE_NULL_SUBMISSION    BIT(2)
+#define IVPU_TEST_MODE_D0I3_MSG_DISABLE   BIT(4)
+#define IVPU_TEST_MODE_D0I3_MSG_ENABLE    BIT(5)
+#define IVPU_TEST_MODE_MIP_DISABLE        BIT(6)
+#define IVPU_TEST_MODE_DISABLE_TIMEOUTS   BIT(8)
+#define IVPU_TEST_MODE_TURBO_ENABLE       BIT(9)
+#define IVPU_TEST_MODE_TURBO_DISABLE      BIT(10)
+#define IVPU_TEST_MODE_CLK_RELINQ_DISABLE BIT(11)
+#define IVPU_TEST_MODE_CLK_RELINQ_ENABLE  BIT(12)
+#define IVPU_TEST_MODE_D0I2_DISABLE       BIT(13)
+extern int ivpu_test_mode;
+
+struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv);
+void ivpu_file_priv_put(struct ivpu_file_priv **link);
+
+int ivpu_boot(struct ivpu_device *vdev);
+int ivpu_shutdown(struct ivpu_device *vdev);
+void ivpu_prepare_for_reset(struct ivpu_device *vdev);
+bool ivpu_is_capable(struct ivpu_device *vdev, u32 capability);
+
+static inline u8 ivpu_revision(struct ivpu_device *vdev)
+{
+	return to_pci_dev(vdev->drm.dev)->revision;
+}
+
+static inline u16 ivpu_device_id(struct ivpu_device *vdev)
+{
+	return to_pci_dev(vdev->drm.dev)->device;
+}
+
+static inline int ivpu_hw_ip_gen(struct ivpu_device *vdev)
+{
+	switch (ivpu_device_id(vdev)) {
+	case PCI_DEVICE_ID_MTL:
+	case PCI_DEVICE_ID_ARL:
+		return IVPU_HW_IP_37XX;
+	case PCI_DEVICE_ID_LNL:
+		return IVPU_HW_IP_40XX;
+	case PCI_DEVICE_ID_PTL_P:
+	case PCI_DEVICE_ID_WCL:
+		return IVPU_HW_IP_50XX;
+	case PCI_DEVICE_ID_NVL:
+		return IVPU_HW_IP_60XX;
+	default:
+		dump_stack();
+		ivpu_err(vdev, "Unknown NPU IP generation\n");
+		return 0;
+	}
+}
+
+static inline int ivpu_hw_btrs_gen(struct ivpu_device *vdev)
+{
+	switch (ivpu_device_id(vdev)) {
+	case PCI_DEVICE_ID_MTL:
+	case PCI_DEVICE_ID_ARL:
+		return IVPU_HW_BTRS_MTL;
+	case PCI_DEVICE_ID_LNL:
+	case PCI_DEVICE_ID_PTL_P:
+	case PCI_DEVICE_ID_WCL:
+	case PCI_DEVICE_ID_NVL:
+		return IVPU_HW_BTRS_LNL;
+	default:
+		dump_stack();
+		ivpu_err(vdev, "Unknown buttress generation\n");
+		return 0;
+	}
+}
+
+static inline struct ivpu_device *to_ivpu_device(struct drm_device *dev)
+{
+	return container_of(dev, struct ivpu_device, drm);
+}
+
+static inline u32 ivpu_get_context_count(struct ivpu_device *vdev)
+{
+	struct xa_limit ctx_limit = vdev->context_xa_limit;
+
+	return (ctx_limit.max - ctx_limit.min + 1);
+}
+
+static inline u32 ivpu_get_platform(struct ivpu_device *vdev)
+{
+	WARN_ON_ONCE(vdev->platform == IVPU_PLATFORM_INVALID);
+	return vdev->platform;
+}
+
+static inline bool ivpu_is_silicon(struct ivpu_device *vdev)
+{
+	return ivpu_get_platform(vdev) == IVPU_PLATFORM_SILICON;
+}
+
+static inline bool ivpu_is_simics(struct ivpu_device *vdev)
+{
+	return ivpu_get_platform(vdev) == IVPU_PLATFORM_SIMICS;
+}
+
+static inline bool ivpu_is_fpga(struct ivpu_device *vdev)
+{
+	return ivpu_get_platform(vdev) == IVPU_PLATFORM_FPGA ||
+	       ivpu_get_platform(vdev) == IVPU_PLATFORM_HSLE;
+}
+
+static inline bool ivpu_is_force_snoop_enabled(struct ivpu_device *vdev)
+{
+	return ivpu_force_snoop;
+}
+
+#endif /* __IVPU_DRV_H__ */
diff --git a/drivers/accel/ivpu/ivpu_fw.c b/drivers/accel/ivpu/ivpu_fw.c
new file mode 100644
index 000000000000..48386d2cddbb
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_fw.c
@@ -0,0 +1,728 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020-2025 Intel Corporation
+ */
+
+#include <linux/firmware.h>
+#include <linux/highmem.h>
+#include <linux/moduleparam.h>
+#include <linux/pci.h>
+
+#include "vpu_boot_api.h"
+#include "ivpu_drv.h"
+#include "ivpu_fw.h"
+#include "ivpu_fw_log.h"
+#include "ivpu_gem.h"
+#include "ivpu_hw.h"
+#include "ivpu_ipc.h"
+#include "ivpu_pm.h"
+
+#define FW_SHAVE_NN_MAX_SIZE	SZ_2M
+#define FW_FILE_IMAGE_OFFSET	(VPU_FW_HEADER_SIZE + FW_VERSION_HEADER_SIZE)
+#define FW_PREEMPT_BUF_MIN_SIZE SZ_4K
+#define FW_PREEMPT_BUF_MAX_SIZE SZ_32M
+
+#define WATCHDOG_MSS_REDIRECT	32
+#define WATCHDOG_NCE_REDIRECT	33
+
+#define ADDR_TO_L2_CACHE_CFG(addr) ((addr) >> 31)
+
+/* Check if FW API is compatible with the driver */
+#define IVPU_FW_CHECK_API_COMPAT(vdev, fw_hdr, name, min_major) \
+	ivpu_fw_check_api(vdev, fw_hdr, #name, \
+			  VPU_##name##_API_VER_INDEX, \
+			  VPU_##name##_API_VER_MAJOR, \
+			  VPU_##name##_API_VER_MINOR, min_major)
+
+/* Check if API version is lower that the given version */
+#define IVPU_FW_CHECK_API_VER_LT(vdev, fw_hdr, name, major, minor) \
+	ivpu_fw_check_api_ver_lt(vdev, fw_hdr, #name, VPU_##name##_API_VER_INDEX, major, minor)
+
+#define IVPU_FOCUS_PRESENT_TIMER_MS 1000
+
+static char *ivpu_firmware;
+#if IS_ENABLED(CONFIG_DRM_ACCEL_IVPU_DEBUG)
+module_param_named_unsafe(firmware, ivpu_firmware, charp, 0644);
+MODULE_PARM_DESC(firmware, "NPU firmware binary in /lib/firmware/..");
+#endif
+
+static struct {
+	int gen;
+	const char *name;
+} fw_names[] = {
+	{ IVPU_HW_IP_37XX, "intel/vpu/vpu_37xx_v1.bin" },
+	{ IVPU_HW_IP_37XX, "intel/vpu/vpu_37xx_v0.0.bin" },
+	{ IVPU_HW_IP_40XX, "intel/vpu/vpu_40xx_v1.bin" },
+	{ IVPU_HW_IP_40XX, "intel/vpu/vpu_40xx_v0.0.bin" },
+	{ IVPU_HW_IP_50XX, "intel/vpu/vpu_50xx_v1.bin" },
+	{ IVPU_HW_IP_50XX, "intel/vpu/vpu_50xx_v0.0.bin" },
+	{ IVPU_HW_IP_60XX, "intel/vpu/vpu_60xx_v1.bin" },
+};
+
+/* Production fw_names from the table above */
+MODULE_FIRMWARE("intel/vpu/vpu_37xx_v1.bin");
+MODULE_FIRMWARE("intel/vpu/vpu_40xx_v1.bin");
+MODULE_FIRMWARE("intel/vpu/vpu_50xx_v1.bin");
+MODULE_FIRMWARE("intel/vpu/vpu_60xx_v1.bin");
+
+static int ivpu_fw_request(struct ivpu_device *vdev)
+{
+	int ret = -ENOENT;
+	int i;
+
+	if (ivpu_firmware) {
+		ret = request_firmware(&vdev->fw->file, ivpu_firmware, vdev->drm.dev);
+		if (!ret)
+			vdev->fw->name = ivpu_firmware;
+		return ret;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(fw_names); i++) {
+		if (fw_names[i].gen != ivpu_hw_ip_gen(vdev))
+			continue;
+
+		ret = firmware_request_nowarn(&vdev->fw->file, fw_names[i].name, vdev->drm.dev);
+		if (!ret) {
+			vdev->fw->name = fw_names[i].name;
+			return 0;
+		}
+	}
+
+	ivpu_err(vdev, "Failed to request firmware: %d\n", ret);
+	return ret;
+}
+
+static int
+ivpu_fw_check_api(struct ivpu_device *vdev, const struct vpu_firmware_header *fw_hdr,
+		  const char *str, int index, u16 expected_major, u16 expected_minor,
+		  u16 min_major)
+{
+	u16 major = (u16)(fw_hdr->api_version[index] >> 16);
+	u16 minor = (u16)(fw_hdr->api_version[index]);
+
+	if (major < min_major) {
+		ivpu_err(vdev, "Incompatible FW %s API version: %d.%d, required %d.0 or later\n",
+			 str, major, minor, min_major);
+		return -EINVAL;
+	}
+	if (major != expected_major) {
+		ivpu_warn(vdev, "Major FW %s API version different: %d.%d (expected %d.%d)\n",
+			  str, major, minor, expected_major, expected_minor);
+	}
+	ivpu_dbg(vdev, FW_BOOT, "FW %s API version: %d.%d (expected %d.%d)\n",
+		 str, major, minor, expected_major, expected_minor);
+
+	return 0;
+}
+
+static bool
+ivpu_fw_check_api_ver_lt(struct ivpu_device *vdev, const struct vpu_firmware_header *fw_hdr,
+			 const char *str, int index, u16 major, u16 minor)
+{
+	u16 fw_major = (u16)(fw_hdr->api_version[index] >> 16);
+	u16 fw_minor = (u16)(fw_hdr->api_version[index]);
+
+	if (fw_major < major || (fw_major == major && fw_minor < minor))
+		return true;
+
+	return false;
+}
+
+bool ivpu_is_within_range(u64 addr, size_t size, struct ivpu_addr_range *range)
+{
+	u64 addr_end;
+
+	if (!range || check_add_overflow(addr, size, &addr_end))
+		return false;
+
+	if (addr < range->start || addr_end > range->end)
+		return false;
+
+	return true;
+}
+
+static u32
+ivpu_fw_sched_mode_select(struct ivpu_device *vdev, const struct vpu_firmware_header *fw_hdr)
+{
+	if (ivpu_hw_ip_gen(vdev) >= IVPU_HW_IP_60XX &&
+	    ivpu_sched_mode == VPU_SCHEDULING_MODE_OS) {
+		ivpu_warn(vdev, "OS sched mode is not supported, using HW mode\n");
+		return VPU_SCHEDULING_MODE_HW;
+	}
+
+	if (ivpu_sched_mode != IVPU_SCHED_MODE_AUTO)
+		return ivpu_sched_mode;
+
+	if (IVPU_FW_CHECK_API_VER_LT(vdev, fw_hdr, JSM, 3, 24))
+		return VPU_SCHEDULING_MODE_OS;
+
+	return VPU_SCHEDULING_MODE_HW;
+}
+
+static void
+ivpu_preemption_config_parse(struct ivpu_device *vdev, const struct vpu_firmware_header *fw_hdr)
+{
+	struct ivpu_fw_info *fw = vdev->fw;
+	u32 primary_preempt_buf_size, secondary_preempt_buf_size;
+
+	if (fw_hdr->preemption_buffer_1_max_size)
+		primary_preempt_buf_size = fw_hdr->preemption_buffer_1_max_size;
+	else
+		primary_preempt_buf_size = fw_hdr->preemption_buffer_1_size;
+
+	if (fw_hdr->preemption_buffer_2_max_size)
+		secondary_preempt_buf_size = fw_hdr->preemption_buffer_2_max_size;
+	else
+		secondary_preempt_buf_size = fw_hdr->preemption_buffer_2_size;
+
+	ivpu_dbg(vdev, FW_BOOT, "Preemption buffer size, primary: %u, secondary: %u\n",
+		 primary_preempt_buf_size, secondary_preempt_buf_size);
+
+	if (primary_preempt_buf_size < FW_PREEMPT_BUF_MIN_SIZE ||
+	    secondary_preempt_buf_size < FW_PREEMPT_BUF_MIN_SIZE) {
+		ivpu_warn(vdev, "Preemption buffers size too small\n");
+		return;
+	}
+
+	if (primary_preempt_buf_size > FW_PREEMPT_BUF_MAX_SIZE ||
+	    secondary_preempt_buf_size > FW_PREEMPT_BUF_MAX_SIZE) {
+		ivpu_warn(vdev, "Preemption buffers size too big\n");
+		return;
+	}
+
+	if (fw->sched_mode != VPU_SCHEDULING_MODE_HW)
+		return;
+
+	if (ivpu_test_mode & IVPU_TEST_MODE_MIP_DISABLE)
+		return;
+
+	vdev->fw->primary_preempt_buf_size = ALIGN(primary_preempt_buf_size, PAGE_SIZE);
+	vdev->fw->secondary_preempt_buf_size = ALIGN(secondary_preempt_buf_size, PAGE_SIZE);
+}
+
+static int ivpu_fw_parse(struct ivpu_device *vdev)
+{
+	struct ivpu_fw_info *fw = vdev->fw;
+	const struct vpu_firmware_header *fw_hdr = (const void *)fw->file->data;
+	struct ivpu_addr_range fw_image_range;
+	u64 boot_params_addr, boot_params_size;
+	u64 fw_version_addr, fw_version_size;
+	u64 runtime_addr, runtime_size;
+	u64 image_load_addr, image_size;
+
+	if (fw->file->size <= FW_FILE_IMAGE_OFFSET) {
+		ivpu_err(vdev, "Firmware file is too small: %zu\n", fw->file->size);
+		return -EINVAL;
+	}
+
+	if (fw_hdr->header_version != VPU_FW_HEADER_VERSION) {
+		ivpu_err(vdev, "Invalid firmware header version: %u\n", fw_hdr->header_version);
+		return -EINVAL;
+	}
+
+	boot_params_addr = fw_hdr->boot_params_load_address;
+	boot_params_size = SZ_4K;
+
+	if (!ivpu_is_within_range(boot_params_addr, boot_params_size, &vdev->hw->ranges.runtime)) {
+		ivpu_err(vdev, "Invalid boot params address: 0x%llx\n", boot_params_addr);
+		return -EINVAL;
+	}
+
+	fw_version_addr = fw_hdr->firmware_version_load_address;
+	fw_version_size = ALIGN(fw_hdr->firmware_version_size, SZ_4K);
+
+	if (fw_version_size != SZ_4K) {
+		ivpu_err(vdev, "Invalid firmware version size: %u\n",
+			 fw_hdr->firmware_version_size);
+		return -EINVAL;
+	}
+
+	if (!ivpu_is_within_range(fw_version_addr, fw_version_size, &vdev->hw->ranges.runtime)) {
+		ivpu_err(vdev, "Invalid firmware version address: 0x%llx\n", fw_version_addr);
+		return -EINVAL;
+	}
+
+	runtime_addr = fw_hdr->image_load_address;
+	runtime_size = fw_hdr->runtime_size - boot_params_size - fw_version_size;
+
+	image_load_addr = fw_hdr->image_load_address;
+	image_size = fw_hdr->image_size;
+
+	if (!ivpu_is_within_range(runtime_addr, runtime_size, &vdev->hw->ranges.runtime)) {
+		ivpu_err(vdev, "Invalid firmware runtime address: 0x%llx and size %llu\n",
+			 runtime_addr, runtime_size);
+		return -EINVAL;
+	}
+
+	if (FW_FILE_IMAGE_OFFSET + image_size > fw->file->size) {
+		ivpu_err(vdev, "Invalid image size: %llu\n", image_size);
+		return -EINVAL;
+	}
+
+	if (!ivpu_is_within_range(image_load_addr, image_size, &vdev->hw->ranges.runtime)) {
+		ivpu_err(vdev, "Invalid firmware load address: 0x%llx and size %llu\n",
+			 image_load_addr, image_size);
+		return -EINVAL;
+	}
+
+	if (ivpu_hw_range_init(vdev, &fw_image_range, image_load_addr, image_size))
+		return -EINVAL;
+
+	if (!ivpu_is_within_range(fw_hdr->entry_point, SZ_4K, &fw_image_range)) {
+		ivpu_err(vdev, "Invalid entry point: 0x%llx\n", fw_hdr->entry_point);
+		return -EINVAL;
+	}
+
+	if (fw_hdr->shave_nn_fw_size > FW_SHAVE_NN_MAX_SIZE) {
+		ivpu_err(vdev, "SHAVE NN firmware is too big: %u\n", fw_hdr->shave_nn_fw_size);
+		return -EINVAL;
+	}
+
+	ivpu_dbg(vdev, FW_BOOT, "Header version: 0x%x, format 0x%x\n",
+		 fw_hdr->header_version, fw_hdr->image_format);
+
+	if (!scnprintf(fw->version, sizeof(fw->version), "%s", fw->file->data + VPU_FW_HEADER_SIZE))
+		ivpu_warn(vdev, "Missing firmware version\n");
+
+	ivpu_info(vdev, "Firmware: %s, version: %s\n", fw->name, fw->version);
+
+	if (IVPU_FW_CHECK_API_COMPAT(vdev, fw_hdr, BOOT, 3))
+		return -EINVAL;
+	if (IVPU_FW_CHECK_API_COMPAT(vdev, fw_hdr, JSM, 3))
+		return -EINVAL;
+
+	fw->boot_params_addr = boot_params_addr;
+	fw->boot_params_size = boot_params_size;
+	fw->fw_version_addr = fw_version_addr;
+	fw->fw_version_size = fw_version_size;
+	fw->runtime_addr = runtime_addr;
+	fw->runtime_size = runtime_size;
+	fw->image_load_offset = image_load_addr - runtime_addr;
+	fw->image_size = image_size;
+	fw->shave_nn_size = PAGE_ALIGN(fw_hdr->shave_nn_fw_size);
+
+	fw->cold_boot_entry_point = fw_hdr->entry_point;
+	fw->entry_point = fw->cold_boot_entry_point;
+
+	fw->trace_level = min_t(u32, ivpu_fw_log_level, IVPU_FW_LOG_FATAL);
+	fw->trace_destination_mask = VPU_TRACE_DESTINATION_VERBOSE_TRACING;
+	fw->trace_hw_component_mask = -1;
+
+	fw->dvfs_mode = 0;
+
+	fw->sched_mode = ivpu_fw_sched_mode_select(vdev, fw_hdr);
+	ivpu_info(vdev, "Scheduler mode: %s\n", fw->sched_mode ? "HW" : "OS");
+
+	ivpu_preemption_config_parse(vdev, fw_hdr);
+	ivpu_dbg(vdev, FW_BOOT, "Mid-inference preemption %s supported\n",
+		 ivpu_fw_preempt_buf_size(vdev) ? "is" : "is not");
+
+	if (fw_hdr->ro_section_start_address &&
+	    !ivpu_is_within_range(fw_hdr->ro_section_start_address, fw_hdr->ro_section_size,
+				  &fw_image_range)) {
+		ivpu_err(vdev, "Invalid read-only section: start address 0x%llx, size %u\n",
+			 fw_hdr->ro_section_start_address, fw_hdr->ro_section_size);
+		return -EINVAL;
+	}
+
+	fw->read_only_addr = fw_hdr->ro_section_start_address;
+	fw->read_only_size = fw_hdr->ro_section_size;
+
+	ivpu_dbg(vdev, FW_BOOT, "Boot params: address 0x%llx, size %llu\n",
+		 fw->boot_params_addr, fw->boot_params_size);
+	ivpu_dbg(vdev, FW_BOOT, "FW version:  address 0x%llx, size %llu\n",
+		 fw->fw_version_addr, fw->fw_version_size);
+	ivpu_dbg(vdev, FW_BOOT, "Runtime:     address 0x%llx, size %u\n",
+		 fw->runtime_addr, fw->runtime_size);
+	ivpu_dbg(vdev, FW_BOOT, "Image load offset: 0x%llx, size %u\n",
+		 fw->image_load_offset, fw->image_size);
+	ivpu_dbg(vdev, FW_BOOT, "Read-only section: address 0x%llx, size %u\n",
+		 fw->read_only_addr, fw->read_only_size);
+	ivpu_dbg(vdev, FW_BOOT, "FW entry point: 0x%llx\n", fw->entry_point);
+	ivpu_dbg(vdev, FW_BOOT, "SHAVE NN size: %u\n", fw->shave_nn_size);
+
+	return 0;
+}
+
+static void ivpu_fw_release(struct ivpu_device *vdev)
+{
+	release_firmware(vdev->fw->file);
+}
+
+/* Initialize workarounds that depend on FW version */
+static void
+ivpu_fw_init_wa(struct ivpu_device *vdev)
+{
+	const struct vpu_firmware_header *fw_hdr = (const void *)vdev->fw->file->data;
+
+	if (IVPU_FW_CHECK_API_VER_LT(vdev, fw_hdr, BOOT, 3, 17) ||
+	    (ivpu_test_mode & IVPU_TEST_MODE_D0I3_MSG_DISABLE))
+		vdev->wa.disable_d0i3_msg = true;
+
+	/* Force enable the feature for testing purposes */
+	if (ivpu_test_mode & IVPU_TEST_MODE_D0I3_MSG_ENABLE)
+		vdev->wa.disable_d0i3_msg = false;
+
+	IVPU_PRINT_WA(disable_d0i3_msg);
+}
+
+static int ivpu_fw_mem_init(struct ivpu_device *vdev)
+{
+	struct ivpu_fw_info *fw = vdev->fw;
+	int log_verb_size;
+	int ret;
+
+	fw->mem_bp = ivpu_bo_create_runtime(vdev, fw->boot_params_addr, fw->boot_params_size,
+					    DRM_IVPU_BO_WC | DRM_IVPU_BO_MAPPABLE);
+	if (!fw->mem_bp) {
+		ivpu_err(vdev, "Failed to create firmware boot params memory buffer\n");
+		return -ENOMEM;
+	}
+
+	fw->mem_fw_ver = ivpu_bo_create_runtime(vdev, fw->fw_version_addr, fw->fw_version_size,
+						DRM_IVPU_BO_WC | DRM_IVPU_BO_MAPPABLE);
+	if (!fw->mem_fw_ver) {
+		ivpu_err(vdev, "Failed to create firmware version memory buffer\n");
+		ret = -ENOMEM;
+		goto err_free_bp;
+	}
+
+	fw->mem = ivpu_bo_create_runtime(vdev, fw->runtime_addr, fw->runtime_size,
+					 DRM_IVPU_BO_WC | DRM_IVPU_BO_MAPPABLE);
+	if (!fw->mem) {
+		ivpu_err(vdev, "Failed to create firmware runtime memory buffer\n");
+		ret = -ENOMEM;
+		goto err_free_fw_ver;
+	}
+
+	ret = ivpu_mmu_context_set_pages_ro(vdev, &vdev->gctx, fw->read_only_addr,
+					    fw->read_only_size);
+	if (ret) {
+		ivpu_err(vdev, "Failed to set firmware image read-only\n");
+		goto err_free_fw_mem;
+	}
+
+	fw->mem_log_crit = ivpu_bo_create_global(vdev, IVPU_FW_CRITICAL_BUFFER_SIZE,
+						 DRM_IVPU_BO_CACHED | DRM_IVPU_BO_MAPPABLE);
+	if (!fw->mem_log_crit) {
+		ivpu_err(vdev, "Failed to create critical log buffer\n");
+		ret = -ENOMEM;
+		goto err_free_fw_mem;
+	}
+
+	if (ivpu_fw_log_level <= IVPU_FW_LOG_INFO)
+		log_verb_size = IVPU_FW_VERBOSE_BUFFER_LARGE_SIZE;
+	else
+		log_verb_size = IVPU_FW_VERBOSE_BUFFER_SMALL_SIZE;
+
+	fw->mem_log_verb = ivpu_bo_create_global(vdev, log_verb_size,
+						 DRM_IVPU_BO_CACHED | DRM_IVPU_BO_MAPPABLE);
+	if (!fw->mem_log_verb) {
+		ivpu_err(vdev, "Failed to create verbose log buffer\n");
+		ret = -ENOMEM;
+		goto err_free_log_crit;
+	}
+
+	if (fw->shave_nn_size) {
+		fw->mem_shave_nn = ivpu_bo_create(vdev, &vdev->gctx, &vdev->hw->ranges.shave,
+						  fw->shave_nn_size, DRM_IVPU_BO_WC);
+		if (!fw->mem_shave_nn) {
+			ivpu_err(vdev, "Failed to create shavenn buffer\n");
+			ret = -ENOMEM;
+			goto err_free_log_verb;
+		}
+	}
+
+	return 0;
+
+err_free_log_verb:
+	ivpu_bo_free(fw->mem_log_verb);
+err_free_log_crit:
+	ivpu_bo_free(fw->mem_log_crit);
+err_free_fw_mem:
+	ivpu_bo_free(fw->mem);
+err_free_fw_ver:
+	ivpu_bo_free(fw->mem_fw_ver);
+err_free_bp:
+	ivpu_bo_free(fw->mem_bp);
+	return ret;
+}
+
+static void ivpu_fw_mem_fini(struct ivpu_device *vdev)
+{
+	struct ivpu_fw_info *fw = vdev->fw;
+
+	if (fw->mem_shave_nn) {
+		ivpu_bo_free(fw->mem_shave_nn);
+		fw->mem_shave_nn = NULL;
+	}
+
+	ivpu_bo_free(fw->mem_log_verb);
+	ivpu_bo_free(fw->mem_log_crit);
+	ivpu_bo_free(fw->mem);
+	ivpu_bo_free(fw->mem_fw_ver);
+	ivpu_bo_free(fw->mem_bp);
+
+	fw->mem_log_verb = NULL;
+	fw->mem_log_crit = NULL;
+	fw->mem = NULL;
+	fw->mem_fw_ver = NULL;
+	fw->mem_bp = NULL;
+}
+
+int ivpu_fw_init(struct ivpu_device *vdev)
+{
+	int ret;
+
+	ret = ivpu_fw_request(vdev);
+	if (ret)
+		return ret;
+
+	ret = ivpu_fw_parse(vdev);
+	if (ret)
+		goto err_fw_release;
+
+	ivpu_fw_init_wa(vdev);
+
+	ret = ivpu_fw_mem_init(vdev);
+	if (ret)
+		goto err_fw_release;
+
+	ivpu_fw_load(vdev);
+
+	return 0;
+
+err_fw_release:
+	ivpu_fw_release(vdev);
+	return ret;
+}
+
+void ivpu_fw_fini(struct ivpu_device *vdev)
+{
+	ivpu_fw_mem_fini(vdev);
+	ivpu_fw_release(vdev);
+}
+
+void ivpu_fw_load(struct ivpu_device *vdev)
+{
+	struct ivpu_fw_info *fw = vdev->fw;
+	u64 image_end_offset = fw->image_load_offset + fw->image_size;
+
+	memset(ivpu_bo_vaddr(fw->mem), 0, fw->image_load_offset);
+	memcpy(ivpu_bo_vaddr(fw->mem) + fw->image_load_offset,
+	       fw->file->data + FW_FILE_IMAGE_OFFSET, fw->image_size);
+
+	if (IVPU_WA(clear_runtime_mem)) {
+		u8 *start = ivpu_bo_vaddr(fw->mem) + image_end_offset;
+		u64 size = ivpu_bo_size(fw->mem) - image_end_offset;
+
+		memset(start, 0, size);
+	}
+
+	wmb(); /* Flush WC buffers after writing fw->mem */
+}
+
+static void ivpu_fw_boot_params_print(struct ivpu_device *vdev, struct vpu_boot_params *boot_params)
+{
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.magic = 0x%x\n",
+		 boot_params->magic);
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_id = 0x%x\n",
+		 boot_params->vpu_id);
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_count = 0x%x\n",
+		 boot_params->vpu_count);
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.frequency = %u\n",
+		 boot_params->frequency);
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.perf_clk_frequency = %u\n",
+		 boot_params->perf_clk_frequency);
+
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_header_area_start = 0x%llx\n",
+		 boot_params->ipc_header_area_start);
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_header_area_size = 0x%x\n",
+		 boot_params->ipc_header_area_size);
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.shared_region_base = 0x%llx\n",
+		 boot_params->shared_region_base);
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.shared_region_size = 0x%x\n",
+		 boot_params->shared_region_size);
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_payload_area_start = 0x%llx\n",
+		 boot_params->ipc_payload_area_start);
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_payload_area_size = 0x%x\n",
+		 boot_params->ipc_payload_area_size);
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.global_aliased_pio_base = 0x%llx\n",
+		 boot_params->global_aliased_pio_base);
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.global_aliased_pio_size = 0x%x\n",
+		 boot_params->global_aliased_pio_size);
+
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.autoconfig = 0x%x\n",
+		 boot_params->autoconfig);
+
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use = 0x%x\n",
+		 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use);
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg = 0x%x\n",
+		 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg);
+
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.shave_nn_fw_base = 0x%llx\n",
+		 boot_params->shave_nn_fw_base);
+
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.watchdog_irq_mss = 0x%x\n",
+		 boot_params->watchdog_irq_mss);
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.watchdog_irq_nce = 0x%x\n",
+		 boot_params->watchdog_irq_nce);
+
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.host_version_id = 0x%x\n",
+		 boot_params->host_version_id);
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.si_stepping = 0x%x\n",
+		 boot_params->si_stepping);
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.device_id = 0x%llx\n",
+		 boot_params->device_id);
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.feature_exclusion = 0x%llx\n",
+		 boot_params->feature_exclusion);
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.sku = 0x%llx\n",
+		 boot_params->sku);
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.min_freq_pll_ratio = 0x%x\n",
+		 boot_params->min_freq_pll_ratio);
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.pn_freq_pll_ratio = 0x%x\n",
+		 boot_params->pn_freq_pll_ratio);
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.max_freq_pll_ratio = 0x%x\n",
+		 boot_params->max_freq_pll_ratio);
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.default_trace_level = 0x%x\n",
+		 boot_params->default_trace_level);
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.tracing_buff_message_format_mask = 0x%llx\n",
+		 boot_params->tracing_buff_message_format_mask);
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.trace_destination_mask = 0x%x\n",
+		 boot_params->trace_destination_mask);
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.trace_hw_component_mask = 0x%llx\n",
+		 boot_params->trace_hw_component_mask);
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.boot_type = 0x%x\n",
+		 boot_params->boot_type);
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.punit_telemetry_sram_base = 0x%llx\n",
+		 boot_params->punit_telemetry_sram_base);
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.punit_telemetry_sram_size = 0x%llx\n",
+		 boot_params->punit_telemetry_sram_size);
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_telemetry_enable = 0x%x\n",
+		 boot_params->vpu_telemetry_enable);
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_scheduling_mode = 0x%x\n",
+		 boot_params->vpu_scheduling_mode);
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.dvfs_mode = %u\n",
+		 boot_params->dvfs_mode);
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_delayed_entry = %d\n",
+		 boot_params->d0i3_delayed_entry);
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_residency_time_us = %lld\n",
+		 boot_params->d0i3_residency_time_us);
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_entry_vpu_ts = %llu\n",
+		 boot_params->d0i3_entry_vpu_ts);
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.system_time_us = %llu\n",
+		 boot_params->system_time_us);
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.power_profile = 0x%x\n",
+		 boot_params->power_profile);
+	ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_uses_ecc_mca_signal = 0x%x\n",
+		 boot_params->vpu_uses_ecc_mca_signal);
+}
+
+void ivpu_fw_boot_params_setup(struct ivpu_device *vdev, struct vpu_boot_params *boot_params)
+{
+	struct ivpu_bo *ipc_mem_rx = vdev->ipc->mem_rx;
+
+	/* In case of warm boot only update variable params */
+	if (!ivpu_fw_is_cold_boot(vdev)) {
+		boot_params->d0i3_residency_time_us =
+			ktime_us_delta(ktime_get_boottime(), vdev->hw->d0i3_entry_host_ts);
+		boot_params->d0i3_entry_vpu_ts = vdev->hw->d0i3_entry_vpu_ts;
+		boot_params->system_time_us = ktime_to_us(ktime_get_real());
+
+		ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_residency_time_us = %lld\n",
+			 boot_params->d0i3_residency_time_us);
+		ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_entry_vpu_ts = %llu\n",
+			 boot_params->d0i3_entry_vpu_ts);
+		ivpu_dbg(vdev, FW_BOOT, "boot_params.system_time_us = %llu\n",
+			 boot_params->system_time_us);
+
+		boot_params->save_restore_ret_address = 0;
+		vdev->pm->is_warmboot = true;
+		wmb(); /* Flush WC buffers after writing save_restore_ret_address */
+		return;
+	}
+
+	memset(boot_params, 0, sizeof(*boot_params));
+	vdev->pm->is_warmboot = false;
+
+	boot_params->magic = VPU_BOOT_PARAMS_MAGIC;
+	boot_params->vpu_id = to_pci_dev(vdev->drm.dev)->bus->number;
+
+	/*
+	 * This param is a debug firmware feature.  It switches default clock
+	 * to higher resolution one for fine-grained and more accurate firmware
+	 * task profiling.
+	 */
+	boot_params->perf_clk_frequency = ivpu_hw_profiling_freq_get(vdev);
+
+	/*
+	 * Uncached region of VPU address space, covers IPC buffers, job queues
+	 * and log buffers, programmable to L2$ Uncached by VPU MTRR
+	 */
+	boot_params->shared_region_base = vdev->hw->ranges.global.start;
+	boot_params->shared_region_size = vdev->hw->ranges.global.end -
+					  vdev->hw->ranges.global.start;
+
+	boot_params->ipc_header_area_start = ipc_mem_rx->vpu_addr;
+	boot_params->ipc_header_area_size = ivpu_bo_size(ipc_mem_rx) / 2;
+
+	boot_params->ipc_payload_area_start = ipc_mem_rx->vpu_addr + ivpu_bo_size(ipc_mem_rx) / 2;
+	boot_params->ipc_payload_area_size = ivpu_bo_size(ipc_mem_rx) / 2;
+
+	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) {
+		boot_params->global_aliased_pio_base = vdev->hw->ranges.user.start;
+		boot_params->global_aliased_pio_size = ivpu_hw_range_size(&vdev->hw->ranges.user);
+	}
+
+	/* Allow configuration for L2C_PAGE_TABLE with boot param value */
+	boot_params->autoconfig = 1;
+
+	/* Enable L2 cache for first 2GB of high memory */
+	boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use = 1;
+	boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg =
+		ADDR_TO_L2_CACHE_CFG(vdev->hw->ranges.shave.start);
+
+	if (vdev->fw->mem_shave_nn)
+		boot_params->shave_nn_fw_base = vdev->fw->mem_shave_nn->vpu_addr;
+
+	boot_params->watchdog_irq_mss = WATCHDOG_MSS_REDIRECT;
+	boot_params->watchdog_irq_nce = WATCHDOG_NCE_REDIRECT;
+	boot_params->si_stepping = ivpu_revision(vdev);
+	boot_params->device_id = ivpu_device_id(vdev);
+	boot_params->feature_exclusion = vdev->hw->tile_fuse;
+	boot_params->sku = vdev->hw->sku;
+
+	boot_params->min_freq_pll_ratio = vdev->hw->pll.min_ratio;
+	boot_params->pn_freq_pll_ratio = vdev->hw->pll.pn_ratio;
+	boot_params->max_freq_pll_ratio = vdev->hw->pll.max_ratio;
+
+	boot_params->default_trace_level = vdev->fw->trace_level;
+	boot_params->tracing_buff_message_format_mask = BIT(VPU_TRACING_FORMAT_STRING);
+	boot_params->trace_destination_mask = vdev->fw->trace_destination_mask;
+	boot_params->trace_hw_component_mask = vdev->fw->trace_hw_component_mask;
+	boot_params->crit_tracing_buff_addr = vdev->fw->mem_log_crit->vpu_addr;
+	boot_params->crit_tracing_buff_size = ivpu_bo_size(vdev->fw->mem_log_crit);
+	boot_params->verbose_tracing_buff_addr = vdev->fw->mem_log_verb->vpu_addr;
+	boot_params->verbose_tracing_buff_size = ivpu_bo_size(vdev->fw->mem_log_verb);
+
+	boot_params->punit_telemetry_sram_base = ivpu_hw_telemetry_offset_get(vdev);
+	boot_params->punit_telemetry_sram_size = ivpu_hw_telemetry_size_get(vdev);
+	boot_params->vpu_telemetry_enable = ivpu_hw_telemetry_enable_get(vdev);
+	boot_params->vpu_scheduling_mode = vdev->fw->sched_mode;
+	if (vdev->fw->sched_mode == VPU_SCHEDULING_MODE_HW)
+		boot_params->vpu_focus_present_timer_ms = IVPU_FOCUS_PRESENT_TIMER_MS;
+	boot_params->dvfs_mode = vdev->fw->dvfs_mode;
+	if (!IVPU_WA(disable_d0i3_msg))
+		boot_params->d0i3_delayed_entry = 1;
+	boot_params->d0i3_residency_time_us = 0;
+	boot_params->d0i3_entry_vpu_ts = 0;
+	if (IVPU_WA(disable_d0i2))
+		boot_params->power_profile |= BIT(1);
+	boot_params->vpu_uses_ecc_mca_signal =
+		ivpu_hw_uses_ecc_mca_signal(vdev) ? VPU_BOOT_MCA_ECC_BOTH : 0;
+
+	boot_params->system_time_us = ktime_to_us(ktime_get_real());
+	wmb(); /* Flush WC buffers after writing bootparams */
+
+	ivpu_fw_boot_params_print(vdev, boot_params);
+}
diff --git a/drivers/accel/ivpu/ivpu_fw.h b/drivers/accel/ivpu/ivpu_fw.h
new file mode 100644
index 000000000000..00945892b55e
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_fw.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2020-2025 Intel Corporation
+ */
+
+#ifndef __IVPU_FW_H__
+#define __IVPU_FW_H__
+
+#include "vpu_jsm_api.h"
+
+#define FW_VERSION_HEADER_SIZE	SZ_4K
+#define FW_VERSION_STR_SIZE	SZ_256
+
+struct ivpu_device;
+struct ivpu_bo;
+struct vpu_boot_params;
+
+struct ivpu_fw_info {
+	const struct firmware *file;
+	const char *name;
+	char version[FW_VERSION_STR_SIZE];
+	struct ivpu_bo *mem_bp;
+	struct ivpu_bo *mem_fw_ver;
+	struct ivpu_bo *mem;
+	struct ivpu_bo *mem_shave_nn;
+	struct ivpu_bo *mem_log_crit;
+	struct ivpu_bo *mem_log_verb;
+	u64 boot_params_addr;
+	u64 boot_params_size;
+	u64 fw_version_addr;
+	u64 fw_version_size;
+	u64 runtime_addr;
+	u32 runtime_size;
+	u64 image_load_offset;
+	u32 image_size;
+	u32 shave_nn_size;
+	u64 entry_point; /* Cold or warm boot entry point for next boot */
+	u64 cold_boot_entry_point;
+	u32 trace_level;
+	u32 trace_destination_mask;
+	u64 trace_hw_component_mask;
+	u32 dvfs_mode;
+	u32 primary_preempt_buf_size;
+	u32 secondary_preempt_buf_size;
+	u64 read_only_addr;
+	u32 read_only_size;
+	u32 sched_mode;
+	u64 last_heartbeat;
+};
+
+bool ivpu_is_within_range(u64 addr, size_t size, struct ivpu_addr_range *range);
+int ivpu_fw_init(struct ivpu_device *vdev);
+void ivpu_fw_fini(struct ivpu_device *vdev);
+void ivpu_fw_load(struct ivpu_device *vdev);
+void ivpu_fw_boot_params_setup(struct ivpu_device *vdev, struct vpu_boot_params *boot_params);
+
+static inline bool ivpu_fw_is_cold_boot(struct ivpu_device *vdev)
+{
+	return vdev->fw->entry_point == vdev->fw->cold_boot_entry_point;
+}
+
+static inline u32 ivpu_fw_preempt_buf_size(struct ivpu_device *vdev)
+{
+	return vdev->fw->primary_preempt_buf_size + vdev->fw->secondary_preempt_buf_size;
+}
+
+#endif /* __IVPU_FW_H__ */
diff --git a/drivers/accel/ivpu/ivpu_fw_log.c b/drivers/accel/ivpu/ivpu_fw_log.c
new file mode 100644
index 000000000000..337c906b0210
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_fw_log.c
@@ -0,0 +1,175 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020-2024 Intel Corporation
+ */
+
+#include <linux/ctype.h>
+#include <linux/highmem.h>
+#include <linux/fs.h>
+#include <linux/slab.h>
+#include <linux/moduleparam.h>
+
+#include "vpu_boot_api.h"
+#include "ivpu_drv.h"
+#include "ivpu_fw.h"
+#include "ivpu_fw_log.h"
+#include "ivpu_gem.h"
+
+#define IVPU_FW_LOG_LINE_LENGTH	256
+
+unsigned int ivpu_fw_log_level = IVPU_FW_LOG_ERROR;
+module_param_named(fw_log_level, ivpu_fw_log_level, uint, 0444);
+MODULE_PARM_DESC(fw_log_level,
+		 "NPU firmware default log level: debug=" __stringify(IVPU_FW_LOG_DEBUG)
+		 " info=" __stringify(IVPU_FW_LOG_INFO)
+		 " warn=" __stringify(IVPU_FW_LOG_WARN)
+		 " error=" __stringify(IVPU_FW_LOG_ERROR)
+		 " fatal=" __stringify(IVPU_FW_LOG_FATAL));
+
+static int fw_log_from_bo(struct ivpu_device *vdev, struct ivpu_bo *bo, u32 *offset,
+			  struct vpu_tracing_buffer_header **out_log)
+{
+	struct vpu_tracing_buffer_header *log;
+
+	if ((*offset + sizeof(*log)) > ivpu_bo_size(bo))
+		return -EINVAL;
+
+	log = ivpu_bo_vaddr(bo) + *offset;
+
+	if (log->vpu_canary_start != VPU_TRACING_BUFFER_CANARY)
+		return -EINVAL;
+
+	if (log->header_size < sizeof(*log) || log->header_size > 1024) {
+		ivpu_dbg(vdev, FW_BOOT, "Invalid header size 0x%x\n", log->header_size);
+		return -EINVAL;
+	}
+	if ((char *)log + log->size > (char *)ivpu_bo_vaddr(bo) + ivpu_bo_size(bo)) {
+		ivpu_dbg(vdev, FW_BOOT, "Invalid log size 0x%x\n", log->size);
+		return -EINVAL;
+	}
+
+	*out_log = log;
+	*offset += log->size;
+
+	ivpu_dbg(vdev, FW_BOOT,
+		 "FW log name \"%s\", write offset 0x%x size 0x%x, wrap count %d, hdr version %d size %d format %d, alignment %d",
+		 log->name, log->write_index, log->size, log->wrap_count, log->header_version,
+		 log->header_size, log->format, log->alignment);
+
+	return 0;
+}
+
+static void fw_log_print_lines(char *buffer, u32 size, struct drm_printer *p)
+{
+	char line[IVPU_FW_LOG_LINE_LENGTH];
+	u32 index = 0;
+
+	if (!size || !buffer)
+		return;
+
+	while (size--) {
+		if (*buffer == '\n' || *buffer == 0) {
+			line[index] = 0;
+			if (index != 0)
+				drm_printf(p, "%s\n", line);
+			index = 0;
+			buffer++;
+			continue;
+		}
+		if (index == IVPU_FW_LOG_LINE_LENGTH - 1) {
+			line[index] = 0;
+			index = 0;
+			drm_printf(p, "%s\n", line);
+		}
+		if (*buffer != '\r' && (isprint(*buffer) || iscntrl(*buffer)))
+			line[index++] = *buffer;
+		buffer++;
+	}
+	line[index] = 0;
+	if (index != 0)
+		drm_printf(p, "%s", line);
+}
+
+static void fw_log_print_buffer(struct vpu_tracing_buffer_header *log, const char *prefix,
+				bool only_new_msgs, struct drm_printer *p)
+{
+	char *log_data = (void *)log + log->header_size;
+	u32 data_size = log->size - log->header_size;
+	u32 log_start = only_new_msgs ? READ_ONCE(log->read_index) : 0;
+	u32 log_end = READ_ONCE(log->write_index);
+
+	if (log->wrap_count == log->read_wrap_count) {
+		if (log_end <= log_start) {
+			drm_printf(p, "==== %s \"%s\" log empty ====\n", prefix, log->name);
+			return;
+		}
+	} else if (log->wrap_count == log->read_wrap_count + 1) {
+		if (log_end > log_start)
+			log_start = log_end;
+	} else {
+		log_start = log_end;
+	}
+
+	drm_printf(p, "==== %s \"%s\" log start ====\n", prefix, log->name);
+	if (log_end > log_start) {
+		fw_log_print_lines(log_data + log_start, log_end - log_start, p);
+	} else {
+		fw_log_print_lines(log_data + log_start, data_size - log_start, p);
+		fw_log_print_lines(log_data, log_end, p);
+	}
+	drm_printf(p, "\n\x1b[0m"); /* add new line and clear formatting */
+	drm_printf(p, "==== %s \"%s\" log end   ====\n", prefix, log->name);
+}
+
+static void
+fw_log_print_all_in_bo(struct ivpu_device *vdev, const char *name,
+		       struct ivpu_bo *bo, bool only_new_msgs, struct drm_printer *p)
+{
+	struct vpu_tracing_buffer_header *log;
+	u32 next = 0;
+
+	while (fw_log_from_bo(vdev, bo, &next, &log) == 0)
+		fw_log_print_buffer(log, name, only_new_msgs, p);
+}
+
+void ivpu_fw_log_print(struct ivpu_device *vdev, bool only_new_msgs, struct drm_printer *p)
+{
+	fw_log_print_all_in_bo(vdev, "NPU critical", vdev->fw->mem_log_crit, only_new_msgs, p);
+	fw_log_print_all_in_bo(vdev, "NPU verbose", vdev->fw->mem_log_verb, only_new_msgs, p);
+}
+
+void ivpu_fw_log_mark_read(struct ivpu_device *vdev)
+{
+	struct vpu_tracing_buffer_header *log;
+	u32 next;
+
+	next = 0;
+	while (fw_log_from_bo(vdev, vdev->fw->mem_log_crit, &next, &log) == 0) {
+		log->read_index = READ_ONCE(log->write_index);
+		log->read_wrap_count = READ_ONCE(log->wrap_count);
+	}
+
+	next = 0;
+	while (fw_log_from_bo(vdev, vdev->fw->mem_log_verb, &next, &log) == 0) {
+		log->read_index = READ_ONCE(log->write_index);
+		log->read_wrap_count = READ_ONCE(log->wrap_count);
+	}
+}
+
+void ivpu_fw_log_reset(struct ivpu_device *vdev)
+{
+	struct vpu_tracing_buffer_header *log;
+	u32 next;
+
+	next = 0;
+	while (fw_log_from_bo(vdev, vdev->fw->mem_log_crit, &next, &log) == 0) {
+		log->read_index = 0;
+		log->read_wrap_count = 0;
+	}
+
+	next = 0;
+	while (fw_log_from_bo(vdev, vdev->fw->mem_log_verb, &next, &log) == 0) {
+		log->read_index = 0;
+		log->read_wrap_count = 0;
+	}
+}
diff --git a/drivers/accel/ivpu/ivpu_fw_log.h b/drivers/accel/ivpu/ivpu_fw_log.h
new file mode 100644
index 000000000000..8bb528a73cb7
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_fw_log.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2020-2024 Intel Corporation
+ */
+
+#ifndef __IVPU_FW_LOG_H__
+#define __IVPU_FW_LOG_H__
+
+#include <linux/types.h>
+
+#include "ivpu_drv.h"
+
+#define IVPU_FW_LOG_DEFAULT 0
+#define IVPU_FW_LOG_DEBUG   1
+#define IVPU_FW_LOG_INFO    2
+#define IVPU_FW_LOG_WARN    3
+#define IVPU_FW_LOG_ERROR   4
+#define IVPU_FW_LOG_FATAL   5
+
+#define IVPU_FW_VERBOSE_BUFFER_SMALL_SIZE	SZ_1M
+#define IVPU_FW_VERBOSE_BUFFER_LARGE_SIZE	SZ_8M
+#define IVPU_FW_CRITICAL_BUFFER_SIZE		SZ_512K
+
+extern unsigned int ivpu_fw_log_level;
+
+void ivpu_fw_log_print(struct ivpu_device *vdev, bool only_new_msgs, struct drm_printer *p);
+void ivpu_fw_log_mark_read(struct ivpu_device *vdev);
+void ivpu_fw_log_reset(struct ivpu_device *vdev);
+
+
+#endif /* __IVPU_FW_LOG_H__ */
diff --git a/drivers/accel/ivpu/ivpu_gem.c b/drivers/accel/ivpu/ivpu_gem.c
new file mode 100644
index 000000000000..ece68f570b7e
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_gem.c
@@ -0,0 +1,579 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020-2023 Intel Corporation
+ */
+
+#include <linux/dma-buf.h>
+#include <linux/highmem.h>
+#include <linux/module.h>
+#include <linux/set_memory.h>
+#include <linux/xarray.h>
+
+#include <drm/drm_cache.h>
+#include <drm/drm_debugfs.h>
+#include <drm/drm_file.h>
+#include <drm/drm_utils.h>
+
+#include "ivpu_drv.h"
+#include "ivpu_fw.h"
+#include "ivpu_gem.h"
+#include "ivpu_hw.h"
+#include "ivpu_mmu.h"
+#include "ivpu_mmu_context.h"
+
+MODULE_IMPORT_NS("DMA_BUF");
+
+static const struct drm_gem_object_funcs ivpu_gem_funcs;
+
+static inline void ivpu_dbg_bo(struct ivpu_device *vdev, struct ivpu_bo *bo, const char *action)
+{
+	ivpu_dbg(vdev, BO,
+		 "%6s: bo %8p size %9zu ctx %d vpu_addr %9llx pages %d sgt %d mmu_mapped %d wc %d imported %d\n",
+		 action, bo, ivpu_bo_size(bo), bo->ctx_id, bo->vpu_addr,
+		 (bool)bo->base.pages, (bool)bo->base.sgt, bo->mmu_mapped, bo->base.map_wc,
+		 (bool)drm_gem_is_imported(&bo->base.base));
+}
+
+static inline int ivpu_bo_lock(struct ivpu_bo *bo)
+{
+	return dma_resv_lock(bo->base.base.resv, NULL);
+}
+
+static inline void ivpu_bo_unlock(struct ivpu_bo *bo)
+{
+	dma_resv_unlock(bo->base.base.resv);
+}
+
+static struct sg_table *ivpu_bo_map_attachment(struct ivpu_device *vdev, struct ivpu_bo *bo)
+{
+	struct sg_table *sgt;
+
+	drm_WARN_ON(&vdev->drm, !bo->base.base.import_attach);
+
+	ivpu_bo_lock(bo);
+
+	sgt = bo->base.sgt;
+	if (!sgt) {
+		sgt = dma_buf_map_attachment(bo->base.base.import_attach, DMA_BIDIRECTIONAL);
+		if (IS_ERR(sgt))
+			ivpu_err(vdev, "Failed to map BO in IOMMU: %ld\n", PTR_ERR(sgt));
+		else
+			bo->base.sgt = sgt;
+	}
+
+	ivpu_bo_unlock(bo);
+
+	return sgt;
+}
+
+/*
+ * ivpu_bo_bind() - pin the backing physical pages and map them to VPU.
+ *
+ * This function pins physical memory pages, then maps the physical pages
+ * to IOMMU address space and finally updates the VPU MMU page tables
+ * to allow the VPU to translate VPU address to IOMMU address.
+ */
+int __must_check ivpu_bo_bind(struct ivpu_bo *bo)
+{
+	struct ivpu_device *vdev = ivpu_bo_to_vdev(bo);
+	struct sg_table *sgt;
+	int ret = 0;
+
+	ivpu_dbg_bo(vdev, bo, "bind");
+
+	if (bo->base.base.import_attach)
+		sgt = ivpu_bo_map_attachment(vdev, bo);
+	else
+		sgt = drm_gem_shmem_get_pages_sgt(&bo->base);
+	if (IS_ERR(sgt)) {
+		ret = PTR_ERR(sgt);
+		ivpu_err(vdev, "Failed to map BO in IOMMU: %d\n", ret);
+		return ret;
+	}
+
+	ivpu_bo_lock(bo);
+
+	if (!bo->mmu_mapped) {
+		drm_WARN_ON(&vdev->drm, !bo->ctx);
+		ret = ivpu_mmu_context_map_sgt(vdev, bo->ctx, bo->vpu_addr, sgt,
+					       ivpu_bo_is_snooped(bo), ivpu_bo_is_read_only(bo));
+		if (ret) {
+			ivpu_err(vdev, "Failed to map BO in MMU: %d\n", ret);
+			goto unlock;
+		}
+		bo->mmu_mapped = true;
+	}
+
+unlock:
+	ivpu_bo_unlock(bo);
+
+	return ret;
+}
+
+static int
+ivpu_bo_alloc_vpu_addr(struct ivpu_bo *bo, struct ivpu_mmu_context *ctx,
+		       const struct ivpu_addr_range *range)
+{
+	struct ivpu_device *vdev = ivpu_bo_to_vdev(bo);
+	int idx, ret;
+
+	if (!drm_dev_enter(&vdev->drm, &idx))
+		return -ENODEV;
+
+	ivpu_bo_lock(bo);
+
+	ret = ivpu_mmu_context_insert_node(ctx, range, ivpu_bo_size(bo), &bo->mm_node);
+	if (!ret) {
+		bo->ctx = ctx;
+		bo->ctx_id = ctx->id;
+		bo->vpu_addr = bo->mm_node.start;
+		ivpu_dbg_bo(vdev, bo, "vaddr");
+	}
+
+	ivpu_bo_unlock(bo);
+
+	drm_dev_exit(idx);
+
+	return ret;
+}
+
+static void ivpu_bo_unbind_locked(struct ivpu_bo *bo)
+{
+	struct ivpu_device *vdev = ivpu_bo_to_vdev(bo);
+
+	dma_resv_assert_held(bo->base.base.resv);
+
+	if (bo->mmu_mapped) {
+		drm_WARN_ON(&vdev->drm, !bo->ctx);
+		drm_WARN_ON(&vdev->drm, !bo->vpu_addr);
+		drm_WARN_ON(&vdev->drm, !bo->base.sgt);
+		ivpu_mmu_context_unmap_sgt(vdev, bo->ctx, bo->vpu_addr, bo->base.sgt);
+		bo->mmu_mapped = false;
+	}
+
+	if (bo->ctx) {
+		ivpu_mmu_context_remove_node(bo->ctx, &bo->mm_node);
+		bo->ctx = NULL;
+	}
+
+	if (bo->base.sgt) {
+		if (bo->base.base.import_attach) {
+			dma_buf_unmap_attachment(bo->base.base.import_attach,
+						 bo->base.sgt, DMA_BIDIRECTIONAL);
+		} else {
+			dma_unmap_sgtable(vdev->drm.dev, bo->base.sgt, DMA_BIDIRECTIONAL, 0);
+			sg_free_table(bo->base.sgt);
+			kfree(bo->base.sgt);
+		}
+		bo->base.sgt = NULL;
+	}
+}
+
+void ivpu_bo_unbind_all_bos_from_context(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx)
+{
+	struct ivpu_bo *bo;
+
+	if (drm_WARN_ON(&vdev->drm, !ctx))
+		return;
+
+	mutex_lock(&vdev->bo_list_lock);
+	list_for_each_entry(bo, &vdev->bo_list, bo_list_node) {
+		ivpu_bo_lock(bo);
+		if (bo->ctx == ctx) {
+			ivpu_dbg_bo(vdev, bo, "unbind");
+			ivpu_bo_unbind_locked(bo);
+		}
+		ivpu_bo_unlock(bo);
+	}
+	mutex_unlock(&vdev->bo_list_lock);
+}
+
+struct drm_gem_object *ivpu_gem_create_object(struct drm_device *dev, size_t size)
+{
+	struct ivpu_bo *bo;
+
+	if (size == 0 || !PAGE_ALIGNED(size))
+		return ERR_PTR(-EINVAL);
+
+	bo = kzalloc(sizeof(*bo), GFP_KERNEL);
+	if (!bo)
+		return ERR_PTR(-ENOMEM);
+
+	bo->base.base.funcs = &ivpu_gem_funcs;
+	bo->base.pages_mark_dirty_on_put = true; /* VPU can dirty a BO anytime */
+
+	INIT_LIST_HEAD(&bo->bo_list_node);
+
+	return &bo->base.base;
+}
+
+struct drm_gem_object *ivpu_gem_prime_import(struct drm_device *dev,
+					     struct dma_buf *dma_buf)
+{
+	struct ivpu_device *vdev = to_ivpu_device(dev);
+	struct device *attach_dev = dev->dev;
+	struct dma_buf_attachment *attach;
+	struct drm_gem_object *obj;
+	struct ivpu_bo *bo;
+	int ret;
+
+	attach = dma_buf_attach(dma_buf, attach_dev);
+	if (IS_ERR(attach))
+		return ERR_CAST(attach);
+
+	get_dma_buf(dma_buf);
+
+	obj = drm_gem_shmem_prime_import_sg_table(dev, attach, NULL);
+	if (IS_ERR(obj)) {
+		ret = PTR_ERR(obj);
+		goto fail_detach;
+	}
+
+	obj->import_attach = attach;
+	obj->resv = dma_buf->resv;
+
+	bo = to_ivpu_bo(obj);
+
+	mutex_lock(&vdev->bo_list_lock);
+	list_add_tail(&bo->bo_list_node, &vdev->bo_list);
+	mutex_unlock(&vdev->bo_list_lock);
+
+	ivpu_dbg(vdev, BO, "import: bo %8p size %9zu\n", bo, ivpu_bo_size(bo));
+
+	return obj;
+
+fail_detach:
+	dma_buf_detach(dma_buf, attach);
+	dma_buf_put(dma_buf);
+
+	return ERR_PTR(ret);
+}
+
+static struct ivpu_bo *ivpu_bo_alloc(struct ivpu_device *vdev, u64 size, u32 flags)
+{
+	struct drm_gem_shmem_object *shmem;
+	struct ivpu_bo *bo;
+
+	switch (flags & DRM_IVPU_BO_CACHE_MASK) {
+	case DRM_IVPU_BO_CACHED:
+	case DRM_IVPU_BO_WC:
+		break;
+	default:
+		return ERR_PTR(-EINVAL);
+	}
+
+	shmem = drm_gem_shmem_create(&vdev->drm, size);
+	if (IS_ERR(shmem))
+		return ERR_CAST(shmem);
+
+	bo = to_ivpu_bo(&shmem->base);
+	bo->base.map_wc = flags & DRM_IVPU_BO_WC;
+	bo->flags = flags;
+
+	mutex_lock(&vdev->bo_list_lock);
+	list_add_tail(&bo->bo_list_node, &vdev->bo_list);
+	mutex_unlock(&vdev->bo_list_lock);
+
+	ivpu_dbg(vdev, BO, " alloc: bo %8p size %9llu\n", bo, size);
+
+	return bo;
+}
+
+static int ivpu_gem_bo_open(struct drm_gem_object *obj, struct drm_file *file)
+{
+	struct ivpu_file_priv *file_priv = file->driver_priv;
+	struct ivpu_device *vdev = file_priv->vdev;
+	struct ivpu_bo *bo = to_ivpu_bo(obj);
+	struct ivpu_addr_range *range;
+
+	if (bo->ctx) {
+		ivpu_dbg(vdev, IOCTL, "Can't add BO %pe to ctx %u: already in ctx %u\n",
+			 bo, file_priv->ctx.id, bo->ctx->id);
+		return -EALREADY;
+	}
+
+	if (bo->flags & DRM_IVPU_BO_SHAVE_MEM)
+		range = &vdev->hw->ranges.shave;
+	else if (bo->flags & DRM_IVPU_BO_DMA_MEM)
+		range = &vdev->hw->ranges.dma;
+	else
+		range = &vdev->hw->ranges.user;
+
+	return ivpu_bo_alloc_vpu_addr(bo, &file_priv->ctx, range);
+}
+
+static void ivpu_gem_bo_free(struct drm_gem_object *obj)
+{
+	struct ivpu_device *vdev = to_ivpu_device(obj->dev);
+	struct ivpu_bo *bo = to_ivpu_bo(obj);
+
+	ivpu_dbg_bo(vdev, bo, "free");
+
+	drm_WARN_ON(&vdev->drm, list_empty(&bo->bo_list_node));
+
+	mutex_lock(&vdev->bo_list_lock);
+	list_del(&bo->bo_list_node);
+
+	drm_WARN_ON(&vdev->drm, !drm_gem_is_imported(&bo->base.base) &&
+		    !dma_resv_test_signaled(obj->resv, DMA_RESV_USAGE_READ));
+	drm_WARN_ON(&vdev->drm, ivpu_bo_size(bo) == 0);
+	drm_WARN_ON(&vdev->drm, bo->base.vaddr);
+
+	ivpu_bo_lock(bo);
+	ivpu_bo_unbind_locked(bo);
+	ivpu_bo_unlock(bo);
+
+	mutex_unlock(&vdev->bo_list_lock);
+
+	drm_WARN_ON(&vdev->drm, bo->mmu_mapped);
+	drm_WARN_ON(&vdev->drm, bo->ctx);
+
+	drm_WARN_ON(obj->dev, refcount_read(&bo->base.pages_use_count) > 1);
+	drm_WARN_ON(obj->dev, bo->base.base.vma_node.vm_files.rb_node);
+	drm_gem_shmem_free(&bo->base);
+}
+
+static enum drm_gem_object_status ivpu_gem_status(struct drm_gem_object *obj)
+{
+	struct ivpu_bo *bo = to_ivpu_bo(obj);
+	enum drm_gem_object_status status = 0;
+
+	if (ivpu_bo_is_resident(bo))
+		status |= DRM_GEM_OBJECT_RESIDENT;
+
+	return status;
+}
+
+static const struct drm_gem_object_funcs ivpu_gem_funcs = {
+	.free = ivpu_gem_bo_free,
+	.open = ivpu_gem_bo_open,
+	.print_info = drm_gem_shmem_object_print_info,
+	.pin = drm_gem_shmem_object_pin,
+	.unpin = drm_gem_shmem_object_unpin,
+	.get_sg_table = drm_gem_shmem_object_get_sg_table,
+	.vmap = drm_gem_shmem_object_vmap,
+	.vunmap = drm_gem_shmem_object_vunmap,
+	.mmap = drm_gem_shmem_object_mmap,
+	.status = ivpu_gem_status,
+	.vm_ops = &drm_gem_shmem_vm_ops,
+};
+
+int ivpu_bo_create_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
+{
+	struct ivpu_file_priv *file_priv = file->driver_priv;
+	struct ivpu_device *vdev = file_priv->vdev;
+	struct drm_ivpu_bo_create *args = data;
+	u64 size = PAGE_ALIGN(args->size);
+	struct ivpu_bo *bo;
+	int ret;
+
+	if (args->flags & ~DRM_IVPU_BO_FLAGS) {
+		ivpu_dbg(vdev, IOCTL, "Invalid BO flags 0x%x\n", args->flags);
+		return -EINVAL;
+	}
+
+	if (size == 0) {
+		ivpu_dbg(vdev, IOCTL, "Invalid BO size %llu\n", args->size);
+		return -EINVAL;
+	}
+
+	bo = ivpu_bo_alloc(vdev, size, args->flags);
+	if (IS_ERR(bo)) {
+		ivpu_dbg(vdev, IOCTL, "Failed to allocate BO: %pe ctx %u size %llu flags 0x%x\n",
+			 bo, file_priv->ctx.id, args->size, args->flags);
+		return PTR_ERR(bo);
+	}
+
+	drm_WARN_ON(&vdev->drm, bo->base.base.handle_count != 0);
+
+	ret = drm_gem_handle_create(file, &bo->base.base, &args->handle);
+	if (ret) {
+		ivpu_dbg(vdev, IOCTL, "Failed to create handle for BO: %pe ctx %u size %llu flags 0x%x\n",
+			 bo, file_priv->ctx.id, args->size, args->flags);
+	} else {
+		args->vpu_addr = bo->vpu_addr;
+		drm_WARN_ON(&vdev->drm, bo->base.base.handle_count != 1);
+	}
+
+	drm_gem_object_put(&bo->base.base);
+
+	return ret;
+}
+
+struct ivpu_bo *
+ivpu_bo_create(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx,
+	       struct ivpu_addr_range *range, u64 size, u32 flags)
+{
+	struct iosys_map map;
+	struct ivpu_bo *bo;
+	int ret;
+
+	if (drm_WARN_ON(&vdev->drm, !range))
+		return NULL;
+
+	drm_WARN_ON(&vdev->drm, !PAGE_ALIGNED(range->start));
+	drm_WARN_ON(&vdev->drm, !PAGE_ALIGNED(range->end));
+	drm_WARN_ON(&vdev->drm, !PAGE_ALIGNED(size));
+
+	bo = ivpu_bo_alloc(vdev, size, flags);
+	if (IS_ERR(bo)) {
+		ivpu_err(vdev, "Failed to allocate BO: %pe vpu_addr 0x%llx size %llu flags 0x%x\n",
+			 bo, range->start, size, flags);
+		return NULL;
+	}
+
+	ret = ivpu_bo_alloc_vpu_addr(bo, ctx, range);
+	if (ret) {
+		ivpu_err(vdev, "Failed to allocate NPU address for BO: %pe ctx %u size %llu: %d\n",
+			 bo, ctx->id, size, ret);
+		goto err_put;
+	}
+
+	ret = ivpu_bo_bind(bo);
+	if (ret)
+		goto err_put;
+
+	if (flags & DRM_IVPU_BO_MAPPABLE) {
+		ivpu_bo_lock(bo);
+		ret = drm_gem_shmem_vmap_locked(&bo->base, &map);
+		ivpu_bo_unlock(bo);
+
+		if (ret)
+			goto err_put;
+	}
+
+	return bo;
+
+err_put:
+	drm_gem_object_put(&bo->base.base);
+	return NULL;
+}
+
+struct ivpu_bo *ivpu_bo_create_runtime(struct ivpu_device *vdev, u64 addr, u64 size, u32 flags)
+{
+	struct ivpu_addr_range range;
+
+	if (!ivpu_is_within_range(addr, size, &vdev->hw->ranges.runtime)) {
+		ivpu_err(vdev, "Invalid runtime BO address 0x%llx size %llu\n", addr, size);
+		return NULL;
+	}
+
+	if (ivpu_hw_range_init(vdev, &range, addr, size))
+		return NULL;
+
+	return ivpu_bo_create(vdev, &vdev->gctx, &range, size, flags);
+}
+
+struct ivpu_bo *ivpu_bo_create_global(struct ivpu_device *vdev, u64 size, u32 flags)
+{
+	return ivpu_bo_create(vdev, &vdev->gctx, &vdev->hw->ranges.global, size, flags);
+}
+
+void ivpu_bo_free(struct ivpu_bo *bo)
+{
+	struct iosys_map map = IOSYS_MAP_INIT_VADDR(bo->base.vaddr);
+
+	if (bo->flags & DRM_IVPU_BO_MAPPABLE) {
+		ivpu_bo_lock(bo);
+		drm_gem_shmem_vunmap_locked(&bo->base, &map);
+		ivpu_bo_unlock(bo);
+	}
+
+	drm_gem_object_put(&bo->base.base);
+}
+
+int ivpu_bo_info_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
+{
+	struct drm_ivpu_bo_info *args = data;
+	struct drm_gem_object *obj;
+	struct ivpu_bo *bo;
+	int ret = 0;
+
+	obj = drm_gem_object_lookup(file, args->handle);
+	if (!obj)
+		return -ENOENT;
+
+	bo = to_ivpu_bo(obj);
+
+	ivpu_bo_lock(bo);
+	args->flags = bo->flags;
+	args->mmap_offset = drm_vma_node_offset_addr(&obj->vma_node);
+	args->vpu_addr = bo->vpu_addr;
+	args->size = obj->size;
+	ivpu_bo_unlock(bo);
+
+	drm_gem_object_put(obj);
+	return ret;
+}
+
+int ivpu_bo_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
+{
+	struct drm_ivpu_bo_wait *args = data;
+	struct drm_gem_object *obj;
+	unsigned long timeout;
+	long ret;
+
+	timeout = drm_timeout_abs_to_jiffies(args->timeout_ns);
+
+	/* Add 1 jiffy to ensure the wait function never times out before intended timeout_ns */
+	timeout += 1;
+
+	obj = drm_gem_object_lookup(file, args->handle);
+	if (!obj)
+		return -EINVAL;
+
+	ret = dma_resv_wait_timeout(obj->resv, DMA_RESV_USAGE_READ, true, timeout);
+	if (ret == 0) {
+		ret = -ETIMEDOUT;
+	} else if (ret > 0) {
+		ret = 0;
+		args->job_status = to_ivpu_bo(obj)->job_status;
+	}
+
+	drm_gem_object_put(obj);
+
+	return ret;
+}
+
+static void ivpu_bo_print_info(struct ivpu_bo *bo, struct drm_printer *p)
+{
+	ivpu_bo_lock(bo);
+
+	drm_printf(p, "%-9p %-3u 0x%-12llx %-10lu 0x%-8x %-4u",
+		   bo, bo->ctx_id, bo->vpu_addr, bo->base.base.size,
+		   bo->flags, kref_read(&bo->base.base.refcount));
+
+	if (bo->base.pages)
+		drm_printf(p, " has_pages");
+
+	if (bo->mmu_mapped)
+		drm_printf(p, " mmu_mapped");
+
+	if (drm_gem_is_imported(&bo->base.base))
+		drm_printf(p, " imported");
+
+	drm_printf(p, "\n");
+
+	ivpu_bo_unlock(bo);
+}
+
+void ivpu_bo_list(struct drm_device *dev, struct drm_printer *p)
+{
+	struct ivpu_device *vdev = to_ivpu_device(dev);
+	struct ivpu_bo *bo;
+
+	drm_printf(p, "%-9s %-3s %-14s %-10s %-10s %-4s %s\n",
+		   "bo", "ctx", "vpu_addr", "size", "flags", "refs", "attribs");
+
+	mutex_lock(&vdev->bo_list_lock);
+	list_for_each_entry(bo, &vdev->bo_list, bo_list_node)
+		ivpu_bo_print_info(bo, p);
+	mutex_unlock(&vdev->bo_list_lock);
+}
+
+void ivpu_bo_list_print(struct drm_device *dev)
+{
+	struct drm_printer p = drm_info_printer(dev->dev);
+
+	ivpu_bo_list(dev, &p);
+}
diff --git a/drivers/accel/ivpu/ivpu_gem.h b/drivers/accel/ivpu/ivpu_gem.h
new file mode 100644
index 000000000000..0c3350f22b55
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_gem.h
@@ -0,0 +1,117 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2020-2025 Intel Corporation
+ */
+#ifndef __IVPU_GEM_H__
+#define __IVPU_GEM_H__
+
+#include <drm/drm_gem.h>
+#include <drm/drm_gem_shmem_helper.h>
+#include <drm/drm_mm.h>
+
+struct ivpu_file_priv;
+
+struct ivpu_bo {
+	struct drm_gem_shmem_object base;
+	struct ivpu_mmu_context *ctx;
+	struct list_head bo_list_node;
+	struct drm_mm_node mm_node;
+
+	u64 vpu_addr;
+	u32 flags;
+	u32 job_status; /* Valid only for command buffer */
+	u32 ctx_id;
+	bool mmu_mapped;
+};
+
+int ivpu_bo_bind(struct ivpu_bo *bo);
+void ivpu_bo_unbind_all_bos_from_context(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx);
+
+struct drm_gem_object *ivpu_gem_create_object(struct drm_device *dev, size_t size);
+struct drm_gem_object *ivpu_gem_prime_import(struct drm_device *dev, struct dma_buf *dma_buf);
+struct ivpu_bo *ivpu_bo_create(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx,
+			       struct ivpu_addr_range *range, u64 size, u32 flags);
+struct ivpu_bo *ivpu_bo_create_runtime(struct ivpu_device *vdev, u64 addr, u64 size, u32 flags);
+struct ivpu_bo *ivpu_bo_create_global(struct ivpu_device *vdev, u64 size, u32 flags);
+void ivpu_bo_free(struct ivpu_bo *bo);
+
+int ivpu_bo_create_ioctl(struct drm_device *dev, void *data, struct drm_file *file);
+int ivpu_bo_info_ioctl(struct drm_device *dev, void *data, struct drm_file *file);
+int ivpu_bo_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file);
+int ivpu_bo_create_from_userptr_ioctl(struct drm_device *dev, void *data,
+				      struct drm_file *file);
+
+void ivpu_bo_list(struct drm_device *dev, struct drm_printer *p);
+void ivpu_bo_list_print(struct drm_device *dev);
+
+static inline struct ivpu_bo *to_ivpu_bo(struct drm_gem_object *obj)
+{
+	return container_of(obj, struct ivpu_bo, base.base);
+}
+
+static inline void *ivpu_bo_vaddr(struct ivpu_bo *bo)
+{
+	return bo->base.vaddr;
+}
+
+static inline size_t ivpu_bo_size(struct ivpu_bo *bo)
+{
+	return bo->base.base.size;
+}
+
+static inline u32 ivpu_bo_cache_mode(struct ivpu_bo *bo)
+{
+	return bo->flags & DRM_IVPU_BO_CACHE_MASK;
+}
+
+static inline struct ivpu_device *ivpu_bo_to_vdev(struct ivpu_bo *bo)
+{
+	return to_ivpu_device(bo->base.base.dev);
+}
+
+static inline bool ivpu_bo_is_snooped(struct ivpu_bo *bo)
+{
+	if (ivpu_is_force_snoop_enabled(ivpu_bo_to_vdev(bo)))
+		return true;
+
+	return ivpu_bo_cache_mode(bo) == DRM_IVPU_BO_CACHED;
+}
+
+static inline bool ivpu_bo_is_read_only(struct ivpu_bo *bo)
+{
+	return bo->flags & DRM_IVPU_BO_READ_ONLY;
+}
+
+static inline bool ivpu_bo_is_resident(struct ivpu_bo *bo)
+{
+	return !!bo->base.pages;
+}
+
+static inline void *ivpu_to_cpu_addr(struct ivpu_bo *bo, u32 vpu_addr)
+{
+	if (vpu_addr < bo->vpu_addr)
+		return NULL;
+
+	if (vpu_addr >= (bo->vpu_addr + ivpu_bo_size(bo)))
+		return NULL;
+
+	return ivpu_bo_vaddr(bo) + (vpu_addr - bo->vpu_addr);
+}
+
+static inline u32 cpu_to_vpu_addr(struct ivpu_bo *bo, void *cpu_addr)
+{
+	if (cpu_addr < ivpu_bo_vaddr(bo))
+		return 0;
+
+	if (cpu_addr >= (ivpu_bo_vaddr(bo) + ivpu_bo_size(bo)))
+		return 0;
+
+	return bo->vpu_addr + (cpu_addr - ivpu_bo_vaddr(bo));
+}
+
+static inline bool ivpu_bo_is_mappable(struct ivpu_bo *bo)
+{
+	return bo->flags & DRM_IVPU_BO_MAPPABLE;
+}
+
+#endif /* __IVPU_GEM_H__ */
diff --git a/drivers/accel/ivpu/ivpu_gem_userptr.c b/drivers/accel/ivpu/ivpu_gem_userptr.c
new file mode 100644
index 000000000000..25ba606164c0
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_gem_userptr.c
@@ -0,0 +1,213 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020-2025 Intel Corporation
+ */
+
+#include <linux/dma-buf.h>
+#include <linux/err.h>
+#include <linux/highmem.h>
+#include <linux/mm.h>
+#include <linux/mman.h>
+#include <linux/scatterlist.h>
+#include <linux/slab.h>
+#include <linux/capability.h>
+
+#include <drm/drm_device.h>
+#include <drm/drm_file.h>
+#include <drm/drm_gem.h>
+
+#include "ivpu_drv.h"
+#include "ivpu_gem.h"
+
+static struct sg_table *
+ivpu_gem_userptr_dmabuf_map(struct dma_buf_attachment *attachment,
+			    enum dma_data_direction direction)
+{
+	struct sg_table *sgt = attachment->dmabuf->priv;
+	int ret;
+
+	ret = dma_map_sgtable(attachment->dev, sgt, direction, DMA_ATTR_SKIP_CPU_SYNC);
+	if (ret)
+		return ERR_PTR(ret);
+
+	return sgt;
+}
+
+static void ivpu_gem_userptr_dmabuf_unmap(struct dma_buf_attachment *attachment,
+					  struct sg_table *sgt,
+					  enum dma_data_direction direction)
+{
+	dma_unmap_sgtable(attachment->dev, sgt, direction, DMA_ATTR_SKIP_CPU_SYNC);
+}
+
+static void ivpu_gem_userptr_dmabuf_release(struct dma_buf *dma_buf)
+{
+	struct sg_table *sgt = dma_buf->priv;
+	struct sg_page_iter page_iter;
+	struct page *page;
+
+	for_each_sgtable_page(sgt, &page_iter, 0) {
+		page = sg_page_iter_page(&page_iter);
+		unpin_user_page(page);
+	}
+
+	sg_free_table(sgt);
+	kfree(sgt);
+}
+
+static const struct dma_buf_ops ivpu_gem_userptr_dmabuf_ops = {
+	.map_dma_buf = ivpu_gem_userptr_dmabuf_map,
+	.unmap_dma_buf = ivpu_gem_userptr_dmabuf_unmap,
+	.release = ivpu_gem_userptr_dmabuf_release,
+};
+
+static struct dma_buf *
+ivpu_create_userptr_dmabuf(struct ivpu_device *vdev, void __user *user_ptr,
+			   size_t size, uint32_t flags)
+{
+	struct dma_buf_export_info exp_info = {};
+	struct dma_buf *dma_buf;
+	struct sg_table *sgt;
+	struct page **pages;
+	unsigned long nr_pages = size >> PAGE_SHIFT;
+	unsigned int gup_flags = FOLL_LONGTERM;
+	int ret, i, pinned;
+
+	/* Add FOLL_WRITE only if the BO is not read-only */
+	if (!(flags & DRM_IVPU_BO_READ_ONLY))
+		gup_flags |= FOLL_WRITE;
+
+	pages = kvmalloc_array(nr_pages, sizeof(*pages), GFP_KERNEL);
+	if (!pages)
+		return ERR_PTR(-ENOMEM);
+
+	pinned = pin_user_pages_fast((unsigned long)user_ptr, nr_pages, gup_flags, pages);
+	if (pinned < 0) {
+		ret = pinned;
+		ivpu_dbg(vdev, IOCTL, "Failed to pin user pages: %d\n", ret);
+		goto free_pages_array;
+	}
+
+	if (pinned != nr_pages) {
+		ivpu_dbg(vdev, IOCTL, "Pinned %d pages, expected %lu\n", pinned, nr_pages);
+		ret = -EFAULT;
+		goto unpin_pages;
+	}
+
+	sgt = kmalloc(sizeof(*sgt), GFP_KERNEL);
+	if (!sgt) {
+		ret = -ENOMEM;
+		goto unpin_pages;
+	}
+
+	ret = sg_alloc_table_from_pages(sgt, pages, nr_pages, 0, size, GFP_KERNEL);
+	if (ret) {
+		ivpu_dbg(vdev, IOCTL, "Failed to create sg table: %d\n", ret);
+		goto free_sgt;
+	}
+
+	exp_info.exp_name = "ivpu_userptr_dmabuf";
+	exp_info.owner = THIS_MODULE;
+	exp_info.ops = &ivpu_gem_userptr_dmabuf_ops;
+	exp_info.size = size;
+	exp_info.flags = O_RDWR | O_CLOEXEC;
+	exp_info.priv = sgt;
+
+	dma_buf = dma_buf_export(&exp_info);
+	if (IS_ERR(dma_buf)) {
+		ret = PTR_ERR(dma_buf);
+		ivpu_dbg(vdev, IOCTL, "Failed to export userptr dma-buf: %d\n", ret);
+		goto free_sg_table;
+	}
+
+	kvfree(pages);
+	return dma_buf;
+
+free_sg_table:
+	sg_free_table(sgt);
+free_sgt:
+	kfree(sgt);
+unpin_pages:
+	for (i = 0; i < pinned; i++)
+		unpin_user_page(pages[i]);
+free_pages_array:
+	kvfree(pages);
+	return ERR_PTR(ret);
+}
+
+static struct ivpu_bo *
+ivpu_bo_create_from_userptr(struct ivpu_device *vdev, void __user *user_ptr,
+			    size_t size, uint32_t flags)
+{
+	struct dma_buf *dma_buf;
+	struct drm_gem_object *obj;
+	struct ivpu_bo *bo;
+
+	dma_buf = ivpu_create_userptr_dmabuf(vdev, user_ptr, size, flags);
+	if (IS_ERR(dma_buf))
+		return ERR_CAST(dma_buf);
+
+	obj = ivpu_gem_prime_import(&vdev->drm, dma_buf);
+	if (IS_ERR(obj)) {
+		dma_buf_put(dma_buf);
+		return ERR_CAST(obj);
+	}
+
+	dma_buf_put(dma_buf);
+
+	bo = to_ivpu_bo(obj);
+	bo->flags = flags;
+
+	return bo;
+}
+
+int ivpu_bo_create_from_userptr_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
+{
+	struct drm_ivpu_bo_create_from_userptr *args = data;
+	struct ivpu_file_priv *file_priv = file->driver_priv;
+	struct ivpu_device *vdev = to_ivpu_device(dev);
+	void __user *user_ptr = u64_to_user_ptr(args->user_ptr);
+	struct ivpu_bo *bo;
+	int ret;
+
+	if (args->flags & ~(DRM_IVPU_BO_HIGH_MEM | DRM_IVPU_BO_DMA_MEM | DRM_IVPU_BO_READ_ONLY)) {
+		ivpu_dbg(vdev, IOCTL, "Invalid BO flags: 0x%x\n", args->flags);
+		return -EINVAL;
+	}
+
+	if (!args->user_ptr || !args->size) {
+		ivpu_dbg(vdev, IOCTL, "Userptr or size are zero: ptr %llx size %llu\n",
+			 args->user_ptr, args->size);
+		return -EINVAL;
+	}
+
+	if (!PAGE_ALIGNED(args->user_ptr) || !PAGE_ALIGNED(args->size)) {
+		ivpu_dbg(vdev, IOCTL, "Userptr or size not page aligned: ptr %llx size %llu\n",
+			 args->user_ptr, args->size);
+		return -EINVAL;
+	}
+
+	if (!access_ok(user_ptr, args->size)) {
+		ivpu_dbg(vdev, IOCTL, "Userptr is not accessible: ptr %llx size %llu\n",
+			 args->user_ptr, args->size);
+		return -EFAULT;
+	}
+
+	bo = ivpu_bo_create_from_userptr(vdev, user_ptr, args->size, args->flags);
+	if (IS_ERR(bo))
+		return PTR_ERR(bo);
+
+	ret = drm_gem_handle_create(file, &bo->base.base, &args->handle);
+	if (ret) {
+		ivpu_dbg(vdev, IOCTL, "Failed to create handle for BO: %pe ctx %u size %llu flags 0x%x\n",
+			 bo, file_priv->ctx.id, args->size, args->flags);
+	} else {
+		ivpu_dbg(vdev, BO, "Created userptr BO: handle=%u vpu_addr=0x%llx size=%llu flags=0x%x\n",
+			 args->handle, bo->vpu_addr, args->size, bo->flags);
+		args->vpu_addr = bo->vpu_addr;
+	}
+
+	drm_gem_object_put(&bo->base.base);
+
+	return ret;
+}
diff --git a/drivers/accel/ivpu/ivpu_hw.c b/drivers/accel/ivpu/ivpu_hw.c
new file mode 100644
index 000000000000..d69cd0d93569
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_hw.c
@@ -0,0 +1,420 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020 - 2024 Intel Corporation
+ */
+
+#include "ivpu_drv.h"
+#include "ivpu_hw.h"
+#include "ivpu_hw_btrs.h"
+#include "ivpu_hw_ip.h"
+
+#include <asm/msr-index.h>
+#include <asm/msr.h>
+#include <linux/dmi.h>
+#include <linux/fault-inject.h>
+#include <linux/pm_runtime.h>
+
+#ifdef CONFIG_FAULT_INJECTION
+DECLARE_FAULT_ATTR(ivpu_hw_failure);
+
+static char *ivpu_fail_hw;
+module_param_named_unsafe(fail_hw, ivpu_fail_hw, charp, 0444);
+MODULE_PARM_DESC(fail_hw, "<interval>,<probability>,<space>,<times>");
+#endif
+
+#define FW_SHARED_MEM_ALIGNMENT	SZ_512K /* VPU MTRR limitation */
+
+#define ECC_MCA_SIGNAL_ENABLE_MASK	0xff
+
+static char *platform_to_str(u32 platform)
+{
+	switch (platform) {
+	case IVPU_PLATFORM_SILICON:
+		return "SILICON";
+	case IVPU_PLATFORM_SIMICS:
+		return "SIMICS";
+	case IVPU_PLATFORM_FPGA:
+		return "FPGA";
+	case IVPU_PLATFORM_HSLE:
+		return "HSLE";
+	default:
+		return "Invalid platform";
+	}
+}
+
+static void platform_init(struct ivpu_device *vdev)
+{
+	int platform = ivpu_hw_btrs_platform_read(vdev);
+
+	ivpu_dbg(vdev, MISC, "Platform type: %s (%d)\n", platform_to_str(platform), platform);
+
+	switch (platform) {
+	case IVPU_PLATFORM_SILICON:
+	case IVPU_PLATFORM_SIMICS:
+	case IVPU_PLATFORM_FPGA:
+	case IVPU_PLATFORM_HSLE:
+		vdev->platform = platform;
+		break;
+
+	default:
+		ivpu_err(vdev, "Invalid platform type: %d\n", platform);
+		break;
+	}
+}
+
+static void wa_init(struct ivpu_device *vdev)
+{
+	vdev->wa.punit_disabled = false;
+	vdev->wa.clear_runtime_mem = false;
+
+	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
+		vdev->wa.interrupt_clear_with_0 = ivpu_hw_btrs_irqs_clear_with_0_mtl(vdev);
+
+	if (ivpu_device_id(vdev) == PCI_DEVICE_ID_LNL &&
+	    ivpu_revision(vdev) < IVPU_HW_IP_REV_LNL_B0)
+		vdev->wa.disable_clock_relinquish = true;
+
+	if (ivpu_test_mode & IVPU_TEST_MODE_CLK_RELINQ_ENABLE)
+		vdev->wa.disable_clock_relinquish = false;
+
+	if (ivpu_test_mode & IVPU_TEST_MODE_CLK_RELINQ_DISABLE)
+		vdev->wa.disable_clock_relinquish = true;
+
+	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
+		vdev->wa.wp0_during_power_up = true;
+
+	if (ivpu_test_mode & IVPU_TEST_MODE_D0I2_DISABLE)
+		vdev->wa.disable_d0i2 = true;
+
+	IVPU_PRINT_WA(punit_disabled);
+	IVPU_PRINT_WA(clear_runtime_mem);
+	IVPU_PRINT_WA(interrupt_clear_with_0);
+	IVPU_PRINT_WA(disable_clock_relinquish);
+	IVPU_PRINT_WA(wp0_during_power_up);
+	IVPU_PRINT_WA(disable_d0i2);
+}
+
+static void timeouts_init(struct ivpu_device *vdev)
+{
+	if (ivpu_test_mode & IVPU_TEST_MODE_DISABLE_TIMEOUTS) {
+		vdev->timeout.boot = -1;
+		vdev->timeout.jsm = -1;
+		vdev->timeout.tdr = -1;
+		vdev->timeout.inference = -1;
+		vdev->timeout.autosuspend = -1;
+		vdev->timeout.d0i3_entry_msg = -1;
+	} else if (ivpu_is_fpga(vdev)) {
+		vdev->timeout.boot = 50;
+		vdev->timeout.jsm = 15000;
+		vdev->timeout.tdr = 30000;
+		vdev->timeout.inference = 900000;
+		vdev->timeout.autosuspend = -1;
+		vdev->timeout.d0i3_entry_msg = 500;
+		vdev->timeout.state_dump_msg = 10000;
+	} else if (ivpu_is_simics(vdev)) {
+		vdev->timeout.boot = 50;
+		vdev->timeout.jsm = 500;
+		vdev->timeout.tdr = 10000;
+		vdev->timeout.inference = 300000;
+		vdev->timeout.autosuspend = 100;
+		vdev->timeout.d0i3_entry_msg = 100;
+		vdev->timeout.state_dump_msg = 10;
+	} else {
+		vdev->timeout.boot = 1000;
+		vdev->timeout.jsm = 500;
+		vdev->timeout.tdr = 2000;
+		vdev->timeout.inference = 60000;
+		if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
+			vdev->timeout.autosuspend = 10;
+		else
+			vdev->timeout.autosuspend = 100;
+		vdev->timeout.d0i3_entry_msg = 5;
+		vdev->timeout.state_dump_msg = 100;
+	}
+}
+
+static void priority_bands_init(struct ivpu_device *vdev)
+{
+	/* Idle */
+	vdev->hw->hws.grace_period[VPU_JOB_SCHEDULING_PRIORITY_BAND_IDLE] = 0;
+	vdev->hw->hws.process_grace_period[VPU_JOB_SCHEDULING_PRIORITY_BAND_IDLE] = 50000;
+	vdev->hw->hws.process_quantum[VPU_JOB_SCHEDULING_PRIORITY_BAND_IDLE] = 160000;
+	/* Normal */
+	vdev->hw->hws.grace_period[VPU_JOB_SCHEDULING_PRIORITY_BAND_NORMAL] = 50000;
+	vdev->hw->hws.process_grace_period[VPU_JOB_SCHEDULING_PRIORITY_BAND_NORMAL] = 50000;
+	vdev->hw->hws.process_quantum[VPU_JOB_SCHEDULING_PRIORITY_BAND_NORMAL] = 300000;
+	/* Focus */
+	vdev->hw->hws.grace_period[VPU_JOB_SCHEDULING_PRIORITY_BAND_FOCUS] = 50000;
+	vdev->hw->hws.process_grace_period[VPU_JOB_SCHEDULING_PRIORITY_BAND_FOCUS] = 50000;
+	vdev->hw->hws.process_quantum[VPU_JOB_SCHEDULING_PRIORITY_BAND_FOCUS] = 200000;
+	/* Realtime */
+	vdev->hw->hws.grace_period[VPU_JOB_SCHEDULING_PRIORITY_BAND_REALTIME] = 0;
+	vdev->hw->hws.process_grace_period[VPU_JOB_SCHEDULING_PRIORITY_BAND_REALTIME] = 50000;
+	vdev->hw->hws.process_quantum[VPU_JOB_SCHEDULING_PRIORITY_BAND_REALTIME] = 200000;
+}
+
+int ivpu_hw_range_init(struct ivpu_device *vdev, struct ivpu_addr_range *range, u64 start, u64 size)
+{
+	u64 end;
+
+	if (!range || check_add_overflow(start, size, &end)) {
+		ivpu_err(vdev, "Invalid range: start 0x%llx size %llu\n", start, size);
+		return -EINVAL;
+	}
+
+	range->start = start;
+	range->end = end;
+
+	return 0;
+}
+
+static void memory_ranges_init(struct ivpu_device *vdev)
+{
+	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) {
+		ivpu_hw_range_init(vdev, &vdev->hw->ranges.runtime, 0x84800000, SZ_64M);
+		ivpu_hw_range_init(vdev, &vdev->hw->ranges.global,  0x90000000, SZ_256M);
+		ivpu_hw_range_init(vdev, &vdev->hw->ranges.user,    0xa0000000, 511 * SZ_1M);
+		ivpu_hw_range_init(vdev, &vdev->hw->ranges.shave,  0x180000000, SZ_2G);
+		ivpu_hw_range_init(vdev, &vdev->hw->ranges.dma,    0x200000000, SZ_128G);
+	} else {
+		ivpu_hw_range_init(vdev, &vdev->hw->ranges.runtime, 0x80000000, SZ_64M);
+		ivpu_hw_range_init(vdev, &vdev->hw->ranges.global,  0x90000000, SZ_256M);
+		ivpu_hw_range_init(vdev, &vdev->hw->ranges.shave,   0x80000000, SZ_2G);
+		ivpu_hw_range_init(vdev, &vdev->hw->ranges.user,   0x100000000, SZ_256G);
+		vdev->hw->ranges.dma = vdev->hw->ranges.user;
+	}
+
+	drm_WARN_ON(&vdev->drm, !IS_ALIGNED(vdev->hw->ranges.global.start,
+					    FW_SHARED_MEM_ALIGNMENT));
+}
+
+static int wp_enable(struct ivpu_device *vdev)
+{
+	return ivpu_hw_btrs_wp_drive(vdev, true);
+}
+
+static int wp_disable(struct ivpu_device *vdev)
+{
+	return ivpu_hw_btrs_wp_drive(vdev, false);
+}
+
+int ivpu_hw_power_up(struct ivpu_device *vdev)
+{
+	int ret;
+
+	if (IVPU_WA(wp0_during_power_up)) {
+		/* WP requests may fail when powering down, so issue WP 0 here */
+		ret = wp_disable(vdev);
+		if (ret)
+			ivpu_warn(vdev, "Failed to disable workpoint: %d\n", ret);
+	}
+
+	ret = ivpu_hw_btrs_d0i3_disable(vdev);
+	if (ret)
+		ivpu_warn(vdev, "Failed to disable D0I3: %d\n", ret);
+
+	ret = wp_enable(vdev);
+	if (ret) {
+		ivpu_err(vdev, "Failed to enable workpoint: %d\n", ret);
+		return ret;
+	}
+
+	if (ivpu_hw_btrs_gen(vdev) >= IVPU_HW_BTRS_LNL) {
+		if (IVPU_WA(disable_clock_relinquish))
+			ivpu_hw_btrs_clock_relinquish_disable_lnl(vdev);
+		ivpu_hw_btrs_profiling_freq_reg_set_lnl(vdev);
+		ivpu_hw_btrs_ats_print_lnl(vdev);
+	}
+
+	ret = ivpu_hw_ip_host_ss_configure(vdev);
+	if (ret) {
+		ivpu_err(vdev, "Failed to configure host SS: %d\n", ret);
+		return ret;
+	}
+
+	ivpu_hw_ip_idle_gen_disable(vdev);
+
+	ret = ivpu_hw_btrs_wait_for_clock_res_own_ack(vdev);
+	if (ret) {
+		ivpu_err(vdev, "Timed out waiting for clock resource own ACK\n");
+		return ret;
+	}
+
+	ret = ivpu_hw_ip_pwr_domain_enable(vdev);
+	if (ret) {
+		ivpu_err(vdev, "Failed to enable power domain: %d\n", ret);
+		return ret;
+	}
+
+	ret = ivpu_hw_ip_host_ss_axi_enable(vdev);
+	if (ret) {
+		ivpu_err(vdev, "Failed to enable AXI: %d\n", ret);
+		return ret;
+	}
+
+	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_LNL)
+		ivpu_hw_btrs_set_port_arbitration_weights_lnl(vdev);
+
+	ret = ivpu_hw_ip_top_noc_enable(vdev);
+	if (ret)
+		ivpu_err(vdev, "Failed to enable TOP NOC: %d\n", ret);
+
+	return ret;
+}
+
+static void save_d0i3_entry_timestamp(struct ivpu_device *vdev)
+{
+	vdev->hw->d0i3_entry_host_ts = ktime_get_boottime();
+	vdev->hw->d0i3_entry_vpu_ts = ivpu_hw_ip_read_perf_timer_counter(vdev);
+}
+
+int ivpu_hw_reset(struct ivpu_device *vdev)
+{
+	int ret = 0;
+
+	if (ivpu_hw_btrs_ip_reset(vdev)) {
+		ivpu_err(vdev, "Failed to reset NPU IP\n");
+		ret = -EIO;
+	}
+
+	if (wp_disable(vdev)) {
+		ivpu_err(vdev, "Failed to disable workpoint\n");
+		ret = -EIO;
+	}
+
+	return ret;
+}
+
+int ivpu_hw_power_down(struct ivpu_device *vdev)
+{
+	int ret = 0;
+
+	save_d0i3_entry_timestamp(vdev);
+
+	if (!ivpu_hw_is_idle(vdev))
+		ivpu_warn(vdev, "NPU not idle during power down\n");
+
+	if (ivpu_hw_reset(vdev)) {
+		ivpu_err(vdev, "Failed to reset NPU\n");
+		ret = -EIO;
+	}
+
+	if (ivpu_hw_btrs_d0i3_enable(vdev)) {
+		ivpu_err(vdev, "Failed to enter D0I3\n");
+		ret = -EIO;
+	}
+
+	return ret;
+}
+
+int ivpu_hw_init(struct ivpu_device *vdev)
+{
+	ivpu_hw_btrs_info_init(vdev);
+	ivpu_hw_btrs_freq_ratios_init(vdev);
+	priority_bands_init(vdev);
+	memory_ranges_init(vdev);
+	platform_init(vdev);
+	wa_init(vdev);
+	timeouts_init(vdev);
+	atomic_set(&vdev->hw->firewall_irq_counter, 0);
+
+#ifdef CONFIG_FAULT_INJECTION
+	if (ivpu_fail_hw)
+		setup_fault_attr(&ivpu_hw_failure, ivpu_fail_hw);
+#endif
+
+	return 0;
+}
+
+int ivpu_hw_boot_fw(struct ivpu_device *vdev)
+{
+	int ret;
+
+	ivpu_hw_ip_snoop_disable(vdev);
+	ivpu_hw_ip_tbu_mmu_enable(vdev);
+	ret = ivpu_hw_ip_soc_cpu_boot(vdev);
+	if (ret)
+		ivpu_err(vdev, "Failed to boot SOC CPU: %d\n", ret);
+
+	return ret;
+}
+
+void ivpu_hw_profiling_freq_drive(struct ivpu_device *vdev, bool enable)
+{
+	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) {
+		vdev->hw->pll.profiling_freq = PLL_PROFILING_FREQ_DEFAULT;
+		return;
+	}
+
+	if (enable)
+		vdev->hw->pll.profiling_freq = PLL_PROFILING_FREQ_HIGH;
+	else
+		vdev->hw->pll.profiling_freq = PLL_PROFILING_FREQ_DEFAULT;
+}
+
+void ivpu_irq_handlers_init(struct ivpu_device *vdev)
+{
+	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
+		vdev->hw->irq.ip_irq_handler = ivpu_hw_ip_irq_handler_37xx;
+	else
+		vdev->hw->irq.ip_irq_handler = ivpu_hw_ip_irq_handler_40xx;
+
+	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
+		vdev->hw->irq.btrs_irq_handler = ivpu_hw_btrs_irq_handler_mtl;
+	else
+		vdev->hw->irq.btrs_irq_handler = ivpu_hw_btrs_irq_handler_lnl;
+}
+
+void ivpu_hw_irq_enable(struct ivpu_device *vdev)
+{
+	ivpu_hw_ip_irq_enable(vdev);
+	ivpu_hw_btrs_irq_enable(vdev);
+}
+
+void ivpu_hw_irq_disable(struct ivpu_device *vdev)
+{
+	ivpu_hw_btrs_irq_disable(vdev);
+	ivpu_hw_ip_irq_disable(vdev);
+}
+
+irqreturn_t ivpu_hw_irq_handler(int irq, void *ptr)
+{
+	struct ivpu_device *vdev = ptr;
+	bool ip_handled, btrs_handled;
+
+	ivpu_hw_btrs_global_int_disable(vdev);
+
+	btrs_handled = ivpu_hw_btrs_irq_handler(vdev, irq);
+	if (!ivpu_hw_is_idle((vdev)) || !btrs_handled)
+		ip_handled = ivpu_hw_ip_irq_handler(vdev, irq);
+	else
+		ip_handled = false;
+
+	/* Re-enable global interrupts to re-trigger MSI for pending interrupts */
+	ivpu_hw_btrs_global_int_enable(vdev);
+
+	if (!ip_handled && !btrs_handled)
+		return IRQ_NONE;
+
+	pm_runtime_mark_last_busy(vdev->drm.dev);
+	return IRQ_HANDLED;
+}
+
+bool ivpu_hw_uses_ecc_mca_signal(struct ivpu_device *vdev)
+{
+	unsigned long long msr_integrity_caps;
+	int ret;
+
+	if (ivpu_hw_ip_gen(vdev) < IVPU_HW_IP_50XX)
+		return false;
+
+	ret = rdmsrq_safe(MSR_INTEGRITY_CAPS, &msr_integrity_caps);
+	if (ret) {
+		ivpu_warn(vdev, "Error reading MSR_INTEGRITY_CAPS: %d", ret);
+		return false;
+	}
+
+	ivpu_dbg(vdev, MISC, "MSR_INTEGRITY_CAPS: 0x%llx\n", msr_integrity_caps);
+
+	return msr_integrity_caps & ECC_MCA_SIGNAL_ENABLE_MASK;
+}
diff --git a/drivers/accel/ivpu/ivpu_hw.h b/drivers/accel/ivpu/ivpu_hw.h
new file mode 100644
index 000000000000..b6d0f0d0dccc
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_hw.h
@@ -0,0 +1,154 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2020-2025 Intel Corporation
+ */
+
+#ifndef __IVPU_HW_H__
+#define __IVPU_HW_H__
+
+#include "ivpu_drv.h"
+#include "ivpu_hw_btrs.h"
+#include "ivpu_hw_ip.h"
+
+struct ivpu_addr_range {
+	resource_size_t start;
+	resource_size_t end;
+};
+
+struct ivpu_hw_info {
+	struct {
+		bool (*btrs_irq_handler)(struct ivpu_device *vdev, int irq);
+		bool (*ip_irq_handler)(struct ivpu_device *vdev, int irq);
+	} irq;
+	struct {
+		struct ivpu_addr_range runtime;
+		struct ivpu_addr_range global;
+		struct ivpu_addr_range user;
+		struct ivpu_addr_range shave;
+		struct ivpu_addr_range dma;
+	} ranges;
+	struct {
+		u8 min_ratio;
+		u8 max_ratio;
+		/*
+		 * Pll ratio for the efficiency frequency. The VPU has optimum
+		 * performance to power ratio at this frequency.
+		 */
+		u8 pn_ratio;
+		u32 profiling_freq;
+	} pll;
+	struct {
+		u32 grace_period[VPU_HWS_NUM_PRIORITY_BANDS];
+		u32 process_quantum[VPU_HWS_NUM_PRIORITY_BANDS];
+		u32 process_grace_period[VPU_HWS_NUM_PRIORITY_BANDS];
+	} hws;
+	u32 tile_fuse;
+	u32 sku;
+	u16 config;
+	int dma_bits;
+	ktime_t d0i3_entry_host_ts;
+	u64 d0i3_entry_vpu_ts;
+	atomic_t firewall_irq_counter;
+};
+
+int ivpu_hw_init(struct ivpu_device *vdev);
+int ivpu_hw_range_init(struct ivpu_device *vdev, struct ivpu_addr_range *range, u64 start,
+		       u64 size);
+int ivpu_hw_power_up(struct ivpu_device *vdev);
+int ivpu_hw_power_down(struct ivpu_device *vdev);
+int ivpu_hw_reset(struct ivpu_device *vdev);
+int ivpu_hw_boot_fw(struct ivpu_device *vdev);
+void ivpu_hw_profiling_freq_drive(struct ivpu_device *vdev, bool enable);
+void ivpu_irq_handlers_init(struct ivpu_device *vdev);
+void ivpu_hw_irq_enable(struct ivpu_device *vdev);
+void ivpu_hw_irq_disable(struct ivpu_device *vdev);
+irqreturn_t ivpu_hw_irq_handler(int irq, void *ptr);
+bool ivpu_hw_uses_ecc_mca_signal(struct ivpu_device *vdev);
+
+static inline u32 ivpu_hw_btrs_irq_handler(struct ivpu_device *vdev, int irq)
+{
+	return vdev->hw->irq.btrs_irq_handler(vdev, irq);
+}
+
+static inline u32 ivpu_hw_ip_irq_handler(struct ivpu_device *vdev, int irq)
+{
+	return vdev->hw->irq.ip_irq_handler(vdev, irq);
+}
+
+static inline u64 ivpu_hw_range_size(const struct ivpu_addr_range *range)
+{
+	return range->end - range->start;
+}
+
+static inline u32 ivpu_hw_dpu_max_freq_get(struct ivpu_device *vdev)
+{
+	return ivpu_hw_btrs_dpu_max_freq_get(vdev);
+}
+
+static inline u32 ivpu_hw_dpu_freq_get(struct ivpu_device *vdev)
+{
+	return ivpu_hw_btrs_dpu_freq_get(vdev);
+}
+
+static inline void ivpu_hw_irq_clear(struct ivpu_device *vdev)
+{
+	ivpu_hw_ip_irq_clear(vdev);
+}
+
+static inline u32 ivpu_hw_profiling_freq_get(struct ivpu_device *vdev)
+{
+	return vdev->hw->pll.profiling_freq;
+}
+
+static inline void ivpu_hw_diagnose_failure(struct ivpu_device *vdev)
+{
+	ivpu_hw_ip_diagnose_failure(vdev);
+	ivpu_hw_btrs_diagnose_failure(vdev);
+}
+
+static inline u32 ivpu_hw_telemetry_offset_get(struct ivpu_device *vdev)
+{
+	return ivpu_hw_btrs_telemetry_offset_get(vdev);
+}
+
+static inline u32 ivpu_hw_telemetry_size_get(struct ivpu_device *vdev)
+{
+	return ivpu_hw_btrs_telemetry_size_get(vdev);
+}
+
+static inline u32 ivpu_hw_telemetry_enable_get(struct ivpu_device *vdev)
+{
+	return ivpu_hw_btrs_telemetry_enable_get(vdev);
+}
+
+static inline bool ivpu_hw_is_idle(struct ivpu_device *vdev)
+{
+	return ivpu_hw_btrs_is_idle(vdev);
+}
+
+static inline int ivpu_hw_wait_for_idle(struct ivpu_device *vdev)
+{
+	return ivpu_hw_btrs_wait_for_idle(vdev);
+}
+
+static inline void ivpu_hw_ipc_tx_set(struct ivpu_device *vdev, u32 vpu_addr)
+{
+	ivpu_hw_ip_ipc_tx_set(vdev, vpu_addr);
+}
+
+static inline void ivpu_hw_db_set(struct ivpu_device *vdev, u32 db_id)
+{
+	ivpu_hw_ip_db_set(vdev, db_id);
+}
+
+static inline u32 ivpu_hw_ipc_rx_addr_get(struct ivpu_device *vdev)
+{
+	return ivpu_hw_ip_ipc_rx_addr_get(vdev);
+}
+
+static inline u32 ivpu_hw_ipc_rx_count_get(struct ivpu_device *vdev)
+{
+	return ivpu_hw_ip_ipc_rx_count_get(vdev);
+}
+
+#endif /* __IVPU_HW_H__ */
diff --git a/drivers/accel/ivpu/ivpu_hw_37xx_reg.h b/drivers/accel/ivpu/ivpu_hw_37xx_reg.h
new file mode 100644
index 000000000000..cf5e2f01049c
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_hw_37xx_reg.h
@@ -0,0 +1,178 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2020-2023 Intel Corporation
+ */
+
+#ifndef __IVPU_HW_37XX_REG_H__
+#define __IVPU_HW_37XX_REG_H__
+
+#include <linux/bits.h>
+
+#define VPU_37XX_HOST_SS_CPR_CLK_SET					0x00000084u
+#define VPU_37XX_HOST_SS_CPR_CLK_SET_TOP_NOC_MASK			BIT_MASK(1)
+#define VPU_37XX_HOST_SS_CPR_CLK_SET_DSS_MAS_MASK			BIT_MASK(10)
+#define VPU_37XX_HOST_SS_CPR_CLK_SET_MSS_MAS_MASK			BIT_MASK(11)
+
+#define VPU_37XX_HOST_SS_CPR_RST_SET					0x00000094u
+#define VPU_37XX_HOST_SS_CPR_RST_SET_TOP_NOC_MASK			BIT_MASK(1)
+#define VPU_37XX_HOST_SS_CPR_RST_SET_DSS_MAS_MASK			BIT_MASK(10)
+#define VPU_37XX_HOST_SS_CPR_RST_SET_MSS_MAS_MASK			BIT_MASK(11)
+
+#define VPU_37XX_HOST_SS_CPR_RST_CLR					0x00000098u
+#define VPU_37XX_HOST_SS_CPR_RST_CLR_AON_MASK				BIT_MASK(0)
+#define VPU_37XX_HOST_SS_CPR_RST_CLR_TOP_NOC_MASK			BIT_MASK(1)
+#define VPU_37XX_HOST_SS_CPR_RST_CLR_DSS_MAS_MASK			BIT_MASK(10)
+#define VPU_37XX_HOST_SS_CPR_RST_CLR_MSS_MAS_MASK			BIT_MASK(11)
+
+#define VPU_37XX_HOST_SS_HW_VERSION					0x00000108u
+#define VPU_37XX_HOST_SS_HW_VERSION_SOC_REVISION_MASK			GENMASK(7, 0)
+#define VPU_37XX_HOST_SS_HW_VERSION_SOC_NUMBER_MASK			GENMASK(15, 8)
+#define VPU_37XX_HOST_SS_HW_VERSION_VPU_GENERATION_MASK			GENMASK(23, 16)
+
+#define VPU_37XX_HOST_SS_GEN_CTRL					0x00000118u
+#define VPU_37XX_HOST_SS_GEN_CTRL_PS_MASK				GENMASK(31, 29)
+
+#define VPU_37XX_HOST_SS_NOC_QREQN					0x00000154u
+#define VPU_37XX_HOST_SS_NOC_QREQN_TOP_SOCMMIO_MASK			BIT_MASK(0)
+
+#define VPU_37XX_HOST_SS_NOC_QACCEPTN					0x00000158u
+#define VPU_37XX_HOST_SS_NOC_QACCEPTN_TOP_SOCMMIO_MASK			BIT_MASK(0)
+
+#define VPU_37XX_HOST_SS_NOC_QDENY					0x0000015cu
+#define VPU_37XX_HOST_SS_NOC_QDENY_TOP_SOCMMIO_MASK			BIT_MASK(0)
+
+#define VPU_37XX_TOP_NOC_QREQN						0x00000160u
+#define VPU_37XX_TOP_NOC_QREQN_CPU_CTRL_MASK				BIT_MASK(0)
+#define VPU_37XX_TOP_NOC_QREQN_HOSTIF_L2CACHE_MASK			BIT_MASK(1)
+
+#define VPU_37XX_TOP_NOC_QACCEPTN					0x00000164u
+#define VPU_37XX_TOP_NOC_QACCEPTN_CPU_CTRL_MASK				BIT_MASK(0)
+#define VPU_37XX_TOP_NOC_QACCEPTN_HOSTIF_L2CACHE_MASK			BIT_MASK(1)
+
+#define VPU_37XX_TOP_NOC_QDENY						0x00000168u
+#define VPU_37XX_TOP_NOC_QDENY_CPU_CTRL_MASK				BIT_MASK(0)
+#define VPU_37XX_TOP_NOC_QDENY_HOSTIF_L2CACHE_MASK			BIT_MASK(1)
+
+#define VPU_37XX_HOST_SS_FW_SOC_IRQ_EN					0x00000170u
+#define VPU_37XX_HOST_SS_FW_SOC_IRQ_EN_CSS_ROM_CMX_MASK			BIT_MASK(0)
+#define VPU_37XX_HOST_SS_FW_SOC_IRQ_EN_CSS_DBG_MASK			BIT_MASK(1)
+#define VPU_37XX_HOST_SS_FW_SOC_IRQ_EN_CSS_CTRL_MASK			BIT_MASK(2)
+#define VPU_37XX_HOST_SS_FW_SOC_IRQ_EN_DEC400_MASK			BIT_MASK(3)
+#define VPU_37XX_HOST_SS_FW_SOC_IRQ_EN_MSS_NCE_MASK			BIT_MASK(4)
+#define VPU_37XX_HOST_SS_FW_SOC_IRQ_EN_MSS_MBI_MASK			BIT_MASK(5)
+#define VPU_37XX_HOST_SS_FW_SOC_IRQ_EN_MSS_MBI_CMX_MASK			BIT_MASK(6)
+
+#define VPU_37XX_HOST_SS_ICB_STATUS_0					0x00010210u
+#define VPU_37XX_HOST_SS_ICB_STATUS_0_TIMER_0_INT_MASK			BIT_MASK(0)
+#define VPU_37XX_HOST_SS_ICB_STATUS_0_TIMER_1_INT_MASK			BIT_MASK(1)
+#define VPU_37XX_HOST_SS_ICB_STATUS_0_TIMER_2_INT_MASK			BIT_MASK(2)
+#define VPU_37XX_HOST_SS_ICB_STATUS_0_TIMER_3_INT_MASK			BIT_MASK(3)
+#define VPU_37XX_HOST_SS_ICB_STATUS_0_HOST_IPC_FIFO_INT_MASK		BIT_MASK(4)
+#define VPU_37XX_HOST_SS_ICB_STATUS_0_MMU_IRQ_0_INT_MASK		BIT_MASK(5)
+#define VPU_37XX_HOST_SS_ICB_STATUS_0_MMU_IRQ_1_INT_MASK		BIT_MASK(6)
+#define VPU_37XX_HOST_SS_ICB_STATUS_0_MMU_IRQ_2_INT_MASK		BIT_MASK(7)
+#define VPU_37XX_HOST_SS_ICB_STATUS_0_NOC_FIREWALL_INT_MASK		BIT_MASK(8)
+#define VPU_37XX_HOST_SS_ICB_STATUS_0_CPU_INT_REDIRECT_0_INT_MASK	BIT_MASK(30)
+#define VPU_37XX_HOST_SS_ICB_STATUS_0_CPU_INT_REDIRECT_1_INT_MASK	BIT_MASK(31)
+
+#define VPU_37XX_HOST_SS_ICB_STATUS_1					0x00010214u
+#define VPU_37XX_HOST_SS_ICB_STATUS_1_CPU_INT_REDIRECT_2_INT_MASK	BIT_MASK(0)
+#define VPU_37XX_HOST_SS_ICB_STATUS_1_CPU_INT_REDIRECT_3_INT_MASK	BIT_MASK(1)
+#define VPU_37XX_HOST_SS_ICB_STATUS_1_CPU_INT_REDIRECT_4_INT_MASK	BIT_MASK(2)
+
+#define VPU_37XX_HOST_SS_ICB_CLEAR_0					0x00010220u
+#define VPU_37XX_HOST_SS_ICB_CLEAR_1					0x00010224u
+#define VPU_37XX_HOST_SS_ICB_ENABLE_0					0x00010240u
+
+#define VPU_37XX_HOST_SS_TIM_IPC_FIFO_ATM				0x000200f4u
+
+#define VPU_37XX_HOST_SS_TIM_IPC_FIFO_STAT				0x000200fcu
+#define VPU_37XX_HOST_SS_TIM_IPC_FIFO_STAT_READ_POINTER_MASK		GENMASK(7, 0)
+#define VPU_37XX_HOST_SS_TIM_IPC_FIFO_STAT_WRITE_POINTER_MASK		GENMASK(15, 8)
+#define VPU_37XX_HOST_SS_TIM_IPC_FIFO_STAT_FILL_LEVEL_MASK		GENMASK(23, 16)
+#define VPU_37XX_HOST_SS_TIM_IPC_FIFO_STAT_RSVD0_MASK			GENMASK(31, 24)
+
+#define VPU_37XX_HOST_SS_AON_PWR_ISO_EN0				0x00030020u
+#define VPU_37XX_HOST_SS_AON_PWR_ISO_EN0_MSS_CPU_MASK			BIT_MASK(3)
+
+#define VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0				0x00030024u
+#define VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0_MSS_CPU_MASK		BIT_MASK(3)
+
+#define VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0			0x00030028u
+#define VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0_MSS_CPU_MASK	BIT_MASK(3)
+
+#define VPU_37XX_HOST_SS_AON_PWR_ISLAND_STATUS0				0x0003002cu
+#define VPU_37XX_HOST_SS_AON_PWR_ISLAND_STATUS0_MSS_CPU_MASK		BIT_MASK(3)
+
+#define VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN				0x00030200u
+#define VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN_EN_MASK			BIT_MASK(0)
+
+#define VPU_37XX_HOST_SS_AON_DPU_ACTIVE					0x00030204u
+#define VPU_37XX_HOST_SS_AON_DPU_ACTIVE_DPU_ACTIVE_MASK			BIT_MASK(0)
+
+#define VPU_37XX_HOST_SS_LOADING_ADDRESS_LO				0x00041040u
+#define VPU_37XX_HOST_SS_LOADING_ADDRESS_LO_DONE_MASK			BIT_MASK(0)
+#define VPU_37XX_HOST_SS_LOADING_ADDRESS_LO_IOSF_RS_ID_MASK		GENMASK(2, 1)
+#define VPU_37XX_HOST_SS_LOADING_ADDRESS_LO_IMAGE_LOCATION_MASK		GENMASK(31, 3)
+
+#define VPU_37XX_HOST_SS_WORKPOINT_CONFIG_MIRROR			0x00082020u
+#define VPU_37XX_HOST_SS_WORKPOINT_CONFIG_MIRROR_FINAL_PLL_FREQ_MASK	GENMASK(15, 0)
+#define VPU_37XX_HOST_SS_WORKPOINT_CONFIG_MIRROR_CONFIG_ID_MASK		GENMASK(31, 16)
+
+#define VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES				0x00360000u
+#define VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES_CACHE_OVERRIDE_EN_MASK	BIT_MASK(0)
+#define VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES_AWCACHE_OVERRIDE_MASK	BIT_MASK(1)
+#define VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES_ARCACHE_OVERRIDE_MASK	BIT_MASK(2)
+#define VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES_NOSNOOP_OVERRIDE_EN_MASK	BIT_MASK(3)
+#define VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES_AW_NOSNOOP_OVERRIDE_MASK	BIT_MASK(4)
+#define VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES_AR_NOSNOOP_OVERRIDE_MASK	BIT_MASK(5)
+#define VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES_PTW_AW_CONTEXT_FLAG_MASK	GENMASK(10, 6)
+#define VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES_PTW_AR_CONTEXT_FLAG_MASK	GENMASK(15, 11)
+
+#define VPU_37XX_HOST_IF_TBU_MMUSSIDV					0x00360004u
+#define VPU_37XX_HOST_IF_TBU_MMUSSIDV_TBU0_AWMMUSSIDV_MASK		BIT_MASK(0)
+#define VPU_37XX_HOST_IF_TBU_MMUSSIDV_TBU0_ARMMUSSIDV_MASK		BIT_MASK(1)
+#define VPU_37XX_HOST_IF_TBU_MMUSSIDV_TBU1_AWMMUSSIDV_MASK		BIT_MASK(2)
+#define VPU_37XX_HOST_IF_TBU_MMUSSIDV_TBU1_ARMMUSSIDV_MASK		BIT_MASK(3)
+#define VPU_37XX_HOST_IF_TBU_MMUSSIDV_TBU2_AWMMUSSIDV_MASK		BIT_MASK(4)
+#define VPU_37XX_HOST_IF_TBU_MMUSSIDV_TBU2_ARMMUSSIDV_MASK		BIT_MASK(5)
+#define VPU_37XX_HOST_IF_TBU_MMUSSIDV_TBU3_AWMMUSSIDV_MASK		BIT_MASK(6)
+#define VPU_37XX_HOST_IF_TBU_MMUSSIDV_TBU3_ARMMUSSIDV_MASK		BIT_MASK(7)
+#define VPU_37XX_HOST_IF_TBU_MMUSSIDV_TBU4_AWMMUSSIDV_MASK		BIT_MASK(8)
+#define VPU_37XX_HOST_IF_TBU_MMUSSIDV_TBU4_ARMMUSSIDV_MASK		BIT_MASK(9)
+
+#define VPU_37XX_CPU_SS_DSU_LEON_RT_BASE				0x04000000u
+#define VPU_37XX_CPU_SS_DSU_LEON_RT_DSU_CTRL				0x04000000u
+#define VPU_37XX_CPU_SS_DSU_LEON_RT_PC_REG				0x04400010u
+#define VPU_37XX_CPU_SS_DSU_LEON_RT_NPC_REG				0x04400014u
+#define VPU_37XX_CPU_SS_DSU_LEON_RT_DSU_TRAP_REG			0x04400020u
+
+#define VPU_37XX_CPU_SS_MSSCPU_CPR_CLK_SET				0x06010004u
+#define VPU_37XX_CPU_SS_MSSCPU_CPR_CLK_SET_CPU_DSU_MASK			BIT_MASK(1)
+
+#define VPU_37XX_CPU_SS_MSSCPU_CPR_RST_CLR				0x06010018u
+#define VPU_37XX_CPU_SS_MSSCPU_CPR_RST_CLR_CPU_DSU_MASK			BIT_MASK(1)
+
+#define VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC				0x06010040u
+#define VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC_IRQI_RSTRUN0_MASK	BIT_MASK(0)
+#define VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC_IRQI_RESUME0_MASK	BIT_MASK(1)
+#define VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC_IRQI_RSTRUN1_MASK	BIT_MASK(2)
+#define VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC_IRQI_RESUME1_MASK	BIT_MASK(3)
+#define VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC_IRQI_RSTVEC_MASK		GENMASK(31, 4)
+
+#define VPU_37XX_CPU_SS_TIM_WATCHDOG					0x0602009cu
+#define VPU_37XX_CPU_SS_TIM_WDOG_EN					0x060200a4u
+#define VPU_37XX_CPU_SS_TIM_SAFE					0x060200a8u
+#define VPU_37XX_CPU_SS_TIM_IPC_FIFO					0x060200f0u
+
+#define VPU_37XX_CPU_SS_TIM_GEN_CONFIG					0x06021008u
+#define VPU_37XX_CPU_SS_TIM_GEN_CONFIG_WDOG_TO_INT_CLR_MASK		BIT_MASK(9)
+
+#define VPU_37XX_CPU_SS_TIM_PERF_FREE_CNT				0x06029000u
+
+#define VPU_37XX_CPU_SS_DOORBELL_0					0x06300000u
+#define VPU_37XX_CPU_SS_DOORBELL_0_SET_MASK				BIT_MASK(0)
+
+#define VPU_37XX_CPU_SS_DOORBELL_1					0x06301000u
+
+#endif /* __IVPU_HW_37XX_REG_H__ */
diff --git a/drivers/accel/ivpu/ivpu_hw_40xx_reg.h b/drivers/accel/ivpu/ivpu_hw_40xx_reg.h
new file mode 100644
index 000000000000..fc0ee8d637f9
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_hw_40xx_reg.h
@@ -0,0 +1,195 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2020-2023 Intel Corporation
+ */
+
+#ifndef __IVPU_HW_40XX_REG_H__
+#define __IVPU_HW_40XX_REG_H__
+
+#include <linux/bits.h>
+
+#define VPU_40XX_HOST_SS_CPR_CLK_EN					0x00000080u
+#define VPU_40XX_HOST_SS_CPR_CLK_EN_TOP_NOC_MASK			BIT_MASK(1)
+#define VPU_40XX_HOST_SS_CPR_CLK_EN_DSS_MAS_MASK			BIT_MASK(10)
+#define VPU_40XX_HOST_SS_CPR_CLK_EN_CSS_MAS_MASK			BIT_MASK(11)
+
+#define VPU_40XX_HOST_SS_CPR_CLK_SET					0x00000084u
+#define VPU_40XX_HOST_SS_CPR_CLK_SET_TOP_NOC_MASK			BIT_MASK(1)
+#define VPU_40XX_HOST_SS_CPR_CLK_SET_DSS_MAS_MASK			BIT_MASK(10)
+#define VPU_40XX_HOST_SS_CPR_CLK_SET_MSS_MAS_MASK			BIT_MASK(11)
+
+#define VPU_40XX_HOST_SS_CPR_RST_EN					0x00000090u
+#define VPU_40XX_HOST_SS_CPR_RST_EN_TOP_NOC_MASK			BIT_MASK(1)
+#define VPU_40XX_HOST_SS_CPR_RST_EN_DSS_MAS_MASK			BIT_MASK(10)
+#define VPU_40XX_HOST_SS_CPR_RST_EN_CSS_MAS_MASK			BIT_MASK(11)
+
+#define VPU_40XX_HOST_SS_CPR_RST_SET					0x00000094u
+#define VPU_40XX_HOST_SS_CPR_RST_SET_TOP_NOC_MASK			BIT_MASK(1)
+#define VPU_40XX_HOST_SS_CPR_RST_SET_DSS_MAS_MASK			BIT_MASK(10)
+#define VPU_40XX_HOST_SS_CPR_RST_SET_MSS_MAS_MASK			BIT_MASK(11)
+
+#define VPU_40XX_HOST_SS_CPR_RST_CLR					0x00000098u
+#define VPU_40XX_HOST_SS_CPR_RST_CLR_TOP_NOC_MASK			BIT_MASK(1)
+#define VPU_40XX_HOST_SS_CPR_RST_CLR_DSS_MAS_MASK			BIT_MASK(10)
+#define VPU_40XX_HOST_SS_CPR_RST_CLR_MSS_MAS_MASK			BIT_MASK(11)
+
+#define VPU_40XX_HOST_SS_HW_VERSION					0x00000108u
+#define VPU_40XX_HOST_SS_HW_VERSION_SOC_REVISION_MASK			GENMASK(7, 0)
+#define VPU_40XX_HOST_SS_HW_VERSION_SOC_NUMBER_MASK			GENMASK(15, 8)
+#define VPU_40XX_HOST_SS_HW_VERSION_VPU_GENERATION_MASK			GENMASK(23, 16)
+
+#define VPU_40XX_HOST_SS_SW_VERSION					0x0000010cu
+
+#define VPU_40XX_HOST_SS_GEN_CTRL					0x00000118u
+#define VPU_40XX_HOST_SS_GEN_CTRL_PS_MASK				GENMASK(31, 29)
+
+#define VPU_40XX_HOST_SS_NOC_QREQN					0x00000154u
+#define VPU_40XX_HOST_SS_NOC_QREQN_TOP_SOCMMIO_MASK			BIT_MASK(0)
+
+#define VPU_40XX_HOST_SS_NOC_QACCEPTN					0x00000158u
+#define VPU_40XX_HOST_SS_NOC_QACCEPTN_TOP_SOCMMIO_MASK			BIT_MASK(0)
+
+#define VPU_40XX_HOST_SS_NOC_QDENY					0x0000015cu
+#define VPU_40XX_HOST_SS_NOC_QDENY_TOP_SOCMMIO_MASK			BIT_MASK(0)
+
+#define VPU_40XX_TOP_NOC_QREQN						0x00000160u
+#define VPU_40XX_TOP_NOC_QREQN_CPU_CTRL_MASK				BIT_MASK(0)
+#define VPU_40XX_TOP_NOC_QREQN_HOSTIF_L2CACHE_MASK			BIT_MASK(2)
+
+#define VPU_40XX_TOP_NOC_QACCEPTN					0x00000164u
+#define VPU_40XX_TOP_NOC_QACCEPTN_CPU_CTRL_MASK				BIT_MASK(0)
+#define VPU_40XX_TOP_NOC_QACCEPTN_HOSTIF_L2CACHE_MASK			BIT_MASK(2)
+
+#define VPU_40XX_TOP_NOC_QDENY						0x00000168u
+#define VPU_40XX_TOP_NOC_QDENY_CPU_CTRL_MASK				BIT_MASK(0)
+#define VPU_40XX_TOP_NOC_QDENY_HOSTIF_L2CACHE_MASK			BIT_MASK(2)
+
+#define VPU_40XX_HOST_SS_FW_SOC_IRQ_EN					0x00000170u
+#define VPU_40XX_HOST_SS_FW_SOC_IRQ_EN_CSS_ROM_CMX_MASK			BIT_MASK(0)
+#define VPU_40XX_HOST_SS_FW_SOC_IRQ_EN_CSS_DBG_MASK			BIT_MASK(1)
+#define VPU_40XX_HOST_SS_FW_SOC_IRQ_EN_CSS_CTRL_MASK			BIT_MASK(2)
+#define VPU_40XX_HOST_SS_FW_SOC_IRQ_EN_DEC400_MASK			BIT_MASK(3)
+#define VPU_40XX_HOST_SS_FW_SOC_IRQ_EN_MSS_NCE_MASK			BIT_MASK(4)
+#define VPU_40XX_HOST_SS_FW_SOC_IRQ_EN_MSS_MBI_MASK			BIT_MASK(5)
+#define VPU_40XX_HOST_SS_FW_SOC_IRQ_EN_MSS_MBI_CMX_MASK			BIT_MASK(6)
+
+#define VPU_40XX_HOST_SS_ICB_STATUS_0					0x00010210u
+#define VPU_40XX_HOST_SS_ICB_STATUS_0_TIMER_0_INT_MASK			BIT_MASK(0)
+#define VPU_40XX_HOST_SS_ICB_STATUS_0_TIMER_1_INT_MASK			BIT_MASK(1)
+#define VPU_40XX_HOST_SS_ICB_STATUS_0_TIMER_2_INT_MASK			BIT_MASK(2)
+#define VPU_40XX_HOST_SS_ICB_STATUS_0_TIMER_3_INT_MASK			BIT_MASK(3)
+#define VPU_40XX_HOST_SS_ICB_STATUS_0_HOST_IPC_FIFO_INT_MASK		BIT_MASK(4)
+#define VPU_40XX_HOST_SS_ICB_STATUS_0_MMU_IRQ_0_INT_MASK		BIT_MASK(5)
+#define VPU_40XX_HOST_SS_ICB_STATUS_0_MMU_IRQ_1_INT_MASK		BIT_MASK(6)
+#define VPU_40XX_HOST_SS_ICB_STATUS_0_MMU_IRQ_2_INT_MASK		BIT_MASK(7)
+#define VPU_40XX_HOST_SS_ICB_STATUS_0_NOC_FIREWALL_INT_MASK		BIT_MASK(8)
+#define VPU_40XX_HOST_SS_ICB_STATUS_0_CPU_INT_REDIRECT_0_INT_MASK	BIT_MASK(30)
+#define VPU_40XX_HOST_SS_ICB_STATUS_0_CPU_INT_REDIRECT_1_INT_MASK	BIT_MASK(31)
+
+#define VPU_40XX_HOST_SS_ICB_STATUS_1					0x00010214u
+#define VPU_40XX_HOST_SS_ICB_STATUS_1_CPU_INT_REDIRECT_2_INT_MASK	BIT_MASK(0)
+#define VPU_40XX_HOST_SS_ICB_STATUS_1_CPU_INT_REDIRECT_3_INT_MASK	BIT_MASK(1)
+#define VPU_40XX_HOST_SS_ICB_STATUS_1_CPU_INT_REDIRECT_4_INT_MASK	BIT_MASK(2)
+
+#define VPU_40XX_HOST_SS_ICB_CLEAR_0					0x00010220u
+#define VPU_40XX_HOST_SS_ICB_CLEAR_1					0x00010224u
+#define VPU_40XX_HOST_SS_ICB_ENABLE_0					0x00010240u
+#define VPU_40XX_HOST_SS_ICB_ENABLE_1					0x00010244u
+
+#define VPU_40XX_HOST_SS_TIM_IPC_FIFO_ATM				0x000200f4u
+
+#define VPU_40XX_HOST_SS_TIM_IPC_FIFO_STAT				0x000200fcu
+#define VPU_40XX_HOST_SS_TIM_IPC_FIFO_STAT_FILL_LEVEL_MASK		GENMASK(23, 16)
+
+#define VPU_40XX_HOST_SS_AON_PWR_ISO_EN0				0x00030020u
+#define VPU_40XX_HOST_SS_AON_PWR_ISO_EN0_CSS_CPU_MASK			BIT_MASK(3)
+
+#define VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0				0x00030024u
+#define VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0_CSS_CPU_MASK		BIT_MASK(3)
+
+#define VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0			0x00030028u
+#define VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0_CSS_CPU_MASK	BIT_MASK(3)
+
+#define VPU_40XX_HOST_SS_AON_PWR_ISLAND_STATUS0				0x0003002cu
+#define VPU_40XX_HOST_SS_AON_PWR_ISLAND_STATUS0_CSS_CPU_MASK		BIT_MASK(3)
+
+#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY			0x00030068u
+#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY_POST_DLY_MASK	GENMASK(7, 0)
+#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY_POST1_DLY_MASK	GENMASK(15, 8)
+#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY_POST2_DLY_MASK	GENMASK(23, 16)
+
+#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY			0x0003006cu
+#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY_STATUS_DLY_MASK	GENMASK(7, 0)
+
+#define VPU_40XX_HOST_SS_AON_IDLE_GEN					0x00030200u
+#define VPU_40XX_HOST_SS_AON_IDLE_GEN_EN_MASK				BIT_MASK(0)
+#define VPU_40XX_HOST_SS_AON_IDLE_GEN_HW_PG_EN_MASK			BIT_MASK(1)
+
+#define VPU_40XX_HOST_SS_AON_DPU_ACTIVE					0x00030204u
+#define VPU_40XX_HOST_SS_AON_DPU_ACTIVE_DPU_ACTIVE_MASK			BIT_MASK(0)
+
+#define VPU_50XX_HOST_SS_AON_FABRIC_REQ_OVERRIDE			0x00030210u
+#define VPU_50XX_HOST_SS_AON_FABRIC_REQ_OVERRIDE_REQ_OVERRIDE_MASK      BIT_MASK(0)
+
+#define VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO			0x00040040u
+#define VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO_DONE_MASK		BIT_MASK(0)
+#define VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO_IOSF_RS_ID_MASK	GENMASK(2, 1)
+#define VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO_IMAGE_LOCATION_MASK	GENMASK(31, 3)
+
+#define VPU_40XX_HOST_SS_WORKPOINT_CONFIG_MIRROR			0x00082020u
+#define VPU_40XX_HOST_SS_WORKPOINT_CONFIG_MIRROR_FINAL_PLL_FREQ_MASK	GENMASK(15, 0)
+#define VPU_40XX_HOST_SS_WORKPOINT_CONFIG_MIRROR_CONFIG_ID_MASK		GENMASK(31, 16)
+
+#define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES				0x00360000u
+#define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_CACHE_OVERRIDE_EN_MASK	BIT_MASK(0)
+#define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_AWCACHE_OVERRIDE_MASK	BIT_MASK(1)
+#define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_ARCACHE_OVERRIDE_MASK	BIT_MASK(2)
+#define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_SNOOP_OVERRIDE_EN_MASK	BIT_MASK(3)
+#define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_AW_SNOOP_OVERRIDE_MASK	BIT_MASK(4)
+#define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_AR_SNOOP_OVERRIDE_MASK	BIT_MASK(5)
+#define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_PTW_AW_CONTEXT_FLAG_MASK	GENMASK(10, 6)
+#define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_PTW_AR_CONTEXT_FLAG_MASK	GENMASK(15, 11)
+
+#define VPU_40XX_HOST_IF_TBU_MMUSSIDV					0x00360004u
+#define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU0_AWMMUSSIDV_MASK		BIT_MASK(0)
+#define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU0_ARMMUSSIDV_MASK		BIT_MASK(1)
+#define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU1_AWMMUSSIDV_MASK		BIT_MASK(2)
+#define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU1_ARMMUSSIDV_MASK		BIT_MASK(3)
+#define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU2_AWMMUSSIDV_MASK		BIT_MASK(4)
+#define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU2_ARMMUSSIDV_MASK		BIT_MASK(5)
+#define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU3_AWMMUSSIDV_MASK		BIT_MASK(6)
+#define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU3_ARMMUSSIDV_MASK		BIT_MASK(7)
+#define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU4_AWMMUSSIDV_MASK		BIT_MASK(8)
+#define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU4_ARMMUSSIDV_MASK		BIT_MASK(9)
+
+#define VPU_40XX_CPU_SS_DSU_LEON_RT_BASE				0x04000000u
+#define VPU_40XX_CPU_SS_DSU_LEON_RT_DSU_CTRL				0x04000000u
+#define VPU_40XX_CPU_SS_DSU_LEON_RT_PC_REG				0x04400010u
+#define VPU_40XX_CPU_SS_DSU_LEON_RT_NPC_REG				0x04400014u
+#define VPU_40XX_CPU_SS_DSU_LEON_RT_DSU_TRAP_REG			0x04400020u
+
+#define VPU_40XX_CPU_SS_TIM_WATCHDOG					0x0102009cu
+#define VPU_40XX_CPU_SS_TIM_WDOG_EN					0x010200a4u
+#define VPU_40XX_CPU_SS_TIM_SAFE					0x010200a8u
+
+#define VPU_40XX_CPU_SS_TIM_GEN_CONFIG					0x01021008u
+#define VPU_40XX_CPU_SS_TIM_GEN_CONFIG_WDOG_TO_INT_CLR_MASK		BIT_MASK(9)
+
+#define VPU_40XX_CPU_SS_CPR_NOC_QREQN					0x01010030u
+#define VPU_40XX_CPU_SS_CPR_NOC_QREQN_TOP_MMIO_MASK			BIT_MASK(0)
+
+#define VPU_40XX_CPU_SS_CPR_NOC_QACCEPTN				0x01010034u
+#define VPU_40XX_CPU_SS_CPR_NOC_QACCEPTN_TOP_MMIO_MASK			BIT_MASK(0)
+
+#define VPU_40XX_CPU_SS_CPR_NOC_QDENY					0x01010038u
+#define VPU_40XX_CPU_SS_CPR_NOC_QDENY_TOP_MMIO_MASK			BIT_MASK(0)
+
+#define VPU_40XX_CPU_SS_TIM_IPC_FIFO					0x010200f0u
+#define VPU_40XX_CPU_SS_TIM_PERF_EXT_FREE_CNT				0x01029008u
+
+#define VPU_40XX_CPU_SS_DOORBELL_0					0x01300000u
+#define VPU_40XX_CPU_SS_DOORBELL_0_SET_MASK				BIT_MASK(0)
+
+#define VPU_40XX_CPU_SS_DOORBELL_1					0x01301000u
+
+#endif /* __IVPU_HW_40XX_REG_H__ */
diff --git a/drivers/accel/ivpu/ivpu_hw_btrs.c b/drivers/accel/ivpu/ivpu_hw_btrs.c
new file mode 100644
index 000000000000..06e65c592618
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_hw_btrs.c
@@ -0,0 +1,905 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020-2025 Intel Corporation
+ */
+
+#include <linux/units.h>
+
+#include "ivpu_drv.h"
+#include "ivpu_hw.h"
+#include "ivpu_hw_btrs.h"
+#include "ivpu_hw_btrs_lnl_reg.h"
+#include "ivpu_hw_btrs_mtl_reg.h"
+#include "ivpu_hw_reg_io.h"
+#include "ivpu_pm.h"
+
+#define BTRS_MTL_IRQ_MASK ((REG_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, ATS_ERR)) | \
+			   (REG_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, UFI_ERR)))
+
+#define BTRS_LNL_IRQ_MASK ((REG_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, ATS_ERR)) | \
+			   (REG_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, CFI0_ERR)) | \
+			   (REG_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, CFI1_ERR)) | \
+			   (REG_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, IMR0_ERR)) | \
+			   (REG_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, IMR1_ERR)) | \
+			   (REG_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, SURV_ERR)))
+
+#define BTRS_MTL_ALL_IRQ_MASK (BTRS_MTL_IRQ_MASK | (REG_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, \
+			       FREQ_CHANGE)))
+
+#define BTRS_IRQ_DISABLE_MASK ((u32)-1)
+
+#define BTRS_LNL_ALL_IRQ_MASK ((u32)-1)
+
+
+#define PLL_CDYN_DEFAULT               0x80
+#define PLL_EPP_DEFAULT                0x80
+#define PLL_REF_CLK_FREQ               50000000ull
+#define PLL_RATIO_TO_FREQ(x)           ((x) * PLL_REF_CLK_FREQ)
+
+#define PLL_TIMEOUT_US		       (1500 * USEC_PER_MSEC)
+#define IDLE_TIMEOUT_US		       (5 * USEC_PER_MSEC)
+#define TIMEOUT_US                     (150 * USEC_PER_MSEC)
+
+/* Work point configuration values */
+#define WP_CONFIG(tile, ratio)         (((tile) << 8) | (ratio))
+#define MTL_CONFIG_1_TILE              0x01
+#define MTL_CONFIG_2_TILE              0x02
+#define MTL_PLL_RATIO_5_3              0x01
+#define MTL_PLL_RATIO_4_3              0x02
+#define BTRS_MTL_TILE_FUSE_ENABLE_BOTH 0x0
+#define BTRS_MTL_TILE_SKU_BOTH         0x3630
+
+#define BTRS_LNL_TILE_MAX_NUM          6
+#define BTRS_LNL_TILE_MAX_MASK         0x3f
+
+#define WEIGHTS_DEFAULT                0xf711f711u
+#define WEIGHTS_ATS_DEFAULT            0x0000f711u
+
+#define DCT_REQ                        0x2
+#define DCT_ENABLE                     0x1
+#define DCT_DISABLE                    0x0
+
+static u32 pll_ratio_to_dpu_freq(struct ivpu_device *vdev, u32 ratio);
+
+int ivpu_hw_btrs_irqs_clear_with_0_mtl(struct ivpu_device *vdev)
+{
+	REGB_WR32(VPU_HW_BTRS_MTL_INTERRUPT_STAT, BTRS_MTL_ALL_IRQ_MASK);
+	if (REGB_RD32(VPU_HW_BTRS_MTL_INTERRUPT_STAT) == BTRS_MTL_ALL_IRQ_MASK) {
+		/* Writing 1s does not clear the interrupt status register */
+		REGB_WR32(VPU_HW_BTRS_MTL_INTERRUPT_STAT, 0x0);
+		return true;
+	}
+
+	return false;
+}
+
+static void freq_ratios_init_mtl(struct ivpu_device *vdev)
+{
+	struct ivpu_hw_info *hw = vdev->hw;
+	u32 fmin_fuse, fmax_fuse;
+
+	fmin_fuse = REGB_RD32(VPU_HW_BTRS_MTL_FMIN_FUSE);
+	hw->pll.min_ratio = REG_GET_FLD(VPU_HW_BTRS_MTL_FMIN_FUSE, MIN_RATIO, fmin_fuse);
+	hw->pll.pn_ratio = REG_GET_FLD(VPU_HW_BTRS_MTL_FMIN_FUSE, PN_RATIO, fmin_fuse);
+
+	fmax_fuse = REGB_RD32(VPU_HW_BTRS_MTL_FMAX_FUSE);
+	hw->pll.max_ratio = REG_GET_FLD(VPU_HW_BTRS_MTL_FMAX_FUSE, MAX_RATIO, fmax_fuse);
+}
+
+static void freq_ratios_init_lnl(struct ivpu_device *vdev)
+{
+	struct ivpu_hw_info *hw = vdev->hw;
+	u32 fmin_fuse, fmax_fuse;
+
+	fmin_fuse = REGB_RD32(VPU_HW_BTRS_LNL_FMIN_FUSE);
+	hw->pll.min_ratio = REG_GET_FLD(VPU_HW_BTRS_LNL_FMIN_FUSE, MIN_RATIO, fmin_fuse);
+	hw->pll.pn_ratio = REG_GET_FLD(VPU_HW_BTRS_LNL_FMIN_FUSE, PN_RATIO, fmin_fuse);
+
+	fmax_fuse = REGB_RD32(VPU_HW_BTRS_LNL_FMAX_FUSE);
+	hw->pll.max_ratio = REG_GET_FLD(VPU_HW_BTRS_LNL_FMAX_FUSE, MAX_RATIO, fmax_fuse);
+}
+
+void ivpu_hw_btrs_freq_ratios_init(struct ivpu_device *vdev)
+{
+	struct ivpu_hw_info *hw = vdev->hw;
+
+	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
+		freq_ratios_init_mtl(vdev);
+	else
+		freq_ratios_init_lnl(vdev);
+
+	hw->pll.min_ratio = clamp_t(u8, ivpu_pll_min_ratio, hw->pll.min_ratio, hw->pll.max_ratio);
+	hw->pll.max_ratio = clamp_t(u8, ivpu_pll_max_ratio, hw->pll.min_ratio, hw->pll.max_ratio);
+	hw->pll.pn_ratio = clamp_t(u8, hw->pll.pn_ratio, hw->pll.min_ratio, hw->pll.max_ratio);
+}
+
+static bool tile_disable_check(u32 config)
+{
+	/* Allowed values: 0 or one bit from range 0-5 (6 tiles) */
+	if (config == 0)
+		return true;
+
+	if (config > BIT(BTRS_LNL_TILE_MAX_NUM - 1))
+		return false;
+
+	if ((config & (config - 1)) == 0)
+		return true;
+
+	return false;
+}
+
+static int read_tile_config_fuse(struct ivpu_device *vdev, u32 *tile_fuse_config)
+{
+	u32 fuse;
+	u32 config;
+
+	fuse = REGB_RD32(VPU_HW_BTRS_LNL_TILE_FUSE);
+	if (!REG_TEST_FLD(VPU_HW_BTRS_LNL_TILE_FUSE, VALID, fuse)) {
+		ivpu_err(vdev, "Fuse: invalid (0x%x)\n", fuse);
+		return -EIO;
+	}
+
+	config = REG_GET_FLD(VPU_HW_BTRS_LNL_TILE_FUSE, CONFIG, fuse);
+	if (!tile_disable_check(config))
+		ivpu_warn(vdev, "More than 1 tile disabled, tile fuse config mask: 0x%x\n", config);
+
+	ivpu_dbg(vdev, MISC, "Tile disable config mask: 0x%x\n", config);
+
+	*tile_fuse_config = config;
+	return 0;
+}
+
+static int info_init_mtl(struct ivpu_device *vdev)
+{
+	struct ivpu_hw_info *hw = vdev->hw;
+
+	hw->tile_fuse = BTRS_MTL_TILE_FUSE_ENABLE_BOTH;
+	hw->sku = BTRS_MTL_TILE_SKU_BOTH;
+	hw->config = WP_CONFIG(MTL_CONFIG_2_TILE, MTL_PLL_RATIO_4_3);
+
+	return 0;
+}
+
+static int info_init_lnl(struct ivpu_device *vdev)
+{
+	struct ivpu_hw_info *hw = vdev->hw;
+	u32 tile_fuse_config;
+	int ret;
+
+	ret = read_tile_config_fuse(vdev, &tile_fuse_config);
+	if (ret)
+		return ret;
+
+	hw->tile_fuse = tile_fuse_config;
+	hw->pll.profiling_freq = PLL_PROFILING_FREQ_DEFAULT;
+
+	return 0;
+}
+
+int ivpu_hw_btrs_info_init(struct ivpu_device *vdev)
+{
+	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
+		return info_init_mtl(vdev);
+	else
+		return info_init_lnl(vdev);
+}
+
+static int wp_request_sync(struct ivpu_device *vdev)
+{
+	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
+		return REGB_POLL_FLD(VPU_HW_BTRS_MTL_WP_REQ_CMD, SEND, 0, PLL_TIMEOUT_US);
+	else
+		return REGB_POLL_FLD(VPU_HW_BTRS_LNL_WP_REQ_CMD, SEND, 0, PLL_TIMEOUT_US);
+}
+
+static int wait_for_status_ready(struct ivpu_device *vdev, bool enable)
+{
+	u32 exp_val = enable ? 0x1 : 0x0;
+
+	if (IVPU_WA(punit_disabled))
+		return 0;
+
+	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
+		return REGB_POLL_FLD(VPU_HW_BTRS_MTL_VPU_STATUS, READY, exp_val, PLL_TIMEOUT_US);
+	else
+		return REGB_POLL_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, READY, exp_val, PLL_TIMEOUT_US);
+}
+
+struct wp_request {
+	u16 min;
+	u16 max;
+	u16 target;
+	u16 cfg;
+	u16 epp;
+	u16 cdyn;
+};
+
+static void wp_request_mtl(struct ivpu_device *vdev, struct wp_request *wp)
+{
+	u32 val;
+
+	val = REGB_RD32(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0);
+	val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0, MIN_RATIO, wp->min, val);
+	val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0, MAX_RATIO, wp->max, val);
+	REGB_WR32(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0, val);
+
+	val = REGB_RD32(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1);
+	val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1, TARGET_RATIO, wp->target, val);
+	val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1, EPP, PLL_EPP_DEFAULT, val);
+	REGB_WR32(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1, val);
+
+	val = REGB_RD32(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2);
+	val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2, CONFIG, wp->cfg, val);
+	REGB_WR32(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2, val);
+
+	val = REGB_RD32(VPU_HW_BTRS_MTL_WP_REQ_CMD);
+	val = REG_SET_FLD(VPU_HW_BTRS_MTL_WP_REQ_CMD, SEND, val);
+	REGB_WR32(VPU_HW_BTRS_MTL_WP_REQ_CMD, val);
+}
+
+static void wp_request_lnl(struct ivpu_device *vdev, struct wp_request *wp)
+{
+	u32 val;
+
+	val = REGB_RD32(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0);
+	val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0, MIN_RATIO, wp->min, val);
+	val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0, MAX_RATIO, wp->max, val);
+	REGB_WR32(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0, val);
+
+	val = REGB_RD32(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1);
+	val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1, TARGET_RATIO, wp->target, val);
+	val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1, EPP, wp->epp, val);
+	REGB_WR32(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1, val);
+
+	val = REGB_RD32(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2);
+	val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2, CONFIG, wp->cfg, val);
+	val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2, CDYN, wp->cdyn, val);
+	REGB_WR32(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2, val);
+
+	val = REGB_RD32(VPU_HW_BTRS_LNL_WP_REQ_CMD);
+	val = REG_SET_FLD(VPU_HW_BTRS_LNL_WP_REQ_CMD, SEND, val);
+	REGB_WR32(VPU_HW_BTRS_LNL_WP_REQ_CMD, val);
+}
+
+static void wp_request(struct ivpu_device *vdev, struct wp_request *wp)
+{
+	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
+		wp_request_mtl(vdev, wp);
+	else
+		wp_request_lnl(vdev, wp);
+}
+
+static int wp_request_send(struct ivpu_device *vdev, struct wp_request *wp)
+{
+	int ret;
+
+	ret = wp_request_sync(vdev);
+	if (ret) {
+		ivpu_err(vdev, "Failed to sync before workpoint request: %d\n", ret);
+		return ret;
+	}
+
+	wp_request(vdev, wp);
+
+	ret = wp_request_sync(vdev);
+	if (ret)
+		ivpu_err(vdev, "Failed to sync after workpoint request: %d\n", ret);
+
+	return ret;
+}
+
+static void prepare_wp_request(struct ivpu_device *vdev, struct wp_request *wp, bool enable)
+{
+	struct ivpu_hw_info *hw = vdev->hw;
+
+	wp->min = hw->pll.min_ratio;
+	wp->max = hw->pll.max_ratio;
+
+	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) {
+		wp->target = enable ? hw->pll.pn_ratio : 0;
+		wp->cfg = enable ? hw->config : 0;
+		wp->cdyn = 0;
+		wp->epp = 0;
+	} else {
+		wp->target = hw->pll.pn_ratio;
+		wp->cfg = 0;
+		wp->cdyn = enable ? PLL_CDYN_DEFAULT : 0;
+		wp->epp = enable ? PLL_EPP_DEFAULT : 0;
+	}
+}
+
+static int wait_for_pll_lock(struct ivpu_device *vdev, bool enable)
+{
+	u32 exp_val = enable ? 0x1 : 0x0;
+
+	if (ivpu_hw_btrs_gen(vdev) != IVPU_HW_BTRS_MTL)
+		return 0;
+
+	if (IVPU_WA(punit_disabled))
+		return 0;
+
+	return REGB_POLL_FLD(VPU_HW_BTRS_MTL_PLL_STATUS, LOCK, exp_val, PLL_TIMEOUT_US);
+}
+
+static int wait_for_cdyn_deassert(struct ivpu_device *vdev)
+{
+	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
+		return 0;
+
+	return REGB_POLL_FLD(VPU_HW_BTRS_LNL_CDYN, CDYN, 0, PLL_TIMEOUT_US);
+}
+
+int ivpu_hw_btrs_wp_drive(struct ivpu_device *vdev, bool enable)
+{
+	struct wp_request wp;
+	int ret;
+
+	if (IVPU_WA(punit_disabled)) {
+		ivpu_dbg(vdev, PM, "Skipping workpoint request\n");
+		return 0;
+	}
+
+	prepare_wp_request(vdev, &wp, enable);
+
+	ivpu_dbg(vdev, PM, "PLL workpoint request: %lu MHz, config: 0x%x, epp: 0x%x, cdyn: 0x%x\n",
+		 pll_ratio_to_dpu_freq(vdev, wp.target) / HZ_PER_MHZ, wp.cfg, wp.epp, wp.cdyn);
+
+	ret = wp_request_send(vdev, &wp);
+	if (ret) {
+		ivpu_err(vdev, "Failed to send workpoint request: %d\n", ret);
+		return ret;
+	}
+
+	ret = wait_for_pll_lock(vdev, enable);
+	if (ret) {
+		ivpu_err(vdev, "Timed out waiting for PLL lock\n");
+		return ret;
+	}
+
+	ret = wait_for_status_ready(vdev, enable);
+	if (ret) {
+		ivpu_err(vdev, "Timed out waiting for NPU ready status\n");
+		return ret;
+	}
+
+	if (!enable) {
+		ret = wait_for_cdyn_deassert(vdev);
+		if (ret) {
+			ivpu_err(vdev, "Timed out waiting for CDYN deassert\n");
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static int d0i3_drive_mtl(struct ivpu_device *vdev, bool enable)
+{
+	int ret;
+	u32 val;
+
+	ret = REGB_POLL_FLD(VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL, INPROGRESS, 0, TIMEOUT_US);
+	if (ret) {
+		ivpu_err(vdev, "Failed to sync before D0i3 transition: %d\n", ret);
+		return ret;
+	}
+
+	val = REGB_RD32(VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL);
+	if (enable)
+		val = REG_SET_FLD(VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL, I3, val);
+	else
+		val = REG_CLR_FLD(VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL, I3, val);
+	REGB_WR32(VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL, val);
+
+	ret = REGB_POLL_FLD(VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL, INPROGRESS, 0, TIMEOUT_US);
+	if (ret)
+		ivpu_err(vdev, "Failed to sync after D0i3 transition: %d\n", ret);
+
+	return ret;
+}
+
+static int d0i3_drive_lnl(struct ivpu_device *vdev, bool enable)
+{
+	int ret;
+	u32 val;
+
+	ret = REGB_POLL_FLD(VPU_HW_BTRS_LNL_D0I3_CONTROL, INPROGRESS, 0, TIMEOUT_US);
+	if (ret) {
+		ivpu_err(vdev, "Failed to sync before D0i3 transition: %d\n", ret);
+		return ret;
+	}
+
+	val = REGB_RD32(VPU_HW_BTRS_LNL_D0I3_CONTROL);
+	if (enable)
+		val = REG_SET_FLD(VPU_HW_BTRS_LNL_D0I3_CONTROL, I3, val);
+	else
+		val = REG_CLR_FLD(VPU_HW_BTRS_LNL_D0I3_CONTROL, I3, val);
+	REGB_WR32(VPU_HW_BTRS_LNL_D0I3_CONTROL, val);
+
+	ret = REGB_POLL_FLD(VPU_HW_BTRS_LNL_D0I3_CONTROL, INPROGRESS, 0, TIMEOUT_US);
+	if (ret) {
+		ivpu_err(vdev, "Failed to sync after D0i3 transition: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int d0i3_drive(struct ivpu_device *vdev, bool enable)
+{
+	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
+		return d0i3_drive_mtl(vdev, enable);
+	else
+		return d0i3_drive_lnl(vdev, enable);
+}
+
+int ivpu_hw_btrs_d0i3_enable(struct ivpu_device *vdev)
+{
+	int ret;
+
+	if (IVPU_WA(punit_disabled))
+		return 0;
+
+	ret = d0i3_drive(vdev, true);
+	if (ret)
+		ivpu_err(vdev, "Failed to enable D0i3: %d\n", ret);
+
+	udelay(5); /* VPU requires 5 us to complete the transition */
+
+	return ret;
+}
+
+int ivpu_hw_btrs_d0i3_disable(struct ivpu_device *vdev)
+{
+	int ret;
+
+	if (IVPU_WA(punit_disabled))
+		return 0;
+
+	ret = d0i3_drive(vdev, false);
+	if (ret)
+		ivpu_err(vdev, "Failed to disable D0i3: %d\n", ret);
+
+	return ret;
+}
+
+int ivpu_hw_btrs_wait_for_clock_res_own_ack(struct ivpu_device *vdev)
+{
+	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
+		return 0;
+
+	return REGB_POLL_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, CLOCK_RESOURCE_OWN_ACK, 1, TIMEOUT_US);
+}
+
+void ivpu_hw_btrs_set_port_arbitration_weights_lnl(struct ivpu_device *vdev)
+{
+	REGB_WR32(VPU_HW_BTRS_LNL_PORT_ARBITRATION_WEIGHTS, WEIGHTS_DEFAULT);
+	REGB_WR32(VPU_HW_BTRS_LNL_PORT_ARBITRATION_WEIGHTS_ATS, WEIGHTS_ATS_DEFAULT);
+}
+
+static int ip_reset_mtl(struct ivpu_device *vdev)
+{
+	int ret;
+	u32 val;
+
+	ret = REGB_POLL_FLD(VPU_HW_BTRS_MTL_VPU_IP_RESET, TRIGGER, 0, TIMEOUT_US);
+	if (ret) {
+		ivpu_err(vdev, "Timed out waiting for TRIGGER bit\n");
+		return ret;
+	}
+
+	val = REGB_RD32(VPU_HW_BTRS_MTL_VPU_IP_RESET);
+	val = REG_SET_FLD(VPU_HW_BTRS_MTL_VPU_IP_RESET, TRIGGER, val);
+	REGB_WR32(VPU_HW_BTRS_MTL_VPU_IP_RESET, val);
+
+	ret = REGB_POLL_FLD(VPU_HW_BTRS_MTL_VPU_IP_RESET, TRIGGER, 0, TIMEOUT_US);
+	if (ret)
+		ivpu_err(vdev, "Timed out waiting for RESET completion\n");
+
+	return ret;
+}
+
+static int ip_reset_lnl(struct ivpu_device *vdev)
+{
+	int ret;
+	u32 val;
+
+	ivpu_hw_btrs_clock_relinquish_disable_lnl(vdev);
+
+	ret = REGB_POLL_FLD(VPU_HW_BTRS_LNL_IP_RESET, TRIGGER, 0, TIMEOUT_US);
+	if (ret) {
+		ivpu_err(vdev, "Wait for *_TRIGGER timed out\n");
+		return ret;
+	}
+
+	val = REGB_RD32(VPU_HW_BTRS_LNL_IP_RESET);
+	val = REG_SET_FLD(VPU_HW_BTRS_LNL_IP_RESET, TRIGGER, val);
+	REGB_WR32(VPU_HW_BTRS_LNL_IP_RESET, val);
+
+	ret = REGB_POLL_FLD(VPU_HW_BTRS_LNL_IP_RESET, TRIGGER, 0, TIMEOUT_US);
+	if (ret)
+		ivpu_err(vdev, "Timed out waiting for RESET completion\n");
+
+	return ret;
+}
+
+int ivpu_hw_btrs_ip_reset(struct ivpu_device *vdev)
+{
+	if (IVPU_WA(punit_disabled))
+		return 0;
+
+	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
+		return ip_reset_mtl(vdev);
+	else
+		return ip_reset_lnl(vdev);
+}
+
+void ivpu_hw_btrs_profiling_freq_reg_set_lnl(struct ivpu_device *vdev)
+{
+	u32 val = REGB_RD32(VPU_HW_BTRS_LNL_VPU_STATUS);
+
+	if (vdev->hw->pll.profiling_freq == PLL_PROFILING_FREQ_DEFAULT)
+		val = REG_CLR_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, PERF_CLK, val);
+	else
+		val = REG_SET_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, PERF_CLK, val);
+
+	REGB_WR32(VPU_HW_BTRS_LNL_VPU_STATUS, val);
+}
+
+void ivpu_hw_btrs_ats_print_lnl(struct ivpu_device *vdev)
+{
+	ivpu_dbg(vdev, MISC, "Buttress ATS: %s\n",
+		 REGB_RD32(VPU_HW_BTRS_LNL_HM_ATS) ? "Enable" : "Disable");
+}
+
+void ivpu_hw_btrs_clock_relinquish_disable_lnl(struct ivpu_device *vdev)
+{
+	u32 val = REGB_RD32(VPU_HW_BTRS_LNL_VPU_STATUS);
+
+	val = REG_SET_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, DISABLE_CLK_RELINQUISH, val);
+	REGB_WR32(VPU_HW_BTRS_LNL_VPU_STATUS, val);
+}
+
+bool ivpu_hw_btrs_is_idle(struct ivpu_device *vdev)
+{
+	u32 val;
+
+	if (IVPU_WA(punit_disabled))
+		return true;
+
+	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) {
+		val = REGB_RD32(VPU_HW_BTRS_MTL_VPU_STATUS);
+
+		return REG_TEST_FLD(VPU_HW_BTRS_MTL_VPU_STATUS, READY, val) &&
+		       REG_TEST_FLD(VPU_HW_BTRS_MTL_VPU_STATUS, IDLE, val);
+	} else {
+		val = REGB_RD32(VPU_HW_BTRS_LNL_VPU_STATUS);
+
+		return REG_TEST_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, READY, val) &&
+		       REG_TEST_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, IDLE, val);
+	}
+}
+
+int ivpu_hw_btrs_wait_for_idle(struct ivpu_device *vdev)
+{
+	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
+		return REGB_POLL_FLD(VPU_HW_BTRS_MTL_VPU_STATUS, IDLE, 0x1, IDLE_TIMEOUT_US);
+	else
+		return REGB_POLL_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, IDLE, 0x1, IDLE_TIMEOUT_US);
+}
+
+static u32 pll_config_get_mtl(struct ivpu_device *vdev)
+{
+	return REGB_RD32(VPU_HW_BTRS_MTL_CURRENT_PLL);
+}
+
+static u32 pll_config_get_lnl(struct ivpu_device *vdev)
+{
+	return REGB_RD32(VPU_HW_BTRS_LNL_PLL_FREQ);
+}
+
+static u32 pll_ratio_to_dpu_freq_mtl(u16 ratio)
+{
+	return (PLL_RATIO_TO_FREQ(ratio) * 2) / 3;
+}
+
+static u32 pll_ratio_to_dpu_freq_lnl(u16 ratio)
+{
+	return PLL_RATIO_TO_FREQ(ratio) / 2;
+}
+
+static u32 pll_ratio_to_dpu_freq(struct ivpu_device *vdev, u32 ratio)
+{
+	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
+		return pll_ratio_to_dpu_freq_mtl(ratio);
+	else
+		return pll_ratio_to_dpu_freq_lnl(ratio);
+}
+
+u32 ivpu_hw_btrs_dpu_max_freq_get(struct ivpu_device *vdev)
+{
+	return pll_ratio_to_dpu_freq(vdev, vdev->hw->pll.max_ratio);
+}
+
+u32 ivpu_hw_btrs_dpu_freq_get(struct ivpu_device *vdev)
+{
+	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
+		return pll_ratio_to_dpu_freq_mtl(pll_config_get_mtl(vdev));
+	else
+		return pll_ratio_to_dpu_freq_lnl(pll_config_get_lnl(vdev));
+}
+
+/* Handler for IRQs from Buttress core (irqB) */
+bool ivpu_hw_btrs_irq_handler_mtl(struct ivpu_device *vdev, int irq)
+{
+	u32 status = REGB_RD32(VPU_HW_BTRS_MTL_INTERRUPT_STAT) & BTRS_MTL_IRQ_MASK;
+	bool schedule_recovery = false;
+
+	if (!status)
+		return false;
+
+	if (REG_TEST_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, FREQ_CHANGE, status)) {
+		u32 pll = pll_config_get_mtl(vdev);
+
+		ivpu_dbg(vdev, IRQ, "FREQ_CHANGE irq, wp %08x, %lu MHz",
+			 pll, pll_ratio_to_dpu_freq_mtl(pll) / HZ_PER_MHZ);
+	}
+
+	if (REG_TEST_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, ATS_ERR, status)) {
+		ivpu_err(vdev, "ATS_ERR irq 0x%016llx", REGB_RD64(VPU_HW_BTRS_MTL_ATS_ERR_LOG_0));
+		REGB_WR32(VPU_HW_BTRS_MTL_ATS_ERR_CLEAR, 0x1);
+		schedule_recovery = true;
+	}
+
+	if (REG_TEST_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, UFI_ERR, status)) {
+		u32 ufi_log = REGB_RD32(VPU_HW_BTRS_MTL_UFI_ERR_LOG);
+
+		ivpu_err(vdev, "UFI_ERR irq (0x%08x) opcode: 0x%02lx axi_id: 0x%02lx cq_id: 0x%03lx",
+			 ufi_log, REG_GET_FLD(VPU_HW_BTRS_MTL_UFI_ERR_LOG, OPCODE, ufi_log),
+			 REG_GET_FLD(VPU_HW_BTRS_MTL_UFI_ERR_LOG, AXI_ID, ufi_log),
+			 REG_GET_FLD(VPU_HW_BTRS_MTL_UFI_ERR_LOG, CQ_ID, ufi_log));
+		REGB_WR32(VPU_HW_BTRS_MTL_UFI_ERR_CLEAR, 0x1);
+		schedule_recovery = true;
+	}
+
+	/* This must be done after interrupts are cleared at the source. */
+	if (IVPU_WA(interrupt_clear_with_0))
+		/*
+		 * Writing 1 triggers an interrupt, so we can't perform read update write.
+		 * Clear local interrupt status by writing 0 to all bits.
+		 */
+		REGB_WR32(VPU_HW_BTRS_MTL_INTERRUPT_STAT, 0x0);
+	else
+		REGB_WR32(VPU_HW_BTRS_MTL_INTERRUPT_STAT, status);
+
+	if (schedule_recovery)
+		ivpu_pm_trigger_recovery(vdev, "Buttress IRQ");
+
+	return true;
+}
+
+/* Handler for IRQs from Buttress core (irqB) */
+bool ivpu_hw_btrs_irq_handler_lnl(struct ivpu_device *vdev, int irq)
+{
+	u32 status = REGB_RD32(VPU_HW_BTRS_LNL_INTERRUPT_STAT) & BTRS_LNL_IRQ_MASK;
+	bool schedule_recovery = false;
+
+	if (!status)
+		return false;
+
+	if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, SURV_ERR, status)) {
+		ivpu_dbg(vdev, IRQ, "Survivability IRQ\n");
+		queue_work(system_percpu_wq, &vdev->irq_dct_work);
+	}
+
+	if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, FREQ_CHANGE, status)) {
+		u32 pll = pll_config_get_lnl(vdev);
+
+		ivpu_dbg(vdev, IRQ, "FREQ_CHANGE irq, wp %08x, %lu MHz",
+			 pll, pll_ratio_to_dpu_freq_lnl(pll) / HZ_PER_MHZ);
+	}
+
+	if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, ATS_ERR, status)) {
+		ivpu_err(vdev, "ATS_ERR LOG1 0x%08x ATS_ERR_LOG2 0x%08x\n",
+			 REGB_RD32(VPU_HW_BTRS_LNL_ATS_ERR_LOG1),
+			 REGB_RD32(VPU_HW_BTRS_LNL_ATS_ERR_LOG2));
+		REGB_WR32(VPU_HW_BTRS_LNL_ATS_ERR_CLEAR, 0x1);
+		schedule_recovery = true;
+	}
+
+	if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, CFI0_ERR, status)) {
+		ivpu_err(vdev, "CFI0_ERR 0x%08x", REGB_RD32(VPU_HW_BTRS_LNL_CFI0_ERR_LOG));
+		REGB_WR32(VPU_HW_BTRS_LNL_CFI0_ERR_CLEAR, 0x1);
+		schedule_recovery = true;
+	}
+
+	if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, CFI1_ERR, status)) {
+		ivpu_err(vdev, "CFI1_ERR 0x%08x", REGB_RD32(VPU_HW_BTRS_LNL_CFI1_ERR_LOG));
+		REGB_WR32(VPU_HW_BTRS_LNL_CFI1_ERR_CLEAR, 0x1);
+		schedule_recovery = true;
+	}
+
+	if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, IMR0_ERR, status)) {
+		ivpu_err(vdev, "IMR_ERR_CFI0 LOW: 0x%08x HIGH: 0x%08x",
+			 REGB_RD32(VPU_HW_BTRS_LNL_IMR_ERR_CFI0_LOW),
+			 REGB_RD32(VPU_HW_BTRS_LNL_IMR_ERR_CFI0_HIGH));
+		REGB_WR32(VPU_HW_BTRS_LNL_IMR_ERR_CFI0_CLEAR, 0x1);
+		schedule_recovery = true;
+	}
+
+	if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, IMR1_ERR, status)) {
+		ivpu_err(vdev, "IMR_ERR_CFI1 LOW: 0x%08x HIGH: 0x%08x",
+			 REGB_RD32(VPU_HW_BTRS_LNL_IMR_ERR_CFI1_LOW),
+			 REGB_RD32(VPU_HW_BTRS_LNL_IMR_ERR_CFI1_HIGH));
+		REGB_WR32(VPU_HW_BTRS_LNL_IMR_ERR_CFI1_CLEAR, 0x1);
+		schedule_recovery = true;
+	}
+
+	/* This must be done after interrupts are cleared at the source. */
+	REGB_WR32(VPU_HW_BTRS_LNL_INTERRUPT_STAT, status);
+
+	if (schedule_recovery)
+		ivpu_pm_trigger_recovery(vdev, "Buttress IRQ");
+
+	return true;
+}
+
+int ivpu_hw_btrs_dct_get_request(struct ivpu_device *vdev, bool *enable)
+{
+	u32 val = REGB_RD32(VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW);
+	u32 cmd = REG_GET_FLD(VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW, CMD, val);
+	u32 param1 = REG_GET_FLD(VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW, PARAM1, val);
+
+	if (cmd != DCT_REQ) {
+		ivpu_err_ratelimited(vdev, "Unsupported PCODE command: 0x%x\n", cmd);
+		return -EBADR;
+	}
+
+	switch (param1) {
+	case DCT_ENABLE:
+		*enable = true;
+		return 0;
+	case DCT_DISABLE:
+		*enable = false;
+		return 0;
+	default:
+		ivpu_err_ratelimited(vdev, "Invalid PARAM1 value: %u\n", param1);
+		return -EINVAL;
+	}
+}
+
+void ivpu_hw_btrs_dct_set_status(struct ivpu_device *vdev, bool enable, u8 active_percent)
+{
+	u32 val = 0;
+	u32 cmd = enable ? DCT_ENABLE : DCT_DISABLE;
+
+	val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS, CMD, DCT_REQ, val);
+	val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS, PARAM1, cmd, val);
+	val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS, PARAM2, active_percent, val);
+
+	REGB_WR32(VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS, val);
+}
+
+u32 ivpu_hw_btrs_telemetry_offset_get(struct ivpu_device *vdev)
+{
+	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
+		return REGB_RD32(VPU_HW_BTRS_MTL_VPU_TELEMETRY_OFFSET);
+	else
+		return REGB_RD32(VPU_HW_BTRS_LNL_VPU_TELEMETRY_OFFSET);
+}
+
+u32 ivpu_hw_btrs_telemetry_size_get(struct ivpu_device *vdev)
+{
+	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
+		return REGB_RD32(VPU_HW_BTRS_MTL_VPU_TELEMETRY_SIZE);
+	else
+		return REGB_RD32(VPU_HW_BTRS_LNL_VPU_TELEMETRY_SIZE);
+}
+
+u32 ivpu_hw_btrs_telemetry_enable_get(struct ivpu_device *vdev)
+{
+	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
+		return REGB_RD32(VPU_HW_BTRS_MTL_VPU_TELEMETRY_ENABLE);
+	else
+		return REGB_RD32(VPU_HW_BTRS_LNL_VPU_TELEMETRY_ENABLE);
+}
+
+void ivpu_hw_btrs_global_int_disable(struct ivpu_device *vdev)
+{
+	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
+		REGB_WR32(VPU_HW_BTRS_MTL_GLOBAL_INT_MASK, 0x1);
+	else
+		REGB_WR32(VPU_HW_BTRS_LNL_GLOBAL_INT_MASK, 0x1);
+}
+
+void ivpu_hw_btrs_global_int_enable(struct ivpu_device *vdev)
+{
+	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
+		REGB_WR32(VPU_HW_BTRS_MTL_GLOBAL_INT_MASK, 0x0);
+	else
+		REGB_WR32(VPU_HW_BTRS_LNL_GLOBAL_INT_MASK, 0x0);
+}
+
+void ivpu_hw_btrs_irq_enable(struct ivpu_device *vdev)
+{
+	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) {
+		REGB_WR32(VPU_HW_BTRS_MTL_LOCAL_INT_MASK, (u32)(~BTRS_MTL_IRQ_MASK));
+		REGB_WR32(VPU_HW_BTRS_MTL_GLOBAL_INT_MASK, 0x0);
+	} else {
+		REGB_WR32(VPU_HW_BTRS_LNL_LOCAL_INT_MASK, (u32)(~BTRS_LNL_IRQ_MASK));
+		REGB_WR32(VPU_HW_BTRS_LNL_GLOBAL_INT_MASK, 0x0);
+	}
+}
+
+void ivpu_hw_btrs_irq_disable(struct ivpu_device *vdev)
+{
+	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) {
+		REGB_WR32(VPU_HW_BTRS_MTL_GLOBAL_INT_MASK, 0x1);
+		REGB_WR32(VPU_HW_BTRS_MTL_LOCAL_INT_MASK, BTRS_IRQ_DISABLE_MASK);
+	} else {
+		REGB_WR32(VPU_HW_BTRS_LNL_GLOBAL_INT_MASK, 0x1);
+		REGB_WR32(VPU_HW_BTRS_LNL_LOCAL_INT_MASK, BTRS_IRQ_DISABLE_MASK);
+	}
+}
+
+static void diagnose_failure_mtl(struct ivpu_device *vdev)
+{
+	u32 reg = REGB_RD32(VPU_HW_BTRS_MTL_INTERRUPT_STAT) & BTRS_MTL_IRQ_MASK;
+
+	if (REG_TEST_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, ATS_ERR, reg))
+		ivpu_err(vdev, "ATS_ERR irq 0x%016llx", REGB_RD64(VPU_HW_BTRS_MTL_ATS_ERR_LOG_0));
+
+	if (REG_TEST_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, UFI_ERR, reg)) {
+		u32 log = REGB_RD32(VPU_HW_BTRS_MTL_UFI_ERR_LOG);
+
+		ivpu_err(vdev, "UFI_ERR irq (0x%08x) opcode: 0x%02lx axi_id: 0x%02lx cq_id: 0x%03lx",
+			 log, REG_GET_FLD(VPU_HW_BTRS_MTL_UFI_ERR_LOG, OPCODE, log),
+			 REG_GET_FLD(VPU_HW_BTRS_MTL_UFI_ERR_LOG, AXI_ID, log),
+			 REG_GET_FLD(VPU_HW_BTRS_MTL_UFI_ERR_LOG, CQ_ID, log));
+	}
+}
+
+static void diagnose_failure_lnl(struct ivpu_device *vdev)
+{
+	u32 reg = REGB_RD32(VPU_HW_BTRS_MTL_INTERRUPT_STAT) & BTRS_LNL_IRQ_MASK;
+
+	if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, ATS_ERR, reg)) {
+		ivpu_err(vdev, "ATS_ERR_LOG1 0x%08x ATS_ERR_LOG2 0x%08x\n",
+			 REGB_RD32(VPU_HW_BTRS_LNL_ATS_ERR_LOG1),
+			 REGB_RD32(VPU_HW_BTRS_LNL_ATS_ERR_LOG2));
+	}
+
+	if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, CFI0_ERR, reg))
+		ivpu_err(vdev, "CFI0_ERR_LOG 0x%08x\n", REGB_RD32(VPU_HW_BTRS_LNL_CFI0_ERR_LOG));
+
+	if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, CFI1_ERR, reg))
+		ivpu_err(vdev, "CFI1_ERR_LOG 0x%08x\n", REGB_RD32(VPU_HW_BTRS_LNL_CFI1_ERR_LOG));
+
+	if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, IMR0_ERR, reg))
+		ivpu_err(vdev, "IMR_ERR_CFI0 LOW: 0x%08x HIGH: 0x%08x\n",
+			 REGB_RD32(VPU_HW_BTRS_LNL_IMR_ERR_CFI0_LOW),
+			 REGB_RD32(VPU_HW_BTRS_LNL_IMR_ERR_CFI0_HIGH));
+
+	if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, IMR1_ERR, reg))
+		ivpu_err(vdev, "IMR_ERR_CFI1 LOW: 0x%08x HIGH: 0x%08x\n",
+			 REGB_RD32(VPU_HW_BTRS_LNL_IMR_ERR_CFI1_LOW),
+			 REGB_RD32(VPU_HW_BTRS_LNL_IMR_ERR_CFI1_HIGH));
+
+	if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, SURV_ERR, reg))
+		ivpu_err(vdev, "Survivability IRQ\n");
+}
+
+void ivpu_hw_btrs_diagnose_failure(struct ivpu_device *vdev)
+{
+	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)
+		return diagnose_failure_mtl(vdev);
+	else
+		return diagnose_failure_lnl(vdev);
+}
+
+int ivpu_hw_btrs_platform_read(struct ivpu_device *vdev)
+{
+	u32 reg = REGB_RD32(VPU_HW_BTRS_LNL_VPU_STATUS);
+
+	return REG_GET_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, PLATFORM, reg);
+}
diff --git a/drivers/accel/ivpu/ivpu_hw_btrs.h b/drivers/accel/ivpu/ivpu_hw_btrs.h
new file mode 100644
index 000000000000..c4c10e22f30f
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_hw_btrs.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2020-2025 Intel Corporation
+ */
+
+#ifndef __IVPU_HW_BTRS_H__
+#define __IVPU_HW_BTRS_H__
+
+#include "ivpu_drv.h"
+#include "ivpu_hw_37xx_reg.h"
+#include "ivpu_hw_40xx_reg.h"
+#include "ivpu_hw_reg_io.h"
+
+#define PLL_PROFILING_FREQ_DEFAULT   38400000
+#define PLL_PROFILING_FREQ_HIGH      400000000
+
+#define DCT_DEFAULT_ACTIVE_PERCENT 30u
+#define DCT_PERIOD_US		   35300u
+
+int ivpu_hw_btrs_info_init(struct ivpu_device *vdev);
+void ivpu_hw_btrs_freq_ratios_init(struct ivpu_device *vdev);
+int ivpu_hw_btrs_irqs_clear_with_0_mtl(struct ivpu_device *vdev);
+int ivpu_hw_btrs_wp_drive(struct ivpu_device *vdev, bool enable);
+int ivpu_hw_btrs_wait_for_clock_res_own_ack(struct ivpu_device *vdev);
+int ivpu_hw_btrs_d0i3_enable(struct ivpu_device *vdev);
+int ivpu_hw_btrs_d0i3_disable(struct ivpu_device *vdev);
+void ivpu_hw_btrs_set_port_arbitration_weights_lnl(struct ivpu_device *vdev);
+bool ivpu_hw_btrs_is_idle(struct ivpu_device *vdev);
+int ivpu_hw_btrs_wait_for_idle(struct ivpu_device *vdev);
+int ivpu_hw_btrs_ip_reset(struct ivpu_device *vdev);
+void ivpu_hw_btrs_profiling_freq_reg_set_lnl(struct ivpu_device *vdev);
+void ivpu_hw_btrs_ats_print_lnl(struct ivpu_device *vdev);
+void ivpu_hw_btrs_clock_relinquish_disable_lnl(struct ivpu_device *vdev);
+u32 ivpu_hw_btrs_dpu_max_freq_get(struct ivpu_device *vdev);
+u32 ivpu_hw_btrs_dpu_freq_get(struct ivpu_device *vdev);
+bool ivpu_hw_btrs_irq_handler_mtl(struct ivpu_device *vdev, int irq);
+bool ivpu_hw_btrs_irq_handler_lnl(struct ivpu_device *vdev, int irq);
+int ivpu_hw_btrs_dct_get_request(struct ivpu_device *vdev, bool *enable);
+void ivpu_hw_btrs_dct_set_status(struct ivpu_device *vdev, bool enable, u8 active_percent);
+u32 ivpu_hw_btrs_telemetry_offset_get(struct ivpu_device *vdev);
+u32 ivpu_hw_btrs_telemetry_size_get(struct ivpu_device *vdev);
+u32 ivpu_hw_btrs_telemetry_enable_get(struct ivpu_device *vdev);
+void ivpu_hw_btrs_global_int_enable(struct ivpu_device *vdev);
+void ivpu_hw_btrs_global_int_disable(struct ivpu_device *vdev);
+void ivpu_hw_btrs_irq_enable(struct ivpu_device *vdev);
+void ivpu_hw_btrs_irq_disable(struct ivpu_device *vdev);
+void ivpu_hw_btrs_diagnose_failure(struct ivpu_device *vdev);
+int ivpu_hw_btrs_platform_read(struct ivpu_device *vdev);
+
+#endif /* __IVPU_HW_BTRS_H__ */
diff --git a/drivers/accel/ivpu/ivpu_hw_btrs_lnl_reg.h b/drivers/accel/ivpu/ivpu_hw_btrs_lnl_reg.h
new file mode 100644
index 000000000000..a81a9ba540fa
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_hw_btrs_lnl_reg.h
@@ -0,0 +1,112 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2020-2024 Intel Corporation
+ */
+
+#ifndef __IVPU_HW_BTRS_LNL_REG_H__
+#define __IVPU_HW_BTRS_LNL_REG_H__
+
+#include <linux/bits.h>
+
+#define VPU_HW_BTRS_LNL_INTERRUPT_STAT				0x00000000u
+#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_FREQ_CHANGE_MASK		BIT_MASK(0)
+#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_ATS_ERR_MASK		BIT_MASK(1)
+#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_CFI0_ERR_MASK		BIT_MASK(2)
+#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_CFI1_ERR_MASK		BIT_MASK(3)
+#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_IMR0_ERR_MASK		BIT_MASK(4)
+#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_IMR1_ERR_MASK		BIT_MASK(5)
+#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_SURV_ERR_MASK		BIT_MASK(6)
+
+#define VPU_HW_BTRS_LNL_LOCAL_INT_MASK				0x00000004u
+#define VPU_HW_BTRS_LNL_GLOBAL_INT_MASK				0x00000008u
+
+#define VPU_HW_BTRS_LNL_HM_ATS					0x0000000cu
+
+#define VPU_HW_BTRS_LNL_ATS_ERR_LOG1				0x00000010u
+#define VPU_HW_BTRS_LNL_ATS_ERR_LOG2				0x00000014u
+#define VPU_HW_BTRS_LNL_ATS_ERR_CLEAR				0x00000018u
+
+#define VPU_HW_BTRS_LNL_CFI0_ERR_LOG				0x0000001cu
+#define VPU_HW_BTRS_LNL_CFI0_ERR_CLEAR				0x00000020u
+
+#define VPU_HW_BTRS_LNL_PORT_ARBITRATION_WEIGHTS_ATS		0x00000024u
+
+#define VPU_HW_BTRS_LNL_CFI1_ERR_LOG				0x00000040u
+#define VPU_HW_BTRS_LNL_CFI1_ERR_CLEAR				0x00000044u
+
+#define VPU_HW_BTRS_LNL_IMR_ERR_CFI0_LOW			0x00000048u
+#define VPU_HW_BTRS_LNL_IMR_ERR_CFI0_HIGH			0x0000004cu
+#define VPU_HW_BTRS_LNL_IMR_ERR_CFI0_CLEAR			0x00000050u
+
+#define VPU_HW_BTRS_LNL_PORT_ARBITRATION_WEIGHTS		0x00000054u
+
+#define VPU_HW_BTRS_LNL_IMR_ERR_CFI1_LOW			0x00000058u
+#define VPU_HW_BTRS_LNL_IMR_ERR_CFI1_HIGH			0x0000005cu
+#define VPU_HW_BTRS_LNL_IMR_ERR_CFI1_CLEAR			0x00000060u
+
+#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS			0x00000070u
+#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS_CMD_MASK		GENMASK(7, 0)
+#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS_PARAM1_MASK	GENMASK(15, 8)
+#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS_PARAM2_MASK	GENMASK(23, 16)
+#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS_PARAM3_MASK	GENMASK(31, 24)
+
+#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW			0x00000074u
+#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW_CMD_MASK		GENMASK(7, 0)
+#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW_PARAM1_MASK	GENMASK(15, 8)
+#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW_PARAM2_MASK	GENMASK(23, 16)
+#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW_PARAM3_MASK	GENMASK(31, 24)
+
+#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0				0x00000130u
+#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0_MIN_RATIO_MASK		GENMASK(15, 0)
+#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0_MAX_RATIO_MASK		GENMASK(31, 16)
+
+#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1				0x00000134u
+#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1_TARGET_RATIO_MASK	GENMASK(15, 0)
+#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1_EPP_MASK		GENMASK(31, 16)
+
+#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2				0x00000138u
+#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2_CONFIG_MASK		GENMASK(15, 0)
+#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2_CDYN_MASK		GENMASK(31, 16)
+
+#define VPU_HW_BTRS_LNL_WP_REQ_CMD				0x0000013cu
+#define VPU_HW_BTRS_LNL_WP_REQ_CMD_SEND_MASK			BIT_MASK(0)
+
+#define VPU_HW_BTRS_LNL_PLL_FREQ				0x00000148u
+#define VPU_HW_BTRS_LNL_PLL_FREQ_RATIO_MASK			GENMASK(15, 0)
+
+#define VPU_HW_BTRS_LNL_CDYN					0x0000014cu
+#define VPU_HW_BTRS_LNL_CDYN_CDYN_MASK				GENMASK(15, 0)
+
+#define VPU_HW_BTRS_LNL_TILE_FUSE				0x00000150u
+#define VPU_HW_BTRS_LNL_TILE_FUSE_VALID_MASK			BIT_MASK(0)
+#define VPU_HW_BTRS_LNL_TILE_FUSE_CONFIG_MASK			GENMASK(6, 1)
+
+#define VPU_HW_BTRS_LNL_VPU_STATUS				0x00000154u
+#define VPU_HW_BTRS_LNL_VPU_STATUS_READY_MASK			BIT_MASK(0)
+#define VPU_HW_BTRS_LNL_VPU_STATUS_IDLE_MASK			BIT_MASK(1)
+#define VPU_HW_BTRS_LNL_VPU_STATUS_DUP_IDLE_MASK		BIT_MASK(2)
+#define VPU_HW_BTRS_LNL_VPU_STATUS_CLOCK_RESOURCE_OWN_ACK_MASK	BIT_MASK(6)
+#define VPU_HW_BTRS_LNL_VPU_STATUS_POWER_RESOURCE_OWN_ACK_MASK	BIT_MASK(7)
+#define VPU_HW_BTRS_LNL_VPU_STATUS_PERF_CLK_MASK		BIT_MASK(11)
+#define VPU_HW_BTRS_LNL_VPU_STATUS_DISABLE_CLK_RELINQUISH_MASK  BIT_MASK(12)
+#define VPU_HW_BTRS_LNL_VPU_STATUS_PLATFORM_MASK		GENMASK(31, 29)
+
+#define VPU_HW_BTRS_LNL_IP_RESET				0x00000160u
+#define VPU_HW_BTRS_LNL_IP_RESET_TRIGGER_MASK			BIT_MASK(0)
+
+#define VPU_HW_BTRS_LNL_D0I3_CONTROL				0x00000164u
+#define VPU_HW_BTRS_LNL_D0I3_CONTROL_INPROGRESS_MASK		BIT_MASK(0)
+#define VPU_HW_BTRS_LNL_D0I3_CONTROL_I3_MASK			BIT_MASK(2)
+
+#define VPU_HW_BTRS_LNL_VPU_TELEMETRY_OFFSET			0x00000168u
+#define VPU_HW_BTRS_LNL_VPU_TELEMETRY_SIZE			0x0000016cu
+#define VPU_HW_BTRS_LNL_VPU_TELEMETRY_ENABLE			0x00000170u
+
+#define VPU_HW_BTRS_LNL_FMIN_FUSE				0x00000174u
+#define VPU_HW_BTRS_LNL_FMIN_FUSE_MIN_RATIO_MASK		GENMASK(7, 0)
+#define VPU_HW_BTRS_LNL_FMIN_FUSE_PN_RATIO_MASK			GENMASK(15, 8)
+
+#define VPU_HW_BTRS_LNL_FMAX_FUSE				0x00000178u
+#define VPU_HW_BTRS_LNL_FMAX_FUSE_MAX_RATIO_MASK		GENMASK(7, 0)
+
+#endif /* __IVPU_HW_BTRS_LNL_REG_H__ */
diff --git a/drivers/accel/ivpu/ivpu_hw_btrs_mtl_reg.h b/drivers/accel/ivpu/ivpu_hw_btrs_mtl_reg.h
new file mode 100644
index 000000000000..e93d539e066f
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_hw_btrs_mtl_reg.h
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2020-2023 Intel Corporation
+ */
+
+#ifndef __IVPU_HW_BTRS_MTL_REG_H__
+#define __IVPU_HW_BTRS_MTL_REG_H__
+
+#include <linux/bits.h>
+
+#define VPU_HW_BTRS_MTL_INTERRUPT_TYPE				0x00000000u
+
+#define VPU_HW_BTRS_MTL_INTERRUPT_STAT				0x00000004u
+#define VPU_HW_BTRS_MTL_INTERRUPT_STAT_FREQ_CHANGE_MASK		BIT_MASK(0)
+#define VPU_HW_BTRS_MTL_INTERRUPT_STAT_ATS_ERR_MASK		BIT_MASK(1)
+#define VPU_HW_BTRS_MTL_INTERRUPT_STAT_UFI_ERR_MASK		BIT_MASK(2)
+
+#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0				0x00000008u
+#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0_MIN_RATIO_MASK		GENMASK(15, 0)
+#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0_MAX_RATIO_MASK		GENMASK(31, 16)
+
+#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1				0x0000000cu
+#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1_TARGET_RATIO_MASK	GENMASK(15, 0)
+#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1_EPP_MASK		GENMASK(31, 16)
+
+#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2				0x00000010u
+#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2_CONFIG_MASK		GENMASK(15, 0)
+
+#define VPU_HW_BTRS_MTL_WP_REQ_CMD				0x00000014u
+#define VPU_HW_BTRS_MTL_WP_REQ_CMD_SEND_MASK			BIT_MASK(0)
+
+#define VPU_HW_BTRS_MTL_WP_DOWNLOAD				0x00000018u
+#define VPU_HW_BTRS_MTL_WP_DOWNLOAD_TARGET_RATIO_MASK		GENMASK(15, 0)
+
+#define VPU_HW_BTRS_MTL_CURRENT_PLL				0x0000001cu
+#define VPU_HW_BTRS_MTL_CURRENT_PLL_RATIO_MASK			GENMASK(15, 0)
+
+#define VPU_HW_BTRS_MTL_PLL_ENABLE				0x00000020u
+
+#define VPU_HW_BTRS_MTL_FMIN_FUSE				0x00000024u
+#define VPU_HW_BTRS_MTL_FMIN_FUSE_MIN_RATIO_MASK		GENMASK(7, 0)
+#define VPU_HW_BTRS_MTL_FMIN_FUSE_PN_RATIO_MASK			GENMASK(15, 8)
+
+#define VPU_HW_BTRS_MTL_FMAX_FUSE				0x00000028u
+#define VPU_HW_BTRS_MTL_FMAX_FUSE_MAX_RATIO_MASK		GENMASK(7, 0)
+
+#define VPU_HW_BTRS_MTL_TILE_FUSE				0x0000002cu
+#define VPU_HW_BTRS_MTL_TILE_FUSE_VALID_MASK			BIT_MASK(0)
+#define VPU_HW_BTRS_MTL_TILE_FUSE_SKU_MASK			GENMASK(3, 2)
+
+#define VPU_HW_BTRS_MTL_LOCAL_INT_MASK				0x00000030u
+#define VPU_HW_BTRS_MTL_GLOBAL_INT_MASK				0x00000034u
+
+#define VPU_HW_BTRS_MTL_PLL_STATUS				0x00000040u
+#define VPU_HW_BTRS_MTL_PLL_STATUS_LOCK_MASK			BIT_MASK(1)
+
+#define VPU_HW_BTRS_MTL_VPU_STATUS				0x00000044u
+#define VPU_HW_BTRS_MTL_VPU_STATUS_READY_MASK			BIT_MASK(0)
+#define VPU_HW_BTRS_MTL_VPU_STATUS_IDLE_MASK			BIT_MASK(1)
+
+#define VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL			0x00000060u
+#define VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL_INPROGRESS_MASK	BIT_MASK(0)
+#define VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL_I3_MASK		BIT_MASK(2)
+
+#define VPU_HW_BTRS_MTL_VPU_IP_RESET				0x00000050u
+#define VPU_HW_BTRS_MTL_VPU_IP_RESET_TRIGGER_MASK		BIT_MASK(0)
+
+#define VPU_HW_BTRS_MTL_VPU_TELEMETRY_OFFSET			0x00000080u
+#define VPU_HW_BTRS_MTL_VPU_TELEMETRY_SIZE			0x00000084u
+#define VPU_HW_BTRS_MTL_VPU_TELEMETRY_ENABLE			0x00000088u
+
+#define VPU_HW_BTRS_MTL_ATS_ERR_LOG_0				0x000000a0u
+#define VPU_HW_BTRS_MTL_ATS_ERR_LOG_1				0x000000a4u
+#define VPU_HW_BTRS_MTL_ATS_ERR_CLEAR				0x000000a8u
+
+#define VPU_HW_BTRS_MTL_UFI_ERR_LOG				0x000000b0u
+#define VPU_HW_BTRS_MTL_UFI_ERR_LOG_CQ_ID_MASK			GENMASK(11, 0)
+#define VPU_HW_BTRS_MTL_UFI_ERR_LOG_AXI_ID_MASK			GENMASK(19, 12)
+#define VPU_HW_BTRS_MTL_UFI_ERR_LOG_OPCODE_MASK			GENMASK(24, 20)
+
+#define VPU_HW_BTRS_MTL_UFI_ERR_CLEAR				0x000000b4u
+
+#endif /* __IVPU_HW_BTRS_MTL_REG_H__ */
diff --git a/drivers/accel/ivpu/ivpu_hw_ip.c b/drivers/accel/ivpu/ivpu_hw_ip.c
new file mode 100644
index 000000000000..06aa1e7dc50b
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_hw_ip.c
@@ -0,0 +1,1199 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020-2024 Intel Corporation
+ */
+
+#include "ivpu_drv.h"
+#include "ivpu_fw.h"
+#include "ivpu_hw.h"
+#include "ivpu_hw_37xx_reg.h"
+#include "ivpu_hw_40xx_reg.h"
+#include "ivpu_hw_btrs.h"
+#include "ivpu_hw_ip.h"
+#include "ivpu_hw_reg_io.h"
+#include "ivpu_mmu.h"
+#include "ivpu_pm.h"
+
+#define PWR_ISLAND_STATUS_TIMEOUT_US        (5 * USEC_PER_MSEC)
+
+#define TIM_SAFE_ENABLE		            0xf1d0dead
+#define TIM_WATCHDOG_RESET_VALUE            0xffffffff
+
+#define ICB_0_IRQ_MASK_37XX ((REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, HOST_IPC_FIFO_INT)) | \
+			     (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_0_INT)) | \
+			     (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_1_INT)) | \
+			     (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_2_INT)) | \
+			     (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT)) | \
+			     (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT)) | \
+			     (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT)))
+
+#define ICB_1_IRQ_MASK_37XX ((REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_2_INT)) | \
+			     (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_3_INT)) | \
+			     (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_4_INT)))
+
+#define ICB_0_1_IRQ_MASK_37XX ((((u64)ICB_1_IRQ_MASK_37XX) << 32) | ICB_0_IRQ_MASK_37XX)
+
+#define ICB_0_IRQ_MASK_40XX ((REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, HOST_IPC_FIFO_INT)) | \
+			     (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_0_INT)) | \
+			     (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_1_INT)) | \
+			     (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_2_INT)) | \
+			     (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT)) | \
+			     (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT)) | \
+			     (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT)))
+
+#define ICB_1_IRQ_MASK_40XX ((REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_2_INT)) | \
+			     (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_3_INT)) | \
+			     (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_4_INT)))
+
+#define ICB_0_1_IRQ_MASK_40XX ((((u64)ICB_1_IRQ_MASK_40XX) << 32) | ICB_0_IRQ_MASK_40XX)
+
+#define ITF_FIREWALL_VIOLATION_MASK_37XX ((REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, CSS_ROM_CMX)) | \
+					  (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, CSS_DBG)) | \
+					  (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, CSS_CTRL)) | \
+					  (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, DEC400)) | \
+					  (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, MSS_NCE)) | \
+					  (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI)) | \
+					  (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI_CMX)))
+
+#define ITF_FIREWALL_VIOLATION_MASK_40XX ((REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, CSS_ROM_CMX)) | \
+					  (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, CSS_DBG)) | \
+					  (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, CSS_CTRL)) | \
+					  (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, DEC400)) | \
+					  (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, MSS_NCE)) | \
+					  (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI)) | \
+					  (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI_CMX)))
+
+static int wait_for_ip_bar(struct ivpu_device *vdev)
+{
+	return REGV_POLL_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, AON, 0, 100);
+}
+
+static void host_ss_rst_clr(struct ivpu_device *vdev)
+{
+	u32 val = 0;
+
+	val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, TOP_NOC, val);
+	val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, DSS_MAS, val);
+	val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, MSS_MAS, val);
+
+	REGV_WR32(VPU_37XX_HOST_SS_CPR_RST_CLR, val);
+}
+
+static int host_ss_noc_qreqn_check_37xx(struct ivpu_device *vdev, u32 exp_val)
+{
+	u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QREQN);
+
+	if (!REG_TEST_FLD_NUM(VPU_37XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, exp_val, val))
+		return -EIO;
+
+	return 0;
+}
+
+static int host_ss_noc_qreqn_check_40xx(struct ivpu_device *vdev, u32 exp_val)
+{
+	u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QREQN);
+
+	if (!REG_TEST_FLD_NUM(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, exp_val, val))
+		return -EIO;
+
+	return 0;
+}
+
+static int host_ss_noc_qreqn_check(struct ivpu_device *vdev, u32 exp_val)
+{
+	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
+		return host_ss_noc_qreqn_check_37xx(vdev, exp_val);
+	else
+		return host_ss_noc_qreqn_check_40xx(vdev, exp_val);
+}
+
+static int host_ss_noc_qacceptn_check_37xx(struct ivpu_device *vdev, u32 exp_val)
+{
+	u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QACCEPTN);
+
+	if (!REG_TEST_FLD_NUM(VPU_37XX_HOST_SS_NOC_QACCEPTN, TOP_SOCMMIO, exp_val, val))
+		return -EIO;
+
+	return 0;
+}
+
+static int host_ss_noc_qacceptn_check_40xx(struct ivpu_device *vdev, u32 exp_val)
+{
+	u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QACCEPTN);
+
+	if (!REG_TEST_FLD_NUM(VPU_40XX_HOST_SS_NOC_QACCEPTN, TOP_SOCMMIO, exp_val, val))
+		return -EIO;
+
+	return 0;
+}
+
+static int host_ss_noc_qacceptn_check(struct ivpu_device *vdev, u32 exp_val)
+{
+	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
+		return host_ss_noc_qacceptn_check_37xx(vdev, exp_val);
+	else
+		return host_ss_noc_qacceptn_check_40xx(vdev, exp_val);
+}
+
+static int host_ss_noc_qdeny_check_37xx(struct ivpu_device *vdev, u32 exp_val)
+{
+	u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QDENY);
+
+	if (!REG_TEST_FLD_NUM(VPU_37XX_HOST_SS_NOC_QDENY, TOP_SOCMMIO, exp_val, val))
+		return -EIO;
+
+	return 0;
+}
+
+static int host_ss_noc_qdeny_check_40xx(struct ivpu_device *vdev, u32 exp_val)
+{
+	u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QDENY);
+
+	if (!REG_TEST_FLD_NUM(VPU_40XX_HOST_SS_NOC_QDENY, TOP_SOCMMIO, exp_val, val))
+		return -EIO;
+
+	return 0;
+}
+
+static int host_ss_noc_qdeny_check(struct ivpu_device *vdev, u32 exp_val)
+{
+	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
+		return host_ss_noc_qdeny_check_37xx(vdev, exp_val);
+	else
+		return host_ss_noc_qdeny_check_40xx(vdev, exp_val);
+}
+
+static int top_noc_qrenqn_check_37xx(struct ivpu_device *vdev, u32 exp_val)
+{
+	u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QREQN);
+
+	if (!REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QREQN, CPU_CTRL, exp_val, val) ||
+	    !REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, exp_val, val))
+		return -EIO;
+
+	return 0;
+}
+
+static int top_noc_qrenqn_check_40xx(struct ivpu_device *vdev, u32 exp_val)
+{
+	u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QREQN);
+
+	if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, exp_val, val) ||
+	    !REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, exp_val, val))
+		return -EIO;
+
+	return 0;
+}
+
+static int top_noc_qreqn_check(struct ivpu_device *vdev, u32 exp_val)
+{
+	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
+		return top_noc_qrenqn_check_37xx(vdev, exp_val);
+	else
+		return top_noc_qrenqn_check_40xx(vdev, exp_val);
+}
+
+int ivpu_hw_ip_host_ss_configure(struct ivpu_device *vdev)
+{
+	int ret;
+
+	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) {
+		ret = wait_for_ip_bar(vdev);
+		if (ret) {
+			ivpu_err(vdev, "Timed out waiting for NPU IP bar\n");
+			return ret;
+		}
+		host_ss_rst_clr(vdev);
+	}
+
+	ret = host_ss_noc_qreqn_check(vdev, 0x0);
+	if (ret) {
+		ivpu_err(vdev, "Failed qreqn check: %d\n", ret);
+		return ret;
+	}
+
+	ret = host_ss_noc_qacceptn_check(vdev, 0x0);
+	if (ret) {
+		ivpu_err(vdev, "Failed qacceptn check: %d\n", ret);
+		return ret;
+	}
+
+	ret = host_ss_noc_qdeny_check(vdev, 0x0);
+	if (ret)
+		ivpu_err(vdev, "Failed qdeny check %d\n", ret);
+
+	return ret;
+}
+
+static void idle_gen_drive_37xx(struct ivpu_device *vdev, bool enable)
+{
+	u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN);
+
+	if (enable)
+		val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN, EN, val);
+	else
+		val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN, EN, val);
+
+	REGV_WR32(VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN, val);
+}
+
+static void idle_gen_drive_40xx(struct ivpu_device *vdev, bool enable)
+{
+	u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_IDLE_GEN);
+
+	if (enable)
+		val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_IDLE_GEN, EN, val);
+	else
+		val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_IDLE_GEN, EN, val);
+
+	REGV_WR32(VPU_40XX_HOST_SS_AON_IDLE_GEN, val);
+}
+
+void ivpu_hw_ip_idle_gen_enable(struct ivpu_device *vdev)
+{
+	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
+		idle_gen_drive_37xx(vdev, true);
+	else
+		idle_gen_drive_40xx(vdev, true);
+}
+
+void ivpu_hw_ip_idle_gen_disable(struct ivpu_device *vdev)
+{
+	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
+		idle_gen_drive_37xx(vdev, false);
+	else
+		idle_gen_drive_40xx(vdev, false);
+}
+
+static void
+pwr_island_delay_set_50xx(struct ivpu_device *vdev, u32 post, u32 post1, u32 post2, u32 status)
+{
+	u32 val;
+
+	val = REGV_RD32(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY);
+	val = REG_SET_FLD_NUM(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY, POST_DLY, post, val);
+	val = REG_SET_FLD_NUM(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY, POST1_DLY, post1, val);
+	val = REG_SET_FLD_NUM(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY, POST2_DLY, post2, val);
+	REGV_WR32(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY, val);
+
+	val = REGV_RD32(VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY);
+	val = REG_SET_FLD_NUM(VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY, STATUS_DLY, status, val);
+	REGV_WR32(VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY, val);
+}
+
+static void pwr_island_trickle_drive_37xx(struct ivpu_device *vdev, bool enable)
+{
+	u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0);
+
+	if (enable)
+		val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, MSS_CPU, val);
+	else
+		val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, MSS_CPU, val);
+
+	REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, val);
+}
+
+static void pwr_island_trickle_drive_40xx(struct ivpu_device *vdev, bool enable)
+{
+	u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0);
+
+	if (enable)
+		val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, CSS_CPU, val);
+	else
+		val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, CSS_CPU, val);
+
+	REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, val);
+}
+
+static void pwr_island_drive_37xx(struct ivpu_device *vdev, bool enable)
+{
+	u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0);
+
+	if (enable)
+		val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, CSS_CPU, val);
+	else
+		val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, CSS_CPU, val);
+
+	REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, val);
+}
+
+static void pwr_island_drive_40xx(struct ivpu_device *vdev, bool enable)
+{
+	u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0);
+
+	if (enable)
+		val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, MSS_CPU, val);
+	else
+		val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, MSS_CPU, val);
+
+	REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, val);
+}
+
+static void pwr_island_enable(struct ivpu_device *vdev)
+{
+	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) {
+		pwr_island_trickle_drive_37xx(vdev, true);
+		ndelay(500);
+		pwr_island_drive_37xx(vdev, true);
+	} else {
+		pwr_island_trickle_drive_40xx(vdev, true);
+		ndelay(500);
+		pwr_island_drive_40xx(vdev, true);
+	}
+}
+
+static int wait_for_pwr_island_status(struct ivpu_device *vdev, u32 exp_val)
+{
+	if (IVPU_WA(punit_disabled))
+		return 0;
+
+	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
+		return REGV_POLL_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_STATUS0, MSS_CPU, exp_val,
+				     PWR_ISLAND_STATUS_TIMEOUT_US);
+	else
+		return REGV_POLL_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_STATUS0, CSS_CPU, exp_val,
+				     PWR_ISLAND_STATUS_TIMEOUT_US);
+}
+
+static void pwr_island_isolation_drive_37xx(struct ivpu_device *vdev, bool enable)
+{
+	u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0);
+
+	if (enable)
+		val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0, MSS_CPU, val);
+	else
+		val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0, MSS_CPU, val);
+
+	REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0, val);
+}
+
+static void pwr_island_isolation_drive_40xx(struct ivpu_device *vdev, bool enable)
+{
+	u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0);
+
+	if (enable)
+		val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, CSS_CPU, val);
+	else
+		val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, CSS_CPU, val);
+
+	REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, val);
+}
+
+static void pwr_island_isolation_drive(struct ivpu_device *vdev, bool enable)
+{
+	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
+		pwr_island_isolation_drive_37xx(vdev, enable);
+	else
+		pwr_island_isolation_drive_40xx(vdev, enable);
+}
+
+static void pwr_island_isolation_disable(struct ivpu_device *vdev)
+{
+	pwr_island_isolation_drive(vdev, false);
+}
+
+static void host_ss_clk_drive_37xx(struct ivpu_device *vdev, bool enable)
+{
+	u32 val = REGV_RD32(VPU_37XX_HOST_SS_CPR_CLK_SET);
+
+	if (enable) {
+		val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, TOP_NOC, val);
+		val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, DSS_MAS, val);
+		val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, MSS_MAS, val);
+	} else {
+		val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, TOP_NOC, val);
+		val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, DSS_MAS, val);
+		val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, MSS_MAS, val);
+	}
+
+	REGV_WR32(VPU_37XX_HOST_SS_CPR_CLK_SET, val);
+}
+
+static void host_ss_clk_drive_40xx(struct ivpu_device *vdev, bool enable)
+{
+	u32 val = REGV_RD32(VPU_40XX_HOST_SS_CPR_CLK_EN);
+
+	if (enable) {
+		val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, TOP_NOC, val);
+		val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, DSS_MAS, val);
+		val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, CSS_MAS, val);
+	} else {
+		val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, TOP_NOC, val);
+		val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, DSS_MAS, val);
+		val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, CSS_MAS, val);
+	}
+
+	REGV_WR32(VPU_40XX_HOST_SS_CPR_CLK_EN, val);
+}
+
+static void host_ss_clk_drive(struct ivpu_device *vdev, bool enable)
+{
+	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
+		host_ss_clk_drive_37xx(vdev, enable);
+	else
+		host_ss_clk_drive_40xx(vdev, enable);
+}
+
+static void host_ss_clk_enable(struct ivpu_device *vdev)
+{
+	host_ss_clk_drive(vdev, true);
+}
+
+static void host_ss_rst_drive_37xx(struct ivpu_device *vdev, bool enable)
+{
+	u32 val = REGV_RD32(VPU_37XX_HOST_SS_CPR_RST_SET);
+
+	if (enable) {
+		val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, TOP_NOC, val);
+		val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, DSS_MAS, val);
+		val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, MSS_MAS, val);
+	} else {
+		val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, TOP_NOC, val);
+		val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, DSS_MAS, val);
+		val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, MSS_MAS, val);
+	}
+
+	REGV_WR32(VPU_37XX_HOST_SS_CPR_RST_SET, val);
+}
+
+static void host_ss_rst_drive_40xx(struct ivpu_device *vdev, bool enable)
+{
+	u32 val = REGV_RD32(VPU_40XX_HOST_SS_CPR_RST_EN);
+
+	if (enable) {
+		val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, TOP_NOC, val);
+		val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, DSS_MAS, val);
+		val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, CSS_MAS, val);
+	} else {
+		val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, TOP_NOC, val);
+		val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, DSS_MAS, val);
+		val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, CSS_MAS, val);
+	}
+
+	REGV_WR32(VPU_40XX_HOST_SS_CPR_RST_EN, val);
+}
+
+static void host_ss_rst_drive(struct ivpu_device *vdev, bool enable)
+{
+	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
+		host_ss_rst_drive_37xx(vdev, enable);
+	else
+		host_ss_rst_drive_40xx(vdev, enable);
+}
+
+static void host_ss_rst_enable(struct ivpu_device *vdev)
+{
+	host_ss_rst_drive(vdev, true);
+}
+
+static void host_ss_noc_qreqn_top_socmmio_drive_37xx(struct ivpu_device *vdev, bool enable)
+{
+	u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QREQN);
+
+	if (enable)
+		val = REG_SET_FLD(VPU_37XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val);
+	else
+		val = REG_CLR_FLD(VPU_37XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val);
+	REGV_WR32(VPU_37XX_HOST_SS_NOC_QREQN, val);
+}
+
+static void host_ss_noc_qreqn_top_socmmio_drive_40xx(struct ivpu_device *vdev, bool enable)
+{
+	u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QREQN);
+
+	if (enable)
+		val = REG_SET_FLD(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val);
+	else
+		val = REG_CLR_FLD(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val);
+	REGV_WR32(VPU_40XX_HOST_SS_NOC_QREQN, val);
+}
+
+static void host_ss_noc_qreqn_top_socmmio_drive(struct ivpu_device *vdev, bool enable)
+{
+	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
+		host_ss_noc_qreqn_top_socmmio_drive_37xx(vdev, enable);
+	else
+		host_ss_noc_qreqn_top_socmmio_drive_40xx(vdev, enable);
+}
+
+static int host_ss_axi_drive(struct ivpu_device *vdev, bool enable)
+{
+	int ret;
+
+	host_ss_noc_qreqn_top_socmmio_drive(vdev, enable);
+
+	ret = host_ss_noc_qacceptn_check(vdev, enable ? 0x1 : 0x0);
+	if (ret) {
+		ivpu_err(vdev, "Failed HOST SS NOC QACCEPTN check: %d\n", ret);
+		return ret;
+	}
+
+	ret = host_ss_noc_qdeny_check(vdev, 0x0);
+	if (ret)
+		ivpu_err(vdev, "Failed HOST SS NOC QDENY check: %d\n", ret);
+
+	return ret;
+}
+
+static void top_noc_qreqn_drive_40xx(struct ivpu_device *vdev, bool enable)
+{
+	u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QREQN);
+
+	if (enable) {
+		val = REG_SET_FLD(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, val);
+		val = REG_SET_FLD(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val);
+	} else {
+		val = REG_CLR_FLD(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, val);
+		val = REG_CLR_FLD(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val);
+	}
+
+	REGV_WR32(VPU_40XX_TOP_NOC_QREQN, val);
+}
+
+static void top_noc_qreqn_drive_37xx(struct ivpu_device *vdev, bool enable)
+{
+	u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QREQN);
+
+	if (enable) {
+		val = REG_SET_FLD(VPU_37XX_TOP_NOC_QREQN, CPU_CTRL, val);
+		val = REG_SET_FLD(VPU_37XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val);
+	} else {
+		val = REG_CLR_FLD(VPU_37XX_TOP_NOC_QREQN, CPU_CTRL, val);
+		val = REG_CLR_FLD(VPU_37XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val);
+	}
+
+	REGV_WR32(VPU_37XX_TOP_NOC_QREQN, val);
+}
+
+static void top_noc_qreqn_drive(struct ivpu_device *vdev, bool enable)
+{
+	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
+		top_noc_qreqn_drive_37xx(vdev, enable);
+	else
+		top_noc_qreqn_drive_40xx(vdev, enable);
+}
+
+int ivpu_hw_ip_host_ss_axi_enable(struct ivpu_device *vdev)
+{
+	return host_ss_axi_drive(vdev, true);
+}
+
+static int top_noc_qacceptn_check_37xx(struct ivpu_device *vdev, u32 exp_val)
+{
+	u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QACCEPTN);
+
+	if (!REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QACCEPTN, CPU_CTRL, exp_val, val) ||
+	    !REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QACCEPTN, HOSTIF_L2CACHE, exp_val, val))
+		return -EIO;
+
+	return 0;
+}
+
+static int top_noc_qacceptn_check_40xx(struct ivpu_device *vdev, u32 exp_val)
+{
+	u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QACCEPTN);
+
+	if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QACCEPTN, CPU_CTRL, exp_val, val) ||
+	    !REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QACCEPTN, HOSTIF_L2CACHE, exp_val, val))
+		return -EIO;
+
+	return 0;
+}
+
+static int top_noc_qacceptn_check(struct ivpu_device *vdev, u32 exp_val)
+{
+	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
+		return top_noc_qacceptn_check_37xx(vdev, exp_val);
+	else
+		return top_noc_qacceptn_check_40xx(vdev, exp_val);
+}
+
+static int top_noc_qdeny_check_37xx(struct ivpu_device *vdev, u32 exp_val)
+{
+	u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QDENY);
+
+	if (!REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QDENY, CPU_CTRL, exp_val, val) ||
+	    !REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QDENY, HOSTIF_L2CACHE, exp_val, val))
+		return -EIO;
+
+	return 0;
+}
+
+static int top_noc_qdeny_check_40xx(struct ivpu_device *vdev, u32 exp_val)
+{
+	u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QDENY);
+
+	if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QDENY, CPU_CTRL, exp_val, val) ||
+	    !REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QDENY, HOSTIF_L2CACHE, exp_val, val))
+		return -EIO;
+
+	return 0;
+}
+
+static int top_noc_qdeny_check(struct ivpu_device *vdev, u32 exp_val)
+{
+	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
+		return top_noc_qdeny_check_37xx(vdev, exp_val);
+	else
+		return top_noc_qdeny_check_40xx(vdev, exp_val);
+}
+
+static int top_noc_drive(struct ivpu_device *vdev, bool enable)
+{
+	int ret;
+
+	top_noc_qreqn_drive(vdev, enable);
+
+	ret = top_noc_qacceptn_check(vdev, enable ? 0x1 : 0x0);
+	if (ret) {
+		ivpu_err(vdev, "Failed TOP NOC QACCEPTN check: %d\n", ret);
+		return ret;
+	}
+
+	ret = top_noc_qdeny_check(vdev, 0x0);
+	if (ret)
+		ivpu_err(vdev, "Failed TOP NOC QDENY check: %d\n", ret);
+
+	return ret;
+}
+
+int ivpu_hw_ip_top_noc_enable(struct ivpu_device *vdev)
+{
+	return top_noc_drive(vdev, true);
+}
+
+static void dpu_active_drive_37xx(struct ivpu_device *vdev, bool enable)
+{
+	u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_DPU_ACTIVE);
+
+	if (enable)
+		val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_DPU_ACTIVE, DPU_ACTIVE, val);
+	else
+		val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_DPU_ACTIVE, DPU_ACTIVE, val);
+
+	REGV_WR32(VPU_37XX_HOST_SS_AON_DPU_ACTIVE, val);
+}
+
+static void pwr_island_delay_set(struct ivpu_device *vdev)
+{
+	bool high = vdev->hw->pll.profiling_freq == PLL_PROFILING_FREQ_HIGH;
+	u32 post, post1, post2, status;
+
+	if (ivpu_hw_ip_gen(vdev) < IVPU_HW_IP_50XX)
+		return;
+
+	switch (ivpu_device_id(vdev)) {
+	case PCI_DEVICE_ID_WCL:
+	case PCI_DEVICE_ID_PTL_P:
+		post = high ? 18 : 0;
+		post1 = 0;
+		post2 = 0;
+		status = high ? 46 : 3;
+		break;
+
+	case PCI_DEVICE_ID_NVL:
+		post = high ? 198 : 17;
+		post1 = 0;
+		post2 = high ? 198 : 17;
+		status = 0;
+		break;
+
+	default:
+		dump_stack();
+		ivpu_err(vdev, "Unknown device ID\n");
+		return;
+	}
+
+	pwr_island_delay_set_50xx(vdev, post, post1, post2, status);
+}
+
+int ivpu_hw_ip_pwr_domain_enable(struct ivpu_device *vdev)
+{
+	int ret;
+
+	pwr_island_delay_set(vdev);
+	pwr_island_enable(vdev);
+
+	ret = wait_for_pwr_island_status(vdev, 0x1);
+	if (ret) {
+		ivpu_err(vdev, "Timed out waiting for power island status\n");
+		return ret;
+	}
+
+	ret = top_noc_qreqn_check(vdev, 0x0);
+	if (ret) {
+		ivpu_err(vdev, "Failed TOP NOC QREQN check %d\n", ret);
+		return ret;
+	}
+
+	host_ss_clk_enable(vdev);
+	pwr_island_isolation_disable(vdev);
+	host_ss_rst_enable(vdev);
+
+	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
+		dpu_active_drive_37xx(vdev, true);
+
+	return ret;
+}
+
+u64 ivpu_hw_ip_read_perf_timer_counter(struct ivpu_device *vdev)
+{
+	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
+		return REGV_RD64(VPU_37XX_CPU_SS_TIM_PERF_FREE_CNT);
+	else
+		return REGV_RD64(VPU_40XX_CPU_SS_TIM_PERF_EXT_FREE_CNT);
+}
+
+static void ivpu_hw_ip_snoop_disable_37xx(struct ivpu_device *vdev)
+{
+	u32 val = REGV_RD32(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES);
+
+	val = REG_SET_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, NOSNOOP_OVERRIDE_EN, val);
+	val = REG_CLR_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, AW_NOSNOOP_OVERRIDE, val);
+
+	if (ivpu_is_force_snoop_enabled(vdev))
+		val = REG_CLR_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, AR_NOSNOOP_OVERRIDE, val);
+	else
+		val = REG_SET_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, AR_NOSNOOP_OVERRIDE, val);
+
+	REGV_WR32(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, val);
+}
+
+static void ivpu_hw_ip_snoop_disable_40xx(struct ivpu_device *vdev)
+{
+	u32 val = REGV_RD32(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES);
+
+	val = REG_SET_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, SNOOP_OVERRIDE_EN, val);
+	val = REG_SET_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, AW_SNOOP_OVERRIDE, val);
+
+	if (ivpu_is_force_snoop_enabled(vdev))
+		val = REG_SET_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, AR_SNOOP_OVERRIDE, val);
+	else
+		val = REG_CLR_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, AR_SNOOP_OVERRIDE, val);
+
+	REGV_WR32(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, val);
+}
+
+void ivpu_hw_ip_snoop_disable(struct ivpu_device *vdev)
+{
+	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
+		return ivpu_hw_ip_snoop_disable_37xx(vdev);
+	else
+		return ivpu_hw_ip_snoop_disable_40xx(vdev);
+}
+
+static void ivpu_hw_ip_tbu_mmu_enable_37xx(struct ivpu_device *vdev)
+{
+	u32 val = REGV_RD32(VPU_37XX_HOST_IF_TBU_MMUSSIDV);
+
+	val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU0_AWMMUSSIDV, val);
+	val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU0_ARMMUSSIDV, val);
+	val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU2_AWMMUSSIDV, val);
+	val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU2_ARMMUSSIDV, val);
+
+	REGV_WR32(VPU_37XX_HOST_IF_TBU_MMUSSIDV, val);
+}
+
+static void ivpu_hw_ip_tbu_mmu_enable_40xx(struct ivpu_device *vdev)
+{
+	u32 val = REGV_RD32(VPU_40XX_HOST_IF_TBU_MMUSSIDV);
+
+	val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU0_AWMMUSSIDV, val);
+	val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU0_ARMMUSSIDV, val);
+	val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU1_AWMMUSSIDV, val);
+	val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU1_ARMMUSSIDV, val);
+	val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU2_AWMMUSSIDV, val);
+	val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU2_ARMMUSSIDV, val);
+
+	REGV_WR32(VPU_40XX_HOST_IF_TBU_MMUSSIDV, val);
+}
+
+void ivpu_hw_ip_tbu_mmu_enable(struct ivpu_device *vdev)
+{
+	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
+		return ivpu_hw_ip_tbu_mmu_enable_37xx(vdev);
+	else
+		return ivpu_hw_ip_tbu_mmu_enable_40xx(vdev);
+}
+
+static int soc_cpu_boot_37xx(struct ivpu_device *vdev)
+{
+	u32 val;
+
+	val = REGV_RD32(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC);
+	val = REG_SET_FLD(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RSTRUN0, val);
+
+	val = REG_CLR_FLD(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RSTVEC, val);
+	REGV_WR32(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, val);
+
+	val = REG_SET_FLD(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RESUME0, val);
+	REGV_WR32(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, val);
+
+	val = REG_CLR_FLD(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RESUME0, val);
+	REGV_WR32(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, val);
+
+	val = vdev->fw->entry_point >> 9;
+	REGV_WR32(VPU_37XX_HOST_SS_LOADING_ADDRESS_LO, val);
+
+	val = REG_SET_FLD(VPU_37XX_HOST_SS_LOADING_ADDRESS_LO, DONE, val);
+	REGV_WR32(VPU_37XX_HOST_SS_LOADING_ADDRESS_LO, val);
+
+	ivpu_dbg(vdev, PM, "Booting firmware, mode: %s\n",
+		 vdev->fw->entry_point == vdev->fw->cold_boot_entry_point ? "cold boot" : "resume");
+
+	return 0;
+}
+
+static int cpu_noc_qacceptn_check_40xx(struct ivpu_device *vdev, u32 exp_val)
+{
+	u32 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QACCEPTN);
+
+	if (!REG_TEST_FLD_NUM(VPU_40XX_CPU_SS_CPR_NOC_QACCEPTN, TOP_MMIO, exp_val, val))
+		return -EIO;
+
+	return 0;
+}
+
+static int cpu_noc_qdeny_check_40xx(struct ivpu_device *vdev, u32 exp_val)
+{
+	u32 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QDENY);
+
+	if (!REG_TEST_FLD_NUM(VPU_40XX_CPU_SS_CPR_NOC_QDENY, TOP_MMIO, exp_val, val))
+		return -EIO;
+
+	return 0;
+}
+
+static void cpu_noc_top_mmio_drive_40xx(struct ivpu_device *vdev, bool enable)
+{
+	u32 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QREQN);
+
+	if (enable)
+		val = REG_SET_FLD(VPU_40XX_CPU_SS_CPR_NOC_QREQN, TOP_MMIO, val);
+	else
+		val = REG_CLR_FLD(VPU_40XX_CPU_SS_CPR_NOC_QREQN, TOP_MMIO, val);
+	REGV_WR32(VPU_40XX_CPU_SS_CPR_NOC_QREQN, val);
+}
+
+static int soc_cpu_drive_40xx(struct ivpu_device *vdev, bool enable)
+{
+	int ret;
+
+	cpu_noc_top_mmio_drive_40xx(vdev, enable);
+
+	ret = cpu_noc_qacceptn_check_40xx(vdev, enable ? 0x1 : 0x0);
+	if (ret) {
+		ivpu_err(vdev, "Failed qacceptn check: %d\n", ret);
+		return ret;
+	}
+
+	ret = cpu_noc_qdeny_check_40xx(vdev, 0x0);
+	if (ret)
+		ivpu_err(vdev, "Failed qdeny check: %d\n", ret);
+
+	return ret;
+}
+
+static int soc_cpu_enable(struct ivpu_device *vdev)
+{
+	if (ivpu_hw_ip_gen(vdev) >= IVPU_HW_IP_60XX)
+		return 0;
+
+	return soc_cpu_drive_40xx(vdev, true);
+}
+
+static int soc_cpu_boot_40xx(struct ivpu_device *vdev)
+{
+	int ret;
+	u32 val;
+	u64 val64;
+
+	ret = soc_cpu_enable(vdev);
+	if (ret) {
+		ivpu_err(vdev, "Failed to enable SOC CPU: %d\n", ret);
+		return ret;
+	}
+
+	val64 = vdev->fw->entry_point;
+	val64 <<= ffs(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO_IMAGE_LOCATION_MASK) - 1;
+	REGV_WR64(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO, val64);
+
+	val = REGV_RD32(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO);
+	val = REG_SET_FLD(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO, DONE, val);
+	REGV_WR32(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO, val);
+
+	ivpu_dbg(vdev, PM, "Booting firmware, mode: %s\n",
+		 ivpu_fw_is_cold_boot(vdev) ? "cold boot" : "resume");
+
+	return 0;
+}
+
+int ivpu_hw_ip_soc_cpu_boot(struct ivpu_device *vdev)
+{
+	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
+		return soc_cpu_boot_37xx(vdev);
+	else
+		return soc_cpu_boot_40xx(vdev);
+}
+
+static void wdt_disable_37xx(struct ivpu_device *vdev)
+{
+	u32 val;
+
+	/* Enable writing and set non-zero WDT value */
+	REGV_WR32(VPU_37XX_CPU_SS_TIM_SAFE, TIM_SAFE_ENABLE);
+	REGV_WR32(VPU_37XX_CPU_SS_TIM_WATCHDOG, TIM_WATCHDOG_RESET_VALUE);
+
+	/* Enable writing and disable watchdog timer */
+	REGV_WR32(VPU_37XX_CPU_SS_TIM_SAFE, TIM_SAFE_ENABLE);
+	REGV_WR32(VPU_37XX_CPU_SS_TIM_WDOG_EN, 0);
+
+	/* Now clear the timeout interrupt */
+	val = REGV_RD32(VPU_37XX_CPU_SS_TIM_GEN_CONFIG);
+	val = REG_CLR_FLD(VPU_37XX_CPU_SS_TIM_GEN_CONFIG, WDOG_TO_INT_CLR, val);
+	REGV_WR32(VPU_37XX_CPU_SS_TIM_GEN_CONFIG, val);
+}
+
+static void wdt_disable_40xx(struct ivpu_device *vdev)
+{
+	u32 val;
+
+	REGV_WR32(VPU_40XX_CPU_SS_TIM_SAFE, TIM_SAFE_ENABLE);
+	REGV_WR32(VPU_40XX_CPU_SS_TIM_WATCHDOG, TIM_WATCHDOG_RESET_VALUE);
+
+	REGV_WR32(VPU_40XX_CPU_SS_TIM_SAFE, TIM_SAFE_ENABLE);
+	REGV_WR32(VPU_40XX_CPU_SS_TIM_WDOG_EN, 0);
+
+	val = REGV_RD32(VPU_40XX_CPU_SS_TIM_GEN_CONFIG);
+	val = REG_CLR_FLD(VPU_40XX_CPU_SS_TIM_GEN_CONFIG, WDOG_TO_INT_CLR, val);
+	REGV_WR32(VPU_40XX_CPU_SS_TIM_GEN_CONFIG, val);
+}
+
+void ivpu_hw_ip_wdt_disable(struct ivpu_device *vdev)
+{
+	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
+		return wdt_disable_37xx(vdev);
+	else
+		return wdt_disable_40xx(vdev);
+}
+
+static u32 ipc_rx_count_get_37xx(struct ivpu_device *vdev)
+{
+	u32 count = readl(vdev->regv + VPU_37XX_HOST_SS_TIM_IPC_FIFO_STAT);
+
+	return REG_GET_FLD(VPU_37XX_HOST_SS_TIM_IPC_FIFO_STAT, FILL_LEVEL, count);
+}
+
+static u32 ipc_rx_count_get_40xx(struct ivpu_device *vdev)
+{
+	u32 count = readl(vdev->regv + VPU_40XX_HOST_SS_TIM_IPC_FIFO_STAT);
+
+	return REG_GET_FLD(VPU_40XX_HOST_SS_TIM_IPC_FIFO_STAT, FILL_LEVEL, count);
+}
+
+u32 ivpu_hw_ip_ipc_rx_count_get(struct ivpu_device *vdev)
+{
+	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
+		return ipc_rx_count_get_37xx(vdev);
+	else
+		return ipc_rx_count_get_40xx(vdev);
+}
+
+void ivpu_hw_ip_irq_enable(struct ivpu_device *vdev)
+{
+	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) {
+		REGV_WR32(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, ITF_FIREWALL_VIOLATION_MASK_37XX);
+		REGV_WR64(VPU_37XX_HOST_SS_ICB_ENABLE_0, ICB_0_1_IRQ_MASK_37XX);
+	} else {
+		REGV_WR32(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, ITF_FIREWALL_VIOLATION_MASK_40XX);
+		REGV_WR64(VPU_40XX_HOST_SS_ICB_ENABLE_0, ICB_0_1_IRQ_MASK_40XX);
+	}
+}
+
+void ivpu_hw_ip_irq_disable(struct ivpu_device *vdev)
+{
+	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) {
+		REGV_WR64(VPU_37XX_HOST_SS_ICB_ENABLE_0, 0x0ull);
+		REGV_WR32(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, 0x0);
+	} else {
+		REGV_WR64(VPU_40XX_HOST_SS_ICB_ENABLE_0, 0x0ull);
+		REGV_WR32(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, 0x0ul);
+	}
+}
+
+static void diagnose_failure_37xx(struct ivpu_device *vdev)
+{
+	u32 reg = REGV_RD32(VPU_37XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK_37XX;
+
+	if (ipc_rx_count_get_37xx(vdev))
+		ivpu_err(vdev, "IPC FIFO queue not empty, missed IPC IRQ");
+
+	if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT, reg))
+		ivpu_err(vdev, "WDT MSS timeout detected\n");
+
+	if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT, reg))
+		ivpu_err(vdev, "WDT NCE timeout detected\n");
+
+	if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT, reg))
+		ivpu_err(vdev, "NOC Firewall irq detected\n");
+}
+
+static void diagnose_failure_40xx(struct ivpu_device *vdev)
+{
+	u32 reg = REGV_RD32(VPU_40XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK_40XX;
+
+	if (ipc_rx_count_get_40xx(vdev))
+		ivpu_err(vdev, "IPC FIFO queue not empty, missed IPC IRQ");
+
+	if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT, reg))
+		ivpu_err(vdev, "WDT MSS timeout detected\n");
+
+	if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT, reg))
+		ivpu_err(vdev, "WDT NCE timeout detected\n");
+
+	if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT, reg))
+		ivpu_err(vdev, "NOC Firewall irq detected\n");
+}
+
+void ivpu_hw_ip_diagnose_failure(struct ivpu_device *vdev)
+{
+	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
+		diagnose_failure_37xx(vdev);
+	else
+		diagnose_failure_40xx(vdev);
+}
+
+void ivpu_hw_ip_irq_clear(struct ivpu_device *vdev)
+{
+	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
+		REGV_WR64(VPU_37XX_HOST_SS_ICB_CLEAR_0, ICB_0_1_IRQ_MASK_37XX);
+	else
+		REGV_WR64(VPU_40XX_HOST_SS_ICB_CLEAR_0, ICB_0_1_IRQ_MASK_40XX);
+}
+
+static void irq_wdt_nce_handler(struct ivpu_device *vdev)
+{
+	ivpu_pm_trigger_recovery(vdev, "WDT NCE IRQ");
+}
+
+static void irq_wdt_mss_handler(struct ivpu_device *vdev)
+{
+	ivpu_hw_ip_wdt_disable(vdev);
+	ivpu_pm_trigger_recovery(vdev, "WDT MSS IRQ");
+}
+
+static void irq_noc_firewall_handler(struct ivpu_device *vdev)
+{
+	atomic_inc(&vdev->hw->firewall_irq_counter);
+
+	ivpu_dbg(vdev, IRQ, "NOC Firewall interrupt detected, counter %d\n",
+		 atomic_read(&vdev->hw->firewall_irq_counter));
+}
+
+/* Handler for IRQs from NPU core */
+bool ivpu_hw_ip_irq_handler_37xx(struct ivpu_device *vdev, int irq)
+{
+	u32 status = REGV_RD32(VPU_37XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK_37XX;
+
+	if (!status)
+		return false;
+
+	REGV_WR32(VPU_37XX_HOST_SS_ICB_CLEAR_0, status);
+
+	if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_0_INT, status))
+		ivpu_mmu_irq_evtq_handler(vdev);
+
+	if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, HOST_IPC_FIFO_INT, status))
+		ivpu_ipc_irq_handler(vdev);
+
+	if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_1_INT, status))
+		ivpu_dbg(vdev, IRQ, "MMU sync complete\n");
+
+	if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_2_INT, status))
+		ivpu_mmu_irq_gerr_handler(vdev);
+
+	if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT, status))
+		irq_wdt_mss_handler(vdev);
+
+	if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT, status))
+		irq_wdt_nce_handler(vdev);
+
+	if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT, status))
+		irq_noc_firewall_handler(vdev);
+
+	return true;
+}
+
+/* Handler for IRQs from NPU core */
+bool ivpu_hw_ip_irq_handler_40xx(struct ivpu_device *vdev, int irq)
+{
+	u32 status = REGV_RD32(VPU_40XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK_40XX;
+
+	if (!status)
+		return false;
+
+	REGV_WR32(VPU_40XX_HOST_SS_ICB_CLEAR_0, status);
+
+	if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_0_INT, status))
+		ivpu_mmu_irq_evtq_handler(vdev);
+
+	if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, HOST_IPC_FIFO_INT, status))
+		ivpu_ipc_irq_handler(vdev);
+
+	if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_1_INT, status))
+		ivpu_dbg(vdev, IRQ, "MMU sync complete\n");
+
+	if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_2_INT, status))
+		ivpu_mmu_irq_gerr_handler(vdev);
+
+	if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT, status))
+		irq_wdt_mss_handler(vdev);
+
+	if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT, status))
+		irq_wdt_nce_handler(vdev);
+
+	if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT, status))
+		irq_noc_firewall_handler(vdev);
+
+	return true;
+}
+
+static void db_set_37xx(struct ivpu_device *vdev, u32 db_id)
+{
+	u32 reg_stride = VPU_37XX_CPU_SS_DOORBELL_1 - VPU_37XX_CPU_SS_DOORBELL_0;
+	u32 val = REG_FLD(VPU_37XX_CPU_SS_DOORBELL_0, SET);
+
+	REGV_WR32I(VPU_37XX_CPU_SS_DOORBELL_0, reg_stride, db_id, val);
+}
+
+static void db_set_40xx(struct ivpu_device *vdev, u32 db_id)
+{
+	u32 reg_stride = VPU_40XX_CPU_SS_DOORBELL_1 - VPU_40XX_CPU_SS_DOORBELL_0;
+	u32 val = REG_FLD(VPU_40XX_CPU_SS_DOORBELL_0, SET);
+
+	REGV_WR32I(VPU_40XX_CPU_SS_DOORBELL_0, reg_stride, db_id, val);
+}
+
+void ivpu_hw_ip_db_set(struct ivpu_device *vdev, u32 db_id)
+{
+	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
+		db_set_37xx(vdev, db_id);
+	else
+		db_set_40xx(vdev, db_id);
+}
+
+u32 ivpu_hw_ip_ipc_rx_addr_get(struct ivpu_device *vdev)
+{
+	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
+		return REGV_RD32(VPU_37XX_HOST_SS_TIM_IPC_FIFO_ATM);
+	else
+		return REGV_RD32(VPU_40XX_HOST_SS_TIM_IPC_FIFO_ATM);
+}
+
+void ivpu_hw_ip_ipc_tx_set(struct ivpu_device *vdev, u32 vpu_addr)
+{
+	if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX)
+		REGV_WR32(VPU_37XX_CPU_SS_TIM_IPC_FIFO, vpu_addr);
+	else
+		REGV_WR32(VPU_40XX_CPU_SS_TIM_IPC_FIFO, vpu_addr);
+}
diff --git a/drivers/accel/ivpu/ivpu_hw_ip.h b/drivers/accel/ivpu/ivpu_hw_ip.h
new file mode 100644
index 000000000000..5b1b391aa577
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_hw_ip.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2020-2024 Intel Corporation
+ */
+
+#ifndef __IVPU_HW_IP_H__
+#define __IVPU_HW_IP_H__
+
+#include "ivpu_drv.h"
+
+int ivpu_hw_ip_host_ss_configure(struct ivpu_device *vdev);
+void ivpu_hw_ip_idle_gen_enable(struct ivpu_device *vdev);
+void ivpu_hw_ip_idle_gen_disable(struct ivpu_device *vdev);
+int ivpu_hw_ip_pwr_domain_enable(struct ivpu_device *vdev);
+int ivpu_hw_ip_host_ss_axi_enable(struct ivpu_device *vdev);
+int ivpu_hw_ip_top_noc_enable(struct ivpu_device *vdev);
+u64 ivpu_hw_ip_read_perf_timer_counter(struct ivpu_device *vdev);
+void ivpu_hw_ip_snoop_disable(struct ivpu_device *vdev);
+void ivpu_hw_ip_tbu_mmu_enable(struct ivpu_device *vdev);
+int ivpu_hw_ip_soc_cpu_boot(struct ivpu_device *vdev);
+void ivpu_hw_ip_wdt_disable(struct ivpu_device *vdev);
+void ivpu_hw_ip_diagnose_failure(struct ivpu_device *vdev);
+u32 ivpu_hw_ip_ipc_rx_count_get(struct ivpu_device *vdev);
+void ivpu_hw_ip_irq_clear(struct ivpu_device *vdev);
+bool ivpu_hw_ip_irq_handler_37xx(struct ivpu_device *vdev, int irq);
+bool ivpu_hw_ip_irq_handler_40xx(struct ivpu_device *vdev, int irq);
+void ivpu_hw_ip_db_set(struct ivpu_device *vdev, u32 db_id);
+u32 ivpu_hw_ip_ipc_rx_addr_get(struct ivpu_device *vdev);
+void ivpu_hw_ip_ipc_tx_set(struct ivpu_device *vdev, u32 vpu_addr);
+void ivpu_hw_ip_irq_enable(struct ivpu_device *vdev);
+void ivpu_hw_ip_irq_disable(struct ivpu_device *vdev);
+void ivpu_hw_ip_diagnose_failure(struct ivpu_device *vdev);
+void ivpu_hw_ip_fabric_req_override_enable_50xx(struct ivpu_device *vdev);
+void ivpu_hw_ip_fabric_req_override_disable_50xx(struct ivpu_device *vdev);
+
+#endif /* __IVPU_HW_IP_H__ */
diff --git a/drivers/accel/ivpu/ivpu_hw_reg_io.h b/drivers/accel/ivpu/ivpu_hw_reg_io.h
new file mode 100644
index 000000000000..66259b0ead02
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_hw_reg_io.h
@@ -0,0 +1,133 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2020-2023 Intel Corporation
+ */
+
+#ifndef __IVPU_HW_REG_IO_H__
+#define __IVPU_HW_REG_IO_H__
+
+#include <linux/bitfield.h>
+#include <linux/fault-inject.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+
+#include "ivpu_drv.h"
+
+#define REG_POLL_SLEEP_US 50
+#define REG_IO_ERROR      0xffffffff
+
+#define REGB_RD32(reg)          ivpu_hw_reg_rd32(vdev, vdev->regb, (reg), #reg, __func__)
+#define REGB_RD64(reg)          ivpu_hw_reg_rd64(vdev, vdev->regb, (reg), #reg, __func__)
+#define REGB_WR32(reg, val)     ivpu_hw_reg_wr32(vdev, vdev->regb, (reg), (val), #reg, __func__)
+#define REGB_WR64(reg, val)     ivpu_hw_reg_wr64(vdev, vdev->regb, (reg), (val), #reg, __func__)
+
+#define REGV_RD32(reg)          ivpu_hw_reg_rd32(vdev, vdev->regv, (reg), #reg, __func__)
+#define REGV_RD64(reg)          ivpu_hw_reg_rd64(vdev, vdev->regv, (reg), #reg, __func__)
+#define REGV_WR32(reg, val)     ivpu_hw_reg_wr32(vdev, vdev->regv, (reg), (val), #reg, __func__)
+#define REGV_WR64(reg, val)     ivpu_hw_reg_wr64(vdev, vdev->regv, (reg), (val), #reg, __func__)
+
+#define REGV_WR32I(reg, stride, index, val) \
+	ivpu_hw_reg_wr32_index(vdev, vdev->regv, (reg), (stride), (index), (val), #reg, __func__)
+
+#define REG_FLD(REG, FLD) \
+	(REG##_##FLD##_MASK)
+#define REG_FLD_NUM(REG, FLD, num) \
+	FIELD_PREP(REG##_##FLD##_MASK, num)
+#define REG_GET_FLD(REG, FLD, val) \
+	FIELD_GET(REG##_##FLD##_MASK, val)
+#define REG_CLR_FLD(REG, FLD, val) \
+	((val) & ~(REG##_##FLD##_MASK))
+#define REG_SET_FLD(REG, FLD, val) \
+	((val) | (REG##_##FLD##_MASK))
+#define REG_SET_FLD_NUM(REG, FLD, num, val) \
+	(((val) & ~(REG##_##FLD##_MASK)) | FIELD_PREP(REG##_##FLD##_MASK, num))
+#define REG_TEST_FLD(REG, FLD, val) \
+	((REG##_##FLD##_MASK) == ((val) & (REG##_##FLD##_MASK)))
+#define REG_TEST_FLD_NUM(REG, FLD, num, val) \
+	((num) == FIELD_GET(REG##_##FLD##_MASK, val))
+
+#define REGB_POLL_FLD(reg, fld, exp_fld_val, timeout_us) \
+	ivpu_hw_reg_poll_fld(vdev, vdev->regb, reg, reg##_##fld##_MASK, \
+			     FIELD_PREP(reg##_##fld##_MASK, exp_fld_val), timeout_us, \
+			     __func__, #reg, #fld)
+
+#define REGV_POLL_FLD(reg, fld, exp_fld_val, timeout_us) \
+	ivpu_hw_reg_poll_fld(vdev, vdev->regv, reg, reg##_##fld##_MASK, \
+			     FIELD_PREP(reg##_##fld##_MASK, exp_fld_val), timeout_us, \
+			     __func__, #reg, #fld)
+
+extern struct fault_attr ivpu_hw_failure;
+
+static inline int __must_check
+ivpu_hw_reg_poll_fld(struct ivpu_device *vdev, void __iomem *base,
+		     u32 reg_offset, u32 reg_mask, u32 exp_masked_val, u32 timeout_us,
+		     const char *func_name, const char *reg_name, const char *fld_name)
+{
+	u32 reg_val;
+	int ret;
+
+	ivpu_dbg(vdev, REG, "%s : %s (0x%08x) POLL %s started (exp_val 0x%x)\n",
+		 func_name, reg_name, reg_offset, fld_name, exp_masked_val);
+
+	ret = read_poll_timeout(readl, reg_val, (reg_val & reg_mask) == exp_masked_val,
+				REG_POLL_SLEEP_US, timeout_us, false, base + reg_offset);
+
+#ifdef CONFIG_FAULT_INJECTION
+	if (should_fail(&ivpu_hw_failure, 1))
+		ret = -ETIMEDOUT;
+#endif
+
+	ivpu_dbg(vdev, REG, "%s : %s (0x%08x) POLL %s %s (reg_val 0x%08x)\n",
+		 func_name, reg_name, reg_offset, fld_name, ret ? "ETIMEDOUT" : "OK", reg_val);
+
+	return ret;
+}
+
+static inline u32
+ivpu_hw_reg_rd32(struct ivpu_device *vdev, void __iomem *base, u32 reg,
+		 const char *name, const char *func)
+{
+	u32 val = readl(base + reg);
+
+	ivpu_dbg(vdev, REG, "%s : %s (0x%08x) RD: 0x%08x\n", func, name, reg, val);
+	return val;
+}
+
+static inline u64
+ivpu_hw_reg_rd64(struct ivpu_device *vdev, void __iomem *base, u32 reg,
+		 const char *name, const char *func)
+{
+	u64 val = readq(base + reg);
+
+	ivpu_dbg(vdev, REG, "%s : %s (0x%08x) RD: 0x%016llx\n", func, name, reg, val);
+	return val;
+}
+
+static inline void
+ivpu_hw_reg_wr32(struct ivpu_device *vdev, void __iomem *base, u32 reg, u32 val,
+		 const char *name, const char *func)
+{
+	ivpu_dbg(vdev, REG, "%s : %s (0x%08x) WR: 0x%08x\n", func, name, reg, val);
+	writel(val, base + reg);
+}
+
+static inline void
+ivpu_hw_reg_wr64(struct ivpu_device *vdev, void __iomem *base, u32 reg, u64 val,
+		 const char *name, const char *func)
+{
+	ivpu_dbg(vdev, REG, "%s : %s (0x%08x) WR: 0x%016llx\n", func, name, reg, val);
+	writeq(val, base + reg);
+}
+
+static inline void
+ivpu_hw_reg_wr32_index(struct ivpu_device *vdev, void __iomem *base, u32 reg,
+		       u32 stride, u32 index, u32 val, const char *name,
+		       const char *func)
+{
+	reg += index * stride;
+
+	ivpu_dbg(vdev, REG, "%s WR: %s_%d (0x%08x) <= 0x%08x\n", func, name, index, reg, val);
+	writel(val, base + reg);
+}
+
+#endif /* __IVPU_HW_REG_IO_H__ */
diff --git a/drivers/accel/ivpu/ivpu_ipc.c b/drivers/accel/ivpu/ivpu_ipc.c
new file mode 100644
index 000000000000..1f13bf95b2b3
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_ipc.c
@@ -0,0 +1,593 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020-2024 Intel Corporation
+ */
+
+#include <linux/genalloc.h>
+#include <linux/highmem.h>
+#include <linux/pm_runtime.h>
+#include <linux/wait.h>
+
+#include "ivpu_drv.h"
+#include "ivpu_gem.h"
+#include "ivpu_hw.h"
+#include "ivpu_hw_reg_io.h"
+#include "ivpu_ipc.h"
+#include "ivpu_jsm_msg.h"
+#include "ivpu_pm.h"
+#include "ivpu_trace.h"
+
+#define IPC_MAX_RX_MSG	128
+
+struct ivpu_ipc_tx_buf {
+	struct ivpu_ipc_hdr ipc;
+	struct vpu_jsm_msg jsm;
+};
+
+static void ivpu_ipc_msg_dump(struct ivpu_device *vdev, char *c,
+			      struct ivpu_ipc_hdr *ipc_hdr, u32 vpu_addr)
+{
+	ivpu_dbg(vdev, IPC,
+		 "%s: vpu:0x%x (data_addr:0x%08x, data_size:0x%x, channel:0x%x, src_node:0x%x, dst_node:0x%x, status:0x%x)",
+		 c, vpu_addr, ipc_hdr->data_addr, ipc_hdr->data_size, ipc_hdr->channel,
+		 ipc_hdr->src_node, ipc_hdr->dst_node, ipc_hdr->status);
+}
+
+static void ivpu_jsm_msg_dump(struct ivpu_device *vdev, char *c,
+			      struct vpu_jsm_msg *jsm_msg, u32 vpu_addr)
+{
+	u32 *payload = (u32 *)&jsm_msg->payload;
+
+	ivpu_dbg(vdev, JSM,
+		 "%s: vpu:0x%08x (type:%s, status:0x%x, id: 0x%x, result: 0x%x, payload:0x%x 0x%x 0x%x 0x%x 0x%x)\n",
+		 c, vpu_addr, ivpu_jsm_msg_type_to_str(jsm_msg->type),
+		 jsm_msg->status, jsm_msg->request_id, jsm_msg->result,
+		 payload[0], payload[1], payload[2], payload[3], payload[4]);
+}
+
+static void
+ivpu_ipc_rx_mark_free(struct ivpu_device *vdev, struct ivpu_ipc_hdr *ipc_hdr,
+		      struct vpu_jsm_msg *jsm_msg)
+{
+	ipc_hdr->status = IVPU_IPC_HDR_FREE;
+	if (jsm_msg)
+		jsm_msg->status = VPU_JSM_MSG_FREE;
+	wmb(); /* Flush WC buffers for message statuses */
+}
+
+static void ivpu_ipc_mem_fini(struct ivpu_device *vdev)
+{
+	struct ivpu_ipc_info *ipc = vdev->ipc;
+
+	ivpu_bo_free(ipc->mem_rx);
+	ivpu_bo_free(ipc->mem_tx);
+}
+
+static int
+ivpu_ipc_tx_prepare(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons,
+		    struct vpu_jsm_msg *req)
+{
+	struct ivpu_ipc_info *ipc = vdev->ipc;
+	struct ivpu_ipc_tx_buf *tx_buf;
+	u32 tx_buf_vpu_addr;
+	u32 jsm_vpu_addr;
+
+	tx_buf_vpu_addr = gen_pool_alloc(ipc->mm_tx, sizeof(*tx_buf));
+	if (!tx_buf_vpu_addr) {
+		ivpu_err_ratelimited(vdev, "Failed to reserve IPC buffer, size %ld\n",
+				     sizeof(*tx_buf));
+		return -ENOMEM;
+	}
+
+	tx_buf = ivpu_to_cpu_addr(ipc->mem_tx, tx_buf_vpu_addr);
+	if (drm_WARN_ON(&vdev->drm, !tx_buf)) {
+		gen_pool_free(ipc->mm_tx, tx_buf_vpu_addr, sizeof(*tx_buf));
+		return -EIO;
+	}
+
+	jsm_vpu_addr = tx_buf_vpu_addr + offsetof(struct ivpu_ipc_tx_buf, jsm);
+
+	if (tx_buf->ipc.status != IVPU_IPC_HDR_FREE)
+		ivpu_warn_ratelimited(vdev, "IPC message vpu:0x%x not released by firmware\n",
+				      tx_buf_vpu_addr);
+
+	if (tx_buf->jsm.status != VPU_JSM_MSG_FREE)
+		ivpu_warn_ratelimited(vdev, "JSM message vpu:0x%x not released by firmware\n",
+				      jsm_vpu_addr);
+
+	memset(tx_buf, 0, sizeof(*tx_buf));
+	tx_buf->ipc.data_addr = jsm_vpu_addr;
+	/* TODO: Set data_size to actual JSM message size, not union of all messages */
+	tx_buf->ipc.data_size = sizeof(*req);
+	tx_buf->ipc.channel = cons->channel;
+	tx_buf->ipc.src_node = 0;
+	tx_buf->ipc.dst_node = 1;
+	tx_buf->ipc.status = IVPU_IPC_HDR_ALLOCATED;
+	tx_buf->jsm.type = req->type;
+	tx_buf->jsm.status = VPU_JSM_MSG_ALLOCATED;
+	tx_buf->jsm.payload = req->payload;
+
+	req->request_id = atomic_inc_return(&ipc->request_id);
+	tx_buf->jsm.request_id = req->request_id;
+	cons->request_id = req->request_id;
+	wmb(); /* Flush WC buffers for IPC, JSM msgs */
+
+	cons->tx_vpu_addr = tx_buf_vpu_addr;
+
+	ivpu_jsm_msg_dump(vdev, "TX", &tx_buf->jsm, jsm_vpu_addr);
+	ivpu_ipc_msg_dump(vdev, "TX", &tx_buf->ipc, tx_buf_vpu_addr);
+
+	return 0;
+}
+
+static void ivpu_ipc_tx_release(struct ivpu_device *vdev, u32 vpu_addr)
+{
+	struct ivpu_ipc_info *ipc = vdev->ipc;
+
+	if (vpu_addr)
+		gen_pool_free(ipc->mm_tx, vpu_addr, sizeof(struct ivpu_ipc_tx_buf));
+}
+
+static void ivpu_ipc_tx(struct ivpu_device *vdev, u32 vpu_addr)
+{
+	ivpu_hw_ipc_tx_set(vdev, vpu_addr);
+}
+
+static void
+ivpu_ipc_rx_msg_add(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons,
+		    struct ivpu_ipc_hdr *ipc_hdr, struct vpu_jsm_msg *jsm_msg)
+{
+	struct ivpu_ipc_info *ipc = vdev->ipc;
+	struct ivpu_ipc_rx_msg *rx_msg;
+
+	lockdep_assert_held(&ipc->cons_lock);
+
+	rx_msg = kzalloc(sizeof(*rx_msg), GFP_ATOMIC);
+	if (!rx_msg) {
+		ivpu_ipc_rx_mark_free(vdev, ipc_hdr, jsm_msg);
+		return;
+	}
+
+	atomic_inc(&ipc->rx_msg_count);
+
+	rx_msg->ipc_hdr = ipc_hdr;
+	rx_msg->jsm_msg = jsm_msg;
+	rx_msg->callback = cons->rx_callback;
+
+	if (rx_msg->callback) {
+		list_add_tail(&rx_msg->link, &ipc->cb_msg_list);
+	} else {
+		spin_lock(&cons->rx_lock);
+		list_add_tail(&rx_msg->link, &cons->rx_msg_list);
+		spin_unlock(&cons->rx_lock);
+		wake_up(&cons->rx_msg_wq);
+	}
+}
+
+static void
+ivpu_ipc_rx_msg_del(struct ivpu_device *vdev, struct ivpu_ipc_rx_msg *rx_msg)
+{
+	list_del(&rx_msg->link);
+	ivpu_ipc_rx_mark_free(vdev, rx_msg->ipc_hdr, rx_msg->jsm_msg);
+	atomic_dec(&vdev->ipc->rx_msg_count);
+	kfree(rx_msg);
+}
+
+void ivpu_ipc_consumer_add(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons,
+			   u32 channel, ivpu_ipc_rx_callback_t rx_callback)
+{
+	struct ivpu_ipc_info *ipc = vdev->ipc;
+
+	INIT_LIST_HEAD(&cons->link);
+	cons->channel = channel;
+	cons->tx_vpu_addr = 0;
+	cons->request_id = 0;
+	cons->aborted = false;
+	cons->rx_callback = rx_callback;
+	spin_lock_init(&cons->rx_lock);
+	INIT_LIST_HEAD(&cons->rx_msg_list);
+	init_waitqueue_head(&cons->rx_msg_wq);
+
+	spin_lock_irq(&ipc->cons_lock);
+	list_add_tail(&cons->link, &ipc->cons_list);
+	spin_unlock_irq(&ipc->cons_lock);
+}
+
+void ivpu_ipc_consumer_del(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons)
+{
+	struct ivpu_ipc_info *ipc = vdev->ipc;
+	struct ivpu_ipc_rx_msg *rx_msg, *r;
+
+	spin_lock_irq(&ipc->cons_lock);
+	list_del(&cons->link);
+	spin_unlock_irq(&ipc->cons_lock);
+
+	spin_lock_irq(&cons->rx_lock);
+	list_for_each_entry_safe(rx_msg, r, &cons->rx_msg_list, link)
+		ivpu_ipc_rx_msg_del(vdev, rx_msg);
+	spin_unlock_irq(&cons->rx_lock);
+
+	ivpu_ipc_tx_release(vdev, cons->tx_vpu_addr);
+}
+
+int ivpu_ipc_send(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons, struct vpu_jsm_msg *req)
+{
+	struct ivpu_ipc_info *ipc = vdev->ipc;
+	int ret;
+
+	mutex_lock(&ipc->lock);
+
+	if (!ipc->on) {
+		ret = -EAGAIN;
+		goto unlock;
+	}
+
+	ret = ivpu_ipc_tx_prepare(vdev, cons, req);
+	if (ret)
+		goto unlock;
+
+	ivpu_ipc_tx(vdev, cons->tx_vpu_addr);
+	trace_jsm("[tx]", req);
+
+unlock:
+	mutex_unlock(&ipc->lock);
+	return ret;
+}
+
+static bool ivpu_ipc_rx_need_wakeup(struct ivpu_ipc_consumer *cons)
+{
+	bool ret;
+
+	spin_lock_irq(&cons->rx_lock);
+	ret = !list_empty(&cons->rx_msg_list) || cons->aborted;
+	spin_unlock_irq(&cons->rx_lock);
+
+	return ret;
+}
+
+int ivpu_ipc_receive(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons,
+		     struct ivpu_ipc_hdr *ipc_buf,
+		     struct vpu_jsm_msg *jsm_msg, unsigned long timeout_ms)
+{
+	struct ivpu_ipc_rx_msg *rx_msg;
+	int wait_ret, ret = 0;
+
+	if (drm_WARN_ONCE(&vdev->drm, cons->rx_callback, "Consumer works only in async mode\n"))
+		return -EINVAL;
+
+	wait_ret = wait_event_timeout(cons->rx_msg_wq,
+				      ivpu_ipc_rx_need_wakeup(cons),
+				      msecs_to_jiffies(timeout_ms));
+
+	if (wait_ret == 0)
+		return -ETIMEDOUT;
+
+	spin_lock_irq(&cons->rx_lock);
+	if (cons->aborted) {
+		spin_unlock_irq(&cons->rx_lock);
+		return -ECANCELED;
+	}
+	rx_msg = list_first_entry_or_null(&cons->rx_msg_list, struct ivpu_ipc_rx_msg, link);
+	if (!rx_msg) {
+		spin_unlock_irq(&cons->rx_lock);
+		return -EAGAIN;
+	}
+
+	if (ipc_buf)
+		memcpy(ipc_buf, rx_msg->ipc_hdr, sizeof(*ipc_buf));
+	if (rx_msg->jsm_msg) {
+		u32 size = min_t(int, rx_msg->ipc_hdr->data_size, sizeof(*jsm_msg));
+
+		if (rx_msg->jsm_msg->result != VPU_JSM_STATUS_SUCCESS) {
+			ivpu_err(vdev, "IPC resp result error: %d\n", rx_msg->jsm_msg->result);
+			ret = -EBADMSG;
+		}
+
+		if (jsm_msg)
+			memcpy(jsm_msg, rx_msg->jsm_msg, size);
+		trace_jsm("[rx]", rx_msg->jsm_msg);
+	}
+
+	ivpu_ipc_rx_msg_del(vdev, rx_msg);
+	spin_unlock_irq(&cons->rx_lock);
+	return ret;
+}
+
+int
+ivpu_ipc_send_receive_internal(struct ivpu_device *vdev, struct vpu_jsm_msg *req,
+			       enum vpu_ipc_msg_type expected_resp_type,
+			       struct vpu_jsm_msg *resp, u32 channel, unsigned long timeout_ms)
+{
+	struct ivpu_ipc_consumer cons;
+	int ret;
+
+	drm_WARN_ON(&vdev->drm, pm_runtime_status_suspended(vdev->drm.dev) &&
+		    pm_runtime_enabled(vdev->drm.dev));
+
+	ivpu_ipc_consumer_add(vdev, &cons, channel, NULL);
+
+	ret = ivpu_ipc_send(vdev, &cons, req);
+	if (ret) {
+		ivpu_warn_ratelimited(vdev, "IPC send failed: %d\n", ret);
+		goto consumer_del;
+	}
+
+	ret = ivpu_ipc_receive(vdev, &cons, NULL, resp, timeout_ms);
+	if (ret) {
+		ivpu_warn_ratelimited(vdev, "IPC receive failed: type %s, ret %d\n",
+				      ivpu_jsm_msg_type_to_str(req->type), ret);
+		goto consumer_del;
+	}
+
+	if (resp->type != expected_resp_type) {
+		ivpu_warn_ratelimited(vdev, "Invalid JSM response type: 0x%x\n", resp->type);
+		ret = -EBADE;
+	}
+
+consumer_del:
+	ivpu_ipc_consumer_del(vdev, &cons);
+	return ret;
+}
+
+int ivpu_ipc_send_receive(struct ivpu_device *vdev, struct vpu_jsm_msg *req,
+			  enum vpu_ipc_msg_type expected_resp, struct vpu_jsm_msg *resp,
+			  u32 channel, unsigned long timeout_ms)
+{
+	struct vpu_jsm_msg hb_req = { .type = VPU_JSM_MSG_QUERY_ENGINE_HB };
+	struct vpu_jsm_msg hb_resp;
+	int ret, hb_ret;
+
+	ret = ivpu_rpm_get(vdev);
+	if (ret < 0)
+		return ret;
+
+	ret = ivpu_ipc_send_receive_internal(vdev, req, expected_resp, resp, channel, timeout_ms);
+	if (ret != -ETIMEDOUT)
+		goto rpm_put;
+
+	hb_ret = ivpu_ipc_send_receive_internal(vdev, &hb_req, VPU_JSM_MSG_QUERY_ENGINE_HB_DONE,
+						&hb_resp, VPU_IPC_CHAN_ASYNC_CMD,
+						vdev->timeout.jsm);
+	if (hb_ret == -ETIMEDOUT)
+		ivpu_pm_trigger_recovery(vdev, "IPC timeout");
+
+rpm_put:
+	ivpu_rpm_put(vdev);
+	return ret;
+}
+
+int ivpu_ipc_send_and_wait(struct ivpu_device *vdev, struct vpu_jsm_msg *req,
+			   u32 channel, unsigned long timeout_ms)
+{
+	struct ivpu_ipc_consumer cons;
+	int ret;
+
+	ret = ivpu_rpm_get(vdev);
+	if (ret < 0)
+		return ret;
+
+	ivpu_ipc_consumer_add(vdev, &cons, channel, NULL);
+
+	ret = ivpu_ipc_send(vdev, &cons, req);
+	if (ret) {
+		ivpu_warn_ratelimited(vdev, "IPC send failed: %d\n", ret);
+		goto consumer_del;
+	}
+
+	msleep(timeout_ms);
+
+consumer_del:
+	ivpu_ipc_consumer_del(vdev, &cons);
+	ivpu_rpm_put(vdev);
+	return ret;
+}
+
+static bool
+ivpu_ipc_match_consumer(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons,
+			struct ivpu_ipc_hdr *ipc_hdr, struct vpu_jsm_msg *jsm_msg)
+{
+	if (cons->channel != ipc_hdr->channel)
+		return false;
+
+	if (!jsm_msg || jsm_msg->request_id == cons->request_id)
+		return true;
+
+	return false;
+}
+
+void ivpu_ipc_irq_handler(struct ivpu_device *vdev)
+{
+	struct ivpu_ipc_info *ipc = vdev->ipc;
+	struct ivpu_ipc_consumer *cons;
+	struct ivpu_ipc_hdr *ipc_hdr;
+	struct vpu_jsm_msg *jsm_msg;
+	unsigned long flags;
+	bool dispatched;
+	u32 vpu_addr;
+
+	/*
+	 * Driver needs to purge all messages from IPC FIFO to clear IPC interrupt.
+	 * Without purge IPC FIFO to 0 next IPC interrupts won't be generated.
+	 */
+	while (ivpu_hw_ipc_rx_count_get(vdev)) {
+		vpu_addr = ivpu_hw_ipc_rx_addr_get(vdev);
+		if (vpu_addr == REG_IO_ERROR) {
+			ivpu_err_ratelimited(vdev, "Failed to read IPC rx addr register\n");
+			return;
+		}
+
+		ipc_hdr = ivpu_to_cpu_addr(ipc->mem_rx, vpu_addr);
+		if (!ipc_hdr) {
+			ivpu_warn_ratelimited(vdev, "IPC msg 0x%x out of range\n", vpu_addr);
+			continue;
+		}
+		ivpu_ipc_msg_dump(vdev, "RX", ipc_hdr, vpu_addr);
+
+		jsm_msg = NULL;
+		if (ipc_hdr->channel != IVPU_IPC_CHAN_BOOT_MSG) {
+			jsm_msg = ivpu_to_cpu_addr(ipc->mem_rx, ipc_hdr->data_addr);
+			if (!jsm_msg) {
+				ivpu_warn_ratelimited(vdev, "JSM msg 0x%x out of range\n",
+						      ipc_hdr->data_addr);
+				ivpu_ipc_rx_mark_free(vdev, ipc_hdr, NULL);
+				continue;
+			}
+			ivpu_jsm_msg_dump(vdev, "RX", jsm_msg, ipc_hdr->data_addr);
+		}
+
+		if (atomic_read(&ipc->rx_msg_count) > IPC_MAX_RX_MSG) {
+			ivpu_warn_ratelimited(vdev, "IPC RX msg dropped, msg count %d\n",
+					      IPC_MAX_RX_MSG);
+			ivpu_ipc_rx_mark_free(vdev, ipc_hdr, jsm_msg);
+			continue;
+		}
+
+		dispatched = false;
+		spin_lock_irqsave(&ipc->cons_lock, flags);
+		list_for_each_entry(cons, &ipc->cons_list, link) {
+			if (ivpu_ipc_match_consumer(vdev, cons, ipc_hdr, jsm_msg)) {
+				ivpu_ipc_rx_msg_add(vdev, cons, ipc_hdr, jsm_msg);
+				dispatched = true;
+				break;
+			}
+		}
+		spin_unlock_irqrestore(&ipc->cons_lock, flags);
+
+		if (!dispatched) {
+			ivpu_dbg(vdev, IPC, "IPC RX msg 0x%x dropped (no consumer)\n", vpu_addr);
+			ivpu_ipc_rx_mark_free(vdev, ipc_hdr, jsm_msg);
+		}
+	}
+
+	queue_work(system_percpu_wq, &vdev->irq_ipc_work);
+}
+
+void ivpu_ipc_irq_work_fn(struct work_struct *work)
+{
+	struct ivpu_device *vdev = container_of(work, struct ivpu_device, irq_ipc_work);
+	struct ivpu_ipc_info *ipc = vdev->ipc;
+	struct ivpu_ipc_rx_msg *rx_msg, *r;
+	struct list_head cb_msg_list;
+
+	INIT_LIST_HEAD(&cb_msg_list);
+
+	spin_lock_irq(&ipc->cons_lock);
+	list_splice_tail_init(&ipc->cb_msg_list, &cb_msg_list);
+	spin_unlock_irq(&ipc->cons_lock);
+
+	list_for_each_entry_safe(rx_msg, r, &cb_msg_list, link) {
+		rx_msg->callback(vdev, rx_msg->ipc_hdr, rx_msg->jsm_msg);
+		ivpu_ipc_rx_msg_del(vdev, rx_msg);
+	}
+}
+
+int ivpu_ipc_init(struct ivpu_device *vdev)
+{
+	struct ivpu_ipc_info *ipc = vdev->ipc;
+	int ret;
+
+	ipc->mem_tx = ivpu_bo_create_global(vdev, SZ_16K, DRM_IVPU_BO_WC | DRM_IVPU_BO_MAPPABLE);
+	if (!ipc->mem_tx) {
+		ivpu_err(vdev, "Failed to allocate mem_tx\n");
+		return -ENOMEM;
+	}
+
+	ipc->mem_rx = ivpu_bo_create_global(vdev, SZ_16K, DRM_IVPU_BO_WC | DRM_IVPU_BO_MAPPABLE);
+	if (!ipc->mem_rx) {
+		ivpu_err(vdev, "Failed to allocate mem_rx\n");
+		ret = -ENOMEM;
+		goto err_free_tx;
+	}
+
+	ipc->mm_tx = devm_gen_pool_create(vdev->drm.dev, __ffs(IVPU_IPC_ALIGNMENT),
+					  -1, "TX_IPC_JSM");
+	if (IS_ERR(ipc->mm_tx)) {
+		ret = PTR_ERR(ipc->mm_tx);
+		ivpu_err(vdev, "Failed to create gen pool, %pe\n", ipc->mm_tx);
+		goto err_free_rx;
+	}
+
+	ret = gen_pool_add(ipc->mm_tx, ipc->mem_tx->vpu_addr, ivpu_bo_size(ipc->mem_tx), -1);
+	if (ret) {
+		ivpu_err(vdev, "gen_pool_add failed, ret %d\n", ret);
+		goto err_free_rx;
+	}
+
+	spin_lock_init(&ipc->cons_lock);
+	INIT_LIST_HEAD(&ipc->cons_list);
+	INIT_LIST_HEAD(&ipc->cb_msg_list);
+	ret = drmm_mutex_init(&vdev->drm, &ipc->lock);
+	if (ret) {
+		ivpu_err(vdev, "Failed to initialize ipc->lock, ret %d\n", ret);
+		goto err_free_rx;
+	}
+	ivpu_ipc_reset(vdev);
+	return 0;
+
+err_free_rx:
+	ivpu_bo_free(ipc->mem_rx);
+err_free_tx:
+	ivpu_bo_free(ipc->mem_tx);
+	return ret;
+}
+
+void ivpu_ipc_fini(struct ivpu_device *vdev)
+{
+	struct ivpu_ipc_info *ipc = vdev->ipc;
+
+	drm_WARN_ON(&vdev->drm, !list_empty(&ipc->cons_list));
+	drm_WARN_ON(&vdev->drm, !list_empty(&ipc->cb_msg_list));
+	drm_WARN_ON(&vdev->drm, atomic_read(&ipc->rx_msg_count) > 0);
+
+	ivpu_ipc_mem_fini(vdev);
+}
+
+void ivpu_ipc_enable(struct ivpu_device *vdev)
+{
+	struct ivpu_ipc_info *ipc = vdev->ipc;
+
+	mutex_lock(&ipc->lock);
+	ipc->on = true;
+	mutex_unlock(&ipc->lock);
+}
+
+void ivpu_ipc_disable(struct ivpu_device *vdev)
+{
+	struct ivpu_ipc_info *ipc = vdev->ipc;
+	struct ivpu_ipc_consumer *cons, *c;
+	struct ivpu_ipc_rx_msg *rx_msg, *r;
+
+	drm_WARN_ON(&vdev->drm, !list_empty(&ipc->cb_msg_list));
+
+	mutex_lock(&ipc->lock);
+	ipc->on = false;
+	mutex_unlock(&ipc->lock);
+
+	spin_lock_irq(&ipc->cons_lock);
+	list_for_each_entry_safe(cons, c, &ipc->cons_list, link) {
+		spin_lock(&cons->rx_lock);
+		if (!cons->rx_callback)
+			cons->aborted = true;
+		list_for_each_entry_safe(rx_msg, r, &cons->rx_msg_list, link)
+			ivpu_ipc_rx_msg_del(vdev, rx_msg);
+		spin_unlock(&cons->rx_lock);
+		wake_up(&cons->rx_msg_wq);
+	}
+	spin_unlock_irq(&ipc->cons_lock);
+
+	drm_WARN_ON(&vdev->drm, atomic_read(&ipc->rx_msg_count) > 0);
+}
+
+void ivpu_ipc_reset(struct ivpu_device *vdev)
+{
+	struct ivpu_ipc_info *ipc = vdev->ipc;
+
+	mutex_lock(&ipc->lock);
+	drm_WARN_ON(&vdev->drm, ipc->on);
+
+	memset(ivpu_bo_vaddr(ipc->mem_tx), 0, ivpu_bo_size(ipc->mem_tx));
+	memset(ivpu_bo_vaddr(ipc->mem_rx), 0, ivpu_bo_size(ipc->mem_rx));
+	wmb(); /* Flush WC buffers for TX and RX rings */
+
+	mutex_unlock(&ipc->lock);
+}
diff --git a/drivers/accel/ivpu/ivpu_ipc.h b/drivers/accel/ivpu/ivpu_ipc.h
new file mode 100644
index 000000000000..b524a1985b9d
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_ipc.h
@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2020-2024 Intel Corporation
+ */
+
+#ifndef __IVPU_IPC_H__
+#define __IVPU_IPC_H__
+
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+
+#include "vpu_jsm_api.h"
+
+struct ivpu_bo;
+
+/* VPU FW boot notification */
+#define IVPU_IPC_CHAN_BOOT_MSG		0x3ff
+#define IVPU_IPC_BOOT_MSG_DATA_ADDR	0x424f4f54
+
+/* The alignment to be used for IPC Buffers and IPC Data. */
+#define IVPU_IPC_ALIGNMENT	   64
+
+#define IVPU_IPC_HDR_FREE	   0
+#define IVPU_IPC_HDR_ALLOCATED	   1
+
+/**
+ * struct ivpu_ipc_hdr - The IPC message header structure, exchanged
+ * with the VPU device firmware.
+ * @data_addr: The VPU address of the payload (JSM message)
+ * @data_size: The size of the payload.
+ * @channel: The channel used.
+ * @src_node: The Node ID of the sender.
+ * @dst_node: The Node ID of the intended receiver.
+ * @status: IPC buffer usage status
+ */
+struct ivpu_ipc_hdr {
+	u32 data_addr;
+	u32 data_size;
+	u16 channel;
+	u8 src_node;
+	u8 dst_node;
+	u8 status;
+} __packed __aligned(IVPU_IPC_ALIGNMENT);
+
+typedef void (*ivpu_ipc_rx_callback_t)(struct ivpu_device *vdev,
+				       struct ivpu_ipc_hdr *ipc_hdr,
+				       struct vpu_jsm_msg *jsm_msg);
+
+struct ivpu_ipc_rx_msg {
+	struct list_head link;
+	struct ivpu_ipc_hdr *ipc_hdr;
+	struct vpu_jsm_msg *jsm_msg;
+	ivpu_ipc_rx_callback_t callback;
+};
+
+struct ivpu_ipc_consumer {
+	struct list_head link;
+	u32 channel;
+	u32 tx_vpu_addr;
+	u32 request_id;
+	bool aborted;
+	ivpu_ipc_rx_callback_t rx_callback;
+
+	spinlock_t rx_lock; /* Protects rx_msg_list and aborted */
+	struct list_head rx_msg_list;
+	wait_queue_head_t rx_msg_wq;
+};
+
+struct ivpu_ipc_info {
+	struct gen_pool *mm_tx;
+	struct ivpu_bo *mem_tx;
+	struct ivpu_bo *mem_rx;
+
+	atomic_t rx_msg_count;
+
+	spinlock_t cons_lock; /* Protects cons_list and cb_msg_list */
+	struct list_head cons_list;
+	struct list_head cb_msg_list;
+
+	atomic_t request_id;
+	struct mutex lock; /* Lock on status */
+	bool on;
+};
+
+int ivpu_ipc_init(struct ivpu_device *vdev);
+void ivpu_ipc_fini(struct ivpu_device *vdev);
+
+void ivpu_ipc_enable(struct ivpu_device *vdev);
+void ivpu_ipc_disable(struct ivpu_device *vdev);
+void ivpu_ipc_reset(struct ivpu_device *vdev);
+
+void ivpu_ipc_irq_handler(struct ivpu_device *vdev);
+void ivpu_ipc_irq_work_fn(struct work_struct *work);
+
+void ivpu_ipc_consumer_add(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons,
+			   u32 channel, ivpu_ipc_rx_callback_t callback);
+void ivpu_ipc_consumer_del(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons);
+
+int ivpu_ipc_send(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons,
+		  struct vpu_jsm_msg *req);
+int ivpu_ipc_receive(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons,
+		     struct ivpu_ipc_hdr *ipc_buf, struct vpu_jsm_msg *jsm_msg,
+		     unsigned long timeout_ms);
+int ivpu_ipc_send_receive_internal(struct ivpu_device *vdev, struct vpu_jsm_msg *req,
+				   enum vpu_ipc_msg_type expected_resp_type,
+				   struct vpu_jsm_msg *resp, u32 channel, unsigned long timeout_ms);
+int ivpu_ipc_send_receive(struct ivpu_device *vdev, struct vpu_jsm_msg *req,
+			  enum vpu_ipc_msg_type expected_resp, struct vpu_jsm_msg *resp,
+			  u32 channel, unsigned long timeout_ms);
+int ivpu_ipc_send_and_wait(struct ivpu_device *vdev, struct vpu_jsm_msg *req,
+			   u32 channel, unsigned long timeout_ms);
+
+#endif /* __IVPU_IPC_H__ */
diff --git a/drivers/accel/ivpu/ivpu_job.c b/drivers/accel/ivpu/ivpu_job.c
new file mode 100644
index 000000000000..4f8564e2878a
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_job.c
@@ -0,0 +1,1153 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020-2025 Intel Corporation
+ */
+
+#include <drm/drm_file.h>
+
+#include <linux/bitfield.h>
+#include <linux/highmem.h>
+#include <linux/pci.h>
+#include <linux/pm_runtime.h>
+#include <linux/module.h>
+#include <uapi/drm/ivpu_accel.h>
+
+#include "ivpu_drv.h"
+#include "ivpu_fw.h"
+#include "ivpu_hw.h"
+#include "ivpu_ipc.h"
+#include "ivpu_job.h"
+#include "ivpu_jsm_msg.h"
+#include "ivpu_mmu.h"
+#include "ivpu_pm.h"
+#include "ivpu_trace.h"
+#include "vpu_boot_api.h"
+
+#define CMD_BUF_IDX	     0
+#define JOB_MAX_BUFFER_COUNT 65535
+
+static void ivpu_cmdq_ring_db(struct ivpu_device *vdev, struct ivpu_cmdq *cmdq)
+{
+	ivpu_hw_db_set(vdev, cmdq->db_id);
+}
+
+static int ivpu_preemption_buffers_create(struct ivpu_device *vdev,
+					  struct ivpu_file_priv *file_priv, struct ivpu_cmdq *cmdq)
+{
+	if (ivpu_fw_preempt_buf_size(vdev) == 0)
+		return 0;
+
+	cmdq->primary_preempt_buf = ivpu_bo_create(vdev, &file_priv->ctx, &vdev->hw->ranges.user,
+						   vdev->fw->primary_preempt_buf_size,
+						   DRM_IVPU_BO_WC);
+	if (!cmdq->primary_preempt_buf) {
+		ivpu_err(vdev, "Failed to create primary preemption buffer\n");
+		return -ENOMEM;
+	}
+
+	cmdq->secondary_preempt_buf = ivpu_bo_create(vdev, &file_priv->ctx, &vdev->hw->ranges.dma,
+						     vdev->fw->secondary_preempt_buf_size,
+						     DRM_IVPU_BO_WC);
+	if (!cmdq->secondary_preempt_buf) {
+		ivpu_err(vdev, "Failed to create secondary preemption buffer\n");
+		goto err_free_primary;
+	}
+
+	return 0;
+
+err_free_primary:
+	ivpu_bo_free(cmdq->primary_preempt_buf);
+	cmdq->primary_preempt_buf = NULL;
+	return -ENOMEM;
+}
+
+static void ivpu_preemption_buffers_free(struct ivpu_device *vdev,
+					 struct ivpu_file_priv *file_priv, struct ivpu_cmdq *cmdq)
+{
+	if (cmdq->primary_preempt_buf)
+		ivpu_bo_free(cmdq->primary_preempt_buf);
+	if (cmdq->secondary_preempt_buf)
+		ivpu_bo_free(cmdq->secondary_preempt_buf);
+}
+
+static int ivpu_preemption_job_init(struct ivpu_device *vdev, struct ivpu_file_priv *file_priv,
+				    struct ivpu_cmdq *cmdq, struct ivpu_job *job)
+{
+	int ret;
+
+	/* Use preemption buffer provided by the user space */
+	if (job->primary_preempt_buf)
+		return 0;
+
+	if (!cmdq->primary_preempt_buf) {
+		/* Allocate per command queue preemption buffers */
+		ret = ivpu_preemption_buffers_create(vdev, file_priv, cmdq);
+		if (ret)
+			return ret;
+	}
+
+	/* Use preemption buffers allocated by the kernel */
+	job->primary_preempt_buf = cmdq->primary_preempt_buf;
+	job->secondary_preempt_buf = cmdq->secondary_preempt_buf;
+
+	return 0;
+}
+
+static struct ivpu_cmdq *ivpu_cmdq_alloc(struct ivpu_file_priv *file_priv)
+{
+	struct ivpu_device *vdev = file_priv->vdev;
+	struct ivpu_cmdq *cmdq;
+
+	cmdq = kzalloc(sizeof(*cmdq), GFP_KERNEL);
+	if (!cmdq)
+		return NULL;
+
+	cmdq->mem = ivpu_bo_create_global(vdev, SZ_4K, DRM_IVPU_BO_WC | DRM_IVPU_BO_MAPPABLE);
+	if (!cmdq->mem)
+		goto err_free_cmdq;
+
+	return cmdq;
+
+err_free_cmdq:
+	kfree(cmdq);
+	return NULL;
+}
+
+/**
+ * ivpu_cmdq_get_entry_count - Calculate the number of entries in the command queue.
+ * @cmdq: Pointer to the command queue structure.
+ *
+ * Returns the number of entries that can fit in the command queue memory.
+ */
+static inline u32 ivpu_cmdq_get_entry_count(struct ivpu_cmdq *cmdq)
+{
+	size_t size = ivpu_bo_size(cmdq->mem) - sizeof(struct vpu_job_queue_header);
+
+	return size / sizeof(struct vpu_job_queue_entry);
+}
+
+/**
+ * ivpu_cmdq_get_flags - Get command queue flags based on input flags and test mode.
+ * @vdev: Pointer to the ivpu device structure.
+ * @flags: Input flags to determine the command queue flags.
+ *
+ * Returns the calculated command queue flags, considering both the input flags
+ * and the current test mode settings.
+ */
+static u32 ivpu_cmdq_get_flags(struct ivpu_device *vdev, u32 flags)
+{
+	u32 cmdq_flags = 0;
+
+	if ((flags & DRM_IVPU_CMDQ_FLAG_TURBO) && (ivpu_hw_ip_gen(vdev) >= IVPU_HW_IP_40XX))
+		cmdq_flags |= VPU_JOB_QUEUE_FLAGS_TURBO_MODE;
+
+	/* Test mode can override the TURBO flag coming from the application */
+	if (ivpu_test_mode & IVPU_TEST_MODE_TURBO_ENABLE)
+		cmdq_flags |= VPU_JOB_QUEUE_FLAGS_TURBO_MODE;
+	if (ivpu_test_mode & IVPU_TEST_MODE_TURBO_DISABLE)
+		cmdq_flags &= ~VPU_JOB_QUEUE_FLAGS_TURBO_MODE;
+
+	return cmdq_flags;
+}
+
+static void ivpu_cmdq_free(struct ivpu_file_priv *file_priv, struct ivpu_cmdq *cmdq)
+{
+	ivpu_preemption_buffers_free(file_priv->vdev, file_priv, cmdq);
+	ivpu_bo_free(cmdq->mem);
+	kfree(cmdq);
+}
+
+static struct ivpu_cmdq *ivpu_cmdq_create(struct ivpu_file_priv *file_priv, u8 priority, u32 flags)
+{
+	struct ivpu_device *vdev = file_priv->vdev;
+	struct ivpu_cmdq *cmdq = NULL;
+	int ret;
+
+	lockdep_assert_held(&file_priv->lock);
+
+	cmdq = ivpu_cmdq_alloc(file_priv);
+	if (!cmdq) {
+		ivpu_err(vdev, "Failed to allocate command queue\n");
+		return NULL;
+	}
+	ret = xa_alloc_cyclic(&file_priv->cmdq_xa, &cmdq->id, cmdq, file_priv->cmdq_limit,
+			      &file_priv->cmdq_id_next, GFP_KERNEL);
+	if (ret < 0) {
+		ivpu_err(vdev, "Failed to allocate command queue ID: %d\n", ret);
+		goto err_free_cmdq;
+	}
+
+	cmdq->entry_count = ivpu_cmdq_get_entry_count(cmdq);
+	cmdq->priority = priority;
+
+	cmdq->jobq = (struct vpu_job_queue *)ivpu_bo_vaddr(cmdq->mem);
+	cmdq->jobq->header.engine_idx = VPU_ENGINE_COMPUTE;
+	cmdq->jobq->header.flags = ivpu_cmdq_get_flags(vdev, flags);
+
+	ivpu_dbg(vdev, JOB, "Command queue %d created, ctx %d, flags 0x%08x\n",
+		 cmdq->id, file_priv->ctx.id, cmdq->jobq->header.flags);
+	return cmdq;
+
+err_free_cmdq:
+	ivpu_cmdq_free(file_priv, cmdq);
+	return NULL;
+}
+
+static int ivpu_hws_cmdq_init(struct ivpu_file_priv *file_priv, struct ivpu_cmdq *cmdq, u16 engine,
+			      u8 priority)
+{
+	struct ivpu_device *vdev = file_priv->vdev;
+	int ret;
+
+	ret = ivpu_jsm_hws_create_cmdq(vdev, file_priv->ctx.id, file_priv->ctx.id, cmdq->id,
+				       task_pid_nr(current), engine,
+				       cmdq->mem->vpu_addr, ivpu_bo_size(cmdq->mem));
+	if (ret)
+		return ret;
+
+	ret = ivpu_jsm_hws_set_context_sched_properties(vdev, file_priv->ctx.id, cmdq->id,
+							priority);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int ivpu_register_db(struct ivpu_file_priv *file_priv, struct ivpu_cmdq *cmdq)
+{
+	struct ivpu_device *vdev = file_priv->vdev;
+	int ret;
+
+	ret = xa_alloc_cyclic(&vdev->db_xa, &cmdq->db_id, NULL, vdev->db_limit, &vdev->db_next,
+			      GFP_KERNEL);
+	if (ret < 0) {
+		ivpu_err(vdev, "Failed to allocate doorbell ID: %d\n", ret);
+		return ret;
+	}
+
+	if (vdev->fw->sched_mode == VPU_SCHEDULING_MODE_HW)
+		ret = ivpu_jsm_hws_register_db(vdev, file_priv->ctx.id, cmdq->id, cmdq->db_id,
+					       cmdq->mem->vpu_addr, ivpu_bo_size(cmdq->mem));
+	else
+		ret = ivpu_jsm_register_db(vdev, file_priv->ctx.id, cmdq->db_id,
+					   cmdq->mem->vpu_addr, ivpu_bo_size(cmdq->mem));
+
+	if (!ret) {
+		ivpu_dbg(vdev, JOB, "DB %d registered to cmdq %d ctx %d priority %d\n",
+			 cmdq->db_id, cmdq->id, file_priv->ctx.id, cmdq->priority);
+	} else {
+		xa_erase(&vdev->db_xa, cmdq->db_id);
+		cmdq->db_id = 0;
+	}
+
+	return ret;
+}
+
+static void ivpu_cmdq_jobq_reset(struct ivpu_device *vdev, struct vpu_job_queue *jobq)
+{
+	jobq->header.head = 0;
+	jobq->header.tail = 0;
+
+	wmb(); /* Flush WC buffer for jobq->header */
+}
+
+static int ivpu_cmdq_register(struct ivpu_file_priv *file_priv, struct ivpu_cmdq *cmdq)
+{
+	struct ivpu_device *vdev = file_priv->vdev;
+	int ret;
+
+	lockdep_assert_held(&file_priv->lock);
+
+	if (cmdq->db_id)
+		return 0;
+
+	ivpu_cmdq_jobq_reset(vdev, cmdq->jobq);
+
+	if (vdev->fw->sched_mode == VPU_SCHEDULING_MODE_HW) {
+		ret = ivpu_hws_cmdq_init(file_priv, cmdq, VPU_ENGINE_COMPUTE, cmdq->priority);
+		if (ret)
+			return ret;
+	}
+
+	ret = ivpu_register_db(file_priv, cmdq);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int ivpu_cmdq_unregister(struct ivpu_file_priv *file_priv, struct ivpu_cmdq *cmdq)
+{
+	struct ivpu_device *vdev = file_priv->vdev;
+	int ret;
+
+	lockdep_assert_held(&file_priv->lock);
+
+	if (!cmdq->db_id)
+		return 0;
+
+	ret = ivpu_jsm_unregister_db(vdev, cmdq->db_id);
+	if (!ret)
+		ivpu_dbg(vdev, JOB, "DB %d unregistered\n", cmdq->db_id);
+
+	if (vdev->fw->sched_mode == VPU_SCHEDULING_MODE_HW) {
+		ret = ivpu_jsm_hws_destroy_cmdq(vdev, file_priv->ctx.id, cmdq->id);
+		if (!ret)
+			ivpu_dbg(vdev, JOB, "Command queue %d destroyed, ctx %d\n",
+				 cmdq->id, file_priv->ctx.id);
+	}
+
+	xa_erase(&file_priv->vdev->db_xa, cmdq->db_id);
+	cmdq->db_id = 0;
+
+	return 0;
+}
+
+static inline u8 ivpu_job_to_jsm_priority(u8 priority)
+{
+	if (priority == DRM_IVPU_JOB_PRIORITY_DEFAULT)
+		return VPU_JOB_SCHEDULING_PRIORITY_BAND_NORMAL;
+
+	return priority - 1;
+}
+
+static void ivpu_cmdq_destroy(struct ivpu_file_priv *file_priv, struct ivpu_cmdq *cmdq)
+{
+	ivpu_cmdq_unregister(file_priv, cmdq);
+	xa_erase(&file_priv->cmdq_xa, cmdq->id);
+	ivpu_cmdq_free(file_priv, cmdq);
+}
+
+static struct ivpu_cmdq *ivpu_cmdq_acquire_legacy(struct ivpu_file_priv *file_priv, u8 priority)
+{
+	struct ivpu_cmdq *cmdq;
+	unsigned long id;
+
+	lockdep_assert_held(&file_priv->lock);
+
+	xa_for_each(&file_priv->cmdq_xa, id, cmdq)
+		if (cmdq->is_legacy && cmdq->priority == priority)
+			break;
+
+	if (!cmdq) {
+		cmdq = ivpu_cmdq_create(file_priv, priority, 0);
+		if (!cmdq)
+			return NULL;
+		cmdq->is_legacy = true;
+	}
+
+	return cmdq;
+}
+
+static struct ivpu_cmdq *ivpu_cmdq_acquire(struct ivpu_file_priv *file_priv, u32 cmdq_id)
+{
+	struct ivpu_device *vdev = file_priv->vdev;
+	struct ivpu_cmdq *cmdq;
+
+	lockdep_assert_held(&file_priv->lock);
+
+	cmdq = xa_load(&file_priv->cmdq_xa, cmdq_id);
+	if (!cmdq) {
+		ivpu_dbg(vdev, IOCTL, "Failed to find command queue with ID: %u\n", cmdq_id);
+		return NULL;
+	}
+
+	return cmdq;
+}
+
+void ivpu_cmdq_release_all_locked(struct ivpu_file_priv *file_priv)
+{
+	struct ivpu_cmdq *cmdq;
+	unsigned long cmdq_id;
+
+	lockdep_assert_held(&file_priv->lock);
+
+	xa_for_each(&file_priv->cmdq_xa, cmdq_id, cmdq)
+		ivpu_cmdq_destroy(file_priv, cmdq);
+}
+
+/*
+ * Mark the doorbell as unregistered
+ * This function needs to be called when the VPU hardware is restarted
+ * and FW loses job queue state. The next time job queue is used it
+ * will be registered again.
+ */
+static void ivpu_cmdq_reset(struct ivpu_file_priv *file_priv)
+{
+	struct ivpu_cmdq *cmdq;
+	unsigned long cmdq_id;
+
+	mutex_lock(&file_priv->lock);
+
+	xa_for_each(&file_priv->cmdq_xa, cmdq_id, cmdq) {
+		xa_erase(&file_priv->vdev->db_xa, cmdq->db_id);
+		cmdq->db_id = 0;
+	}
+
+	mutex_unlock(&file_priv->lock);
+}
+
+void ivpu_cmdq_reset_all_contexts(struct ivpu_device *vdev)
+{
+	struct ivpu_file_priv *file_priv;
+	unsigned long ctx_id;
+
+	mutex_lock(&vdev->context_list_lock);
+
+	xa_for_each(&vdev->context_xa, ctx_id, file_priv)
+		ivpu_cmdq_reset(file_priv);
+
+	mutex_unlock(&vdev->context_list_lock);
+}
+
+void ivpu_context_abort_locked(struct ivpu_file_priv *file_priv)
+{
+	struct ivpu_device *vdev = file_priv->vdev;
+	struct ivpu_cmdq *cmdq;
+	unsigned long cmdq_id;
+
+	lockdep_assert_held(&file_priv->lock);
+	ivpu_dbg(vdev, JOB, "Context ID: %u abort\n", file_priv->ctx.id);
+
+	xa_for_each(&file_priv->cmdq_xa, cmdq_id, cmdq)
+		ivpu_cmdq_unregister(file_priv, cmdq);
+
+	if (vdev->fw->sched_mode == VPU_SCHEDULING_MODE_OS)
+		ivpu_jsm_context_release(vdev, file_priv->ctx.id);
+
+	ivpu_mmu_disable_ssid_events(vdev, file_priv->ctx.id);
+
+	file_priv->aborted = true;
+}
+
+static int ivpu_cmdq_push_job(struct ivpu_cmdq *cmdq, struct ivpu_job *job)
+{
+	struct ivpu_device *vdev = job->vdev;
+	struct vpu_job_queue_header *header = &cmdq->jobq->header;
+	struct vpu_job_queue_entry *entry;
+	u32 tail = READ_ONCE(header->tail);
+	u32 next_entry = (tail + 1) % cmdq->entry_count;
+
+	/* Check if there is space left in job queue */
+	if (next_entry == header->head) {
+		ivpu_dbg(vdev, JOB, "Job queue full: ctx %d cmdq %d db %d head %d tail %d\n",
+			 job->file_priv->ctx.id, cmdq->id, cmdq->db_id, header->head, tail);
+		return -EBUSY;
+	}
+
+	entry = &cmdq->jobq->slot[tail].job;
+	entry->batch_buf_addr = job->cmd_buf_vpu_addr;
+	entry->job_id = job->job_id;
+	entry->flags = 0;
+	if (unlikely(ivpu_test_mode & IVPU_TEST_MODE_NULL_SUBMISSION))
+		entry->flags = VPU_JOB_FLAGS_NULL_SUBMISSION_MASK;
+
+	if (job->primary_preempt_buf) {
+		entry->primary_preempt_buf_addr = job->primary_preempt_buf->vpu_addr;
+		entry->primary_preempt_buf_size = ivpu_bo_size(job->primary_preempt_buf);
+	}
+
+	if (job->secondary_preempt_buf) {
+		entry->secondary_preempt_buf_addr = job->secondary_preempt_buf->vpu_addr;
+		entry->secondary_preempt_buf_size = ivpu_bo_size(job->secondary_preempt_buf);
+	}
+
+	wmb(); /* Ensure that tail is updated after filling entry */
+	header->tail = next_entry;
+	wmb(); /* Flush WC buffer for jobq header */
+
+	return 0;
+}
+
+struct ivpu_fence {
+	struct dma_fence base;
+	spinlock_t lock; /* protects base */
+	struct ivpu_device *vdev;
+};
+
+static inline struct ivpu_fence *to_vpu_fence(struct dma_fence *fence)
+{
+	return container_of(fence, struct ivpu_fence, base);
+}
+
+static const char *ivpu_fence_get_driver_name(struct dma_fence *fence)
+{
+	return DRIVER_NAME;
+}
+
+static const char *ivpu_fence_get_timeline_name(struct dma_fence *fence)
+{
+	struct ivpu_fence *ivpu_fence = to_vpu_fence(fence);
+
+	return dev_name(ivpu_fence->vdev->drm.dev);
+}
+
+static const struct dma_fence_ops ivpu_fence_ops = {
+	.get_driver_name = ivpu_fence_get_driver_name,
+	.get_timeline_name = ivpu_fence_get_timeline_name,
+};
+
+static struct dma_fence *ivpu_fence_create(struct ivpu_device *vdev)
+{
+	struct ivpu_fence *fence;
+
+	fence = kzalloc(sizeof(*fence), GFP_KERNEL);
+	if (!fence)
+		return NULL;
+
+	fence->vdev = vdev;
+	spin_lock_init(&fence->lock);
+	dma_fence_init(&fence->base, &ivpu_fence_ops, &fence->lock, dma_fence_context_alloc(1), 1);
+
+	return &fence->base;
+}
+
+static void ivpu_job_destroy(struct ivpu_job *job)
+{
+	struct ivpu_device *vdev = job->vdev;
+	u32 i;
+
+	ivpu_dbg(vdev, JOB, "Job destroyed: id %3u ctx %2d cmdq_id %u engine %d",
+		 job->job_id, job->file_priv->ctx.id, job->cmdq_id, job->engine_idx);
+
+	for (i = 0; i < job->bo_count; i++)
+		if (job->bos[i])
+			drm_gem_object_put(&job->bos[i]->base.base);
+
+	dma_fence_put(job->done_fence);
+	ivpu_file_priv_put(&job->file_priv);
+	kfree(job);
+}
+
+static struct ivpu_job *
+ivpu_job_create(struct ivpu_file_priv *file_priv, u32 engine_idx, u32 bo_count)
+{
+	struct ivpu_device *vdev = file_priv->vdev;
+	struct ivpu_job *job;
+
+	job = kzalloc(struct_size(job, bos, bo_count), GFP_KERNEL);
+	if (!job)
+		return NULL;
+
+	job->vdev = vdev;
+	job->engine_idx = engine_idx;
+	job->bo_count = bo_count;
+	job->done_fence = ivpu_fence_create(vdev);
+	if (!job->done_fence) {
+		ivpu_err(vdev, "Failed to create a fence\n");
+		goto err_free_job;
+	}
+
+	job->file_priv = ivpu_file_priv_get(file_priv);
+
+	trace_job("create", job);
+	ivpu_dbg(vdev, JOB, "Job created: ctx %2d engine %d", file_priv->ctx.id, job->engine_idx);
+	return job;
+
+err_free_job:
+	kfree(job);
+	return NULL;
+}
+
+static struct ivpu_job *ivpu_job_remove_from_submitted_jobs(struct ivpu_device *vdev, u32 job_id)
+{
+	struct ivpu_job *job;
+
+	lockdep_assert_held(&vdev->submitted_jobs_lock);
+
+	job = xa_erase(&vdev->submitted_jobs_xa, job_id);
+	if (xa_empty(&vdev->submitted_jobs_xa) && job) {
+		vdev->busy_time = ktime_add(ktime_sub(ktime_get(), vdev->busy_start_ts),
+					    vdev->busy_time);
+	}
+
+	return job;
+}
+
+bool ivpu_job_handle_engine_error(struct ivpu_device *vdev, u32 job_id, u32 job_status)
+{
+	lockdep_assert_held(&vdev->submitted_jobs_lock);
+
+	switch (job_status) {
+	case VPU_JSM_STATUS_PROCESSING_ERR:
+	case VPU_JSM_STATUS_ENGINE_RESET_REQUIRED_MIN ... VPU_JSM_STATUS_ENGINE_RESET_REQUIRED_MAX:
+	{
+		struct ivpu_job *job = xa_load(&vdev->submitted_jobs_xa, job_id);
+
+		if (!job)
+			return false;
+
+		/* Trigger an engine reset */
+		guard(mutex)(&job->file_priv->lock);
+
+		job->job_status = job_status;
+
+		if (job->file_priv->has_mmu_faults)
+			return false;
+
+		/*
+		 * Mark context as faulty and defer destruction of the job to jobs abort thread
+		 * handler to synchronize between both faults and jobs returning context violation
+		 * status and ensure both are handled in the same way
+		 */
+		job->file_priv->has_mmu_faults = true;
+		queue_work(system_percpu_wq, &vdev->context_abort_work);
+		return true;
+	}
+	default:
+		/* Complete job with error status, engine reset not required */
+		break;
+	}
+
+	return false;
+}
+
+static int ivpu_job_signal_and_destroy(struct ivpu_device *vdev, u32 job_id, u32 job_status)
+{
+	struct ivpu_job *job;
+
+	lockdep_assert_held(&vdev->submitted_jobs_lock);
+
+	job = xa_load(&vdev->submitted_jobs_xa, job_id);
+	if (!job)
+		return -ENOENT;
+
+	ivpu_job_remove_from_submitted_jobs(vdev, job_id);
+
+	if (job->job_status == VPU_JSM_STATUS_SUCCESS) {
+		if (job->file_priv->has_mmu_faults)
+			job->job_status = DRM_IVPU_JOB_STATUS_ABORTED;
+		else
+			job->job_status = job_status;
+	}
+
+	job->bos[CMD_BUF_IDX]->job_status = job->job_status;
+	dma_fence_signal(job->done_fence);
+
+	trace_job("done", job);
+	ivpu_dbg(vdev, JOB, "Job complete:  id %3u ctx %2d cmdq_id %u engine %d status 0x%x\n",
+		 job->job_id, job->file_priv->ctx.id, job->cmdq_id, job->engine_idx,
+		 job->job_status);
+
+	ivpu_job_destroy(job);
+	ivpu_stop_job_timeout_detection(vdev);
+
+	ivpu_rpm_put(vdev);
+
+	if (!xa_empty(&vdev->submitted_jobs_xa))
+		ivpu_start_job_timeout_detection(vdev);
+
+	return 0;
+}
+
+void ivpu_jobs_abort_all(struct ivpu_device *vdev)
+{
+	struct ivpu_job *job;
+	unsigned long id;
+
+	mutex_lock(&vdev->submitted_jobs_lock);
+
+	xa_for_each(&vdev->submitted_jobs_xa, id, job)
+		ivpu_job_signal_and_destroy(vdev, id, DRM_IVPU_JOB_STATUS_ABORTED);
+
+	mutex_unlock(&vdev->submitted_jobs_lock);
+}
+
+void ivpu_cmdq_abort_all_jobs(struct ivpu_device *vdev, u32 ctx_id, u32 cmdq_id)
+{
+	struct ivpu_job *job;
+	unsigned long id;
+
+	mutex_lock(&vdev->submitted_jobs_lock);
+
+	xa_for_each(&vdev->submitted_jobs_xa, id, job)
+		if (job->file_priv->ctx.id == ctx_id && job->cmdq_id == cmdq_id)
+			ivpu_job_signal_and_destroy(vdev, id, DRM_IVPU_JOB_STATUS_ABORTED);
+
+	mutex_unlock(&vdev->submitted_jobs_lock);
+}
+
+static int ivpu_job_submit(struct ivpu_job *job, u8 priority, u32 cmdq_id)
+{
+	struct ivpu_file_priv *file_priv = job->file_priv;
+	struct ivpu_device *vdev = job->vdev;
+	struct ivpu_cmdq *cmdq;
+	bool is_first_job;
+	int ret;
+
+	ret = ivpu_rpm_get(vdev);
+	if (ret < 0)
+		return ret;
+
+	mutex_lock(&vdev->submitted_jobs_lock);
+	mutex_lock(&file_priv->lock);
+
+	if (cmdq_id == 0)
+		cmdq = ivpu_cmdq_acquire_legacy(file_priv, priority);
+	else
+		cmdq = ivpu_cmdq_acquire(file_priv, cmdq_id);
+	if (!cmdq) {
+		ret = -EINVAL;
+		goto err_unlock;
+	}
+
+	ret = ivpu_cmdq_register(file_priv, cmdq);
+	if (ret) {
+		ivpu_err(vdev, "Failed to register command queue: %d\n", ret);
+		goto err_unlock;
+	}
+
+	ret = ivpu_preemption_job_init(vdev, file_priv, cmdq, job);
+	if (ret) {
+		ivpu_err(vdev, "Failed to initialize preemption buffers for job %d: %d\n",
+			 job->job_id, ret);
+		goto err_unlock;
+	}
+
+	job->cmdq_id = cmdq->id;
+
+	is_first_job = xa_empty(&vdev->submitted_jobs_xa);
+	ret = xa_alloc_cyclic(&vdev->submitted_jobs_xa, &job->job_id, job, file_priv->job_limit,
+			      &file_priv->job_id_next, GFP_KERNEL);
+	if (ret < 0) {
+		ivpu_dbg(vdev, JOB, "Too many active jobs in ctx %d\n",
+			 file_priv->ctx.id);
+		ret = -EBUSY;
+		goto err_unlock;
+	}
+
+	ret = ivpu_cmdq_push_job(cmdq, job);
+	if (ret)
+		goto err_erase_xa;
+
+	ivpu_start_job_timeout_detection(vdev);
+
+	if (unlikely(ivpu_test_mode & IVPU_TEST_MODE_NULL_HW)) {
+		cmdq->jobq->header.head = cmdq->jobq->header.tail;
+		wmb(); /* Flush WC buffer for jobq header */
+	} else {
+		ivpu_cmdq_ring_db(vdev, cmdq);
+		if (is_first_job)
+			vdev->busy_start_ts = ktime_get();
+	}
+
+	trace_job("submit", job);
+	ivpu_dbg(vdev, JOB, "Job submitted: id %3u ctx %2d cmdq_id %u engine %d prio %d addr 0x%llx next %d\n",
+		 job->job_id, file_priv->ctx.id, cmdq->id, job->engine_idx, cmdq->priority,
+		 job->cmd_buf_vpu_addr, cmdq->jobq->header.tail);
+
+	mutex_unlock(&file_priv->lock);
+
+	if (unlikely(ivpu_test_mode & IVPU_TEST_MODE_NULL_HW)) {
+		ivpu_job_signal_and_destroy(vdev, job->job_id, VPU_JSM_STATUS_SUCCESS);
+	}
+
+	mutex_unlock(&vdev->submitted_jobs_lock);
+
+	return 0;
+
+err_erase_xa:
+	xa_erase(&vdev->submitted_jobs_xa, job->job_id);
+err_unlock:
+	mutex_unlock(&file_priv->lock);
+	mutex_unlock(&vdev->submitted_jobs_lock);
+	ivpu_rpm_put(vdev);
+	return ret;
+}
+
+static int
+ivpu_job_prepare_bos_for_submit(struct drm_file *file, struct ivpu_job *job, u32 *buf_handles,
+				u32 buf_count, u32 commands_offset, u32 preempt_buffer_index)
+{
+	struct ivpu_file_priv *file_priv = job->file_priv;
+	struct ivpu_device *vdev = file_priv->vdev;
+	struct ww_acquire_ctx acquire_ctx;
+	enum dma_resv_usage usage;
+	struct ivpu_bo *bo;
+	int ret;
+	u32 i;
+
+	for (i = 0; i < buf_count; i++) {
+		struct drm_gem_object *obj = drm_gem_object_lookup(file, buf_handles[i]);
+
+		if (!obj) {
+			ivpu_dbg(vdev, IOCTL, "Failed to lookup GEM object with handle %u\n",
+				 buf_handles[i]);
+			return -ENOENT;
+		}
+
+		job->bos[i] = to_ivpu_bo(obj);
+
+		ret = ivpu_bo_bind(job->bos[i]);
+		if (ret)
+			return ret;
+	}
+
+	bo = job->bos[CMD_BUF_IDX];
+	if (!dma_resv_test_signaled(bo->base.base.resv, DMA_RESV_USAGE_READ)) {
+		ivpu_dbg(vdev, IOCTL, "Buffer is already in use by another job\n");
+		return -EBUSY;
+	}
+
+	if (commands_offset >= ivpu_bo_size(bo)) {
+		ivpu_dbg(vdev, IOCTL, "Invalid commands offset %u for buffer size %zu\n",
+			 commands_offset, ivpu_bo_size(bo));
+		return -EINVAL;
+	}
+
+	job->cmd_buf_vpu_addr = bo->vpu_addr + commands_offset;
+
+	if (preempt_buffer_index) {
+		struct ivpu_bo *preempt_bo = job->bos[preempt_buffer_index];
+
+		if (ivpu_bo_size(preempt_bo) < ivpu_fw_preempt_buf_size(vdev)) {
+			ivpu_dbg(vdev, IOCTL, "Preemption buffer is too small\n");
+			return -EINVAL;
+		}
+		if (ivpu_bo_is_mappable(preempt_bo)) {
+			ivpu_dbg(vdev, IOCTL, "Preemption buffer cannot be mappable\n");
+			return -EINVAL;
+		}
+		job->primary_preempt_buf = preempt_bo;
+	}
+
+	ret = drm_gem_lock_reservations((struct drm_gem_object **)job->bos, buf_count,
+					&acquire_ctx);
+	if (ret) {
+		ivpu_warn_ratelimited(vdev, "Failed to lock reservations: %d\n", ret);
+		return ret;
+	}
+
+	for (i = 0; i < buf_count; i++) {
+		ret = dma_resv_reserve_fences(job->bos[i]->base.base.resv, 1);
+		if (ret) {
+			ivpu_warn_ratelimited(vdev, "Failed to reserve fences: %d\n", ret);
+			goto unlock_reservations;
+		}
+	}
+
+	for (i = 0; i < buf_count; i++) {
+		usage = (i == CMD_BUF_IDX) ? DMA_RESV_USAGE_WRITE : DMA_RESV_USAGE_BOOKKEEP;
+		dma_resv_add_fence(job->bos[i]->base.base.resv, job->done_fence, usage);
+	}
+
+unlock_reservations:
+	drm_gem_unlock_reservations((struct drm_gem_object **)job->bos, buf_count, &acquire_ctx);
+
+	wmb(); /* Flush write combining buffers */
+
+	return ret;
+}
+
+static int ivpu_submit(struct drm_file *file, struct ivpu_file_priv *file_priv, u32 cmdq_id,
+		       u32 buffer_count, u32 engine, void __user *buffers_ptr, u32 cmds_offset,
+		       u32 preempt_buffer_index, u8 priority)
+{
+	struct ivpu_device *vdev = file_priv->vdev;
+	struct ivpu_job *job;
+	u32 *buf_handles;
+	int idx, ret;
+
+	buf_handles = kcalloc(buffer_count, sizeof(u32), GFP_KERNEL);
+	if (!buf_handles)
+		return -ENOMEM;
+
+	ret = copy_from_user(buf_handles, buffers_ptr, buffer_count * sizeof(u32));
+	if (ret) {
+		ret = -EFAULT;
+		goto err_free_handles;
+	}
+
+	if (!drm_dev_enter(&vdev->drm, &idx)) {
+		ret = -ENODEV;
+		goto err_free_handles;
+	}
+
+	ivpu_dbg(vdev, JOB, "Submit ioctl: ctx %u cmdq_id %u buf_count %u\n",
+		 file_priv->ctx.id, cmdq_id, buffer_count);
+
+	job = ivpu_job_create(file_priv, engine, buffer_count);
+	if (!job) {
+		ret = -ENOMEM;
+		goto err_exit_dev;
+	}
+
+	ret = ivpu_job_prepare_bos_for_submit(file, job, buf_handles, buffer_count, cmds_offset,
+					      preempt_buffer_index);
+	if (ret)
+		goto err_destroy_job;
+
+	down_read(&vdev->pm->reset_lock);
+	ret = ivpu_job_submit(job, priority, cmdq_id);
+	up_read(&vdev->pm->reset_lock);
+	if (ret)
+		goto err_signal_fence;
+
+	drm_dev_exit(idx);
+	kfree(buf_handles);
+	return ret;
+
+err_signal_fence:
+	dma_fence_signal(job->done_fence);
+err_destroy_job:
+	ivpu_job_destroy(job);
+err_exit_dev:
+	drm_dev_exit(idx);
+err_free_handles:
+	kfree(buf_handles);
+	return ret;
+}
+
+int ivpu_submit_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
+{
+	struct ivpu_file_priv *file_priv = file->driver_priv;
+	struct ivpu_device *vdev = file_priv->vdev;
+	struct drm_ivpu_submit *args = data;
+	u8 priority;
+
+	if (args->engine != DRM_IVPU_ENGINE_COMPUTE) {
+		ivpu_dbg(vdev, IOCTL, "Invalid engine %d\n", args->engine);
+		return -EINVAL;
+	}
+
+	if (args->priority > DRM_IVPU_JOB_PRIORITY_REALTIME) {
+		ivpu_dbg(vdev, IOCTL, "Invalid priority %d\n", args->priority);
+		return -EINVAL;
+	}
+
+	if (args->buffer_count == 0 || args->buffer_count > JOB_MAX_BUFFER_COUNT) {
+		ivpu_dbg(vdev, IOCTL, "Invalid buffer count %u\n", args->buffer_count);
+		return -EINVAL;
+	}
+
+	if (!IS_ALIGNED(args->commands_offset, 8)) {
+		ivpu_dbg(vdev, IOCTL, "Invalid commands offset %u\n", args->commands_offset);
+		return -EINVAL;
+	}
+
+	if (!file_priv->ctx.id) {
+		ivpu_dbg(vdev, IOCTL, "Context not initialized\n");
+		return -EINVAL;
+	}
+
+	if (file_priv->has_mmu_faults) {
+		ivpu_dbg(vdev, IOCTL, "Context %u has MMU faults\n", file_priv->ctx.id);
+		return -EBADFD;
+	}
+
+	priority = ivpu_job_to_jsm_priority(args->priority);
+
+	return ivpu_submit(file, file_priv, 0, args->buffer_count, args->engine,
+			   (void __user *)args->buffers_ptr, args->commands_offset, 0, priority);
+}
+
+int ivpu_cmdq_submit_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
+{
+	struct ivpu_file_priv *file_priv = file->driver_priv;
+	struct ivpu_device *vdev = file_priv->vdev;
+	struct drm_ivpu_cmdq_submit *args = data;
+
+	if (!ivpu_is_capable(file_priv->vdev, DRM_IVPU_CAP_MANAGE_CMDQ)) {
+		ivpu_dbg(vdev, IOCTL, "Command queue management not supported\n");
+		return -ENODEV;
+	}
+
+	if (args->cmdq_id < IVPU_CMDQ_MIN_ID || args->cmdq_id > IVPU_CMDQ_MAX_ID) {
+		ivpu_dbg(vdev, IOCTL, "Invalid command queue ID %u\n", args->cmdq_id);
+		return -EINVAL;
+	}
+
+	if (args->buffer_count == 0 || args->buffer_count > JOB_MAX_BUFFER_COUNT) {
+		ivpu_dbg(vdev, IOCTL, "Invalid buffer count %u\n", args->buffer_count);
+		return -EINVAL;
+	}
+
+	if (args->preempt_buffer_index >= args->buffer_count) {
+		ivpu_dbg(vdev, IOCTL, "Invalid preemption buffer index %u\n",
+			 args->preempt_buffer_index);
+		return -EINVAL;
+	}
+
+	if (!IS_ALIGNED(args->commands_offset, 8)) {
+		ivpu_dbg(vdev, IOCTL, "Invalid commands offset %u\n", args->commands_offset);
+		return -EINVAL;
+	}
+
+	if (!file_priv->ctx.id) {
+		ivpu_dbg(vdev, IOCTL, "Context not initialized\n");
+		return -EINVAL;
+	}
+
+	if (file_priv->has_mmu_faults) {
+		ivpu_dbg(vdev, IOCTL, "Context %u has MMU faults\n", file_priv->ctx.id);
+		return -EBADFD;
+	}
+
+	return ivpu_submit(file, file_priv, args->cmdq_id, args->buffer_count, VPU_ENGINE_COMPUTE,
+			   (void __user *)args->buffers_ptr, args->commands_offset,
+			   args->preempt_buffer_index, 0);
+}
+
+int ivpu_cmdq_create_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
+{
+	struct ivpu_file_priv *file_priv = file->driver_priv;
+	struct ivpu_device *vdev = file_priv->vdev;
+	struct drm_ivpu_cmdq_create *args = data;
+	struct ivpu_cmdq *cmdq;
+	int ret;
+
+	if (!ivpu_is_capable(vdev, DRM_IVPU_CAP_MANAGE_CMDQ)) {
+		ivpu_dbg(vdev, IOCTL, "Command queue management not supported\n");
+		return -ENODEV;
+	}
+
+	if (args->priority > DRM_IVPU_JOB_PRIORITY_REALTIME) {
+		ivpu_dbg(vdev, IOCTL, "Invalid priority %d\n", args->priority);
+		return -EINVAL;
+	}
+
+	ret = ivpu_rpm_get(vdev);
+	if (ret < 0)
+		return ret;
+
+	mutex_lock(&file_priv->lock);
+
+	cmdq = ivpu_cmdq_create(file_priv, ivpu_job_to_jsm_priority(args->priority), args->flags);
+	if (cmdq)
+		args->cmdq_id = cmdq->id;
+
+	mutex_unlock(&file_priv->lock);
+
+	ivpu_rpm_put(vdev);
+
+	return cmdq ? 0 : -ENOMEM;
+}
+
+int ivpu_cmdq_destroy_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
+{
+	struct ivpu_file_priv *file_priv = file->driver_priv;
+	struct ivpu_device *vdev = file_priv->vdev;
+	struct drm_ivpu_cmdq_destroy *args = data;
+	struct ivpu_cmdq *cmdq;
+	u32 cmdq_id = 0;
+	int ret;
+
+	if (!ivpu_is_capable(vdev, DRM_IVPU_CAP_MANAGE_CMDQ)) {
+		ivpu_dbg(vdev, IOCTL, "Command queue management not supported\n");
+		return -ENODEV;
+	}
+
+	ret = ivpu_rpm_get(vdev);
+	if (ret < 0)
+		return ret;
+
+	mutex_lock(&file_priv->lock);
+
+	cmdq = xa_load(&file_priv->cmdq_xa, args->cmdq_id);
+	if (!cmdq || cmdq->is_legacy) {
+		ret = -ENOENT;
+	} else {
+		cmdq_id = cmdq->id;
+		ivpu_cmdq_destroy(file_priv, cmdq);
+		ret = 0;
+	}
+
+	mutex_unlock(&file_priv->lock);
+
+	/* Abort any pending jobs only if cmdq was destroyed */
+	if (!ret)
+		ivpu_cmdq_abort_all_jobs(vdev, file_priv->ctx.id, cmdq_id);
+
+	ivpu_rpm_put(vdev);
+
+	return ret;
+}
+
+static void
+ivpu_job_done_callback(struct ivpu_device *vdev, struct ivpu_ipc_hdr *ipc_hdr,
+		       struct vpu_jsm_msg *jsm_msg)
+{
+	struct vpu_ipc_msg_payload_job_done *payload;
+
+	if (!jsm_msg) {
+		ivpu_err(vdev, "IPC message has no JSM payload\n");
+		return;
+	}
+
+	if (jsm_msg->result != VPU_JSM_STATUS_SUCCESS) {
+		ivpu_err(vdev, "Invalid JSM message result: %d\n", jsm_msg->result);
+		return;
+	}
+
+	payload = (struct vpu_ipc_msg_payload_job_done *)&jsm_msg->payload;
+
+	mutex_lock(&vdev->submitted_jobs_lock);
+	if (!ivpu_job_handle_engine_error(vdev, payload->job_id, payload->job_status))
+		/* No engine error, complete the job normally */
+		ivpu_job_signal_and_destroy(vdev, payload->job_id, payload->job_status);
+	mutex_unlock(&vdev->submitted_jobs_lock);
+}
+
+void ivpu_job_done_consumer_init(struct ivpu_device *vdev)
+{
+	ivpu_ipc_consumer_add(vdev, &vdev->job_done_consumer,
+			      VPU_IPC_CHAN_JOB_RET, ivpu_job_done_callback);
+}
+
+void ivpu_job_done_consumer_fini(struct ivpu_device *vdev)
+{
+	ivpu_ipc_consumer_del(vdev, &vdev->job_done_consumer);
+}
+
+void ivpu_context_abort_work_fn(struct work_struct *work)
+{
+	struct ivpu_device *vdev = container_of(work, struct ivpu_device, context_abort_work);
+	struct ivpu_file_priv *file_priv;
+	struct ivpu_job *job;
+	unsigned long ctx_id;
+	unsigned long id;
+
+	if (drm_WARN_ON(&vdev->drm, pm_runtime_get_if_active(vdev->drm.dev) <= 0))
+		return;
+
+	if (vdev->fw->sched_mode == VPU_SCHEDULING_MODE_HW)
+		if (ivpu_jsm_reset_engine(vdev, 0))
+			goto runtime_put;
+
+	mutex_lock(&vdev->context_list_lock);
+	xa_for_each(&vdev->context_xa, ctx_id, file_priv) {
+		if (!file_priv->has_mmu_faults || file_priv->aborted)
+			continue;
+
+		mutex_lock(&file_priv->lock);
+		ivpu_context_abort_locked(file_priv);
+		mutex_unlock(&file_priv->lock);
+	}
+	mutex_unlock(&vdev->context_list_lock);
+
+	/*
+	 * We will not receive new MMU event interrupts until existing events are discarded
+	 * however, we want to discard these events only after aborting the faulty context
+	 * to avoid generating new faults from that context
+	 */
+	ivpu_mmu_discard_events(vdev);
+
+	if (vdev->fw->sched_mode != VPU_SCHEDULING_MODE_HW)
+		goto runtime_put;
+
+	if (ivpu_jsm_hws_resume_engine(vdev, 0))
+		goto runtime_put;
+	/*
+	 * In hardware scheduling mode NPU already has stopped processing jobs
+	 * and won't send us any further notifications, thus we have to free job related resources
+	 * and notify userspace
+	 */
+	mutex_lock(&vdev->submitted_jobs_lock);
+	xa_for_each(&vdev->submitted_jobs_xa, id, job)
+		if (job->file_priv->aborted)
+			ivpu_job_signal_and_destroy(vdev, job->job_id, DRM_IVPU_JOB_STATUS_ABORTED);
+	mutex_unlock(&vdev->submitted_jobs_lock);
+
+runtime_put:
+	pm_runtime_put_autosuspend(vdev->drm.dev);
+}
diff --git a/drivers/accel/ivpu/ivpu_job.h b/drivers/accel/ivpu/ivpu_job.h
new file mode 100644
index 000000000000..3ab61e6a5616
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_job.h
@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2020-2025 Intel Corporation
+ */
+
+#ifndef __IVPU_JOB_H__
+#define __IVPU_JOB_H__
+
+#include <linux/kref.h>
+#include <linux/idr.h>
+
+#include "ivpu_gem.h"
+
+struct ivpu_device;
+struct ivpu_file_priv;
+
+/**
+ * struct ivpu_cmdq - Represents a command queue for submitting jobs to the VPU.
+ * Tracks queue memory, preemption buffers, and metadata for job management.
+ * @jobq:                Pointer to job queue memory shared with the device
+ * @primary_preempt_buf: Primary preemption buffer for this queue (optional)
+ * @secondary_preempt_buf: Secondary preemption buffer for this queue (optional)
+ * @mem:                 Memory allocated for the job queue, shared with device
+ * @entry_count:         Number of job entries in the queue
+ * @id:                  Unique command queue ID
+ * @db_id:               Doorbell ID assigned to this job queue
+ * @priority:            Priority level of the command queue
+ * @is_legacy:           True if this is a legacy command queue
+ */
+struct ivpu_cmdq {
+	struct vpu_job_queue *jobq;
+	struct ivpu_bo *primary_preempt_buf;
+	struct ivpu_bo *secondary_preempt_buf;
+	struct ivpu_bo *mem;
+	u32 entry_count;
+	u32 id;
+	u32 db_id;
+	u8 priority;
+	bool is_legacy;
+};
+
+/**
+ * struct ivpu_job - Representing a batch or DMA buffer submitted to the VPU.
+ * Each job is a unit of execution, tracked by job_id for status reporting from VPU FW.
+ * The structure holds all resources and metadata needed for job submission, execution,
+ * and completion handling.
+ * @vdev:                Pointer to the VPU device
+ * @file_priv:           The client context that submitted this job
+ * @done_fence:          Fence signaled when job completes
+ * @cmd_buf_vpu_addr:    VPU address of the command buffer for this job
+ * @cmdq_id:             Command queue ID used for submission
+ * @job_id:              Unique job ID for tracking and status reporting
+ * @engine_idx:          Engine index for job execution
+ * @job_status:          Status reported by firmware for this job
+ * @primary_preempt_buf: Primary preemption buffer for job
+ * @secondary_preempt_buf: Secondary preemption buffer for job (optional)
+ * @bo_count:            Number of buffer objects associated with this job
+ * @bos:                 Array of buffer objects used by the job (batch buffer is at index 0)
+ */
+struct ivpu_job {
+	struct ivpu_device *vdev;
+	struct ivpu_file_priv *file_priv;
+	struct dma_fence *done_fence;
+	u64 cmd_buf_vpu_addr;
+	u32 cmdq_id;
+	u32 job_id;
+	u32 engine_idx;
+	u32 job_status;
+	struct ivpu_bo *primary_preempt_buf;
+	struct ivpu_bo *secondary_preempt_buf;
+	size_t bo_count;
+	struct ivpu_bo *bos[] __counted_by(bo_count);
+};
+
+int ivpu_submit_ioctl(struct drm_device *dev, void *data, struct drm_file *file);
+int ivpu_cmdq_create_ioctl(struct drm_device *dev, void *data, struct drm_file *file);
+int ivpu_cmdq_destroy_ioctl(struct drm_device *dev, void *data, struct drm_file *file);
+int ivpu_cmdq_submit_ioctl(struct drm_device *dev, void *data, struct drm_file *file);
+
+void ivpu_context_abort_locked(struct ivpu_file_priv *file_priv);
+
+void ivpu_cmdq_release_all_locked(struct ivpu_file_priv *file_priv);
+void ivpu_cmdq_reset_all_contexts(struct ivpu_device *vdev);
+void ivpu_cmdq_abort_all_jobs(struct ivpu_device *vdev, u32 ctx_id, u32 cmdq_id);
+
+void ivpu_job_done_consumer_init(struct ivpu_device *vdev);
+void ivpu_job_done_consumer_fini(struct ivpu_device *vdev);
+bool ivpu_job_handle_engine_error(struct ivpu_device *vdev, u32 job_id, u32 job_status);
+void ivpu_context_abort_work_fn(struct work_struct *work);
+
+void ivpu_jobs_abort_all(struct ivpu_device *vdev);
+
+#endif /* __IVPU_JOB_H__ */
diff --git a/drivers/accel/ivpu/ivpu_jsm_msg.c b/drivers/accel/ivpu/ivpu_jsm_msg.c
new file mode 100644
index 000000000000..0256b2dfefc1
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_jsm_msg.c
@@ -0,0 +1,562 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020-2024 Intel Corporation
+ */
+
+#include "ivpu_drv.h"
+#include "ivpu_hw.h"
+#include "ivpu_ipc.h"
+#include "ivpu_jsm_msg.h"
+#include "ivpu_pm.h"
+#include "vpu_jsm_api.h"
+
+const char *ivpu_jsm_msg_type_to_str(enum vpu_ipc_msg_type type)
+{
+	#define IVPU_CASE_TO_STR(x) case x: return #x
+	switch (type) {
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_UNKNOWN);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_ENGINE_RESET);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_ENGINE_PREEMPT);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_REGISTER_DB);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_UNREGISTER_DB);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_QUERY_ENGINE_HB);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_GET_POWER_LEVEL_COUNT);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_GET_POWER_LEVEL);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_SET_POWER_LEVEL);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_METRIC_STREAMER_OPEN);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_METRIC_STREAMER_CLOSE);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_TRACE_SET_CONFIG);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_TRACE_GET_CONFIG);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_TRACE_GET_CAPABILITY);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_TRACE_GET_NAME);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_SSID_RELEASE);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_METRIC_STREAMER_START);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_METRIC_STREAMER_STOP);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_METRIC_STREAMER_UPDATE);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_METRIC_STREAMER_INFO);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_SET_PRIORITY_BAND_SETUP);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_CREATE_CMD_QUEUE);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_DESTROY_CMD_QUEUE);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_SET_CONTEXT_SCHED_PROPERTIES);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_HWS_REGISTER_DB);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_HWS_RESUME_CMDQ);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_HWS_SUSPEND_CMDQ);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_HWS_RESUME_CMDQ_RSP);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_HWS_SUSPEND_CMDQ_DONE);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_HWS_SET_SCHEDULING_LOG);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_HWS_SET_SCHEDULING_LOG_RSP);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_HWS_SCHEDULING_LOG_NOTIFICATION);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_HWS_ENGINE_RESUME);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_HWS_RESUME_ENGINE_DONE);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_STATE_DUMP);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_STATE_DUMP_RSP);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_BLOB_DEINIT_DEPRECATED);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_DYNDBG_CONTROL);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_JOB_DONE);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_NATIVE_FENCE_SIGNALLED);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_ENGINE_RESET_DONE);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_ENGINE_PREEMPT_DONE);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_REGISTER_DB_DONE);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_UNREGISTER_DB_DONE);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_QUERY_ENGINE_HB_DONE);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_GET_POWER_LEVEL_COUNT_DONE);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_GET_POWER_LEVEL_DONE);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_SET_POWER_LEVEL_DONE);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_METRIC_STREAMER_OPEN_DONE);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_METRIC_STREAMER_CLOSE_DONE);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_TRACE_SET_CONFIG_RSP);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_TRACE_GET_CONFIG_RSP);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_TRACE_GET_CAPABILITY_RSP);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_TRACE_GET_NAME_RSP);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_SSID_RELEASE_DONE);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_METRIC_STREAMER_START_DONE);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_METRIC_STREAMER_STOP_DONE);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_METRIC_STREAMER_UPDATE_DONE);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_METRIC_STREAMER_INFO_DONE);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_METRIC_STREAMER_NOTIFICATION);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_SET_PRIORITY_BAND_SETUP_RSP);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_CREATE_CMD_QUEUE_RSP);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_DESTROY_CMD_QUEUE_RSP);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_SET_CONTEXT_SCHED_PROPERTIES_RSP);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_BLOB_DEINIT_DONE);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_DYNDBG_CONTROL_RSP);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_PWR_D0I3_ENTER);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_PWR_D0I3_ENTER_DONE);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_DCT_ENABLE);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_DCT_ENABLE_DONE);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_DCT_DISABLE);
+	IVPU_CASE_TO_STR(VPU_JSM_MSG_DCT_DISABLE_DONE);
+	}
+	#undef IVPU_CASE_TO_STR
+
+	return "Unknown JSM message type";
+}
+
+int ivpu_jsm_register_db(struct ivpu_device *vdev, u32 ctx_id, u32 db_id,
+			 u64 jobq_base, u32 jobq_size)
+{
+	struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_REGISTER_DB };
+	struct vpu_jsm_msg resp;
+	int ret = 0;
+
+	req.payload.register_db.db_idx = db_id;
+	req.payload.register_db.jobq_base = jobq_base;
+	req.payload.register_db.jobq_size = jobq_size;
+	req.payload.register_db.host_ssid = ctx_id;
+
+	ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_REGISTER_DB_DONE, &resp,
+				    VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
+	if (ret)
+		ivpu_err_ratelimited(vdev, "Failed to register doorbell %u: %d\n", db_id, ret);
+
+	return ret;
+}
+
+int ivpu_jsm_unregister_db(struct ivpu_device *vdev, u32 db_id)
+{
+	struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_UNREGISTER_DB };
+	struct vpu_jsm_msg resp;
+	int ret = 0;
+
+	req.payload.unregister_db.db_idx = db_id;
+
+	ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_UNREGISTER_DB_DONE, &resp,
+				    VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
+	if (ret)
+		ivpu_warn_ratelimited(vdev, "Failed to unregister doorbell %u: %d\n", db_id, ret);
+
+	return ret;
+}
+
+int ivpu_jsm_get_heartbeat(struct ivpu_device *vdev, u32 engine, u64 *heartbeat)
+{
+	struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_QUERY_ENGINE_HB };
+	struct vpu_jsm_msg resp;
+	int ret;
+
+	if (engine != VPU_ENGINE_COMPUTE)
+		return -EINVAL;
+
+	req.payload.query_engine_hb.engine_idx = engine;
+
+	ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_QUERY_ENGINE_HB_DONE, &resp,
+				    VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
+	if (ret) {
+		ivpu_err_ratelimited(vdev, "Failed to get heartbeat from engine %d: %d\n",
+				     engine, ret);
+		return ret;
+	}
+
+	*heartbeat = resp.payload.query_engine_hb_done.heartbeat;
+	return ret;
+}
+
+int ivpu_jsm_reset_engine(struct ivpu_device *vdev, u32 engine)
+{
+	struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_ENGINE_RESET };
+	struct vpu_jsm_msg resp;
+	int ret;
+
+	if (engine != VPU_ENGINE_COMPUTE)
+		return -EINVAL;
+
+	req.payload.engine_reset.engine_idx = engine;
+
+	ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_ENGINE_RESET_DONE, &resp,
+				    VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
+	if (ret) {
+		ivpu_err_ratelimited(vdev, "Failed to reset engine %d: %d\n", engine, ret);
+		ivpu_pm_trigger_recovery(vdev, "Engine reset failed");
+	}
+
+	return ret;
+}
+
+int ivpu_jsm_preempt_engine(struct ivpu_device *vdev, u32 engine, u32 preempt_id)
+{
+	struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_ENGINE_PREEMPT };
+	struct vpu_jsm_msg resp;
+	int ret;
+
+	if (engine != VPU_ENGINE_COMPUTE)
+		return -EINVAL;
+
+	req.payload.engine_preempt.engine_idx = engine;
+	req.payload.engine_preempt.preempt_id = preempt_id;
+
+	ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_ENGINE_PREEMPT_DONE, &resp,
+				    VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
+	if (ret)
+		ivpu_err_ratelimited(vdev, "Failed to preempt engine %d: %d\n", engine, ret);
+
+	return ret;
+}
+
+int ivpu_jsm_dyndbg_control(struct ivpu_device *vdev, char *command, size_t size)
+{
+	struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_DYNDBG_CONTROL };
+	struct vpu_jsm_msg resp;
+	int ret;
+
+	strscpy(req.payload.dyndbg_control.dyndbg_cmd, command, VPU_DYNDBG_CMD_MAX_LEN);
+
+	ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_DYNDBG_CONTROL_RSP, &resp,
+				    VPU_IPC_CHAN_GEN_CMD, vdev->timeout.jsm);
+	if (ret)
+		ivpu_warn_ratelimited(vdev, "Failed to send command \"%s\": ret %d\n",
+				      command, ret);
+
+	return ret;
+}
+
+int ivpu_jsm_trace_get_capability(struct ivpu_device *vdev, u32 *trace_destination_mask,
+				  u64 *trace_hw_component_mask)
+{
+	struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_TRACE_GET_CAPABILITY };
+	struct vpu_jsm_msg resp;
+	int ret;
+
+	ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_TRACE_GET_CAPABILITY_RSP, &resp,
+				    VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
+	if (ret) {
+		ivpu_warn_ratelimited(vdev, "Failed to get trace capability: %d\n", ret);
+		return ret;
+	}
+
+	*trace_destination_mask = resp.payload.trace_capability.trace_destination_mask;
+	*trace_hw_component_mask = resp.payload.trace_capability.trace_hw_component_mask;
+
+	return ret;
+}
+
+int ivpu_jsm_trace_set_config(struct ivpu_device *vdev, u32 trace_level, u32 trace_destination_mask,
+			      u64 trace_hw_component_mask)
+{
+	struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_TRACE_SET_CONFIG };
+	struct vpu_jsm_msg resp;
+	int ret;
+
+	req.payload.trace_config.trace_level = trace_level;
+	req.payload.trace_config.trace_destination_mask = trace_destination_mask;
+	req.payload.trace_config.trace_hw_component_mask = trace_hw_component_mask;
+
+	ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_TRACE_SET_CONFIG_RSP, &resp,
+				    VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
+	if (ret)
+		ivpu_warn_ratelimited(vdev, "Failed to set config: %d\n", ret);
+
+	return ret;
+}
+
+int ivpu_jsm_context_release(struct ivpu_device *vdev, u32 host_ssid)
+{
+	struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_SSID_RELEASE };
+	struct vpu_jsm_msg resp;
+	int ret;
+
+	req.payload.ssid_release.host_ssid = host_ssid;
+
+	ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_SSID_RELEASE_DONE, &resp,
+				    VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
+	if (ret)
+		ivpu_warn_ratelimited(vdev, "Failed to release context: %d\n", ret);
+
+	return ret;
+}
+
+int ivpu_jsm_pwr_d0i3_enter(struct ivpu_device *vdev)
+{
+	struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_PWR_D0I3_ENTER };
+	struct vpu_jsm_msg resp;
+	int ret;
+
+	if (IVPU_WA(disable_d0i3_msg))
+		return 0;
+
+	req.payload.pwr_d0i3_enter.send_response = 1;
+
+	ret = ivpu_ipc_send_receive_internal(vdev, &req, VPU_JSM_MSG_PWR_D0I3_ENTER_DONE, &resp,
+					     VPU_IPC_CHAN_GEN_CMD, vdev->timeout.d0i3_entry_msg);
+	if (ret)
+		return ret;
+
+	return ivpu_hw_wait_for_idle(vdev);
+}
+
+int ivpu_jsm_hws_create_cmdq(struct ivpu_device *vdev, u32 ctx_id, u32 cmdq_group, u32 cmdq_id,
+			     u32 pid, u32 engine, u64 cmdq_base, u32 cmdq_size)
+{
+	struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_CREATE_CMD_QUEUE };
+	struct vpu_jsm_msg resp;
+	int ret;
+
+	req.payload.hws_create_cmdq.host_ssid = ctx_id;
+	req.payload.hws_create_cmdq.process_id = pid;
+	req.payload.hws_create_cmdq.engine_idx = engine;
+	req.payload.hws_create_cmdq.cmdq_group = cmdq_group;
+	req.payload.hws_create_cmdq.cmdq_id = cmdq_id;
+	req.payload.hws_create_cmdq.cmdq_base = cmdq_base;
+	req.payload.hws_create_cmdq.cmdq_size = cmdq_size;
+
+	ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_CREATE_CMD_QUEUE_RSP, &resp,
+				    VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
+	if (ret)
+		ivpu_warn_ratelimited(vdev, "Failed to create command queue: %d\n", ret);
+
+	return ret;
+}
+
+int ivpu_jsm_hws_destroy_cmdq(struct ivpu_device *vdev, u32 ctx_id, u32 cmdq_id)
+{
+	struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_DESTROY_CMD_QUEUE };
+	struct vpu_jsm_msg resp;
+	int ret;
+
+	req.payload.hws_destroy_cmdq.host_ssid = ctx_id;
+	req.payload.hws_destroy_cmdq.cmdq_id = cmdq_id;
+
+	ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_DESTROY_CMD_QUEUE_RSP, &resp,
+				    VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
+	if (ret)
+		ivpu_warn_ratelimited(vdev, "Failed to destroy command queue: %d\n", ret);
+
+	return ret;
+}
+
+int ivpu_jsm_hws_register_db(struct ivpu_device *vdev, u32 ctx_id, u32 cmdq_id, u32 db_id,
+			     u64 cmdq_base, u32 cmdq_size)
+{
+	struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_HWS_REGISTER_DB };
+	struct vpu_jsm_msg resp;
+	int ret = 0;
+
+	req.payload.hws_register_db.db_id = db_id;
+	req.payload.hws_register_db.host_ssid = ctx_id;
+	req.payload.hws_register_db.cmdq_id = cmdq_id;
+	req.payload.hws_register_db.cmdq_base = cmdq_base;
+	req.payload.hws_register_db.cmdq_size = cmdq_size;
+
+	ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_REGISTER_DB_DONE, &resp,
+				    VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
+	if (ret)
+		ivpu_err_ratelimited(vdev, "Failed to register doorbell %u: %d\n", db_id, ret);
+
+	return ret;
+}
+
+int ivpu_jsm_hws_resume_engine(struct ivpu_device *vdev, u32 engine)
+{
+	struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_HWS_ENGINE_RESUME };
+	struct vpu_jsm_msg resp;
+	int ret;
+
+	if (engine != VPU_ENGINE_COMPUTE)
+		return -EINVAL;
+
+	req.payload.hws_resume_engine.engine_idx = engine;
+
+	ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_HWS_RESUME_ENGINE_DONE, &resp,
+				    VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
+	if (ret) {
+		ivpu_err_ratelimited(vdev, "Failed to resume engine %d: %d\n", engine, ret);
+		ivpu_pm_trigger_recovery(vdev, "Engine resume failed");
+	}
+
+	return ret;
+}
+
+int ivpu_jsm_hws_set_context_sched_properties(struct ivpu_device *vdev, u32 ctx_id, u32 cmdq_id,
+					      u32 priority)
+{
+	struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_SET_CONTEXT_SCHED_PROPERTIES };
+	struct vpu_jsm_msg resp;
+	int ret;
+
+	req.payload.hws_set_context_sched_properties.host_ssid = ctx_id;
+	req.payload.hws_set_context_sched_properties.cmdq_id = cmdq_id;
+	req.payload.hws_set_context_sched_properties.priority_band = priority;
+	req.payload.hws_set_context_sched_properties.realtime_priority_level = 0;
+	req.payload.hws_set_context_sched_properties.in_process_priority = 0;
+	req.payload.hws_set_context_sched_properties.context_quantum = 20000;
+	req.payload.hws_set_context_sched_properties.grace_period_same_priority = 10000;
+	req.payload.hws_set_context_sched_properties.grace_period_lower_priority = 0;
+
+	ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_SET_CONTEXT_SCHED_PROPERTIES_RSP, &resp,
+				    VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
+	if (ret)
+		ivpu_warn_ratelimited(vdev, "Failed to set context sched properties: %d\n", ret);
+
+	return ret;
+}
+
+int ivpu_jsm_hws_set_scheduling_log(struct ivpu_device *vdev, u32 engine_idx, u32 host_ssid,
+				    u64 vpu_log_buffer_va)
+{
+	struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_HWS_SET_SCHEDULING_LOG };
+	struct vpu_jsm_msg resp;
+	int ret;
+
+	req.payload.hws_set_scheduling_log.engine_idx = engine_idx;
+	req.payload.hws_set_scheduling_log.host_ssid = host_ssid;
+	req.payload.hws_set_scheduling_log.vpu_log_buffer_va = vpu_log_buffer_va;
+	req.payload.hws_set_scheduling_log.notify_index = 0;
+
+	ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_HWS_SET_SCHEDULING_LOG_RSP, &resp,
+				    VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
+	if (ret)
+		ivpu_warn_ratelimited(vdev, "Failed to set scheduling log: %d\n", ret);
+
+	return ret;
+}
+
+int ivpu_jsm_hws_setup_priority_bands(struct ivpu_device *vdev)
+{
+	struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_SET_PRIORITY_BAND_SETUP };
+	struct vpu_jsm_msg resp;
+	struct ivpu_hw_info *hw = vdev->hw;
+	struct vpu_ipc_msg_payload_hws_priority_band_setup *setup =
+		&req.payload.hws_priority_band_setup;
+	int ret;
+
+	for (int band = VPU_JOB_SCHEDULING_PRIORITY_BAND_IDLE;
+	     band < VPU_JOB_SCHEDULING_PRIORITY_BAND_COUNT; band++) {
+		setup->grace_period[band] = hw->hws.grace_period[band];
+		setup->process_grace_period[band] = hw->hws.process_grace_period[band];
+		setup->process_quantum[band] = hw->hws.process_quantum[band];
+	}
+	setup->normal_band_percentage = 10;
+
+	ret = ivpu_ipc_send_receive_internal(vdev, &req, VPU_JSM_MSG_SET_PRIORITY_BAND_SETUP_RSP,
+					     &resp, VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
+	if (ret)
+		ivpu_warn_ratelimited(vdev, "Failed to set priority bands: %d\n", ret);
+
+	return ret;
+}
+
+int ivpu_jsm_metric_streamer_start(struct ivpu_device *vdev, u64 metric_group_mask,
+				   u64 sampling_rate, u64 buffer_addr, u64 buffer_size)
+{
+	struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_METRIC_STREAMER_START };
+	struct vpu_jsm_msg resp;
+	int ret;
+
+	req.payload.metric_streamer_start.metric_group_mask = metric_group_mask;
+	req.payload.metric_streamer_start.sampling_rate = sampling_rate;
+	req.payload.metric_streamer_start.buffer_addr = buffer_addr;
+	req.payload.metric_streamer_start.buffer_size = buffer_size;
+
+	ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_METRIC_STREAMER_START_DONE, &resp,
+				    VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
+	if (ret) {
+		ivpu_warn_ratelimited(vdev, "Failed to start metric streamer: ret %d\n", ret);
+		return ret;
+	}
+
+	return ret;
+}
+
+int ivpu_jsm_metric_streamer_stop(struct ivpu_device *vdev, u64 metric_group_mask)
+{
+	struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_METRIC_STREAMER_STOP };
+	struct vpu_jsm_msg resp;
+	int ret;
+
+	req.payload.metric_streamer_stop.metric_group_mask = metric_group_mask;
+
+	ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_METRIC_STREAMER_STOP_DONE, &resp,
+				    VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
+	if (ret)
+		ivpu_warn_ratelimited(vdev, "Failed to stop metric streamer: ret %d\n", ret);
+
+	return ret;
+}
+
+int ivpu_jsm_metric_streamer_update(struct ivpu_device *vdev, u64 metric_group_mask,
+				    u64 buffer_addr, u64 buffer_size, u64 *bytes_written)
+{
+	struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_METRIC_STREAMER_UPDATE };
+	struct vpu_jsm_msg resp;
+	int ret;
+
+	req.payload.metric_streamer_update.metric_group_mask = metric_group_mask;
+	req.payload.metric_streamer_update.buffer_addr = buffer_addr;
+	req.payload.metric_streamer_update.buffer_size = buffer_size;
+
+	ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_METRIC_STREAMER_UPDATE_DONE, &resp,
+				    VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
+	if (ret) {
+		ivpu_warn_ratelimited(vdev, "Failed to update metric streamer: ret %d\n", ret);
+		return ret;
+	}
+
+	if (buffer_size && resp.payload.metric_streamer_done.bytes_written > buffer_size) {
+		ivpu_warn_ratelimited(vdev, "MS buffer overflow: bytes_written %#llx > buffer_size %#llx\n",
+				      resp.payload.metric_streamer_done.bytes_written, buffer_size);
+		return -EOVERFLOW;
+	}
+
+	*bytes_written = resp.payload.metric_streamer_done.bytes_written;
+
+	return ret;
+}
+
+int ivpu_jsm_metric_streamer_info(struct ivpu_device *vdev, u64 metric_group_mask, u64 buffer_addr,
+				  u64 buffer_size, u32 *sample_size, u64 *info_size)
+{
+	struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_METRIC_STREAMER_INFO };
+	struct vpu_jsm_msg resp;
+	int ret;
+
+	req.payload.metric_streamer_start.metric_group_mask = metric_group_mask;
+	req.payload.metric_streamer_start.buffer_addr = buffer_addr;
+	req.payload.metric_streamer_start.buffer_size = buffer_size;
+
+	ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_METRIC_STREAMER_INFO_DONE, &resp,
+				    VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
+	if (ret) {
+		ivpu_warn_ratelimited(vdev, "Failed to get metric streamer info: ret %d\n", ret);
+		return ret;
+	}
+
+	if (!resp.payload.metric_streamer_done.sample_size) {
+		ivpu_warn_ratelimited(vdev, "Invalid sample size\n");
+		return -EBADMSG;
+	}
+
+	if (sample_size)
+		*sample_size = resp.payload.metric_streamer_done.sample_size;
+	if (info_size)
+		*info_size = resp.payload.metric_streamer_done.bytes_written;
+
+	return ret;
+}
+
+int ivpu_jsm_dct_enable(struct ivpu_device *vdev, u32 active_us, u32 inactive_us)
+{
+	struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_DCT_ENABLE };
+	struct vpu_jsm_msg resp;
+
+	req.payload.pwr_dct_control.dct_active_us = active_us;
+	req.payload.pwr_dct_control.dct_inactive_us = inactive_us;
+
+	return ivpu_ipc_send_receive_internal(vdev, &req, VPU_JSM_MSG_DCT_ENABLE_DONE, &resp,
+					      VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
+}
+
+int ivpu_jsm_dct_disable(struct ivpu_device *vdev)
+{
+	struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_DCT_DISABLE };
+	struct vpu_jsm_msg resp;
+
+	return ivpu_ipc_send_receive_internal(vdev, &req, VPU_JSM_MSG_DCT_DISABLE_DONE, &resp,
+					      VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);
+}
+
+int ivpu_jsm_state_dump(struct ivpu_device *vdev)
+{
+	struct vpu_jsm_msg req = { .type = VPU_JSM_MSG_STATE_DUMP };
+
+	return ivpu_ipc_send_and_wait(vdev, &req, VPU_IPC_CHAN_ASYNC_CMD,
+				      vdev->timeout.state_dump_msg);
+}
diff --git a/drivers/accel/ivpu/ivpu_jsm_msg.h b/drivers/accel/ivpu/ivpu_jsm_msg.h
new file mode 100644
index 000000000000..9e84d3526a14
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_jsm_msg.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2020-2024 Intel Corporation
+ */
+
+#ifndef __IVPU_JSM_MSG_H__
+#define __IVPU_JSM_MSG_H__
+
+#include "vpu_jsm_api.h"
+
+const char *ivpu_jsm_msg_type_to_str(enum vpu_ipc_msg_type type);
+
+int ivpu_jsm_register_db(struct ivpu_device *vdev, u32 ctx_id, u32 db_id,
+			 u64 jobq_base, u32 jobq_size);
+int ivpu_jsm_unregister_db(struct ivpu_device *vdev, u32 db_id);
+int ivpu_jsm_get_heartbeat(struct ivpu_device *vdev, u32 engine, u64 *heartbeat);
+int ivpu_jsm_reset_engine(struct ivpu_device *vdev, u32 engine);
+int ivpu_jsm_preempt_engine(struct ivpu_device *vdev, u32 engine, u32 preempt_id);
+int ivpu_jsm_dyndbg_control(struct ivpu_device *vdev, char *command, size_t size);
+int ivpu_jsm_trace_get_capability(struct ivpu_device *vdev, u32 *trace_destination_mask,
+				  u64 *trace_hw_component_mask);
+int ivpu_jsm_trace_set_config(struct ivpu_device *vdev, u32 trace_level, u32 trace_destination_mask,
+			      u64 trace_hw_component_mask);
+int ivpu_jsm_context_release(struct ivpu_device *vdev, u32 host_ssid);
+int ivpu_jsm_pwr_d0i3_enter(struct ivpu_device *vdev);
+int ivpu_jsm_hws_create_cmdq(struct ivpu_device *vdev, u32 ctx_id, u32 cmdq_group, u32 cmdq_id,
+			     u32 pid, u32 engine, u64 cmdq_base, u32 cmdq_size);
+int ivpu_jsm_hws_destroy_cmdq(struct ivpu_device *vdev, u32 ctx_id, u32 cmdq_id);
+int ivpu_jsm_hws_register_db(struct ivpu_device *vdev, u32 ctx_id, u32 cmdq_id, u32 db_id,
+			     u64 cmdq_base, u32 cmdq_size);
+int ivpu_jsm_hws_resume_engine(struct ivpu_device *vdev, u32 engine);
+int ivpu_jsm_hws_set_context_sched_properties(struct ivpu_device *vdev, u32 ctx_id, u32 cmdq_id,
+					      u32 priority);
+int ivpu_jsm_hws_set_scheduling_log(struct ivpu_device *vdev, u32 engine_idx, u32 host_ssid,
+				    u64 vpu_log_buffer_va);
+int ivpu_jsm_hws_setup_priority_bands(struct ivpu_device *vdev);
+int ivpu_jsm_metric_streamer_start(struct ivpu_device *vdev, u64 metric_group_mask,
+				   u64 sampling_rate, u64 buffer_addr, u64 buffer_size);
+int ivpu_jsm_metric_streamer_stop(struct ivpu_device *vdev, u64 metric_group_mask);
+int ivpu_jsm_metric_streamer_update(struct ivpu_device *vdev, u64 metric_group_mask,
+				    u64 buffer_addr, u64 buffer_size, u64 *bytes_written);
+int ivpu_jsm_metric_streamer_info(struct ivpu_device *vdev, u64 metric_group_mask, u64 buffer_addr,
+				  u64 buffer_size, u32 *sample_size, u64 *info_size);
+int ivpu_jsm_dct_enable(struct ivpu_device *vdev, u32 active_us, u32 inactive_us);
+int ivpu_jsm_dct_disable(struct ivpu_device *vdev);
+int ivpu_jsm_state_dump(struct ivpu_device *vdev);
+
+#endif
diff --git a/drivers/accel/ivpu/ivpu_mmu.c b/drivers/accel/ivpu/ivpu_mmu.c
new file mode 100644
index 000000000000..e1baf6b64935
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_mmu.c
@@ -0,0 +1,1029 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020-2024 Intel Corporation
+ */
+
+#include <linux/circ_buf.h>
+#include <linux/highmem.h>
+
+#include "ivpu_drv.h"
+#include "ivpu_hw.h"
+#include "ivpu_hw_reg_io.h"
+#include "ivpu_mmu.h"
+#include "ivpu_mmu_context.h"
+#include "ivpu_pm.h"
+
+#define IVPU_MMU_REG_IDR0		      0x00200000u
+#define IVPU_MMU_REG_IDR1		      0x00200004u
+#define IVPU_MMU_REG_IDR3		      0x0020000cu
+#define IVPU_MMU_REG_IDR5		      0x00200014u
+#define IVPU_MMU_REG_CR0		      0x00200020u
+#define IVPU_MMU_REG_CR0ACK		      0x00200024u
+#define IVPU_MMU_REG_CR0ACK_VAL_MASK	      GENMASK(31, 0)
+#define IVPU_MMU_REG_CR0_ATSCHK_MASK	      BIT(4)
+#define IVPU_MMU_REG_CR0_CMDQEN_MASK	      BIT(3)
+#define IVPU_MMU_REG_CR0_EVTQEN_MASK	      BIT(2)
+#define IVPU_MMU_REG_CR0_PRIQEN_MASK	      BIT(1)
+#define IVPU_MMU_REG_CR0_SMMUEN_MASK	      BIT(0)
+
+#define IVPU_MMU_REG_CR1		      0x00200028u
+#define IVPU_MMU_REG_CR2		      0x0020002cu
+#define IVPU_MMU_REG_IRQ_CTRL		      0x00200050u
+#define IVPU_MMU_REG_IRQ_CTRLACK	      0x00200054u
+#define IVPU_MMU_REG_IRQ_CTRLACK_VAL_MASK     GENMASK(31, 0)
+
+#define IVPU_MMU_REG_GERROR		      0x00200060u
+#define IVPU_MMU_REG_GERROR_CMDQ_MASK	      BIT_MASK(0)
+#define IVPU_MMU_REG_GERROR_EVTQ_ABT_MASK     BIT_MASK(2)
+#define IVPU_MMU_REG_GERROR_PRIQ_ABT_MASK     BIT_MASK(3)
+#define IVPU_MMU_REG_GERROR_MSI_CMDQ_ABT_MASK BIT_MASK(4)
+#define IVPU_MMU_REG_GERROR_MSI_EVTQ_ABT_MASK BIT_MASK(5)
+#define IVPU_MMU_REG_GERROR_MSI_PRIQ_ABT_MASK BIT_MASK(6)
+#define IVPU_MMU_REG_GERROR_MSI_ABT_MASK      BIT_MASK(7)
+
+#define IVPU_MMU_REG_GERRORN		      0x00200064u
+
+#define IVPU_MMU_REG_STRTAB_BASE	      0x00200080u
+#define IVPU_MMU_REG_STRTAB_BASE_CFG	      0x00200088u
+#define IVPU_MMU_REG_CMDQ_BASE		      0x00200090u
+#define IVPU_MMU_REG_CMDQ_PROD		      0x00200098u
+#define IVPU_MMU_REG_CMDQ_CONS		      0x0020009cu
+#define IVPU_MMU_REG_CMDQ_CONS_VAL_MASK	      GENMASK(23, 0)
+#define IVPU_MMU_REG_CMDQ_CONS_ERR_MASK	      GENMASK(30, 24)
+#define IVPU_MMU_REG_EVTQ_BASE		      0x002000a0u
+#define IVPU_MMU_REG_EVTQ_PROD		      0x002000a8u
+#define IVPU_MMU_REG_EVTQ_CONS		      0x002000acu
+#define IVPU_MMU_REG_EVTQ_PROD_SEC	      (0x002000a8u + SZ_64K)
+#define IVPU_MMU_REG_EVTQ_CONS_SEC	      (0x002000acu + SZ_64K)
+
+#define IVPU_MMU_IDR0_REF		0x080f3e0f
+#define IVPU_MMU_IDR0_REF_SIMICS	0x080f3e1f
+#define IVPU_MMU_IDR1_REF		0x0e739d18
+#define IVPU_MMU_IDR3_REF		0x0000003c
+#define IVPU_MMU_IDR5_REF		0x00040070
+#define IVPU_MMU_IDR5_REF_SIMICS	0x00000075
+#define IVPU_MMU_IDR5_REF_FPGA		0x00800075
+
+#define IVPU_MMU_CDTAB_ENT_SIZE		64
+#define IVPU_MMU_CDTAB_ENT_COUNT_LOG2	8 /* 256 entries */
+#define IVPU_MMU_CDTAB_ENT_COUNT	((u32)1 << IVPU_MMU_CDTAB_ENT_COUNT_LOG2)
+
+#define IVPU_MMU_STREAM_ID0		0
+#define IVPU_MMU_STREAM_ID3		3
+
+#define IVPU_MMU_STRTAB_ENT_SIZE	64
+#define IVPU_MMU_STRTAB_ENT_COUNT	4
+#define IVPU_MMU_STRTAB_CFG_LOG2SIZE	2
+#define IVPU_MMU_STRTAB_CFG		IVPU_MMU_STRTAB_CFG_LOG2SIZE
+
+#define IVPU_MMU_Q_COUNT_LOG2		4 /* 16 entries */
+#define IVPU_MMU_Q_COUNT		((u32)1 << IVPU_MMU_Q_COUNT_LOG2)
+#define IVPU_MMU_Q_WRAP_MASK            GENMASK(IVPU_MMU_Q_COUNT_LOG2, 0)
+#define IVPU_MMU_Q_IDX_MASK             (IVPU_MMU_Q_COUNT - 1)
+#define IVPU_MMU_Q_IDX(val)		((val) & IVPU_MMU_Q_IDX_MASK)
+#define IVPU_MMU_Q_WRP(val)             ((val) & IVPU_MMU_Q_COUNT)
+
+#define IVPU_MMU_CMDQ_CMD_SIZE		16
+#define IVPU_MMU_CMDQ_SIZE		(IVPU_MMU_Q_COUNT * IVPU_MMU_CMDQ_CMD_SIZE)
+
+#define IVPU_MMU_EVTQ_CMD_SIZE		32
+#define IVPU_MMU_EVTQ_SIZE		(IVPU_MMU_Q_COUNT * IVPU_MMU_EVTQ_CMD_SIZE)
+
+#define IVPU_MMU_CMD_OPCODE		GENMASK(7, 0)
+
+#define IVPU_MMU_CMD_SYNC_0_CS		GENMASK(13, 12)
+#define IVPU_MMU_CMD_SYNC_0_MSH		GENMASK(23, 22)
+#define IVPU_MMU_CMD_SYNC_0_MSI_ATTR	GENMASK(27, 24)
+#define IVPU_MMU_CMD_SYNC_0_MSI_ATTR	GENMASK(27, 24)
+#define IVPU_MMU_CMD_SYNC_0_MSI_DATA	GENMASK(63, 32)
+
+#define IVPU_MMU_CMD_CFGI_0_SSEC	BIT(10)
+#define IVPU_MMU_CMD_CFGI_0_SSV		BIT(11)
+#define IVPU_MMU_CMD_CFGI_0_SSID	GENMASK(31, 12)
+#define IVPU_MMU_CMD_CFGI_0_SID		GENMASK(63, 32)
+#define IVPU_MMU_CMD_CFGI_1_RANGE	GENMASK(4, 0)
+
+#define IVPU_MMU_CMD_TLBI_0_ASID	GENMASK(63, 48)
+#define IVPU_MMU_CMD_TLBI_0_VMID	GENMASK(47, 32)
+
+#define CMD_PREFETCH_CFG		0x1
+#define CMD_CFGI_STE			0x3
+#define CMD_CFGI_ALL			0x4
+#define CMD_CFGI_CD			0x5
+#define CMD_CFGI_CD_ALL			0x6
+#define CMD_TLBI_NH_ASID		0x11
+#define CMD_TLBI_EL2_ALL		0x20
+#define CMD_TLBI_NSNH_ALL		0x30
+#define CMD_SYNC			0x46
+
+#define IVPU_MMU_EVT_F_UUT		0x01
+#define IVPU_MMU_EVT_C_BAD_STREAMID	0x02
+#define IVPU_MMU_EVT_F_STE_FETCH	0x03
+#define IVPU_MMU_EVT_C_BAD_STE		0x04
+#define IVPU_MMU_EVT_F_BAD_ATS_TREQ	0x05
+#define IVPU_MMU_EVT_F_STREAM_DISABLED	0x06
+#define IVPU_MMU_EVT_F_TRANSL_FORBIDDEN	0x07
+#define IVPU_MMU_EVT_C_BAD_SUBSTREAMID	0x08
+#define IVPU_MMU_EVT_F_CD_FETCH		0x09
+#define IVPU_MMU_EVT_C_BAD_CD		0x0a
+#define IVPU_MMU_EVT_F_WALK_EABT	0x0b
+#define IVPU_MMU_EVT_F_TRANSLATION	0x10
+#define IVPU_MMU_EVT_F_ADDR_SIZE	0x11
+#define IVPU_MMU_EVT_F_ACCESS		0x12
+#define IVPU_MMU_EVT_F_PERMISSION	0x13
+#define IVPU_MMU_EVT_F_TLB_CONFLICT	0x20
+#define IVPU_MMU_EVT_F_CFG_CONFLICT	0x21
+#define IVPU_MMU_EVT_E_PAGE_REQUEST	0x24
+#define IVPU_MMU_EVT_F_VMS_FETCH	0x25
+
+#define IVPU_MMU_EVT_OP_MASK		GENMASK_ULL(7, 0)
+#define IVPU_MMU_EVT_SSID_MASK		GENMASK_ULL(31, 12)
+
+#define IVPU_MMU_Q_BASE_RWA		BIT(62)
+#define IVPU_MMU_Q_BASE_ADDR_MASK	GENMASK_ULL(51, 5)
+#define IVPU_MMU_STRTAB_BASE_RA		BIT(62)
+#define IVPU_MMU_STRTAB_BASE_ADDR_MASK	GENMASK_ULL(51, 6)
+
+#define IVPU_MMU_IRQ_EVTQ_EN		BIT(2)
+#define IVPU_MMU_IRQ_GERROR_EN		BIT(0)
+
+#define IVPU_MMU_CR1_TABLE_SH		GENMASK(11, 10)
+#define IVPU_MMU_CR1_TABLE_OC		GENMASK(9, 8)
+#define IVPU_MMU_CR1_TABLE_IC		GENMASK(7, 6)
+#define IVPU_MMU_CR1_QUEUE_SH		GENMASK(5, 4)
+#define IVPU_MMU_CR1_QUEUE_OC		GENMASK(3, 2)
+#define IVPU_MMU_CR1_QUEUE_IC		GENMASK(1, 0)
+#define IVPU_MMU_CACHE_NC		0
+#define IVPU_MMU_CACHE_WB		1
+#define IVPU_MMU_CACHE_WT		2
+#define IVPU_MMU_SH_NSH			0
+#define IVPU_MMU_SH_OSH			2
+#define IVPU_MMU_SH_ISH			3
+
+#define IVPU_MMU_CMDQ_OP		GENMASK_ULL(7, 0)
+
+#define IVPU_MMU_CD_0_TCR_T0SZ		GENMASK_ULL(5, 0)
+#define IVPU_MMU_CD_0_TCR_TG0		GENMASK_ULL(7, 6)
+#define IVPU_MMU_CD_0_TCR_IRGN0		GENMASK_ULL(9, 8)
+#define IVPU_MMU_CD_0_TCR_ORGN0		GENMASK_ULL(11, 10)
+#define IVPU_MMU_CD_0_TCR_SH0		GENMASK_ULL(13, 12)
+#define IVPU_MMU_CD_0_TCR_EPD0		BIT_ULL(14)
+#define IVPU_MMU_CD_0_TCR_EPD1		BIT_ULL(30)
+#define IVPU_MMU_CD_0_ENDI		BIT(15)
+#define IVPU_MMU_CD_0_V			BIT(31)
+#define IVPU_MMU_CD_0_TCR_IPS		GENMASK_ULL(34, 32)
+#define IVPU_MMU_CD_0_TCR_TBI0		BIT_ULL(38)
+#define IVPU_MMU_CD_0_AA64		BIT(41)
+#define IVPU_MMU_CD_0_S			BIT(44)
+#define IVPU_MMU_CD_0_R			BIT(45)
+#define IVPU_MMU_CD_0_A			BIT(46)
+#define IVPU_MMU_CD_0_ASET		BIT(47)
+#define IVPU_MMU_CD_0_ASID		GENMASK_ULL(63, 48)
+
+#define IVPU_MMU_T0SZ_48BIT             16
+#define IVPU_MMU_T0SZ_38BIT             26
+
+#define IVPU_MMU_IPS_48BIT		5
+#define IVPU_MMU_IPS_44BIT		4
+#define IVPU_MMU_IPS_42BIT		3
+#define IVPU_MMU_IPS_40BIT		2
+#define IVPU_MMU_IPS_36BIT		1
+#define IVPU_MMU_IPS_32BIT		0
+
+#define IVPU_MMU_CD_1_TTB0_MASK		GENMASK_ULL(51, 4)
+
+#define IVPU_MMU_STE_0_S1CDMAX		GENMASK_ULL(63, 59)
+#define IVPU_MMU_STE_0_S1FMT		GENMASK_ULL(5, 4)
+#define IVPU_MMU_STE_0_S1FMT_LINEAR	0
+#define IVPU_MMU_STE_DWORDS		8
+#define IVPU_MMU_STE_0_CFG_S1_TRANS	5
+#define IVPU_MMU_STE_0_CFG		GENMASK_ULL(3, 1)
+#define IVPU_MMU_STE_0_S1CTXPTR_MASK	GENMASK_ULL(51, 6)
+#define IVPU_MMU_STE_0_V			BIT(0)
+
+#define IVPU_MMU_STE_1_STRW_NSEL1	0ul
+#define IVPU_MMU_STE_1_CONT		GENMASK_ULL(16, 13)
+#define IVPU_MMU_STE_1_STRW		GENMASK_ULL(31, 30)
+#define IVPU_MMU_STE_1_PRIVCFG		GENMASK_ULL(49, 48)
+#define IVPU_MMU_STE_1_PRIVCFG_UNPRIV	2ul
+#define IVPU_MMU_STE_1_INSTCFG		GENMASK_ULL(51, 50)
+#define IVPU_MMU_STE_1_INSTCFG_DATA	2ul
+#define IVPU_MMU_STE_1_MEV		BIT(19)
+#define IVPU_MMU_STE_1_S1STALLD		BIT(27)
+#define IVPU_MMU_STE_1_S1C_CACHE_NC	0ul
+#define IVPU_MMU_STE_1_S1C_CACHE_WBRA	1ul
+#define IVPU_MMU_STE_1_S1C_CACHE_WT	2ul
+#define IVPU_MMU_STE_1_S1C_CACHE_WB	3ul
+#define IVPU_MMU_STE_1_S1CIR		GENMASK_ULL(3, 2)
+#define IVPU_MMU_STE_1_S1COR		GENMASK_ULL(5, 4)
+#define IVPU_MMU_STE_1_S1CSH		GENMASK_ULL(7, 6)
+#define IVPU_MMU_STE_1_S1DSS		GENMASK_ULL(1, 0)
+#define IVPU_MMU_STE_1_S1DSS_TERMINATE	0x0
+
+#define IVPU_MMU_REG_TIMEOUT_US		(10 * USEC_PER_MSEC)
+#define IVPU_MMU_QUEUE_TIMEOUT_US	(100 * USEC_PER_MSEC)
+
+#define IVPU_MMU_GERROR_ERR_MASK ((REG_FLD(IVPU_MMU_REG_GERROR, CMDQ)) | \
+				  (REG_FLD(IVPU_MMU_REG_GERROR, EVTQ_ABT)) | \
+				  (REG_FLD(IVPU_MMU_REG_GERROR, PRIQ_ABT)) | \
+				  (REG_FLD(IVPU_MMU_REG_GERROR, MSI_CMDQ_ABT)) | \
+				  (REG_FLD(IVPU_MMU_REG_GERROR, MSI_EVTQ_ABT)) | \
+				  (REG_FLD(IVPU_MMU_REG_GERROR, MSI_PRIQ_ABT)) | \
+				  (REG_FLD(IVPU_MMU_REG_GERROR, MSI_ABT)))
+
+#define IVPU_MMU_CERROR_NONE         0x0
+#define IVPU_MMU_CERROR_ILL          0x1
+#define IVPU_MMU_CERROR_ABT          0x2
+#define IVPU_MMU_CERROR_ATC_INV_SYNC 0x3
+
+static const char *ivpu_mmu_event_to_str(u32 cmd)
+{
+	switch (cmd) {
+	case IVPU_MMU_EVT_F_UUT:
+		return "Unsupported Upstream Transaction";
+	case IVPU_MMU_EVT_C_BAD_STREAMID:
+		return "Transaction StreamID out of range";
+	case IVPU_MMU_EVT_F_STE_FETCH:
+		return "Fetch of STE caused external abort";
+	case IVPU_MMU_EVT_C_BAD_STE:
+		return "Used STE invalid";
+	case IVPU_MMU_EVT_F_BAD_ATS_TREQ:
+		return "Address Request disallowed for a StreamID";
+	case IVPU_MMU_EVT_F_STREAM_DISABLED:
+		return "Transaction marks non-substream disabled";
+	case IVPU_MMU_EVT_F_TRANSL_FORBIDDEN:
+		return "MMU bypass is disallowed for this StreamID";
+	case IVPU_MMU_EVT_C_BAD_SUBSTREAMID:
+		return "Invalid StreamID";
+	case IVPU_MMU_EVT_F_CD_FETCH:
+		return "Fetch of CD caused external abort";
+	case IVPU_MMU_EVT_C_BAD_CD:
+		return "Fetched CD invalid";
+	case IVPU_MMU_EVT_F_WALK_EABT:
+		return " An external abort occurred fetching a TLB";
+	case IVPU_MMU_EVT_F_TRANSLATION:
+		return "Translation fault";
+	case IVPU_MMU_EVT_F_ADDR_SIZE:
+		return " Output address caused address size fault";
+	case IVPU_MMU_EVT_F_ACCESS:
+		return "Access flag fault";
+	case IVPU_MMU_EVT_F_PERMISSION:
+		return "Permission fault occurred on page access";
+	case IVPU_MMU_EVT_F_TLB_CONFLICT:
+		return "A TLB conflict";
+	case IVPU_MMU_EVT_F_CFG_CONFLICT:
+		return "A configuration cache conflict";
+	case IVPU_MMU_EVT_E_PAGE_REQUEST:
+		return "Page request hint from a client device";
+	case IVPU_MMU_EVT_F_VMS_FETCH:
+		return "Fetch of VMS caused external abort";
+	default:
+		return "Unknown event";
+	}
+}
+
+static const char *ivpu_mmu_cmdq_err_to_str(u32 err)
+{
+	switch (err) {
+	case IVPU_MMU_CERROR_NONE:
+		return "No error";
+	case IVPU_MMU_CERROR_ILL:
+		return "Illegal command";
+	case IVPU_MMU_CERROR_ABT:
+		return "External abort on command queue read";
+	case IVPU_MMU_CERROR_ATC_INV_SYNC:
+		return "Sync failed to complete ATS invalidation";
+	default:
+		return "Unknown error";
+	}
+}
+
+static void ivpu_mmu_config_check(struct ivpu_device *vdev)
+{
+	u32 val_ref;
+	u32 val;
+
+	if (ivpu_is_simics(vdev))
+		val_ref = IVPU_MMU_IDR0_REF_SIMICS;
+	else
+		val_ref = IVPU_MMU_IDR0_REF;
+
+	val = REGV_RD32(IVPU_MMU_REG_IDR0);
+	if (val != val_ref)
+		ivpu_dbg(vdev, MMU, "IDR0 0x%x != IDR0_REF 0x%x\n", val, val_ref);
+
+	val = REGV_RD32(IVPU_MMU_REG_IDR1);
+	if (val != IVPU_MMU_IDR1_REF)
+		ivpu_dbg(vdev, MMU, "IDR1 0x%x != IDR1_REF 0x%x\n", val, IVPU_MMU_IDR1_REF);
+
+	val = REGV_RD32(IVPU_MMU_REG_IDR3);
+	if (val != IVPU_MMU_IDR3_REF)
+		ivpu_dbg(vdev, MMU, "IDR3 0x%x != IDR3_REF 0x%x\n", val, IVPU_MMU_IDR3_REF);
+
+	if (ivpu_is_simics(vdev))
+		val_ref = IVPU_MMU_IDR5_REF_SIMICS;
+	else if (ivpu_is_fpga(vdev))
+		val_ref = IVPU_MMU_IDR5_REF_FPGA;
+	else
+		val_ref = IVPU_MMU_IDR5_REF;
+
+	val = REGV_RD32(IVPU_MMU_REG_IDR5);
+	if (val != val_ref)
+		ivpu_dbg(vdev, MMU, "IDR5 0x%x != IDR5_REF 0x%x\n", val, val_ref);
+}
+
+static int ivpu_mmu_cdtab_alloc(struct ivpu_device *vdev)
+{
+	struct ivpu_mmu_info *mmu = vdev->mmu;
+	struct ivpu_mmu_cdtab *cdtab = &mmu->cdtab;
+	size_t size = IVPU_MMU_CDTAB_ENT_COUNT * IVPU_MMU_CDTAB_ENT_SIZE;
+
+	cdtab->base = dmam_alloc_coherent(vdev->drm.dev, size, &cdtab->dma, GFP_KERNEL);
+	if (!cdtab->base)
+		return -ENOMEM;
+
+	ivpu_dbg(vdev, MMU, "CDTAB alloc: dma=%pad size=%zu\n", &cdtab->dma, size);
+
+	return 0;
+}
+
+static int ivpu_mmu_strtab_alloc(struct ivpu_device *vdev)
+{
+	struct ivpu_mmu_info *mmu = vdev->mmu;
+	struct ivpu_mmu_strtab *strtab = &mmu->strtab;
+	size_t size = IVPU_MMU_STRTAB_ENT_COUNT * IVPU_MMU_STRTAB_ENT_SIZE;
+
+	strtab->base = dmam_alloc_coherent(vdev->drm.dev, size, &strtab->dma, GFP_KERNEL);
+	if (!strtab->base)
+		return -ENOMEM;
+
+	strtab->base_cfg = IVPU_MMU_STRTAB_CFG;
+	strtab->dma_q = IVPU_MMU_STRTAB_BASE_RA;
+	strtab->dma_q |= strtab->dma & IVPU_MMU_STRTAB_BASE_ADDR_MASK;
+
+	ivpu_dbg(vdev, MMU, "STRTAB alloc: dma=%pad dma_q=%pad size=%zu\n",
+		 &strtab->dma, &strtab->dma_q, size);
+
+	return 0;
+}
+
+static int ivpu_mmu_cmdq_alloc(struct ivpu_device *vdev)
+{
+	struct ivpu_mmu_info *mmu = vdev->mmu;
+	struct ivpu_mmu_queue *q = &mmu->cmdq;
+
+	q->base = dmam_alloc_coherent(vdev->drm.dev, IVPU_MMU_CMDQ_SIZE, &q->dma, GFP_KERNEL);
+	if (!q->base)
+		return -ENOMEM;
+
+	q->dma_q = IVPU_MMU_Q_BASE_RWA;
+	q->dma_q |= q->dma & IVPU_MMU_Q_BASE_ADDR_MASK;
+	q->dma_q |= IVPU_MMU_Q_COUNT_LOG2;
+
+	ivpu_dbg(vdev, MMU, "CMDQ alloc: dma=%pad dma_q=%pad size=%u\n",
+		 &q->dma, &q->dma_q, IVPU_MMU_CMDQ_SIZE);
+
+	return 0;
+}
+
+static int ivpu_mmu_evtq_alloc(struct ivpu_device *vdev)
+{
+	struct ivpu_mmu_info *mmu = vdev->mmu;
+	struct ivpu_mmu_queue *q = &mmu->evtq;
+
+	q->base = dmam_alloc_coherent(vdev->drm.dev, IVPU_MMU_EVTQ_SIZE, &q->dma, GFP_KERNEL);
+	if (!q->base)
+		return -ENOMEM;
+
+	q->dma_q = IVPU_MMU_Q_BASE_RWA;
+	q->dma_q |= q->dma & IVPU_MMU_Q_BASE_ADDR_MASK;
+	q->dma_q |= IVPU_MMU_Q_COUNT_LOG2;
+
+	ivpu_dbg(vdev, MMU, "EVTQ alloc: dma=%pad dma_q=%pad size=%u\n",
+		 &q->dma, &q->dma_q, IVPU_MMU_EVTQ_SIZE);
+
+	return 0;
+}
+
+static int ivpu_mmu_structs_alloc(struct ivpu_device *vdev)
+{
+	int ret;
+
+	ret = ivpu_mmu_cdtab_alloc(vdev);
+	if (ret) {
+		ivpu_err(vdev, "Failed to allocate cdtab: %d\n", ret);
+		return ret;
+	}
+
+	ret = ivpu_mmu_strtab_alloc(vdev);
+	if (ret) {
+		ivpu_err(vdev, "Failed to allocate strtab: %d\n", ret);
+		return ret;
+	}
+
+	ret = ivpu_mmu_cmdq_alloc(vdev);
+	if (ret) {
+		ivpu_err(vdev, "Failed to allocate cmdq: %d\n", ret);
+		return ret;
+	}
+
+	ret = ivpu_mmu_evtq_alloc(vdev);
+	if (ret)
+		ivpu_err(vdev, "Failed to allocate evtq: %d\n", ret);
+
+	return ret;
+}
+
+static int ivpu_mmu_reg_write_cr0(struct ivpu_device *vdev, u32 val)
+{
+	REGV_WR32(IVPU_MMU_REG_CR0, val);
+
+	return REGV_POLL_FLD(IVPU_MMU_REG_CR0ACK, VAL, val, IVPU_MMU_REG_TIMEOUT_US);
+}
+
+static int ivpu_mmu_reg_write_irq_ctrl(struct ivpu_device *vdev, u32 val)
+{
+	REGV_WR32(IVPU_MMU_REG_IRQ_CTRL, val);
+
+	return REGV_POLL_FLD(IVPU_MMU_REG_IRQ_CTRLACK, VAL, val, IVPU_MMU_REG_TIMEOUT_US);
+}
+
+static int ivpu_mmu_irqs_setup(struct ivpu_device *vdev)
+{
+	u32 irq_ctrl = IVPU_MMU_IRQ_EVTQ_EN | IVPU_MMU_IRQ_GERROR_EN;
+	int ret;
+
+	ret = ivpu_mmu_reg_write_irq_ctrl(vdev, 0);
+	if (ret)
+		return ret;
+
+	return ivpu_mmu_reg_write_irq_ctrl(vdev, irq_ctrl);
+}
+
+static int ivpu_mmu_cmdq_wait_for_cons(struct ivpu_device *vdev)
+{
+	struct ivpu_mmu_queue *cmdq = &vdev->mmu->cmdq;
+	int ret;
+
+	ret = REGV_POLL_FLD(IVPU_MMU_REG_CMDQ_CONS, VAL, cmdq->prod,
+			    IVPU_MMU_QUEUE_TIMEOUT_US);
+	if (ret)
+		return ret;
+
+	cmdq->cons = cmdq->prod;
+
+	return 0;
+}
+
+static bool ivpu_mmu_queue_is_full(struct ivpu_mmu_queue *q)
+{
+	return ((IVPU_MMU_Q_IDX(q->prod) == IVPU_MMU_Q_IDX(q->cons)) &&
+		(IVPU_MMU_Q_WRP(q->prod) != IVPU_MMU_Q_WRP(q->cons)));
+}
+
+static bool ivpu_mmu_queue_is_empty(struct ivpu_mmu_queue *q)
+{
+	return ((IVPU_MMU_Q_IDX(q->prod) == IVPU_MMU_Q_IDX(q->cons)) &&
+		(IVPU_MMU_Q_WRP(q->prod) == IVPU_MMU_Q_WRP(q->cons)));
+}
+
+static int ivpu_mmu_cmdq_cmd_write(struct ivpu_device *vdev, const char *name, u64 data0, u64 data1)
+{
+	struct ivpu_mmu_queue *cmdq = &vdev->mmu->cmdq;
+	u64 *queue_buffer = cmdq->base;
+	int idx = IVPU_MMU_Q_IDX(cmdq->prod) * (IVPU_MMU_CMDQ_CMD_SIZE / sizeof(*queue_buffer));
+
+	if (ivpu_mmu_queue_is_full(cmdq)) {
+		ivpu_err(vdev, "Failed to write MMU CMD %s\n", name);
+		return -EBUSY;
+	}
+
+	queue_buffer[idx] = data0;
+	queue_buffer[idx + 1] = data1;
+	cmdq->prod = (cmdq->prod + 1) & IVPU_MMU_Q_WRAP_MASK;
+
+	ivpu_dbg(vdev, MMU, "CMD write: %s data: 0x%llx 0x%llx\n", name, data0, data1);
+
+	return 0;
+}
+
+static int ivpu_mmu_cmdq_sync(struct ivpu_device *vdev)
+{
+	struct ivpu_mmu_queue *q = &vdev->mmu->cmdq;
+	u64 val;
+	int ret;
+
+	val = FIELD_PREP(IVPU_MMU_CMD_OPCODE, CMD_SYNC);
+
+	ret = ivpu_mmu_cmdq_cmd_write(vdev, "SYNC", val, 0);
+	if (ret)
+		return ret;
+
+	if (!ivpu_is_force_snoop_enabled(vdev))
+		clflush_cache_range(q->base, IVPU_MMU_CMDQ_SIZE);
+	REGV_WR32(IVPU_MMU_REG_CMDQ_PROD, q->prod);
+
+	ret = ivpu_mmu_cmdq_wait_for_cons(vdev);
+	if (ret) {
+		u32 err;
+
+		val = REGV_RD32(IVPU_MMU_REG_CMDQ_CONS);
+		err = REG_GET_FLD(IVPU_MMU_REG_CMDQ_CONS, ERR, val);
+
+		ivpu_err(vdev, "Timed out waiting for MMU consumer: %d, error: %s\n", ret,
+			 ivpu_mmu_cmdq_err_to_str(err));
+		ivpu_hw_diagnose_failure(vdev);
+	}
+
+	return ret;
+}
+
+static int ivpu_mmu_cmdq_write_cfgi_all(struct ivpu_device *vdev)
+{
+	u64 data0 = FIELD_PREP(IVPU_MMU_CMD_OPCODE, CMD_CFGI_ALL);
+	u64 data1 = FIELD_PREP(IVPU_MMU_CMD_CFGI_1_RANGE, 0x1f);
+
+	return ivpu_mmu_cmdq_cmd_write(vdev, "CFGI_ALL", data0, data1);
+}
+
+static int ivpu_mmu_cmdq_write_tlbi_nh_asid(struct ivpu_device *vdev, u16 ssid)
+{
+	u64 val = FIELD_PREP(IVPU_MMU_CMD_OPCODE, CMD_TLBI_NH_ASID) |
+		  FIELD_PREP(IVPU_MMU_CMD_TLBI_0_ASID, ssid);
+
+	return ivpu_mmu_cmdq_cmd_write(vdev, "TLBI_NH_ASID", val, 0);
+}
+
+static int ivpu_mmu_cmdq_write_tlbi_nsnh_all(struct ivpu_device *vdev)
+{
+	u64 val = FIELD_PREP(IVPU_MMU_CMD_OPCODE, CMD_TLBI_NSNH_ALL);
+
+	return ivpu_mmu_cmdq_cmd_write(vdev, "TLBI_NSNH_ALL", val, 0);
+}
+
+static int ivpu_mmu_reset(struct ivpu_device *vdev)
+{
+	struct ivpu_mmu_info *mmu = vdev->mmu;
+	u32 val;
+	int ret;
+
+	memset(mmu->cmdq.base, 0, IVPU_MMU_CMDQ_SIZE);
+	if (!ivpu_is_force_snoop_enabled(vdev))
+		clflush_cache_range(mmu->cmdq.base, IVPU_MMU_CMDQ_SIZE);
+	mmu->cmdq.prod = 0;
+	mmu->cmdq.cons = 0;
+
+	memset(mmu->evtq.base, 0, IVPU_MMU_EVTQ_SIZE);
+	mmu->evtq.prod = 0;
+	mmu->evtq.cons = 0;
+
+	ret = ivpu_mmu_reg_write_cr0(vdev, 0);
+	if (ret)
+		return ret;
+
+	val = FIELD_PREP(IVPU_MMU_CR1_TABLE_SH, IVPU_MMU_SH_ISH) |
+	      FIELD_PREP(IVPU_MMU_CR1_TABLE_OC, IVPU_MMU_CACHE_WB) |
+	      FIELD_PREP(IVPU_MMU_CR1_TABLE_IC, IVPU_MMU_CACHE_WB) |
+	      FIELD_PREP(IVPU_MMU_CR1_QUEUE_SH, IVPU_MMU_SH_ISH) |
+	      FIELD_PREP(IVPU_MMU_CR1_QUEUE_OC, IVPU_MMU_CACHE_WB) |
+	      FIELD_PREP(IVPU_MMU_CR1_QUEUE_IC, IVPU_MMU_CACHE_WB);
+	REGV_WR32(IVPU_MMU_REG_CR1, val);
+
+	REGV_WR64(IVPU_MMU_REG_STRTAB_BASE, mmu->strtab.dma_q);
+	REGV_WR32(IVPU_MMU_REG_STRTAB_BASE_CFG, mmu->strtab.base_cfg);
+
+	REGV_WR64(IVPU_MMU_REG_CMDQ_BASE, mmu->cmdq.dma_q);
+	REGV_WR32(IVPU_MMU_REG_CMDQ_PROD, 0);
+	REGV_WR32(IVPU_MMU_REG_CMDQ_CONS, 0);
+
+	val = REG_SET_FLD(IVPU_MMU_REG_CR0, CMDQEN, 0);
+	ret = ivpu_mmu_reg_write_cr0(vdev, val);
+	if (ret)
+		return ret;
+
+	ret = ivpu_mmu_cmdq_write_cfgi_all(vdev);
+	if (ret)
+		return ret;
+
+	ret = ivpu_mmu_cmdq_write_tlbi_nsnh_all(vdev);
+	if (ret)
+		return ret;
+
+	ret = ivpu_mmu_cmdq_sync(vdev);
+	if (ret)
+		return ret;
+
+	REGV_WR64(IVPU_MMU_REG_EVTQ_BASE, mmu->evtq.dma_q);
+	REGV_WR32(IVPU_MMU_REG_EVTQ_PROD_SEC, 0);
+	REGV_WR32(IVPU_MMU_REG_EVTQ_CONS_SEC, 0);
+
+	val = REG_SET_FLD(IVPU_MMU_REG_CR0, EVTQEN, val);
+	ret = ivpu_mmu_reg_write_cr0(vdev, val);
+	if (ret)
+		return ret;
+
+	val = REG_SET_FLD(IVPU_MMU_REG_CR0, ATSCHK, val);
+	ret = ivpu_mmu_reg_write_cr0(vdev, val);
+	if (ret)
+		return ret;
+
+	ret = ivpu_mmu_irqs_setup(vdev);
+	if (ret)
+		return ret;
+
+	val = REG_SET_FLD(IVPU_MMU_REG_CR0, SMMUEN, val);
+	return ivpu_mmu_reg_write_cr0(vdev, val);
+}
+
+static void ivpu_mmu_strtab_link_cd(struct ivpu_device *vdev, u32 sid)
+{
+	struct ivpu_mmu_info *mmu = vdev->mmu;
+	struct ivpu_mmu_strtab *strtab = &mmu->strtab;
+	struct ivpu_mmu_cdtab *cdtab = &mmu->cdtab;
+	u64 *entry = strtab->base + (sid * IVPU_MMU_STRTAB_ENT_SIZE);
+	u64 str[2];
+
+	str[0] = FIELD_PREP(IVPU_MMU_STE_0_CFG, IVPU_MMU_STE_0_CFG_S1_TRANS) |
+		 FIELD_PREP(IVPU_MMU_STE_0_S1CDMAX, IVPU_MMU_CDTAB_ENT_COUNT_LOG2) |
+		 FIELD_PREP(IVPU_MMU_STE_0_S1FMT, IVPU_MMU_STE_0_S1FMT_LINEAR) |
+		 IVPU_MMU_STE_0_V |
+		 (cdtab->dma & IVPU_MMU_STE_0_S1CTXPTR_MASK);
+
+	str[1] = FIELD_PREP(IVPU_MMU_STE_1_S1DSS, IVPU_MMU_STE_1_S1DSS_TERMINATE) |
+		 FIELD_PREP(IVPU_MMU_STE_1_S1CIR, IVPU_MMU_STE_1_S1C_CACHE_NC) |
+		 FIELD_PREP(IVPU_MMU_STE_1_S1COR, IVPU_MMU_STE_1_S1C_CACHE_NC) |
+		 FIELD_PREP(IVPU_MMU_STE_1_S1CSH, IVPU_MMU_SH_NSH) |
+		 FIELD_PREP(IVPU_MMU_STE_1_PRIVCFG, IVPU_MMU_STE_1_PRIVCFG_UNPRIV) |
+		 FIELD_PREP(IVPU_MMU_STE_1_INSTCFG, IVPU_MMU_STE_1_INSTCFG_DATA) |
+		 FIELD_PREP(IVPU_MMU_STE_1_STRW, IVPU_MMU_STE_1_STRW_NSEL1) |
+		 FIELD_PREP(IVPU_MMU_STE_1_CONT, IVPU_MMU_STRTAB_CFG_LOG2SIZE) |
+		 IVPU_MMU_STE_1_MEV |
+		 IVPU_MMU_STE_1_S1STALLD;
+
+	WRITE_ONCE(entry[1], str[1]);
+	WRITE_ONCE(entry[0], str[0]);
+
+	if (!ivpu_is_force_snoop_enabled(vdev))
+		clflush_cache_range(entry, IVPU_MMU_STRTAB_ENT_SIZE);
+
+	ivpu_dbg(vdev, MMU, "STRTAB write entry (SSID=%u): 0x%llx, 0x%llx\n", sid, str[0], str[1]);
+}
+
+static int ivpu_mmu_strtab_init(struct ivpu_device *vdev)
+{
+	ivpu_mmu_strtab_link_cd(vdev, IVPU_MMU_STREAM_ID0);
+	ivpu_mmu_strtab_link_cd(vdev, IVPU_MMU_STREAM_ID3);
+
+	return 0;
+}
+
+int ivpu_mmu_invalidate_tlb(struct ivpu_device *vdev, u16 ssid)
+{
+	struct ivpu_mmu_info *mmu = vdev->mmu;
+	int ret = 0;
+
+	mutex_lock(&mmu->lock);
+	if (!mmu->on)
+		goto unlock;
+
+	ret = ivpu_mmu_cmdq_write_tlbi_nh_asid(vdev, ssid);
+	if (ret)
+		goto unlock;
+
+	ret = ivpu_mmu_cmdq_sync(vdev);
+unlock:
+	mutex_unlock(&mmu->lock);
+	return ret;
+}
+
+static int ivpu_mmu_cdtab_entry_set(struct ivpu_device *vdev, u32 ssid, u64 cd_dma, bool valid)
+{
+	struct ivpu_mmu_info *mmu = vdev->mmu;
+	struct ivpu_mmu_cdtab *cdtab = &mmu->cdtab;
+	u64 *entry;
+	u64 cd[4];
+	int ret = 0;
+
+	if (ssid > IVPU_MMU_CDTAB_ENT_COUNT)
+		return -EINVAL;
+
+	entry = cdtab->base + (ssid * IVPU_MMU_CDTAB_ENT_SIZE);
+	drm_WARN_ON(&vdev->drm, (entry[0] & IVPU_MMU_CD_0_V) == valid);
+
+	cd[0] = FIELD_PREP(IVPU_MMU_CD_0_TCR_T0SZ, IVPU_MMU_T0SZ_48BIT) |
+		FIELD_PREP(IVPU_MMU_CD_0_TCR_TG0, 0) |
+		FIELD_PREP(IVPU_MMU_CD_0_TCR_IRGN0, 0) |
+		FIELD_PREP(IVPU_MMU_CD_0_TCR_ORGN0, 0) |
+		FIELD_PREP(IVPU_MMU_CD_0_TCR_SH0, 0) |
+		FIELD_PREP(IVPU_MMU_CD_0_TCR_IPS, IVPU_MMU_IPS_48BIT) |
+		FIELD_PREP(IVPU_MMU_CD_0_ASID, ssid) |
+		IVPU_MMU_CD_0_TCR_EPD1 |
+		IVPU_MMU_CD_0_AA64 |
+		IVPU_MMU_CD_0_R |
+		IVPU_MMU_CD_0_ASET;
+	cd[1] = cd_dma & IVPU_MMU_CD_1_TTB0_MASK;
+	cd[2] = 0;
+	cd[3] = 0x0000000000007444;
+
+	/* For global and reserved contexts generate memory fault on VPU */
+	if (ssid == IVPU_GLOBAL_CONTEXT_MMU_SSID || ssid == IVPU_RESERVED_CONTEXT_MMU_SSID)
+		cd[0] |= IVPU_MMU_CD_0_A;
+
+	if (valid)
+		cd[0] |= IVPU_MMU_CD_0_V;
+
+	WRITE_ONCE(entry[1], cd[1]);
+	WRITE_ONCE(entry[2], cd[2]);
+	WRITE_ONCE(entry[3], cd[3]);
+	WRITE_ONCE(entry[0], cd[0]);
+
+	if (!ivpu_is_force_snoop_enabled(vdev))
+		clflush_cache_range(entry, IVPU_MMU_CDTAB_ENT_SIZE);
+
+	ivpu_dbg(vdev, MMU, "CDTAB set %s entry (SSID=%u, dma=%pad): 0x%llx, 0x%llx, 0x%llx, 0x%llx\n",
+		 valid ? "valid" : "invalid", ssid, &cd_dma, cd[0], cd[1], cd[2], cd[3]);
+
+	mutex_lock(&mmu->lock);
+	if (!mmu->on)
+		goto unlock;
+
+	ret = ivpu_mmu_cmdq_write_cfgi_all(vdev);
+	if (ret)
+		goto err_invalidate;
+
+	ret = ivpu_mmu_cmdq_sync(vdev);
+	if (ret)
+		goto err_invalidate;
+unlock:
+	mutex_unlock(&mmu->lock);
+	return 0;
+
+err_invalidate:
+	WRITE_ONCE(entry[0], 0);
+	mutex_unlock(&mmu->lock);
+	return ret;
+}
+
+int ivpu_mmu_init(struct ivpu_device *vdev)
+{
+	struct ivpu_mmu_info *mmu = vdev->mmu;
+	int ret;
+
+	ivpu_dbg(vdev, MMU, "Init..\n");
+
+	ivpu_mmu_config_check(vdev);
+
+	ret = drmm_mutex_init(&vdev->drm, &mmu->lock);
+	if (ret)
+		return ret;
+
+	ret = ivpu_mmu_structs_alloc(vdev);
+	if (ret)
+		return ret;
+
+	ret = ivpu_mmu_strtab_init(vdev);
+	if (ret) {
+		ivpu_err(vdev, "Failed to initialize strtab: %d\n", ret);
+		return ret;
+	}
+
+	ret = ivpu_mmu_enable(vdev);
+	if (ret) {
+		ivpu_err(vdev, "Failed to resume MMU: %d\n", ret);
+		return ret;
+	}
+
+	ivpu_dbg(vdev, MMU, "Init done\n");
+
+	return 0;
+}
+
+int ivpu_mmu_enable(struct ivpu_device *vdev)
+{
+	struct ivpu_mmu_info *mmu = vdev->mmu;
+	int ret;
+
+	mutex_lock(&mmu->lock);
+
+	mmu->on = true;
+
+	ret = ivpu_mmu_reset(vdev);
+	if (ret) {
+		ivpu_err(vdev, "Failed to reset MMU: %d\n", ret);
+		goto err;
+	}
+
+	ret = ivpu_mmu_cmdq_write_cfgi_all(vdev);
+	if (ret)
+		goto err;
+
+	ret = ivpu_mmu_cmdq_write_tlbi_nsnh_all(vdev);
+	if (ret)
+		goto err;
+
+	ret = ivpu_mmu_cmdq_sync(vdev);
+	if (ret)
+		goto err;
+
+	mutex_unlock(&mmu->lock);
+
+	return 0;
+err:
+	mmu->on = false;
+	mutex_unlock(&mmu->lock);
+	return ret;
+}
+
+void ivpu_mmu_disable(struct ivpu_device *vdev)
+{
+	struct ivpu_mmu_info *mmu = vdev->mmu;
+
+	mutex_lock(&mmu->lock);
+	mmu->on = false;
+	mutex_unlock(&mmu->lock);
+}
+
+static void ivpu_mmu_dump_event(struct ivpu_device *vdev, u32 *event)
+{
+	u32 ssid = FIELD_GET(IVPU_MMU_EVT_SSID_MASK, event[0]);
+	u32 op = FIELD_GET(IVPU_MMU_EVT_OP_MASK, event[0]);
+	u64 fetch_addr = ((u64)event[7]) << 32 | event[6];
+	u64 in_addr = ((u64)event[5]) << 32 | event[4];
+	u32 sid = event[1];
+
+	ivpu_err_ratelimited(vdev, "MMU EVTQ: 0x%x (%s) SSID: %d SID: %d, e[2] %08x, e[3] %08x, in addr: 0x%llx, fetch addr: 0x%llx\n",
+			     op, ivpu_mmu_event_to_str(op), ssid, sid,
+			     event[2], event[3], in_addr, fetch_addr);
+}
+
+static u32 *ivpu_mmu_get_event(struct ivpu_device *vdev)
+{
+	struct ivpu_mmu_queue *evtq = &vdev->mmu->evtq;
+	u32 idx = IVPU_MMU_Q_IDX(evtq->cons);
+	u32 *evt = evtq->base + (idx * IVPU_MMU_EVTQ_CMD_SIZE);
+
+	evtq->prod = REGV_RD32(IVPU_MMU_REG_EVTQ_PROD_SEC);
+	if (ivpu_mmu_queue_is_empty(evtq))
+		return NULL;
+
+	evtq->cons = (evtq->cons + 1) & IVPU_MMU_Q_WRAP_MASK;
+	return evt;
+}
+
+static int ivpu_mmu_evtq_set(struct ivpu_device *vdev, bool enable)
+{
+	u32 val = REGV_RD32(IVPU_MMU_REG_CR0);
+
+	if (enable)
+		val = REG_SET_FLD(IVPU_MMU_REG_CR0, EVTQEN, val);
+	else
+		val = REG_CLR_FLD(IVPU_MMU_REG_CR0, EVTQEN, val);
+	REGV_WR32(IVPU_MMU_REG_CR0, val);
+
+	return REGV_POLL_FLD(IVPU_MMU_REG_CR0ACK, VAL, val, IVPU_MMU_REG_TIMEOUT_US);
+}
+
+static int ivpu_mmu_evtq_enable(struct ivpu_device *vdev)
+{
+	return ivpu_mmu_evtq_set(vdev, true);
+}
+
+static int ivpu_mmu_evtq_disable(struct ivpu_device *vdev)
+{
+	return ivpu_mmu_evtq_set(vdev, false);
+}
+
+void ivpu_mmu_discard_events(struct ivpu_device *vdev)
+{
+	struct ivpu_mmu_info *mmu = vdev->mmu;
+
+	mutex_lock(&mmu->lock);
+	/*
+	 * Disable event queue (stop MMU from updating the producer)
+	 * to allow synchronization of consumer and producer indexes
+	 */
+	ivpu_mmu_evtq_disable(vdev);
+
+	vdev->mmu->evtq.cons = REGV_RD32(IVPU_MMU_REG_EVTQ_PROD_SEC);
+	REGV_WR32(IVPU_MMU_REG_EVTQ_CONS_SEC, vdev->mmu->evtq.cons);
+	vdev->mmu->evtq.prod = REGV_RD32(IVPU_MMU_REG_EVTQ_PROD_SEC);
+
+	ivpu_mmu_evtq_enable(vdev);
+
+	drm_WARN_ON_ONCE(&vdev->drm, vdev->mmu->evtq.cons != vdev->mmu->evtq.prod);
+
+	mutex_unlock(&mmu->lock);
+}
+
+int ivpu_mmu_disable_ssid_events(struct ivpu_device *vdev, u32 ssid)
+{
+	struct ivpu_mmu_info *mmu = vdev->mmu;
+	struct ivpu_mmu_cdtab *cdtab = &mmu->cdtab;
+	u64 *entry;
+	u64 val;
+
+	if (ssid > IVPU_MMU_CDTAB_ENT_COUNT)
+		return -EINVAL;
+
+	mutex_lock(&mmu->lock);
+
+	entry = cdtab->base + (ssid * IVPU_MMU_CDTAB_ENT_SIZE);
+
+	val = READ_ONCE(entry[0]);
+	val &= ~IVPU_MMU_CD_0_R;
+	WRITE_ONCE(entry[0], val);
+
+	if (!ivpu_is_force_snoop_enabled(vdev))
+		clflush_cache_range(entry, IVPU_MMU_CDTAB_ENT_SIZE);
+
+	ivpu_mmu_cmdq_write_cfgi_all(vdev);
+	ivpu_mmu_cmdq_sync(vdev);
+
+	mutex_unlock(&mmu->lock);
+
+	return 0;
+}
+
+void ivpu_mmu_irq_evtq_handler(struct ivpu_device *vdev)
+{
+	struct ivpu_file_priv *file_priv;
+	u32 *event;
+	u32 ssid;
+
+	ivpu_dbg(vdev, IRQ, "MMU event queue\n");
+
+	while ((event = ivpu_mmu_get_event(vdev))) {
+		ssid = FIELD_GET(IVPU_MMU_EVT_SSID_MASK, *event);
+		if (ssid == IVPU_GLOBAL_CONTEXT_MMU_SSID ||
+		    ssid == IVPU_RESERVED_CONTEXT_MMU_SSID) {
+			ivpu_mmu_dump_event(vdev, event);
+			ivpu_pm_trigger_recovery(vdev, "MMU event");
+			return;
+		}
+
+		file_priv = xa_load(&vdev->context_xa, ssid);
+		if (file_priv) {
+			if (!READ_ONCE(file_priv->has_mmu_faults)) {
+				ivpu_mmu_dump_event(vdev, event);
+				WRITE_ONCE(file_priv->has_mmu_faults, true);
+			}
+		}
+	}
+
+	queue_work(system_percpu_wq, &vdev->context_abort_work);
+}
+
+void ivpu_mmu_evtq_dump(struct ivpu_device *vdev)
+{
+	u32 *event;
+
+	while ((event = ivpu_mmu_get_event(vdev)) != NULL)
+		ivpu_mmu_dump_event(vdev, event);
+}
+
+void ivpu_mmu_irq_gerr_handler(struct ivpu_device *vdev)
+{
+	u32 gerror_val, gerrorn_val, active;
+
+	ivpu_dbg(vdev, IRQ, "MMU error\n");
+
+	gerror_val = REGV_RD32(IVPU_MMU_REG_GERROR);
+	gerrorn_val = REGV_RD32(IVPU_MMU_REG_GERRORN);
+
+	active = gerror_val ^ gerrorn_val;
+	if (!(active & IVPU_MMU_GERROR_ERR_MASK))
+		return;
+
+	if (REG_TEST_FLD(IVPU_MMU_REG_GERROR, MSI_ABT, active))
+		ivpu_warn_ratelimited(vdev, "MMU MSI ABT write aborted\n");
+
+	if (REG_TEST_FLD(IVPU_MMU_REG_GERROR, MSI_PRIQ_ABT, active))
+		ivpu_warn_ratelimited(vdev, "MMU PRIQ MSI ABT write aborted\n");
+
+	if (REG_TEST_FLD(IVPU_MMU_REG_GERROR, MSI_EVTQ_ABT, active))
+		ivpu_warn_ratelimited(vdev, "MMU EVTQ MSI ABT write aborted\n");
+
+	if (REG_TEST_FLD(IVPU_MMU_REG_GERROR, MSI_CMDQ_ABT, active))
+		ivpu_warn_ratelimited(vdev, "MMU CMDQ MSI ABT write aborted\n");
+
+	if (REG_TEST_FLD(IVPU_MMU_REG_GERROR, PRIQ_ABT, active))
+		ivpu_err_ratelimited(vdev, "MMU PRIQ write aborted\n");
+
+	if (REG_TEST_FLD(IVPU_MMU_REG_GERROR, EVTQ_ABT, active))
+		ivpu_err_ratelimited(vdev, "MMU EVTQ write aborted\n");
+
+	if (REG_TEST_FLD(IVPU_MMU_REG_GERROR, CMDQ, active))
+		ivpu_err_ratelimited(vdev, "MMU CMDQ write aborted\n");
+
+	REGV_WR32(IVPU_MMU_REG_GERRORN, gerror_val);
+}
+
+int ivpu_mmu_cd_set(struct ivpu_device *vdev, int ssid, struct ivpu_mmu_pgtable *pgtable)
+{
+	return ivpu_mmu_cdtab_entry_set(vdev, ssid, pgtable->pgd_dma, true);
+}
+
+void ivpu_mmu_cd_clear(struct ivpu_device *vdev, int ssid)
+{
+	ivpu_mmu_cdtab_entry_set(vdev, ssid, 0, false);
+}
diff --git a/drivers/accel/ivpu/ivpu_mmu.h b/drivers/accel/ivpu/ivpu_mmu.h
new file mode 100644
index 000000000000..1ce7529746ad
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_mmu.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2020-2023 Intel Corporation
+ */
+
+#ifndef __IVPU_MMU_H__
+#define __IVPU_MMU_H__
+
+struct ivpu_device;
+
+struct ivpu_mmu_cdtab {
+	void *base;
+	dma_addr_t dma;
+};
+
+struct ivpu_mmu_strtab {
+	void *base;
+	dma_addr_t dma;
+	u64 dma_q;
+	u32 base_cfg;
+};
+
+struct ivpu_mmu_queue {
+	void *base;
+	dma_addr_t dma;
+	u64 dma_q;
+	u32 prod;
+	u32 cons;
+};
+
+struct ivpu_mmu_info {
+	struct mutex lock; /* Protects cdtab, strtab, cmdq, on */
+	struct ivpu_mmu_cdtab cdtab;
+	struct ivpu_mmu_strtab strtab;
+	struct ivpu_mmu_queue cmdq;
+	struct ivpu_mmu_queue evtq;
+	bool on;
+};
+
+int ivpu_mmu_init(struct ivpu_device *vdev);
+void ivpu_mmu_disable(struct ivpu_device *vdev);
+int ivpu_mmu_enable(struct ivpu_device *vdev);
+int ivpu_mmu_cd_set(struct ivpu_device *vdev, int ssid, struct ivpu_mmu_pgtable *pgtable);
+void ivpu_mmu_cd_clear(struct ivpu_device *vdev, int ssid);
+int ivpu_mmu_invalidate_tlb(struct ivpu_device *vdev, u16 ssid);
+
+void ivpu_mmu_irq_evtq_handler(struct ivpu_device *vdev);
+void ivpu_mmu_irq_gerr_handler(struct ivpu_device *vdev);
+void ivpu_mmu_evtq_dump(struct ivpu_device *vdev);
+void ivpu_mmu_discard_events(struct ivpu_device *vdev);
+int ivpu_mmu_disable_ssid_events(struct ivpu_device *vdev, u32 ssid);
+
+#endif /* __IVPU_MMU_H__ */
diff --git a/drivers/accel/ivpu/ivpu_mmu_context.c b/drivers/accel/ivpu/ivpu_mmu_context.c
new file mode 100644
index 000000000000..87ad593ef47d
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_mmu_context.c
@@ -0,0 +1,640 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020-2023 Intel Corporation
+ */
+
+#include <linux/bitfield.h>
+#include <linux/highmem.h>
+#include <linux/set_memory.h>
+#include <linux/vmalloc.h>
+
+#include <drm/drm_cache.h>
+
+#include "ivpu_drv.h"
+#include "ivpu_hw.h"
+#include "ivpu_mmu.h"
+#include "ivpu_mmu_context.h"
+
+#define IVPU_MMU_VPU_ADDRESS_MASK        GENMASK(47, 12)
+#define IVPU_MMU_PGD_INDEX_MASK          GENMASK(47, 39)
+#define IVPU_MMU_PUD_INDEX_MASK          GENMASK(38, 30)
+#define IVPU_MMU_PMD_INDEX_MASK          GENMASK(29, 21)
+#define IVPU_MMU_PTE_INDEX_MASK          GENMASK(20, 12)
+#define IVPU_MMU_ENTRY_FLAGS_MASK        (BIT(52) | GENMASK(11, 0))
+#define IVPU_MMU_ENTRY_FLAG_CONT         BIT(52)
+#define IVPU_MMU_ENTRY_FLAG_NG           BIT(11)
+#define IVPU_MMU_ENTRY_FLAG_AF           BIT(10)
+#define IVPU_MMU_ENTRY_FLAG_RO           BIT(7)
+#define IVPU_MMU_ENTRY_FLAG_USER         BIT(6)
+#define IVPU_MMU_ENTRY_FLAG_LLC_COHERENT BIT(2)
+#define IVPU_MMU_ENTRY_FLAG_TYPE_PAGE    BIT(1)
+#define IVPU_MMU_ENTRY_FLAG_VALID        BIT(0)
+
+#define IVPU_MMU_PAGE_SIZE       SZ_4K
+#define IVPU_MMU_CONT_PAGES_SIZE (IVPU_MMU_PAGE_SIZE * 16)
+#define IVPU_MMU_PTE_MAP_SIZE    (IVPU_MMU_PGTABLE_ENTRIES * IVPU_MMU_PAGE_SIZE)
+#define IVPU_MMU_PMD_MAP_SIZE    (IVPU_MMU_PGTABLE_ENTRIES * IVPU_MMU_PTE_MAP_SIZE)
+#define IVPU_MMU_PUD_MAP_SIZE    (IVPU_MMU_PGTABLE_ENTRIES * IVPU_MMU_PMD_MAP_SIZE)
+#define IVPU_MMU_PGD_MAP_SIZE    (IVPU_MMU_PGTABLE_ENTRIES * IVPU_MMU_PUD_MAP_SIZE)
+#define IVPU_MMU_PGTABLE_SIZE    (IVPU_MMU_PGTABLE_ENTRIES * sizeof(u64))
+
+#define IVPU_MMU_DUMMY_ADDRESS 0xdeadb000
+#define IVPU_MMU_ENTRY_VALID   (IVPU_MMU_ENTRY_FLAG_TYPE_PAGE | IVPU_MMU_ENTRY_FLAG_VALID)
+#define IVPU_MMU_ENTRY_INVALID (IVPU_MMU_DUMMY_ADDRESS & ~IVPU_MMU_ENTRY_FLAGS_MASK)
+#define IVPU_MMU_ENTRY_MAPPED  (IVPU_MMU_ENTRY_FLAG_AF | IVPU_MMU_ENTRY_FLAG_USER | \
+				IVPU_MMU_ENTRY_FLAG_NG | IVPU_MMU_ENTRY_VALID)
+
+static void *ivpu_pgtable_alloc_page(struct ivpu_device *vdev, dma_addr_t *dma)
+{
+	dma_addr_t dma_addr;
+	struct page *page;
+	void *cpu;
+
+	page = alloc_page(GFP_KERNEL | __GFP_HIGHMEM | __GFP_ZERO);
+	if (!page)
+		return NULL;
+
+	set_pages_array_wc(&page, 1);
+
+	dma_addr = dma_map_page(vdev->drm.dev, page, 0, PAGE_SIZE, DMA_BIDIRECTIONAL);
+	if (dma_mapping_error(vdev->drm.dev, dma_addr))
+		goto err_free_page;
+
+	cpu = vmap(&page, 1, VM_MAP, pgprot_writecombine(PAGE_KERNEL));
+	if (!cpu)
+		goto err_dma_unmap_page;
+
+
+	*dma = dma_addr;
+	return cpu;
+
+err_dma_unmap_page:
+	dma_unmap_page(vdev->drm.dev, dma_addr, PAGE_SIZE, DMA_BIDIRECTIONAL);
+
+err_free_page:
+	put_page(page);
+	return NULL;
+}
+
+static void ivpu_pgtable_free_page(struct ivpu_device *vdev, u64 *cpu_addr, dma_addr_t dma_addr)
+{
+	struct page *page;
+
+	if (cpu_addr) {
+		page = vmalloc_to_page(cpu_addr);
+		vunmap(cpu_addr);
+		dma_unmap_page(vdev->drm.dev, dma_addr & ~IVPU_MMU_ENTRY_FLAGS_MASK, PAGE_SIZE,
+			       DMA_BIDIRECTIONAL);
+		set_pages_array_wb(&page, 1);
+		put_page(page);
+	}
+}
+
+static void ivpu_mmu_pgtables_free(struct ivpu_device *vdev, struct ivpu_mmu_pgtable *pgtable)
+{
+	int pgd_idx, pud_idx, pmd_idx;
+	dma_addr_t pud_dma, pmd_dma, pte_dma;
+	u64 *pud_dma_ptr, *pmd_dma_ptr, *pte_dma_ptr;
+
+	for (pgd_idx = 0; pgd_idx < IVPU_MMU_PGTABLE_ENTRIES; ++pgd_idx) {
+		pud_dma_ptr = pgtable->pud_ptrs[pgd_idx];
+		pud_dma = pgtable->pgd_dma_ptr[pgd_idx];
+
+		if (!pud_dma_ptr)
+			continue;
+
+		for (pud_idx = 0; pud_idx < IVPU_MMU_PGTABLE_ENTRIES; ++pud_idx) {
+			pmd_dma_ptr = pgtable->pmd_ptrs[pgd_idx][pud_idx];
+			pmd_dma = pgtable->pud_ptrs[pgd_idx][pud_idx];
+
+			if (!pmd_dma_ptr)
+				continue;
+
+			for (pmd_idx = 0; pmd_idx < IVPU_MMU_PGTABLE_ENTRIES; ++pmd_idx) {
+				pte_dma_ptr = pgtable->pte_ptrs[pgd_idx][pud_idx][pmd_idx];
+				pte_dma = pgtable->pmd_ptrs[pgd_idx][pud_idx][pmd_idx];
+
+				ivpu_pgtable_free_page(vdev, pte_dma_ptr, pte_dma);
+			}
+
+			kfree(pgtable->pte_ptrs[pgd_idx][pud_idx]);
+			ivpu_pgtable_free_page(vdev, pmd_dma_ptr, pmd_dma);
+		}
+
+		kfree(pgtable->pmd_ptrs[pgd_idx]);
+		kfree(pgtable->pte_ptrs[pgd_idx]);
+		ivpu_pgtable_free_page(vdev, pud_dma_ptr, pud_dma);
+	}
+
+	ivpu_pgtable_free_page(vdev, pgtable->pgd_dma_ptr, pgtable->pgd_dma);
+	pgtable->pgd_dma_ptr = NULL;
+	pgtable->pgd_dma = 0;
+}
+
+static u64*
+ivpu_mmu_ensure_pgd(struct ivpu_device *vdev, struct ivpu_mmu_pgtable *pgtable)
+{
+	u64 *pgd_dma_ptr = pgtable->pgd_dma_ptr;
+	dma_addr_t pgd_dma;
+
+	if (pgd_dma_ptr)
+		return pgd_dma_ptr;
+
+	pgd_dma_ptr = ivpu_pgtable_alloc_page(vdev, &pgd_dma);
+	if (!pgd_dma_ptr)
+		return NULL;
+
+	pgtable->pgd_dma_ptr = pgd_dma_ptr;
+	pgtable->pgd_dma = pgd_dma;
+
+	return pgd_dma_ptr;
+}
+
+static u64*
+ivpu_mmu_ensure_pud(struct ivpu_device *vdev, struct ivpu_mmu_pgtable *pgtable, int pgd_idx)
+{
+	u64 *pud_dma_ptr = pgtable->pud_ptrs[pgd_idx];
+	dma_addr_t pud_dma;
+
+	if (pud_dma_ptr)
+		return pud_dma_ptr;
+
+	pud_dma_ptr = ivpu_pgtable_alloc_page(vdev, &pud_dma);
+	if (!pud_dma_ptr)
+		return NULL;
+
+	drm_WARN_ON(&vdev->drm, pgtable->pmd_ptrs[pgd_idx]);
+	pgtable->pmd_ptrs[pgd_idx] = kzalloc(IVPU_MMU_PGTABLE_SIZE, GFP_KERNEL);
+	if (!pgtable->pmd_ptrs[pgd_idx])
+		goto err_free_pud_dma_ptr;
+
+	drm_WARN_ON(&vdev->drm, pgtable->pte_ptrs[pgd_idx]);
+	pgtable->pte_ptrs[pgd_idx] = kzalloc(IVPU_MMU_PGTABLE_SIZE, GFP_KERNEL);
+	if (!pgtable->pte_ptrs[pgd_idx])
+		goto err_free_pmd_ptrs;
+
+	pgtable->pud_ptrs[pgd_idx] = pud_dma_ptr;
+	pgtable->pgd_dma_ptr[pgd_idx] = pud_dma | IVPU_MMU_ENTRY_VALID;
+
+	return pud_dma_ptr;
+
+err_free_pmd_ptrs:
+	kfree(pgtable->pmd_ptrs[pgd_idx]);
+
+err_free_pud_dma_ptr:
+	ivpu_pgtable_free_page(vdev, pud_dma_ptr, pud_dma);
+	return NULL;
+}
+
+static u64*
+ivpu_mmu_ensure_pmd(struct ivpu_device *vdev, struct ivpu_mmu_pgtable *pgtable, int pgd_idx,
+		    int pud_idx)
+{
+	u64 *pmd_dma_ptr = pgtable->pmd_ptrs[pgd_idx][pud_idx];
+	dma_addr_t pmd_dma;
+
+	if (pmd_dma_ptr)
+		return pmd_dma_ptr;
+
+	pmd_dma_ptr = ivpu_pgtable_alloc_page(vdev, &pmd_dma);
+	if (!pmd_dma_ptr)
+		return NULL;
+
+	drm_WARN_ON(&vdev->drm, pgtable->pte_ptrs[pgd_idx][pud_idx]);
+	pgtable->pte_ptrs[pgd_idx][pud_idx] = kzalloc(IVPU_MMU_PGTABLE_SIZE, GFP_KERNEL);
+	if (!pgtable->pte_ptrs[pgd_idx][pud_idx])
+		goto err_free_pmd_dma_ptr;
+
+	pgtable->pmd_ptrs[pgd_idx][pud_idx] = pmd_dma_ptr;
+	pgtable->pud_ptrs[pgd_idx][pud_idx] = pmd_dma | IVPU_MMU_ENTRY_VALID;
+
+	return pmd_dma_ptr;
+
+err_free_pmd_dma_ptr:
+	ivpu_pgtable_free_page(vdev, pmd_dma_ptr, pmd_dma);
+	return NULL;
+}
+
+static u64*
+ivpu_mmu_ensure_pte(struct ivpu_device *vdev, struct ivpu_mmu_pgtable *pgtable,
+		    int pgd_idx, int pud_idx, int pmd_idx)
+{
+	u64 *pte_dma_ptr = pgtable->pte_ptrs[pgd_idx][pud_idx][pmd_idx];
+	dma_addr_t pte_dma;
+
+	if (pte_dma_ptr)
+		return pte_dma_ptr;
+
+	pte_dma_ptr = ivpu_pgtable_alloc_page(vdev, &pte_dma);
+	if (!pte_dma_ptr)
+		return NULL;
+
+	pgtable->pte_ptrs[pgd_idx][pud_idx][pmd_idx] = pte_dma_ptr;
+	pgtable->pmd_ptrs[pgd_idx][pud_idx][pmd_idx] = pte_dma | IVPU_MMU_ENTRY_VALID;
+
+	return pte_dma_ptr;
+}
+
+static int
+ivpu_mmu_context_map_page(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx,
+			  u64 vpu_addr, dma_addr_t dma_addr, u64 prot)
+{
+	u64 *pte;
+	int pgd_idx = FIELD_GET(IVPU_MMU_PGD_INDEX_MASK, vpu_addr);
+	int pud_idx = FIELD_GET(IVPU_MMU_PUD_INDEX_MASK, vpu_addr);
+	int pmd_idx = FIELD_GET(IVPU_MMU_PMD_INDEX_MASK, vpu_addr);
+	int pte_idx = FIELD_GET(IVPU_MMU_PTE_INDEX_MASK, vpu_addr);
+
+	drm_WARN_ON(&vdev->drm, ctx->id == IVPU_RESERVED_CONTEXT_MMU_SSID);
+
+	/* Allocate PGD - first level page table if needed */
+	if (!ivpu_mmu_ensure_pgd(vdev, &ctx->pgtable))
+		return -ENOMEM;
+
+	/* Allocate PUD - second level page table if needed */
+	if (!ivpu_mmu_ensure_pud(vdev, &ctx->pgtable, pgd_idx))
+		return -ENOMEM;
+
+	/* Allocate PMD - third level page table if needed */
+	if (!ivpu_mmu_ensure_pmd(vdev, &ctx->pgtable, pgd_idx, pud_idx))
+		return -ENOMEM;
+
+	/* Allocate PTE - fourth level page table if needed */
+	pte = ivpu_mmu_ensure_pte(vdev, &ctx->pgtable, pgd_idx, pud_idx, pmd_idx);
+	if (!pte)
+		return -ENOMEM;
+
+	/* Update PTE */
+	pte[pte_idx] = dma_addr | prot;
+
+	return 0;
+}
+
+static int
+ivpu_mmu_context_map_cont_64k(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx, u64 vpu_addr,
+			      dma_addr_t dma_addr, u64 prot)
+{
+	size_t size = IVPU_MMU_CONT_PAGES_SIZE;
+
+	drm_WARN_ON(&vdev->drm, !IS_ALIGNED(vpu_addr, size));
+	drm_WARN_ON(&vdev->drm, !IS_ALIGNED(dma_addr, size));
+
+	prot |= IVPU_MMU_ENTRY_FLAG_CONT;
+
+	while (size) {
+		int ret = ivpu_mmu_context_map_page(vdev, ctx, vpu_addr, dma_addr, prot);
+
+		if (ret)
+			return ret;
+
+		size -= IVPU_MMU_PAGE_SIZE;
+		vpu_addr += IVPU_MMU_PAGE_SIZE;
+		dma_addr += IVPU_MMU_PAGE_SIZE;
+	}
+
+	return 0;
+}
+
+static void ivpu_mmu_context_unmap_page(struct ivpu_mmu_context *ctx, u64 vpu_addr)
+{
+	int pgd_idx = FIELD_GET(IVPU_MMU_PGD_INDEX_MASK, vpu_addr);
+	int pud_idx = FIELD_GET(IVPU_MMU_PUD_INDEX_MASK, vpu_addr);
+	int pmd_idx = FIELD_GET(IVPU_MMU_PMD_INDEX_MASK, vpu_addr);
+	int pte_idx = FIELD_GET(IVPU_MMU_PTE_INDEX_MASK, vpu_addr);
+
+	/* Update PTE with dummy physical address and clear flags */
+	ctx->pgtable.pte_ptrs[pgd_idx][pud_idx][pmd_idx][pte_idx] = IVPU_MMU_ENTRY_INVALID;
+}
+
+static int
+ivpu_mmu_context_map_pages(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx,
+			   u64 vpu_addr, dma_addr_t dma_addr, size_t size, u64 prot)
+{
+	int map_size;
+	int ret;
+
+	while (size) {
+		if (!ivpu_disable_mmu_cont_pages && size >= IVPU_MMU_CONT_PAGES_SIZE &&
+		    IS_ALIGNED(vpu_addr | dma_addr, IVPU_MMU_CONT_PAGES_SIZE)) {
+			ret = ivpu_mmu_context_map_cont_64k(vdev, ctx, vpu_addr, dma_addr, prot);
+			map_size = IVPU_MMU_CONT_PAGES_SIZE;
+		} else {
+			ret = ivpu_mmu_context_map_page(vdev, ctx, vpu_addr, dma_addr, prot);
+			map_size = IVPU_MMU_PAGE_SIZE;
+		}
+
+		if (ret)
+			return ret;
+
+		vpu_addr += map_size;
+		dma_addr += map_size;
+		size -= map_size;
+	}
+
+	return 0;
+}
+
+static void ivpu_mmu_context_set_page_ro(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx,
+					 u64 vpu_addr)
+{
+	int pgd_idx = FIELD_GET(IVPU_MMU_PGD_INDEX_MASK, vpu_addr);
+	int pud_idx = FIELD_GET(IVPU_MMU_PUD_INDEX_MASK, vpu_addr);
+	int pmd_idx = FIELD_GET(IVPU_MMU_PMD_INDEX_MASK, vpu_addr);
+	int pte_idx = FIELD_GET(IVPU_MMU_PTE_INDEX_MASK, vpu_addr);
+
+	ctx->pgtable.pte_ptrs[pgd_idx][pud_idx][pmd_idx][pte_idx] |= IVPU_MMU_ENTRY_FLAG_RO;
+}
+
+static void ivpu_mmu_context_split_page(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx,
+					u64 vpu_addr)
+{
+	int pgd_idx = FIELD_GET(IVPU_MMU_PGD_INDEX_MASK, vpu_addr);
+	int pud_idx = FIELD_GET(IVPU_MMU_PUD_INDEX_MASK, vpu_addr);
+	int pmd_idx = FIELD_GET(IVPU_MMU_PMD_INDEX_MASK, vpu_addr);
+	int pte_idx = FIELD_GET(IVPU_MMU_PTE_INDEX_MASK, vpu_addr);
+
+	ctx->pgtable.pte_ptrs[pgd_idx][pud_idx][pmd_idx][pte_idx] &= ~IVPU_MMU_ENTRY_FLAG_CONT;
+}
+
+static void ivpu_mmu_context_split_64k_page(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx,
+					    u64 vpu_addr)
+{
+	u64 start = ALIGN_DOWN(vpu_addr, IVPU_MMU_CONT_PAGES_SIZE);
+	u64 end = ALIGN(vpu_addr, IVPU_MMU_CONT_PAGES_SIZE);
+	u64 offset = 0;
+
+	ivpu_dbg(vdev, MMU_MAP, "Split 64K page ctx: %u vpu_addr: 0x%llx\n", ctx->id, vpu_addr);
+
+	while (start + offset < end) {
+		ivpu_mmu_context_split_page(vdev, ctx, start + offset);
+		offset += IVPU_MMU_PAGE_SIZE;
+	}
+}
+
+int
+ivpu_mmu_context_set_pages_ro(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx, u64 vpu_addr,
+			      size_t size)
+{
+	u64 end = vpu_addr + size;
+	size_t size_left = size;
+	int ret;
+
+	if (size == 0)
+		return 0;
+
+	if (drm_WARN_ON(&vdev->drm, !IS_ALIGNED(vpu_addr | size, IVPU_MMU_PAGE_SIZE)))
+		return -EINVAL;
+
+	mutex_lock(&ctx->lock);
+
+	ivpu_dbg(vdev, MMU_MAP, "Set read-only pages ctx: %u vpu_addr: 0x%llx size: %lu\n",
+		 ctx->id, vpu_addr, size);
+
+	if (!ivpu_disable_mmu_cont_pages) {
+		/* Split 64K contiguous page at the beginning if needed */
+		if (!IS_ALIGNED(vpu_addr, IVPU_MMU_CONT_PAGES_SIZE))
+			ivpu_mmu_context_split_64k_page(vdev, ctx, vpu_addr);
+
+		/* Split 64K contiguous page at the end if needed */
+		if (!IS_ALIGNED(vpu_addr + size, IVPU_MMU_CONT_PAGES_SIZE))
+			ivpu_mmu_context_split_64k_page(vdev, ctx, vpu_addr + size);
+	}
+
+	while (size_left) {
+		if (vpu_addr < end)
+			ivpu_mmu_context_set_page_ro(vdev, ctx, vpu_addr);
+
+		vpu_addr += IVPU_MMU_PAGE_SIZE;
+		size_left -= IVPU_MMU_PAGE_SIZE;
+	}
+
+	/* Ensure page table modifications are flushed from wc buffers to memory */
+	wmb();
+
+	mutex_unlock(&ctx->lock);
+	ret = ivpu_mmu_invalidate_tlb(vdev, ctx->id);
+	if (ret)
+		ivpu_err(vdev, "Failed to invalidate TLB for ctx %u: %d\n", ctx->id, ret);
+
+	return 0;
+}
+
+static void ivpu_mmu_context_unmap_pages(struct ivpu_mmu_context *ctx, u64 vpu_addr, size_t size)
+{
+	while (size) {
+		ivpu_mmu_context_unmap_page(ctx, vpu_addr);
+		vpu_addr += IVPU_MMU_PAGE_SIZE;
+		size -= IVPU_MMU_PAGE_SIZE;
+	}
+}
+
+int
+ivpu_mmu_context_map_sgt(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx,
+			 u64 vpu_addr, struct sg_table *sgt, bool llc_coherent, bool read_only)
+{
+	size_t start_vpu_addr = vpu_addr;
+	struct scatterlist *sg;
+	int ret;
+	u64 prot;
+	u64 i;
+
+	if (drm_WARN_ON(&vdev->drm, !ctx))
+		return -EINVAL;
+
+	if (!IS_ALIGNED(vpu_addr, IVPU_MMU_PAGE_SIZE))
+		return -EINVAL;
+
+	if (vpu_addr & ~IVPU_MMU_VPU_ADDRESS_MASK)
+		return -EINVAL;
+
+	prot = IVPU_MMU_ENTRY_MAPPED;
+	if (llc_coherent)
+		prot |= IVPU_MMU_ENTRY_FLAG_LLC_COHERENT;
+	if (read_only)
+		prot |= IVPU_MMU_ENTRY_FLAG_RO;
+
+	mutex_lock(&ctx->lock);
+
+	for_each_sgtable_dma_sg(sgt, sg, i) {
+		dma_addr_t dma_addr = sg_dma_address(sg) - sg->offset;
+		size_t size = sg_dma_len(sg) + sg->offset;
+
+		ivpu_dbg(vdev, MMU_MAP, "Map ctx: %u dma_addr: 0x%llx vpu_addr: 0x%llx size: %lu\n",
+			 ctx->id, dma_addr, vpu_addr, size);
+
+		ret = ivpu_mmu_context_map_pages(vdev, ctx, vpu_addr, dma_addr, size, prot);
+		if (ret) {
+			ivpu_err(vdev, "Failed to map context pages\n");
+			goto err_unmap_pages;
+		}
+		vpu_addr += size;
+	}
+
+	if (!ctx->is_cd_valid) {
+		ret = ivpu_mmu_cd_set(vdev, ctx->id, &ctx->pgtable);
+		if (ret) {
+			ivpu_err(vdev, "Failed to set context descriptor for context %u: %d\n",
+				 ctx->id, ret);
+			goto err_unmap_pages;
+		}
+		ctx->is_cd_valid = true;
+	}
+
+	/* Ensure page table modifications are flushed from wc buffers to memory */
+	wmb();
+
+	ret = ivpu_mmu_invalidate_tlb(vdev, ctx->id);
+	if (ret) {
+		ivpu_err(vdev, "Failed to invalidate TLB for ctx %u: %d\n", ctx->id, ret);
+		goto err_unmap_pages;
+	}
+
+	mutex_unlock(&ctx->lock);
+	return 0;
+
+err_unmap_pages:
+	ivpu_mmu_context_unmap_pages(ctx, start_vpu_addr, vpu_addr - start_vpu_addr);
+	mutex_unlock(&ctx->lock);
+	return ret;
+}
+
+void
+ivpu_mmu_context_unmap_sgt(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx,
+			   u64 vpu_addr, struct sg_table *sgt)
+{
+	struct scatterlist *sg;
+	int ret;
+	u64 i;
+
+	if (drm_WARN_ON(&vdev->drm, !ctx))
+		return;
+
+	mutex_lock(&ctx->lock);
+
+	for_each_sgtable_dma_sg(sgt, sg, i) {
+		dma_addr_t dma_addr = sg_dma_address(sg) - sg->offset;
+		size_t size = sg_dma_len(sg) + sg->offset;
+
+		ivpu_dbg(vdev, MMU_MAP, "Unmap ctx: %u dma_addr: 0x%llx vpu_addr: 0x%llx size: %lu\n",
+			 ctx->id, dma_addr, vpu_addr, size);
+
+		ivpu_mmu_context_unmap_pages(ctx, vpu_addr, size);
+		vpu_addr += size;
+	}
+
+	/* Ensure page table modifications are flushed from wc buffers to memory */
+	wmb();
+
+	mutex_unlock(&ctx->lock);
+
+	ret = ivpu_mmu_invalidate_tlb(vdev, ctx->id);
+	if (ret)
+		ivpu_warn_ratelimited(vdev, "Failed to invalidate TLB for ctx %u: %d\n",
+				      ctx->id, ret);
+}
+
+int
+ivpu_mmu_context_insert_node(struct ivpu_mmu_context *ctx, const struct ivpu_addr_range *range,
+			     u64 size, struct drm_mm_node *node)
+{
+	int ret;
+
+	WARN_ON(!range);
+
+	mutex_lock(&ctx->lock);
+	if (!ivpu_disable_mmu_cont_pages && size >= IVPU_MMU_CONT_PAGES_SIZE) {
+		ret = drm_mm_insert_node_in_range(&ctx->mm, node, size, IVPU_MMU_CONT_PAGES_SIZE, 0,
+						  range->start, range->end, DRM_MM_INSERT_BEST);
+		if (!ret)
+			goto unlock;
+	}
+
+	ret = drm_mm_insert_node_in_range(&ctx->mm, node, size, IVPU_MMU_PAGE_SIZE, 0,
+					  range->start, range->end, DRM_MM_INSERT_BEST);
+unlock:
+	mutex_unlock(&ctx->lock);
+	return ret;
+}
+
+void
+ivpu_mmu_context_remove_node(struct ivpu_mmu_context *ctx, struct drm_mm_node *node)
+{
+	mutex_lock(&ctx->lock);
+	drm_mm_remove_node(node);
+	mutex_unlock(&ctx->lock);
+}
+
+void ivpu_mmu_context_init(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx, u32 context_id)
+{
+	u64 start, end;
+
+	mutex_init(&ctx->lock);
+
+	if (!context_id) {
+		start = vdev->hw->ranges.runtime.start;
+		end = vdev->hw->ranges.shave.end;
+	} else {
+		start = min_t(u64, vdev->hw->ranges.user.start, vdev->hw->ranges.shave.start);
+		end = max_t(u64, vdev->hw->ranges.user.end, vdev->hw->ranges.dma.end);
+	}
+
+	drm_mm_init(&ctx->mm, start, end - start);
+	ctx->id = context_id;
+}
+
+void ivpu_mmu_context_fini(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx)
+{
+	if (ctx->is_cd_valid) {
+		ivpu_mmu_cd_clear(vdev, ctx->id);
+		ctx->is_cd_valid = false;
+	}
+
+	mutex_destroy(&ctx->lock);
+	ivpu_mmu_pgtables_free(vdev, &ctx->pgtable);
+	drm_mm_takedown(&ctx->mm);
+}
+
+void ivpu_mmu_global_context_init(struct ivpu_device *vdev)
+{
+	ivpu_mmu_context_init(vdev, &vdev->gctx, IVPU_GLOBAL_CONTEXT_MMU_SSID);
+}
+
+void ivpu_mmu_global_context_fini(struct ivpu_device *vdev)
+{
+	ivpu_mmu_context_fini(vdev, &vdev->gctx);
+}
+
+int ivpu_mmu_reserved_context_init(struct ivpu_device *vdev)
+{
+	int ret;
+
+	ivpu_mmu_context_init(vdev, &vdev->rctx, IVPU_RESERVED_CONTEXT_MMU_SSID);
+
+	mutex_lock(&vdev->rctx.lock);
+
+	if (!ivpu_mmu_ensure_pgd(vdev, &vdev->rctx.pgtable)) {
+		ivpu_err(vdev, "Failed to allocate root page table for reserved context\n");
+		ret = -ENOMEM;
+		goto err_ctx_fini;
+	}
+
+	ret = ivpu_mmu_cd_set(vdev, vdev->rctx.id, &vdev->rctx.pgtable);
+	if (ret) {
+		ivpu_err(vdev, "Failed to set context descriptor for reserved context\n");
+		goto err_ctx_fini;
+	}
+
+	mutex_unlock(&vdev->rctx.lock);
+	return ret;
+
+err_ctx_fini:
+	mutex_unlock(&vdev->rctx.lock);
+	ivpu_mmu_context_fini(vdev, &vdev->rctx);
+	return ret;
+}
+
+void ivpu_mmu_reserved_context_fini(struct ivpu_device *vdev)
+{
+	ivpu_mmu_cd_clear(vdev, vdev->rctx.id);
+	ivpu_mmu_context_fini(vdev, &vdev->rctx);
+}
diff --git a/drivers/accel/ivpu/ivpu_mmu_context.h b/drivers/accel/ivpu/ivpu_mmu_context.h
new file mode 100644
index 000000000000..663a11a9db11
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_mmu_context.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2020-2023 Intel Corporation
+ */
+
+#ifndef __IVPU_MMU_CONTEXT_H__
+#define __IVPU_MMU_CONTEXT_H__
+
+#include <drm/drm_mm.h>
+
+struct ivpu_device;
+struct ivpu_file_priv;
+struct ivpu_addr_range;
+
+#define IVPU_MMU_PGTABLE_ENTRIES	512ull
+
+struct ivpu_mmu_pgtable {
+	u64		***pte_ptrs[IVPU_MMU_PGTABLE_ENTRIES];
+	u64		**pmd_ptrs[IVPU_MMU_PGTABLE_ENTRIES];
+	u64		*pud_ptrs[IVPU_MMU_PGTABLE_ENTRIES];
+	u64		*pgd_dma_ptr;
+	dma_addr_t	pgd_dma;
+};
+
+struct ivpu_mmu_context {
+	struct mutex lock; /* Protects: mm, pgtable, is_cd_valid */
+	struct drm_mm mm;
+	struct ivpu_mmu_pgtable pgtable;
+	bool is_cd_valid;
+	u32 id;
+};
+
+void ivpu_mmu_context_init(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx, u32 context_id);
+void ivpu_mmu_context_fini(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx);
+void ivpu_mmu_global_context_init(struct ivpu_device *vdev);
+void ivpu_mmu_global_context_fini(struct ivpu_device *vdev);
+int ivpu_mmu_reserved_context_init(struct ivpu_device *vdev);
+void ivpu_mmu_reserved_context_fini(struct ivpu_device *vdev);
+
+int ivpu_mmu_context_insert_node(struct ivpu_mmu_context *ctx, const struct ivpu_addr_range *range,
+				 u64 size, struct drm_mm_node *node);
+void ivpu_mmu_context_remove_node(struct ivpu_mmu_context *ctx, struct drm_mm_node *node);
+
+int ivpu_mmu_context_map_sgt(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx,
+			     u64 vpu_addr, struct sg_table *sgt, bool llc_coherent, bool read_only);
+void ivpu_mmu_context_unmap_sgt(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx,
+				u64 vpu_addr, struct sg_table *sgt);
+int ivpu_mmu_context_set_pages_ro(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx,
+				  u64 vpu_addr, size_t size);
+
+#endif /* __IVPU_MMU_CONTEXT_H__ */
diff --git a/drivers/accel/ivpu/ivpu_ms.c b/drivers/accel/ivpu/ivpu_ms.c
new file mode 100644
index 000000000000..1d9c1cb17924
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_ms.c
@@ -0,0 +1,342 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Copyright (C) 2020-2024 Intel Corporation
+ */
+
+#include <drm/drm_file.h>
+#include <linux/pm_runtime.h>
+
+#include "ivpu_drv.h"
+#include "ivpu_gem.h"
+#include "ivpu_hw.h"
+#include "ivpu_jsm_msg.h"
+#include "ivpu_ms.h"
+#include "ivpu_pm.h"
+
+#define MS_INFO_BUFFER_SIZE	  SZ_64K
+#define MS_NUM_BUFFERS		  2
+#define MS_READ_PERIOD_MULTIPLIER 2
+#define MS_MIN_SAMPLE_PERIOD_NS   1000000
+
+static struct ivpu_ms_instance *
+get_instance_by_mask(struct ivpu_file_priv *file_priv, u64 metric_mask)
+{
+	struct ivpu_ms_instance *ms;
+
+	lockdep_assert_held(&file_priv->ms_lock);
+
+	list_for_each_entry(ms, &file_priv->ms_instance_list, ms_instance_node)
+		if (ms->mask == metric_mask)
+			return ms;
+
+	return NULL;
+}
+
+int ivpu_ms_start_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
+{
+	struct ivpu_file_priv *file_priv = file->driver_priv;
+	struct drm_ivpu_metric_streamer_start *args = data;
+	struct ivpu_device *vdev = file_priv->vdev;
+	struct ivpu_ms_instance *ms;
+	u32 sample_size;
+	u64 buf_size;
+	int ret;
+
+	if (!args->metric_group_mask || !args->read_period_samples ||
+	    args->sampling_period_ns < MS_MIN_SAMPLE_PERIOD_NS)
+		return -EINVAL;
+
+	ret = ivpu_rpm_get(vdev);
+	if (ret < 0)
+		return ret;
+
+	mutex_lock(&file_priv->ms_lock);
+
+	if (get_instance_by_mask(file_priv, args->metric_group_mask)) {
+		ivpu_dbg(vdev, IOCTL, "Instance already exists (mask %#llx)\n",
+			 args->metric_group_mask);
+		ret = -EALREADY;
+		goto unlock;
+	}
+
+	ms = kzalloc(sizeof(*ms), GFP_KERNEL);
+	if (!ms) {
+		ret = -ENOMEM;
+		goto unlock;
+	}
+
+	ms->mask = args->metric_group_mask;
+
+	ret = ivpu_jsm_metric_streamer_info(vdev, ms->mask, 0, 0, &sample_size, NULL);
+	if (ret)
+		goto err_free_ms;
+
+	buf_size = PAGE_ALIGN((u64)args->read_period_samples * sample_size *
+			      MS_READ_PERIOD_MULTIPLIER * MS_NUM_BUFFERS);
+	if (buf_size > ivpu_hw_range_size(&vdev->hw->ranges.global)) {
+		ivpu_dbg(vdev, IOCTL, "Requested MS buffer size %llu exceeds range size %llu\n",
+			 buf_size, ivpu_hw_range_size(&vdev->hw->ranges.global));
+		ret = -EINVAL;
+		goto err_free_ms;
+	}
+
+	ms->bo = ivpu_bo_create_global(vdev, buf_size, DRM_IVPU_BO_CACHED | DRM_IVPU_BO_MAPPABLE);
+	if (!ms->bo) {
+		ivpu_dbg(vdev, IOCTL, "Failed to allocate MS buffer (size %llu)\n", buf_size);
+		ret = -ENOMEM;
+		goto err_free_ms;
+	}
+
+	ms->buff_size = ivpu_bo_size(ms->bo) / MS_NUM_BUFFERS;
+	ms->active_buff_vpu_addr = ms->bo->vpu_addr;
+	ms->inactive_buff_vpu_addr = ms->bo->vpu_addr + ms->buff_size;
+	ms->active_buff_ptr = ivpu_bo_vaddr(ms->bo);
+	ms->inactive_buff_ptr = ivpu_bo_vaddr(ms->bo) + ms->buff_size;
+
+	ret = ivpu_jsm_metric_streamer_start(vdev, ms->mask, args->sampling_period_ns,
+					     ms->active_buff_vpu_addr, ms->buff_size);
+	if (ret)
+		goto err_free_bo;
+
+	args->sample_size = sample_size;
+	args->max_data_size = ivpu_bo_size(ms->bo);
+	list_add_tail(&ms->ms_instance_node, &file_priv->ms_instance_list);
+	goto unlock;
+
+err_free_bo:
+	ivpu_bo_free(ms->bo);
+err_free_ms:
+	kfree(ms);
+unlock:
+	mutex_unlock(&file_priv->ms_lock);
+
+	ivpu_rpm_put(vdev);
+	return ret;
+}
+
+static int
+copy_leftover_bytes(struct ivpu_ms_instance *ms,
+		    void __user *user_ptr, u64 user_size, u64 *user_bytes_copied)
+{
+	u64 copy_bytes;
+
+	if (ms->leftover_bytes) {
+		copy_bytes = min(user_size - *user_bytes_copied, ms->leftover_bytes);
+		if (copy_to_user(user_ptr + *user_bytes_copied, ms->leftover_addr, copy_bytes))
+			return -EFAULT;
+
+		ms->leftover_bytes -= copy_bytes;
+		ms->leftover_addr += copy_bytes;
+		*user_bytes_copied += copy_bytes;
+	}
+
+	return 0;
+}
+
+static int
+copy_samples_to_user(struct ivpu_device *vdev, struct ivpu_ms_instance *ms,
+		     void __user *user_ptr, u64 user_size, u64 *user_bytes_copied)
+{
+	u64 bytes_written;
+	int ret;
+
+	*user_bytes_copied = 0;
+
+	ret = copy_leftover_bytes(ms, user_ptr, user_size, user_bytes_copied);
+	if (ret)
+		return ret;
+
+	if (*user_bytes_copied == user_size)
+		return 0;
+
+	ret = ivpu_jsm_metric_streamer_update(vdev, ms->mask, ms->inactive_buff_vpu_addr,
+					      ms->buff_size, &bytes_written);
+	if (ret)
+		return ret;
+
+	swap(ms->active_buff_vpu_addr, ms->inactive_buff_vpu_addr);
+	swap(ms->active_buff_ptr, ms->inactive_buff_ptr);
+
+	ms->leftover_bytes = bytes_written;
+	ms->leftover_addr = ms->inactive_buff_ptr;
+
+	return copy_leftover_bytes(ms, user_ptr, user_size, user_bytes_copied);
+}
+
+int ivpu_ms_get_data_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
+{
+	struct drm_ivpu_metric_streamer_get_data *args = data;
+	struct ivpu_file_priv *file_priv = file->driver_priv;
+	struct ivpu_device *vdev = file_priv->vdev;
+	struct ivpu_ms_instance *ms;
+	u64 bytes_written;
+	int ret;
+
+	if (!args->metric_group_mask)
+		return -EINVAL;
+
+	ret = ivpu_rpm_get(vdev);
+	if (ret < 0)
+		return ret;
+
+	mutex_lock(&file_priv->ms_lock);
+
+	ms = get_instance_by_mask(file_priv, args->metric_group_mask);
+	if (!ms) {
+		ivpu_dbg(vdev, IOCTL, "Instance doesn't exist for mask: %#llx\n",
+			 args->metric_group_mask);
+		ret = -EINVAL;
+		goto unlock;
+	}
+
+	if (!args->buffer_size) {
+		ret = ivpu_jsm_metric_streamer_update(vdev, ms->mask, 0, 0, &bytes_written);
+		if (ret)
+			goto unlock;
+		args->data_size = bytes_written + ms->leftover_bytes;
+		goto unlock;
+	}
+
+	if (!args->buffer_ptr) {
+		ret = -EINVAL;
+		goto unlock;
+	}
+
+	ret = copy_samples_to_user(vdev, ms, u64_to_user_ptr(args->buffer_ptr),
+				   args->buffer_size, &args->data_size);
+unlock:
+	mutex_unlock(&file_priv->ms_lock);
+
+	ivpu_rpm_put(vdev);
+	return ret;
+}
+
+static void free_instance(struct ivpu_file_priv *file_priv, struct ivpu_ms_instance *ms)
+{
+	lockdep_assert_held(&file_priv->ms_lock);
+
+	list_del(&ms->ms_instance_node);
+	ivpu_jsm_metric_streamer_stop(file_priv->vdev, ms->mask);
+	ivpu_bo_free(ms->bo);
+	kfree(ms);
+}
+
+int ivpu_ms_stop_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
+{
+	struct ivpu_file_priv *file_priv = file->driver_priv;
+	struct drm_ivpu_metric_streamer_stop *args = data;
+	struct ivpu_device *vdev = file_priv->vdev;
+	struct ivpu_ms_instance *ms;
+	int ret;
+
+	if (!args->metric_group_mask)
+		return -EINVAL;
+
+	ret = ivpu_rpm_get(vdev);
+	if (ret < 0)
+		return ret;
+
+	mutex_lock(&file_priv->ms_lock);
+
+	ms = get_instance_by_mask(file_priv, args->metric_group_mask);
+	if (ms)
+		free_instance(file_priv, ms);
+
+	mutex_unlock(&file_priv->ms_lock);
+
+	ivpu_rpm_put(vdev);
+	return ms ? 0 : -EINVAL;
+}
+
+static inline struct ivpu_bo *get_ms_info_bo(struct ivpu_file_priv *file_priv)
+{
+	lockdep_assert_held(&file_priv->ms_lock);
+
+	if (file_priv->ms_info_bo)
+		return file_priv->ms_info_bo;
+
+	file_priv->ms_info_bo = ivpu_bo_create_global(file_priv->vdev, MS_INFO_BUFFER_SIZE,
+						      DRM_IVPU_BO_CACHED | DRM_IVPU_BO_MAPPABLE);
+	return file_priv->ms_info_bo;
+}
+
+int ivpu_ms_get_info_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
+{
+	struct drm_ivpu_metric_streamer_get_data *args = data;
+	struct ivpu_file_priv *file_priv = file->driver_priv;
+	struct ivpu_device *vdev = file_priv->vdev;
+	struct ivpu_bo *bo;
+	u64 info_size;
+	int ret;
+
+	if (!args->metric_group_mask)
+		return -EINVAL;
+
+	if (!args->buffer_size)
+		return ivpu_jsm_metric_streamer_info(vdev, args->metric_group_mask,
+						     0, 0, NULL, &args->data_size);
+	if (!args->buffer_ptr)
+		return -EINVAL;
+
+	mutex_lock(&file_priv->ms_lock);
+
+	bo = get_ms_info_bo(file_priv);
+	if (!bo) {
+		ret = -ENOMEM;
+		goto unlock;
+	}
+
+	ret = ivpu_jsm_metric_streamer_info(vdev, args->metric_group_mask, bo->vpu_addr,
+					    ivpu_bo_size(bo), NULL, &info_size);
+	if (ret)
+		goto unlock;
+
+	if (args->buffer_size < info_size) {
+		ret = -ENOSPC;
+		goto unlock;
+	}
+
+	if (copy_to_user(u64_to_user_ptr(args->buffer_ptr), ivpu_bo_vaddr(bo), info_size))
+		ret = -EFAULT;
+
+	args->data_size = info_size;
+unlock:
+	mutex_unlock(&file_priv->ms_lock);
+
+	return ret;
+}
+
+void ivpu_ms_cleanup(struct ivpu_file_priv *file_priv)
+{
+	struct ivpu_ms_instance *ms, *tmp;
+	struct ivpu_device *vdev = file_priv->vdev;
+
+	pm_runtime_get_sync(vdev->drm.dev);
+
+	mutex_lock(&file_priv->ms_lock);
+
+	if (file_priv->ms_info_bo) {
+		ivpu_bo_free(file_priv->ms_info_bo);
+		file_priv->ms_info_bo = NULL;
+	}
+
+	list_for_each_entry_safe(ms, tmp, &file_priv->ms_instance_list, ms_instance_node)
+		free_instance(file_priv, ms);
+
+	mutex_unlock(&file_priv->ms_lock);
+
+	pm_runtime_put_autosuspend(vdev->drm.dev);
+}
+
+void ivpu_ms_cleanup_all(struct ivpu_device *vdev)
+{
+	struct ivpu_file_priv *file_priv;
+	unsigned long ctx_id;
+
+	mutex_lock(&vdev->context_list_lock);
+
+	xa_for_each(&vdev->context_xa, ctx_id, file_priv)
+		ivpu_ms_cleanup(file_priv);
+
+	mutex_unlock(&vdev->context_list_lock);
+}
diff --git a/drivers/accel/ivpu/ivpu_ms.h b/drivers/accel/ivpu/ivpu_ms.h
new file mode 100644
index 000000000000..fbd5ebebc3d9
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_ms.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+/*
+ * Copyright (C) 2020-2024 Intel Corporation
+ */
+#ifndef __IVPU_MS_H__
+#define __IVPU_MS_H__
+
+#include <linux/list.h>
+
+struct drm_device;
+struct drm_file;
+struct ivpu_bo;
+struct ivpu_device;
+struct ivpu_file_priv;
+
+struct ivpu_ms_instance {
+	struct ivpu_bo *bo;
+	struct list_head ms_instance_node;
+	u64 mask;
+	u64 buff_size;
+	u64 active_buff_vpu_addr;
+	u64 inactive_buff_vpu_addr;
+	void *active_buff_ptr;
+	void *inactive_buff_ptr;
+	u64 leftover_bytes;
+	void *leftover_addr;
+};
+
+int ivpu_ms_start_ioctl(struct drm_device *dev, void *data, struct drm_file *file);
+int ivpu_ms_stop_ioctl(struct drm_device *dev, void *data, struct drm_file *file);
+int ivpu_ms_get_data_ioctl(struct drm_device *dev, void *data, struct drm_file *file);
+int ivpu_ms_get_info_ioctl(struct drm_device *dev, void *data, struct drm_file *file);
+void ivpu_ms_cleanup(struct ivpu_file_priv *file_priv);
+void ivpu_ms_cleanup_all(struct ivpu_device *vdev);
+
+#endif /* __IVPU_MS_H__ */
diff --git a/drivers/accel/ivpu/ivpu_pm.c b/drivers/accel/ivpu/ivpu_pm.c
new file mode 100644
index 000000000000..480c075d87f6
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_pm.c
@@ -0,0 +1,511 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020-2024 Intel Corporation
+ */
+
+#include <linux/highmem.h>
+#include <linux/moduleparam.h>
+#include <linux/pci.h>
+#include <linux/pm_runtime.h>
+#include <linux/reboot.h>
+
+#include "ivpu_coredump.h"
+#include "ivpu_drv.h"
+#include "ivpu_fw.h"
+#include "ivpu_fw_log.h"
+#include "ivpu_hw.h"
+#include "ivpu_ipc.h"
+#include "ivpu_job.h"
+#include "ivpu_jsm_msg.h"
+#include "ivpu_mmu.h"
+#include "ivpu_ms.h"
+#include "ivpu_pm.h"
+#include "ivpu_trace.h"
+#include "vpu_boot_api.h"
+
+static bool ivpu_disable_recovery;
+#if IS_ENABLED(CONFIG_DRM_ACCEL_IVPU_DEBUG)
+module_param_named_unsafe(disable_recovery, ivpu_disable_recovery, bool, 0644);
+MODULE_PARM_DESC(disable_recovery, "Disables recovery when NPU hang is detected");
+#endif
+
+static unsigned long ivpu_tdr_timeout_ms;
+module_param_named(tdr_timeout_ms, ivpu_tdr_timeout_ms, ulong, 0644);
+MODULE_PARM_DESC(tdr_timeout_ms, "Timeout for device hang detection, in milliseconds, 0 - default");
+
+static unsigned long ivpu_inference_timeout_ms;
+module_param_named(inference_timeout_ms, ivpu_inference_timeout_ms, ulong, 0644);
+MODULE_PARM_DESC(inference_timeout_ms, "Inference maximum duration, in milliseconds, 0 - default");
+
+#define PM_RESCHEDULE_LIMIT     5
+
+static void ivpu_pm_prepare_cold_boot(struct ivpu_device *vdev)
+{
+	struct ivpu_fw_info *fw = vdev->fw;
+
+	ivpu_cmdq_reset_all_contexts(vdev);
+	ivpu_ipc_reset(vdev);
+	ivpu_fw_log_reset(vdev);
+	ivpu_fw_load(vdev);
+	fw->entry_point = fw->cold_boot_entry_point;
+	fw->last_heartbeat = 0;
+}
+
+static void ivpu_pm_prepare_warm_boot(struct ivpu_device *vdev)
+{
+	struct ivpu_fw_info *fw = vdev->fw;
+	struct vpu_boot_params *bp = ivpu_bo_vaddr(fw->mem_bp);
+
+	if (!bp->save_restore_ret_address) {
+		ivpu_pm_prepare_cold_boot(vdev);
+		return;
+	}
+
+	ivpu_dbg(vdev, FW_BOOT, "Save/restore entry point %llx", bp->save_restore_ret_address);
+	fw->entry_point = bp->save_restore_ret_address;
+}
+
+static int ivpu_suspend(struct ivpu_device *vdev)
+{
+	int ret;
+
+	ivpu_prepare_for_reset(vdev);
+
+	ret = ivpu_shutdown(vdev);
+	if (ret)
+		ivpu_err(vdev, "Failed to shutdown NPU: %d\n", ret);
+
+	return ret;
+}
+
+static int ivpu_resume(struct ivpu_device *vdev)
+{
+	int ret;
+
+retry:
+	pci_set_power_state(to_pci_dev(vdev->drm.dev), PCI_D0);
+	pci_restore_state(to_pci_dev(vdev->drm.dev));
+
+	ret = ivpu_hw_power_up(vdev);
+	if (ret) {
+		ivpu_err(vdev, "Failed to power up HW: %d\n", ret);
+		goto err_power_down;
+	}
+
+	ret = ivpu_mmu_enable(vdev);
+	if (ret) {
+		ivpu_err(vdev, "Failed to resume MMU: %d\n", ret);
+		goto err_power_down;
+	}
+
+	ret = ivpu_boot(vdev);
+	if (ret)
+		goto err_mmu_disable;
+
+	return 0;
+
+err_mmu_disable:
+	ivpu_mmu_disable(vdev);
+err_power_down:
+	ivpu_hw_power_down(vdev);
+	pci_set_power_state(to_pci_dev(vdev->drm.dev), PCI_D3hot);
+
+	if (!ivpu_fw_is_cold_boot(vdev)) {
+		ivpu_pm_prepare_cold_boot(vdev);
+		goto retry;
+	} else {
+		ivpu_err(vdev, "Failed to resume the FW: %d\n", ret);
+	}
+
+	return ret;
+}
+
+static void ivpu_pm_reset_begin(struct ivpu_device *vdev)
+{
+	pm_runtime_disable(vdev->drm.dev);
+
+	atomic_inc(&vdev->pm->reset_counter);
+	atomic_set(&vdev->pm->reset_pending, 1);
+	down_write(&vdev->pm->reset_lock);
+}
+
+static void ivpu_pm_reset_complete(struct ivpu_device *vdev)
+{
+	int ret;
+
+	ivpu_pm_prepare_cold_boot(vdev);
+	ivpu_jobs_abort_all(vdev);
+	ivpu_ms_cleanup_all(vdev);
+
+	ret = ivpu_resume(vdev);
+	if (ret) {
+		ivpu_err(vdev, "Failed to resume NPU: %d\n", ret);
+		pm_runtime_set_suspended(vdev->drm.dev);
+	} else {
+		pm_runtime_set_active(vdev->drm.dev);
+	}
+
+	up_write(&vdev->pm->reset_lock);
+	atomic_set(&vdev->pm->reset_pending, 0);
+
+	pm_runtime_mark_last_busy(vdev->drm.dev);
+	pm_runtime_enable(vdev->drm.dev);
+}
+
+static void ivpu_pm_recovery_work(struct work_struct *work)
+{
+	struct ivpu_pm_info *pm = container_of(work, struct ivpu_pm_info, recovery_work);
+	struct ivpu_device *vdev = pm->vdev;
+	char *evt[2] = {"IVPU_PM_EVENT=IVPU_RECOVER", NULL};
+
+	ivpu_err(vdev, "Recovering the NPU (reset #%d)\n", atomic_read(&vdev->pm->reset_counter));
+
+	ivpu_pm_reset_begin(vdev);
+
+	if (!pm_runtime_status_suspended(vdev->drm.dev)) {
+		ivpu_jsm_state_dump(vdev);
+		ivpu_dev_coredump(vdev);
+		ivpu_suspend(vdev);
+	}
+
+	ivpu_pm_reset_complete(vdev);
+
+	kobject_uevent_env(&vdev->drm.dev->kobj, KOBJ_CHANGE, evt);
+}
+
+void ivpu_pm_trigger_recovery(struct ivpu_device *vdev, const char *reason)
+{
+	ivpu_err(vdev, "Recovery triggered by %s\n", reason);
+
+	if (ivpu_disable_recovery) {
+		ivpu_err(vdev, "Recovery not available when disable_recovery param is set\n");
+		return;
+	}
+
+	/* Trigger recovery if it's not in progress */
+	if (atomic_cmpxchg(&vdev->pm->reset_pending, 0, 1) == 0) {
+		ivpu_hw_diagnose_failure(vdev);
+		ivpu_hw_irq_disable(vdev); /* Disable IRQ early to protect from IRQ storm */
+		queue_work(system_dfl_wq, &vdev->pm->recovery_work);
+	}
+}
+
+static void ivpu_job_timeout_work(struct work_struct *work)
+{
+	struct ivpu_pm_info *pm = container_of(work, struct ivpu_pm_info, job_timeout_work.work);
+	struct ivpu_device *vdev = pm->vdev;
+	unsigned long timeout_ms = ivpu_tdr_timeout_ms ? ivpu_tdr_timeout_ms : vdev->timeout.tdr;
+	unsigned long inference_timeout_ms = ivpu_inference_timeout_ms ? ivpu_inference_timeout_ms :
+					     vdev->timeout.inference;
+	u64 inference_max_retries;
+	u64 heartbeat;
+
+	if (ivpu_jsm_get_heartbeat(vdev, 0, &heartbeat) || heartbeat <= vdev->fw->last_heartbeat) {
+		ivpu_err(vdev, "Job timeout detected, heartbeat not progressed\n");
+		goto recovery;
+	}
+
+	inference_max_retries = DIV_ROUND_UP(inference_timeout_ms, timeout_ms);
+	if (atomic_fetch_inc(&vdev->job_timeout_counter) >= inference_max_retries) {
+		ivpu_err(vdev, "Job timeout detected, heartbeat limit (%lld) exceeded\n",
+			 inference_max_retries);
+		goto recovery;
+	}
+
+	vdev->fw->last_heartbeat = heartbeat;
+	ivpu_start_job_timeout_detection(vdev);
+	return;
+
+recovery:
+	atomic_set(&vdev->job_timeout_counter, 0);
+	ivpu_pm_trigger_recovery(vdev, "TDR");
+}
+
+void ivpu_start_job_timeout_detection(struct ivpu_device *vdev)
+{
+	unsigned long timeout_ms = ivpu_tdr_timeout_ms ? ivpu_tdr_timeout_ms : vdev->timeout.tdr;
+
+	/* No-op if already queued */
+	queue_delayed_work(system_percpu_wq, &vdev->pm->job_timeout_work,
+			   msecs_to_jiffies(timeout_ms));
+}
+
+void ivpu_stop_job_timeout_detection(struct ivpu_device *vdev)
+{
+	cancel_delayed_work_sync(&vdev->pm->job_timeout_work);
+	atomic_set(&vdev->job_timeout_counter, 0);
+}
+
+int ivpu_pm_suspend_cb(struct device *dev)
+{
+	struct drm_device *drm = dev_get_drvdata(dev);
+	struct ivpu_device *vdev = to_ivpu_device(drm);
+	unsigned long timeout;
+
+	trace_pm("suspend");
+	ivpu_dbg(vdev, PM, "Suspend..\n");
+
+	timeout = jiffies + msecs_to_jiffies(vdev->timeout.tdr);
+	while (!ivpu_hw_is_idle(vdev)) {
+		cond_resched();
+		if (time_after_eq(jiffies, timeout)) {
+			ivpu_err(vdev, "Failed to enter idle on system suspend\n");
+			return -EBUSY;
+		}
+	}
+
+	ivpu_jsm_pwr_d0i3_enter(vdev);
+
+	ivpu_suspend(vdev);
+	ivpu_pm_prepare_warm_boot(vdev);
+
+	ivpu_dbg(vdev, PM, "Suspend done.\n");
+	trace_pm("suspend done");
+
+	return 0;
+}
+
+int ivpu_pm_resume_cb(struct device *dev)
+{
+	struct drm_device *drm = dev_get_drvdata(dev);
+	struct ivpu_device *vdev = to_ivpu_device(drm);
+	int ret;
+
+	trace_pm("resume");
+	ivpu_dbg(vdev, PM, "Resume..\n");
+
+	ret = ivpu_resume(vdev);
+	if (ret)
+		ivpu_err(vdev, "Failed to resume: %d\n", ret);
+
+	ivpu_dbg(vdev, PM, "Resume done.\n");
+	trace_pm("resume done");
+
+	return ret;
+}
+
+int ivpu_pm_runtime_suspend_cb(struct device *dev)
+{
+	struct drm_device *drm = dev_get_drvdata(dev);
+	struct ivpu_device *vdev = to_ivpu_device(drm);
+	int ret, ret_d0i3;
+	bool is_idle;
+
+	drm_WARN_ON(&vdev->drm, !xa_empty(&vdev->submitted_jobs_xa));
+	drm_WARN_ON(&vdev->drm, work_pending(&vdev->pm->recovery_work));
+
+	trace_pm("runtime suspend");
+	ivpu_dbg(vdev, PM, "Runtime suspend..\n");
+
+	ivpu_mmu_disable(vdev);
+
+	is_idle = ivpu_hw_is_idle(vdev) || vdev->pm->dct_active_percent;
+	if (!is_idle)
+		ivpu_err(vdev, "NPU is not idle before autosuspend\n");
+
+	ret_d0i3 = ivpu_jsm_pwr_d0i3_enter(vdev);
+	if (ret_d0i3)
+		ivpu_err(vdev, "Failed to prepare for d0i3: %d\n", ret_d0i3);
+
+	ret = ivpu_suspend(vdev);
+	if (ret)
+		ivpu_err(vdev, "Failed to suspend NPU: %d\n", ret);
+
+	if (!is_idle || ret_d0i3) {
+		ivpu_err(vdev, "Forcing cold boot due to previous errors\n");
+		atomic_inc(&vdev->pm->reset_counter);
+		ivpu_dev_coredump(vdev);
+		ivpu_pm_prepare_cold_boot(vdev);
+	} else {
+		ivpu_pm_prepare_warm_boot(vdev);
+	}
+
+	ivpu_dbg(vdev, PM, "Runtime suspend done.\n");
+	trace_pm("runtime suspend done");
+
+	return 0;
+}
+
+int ivpu_pm_runtime_resume_cb(struct device *dev)
+{
+	struct drm_device *drm = dev_get_drvdata(dev);
+	struct ivpu_device *vdev = to_ivpu_device(drm);
+	int ret;
+
+	trace_pm("runtime resume");
+	ivpu_dbg(vdev, PM, "Runtime resume..\n");
+
+	ret = ivpu_resume(vdev);
+	if (ret)
+		ivpu_err(vdev, "Failed to set RESUME state: %d\n", ret);
+
+	ivpu_dbg(vdev, PM, "Runtime resume done.\n");
+	trace_pm("runtime resume done");
+
+	return ret;
+}
+
+int ivpu_rpm_get(struct ivpu_device *vdev)
+{
+	int ret;
+
+	ret = pm_runtime_resume_and_get(vdev->drm.dev);
+	if (ret < 0) {
+		ivpu_err(vdev, "Failed to resume NPU: %d\n", ret);
+		pm_runtime_set_suspended(vdev->drm.dev);
+	}
+
+	return ret;
+}
+
+void ivpu_rpm_put(struct ivpu_device *vdev)
+{
+	pm_runtime_put_autosuspend(vdev->drm.dev);
+}
+
+void ivpu_pm_reset_prepare_cb(struct pci_dev *pdev)
+{
+	struct ivpu_device *vdev = pci_get_drvdata(pdev);
+
+	ivpu_dbg(vdev, PM, "Pre-reset..\n");
+
+	ivpu_pm_reset_begin(vdev);
+
+	if (!pm_runtime_status_suspended(vdev->drm.dev)) {
+		ivpu_prepare_for_reset(vdev);
+		ivpu_hw_reset(vdev);
+	}
+
+	ivpu_dbg(vdev, PM, "Pre-reset done.\n");
+}
+
+void ivpu_pm_reset_done_cb(struct pci_dev *pdev)
+{
+	struct ivpu_device *vdev = pci_get_drvdata(pdev);
+
+	ivpu_dbg(vdev, PM, "Post-reset..\n");
+
+	ivpu_pm_reset_complete(vdev);
+
+	ivpu_dbg(vdev, PM, "Post-reset done.\n");
+}
+
+void ivpu_pm_init(struct ivpu_device *vdev)
+{
+	struct device *dev = vdev->drm.dev;
+	struct ivpu_pm_info *pm = vdev->pm;
+	int delay;
+
+	pm->vdev = vdev;
+
+	init_rwsem(&pm->reset_lock);
+	atomic_set(&pm->reset_pending, 0);
+	atomic_set(&pm->reset_counter, 0);
+
+	INIT_WORK(&pm->recovery_work, ivpu_pm_recovery_work);
+	INIT_DELAYED_WORK(&pm->job_timeout_work, ivpu_job_timeout_work);
+
+	if (ivpu_disable_recovery)
+		delay = -1;
+	else
+		delay = vdev->timeout.autosuspend;
+
+	pm_runtime_use_autosuspend(dev);
+	pm_runtime_set_autosuspend_delay(dev, delay);
+	pm_runtime_set_active(dev);
+
+	ivpu_dbg(vdev, PM, "Autosuspend delay = %d\n", delay);
+}
+
+void ivpu_pm_disable_recovery(struct ivpu_device *vdev)
+{
+	drm_WARN_ON(&vdev->drm, delayed_work_pending(&vdev->pm->job_timeout_work));
+	disable_work_sync(&vdev->pm->recovery_work);
+}
+
+void ivpu_pm_enable(struct ivpu_device *vdev)
+{
+	struct device *dev = vdev->drm.dev;
+
+	pm_runtime_allow(dev);
+	pm_runtime_put_autosuspend(dev);
+}
+
+void ivpu_pm_disable(struct ivpu_device *vdev)
+{
+	pm_runtime_get_noresume(vdev->drm.dev);
+	pm_runtime_forbid(vdev->drm.dev);
+}
+
+int ivpu_pm_dct_init(struct ivpu_device *vdev)
+{
+	if (vdev->pm->dct_active_percent)
+		return ivpu_pm_dct_enable(vdev, vdev->pm->dct_active_percent);
+
+	return 0;
+}
+
+int ivpu_pm_dct_enable(struct ivpu_device *vdev, u8 active_percent)
+{
+	u32 active_us, inactive_us;
+	int ret;
+
+	if (active_percent == 0 || active_percent > 100)
+		return -EINVAL;
+
+	active_us = (DCT_PERIOD_US * active_percent) / 100;
+	inactive_us = DCT_PERIOD_US - active_us;
+
+	vdev->pm->dct_active_percent = active_percent;
+
+	ivpu_dbg(vdev, PM, "DCT requested %u%% (D0: %uus, D0i2: %uus)\n",
+		 active_percent, active_us, inactive_us);
+
+	ret = ivpu_jsm_dct_enable(vdev, active_us, inactive_us);
+	if (ret) {
+		ivpu_err_ratelimited(vdev, "Failed to enable DCT: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+int ivpu_pm_dct_disable(struct ivpu_device *vdev)
+{
+	int ret;
+
+	vdev->pm->dct_active_percent = 0;
+
+	ivpu_dbg(vdev, PM, "DCT requested to be disabled\n");
+
+	ret = ivpu_jsm_dct_disable(vdev);
+	if (ret) {
+		ivpu_err_ratelimited(vdev, "Failed to disable DCT: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+void ivpu_pm_irq_dct_work_fn(struct work_struct *work)
+{
+	struct ivpu_device *vdev = container_of(work, struct ivpu_device, irq_dct_work);
+	bool enable;
+	int ret;
+
+	if (ivpu_hw_btrs_dct_get_request(vdev, &enable))
+		return;
+
+	if (enable)
+		ret = ivpu_pm_dct_enable(vdev, DCT_DEFAULT_ACTIVE_PERCENT);
+	else
+		ret = ivpu_pm_dct_disable(vdev);
+
+	if (!ret) {
+		/* Convert percent to U1.7 format */
+		u8 val = DIV_ROUND_CLOSEST(vdev->pm->dct_active_percent * 128, 100);
+
+		ivpu_hw_btrs_dct_set_status(vdev, enable, val);
+	}
+
+}
diff --git a/drivers/accel/ivpu/ivpu_pm.h b/drivers/accel/ivpu/ivpu_pm.h
new file mode 100644
index 000000000000..a2aa7a27f32e
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_pm.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2020-2024 Intel Corporation
+ */
+
+#ifndef __IVPU_PM_H__
+#define __IVPU_PM_H__
+
+#include <linux/rwsem.h>
+#include <linux/types.h>
+
+struct ivpu_device;
+
+struct ivpu_pm_info {
+	struct ivpu_device *vdev;
+	struct delayed_work job_timeout_work;
+	struct work_struct recovery_work;
+	struct rw_semaphore reset_lock;
+	atomic_t reset_counter;
+	atomic_t reset_pending;
+	bool is_warmboot;
+	u8 dct_active_percent;
+};
+
+void ivpu_pm_init(struct ivpu_device *vdev);
+void ivpu_pm_enable(struct ivpu_device *vdev);
+void ivpu_pm_disable(struct ivpu_device *vdev);
+void ivpu_pm_disable_recovery(struct ivpu_device *vdev);
+
+int ivpu_pm_suspend_cb(struct device *dev);
+int ivpu_pm_resume_cb(struct device *dev);
+int ivpu_pm_runtime_suspend_cb(struct device *dev);
+int ivpu_pm_runtime_resume_cb(struct device *dev);
+
+void ivpu_pm_reset_prepare_cb(struct pci_dev *pdev);
+void ivpu_pm_reset_done_cb(struct pci_dev *pdev);
+
+int __must_check ivpu_rpm_get(struct ivpu_device *vdev);
+void ivpu_rpm_put(struct ivpu_device *vdev);
+
+void ivpu_pm_trigger_recovery(struct ivpu_device *vdev, const char *reason);
+void ivpu_start_job_timeout_detection(struct ivpu_device *vdev);
+void ivpu_stop_job_timeout_detection(struct ivpu_device *vdev);
+
+int ivpu_pm_dct_init(struct ivpu_device *vdev);
+int ivpu_pm_dct_enable(struct ivpu_device *vdev, u8 active_percent);
+int ivpu_pm_dct_disable(struct ivpu_device *vdev);
+void ivpu_pm_irq_dct_work_fn(struct work_struct *work);
+
+#endif /* __IVPU_PM_H__ */
diff --git a/drivers/accel/ivpu/ivpu_sysfs.c b/drivers/accel/ivpu/ivpu_sysfs.c
new file mode 100644
index 000000000000..d250a10caca9
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_sysfs.c
@@ -0,0 +1,159 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2024-2025 Intel Corporation
+ */
+
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/pm_runtime.h>
+#include <linux/units.h>
+
+#include "ivpu_drv.h"
+#include "ivpu_gem.h"
+#include "ivpu_fw.h"
+#include "ivpu_hw.h"
+#include "ivpu_sysfs.h"
+
+/**
+ * DOC: npu_busy_time_us
+ *
+ * npu_busy_time_us is the time that the device spent executing jobs.
+ * The time is counted when and only when there are jobs submitted to firmware.
+ *
+ * This time can be used to measure the utilization of NPU, either by calculating
+ * npu_busy_time_us difference between two timepoints (i.e. measuring the time
+ * that the NPU was active during some workload) or monitoring utilization percentage
+ * by reading npu_busy_time_us periodically.
+ *
+ * When reading the value periodically, it shouldn't be read too often as it may have
+ * an impact on job submission performance. Recommended period is 1 second.
+ */
+static ssize_t
+npu_busy_time_us_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+	struct drm_device *drm = dev_get_drvdata(dev);
+	struct ivpu_device *vdev = to_ivpu_device(drm);
+	ktime_t total, now = 0;
+
+	mutex_lock(&vdev->submitted_jobs_lock);
+
+	total = vdev->busy_time;
+	if (!xa_empty(&vdev->submitted_jobs_xa))
+		now = ktime_sub(ktime_get(), vdev->busy_start_ts);
+	mutex_unlock(&vdev->submitted_jobs_lock);
+
+	return sysfs_emit(buf, "%lld\n", ktime_to_us(ktime_add(total, now)));
+}
+
+static DEVICE_ATTR_RO(npu_busy_time_us);
+
+/**
+ * DOC: npu_memory_utilization
+ *
+ * The npu_memory_utilization is used to report in bytes a current NPU memory utilization.
+ *
+ */
+static ssize_t
+npu_memory_utilization_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+	struct drm_device *drm = dev_get_drvdata(dev);
+	struct ivpu_device *vdev = to_ivpu_device(drm);
+	struct ivpu_bo *bo;
+	u64 total_npu_memory = 0;
+
+	mutex_lock(&vdev->bo_list_lock);
+	list_for_each_entry(bo, &vdev->bo_list, bo_list_node)
+		if (ivpu_bo_is_resident(bo))
+			total_npu_memory += ivpu_bo_size(bo);
+	mutex_unlock(&vdev->bo_list_lock);
+
+	return sysfs_emit(buf, "%lld\n", total_npu_memory);
+}
+
+static DEVICE_ATTR_RO(npu_memory_utilization);
+
+/**
+ * DOC: sched_mode
+ *
+ * The sched_mode is used to report current NPU scheduling mode.
+ *
+ * It returns following strings:
+ * - "HW"		- Hardware Scheduler mode
+ * - "OS"		- Operating System Scheduler mode
+ *
+ */
+static ssize_t
+sched_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+	struct drm_device *drm = dev_get_drvdata(dev);
+	struct ivpu_device *vdev = to_ivpu_device(drm);
+
+	return sysfs_emit(buf, "%s\n", vdev->fw->sched_mode ? "HW" : "OS");
+}
+
+static DEVICE_ATTR_RO(sched_mode);
+
+/**
+ * DOC: npu_max_frequency
+ *
+ * The npu_max_frequency shows maximum frequency in MHz of the NPU's data
+ * processing unit
+ */
+static ssize_t
+npu_max_frequency_mhz_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+	struct drm_device *drm = dev_get_drvdata(dev);
+	struct ivpu_device *vdev = to_ivpu_device(drm);
+	u32 freq = ivpu_hw_dpu_max_freq_get(vdev);
+
+	return sysfs_emit(buf, "%lu\n", freq / HZ_PER_MHZ);
+}
+
+static DEVICE_ATTR_RO(npu_max_frequency_mhz);
+
+/**
+ * DOC: npu_current_frequency_mhz
+ *
+ * The npu_current_frequency_mhz shows current frequency in MHz of the NPU's
+ * data processing unit
+ */
+static ssize_t
+npu_current_frequency_mhz_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+	struct drm_device *drm = dev_get_drvdata(dev);
+	struct ivpu_device *vdev = to_ivpu_device(drm);
+	u32 freq = 0;
+
+	/* Read frequency only if device is active, otherwise frequency is 0 */
+	if (pm_runtime_get_if_active(vdev->drm.dev) > 0) {
+		freq = ivpu_hw_dpu_freq_get(vdev);
+
+		pm_runtime_put_autosuspend(vdev->drm.dev);
+	}
+
+	return sysfs_emit(buf, "%lu\n", freq / HZ_PER_MHZ);
+}
+
+static DEVICE_ATTR_RO(npu_current_frequency_mhz);
+
+static struct attribute *ivpu_dev_attrs[] = {
+	&dev_attr_npu_busy_time_us.attr,
+	&dev_attr_npu_memory_utilization.attr,
+	&dev_attr_sched_mode.attr,
+	&dev_attr_npu_max_frequency_mhz.attr,
+	&dev_attr_npu_current_frequency_mhz.attr,
+	NULL,
+};
+
+static struct attribute_group ivpu_dev_attr_group = {
+	.attrs = ivpu_dev_attrs,
+};
+
+void ivpu_sysfs_init(struct ivpu_device *vdev)
+{
+	int ret;
+
+	ret = devm_device_add_group(vdev->drm.dev, &ivpu_dev_attr_group);
+	if (ret)
+		ivpu_warn(vdev, "Failed to add group to device, ret %d", ret);
+}
diff --git a/drivers/accel/ivpu/ivpu_sysfs.h b/drivers/accel/ivpu/ivpu_sysfs.h
new file mode 100644
index 000000000000..9836f09b35a3
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_sysfs.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2024 Intel Corporation
+ */
+
+#ifndef __IVPU_SYSFS_H__
+#define __IVPU_SYSFS_H__
+
+#include "ivpu_drv.h"
+
+void ivpu_sysfs_init(struct ivpu_device *vdev);
+
+#endif /* __IVPU_SYSFS_H__ */
diff --git a/drivers/accel/ivpu/ivpu_trace.h b/drivers/accel/ivpu/ivpu_trace.h
new file mode 100644
index 000000000000..eb792038e701
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_trace.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2020-2024 Intel Corporation
+ */
+
+#if !defined(__IVPU_TRACE_H__) || defined(TRACE_HEADER_MULTI_READ)
+#define __IVPU_TRACE_H__
+
+#include <linux/tracepoint.h>
+#include "ivpu_drv.h"
+#include "ivpu_job.h"
+#include "vpu_jsm_api.h"
+#include "ivpu_jsm_msg.h"
+#include "ivpu_ipc.h"
+
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM vpu
+#define TRACE_INCLUDE_FILE ivpu_trace
+
+TRACE_EVENT(pm,
+	    TP_PROTO(const char *event),
+	    TP_ARGS(event),
+	    TP_STRUCT__entry(__field(const char *, event)),
+	    TP_fast_assign(__entry->event = event;),
+	    TP_printk("%s", __entry->event)
+);
+
+TRACE_EVENT(job,
+	    TP_PROTO(const char *event, struct ivpu_job *job),
+	    TP_ARGS(event, job),
+	    TP_STRUCT__entry(__field(const char *, event)
+		__field(u32, ctx_id)
+		__field(u32, engine_id)
+		__field(u32, job_id)
+		),
+	    TP_fast_assign(__entry->event = event;
+		__entry->ctx_id = job->file_priv->ctx.id;
+		__entry->engine_id = job->engine_idx;
+		__entry->job_id = job->job_id;),
+	    TP_printk("%s context:%d engine:%d job:%d",
+		      __entry->event,
+		      __entry->ctx_id,
+		      __entry->engine_id,
+		      __entry->job_id)
+);
+
+TRACE_EVENT(jsm,
+	    TP_PROTO(const char *event, struct vpu_jsm_msg *msg),
+	    TP_ARGS(event, msg),
+	    TP_STRUCT__entry(__field(const char *, event)
+		__field(const char *, type)
+		__field(enum vpu_ipc_msg_status, status)
+		__field(u32, request_id)
+		__field(u32, result)
+		),
+	    TP_fast_assign(__entry->event = event;
+		__entry->type = ivpu_jsm_msg_type_to_str(msg->type);
+		__entry->status = msg->status;
+		__entry->request_id = msg->request_id;
+		__entry->result = msg->result;),
+	    TP_printk("%s type:%s, status:%#x, id:%#x, result:%#x",
+		      __entry->event,
+		      __entry->type,
+		      __entry->status,
+		      __entry->request_id,
+		      __entry->result)
+);
+
+#endif /* __IVPU_TRACE_H__ */
+
+#undef TRACE_INCLUDE_PATH
+#define TRACE_INCLUDE_PATH .
+#include <trace/define_trace.h>
diff --git a/drivers/accel/ivpu/ivpu_trace_points.c b/drivers/accel/ivpu/ivpu_trace_points.c
new file mode 100644
index 000000000000..f8fb99de0de3
--- /dev/null
+++ b/drivers/accel/ivpu/ivpu_trace_points.c
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020-2024 Intel Corporation
+ */
+
+#ifndef __CHECKER__
+#define CREATE_TRACE_POINTS
+#include "ivpu_trace.h"
+#endif
diff --git a/drivers/accel/ivpu/vpu_boot_api.h b/drivers/accel/ivpu/vpu_boot_api.h
new file mode 100644
index 000000000000..218468bbbcad
--- /dev/null
+++ b/drivers/accel/ivpu/vpu_boot_api.h
@@ -0,0 +1,473 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright (c) 2020-2024, Intel Corporation.
+ */
+
+#ifndef VPU_BOOT_API_H
+#define VPU_BOOT_API_H
+
+/*
+ *  The below values will be used to construct the version info this way:
+ *  fw_bin_header->api_version[VPU_BOOT_API_VER_ID] = (VPU_BOOT_API_VER_MAJOR << 16) |
+ *  VPU_BOOT_API_VER_MINOR;
+ *  VPU_BOOT_API_VER_PATCH will be ignored. KMD and compatibility is not affected if this changes
+ *  This information is collected by using vpuip_2/application/vpuFirmware/make_std_fw_image.py
+ *  If a header is missing this info we ignore the header, if a header is missing or contains
+ *  partial info a build error will be generated.
+ */
+
+/*
+ * Major version changes that break backward compatibility.
+ * Major version must start from 1 and can only be incremented.
+ */
+#define VPU_BOOT_API_VER_MAJOR 3
+
+/*
+ * Minor version changes when API backward compatibility is preserved.
+ * Resets to 0 if Major version is incremented.
+ */
+#define VPU_BOOT_API_VER_MINOR 28
+
+/*
+ * API header changed (field names, documentation, formatting) but API itself has not been changed
+ */
+#define VPU_BOOT_API_VER_PATCH 3
+
+/*
+ * Index in the API version table
+ * Must be unique for each API
+ */
+#define VPU_BOOT_API_VER_INDEX 0
+
+#pragma pack(push, 4)
+
+/*
+ * Firmware image header format
+ */
+#define VPU_FW_HEADER_SIZE    4096
+#define VPU_FW_HEADER_VERSION 0x1
+#define VPU_FW_VERSION_SIZE   32
+#define VPU_FW_API_VER_NUM    16
+
+struct vpu_firmware_header {
+	u32 header_version;
+	u32 image_format;
+	u64 image_load_address;
+	u32 image_size;
+	u64 entry_point;
+	u8 vpu_version[VPU_FW_VERSION_SIZE];
+	u32 compression_type;
+	u64 firmware_version_load_address;
+	u32 firmware_version_size;
+	u64 boot_params_load_address;
+	u32 api_version[VPU_FW_API_VER_NUM];
+	/* Size of memory require for firmware execution */
+	u32 runtime_size;
+	u32 shave_nn_fw_size;
+	/*
+	 * Size of primary preemption buffer, assuming a 2-job submission queue.
+	 * NOTE: host driver is expected to adapt size accordingly to actual
+	 * submission queue size and device capabilities.
+	 */
+	u32 preemption_buffer_1_size;
+	/*
+	 * Size of secondary preemption buffer, assuming a 2-job submission queue.
+	 * NOTE: host driver is expected to adapt size accordingly to actual
+	 * submission queue size and device capabilities.
+	 */
+	u32 preemption_buffer_2_size;
+	/*
+	 * Maximum preemption buffer size that the FW can use: no need for the host
+	 * driver to allocate more space than that specified by these fields.
+	 * A value of 0 means no declared limit.
+	 */
+	u32 preemption_buffer_1_max_size;
+	u32 preemption_buffer_2_max_size;
+	/* Space reserved for future preemption-related fields. */
+	u32 preemption_reserved[4];
+	/* FW image read only section start address, 4KB aligned */
+	u64 ro_section_start_address;
+	/* FW image read only section size, 4KB aligned */
+	u32 ro_section_size;
+	u32 reserved;
+};
+
+/*
+ * Firmware boot parameters format
+ */
+
+#define VPU_BOOT_PLL_COUNT     3
+#define VPU_BOOT_PLL_OUT_COUNT 4
+
+/** Values for boot_type field */
+#define VPU_BOOT_TYPE_COLDBOOT 0
+#define VPU_BOOT_TYPE_WARMBOOT 1
+
+/** Value for magic filed */
+#define VPU_BOOT_PARAMS_MAGIC 0x10000
+
+/** VPU scheduling mode. By default, OS scheduling is used. */
+#define VPU_SCHEDULING_MODE_OS 0
+#define VPU_SCHEDULING_MODE_HW 1
+
+enum VPU_BOOT_L2_CACHE_CFG_TYPE {
+	VPU_BOOT_L2_CACHE_CFG_UPA = 0,
+	VPU_BOOT_L2_CACHE_CFG_NN = 1,
+	VPU_BOOT_L2_CACHE_CFG_NUM = 2
+};
+
+/** VPU MCA ECC signalling mode. By default, no signalling is used */
+enum VPU_BOOT_MCA_ECC_SIGNAL_TYPE {
+	VPU_BOOT_MCA_ECC_NONE = 0,
+	VPU_BOOT_MCA_ECC_CORR = 1,
+	VPU_BOOT_MCA_ECC_FATAL = 2,
+	VPU_BOOT_MCA_ECC_BOTH = 3
+};
+
+/**
+ * Logging destinations.
+ *
+ * Logging output can be directed to different logging destinations. This enum
+ * defines the list of logging destinations supported by the VPU firmware (NOTE:
+ * a specific VPU FW binary may support only a subset of such output
+ * destinations, depending on the target platform and compile options).
+ */
+enum vpu_trace_destination {
+	VPU_TRACE_DESTINATION_PIPEPRINT = 0x1,
+	VPU_TRACE_DESTINATION_VERBOSE_TRACING = 0x2,
+	VPU_TRACE_DESTINATION_NORTH_PEAK = 0x4,
+};
+
+/*
+ * Processor bit shifts (for loggable HW components).
+ */
+#define VPU_TRACE_PROC_BIT_RESERVED  0
+#define VPU_TRACE_PROC_BIT_LRT	     1
+#define VPU_TRACE_PROC_BIT_LNN	     2
+#define VPU_TRACE_PROC_BIT_SHV_0     3
+#define VPU_TRACE_PROC_BIT_SHV_1     4
+#define VPU_TRACE_PROC_BIT_SHV_2     5
+#define VPU_TRACE_PROC_BIT_SHV_3     6
+#define VPU_TRACE_PROC_BIT_SHV_4     7
+#define VPU_TRACE_PROC_BIT_SHV_5     8
+#define VPU_TRACE_PROC_BIT_SHV_6     9
+#define VPU_TRACE_PROC_BIT_SHV_7     10
+#define VPU_TRACE_PROC_BIT_SHV_8     11
+#define VPU_TRACE_PROC_BIT_SHV_9     12
+#define VPU_TRACE_PROC_BIT_SHV_10    13
+#define VPU_TRACE_PROC_BIT_SHV_11    14
+#define VPU_TRACE_PROC_BIT_SHV_12    15
+#define VPU_TRACE_PROC_BIT_SHV_13    16
+#define VPU_TRACE_PROC_BIT_SHV_14    17
+#define VPU_TRACE_PROC_BIT_SHV_15    18
+#define VPU_TRACE_PROC_BIT_ACT_SHV_0 19
+#define VPU_TRACE_PROC_BIT_ACT_SHV_1 20
+#define VPU_TRACE_PROC_BIT_ACT_SHV_2 21
+#define VPU_TRACE_PROC_BIT_ACT_SHV_3 22
+#define VPU_TRACE_PROC_NO_OF_HW_DEVS 23
+
+/* VPU 30xx HW component IDs are sequential, so define first and last IDs. */
+#define VPU_TRACE_PROC_BIT_30XX_FIRST VPU_TRACE_PROC_BIT_LRT
+#define VPU_TRACE_PROC_BIT_30XX_LAST  VPU_TRACE_PROC_BIT_SHV_15
+
+struct vpu_boot_l2_cache_config {
+	u8 use;
+	u8 cfg;
+};
+
+struct vpu_warm_boot_section {
+	u32 src;
+	u32 dst;
+	u32 size;
+	u32 core_id;
+	u32 is_clear_op;
+};
+
+/*
+ * When HW scheduling mode is enabled, a present period is defined.
+ * It will be used by VPU to swap between normal and focus priorities
+ * to prevent starving of normal priority band (when implemented).
+ * Host must provide a valid value at boot time in
+ * `vpu_focus_present_timer_ms`. If the value provided by the host is not within the
+ * defined range a default value will be used. Here we define the min. and max.
+ * allowed values and the and default value of the present period. Units are milliseconds.
+ */
+#define VPU_PRESENT_CALL_PERIOD_MS_DEFAULT 50
+#define VPU_PRESENT_CALL_PERIOD_MS_MIN	   16
+#define VPU_PRESENT_CALL_PERIOD_MS_MAX	   10000
+
+/**
+ * Macros to enable various power profiles within the NPU.
+ * To be defined as part of 32 bit mask.
+ */
+#define POWER_PROFILE_SURVIVABILITY 0x1
+
+/**
+ * Enum for dvfs_mode boot param.
+ */
+enum vpu_governor {
+	VPU_GOV_DEFAULT = 0, /* Default Governor for the system */
+	VPU_GOV_MAX_PERFORMANCE = 1, /* Maximum performance governor */
+	VPU_GOV_ON_DEMAND = 2, /* On Demand frequency control governor */
+	VPU_GOV_POWER_SAVE = 3, /* Power save governor */
+	VPU_GOV_ON_DEMAND_PRIORITY_AWARE = 4 /* On Demand priority based governor */
+};
+
+struct vpu_boot_params {
+	u32 magic;
+	u32 vpu_id;
+	u32 vpu_count;
+	u32 pad0[5];
+	/* Clock frequencies: 0x20 - 0xFF */
+	u32 frequency;
+	u32 pll[VPU_BOOT_PLL_COUNT][VPU_BOOT_PLL_OUT_COUNT];
+	u32 perf_clk_frequency;
+	u32 pad1[42];
+	/* Memory regions: 0x100 - 0x1FF */
+	u64 ipc_header_area_start;
+	u32 ipc_header_area_size;
+	u64 shared_region_base;
+	u32 shared_region_size;
+	u64 ipc_payload_area_start;
+	u32 ipc_payload_area_size;
+	u64 global_aliased_pio_base;
+	u32 global_aliased_pio_size;
+	u32 autoconfig;
+	struct vpu_boot_l2_cache_config cache_defaults[VPU_BOOT_L2_CACHE_CFG_NUM];
+	u64 global_memory_allocator_base;
+	u32 global_memory_allocator_size;
+	/**
+	 * ShaveNN FW section VPU base address
+	 * On VPU2.7 HW this address must be within 2GB range starting from L2C_PAGE_TABLE base
+	 */
+	u64 shave_nn_fw_base;
+	u64 save_restore_ret_address; /* stores the address of FW's restore entry point */
+	u32 pad2[43];
+	/* IRQ re-direct numbers: 0x200 - 0x2FF */
+	s32 watchdog_irq_mss;
+	s32 watchdog_irq_nce;
+	/* ARM -> VPU doorbell interrupt. ARM is notifying VPU of async command or compute job. */
+	u32 host_to_vpu_irq;
+	/* VPU -> ARM job done interrupt. VPU is notifying ARM of compute job completion. */
+	u32 job_done_irq;
+	/* VPU -> ARM IRQ line to use to request MMU update. */
+	u32 mmu_update_request_irq;
+	/* ARM -> VPU IRQ line to use to notify of MMU update completion. */
+	u32 mmu_update_done_irq;
+	/* ARM -> VPU IRQ line to use to request power level change. */
+	u32 set_power_level_irq;
+	/* VPU -> ARM IRQ line to use to notify of power level change completion. */
+	u32 set_power_level_done_irq;
+	/* VPU -> ARM IRQ line to use to notify of VPU idle state change */
+	u32 set_vpu_idle_update_irq;
+	/* VPU -> ARM IRQ line to use to request counter reset. */
+	u32 metric_query_event_irq;
+	/* ARM -> VPU IRQ line to use to notify of counter reset completion. */
+	u32 metric_query_event_done_irq;
+	/* VPU -> ARM IRQ line to use to notify of preemption completion. */
+	u32 preemption_done_irq;
+	/* Padding. */
+	u32 pad3[52];
+	/* Silicon information: 0x300 - 0x3FF */
+	u32 host_version_id;
+	u32 si_stepping;
+	u64 device_id;
+	u64 feature_exclusion;
+	u64 sku;
+	/** PLL ratio for minimum clock frequency */
+	u32 min_freq_pll_ratio;
+	/** PLL ratio for maximum clock frequency */
+	u32 max_freq_pll_ratio;
+	/**
+	 * Initial log level threshold (messages with log level severity less than
+	 * the threshold will not be logged); applies to every enabled logging
+	 * destination and loggable HW component. See 'mvLog_t' enum for acceptable
+	 * values.
+	 * TODO: EISW-33556: Move log level definition (mvLog_t) to this file.
+	 */
+	u32 default_trace_level;
+	u32 boot_type;
+	u64 punit_telemetry_sram_base;
+	u64 punit_telemetry_sram_size;
+	u32 vpu_telemetry_enable;
+	u64 crit_tracing_buff_addr;
+	u32 crit_tracing_buff_size;
+	u64 verbose_tracing_buff_addr;
+	u32 verbose_tracing_buff_size;
+	u64 verbose_tracing_sw_component_mask; /* TO BE REMOVED */
+	/**
+	 * Mask of destinations to which logging messages are delivered; bitwise OR
+	 * of values defined in vpu_trace_destination enum.
+	 */
+	u32 trace_destination_mask;
+	/**
+	 * Mask of hardware components for which logging is enabled; bitwise OR of
+	 * bits defined by the VPU_TRACE_PROC_BIT_* macros.
+	 */
+	u64 trace_hw_component_mask;
+	/** Mask of trace message formats supported by the driver */
+	u64 tracing_buff_message_format_mask;
+	u64 trace_reserved_1[2];
+	/**
+	 * Period at which the VPU reads the temp sensor values into MMIO, on
+	 * platforms where that is necessary (in ms). 0 to disable reads.
+	 */
+	u32 temp_sensor_period_ms;
+	/** PLL ratio for efficient clock frequency */
+	u32 pn_freq_pll_ratio;
+	/**
+	 * DVFS Mode:
+	 * 0 - Default, DVFS mode selected by the firmware
+	 * 1 - Max Performance
+	 * 2 - On Demand
+	 * 3 - Power Save
+	 * 4 - On Demand Priority Aware
+	 */
+	u32 dvfs_mode;
+	/**
+	 * Depending on DVFS Mode:
+	 * On-demand: Default if 0.
+	 *    Bit 0-7   - uint8_t: Highest residency percent
+	 *    Bit 8-15  - uint8_t: High residency percent
+	 *    Bit 16-23 - uint8_t: Low residency percent
+	 *    Bit 24-31 - uint8_t: Lowest residency percent
+	 *    Bit 32-35 - unsigned 4b: PLL Ratio increase amount on highest residency
+	 *    Bit 36-39 - unsigned 4b: PLL Ratio increase amount on high residency
+	 *    Bit 40-43 - unsigned 4b: PLL Ratio decrease amount on low residency
+	 *    Bit 44-47 - unsigned 4b: PLL Ratio decrease amount on lowest frequency
+	 *    Bit 48-55 - uint8_t: Period (ms) for residency decisions
+	 *    Bit 56-63 - uint8_t: Averaging windows (as multiples of period. Max: 30 decimal)
+	 * Power Save/Max Performance: Unused
+	 */
+	u64 dvfs_param;
+	/**
+	 * D0i3 delayed entry
+	 * Bit0: Disable CPU state save on D0i2 entry flow.
+	 *       0: Every D0i2 entry saves state. Save state IPC message ignored.
+	 *       1: IPC message required to save state on D0i3 entry flow.
+	 */
+	u32 d0i3_delayed_entry;
+	/* Time spent by VPU in D0i3 state */
+	u64 d0i3_residency_time_us;
+	/* Value of VPU perf counter at the time of entering D0i3 state . */
+	u64 d0i3_entry_vpu_ts;
+	/*
+	 * The system time of the host operating system in microseconds.
+	 * E.g the number of microseconds since 1st of January 1970, or whatever
+	 * date the host operating system uses to maintain system time.
+	 * This value will be used to track system time on the VPU.
+	 * The KMD is required to update this value on every VPU reset.
+	 */
+	u64 system_time_us;
+	u32 pad4[2];
+	/*
+	 * The delta between device monotonic time and the current value of the
+	 * HW timestamp register, in ticks. Written by the firmware during boot.
+	 * Can be used by the KMD to calculate device time.
+	 */
+	u64 device_time_delta_ticks;
+	u32 pad7[14];
+	/* Warm boot information: 0x400 - 0x43F */
+	u32 warm_boot_sections_count;
+	u32 warm_boot_start_address_reference;
+	u32 warm_boot_section_info_address_offset;
+	u32 pad5[13];
+	/* Power States transitions timestamps: 0x440 - 0x46F*/
+	struct {
+		/* VPU_IDLE -> VPU_ACTIVE transition initiated timestamp */
+		u64 vpu_active_state_requested;
+		/* VPU_IDLE -> VPU_ACTIVE transition completed timestamp */
+		u64 vpu_active_state_achieved;
+		/* VPU_ACTIVE -> VPU_IDLE transition initiated timestamp */
+		u64 vpu_idle_state_requested;
+		/* VPU_ACTIVE -> VPU_IDLE transition completed timestamp */
+		u64 vpu_idle_state_achieved;
+		/* VPU_IDLE -> VPU_STANDBY transition initiated timestamp */
+		u64 vpu_standby_state_requested;
+		/* VPU_IDLE -> VPU_STANDBY transition completed timestamp */
+		u64 vpu_standby_state_achieved;
+	} power_states_timestamps;
+	/* VPU scheduling mode. Values defined by VPU_SCHEDULING_MODE_* macros. */
+	u32 vpu_scheduling_mode;
+	/* Present call period in milliseconds. */
+	u32 vpu_focus_present_timer_ms;
+	/* VPU ECC Signaling */
+	u32 vpu_uses_ecc_mca_signal;
+	/* Values defined by POWER_PROFILE* macros */
+	u32 power_profile;
+	/* Microsecond value for DCT active cycle */
+	u32 dct_active_us;
+	/* Microsecond value for DCT inactive cycle */
+	u32 dct_inactive_us;
+	/* Unused/reserved: 0x488 - 0xFFF */
+	u32 pad6[734];
+};
+
+/* Magic numbers set between host and vpu to detect corruption of tracing init */
+#define VPU_TRACING_BUFFER_CANARY (0xCAFECAFE)
+
+/* Tracing buffer message format definitions */
+#define VPU_TRACING_FORMAT_STRING 0
+#define VPU_TRACING_FORMAT_MIPI	  2
+/*
+ * Header of the tracing buffer.
+ * The below defined header will be stored at the beginning of
+ * each allocated tracing buffer, followed by a series of 256b
+ * of ASCII trace message entries.
+ */
+struct vpu_tracing_buffer_header {
+	/**
+	 * Magic number set by host to detect corruption
+	 * @see VPU_TRACING_BUFFER_CANARY
+	 */
+	u32 host_canary_start;
+	/* offset from start of buffer for trace entries */
+	u32 read_index;
+	/* keeps track of wrapping on the reader side */
+	u32 read_wrap_count;
+	u32 pad_to_cache_line_size_0[13];
+	/* End of first cache line */
+
+	/**
+	 * Magic number set by host to detect corruption
+	 * @see VPU_TRACING_BUFFER_CANARY
+	 */
+	u32 vpu_canary_start;
+	/* offset from start of buffer from write start */
+	u32 write_index;
+	/* counter for buffer wrapping */
+	u32 wrap_count;
+	/* legacy field - do not use */
+	u32 reserved_0;
+	/**
+	 * Size of the log buffer include this header (@header_size) and space
+	 * reserved for all messages. If @alignment` is greater that 0 the @Size
+	 * must be multiple of @Alignment.
+	 */
+	u32 size;
+	/* Header version */
+	u16 header_version;
+	/* Header size */
+	u16 header_size;
+	/*
+	 * Format of the messages in the trace buffer
+	 * 0 - null terminated string
+	 * 1 - size + null terminated string
+	 * 2 - MIPI-SysT encoding
+	 */
+	u32 format;
+	/*
+	 * Message alignment
+	 * 0 - messages are place 1 after another
+	 * n - every message starts and multiple on offset
+	 */
+	u32 alignment; /* 64, 128, 256 */
+	/* Name of the logging entity, i.e "LRT", "LNN", "SHV0", etc */
+	char name[16];
+	u32 pad_to_cache_line_size_1[4];
+	/* End of second cache line */
+};
+
+#pragma pack(pop)
+
+#endif
diff --git a/drivers/accel/ivpu/vpu_jsm_api.h b/drivers/accel/ivpu/vpu_jsm_api.h
new file mode 100644
index 000000000000..bca6a44dc041
--- /dev/null
+++ b/drivers/accel/ivpu/vpu_jsm_api.h
@@ -0,0 +1,1726 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright (c) 2020-2025, Intel Corporation.
+ */
+
+/**
+ * @addtogroup Jsm
+ * @{
+ */
+
+/**
+ * @file
+ * @brief JSM shared definitions
+ */
+#ifndef VPU_JSM_API_H
+#define VPU_JSM_API_H
+
+/*
+ * Major version changes that break backward compatibility
+ */
+#define VPU_JSM_API_VER_MAJOR 3
+
+/*
+ * Minor version changes when API backward compatibility is preserved.
+ */
+#define VPU_JSM_API_VER_MINOR 33
+
+/*
+ * API header changed (field names, documentation, formatting) but API itself has not been changed
+ */
+#define VPU_JSM_API_VER_PATCH 0
+
+/*
+ * Index in the API version table
+ */
+#define VPU_JSM_API_VER_INDEX 4
+
+/*
+ * Number of Priority Bands for Hardware Scheduling
+ * Bands: Idle(0), Normal(1), Focus(2), RealTime(3)
+ */
+#define VPU_HWS_NUM_PRIORITY_BANDS 4
+
+/* Max number of impacted contexts that can be dealt with the engine reset command */
+#define VPU_MAX_ENGINE_RESET_IMPACTED_CONTEXTS 3
+
+/*
+ * Pack the API structures to enforce binary compatibility
+ * Align to 8 bytes for optimal performance
+ */
+#pragma pack(push, 8)
+
+/*
+ * Engine indexes.
+ */
+#define VPU_ENGINE_COMPUTE 0
+#define VPU_ENGINE_NB	   1
+
+/*
+ * VPU status values.
+ */
+#define VPU_JSM_STATUS_SUCCESS				 0x0U
+#define VPU_JSM_STATUS_PARSING_ERR			 0x1U
+#define VPU_JSM_STATUS_PROCESSING_ERR			 0x2U
+#define VPU_JSM_STATUS_PREEMPTED			 0x3U
+#define VPU_JSM_STATUS_ABORTED				 0x4U
+#define VPU_JSM_STATUS_USER_CTX_VIOL_ERR		 0x5U
+#define VPU_JSM_STATUS_GLOBAL_CTX_VIOL_ERR		 0x6U
+#define VPU_JSM_STATUS_MVNCI_WRONG_INPUT_FORMAT		 0x7U
+#define VPU_JSM_STATUS_MVNCI_UNSUPPORTED_NETWORK_ELEMENT 0x8U
+#define VPU_JSM_STATUS_MVNCI_INVALID_HANDLE		 0x9U
+#define VPU_JSM_STATUS_MVNCI_OUT_OF_RESOURCES		 0xAU
+#define VPU_JSM_STATUS_MVNCI_NOT_IMPLEMENTED		 0xBU
+#define VPU_JSM_STATUS_MVNCI_INTERNAL_ERROR		 0xCU
+/* @deprecated (use VPU_JSM_STATUS_PREEMPTED_MID_COMMAND instead) */
+#define VPU_JSM_STATUS_PREEMPTED_MID_INFERENCE		 0xDU
+/* Job status returned when the job was preempted mid-command */
+#define VPU_JSM_STATUS_PREEMPTED_MID_COMMAND		 0xDU
+/* Range of status codes that require engine reset */
+#define VPU_JSM_STATUS_ENGINE_RESET_REQUIRED_MIN	 0xEU
+#define VPU_JSM_STATUS_MVNCI_CONTEXT_VIOLATION_HW	 0xEU
+#define VPU_JSM_STATUS_MVNCI_PREEMPTION_TIMED_OUT	 0xFU
+#define VPU_JSM_STATUS_ENGINE_RESET_REQUIRED_MAX	 0x1FU
+
+/*
+ * Host <-> VPU IPC channels.
+ * ASYNC commands use a high priority channel, other messages use low-priority ones.
+ */
+#define VPU_IPC_CHAN_ASYNC_CMD 0
+#define VPU_IPC_CHAN_GEN_CMD   10
+#define VPU_IPC_CHAN_JOB_RET   11
+
+/*
+ * Job flags bit masks.
+ */
+enum {
+	/*
+	 * Null submission mask.
+	 * When set, batch buffer's commands are not processed but returned as
+	 * successful immediately, except fences and timestamps.
+	 * When cleared, batch buffer's commands are processed normally.
+	 * Used for testing and profiling purposes.
+	 */
+	VPU_JOB_FLAGS_NULL_SUBMISSION_MASK = (1 << 0U),
+	/*
+	 * Inline command mask.
+	 * When set, the object in job queue is an inline command (see struct vpu_inline_cmd below).
+	 * When cleared, the object in job queue is a job (see struct vpu_job_queue_entry below).
+	 */
+	VPU_JOB_FLAGS_INLINE_CMD_MASK = (1 << 1U),
+	/*
+	 * VPU private data mask.
+	 * Reserved for the VPU to store private data about the job (or inline command)
+	 * while being processed.
+	 */
+	VPU_JOB_FLAGS_PRIVATE_DATA_MASK = 0xFFFF0000U
+};
+
+/*
+ * Job queue flags bit masks.
+ */
+enum {
+	/*
+	 * No job done notification mask.
+	 * When set, indicates that no job done notification should be sent for any
+	 * job from this queue. When cleared, indicates that job done notification
+	 * should be sent for every job completed from this queue.
+	 */
+	VPU_JOB_QUEUE_FLAGS_NO_JOB_DONE_MASK = (1 << 0U),
+	/*
+	 * Native fence usage mask.
+	 * When set, indicates that job queue uses native fences (as inline commands
+	 * in job queue). Such queues may also use legacy fences (as commands in batch buffers).
+	 * When cleared, indicates the job queue only uses legacy fences.
+	 * NOTES:
+	 *   1. For queues using native fences, VPU expects that all jobs in the queue
+	 *      are immediately followed by an inline command object. This object is expected
+	 *      to be a fence signal command in most cases, but can also be a NOP in case the host
+	 *      does not need per-job fence signalling. Other inline commands objects can be
+	 *      inserted between "job and inline command" pairs.
+	 *  2. Native fence queues are only supported on VPU 40xx onwards.
+	 */
+	VPU_JOB_QUEUE_FLAGS_USE_NATIVE_FENCE_MASK = (1 << 1U),
+	/*
+	 * Enable turbo mode for testing NPU performance; not recommended for regular usage.
+	 */
+	VPU_JOB_QUEUE_FLAGS_TURBO_MODE = (1 << 2U),
+	/*
+	 * Queue error detection mode flag
+	 * For 'interactive' queues (this bit not set), the FW will identify queues that have not
+	 * completed a job inside the TDR timeout as in error as part of engine reset sequence.
+	 * For 'non-interactive' queues (this bit set), the FW will identify queues that have not
+	 * progressed the heartbeat inside the non-interactive no-progress timeout as in error as
+	 * part of engine reset sequence. Additionally, there is an upper limit applied to these
+	 * queues: even if they progress the heartbeat, if they run longer than non-interactive
+	 * timeout, then the FW will also identify them as in error.
+	 */
+	VPU_JOB_QUEUE_FLAGS_NON_INTERACTIVE = (1 << 3U)
+};
+
+/*
+ * Max length (including trailing NULL char) of trace entity name (e.g., the
+ * name of a logging destination or a loggable HW component).
+ */
+#define VPU_TRACE_ENTITY_NAME_MAX_LEN 32
+
+/*
+ * Max length (including trailing NULL char) of a dyndbg command.
+ *
+ * NOTE: 96 is used so that the size of 'struct vpu_ipc_msg' in the JSM API is
+ * 128 bytes (multiple of 64 bytes, the cache line size).
+ */
+#define VPU_DYNDBG_CMD_MAX_LEN 96
+
+/*
+ * For HWS command queue scheduling, we can prioritise command queues inside the
+ * same process with a relative in-process priority. Valid values for relative
+ * priority are given below - max and min.
+ */
+#define VPU_HWS_COMMAND_QUEUE_MAX_IN_PROCESS_PRIORITY 7
+#define VPU_HWS_COMMAND_QUEUE_MIN_IN_PROCESS_PRIORITY -7
+
+/*
+ * For HWS priority scheduling, we can have multiple realtime priority bands.
+ * They are numbered 0 to a MAX.
+ */
+#define VPU_HWS_MAX_REALTIME_PRIORITY_LEVEL 31U
+
+/*
+ * vpu_jsm_engine_reset_context flag definitions
+ */
+#define VPU_ENGINE_RESET_CONTEXT_FLAG_COLLATERAL_DAMAGE_MASK BIT(0)
+#define VPU_ENGINE_RESET_CONTEXT_HANG_PRIMARY_CAUSE	     0
+#define VPU_ENGINE_RESET_CONTEXT_COLLATERAL_DAMAGE	     1
+
+/*
+ * Invalid command queue handle identifier. Applies to cmdq_id and cmdq_group
+ * in this API.
+ */
+#define VPU_HWS_INVALID_CMDQ_HANDLE 0ULL
+
+/*
+ * Inline commands types.
+ */
+/*
+ * NOP.
+ * VPU does nothing other than consuming the inline command object.
+ */
+#define VPU_INLINE_CMD_TYPE_NOP		 0x0
+/*
+ * Fence wait.
+ * VPU waits for the fence current value to reach monitored value.
+ * Fence wait operations are executed upon job dispatching. While waiting for
+ * the fence to be satisfied, VPU blocks fetching of the next objects in the queue.
+ * Jobs present in the queue prior to the fence wait object may be processed
+ * concurrently.
+ */
+#define VPU_INLINE_CMD_TYPE_FENCE_WAIT	 0x1
+/*
+ * Fence signal.
+ * VPU sets the fence current value to the provided value. If new current value
+ * is equal to or higher than monitored value, VPU sends fence signalled notification
+ * to the host. Fence signal operations are executed upon completion of all the jobs
+ * present in the queue prior to them, and in-order relative to each other in the queue.
+ * But jobs in-between them may be processed concurrently and may complete out-of-order.
+ */
+#define VPU_INLINE_CMD_TYPE_FENCE_SIGNAL 0x2
+
+/**
+ * Job scheduling priority bands for both hardware scheduling and OS scheduling.
+ */
+enum vpu_job_scheduling_priority_band {
+	VPU_JOB_SCHEDULING_PRIORITY_BAND_IDLE = 0,
+	VPU_JOB_SCHEDULING_PRIORITY_BAND_NORMAL = 1,
+	VPU_JOB_SCHEDULING_PRIORITY_BAND_FOCUS = 2,
+	VPU_JOB_SCHEDULING_PRIORITY_BAND_REALTIME = 3,
+	VPU_JOB_SCHEDULING_PRIORITY_BAND_COUNT = 4,
+};
+
+/**
+ * Job format.
+ * Jobs defines the actual workloads to be executed by a given engine.
+ */
+struct vpu_job_queue_entry {
+	/** Address of VPU commands batch buffer */
+	u64 batch_buf_addr;
+	/** Job ID */
+	u32 job_id;
+	/** Flags bit field, see VPU_JOB_FLAGS_* above */
+	u32 flags;
+	/**
+	 * Doorbell ring timestamp taken by KMD from SoC's global system clock, in
+	 * microseconds. NPU can convert this value to its own fixed clock's timebase,
+	 * to match other profiling timestamps.
+	 */
+	u64 doorbell_timestamp;
+	/** Extra id for job tracking, used only in the firmware perf traces */
+	u64 host_tracking_id;
+	/** Address of the primary preemption buffer to use for this job */
+	u64 primary_preempt_buf_addr;
+	/** Size of the primary preemption buffer to use for this job */
+	u32 primary_preempt_buf_size;
+	/** Size of secondary preemption buffer to use for this job */
+	u32 secondary_preempt_buf_size;
+	/** Address of secondary preemption buffer to use for this job */
+	u64 secondary_preempt_buf_addr;
+	u64 reserved_0;
+};
+
+/**
+ * Inline command format.
+ * Inline commands are the commands executed at scheduler level (typically,
+ * synchronization directives). Inline command and job objects must be of
+ * the same size and have flags field at same offset.
+ */
+struct vpu_inline_cmd {
+	u64 reserved_0;
+	/** Inline command type, see VPU_INLINE_CMD_TYPE_* defines. */
+	u32 type;
+	/** Flags bit field, see VPU_JOB_FLAGS_* above. */
+	u32 flags;
+	/** Inline command payload. Depends on inline command type. */
+	union payload {
+		/** Fence (wait and signal) commands' payload. */
+		struct fence {
+			/** Fence object handle. */
+			u64 fence_handle;
+			/** User VA of the current fence value. */
+			u64 current_value_va;
+			/** User VA of the monitored fence value (read-only). */
+			u64 monitored_value_va;
+			/** Value to wait for or write in fence location. */
+			u64 value;
+			/** User VA of the log buffer in which to add log entry on completion. */
+			u64 log_buffer_va;
+			/** NPU private data. */
+			u64 npu_private_data;
+		} fence;
+		/**
+		 * Other commands do not have a payload:
+		 * Payload definition for future inline commands can be inserted here.
+		 */
+		u64 reserved_1[6];
+	} payload;
+};
+
+/**
+ * Job queue slots can be populated either with job objects or inline command objects.
+ */
+union vpu_jobq_slot {
+	struct vpu_job_queue_entry job;
+	struct vpu_inline_cmd inline_cmd;
+};
+
+/**
+ * Job queue control registers.
+ */
+struct vpu_job_queue_header {
+	u32 engine_idx;
+	u32 head;
+	u32 tail;
+	u32 flags;
+	/** Set to 1 to indicate priority_band field is valid */
+	u32 priority_band_valid;
+	/**
+	 * Priority for the work of this job queue, valid only if the HWS is NOT used
+	 * and the @ref priority_band_valid is set to 1. It is applied only during
+	 * the @ref VPU_JSM_MSG_REGISTER_DB message processing.
+	 * The device firmware might use the priority_band to optimize the power
+	 * management logic, but it will not affect the order of jobs.
+	 * Available priority bands: @see enum vpu_job_scheduling_priority_band
+	 */
+	u32 priority_band;
+	/** Inside realtime band assigns a further priority, limited to 0..31 range */
+	u32 realtime_priority_level;
+	u32 reserved_0[9];
+};
+
+/*
+ * Job queue format.
+ */
+struct vpu_job_queue {
+	struct vpu_job_queue_header header;
+	union vpu_jobq_slot slot[];
+};
+
+/**
+ * Logging entity types.
+ *
+ * This enum defines the different types of entities involved in logging.
+ */
+enum vpu_trace_entity_type {
+	/** Logging destination (entity where logs can be stored / printed). */
+	VPU_TRACE_ENTITY_TYPE_DESTINATION = 1,
+	/** Loggable HW component (HW entity that can be logged). */
+	VPU_TRACE_ENTITY_TYPE_HW_COMPONENT = 2,
+};
+
+/**
+ * HWS specific log buffer header details.
+ * Total size is 32 bytes.
+ */
+struct vpu_hws_log_buffer_header {
+	/** Written by VPU after adding a log entry. Initialised by host to 0. */
+	u32 first_free_entry_index;
+	/** Incremented by VPU every time the VPU writes the 0th entry; initialised by host to 0. */
+	u32 wraparound_count;
+	/**
+	 * This is the number of buffers that can be stored in the log buffer provided by the host.
+	 * It is written by host before passing buffer to VPU. VPU should consider it read-only.
+	 */
+	u64 num_of_entries;
+	u64 reserved[2];
+};
+
+/**
+ * HWS specific log buffer entry details.
+ * Total size is 32 bytes.
+ */
+struct vpu_hws_log_buffer_entry {
+	/** VPU timestamp must be an invariant timer tick (not impacted by DVFS) */
+	u64 vpu_timestamp;
+	/**
+	 * Operation type:
+	 *     0 - context state change
+	 *     1 - queue new work
+	 *     2 - queue unwait sync object
+	 *     3 - queue no more work
+	 *     4 - queue wait sync object
+	 */
+	u32 operation_type;
+	u32 reserved;
+	/** Operation data depends on operation type */
+	u64 operation_data[2];
+};
+
+/* Native fence log buffer types. */
+enum vpu_hws_native_fence_log_type {
+	VPU_HWS_NATIVE_FENCE_LOG_TYPE_WAITS = 1,
+	VPU_HWS_NATIVE_FENCE_LOG_TYPE_SIGNALS = 2
+};
+
+/** HWS native fence log buffer header. */
+struct vpu_hws_native_fence_log_header {
+	union {
+		struct {
+			/** Index of the first free entry in buffer. */
+			u32 first_free_entry_idx;
+			/**
+			 * Incremented whenever the NPU wraps around the buffer and writes
+			 * to the first entry again.
+			 */
+			u32 wraparound_count;
+		};
+		/** Field allowing atomic update of both fields above. */
+		u64 atomic_wraparound_and_entry_idx;
+	};
+	/** Log buffer type, see enum vpu_hws_native_fence_log_type. */
+	u64 type;
+	/** Allocated number of entries in the log buffer. */
+	u64 entry_nb;
+	u64 reserved[2];
+};
+
+/** Native fence log operation types. */
+enum vpu_hws_native_fence_log_op {
+	VPU_HWS_NATIVE_FENCE_LOG_OP_SIGNAL_EXECUTED = 0,
+	VPU_HWS_NATIVE_FENCE_LOG_OP_WAIT_UNBLOCKED = 1
+};
+
+/** HWS native fence log entry. */
+struct vpu_hws_native_fence_log_entry {
+	/** Newly signaled/unblocked fence value. */
+	u64 fence_value;
+	/** Native fence object handle to which this operation belongs. */
+	u64 fence_handle;
+	/** Operation type, see enum vpu_hws_native_fence_log_op. */
+	u64 op_type;
+	u64 reserved_0;
+	/**
+	 * VPU_HWS_NATIVE_FENCE_LOG_OP_WAIT_UNBLOCKED only: Timestamp at which fence
+	 * wait was started (in NPU SysTime).
+	 */
+	u64 fence_wait_start_ts;
+	u64 reserved_1;
+	/** Timestamp at which fence operation was completed (in NPU SysTime). */
+	u64 fence_end_ts;
+};
+
+/** Native fence log buffer. */
+struct vpu_hws_native_fence_log_buffer {
+	struct vpu_hws_native_fence_log_header header;
+	struct vpu_hws_native_fence_log_entry entry[];
+};
+
+/*
+ * Host <-> VPU IPC messages types.
+ */
+enum vpu_ipc_msg_type {
+	/** Unsupported command */
+	VPU_JSM_MSG_UNKNOWN = 0xFFFFFFFF,
+
+	/** IPC Host -> Device, base id for async commands */
+	VPU_JSM_MSG_ASYNC_CMD = 0x1100,
+	/**
+	 * Reset engine. The NPU cancels all the jobs currently executing on the target
+	 * engine making the engine become idle and then does a HW reset, before returning
+	 * to the host.
+	 * @see struct vpu_ipc_msg_payload_engine_reset
+	 */
+	VPU_JSM_MSG_ENGINE_RESET = VPU_JSM_MSG_ASYNC_CMD,
+	/**
+	 * Preempt engine. The NPU stops (preempts) all the jobs currently
+	 * executing on the target engine making the engine become idle and ready to
+	 * execute new jobs.
+	 * NOTE: The NPU does not remove unstarted jobs (if any) from job queues of
+	 * the target engine, but it stops processing them (until the queue doorbell
+	 * is rung again); the host is responsible to reset the job queue, either
+	 * after preemption or when resubmitting jobs to the queue.
+	 * @see vpu_ipc_msg_payload_engine_preempt
+	 */
+	VPU_JSM_MSG_ENGINE_PREEMPT = 0x1101,
+	/**
+	 * OS scheduling doorbell register command
+	 * @see vpu_ipc_msg_payload_register_db
+	 */
+	VPU_JSM_MSG_REGISTER_DB = 0x1102,
+	/**
+	 * OS scheduling doorbell unregister command
+	 * @see vpu_ipc_msg_payload_unregister_db
+	 */
+	VPU_JSM_MSG_UNREGISTER_DB = 0x1103,
+	/**
+	 * Query engine heartbeat. Heartbeat is expected to increase monotonically
+	 * and increase while work is being progressed by NPU.
+	 * @see vpu_ipc_msg_payload_query_engine_hb
+	 */
+	VPU_JSM_MSG_QUERY_ENGINE_HB = 0x1104,
+	VPU_JSM_MSG_GET_POWER_LEVEL_COUNT = 0x1105,
+	VPU_JSM_MSG_GET_POWER_LEVEL = 0x1106,
+	VPU_JSM_MSG_SET_POWER_LEVEL = 0x1107,
+	/* @deprecated */
+	VPU_JSM_MSG_METRIC_STREAMER_OPEN = 0x1108,
+	/* @deprecated */
+	VPU_JSM_MSG_METRIC_STREAMER_CLOSE = 0x1109,
+	/** Configure logging (used to modify configuration passed in boot params). */
+	VPU_JSM_MSG_TRACE_SET_CONFIG = 0x110a,
+	/** Return current logging configuration. */
+	VPU_JSM_MSG_TRACE_GET_CONFIG = 0x110b,
+	/**
+	 * Get masks of destinations and HW components supported by the firmware
+	 * (may vary between HW generations and FW compile
+	 * time configurations)
+	 */
+	VPU_JSM_MSG_TRACE_GET_CAPABILITY = 0x110c,
+	/** Get the name of a destination or HW component. */
+	VPU_JSM_MSG_TRACE_GET_NAME = 0x110d,
+	/**
+	 * Release resource associated with host ssid . All jobs that belong to the host_ssid
+	 * aborted and removed from internal scheduling queues. All doorbells assigned
+	 * to the host_ssid are unregistered and any internal FW resources belonging to
+	 * the host_ssid are released.
+	 * @see vpu_ipc_msg_payload_ssid_release
+	 */
+	VPU_JSM_MSG_SSID_RELEASE = 0x110e,
+	/**
+	 * Start collecting metric data.
+	 * @see vpu_jsm_metric_streamer_start
+	 */
+	VPU_JSM_MSG_METRIC_STREAMER_START = 0x110f,
+	/**
+	 * Stop collecting metric data. This command will return success if it is called
+	 * for a metric stream that has already been stopped or was never started.
+	 * @see vpu_jsm_metric_streamer_stop
+	 */
+	VPU_JSM_MSG_METRIC_STREAMER_STOP = 0x1110,
+	/**
+	 * Update current and next buffer for metric data collection. This command can
+	 * also be used to request information about the number of collected samples
+	 * and the amount of data written to the buffer.
+	 * @see vpu_jsm_metric_streamer_update
+	 */
+	VPU_JSM_MSG_METRIC_STREAMER_UPDATE = 0x1111,
+	/**
+	 * Request description of selected metric groups and metric counters within
+	 * each group. The VPU will write the description of groups and counters to
+	 * the buffer specified in the command structure.
+	 * @see vpu_jsm_metric_streamer_start
+	 */
+	VPU_JSM_MSG_METRIC_STREAMER_INFO = 0x1112,
+	/**
+	 * Control command: Priority band setup
+	 * @see vpu_ipc_msg_payload_hws_priority_band_setup
+	 */
+	VPU_JSM_MSG_SET_PRIORITY_BAND_SETUP = 0x1113,
+	/**
+	 * Control command: Create command queue
+	 * @see vpu_ipc_msg_payload_hws_create_cmdq
+	 */
+	VPU_JSM_MSG_CREATE_CMD_QUEUE = 0x1114,
+	/**
+	 * Control command: Destroy command queue
+	 * @see vpu_ipc_msg_payload_hws_destroy_cmdq
+	 */
+	VPU_JSM_MSG_DESTROY_CMD_QUEUE = 0x1115,
+	/**
+	 * Control command: Set context scheduling properties
+	 * @see vpu_ipc_msg_payload_hws_set_context_sched_properties
+	 */
+	VPU_JSM_MSG_SET_CONTEXT_SCHED_PROPERTIES = 0x1116,
+	/**
+	 * Register a doorbell to notify VPU of new work. The doorbell may later be
+	 * deallocated or reassigned to another context.
+	 * @see vpu_jsm_hws_register_db
+	 */
+	VPU_JSM_MSG_HWS_REGISTER_DB = 0x1117,
+	/**
+	 * Control command: Log buffer setting
+	 * @see vpu_ipc_msg_payload_hws_set_scheduling_log
+	 */
+	VPU_JSM_MSG_HWS_SET_SCHEDULING_LOG = 0x1118,
+	/**
+	 * Control command: Suspend command queue.
+	 * @see vpu_ipc_msg_payload_hws_suspend_cmdq
+	 */
+	VPU_JSM_MSG_HWS_SUSPEND_CMDQ = 0x1119,
+	/**
+	 * Control command: Resume command queue
+	 * @see vpu_ipc_msg_payload_hws_resume_cmdq
+	 */
+	VPU_JSM_MSG_HWS_RESUME_CMDQ = 0x111a,
+	/**
+	 * Control command: Resume engine after reset
+	 * @see vpu_ipc_msg_payload_hws_resume_engine
+	 */
+	VPU_JSM_MSG_HWS_ENGINE_RESUME = 0x111b,
+	/**
+	 * Control command: Enable survivability/DCT mode
+	 * @see vpu_ipc_msg_payload_pwr_dct_control
+	 */
+	VPU_JSM_MSG_DCT_ENABLE = 0x111c,
+	/**
+	 * Control command: Disable survivability/DCT mode
+	 * This command has no payload
+	 */
+	VPU_JSM_MSG_DCT_DISABLE = 0x111d,
+	/**
+	 * Dump VPU state. To be used for debug purposes only.
+	 * This command has no payload.
+	 * NOTE: Please introduce new ASYNC commands before this one.
+	 */
+	VPU_JSM_MSG_STATE_DUMP = 0x11FF,
+
+	/** IPC Host -> Device, base id for general commands */
+	VPU_JSM_MSG_GENERAL_CMD = 0x1200,
+	/** Unsupported command */
+	VPU_JSM_MSG_BLOB_DEINIT_DEPRECATED = VPU_JSM_MSG_GENERAL_CMD,
+	/**
+	 * Control dyndbg behavior by executing a dyndbg command; equivalent to
+	 * Linux command:
+	 * @verbatim echo '<dyndbg_cmd>' > <debugfs>/dynamic_debug/control @endverbatim
+	 * @see vpu_ipc_msg_payload_dyndbg_control
+	 */
+	VPU_JSM_MSG_DYNDBG_CONTROL = 0x1201,
+	/**
+	 * Perform the save procedure for the D0i3 entry
+	 */
+	VPU_JSM_MSG_PWR_D0I3_ENTER = 0x1202,
+
+	/**
+	 * IPC Device -> Host, Job completion
+	 * @see struct vpu_ipc_msg_payload_job_done
+	 */
+	VPU_JSM_MSG_JOB_DONE = 0x2100,
+	/**
+	 * IPC Device -> Host, Fence signalled
+	 * @see vpu_ipc_msg_payload_native_fence_signalled
+	 */
+	VPU_JSM_MSG_NATIVE_FENCE_SIGNALLED = 0x2101,
+
+	/* IPC Device -> Host, Async command completion */
+	VPU_JSM_MSG_ASYNC_CMD_DONE = 0x2200,
+	/**
+	 * IPC Device -> Host, engine reset complete
+	 * @see vpu_ipc_msg_payload_engine_reset_done
+	 */
+	VPU_JSM_MSG_ENGINE_RESET_DONE = VPU_JSM_MSG_ASYNC_CMD_DONE,
+	/**
+	 * Preempt complete message
+	 * @see vpu_ipc_msg_payload_engine_preempt_done
+	 */
+	VPU_JSM_MSG_ENGINE_PREEMPT_DONE = 0x2201,
+	VPU_JSM_MSG_REGISTER_DB_DONE = 0x2202,
+	VPU_JSM_MSG_UNREGISTER_DB_DONE = 0x2203,
+	/**
+	 * Response to query engine heartbeat.
+	 * @see vpu_ipc_msg_payload_query_engine_hb_done
+	 */
+	VPU_JSM_MSG_QUERY_ENGINE_HB_DONE = 0x2204,
+	VPU_JSM_MSG_GET_POWER_LEVEL_COUNT_DONE = 0x2205,
+	VPU_JSM_MSG_GET_POWER_LEVEL_DONE = 0x2206,
+	VPU_JSM_MSG_SET_POWER_LEVEL_DONE = 0x2207,
+	/* @deprecated */
+	VPU_JSM_MSG_METRIC_STREAMER_OPEN_DONE = 0x2208,
+	/* @deprecated */
+	VPU_JSM_MSG_METRIC_STREAMER_CLOSE_DONE = 0x2209,
+	/** Response to VPU_JSM_MSG_TRACE_SET_CONFIG. */
+	VPU_JSM_MSG_TRACE_SET_CONFIG_RSP = 0x220a,
+	/** Response to VPU_JSM_MSG_TRACE_GET_CONFIG. */
+	VPU_JSM_MSG_TRACE_GET_CONFIG_RSP = 0x220b,
+	/** Response to VPU_JSM_MSG_TRACE_GET_CAPABILITY. */
+	VPU_JSM_MSG_TRACE_GET_CAPABILITY_RSP = 0x220c,
+	/** Response to VPU_JSM_MSG_TRACE_GET_NAME. */
+	VPU_JSM_MSG_TRACE_GET_NAME_RSP = 0x220d,
+	/**
+	 * Response to VPU_JSM_MSG_SSID_RELEASE.
+	 * @see vpu_ipc_msg_payload_ssid_release
+	 */
+	VPU_JSM_MSG_SSID_RELEASE_DONE = 0x220e,
+	/**
+	 * Response to VPU_JSM_MSG_METRIC_STREAMER_START.
+	 * VPU will return an error result if metric collection cannot be started,
+	 * e.g. when the specified metric mask is invalid.
+	 * @see vpu_jsm_metric_streamer_done
+	 */
+	VPU_JSM_MSG_METRIC_STREAMER_START_DONE = 0x220f,
+	/**
+	 * Response to VPU_JSM_MSG_METRIC_STREAMER_STOP.
+	 * Returns information about collected metric data.
+	 * @see vpu_jsm_metric_streamer_done
+	 */
+	VPU_JSM_MSG_METRIC_STREAMER_STOP_DONE = 0x2210,
+	/**
+	 * Response to VPU_JSM_MSG_METRIC_STREAMER_UPDATE.
+	 * Returns information about collected metric data.
+	 * @see vpu_jsm_metric_streamer_done
+	 */
+	VPU_JSM_MSG_METRIC_STREAMER_UPDATE_DONE = 0x2211,
+	/**
+	 * Response to VPU_JSM_MSG_METRIC_STREAMER_INFO.
+	 * Returns a description of the metric groups and metric counters.
+	 * @see vpu_jsm_metric_streamer_done
+	 */
+	VPU_JSM_MSG_METRIC_STREAMER_INFO_DONE = 0x2212,
+	/**
+	 * Asynchronous event sent from the VPU to the host either when the current
+	 * metric buffer is full or when the VPU has collected a multiple of
+	 * @ref vpu_jsm_metric_streamer_start::notify_sample_count samples as indicated
+	 * through the start command (VPU_JSM_MSG_METRIC_STREAMER_START). Returns
+	 * information about collected metric data.
+	 * @see vpu_jsm_metric_streamer_done
+	 */
+	VPU_JSM_MSG_METRIC_STREAMER_NOTIFICATION = 0x2213,
+	/**
+	 * Response to control command: Priority band setup
+	 * @see vpu_ipc_msg_payload_hws_priority_band_setup
+	 */
+	VPU_JSM_MSG_SET_PRIORITY_BAND_SETUP_RSP = 0x2214,
+	/**
+	 * Response to control command: Create command queue
+	 * @see vpu_ipc_msg_payload_hws_create_cmdq_rsp
+	 */
+	VPU_JSM_MSG_CREATE_CMD_QUEUE_RSP = 0x2215,
+	/**
+	 * Response to control command: Destroy command queue
+	 * @see vpu_ipc_msg_payload_hws_destroy_cmdq
+	 */
+	VPU_JSM_MSG_DESTROY_CMD_QUEUE_RSP = 0x2216,
+	/**
+	 * Response to control command: Set context scheduling properties
+	 * @see vpu_ipc_msg_payload_hws_set_context_sched_properties
+	 */
+	VPU_JSM_MSG_SET_CONTEXT_SCHED_PROPERTIES_RSP = 0x2217,
+	/**
+	 * Response to control command: Log buffer setting
+	 * @see vpu_ipc_msg_payload_hws_set_scheduling_log
+	 */
+	VPU_JSM_MSG_HWS_SET_SCHEDULING_LOG_RSP = 0x2218,
+	/**
+	 * IPC Device -> Host, HWS notify index entry of log buffer written
+	 * @see vpu_ipc_msg_payload_hws_scheduling_log_notification
+	 */
+	VPU_JSM_MSG_HWS_SCHEDULING_LOG_NOTIFICATION = 0x2219,
+	/**
+	 * IPC Device -> Host, HWS completion of a context suspend request
+	 * @see vpu_ipc_msg_payload_hws_suspend_cmdq
+	 */
+	VPU_JSM_MSG_HWS_SUSPEND_CMDQ_DONE = 0x221a,
+	/**
+	 * Response to control command: Resume command queue
+	 * @see vpu_ipc_msg_payload_hws_resume_cmdq
+	 */
+	VPU_JSM_MSG_HWS_RESUME_CMDQ_RSP = 0x221b,
+	/**
+	 * Response to control command: Resume engine command response
+	 * @see vpu_ipc_msg_payload_hws_resume_engine
+	 */
+	VPU_JSM_MSG_HWS_RESUME_ENGINE_DONE = 0x221c,
+	/**
+	 * Response to control command: Enable survivability/DCT mode
+	 * This command has no payload
+	 */
+	VPU_JSM_MSG_DCT_ENABLE_DONE = 0x221d,
+	/**
+	 * Response to control command: Disable survivability/DCT mode
+	 * This command has no payload
+	 */
+	VPU_JSM_MSG_DCT_DISABLE_DONE = 0x221e,
+	/**
+	 * Response to state dump control command.
+	 * This command has no payload.
+	 * NOTE: Please introduce new ASYNC responses before this one.
+	 */
+	VPU_JSM_MSG_STATE_DUMP_RSP = 0x22FF,
+
+	/* IPC Device -> Host, General command completion */
+	VPU_JSM_MSG_GENERAL_CMD_DONE = 0x2300,
+	VPU_JSM_MSG_BLOB_DEINIT_DONE = VPU_JSM_MSG_GENERAL_CMD_DONE,
+	/** Response to VPU_JSM_MSG_DYNDBG_CONTROL. */
+	VPU_JSM_MSG_DYNDBG_CONTROL_RSP = 0x2301,
+	/**
+	 * Acknowledgment of completion of the save procedure initiated by
+	 * VPU_JSM_MSG_PWR_D0I3_ENTER
+	 */
+	VPU_JSM_MSG_PWR_D0I3_ENTER_DONE = 0x2302,
+};
+
+enum vpu_ipc_msg_status { VPU_JSM_MSG_FREE, VPU_JSM_MSG_ALLOCATED };
+
+/**
+ * Engine reset request payload
+ * @see VPU_JSM_MSG_ENGINE_RESET
+ */
+struct vpu_ipc_msg_payload_engine_reset {
+	/** Engine to be reset. */
+	u32 engine_idx;
+	/** Reserved */
+	u32 reserved_0;
+};
+
+/**
+ * Engine preemption request struct
+ * @see VPU_JSM_MSG_ENGINE_PREEMPT
+ */
+struct vpu_ipc_msg_payload_engine_preempt {
+	/** Engine to be preempted. */
+	u32 engine_idx;
+	/** ID of the preemption request. */
+	u32 preempt_id;
+};
+
+/**
+ * Register doorbell command structure.
+ * This structure supports doorbell registration for only OS scheduling.
+ * @see VPU_JSM_MSG_REGISTER_DB
+ */
+struct vpu_ipc_msg_payload_register_db {
+	/** Index of the doorbell to register. */
+	u32 db_idx;
+	/** Reserved */
+	u32 reserved_0;
+	/** Virtual address in Global GTT pointing to the start of job queue. */
+	u64 jobq_base;
+	/** Size of the job queue in bytes. */
+	u32 jobq_size;
+	/** Host sub-stream ID for the context assigned to the doorbell. */
+	u32 host_ssid;
+};
+
+/**
+ * Unregister doorbell command structure.
+ * Request structure to unregister a doorbell for both HW and OS scheduling.
+ * @see VPU_JSM_MSG_UNREGISTER_DB
+ */
+struct vpu_ipc_msg_payload_unregister_db {
+	/** Index of the doorbell to unregister. */
+	u32 db_idx;
+	/** Reserved */
+	u32 reserved_0;
+};
+
+/**
+ * Heartbeat request structure
+ * @see VPU_JSM_MSG_QUERY_ENGINE_HB
+ */
+struct vpu_ipc_msg_payload_query_engine_hb {
+	/** Engine to return heartbeat value. */
+	u32 engine_idx;
+	/** Reserved */
+	u32 reserved_0;
+};
+
+struct vpu_ipc_msg_payload_power_level {
+	/**
+	 * Requested power level. The power level value is in the
+	 * range [0, power_level_count-1] where power_level_count
+	 * is the number of available power levels as returned by
+	 * the get power level count command. A power level of 0
+	 * corresponds to the maximum possible power level, while
+	 * power_level_count-1 corresponds to the minimum possible
+	 * power level. Values outside of this range are not
+	 * considered to be valid.
+	 */
+	u32 power_level;
+	/* Reserved */
+	u32 reserved_0;
+};
+
+/**
+ * Structure for requesting ssid release
+ * @see VPU_JSM_MSG_SSID_RELEASE
+ */
+struct vpu_ipc_msg_payload_ssid_release {
+	/** Host sub-stream ID for the context to be released. */
+	u32 host_ssid;
+	/** Reserved */
+	u32 reserved_0;
+};
+
+/**
+ * @brief Metric streamer start command structure.
+ * This structure is also used with VPU_JSM_MSG_METRIC_STREAMER_INFO to request metric
+ * groups and metric counters description from the firmware.
+ * @see VPU_JSM_MSG_METRIC_STREAMER_START
+ * @see VPU_JSM_MSG_METRIC_STREAMER_INFO
+ */
+struct vpu_jsm_metric_streamer_start {
+	/**
+	 * Bitmask to select the desired metric groups.
+	 * A metric group can belong only to one metric streamer instance at a time.
+	 * Since each metric streamer instance has a unique set of metric groups, it
+	 * can also identify a metric streamer instance if more than one instance was
+	 * started. If the VPU device does not support multiple metric streamer instances,
+	 * then VPU_JSM_MSG_METRIC_STREAMER_START will return an error even if the second
+	 * instance has different groups to the first.
+	 */
+	u64 metric_group_mask;
+	/** Sampling rate in nanoseconds. */
+	u64 sampling_rate;
+	/**
+	 * If > 0 the VPU will send a VPU_JSM_MSG_METRIC_STREAMER_NOTIFICATION message
+	 * after every @ref notify_sample_count samples is collected or dropped by the VPU.
+	 * If set to UINT_MAX the VPU will only generate a notification when the metric
+	 * buffer is full. If set to 0 the VPU will never generate a notification.
+	 */
+	u32 notify_sample_count;
+	u32 reserved_0;
+	/**
+	 * Address and size of the buffer where the VPU will write metric data. The
+	 * VPU writes all counters from enabled metric groups one after another. If
+	 * there is no space left to write data at the next sample period the VPU
+	 * will switch to the next buffer (@ref next_buffer_addr) and will optionally
+	 * send a notification to the host driver if @ref notify_sample_count is non-zero.
+	 * If @ref next_buffer_addr is NULL the VPU will stop collecting metric data.
+	 */
+	u64 buffer_addr;
+	u64 buffer_size;
+	/**
+	 * Address and size of the next buffer to write metric data to after the initial
+	 * buffer is full. If the address is NULL the VPU will stop collecting metric
+	 * data.
+	 */
+	u64 next_buffer_addr;
+	u64 next_buffer_size;
+};
+
+/**
+ * @brief Metric streamer stop command structure.
+ * @see VPU_JSM_MSG_METRIC_STREAMER_STOP
+ */
+struct vpu_jsm_metric_streamer_stop {
+	/** Bitmask to select the desired metric groups. */
+	u64 metric_group_mask;
+};
+
+/**
+ * Provide VPU FW with buffers to write metric data.
+ * @see VPU_JSM_MSG_METRIC_STREAMER_UPDATE
+ */
+struct vpu_jsm_metric_streamer_update {
+	/** Metric group mask that identifies metric streamer instance. */
+	u64 metric_group_mask;
+	/**
+	 * Address and size of the buffer where the VPU will write metric data.
+	 * This member dictates how the update operation should perform:
+	 * 1. client needs information about the number of collected samples and the
+	 *   amount of data written to the current buffer
+	 * 2. client wants to switch to a new buffer
+	 *
+	 * Case 1. is identified by the buffer address being 0 or the same as the
+	 * currently used buffer address. In this case the buffer size is ignored and
+	 * the size of the current buffer is unchanged. The VPU will return an update
+	 * in the vpu_jsm_metric_streamer_done structure. The internal writing position
+	 * into the buffer is not changed.
+	 *
+	 * Case 2. is identified by the address being non-zero and differs from the
+	 * current buffer address. The VPU will immediately switch data collection to
+	 * the new buffer. Then the VPU will return an update in the
+	 * vpu_jsm_metric_streamer_done structure.
+	 */
+	u64 buffer_addr;
+	u64 buffer_size;
+	/**
+	 * Address and size of the next buffer to write metric data after the initial
+	 * buffer is full. If the address is NULL the VPU will stop collecting metric
+	 * data but will continue to record dropped samples.
+	 *
+	 * Note that there is a hazard possible if both buffer_addr and the next_buffer_addr
+	 * are non-zero in same update request. It is the host's responsibility to ensure
+	 * that both addresses make sense even if the VPU just switched to writing samples
+	 * from the current to the next buffer.
+	 */
+	u64 next_buffer_addr;
+	u64 next_buffer_size;
+};
+
+/**
+ * Device -> host job completion message.
+ * @see VPU_JSM_MSG_JOB_DONE
+ */
+struct vpu_ipc_msg_payload_job_done {
+	/** Engine to which the job was submitted. */
+	u32 engine_idx;
+	/** Index of the doorbell to which the job was submitted */
+	u32 db_idx;
+	/** ID of the completed job */
+	u32 job_id;
+	/** Status of the completed job */
+	u32 job_status;
+	/** Host SSID */
+	u32 host_ssid;
+	/** Zero Padding */
+	u32 reserved_0;
+	/** Command queue id */
+	u64 cmdq_id;
+};
+
+/**
+ * Notification message upon native fence signalling.
+ * @see VPU_JSM_MSG_NATIVE_FENCE_SIGNALLED
+ */
+struct vpu_ipc_msg_payload_native_fence_signalled {
+	/** Engine ID. */
+	u32 engine_idx;
+	/** Host SSID. */
+	u32 host_ssid;
+	/** CMDQ ID */
+	u64 cmdq_id;
+	/** Fence object handle. */
+	u64 fence_handle;
+};
+
+/**
+ * vpu_ipc_msg_payload_engine_reset_done will contain an array of this structure
+ * which contains which queues caused reset if FW was able to detect any error.
+ * @see vpu_ipc_msg_payload_engine_reset_done
+ */
+struct vpu_jsm_engine_reset_context {
+	/** Host SSID */
+	u32 host_ssid;
+	/** Zero Padding */
+	u32 reserved_0;
+	/** Command queue id */
+	u64 cmdq_id;
+	/** See VPU_ENGINE_RESET_CONTEXT_* defines */
+	u64 flags;
+};
+
+/**
+ * Engine reset response.
+ * @see VPU_JSM_MSG_ENGINE_RESET_DONE
+ */
+struct vpu_ipc_msg_payload_engine_reset_done {
+	/** Engine ordinal */
+	u32 engine_idx;
+	/** Number of impacted contexts */
+	u32 num_impacted_contexts;
+	/** Array of impacted command queue ids and their flags */
+	struct vpu_jsm_engine_reset_context
+		impacted_contexts[VPU_MAX_ENGINE_RESET_IMPACTED_CONTEXTS];
+};
+
+/**
+ * Preemption response struct
+ * @see VPU_JSM_MSG_ENGINE_PREEMPT_DONE
+ */
+struct vpu_ipc_msg_payload_engine_preempt_done {
+	/** Engine preempted. */
+	u32 engine_idx;
+	/** ID of the preemption request. */
+	u32 preempt_id;
+};
+
+/**
+ * Response structure for register doorbell command for both OS
+ * and HW scheduling.
+ * @see VPU_JSM_MSG_REGISTER_DB
+ * @see VPU_JSM_MSG_HWS_REGISTER_DB
+ */
+struct vpu_ipc_msg_payload_register_db_done {
+	/* Index of the registered doorbell. */
+	u32 db_idx;
+	/* Reserved */
+	u32 reserved_0;
+};
+
+/**
+ * Response structure for unregister doorbell command for both OS
+ * and HW scheduling.
+ * @see VPU_JSM_MSG_UNREGISTER_DB
+ */
+struct vpu_ipc_msg_payload_unregister_db_done {
+	/* Index of the unregistered doorbell. */
+	u32 db_idx;
+	/* Reserved */
+	u32 reserved_0;
+};
+
+/**
+ * Structure for heartbeat response
+ * @see VPU_JSM_MSG_QUERY_ENGINE_HB_DONE
+ */
+struct vpu_ipc_msg_payload_query_engine_hb_done {
+	/** Engine returning heartbeat value. */
+	u32 engine_idx;
+	/** Reserved */
+	u32 reserved_0;
+	/** Heartbeat value. */
+	u64 heartbeat;
+};
+
+struct vpu_ipc_msg_payload_get_power_level_count_done {
+	/**
+	 * Number of supported power levels. The maximum possible
+	 * value of power_level_count is 16 but this may vary across
+	 * implementations.
+	 */
+	u32 power_level_count;
+	/* Reserved */
+	u32 reserved_0;
+	/**
+	 * Power consumption limit for each supported power level in
+	 * [0-100%] range relative to power level 0.
+	 */
+	u8 power_limit[16];
+};
+
+/**
+ * HWS priority band setup request / response
+ * @see VPU_JSM_MSG_SET_PRIORITY_BAND_SETUP
+ */
+struct vpu_ipc_msg_payload_hws_priority_band_setup {
+	/*
+	 * Grace period in 100ns units when preempting another priority band for
+	 * this priority band
+	 */
+	u32 grace_period[VPU_HWS_NUM_PRIORITY_BANDS];
+	/*
+	 * Default quantum in 100ns units for scheduling across processes
+	 * within a priority band
+	 * Minimum value supported by NPU is 1ms (10000 in 100ns units).
+	 */
+	u32 process_quantum[VPU_HWS_NUM_PRIORITY_BANDS];
+	/*
+	 * Default grace period in 100ns units for processes that preempt each
+	 * other within a priority band
+	 */
+	u32 process_grace_period[VPU_HWS_NUM_PRIORITY_BANDS];
+	/*
+	 * For normal priority band, specifies the target VPU percentage
+	 * in situations when it's starved by the focus band.
+	 */
+	u32 normal_band_percentage;
+	/*
+	 * TDR timeout value in milliseconds. Default value of 0 meaning no timeout.
+	 */
+	u32 tdr_timeout;
+	/* Non-interactive queue timeout for no progress of heartbeat in milliseconds.
+	 * Default value of 0 meaning no timeout.
+	 */
+	u32 non_interactive_no_progress_timeout;
+	/*
+	 * Non-interactive queue upper limit timeout value in milliseconds. Default
+	 * value of 0 meaning no timeout.
+	 */
+	u32 non_interactive_timeout;
+};
+
+/**
+ * @brief HWS create command queue request.
+ * Host will create a command queue via this command.
+ * Note: Cmdq group is a handle of an object which
+ * may contain one or more command queues.
+ * @see VPU_JSM_MSG_CREATE_CMD_QUEUE
+ */
+struct vpu_ipc_msg_payload_hws_create_cmdq {
+	/* Process id */
+	u64 process_id;
+	/* Host SSID */
+	u32 host_ssid;
+	/* Engine for which queue is being created */
+	u32 engine_idx;
+	/* Cmdq group: only used for HWS logging of state changes */
+	u64 cmdq_group;
+	/* Command queue id */
+	u64 cmdq_id;
+	/* Command queue base */
+	u64 cmdq_base;
+	/* Command queue size */
+	u32 cmdq_size;
+	/* Zero padding */
+	u32 reserved_0;
+};
+
+/**
+ * HWS create command queue response.
+ * @see VPU_JSM_MSG_CREATE_CMD_QUEUE_RSP
+ */
+struct vpu_ipc_msg_payload_hws_create_cmdq_rsp {
+	/** Process id */
+	u64 process_id;
+	/** Host SSID */
+	u32 host_ssid;
+	/** Engine for which queue is being created */
+	u32 engine_idx;
+	/** Command queue group */
+	u64 cmdq_group;
+	/** Command queue id */
+	u64 cmdq_id;
+};
+
+/**
+ * HWS destroy command queue request / response
+ * @see VPU_JSM_MSG_DESTROY_CMD_QUEUE
+ * @see VPU_JSM_MSG_DESTROY_CMD_QUEUE_RSP
+ */
+struct vpu_ipc_msg_payload_hws_destroy_cmdq {
+	/** Host SSID */
+	u32 host_ssid;
+	/** Zero Padding */
+	u32 reserved;
+	/** Command queue id */
+	u64 cmdq_id;
+};
+
+/**
+ * HWS set context scheduling properties request / response
+ * @see VPU_JSM_MSG_SET_CONTEXT_SCHED_PROPERTIES
+ * @see VPU_JSM_MSG_SET_CONTEXT_SCHED_PROPERTIES_RSP
+ */
+struct vpu_ipc_msg_payload_hws_set_context_sched_properties {
+	/** Host SSID */
+	u32 host_ssid;
+	/** Zero Padding */
+	u32 reserved_0;
+	/** Command queue id */
+	u64 cmdq_id;
+	/**
+	 * Priority band to assign to work of this context.
+	 * Available priority bands: @see enum vpu_job_scheduling_priority_band
+	 */
+	u32 priority_band;
+	/** Inside realtime band assigns a further priority */
+	u32 realtime_priority_level;
+	/** Priority relative to other contexts in the same process */
+	s32 in_process_priority;
+	/** Zero padding / Reserved */
+	u32 reserved_1;
+	/**
+	 * Context quantum relative to other contexts of same priority in the same process
+	 * Minimum value supported by NPU is 1ms (10000 in 100ns units).
+	 */
+	u64 context_quantum;
+	/** Grace period when preempting context of the same priority within the same process */
+	u64 grace_period_same_priority;
+	/** Grace period when preempting context of a lower priority within the same process */
+	u64 grace_period_lower_priority;
+};
+
+/**
+ * Register doorbell command structure.
+ * This structure supports doorbell registration for both HW and OS scheduling.
+ * Note: Queue base and size are added here so that the same structure can be used for
+ * OS scheduling and HW scheduling. For OS scheduling, cmdq_id will be ignored
+ * and cmdq_base and cmdq_size will be used. For HW scheduling, cmdq_base and cmdq_size will be
+ * ignored and cmdq_id is used.
+ * @see VPU_JSM_MSG_HWS_REGISTER_DB
+ */
+struct vpu_jsm_hws_register_db {
+	/** Index of the doorbell to register. */
+	u32 db_id;
+	/** Host sub-stream ID for the context assigned to the doorbell. */
+	u32 host_ssid;
+	/** ID of the command queue associated with the doorbell. */
+	u64 cmdq_id;
+	/** Virtual address pointing to the start of command queue. */
+	u64 cmdq_base;
+	/** Size of the command queue in bytes. */
+	u64 cmdq_size;
+};
+
+/**
+ * Structure to set another buffer to be used for scheduling-related logging.
+ * The size of the logging buffer and the number of entries is defined as part of the
+ * buffer itself as described next.
+ * The log buffer received from the host is made up of;
+ *   - header:     32 bytes in size, as shown in @ref vpu_hws_log_buffer_header.
+ *                 The header contains the number of log entries in the buffer.
+ *   - log entry:  0 to n-1, each log entry is 32 bytes in size, as shown in
+ *                 @ref vpu_hws_log_buffer_entry.
+ *                 The entry contains the VPU timestamp, operation type and data.
+ * The host should provide the notify index value of log buffer to VPU. This is a
+ * value defined within the log buffer and when written to will generate the
+ * scheduling log notification.
+ * The host should set engine_idx and vpu_log_buffer_va to 0 to disable logging
+ * for a particular engine.
+ * VPU will handle one log buffer for each of supported engines.
+ * VPU should allow the logging to consume one host_ssid.
+ * @see VPU_JSM_MSG_HWS_SET_SCHEDULING_LOG
+ * @see VPU_JSM_MSG_HWS_SET_SCHEDULING_LOG_RSP
+ * @see VPU_JSM_MSG_HWS_SCHEDULING_LOG_NOTIFICATION
+ */
+struct vpu_ipc_msg_payload_hws_set_scheduling_log {
+	/** Engine ordinal */
+	u32 engine_idx;
+	/** Host SSID */
+	u32 host_ssid;
+	/**
+	 * VPU log buffer virtual address.
+	 * Set to 0 to disable logging for this engine.
+	 */
+	u64 vpu_log_buffer_va;
+	/**
+	 * Notify index of log buffer. VPU_JSM_MSG_HWS_SCHEDULING_LOG_NOTIFICATION
+	 * is generated when an event log is written to this index.
+	 */
+	u64 notify_index;
+	/**
+	 * Field is now deprecated, will be removed when KMD is updated to support removal
+	 */
+	u32 enable_extra_events;
+	/** Zero Padding */
+	u32 reserved_0;
+};
+
+/**
+ * The scheduling log notification is generated by VPU when it writes
+ * an event into the log buffer at the notify_index. VPU notifies host with
+ * VPU_JSM_MSG_HWS_SCHEDULING_LOG_NOTIFICATION. This is an asynchronous
+ * message from VPU to host.
+ * @see VPU_JSM_MSG_HWS_SCHEDULING_LOG_NOTIFICATION
+ * @see VPU_JSM_MSG_HWS_SET_SCHEDULING_LOG
+ */
+struct vpu_ipc_msg_payload_hws_scheduling_log_notification {
+	/** Engine ordinal */
+	u32 engine_idx;
+	/** Zero Padding */
+	u32 reserved_0;
+};
+
+/**
+ * HWS suspend command queue request and done structure.
+ * Host will request the suspend of contexts and VPU will;
+ *   - Suspend all work on this context
+ *   - Preempt any running work
+ *   - Asynchronously perform the above and return success immediately once
+ *     all items above are started successfully
+ *   - Notify the host of completion of these operations via
+ *     VPU_JSM_MSG_HWS_SUSPEND_CMDQ_DONE
+ *   - Reject any other context operations on a context with an in-flight
+ *     suspend request running
+ * Same structure used when VPU notifies host of completion of a context suspend
+ * request. The ids and suspend fence value reported in this command will match
+ * the one in the request from the host to suspend the context. Once suspend is
+ * complete, VPU will not access any data relating to this command queue until
+ * it is resumed.
+ * @see VPU_JSM_MSG_HWS_SUSPEND_CMDQ
+ * @see VPU_JSM_MSG_HWS_SUSPEND_CMDQ_DONE
+ */
+struct vpu_ipc_msg_payload_hws_suspend_cmdq {
+	/** Host SSID */
+	u32 host_ssid;
+	/** Zero Padding */
+	u32 reserved_0;
+	/** Command queue id */
+	u64 cmdq_id;
+	/**
+	 * Suspend fence value - reported by the VPU suspend context
+	 * completed once suspend is complete.
+	 */
+	u64 suspend_fence_value;
+};
+
+/**
+ * HWS Resume command queue request / response structure.
+ * Host will request the resume of a context;
+ *  - VPU will resume all work on this context
+ *  - Scheduler will allow this context to be scheduled
+ * @see VPU_JSM_MSG_HWS_RESUME_CMDQ
+ * @see VPU_JSM_MSG_HWS_RESUME_CMDQ_RSP
+ */
+struct vpu_ipc_msg_payload_hws_resume_cmdq {
+	/** Host SSID */
+	u32 host_ssid;
+	/** Zero Padding */
+	u32 reserved_0;
+	/** Command queue id */
+	u64 cmdq_id;
+};
+
+/**
+ * HWS Resume engine request / response structure.
+ * After a HWS engine reset, all scheduling is stopped on VPU until an engine resume.
+ * Host shall send this command to resume scheduling of any valid queue.
+ * @see VPU_JSM_MSG_HWS_ENGINE_RESUME
+ * @see VPU_JSM_MSG_HWS_RESUME_ENGINE_DONE
+ */
+struct vpu_ipc_msg_payload_hws_resume_engine {
+	/** Engine to be resumed */
+	u32 engine_idx;
+	/** Reserved */
+	u32 reserved_0;
+};
+
+/**
+ * Payload for VPU_JSM_MSG_TRACE_SET_CONFIG[_RSP] and
+ * VPU_JSM_MSG_TRACE_GET_CONFIG_RSP messages.
+ *
+ * The payload is interpreted differently depending on the type of message:
+ *
+ * - For VPU_JSM_MSG_TRACE_SET_CONFIG, the payload specifies the desired
+ *   logging configuration to be set.
+ *
+ * - For VPU_JSM_MSG_TRACE_SET_CONFIG_RSP, the payload reports the logging
+ *   configuration that was set after a VPU_JSM_MSG_TRACE_SET_CONFIG request.
+ *   The host can compare this payload with the one it sent in the
+ *   VPU_JSM_MSG_TRACE_SET_CONFIG request to check whether or not the
+ *   configuration was set as desired.
+ *
+ * - VPU_JSM_MSG_TRACE_GET_CONFIG_RSP, the payload reports the current logging
+ *   configuration.
+ */
+struct vpu_ipc_msg_payload_trace_config {
+	/**
+	 * Logging level (currently set or to be set); see 'mvLog_t' enum for
+	 * acceptable values. The specified logging level applies to all
+	 * destinations and HW components
+	 */
+	u32 trace_level;
+	/**
+	 * Bitmask of logging destinations (currently enabled or to be enabled);
+	 * bitwise OR of values defined in logging_destination enum.
+	 */
+	u32 trace_destination_mask;
+	/**
+	 * Bitmask of loggable HW components (currently enabled or to be enabled);
+	 * bitwise OR of values defined in loggable_hw_component enum.
+	 */
+	u64 trace_hw_component_mask;
+	u64 reserved_0; /**< Reserved for future extensions. */
+};
+
+/**
+ * Payload for VPU_JSM_MSG_TRACE_GET_CAPABILITY_RSP messages.
+ */
+struct vpu_ipc_msg_payload_trace_capability_rsp {
+	u32 trace_destination_mask; /**< Bitmask of supported logging destinations. */
+	u32 reserved_0;
+	u64 trace_hw_component_mask; /**< Bitmask of supported loggable HW components. */
+	u64 reserved_1; /**< Reserved for future extensions. */
+};
+
+/**
+ * Payload for VPU_JSM_MSG_TRACE_GET_NAME requests.
+ */
+struct vpu_ipc_msg_payload_trace_get_name {
+	/**
+	 * The type of the entity to query name for; see logging_entity_type for
+	 * possible values.
+	 */
+	u32 entity_type;
+	u32 reserved_0;
+	/**
+	 * The ID of the entity to query name for; possible values depends on the
+	 * entity type.
+	 */
+	u64 entity_id;
+};
+
+/**
+ * Payload for VPU_JSM_MSG_TRACE_GET_NAME_RSP responses.
+ */
+struct vpu_ipc_msg_payload_trace_get_name_rsp {
+	/**
+	 * The type of the entity whose name was queried; see logging_entity_type
+	 * for possible values.
+	 */
+	u32 entity_type;
+	u32 reserved_0;
+	/**
+	 * The ID of the entity whose name was queried; possible values depends on
+	 * the entity type.
+	 */
+	u64 entity_id;
+	/** Reserved for future extensions. */
+	u64 reserved_1;
+	/** The name of the entity. */
+	char entity_name[VPU_TRACE_ENTITY_NAME_MAX_LEN];
+};
+
+/**
+ * Data sent from the VPU to the host in all metric streamer response messages
+ * and in asynchronous notification.
+ * @see VPU_JSM_MSG_METRIC_STREAMER_START_DONE
+ * @see VPU_JSM_MSG_METRIC_STREAMER_STOP_DONE
+ * @see VPU_JSM_MSG_METRIC_STREAMER_UPDATE_DONE
+ * @see VPU_JSM_MSG_METRIC_STREAMER_INFO_DONE
+ * @see VPU_JSM_MSG_METRIC_STREAMER_NOTIFICATION
+ */
+struct vpu_jsm_metric_streamer_done {
+	/** Metric group mask that identifies metric streamer instance. */
+	u64 metric_group_mask;
+	/**
+	 * Size in bytes of single sample - total size of all enabled counters.
+	 * Some VPU implementations may align sample_size to more than 8 bytes.
+	 */
+	u32 sample_size;
+	u32 reserved_0;
+	/**
+	 * Number of samples collected since the metric streamer was started.
+	 * This will be 0 if the metric streamer was not started.
+	 */
+	u32 samples_collected;
+	/**
+	 * Number of samples dropped since the metric streamer was started. This
+	 * is incremented every time the metric streamer is not able to write
+	 * collected samples because the current buffer is full and there is no
+	 * next buffer to switch to.
+	 */
+	u32 samples_dropped;
+	/** Address of the buffer that contains the latest metric data. */
+	u64 buffer_addr;
+	/**
+	 * Number of bytes written into the metric data buffer. In response to the
+	 * VPU_JSM_MSG_METRIC_STREAMER_INFO request this field contains the size of
+	 * all group and counter descriptors. The size is updated even if the buffer
+	 * in the request was NULL or too small to hold descriptors of all counters
+	 */
+	u64 bytes_written;
+};
+
+/**
+ * Metric group description placed in the metric buffer after successful completion
+ * of the VPU_JSM_MSG_METRIC_STREAMER_INFO command. This is followed by one or more
+ * @ref vpu_jsm_metric_counter_descriptor records.
+ * @see VPU_JSM_MSG_METRIC_STREAMER_INFO
+ */
+struct vpu_jsm_metric_group_descriptor {
+	/**
+	 * Offset to the next metric group (8-byte aligned). If this offset is 0 this
+	 * is the last descriptor. The value of metric_info_size must be greater than
+	 * or equal to sizeof(struct vpu_jsm_metric_group_descriptor) + name_string_size
+	 * + description_string_size and must be 8-byte aligned.
+	 */
+	u32 next_metric_group_info_offset;
+	/**
+	 * Offset to the first metric counter description record (8-byte aligned).
+	 * @see vpu_jsm_metric_counter_descriptor
+	 */
+	u32 next_metric_counter_info_offset;
+	/** Index of the group. This corresponds to bit index in metric_group_mask. */
+	u32 group_id;
+	/** Number of counters in the metric group. */
+	u32 num_counters;
+	/** Data size for all counters, must be a multiple of 8 bytes.*/
+	u32 metric_group_data_size;
+	/**
+	 * Metric group domain number. Cannot use multiple, simultaneous metric groups
+	 * from the same domain.
+	 */
+	u32 domain;
+	/**
+	 * Counter name string size. The string must include a null termination character.
+	 * The FW may use a fixed size name or send a different name for each counter.
+	 * If the VPU uses fixed size strings, all characters from the end of the name
+	 * to the of the fixed size character array must be zeroed.
+	 */
+	u32 name_string_size;
+	/** Counter description string size, @see name_string_size */
+	u32 description_string_size;
+	u64 reserved_0;
+	/**
+	 * Right after this structure, the VPU writes name and description of
+	 * the metric group.
+	 */
+};
+
+/**
+ * Metric counter description, placed in the buffer after vpu_jsm_metric_group_descriptor.
+ * @see VPU_JSM_MSG_METRIC_STREAMER_INFO
+ */
+struct vpu_jsm_metric_counter_descriptor {
+	/**
+	 * Offset to the next counter in a group (8-byte aligned). If this offset is
+	 * 0 this is the last counter in the group.
+	 */
+	u32 next_metric_counter_info_offset;
+	/**
+	 * Offset to the counter data from the start of samples in this metric group.
+	 * Note that metric_data_offset % metric_data_size must be 0.
+	 */
+	u32 metric_data_offset;
+	/** Size of the metric counter data in bytes. */
+	u32 metric_data_size;
+	/** Metric type, see Level Zero API for definitions. */
+	u32 tier;
+	/** Metric type, see set_metric_type_t for definitions. */
+	u32 metric_type;
+	/** Metric type, see set_value_type_t for definitions. */
+	u32 metric_value_type;
+	/**
+	 * Counter name string size. The string must include a null termination character.
+	 * The FW may use a fixed size name or send a different name for each counter.
+	 * If the VPU uses fixed size strings, all characters from the end of the name
+	 * to the of the fixed size character array must be zeroed.
+	 */
+	u32 name_string_size;
+	/** Counter description string size, @see name_string_size */
+	u32 description_string_size;
+	/** Counter component name string size, @see name_string_size */
+	u32 component_string_size;
+	/** Counter string size, @see name_string_size */
+	u32 units_string_size;
+	u64 reserved_0;
+	/**
+	 * Right after this structure, the VPU writes name, description
+	 * component and unit strings.
+	 */
+};
+
+/**
+ * Payload for @ref VPU_JSM_MSG_DYNDBG_CONTROL requests.
+ *
+ * VPU_JSM_MSG_DYNDBG_CONTROL requests are used to control the VPU FW dynamic debug
+ * feature, which allows developers to selectively enable/disable code to obtain
+ * additional FW information. This is equivalent to the dynamic debug functionality
+ * provided by Linux. The host can control dynamic debug behavior by sending dyndbg
+ * commands, using the same syntax as for Linux dynamic debug commands.
+ *
+ * @see https://www.kernel.org/doc/html/latest/admin-guide/dynamic-debug-howto.html.
+ *
+ * NOTE:
+ * As the dynamic debug feature uses MVLOG messages to provide information, the host
+ * must first set the logging level to MVLOG_DEBUG, using the @ref VPU_JSM_MSG_TRACE_SET_CONFIG
+ * command.
+ */
+struct vpu_ipc_msg_payload_dyndbg_control {
+	/**
+	 * Dyndbg command to be executed.
+	 */
+	char dyndbg_cmd[VPU_DYNDBG_CMD_MAX_LEN];
+};
+
+/**
+ * Payload for VPU_JSM_MSG_PWR_D0I3_ENTER
+ *
+ * This is a bi-directional payload.
+ */
+struct vpu_ipc_msg_payload_pwr_d0i3_enter {
+	/**
+	 * 0: VPU_JSM_MSG_PWR_D0I3_ENTER_DONE is not sent to the host driver
+	 *    The driver will poll for D0i2 Idle state transitions.
+	 * 1: VPU_JSM_MSG_PWR_D0I3_ENTER_DONE is sent after VPU state save is complete
+	 */
+	u32 send_response;
+	u32 reserved_0;
+};
+
+/**
+ * Payload for @ref VPU_JSM_MSG_DCT_ENABLE message.
+ *
+ * Default values for DCT active/inactive times are 5.3ms and 30ms respectively,
+ * corresponding to a 85% duty cycle. This payload allows the host to tune these
+ * values according to application requirements.
+ */
+struct vpu_ipc_msg_payload_pwr_dct_control {
+	/** Duty cycle active time in microseconds */
+	u32 dct_active_us;
+	/** Duty cycle inactive time in microseconds */
+	u32 dct_inactive_us;
+};
+
+/*
+ * Payloads union, used to define complete message format.
+ */
+union vpu_ipc_msg_payload {
+	struct vpu_ipc_msg_payload_engine_reset engine_reset;
+	struct vpu_ipc_msg_payload_engine_preempt engine_preempt;
+	struct vpu_ipc_msg_payload_register_db register_db;
+	struct vpu_ipc_msg_payload_unregister_db unregister_db;
+	struct vpu_ipc_msg_payload_query_engine_hb query_engine_hb;
+	struct vpu_ipc_msg_payload_power_level power_level;
+	struct vpu_jsm_metric_streamer_start metric_streamer_start;
+	struct vpu_jsm_metric_streamer_stop metric_streamer_stop;
+	struct vpu_jsm_metric_streamer_update metric_streamer_update;
+	struct vpu_ipc_msg_payload_ssid_release ssid_release;
+	struct vpu_jsm_hws_register_db hws_register_db;
+	struct vpu_ipc_msg_payload_job_done job_done;
+	struct vpu_ipc_msg_payload_native_fence_signalled native_fence_signalled;
+	struct vpu_ipc_msg_payload_engine_reset_done engine_reset_done;
+	struct vpu_ipc_msg_payload_engine_preempt_done engine_preempt_done;
+	struct vpu_ipc_msg_payload_register_db_done register_db_done;
+	struct vpu_ipc_msg_payload_unregister_db_done unregister_db_done;
+	struct vpu_ipc_msg_payload_query_engine_hb_done query_engine_hb_done;
+	struct vpu_ipc_msg_payload_get_power_level_count_done get_power_level_count_done;
+	struct vpu_jsm_metric_streamer_done metric_streamer_done;
+	struct vpu_ipc_msg_payload_trace_config trace_config;
+	struct vpu_ipc_msg_payload_trace_capability_rsp trace_capability;
+	struct vpu_ipc_msg_payload_trace_get_name trace_get_name;
+	struct vpu_ipc_msg_payload_trace_get_name_rsp trace_get_name_rsp;
+	struct vpu_ipc_msg_payload_dyndbg_control dyndbg_control;
+	struct vpu_ipc_msg_payload_hws_priority_band_setup hws_priority_band_setup;
+	struct vpu_ipc_msg_payload_hws_create_cmdq hws_create_cmdq;
+	struct vpu_ipc_msg_payload_hws_create_cmdq_rsp hws_create_cmdq_rsp;
+	struct vpu_ipc_msg_payload_hws_destroy_cmdq hws_destroy_cmdq;
+	struct vpu_ipc_msg_payload_hws_set_context_sched_properties
+		hws_set_context_sched_properties;
+	struct vpu_ipc_msg_payload_hws_set_scheduling_log hws_set_scheduling_log;
+	struct vpu_ipc_msg_payload_hws_scheduling_log_notification hws_scheduling_log_notification;
+	struct vpu_ipc_msg_payload_hws_suspend_cmdq hws_suspend_cmdq;
+	struct vpu_ipc_msg_payload_hws_resume_cmdq hws_resume_cmdq;
+	struct vpu_ipc_msg_payload_hws_resume_engine hws_resume_engine;
+	struct vpu_ipc_msg_payload_pwr_d0i3_enter pwr_d0i3_enter;
+	struct vpu_ipc_msg_payload_pwr_dct_control pwr_dct_control;
+};
+
+/**
+ * Host <-> NPU IPC message base structure.
+ *
+ * NOTE: All instances of this object must be aligned on a 64B boundary
+ * to allow proper handling of VPU cache operations.
+ */
+struct vpu_jsm_msg {
+	/** Reserved */
+	u64 reserved_0;
+	/** Message type, see @ref vpu_ipc_msg_type. */
+	u32 type;
+	/** Buffer status, see @ref vpu_ipc_msg_status. */
+	u32 status;
+	/**
+	 * Request ID, provided by the host in a request message and passed
+	 * back by VPU in the response message.
+	 */
+	u32 request_id;
+	/** Request return code set by the VPU, see VPU_JSM_STATUS_* defines. */
+	u32 result;
+	u64 reserved_1;
+	/** Message payload depending on message type, see vpu_ipc_msg_payload union. */
+	union vpu_ipc_msg_payload payload;
+};
+
+#pragma pack(pop)
+
+#endif
+
+///@}
diff --git a/drivers/accel/qaic/Kconfig b/drivers/accel/qaic/Kconfig
new file mode 100644
index 000000000000..116e42d152ca
--- /dev/null
+++ b/drivers/accel/qaic/Kconfig
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Qualcomm Cloud AI accelerators driver
+#
+
+config DRM_ACCEL_QAIC
+	tristate "Qualcomm Cloud AI accelerators"
+	depends on DRM_ACCEL
+	depends on PCI && HAS_IOMEM
+	depends on MHI_BUS
+	select CRC32
+	select WANT_DEV_COREDUMP
+	help
+	  Enables driver for Qualcomm's Cloud AI accelerator PCIe cards that are
+	  designed to accelerate Deep Learning inference workloads.
+
+	  The driver manages the PCIe devices and provides an IOCTL interface
+	  for users to submit workloads to the devices.
+
+	  If unsure, say N.
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called qaic.
diff --git a/drivers/accel/qaic/Makefile b/drivers/accel/qaic/Makefile
new file mode 100644
index 000000000000..71f727b74da3
--- /dev/null
+++ b/drivers/accel/qaic/Makefile
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Makefile for Qualcomm Cloud AI accelerators driver
+#
+
+obj-$(CONFIG_DRM_ACCEL_QAIC)	:= qaic.o
+
+qaic-y := \
+	mhi_controller.o \
+	qaic_control.o \
+	qaic_data.o \
+	qaic_drv.o \
+	qaic_ras.o \
+	qaic_ssr.o \
+	qaic_sysfs.o \
+	qaic_timesync.o \
+	sahara.o
+
+qaic-$(CONFIG_DEBUG_FS) += qaic_debugfs.o
diff --git a/drivers/accel/qaic/mhi_controller.c b/drivers/accel/qaic/mhi_controller.c
new file mode 100644
index 000000000000..13a14c6c6168
--- /dev/null
+++ b/drivers/accel/qaic/mhi_controller.c
@@ -0,0 +1,976 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. */
+/* Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. */
+
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/memblock.h>
+#include <linux/mhi.h>
+#include <linux/moduleparam.h>
+#include <linux/pci.h>
+#include <linux/sizes.h>
+
+#include "mhi_controller.h"
+#include "qaic.h"
+
+#define MAX_RESET_TIME_SEC 25
+
+static unsigned int mhi_timeout_ms = 2000; /* 2 sec default */
+module_param(mhi_timeout_ms, uint, 0600);
+MODULE_PARM_DESC(mhi_timeout_ms, "MHI controller timeout value");
+
+static const char *fw_image_paths[FAMILY_MAX] = {
+	[FAMILY_AIC100] = "qcom/aic100/sbl.bin",
+	[FAMILY_AIC200] = "qcom/aic200/sbl.bin",
+};
+
+static const struct mhi_channel_config aic100_channels[] = {
+	{
+		.name = "QAIC_LOOPBACK",
+		.num = 0,
+		.num_elements = 32,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_TO_DEVICE,
+		.ee_mask = MHI_CH_EE_AMSS,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "QAIC_LOOPBACK",
+		.num = 1,
+		.num_elements = 32,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_FROM_DEVICE,
+		.ee_mask = MHI_CH_EE_AMSS,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "QAIC_SAHARA",
+		.num = 2,
+		.num_elements = 32,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_TO_DEVICE,
+		.ee_mask = MHI_CH_EE_SBL,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "QAIC_SAHARA",
+		.num = 3,
+		.num_elements = 32,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_FROM_DEVICE,
+		.ee_mask = MHI_CH_EE_SBL,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "QAIC_DIAG",
+		.num = 4,
+		.num_elements = 32,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_TO_DEVICE,
+		.ee_mask = MHI_CH_EE_AMSS,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "QAIC_DIAG",
+		.num = 5,
+		.num_elements = 32,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_FROM_DEVICE,
+		.ee_mask = MHI_CH_EE_AMSS,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "QAIC_SSR",
+		.num = 6,
+		.num_elements = 32,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_TO_DEVICE,
+		.ee_mask = MHI_CH_EE_AMSS,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "QAIC_SSR",
+		.num = 7,
+		.num_elements = 32,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_FROM_DEVICE,
+		.ee_mask = MHI_CH_EE_AMSS,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "QAIC_QDSS",
+		.num = 8,
+		.num_elements = 32,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_TO_DEVICE,
+		.ee_mask = MHI_CH_EE_AMSS,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "QAIC_QDSS",
+		.num = 9,
+		.num_elements = 32,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_FROM_DEVICE,
+		.ee_mask = MHI_CH_EE_AMSS,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "QAIC_CONTROL",
+		.num = 10,
+		.num_elements = 128,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_TO_DEVICE,
+		.ee_mask = MHI_CH_EE_AMSS,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "QAIC_CONTROL",
+		.num = 11,
+		.num_elements = 128,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_FROM_DEVICE,
+		.ee_mask = MHI_CH_EE_AMSS,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "QAIC_LOGGING",
+		.num = 12,
+		.num_elements = 32,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_TO_DEVICE,
+		.ee_mask = MHI_CH_EE_SBL,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "QAIC_LOGGING",
+		.num = 13,
+		.num_elements = 32,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_FROM_DEVICE,
+		.ee_mask = MHI_CH_EE_SBL,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "QAIC_STATUS",
+		.num = 14,
+		.num_elements = 32,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_TO_DEVICE,
+		.ee_mask = MHI_CH_EE_AMSS,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "QAIC_STATUS",
+		.num = 15,
+		.num_elements = 32,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_FROM_DEVICE,
+		.ee_mask = MHI_CH_EE_AMSS,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "QAIC_TELEMETRY",
+		.num = 16,
+		.num_elements = 32,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_TO_DEVICE,
+		.ee_mask = MHI_CH_EE_AMSS,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "QAIC_TELEMETRY",
+		.num = 17,
+		.num_elements = 32,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_FROM_DEVICE,
+		.ee_mask = MHI_CH_EE_AMSS,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "QAIC_DEBUG",
+		.num = 18,
+		.num_elements = 32,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_TO_DEVICE,
+		.ee_mask = MHI_CH_EE_AMSS,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "QAIC_DEBUG",
+		.num = 19,
+		.num_elements = 32,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_FROM_DEVICE,
+		.ee_mask = MHI_CH_EE_AMSS,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "QAIC_TIMESYNC",
+		.num = 20,
+		.num_elements = 32,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_TO_DEVICE,
+		.ee_mask = MHI_CH_EE_SBL,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "QAIC_TIMESYNC",
+		.num = 21,
+		.num_elements = 32,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_FROM_DEVICE,
+		.ee_mask = MHI_CH_EE_SBL,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "QAIC_TIMESYNC_PERIODIC",
+		.num = 22,
+		.num_elements = 32,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_TO_DEVICE,
+		.ee_mask = MHI_CH_EE_AMSS,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "QAIC_TIMESYNC_PERIODIC",
+		.num = 23,
+		.num_elements = 32,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_FROM_DEVICE,
+		.ee_mask = MHI_CH_EE_AMSS,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "IPCR",
+		.num = 24,
+		.num_elements = 32,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_TO_DEVICE,
+		.ee_mask = MHI_CH_EE_AMSS,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "IPCR",
+		.num = 25,
+		.num_elements = 32,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_FROM_DEVICE,
+		.ee_mask = MHI_CH_EE_AMSS,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = true,
+		.wake_capable = false,
+	},
+};
+
+static const struct mhi_channel_config aic200_channels[] = {
+	{
+		.name = "QAIC_LOOPBACK",
+		.num = 0,
+		.num_elements = 32,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_TO_DEVICE,
+		.ee_mask = MHI_CH_EE_AMSS,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "QAIC_LOOPBACK",
+		.num = 1,
+		.num_elements = 32,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_FROM_DEVICE,
+		.ee_mask = MHI_CH_EE_AMSS,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "QAIC_SAHARA",
+		.num = 2,
+		.num_elements = 32,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_TO_DEVICE,
+		.ee_mask = MHI_CH_EE_SBL,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "QAIC_SAHARA",
+		.num = 3,
+		.num_elements = 32,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_FROM_DEVICE,
+		.ee_mask = MHI_CH_EE_SBL,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "QAIC_SSR",
+		.num = 6,
+		.num_elements = 32,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_TO_DEVICE,
+		.ee_mask = MHI_CH_EE_AMSS,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "QAIC_SSR",
+		.num = 7,
+		.num_elements = 32,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_FROM_DEVICE,
+		.ee_mask = MHI_CH_EE_AMSS,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "QAIC_CONTROL",
+		.num = 10,
+		.num_elements = 128,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_TO_DEVICE,
+		.ee_mask = MHI_CH_EE_AMSS,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "QAIC_CONTROL",
+		.num = 11,
+		.num_elements = 128,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_FROM_DEVICE,
+		.ee_mask = MHI_CH_EE_AMSS,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "QAIC_LOGGING",
+		.num = 12,
+		.num_elements = 32,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_TO_DEVICE,
+		.ee_mask = MHI_CH_EE_SBL,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "QAIC_LOGGING",
+		.num = 13,
+		.num_elements = 32,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_FROM_DEVICE,
+		.ee_mask = MHI_CH_EE_SBL,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "QAIC_STATUS",
+		.num = 14,
+		.num_elements = 32,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_TO_DEVICE,
+		.ee_mask = MHI_CH_EE_AMSS,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "QAIC_STATUS",
+		.num = 15,
+		.num_elements = 32,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_FROM_DEVICE,
+		.ee_mask = MHI_CH_EE_AMSS,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "QAIC_TELEMETRY",
+		.num = 16,
+		.num_elements = 32,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_TO_DEVICE,
+		.ee_mask = MHI_CH_EE_AMSS,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "QAIC_TELEMETRY",
+		.num = 17,
+		.num_elements = 32,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_FROM_DEVICE,
+		.ee_mask = MHI_CH_EE_AMSS,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "QAIC_TIMESYNC_PERIODIC",
+		.num = 22,
+		.num_elements = 32,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_TO_DEVICE,
+		.ee_mask = MHI_CH_EE_AMSS,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "QAIC_TIMESYNC_PERIODIC",
+		.num = 23,
+		.num_elements = 32,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_FROM_DEVICE,
+		.ee_mask = MHI_CH_EE_AMSS,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "IPCR",
+		.num = 24,
+		.num_elements = 32,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_TO_DEVICE,
+		.ee_mask = MHI_CH_EE_AMSS,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = false,
+		.wake_capable = false,
+	},
+	{
+		.name = "IPCR",
+		.num = 25,
+		.num_elements = 32,
+		.local_elements = 0,
+		.event_ring = 0,
+		.dir = DMA_FROM_DEVICE,
+		.ee_mask = MHI_CH_EE_AMSS,
+		.pollcfg = 0,
+		.doorbell = MHI_DB_BRST_DISABLE,
+		.lpm_notify = false,
+		.offload_channel = false,
+		.doorbell_mode_switch = false,
+		.auto_queue = true,
+		.wake_capable = false,
+	},
+};
+
+static struct mhi_event_config aic100_events[] = {
+	{
+		.num_elements = 32,
+		.irq_moderation_ms = 0,
+		.irq = 0,
+		.channel = U32_MAX,
+		.priority = 1,
+		.mode = MHI_DB_BRST_DISABLE,
+		.data_type = MHI_ER_CTRL,
+		.hardware_event = false,
+		.client_managed = false,
+		.offload_channel = false,
+	},
+};
+
+static struct mhi_event_config aic200_events[] = {
+	{
+		.num_elements = 32,
+		.irq_moderation_ms = 0,
+		.irq = 0,
+		.channel = U32_MAX,
+		.priority = 1,
+		.mode = MHI_DB_BRST_DISABLE,
+		.data_type = MHI_ER_CTRL,
+		.hardware_event = false,
+		.client_managed = false,
+		.offload_channel = false,
+	},
+};
+
+static struct mhi_controller_config mhi_cntrl_configs[] = {
+	[FAMILY_AIC100] = {
+		.max_channels = 128,
+		.timeout_ms = 0, /* controlled by mhi_timeout */
+		.buf_len = 0,
+		.num_channels = ARRAY_SIZE(aic100_channels),
+		.ch_cfg = aic100_channels,
+		.num_events = ARRAY_SIZE(aic100_events),
+		.event_cfg = aic100_events,
+		.use_bounce_buf = false,
+		.m2_no_db = false,
+	},
+	[FAMILY_AIC200] = {
+		.max_channels = 128,
+		.timeout_ms = 0, /* controlled by mhi_timeout */
+		.buf_len = 0,
+		.num_channels = ARRAY_SIZE(aic200_channels),
+		.ch_cfg = aic200_channels,
+		.num_events = ARRAY_SIZE(aic200_events),
+		.event_cfg = aic200_events,
+		.use_bounce_buf = false,
+		.m2_no_db = false,
+	},
+};
+
+static int mhi_read_reg(struct mhi_controller *mhi_cntrl, void __iomem *addr, u32 *out)
+{
+	u32 tmp;
+
+	/*
+	 * SOC_HW_VERSION quirk
+	 * The SOC_HW_VERSION register (offset 0x224) is not reliable and
+	 * may contain uninitialized values, including 0xFFFFFFFF. This could
+	 * cause a false positive link down error.  Instead, intercept any
+	 * reads and provide the correct value of the register.
+	 */
+	if (addr - mhi_cntrl->regs == 0x224) {
+		*out = 0x60110200;
+		return 0;
+	}
+
+	tmp = readl_relaxed(addr);
+	if (tmp == U32_MAX)
+		return -EIO;
+
+	*out = tmp;
+
+	return 0;
+}
+
+static void mhi_write_reg(struct mhi_controller *mhi_cntrl, void __iomem *addr, u32 val)
+{
+	writel_relaxed(val, addr);
+}
+
+static int mhi_runtime_get(struct mhi_controller *mhi_cntrl)
+{
+	return 0;
+}
+
+static void mhi_runtime_put(struct mhi_controller *mhi_cntrl)
+{
+}
+
+static void mhi_status_cb(struct mhi_controller *mhi_cntrl, enum mhi_callback reason)
+{
+	struct qaic_device *qdev = pci_get_drvdata(to_pci_dev(mhi_cntrl->cntrl_dev));
+
+	/* this event occurs in atomic context */
+	if (reason == MHI_CB_FATAL_ERROR)
+		pci_err(qdev->pdev, "Fatal error received from device. Attempting to recover\n");
+	/* this event occurs in non-atomic context */
+	if (reason == MHI_CB_SYS_ERROR)
+		qaic_dev_reset_clean_local_state(qdev);
+}
+
+static int mhi_reset_and_async_power_up(struct mhi_controller *mhi_cntrl)
+{
+	u8 time_sec = 1;
+	int current_ee;
+	int ret;
+
+	/* Reset the device to bring the device in PBL EE */
+	mhi_soc_reset(mhi_cntrl);
+
+	/*
+	 * Keep checking the execution environment(EE) after every 1 second
+	 * interval.
+	 */
+	do {
+		msleep(1000);
+		current_ee = mhi_get_exec_env(mhi_cntrl);
+	} while (current_ee != MHI_EE_PBL && time_sec++ <= MAX_RESET_TIME_SEC);
+
+	/* If the device is in PBL EE retry power up */
+	if (current_ee == MHI_EE_PBL)
+		ret = mhi_async_power_up(mhi_cntrl);
+	else
+		ret = -EIO;
+
+	return ret;
+}
+
+struct mhi_controller *qaic_mhi_register_controller(struct pci_dev *pci_dev, void __iomem *mhi_bar,
+						    int mhi_irq, bool shared_msi, int family)
+{
+	struct mhi_controller_config mhi_config = mhi_cntrl_configs[family];
+	struct mhi_controller *mhi_cntrl;
+	int ret;
+
+	mhi_cntrl = devm_kzalloc(&pci_dev->dev, sizeof(*mhi_cntrl), GFP_KERNEL);
+	if (!mhi_cntrl)
+		return ERR_PTR(-ENOMEM);
+
+	mhi_cntrl->cntrl_dev = &pci_dev->dev;
+
+	/*
+	 * Covers the entire possible physical ram region. Remote side is
+	 * going to calculate a size of this range, so subtract 1 to prevent
+	 * rollover.
+	 */
+	mhi_cntrl->iova_start = 0;
+	mhi_cntrl->iova_stop = PHYS_ADDR_MAX - 1;
+	mhi_cntrl->status_cb = mhi_status_cb;
+	mhi_cntrl->runtime_get = mhi_runtime_get;
+	mhi_cntrl->runtime_put = mhi_runtime_put;
+	mhi_cntrl->read_reg = mhi_read_reg;
+	mhi_cntrl->write_reg = mhi_write_reg;
+	mhi_cntrl->regs = mhi_bar;
+	mhi_cntrl->reg_len = SZ_4K;
+	mhi_cntrl->nr_irqs = 1;
+	mhi_cntrl->irq = devm_kmalloc(&pci_dev->dev, sizeof(*mhi_cntrl->irq), GFP_KERNEL);
+
+	if (!mhi_cntrl->irq)
+		return ERR_PTR(-ENOMEM);
+
+	mhi_cntrl->irq[0] = mhi_irq;
+
+	if (shared_msi) /* MSI shared with data path, no IRQF_NO_SUSPEND */
+		mhi_cntrl->irq_flags = IRQF_SHARED;
+
+	mhi_cntrl->fw_image = fw_image_paths[family];
+
+	if (family == FAMILY_AIC200) {
+		mhi_cntrl->name = "AIC200";
+		mhi_cntrl->seg_len = SZ_512K;
+	} else {
+		mhi_cntrl->name = "AIC100";
+	}
+
+	/* use latest configured timeout */
+	mhi_config.timeout_ms = mhi_timeout_ms;
+	ret = mhi_register_controller(mhi_cntrl, &mhi_config);
+	if (ret) {
+		pci_err(pci_dev, "mhi_register_controller failed %d\n", ret);
+		return ERR_PTR(ret);
+	}
+
+	ret = mhi_prepare_for_power_up(mhi_cntrl);
+	if (ret) {
+		pci_err(pci_dev, "mhi_prepare_for_power_up failed %d\n", ret);
+		goto prepare_power_up_fail;
+	}
+
+	ret = mhi_async_power_up(mhi_cntrl);
+	/*
+	 * If EIO is returned it is possible that device is in SBL EE, which is
+	 * undesired. SOC reset the device and try to power up again.
+	 */
+	if (ret == -EIO && MHI_EE_SBL == mhi_get_exec_env(mhi_cntrl)) {
+		pci_err(pci_dev, "Found device in SBL at MHI init. Attempting a reset.\n");
+		ret = mhi_reset_and_async_power_up(mhi_cntrl);
+	}
+
+	if (ret) {
+		pci_err(pci_dev, "mhi_async_power_up failed %d\n", ret);
+		goto power_up_fail;
+	}
+
+	return mhi_cntrl;
+
+power_up_fail:
+	mhi_unprepare_after_power_down(mhi_cntrl);
+prepare_power_up_fail:
+	mhi_unregister_controller(mhi_cntrl);
+	return ERR_PTR(ret);
+}
+
+void qaic_mhi_free_controller(struct mhi_controller *mhi_cntrl, bool link_up)
+{
+	mhi_power_down(mhi_cntrl, link_up);
+	mhi_unprepare_after_power_down(mhi_cntrl);
+	mhi_unregister_controller(mhi_cntrl);
+}
+
+void qaic_mhi_start_reset(struct mhi_controller *mhi_cntrl)
+{
+	mhi_power_down(mhi_cntrl, true);
+}
+
+void qaic_mhi_reset_done(struct mhi_controller *mhi_cntrl)
+{
+	struct pci_dev *pci_dev = container_of(mhi_cntrl->cntrl_dev, struct pci_dev, dev);
+	int ret;
+
+	ret = mhi_async_power_up(mhi_cntrl);
+	if (ret)
+		pci_err(pci_dev, "mhi_async_power_up failed after reset %d\n", ret);
+}
diff --git a/drivers/accel/qaic/mhi_controller.h b/drivers/accel/qaic/mhi_controller.h
new file mode 100644
index 000000000000..8939f6ae185e
--- /dev/null
+++ b/drivers/accel/qaic/mhi_controller.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only
+ *
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef MHICONTROLLERQAIC_H_
+#define MHICONTROLLERQAIC_H_
+
+struct mhi_controller *qaic_mhi_register_controller(struct pci_dev *pci_dev, void __iomem *mhi_bar,
+						    int mhi_irq, bool shared_msi, int family);
+void qaic_mhi_free_controller(struct mhi_controller *mhi_cntrl, bool link_up);
+void qaic_mhi_start_reset(struct mhi_controller *mhi_cntrl);
+void qaic_mhi_reset_done(struct mhi_controller *mhi_cntrl);
+
+#endif /* MHICONTROLLERQAIC_H_ */
diff --git a/drivers/accel/qaic/qaic.h b/drivers/accel/qaic/qaic.h
new file mode 100644
index 000000000000..fa7a8155658c
--- /dev/null
+++ b/drivers/accel/qaic/qaic.h
@@ -0,0 +1,360 @@
+/* SPDX-License-Identifier: GPL-2.0-only
+ *
+ * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _QAIC_H_
+#define _QAIC_H_
+
+#include <linux/interrupt.h>
+#include <linux/kref.h>
+#include <linux/mhi.h>
+#include <linux/mutex.h>
+#include <linux/pci.h>
+#include <linux/spinlock.h>
+#include <linux/srcu.h>
+#include <linux/wait.h>
+#include <linux/workqueue.h>
+#include <drm/drm_device.h>
+#include <drm/drm_gem.h>
+
+#define QAIC_DBC_BASE		SZ_128K
+#define QAIC_DBC_SIZE		SZ_4K
+#define QAIC_SSR_DBC_SENTINEL	U32_MAX /* No ongoing SSR sentinel */
+
+#define QAIC_NO_PARTITION	-1
+
+#define QAIC_DBC_OFF(i)		((i) * QAIC_DBC_SIZE + QAIC_DBC_BASE)
+
+#define to_qaic_bo(obj) container_of(obj, struct qaic_bo, base)
+#define to_qaic_drm_device(dev) container_of(dev, struct qaic_drm_device, drm)
+#define to_drm(qddev) (&(qddev)->drm)
+#define to_accel_kdev(qddev) (to_drm(qddev)->accel->kdev) /* Return Linux device of accel node */
+#define to_qaic_device(dev) (to_qaic_drm_device((dev))->qdev)
+
+enum aic_families {
+	FAMILY_AIC100,
+	FAMILY_AIC200,
+	FAMILY_MAX,
+};
+
+enum __packed dev_states {
+	/* Device is offline or will be very soon */
+	QAIC_OFFLINE,
+	/* Device is booting, not clear if it's in a usable state */
+	QAIC_BOOT,
+	/* Device is fully operational */
+	QAIC_ONLINE,
+};
+
+enum dbc_states {
+	/* DBC is free and can be activated */
+	DBC_STATE_IDLE,
+	/* DBC is activated and a workload is running on device */
+	DBC_STATE_ASSIGNED,
+	/* Sub-system associated with this workload has crashed and it will shutdown soon */
+	DBC_STATE_BEFORE_SHUTDOWN,
+	/* Sub-system associated with this workload has crashed and it has shutdown */
+	DBC_STATE_AFTER_SHUTDOWN,
+	/* Sub-system associated with this workload is shutdown and it will be powered up soon */
+	DBC_STATE_BEFORE_POWER_UP,
+	/* Sub-system associated with this workload is now powered up */
+	DBC_STATE_AFTER_POWER_UP,
+	DBC_STATE_MAX,
+};
+
+extern bool datapath_polling;
+
+struct qaic_user {
+	/* Uniquely identifies this user for the device */
+	int			handle;
+	struct kref		ref_count;
+	/* Char device opened by this user */
+	struct qaic_drm_device	*qddev;
+	/* Node in list of users that opened this drm device */
+	struct list_head	node;
+	/* SRCU used to synchronize this user during cleanup */
+	struct srcu_struct	qddev_lock;
+	atomic_t		chunk_id;
+};
+
+struct dma_bridge_chan {
+	/* Pointer to device strcut maintained by driver */
+	struct qaic_device	*qdev;
+	/* ID of this DMA bridge channel(DBC) */
+	unsigned int		id;
+	/* Synchronizes access to xfer_list */
+	spinlock_t		xfer_lock;
+	/* Base address of request queue */
+	void			*req_q_base;
+	/* Base address of response queue */
+	void			*rsp_q_base;
+	/*
+	 * Base bus address of request queue. Response queue bus address can be
+	 * calculated by adding request queue size to this variable
+	 */
+	dma_addr_t		dma_addr;
+	/* Total size of request and response queue in byte */
+	u32			total_size;
+	/* Capacity of request/response queue */
+	u32			nelem;
+	/* The user that opened this DBC */
+	struct qaic_user	*usr;
+	/*
+	 * Request ID of next memory handle that goes in request queue. One
+	 * memory handle can enqueue more than one request elements, all
+	 * this requests that belong to same memory handle have same request ID
+	 */
+	u16			next_req_id;
+	/* true: DBC is in use; false: DBC not in use */
+	bool			in_use;
+	/*
+	 * Base address of device registers. Used to read/write request and
+	 * response queue's head and tail pointer of this DBC.
+	 */
+	void __iomem		*dbc_base;
+	/* Synchronizes access to Request queue's head and tail pointer */
+	struct mutex		req_lock;
+	/* Head of list where each node is a memory handle queued in request queue */
+	struct list_head	xfer_list;
+	/* Synchronizes DBC readers during cleanup */
+	struct srcu_struct	ch_lock;
+	/*
+	 * When this DBC is released, any thread waiting on this wait queue is
+	 * woken up
+	 */
+	wait_queue_head_t	dbc_release;
+	/* Head of list where each node is a bo associated with this DBC */
+	struct list_head	bo_lists;
+	/* The irq line for this DBC. Used for polling */
+	unsigned int		irq;
+	/* Polling work item to simulate interrupts */
+	struct work_struct	poll_work;
+	/* Represents various states of this DBC from enum dbc_states */
+	unsigned int		state;
+};
+
+struct qaic_device {
+	/* Pointer to base PCI device struct of our physical device */
+	struct pci_dev		*pdev;
+	/* Req. ID of request that will be queued next in MHI control device */
+	u32			next_seq_num;
+	/* Base address of the MHI bar */
+	void __iomem		*bar_mhi;
+	/* Base address of the DBCs bar */
+	void __iomem		*bar_dbc;
+	/* Controller structure for MHI devices */
+	struct mhi_controller	*mhi_cntrl;
+	/* MHI control channel device */
+	struct mhi_device	*cntl_ch;
+	/* List of requests queued in MHI control device */
+	struct list_head	cntl_xfer_list;
+	/* Synchronizes MHI control device transactions and its xfer list */
+	struct mutex		cntl_mutex;
+	/* Array of DBC struct of this device */
+	struct dma_bridge_chan	*dbc;
+	/* Work queue for tasks related to MHI control device */
+	struct workqueue_struct	*cntl_wq;
+	/* Synchronizes all the users of device during cleanup */
+	struct srcu_struct	dev_lock;
+	/* Track the state of the device during resets */
+	enum dev_states		dev_state;
+	/* true: single MSI is used to operate device */
+	bool			single_msi;
+	/*
+	 * true: A tx MHI transaction has failed and a rx buffer is still queued
+	 * in control device. Such a buffer is considered lost rx buffer
+	 * false: No rx buffer is lost in control device
+	 */
+	bool			cntl_lost_buf;
+	/* Maximum number of DBC supported by this device */
+	u32			num_dbc;
+	/* Reference to the drm_device for this device when it is created */
+	struct qaic_drm_device	*qddev;
+	/* Generate the CRC of a control message */
+	u32 (*gen_crc)(void *msg);
+	/* Validate the CRC of a control message */
+	bool (*valid_crc)(void *msg);
+	/* MHI "QAIC_TIMESYNC" channel device */
+	struct mhi_device	*qts_ch;
+	/* Work queue for tasks related to MHI "QAIC_TIMESYNC" channel */
+	struct workqueue_struct	*qts_wq;
+	/* MHI "QAIC_TIMESYNC_PERIODIC" channel device */
+	struct mhi_device	*mqts_ch;
+	/* Head of list of page allocated by MHI bootlog device */
+	struct list_head        bootlog;
+	/* MHI bootlog channel device */
+	struct mhi_device       *bootlog_ch;
+	/* Work queue for tasks related to MHI bootlog device */
+	struct workqueue_struct *bootlog_wq;
+	/* Synchronizes access of pages in MHI bootlog device */
+	struct mutex            bootlog_mutex;
+	/* MHI RAS channel device */
+	struct mhi_device	*ras_ch;
+	/* Correctable error count */
+	unsigned int		ce_count;
+	/* Un-correctable error count */
+	unsigned int		ue_count;
+	/* Un-correctable non-fatal error count */
+	unsigned int		ue_nf_count;
+	/* MHI SSR channel device */
+	struct mhi_device	*ssr_ch;
+	/* Work queue for tasks related to MHI SSR device */
+	struct workqueue_struct	*ssr_wq;
+	/* Buffer to collect SSR crashdump via SSR MHI channel */
+	void			*ssr_mhi_buf;
+	/* DBC which is under SSR. Sentinel U32_MAX would mean that no SSR in progress */
+	u32			ssr_dbc;
+};
+
+struct qaic_drm_device {
+	/* The drm device struct of this drm device */
+	struct drm_device	drm;
+	/* Pointer to the root device struct driven by this driver */
+	struct qaic_device	*qdev;
+	/*
+	 * The physical device can be partition in number of logical devices.
+	 * And each logical device is given a partition id. This member stores
+	 * that id. QAIC_NO_PARTITION is a sentinel used to mark that this drm
+	 * device is the actual physical device
+	 */
+	s32			partition_id;
+	/* Head in list of users who have opened this drm device */
+	struct list_head	users;
+	/* Synchronizes access to users list */
+	struct mutex		users_mutex;
+	/* Pointer to array of DBC sysfs attributes */
+	void			*sysfs_attrs;
+};
+
+struct qaic_bo {
+	struct drm_gem_object	base;
+	/* Scatter/gather table for allocate/imported BO */
+	struct sg_table		*sgt;
+	/* Head in list of slices of this BO */
+	struct list_head	slices;
+	/* Total nents, for all slices of this BO */
+	int			total_slice_nents;
+	/*
+	 * Direction of transfer. It can assume only two value DMA_TO_DEVICE and
+	 * DMA_FROM_DEVICE.
+	 */
+	int			dir;
+	/* The pointer of the DBC which operates on this BO */
+	struct dma_bridge_chan	*dbc;
+	/* Number of slice that belongs to this buffer */
+	u32			nr_slice;
+	/* Number of slice that have been transferred by DMA engine */
+	u32			nr_slice_xfer_done;
+	/*
+	 * If true then user has attached slicing information to this BO by
+	 * calling DRM_IOCTL_QAIC_ATTACH_SLICE_BO ioctl.
+	 */
+	bool			sliced;
+	/* Request ID of this BO if it is queued for execution */
+	u16			req_id;
+	/* Wait on this for completion of DMA transfer of this BO */
+	struct completion	xfer_done;
+	/*
+	 * Node in linked list where head is dbc->xfer_list.
+	 * This link list contain BO's that are queued for DMA transfer.
+	 */
+	struct list_head	xfer_list;
+	/*
+	 * Node in linked list where head is dbc->bo_lists.
+	 * This link list contain BO's that are associated with the DBC it is
+	 * linked to.
+	 */
+	struct list_head	bo_list;
+	struct {
+		/*
+		 * Latest timestamp(ns) at which kernel received a request to
+		 * execute this BO
+		 */
+		u64		req_received_ts;
+		/*
+		 * Latest timestamp(ns) at which kernel enqueued requests of
+		 * this BO for execution in DMA queue
+		 */
+		u64		req_submit_ts;
+		/*
+		 * Latest timestamp(ns) at which kernel received a completion
+		 * interrupt for requests of this BO
+		 */
+		u64		req_processed_ts;
+		/*
+		 * Number of elements already enqueued in DMA queue before
+		 * enqueuing requests of this BO
+		 */
+		u32		queue_level_before;
+	} perf_stats;
+	/* Synchronizes BO operations */
+	struct mutex		lock;
+};
+
+struct bo_slice {
+	/* Mapped pages */
+	struct sg_table		*sgt;
+	/* Number of requests required to queue in DMA queue */
+	int			nents;
+	/* See enum dma_data_direction */
+	int			dir;
+	/* Actual requests that will be copied in DMA queue */
+	struct dbc_req		*reqs;
+	struct kref		ref_count;
+	/* true: No DMA transfer required */
+	bool			no_xfer;
+	/* Pointer to the parent BO handle */
+	struct qaic_bo		*bo;
+	/* Node in list of slices maintained by parent BO */
+	struct list_head	slice;
+	/* Size of this slice in bytes */
+	u64			size;
+	/* Offset of this slice in buffer */
+	u64			offset;
+};
+
+int get_dbc_req_elem_size(void);
+int get_dbc_rsp_elem_size(void);
+int get_cntl_version(struct qaic_device *qdev, struct qaic_user *usr, u16 *major, u16 *minor);
+int qaic_manage_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
+void qaic_mhi_ul_xfer_cb(struct mhi_device *mhi_dev, struct mhi_result *mhi_result);
+
+void qaic_mhi_dl_xfer_cb(struct mhi_device *mhi_dev, struct mhi_result *mhi_result);
+
+int qaic_control_open(struct qaic_device *qdev);
+void qaic_control_close(struct qaic_device *qdev);
+void qaic_release_usr(struct qaic_device *qdev, struct qaic_user *usr);
+
+irqreturn_t dbc_irq_threaded_fn(int irq, void *data);
+irqreturn_t dbc_irq_handler(int irq, void *data);
+int disable_dbc(struct qaic_device *qdev, u32 dbc_id, struct qaic_user *usr);
+void enable_dbc(struct qaic_device *qdev, u32 dbc_id, struct qaic_user *usr);
+void wakeup_dbc(struct qaic_device *qdev, u32 dbc_id);
+void release_dbc(struct qaic_device *qdev, u32 dbc_id);
+void qaic_data_get_fifo_info(struct dma_bridge_chan *dbc, u32 *head, u32 *tail);
+
+void wake_all_cntl(struct qaic_device *qdev);
+void qaic_dev_reset_clean_local_state(struct qaic_device *qdev);
+
+struct drm_gem_object *qaic_gem_prime_import(struct drm_device *dev, struct dma_buf *dma_buf);
+
+int qaic_create_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
+int qaic_mmap_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
+int qaic_attach_slice_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
+int qaic_execute_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
+int qaic_partial_execute_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
+int qaic_wait_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
+int qaic_perf_stats_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
+int qaic_detach_slice_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv);
+void qaic_irq_polling_work(struct work_struct *work);
+void qaic_dbc_enter_ssr(struct qaic_device *qdev, u32 dbc_id);
+void qaic_dbc_exit_ssr(struct qaic_device *qdev);
+
+/* qaic_sysfs.c */
+int qaic_sysfs_init(struct qaic_drm_device *qddev);
+void qaic_sysfs_remove(struct qaic_drm_device *qddev);
+void set_dbc_state(struct qaic_device *qdev, u32 dbc_id, unsigned int state);
+
+#endif /* _QAIC_H_ */
diff --git a/drivers/accel/qaic/qaic_control.c b/drivers/accel/qaic/qaic_control.c
new file mode 100644
index 000000000000..428d8f65bff3
--- /dev/null
+++ b/drivers/accel/qaic/qaic_control.c
@@ -0,0 +1,1560 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. */
+/* Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. */
+
+#include <asm/byteorder.h>
+#include <linux/completion.h>
+#include <linux/crc32.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/kref.h>
+#include <linux/list.h>
+#include <linux/mhi.h>
+#include <linux/mm.h>
+#include <linux/moduleparam.h>
+#include <linux/mutex.h>
+#include <linux/overflow.h>
+#include <linux/pci.h>
+#include <linux/scatterlist.h>
+#include <linux/sched/signal.h>
+#include <linux/types.h>
+#include <linux/uaccess.h>
+#include <linux/workqueue.h>
+#include <linux/wait.h>
+#include <drm/drm_device.h>
+#include <drm/drm_file.h>
+#include <uapi/drm/qaic_accel.h>
+
+#include "qaic.h"
+
+#define MANAGE_MAGIC_NUMBER		((__force __le32)0x43494151) /* "QAIC" in little endian */
+#define QAIC_DBC_Q_GAP			SZ_256
+#define QAIC_DBC_Q_BUF_ALIGN		SZ_4K
+#define QAIC_MANAGE_WIRE_MSG_LENGTH	SZ_64K /* Max DMA message length */
+#define QAIC_WRAPPER_MAX_SIZE		SZ_4K
+#define QAIC_MHI_RETRY_WAIT_MS		100
+#define QAIC_MHI_RETRY_MAX		20
+
+static unsigned int control_resp_timeout_s = 60; /* 60 sec default */
+module_param(control_resp_timeout_s, uint, 0600);
+MODULE_PARM_DESC(control_resp_timeout_s, "Timeout for NNC responses from QSM");
+
+struct manage_msg {
+	u32 len;
+	u32 count;
+	u8 data[];
+};
+
+/*
+ * wire encoding structures for the manage protocol.
+ * All fields are little endian on the wire
+ */
+struct wire_msg_hdr {
+	__le32 crc32; /* crc of everything following this field in the message */
+	__le32 magic_number;
+	__le32 sequence_number;
+	__le32 len; /* length of this message */
+	__le32 count; /* number of transactions in this message */
+	__le32 handle; /* unique id to track the resources consumed */
+	__le32 partition_id; /* partition id for the request (signed) */
+	__le32 padding; /* must be 0 */
+} __packed;
+
+struct wire_msg {
+	struct wire_msg_hdr hdr;
+	u8 data[];
+} __packed;
+
+struct wire_trans_hdr {
+	__le32 type;
+	__le32 len;
+} __packed;
+
+/* Each message sent from driver to device are organized in a list of wrapper_msg */
+struct wrapper_msg {
+	struct list_head list;
+	struct kref ref_count;
+	u32 len; /* length of data to transfer */
+	struct wrapper_list *head;
+	union {
+		struct wire_msg msg;
+		struct wire_trans_hdr trans;
+	};
+};
+
+struct wrapper_list {
+	struct list_head list;
+	spinlock_t lock; /* Protects the list state during additions and removals */
+};
+
+struct wire_trans_passthrough {
+	struct wire_trans_hdr hdr;
+	u8 data[];
+} __packed;
+
+struct wire_addr_size_pair {
+	__le64 addr;
+	__le64 size;
+} __packed;
+
+struct wire_trans_dma_xfer {
+	struct wire_trans_hdr hdr;
+	__le32 tag;
+	__le32 count;
+	__le32 dma_chunk_id;
+	__le32 padding;
+	struct wire_addr_size_pair data[];
+} __packed;
+
+/* Initiated by device to continue the DMA xfer of a large piece of data */
+struct wire_trans_dma_xfer_cont {
+	struct wire_trans_hdr hdr;
+	__le32 dma_chunk_id;
+	__le32 padding;
+	__le64 xferred_size;
+} __packed;
+
+struct wire_trans_activate_to_dev {
+	struct wire_trans_hdr hdr;
+	__le64 req_q_addr;
+	__le64 rsp_q_addr;
+	__le32 req_q_size;
+	__le32 rsp_q_size;
+	__le32 buf_len;
+	__le32 options; /* unused, but BIT(16) has meaning to the device */
+} __packed;
+
+struct wire_trans_activate_from_dev {
+	struct wire_trans_hdr hdr;
+	__le32 status;
+	__le32 dbc_id;
+	__le64 options; /* unused */
+} __packed;
+
+struct wire_trans_deactivate_from_dev {
+	struct wire_trans_hdr hdr;
+	__le32 status;
+	__le32 dbc_id;
+} __packed;
+
+struct wire_trans_terminate_to_dev {
+	struct wire_trans_hdr hdr;
+	__le32 handle;
+	__le32 padding;
+} __packed;
+
+struct wire_trans_terminate_from_dev {
+	struct wire_trans_hdr hdr;
+	__le32 status;
+	__le32 padding;
+} __packed;
+
+struct wire_trans_status_to_dev {
+	struct wire_trans_hdr hdr;
+} __packed;
+
+struct wire_trans_status_from_dev {
+	struct wire_trans_hdr hdr;
+	__le16 major;
+	__le16 minor;
+	__le32 status;
+	__le64 status_flags;
+} __packed;
+
+struct wire_trans_validate_part_to_dev {
+	struct wire_trans_hdr hdr;
+	__le32 part_id;
+	__le32 padding;
+} __packed;
+
+struct wire_trans_validate_part_from_dev {
+	struct wire_trans_hdr hdr;
+	__le32 status;
+	__le32 padding;
+} __packed;
+
+struct xfer_queue_elem {
+	/*
+	 * Node in list of ongoing transfer request on control channel.
+	 * Maintained by root device struct.
+	 */
+	struct list_head list;
+	/* Sequence number of this transfer request */
+	u32 seq_num;
+	/* This is used to wait on until completion of transfer request */
+	struct completion xfer_done;
+	/* Received data from device */
+	void *buf;
+};
+
+struct dma_xfer {
+	/* Node in list of DMA transfers which is used for cleanup */
+	struct list_head list;
+	/* SG table of memory used for DMA */
+	struct sg_table *sgt;
+	/* Array pages used for DMA */
+	struct page **page_list;
+	/* Number of pages used for DMA */
+	unsigned long nr_pages;
+};
+
+struct ioctl_resources {
+	/* List of all DMA transfers which is used later for cleanup */
+	struct list_head dma_xfers;
+	/* Base address of request queue which belongs to a DBC */
+	void *buf;
+	/*
+	 * Base bus address of request queue which belongs to a DBC. Response
+	 * queue base bus address can be calculated by adding size of request
+	 * queue to base bus address of request queue.
+	 */
+	dma_addr_t dma_addr;
+	/* Total size of request queue and response queue in byte */
+	u32 total_size;
+	/* Total number of elements that can be queued in each of request and response queue */
+	u32 nelem;
+	/* Base address of response queue which belongs to a DBC */
+	void *rsp_q_base;
+	/* Status of the NNC message received */
+	u32 status;
+	/* DBC id of the DBC received from device */
+	u32 dbc_id;
+	/*
+	 * DMA transfer request messages can be big in size and it may not be
+	 * possible to send them in one shot. In such cases the messages are
+	 * broken into chunks, this field stores ID of such chunks.
+	 */
+	u32 dma_chunk_id;
+	/* Total number of bytes transferred for a DMA xfer request */
+	u64 xferred_dma_size;
+	/* Header of transaction message received from user. Used during DMA xfer request. */
+	void *trans_hdr;
+};
+
+struct resp_work {
+	struct work_struct work;
+	struct qaic_device *qdev;
+	void *buf;
+};
+
+/*
+ * Since we're working with little endian messages, its useful to be able to
+ * increment without filling a whole line with conversions back and forth just
+ * to add one(1) to a message count.
+ */
+static __le32 incr_le32(__le32 val)
+{
+	return cpu_to_le32(le32_to_cpu(val) + 1);
+}
+
+static u32 gen_crc(void *msg)
+{
+	struct wrapper_list *wrappers = msg;
+	struct wrapper_msg *w;
+	u32 crc = ~0;
+
+	list_for_each_entry(w, &wrappers->list, list)
+		crc = crc32(crc, &w->msg, w->len);
+
+	return crc ^ ~0;
+}
+
+static u32 gen_crc_stub(void *msg)
+{
+	return 0;
+}
+
+static bool valid_crc(void *msg)
+{
+	struct wire_msg_hdr *hdr = msg;
+	bool ret;
+	u32 crc;
+
+	/*
+	 * The output of this algorithm is always converted to the native
+	 * endianness.
+	 */
+	crc = le32_to_cpu(hdr->crc32);
+	hdr->crc32 = 0;
+	ret = (crc32(~0, msg, le32_to_cpu(hdr->len)) ^ ~0) == crc;
+	hdr->crc32 = cpu_to_le32(crc);
+	return ret;
+}
+
+static bool valid_crc_stub(void *msg)
+{
+	return true;
+}
+
+static void free_wrapper(struct kref *ref)
+{
+	struct wrapper_msg *wrapper = container_of(ref, struct wrapper_msg, ref_count);
+
+	list_del(&wrapper->list);
+	kfree(wrapper);
+}
+
+static void save_dbc_buf(struct qaic_device *qdev, struct ioctl_resources *resources,
+			 struct qaic_user *usr)
+{
+	u32 dbc_id = resources->dbc_id;
+
+	if (resources->buf) {
+		wait_event_interruptible(qdev->dbc[dbc_id].dbc_release, !qdev->dbc[dbc_id].in_use);
+		qdev->dbc[dbc_id].req_q_base = resources->buf;
+		qdev->dbc[dbc_id].rsp_q_base = resources->rsp_q_base;
+		qdev->dbc[dbc_id].dma_addr = resources->dma_addr;
+		qdev->dbc[dbc_id].total_size = resources->total_size;
+		qdev->dbc[dbc_id].nelem = resources->nelem;
+		enable_dbc(qdev, dbc_id, usr);
+		qdev->dbc[dbc_id].in_use = true;
+		resources->buf = NULL;
+		set_dbc_state(qdev, dbc_id, DBC_STATE_ASSIGNED);
+	}
+}
+
+static void free_dbc_buf(struct qaic_device *qdev, struct ioctl_resources *resources)
+{
+	if (resources->buf)
+		dma_free_coherent(&qdev->pdev->dev, resources->total_size, resources->buf,
+				  resources->dma_addr);
+	resources->buf = NULL;
+}
+
+static void free_dma_xfers(struct qaic_device *qdev, struct ioctl_resources *resources)
+{
+	struct dma_xfer *xfer;
+	struct dma_xfer *x;
+	int i;
+
+	list_for_each_entry_safe(xfer, x, &resources->dma_xfers, list) {
+		dma_unmap_sgtable(&qdev->pdev->dev, xfer->sgt, DMA_TO_DEVICE, 0);
+		sg_free_table(xfer->sgt);
+		kfree(xfer->sgt);
+		for (i = 0; i < xfer->nr_pages; ++i)
+			put_page(xfer->page_list[i]);
+		kfree(xfer->page_list);
+		list_del(&xfer->list);
+		kfree(xfer);
+	}
+}
+
+static struct wrapper_msg *add_wrapper(struct wrapper_list *wrappers, u32 size)
+{
+	struct wrapper_msg *w = kzalloc(size, GFP_KERNEL);
+
+	if (!w)
+		return NULL;
+	list_add_tail(&w->list, &wrappers->list);
+	kref_init(&w->ref_count);
+	w->head = wrappers;
+	return w;
+}
+
+static int encode_passthrough(struct qaic_device *qdev, void *trans, struct wrapper_list *wrappers,
+			      u32 *user_len)
+{
+	struct qaic_manage_trans_passthrough *in_trans = trans;
+	struct wire_trans_passthrough *out_trans;
+	struct wrapper_msg *trans_wrapper;
+	struct wrapper_msg *wrapper;
+	struct wire_msg *msg;
+	u32 msg_hdr_len;
+
+	wrapper = list_first_entry(&wrappers->list, struct wrapper_msg, list);
+	msg = &wrapper->msg;
+	msg_hdr_len = le32_to_cpu(msg->hdr.len);
+
+	if (in_trans->hdr.len % 8 != 0)
+		return -EINVAL;
+
+	if (size_add(msg_hdr_len, in_trans->hdr.len) > QAIC_MANAGE_WIRE_MSG_LENGTH)
+		return -ENOSPC;
+
+	trans_wrapper = add_wrapper(wrappers,
+				    offsetof(struct wrapper_msg, trans) + in_trans->hdr.len);
+	if (!trans_wrapper)
+		return -ENOMEM;
+	trans_wrapper->len = in_trans->hdr.len;
+	out_trans = (struct wire_trans_passthrough *)&trans_wrapper->trans;
+
+	memcpy(out_trans->data, in_trans->data, in_trans->hdr.len - sizeof(in_trans->hdr));
+	msg->hdr.len = cpu_to_le32(msg_hdr_len + in_trans->hdr.len);
+	msg->hdr.count = incr_le32(msg->hdr.count);
+	*user_len += in_trans->hdr.len;
+	out_trans->hdr.type = cpu_to_le32(QAIC_TRANS_PASSTHROUGH_TO_DEV);
+	out_trans->hdr.len = cpu_to_le32(in_trans->hdr.len);
+
+	return 0;
+}
+
+/* returns error code for failure, 0 if enough pages alloc'd, 1 if dma_cont is needed */
+static int find_and_map_user_pages(struct qaic_device *qdev,
+				   struct qaic_manage_trans_dma_xfer *in_trans,
+				   struct ioctl_resources *resources, struct dma_xfer *xfer)
+{
+	u64 xfer_start_addr, remaining, end, total;
+	unsigned long need_pages;
+	struct page **page_list;
+	unsigned long nr_pages;
+	struct sg_table *sgt;
+	int ret;
+	int i;
+
+	if (check_add_overflow(in_trans->addr, resources->xferred_dma_size, &xfer_start_addr))
+		return -EINVAL;
+
+	if (in_trans->size < resources->xferred_dma_size)
+		return -EINVAL;
+	remaining = in_trans->size - resources->xferred_dma_size;
+	if (remaining == 0)
+		return -EINVAL;
+
+	if (check_add_overflow(xfer_start_addr, remaining, &end))
+		return -EINVAL;
+
+	total = remaining + offset_in_page(xfer_start_addr);
+	if (total >= SIZE_MAX)
+		return -EINVAL;
+
+	need_pages = DIV_ROUND_UP(total, PAGE_SIZE);
+
+	nr_pages = need_pages;
+
+	while (1) {
+		page_list = kmalloc_array(nr_pages, sizeof(*page_list), GFP_KERNEL | __GFP_NOWARN);
+		if (!page_list) {
+			nr_pages = nr_pages / 2;
+			if (!nr_pages)
+				return -ENOMEM;
+		} else {
+			break;
+		}
+	}
+
+	ret = get_user_pages_fast(xfer_start_addr, nr_pages, 0, page_list);
+	if (ret < 0)
+		goto free_page_list;
+	if (ret != nr_pages) {
+		nr_pages = ret;
+		ret = -EFAULT;
+		goto put_pages;
+	}
+
+	sgt = kmalloc(sizeof(*sgt), GFP_KERNEL);
+	if (!sgt) {
+		ret = -ENOMEM;
+		goto put_pages;
+	}
+
+	ret = sg_alloc_table_from_pages(sgt, page_list, nr_pages,
+					offset_in_page(xfer_start_addr),
+					remaining, GFP_KERNEL);
+	if (ret) {
+		ret = -ENOMEM;
+		goto free_sgt;
+	}
+
+	ret = dma_map_sgtable(&qdev->pdev->dev, sgt, DMA_TO_DEVICE, 0);
+	if (ret)
+		goto free_table;
+
+	xfer->sgt = sgt;
+	xfer->page_list = page_list;
+	xfer->nr_pages = nr_pages;
+
+	return need_pages > nr_pages ? 1 : 0;
+
+free_table:
+	sg_free_table(sgt);
+free_sgt:
+	kfree(sgt);
+put_pages:
+	for (i = 0; i < nr_pages; ++i)
+		put_page(page_list[i]);
+free_page_list:
+	kfree(page_list);
+	return ret;
+}
+
+/* returns error code for failure, 0 if everything was encoded, 1 if dma_cont is needed */
+static int encode_addr_size_pairs(struct dma_xfer *xfer, struct wrapper_list *wrappers,
+				  struct ioctl_resources *resources, u32 msg_hdr_len, u32 *size,
+				  struct wire_trans_dma_xfer **out_trans)
+{
+	struct wrapper_msg *trans_wrapper;
+	struct sg_table *sgt = xfer->sgt;
+	struct wire_addr_size_pair *asp;
+	struct scatterlist *sg;
+	struct wrapper_msg *w;
+	unsigned int dma_len;
+	u64 dma_chunk_len;
+	void *boundary;
+	int nents_dma;
+	int nents;
+	int i;
+
+	nents = sgt->nents;
+	nents_dma = nents;
+	*size = QAIC_MANAGE_WIRE_MSG_LENGTH - msg_hdr_len - sizeof(**out_trans);
+	for_each_sgtable_dma_sg(sgt, sg, i) {
+		*size -= sizeof(*asp);
+		/* Save 1K for possible follow-up transactions. */
+		if (*size < SZ_1K) {
+			nents_dma = i;
+			break;
+		}
+	}
+
+	trans_wrapper = add_wrapper(wrappers, QAIC_WRAPPER_MAX_SIZE);
+	if (!trans_wrapper)
+		return -ENOMEM;
+	*out_trans = (struct wire_trans_dma_xfer *)&trans_wrapper->trans;
+
+	asp = (*out_trans)->data;
+	boundary = (void *)trans_wrapper + QAIC_WRAPPER_MAX_SIZE;
+	*size = 0;
+
+	dma_len = 0;
+	w = trans_wrapper;
+	dma_chunk_len = 0;
+	for_each_sg(sgt->sgl, sg, nents_dma, i) {
+		asp->size = cpu_to_le64(dma_len);
+		dma_chunk_len += dma_len;
+		if (dma_len) {
+			asp++;
+			if ((void *)asp + sizeof(*asp) > boundary) {
+				w->len = (void *)asp - (void *)&w->msg;
+				*size += w->len;
+				w = add_wrapper(wrappers, QAIC_WRAPPER_MAX_SIZE);
+				if (!w)
+					return -ENOMEM;
+				boundary = (void *)w + QAIC_WRAPPER_MAX_SIZE;
+				asp = (struct wire_addr_size_pair *)&w->msg;
+			}
+		}
+		asp->addr = cpu_to_le64(sg_dma_address(sg));
+		dma_len = sg_dma_len(sg);
+	}
+	/* finalize the last segment */
+	asp->size = cpu_to_le64(dma_len);
+	w->len = (void *)asp + sizeof(*asp) - (void *)&w->msg;
+	*size += w->len;
+	dma_chunk_len += dma_len;
+	resources->xferred_dma_size += dma_chunk_len;
+
+	return nents_dma < nents ? 1 : 0;
+}
+
+static void cleanup_xfer(struct qaic_device *qdev, struct dma_xfer *xfer)
+{
+	int i;
+
+	dma_unmap_sgtable(&qdev->pdev->dev, xfer->sgt, DMA_TO_DEVICE, 0);
+	sg_free_table(xfer->sgt);
+	kfree(xfer->sgt);
+	for (i = 0; i < xfer->nr_pages; ++i)
+		put_page(xfer->page_list[i]);
+	kfree(xfer->page_list);
+}
+
+static int encode_dma(struct qaic_device *qdev, void *trans, struct wrapper_list *wrappers,
+		      u32 *user_len, struct ioctl_resources *resources, struct qaic_user *usr)
+{
+	struct qaic_manage_trans_dma_xfer *in_trans = trans;
+	struct wire_trans_dma_xfer *out_trans;
+	struct wrapper_msg *wrapper;
+	struct dma_xfer *xfer;
+	struct wire_msg *msg;
+	bool need_cont_dma;
+	u32 msg_hdr_len;
+	u32 size;
+	int ret;
+
+	wrapper = list_first_entry(&wrappers->list, struct wrapper_msg, list);
+	msg = &wrapper->msg;
+	msg_hdr_len = le32_to_cpu(msg->hdr.len);
+
+	/* There should be enough space to hold at least one ASP entry. */
+	if (size_add(msg_hdr_len, sizeof(*out_trans) + sizeof(struct wire_addr_size_pair)) >
+	    QAIC_MANAGE_WIRE_MSG_LENGTH)
+		return -ENOMEM;
+
+	xfer = kmalloc(sizeof(*xfer), GFP_KERNEL);
+	if (!xfer)
+		return -ENOMEM;
+
+	ret = find_and_map_user_pages(qdev, in_trans, resources, xfer);
+	if (ret < 0)
+		goto free_xfer;
+
+	need_cont_dma = (bool)ret;
+
+	ret = encode_addr_size_pairs(xfer, wrappers, resources, msg_hdr_len, &size, &out_trans);
+	if (ret < 0)
+		goto cleanup_xfer;
+
+	need_cont_dma = need_cont_dma || (bool)ret;
+
+	msg->hdr.len = cpu_to_le32(msg_hdr_len + size);
+	msg->hdr.count = incr_le32(msg->hdr.count);
+
+	out_trans->hdr.type = cpu_to_le32(QAIC_TRANS_DMA_XFER_TO_DEV);
+	out_trans->hdr.len = cpu_to_le32(size);
+	out_trans->tag = cpu_to_le32(in_trans->tag);
+	out_trans->count = cpu_to_le32((size - sizeof(*out_trans)) /
+								sizeof(struct wire_addr_size_pair));
+
+	*user_len += in_trans->hdr.len;
+
+	if (resources->dma_chunk_id) {
+		out_trans->dma_chunk_id = cpu_to_le32(resources->dma_chunk_id);
+	} else if (need_cont_dma) {
+		while (resources->dma_chunk_id == 0)
+			resources->dma_chunk_id = atomic_inc_return(&usr->chunk_id);
+
+		out_trans->dma_chunk_id = cpu_to_le32(resources->dma_chunk_id);
+	}
+	resources->trans_hdr = trans;
+
+	list_add(&xfer->list, &resources->dma_xfers);
+	return 0;
+
+cleanup_xfer:
+	cleanup_xfer(qdev, xfer);
+free_xfer:
+	kfree(xfer);
+	return ret;
+}
+
+static int encode_activate(struct qaic_device *qdev, void *trans, struct wrapper_list *wrappers,
+			   u32 *user_len, struct ioctl_resources *resources)
+{
+	struct qaic_manage_trans_activate_to_dev *in_trans = trans;
+	struct wire_trans_activate_to_dev *out_trans;
+	struct wrapper_msg *trans_wrapper;
+	struct wrapper_msg *wrapper;
+	struct wire_msg *msg;
+	dma_addr_t dma_addr;
+	u32 msg_hdr_len;
+	void *buf;
+	u32 nelem;
+	u32 size;
+	int ret;
+
+	wrapper = list_first_entry(&wrappers->list, struct wrapper_msg, list);
+	msg = &wrapper->msg;
+	msg_hdr_len = le32_to_cpu(msg->hdr.len);
+
+	if (size_add(msg_hdr_len, sizeof(*out_trans)) > QAIC_MANAGE_WIRE_MSG_LENGTH)
+		return -ENOSPC;
+
+	if (!in_trans->queue_size)
+		return -EINVAL;
+
+	if (in_trans->pad)
+		return -EINVAL;
+
+	nelem = in_trans->queue_size;
+	if (check_mul_overflow((u32)(get_dbc_req_elem_size() + get_dbc_rsp_elem_size()),
+			       nelem,
+			       &size))
+		return -EINVAL;
+
+	if (size + QAIC_DBC_Q_GAP + QAIC_DBC_Q_BUF_ALIGN < size)
+		return -EINVAL;
+
+	size = ALIGN((size + QAIC_DBC_Q_GAP), QAIC_DBC_Q_BUF_ALIGN);
+
+	buf = dma_alloc_coherent(&qdev->pdev->dev, size, &dma_addr, GFP_KERNEL);
+	if (!buf)
+		return -ENOMEM;
+
+	trans_wrapper = add_wrapper(wrappers,
+				    offsetof(struct wrapper_msg, trans) + sizeof(*out_trans));
+	if (!trans_wrapper) {
+		ret = -ENOMEM;
+		goto free_dma;
+	}
+	trans_wrapper->len = sizeof(*out_trans);
+	out_trans = (struct wire_trans_activate_to_dev *)&trans_wrapper->trans;
+
+	out_trans->hdr.type = cpu_to_le32(QAIC_TRANS_ACTIVATE_TO_DEV);
+	out_trans->hdr.len = cpu_to_le32(sizeof(*out_trans));
+	out_trans->buf_len = cpu_to_le32(size);
+	out_trans->req_q_addr = cpu_to_le64(dma_addr);
+	out_trans->req_q_size = cpu_to_le32(nelem);
+	out_trans->rsp_q_addr = cpu_to_le64(dma_addr + size - nelem * get_dbc_rsp_elem_size());
+	out_trans->rsp_q_size = cpu_to_le32(nelem);
+	out_trans->options = cpu_to_le32(in_trans->options);
+
+	*user_len += in_trans->hdr.len;
+	msg->hdr.len = cpu_to_le32(msg_hdr_len + sizeof(*out_trans));
+	msg->hdr.count = incr_le32(msg->hdr.count);
+
+	resources->buf = buf;
+	resources->dma_addr = dma_addr;
+	resources->total_size = size;
+	resources->nelem = nelem;
+	resources->rsp_q_base = buf + size - nelem * get_dbc_rsp_elem_size();
+	return 0;
+
+free_dma:
+	dma_free_coherent(&qdev->pdev->dev, size, buf, dma_addr);
+	return ret;
+}
+
+static int encode_deactivate(struct qaic_device *qdev, void *trans,
+			     u32 *user_len, struct qaic_user *usr)
+{
+	struct qaic_manage_trans_deactivate *in_trans = trans;
+
+	if (in_trans->dbc_id >= qdev->num_dbc || in_trans->pad)
+		return -EINVAL;
+
+	*user_len += in_trans->hdr.len;
+
+	return disable_dbc(qdev, in_trans->dbc_id, usr);
+}
+
+static int encode_status(struct qaic_device *qdev, void *trans, struct wrapper_list *wrappers,
+			 u32 *user_len)
+{
+	struct qaic_manage_trans_status_to_dev *in_trans = trans;
+	struct wire_trans_status_to_dev *out_trans;
+	struct wrapper_msg *trans_wrapper;
+	struct wrapper_msg *wrapper;
+	struct wire_msg *msg;
+	u32 msg_hdr_len;
+
+	wrapper = list_first_entry(&wrappers->list, struct wrapper_msg, list);
+	msg = &wrapper->msg;
+	msg_hdr_len = le32_to_cpu(msg->hdr.len);
+
+	if (size_add(msg_hdr_len, in_trans->hdr.len) > QAIC_MANAGE_WIRE_MSG_LENGTH)
+		return -ENOSPC;
+
+	trans_wrapper = add_wrapper(wrappers, sizeof(*trans_wrapper));
+	if (!trans_wrapper)
+		return -ENOMEM;
+
+	trans_wrapper->len = sizeof(*out_trans);
+	out_trans = (struct wire_trans_status_to_dev *)&trans_wrapper->trans;
+
+	out_trans->hdr.type = cpu_to_le32(QAIC_TRANS_STATUS_TO_DEV);
+	out_trans->hdr.len = cpu_to_le32(in_trans->hdr.len);
+	msg->hdr.len = cpu_to_le32(msg_hdr_len + in_trans->hdr.len);
+	msg->hdr.count = incr_le32(msg->hdr.count);
+	*user_len += in_trans->hdr.len;
+
+	return 0;
+}
+
+static int encode_message(struct qaic_device *qdev, struct manage_msg *user_msg,
+			  struct wrapper_list *wrappers, struct ioctl_resources *resources,
+			  struct qaic_user *usr)
+{
+	struct qaic_manage_trans_hdr *trans_hdr;
+	struct wrapper_msg *wrapper;
+	struct wire_msg *msg;
+	u32 user_len = 0;
+	int ret;
+	int i;
+
+	if (!user_msg->count ||
+	    user_msg->len < sizeof(*trans_hdr)) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	wrapper = list_first_entry(&wrappers->list, struct wrapper_msg, list);
+	msg = &wrapper->msg;
+
+	msg->hdr.len = cpu_to_le32(sizeof(msg->hdr));
+
+	if (resources->dma_chunk_id) {
+		ret = encode_dma(qdev, resources->trans_hdr, wrappers, &user_len, resources, usr);
+		msg->hdr.count = cpu_to_le32(1);
+		goto out;
+	}
+
+	for (i = 0; i < user_msg->count; ++i) {
+		if (user_len > user_msg->len - sizeof(*trans_hdr)) {
+			ret = -EINVAL;
+			break;
+		}
+		trans_hdr = (struct qaic_manage_trans_hdr *)(user_msg->data + user_len);
+		if (trans_hdr->len < sizeof(trans_hdr) ||
+		    size_add(user_len, trans_hdr->len) > user_msg->len) {
+			ret = -EINVAL;
+			break;
+		}
+
+		switch (trans_hdr->type) {
+		case QAIC_TRANS_PASSTHROUGH_FROM_USR:
+			ret = encode_passthrough(qdev, trans_hdr, wrappers, &user_len);
+			break;
+		case QAIC_TRANS_DMA_XFER_FROM_USR:
+			ret = encode_dma(qdev, trans_hdr, wrappers, &user_len, resources, usr);
+			break;
+		case QAIC_TRANS_ACTIVATE_FROM_USR:
+			ret = encode_activate(qdev, trans_hdr, wrappers, &user_len, resources);
+			break;
+		case QAIC_TRANS_DEACTIVATE_FROM_USR:
+			ret = encode_deactivate(qdev, trans_hdr, &user_len, usr);
+			break;
+		case QAIC_TRANS_STATUS_FROM_USR:
+			ret = encode_status(qdev, trans_hdr, wrappers, &user_len);
+			break;
+		default:
+			ret = -EINVAL;
+			break;
+		}
+
+		if (ret)
+			goto out;
+	}
+
+	if (user_len != user_msg->len)
+		ret = -EINVAL;
+out:
+	if (ret) {
+		free_dma_xfers(qdev, resources);
+		free_dbc_buf(qdev, resources);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int decode_passthrough(struct qaic_device *qdev, void *trans, struct manage_msg *user_msg,
+			      u32 *msg_len)
+{
+	struct qaic_manage_trans_passthrough *out_trans;
+	struct wire_trans_passthrough *in_trans = trans;
+	u32 len;
+
+	out_trans = (void *)user_msg->data + user_msg->len;
+
+	len = le32_to_cpu(in_trans->hdr.len);
+	if (len % 8 != 0)
+		return -EINVAL;
+
+	if (user_msg->len + len > QAIC_MANAGE_MAX_MSG_LENGTH)
+		return -ENOSPC;
+
+	memcpy(out_trans->data, in_trans->data, len - sizeof(in_trans->hdr));
+	user_msg->len += len;
+	*msg_len += len;
+	out_trans->hdr.type = le32_to_cpu(in_trans->hdr.type);
+	out_trans->hdr.len = len;
+
+	return 0;
+}
+
+static int decode_activate(struct qaic_device *qdev, void *trans, struct manage_msg *user_msg,
+			   u32 *msg_len, struct ioctl_resources *resources, struct qaic_user *usr)
+{
+	struct qaic_manage_trans_activate_from_dev *out_trans;
+	struct wire_trans_activate_from_dev *in_trans = trans;
+	u32 len;
+
+	out_trans = (void *)user_msg->data + user_msg->len;
+
+	len = le32_to_cpu(in_trans->hdr.len);
+	if (user_msg->len + len > QAIC_MANAGE_MAX_MSG_LENGTH)
+		return -ENOSPC;
+
+	user_msg->len += len;
+	*msg_len += len;
+	out_trans->hdr.type = le32_to_cpu(in_trans->hdr.type);
+	out_trans->hdr.len = len;
+	out_trans->status = le32_to_cpu(in_trans->status);
+	out_trans->dbc_id = le32_to_cpu(in_trans->dbc_id);
+	out_trans->options = le64_to_cpu(in_trans->options);
+
+	if (!resources->buf)
+		/* how did we get an activate response without a request? */
+		return -EINVAL;
+
+	if (out_trans->dbc_id >= qdev->num_dbc)
+		/*
+		 * The device assigned an invalid resource, which should never
+		 * happen. Return an error so the user can try to recover.
+		 */
+		return -ENODEV;
+
+	if (out_trans->status)
+		/*
+		 * Allocating resources failed on device side. This is not an
+		 * expected behaviour, user is expected to handle this situation.
+		 */
+		return -ECANCELED;
+
+	resources->status = out_trans->status;
+	resources->dbc_id = out_trans->dbc_id;
+	save_dbc_buf(qdev, resources, usr);
+
+	return 0;
+}
+
+static int decode_deactivate(struct qaic_device *qdev, void *trans, u32 *msg_len,
+			     struct qaic_user *usr)
+{
+	struct wire_trans_deactivate_from_dev *in_trans = trans;
+	u32 dbc_id = le32_to_cpu(in_trans->dbc_id);
+	u32 status = le32_to_cpu(in_trans->status);
+
+	if (dbc_id >= qdev->num_dbc)
+		/*
+		 * The device assigned an invalid resource, which should never
+		 * happen. Inject an error so the user can try to recover.
+		 */
+		return -ENODEV;
+
+	if (status) {
+		/*
+		 * Releasing resources failed on the device side, which puts
+		 * us in a bind since they may still be in use, so enable the
+		 * dbc. User is expected to retry deactivation.
+		 */
+		enable_dbc(qdev, dbc_id, usr);
+		return -ECANCELED;
+	}
+
+	release_dbc(qdev, dbc_id);
+	set_dbc_state(qdev, dbc_id, DBC_STATE_IDLE);
+	*msg_len += sizeof(*in_trans);
+
+	return 0;
+}
+
+static int decode_status(struct qaic_device *qdev, void *trans, struct manage_msg *user_msg,
+			 u32 *user_len, struct wire_msg *msg)
+{
+	struct qaic_manage_trans_status_from_dev *out_trans;
+	struct wire_trans_status_from_dev *in_trans = trans;
+	u32 len;
+
+	out_trans = (void *)user_msg->data + user_msg->len;
+
+	len = le32_to_cpu(in_trans->hdr.len);
+	if (user_msg->len + len > QAIC_MANAGE_MAX_MSG_LENGTH)
+		return -ENOSPC;
+
+	out_trans->hdr.type = QAIC_TRANS_STATUS_FROM_DEV;
+	out_trans->hdr.len = len;
+	out_trans->major = le16_to_cpu(in_trans->major);
+	out_trans->minor = le16_to_cpu(in_trans->minor);
+	out_trans->status_flags = le64_to_cpu(in_trans->status_flags);
+	out_trans->status = le32_to_cpu(in_trans->status);
+	*user_len += le32_to_cpu(in_trans->hdr.len);
+	user_msg->len += len;
+
+	if (out_trans->status)
+		return -ECANCELED;
+	if (out_trans->status_flags & BIT(0) && !valid_crc(msg))
+		return -EPIPE;
+
+	return 0;
+}
+
+static int decode_message(struct qaic_device *qdev, struct manage_msg *user_msg,
+			  struct wire_msg *msg, struct ioctl_resources *resources,
+			  struct qaic_user *usr)
+{
+	u32 msg_hdr_len = le32_to_cpu(msg->hdr.len);
+	struct wire_trans_hdr *trans_hdr;
+	u32 msg_len = 0;
+	int ret;
+	int i;
+
+	if (msg_hdr_len < sizeof(*trans_hdr) ||
+	    msg_hdr_len > QAIC_MANAGE_MAX_MSG_LENGTH)
+		return -EINVAL;
+
+	user_msg->len = 0;
+	user_msg->count = le32_to_cpu(msg->hdr.count);
+
+	for (i = 0; i < user_msg->count; ++i) {
+		u32 hdr_len;
+
+		if (msg_len > msg_hdr_len - sizeof(*trans_hdr))
+			return -EINVAL;
+
+		trans_hdr = (struct wire_trans_hdr *)(msg->data + msg_len);
+		hdr_len = le32_to_cpu(trans_hdr->len);
+		if (hdr_len < sizeof(*trans_hdr) ||
+		    size_add(msg_len, hdr_len) > msg_hdr_len)
+			return -EINVAL;
+
+		switch (le32_to_cpu(trans_hdr->type)) {
+		case QAIC_TRANS_PASSTHROUGH_FROM_DEV:
+			ret = decode_passthrough(qdev, trans_hdr, user_msg, &msg_len);
+			break;
+		case QAIC_TRANS_ACTIVATE_FROM_DEV:
+			ret = decode_activate(qdev, trans_hdr, user_msg, &msg_len, resources, usr);
+			break;
+		case QAIC_TRANS_DEACTIVATE_FROM_DEV:
+			ret = decode_deactivate(qdev, trans_hdr, &msg_len, usr);
+			break;
+		case QAIC_TRANS_STATUS_FROM_DEV:
+			ret = decode_status(qdev, trans_hdr, user_msg, &msg_len, msg);
+			break;
+		default:
+			return -EINVAL;
+		}
+
+		if (ret)
+			return ret;
+	}
+
+	if (msg_len != (msg_hdr_len - sizeof(msg->hdr)))
+		return -EINVAL;
+
+	return 0;
+}
+
+static void *msg_xfer(struct qaic_device *qdev, struct wrapper_list *wrappers, u32 seq_num,
+		      bool ignore_signal)
+{
+	struct xfer_queue_elem elem;
+	struct wire_msg *out_buf;
+	struct wrapper_msg *w;
+	long ret = -EAGAIN;
+	int xfer_count = 0;
+	int retry_count;
+
+	/* Allow QAIC_BOOT state since we need to check control protocol version */
+	if (qdev->dev_state == QAIC_OFFLINE) {
+		mutex_unlock(&qdev->cntl_mutex);
+		return ERR_PTR(-ENODEV);
+	}
+
+	/* Attempt to avoid a partial commit of a message */
+	list_for_each_entry(w, &wrappers->list, list)
+		xfer_count++;
+
+	for (retry_count = 0; retry_count < QAIC_MHI_RETRY_MAX; retry_count++) {
+		if (xfer_count <= mhi_get_free_desc_count(qdev->cntl_ch, DMA_TO_DEVICE)) {
+			ret = 0;
+			break;
+		}
+		msleep_interruptible(QAIC_MHI_RETRY_WAIT_MS);
+		if (signal_pending(current))
+			break;
+	}
+
+	if (ret) {
+		mutex_unlock(&qdev->cntl_mutex);
+		return ERR_PTR(ret);
+	}
+
+	elem.seq_num = seq_num;
+	elem.buf = NULL;
+	init_completion(&elem.xfer_done);
+	if (likely(!qdev->cntl_lost_buf)) {
+		/*
+		 * The max size of request to device is QAIC_MANAGE_WIRE_MSG_LENGTH.
+		 * The max size of response from device is QAIC_MANAGE_MAX_MSG_LENGTH.
+		 */
+		out_buf = kmalloc(QAIC_MANAGE_MAX_MSG_LENGTH, GFP_KERNEL);
+		if (!out_buf) {
+			mutex_unlock(&qdev->cntl_mutex);
+			return ERR_PTR(-ENOMEM);
+		}
+
+		ret = mhi_queue_buf(qdev->cntl_ch, DMA_FROM_DEVICE, out_buf,
+				    QAIC_MANAGE_MAX_MSG_LENGTH, MHI_EOT);
+		if (ret) {
+			mutex_unlock(&qdev->cntl_mutex);
+			return ERR_PTR(ret);
+		}
+	} else {
+		/*
+		 * we lost a buffer because we queued a recv buf, but then
+		 * queuing the corresponding tx buf failed. To try to avoid
+		 * a memory leak, lets reclaim it and use it for this
+		 * transaction.
+		 */
+		qdev->cntl_lost_buf = false;
+	}
+
+	list_for_each_entry(w, &wrappers->list, list) {
+		kref_get(&w->ref_count);
+		ret = mhi_queue_buf(qdev->cntl_ch, DMA_TO_DEVICE, &w->msg, w->len,
+				    list_is_last(&w->list, &wrappers->list) ? MHI_EOT : MHI_CHAIN);
+		if (ret) {
+			qdev->cntl_lost_buf = true;
+			kref_put(&w->ref_count, free_wrapper);
+			mutex_unlock(&qdev->cntl_mutex);
+			return ERR_PTR(ret);
+		}
+	}
+
+	list_add_tail(&elem.list, &qdev->cntl_xfer_list);
+	mutex_unlock(&qdev->cntl_mutex);
+
+	if (ignore_signal)
+		ret = wait_for_completion_timeout(&elem.xfer_done, control_resp_timeout_s * HZ);
+	else
+		ret = wait_for_completion_interruptible_timeout(&elem.xfer_done,
+								control_resp_timeout_s * HZ);
+	/*
+	 * not using _interruptable because we have to cleanup or we'll
+	 * likely cause memory corruption
+	 */
+	mutex_lock(&qdev->cntl_mutex);
+	if (!list_empty(&elem.list))
+		list_del(&elem.list);
+	if (!ret && !elem.buf)
+		ret = -ETIMEDOUT;
+	else if (ret > 0 && !elem.buf)
+		ret = -EIO;
+	mutex_unlock(&qdev->cntl_mutex);
+
+	if (ret < 0) {
+		kfree(elem.buf);
+		return ERR_PTR(ret);
+	} else if (!qdev->valid_crc(elem.buf)) {
+		kfree(elem.buf);
+		return ERR_PTR(-EPIPE);
+	}
+
+	return elem.buf;
+}
+
+/* Add a transaction to abort the outstanding DMA continuation */
+static int abort_dma_cont(struct qaic_device *qdev, struct wrapper_list *wrappers, u32 dma_chunk_id)
+{
+	struct wire_trans_dma_xfer *out_trans;
+	u32 size = sizeof(*out_trans);
+	struct wrapper_msg *wrapper;
+	struct wrapper_msg *w;
+	struct wire_msg *msg;
+
+	wrapper = list_first_entry(&wrappers->list, struct wrapper_msg, list);
+	msg = &wrapper->msg;
+
+	/* Remove all but the first wrapper which has the msg header */
+	list_for_each_entry_safe(wrapper, w, &wrappers->list, list)
+		if (!list_is_first(&wrapper->list, &wrappers->list))
+			kref_put(&wrapper->ref_count, free_wrapper);
+
+	wrapper = add_wrapper(wrappers, sizeof(*wrapper));
+
+	if (!wrapper)
+		return -ENOMEM;
+
+	out_trans = (struct wire_trans_dma_xfer *)&wrapper->trans;
+	out_trans->hdr.type = cpu_to_le32(QAIC_TRANS_DMA_XFER_TO_DEV);
+	out_trans->hdr.len = cpu_to_le32(size);
+	out_trans->tag = cpu_to_le32(0);
+	out_trans->count = cpu_to_le32(0);
+	out_trans->dma_chunk_id = cpu_to_le32(dma_chunk_id);
+
+	msg->hdr.len = cpu_to_le32(size + sizeof(*msg));
+	msg->hdr.count = cpu_to_le32(1);
+	wrapper->len = size;
+
+	return 0;
+}
+
+static struct wrapper_list *alloc_wrapper_list(void)
+{
+	struct wrapper_list *wrappers;
+
+	wrappers = kmalloc(sizeof(*wrappers), GFP_KERNEL);
+	if (!wrappers)
+		return NULL;
+	INIT_LIST_HEAD(&wrappers->list);
+	spin_lock_init(&wrappers->lock);
+
+	return wrappers;
+}
+
+static int qaic_manage_msg_xfer(struct qaic_device *qdev, struct qaic_user *usr,
+				struct manage_msg *user_msg, struct ioctl_resources *resources,
+				struct wire_msg **rsp)
+{
+	struct wrapper_list *wrappers;
+	struct wrapper_msg *wrapper;
+	struct wrapper_msg *w;
+	bool all_done = false;
+	struct wire_msg *msg;
+	int ret;
+
+	wrappers = alloc_wrapper_list();
+	if (!wrappers)
+		return -ENOMEM;
+
+	wrapper = add_wrapper(wrappers, sizeof(*wrapper));
+	if (!wrapper) {
+		kfree(wrappers);
+		return -ENOMEM;
+	}
+
+	msg = &wrapper->msg;
+	wrapper->len = sizeof(*msg);
+
+	ret = encode_message(qdev, user_msg, wrappers, resources, usr);
+	if (ret && resources->dma_chunk_id)
+		ret = abort_dma_cont(qdev, wrappers, resources->dma_chunk_id);
+	if (ret)
+		goto encode_failed;
+
+	ret = mutex_lock_interruptible(&qdev->cntl_mutex);
+	if (ret)
+		goto lock_failed;
+
+	msg->hdr.magic_number = MANAGE_MAGIC_NUMBER;
+	msg->hdr.sequence_number = cpu_to_le32(qdev->next_seq_num++);
+
+	if (usr) {
+		msg->hdr.handle = cpu_to_le32(usr->handle);
+		msg->hdr.partition_id = cpu_to_le32(usr->qddev->partition_id);
+	} else {
+		msg->hdr.handle = 0;
+		msg->hdr.partition_id = cpu_to_le32(QAIC_NO_PARTITION);
+	}
+
+	msg->hdr.padding = cpu_to_le32(0);
+	msg->hdr.crc32 = cpu_to_le32(qdev->gen_crc(wrappers));
+
+	/* msg_xfer releases the mutex */
+	*rsp = msg_xfer(qdev, wrappers, qdev->next_seq_num - 1, false);
+	if (IS_ERR(*rsp))
+		ret = PTR_ERR(*rsp);
+
+lock_failed:
+	free_dma_xfers(qdev, resources);
+encode_failed:
+	spin_lock(&wrappers->lock);
+	list_for_each_entry_safe(wrapper, w, &wrappers->list, list)
+		kref_put(&wrapper->ref_count, free_wrapper);
+	all_done = list_empty(&wrappers->list);
+	spin_unlock(&wrappers->lock);
+	if (all_done)
+		kfree(wrappers);
+
+	return ret;
+}
+
+static int qaic_manage(struct qaic_device *qdev, struct qaic_user *usr, struct manage_msg *user_msg)
+{
+	struct wire_trans_dma_xfer_cont *dma_cont = NULL;
+	struct ioctl_resources resources;
+	struct wire_msg *rsp = NULL;
+	int ret;
+
+	memset(&resources, 0, sizeof(struct ioctl_resources));
+
+	INIT_LIST_HEAD(&resources.dma_xfers);
+
+	if (user_msg->len > QAIC_MANAGE_MAX_MSG_LENGTH ||
+	    user_msg->count > QAIC_MANAGE_MAX_MSG_LENGTH / sizeof(struct qaic_manage_trans_hdr))
+		return -EINVAL;
+
+dma_xfer_continue:
+	ret = qaic_manage_msg_xfer(qdev, usr, user_msg, &resources, &rsp);
+	if (ret)
+		return ret;
+	/* dma_cont should be the only transaction if present */
+	if (le32_to_cpu(rsp->hdr.count) == 1) {
+		dma_cont = (struct wire_trans_dma_xfer_cont *)rsp->data;
+		if (le32_to_cpu(dma_cont->hdr.type) != QAIC_TRANS_DMA_XFER_CONT)
+			dma_cont = NULL;
+	}
+	if (dma_cont) {
+		if (le32_to_cpu(dma_cont->dma_chunk_id) == resources.dma_chunk_id &&
+		    le64_to_cpu(dma_cont->xferred_size) == resources.xferred_dma_size) {
+			kfree(rsp);
+			goto dma_xfer_continue;
+		}
+
+		ret = -EINVAL;
+		goto dma_cont_failed;
+	}
+
+	ret = decode_message(qdev, user_msg, rsp, &resources, usr);
+
+dma_cont_failed:
+	free_dbc_buf(qdev, &resources);
+	kfree(rsp);
+	return ret;
+}
+
+int qaic_manage_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv)
+{
+	struct qaic_manage_msg *user_msg = data;
+	struct qaic_device *qdev;
+	struct manage_msg *msg;
+	struct qaic_user *usr;
+	u8 __user *user_data;
+	int qdev_rcu_id;
+	int usr_rcu_id;
+	int ret;
+
+	if (user_msg->len > QAIC_MANAGE_MAX_MSG_LENGTH)
+		return -EINVAL;
+
+	usr = file_priv->driver_priv;
+
+	usr_rcu_id = srcu_read_lock(&usr->qddev_lock);
+	if (!usr->qddev) {
+		srcu_read_unlock(&usr->qddev_lock, usr_rcu_id);
+		return -ENODEV;
+	}
+
+	qdev = usr->qddev->qdev;
+
+	qdev_rcu_id = srcu_read_lock(&qdev->dev_lock);
+	if (qdev->dev_state != QAIC_ONLINE) {
+		srcu_read_unlock(&qdev->dev_lock, qdev_rcu_id);
+		srcu_read_unlock(&usr->qddev_lock, usr_rcu_id);
+		return -ENODEV;
+	}
+
+	msg = kzalloc(QAIC_MANAGE_MAX_MSG_LENGTH + sizeof(*msg), GFP_KERNEL);
+	if (!msg) {
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	msg->len = user_msg->len;
+	msg->count = user_msg->count;
+
+	user_data = u64_to_user_ptr(user_msg->data);
+
+	if (copy_from_user(msg->data, user_data, user_msg->len)) {
+		ret = -EFAULT;
+		goto free_msg;
+	}
+
+	ret = qaic_manage(qdev, usr, msg);
+
+	/*
+	 * If the qaic_manage() is successful then we copy the message onto
+	 * userspace memory but we have an exception for -ECANCELED.
+	 * For -ECANCELED, it means that device has NACKed the message with a
+	 * status error code which userspace would like to know.
+	 */
+	if (ret == -ECANCELED || !ret) {
+		if (copy_to_user(user_data, msg->data, msg->len)) {
+			ret = -EFAULT;
+		} else {
+			user_msg->len = msg->len;
+			user_msg->count = msg->count;
+		}
+	}
+
+free_msg:
+	kfree(msg);
+out:
+	srcu_read_unlock(&qdev->dev_lock, qdev_rcu_id);
+	srcu_read_unlock(&usr->qddev_lock, usr_rcu_id);
+	return ret;
+}
+
+int get_cntl_version(struct qaic_device *qdev, struct qaic_user *usr, u16 *major, u16 *minor)
+{
+	struct qaic_manage_trans_status_from_dev *status_result;
+	struct qaic_manage_trans_status_to_dev *status_query;
+	struct manage_msg *user_msg;
+	int ret;
+
+	user_msg = kmalloc(sizeof(*user_msg) + sizeof(*status_result), GFP_KERNEL);
+	if (!user_msg) {
+		ret = -ENOMEM;
+		goto out;
+	}
+	user_msg->len = sizeof(*status_query);
+	user_msg->count = 1;
+
+	status_query = (struct qaic_manage_trans_status_to_dev *)user_msg->data;
+	status_query->hdr.type = QAIC_TRANS_STATUS_FROM_USR;
+	status_query->hdr.len = sizeof(status_query->hdr);
+
+	ret = qaic_manage(qdev, usr, user_msg);
+	if (ret)
+		goto kfree_user_msg;
+	status_result = (struct qaic_manage_trans_status_from_dev *)user_msg->data;
+	*major = status_result->major;
+	*minor = status_result->minor;
+
+	if (status_result->status_flags & BIT(0)) { /* device is using CRC */
+		/* By default qdev->gen_crc is programmed to generate CRC */
+		qdev->valid_crc = valid_crc;
+	} else {
+		/* By default qdev->valid_crc is programmed to bypass CRC */
+		qdev->gen_crc = gen_crc_stub;
+	}
+
+kfree_user_msg:
+	kfree(user_msg);
+out:
+	return ret;
+}
+
+static void resp_worker(struct work_struct *work)
+{
+	struct resp_work *resp = container_of(work, struct resp_work, work);
+	struct qaic_device *qdev = resp->qdev;
+	struct wire_msg *msg = resp->buf;
+	struct xfer_queue_elem *elem;
+	struct xfer_queue_elem *i;
+	bool found = false;
+
+	mutex_lock(&qdev->cntl_mutex);
+	list_for_each_entry_safe(elem, i, &qdev->cntl_xfer_list, list) {
+		if (elem->seq_num == le32_to_cpu(msg->hdr.sequence_number)) {
+			found = true;
+			list_del_init(&elem->list);
+			elem->buf = msg;
+			complete_all(&elem->xfer_done);
+			break;
+		}
+	}
+	mutex_unlock(&qdev->cntl_mutex);
+
+	if (!found)
+		/* request must have timed out, drop packet */
+		kfree(msg);
+
+	kfree(resp);
+}
+
+static void free_wrapper_from_list(struct wrapper_list *wrappers, struct wrapper_msg *wrapper)
+{
+	bool all_done = false;
+
+	spin_lock(&wrappers->lock);
+	kref_put(&wrapper->ref_count, free_wrapper);
+	all_done = list_empty(&wrappers->list);
+	spin_unlock(&wrappers->lock);
+
+	if (all_done)
+		kfree(wrappers);
+}
+
+void qaic_mhi_ul_xfer_cb(struct mhi_device *mhi_dev, struct mhi_result *mhi_result)
+{
+	struct wire_msg *msg = mhi_result->buf_addr;
+	struct wrapper_msg *wrapper = container_of(msg, struct wrapper_msg, msg);
+
+	free_wrapper_from_list(wrapper->head, wrapper);
+}
+
+void qaic_mhi_dl_xfer_cb(struct mhi_device *mhi_dev, struct mhi_result *mhi_result)
+{
+	struct qaic_device *qdev = dev_get_drvdata(&mhi_dev->dev);
+	struct wire_msg *msg = mhi_result->buf_addr;
+	struct resp_work *resp;
+
+	if (mhi_result->transaction_status || msg->hdr.magic_number != MANAGE_MAGIC_NUMBER) {
+		kfree(msg);
+		return;
+	}
+
+	resp = kmalloc(sizeof(*resp), GFP_ATOMIC);
+	if (!resp) {
+		kfree(msg);
+		return;
+	}
+
+	INIT_WORK(&resp->work, resp_worker);
+	resp->qdev = qdev;
+	resp->buf = msg;
+	queue_work(qdev->cntl_wq, &resp->work);
+}
+
+int qaic_control_open(struct qaic_device *qdev)
+{
+	if (!qdev->cntl_ch)
+		return -ENODEV;
+
+	qdev->cntl_lost_buf = false;
+	/*
+	 * By default qaic should assume that device has CRC enabled.
+	 * Qaic comes to know if device has CRC enabled or disabled during the
+	 * device status transaction, which is the first transaction performed
+	 * on control channel.
+	 *
+	 * So CRC validation of first device status transaction response is
+	 * ignored (by calling valid_crc_stub) and is done later during decoding
+	 * if device has CRC enabled.
+	 * Now that qaic knows whether device has CRC enabled or not it acts
+	 * accordingly.
+	 */
+	qdev->gen_crc = gen_crc;
+	qdev->valid_crc = valid_crc_stub;
+
+	return mhi_prepare_for_transfer(qdev->cntl_ch);
+}
+
+void qaic_control_close(struct qaic_device *qdev)
+{
+	mhi_unprepare_from_transfer(qdev->cntl_ch);
+}
+
+void qaic_release_usr(struct qaic_device *qdev, struct qaic_user *usr)
+{
+	struct wire_trans_terminate_to_dev *trans;
+	struct wrapper_list *wrappers;
+	struct wrapper_msg *wrapper;
+	struct wire_msg *msg;
+	struct wire_msg *rsp;
+
+	wrappers = alloc_wrapper_list();
+	if (!wrappers)
+		return;
+
+	wrapper = add_wrapper(wrappers, sizeof(*wrapper) + sizeof(*msg) + sizeof(*trans));
+	if (!wrapper)
+		return;
+
+	msg = &wrapper->msg;
+
+	trans = (struct wire_trans_terminate_to_dev *)msg->data;
+
+	trans->hdr.type = cpu_to_le32(QAIC_TRANS_TERMINATE_TO_DEV);
+	trans->hdr.len = cpu_to_le32(sizeof(*trans));
+	trans->handle = cpu_to_le32(usr->handle);
+
+	mutex_lock(&qdev->cntl_mutex);
+	wrapper->len = sizeof(msg->hdr) + sizeof(*trans);
+	msg->hdr.magic_number = MANAGE_MAGIC_NUMBER;
+	msg->hdr.sequence_number = cpu_to_le32(qdev->next_seq_num++);
+	msg->hdr.len = cpu_to_le32(wrapper->len);
+	msg->hdr.count = cpu_to_le32(1);
+	msg->hdr.handle = cpu_to_le32(usr->handle);
+	msg->hdr.padding = cpu_to_le32(0);
+	msg->hdr.crc32 = cpu_to_le32(qdev->gen_crc(wrappers));
+
+	/*
+	 * msg_xfer releases the mutex
+	 * We don't care about the return of msg_xfer since we will not do
+	 * anything different based on what happens.
+	 * We ignore pending signals since one will be set if the user is
+	 * killed, and we need give the device a chance to cleanup, otherwise
+	 * DMA may still be in progress when we return.
+	 */
+	rsp = msg_xfer(qdev, wrappers, qdev->next_seq_num - 1, true);
+	if (!IS_ERR(rsp))
+		kfree(rsp);
+	free_wrapper_from_list(wrappers, wrapper);
+}
+
+void wake_all_cntl(struct qaic_device *qdev)
+{
+	struct xfer_queue_elem *elem;
+	struct xfer_queue_elem *i;
+
+	mutex_lock(&qdev->cntl_mutex);
+	list_for_each_entry_safe(elem, i, &qdev->cntl_xfer_list, list) {
+		list_del_init(&elem->list);
+		complete_all(&elem->xfer_done);
+	}
+	mutex_unlock(&qdev->cntl_mutex);
+}
diff --git a/drivers/accel/qaic/qaic_data.c b/drivers/accel/qaic/qaic_data.c
new file mode 100644
index 000000000000..60cb4d65d48e
--- /dev/null
+++ b/drivers/accel/qaic/qaic_data.c
@@ -0,0 +1,2072 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. */
+/* Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. */
+
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/dma-buf.h>
+#include <linux/dma-mapping.h>
+#include <linux/interrupt.h>
+#include <linux/kref.h>
+#include <linux/list.h>
+#include <linux/math64.h>
+#include <linux/mm.h>
+#include <linux/moduleparam.h>
+#include <linux/scatterlist.h>
+#include <linux/spinlock.h>
+#include <linux/srcu.h>
+#include <linux/string.h>
+#include <linux/types.h>
+#include <linux/uaccess.h>
+#include <linux/wait.h>
+#include <drm/drm_file.h>
+#include <drm/drm_gem.h>
+#include <drm/drm_prime.h>
+#include <drm/drm_print.h>
+#include <uapi/drm/qaic_accel.h>
+
+#include "qaic.h"
+
+#define SEM_VAL_MASK	GENMASK_ULL(11, 0)
+#define SEM_INDEX_MASK	GENMASK_ULL(4, 0)
+#define BULK_XFER	BIT(3)
+#define GEN_COMPLETION	BIT(4)
+#define INBOUND_XFER	1
+#define OUTBOUND_XFER	2
+#define REQHP_OFF	0x0 /* we read this */
+#define REQTP_OFF	0x4 /* we write this */
+#define RSPHP_OFF	0x8 /* we write this */
+#define RSPTP_OFF	0xc /* we read this */
+
+#define ENCODE_SEM(val, index, sync, cmd, flags)			\
+		({							\
+			FIELD_PREP(GENMASK(11, 0), (val)) |		\
+			FIELD_PREP(GENMASK(20, 16), (index)) |		\
+			FIELD_PREP(BIT(22), (sync)) |			\
+			FIELD_PREP(GENMASK(26, 24), (cmd)) |		\
+			FIELD_PREP(GENMASK(30, 29), (flags)) |		\
+			FIELD_PREP(BIT(31), (cmd) ? 1 : 0);		\
+		})
+#define NUM_EVENTS	128
+#define NUM_DELAYS	10
+#define fifo_at(base, offset) ((base) + (offset) * get_dbc_req_elem_size())
+
+static unsigned int wait_exec_default_timeout_ms = 5000; /* 5 sec default */
+module_param(wait_exec_default_timeout_ms, uint, 0600);
+MODULE_PARM_DESC(wait_exec_default_timeout_ms, "Default timeout for DRM_IOCTL_QAIC_WAIT_BO");
+
+static unsigned int datapath_poll_interval_us = 100; /* 100 usec default */
+module_param(datapath_poll_interval_us, uint, 0600);
+MODULE_PARM_DESC(datapath_poll_interval_us,
+		 "Amount of time to sleep between activity when datapath polling is enabled");
+
+struct dbc_req {
+	/*
+	 * A request ID is assigned to each memory handle going in DMA queue.
+	 * As a single memory handle can enqueue multiple elements in DMA queue
+	 * all of them will have the same request ID.
+	 */
+	__le16	req_id;
+	/* Future use */
+	__u8	seq_id;
+	/*
+	 * Special encoded variable
+	 * 7	0 - Do not force to generate MSI after DMA is completed
+	 *	1 - Force to generate MSI after DMA is completed
+	 * 6:5	Reserved
+	 * 4	1 - Generate completion element in the response queue
+	 *	0 - No Completion Code
+	 * 3	0 - DMA request is a Link list transfer
+	 *	1 - DMA request is a Bulk transfer
+	 * 2	Reserved
+	 * 1:0	00 - No DMA transfer involved
+	 *	01 - DMA transfer is part of inbound transfer
+	 *	10 - DMA transfer has outbound transfer
+	 *	11 - NA
+	 */
+	__u8	cmd;
+	__le32	resv;
+	/* Source address for the transfer */
+	__le64	src_addr;
+	/* Destination address for the transfer */
+	__le64	dest_addr;
+	/* Length of transfer request */
+	__le32	len;
+	__le32	resv2;
+	/* Doorbell address */
+	__le64	db_addr;
+	/*
+	 * Special encoded variable
+	 * 7	1 - Doorbell(db) write
+	 *	0 - No doorbell write
+	 * 6:2	Reserved
+	 * 1:0	00 - 32 bit access, db address must be aligned to 32bit-boundary
+	 *	01 - 16 bit access, db address must be aligned to 16bit-boundary
+	 *	10 - 8 bit access, db address must be aligned to 8bit-boundary
+	 *	11 - Reserved
+	 */
+	__u8	db_len;
+	__u8	resv3;
+	__le16	resv4;
+	/* 32 bit data written to doorbell address */
+	__le32	db_data;
+	/*
+	 * Special encoded variable
+	 * All the fields of sem_cmdX are passed from user and all are ORed
+	 * together to form sem_cmd.
+	 * 0:11		Semaphore value
+	 * 15:12	Reserved
+	 * 20:16	Semaphore index
+	 * 21		Reserved
+	 * 22		Semaphore Sync
+	 * 23		Reserved
+	 * 26:24	Semaphore command
+	 * 28:27	Reserved
+	 * 29		Semaphore DMA out bound sync fence
+	 * 30		Semaphore DMA in bound sync fence
+	 * 31		Enable semaphore command
+	 */
+	__le32	sem_cmd0;
+	__le32	sem_cmd1;
+	__le32	sem_cmd2;
+	__le32	sem_cmd3;
+} __packed;
+
+struct dbc_rsp {
+	/* Request ID of the memory handle whose DMA transaction is completed */
+	__le16	req_id;
+	/* Status of the DMA transaction. 0 : Success otherwise failure */
+	__le16	status;
+} __packed;
+
+static inline bool bo_queued(struct qaic_bo *bo)
+{
+	return !list_empty(&bo->xfer_list);
+}
+
+inline int get_dbc_req_elem_size(void)
+{
+	return sizeof(struct dbc_req);
+}
+
+inline int get_dbc_rsp_elem_size(void)
+{
+	return sizeof(struct dbc_rsp);
+}
+
+static void free_slice(struct kref *kref)
+{
+	struct bo_slice *slice = container_of(kref, struct bo_slice, ref_count);
+
+	slice->bo->total_slice_nents -= slice->nents;
+	list_del(&slice->slice);
+	drm_gem_object_put(&slice->bo->base);
+	sg_free_table(slice->sgt);
+	kfree(slice->sgt);
+	kvfree(slice->reqs);
+	kfree(slice);
+}
+
+static int clone_range_of_sgt_for_slice(struct qaic_device *qdev, struct sg_table **sgt_out,
+					struct sg_table *sgt_in, u64 size, u64 offset)
+{
+	struct scatterlist *sg, *sgn, *sgf, *sgl;
+	unsigned int len, nents, offf, offl;
+	struct sg_table *sgt;
+	size_t total_len;
+	int ret, j;
+
+	/* find out number of relevant nents needed for this mem */
+	total_len = 0;
+	sgf = NULL;
+	sgl = NULL;
+	nents = 0;
+	offf = 0;
+	offl = 0;
+
+	size = size ? size : PAGE_SIZE;
+	for_each_sgtable_dma_sg(sgt_in, sg, j) {
+		len = sg_dma_len(sg);
+
+		if (!len)
+			continue;
+		if (offset >= total_len && offset < total_len + len) {
+			sgf = sg;
+			offf = offset - total_len;
+		}
+		if (sgf)
+			nents++;
+		if (offset + size >= total_len &&
+		    offset + size <= total_len + len) {
+			sgl = sg;
+			offl = offset + size - total_len;
+			break;
+		}
+		total_len += len;
+	}
+
+	if (!sgf || !sgl) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	sgt = kzalloc(sizeof(*sgt), GFP_KERNEL);
+	if (!sgt) {
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	ret = sg_alloc_table(sgt, nents, GFP_KERNEL);
+	if (ret)
+		goto free_sgt;
+
+	/* copy relevant sg node and fix page and length */
+	sgn = sgf;
+	for_each_sgtable_dma_sg(sgt, sg, j) {
+		memcpy(sg, sgn, sizeof(*sg));
+		if (sgn == sgf) {
+			sg_dma_address(sg) += offf;
+			sg_dma_len(sg) -= offf;
+			sg_set_page(sg, sg_page(sgn), sg_dma_len(sg), offf);
+		} else {
+			offf = 0;
+		}
+		if (sgn == sgl) {
+			sg_dma_len(sg) = offl - offf;
+			sg_set_page(sg, sg_page(sgn), offl - offf, offf);
+			sg_mark_end(sg);
+			break;
+		}
+		sgn = sg_next(sgn);
+	}
+
+	*sgt_out = sgt;
+	return ret;
+
+free_sgt:
+	kfree(sgt);
+out:
+	*sgt_out = NULL;
+	return ret;
+}
+
+static int encode_reqs(struct qaic_device *qdev, struct bo_slice *slice,
+		       struct qaic_attach_slice_entry *req)
+{
+	__le64 db_addr = cpu_to_le64(req->db_addr);
+	__le32 db_data = cpu_to_le32(req->db_data);
+	struct scatterlist *sg;
+	__u8 cmd = BULK_XFER;
+	int presync_sem;
+	u64 dev_addr;
+	__u8 db_len;
+	int i;
+
+	if (!slice->no_xfer)
+		cmd |= (slice->dir == DMA_TO_DEVICE ? INBOUND_XFER : OUTBOUND_XFER);
+
+	if (req->db_len && !IS_ALIGNED(req->db_addr, req->db_len / 8))
+		return -EINVAL;
+
+	presync_sem = req->sem0.presync + req->sem1.presync + req->sem2.presync + req->sem3.presync;
+	if (presync_sem > 1)
+		return -EINVAL;
+
+	presync_sem = req->sem0.presync << 0 | req->sem1.presync << 1 |
+		      req->sem2.presync << 2 | req->sem3.presync << 3;
+
+	switch (req->db_len) {
+	case 32:
+		db_len = BIT(7);
+		break;
+	case 16:
+		db_len = BIT(7) | 1;
+		break;
+	case 8:
+		db_len = BIT(7) | 2;
+		break;
+	case 0:
+		db_len = 0; /* doorbell is not active for this command */
+		break;
+	default:
+		return -EINVAL; /* should never hit this */
+	}
+
+	/*
+	 * When we end up splitting up a single request (ie a buf slice) into
+	 * multiple DMA requests, we have to manage the sync data carefully.
+	 * There can only be one presync sem. That needs to be on every xfer
+	 * so that the DMA engine doesn't transfer data before the receiver is
+	 * ready. We only do the doorbell and postsync sems after the xfer.
+	 * To guarantee previous xfers for the request are complete, we use a
+	 * fence.
+	 */
+	dev_addr = req->dev_addr;
+	for_each_sgtable_dma_sg(slice->sgt, sg, i) {
+		slice->reqs[i].cmd = cmd;
+		slice->reqs[i].src_addr = cpu_to_le64(slice->dir == DMA_TO_DEVICE ?
+						      sg_dma_address(sg) : dev_addr);
+		slice->reqs[i].dest_addr = cpu_to_le64(slice->dir == DMA_TO_DEVICE ?
+						       dev_addr : sg_dma_address(sg));
+		/*
+		 * sg_dma_len(sg) returns size of a DMA segment, maximum DMA
+		 * segment size is set to UINT_MAX by qaic and hence return
+		 * values of sg_dma_len(sg) can never exceed u32 range. So,
+		 * by down sizing we are not corrupting the value.
+		 */
+		slice->reqs[i].len = cpu_to_le32((u32)sg_dma_len(sg));
+		switch (presync_sem) {
+		case BIT(0):
+			slice->reqs[i].sem_cmd0 = cpu_to_le32(ENCODE_SEM(req->sem0.val,
+									 req->sem0.index,
+									 req->sem0.presync,
+									 req->sem0.cmd,
+									 req->sem0.flags));
+			break;
+		case BIT(1):
+			slice->reqs[i].sem_cmd1 = cpu_to_le32(ENCODE_SEM(req->sem1.val,
+									 req->sem1.index,
+									 req->sem1.presync,
+									 req->sem1.cmd,
+									 req->sem1.flags));
+			break;
+		case BIT(2):
+			slice->reqs[i].sem_cmd2 = cpu_to_le32(ENCODE_SEM(req->sem2.val,
+									 req->sem2.index,
+									 req->sem2.presync,
+									 req->sem2.cmd,
+									 req->sem2.flags));
+			break;
+		case BIT(3):
+			slice->reqs[i].sem_cmd3 = cpu_to_le32(ENCODE_SEM(req->sem3.val,
+									 req->sem3.index,
+									 req->sem3.presync,
+									 req->sem3.cmd,
+									 req->sem3.flags));
+			break;
+		}
+		dev_addr += sg_dma_len(sg);
+	}
+	/* add post transfer stuff to last segment */
+	i--;
+	slice->reqs[i].cmd |= GEN_COMPLETION;
+	slice->reqs[i].db_addr = db_addr;
+	slice->reqs[i].db_len = db_len;
+	slice->reqs[i].db_data = db_data;
+	/*
+	 * Add a fence if we have more than one request going to the hardware
+	 * representing the entirety of the user request, and the user request
+	 * has no presync condition.
+	 * Fences are expensive, so we try to avoid them. We rely on the
+	 * hardware behavior to avoid needing one when there is a presync
+	 * condition. When a presync exists, all requests for that same
+	 * presync will be queued into a fifo. Thus, since we queue the
+	 * post xfer activity only on the last request we queue, the hardware
+	 * will ensure that the last queued request is processed last, thus
+	 * making sure the post xfer activity happens at the right time without
+	 * a fence.
+	 */
+	if (i && !presync_sem)
+		req->sem0.flags |= (slice->dir == DMA_TO_DEVICE ?
+				    QAIC_SEM_INSYNCFENCE : QAIC_SEM_OUTSYNCFENCE);
+	slice->reqs[i].sem_cmd0 = cpu_to_le32(ENCODE_SEM(req->sem0.val, req->sem0.index,
+							 req->sem0.presync, req->sem0.cmd,
+							 req->sem0.flags));
+	slice->reqs[i].sem_cmd1 = cpu_to_le32(ENCODE_SEM(req->sem1.val, req->sem1.index,
+							 req->sem1.presync, req->sem1.cmd,
+							 req->sem1.flags));
+	slice->reqs[i].sem_cmd2 = cpu_to_le32(ENCODE_SEM(req->sem2.val, req->sem2.index,
+							 req->sem2.presync, req->sem2.cmd,
+							 req->sem2.flags));
+	slice->reqs[i].sem_cmd3 = cpu_to_le32(ENCODE_SEM(req->sem3.val, req->sem3.index,
+							 req->sem3.presync, req->sem3.cmd,
+							 req->sem3.flags));
+
+	return 0;
+}
+
+static int qaic_map_one_slice(struct qaic_device *qdev, struct qaic_bo *bo,
+			      struct qaic_attach_slice_entry *slice_ent)
+{
+	struct sg_table *sgt = NULL;
+	struct bo_slice *slice;
+	int ret;
+
+	ret = clone_range_of_sgt_for_slice(qdev, &sgt, bo->sgt, slice_ent->size, slice_ent->offset);
+	if (ret)
+		goto out;
+
+	slice = kmalloc(sizeof(*slice), GFP_KERNEL);
+	if (!slice) {
+		ret = -ENOMEM;
+		goto free_sgt;
+	}
+
+	slice->reqs = kvcalloc(sgt->nents, sizeof(*slice->reqs), GFP_KERNEL);
+	if (!slice->reqs) {
+		ret = -ENOMEM;
+		goto free_slice;
+	}
+
+	slice->no_xfer = !slice_ent->size;
+	slice->sgt = sgt;
+	slice->nents = sgt->nents;
+	slice->dir = bo->dir;
+	slice->bo = bo;
+	slice->size = slice_ent->size;
+	slice->offset = slice_ent->offset;
+
+	ret = encode_reqs(qdev, slice, slice_ent);
+	if (ret)
+		goto free_req;
+
+	bo->total_slice_nents += sgt->nents;
+	kref_init(&slice->ref_count);
+	drm_gem_object_get(&bo->base);
+	list_add_tail(&slice->slice, &bo->slices);
+
+	return 0;
+
+free_req:
+	kvfree(slice->reqs);
+free_slice:
+	kfree(slice);
+free_sgt:
+	sg_free_table(sgt);
+	kfree(sgt);
+out:
+	return ret;
+}
+
+static int create_sgt(struct qaic_device *qdev, struct sg_table **sgt_out, u64 size)
+{
+	struct scatterlist *sg;
+	struct sg_table *sgt;
+	struct page **pages;
+	int *pages_order;
+	int buf_extra;
+	int max_order;
+	int nr_pages;
+	int ret = 0;
+	int i, j, k;
+	int order;
+
+	if (size) {
+		nr_pages = DIV_ROUND_UP(size, PAGE_SIZE);
+		/*
+		 * calculate how much extra we are going to allocate, to remove
+		 * later
+		 */
+		buf_extra = (PAGE_SIZE - size % PAGE_SIZE) % PAGE_SIZE;
+		max_order = min(MAX_PAGE_ORDER, get_order(size));
+	} else {
+		/* allocate a single page for book keeping */
+		nr_pages = 1;
+		buf_extra = 0;
+		max_order = 0;
+	}
+
+	pages = kvmalloc_array(nr_pages, sizeof(*pages) + sizeof(*pages_order), GFP_KERNEL);
+	if (!pages) {
+		ret = -ENOMEM;
+		goto out;
+	}
+	pages_order = (void *)pages + sizeof(*pages) * nr_pages;
+
+	/*
+	 * Allocate requested memory using alloc_pages. It is possible to allocate
+	 * the requested memory in multiple chunks by calling alloc_pages
+	 * multiple times. Use SG table to handle multiple allocated pages.
+	 */
+	i = 0;
+	while (nr_pages > 0) {
+		order = min(get_order(nr_pages * PAGE_SIZE), max_order);
+		while (1) {
+			pages[i] = alloc_pages(GFP_KERNEL | GFP_HIGHUSER |
+					       __GFP_NOWARN | __GFP_ZERO |
+					       (order ? __GFP_NORETRY : __GFP_RETRY_MAYFAIL),
+					       order);
+			if (pages[i])
+				break;
+			if (!order--) {
+				ret = -ENOMEM;
+				goto free_partial_alloc;
+			}
+		}
+
+		max_order = order;
+		pages_order[i] = order;
+
+		nr_pages -= 1 << order;
+		if (nr_pages <= 0)
+			/* account for over allocation */
+			buf_extra += abs(nr_pages) * PAGE_SIZE;
+		i++;
+	}
+
+	sgt = kmalloc(sizeof(*sgt), GFP_KERNEL);
+	if (!sgt) {
+		ret = -ENOMEM;
+		goto free_partial_alloc;
+	}
+
+	if (sg_alloc_table(sgt, i, GFP_KERNEL)) {
+		ret = -ENOMEM;
+		goto free_sgt;
+	}
+
+	/* Populate the SG table with the allocated memory pages */
+	sg = sgt->sgl;
+	for (k = 0; k < i; k++, sg = sg_next(sg)) {
+		/* Last entry requires special handling */
+		if (k < i - 1) {
+			sg_set_page(sg, pages[k], PAGE_SIZE << pages_order[k], 0);
+		} else {
+			sg_set_page(sg, pages[k], (PAGE_SIZE << pages_order[k]) - buf_extra, 0);
+			sg_mark_end(sg);
+		}
+	}
+
+	kvfree(pages);
+	*sgt_out = sgt;
+	return ret;
+
+free_sgt:
+	kfree(sgt);
+free_partial_alloc:
+	for (j = 0; j < i; j++)
+		__free_pages(pages[j], pages_order[j]);
+	kvfree(pages);
+out:
+	*sgt_out = NULL;
+	return ret;
+}
+
+static bool invalid_sem(struct qaic_sem *sem)
+{
+	if (sem->val & ~SEM_VAL_MASK || sem->index & ~SEM_INDEX_MASK ||
+	    !(sem->presync == 0 || sem->presync == 1) || sem->pad ||
+	    sem->flags & ~(QAIC_SEM_INSYNCFENCE | QAIC_SEM_OUTSYNCFENCE) ||
+	    sem->cmd > QAIC_SEM_WAIT_GT_0)
+		return true;
+	return false;
+}
+
+static int qaic_validate_req(struct qaic_device *qdev, struct qaic_attach_slice_entry *slice_ent,
+			     u32 count, u64 total_size)
+{
+	u64 total;
+	int i;
+
+	for (i = 0; i < count; i++) {
+		if (!(slice_ent[i].db_len == 32 || slice_ent[i].db_len == 16 ||
+		      slice_ent[i].db_len == 8 || slice_ent[i].db_len == 0) ||
+		      invalid_sem(&slice_ent[i].sem0) || invalid_sem(&slice_ent[i].sem1) ||
+		      invalid_sem(&slice_ent[i].sem2) || invalid_sem(&slice_ent[i].sem3))
+			return -EINVAL;
+
+		if (check_add_overflow(slice_ent[i].offset, slice_ent[i].size, &total) ||
+		    total > total_size)
+			return -EINVAL;
+	}
+
+	return 0;
+}
+
+static void qaic_free_sgt(struct sg_table *sgt)
+{
+	struct scatterlist *sg;
+
+	if (!sgt)
+		return;
+
+	for (sg = sgt->sgl; sg; sg = sg_next(sg))
+		if (sg_page(sg))
+			__free_pages(sg_page(sg), get_order(sg->length));
+	sg_free_table(sgt);
+	kfree(sgt);
+}
+
+static void qaic_gem_print_info(struct drm_printer *p, unsigned int indent,
+				const struct drm_gem_object *obj)
+{
+	struct qaic_bo *bo = to_qaic_bo(obj);
+
+	drm_printf_indent(p, indent, "BO DMA direction %d\n", bo->dir);
+}
+
+static const struct vm_operations_struct drm_vm_ops = {
+	.open = drm_gem_vm_open,
+	.close = drm_gem_vm_close,
+};
+
+static int qaic_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma)
+{
+	struct qaic_bo *bo = to_qaic_bo(obj);
+	unsigned long offset = 0;
+	struct scatterlist *sg;
+	int ret = 0;
+
+	if (drm_gem_is_imported(obj))
+		return -EINVAL;
+
+	for (sg = bo->sgt->sgl; sg; sg = sg_next(sg)) {
+		if (sg_page(sg)) {
+			ret = remap_pfn_range(vma, vma->vm_start + offset, page_to_pfn(sg_page(sg)),
+					      sg->length, vma->vm_page_prot);
+			if (ret)
+				goto out;
+			offset += sg->length;
+		}
+	}
+
+out:
+	return ret;
+}
+
+static void qaic_free_object(struct drm_gem_object *obj)
+{
+	struct qaic_bo *bo = to_qaic_bo(obj);
+
+	if (drm_gem_is_imported(obj)) {
+		/* DMABUF/PRIME Path */
+		drm_prime_gem_destroy(obj, NULL);
+	} else {
+		/* Private buffer allocation path */
+		qaic_free_sgt(bo->sgt);
+	}
+
+	mutex_destroy(&bo->lock);
+	drm_gem_object_release(obj);
+	kfree(bo);
+}
+
+static struct sg_table *qaic_get_sg_table(struct drm_gem_object *obj)
+{
+	struct qaic_bo *bo = to_qaic_bo(obj);
+	struct scatterlist *sg, *sg_in;
+	struct sg_table *sgt, *sgt_in;
+	int i;
+
+	sgt_in = bo->sgt;
+
+	sgt = kmalloc(sizeof(*sgt), GFP_KERNEL);
+	if (!sgt)
+		return ERR_PTR(-ENOMEM);
+
+	if (sg_alloc_table(sgt, sgt_in->orig_nents, GFP_KERNEL)) {
+		kfree(sgt);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	sg = sgt->sgl;
+	for_each_sgtable_sg(sgt_in, sg_in, i) {
+		memcpy(sg, sg_in, sizeof(*sg));
+		sg = sg_next(sg);
+	}
+
+	return sgt;
+}
+
+static const struct drm_gem_object_funcs qaic_gem_funcs = {
+	.free = qaic_free_object,
+	.get_sg_table = qaic_get_sg_table,
+	.print_info = qaic_gem_print_info,
+	.mmap = qaic_gem_object_mmap,
+	.vm_ops = &drm_vm_ops,
+};
+
+static void qaic_init_bo(struct qaic_bo *bo, bool reinit)
+{
+	if (reinit) {
+		bo->sliced = false;
+		reinit_completion(&bo->xfer_done);
+	} else {
+		mutex_init(&bo->lock);
+		init_completion(&bo->xfer_done);
+	}
+	complete_all(&bo->xfer_done);
+	INIT_LIST_HEAD(&bo->slices);
+	INIT_LIST_HEAD(&bo->xfer_list);
+}
+
+static struct qaic_bo *qaic_alloc_init_bo(void)
+{
+	struct qaic_bo *bo;
+
+	bo = kzalloc(sizeof(*bo), GFP_KERNEL);
+	if (!bo)
+		return ERR_PTR(-ENOMEM);
+
+	qaic_init_bo(bo, false);
+
+	return bo;
+}
+
+int qaic_create_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv)
+{
+	struct qaic_create_bo *args = data;
+	int usr_rcu_id, qdev_rcu_id;
+	struct drm_gem_object *obj;
+	struct qaic_device *qdev;
+	struct qaic_user *usr;
+	struct qaic_bo *bo;
+	size_t size;
+	int ret;
+
+	if (args->pad)
+		return -EINVAL;
+
+	size = PAGE_ALIGN(args->size);
+	if (size == 0)
+		return -EINVAL;
+
+	usr = file_priv->driver_priv;
+	usr_rcu_id = srcu_read_lock(&usr->qddev_lock);
+	if (!usr->qddev) {
+		ret = -ENODEV;
+		goto unlock_usr_srcu;
+	}
+
+	qdev = usr->qddev->qdev;
+	qdev_rcu_id = srcu_read_lock(&qdev->dev_lock);
+	if (qdev->dev_state != QAIC_ONLINE) {
+		ret = -ENODEV;
+		goto unlock_dev_srcu;
+	}
+
+	bo = qaic_alloc_init_bo();
+	if (IS_ERR(bo)) {
+		ret = PTR_ERR(bo);
+		goto unlock_dev_srcu;
+	}
+	obj = &bo->base;
+
+	drm_gem_private_object_init(dev, obj, size);
+
+	obj->funcs = &qaic_gem_funcs;
+	ret = create_sgt(qdev, &bo->sgt, size);
+	if (ret)
+		goto free_bo;
+
+	ret = drm_gem_create_mmap_offset(obj);
+	if (ret)
+		goto free_bo;
+
+	ret = drm_gem_handle_create(file_priv, obj, &args->handle);
+	if (ret)
+		goto free_bo;
+
+	drm_gem_object_put(obj);
+	srcu_read_unlock(&qdev->dev_lock, qdev_rcu_id);
+	srcu_read_unlock(&usr->qddev_lock, usr_rcu_id);
+
+	return 0;
+
+free_bo:
+	drm_gem_object_put(obj);
+unlock_dev_srcu:
+	srcu_read_unlock(&qdev->dev_lock, qdev_rcu_id);
+unlock_usr_srcu:
+	srcu_read_unlock(&usr->qddev_lock, usr_rcu_id);
+	return ret;
+}
+
+int qaic_mmap_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv)
+{
+	struct qaic_mmap_bo *args = data;
+	int usr_rcu_id, qdev_rcu_id;
+	struct drm_gem_object *obj;
+	struct qaic_device *qdev;
+	struct qaic_user *usr;
+	int ret = 0;
+
+	usr = file_priv->driver_priv;
+	usr_rcu_id = srcu_read_lock(&usr->qddev_lock);
+	if (!usr->qddev) {
+		ret = -ENODEV;
+		goto unlock_usr_srcu;
+	}
+
+	qdev = usr->qddev->qdev;
+	qdev_rcu_id = srcu_read_lock(&qdev->dev_lock);
+	if (qdev->dev_state != QAIC_ONLINE) {
+		ret = -ENODEV;
+		goto unlock_dev_srcu;
+	}
+
+	obj = drm_gem_object_lookup(file_priv, args->handle);
+	if (!obj) {
+		ret = -ENOENT;
+		goto unlock_dev_srcu;
+	}
+
+	args->offset = drm_vma_node_offset_addr(&obj->vma_node);
+
+	drm_gem_object_put(obj);
+
+unlock_dev_srcu:
+	srcu_read_unlock(&qdev->dev_lock, qdev_rcu_id);
+unlock_usr_srcu:
+	srcu_read_unlock(&usr->qddev_lock, usr_rcu_id);
+	return ret;
+}
+
+struct drm_gem_object *qaic_gem_prime_import(struct drm_device *dev, struct dma_buf *dma_buf)
+{
+	struct dma_buf_attachment *attach;
+	struct drm_gem_object *obj;
+	struct qaic_bo *bo;
+	int ret;
+
+	bo = qaic_alloc_init_bo();
+	if (IS_ERR(bo)) {
+		ret = PTR_ERR(bo);
+		goto out;
+	}
+
+	obj = &bo->base;
+	get_dma_buf(dma_buf);
+
+	attach = dma_buf_attach(dma_buf, dev->dev);
+	if (IS_ERR(attach)) {
+		ret = PTR_ERR(attach);
+		goto attach_fail;
+	}
+
+	if (!attach->dmabuf->size) {
+		ret = -EINVAL;
+		goto size_align_fail;
+	}
+
+	drm_gem_private_object_init(dev, obj, attach->dmabuf->size);
+	/*
+	 * skipping dma_buf_map_attachment() as we do not know the direction
+	 * just yet. Once the direction is known in the subsequent IOCTL to
+	 * attach slicing, we can do it then.
+	 */
+
+	obj->funcs = &qaic_gem_funcs;
+	obj->import_attach = attach;
+	obj->resv = dma_buf->resv;
+
+	return obj;
+
+size_align_fail:
+	dma_buf_detach(dma_buf, attach);
+attach_fail:
+	dma_buf_put(dma_buf);
+	kfree(bo);
+out:
+	return ERR_PTR(ret);
+}
+
+static int qaic_prepare_import_bo(struct qaic_bo *bo, struct qaic_attach_slice_hdr *hdr)
+{
+	struct drm_gem_object *obj = &bo->base;
+	struct sg_table *sgt;
+	int ret;
+
+	sgt = dma_buf_map_attachment(obj->import_attach, hdr->dir);
+	if (IS_ERR(sgt)) {
+		ret = PTR_ERR(sgt);
+		return ret;
+	}
+
+	bo->sgt = sgt;
+
+	return 0;
+}
+
+static int qaic_prepare_export_bo(struct qaic_device *qdev, struct qaic_bo *bo,
+				  struct qaic_attach_slice_hdr *hdr)
+{
+	int ret;
+
+	ret = dma_map_sgtable(&qdev->pdev->dev, bo->sgt, hdr->dir, 0);
+	if (ret)
+		return -EFAULT;
+
+	return 0;
+}
+
+static int qaic_prepare_bo(struct qaic_device *qdev, struct qaic_bo *bo,
+			   struct qaic_attach_slice_hdr *hdr)
+{
+	int ret;
+
+	if (drm_gem_is_imported(&bo->base))
+		ret = qaic_prepare_import_bo(bo, hdr);
+	else
+		ret = qaic_prepare_export_bo(qdev, bo, hdr);
+	bo->dir = hdr->dir;
+	bo->dbc = &qdev->dbc[hdr->dbc_id];
+	bo->nr_slice = hdr->count;
+
+	return ret;
+}
+
+static void qaic_unprepare_import_bo(struct qaic_bo *bo)
+{
+	dma_buf_unmap_attachment(bo->base.import_attach, bo->sgt, bo->dir);
+	bo->sgt = NULL;
+}
+
+static void qaic_unprepare_export_bo(struct qaic_device *qdev, struct qaic_bo *bo)
+{
+	dma_unmap_sgtable(&qdev->pdev->dev, bo->sgt, bo->dir, 0);
+}
+
+static void qaic_unprepare_bo(struct qaic_device *qdev, struct qaic_bo *bo)
+{
+	if (drm_gem_is_imported(&bo->base))
+		qaic_unprepare_import_bo(bo);
+	else
+		qaic_unprepare_export_bo(qdev, bo);
+
+	bo->dir = 0;
+	bo->dbc = NULL;
+	bo->nr_slice = 0;
+}
+
+static void qaic_free_slices_bo(struct qaic_bo *bo)
+{
+	struct bo_slice *slice, *temp;
+
+	list_for_each_entry_safe(slice, temp, &bo->slices, slice)
+		kref_put(&slice->ref_count, free_slice);
+	if (WARN_ON_ONCE(bo->total_slice_nents != 0))
+		bo->total_slice_nents = 0;
+	bo->nr_slice = 0;
+}
+
+static int qaic_attach_slicing_bo(struct qaic_device *qdev, struct qaic_bo *bo,
+				  struct qaic_attach_slice_hdr *hdr,
+				  struct qaic_attach_slice_entry *slice_ent)
+{
+	int ret, i;
+
+	for (i = 0; i < hdr->count; i++) {
+		ret = qaic_map_one_slice(qdev, bo, &slice_ent[i]);
+		if (ret) {
+			qaic_free_slices_bo(bo);
+			return ret;
+		}
+	}
+
+	if (bo->total_slice_nents > bo->dbc->nelem) {
+		qaic_free_slices_bo(bo);
+		return -ENOSPC;
+	}
+
+	return 0;
+}
+
+int qaic_attach_slice_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv)
+{
+	struct qaic_attach_slice_entry *slice_ent;
+	struct qaic_attach_slice *args = data;
+	int rcu_id, usr_rcu_id, qdev_rcu_id;
+	struct dma_bridge_chan	*dbc;
+	struct drm_gem_object *obj;
+	struct qaic_device *qdev;
+	unsigned long arg_size;
+	struct qaic_user *usr;
+	u8 __user *user_data;
+	struct qaic_bo *bo;
+	int ret;
+
+	if (args->hdr.count == 0)
+		return -EINVAL;
+
+	if (check_mul_overflow((unsigned long)args->hdr.count,
+			       (unsigned long)sizeof(*slice_ent),
+			       &arg_size))
+		return -EINVAL;
+
+	if (!(args->hdr.dir == DMA_TO_DEVICE || args->hdr.dir == DMA_FROM_DEVICE))
+		return -EINVAL;
+
+	if (args->data == 0)
+		return -EINVAL;
+
+	usr = file_priv->driver_priv;
+	usr_rcu_id = srcu_read_lock(&usr->qddev_lock);
+	if (!usr->qddev) {
+		ret = -ENODEV;
+		goto unlock_usr_srcu;
+	}
+
+	qdev = usr->qddev->qdev;
+	qdev_rcu_id = srcu_read_lock(&qdev->dev_lock);
+	if (qdev->dev_state != QAIC_ONLINE) {
+		ret = -ENODEV;
+		goto unlock_dev_srcu;
+	}
+
+	if (args->hdr.dbc_id >= qdev->num_dbc) {
+		ret = -EINVAL;
+		goto unlock_dev_srcu;
+	}
+
+	user_data = u64_to_user_ptr(args->data);
+
+	slice_ent = memdup_user(user_data, arg_size);
+	if (IS_ERR(slice_ent)) {
+		ret = PTR_ERR(slice_ent);
+		goto unlock_dev_srcu;
+	}
+
+	obj = drm_gem_object_lookup(file_priv, args->hdr.handle);
+	if (!obj) {
+		ret = -ENOENT;
+		goto free_slice_ent;
+	}
+
+	ret = qaic_validate_req(qdev, slice_ent, args->hdr.count, obj->size);
+	if (ret)
+		goto put_bo;
+
+	bo = to_qaic_bo(obj);
+	ret = mutex_lock_interruptible(&bo->lock);
+	if (ret)
+		goto put_bo;
+
+	if (bo->sliced) {
+		ret = -EINVAL;
+		goto unlock_bo;
+	}
+
+	dbc = &qdev->dbc[args->hdr.dbc_id];
+	rcu_id = srcu_read_lock(&dbc->ch_lock);
+	if (dbc->usr != usr) {
+		ret = -EINVAL;
+		goto unlock_ch_srcu;
+	}
+
+	if (dbc->id == qdev->ssr_dbc) {
+		ret = -EPIPE;
+		goto unlock_ch_srcu;
+	}
+
+	ret = qaic_prepare_bo(qdev, bo, &args->hdr);
+	if (ret)
+		goto unlock_ch_srcu;
+
+	ret = qaic_attach_slicing_bo(qdev, bo, &args->hdr, slice_ent);
+	if (ret)
+		goto unprepare_bo;
+
+	if (args->hdr.dir == DMA_TO_DEVICE)
+		dma_sync_sgtable_for_cpu(&qdev->pdev->dev, bo->sgt, args->hdr.dir);
+
+	bo->sliced = true;
+	list_add_tail(&bo->bo_list, &bo->dbc->bo_lists);
+	srcu_read_unlock(&dbc->ch_lock, rcu_id);
+	mutex_unlock(&bo->lock);
+	kfree(slice_ent);
+	srcu_read_unlock(&qdev->dev_lock, qdev_rcu_id);
+	srcu_read_unlock(&usr->qddev_lock, usr_rcu_id);
+
+	return 0;
+
+unprepare_bo:
+	qaic_unprepare_bo(qdev, bo);
+unlock_ch_srcu:
+	srcu_read_unlock(&dbc->ch_lock, rcu_id);
+unlock_bo:
+	mutex_unlock(&bo->lock);
+put_bo:
+	drm_gem_object_put(obj);
+free_slice_ent:
+	kfree(slice_ent);
+unlock_dev_srcu:
+	srcu_read_unlock(&qdev->dev_lock, qdev_rcu_id);
+unlock_usr_srcu:
+	srcu_read_unlock(&usr->qddev_lock, usr_rcu_id);
+	return ret;
+}
+
+static inline u32 fifo_space_avail(u32 head, u32 tail, u32 q_size)
+{
+	u32 avail = head - tail - 1;
+
+	if (head <= tail)
+		avail += q_size;
+
+	return avail;
+}
+
+static inline int copy_exec_reqs(struct qaic_device *qdev, struct bo_slice *slice, u32 dbc_id,
+				 u32 head, u32 *ptail)
+{
+	struct dma_bridge_chan *dbc = &qdev->dbc[dbc_id];
+	struct dbc_req *reqs = slice->reqs;
+	u32 tail = *ptail;
+	u32 avail;
+
+	avail = fifo_space_avail(head, tail, dbc->nelem);
+	if (avail < slice->nents)
+		return -EAGAIN;
+
+	if (tail + slice->nents > dbc->nelem) {
+		avail = dbc->nelem - tail;
+		avail = min_t(u32, avail, slice->nents);
+		memcpy(fifo_at(dbc->req_q_base, tail), reqs, sizeof(*reqs) * avail);
+		reqs += avail;
+		avail = slice->nents - avail;
+		if (avail)
+			memcpy(dbc->req_q_base, reqs, sizeof(*reqs) * avail);
+	} else {
+		memcpy(fifo_at(dbc->req_q_base, tail), reqs, sizeof(*reqs) * slice->nents);
+	}
+
+	*ptail = (tail + slice->nents) % dbc->nelem;
+
+	return 0;
+}
+
+static inline int copy_partial_exec_reqs(struct qaic_device *qdev, struct bo_slice *slice,
+					 u64 resize, struct dma_bridge_chan *dbc, u32 head,
+					 u32 *ptail)
+{
+	struct dbc_req *reqs = slice->reqs;
+	struct dbc_req *last_req;
+	u32 tail = *ptail;
+	u64 last_bytes;
+	u32 first_n;
+	u32 avail;
+
+	avail = fifo_space_avail(head, tail, dbc->nelem);
+
+	/*
+	 * After this for loop is complete, first_n represents the index
+	 * of the last DMA request of this slice that needs to be
+	 * transferred after resizing and last_bytes represents DMA size
+	 * of that request.
+	 */
+	last_bytes = resize;
+	for (first_n = 0; first_n < slice->nents; first_n++)
+		if (last_bytes > le32_to_cpu(reqs[first_n].len))
+			last_bytes -= le32_to_cpu(reqs[first_n].len);
+		else
+			break;
+
+	if (avail < (first_n + 1))
+		return -EAGAIN;
+
+	if (first_n) {
+		if (tail + first_n > dbc->nelem) {
+			avail = dbc->nelem - tail;
+			avail = min_t(u32, avail, first_n);
+			memcpy(fifo_at(dbc->req_q_base, tail), reqs, sizeof(*reqs) * avail);
+			last_req = reqs + avail;
+			avail = first_n - avail;
+			if (avail)
+				memcpy(dbc->req_q_base, last_req, sizeof(*reqs) * avail);
+		} else {
+			memcpy(fifo_at(dbc->req_q_base, tail), reqs, sizeof(*reqs) * first_n);
+		}
+	}
+
+	/*
+	 * Copy over the last entry. Here we need to adjust len to the left over
+	 * size, and set src and dst to the entry it is copied to.
+	 */
+	last_req = fifo_at(dbc->req_q_base, (tail + first_n) % dbc->nelem);
+	memcpy(last_req, reqs + slice->nents - 1, sizeof(*reqs));
+
+	/*
+	 * last_bytes holds size of a DMA segment, maximum DMA segment size is
+	 * set to UINT_MAX by qaic and hence last_bytes can never exceed u32
+	 * range. So, by down sizing we are not corrupting the value.
+	 */
+	last_req->len = cpu_to_le32((u32)last_bytes);
+	last_req->src_addr = reqs[first_n].src_addr;
+	last_req->dest_addr = reqs[first_n].dest_addr;
+	if (!last_bytes)
+		/* Disable DMA transfer */
+		last_req->cmd = GENMASK(7, 2) & reqs[first_n].cmd;
+
+	*ptail = (tail + first_n + 1) % dbc->nelem;
+
+	return 0;
+}
+
+static int send_bo_list_to_device(struct qaic_device *qdev, struct drm_file *file_priv,
+				  struct qaic_execute_entry *exec, unsigned int count,
+				  bool is_partial, struct dma_bridge_chan *dbc, u32 head,
+				  u32 *tail)
+{
+	struct qaic_partial_execute_entry *pexec = (struct qaic_partial_execute_entry *)exec;
+	struct drm_gem_object *obj;
+	struct bo_slice *slice;
+	unsigned long flags;
+	struct qaic_bo *bo;
+	int i, j;
+	int ret;
+
+	for (i = 0; i < count; i++) {
+		/*
+		 * ref count will be decremented when the transfer of this
+		 * buffer is complete. It is inside dbc_irq_threaded_fn().
+		 */
+		obj = drm_gem_object_lookup(file_priv,
+					    is_partial ? pexec[i].handle : exec[i].handle);
+		if (!obj) {
+			ret = -ENOENT;
+			goto failed_to_send_bo;
+		}
+
+		bo = to_qaic_bo(obj);
+		ret = mutex_lock_interruptible(&bo->lock);
+		if (ret)
+			goto failed_to_send_bo;
+
+		if (!bo->sliced) {
+			ret = -EINVAL;
+			goto unlock_bo;
+		}
+
+		if (is_partial && pexec[i].resize > bo->base.size) {
+			ret = -EINVAL;
+			goto unlock_bo;
+		}
+
+		spin_lock_irqsave(&dbc->xfer_lock, flags);
+		if (bo_queued(bo)) {
+			spin_unlock_irqrestore(&dbc->xfer_lock, flags);
+			ret = -EINVAL;
+			goto unlock_bo;
+		}
+
+		bo->req_id = dbc->next_req_id++;
+
+		list_for_each_entry(slice, &bo->slices, slice) {
+			for (j = 0; j < slice->nents; j++)
+				slice->reqs[j].req_id = cpu_to_le16(bo->req_id);
+
+			if (is_partial && (!pexec[i].resize || pexec[i].resize <= slice->offset))
+				/* Configure the slice for no DMA transfer */
+				ret = copy_partial_exec_reqs(qdev, slice, 0, dbc, head, tail);
+			else if (is_partial && pexec[i].resize < slice->offset + slice->size)
+				/* Configure the slice to be partially DMA transferred */
+				ret = copy_partial_exec_reqs(qdev, slice,
+							     pexec[i].resize - slice->offset, dbc,
+							     head, tail);
+			else
+				ret = copy_exec_reqs(qdev, slice, dbc->id, head, tail);
+			if (ret) {
+				spin_unlock_irqrestore(&dbc->xfer_lock, flags);
+				goto unlock_bo;
+			}
+		}
+		reinit_completion(&bo->xfer_done);
+		list_add_tail(&bo->xfer_list, &dbc->xfer_list);
+		spin_unlock_irqrestore(&dbc->xfer_lock, flags);
+		dma_sync_sgtable_for_device(&qdev->pdev->dev, bo->sgt, bo->dir);
+		mutex_unlock(&bo->lock);
+	}
+
+	return 0;
+
+unlock_bo:
+	mutex_unlock(&bo->lock);
+failed_to_send_bo:
+	if (likely(obj))
+		drm_gem_object_put(obj);
+	for (j = 0; j < i; j++) {
+		spin_lock_irqsave(&dbc->xfer_lock, flags);
+		bo = list_last_entry(&dbc->xfer_list, struct qaic_bo, xfer_list);
+		obj = &bo->base;
+		list_del_init(&bo->xfer_list);
+		spin_unlock_irqrestore(&dbc->xfer_lock, flags);
+		dma_sync_sgtable_for_cpu(&qdev->pdev->dev, bo->sgt, bo->dir);
+		drm_gem_object_put(obj);
+	}
+	return ret;
+}
+
+static void update_profiling_data(struct drm_file *file_priv,
+				  struct qaic_execute_entry *exec, unsigned int count,
+				  bool is_partial, u64 received_ts, u64 submit_ts, u32 queue_level)
+{
+	struct qaic_partial_execute_entry *pexec = (struct qaic_partial_execute_entry *)exec;
+	struct drm_gem_object *obj;
+	struct qaic_bo *bo;
+	int i;
+
+	for (i = 0; i < count; i++) {
+		/*
+		 * Since we already committed the BO to hardware, the only way
+		 * this should fail is a pending signal. We can't cancel the
+		 * submit to hardware, so we have to just skip the profiling
+		 * data. In case the signal is not fatal to the process, we
+		 * return success so that the user doesn't try to resubmit.
+		 */
+		obj = drm_gem_object_lookup(file_priv,
+					    is_partial ? pexec[i].handle : exec[i].handle);
+		if (!obj)
+			break;
+		bo = to_qaic_bo(obj);
+		bo->perf_stats.req_received_ts = received_ts;
+		bo->perf_stats.req_submit_ts = submit_ts;
+		bo->perf_stats.queue_level_before = queue_level;
+		queue_level += bo->total_slice_nents;
+		drm_gem_object_put(obj);
+	}
+}
+
+static int __qaic_execute_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv,
+				   bool is_partial)
+{
+	struct qaic_execute *args = data;
+	struct qaic_execute_entry *exec;
+	struct dma_bridge_chan *dbc;
+	int usr_rcu_id, qdev_rcu_id;
+	struct qaic_device *qdev;
+	struct qaic_user *usr;
+	u64 received_ts;
+	u32 queue_level;
+	u64 submit_ts;
+	int rcu_id;
+	u32 head;
+	u32 tail;
+	u64 size;
+	int ret;
+
+	received_ts = ktime_get_ns();
+
+	size = is_partial ? sizeof(struct qaic_partial_execute_entry) : sizeof(*exec);
+	if (args->hdr.count == 0)
+		return -EINVAL;
+
+	exec = memdup_array_user(u64_to_user_ptr(args->data), args->hdr.count, size);
+	if (IS_ERR(exec))
+		return PTR_ERR(exec);
+
+	usr = file_priv->driver_priv;
+	usr_rcu_id = srcu_read_lock(&usr->qddev_lock);
+	if (!usr->qddev) {
+		ret = -ENODEV;
+		goto unlock_usr_srcu;
+	}
+
+	qdev = usr->qddev->qdev;
+	qdev_rcu_id = srcu_read_lock(&qdev->dev_lock);
+	if (qdev->dev_state != QAIC_ONLINE) {
+		ret = -ENODEV;
+		goto unlock_dev_srcu;
+	}
+
+	if (args->hdr.dbc_id >= qdev->num_dbc) {
+		ret = -EINVAL;
+		goto unlock_dev_srcu;
+	}
+
+	dbc = &qdev->dbc[args->hdr.dbc_id];
+
+	rcu_id = srcu_read_lock(&dbc->ch_lock);
+	if (!dbc->usr || dbc->usr->handle != usr->handle) {
+		ret = -EPERM;
+		goto release_ch_rcu;
+	}
+
+	if (dbc->id == qdev->ssr_dbc) {
+		ret = -EPIPE;
+		goto release_ch_rcu;
+	}
+
+	ret = mutex_lock_interruptible(&dbc->req_lock);
+	if (ret)
+		goto release_ch_rcu;
+
+	head = readl(dbc->dbc_base + REQHP_OFF);
+	tail = readl(dbc->dbc_base + REQTP_OFF);
+
+	if (head == U32_MAX || tail == U32_MAX) {
+		/* PCI link error */
+		ret = -ENODEV;
+		goto unlock_req_lock;
+	}
+
+	queue_level = head <= tail ? tail - head : dbc->nelem - (head - tail);
+
+	ret = send_bo_list_to_device(qdev, file_priv, exec, args->hdr.count, is_partial, dbc,
+				     head, &tail);
+	if (ret)
+		goto unlock_req_lock;
+
+	/* Finalize commit to hardware */
+	submit_ts = ktime_get_ns();
+	writel(tail, dbc->dbc_base + REQTP_OFF);
+	mutex_unlock(&dbc->req_lock);
+
+	update_profiling_data(file_priv, exec, args->hdr.count, is_partial, received_ts,
+			      submit_ts, queue_level);
+
+	if (datapath_polling)
+		schedule_work(&dbc->poll_work);
+
+unlock_req_lock:
+	if (ret)
+		mutex_unlock(&dbc->req_lock);
+release_ch_rcu:
+	srcu_read_unlock(&dbc->ch_lock, rcu_id);
+unlock_dev_srcu:
+	srcu_read_unlock(&qdev->dev_lock, qdev_rcu_id);
+unlock_usr_srcu:
+	srcu_read_unlock(&usr->qddev_lock, usr_rcu_id);
+	kfree(exec);
+	return ret;
+}
+
+int qaic_execute_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv)
+{
+	return __qaic_execute_bo_ioctl(dev, data, file_priv, false);
+}
+
+int qaic_partial_execute_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv)
+{
+	return __qaic_execute_bo_ioctl(dev, data, file_priv, true);
+}
+
+/*
+ * Our interrupt handling is a bit more complicated than a simple ideal, but
+ * sadly necessary.
+ *
+ * Each dbc has a completion queue. Entries in the queue correspond to DMA
+ * requests which the device has processed. The hardware already has a built
+ * in irq mitigation. When the device puts an entry into the queue, it will
+ * only trigger an interrupt if the queue was empty. Therefore, when adding
+ * the Nth event to a non-empty queue, the hardware doesn't trigger an
+ * interrupt. This means the host doesn't get additional interrupts signaling
+ * the same thing - the queue has something to process.
+ * This behavior can be overridden in the DMA request.
+ * This means that when the host receives an interrupt, it is required to
+ * drain the queue.
+ *
+ * This behavior is what NAPI attempts to accomplish, although we can't use
+ * NAPI as we don't have a netdev. We use threaded irqs instead.
+ *
+ * However, there is a situation where the host drains the queue fast enough
+ * that every event causes an interrupt. Typically this is not a problem as
+ * the rate of events would be low. However, that is not the case with
+ * lprnet for example. On an Intel Xeon D-2191 where we run 8 instances of
+ * lprnet, the host receives roughly 80k interrupts per second from the device
+ * (per /proc/interrupts). While NAPI documentation indicates the host should
+ * just chug along, sadly that behavior causes instability in some hosts.
+ *
+ * Therefore, we implement an interrupt disable scheme similar to NAPI. The
+ * key difference is that we will delay after draining the queue for a small
+ * time to allow additional events to come in via polling. Using the above
+ * lprnet workload, this reduces the number of interrupts processed from
+ * ~80k/sec to about 64 in 5 minutes and appears to solve the system
+ * instability.
+ */
+irqreturn_t dbc_irq_handler(int irq, void *data)
+{
+	struct dma_bridge_chan *dbc = data;
+	int rcu_id;
+	u32 head;
+	u32 tail;
+
+	rcu_id = srcu_read_lock(&dbc->ch_lock);
+
+	if (datapath_polling) {
+		srcu_read_unlock(&dbc->ch_lock, rcu_id);
+		/*
+		 * Normally datapath_polling will not have irqs enabled, but
+		 * when running with only one MSI the interrupt is shared with
+		 * MHI so it cannot be disabled. Return ASAP instead.
+		 */
+		return IRQ_HANDLED;
+	}
+
+	if (!dbc->usr) {
+		srcu_read_unlock(&dbc->ch_lock, rcu_id);
+		return IRQ_HANDLED;
+	}
+
+	head = readl(dbc->dbc_base + RSPHP_OFF);
+	if (head == U32_MAX) { /* PCI link error */
+		srcu_read_unlock(&dbc->ch_lock, rcu_id);
+		return IRQ_NONE;
+	}
+
+	tail = readl(dbc->dbc_base + RSPTP_OFF);
+	if (tail == U32_MAX) { /* PCI link error */
+		srcu_read_unlock(&dbc->ch_lock, rcu_id);
+		return IRQ_NONE;
+	}
+
+	if (head == tail) { /* queue empty */
+		srcu_read_unlock(&dbc->ch_lock, rcu_id);
+		return IRQ_NONE;
+	}
+
+	if (!dbc->qdev->single_msi)
+		disable_irq_nosync(irq);
+	srcu_read_unlock(&dbc->ch_lock, rcu_id);
+	return IRQ_WAKE_THREAD;
+}
+
+void qaic_irq_polling_work(struct work_struct *work)
+{
+	struct dma_bridge_chan *dbc = container_of(work, struct dma_bridge_chan,  poll_work);
+	unsigned long flags;
+	int rcu_id;
+	u32 head;
+	u32 tail;
+
+	rcu_id = srcu_read_lock(&dbc->ch_lock);
+
+	while (1) {
+		if (dbc->qdev->dev_state != QAIC_ONLINE) {
+			srcu_read_unlock(&dbc->ch_lock, rcu_id);
+			return;
+		}
+		if (!dbc->usr) {
+			srcu_read_unlock(&dbc->ch_lock, rcu_id);
+			return;
+		}
+		spin_lock_irqsave(&dbc->xfer_lock, flags);
+		if (list_empty(&dbc->xfer_list)) {
+			spin_unlock_irqrestore(&dbc->xfer_lock, flags);
+			srcu_read_unlock(&dbc->ch_lock, rcu_id);
+			return;
+		}
+		spin_unlock_irqrestore(&dbc->xfer_lock, flags);
+
+		head = readl(dbc->dbc_base + RSPHP_OFF);
+		if (head == U32_MAX) { /* PCI link error */
+			srcu_read_unlock(&dbc->ch_lock, rcu_id);
+			return;
+		}
+
+		tail = readl(dbc->dbc_base + RSPTP_OFF);
+		if (tail == U32_MAX) { /* PCI link error */
+			srcu_read_unlock(&dbc->ch_lock, rcu_id);
+			return;
+		}
+
+		if (head != tail) {
+			irq_wake_thread(dbc->irq, dbc);
+			srcu_read_unlock(&dbc->ch_lock, rcu_id);
+			return;
+		}
+
+		cond_resched();
+		usleep_range(datapath_poll_interval_us, 2 * datapath_poll_interval_us);
+	}
+}
+
+irqreturn_t dbc_irq_threaded_fn(int irq, void *data)
+{
+	struct dma_bridge_chan *dbc = data;
+	int event_count = NUM_EVENTS;
+	int delay_count = NUM_DELAYS;
+	struct qaic_device *qdev;
+	struct qaic_bo *bo, *i;
+	struct dbc_rsp *rsp;
+	unsigned long flags;
+	int rcu_id;
+	u16 status;
+	u16 req_id;
+	u32 head;
+	u32 tail;
+
+	rcu_id = srcu_read_lock(&dbc->ch_lock);
+	qdev = dbc->qdev;
+
+	head = readl(dbc->dbc_base + RSPHP_OFF);
+	if (head == U32_MAX) /* PCI link error */
+		goto error_out;
+
+read_fifo:
+
+	if (!event_count) {
+		event_count = NUM_EVENTS;
+		cond_resched();
+	}
+
+	/*
+	 * if this channel isn't assigned or gets unassigned during processing
+	 * we have nothing further to do
+	 */
+	if (!dbc->usr)
+		goto error_out;
+
+	tail = readl(dbc->dbc_base + RSPTP_OFF);
+	if (tail == U32_MAX) /* PCI link error */
+		goto error_out;
+
+	if (head == tail) { /* queue empty */
+		if (delay_count) {
+			--delay_count;
+			usleep_range(100, 200);
+			goto read_fifo; /* check for a new event */
+		}
+		goto normal_out;
+	}
+
+	delay_count = NUM_DELAYS;
+	while (head != tail) {
+		if (!event_count)
+			break;
+		--event_count;
+		rsp = dbc->rsp_q_base + head * sizeof(*rsp);
+		req_id = le16_to_cpu(rsp->req_id);
+		status = le16_to_cpu(rsp->status);
+		if (status)
+			pci_dbg(qdev->pdev, "req_id %d failed with status %d\n", req_id, status);
+		spin_lock_irqsave(&dbc->xfer_lock, flags);
+		/*
+		 * A BO can receive multiple interrupts, since a BO can be
+		 * divided into multiple slices and a buffer receives as many
+		 * interrupts as slices. So until it receives interrupts for
+		 * all the slices we cannot mark that buffer complete.
+		 */
+		list_for_each_entry_safe(bo, i, &dbc->xfer_list, xfer_list) {
+			if (bo->req_id == req_id)
+				bo->nr_slice_xfer_done++;
+			else
+				continue;
+
+			if (bo->nr_slice_xfer_done < bo->nr_slice)
+				break;
+
+			/*
+			 * At this point we have received all the interrupts for
+			 * BO, which means BO execution is complete.
+			 */
+			dma_sync_sgtable_for_cpu(&qdev->pdev->dev, bo->sgt, bo->dir);
+			bo->nr_slice_xfer_done = 0;
+			list_del_init(&bo->xfer_list);
+			bo->perf_stats.req_processed_ts = ktime_get_ns();
+			complete_all(&bo->xfer_done);
+			drm_gem_object_put(&bo->base);
+			break;
+		}
+		spin_unlock_irqrestore(&dbc->xfer_lock, flags);
+		head = (head + 1) % dbc->nelem;
+	}
+
+	/*
+	 * Update the head pointer of response queue and let the device know
+	 * that we have consumed elements from the queue.
+	 */
+	writel(head, dbc->dbc_base + RSPHP_OFF);
+
+	/* elements might have been put in the queue while we were processing */
+	goto read_fifo;
+
+normal_out:
+	if (!qdev->single_msi && likely(!datapath_polling))
+		enable_irq(irq);
+	else if (unlikely(datapath_polling))
+		schedule_work(&dbc->poll_work);
+	/* checking the fifo and enabling irqs is a race, missed event check */
+	tail = readl(dbc->dbc_base + RSPTP_OFF);
+	if (tail != U32_MAX && head != tail) {
+		if (!qdev->single_msi && likely(!datapath_polling))
+			disable_irq_nosync(irq);
+		goto read_fifo;
+	}
+	srcu_read_unlock(&dbc->ch_lock, rcu_id);
+	return IRQ_HANDLED;
+
+error_out:
+	srcu_read_unlock(&dbc->ch_lock, rcu_id);
+	if (!qdev->single_msi && likely(!datapath_polling))
+		enable_irq(irq);
+	else if (unlikely(datapath_polling))
+		schedule_work(&dbc->poll_work);
+
+	return IRQ_HANDLED;
+}
+
+int qaic_wait_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv)
+{
+	struct qaic_wait *args = data;
+	int usr_rcu_id, qdev_rcu_id;
+	struct dma_bridge_chan *dbc;
+	struct drm_gem_object *obj;
+	struct qaic_device *qdev;
+	unsigned long timeout;
+	struct qaic_user *usr;
+	struct qaic_bo *bo;
+	int rcu_id;
+	int ret;
+
+	if (args->pad != 0)
+		return -EINVAL;
+
+	usr = file_priv->driver_priv;
+	usr_rcu_id = srcu_read_lock(&usr->qddev_lock);
+	if (!usr->qddev) {
+		ret = -ENODEV;
+		goto unlock_usr_srcu;
+	}
+
+	qdev = usr->qddev->qdev;
+	qdev_rcu_id = srcu_read_lock(&qdev->dev_lock);
+	if (qdev->dev_state != QAIC_ONLINE) {
+		ret = -ENODEV;
+		goto unlock_dev_srcu;
+	}
+
+	if (args->dbc_id >= qdev->num_dbc) {
+		ret = -EINVAL;
+		goto unlock_dev_srcu;
+	}
+
+	dbc = &qdev->dbc[args->dbc_id];
+
+	rcu_id = srcu_read_lock(&dbc->ch_lock);
+	if (dbc->usr != usr) {
+		ret = -EPERM;
+		goto unlock_ch_srcu;
+	}
+
+	if (dbc->id == qdev->ssr_dbc) {
+		ret = -EPIPE;
+		goto unlock_ch_srcu;
+	}
+
+	obj = drm_gem_object_lookup(file_priv, args->handle);
+	if (!obj) {
+		ret = -ENOENT;
+		goto unlock_ch_srcu;
+	}
+
+	bo = to_qaic_bo(obj);
+	timeout = args->timeout ? args->timeout : wait_exec_default_timeout_ms;
+	timeout = msecs_to_jiffies(timeout);
+	ret = wait_for_completion_interruptible_timeout(&bo->xfer_done, timeout);
+	if (!ret) {
+		ret = -ETIMEDOUT;
+		goto put_obj;
+	}
+	if (ret > 0)
+		ret = 0;
+
+	if (!dbc->usr)
+		ret = -EPERM;
+
+	if (dbc->id == qdev->ssr_dbc)
+		ret = -EPIPE;
+
+put_obj:
+	drm_gem_object_put(obj);
+unlock_ch_srcu:
+	srcu_read_unlock(&dbc->ch_lock, rcu_id);
+unlock_dev_srcu:
+	srcu_read_unlock(&qdev->dev_lock, qdev_rcu_id);
+unlock_usr_srcu:
+	srcu_read_unlock(&usr->qddev_lock, usr_rcu_id);
+	return ret;
+}
+
+int qaic_perf_stats_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv)
+{
+	struct qaic_perf_stats_entry *ent = NULL;
+	struct qaic_perf_stats *args = data;
+	int usr_rcu_id, qdev_rcu_id;
+	struct drm_gem_object *obj;
+	struct qaic_device *qdev;
+	struct qaic_user *usr;
+	struct qaic_bo *bo;
+	int ret = 0;
+	int i;
+
+	usr = file_priv->driver_priv;
+	usr_rcu_id = srcu_read_lock(&usr->qddev_lock);
+	if (!usr->qddev) {
+		ret = -ENODEV;
+		goto unlock_usr_srcu;
+	}
+
+	qdev = usr->qddev->qdev;
+	qdev_rcu_id = srcu_read_lock(&qdev->dev_lock);
+	if (qdev->dev_state != QAIC_ONLINE) {
+		ret = -ENODEV;
+		goto unlock_dev_srcu;
+	}
+
+	if (args->hdr.dbc_id >= qdev->num_dbc) {
+		ret = -EINVAL;
+		goto unlock_dev_srcu;
+	}
+
+	ent = memdup_array_user(u64_to_user_ptr(args->data), args->hdr.count, sizeof(*ent));
+	if (IS_ERR(ent)) {
+		ret = PTR_ERR(ent);
+		goto unlock_dev_srcu;
+	}
+
+	for (i = 0; i < args->hdr.count; i++) {
+		obj = drm_gem_object_lookup(file_priv, ent[i].handle);
+		if (!obj) {
+			ret = -ENOENT;
+			goto free_ent;
+		}
+		bo = to_qaic_bo(obj);
+		if (!bo->sliced) {
+			drm_gem_object_put(obj);
+			ret = -EINVAL;
+			goto free_ent;
+		}
+		if (bo->dbc->id != args->hdr.dbc_id) {
+			drm_gem_object_put(obj);
+			ret = -EINVAL;
+			goto free_ent;
+		}
+		/*
+		 * perf stats ioctl is called before wait ioctl is complete then
+		 * the latency information is invalid.
+		 */
+		if (bo->perf_stats.req_processed_ts < bo->perf_stats.req_submit_ts) {
+			ent[i].device_latency_us = 0;
+		} else {
+			ent[i].device_latency_us = div_u64((bo->perf_stats.req_processed_ts -
+							    bo->perf_stats.req_submit_ts), 1000);
+		}
+		ent[i].submit_latency_us = div_u64((bo->perf_stats.req_submit_ts -
+						    bo->perf_stats.req_received_ts), 1000);
+		ent[i].queue_level_before = bo->perf_stats.queue_level_before;
+		ent[i].num_queue_element = bo->total_slice_nents;
+		drm_gem_object_put(obj);
+	}
+
+	if (copy_to_user(u64_to_user_ptr(args->data), ent, args->hdr.count * sizeof(*ent)))
+		ret = -EFAULT;
+
+free_ent:
+	kfree(ent);
+unlock_dev_srcu:
+	srcu_read_unlock(&qdev->dev_lock, qdev_rcu_id);
+unlock_usr_srcu:
+	srcu_read_unlock(&usr->qddev_lock, usr_rcu_id);
+	return ret;
+}
+
+static void detach_slice_bo(struct qaic_device *qdev, struct qaic_bo *bo)
+{
+	qaic_free_slices_bo(bo);
+	qaic_unprepare_bo(qdev, bo);
+	qaic_init_bo(bo, true);
+	list_del(&bo->bo_list);
+	drm_gem_object_put(&bo->base);
+}
+
+int qaic_detach_slice_bo_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv)
+{
+	struct qaic_detach_slice *args = data;
+	int rcu_id, usr_rcu_id, qdev_rcu_id;
+	struct dma_bridge_chan *dbc;
+	struct drm_gem_object *obj;
+	struct qaic_device *qdev;
+	struct qaic_user *usr;
+	unsigned long flags;
+	struct qaic_bo *bo;
+	int ret;
+
+	if (args->pad != 0)
+		return -EINVAL;
+
+	usr = file_priv->driver_priv;
+	usr_rcu_id = srcu_read_lock(&usr->qddev_lock);
+	if (!usr->qddev) {
+		ret = -ENODEV;
+		goto unlock_usr_srcu;
+	}
+
+	qdev = usr->qddev->qdev;
+	qdev_rcu_id = srcu_read_lock(&qdev->dev_lock);
+	if (qdev->dev_state != QAIC_ONLINE) {
+		ret = -ENODEV;
+		goto unlock_dev_srcu;
+	}
+
+	obj = drm_gem_object_lookup(file_priv, args->handle);
+	if (!obj) {
+		ret = -ENOENT;
+		goto unlock_dev_srcu;
+	}
+
+	bo = to_qaic_bo(obj);
+	ret = mutex_lock_interruptible(&bo->lock);
+	if (ret)
+		goto put_bo;
+
+	if (!bo->sliced) {
+		ret = -EINVAL;
+		goto unlock_bo;
+	}
+
+	dbc = bo->dbc;
+	rcu_id = srcu_read_lock(&dbc->ch_lock);
+	if (dbc->usr != usr) {
+		ret = -EINVAL;
+		goto unlock_ch_srcu;
+	}
+
+	/* Check if BO is committed to H/W for DMA */
+	spin_lock_irqsave(&dbc->xfer_lock, flags);
+	if (bo_queued(bo)) {
+		spin_unlock_irqrestore(&dbc->xfer_lock, flags);
+		ret = -EBUSY;
+		goto unlock_ch_srcu;
+	}
+	spin_unlock_irqrestore(&dbc->xfer_lock, flags);
+
+	detach_slice_bo(qdev, bo);
+
+unlock_ch_srcu:
+	srcu_read_unlock(&dbc->ch_lock, rcu_id);
+unlock_bo:
+	mutex_unlock(&bo->lock);
+put_bo:
+	drm_gem_object_put(obj);
+unlock_dev_srcu:
+	srcu_read_unlock(&qdev->dev_lock, qdev_rcu_id);
+unlock_usr_srcu:
+	srcu_read_unlock(&usr->qddev_lock, usr_rcu_id);
+	return ret;
+}
+
+static void empty_xfer_list(struct qaic_device *qdev, struct dma_bridge_chan *dbc)
+{
+	unsigned long flags;
+	struct qaic_bo *bo;
+
+	spin_lock_irqsave(&dbc->xfer_lock, flags);
+	while (!list_empty(&dbc->xfer_list)) {
+		bo = list_first_entry(&dbc->xfer_list, typeof(*bo), xfer_list);
+		list_del_init(&bo->xfer_list);
+		spin_unlock_irqrestore(&dbc->xfer_lock, flags);
+		bo->nr_slice_xfer_done = 0;
+		bo->req_id = 0;
+		bo->perf_stats.req_received_ts = 0;
+		bo->perf_stats.req_submit_ts = 0;
+		bo->perf_stats.req_processed_ts = 0;
+		bo->perf_stats.queue_level_before = 0;
+		dma_sync_sgtable_for_cpu(&qdev->pdev->dev, bo->sgt, bo->dir);
+		complete_all(&bo->xfer_done);
+		drm_gem_object_put(&bo->base);
+		spin_lock_irqsave(&dbc->xfer_lock, flags);
+	}
+	spin_unlock_irqrestore(&dbc->xfer_lock, flags);
+}
+
+static void sync_empty_xfer_list(struct qaic_device *qdev, struct dma_bridge_chan *dbc)
+{
+	empty_xfer_list(qdev, dbc);
+	synchronize_srcu(&dbc->ch_lock);
+	/*
+	 * Threads holding channel lock, may add more elements in the xfer_list.
+	 * Flush out these elements from xfer_list.
+	 */
+	empty_xfer_list(qdev, dbc);
+}
+
+int disable_dbc(struct qaic_device *qdev, u32 dbc_id, struct qaic_user *usr)
+{
+	if (!qdev->dbc[dbc_id].usr || qdev->dbc[dbc_id].usr->handle != usr->handle)
+		return -EPERM;
+
+	qdev->dbc[dbc_id].usr = NULL;
+	synchronize_srcu(&qdev->dbc[dbc_id].ch_lock);
+	return 0;
+}
+
+/**
+ * enable_dbc - Enable the DBC. DBCs are disabled by removing the context of
+ * user. Add user context back to DBC to enable it. This function trusts the
+ * DBC ID passed and expects the DBC to be disabled.
+ * @qdev: qaic device handle
+ * @dbc_id: ID of the DBC
+ * @usr: User context
+ */
+void enable_dbc(struct qaic_device *qdev, u32 dbc_id, struct qaic_user *usr)
+{
+	qdev->dbc[dbc_id].usr = usr;
+}
+
+void wakeup_dbc(struct qaic_device *qdev, u32 dbc_id)
+{
+	struct dma_bridge_chan *dbc = &qdev->dbc[dbc_id];
+
+	dbc->usr = NULL;
+	sync_empty_xfer_list(qdev, dbc);
+}
+
+void release_dbc(struct qaic_device *qdev, u32 dbc_id)
+{
+	struct qaic_bo *bo, *bo_temp;
+	struct dma_bridge_chan *dbc;
+
+	dbc = &qdev->dbc[dbc_id];
+	if (!dbc->in_use)
+		return;
+
+	wakeup_dbc(qdev, dbc_id);
+
+	dma_free_coherent(&qdev->pdev->dev, dbc->total_size, dbc->req_q_base, dbc->dma_addr);
+	dbc->total_size = 0;
+	dbc->req_q_base = NULL;
+	dbc->dma_addr = 0;
+	dbc->nelem = 0;
+	dbc->usr = NULL;
+
+	list_for_each_entry_safe(bo, bo_temp, &dbc->bo_lists, bo_list) {
+		drm_gem_object_get(&bo->base);
+		mutex_lock(&bo->lock);
+		detach_slice_bo(qdev, bo);
+		mutex_unlock(&bo->lock);
+		drm_gem_object_put(&bo->base);
+	}
+
+	dbc->in_use = false;
+	wake_up(&dbc->dbc_release);
+}
+
+void qaic_data_get_fifo_info(struct dma_bridge_chan *dbc, u32 *head, u32 *tail)
+{
+	if (!dbc || !head || !tail)
+		return;
+
+	*head = readl(dbc->dbc_base + REQHP_OFF);
+	*tail = readl(dbc->dbc_base + REQTP_OFF);
+}
+
+/*
+ * qaic_dbc_enter_ssr - Prepare to enter in sub system reset(SSR) for given DBC ID.
+ * @qdev: qaic device handle
+ * @dbc_id: ID of the DBC which will enter SSR
+ *
+ * The device will automatically deactivate the workload as not
+ * all errors can be silently recovered. The user will be
+ * notified and will need to decide the required recovery
+ * action to take.
+ */
+void qaic_dbc_enter_ssr(struct qaic_device *qdev, u32 dbc_id)
+{
+	qdev->ssr_dbc = dbc_id;
+	release_dbc(qdev, dbc_id);
+}
+
+/*
+ * qaic_dbc_exit_ssr - Prepare to exit from sub system reset(SSR) for given DBC ID.
+ * @qdev: qaic device handle
+ *
+ * The DBC returns to an operational state and begins accepting work after exiting SSR.
+ */
+void qaic_dbc_exit_ssr(struct qaic_device *qdev)
+{
+	qdev->ssr_dbc = QAIC_SSR_DBC_SENTINEL;
+}
diff --git a/drivers/accel/qaic/qaic_debugfs.c b/drivers/accel/qaic/qaic_debugfs.c
new file mode 100644
index 000000000000..8dc4fe5bb560
--- /dev/null
+++ b/drivers/accel/qaic/qaic_debugfs.c
@@ -0,0 +1,304 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/* Copyright (c) 2020, The Linux Foundation. All rights reserved. */
+/* Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. */
+
+#include <linux/debugfs.h>
+#include <linux/device.h>
+#include <linux/fs.h>
+#include <linux/list.h>
+#include <linux/mhi.h>
+#include <linux/mutex.h>
+#include <linux/overflow.h>
+#include <linux/pci.h>
+#include <linux/seq_file.h>
+#include <linux/sprintf.h>
+#include <linux/string.h>
+#include <linux/types.h>
+#include <linux/workqueue.h>
+
+#include "qaic.h"
+#include "qaic_debugfs.h"
+
+#define BOOTLOG_POOL_SIZE		16
+#define BOOTLOG_MSG_SIZE		512
+#define QAIC_DBC_DIR_NAME		9
+
+struct bootlog_msg {
+	/* Buffer for bootlog messages */
+	char str[BOOTLOG_MSG_SIZE];
+	/* Root struct of device, used to access device resources */
+	struct qaic_device *qdev;
+	/* Work struct to schedule work coming on QAIC_LOGGING channel */
+	struct work_struct work;
+};
+
+struct bootlog_page {
+	/* Node in list of bootlog pages maintained by root device struct */
+	struct list_head node;
+	/* Total size of the buffer that holds the bootlogs. It is PAGE_SIZE */
+	unsigned int size;
+	/* Offset for the next bootlog */
+	unsigned int offset;
+};
+
+static int bootlog_show(struct seq_file *s, void *unused)
+{
+	struct bootlog_page *page;
+	struct qaic_device *qdev;
+	void *page_end;
+	void *log;
+
+	qdev = s->private;
+	mutex_lock(&qdev->bootlog_mutex);
+	list_for_each_entry(page, &qdev->bootlog, node) {
+		log = page + 1;
+		page_end = (void *)page + page->offset;
+		while (log < page_end) {
+			seq_printf(s, "%s", (char *)log);
+			log += strlen(log) + 1;
+		}
+	}
+	mutex_unlock(&qdev->bootlog_mutex);
+
+	return 0;
+}
+
+DEFINE_SHOW_ATTRIBUTE(bootlog);
+
+static int fifo_size_show(struct seq_file *s, void *unused)
+{
+	struct dma_bridge_chan *dbc = s->private;
+
+	seq_printf(s, "%u\n", dbc->nelem);
+	return 0;
+}
+
+DEFINE_SHOW_ATTRIBUTE(fifo_size);
+
+static int queued_show(struct seq_file *s, void *unused)
+{
+	struct dma_bridge_chan *dbc = s->private;
+	u32 tail = 0, head = 0;
+
+	qaic_data_get_fifo_info(dbc, &head, &tail);
+
+	if (head == U32_MAX || tail == U32_MAX)
+		seq_printf(s, "%u\n", 0);
+	else if (head > tail)
+		seq_printf(s, "%u\n", dbc->nelem - head + tail);
+	else
+		seq_printf(s, "%u\n", tail - head);
+
+	return 0;
+}
+
+DEFINE_SHOW_ATTRIBUTE(queued);
+
+void qaic_debugfs_init(struct qaic_drm_device *qddev)
+{
+	struct qaic_device *qdev = qddev->qdev;
+	struct dentry *debugfs_root;
+	struct dentry *debugfs_dir;
+	char name[QAIC_DBC_DIR_NAME];
+	u32 i;
+
+	debugfs_root = to_drm(qddev)->debugfs_root;
+
+	debugfs_create_file("bootlog", 0400, debugfs_root, qdev, &bootlog_fops);
+	/*
+	 * 256 dbcs per device is likely the max we will ever see and lets static checking see a
+	 * reasonable range.
+	 */
+	for (i = 0; i < qdev->num_dbc && i < 256; ++i) {
+		snprintf(name, QAIC_DBC_DIR_NAME, "dbc%03u", i);
+		debugfs_dir = debugfs_create_dir(name, debugfs_root);
+		debugfs_create_file("fifo_size", 0400, debugfs_dir, &qdev->dbc[i], &fifo_size_fops);
+		debugfs_create_file("queued", 0400, debugfs_dir, &qdev->dbc[i], &queued_fops);
+	}
+}
+
+static struct bootlog_page *alloc_bootlog_page(struct qaic_device *qdev)
+{
+	struct bootlog_page *page;
+
+	page = (struct bootlog_page *)devm_get_free_pages(&qdev->pdev->dev, GFP_KERNEL, 0);
+	if (!page)
+		return page;
+
+	page->size = PAGE_SIZE;
+	page->offset = sizeof(*page);
+	list_add_tail(&page->node, &qdev->bootlog);
+
+	return page;
+}
+
+static int reset_bootlog(struct qaic_device *qdev)
+{
+	struct bootlog_page *page;
+	struct bootlog_page *i;
+
+	mutex_lock(&qdev->bootlog_mutex);
+	list_for_each_entry_safe(page, i, &qdev->bootlog, node) {
+		list_del(&page->node);
+		devm_free_pages(&qdev->pdev->dev, (unsigned long)page);
+	}
+
+	page = alloc_bootlog_page(qdev);
+	mutex_unlock(&qdev->bootlog_mutex);
+	if (!page)
+		return -ENOMEM;
+
+	return 0;
+}
+
+static void *bootlog_get_space(struct qaic_device *qdev, unsigned int size)
+{
+	struct bootlog_page *page;
+
+	page = list_last_entry(&qdev->bootlog, struct bootlog_page, node);
+
+	if (size_add(size, sizeof(*page)) > page->size)
+		return NULL;
+
+	if (page->offset + size > page->size) {
+		page = alloc_bootlog_page(qdev);
+		if (!page)
+			return NULL;
+	}
+
+	return (void *)page + page->offset;
+}
+
+static void bootlog_commit(struct qaic_device *qdev, unsigned int size)
+{
+	struct bootlog_page *page;
+
+	page = list_last_entry(&qdev->bootlog, struct bootlog_page, node);
+
+	page->offset += size;
+}
+
+static void bootlog_log(struct work_struct *work)
+{
+	struct bootlog_msg *msg = container_of(work, struct bootlog_msg, work);
+	unsigned int len = strlen(msg->str) + 1;
+	struct qaic_device *qdev = msg->qdev;
+	void *log;
+
+	mutex_lock(&qdev->bootlog_mutex);
+	log = bootlog_get_space(qdev, len);
+	if (log) {
+		memcpy(log, msg, len);
+		bootlog_commit(qdev, len);
+	}
+	mutex_unlock(&qdev->bootlog_mutex);
+
+	if (mhi_queue_buf(qdev->bootlog_ch, DMA_FROM_DEVICE, msg, BOOTLOG_MSG_SIZE, MHI_EOT))
+		devm_kfree(&qdev->pdev->dev, msg);
+}
+
+static int qaic_bootlog_mhi_probe(struct mhi_device *mhi_dev, const struct mhi_device_id *id)
+{
+	struct qaic_device *qdev = pci_get_drvdata(to_pci_dev(mhi_dev->mhi_cntrl->cntrl_dev));
+	struct bootlog_msg *msg;
+	int i, ret;
+
+	qdev->bootlog_wq = alloc_ordered_workqueue("qaic_bootlog", 0);
+	if (!qdev->bootlog_wq) {
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	ret = reset_bootlog(qdev);
+	if (ret)
+		goto destroy_workqueue;
+
+	ret = mhi_prepare_for_transfer(mhi_dev);
+	if (ret)
+		goto destroy_workqueue;
+
+	dev_set_drvdata(&mhi_dev->dev, qdev);
+	qdev->bootlog_ch = mhi_dev;
+
+	for (i = 0; i < BOOTLOG_POOL_SIZE; i++) {
+		msg = devm_kzalloc(&qdev->pdev->dev, sizeof(*msg), GFP_KERNEL);
+		if (!msg) {
+			ret = -ENOMEM;
+			goto mhi_unprepare;
+		}
+
+		msg->qdev = qdev;
+		INIT_WORK(&msg->work, bootlog_log);
+
+		ret = mhi_queue_buf(mhi_dev, DMA_FROM_DEVICE, msg, BOOTLOG_MSG_SIZE, MHI_EOT);
+		if (ret)
+			goto mhi_unprepare;
+	}
+
+	return 0;
+
+mhi_unprepare:
+	mhi_unprepare_from_transfer(mhi_dev);
+destroy_workqueue:
+	destroy_workqueue(qdev->bootlog_wq);
+out:
+	return ret;
+}
+
+static void qaic_bootlog_mhi_remove(struct mhi_device *mhi_dev)
+{
+	struct qaic_device *qdev;
+
+	qdev = dev_get_drvdata(&mhi_dev->dev);
+
+	mhi_unprepare_from_transfer(qdev->bootlog_ch);
+	destroy_workqueue(qdev->bootlog_wq);
+	qdev->bootlog_ch = NULL;
+}
+
+static void qaic_bootlog_mhi_ul_xfer_cb(struct mhi_device *mhi_dev, struct mhi_result *mhi_result)
+{
+}
+
+static void qaic_bootlog_mhi_dl_xfer_cb(struct mhi_device *mhi_dev, struct mhi_result *mhi_result)
+{
+	struct qaic_device *qdev = dev_get_drvdata(&mhi_dev->dev);
+	struct bootlog_msg *msg = mhi_result->buf_addr;
+
+	if (mhi_result->transaction_status) {
+		devm_kfree(&qdev->pdev->dev, msg);
+		return;
+	}
+
+	/* Force a null at the end of the transferred string */
+	msg->str[mhi_result->bytes_xferd - 1] = 0;
+
+	queue_work(qdev->bootlog_wq, &msg->work);
+}
+
+static const struct mhi_device_id qaic_bootlog_mhi_match_table[] = {
+	{ .chan = "QAIC_LOGGING", },
+	{},
+};
+
+static struct mhi_driver qaic_bootlog_mhi_driver = {
+	.id_table = qaic_bootlog_mhi_match_table,
+	.remove = qaic_bootlog_mhi_remove,
+	.probe = qaic_bootlog_mhi_probe,
+	.ul_xfer_cb = qaic_bootlog_mhi_ul_xfer_cb,
+	.dl_xfer_cb = qaic_bootlog_mhi_dl_xfer_cb,
+	.driver = {
+		.name = "qaic_bootlog",
+	},
+};
+
+int qaic_bootlog_register(void)
+{
+	return mhi_driver_register(&qaic_bootlog_mhi_driver);
+}
+
+void qaic_bootlog_unregister(void)
+{
+	mhi_driver_unregister(&qaic_bootlog_mhi_driver);
+}
diff --git a/drivers/accel/qaic/qaic_debugfs.h b/drivers/accel/qaic/qaic_debugfs.h
new file mode 100644
index 000000000000..05e74f84cf9f
--- /dev/null
+++ b/drivers/accel/qaic/qaic_debugfs.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Copyright (c) 2020, The Linux Foundation. All rights reserved. */
+/* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */
+
+#ifndef __QAIC_DEBUGFS_H__
+#define __QAIC_DEBUGFS_H__
+
+#include <drm/drm_file.h>
+
+#ifdef CONFIG_DEBUG_FS
+int qaic_bootlog_register(void);
+void qaic_bootlog_unregister(void);
+void qaic_debugfs_init(struct qaic_drm_device *qddev);
+#else
+static inline int qaic_bootlog_register(void) { return 0; }
+static inline void qaic_bootlog_unregister(void) {}
+static inline void qaic_debugfs_init(struct qaic_drm_device *qddev) {}
+#endif /* CONFIG_DEBUG_FS */
+#endif /* __QAIC_DEBUGFS_H__ */
diff --git a/drivers/accel/qaic/qaic_drv.c b/drivers/accel/qaic/qaic_drv.c
new file mode 100644
index 000000000000..4c70bd949d53
--- /dev/null
+++ b/drivers/accel/qaic/qaic_drv.c
@@ -0,0 +1,860 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. */
+/* Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. */
+
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/idr.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/kobject.h>
+#include <linux/kref.h>
+#include <linux/mhi.h>
+#include <linux/module.h>
+#include <linux/msi.h>
+#include <linux/mutex.h>
+#include <linux/pci.h>
+#include <linux/spinlock.h>
+#include <linux/workqueue.h>
+#include <linux/wait.h>
+#include <drm/drm_accel.h>
+#include <drm/drm_drv.h>
+#include <drm/drm_file.h>
+#include <drm/drm_gem.h>
+#include <drm/drm_ioctl.h>
+#include <drm/drm_managed.h>
+#include <uapi/drm/qaic_accel.h>
+
+#include "mhi_controller.h"
+#include "qaic.h"
+#include "qaic_debugfs.h"
+#include "qaic_ras.h"
+#include "qaic_ssr.h"
+#include "qaic_timesync.h"
+#include "sahara.h"
+
+MODULE_IMPORT_NS("DMA_BUF");
+
+#define PCI_DEVICE_ID_QCOM_AIC080	0xa080
+#define PCI_DEVICE_ID_QCOM_AIC100	0xa100
+#define PCI_DEVICE_ID_QCOM_AIC200	0xa110
+#define QAIC_NAME			"qaic"
+#define QAIC_DESC			"Qualcomm Cloud AI Accelerators"
+#define CNTL_MAJOR			5
+#define CNTL_MINOR			0
+
+struct qaic_device_config {
+	/* Indicates the AIC family the device belongs to */
+	int family;
+	/* A bitmask representing the available BARs */
+	int bar_mask;
+	/* An index value used to identify the MHI controller BAR */
+	unsigned int mhi_bar_idx;
+	/* An index value used to identify the DBCs BAR */
+	unsigned int dbc_bar_idx;
+};
+
+static const struct qaic_device_config aic080_config = {
+	.family = FAMILY_AIC100,
+	.bar_mask = BIT(0) | BIT(2) | BIT(4),
+	.mhi_bar_idx = 0,
+	.dbc_bar_idx = 2,
+};
+
+static const struct qaic_device_config aic100_config = {
+	.family = FAMILY_AIC100,
+	.bar_mask = BIT(0) | BIT(2) | BIT(4),
+	.mhi_bar_idx = 0,
+	.dbc_bar_idx = 2,
+};
+
+static const struct qaic_device_config aic200_config = {
+	.family = FAMILY_AIC200,
+	.bar_mask = BIT(0) | BIT(1) | BIT(2) | BIT(4),
+	.mhi_bar_idx = 1,
+	.dbc_bar_idx = 2,
+};
+
+bool datapath_polling;
+module_param(datapath_polling, bool, 0400);
+MODULE_PARM_DESC(datapath_polling, "Operate the datapath in polling mode");
+static bool link_up;
+static DEFINE_IDA(qaic_usrs);
+
+static void qaicm_wq_release(struct drm_device *dev, void *res)
+{
+	struct workqueue_struct *wq = res;
+
+	destroy_workqueue(wq);
+}
+
+static struct workqueue_struct *qaicm_wq_init(struct drm_device *dev, const char *name)
+{
+	struct workqueue_struct *wq;
+	int ret;
+
+	wq = alloc_workqueue("%s", WQ_UNBOUND, 0, name);
+	if (!wq)
+		return ERR_PTR(-ENOMEM);
+	ret = drmm_add_action_or_reset(dev, qaicm_wq_release, wq);
+	if (ret)
+		return ERR_PTR(ret);
+
+	return wq;
+}
+
+static void qaicm_srcu_release(struct drm_device *dev, void *res)
+{
+	struct srcu_struct *lock = res;
+
+	cleanup_srcu_struct(lock);
+}
+
+static int qaicm_srcu_init(struct drm_device *dev, struct srcu_struct *lock)
+{
+	int ret;
+
+	ret = init_srcu_struct(lock);
+	if (ret)
+		return ret;
+
+	return drmm_add_action_or_reset(dev, qaicm_srcu_release, lock);
+}
+
+static void qaicm_pci_release(struct drm_device *dev, void *res)
+{
+	struct qaic_device *qdev = to_qaic_device(dev);
+
+	pci_set_drvdata(qdev->pdev, NULL);
+}
+
+static void free_usr(struct kref *kref)
+{
+	struct qaic_user *usr = container_of(kref, struct qaic_user, ref_count);
+
+	cleanup_srcu_struct(&usr->qddev_lock);
+	ida_free(&qaic_usrs, usr->handle);
+	kfree(usr);
+}
+
+static int qaic_open(struct drm_device *dev, struct drm_file *file)
+{
+	struct qaic_drm_device *qddev = to_qaic_drm_device(dev);
+	struct qaic_device *qdev = qddev->qdev;
+	struct qaic_user *usr;
+	int rcu_id;
+	int ret;
+
+	rcu_id = srcu_read_lock(&qdev->dev_lock);
+	if (qdev->dev_state != QAIC_ONLINE) {
+		ret = -ENODEV;
+		goto dev_unlock;
+	}
+
+	usr = kmalloc(sizeof(*usr), GFP_KERNEL);
+	if (!usr) {
+		ret = -ENOMEM;
+		goto dev_unlock;
+	}
+
+	usr->handle = ida_alloc(&qaic_usrs, GFP_KERNEL);
+	if (usr->handle < 0) {
+		ret = usr->handle;
+		goto free_usr;
+	}
+	usr->qddev = qddev;
+	atomic_set(&usr->chunk_id, 0);
+	init_srcu_struct(&usr->qddev_lock);
+	kref_init(&usr->ref_count);
+
+	ret = mutex_lock_interruptible(&qddev->users_mutex);
+	if (ret)
+		goto cleanup_usr;
+
+	list_add(&usr->node, &qddev->users);
+	mutex_unlock(&qddev->users_mutex);
+
+	file->driver_priv = usr;
+
+	srcu_read_unlock(&qdev->dev_lock, rcu_id);
+	return 0;
+
+cleanup_usr:
+	cleanup_srcu_struct(&usr->qddev_lock);
+	ida_free(&qaic_usrs, usr->handle);
+free_usr:
+	kfree(usr);
+dev_unlock:
+	srcu_read_unlock(&qdev->dev_lock, rcu_id);
+	return ret;
+}
+
+static void qaic_postclose(struct drm_device *dev, struct drm_file *file)
+{
+	struct qaic_user *usr = file->driver_priv;
+	struct qaic_drm_device *qddev;
+	struct qaic_device *qdev;
+	int qdev_rcu_id;
+	int usr_rcu_id;
+	int i;
+
+	qddev = usr->qddev;
+	usr_rcu_id = srcu_read_lock(&usr->qddev_lock);
+	if (qddev) {
+		qdev = qddev->qdev;
+		qdev_rcu_id = srcu_read_lock(&qdev->dev_lock);
+		if (qdev->dev_state == QAIC_ONLINE) {
+			qaic_release_usr(qdev, usr);
+			for (i = 0; i < qdev->num_dbc; ++i)
+				if (qdev->dbc[i].usr && qdev->dbc[i].usr->handle == usr->handle)
+					release_dbc(qdev, i);
+		}
+		srcu_read_unlock(&qdev->dev_lock, qdev_rcu_id);
+
+		mutex_lock(&qddev->users_mutex);
+		if (!list_empty(&usr->node))
+			list_del_init(&usr->node);
+		mutex_unlock(&qddev->users_mutex);
+	}
+
+	srcu_read_unlock(&usr->qddev_lock, usr_rcu_id);
+	kref_put(&usr->ref_count, free_usr);
+
+	file->driver_priv = NULL;
+}
+
+DEFINE_DRM_ACCEL_FOPS(qaic_accel_fops);
+
+static const struct drm_ioctl_desc qaic_drm_ioctls[] = {
+	DRM_IOCTL_DEF_DRV(QAIC_MANAGE, qaic_manage_ioctl, 0),
+	DRM_IOCTL_DEF_DRV(QAIC_CREATE_BO, qaic_create_bo_ioctl, 0),
+	DRM_IOCTL_DEF_DRV(QAIC_MMAP_BO, qaic_mmap_bo_ioctl, 0),
+	DRM_IOCTL_DEF_DRV(QAIC_ATTACH_SLICE_BO, qaic_attach_slice_bo_ioctl, 0),
+	DRM_IOCTL_DEF_DRV(QAIC_EXECUTE_BO, qaic_execute_bo_ioctl, 0),
+	DRM_IOCTL_DEF_DRV(QAIC_PARTIAL_EXECUTE_BO, qaic_partial_execute_bo_ioctl, 0),
+	DRM_IOCTL_DEF_DRV(QAIC_WAIT_BO, qaic_wait_bo_ioctl, 0),
+	DRM_IOCTL_DEF_DRV(QAIC_PERF_STATS_BO, qaic_perf_stats_bo_ioctl, 0),
+	DRM_IOCTL_DEF_DRV(QAIC_DETACH_SLICE_BO, qaic_detach_slice_bo_ioctl, 0),
+};
+
+static const struct drm_driver qaic_accel_driver = {
+	.driver_features	= DRIVER_GEM | DRIVER_COMPUTE_ACCEL,
+
+	.name			= QAIC_NAME,
+	.desc			= QAIC_DESC,
+
+	.fops			= &qaic_accel_fops,
+	.open			= qaic_open,
+	.postclose		= qaic_postclose,
+
+	.ioctls			= qaic_drm_ioctls,
+	.num_ioctls		= ARRAY_SIZE(qaic_drm_ioctls),
+	.gem_prime_import	= qaic_gem_prime_import,
+};
+
+static int qaic_create_drm_device(struct qaic_device *qdev, s32 partition_id)
+{
+	struct qaic_drm_device *qddev = qdev->qddev;
+	struct drm_device *drm = to_drm(qddev);
+	int ret;
+
+	/* Hold off implementing partitions until the uapi is determined */
+	if (partition_id != QAIC_NO_PARTITION)
+		return -EINVAL;
+
+	qddev->partition_id = partition_id;
+
+	ret = drm_dev_register(drm, 0);
+	if (ret) {
+		pci_dbg(qdev->pdev, "drm_dev_register failed %d\n", ret);
+		return ret;
+	}
+
+	ret = qaic_sysfs_init(qddev);
+	if (ret) {
+		drm_dev_unregister(drm);
+		pci_dbg(qdev->pdev, "qaic_sysfs_init failed %d\n", ret);
+		return ret;
+	}
+
+	qaic_debugfs_init(qddev);
+
+	return ret;
+}
+
+static void qaic_destroy_drm_device(struct qaic_device *qdev, s32 partition_id)
+{
+	struct qaic_drm_device *qddev = qdev->qddev;
+	struct drm_device *drm = to_drm(qddev);
+	struct qaic_user *usr;
+
+	qaic_sysfs_remove(qddev);
+	drm_dev_unregister(drm);
+	qddev->partition_id = 0;
+	/*
+	 * Existing users get unresolvable errors till they close FDs.
+	 * Need to sync carefully with users calling close(). The
+	 * list of users can be modified elsewhere when the lock isn't
+	 * held here, but the sync'ing the srcu with the mutex held
+	 * could deadlock. Grab the mutex so that the list will be
+	 * unmodified. The user we get will exist as long as the
+	 * lock is held. Signal that the qcdev is going away, and
+	 * grab a reference to the user so they don't go away for
+	 * synchronize_srcu(). Then release the mutex to avoid
+	 * deadlock and make sure the user has observed the signal.
+	 * With the lock released, we cannot maintain any state of the
+	 * user list.
+	 */
+	mutex_lock(&qddev->users_mutex);
+	while (!list_empty(&qddev->users)) {
+		usr = list_first_entry(&qddev->users, struct qaic_user, node);
+		list_del_init(&usr->node);
+		kref_get(&usr->ref_count);
+		usr->qddev = NULL;
+		mutex_unlock(&qddev->users_mutex);
+		synchronize_srcu(&usr->qddev_lock);
+		kref_put(&usr->ref_count, free_usr);
+		mutex_lock(&qddev->users_mutex);
+	}
+	mutex_unlock(&qddev->users_mutex);
+}
+
+static int qaic_mhi_probe(struct mhi_device *mhi_dev, const struct mhi_device_id *id)
+{
+	u16 major = -1, minor = -1;
+	struct qaic_device *qdev;
+	int ret;
+
+	/*
+	 * Invoking this function indicates that the control channel to the
+	 * device is available. We use that as a signal to indicate that
+	 * the device side firmware has booted. The device side firmware
+	 * manages the device resources, so we need to communicate with it
+	 * via the control channel in order to utilize the device. Therefore
+	 * we wait until this signal to create the drm dev that userspace will
+	 * use to control the device, because without the device side firmware,
+	 * userspace can't do anything useful.
+	 */
+
+	qdev = pci_get_drvdata(to_pci_dev(mhi_dev->mhi_cntrl->cntrl_dev));
+
+	dev_set_drvdata(&mhi_dev->dev, qdev);
+	qdev->cntl_ch = mhi_dev;
+
+	ret = qaic_control_open(qdev);
+	if (ret) {
+		pci_dbg(qdev->pdev, "%s: control_open failed %d\n", __func__, ret);
+		return ret;
+	}
+
+	qdev->dev_state = QAIC_BOOT;
+	ret = get_cntl_version(qdev, NULL, &major, &minor);
+	if (ret || major != CNTL_MAJOR || minor > CNTL_MINOR) {
+		pci_err(qdev->pdev, "%s: Control protocol version (%d.%d) not supported. Supported version is (%d.%d). Ret: %d\n",
+			__func__, major, minor, CNTL_MAJOR, CNTL_MINOR, ret);
+		ret = -EINVAL;
+		goto close_control;
+	}
+	qdev->dev_state = QAIC_ONLINE;
+	kobject_uevent(&(to_accel_kdev(qdev->qddev))->kobj, KOBJ_ONLINE);
+
+	return ret;
+
+close_control:
+	qaic_control_close(qdev);
+	return ret;
+}
+
+static void qaic_mhi_remove(struct mhi_device *mhi_dev)
+{
+/* This is redundant since we have already observed the device crash */
+}
+
+static void qaic_notify_reset(struct qaic_device *qdev)
+{
+	int i;
+
+	kobject_uevent(&(to_accel_kdev(qdev->qddev))->kobj, KOBJ_OFFLINE);
+	qdev->dev_state = QAIC_OFFLINE;
+	/* wake up any waiters to avoid waiting for timeouts at sync */
+	wake_all_cntl(qdev);
+	for (i = 0; i < qdev->num_dbc; ++i)
+		wakeup_dbc(qdev, i);
+	synchronize_srcu(&qdev->dev_lock);
+}
+
+void qaic_dev_reset_clean_local_state(struct qaic_device *qdev)
+{
+	int i;
+
+	qaic_notify_reset(qdev);
+
+	/* start tearing things down */
+	qaic_clean_up_ssr(qdev);
+	for (i = 0; i < qdev->num_dbc; ++i)
+		release_dbc(qdev, i);
+}
+
+static struct qaic_device *create_qdev(struct pci_dev *pdev,
+				       const struct qaic_device_config *config)
+{
+	struct device *dev = &pdev->dev;
+	struct qaic_drm_device *qddev;
+	struct qaic_device *qdev;
+	struct drm_device *drm;
+	int i, ret;
+
+	qdev = devm_kzalloc(dev, sizeof(*qdev), GFP_KERNEL);
+	if (!qdev)
+		return NULL;
+
+	qdev->dev_state = QAIC_OFFLINE;
+	qdev->num_dbc = 16;
+	qdev->dbc = devm_kcalloc(dev, qdev->num_dbc, sizeof(*qdev->dbc), GFP_KERNEL);
+	if (!qdev->dbc)
+		return NULL;
+
+	qddev = devm_drm_dev_alloc(&pdev->dev, &qaic_accel_driver, struct qaic_drm_device, drm);
+	if (IS_ERR(qddev))
+		return NULL;
+
+	drm = to_drm(qddev);
+	pci_set_drvdata(pdev, qdev);
+
+	ret = drmm_mutex_init(drm, &qddev->users_mutex);
+	if (ret)
+		return NULL;
+	ret = drmm_add_action_or_reset(drm, qaicm_pci_release, NULL);
+	if (ret)
+		return NULL;
+	ret = drmm_mutex_init(drm, &qdev->cntl_mutex);
+	if (ret)
+		return NULL;
+	ret = drmm_mutex_init(drm, &qdev->bootlog_mutex);
+	if (ret)
+		return NULL;
+
+	qdev->cntl_wq = qaicm_wq_init(drm, "qaic_cntl");
+	if (IS_ERR(qdev->cntl_wq))
+		return NULL;
+	qdev->qts_wq = qaicm_wq_init(drm, "qaic_ts");
+	if (IS_ERR(qdev->qts_wq))
+		return NULL;
+	qdev->ssr_wq = qaicm_wq_init(drm, "qaic_ssr");
+	if (IS_ERR(qdev->ssr_wq))
+		return NULL;
+
+	ret = qaicm_srcu_init(drm, &qdev->dev_lock);
+	if (ret)
+		return NULL;
+
+	ret = qaic_ssr_init(qdev, drm);
+	if (ret)
+		pci_info(pdev, "QAIC SSR crashdump collection not supported.\n");
+
+	qdev->qddev = qddev;
+	qdev->pdev = pdev;
+	qddev->qdev = qdev;
+
+	INIT_LIST_HEAD(&qdev->cntl_xfer_list);
+	INIT_LIST_HEAD(&qdev->bootlog);
+	INIT_LIST_HEAD(&qddev->users);
+
+	for (i = 0; i < qdev->num_dbc; ++i) {
+		spin_lock_init(&qdev->dbc[i].xfer_lock);
+		qdev->dbc[i].qdev = qdev;
+		qdev->dbc[i].id = i;
+		INIT_LIST_HEAD(&qdev->dbc[i].xfer_list);
+		ret = qaicm_srcu_init(drm, &qdev->dbc[i].ch_lock);
+		if (ret)
+			return NULL;
+		init_waitqueue_head(&qdev->dbc[i].dbc_release);
+		INIT_LIST_HEAD(&qdev->dbc[i].bo_lists);
+		ret = drmm_mutex_init(drm, &qdev->dbc[i].req_lock);
+		if (ret)
+			return NULL;
+	}
+
+	return qdev;
+}
+
+static int init_pci(struct qaic_device *qdev, struct pci_dev *pdev,
+		    const struct qaic_device_config *config)
+{
+	int bars;
+	int ret;
+
+	bars = pci_select_bars(pdev, IORESOURCE_MEM) & 0x3f;
+
+	/* make sure the device has the expected BARs */
+	if (bars != config->bar_mask) {
+		pci_dbg(pdev, "%s: expected BARs %#x not found in device. Found %#x\n",
+			__func__, config->bar_mask, bars);
+		return -EINVAL;
+	}
+
+	ret = pcim_enable_device(pdev);
+	if (ret)
+		return ret;
+
+	ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
+	if (ret)
+		return ret;
+	dma_set_max_seg_size(&pdev->dev, UINT_MAX);
+
+	qdev->bar_mhi = devm_ioremap_resource(&pdev->dev, &pdev->resource[config->mhi_bar_idx]);
+	if (IS_ERR(qdev->bar_mhi))
+		return PTR_ERR(qdev->bar_mhi);
+
+	qdev->bar_dbc = devm_ioremap_resource(&pdev->dev, &pdev->resource[config->dbc_bar_idx]);
+	if (IS_ERR(qdev->bar_dbc))
+		return PTR_ERR(qdev->bar_dbc);
+
+	/* Managed release since we use pcim_enable_device above */
+	pci_set_master(pdev);
+
+	return 0;
+}
+
+static int init_msi(struct qaic_device *qdev, struct pci_dev *pdev)
+{
+	int irq_count = qdev->num_dbc + 1;
+	int mhi_irq;
+	int ret;
+	int i;
+
+	/* Managed release since we use pcim_enable_device */
+	ret = pci_alloc_irq_vectors(pdev, irq_count, irq_count, PCI_IRQ_MSI | PCI_IRQ_MSIX);
+	if (ret == -ENOSPC) {
+		ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI | PCI_IRQ_MSIX);
+		if (ret < 0)
+			return ret;
+
+		/*
+		 * Operate in one MSI mode. All interrupts will be directed to
+		 * MSI0; every interrupt will wake up all the interrupt handlers
+		 * (MHI and DBC[0-15]). Since the interrupt is now shared, it is
+		 * not disabled during DBC threaded handler, but only one thread
+		 * will be allowed to run per DBC, so while it can be
+		 * interrupted, it shouldn't race with itself.
+		 */
+		qdev->single_msi = true;
+		pci_info(pdev, "Allocating %d MSIs failed, operating in 1 MSI mode. Performance may be impacted.\n",
+			 irq_count);
+	} else if (ret < 0) {
+		return ret;
+	}
+
+	mhi_irq = pci_irq_vector(pdev, 0);
+	if (mhi_irq < 0)
+		return mhi_irq;
+
+	for (i = 0; i < qdev->num_dbc; ++i) {
+		ret = devm_request_threaded_irq(&pdev->dev,
+						pci_irq_vector(pdev, qdev->single_msi ? 0 : i + 1),
+						dbc_irq_handler, dbc_irq_threaded_fn, IRQF_SHARED,
+						"qaic_dbc", &qdev->dbc[i]);
+		if (ret)
+			return ret;
+
+		if (datapath_polling) {
+			qdev->dbc[i].irq = pci_irq_vector(pdev, qdev->single_msi ? 0 : i + 1);
+			if (!qdev->single_msi)
+				disable_irq_nosync(qdev->dbc[i].irq);
+			INIT_WORK(&qdev->dbc[i].poll_work, qaic_irq_polling_work);
+		}
+	}
+
+	return mhi_irq;
+}
+
+static int qaic_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+{
+	struct qaic_device_config *config = (struct qaic_device_config *)id->driver_data;
+	struct qaic_device *qdev;
+	int mhi_irq;
+	int ret;
+	int i;
+
+	qdev = create_qdev(pdev, config);
+	if (!qdev)
+		return -ENOMEM;
+
+	ret = init_pci(qdev, pdev, config);
+	if (ret)
+		return ret;
+
+	for (i = 0; i < qdev->num_dbc; ++i)
+		qdev->dbc[i].dbc_base = qdev->bar_dbc + QAIC_DBC_OFF(i);
+
+	mhi_irq = init_msi(qdev, pdev);
+	if (mhi_irq < 0)
+		return mhi_irq;
+
+	ret = qaic_create_drm_device(qdev, QAIC_NO_PARTITION);
+	if (ret)
+		return ret;
+
+	qdev->mhi_cntrl = qaic_mhi_register_controller(pdev, qdev->bar_mhi, mhi_irq,
+						       qdev->single_msi, config->family);
+	if (IS_ERR(qdev->mhi_cntrl)) {
+		ret = PTR_ERR(qdev->mhi_cntrl);
+		qaic_destroy_drm_device(qdev, QAIC_NO_PARTITION);
+		return ret;
+	}
+
+	return 0;
+}
+
+static void qaic_pci_remove(struct pci_dev *pdev)
+{
+	struct qaic_device *qdev = pci_get_drvdata(pdev);
+
+	if (!qdev)
+		return;
+
+	qaic_dev_reset_clean_local_state(qdev);
+	qaic_mhi_free_controller(qdev->mhi_cntrl, link_up);
+	qaic_destroy_drm_device(qdev, QAIC_NO_PARTITION);
+}
+
+static void qaic_pci_shutdown(struct pci_dev *pdev)
+{
+	/* see qaic_exit for what link_up is doing */
+	link_up = true;
+	qaic_pci_remove(pdev);
+}
+
+static pci_ers_result_t qaic_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t error)
+{
+	return PCI_ERS_RESULT_NEED_RESET;
+}
+
+static void qaic_pci_reset_prepare(struct pci_dev *pdev)
+{
+	struct qaic_device *qdev = pci_get_drvdata(pdev);
+
+	qaic_notify_reset(qdev);
+	qaic_mhi_start_reset(qdev->mhi_cntrl);
+	qaic_dev_reset_clean_local_state(qdev);
+}
+
+static void qaic_pci_reset_done(struct pci_dev *pdev)
+{
+	struct qaic_device *qdev = pci_get_drvdata(pdev);
+
+	qaic_mhi_reset_done(qdev->mhi_cntrl);
+}
+
+static const struct mhi_device_id qaic_mhi_match_table[] = {
+	{ .chan = "QAIC_CONTROL", },
+	{},
+};
+
+static struct mhi_driver qaic_mhi_driver = {
+	.id_table = qaic_mhi_match_table,
+	.remove = qaic_mhi_remove,
+	.probe = qaic_mhi_probe,
+	.ul_xfer_cb = qaic_mhi_ul_xfer_cb,
+	.dl_xfer_cb = qaic_mhi_dl_xfer_cb,
+	.driver = {
+		.name = "qaic_mhi",
+	},
+};
+
+static const struct pci_device_id qaic_ids[] = {
+	{ PCI_DEVICE_DATA(QCOM, AIC080, (kernel_ulong_t)&aic080_config), },
+	{ PCI_DEVICE_DATA(QCOM, AIC100, (kernel_ulong_t)&aic100_config), },
+	{ PCI_DEVICE_DATA(QCOM, AIC200, (kernel_ulong_t)&aic200_config), },
+	{ }
+};
+MODULE_DEVICE_TABLE(pci, qaic_ids);
+
+static const struct pci_error_handlers qaic_pci_err_handler = {
+	.error_detected = qaic_pci_error_detected,
+	.reset_prepare = qaic_pci_reset_prepare,
+	.reset_done = qaic_pci_reset_done,
+};
+
+static bool qaic_is_under_reset(struct qaic_device *qdev)
+{
+	int rcu_id;
+	bool ret;
+
+	rcu_id = srcu_read_lock(&qdev->dev_lock);
+	ret = qdev->dev_state != QAIC_ONLINE;
+	srcu_read_unlock(&qdev->dev_lock, rcu_id);
+	return ret;
+}
+
+static bool qaic_data_path_busy(struct qaic_device *qdev)
+{
+	bool ret = false;
+	int dev_rcu_id;
+	int i;
+
+	dev_rcu_id = srcu_read_lock(&qdev->dev_lock);
+	if (qdev->dev_state != QAIC_ONLINE) {
+		srcu_read_unlock(&qdev->dev_lock, dev_rcu_id);
+		return false;
+	}
+	for (i = 0; i < qdev->num_dbc; i++) {
+		struct dma_bridge_chan *dbc = &qdev->dbc[i];
+		unsigned long flags;
+		int ch_rcu_id;
+
+		ch_rcu_id = srcu_read_lock(&dbc->ch_lock);
+		if (!dbc->usr || !dbc->in_use) {
+			srcu_read_unlock(&dbc->ch_lock, ch_rcu_id);
+			continue;
+		}
+		spin_lock_irqsave(&dbc->xfer_lock, flags);
+		ret = !list_empty(&dbc->xfer_list);
+		spin_unlock_irqrestore(&dbc->xfer_lock, flags);
+		srcu_read_unlock(&dbc->ch_lock, ch_rcu_id);
+		if (ret)
+			break;
+	}
+	srcu_read_unlock(&qdev->dev_lock, dev_rcu_id);
+	return ret;
+}
+
+static int qaic_pm_suspend(struct device *dev)
+{
+	struct qaic_device *qdev = pci_get_drvdata(to_pci_dev(dev));
+
+	dev_dbg(dev, "Suspending..\n");
+	if (qaic_data_path_busy(qdev)) {
+		dev_dbg(dev, "Device's datapath is busy. Aborting suspend..\n");
+		return -EBUSY;
+	}
+	if (qaic_is_under_reset(qdev)) {
+		dev_dbg(dev, "Device is under reset. Aborting suspend..\n");
+		return -EBUSY;
+	}
+	qaic_mqts_ch_stop_timer(qdev->mqts_ch);
+	qaic_pci_reset_prepare(qdev->pdev);
+	pci_save_state(qdev->pdev);
+	pci_disable_device(qdev->pdev);
+	pci_set_power_state(qdev->pdev, PCI_D3hot);
+	return 0;
+}
+
+static int qaic_pm_resume(struct device *dev)
+{
+	struct qaic_device *qdev = pci_get_drvdata(to_pci_dev(dev));
+	int ret;
+
+	dev_dbg(dev, "Resuming..\n");
+	pci_set_power_state(qdev->pdev, PCI_D0);
+	pci_restore_state(qdev->pdev);
+	ret = pci_enable_device(qdev->pdev);
+	if (ret) {
+		dev_err(dev, "pci_enable_device failed on resume %d\n", ret);
+		return ret;
+	}
+	pci_set_master(qdev->pdev);
+	qaic_pci_reset_done(qdev->pdev);
+	return 0;
+}
+
+static const struct dev_pm_ops qaic_pm_ops = {
+	SYSTEM_SLEEP_PM_OPS(qaic_pm_suspend, qaic_pm_resume)
+};
+
+static struct pci_driver qaic_pci_driver = {
+	.name = QAIC_NAME,
+	.id_table = qaic_ids,
+	.probe = qaic_pci_probe,
+	.remove = qaic_pci_remove,
+	.shutdown = qaic_pci_shutdown,
+	.err_handler = &qaic_pci_err_handler,
+	.driver = {
+		.pm = pm_sleep_ptr(&qaic_pm_ops),
+	},
+};
+
+static int __init qaic_init(void)
+{
+	int ret;
+
+	ret = pci_register_driver(&qaic_pci_driver);
+	if (ret) {
+		pr_debug("qaic: pci_register_driver failed %d\n", ret);
+		return ret;
+	}
+
+	ret = mhi_driver_register(&qaic_mhi_driver);
+	if (ret) {
+		pr_debug("qaic: mhi_driver_register failed %d\n", ret);
+		goto free_pci;
+	}
+
+	ret = sahara_register();
+	if (ret) {
+		pr_debug("qaic: sahara_register failed %d\n", ret);
+		goto free_mhi;
+	}
+
+	ret = qaic_timesync_init();
+	if (ret)
+		pr_debug("qaic: qaic_timesync_init failed %d\n", ret);
+
+	ret = qaic_bootlog_register();
+	if (ret)
+		pr_debug("qaic: qaic_bootlog_register failed %d\n", ret);
+
+	ret = qaic_ras_register();
+	if (ret)
+		pr_debug("qaic: qaic_ras_register failed %d\n", ret);
+	ret = qaic_ssr_register();
+	if (ret) {
+		pr_debug("qaic: qaic_ssr_register failed %d\n", ret);
+		goto free_bootlog;
+	}
+
+	return 0;
+
+free_bootlog:
+	qaic_bootlog_unregister();
+free_mhi:
+	mhi_driver_unregister(&qaic_mhi_driver);
+free_pci:
+	pci_unregister_driver(&qaic_pci_driver);
+	return ret;
+}
+
+static void __exit qaic_exit(void)
+{
+	/*
+	 * We assume that qaic_pci_remove() is called due to a hotplug event
+	 * which would mean that the link is down, and thus
+	 * qaic_mhi_free_controller() should not try to access the device during
+	 * cleanup.
+	 * We call pci_unregister_driver() below, which also triggers
+	 * qaic_pci_remove(), but since this is module exit, we expect the link
+	 * to the device to be up, in which case qaic_mhi_free_controller()
+	 * should try to access the device during cleanup to put the device in
+	 * a sane state.
+	 * For that reason, we set link_up here to let qaic_mhi_free_controller
+	 * know the expected link state. Since the module is going to be
+	 * removed at the end of this, we don't need to worry about
+	 * reinitializing the link_up state after the cleanup is done.
+	 */
+	link_up = true;
+	qaic_ssr_unregister();
+	qaic_ras_unregister();
+	qaic_bootlog_unregister();
+	qaic_timesync_deinit();
+	sahara_unregister();
+	mhi_driver_unregister(&qaic_mhi_driver);
+	pci_unregister_driver(&qaic_pci_driver);
+}
+
+module_init(qaic_init);
+module_exit(qaic_exit);
+
+MODULE_AUTHOR(QAIC_DESC " Kernel Driver Team");
+MODULE_DESCRIPTION(QAIC_DESC " Accel Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/accel/qaic/qaic_ras.c b/drivers/accel/qaic/qaic_ras.c
new file mode 100644
index 000000000000..f1d52a710136
--- /dev/null
+++ b/drivers/accel/qaic/qaic_ras.c
@@ -0,0 +1,642 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. */
+/* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */
+/* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */
+
+#include <asm/byteorder.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/mhi.h>
+
+#include "qaic.h"
+#include "qaic_ras.h"
+
+#define MAGIC		0x55AA
+#define VERSION		0x2
+#define HDR_SZ		12
+#define NUM_TEMP_LVL	3
+#define POWER_BREAK	BIT(0)
+
+enum msg_type {
+	MSG_PUSH, /* async push from device */
+	MSG_REQ,  /* sync request to device */
+	MSG_RESP, /* sync response from device */
+};
+
+enum err_type {
+	CE,	/* correctable error */
+	UE,	/* uncorrectable error */
+	UE_NF,	/* uncorrectable error that is non-fatal, expect a disruption */
+	ERR_TYPE_MAX,
+};
+
+static const char * const err_type_str[] = {
+	[CE]    = "Correctable",
+	[UE]    = "Uncorrectable",
+	[UE_NF] = "Uncorrectable Non-Fatal",
+};
+
+static const char * const err_class_str[] = {
+	[CE]    = "Warning",
+	[UE]    = "Fatal",
+	[UE_NF] = "Warning",
+};
+
+enum err_source {
+	SOC_MEM,
+	PCIE,
+	DDR,
+	SYS_BUS1,
+	SYS_BUS2,
+	NSP_MEM,
+	TSENS,
+};
+
+static const char * const err_src_str[TSENS + 1] = {
+	[SOC_MEM]	= "SoC Memory",
+	[PCIE]		= "PCIE",
+	[DDR]		= "DDR",
+	[SYS_BUS1]	= "System Bus source 1",
+	[SYS_BUS2]	= "System Bus source 2",
+	[NSP_MEM]	= "NSP Memory",
+	[TSENS]		= "Temperature Sensors",
+};
+
+struct ras_data {
+	/* header start */
+	/* Magic number to validate the message */
+	u16 magic;
+	/* RAS version number */
+	u16 ver;
+	u32 seq_num;
+	/* RAS message type */
+	u8  type;
+	u8  id;
+	/* Size of RAS message without the header in byte */
+	u16 len;
+	/* header end */
+	s32 result;
+	/*
+	 * Error source
+	 * 0 : SoC Memory
+	 * 1 : PCIE
+	 * 2 : DDR
+	 * 3 : System Bus source 1
+	 * 4 : System Bus source 2
+	 * 5 : NSP Memory
+	 * 6 : Temperature Sensors
+	 */
+	u32 source;
+	/*
+	 * Stores the error type, there are three types of error in RAS
+	 * 0 : correctable error (CE)
+	 * 1 : uncorrectable error (UE)
+	 * 2 : uncorrectable error that is non-fatal (UE_NF)
+	 */
+	u32 err_type;
+	u32 err_threshold;
+	u32 ce_count;
+	u32 ue_count;
+	u32 intr_num;
+	/* Data specific to error source */
+	u8  syndrome[64];
+} __packed;
+
+struct soc_mem_syndrome {
+	u64 error_address[8];
+} __packed;
+
+struct nsp_mem_syndrome {
+	u32 error_address[8];
+	u8 nsp_id;
+} __packed;
+
+struct ddr_syndrome {
+	u32 count;
+	u32 irq_status;
+	u32 data_31_0[2];
+	u32 data_63_32[2];
+	u32 data_95_64[2];
+	u32 data_127_96[2];
+	u32 addr_lsb;
+	u16 addr_msb;
+	u16 parity_bits;
+	u16 instance;
+	u16 err_type;
+} __packed;
+
+struct tsens_syndrome {
+	u32 threshold_type;
+	s32 temp;
+} __packed;
+
+struct sysbus1_syndrome {
+	u32 slave;
+	u32 err_type;
+	u16 addr[8];
+	u8  instance;
+} __packed;
+
+struct sysbus2_syndrome {
+	u32 lsb3;
+	u32 msb3;
+	u32 lsb2;
+	u32 msb2;
+	u32 ext_id;
+	u16 path;
+	u16 op_type;
+	u16 len;
+	u16 redirect;
+	u8  valid;
+	u8  word_error;
+	u8  non_secure;
+	u8  opc;
+	u8  error_code;
+	u8  trans_type;
+	u8  addr_space;
+	u8  instance;
+} __packed;
+
+struct pcie_syndrome {
+	/* CE info */
+	u32 bad_tlp;
+	u32 bad_dllp;
+	u32 replay_rollover;
+	u32 replay_timeout;
+	u32 rx_err;
+	u32 internal_ce_count;
+	/* UE_NF info */
+	u32 fc_timeout;
+	u32 poison_tlp;
+	u32 ecrc_err;
+	u32 unsupported_req;
+	u32 completer_abort;
+	u32 completion_timeout;
+	/* UE info */
+	u32 addr;
+	u8  index;
+	/*
+	 * Flag to indicate specific event of PCIe
+	 * BIT(0): Power break (low power)
+	 * BIT(1) to BIT(7): Reserved
+	 */
+	u8 flag;
+} __packed;
+
+static const char * const threshold_type_str[NUM_TEMP_LVL] = {
+	[0] = "lower",
+	[1] = "upper",
+	[2] = "critical",
+};
+
+static void ras_msg_to_cpu(struct ras_data *msg)
+{
+	struct sysbus1_syndrome *sysbus1_syndrome = (struct sysbus1_syndrome *)&msg->syndrome[0];
+	struct sysbus2_syndrome *sysbus2_syndrome = (struct sysbus2_syndrome *)&msg->syndrome[0];
+	struct soc_mem_syndrome *soc_syndrome = (struct soc_mem_syndrome *)&msg->syndrome[0];
+	struct nsp_mem_syndrome *nsp_syndrome = (struct nsp_mem_syndrome *)&msg->syndrome[0];
+	struct tsens_syndrome *tsens_syndrome = (struct tsens_syndrome *)&msg->syndrome[0];
+	struct pcie_syndrome *pcie_syndrome = (struct pcie_syndrome *)&msg->syndrome[0];
+	struct ddr_syndrome *ddr_syndrome = (struct ddr_syndrome *)&msg->syndrome[0];
+	int i;
+
+	le16_to_cpus(&msg->magic);
+	le16_to_cpus(&msg->ver);
+	le32_to_cpus(&msg->seq_num);
+	le16_to_cpus(&msg->len);
+	le32_to_cpus(&msg->result);
+	le32_to_cpus(&msg->source);
+	le32_to_cpus(&msg->err_type);
+	le32_to_cpus(&msg->err_threshold);
+	le32_to_cpus(&msg->ce_count);
+	le32_to_cpus(&msg->ue_count);
+	le32_to_cpus(&msg->intr_num);
+
+	switch (msg->source) {
+	case SOC_MEM:
+		for (i = 0; i < 8; i++)
+			le64_to_cpus(&soc_syndrome->error_address[i]);
+		break;
+	case PCIE:
+		le32_to_cpus(&pcie_syndrome->bad_tlp);
+		le32_to_cpus(&pcie_syndrome->bad_dllp);
+		le32_to_cpus(&pcie_syndrome->replay_rollover);
+		le32_to_cpus(&pcie_syndrome->replay_timeout);
+		le32_to_cpus(&pcie_syndrome->rx_err);
+		le32_to_cpus(&pcie_syndrome->internal_ce_count);
+		le32_to_cpus(&pcie_syndrome->fc_timeout);
+		le32_to_cpus(&pcie_syndrome->poison_tlp);
+		le32_to_cpus(&pcie_syndrome->ecrc_err);
+		le32_to_cpus(&pcie_syndrome->unsupported_req);
+		le32_to_cpus(&pcie_syndrome->completer_abort);
+		le32_to_cpus(&pcie_syndrome->completion_timeout);
+		le32_to_cpus(&pcie_syndrome->addr);
+		break;
+	case DDR:
+		le16_to_cpus(&ddr_syndrome->instance);
+		le16_to_cpus(&ddr_syndrome->err_type);
+		le32_to_cpus(&ddr_syndrome->count);
+		le32_to_cpus(&ddr_syndrome->irq_status);
+		le32_to_cpus(&ddr_syndrome->data_31_0[0]);
+		le32_to_cpus(&ddr_syndrome->data_31_0[1]);
+		le32_to_cpus(&ddr_syndrome->data_63_32[0]);
+		le32_to_cpus(&ddr_syndrome->data_63_32[1]);
+		le32_to_cpus(&ddr_syndrome->data_95_64[0]);
+		le32_to_cpus(&ddr_syndrome->data_95_64[1]);
+		le32_to_cpus(&ddr_syndrome->data_127_96[0]);
+		le32_to_cpus(&ddr_syndrome->data_127_96[1]);
+		le16_to_cpus(&ddr_syndrome->parity_bits);
+		le16_to_cpus(&ddr_syndrome->addr_msb);
+		le32_to_cpus(&ddr_syndrome->addr_lsb);
+		break;
+	case SYS_BUS1:
+		le32_to_cpus(&sysbus1_syndrome->slave);
+		le32_to_cpus(&sysbus1_syndrome->err_type);
+		for (i = 0; i < 8; i++)
+			le16_to_cpus(&sysbus1_syndrome->addr[i]);
+		break;
+	case SYS_BUS2:
+		le16_to_cpus(&sysbus2_syndrome->op_type);
+		le16_to_cpus(&sysbus2_syndrome->len);
+		le16_to_cpus(&sysbus2_syndrome->redirect);
+		le16_to_cpus(&sysbus2_syndrome->path);
+		le32_to_cpus(&sysbus2_syndrome->ext_id);
+		le32_to_cpus(&sysbus2_syndrome->lsb2);
+		le32_to_cpus(&sysbus2_syndrome->msb2);
+		le32_to_cpus(&sysbus2_syndrome->lsb3);
+		le32_to_cpus(&sysbus2_syndrome->msb3);
+		break;
+	case NSP_MEM:
+		for (i = 0; i < 8; i++)
+			le32_to_cpus(&nsp_syndrome->error_address[i]);
+		break;
+	case TSENS:
+		le32_to_cpus(&tsens_syndrome->threshold_type);
+		le32_to_cpus(&tsens_syndrome->temp);
+		break;
+	}
+}
+
+static void decode_ras_msg(struct qaic_device *qdev, struct ras_data *msg)
+{
+	struct sysbus1_syndrome *sysbus1_syndrome = (struct sysbus1_syndrome *)&msg->syndrome[0];
+	struct sysbus2_syndrome *sysbus2_syndrome = (struct sysbus2_syndrome *)&msg->syndrome[0];
+	struct soc_mem_syndrome *soc_syndrome = (struct soc_mem_syndrome *)&msg->syndrome[0];
+	struct nsp_mem_syndrome *nsp_syndrome = (struct nsp_mem_syndrome *)&msg->syndrome[0];
+	struct tsens_syndrome *tsens_syndrome = (struct tsens_syndrome *)&msg->syndrome[0];
+	struct pcie_syndrome *pcie_syndrome = (struct pcie_syndrome *)&msg->syndrome[0];
+	struct ddr_syndrome *ddr_syndrome = (struct ddr_syndrome *)&msg->syndrome[0];
+	char *class;
+	char *level;
+
+	if (msg->magic != MAGIC) {
+		pci_warn(qdev->pdev, "Dropping RAS message with invalid magic %x\n", msg->magic);
+		return;
+	}
+
+	if (!msg->ver || msg->ver > VERSION) {
+		pci_warn(qdev->pdev, "Dropping RAS message with invalid version %d\n", msg->ver);
+		return;
+	}
+
+	if (msg->type != MSG_PUSH) {
+		pci_warn(qdev->pdev, "Dropping non-PUSH RAS message\n");
+		return;
+	}
+
+	if (msg->len != sizeof(*msg) - HDR_SZ) {
+		pci_warn(qdev->pdev, "Dropping RAS message with invalid len %d\n", msg->len);
+		return;
+	}
+
+	if (msg->err_type >= ERR_TYPE_MAX) {
+		pci_warn(qdev->pdev, "Dropping RAS message with err type %d\n", msg->err_type);
+		return;
+	}
+
+	if (msg->err_type == UE)
+		level = KERN_ERR;
+	else
+		level = KERN_WARNING;
+
+	switch (msg->source) {
+	case SOC_MEM:
+		dev_printk(level, &qdev->pdev->dev, "RAS event.\nClass:%s\nDescription:%s %s %s\nError Threshold for this report %d\nSyndrome:\n    0x%llx\n    0x%llx\n    0x%llx\n    0x%llx\n    0x%llx\n    0x%llx\n    0x%llx\n    0x%llx\n",
+			   err_class_str[msg->err_type],
+			   err_type_str[msg->err_type],
+			   "error from",
+			   err_src_str[msg->source],
+			   msg->err_threshold,
+			   soc_syndrome->error_address[0],
+			   soc_syndrome->error_address[1],
+			   soc_syndrome->error_address[2],
+			   soc_syndrome->error_address[3],
+			   soc_syndrome->error_address[4],
+			   soc_syndrome->error_address[5],
+			   soc_syndrome->error_address[6],
+			   soc_syndrome->error_address[7]);
+		break;
+	case PCIE:
+		dev_printk(level, &qdev->pdev->dev, "RAS event.\nClass:%s\nDescription:%s %s %s\nError Threshold for this report %d\n",
+			   err_class_str[msg->err_type],
+			   err_type_str[msg->err_type],
+			   "error from",
+			   err_src_str[msg->source],
+			   msg->err_threshold);
+
+		switch (msg->err_type) {
+		case CE:
+			/*
+			 * Modeled after AER prints. This continues the dev_printk() from a few
+			 * lines up. We reduce duplication of code, but also avoid re-printing the
+			 * PCI device info so that the end result looks uniform to the log user.
+			 */
+			printk(KERN_WARNING pr_fmt("Syndrome:\n    Bad TLP count %d\n    Bad DLLP count %d\n    Replay Rollover count %d\n    Replay Timeout count %d\n    Recv Error count %d\n    Internal CE count %d\n"),
+			       pcie_syndrome->bad_tlp,
+			       pcie_syndrome->bad_dllp,
+			       pcie_syndrome->replay_rollover,
+			       pcie_syndrome->replay_timeout,
+			       pcie_syndrome->rx_err,
+			       pcie_syndrome->internal_ce_count);
+			if (msg->ver > 0x1)
+				pr_warn("    Power break %s\n",
+					pcie_syndrome->flag & POWER_BREAK ? "ON" : "OFF");
+			break;
+		case UE:
+			printk(KERN_ERR pr_fmt("Syndrome:\n    Index %d\n    Address 0x%x\n"),
+			       pcie_syndrome->index, pcie_syndrome->addr);
+			break;
+		case UE_NF:
+			printk(KERN_WARNING pr_fmt("Syndrome:\n    FC timeout count %d\n    Poisoned TLP count %d\n    ECRC error count %d\n    Unsupported request count %d\n    Completer abort count %d\n    Completion timeout count %d\n"),
+			       pcie_syndrome->fc_timeout,
+			       pcie_syndrome->poison_tlp,
+			       pcie_syndrome->ecrc_err,
+			       pcie_syndrome->unsupported_req,
+			       pcie_syndrome->completer_abort,
+			       pcie_syndrome->completion_timeout);
+			break;
+		default:
+			break;
+		}
+		break;
+	case DDR:
+		dev_printk(level, &qdev->pdev->dev, "RAS event.\nClass:%s\nDescription:%s %s %s\nError Threshold for this report %d\nSyndrome:\n    Instance %d\n    Count %d\n    Data 31_0 0x%x 0x%x\n    Data 63_32 0x%x 0x%x\n    Data 95_64 0x%x 0x%x\n    Data 127_96 0x%x 0x%x\n    Parity bits 0x%x\n    Address msb 0x%x\n    Address lsb 0x%x\n",
+			   err_class_str[msg->err_type],
+			   err_type_str[msg->err_type],
+			   "error from",
+			   err_src_str[msg->source],
+			   msg->err_threshold,
+			   ddr_syndrome->instance,
+			   ddr_syndrome->count,
+			   ddr_syndrome->data_31_0[1],
+			   ddr_syndrome->data_31_0[0],
+			   ddr_syndrome->data_63_32[1],
+			   ddr_syndrome->data_63_32[0],
+			   ddr_syndrome->data_95_64[1],
+			   ddr_syndrome->data_95_64[0],
+			   ddr_syndrome->data_127_96[1],
+			   ddr_syndrome->data_127_96[0],
+			   ddr_syndrome->parity_bits,
+			   ddr_syndrome->addr_msb,
+			   ddr_syndrome->addr_lsb);
+		break;
+	case SYS_BUS1:
+		dev_printk(level, &qdev->pdev->dev, "RAS event.\nClass:%s\nDescription:%s %s %s\nError Threshold for this report %d\nSyndrome:\n    instance %d\n    %s\n    err_type %d\n    address0 0x%x\n    address1 0x%x\n    address2 0x%x\n    address3 0x%x\n    address4 0x%x\n    address5 0x%x\n    address6 0x%x\n    address7 0x%x\n",
+			   err_class_str[msg->err_type],
+			   err_type_str[msg->err_type],
+			   "error from",
+			   err_src_str[msg->source],
+			   msg->err_threshold,
+			   sysbus1_syndrome->instance,
+			   sysbus1_syndrome->slave ? "Slave" : "Master",
+			   sysbus1_syndrome->err_type,
+			   sysbus1_syndrome->addr[0],
+			   sysbus1_syndrome->addr[1],
+			   sysbus1_syndrome->addr[2],
+			   sysbus1_syndrome->addr[3],
+			   sysbus1_syndrome->addr[4],
+			   sysbus1_syndrome->addr[5],
+			   sysbus1_syndrome->addr[6],
+			   sysbus1_syndrome->addr[7]);
+		break;
+	case SYS_BUS2:
+		dev_printk(level, &qdev->pdev->dev, "RAS event.\nClass:%s\nDescription:%s %s %s\nError Threshold for this report %d\nSyndrome:\n    instance %d\n    valid %d\n    word error %d\n    non-secure %d\n    opc %d\n    error code %d\n    transaction type %d\n    address space %d\n    operation type %d\n    len %d\n    redirect %d\n    path %d\n    ext_id %d\n    lsb2 %d\n    msb2 %d\n    lsb3 %d\n    msb3 %d\n",
+			   err_class_str[msg->err_type],
+			   err_type_str[msg->err_type],
+			   "error from",
+			   err_src_str[msg->source],
+			   msg->err_threshold,
+			   sysbus2_syndrome->instance,
+			   sysbus2_syndrome->valid,
+			   sysbus2_syndrome->word_error,
+			   sysbus2_syndrome->non_secure,
+			   sysbus2_syndrome->opc,
+			   sysbus2_syndrome->error_code,
+			   sysbus2_syndrome->trans_type,
+			   sysbus2_syndrome->addr_space,
+			   sysbus2_syndrome->op_type,
+			   sysbus2_syndrome->len,
+			   sysbus2_syndrome->redirect,
+			   sysbus2_syndrome->path,
+			   sysbus2_syndrome->ext_id,
+			   sysbus2_syndrome->lsb2,
+			   sysbus2_syndrome->msb2,
+			   sysbus2_syndrome->lsb3,
+			   sysbus2_syndrome->msb3);
+		break;
+	case NSP_MEM:
+		dev_printk(level, &qdev->pdev->dev, "RAS event.\nClass:%s\nDescription:%s %s %s\nError Threshold for this report %d\nSyndrome:\n    NSP ID %d\n    0x%x\n    0x%x\n    0x%x\n    0x%x\n    0x%x\n    0x%x\n    0x%x\n    0x%x\n",
+			   err_class_str[msg->err_type],
+			   err_type_str[msg->err_type],
+			   "error from",
+			   err_src_str[msg->source],
+			   msg->err_threshold,
+			   nsp_syndrome->nsp_id,
+			   nsp_syndrome->error_address[0],
+			   nsp_syndrome->error_address[1],
+			   nsp_syndrome->error_address[2],
+			   nsp_syndrome->error_address[3],
+			   nsp_syndrome->error_address[4],
+			   nsp_syndrome->error_address[5],
+			   nsp_syndrome->error_address[6],
+			   nsp_syndrome->error_address[7]);
+		break;
+	case TSENS:
+		if (tsens_syndrome->threshold_type >= NUM_TEMP_LVL) {
+			pci_warn(qdev->pdev, "Dropping RAS message with invalid temp threshold %d\n",
+				 tsens_syndrome->threshold_type);
+			break;
+		}
+
+		if (msg->err_type)
+			class = "Fatal";
+		else if (tsens_syndrome->threshold_type)
+			class = "Critical";
+		else
+			class = "Warning";
+
+		dev_printk(level, &qdev->pdev->dev, "RAS event.\nClass:%s\nDescription:%s %s %s\nError Threshold for this report %d\nSyndrome:\n    %s threshold\n    %d deg C\n",
+			   class,
+			   err_type_str[msg->err_type],
+			   "error from",
+			   err_src_str[msg->source],
+			   msg->err_threshold,
+			   threshold_type_str[tsens_syndrome->threshold_type],
+			   tsens_syndrome->temp);
+		break;
+	}
+
+	/* Uncorrectable errors are fatal */
+	if (msg->err_type == UE)
+		mhi_soc_reset(qdev->mhi_cntrl);
+
+	switch (msg->err_type) {
+	case CE:
+		if (qdev->ce_count != UINT_MAX)
+			qdev->ce_count++;
+		break;
+	case UE:
+		if (qdev->ce_count != UINT_MAX)
+			qdev->ue_count++;
+		break;
+	case UE_NF:
+		if (qdev->ce_count != UINT_MAX)
+			qdev->ue_nf_count++;
+		break;
+	default:
+		/* not possible */
+		break;
+	}
+}
+
+static ssize_t ce_count_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+	struct qaic_device *qdev = pci_get_drvdata(to_pci_dev(dev));
+
+	return sysfs_emit(buf, "%d\n", qdev->ce_count);
+}
+
+static ssize_t ue_count_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+	struct qaic_device *qdev = pci_get_drvdata(to_pci_dev(dev));
+
+	return sysfs_emit(buf, "%d\n", qdev->ue_count);
+}
+
+static ssize_t ue_nonfatal_count_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+	struct qaic_device *qdev = pci_get_drvdata(to_pci_dev(dev));
+
+	return sysfs_emit(buf, "%d\n", qdev->ue_nf_count);
+}
+
+static DEVICE_ATTR_RO(ce_count);
+static DEVICE_ATTR_RO(ue_count);
+static DEVICE_ATTR_RO(ue_nonfatal_count);
+
+static struct attribute *ras_attrs[] = {
+	&dev_attr_ce_count.attr,
+	&dev_attr_ue_count.attr,
+	&dev_attr_ue_nonfatal_count.attr,
+	NULL,
+};
+
+static struct attribute_group ras_group = {
+	.attrs = ras_attrs,
+};
+
+static int qaic_ras_mhi_probe(struct mhi_device *mhi_dev, const struct mhi_device_id *id)
+{
+	struct qaic_device *qdev = pci_get_drvdata(to_pci_dev(mhi_dev->mhi_cntrl->cntrl_dev));
+	struct ras_data *resp;
+	int ret;
+
+	ret = mhi_prepare_for_transfer(mhi_dev);
+	if (ret)
+		return ret;
+
+	resp = kzalloc(sizeof(*resp), GFP_KERNEL);
+	if (!resp) {
+		mhi_unprepare_from_transfer(mhi_dev);
+		return -ENOMEM;
+	}
+
+	ret = mhi_queue_buf(mhi_dev, DMA_FROM_DEVICE, resp, sizeof(*resp), MHI_EOT);
+	if (ret) {
+		kfree(resp);
+		mhi_unprepare_from_transfer(mhi_dev);
+		return ret;
+	}
+
+	ret = device_add_group(&qdev->pdev->dev, &ras_group);
+	if (ret) {
+		mhi_unprepare_from_transfer(mhi_dev);
+		pci_dbg(qdev->pdev, "ras add sysfs failed %d\n", ret);
+		return ret;
+	}
+
+	dev_set_drvdata(&mhi_dev->dev, qdev);
+	qdev->ras_ch = mhi_dev;
+
+	return ret;
+}
+
+static void qaic_ras_mhi_remove(struct mhi_device *mhi_dev)
+{
+	struct qaic_device *qdev;
+
+	qdev = dev_get_drvdata(&mhi_dev->dev);
+	qdev->ras_ch = NULL;
+	device_remove_group(&qdev->pdev->dev, &ras_group);
+	mhi_unprepare_from_transfer(mhi_dev);
+}
+
+static void qaic_ras_mhi_ul_xfer_cb(struct mhi_device *mhi_dev, struct mhi_result *mhi_result) {}
+
+static void qaic_ras_mhi_dl_xfer_cb(struct mhi_device *mhi_dev, struct mhi_result *mhi_result)
+{
+	struct qaic_device *qdev = dev_get_drvdata(&mhi_dev->dev);
+	struct ras_data *msg = mhi_result->buf_addr;
+	int ret;
+
+	if (mhi_result->transaction_status) {
+		kfree(msg);
+		return;
+	}
+
+	ras_msg_to_cpu(msg);
+	decode_ras_msg(qdev, msg);
+
+	ret = mhi_queue_buf(qdev->ras_ch, DMA_FROM_DEVICE, msg, sizeof(*msg), MHI_EOT);
+	if (ret) {
+		dev_err(&mhi_dev->dev, "Cannot requeue RAS recv buf %d\n", ret);
+		kfree(msg);
+	}
+}
+
+static const struct mhi_device_id qaic_ras_mhi_match_table[] = {
+	{ .chan = "QAIC_STATUS", },
+	{},
+};
+
+static struct mhi_driver qaic_ras_mhi_driver = {
+	.id_table = qaic_ras_mhi_match_table,
+	.remove = qaic_ras_mhi_remove,
+	.probe = qaic_ras_mhi_probe,
+	.ul_xfer_cb = qaic_ras_mhi_ul_xfer_cb,
+	.dl_xfer_cb = qaic_ras_mhi_dl_xfer_cb,
+	.driver = {
+		.name = "qaic_ras",
+	},
+};
+
+int qaic_ras_register(void)
+{
+	return mhi_driver_register(&qaic_ras_mhi_driver);
+}
+
+void qaic_ras_unregister(void)
+{
+	mhi_driver_unregister(&qaic_ras_mhi_driver);
+}
diff --git a/drivers/accel/qaic/qaic_ras.h b/drivers/accel/qaic/qaic_ras.h
new file mode 100644
index 000000000000..d44a4eeeb060
--- /dev/null
+++ b/drivers/accel/qaic/qaic_ras.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2020, The Linux Foundation. All rights reserved. */
+
+#ifndef __QAIC_RAS_H__
+#define __QAIC_RAS_H__
+
+int qaic_ras_register(void);
+void qaic_ras_unregister(void);
+
+#endif /* __QAIC_RAS_H__ */
diff --git a/drivers/accel/qaic/qaic_ssr.c b/drivers/accel/qaic/qaic_ssr.c
new file mode 100644
index 000000000000..9b662d690371
--- /dev/null
+++ b/drivers/accel/qaic/qaic_ssr.c
@@ -0,0 +1,815 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. */
+/* Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. */
+
+#include <asm/byteorder.h>
+#include <drm/drm_file.h>
+#include <drm/drm_managed.h>
+#include <linux/devcoredump.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/mhi.h>
+#include <linux/workqueue.h>
+
+#include "qaic.h"
+#include "qaic_ssr.h"
+
+#define SSR_RESP_MSG_SZ 32
+#define SSR_MHI_BUF_SIZE SZ_64K
+#define SSR_MEM_READ_DATA_SIZE ((u64)SSR_MHI_BUF_SIZE - sizeof(struct ssr_crashdump))
+#define SSR_MEM_READ_CHUNK_SIZE ((u64)SSR_MEM_READ_DATA_SIZE - sizeof(struct ssr_memory_read_rsp))
+
+#define DEBUG_TRANSFER_INFO		BIT(0)
+#define DEBUG_TRANSFER_INFO_RSP		BIT(1)
+#define MEMORY_READ			BIT(2)
+#define MEMORY_READ_RSP			BIT(3)
+#define DEBUG_TRANSFER_DONE		BIT(4)
+#define DEBUG_TRANSFER_DONE_RSP		BIT(5)
+#define SSR_EVENT			BIT(8)
+#define SSR_EVENT_RSP			BIT(9)
+
+#define SSR_EVENT_NACK		BIT(0)
+#define BEFORE_SHUTDOWN		BIT(1)
+#define AFTER_SHUTDOWN		BIT(2)
+#define BEFORE_POWER_UP		BIT(3)
+#define AFTER_POWER_UP		BIT(4)
+
+struct debug_info_table {
+	/* Save preferences. Default is mandatory */
+	u64 save_perf;
+	/* Base address of the debug region */
+	u64 mem_base;
+	/* Size of debug region in bytes */
+	u64 len;
+	/* Description */
+	char desc[20];
+	/* Filename of debug region */
+	char filename[20];
+};
+
+struct _ssr_hdr {
+	__le32 cmd;
+	__le32 len;
+	__le32 dbc_id;
+};
+
+struct ssr_hdr {
+	u32 cmd;
+	u32 len;
+	u32 dbc_id;
+};
+
+struct ssr_debug_transfer_info {
+	struct ssr_hdr hdr;
+	u32 resv;
+	u64 tbl_addr;
+	u64 tbl_len;
+} __packed;
+
+struct ssr_debug_transfer_info_rsp {
+	struct _ssr_hdr hdr;
+	__le32 ret;
+} __packed;
+
+struct ssr_memory_read {
+	struct _ssr_hdr hdr;
+	__le32 resv;
+	__le64 addr;
+	__le64 len;
+} __packed;
+
+struct ssr_memory_read_rsp {
+	struct _ssr_hdr hdr;
+	__le32 resv;
+	u8 data[];
+} __packed;
+
+struct ssr_debug_transfer_done {
+	struct _ssr_hdr hdr;
+	__le32 resv;
+} __packed;
+
+struct ssr_debug_transfer_done_rsp {
+	struct _ssr_hdr hdr;
+	__le32 ret;
+} __packed;
+
+struct ssr_event {
+	struct ssr_hdr hdr;
+	u32 event;
+} __packed;
+
+struct ssr_event_rsp {
+	struct _ssr_hdr hdr;
+	__le32 event;
+} __packed;
+
+struct ssr_resp {
+	/* Work struct to schedule work coming on QAIC_SSR channel */
+	struct work_struct work;
+	/* Root struct of device, used to access device resources */
+	struct qaic_device *qdev;
+	/* Buffer used by MHI for transfer requests */
+	u8 data[] __aligned(8);
+};
+
+/* SSR crashdump book keeping structure */
+struct ssr_dump_info {
+	/* DBC associated with this SSR crashdump */
+	struct dma_bridge_chan *dbc;
+	/*
+	 * It will be used when we complete the crashdump download and switch
+	 * to waiting on SSR events
+	 */
+	struct ssr_resp *resp;
+	/* MEMORY READ request MHI buffer.*/
+	struct ssr_memory_read *read_buf_req;
+	/* TRUE: ->read_buf_req is queued for MHI transaction. FALSE: Otherwise */
+	bool read_buf_req_queued;
+	/* Address of table in host */
+	void *tbl_addr;
+	/* Total size of table */
+	u64 tbl_len;
+	/* Offset of table(->tbl_addr) where the new chunk will be dumped */
+	u64 tbl_off;
+	/* Address of table in device/target */
+	u64 tbl_addr_dev;
+	/* Ptr to the entire dump */
+	void *dump_addr;
+	/* Entire crashdump size */
+	u64 dump_sz;
+	/* Offset of crashdump(->dump_addr) where the new chunk will be dumped */
+	u64 dump_off;
+	/* Points to the table entry we are currently downloading */
+	struct debug_info_table *tbl_ent;
+	/* Offset in the current table entry(->tbl_ent) for next chuck */
+	u64 tbl_ent_off;
+};
+
+struct ssr_crashdump {
+	/*
+	 * Points to a book keeping struct maintained by MHI SSR device while
+	 * downloading a SSR crashdump. It is NULL when crashdump downloading
+	 * not in progress.
+	 */
+	struct ssr_dump_info *dump_info;
+	/* Work struct to schedule work coming on QAIC_SSR channel */
+	struct work_struct work;
+	/* Root struct of device, used to access device resources */
+	struct qaic_device *qdev;
+	/* Buffer used by MHI for transfer requests */
+	u8 data[];
+};
+
+#define QAIC_SSR_DUMP_V1_MAGIC 0x1234567890abcdef
+#define QAIC_SSR_DUMP_V1_VER   1
+struct dump_file_meta {
+	u64 magic;
+	u64 version;
+	u64 size;		/* Total size of the entire dump */
+	u64 tbl_len;		/* Length of the table in byte */
+};
+
+/*
+ * Layout of crashdump
+ *              +------------------------------------------+
+ *              |         Crashdump Meta structure         |
+ *              | type: struct dump_file_meta              |
+ *              +------------------------------------------+
+ *              |             Crashdump Table              |
+ *              | type: array of struct debug_info_table   |
+ *              |                                          |
+ *              |                                          |
+ *              |                                          |
+ *              +------------------------------------------+
+ *              |                Crashdump                 |
+ *              |                                          |
+ *              |                                          |
+ *              |                                          |
+ *              |                                          |
+ *              |                                          |
+ *              +------------------------------------------+
+ */
+
+static void free_ssr_dump_info(struct ssr_crashdump *ssr_crash)
+{
+	struct ssr_dump_info *dump_info = ssr_crash->dump_info;
+
+	ssr_crash->dump_info = NULL;
+	if (!dump_info)
+		return;
+	if (!dump_info->read_buf_req_queued)
+		kfree(dump_info->read_buf_req);
+	vfree(dump_info->tbl_addr);
+	vfree(dump_info->dump_addr);
+	kfree(dump_info);
+}
+
+void qaic_clean_up_ssr(struct qaic_device *qdev)
+{
+	struct ssr_crashdump *ssr_crash = qdev->ssr_mhi_buf;
+
+	if (!ssr_crash)
+		return;
+
+	qaic_dbc_exit_ssr(qdev);
+	free_ssr_dump_info(ssr_crash);
+}
+
+static int alloc_dump(struct ssr_dump_info *dump_info)
+{
+	struct debug_info_table *tbl_ent = dump_info->tbl_addr;
+	struct dump_file_meta *dump_meta;
+	u64 tbl_sz_lp = 0;
+	u64 dump_size = 0;
+
+	while (tbl_sz_lp < dump_info->tbl_len) {
+		le64_to_cpus(&tbl_ent->save_perf);
+		le64_to_cpus(&tbl_ent->mem_base);
+		le64_to_cpus(&tbl_ent->len);
+
+		if (tbl_ent->len == 0)
+			return -EINVAL;
+
+		dump_size += tbl_ent->len;
+		tbl_ent++;
+		tbl_sz_lp += sizeof(*tbl_ent);
+	}
+
+	dump_info->dump_sz = dump_size + dump_info->tbl_len + sizeof(*dump_meta);
+	dump_info->dump_addr = vzalloc(dump_info->dump_sz);
+	if (!dump_info->dump_addr)
+		return -ENOMEM;
+
+	/* Copy crashdump meta and table */
+	dump_meta = dump_info->dump_addr;
+	dump_meta->magic = QAIC_SSR_DUMP_V1_MAGIC;
+	dump_meta->version = QAIC_SSR_DUMP_V1_VER;
+	dump_meta->size = dump_info->dump_sz;
+	dump_meta->tbl_len = dump_info->tbl_len;
+	memcpy(dump_info->dump_addr + sizeof(*dump_meta), dump_info->tbl_addr, dump_info->tbl_len);
+	/* Offset by crashdump meta and table (copied above) */
+	dump_info->dump_off = dump_info->tbl_len + sizeof(*dump_meta);
+
+	return 0;
+}
+
+static int send_xfer_done(struct qaic_device *qdev, void *resp, u32 dbc_id)
+{
+	struct ssr_debug_transfer_done *xfer_done;
+	int ret;
+
+	xfer_done = kmalloc(sizeof(*xfer_done), GFP_KERNEL);
+	if (!xfer_done) {
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	ret = mhi_queue_buf(qdev->ssr_ch, DMA_FROM_DEVICE, resp, SSR_RESP_MSG_SZ, MHI_EOT);
+	if (ret)
+		goto free_xfer_done;
+
+	xfer_done->hdr.cmd = cpu_to_le32(DEBUG_TRANSFER_DONE);
+	xfer_done->hdr.len = cpu_to_le32(sizeof(*xfer_done));
+	xfer_done->hdr.dbc_id = cpu_to_le32(dbc_id);
+
+	ret = mhi_queue_buf(qdev->ssr_ch, DMA_TO_DEVICE, xfer_done, sizeof(*xfer_done), MHI_EOT);
+	if (ret)
+		goto free_xfer_done;
+
+	return 0;
+
+free_xfer_done:
+	kfree(xfer_done);
+out:
+	return ret;
+}
+
+static int mem_read_req(struct qaic_device *qdev, u64 dest_addr, u64 dest_len)
+{
+	struct ssr_crashdump *ssr_crash = qdev->ssr_mhi_buf;
+	struct ssr_memory_read *read_buf_req;
+	struct ssr_dump_info *dump_info;
+	int ret;
+
+	dump_info = ssr_crash->dump_info;
+	ret = mhi_queue_buf(qdev->ssr_ch, DMA_FROM_DEVICE, ssr_crash->data, SSR_MEM_READ_DATA_SIZE,
+			    MHI_EOT);
+	if (ret)
+		goto out;
+
+	read_buf_req = dump_info->read_buf_req;
+	read_buf_req->hdr.cmd = cpu_to_le32(MEMORY_READ);
+	read_buf_req->hdr.len = cpu_to_le32(sizeof(*read_buf_req));
+	read_buf_req->hdr.dbc_id = cpu_to_le32(qdev->ssr_dbc);
+	read_buf_req->addr = cpu_to_le64(dest_addr);
+	read_buf_req->len = cpu_to_le64(dest_len);
+
+	ret = mhi_queue_buf(qdev->ssr_ch, DMA_TO_DEVICE, read_buf_req, sizeof(*read_buf_req),
+			    MHI_EOT);
+	if (!ret)
+		dump_info->read_buf_req_queued = true;
+
+out:
+	return ret;
+}
+
+static int ssr_copy_table(struct ssr_dump_info *dump_info, void *data, u64 len)
+{
+	if (len > dump_info->tbl_len - dump_info->tbl_off)
+		return -EINVAL;
+
+	memcpy(dump_info->tbl_addr + dump_info->tbl_off, data, len);
+	dump_info->tbl_off += len;
+
+	/* Entire table has been downloaded, alloc dump memory */
+	if (dump_info->tbl_off == dump_info->tbl_len) {
+		dump_info->tbl_ent = dump_info->tbl_addr;
+		return alloc_dump(dump_info);
+	}
+
+	return 0;
+}
+
+static int ssr_copy_dump(struct ssr_dump_info *dump_info, void *data, u64 len)
+{
+	struct debug_info_table *tbl_ent;
+
+	tbl_ent = dump_info->tbl_ent;
+
+	if (len > tbl_ent->len - dump_info->tbl_ent_off)
+		return -EINVAL;
+
+	memcpy(dump_info->dump_addr + dump_info->dump_off, data, len);
+	dump_info->dump_off += len;
+	dump_info->tbl_ent_off += len;
+
+	/*
+	 * Current segment (a entry in table) of the crashdump is complete,
+	 * move to next one
+	 */
+	if (tbl_ent->len == dump_info->tbl_ent_off) {
+		dump_info->tbl_ent++;
+		dump_info->tbl_ent_off = 0;
+	}
+
+	return 0;
+}
+
+static void ssr_dump_worker(struct work_struct *work)
+{
+	struct ssr_crashdump *ssr_crash = container_of(work, struct ssr_crashdump, work);
+	struct qaic_device *qdev = ssr_crash->qdev;
+	struct ssr_memory_read_rsp *mem_rd_resp;
+	struct debug_info_table *tbl_ent;
+	struct ssr_dump_info *dump_info;
+	u64 dest_addr, dest_len;
+	struct _ssr_hdr *_hdr;
+	struct ssr_hdr hdr;
+	u64 data_len;
+	int ret;
+
+	mem_rd_resp = (struct ssr_memory_read_rsp *)ssr_crash->data;
+	_hdr = &mem_rd_resp->hdr;
+	hdr.cmd = le32_to_cpu(_hdr->cmd);
+	hdr.len = le32_to_cpu(_hdr->len);
+	hdr.dbc_id = le32_to_cpu(_hdr->dbc_id);
+
+	if (hdr.dbc_id != qdev->ssr_dbc)
+		goto reset_device;
+
+	dump_info = ssr_crash->dump_info;
+	if (!dump_info)
+		goto reset_device;
+
+	if (hdr.cmd != MEMORY_READ_RSP)
+		goto free_dump_info;
+
+	if (hdr.len > SSR_MEM_READ_DATA_SIZE)
+		goto free_dump_info;
+
+	data_len = hdr.len - sizeof(*mem_rd_resp);
+
+	if (dump_info->tbl_off < dump_info->tbl_len) /* Chunk belongs to table */
+		ret = ssr_copy_table(dump_info, mem_rd_resp->data, data_len);
+	else /* Chunk belongs to crashdump */
+		ret = ssr_copy_dump(dump_info, mem_rd_resp->data, data_len);
+
+	if (ret)
+		goto free_dump_info;
+
+	if (dump_info->tbl_off < dump_info->tbl_len) {
+		/* Continue downloading table */
+		dest_addr = dump_info->tbl_addr_dev + dump_info->tbl_off;
+		dest_len = min(SSR_MEM_READ_CHUNK_SIZE, dump_info->tbl_len - dump_info->tbl_off);
+		ret = mem_read_req(qdev, dest_addr, dest_len);
+	} else if (dump_info->dump_off < dump_info->dump_sz) {
+		/* Continue downloading crashdump */
+		tbl_ent = dump_info->tbl_ent;
+		dest_addr = tbl_ent->mem_base + dump_info->tbl_ent_off;
+		dest_len = min(SSR_MEM_READ_CHUNK_SIZE, tbl_ent->len - dump_info->tbl_ent_off);
+		ret = mem_read_req(qdev, dest_addr, dest_len);
+	} else {
+		/* Crashdump download complete */
+		ret = send_xfer_done(qdev, dump_info->resp->data, hdr.dbc_id);
+	}
+
+	/* Most likely a MHI xfer has failed */
+	if (ret)
+		goto free_dump_info;
+
+	return;
+
+free_dump_info:
+	/* Free the allocated memory */
+	free_ssr_dump_info(ssr_crash);
+reset_device:
+	/*
+	 * After subsystem crashes in device crashdump collection begins but
+	 * something went wrong while collecting crashdump, now instead of
+	 * handling this error we just reset the device as the best effort has
+	 * been made
+	 */
+	mhi_soc_reset(qdev->mhi_cntrl);
+}
+
+static struct ssr_dump_info *alloc_dump_info(struct qaic_device *qdev,
+					     struct ssr_debug_transfer_info *debug_info)
+{
+	struct ssr_dump_info *dump_info;
+	int ret;
+
+	le64_to_cpus(&debug_info->tbl_len);
+	le64_to_cpus(&debug_info->tbl_addr);
+
+	if (debug_info->tbl_len == 0 ||
+	    debug_info->tbl_len % sizeof(struct debug_info_table) != 0) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	/* Allocate SSR crashdump book keeping structure */
+	dump_info = kzalloc(sizeof(*dump_info), GFP_KERNEL);
+	if (!dump_info) {
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	/* Buffer used to send MEMORY READ request to device via MHI */
+	dump_info->read_buf_req = kzalloc(sizeof(*dump_info->read_buf_req), GFP_KERNEL);
+	if (!dump_info->read_buf_req) {
+		ret = -ENOMEM;
+		goto free_dump_info;
+	}
+
+	/* Crashdump meta table buffer */
+	dump_info->tbl_addr = vzalloc(debug_info->tbl_len);
+	if (!dump_info->tbl_addr) {
+		ret = -ENOMEM;
+		goto free_read_buf_req;
+	}
+
+	dump_info->tbl_addr_dev = debug_info->tbl_addr;
+	dump_info->tbl_len = debug_info->tbl_len;
+
+	return dump_info;
+
+free_read_buf_req:
+	kfree(dump_info->read_buf_req);
+free_dump_info:
+	kfree(dump_info);
+out:
+	return ERR_PTR(ret);
+}
+
+static int dbg_xfer_info_rsp(struct qaic_device *qdev, struct dma_bridge_chan *dbc,
+			     struct ssr_debug_transfer_info *debug_info)
+{
+	struct ssr_debug_transfer_info_rsp *debug_rsp;
+	struct ssr_crashdump *ssr_crash = NULL;
+	int ret = 0, ret2;
+
+	debug_rsp = kmalloc(sizeof(*debug_rsp), GFP_KERNEL);
+	if (!debug_rsp)
+		return -ENOMEM;
+
+	if (!qdev->ssr_mhi_buf) {
+		ret = -ENOMEM;
+		goto send_rsp;
+	}
+
+	if (dbc->state != DBC_STATE_BEFORE_POWER_UP) {
+		ret = -EINVAL;
+		goto send_rsp;
+	}
+
+	ssr_crash = qdev->ssr_mhi_buf;
+	ssr_crash->dump_info = alloc_dump_info(qdev, debug_info);
+	if (IS_ERR(ssr_crash->dump_info)) {
+		ret = PTR_ERR(ssr_crash->dump_info);
+		ssr_crash->dump_info = NULL;
+	}
+
+send_rsp:
+	debug_rsp->hdr.cmd = cpu_to_le32(DEBUG_TRANSFER_INFO_RSP);
+	debug_rsp->hdr.len = cpu_to_le32(sizeof(*debug_rsp));
+	debug_rsp->hdr.dbc_id = cpu_to_le32(dbc->id);
+	/*
+	 * 0 = Return an ACK confirming the host is ready to download crashdump
+	 * 1 = Return an NACK confirming the host is not ready to download crashdump
+	 */
+	debug_rsp->ret = cpu_to_le32(ret ? 1 : 0);
+
+	ret2 = mhi_queue_buf(qdev->ssr_ch, DMA_TO_DEVICE, debug_rsp, sizeof(*debug_rsp), MHI_EOT);
+	if (ret2) {
+		free_ssr_dump_info(ssr_crash);
+		kfree(debug_rsp);
+		return ret2;
+	}
+
+	return ret;
+}
+
+static void dbg_xfer_done_rsp(struct qaic_device *qdev, struct dma_bridge_chan *dbc,
+			      struct ssr_debug_transfer_done_rsp *xfer_rsp)
+{
+	struct ssr_crashdump *ssr_crash = qdev->ssr_mhi_buf;
+	u32 status = le32_to_cpu(xfer_rsp->ret);
+	struct device *dev = &qdev->pdev->dev;
+	struct ssr_dump_info *dump_info;
+
+	dump_info = ssr_crash->dump_info;
+	if (!dump_info)
+		return;
+
+	if (status) {
+		free_ssr_dump_info(ssr_crash);
+		return;
+	}
+
+	dev_coredumpv(dev, dump_info->dump_addr, dump_info->dump_sz, GFP_KERNEL);
+	/* dev_coredumpv will free dump_info->dump_addr */
+	dump_info->dump_addr = NULL;
+	free_ssr_dump_info(ssr_crash);
+}
+
+static void ssr_worker(struct work_struct *work)
+{
+	struct ssr_resp *resp = container_of(work, struct ssr_resp, work);
+	struct ssr_hdr *hdr = (struct ssr_hdr *)resp->data;
+	struct ssr_dump_info *dump_info = NULL;
+	struct qaic_device *qdev = resp->qdev;
+	struct ssr_crashdump *ssr_crash;
+	struct ssr_event_rsp *event_rsp;
+	struct dma_bridge_chan *dbc;
+	struct ssr_event *event;
+	u32 ssr_event_ack;
+	int ret;
+
+	le32_to_cpus(&hdr->cmd);
+	le32_to_cpus(&hdr->len);
+	le32_to_cpus(&hdr->dbc_id);
+
+	if (hdr->len > SSR_RESP_MSG_SZ)
+		goto out;
+
+	if (hdr->dbc_id >= qdev->num_dbc)
+		goto out;
+
+	dbc = &qdev->dbc[hdr->dbc_id];
+
+	switch (hdr->cmd) {
+	case DEBUG_TRANSFER_INFO:
+		ret = dbg_xfer_info_rsp(qdev, dbc, (struct ssr_debug_transfer_info *)resp->data);
+		if (ret)
+			break;
+
+		ssr_crash = qdev->ssr_mhi_buf;
+		dump_info = ssr_crash->dump_info;
+		dump_info->dbc = dbc;
+		dump_info->resp = resp;
+
+		/* Start by downloading debug table */
+		ret = mem_read_req(qdev, dump_info->tbl_addr_dev,
+				   min(dump_info->tbl_len, SSR_MEM_READ_CHUNK_SIZE));
+		if (ret) {
+			free_ssr_dump_info(ssr_crash);
+			break;
+		}
+
+		/*
+		 * Till now everything went fine, which means that we will be
+		 * collecting crashdump chunk by chunk. Do not queue a response
+		 * buffer for SSR cmds till the crashdump is complete.
+		 */
+		return;
+	case SSR_EVENT:
+		event = (struct ssr_event *)hdr;
+		le32_to_cpus(&event->event);
+		ssr_event_ack = event->event;
+		ssr_crash = qdev->ssr_mhi_buf;
+
+		switch (event->event) {
+		case BEFORE_SHUTDOWN:
+			set_dbc_state(qdev, hdr->dbc_id, DBC_STATE_BEFORE_SHUTDOWN);
+			qaic_dbc_enter_ssr(qdev, hdr->dbc_id);
+			break;
+		case AFTER_SHUTDOWN:
+			set_dbc_state(qdev, hdr->dbc_id, DBC_STATE_AFTER_SHUTDOWN);
+			break;
+		case BEFORE_POWER_UP:
+			set_dbc_state(qdev, hdr->dbc_id, DBC_STATE_BEFORE_POWER_UP);
+			break;
+		case AFTER_POWER_UP:
+			/*
+			 * If dump info is a non NULL value it means that we
+			 * have received this SSR event while downloading a
+			 * crashdump for this DBC is still in progress. NACK
+			 * the SSR event
+			 */
+			if (ssr_crash && ssr_crash->dump_info) {
+				free_ssr_dump_info(ssr_crash);
+				ssr_event_ack = SSR_EVENT_NACK;
+				break;
+			}
+
+			set_dbc_state(qdev, hdr->dbc_id, DBC_STATE_AFTER_POWER_UP);
+			break;
+		default:
+			break;
+		}
+
+		event_rsp = kmalloc(sizeof(*event_rsp), GFP_KERNEL);
+		if (!event_rsp)
+			break;
+
+		event_rsp->hdr.cmd = cpu_to_le32(SSR_EVENT_RSP);
+		event_rsp->hdr.len = cpu_to_le32(sizeof(*event_rsp));
+		event_rsp->hdr.dbc_id = cpu_to_le32(hdr->dbc_id);
+		event_rsp->event = cpu_to_le32(ssr_event_ack);
+
+		ret = mhi_queue_buf(qdev->ssr_ch, DMA_TO_DEVICE, event_rsp, sizeof(*event_rsp),
+				    MHI_EOT);
+		if (ret)
+			kfree(event_rsp);
+
+		if (event->event == AFTER_POWER_UP && ssr_event_ack != SSR_EVENT_NACK) {
+			qaic_dbc_exit_ssr(qdev);
+			set_dbc_state(qdev, hdr->dbc_id, DBC_STATE_IDLE);
+		}
+
+		break;
+	case DEBUG_TRANSFER_DONE_RSP:
+		dbg_xfer_done_rsp(qdev, dbc, (struct ssr_debug_transfer_done_rsp *)hdr);
+		break;
+	default:
+		break;
+	}
+
+out:
+	ret = mhi_queue_buf(qdev->ssr_ch, DMA_FROM_DEVICE, resp->data, SSR_RESP_MSG_SZ, MHI_EOT);
+	if (ret)
+		kfree(resp);
+}
+
+static int qaic_ssr_mhi_probe(struct mhi_device *mhi_dev, const struct mhi_device_id *id)
+{
+	struct qaic_device *qdev = pci_get_drvdata(to_pci_dev(mhi_dev->mhi_cntrl->cntrl_dev));
+	struct ssr_resp *resp;
+	int ret;
+
+	ret = mhi_prepare_for_transfer(mhi_dev);
+	if (ret)
+		return ret;
+
+	resp = kzalloc(sizeof(*resp) + SSR_RESP_MSG_SZ, GFP_KERNEL);
+	if (!resp) {
+		mhi_unprepare_from_transfer(mhi_dev);
+		return -ENOMEM;
+	}
+
+	resp->qdev = qdev;
+	INIT_WORK(&resp->work, ssr_worker);
+
+	ret = mhi_queue_buf(mhi_dev, DMA_FROM_DEVICE, resp->data, SSR_RESP_MSG_SZ, MHI_EOT);
+	if (ret) {
+		kfree(resp);
+		mhi_unprepare_from_transfer(mhi_dev);
+		return ret;
+	}
+
+	dev_set_drvdata(&mhi_dev->dev, qdev);
+	qdev->ssr_ch = mhi_dev;
+
+	return 0;
+}
+
+static void qaic_ssr_mhi_remove(struct mhi_device *mhi_dev)
+{
+	struct qaic_device *qdev;
+
+	qdev = dev_get_drvdata(&mhi_dev->dev);
+	mhi_unprepare_from_transfer(qdev->ssr_ch);
+	qdev->ssr_ch = NULL;
+}
+
+static void qaic_ssr_mhi_ul_xfer_cb(struct mhi_device *mhi_dev, struct mhi_result *mhi_result)
+{
+	struct qaic_device *qdev = dev_get_drvdata(&mhi_dev->dev);
+	struct ssr_crashdump *ssr_crash = qdev->ssr_mhi_buf;
+	struct _ssr_hdr *hdr = mhi_result->buf_addr;
+	struct ssr_dump_info *dump_info;
+
+	if (mhi_result->transaction_status) {
+		kfree(mhi_result->buf_addr);
+		return;
+	}
+
+	/*
+	 * MEMORY READ is used to download crashdump. And crashdump is
+	 * downloaded chunk by chunk in a series of MEMORY READ SSR commands.
+	 * Hence to avoid too many kmalloc() and kfree() of the same MEMORY READ
+	 * request buffer, we allocate only one such buffer and free it only
+	 * once.
+	 */
+	if (le32_to_cpu(hdr->cmd) == MEMORY_READ) {
+		dump_info = ssr_crash->dump_info;
+		if (dump_info) {
+			dump_info->read_buf_req_queued = false;
+			return;
+		}
+	}
+
+	kfree(mhi_result->buf_addr);
+}
+
+static void qaic_ssr_mhi_dl_xfer_cb(struct mhi_device *mhi_dev, struct mhi_result *mhi_result)
+{
+	struct ssr_resp *resp = container_of(mhi_result->buf_addr, struct ssr_resp, data);
+	struct qaic_device *qdev = dev_get_drvdata(&mhi_dev->dev);
+	struct ssr_crashdump *ssr_crash = qdev->ssr_mhi_buf;
+	bool memory_read_rsp = false;
+
+	if (ssr_crash && ssr_crash->data == mhi_result->buf_addr)
+		memory_read_rsp = true;
+
+	if (mhi_result->transaction_status) {
+		/* Do not free SSR crashdump buffer as it allocated via managed APIs */
+		if (!memory_read_rsp)
+			kfree(resp);
+		return;
+	}
+
+	if (memory_read_rsp)
+		queue_work(qdev->ssr_wq, &ssr_crash->work);
+	else
+		queue_work(qdev->ssr_wq, &resp->work);
+}
+
+static const struct mhi_device_id qaic_ssr_mhi_match_table[] = {
+	{ .chan = "QAIC_SSR", },
+	{},
+};
+
+static struct mhi_driver qaic_ssr_mhi_driver = {
+	.id_table = qaic_ssr_mhi_match_table,
+	.remove = qaic_ssr_mhi_remove,
+	.probe = qaic_ssr_mhi_probe,
+	.ul_xfer_cb = qaic_ssr_mhi_ul_xfer_cb,
+	.dl_xfer_cb = qaic_ssr_mhi_dl_xfer_cb,
+	.driver = {
+		.name = "qaic_ssr",
+	},
+};
+
+int qaic_ssr_init(struct qaic_device *qdev, struct drm_device *drm)
+{
+	struct ssr_crashdump *ssr_crash;
+
+	qdev->ssr_dbc = QAIC_SSR_DBC_SENTINEL;
+
+	/*
+	 * Device requests only one SSR at a time. So allocating only one
+	 * buffer to download crashdump is good enough.
+	 */
+	ssr_crash = drmm_kzalloc(drm, SSR_MHI_BUF_SIZE, GFP_KERNEL);
+	if (!ssr_crash)
+		return -ENOMEM;
+
+	ssr_crash->qdev = qdev;
+	INIT_WORK(&ssr_crash->work, ssr_dump_worker);
+	qdev->ssr_mhi_buf = ssr_crash;
+
+	return 0;
+}
+
+int qaic_ssr_register(void)
+{
+	return mhi_driver_register(&qaic_ssr_mhi_driver);
+}
+
+void qaic_ssr_unregister(void)
+{
+	mhi_driver_unregister(&qaic_ssr_mhi_driver);
+}
diff --git a/drivers/accel/qaic/qaic_ssr.h b/drivers/accel/qaic/qaic_ssr.h
new file mode 100644
index 000000000000..97ccff305750
--- /dev/null
+++ b/drivers/accel/qaic/qaic_ssr.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only
+ *
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021, 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef __QAIC_SSR_H__
+#define __QAIC_SSR_H__
+
+struct drm_device;
+struct qaic_device;
+
+int qaic_ssr_register(void);
+void qaic_ssr_unregister(void);
+void qaic_clean_up_ssr(struct qaic_device *qdev);
+int qaic_ssr_init(struct qaic_device *qdev, struct drm_device *drm);
+#endif /* __QAIC_SSR_H__ */
diff --git a/drivers/accel/qaic/qaic_sysfs.c b/drivers/accel/qaic/qaic_sysfs.c
new file mode 100644
index 000000000000..e0afb0ffb589
--- /dev/null
+++ b/drivers/accel/qaic/qaic_sysfs.c
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/* Copyright (c) 2020-2025, The Linux Foundation. All rights reserved. */
+
+#include <drm/drm_file.h>
+#include <drm/drm_managed.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/kobject.h>
+#include <linux/mutex.h>
+#include <linux/sysfs.h>
+
+#include "qaic.h"
+
+#define NAME_LEN		14
+
+struct dbc_attribute {
+	struct device_attribute dev_attr;
+	u32 dbc_id;
+	char name[NAME_LEN];
+};
+
+static ssize_t dbc_state_show(struct device *dev, struct device_attribute *a, char *buf)
+{
+	struct dbc_attribute *dbc_attr = container_of(a, struct dbc_attribute, dev_attr);
+	struct drm_minor *minor = dev_get_drvdata(dev);
+	struct qaic_device *qdev;
+
+	qdev = to_qaic_device(minor->dev);
+	return sysfs_emit(buf, "%d\n", qdev->dbc[dbc_attr->dbc_id].state);
+}
+
+void set_dbc_state(struct qaic_device *qdev, u32 dbc_id, unsigned int state)
+{
+	struct device *kdev = to_accel_kdev(qdev->qddev);
+	char *envp[3] = {};
+	char state_str[16];
+	char id_str[12];
+
+	envp[0] = id_str;
+	envp[1] = state_str;
+
+	if (state >= DBC_STATE_MAX)
+		return;
+	if (dbc_id >= qdev->num_dbc)
+		return;
+	if (state == qdev->dbc[dbc_id].state)
+		return;
+
+	scnprintf(id_str, ARRAY_SIZE(id_str), "DBC_ID=%d", dbc_id);
+	scnprintf(state_str, ARRAY_SIZE(state_str), "DBC_STATE=%d", state);
+
+	qdev->dbc[dbc_id].state = state;
+	kobject_uevent_env(&kdev->kobj, KOBJ_CHANGE, envp);
+}
+
+int qaic_sysfs_init(struct qaic_drm_device *qddev)
+{
+	struct device *kdev = to_accel_kdev(qddev);
+	struct drm_device *drm = to_drm(qddev);
+	u32 num_dbc = qddev->qdev->num_dbc;
+	struct dbc_attribute *dbc_attrs;
+	int i, ret;
+
+	dbc_attrs = drmm_kcalloc(drm, num_dbc, sizeof(*dbc_attrs), GFP_KERNEL);
+	if (!dbc_attrs)
+		return -ENOMEM;
+
+	for (i = 0; i < num_dbc; ++i) {
+		struct dbc_attribute *dbc_attr = &dbc_attrs[i];
+
+		sysfs_attr_init(&dbc_attr->dev_attr.attr);
+		dbc_attr->dbc_id = i;
+		scnprintf(dbc_attr->name, NAME_LEN, "dbc%d_state", i);
+		dbc_attr->dev_attr.attr.name = dbc_attr->name;
+		dbc_attr->dev_attr.attr.mode = 0444;
+		dbc_attr->dev_attr.show = dbc_state_show;
+		ret = sysfs_create_file(&kdev->kobj, &dbc_attr->dev_attr.attr);
+		if (ret) {
+			int j;
+
+			for (j = 0; j < i; ++j) {
+				dbc_attr = &dbc_attrs[j];
+				sysfs_remove_file(&kdev->kobj, &dbc_attr->dev_attr.attr);
+			}
+			drmm_kfree(drm, dbc_attrs);
+			return ret;
+		}
+	}
+
+	qddev->sysfs_attrs = dbc_attrs;
+	return 0;
+}
+
+void qaic_sysfs_remove(struct qaic_drm_device *qddev)
+{
+	struct dbc_attribute *dbc_attrs = qddev->sysfs_attrs;
+	struct device *kdev = to_accel_kdev(qddev);
+	u32 num_dbc = qddev->qdev->num_dbc;
+	int i;
+
+	if (!dbc_attrs)
+		return;
+
+	qddev->sysfs_attrs = NULL;
+	for (i = 0; i < num_dbc; ++i)
+		sysfs_remove_file(&kdev->kobj, &dbc_attrs[i].dev_attr.attr);
+	drmm_kfree(to_drm(qddev), dbc_attrs);
+}
diff --git a/drivers/accel/qaic/qaic_timesync.c b/drivers/accel/qaic/qaic_timesync.c
new file mode 100644
index 000000000000..8af2475f4f36
--- /dev/null
+++ b/drivers/accel/qaic/qaic_timesync.c
@@ -0,0 +1,404 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/math64.h>
+#include <linux/mhi.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/time64.h>
+#include <linux/timer.h>
+
+#include "qaic.h"
+#include "qaic_timesync.h"
+
+#define QTIMER_REG_OFFSET			0xa28
+#define QAIC_TIMESYNC_SIGNATURE			0x55aa
+#define QAIC_CONV_QTIMER_TO_US(qtimer)		(mul_u64_u32_div(qtimer, 10, 192))
+
+static unsigned int timesync_delay_ms = 1000; /* 1 sec default */
+module_param(timesync_delay_ms, uint, 0600);
+MODULE_PARM_DESC(timesync_delay_ms, "Delay in ms between two consecutive timesync operations");
+
+enum qts_msg_type {
+	QAIC_TS_CMD_TO_HOST,
+	QAIC_TS_SYNC_REQ,
+	QAIC_TS_ACK_TO_HOST,
+	QAIC_TS_MSG_TYPE_MAX
+};
+
+/**
+ * struct qts_hdr - Timesync message header structure.
+ * @signature: Unique signature to identify the timesync message.
+ * @reserved_1: Reserved for future use.
+ * @reserved_2: Reserved for future use.
+ * @msg_type: sub-type of the timesync message.
+ * @reserved_3: Reserved for future use.
+ */
+struct qts_hdr {
+	__le16	signature;
+	__le16	reserved_1;
+	u8	reserved_2;
+	u8	msg_type;
+	__le16	reserved_3;
+} __packed;
+
+/**
+ * struct qts_timeval - Structure to carry time information.
+ * @tv_sec: Seconds part of the time.
+ * @tv_usec: uS (microseconds) part of the time.
+ */
+struct qts_timeval {
+	__le64	tv_sec;
+	__le64	tv_usec;
+} __packed;
+
+/**
+ * struct qts_host_time_sync_msg_data - Structure to denote the timesync message.
+ * @header: Header of the timesync message.
+ * @data: Time information.
+ */
+struct qts_host_time_sync_msg_data {
+	struct	qts_hdr header;
+	struct	qts_timeval data;
+} __packed;
+
+/**
+ * struct mqts_dev - MHI QAIC Timesync Control device.
+ * @qdev: Pointer to the root device struct driven by QAIC driver.
+ * @mhi_dev: Pointer to associated MHI device.
+ * @timer: Timer handle used for timesync.
+ * @qtimer_addr: Device QTimer register pointer.
+ * @buff_in_use: atomic variable to track if the sync_msg buffer is in use.
+ * @dev: Device pointer to qdev->pdev->dev stored for easy access.
+ * @sync_msg: Buffer used to send timesync message over MHI.
+ */
+struct mqts_dev {
+	struct qaic_device *qdev;
+	struct mhi_device *mhi_dev;
+	struct timer_list timer;
+	void __iomem *qtimer_addr;
+	atomic_t buff_in_use;
+	struct device *dev;
+	struct qts_host_time_sync_msg_data *sync_msg;
+};
+
+struct qts_resp_msg {
+	struct qts_hdr	hdr;
+} __packed;
+
+struct qts_resp {
+	struct qts_resp_msg	data;
+	struct work_struct	work;
+	struct qaic_device	*qdev;
+};
+
+#ifdef readq
+static u64 read_qtimer(const volatile void __iomem *addr)
+{
+	return readq(addr);
+}
+#else
+static u64 read_qtimer(const volatile void __iomem *addr)
+{
+	u64 low, high;
+
+	low = readl(addr);
+	high = readl(addr + sizeof(u32));
+	return low | (high << 32);
+}
+#endif
+
+static void qaic_timesync_ul_xfer_cb(struct mhi_device *mhi_dev, struct mhi_result *mhi_result)
+{
+	struct mqts_dev *mqtsdev = dev_get_drvdata(&mhi_dev->dev);
+
+	dev_dbg(mqtsdev->dev, "%s status: %d xfer_len: %zu\n", __func__,
+		mhi_result->transaction_status, mhi_result->bytes_xferd);
+
+	atomic_set(&mqtsdev->buff_in_use, 0);
+}
+
+static void qaic_timesync_dl_xfer_cb(struct mhi_device *mhi_dev, struct mhi_result *mhi_result)
+{
+	struct mqts_dev *mqtsdev = dev_get_drvdata(&mhi_dev->dev);
+
+	dev_err(mqtsdev->dev, "%s no data expected on dl channel\n", __func__);
+}
+
+static void qaic_timesync_timer(struct timer_list *t)
+{
+	struct mqts_dev *mqtsdev = timer_container_of(mqtsdev, t, timer);
+	struct qts_host_time_sync_msg_data *sync_msg;
+	u64 device_qtimer_us;
+	u64 device_qtimer;
+	u64 host_time_us;
+	u64 offset_us;
+	u64 host_sec;
+	int ret;
+
+	if (atomic_read(&mqtsdev->buff_in_use)) {
+		dev_dbg(mqtsdev->dev, "%s buffer not free, schedule next cycle\n", __func__);
+		goto mod_timer;
+	}
+	atomic_set(&mqtsdev->buff_in_use, 1);
+
+	sync_msg = mqtsdev->sync_msg;
+	sync_msg->header.signature = cpu_to_le16(QAIC_TIMESYNC_SIGNATURE);
+	sync_msg->header.msg_type = QAIC_TS_SYNC_REQ;
+	/* Read host UTC time and convert to uS*/
+	host_time_us = div_u64(ktime_get_real_ns(), NSEC_PER_USEC);
+	device_qtimer = read_qtimer(mqtsdev->qtimer_addr);
+	device_qtimer_us = QAIC_CONV_QTIMER_TO_US(device_qtimer);
+	/* Offset between host UTC and device time */
+	offset_us = host_time_us - device_qtimer_us;
+
+	host_sec = div_u64(offset_us, USEC_PER_SEC);
+	sync_msg->data.tv_usec = cpu_to_le64(offset_us - host_sec * USEC_PER_SEC);
+	sync_msg->data.tv_sec = cpu_to_le64(host_sec);
+	ret = mhi_queue_buf(mqtsdev->mhi_dev, DMA_TO_DEVICE, sync_msg, sizeof(*sync_msg), MHI_EOT);
+	if (ret && (ret != -EAGAIN)) {
+		dev_err(mqtsdev->dev, "%s unable to queue to mhi:%d\n", __func__, ret);
+		return;
+	} else if (ret == -EAGAIN) {
+		atomic_set(&mqtsdev->buff_in_use, 0);
+	}
+
+mod_timer:
+	ret = mod_timer(t, jiffies + msecs_to_jiffies(timesync_delay_ms));
+	if (ret)
+		dev_err(mqtsdev->dev, "%s mod_timer error:%d\n", __func__, ret);
+}
+
+void qaic_mqts_ch_stop_timer(struct mhi_device *mhi_dev)
+{
+	struct mqts_dev *mqtsdev = dev_get_drvdata(&mhi_dev->dev);
+
+	timer_delete_sync(&mqtsdev->timer);
+}
+
+static int qaic_timesync_probe(struct mhi_device *mhi_dev, const struct mhi_device_id *id)
+{
+	struct qaic_device *qdev = pci_get_drvdata(to_pci_dev(mhi_dev->mhi_cntrl->cntrl_dev));
+	struct mqts_dev *mqtsdev;
+	struct timer_list *timer;
+	int ret;
+
+	mqtsdev = kzalloc(sizeof(*mqtsdev), GFP_KERNEL);
+	if (!mqtsdev) {
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	timer = &mqtsdev->timer;
+	mqtsdev->mhi_dev = mhi_dev;
+	mqtsdev->qdev = qdev;
+	mqtsdev->dev = &qdev->pdev->dev;
+
+	mqtsdev->sync_msg = kzalloc(sizeof(*mqtsdev->sync_msg), GFP_KERNEL);
+	if (!mqtsdev->sync_msg) {
+		ret = -ENOMEM;
+		goto free_mqts_dev;
+	}
+	atomic_set(&mqtsdev->buff_in_use, 0);
+
+	ret = mhi_prepare_for_transfer(mhi_dev);
+	if (ret)
+		goto free_sync_msg;
+
+	/* Qtimer register pointer */
+	mqtsdev->qtimer_addr = qdev->bar_mhi + QTIMER_REG_OFFSET;
+	timer_setup(timer, qaic_timesync_timer, 0);
+	timer->expires = jiffies + msecs_to_jiffies(timesync_delay_ms);
+	add_timer(timer);
+	dev_set_drvdata(&mhi_dev->dev, mqtsdev);
+	qdev->mqts_ch = mhi_dev;
+
+	return 0;
+
+free_sync_msg:
+	kfree(mqtsdev->sync_msg);
+free_mqts_dev:
+	kfree(mqtsdev);
+out:
+	return ret;
+};
+
+static void qaic_timesync_remove(struct mhi_device *mhi_dev)
+{
+	struct mqts_dev *mqtsdev = dev_get_drvdata(&mhi_dev->dev);
+
+	mqtsdev->qdev->mqts_ch = NULL;
+	timer_delete_sync(&mqtsdev->timer);
+	mhi_unprepare_from_transfer(mqtsdev->mhi_dev);
+	kfree(mqtsdev->sync_msg);
+	kfree(mqtsdev);
+}
+
+static const struct mhi_device_id qaic_timesync_match_table[] = {
+	{ .chan = "QAIC_TIMESYNC_PERIODIC"},
+	{},
+};
+
+MODULE_DEVICE_TABLE(mhi, qaic_timesync_match_table);
+
+static struct mhi_driver qaic_timesync_driver = {
+	.id_table = qaic_timesync_match_table,
+	.remove = qaic_timesync_remove,
+	.probe = qaic_timesync_probe,
+	.ul_xfer_cb = qaic_timesync_ul_xfer_cb,
+	.dl_xfer_cb = qaic_timesync_dl_xfer_cb,
+	.driver = {
+		.name = "qaic_timesync_periodic",
+	},
+};
+
+static void qaic_boot_timesync_worker(struct work_struct *work)
+{
+	struct qts_resp *resp = container_of(work, struct qts_resp, work);
+	struct qts_host_time_sync_msg_data *req;
+	struct qts_resp_msg data = resp->data;
+	struct qaic_device *qdev = resp->qdev;
+	struct mhi_device *mhi_dev;
+	struct timespec64 ts;
+	int ret;
+
+	mhi_dev = qdev->qts_ch;
+	/* Queue the response message beforehand to avoid race conditions */
+	ret = mhi_queue_buf(mhi_dev, DMA_FROM_DEVICE, &resp->data, sizeof(resp->data), MHI_EOT);
+	if (ret) {
+		kfree(resp);
+		dev_warn(&mhi_dev->dev, "Failed to re-queue response buffer %d\n", ret);
+		return;
+	}
+
+	switch (data.hdr.msg_type) {
+	case QAIC_TS_CMD_TO_HOST:
+		req = kzalloc(sizeof(*req), GFP_KERNEL);
+		if (!req)
+			break;
+
+		req->header = data.hdr;
+		req->header.msg_type = QAIC_TS_SYNC_REQ;
+		ktime_get_real_ts64(&ts);
+		req->data.tv_sec = cpu_to_le64(ts.tv_sec);
+		req->data.tv_usec = cpu_to_le64(div_u64(ts.tv_nsec, NSEC_PER_USEC));
+
+		ret = mhi_queue_buf(mhi_dev, DMA_TO_DEVICE, req, sizeof(*req), MHI_EOT);
+		if (ret) {
+			kfree(req);
+			dev_dbg(&mhi_dev->dev, "Failed to send request message. Error %d\n", ret);
+		}
+		break;
+	case QAIC_TS_ACK_TO_HOST:
+		dev_dbg(&mhi_dev->dev, "ACK received from device\n");
+		break;
+	default:
+		dev_err(&mhi_dev->dev, "Invalid message type %u.\n", data.hdr.msg_type);
+	}
+}
+
+static int qaic_boot_timesync_queue_resp(struct mhi_device *mhi_dev, struct qaic_device *qdev)
+{
+	struct qts_resp *resp;
+	int ret;
+
+	resp = kzalloc(sizeof(*resp), GFP_KERNEL);
+	if (!resp)
+		return -ENOMEM;
+
+	resp->qdev = qdev;
+	INIT_WORK(&resp->work, qaic_boot_timesync_worker);
+
+	ret = mhi_queue_buf(mhi_dev, DMA_FROM_DEVICE, &resp->data, sizeof(resp->data), MHI_EOT);
+	if (ret) {
+		kfree(resp);
+		dev_warn(&mhi_dev->dev, "Failed to queue response buffer %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static void qaic_boot_timesync_remove(struct mhi_device *mhi_dev)
+{
+	struct qaic_device *qdev;
+
+	qdev = dev_get_drvdata(&mhi_dev->dev);
+	mhi_unprepare_from_transfer(qdev->qts_ch);
+	qdev->qts_ch = NULL;
+}
+
+static int qaic_boot_timesync_probe(struct mhi_device *mhi_dev, const struct mhi_device_id *id)
+{
+	struct qaic_device *qdev = pci_get_drvdata(to_pci_dev(mhi_dev->mhi_cntrl->cntrl_dev));
+	int ret;
+
+	ret = mhi_prepare_for_transfer(mhi_dev);
+	if (ret)
+		return ret;
+
+	qdev->qts_ch = mhi_dev;
+	dev_set_drvdata(&mhi_dev->dev, qdev);
+
+	ret = qaic_boot_timesync_queue_resp(mhi_dev, qdev);
+	if (ret) {
+		dev_set_drvdata(&mhi_dev->dev, NULL);
+		qdev->qts_ch = NULL;
+		mhi_unprepare_from_transfer(mhi_dev);
+	}
+
+	return ret;
+}
+
+static void qaic_boot_timesync_ul_xfer_cb(struct mhi_device *mhi_dev, struct mhi_result *mhi_result)
+{
+	kfree(mhi_result->buf_addr);
+}
+
+static void qaic_boot_timesync_dl_xfer_cb(struct mhi_device *mhi_dev, struct mhi_result *mhi_result)
+{
+	struct qts_resp *resp = container_of(mhi_result->buf_addr, struct qts_resp, data);
+
+	if (mhi_result->transaction_status || mhi_result->bytes_xferd != sizeof(resp->data)) {
+		kfree(resp);
+		return;
+	}
+
+	queue_work(resp->qdev->qts_wq, &resp->work);
+}
+
+static const struct mhi_device_id qaic_boot_timesync_match_table[] = {
+	{ .chan = "QAIC_TIMESYNC"},
+	{},
+};
+
+static struct mhi_driver qaic_boot_timesync_driver = {
+	.id_table = qaic_boot_timesync_match_table,
+	.remove = qaic_boot_timesync_remove,
+	.probe = qaic_boot_timesync_probe,
+	.ul_xfer_cb = qaic_boot_timesync_ul_xfer_cb,
+	.dl_xfer_cb = qaic_boot_timesync_dl_xfer_cb,
+	.driver = {
+		.name = "qaic_timesync",
+	},
+};
+
+int qaic_timesync_init(void)
+{
+	int ret;
+
+	ret = mhi_driver_register(&qaic_timesync_driver);
+	if (ret)
+		return ret;
+	ret = mhi_driver_register(&qaic_boot_timesync_driver);
+
+	return ret;
+}
+
+void qaic_timesync_deinit(void)
+{
+	mhi_driver_unregister(&qaic_boot_timesync_driver);
+	mhi_driver_unregister(&qaic_timesync_driver);
+}
diff --git a/drivers/accel/qaic/qaic_timesync.h b/drivers/accel/qaic/qaic_timesync.h
new file mode 100644
index 000000000000..77b9c2b55057
--- /dev/null
+++ b/drivers/accel/qaic/qaic_timesync.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only
+ *
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef __QAIC_TIMESYNC_H__
+#define __QAIC_TIMESYNC_H__
+
+#include <linux/mhi.h>
+
+int qaic_timesync_init(void);
+void qaic_timesync_deinit(void);
+void qaic_mqts_ch_stop_timer(struct mhi_device *mhi_dev);
+#endif /* __QAIC_TIMESYNC_H__ */
diff --git a/drivers/accel/qaic/sahara.c b/drivers/accel/qaic/sahara.c
new file mode 100644
index 000000000000..fd3c3b2d1fd3
--- /dev/null
+++ b/drivers/accel/qaic/sahara.c
@@ -0,0 +1,935 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */
+
+#include <linux/devcoredump.h>
+#include <linux/firmware.h>
+#include <linux/limits.h>
+#include <linux/mhi.h>
+#include <linux/minmax.h>
+#include <linux/mod_devicetable.h>
+#include <linux/overflow.h>
+#include <linux/types.h>
+#include <linux/vmalloc.h>
+#include <linux/workqueue.h>
+
+#include "sahara.h"
+
+#define SAHARA_HELLO_CMD		0x1  /* Min protocol version 1.0 */
+#define SAHARA_HELLO_RESP_CMD		0x2  /* Min protocol version 1.0 */
+#define SAHARA_READ_DATA_CMD		0x3  /* Min protocol version 1.0 */
+#define SAHARA_END_OF_IMAGE_CMD		0x4  /* Min protocol version 1.0 */
+#define SAHARA_DONE_CMD			0x5  /* Min protocol version 1.0 */
+#define SAHARA_DONE_RESP_CMD		0x6  /* Min protocol version 1.0 */
+#define SAHARA_RESET_CMD		0x7  /* Min protocol version 1.0 */
+#define SAHARA_RESET_RESP_CMD		0x8  /* Min protocol version 1.0 */
+#define SAHARA_MEM_DEBUG_CMD		0x9  /* Min protocol version 2.0 */
+#define SAHARA_MEM_READ_CMD		0xa  /* Min protocol version 2.0 */
+#define SAHARA_CMD_READY_CMD		0xb  /* Min protocol version 2.1 */
+#define SAHARA_SWITCH_MODE_CMD		0xc  /* Min protocol version 2.1 */
+#define SAHARA_EXECUTE_CMD		0xd  /* Min protocol version 2.1 */
+#define SAHARA_EXECUTE_RESP_CMD		0xe  /* Min protocol version 2.1 */
+#define SAHARA_EXECUTE_DATA_CMD		0xf  /* Min protocol version 2.1 */
+#define SAHARA_MEM_DEBUG64_CMD		0x10 /* Min protocol version 2.5 */
+#define SAHARA_MEM_READ64_CMD		0x11 /* Min protocol version 2.5 */
+#define SAHARA_READ_DATA64_CMD		0x12 /* Min protocol version 2.8 */
+#define SAHARA_RESET_STATE_CMD		0x13 /* Min protocol version 2.9 */
+#define SAHARA_WRITE_DATA_CMD		0x14 /* Min protocol version 3.0 */
+
+#define SAHARA_PACKET_MAX_SIZE		0xffffU /* MHI_MAX_MTU */
+#define SAHARA_TRANSFER_MAX_SIZE	0x80000
+#define SAHARA_READ_MAX_SIZE		0xfff0U /* Avoid unaligned requests */
+#define SAHARA_NUM_TX_BUF		DIV_ROUND_UP(SAHARA_TRANSFER_MAX_SIZE,\
+							SAHARA_PACKET_MAX_SIZE)
+#define SAHARA_IMAGE_ID_NONE		U32_MAX
+
+#define SAHARA_VERSION			2
+#define SAHARA_SUCCESS			0
+#define SAHARA_TABLE_ENTRY_STR_LEN	20
+
+#define SAHARA_MODE_IMAGE_TX_PENDING	0x0
+#define SAHARA_MODE_IMAGE_TX_COMPLETE	0x1
+#define SAHARA_MODE_MEMORY_DEBUG	0x2
+#define SAHARA_MODE_COMMAND		0x3
+
+#define SAHARA_HELLO_LENGTH		0x30
+#define SAHARA_READ_DATA_LENGTH		0x14
+#define SAHARA_END_OF_IMAGE_LENGTH	0x10
+#define SAHARA_DONE_LENGTH		0x8
+#define SAHARA_RESET_LENGTH		0x8
+#define SAHARA_MEM_DEBUG64_LENGTH	0x18
+#define SAHARA_MEM_READ64_LENGTH	0x18
+
+struct sahara_packet {
+	__le32 cmd;
+	__le32 length;
+
+	union {
+		struct {
+			__le32 version;
+			__le32 version_compat;
+			__le32 max_length;
+			__le32 mode;
+		} hello;
+		struct {
+			__le32 version;
+			__le32 version_compat;
+			__le32 status;
+			__le32 mode;
+		} hello_resp;
+		struct {
+			__le32 image;
+			__le32 offset;
+			__le32 length;
+		} read_data;
+		struct {
+			__le32 image;
+			__le32 status;
+		} end_of_image;
+		struct {
+			__le64 table_address;
+			__le64 table_length;
+		} memory_debug64;
+		struct {
+			__le64 memory_address;
+			__le64 memory_length;
+		} memory_read64;
+	};
+};
+
+struct sahara_debug_table_entry64 {
+	__le64	type;
+	__le64	address;
+	__le64	length;
+	char	description[SAHARA_TABLE_ENTRY_STR_LEN];
+	char	filename[SAHARA_TABLE_ENTRY_STR_LEN];
+};
+
+struct sahara_dump_table_entry {
+	u64	type;
+	u64	address;
+	u64	length;
+	char	description[SAHARA_TABLE_ENTRY_STR_LEN];
+	char	filename[SAHARA_TABLE_ENTRY_STR_LEN];
+};
+
+#define SAHARA_DUMP_V1_MAGIC 0x1234567890abcdef
+#define SAHARA_DUMP_V1_VER   1
+struct sahara_memory_dump_meta_v1 {
+	u64	magic;
+	u64	version;
+	u64	dump_size;
+	u64	table_size;
+};
+
+/*
+ * Layout of crashdump provided to user via devcoredump
+ *              +------------------------------------------+
+ *              |         Crashdump Meta structure         |
+ *              | type: struct sahara_memory_dump_meta_v1  |
+ *              +------------------------------------------+
+ *              |             Crashdump Table              |
+ *              | type: array of struct                    |
+ *              |       sahara_dump_table_entry            |
+ *              |                                          |
+ *              |                                          |
+ *              +------------------------------------------+
+ *              |                Crashdump                 |
+ *              |                                          |
+ *              |                                          |
+ *              |                                          |
+ *              |                                          |
+ *              |                                          |
+ *              +------------------------------------------+
+ *
+ * First is the metadata header. Userspace can use the magic number to verify
+ * the content type, and then check the version for the rest of the format.
+ * New versions should keep the magic number location/value, and version
+ * location, but increment the version value.
+ *
+ * For v1, the metadata lists the size of the entire dump (header + table +
+ * dump) and the size of the table. Then the dump image table, which describes
+ * the contents of the dump. Finally all the images are listed in order, with
+ * no deadspace in between. Userspace can use the sizes listed in the image
+ * table to reconstruct the individual images.
+ */
+
+struct sahara_context {
+	struct sahara_packet		*tx[SAHARA_NUM_TX_BUF];
+	struct sahara_packet		*rx;
+	struct work_struct		fw_work;
+	struct work_struct		dump_work;
+	struct work_struct		read_data_work;
+	struct mhi_device		*mhi_dev;
+	const char * const		*image_table;
+	u32				table_size;
+	u32				active_image_id;
+	const struct firmware		*firmware;
+	u64				dump_table_address;
+	u64				dump_table_length;
+	size_t				rx_size;
+	size_t				rx_size_requested;
+	void				*mem_dump;
+	size_t				mem_dump_sz;
+	struct sahara_dump_table_entry	*dump_image;
+	u64				dump_image_offset;
+	void				*mem_dump_freespace;
+	u64				dump_images_left;
+	u32				read_data_offset;
+	u32				read_data_length;
+	bool				is_mem_dump_mode;
+	bool				non_streaming;
+};
+
+static const char * const aic100_image_table[] = {
+	[1]  = "qcom/aic100/fw1.bin",
+	[2]  = "qcom/aic100/fw2.bin",
+	[4]  = "qcom/aic100/fw4.bin",
+	[5]  = "qcom/aic100/fw5.bin",
+	[6]  = "qcom/aic100/fw6.bin",
+	[8]  = "qcom/aic100/fw8.bin",
+	[9]  = "qcom/aic100/fw9.bin",
+	[10] = "qcom/aic100/fw10.bin",
+};
+
+static const char * const aic200_image_table[] = {
+	[5]  = "qcom/aic200/uefi.elf",
+	[12] = "qcom/aic200/aic200-nsp.bin",
+	[23] = "qcom/aic200/aop.mbn",
+	[32] = "qcom/aic200/tz.mbn",
+	[33] = "qcom/aic200/hypvm.mbn",
+	[38] = "qcom/aic200/xbl_config.elf",
+	[39] = "qcom/aic200/aic200_abl.elf",
+	[40] = "qcom/aic200/apdp.mbn",
+	[41] = "qcom/aic200/devcfg.mbn",
+	[42] = "qcom/aic200/sec.elf",
+	[43] = "qcom/aic200/aic200-hlos.elf",
+	[49] = "qcom/aic200/shrm.elf",
+	[50] = "qcom/aic200/cpucp.elf",
+	[51] = "qcom/aic200/aop_devcfg.mbn",
+	[54] = "qcom/aic200/qupv3fw.elf",
+	[57] = "qcom/aic200/cpucp_dtbs.elf",
+	[62] = "qcom/aic200/uefi_dtbs.elf",
+	[63] = "qcom/aic200/xbl_ac_config.mbn",
+	[64] = "qcom/aic200/tz_ac_config.mbn",
+	[65] = "qcom/aic200/hyp_ac_config.mbn",
+	[66] = "qcom/aic200/pdp.elf",
+	[67] = "qcom/aic200/pdp_cdb.elf",
+	[68] = "qcom/aic200/sdi.mbn",
+	[69] = "qcom/aic200/dcd.mbn",
+	[73] = "qcom/aic200/gearvm.mbn",
+	[74] = "qcom/aic200/sti.bin",
+	[76] = "qcom/aic200/tz_qti_config.mbn",
+	[78] = "qcom/aic200/pvs.bin",
+};
+
+static bool is_streaming(struct sahara_context *context)
+{
+	return !context->non_streaming;
+}
+
+static int sahara_find_image(struct sahara_context *context, u32 image_id)
+{
+	int ret;
+
+	if (image_id == context->active_image_id)
+		return 0;
+
+	if (context->active_image_id != SAHARA_IMAGE_ID_NONE) {
+		dev_err(&context->mhi_dev->dev, "image id %d is not valid as %d is active\n",
+			image_id, context->active_image_id);
+		return -EINVAL;
+	}
+
+	if (image_id >= context->table_size || !context->image_table[image_id]) {
+		dev_err(&context->mhi_dev->dev, "request for unknown image: %d\n", image_id);
+		return -EINVAL;
+	}
+
+	/*
+	 * This image might be optional. The device may continue without it.
+	 * Only the device knows. Suppress error messages that could suggest an
+	 * a problem when we were actually able to continue.
+	 */
+	ret = firmware_request_nowarn(&context->firmware,
+				      context->image_table[image_id],
+				      &context->mhi_dev->dev);
+	if (ret) {
+		dev_dbg(&context->mhi_dev->dev, "request for image id %d / file %s failed %d\n",
+			image_id, context->image_table[image_id], ret);
+		return ret;
+	}
+
+	context->active_image_id = image_id;
+
+	return 0;
+}
+
+static void sahara_release_image(struct sahara_context *context)
+{
+	if (context->active_image_id != SAHARA_IMAGE_ID_NONE)
+		release_firmware(context->firmware);
+	context->active_image_id = SAHARA_IMAGE_ID_NONE;
+}
+
+static void sahara_send_reset(struct sahara_context *context)
+{
+	int ret;
+
+	context->is_mem_dump_mode = false;
+	context->read_data_offset = 0;
+	context->read_data_length = 0;
+
+	context->tx[0]->cmd = cpu_to_le32(SAHARA_RESET_CMD);
+	context->tx[0]->length = cpu_to_le32(SAHARA_RESET_LENGTH);
+
+	ret = mhi_queue_buf(context->mhi_dev, DMA_TO_DEVICE, context->tx[0],
+			    SAHARA_RESET_LENGTH, MHI_EOT);
+	if (ret)
+		dev_err(&context->mhi_dev->dev, "Unable to send reset response %d\n", ret);
+}
+
+static void sahara_hello(struct sahara_context *context)
+{
+	int ret;
+
+	dev_dbg(&context->mhi_dev->dev,
+		"HELLO cmd received. length:%d version:%d version_compat:%d max_length:%d mode:%d\n",
+		le32_to_cpu(context->rx->length),
+		le32_to_cpu(context->rx->hello.version),
+		le32_to_cpu(context->rx->hello.version_compat),
+		le32_to_cpu(context->rx->hello.max_length),
+		le32_to_cpu(context->rx->hello.mode));
+
+	if (le32_to_cpu(context->rx->length) != SAHARA_HELLO_LENGTH) {
+		dev_err(&context->mhi_dev->dev, "Malformed hello packet - length %d\n",
+			le32_to_cpu(context->rx->length));
+		return;
+	}
+	if (le32_to_cpu(context->rx->hello.version) != SAHARA_VERSION) {
+		dev_err(&context->mhi_dev->dev, "Unsupported hello packet - version %d\n",
+			le32_to_cpu(context->rx->hello.version));
+		return;
+	}
+
+	if (le32_to_cpu(context->rx->hello.mode) != SAHARA_MODE_IMAGE_TX_PENDING &&
+	    le32_to_cpu(context->rx->hello.mode) != SAHARA_MODE_IMAGE_TX_COMPLETE &&
+	    le32_to_cpu(context->rx->hello.mode) != SAHARA_MODE_MEMORY_DEBUG) {
+		dev_err(&context->mhi_dev->dev, "Unsupported hello packet - mode %d\n",
+			le32_to_cpu(context->rx->hello.mode));
+		return;
+	}
+
+	context->tx[0]->cmd = cpu_to_le32(SAHARA_HELLO_RESP_CMD);
+	context->tx[0]->length = cpu_to_le32(SAHARA_HELLO_LENGTH);
+	context->tx[0]->hello_resp.version = cpu_to_le32(SAHARA_VERSION);
+	context->tx[0]->hello_resp.version_compat = cpu_to_le32(SAHARA_VERSION);
+	context->tx[0]->hello_resp.status = cpu_to_le32(SAHARA_SUCCESS);
+	context->tx[0]->hello_resp.mode = context->rx->hello_resp.mode;
+
+	ret = mhi_queue_buf(context->mhi_dev, DMA_TO_DEVICE, context->tx[0],
+			    SAHARA_HELLO_LENGTH, MHI_EOT);
+	if (ret)
+		dev_err(&context->mhi_dev->dev, "Unable to send hello response %d\n", ret);
+}
+
+static int read_data_helper(struct sahara_context *context, int buf_index)
+{
+	enum mhi_flags mhi_flag;
+	u32 pkt_data_len;
+	int ret;
+
+	pkt_data_len = min(context->read_data_length, SAHARA_PACKET_MAX_SIZE);
+
+	memcpy(context->tx[buf_index],
+	       &context->firmware->data[context->read_data_offset],
+	       pkt_data_len);
+
+	context->read_data_offset += pkt_data_len;
+	context->read_data_length -= pkt_data_len;
+
+	if (is_streaming(context) || !context->read_data_length)
+		mhi_flag = MHI_EOT;
+	else
+		mhi_flag = MHI_CHAIN;
+
+	ret = mhi_queue_buf(context->mhi_dev, DMA_TO_DEVICE,
+			    context->tx[buf_index], pkt_data_len, mhi_flag);
+	if (ret) {
+		dev_err(&context->mhi_dev->dev, "Unable to send read_data response %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static void sahara_read_data(struct sahara_context *context)
+{
+	u32 image_id, data_offset, data_len;
+	int ret;
+	int i;
+
+	dev_dbg(&context->mhi_dev->dev,
+		"READ_DATA cmd received. length:%d image:%d offset:%d data_length:%d\n",
+		le32_to_cpu(context->rx->length),
+		le32_to_cpu(context->rx->read_data.image),
+		le32_to_cpu(context->rx->read_data.offset),
+		le32_to_cpu(context->rx->read_data.length));
+
+	if (le32_to_cpu(context->rx->length) != SAHARA_READ_DATA_LENGTH) {
+		dev_err(&context->mhi_dev->dev, "Malformed read_data packet - length %d\n",
+			le32_to_cpu(context->rx->length));
+		return;
+	}
+
+	image_id = le32_to_cpu(context->rx->read_data.image);
+	data_offset = le32_to_cpu(context->rx->read_data.offset);
+	data_len = le32_to_cpu(context->rx->read_data.length);
+
+	ret = sahara_find_image(context, image_id);
+	if (ret) {
+		sahara_send_reset(context);
+		return;
+	}
+
+	/*
+	 * Image is released when the device is done with it via
+	 * SAHARA_END_OF_IMAGE_CMD. sahara_send_reset() will either cause the
+	 * device to retry the operation with a modification, or decide to be
+	 * done with the image and trigger SAHARA_END_OF_IMAGE_CMD.
+	 * release_image() is called from SAHARA_END_OF_IMAGE_CMD. processing
+	 * and is not needed here on error.
+	 */
+
+	if (context->non_streaming && data_len > SAHARA_TRANSFER_MAX_SIZE) {
+		dev_err(&context->mhi_dev->dev, "Malformed read_data packet - data len %d exceeds max xfer size %d\n",
+			data_len, SAHARA_TRANSFER_MAX_SIZE);
+		sahara_send_reset(context);
+		return;
+	}
+
+	if (data_offset >= context->firmware->size) {
+		dev_err(&context->mhi_dev->dev, "Malformed read_data packet - data offset %d exceeds file size %zu\n",
+			data_offset, context->firmware->size);
+		sahara_send_reset(context);
+		return;
+	}
+
+	if (size_add(data_offset, data_len) > context->firmware->size) {
+		dev_err(&context->mhi_dev->dev, "Malformed read_data packet - data offset %d and length %d exceeds file size %zu\n",
+			data_offset, data_len, context->firmware->size);
+		sahara_send_reset(context);
+		return;
+	}
+
+	context->read_data_offset = data_offset;
+	context->read_data_length = data_len;
+
+	if (is_streaming(context)) {
+		schedule_work(&context->read_data_work);
+		return;
+	}
+
+	for (i = 0; i < SAHARA_NUM_TX_BUF && context->read_data_length; ++i) {
+		ret = read_data_helper(context, i);
+		if (ret)
+			break;
+	}
+}
+
+static void sahara_end_of_image(struct sahara_context *context)
+{
+	int ret;
+
+	dev_dbg(&context->mhi_dev->dev,
+		"END_OF_IMAGE cmd received. length:%d image:%d status:%d\n",
+		le32_to_cpu(context->rx->length),
+		le32_to_cpu(context->rx->end_of_image.image),
+		le32_to_cpu(context->rx->end_of_image.status));
+
+	if (le32_to_cpu(context->rx->length) != SAHARA_END_OF_IMAGE_LENGTH) {
+		dev_err(&context->mhi_dev->dev, "Malformed end_of_image packet - length %d\n",
+			le32_to_cpu(context->rx->length));
+		return;
+	}
+
+	if (context->active_image_id != SAHARA_IMAGE_ID_NONE &&
+	    le32_to_cpu(context->rx->end_of_image.image) != context->active_image_id) {
+		dev_err(&context->mhi_dev->dev, "Malformed end_of_image packet - image %d is not the active image\n",
+			le32_to_cpu(context->rx->end_of_image.image));
+		return;
+	}
+
+	sahara_release_image(context);
+
+	if (le32_to_cpu(context->rx->end_of_image.status))
+		return;
+
+	context->tx[0]->cmd = cpu_to_le32(SAHARA_DONE_CMD);
+	context->tx[0]->length = cpu_to_le32(SAHARA_DONE_LENGTH);
+
+	ret = mhi_queue_buf(context->mhi_dev, DMA_TO_DEVICE, context->tx[0],
+			    SAHARA_DONE_LENGTH, MHI_EOT);
+	if (ret)
+		dev_dbg(&context->mhi_dev->dev, "Unable to send done response %d\n", ret);
+}
+
+static void sahara_memory_debug64(struct sahara_context *context)
+{
+	int ret;
+
+	dev_dbg(&context->mhi_dev->dev,
+		"MEMORY DEBUG64 cmd received. length:%d table_address:%#llx table_length:%#llx\n",
+		le32_to_cpu(context->rx->length),
+		le64_to_cpu(context->rx->memory_debug64.table_address),
+		le64_to_cpu(context->rx->memory_debug64.table_length));
+
+	if (le32_to_cpu(context->rx->length) != SAHARA_MEM_DEBUG64_LENGTH) {
+		dev_err(&context->mhi_dev->dev, "Malformed memory debug64 packet - length %d\n",
+			le32_to_cpu(context->rx->length));
+		return;
+	}
+
+	context->dump_table_address = le64_to_cpu(context->rx->memory_debug64.table_address);
+	context->dump_table_length = le64_to_cpu(context->rx->memory_debug64.table_length);
+
+	if (context->dump_table_length % sizeof(struct sahara_debug_table_entry64) != 0 ||
+	    !context->dump_table_length) {
+		dev_err(&context->mhi_dev->dev, "Malformed memory debug64 packet - table length %lld\n",
+			context->dump_table_length);
+		return;
+	}
+
+	/*
+	 * From this point, the protocol flips. We make memory_read requests to
+	 * the device, and the device responds with the raw data. If the device
+	 * has an error, it will send an End of Image command. First we need to
+	 * request the memory dump table so that we know where all the pieces
+	 * of the dump are that we can consume.
+	 */
+
+	context->is_mem_dump_mode = true;
+
+	/*
+	 * Assume that the table is smaller than our MTU so that we can read it
+	 * in one shot. The spec does not put an upper limit on the table, but
+	 * no known device will exceed this.
+	 */
+	if (context->dump_table_length > SAHARA_PACKET_MAX_SIZE) {
+		dev_err(&context->mhi_dev->dev, "Memory dump table length %lld exceeds supported size. Discarding dump\n",
+			context->dump_table_length);
+		sahara_send_reset(context);
+		return;
+	}
+
+	context->tx[0]->cmd = cpu_to_le32(SAHARA_MEM_READ64_CMD);
+	context->tx[0]->length = cpu_to_le32(SAHARA_MEM_READ64_LENGTH);
+	context->tx[0]->memory_read64.memory_address = cpu_to_le64(context->dump_table_address);
+	context->tx[0]->memory_read64.memory_length = cpu_to_le64(context->dump_table_length);
+
+	context->rx_size_requested = context->dump_table_length;
+
+	ret = mhi_queue_buf(context->mhi_dev, DMA_TO_DEVICE, context->tx[0],
+			    SAHARA_MEM_READ64_LENGTH, MHI_EOT);
+	if (ret)
+		dev_err(&context->mhi_dev->dev, "Unable to send read for dump table %d\n", ret);
+}
+
+static void sahara_processing(struct work_struct *work)
+{
+	struct sahara_context *context = container_of(work, struct sahara_context, fw_work);
+	int ret;
+
+	switch (le32_to_cpu(context->rx->cmd)) {
+	case SAHARA_HELLO_CMD:
+		sahara_hello(context);
+		break;
+	case SAHARA_READ_DATA_CMD:
+		sahara_read_data(context);
+		break;
+	case SAHARA_END_OF_IMAGE_CMD:
+		sahara_end_of_image(context);
+		break;
+	case SAHARA_DONE_RESP_CMD:
+		/* Intentional do nothing as we don't need to exit an app */
+		break;
+	case SAHARA_RESET_RESP_CMD:
+		/* Intentional do nothing as we don't need to exit an app */
+		break;
+	case SAHARA_MEM_DEBUG64_CMD:
+		sahara_memory_debug64(context);
+		break;
+	default:
+		dev_err(&context->mhi_dev->dev, "Unknown command %d\n",
+			le32_to_cpu(context->rx->cmd));
+		break;
+	}
+
+	ret = mhi_queue_buf(context->mhi_dev, DMA_FROM_DEVICE, context->rx,
+			    SAHARA_PACKET_MAX_SIZE, MHI_EOT);
+	if (ret)
+		dev_err(&context->mhi_dev->dev, "Unable to requeue rx buf %d\n", ret);
+}
+
+static void sahara_parse_dump_table(struct sahara_context *context)
+{
+	struct sahara_dump_table_entry *image_out_table;
+	struct sahara_debug_table_entry64 *dev_table;
+	struct sahara_memory_dump_meta_v1 *dump_meta;
+	u64 table_nents;
+	u64 dump_length;
+	u64 mul_bytes;
+	int ret;
+	u64 i;
+
+	table_nents = context->dump_table_length / sizeof(*dev_table);
+	context->dump_images_left = table_nents;
+	dump_length = 0;
+
+	dev_table = (struct sahara_debug_table_entry64 *)(context->rx);
+	for (i = 0; i < table_nents; ++i) {
+		/* Do not trust the device, ensure the strings are terminated */
+		dev_table[i].description[SAHARA_TABLE_ENTRY_STR_LEN - 1] = 0;
+		dev_table[i].filename[SAHARA_TABLE_ENTRY_STR_LEN - 1] = 0;
+
+		if (check_add_overflow(dump_length,
+				       le64_to_cpu(dev_table[i].length),
+				       &dump_length)) {
+			/* Discard the dump */
+			sahara_send_reset(context);
+			return;
+		}
+
+		dev_dbg(&context->mhi_dev->dev,
+			"Memory dump table entry %lld type: %lld address: %#llx length: %#llx description: \"%s\" filename \"%s\"\n",
+			i,
+			le64_to_cpu(dev_table[i].type),
+			le64_to_cpu(dev_table[i].address),
+			le64_to_cpu(dev_table[i].length),
+			dev_table[i].description,
+			dev_table[i].filename);
+	}
+
+	if (check_add_overflow(dump_length, (u64)sizeof(*dump_meta), &dump_length)) {
+		/* Discard the dump */
+		sahara_send_reset(context);
+		return;
+	}
+	if (check_mul_overflow((u64)sizeof(*image_out_table), table_nents, &mul_bytes)) {
+		/* Discard the dump */
+		sahara_send_reset(context);
+		return;
+	}
+	if (check_add_overflow(dump_length, mul_bytes, &dump_length)) {
+		/* Discard the dump */
+		sahara_send_reset(context);
+		return;
+	}
+
+	context->mem_dump_sz = dump_length;
+	context->mem_dump = vzalloc(dump_length);
+	if (!context->mem_dump) {
+		/* Discard the dump */
+		sahara_send_reset(context);
+		return;
+	}
+
+	/* Populate the dump metadata and table for userspace */
+	dump_meta = context->mem_dump;
+	dump_meta->magic = SAHARA_DUMP_V1_MAGIC;
+	dump_meta->version = SAHARA_DUMP_V1_VER;
+	dump_meta->dump_size = dump_length;
+	dump_meta->table_size = context->dump_table_length;
+
+	image_out_table = context->mem_dump + sizeof(*dump_meta);
+	for (i = 0; i < table_nents; ++i) {
+		image_out_table[i].type = le64_to_cpu(dev_table[i].type);
+		image_out_table[i].address = le64_to_cpu(dev_table[i].address);
+		image_out_table[i].length = le64_to_cpu(dev_table[i].length);
+		strscpy(image_out_table[i].description, dev_table[i].description,
+			SAHARA_TABLE_ENTRY_STR_LEN);
+		strscpy(image_out_table[i].filename,
+			dev_table[i].filename,
+			SAHARA_TABLE_ENTRY_STR_LEN);
+	}
+
+	context->mem_dump_freespace = &image_out_table[i];
+
+	/* Done parsing the table, switch to image dump mode */
+	context->dump_table_length = 0;
+
+	/* Request the first chunk of the first image */
+	context->dump_image = &image_out_table[0];
+	dump_length = min_t(u64, context->dump_image->length, SAHARA_READ_MAX_SIZE);
+	/* Avoid requesting EOI sized data so that we can identify errors */
+	if (dump_length == SAHARA_END_OF_IMAGE_LENGTH)
+		dump_length = SAHARA_END_OF_IMAGE_LENGTH / 2;
+
+	context->dump_image_offset = dump_length;
+
+	context->tx[0]->cmd = cpu_to_le32(SAHARA_MEM_READ64_CMD);
+	context->tx[0]->length = cpu_to_le32(SAHARA_MEM_READ64_LENGTH);
+	context->tx[0]->memory_read64.memory_address = cpu_to_le64(context->dump_image->address);
+	context->tx[0]->memory_read64.memory_length = cpu_to_le64(dump_length);
+
+	context->rx_size_requested = dump_length;
+
+	ret = mhi_queue_buf(context->mhi_dev, DMA_TO_DEVICE, context->tx[0],
+			    SAHARA_MEM_READ64_LENGTH, MHI_EOT);
+	if (ret)
+		dev_err(&context->mhi_dev->dev, "Unable to send read for dump content %d\n", ret);
+}
+
+static void sahara_parse_dump_image(struct sahara_context *context)
+{
+	u64 dump_length;
+	int ret;
+
+	memcpy(context->mem_dump_freespace, context->rx, context->rx_size);
+	context->mem_dump_freespace += context->rx_size;
+
+	if (context->dump_image_offset >= context->dump_image->length) {
+		/* Need to move to next image */
+		context->dump_image++;
+		context->dump_images_left--;
+		context->dump_image_offset = 0;
+
+		if (!context->dump_images_left) {
+			/* Dump done */
+			dev_coredumpv(context->mhi_dev->mhi_cntrl->cntrl_dev,
+				      context->mem_dump,
+				      context->mem_dump_sz,
+				      GFP_KERNEL);
+			context->mem_dump = NULL;
+			sahara_send_reset(context);
+			return;
+		}
+	}
+
+	/* Get next image chunk */
+	dump_length = context->dump_image->length - context->dump_image_offset;
+	dump_length = min_t(u64, dump_length, SAHARA_READ_MAX_SIZE);
+	/* Avoid requesting EOI sized data so that we can identify errors */
+	if (dump_length == SAHARA_END_OF_IMAGE_LENGTH)
+		dump_length = SAHARA_END_OF_IMAGE_LENGTH / 2;
+
+	context->tx[0]->cmd = cpu_to_le32(SAHARA_MEM_READ64_CMD);
+	context->tx[0]->length = cpu_to_le32(SAHARA_MEM_READ64_LENGTH);
+	context->tx[0]->memory_read64.memory_address =
+		cpu_to_le64(context->dump_image->address + context->dump_image_offset);
+	context->tx[0]->memory_read64.memory_length = cpu_to_le64(dump_length);
+
+	context->dump_image_offset += dump_length;
+	context->rx_size_requested = dump_length;
+
+	ret = mhi_queue_buf(context->mhi_dev, DMA_TO_DEVICE, context->tx[0],
+			    SAHARA_MEM_READ64_LENGTH, MHI_EOT);
+	if (ret)
+		dev_err(&context->mhi_dev->dev,
+			"Unable to send read for dump content %d\n", ret);
+}
+
+static void sahara_dump_processing(struct work_struct *work)
+{
+	struct sahara_context *context = container_of(work, struct sahara_context, dump_work);
+	int ret;
+
+	/*
+	 * We should get the expected raw data, but if the device has an error
+	 * it is supposed to send EOI with an error code.
+	 */
+	if (context->rx_size != context->rx_size_requested &&
+	    context->rx_size != SAHARA_END_OF_IMAGE_LENGTH) {
+		dev_err(&context->mhi_dev->dev,
+			"Unexpected response to read_data. Expected size: %#zx got: %#zx\n",
+			context->rx_size_requested,
+			context->rx_size);
+		goto error;
+	}
+
+	if (context->rx_size == SAHARA_END_OF_IMAGE_LENGTH &&
+	    le32_to_cpu(context->rx->cmd) == SAHARA_END_OF_IMAGE_CMD) {
+		dev_err(&context->mhi_dev->dev,
+			"Unexpected EOI response to read_data. Status: %d\n",
+			le32_to_cpu(context->rx->end_of_image.status));
+		goto error;
+	}
+
+	if (context->rx_size == SAHARA_END_OF_IMAGE_LENGTH &&
+	    le32_to_cpu(context->rx->cmd) != SAHARA_END_OF_IMAGE_CMD) {
+		dev_err(&context->mhi_dev->dev,
+			"Invalid EOI response to read_data. CMD: %d\n",
+			le32_to_cpu(context->rx->cmd));
+		goto error;
+	}
+
+	/*
+	 * Need to know if we received the dump table, or part of a dump image.
+	 * Since we get raw data, we cannot tell from the data itself. Instead,
+	 * we use the stored dump_table_length, which we zero after we read and
+	 * process the entire table.
+	 */
+	if (context->dump_table_length)
+		sahara_parse_dump_table(context);
+	else
+		sahara_parse_dump_image(context);
+
+	ret = mhi_queue_buf(context->mhi_dev, DMA_FROM_DEVICE, context->rx,
+			    SAHARA_PACKET_MAX_SIZE, MHI_EOT);
+	if (ret)
+		dev_err(&context->mhi_dev->dev, "Unable to requeue rx buf %d\n", ret);
+
+	return;
+
+error:
+	vfree(context->mem_dump);
+	context->mem_dump = NULL;
+	sahara_send_reset(context);
+}
+
+static void sahara_read_data_processing(struct work_struct *work)
+{
+	struct sahara_context *context = container_of(work, struct sahara_context, read_data_work);
+
+	read_data_helper(context, 0);
+}
+
+static int sahara_mhi_probe(struct mhi_device *mhi_dev, const struct mhi_device_id *id)
+{
+	struct sahara_context *context;
+	int ret;
+	int i;
+
+	context = devm_kzalloc(&mhi_dev->dev, sizeof(*context), GFP_KERNEL);
+	if (!context)
+		return -ENOMEM;
+
+	context->rx = devm_kzalloc(&mhi_dev->dev, SAHARA_PACKET_MAX_SIZE, GFP_KERNEL);
+	if (!context->rx)
+		return -ENOMEM;
+
+	if (!strcmp(mhi_dev->mhi_cntrl->name, "AIC200")) {
+		context->image_table = aic200_image_table;
+		context->table_size = ARRAY_SIZE(aic200_image_table);
+	} else {
+		context->image_table = aic100_image_table;
+		context->table_size = ARRAY_SIZE(aic100_image_table);
+		context->non_streaming = true;
+	}
+
+	/*
+	 * There are two firmware implementations for READ_DATA handling.
+	 * The older "SBL" implementation defines a Sahara transfer size, and
+	 * expects that the response is a single transport transfer. If the
+	 * FW wants to transfer a file that is larger than the transfer size,
+	 * the FW will issue multiple READ_DATA commands. For this
+	 * implementation, we need to allocate enough buffers to contain the
+	 * entire Sahara transfer size.
+	 *
+	 * The newer "XBL" implementation does not define a maximum transfer
+	 * size and instead expects the data to be streamed over using the
+	 * transport level MTU. The FW will issue a single READ_DATA command
+	 * of whatever size, and consume multiple transport level transfers
+	 * until the expected amount of data is consumed. For this
+	 * implementation we only need a single buffer of the transport MTU
+	 * but we'll need to be able to use it multiple times for a single
+	 * READ_DATA request.
+	 *
+	 * AIC100 is the SBL implementation and defines SAHARA_TRANSFER_MAX_SIZE
+	 * and we need 9x SAHARA_PACKET_MAX_SIZE to cover that. We can use
+	 * MHI_CHAIN to link multiple buffers into a single transfer but the
+	 * remote side will not consume the buffers until it sees an EOT, thus
+	 * we need to allocate enough buffers to put in the tx fifo to cover an
+	 * entire READ_DATA request of the max size.
+	 *
+	 * AIC200 is the XBL implementation, and so a single buffer will work.
+	 */
+	for (i = 0; i < SAHARA_NUM_TX_BUF; ++i) {
+		context->tx[i] = devm_kzalloc(&mhi_dev->dev,
+					      SAHARA_PACKET_MAX_SIZE,
+					      GFP_KERNEL);
+		if (!context->tx[i])
+			return -ENOMEM;
+		if (is_streaming(context))
+			break;
+	}
+
+	context->mhi_dev = mhi_dev;
+	INIT_WORK(&context->fw_work, sahara_processing);
+	INIT_WORK(&context->dump_work, sahara_dump_processing);
+	INIT_WORK(&context->read_data_work, sahara_read_data_processing);
+
+	context->active_image_id = SAHARA_IMAGE_ID_NONE;
+	dev_set_drvdata(&mhi_dev->dev, context);
+
+	ret = mhi_prepare_for_transfer(mhi_dev);
+	if (ret)
+		return ret;
+
+	ret = mhi_queue_buf(mhi_dev, DMA_FROM_DEVICE, context->rx, SAHARA_PACKET_MAX_SIZE, MHI_EOT);
+	if (ret) {
+		mhi_unprepare_from_transfer(mhi_dev);
+		return ret;
+	}
+
+	return 0;
+}
+
+static void sahara_mhi_remove(struct mhi_device *mhi_dev)
+{
+	struct sahara_context *context = dev_get_drvdata(&mhi_dev->dev);
+
+	cancel_work_sync(&context->fw_work);
+	cancel_work_sync(&context->dump_work);
+	vfree(context->mem_dump);
+	sahara_release_image(context);
+	mhi_unprepare_from_transfer(mhi_dev);
+}
+
+static void sahara_mhi_ul_xfer_cb(struct mhi_device *mhi_dev, struct mhi_result *mhi_result)
+{
+	struct sahara_context *context = dev_get_drvdata(&mhi_dev->dev);
+
+	if (!mhi_result->transaction_status && context->read_data_length && is_streaming(context))
+		schedule_work(&context->read_data_work);
+}
+
+static void sahara_mhi_dl_xfer_cb(struct mhi_device *mhi_dev, struct mhi_result *mhi_result)
+{
+	struct sahara_context *context = dev_get_drvdata(&mhi_dev->dev);
+
+	if (!mhi_result->transaction_status) {
+		context->rx_size = mhi_result->bytes_xferd;
+		if (context->is_mem_dump_mode)
+			schedule_work(&context->dump_work);
+		else
+			schedule_work(&context->fw_work);
+	}
+
+}
+
+static const struct mhi_device_id sahara_mhi_match_table[] = {
+	{ .chan = "QAIC_SAHARA", },
+	{},
+};
+
+static struct mhi_driver sahara_mhi_driver = {
+	.id_table = sahara_mhi_match_table,
+	.remove = sahara_mhi_remove,
+	.probe = sahara_mhi_probe,
+	.ul_xfer_cb = sahara_mhi_ul_xfer_cb,
+	.dl_xfer_cb = sahara_mhi_dl_xfer_cb,
+	.driver = {
+		.name = "sahara",
+	},
+};
+
+int sahara_register(void)
+{
+	return mhi_driver_register(&sahara_mhi_driver);
+}
+
+void sahara_unregister(void)
+{
+	mhi_driver_unregister(&sahara_mhi_driver);
+}
diff --git a/drivers/accel/qaic/sahara.h b/drivers/accel/qaic/sahara.h
new file mode 100644
index 000000000000..640208acc0d1
--- /dev/null
+++ b/drivers/accel/qaic/sahara.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */
+
+#ifndef __SAHARA_H__
+#define __SAHARA_H__
+
+int sahara_register(void);
+void sahara_unregister(void);
+#endif /* __SAHARA_H__ */
diff --git a/drivers/accel/rocket/Kconfig b/drivers/accel/rocket/Kconfig
new file mode 100644
index 000000000000..16465abe0660
--- /dev/null
+++ b/drivers/accel/rocket/Kconfig
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config DRM_ACCEL_ROCKET
+	tristate "Rocket (support for Rockchip NPUs)"
+	depends on DRM_ACCEL
+	depends on (ARCH_ROCKCHIP && ARM64) || COMPILE_TEST
+	depends on ROCKCHIP_IOMMU || COMPILE_TEST
+	depends on MMU
+	select DRM_SCHED
+	select DRM_GEM_SHMEM_HELPER
+	help
+	  Choose this option if you have a Rockchip SoC that contains a
+	  compatible Neural Processing Unit (NPU), such as the RK3588. Called by
+	  Rockchip either RKNN or RKNPU, it accelerates inference of neural
+	  networks.
+
+	  The interface exposed to userspace is described in
+	  include/uapi/drm/rocket_accel.h and is used by the Rocket userspace
+	  driver in Mesa3D.
+
+	  If unsure, say N.
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called rocket.
diff --git a/drivers/accel/rocket/Makefile b/drivers/accel/rocket/Makefile
new file mode 100644
index 000000000000..3713dfe223d6
--- /dev/null
+++ b/drivers/accel/rocket/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+obj-$(CONFIG_DRM_ACCEL_ROCKET) := rocket.o
+
+rocket-y := \
+	rocket_core.o \
+	rocket_device.o \
+	rocket_drv.o \
+	rocket_gem.o \
+	rocket_job.o
diff --git a/drivers/accel/rocket/rocket_core.c b/drivers/accel/rocket/rocket_core.c
new file mode 100644
index 000000000000..abe7719c1db4
--- /dev/null
+++ b/drivers/accel/rocket/rocket_core.c
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright 2024-2025 Tomeu Vizoso <tomeu@tomeuvizoso.net> */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/dev_printk.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/iommu.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+
+#include "rocket_core.h"
+#include "rocket_job.h"
+
+int rocket_core_init(struct rocket_core *core)
+{
+	struct device *dev = core->dev;
+	struct platform_device *pdev = to_platform_device(dev);
+	u32 version;
+	int err = 0;
+
+	core->resets[0].id = "srst_a";
+	core->resets[1].id = "srst_h";
+	err = devm_reset_control_bulk_get_exclusive(&pdev->dev, ARRAY_SIZE(core->resets),
+						    core->resets);
+	if (err)
+		return dev_err_probe(dev, err, "failed to get resets for core %d\n", core->index);
+
+	err = devm_clk_bulk_get(dev, ARRAY_SIZE(core->clks), core->clks);
+	if (err)
+		return dev_err_probe(dev, err, "failed to get clocks for core %d\n", core->index);
+
+	core->pc_iomem = devm_platform_ioremap_resource_byname(pdev, "pc");
+	if (IS_ERR(core->pc_iomem)) {
+		dev_err(dev, "couldn't find PC registers %ld\n", PTR_ERR(core->pc_iomem));
+		return PTR_ERR(core->pc_iomem);
+	}
+
+	core->cna_iomem = devm_platform_ioremap_resource_byname(pdev, "cna");
+	if (IS_ERR(core->cna_iomem)) {
+		dev_err(dev, "couldn't find CNA registers %ld\n", PTR_ERR(core->cna_iomem));
+		return PTR_ERR(core->cna_iomem);
+	}
+
+	core->core_iomem = devm_platform_ioremap_resource_byname(pdev, "core");
+	if (IS_ERR(core->core_iomem)) {
+		dev_err(dev, "couldn't find CORE registers %ld\n", PTR_ERR(core->core_iomem));
+		return PTR_ERR(core->core_iomem);
+	}
+
+	dma_set_max_seg_size(dev, UINT_MAX);
+
+	err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
+	if (err)
+		return err;
+
+	core->iommu_group = iommu_group_get(dev);
+
+	err = rocket_job_init(core);
+	if (err)
+		return err;
+
+	pm_runtime_use_autosuspend(dev);
+
+	/*
+	 * As this NPU will be most often used as part of a media pipeline that
+	 * ends presenting in a display, choose 50 ms (~3 frames at 60Hz) as an
+	 * autosuspend delay as that will keep the device powered up while the
+	 * pipeline is running.
+	 */
+	pm_runtime_set_autosuspend_delay(dev, 50);
+
+	pm_runtime_enable(dev);
+
+	err = pm_runtime_resume_and_get(dev);
+	if (err) {
+		rocket_job_fini(core);
+		return err;
+	}
+
+	version = rocket_pc_readl(core, VERSION);
+	version += rocket_pc_readl(core, VERSION_NUM) & 0xffff;
+
+	pm_runtime_mark_last_busy(dev);
+	pm_runtime_put_autosuspend(dev);
+
+	dev_info(dev, "Rockchip NPU core %d version: %d\n", core->index, version);
+
+	return 0;
+}
+
+void rocket_core_fini(struct rocket_core *core)
+{
+	pm_runtime_dont_use_autosuspend(core->dev);
+	pm_runtime_disable(core->dev);
+	iommu_group_put(core->iommu_group);
+	core->iommu_group = NULL;
+	rocket_job_fini(core);
+}
+
+void rocket_core_reset(struct rocket_core *core)
+{
+	reset_control_bulk_assert(ARRAY_SIZE(core->resets), core->resets);
+
+	udelay(10);
+
+	reset_control_bulk_deassert(ARRAY_SIZE(core->resets), core->resets);
+}
diff --git a/drivers/accel/rocket/rocket_core.h b/drivers/accel/rocket/rocket_core.h
new file mode 100644
index 000000000000..f6d7382854ca
--- /dev/null
+++ b/drivers/accel/rocket/rocket_core.h
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright 2024-2025 Tomeu Vizoso <tomeu@tomeuvizoso.net> */
+
+#ifndef __ROCKET_CORE_H__
+#define __ROCKET_CORE_H__
+
+#include <drm/gpu_scheduler.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/mutex_types.h>
+#include <linux/reset.h>
+
+#include "rocket_registers.h"
+
+#define rocket_pc_readl(core, reg) \
+	readl((core)->pc_iomem + (REG_PC_##reg))
+#define rocket_pc_writel(core, reg, value) \
+	writel(value, (core)->pc_iomem + (REG_PC_##reg))
+
+#define rocket_cna_readl(core, reg) \
+	readl((core)->cna_iomem + (REG_CNA_##reg) - REG_CNA_S_STATUS)
+#define rocket_cna_writel(core, reg, value) \
+	writel(value, (core)->cna_iomem + (REG_CNA_##reg) - REG_CNA_S_STATUS)
+
+#define rocket_core_readl(core, reg) \
+	readl((core)->core_iomem + (REG_CORE_##reg) - REG_CORE_S_STATUS)
+#define rocket_core_writel(core, reg, value) \
+	writel(value, (core)->core_iomem + (REG_CORE_##reg) - REG_CORE_S_STATUS)
+
+struct rocket_core {
+	struct device *dev;
+	struct rocket_device *rdev;
+	unsigned int index;
+
+	int irq;
+	void __iomem *pc_iomem;
+	void __iomem *cna_iomem;
+	void __iomem *core_iomem;
+	struct clk_bulk_data clks[4];
+	struct reset_control_bulk_data resets[2];
+
+	struct iommu_group *iommu_group;
+
+	struct mutex job_lock;
+	struct rocket_job *in_flight_job;
+
+	spinlock_t fence_lock;
+
+	struct {
+		struct workqueue_struct *wq;
+		struct work_struct work;
+		atomic_t pending;
+	} reset;
+
+	struct drm_gpu_scheduler sched;
+	u64 fence_context;
+	u64 emit_seqno;
+};
+
+int rocket_core_init(struct rocket_core *core);
+void rocket_core_fini(struct rocket_core *core);
+void rocket_core_reset(struct rocket_core *core);
+
+#endif
diff --git a/drivers/accel/rocket/rocket_device.c b/drivers/accel/rocket/rocket_device.c
new file mode 100644
index 000000000000..46e6ee1e72c5
--- /dev/null
+++ b/drivers/accel/rocket/rocket_device.c
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright 2024-2025 Tomeu Vizoso <tomeu@tomeuvizoso.net> */
+
+#include <drm/drm_drv.h>
+#include <linux/array_size.h>
+#include <linux/clk.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+
+#include "rocket_device.h"
+
+struct rocket_device *rocket_device_init(struct platform_device *pdev,
+					 const struct drm_driver *rocket_drm_driver)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *core_node;
+	struct rocket_device *rdev;
+	struct drm_device *ddev;
+	unsigned int num_cores = 0;
+	int err;
+
+	rdev = devm_drm_dev_alloc(dev, rocket_drm_driver, struct rocket_device, ddev);
+	if (IS_ERR(rdev))
+		return rdev;
+
+	ddev = &rdev->ddev;
+	dev_set_drvdata(dev, rdev);
+
+	for_each_compatible_node(core_node, NULL, "rockchip,rk3588-rknn-core")
+		if (of_device_is_available(core_node))
+			num_cores++;
+
+	rdev->cores = devm_kcalloc(dev, num_cores, sizeof(*rdev->cores), GFP_KERNEL);
+	if (!rdev->cores)
+		return ERR_PTR(-ENOMEM);
+
+	dma_set_max_seg_size(dev, UINT_MAX);
+
+	err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
+	if (err)
+		return ERR_PTR(err);
+
+	err = devm_mutex_init(dev, &rdev->sched_lock);
+	if (err)
+		return ERR_PTR(-ENOMEM);
+
+	err = drm_dev_register(ddev, 0);
+	if (err)
+		return ERR_PTR(err);
+
+	return rdev;
+}
+
+void rocket_device_fini(struct rocket_device *rdev)
+{
+	WARN_ON(rdev->num_cores > 0);
+
+	drm_dev_unregister(&rdev->ddev);
+}
diff --git a/drivers/accel/rocket/rocket_device.h b/drivers/accel/rocket/rocket_device.h
new file mode 100644
index 000000000000..ce662abc01d3
--- /dev/null
+++ b/drivers/accel/rocket/rocket_device.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright 2024-2025 Tomeu Vizoso <tomeu@tomeuvizoso.net> */
+
+#ifndef __ROCKET_DEVICE_H__
+#define __ROCKET_DEVICE_H__
+
+#include <drm/drm_device.h>
+#include <linux/clk.h>
+#include <linux/container_of.h>
+#include <linux/iommu.h>
+#include <linux/platform_device.h>
+
+#include "rocket_core.h"
+
+struct rocket_device {
+	struct drm_device ddev;
+
+	struct mutex sched_lock;
+
+	struct rocket_core *cores;
+	unsigned int num_cores;
+};
+
+struct rocket_device *rocket_device_init(struct platform_device *pdev,
+					 const struct drm_driver *rocket_drm_driver);
+void rocket_device_fini(struct rocket_device *rdev);
+#define to_rocket_device(drm_dev) \
+	((struct rocket_device *)(container_of((drm_dev), struct rocket_device, ddev)))
+
+#endif /* __ROCKET_DEVICE_H__ */
diff --git a/drivers/accel/rocket/rocket_drv.c b/drivers/accel/rocket/rocket_drv.c
new file mode 100644
index 000000000000..5c0b63f0a8f0
--- /dev/null
+++ b/drivers/accel/rocket/rocket_drv.c
@@ -0,0 +1,290 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright 2024-2025 Tomeu Vizoso <tomeu@tomeuvizoso.net> */
+
+#include <drm/drm_accel.h>
+#include <drm/drm_drv.h>
+#include <drm/drm_gem.h>
+#include <drm/drm_ioctl.h>
+#include <drm/rocket_accel.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/iommu.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+
+#include "rocket_drv.h"
+#include "rocket_gem.h"
+#include "rocket_job.h"
+
+/*
+ * Facade device, used to expose a single DRM device to userspace, that
+ * schedules jobs to any RKNN cores in the system.
+ */
+static struct platform_device *drm_dev;
+static struct rocket_device *rdev;
+
+static void
+rocket_iommu_domain_destroy(struct kref *kref)
+{
+	struct rocket_iommu_domain *domain = container_of(kref, struct rocket_iommu_domain, kref);
+
+	iommu_domain_free(domain->domain);
+	domain->domain = NULL;
+	kfree(domain);
+}
+
+static struct rocket_iommu_domain*
+rocket_iommu_domain_create(struct device *dev)
+{
+	struct rocket_iommu_domain *domain = kmalloc(sizeof(*domain), GFP_KERNEL);
+	void *err;
+
+	if (!domain)
+		return ERR_PTR(-ENOMEM);
+
+	domain->domain = iommu_paging_domain_alloc(dev);
+	if (IS_ERR(domain->domain)) {
+		err = ERR_CAST(domain->domain);
+		kfree(domain);
+		return err;
+	}
+	kref_init(&domain->kref);
+
+	return domain;
+}
+
+struct rocket_iommu_domain *
+rocket_iommu_domain_get(struct rocket_file_priv *rocket_priv)
+{
+	kref_get(&rocket_priv->domain->kref);
+	return rocket_priv->domain;
+}
+
+void
+rocket_iommu_domain_put(struct rocket_iommu_domain *domain)
+{
+	kref_put(&domain->kref, rocket_iommu_domain_destroy);
+}
+
+static int
+rocket_open(struct drm_device *dev, struct drm_file *file)
+{
+	struct rocket_device *rdev = to_rocket_device(dev);
+	struct rocket_file_priv *rocket_priv;
+	u64 start, end;
+	int ret;
+
+	if (!try_module_get(THIS_MODULE))
+		return -EINVAL;
+
+	rocket_priv = kzalloc(sizeof(*rocket_priv), GFP_KERNEL);
+	if (!rocket_priv) {
+		ret = -ENOMEM;
+		goto err_put_mod;
+	}
+
+	rocket_priv->rdev = rdev;
+	rocket_priv->domain = rocket_iommu_domain_create(rdev->cores[0].dev);
+	if (IS_ERR(rocket_priv->domain)) {
+		ret = PTR_ERR(rocket_priv->domain);
+		goto err_free;
+	}
+
+	file->driver_priv = rocket_priv;
+
+	start = rocket_priv->domain->domain->geometry.aperture_start;
+	end = rocket_priv->domain->domain->geometry.aperture_end;
+	drm_mm_init(&rocket_priv->mm, start, end - start + 1);
+	mutex_init(&rocket_priv->mm_lock);
+
+	ret = rocket_job_open(rocket_priv);
+	if (ret)
+		goto err_mm_takedown;
+
+	return 0;
+
+err_mm_takedown:
+	mutex_destroy(&rocket_priv->mm_lock);
+	drm_mm_takedown(&rocket_priv->mm);
+	rocket_iommu_domain_put(rocket_priv->domain);
+err_free:
+	kfree(rocket_priv);
+err_put_mod:
+	module_put(THIS_MODULE);
+	return ret;
+}
+
+static void
+rocket_postclose(struct drm_device *dev, struct drm_file *file)
+{
+	struct rocket_file_priv *rocket_priv = file->driver_priv;
+
+	rocket_job_close(rocket_priv);
+	mutex_destroy(&rocket_priv->mm_lock);
+	drm_mm_takedown(&rocket_priv->mm);
+	rocket_iommu_domain_put(rocket_priv->domain);
+	kfree(rocket_priv);
+	module_put(THIS_MODULE);
+}
+
+static const struct drm_ioctl_desc rocket_drm_driver_ioctls[] = {
+#define ROCKET_IOCTL(n, func) \
+	DRM_IOCTL_DEF_DRV(ROCKET_##n, rocket_ioctl_##func, 0)
+
+	ROCKET_IOCTL(CREATE_BO, create_bo),
+	ROCKET_IOCTL(SUBMIT, submit),
+	ROCKET_IOCTL(PREP_BO, prep_bo),
+	ROCKET_IOCTL(FINI_BO, fini_bo),
+};
+
+DEFINE_DRM_ACCEL_FOPS(rocket_accel_driver_fops);
+
+/*
+ * Rocket driver version:
+ * - 1.0 - initial interface
+ */
+static const struct drm_driver rocket_drm_driver = {
+	.driver_features	= DRIVER_COMPUTE_ACCEL | DRIVER_GEM,
+	.open			= rocket_open,
+	.postclose		= rocket_postclose,
+	.gem_create_object	= rocket_gem_create_object,
+	.ioctls			= rocket_drm_driver_ioctls,
+	.num_ioctls		= ARRAY_SIZE(rocket_drm_driver_ioctls),
+	.fops			= &rocket_accel_driver_fops,
+	.name			= "rocket",
+	.desc			= "rocket DRM",
+};
+
+static int rocket_probe(struct platform_device *pdev)
+{
+	if (rdev == NULL) {
+		/* First core probing, initialize DRM device. */
+		rdev = rocket_device_init(drm_dev, &rocket_drm_driver);
+		if (IS_ERR(rdev)) {
+			dev_err(&pdev->dev, "failed to initialize rocket device\n");
+			return PTR_ERR(rdev);
+		}
+	}
+
+	unsigned int core = rdev->num_cores;
+
+	dev_set_drvdata(&pdev->dev, rdev);
+
+	rdev->cores[core].rdev = rdev;
+	rdev->cores[core].dev = &pdev->dev;
+	rdev->cores[core].index = core;
+
+	rdev->num_cores++;
+
+	return rocket_core_init(&rdev->cores[core]);
+}
+
+static void rocket_remove(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+
+	for (unsigned int core = 0; core < rdev->num_cores; core++) {
+		if (rdev->cores[core].dev == dev) {
+			rocket_core_fini(&rdev->cores[core]);
+			rdev->num_cores--;
+			break;
+		}
+	}
+
+	if (rdev->num_cores == 0) {
+		/* Last core removed, deinitialize DRM device. */
+		rocket_device_fini(rdev);
+		rdev = NULL;
+	}
+}
+
+static const struct of_device_id dt_match[] = {
+	{ .compatible = "rockchip,rk3588-rknn-core" },
+	{}
+};
+MODULE_DEVICE_TABLE(of, dt_match);
+
+static int find_core_for_dev(struct device *dev)
+{
+	struct rocket_device *rdev = dev_get_drvdata(dev);
+
+	for (unsigned int core = 0; core < rdev->num_cores; core++) {
+		if (dev == rdev->cores[core].dev)
+			return core;
+	}
+
+	return -1;
+}
+
+static int rocket_device_runtime_resume(struct device *dev)
+{
+	struct rocket_device *rdev = dev_get_drvdata(dev);
+	int core = find_core_for_dev(dev);
+	int err = 0;
+
+	if (core < 0)
+		return -ENODEV;
+
+	err = clk_bulk_prepare_enable(ARRAY_SIZE(rdev->cores[core].clks), rdev->cores[core].clks);
+	if (err) {
+		dev_err(dev, "failed to enable (%d) clocks for core %d\n", err, core);
+		return err;
+	}
+
+	return 0;
+}
+
+static int rocket_device_runtime_suspend(struct device *dev)
+{
+	struct rocket_device *rdev = dev_get_drvdata(dev);
+	int core = find_core_for_dev(dev);
+
+	if (core < 0)
+		return -ENODEV;
+
+	if (!rocket_job_is_idle(&rdev->cores[core]))
+		return -EBUSY;
+
+	clk_bulk_disable_unprepare(ARRAY_SIZE(rdev->cores[core].clks), rdev->cores[core].clks);
+
+	return 0;
+}
+
+EXPORT_GPL_DEV_PM_OPS(rocket_pm_ops) = {
+	RUNTIME_PM_OPS(rocket_device_runtime_suspend, rocket_device_runtime_resume, NULL)
+	SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
+};
+
+static struct platform_driver rocket_driver = {
+	.probe = rocket_probe,
+	.remove = rocket_remove,
+	.driver	 = {
+		.name = "rocket",
+		.pm = pm_ptr(&rocket_pm_ops),
+		.of_match_table = dt_match,
+	},
+};
+
+static int __init rocket_register(void)
+{
+	drm_dev = platform_device_register_simple("rknn", -1, NULL, 0);
+	if (IS_ERR(drm_dev))
+		return PTR_ERR(drm_dev);
+
+	return platform_driver_register(&rocket_driver);
+}
+
+static void __exit rocket_unregister(void)
+{
+	platform_driver_unregister(&rocket_driver);
+
+	platform_device_unregister(drm_dev);
+}
+
+module_init(rocket_register);
+module_exit(rocket_unregister);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("DRM driver for the Rockchip NPU IP");
+MODULE_AUTHOR("Tomeu Vizoso");
diff --git a/drivers/accel/rocket/rocket_drv.h b/drivers/accel/rocket/rocket_drv.h
new file mode 100644
index 000000000000..2c673bb99ccc
--- /dev/null
+++ b/drivers/accel/rocket/rocket_drv.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright 2024-2025 Tomeu Vizoso <tomeu@tomeuvizoso.net> */
+
+#ifndef __ROCKET_DRV_H__
+#define __ROCKET_DRV_H__
+
+#include <drm/drm_mm.h>
+#include <drm/gpu_scheduler.h>
+
+#include "rocket_device.h"
+
+extern const struct dev_pm_ops rocket_pm_ops;
+
+struct rocket_iommu_domain {
+	struct iommu_domain *domain;
+	struct kref kref;
+};
+
+struct rocket_file_priv {
+	struct rocket_device *rdev;
+
+	struct rocket_iommu_domain *domain;
+	struct drm_mm mm;
+	struct mutex mm_lock;
+
+	struct drm_sched_entity sched_entity;
+};
+
+struct rocket_iommu_domain *rocket_iommu_domain_get(struct rocket_file_priv *rocket_priv);
+void rocket_iommu_domain_put(struct rocket_iommu_domain *domain);
+
+#endif
diff --git a/drivers/accel/rocket/rocket_gem.c b/drivers/accel/rocket/rocket_gem.c
new file mode 100644
index 000000000000..624c4ecf5a34
--- /dev/null
+++ b/drivers/accel/rocket/rocket_gem.c
@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright 2024-2025 Tomeu Vizoso <tomeu@tomeuvizoso.net> */
+
+#include <drm/drm_device.h>
+#include <drm/drm_print.h>
+#include <drm/drm_utils.h>
+#include <drm/rocket_accel.h>
+#include <linux/dma-mapping.h>
+#include <linux/iommu.h>
+
+#include "rocket_drv.h"
+#include "rocket_gem.h"
+
+static void rocket_gem_bo_free(struct drm_gem_object *obj)
+{
+	struct rocket_gem_object *bo = to_rocket_bo(obj);
+	struct rocket_file_priv *rocket_priv = bo->driver_priv;
+	size_t unmapped;
+
+	drm_WARN_ON(obj->dev, refcount_read(&bo->base.pages_use_count) > 1);
+
+	unmapped = iommu_unmap(bo->domain->domain, bo->mm.start, bo->size);
+	drm_WARN_ON(obj->dev, unmapped != bo->size);
+
+	mutex_lock(&rocket_priv->mm_lock);
+	drm_mm_remove_node(&bo->mm);
+	mutex_unlock(&rocket_priv->mm_lock);
+
+	rocket_iommu_domain_put(bo->domain);
+	bo->domain = NULL;
+
+	drm_gem_shmem_free(&bo->base);
+}
+
+static const struct drm_gem_object_funcs rocket_gem_funcs = {
+	.free = rocket_gem_bo_free,
+	.print_info = drm_gem_shmem_object_print_info,
+	.pin = drm_gem_shmem_object_pin,
+	.unpin = drm_gem_shmem_object_unpin,
+	.get_sg_table = drm_gem_shmem_object_get_sg_table,
+	.vmap = drm_gem_shmem_object_vmap,
+	.vunmap = drm_gem_shmem_object_vunmap,
+	.mmap = drm_gem_shmem_object_mmap,
+	.vm_ops = &drm_gem_shmem_vm_ops,
+};
+
+struct drm_gem_object *rocket_gem_create_object(struct drm_device *dev, size_t size)
+{
+	struct rocket_gem_object *obj;
+
+	obj = kzalloc(sizeof(*obj), GFP_KERNEL);
+	if (!obj)
+		return ERR_PTR(-ENOMEM);
+
+	obj->base.base.funcs = &rocket_gem_funcs;
+
+	return &obj->base.base;
+}
+
+int rocket_ioctl_create_bo(struct drm_device *dev, void *data, struct drm_file *file)
+{
+	struct rocket_file_priv *rocket_priv = file->driver_priv;
+	struct drm_rocket_create_bo *args = data;
+	struct drm_gem_shmem_object *shmem_obj;
+	struct rocket_gem_object *rkt_obj;
+	struct drm_gem_object *gem_obj;
+	struct sg_table *sgt;
+	int ret;
+
+	shmem_obj = drm_gem_shmem_create(dev, args->size);
+	if (IS_ERR(shmem_obj))
+		return PTR_ERR(shmem_obj);
+
+	gem_obj = &shmem_obj->base;
+	rkt_obj = to_rocket_bo(gem_obj);
+
+	rkt_obj->driver_priv = rocket_priv;
+	rkt_obj->domain = rocket_iommu_domain_get(rocket_priv);
+	rkt_obj->size = args->size;
+	rkt_obj->offset = 0;
+
+	ret = drm_gem_handle_create(file, gem_obj, &args->handle);
+	drm_gem_object_put(gem_obj);
+	if (ret)
+		goto err;
+
+	sgt = drm_gem_shmem_get_pages_sgt(shmem_obj);
+	if (IS_ERR(sgt)) {
+		ret = PTR_ERR(sgt);
+		goto err;
+	}
+
+	mutex_lock(&rocket_priv->mm_lock);
+	ret = drm_mm_insert_node_generic(&rocket_priv->mm, &rkt_obj->mm,
+					 rkt_obj->size, PAGE_SIZE,
+					 0, 0);
+	mutex_unlock(&rocket_priv->mm_lock);
+
+	ret = iommu_map_sgtable(rocket_priv->domain->domain,
+				rkt_obj->mm.start,
+				shmem_obj->sgt,
+				IOMMU_READ | IOMMU_WRITE);
+	if (ret < 0 || ret < args->size) {
+		drm_err(dev, "failed to map buffer: size=%d request_size=%u\n",
+			ret, args->size);
+		ret = -ENOMEM;
+		goto err_remove_node;
+	}
+
+	/* iommu_map_sgtable might have aligned the size */
+	rkt_obj->size = ret;
+	args->offset = drm_vma_node_offset_addr(&gem_obj->vma_node);
+	args->dma_address = rkt_obj->mm.start;
+
+	return 0;
+
+err_remove_node:
+	mutex_lock(&rocket_priv->mm_lock);
+	drm_mm_remove_node(&rkt_obj->mm);
+	mutex_unlock(&rocket_priv->mm_lock);
+
+err:
+	drm_gem_shmem_object_free(gem_obj);
+
+	return ret;
+}
+
+int rocket_ioctl_prep_bo(struct drm_device *dev, void *data, struct drm_file *file)
+{
+	struct drm_rocket_prep_bo *args = data;
+	unsigned long timeout = drm_timeout_abs_to_jiffies(args->timeout_ns);
+	struct drm_gem_object *gem_obj;
+	struct drm_gem_shmem_object *shmem_obj;
+	long ret = 0;
+
+	if (args->reserved != 0) {
+		drm_dbg(dev, "Reserved field in drm_rocket_prep_bo struct should be 0.\n");
+		return -EINVAL;
+	}
+
+	gem_obj = drm_gem_object_lookup(file, args->handle);
+	if (!gem_obj)
+		return -ENOENT;
+
+	ret = dma_resv_wait_timeout(gem_obj->resv, DMA_RESV_USAGE_WRITE, true, timeout);
+	if (!ret)
+		ret = timeout ? -ETIMEDOUT : -EBUSY;
+
+	shmem_obj = &to_rocket_bo(gem_obj)->base;
+
+	dma_sync_sgtable_for_cpu(dev->dev, shmem_obj->sgt, DMA_BIDIRECTIONAL);
+
+	drm_gem_object_put(gem_obj);
+
+	return ret;
+}
+
+int rocket_ioctl_fini_bo(struct drm_device *dev, void *data, struct drm_file *file)
+{
+	struct drm_rocket_fini_bo *args = data;
+	struct drm_gem_shmem_object *shmem_obj;
+	struct rocket_gem_object *rkt_obj;
+	struct drm_gem_object *gem_obj;
+
+	if (args->reserved != 0) {
+		drm_dbg(dev, "Reserved field in drm_rocket_fini_bo struct should be 0.\n");
+		return -EINVAL;
+	}
+
+	gem_obj = drm_gem_object_lookup(file, args->handle);
+	if (!gem_obj)
+		return -ENOENT;
+
+	rkt_obj = to_rocket_bo(gem_obj);
+	shmem_obj = &rkt_obj->base;
+
+	dma_sync_sgtable_for_device(dev->dev, shmem_obj->sgt, DMA_BIDIRECTIONAL);
+
+	drm_gem_object_put(gem_obj);
+
+	return 0;
+}
diff --git a/drivers/accel/rocket/rocket_gem.h b/drivers/accel/rocket/rocket_gem.h
new file mode 100644
index 000000000000..240430334509
--- /dev/null
+++ b/drivers/accel/rocket/rocket_gem.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright 2024-2025 Tomeu Vizoso <tomeu@tomeuvizoso.net> */
+
+#ifndef __ROCKET_GEM_H__
+#define __ROCKET_GEM_H__
+
+#include <drm/drm_gem_shmem_helper.h>
+
+struct rocket_gem_object {
+	struct drm_gem_shmem_object base;
+
+	struct rocket_file_priv *driver_priv;
+
+	struct rocket_iommu_domain *domain;
+	struct drm_mm_node mm;
+	size_t size;
+	u32 offset;
+};
+
+struct drm_gem_object *rocket_gem_create_object(struct drm_device *dev, size_t size);
+
+int rocket_ioctl_create_bo(struct drm_device *dev, void *data, struct drm_file *file);
+
+int rocket_ioctl_prep_bo(struct drm_device *dev, void *data, struct drm_file *file);
+
+int rocket_ioctl_fini_bo(struct drm_device *dev, void *data, struct drm_file *file);
+
+static inline
+struct  rocket_gem_object *to_rocket_bo(struct drm_gem_object *obj)
+{
+	return container_of(to_drm_gem_shmem_obj(obj), struct rocket_gem_object, base);
+}
+
+#endif
diff --git a/drivers/accel/rocket/rocket_job.c b/drivers/accel/rocket/rocket_job.c
new file mode 100644
index 000000000000..acd606160dc9
--- /dev/null
+++ b/drivers/accel/rocket/rocket_job.c
@@ -0,0 +1,637 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright 2019 Linaro, Ltd, Rob Herring <robh@kernel.org> */
+/* Copyright 2019 Collabora ltd. */
+/* Copyright 2024-2025 Tomeu Vizoso <tomeu@tomeuvizoso.net> */
+
+#include <drm/drm_print.h>
+#include <drm/drm_file.h>
+#include <drm/drm_gem.h>
+#include <drm/rocket_accel.h>
+#include <linux/interrupt.h>
+#include <linux/iommu.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+
+#include "rocket_core.h"
+#include "rocket_device.h"
+#include "rocket_drv.h"
+#include "rocket_job.h"
+#include "rocket_registers.h"
+
+#define JOB_TIMEOUT_MS 500
+
+static struct rocket_job *
+to_rocket_job(struct drm_sched_job *sched_job)
+{
+	return container_of(sched_job, struct rocket_job, base);
+}
+
+static const char *rocket_fence_get_driver_name(struct dma_fence *fence)
+{
+	return "rocket";
+}
+
+static const char *rocket_fence_get_timeline_name(struct dma_fence *fence)
+{
+	return "rockchip-npu";
+}
+
+static const struct dma_fence_ops rocket_fence_ops = {
+	.get_driver_name = rocket_fence_get_driver_name,
+	.get_timeline_name = rocket_fence_get_timeline_name,
+};
+
+static struct dma_fence *rocket_fence_create(struct rocket_core *core)
+{
+	struct dma_fence *fence;
+
+	fence = kzalloc(sizeof(*fence), GFP_KERNEL);
+	if (!fence)
+		return ERR_PTR(-ENOMEM);
+
+	dma_fence_init(fence, &rocket_fence_ops, &core->fence_lock,
+		       core->fence_context, ++core->emit_seqno);
+
+	return fence;
+}
+
+static int
+rocket_copy_tasks(struct drm_device *dev,
+		  struct drm_file *file_priv,
+		  struct drm_rocket_job *job,
+		  struct rocket_job *rjob)
+{
+	int ret = 0;
+
+	if (job->task_struct_size < sizeof(struct drm_rocket_task))
+		return -EINVAL;
+
+	rjob->task_count = job->task_count;
+
+	if (!rjob->task_count)
+		return 0;
+
+	rjob->tasks = kvmalloc_array(job->task_count, sizeof(*rjob->tasks), GFP_KERNEL);
+	if (!rjob->tasks) {
+		drm_dbg(dev, "Failed to allocate task array\n");
+		return -ENOMEM;
+	}
+
+	for (int i = 0; i < rjob->task_count; i++) {
+		struct drm_rocket_task task = {0};
+
+		if (copy_from_user(&task,
+				   u64_to_user_ptr(job->tasks) + i * job->task_struct_size,
+				   sizeof(task))) {
+			drm_dbg(dev, "Failed to copy incoming tasks\n");
+			ret = -EFAULT;
+			goto fail;
+		}
+
+		if (task.regcmd_count == 0) {
+			drm_dbg(dev, "regcmd_count field in drm_rocket_task should be > 0.\n");
+			ret = -EINVAL;
+			goto fail;
+		}
+
+		rjob->tasks[i].regcmd = task.regcmd;
+		rjob->tasks[i].regcmd_count = task.regcmd_count;
+	}
+
+	return 0;
+
+fail:
+	kvfree(rjob->tasks);
+	return ret;
+}
+
+static void rocket_job_hw_submit(struct rocket_core *core, struct rocket_job *job)
+{
+	struct rocket_task *task;
+	unsigned int extra_bit;
+
+	/* Don't queue the job if a reset is in progress */
+	if (atomic_read(&core->reset.pending))
+		return;
+
+	/* GO ! */
+
+	task = &job->tasks[job->next_task_idx];
+	job->next_task_idx++;
+
+	rocket_pc_writel(core, BASE_ADDRESS, 0x1);
+
+	 /* From rknpu, in the TRM this bit is marked as reserved */
+	extra_bit = 0x10000000 * core->index;
+	rocket_cna_writel(core, S_POINTER, CNA_S_POINTER_POINTER_PP_EN(1) |
+					   CNA_S_POINTER_EXECUTER_PP_EN(1) |
+					   CNA_S_POINTER_POINTER_PP_MODE(1) |
+					   extra_bit);
+
+	rocket_core_writel(core, S_POINTER, CORE_S_POINTER_POINTER_PP_EN(1) |
+					    CORE_S_POINTER_EXECUTER_PP_EN(1) |
+					    CORE_S_POINTER_POINTER_PP_MODE(1) |
+					    extra_bit);
+
+	rocket_pc_writel(core, BASE_ADDRESS, task->regcmd);
+	rocket_pc_writel(core, REGISTER_AMOUNTS,
+			 PC_REGISTER_AMOUNTS_PC_DATA_AMOUNT((task->regcmd_count + 1) / 2 - 1));
+
+	rocket_pc_writel(core, INTERRUPT_MASK, PC_INTERRUPT_MASK_DPU_0 | PC_INTERRUPT_MASK_DPU_1);
+	rocket_pc_writel(core, INTERRUPT_CLEAR, PC_INTERRUPT_CLEAR_DPU_0 | PC_INTERRUPT_CLEAR_DPU_1);
+
+	rocket_pc_writel(core, TASK_CON, PC_TASK_CON_RESERVED_0(1) |
+					 PC_TASK_CON_TASK_COUNT_CLEAR(1) |
+					 PC_TASK_CON_TASK_NUMBER(1) |
+					 PC_TASK_CON_TASK_PP_EN(1));
+
+	rocket_pc_writel(core, TASK_DMA_BASE_ADDR, PC_TASK_DMA_BASE_ADDR_DMA_BASE_ADDR(0x0));
+
+	rocket_pc_writel(core, OPERATION_ENABLE, PC_OPERATION_ENABLE_OP_EN(1));
+
+	dev_dbg(core->dev, "Submitted regcmd at 0x%llx to core %d", task->regcmd, core->index);
+}
+
+static int rocket_acquire_object_fences(struct drm_gem_object **bos,
+					int bo_count,
+					struct drm_sched_job *job,
+					bool is_write)
+{
+	int i, ret;
+
+	for (i = 0; i < bo_count; i++) {
+		ret = dma_resv_reserve_fences(bos[i]->resv, 1);
+		if (ret)
+			return ret;
+
+		ret = drm_sched_job_add_implicit_dependencies(job, bos[i],
+							      is_write);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static void rocket_attach_object_fences(struct drm_gem_object **bos,
+					int bo_count,
+					struct dma_fence *fence)
+{
+	int i;
+
+	for (i = 0; i < bo_count; i++)
+		dma_resv_add_fence(bos[i]->resv, fence, DMA_RESV_USAGE_WRITE);
+}
+
+static int rocket_job_push(struct rocket_job *job)
+{
+	struct rocket_device *rdev = job->rdev;
+	struct drm_gem_object **bos;
+	struct ww_acquire_ctx acquire_ctx;
+	int ret = 0;
+
+	bos = kvmalloc_array(job->in_bo_count + job->out_bo_count, sizeof(void *),
+			     GFP_KERNEL);
+	memcpy(bos, job->in_bos, job->in_bo_count * sizeof(void *));
+	memcpy(&bos[job->in_bo_count], job->out_bos, job->out_bo_count * sizeof(void *));
+
+	ret = drm_gem_lock_reservations(bos, job->in_bo_count + job->out_bo_count, &acquire_ctx);
+	if (ret)
+		goto err;
+
+	scoped_guard(mutex, &rdev->sched_lock) {
+		drm_sched_job_arm(&job->base);
+
+		job->inference_done_fence = dma_fence_get(&job->base.s_fence->finished);
+
+		ret = rocket_acquire_object_fences(job->in_bos, job->in_bo_count, &job->base, false);
+		if (ret)
+			goto err_unlock;
+
+		ret = rocket_acquire_object_fences(job->out_bos, job->out_bo_count, &job->base, true);
+		if (ret)
+			goto err_unlock;
+
+		kref_get(&job->refcount); /* put by scheduler job completion */
+
+		drm_sched_entity_push_job(&job->base);
+	}
+
+	rocket_attach_object_fences(job->out_bos, job->out_bo_count, job->inference_done_fence);
+
+err_unlock:
+	drm_gem_unlock_reservations(bos, job->in_bo_count + job->out_bo_count, &acquire_ctx);
+err:
+	kvfree(bos);
+
+	return ret;
+}
+
+static void rocket_job_cleanup(struct kref *ref)
+{
+	struct rocket_job *job = container_of(ref, struct rocket_job,
+						refcount);
+	unsigned int i;
+
+	rocket_iommu_domain_put(job->domain);
+
+	dma_fence_put(job->done_fence);
+	dma_fence_put(job->inference_done_fence);
+
+	if (job->in_bos) {
+		for (i = 0; i < job->in_bo_count; i++)
+			drm_gem_object_put(job->in_bos[i]);
+
+		kvfree(job->in_bos);
+	}
+
+	if (job->out_bos) {
+		for (i = 0; i < job->out_bo_count; i++)
+			drm_gem_object_put(job->out_bos[i]);
+
+		kvfree(job->out_bos);
+	}
+
+	kvfree(job->tasks);
+
+	kfree(job);
+}
+
+static void rocket_job_put(struct rocket_job *job)
+{
+	kref_put(&job->refcount, rocket_job_cleanup);
+}
+
+static void rocket_job_free(struct drm_sched_job *sched_job)
+{
+	struct rocket_job *job = to_rocket_job(sched_job);
+
+	drm_sched_job_cleanup(sched_job);
+
+	rocket_job_put(job);
+}
+
+static struct rocket_core *sched_to_core(struct rocket_device *rdev,
+					 struct drm_gpu_scheduler *sched)
+{
+	unsigned int core;
+
+	for (core = 0; core < rdev->num_cores; core++) {
+		if (&rdev->cores[core].sched == sched)
+			return &rdev->cores[core];
+	}
+
+	return NULL;
+}
+
+static struct dma_fence *rocket_job_run(struct drm_sched_job *sched_job)
+{
+	struct rocket_job *job = to_rocket_job(sched_job);
+	struct rocket_device *rdev = job->rdev;
+	struct rocket_core *core = sched_to_core(rdev, sched_job->sched);
+	struct dma_fence *fence = NULL;
+	int ret;
+
+	if (unlikely(job->base.s_fence->finished.error))
+		return NULL;
+
+	/*
+	 * Nothing to execute: can happen if the job has finished while
+	 * we were resetting the NPU.
+	 */
+	if (job->next_task_idx == job->task_count)
+		return NULL;
+
+	fence = rocket_fence_create(core);
+	if (IS_ERR(fence))
+		return fence;
+
+	if (job->done_fence)
+		dma_fence_put(job->done_fence);
+	job->done_fence = dma_fence_get(fence);
+
+	ret = pm_runtime_get_sync(core->dev);
+	if (ret < 0)
+		return fence;
+
+	ret = iommu_attach_group(job->domain->domain, core->iommu_group);
+	if (ret < 0)
+		return fence;
+
+	scoped_guard(mutex, &core->job_lock) {
+		core->in_flight_job = job;
+		rocket_job_hw_submit(core, job);
+	}
+
+	return fence;
+}
+
+static void rocket_job_handle_irq(struct rocket_core *core)
+{
+	pm_runtime_mark_last_busy(core->dev);
+
+	rocket_pc_writel(core, OPERATION_ENABLE, 0x0);
+	rocket_pc_writel(core, INTERRUPT_CLEAR, 0x1ffff);
+
+	scoped_guard(mutex, &core->job_lock)
+		if (core->in_flight_job) {
+			if (core->in_flight_job->next_task_idx < core->in_flight_job->task_count) {
+				rocket_job_hw_submit(core, core->in_flight_job);
+				return;
+			}
+
+			iommu_detach_group(NULL, iommu_group_get(core->dev));
+			dma_fence_signal(core->in_flight_job->done_fence);
+			pm_runtime_put_autosuspend(core->dev);
+			core->in_flight_job = NULL;
+		}
+}
+
+static void
+rocket_reset(struct rocket_core *core, struct drm_sched_job *bad)
+{
+	if (!atomic_read(&core->reset.pending))
+		return;
+
+	drm_sched_stop(&core->sched, bad);
+
+	/*
+	 * Remaining interrupts have been handled, but we might still have
+	 * stuck jobs. Let's make sure the PM counters stay balanced by
+	 * manually calling pm_runtime_put_noidle().
+	 */
+	scoped_guard(mutex, &core->job_lock) {
+		if (core->in_flight_job)
+			pm_runtime_put_noidle(core->dev);
+
+		iommu_detach_group(NULL, core->iommu_group);
+
+		core->in_flight_job = NULL;
+	}
+
+	/* Proceed with reset now. */
+	rocket_core_reset(core);
+
+	/* NPU has been reset, we can clear the reset pending bit. */
+	atomic_set(&core->reset.pending, 0);
+
+	/* Restart the scheduler */
+	drm_sched_start(&core->sched, 0);
+}
+
+static enum drm_gpu_sched_stat rocket_job_timedout(struct drm_sched_job *sched_job)
+{
+	struct rocket_job *job = to_rocket_job(sched_job);
+	struct rocket_device *rdev = job->rdev;
+	struct rocket_core *core = sched_to_core(rdev, sched_job->sched);
+
+	dev_err(core->dev, "NPU job timed out");
+
+	atomic_set(&core->reset.pending, 1);
+	rocket_reset(core, sched_job);
+
+	return DRM_GPU_SCHED_STAT_RESET;
+}
+
+static void rocket_reset_work(struct work_struct *work)
+{
+	struct rocket_core *core;
+
+	core = container_of(work, struct rocket_core, reset.work);
+	rocket_reset(core, NULL);
+}
+
+static const struct drm_sched_backend_ops rocket_sched_ops = {
+	.run_job = rocket_job_run,
+	.timedout_job = rocket_job_timedout,
+	.free_job = rocket_job_free
+};
+
+static irqreturn_t rocket_job_irq_handler_thread(int irq, void *data)
+{
+	struct rocket_core *core = data;
+
+	rocket_job_handle_irq(core);
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t rocket_job_irq_handler(int irq, void *data)
+{
+	struct rocket_core *core = data;
+	u32 raw_status = rocket_pc_readl(core, INTERRUPT_RAW_STATUS);
+
+	WARN_ON(raw_status & PC_INTERRUPT_RAW_STATUS_DMA_READ_ERROR);
+	WARN_ON(raw_status & PC_INTERRUPT_RAW_STATUS_DMA_WRITE_ERROR);
+
+	if (!(raw_status & PC_INTERRUPT_RAW_STATUS_DPU_0 ||
+	      raw_status & PC_INTERRUPT_RAW_STATUS_DPU_1))
+		return IRQ_NONE;
+
+	rocket_pc_writel(core, INTERRUPT_MASK, 0x0);
+
+	return IRQ_WAKE_THREAD;
+}
+
+int rocket_job_init(struct rocket_core *core)
+{
+	struct drm_sched_init_args args = {
+		.ops = &rocket_sched_ops,
+		.num_rqs = DRM_SCHED_PRIORITY_COUNT,
+		.credit_limit = 1,
+		.timeout = msecs_to_jiffies(JOB_TIMEOUT_MS),
+		.name = dev_name(core->dev),
+		.dev = core->dev,
+	};
+	int ret;
+
+	INIT_WORK(&core->reset.work, rocket_reset_work);
+	spin_lock_init(&core->fence_lock);
+	mutex_init(&core->job_lock);
+
+	core->irq = platform_get_irq(to_platform_device(core->dev), 0);
+	if (core->irq < 0)
+		return core->irq;
+
+	ret = devm_request_threaded_irq(core->dev, core->irq,
+					rocket_job_irq_handler,
+					rocket_job_irq_handler_thread,
+					IRQF_SHARED, dev_name(core->dev),
+					core);
+	if (ret) {
+		dev_err(core->dev, "failed to request job irq");
+		return ret;
+	}
+
+	core->reset.wq = alloc_ordered_workqueue("rocket-reset-%d", 0, core->index);
+	if (!core->reset.wq)
+		return -ENOMEM;
+
+	core->fence_context = dma_fence_context_alloc(1);
+
+	args.timeout_wq = core->reset.wq;
+	ret = drm_sched_init(&core->sched, &args);
+	if (ret) {
+		dev_err(core->dev, "Failed to create scheduler: %d.", ret);
+		goto err_sched;
+	}
+
+	return 0;
+
+err_sched:
+	drm_sched_fini(&core->sched);
+
+	destroy_workqueue(core->reset.wq);
+	return ret;
+}
+
+void rocket_job_fini(struct rocket_core *core)
+{
+	drm_sched_fini(&core->sched);
+
+	cancel_work_sync(&core->reset.work);
+	destroy_workqueue(core->reset.wq);
+}
+
+int rocket_job_open(struct rocket_file_priv *rocket_priv)
+{
+	struct rocket_device *rdev = rocket_priv->rdev;
+	struct drm_gpu_scheduler **scheds = kmalloc_array(rdev->num_cores,
+							  sizeof(*scheds),
+							  GFP_KERNEL);
+	unsigned int core;
+	int ret;
+
+	for (core = 0; core < rdev->num_cores; core++)
+		scheds[core] = &rdev->cores[core].sched;
+
+	ret = drm_sched_entity_init(&rocket_priv->sched_entity,
+				    DRM_SCHED_PRIORITY_NORMAL,
+				    scheds,
+				    rdev->num_cores, NULL);
+	if (WARN_ON(ret))
+		return ret;
+
+	return 0;
+}
+
+void rocket_job_close(struct rocket_file_priv *rocket_priv)
+{
+	struct drm_sched_entity *entity = &rocket_priv->sched_entity;
+
+	kfree(entity->sched_list);
+	drm_sched_entity_destroy(entity);
+}
+
+int rocket_job_is_idle(struct rocket_core *core)
+{
+	/* If there are any jobs in this HW queue, we're not idle */
+	if (atomic_read(&core->sched.credit_count))
+		return false;
+
+	return true;
+}
+
+static int rocket_ioctl_submit_job(struct drm_device *dev, struct drm_file *file,
+				   struct drm_rocket_job *job)
+{
+	struct rocket_device *rdev = to_rocket_device(dev);
+	struct rocket_file_priv *file_priv = file->driver_priv;
+	struct rocket_job *rjob = NULL;
+	int ret = 0;
+
+	if (job->task_count == 0)
+		return -EINVAL;
+
+	rjob = kzalloc(sizeof(*rjob), GFP_KERNEL);
+	if (!rjob)
+		return -ENOMEM;
+
+	kref_init(&rjob->refcount);
+
+	rjob->rdev = rdev;
+
+	ret = drm_sched_job_init(&rjob->base,
+				 &file_priv->sched_entity,
+				 1, NULL, file->client_id);
+	if (ret)
+		goto out_put_job;
+
+	ret = rocket_copy_tasks(dev, file, job, rjob);
+	if (ret)
+		goto out_cleanup_job;
+
+	ret = drm_gem_objects_lookup(file, u64_to_user_ptr(job->in_bo_handles),
+				     job->in_bo_handle_count, &rjob->in_bos);
+	if (ret)
+		goto out_cleanup_job;
+
+	rjob->in_bo_count = job->in_bo_handle_count;
+
+	ret = drm_gem_objects_lookup(file, u64_to_user_ptr(job->out_bo_handles),
+				     job->out_bo_handle_count, &rjob->out_bos);
+	if (ret)
+		goto out_cleanup_job;
+
+	rjob->out_bo_count = job->out_bo_handle_count;
+
+	rjob->domain = rocket_iommu_domain_get(file_priv);
+
+	ret = rocket_job_push(rjob);
+	if (ret)
+		goto out_cleanup_job;
+
+out_cleanup_job:
+	if (ret)
+		drm_sched_job_cleanup(&rjob->base);
+out_put_job:
+	rocket_job_put(rjob);
+
+	return ret;
+}
+
+int rocket_ioctl_submit(struct drm_device *dev, void *data, struct drm_file *file)
+{
+	struct drm_rocket_submit *args = data;
+	struct drm_rocket_job *jobs;
+	int ret = 0;
+	unsigned int i = 0;
+
+	if (args->job_count == 0)
+		return 0;
+
+	if (args->job_struct_size < sizeof(struct drm_rocket_job)) {
+		drm_dbg(dev, "job_struct_size field in drm_rocket_submit struct is too small.\n");
+		return -EINVAL;
+	}
+
+	if (args->reserved != 0) {
+		drm_dbg(dev, "Reserved field in drm_rocket_submit struct should be 0.\n");
+		return -EINVAL;
+	}
+
+	jobs = kvmalloc_array(args->job_count, sizeof(*jobs), GFP_KERNEL);
+	if (!jobs) {
+		drm_dbg(dev, "Failed to allocate incoming job array\n");
+		return -ENOMEM;
+	}
+
+	for (i = 0; i < args->job_count; i++) {
+		if (copy_from_user(&jobs[i],
+				   u64_to_user_ptr(args->jobs) + i * args->job_struct_size,
+				   sizeof(*jobs))) {
+			ret = -EFAULT;
+			drm_dbg(dev, "Failed to copy incoming job array\n");
+			goto exit;
+		}
+	}
+
+
+	for (i = 0; i < args->job_count; i++)
+		rocket_ioctl_submit_job(dev, file, &jobs[i]);
+
+exit:
+	kvfree(jobs);
+
+	return ret;
+}
diff --git a/drivers/accel/rocket/rocket_job.h b/drivers/accel/rocket/rocket_job.h
new file mode 100644
index 000000000000..4ae00feec3b9
--- /dev/null
+++ b/drivers/accel/rocket/rocket_job.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright 2024-2025 Tomeu Vizoso <tomeu@tomeuvizoso.net> */
+
+#ifndef __ROCKET_JOB_H__
+#define __ROCKET_JOB_H__
+
+#include <drm/drm_drv.h>
+#include <drm/gpu_scheduler.h>
+
+#include "rocket_core.h"
+#include "rocket_drv.h"
+
+struct rocket_task {
+	u64 regcmd;
+	u32 regcmd_count;
+};
+
+struct rocket_job {
+	struct drm_sched_job base;
+
+	struct rocket_device *rdev;
+
+	struct drm_gem_object **in_bos;
+	struct drm_gem_object **out_bos;
+
+	u32 in_bo_count;
+	u32 out_bo_count;
+
+	struct rocket_task *tasks;
+	u32 task_count;
+	u32 next_task_idx;
+
+	/* Fence to be signaled by drm-sched once its done with the job */
+	struct dma_fence *inference_done_fence;
+
+	/* Fence to be signaled by IRQ handler when the job is complete. */
+	struct dma_fence *done_fence;
+
+	struct rocket_iommu_domain *domain;
+
+	struct kref refcount;
+};
+
+int rocket_ioctl_submit(struct drm_device *dev, void *data, struct drm_file *file);
+
+int rocket_job_init(struct rocket_core *core);
+void rocket_job_fini(struct rocket_core *core);
+int rocket_job_open(struct rocket_file_priv *rocket_priv);
+void rocket_job_close(struct rocket_file_priv *rocket_priv);
+int rocket_job_is_idle(struct rocket_core *core);
+
+#endif
diff --git a/drivers/accel/rocket/rocket_registers.h b/drivers/accel/rocket/rocket_registers.h
new file mode 100644
index 000000000000..9aef614c3470
--- /dev/null
+++ b/drivers/accel/rocket/rocket_registers.h
@@ -0,0 +1,4404 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef __ROCKET_REGISTERS_XML__
+#define __ROCKET_REGISTERS_XML__
+
+/* Autogenerated file, DO NOT EDIT manually!
+
+This file was generated by the rules-ng-ng gen_header.py tool in this git repository:
+http://gitlab.freedesktop.org/mesa/mesa/
+git clone https://gitlab.freedesktop.org/mesa/mesa.git
+
+The rules-ng-ng source files this header was generated from are:
+
+- /home/tomeu/src/mesa/src/gallium/drivers/rocket/registers.xml (  60076 bytes, from Wed Jun 12 10:02:25 2024)
+
+Copyright (C) 2024-2025 by the following authors:
+- Tomeu Vizoso <tomeu@tomeuvizoso.net>
+*/
+
+#define REG_PC_VERSION						0x00000000
+#define PC_VERSION_VERSION__MASK				0xffffffff
+#define PC_VERSION_VERSION__SHIFT				0
+static inline uint32_t PC_VERSION_VERSION(uint32_t val)
+{
+	return ((val) << PC_VERSION_VERSION__SHIFT) & PC_VERSION_VERSION__MASK;
+}
+
+#define REG_PC_VERSION_NUM					0x00000004
+#define PC_VERSION_NUM_VERSION_NUM__MASK			0xffffffff
+#define PC_VERSION_NUM_VERSION_NUM__SHIFT			0
+static inline uint32_t PC_VERSION_NUM_VERSION_NUM(uint32_t val)
+{
+	return ((val) << PC_VERSION_NUM_VERSION_NUM__SHIFT) & PC_VERSION_NUM_VERSION_NUM__MASK;
+}
+
+#define REG_PC_OPERATION_ENABLE					0x00000008
+#define PC_OPERATION_ENABLE_RESERVED_0__MASK			0xfffffffe
+#define PC_OPERATION_ENABLE_RESERVED_0__SHIFT			1
+static inline uint32_t PC_OPERATION_ENABLE_RESERVED_0(uint32_t val)
+{
+	return ((val) << PC_OPERATION_ENABLE_RESERVED_0__SHIFT) & PC_OPERATION_ENABLE_RESERVED_0__MASK;
+}
+#define PC_OPERATION_ENABLE_OP_EN__MASK				0x00000001
+#define PC_OPERATION_ENABLE_OP_EN__SHIFT			0
+static inline uint32_t PC_OPERATION_ENABLE_OP_EN(uint32_t val)
+{
+	return ((val) << PC_OPERATION_ENABLE_OP_EN__SHIFT) & PC_OPERATION_ENABLE_OP_EN__MASK;
+}
+
+#define REG_PC_BASE_ADDRESS					0x00000010
+#define PC_BASE_ADDRESS_PC_SOURCE_ADDR__MASK			0xfffffff0
+#define PC_BASE_ADDRESS_PC_SOURCE_ADDR__SHIFT			4
+static inline uint32_t PC_BASE_ADDRESS_PC_SOURCE_ADDR(uint32_t val)
+{
+	return ((val) << PC_BASE_ADDRESS_PC_SOURCE_ADDR__SHIFT) & PC_BASE_ADDRESS_PC_SOURCE_ADDR__MASK;
+}
+#define PC_BASE_ADDRESS_RESERVED_0__MASK			0x0000000e
+#define PC_BASE_ADDRESS_RESERVED_0__SHIFT			1
+static inline uint32_t PC_BASE_ADDRESS_RESERVED_0(uint32_t val)
+{
+	return ((val) << PC_BASE_ADDRESS_RESERVED_0__SHIFT) & PC_BASE_ADDRESS_RESERVED_0__MASK;
+}
+#define PC_BASE_ADDRESS_PC_SEL__MASK				0x00000001
+#define PC_BASE_ADDRESS_PC_SEL__SHIFT				0
+static inline uint32_t PC_BASE_ADDRESS_PC_SEL(uint32_t val)
+{
+	return ((val) << PC_BASE_ADDRESS_PC_SEL__SHIFT) & PC_BASE_ADDRESS_PC_SEL__MASK;
+}
+
+#define REG_PC_REGISTER_AMOUNTS					0x00000014
+#define PC_REGISTER_AMOUNTS_RESERVED_0__MASK			0xffff0000
+#define PC_REGISTER_AMOUNTS_RESERVED_0__SHIFT			16
+static inline uint32_t PC_REGISTER_AMOUNTS_RESERVED_0(uint32_t val)
+{
+	return ((val) << PC_REGISTER_AMOUNTS_RESERVED_0__SHIFT) & PC_REGISTER_AMOUNTS_RESERVED_0__MASK;
+}
+#define PC_REGISTER_AMOUNTS_PC_DATA_AMOUNT__MASK		0x0000ffff
+#define PC_REGISTER_AMOUNTS_PC_DATA_AMOUNT__SHIFT		0
+static inline uint32_t PC_REGISTER_AMOUNTS_PC_DATA_AMOUNT(uint32_t val)
+{
+	return ((val) << PC_REGISTER_AMOUNTS_PC_DATA_AMOUNT__SHIFT) & PC_REGISTER_AMOUNTS_PC_DATA_AMOUNT__MASK;
+}
+
+#define REG_PC_INTERRUPT_MASK					0x00000020
+#define PC_INTERRUPT_MASK_RESERVED_0__MASK			0xffffc000
+#define PC_INTERRUPT_MASK_RESERVED_0__SHIFT			14
+static inline uint32_t PC_INTERRUPT_MASK_RESERVED_0(uint32_t val)
+{
+	return ((val) << PC_INTERRUPT_MASK_RESERVED_0__SHIFT) & PC_INTERRUPT_MASK_RESERVED_0__MASK;
+}
+#define PC_INTERRUPT_MASK_DMA_WRITE_ERROR			0x00002000
+#define PC_INTERRUPT_MASK_DMA_READ_ERROR			0x00001000
+#define PC_INTERRUPT_MASK_PPU_1					0x00000800
+#define PC_INTERRUPT_MASK_PPU_0					0x00000400
+#define PC_INTERRUPT_MASK_DPU_1					0x00000200
+#define PC_INTERRUPT_MASK_DPU_0					0x00000100
+#define PC_INTERRUPT_MASK_CORE_1				0x00000080
+#define PC_INTERRUPT_MASK_CORE_0				0x00000040
+#define PC_INTERRUPT_MASK_CNA_CSC_1				0x00000020
+#define PC_INTERRUPT_MASK_CNA_CSC_0				0x00000010
+#define PC_INTERRUPT_MASK_CNA_WEIGHT_1				0x00000008
+#define PC_INTERRUPT_MASK_CNA_WEIGHT_0				0x00000004
+#define PC_INTERRUPT_MASK_CNA_FEATURE_1				0x00000002
+#define PC_INTERRUPT_MASK_CNA_FEATURE_0				0x00000001
+
+#define REG_PC_INTERRUPT_CLEAR					0x00000024
+#define PC_INTERRUPT_CLEAR_RESERVED_0__MASK			0xffffc000
+#define PC_INTERRUPT_CLEAR_RESERVED_0__SHIFT			14
+static inline uint32_t PC_INTERRUPT_CLEAR_RESERVED_0(uint32_t val)
+{
+	return ((val) << PC_INTERRUPT_CLEAR_RESERVED_0__SHIFT) & PC_INTERRUPT_CLEAR_RESERVED_0__MASK;
+}
+#define PC_INTERRUPT_CLEAR_DMA_WRITE_ERROR			0x00002000
+#define PC_INTERRUPT_CLEAR_DMA_READ_ERROR			0x00001000
+#define PC_INTERRUPT_CLEAR_PPU_1				0x00000800
+#define PC_INTERRUPT_CLEAR_PPU_0				0x00000400
+#define PC_INTERRUPT_CLEAR_DPU_1				0x00000200
+#define PC_INTERRUPT_CLEAR_DPU_0				0x00000100
+#define PC_INTERRUPT_CLEAR_CORE_1				0x00000080
+#define PC_INTERRUPT_CLEAR_CORE_0				0x00000040
+#define PC_INTERRUPT_CLEAR_CNA_CSC_1				0x00000020
+#define PC_INTERRUPT_CLEAR_CNA_CSC_0				0x00000010
+#define PC_INTERRUPT_CLEAR_CNA_WEIGHT_1				0x00000008
+#define PC_INTERRUPT_CLEAR_CNA_WEIGHT_0				0x00000004
+#define PC_INTERRUPT_CLEAR_CNA_FEATURE_1			0x00000002
+#define PC_INTERRUPT_CLEAR_CNA_FEATURE_0			0x00000001
+
+#define REG_PC_INTERRUPT_STATUS					0x00000028
+#define PC_INTERRUPT_STATUS_RESERVED_0__MASK			0xffffc000
+#define PC_INTERRUPT_STATUS_RESERVED_0__SHIFT			14
+static inline uint32_t PC_INTERRUPT_STATUS_RESERVED_0(uint32_t val)
+{
+	return ((val) << PC_INTERRUPT_STATUS_RESERVED_0__SHIFT) & PC_INTERRUPT_STATUS_RESERVED_0__MASK;
+}
+#define PC_INTERRUPT_STATUS_DMA_WRITE_ERROR			0x00002000
+#define PC_INTERRUPT_STATUS_DMA_READ_ERROR			0x00001000
+#define PC_INTERRUPT_STATUS_PPU_1				0x00000800
+#define PC_INTERRUPT_STATUS_PPU_0				0x00000400
+#define PC_INTERRUPT_STATUS_DPU_1				0x00000200
+#define PC_INTERRUPT_STATUS_DPU_0				0x00000100
+#define PC_INTERRUPT_STATUS_CORE_1				0x00000080
+#define PC_INTERRUPT_STATUS_CORE_0				0x00000040
+#define PC_INTERRUPT_STATUS_CNA_CSC_1				0x00000020
+#define PC_INTERRUPT_STATUS_CNA_CSC_0				0x00000010
+#define PC_INTERRUPT_STATUS_CNA_WEIGHT_1			0x00000008
+#define PC_INTERRUPT_STATUS_CNA_WEIGHT_0			0x00000004
+#define PC_INTERRUPT_STATUS_CNA_FEATURE_1			0x00000002
+#define PC_INTERRUPT_STATUS_CNA_FEATURE_0			0x00000001
+
+#define REG_PC_INTERRUPT_RAW_STATUS				0x0000002c
+#define PC_INTERRUPT_RAW_STATUS_RESERVED_0__MASK		0xffffc000
+#define PC_INTERRUPT_RAW_STATUS_RESERVED_0__SHIFT		14
+static inline uint32_t PC_INTERRUPT_RAW_STATUS_RESERVED_0(uint32_t val)
+{
+	return ((val) << PC_INTERRUPT_RAW_STATUS_RESERVED_0__SHIFT) & PC_INTERRUPT_RAW_STATUS_RESERVED_0__MASK;
+}
+#define PC_INTERRUPT_RAW_STATUS_DMA_WRITE_ERROR			0x00002000
+#define PC_INTERRUPT_RAW_STATUS_DMA_READ_ERROR			0x00001000
+#define PC_INTERRUPT_RAW_STATUS_PPU_1				0x00000800
+#define PC_INTERRUPT_RAW_STATUS_PPU_0				0x00000400
+#define PC_INTERRUPT_RAW_STATUS_DPU_1				0x00000200
+#define PC_INTERRUPT_RAW_STATUS_DPU_0				0x00000100
+#define PC_INTERRUPT_RAW_STATUS_CORE_1				0x00000080
+#define PC_INTERRUPT_RAW_STATUS_CORE_0				0x00000040
+#define PC_INTERRUPT_RAW_STATUS_CNA_CSC_1			0x00000020
+#define PC_INTERRUPT_RAW_STATUS_CNA_CSC_0			0x00000010
+#define PC_INTERRUPT_RAW_STATUS_CNA_WEIGHT_1			0x00000008
+#define PC_INTERRUPT_RAW_STATUS_CNA_WEIGHT_0			0x00000004
+#define PC_INTERRUPT_RAW_STATUS_CNA_FEATURE_1			0x00000002
+#define PC_INTERRUPT_RAW_STATUS_CNA_FEATURE_0			0x00000001
+
+#define REG_PC_TASK_CON						0x00000030
+#define PC_TASK_CON_RESERVED_0__MASK				0xffffc000
+#define PC_TASK_CON_RESERVED_0__SHIFT				14
+static inline uint32_t PC_TASK_CON_RESERVED_0(uint32_t val)
+{
+	return ((val) << PC_TASK_CON_RESERVED_0__SHIFT) & PC_TASK_CON_RESERVED_0__MASK;
+}
+#define PC_TASK_CON_TASK_COUNT_CLEAR__MASK			0x00002000
+#define PC_TASK_CON_TASK_COUNT_CLEAR__SHIFT			13
+static inline uint32_t PC_TASK_CON_TASK_COUNT_CLEAR(uint32_t val)
+{
+	return ((val) << PC_TASK_CON_TASK_COUNT_CLEAR__SHIFT) & PC_TASK_CON_TASK_COUNT_CLEAR__MASK;
+}
+#define PC_TASK_CON_TASK_PP_EN__MASK				0x00001000
+#define PC_TASK_CON_TASK_PP_EN__SHIFT				12
+static inline uint32_t PC_TASK_CON_TASK_PP_EN(uint32_t val)
+{
+	return ((val) << PC_TASK_CON_TASK_PP_EN__SHIFT) & PC_TASK_CON_TASK_PP_EN__MASK;
+}
+#define PC_TASK_CON_TASK_NUMBER__MASK				0x00000fff
+#define PC_TASK_CON_TASK_NUMBER__SHIFT				0
+static inline uint32_t PC_TASK_CON_TASK_NUMBER(uint32_t val)
+{
+	return ((val) << PC_TASK_CON_TASK_NUMBER__SHIFT) & PC_TASK_CON_TASK_NUMBER__MASK;
+}
+
+#define REG_PC_TASK_DMA_BASE_ADDR				0x00000034
+#define PC_TASK_DMA_BASE_ADDR_DMA_BASE_ADDR__MASK		0xfffffff0
+#define PC_TASK_DMA_BASE_ADDR_DMA_BASE_ADDR__SHIFT		4
+static inline uint32_t PC_TASK_DMA_BASE_ADDR_DMA_BASE_ADDR(uint32_t val)
+{
+	return ((val) << PC_TASK_DMA_BASE_ADDR_DMA_BASE_ADDR__SHIFT) & PC_TASK_DMA_BASE_ADDR_DMA_BASE_ADDR__MASK;
+}
+#define PC_TASK_DMA_BASE_ADDR_RESERVED_0__MASK			0x0000000f
+#define PC_TASK_DMA_BASE_ADDR_RESERVED_0__SHIFT			0
+static inline uint32_t PC_TASK_DMA_BASE_ADDR_RESERVED_0(uint32_t val)
+{
+	return ((val) << PC_TASK_DMA_BASE_ADDR_RESERVED_0__SHIFT) & PC_TASK_DMA_BASE_ADDR_RESERVED_0__MASK;
+}
+
+#define REG_PC_TASK_STATUS					0x0000003c
+#define PC_TASK_STATUS_RESERVED_0__MASK				0xf0000000
+#define PC_TASK_STATUS_RESERVED_0__SHIFT			28
+static inline uint32_t PC_TASK_STATUS_RESERVED_0(uint32_t val)
+{
+	return ((val) << PC_TASK_STATUS_RESERVED_0__SHIFT) & PC_TASK_STATUS_RESERVED_0__MASK;
+}
+#define PC_TASK_STATUS_TASK_STATUS__MASK			0x0fffffff
+#define PC_TASK_STATUS_TASK_STATUS__SHIFT			0
+static inline uint32_t PC_TASK_STATUS_TASK_STATUS(uint32_t val)
+{
+	return ((val) << PC_TASK_STATUS_TASK_STATUS__SHIFT) & PC_TASK_STATUS_TASK_STATUS__MASK;
+}
+
+#define REG_CNA_S_STATUS					0x00001000
+#define CNA_S_STATUS_RESERVED_0__MASK				0xfffc0000
+#define CNA_S_STATUS_RESERVED_0__SHIFT				18
+static inline uint32_t CNA_S_STATUS_RESERVED_0(uint32_t val)
+{
+	return ((val) << CNA_S_STATUS_RESERVED_0__SHIFT) & CNA_S_STATUS_RESERVED_0__MASK;
+}
+#define CNA_S_STATUS_STATUS_1__MASK				0x00030000
+#define CNA_S_STATUS_STATUS_1__SHIFT				16
+static inline uint32_t CNA_S_STATUS_STATUS_1(uint32_t val)
+{
+	return ((val) << CNA_S_STATUS_STATUS_1__SHIFT) & CNA_S_STATUS_STATUS_1__MASK;
+}
+#define CNA_S_STATUS_RESERVED_1__MASK				0x0000fffc
+#define CNA_S_STATUS_RESERVED_1__SHIFT				2
+static inline uint32_t CNA_S_STATUS_RESERVED_1(uint32_t val)
+{
+	return ((val) << CNA_S_STATUS_RESERVED_1__SHIFT) & CNA_S_STATUS_RESERVED_1__MASK;
+}
+#define CNA_S_STATUS_STATUS_0__MASK				0x00000003
+#define CNA_S_STATUS_STATUS_0__SHIFT				0
+static inline uint32_t CNA_S_STATUS_STATUS_0(uint32_t val)
+{
+	return ((val) << CNA_S_STATUS_STATUS_0__SHIFT) & CNA_S_STATUS_STATUS_0__MASK;
+}
+
+#define REG_CNA_S_POINTER					0x00001004
+#define CNA_S_POINTER_RESERVED_0__MASK				0xfffe0000
+#define CNA_S_POINTER_RESERVED_0__SHIFT				17
+static inline uint32_t CNA_S_POINTER_RESERVED_0(uint32_t val)
+{
+	return ((val) << CNA_S_POINTER_RESERVED_0__SHIFT) & CNA_S_POINTER_RESERVED_0__MASK;
+}
+#define CNA_S_POINTER_EXECUTER__MASK				0x00010000
+#define CNA_S_POINTER_EXECUTER__SHIFT				16
+static inline uint32_t CNA_S_POINTER_EXECUTER(uint32_t val)
+{
+	return ((val) << CNA_S_POINTER_EXECUTER__SHIFT) & CNA_S_POINTER_EXECUTER__MASK;
+}
+#define CNA_S_POINTER_RESERVED_1__MASK				0x0000ffc0
+#define CNA_S_POINTER_RESERVED_1__SHIFT				6
+static inline uint32_t CNA_S_POINTER_RESERVED_1(uint32_t val)
+{
+	return ((val) << CNA_S_POINTER_RESERVED_1__SHIFT) & CNA_S_POINTER_RESERVED_1__MASK;
+}
+#define CNA_S_POINTER_EXECUTER_PP_CLEAR__MASK			0x00000020
+#define CNA_S_POINTER_EXECUTER_PP_CLEAR__SHIFT			5
+static inline uint32_t CNA_S_POINTER_EXECUTER_PP_CLEAR(uint32_t val)
+{
+	return ((val) << CNA_S_POINTER_EXECUTER_PP_CLEAR__SHIFT) & CNA_S_POINTER_EXECUTER_PP_CLEAR__MASK;
+}
+#define CNA_S_POINTER_POINTER_PP_CLEAR__MASK			0x00000010
+#define CNA_S_POINTER_POINTER_PP_CLEAR__SHIFT			4
+static inline uint32_t CNA_S_POINTER_POINTER_PP_CLEAR(uint32_t val)
+{
+	return ((val) << CNA_S_POINTER_POINTER_PP_CLEAR__SHIFT) & CNA_S_POINTER_POINTER_PP_CLEAR__MASK;
+}
+#define CNA_S_POINTER_POINTER_PP_MODE__MASK			0x00000008
+#define CNA_S_POINTER_POINTER_PP_MODE__SHIFT			3
+static inline uint32_t CNA_S_POINTER_POINTER_PP_MODE(uint32_t val)
+{
+	return ((val) << CNA_S_POINTER_POINTER_PP_MODE__SHIFT) & CNA_S_POINTER_POINTER_PP_MODE__MASK;
+}
+#define CNA_S_POINTER_EXECUTER_PP_EN__MASK			0x00000004
+#define CNA_S_POINTER_EXECUTER_PP_EN__SHIFT			2
+static inline uint32_t CNA_S_POINTER_EXECUTER_PP_EN(uint32_t val)
+{
+	return ((val) << CNA_S_POINTER_EXECUTER_PP_EN__SHIFT) & CNA_S_POINTER_EXECUTER_PP_EN__MASK;
+}
+#define CNA_S_POINTER_POINTER_PP_EN__MASK			0x00000002
+#define CNA_S_POINTER_POINTER_PP_EN__SHIFT			1
+static inline uint32_t CNA_S_POINTER_POINTER_PP_EN(uint32_t val)
+{
+	return ((val) << CNA_S_POINTER_POINTER_PP_EN__SHIFT) & CNA_S_POINTER_POINTER_PP_EN__MASK;
+}
+#define CNA_S_POINTER_POINTER__MASK				0x00000001
+#define CNA_S_POINTER_POINTER__SHIFT				0
+static inline uint32_t CNA_S_POINTER_POINTER(uint32_t val)
+{
+	return ((val) << CNA_S_POINTER_POINTER__SHIFT) & CNA_S_POINTER_POINTER__MASK;
+}
+
+#define REG_CNA_OPERATION_ENABLE				0x00001008
+#define CNA_OPERATION_ENABLE_RESERVED_0__MASK			0xfffffffe
+#define CNA_OPERATION_ENABLE_RESERVED_0__SHIFT			1
+static inline uint32_t CNA_OPERATION_ENABLE_RESERVED_0(uint32_t val)
+{
+	return ((val) << CNA_OPERATION_ENABLE_RESERVED_0__SHIFT) & CNA_OPERATION_ENABLE_RESERVED_0__MASK;
+}
+#define CNA_OPERATION_ENABLE_OP_EN__MASK			0x00000001
+#define CNA_OPERATION_ENABLE_OP_EN__SHIFT			0
+static inline uint32_t CNA_OPERATION_ENABLE_OP_EN(uint32_t val)
+{
+	return ((val) << CNA_OPERATION_ENABLE_OP_EN__SHIFT) & CNA_OPERATION_ENABLE_OP_EN__MASK;
+}
+
+#define REG_CNA_CONV_CON1					0x0000100c
+#define CNA_CONV_CON1_RESERVED_0__MASK				0x80000000
+#define CNA_CONV_CON1_RESERVED_0__SHIFT				31
+static inline uint32_t CNA_CONV_CON1_RESERVED_0(uint32_t val)
+{
+	return ((val) << CNA_CONV_CON1_RESERVED_0__SHIFT) & CNA_CONV_CON1_RESERVED_0__MASK;
+}
+#define CNA_CONV_CON1_NONALIGN_DMA__MASK			0x40000000
+#define CNA_CONV_CON1_NONALIGN_DMA__SHIFT			30
+static inline uint32_t CNA_CONV_CON1_NONALIGN_DMA(uint32_t val)
+{
+	return ((val) << CNA_CONV_CON1_NONALIGN_DMA__SHIFT) & CNA_CONV_CON1_NONALIGN_DMA__MASK;
+}
+#define CNA_CONV_CON1_GROUP_LINE_OFF__MASK			0x20000000
+#define CNA_CONV_CON1_GROUP_LINE_OFF__SHIFT			29
+static inline uint32_t CNA_CONV_CON1_GROUP_LINE_OFF(uint32_t val)
+{
+	return ((val) << CNA_CONV_CON1_GROUP_LINE_OFF__SHIFT) & CNA_CONV_CON1_GROUP_LINE_OFF__MASK;
+}
+#define CNA_CONV_CON1_RESERVED_1__MASK				0x1ffe0000
+#define CNA_CONV_CON1_RESERVED_1__SHIFT				17
+static inline uint32_t CNA_CONV_CON1_RESERVED_1(uint32_t val)
+{
+	return ((val) << CNA_CONV_CON1_RESERVED_1__SHIFT) & CNA_CONV_CON1_RESERVED_1__MASK;
+}
+#define CNA_CONV_CON1_DECONV__MASK				0x00010000
+#define CNA_CONV_CON1_DECONV__SHIFT				16
+static inline uint32_t CNA_CONV_CON1_DECONV(uint32_t val)
+{
+	return ((val) << CNA_CONV_CON1_DECONV__SHIFT) & CNA_CONV_CON1_DECONV__MASK;
+}
+#define CNA_CONV_CON1_ARGB_IN__MASK				0x0000f000
+#define CNA_CONV_CON1_ARGB_IN__SHIFT				12
+static inline uint32_t CNA_CONV_CON1_ARGB_IN(uint32_t val)
+{
+	return ((val) << CNA_CONV_CON1_ARGB_IN__SHIFT) & CNA_CONV_CON1_ARGB_IN__MASK;
+}
+#define CNA_CONV_CON1_RESERVED_2__MASK				0x00000c00
+#define CNA_CONV_CON1_RESERVED_2__SHIFT				10
+static inline uint32_t CNA_CONV_CON1_RESERVED_2(uint32_t val)
+{
+	return ((val) << CNA_CONV_CON1_RESERVED_2__SHIFT) & CNA_CONV_CON1_RESERVED_2__MASK;
+}
+#define CNA_CONV_CON1_PROC_PRECISION__MASK			0x00000380
+#define CNA_CONV_CON1_PROC_PRECISION__SHIFT			7
+static inline uint32_t CNA_CONV_CON1_PROC_PRECISION(uint32_t val)
+{
+	return ((val) << CNA_CONV_CON1_PROC_PRECISION__SHIFT) & CNA_CONV_CON1_PROC_PRECISION__MASK;
+}
+#define CNA_CONV_CON1_IN_PRECISION__MASK			0x00000070
+#define CNA_CONV_CON1_IN_PRECISION__SHIFT			4
+static inline uint32_t CNA_CONV_CON1_IN_PRECISION(uint32_t val)
+{
+	return ((val) << CNA_CONV_CON1_IN_PRECISION__SHIFT) & CNA_CONV_CON1_IN_PRECISION__MASK;
+}
+#define CNA_CONV_CON1_CONV_MODE__MASK				0x0000000f
+#define CNA_CONV_CON1_CONV_MODE__SHIFT				0
+static inline uint32_t CNA_CONV_CON1_CONV_MODE(uint32_t val)
+{
+	return ((val) << CNA_CONV_CON1_CONV_MODE__SHIFT) & CNA_CONV_CON1_CONV_MODE__MASK;
+}
+
+#define REG_CNA_CONV_CON2					0x00001010
+#define CNA_CONV_CON2_RESERVED_0__MASK				0xff000000
+#define CNA_CONV_CON2_RESERVED_0__SHIFT				24
+static inline uint32_t CNA_CONV_CON2_RESERVED_0(uint32_t val)
+{
+	return ((val) << CNA_CONV_CON2_RESERVED_0__SHIFT) & CNA_CONV_CON2_RESERVED_0__MASK;
+}
+#define CNA_CONV_CON2_KERNEL_GROUP__MASK			0x00ff0000
+#define CNA_CONV_CON2_KERNEL_GROUP__SHIFT			16
+static inline uint32_t CNA_CONV_CON2_KERNEL_GROUP(uint32_t val)
+{
+	return ((val) << CNA_CONV_CON2_KERNEL_GROUP__SHIFT) & CNA_CONV_CON2_KERNEL_GROUP__MASK;
+}
+#define CNA_CONV_CON2_RESERVED_1__MASK				0x0000c000
+#define CNA_CONV_CON2_RESERVED_1__SHIFT				14
+static inline uint32_t CNA_CONV_CON2_RESERVED_1(uint32_t val)
+{
+	return ((val) << CNA_CONV_CON2_RESERVED_1__SHIFT) & CNA_CONV_CON2_RESERVED_1__MASK;
+}
+#define CNA_CONV_CON2_FEATURE_GRAINS__MASK			0x00003ff0
+#define CNA_CONV_CON2_FEATURE_GRAINS__SHIFT			4
+static inline uint32_t CNA_CONV_CON2_FEATURE_GRAINS(uint32_t val)
+{
+	return ((val) << CNA_CONV_CON2_FEATURE_GRAINS__SHIFT) & CNA_CONV_CON2_FEATURE_GRAINS__MASK;
+}
+#define CNA_CONV_CON2_RESERVED_2__MASK				0x00000008
+#define CNA_CONV_CON2_RESERVED_2__SHIFT				3
+static inline uint32_t CNA_CONV_CON2_RESERVED_2(uint32_t val)
+{
+	return ((val) << CNA_CONV_CON2_RESERVED_2__SHIFT) & CNA_CONV_CON2_RESERVED_2__MASK;
+}
+#define CNA_CONV_CON2_CSC_WO_EN__MASK				0x00000004
+#define CNA_CONV_CON2_CSC_WO_EN__SHIFT				2
+static inline uint32_t CNA_CONV_CON2_CSC_WO_EN(uint32_t val)
+{
+	return ((val) << CNA_CONV_CON2_CSC_WO_EN__SHIFT) & CNA_CONV_CON2_CSC_WO_EN__MASK;
+}
+#define CNA_CONV_CON2_CSC_DO_EN__MASK				0x00000002
+#define CNA_CONV_CON2_CSC_DO_EN__SHIFT				1
+static inline uint32_t CNA_CONV_CON2_CSC_DO_EN(uint32_t val)
+{
+	return ((val) << CNA_CONV_CON2_CSC_DO_EN__SHIFT) & CNA_CONV_CON2_CSC_DO_EN__MASK;
+}
+#define CNA_CONV_CON2_CMD_FIFO_SRST__MASK			0x00000001
+#define CNA_CONV_CON2_CMD_FIFO_SRST__SHIFT			0
+static inline uint32_t CNA_CONV_CON2_CMD_FIFO_SRST(uint32_t val)
+{
+	return ((val) << CNA_CONV_CON2_CMD_FIFO_SRST__SHIFT) & CNA_CONV_CON2_CMD_FIFO_SRST__MASK;
+}
+
+#define REG_CNA_CONV_CON3					0x00001014
+#define CNA_CONV_CON3_RESERVED_0__MASK				0x80000000
+#define CNA_CONV_CON3_RESERVED_0__SHIFT				31
+static inline uint32_t CNA_CONV_CON3_RESERVED_0(uint32_t val)
+{
+	return ((val) << CNA_CONV_CON3_RESERVED_0__SHIFT) & CNA_CONV_CON3_RESERVED_0__MASK;
+}
+#define CNA_CONV_CON3_NN_MODE__MASK				0x70000000
+#define CNA_CONV_CON3_NN_MODE__SHIFT				28
+static inline uint32_t CNA_CONV_CON3_NN_MODE(uint32_t val)
+{
+	return ((val) << CNA_CONV_CON3_NN_MODE__SHIFT) & CNA_CONV_CON3_NN_MODE__MASK;
+}
+#define CNA_CONV_CON3_RESERVED_1__MASK				0x0c000000
+#define CNA_CONV_CON3_RESERVED_1__SHIFT				26
+static inline uint32_t CNA_CONV_CON3_RESERVED_1(uint32_t val)
+{
+	return ((val) << CNA_CONV_CON3_RESERVED_1__SHIFT) & CNA_CONV_CON3_RESERVED_1__MASK;
+}
+#define CNA_CONV_CON3_ATROUS_Y_DILATION__MASK			0x03e00000
+#define CNA_CONV_CON3_ATROUS_Y_DILATION__SHIFT			21
+static inline uint32_t CNA_CONV_CON3_ATROUS_Y_DILATION(uint32_t val)
+{
+	return ((val) << CNA_CONV_CON3_ATROUS_Y_DILATION__SHIFT) & CNA_CONV_CON3_ATROUS_Y_DILATION__MASK;
+}
+#define CNA_CONV_CON3_ATROUS_X_DILATION__MASK			0x001f0000
+#define CNA_CONV_CON3_ATROUS_X_DILATION__SHIFT			16
+static inline uint32_t CNA_CONV_CON3_ATROUS_X_DILATION(uint32_t val)
+{
+	return ((val) << CNA_CONV_CON3_ATROUS_X_DILATION__SHIFT) & CNA_CONV_CON3_ATROUS_X_DILATION__MASK;
+}
+#define CNA_CONV_CON3_RESERVED_2__MASK				0x0000c000
+#define CNA_CONV_CON3_RESERVED_2__SHIFT				14
+static inline uint32_t CNA_CONV_CON3_RESERVED_2(uint32_t val)
+{
+	return ((val) << CNA_CONV_CON3_RESERVED_2__SHIFT) & CNA_CONV_CON3_RESERVED_2__MASK;
+}
+#define CNA_CONV_CON3_DECONV_Y_STRIDE__MASK			0x00003800
+#define CNA_CONV_CON3_DECONV_Y_STRIDE__SHIFT			11
+static inline uint32_t CNA_CONV_CON3_DECONV_Y_STRIDE(uint32_t val)
+{
+	return ((val) << CNA_CONV_CON3_DECONV_Y_STRIDE__SHIFT) & CNA_CONV_CON3_DECONV_Y_STRIDE__MASK;
+}
+#define CNA_CONV_CON3_DECONV_X_STRIDE__MASK			0x00000700
+#define CNA_CONV_CON3_DECONV_X_STRIDE__SHIFT			8
+static inline uint32_t CNA_CONV_CON3_DECONV_X_STRIDE(uint32_t val)
+{
+	return ((val) << CNA_CONV_CON3_DECONV_X_STRIDE__SHIFT) & CNA_CONV_CON3_DECONV_X_STRIDE__MASK;
+}
+#define CNA_CONV_CON3_RESERVED_3__MASK				0x000000c0
+#define CNA_CONV_CON3_RESERVED_3__SHIFT				6
+static inline uint32_t CNA_CONV_CON3_RESERVED_3(uint32_t val)
+{
+	return ((val) << CNA_CONV_CON3_RESERVED_3__SHIFT) & CNA_CONV_CON3_RESERVED_3__MASK;
+}
+#define CNA_CONV_CON3_CONV_Y_STRIDE__MASK			0x00000038
+#define CNA_CONV_CON3_CONV_Y_STRIDE__SHIFT			3
+static inline uint32_t CNA_CONV_CON3_CONV_Y_STRIDE(uint32_t val)
+{
+	return ((val) << CNA_CONV_CON3_CONV_Y_STRIDE__SHIFT) & CNA_CONV_CON3_CONV_Y_STRIDE__MASK;
+}
+#define CNA_CONV_CON3_CONV_X_STRIDE__MASK			0x00000007
+#define CNA_CONV_CON3_CONV_X_STRIDE__SHIFT			0
+static inline uint32_t CNA_CONV_CON3_CONV_X_STRIDE(uint32_t val)
+{
+	return ((val) << CNA_CONV_CON3_CONV_X_STRIDE__SHIFT) & CNA_CONV_CON3_CONV_X_STRIDE__MASK;
+}
+
+#define REG_CNA_DATA_SIZE0					0x00001020
+#define CNA_DATA_SIZE0_RESERVED_0__MASK				0xf8000000
+#define CNA_DATA_SIZE0_RESERVED_0__SHIFT			27
+static inline uint32_t CNA_DATA_SIZE0_RESERVED_0(uint32_t val)
+{
+	return ((val) << CNA_DATA_SIZE0_RESERVED_0__SHIFT) & CNA_DATA_SIZE0_RESERVED_0__MASK;
+}
+#define CNA_DATA_SIZE0_DATAIN_WIDTH__MASK			0x07ff0000
+#define CNA_DATA_SIZE0_DATAIN_WIDTH__SHIFT			16
+static inline uint32_t CNA_DATA_SIZE0_DATAIN_WIDTH(uint32_t val)
+{
+	return ((val) << CNA_DATA_SIZE0_DATAIN_WIDTH__SHIFT) & CNA_DATA_SIZE0_DATAIN_WIDTH__MASK;
+}
+#define CNA_DATA_SIZE0_RESERVED_1__MASK				0x0000f800
+#define CNA_DATA_SIZE0_RESERVED_1__SHIFT			11
+static inline uint32_t CNA_DATA_SIZE0_RESERVED_1(uint32_t val)
+{
+	return ((val) << CNA_DATA_SIZE0_RESERVED_1__SHIFT) & CNA_DATA_SIZE0_RESERVED_1__MASK;
+}
+#define CNA_DATA_SIZE0_DATAIN_HEIGHT__MASK			0x000007ff
+#define CNA_DATA_SIZE0_DATAIN_HEIGHT__SHIFT			0
+static inline uint32_t CNA_DATA_SIZE0_DATAIN_HEIGHT(uint32_t val)
+{
+	return ((val) << CNA_DATA_SIZE0_DATAIN_HEIGHT__SHIFT) & CNA_DATA_SIZE0_DATAIN_HEIGHT__MASK;
+}
+
+#define REG_CNA_DATA_SIZE1					0x00001024
+#define CNA_DATA_SIZE1_RESERVED_0__MASK				0xc0000000
+#define CNA_DATA_SIZE1_RESERVED_0__SHIFT			30
+static inline uint32_t CNA_DATA_SIZE1_RESERVED_0(uint32_t val)
+{
+	return ((val) << CNA_DATA_SIZE1_RESERVED_0__SHIFT) & CNA_DATA_SIZE1_RESERVED_0__MASK;
+}
+#define CNA_DATA_SIZE1_DATAIN_CHANNEL_REAL__MASK		0x3fff0000
+#define CNA_DATA_SIZE1_DATAIN_CHANNEL_REAL__SHIFT		16
+static inline uint32_t CNA_DATA_SIZE1_DATAIN_CHANNEL_REAL(uint32_t val)
+{
+	return ((val) << CNA_DATA_SIZE1_DATAIN_CHANNEL_REAL__SHIFT) & CNA_DATA_SIZE1_DATAIN_CHANNEL_REAL__MASK;
+}
+#define CNA_DATA_SIZE1_DATAIN_CHANNEL__MASK			0x0000ffff
+#define CNA_DATA_SIZE1_DATAIN_CHANNEL__SHIFT			0
+static inline uint32_t CNA_DATA_SIZE1_DATAIN_CHANNEL(uint32_t val)
+{
+	return ((val) << CNA_DATA_SIZE1_DATAIN_CHANNEL__SHIFT) & CNA_DATA_SIZE1_DATAIN_CHANNEL__MASK;
+}
+
+#define REG_CNA_DATA_SIZE2					0x00001028
+#define CNA_DATA_SIZE2_RESERVED_0__MASK				0xfffff800
+#define CNA_DATA_SIZE2_RESERVED_0__SHIFT			11
+static inline uint32_t CNA_DATA_SIZE2_RESERVED_0(uint32_t val)
+{
+	return ((val) << CNA_DATA_SIZE2_RESERVED_0__SHIFT) & CNA_DATA_SIZE2_RESERVED_0__MASK;
+}
+#define CNA_DATA_SIZE2_DATAOUT_WIDTH__MASK			0x000007ff
+#define CNA_DATA_SIZE2_DATAOUT_WIDTH__SHIFT			0
+static inline uint32_t CNA_DATA_SIZE2_DATAOUT_WIDTH(uint32_t val)
+{
+	return ((val) << CNA_DATA_SIZE2_DATAOUT_WIDTH__SHIFT) & CNA_DATA_SIZE2_DATAOUT_WIDTH__MASK;
+}
+
+#define REG_CNA_DATA_SIZE3					0x0000102c
+#define CNA_DATA_SIZE3_RESERVED_0__MASK				0xff000000
+#define CNA_DATA_SIZE3_RESERVED_0__SHIFT			24
+static inline uint32_t CNA_DATA_SIZE3_RESERVED_0(uint32_t val)
+{
+	return ((val) << CNA_DATA_SIZE3_RESERVED_0__SHIFT) & CNA_DATA_SIZE3_RESERVED_0__MASK;
+}
+#define CNA_DATA_SIZE3_SURF_MODE__MASK				0x00c00000
+#define CNA_DATA_SIZE3_SURF_MODE__SHIFT				22
+static inline uint32_t CNA_DATA_SIZE3_SURF_MODE(uint32_t val)
+{
+	return ((val) << CNA_DATA_SIZE3_SURF_MODE__SHIFT) & CNA_DATA_SIZE3_SURF_MODE__MASK;
+}
+#define CNA_DATA_SIZE3_DATAOUT_ATOMICS__MASK			0x003fffff
+#define CNA_DATA_SIZE3_DATAOUT_ATOMICS__SHIFT			0
+static inline uint32_t CNA_DATA_SIZE3_DATAOUT_ATOMICS(uint32_t val)
+{
+	return ((val) << CNA_DATA_SIZE3_DATAOUT_ATOMICS__SHIFT) & CNA_DATA_SIZE3_DATAOUT_ATOMICS__MASK;
+}
+
+#define REG_CNA_WEIGHT_SIZE0					0x00001030
+#define CNA_WEIGHT_SIZE0_WEIGHT_BYTES__MASK			0xffffffff
+#define CNA_WEIGHT_SIZE0_WEIGHT_BYTES__SHIFT			0
+static inline uint32_t CNA_WEIGHT_SIZE0_WEIGHT_BYTES(uint32_t val)
+{
+	return ((val) << CNA_WEIGHT_SIZE0_WEIGHT_BYTES__SHIFT) & CNA_WEIGHT_SIZE0_WEIGHT_BYTES__MASK;
+}
+
+#define REG_CNA_WEIGHT_SIZE1					0x00001034
+#define CNA_WEIGHT_SIZE1_RESERVED_0__MASK			0xfff80000
+#define CNA_WEIGHT_SIZE1_RESERVED_0__SHIFT			19
+static inline uint32_t CNA_WEIGHT_SIZE1_RESERVED_0(uint32_t val)
+{
+	return ((val) << CNA_WEIGHT_SIZE1_RESERVED_0__SHIFT) & CNA_WEIGHT_SIZE1_RESERVED_0__MASK;
+}
+#define CNA_WEIGHT_SIZE1_WEIGHT_BYTES_PER_KERNEL__MASK		0x0007ffff
+#define CNA_WEIGHT_SIZE1_WEIGHT_BYTES_PER_KERNEL__SHIFT		0
+static inline uint32_t CNA_WEIGHT_SIZE1_WEIGHT_BYTES_PER_KERNEL(uint32_t val)
+{
+	return ((val) << CNA_WEIGHT_SIZE1_WEIGHT_BYTES_PER_KERNEL__SHIFT) & CNA_WEIGHT_SIZE1_WEIGHT_BYTES_PER_KERNEL__MASK;
+}
+
+#define REG_CNA_WEIGHT_SIZE2					0x00001038
+#define CNA_WEIGHT_SIZE2_RESERVED_0__MASK			0xe0000000
+#define CNA_WEIGHT_SIZE2_RESERVED_0__SHIFT			29
+static inline uint32_t CNA_WEIGHT_SIZE2_RESERVED_0(uint32_t val)
+{
+	return ((val) << CNA_WEIGHT_SIZE2_RESERVED_0__SHIFT) & CNA_WEIGHT_SIZE2_RESERVED_0__MASK;
+}
+#define CNA_WEIGHT_SIZE2_WEIGHT_WIDTH__MASK			0x1f000000
+#define CNA_WEIGHT_SIZE2_WEIGHT_WIDTH__SHIFT			24
+static inline uint32_t CNA_WEIGHT_SIZE2_WEIGHT_WIDTH(uint32_t val)
+{
+	return ((val) << CNA_WEIGHT_SIZE2_WEIGHT_WIDTH__SHIFT) & CNA_WEIGHT_SIZE2_WEIGHT_WIDTH__MASK;
+}
+#define CNA_WEIGHT_SIZE2_RESERVED_1__MASK			0x00e00000
+#define CNA_WEIGHT_SIZE2_RESERVED_1__SHIFT			21
+static inline uint32_t CNA_WEIGHT_SIZE2_RESERVED_1(uint32_t val)
+{
+	return ((val) << CNA_WEIGHT_SIZE2_RESERVED_1__SHIFT) & CNA_WEIGHT_SIZE2_RESERVED_1__MASK;
+}
+#define CNA_WEIGHT_SIZE2_WEIGHT_HEIGHT__MASK			0x001f0000
+#define CNA_WEIGHT_SIZE2_WEIGHT_HEIGHT__SHIFT			16
+static inline uint32_t CNA_WEIGHT_SIZE2_WEIGHT_HEIGHT(uint32_t val)
+{
+	return ((val) << CNA_WEIGHT_SIZE2_WEIGHT_HEIGHT__SHIFT) & CNA_WEIGHT_SIZE2_WEIGHT_HEIGHT__MASK;
+}
+#define CNA_WEIGHT_SIZE2_RESERVED_2__MASK			0x0000c000
+#define CNA_WEIGHT_SIZE2_RESERVED_2__SHIFT			14
+static inline uint32_t CNA_WEIGHT_SIZE2_RESERVED_2(uint32_t val)
+{
+	return ((val) << CNA_WEIGHT_SIZE2_RESERVED_2__SHIFT) & CNA_WEIGHT_SIZE2_RESERVED_2__MASK;
+}
+#define CNA_WEIGHT_SIZE2_WEIGHT_KERNELS__MASK			0x00003fff
+#define CNA_WEIGHT_SIZE2_WEIGHT_KERNELS__SHIFT			0
+static inline uint32_t CNA_WEIGHT_SIZE2_WEIGHT_KERNELS(uint32_t val)
+{
+	return ((val) << CNA_WEIGHT_SIZE2_WEIGHT_KERNELS__SHIFT) & CNA_WEIGHT_SIZE2_WEIGHT_KERNELS__MASK;
+}
+
+#define REG_CNA_CBUF_CON0					0x00001040
+#define CNA_CBUF_CON0_RESERVED_0__MASK				0xffffc000
+#define CNA_CBUF_CON0_RESERVED_0__SHIFT				14
+static inline uint32_t CNA_CBUF_CON0_RESERVED_0(uint32_t val)
+{
+	return ((val) << CNA_CBUF_CON0_RESERVED_0__SHIFT) & CNA_CBUF_CON0_RESERVED_0__MASK;
+}
+#define CNA_CBUF_CON0_WEIGHT_REUSE__MASK			0x00002000
+#define CNA_CBUF_CON0_WEIGHT_REUSE__SHIFT			13
+static inline uint32_t CNA_CBUF_CON0_WEIGHT_REUSE(uint32_t val)
+{
+	return ((val) << CNA_CBUF_CON0_WEIGHT_REUSE__SHIFT) & CNA_CBUF_CON0_WEIGHT_REUSE__MASK;
+}
+#define CNA_CBUF_CON0_DATA_REUSE__MASK				0x00001000
+#define CNA_CBUF_CON0_DATA_REUSE__SHIFT				12
+static inline uint32_t CNA_CBUF_CON0_DATA_REUSE(uint32_t val)
+{
+	return ((val) << CNA_CBUF_CON0_DATA_REUSE__SHIFT) & CNA_CBUF_CON0_DATA_REUSE__MASK;
+}
+#define CNA_CBUF_CON0_RESERVED_1__MASK				0x00000800
+#define CNA_CBUF_CON0_RESERVED_1__SHIFT				11
+static inline uint32_t CNA_CBUF_CON0_RESERVED_1(uint32_t val)
+{
+	return ((val) << CNA_CBUF_CON0_RESERVED_1__SHIFT) & CNA_CBUF_CON0_RESERVED_1__MASK;
+}
+#define CNA_CBUF_CON0_FC_DATA_BANK__MASK			0x00000700
+#define CNA_CBUF_CON0_FC_DATA_BANK__SHIFT			8
+static inline uint32_t CNA_CBUF_CON0_FC_DATA_BANK(uint32_t val)
+{
+	return ((val) << CNA_CBUF_CON0_FC_DATA_BANK__SHIFT) & CNA_CBUF_CON0_FC_DATA_BANK__MASK;
+}
+#define CNA_CBUF_CON0_WEIGHT_BANK__MASK				0x000000f0
+#define CNA_CBUF_CON0_WEIGHT_BANK__SHIFT			4
+static inline uint32_t CNA_CBUF_CON0_WEIGHT_BANK(uint32_t val)
+{
+	return ((val) << CNA_CBUF_CON0_WEIGHT_BANK__SHIFT) & CNA_CBUF_CON0_WEIGHT_BANK__MASK;
+}
+#define CNA_CBUF_CON0_DATA_BANK__MASK				0x0000000f
+#define CNA_CBUF_CON0_DATA_BANK__SHIFT				0
+static inline uint32_t CNA_CBUF_CON0_DATA_BANK(uint32_t val)
+{
+	return ((val) << CNA_CBUF_CON0_DATA_BANK__SHIFT) & CNA_CBUF_CON0_DATA_BANK__MASK;
+}
+
+#define REG_CNA_CBUF_CON1					0x00001044
+#define CNA_CBUF_CON1_RESERVED_0__MASK				0xffffc000
+#define CNA_CBUF_CON1_RESERVED_0__SHIFT				14
+static inline uint32_t CNA_CBUF_CON1_RESERVED_0(uint32_t val)
+{
+	return ((val) << CNA_CBUF_CON1_RESERVED_0__SHIFT) & CNA_CBUF_CON1_RESERVED_0__MASK;
+}
+#define CNA_CBUF_CON1_DATA_ENTRIES__MASK			0x00003fff
+#define CNA_CBUF_CON1_DATA_ENTRIES__SHIFT			0
+static inline uint32_t CNA_CBUF_CON1_DATA_ENTRIES(uint32_t val)
+{
+	return ((val) << CNA_CBUF_CON1_DATA_ENTRIES__SHIFT) & CNA_CBUF_CON1_DATA_ENTRIES__MASK;
+}
+
+#define REG_CNA_CVT_CON0					0x0000104c
+#define CNA_CVT_CON0_RESERVED_0__MASK				0xf0000000
+#define CNA_CVT_CON0_RESERVED_0__SHIFT				28
+static inline uint32_t CNA_CVT_CON0_RESERVED_0(uint32_t val)
+{
+	return ((val) << CNA_CVT_CON0_RESERVED_0__SHIFT) & CNA_CVT_CON0_RESERVED_0__MASK;
+}
+#define CNA_CVT_CON0_CVT_TRUNCATE_3__MASK			0x0fc00000
+#define CNA_CVT_CON0_CVT_TRUNCATE_3__SHIFT			22
+static inline uint32_t CNA_CVT_CON0_CVT_TRUNCATE_3(uint32_t val)
+{
+	return ((val) << CNA_CVT_CON0_CVT_TRUNCATE_3__SHIFT) & CNA_CVT_CON0_CVT_TRUNCATE_3__MASK;
+}
+#define CNA_CVT_CON0_CVT_TRUNCATE_2__MASK			0x003f0000
+#define CNA_CVT_CON0_CVT_TRUNCATE_2__SHIFT			16
+static inline uint32_t CNA_CVT_CON0_CVT_TRUNCATE_2(uint32_t val)
+{
+	return ((val) << CNA_CVT_CON0_CVT_TRUNCATE_2__SHIFT) & CNA_CVT_CON0_CVT_TRUNCATE_2__MASK;
+}
+#define CNA_CVT_CON0_CVT_TRUNCATE_1__MASK			0x0000fc00
+#define CNA_CVT_CON0_CVT_TRUNCATE_1__SHIFT			10
+static inline uint32_t CNA_CVT_CON0_CVT_TRUNCATE_1(uint32_t val)
+{
+	return ((val) << CNA_CVT_CON0_CVT_TRUNCATE_1__SHIFT) & CNA_CVT_CON0_CVT_TRUNCATE_1__MASK;
+}
+#define CNA_CVT_CON0_CVT_TRUNCATE_0__MASK			0x000003f0
+#define CNA_CVT_CON0_CVT_TRUNCATE_0__SHIFT			4
+static inline uint32_t CNA_CVT_CON0_CVT_TRUNCATE_0(uint32_t val)
+{
+	return ((val) << CNA_CVT_CON0_CVT_TRUNCATE_0__SHIFT) & CNA_CVT_CON0_CVT_TRUNCATE_0__MASK;
+}
+#define CNA_CVT_CON0_DATA_SIGN__MASK				0x00000008
+#define CNA_CVT_CON0_DATA_SIGN__SHIFT				3
+static inline uint32_t CNA_CVT_CON0_DATA_SIGN(uint32_t val)
+{
+	return ((val) << CNA_CVT_CON0_DATA_SIGN__SHIFT) & CNA_CVT_CON0_DATA_SIGN__MASK;
+}
+#define CNA_CVT_CON0_ROUND_TYPE__MASK				0x00000004
+#define CNA_CVT_CON0_ROUND_TYPE__SHIFT				2
+static inline uint32_t CNA_CVT_CON0_ROUND_TYPE(uint32_t val)
+{
+	return ((val) << CNA_CVT_CON0_ROUND_TYPE__SHIFT) & CNA_CVT_CON0_ROUND_TYPE__MASK;
+}
+#define CNA_CVT_CON0_CVT_TYPE__MASK				0x00000002
+#define CNA_CVT_CON0_CVT_TYPE__SHIFT				1
+static inline uint32_t CNA_CVT_CON0_CVT_TYPE(uint32_t val)
+{
+	return ((val) << CNA_CVT_CON0_CVT_TYPE__SHIFT) & CNA_CVT_CON0_CVT_TYPE__MASK;
+}
+#define CNA_CVT_CON0_CVT_BYPASS__MASK				0x00000001
+#define CNA_CVT_CON0_CVT_BYPASS__SHIFT				0
+static inline uint32_t CNA_CVT_CON0_CVT_BYPASS(uint32_t val)
+{
+	return ((val) << CNA_CVT_CON0_CVT_BYPASS__SHIFT) & CNA_CVT_CON0_CVT_BYPASS__MASK;
+}
+
+#define REG_CNA_CVT_CON1					0x00001050
+#define CNA_CVT_CON1_CVT_SCALE0__MASK				0xffff0000
+#define CNA_CVT_CON1_CVT_SCALE0__SHIFT				16
+static inline uint32_t CNA_CVT_CON1_CVT_SCALE0(uint32_t val)
+{
+	return ((val) << CNA_CVT_CON1_CVT_SCALE0__SHIFT) & CNA_CVT_CON1_CVT_SCALE0__MASK;
+}
+#define CNA_CVT_CON1_CVT_OFFSET0__MASK				0x0000ffff
+#define CNA_CVT_CON1_CVT_OFFSET0__SHIFT				0
+static inline uint32_t CNA_CVT_CON1_CVT_OFFSET0(uint32_t val)
+{
+	return ((val) << CNA_CVT_CON1_CVT_OFFSET0__SHIFT) & CNA_CVT_CON1_CVT_OFFSET0__MASK;
+}
+
+#define REG_CNA_CVT_CON2					0x00001054
+#define CNA_CVT_CON2_CVT_SCALE1__MASK				0xffff0000
+#define CNA_CVT_CON2_CVT_SCALE1__SHIFT				16
+static inline uint32_t CNA_CVT_CON2_CVT_SCALE1(uint32_t val)
+{
+	return ((val) << CNA_CVT_CON2_CVT_SCALE1__SHIFT) & CNA_CVT_CON2_CVT_SCALE1__MASK;
+}
+#define CNA_CVT_CON2_CVT_OFFSET1__MASK				0x0000ffff
+#define CNA_CVT_CON2_CVT_OFFSET1__SHIFT				0
+static inline uint32_t CNA_CVT_CON2_CVT_OFFSET1(uint32_t val)
+{
+	return ((val) << CNA_CVT_CON2_CVT_OFFSET1__SHIFT) & CNA_CVT_CON2_CVT_OFFSET1__MASK;
+}
+
+#define REG_CNA_CVT_CON3					0x00001058
+#define CNA_CVT_CON3_CVT_SCALE2__MASK				0xffff0000
+#define CNA_CVT_CON3_CVT_SCALE2__SHIFT				16
+static inline uint32_t CNA_CVT_CON3_CVT_SCALE2(uint32_t val)
+{
+	return ((val) << CNA_CVT_CON3_CVT_SCALE2__SHIFT) & CNA_CVT_CON3_CVT_SCALE2__MASK;
+}
+#define CNA_CVT_CON3_CVT_OFFSET2__MASK				0x0000ffff
+#define CNA_CVT_CON3_CVT_OFFSET2__SHIFT				0
+static inline uint32_t CNA_CVT_CON3_CVT_OFFSET2(uint32_t val)
+{
+	return ((val) << CNA_CVT_CON3_CVT_OFFSET2__SHIFT) & CNA_CVT_CON3_CVT_OFFSET2__MASK;
+}
+
+#define REG_CNA_CVT_CON4					0x0000105c
+#define CNA_CVT_CON4_CVT_SCALE3__MASK				0xffff0000
+#define CNA_CVT_CON4_CVT_SCALE3__SHIFT				16
+static inline uint32_t CNA_CVT_CON4_CVT_SCALE3(uint32_t val)
+{
+	return ((val) << CNA_CVT_CON4_CVT_SCALE3__SHIFT) & CNA_CVT_CON4_CVT_SCALE3__MASK;
+}
+#define CNA_CVT_CON4_CVT_OFFSET3__MASK				0x0000ffff
+#define CNA_CVT_CON4_CVT_OFFSET3__SHIFT				0
+static inline uint32_t CNA_CVT_CON4_CVT_OFFSET3(uint32_t val)
+{
+	return ((val) << CNA_CVT_CON4_CVT_OFFSET3__SHIFT) & CNA_CVT_CON4_CVT_OFFSET3__MASK;
+}
+
+#define REG_CNA_FC_CON0						0x00001060
+#define CNA_FC_CON0_FC_SKIP_DATA__MASK				0xffff0000
+#define CNA_FC_CON0_FC_SKIP_DATA__SHIFT				16
+static inline uint32_t CNA_FC_CON0_FC_SKIP_DATA(uint32_t val)
+{
+	return ((val) << CNA_FC_CON0_FC_SKIP_DATA__SHIFT) & CNA_FC_CON0_FC_SKIP_DATA__MASK;
+}
+#define CNA_FC_CON0_RESERVED_0__MASK				0x0000fffe
+#define CNA_FC_CON0_RESERVED_0__SHIFT				1
+static inline uint32_t CNA_FC_CON0_RESERVED_0(uint32_t val)
+{
+	return ((val) << CNA_FC_CON0_RESERVED_0__SHIFT) & CNA_FC_CON0_RESERVED_0__MASK;
+}
+#define CNA_FC_CON0_FC_SKIP_EN__MASK				0x00000001
+#define CNA_FC_CON0_FC_SKIP_EN__SHIFT				0
+static inline uint32_t CNA_FC_CON0_FC_SKIP_EN(uint32_t val)
+{
+	return ((val) << CNA_FC_CON0_FC_SKIP_EN__SHIFT) & CNA_FC_CON0_FC_SKIP_EN__MASK;
+}
+
+#define REG_CNA_FC_CON1						0x00001064
+#define CNA_FC_CON1_RESERVED_0__MASK				0xfffe0000
+#define CNA_FC_CON1_RESERVED_0__SHIFT				17
+static inline uint32_t CNA_FC_CON1_RESERVED_0(uint32_t val)
+{
+	return ((val) << CNA_FC_CON1_RESERVED_0__SHIFT) & CNA_FC_CON1_RESERVED_0__MASK;
+}
+#define CNA_FC_CON1_DATA_OFFSET__MASK				0x0001ffff
+#define CNA_FC_CON1_DATA_OFFSET__SHIFT				0
+static inline uint32_t CNA_FC_CON1_DATA_OFFSET(uint32_t val)
+{
+	return ((val) << CNA_FC_CON1_DATA_OFFSET__SHIFT) & CNA_FC_CON1_DATA_OFFSET__MASK;
+}
+
+#define REG_CNA_PAD_CON0					0x00001068
+#define CNA_PAD_CON0_RESERVED_0__MASK				0xffffff00
+#define CNA_PAD_CON0_RESERVED_0__SHIFT				8
+static inline uint32_t CNA_PAD_CON0_RESERVED_0(uint32_t val)
+{
+	return ((val) << CNA_PAD_CON0_RESERVED_0__SHIFT) & CNA_PAD_CON0_RESERVED_0__MASK;
+}
+#define CNA_PAD_CON0_PAD_LEFT__MASK				0x000000f0
+#define CNA_PAD_CON0_PAD_LEFT__SHIFT				4
+static inline uint32_t CNA_PAD_CON0_PAD_LEFT(uint32_t val)
+{
+	return ((val) << CNA_PAD_CON0_PAD_LEFT__SHIFT) & CNA_PAD_CON0_PAD_LEFT__MASK;
+}
+#define CNA_PAD_CON0_PAD_TOP__MASK				0x0000000f
+#define CNA_PAD_CON0_PAD_TOP__SHIFT				0
+static inline uint32_t CNA_PAD_CON0_PAD_TOP(uint32_t val)
+{
+	return ((val) << CNA_PAD_CON0_PAD_TOP__SHIFT) & CNA_PAD_CON0_PAD_TOP__MASK;
+}
+
+#define REG_CNA_FEATURE_DATA_ADDR				0x00001070
+#define CNA_FEATURE_DATA_ADDR_FEATURE_BASE_ADDR__MASK		0xffffffff
+#define CNA_FEATURE_DATA_ADDR_FEATURE_BASE_ADDR__SHIFT		0
+static inline uint32_t CNA_FEATURE_DATA_ADDR_FEATURE_BASE_ADDR(uint32_t val)
+{
+	return ((val) << CNA_FEATURE_DATA_ADDR_FEATURE_BASE_ADDR__SHIFT) & CNA_FEATURE_DATA_ADDR_FEATURE_BASE_ADDR__MASK;
+}
+
+#define REG_CNA_FC_CON2						0x00001074
+#define CNA_FC_CON2_RESERVED_0__MASK				0xfffe0000
+#define CNA_FC_CON2_RESERVED_0__SHIFT				17
+static inline uint32_t CNA_FC_CON2_RESERVED_0(uint32_t val)
+{
+	return ((val) << CNA_FC_CON2_RESERVED_0__SHIFT) & CNA_FC_CON2_RESERVED_0__MASK;
+}
+#define CNA_FC_CON2_WEIGHT_OFFSET__MASK				0x0001ffff
+#define CNA_FC_CON2_WEIGHT_OFFSET__SHIFT			0
+static inline uint32_t CNA_FC_CON2_WEIGHT_OFFSET(uint32_t val)
+{
+	return ((val) << CNA_FC_CON2_WEIGHT_OFFSET__SHIFT) & CNA_FC_CON2_WEIGHT_OFFSET__MASK;
+}
+
+#define REG_CNA_DMA_CON0					0x00001078
+#define CNA_DMA_CON0_OV4K_BYPASS__MASK				0x80000000
+#define CNA_DMA_CON0_OV4K_BYPASS__SHIFT				31
+static inline uint32_t CNA_DMA_CON0_OV4K_BYPASS(uint32_t val)
+{
+	return ((val) << CNA_DMA_CON0_OV4K_BYPASS__SHIFT) & CNA_DMA_CON0_OV4K_BYPASS__MASK;
+}
+#define CNA_DMA_CON0_RESERVED_0__MASK				0x7ff00000
+#define CNA_DMA_CON0_RESERVED_0__SHIFT				20
+static inline uint32_t CNA_DMA_CON0_RESERVED_0(uint32_t val)
+{
+	return ((val) << CNA_DMA_CON0_RESERVED_0__SHIFT) & CNA_DMA_CON0_RESERVED_0__MASK;
+}
+#define CNA_DMA_CON0_WEIGHT_BURST_LEN__MASK			0x000f0000
+#define CNA_DMA_CON0_WEIGHT_BURST_LEN__SHIFT			16
+static inline uint32_t CNA_DMA_CON0_WEIGHT_BURST_LEN(uint32_t val)
+{
+	return ((val) << CNA_DMA_CON0_WEIGHT_BURST_LEN__SHIFT) & CNA_DMA_CON0_WEIGHT_BURST_LEN__MASK;
+}
+#define CNA_DMA_CON0_RESERVED_1__MASK				0x0000fff0
+#define CNA_DMA_CON0_RESERVED_1__SHIFT				4
+static inline uint32_t CNA_DMA_CON0_RESERVED_1(uint32_t val)
+{
+	return ((val) << CNA_DMA_CON0_RESERVED_1__SHIFT) & CNA_DMA_CON0_RESERVED_1__MASK;
+}
+#define CNA_DMA_CON0_DATA_BURST_LEN__MASK			0x0000000f
+#define CNA_DMA_CON0_DATA_BURST_LEN__SHIFT			0
+static inline uint32_t CNA_DMA_CON0_DATA_BURST_LEN(uint32_t val)
+{
+	return ((val) << CNA_DMA_CON0_DATA_BURST_LEN__SHIFT) & CNA_DMA_CON0_DATA_BURST_LEN__MASK;
+}
+
+#define REG_CNA_DMA_CON1					0x0000107c
+#define CNA_DMA_CON1_RESERVED_0__MASK				0xf0000000
+#define CNA_DMA_CON1_RESERVED_0__SHIFT				28
+static inline uint32_t CNA_DMA_CON1_RESERVED_0(uint32_t val)
+{
+	return ((val) << CNA_DMA_CON1_RESERVED_0__SHIFT) & CNA_DMA_CON1_RESERVED_0__MASK;
+}
+#define CNA_DMA_CON1_LINE_STRIDE__MASK				0x0fffffff
+#define CNA_DMA_CON1_LINE_STRIDE__SHIFT				0
+static inline uint32_t CNA_DMA_CON1_LINE_STRIDE(uint32_t val)
+{
+	return ((val) << CNA_DMA_CON1_LINE_STRIDE__SHIFT) & CNA_DMA_CON1_LINE_STRIDE__MASK;
+}
+
+#define REG_CNA_DMA_CON2					0x00001080
+#define CNA_DMA_CON2_RESERVED_0__MASK				0xf0000000
+#define CNA_DMA_CON2_RESERVED_0__SHIFT				28
+static inline uint32_t CNA_DMA_CON2_RESERVED_0(uint32_t val)
+{
+	return ((val) << CNA_DMA_CON2_RESERVED_0__SHIFT) & CNA_DMA_CON2_RESERVED_0__MASK;
+}
+#define CNA_DMA_CON2_SURF_STRIDE__MASK				0x0fffffff
+#define CNA_DMA_CON2_SURF_STRIDE__SHIFT				0
+static inline uint32_t CNA_DMA_CON2_SURF_STRIDE(uint32_t val)
+{
+	return ((val) << CNA_DMA_CON2_SURF_STRIDE__SHIFT) & CNA_DMA_CON2_SURF_STRIDE__MASK;
+}
+
+#define REG_CNA_FC_DATA_SIZE0					0x00001084
+#define CNA_FC_DATA_SIZE0_RESERVED_0__MASK			0xc0000000
+#define CNA_FC_DATA_SIZE0_RESERVED_0__SHIFT			30
+static inline uint32_t CNA_FC_DATA_SIZE0_RESERVED_0(uint32_t val)
+{
+	return ((val) << CNA_FC_DATA_SIZE0_RESERVED_0__SHIFT) & CNA_FC_DATA_SIZE0_RESERVED_0__MASK;
+}
+#define CNA_FC_DATA_SIZE0_DMA_WIDTH__MASK			0x3fff0000
+#define CNA_FC_DATA_SIZE0_DMA_WIDTH__SHIFT			16
+static inline uint32_t CNA_FC_DATA_SIZE0_DMA_WIDTH(uint32_t val)
+{
+	return ((val) << CNA_FC_DATA_SIZE0_DMA_WIDTH__SHIFT) & CNA_FC_DATA_SIZE0_DMA_WIDTH__MASK;
+}
+#define CNA_FC_DATA_SIZE0_RESERVED_1__MASK			0x0000f800
+#define CNA_FC_DATA_SIZE0_RESERVED_1__SHIFT			11
+static inline uint32_t CNA_FC_DATA_SIZE0_RESERVED_1(uint32_t val)
+{
+	return ((val) << CNA_FC_DATA_SIZE0_RESERVED_1__SHIFT) & CNA_FC_DATA_SIZE0_RESERVED_1__MASK;
+}
+#define CNA_FC_DATA_SIZE0_DMA_HEIGHT__MASK			0x000007ff
+#define CNA_FC_DATA_SIZE0_DMA_HEIGHT__SHIFT			0
+static inline uint32_t CNA_FC_DATA_SIZE0_DMA_HEIGHT(uint32_t val)
+{
+	return ((val) << CNA_FC_DATA_SIZE0_DMA_HEIGHT__SHIFT) & CNA_FC_DATA_SIZE0_DMA_HEIGHT__MASK;
+}
+
+#define REG_CNA_FC_DATA_SIZE1					0x00001088
+#define CNA_FC_DATA_SIZE1_RESERVED_0__MASK			0xffff0000
+#define CNA_FC_DATA_SIZE1_RESERVED_0__SHIFT			16
+static inline uint32_t CNA_FC_DATA_SIZE1_RESERVED_0(uint32_t val)
+{
+	return ((val) << CNA_FC_DATA_SIZE1_RESERVED_0__SHIFT) & CNA_FC_DATA_SIZE1_RESERVED_0__MASK;
+}
+#define CNA_FC_DATA_SIZE1_DMA_CHANNEL__MASK			0x0000ffff
+#define CNA_FC_DATA_SIZE1_DMA_CHANNEL__SHIFT			0
+static inline uint32_t CNA_FC_DATA_SIZE1_DMA_CHANNEL(uint32_t val)
+{
+	return ((val) << CNA_FC_DATA_SIZE1_DMA_CHANNEL__SHIFT) & CNA_FC_DATA_SIZE1_DMA_CHANNEL__MASK;
+}
+
+#define REG_CNA_CLK_GATE					0x00001090
+#define CNA_CLK_GATE_RESERVED_0__MASK				0xffffffe0
+#define CNA_CLK_GATE_RESERVED_0__SHIFT				5
+static inline uint32_t CNA_CLK_GATE_RESERVED_0(uint32_t val)
+{
+	return ((val) << CNA_CLK_GATE_RESERVED_0__SHIFT) & CNA_CLK_GATE_RESERVED_0__MASK;
+}
+#define CNA_CLK_GATE_CBUF_CS_DISABLE_CLKGATE__MASK		0x00000010
+#define CNA_CLK_GATE_CBUF_CS_DISABLE_CLKGATE__SHIFT		4
+static inline uint32_t CNA_CLK_GATE_CBUF_CS_DISABLE_CLKGATE(uint32_t val)
+{
+	return ((val) << CNA_CLK_GATE_CBUF_CS_DISABLE_CLKGATE__SHIFT) & CNA_CLK_GATE_CBUF_CS_DISABLE_CLKGATE__MASK;
+}
+#define CNA_CLK_GATE_RESERVED_1__MASK				0x00000008
+#define CNA_CLK_GATE_RESERVED_1__SHIFT				3
+static inline uint32_t CNA_CLK_GATE_RESERVED_1(uint32_t val)
+{
+	return ((val) << CNA_CLK_GATE_RESERVED_1__SHIFT) & CNA_CLK_GATE_RESERVED_1__MASK;
+}
+#define CNA_CLK_GATE_CSC_DISABLE_CLKGATE__MASK			0x00000004
+#define CNA_CLK_GATE_CSC_DISABLE_CLKGATE__SHIFT			2
+static inline uint32_t CNA_CLK_GATE_CSC_DISABLE_CLKGATE(uint32_t val)
+{
+	return ((val) << CNA_CLK_GATE_CSC_DISABLE_CLKGATE__SHIFT) & CNA_CLK_GATE_CSC_DISABLE_CLKGATE__MASK;
+}
+#define CNA_CLK_GATE_CNA_WEIGHT_DISABLE_CLKGATE__MASK		0x00000002
+#define CNA_CLK_GATE_CNA_WEIGHT_DISABLE_CLKGATE__SHIFT		1
+static inline uint32_t CNA_CLK_GATE_CNA_WEIGHT_DISABLE_CLKGATE(uint32_t val)
+{
+	return ((val) << CNA_CLK_GATE_CNA_WEIGHT_DISABLE_CLKGATE__SHIFT) & CNA_CLK_GATE_CNA_WEIGHT_DISABLE_CLKGATE__MASK;
+}
+#define CNA_CLK_GATE_CNA_FEATURE_DISABLE_CLKGATE__MASK		0x00000001
+#define CNA_CLK_GATE_CNA_FEATURE_DISABLE_CLKGATE__SHIFT		0
+static inline uint32_t CNA_CLK_GATE_CNA_FEATURE_DISABLE_CLKGATE(uint32_t val)
+{
+	return ((val) << CNA_CLK_GATE_CNA_FEATURE_DISABLE_CLKGATE__SHIFT) & CNA_CLK_GATE_CNA_FEATURE_DISABLE_CLKGATE__MASK;
+}
+
+#define REG_CNA_DCOMP_CTRL					0x00001100
+#define CNA_DCOMP_CTRL_RESERVED_0__MASK				0xfffffff0
+#define CNA_DCOMP_CTRL_RESERVED_0__SHIFT			4
+static inline uint32_t CNA_DCOMP_CTRL_RESERVED_0(uint32_t val)
+{
+	return ((val) << CNA_DCOMP_CTRL_RESERVED_0__SHIFT) & CNA_DCOMP_CTRL_RESERVED_0__MASK;
+}
+#define CNA_DCOMP_CTRL_WT_DEC_BYPASS__MASK			0x00000008
+#define CNA_DCOMP_CTRL_WT_DEC_BYPASS__SHIFT			3
+static inline uint32_t CNA_DCOMP_CTRL_WT_DEC_BYPASS(uint32_t val)
+{
+	return ((val) << CNA_DCOMP_CTRL_WT_DEC_BYPASS__SHIFT) & CNA_DCOMP_CTRL_WT_DEC_BYPASS__MASK;
+}
+#define CNA_DCOMP_CTRL_DECOMP_CONTROL__MASK			0x00000007
+#define CNA_DCOMP_CTRL_DECOMP_CONTROL__SHIFT			0
+static inline uint32_t CNA_DCOMP_CTRL_DECOMP_CONTROL(uint32_t val)
+{
+	return ((val) << CNA_DCOMP_CTRL_DECOMP_CONTROL__SHIFT) & CNA_DCOMP_CTRL_DECOMP_CONTROL__MASK;
+}
+
+#define REG_CNA_DCOMP_REGNUM					0x00001104
+#define CNA_DCOMP_REGNUM_DCOMP_REGNUM__MASK			0xffffffff
+#define CNA_DCOMP_REGNUM_DCOMP_REGNUM__SHIFT			0
+static inline uint32_t CNA_DCOMP_REGNUM_DCOMP_REGNUM(uint32_t val)
+{
+	return ((val) << CNA_DCOMP_REGNUM_DCOMP_REGNUM__SHIFT) & CNA_DCOMP_REGNUM_DCOMP_REGNUM__MASK;
+}
+
+#define REG_CNA_DCOMP_ADDR0					0x00001110
+#define CNA_DCOMP_ADDR0_DECOMPRESS_ADDR0__MASK			0xffffffff
+#define CNA_DCOMP_ADDR0_DECOMPRESS_ADDR0__SHIFT			0
+static inline uint32_t CNA_DCOMP_ADDR0_DECOMPRESS_ADDR0(uint32_t val)
+{
+	return ((val) << CNA_DCOMP_ADDR0_DECOMPRESS_ADDR0__SHIFT) & CNA_DCOMP_ADDR0_DECOMPRESS_ADDR0__MASK;
+}
+
+#define REG_CNA_DCOMP_AMOUNT0					0x00001140
+#define CNA_DCOMP_AMOUNT0_DCOMP_AMOUNT0__MASK			0xffffffff
+#define CNA_DCOMP_AMOUNT0_DCOMP_AMOUNT0__SHIFT			0
+static inline uint32_t CNA_DCOMP_AMOUNT0_DCOMP_AMOUNT0(uint32_t val)
+{
+	return ((val) << CNA_DCOMP_AMOUNT0_DCOMP_AMOUNT0__SHIFT) & CNA_DCOMP_AMOUNT0_DCOMP_AMOUNT0__MASK;
+}
+
+#define REG_CNA_DCOMP_AMOUNT1					0x00001144
+#define CNA_DCOMP_AMOUNT1_DCOMP_AMOUNT1__MASK			0xffffffff
+#define CNA_DCOMP_AMOUNT1_DCOMP_AMOUNT1__SHIFT			0
+static inline uint32_t CNA_DCOMP_AMOUNT1_DCOMP_AMOUNT1(uint32_t val)
+{
+	return ((val) << CNA_DCOMP_AMOUNT1_DCOMP_AMOUNT1__SHIFT) & CNA_DCOMP_AMOUNT1_DCOMP_AMOUNT1__MASK;
+}
+
+#define REG_CNA_DCOMP_AMOUNT2					0x00001148
+#define CNA_DCOMP_AMOUNT2_DCOMP_AMOUNT2__MASK			0xffffffff
+#define CNA_DCOMP_AMOUNT2_DCOMP_AMOUNT2__SHIFT			0
+static inline uint32_t CNA_DCOMP_AMOUNT2_DCOMP_AMOUNT2(uint32_t val)
+{
+	return ((val) << CNA_DCOMP_AMOUNT2_DCOMP_AMOUNT2__SHIFT) & CNA_DCOMP_AMOUNT2_DCOMP_AMOUNT2__MASK;
+}
+
+#define REG_CNA_DCOMP_AMOUNT3					0x0000114c
+#define CNA_DCOMP_AMOUNT3_DCOMP_AMOUNT3__MASK			0xffffffff
+#define CNA_DCOMP_AMOUNT3_DCOMP_AMOUNT3__SHIFT			0
+static inline uint32_t CNA_DCOMP_AMOUNT3_DCOMP_AMOUNT3(uint32_t val)
+{
+	return ((val) << CNA_DCOMP_AMOUNT3_DCOMP_AMOUNT3__SHIFT) & CNA_DCOMP_AMOUNT3_DCOMP_AMOUNT3__MASK;
+}
+
+#define REG_CNA_DCOMP_AMOUNT4					0x00001150
+#define CNA_DCOMP_AMOUNT4_DCOMP_AMOUNT4__MASK			0xffffffff
+#define CNA_DCOMP_AMOUNT4_DCOMP_AMOUNT4__SHIFT			0
+static inline uint32_t CNA_DCOMP_AMOUNT4_DCOMP_AMOUNT4(uint32_t val)
+{
+	return ((val) << CNA_DCOMP_AMOUNT4_DCOMP_AMOUNT4__SHIFT) & CNA_DCOMP_AMOUNT4_DCOMP_AMOUNT4__MASK;
+}
+
+#define REG_CNA_DCOMP_AMOUNT5					0x00001154
+#define CNA_DCOMP_AMOUNT5_DCOMP_AMOUNT5__MASK			0xffffffff
+#define CNA_DCOMP_AMOUNT5_DCOMP_AMOUNT5__SHIFT			0
+static inline uint32_t CNA_DCOMP_AMOUNT5_DCOMP_AMOUNT5(uint32_t val)
+{
+	return ((val) << CNA_DCOMP_AMOUNT5_DCOMP_AMOUNT5__SHIFT) & CNA_DCOMP_AMOUNT5_DCOMP_AMOUNT5__MASK;
+}
+
+#define REG_CNA_DCOMP_AMOUNT6					0x00001158
+#define CNA_DCOMP_AMOUNT6_DCOMP_AMOUNT6__MASK			0xffffffff
+#define CNA_DCOMP_AMOUNT6_DCOMP_AMOUNT6__SHIFT			0
+static inline uint32_t CNA_DCOMP_AMOUNT6_DCOMP_AMOUNT6(uint32_t val)
+{
+	return ((val) << CNA_DCOMP_AMOUNT6_DCOMP_AMOUNT6__SHIFT) & CNA_DCOMP_AMOUNT6_DCOMP_AMOUNT6__MASK;
+}
+
+#define REG_CNA_DCOMP_AMOUNT7					0x0000115c
+#define CNA_DCOMP_AMOUNT7_DCOMP_AMOUNT7__MASK			0xffffffff
+#define CNA_DCOMP_AMOUNT7_DCOMP_AMOUNT7__SHIFT			0
+static inline uint32_t CNA_DCOMP_AMOUNT7_DCOMP_AMOUNT7(uint32_t val)
+{
+	return ((val) << CNA_DCOMP_AMOUNT7_DCOMP_AMOUNT7__SHIFT) & CNA_DCOMP_AMOUNT7_DCOMP_AMOUNT7__MASK;
+}
+
+#define REG_CNA_DCOMP_AMOUNT8					0x00001160
+#define CNA_DCOMP_AMOUNT8_DCOMP_AMOUNT8__MASK			0xffffffff
+#define CNA_DCOMP_AMOUNT8_DCOMP_AMOUNT8__SHIFT			0
+static inline uint32_t CNA_DCOMP_AMOUNT8_DCOMP_AMOUNT8(uint32_t val)
+{
+	return ((val) << CNA_DCOMP_AMOUNT8_DCOMP_AMOUNT8__SHIFT) & CNA_DCOMP_AMOUNT8_DCOMP_AMOUNT8__MASK;
+}
+
+#define REG_CNA_DCOMP_AMOUNT9					0x00001164
+#define CNA_DCOMP_AMOUNT9_DCOMP_AMOUNT9__MASK			0xffffffff
+#define CNA_DCOMP_AMOUNT9_DCOMP_AMOUNT9__SHIFT			0
+static inline uint32_t CNA_DCOMP_AMOUNT9_DCOMP_AMOUNT9(uint32_t val)
+{
+	return ((val) << CNA_DCOMP_AMOUNT9_DCOMP_AMOUNT9__SHIFT) & CNA_DCOMP_AMOUNT9_DCOMP_AMOUNT9__MASK;
+}
+
+#define REG_CNA_DCOMP_AMOUNT10					0x00001168
+#define CNA_DCOMP_AMOUNT10_DCOMP_AMOUNT10__MASK			0xffffffff
+#define CNA_DCOMP_AMOUNT10_DCOMP_AMOUNT10__SHIFT		0
+static inline uint32_t CNA_DCOMP_AMOUNT10_DCOMP_AMOUNT10(uint32_t val)
+{
+	return ((val) << CNA_DCOMP_AMOUNT10_DCOMP_AMOUNT10__SHIFT) & CNA_DCOMP_AMOUNT10_DCOMP_AMOUNT10__MASK;
+}
+
+#define REG_CNA_DCOMP_AMOUNT11					0x0000116c
+#define CNA_DCOMP_AMOUNT11_DCOMP_AMOUNT11__MASK			0xffffffff
+#define CNA_DCOMP_AMOUNT11_DCOMP_AMOUNT11__SHIFT		0
+static inline uint32_t CNA_DCOMP_AMOUNT11_DCOMP_AMOUNT11(uint32_t val)
+{
+	return ((val) << CNA_DCOMP_AMOUNT11_DCOMP_AMOUNT11__SHIFT) & CNA_DCOMP_AMOUNT11_DCOMP_AMOUNT11__MASK;
+}
+
+#define REG_CNA_DCOMP_AMOUNT12					0x00001170
+#define CNA_DCOMP_AMOUNT12_DCOMP_AMOUNT12__MASK			0xffffffff
+#define CNA_DCOMP_AMOUNT12_DCOMP_AMOUNT12__SHIFT		0
+static inline uint32_t CNA_DCOMP_AMOUNT12_DCOMP_AMOUNT12(uint32_t val)
+{
+	return ((val) << CNA_DCOMP_AMOUNT12_DCOMP_AMOUNT12__SHIFT) & CNA_DCOMP_AMOUNT12_DCOMP_AMOUNT12__MASK;
+}
+
+#define REG_CNA_DCOMP_AMOUNT13					0x00001174
+#define CNA_DCOMP_AMOUNT13_DCOMP_AMOUNT13__MASK			0xffffffff
+#define CNA_DCOMP_AMOUNT13_DCOMP_AMOUNT13__SHIFT		0
+static inline uint32_t CNA_DCOMP_AMOUNT13_DCOMP_AMOUNT13(uint32_t val)
+{
+	return ((val) << CNA_DCOMP_AMOUNT13_DCOMP_AMOUNT13__SHIFT) & CNA_DCOMP_AMOUNT13_DCOMP_AMOUNT13__MASK;
+}
+
+#define REG_CNA_DCOMP_AMOUNT14					0x00001178
+#define CNA_DCOMP_AMOUNT14_DCOMP_AMOUNT14__MASK			0xffffffff
+#define CNA_DCOMP_AMOUNT14_DCOMP_AMOUNT14__SHIFT		0
+static inline uint32_t CNA_DCOMP_AMOUNT14_DCOMP_AMOUNT14(uint32_t val)
+{
+	return ((val) << CNA_DCOMP_AMOUNT14_DCOMP_AMOUNT14__SHIFT) & CNA_DCOMP_AMOUNT14_DCOMP_AMOUNT14__MASK;
+}
+
+#define REG_CNA_DCOMP_AMOUNT15					0x0000117c
+#define CNA_DCOMP_AMOUNT15_DCOMP_AMOUNT15__MASK			0xffffffff
+#define CNA_DCOMP_AMOUNT15_DCOMP_AMOUNT15__SHIFT		0
+static inline uint32_t CNA_DCOMP_AMOUNT15_DCOMP_AMOUNT15(uint32_t val)
+{
+	return ((val) << CNA_DCOMP_AMOUNT15_DCOMP_AMOUNT15__SHIFT) & CNA_DCOMP_AMOUNT15_DCOMP_AMOUNT15__MASK;
+}
+
+#define REG_CNA_CVT_CON5					0x00001180
+#define CNA_CVT_CON5_PER_CHANNEL_CVT_EN__MASK			0xffffffff
+#define CNA_CVT_CON5_PER_CHANNEL_CVT_EN__SHIFT			0
+static inline uint32_t CNA_CVT_CON5_PER_CHANNEL_CVT_EN(uint32_t val)
+{
+	return ((val) << CNA_CVT_CON5_PER_CHANNEL_CVT_EN__SHIFT) & CNA_CVT_CON5_PER_CHANNEL_CVT_EN__MASK;
+}
+
+#define REG_CNA_PAD_CON1					0x00001184
+#define CNA_PAD_CON1_PAD_VALUE__MASK				0xffffffff
+#define CNA_PAD_CON1_PAD_VALUE__SHIFT				0
+static inline uint32_t CNA_PAD_CON1_PAD_VALUE(uint32_t val)
+{
+	return ((val) << CNA_PAD_CON1_PAD_VALUE__SHIFT) & CNA_PAD_CON1_PAD_VALUE__MASK;
+}
+
+#define REG_CORE_S_STATUS					0x00003000
+#define CORE_S_STATUS_RESERVED_0__MASK				0xfffc0000
+#define CORE_S_STATUS_RESERVED_0__SHIFT				18
+static inline uint32_t CORE_S_STATUS_RESERVED_0(uint32_t val)
+{
+	return ((val) << CORE_S_STATUS_RESERVED_0__SHIFT) & CORE_S_STATUS_RESERVED_0__MASK;
+}
+#define CORE_S_STATUS_STATUS_1__MASK				0x00030000
+#define CORE_S_STATUS_STATUS_1__SHIFT				16
+static inline uint32_t CORE_S_STATUS_STATUS_1(uint32_t val)
+{
+	return ((val) << CORE_S_STATUS_STATUS_1__SHIFT) & CORE_S_STATUS_STATUS_1__MASK;
+}
+#define CORE_S_STATUS_RESERVED_1__MASK				0x0000fffc
+#define CORE_S_STATUS_RESERVED_1__SHIFT				2
+static inline uint32_t CORE_S_STATUS_RESERVED_1(uint32_t val)
+{
+	return ((val) << CORE_S_STATUS_RESERVED_1__SHIFT) & CORE_S_STATUS_RESERVED_1__MASK;
+}
+#define CORE_S_STATUS_STATUS_0__MASK				0x00000003
+#define CORE_S_STATUS_STATUS_0__SHIFT				0
+static inline uint32_t CORE_S_STATUS_STATUS_0(uint32_t val)
+{
+	return ((val) << CORE_S_STATUS_STATUS_0__SHIFT) & CORE_S_STATUS_STATUS_0__MASK;
+}
+
+#define REG_CORE_S_POINTER					0x00003004
+#define CORE_S_POINTER_RESERVED_0__MASK				0xfffe0000
+#define CORE_S_POINTER_RESERVED_0__SHIFT			17
+static inline uint32_t CORE_S_POINTER_RESERVED_0(uint32_t val)
+{
+	return ((val) << CORE_S_POINTER_RESERVED_0__SHIFT) & CORE_S_POINTER_RESERVED_0__MASK;
+}
+#define CORE_S_POINTER_EXECUTER__MASK				0x00010000
+#define CORE_S_POINTER_EXECUTER__SHIFT				16
+static inline uint32_t CORE_S_POINTER_EXECUTER(uint32_t val)
+{
+	return ((val) << CORE_S_POINTER_EXECUTER__SHIFT) & CORE_S_POINTER_EXECUTER__MASK;
+}
+#define CORE_S_POINTER_RESERVED_1__MASK				0x0000ffc0
+#define CORE_S_POINTER_RESERVED_1__SHIFT			6
+static inline uint32_t CORE_S_POINTER_RESERVED_1(uint32_t val)
+{
+	return ((val) << CORE_S_POINTER_RESERVED_1__SHIFT) & CORE_S_POINTER_RESERVED_1__MASK;
+}
+#define CORE_S_POINTER_EXECUTER_PP_CLEAR__MASK			0x00000020
+#define CORE_S_POINTER_EXECUTER_PP_CLEAR__SHIFT			5
+static inline uint32_t CORE_S_POINTER_EXECUTER_PP_CLEAR(uint32_t val)
+{
+	return ((val) << CORE_S_POINTER_EXECUTER_PP_CLEAR__SHIFT) & CORE_S_POINTER_EXECUTER_PP_CLEAR__MASK;
+}
+#define CORE_S_POINTER_POINTER_PP_CLEAR__MASK			0x00000010
+#define CORE_S_POINTER_POINTER_PP_CLEAR__SHIFT			4
+static inline uint32_t CORE_S_POINTER_POINTER_PP_CLEAR(uint32_t val)
+{
+	return ((val) << CORE_S_POINTER_POINTER_PP_CLEAR__SHIFT) & CORE_S_POINTER_POINTER_PP_CLEAR__MASK;
+}
+#define CORE_S_POINTER_POINTER_PP_MODE__MASK			0x00000008
+#define CORE_S_POINTER_POINTER_PP_MODE__SHIFT			3
+static inline uint32_t CORE_S_POINTER_POINTER_PP_MODE(uint32_t val)
+{
+	return ((val) << CORE_S_POINTER_POINTER_PP_MODE__SHIFT) & CORE_S_POINTER_POINTER_PP_MODE__MASK;
+}
+#define CORE_S_POINTER_EXECUTER_PP_EN__MASK			0x00000004
+#define CORE_S_POINTER_EXECUTER_PP_EN__SHIFT			2
+static inline uint32_t CORE_S_POINTER_EXECUTER_PP_EN(uint32_t val)
+{
+	return ((val) << CORE_S_POINTER_EXECUTER_PP_EN__SHIFT) & CORE_S_POINTER_EXECUTER_PP_EN__MASK;
+}
+#define CORE_S_POINTER_POINTER_PP_EN__MASK			0x00000002
+#define CORE_S_POINTER_POINTER_PP_EN__SHIFT			1
+static inline uint32_t CORE_S_POINTER_POINTER_PP_EN(uint32_t val)
+{
+	return ((val) << CORE_S_POINTER_POINTER_PP_EN__SHIFT) & CORE_S_POINTER_POINTER_PP_EN__MASK;
+}
+#define CORE_S_POINTER_POINTER__MASK				0x00000001
+#define CORE_S_POINTER_POINTER__SHIFT				0
+static inline uint32_t CORE_S_POINTER_POINTER(uint32_t val)
+{
+	return ((val) << CORE_S_POINTER_POINTER__SHIFT) & CORE_S_POINTER_POINTER__MASK;
+}
+
+#define REG_CORE_OPERATION_ENABLE				0x00003008
+#define CORE_OPERATION_ENABLE_RESERVED_0__MASK			0xfffffffe
+#define CORE_OPERATION_ENABLE_RESERVED_0__SHIFT			1
+static inline uint32_t CORE_OPERATION_ENABLE_RESERVED_0(uint32_t val)
+{
+	return ((val) << CORE_OPERATION_ENABLE_RESERVED_0__SHIFT) & CORE_OPERATION_ENABLE_RESERVED_0__MASK;
+}
+#define CORE_OPERATION_ENABLE_OP_EN__MASK			0x00000001
+#define CORE_OPERATION_ENABLE_OP_EN__SHIFT			0
+static inline uint32_t CORE_OPERATION_ENABLE_OP_EN(uint32_t val)
+{
+	return ((val) << CORE_OPERATION_ENABLE_OP_EN__SHIFT) & CORE_OPERATION_ENABLE_OP_EN__MASK;
+}
+
+#define REG_CORE_MAC_GATING					0x0000300c
+#define CORE_MAC_GATING_RESERVED_0__MASK			0xf8000000
+#define CORE_MAC_GATING_RESERVED_0__SHIFT			27
+static inline uint32_t CORE_MAC_GATING_RESERVED_0(uint32_t val)
+{
+	return ((val) << CORE_MAC_GATING_RESERVED_0__SHIFT) & CORE_MAC_GATING_RESERVED_0__MASK;
+}
+#define CORE_MAC_GATING_SLCG_OP_EN__MASK			0x07ffffff
+#define CORE_MAC_GATING_SLCG_OP_EN__SHIFT			0
+static inline uint32_t CORE_MAC_GATING_SLCG_OP_EN(uint32_t val)
+{
+	return ((val) << CORE_MAC_GATING_SLCG_OP_EN__SHIFT) & CORE_MAC_GATING_SLCG_OP_EN__MASK;
+}
+
+#define REG_CORE_MISC_CFG					0x00003010
+#define CORE_MISC_CFG_RESERVED_0__MASK				0xfff00000
+#define CORE_MISC_CFG_RESERVED_0__SHIFT				20
+static inline uint32_t CORE_MISC_CFG_RESERVED_0(uint32_t val)
+{
+	return ((val) << CORE_MISC_CFG_RESERVED_0__SHIFT) & CORE_MISC_CFG_RESERVED_0__MASK;
+}
+#define CORE_MISC_CFG_SOFT_GATING__MASK				0x000fc000
+#define CORE_MISC_CFG_SOFT_GATING__SHIFT			14
+static inline uint32_t CORE_MISC_CFG_SOFT_GATING(uint32_t val)
+{
+	return ((val) << CORE_MISC_CFG_SOFT_GATING__SHIFT) & CORE_MISC_CFG_SOFT_GATING__MASK;
+}
+#define CORE_MISC_CFG_RESERVED_1__MASK				0x00003800
+#define CORE_MISC_CFG_RESERVED_1__SHIFT				11
+static inline uint32_t CORE_MISC_CFG_RESERVED_1(uint32_t val)
+{
+	return ((val) << CORE_MISC_CFG_RESERVED_1__SHIFT) & CORE_MISC_CFG_RESERVED_1__MASK;
+}
+#define CORE_MISC_CFG_PROC_PRECISION__MASK			0x00000700
+#define CORE_MISC_CFG_PROC_PRECISION__SHIFT			8
+static inline uint32_t CORE_MISC_CFG_PROC_PRECISION(uint32_t val)
+{
+	return ((val) << CORE_MISC_CFG_PROC_PRECISION__SHIFT) & CORE_MISC_CFG_PROC_PRECISION__MASK;
+}
+#define CORE_MISC_CFG_RESERVED_2__MASK				0x000000fc
+#define CORE_MISC_CFG_RESERVED_2__SHIFT				2
+static inline uint32_t CORE_MISC_CFG_RESERVED_2(uint32_t val)
+{
+	return ((val) << CORE_MISC_CFG_RESERVED_2__SHIFT) & CORE_MISC_CFG_RESERVED_2__MASK;
+}
+#define CORE_MISC_CFG_DW_EN__MASK				0x00000002
+#define CORE_MISC_CFG_DW_EN__SHIFT				1
+static inline uint32_t CORE_MISC_CFG_DW_EN(uint32_t val)
+{
+	return ((val) << CORE_MISC_CFG_DW_EN__SHIFT) & CORE_MISC_CFG_DW_EN__MASK;
+}
+#define CORE_MISC_CFG_QD_EN__MASK				0x00000001
+#define CORE_MISC_CFG_QD_EN__SHIFT				0
+static inline uint32_t CORE_MISC_CFG_QD_EN(uint32_t val)
+{
+	return ((val) << CORE_MISC_CFG_QD_EN__SHIFT) & CORE_MISC_CFG_QD_EN__MASK;
+}
+
+#define REG_CORE_DATAOUT_SIZE_0					0x00003014
+#define CORE_DATAOUT_SIZE_0_DATAOUT_HEIGHT__MASK		0xffff0000
+#define CORE_DATAOUT_SIZE_0_DATAOUT_HEIGHT__SHIFT		16
+static inline uint32_t CORE_DATAOUT_SIZE_0_DATAOUT_HEIGHT(uint32_t val)
+{
+	return ((val) << CORE_DATAOUT_SIZE_0_DATAOUT_HEIGHT__SHIFT) & CORE_DATAOUT_SIZE_0_DATAOUT_HEIGHT__MASK;
+}
+#define CORE_DATAOUT_SIZE_0_DATAOUT_WIDTH__MASK			0x0000ffff
+#define CORE_DATAOUT_SIZE_0_DATAOUT_WIDTH__SHIFT		0
+static inline uint32_t CORE_DATAOUT_SIZE_0_DATAOUT_WIDTH(uint32_t val)
+{
+	return ((val) << CORE_DATAOUT_SIZE_0_DATAOUT_WIDTH__SHIFT) & CORE_DATAOUT_SIZE_0_DATAOUT_WIDTH__MASK;
+}
+
+#define REG_CORE_DATAOUT_SIZE_1					0x00003018
+#define CORE_DATAOUT_SIZE_1_RESERVED_0__MASK			0xffff0000
+#define CORE_DATAOUT_SIZE_1_RESERVED_0__SHIFT			16
+static inline uint32_t CORE_DATAOUT_SIZE_1_RESERVED_0(uint32_t val)
+{
+	return ((val) << CORE_DATAOUT_SIZE_1_RESERVED_0__SHIFT) & CORE_DATAOUT_SIZE_1_RESERVED_0__MASK;
+}
+#define CORE_DATAOUT_SIZE_1_DATAOUT_CHANNEL__MASK		0x0000ffff
+#define CORE_DATAOUT_SIZE_1_DATAOUT_CHANNEL__SHIFT		0
+static inline uint32_t CORE_DATAOUT_SIZE_1_DATAOUT_CHANNEL(uint32_t val)
+{
+	return ((val) << CORE_DATAOUT_SIZE_1_DATAOUT_CHANNEL__SHIFT) & CORE_DATAOUT_SIZE_1_DATAOUT_CHANNEL__MASK;
+}
+
+#define REG_CORE_CLIP_TRUNCATE					0x0000301c
+#define CORE_CLIP_TRUNCATE_RESERVED_0__MASK			0xffffff80
+#define CORE_CLIP_TRUNCATE_RESERVED_0__SHIFT			7
+static inline uint32_t CORE_CLIP_TRUNCATE_RESERVED_0(uint32_t val)
+{
+	return ((val) << CORE_CLIP_TRUNCATE_RESERVED_0__SHIFT) & CORE_CLIP_TRUNCATE_RESERVED_0__MASK;
+}
+#define CORE_CLIP_TRUNCATE_ROUND_TYPE__MASK			0x00000040
+#define CORE_CLIP_TRUNCATE_ROUND_TYPE__SHIFT			6
+static inline uint32_t CORE_CLIP_TRUNCATE_ROUND_TYPE(uint32_t val)
+{
+	return ((val) << CORE_CLIP_TRUNCATE_ROUND_TYPE__SHIFT) & CORE_CLIP_TRUNCATE_ROUND_TYPE__MASK;
+}
+#define CORE_CLIP_TRUNCATE_RESERVED_1__MASK			0x00000020
+#define CORE_CLIP_TRUNCATE_RESERVED_1__SHIFT			5
+static inline uint32_t CORE_CLIP_TRUNCATE_RESERVED_1(uint32_t val)
+{
+	return ((val) << CORE_CLIP_TRUNCATE_RESERVED_1__SHIFT) & CORE_CLIP_TRUNCATE_RESERVED_1__MASK;
+}
+#define CORE_CLIP_TRUNCATE_CLIP_TRUNCATE__MASK			0x0000001f
+#define CORE_CLIP_TRUNCATE_CLIP_TRUNCATE__SHIFT			0
+static inline uint32_t CORE_CLIP_TRUNCATE_CLIP_TRUNCATE(uint32_t val)
+{
+	return ((val) << CORE_CLIP_TRUNCATE_CLIP_TRUNCATE__SHIFT) & CORE_CLIP_TRUNCATE_CLIP_TRUNCATE__MASK;
+}
+
+#define REG_DPU_S_STATUS					0x00004000
+#define DPU_S_STATUS_RESERVED_0__MASK				0xfffc0000
+#define DPU_S_STATUS_RESERVED_0__SHIFT				18
+static inline uint32_t DPU_S_STATUS_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_S_STATUS_RESERVED_0__SHIFT) & DPU_S_STATUS_RESERVED_0__MASK;
+}
+#define DPU_S_STATUS_STATUS_1__MASK				0x00030000
+#define DPU_S_STATUS_STATUS_1__SHIFT				16
+static inline uint32_t DPU_S_STATUS_STATUS_1(uint32_t val)
+{
+	return ((val) << DPU_S_STATUS_STATUS_1__SHIFT) & DPU_S_STATUS_STATUS_1__MASK;
+}
+#define DPU_S_STATUS_RESERVED_1__MASK				0x0000fffc
+#define DPU_S_STATUS_RESERVED_1__SHIFT				2
+static inline uint32_t DPU_S_STATUS_RESERVED_1(uint32_t val)
+{
+	return ((val) << DPU_S_STATUS_RESERVED_1__SHIFT) & DPU_S_STATUS_RESERVED_1__MASK;
+}
+#define DPU_S_STATUS_STATUS_0__MASK				0x00000003
+#define DPU_S_STATUS_STATUS_0__SHIFT				0
+static inline uint32_t DPU_S_STATUS_STATUS_0(uint32_t val)
+{
+	return ((val) << DPU_S_STATUS_STATUS_0__SHIFT) & DPU_S_STATUS_STATUS_0__MASK;
+}
+
+#define REG_DPU_S_POINTER					0x00004004
+#define DPU_S_POINTER_RESERVED_0__MASK				0xfffe0000
+#define DPU_S_POINTER_RESERVED_0__SHIFT				17
+static inline uint32_t DPU_S_POINTER_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_S_POINTER_RESERVED_0__SHIFT) & DPU_S_POINTER_RESERVED_0__MASK;
+}
+#define DPU_S_POINTER_EXECUTER__MASK				0x00010000
+#define DPU_S_POINTER_EXECUTER__SHIFT				16
+static inline uint32_t DPU_S_POINTER_EXECUTER(uint32_t val)
+{
+	return ((val) << DPU_S_POINTER_EXECUTER__SHIFT) & DPU_S_POINTER_EXECUTER__MASK;
+}
+#define DPU_S_POINTER_RESERVED_1__MASK				0x0000ffc0
+#define DPU_S_POINTER_RESERVED_1__SHIFT				6
+static inline uint32_t DPU_S_POINTER_RESERVED_1(uint32_t val)
+{
+	return ((val) << DPU_S_POINTER_RESERVED_1__SHIFT) & DPU_S_POINTER_RESERVED_1__MASK;
+}
+#define DPU_S_POINTER_EXECUTER_PP_CLEAR__MASK			0x00000020
+#define DPU_S_POINTER_EXECUTER_PP_CLEAR__SHIFT			5
+static inline uint32_t DPU_S_POINTER_EXECUTER_PP_CLEAR(uint32_t val)
+{
+	return ((val) << DPU_S_POINTER_EXECUTER_PP_CLEAR__SHIFT) & DPU_S_POINTER_EXECUTER_PP_CLEAR__MASK;
+}
+#define DPU_S_POINTER_POINTER_PP_CLEAR__MASK			0x00000010
+#define DPU_S_POINTER_POINTER_PP_CLEAR__SHIFT			4
+static inline uint32_t DPU_S_POINTER_POINTER_PP_CLEAR(uint32_t val)
+{
+	return ((val) << DPU_S_POINTER_POINTER_PP_CLEAR__SHIFT) & DPU_S_POINTER_POINTER_PP_CLEAR__MASK;
+}
+#define DPU_S_POINTER_POINTER_PP_MODE__MASK			0x00000008
+#define DPU_S_POINTER_POINTER_PP_MODE__SHIFT			3
+static inline uint32_t DPU_S_POINTER_POINTER_PP_MODE(uint32_t val)
+{
+	return ((val) << DPU_S_POINTER_POINTER_PP_MODE__SHIFT) & DPU_S_POINTER_POINTER_PP_MODE__MASK;
+}
+#define DPU_S_POINTER_EXECUTER_PP_EN__MASK			0x00000004
+#define DPU_S_POINTER_EXECUTER_PP_EN__SHIFT			2
+static inline uint32_t DPU_S_POINTER_EXECUTER_PP_EN(uint32_t val)
+{
+	return ((val) << DPU_S_POINTER_EXECUTER_PP_EN__SHIFT) & DPU_S_POINTER_EXECUTER_PP_EN__MASK;
+}
+#define DPU_S_POINTER_POINTER_PP_EN__MASK			0x00000002
+#define DPU_S_POINTER_POINTER_PP_EN__SHIFT			1
+static inline uint32_t DPU_S_POINTER_POINTER_PP_EN(uint32_t val)
+{
+	return ((val) << DPU_S_POINTER_POINTER_PP_EN__SHIFT) & DPU_S_POINTER_POINTER_PP_EN__MASK;
+}
+#define DPU_S_POINTER_POINTER__MASK				0x00000001
+#define DPU_S_POINTER_POINTER__SHIFT				0
+static inline uint32_t DPU_S_POINTER_POINTER(uint32_t val)
+{
+	return ((val) << DPU_S_POINTER_POINTER__SHIFT) & DPU_S_POINTER_POINTER__MASK;
+}
+
+#define REG_DPU_OPERATION_ENABLE				0x00004008
+#define DPU_OPERATION_ENABLE_RESERVED_0__MASK			0xfffffffe
+#define DPU_OPERATION_ENABLE_RESERVED_0__SHIFT			1
+static inline uint32_t DPU_OPERATION_ENABLE_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_OPERATION_ENABLE_RESERVED_0__SHIFT) & DPU_OPERATION_ENABLE_RESERVED_0__MASK;
+}
+#define DPU_OPERATION_ENABLE_OP_EN__MASK			0x00000001
+#define DPU_OPERATION_ENABLE_OP_EN__SHIFT			0
+static inline uint32_t DPU_OPERATION_ENABLE_OP_EN(uint32_t val)
+{
+	return ((val) << DPU_OPERATION_ENABLE_OP_EN__SHIFT) & DPU_OPERATION_ENABLE_OP_EN__MASK;
+}
+
+#define REG_DPU_FEATURE_MODE_CFG				0x0000400c
+#define DPU_FEATURE_MODE_CFG_COMB_USE__MASK			0x80000000
+#define DPU_FEATURE_MODE_CFG_COMB_USE__SHIFT			31
+static inline uint32_t DPU_FEATURE_MODE_CFG_COMB_USE(uint32_t val)
+{
+	return ((val) << DPU_FEATURE_MODE_CFG_COMB_USE__SHIFT) & DPU_FEATURE_MODE_CFG_COMB_USE__MASK;
+}
+#define DPU_FEATURE_MODE_CFG_TP_EN__MASK			0x40000000
+#define DPU_FEATURE_MODE_CFG_TP_EN__SHIFT			30
+static inline uint32_t DPU_FEATURE_MODE_CFG_TP_EN(uint32_t val)
+{
+	return ((val) << DPU_FEATURE_MODE_CFG_TP_EN__SHIFT) & DPU_FEATURE_MODE_CFG_TP_EN__MASK;
+}
+#define DPU_FEATURE_MODE_CFG_RGP_TYPE__MASK			0x3c000000
+#define DPU_FEATURE_MODE_CFG_RGP_TYPE__SHIFT			26
+static inline uint32_t DPU_FEATURE_MODE_CFG_RGP_TYPE(uint32_t val)
+{
+	return ((val) << DPU_FEATURE_MODE_CFG_RGP_TYPE__SHIFT) & DPU_FEATURE_MODE_CFG_RGP_TYPE__MASK;
+}
+#define DPU_FEATURE_MODE_CFG_NONALIGN__MASK			0x02000000
+#define DPU_FEATURE_MODE_CFG_NONALIGN__SHIFT			25
+static inline uint32_t DPU_FEATURE_MODE_CFG_NONALIGN(uint32_t val)
+{
+	return ((val) << DPU_FEATURE_MODE_CFG_NONALIGN__SHIFT) & DPU_FEATURE_MODE_CFG_NONALIGN__MASK;
+}
+#define DPU_FEATURE_MODE_CFG_SURF_LEN__MASK			0x01fffe00
+#define DPU_FEATURE_MODE_CFG_SURF_LEN__SHIFT			9
+static inline uint32_t DPU_FEATURE_MODE_CFG_SURF_LEN(uint32_t val)
+{
+	return ((val) << DPU_FEATURE_MODE_CFG_SURF_LEN__SHIFT) & DPU_FEATURE_MODE_CFG_SURF_LEN__MASK;
+}
+#define DPU_FEATURE_MODE_CFG_BURST_LEN__MASK			0x000001e0
+#define DPU_FEATURE_MODE_CFG_BURST_LEN__SHIFT			5
+static inline uint32_t DPU_FEATURE_MODE_CFG_BURST_LEN(uint32_t val)
+{
+	return ((val) << DPU_FEATURE_MODE_CFG_BURST_LEN__SHIFT) & DPU_FEATURE_MODE_CFG_BURST_LEN__MASK;
+}
+#define DPU_FEATURE_MODE_CFG_CONV_MODE__MASK			0x00000018
+#define DPU_FEATURE_MODE_CFG_CONV_MODE__SHIFT			3
+static inline uint32_t DPU_FEATURE_MODE_CFG_CONV_MODE(uint32_t val)
+{
+	return ((val) << DPU_FEATURE_MODE_CFG_CONV_MODE__SHIFT) & DPU_FEATURE_MODE_CFG_CONV_MODE__MASK;
+}
+#define DPU_FEATURE_MODE_CFG_OUTPUT_MODE__MASK			0x00000006
+#define DPU_FEATURE_MODE_CFG_OUTPUT_MODE__SHIFT			1
+static inline uint32_t DPU_FEATURE_MODE_CFG_OUTPUT_MODE(uint32_t val)
+{
+	return ((val) << DPU_FEATURE_MODE_CFG_OUTPUT_MODE__SHIFT) & DPU_FEATURE_MODE_CFG_OUTPUT_MODE__MASK;
+}
+#define DPU_FEATURE_MODE_CFG_FLYING_MODE__MASK			0x00000001
+#define DPU_FEATURE_MODE_CFG_FLYING_MODE__SHIFT			0
+static inline uint32_t DPU_FEATURE_MODE_CFG_FLYING_MODE(uint32_t val)
+{
+	return ((val) << DPU_FEATURE_MODE_CFG_FLYING_MODE__SHIFT) & DPU_FEATURE_MODE_CFG_FLYING_MODE__MASK;
+}
+
+#define REG_DPU_DATA_FORMAT					0x00004010
+#define DPU_DATA_FORMAT_OUT_PRECISION__MASK			0xe0000000
+#define DPU_DATA_FORMAT_OUT_PRECISION__SHIFT			29
+static inline uint32_t DPU_DATA_FORMAT_OUT_PRECISION(uint32_t val)
+{
+	return ((val) << DPU_DATA_FORMAT_OUT_PRECISION__SHIFT) & DPU_DATA_FORMAT_OUT_PRECISION__MASK;
+}
+#define DPU_DATA_FORMAT_IN_PRECISION__MASK			0x1c000000
+#define DPU_DATA_FORMAT_IN_PRECISION__SHIFT			26
+static inline uint32_t DPU_DATA_FORMAT_IN_PRECISION(uint32_t val)
+{
+	return ((val) << DPU_DATA_FORMAT_IN_PRECISION__SHIFT) & DPU_DATA_FORMAT_IN_PRECISION__MASK;
+}
+#define DPU_DATA_FORMAT_EW_TRUNCATE_NEG__MASK			0x03ff0000
+#define DPU_DATA_FORMAT_EW_TRUNCATE_NEG__SHIFT			16
+static inline uint32_t DPU_DATA_FORMAT_EW_TRUNCATE_NEG(uint32_t val)
+{
+	return ((val) << DPU_DATA_FORMAT_EW_TRUNCATE_NEG__SHIFT) & DPU_DATA_FORMAT_EW_TRUNCATE_NEG__MASK;
+}
+#define DPU_DATA_FORMAT_BN_MUL_SHIFT_VALUE_NEG__MASK		0x0000fc00
+#define DPU_DATA_FORMAT_BN_MUL_SHIFT_VALUE_NEG__SHIFT		10
+static inline uint32_t DPU_DATA_FORMAT_BN_MUL_SHIFT_VALUE_NEG(uint32_t val)
+{
+	return ((val) << DPU_DATA_FORMAT_BN_MUL_SHIFT_VALUE_NEG__SHIFT) & DPU_DATA_FORMAT_BN_MUL_SHIFT_VALUE_NEG__MASK;
+}
+#define DPU_DATA_FORMAT_BS_MUL_SHIFT_VALUE_NEG__MASK		0x000003f0
+#define DPU_DATA_FORMAT_BS_MUL_SHIFT_VALUE_NEG__SHIFT		4
+static inline uint32_t DPU_DATA_FORMAT_BS_MUL_SHIFT_VALUE_NEG(uint32_t val)
+{
+	return ((val) << DPU_DATA_FORMAT_BS_MUL_SHIFT_VALUE_NEG__SHIFT) & DPU_DATA_FORMAT_BS_MUL_SHIFT_VALUE_NEG__MASK;
+}
+#define DPU_DATA_FORMAT_MC_SURF_OUT__MASK			0x00000008
+#define DPU_DATA_FORMAT_MC_SURF_OUT__SHIFT			3
+static inline uint32_t DPU_DATA_FORMAT_MC_SURF_OUT(uint32_t val)
+{
+	return ((val) << DPU_DATA_FORMAT_MC_SURF_OUT__SHIFT) & DPU_DATA_FORMAT_MC_SURF_OUT__MASK;
+}
+#define DPU_DATA_FORMAT_PROC_PRECISION__MASK			0x00000007
+#define DPU_DATA_FORMAT_PROC_PRECISION__SHIFT			0
+static inline uint32_t DPU_DATA_FORMAT_PROC_PRECISION(uint32_t val)
+{
+	return ((val) << DPU_DATA_FORMAT_PROC_PRECISION__SHIFT) & DPU_DATA_FORMAT_PROC_PRECISION__MASK;
+}
+
+#define REG_DPU_OFFSET_PEND					0x00004014
+#define DPU_OFFSET_PEND_RESERVED_0__MASK			0xffff0000
+#define DPU_OFFSET_PEND_RESERVED_0__SHIFT			16
+static inline uint32_t DPU_OFFSET_PEND_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_OFFSET_PEND_RESERVED_0__SHIFT) & DPU_OFFSET_PEND_RESERVED_0__MASK;
+}
+#define DPU_OFFSET_PEND_OFFSET_PEND__MASK			0x0000ffff
+#define DPU_OFFSET_PEND_OFFSET_PEND__SHIFT			0
+static inline uint32_t DPU_OFFSET_PEND_OFFSET_PEND(uint32_t val)
+{
+	return ((val) << DPU_OFFSET_PEND_OFFSET_PEND__SHIFT) & DPU_OFFSET_PEND_OFFSET_PEND__MASK;
+}
+
+#define REG_DPU_DST_BASE_ADDR					0x00004020
+#define DPU_DST_BASE_ADDR_DST_BASE_ADDR__MASK			0xffffffff
+#define DPU_DST_BASE_ADDR_DST_BASE_ADDR__SHIFT			0
+static inline uint32_t DPU_DST_BASE_ADDR_DST_BASE_ADDR(uint32_t val)
+{
+	return ((val) << DPU_DST_BASE_ADDR_DST_BASE_ADDR__SHIFT) & DPU_DST_BASE_ADDR_DST_BASE_ADDR__MASK;
+}
+
+#define REG_DPU_DST_SURF_STRIDE					0x00004024
+#define DPU_DST_SURF_STRIDE_DST_SURF_STRIDE__MASK		0xfffffff0
+#define DPU_DST_SURF_STRIDE_DST_SURF_STRIDE__SHIFT		4
+static inline uint32_t DPU_DST_SURF_STRIDE_DST_SURF_STRIDE(uint32_t val)
+{
+	return ((val) << DPU_DST_SURF_STRIDE_DST_SURF_STRIDE__SHIFT) & DPU_DST_SURF_STRIDE_DST_SURF_STRIDE__MASK;
+}
+#define DPU_DST_SURF_STRIDE_RESERVED_0__MASK			0x0000000f
+#define DPU_DST_SURF_STRIDE_RESERVED_0__SHIFT			0
+static inline uint32_t DPU_DST_SURF_STRIDE_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_DST_SURF_STRIDE_RESERVED_0__SHIFT) & DPU_DST_SURF_STRIDE_RESERVED_0__MASK;
+}
+
+#define REG_DPU_DATA_CUBE_WIDTH					0x00004030
+#define DPU_DATA_CUBE_WIDTH_RESERVED_0__MASK			0xffffe000
+#define DPU_DATA_CUBE_WIDTH_RESERVED_0__SHIFT			13
+static inline uint32_t DPU_DATA_CUBE_WIDTH_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_DATA_CUBE_WIDTH_RESERVED_0__SHIFT) & DPU_DATA_CUBE_WIDTH_RESERVED_0__MASK;
+}
+#define DPU_DATA_CUBE_WIDTH_WIDTH__MASK				0x00001fff
+#define DPU_DATA_CUBE_WIDTH_WIDTH__SHIFT			0
+static inline uint32_t DPU_DATA_CUBE_WIDTH_WIDTH(uint32_t val)
+{
+	return ((val) << DPU_DATA_CUBE_WIDTH_WIDTH__SHIFT) & DPU_DATA_CUBE_WIDTH_WIDTH__MASK;
+}
+
+#define REG_DPU_DATA_CUBE_HEIGHT				0x00004034
+#define DPU_DATA_CUBE_HEIGHT_RESERVED_0__MASK			0xfe000000
+#define DPU_DATA_CUBE_HEIGHT_RESERVED_0__SHIFT			25
+static inline uint32_t DPU_DATA_CUBE_HEIGHT_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_DATA_CUBE_HEIGHT_RESERVED_0__SHIFT) & DPU_DATA_CUBE_HEIGHT_RESERVED_0__MASK;
+}
+#define DPU_DATA_CUBE_HEIGHT_MINMAX_CTL__MASK			0x01c00000
+#define DPU_DATA_CUBE_HEIGHT_MINMAX_CTL__SHIFT			22
+static inline uint32_t DPU_DATA_CUBE_HEIGHT_MINMAX_CTL(uint32_t val)
+{
+	return ((val) << DPU_DATA_CUBE_HEIGHT_MINMAX_CTL__SHIFT) & DPU_DATA_CUBE_HEIGHT_MINMAX_CTL__MASK;
+}
+#define DPU_DATA_CUBE_HEIGHT_RESERVED_1__MASK			0x003fe000
+#define DPU_DATA_CUBE_HEIGHT_RESERVED_1__SHIFT			13
+static inline uint32_t DPU_DATA_CUBE_HEIGHT_RESERVED_1(uint32_t val)
+{
+	return ((val) << DPU_DATA_CUBE_HEIGHT_RESERVED_1__SHIFT) & DPU_DATA_CUBE_HEIGHT_RESERVED_1__MASK;
+}
+#define DPU_DATA_CUBE_HEIGHT_HEIGHT__MASK			0x00001fff
+#define DPU_DATA_CUBE_HEIGHT_HEIGHT__SHIFT			0
+static inline uint32_t DPU_DATA_CUBE_HEIGHT_HEIGHT(uint32_t val)
+{
+	return ((val) << DPU_DATA_CUBE_HEIGHT_HEIGHT__SHIFT) & DPU_DATA_CUBE_HEIGHT_HEIGHT__MASK;
+}
+
+#define REG_DPU_DATA_CUBE_NOTCH_ADDR				0x00004038
+#define DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_0__MASK		0xe0000000
+#define DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_0__SHIFT		29
+static inline uint32_t DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_0__SHIFT) & DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_0__MASK;
+}
+#define DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_1__MASK		0x1fff0000
+#define DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_1__SHIFT		16
+static inline uint32_t DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_1(uint32_t val)
+{
+	return ((val) << DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_1__SHIFT) & DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_1__MASK;
+}
+#define DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_1__MASK		0x0000e000
+#define DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_1__SHIFT		13
+static inline uint32_t DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_1(uint32_t val)
+{
+	return ((val) << DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_1__SHIFT) & DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_1__MASK;
+}
+#define DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_0__MASK		0x00001fff
+#define DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_0__SHIFT		0
+static inline uint32_t DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_0(uint32_t val)
+{
+	return ((val) << DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_0__SHIFT) & DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_0__MASK;
+}
+
+#define REG_DPU_DATA_CUBE_CHANNEL				0x0000403c
+#define DPU_DATA_CUBE_CHANNEL_RESERVED_0__MASK			0xe0000000
+#define DPU_DATA_CUBE_CHANNEL_RESERVED_0__SHIFT			29
+static inline uint32_t DPU_DATA_CUBE_CHANNEL_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_DATA_CUBE_CHANNEL_RESERVED_0__SHIFT) & DPU_DATA_CUBE_CHANNEL_RESERVED_0__MASK;
+}
+#define DPU_DATA_CUBE_CHANNEL_ORIG_CHANNEL__MASK		0x1fff0000
+#define DPU_DATA_CUBE_CHANNEL_ORIG_CHANNEL__SHIFT		16
+static inline uint32_t DPU_DATA_CUBE_CHANNEL_ORIG_CHANNEL(uint32_t val)
+{
+	return ((val) << DPU_DATA_CUBE_CHANNEL_ORIG_CHANNEL__SHIFT) & DPU_DATA_CUBE_CHANNEL_ORIG_CHANNEL__MASK;
+}
+#define DPU_DATA_CUBE_CHANNEL_RESERVED_1__MASK			0x0000e000
+#define DPU_DATA_CUBE_CHANNEL_RESERVED_1__SHIFT			13
+static inline uint32_t DPU_DATA_CUBE_CHANNEL_RESERVED_1(uint32_t val)
+{
+	return ((val) << DPU_DATA_CUBE_CHANNEL_RESERVED_1__SHIFT) & DPU_DATA_CUBE_CHANNEL_RESERVED_1__MASK;
+}
+#define DPU_DATA_CUBE_CHANNEL_CHANNEL__MASK			0x00001fff
+#define DPU_DATA_CUBE_CHANNEL_CHANNEL__SHIFT			0
+static inline uint32_t DPU_DATA_CUBE_CHANNEL_CHANNEL(uint32_t val)
+{
+	return ((val) << DPU_DATA_CUBE_CHANNEL_CHANNEL__SHIFT) & DPU_DATA_CUBE_CHANNEL_CHANNEL__MASK;
+}
+
+#define REG_DPU_BS_CFG						0x00004040
+#define DPU_BS_CFG_RESERVED_0__MASK				0xfff00000
+#define DPU_BS_CFG_RESERVED_0__SHIFT				20
+static inline uint32_t DPU_BS_CFG_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_BS_CFG_RESERVED_0__SHIFT) & DPU_BS_CFG_RESERVED_0__MASK;
+}
+#define DPU_BS_CFG_BS_ALU_ALGO__MASK				0x000f0000
+#define DPU_BS_CFG_BS_ALU_ALGO__SHIFT				16
+static inline uint32_t DPU_BS_CFG_BS_ALU_ALGO(uint32_t val)
+{
+	return ((val) << DPU_BS_CFG_BS_ALU_ALGO__SHIFT) & DPU_BS_CFG_BS_ALU_ALGO__MASK;
+}
+#define DPU_BS_CFG_RESERVED_1__MASK				0x0000fe00
+#define DPU_BS_CFG_RESERVED_1__SHIFT				9
+static inline uint32_t DPU_BS_CFG_RESERVED_1(uint32_t val)
+{
+	return ((val) << DPU_BS_CFG_RESERVED_1__SHIFT) & DPU_BS_CFG_RESERVED_1__MASK;
+}
+#define DPU_BS_CFG_BS_ALU_SRC__MASK				0x00000100
+#define DPU_BS_CFG_BS_ALU_SRC__SHIFT				8
+static inline uint32_t DPU_BS_CFG_BS_ALU_SRC(uint32_t val)
+{
+	return ((val) << DPU_BS_CFG_BS_ALU_SRC__SHIFT) & DPU_BS_CFG_BS_ALU_SRC__MASK;
+}
+#define DPU_BS_CFG_BS_RELUX_EN__MASK				0x00000080
+#define DPU_BS_CFG_BS_RELUX_EN__SHIFT				7
+static inline uint32_t DPU_BS_CFG_BS_RELUX_EN(uint32_t val)
+{
+	return ((val) << DPU_BS_CFG_BS_RELUX_EN__SHIFT) & DPU_BS_CFG_BS_RELUX_EN__MASK;
+}
+#define DPU_BS_CFG_BS_RELU_BYPASS__MASK				0x00000040
+#define DPU_BS_CFG_BS_RELU_BYPASS__SHIFT			6
+static inline uint32_t DPU_BS_CFG_BS_RELU_BYPASS(uint32_t val)
+{
+	return ((val) << DPU_BS_CFG_BS_RELU_BYPASS__SHIFT) & DPU_BS_CFG_BS_RELU_BYPASS__MASK;
+}
+#define DPU_BS_CFG_BS_MUL_PRELU__MASK				0x00000020
+#define DPU_BS_CFG_BS_MUL_PRELU__SHIFT				5
+static inline uint32_t DPU_BS_CFG_BS_MUL_PRELU(uint32_t val)
+{
+	return ((val) << DPU_BS_CFG_BS_MUL_PRELU__SHIFT) & DPU_BS_CFG_BS_MUL_PRELU__MASK;
+}
+#define DPU_BS_CFG_BS_MUL_BYPASS__MASK				0x00000010
+#define DPU_BS_CFG_BS_MUL_BYPASS__SHIFT				4
+static inline uint32_t DPU_BS_CFG_BS_MUL_BYPASS(uint32_t val)
+{
+	return ((val) << DPU_BS_CFG_BS_MUL_BYPASS__SHIFT) & DPU_BS_CFG_BS_MUL_BYPASS__MASK;
+}
+#define DPU_BS_CFG_RESERVED_2__MASK				0x0000000c
+#define DPU_BS_CFG_RESERVED_2__SHIFT				2
+static inline uint32_t DPU_BS_CFG_RESERVED_2(uint32_t val)
+{
+	return ((val) << DPU_BS_CFG_RESERVED_2__SHIFT) & DPU_BS_CFG_RESERVED_2__MASK;
+}
+#define DPU_BS_CFG_BS_ALU_BYPASS__MASK				0x00000002
+#define DPU_BS_CFG_BS_ALU_BYPASS__SHIFT				1
+static inline uint32_t DPU_BS_CFG_BS_ALU_BYPASS(uint32_t val)
+{
+	return ((val) << DPU_BS_CFG_BS_ALU_BYPASS__SHIFT) & DPU_BS_CFG_BS_ALU_BYPASS__MASK;
+}
+#define DPU_BS_CFG_BS_BYPASS__MASK				0x00000001
+#define DPU_BS_CFG_BS_BYPASS__SHIFT				0
+static inline uint32_t DPU_BS_CFG_BS_BYPASS(uint32_t val)
+{
+	return ((val) << DPU_BS_CFG_BS_BYPASS__SHIFT) & DPU_BS_CFG_BS_BYPASS__MASK;
+}
+
+#define REG_DPU_BS_ALU_CFG					0x00004044
+#define DPU_BS_ALU_CFG_BS_ALU_OPERAND__MASK			0xffffffff
+#define DPU_BS_ALU_CFG_BS_ALU_OPERAND__SHIFT			0
+static inline uint32_t DPU_BS_ALU_CFG_BS_ALU_OPERAND(uint32_t val)
+{
+	return ((val) << DPU_BS_ALU_CFG_BS_ALU_OPERAND__SHIFT) & DPU_BS_ALU_CFG_BS_ALU_OPERAND__MASK;
+}
+
+#define REG_DPU_BS_MUL_CFG					0x00004048
+#define DPU_BS_MUL_CFG_BS_MUL_OPERAND__MASK			0xffff0000
+#define DPU_BS_MUL_CFG_BS_MUL_OPERAND__SHIFT			16
+static inline uint32_t DPU_BS_MUL_CFG_BS_MUL_OPERAND(uint32_t val)
+{
+	return ((val) << DPU_BS_MUL_CFG_BS_MUL_OPERAND__SHIFT) & DPU_BS_MUL_CFG_BS_MUL_OPERAND__MASK;
+}
+#define DPU_BS_MUL_CFG_RESERVED_0__MASK				0x0000c000
+#define DPU_BS_MUL_CFG_RESERVED_0__SHIFT			14
+static inline uint32_t DPU_BS_MUL_CFG_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_BS_MUL_CFG_RESERVED_0__SHIFT) & DPU_BS_MUL_CFG_RESERVED_0__MASK;
+}
+#define DPU_BS_MUL_CFG_BS_MUL_SHIFT_VALUE__MASK			0x00003f00
+#define DPU_BS_MUL_CFG_BS_MUL_SHIFT_VALUE__SHIFT		8
+static inline uint32_t DPU_BS_MUL_CFG_BS_MUL_SHIFT_VALUE(uint32_t val)
+{
+	return ((val) << DPU_BS_MUL_CFG_BS_MUL_SHIFT_VALUE__SHIFT) & DPU_BS_MUL_CFG_BS_MUL_SHIFT_VALUE__MASK;
+}
+#define DPU_BS_MUL_CFG_RESERVED_1__MASK				0x000000fc
+#define DPU_BS_MUL_CFG_RESERVED_1__SHIFT			2
+static inline uint32_t DPU_BS_MUL_CFG_RESERVED_1(uint32_t val)
+{
+	return ((val) << DPU_BS_MUL_CFG_RESERVED_1__SHIFT) & DPU_BS_MUL_CFG_RESERVED_1__MASK;
+}
+#define DPU_BS_MUL_CFG_BS_TRUNCATE_SRC__MASK			0x00000002
+#define DPU_BS_MUL_CFG_BS_TRUNCATE_SRC__SHIFT			1
+static inline uint32_t DPU_BS_MUL_CFG_BS_TRUNCATE_SRC(uint32_t val)
+{
+	return ((val) << DPU_BS_MUL_CFG_BS_TRUNCATE_SRC__SHIFT) & DPU_BS_MUL_CFG_BS_TRUNCATE_SRC__MASK;
+}
+#define DPU_BS_MUL_CFG_BS_MUL_SRC__MASK				0x00000001
+#define DPU_BS_MUL_CFG_BS_MUL_SRC__SHIFT			0
+static inline uint32_t DPU_BS_MUL_CFG_BS_MUL_SRC(uint32_t val)
+{
+	return ((val) << DPU_BS_MUL_CFG_BS_MUL_SRC__SHIFT) & DPU_BS_MUL_CFG_BS_MUL_SRC__MASK;
+}
+
+#define REG_DPU_BS_RELUX_CMP_VALUE				0x0000404c
+#define DPU_BS_RELUX_CMP_VALUE_BS_RELUX_CMP_DAT__MASK		0xffffffff
+#define DPU_BS_RELUX_CMP_VALUE_BS_RELUX_CMP_DAT__SHIFT		0
+static inline uint32_t DPU_BS_RELUX_CMP_VALUE_BS_RELUX_CMP_DAT(uint32_t val)
+{
+	return ((val) << DPU_BS_RELUX_CMP_VALUE_BS_RELUX_CMP_DAT__SHIFT) & DPU_BS_RELUX_CMP_VALUE_BS_RELUX_CMP_DAT__MASK;
+}
+
+#define REG_DPU_BS_OW_CFG					0x00004050
+#define DPU_BS_OW_CFG_RGP_CNTER__MASK				0xf0000000
+#define DPU_BS_OW_CFG_RGP_CNTER__SHIFT				28
+static inline uint32_t DPU_BS_OW_CFG_RGP_CNTER(uint32_t val)
+{
+	return ((val) << DPU_BS_OW_CFG_RGP_CNTER__SHIFT) & DPU_BS_OW_CFG_RGP_CNTER__MASK;
+}
+#define DPU_BS_OW_CFG_TP_ORG_EN__MASK				0x08000000
+#define DPU_BS_OW_CFG_TP_ORG_EN__SHIFT				27
+static inline uint32_t DPU_BS_OW_CFG_TP_ORG_EN(uint32_t val)
+{
+	return ((val) << DPU_BS_OW_CFG_TP_ORG_EN__SHIFT) & DPU_BS_OW_CFG_TP_ORG_EN__MASK;
+}
+#define DPU_BS_OW_CFG_RESERVED_0__MASK				0x07fff800
+#define DPU_BS_OW_CFG_RESERVED_0__SHIFT				11
+static inline uint32_t DPU_BS_OW_CFG_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_BS_OW_CFG_RESERVED_0__SHIFT) & DPU_BS_OW_CFG_RESERVED_0__MASK;
+}
+#define DPU_BS_OW_CFG_SIZE_E_2__MASK				0x00000700
+#define DPU_BS_OW_CFG_SIZE_E_2__SHIFT				8
+static inline uint32_t DPU_BS_OW_CFG_SIZE_E_2(uint32_t val)
+{
+	return ((val) << DPU_BS_OW_CFG_SIZE_E_2__SHIFT) & DPU_BS_OW_CFG_SIZE_E_2__MASK;
+}
+#define DPU_BS_OW_CFG_SIZE_E_1__MASK				0x000000e0
+#define DPU_BS_OW_CFG_SIZE_E_1__SHIFT				5
+static inline uint32_t DPU_BS_OW_CFG_SIZE_E_1(uint32_t val)
+{
+	return ((val) << DPU_BS_OW_CFG_SIZE_E_1__SHIFT) & DPU_BS_OW_CFG_SIZE_E_1__MASK;
+}
+#define DPU_BS_OW_CFG_SIZE_E_0__MASK				0x0000001c
+#define DPU_BS_OW_CFG_SIZE_E_0__SHIFT				2
+static inline uint32_t DPU_BS_OW_CFG_SIZE_E_0(uint32_t val)
+{
+	return ((val) << DPU_BS_OW_CFG_SIZE_E_0__SHIFT) & DPU_BS_OW_CFG_SIZE_E_0__MASK;
+}
+#define DPU_BS_OW_CFG_OD_BYPASS__MASK				0x00000002
+#define DPU_BS_OW_CFG_OD_BYPASS__SHIFT				1
+static inline uint32_t DPU_BS_OW_CFG_OD_BYPASS(uint32_t val)
+{
+	return ((val) << DPU_BS_OW_CFG_OD_BYPASS__SHIFT) & DPU_BS_OW_CFG_OD_BYPASS__MASK;
+}
+#define DPU_BS_OW_CFG_OW_SRC__MASK				0x00000001
+#define DPU_BS_OW_CFG_OW_SRC__SHIFT				0
+static inline uint32_t DPU_BS_OW_CFG_OW_SRC(uint32_t val)
+{
+	return ((val) << DPU_BS_OW_CFG_OW_SRC__SHIFT) & DPU_BS_OW_CFG_OW_SRC__MASK;
+}
+
+#define REG_DPU_BS_OW_OP					0x00004054
+#define DPU_BS_OW_OP_RESERVED_0__MASK				0xffff0000
+#define DPU_BS_OW_OP_RESERVED_0__SHIFT				16
+static inline uint32_t DPU_BS_OW_OP_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_BS_OW_OP_RESERVED_0__SHIFT) & DPU_BS_OW_OP_RESERVED_0__MASK;
+}
+#define DPU_BS_OW_OP_OW_OP__MASK				0x0000ffff
+#define DPU_BS_OW_OP_OW_OP__SHIFT				0
+static inline uint32_t DPU_BS_OW_OP_OW_OP(uint32_t val)
+{
+	return ((val) << DPU_BS_OW_OP_OW_OP__SHIFT) & DPU_BS_OW_OP_OW_OP__MASK;
+}
+
+#define REG_DPU_WDMA_SIZE_0					0x00004058
+#define DPU_WDMA_SIZE_0_RESERVED_0__MASK			0xf0000000
+#define DPU_WDMA_SIZE_0_RESERVED_0__SHIFT			28
+static inline uint32_t DPU_WDMA_SIZE_0_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_WDMA_SIZE_0_RESERVED_0__SHIFT) & DPU_WDMA_SIZE_0_RESERVED_0__MASK;
+}
+#define DPU_WDMA_SIZE_0_TP_PRECISION__MASK			0x08000000
+#define DPU_WDMA_SIZE_0_TP_PRECISION__SHIFT			27
+static inline uint32_t DPU_WDMA_SIZE_0_TP_PRECISION(uint32_t val)
+{
+	return ((val) << DPU_WDMA_SIZE_0_TP_PRECISION__SHIFT) & DPU_WDMA_SIZE_0_TP_PRECISION__MASK;
+}
+#define DPU_WDMA_SIZE_0_SIZE_C_WDMA__MASK			0x07ff0000
+#define DPU_WDMA_SIZE_0_SIZE_C_WDMA__SHIFT			16
+static inline uint32_t DPU_WDMA_SIZE_0_SIZE_C_WDMA(uint32_t val)
+{
+	return ((val) << DPU_WDMA_SIZE_0_SIZE_C_WDMA__SHIFT) & DPU_WDMA_SIZE_0_SIZE_C_WDMA__MASK;
+}
+#define DPU_WDMA_SIZE_0_RESERVED_1__MASK			0x0000e000
+#define DPU_WDMA_SIZE_0_RESERVED_1__SHIFT			13
+static inline uint32_t DPU_WDMA_SIZE_0_RESERVED_1(uint32_t val)
+{
+	return ((val) << DPU_WDMA_SIZE_0_RESERVED_1__SHIFT) & DPU_WDMA_SIZE_0_RESERVED_1__MASK;
+}
+#define DPU_WDMA_SIZE_0_CHANNEL_WDMA__MASK			0x00001fff
+#define DPU_WDMA_SIZE_0_CHANNEL_WDMA__SHIFT			0
+static inline uint32_t DPU_WDMA_SIZE_0_CHANNEL_WDMA(uint32_t val)
+{
+	return ((val) << DPU_WDMA_SIZE_0_CHANNEL_WDMA__SHIFT) & DPU_WDMA_SIZE_0_CHANNEL_WDMA__MASK;
+}
+
+#define REG_DPU_WDMA_SIZE_1					0x0000405c
+#define DPU_WDMA_SIZE_1_RESERVED_0__MASK			0xe0000000
+#define DPU_WDMA_SIZE_1_RESERVED_0__SHIFT			29
+static inline uint32_t DPU_WDMA_SIZE_1_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_WDMA_SIZE_1_RESERVED_0__SHIFT) & DPU_WDMA_SIZE_1_RESERVED_0__MASK;
+}
+#define DPU_WDMA_SIZE_1_HEIGHT_WDMA__MASK			0x1fff0000
+#define DPU_WDMA_SIZE_1_HEIGHT_WDMA__SHIFT			16
+static inline uint32_t DPU_WDMA_SIZE_1_HEIGHT_WDMA(uint32_t val)
+{
+	return ((val) << DPU_WDMA_SIZE_1_HEIGHT_WDMA__SHIFT) & DPU_WDMA_SIZE_1_HEIGHT_WDMA__MASK;
+}
+#define DPU_WDMA_SIZE_1_RESERVED_1__MASK			0x0000e000
+#define DPU_WDMA_SIZE_1_RESERVED_1__SHIFT			13
+static inline uint32_t DPU_WDMA_SIZE_1_RESERVED_1(uint32_t val)
+{
+	return ((val) << DPU_WDMA_SIZE_1_RESERVED_1__SHIFT) & DPU_WDMA_SIZE_1_RESERVED_1__MASK;
+}
+#define DPU_WDMA_SIZE_1_WIDTH_WDMA__MASK			0x00001fff
+#define DPU_WDMA_SIZE_1_WIDTH_WDMA__SHIFT			0
+static inline uint32_t DPU_WDMA_SIZE_1_WIDTH_WDMA(uint32_t val)
+{
+	return ((val) << DPU_WDMA_SIZE_1_WIDTH_WDMA__SHIFT) & DPU_WDMA_SIZE_1_WIDTH_WDMA__MASK;
+}
+
+#define REG_DPU_BN_CFG						0x00004060
+#define DPU_BN_CFG_RESERVED_0__MASK				0xfff00000
+#define DPU_BN_CFG_RESERVED_0__SHIFT				20
+static inline uint32_t DPU_BN_CFG_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_BN_CFG_RESERVED_0__SHIFT) & DPU_BN_CFG_RESERVED_0__MASK;
+}
+#define DPU_BN_CFG_BN_ALU_ALGO__MASK				0x000f0000
+#define DPU_BN_CFG_BN_ALU_ALGO__SHIFT				16
+static inline uint32_t DPU_BN_CFG_BN_ALU_ALGO(uint32_t val)
+{
+	return ((val) << DPU_BN_CFG_BN_ALU_ALGO__SHIFT) & DPU_BN_CFG_BN_ALU_ALGO__MASK;
+}
+#define DPU_BN_CFG_RESERVED_1__MASK				0x0000fe00
+#define DPU_BN_CFG_RESERVED_1__SHIFT				9
+static inline uint32_t DPU_BN_CFG_RESERVED_1(uint32_t val)
+{
+	return ((val) << DPU_BN_CFG_RESERVED_1__SHIFT) & DPU_BN_CFG_RESERVED_1__MASK;
+}
+#define DPU_BN_CFG_BN_ALU_SRC__MASK				0x00000100
+#define DPU_BN_CFG_BN_ALU_SRC__SHIFT				8
+static inline uint32_t DPU_BN_CFG_BN_ALU_SRC(uint32_t val)
+{
+	return ((val) << DPU_BN_CFG_BN_ALU_SRC__SHIFT) & DPU_BN_CFG_BN_ALU_SRC__MASK;
+}
+#define DPU_BN_CFG_BN_RELUX_EN__MASK				0x00000080
+#define DPU_BN_CFG_BN_RELUX_EN__SHIFT				7
+static inline uint32_t DPU_BN_CFG_BN_RELUX_EN(uint32_t val)
+{
+	return ((val) << DPU_BN_CFG_BN_RELUX_EN__SHIFT) & DPU_BN_CFG_BN_RELUX_EN__MASK;
+}
+#define DPU_BN_CFG_BN_RELU_BYPASS__MASK				0x00000040
+#define DPU_BN_CFG_BN_RELU_BYPASS__SHIFT			6
+static inline uint32_t DPU_BN_CFG_BN_RELU_BYPASS(uint32_t val)
+{
+	return ((val) << DPU_BN_CFG_BN_RELU_BYPASS__SHIFT) & DPU_BN_CFG_BN_RELU_BYPASS__MASK;
+}
+#define DPU_BN_CFG_BN_MUL_PRELU__MASK				0x00000020
+#define DPU_BN_CFG_BN_MUL_PRELU__SHIFT				5
+static inline uint32_t DPU_BN_CFG_BN_MUL_PRELU(uint32_t val)
+{
+	return ((val) << DPU_BN_CFG_BN_MUL_PRELU__SHIFT) & DPU_BN_CFG_BN_MUL_PRELU__MASK;
+}
+#define DPU_BN_CFG_BN_MUL_BYPASS__MASK				0x00000010
+#define DPU_BN_CFG_BN_MUL_BYPASS__SHIFT				4
+static inline uint32_t DPU_BN_CFG_BN_MUL_BYPASS(uint32_t val)
+{
+	return ((val) << DPU_BN_CFG_BN_MUL_BYPASS__SHIFT) & DPU_BN_CFG_BN_MUL_BYPASS__MASK;
+}
+#define DPU_BN_CFG_RESERVED_2__MASK				0x0000000c
+#define DPU_BN_CFG_RESERVED_2__SHIFT				2
+static inline uint32_t DPU_BN_CFG_RESERVED_2(uint32_t val)
+{
+	return ((val) << DPU_BN_CFG_RESERVED_2__SHIFT) & DPU_BN_CFG_RESERVED_2__MASK;
+}
+#define DPU_BN_CFG_BN_ALU_BYPASS__MASK				0x00000002
+#define DPU_BN_CFG_BN_ALU_BYPASS__SHIFT				1
+static inline uint32_t DPU_BN_CFG_BN_ALU_BYPASS(uint32_t val)
+{
+	return ((val) << DPU_BN_CFG_BN_ALU_BYPASS__SHIFT) & DPU_BN_CFG_BN_ALU_BYPASS__MASK;
+}
+#define DPU_BN_CFG_BN_BYPASS__MASK				0x00000001
+#define DPU_BN_CFG_BN_BYPASS__SHIFT				0
+static inline uint32_t DPU_BN_CFG_BN_BYPASS(uint32_t val)
+{
+	return ((val) << DPU_BN_CFG_BN_BYPASS__SHIFT) & DPU_BN_CFG_BN_BYPASS__MASK;
+}
+
+#define REG_DPU_BN_ALU_CFG					0x00004064
+#define DPU_BN_ALU_CFG_BN_ALU_OPERAND__MASK			0xffffffff
+#define DPU_BN_ALU_CFG_BN_ALU_OPERAND__SHIFT			0
+static inline uint32_t DPU_BN_ALU_CFG_BN_ALU_OPERAND(uint32_t val)
+{
+	return ((val) << DPU_BN_ALU_CFG_BN_ALU_OPERAND__SHIFT) & DPU_BN_ALU_CFG_BN_ALU_OPERAND__MASK;
+}
+
+#define REG_DPU_BN_MUL_CFG					0x00004068
+#define DPU_BN_MUL_CFG_BN_MUL_OPERAND__MASK			0xffff0000
+#define DPU_BN_MUL_CFG_BN_MUL_OPERAND__SHIFT			16
+static inline uint32_t DPU_BN_MUL_CFG_BN_MUL_OPERAND(uint32_t val)
+{
+	return ((val) << DPU_BN_MUL_CFG_BN_MUL_OPERAND__SHIFT) & DPU_BN_MUL_CFG_BN_MUL_OPERAND__MASK;
+}
+#define DPU_BN_MUL_CFG_RESERVED_0__MASK				0x0000c000
+#define DPU_BN_MUL_CFG_RESERVED_0__SHIFT			14
+static inline uint32_t DPU_BN_MUL_CFG_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_BN_MUL_CFG_RESERVED_0__SHIFT) & DPU_BN_MUL_CFG_RESERVED_0__MASK;
+}
+#define DPU_BN_MUL_CFG_BN_MUL_SHIFT_VALUE__MASK			0x00003f00
+#define DPU_BN_MUL_CFG_BN_MUL_SHIFT_VALUE__SHIFT		8
+static inline uint32_t DPU_BN_MUL_CFG_BN_MUL_SHIFT_VALUE(uint32_t val)
+{
+	return ((val) << DPU_BN_MUL_CFG_BN_MUL_SHIFT_VALUE__SHIFT) & DPU_BN_MUL_CFG_BN_MUL_SHIFT_VALUE__MASK;
+}
+#define DPU_BN_MUL_CFG_RESERVED_1__MASK				0x000000fc
+#define DPU_BN_MUL_CFG_RESERVED_1__SHIFT			2
+static inline uint32_t DPU_BN_MUL_CFG_RESERVED_1(uint32_t val)
+{
+	return ((val) << DPU_BN_MUL_CFG_RESERVED_1__SHIFT) & DPU_BN_MUL_CFG_RESERVED_1__MASK;
+}
+#define DPU_BN_MUL_CFG_BN_TRUNCATE_SRC__MASK			0x00000002
+#define DPU_BN_MUL_CFG_BN_TRUNCATE_SRC__SHIFT			1
+static inline uint32_t DPU_BN_MUL_CFG_BN_TRUNCATE_SRC(uint32_t val)
+{
+	return ((val) << DPU_BN_MUL_CFG_BN_TRUNCATE_SRC__SHIFT) & DPU_BN_MUL_CFG_BN_TRUNCATE_SRC__MASK;
+}
+#define DPU_BN_MUL_CFG_BN_MUL_SRC__MASK				0x00000001
+#define DPU_BN_MUL_CFG_BN_MUL_SRC__SHIFT			0
+static inline uint32_t DPU_BN_MUL_CFG_BN_MUL_SRC(uint32_t val)
+{
+	return ((val) << DPU_BN_MUL_CFG_BN_MUL_SRC__SHIFT) & DPU_BN_MUL_CFG_BN_MUL_SRC__MASK;
+}
+
+#define REG_DPU_BN_RELUX_CMP_VALUE				0x0000406c
+#define DPU_BN_RELUX_CMP_VALUE_BN_RELUX_CMP_DAT__MASK		0xffffffff
+#define DPU_BN_RELUX_CMP_VALUE_BN_RELUX_CMP_DAT__SHIFT		0
+static inline uint32_t DPU_BN_RELUX_CMP_VALUE_BN_RELUX_CMP_DAT(uint32_t val)
+{
+	return ((val) << DPU_BN_RELUX_CMP_VALUE_BN_RELUX_CMP_DAT__SHIFT) & DPU_BN_RELUX_CMP_VALUE_BN_RELUX_CMP_DAT__MASK;
+}
+
+#define REG_DPU_EW_CFG						0x00004070
+#define DPU_EW_CFG_EW_CVT_TYPE__MASK				0x80000000
+#define DPU_EW_CFG_EW_CVT_TYPE__SHIFT				31
+static inline uint32_t DPU_EW_CFG_EW_CVT_TYPE(uint32_t val)
+{
+	return ((val) << DPU_EW_CFG_EW_CVT_TYPE__SHIFT) & DPU_EW_CFG_EW_CVT_TYPE__MASK;
+}
+#define DPU_EW_CFG_EW_CVT_ROUND__MASK				0x40000000
+#define DPU_EW_CFG_EW_CVT_ROUND__SHIFT				30
+static inline uint32_t DPU_EW_CFG_EW_CVT_ROUND(uint32_t val)
+{
+	return ((val) << DPU_EW_CFG_EW_CVT_ROUND__SHIFT) & DPU_EW_CFG_EW_CVT_ROUND__MASK;
+}
+#define DPU_EW_CFG_EW_DATA_MODE__MASK				0x30000000
+#define DPU_EW_CFG_EW_DATA_MODE__SHIFT				28
+static inline uint32_t DPU_EW_CFG_EW_DATA_MODE(uint32_t val)
+{
+	return ((val) << DPU_EW_CFG_EW_DATA_MODE__SHIFT) & DPU_EW_CFG_EW_DATA_MODE__MASK;
+}
+#define DPU_EW_CFG_RESERVED_0__MASK				0x0f000000
+#define DPU_EW_CFG_RESERVED_0__SHIFT				24
+static inline uint32_t DPU_EW_CFG_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_EW_CFG_RESERVED_0__SHIFT) & DPU_EW_CFG_RESERVED_0__MASK;
+}
+#define DPU_EW_CFG_EDATA_SIZE__MASK				0x00c00000
+#define DPU_EW_CFG_EDATA_SIZE__SHIFT				22
+static inline uint32_t DPU_EW_CFG_EDATA_SIZE(uint32_t val)
+{
+	return ((val) << DPU_EW_CFG_EDATA_SIZE__SHIFT) & DPU_EW_CFG_EDATA_SIZE__MASK;
+}
+#define DPU_EW_CFG_EW_EQUAL_EN__MASK				0x00200000
+#define DPU_EW_CFG_EW_EQUAL_EN__SHIFT				21
+static inline uint32_t DPU_EW_CFG_EW_EQUAL_EN(uint32_t val)
+{
+	return ((val) << DPU_EW_CFG_EW_EQUAL_EN__SHIFT) & DPU_EW_CFG_EW_EQUAL_EN__MASK;
+}
+#define DPU_EW_CFG_EW_BINARY_EN__MASK				0x00100000
+#define DPU_EW_CFG_EW_BINARY_EN__SHIFT				20
+static inline uint32_t DPU_EW_CFG_EW_BINARY_EN(uint32_t val)
+{
+	return ((val) << DPU_EW_CFG_EW_BINARY_EN__SHIFT) & DPU_EW_CFG_EW_BINARY_EN__MASK;
+}
+#define DPU_EW_CFG_EW_ALU_ALGO__MASK				0x000f0000
+#define DPU_EW_CFG_EW_ALU_ALGO__SHIFT				16
+static inline uint32_t DPU_EW_CFG_EW_ALU_ALGO(uint32_t val)
+{
+	return ((val) << DPU_EW_CFG_EW_ALU_ALGO__SHIFT) & DPU_EW_CFG_EW_ALU_ALGO__MASK;
+}
+#define DPU_EW_CFG_RESERVED_1__MASK				0x0000f800
+#define DPU_EW_CFG_RESERVED_1__SHIFT				11
+static inline uint32_t DPU_EW_CFG_RESERVED_1(uint32_t val)
+{
+	return ((val) << DPU_EW_CFG_RESERVED_1__SHIFT) & DPU_EW_CFG_RESERVED_1__MASK;
+}
+#define DPU_EW_CFG_EW_RELUX_EN__MASK				0x00000400
+#define DPU_EW_CFG_EW_RELUX_EN__SHIFT				10
+static inline uint32_t DPU_EW_CFG_EW_RELUX_EN(uint32_t val)
+{
+	return ((val) << DPU_EW_CFG_EW_RELUX_EN__SHIFT) & DPU_EW_CFG_EW_RELUX_EN__MASK;
+}
+#define DPU_EW_CFG_EW_RELU_BYPASS__MASK				0x00000200
+#define DPU_EW_CFG_EW_RELU_BYPASS__SHIFT			9
+static inline uint32_t DPU_EW_CFG_EW_RELU_BYPASS(uint32_t val)
+{
+	return ((val) << DPU_EW_CFG_EW_RELU_BYPASS__SHIFT) & DPU_EW_CFG_EW_RELU_BYPASS__MASK;
+}
+#define DPU_EW_CFG_EW_OP_CVT_BYPASS__MASK			0x00000100
+#define DPU_EW_CFG_EW_OP_CVT_BYPASS__SHIFT			8
+static inline uint32_t DPU_EW_CFG_EW_OP_CVT_BYPASS(uint32_t val)
+{
+	return ((val) << DPU_EW_CFG_EW_OP_CVT_BYPASS__SHIFT) & DPU_EW_CFG_EW_OP_CVT_BYPASS__MASK;
+}
+#define DPU_EW_CFG_EW_LUT_BYPASS__MASK				0x00000080
+#define DPU_EW_CFG_EW_LUT_BYPASS__SHIFT				7
+static inline uint32_t DPU_EW_CFG_EW_LUT_BYPASS(uint32_t val)
+{
+	return ((val) << DPU_EW_CFG_EW_LUT_BYPASS__SHIFT) & DPU_EW_CFG_EW_LUT_BYPASS__MASK;
+}
+#define DPU_EW_CFG_EW_OP_SRC__MASK				0x00000040
+#define DPU_EW_CFG_EW_OP_SRC__SHIFT				6
+static inline uint32_t DPU_EW_CFG_EW_OP_SRC(uint32_t val)
+{
+	return ((val) << DPU_EW_CFG_EW_OP_SRC__SHIFT) & DPU_EW_CFG_EW_OP_SRC__MASK;
+}
+#define DPU_EW_CFG_EW_MUL_PRELU__MASK				0x00000020
+#define DPU_EW_CFG_EW_MUL_PRELU__SHIFT				5
+static inline uint32_t DPU_EW_CFG_EW_MUL_PRELU(uint32_t val)
+{
+	return ((val) << DPU_EW_CFG_EW_MUL_PRELU__SHIFT) & DPU_EW_CFG_EW_MUL_PRELU__MASK;
+}
+#define DPU_EW_CFG_RESERVED_2__MASK				0x00000018
+#define DPU_EW_CFG_RESERVED_2__SHIFT				3
+static inline uint32_t DPU_EW_CFG_RESERVED_2(uint32_t val)
+{
+	return ((val) << DPU_EW_CFG_RESERVED_2__SHIFT) & DPU_EW_CFG_RESERVED_2__MASK;
+}
+#define DPU_EW_CFG_EW_OP_TYPE__MASK				0x00000004
+#define DPU_EW_CFG_EW_OP_TYPE__SHIFT				2
+static inline uint32_t DPU_EW_CFG_EW_OP_TYPE(uint32_t val)
+{
+	return ((val) << DPU_EW_CFG_EW_OP_TYPE__SHIFT) & DPU_EW_CFG_EW_OP_TYPE__MASK;
+}
+#define DPU_EW_CFG_EW_OP_BYPASS__MASK				0x00000002
+#define DPU_EW_CFG_EW_OP_BYPASS__SHIFT				1
+static inline uint32_t DPU_EW_CFG_EW_OP_BYPASS(uint32_t val)
+{
+	return ((val) << DPU_EW_CFG_EW_OP_BYPASS__SHIFT) & DPU_EW_CFG_EW_OP_BYPASS__MASK;
+}
+#define DPU_EW_CFG_EW_BYPASS__MASK				0x00000001
+#define DPU_EW_CFG_EW_BYPASS__SHIFT				0
+static inline uint32_t DPU_EW_CFG_EW_BYPASS(uint32_t val)
+{
+	return ((val) << DPU_EW_CFG_EW_BYPASS__SHIFT) & DPU_EW_CFG_EW_BYPASS__MASK;
+}
+
+#define REG_DPU_EW_CVT_OFFSET_VALUE				0x00004074
+#define DPU_EW_CVT_OFFSET_VALUE_EW_OP_CVT_OFFSET__MASK		0xffffffff
+#define DPU_EW_CVT_OFFSET_VALUE_EW_OP_CVT_OFFSET__SHIFT		0
+static inline uint32_t DPU_EW_CVT_OFFSET_VALUE_EW_OP_CVT_OFFSET(uint32_t val)
+{
+	return ((val) << DPU_EW_CVT_OFFSET_VALUE_EW_OP_CVT_OFFSET__SHIFT) & DPU_EW_CVT_OFFSET_VALUE_EW_OP_CVT_OFFSET__MASK;
+}
+
+#define REG_DPU_EW_CVT_SCALE_VALUE				0x00004078
+#define DPU_EW_CVT_SCALE_VALUE_EW_TRUNCATE__MASK		0xffc00000
+#define DPU_EW_CVT_SCALE_VALUE_EW_TRUNCATE__SHIFT		22
+static inline uint32_t DPU_EW_CVT_SCALE_VALUE_EW_TRUNCATE(uint32_t val)
+{
+	return ((val) << DPU_EW_CVT_SCALE_VALUE_EW_TRUNCATE__SHIFT) & DPU_EW_CVT_SCALE_VALUE_EW_TRUNCATE__MASK;
+}
+#define DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SHIFT__MASK		0x003f0000
+#define DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SHIFT__SHIFT		16
+static inline uint32_t DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SHIFT(uint32_t val)
+{
+	return ((val) << DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SHIFT__SHIFT) & DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SHIFT__MASK;
+}
+#define DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SCALE__MASK		0x0000ffff
+#define DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SCALE__SHIFT		0
+static inline uint32_t DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SCALE(uint32_t val)
+{
+	return ((val) << DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SCALE__SHIFT) & DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SCALE__MASK;
+}
+
+#define REG_DPU_EW_RELUX_CMP_VALUE				0x0000407c
+#define DPU_EW_RELUX_CMP_VALUE_EW_RELUX_CMP_DAT__MASK		0xffffffff
+#define DPU_EW_RELUX_CMP_VALUE_EW_RELUX_CMP_DAT__SHIFT		0
+static inline uint32_t DPU_EW_RELUX_CMP_VALUE_EW_RELUX_CMP_DAT(uint32_t val)
+{
+	return ((val) << DPU_EW_RELUX_CMP_VALUE_EW_RELUX_CMP_DAT__SHIFT) & DPU_EW_RELUX_CMP_VALUE_EW_RELUX_CMP_DAT__MASK;
+}
+
+#define REG_DPU_OUT_CVT_OFFSET					0x00004080
+#define DPU_OUT_CVT_OFFSET_OUT_CVT_OFFSET__MASK			0xffffffff
+#define DPU_OUT_CVT_OFFSET_OUT_CVT_OFFSET__SHIFT		0
+static inline uint32_t DPU_OUT_CVT_OFFSET_OUT_CVT_OFFSET(uint32_t val)
+{
+	return ((val) << DPU_OUT_CVT_OFFSET_OUT_CVT_OFFSET__SHIFT) & DPU_OUT_CVT_OFFSET_OUT_CVT_OFFSET__MASK;
+}
+
+#define REG_DPU_OUT_CVT_SCALE					0x00004084
+#define DPU_OUT_CVT_SCALE_RESERVED_0__MASK			0xfffe0000
+#define DPU_OUT_CVT_SCALE_RESERVED_0__SHIFT			17
+static inline uint32_t DPU_OUT_CVT_SCALE_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_OUT_CVT_SCALE_RESERVED_0__SHIFT) & DPU_OUT_CVT_SCALE_RESERVED_0__MASK;
+}
+#define DPU_OUT_CVT_SCALE_FP32TOFP16_EN__MASK			0x00010000
+#define DPU_OUT_CVT_SCALE_FP32TOFP16_EN__SHIFT			16
+static inline uint32_t DPU_OUT_CVT_SCALE_FP32TOFP16_EN(uint32_t val)
+{
+	return ((val) << DPU_OUT_CVT_SCALE_FP32TOFP16_EN__SHIFT) & DPU_OUT_CVT_SCALE_FP32TOFP16_EN__MASK;
+}
+#define DPU_OUT_CVT_SCALE_OUT_CVT_SCALE__MASK			0x0000ffff
+#define DPU_OUT_CVT_SCALE_OUT_CVT_SCALE__SHIFT			0
+static inline uint32_t DPU_OUT_CVT_SCALE_OUT_CVT_SCALE(uint32_t val)
+{
+	return ((val) << DPU_OUT_CVT_SCALE_OUT_CVT_SCALE__SHIFT) & DPU_OUT_CVT_SCALE_OUT_CVT_SCALE__MASK;
+}
+
+#define REG_DPU_OUT_CVT_SHIFT					0x00004088
+#define DPU_OUT_CVT_SHIFT_CVT_TYPE__MASK			0x80000000
+#define DPU_OUT_CVT_SHIFT_CVT_TYPE__SHIFT			31
+static inline uint32_t DPU_OUT_CVT_SHIFT_CVT_TYPE(uint32_t val)
+{
+	return ((val) << DPU_OUT_CVT_SHIFT_CVT_TYPE__SHIFT) & DPU_OUT_CVT_SHIFT_CVT_TYPE__MASK;
+}
+#define DPU_OUT_CVT_SHIFT_CVT_ROUND__MASK			0x40000000
+#define DPU_OUT_CVT_SHIFT_CVT_ROUND__SHIFT			30
+static inline uint32_t DPU_OUT_CVT_SHIFT_CVT_ROUND(uint32_t val)
+{
+	return ((val) << DPU_OUT_CVT_SHIFT_CVT_ROUND__SHIFT) & DPU_OUT_CVT_SHIFT_CVT_ROUND__MASK;
+}
+#define DPU_OUT_CVT_SHIFT_RESERVED_0__MASK			0x3ff00000
+#define DPU_OUT_CVT_SHIFT_RESERVED_0__SHIFT			20
+static inline uint32_t DPU_OUT_CVT_SHIFT_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_OUT_CVT_SHIFT_RESERVED_0__SHIFT) & DPU_OUT_CVT_SHIFT_RESERVED_0__MASK;
+}
+#define DPU_OUT_CVT_SHIFT_MINUS_EXP__MASK			0x000ff000
+#define DPU_OUT_CVT_SHIFT_MINUS_EXP__SHIFT			12
+static inline uint32_t DPU_OUT_CVT_SHIFT_MINUS_EXP(uint32_t val)
+{
+	return ((val) << DPU_OUT_CVT_SHIFT_MINUS_EXP__SHIFT) & DPU_OUT_CVT_SHIFT_MINUS_EXP__MASK;
+}
+#define DPU_OUT_CVT_SHIFT_OUT_CVT_SHIFT__MASK			0x00000fff
+#define DPU_OUT_CVT_SHIFT_OUT_CVT_SHIFT__SHIFT			0
+static inline uint32_t DPU_OUT_CVT_SHIFT_OUT_CVT_SHIFT(uint32_t val)
+{
+	return ((val) << DPU_OUT_CVT_SHIFT_OUT_CVT_SHIFT__SHIFT) & DPU_OUT_CVT_SHIFT_OUT_CVT_SHIFT__MASK;
+}
+
+#define REG_DPU_EW_OP_VALUE_0					0x00004090
+#define DPU_EW_OP_VALUE_0_EW_OPERAND_0__MASK			0xffffffff
+#define DPU_EW_OP_VALUE_0_EW_OPERAND_0__SHIFT			0
+static inline uint32_t DPU_EW_OP_VALUE_0_EW_OPERAND_0(uint32_t val)
+{
+	return ((val) << DPU_EW_OP_VALUE_0_EW_OPERAND_0__SHIFT) & DPU_EW_OP_VALUE_0_EW_OPERAND_0__MASK;
+}
+
+#define REG_DPU_EW_OP_VALUE_1					0x00004094
+#define DPU_EW_OP_VALUE_1_EW_OPERAND_1__MASK			0xffffffff
+#define DPU_EW_OP_VALUE_1_EW_OPERAND_1__SHIFT			0
+static inline uint32_t DPU_EW_OP_VALUE_1_EW_OPERAND_1(uint32_t val)
+{
+	return ((val) << DPU_EW_OP_VALUE_1_EW_OPERAND_1__SHIFT) & DPU_EW_OP_VALUE_1_EW_OPERAND_1__MASK;
+}
+
+#define REG_DPU_EW_OP_VALUE_2					0x00004098
+#define DPU_EW_OP_VALUE_2_EW_OPERAND_2__MASK			0xffffffff
+#define DPU_EW_OP_VALUE_2_EW_OPERAND_2__SHIFT			0
+static inline uint32_t DPU_EW_OP_VALUE_2_EW_OPERAND_2(uint32_t val)
+{
+	return ((val) << DPU_EW_OP_VALUE_2_EW_OPERAND_2__SHIFT) & DPU_EW_OP_VALUE_2_EW_OPERAND_2__MASK;
+}
+
+#define REG_DPU_EW_OP_VALUE_3					0x0000409c
+#define DPU_EW_OP_VALUE_3_EW_OPERAND_3__MASK			0xffffffff
+#define DPU_EW_OP_VALUE_3_EW_OPERAND_3__SHIFT			0
+static inline uint32_t DPU_EW_OP_VALUE_3_EW_OPERAND_3(uint32_t val)
+{
+	return ((val) << DPU_EW_OP_VALUE_3_EW_OPERAND_3__SHIFT) & DPU_EW_OP_VALUE_3_EW_OPERAND_3__MASK;
+}
+
+#define REG_DPU_EW_OP_VALUE_4					0x000040a0
+#define DPU_EW_OP_VALUE_4_EW_OPERAND_4__MASK			0xffffffff
+#define DPU_EW_OP_VALUE_4_EW_OPERAND_4__SHIFT			0
+static inline uint32_t DPU_EW_OP_VALUE_4_EW_OPERAND_4(uint32_t val)
+{
+	return ((val) << DPU_EW_OP_VALUE_4_EW_OPERAND_4__SHIFT) & DPU_EW_OP_VALUE_4_EW_OPERAND_4__MASK;
+}
+
+#define REG_DPU_EW_OP_VALUE_5					0x000040a4
+#define DPU_EW_OP_VALUE_5_EW_OPERAND_5__MASK			0xffffffff
+#define DPU_EW_OP_VALUE_5_EW_OPERAND_5__SHIFT			0
+static inline uint32_t DPU_EW_OP_VALUE_5_EW_OPERAND_5(uint32_t val)
+{
+	return ((val) << DPU_EW_OP_VALUE_5_EW_OPERAND_5__SHIFT) & DPU_EW_OP_VALUE_5_EW_OPERAND_5__MASK;
+}
+
+#define REG_DPU_EW_OP_VALUE_6					0x000040a8
+#define DPU_EW_OP_VALUE_6_EW_OPERAND_6__MASK			0xffffffff
+#define DPU_EW_OP_VALUE_6_EW_OPERAND_6__SHIFT			0
+static inline uint32_t DPU_EW_OP_VALUE_6_EW_OPERAND_6(uint32_t val)
+{
+	return ((val) << DPU_EW_OP_VALUE_6_EW_OPERAND_6__SHIFT) & DPU_EW_OP_VALUE_6_EW_OPERAND_6__MASK;
+}
+
+#define REG_DPU_EW_OP_VALUE_7					0x000040ac
+#define DPU_EW_OP_VALUE_7_EW_OPERAND_7__MASK			0xffffffff
+#define DPU_EW_OP_VALUE_7_EW_OPERAND_7__SHIFT			0
+static inline uint32_t DPU_EW_OP_VALUE_7_EW_OPERAND_7(uint32_t val)
+{
+	return ((val) << DPU_EW_OP_VALUE_7_EW_OPERAND_7__SHIFT) & DPU_EW_OP_VALUE_7_EW_OPERAND_7__MASK;
+}
+
+#define REG_DPU_SURFACE_ADD					0x000040c0
+#define DPU_SURFACE_ADD_SURF_ADD__MASK				0xfffffff0
+#define DPU_SURFACE_ADD_SURF_ADD__SHIFT				4
+static inline uint32_t DPU_SURFACE_ADD_SURF_ADD(uint32_t val)
+{
+	return ((val) << DPU_SURFACE_ADD_SURF_ADD__SHIFT) & DPU_SURFACE_ADD_SURF_ADD__MASK;
+}
+#define DPU_SURFACE_ADD_RESERVED_0__MASK			0x0000000f
+#define DPU_SURFACE_ADD_RESERVED_0__SHIFT			0
+static inline uint32_t DPU_SURFACE_ADD_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_SURFACE_ADD_RESERVED_0__SHIFT) & DPU_SURFACE_ADD_RESERVED_0__MASK;
+}
+
+#define REG_DPU_LUT_ACCESS_CFG					0x00004100
+#define DPU_LUT_ACCESS_CFG_RESERVED_0__MASK			0xfffc0000
+#define DPU_LUT_ACCESS_CFG_RESERVED_0__SHIFT			18
+static inline uint32_t DPU_LUT_ACCESS_CFG_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_LUT_ACCESS_CFG_RESERVED_0__SHIFT) & DPU_LUT_ACCESS_CFG_RESERVED_0__MASK;
+}
+#define DPU_LUT_ACCESS_CFG_LUT_ACCESS_TYPE__MASK		0x00020000
+#define DPU_LUT_ACCESS_CFG_LUT_ACCESS_TYPE__SHIFT		17
+static inline uint32_t DPU_LUT_ACCESS_CFG_LUT_ACCESS_TYPE(uint32_t val)
+{
+	return ((val) << DPU_LUT_ACCESS_CFG_LUT_ACCESS_TYPE__SHIFT) & DPU_LUT_ACCESS_CFG_LUT_ACCESS_TYPE__MASK;
+}
+#define DPU_LUT_ACCESS_CFG_LUT_TABLE_ID__MASK			0x00010000
+#define DPU_LUT_ACCESS_CFG_LUT_TABLE_ID__SHIFT			16
+static inline uint32_t DPU_LUT_ACCESS_CFG_LUT_TABLE_ID(uint32_t val)
+{
+	return ((val) << DPU_LUT_ACCESS_CFG_LUT_TABLE_ID__SHIFT) & DPU_LUT_ACCESS_CFG_LUT_TABLE_ID__MASK;
+}
+#define DPU_LUT_ACCESS_CFG_RESERVED_1__MASK			0x0000fc00
+#define DPU_LUT_ACCESS_CFG_RESERVED_1__SHIFT			10
+static inline uint32_t DPU_LUT_ACCESS_CFG_RESERVED_1(uint32_t val)
+{
+	return ((val) << DPU_LUT_ACCESS_CFG_RESERVED_1__SHIFT) & DPU_LUT_ACCESS_CFG_RESERVED_1__MASK;
+}
+#define DPU_LUT_ACCESS_CFG_LUT_ADDR__MASK			0x000003ff
+#define DPU_LUT_ACCESS_CFG_LUT_ADDR__SHIFT			0
+static inline uint32_t DPU_LUT_ACCESS_CFG_LUT_ADDR(uint32_t val)
+{
+	return ((val) << DPU_LUT_ACCESS_CFG_LUT_ADDR__SHIFT) & DPU_LUT_ACCESS_CFG_LUT_ADDR__MASK;
+}
+
+#define REG_DPU_LUT_ACCESS_DATA					0x00004104
+#define DPU_LUT_ACCESS_DATA_RESERVED_0__MASK			0xffff0000
+#define DPU_LUT_ACCESS_DATA_RESERVED_0__SHIFT			16
+static inline uint32_t DPU_LUT_ACCESS_DATA_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_LUT_ACCESS_DATA_RESERVED_0__SHIFT) & DPU_LUT_ACCESS_DATA_RESERVED_0__MASK;
+}
+#define DPU_LUT_ACCESS_DATA_LUT_ACCESS_DATA__MASK		0x0000ffff
+#define DPU_LUT_ACCESS_DATA_LUT_ACCESS_DATA__SHIFT		0
+static inline uint32_t DPU_LUT_ACCESS_DATA_LUT_ACCESS_DATA(uint32_t val)
+{
+	return ((val) << DPU_LUT_ACCESS_DATA_LUT_ACCESS_DATA__SHIFT) & DPU_LUT_ACCESS_DATA_LUT_ACCESS_DATA__MASK;
+}
+
+#define REG_DPU_LUT_CFG						0x00004108
+#define DPU_LUT_CFG_RESERVED_0__MASK				0xffffff00
+#define DPU_LUT_CFG_RESERVED_0__SHIFT				8
+static inline uint32_t DPU_LUT_CFG_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_LUT_CFG_RESERVED_0__SHIFT) & DPU_LUT_CFG_RESERVED_0__MASK;
+}
+#define DPU_LUT_CFG_LUT_CAL_SEL__MASK				0x00000080
+#define DPU_LUT_CFG_LUT_CAL_SEL__SHIFT				7
+static inline uint32_t DPU_LUT_CFG_LUT_CAL_SEL(uint32_t val)
+{
+	return ((val) << DPU_LUT_CFG_LUT_CAL_SEL__SHIFT) & DPU_LUT_CFG_LUT_CAL_SEL__MASK;
+}
+#define DPU_LUT_CFG_LUT_HYBRID_PRIORITY__MASK			0x00000040
+#define DPU_LUT_CFG_LUT_HYBRID_PRIORITY__SHIFT			6
+static inline uint32_t DPU_LUT_CFG_LUT_HYBRID_PRIORITY(uint32_t val)
+{
+	return ((val) << DPU_LUT_CFG_LUT_HYBRID_PRIORITY__SHIFT) & DPU_LUT_CFG_LUT_HYBRID_PRIORITY__MASK;
+}
+#define DPU_LUT_CFG_LUT_OFLOW_PRIORITY__MASK			0x00000020
+#define DPU_LUT_CFG_LUT_OFLOW_PRIORITY__SHIFT			5
+static inline uint32_t DPU_LUT_CFG_LUT_OFLOW_PRIORITY(uint32_t val)
+{
+	return ((val) << DPU_LUT_CFG_LUT_OFLOW_PRIORITY__SHIFT) & DPU_LUT_CFG_LUT_OFLOW_PRIORITY__MASK;
+}
+#define DPU_LUT_CFG_LUT_UFLOW_PRIORITY__MASK			0x00000010
+#define DPU_LUT_CFG_LUT_UFLOW_PRIORITY__SHIFT			4
+static inline uint32_t DPU_LUT_CFG_LUT_UFLOW_PRIORITY(uint32_t val)
+{
+	return ((val) << DPU_LUT_CFG_LUT_UFLOW_PRIORITY__SHIFT) & DPU_LUT_CFG_LUT_UFLOW_PRIORITY__MASK;
+}
+#define DPU_LUT_CFG_LUT_LO_LE_MUX__MASK				0x0000000c
+#define DPU_LUT_CFG_LUT_LO_LE_MUX__SHIFT			2
+static inline uint32_t DPU_LUT_CFG_LUT_LO_LE_MUX(uint32_t val)
+{
+	return ((val) << DPU_LUT_CFG_LUT_LO_LE_MUX__SHIFT) & DPU_LUT_CFG_LUT_LO_LE_MUX__MASK;
+}
+#define DPU_LUT_CFG_LUT_EXPAND_EN__MASK				0x00000002
+#define DPU_LUT_CFG_LUT_EXPAND_EN__SHIFT			1
+static inline uint32_t DPU_LUT_CFG_LUT_EXPAND_EN(uint32_t val)
+{
+	return ((val) << DPU_LUT_CFG_LUT_EXPAND_EN__SHIFT) & DPU_LUT_CFG_LUT_EXPAND_EN__MASK;
+}
+#define DPU_LUT_CFG_LUT_ROAD_SEL__MASK				0x00000001
+#define DPU_LUT_CFG_LUT_ROAD_SEL__SHIFT				0
+static inline uint32_t DPU_LUT_CFG_LUT_ROAD_SEL(uint32_t val)
+{
+	return ((val) << DPU_LUT_CFG_LUT_ROAD_SEL__SHIFT) & DPU_LUT_CFG_LUT_ROAD_SEL__MASK;
+}
+
+#define REG_DPU_LUT_INFO					0x0000410c
+#define DPU_LUT_INFO_RESERVED_0__MASK				0xff000000
+#define DPU_LUT_INFO_RESERVED_0__SHIFT				24
+static inline uint32_t DPU_LUT_INFO_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_LUT_INFO_RESERVED_0__SHIFT) & DPU_LUT_INFO_RESERVED_0__MASK;
+}
+#define DPU_LUT_INFO_LUT_LO_INDEX_SELECT__MASK			0x00ff0000
+#define DPU_LUT_INFO_LUT_LO_INDEX_SELECT__SHIFT			16
+static inline uint32_t DPU_LUT_INFO_LUT_LO_INDEX_SELECT(uint32_t val)
+{
+	return ((val) << DPU_LUT_INFO_LUT_LO_INDEX_SELECT__SHIFT) & DPU_LUT_INFO_LUT_LO_INDEX_SELECT__MASK;
+}
+#define DPU_LUT_INFO_LUT_LE_INDEX_SELECT__MASK			0x0000ff00
+#define DPU_LUT_INFO_LUT_LE_INDEX_SELECT__SHIFT			8
+static inline uint32_t DPU_LUT_INFO_LUT_LE_INDEX_SELECT(uint32_t val)
+{
+	return ((val) << DPU_LUT_INFO_LUT_LE_INDEX_SELECT__SHIFT) & DPU_LUT_INFO_LUT_LE_INDEX_SELECT__MASK;
+}
+#define DPU_LUT_INFO_RESERVED_1__MASK				0x000000ff
+#define DPU_LUT_INFO_RESERVED_1__SHIFT				0
+static inline uint32_t DPU_LUT_INFO_RESERVED_1(uint32_t val)
+{
+	return ((val) << DPU_LUT_INFO_RESERVED_1__SHIFT) & DPU_LUT_INFO_RESERVED_1__MASK;
+}
+
+#define REG_DPU_LUT_LE_START					0x00004110
+#define DPU_LUT_LE_START_LUT_LE_START__MASK			0xffffffff
+#define DPU_LUT_LE_START_LUT_LE_START__SHIFT			0
+static inline uint32_t DPU_LUT_LE_START_LUT_LE_START(uint32_t val)
+{
+	return ((val) << DPU_LUT_LE_START_LUT_LE_START__SHIFT) & DPU_LUT_LE_START_LUT_LE_START__MASK;
+}
+
+#define REG_DPU_LUT_LE_END					0x00004114
+#define DPU_LUT_LE_END_LUT_LE_END__MASK				0xffffffff
+#define DPU_LUT_LE_END_LUT_LE_END__SHIFT			0
+static inline uint32_t DPU_LUT_LE_END_LUT_LE_END(uint32_t val)
+{
+	return ((val) << DPU_LUT_LE_END_LUT_LE_END__SHIFT) & DPU_LUT_LE_END_LUT_LE_END__MASK;
+}
+
+#define REG_DPU_LUT_LO_START					0x00004118
+#define DPU_LUT_LO_START_LUT_LO_START__MASK			0xffffffff
+#define DPU_LUT_LO_START_LUT_LO_START__SHIFT			0
+static inline uint32_t DPU_LUT_LO_START_LUT_LO_START(uint32_t val)
+{
+	return ((val) << DPU_LUT_LO_START_LUT_LO_START__SHIFT) & DPU_LUT_LO_START_LUT_LO_START__MASK;
+}
+
+#define REG_DPU_LUT_LO_END					0x0000411c
+#define DPU_LUT_LO_END_LUT_LO_END__MASK				0xffffffff
+#define DPU_LUT_LO_END_LUT_LO_END__SHIFT			0
+static inline uint32_t DPU_LUT_LO_END_LUT_LO_END(uint32_t val)
+{
+	return ((val) << DPU_LUT_LO_END_LUT_LO_END__SHIFT) & DPU_LUT_LO_END_LUT_LO_END__MASK;
+}
+
+#define REG_DPU_LUT_LE_SLOPE_SCALE				0x00004120
+#define DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_OFLOW_SCALE__MASK	0xffff0000
+#define DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_OFLOW_SCALE__SHIFT	16
+static inline uint32_t DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_OFLOW_SCALE(uint32_t val)
+{
+	return ((val) << DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_OFLOW_SCALE__SHIFT) & DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_OFLOW_SCALE__MASK;
+}
+#define DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_UFLOW_SCALE__MASK	0x0000ffff
+#define DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_UFLOW_SCALE__SHIFT	0
+static inline uint32_t DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_UFLOW_SCALE(uint32_t val)
+{
+	return ((val) << DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_UFLOW_SCALE__SHIFT) & DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_UFLOW_SCALE__MASK;
+}
+
+#define REG_DPU_LUT_LE_SLOPE_SHIFT				0x00004124
+#define DPU_LUT_LE_SLOPE_SHIFT_RESERVED_0__MASK			0xfffffc00
+#define DPU_LUT_LE_SLOPE_SHIFT_RESERVED_0__SHIFT		10
+static inline uint32_t DPU_LUT_LE_SLOPE_SHIFT_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_LUT_LE_SLOPE_SHIFT_RESERVED_0__SHIFT) & DPU_LUT_LE_SLOPE_SHIFT_RESERVED_0__MASK;
+}
+#define DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_OFLOW_SHIFT__MASK	0x000003e0
+#define DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_OFLOW_SHIFT__SHIFT	5
+static inline uint32_t DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_OFLOW_SHIFT(uint32_t val)
+{
+	return ((val) << DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_OFLOW_SHIFT__SHIFT) & DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_OFLOW_SHIFT__MASK;
+}
+#define DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_UFLOW_SHIFT__MASK	0x0000001f
+#define DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_UFLOW_SHIFT__SHIFT	0
+static inline uint32_t DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_UFLOW_SHIFT(uint32_t val)
+{
+	return ((val) << DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_UFLOW_SHIFT__SHIFT) & DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_UFLOW_SHIFT__MASK;
+}
+
+#define REG_DPU_LUT_LO_SLOPE_SCALE				0x00004128
+#define DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_OFLOW_SCALE__MASK	0xffff0000
+#define DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_OFLOW_SCALE__SHIFT	16
+static inline uint32_t DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_OFLOW_SCALE(uint32_t val)
+{
+	return ((val) << DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_OFLOW_SCALE__SHIFT) & DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_OFLOW_SCALE__MASK;
+}
+#define DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_UFLOW_SCALE__MASK	0x0000ffff
+#define DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_UFLOW_SCALE__SHIFT	0
+static inline uint32_t DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_UFLOW_SCALE(uint32_t val)
+{
+	return ((val) << DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_UFLOW_SCALE__SHIFT) & DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_UFLOW_SCALE__MASK;
+}
+
+#define REG_DPU_LUT_LO_SLOPE_SHIFT				0x0000412c
+#define DPU_LUT_LO_SLOPE_SHIFT_RESERVED_0__MASK			0xfffffc00
+#define DPU_LUT_LO_SLOPE_SHIFT_RESERVED_0__SHIFT		10
+static inline uint32_t DPU_LUT_LO_SLOPE_SHIFT_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_LUT_LO_SLOPE_SHIFT_RESERVED_0__SHIFT) & DPU_LUT_LO_SLOPE_SHIFT_RESERVED_0__MASK;
+}
+#define DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_OFLOW_SHIFT__MASK	0x000003e0
+#define DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_OFLOW_SHIFT__SHIFT	5
+static inline uint32_t DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_OFLOW_SHIFT(uint32_t val)
+{
+	return ((val) << DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_OFLOW_SHIFT__SHIFT) & DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_OFLOW_SHIFT__MASK;
+}
+#define DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_UFLOW_SHIFT__MASK	0x0000001f
+#define DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_UFLOW_SHIFT__SHIFT	0
+static inline uint32_t DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_UFLOW_SHIFT(uint32_t val)
+{
+	return ((val) << DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_UFLOW_SHIFT__SHIFT) & DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_UFLOW_SHIFT__MASK;
+}
+
+#define REG_DPU_RDMA_RDMA_S_STATUS				0x00005000
+#define DPU_RDMA_RDMA_S_STATUS_RESERVED_0__MASK			0xfffc0000
+#define DPU_RDMA_RDMA_S_STATUS_RESERVED_0__SHIFT		18
+static inline uint32_t DPU_RDMA_RDMA_S_STATUS_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_S_STATUS_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_S_STATUS_RESERVED_0__MASK;
+}
+#define DPU_RDMA_RDMA_S_STATUS_STATUS_1__MASK			0x00030000
+#define DPU_RDMA_RDMA_S_STATUS_STATUS_1__SHIFT			16
+static inline uint32_t DPU_RDMA_RDMA_S_STATUS_STATUS_1(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_S_STATUS_STATUS_1__SHIFT) & DPU_RDMA_RDMA_S_STATUS_STATUS_1__MASK;
+}
+#define DPU_RDMA_RDMA_S_STATUS_RESERVED_1__MASK			0x0000fffc
+#define DPU_RDMA_RDMA_S_STATUS_RESERVED_1__SHIFT		2
+static inline uint32_t DPU_RDMA_RDMA_S_STATUS_RESERVED_1(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_S_STATUS_RESERVED_1__SHIFT) & DPU_RDMA_RDMA_S_STATUS_RESERVED_1__MASK;
+}
+#define DPU_RDMA_RDMA_S_STATUS_STATUS_0__MASK			0x00000003
+#define DPU_RDMA_RDMA_S_STATUS_STATUS_0__SHIFT			0
+static inline uint32_t DPU_RDMA_RDMA_S_STATUS_STATUS_0(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_S_STATUS_STATUS_0__SHIFT) & DPU_RDMA_RDMA_S_STATUS_STATUS_0__MASK;
+}
+
+#define REG_DPU_RDMA_RDMA_S_POINTER				0x00005004
+#define DPU_RDMA_RDMA_S_POINTER_RESERVED_0__MASK		0xfffe0000
+#define DPU_RDMA_RDMA_S_POINTER_RESERVED_0__SHIFT		17
+static inline uint32_t DPU_RDMA_RDMA_S_POINTER_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_S_POINTER_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_S_POINTER_RESERVED_0__MASK;
+}
+#define DPU_RDMA_RDMA_S_POINTER_EXECUTER__MASK			0x00010000
+#define DPU_RDMA_RDMA_S_POINTER_EXECUTER__SHIFT			16
+static inline uint32_t DPU_RDMA_RDMA_S_POINTER_EXECUTER(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_S_POINTER_EXECUTER__SHIFT) & DPU_RDMA_RDMA_S_POINTER_EXECUTER__MASK;
+}
+#define DPU_RDMA_RDMA_S_POINTER_RESERVED_1__MASK		0x0000ffc0
+#define DPU_RDMA_RDMA_S_POINTER_RESERVED_1__SHIFT		6
+static inline uint32_t DPU_RDMA_RDMA_S_POINTER_RESERVED_1(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_S_POINTER_RESERVED_1__SHIFT) & DPU_RDMA_RDMA_S_POINTER_RESERVED_1__MASK;
+}
+#define DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__MASK		0x00000020
+#define DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__SHIFT	5
+static inline uint32_t DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__SHIFT) & DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__MASK;
+}
+#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__MASK		0x00000010
+#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__SHIFT		4
+static inline uint32_t DPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__SHIFT) & DPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__MASK;
+}
+#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__MASK		0x00000008
+#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__SHIFT		3
+static inline uint32_t DPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__SHIFT) & DPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__MASK;
+}
+#define DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__MASK		0x00000004
+#define DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__SHIFT		2
+static inline uint32_t DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__SHIFT) & DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__MASK;
+}
+#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__MASK		0x00000002
+#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__SHIFT		1
+static inline uint32_t DPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__SHIFT) & DPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__MASK;
+}
+#define DPU_RDMA_RDMA_S_POINTER_POINTER__MASK			0x00000001
+#define DPU_RDMA_RDMA_S_POINTER_POINTER__SHIFT			0
+static inline uint32_t DPU_RDMA_RDMA_S_POINTER_POINTER(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_S_POINTER_POINTER__SHIFT) & DPU_RDMA_RDMA_S_POINTER_POINTER__MASK;
+}
+
+#define REG_DPU_RDMA_RDMA_OPERATION_ENABLE			0x00005008
+#define DPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__MASK		0xfffffffe
+#define DPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__SHIFT	1
+static inline uint32_t DPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__MASK;
+}
+#define DPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__MASK		0x00000001
+#define DPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__SHIFT		0
+static inline uint32_t DPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__SHIFT) & DPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__MASK;
+}
+
+#define REG_DPU_RDMA_RDMA_DATA_CUBE_WIDTH			0x0000500c
+#define DPU_RDMA_RDMA_DATA_CUBE_WIDTH_RESERVED_0__MASK		0xffffe000
+#define DPU_RDMA_RDMA_DATA_CUBE_WIDTH_RESERVED_0__SHIFT		13
+static inline uint32_t DPU_RDMA_RDMA_DATA_CUBE_WIDTH_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_DATA_CUBE_WIDTH_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_DATA_CUBE_WIDTH_RESERVED_0__MASK;
+}
+#define DPU_RDMA_RDMA_DATA_CUBE_WIDTH_WIDTH__MASK		0x00001fff
+#define DPU_RDMA_RDMA_DATA_CUBE_WIDTH_WIDTH__SHIFT		0
+static inline uint32_t DPU_RDMA_RDMA_DATA_CUBE_WIDTH_WIDTH(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_DATA_CUBE_WIDTH_WIDTH__SHIFT) & DPU_RDMA_RDMA_DATA_CUBE_WIDTH_WIDTH__MASK;
+}
+
+#define REG_DPU_RDMA_RDMA_DATA_CUBE_HEIGHT			0x00005010
+#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_0__MASK		0xe0000000
+#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_0__SHIFT	29
+static inline uint32_t DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_0__MASK;
+}
+#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_EW_LINE_NOTCH_ADDR__MASK	0x1fff0000
+#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_EW_LINE_NOTCH_ADDR__SHIFT	16
+static inline uint32_t DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_EW_LINE_NOTCH_ADDR(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_EW_LINE_NOTCH_ADDR__SHIFT) & DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_EW_LINE_NOTCH_ADDR__MASK;
+}
+#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_1__MASK		0x0000e000
+#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_1__SHIFT	13
+static inline uint32_t DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_1(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_1__SHIFT) & DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_1__MASK;
+}
+#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_HEIGHT__MASK		0x00001fff
+#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_HEIGHT__SHIFT		0
+static inline uint32_t DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_HEIGHT(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_HEIGHT__SHIFT) & DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_HEIGHT__MASK;
+}
+
+#define REG_DPU_RDMA_RDMA_DATA_CUBE_CHANNEL			0x00005014
+#define DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_RESERVED_0__MASK	0xffffe000
+#define DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_RESERVED_0__SHIFT	13
+static inline uint32_t DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_RESERVED_0__MASK;
+}
+#define DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_CHANNEL__MASK		0x00001fff
+#define DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_CHANNEL__SHIFT		0
+static inline uint32_t DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_CHANNEL(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_CHANNEL__SHIFT) & DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_CHANNEL__MASK;
+}
+
+#define REG_DPU_RDMA_RDMA_SRC_BASE_ADDR				0x00005018
+#define DPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__MASK		0xffffffff
+#define DPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__SHIFT	0
+static inline uint32_t DPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__SHIFT) & DPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__MASK;
+}
+
+#define REG_DPU_RDMA_RDMA_BRDMA_CFG				0x0000501c
+#define DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_0__MASK		0xffffffe0
+#define DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_0__SHIFT		5
+static inline uint32_t DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_0__MASK;
+}
+#define DPU_RDMA_RDMA_BRDMA_CFG_BRDMA_DATA_USE__MASK		0x0000001e
+#define DPU_RDMA_RDMA_BRDMA_CFG_BRDMA_DATA_USE__SHIFT		1
+static inline uint32_t DPU_RDMA_RDMA_BRDMA_CFG_BRDMA_DATA_USE(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_BRDMA_CFG_BRDMA_DATA_USE__SHIFT) & DPU_RDMA_RDMA_BRDMA_CFG_BRDMA_DATA_USE__MASK;
+}
+#define DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_1__MASK		0x00000001
+#define DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_1__SHIFT		0
+static inline uint32_t DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_1(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_1__SHIFT) & DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_1__MASK;
+}
+
+#define REG_DPU_RDMA_RDMA_BS_BASE_ADDR				0x00005020
+#define DPU_RDMA_RDMA_BS_BASE_ADDR_BS_BASE_ADDR__MASK		0xffffffff
+#define DPU_RDMA_RDMA_BS_BASE_ADDR_BS_BASE_ADDR__SHIFT		0
+static inline uint32_t DPU_RDMA_RDMA_BS_BASE_ADDR_BS_BASE_ADDR(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_BS_BASE_ADDR_BS_BASE_ADDR__SHIFT) & DPU_RDMA_RDMA_BS_BASE_ADDR_BS_BASE_ADDR__MASK;
+}
+
+#define REG_DPU_RDMA_RDMA_NRDMA_CFG				0x00005028
+#define DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_0__MASK		0xffffffe0
+#define DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_0__SHIFT		5
+static inline uint32_t DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_0__MASK;
+}
+#define DPU_RDMA_RDMA_NRDMA_CFG_NRDMA_DATA_USE__MASK		0x0000001e
+#define DPU_RDMA_RDMA_NRDMA_CFG_NRDMA_DATA_USE__SHIFT		1
+static inline uint32_t DPU_RDMA_RDMA_NRDMA_CFG_NRDMA_DATA_USE(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_NRDMA_CFG_NRDMA_DATA_USE__SHIFT) & DPU_RDMA_RDMA_NRDMA_CFG_NRDMA_DATA_USE__MASK;
+}
+#define DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_1__MASK		0x00000001
+#define DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_1__SHIFT		0
+static inline uint32_t DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_1(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_1__SHIFT) & DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_1__MASK;
+}
+
+#define REG_DPU_RDMA_RDMA_BN_BASE_ADDR				0x0000502c
+#define DPU_RDMA_RDMA_BN_BASE_ADDR_BN_BASE_ADDR__MASK		0xffffffff
+#define DPU_RDMA_RDMA_BN_BASE_ADDR_BN_BASE_ADDR__SHIFT		0
+static inline uint32_t DPU_RDMA_RDMA_BN_BASE_ADDR_BN_BASE_ADDR(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_BN_BASE_ADDR_BN_BASE_ADDR__SHIFT) & DPU_RDMA_RDMA_BN_BASE_ADDR_BN_BASE_ADDR__MASK;
+}
+
+#define REG_DPU_RDMA_RDMA_ERDMA_CFG				0x00005034
+#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_MODE__MASK		0xc0000000
+#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_MODE__SHIFT		30
+static inline uint32_t DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_MODE(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_MODE__SHIFT) & DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_MODE__MASK;
+}
+#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_SURF_MODE__MASK		0x20000000
+#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_SURF_MODE__SHIFT		29
+static inline uint32_t DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_SURF_MODE(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_SURF_MODE__SHIFT) & DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_SURF_MODE__MASK;
+}
+#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_NONALIGN__MASK		0x10000000
+#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_NONALIGN__SHIFT		28
+static inline uint32_t DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_NONALIGN(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_NONALIGN__SHIFT) & DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_NONALIGN__MASK;
+}
+#define DPU_RDMA_RDMA_ERDMA_CFG_RESERVED_0__MASK		0x0ffffff0
+#define DPU_RDMA_RDMA_ERDMA_CFG_RESERVED_0__SHIFT		4
+static inline uint32_t DPU_RDMA_RDMA_ERDMA_CFG_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_ERDMA_CFG_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_ERDMA_CFG_RESERVED_0__MASK;
+}
+#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_SIZE__MASK		0x0000000c
+#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_SIZE__SHIFT		2
+static inline uint32_t DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_SIZE(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_SIZE__SHIFT) & DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_SIZE__MASK;
+}
+#define DPU_RDMA_RDMA_ERDMA_CFG_OV4K_BYPASS__MASK		0x00000002
+#define DPU_RDMA_RDMA_ERDMA_CFG_OV4K_BYPASS__SHIFT		1
+static inline uint32_t DPU_RDMA_RDMA_ERDMA_CFG_OV4K_BYPASS(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_ERDMA_CFG_OV4K_BYPASS__SHIFT) & DPU_RDMA_RDMA_ERDMA_CFG_OV4K_BYPASS__MASK;
+}
+#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DISABLE__MASK		0x00000001
+#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DISABLE__SHIFT		0
+static inline uint32_t DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DISABLE(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DISABLE__SHIFT) & DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DISABLE__MASK;
+}
+
+#define REG_DPU_RDMA_RDMA_EW_BASE_ADDR				0x00005038
+#define DPU_RDMA_RDMA_EW_BASE_ADDR_EW_BASE_ADDR__MASK		0xffffffff
+#define DPU_RDMA_RDMA_EW_BASE_ADDR_EW_BASE_ADDR__SHIFT		0
+static inline uint32_t DPU_RDMA_RDMA_EW_BASE_ADDR_EW_BASE_ADDR(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_EW_BASE_ADDR_EW_BASE_ADDR__SHIFT) & DPU_RDMA_RDMA_EW_BASE_ADDR_EW_BASE_ADDR__MASK;
+}
+
+#define REG_DPU_RDMA_RDMA_EW_SURF_STRIDE			0x00005040
+#define DPU_RDMA_RDMA_EW_SURF_STRIDE_EW_SURF_STRIDE__MASK	0xfffffff0
+#define DPU_RDMA_RDMA_EW_SURF_STRIDE_EW_SURF_STRIDE__SHIFT	4
+static inline uint32_t DPU_RDMA_RDMA_EW_SURF_STRIDE_EW_SURF_STRIDE(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_EW_SURF_STRIDE_EW_SURF_STRIDE__SHIFT) & DPU_RDMA_RDMA_EW_SURF_STRIDE_EW_SURF_STRIDE__MASK;
+}
+#define DPU_RDMA_RDMA_EW_SURF_STRIDE_RESERVED_0__MASK		0x0000000f
+#define DPU_RDMA_RDMA_EW_SURF_STRIDE_RESERVED_0__SHIFT		0
+static inline uint32_t DPU_RDMA_RDMA_EW_SURF_STRIDE_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_EW_SURF_STRIDE_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_EW_SURF_STRIDE_RESERVED_0__MASK;
+}
+
+#define REG_DPU_RDMA_RDMA_FEATURE_MODE_CFG			0x00005044
+#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_RESERVED_0__MASK		0xfffc0000
+#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_RESERVED_0__SHIFT	18
+static inline uint32_t DPU_RDMA_RDMA_FEATURE_MODE_CFG_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_FEATURE_MODE_CFG_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_FEATURE_MODE_CFG_RESERVED_0__MASK;
+}
+#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_IN_PRECISION__MASK	0x00038000
+#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_IN_PRECISION__SHIFT	15
+static inline uint32_t DPU_RDMA_RDMA_FEATURE_MODE_CFG_IN_PRECISION(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_FEATURE_MODE_CFG_IN_PRECISION__SHIFT) & DPU_RDMA_RDMA_FEATURE_MODE_CFG_IN_PRECISION__MASK;
+}
+#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_BURST_LEN__MASK		0x00007800
+#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_BURST_LEN__SHIFT		11
+static inline uint32_t DPU_RDMA_RDMA_FEATURE_MODE_CFG_BURST_LEN(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_FEATURE_MODE_CFG_BURST_LEN__SHIFT) & DPU_RDMA_RDMA_FEATURE_MODE_CFG_BURST_LEN__MASK;
+}
+#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_COMB_USE__MASK		0x00000700
+#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_COMB_USE__SHIFT		8
+static inline uint32_t DPU_RDMA_RDMA_FEATURE_MODE_CFG_COMB_USE(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_FEATURE_MODE_CFG_COMB_USE__SHIFT) & DPU_RDMA_RDMA_FEATURE_MODE_CFG_COMB_USE__MASK;
+}
+#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_PROC_PRECISION__MASK	0x000000e0
+#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_PROC_PRECISION__SHIFT	5
+static inline uint32_t DPU_RDMA_RDMA_FEATURE_MODE_CFG_PROC_PRECISION(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_FEATURE_MODE_CFG_PROC_PRECISION__SHIFT) & DPU_RDMA_RDMA_FEATURE_MODE_CFG_PROC_PRECISION__MASK;
+}
+#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_DISABLE__MASK	0x00000010
+#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_DISABLE__SHIFT	4
+static inline uint32_t DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_DISABLE(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_DISABLE__SHIFT) & DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_DISABLE__MASK;
+}
+#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_FP16TOFP32_EN__MASK	0x00000008
+#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_FP16TOFP32_EN__SHIFT	3
+static inline uint32_t DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_FP16TOFP32_EN(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_FP16TOFP32_EN__SHIFT) & DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_FP16TOFP32_EN__MASK;
+}
+#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_CONV_MODE__MASK		0x00000006
+#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_CONV_MODE__SHIFT		1
+static inline uint32_t DPU_RDMA_RDMA_FEATURE_MODE_CFG_CONV_MODE(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_FEATURE_MODE_CFG_CONV_MODE__SHIFT) & DPU_RDMA_RDMA_FEATURE_MODE_CFG_CONV_MODE__MASK;
+}
+#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_FLYING_MODE__MASK	0x00000001
+#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_FLYING_MODE__SHIFT	0
+static inline uint32_t DPU_RDMA_RDMA_FEATURE_MODE_CFG_FLYING_MODE(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_FEATURE_MODE_CFG_FLYING_MODE__SHIFT) & DPU_RDMA_RDMA_FEATURE_MODE_CFG_FLYING_MODE__MASK;
+}
+
+#define REG_DPU_RDMA_RDMA_SRC_DMA_CFG				0x00005048
+#define DPU_RDMA_RDMA_SRC_DMA_CFG_LINE_NOTCH_ADDR__MASK		0xfff80000
+#define DPU_RDMA_RDMA_SRC_DMA_CFG_LINE_NOTCH_ADDR__SHIFT	19
+static inline uint32_t DPU_RDMA_RDMA_SRC_DMA_CFG_LINE_NOTCH_ADDR(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_SRC_DMA_CFG_LINE_NOTCH_ADDR__SHIFT) & DPU_RDMA_RDMA_SRC_DMA_CFG_LINE_NOTCH_ADDR__MASK;
+}
+#define DPU_RDMA_RDMA_SRC_DMA_CFG_RESERVED_0__MASK		0x0007c000
+#define DPU_RDMA_RDMA_SRC_DMA_CFG_RESERVED_0__SHIFT		14
+static inline uint32_t DPU_RDMA_RDMA_SRC_DMA_CFG_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_SRC_DMA_CFG_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_SRC_DMA_CFG_RESERVED_0__MASK;
+}
+#define DPU_RDMA_RDMA_SRC_DMA_CFG_POOLING_METHOD__MASK		0x00002000
+#define DPU_RDMA_RDMA_SRC_DMA_CFG_POOLING_METHOD__SHIFT		13
+static inline uint32_t DPU_RDMA_RDMA_SRC_DMA_CFG_POOLING_METHOD(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_SRC_DMA_CFG_POOLING_METHOD__SHIFT) & DPU_RDMA_RDMA_SRC_DMA_CFG_POOLING_METHOD__MASK;
+}
+#define DPU_RDMA_RDMA_SRC_DMA_CFG_UNPOOLING_EN__MASK		0x00001000
+#define DPU_RDMA_RDMA_SRC_DMA_CFG_UNPOOLING_EN__SHIFT		12
+static inline uint32_t DPU_RDMA_RDMA_SRC_DMA_CFG_UNPOOLING_EN(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_SRC_DMA_CFG_UNPOOLING_EN__SHIFT) & DPU_RDMA_RDMA_SRC_DMA_CFG_UNPOOLING_EN__MASK;
+}
+#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_HEIGHT__MASK	0x00000e00
+#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_HEIGHT__SHIFT	9
+static inline uint32_t DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_HEIGHT(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_HEIGHT__SHIFT) & DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_HEIGHT__MASK;
+}
+#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_WIDTH__MASK	0x000001c0
+#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_WIDTH__SHIFT	6
+static inline uint32_t DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_WIDTH(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_WIDTH__SHIFT) & DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_WIDTH__MASK;
+}
+#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_HEIGHT__MASK		0x00000038
+#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_HEIGHT__SHIFT		3
+static inline uint32_t DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_HEIGHT(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_HEIGHT__SHIFT) & DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_HEIGHT__MASK;
+}
+#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_WIDTH__MASK		0x00000007
+#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_WIDTH__SHIFT		0
+static inline uint32_t DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_WIDTH(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_WIDTH__SHIFT) & DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_WIDTH__MASK;
+}
+
+#define REG_DPU_RDMA_RDMA_SURF_NOTCH				0x0000504c
+#define DPU_RDMA_RDMA_SURF_NOTCH_SURF_NOTCH_ADDR__MASK		0xfffffff0
+#define DPU_RDMA_RDMA_SURF_NOTCH_SURF_NOTCH_ADDR__SHIFT		4
+static inline uint32_t DPU_RDMA_RDMA_SURF_NOTCH_SURF_NOTCH_ADDR(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_SURF_NOTCH_SURF_NOTCH_ADDR__SHIFT) & DPU_RDMA_RDMA_SURF_NOTCH_SURF_NOTCH_ADDR__MASK;
+}
+#define DPU_RDMA_RDMA_SURF_NOTCH_RESERVED_0__MASK		0x0000000f
+#define DPU_RDMA_RDMA_SURF_NOTCH_RESERVED_0__SHIFT		0
+static inline uint32_t DPU_RDMA_RDMA_SURF_NOTCH_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_SURF_NOTCH_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_SURF_NOTCH_RESERVED_0__MASK;
+}
+
+#define REG_DPU_RDMA_RDMA_PAD_CFG				0x00005064
+#define DPU_RDMA_RDMA_PAD_CFG_PAD_VALUE__MASK			0xffff0000
+#define DPU_RDMA_RDMA_PAD_CFG_PAD_VALUE__SHIFT			16
+static inline uint32_t DPU_RDMA_RDMA_PAD_CFG_PAD_VALUE(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_PAD_CFG_PAD_VALUE__SHIFT) & DPU_RDMA_RDMA_PAD_CFG_PAD_VALUE__MASK;
+}
+#define DPU_RDMA_RDMA_PAD_CFG_RESERVED_0__MASK			0x0000ff80
+#define DPU_RDMA_RDMA_PAD_CFG_RESERVED_0__SHIFT			7
+static inline uint32_t DPU_RDMA_RDMA_PAD_CFG_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_PAD_CFG_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_PAD_CFG_RESERVED_0__MASK;
+}
+#define DPU_RDMA_RDMA_PAD_CFG_PAD_TOP__MASK			0x00000070
+#define DPU_RDMA_RDMA_PAD_CFG_PAD_TOP__SHIFT			4
+static inline uint32_t DPU_RDMA_RDMA_PAD_CFG_PAD_TOP(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_PAD_CFG_PAD_TOP__SHIFT) & DPU_RDMA_RDMA_PAD_CFG_PAD_TOP__MASK;
+}
+#define DPU_RDMA_RDMA_PAD_CFG_RESERVED_1__MASK			0x00000008
+#define DPU_RDMA_RDMA_PAD_CFG_RESERVED_1__SHIFT			3
+static inline uint32_t DPU_RDMA_RDMA_PAD_CFG_RESERVED_1(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_PAD_CFG_RESERVED_1__SHIFT) & DPU_RDMA_RDMA_PAD_CFG_RESERVED_1__MASK;
+}
+#define DPU_RDMA_RDMA_PAD_CFG_PAD_LEFT__MASK			0x00000007
+#define DPU_RDMA_RDMA_PAD_CFG_PAD_LEFT__SHIFT			0
+static inline uint32_t DPU_RDMA_RDMA_PAD_CFG_PAD_LEFT(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_PAD_CFG_PAD_LEFT__SHIFT) & DPU_RDMA_RDMA_PAD_CFG_PAD_LEFT__MASK;
+}
+
+#define REG_DPU_RDMA_RDMA_WEIGHT				0x00005068
+#define DPU_RDMA_RDMA_WEIGHT_E_WEIGHT__MASK			0xff000000
+#define DPU_RDMA_RDMA_WEIGHT_E_WEIGHT__SHIFT			24
+static inline uint32_t DPU_RDMA_RDMA_WEIGHT_E_WEIGHT(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_WEIGHT_E_WEIGHT__SHIFT) & DPU_RDMA_RDMA_WEIGHT_E_WEIGHT__MASK;
+}
+#define DPU_RDMA_RDMA_WEIGHT_N_WEIGHT__MASK			0x00ff0000
+#define DPU_RDMA_RDMA_WEIGHT_N_WEIGHT__SHIFT			16
+static inline uint32_t DPU_RDMA_RDMA_WEIGHT_N_WEIGHT(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_WEIGHT_N_WEIGHT__SHIFT) & DPU_RDMA_RDMA_WEIGHT_N_WEIGHT__MASK;
+}
+#define DPU_RDMA_RDMA_WEIGHT_B_WEIGHT__MASK			0x0000ff00
+#define DPU_RDMA_RDMA_WEIGHT_B_WEIGHT__SHIFT			8
+static inline uint32_t DPU_RDMA_RDMA_WEIGHT_B_WEIGHT(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_WEIGHT_B_WEIGHT__SHIFT) & DPU_RDMA_RDMA_WEIGHT_B_WEIGHT__MASK;
+}
+#define DPU_RDMA_RDMA_WEIGHT_M_WEIGHT__MASK			0x000000ff
+#define DPU_RDMA_RDMA_WEIGHT_M_WEIGHT__SHIFT			0
+static inline uint32_t DPU_RDMA_RDMA_WEIGHT_M_WEIGHT(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_WEIGHT_M_WEIGHT__SHIFT) & DPU_RDMA_RDMA_WEIGHT_M_WEIGHT__MASK;
+}
+
+#define REG_DPU_RDMA_RDMA_EW_SURF_NOTCH				0x0000506c
+#define DPU_RDMA_RDMA_EW_SURF_NOTCH_EW_SURF_NOTCH__MASK		0xfffffff0
+#define DPU_RDMA_RDMA_EW_SURF_NOTCH_EW_SURF_NOTCH__SHIFT	4
+static inline uint32_t DPU_RDMA_RDMA_EW_SURF_NOTCH_EW_SURF_NOTCH(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_EW_SURF_NOTCH_EW_SURF_NOTCH__SHIFT) & DPU_RDMA_RDMA_EW_SURF_NOTCH_EW_SURF_NOTCH__MASK;
+}
+#define DPU_RDMA_RDMA_EW_SURF_NOTCH_RESERVED_0__MASK		0x0000000f
+#define DPU_RDMA_RDMA_EW_SURF_NOTCH_RESERVED_0__SHIFT		0
+static inline uint32_t DPU_RDMA_RDMA_EW_SURF_NOTCH_RESERVED_0(uint32_t val)
+{
+	return ((val) << DPU_RDMA_RDMA_EW_SURF_NOTCH_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_EW_SURF_NOTCH_RESERVED_0__MASK;
+}
+
+#define REG_PPU_S_STATUS					0x00006000
+#define PPU_S_STATUS_RESERVED_0__MASK				0xfffc0000
+#define PPU_S_STATUS_RESERVED_0__SHIFT				18
+static inline uint32_t PPU_S_STATUS_RESERVED_0(uint32_t val)
+{
+	return ((val) << PPU_S_STATUS_RESERVED_0__SHIFT) & PPU_S_STATUS_RESERVED_0__MASK;
+}
+#define PPU_S_STATUS_STATUS_1__MASK				0x00030000
+#define PPU_S_STATUS_STATUS_1__SHIFT				16
+static inline uint32_t PPU_S_STATUS_STATUS_1(uint32_t val)
+{
+	return ((val) << PPU_S_STATUS_STATUS_1__SHIFT) & PPU_S_STATUS_STATUS_1__MASK;
+}
+#define PPU_S_STATUS_RESERVED_1__MASK				0x0000fffc
+#define PPU_S_STATUS_RESERVED_1__SHIFT				2
+static inline uint32_t PPU_S_STATUS_RESERVED_1(uint32_t val)
+{
+	return ((val) << PPU_S_STATUS_RESERVED_1__SHIFT) & PPU_S_STATUS_RESERVED_1__MASK;
+}
+#define PPU_S_STATUS_STATUS_0__MASK				0x00000003
+#define PPU_S_STATUS_STATUS_0__SHIFT				0
+static inline uint32_t PPU_S_STATUS_STATUS_0(uint32_t val)
+{
+	return ((val) << PPU_S_STATUS_STATUS_0__SHIFT) & PPU_S_STATUS_STATUS_0__MASK;
+}
+
+#define REG_PPU_S_POINTER					0x00006004
+#define PPU_S_POINTER_RESERVED_0__MASK				0xfffe0000
+#define PPU_S_POINTER_RESERVED_0__SHIFT				17
+static inline uint32_t PPU_S_POINTER_RESERVED_0(uint32_t val)
+{
+	return ((val) << PPU_S_POINTER_RESERVED_0__SHIFT) & PPU_S_POINTER_RESERVED_0__MASK;
+}
+#define PPU_S_POINTER_EXECUTER__MASK				0x00010000
+#define PPU_S_POINTER_EXECUTER__SHIFT				16
+static inline uint32_t PPU_S_POINTER_EXECUTER(uint32_t val)
+{
+	return ((val) << PPU_S_POINTER_EXECUTER__SHIFT) & PPU_S_POINTER_EXECUTER__MASK;
+}
+#define PPU_S_POINTER_RESERVED_1__MASK				0x0000ffc0
+#define PPU_S_POINTER_RESERVED_1__SHIFT				6
+static inline uint32_t PPU_S_POINTER_RESERVED_1(uint32_t val)
+{
+	return ((val) << PPU_S_POINTER_RESERVED_1__SHIFT) & PPU_S_POINTER_RESERVED_1__MASK;
+}
+#define PPU_S_POINTER_EXECUTER_PP_CLEAR__MASK			0x00000020
+#define PPU_S_POINTER_EXECUTER_PP_CLEAR__SHIFT			5
+static inline uint32_t PPU_S_POINTER_EXECUTER_PP_CLEAR(uint32_t val)
+{
+	return ((val) << PPU_S_POINTER_EXECUTER_PP_CLEAR__SHIFT) & PPU_S_POINTER_EXECUTER_PP_CLEAR__MASK;
+}
+#define PPU_S_POINTER_POINTER_PP_CLEAR__MASK			0x00000010
+#define PPU_S_POINTER_POINTER_PP_CLEAR__SHIFT			4
+static inline uint32_t PPU_S_POINTER_POINTER_PP_CLEAR(uint32_t val)
+{
+	return ((val) << PPU_S_POINTER_POINTER_PP_CLEAR__SHIFT) & PPU_S_POINTER_POINTER_PP_CLEAR__MASK;
+}
+#define PPU_S_POINTER_POINTER_PP_MODE__MASK			0x00000008
+#define PPU_S_POINTER_POINTER_PP_MODE__SHIFT			3
+static inline uint32_t PPU_S_POINTER_POINTER_PP_MODE(uint32_t val)
+{
+	return ((val) << PPU_S_POINTER_POINTER_PP_MODE__SHIFT) & PPU_S_POINTER_POINTER_PP_MODE__MASK;
+}
+#define PPU_S_POINTER_EXECUTER_PP_EN__MASK			0x00000004
+#define PPU_S_POINTER_EXECUTER_PP_EN__SHIFT			2
+static inline uint32_t PPU_S_POINTER_EXECUTER_PP_EN(uint32_t val)
+{
+	return ((val) << PPU_S_POINTER_EXECUTER_PP_EN__SHIFT) & PPU_S_POINTER_EXECUTER_PP_EN__MASK;
+}
+#define PPU_S_POINTER_POINTER_PP_EN__MASK			0x00000002
+#define PPU_S_POINTER_POINTER_PP_EN__SHIFT			1
+static inline uint32_t PPU_S_POINTER_POINTER_PP_EN(uint32_t val)
+{
+	return ((val) << PPU_S_POINTER_POINTER_PP_EN__SHIFT) & PPU_S_POINTER_POINTER_PP_EN__MASK;
+}
+#define PPU_S_POINTER_POINTER__MASK				0x00000001
+#define PPU_S_POINTER_POINTER__SHIFT				0
+static inline uint32_t PPU_S_POINTER_POINTER(uint32_t val)
+{
+	return ((val) << PPU_S_POINTER_POINTER__SHIFT) & PPU_S_POINTER_POINTER__MASK;
+}
+
+#define REG_PPU_OPERATION_ENABLE				0x00006008
+#define PPU_OPERATION_ENABLE_RESERVED_0__MASK			0xfffffffe
+#define PPU_OPERATION_ENABLE_RESERVED_0__SHIFT			1
+static inline uint32_t PPU_OPERATION_ENABLE_RESERVED_0(uint32_t val)
+{
+	return ((val) << PPU_OPERATION_ENABLE_RESERVED_0__SHIFT) & PPU_OPERATION_ENABLE_RESERVED_0__MASK;
+}
+#define PPU_OPERATION_ENABLE_OP_EN__MASK			0x00000001
+#define PPU_OPERATION_ENABLE_OP_EN__SHIFT			0
+static inline uint32_t PPU_OPERATION_ENABLE_OP_EN(uint32_t val)
+{
+	return ((val) << PPU_OPERATION_ENABLE_OP_EN__SHIFT) & PPU_OPERATION_ENABLE_OP_EN__MASK;
+}
+
+#define REG_PPU_DATA_CUBE_IN_WIDTH				0x0000600c
+#define PPU_DATA_CUBE_IN_WIDTH_RESERVED_0__MASK			0xffffe000
+#define PPU_DATA_CUBE_IN_WIDTH_RESERVED_0__SHIFT		13
+static inline uint32_t PPU_DATA_CUBE_IN_WIDTH_RESERVED_0(uint32_t val)
+{
+	return ((val) << PPU_DATA_CUBE_IN_WIDTH_RESERVED_0__SHIFT) & PPU_DATA_CUBE_IN_WIDTH_RESERVED_0__MASK;
+}
+#define PPU_DATA_CUBE_IN_WIDTH_CUBE_IN_WIDTH__MASK		0x00001fff
+#define PPU_DATA_CUBE_IN_WIDTH_CUBE_IN_WIDTH__SHIFT		0
+static inline uint32_t PPU_DATA_CUBE_IN_WIDTH_CUBE_IN_WIDTH(uint32_t val)
+{
+	return ((val) << PPU_DATA_CUBE_IN_WIDTH_CUBE_IN_WIDTH__SHIFT) & PPU_DATA_CUBE_IN_WIDTH_CUBE_IN_WIDTH__MASK;
+}
+
+#define REG_PPU_DATA_CUBE_IN_HEIGHT				0x00006010
+#define PPU_DATA_CUBE_IN_HEIGHT_RESERVED_0__MASK		0xffffe000
+#define PPU_DATA_CUBE_IN_HEIGHT_RESERVED_0__SHIFT		13
+static inline uint32_t PPU_DATA_CUBE_IN_HEIGHT_RESERVED_0(uint32_t val)
+{
+	return ((val) << PPU_DATA_CUBE_IN_HEIGHT_RESERVED_0__SHIFT) & PPU_DATA_CUBE_IN_HEIGHT_RESERVED_0__MASK;
+}
+#define PPU_DATA_CUBE_IN_HEIGHT_CUBE_IN_HEIGHT__MASK		0x00001fff
+#define PPU_DATA_CUBE_IN_HEIGHT_CUBE_IN_HEIGHT__SHIFT		0
+static inline uint32_t PPU_DATA_CUBE_IN_HEIGHT_CUBE_IN_HEIGHT(uint32_t val)
+{
+	return ((val) << PPU_DATA_CUBE_IN_HEIGHT_CUBE_IN_HEIGHT__SHIFT) & PPU_DATA_CUBE_IN_HEIGHT_CUBE_IN_HEIGHT__MASK;
+}
+
+#define REG_PPU_DATA_CUBE_IN_CHANNEL				0x00006014
+#define PPU_DATA_CUBE_IN_CHANNEL_RESERVED_0__MASK		0xffffe000
+#define PPU_DATA_CUBE_IN_CHANNEL_RESERVED_0__SHIFT		13
+static inline uint32_t PPU_DATA_CUBE_IN_CHANNEL_RESERVED_0(uint32_t val)
+{
+	return ((val) << PPU_DATA_CUBE_IN_CHANNEL_RESERVED_0__SHIFT) & PPU_DATA_CUBE_IN_CHANNEL_RESERVED_0__MASK;
+}
+#define PPU_DATA_CUBE_IN_CHANNEL_CUBE_IN_CHANNEL__MASK		0x00001fff
+#define PPU_DATA_CUBE_IN_CHANNEL_CUBE_IN_CHANNEL__SHIFT		0
+static inline uint32_t PPU_DATA_CUBE_IN_CHANNEL_CUBE_IN_CHANNEL(uint32_t val)
+{
+	return ((val) << PPU_DATA_CUBE_IN_CHANNEL_CUBE_IN_CHANNEL__SHIFT) & PPU_DATA_CUBE_IN_CHANNEL_CUBE_IN_CHANNEL__MASK;
+}
+
+#define REG_PPU_DATA_CUBE_OUT_WIDTH				0x00006018
+#define PPU_DATA_CUBE_OUT_WIDTH_RESERVED_0__MASK		0xffffe000
+#define PPU_DATA_CUBE_OUT_WIDTH_RESERVED_0__SHIFT		13
+static inline uint32_t PPU_DATA_CUBE_OUT_WIDTH_RESERVED_0(uint32_t val)
+{
+	return ((val) << PPU_DATA_CUBE_OUT_WIDTH_RESERVED_0__SHIFT) & PPU_DATA_CUBE_OUT_WIDTH_RESERVED_0__MASK;
+}
+#define PPU_DATA_CUBE_OUT_WIDTH_CUBE_OUT_WIDTH__MASK		0x00001fff
+#define PPU_DATA_CUBE_OUT_WIDTH_CUBE_OUT_WIDTH__SHIFT		0
+static inline uint32_t PPU_DATA_CUBE_OUT_WIDTH_CUBE_OUT_WIDTH(uint32_t val)
+{
+	return ((val) << PPU_DATA_CUBE_OUT_WIDTH_CUBE_OUT_WIDTH__SHIFT) & PPU_DATA_CUBE_OUT_WIDTH_CUBE_OUT_WIDTH__MASK;
+}
+
+#define REG_PPU_DATA_CUBE_OUT_HEIGHT				0x0000601c
+#define PPU_DATA_CUBE_OUT_HEIGHT_RESERVED_0__MASK		0xffffe000
+#define PPU_DATA_CUBE_OUT_HEIGHT_RESERVED_0__SHIFT		13
+static inline uint32_t PPU_DATA_CUBE_OUT_HEIGHT_RESERVED_0(uint32_t val)
+{
+	return ((val) << PPU_DATA_CUBE_OUT_HEIGHT_RESERVED_0__SHIFT) & PPU_DATA_CUBE_OUT_HEIGHT_RESERVED_0__MASK;
+}
+#define PPU_DATA_CUBE_OUT_HEIGHT_CUBE_OUT_HEIGHT__MASK		0x00001fff
+#define PPU_DATA_CUBE_OUT_HEIGHT_CUBE_OUT_HEIGHT__SHIFT		0
+static inline uint32_t PPU_DATA_CUBE_OUT_HEIGHT_CUBE_OUT_HEIGHT(uint32_t val)
+{
+	return ((val) << PPU_DATA_CUBE_OUT_HEIGHT_CUBE_OUT_HEIGHT__SHIFT) & PPU_DATA_CUBE_OUT_HEIGHT_CUBE_OUT_HEIGHT__MASK;
+}
+
+#define REG_PPU_DATA_CUBE_OUT_CHANNEL				0x00006020
+#define PPU_DATA_CUBE_OUT_CHANNEL_RESERVED_0__MASK		0xffffe000
+#define PPU_DATA_CUBE_OUT_CHANNEL_RESERVED_0__SHIFT		13
+static inline uint32_t PPU_DATA_CUBE_OUT_CHANNEL_RESERVED_0(uint32_t val)
+{
+	return ((val) << PPU_DATA_CUBE_OUT_CHANNEL_RESERVED_0__SHIFT) & PPU_DATA_CUBE_OUT_CHANNEL_RESERVED_0__MASK;
+}
+#define PPU_DATA_CUBE_OUT_CHANNEL_CUBE_OUT_CHANNEL__MASK	0x00001fff
+#define PPU_DATA_CUBE_OUT_CHANNEL_CUBE_OUT_CHANNEL__SHIFT	0
+static inline uint32_t PPU_DATA_CUBE_OUT_CHANNEL_CUBE_OUT_CHANNEL(uint32_t val)
+{
+	return ((val) << PPU_DATA_CUBE_OUT_CHANNEL_CUBE_OUT_CHANNEL__SHIFT) & PPU_DATA_CUBE_OUT_CHANNEL_CUBE_OUT_CHANNEL__MASK;
+}
+
+#define REG_PPU_OPERATION_MODE_CFG				0x00006024
+#define PPU_OPERATION_MODE_CFG_RESERVED_0__MASK			0x80000000
+#define PPU_OPERATION_MODE_CFG_RESERVED_0__SHIFT		31
+static inline uint32_t PPU_OPERATION_MODE_CFG_RESERVED_0(uint32_t val)
+{
+	return ((val) << PPU_OPERATION_MODE_CFG_RESERVED_0__SHIFT) & PPU_OPERATION_MODE_CFG_RESERVED_0__MASK;
+}
+#define PPU_OPERATION_MODE_CFG_INDEX_EN__MASK			0x40000000
+#define PPU_OPERATION_MODE_CFG_INDEX_EN__SHIFT			30
+static inline uint32_t PPU_OPERATION_MODE_CFG_INDEX_EN(uint32_t val)
+{
+	return ((val) << PPU_OPERATION_MODE_CFG_INDEX_EN__SHIFT) & PPU_OPERATION_MODE_CFG_INDEX_EN__MASK;
+}
+#define PPU_OPERATION_MODE_CFG_RESERVED_1__MASK			0x20000000
+#define PPU_OPERATION_MODE_CFG_RESERVED_1__SHIFT		29
+static inline uint32_t PPU_OPERATION_MODE_CFG_RESERVED_1(uint32_t val)
+{
+	return ((val) << PPU_OPERATION_MODE_CFG_RESERVED_1__SHIFT) & PPU_OPERATION_MODE_CFG_RESERVED_1__MASK;
+}
+#define PPU_OPERATION_MODE_CFG_NOTCH_ADDR__MASK			0x1fff0000
+#define PPU_OPERATION_MODE_CFG_NOTCH_ADDR__SHIFT		16
+static inline uint32_t PPU_OPERATION_MODE_CFG_NOTCH_ADDR(uint32_t val)
+{
+	return ((val) << PPU_OPERATION_MODE_CFG_NOTCH_ADDR__SHIFT) & PPU_OPERATION_MODE_CFG_NOTCH_ADDR__MASK;
+}
+#define PPU_OPERATION_MODE_CFG_RESERVED_2__MASK			0x0000ff00
+#define PPU_OPERATION_MODE_CFG_RESERVED_2__SHIFT		8
+static inline uint32_t PPU_OPERATION_MODE_CFG_RESERVED_2(uint32_t val)
+{
+	return ((val) << PPU_OPERATION_MODE_CFG_RESERVED_2__SHIFT) & PPU_OPERATION_MODE_CFG_RESERVED_2__MASK;
+}
+#define PPU_OPERATION_MODE_CFG_USE_CNT__MASK			0x000000e0
+#define PPU_OPERATION_MODE_CFG_USE_CNT__SHIFT			5
+static inline uint32_t PPU_OPERATION_MODE_CFG_USE_CNT(uint32_t val)
+{
+	return ((val) << PPU_OPERATION_MODE_CFG_USE_CNT__SHIFT) & PPU_OPERATION_MODE_CFG_USE_CNT__MASK;
+}
+#define PPU_OPERATION_MODE_CFG_FLYING_MODE__MASK		0x00000010
+#define PPU_OPERATION_MODE_CFG_FLYING_MODE__SHIFT		4
+static inline uint32_t PPU_OPERATION_MODE_CFG_FLYING_MODE(uint32_t val)
+{
+	return ((val) << PPU_OPERATION_MODE_CFG_FLYING_MODE__SHIFT) & PPU_OPERATION_MODE_CFG_FLYING_MODE__MASK;
+}
+#define PPU_OPERATION_MODE_CFG_RESERVED_3__MASK			0x0000000c
+#define PPU_OPERATION_MODE_CFG_RESERVED_3__SHIFT		2
+static inline uint32_t PPU_OPERATION_MODE_CFG_RESERVED_3(uint32_t val)
+{
+	return ((val) << PPU_OPERATION_MODE_CFG_RESERVED_3__SHIFT) & PPU_OPERATION_MODE_CFG_RESERVED_3__MASK;
+}
+#define PPU_OPERATION_MODE_CFG_POOLING_METHOD__MASK		0x00000003
+#define PPU_OPERATION_MODE_CFG_POOLING_METHOD__SHIFT		0
+static inline uint32_t PPU_OPERATION_MODE_CFG_POOLING_METHOD(uint32_t val)
+{
+	return ((val) << PPU_OPERATION_MODE_CFG_POOLING_METHOD__SHIFT) & PPU_OPERATION_MODE_CFG_POOLING_METHOD__MASK;
+}
+
+#define REG_PPU_POOLING_KERNEL_CFG				0x00006034
+#define PPU_POOLING_KERNEL_CFG_RESERVED_0__MASK			0xff000000
+#define PPU_POOLING_KERNEL_CFG_RESERVED_0__SHIFT		24
+static inline uint32_t PPU_POOLING_KERNEL_CFG_RESERVED_0(uint32_t val)
+{
+	return ((val) << PPU_POOLING_KERNEL_CFG_RESERVED_0__SHIFT) & PPU_POOLING_KERNEL_CFG_RESERVED_0__MASK;
+}
+#define PPU_POOLING_KERNEL_CFG_KERNEL_STRIDE_HEIGHT__MASK	0x00f00000
+#define PPU_POOLING_KERNEL_CFG_KERNEL_STRIDE_HEIGHT__SHIFT	20
+static inline uint32_t PPU_POOLING_KERNEL_CFG_KERNEL_STRIDE_HEIGHT(uint32_t val)
+{
+	return ((val) << PPU_POOLING_KERNEL_CFG_KERNEL_STRIDE_HEIGHT__SHIFT) & PPU_POOLING_KERNEL_CFG_KERNEL_STRIDE_HEIGHT__MASK;
+}
+#define PPU_POOLING_KERNEL_CFG_KERNEL_STRIDE_WIDTH__MASK	0x000f0000
+#define PPU_POOLING_KERNEL_CFG_KERNEL_STRIDE_WIDTH__SHIFT	16
+static inline uint32_t PPU_POOLING_KERNEL_CFG_KERNEL_STRIDE_WIDTH(uint32_t val)
+{
+	return ((val) << PPU_POOLING_KERNEL_CFG_KERNEL_STRIDE_WIDTH__SHIFT) & PPU_POOLING_KERNEL_CFG_KERNEL_STRIDE_WIDTH__MASK;
+}
+#define PPU_POOLING_KERNEL_CFG_RESERVED_1__MASK			0x0000f000
+#define PPU_POOLING_KERNEL_CFG_RESERVED_1__SHIFT		12
+static inline uint32_t PPU_POOLING_KERNEL_CFG_RESERVED_1(uint32_t val)
+{
+	return ((val) << PPU_POOLING_KERNEL_CFG_RESERVED_1__SHIFT) & PPU_POOLING_KERNEL_CFG_RESERVED_1__MASK;
+}
+#define PPU_POOLING_KERNEL_CFG_KERNEL_HEIGHT__MASK		0x00000f00
+#define PPU_POOLING_KERNEL_CFG_KERNEL_HEIGHT__SHIFT		8
+static inline uint32_t PPU_POOLING_KERNEL_CFG_KERNEL_HEIGHT(uint32_t val)
+{
+	return ((val) << PPU_POOLING_KERNEL_CFG_KERNEL_HEIGHT__SHIFT) & PPU_POOLING_KERNEL_CFG_KERNEL_HEIGHT__MASK;
+}
+#define PPU_POOLING_KERNEL_CFG_RESERVED_2__MASK			0x000000f0
+#define PPU_POOLING_KERNEL_CFG_RESERVED_2__SHIFT		4
+static inline uint32_t PPU_POOLING_KERNEL_CFG_RESERVED_2(uint32_t val)
+{
+	return ((val) << PPU_POOLING_KERNEL_CFG_RESERVED_2__SHIFT) & PPU_POOLING_KERNEL_CFG_RESERVED_2__MASK;
+}
+#define PPU_POOLING_KERNEL_CFG_KERNEL_WIDTH__MASK		0x0000000f
+#define PPU_POOLING_KERNEL_CFG_KERNEL_WIDTH__SHIFT		0
+static inline uint32_t PPU_POOLING_KERNEL_CFG_KERNEL_WIDTH(uint32_t val)
+{
+	return ((val) << PPU_POOLING_KERNEL_CFG_KERNEL_WIDTH__SHIFT) & PPU_POOLING_KERNEL_CFG_KERNEL_WIDTH__MASK;
+}
+
+#define REG_PPU_RECIP_KERNEL_WIDTH				0x00006038
+#define PPU_RECIP_KERNEL_WIDTH_RESERVED_0__MASK			0xfffe0000
+#define PPU_RECIP_KERNEL_WIDTH_RESERVED_0__SHIFT		17
+static inline uint32_t PPU_RECIP_KERNEL_WIDTH_RESERVED_0(uint32_t val)
+{
+	return ((val) << PPU_RECIP_KERNEL_WIDTH_RESERVED_0__SHIFT) & PPU_RECIP_KERNEL_WIDTH_RESERVED_0__MASK;
+}
+#define PPU_RECIP_KERNEL_WIDTH_RECIP_KERNEL_WIDTH__MASK		0x0001ffff
+#define PPU_RECIP_KERNEL_WIDTH_RECIP_KERNEL_WIDTH__SHIFT	0
+static inline uint32_t PPU_RECIP_KERNEL_WIDTH_RECIP_KERNEL_WIDTH(uint32_t val)
+{
+	return ((val) << PPU_RECIP_KERNEL_WIDTH_RECIP_KERNEL_WIDTH__SHIFT) & PPU_RECIP_KERNEL_WIDTH_RECIP_KERNEL_WIDTH__MASK;
+}
+
+#define REG_PPU_RECIP_KERNEL_HEIGHT				0x0000603c
+#define PPU_RECIP_KERNEL_HEIGHT_RESERVED_0__MASK		0xfffe0000
+#define PPU_RECIP_KERNEL_HEIGHT_RESERVED_0__SHIFT		17
+static inline uint32_t PPU_RECIP_KERNEL_HEIGHT_RESERVED_0(uint32_t val)
+{
+	return ((val) << PPU_RECIP_KERNEL_HEIGHT_RESERVED_0__SHIFT) & PPU_RECIP_KERNEL_HEIGHT_RESERVED_0__MASK;
+}
+#define PPU_RECIP_KERNEL_HEIGHT_RECIP_KERNEL_HEIGHT__MASK	0x0001ffff
+#define PPU_RECIP_KERNEL_HEIGHT_RECIP_KERNEL_HEIGHT__SHIFT	0
+static inline uint32_t PPU_RECIP_KERNEL_HEIGHT_RECIP_KERNEL_HEIGHT(uint32_t val)
+{
+	return ((val) << PPU_RECIP_KERNEL_HEIGHT_RECIP_KERNEL_HEIGHT__SHIFT) & PPU_RECIP_KERNEL_HEIGHT_RECIP_KERNEL_HEIGHT__MASK;
+}
+
+#define REG_PPU_POOLING_PADDING_CFG				0x00006040
+#define PPU_POOLING_PADDING_CFG_RESERVED_0__MASK		0xffff8000
+#define PPU_POOLING_PADDING_CFG_RESERVED_0__SHIFT		15
+static inline uint32_t PPU_POOLING_PADDING_CFG_RESERVED_0(uint32_t val)
+{
+	return ((val) << PPU_POOLING_PADDING_CFG_RESERVED_0__SHIFT) & PPU_POOLING_PADDING_CFG_RESERVED_0__MASK;
+}
+#define PPU_POOLING_PADDING_CFG_PAD_BOTTOM__MASK		0x00007000
+#define PPU_POOLING_PADDING_CFG_PAD_BOTTOM__SHIFT		12
+static inline uint32_t PPU_POOLING_PADDING_CFG_PAD_BOTTOM(uint32_t val)
+{
+	return ((val) << PPU_POOLING_PADDING_CFG_PAD_BOTTOM__SHIFT) & PPU_POOLING_PADDING_CFG_PAD_BOTTOM__MASK;
+}
+#define PPU_POOLING_PADDING_CFG_RESERVED_1__MASK		0x00000800
+#define PPU_POOLING_PADDING_CFG_RESERVED_1__SHIFT		11
+static inline uint32_t PPU_POOLING_PADDING_CFG_RESERVED_1(uint32_t val)
+{
+	return ((val) << PPU_POOLING_PADDING_CFG_RESERVED_1__SHIFT) & PPU_POOLING_PADDING_CFG_RESERVED_1__MASK;
+}
+#define PPU_POOLING_PADDING_CFG_PAD_RIGHT__MASK			0x00000700
+#define PPU_POOLING_PADDING_CFG_PAD_RIGHT__SHIFT		8
+static inline uint32_t PPU_POOLING_PADDING_CFG_PAD_RIGHT(uint32_t val)
+{
+	return ((val) << PPU_POOLING_PADDING_CFG_PAD_RIGHT__SHIFT) & PPU_POOLING_PADDING_CFG_PAD_RIGHT__MASK;
+}
+#define PPU_POOLING_PADDING_CFG_RESERVED_2__MASK		0x00000080
+#define PPU_POOLING_PADDING_CFG_RESERVED_2__SHIFT		7
+static inline uint32_t PPU_POOLING_PADDING_CFG_RESERVED_2(uint32_t val)
+{
+	return ((val) << PPU_POOLING_PADDING_CFG_RESERVED_2__SHIFT) & PPU_POOLING_PADDING_CFG_RESERVED_2__MASK;
+}
+#define PPU_POOLING_PADDING_CFG_PAD_TOP__MASK			0x00000070
+#define PPU_POOLING_PADDING_CFG_PAD_TOP__SHIFT			4
+static inline uint32_t PPU_POOLING_PADDING_CFG_PAD_TOP(uint32_t val)
+{
+	return ((val) << PPU_POOLING_PADDING_CFG_PAD_TOP__SHIFT) & PPU_POOLING_PADDING_CFG_PAD_TOP__MASK;
+}
+#define PPU_POOLING_PADDING_CFG_RESERVED_3__MASK		0x00000008
+#define PPU_POOLING_PADDING_CFG_RESERVED_3__SHIFT		3
+static inline uint32_t PPU_POOLING_PADDING_CFG_RESERVED_3(uint32_t val)
+{
+	return ((val) << PPU_POOLING_PADDING_CFG_RESERVED_3__SHIFT) & PPU_POOLING_PADDING_CFG_RESERVED_3__MASK;
+}
+#define PPU_POOLING_PADDING_CFG_PAD_LEFT__MASK			0x00000007
+#define PPU_POOLING_PADDING_CFG_PAD_LEFT__SHIFT			0
+static inline uint32_t PPU_POOLING_PADDING_CFG_PAD_LEFT(uint32_t val)
+{
+	return ((val) << PPU_POOLING_PADDING_CFG_PAD_LEFT__SHIFT) & PPU_POOLING_PADDING_CFG_PAD_LEFT__MASK;
+}
+
+#define REG_PPU_PADDING_VALUE_1_CFG				0x00006044
+#define PPU_PADDING_VALUE_1_CFG_PAD_VALUE_0__MASK		0xffffffff
+#define PPU_PADDING_VALUE_1_CFG_PAD_VALUE_0__SHIFT		0
+static inline uint32_t PPU_PADDING_VALUE_1_CFG_PAD_VALUE_0(uint32_t val)
+{
+	return ((val) << PPU_PADDING_VALUE_1_CFG_PAD_VALUE_0__SHIFT) & PPU_PADDING_VALUE_1_CFG_PAD_VALUE_0__MASK;
+}
+
+#define REG_PPU_PADDING_VALUE_2_CFG				0x00006048
+#define PPU_PADDING_VALUE_2_CFG_RESERVED_0__MASK		0xfffffff8
+#define PPU_PADDING_VALUE_2_CFG_RESERVED_0__SHIFT		3
+static inline uint32_t PPU_PADDING_VALUE_2_CFG_RESERVED_0(uint32_t val)
+{
+	return ((val) << PPU_PADDING_VALUE_2_CFG_RESERVED_0__SHIFT) & PPU_PADDING_VALUE_2_CFG_RESERVED_0__MASK;
+}
+#define PPU_PADDING_VALUE_2_CFG_PAD_VALUE_1__MASK		0x00000007
+#define PPU_PADDING_VALUE_2_CFG_PAD_VALUE_1__SHIFT		0
+static inline uint32_t PPU_PADDING_VALUE_2_CFG_PAD_VALUE_1(uint32_t val)
+{
+	return ((val) << PPU_PADDING_VALUE_2_CFG_PAD_VALUE_1__SHIFT) & PPU_PADDING_VALUE_2_CFG_PAD_VALUE_1__MASK;
+}
+
+#define REG_PPU_DST_BASE_ADDR					0x00006070
+#define PPU_DST_BASE_ADDR_DST_BASE_ADDR__MASK			0xfffffff0
+#define PPU_DST_BASE_ADDR_DST_BASE_ADDR__SHIFT			4
+static inline uint32_t PPU_DST_BASE_ADDR_DST_BASE_ADDR(uint32_t val)
+{
+	return ((val) << PPU_DST_BASE_ADDR_DST_BASE_ADDR__SHIFT) & PPU_DST_BASE_ADDR_DST_BASE_ADDR__MASK;
+}
+#define PPU_DST_BASE_ADDR_RESERVED_0__MASK			0x0000000f
+#define PPU_DST_BASE_ADDR_RESERVED_0__SHIFT			0
+static inline uint32_t PPU_DST_BASE_ADDR_RESERVED_0(uint32_t val)
+{
+	return ((val) << PPU_DST_BASE_ADDR_RESERVED_0__SHIFT) & PPU_DST_BASE_ADDR_RESERVED_0__MASK;
+}
+
+#define REG_PPU_DST_SURF_STRIDE					0x0000607c
+#define PPU_DST_SURF_STRIDE_DST_SURF_STRIDE__MASK		0xfffffff0
+#define PPU_DST_SURF_STRIDE_DST_SURF_STRIDE__SHIFT		4
+static inline uint32_t PPU_DST_SURF_STRIDE_DST_SURF_STRIDE(uint32_t val)
+{
+	return ((val) << PPU_DST_SURF_STRIDE_DST_SURF_STRIDE__SHIFT) & PPU_DST_SURF_STRIDE_DST_SURF_STRIDE__MASK;
+}
+#define PPU_DST_SURF_STRIDE_RESERVED_0__MASK			0x0000000f
+#define PPU_DST_SURF_STRIDE_RESERVED_0__SHIFT			0
+static inline uint32_t PPU_DST_SURF_STRIDE_RESERVED_0(uint32_t val)
+{
+	return ((val) << PPU_DST_SURF_STRIDE_RESERVED_0__SHIFT) & PPU_DST_SURF_STRIDE_RESERVED_0__MASK;
+}
+
+#define REG_PPU_DATA_FORMAT					0x00006084
+#define PPU_DATA_FORMAT_INDEX_ADD__MASK				0xfffffff0
+#define PPU_DATA_FORMAT_INDEX_ADD__SHIFT			4
+static inline uint32_t PPU_DATA_FORMAT_INDEX_ADD(uint32_t val)
+{
+	return ((val) << PPU_DATA_FORMAT_INDEX_ADD__SHIFT) & PPU_DATA_FORMAT_INDEX_ADD__MASK;
+}
+#define PPU_DATA_FORMAT_DPU_FLYIN__MASK				0x00000008
+#define PPU_DATA_FORMAT_DPU_FLYIN__SHIFT			3
+static inline uint32_t PPU_DATA_FORMAT_DPU_FLYIN(uint32_t val)
+{
+	return ((val) << PPU_DATA_FORMAT_DPU_FLYIN__SHIFT) & PPU_DATA_FORMAT_DPU_FLYIN__MASK;
+}
+#define PPU_DATA_FORMAT_PROC_PRECISION__MASK			0x00000007
+#define PPU_DATA_FORMAT_PROC_PRECISION__SHIFT			0
+static inline uint32_t PPU_DATA_FORMAT_PROC_PRECISION(uint32_t val)
+{
+	return ((val) << PPU_DATA_FORMAT_PROC_PRECISION__SHIFT) & PPU_DATA_FORMAT_PROC_PRECISION__MASK;
+}
+
+#define REG_PPU_MISC_CTRL					0x000060dc
+#define PPU_MISC_CTRL_SURF_LEN__MASK				0xffff0000
+#define PPU_MISC_CTRL_SURF_LEN__SHIFT				16
+static inline uint32_t PPU_MISC_CTRL_SURF_LEN(uint32_t val)
+{
+	return ((val) << PPU_MISC_CTRL_SURF_LEN__SHIFT) & PPU_MISC_CTRL_SURF_LEN__MASK;
+}
+#define PPU_MISC_CTRL_RESERVED_0__MASK				0x0000fe00
+#define PPU_MISC_CTRL_RESERVED_0__SHIFT				9
+static inline uint32_t PPU_MISC_CTRL_RESERVED_0(uint32_t val)
+{
+	return ((val) << PPU_MISC_CTRL_RESERVED_0__SHIFT) & PPU_MISC_CTRL_RESERVED_0__MASK;
+}
+#define PPU_MISC_CTRL_MC_SURF_OUT__MASK				0x00000100
+#define PPU_MISC_CTRL_MC_SURF_OUT__SHIFT			8
+static inline uint32_t PPU_MISC_CTRL_MC_SURF_OUT(uint32_t val)
+{
+	return ((val) << PPU_MISC_CTRL_MC_SURF_OUT__SHIFT) & PPU_MISC_CTRL_MC_SURF_OUT__MASK;
+}
+#define PPU_MISC_CTRL_NONALIGN__MASK				0x00000080
+#define PPU_MISC_CTRL_NONALIGN__SHIFT				7
+static inline uint32_t PPU_MISC_CTRL_NONALIGN(uint32_t val)
+{
+	return ((val) << PPU_MISC_CTRL_NONALIGN__SHIFT) & PPU_MISC_CTRL_NONALIGN__MASK;
+}
+#define PPU_MISC_CTRL_RESERVED_1__MASK				0x00000070
+#define PPU_MISC_CTRL_RESERVED_1__SHIFT				4
+static inline uint32_t PPU_MISC_CTRL_RESERVED_1(uint32_t val)
+{
+	return ((val) << PPU_MISC_CTRL_RESERVED_1__SHIFT) & PPU_MISC_CTRL_RESERVED_1__MASK;
+}
+#define PPU_MISC_CTRL_BURST_LEN__MASK				0x0000000f
+#define PPU_MISC_CTRL_BURST_LEN__SHIFT				0
+static inline uint32_t PPU_MISC_CTRL_BURST_LEN(uint32_t val)
+{
+	return ((val) << PPU_MISC_CTRL_BURST_LEN__SHIFT) & PPU_MISC_CTRL_BURST_LEN__MASK;
+}
+
+#define REG_PPU_RDMA_RDMA_S_STATUS				0x00007000
+#define PPU_RDMA_RDMA_S_STATUS_RESERVED_0__MASK			0xfffc0000
+#define PPU_RDMA_RDMA_S_STATUS_RESERVED_0__SHIFT		18
+static inline uint32_t PPU_RDMA_RDMA_S_STATUS_RESERVED_0(uint32_t val)
+{
+	return ((val) << PPU_RDMA_RDMA_S_STATUS_RESERVED_0__SHIFT) & PPU_RDMA_RDMA_S_STATUS_RESERVED_0__MASK;
+}
+#define PPU_RDMA_RDMA_S_STATUS_STATUS_1__MASK			0x00030000
+#define PPU_RDMA_RDMA_S_STATUS_STATUS_1__SHIFT			16
+static inline uint32_t PPU_RDMA_RDMA_S_STATUS_STATUS_1(uint32_t val)
+{
+	return ((val) << PPU_RDMA_RDMA_S_STATUS_STATUS_1__SHIFT) & PPU_RDMA_RDMA_S_STATUS_STATUS_1__MASK;
+}
+#define PPU_RDMA_RDMA_S_STATUS_RESERVED_1__MASK			0x0000fffc
+#define PPU_RDMA_RDMA_S_STATUS_RESERVED_1__SHIFT		2
+static inline uint32_t PPU_RDMA_RDMA_S_STATUS_RESERVED_1(uint32_t val)
+{
+	return ((val) << PPU_RDMA_RDMA_S_STATUS_RESERVED_1__SHIFT) & PPU_RDMA_RDMA_S_STATUS_RESERVED_1__MASK;
+}
+#define PPU_RDMA_RDMA_S_STATUS_STATUS_0__MASK			0x00000003
+#define PPU_RDMA_RDMA_S_STATUS_STATUS_0__SHIFT			0
+static inline uint32_t PPU_RDMA_RDMA_S_STATUS_STATUS_0(uint32_t val)
+{
+	return ((val) << PPU_RDMA_RDMA_S_STATUS_STATUS_0__SHIFT) & PPU_RDMA_RDMA_S_STATUS_STATUS_0__MASK;
+}
+
+#define REG_PPU_RDMA_RDMA_S_POINTER				0x00007004
+#define PPU_RDMA_RDMA_S_POINTER_RESERVED_0__MASK		0xfffe0000
+#define PPU_RDMA_RDMA_S_POINTER_RESERVED_0__SHIFT		17
+static inline uint32_t PPU_RDMA_RDMA_S_POINTER_RESERVED_0(uint32_t val)
+{
+	return ((val) << PPU_RDMA_RDMA_S_POINTER_RESERVED_0__SHIFT) & PPU_RDMA_RDMA_S_POINTER_RESERVED_0__MASK;
+}
+#define PPU_RDMA_RDMA_S_POINTER_EXECUTER__MASK			0x00010000
+#define PPU_RDMA_RDMA_S_POINTER_EXECUTER__SHIFT			16
+static inline uint32_t PPU_RDMA_RDMA_S_POINTER_EXECUTER(uint32_t val)
+{
+	return ((val) << PPU_RDMA_RDMA_S_POINTER_EXECUTER__SHIFT) & PPU_RDMA_RDMA_S_POINTER_EXECUTER__MASK;
+}
+#define PPU_RDMA_RDMA_S_POINTER_RESERVED_1__MASK		0x0000ffc0
+#define PPU_RDMA_RDMA_S_POINTER_RESERVED_1__SHIFT		6
+static inline uint32_t PPU_RDMA_RDMA_S_POINTER_RESERVED_1(uint32_t val)
+{
+	return ((val) << PPU_RDMA_RDMA_S_POINTER_RESERVED_1__SHIFT) & PPU_RDMA_RDMA_S_POINTER_RESERVED_1__MASK;
+}
+#define PPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__MASK		0x00000020
+#define PPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__SHIFT	5
+static inline uint32_t PPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR(uint32_t val)
+{
+	return ((val) << PPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__SHIFT) & PPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__MASK;
+}
+#define PPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__MASK		0x00000010
+#define PPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__SHIFT		4
+static inline uint32_t PPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR(uint32_t val)
+{
+	return ((val) << PPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__SHIFT) & PPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__MASK;
+}
+#define PPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__MASK		0x00000008
+#define PPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__SHIFT		3
+static inline uint32_t PPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE(uint32_t val)
+{
+	return ((val) << PPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__SHIFT) & PPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__MASK;
+}
+#define PPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__MASK		0x00000004
+#define PPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__SHIFT		2
+static inline uint32_t PPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN(uint32_t val)
+{
+	return ((val) << PPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__SHIFT) & PPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__MASK;
+}
+#define PPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__MASK		0x00000002
+#define PPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__SHIFT		1
+static inline uint32_t PPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN(uint32_t val)
+{
+	return ((val) << PPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__SHIFT) & PPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__MASK;
+}
+#define PPU_RDMA_RDMA_S_POINTER_POINTER__MASK			0x00000001
+#define PPU_RDMA_RDMA_S_POINTER_POINTER__SHIFT			0
+static inline uint32_t PPU_RDMA_RDMA_S_POINTER_POINTER(uint32_t val)
+{
+	return ((val) << PPU_RDMA_RDMA_S_POINTER_POINTER__SHIFT) & PPU_RDMA_RDMA_S_POINTER_POINTER__MASK;
+}
+
+#define REG_PPU_RDMA_RDMA_OPERATION_ENABLE			0x00007008
+#define PPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__MASK		0xfffffffe
+#define PPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__SHIFT	1
+static inline uint32_t PPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0(uint32_t val)
+{
+	return ((val) << PPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__SHIFT) & PPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__MASK;
+}
+#define PPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__MASK		0x00000001
+#define PPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__SHIFT		0
+static inline uint32_t PPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN(uint32_t val)
+{
+	return ((val) << PPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__SHIFT) & PPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__MASK;
+}
+
+#define REG_PPU_RDMA_RDMA_CUBE_IN_WIDTH				0x0000700c
+#define PPU_RDMA_RDMA_CUBE_IN_WIDTH_RESERVED_0__MASK		0xffffe000
+#define PPU_RDMA_RDMA_CUBE_IN_WIDTH_RESERVED_0__SHIFT		13
+static inline uint32_t PPU_RDMA_RDMA_CUBE_IN_WIDTH_RESERVED_0(uint32_t val)
+{
+	return ((val) << PPU_RDMA_RDMA_CUBE_IN_WIDTH_RESERVED_0__SHIFT) & PPU_RDMA_RDMA_CUBE_IN_WIDTH_RESERVED_0__MASK;
+}
+#define PPU_RDMA_RDMA_CUBE_IN_WIDTH_CUBE_IN_WIDTH__MASK		0x00001fff
+#define PPU_RDMA_RDMA_CUBE_IN_WIDTH_CUBE_IN_WIDTH__SHIFT	0
+static inline uint32_t PPU_RDMA_RDMA_CUBE_IN_WIDTH_CUBE_IN_WIDTH(uint32_t val)
+{
+	return ((val) << PPU_RDMA_RDMA_CUBE_IN_WIDTH_CUBE_IN_WIDTH__SHIFT) & PPU_RDMA_RDMA_CUBE_IN_WIDTH_CUBE_IN_WIDTH__MASK;
+}
+
+#define REG_PPU_RDMA_RDMA_CUBE_IN_HEIGHT			0x00007010
+#define PPU_RDMA_RDMA_CUBE_IN_HEIGHT_RESERVED_0__MASK		0xffffe000
+#define PPU_RDMA_RDMA_CUBE_IN_HEIGHT_RESERVED_0__SHIFT		13
+static inline uint32_t PPU_RDMA_RDMA_CUBE_IN_HEIGHT_RESERVED_0(uint32_t val)
+{
+	return ((val) << PPU_RDMA_RDMA_CUBE_IN_HEIGHT_RESERVED_0__SHIFT) & PPU_RDMA_RDMA_CUBE_IN_HEIGHT_RESERVED_0__MASK;
+}
+#define PPU_RDMA_RDMA_CUBE_IN_HEIGHT_CUBE_IN_HEIGHT__MASK	0x00001fff
+#define PPU_RDMA_RDMA_CUBE_IN_HEIGHT_CUBE_IN_HEIGHT__SHIFT	0
+static inline uint32_t PPU_RDMA_RDMA_CUBE_IN_HEIGHT_CUBE_IN_HEIGHT(uint32_t val)
+{
+	return ((val) << PPU_RDMA_RDMA_CUBE_IN_HEIGHT_CUBE_IN_HEIGHT__SHIFT) & PPU_RDMA_RDMA_CUBE_IN_HEIGHT_CUBE_IN_HEIGHT__MASK;
+}
+
+#define REG_PPU_RDMA_RDMA_CUBE_IN_CHANNEL			0x00007014
+#define PPU_RDMA_RDMA_CUBE_IN_CHANNEL_RESERVED_0__MASK		0xffffe000
+#define PPU_RDMA_RDMA_CUBE_IN_CHANNEL_RESERVED_0__SHIFT		13
+static inline uint32_t PPU_RDMA_RDMA_CUBE_IN_CHANNEL_RESERVED_0(uint32_t val)
+{
+	return ((val) << PPU_RDMA_RDMA_CUBE_IN_CHANNEL_RESERVED_0__SHIFT) & PPU_RDMA_RDMA_CUBE_IN_CHANNEL_RESERVED_0__MASK;
+}
+#define PPU_RDMA_RDMA_CUBE_IN_CHANNEL_CUBE_IN_CHANNEL__MASK	0x00001fff
+#define PPU_RDMA_RDMA_CUBE_IN_CHANNEL_CUBE_IN_CHANNEL__SHIFT	0
+static inline uint32_t PPU_RDMA_RDMA_CUBE_IN_CHANNEL_CUBE_IN_CHANNEL(uint32_t val)
+{
+	return ((val) << PPU_RDMA_RDMA_CUBE_IN_CHANNEL_CUBE_IN_CHANNEL__SHIFT) & PPU_RDMA_RDMA_CUBE_IN_CHANNEL_CUBE_IN_CHANNEL__MASK;
+}
+
+#define REG_PPU_RDMA_RDMA_SRC_BASE_ADDR				0x0000701c
+#define PPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__MASK		0xffffffff
+#define PPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__SHIFT	0
+static inline uint32_t PPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR(uint32_t val)
+{
+	return ((val) << PPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__SHIFT) & PPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__MASK;
+}
+
+#define REG_PPU_RDMA_RDMA_SRC_LINE_STRIDE			0x00007024
+#define PPU_RDMA_RDMA_SRC_LINE_STRIDE_SRC_LINE_STRIDE__MASK	0xfffffff0
+#define PPU_RDMA_RDMA_SRC_LINE_STRIDE_SRC_LINE_STRIDE__SHIFT	4
+static inline uint32_t PPU_RDMA_RDMA_SRC_LINE_STRIDE_SRC_LINE_STRIDE(uint32_t val)
+{
+	return ((val) << PPU_RDMA_RDMA_SRC_LINE_STRIDE_SRC_LINE_STRIDE__SHIFT) & PPU_RDMA_RDMA_SRC_LINE_STRIDE_SRC_LINE_STRIDE__MASK;
+}
+#define PPU_RDMA_RDMA_SRC_LINE_STRIDE_RESERVED_0__MASK		0x0000000f
+#define PPU_RDMA_RDMA_SRC_LINE_STRIDE_RESERVED_0__SHIFT		0
+static inline uint32_t PPU_RDMA_RDMA_SRC_LINE_STRIDE_RESERVED_0(uint32_t val)
+{
+	return ((val) << PPU_RDMA_RDMA_SRC_LINE_STRIDE_RESERVED_0__SHIFT) & PPU_RDMA_RDMA_SRC_LINE_STRIDE_RESERVED_0__MASK;
+}
+
+#define REG_PPU_RDMA_RDMA_SRC_SURF_STRIDE			0x00007028
+#define PPU_RDMA_RDMA_SRC_SURF_STRIDE_SRC_SURF_STRIDE__MASK	0xfffffff0
+#define PPU_RDMA_RDMA_SRC_SURF_STRIDE_SRC_SURF_STRIDE__SHIFT	4
+static inline uint32_t PPU_RDMA_RDMA_SRC_SURF_STRIDE_SRC_SURF_STRIDE(uint32_t val)
+{
+	return ((val) << PPU_RDMA_RDMA_SRC_SURF_STRIDE_SRC_SURF_STRIDE__SHIFT) & PPU_RDMA_RDMA_SRC_SURF_STRIDE_SRC_SURF_STRIDE__MASK;
+}
+#define PPU_RDMA_RDMA_SRC_SURF_STRIDE_RESERVED_0__MASK		0x0000000f
+#define PPU_RDMA_RDMA_SRC_SURF_STRIDE_RESERVED_0__SHIFT		0
+static inline uint32_t PPU_RDMA_RDMA_SRC_SURF_STRIDE_RESERVED_0(uint32_t val)
+{
+	return ((val) << PPU_RDMA_RDMA_SRC_SURF_STRIDE_RESERVED_0__SHIFT) & PPU_RDMA_RDMA_SRC_SURF_STRIDE_RESERVED_0__MASK;
+}
+
+#define REG_PPU_RDMA_RDMA_DATA_FORMAT				0x00007030
+#define PPU_RDMA_RDMA_DATA_FORMAT_RESERVED_0__MASK		0xfffffffc
+#define PPU_RDMA_RDMA_DATA_FORMAT_RESERVED_0__SHIFT		2
+static inline uint32_t PPU_RDMA_RDMA_DATA_FORMAT_RESERVED_0(uint32_t val)
+{
+	return ((val) << PPU_RDMA_RDMA_DATA_FORMAT_RESERVED_0__SHIFT) & PPU_RDMA_RDMA_DATA_FORMAT_RESERVED_0__MASK;
+}
+#define PPU_RDMA_RDMA_DATA_FORMAT_IN_PRECISION__MASK		0x00000003
+#define PPU_RDMA_RDMA_DATA_FORMAT_IN_PRECISION__SHIFT		0
+static inline uint32_t PPU_RDMA_RDMA_DATA_FORMAT_IN_PRECISION(uint32_t val)
+{
+	return ((val) << PPU_RDMA_RDMA_DATA_FORMAT_IN_PRECISION__SHIFT) & PPU_RDMA_RDMA_DATA_FORMAT_IN_PRECISION__MASK;
+}
+
+#define REG_DDMA_CFG_OUTSTANDING				0x00008000
+#define DDMA_CFG_OUTSTANDING_RESERVED_0__MASK			0xffff0000
+#define DDMA_CFG_OUTSTANDING_RESERVED_0__SHIFT			16
+static inline uint32_t DDMA_CFG_OUTSTANDING_RESERVED_0(uint32_t val)
+{
+	return ((val) << DDMA_CFG_OUTSTANDING_RESERVED_0__SHIFT) & DDMA_CFG_OUTSTANDING_RESERVED_0__MASK;
+}
+#define DDMA_CFG_OUTSTANDING_WR_OS_CNT__MASK			0x0000ff00
+#define DDMA_CFG_OUTSTANDING_WR_OS_CNT__SHIFT			8
+static inline uint32_t DDMA_CFG_OUTSTANDING_WR_OS_CNT(uint32_t val)
+{
+	return ((val) << DDMA_CFG_OUTSTANDING_WR_OS_CNT__SHIFT) & DDMA_CFG_OUTSTANDING_WR_OS_CNT__MASK;
+}
+#define DDMA_CFG_OUTSTANDING_RD_OS_CNT__MASK			0x000000ff
+#define DDMA_CFG_OUTSTANDING_RD_OS_CNT__SHIFT			0
+static inline uint32_t DDMA_CFG_OUTSTANDING_RD_OS_CNT(uint32_t val)
+{
+	return ((val) << DDMA_CFG_OUTSTANDING_RD_OS_CNT__SHIFT) & DDMA_CFG_OUTSTANDING_RD_OS_CNT__MASK;
+}
+
+#define REG_DDMA_RD_WEIGHT_0					0x00008004
+#define DDMA_RD_WEIGHT_0_RD_WEIGHT_PDP__MASK			0xff000000
+#define DDMA_RD_WEIGHT_0_RD_WEIGHT_PDP__SHIFT			24
+static inline uint32_t DDMA_RD_WEIGHT_0_RD_WEIGHT_PDP(uint32_t val)
+{
+	return ((val) << DDMA_RD_WEIGHT_0_RD_WEIGHT_PDP__SHIFT) & DDMA_RD_WEIGHT_0_RD_WEIGHT_PDP__MASK;
+}
+#define DDMA_RD_WEIGHT_0_RD_WEIGHT_DPU__MASK			0x00ff0000
+#define DDMA_RD_WEIGHT_0_RD_WEIGHT_DPU__SHIFT			16
+static inline uint32_t DDMA_RD_WEIGHT_0_RD_WEIGHT_DPU(uint32_t val)
+{
+	return ((val) << DDMA_RD_WEIGHT_0_RD_WEIGHT_DPU__SHIFT) & DDMA_RD_WEIGHT_0_RD_WEIGHT_DPU__MASK;
+}
+#define DDMA_RD_WEIGHT_0_RD_WEIGHT_KERNEL__MASK			0x0000ff00
+#define DDMA_RD_WEIGHT_0_RD_WEIGHT_KERNEL__SHIFT		8
+static inline uint32_t DDMA_RD_WEIGHT_0_RD_WEIGHT_KERNEL(uint32_t val)
+{
+	return ((val) << DDMA_RD_WEIGHT_0_RD_WEIGHT_KERNEL__SHIFT) & DDMA_RD_WEIGHT_0_RD_WEIGHT_KERNEL__MASK;
+}
+#define DDMA_RD_WEIGHT_0_RD_WEIGHT_FEATURE__MASK		0x000000ff
+#define DDMA_RD_WEIGHT_0_RD_WEIGHT_FEATURE__SHIFT		0
+static inline uint32_t DDMA_RD_WEIGHT_0_RD_WEIGHT_FEATURE(uint32_t val)
+{
+	return ((val) << DDMA_RD_WEIGHT_0_RD_WEIGHT_FEATURE__SHIFT) & DDMA_RD_WEIGHT_0_RD_WEIGHT_FEATURE__MASK;
+}
+
+#define REG_DDMA_WR_WEIGHT_0					0x00008008
+#define DDMA_WR_WEIGHT_0_RESERVED_0__MASK			0xffff0000
+#define DDMA_WR_WEIGHT_0_RESERVED_0__SHIFT			16
+static inline uint32_t DDMA_WR_WEIGHT_0_RESERVED_0(uint32_t val)
+{
+	return ((val) << DDMA_WR_WEIGHT_0_RESERVED_0__SHIFT) & DDMA_WR_WEIGHT_0_RESERVED_0__MASK;
+}
+#define DDMA_WR_WEIGHT_0_WR_WEIGHT_PDP__MASK			0x0000ff00
+#define DDMA_WR_WEIGHT_0_WR_WEIGHT_PDP__SHIFT			8
+static inline uint32_t DDMA_WR_WEIGHT_0_WR_WEIGHT_PDP(uint32_t val)
+{
+	return ((val) << DDMA_WR_WEIGHT_0_WR_WEIGHT_PDP__SHIFT) & DDMA_WR_WEIGHT_0_WR_WEIGHT_PDP__MASK;
+}
+#define DDMA_WR_WEIGHT_0_WR_WEIGHT_DPU__MASK			0x000000ff
+#define DDMA_WR_WEIGHT_0_WR_WEIGHT_DPU__SHIFT			0
+static inline uint32_t DDMA_WR_WEIGHT_0_WR_WEIGHT_DPU(uint32_t val)
+{
+	return ((val) << DDMA_WR_WEIGHT_0_WR_WEIGHT_DPU__SHIFT) & DDMA_WR_WEIGHT_0_WR_WEIGHT_DPU__MASK;
+}
+
+#define REG_DDMA_CFG_ID_ERROR					0x0000800c
+#define DDMA_CFG_ID_ERROR_RESERVED_0__MASK			0xfffffc00
+#define DDMA_CFG_ID_ERROR_RESERVED_0__SHIFT			10
+static inline uint32_t DDMA_CFG_ID_ERROR_RESERVED_0(uint32_t val)
+{
+	return ((val) << DDMA_CFG_ID_ERROR_RESERVED_0__SHIFT) & DDMA_CFG_ID_ERROR_RESERVED_0__MASK;
+}
+#define DDMA_CFG_ID_ERROR_WR_RESP_ID__MASK			0x000003c0
+#define DDMA_CFG_ID_ERROR_WR_RESP_ID__SHIFT			6
+static inline uint32_t DDMA_CFG_ID_ERROR_WR_RESP_ID(uint32_t val)
+{
+	return ((val) << DDMA_CFG_ID_ERROR_WR_RESP_ID__SHIFT) & DDMA_CFG_ID_ERROR_WR_RESP_ID__MASK;
+}
+#define DDMA_CFG_ID_ERROR_RESERVED_1__MASK			0x00000020
+#define DDMA_CFG_ID_ERROR_RESERVED_1__SHIFT			5
+static inline uint32_t DDMA_CFG_ID_ERROR_RESERVED_1(uint32_t val)
+{
+	return ((val) << DDMA_CFG_ID_ERROR_RESERVED_1__SHIFT) & DDMA_CFG_ID_ERROR_RESERVED_1__MASK;
+}
+#define DDMA_CFG_ID_ERROR_RD_RESP_ID__MASK			0x0000001f
+#define DDMA_CFG_ID_ERROR_RD_RESP_ID__SHIFT			0
+static inline uint32_t DDMA_CFG_ID_ERROR_RD_RESP_ID(uint32_t val)
+{
+	return ((val) << DDMA_CFG_ID_ERROR_RD_RESP_ID__SHIFT) & DDMA_CFG_ID_ERROR_RD_RESP_ID__MASK;
+}
+
+#define REG_DDMA_RD_WEIGHT_1					0x00008010
+#define DDMA_RD_WEIGHT_1_RESERVED_0__MASK			0xffffff00
+#define DDMA_RD_WEIGHT_1_RESERVED_0__SHIFT			8
+static inline uint32_t DDMA_RD_WEIGHT_1_RESERVED_0(uint32_t val)
+{
+	return ((val) << DDMA_RD_WEIGHT_1_RESERVED_0__SHIFT) & DDMA_RD_WEIGHT_1_RESERVED_0__MASK;
+}
+#define DDMA_RD_WEIGHT_1_RD_WEIGHT_PC__MASK			0x000000ff
+#define DDMA_RD_WEIGHT_1_RD_WEIGHT_PC__SHIFT			0
+static inline uint32_t DDMA_RD_WEIGHT_1_RD_WEIGHT_PC(uint32_t val)
+{
+	return ((val) << DDMA_RD_WEIGHT_1_RD_WEIGHT_PC__SHIFT) & DDMA_RD_WEIGHT_1_RD_WEIGHT_PC__MASK;
+}
+
+#define REG_DDMA_CFG_DMA_FIFO_CLR				0x00008014
+#define DDMA_CFG_DMA_FIFO_CLR_RESERVED_0__MASK			0xfffffffe
+#define DDMA_CFG_DMA_FIFO_CLR_RESERVED_0__SHIFT			1
+static inline uint32_t DDMA_CFG_DMA_FIFO_CLR_RESERVED_0(uint32_t val)
+{
+	return ((val) << DDMA_CFG_DMA_FIFO_CLR_RESERVED_0__SHIFT) & DDMA_CFG_DMA_FIFO_CLR_RESERVED_0__MASK;
+}
+#define DDMA_CFG_DMA_FIFO_CLR_DMA_FIFO_CLR__MASK		0x00000001
+#define DDMA_CFG_DMA_FIFO_CLR_DMA_FIFO_CLR__SHIFT		0
+static inline uint32_t DDMA_CFG_DMA_FIFO_CLR_DMA_FIFO_CLR(uint32_t val)
+{
+	return ((val) << DDMA_CFG_DMA_FIFO_CLR_DMA_FIFO_CLR__SHIFT) & DDMA_CFG_DMA_FIFO_CLR_DMA_FIFO_CLR__MASK;
+}
+
+#define REG_DDMA_CFG_DMA_ARB					0x00008018
+#define DDMA_CFG_DMA_ARB_RESERVED_0__MASK			0xfffffc00
+#define DDMA_CFG_DMA_ARB_RESERVED_0__SHIFT			10
+static inline uint32_t DDMA_CFG_DMA_ARB_RESERVED_0(uint32_t val)
+{
+	return ((val) << DDMA_CFG_DMA_ARB_RESERVED_0__SHIFT) & DDMA_CFG_DMA_ARB_RESERVED_0__MASK;
+}
+#define DDMA_CFG_DMA_ARB_WR_ARBIT_MODEL__MASK			0x00000200
+#define DDMA_CFG_DMA_ARB_WR_ARBIT_MODEL__SHIFT			9
+static inline uint32_t DDMA_CFG_DMA_ARB_WR_ARBIT_MODEL(uint32_t val)
+{
+	return ((val) << DDMA_CFG_DMA_ARB_WR_ARBIT_MODEL__SHIFT) & DDMA_CFG_DMA_ARB_WR_ARBIT_MODEL__MASK;
+}
+#define DDMA_CFG_DMA_ARB_RD_ARBIT_MODEL__MASK			0x00000100
+#define DDMA_CFG_DMA_ARB_RD_ARBIT_MODEL__SHIFT			8
+static inline uint32_t DDMA_CFG_DMA_ARB_RD_ARBIT_MODEL(uint32_t val)
+{
+	return ((val) << DDMA_CFG_DMA_ARB_RD_ARBIT_MODEL__SHIFT) & DDMA_CFG_DMA_ARB_RD_ARBIT_MODEL__MASK;
+}
+#define DDMA_CFG_DMA_ARB_RESERVED_1__MASK			0x00000080
+#define DDMA_CFG_DMA_ARB_RESERVED_1__SHIFT			7
+static inline uint32_t DDMA_CFG_DMA_ARB_RESERVED_1(uint32_t val)
+{
+	return ((val) << DDMA_CFG_DMA_ARB_RESERVED_1__SHIFT) & DDMA_CFG_DMA_ARB_RESERVED_1__MASK;
+}
+#define DDMA_CFG_DMA_ARB_WR_FIX_ARB__MASK			0x00000070
+#define DDMA_CFG_DMA_ARB_WR_FIX_ARB__SHIFT			4
+static inline uint32_t DDMA_CFG_DMA_ARB_WR_FIX_ARB(uint32_t val)
+{
+	return ((val) << DDMA_CFG_DMA_ARB_WR_FIX_ARB__SHIFT) & DDMA_CFG_DMA_ARB_WR_FIX_ARB__MASK;
+}
+#define DDMA_CFG_DMA_ARB_RESERVED_2__MASK			0x00000008
+#define DDMA_CFG_DMA_ARB_RESERVED_2__SHIFT			3
+static inline uint32_t DDMA_CFG_DMA_ARB_RESERVED_2(uint32_t val)
+{
+	return ((val) << DDMA_CFG_DMA_ARB_RESERVED_2__SHIFT) & DDMA_CFG_DMA_ARB_RESERVED_2__MASK;
+}
+#define DDMA_CFG_DMA_ARB_RD_FIX_ARB__MASK			0x00000007
+#define DDMA_CFG_DMA_ARB_RD_FIX_ARB__SHIFT			0
+static inline uint32_t DDMA_CFG_DMA_ARB_RD_FIX_ARB(uint32_t val)
+{
+	return ((val) << DDMA_CFG_DMA_ARB_RD_FIX_ARB__SHIFT) & DDMA_CFG_DMA_ARB_RD_FIX_ARB__MASK;
+}
+
+#define REG_DDMA_CFG_DMA_RD_QOS					0x00008020
+#define DDMA_CFG_DMA_RD_QOS_RESERVED_0__MASK			0xfffffc00
+#define DDMA_CFG_DMA_RD_QOS_RESERVED_0__SHIFT			10
+static inline uint32_t DDMA_CFG_DMA_RD_QOS_RESERVED_0(uint32_t val)
+{
+	return ((val) << DDMA_CFG_DMA_RD_QOS_RESERVED_0__SHIFT) & DDMA_CFG_DMA_RD_QOS_RESERVED_0__MASK;
+}
+#define DDMA_CFG_DMA_RD_QOS_RD_PC_QOS__MASK			0x00000300
+#define DDMA_CFG_DMA_RD_QOS_RD_PC_QOS__SHIFT			8
+static inline uint32_t DDMA_CFG_DMA_RD_QOS_RD_PC_QOS(uint32_t val)
+{
+	return ((val) << DDMA_CFG_DMA_RD_QOS_RD_PC_QOS__SHIFT) & DDMA_CFG_DMA_RD_QOS_RD_PC_QOS__MASK;
+}
+#define DDMA_CFG_DMA_RD_QOS_RD_PPU_QOS__MASK			0x000000c0
+#define DDMA_CFG_DMA_RD_QOS_RD_PPU_QOS__SHIFT			6
+static inline uint32_t DDMA_CFG_DMA_RD_QOS_RD_PPU_QOS(uint32_t val)
+{
+	return ((val) << DDMA_CFG_DMA_RD_QOS_RD_PPU_QOS__SHIFT) & DDMA_CFG_DMA_RD_QOS_RD_PPU_QOS__MASK;
+}
+#define DDMA_CFG_DMA_RD_QOS_RD_DPU_QOS__MASK			0x00000030
+#define DDMA_CFG_DMA_RD_QOS_RD_DPU_QOS__SHIFT			4
+static inline uint32_t DDMA_CFG_DMA_RD_QOS_RD_DPU_QOS(uint32_t val)
+{
+	return ((val) << DDMA_CFG_DMA_RD_QOS_RD_DPU_QOS__SHIFT) & DDMA_CFG_DMA_RD_QOS_RD_DPU_QOS__MASK;
+}
+#define DDMA_CFG_DMA_RD_QOS_RD_KERNEL_QOS__MASK			0x0000000c
+#define DDMA_CFG_DMA_RD_QOS_RD_KERNEL_QOS__SHIFT		2
+static inline uint32_t DDMA_CFG_DMA_RD_QOS_RD_KERNEL_QOS(uint32_t val)
+{
+	return ((val) << DDMA_CFG_DMA_RD_QOS_RD_KERNEL_QOS__SHIFT) & DDMA_CFG_DMA_RD_QOS_RD_KERNEL_QOS__MASK;
+}
+#define DDMA_CFG_DMA_RD_QOS_RD_FEATURE_QOS__MASK		0x00000003
+#define DDMA_CFG_DMA_RD_QOS_RD_FEATURE_QOS__SHIFT		0
+static inline uint32_t DDMA_CFG_DMA_RD_QOS_RD_FEATURE_QOS(uint32_t val)
+{
+	return ((val) << DDMA_CFG_DMA_RD_QOS_RD_FEATURE_QOS__SHIFT) & DDMA_CFG_DMA_RD_QOS_RD_FEATURE_QOS__MASK;
+}
+
+#define REG_DDMA_CFG_DMA_RD_CFG					0x00008024
+#define DDMA_CFG_DMA_RD_CFG_RESERVED_0__MASK			0xffffe000
+#define DDMA_CFG_DMA_RD_CFG_RESERVED_0__SHIFT			13
+static inline uint32_t DDMA_CFG_DMA_RD_CFG_RESERVED_0(uint32_t val)
+{
+	return ((val) << DDMA_CFG_DMA_RD_CFG_RESERVED_0__SHIFT) & DDMA_CFG_DMA_RD_CFG_RESERVED_0__MASK;
+}
+#define DDMA_CFG_DMA_RD_CFG_RD_ARLOCK__MASK			0x00001000
+#define DDMA_CFG_DMA_RD_CFG_RD_ARLOCK__SHIFT			12
+static inline uint32_t DDMA_CFG_DMA_RD_CFG_RD_ARLOCK(uint32_t val)
+{
+	return ((val) << DDMA_CFG_DMA_RD_CFG_RD_ARLOCK__SHIFT) & DDMA_CFG_DMA_RD_CFG_RD_ARLOCK__MASK;
+}
+#define DDMA_CFG_DMA_RD_CFG_RD_ARCACHE__MASK			0x00000f00
+#define DDMA_CFG_DMA_RD_CFG_RD_ARCACHE__SHIFT			8
+static inline uint32_t DDMA_CFG_DMA_RD_CFG_RD_ARCACHE(uint32_t val)
+{
+	return ((val) << DDMA_CFG_DMA_RD_CFG_RD_ARCACHE__SHIFT) & DDMA_CFG_DMA_RD_CFG_RD_ARCACHE__MASK;
+}
+#define DDMA_CFG_DMA_RD_CFG_RD_ARPROT__MASK			0x000000e0
+#define DDMA_CFG_DMA_RD_CFG_RD_ARPROT__SHIFT			5
+static inline uint32_t DDMA_CFG_DMA_RD_CFG_RD_ARPROT(uint32_t val)
+{
+	return ((val) << DDMA_CFG_DMA_RD_CFG_RD_ARPROT__SHIFT) & DDMA_CFG_DMA_RD_CFG_RD_ARPROT__MASK;
+}
+#define DDMA_CFG_DMA_RD_CFG_RD_ARBURST__MASK			0x00000018
+#define DDMA_CFG_DMA_RD_CFG_RD_ARBURST__SHIFT			3
+static inline uint32_t DDMA_CFG_DMA_RD_CFG_RD_ARBURST(uint32_t val)
+{
+	return ((val) << DDMA_CFG_DMA_RD_CFG_RD_ARBURST__SHIFT) & DDMA_CFG_DMA_RD_CFG_RD_ARBURST__MASK;
+}
+#define DDMA_CFG_DMA_RD_CFG_RD_ARSIZE__MASK			0x00000007
+#define DDMA_CFG_DMA_RD_CFG_RD_ARSIZE__SHIFT			0
+static inline uint32_t DDMA_CFG_DMA_RD_CFG_RD_ARSIZE(uint32_t val)
+{
+	return ((val) << DDMA_CFG_DMA_RD_CFG_RD_ARSIZE__SHIFT) & DDMA_CFG_DMA_RD_CFG_RD_ARSIZE__MASK;
+}
+
+#define REG_DDMA_CFG_DMA_WR_CFG					0x00008028
+#define DDMA_CFG_DMA_WR_CFG_RESERVED_0__MASK			0xffffe000
+#define DDMA_CFG_DMA_WR_CFG_RESERVED_0__SHIFT			13
+static inline uint32_t DDMA_CFG_DMA_WR_CFG_RESERVED_0(uint32_t val)
+{
+	return ((val) << DDMA_CFG_DMA_WR_CFG_RESERVED_0__SHIFT) & DDMA_CFG_DMA_WR_CFG_RESERVED_0__MASK;
+}
+#define DDMA_CFG_DMA_WR_CFG_WR_AWLOCK__MASK			0x00001000
+#define DDMA_CFG_DMA_WR_CFG_WR_AWLOCK__SHIFT			12
+static inline uint32_t DDMA_CFG_DMA_WR_CFG_WR_AWLOCK(uint32_t val)
+{
+	return ((val) << DDMA_CFG_DMA_WR_CFG_WR_AWLOCK__SHIFT) & DDMA_CFG_DMA_WR_CFG_WR_AWLOCK__MASK;
+}
+#define DDMA_CFG_DMA_WR_CFG_WR_AWCACHE__MASK			0x00000f00
+#define DDMA_CFG_DMA_WR_CFG_WR_AWCACHE__SHIFT			8
+static inline uint32_t DDMA_CFG_DMA_WR_CFG_WR_AWCACHE(uint32_t val)
+{
+	return ((val) << DDMA_CFG_DMA_WR_CFG_WR_AWCACHE__SHIFT) & DDMA_CFG_DMA_WR_CFG_WR_AWCACHE__MASK;
+}
+#define DDMA_CFG_DMA_WR_CFG_WR_AWPROT__MASK			0x000000e0
+#define DDMA_CFG_DMA_WR_CFG_WR_AWPROT__SHIFT			5
+static inline uint32_t DDMA_CFG_DMA_WR_CFG_WR_AWPROT(uint32_t val)
+{
+	return ((val) << DDMA_CFG_DMA_WR_CFG_WR_AWPROT__SHIFT) & DDMA_CFG_DMA_WR_CFG_WR_AWPROT__MASK;
+}
+#define DDMA_CFG_DMA_WR_CFG_WR_AWBURST__MASK			0x00000018
+#define DDMA_CFG_DMA_WR_CFG_WR_AWBURST__SHIFT			3
+static inline uint32_t DDMA_CFG_DMA_WR_CFG_WR_AWBURST(uint32_t val)
+{
+	return ((val) << DDMA_CFG_DMA_WR_CFG_WR_AWBURST__SHIFT) & DDMA_CFG_DMA_WR_CFG_WR_AWBURST__MASK;
+}
+#define DDMA_CFG_DMA_WR_CFG_WR_AWSIZE__MASK			0x00000007
+#define DDMA_CFG_DMA_WR_CFG_WR_AWSIZE__SHIFT			0
+static inline uint32_t DDMA_CFG_DMA_WR_CFG_WR_AWSIZE(uint32_t val)
+{
+	return ((val) << DDMA_CFG_DMA_WR_CFG_WR_AWSIZE__SHIFT) & DDMA_CFG_DMA_WR_CFG_WR_AWSIZE__MASK;
+}
+
+#define REG_DDMA_CFG_DMA_WSTRB					0x0000802c
+#define DDMA_CFG_DMA_WSTRB_WR_WSTRB__MASK			0xffffffff
+#define DDMA_CFG_DMA_WSTRB_WR_WSTRB__SHIFT			0
+static inline uint32_t DDMA_CFG_DMA_WSTRB_WR_WSTRB(uint32_t val)
+{
+	return ((val) << DDMA_CFG_DMA_WSTRB_WR_WSTRB__SHIFT) & DDMA_CFG_DMA_WSTRB_WR_WSTRB__MASK;
+}
+
+#define REG_DDMA_CFG_STATUS					0x00008030
+#define DDMA_CFG_STATUS_RESERVED_0__MASK			0xfffffe00
+#define DDMA_CFG_STATUS_RESERVED_0__SHIFT			9
+static inline uint32_t DDMA_CFG_STATUS_RESERVED_0(uint32_t val)
+{
+	return ((val) << DDMA_CFG_STATUS_RESERVED_0__SHIFT) & DDMA_CFG_STATUS_RESERVED_0__MASK;
+}
+#define DDMA_CFG_STATUS_IDEL__MASK				0x00000100
+#define DDMA_CFG_STATUS_IDEL__SHIFT				8
+static inline uint32_t DDMA_CFG_STATUS_IDEL(uint32_t val)
+{
+	return ((val) << DDMA_CFG_STATUS_IDEL__SHIFT) & DDMA_CFG_STATUS_IDEL__MASK;
+}
+#define DDMA_CFG_STATUS_RESERVED_1__MASK			0x000000ff
+#define DDMA_CFG_STATUS_RESERVED_1__SHIFT			0
+static inline uint32_t DDMA_CFG_STATUS_RESERVED_1(uint32_t val)
+{
+	return ((val) << DDMA_CFG_STATUS_RESERVED_1__SHIFT) & DDMA_CFG_STATUS_RESERVED_1__MASK;
+}
+
+#define REG_SDMA_CFG_OUTSTANDING				0x00009000
+#define SDMA_CFG_OUTSTANDING_RESERVED_0__MASK			0xffff0000
+#define SDMA_CFG_OUTSTANDING_RESERVED_0__SHIFT			16
+static inline uint32_t SDMA_CFG_OUTSTANDING_RESERVED_0(uint32_t val)
+{
+	return ((val) << SDMA_CFG_OUTSTANDING_RESERVED_0__SHIFT) & SDMA_CFG_OUTSTANDING_RESERVED_0__MASK;
+}
+#define SDMA_CFG_OUTSTANDING_WR_OS_CNT__MASK			0x0000ff00
+#define SDMA_CFG_OUTSTANDING_WR_OS_CNT__SHIFT			8
+static inline uint32_t SDMA_CFG_OUTSTANDING_WR_OS_CNT(uint32_t val)
+{
+	return ((val) << SDMA_CFG_OUTSTANDING_WR_OS_CNT__SHIFT) & SDMA_CFG_OUTSTANDING_WR_OS_CNT__MASK;
+}
+#define SDMA_CFG_OUTSTANDING_RD_OS_CNT__MASK			0x000000ff
+#define SDMA_CFG_OUTSTANDING_RD_OS_CNT__SHIFT			0
+static inline uint32_t SDMA_CFG_OUTSTANDING_RD_OS_CNT(uint32_t val)
+{
+	return ((val) << SDMA_CFG_OUTSTANDING_RD_OS_CNT__SHIFT) & SDMA_CFG_OUTSTANDING_RD_OS_CNT__MASK;
+}
+
+#define REG_SDMA_RD_WEIGHT_0					0x00009004
+#define SDMA_RD_WEIGHT_0_RD_WEIGHT_PDP__MASK			0xff000000
+#define SDMA_RD_WEIGHT_0_RD_WEIGHT_PDP__SHIFT			24
+static inline uint32_t SDMA_RD_WEIGHT_0_RD_WEIGHT_PDP(uint32_t val)
+{
+	return ((val) << SDMA_RD_WEIGHT_0_RD_WEIGHT_PDP__SHIFT) & SDMA_RD_WEIGHT_0_RD_WEIGHT_PDP__MASK;
+}
+#define SDMA_RD_WEIGHT_0_RD_WEIGHT_DPU__MASK			0x00ff0000
+#define SDMA_RD_WEIGHT_0_RD_WEIGHT_DPU__SHIFT			16
+static inline uint32_t SDMA_RD_WEIGHT_0_RD_WEIGHT_DPU(uint32_t val)
+{
+	return ((val) << SDMA_RD_WEIGHT_0_RD_WEIGHT_DPU__SHIFT) & SDMA_RD_WEIGHT_0_RD_WEIGHT_DPU__MASK;
+}
+#define SDMA_RD_WEIGHT_0_RD_WEIGHT_KERNEL__MASK			0x0000ff00
+#define SDMA_RD_WEIGHT_0_RD_WEIGHT_KERNEL__SHIFT		8
+static inline uint32_t SDMA_RD_WEIGHT_0_RD_WEIGHT_KERNEL(uint32_t val)
+{
+	return ((val) << SDMA_RD_WEIGHT_0_RD_WEIGHT_KERNEL__SHIFT) & SDMA_RD_WEIGHT_0_RD_WEIGHT_KERNEL__MASK;
+}
+#define SDMA_RD_WEIGHT_0_RD_WEIGHT_FEATURE__MASK		0x000000ff
+#define SDMA_RD_WEIGHT_0_RD_WEIGHT_FEATURE__SHIFT		0
+static inline uint32_t SDMA_RD_WEIGHT_0_RD_WEIGHT_FEATURE(uint32_t val)
+{
+	return ((val) << SDMA_RD_WEIGHT_0_RD_WEIGHT_FEATURE__SHIFT) & SDMA_RD_WEIGHT_0_RD_WEIGHT_FEATURE__MASK;
+}
+
+#define REG_SDMA_WR_WEIGHT_0					0x00009008
+#define SDMA_WR_WEIGHT_0_RESERVED_0__MASK			0xffff0000
+#define SDMA_WR_WEIGHT_0_RESERVED_0__SHIFT			16
+static inline uint32_t SDMA_WR_WEIGHT_0_RESERVED_0(uint32_t val)
+{
+	return ((val) << SDMA_WR_WEIGHT_0_RESERVED_0__SHIFT) & SDMA_WR_WEIGHT_0_RESERVED_0__MASK;
+}
+#define SDMA_WR_WEIGHT_0_WR_WEIGHT_PDP__MASK			0x0000ff00
+#define SDMA_WR_WEIGHT_0_WR_WEIGHT_PDP__SHIFT			8
+static inline uint32_t SDMA_WR_WEIGHT_0_WR_WEIGHT_PDP(uint32_t val)
+{
+	return ((val) << SDMA_WR_WEIGHT_0_WR_WEIGHT_PDP__SHIFT) & SDMA_WR_WEIGHT_0_WR_WEIGHT_PDP__MASK;
+}
+#define SDMA_WR_WEIGHT_0_WR_WEIGHT_DPU__MASK			0x000000ff
+#define SDMA_WR_WEIGHT_0_WR_WEIGHT_DPU__SHIFT			0
+static inline uint32_t SDMA_WR_WEIGHT_0_WR_WEIGHT_DPU(uint32_t val)
+{
+	return ((val) << SDMA_WR_WEIGHT_0_WR_WEIGHT_DPU__SHIFT) & SDMA_WR_WEIGHT_0_WR_WEIGHT_DPU__MASK;
+}
+
+#define REG_SDMA_CFG_ID_ERROR					0x0000900c
+#define SDMA_CFG_ID_ERROR_RESERVED_0__MASK			0xfffffc00
+#define SDMA_CFG_ID_ERROR_RESERVED_0__SHIFT			10
+static inline uint32_t SDMA_CFG_ID_ERROR_RESERVED_0(uint32_t val)
+{
+	return ((val) << SDMA_CFG_ID_ERROR_RESERVED_0__SHIFT) & SDMA_CFG_ID_ERROR_RESERVED_0__MASK;
+}
+#define SDMA_CFG_ID_ERROR_WR_RESP_ID__MASK			0x000003c0
+#define SDMA_CFG_ID_ERROR_WR_RESP_ID__SHIFT			6
+static inline uint32_t SDMA_CFG_ID_ERROR_WR_RESP_ID(uint32_t val)
+{
+	return ((val) << SDMA_CFG_ID_ERROR_WR_RESP_ID__SHIFT) & SDMA_CFG_ID_ERROR_WR_RESP_ID__MASK;
+}
+#define SDMA_CFG_ID_ERROR_RESERVED_1__MASK			0x00000020
+#define SDMA_CFG_ID_ERROR_RESERVED_1__SHIFT			5
+static inline uint32_t SDMA_CFG_ID_ERROR_RESERVED_1(uint32_t val)
+{
+	return ((val) << SDMA_CFG_ID_ERROR_RESERVED_1__SHIFT) & SDMA_CFG_ID_ERROR_RESERVED_1__MASK;
+}
+#define SDMA_CFG_ID_ERROR_RD_RESP_ID__MASK			0x0000001f
+#define SDMA_CFG_ID_ERROR_RD_RESP_ID__SHIFT			0
+static inline uint32_t SDMA_CFG_ID_ERROR_RD_RESP_ID(uint32_t val)
+{
+	return ((val) << SDMA_CFG_ID_ERROR_RD_RESP_ID__SHIFT) & SDMA_CFG_ID_ERROR_RD_RESP_ID__MASK;
+}
+
+#define REG_SDMA_RD_WEIGHT_1					0x00009010
+#define SDMA_RD_WEIGHT_1_RESERVED_0__MASK			0xffffff00
+#define SDMA_RD_WEIGHT_1_RESERVED_0__SHIFT			8
+static inline uint32_t SDMA_RD_WEIGHT_1_RESERVED_0(uint32_t val)
+{
+	return ((val) << SDMA_RD_WEIGHT_1_RESERVED_0__SHIFT) & SDMA_RD_WEIGHT_1_RESERVED_0__MASK;
+}
+#define SDMA_RD_WEIGHT_1_RD_WEIGHT_PC__MASK			0x000000ff
+#define SDMA_RD_WEIGHT_1_RD_WEIGHT_PC__SHIFT			0
+static inline uint32_t SDMA_RD_WEIGHT_1_RD_WEIGHT_PC(uint32_t val)
+{
+	return ((val) << SDMA_RD_WEIGHT_1_RD_WEIGHT_PC__SHIFT) & SDMA_RD_WEIGHT_1_RD_WEIGHT_PC__MASK;
+}
+
+#define REG_SDMA_CFG_DMA_FIFO_CLR				0x00009014
+#define SDMA_CFG_DMA_FIFO_CLR_RESERVED_0__MASK			0xfffffffe
+#define SDMA_CFG_DMA_FIFO_CLR_RESERVED_0__SHIFT			1
+static inline uint32_t SDMA_CFG_DMA_FIFO_CLR_RESERVED_0(uint32_t val)
+{
+	return ((val) << SDMA_CFG_DMA_FIFO_CLR_RESERVED_0__SHIFT) & SDMA_CFG_DMA_FIFO_CLR_RESERVED_0__MASK;
+}
+#define SDMA_CFG_DMA_FIFO_CLR_DMA_FIFO_CLR__MASK		0x00000001
+#define SDMA_CFG_DMA_FIFO_CLR_DMA_FIFO_CLR__SHIFT		0
+static inline uint32_t SDMA_CFG_DMA_FIFO_CLR_DMA_FIFO_CLR(uint32_t val)
+{
+	return ((val) << SDMA_CFG_DMA_FIFO_CLR_DMA_FIFO_CLR__SHIFT) & SDMA_CFG_DMA_FIFO_CLR_DMA_FIFO_CLR__MASK;
+}
+
+#define REG_SDMA_CFG_DMA_ARB					0x00009018
+#define SDMA_CFG_DMA_ARB_RESERVED_0__MASK			0xfffffc00
+#define SDMA_CFG_DMA_ARB_RESERVED_0__SHIFT			10
+static inline uint32_t SDMA_CFG_DMA_ARB_RESERVED_0(uint32_t val)
+{
+	return ((val) << SDMA_CFG_DMA_ARB_RESERVED_0__SHIFT) & SDMA_CFG_DMA_ARB_RESERVED_0__MASK;
+}
+#define SDMA_CFG_DMA_ARB_WR_ARBIT_MODEL__MASK			0x00000200
+#define SDMA_CFG_DMA_ARB_WR_ARBIT_MODEL__SHIFT			9
+static inline uint32_t SDMA_CFG_DMA_ARB_WR_ARBIT_MODEL(uint32_t val)
+{
+	return ((val) << SDMA_CFG_DMA_ARB_WR_ARBIT_MODEL__SHIFT) & SDMA_CFG_DMA_ARB_WR_ARBIT_MODEL__MASK;
+}
+#define SDMA_CFG_DMA_ARB_RD_ARBIT_MODEL__MASK			0x00000100
+#define SDMA_CFG_DMA_ARB_RD_ARBIT_MODEL__SHIFT			8
+static inline uint32_t SDMA_CFG_DMA_ARB_RD_ARBIT_MODEL(uint32_t val)
+{
+	return ((val) << SDMA_CFG_DMA_ARB_RD_ARBIT_MODEL__SHIFT) & SDMA_CFG_DMA_ARB_RD_ARBIT_MODEL__MASK;
+}
+#define SDMA_CFG_DMA_ARB_RESERVED_1__MASK			0x00000080
+#define SDMA_CFG_DMA_ARB_RESERVED_1__SHIFT			7
+static inline uint32_t SDMA_CFG_DMA_ARB_RESERVED_1(uint32_t val)
+{
+	return ((val) << SDMA_CFG_DMA_ARB_RESERVED_1__SHIFT) & SDMA_CFG_DMA_ARB_RESERVED_1__MASK;
+}
+#define SDMA_CFG_DMA_ARB_WR_FIX_ARB__MASK			0x00000070
+#define SDMA_CFG_DMA_ARB_WR_FIX_ARB__SHIFT			4
+static inline uint32_t SDMA_CFG_DMA_ARB_WR_FIX_ARB(uint32_t val)
+{
+	return ((val) << SDMA_CFG_DMA_ARB_WR_FIX_ARB__SHIFT) & SDMA_CFG_DMA_ARB_WR_FIX_ARB__MASK;
+}
+#define SDMA_CFG_DMA_ARB_RESERVED_2__MASK			0x00000008
+#define SDMA_CFG_DMA_ARB_RESERVED_2__SHIFT			3
+static inline uint32_t SDMA_CFG_DMA_ARB_RESERVED_2(uint32_t val)
+{
+	return ((val) << SDMA_CFG_DMA_ARB_RESERVED_2__SHIFT) & SDMA_CFG_DMA_ARB_RESERVED_2__MASK;
+}
+#define SDMA_CFG_DMA_ARB_RD_FIX_ARB__MASK			0x00000007
+#define SDMA_CFG_DMA_ARB_RD_FIX_ARB__SHIFT			0
+static inline uint32_t SDMA_CFG_DMA_ARB_RD_FIX_ARB(uint32_t val)
+{
+	return ((val) << SDMA_CFG_DMA_ARB_RD_FIX_ARB__SHIFT) & SDMA_CFG_DMA_ARB_RD_FIX_ARB__MASK;
+}
+
+#define REG_SDMA_CFG_DMA_RD_QOS					0x00009020
+#define SDMA_CFG_DMA_RD_QOS_RESERVED_0__MASK			0xfffffc00
+#define SDMA_CFG_DMA_RD_QOS_RESERVED_0__SHIFT			10
+static inline uint32_t SDMA_CFG_DMA_RD_QOS_RESERVED_0(uint32_t val)
+{
+	return ((val) << SDMA_CFG_DMA_RD_QOS_RESERVED_0__SHIFT) & SDMA_CFG_DMA_RD_QOS_RESERVED_0__MASK;
+}
+#define SDMA_CFG_DMA_RD_QOS_RD_PC_QOS__MASK			0x00000300
+#define SDMA_CFG_DMA_RD_QOS_RD_PC_QOS__SHIFT			8
+static inline uint32_t SDMA_CFG_DMA_RD_QOS_RD_PC_QOS(uint32_t val)
+{
+	return ((val) << SDMA_CFG_DMA_RD_QOS_RD_PC_QOS__SHIFT) & SDMA_CFG_DMA_RD_QOS_RD_PC_QOS__MASK;
+}
+#define SDMA_CFG_DMA_RD_QOS_RD_PPU_QOS__MASK			0x000000c0
+#define SDMA_CFG_DMA_RD_QOS_RD_PPU_QOS__SHIFT			6
+static inline uint32_t SDMA_CFG_DMA_RD_QOS_RD_PPU_QOS(uint32_t val)
+{
+	return ((val) << SDMA_CFG_DMA_RD_QOS_RD_PPU_QOS__SHIFT) & SDMA_CFG_DMA_RD_QOS_RD_PPU_QOS__MASK;
+}
+#define SDMA_CFG_DMA_RD_QOS_RD_DPU_QOS__MASK			0x00000030
+#define SDMA_CFG_DMA_RD_QOS_RD_DPU_QOS__SHIFT			4
+static inline uint32_t SDMA_CFG_DMA_RD_QOS_RD_DPU_QOS(uint32_t val)
+{
+	return ((val) << SDMA_CFG_DMA_RD_QOS_RD_DPU_QOS__SHIFT) & SDMA_CFG_DMA_RD_QOS_RD_DPU_QOS__MASK;
+}
+#define SDMA_CFG_DMA_RD_QOS_RD_KERNEL_QOS__MASK			0x0000000c
+#define SDMA_CFG_DMA_RD_QOS_RD_KERNEL_QOS__SHIFT		2
+static inline uint32_t SDMA_CFG_DMA_RD_QOS_RD_KERNEL_QOS(uint32_t val)
+{
+	return ((val) << SDMA_CFG_DMA_RD_QOS_RD_KERNEL_QOS__SHIFT) & SDMA_CFG_DMA_RD_QOS_RD_KERNEL_QOS__MASK;
+}
+#define SDMA_CFG_DMA_RD_QOS_RD_FEATURE_QOS__MASK		0x00000003
+#define SDMA_CFG_DMA_RD_QOS_RD_FEATURE_QOS__SHIFT		0
+static inline uint32_t SDMA_CFG_DMA_RD_QOS_RD_FEATURE_QOS(uint32_t val)
+{
+	return ((val) << SDMA_CFG_DMA_RD_QOS_RD_FEATURE_QOS__SHIFT) & SDMA_CFG_DMA_RD_QOS_RD_FEATURE_QOS__MASK;
+}
+
+#define REG_SDMA_CFG_DMA_RD_CFG					0x00009024
+#define SDMA_CFG_DMA_RD_CFG_RESERVED_0__MASK			0xffffe000
+#define SDMA_CFG_DMA_RD_CFG_RESERVED_0__SHIFT			13
+static inline uint32_t SDMA_CFG_DMA_RD_CFG_RESERVED_0(uint32_t val)
+{
+	return ((val) << SDMA_CFG_DMA_RD_CFG_RESERVED_0__SHIFT) & SDMA_CFG_DMA_RD_CFG_RESERVED_0__MASK;
+}
+#define SDMA_CFG_DMA_RD_CFG_RD_ARLOCK__MASK			0x00001000
+#define SDMA_CFG_DMA_RD_CFG_RD_ARLOCK__SHIFT			12
+static inline uint32_t SDMA_CFG_DMA_RD_CFG_RD_ARLOCK(uint32_t val)
+{
+	return ((val) << SDMA_CFG_DMA_RD_CFG_RD_ARLOCK__SHIFT) & SDMA_CFG_DMA_RD_CFG_RD_ARLOCK__MASK;
+}
+#define SDMA_CFG_DMA_RD_CFG_RD_ARCACHE__MASK			0x00000f00
+#define SDMA_CFG_DMA_RD_CFG_RD_ARCACHE__SHIFT			8
+static inline uint32_t SDMA_CFG_DMA_RD_CFG_RD_ARCACHE(uint32_t val)
+{
+	return ((val) << SDMA_CFG_DMA_RD_CFG_RD_ARCACHE__SHIFT) & SDMA_CFG_DMA_RD_CFG_RD_ARCACHE__MASK;
+}
+#define SDMA_CFG_DMA_RD_CFG_RD_ARPROT__MASK			0x000000e0
+#define SDMA_CFG_DMA_RD_CFG_RD_ARPROT__SHIFT			5
+static inline uint32_t SDMA_CFG_DMA_RD_CFG_RD_ARPROT(uint32_t val)
+{
+	return ((val) << SDMA_CFG_DMA_RD_CFG_RD_ARPROT__SHIFT) & SDMA_CFG_DMA_RD_CFG_RD_ARPROT__MASK;
+}
+#define SDMA_CFG_DMA_RD_CFG_RD_ARBURST__MASK			0x00000018
+#define SDMA_CFG_DMA_RD_CFG_RD_ARBURST__SHIFT			3
+static inline uint32_t SDMA_CFG_DMA_RD_CFG_RD_ARBURST(uint32_t val)
+{
+	return ((val) << SDMA_CFG_DMA_RD_CFG_RD_ARBURST__SHIFT) & SDMA_CFG_DMA_RD_CFG_RD_ARBURST__MASK;
+}
+#define SDMA_CFG_DMA_RD_CFG_RD_ARSIZE__MASK			0x00000007
+#define SDMA_CFG_DMA_RD_CFG_RD_ARSIZE__SHIFT			0
+static inline uint32_t SDMA_CFG_DMA_RD_CFG_RD_ARSIZE(uint32_t val)
+{
+	return ((val) << SDMA_CFG_DMA_RD_CFG_RD_ARSIZE__SHIFT) & SDMA_CFG_DMA_RD_CFG_RD_ARSIZE__MASK;
+}
+
+#define REG_SDMA_CFG_DMA_WR_CFG					0x00009028
+#define SDMA_CFG_DMA_WR_CFG_RESERVED_0__MASK			0xffffe000
+#define SDMA_CFG_DMA_WR_CFG_RESERVED_0__SHIFT			13
+static inline uint32_t SDMA_CFG_DMA_WR_CFG_RESERVED_0(uint32_t val)
+{
+	return ((val) << SDMA_CFG_DMA_WR_CFG_RESERVED_0__SHIFT) & SDMA_CFG_DMA_WR_CFG_RESERVED_0__MASK;
+}
+#define SDMA_CFG_DMA_WR_CFG_WR_AWLOCK__MASK			0x00001000
+#define SDMA_CFG_DMA_WR_CFG_WR_AWLOCK__SHIFT			12
+static inline uint32_t SDMA_CFG_DMA_WR_CFG_WR_AWLOCK(uint32_t val)
+{
+	return ((val) << SDMA_CFG_DMA_WR_CFG_WR_AWLOCK__SHIFT) & SDMA_CFG_DMA_WR_CFG_WR_AWLOCK__MASK;
+}
+#define SDMA_CFG_DMA_WR_CFG_WR_AWCACHE__MASK			0x00000f00
+#define SDMA_CFG_DMA_WR_CFG_WR_AWCACHE__SHIFT			8
+static inline uint32_t SDMA_CFG_DMA_WR_CFG_WR_AWCACHE(uint32_t val)
+{
+	return ((val) << SDMA_CFG_DMA_WR_CFG_WR_AWCACHE__SHIFT) & SDMA_CFG_DMA_WR_CFG_WR_AWCACHE__MASK;
+}
+#define SDMA_CFG_DMA_WR_CFG_WR_AWPROT__MASK			0x000000e0
+#define SDMA_CFG_DMA_WR_CFG_WR_AWPROT__SHIFT			5
+static inline uint32_t SDMA_CFG_DMA_WR_CFG_WR_AWPROT(uint32_t val)
+{
+	return ((val) << SDMA_CFG_DMA_WR_CFG_WR_AWPROT__SHIFT) & SDMA_CFG_DMA_WR_CFG_WR_AWPROT__MASK;
+}
+#define SDMA_CFG_DMA_WR_CFG_WR_AWBURST__MASK			0x00000018
+#define SDMA_CFG_DMA_WR_CFG_WR_AWBURST__SHIFT			3
+static inline uint32_t SDMA_CFG_DMA_WR_CFG_WR_AWBURST(uint32_t val)
+{
+	return ((val) << SDMA_CFG_DMA_WR_CFG_WR_AWBURST__SHIFT) & SDMA_CFG_DMA_WR_CFG_WR_AWBURST__MASK;
+}
+#define SDMA_CFG_DMA_WR_CFG_WR_AWSIZE__MASK			0x00000007
+#define SDMA_CFG_DMA_WR_CFG_WR_AWSIZE__SHIFT			0
+static inline uint32_t SDMA_CFG_DMA_WR_CFG_WR_AWSIZE(uint32_t val)
+{
+	return ((val) << SDMA_CFG_DMA_WR_CFG_WR_AWSIZE__SHIFT) & SDMA_CFG_DMA_WR_CFG_WR_AWSIZE__MASK;
+}
+
+#define REG_SDMA_CFG_DMA_WSTRB					0x0000902c
+#define SDMA_CFG_DMA_WSTRB_WR_WSTRB__MASK			0xffffffff
+#define SDMA_CFG_DMA_WSTRB_WR_WSTRB__SHIFT			0
+static inline uint32_t SDMA_CFG_DMA_WSTRB_WR_WSTRB(uint32_t val)
+{
+	return ((val) << SDMA_CFG_DMA_WSTRB_WR_WSTRB__SHIFT) & SDMA_CFG_DMA_WSTRB_WR_WSTRB__MASK;
+}
+
+#define REG_SDMA_CFG_STATUS					0x00009030
+#define SDMA_CFG_STATUS_RESERVED_0__MASK			0xfffffe00
+#define SDMA_CFG_STATUS_RESERVED_0__SHIFT			9
+static inline uint32_t SDMA_CFG_STATUS_RESERVED_0(uint32_t val)
+{
+	return ((val) << SDMA_CFG_STATUS_RESERVED_0__SHIFT) & SDMA_CFG_STATUS_RESERVED_0__MASK;
+}
+#define SDMA_CFG_STATUS_IDEL__MASK				0x00000100
+#define SDMA_CFG_STATUS_IDEL__SHIFT				8
+static inline uint32_t SDMA_CFG_STATUS_IDEL(uint32_t val)
+{
+	return ((val) << SDMA_CFG_STATUS_IDEL__SHIFT) & SDMA_CFG_STATUS_IDEL__MASK;
+}
+#define SDMA_CFG_STATUS_RESERVED_1__MASK			0x000000ff
+#define SDMA_CFG_STATUS_RESERVED_1__SHIFT			0
+static inline uint32_t SDMA_CFG_STATUS_RESERVED_1(uint32_t val)
+{
+	return ((val) << SDMA_CFG_STATUS_RESERVED_1__SHIFT) & SDMA_CFG_STATUS_RESERVED_1__MASK;
+}
+
+#define REG_GLOBAL_OPERATION_ENABLE				0x0000f008
+#define GLOBAL_OPERATION_ENABLE_RESERVED_0__MASK		0xffffff80
+#define GLOBAL_OPERATION_ENABLE_RESERVED_0__SHIFT		7
+static inline uint32_t GLOBAL_OPERATION_ENABLE_RESERVED_0(uint32_t val)
+{
+	return ((val) << GLOBAL_OPERATION_ENABLE_RESERVED_0__SHIFT) & GLOBAL_OPERATION_ENABLE_RESERVED_0__MASK;
+}
+#define GLOBAL_OPERATION_ENABLE_PPU_RDMA_OP_EN__MASK		0x00000040
+#define GLOBAL_OPERATION_ENABLE_PPU_RDMA_OP_EN__SHIFT		6
+static inline uint32_t GLOBAL_OPERATION_ENABLE_PPU_RDMA_OP_EN(uint32_t val)
+{
+	return ((val) << GLOBAL_OPERATION_ENABLE_PPU_RDMA_OP_EN__SHIFT) & GLOBAL_OPERATION_ENABLE_PPU_RDMA_OP_EN__MASK;
+}
+#define GLOBAL_OPERATION_ENABLE_PPU_OP_EN__MASK			0x00000020
+#define GLOBAL_OPERATION_ENABLE_PPU_OP_EN__SHIFT		5
+static inline uint32_t GLOBAL_OPERATION_ENABLE_PPU_OP_EN(uint32_t val)
+{
+	return ((val) << GLOBAL_OPERATION_ENABLE_PPU_OP_EN__SHIFT) & GLOBAL_OPERATION_ENABLE_PPU_OP_EN__MASK;
+}
+#define GLOBAL_OPERATION_ENABLE_DPU_RDMA_OP_EN__MASK		0x00000010
+#define GLOBAL_OPERATION_ENABLE_DPU_RDMA_OP_EN__SHIFT		4
+static inline uint32_t GLOBAL_OPERATION_ENABLE_DPU_RDMA_OP_EN(uint32_t val)
+{
+	return ((val) << GLOBAL_OPERATION_ENABLE_DPU_RDMA_OP_EN__SHIFT) & GLOBAL_OPERATION_ENABLE_DPU_RDMA_OP_EN__MASK;
+}
+#define GLOBAL_OPERATION_ENABLE_DPU_OP_EN__MASK			0x00000008
+#define GLOBAL_OPERATION_ENABLE_DPU_OP_EN__SHIFT		3
+static inline uint32_t GLOBAL_OPERATION_ENABLE_DPU_OP_EN(uint32_t val)
+{
+	return ((val) << GLOBAL_OPERATION_ENABLE_DPU_OP_EN__SHIFT) & GLOBAL_OPERATION_ENABLE_DPU_OP_EN__MASK;
+}
+#define GLOBAL_OPERATION_ENABLE_CORE_OP_EN__MASK		0x00000004
+#define GLOBAL_OPERATION_ENABLE_CORE_OP_EN__SHIFT		2
+static inline uint32_t GLOBAL_OPERATION_ENABLE_CORE_OP_EN(uint32_t val)
+{
+	return ((val) << GLOBAL_OPERATION_ENABLE_CORE_OP_EN__SHIFT) & GLOBAL_OPERATION_ENABLE_CORE_OP_EN__MASK;
+}
+#define GLOBAL_OPERATION_ENABLE_RESERVED_1__MASK		0x00000002
+#define GLOBAL_OPERATION_ENABLE_RESERVED_1__SHIFT		1
+static inline uint32_t GLOBAL_OPERATION_ENABLE_RESERVED_1(uint32_t val)
+{
+	return ((val) << GLOBAL_OPERATION_ENABLE_RESERVED_1__SHIFT) & GLOBAL_OPERATION_ENABLE_RESERVED_1__MASK;
+}
+#define GLOBAL_OPERATION_ENABLE_CNA_OP_EN__MASK			0x00000001
+#define GLOBAL_OPERATION_ENABLE_CNA_OP_EN__SHIFT		0
+static inline uint32_t GLOBAL_OPERATION_ENABLE_CNA_OP_EN(uint32_t val)
+{
+	return ((val) << GLOBAL_OPERATION_ENABLE_CNA_OP_EN__SHIFT) & GLOBAL_OPERATION_ENABLE_CNA_OP_EN__MASK;
+}
+
+#endif /* __ROCKET_REGISTERS_XML__ */
diff --git a/drivers/accessibility/Kconfig b/drivers/accessibility/Kconfig
index 00f7512c9cf4..6b2f79d1f1b8 100644
--- a/drivers/accessibility/Kconfig
+++ b/drivers/accessibility/Kconfig
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 menuconfig ACCESSIBILITY
 	bool "Accessibility support"
-	---help---
+	help
 	  Accessibility handles all special kinds of hardware devices or
 	  software adapters which help people with disabilities (e.g.
 	  blindness) to use computers.
@@ -21,7 +21,7 @@ config A11Y_BRAILLE_CONSOLE
 	bool "Console on braille device"
 	depends on VT
 	depends on SERIAL_CORE_CONSOLE
-	---help---
+	help
 	  Enables console output on a braille device connected to a 8250
 	  serial port. For now only the VisioBraille device is supported.
 
@@ -31,4 +31,6 @@ config A11Y_BRAILLE_CONSOLE
 
 	  If unsure, say N.
 
+source "drivers/accessibility/speakup/Kconfig"
+
 endif # ACCESSIBILITY
diff --git a/drivers/accessibility/Makefile b/drivers/accessibility/Makefile
index e8c182f82c44..833603086530 100644
--- a/drivers/accessibility/Makefile
+++ b/drivers/accessibility/Makefile
@@ -1,2 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0-only
 obj-y				+= braille/
+obj-$(CONFIG_SPEAKUP)		+= speakup/
diff --git a/drivers/accessibility/braille/braille_console.c b/drivers/accessibility/braille/braille_console.c
index a8f7c278b691..06b43b678d6e 100644
--- a/drivers/accessibility/braille/braille_console.c
+++ b/drivers/accessibility/braille/braille_console.c
@@ -24,7 +24,6 @@
 
 MODULE_AUTHOR("samuel.thibault@ens-lyon.org");
 MODULE_DESCRIPTION("braille device");
-MODULE_LICENSE("GPL");
 
 /*
  * Braille device support part.
@@ -109,16 +108,16 @@ static void braille_write(u16 *buf)
 /* Follow the VC cursor*/
 static void vc_follow_cursor(struct vc_data *vc)
 {
-	vc_x = vc->vc_x - (vc->vc_x % WIDTH);
-	vc_y = vc->vc_y;
-	lastvc_x = vc->vc_x;
-	lastvc_y = vc->vc_y;
+	vc_x = vc->state.x - (vc->state.x % WIDTH);
+	vc_y = vc->state.y;
+	lastvc_x = vc->state.x;
+	lastvc_y = vc->state.y;
 }
 
 /* Maybe the VC cursor moved, if so follow it */
 static void vc_maybe_cursor_moved(struct vc_data *vc)
 {
-	if (vc->vc_x != lastvc_x || vc->vc_y != lastvc_y)
+	if (vc->state.x != lastvc_x || vc->state.y != lastvc_y)
 		vc_follow_cursor(vc);
 }
 
@@ -131,7 +130,7 @@ static void vc_refresh(struct vc_data *vc)
 	for (i = 0; i < WIDTH; i++) {
 		u16 glyph = screen_glyph(vc,
 				2 * (vc_x + i) + vc_y * vc->vc_size_row);
-		buf[i] = inverse_translate(vc, glyph, 1);
+		buf[i] = inverse_translate(vc, glyph, true);
 	}
 	braille_write(buf);
 }
@@ -225,6 +224,7 @@ static int keyboard_notifier_call(struct notifier_block *blk,
 	case KBD_POST_KEYSYM:
 	{
 		unsigned char type = KTYP(param->value) - 0xf0;
+
 		if (type == KT_SPEC) {
 			unsigned char val = KVAL(param->value);
 			int on_off = -1;
@@ -246,6 +246,7 @@ static int keyboard_notifier_call(struct notifier_block *blk,
 				beep(440);
 		}
 	}
+		break;
 	case KBD_UNBOUND_KEYCODE:
 	case KBD_UNICODE:
 	case KBD_KEYSYM:
@@ -264,6 +265,7 @@ static int vt_notifier_call(struct notifier_block *blk,
 {
 	struct vt_notifier_param *param = _param;
 	struct vc_data *vc = param->vc;
+
 	switch (code) {
 	case VT_ALLOCATE:
 		break;
@@ -272,6 +274,7 @@ static int vt_notifier_call(struct notifier_block *blk,
 	case VT_WRITE:
 	{
 		unsigned char c = param->c;
+
 		if (vc->vc_num != fg_console)
 			break;
 		switch (c) {
@@ -290,7 +293,7 @@ static int vt_notifier_call(struct notifier_block *blk,
 			break;
 		case '\t':
 			c = ' ';
-			/* Fallthrough */
+			fallthrough;
 		default:
 			if (c < 32)
 				/* Ignore other control sequences */
diff --git a/drivers/accessibility/speakup/.gitignore b/drivers/accessibility/speakup/.gitignore
new file mode 100644
index 000000000000..ac084679fea7
--- /dev/null
+++ b/drivers/accessibility/speakup/.gitignore
@@ -0,0 +1,4 @@
+/makemapdata
+/mapdata.h
+/genmap
+/speakupmap.h
diff --git a/drivers/staging/speakup/DefaultKeyAssignments b/drivers/accessibility/speakup/DefaultKeyAssignments
index 101c803b21fd..101c803b21fd 100644
--- a/drivers/staging/speakup/DefaultKeyAssignments
+++ b/drivers/accessibility/speakup/DefaultKeyAssignments
diff --git a/drivers/accessibility/speakup/Kconfig b/drivers/accessibility/speakup/Kconfig
new file mode 100644
index 000000000000..e84fb617acc4
--- /dev/null
+++ b/drivers/accessibility/speakup/Kconfig
@@ -0,0 +1,206 @@
+# SPDX-License-Identifier: GPL-2.0
+menu "Speakup console speech"
+
+config SPEAKUP
+	depends on VT
+	tristate "Speakup core"
+	help
+		This is the Speakup screen reader.  Think of it as a
+		video console for blind people.  If built in to the
+		kernel, it can speak everything on the text console from
+		boot up to shutdown.  For more information on Speakup,
+		point your browser at <http://www.linux-speakup.org/>.
+		There is also a mailing list at the above url that you
+		can subscribe to.
+
+		Supported synthesizers are accent sa, accent pc,
+		appollo II., Auddapter, Braille 'n Speak, Dectalk
+		external (old), Dectalk PC (full length isa board),
+		Dectalk express, Doubletalk, Doubletalk LT or
+		Litetalk, Keynote Gold internal PC, software
+		synthesizers, Speakout, transport, and a dummy module
+		that can be used with a plain text terminal.
+
+		Speakup can either be built in or compiled as a module
+		by answering y or m.  If you answer y here, then you
+		must answer either y or m to at least one of the
+		synthesizer drivers below.  If you answer m here, then
+		the synthesizer drivers below can only be built as
+		modules.
+
+		These drivers are not standalone drivers, but must be
+		used in conjunction with Speakup.  Think of them as
+		video cards for blind people.
+
+
+		The Dectalk pc driver can only be built as a module, and
+		requires software to be pre-loaded on to the card before
+		the module can be loaded.  See the decpc choice below
+		for more details.
+
+		If you are not a blind person, or don't have access to
+		one of the listed synthesizers, you should say n.
+
+if SPEAKUP
+
+config SPEAKUP_SERIALIO
+	def_bool y
+	depends on ISA || COMPILE_TEST
+	depends on HAS_IOPORT
+
+config SPEAKUP_SYNTH_ACNTSA
+	tristate "Accent SA synthesizer support"
+	help
+		This is the Speakup driver for the Accent SA
+		synthesizer.  You can say y to build it into the kernel,
+		or m to build it as a module.  See the configuration
+		help on the Speakup choice above for more info.
+
+config SPEAKUP_SYNTH_ACNTPC
+	tristate "Accent PC synthesizer support"
+	depends on SPEAKUP_SERIALIO
+	help
+		This is the Speakup driver for the accent pc
+		synthesizer.  You can say y to build it into the kernel,
+		or m to build it as a module.  See the configuration
+		help on the Speakup choice above for more info.
+
+config SPEAKUP_SYNTH_APOLLO
+	tristate "Apollo II synthesizer support"
+	help
+		This is the Speakup driver for the Apollo II
+		synthesizer.  You can say y to build it into the kernel,
+		or m to build it as a module.  See the configuration
+		help on the Speakup choice above for more info.
+
+config SPEAKUP_SYNTH_AUDPTR
+	tristate "Audapter synthesizer support"
+	help
+		This is the Speakup driver for the Audapter synthesizer.
+		 You can say y to build it into the kernel, or m to
+		build it as a module.  See the configuration help on the
+		Speakup choice above for more info.
+
+config SPEAKUP_SYNTH_BNS
+	tristate "Braille 'n' Speak synthesizer support"
+	help
+		This is the Speakup driver for the Braille 'n' Speak
+		synthesizer.  You can say y to build it into the kernel,
+		or m to build it as a module.  See the configuration
+		help on the Speakup choice above for more info.
+
+config SPEAKUP_SYNTH_DECTLK
+	tristate "DECtalk Express synthesizer support"
+	help
+
+		This is the Speakup driver for the DecTalk Express
+		synthesizer.  You can say y to build it into the kernel,
+		or m to build it as a module.  See the configuration
+		help on the Speakup choice above for more info.
+
+config SPEAKUP_SYNTH_DECEXT
+	tristate "DECtalk External (old) synthesizer support"
+	help
+
+		This is the Speakup driver for the DecTalk External
+		(old) synthesizer.  You can say y to build it into the
+		kernel, or m to build it as a module.  See the
+		configuration help on the Speakup choice above for more
+		info.
+
+config SPEAKUP_SYNTH_DECPC
+	depends on m
+	depends on SPEAKUP_SERIALIO
+	tristate "DECtalk PC (big ISA card) synthesizer support"
+	help
+
+		This is the Speakup driver for the DecTalk PC (full
+		length ISA) synthesizer.  You can say m to build it as
+		a module.  See the configuration help on the Speakup
+		choice above for more info.
+
+		In order to use the DecTalk PC driver, you must download
+		the dec_pc.tgz file from linux-speakup.org.  It is in
+		the pub/linux/goodies directory.  The dec_pc.tgz file
+		contains the software which must be pre-loaded on to the
+		DecTalk PC board in order to use it with this driver.
+		This driver must be built as a module, and can not be
+		loaded until the file system is mounted and the DecTalk
+		PC software has been pre-loaded on to the board.
+
+		See the README file in the dec_pc.tgz file for more
+		details.
+
+config SPEAKUP_SYNTH_DTLK
+	tristate "DoubleTalk PC synthesizer support"
+	depends on SPEAKUP_SERIALIO
+	help
+
+		This is the Speakup driver for the internal DoubleTalk
+		PC synthesizer.  You can say y to build it into the
+		kernel, or m to build it as a module.  See the
+		configuration help on the Speakup choice above for more
+		info.
+
+config SPEAKUP_SYNTH_KEYPC
+	tristate "Keynote Gold PC synthesizer support"
+	depends on SPEAKUP_SERIALIO
+	help
+
+		This is the Speakup driver for the Keynote Gold
+		PC synthesizer.  You can say y to build it into the
+		kernel, or m to build it as a module.  See the
+		configuration help on the Speakup choice above for more
+		info.
+
+config SPEAKUP_SYNTH_LTLK
+	tristate "DoubleTalk LT/LiteTalk synthesizer support"
+help
+
+		This is the Speakup driver for the LiteTalk/DoubleTalk
+		LT synthesizer.  You can say y to build it into the
+		kernel, or m to build it as a module.  See the
+		configuration help on the Speakup choice above for more
+		info.
+
+config SPEAKUP_SYNTH_SOFT
+	tristate "Userspace software synthesizer support"
+	help
+
+		This is the software synthesizer device node.  It will
+		register a device /dev/softsynth which midware programs
+		and speech daemons may open and read to provide kernel
+		output to software synths such as espeak, festival,
+		flite and so forth.  You can select 'y' or 'm' to have
+		it built-in to the kernel or loaded as a module.
+
+config SPEAKUP_SYNTH_SPKOUT
+	tristate "Speak Out synthesizer support"
+	help
+
+		This is the Speakup driver for the Speakout synthesizer.
+		 You can say y to build it into the kernel, or m to
+		build it as a module.  See the configuration help on the
+		Speakup choice above for more info.
+
+config SPEAKUP_SYNTH_TXPRT
+	tristate "Transport synthesizer support"
+	help
+
+		This is the Speakup driver for the Transport
+		synthesizer.  You can say y to build it into the kernel,
+		or m to build it as a module.  See the configuration
+		help on the Speakup choice above for more info.
+
+config SPEAKUP_SYNTH_DUMMY
+	tristate "Dummy synthesizer driver (for testing)"
+	help
+
+		This is a dummy Speakup driver for plugging a mere serial
+		terminal.  This is handy if you want to test speakup but
+		don't have the hardware.  You can say y to build it into
+		the kernel, or m to build it as a module.  See the
+		configuration help on the Speakup choice above for more info.
+
+endif	# SPEAKUP
+endmenu
diff --git a/drivers/accessibility/speakup/Makefile b/drivers/accessibility/speakup/Makefile
new file mode 100644
index 000000000000..14ba1cca87f4
--- /dev/null
+++ b/drivers/accessibility/speakup/Makefile
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_SPEAKUP_SYNTH_ACNTSA) += speakup_acntsa.o
+obj-$(CONFIG_SPEAKUP_SYNTH_ACNTPC) += speakup_acntpc.o
+obj-$(CONFIG_SPEAKUP_SYNTH_APOLLO) += speakup_apollo.o
+obj-$(CONFIG_SPEAKUP_SYNTH_AUDPTR) += speakup_audptr.o
+obj-$(CONFIG_SPEAKUP_SYNTH_BNS) += speakup_bns.o
+obj-$(CONFIG_SPEAKUP_SYNTH_DECTLK) += speakup_dectlk.o
+obj-$(CONFIG_SPEAKUP_SYNTH_DECEXT) += speakup_decext.o
+obj-$(CONFIG_SPEAKUP_SYNTH_DECPC) += speakup_decpc.o
+obj-$(CONFIG_SPEAKUP_SYNTH_DTLK) += speakup_dtlk.o
+obj-$(CONFIG_SPEAKUP_SYNTH_KEYPC) += speakup_keypc.o
+obj-$(CONFIG_SPEAKUP_SYNTH_LTLK) += speakup_ltlk.o
+obj-$(CONFIG_SPEAKUP_SYNTH_SOFT) += speakup_soft.o
+obj-$(CONFIG_SPEAKUP_SYNTH_SPKOUT) += speakup_spkout.o
+obj-$(CONFIG_SPEAKUP_SYNTH_TXPRT) += speakup_txprt.o
+obj-$(CONFIG_SPEAKUP_SYNTH_DUMMY) += speakup_dummy.o
+
+obj-$(CONFIG_SPEAKUP) += speakup.o
+speakup-y := \
+	buffers.o \
+	devsynth.o \
+	i18n.o \
+	fakekey.o \
+	main.o \
+	keyhelp.o \
+	kobjects.o \
+	selection.o \
+	spk_ttyio.o \
+	synth.o \
+	thread.o \
+	varhandlers.o
+speakup-$(CONFIG_SPEAKUP_SERIALIO) += serialio.o
+
+
+clean-files := mapdata.h speakupmap.h
+
+
+# Generate mapdata.h from headers
+hostprogs += makemapdata
+makemapdata-objs := makemapdata.o
+
+quiet_cmd_mkmap = MKMAP   $@
+      cmd_mkmap = TOPDIR=$(srctree) SPKDIR=$(src) $(obj)/makemapdata > $@
+
+$(obj)/mapdata.h: $(obj)/makemapdata
+	$(call cmd,mkmap)
+
+
+# Generate speakupmap.h from mapdata.h
+hostprogs += genmap
+genmap-objs := genmap.o
+$(obj)/genmap.o: $(obj)/mapdata.h
+
+quiet_cmd_genmap = GENMAP  $@
+      cmd_genmap = $(obj)/genmap $< > $@
+
+$(obj)/speakupmap.h: $(src)/speakupmap.map $(obj)/genmap
+	$(call cmd,genmap)
+
+$(obj)/main.o: $(obj)/speakupmap.h
diff --git a/drivers/accessibility/speakup/TODO b/drivers/accessibility/speakup/TODO
new file mode 100644
index 000000000000..d4ca093bf0bd
--- /dev/null
+++ b/drivers/accessibility/speakup/TODO
@@ -0,0 +1,22 @@
+Speakup project home:  http://www.linux-speakup.org
+
+Mailing List:  speakup@linux-speakup.org
+
+Speakup is a kernel based screen review package for the linux operating
+system.  It allows blind users to interact with applications on the
+linux console by means of synthetic speech.
+
+Currently, speakup has one issue we know of.
+
+It seems to only happen on SMP systems. It seems that text in the output buffer
+gets garbled because a lock is not set. This bug happens regularly, but no one
+has been able to find a situation which produces it consistently.
+
+Patches, suggestions, corrections, etc, are definitely welcome.
+
+We prefer that you contact us on the mailing list; however, if you do
+not want to subscribe to a mailing list, send your email to all of the
+following:
+
+okash.khawaja@gmail.com, w.d.hubbs@gmail.com, chris@the-brannons.com,
+kirk@reisers.ca and samuel.thibault@ens-lyon.org.
diff --git a/drivers/staging/speakup/buffers.c b/drivers/accessibility/speakup/buffers.c
index 1371ced2f5ca..1371ced2f5ca 100644
--- a/drivers/staging/speakup/buffers.c
+++ b/drivers/accessibility/speakup/buffers.c
diff --git a/drivers/accessibility/speakup/devsynth.c b/drivers/accessibility/speakup/devsynth.c
new file mode 100644
index 000000000000..e3d909bd0480
--- /dev/null
+++ b/drivers/accessibility/speakup/devsynth.c
@@ -0,0 +1,178 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <linux/errno.h>
+#include <linux/miscdevice.h>	/* for misc_register, and MISC_DYNAMIC_MINOR */
+#include <linux/types.h>
+#include <linux/uaccess.h>
+
+#include "speakup.h"
+#include "spk_priv.h"
+
+static int synth_registered, synthu_registered;
+static int dev_opened;
+
+/* Latin1 version */
+static ssize_t speakup_file_write(struct file *fp, const char __user *buffer,
+				  size_t nbytes, loff_t *ppos)
+{
+	size_t count = nbytes;
+	const char __user *ptr = buffer;
+	size_t bytes;
+	unsigned long flags;
+	u_char buf[256];
+
+	if (!synth)
+		return -ENODEV;
+	while (count > 0) {
+		bytes = min(count, sizeof(buf));
+		if (copy_from_user(buf, ptr, bytes))
+			return -EFAULT;
+		count -= bytes;
+		ptr += bytes;
+		spin_lock_irqsave(&speakup_info.spinlock, flags);
+		synth_write(buf, bytes);
+		spin_unlock_irqrestore(&speakup_info.spinlock, flags);
+	}
+	return (ssize_t)nbytes;
+}
+
+/* UTF-8 version */
+static ssize_t speakup_file_writeu(struct file *fp, const char __user *buffer,
+				   size_t nbytes, loff_t *ppos)
+{
+	size_t count = nbytes, consumed, want;
+	const char __user *ptr = buffer;
+	size_t bytes;
+	unsigned long flags;
+	unsigned char buf[256];
+	u16 ubuf[256];
+	size_t in, out;
+
+	if (!synth)
+		return -ENODEV;
+
+	want = 1;
+	while (count >= want) {
+		/* Copy some UTF-8 piece from userland */
+		bytes = min(count, sizeof(buf));
+		if (copy_from_user(buf, ptr, bytes))
+			return -EFAULT;
+
+		/* Convert to u16 */
+		for (in = 0, out = 0; in < bytes; in += consumed) {
+			s32 value;
+
+			value = synth_utf8_get(buf + in, bytes - in, &consumed, &want);
+			if (value == -1) {
+				/* Invalid or incomplete */
+
+				if (want > bytes - in)
+					/* We don't have it all yet, stop here
+					 * and wait for the rest
+					 */
+					bytes = in;
+
+				continue;
+			}
+
+			if (value < 0x10000)
+				ubuf[out++] = value;
+		}
+
+		count -= bytes;
+		ptr += bytes;
+
+		/* And speak this up */
+		if (out) {
+			spin_lock_irqsave(&speakup_info.spinlock, flags);
+			for (in = 0; in < out; in++)
+				synth_buffer_add(ubuf[in]);
+			synth_start();
+			spin_unlock_irqrestore(&speakup_info.spinlock, flags);
+		}
+	}
+
+	return (ssize_t)(nbytes - count);
+}
+
+static ssize_t speakup_file_read(struct file *fp, char __user *buf,
+				 size_t nbytes, loff_t *ppos)
+{
+	return 0;
+}
+
+static int speakup_file_open(struct inode *ip, struct file *fp)
+{
+	if (!synth)
+		return -ENODEV;
+	if (xchg(&dev_opened, 1))
+		return -EBUSY;
+	return 0;
+}
+
+static int speakup_file_release(struct inode *ip, struct file *fp)
+{
+	dev_opened = 0;
+	return 0;
+}
+
+static const struct file_operations synth_fops = {
+	.read = speakup_file_read,
+	.write = speakup_file_write,
+	.open = speakup_file_open,
+	.release = speakup_file_release,
+};
+
+static const struct file_operations synthu_fops = {
+	.read = speakup_file_read,
+	.write = speakup_file_writeu,
+	.open = speakup_file_open,
+	.release = speakup_file_release,
+};
+
+static struct miscdevice synth_device = {
+	.minor = MISC_DYNAMIC_MINOR,
+	.name = "synth",
+	.fops = &synth_fops,
+};
+
+static struct miscdevice synthu_device = {
+	.minor = MISC_DYNAMIC_MINOR,
+	.name = "synthu",
+	.fops = &synthu_fops,
+};
+
+void speakup_register_devsynth(void)
+{
+	if (!synth_registered) {
+		if (misc_register(&synth_device)) {
+			pr_warn("Couldn't initialize miscdevice /dev/synth.\n");
+		} else {
+			pr_info("initialized device: /dev/synth, node (MAJOR %d, MINOR %d)\n",
+				MISC_MAJOR, synth_device.minor);
+			synth_registered = 1;
+		}
+	}
+	if (!synthu_registered) {
+		if (misc_register(&synthu_device)) {
+			pr_warn("Couldn't initialize miscdevice /dev/synthu.\n");
+		} else {
+			pr_info("initialized device: /dev/synthu, node (MAJOR %d, MINOR %d)\n",
+				MISC_MAJOR, synthu_device.minor);
+			synthu_registered = 1;
+		}
+	}
+}
+
+void speakup_unregister_devsynth(void)
+{
+	if (synth_registered) {
+		pr_info("speakup: unregistering synth device /dev/synth\n");
+		misc_deregister(&synth_device);
+		synth_registered = 0;
+	}
+	if (synthu_registered) {
+		pr_info("speakup: unregistering synth device /dev/synthu\n");
+		misc_deregister(&synthu_device);
+		synthu_registered = 0;
+	}
+}
diff --git a/drivers/staging/speakup/fakekey.c b/drivers/accessibility/speakup/fakekey.c
index cd029968462f..868c47b2a59b 100644
--- a/drivers/staging/speakup/fakekey.c
+++ b/drivers/accessibility/speakup/fakekey.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /* fakekey.c
- * Functions for simulating keypresses.
+ * Functions for simulating key presses.
  *
  * Copyright (C) 2010 the Speakup Team
  */
@@ -78,7 +78,7 @@ void speakup_fake_down_arrow(void)
 }
 
 /*
- * Are we handling a simulated keypress on the current CPU?
+ * Are we handling a simulated key press on the current CPU?
  * Returns a boolean.
  */
 bool speakup_fake_key_pressed(void)
diff --git a/drivers/accessibility/speakup/genmap.c b/drivers/accessibility/speakup/genmap.c
new file mode 100644
index 000000000000..0882bab10fb8
--- /dev/null
+++ b/drivers/accessibility/speakup/genmap.c
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* genmap.c
+ * originally written by: Kirk Reiser.
+ *
+ ** Copyright (C) 2002  Kirk Reiser.
+ *  Copyright (C) 2003  David Borowski.
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <libgen.h>
+#include <string.h>
+#include <ctype.h>
+#include "utils.h"
+
+struct st_key_init {
+	char *name;
+	int value, shift;
+};
+
+static unsigned char key_data[MAXKEYVAL][16], *kp;
+
+#include "mapdata.h"
+
+static const char delims[] = "\t\n ";
+static char *cp;
+static int map_ver = 119; /* an arbitrary number so speakup can check */
+static int shift_table[17];
+static int max_states = 1, flags;
+/* flags reserved for later, maybe for individual console maps */
+
+static int get_shift_value(int state)
+{
+	int i;
+
+	for (i = 0; shift_table[i] != state; i++) {
+		if (shift_table[i] == -1) {
+			if (i >= 16)
+				oops("too many shift states", NULL);
+			shift_table[i] = state;
+			max_states = i+1;
+		break;
+	}
+	}
+	return i;
+}
+
+int
+main(int argc, char *argv[])
+{
+	int value, shift_state, i, spk_val = 0, lock_val = 0;
+	int max_key_used = 0, num_keys_used = 0;
+	struct st_key *this;
+	struct st_key_init *p_init;
+	char buffer[256];
+
+	bzero(key_table, sizeof(key_table));
+	bzero(key_data, sizeof(key_data));
+
+	shift_table[0] = 0;
+	for (i = 1; i <= 16; i++)
+		shift_table[i] = -1;
+
+	if (argc < 2) {
+		fputs("usage: genmap filename\n", stderr);
+		exit(1);
+	}
+
+	for (p_init = init_key_data; p_init->name[0] != '.'; p_init++)
+		add_key(p_init->name, p_init->value, p_init->shift);
+
+	open_input(NULL, argv[1]);
+	while (fgets(buffer, sizeof(buffer), infile)) {
+		lc++;
+		value = shift_state = 0;
+
+		cp = strtok(buffer, delims);
+		if (*cp == '#')
+			continue;
+
+		while (cp) {
+			if (*cp == '=')
+				break;
+			this = find_key(cp);
+			if (this == NULL)
+				oops("unknown key/modifier", cp);
+			if (this->shift == is_shift) {
+				if (value)
+					oops("modifiers must come first", cp);
+				shift_state += this->value;
+			} else if (this->shift == is_input)
+				value = this->value;
+			else
+				oops("bad modifier or key", cp);
+			cp = strtok(0, delims);
+		}
+		if (!cp)
+			oops("no = found", NULL);
+
+		cp = strtok(0, delims);
+		if (!cp)
+			oops("no speakup function after =", NULL);
+
+		this = find_key(cp);
+		if (this == NULL || this->shift != is_spk)
+			oops("invalid speakup function", cp);
+
+		i = get_shift_value(shift_state);
+		if (key_data[value][i]) {
+			while (--cp > buffer)
+				if (!*cp)
+					*cp = ' ';
+			oops("two functions on same key combination", cp);
+		}
+		key_data[value][i] = (char)this->value;
+		if (value > max_key_used)
+			max_key_used = value;
+	}
+	fclose(infile);
+
+	this = find_key("spk_key");
+	if (this)
+		spk_val = this->value;
+
+	this = find_key("spk_lock");
+	if (this)
+		lock_val = this->value;
+
+	for (lc = 1; lc <= max_key_used; lc++) {
+		kp = key_data[lc];
+		if (!memcmp(key_data[0], kp, 16))
+			continue;
+		num_keys_used++;
+		for (i = 0; i < max_states; i++) {
+			if (kp[i] != spk_val && kp[i] != lock_val)
+				continue;
+			shift_state = shift_table[i];
+			if (shift_state&16)
+				continue;
+			shift_state = get_shift_value(shift_state+16);
+			kp[shift_state] = kp[i];
+			/* fill in so we can process the key up, as spk bit will be set */
+		}
+	}
+
+	printf("\t%d, %d, %d,\n\t", map_ver, num_keys_used, max_states);
+	for (i = 0; i < max_states; i++)
+		printf("%d, ", shift_table[i]);
+	printf("%d,", flags);
+	for (lc = 1; lc <= max_key_used; lc++) {
+		kp = key_data[lc];
+		if (!memcmp(key_data[0], kp, 16))
+			continue;
+		printf("\n\t%d,", lc);
+		for (i = 0; i < max_states; i++)
+			printf(" %d,", (unsigned int)kp[i]);
+	}
+	printf("\n\t0, %d\n", map_ver);
+
+	exit(0);
+}
diff --git a/drivers/staging/speakup/i18n.c b/drivers/accessibility/speakup/i18n.c
index ee240d36f947..d62079b1661f 100644
--- a/drivers/staging/speakup/i18n.c
+++ b/drivers/accessibility/speakup/i18n.c
@@ -90,6 +90,13 @@ static char *speakup_default_msgs[MSG_LAST_INDEX] = {
 	[MSG_COLOR_YELLOW] = "yellow",
 	[MSG_COLOR_WHITE] = "white",
 	[MSG_COLOR_GREY] = "grey",
+	[MSG_COLOR_BRIGHTBLUE] = "bright blue",
+	[MSG_COLOR_BRIGHTGREEN] = "bright green",
+	[MSG_COLOR_BRIGHTCYAN] = "bright cyan",
+	[MSG_COLOR_BRIGHTRED] = "bright red",
+	[MSG_COLOR_BRIGHTMAGENTA] = "bright magenta",
+	[MSG_COLOR_BRIGHTYELLOW] = "bright yellow",
+	[MSG_COLOR_BRIGHTWHITE] = "bright white",
 
 	/* Names of key states. */
 	[MSG_STATE_DOUBLE] = "double",
@@ -548,12 +555,10 @@ ssize_t spk_msg_set(enum msg_index_t index, char *text, size_t length)
 	if ((index < MSG_FIRST_INDEX) || (index >= MSG_LAST_INDEX))
 		return -EINVAL;
 
-	newstr = kmalloc(length + 1, GFP_KERNEL);
+	newstr = kmemdup_nul(text, length, GFP_KERNEL);
 	if (!newstr)
 		return -ENOMEM;
 
-	memcpy(newstr, text, length);
-	newstr[length] = '\0';
 	if (index >= MSG_FORMATTED_START &&
 	    index <= MSG_FORMATTED_END &&
 	    !fmt_validate(speakup_default_msgs[index], newstr)) {
diff --git a/drivers/staging/speakup/i18n.h b/drivers/accessibility/speakup/i18n.h
index 2ec6e659d02b..51e3260995d9 100644
--- a/drivers/staging/speakup/i18n.h
+++ b/drivers/accessibility/speakup/i18n.h
@@ -23,12 +23,15 @@ enum msg_index_t {
 	MSG_OFF = MSG_STATUS_START,
 	MSG_ON,
 	MSG_NO_WINDOW,
+
+	/* These must be ordered the same as enum cursor_track */
 	MSG_CURSOR_MSGS_START,
 	MSG_CURSORING_OFF = MSG_CURSOR_MSGS_START,
 	MSG_CURSORING_ON,
 	MSG_HIGHLIGHT_TRACKING,
 	MSG_READ_WINDOW,
 	MSG_READ_ALL,
+
 	MSG_EDIT_DONE,
 	MSG_WINDOW_ALREADY_SET,
 	MSG_END_BEFORE_START,
@@ -41,11 +44,14 @@ enum msg_index_t {
 	MSG_LEAVING_HELP,
 	MSG_IS_UNASSIGNED,
 	MSG_HELP_INFO,
+
+	/* These must be ordered the same as enum edge */
 	MSG_EDGE_MSGS_START,
 	MSG_EDGE_TOP  = MSG_EDGE_MSGS_START,
 	MSG_EDGE_BOTTOM,
 	MSG_EDGE_LEFT,
 	MSG_EDGE_RIGHT,
+
 	MSG_NUMBER,
 	MSG_SPACE,
 	MSG_START, /* A little confusing, given our convention. */
@@ -93,7 +99,14 @@ enum msg_index_t {
 	MSG_COLOR_YELLOW,
 	MSG_COLOR_WHITE,
 	MSG_COLOR_GREY,
-	MSG_COLORS_END = MSG_COLOR_GREY,
+	MSG_COLOR_BRIGHTBLUE,
+	MSG_COLOR_BRIGHTGREEN,
+	MSG_COLOR_BRIGHTCYAN,
+	MSG_COLOR_BRIGHTRED,
+	MSG_COLOR_BRIGHTMAGENTA,
+	MSG_COLOR_BRIGHTYELLOW,
+	MSG_COLOR_BRIGHTWHITE,
+	MSG_COLORS_END = MSG_COLOR_BRIGHTWHITE,
 
 	MSG_STATES_START,
 	MSG_STATE_DOUBLE = MSG_STATES_START,
diff --git a/drivers/staging/speakup/keyhelp.c b/drivers/accessibility/speakup/keyhelp.c
index 822ceac83068..822ceac83068 100644
--- a/drivers/staging/speakup/keyhelp.c
+++ b/drivers/accessibility/speakup/keyhelp.c
diff --git a/drivers/staging/speakup/kobjects.c b/drivers/accessibility/speakup/kobjects.c
index 41ae24ab5d08..0dfdb6608e02 100644
--- a/drivers/staging/speakup/kobjects.c
+++ b/drivers/accessibility/speakup/kobjects.c
@@ -413,27 +413,24 @@ static ssize_t synth_direct_store(struct kobject *kobj,
 				  struct kobj_attribute *attr,
 				  const char *buf, size_t count)
 {
-	u_char tmp[256];
-	int len;
-	int bytes;
-	const char *ptr = buf;
+	char *unescaped;
 	unsigned long flags;
 
 	if (!synth)
 		return -EPERM;
 
-	len = strlen(buf);
+	unescaped = kstrdup(buf, GFP_KERNEL);
+	if (!unescaped)
+		return -ENOMEM;
+
+	string_unescape_any_inplace(unescaped);
+
 	spin_lock_irqsave(&speakup_info.spinlock, flags);
-	while (len > 0) {
-		bytes = min_t(size_t, len, 250);
-		strncpy(tmp, ptr, bytes);
-		tmp[bytes] = '\0';
-		string_unescape_any_inplace(tmp);
-		synth_printf("%s", tmp);
-		ptr += bytes;
-		len -= bytes;
-	}
+	synth_write(unescaped, strlen(unescaped));
 	spin_unlock_irqrestore(&speakup_info.spinlock, flags);
+
+	kfree(unescaped);
+
 	return count;
 }
 
@@ -914,6 +911,8 @@ static struct kobj_attribute say_word_ctl_attribute =
 	__ATTR(say_word_ctl, 0644, spk_var_show, spk_var_store);
 static struct kobj_attribute spell_delay_attribute =
 	__ATTR(spell_delay, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute cur_phonetic_attribute =
+	__ATTR(cur_phonetic, 0644, spk_var_show, spk_var_store);
 
 /*
  * These attributes are i18n related.
@@ -967,6 +966,7 @@ static struct attribute *main_attrs[] = {
 	&say_control_attribute.attr,
 	&say_word_ctl_attribute.attr,
 	&spell_delay_attribute.attr,
+	&cur_phonetic_attribute.attr,
 	NULL,
 };
 
diff --git a/drivers/accessibility/speakup/main.c b/drivers/accessibility/speakup/main.c
new file mode 100644
index 000000000000..e68cf1d83787
--- /dev/null
+++ b/drivers/accessibility/speakup/main.c
@@ -0,0 +1,2499 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* speakup.c
+ * review functions for the speakup screen review package.
+ * originally written by: Kirk Reiser and Andy Berdan.
+ *
+ * extensively modified by David Borowski.
+ *
+ ** Copyright (C) 1998  Kirk Reiser.
+ *  Copyright (C) 2003  David Borowski.
+ */
+
+#include <linux/kernel.h>
+#include <linux/vt.h>
+#include <linux/tty.h>
+#include <linux/mm.h>		/* __get_free_page() and friends */
+#include <linux/vt_kern.h>
+#include <linux/ctype.h>
+#include <linux/selection.h>
+#include <linux/unistd.h>
+#include <linux/jiffies.h>
+#include <linux/kthread.h>
+#include <linux/keyboard.h>	/* for KT_SHIFT */
+#include <linux/kbd_kern.h>	/* for vc_kbd_* and friends */
+#include <linux/input.h>
+#include <linux/kmod.h>
+
+/* speakup_*_selection */
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+#include <linux/consolemap.h>
+
+#include <linux/spinlock.h>
+#include <linux/notifier.h>
+
+#include <linux/uaccess.h>	/* copy_from|to|user() and others */
+
+#include "spk_priv.h"
+#include "speakup.h"
+
+#define MAX_DELAY msecs_to_jiffies(500)
+#define MINECHOCHAR SPACE
+
+MODULE_AUTHOR("Kirk Reiser <kirk@braille.uwo.ca>");
+MODULE_AUTHOR("Daniel Drake <dsd@gentoo.org>");
+MODULE_DESCRIPTION("Speakup console speech");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(SPEAKUP_VERSION);
+
+char *synth_name;
+module_param_named(synth, synth_name, charp, 0444);
+module_param_named(quiet, spk_quiet_boot, bool, 0444);
+
+MODULE_PARM_DESC(synth, "Synth to start if speakup is built in.");
+MODULE_PARM_DESC(quiet, "Do not announce when the synthesizer is found.");
+
+special_func spk_special_handler;
+
+short spk_pitch_shift, synth_flags;
+static u16 buf[256];
+int spk_attrib_bleep, spk_bleeps, spk_bleep_time = 10;
+int spk_no_intr, spk_spell_delay;
+int spk_key_echo, spk_say_word_ctl;
+int spk_say_ctrl, spk_bell_pos;
+short spk_punc_mask;
+int spk_punc_level, spk_reading_punc;
+int spk_cur_phonetic;
+char spk_str_caps_start[MAXVARLEN + 1] = "\0";
+char spk_str_caps_stop[MAXVARLEN + 1] = "\0";
+char spk_str_pause[MAXVARLEN + 1] = "\0";
+bool spk_paused;
+const struct st_bits_data spk_punc_info[] = {
+	{"none", "", 0},
+	{"some", "/$%&@", SOME},
+	{"most", "$%&#()=+*/@^<>|\\", MOST},
+	{"all", "!\"#$%&'()*+,-./:;<=>?@[\\]^_`{|}~", PUNC},
+	{"delimiters", "", B_WDLM},
+	{"repeats", "()", CH_RPT},
+	{"extended numeric", "", B_EXNUM},
+	{"symbols", "", B_SYM},
+	{NULL, NULL}
+};
+
+static char mark_cut_flag;
+#define MAX_KEY 160
+static u_char *spk_shift_table;
+u_char *spk_our_keys[MAX_KEY];
+u_char spk_key_buf[600];
+const u_char spk_key_defaults[] = {
+#include "speakupmap.h"
+};
+
+/* cursor track modes, must be ordered same as cursor_msgs in enum msg_index_t */
+enum cursor_track {
+	CT_Off = 0,
+	CT_On,
+	CT_Highlight,
+	CT_Window,
+	CT_Max,
+	read_all_mode = CT_Max,
+};
+
+/* Speakup Cursor Track Variables */
+static enum cursor_track cursor_track = 1, prev_cursor_track = 1;
+
+static struct tty_struct *tty;
+
+static void spkup_write(const u16 *in_buf, int count);
+
+static char *phonetic[] = {
+	"alfa", "bravo", "charlie", "delta", "echo", "foxtrot", "golf", "hotel",
+	"india", "juliett", "keelo", "leema", "mike", "november", "oscar",
+	    "papa",
+	"keh beck", "romeo", "sierra", "tango", "uniform", "victer", "whiskey",
+	"x ray", "yankee", "zulu"
+};
+
+/* array of 256 char pointers (one for each character description)
+ * initialized to default_chars and user selectable via
+ * /proc/speakup/characters
+ */
+char *spk_characters[256];
+
+char *spk_default_chars[256] = {
+/*000*/ "null", "^a", "^b", "^c", "^d", "^e", "^f", "^g",
+/*008*/ "^h", "^i", "^j", "^k", "^l", "^m", "^n", "^o",
+/*016*/ "^p", "^q", "^r", "^s", "^t", "^u", "^v", "^w",
+/*024*/ "^x", "^y", "^z", "control", "control", "control", "control",
+	    "control",
+/*032*/ "space", "bang!", "quote", "number", "dollar", "percent", "and",
+	    "tick",
+/*040*/ "left paren", "right paren", "star", "plus", "comma", "dash",
+	    "dot",
+	"slash",
+/*048*/ "zero", "one", "two", "three", "four", "five", "six", "seven",
+	"eight", "nine",
+/*058*/ "colon", "semmy", "less", "equals", "greater", "question", "at",
+/*065*/ "EIGH", "B", "C", "D", "E", "F", "G",
+/*072*/ "H", "I", "J", "K", "L", "M", "N", "O",
+/*080*/ "P", "Q", "R", "S", "T", "U", "V", "W", "X",
+/*089*/ "Y", "ZED", "left bracket", "backslash", "right bracket",
+	    "caret",
+	"line",
+/*096*/ "accent", "a", "b", "c", "d", "e", "f", "g",
+/*104*/ "h", "i", "j", "k", "l", "m", "n", "o",
+/*112*/ "p", "q", "r", "s", "t", "u", "v", "w",
+/*120*/ "x", "y", "zed", "left brace", "bar", "right brace", "tihlduh",
+/*127*/ "del", "control", "control", "control", "control", "control",
+	    "control", "control", "control", "control", "control",
+/*138*/ "control", "control", "control", "control", "control",
+	    "control", "control", "control", "control", "control",
+	    "control", "control",
+/*150*/ "control", "control", "control", "control", "control",
+	    "control", "control", "control", "control", "control",
+/*160*/ "nbsp", "inverted bang",
+/*162*/ "cents", "pounds", "currency", "yen", "broken bar", "section",
+/*168*/ "diaeresis", "copyright", "female ordinal", "double left angle",
+/*172*/ "not", "soft hyphen", "registered", "macron",
+/*176*/ "degrees", "plus or minus", "super two", "super three",
+/*180*/ "acute accent", "micro", "pilcrow", "middle dot",
+/*184*/ "cedilla", "super one", "male ordinal", "double right angle",
+/*188*/ "one quarter", "one half", "three quarters",
+	    "inverted question",
+/*192*/ "A GRAVE", "A ACUTE", "A CIRCUMFLEX", "A TILDE", "A OOMLAUT",
+	    "A RING",
+/*198*/ "AE", "C CIDELLA", "E GRAVE", "E ACUTE", "E CIRCUMFLEX",
+	    "E OOMLAUT",
+/*204*/ "I GRAVE", "I ACUTE", "I CIRCUMFLEX", "I OOMLAUT", "ETH",
+	    "N TILDE",
+/*210*/ "O GRAVE", "O ACUTE", "O CIRCUMFLEX", "O TILDE", "O OOMLAUT",
+/*215*/ "multiplied by", "O STROKE", "U GRAVE", "U ACUTE",
+	    "U CIRCUMFLEX",
+/*220*/ "U OOMLAUT", "Y ACUTE", "THORN", "sharp s", "a grave",
+/*225*/ "a acute", "a circumflex", "a tilde", "a oomlaut", "a ring",
+/*230*/ "ae", "c cidella", "e grave", "e acute",
+/*234*/ "e circumflex", "e oomlaut", "i grave", "i acute",
+	    "i circumflex",
+/*239*/ "i oomlaut", "eth", "n tilde", "o grave", "o acute",
+	    "o circumflex",
+/*245*/ "o tilde", "o oomlaut", "divided by", "o stroke", "u grave",
+	    "u acute",
+/* 251 */ "u circumflex", "u oomlaut", "y acute", "thorn", "y oomlaut"
+};
+
+/* array of 256 u_short (one for each character)
+ * initialized to default_chartab and user selectable via
+ * /sys/module/speakup/parameters/chartab
+ */
+u_short spk_chartab[256];
+
+static u_short default_chartab[256] = {
+	B_CTL, B_CTL, B_CTL, B_CTL, B_CTL, B_CTL, B_CTL, B_CTL,	/* 0-7 */
+	B_CTL, B_CTL, A_CTL, B_CTL, B_CTL, B_CTL, B_CTL, B_CTL,	/* 8-15 */
+	B_CTL, B_CTL, B_CTL, B_CTL, B_CTL, B_CTL, B_CTL, B_CTL,	/*16-23 */
+	B_CTL, B_CTL, B_CTL, B_CTL, B_CTL, B_CTL, B_CTL, B_CTL,	/* 24-31 */
+	WDLM, A_PUNC, PUNC, PUNC, PUNC, PUNC, PUNC, A_PUNC,	/*  !"#$%&' */
+	PUNC, PUNC, PUNC, PUNC, A_PUNC, A_PUNC, A_PUNC, PUNC,	/* ()*+, -./ */
+	NUM, NUM, NUM, NUM, NUM, NUM, NUM, NUM,	/* 01234567 */
+	NUM, NUM, A_PUNC, PUNC, PUNC, PUNC, PUNC, A_PUNC,	/* 89:;<=>? */
+	PUNC, A_CAP, A_CAP, A_CAP, A_CAP, A_CAP, A_CAP, A_CAP,	/* @ABCDEFG */
+	A_CAP, A_CAP, A_CAP, A_CAP, A_CAP, A_CAP, A_CAP, A_CAP,	/* HIJKLMNO */
+	A_CAP, A_CAP, A_CAP, A_CAP, A_CAP, A_CAP, A_CAP, A_CAP,	/* PQRSTUVW */
+	A_CAP, A_CAP, A_CAP, PUNC, PUNC, PUNC, PUNC, PUNC,	/* XYZ[\]^_ */
+	PUNC, ALPHA, ALPHA, ALPHA, ALPHA, ALPHA, ALPHA, ALPHA,	/* `abcdefg */
+	ALPHA, ALPHA, ALPHA, ALPHA, ALPHA, ALPHA, ALPHA, ALPHA,	/* hijklmno */
+	ALPHA, ALPHA, ALPHA, ALPHA, ALPHA, ALPHA, ALPHA, ALPHA,	/* pqrstuvw */
+	ALPHA, ALPHA, ALPHA, PUNC, PUNC, PUNC, PUNC, 0,	/* xyz{|}~ */
+	B_CAPSYM, B_CAPSYM, B_SYM, B_SYM, B_SYM, B_SYM, B_SYM, /* 128-134 */
+	B_SYM,	/* 135 */
+	B_SYM, B_SYM, B_SYM, B_SYM, B_SYM, B_SYM, B_SYM, /* 136-142 */
+	B_CAPSYM,	/* 143 */
+	B_CAPSYM, B_CAPSYM, B_SYM, B_CAPSYM, B_SYM, B_SYM, B_SYM, /* 144-150 */
+	B_SYM,	/* 151 */
+	B_SYM, B_SYM, B_CAPSYM, B_CAPSYM, B_SYM, B_SYM, B_SYM, /*152-158 */
+	B_SYM,	/* 159 */
+	WDLM, B_SYM, B_SYM, B_SYM, B_SYM, B_SYM, B_CAPSYM, /* 160-166 */
+	B_SYM,	/* 167 */
+	B_SYM, B_SYM, B_SYM, B_SYM, B_SYM, B_SYM, B_SYM, B_SYM,	/* 168-175 */
+	B_SYM, B_SYM, B_SYM, B_SYM, B_SYM, B_SYM, B_SYM, B_SYM,	/* 176-183 */
+	B_SYM, B_SYM, B_SYM, B_SYM, B_SYM, B_SYM, B_SYM, B_SYM,	/* 184-191 */
+	A_CAP, A_CAP, A_CAP, A_CAP, A_CAP, A_CAP, A_CAP, A_CAP,	/* 192-199 */
+	A_CAP, A_CAP, A_CAP, A_CAP, A_CAP, A_CAP, A_CAP, A_CAP,	/* 200-207 */
+	A_CAP, A_CAP, A_CAP, A_CAP, A_CAP, A_CAP, A_CAP, B_SYM,	/* 208-215 */
+	A_CAP, A_CAP, A_CAP, A_CAP, A_CAP, A_CAP, A_CAP, ALPHA,	/* 216-223 */
+	ALPHA, ALPHA, ALPHA, ALPHA, ALPHA, ALPHA, ALPHA, ALPHA,	/* 224-231 */
+	ALPHA, ALPHA, ALPHA, ALPHA, ALPHA, ALPHA, ALPHA, ALPHA,	/* 232-239 */
+	ALPHA, ALPHA, ALPHA, ALPHA, ALPHA, ALPHA, ALPHA, B_SYM,	/* 240-247 */
+	ALPHA, ALPHA, ALPHA, ALPHA, ALPHA, ALPHA, ALPHA, ALPHA	/* 248-255 */
+};
+
+struct task_struct *speakup_task;
+struct bleep spk_unprocessed_sound;
+static int spk_keydown;
+static u16 spk_lastkey;
+static u_char spk_close_press, keymap_flags;
+static u_char last_keycode, this_speakup_key;
+static u_long last_spk_jiffy;
+
+struct st_spk_t *speakup_console[MAX_NR_CONSOLES];
+
+DEFINE_MUTEX(spk_mutex);
+
+static int keyboard_notifier_call(struct notifier_block *,
+				  unsigned long code, void *param);
+
+static struct notifier_block keyboard_notifier_block = {
+	.notifier_call = keyboard_notifier_call,
+};
+
+static int vt_notifier_call(struct notifier_block *,
+			    unsigned long code, void *param);
+
+static struct notifier_block vt_notifier_block = {
+	.notifier_call = vt_notifier_call,
+};
+
+static unsigned char get_attributes(struct vc_data *vc, u16 *pos)
+{
+	pos = screen_pos(vc, pos - (u16 *)vc->vc_origin, true);
+	return (scr_readw(pos) & ~vc->vc_hi_font_mask) >> 8;
+}
+
+static void speakup_date(struct vc_data *vc)
+{
+	spk_x = spk_cx = vc->state.x;
+	spk_y = spk_cy = vc->state.y;
+	spk_pos = spk_cp = vc->vc_pos;
+	spk_old_attr = spk_attr;
+	spk_attr = get_attributes(vc, (u_short *)spk_pos);
+}
+
+static void bleep(u_short val)
+{
+	static const short vals[] = {
+		350, 370, 392, 414, 440, 466, 491, 523, 554, 587, 619, 659
+	};
+	short freq;
+	int time = spk_bleep_time;
+
+	freq = vals[val % 12];
+	if (val > 11)
+		freq *= (1 << (val / 12));
+	spk_unprocessed_sound.freq = freq;
+	spk_unprocessed_sound.jiffies = msecs_to_jiffies(time);
+	spk_unprocessed_sound.active = 1;
+	/* We can only have 1 active sound at a time. */
+}
+
+static void speakup_shut_up(struct vc_data *vc)
+{
+	if (spk_killed)
+		return;
+	spk_shut_up |= 0x01;
+	spk_parked &= 0xfe;
+	speakup_date(vc);
+	if (synth)
+		spk_do_flush();
+}
+
+static void speech_kill(struct vc_data *vc)
+{
+	char val = synth->is_alive(synth);
+
+	if (val == 0)
+		return;
+
+	/* re-enables synth, if disabled */
+	if (val == 2 || spk_killed) {
+		/* dead */
+		spk_shut_up &= ~0x40;
+		synth_printf("%s\n", spk_msg_get(MSG_IAM_ALIVE));
+	} else {
+		synth_printf("%s\n", spk_msg_get(MSG_YOU_KILLED_SPEAKUP));
+		spk_shut_up |= 0x40;
+	}
+}
+
+static void speakup_off(struct vc_data *vc)
+{
+	if (spk_shut_up & 0x80) {
+		spk_shut_up &= 0x7f;
+		synth_printf("%s\n", spk_msg_get(MSG_HEY_THATS_BETTER));
+	} else {
+		spk_shut_up |= 0x80;
+		synth_printf("%s\n", spk_msg_get(MSG_YOU_TURNED_ME_OFF));
+	}
+	speakup_date(vc);
+}
+
+static void speakup_parked(struct vc_data *vc)
+{
+	if (spk_parked & 0x80) {
+		spk_parked = 0;
+		synth_printf("%s\n", spk_msg_get(MSG_UNPARKED));
+	} else {
+		spk_parked |= 0x80;
+		synth_printf("%s\n", spk_msg_get(MSG_PARKED));
+	}
+}
+
+static void speakup_cut(struct vc_data *vc)
+{
+	static const char err_buf[] = "set selection failed";
+	int ret;
+
+	if (!mark_cut_flag) {
+		mark_cut_flag = 1;
+		spk_xs = (u_short)spk_x;
+		spk_ys = (u_short)spk_y;
+		spk_sel_cons = vc;
+		synth_printf("%s\n", spk_msg_get(MSG_MARK));
+		return;
+	}
+	spk_xe = (u_short)spk_x;
+	spk_ye = (u_short)spk_y;
+	mark_cut_flag = 0;
+	synth_printf("%s\n", spk_msg_get(MSG_CUT));
+
+	ret = speakup_set_selection(tty);
+
+	switch (ret) {
+	case 0:
+		break;		/* no error */
+	case -EFAULT:
+		pr_warn("%sEFAULT\n", err_buf);
+		break;
+	case -EINVAL:
+		pr_warn("%sEINVAL\n", err_buf);
+		break;
+	case -ENOMEM:
+		pr_warn("%sENOMEM\n", err_buf);
+		break;
+	}
+}
+
+static void speakup_paste(struct vc_data *vc)
+{
+	if (mark_cut_flag) {
+		mark_cut_flag = 0;
+		synth_printf("%s\n", spk_msg_get(MSG_MARK_CLEARED));
+	} else {
+		synth_printf("%s\n", spk_msg_get(MSG_PASTE));
+		speakup_paste_selection(tty);
+	}
+}
+
+static void say_attributes(struct vc_data *vc)
+{
+	int fg = spk_attr & 0x0f;
+	int bg = spk_attr >> 4;
+
+	synth_printf("%s", spk_msg_get(MSG_COLORS_START + fg));
+	if (bg > 7) {
+		synth_printf(" %s ", spk_msg_get(MSG_ON_BLINKING));
+		bg -= 8;
+	} else {
+		synth_printf(" %s ", spk_msg_get(MSG_ON));
+	}
+	synth_printf("%s\n", spk_msg_get(MSG_COLORS_START + bg));
+}
+
+/* must be ordered same as edge_msgs in enum msg_index_t */
+enum edge {
+	edge_none = 0,
+	edge_top,
+	edge_bottom,
+	edge_left,
+	edge_right,
+	edge_quiet
+};
+
+static void announce_edge(struct vc_data *vc, enum edge msg_id)
+{
+	if (spk_bleeps & 1)
+		bleep(spk_y);
+	if ((spk_bleeps & 2) && (msg_id < edge_quiet))
+		synth_printf("%s\n",
+			     spk_msg_get(MSG_EDGE_MSGS_START + msg_id - 1));
+}
+
+static void speak_char(u16 ch)
+{
+	char *cp;
+	struct var_t *direct = spk_get_var(DIRECT);
+
+	if (ch >= 0x100 || (direct && direct->u.n.value)) {
+		if (ch < 0x100 && IS_CHAR(ch, B_CAP)) {
+			spk_pitch_shift++;
+			synth_printf("%s", spk_str_caps_start);
+		}
+		synth_putwc_s(ch);
+		if (ch < 0x100 && IS_CHAR(ch, B_CAP))
+			synth_printf("%s", spk_str_caps_stop);
+		return;
+	}
+
+	cp = spk_characters[ch];
+	if (!cp) {
+		pr_info("%s: cp == NULL!\n", __func__);
+		return;
+	}
+	if (IS_CHAR(ch, B_CAP)) {
+		spk_pitch_shift++;
+		synth_printf("%s %s %s",
+			     spk_str_caps_start, cp, spk_str_caps_stop);
+	} else {
+		if (*cp == '^') {
+			cp++;
+			synth_printf(" %s%s ", spk_msg_get(MSG_CTRL), cp);
+		} else {
+			synth_printf(" %s ", cp);
+		}
+	}
+}
+
+static u16 get_char(struct vc_data *vc, u16 *pos, u_char *attribs)
+{
+	u16 ch = ' ';
+
+	if (vc && pos) {
+		u16 w;
+		u16 c;
+
+		pos = screen_pos(vc, pos - (u16 *)vc->vc_origin, true);
+		w = scr_readw(pos);
+		c = w & 0xff;
+
+		if (w & vc->vc_hi_font_mask) {
+			w &= ~vc->vc_hi_font_mask;
+			c |= 0x100;
+		}
+
+		ch = inverse_translate(vc, c, true);
+		*attribs = (w & 0xff00) >> 8;
+	}
+	return ch;
+}
+
+static void say_char(struct vc_data *vc)
+{
+	u16 ch;
+
+	spk_old_attr = spk_attr;
+	ch = get_char(vc, (u_short *)spk_pos, &spk_attr);
+	if (spk_attr != spk_old_attr) {
+		if (spk_attrib_bleep & 1)
+			bleep(spk_y);
+		if (spk_attrib_bleep & 2)
+			say_attributes(vc);
+	}
+	speak_char(ch);
+}
+
+static void say_phonetic_char(struct vc_data *vc)
+{
+	u16 ch;
+
+	spk_old_attr = spk_attr;
+	ch = get_char(vc, (u_short *)spk_pos, &spk_attr);
+	if (ch <= 0x7f && isalpha(ch)) {
+		ch &= 0x1f;
+		synth_printf("%s\n", phonetic[--ch]);
+	} else {
+		if (ch < 0x100 && IS_CHAR(ch, B_NUM))
+			synth_printf("%s ", spk_msg_get(MSG_NUMBER));
+		speak_char(ch);
+	}
+}
+
+static void say_prev_char(struct vc_data *vc)
+{
+	spk_parked |= 0x01;
+	if (spk_x == 0) {
+		announce_edge(vc, edge_left);
+		return;
+	}
+	spk_x--;
+	spk_pos -= 2;
+	say_char(vc);
+}
+
+static void say_next_char(struct vc_data *vc)
+{
+	spk_parked |= 0x01;
+	if (spk_x == vc->vc_cols - 1) {
+		announce_edge(vc, edge_right);
+		return;
+	}
+	spk_x++;
+	spk_pos += 2;
+	say_char(vc);
+}
+
+/* get_word - will first check to see if the character under the
+ * reading cursor is a space and if spk_say_word_ctl is true it will
+ * return the word space.  If spk_say_word_ctl is not set it will check to
+ * see if there is a word starting on the next position to the right
+ * and return that word if it exists.  If it does not exist it will
+ * move left to the beginning of any previous word on the line or the
+ * beginning off the line whichever comes first..
+ */
+
+static u_long get_word(struct vc_data *vc)
+{
+	u_long cnt = 0, tmpx = spk_x, tmp_pos = spk_pos;
+	u16 ch;
+	u16 attr_ch;
+	u_char temp;
+
+	spk_old_attr = spk_attr;
+	ch = get_char(vc, (u_short *)tmp_pos, &temp);
+
+/* decided to take out the sayword if on a space (mis-information */
+	if (spk_say_word_ctl && ch == SPACE) {
+		*buf = '\0';
+		synth_printf("%s\n", spk_msg_get(MSG_SPACE));
+		return 0;
+	} else if (tmpx < vc->vc_cols - 2 &&
+		   (ch == SPACE || ch == 0 || (ch < 0x100 && IS_WDLM(ch))) &&
+		   get_char(vc, (u_short *)tmp_pos + 1, &temp) > SPACE) {
+		tmp_pos += 2;
+		tmpx++;
+	} else {
+		while (tmpx > 0) {
+			ch = get_char(vc, (u_short *)tmp_pos - 1, &temp);
+			if ((ch == SPACE || ch == 0 ||
+			     (ch < 0x100 && IS_WDLM(ch))) &&
+			    get_char(vc, (u_short *)tmp_pos, &temp) > SPACE)
+				break;
+			tmp_pos -= 2;
+			tmpx--;
+		}
+	}
+	attr_ch = get_char(vc, (u_short *)tmp_pos, &spk_attr);
+	buf[cnt++] = attr_ch;
+	while (tmpx < vc->vc_cols - 1 && cnt < ARRAY_SIZE(buf) - 1) {
+		tmp_pos += 2;
+		tmpx++;
+		ch = get_char(vc, (u_short *)tmp_pos, &temp);
+		if (ch == SPACE || ch == 0 ||
+		    (buf[cnt - 1] < 0x100 && IS_WDLM(buf[cnt - 1]) &&
+		     ch > SPACE))
+			break;
+		buf[cnt++] = ch;
+	}
+	buf[cnt] = '\0';
+	return cnt;
+}
+
+static void say_word(struct vc_data *vc)
+{
+	u_long cnt = get_word(vc);
+	u_short saved_punc_mask = spk_punc_mask;
+
+	if (cnt == 0)
+		return;
+	spk_punc_mask = PUNC;
+	buf[cnt++] = SPACE;
+	spkup_write(buf, cnt);
+	spk_punc_mask = saved_punc_mask;
+}
+
+static void say_prev_word(struct vc_data *vc)
+{
+	u_char temp;
+	u16 ch;
+	enum edge edge_said = edge_none;
+	u_short last_state = 0, state = 0;
+
+	spk_parked |= 0x01;
+
+	if (spk_x == 0) {
+		if (spk_y == 0) {
+			announce_edge(vc, edge_top);
+			return;
+		}
+		spk_y--;
+		spk_x = vc->vc_cols;
+		edge_said = edge_quiet;
+	}
+	while (1) {
+		if (spk_x == 0) {
+			if (spk_y == 0) {
+				edge_said = edge_top;
+				break;
+			}
+			if (edge_said != edge_quiet)
+				edge_said = edge_left;
+			if (state > 0)
+				break;
+			spk_y--;
+			spk_x = vc->vc_cols - 1;
+		} else {
+			spk_x--;
+		}
+		spk_pos -= 2;
+		ch = get_char(vc, (u_short *)spk_pos, &temp);
+		if (ch == SPACE || ch == 0)
+			state = 0;
+		else if (ch < 0x100 && IS_WDLM(ch))
+			state = 1;
+		else
+			state = 2;
+		if (state < last_state) {
+			spk_pos += 2;
+			spk_x++;
+			break;
+		}
+		last_state = state;
+	}
+	if (spk_x == 0 && edge_said == edge_quiet)
+		edge_said = edge_left;
+	if (edge_said > edge_none && edge_said < edge_quiet)
+		announce_edge(vc, edge_said);
+	say_word(vc);
+}
+
+static void say_next_word(struct vc_data *vc)
+{
+	u_char temp;
+	u16 ch;
+	enum edge edge_said = edge_none;
+	u_short last_state = 2, state = 0;
+
+	spk_parked |= 0x01;
+	if (spk_x == vc->vc_cols - 1 && spk_y == vc->vc_rows - 1) {
+		announce_edge(vc, edge_bottom);
+		return;
+	}
+	while (1) {
+		ch = get_char(vc, (u_short *)spk_pos, &temp);
+		if (ch == SPACE || ch == 0)
+			state = 0;
+		else if (ch < 0x100 && IS_WDLM(ch))
+			state = 1;
+		else
+			state = 2;
+		if (state > last_state)
+			break;
+		if (spk_x >= vc->vc_cols - 1) {
+			if (spk_y == vc->vc_rows - 1) {
+				edge_said = edge_bottom;
+				break;
+			}
+			state = 0;
+			spk_y++;
+			spk_x = 0;
+			edge_said = edge_right;
+		} else {
+			spk_x++;
+		}
+		spk_pos += 2;
+		last_state = state;
+	}
+	if (edge_said > edge_none)
+		announce_edge(vc, edge_said);
+	say_word(vc);
+}
+
+static void spell_word(struct vc_data *vc)
+{
+	static char const *delay_str[] = { "", ",", ".", ". .", ". . ." };
+	u16 *cp = buf;
+	char *cp1;
+	char *str_cap = spk_str_caps_stop;
+	char *last_cap = spk_str_caps_stop;
+	struct var_t *direct = spk_get_var(DIRECT);
+	u16 ch;
+
+	if (!get_word(vc))
+		return;
+	while ((ch = *cp)) {
+		if (cp != buf)
+			synth_printf(" %s ", delay_str[spk_spell_delay]);
+		/* FIXME: Non-latin1 considered as lower case */
+		if (ch < 0x100 && IS_CHAR(ch, B_CAP)) {
+			str_cap = spk_str_caps_start;
+			if (*spk_str_caps_stop)
+				spk_pitch_shift++;
+			else	/* synth has no pitch */
+				last_cap = spk_str_caps_stop;
+		} else {
+			str_cap = spk_str_caps_stop;
+		}
+		if (str_cap != last_cap) {
+			synth_printf("%s", str_cap);
+			last_cap = str_cap;
+		}
+		if (ch >= 0x100 || (direct && direct->u.n.value)) {
+			synth_putwc_s(ch);
+		} else if (this_speakup_key == SPELL_PHONETIC &&
+		    ch <= 0x7f && isalpha(ch)) {
+			ch &= 0x1f;
+			cp1 = phonetic[--ch];
+			synth_printf("%s", cp1);
+		} else {
+			cp1 = spk_characters[ch];
+			if (*cp1 == '^') {
+				synth_printf("%s", spk_msg_get(MSG_CTRL));
+				cp1++;
+			}
+			synth_printf("%s", cp1);
+		}
+		cp++;
+	}
+	if (str_cap != spk_str_caps_stop)
+		synth_printf("%s", spk_str_caps_stop);
+}
+
+static int get_line(struct vc_data *vc)
+{
+	u_long tmp = spk_pos - (spk_x * 2);
+	int i = 0;
+	u_char tmp2;
+
+	spk_old_attr = spk_attr;
+	spk_attr = get_attributes(vc, (u_short *)spk_pos);
+	for (i = 0; i < vc->vc_cols; i++) {
+		buf[i] = get_char(vc, (u_short *)tmp, &tmp2);
+		tmp += 2;
+	}
+	for (--i; i >= 0; i--)
+		if (buf[i] != SPACE)
+			break;
+	return ++i;
+}
+
+static void say_line(struct vc_data *vc)
+{
+	int i = get_line(vc);
+	u16 *cp;
+	u_short saved_punc_mask = spk_punc_mask;
+
+	if (i == 0) {
+		synth_printf("%s\n", spk_msg_get(MSG_BLANK));
+		return;
+	}
+	buf[i++] = '\n';
+	if (this_speakup_key == SAY_LINE_INDENT) {
+		cp = buf;
+		while (*cp == SPACE)
+			cp++;
+		synth_printf("%zd, ", (cp - buf) + 1);
+	}
+	spk_punc_mask = spk_punc_masks[spk_reading_punc];
+	spkup_write(buf, i);
+	spk_punc_mask = saved_punc_mask;
+}
+
+static void say_prev_line(struct vc_data *vc)
+{
+	spk_parked |= 0x01;
+	if (spk_y == 0) {
+		announce_edge(vc, edge_top);
+		return;
+	}
+	spk_y--;
+	spk_pos -= vc->vc_size_row;
+	say_line(vc);
+}
+
+static void say_next_line(struct vc_data *vc)
+{
+	spk_parked |= 0x01;
+	if (spk_y == vc->vc_rows - 1) {
+		announce_edge(vc, edge_bottom);
+		return;
+	}
+	spk_y++;
+	spk_pos += vc->vc_size_row;
+	say_line(vc);
+}
+
+static int say_from_to(struct vc_data *vc, u_long from, u_long to,
+		       int read_punc)
+{
+	int i = 0;
+	u_char tmp;
+	u_short saved_punc_mask = spk_punc_mask;
+
+	spk_old_attr = spk_attr;
+	spk_attr = get_attributes(vc, (u_short *)from);
+	while (from < to) {
+		buf[i++] = get_char(vc, (u_short *)from, &tmp);
+		from += 2;
+		if (i >= vc->vc_size_row)
+			break;
+	}
+	for (--i; i >= 0; i--)
+		if (buf[i] != SPACE)
+			break;
+	buf[++i] = SPACE;
+	buf[++i] = '\0';
+	if (i < 1)
+		return i;
+	if (read_punc)
+		spk_punc_mask = spk_punc_info[spk_reading_punc].mask;
+	spkup_write(buf, i);
+	if (read_punc)
+		spk_punc_mask = saved_punc_mask;
+	return i - 1;
+}
+
+static void say_line_from_to(struct vc_data *vc, u_long from, u_long to,
+			     int read_punc)
+{
+	u_long start = vc->vc_origin + (spk_y * vc->vc_size_row);
+	u_long end = start + (to * 2);
+
+	start += from * 2;
+	if (say_from_to(vc, start, end, read_punc) <= 0)
+		if (cursor_track != read_all_mode)
+			synth_printf("%s\n", spk_msg_get(MSG_BLANK));
+}
+
+/* Sentence Reading Commands */
+
+static int currsentence;
+static int numsentences[2];
+static u16 *sentbufend[2];
+static u16 *sentmarks[2][10];
+static int currbuf;
+static int bn;
+static u16 sentbuf[2][256];
+
+static int say_sentence_num(int num, int prev)
+{
+	bn = currbuf;
+	currsentence = num + 1;
+	if (prev && --bn == -1)
+		bn = 1;
+
+	if (num > numsentences[bn])
+		return 0;
+
+	spkup_write(sentmarks[bn][num], sentbufend[bn] - sentmarks[bn][num]);
+	return 1;
+}
+
+static int get_sentence_buf(struct vc_data *vc, int read_punc)
+{
+	u_long start, end;
+	int i, bn;
+	u_char tmp;
+
+	currbuf++;
+	if (currbuf == 2)
+		currbuf = 0;
+	bn = currbuf;
+	start = vc->vc_origin + ((spk_y) * vc->vc_size_row);
+	end = vc->vc_origin + ((spk_y) * vc->vc_size_row) + vc->vc_cols * 2;
+
+	numsentences[bn] = 0;
+	sentmarks[bn][0] = &sentbuf[bn][0];
+	i = 0;
+	spk_old_attr = spk_attr;
+	spk_attr = get_attributes(vc, (u_short *)start);
+
+	while (start < end) {
+		sentbuf[bn][i] = get_char(vc, (u_short *)start, &tmp);
+		if (i > 0) {
+			if (sentbuf[bn][i] == SPACE &&
+			    sentbuf[bn][i - 1] == '.' &&
+			    numsentences[bn] < 9) {
+				/* Sentence Marker */
+				numsentences[bn]++;
+				sentmarks[bn][numsentences[bn]] =
+				    &sentbuf[bn][i];
+			}
+		}
+		i++;
+		start += 2;
+		if (i >= vc->vc_size_row)
+			break;
+	}
+
+	for (--i; i >= 0; i--)
+		if (sentbuf[bn][i] != SPACE)
+			break;
+
+	if (i < 1)
+		return -1;
+
+	sentbuf[bn][++i] = SPACE;
+	sentbuf[bn][++i] = '\0';
+
+	sentbufend[bn] = &sentbuf[bn][i];
+	return numsentences[bn];
+}
+
+static void say_screen_from_to(struct vc_data *vc, u_long from, u_long to)
+{
+	u_long start = vc->vc_origin, end;
+
+	if (from > 0)
+		start += from * vc->vc_size_row;
+	if (to > vc->vc_rows)
+		to = vc->vc_rows;
+	end = vc->vc_origin + (to * vc->vc_size_row);
+	for (from = start; from < end; from = to) {
+		to = from + vc->vc_size_row;
+		say_from_to(vc, from, to, 1);
+	}
+}
+
+static void say_screen(struct vc_data *vc)
+{
+	say_screen_from_to(vc, 0, vc->vc_rows);
+}
+
+static void speakup_win_say(struct vc_data *vc)
+{
+	u_long start, end, from, to;
+
+	if (win_start < 2) {
+		synth_printf("%s\n", spk_msg_get(MSG_NO_WINDOW));
+		return;
+	}
+	start = vc->vc_origin + (win_top * vc->vc_size_row);
+	end = vc->vc_origin + (win_bottom * vc->vc_size_row);
+	while (start <= end) {
+		from = start + (win_left * 2);
+		to = start + (win_right * 2);
+		say_from_to(vc, from, to, 1);
+		start += vc->vc_size_row;
+	}
+}
+
+static void top_edge(struct vc_data *vc)
+{
+	spk_parked |= 0x01;
+	spk_pos = vc->vc_origin + 2 * spk_x;
+	spk_y = 0;
+	say_line(vc);
+}
+
+static void bottom_edge(struct vc_data *vc)
+{
+	spk_parked |= 0x01;
+	spk_pos += (vc->vc_rows - spk_y - 1) * vc->vc_size_row;
+	spk_y = vc->vc_rows - 1;
+	say_line(vc);
+}
+
+static void left_edge(struct vc_data *vc)
+{
+	spk_parked |= 0x01;
+	spk_pos -= spk_x * 2;
+	spk_x = 0;
+	say_char(vc);
+}
+
+static void right_edge(struct vc_data *vc)
+{
+	spk_parked |= 0x01;
+	spk_pos += (vc->vc_cols - spk_x - 1) * 2;
+	spk_x = vc->vc_cols - 1;
+	say_char(vc);
+}
+
+static void say_first_char(struct vc_data *vc)
+{
+	int i, len = get_line(vc);
+	u16 ch;
+
+	spk_parked |= 0x01;
+	if (len == 0) {
+		synth_printf("%s\n", spk_msg_get(MSG_BLANK));
+		return;
+	}
+	for (i = 0; i < len; i++)
+		if (buf[i] != SPACE)
+			break;
+	ch = buf[i];
+	spk_pos -= (spk_x - i) * 2;
+	spk_x = i;
+	synth_printf("%d, ", ++i);
+	speak_char(ch);
+}
+
+static void say_last_char(struct vc_data *vc)
+{
+	int len = get_line(vc);
+	u16 ch;
+
+	spk_parked |= 0x01;
+	if (len == 0) {
+		synth_printf("%s\n", spk_msg_get(MSG_BLANK));
+		return;
+	}
+	ch = buf[--len];
+	spk_pos -= (spk_x - len) * 2;
+	spk_x = len;
+	synth_printf("%d, ", ++len);
+	speak_char(ch);
+}
+
+static void say_position(struct vc_data *vc)
+{
+	synth_printf(spk_msg_get(MSG_POS_INFO), spk_y + 1, spk_x + 1,
+		     vc->vc_num + 1);
+	synth_printf("\n");
+}
+
+/* Added by brianb */
+static void say_char_num(struct vc_data *vc)
+{
+	u_char tmp;
+	u16 ch = get_char(vc, (u_short *)spk_pos, &tmp);
+
+	synth_printf(spk_msg_get(MSG_CHAR_INFO), ch, ch);
+}
+
+/* these are stub functions to keep keyboard.c happy. */
+
+static void say_from_top(struct vc_data *vc)
+{
+	say_screen_from_to(vc, 0, spk_y);
+}
+
+static void say_to_bottom(struct vc_data *vc)
+{
+	say_screen_from_to(vc, spk_y, vc->vc_rows);
+}
+
+static void say_from_left(struct vc_data *vc)
+{
+	say_line_from_to(vc, 0, spk_x, 1);
+}
+
+static void say_to_right(struct vc_data *vc)
+{
+	say_line_from_to(vc, spk_x, vc->vc_cols, 1);
+}
+
+/* end of stub functions. */
+
+static void spkup_write(const u16 *in_buf, int count)
+{
+	static int rep_count;
+	static u16 ch = '\0', old_ch = '\0';
+	static u_short char_type, last_type;
+	int in_count = count;
+
+	spk_keydown = 0;
+	while (count--) {
+		if (cursor_track == read_all_mode) {
+			/* Insert Sentence Index */
+			if ((in_buf == sentmarks[bn][currsentence]) &&
+			    (currsentence <= numsentences[bn]))
+				synth_insert_next_index(currsentence++);
+		}
+		ch = *in_buf++;
+		if (ch < 0x100)
+			char_type = spk_chartab[ch];
+		else
+			char_type = ALPHA;
+		if (ch == old_ch && !(char_type & B_NUM)) {
+			if (++rep_count > 2)
+				continue;
+		} else {
+			if ((last_type & CH_RPT) && rep_count > 2) {
+				synth_printf(" ");
+				synth_printf(spk_msg_get(MSG_REPEAT_DESC),
+					     ++rep_count);
+				synth_printf(" ");
+			}
+			rep_count = 0;
+		}
+		if (ch == spk_lastkey) {
+			rep_count = 0;
+			if (spk_key_echo == 1 && ch >= MINECHOCHAR)
+				speak_char(ch);
+		} else if (char_type & B_ALPHA) {
+			if ((synth_flags & SF_DEC) && (last_type & PUNC))
+				synth_buffer_add(SPACE);
+			synth_putwc_s(ch);
+		} else if (char_type & B_NUM) {
+			rep_count = 0;
+			synth_putwc_s(ch);
+		} else if (char_type & spk_punc_mask) {
+			speak_char(ch);
+			char_type &= ~PUNC;	/* for dec nospell processing */
+		} else if (char_type & SYNTH_OK) {
+			/* these are usually puncts like . and , which synth
+			 * needs for expression.
+			 * suppress multiple to get rid of long pauses and
+			 * clear repeat count
+			 * so if someone has
+			 * repeats on you don't get nothing repeated count
+			 */
+			if (ch != old_ch)
+				synth_putwc_s(ch);
+			else
+				rep_count = 0;
+		} else {
+/* send space and record position, if next is num overwrite space */
+			if (old_ch != ch)
+				synth_buffer_add(SPACE);
+			else
+				rep_count = 0;
+		}
+		old_ch = ch;
+		last_type = char_type;
+	}
+	spk_lastkey = 0;
+	if (in_count > 2 && rep_count > 2) {
+		if (last_type & CH_RPT) {
+			synth_printf(" ");
+			synth_printf(spk_msg_get(MSG_REPEAT_DESC2),
+				     ++rep_count);
+			synth_printf(" ");
+		}
+		rep_count = 0;
+	}
+}
+
+static const int NUM_CTL_LABELS = (MSG_CTL_END - MSG_CTL_START + 1);
+
+static void read_all_doc(struct vc_data *vc);
+static void cursor_done(struct timer_list *unused);
+static DEFINE_TIMER(cursor_timer, cursor_done);
+
+static void do_handle_shift(struct vc_data *vc, u_char value, char up_flag)
+{
+	unsigned long flags;
+
+	if (!synth || up_flag || spk_killed)
+		return;
+	spin_lock_irqsave(&speakup_info.spinlock, flags);
+	if (cursor_track == read_all_mode) {
+		switch (value) {
+		case KVAL(K_SHIFT):
+			timer_delete(&cursor_timer);
+			spk_shut_up &= 0xfe;
+			spk_do_flush();
+			read_all_doc(vc);
+			break;
+		case KVAL(K_CTRL):
+			timer_delete(&cursor_timer);
+			cursor_track = prev_cursor_track;
+			spk_shut_up &= 0xfe;
+			spk_do_flush();
+			break;
+		}
+	} else {
+		spk_shut_up &= 0xfe;
+		spk_do_flush();
+	}
+	if (spk_say_ctrl && value < NUM_CTL_LABELS)
+		synth_printf("%s", spk_msg_get(MSG_CTL_START + value));
+	spin_unlock_irqrestore(&speakup_info.spinlock, flags);
+}
+
+static void do_handle_latin(struct vc_data *vc, u_char value, char up_flag)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&speakup_info.spinlock, flags);
+	if (up_flag) {
+		spk_lastkey = 0;
+		spk_keydown = 0;
+		spin_unlock_irqrestore(&speakup_info.spinlock, flags);
+		return;
+	}
+	if (!synth || spk_killed) {
+		spin_unlock_irqrestore(&speakup_info.spinlock, flags);
+		return;
+	}
+	spk_shut_up &= 0xfe;
+	spk_lastkey = value;
+	spk_keydown++;
+	spk_parked &= 0xfe;
+	if (spk_key_echo == 2 && value >= MINECHOCHAR)
+		speak_char(value);
+	spin_unlock_irqrestore(&speakup_info.spinlock, flags);
+}
+
+int spk_set_key_info(const u_char *key_info, u_char *k_buffer)
+{
+	int i = 0, states, key_data_len;
+	const u_char *cp = key_info;
+	u_char *cp1 = k_buffer;
+	u_char ch, version, num_keys;
+
+	version = *cp++;
+	if (version != KEY_MAP_VER) {
+		pr_debug("version found %d should be %d\n",
+			 version, KEY_MAP_VER);
+		return -EINVAL;
+	}
+	num_keys = *cp;
+	states = (int)cp[1];
+	key_data_len = (states + 1) * (num_keys + 1);
+	if (key_data_len + SHIFT_TBL_SIZE + 4 >= sizeof(spk_key_buf)) {
+		pr_debug("too many key_infos (%d over %u)\n",
+			 key_data_len + SHIFT_TBL_SIZE + 4,
+			 (unsigned int)(sizeof(spk_key_buf)));
+		return -EINVAL;
+	}
+	memset(k_buffer, 0, SHIFT_TBL_SIZE);
+	memset(spk_our_keys, 0, sizeof(spk_our_keys));
+	spk_shift_table = k_buffer;
+	spk_our_keys[0] = spk_shift_table;
+	cp1 += SHIFT_TBL_SIZE;
+	memcpy(cp1, cp, key_data_len + 3);
+	/* get num_keys, states and data */
+	cp1 += 2;		/* now pointing at shift states */
+	for (i = 1; i <= states; i++) {
+		ch = *cp1++;
+		if (ch >= SHIFT_TBL_SIZE) {
+			pr_debug("(%d) not valid shift state (max_allowed = %d)\n",
+				 ch, SHIFT_TBL_SIZE);
+			return -EINVAL;
+		}
+		spk_shift_table[ch] = i;
+	}
+	keymap_flags = *cp1++;
+	while ((ch = *cp1)) {
+		if (ch >= MAX_KEY) {
+			pr_debug("(%d), not valid key, (max_allowed = %d)\n",
+				 ch, MAX_KEY);
+			return -EINVAL;
+		}
+		spk_our_keys[ch] = cp1;
+		cp1 += states + 1;
+	}
+	return 0;
+}
+
+enum spk_vars_id {
+	BELL_POS_ID = 0, SPELL_DELAY_ID, ATTRIB_BLEEP_ID,
+	BLEEPS_ID, BLEEP_TIME_ID, PUNC_LEVEL_ID,
+	READING_PUNC_ID, CURSOR_TIME_ID, SAY_CONTROL_ID,
+	SAY_WORD_CTL_ID, NO_INTERRUPT_ID, KEY_ECHO_ID,
+	CUR_PHONETIC_ID, V_LAST_VAR_ID, NB_ID
+};
+
+static struct var_t spk_vars[NB_ID] = {
+	/* bell must be first to set high limit */
+	[BELL_POS_ID] = { BELL_POS, .u.n = {NULL, 0, 0, 0, 0, 0, NULL} },
+	[SPELL_DELAY_ID] = { SPELL_DELAY, .u.n = {NULL, 0, 0, 4, 0, 0, NULL} },
+	[ATTRIB_BLEEP_ID] = { ATTRIB_BLEEP, .u.n = {NULL, 1, 0, 3, 0, 0, NULL} },
+	[BLEEPS_ID] = { BLEEPS, .u.n = {NULL, 3, 0, 3, 0, 0, NULL} },
+	[BLEEP_TIME_ID] = { BLEEP_TIME, .u.n = {NULL, 30, 1, 200, 0, 0, NULL} },
+	[PUNC_LEVEL_ID] = { PUNC_LEVEL, .u.n = {NULL, 1, 0, 4, 0, 0, NULL} },
+	[READING_PUNC_ID] = { READING_PUNC, .u.n = {NULL, 1, 0, 4, 0, 0, NULL} },
+	[CURSOR_TIME_ID] = { CURSOR_TIME, .u.n = {NULL, 120, 50, 600, 0, 0, NULL} },
+	[SAY_CONTROL_ID] = { SAY_CONTROL, TOGGLE_0},
+	[SAY_WORD_CTL_ID] = {SAY_WORD_CTL, TOGGLE_0},
+	[NO_INTERRUPT_ID] = { NO_INTERRUPT, TOGGLE_0},
+	[KEY_ECHO_ID] = { KEY_ECHO, .u.n = {NULL, 1, 0, 2, 0, 0, NULL} },
+	[CUR_PHONETIC_ID] = { CUR_PHONETIC, .u.n = {NULL, 0, 0, 1, 0, 0, NULL} },
+	V_LAST_VAR
+};
+
+static void toggle_cursoring(struct vc_data *vc)
+{
+	if (cursor_track == read_all_mode)
+		cursor_track = prev_cursor_track;
+	if (++cursor_track >= CT_Max)
+		cursor_track = 0;
+	synth_printf("%s\n", spk_msg_get(MSG_CURSOR_MSGS_START + cursor_track));
+}
+
+void spk_reset_default_chars(void)
+{
+	int i;
+
+	/* First, free any non-default */
+	for (i = 0; i < 256; i++) {
+		if (spk_characters[i] &&
+		    (spk_characters[i] != spk_default_chars[i]))
+			kfree(spk_characters[i]);
+	}
+
+	memcpy(spk_characters, spk_default_chars, sizeof(spk_default_chars));
+}
+
+void spk_reset_default_chartab(void)
+{
+	memcpy(spk_chartab, default_chartab, sizeof(default_chartab));
+}
+
+static const struct st_bits_data *pb_edit;
+
+static int edit_bits(struct vc_data *vc, u_char type, u_char ch, u_short key)
+{
+	short mask = pb_edit->mask, ch_type = spk_chartab[ch];
+
+	if (type != KT_LATIN || (ch_type & B_NUM) || ch < SPACE)
+		return -1;
+	if (ch == SPACE) {
+		synth_printf("%s\n", spk_msg_get(MSG_EDIT_DONE));
+		spk_special_handler = NULL;
+		return 1;
+	}
+	if (mask < PUNC && !(ch_type & PUNC))
+		return -1;
+	spk_chartab[ch] ^= mask;
+	speak_char(ch);
+	synth_printf(" %s\n",
+		     (spk_chartab[ch] & mask) ? spk_msg_get(MSG_ON) :
+		     spk_msg_get(MSG_OFF));
+	return 1;
+}
+
+/* Allocation concurrency is protected by the console semaphore */
+static int speakup_allocate(struct vc_data *vc, gfp_t gfp_flags)
+{
+	int vc_num;
+
+	vc_num = vc->vc_num;
+	if (!speakup_console[vc_num]) {
+		speakup_console[vc_num] = kzalloc(sizeof(*speakup_console[0]),
+						  gfp_flags);
+		if (!speakup_console[vc_num])
+			return -ENOMEM;
+		speakup_date(vc);
+	} else if (!spk_parked) {
+		speakup_date(vc);
+	}
+
+	return 0;
+}
+
+static void speakup_deallocate(struct vc_data *vc)
+{
+	int vc_num;
+
+	vc_num = vc->vc_num;
+	kfree(speakup_console[vc_num]);
+	speakup_console[vc_num] = NULL;
+}
+
+enum read_all_command {
+	RA_NEXT_SENT = KVAL(K_DOWN)+1,
+	RA_PREV_LINE = KVAL(K_LEFT)+1,
+	RA_NEXT_LINE = KVAL(K_RIGHT)+1,
+	RA_PREV_SENT = KVAL(K_UP)+1,
+	RA_DOWN_ARROW,
+	RA_TIMER,
+	RA_FIND_NEXT_SENT,
+	RA_FIND_PREV_SENT,
+};
+
+static u_char is_cursor;
+static u_long old_cursor_pos, old_cursor_x, old_cursor_y;
+static int cursor_con;
+
+static void reset_highlight_buffers(struct vc_data *);
+
+static enum read_all_command read_all_key;
+
+static int in_keyboard_notifier;
+
+static void start_read_all_timer(struct vc_data *vc, enum read_all_command command);
+
+static void kbd_fakekey2(struct vc_data *vc, enum read_all_command command)
+{
+	timer_delete(&cursor_timer);
+	speakup_fake_down_arrow();
+	start_read_all_timer(vc, command);
+}
+
+static void read_all_doc(struct vc_data *vc)
+{
+	if ((vc->vc_num != fg_console) || !synth || spk_shut_up)
+		return;
+	if (!synth_supports_indexing())
+		return;
+	if (cursor_track != read_all_mode)
+		prev_cursor_track = cursor_track;
+	cursor_track = read_all_mode;
+	spk_reset_index_count(0);
+	if (get_sentence_buf(vc, 0) == -1) {
+		timer_delete(&cursor_timer);
+		if (!in_keyboard_notifier)
+			speakup_fake_down_arrow();
+		start_read_all_timer(vc, RA_DOWN_ARROW);
+	} else {
+		say_sentence_num(0, 0);
+		synth_insert_next_index(0);
+		start_read_all_timer(vc, RA_TIMER);
+	}
+}
+
+static void stop_read_all(struct vc_data *vc)
+{
+	timer_delete(&cursor_timer);
+	cursor_track = prev_cursor_track;
+	spk_shut_up &= 0xfe;
+	spk_do_flush();
+}
+
+static void start_read_all_timer(struct vc_data *vc, enum read_all_command command)
+{
+	struct var_t *cursor_timeout;
+
+	cursor_con = vc->vc_num;
+	read_all_key = command;
+	cursor_timeout = spk_get_var(CURSOR_TIME);
+	mod_timer(&cursor_timer,
+		  jiffies + msecs_to_jiffies(cursor_timeout->u.n.value));
+}
+
+static void handle_cursor_read_all(struct vc_data *vc, enum read_all_command command)
+{
+	int indcount, sentcount, rv, sn;
+
+	switch (command) {
+	case RA_NEXT_SENT:
+		/* Get Current Sentence */
+		spk_get_index_count(&indcount, &sentcount);
+		/*printk("%d %d  ", indcount, sentcount); */
+		spk_reset_index_count(sentcount + 1);
+		if (indcount == 1) {
+			if (!say_sentence_num(sentcount + 1, 0)) {
+				kbd_fakekey2(vc, RA_FIND_NEXT_SENT);
+				return;
+			}
+			synth_insert_next_index(0);
+		} else {
+			sn = 0;
+			if (!say_sentence_num(sentcount + 1, 1)) {
+				sn = 1;
+				spk_reset_index_count(sn);
+			} else {
+				synth_insert_next_index(0);
+			}
+			if (!say_sentence_num(sn, 0)) {
+				kbd_fakekey2(vc, RA_FIND_NEXT_SENT);
+				return;
+			}
+			synth_insert_next_index(0);
+		}
+		start_read_all_timer(vc, RA_TIMER);
+		break;
+	case RA_PREV_SENT:
+		break;
+	case RA_NEXT_LINE:
+		read_all_doc(vc);
+		break;
+	case RA_PREV_LINE:
+		break;
+	case RA_DOWN_ARROW:
+		if (get_sentence_buf(vc, 0) == -1) {
+			kbd_fakekey2(vc, RA_DOWN_ARROW);
+		} else {
+			say_sentence_num(0, 0);
+			synth_insert_next_index(0);
+			start_read_all_timer(vc, RA_TIMER);
+		}
+		break;
+	case RA_FIND_NEXT_SENT:
+		rv = get_sentence_buf(vc, 0);
+		if (rv == -1)
+			read_all_doc(vc);
+		if (rv == 0) {
+			kbd_fakekey2(vc, RA_FIND_NEXT_SENT);
+		} else {
+			say_sentence_num(1, 0);
+			synth_insert_next_index(0);
+			start_read_all_timer(vc, RA_TIMER);
+		}
+		break;
+	case RA_FIND_PREV_SENT:
+		break;
+	case RA_TIMER:
+		spk_get_index_count(&indcount, &sentcount);
+		if (indcount < 2)
+			kbd_fakekey2(vc, RA_DOWN_ARROW);
+		else
+			start_read_all_timer(vc, RA_TIMER);
+		break;
+	}
+}
+
+static int pre_handle_cursor(struct vc_data *vc, u_char value, char up_flag)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&speakup_info.spinlock, flags);
+	if (cursor_track == read_all_mode) {
+		spk_parked &= 0xfe;
+		if (!synth || up_flag || spk_shut_up) {
+			spin_unlock_irqrestore(&speakup_info.spinlock, flags);
+			return NOTIFY_STOP;
+		}
+		timer_delete(&cursor_timer);
+		spk_shut_up &= 0xfe;
+		spk_do_flush();
+		start_read_all_timer(vc, value + 1);
+		spin_unlock_irqrestore(&speakup_info.spinlock, flags);
+		return NOTIFY_STOP;
+	}
+	spin_unlock_irqrestore(&speakup_info.spinlock, flags);
+	return NOTIFY_OK;
+}
+
+static void do_handle_cursor(struct vc_data *vc, u_char value, char up_flag)
+{
+	unsigned long flags;
+	struct var_t *cursor_timeout;
+
+	spin_lock_irqsave(&speakup_info.spinlock, flags);
+	spk_parked &= 0xfe;
+	if (!synth || up_flag || spk_shut_up || cursor_track == CT_Off) {
+		spin_unlock_irqrestore(&speakup_info.spinlock, flags);
+		return;
+	}
+	spk_shut_up &= 0xfe;
+	if (spk_no_intr)
+		spk_do_flush();
+/* the key press flushes if !no_inter but we want to flush on cursor
+ * moves regardless of no_inter state
+ */
+	is_cursor = value + 1;
+	old_cursor_pos = vc->vc_pos;
+	old_cursor_x = vc->state.x;
+	old_cursor_y = vc->state.y;
+	speakup_console[vc->vc_num]->ht.cy = vc->state.y;
+	cursor_con = vc->vc_num;
+	if (cursor_track == CT_Highlight)
+		reset_highlight_buffers(vc);
+	cursor_timeout = spk_get_var(CURSOR_TIME);
+	mod_timer(&cursor_timer,
+		  jiffies + msecs_to_jiffies(cursor_timeout->u.n.value));
+	spin_unlock_irqrestore(&speakup_info.spinlock, flags);
+}
+
+static void update_color_buffer(struct vc_data *vc, const u16 *ic, int len)
+{
+	int i, bi, hi;
+	int vc_num = vc->vc_num;
+
+	bi = (vc->vc_attr & 0x70) >> 4;
+	hi = speakup_console[vc_num]->ht.highsize[bi];
+
+	i = 0;
+	if (speakup_console[vc_num]->ht.highsize[bi] == 0) {
+		speakup_console[vc_num]->ht.rpos[bi] = vc->vc_pos;
+		speakup_console[vc_num]->ht.rx[bi] = vc->state.x;
+		speakup_console[vc_num]->ht.ry[bi] = vc->state.y;
+	}
+	while ((hi < COLOR_BUFFER_SIZE) && (i < len)) {
+		if (ic[i] > 32) {
+			speakup_console[vc_num]->ht.highbuf[bi][hi] = ic[i];
+			hi++;
+		} else if ((ic[i] == 32) && (hi != 0)) {
+			if (speakup_console[vc_num]->ht.highbuf[bi][hi - 1] !=
+			    32) {
+				speakup_console[vc_num]->ht.highbuf[bi][hi] =
+				    ic[i];
+				hi++;
+			}
+		}
+		i++;
+	}
+	speakup_console[vc_num]->ht.highsize[bi] = hi;
+}
+
+static void reset_highlight_buffers(struct vc_data *vc)
+{
+	int i;
+	int vc_num = vc->vc_num;
+
+	for (i = 0; i < 8; i++)
+		speakup_console[vc_num]->ht.highsize[i] = 0;
+}
+
+static int count_highlight_color(struct vc_data *vc)
+{
+	int i, bg;
+	int cc;
+	int vc_num = vc->vc_num;
+	u16 ch;
+	u16 *start = (u16 *)vc->vc_origin;
+
+	for (i = 0; i < 8; i++)
+		speakup_console[vc_num]->ht.bgcount[i] = 0;
+
+	for (i = 0; i < vc->vc_rows; i++) {
+		u16 *end = start + vc->vc_cols * 2;
+		u16 *ptr;
+
+		for (ptr = start; ptr < end; ptr++) {
+			ch = get_attributes(vc, ptr);
+			bg = (ch & 0x70) >> 4;
+			speakup_console[vc_num]->ht.bgcount[bg]++;
+		}
+		start += vc->vc_size_row;
+	}
+
+	cc = 0;
+	for (i = 0; i < 8; i++)
+		if (speakup_console[vc_num]->ht.bgcount[i] > 0)
+			cc++;
+	return cc;
+}
+
+static int get_highlight_color(struct vc_data *vc)
+{
+	int i, j;
+	unsigned int cptr[8];
+	int vc_num = vc->vc_num;
+
+	for (i = 0; i < 8; i++)
+		cptr[i] = i;
+
+	for (i = 0; i < 7; i++)
+		for (j = i + 1; j < 8; j++)
+			if (speakup_console[vc_num]->ht.bgcount[cptr[i]] >
+			    speakup_console[vc_num]->ht.bgcount[cptr[j]])
+				swap(cptr[i], cptr[j]);
+
+	for (i = 0; i < 8; i++)
+		if (speakup_console[vc_num]->ht.bgcount[cptr[i]] != 0)
+			if (speakup_console[vc_num]->ht.highsize[cptr[i]] > 0)
+				return cptr[i];
+	return -1;
+}
+
+static int speak_highlight(struct vc_data *vc)
+{
+	int hc, d;
+	int vc_num = vc->vc_num;
+
+	if (count_highlight_color(vc) == 1)
+		return 0;
+	hc = get_highlight_color(vc);
+	if (hc != -1) {
+		d = vc->state.y - speakup_console[vc_num]->ht.cy;
+		if ((d == 1) || (d == -1))
+			if (speakup_console[vc_num]->ht.ry[hc] != vc->state.y)
+				return 0;
+		spk_parked |= 0x01;
+		spk_do_flush();
+		spkup_write(speakup_console[vc_num]->ht.highbuf[hc],
+			    speakup_console[vc_num]->ht.highsize[hc]);
+		spk_pos = spk_cp = speakup_console[vc_num]->ht.rpos[hc];
+		spk_x = spk_cx = speakup_console[vc_num]->ht.rx[hc];
+		spk_y = spk_cy = speakup_console[vc_num]->ht.ry[hc];
+		return 1;
+	}
+	return 0;
+}
+
+static void cursor_done(struct timer_list *unused)
+{
+	struct vc_data *vc = vc_cons[cursor_con].d;
+	unsigned long flags;
+
+	timer_delete(&cursor_timer);
+	spin_lock_irqsave(&speakup_info.spinlock, flags);
+	if (cursor_con != fg_console) {
+		is_cursor = 0;
+		goto out;
+	}
+	speakup_date(vc);
+	if (win_enabled) {
+		if (vc->state.x >= win_left && vc->state.x <= win_right &&
+		    vc->state.y >= win_top && vc->state.y <= win_bottom) {
+			spk_keydown = 0;
+			is_cursor = 0;
+			goto out;
+		}
+	}
+	if (cursor_track == read_all_mode) {
+		handle_cursor_read_all(vc, read_all_key);
+		goto out;
+	}
+	if (cursor_track == CT_Highlight) {
+		if (speak_highlight(vc)) {
+			spk_keydown = 0;
+			is_cursor = 0;
+			goto out;
+		}
+	}
+	if (cursor_track == CT_Window)
+		speakup_win_say(vc);
+	else if (is_cursor == 1 || is_cursor == 4)
+		say_line_from_to(vc, 0, vc->vc_cols, 0);
+	else {
+		if (spk_cur_phonetic == 1)
+			say_phonetic_char(vc);
+		else
+			say_char(vc);
+	}
+	spk_keydown = 0;
+	is_cursor = 0;
+out:
+	spin_unlock_irqrestore(&speakup_info.spinlock, flags);
+}
+
+/* called by: vt_notifier_call() */
+static void speakup_bs(struct vc_data *vc)
+{
+	unsigned long flags;
+
+	if (!speakup_console[vc->vc_num])
+		return;
+	if (!spin_trylock_irqsave(&speakup_info.spinlock, flags))
+		/* Speakup output, discard */
+		return;
+	if (!spk_parked)
+		speakup_date(vc);
+	if (spk_shut_up || !synth) {
+		spin_unlock_irqrestore(&speakup_info.spinlock, flags);
+		return;
+	}
+	if (vc->vc_num == fg_console && spk_keydown) {
+		spk_keydown = 0;
+		if (!is_cursor)
+			say_char(vc);
+	}
+	spin_unlock_irqrestore(&speakup_info.spinlock, flags);
+}
+
+/* called by: vt_notifier_call() */
+static void speakup_con_write(struct vc_data *vc, u16 *str, int len)
+{
+	unsigned long flags;
+
+	if ((vc->vc_num != fg_console) || spk_shut_up || !synth)
+		return;
+	if (!spin_trylock_irqsave(&speakup_info.spinlock, flags))
+		/* Speakup output, discard */
+		return;
+	if (spk_bell_pos && spk_keydown && (vc->state.x == spk_bell_pos - 1))
+		bleep(3);
+	if ((is_cursor) || (cursor_track == read_all_mode)) {
+		if (cursor_track == CT_Highlight)
+			update_color_buffer(vc, str, len);
+		spin_unlock_irqrestore(&speakup_info.spinlock, flags);
+		return;
+	}
+	if (win_enabled) {
+		if (vc->state.x >= win_left && vc->state.x <= win_right &&
+		    vc->state.y >= win_top && vc->state.y <= win_bottom) {
+			spin_unlock_irqrestore(&speakup_info.spinlock, flags);
+			return;
+		}
+	}
+
+	spkup_write(str, len);
+	spin_unlock_irqrestore(&speakup_info.spinlock, flags);
+}
+
+static void speakup_con_update(struct vc_data *vc)
+{
+	unsigned long flags;
+
+	if (!speakup_console[vc->vc_num] || spk_parked || !synth)
+		return;
+	if (!spin_trylock_irqsave(&speakup_info.spinlock, flags))
+		/* Speakup output, discard */
+		return;
+	speakup_date(vc);
+	if (vc->vc_mode == KD_GRAPHICS && !spk_paused && spk_str_pause[0]) {
+		synth_printf("%s", spk_str_pause);
+		spk_paused = true;
+	}
+	spin_unlock_irqrestore(&speakup_info.spinlock, flags);
+}
+
+static void do_handle_spec(struct vc_data *vc, u_char value, char up_flag)
+{
+	unsigned long flags;
+	int on_off = 2;
+	char *label;
+
+	if (!synth || up_flag || spk_killed)
+		return;
+	spin_lock_irqsave(&speakup_info.spinlock, flags);
+	spk_shut_up &= 0xfe;
+	if (spk_no_intr)
+		spk_do_flush();
+	switch (value) {
+	case KVAL(K_CAPS):
+		label = spk_msg_get(MSG_KEYNAME_CAPSLOCK);
+		on_off = vt_get_leds(fg_console, VC_CAPSLOCK);
+		break;
+	case KVAL(K_NUM):
+		label = spk_msg_get(MSG_KEYNAME_NUMLOCK);
+		on_off = vt_get_leds(fg_console, VC_NUMLOCK);
+		break;
+	case KVAL(K_HOLD):
+		label = spk_msg_get(MSG_KEYNAME_SCROLLLOCK);
+		on_off = vt_get_leds(fg_console, VC_SCROLLOCK);
+		if (speakup_console[vc->vc_num])
+			speakup_console[vc->vc_num]->tty_stopped = on_off;
+		break;
+	default:
+		spk_parked &= 0xfe;
+		spin_unlock_irqrestore(&speakup_info.spinlock, flags);
+		return;
+	}
+	if (on_off < 2)
+		synth_printf("%s %s\n",
+			     label, spk_msg_get(MSG_STATUS_START + on_off));
+	spin_unlock_irqrestore(&speakup_info.spinlock, flags);
+}
+
+static int inc_dec_var(u_char value)
+{
+	struct st_var_header *p_header;
+	struct var_t *var_data;
+	char num_buf[32];
+	char *cp = num_buf;
+	char *pn;
+	int var_id = (int)value - VAR_START;
+	int how = (var_id & 1) ? E_INC : E_DEC;
+
+	var_id = var_id / 2 + FIRST_SET_VAR;
+	p_header = spk_get_var_header(var_id);
+	if (!p_header)
+		return -1;
+	if (p_header->var_type != VAR_NUM)
+		return -1;
+	var_data = p_header->data;
+	if (spk_set_num_var(1, p_header, how) != 0)
+		return -1;
+	if (!spk_close_press) {
+		for (pn = p_header->name; *pn; pn++) {
+			if (*pn == '_')
+				*cp = SPACE;
+			else
+				*cp++ = *pn;
+		}
+	}
+	snprintf(cp, sizeof(num_buf) - (cp - num_buf), " %d ",
+		 var_data->u.n.value);
+	synth_printf("%s", num_buf);
+	return 0;
+}
+
+static void speakup_win_set(struct vc_data *vc)
+{
+	char info[40];
+
+	if (win_start > 1) {
+		synth_printf("%s\n", spk_msg_get(MSG_WINDOW_ALREADY_SET));
+		return;
+	}
+	if (spk_x < win_left || spk_y < win_top) {
+		synth_printf("%s\n", spk_msg_get(MSG_END_BEFORE_START));
+		return;
+	}
+	if (win_start && spk_x == win_left && spk_y == win_top) {
+		win_left = 0;
+		win_right = vc->vc_cols - 1;
+		win_bottom = spk_y;
+		snprintf(info, sizeof(info), spk_msg_get(MSG_WINDOW_LINE),
+			 (int)win_top + 1);
+	} else {
+		if (!win_start) {
+			win_top = spk_y;
+			win_left = spk_x;
+		} else {
+			win_bottom = spk_y;
+			win_right = spk_x;
+		}
+		snprintf(info, sizeof(info), spk_msg_get(MSG_WINDOW_BOUNDARY),
+			 (win_start) ?
+				spk_msg_get(MSG_END) : spk_msg_get(MSG_START),
+			 (int)spk_y + 1, (int)spk_x + 1);
+	}
+	synth_printf("%s\n", info);
+	win_start++;
+}
+
+static void speakup_win_clear(struct vc_data *vc)
+{
+	win_top = 0;
+	win_bottom = 0;
+	win_left = 0;
+	win_right = 0;
+	win_start = 0;
+	synth_printf("%s\n", spk_msg_get(MSG_WINDOW_CLEARED));
+}
+
+static void speakup_win_enable(struct vc_data *vc)
+{
+	if (win_start < 2) {
+		synth_printf("%s\n", spk_msg_get(MSG_NO_WINDOW));
+		return;
+	}
+	win_enabled ^= 1;
+	if (win_enabled)
+		synth_printf("%s\n", spk_msg_get(MSG_WINDOW_SILENCED));
+	else
+		synth_printf("%s\n", spk_msg_get(MSG_WINDOW_SILENCE_DISABLED));
+}
+
+static void speakup_bits(struct vc_data *vc)
+{
+	int val = this_speakup_key - (FIRST_EDIT_BITS - 1);
+
+	if (spk_special_handler || val < 1 || val > 6) {
+		synth_printf("%s\n", spk_msg_get(MSG_ERROR));
+		return;
+	}
+	pb_edit = &spk_punc_info[val];
+	synth_printf(spk_msg_get(MSG_EDIT_PROMPT), pb_edit->name);
+	spk_special_handler = edit_bits;
+}
+
+static int handle_goto(struct vc_data *vc, u_char type, u_char ch, u_short key)
+{
+	static u_char goto_buf[8];
+	static int num;
+	int maxlen;
+	char *cp;
+	u16 wch;
+
+	if (type == KT_SPKUP && ch == SPEAKUP_GOTO)
+		goto do_goto;
+	if (type == KT_LATIN && ch == '\n')
+		goto do_goto;
+	if (type != 0)
+		goto oops;
+	if (ch == 8) {
+		u16 wch;
+
+		if (num == 0)
+			return -1;
+		wch = goto_buf[--num];
+		goto_buf[num] = '\0';
+		spkup_write(&wch, 1);
+		return 1;
+	}
+	if (ch < '+' || ch > 'y')
+		goto oops;
+	wch = ch;
+	goto_buf[num++] = ch;
+	goto_buf[num] = '\0';
+	spkup_write(&wch, 1);
+	maxlen = (*goto_buf >= '0') ? 3 : 4;
+	if ((ch == '+' || ch == '-') && num == 1)
+		return 1;
+	if (ch >= '0' && ch <= '9' && num < maxlen)
+		return 1;
+	if (num < maxlen - 1 || num > maxlen)
+		goto oops;
+	if (ch < 'x' || ch > 'y') {
+oops:
+		if (!spk_killed)
+			synth_printf(" %s\n", spk_msg_get(MSG_GOTO_CANCELED));
+		goto_buf[num = 0] = '\0';
+		spk_special_handler = NULL;
+		return 1;
+	}
+
+	/* Do not replace with kstrtoul: here we need cp to be updated */
+	goto_pos = simple_strtoul(goto_buf, &cp, 10);
+
+	if (*cp == 'x') {
+		if (*goto_buf < '0')
+			goto_pos += spk_x;
+		else if (goto_pos > 0)
+			goto_pos--;
+
+		if (goto_pos >= vc->vc_cols)
+			goto_pos = vc->vc_cols - 1;
+		goto_x = 1;
+	} else {
+		if (*goto_buf < '0')
+			goto_pos += spk_y;
+		else if (goto_pos > 0)
+			goto_pos--;
+
+		if (goto_pos >= vc->vc_rows)
+			goto_pos = vc->vc_rows - 1;
+		goto_x = 0;
+	}
+	goto_buf[num = 0] = '\0';
+do_goto:
+	spk_special_handler = NULL;
+	spk_parked |= 0x01;
+	if (goto_x) {
+		spk_pos -= spk_x * 2;
+		spk_x = goto_pos;
+		spk_pos += goto_pos * 2;
+		say_word(vc);
+	} else {
+		spk_y = goto_pos;
+		spk_pos = vc->vc_origin + (goto_pos * vc->vc_size_row);
+		say_line(vc);
+	}
+	return 1;
+}
+
+static void speakup_goto(struct vc_data *vc)
+{
+	if (spk_special_handler) {
+		synth_printf("%s\n", spk_msg_get(MSG_ERROR));
+		return;
+	}
+	synth_printf("%s\n", spk_msg_get(MSG_GOTO));
+	spk_special_handler = handle_goto;
+}
+
+static void speakup_help(struct vc_data *vc)
+{
+	spk_handle_help(vc, KT_SPKUP, SPEAKUP_HELP, 0);
+}
+
+static void do_nothing(struct vc_data *vc)
+{
+	return;			/* flush done in do_spkup */
+}
+
+static u_char key_speakup, spk_key_locked;
+
+static void speakup_lock(struct vc_data *vc)
+{
+	if (!spk_key_locked) {
+		spk_key_locked = 16;
+		key_speakup = 16;
+	} else {
+		spk_key_locked = 0;
+		key_speakup = 0;
+	}
+}
+
+typedef void (*spkup_hand) (struct vc_data *);
+static spkup_hand spkup_handler[] = {
+	/* must be ordered same as defines in speakup.h */
+	do_nothing, speakup_goto, speech_kill, speakup_shut_up,
+	speakup_cut, speakup_paste, say_first_char, say_last_char,
+	say_char, say_prev_char, say_next_char,
+	say_word, say_prev_word, say_next_word,
+	say_line, say_prev_line, say_next_line,
+	top_edge, bottom_edge, left_edge, right_edge,
+	spell_word, spell_word, say_screen,
+	say_position, say_attributes,
+	speakup_off, speakup_parked, say_line,	/* this is for indent */
+	say_from_top, say_to_bottom,
+	say_from_left, say_to_right,
+	say_char_num, speakup_bits, speakup_bits, say_phonetic_char,
+	speakup_bits, speakup_bits, speakup_bits,
+	speakup_win_set, speakup_win_clear, speakup_win_enable, speakup_win_say,
+	speakup_lock, speakup_help, toggle_cursoring, read_all_doc, NULL
+};
+
+static void do_spkup(struct vc_data *vc, u_char value)
+{
+	if (spk_killed && value != SPEECH_KILL)
+		return;
+	spk_keydown = 0;
+	spk_lastkey = 0;
+	spk_shut_up &= 0xfe;
+	this_speakup_key = value;
+	if (value < SPKUP_MAX_FUNC && spkup_handler[value]) {
+		spk_do_flush();
+		(*spkup_handler[value]) (vc);
+	} else {
+		if (inc_dec_var(value) < 0)
+			bleep(9);
+	}
+}
+
+static const char *pad_chars = "0123456789+-*/\015,.?()";
+
+static int
+speakup_key(struct vc_data *vc, int shift_state, int keycode, u_short keysym,
+	    int up_flag)
+{
+	unsigned long flags;
+	int kh;
+	u_char *key_info;
+	u_char type = KTYP(keysym), value = KVAL(keysym), new_key = 0;
+	u_char shift_info, offset;
+	int ret = 0;
+
+	if (!synth)
+		return 0;
+
+	spin_lock_irqsave(&speakup_info.spinlock, flags);
+	tty = vc->port.tty;
+	if (type >= 0xf0)
+		type -= 0xf0;
+	if (type == KT_PAD &&
+	    (vt_get_leds(fg_console, VC_NUMLOCK))) {
+		if (up_flag) {
+			spk_keydown = 0;
+			goto out;
+		}
+		value = pad_chars[value];
+		spk_lastkey = value;
+		spk_keydown++;
+		spk_parked &= 0xfe;
+		goto no_map;
+	}
+	if (keycode >= MAX_KEY)
+		goto no_map;
+	key_info = spk_our_keys[keycode];
+	if (!key_info)
+		goto no_map;
+	/* Check valid read all mode keys */
+	if ((cursor_track == read_all_mode) && (!up_flag)) {
+		switch (value) {
+		case KVAL(K_DOWN):
+		case KVAL(K_UP):
+		case KVAL(K_LEFT):
+		case KVAL(K_RIGHT):
+		case KVAL(K_PGUP):
+		case KVAL(K_PGDN):
+			break;
+		default:
+			stop_read_all(vc);
+			break;
+		}
+	}
+	shift_info = (shift_state & 0x0f) + key_speakup;
+	offset = spk_shift_table[shift_info];
+	if (offset) {
+		new_key = key_info[offset];
+		if (new_key) {
+			ret = 1;
+			if (new_key == SPK_KEY) {
+				if (!spk_key_locked)
+					key_speakup = (up_flag) ? 0 : 16;
+				if (up_flag || spk_killed)
+					goto out;
+				spk_shut_up &= 0xfe;
+				spk_do_flush();
+				goto out;
+			}
+			if (up_flag)
+				goto out;
+			if (last_keycode == keycode &&
+			    time_after(last_spk_jiffy + MAX_DELAY, jiffies)) {
+				spk_close_press = 1;
+				offset = spk_shift_table[shift_info + 32];
+				/* double press? */
+				if (offset && key_info[offset])
+					new_key = key_info[offset];
+			}
+			last_keycode = keycode;
+			last_spk_jiffy = jiffies;
+			type = KT_SPKUP;
+			value = new_key;
+		}
+	}
+no_map:
+	if (type == KT_SPKUP && !spk_special_handler) {
+		do_spkup(vc, new_key);
+		spk_close_press = 0;
+		ret = 1;
+		goto out;
+	}
+	if (up_flag || spk_killed || type == KT_SHIFT)
+		goto out;
+	spk_shut_up &= 0xfe;
+	kh = (value == KVAL(K_DOWN)) ||
+	    (value == KVAL(K_UP)) ||
+	    (value == KVAL(K_LEFT)) ||
+	    (value == KVAL(K_RIGHT));
+	if ((cursor_track != read_all_mode) || !kh)
+		if (!spk_no_intr)
+			spk_do_flush();
+	if (spk_special_handler) {
+		if (type == KT_SPEC && value == 1) {
+			value = '\n';
+			type = KT_LATIN;
+		} else if (type == KT_LETTER) {
+			type = KT_LATIN;
+		} else if (value == 0x7f) {
+			value = 8;	/* make del = backspace */
+		}
+		ret = (*spk_special_handler) (vc, type, value, keycode);
+		spk_close_press = 0;
+		if (ret < 0)
+			bleep(9);
+		goto out;
+	}
+	last_keycode = 0;
+out:
+	spin_unlock_irqrestore(&speakup_info.spinlock, flags);
+	return ret;
+}
+
+static int keyboard_notifier_call(struct notifier_block *nb,
+				  unsigned long code, void *_param)
+{
+	struct keyboard_notifier_param *param = _param;
+	struct vc_data *vc = param->vc;
+	int up = !param->down;
+	int ret = NOTIFY_OK;
+	static int keycode;	/* to hold the current keycode */
+
+	in_keyboard_notifier = 1;
+
+	if (vc->vc_mode == KD_GRAPHICS)
+		goto out;
+
+	/*
+	 * First, determine whether we are handling a fake keypress on
+	 * the current processor.  If we are, then return NOTIFY_OK,
+	 * to pass the keystroke up the chain.  This prevents us from
+	 * trying to take the Speakup lock while it is held by the
+	 * processor on which the simulated keystroke was generated.
+	 * Also, the simulated keystrokes should be ignored by Speakup.
+	 */
+
+	if (speakup_fake_key_pressed())
+		goto out;
+
+	switch (code) {
+	case KBD_KEYCODE:
+		/* speakup requires keycode and keysym currently */
+		keycode = param->value;
+		break;
+	case KBD_UNBOUND_KEYCODE:
+		/* not used yet */
+		break;
+	case KBD_UNICODE:
+		/* not used yet */
+		break;
+	case KBD_KEYSYM:
+		if (speakup_key(vc, param->shift, keycode, param->value, up))
+			ret = NOTIFY_STOP;
+		else if (KTYP(param->value) == KT_CUR)
+			ret = pre_handle_cursor(vc, KVAL(param->value), up);
+		break;
+	case KBD_POST_KEYSYM:{
+			unsigned char type = KTYP(param->value) - 0xf0;
+			unsigned char val = KVAL(param->value);
+
+			switch (type) {
+			case KT_SHIFT:
+				do_handle_shift(vc, val, up);
+				break;
+			case KT_LATIN:
+			case KT_LETTER:
+				do_handle_latin(vc, val, up);
+				break;
+			case KT_CUR:
+				do_handle_cursor(vc, val, up);
+				break;
+			case KT_SPEC:
+				do_handle_spec(vc, val, up);
+				break;
+			}
+			break;
+		}
+	}
+out:
+	in_keyboard_notifier = 0;
+	return ret;
+}
+
+static int vt_notifier_call(struct notifier_block *nb,
+			    unsigned long code, void *_param)
+{
+	struct vt_notifier_param *param = _param;
+	struct vc_data *vc = param->vc;
+
+	switch (code) {
+	case VT_ALLOCATE:
+		if (vc->vc_mode == KD_TEXT)
+			speakup_allocate(vc, GFP_ATOMIC);
+		break;
+	case VT_DEALLOCATE:
+		speakup_deallocate(vc);
+		break;
+	case VT_WRITE:
+		if (param->c == '\b') {
+			speakup_bs(vc);
+		} else {
+			u16 d = param->c;
+
+			speakup_con_write(vc, &d, 1);
+		}
+		break;
+	case VT_UPDATE:
+		speakup_con_update(vc);
+		break;
+	}
+	return NOTIFY_OK;
+}
+
+/* called by: module_exit() */
+static void __exit speakup_exit(void)
+{
+	int i;
+
+	unregister_keyboard_notifier(&keyboard_notifier_block);
+	unregister_vt_notifier(&vt_notifier_block);
+	speakup_unregister_devsynth();
+	speakup_cancel_selection();
+	speakup_cancel_paste();
+	timer_delete_sync(&cursor_timer);
+	kthread_stop(speakup_task);
+	speakup_task = NULL;
+	mutex_lock(&spk_mutex);
+	synth_release();
+	mutex_unlock(&spk_mutex);
+	spk_ttyio_unregister_ldisc();
+
+	speakup_kobj_exit();
+
+	for (i = 0; i < MAX_NR_CONSOLES; i++)
+		kfree(speakup_console[i]);
+
+	speakup_remove_virtual_keyboard();
+
+	for (i = 0; i < MAXVARS; i++)
+		speakup_unregister_var(i);
+
+	for (i = 0; i < 256; i++) {
+		if (spk_characters[i] != spk_default_chars[i])
+			kfree(spk_characters[i]);
+	}
+
+	spk_free_user_msgs();
+}
+
+/* call by: module_init() */
+static int __init speakup_init(void)
+{
+	int i;
+	long err = 0;
+	struct vc_data *vc = vc_cons[fg_console].d;
+	struct var_t *var;
+
+	/* These first few initializations cannot fail. */
+	spk_initialize_msgs();	/* Initialize arrays for i18n. */
+	spk_reset_default_chars();
+	spk_reset_default_chartab();
+	spk_strlwr(synth_name);
+	spk_vars[0].u.n.high = vc->vc_cols;
+	for (var = spk_vars; var->var_id != MAXVARS; var++)
+		speakup_register_var(var);
+	for (var = synth_time_vars;
+	     (var->var_id >= 0) && (var->var_id < MAXVARS); var++)
+		speakup_register_var(var);
+	for (i = 1; spk_punc_info[i].mask != 0; i++)
+		spk_set_mask_bits(NULL, i, 2);
+
+	spk_set_key_info(spk_key_defaults, spk_key_buf);
+
+	/* From here on out, initializations can fail. */
+	err = speakup_add_virtual_keyboard();
+	if (err)
+		goto error_virtkeyboard;
+
+	for (i = 0; i < MAX_NR_CONSOLES; i++)
+		if (vc_cons[i].d) {
+			err = speakup_allocate(vc_cons[i].d, GFP_KERNEL);
+			if (err)
+				goto error_kobjects;
+		}
+
+	if (spk_quiet_boot)
+		spk_shut_up |= 0x01;
+
+	err = speakup_kobj_init();
+	if (err)
+		goto error_kobjects;
+
+	spk_ttyio_register_ldisc();
+	synth_init(synth_name);
+	speakup_register_devsynth();
+	/*
+	 * register_devsynth might fail, but this error is not fatal.
+	 * /dev/synth is an extra feature; the rest of Speakup
+	 * will work fine without it.
+	 */
+
+	err = register_keyboard_notifier(&keyboard_notifier_block);
+	if (err)
+		goto error_kbdnotifier;
+	err = register_vt_notifier(&vt_notifier_block);
+	if (err)
+		goto error_vtnotifier;
+
+	speakup_task = kthread_create(speakup_thread, NULL, "speakup");
+
+	if (IS_ERR(speakup_task)) {
+		err = PTR_ERR(speakup_task);
+		goto error_task;
+	}
+
+	set_user_nice(speakup_task, 10);
+	wake_up_process(speakup_task);
+
+	pr_info("speakup %s: initialized\n", SPEAKUP_VERSION);
+	pr_info("synth name on entry is: %s\n", synth_name);
+	goto out;
+
+error_task:
+	unregister_vt_notifier(&vt_notifier_block);
+
+error_vtnotifier:
+	unregister_keyboard_notifier(&keyboard_notifier_block);
+	timer_delete(&cursor_timer);
+
+error_kbdnotifier:
+	speakup_unregister_devsynth();
+	mutex_lock(&spk_mutex);
+	synth_release();
+	mutex_unlock(&spk_mutex);
+	speakup_kobj_exit();
+
+error_kobjects:
+	for (i = 0; i < MAX_NR_CONSOLES; i++)
+		kfree(speakup_console[i]);
+
+	speakup_remove_virtual_keyboard();
+
+error_virtkeyboard:
+	for (i = 0; i < MAXVARS; i++)
+		speakup_unregister_var(i);
+
+	for (i = 0; i < 256; i++) {
+		if (spk_characters[i] != spk_default_chars[i])
+			kfree(spk_characters[i]);
+	}
+
+	spk_free_user_msgs();
+
+out:
+	return err;
+}
+
+module_param_named(bell_pos, spk_vars[BELL_POS_ID].u.n.default_val, int, 0444);
+module_param_named(spell_delay, spk_vars[SPELL_DELAY_ID].u.n.default_val, int, 0444);
+module_param_named(attrib_bleep, spk_vars[ATTRIB_BLEEP_ID].u.n.default_val, int, 0444);
+module_param_named(bleeps, spk_vars[BLEEPS_ID].u.n.default_val, int, 0444);
+module_param_named(bleep_time, spk_vars[BLEEP_TIME_ID].u.n.default_val, int, 0444);
+module_param_named(punc_level, spk_vars[PUNC_LEVEL_ID].u.n.default_val, int, 0444);
+module_param_named(reading_punc, spk_vars[READING_PUNC_ID].u.n.default_val, int, 0444);
+module_param_named(cursor_time, spk_vars[CURSOR_TIME_ID].u.n.default_val, int, 0444);
+module_param_named(say_control, spk_vars[SAY_CONTROL_ID].u.n.default_val, int, 0444);
+module_param_named(say_word_ctl, spk_vars[SAY_WORD_CTL_ID].u.n.default_val, int, 0444);
+module_param_named(no_interrupt, spk_vars[NO_INTERRUPT_ID].u.n.default_val, int, 0444);
+module_param_named(key_echo, spk_vars[KEY_ECHO_ID].u.n.default_val, int, 0444);
+module_param_named(cur_phonetic, spk_vars[CUR_PHONETIC_ID].u.n.default_val, int, 0444);
+
+MODULE_PARM_DESC(bell_pos, "This works much like a typewriter bell. If for example 72 is echoed to bell_pos, it will beep the PC speaker when typing on a line past character 72.");
+MODULE_PARM_DESC(spell_delay, "This controls how fast a word is spelled when speakup's spell word review command is pressed.");
+MODULE_PARM_DESC(attrib_bleep, "Beeps the PC speaker when there is an attribute change such as background color when using speakup review commands. One = on, zero = off.");
+MODULE_PARM_DESC(bleeps, "This controls whether one hears beeps through the PC speaker when using speakup review commands.");
+MODULE_PARM_DESC(bleep_time, "This controls the duration of the PC speaker beeps speakup produces.");
+MODULE_PARM_DESC(punc_level, "Controls the level of punctuation spoken as the screen is displayed, not reviewed.");
+MODULE_PARM_DESC(reading_punc, "It controls the level of punctuation when reviewing the screen with speakup's screen review commands.");
+MODULE_PARM_DESC(cursor_time, "This controls cursor delay when using arrow keys.");
+MODULE_PARM_DESC(say_control, "This controls if speakup speaks shift, alt and control when those keys are pressed or not.");
+MODULE_PARM_DESC(say_word_ctl, "Sets the say_word_ctl on load.");
+MODULE_PARM_DESC(no_interrupt, "Controls if typing interrupts output from speakup.");
+MODULE_PARM_DESC(key_echo, "Controls if speakup speaks keys when they are typed. One = on zero = off or don't echo keys.");
+MODULE_PARM_DESC(cur_phonetic, "Controls if speakup speaks letters phonetically during navigation. One = on zero = off or don't speak phonetically.");
+
+module_init(speakup_init);
+module_exit(speakup_exit);
diff --git a/drivers/accessibility/speakup/makemapdata.c b/drivers/accessibility/speakup/makemapdata.c
new file mode 100644
index 000000000000..55e4ef8a93dc
--- /dev/null
+++ b/drivers/accessibility/speakup/makemapdata.c
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* makemapdata.c
+ * originally written by: Kirk Reiser.
+ *
+ ** Copyright (C) 2002  Kirk Reiser.
+ *  Copyright (C) 2003  David Borowski.
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <libgen.h>
+#include <string.h>
+#include <ctype.h>
+#include "utils.h"
+
+static char buffer[256];
+
+static int get_define(void)
+{
+	char *c;
+
+	while (fgets(buffer, sizeof(buffer)-1, infile)) {
+		lc++;
+		if (strncmp(buffer, "#define", 7))
+			continue;
+		c = buffer + 7;
+		while (*c == ' ' || *c == '\t')
+			c++;
+		def_name = c;
+		while (*c && *c != ' ' && *c != '\t' && *c != '\n')
+			c++;
+		if (!*c || *c == '\n')
+			continue;
+		*c++ = '\0';
+		while (*c == ' ' || *c == '\t' || *c == '(')
+			c++;
+		def_val = c;
+		while (*c && *c != '\n' && *c != ')')
+			c++;
+		*c++ = '\0';
+		return 1;
+	}
+	fclose(infile);
+	infile = 0;
+	return 0;
+}
+
+int
+main(int argc, char *argv[])
+{
+	int value, i;
+	struct st_key *this;
+	const char *dir_name, *spk_dir_name;
+	char *cp;
+
+	dir_name = getenv("TOPDIR");
+	if (!dir_name)
+		dir_name = ".";
+	spk_dir_name = getenv("SPKDIR");
+	if (!spk_dir_name)
+		spk_dir_name = "drivers/accessibility/speakup";
+	bzero(key_table, sizeof(key_table));
+	add_key("shift",	1, is_shift);
+	add_key("altgr",	2, is_shift);
+	add_key("ctrl",	4, is_shift);
+	add_key("alt",	8, is_shift);
+	add_key("spk", 16, is_shift);
+	add_key("double", 32, is_shift);
+
+	open_input(dir_name, "include/linux/input.h");
+	while (get_define()) {
+		if (strncmp(def_name, "KEY_", 4))
+			continue;
+		value = atoi(def_val);
+		if (value > 0 && value < MAXKEYVAL)
+			add_key(def_name, value, is_input);
+	}
+
+	open_input(dir_name, "include/uapi/linux/input-event-codes.h");
+	while (get_define()) {
+		if (strncmp(def_name, "KEY_", 4))
+			continue;
+		value = atoi(def_val);
+		if (value > 0 && value < MAXKEYVAL)
+			add_key(def_name, value, is_input);
+	}
+
+	open_input(spk_dir_name, "spk_priv_keyinfo.h");
+	while (get_define()) {
+		if (strlen(def_val) > 5) {
+			//if (def_val[0] == '(')
+			//	def_val++;
+			cp = strchr(def_val, '+');
+			if (!cp)
+				continue;
+			if (cp[-1] == ' ')
+				cp[-1] = '\0';
+			*cp++ = '\0';
+			this = find_key(def_val);
+			while (*cp == ' ')
+				cp++;
+			if (!this || *cp < '0' || *cp > '9')
+				continue;
+			value = this->value+atoi(cp);
+		} else if (!strncmp(def_val, "0x", 2))
+			sscanf(def_val+2, "%x", &value);
+		else if (*def_val >= '0' && *def_val <= '9')
+			value = atoi(def_val);
+		else
+			continue;
+		add_key(def_name, value, is_spk);
+	}
+
+	printf("struct st_key_init init_key_data[] = {\n");
+	for (i = 0; i < HASHSIZE; i++) {
+		this = &key_table[i];
+		if (!this->name)
+			continue;
+		do {
+			printf("\t{ \"%s\", %d, %d, },\n", this->name, this->value, this->shift);
+			this = this->next;
+		} while (this);
+	}
+	printf("\t{ \".\", 0, 0 }\n};\n");
+
+	exit(0);
+}
diff --git a/drivers/staging/speakup/selection.c b/drivers/accessibility/speakup/selection.c
index 032f3264fba1..7df7afad5ab4 100644
--- a/drivers/staging/speakup/selection.c
+++ b/drivers/accessibility/speakup/selection.c
@@ -22,13 +22,6 @@ struct speakup_selection_work {
 	struct tty_struct *tty;
 };
 
-void speakup_clear_selection(void)
-{
-	console_lock();
-	clear_selection();
-	console_unlock();
-}
-
 static void __speakup_set_selection(struct work_struct *work)
 {
 	struct speakup_selection_work *ssw =
@@ -51,6 +44,10 @@ static void __speakup_set_selection(struct work_struct *work)
 		goto unref;
 	}
 
+	console_lock();
+	clear_selection();
+	console_unlock();
+
 	set_selection_kernel(&sel, tty);
 
 unref:
diff --git a/drivers/staging/speakup/serialio.c b/drivers/accessibility/speakup/serialio.c
index 177a2988641c..3418ea31d28f 100644
--- a/drivers/staging/speakup/serialio.c
+++ b/drivers/accessibility/speakup/serialio.c
@@ -27,11 +27,12 @@ static const struct old_serial_port *serstate;
 static int timeouts;
 
 static int spk_serial_out(struct spk_synth *in_synth, const char ch);
-static void spk_serial_send_xchar(char ch);
-static void spk_serial_tiocmset(unsigned int set, unsigned int clear);
-static unsigned char spk_serial_in(void);
-static unsigned char spk_serial_in_nowait(void);
-static void spk_serial_flush_buffer(void);
+static void spk_serial_send_xchar(struct spk_synth *in_synth, char ch);
+static void spk_serial_tiocmset(struct spk_synth *in_synth, unsigned int set, unsigned int clear);
+static unsigned char spk_serial_in(struct spk_synth *in_synth);
+static unsigned char spk_serial_in_nowait(struct spk_synth *in_synth);
+static void spk_serial_flush_buffer(struct spk_synth *in_synth);
+static int spk_serial_wait_for_xmitr(struct spk_synth *in_synth);
 
 struct spk_io_ops spk_serial_io_ops = {
 	.synth_out = spk_serial_out,
@@ -40,6 +41,7 @@ struct spk_io_ops spk_serial_io_ops = {
 	.synth_in = spk_serial_in,
 	.synth_in_nowait = spk_serial_in_nowait,
 	.flush_buffer = spk_serial_flush_buffer,
+	.wait_for_xmitr = spk_serial_wait_for_xmitr,
 };
 EXPORT_SYMBOL_GPL(spk_serial_io_ops);
 
@@ -57,7 +59,7 @@ const struct old_serial_port *spk_serial_init(int index)
 	}
 	ser = rs_table + index;
 
-	/*	Divisor, bytesize and parity */
+	/*	Divisor, byte size and parity */
 	quot = ser->baud_base / baud;
 	cval = cflag & (CSIZE | CSTOPB);
 #if defined(__powerpc__) || defined(__alpha__)
@@ -148,7 +150,7 @@ static void start_serial_interrupt(int irq)
 	outb(1, speakup_info.port_tts + UART_FCR);	/* Turn FIFO On */
 }
 
-static void spk_serial_send_xchar(char ch)
+static void spk_serial_send_xchar(struct spk_synth *synth, char ch)
 {
 	int timeout = SPK_XMITR_TIMEOUT;
 
@@ -160,7 +162,7 @@ static void spk_serial_send_xchar(char ch)
 	outb(ch, speakup_info.port_tts);
 }
 
-static void spk_serial_tiocmset(unsigned int set, unsigned int clear)
+static void spk_serial_tiocmset(struct spk_synth *in_synth, unsigned int set, unsigned int clear)
 {
 	int old = inb(speakup_info.port_tts + UART_MCR);
 
@@ -211,7 +213,7 @@ void spk_stop_serial_interrupt(void)
 }
 EXPORT_SYMBOL_GPL(spk_stop_serial_interrupt);
 
-int spk_wait_for_xmitr(struct spk_synth *in_synth)
+static int spk_serial_wait_for_xmitr(struct spk_synth *in_synth)
 {
 	int tmout = SPK_XMITR_TIMEOUT;
 
@@ -249,7 +251,7 @@ int spk_wait_for_xmitr(struct spk_synth *in_synth)
 	return 1;
 }
 
-static unsigned char spk_serial_in(void)
+static unsigned char spk_serial_in(struct spk_synth *in_synth)
 {
 	int tmout = SPK_SERIAL_TIMEOUT;
 
@@ -263,7 +265,7 @@ static unsigned char spk_serial_in(void)
 	return inb_p(speakup_info.port_tts + UART_RX);
 }
 
-static unsigned char spk_serial_in_nowait(void)
+static unsigned char spk_serial_in_nowait(struct spk_synth *in_synth)
 {
 	unsigned char lsr;
 
@@ -273,14 +275,14 @@ static unsigned char spk_serial_in_nowait(void)
 	return inb_p(speakup_info.port_tts + UART_RX);
 }
 
-static void spk_serial_flush_buffer(void)
+static void spk_serial_flush_buffer(struct spk_synth *in_synth)
 {
 	/* TODO: flush the UART 16550 buffer */
 }
 
 static int spk_serial_out(struct spk_synth *in_synth, const char ch)
 {
-	if (in_synth->alive && spk_wait_for_xmitr(in_synth)) {
+	if (in_synth->alive && spk_serial_wait_for_xmitr(in_synth)) {
 		outb_p(ch, speakup_info.port_tts);
 		return 1;
 	}
@@ -295,7 +297,7 @@ const char *spk_serial_synth_immediate(struct spk_synth *synth,
 	while ((ch = *buff)) {
 		if (ch == '\n')
 			ch = synth->procspeech;
-		if (spk_wait_for_xmitr(synth))
+		if (spk_serial_wait_for_xmitr(synth))
 			outb(ch, speakup_info.port_tts);
 		else
 			return buff;
@@ -305,7 +307,7 @@ const char *spk_serial_synth_immediate(struct spk_synth *synth,
 }
 EXPORT_SYMBOL_GPL(spk_serial_synth_immediate);
 
-void spk_serial_release(void)
+void spk_serial_release(struct spk_synth *synth)
 {
 	spk_stop_serial_interrupt();
 	if (speakup_info.port_tts == 0)
diff --git a/drivers/staging/speakup/serialio.h b/drivers/accessibility/speakup/serialio.h
index 6f8f86f161bb..b4f9a1925b81 100644
--- a/drivers/staging/speakup/serialio.h
+++ b/drivers/accessibility/speakup/serialio.h
@@ -33,9 +33,8 @@ struct old_serial_port {
 #define NUM_DISABLE_TIMEOUTS 3
 /* buffer timeout in ms */
 #define SPK_TIMEOUT 100
-#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
 
 #define spk_serial_tx_busy() \
-	((inb(speakup_info.port_tts + UART_LSR) & BOTH_EMPTY) != BOTH_EMPTY)
+	(!uart_lsr_tx_empty(inb(speakup_info.port_tts + UART_LSR)))
 
 #endif
diff --git a/drivers/staging/speakup/speakup.h b/drivers/accessibility/speakup/speakup.h
index 74fe49c2c511..54f1226ea061 100644
--- a/drivers/staging/speakup/speakup.h
+++ b/drivers/accessibility/speakup/speakup.h
@@ -70,14 +70,15 @@ void spk_do_flush(void);
 void speakup_start_ttys(void);
 void synth_buffer_add(u16 ch);
 void synth_buffer_clear(void);
-void speakup_clear_selection(void);
 int speakup_set_selection(struct tty_struct *tty);
 void speakup_cancel_selection(void);
 int speakup_paste_selection(struct tty_struct *tty);
 void speakup_cancel_paste(void);
 void speakup_register_devsynth(void);
 void speakup_unregister_devsynth(void);
+s32 synth_utf8_get(const char *buf, size_t count, size_t *consumed, size_t *want);
 void synth_write(const char *buf, size_t count);
+void synth_writeu(const char *buf, size_t count);
 int synth_supports_indexing(void);
 
 extern struct vc_data *spk_sel_cons;
@@ -106,6 +107,7 @@ extern int spk_no_intr, spk_say_ctrl, spk_say_word_ctl, spk_punc_level;
 extern int spk_reading_punc, spk_attrib_bleep, spk_bleeps;
 extern int spk_bleep_time, spk_bell_pos;
 extern int spk_spell_delay, spk_key_echo;
+extern int spk_cur_phonetic;
 extern short spk_punc_mask;
 extern short spk_pitch_shift, synth_flags;
 extern bool spk_quiet_boot;
diff --git a/drivers/staging/speakup/speakup_acnt.h b/drivers/accessibility/speakup/speakup_acnt.h
index cffa938ae580..cffa938ae580 100644
--- a/drivers/staging/speakup/speakup_acnt.h
+++ b/drivers/accessibility/speakup/speakup_acnt.h
diff --git a/drivers/staging/speakup/speakup_acntpc.c b/drivers/accessibility/speakup/speakup_acntpc.c
index c94328a5bd4a..a27e6bbf05da 100644
--- a/drivers/staging/speakup/speakup_acntpc.c
+++ b/drivers/accessibility/speakup/speakup_acntpc.c
@@ -6,7 +6,7 @@
  * Copyright (C) 1998-99  Kirk Reiser.
  * Copyright (C) 2003 David Borowski.
  *
- * this code is specificly written as a driver for the speakup screenreview
+ * this code is specifically written as a driver for the speakup screenreview
  * package and is not a general device driver.
  * This driver is for the Aicom Acent PC internal synthesizer.
  */
@@ -25,7 +25,7 @@
 #define PROCSPEECH '\r'
 
 static int synth_probe(struct spk_synth *synth);
-static void accent_release(void);
+static void accent_release(struct spk_synth *synth);
 static const char *synth_immediate(struct spk_synth *synth, const char *buf);
 static void do_catch_up(struct spk_synth *synth);
 static void synth_flush(struct spk_synth *synth);
@@ -34,14 +34,23 @@ static int synth_port_control;
 static int port_forced;
 static unsigned int synth_portlist[] = { 0x2a8, 0 };
 
-static struct var_t vars[] = {
-	{ CAPS_START, .u.s = {"\033P8" } },
-	{ CAPS_STOP, .u.s = {"\033P5" } },
-	{ RATE, .u.n = {"\033R%c", 9, 0, 17, 0, 0, "0123456789abcdefgh" } },
-	{ PITCH, .u.n = {"\033P%d", 5, 0, 9, 0, 0, NULL } },
-	{ VOL, .u.n = {"\033A%d", 5, 0, 9, 0, 0, NULL } },
-	{ TONE, .u.n = {"\033V%d", 5, 0, 9, 0, 0, NULL } },
-	{ DIRECT, .u.n = {NULL, 0, 0, 1, 0, 0, NULL } },
+enum default_vars_id {
+	CAPS_START_ID = 0, CAPS_STOP_ID,
+	RATE_ID, PITCH_ID,
+	VOL_ID, TONE_ID,
+	DIRECT_ID, V_LAST_VAR_ID,
+	NB_ID
+};
+
+
+static struct var_t vars[NB_ID] = {
+	[CAPS_START_ID] = { CAPS_START, .u.s = {"\033P8" } },
+	[CAPS_STOP_ID] = { CAPS_STOP, .u.s = {"\033P5" } },
+	[RATE_ID] = { RATE, .u.n = {"\033R%c", 9, 0, 17, 0, 0, "0123456789abcdefgh" } },
+	[PITCH_ID] = { PITCH, .u.n = {"\033P%d", 5, 0, 9, 0, 0, NULL } },
+	[VOL_ID] = { VOL, .u.n = {"\033A%d", 5, 0, 9, 0, 0, NULL } },
+	[TONE_ID] = { TONE, .u.n = {"\033V%d", 5, 0, 9, 0, 0, NULL } },
+	[DIRECT_ID] = { DIRECT, .u.n = {NULL, 0, 0, 1, 0, 0, NULL } },
 	V_LAST_VAR
 };
 
@@ -247,7 +256,7 @@ static void synth_flush(struct spk_synth *synth)
 static int synth_probe(struct spk_synth *synth)
 {
 	unsigned int port_val = 0;
-	int i = 0;
+	int i;
 
 	pr_info("Probing for %s.\n", synth->long_name);
 	if (port_forced) {
@@ -294,7 +303,7 @@ static int synth_probe(struct spk_synth *synth)
 	return 0;
 }
 
-static void accent_release(void)
+static void accent_release(struct spk_synth *synth)
 {
 	spk_stop_serial_interrupt();
 	if (speakup_info.port_tts)
@@ -305,9 +314,22 @@ static void accent_release(void)
 
 module_param_hw_named(port, port_forced, int, ioport, 0444);
 module_param_named(start, synth_acntpc.startup, short, 0444);
+module_param_named(rate, vars[RATE_ID].u.n.default_val, int, 0444);
+module_param_named(pitch, vars[PITCH_ID].u.n.default_val, int, 0444);
+module_param_named(vol, vars[VOL_ID].u.n.default_val, int, 0444);
+module_param_named(tone, vars[TONE_ID].u.n.default_val, int, 0444);
+module_param_named(direct, vars[DIRECT_ID].u.n.default_val, int, 0444);
+
+
 
 MODULE_PARM_DESC(port, "Set the port for the synthesizer (override probing).");
 MODULE_PARM_DESC(start, "Start the synthesizer once it is loaded.");
+MODULE_PARM_DESC(rate, "Set the rate variable on load.");
+MODULE_PARM_DESC(pitch, "Set the pitch variable on load.");
+MODULE_PARM_DESC(vol, "Set the vol variable on load.");
+MODULE_PARM_DESC(tone, "Set the tone variable on load.");
+MODULE_PARM_DESC(direct, "Set the direct variable on load.");
+
 
 module_spk_synth(synth_acntpc);
 
diff --git a/drivers/accessibility/speakup/speakup_acntsa.c b/drivers/accessibility/speakup/speakup_acntsa.c
new file mode 100644
index 000000000000..26bb9f9399d3
--- /dev/null
+++ b/drivers/accessibility/speakup/speakup_acntsa.c
@@ -0,0 +1,165 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * originally written by: Kirk Reiser <kirk@braille.uwo.ca>
+ * this version considerably modified by David Borowski, david575@rogers.com
+ *
+ * Copyright (C) 1998-99  Kirk Reiser.
+ * Copyright (C) 2003 David Borowski.
+ *
+ * this code is specifically written as a driver for the speakup screenreview
+ * package and is not a general device driver.
+ */
+
+#include "spk_priv.h"
+#include "speakup.h"
+#include "speakup_acnt.h" /* local header file for Accent values */
+
+#define DRV_VERSION "2.11"
+#define PROCSPEECH '\r'
+
+static int synth_probe(struct spk_synth *synth);
+
+
+enum default_vars_id {
+	CAPS_START_ID = 0, CAPS_STOP_ID,
+	RATE_ID, PITCH_ID,
+	VOL_ID, TONE_ID,
+	DIRECT_ID, V_LAST_VAR_ID,
+	NB_ID
+};
+
+
+static struct var_t vars[NB_ID] = {
+	[CAPS_START_ID] = { CAPS_START, .u.s = {"\033P8" } },
+	[CAPS_STOP_ID] = { CAPS_STOP, .u.s = {"\033P5" } },
+	[RATE_ID] = { RATE, .u.n = {"\033R%c", 9, 0, 17, 0, 0, "0123456789abcdefgh" } },
+	[PITCH_ID] = { PITCH, .u.n = {"\033P%d", 5, 0, 9, 0, 0, NULL } },
+	[VOL_ID] = { VOL, .u.n = {"\033A%d", 9, 0, 9, 0, 0, NULL } },
+	[TONE_ID] = { TONE, .u.n = {"\033V%d", 5, 0, 9, 0, 0, NULL } },
+	[DIRECT_ID] = { DIRECT, .u.n = {NULL, 0, 0, 1, 0, 0, NULL } },
+	V_LAST_VAR
+};
+
+/*
+ * These attributes will appear in /sys/accessibility/speakup/acntsa.
+ */
+static struct kobj_attribute caps_start_attribute =
+	__ATTR(caps_start, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute caps_stop_attribute =
+	__ATTR(caps_stop, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute pitch_attribute =
+	__ATTR(pitch, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute rate_attribute =
+	__ATTR(rate, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute tone_attribute =
+	__ATTR(tone, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute vol_attribute =
+	__ATTR(vol, 0644, spk_var_show, spk_var_store);
+
+static struct kobj_attribute delay_time_attribute =
+	__ATTR(delay_time, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute direct_attribute =
+	__ATTR(direct, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute full_time_attribute =
+	__ATTR(full_time, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute jiffy_delta_attribute =
+	__ATTR(jiffy_delta, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute trigger_time_attribute =
+	__ATTR(trigger_time, 0644, spk_var_show, spk_var_store);
+
+/*
+ * Create a group of attributes so that we can create and destroy them all
+ * at once.
+ */
+static struct attribute *synth_attrs[] = {
+	&caps_start_attribute.attr,
+	&caps_stop_attribute.attr,
+	&pitch_attribute.attr,
+	&rate_attribute.attr,
+	&tone_attribute.attr,
+	&vol_attribute.attr,
+	&delay_time_attribute.attr,
+	&direct_attribute.attr,
+	&full_time_attribute.attr,
+	&jiffy_delta_attribute.attr,
+	&trigger_time_attribute.attr,
+	NULL,	/* need to NULL terminate the list of attributes */
+};
+
+static struct spk_synth synth_acntsa = {
+	.name = "acntsa",
+	.version = DRV_VERSION,
+	.long_name = "Accent-SA",
+	.init = "\033T2\033=M\033Oi\033N1\n",
+	.procspeech = PROCSPEECH,
+	.clear = SYNTH_CLEAR,
+	.delay = 400,
+	.trigger = 50,
+	.jiffies = 30,
+	.full = 40000,
+	.dev_name = SYNTH_DEFAULT_DEV,
+	.startup = SYNTH_START,
+	.checkval = SYNTH_CHECK,
+	.vars = vars,
+	.io_ops = &spk_ttyio_ops,
+	.probe = synth_probe,
+	.release = spk_ttyio_release,
+	.synth_immediate = spk_ttyio_synth_immediate,
+	.catch_up = spk_do_catch_up,
+	.flush = spk_synth_flush,
+	.is_alive = spk_synth_is_alive_restart,
+	.synth_adjust = NULL,
+	.read_buff_add = NULL,
+	.get_index = NULL,
+	.indexing = {
+		.command = NULL,
+		.lowindex = 0,
+		.highindex = 0,
+		.currindex = 0,
+	},
+	.attributes = {
+		.attrs = synth_attrs,
+		.name = "acntsa",
+	},
+};
+
+static int synth_probe(struct spk_synth *synth)
+{
+	int failed;
+
+	failed = spk_ttyio_synth_probe(synth);
+	if (failed == 0) {
+		synth->synth_immediate(synth, "\033=R\r");
+		mdelay(100);
+	}
+	synth->alive = !failed;
+	return failed;
+}
+
+module_param_named(ser, synth_acntsa.ser, int, 0444);
+module_param_named(dev, synth_acntsa.dev_name, charp, 0444);
+module_param_named(start, synth_acntsa.startup, short, 0444);
+module_param_named(rate, vars[RATE_ID].u.n.default_val, int, 0444);
+module_param_named(pitch, vars[PITCH_ID].u.n.default_val, int, 0444);
+module_param_named(vol, vars[VOL_ID].u.n.default_val, int, 0444);
+module_param_named(tone, vars[TONE_ID].u.n.default_val, int, 0444);
+module_param_named(direct, vars[DIRECT_ID].u.n.default_val, int, 0444);
+
+MODULE_PARM_DESC(ser, "Set the serial port for the synthesizer (0-based).");
+MODULE_PARM_DESC(dev, "Set the device e.g. ttyUSB0, for the synthesizer.");
+MODULE_PARM_DESC(start, "Start the synthesizer once it is loaded.");
+MODULE_PARM_DESC(rate, "Set the rate variable on load.");
+MODULE_PARM_DESC(pitch, "Set the pitch variable on load.");
+MODULE_PARM_DESC(vol, "Set the vol variable on load.");
+MODULE_PARM_DESC(tone, "Set the tone variable on load.");
+MODULE_PARM_DESC(direct, "Set the direct variable on load.");
+
+
+module_spk_synth(synth_acntsa);
+
+MODULE_AUTHOR("Kirk Reiser <kirk@braille.uwo.ca>");
+MODULE_AUTHOR("David Borowski");
+MODULE_DESCRIPTION("Speakup support for Accent SA synthesizer");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(DRV_VERSION);
+
diff --git a/drivers/staging/speakup/speakup_apollo.c b/drivers/accessibility/speakup/speakup_apollo.c
index 0877b4044c28..d2fbb3f57221 100644
--- a/drivers/staging/speakup/speakup_apollo.c
+++ b/drivers/accessibility/speakup/speakup_apollo.c
@@ -6,7 +6,7 @@
  * Copyright (C) 1998-99  Kirk Reiser.
  * Copyright (C) 2003 David Borowski.
  *
- * this code is specificly written as a driver for the speakup screenreview
+ * this code is specifically written as a driver for the speakup screenreview
  * package and is not a general device driver.
  */
 #include <linux/jiffies.h>
@@ -24,15 +24,28 @@
 
 static void do_catch_up(struct spk_synth *synth);
 
-static struct var_t vars[] = {
-	{ CAPS_START, .u.s = {"cap, " } },
-	{ CAPS_STOP, .u.s = {"" } },
-	{ RATE, .u.n = {"@W%d", 6, 1, 9, 0, 0, NULL } },
-	{ PITCH, .u.n = {"@F%x", 10, 0, 15, 0, 0, NULL } },
-	{ VOL, .u.n = {"@A%x", 10, 0, 15, 0, 0, NULL } },
-	{ VOICE, .u.n = {"@V%d", 1, 1, 6, 0, 0, NULL } },
-	{ LANG, .u.n = {"@=%d,", 1, 1, 4, 0, 0, NULL } },
-	{ DIRECT, .u.n = {NULL, 0, 0, 1, 0, 0, NULL } },
+
+
+enum default_vars_id {
+	CAPS_START_ID = 0, CAPS_STOP_ID,
+	RATE_ID, PITCH_ID,
+	VOL_ID, VOICE_ID, LANG_ID,
+	DIRECT_ID, V_LAST_VAR_ID,
+	NB_ID
+};
+
+
+
+
+static struct var_t vars[NB_ID] = {
+	[CAPS_START_ID] = { CAPS_START, .u.s = {"cap, " } },
+	[CAPS_STOP_ID] = { CAPS_STOP, .u.s = {"" } },
+	[RATE_ID] = { RATE, .u.n = {"@W%d", 6, 1, 9, 0, 0, NULL } },
+	[PITCH_ID] = { PITCH, .u.n = {"@F%x", 10, 0, 15, 0, 0, NULL } },
+	[VOL_ID] = { VOL, .u.n = {"@A%x", 10, 0, 15, 0, 0, NULL } },
+	[VOICE_ID] = { VOICE, .u.n = {"@V%d", 1, 1, 6, 0, 0, NULL } },
+	[LANG_ID] = { LANG, .u.n = {"@=%d,", 1, 1, 4, 0, 0, NULL } },
+	[DIRECT_ID] = { DIRECT, .u.n = {NULL, 0, 0, 1, 0, 0, NULL } },
 	V_LAST_VAR
 };
 
@@ -163,8 +176,8 @@ static void do_catch_up(struct spk_synth *synth)
 		full_time_val = full_time->u.n.value;
 		spin_unlock_irqrestore(&speakup_info.spinlock, flags);
 		if (!synth->io_ops->synth_out(synth, ch)) {
-			synth->io_ops->tiocmset(0, UART_MCR_RTS);
-			synth->io_ops->tiocmset(UART_MCR_RTS, 0);
+			synth->io_ops->tiocmset(synth, 0, UART_MCR_RTS);
+			synth->io_ops->tiocmset(synth, UART_MCR_RTS, 0);
 			schedule_timeout(msecs_to_jiffies(full_time_val));
 			continue;
 		}
@@ -193,10 +206,25 @@ static void do_catch_up(struct spk_synth *synth)
 module_param_named(ser, synth_apollo.ser, int, 0444);
 module_param_named(dev, synth_apollo.dev_name, charp, 0444);
 module_param_named(start, synth_apollo.startup, short, 0444);
+module_param_named(rate, vars[RATE_ID].u.n.default_val, int, 0444);
+module_param_named(pitch, vars[PITCH_ID].u.n.default_val, int, 0444);
+module_param_named(vol, vars[VOL_ID].u.n.default_val, int, 0444);
+module_param_named(voice, vars[VOICE_ID].u.n.default_val, int, 0444);
+module_param_named(lang, vars[LANG_ID].u.n.default_val, int, 0444);
+module_param_named(direct, vars[DIRECT_ID].u.n.default_val, int, 0444);
+
 
 MODULE_PARM_DESC(ser, "Set the serial port for the synthesizer (0-based).");
 MODULE_PARM_DESC(dev, "Set the device e.g. ttyUSB0, for the synthesizer.");
 MODULE_PARM_DESC(start, "Start the synthesizer once it is loaded.");
+MODULE_PARM_DESC(rate, "Set the rate variable on load.");
+MODULE_PARM_DESC(pitch, "Set the pitch variable on load.");
+MODULE_PARM_DESC(vol, "Set the vol variable on load.");
+MODULE_PARM_DESC(voice, "Set the voice variable on load.");
+MODULE_PARM_DESC(lang, "Set the lang variable on load.");
+MODULE_PARM_DESC(direct, "Set the direct variable on load.");
+
+
 
 module_spk_synth(synth_apollo);
 
diff --git a/drivers/accessibility/speakup/speakup_audptr.c b/drivers/accessibility/speakup/speakup_audptr.c
new file mode 100644
index 000000000000..55813f3e40ff
--- /dev/null
+++ b/drivers/accessibility/speakup/speakup_audptr.c
@@ -0,0 +1,197 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * originally written by: Kirk Reiser <kirk@braille.uwo.ca>
+ * this version considerably modified by David Borowski, david575@rogers.com
+ *
+ * Copyright (C) 1998-99  Kirk Reiser.
+ * Copyright (C) 2003 David Borowski.
+ *
+ * specifically written as a driver for the speakup screenreview
+ * s not a general device driver.
+ */
+#include "spk_priv.h"
+#include "speakup.h"
+
+#define DRV_VERSION "2.11"
+#define SYNTH_CLEAR 0x18 /* flush synth buffer */
+#define PROCSPEECH '\r' /* start synth processing speech char */
+
+static int synth_probe(struct spk_synth *synth);
+static void synth_flush(struct spk_synth *synth);
+
+
+enum default_vars_id {
+	CAPS_START_ID = 0, CAPS_STOP_ID,
+	RATE_ID, PITCH_ID,
+	VOL_ID, TONE_ID, PUNCT_ID,
+	DIRECT_ID, V_LAST_VAR_ID,
+	NB_ID
+};
+
+static struct var_t vars[NB_ID] = {
+	[CAPS_START_ID] = { CAPS_START, .u.s = {"\x05[f99]" } },
+	[CAPS_STOP_ID] = { CAPS_STOP, .u.s = {"\x05[f80]" } },
+	[RATE_ID] = { RATE, .u.n = {"\x05[r%d]", 10, 0, 20, 100, -10, NULL } },
+	[PITCH_ID] = { PITCH, .u.n = {"\x05[f%d]", 80, 39, 4500, 0, 0, NULL } },
+	[VOL_ID] = { VOL, .u.n = {"\x05[g%d]", 21, 0, 40, 0, 0, NULL } },
+	[TONE_ID] = { TONE, .u.n = {"\x05[s%d]", 9, 0, 63, 0, 0, NULL } },
+	[PUNCT_ID] = { PUNCT, .u.n = {"\x05[A%c]", 0, 0, 3, 0, 0, "nmsa" } },
+	[DIRECT_ID] = { DIRECT, .u.n = {NULL, 0, 0, 1, 0, 0, NULL } },
+	V_LAST_VAR
+};
+
+/*
+ * These attributes will appear in /sys/accessibility/speakup/audptr.
+ */
+static struct kobj_attribute caps_start_attribute =
+	__ATTR(caps_start, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute caps_stop_attribute =
+	__ATTR(caps_stop, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute pitch_attribute =
+	__ATTR(pitch, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute punct_attribute =
+	__ATTR(punct, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute rate_attribute =
+	__ATTR(rate, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute tone_attribute =
+	__ATTR(tone, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute vol_attribute =
+	__ATTR(vol, 0644, spk_var_show, spk_var_store);
+
+static struct kobj_attribute delay_time_attribute =
+	__ATTR(delay_time, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute direct_attribute =
+	__ATTR(direct, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute full_time_attribute =
+	__ATTR(full_time, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute jiffy_delta_attribute =
+	__ATTR(jiffy_delta, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute trigger_time_attribute =
+	__ATTR(trigger_time, 0644, spk_var_show, spk_var_store);
+
+/*
+ * Create a group of attributes so that we can create and destroy them all
+ * at once.
+ */
+static struct attribute *synth_attrs[] = {
+	&caps_start_attribute.attr,
+	&caps_stop_attribute.attr,
+	&pitch_attribute.attr,
+	&punct_attribute.attr,
+	&rate_attribute.attr,
+	&tone_attribute.attr,
+	&vol_attribute.attr,
+	&delay_time_attribute.attr,
+	&direct_attribute.attr,
+	&full_time_attribute.attr,
+	&jiffy_delta_attribute.attr,
+	&trigger_time_attribute.attr,
+	NULL,	/* need to NULL terminate the list of attributes */
+};
+
+static struct spk_synth synth_audptr = {
+	.name = "audptr",
+	.version = DRV_VERSION,
+	.long_name = "Audapter",
+	.init = "\x05[D1]\x05[Ol]",
+	.procspeech = PROCSPEECH,
+	.clear = SYNTH_CLEAR,
+	.delay = 400,
+	.trigger = 50,
+	.jiffies = 30,
+	.full = 18000,
+	.dev_name = SYNTH_DEFAULT_DEV,
+	.startup = SYNTH_START,
+	.checkval = SYNTH_CHECK,
+	.vars = vars,
+	.io_ops = &spk_ttyio_ops,
+	.probe = synth_probe,
+	.release = spk_ttyio_release,
+	.synth_immediate = spk_ttyio_synth_immediate,
+	.catch_up = spk_do_catch_up,
+	.flush = synth_flush,
+	.is_alive = spk_synth_is_alive_restart,
+	.synth_adjust = NULL,
+	.read_buff_add = NULL,
+	.get_index = NULL,
+	.indexing = {
+		.command = NULL,
+		.lowindex = 0,
+		.highindex = 0,
+		.currindex = 0,
+	},
+	.attributes = {
+		.attrs = synth_attrs,
+		.name = "audptr",
+	},
+};
+
+static void synth_flush(struct spk_synth *synth)
+{
+	synth->io_ops->flush_buffer(synth);
+	synth->io_ops->send_xchar(synth, SYNTH_CLEAR);
+	synth->io_ops->synth_out(synth, PROCSPEECH);
+}
+
+static void synth_version(struct spk_synth *synth)
+{
+	unsigned i;
+	char synth_id[33];
+
+	synth->synth_immediate(synth, "\x05[Q]");
+	synth_id[0] = synth->io_ops->synth_in(synth);
+	if (synth_id[0] != 'A')
+		return;
+
+	for (i = 1; i < sizeof(synth_id) - 1; i++) {
+		/* read version string from synth */
+		synth_id[i] = synth->io_ops->synth_in(synth);
+		if (synth_id[i] == '\n')
+			break;
+	}
+	synth_id[i] = '\0';
+	pr_info("%s version: %s", synth->long_name, synth_id);
+}
+
+static int synth_probe(struct spk_synth *synth)
+{
+	int failed;
+
+	failed = spk_ttyio_synth_probe(synth);
+	if (failed == 0)
+		synth_version(synth);
+	synth->alive = !failed;
+	return 0;
+}
+
+module_param_named(ser, synth_audptr.ser, int, 0444);
+module_param_named(dev, synth_audptr.dev_name, charp, 0444);
+module_param_named(start, synth_audptr.startup, short, 0444);
+module_param_named(rate, vars[RATE_ID].u.n.default_val, int, 0444);
+module_param_named(pitch, vars[PITCH_ID].u.n.default_val, int, 0444);
+module_param_named(vol, vars[VOL_ID].u.n.default_val, int, 0444);
+module_param_named(tone, vars[TONE_ID].u.n.default_val, int, 0444);
+module_param_named(punct, vars[PUNCT_ID].u.n.default_val, int, 0444);
+module_param_named(direct, vars[DIRECT_ID].u.n.default_val, int, 0444);
+
+
+
+MODULE_PARM_DESC(ser, "Set the serial port for the synthesizer (0-based).");
+MODULE_PARM_DESC(dev, "Set the device e.g. ttyUSB0, for the synthesizer.");
+MODULE_PARM_DESC(start, "Start the synthesizer once it is loaded.");
+MODULE_PARM_DESC(rate, "Set the rate variable on load.");
+MODULE_PARM_DESC(pitch, "Set the pitch variable on load.");
+MODULE_PARM_DESC(vol, "Set the vol variable on load.");
+MODULE_PARM_DESC(tone, "Set the tone variable on load.");
+MODULE_PARM_DESC(punct, "Set the punct variable on load.");
+MODULE_PARM_DESC(direct, "Set the direct variable on load.");
+
+
+module_spk_synth(synth_audptr);
+
+MODULE_AUTHOR("Kirk Reiser <kirk@braille.uwo.ca>");
+MODULE_AUTHOR("David Borowski");
+MODULE_DESCRIPTION("Speakup support for Audapter synthesizer");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(DRV_VERSION);
+
diff --git a/drivers/accessibility/speakup/speakup_bns.c b/drivers/accessibility/speakup/speakup_bns.c
new file mode 100644
index 000000000000..60507756499c
--- /dev/null
+++ b/drivers/accessibility/speakup/speakup_bns.c
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * originally written by: Kirk Reiser <kirk@braille.uwo.ca>
+ * this version considerably modified by David Borowski, david575@rogers.com
+ *
+ * Copyright (C) 1998-99  Kirk Reiser.
+ * Copyright (C) 2003 David Borowski.
+ *
+ * this code is specifically written as a driver for the speakup screenreview
+ * package and is not a general device driver.
+ */
+#include "spk_priv.h"
+#include "speakup.h"
+
+#define DRV_VERSION "2.11"
+#define SYNTH_CLEAR 0x18
+#define PROCSPEECH '\r'
+
+
+enum default_vars_id {
+	CAPS_START_ID = 0, CAPS_STOP_ID,
+	RATE_ID, PITCH_ID,
+	VOL_ID, TONE_ID,
+	DIRECT_ID, V_LAST_VAR_ID,
+	NB_ID
+};
+
+static struct var_t vars[NB_ID] = {
+	[CAPS_START_ID] = { CAPS_START, .u.s = {"\x05\x31\x32P" } },
+	[CAPS_STOP_ID] = { CAPS_STOP, .u.s = {"\x05\x38P" } },
+	[RATE_ID] = { RATE, .u.n = {"\x05%dE", 8, 1, 16, 0, 0, NULL } },
+	[PITCH_ID] = { PITCH, .u.n = {"\x05%dP", 8, 0, 16, 0, 0, NULL } },
+	[VOL_ID] = { VOL, .u.n = {"\x05%dV", 8, 0, 16, 0, 0, NULL } },
+	[TONE_ID] = { TONE, .u.n = {"\x05%dT", 8, 0, 16, 0, 0, NULL } },
+	[DIRECT_ID] = { DIRECT, .u.n = {NULL, 0, 0, 1, 0, 0, NULL } },
+	V_LAST_VAR
+};
+
+/*
+ * These attributes will appear in /sys/accessibility/speakup/bns.
+ */
+static struct kobj_attribute caps_start_attribute =
+	__ATTR(caps_start, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute caps_stop_attribute =
+	__ATTR(caps_stop, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute pitch_attribute =
+	__ATTR(pitch, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute rate_attribute =
+	__ATTR(rate, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute tone_attribute =
+	__ATTR(tone, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute vol_attribute =
+	__ATTR(vol, 0644, spk_var_show, spk_var_store);
+
+static struct kobj_attribute delay_time_attribute =
+	__ATTR(delay_time, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute direct_attribute =
+	__ATTR(direct, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute full_time_attribute =
+	__ATTR(full_time, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute jiffy_delta_attribute =
+	__ATTR(jiffy_delta, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute trigger_time_attribute =
+	__ATTR(trigger_time, 0644, spk_var_show, spk_var_store);
+
+/*
+ * Create a group of attributes so that we can create and destroy them all
+ * at once.
+ */
+static struct attribute *synth_attrs[] = {
+	&caps_start_attribute.attr,
+	&caps_stop_attribute.attr,
+	&pitch_attribute.attr,
+	&rate_attribute.attr,
+	&tone_attribute.attr,
+	&vol_attribute.attr,
+	&delay_time_attribute.attr,
+	&direct_attribute.attr,
+	&full_time_attribute.attr,
+	&jiffy_delta_attribute.attr,
+	&trigger_time_attribute.attr,
+	NULL,	/* need to NULL terminate the list of attributes */
+};
+
+static struct spk_synth synth_bns = {
+	.name = "bns",
+	.version = DRV_VERSION,
+	.long_name = "Braille 'N Speak",
+	.init = "\x05Z\x05\x43",
+	.procspeech = PROCSPEECH,
+	.clear = SYNTH_CLEAR,
+	.delay = 500,
+	.trigger = 50,
+	.jiffies = 50,
+	.full = 40000,
+	.dev_name = SYNTH_DEFAULT_DEV,
+	.startup = SYNTH_START,
+	.checkval = SYNTH_CHECK,
+	.vars = vars,
+	.io_ops = &spk_ttyio_ops,
+	.probe = spk_ttyio_synth_probe,
+	.release = spk_ttyio_release,
+	.synth_immediate = spk_ttyio_synth_immediate,
+	.catch_up = spk_do_catch_up,
+	.flush = spk_synth_flush,
+	.is_alive = spk_synth_is_alive_restart,
+	.synth_adjust = NULL,
+	.read_buff_add = NULL,
+	.get_index = NULL,
+	.indexing = {
+		.command = NULL,
+		.lowindex = 0,
+		.highindex = 0,
+		.currindex = 0,
+	},
+	.attributes = {
+		.attrs = synth_attrs,
+		.name = "bns",
+	},
+};
+
+module_param_named(ser, synth_bns.ser, int, 0444);
+module_param_named(dev, synth_bns.dev_name, charp, 0444);
+module_param_named(start, synth_bns.startup, short, 0444);
+module_param_named(rate, vars[RATE_ID].u.n.default_val, int, 0444);
+module_param_named(pitch, vars[PITCH_ID].u.n.default_val, int, 0444);
+module_param_named(vol, vars[VOL_ID].u.n.default_val, int, 0444);
+module_param_named(tone, vars[TONE_ID].u.n.default_val, int, 0444);
+module_param_named(direct, vars[DIRECT_ID].u.n.default_val, int, 0444);
+
+
+MODULE_PARM_DESC(ser, "Set the serial port for the synthesizer (0-based).");
+MODULE_PARM_DESC(dev, "Set the device e.g. ttyUSB0, for the synthesizer.");
+MODULE_PARM_DESC(start, "Start the synthesizer once it is loaded.");
+MODULE_PARM_DESC(rate, "Set the rate variable on load.");
+MODULE_PARM_DESC(pitch, "Set the pitch variable on load.");
+MODULE_PARM_DESC(vol, "Set the vol variable on load.");
+MODULE_PARM_DESC(tone, "Set the tone variable on load.");
+MODULE_PARM_DESC(direct, "Set the direct variable on load.");
+
+module_spk_synth(synth_bns);
+
+MODULE_AUTHOR("Kirk Reiser <kirk@braille.uwo.ca>");
+MODULE_AUTHOR("David Borowski");
+MODULE_DESCRIPTION("Speakup support for Braille 'n Speak synthesizers");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(DRV_VERSION);
+
diff --git a/drivers/staging/speakup/speakup_decext.c b/drivers/accessibility/speakup/speakup_decext.c
index ddbb7e97d118..271bcf279bf9 100644
--- a/drivers/staging/speakup/speakup_decext.c
+++ b/drivers/accessibility/speakup/speakup_decext.c
@@ -6,7 +6,7 @@
  * Copyright (C) 1998-99  Kirk Reiser.
  * Copyright (C) 2003 David Borowski.
  *
- * specificly written as a driver for the speakup screenreview
+ * specifically written as a driver for the speakup screenreview
  * s not a general device driver.
  */
 #include <linux/jiffies.h>
@@ -38,15 +38,25 @@ static void synth_flush(struct spk_synth *synth);
 
 static int in_escape;
 
-static struct var_t vars[] = {
-	{ CAPS_START, .u.s = {"[:dv ap 222]" } },
-	{ CAPS_STOP, .u.s = {"[:dv ap 100]" } },
-	{ RATE, .u.n = {"[:ra %d]", 7, 0, 9, 150, 25, NULL } },
-	{ PITCH, .u.n = {"[:dv ap %d]", 100, 0, 100, 0, 0, NULL } },
-	{ VOL, .u.n = {"[:dv gv %d]", 13, 0, 16, 0, 5, NULL } },
-	{ PUNCT, .u.n = {"[:pu %c]", 0, 0, 2, 0, 0, "nsa" } },
-	{ VOICE, .u.n = {"[:n%c]", 0, 0, 9, 0, 0, "phfdburwkv" } },
-	{ DIRECT, .u.n = {NULL, 0, 0, 1, 0, 0, NULL } },
+
+enum default_vars_id {
+	CAPS_START_ID = 0, CAPS_STOP_ID,
+	RATE_ID, PITCH_ID, INFLECTION_ID,
+	VOL_ID, PUNCT_ID, VOICE_ID,
+	DIRECT_ID, V_LAST_ID,
+	NB_ID,
+};
+
+static struct var_t vars[NB_ID] = {
+	[CAPS_START_ID] = { CAPS_START, .u.s = {"[:dv ap 222]" } },
+	[CAPS_STOP_ID] = { CAPS_STOP, .u.s = {"[:dv ap 100]" } },
+	[RATE_ID] = { RATE, .u.n = {"[:ra %d]", 7, 0, 9, 150, 25, NULL } },
+	[PITCH_ID] = { PITCH, .u.n = {"[:dv ap %d]", 100, 0, 100, 0, 0, NULL } },
+	[INFLECTION_ID] = { INFLECTION, .u.n = {"[:dv pr %d] ", 100, 0, 10000, 0, 0, NULL } },
+	[VOL_ID] = { VOL, .u.n = {"[:dv gv %d]", 13, 0, 16, 0, 5, NULL } },
+	[PUNCT_ID] = { PUNCT, .u.n = {"[:pu %c]", 0, 0, 2, 0, 0, "nsa" } },
+	[VOICE_ID] = { VOICE, .u.n = {"[:n%c]", 0, 0, 9, 0, 0, "phfdburwkv" } },
+	[DIRECT_ID] = { DIRECT, .u.n = {NULL, 0, 0, 1, 0, 0, NULL } },
 	V_LAST_VAR
 };
 
@@ -59,6 +69,8 @@ static struct kobj_attribute caps_stop_attribute =
 	__ATTR(caps_stop, 0644, spk_var_show, spk_var_store);
 static struct kobj_attribute pitch_attribute =
 	__ATTR(pitch, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute inflection_attribute =
+	__ATTR(inflection, 0644, spk_var_show, spk_var_store);
 static struct kobj_attribute punct_attribute =
 	__ATTR(punct, 0644, spk_var_show, spk_var_store);
 static struct kobj_attribute rate_attribute =
@@ -87,6 +99,7 @@ static struct attribute *synth_attrs[] = {
 	&caps_start_attribute.attr,
 	&caps_stop_attribute.attr,
 	&pitch_attribute.attr,
+	&inflection_attribute.attr,
 	&punct_attribute.attr,
 	&rate_attribute.attr,
 	&voice_attribute.attr,
@@ -214,17 +227,32 @@ static void do_catch_up(struct spk_synth *synth)
 static void synth_flush(struct spk_synth *synth)
 {
 	in_escape = 0;
-	synth->io_ops->flush_buffer();
+	synth->io_ops->flush_buffer(synth);
 	synth->synth_immediate(synth, "\033P;10z\033\\");
 }
 
 module_param_named(ser, synth_decext.ser, int, 0444);
 module_param_named(dev, synth_decext.dev_name, charp, 0444);
 module_param_named(start, synth_decext.startup, short, 0444);
+module_param_named(rate, vars[RATE_ID].u.n.default_val, int, 0444);
+module_param_named(pitch, vars[PITCH_ID].u.n.default_val, int, 0444);
+module_param_named(inflection, vars[INFLECTION_ID].u.n.default_val, int, 0444);
+module_param_named(vol, vars[VOL_ID].u.n.default_val, int, 0444);
+module_param_named(punct, vars[PUNCT_ID].u.n.default_val, int, 0444);
+module_param_named(voice, vars[VOICE_ID].u.n.default_val, int, 0444);
+module_param_named(direct, vars[DIRECT_ID].u.n.default_val, int, 0444);
+
 
 MODULE_PARM_DESC(ser, "Set the serial port for the synthesizer (0-based).");
 MODULE_PARM_DESC(dev, "Set the device e.g. ttyUSB0, for the synthesizer.");
 MODULE_PARM_DESC(start, "Start the synthesizer once it is loaded.");
+MODULE_PARM_DESC(rate, "Set the rate variable on load.");
+MODULE_PARM_DESC(pitch, "Set the pitch variable on load.");
+MODULE_PARM_DESC(inflection, "Set the inflection variable on load.");
+MODULE_PARM_DESC(vol, "Set the vol variable on load.");
+MODULE_PARM_DESC(punct, "Set the punct variable on load.");
+MODULE_PARM_DESC(voice, "Set the voice variable on load.");
+MODULE_PARM_DESC(direct, "Set the direct variable on load.");
 
 module_spk_synth(synth_decext);
 
diff --git a/drivers/staging/speakup/speakup_decpc.c b/drivers/accessibility/speakup/speakup_decpc.c
index 798c42dfa16c..083ca9265805 100644
--- a/drivers/staging/speakup/speakup_decpc.c
+++ b/drivers/accessibility/speakup/speakup_decpc.c
@@ -125,7 +125,7 @@ enum {	PRIMARY_DIC	= 0, USER_DIC, COMMAND_DIC, ABBREV_DIC };
 #define SYNTH_IO_EXTENT 8
 
 static int synth_probe(struct spk_synth *synth);
-static void dtpc_release(void);
+static void dtpc_release(struct spk_synth *synth);
 static const char *synth_immediate(struct spk_synth *synth, const char *buf);
 static void do_catch_up(struct spk_synth *synth);
 static void synth_flush(struct spk_synth *synth);
@@ -134,15 +134,27 @@ static int synth_portlist[] = { 0x340, 0x350, 0x240, 0x250, 0 };
 static int in_escape, is_flushing;
 static int dt_stat, dma_state;
 
-static struct var_t vars[] = {
-	{ CAPS_START, .u.s = {"[:dv ap 200]" } },
-	{ CAPS_STOP, .u.s = {"[:dv ap 100]" } },
-	{ RATE, .u.n = {"[:ra %d]", 9, 0, 18, 150, 25, NULL } },
-	{ PITCH, .u.n = {"[:dv ap %d]", 80, 0, 100, 20, 0, NULL } },
-	{ VOL, .u.n = {"[:vo se %d]", 5, 0, 9, 5, 10, NULL } },
-	{ PUNCT, .u.n = {"[:pu %c]", 0, 0, 2, 0, 0, "nsa" } },
-	{ VOICE, .u.n = {"[:n%c]", 0, 0, 9, 0, 0, "phfdburwkv" } },
-	{ DIRECT, .u.n = {NULL, 0, 0, 1, 0, 0, NULL } },
+
+enum default_vars_id {
+	CAPS_START_ID = 0, CAPS_STOP_ID,
+	RATE_ID, PITCH_ID, INFLECTION_ID,
+	VOL_ID, PUNCT_ID, VOICE_ID,
+	DIRECT_ID, V_LAST_VAR_ID,
+	NB_ID,
+};
+
+
+
+static struct var_t vars[NB_ID] = {
+	[CAPS_START_ID] = { CAPS_START, .u.s = {"[:dv ap 200]" } },
+	[CAPS_STOP_ID] = { CAPS_STOP, .u.s = {"[:dv ap 100]" } },
+	[RATE_ID] = { RATE, .u.n = {"[:ra %d]", 9, 0, 18, 150, 25, NULL } },
+	[PITCH_ID] = { PITCH, .u.n = {"[:dv ap %d]", 80, 0, 100, 20, 0, NULL } },
+	[INFLECTION_ID] = { INFLECTION, .u.n = {"[:dv pr %d] ", 100, 0, 10000, 0, 0, NULL } },
+	[VOL_ID] = { VOL, .u.n = {"[:vo se %d]", 5, 0, 9, 5, 10, NULL } },
+	[PUNCT_ID] = { PUNCT, .u.n = {"[:pu %c]", 0, 0, 2, 0, 0, "nsa" } },
+	[VOICE_ID] = { VOICE, .u.n = {"[:n%c]", 0, 0, 9, 0, 0, "phfdburwkv" } },
+	[DIRECT_ID] = { DIRECT, .u.n = {NULL, 0, 0, 1, 0, 0, NULL } },
 	V_LAST_VAR
 };
 
@@ -155,6 +167,8 @@ static struct kobj_attribute caps_stop_attribute =
 	__ATTR(caps_stop, 0644, spk_var_show, spk_var_store);
 static struct kobj_attribute pitch_attribute =
 	__ATTR(pitch, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute inflection_attribute =
+	__ATTR(inflection, 0644, spk_var_show, spk_var_store);
 static struct kobj_attribute punct_attribute =
 	__ATTR(punct, 0644, spk_var_show, spk_var_store);
 static struct kobj_attribute rate_attribute =
@@ -183,6 +197,7 @@ static struct attribute *synth_attrs[] = {
 	&caps_start_attribute.attr,
 	&caps_stop_attribute.attr,
 	&pitch_attribute.attr,
+	&inflection_attribute.attr,
 	&punct_attribute.attr,
 	&rate_attribute.attr,
 	&voice_attribute.attr,
@@ -470,7 +485,7 @@ static int synth_probe(struct spk_synth *synth)
 	return 0;
 }
 
-static void dtpc_release(void)
+static void dtpc_release(struct spk_synth *synth)
 {
 	spk_stop_serial_interrupt();
 	if (speakup_info.port_tts)
@@ -479,8 +494,25 @@ static void dtpc_release(void)
 }
 
 module_param_named(start, synth_dec_pc.startup, short, 0444);
+module_param_named(rate, vars[RATE_ID].u.n.default_val, int, 0444);
+module_param_named(pitch, vars[PITCH_ID].u.n.default_val, int, 0444);
+module_param_named(inflection, vars[INFLECTION_ID].u.n.default_val, int, 0444);
+module_param_named(vol, vars[VOL_ID].u.n.default_val, int, 0444);
+module_param_named(punct, vars[PUNCT_ID].u.n.default_val, int, 0444);
+module_param_named(voice, vars[VOICE_ID].u.n.default_val, int, 0444);
+module_param_named(direct, vars[DIRECT_ID].u.n.default_val, int, 0444);
+
+
+
 
 MODULE_PARM_DESC(start, "Start the synthesizer once it is loaded.");
+MODULE_PARM_DESC(rate, "Set the rate variable on load.");
+MODULE_PARM_DESC(pitch, "Set the pitch variable on load.");
+MODULE_PARM_DESC(inflection, "Set the inflection variable on load.");
+MODULE_PARM_DESC(vol, "Set the vol variable on load.");
+MODULE_PARM_DESC(punct, "Set the punct variable on load.");
+MODULE_PARM_DESC(voice, "Set the voice variable on load.");
+MODULE_PARM_DESC(direct, "Set the direct variable on load.");
 
 module_spk_synth(synth_dec_pc);
 
diff --git a/drivers/staging/speakup/speakup_dectlk.c b/drivers/accessibility/speakup/speakup_dectlk.c
index dccb4ea29d37..56334405d865 100644
--- a/drivers/staging/speakup/speakup_dectlk.c
+++ b/drivers/accessibility/speakup/speakup_dectlk.c
@@ -6,7 +6,7 @@
  * Copyright (C) 1998-99  Kirk Reiser.
  * Copyright (C) 2003 David Borowski.
  *
- * specificly written as a driver for the speakup screenreview
+ * specifically written as a driver for the speakup screenreview
  * s not a general device driver.
  */
 #include <linux/unistd.h>
@@ -37,18 +37,27 @@ static unsigned char get_index(struct spk_synth *synth);
 static int in_escape;
 static int is_flushing;
 
-static spinlock_t flush_lock;
+static DEFINE_SPINLOCK(flush_lock);
 static DECLARE_WAIT_QUEUE_HEAD(flush);
 
-static struct var_t vars[] = {
-	{ CAPS_START, .u.s = {"[:dv ap 160] " } },
-	{ CAPS_STOP, .u.s = {"[:dv ap 100 ] " } },
-	{ RATE, .u.n = {"[:ra %d] ", 180, 75, 650, 0, 0, NULL } },
-	{ PITCH, .u.n = {"[:dv ap %d] ", 122, 50, 350, 0, 0, NULL } },
-	{ VOL, .u.n = {"[:dv g5 %d] ", 86, 60, 86, 0, 0, NULL } },
-	{ PUNCT, .u.n = {"[:pu %c] ", 0, 0, 2, 0, 0, "nsa" } },
-	{ VOICE, .u.n = {"[:n%c] ", 0, 0, 9, 0, 0, "phfdburwkv" } },
-	{ DIRECT, .u.n = {NULL, 0, 0, 1, 0, 0, NULL } },
+enum default_vars_id {
+	CAPS_START_ID = 0, CAPS_STOP_ID,
+	RATE_ID, PITCH_ID, INFLECTION_ID,
+	VOL_ID, PUNCT_ID, VOICE_ID,
+	DIRECT_ID, V_LAST_VAR_ID,
+	NB_ID,
+};
+
+static struct var_t vars[NB_ID] = {
+	[CAPS_START_ID] = { CAPS_START, .u.s = {"[:dv ap 160] " } },
+	[CAPS_STOP_ID] = { CAPS_STOP, .u.s = {"[:dv ap 100 ] " } },
+	[RATE_ID] = { RATE, .u.n = {"[:ra %d] ", 180, 75, 650, 0, 0, NULL } },
+	[PITCH_ID] = { PITCH, .u.n = {"[:dv ap %d] ", 122, 50, 350, 0, 0, NULL } },
+	[INFLECTION_ID] = { INFLECTION, .u.n = {"[:dv pr %d] ", 100, 0, 10000, 0, 0, NULL } },
+	[VOL_ID] = { VOL, .u.n = {"[:dv g5 %d] ", 86, 60, 86, 0, 0, NULL } },
+	[PUNCT_ID] = { PUNCT, .u.n = {"[:pu %c] ", 0, 0, 2, 0, 0, "nsa" } },
+	[VOICE_ID] = { VOICE, .u.n = {"[:n%c] ", 0, 0, 9, 0, 0, "phfdburwkv" } },
+	[DIRECT_ID] = { DIRECT, .u.n = {NULL, 0, 0, 1, 0, 0, NULL } },
 	V_LAST_VAR
 };
 
@@ -61,6 +70,8 @@ static struct kobj_attribute caps_stop_attribute =
 	__ATTR(caps_stop, 0644, spk_var_show, spk_var_store);
 static struct kobj_attribute pitch_attribute =
 	__ATTR(pitch, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute inflection_attribute =
+	__ATTR(inflection, 0644, spk_var_show, spk_var_store);
 static struct kobj_attribute punct_attribute =
 	__ATTR(punct, 0644, spk_var_show, spk_var_store);
 static struct kobj_attribute rate_attribute =
@@ -76,6 +87,8 @@ static struct kobj_attribute direct_attribute =
 	__ATTR(direct, 0644, spk_var_show, spk_var_store);
 static struct kobj_attribute full_time_attribute =
 	__ATTR(full_time, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute flush_time_attribute =
+	__ATTR(flush_time, 0644, spk_var_show, spk_var_store);
 static struct kobj_attribute jiffy_delta_attribute =
 	__ATTR(jiffy_delta, 0644, spk_var_show, spk_var_store);
 static struct kobj_attribute trigger_time_attribute =
@@ -89,6 +102,7 @@ static struct attribute *synth_attrs[] = {
 	&caps_start_attribute.attr,
 	&caps_stop_attribute.attr,
 	&pitch_attribute.attr,
+	&inflection_attribute.attr,
 	&punct_attribute.attr,
 	&rate_attribute.attr,
 	&voice_attribute.attr,
@@ -96,6 +110,7 @@ static struct attribute *synth_attrs[] = {
 	&delay_time_attribute.attr,
 	&direct_attribute.attr,
 	&full_time_attribute.attr,
+	&flush_time_attribute.attr,
 	&jiffy_delta_attribute.attr,
 	&trigger_time_attribute.attr,
 	NULL,	/* need to NULL terminate the list of attributes */
@@ -115,6 +130,7 @@ static struct spk_synth synth_dectlk = {
 	.trigger = 50,
 	.jiffies = 50,
 	.full = 40000,
+	.flush_time = 4000,
 	.dev_name = SYNTH_DEFAULT_DEV,
 	.startup = SYNTH_START,
 	.checkval = SYNTH_CHECK,
@@ -197,18 +213,23 @@ static void do_catch_up(struct spk_synth *synth)
 	static u_char last = '\0';
 	unsigned long flags;
 	unsigned long jiff_max;
-	unsigned long timeout = msecs_to_jiffies(4000);
+	unsigned long timeout;
 	DEFINE_WAIT(wait);
 	struct var_t *jiffy_delta;
 	struct var_t *delay_time;
+	struct var_t *flush_time;
 	int jiffy_delta_val;
 	int delay_time_val;
+	int timeout_val;
 
 	jiffy_delta = spk_get_var(JIFFY);
 	delay_time = spk_get_var(DELAY);
+	flush_time = spk_get_var(FLUSH);
 	spin_lock_irqsave(&speakup_info.spinlock, flags);
 	jiffy_delta_val = jiffy_delta->u.n.value;
+	timeout_val = flush_time->u.n.value;
 	spin_unlock_irqrestore(&speakup_info.spinlock, flags);
+	timeout = msecs_to_jiffies(timeout_val);
 	jiff_max = jiffies + jiffy_delta_val;
 
 	while (!kthread_should_stop()) {
@@ -286,17 +307,34 @@ static void synth_flush(struct spk_synth *synth)
 		synth->io_ops->synth_out(synth, ']');
 	in_escape = 0;
 	is_flushing = 1;
-	synth->io_ops->flush_buffer();
+	synth->io_ops->flush_buffer(synth);
 	synth->io_ops->synth_out(synth, SYNTH_CLEAR);
 }
 
 module_param_named(ser, synth_dectlk.ser, int, 0444);
 module_param_named(dev, synth_dectlk.dev_name, charp, 0444);
 module_param_named(start, synth_dectlk.startup, short, 0444);
+module_param_named(rate, vars[RATE_ID].u.n.default_val, int, 0444);
+module_param_named(pitch, vars[PITCH_ID].u.n.default_val, int, 0444);
+module_param_named(inflection, vars[INFLECTION_ID].u.n.default_val, int, 0444);
+module_param_named(vol, vars[VOL_ID].u.n.default_val, int, 0444);
+module_param_named(punct, vars[PUNCT_ID].u.n.default_val, int, 0444);
+module_param_named(voice, vars[VOICE_ID].u.n.default_val, int, 0444);
+module_param_named(direct, vars[DIRECT_ID].u.n.default_val, int, 0444);
+
+
 
 MODULE_PARM_DESC(ser, "Set the serial port for the synthesizer (0-based).");
 MODULE_PARM_DESC(dev, "Set the device e.g. ttyUSB0, for the synthesizer.");
 MODULE_PARM_DESC(start, "Start the synthesizer once it is loaded.");
+MODULE_PARM_DESC(rate, "Set the rate variable on load.");
+MODULE_PARM_DESC(pitch, "Set the pitch variable on load.");
+MODULE_PARM_DESC(inflection, "Set the inflection variable on load.");
+MODULE_PARM_DESC(vol, "Set the vol variable on load.");
+MODULE_PARM_DESC(punct, "Set the punct variable on load.");
+MODULE_PARM_DESC(voice, "Set the voice variable on load.");
+MODULE_PARM_DESC(direct, "Set the direct variable on load.");
+
 
 module_spk_synth(synth_dectlk);
 
diff --git a/drivers/staging/speakup/speakup_dtlk.c b/drivers/accessibility/speakup/speakup_dtlk.c
index dbebed0eeeec..fa826568937b 100644
--- a/drivers/staging/speakup/speakup_dtlk.c
+++ b/drivers/accessibility/speakup/speakup_dtlk.c
@@ -6,7 +6,7 @@
  * Copyright (C) 1998-99  Kirk Reiser.
  * Copyright (C) 2003 David Borowski.
  *
- * specificly written as a driver for the speakup screenreview
+ * specifically written as a driver for the speakup screenreview
  * package it's not a general device driver.
  * This driver is for the RC Systems DoubleTalk PC internal synthesizer.
  */
@@ -24,7 +24,7 @@
 #define PROCSPEECH 0x00
 
 static int synth_probe(struct spk_synth *synth);
-static void dtlk_release(void);
+static void dtlk_release(struct spk_synth *synth);
 static const char *synth_immediate(struct spk_synth *synth, const char *buf);
 static void do_catch_up(struct spk_synth *synth);
 static void synth_flush(struct spk_synth *synth);
@@ -37,17 +37,27 @@ static unsigned int synth_portlist[] = {
 
 static u_char synth_status;
 
-static struct var_t vars[] = {
-	{ CAPS_START, .u.s = {"\x01+35p" } },
-	{ CAPS_STOP, .u.s = {"\x01-35p" } },
-	{ RATE, .u.n = {"\x01%ds", 8, 0, 9, 0, 0, NULL } },
-	{ PITCH, .u.n = {"\x01%dp", 50, 0, 99, 0, 0, NULL } },
-	{ VOL, .u.n = {"\x01%dv", 5, 0, 9, 0, 0, NULL } },
-	{ TONE, .u.n = {"\x01%dx", 1, 0, 2, 0, 0, NULL } },
-	{ PUNCT, .u.n = {"\x01%db", 7, 0, 15, 0, 0, NULL } },
-	{ VOICE, .u.n = {"\x01%do", 0, 0, 7, 0, 0, NULL } },
-	{ FREQUENCY, .u.n = {"\x01%df", 5, 0, 9, 0, 0, NULL } },
-	{ DIRECT, .u.n = {NULL, 0, 0, 1, 0, 0, NULL } },
+enum default_vars_id {
+	CAPS_START_ID = 0, CAPS_STOP_ID,
+	RATE_ID, PITCH_ID,
+	VOL_ID, TONE_ID, PUNCT_ID,
+	VOICE_ID, FREQUENCY_ID,
+	DIRECT_ID, V_LAST_VAR_ID,
+	NB_ID,
+};
+
+
+static struct var_t vars[NB_ID] = {
+	[CAPS_START_ID] = { CAPS_START, .u.s = {"\x01+35p" } },
+	[CAPS_STOP_ID] = { CAPS_STOP, .u.s = {"\x01-35p" } },
+	[RATE_ID] = { RATE, .u.n = {"\x01%ds", 8, 0, 9, 0, 0, NULL } },
+	[PITCH_ID] = { PITCH, .u.n = {"\x01%dp", 50, 0, 99, 0, 0, NULL } },
+	[VOL_ID] = { VOL, .u.n = {"\x01%dv", 5, 0, 9, 0, 0, NULL } },
+	[TONE_ID] = { TONE, .u.n = {"\x01%dx", 1, 0, 2, 0, 0, NULL } },
+	[PUNCT_ID] = { PUNCT, .u.n = {"\x01%db", 7, 0, 15, 0, 0, NULL } },
+	[VOICE_ID] = { VOICE, .u.n = {"\x01%do", 0, 0, 7, 0, 0, NULL } },
+	[FREQUENCY_ID] = { FREQUENCY, .u.n = {"\x01%df", 5, 0, 9, 0, 0, NULL } },
+	[DIRECT_ID] = { DIRECT, .u.n = {NULL, 0, 0, 1, 0, 0, NULL } },
 	V_LAST_VAR
 };
 
@@ -316,7 +326,7 @@ static struct synth_settings *synth_interrogate(struct spk_synth *synth)
 static int synth_probe(struct spk_synth *synth)
 {
 	unsigned int port_val = 0;
-	int i = 0;
+	int i;
 	struct synth_settings *sp;
 
 	pr_info("Probing for DoubleTalk.\n");
@@ -365,7 +375,7 @@ static int synth_probe(struct spk_synth *synth)
 	return 0;
 }
 
-static void dtlk_release(void)
+static void dtlk_release(struct spk_synth *synth)
 {
 	spk_stop_serial_interrupt();
 	if (speakup_info.port_tts)
@@ -376,9 +386,27 @@ static void dtlk_release(void)
 
 module_param_hw_named(port, port_forced, int, ioport, 0444);
 module_param_named(start, synth_dtlk.startup, short, 0444);
+module_param_named(rate, vars[RATE_ID].u.n.default_val, int, 0444);
+module_param_named(pitch, vars[PITCH_ID].u.n.default_val, int, 0444);
+module_param_named(vol, vars[VOL_ID].u.n.default_val, int, 0444);
+module_param_named(tone, vars[TONE_ID].u.n.default_val, int, 0444);
+module_param_named(punct, vars[PUNCT_ID].u.n.default_val, int, 0444);
+module_param_named(voice, vars[VOICE_ID].u.n.default_val, int, 0444);
+module_param_named(frequency, vars[FREQUENCY_ID].u.n.default_val, int, 0444);
+module_param_named(direct, vars[DIRECT_ID].u.n.default_val, int, 0444);
+
 
 MODULE_PARM_DESC(port, "Set the port for the synthesizer (override probing).");
 MODULE_PARM_DESC(start, "Start the synthesizer once it is loaded.");
+MODULE_PARM_DESC(rate, "Set the rate variable on load.");
+MODULE_PARM_DESC(pitch, "Set the pitch variable on load.");
+MODULE_PARM_DESC(vol, "Set the vol variable on load.");
+MODULE_PARM_DESC(tone, "Set the tone variable on load.");
+MODULE_PARM_DESC(punct, "Set the punct variable on load.");
+MODULE_PARM_DESC(voice, "Set the voice variable on load.");
+MODULE_PARM_DESC(frequency, "Set the frequency variable on load.");
+MODULE_PARM_DESC(direct, "Set the direct variable on load.");
+
 
 module_spk_synth(synth_dtlk);
 
diff --git a/drivers/staging/speakup/speakup_dtlk.h b/drivers/accessibility/speakup/speakup_dtlk.h
index 9c378b58066e..9c378b58066e 100644
--- a/drivers/staging/speakup/speakup_dtlk.h
+++ b/drivers/accessibility/speakup/speakup_dtlk.h
diff --git a/drivers/accessibility/speakup/speakup_dummy.c b/drivers/accessibility/speakup/speakup_dummy.c
new file mode 100644
index 000000000000..52b2c5d44576
--- /dev/null
+++ b/drivers/accessibility/speakup/speakup_dummy.c
@@ -0,0 +1,174 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * originally written by: Kirk Reiser <kirk@braille.uwo.ca>
+ * this version considerably modified by David Borowski, david575@rogers.com
+ * eventually modified by Samuel Thibault <samuel.thibault@ens-lyon.org>
+ *
+ * Copyright (C) 1998-99  Kirk Reiser.
+ * Copyright (C) 2003 David Borowski.
+ * Copyright (C) 2007 Samuel Thibault.
+ *
+ * specifically written as a driver for the speakup screenreview
+ * s not a general device driver.
+ */
+#include "spk_priv.h"
+#include "speakup.h"
+
+#define PROCSPEECH '\n'
+#define DRV_VERSION "2.11"
+#define SYNTH_CLEAR '!'
+
+
+enum default_vars_id {
+	CAPS_START_ID = 0, CAPS_STOP_ID,
+	PAUSE_ID,
+	RATE_ID, PITCH_ID, INFLECTION_ID,
+	VOL_ID, TONE_ID, PUNCT_ID,
+	DIRECT_ID, V_LAST_VAR_ID,
+	NB_ID
+};
+
+
+
+
+static struct var_t vars[NB_ID] = {
+	[CAPS_START_ID] = { CAPS_START, .u.s = {"CAPS_START\n" } },
+	[CAPS_STOP_ID] = { CAPS_STOP, .u.s = {"CAPS_STOP\n" } },
+	[PAUSE_ID] = { PAUSE, .u.s = {"PAUSE\n"} },
+	[RATE_ID] = { RATE, .u.n = {"RATE %d\n", 8, 1, 16, 0, 0, NULL } },
+	[PITCH_ID] = { PITCH, .u.n = {"PITCH %d\n", 8, 0, 16, 0, 0, NULL } },
+	[INFLECTION_ID] = { INFLECTION, .u.n = {"INFLECTION %d\n", 8, 0, 16, 0, 0, NULL } },
+	[VOL_ID] = { VOL, .u.n = {"VOL %d\n", 8, 0, 16, 0, 0, NULL } },
+	[TONE_ID] = { TONE, .u.n = {"TONE %d\n", 8, 0, 16, 0, 0, NULL } },
+	[PUNCT_ID] = { PUNCT, .u.n = {"PUNCT %d\n", 0, 0, 3, 0, 0, NULL } },
+	[DIRECT_ID] = { DIRECT, .u.n = {NULL, 0, 0, 1, 0, 0, NULL } },
+	V_LAST_VAR
+};
+
+/*
+ * These attributes will appear in /sys/accessibility/speakup/dummy.
+ */
+static struct kobj_attribute caps_start_attribute =
+	__ATTR(caps_start, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute caps_stop_attribute =
+	__ATTR(caps_stop, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute pitch_attribute =
+	__ATTR(pitch, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute inflection_attribute =
+	__ATTR(inflection, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute punct_attribute =
+	__ATTR(punct, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute rate_attribute =
+	__ATTR(rate, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute tone_attribute =
+	__ATTR(tone, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute vol_attribute =
+	__ATTR(vol, 0644, spk_var_show, spk_var_store);
+
+static struct kobj_attribute delay_time_attribute =
+	__ATTR(delay_time, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute direct_attribute =
+	__ATTR(direct, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute full_time_attribute =
+	__ATTR(full_time, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute jiffy_delta_attribute =
+	__ATTR(jiffy_delta, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute trigger_time_attribute =
+	__ATTR(trigger_time, 0644, spk_var_show, spk_var_store);
+
+/*
+ * Create a group of attributes so that we can create and destroy them all
+ * at once.
+ */
+static struct attribute *synth_attrs[] = {
+	&caps_start_attribute.attr,
+	&caps_stop_attribute.attr,
+	&pitch_attribute.attr,
+	&inflection_attribute.attr,
+	&punct_attribute.attr,
+	&rate_attribute.attr,
+	&tone_attribute.attr,
+	&vol_attribute.attr,
+	&delay_time_attribute.attr,
+	&direct_attribute.attr,
+	&full_time_attribute.attr,
+	&jiffy_delta_attribute.attr,
+	&trigger_time_attribute.attr,
+	NULL,	/* need to NULL terminate the list of attributes */
+};
+
+static void read_buff_add(u_char c)
+{
+	pr_info("speakup_dummy: got character %02x\n", c);
+}
+
+static struct spk_synth synth_dummy = {
+	.name = "dummy",
+	.version = DRV_VERSION,
+	.long_name = "Dummy",
+	.init = "Speakup\n",
+	.procspeech = PROCSPEECH,
+	.clear = SYNTH_CLEAR,
+	.delay = 500,
+	.trigger = 50,
+	.jiffies = 50,
+	.full = 40000,
+	.dev_name = SYNTH_DEFAULT_DEV,
+	.startup = SYNTH_START,
+	.checkval = SYNTH_CHECK,
+	.vars = vars,
+	.io_ops = &spk_ttyio_ops,
+	.probe = spk_ttyio_synth_probe,
+	.release = spk_ttyio_release,
+	.synth_immediate = spk_ttyio_synth_immediate,
+	.catch_up = spk_do_catch_up_unicode,
+	.flush = spk_synth_flush,
+	.is_alive = spk_synth_is_alive_restart,
+	.synth_adjust = NULL,
+	.read_buff_add = read_buff_add,
+	.get_index = NULL,
+	.indexing = {
+		.command = NULL,
+		.lowindex = 0,
+		.highindex = 0,
+		.currindex = 0,
+	},
+	.attributes = {
+		.attrs = synth_attrs,
+		.name = "dummy",
+	},
+};
+
+module_param_named(ser, synth_dummy.ser, int, 0444);
+module_param_named(dev, synth_dummy.dev_name, charp, 0444);
+module_param_named(start, synth_dummy.startup, short, 0444);
+module_param_named(rate, vars[RATE_ID].u.n.default_val, int, 0444);
+module_param_named(pitch, vars[PITCH_ID].u.n.default_val, int, 0444);
+module_param_named(inflection, vars[INFLECTION_ID].u.n.default_val, int, 0444);
+module_param_named(vol, vars[VOL_ID].u.n.default_val, int, 0444);
+module_param_named(tone, vars[TONE_ID].u.n.default_val, int, 0444);
+module_param_named(punct, vars[PUNCT_ID].u.n.default_val, int, 0444);
+module_param_named(direct, vars[DIRECT_ID].u.n.default_val, int, 0444);
+
+
+
+
+MODULE_PARM_DESC(ser, "Set the serial port for the synthesizer (0-based).");
+MODULE_PARM_DESC(dev, "Set the device e.g. ttyUSB0, for the synthesizer.");
+MODULE_PARM_DESC(start, "Start the synthesizer once it is loaded.");
+MODULE_PARM_DESC(rate, "Set the rate variable on load.");
+MODULE_PARM_DESC(pitch, "Set the pitch variable on load.");
+MODULE_PARM_DESC(inflection, "Set the inflection variable on load.");
+MODULE_PARM_DESC(vol, "Set the vol variable on load.");
+MODULE_PARM_DESC(tone, "Set the tone variable on load.");
+MODULE_PARM_DESC(punct, "Set the punct variable on load.");
+MODULE_PARM_DESC(direct, "Set the direct variable on load.");
+
+
+module_spk_synth(synth_dummy);
+
+MODULE_AUTHOR("Samuel Thibault <samuel.thibault@ens-lyon.org>");
+MODULE_DESCRIPTION("Speakup support for text console");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(DRV_VERSION);
+
diff --git a/drivers/staging/speakup/speakup_keypc.c b/drivers/accessibility/speakup/speakup_keypc.c
index 414827e888fc..9356f6379560 100644
--- a/drivers/staging/speakup/speakup_keypc.c
+++ b/drivers/accessibility/speakup/speakup_keypc.c
@@ -4,7 +4,7 @@
  *
  * Copyright (C) 2003 David Borowski.
  *
- * specificly written as a driver for the speakup screenreview
+ * specifically written as a driver for the speakup screenreview
  * package it's not a general device driver.
  * This driver is for the Keynote Gold internal synthesizer.
  */
@@ -24,7 +24,7 @@
 #define SYNTH_CLEAR 0x03
 
 static int synth_probe(struct spk_synth *synth);
-static void keynote_release(void);
+static void keynote_release(struct spk_synth *synth);
 static const char *synth_immediate(struct spk_synth *synth, const char *buf);
 static void do_catch_up(struct spk_synth *synth);
 static void synth_flush(struct spk_synth *synth);
@@ -33,12 +33,21 @@ static int synth_port;
 static int port_forced;
 static unsigned int synth_portlist[] = { 0x2a8, 0 };
 
-static struct var_t vars[] = {
-	{ CAPS_START, .u.s = {"[f130]" } },
-	{ CAPS_STOP, .u.s = {"[f90]" } },
-	{ RATE, .u.n = {"\04%c ", 8, 0, 10, 81, -8, NULL } },
-	{ PITCH, .u.n = {"[f%d]", 5, 0, 9, 40, 10, NULL } },
-	{ DIRECT, .u.n = {NULL, 0, 0, 1, 0, 0, NULL } },
+
+enum default_vars_id {
+	CAPS_START_ID = 0, CAPS_STOP_ID,
+	RATE_ID, PITCH_ID,
+	DIRECT_ID, V_LAST_VAR_ID,
+	NB_ID
+};
+
+
+static struct var_t vars[NB_ID] = {
+	[CAPS_START_ID] = { CAPS_START, .u.s = {"[f130]" } },
+	[CAPS_STOP_ID] = { CAPS_STOP, .u.s = {"[f90]" } },
+	[RATE_ID] = { RATE, .u.n = {"\04%c ", 8, 0, 10, 81, -8, NULL } },
+	[PITCH_ID] = { PITCH, .u.n = {"[f%d]", 5, 0, 9, 40, 10, NULL } },
+	[DIRECT_ID] = { DIRECT, .u.n = {NULL, 0, 0, 1, 0, 0, NULL } },
 	V_LAST_VAR
 };
 
@@ -254,7 +263,7 @@ static void synth_flush(struct spk_synth *synth)
 static int synth_probe(struct spk_synth *synth)
 {
 	unsigned int port_val = 0;
-	int i = 0;
+	int i;
 
 	pr_info("Probing for %s.\n", synth->long_name);
 	if (port_forced) {
@@ -295,7 +304,7 @@ static int synth_probe(struct spk_synth *synth)
 	return 0;
 }
 
-static void keynote_release(void)
+static void keynote_release(struct spk_synth *synth)
 {
 	spk_stop_serial_interrupt();
 	if (synth_port)
@@ -305,9 +314,17 @@ static void keynote_release(void)
 
 module_param_hw_named(port, port_forced, int, ioport, 0444);
 module_param_named(start, synth_keypc.startup, short, 0444);
+module_param_named(rate, vars[RATE_ID].u.n.default_val, int, 0444);
+module_param_named(pitch, vars[PITCH_ID].u.n.default_val, int, 0444);
+module_param_named(direct, vars[DIRECT_ID].u.n.default_val, int, 0444);
 
 MODULE_PARM_DESC(port, "Set the port for the synthesizer (override probing).");
 MODULE_PARM_DESC(start, "Start the synthesizer once it is loaded.");
+MODULE_PARM_DESC(rate, "Set the rate variable on load.");
+MODULE_PARM_DESC(pitch, "Set the pitch variable on load.");
+MODULE_PARM_DESC(direct, "Set the direct variable on load.");
+
+
 
 module_spk_synth(synth_keypc);
 
diff --git a/drivers/accessibility/speakup/speakup_ltlk.c b/drivers/accessibility/speakup/speakup_ltlk.c
new file mode 100644
index 000000000000..1e279ae143bf
--- /dev/null
+++ b/drivers/accessibility/speakup/speakup_ltlk.c
@@ -0,0 +1,206 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * originally written by: Kirk Reiser <kirk@braille.uwo.ca>
+ * this version considerably modified by David Borowski, david575@rogers.com
+ *
+ * Copyright (C) 1998-99  Kirk Reiser.
+ * Copyright (C) 2003 David Borowski.
+ *
+ * specifically written as a driver for the speakup screenreview
+ * s not a general device driver.
+ */
+#include "speakup.h"
+#include "spk_priv.h"
+#include "speakup_dtlk.h" /* local header file for LiteTalk values */
+
+#define DRV_VERSION "2.11"
+#define PROCSPEECH 0x0d
+
+static int synth_probe(struct spk_synth *synth);
+
+
+enum default_vars_id {
+	CAPS_START_ID = 0, CAPS_STOP_ID,
+	RATE_ID, PITCH_ID,
+	VOL_ID, TONE_ID, PUNCT_ID,
+	VOICE_ID, FREQUENCY_ID,
+	DIRECT_ID, V_LAST_VAR_ID,
+	NB_ID
+};
+
+
+static struct var_t vars[NB_ID] = {
+	[CAPS_START_ID] = { CAPS_START, .u.s = {"\x01+35p" } },
+	[CAPS_STOP_ID] = { CAPS_STOP, .u.s = {"\x01-35p" } },
+	[RATE_ID] = { RATE, .u.n = {"\x01%ds", 8, 0, 9, 0, 0, NULL } },
+	[PITCH_ID] = { PITCH, .u.n = {"\x01%dp", 50, 0, 99, 0, 0, NULL } },
+	[VOL_ID] = { VOL, .u.n = {"\x01%dv", 5, 0, 9, 0, 0, NULL } },
+	[TONE_ID] = { TONE, .u.n = {"\x01%dx", 1, 0, 2, 0, 0, NULL } },
+	[PUNCT_ID] = { PUNCT, .u.n = {"\x01%db", 7, 0, 15, 0, 0, NULL } },
+	[VOICE_ID] = { VOICE, .u.n = {"\x01%do", 0, 0, 7, 0, 0, NULL } },
+	[FREQUENCY_ID] = { FREQUENCY, .u.n = {"\x01%df", 5, 0, 9, 0, 0, NULL } },
+	[DIRECT_ID] = { DIRECT, .u.n = {NULL, 0, 0, 1, 0, 0, NULL } },
+	V_LAST_VAR
+};
+
+/*
+ * These attributes will appear in /sys/accessibility/speakup/ltlk.
+ */
+static struct kobj_attribute caps_start_attribute =
+	__ATTR(caps_start, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute caps_stop_attribute =
+	__ATTR(caps_stop, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute freq_attribute =
+	__ATTR(freq, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute pitch_attribute =
+	__ATTR(pitch, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute punct_attribute =
+	__ATTR(punct, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute rate_attribute =
+	__ATTR(rate, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute tone_attribute =
+	__ATTR(tone, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute voice_attribute =
+	__ATTR(voice, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute vol_attribute =
+	__ATTR(vol, 0644, spk_var_show, spk_var_store);
+
+static struct kobj_attribute delay_time_attribute =
+	__ATTR(delay_time, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute direct_attribute =
+	__ATTR(direct, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute full_time_attribute =
+	__ATTR(full_time, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute jiffy_delta_attribute =
+	__ATTR(jiffy_delta, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute trigger_time_attribute =
+	__ATTR(trigger_time, 0644, spk_var_show, spk_var_store);
+
+/*
+ * Create a group of attributes so that we can create and destroy them all
+ * at once.
+ */
+static struct attribute *synth_attrs[] = {
+	&caps_start_attribute.attr,
+	&caps_stop_attribute.attr,
+	&freq_attribute.attr,
+	&pitch_attribute.attr,
+	&punct_attribute.attr,
+	&rate_attribute.attr,
+	&tone_attribute.attr,
+	&voice_attribute.attr,
+	&vol_attribute.attr,
+	&delay_time_attribute.attr,
+	&direct_attribute.attr,
+	&full_time_attribute.attr,
+	&jiffy_delta_attribute.attr,
+	&trigger_time_attribute.attr,
+	NULL,	/* need to NULL terminate the list of attributes */
+};
+
+static struct spk_synth synth_ltlk = {
+	.name = "ltlk",
+	.version = DRV_VERSION,
+	.long_name = "LiteTalk",
+	.init = "\01@\x01\x31y\n\0",
+	.procspeech = PROCSPEECH,
+	.clear = SYNTH_CLEAR,
+	.delay = 500,
+	.trigger = 50,
+	.jiffies = 50,
+	.full = 40000,
+	.dev_name = SYNTH_DEFAULT_DEV,
+	.startup = SYNTH_START,
+	.checkval = SYNTH_CHECK,
+	.vars = vars,
+	.io_ops = &spk_ttyio_ops,
+	.probe = synth_probe,
+	.release = spk_ttyio_release,
+	.synth_immediate = spk_ttyio_synth_immediate,
+	.catch_up = spk_do_catch_up,
+	.flush = spk_synth_flush,
+	.is_alive = spk_synth_is_alive_restart,
+	.synth_adjust = NULL,
+	.read_buff_add = NULL,
+	.get_index = spk_synth_get_index,
+	.indexing = {
+		.command = "\x01%di",
+		.lowindex = 1,
+		.highindex = 5,
+		.currindex = 1,
+	},
+	.attributes = {
+		.attrs = synth_attrs,
+		.name = "ltlk",
+	},
+};
+
+/* interrogate the LiteTalk and print its settings */
+static void synth_interrogate(struct spk_synth *synth)
+{
+	unsigned char *t, i;
+	unsigned char buf[50], rom_v[20];
+
+	synth->synth_immediate(synth, "\x18\x01?");
+	for (i = 0; i < 50; i++) {
+		buf[i] = synth->io_ops->synth_in(synth);
+		if (i > 2 && buf[i] == 0x7f)
+			break;
+	}
+	t = buf + 2;
+	for (i = 0; *t != '\r'; t++) {
+		rom_v[i] = *t;
+		if (++i >= 19)
+			break;
+	}
+	rom_v[i] = 0;
+	pr_info("%s: ROM version: %s\n", synth->long_name, rom_v);
+}
+
+static int synth_probe(struct spk_synth *synth)
+{
+	int failed = 0;
+
+	failed = spk_ttyio_synth_probe(synth);
+	if (failed == 0)
+		synth_interrogate(synth);
+	synth->alive = !failed;
+	return failed;
+}
+
+module_param_named(ser, synth_ltlk.ser, int, 0444);
+module_param_named(dev, synth_ltlk.dev_name, charp, 0444);
+module_param_named(start, synth_ltlk.startup, short, 0444);
+module_param_named(rate, vars[RATE_ID].u.n.default_val, int, 0444);
+module_param_named(pitch, vars[PITCH_ID].u.n.default_val, int, 0444);
+module_param_named(vol, vars[VOL_ID].u.n.default_val, int, 0444);
+module_param_named(tone, vars[TONE_ID].u.n.default_val, int, 0444);
+module_param_named(punct, vars[PUNCT_ID].u.n.default_val, int, 0444);
+module_param_named(voice, vars[VOICE_ID].u.n.default_val, int, 0444);
+module_param_named(frequency, vars[FREQUENCY_ID].u.n.default_val, int, 0444);
+module_param_named(direct, vars[DIRECT_ID].u.n.default_val, int, 0444);
+
+
+
+
+MODULE_PARM_DESC(ser, "Set the serial port for the synthesizer (0-based).");
+MODULE_PARM_DESC(dev, "Set the device e.g. ttyUSB0, for the synthesizer.");
+MODULE_PARM_DESC(start, "Start the synthesizer once it is loaded.");
+MODULE_PARM_DESC(rate, "Set the rate variable on load.");
+MODULE_PARM_DESC(pitch, "Set the pitch variable on load.");
+MODULE_PARM_DESC(vol, "Set the vol variable on load.");
+MODULE_PARM_DESC(tone, "Set the tone variable on load.");
+MODULE_PARM_DESC(punct, "Set the punct variable on load.");
+MODULE_PARM_DESC(voice, "Set the voice variable on load.");
+MODULE_PARM_DESC(frequency, "Set the frequency variable on load.");
+MODULE_PARM_DESC(direct, "Set the direct variable on load.");
+
+
+module_spk_synth(synth_ltlk);
+
+MODULE_AUTHOR("Kirk Reiser <kirk@braille.uwo.ca>");
+MODULE_AUTHOR("David Borowski");
+MODULE_DESCRIPTION("Speakup support for DoubleTalk LT/LiteTalk synthesizers");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(DRV_VERSION);
+
diff --git a/drivers/accessibility/speakup/speakup_soft.c b/drivers/accessibility/speakup/speakup_soft.c
new file mode 100644
index 000000000000..6d446824677b
--- /dev/null
+++ b/drivers/accessibility/speakup/speakup_soft.c
@@ -0,0 +1,491 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* speakup_soft.c - speakup driver to register and make available
+ * a user space device for software synthesizers.  written by: Kirk
+ * Reiser <kirk@braille.uwo.ca>
+ *
+ * Copyright (C) 2003  Kirk Reiser.
+ *
+ * this code is specifically written as a driver for the speakup screenreview
+ * package and is not a general device driver.
+ */
+
+#include <linux/unistd.h>
+#include <linux/miscdevice.h>	/* for misc_register, and MISC_DYNAMIC_MINOR */
+#include <linux/poll.h>		/* for poll_wait() */
+
+/* schedule(), signal_pending(), TASK_INTERRUPTIBLE */
+#include <linux/sched/signal.h>
+
+#include "spk_priv.h"
+#include "speakup.h"
+
+#define DRV_VERSION "2.6"
+#define PROCSPEECH 0x0d
+#define CLEAR_SYNTH 0x18
+
+static int softsynth_probe(struct spk_synth *synth);
+static void softsynth_release(struct spk_synth *synth);
+static int softsynth_is_alive(struct spk_synth *synth);
+static int softsynth_adjust(struct spk_synth *synth, struct st_var_header *var);
+static unsigned char get_index(struct spk_synth *synth);
+
+static struct miscdevice synth_device, synthu_device;
+static int init_pos;
+static int misc_registered;
+
+
+enum default_vars_id {
+	DIRECT_ID = 0, CAPS_START_ID, CAPS_STOP_ID,
+	PAUSE_ID, RATE_ID, PITCH_ID, INFLECTION_ID,
+	VOL_ID, TONE_ID, PUNCT_ID, VOICE_ID,
+	FREQUENCY_ID, V_LAST_VAR_ID,
+	 NB_ID
+};
+
+
+static struct var_t vars[NB_ID] = {
+
+	[DIRECT_ID]  = { DIRECT, .u.n = {NULL, 0, 0, 1, 0, 0, NULL } },
+	[CAPS_START_ID] = { CAPS_START, .u.s = {"\x01+3p" } },
+	[CAPS_STOP_ID]  = { CAPS_STOP, .u.s = {"\x01-3p" } },
+	[PAUSE_ID]  = { PAUSE, .u.n = {"\x01P" } },
+	[RATE_ID]  = { RATE, .u.n = {"\x01%ds", 2, 0, 9, 0, 0, NULL } },
+	[PITCH_ID]  = { PITCH, .u.n = {"\x01%dp", 5, 0, 9, 0, 0, NULL } },
+	[INFLECTION_ID]  = { INFLECTION, .u.n = {"\x01%dr", 5, 0, 9, 0, 0, NULL } },
+	[VOL_ID]  = { VOL, .u.n = {"\x01%dv", 5, 0, 9, 0, 0, NULL } },
+	[TONE_ID]  = { TONE, .u.n = {"\x01%dx", 1, 0, 2, 0, 0, NULL } },
+	[PUNCT_ID]  = { PUNCT, .u.n = {"\x01%db", 0, 0, 3, 0, 0, NULL } },
+	[VOICE_ID]  = { VOICE, .u.n = {"\x01%do", 0, 0, 7, 0, 0, NULL } },
+	[FREQUENCY_ID]  = { FREQUENCY, .u.n = {"\x01%df", 5, 0, 9, 0, 0, NULL } },
+	V_LAST_VAR
+};
+
+/* These attributes will appear in /sys/accessibility/speakup/soft. */
+
+static struct kobj_attribute caps_start_attribute =
+	__ATTR(caps_start, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute caps_stop_attribute =
+	__ATTR(caps_stop, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute freq_attribute =
+	__ATTR(freq, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute pitch_attribute =
+	__ATTR(pitch, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute inflection_attribute =
+	__ATTR(inflection, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute punct_attribute =
+	__ATTR(punct, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute rate_attribute =
+	__ATTR(rate, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute tone_attribute =
+	__ATTR(tone, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute voice_attribute =
+	__ATTR(voice, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute vol_attribute =
+	__ATTR(vol, 0644, spk_var_show, spk_var_store);
+
+/*
+ * We should uncomment the following definition, when we agree on a
+ * method of passing a language designation to the software synthesizer.
+ * static struct kobj_attribute lang_attribute =
+ *	__ATTR(lang, 0644, spk_var_show, spk_var_store);
+ */
+
+static struct kobj_attribute delay_time_attribute =
+	__ATTR(delay_time, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute direct_attribute =
+	__ATTR(direct, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute full_time_attribute =
+	__ATTR(full_time, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute jiffy_delta_attribute =
+	__ATTR(jiffy_delta, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute trigger_time_attribute =
+	__ATTR(trigger_time, 0644, spk_var_show, spk_var_store);
+
+/*
+ * Create a group of attributes so that we can create and destroy them all
+ * at once.
+ */
+static struct attribute *synth_attrs[] = {
+	&caps_start_attribute.attr,
+	&caps_stop_attribute.attr,
+	&freq_attribute.attr,
+/*	&lang_attribute.attr, */
+	&pitch_attribute.attr,
+	&inflection_attribute.attr,
+	&punct_attribute.attr,
+	&rate_attribute.attr,
+	&tone_attribute.attr,
+	&voice_attribute.attr,
+	&vol_attribute.attr,
+	&delay_time_attribute.attr,
+	&direct_attribute.attr,
+	&full_time_attribute.attr,
+	&jiffy_delta_attribute.attr,
+	&trigger_time_attribute.attr,
+	NULL,	/* need to NULL terminate the list of attributes */
+};
+
+static struct spk_synth synth_soft = {
+	.name = "soft",
+	.version = DRV_VERSION,
+	.long_name = "software synth",
+	.init = "\01@\x01\x31y\n",
+	.procspeech = PROCSPEECH,
+	.delay = 0,
+	.trigger = 0,
+	.jiffies = 0,
+	.full = 0,
+	.startup = SYNTH_START,
+	.checkval = SYNTH_CHECK,
+	.vars = vars,
+	.io_ops = NULL,
+	.probe = softsynth_probe,
+	.release = softsynth_release,
+	.synth_immediate = NULL,
+	.catch_up = NULL,
+	.flush = NULL,
+	.is_alive = softsynth_is_alive,
+	.synth_adjust = softsynth_adjust,
+	.read_buff_add = NULL,
+	.get_index = get_index,
+	.indexing = {
+		.command = "\x01%di",
+		.lowindex = 1,
+		.highindex = 5,
+		.currindex = 1,
+	},
+	.attributes = {
+		.attrs = synth_attrs,
+		.name = "soft",
+	},
+};
+
+static char *get_initstring(void)
+{
+	static char buf[40];
+	char *cp;
+	struct var_t *var;
+	size_t len;
+	size_t n;
+
+	memset(buf, 0, sizeof(buf));
+	cp = buf;
+	len = sizeof(buf);
+
+	var = synth_soft.vars;
+	while (var->var_id != MAXVARS) {
+		if (var->var_id != CAPS_START && var->var_id != CAPS_STOP &&
+		    var->var_id != PAUSE && var->var_id != DIRECT) {
+			n = scnprintf(cp, len, var->u.n.synth_fmt,
+				      var->u.n.value);
+			cp = cp + n;
+			len = len - n;
+		}
+		var++;
+	}
+	cp = cp + scnprintf(cp, len, "\n");
+	return buf;
+}
+
+static int softsynth_open(struct inode *inode, struct file *fp)
+{
+	unsigned long flags;
+	/*if ((fp->f_flags & O_ACCMODE) != O_RDONLY) */
+	/*	return -EPERM; */
+	spin_lock_irqsave(&speakup_info.spinlock, flags);
+	if (synth_soft.alive) {
+		spin_unlock_irqrestore(&speakup_info.spinlock, flags);
+		return -EBUSY;
+	}
+	synth_soft.alive = 1;
+	spin_unlock_irqrestore(&speakup_info.spinlock, flags);
+	return 0;
+}
+
+static int softsynth_close(struct inode *inode, struct file *fp)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&speakup_info.spinlock, flags);
+	synth_soft.alive = 0;
+	init_pos = 0;
+	spin_unlock_irqrestore(&speakup_info.spinlock, flags);
+	/* Make sure we let applications go before leaving */
+	speakup_start_ttys();
+	return 0;
+}
+
+static ssize_t softsynthx_read(struct file *fp, char __user *buf, size_t count,
+			       loff_t *pos, int unicode)
+{
+	int chars_sent = 0;
+	char __user *cp;
+	char *init;
+	size_t bytes_per_ch = unicode ? 3 : 1;
+	u16 ch;
+	int empty;
+	unsigned long flags;
+	DEFINE_WAIT(wait);
+
+	if (count < bytes_per_ch)
+		return -EINVAL;
+
+	spin_lock_irqsave(&speakup_info.spinlock, flags);
+	synth_soft.alive = 1;
+	while (1) {
+		prepare_to_wait(&speakup_event, &wait, TASK_INTERRUPTIBLE);
+		if (synth_current() == &synth_soft) {
+			if (!unicode)
+				synth_buffer_skip_nonlatin1();
+			if (!synth_buffer_empty() || speakup_info.flushing)
+				break;
+		}
+		spin_unlock_irqrestore(&speakup_info.spinlock, flags);
+		if (fp->f_flags & O_NONBLOCK) {
+			finish_wait(&speakup_event, &wait);
+			return -EAGAIN;
+		}
+		if (signal_pending(current)) {
+			finish_wait(&speakup_event, &wait);
+			return -ERESTARTSYS;
+		}
+		schedule();
+		spin_lock_irqsave(&speakup_info.spinlock, flags);
+	}
+	finish_wait(&speakup_event, &wait);
+
+	cp = buf;
+	init = get_initstring();
+
+	/* Keep 3 bytes available for a 16bit UTF-8-encoded character */
+	while (chars_sent <= count - bytes_per_ch) {
+		if (synth_current() != &synth_soft)
+			break;
+		if (speakup_info.flushing) {
+			speakup_info.flushing = 0;
+			ch = '\x18';
+		} else if (init[init_pos]) {
+			ch = init[init_pos++];
+		} else {
+			if (!unicode)
+				synth_buffer_skip_nonlatin1();
+			if (synth_buffer_empty())
+				break;
+			ch = synth_buffer_getc();
+		}
+		spin_unlock_irqrestore(&speakup_info.spinlock, flags);
+
+		if ((!unicode && ch < 0x100) || (unicode && ch < 0x80)) {
+			u_char c = ch;
+
+			if (copy_to_user(cp, &c, 1))
+				return -EFAULT;
+
+			chars_sent++;
+			cp++;
+		} else if (unicode && ch < 0x800) {
+			u_char s[2] = {
+				0xc0 | (ch >> 6),
+				0x80 | (ch & 0x3f)
+			};
+
+			if (copy_to_user(cp, s, sizeof(s)))
+				return -EFAULT;
+
+			chars_sent += sizeof(s);
+			cp += sizeof(s);
+		} else if (unicode) {
+			u_char s[3] = {
+				0xe0 | (ch >> 12),
+				0x80 | ((ch >> 6) & 0x3f),
+				0x80 | (ch & 0x3f)
+			};
+
+			if (copy_to_user(cp, s, sizeof(s)))
+				return -EFAULT;
+
+			chars_sent += sizeof(s);
+			cp += sizeof(s);
+		}
+
+		spin_lock_irqsave(&speakup_info.spinlock, flags);
+	}
+	*pos += chars_sent;
+	empty = synth_buffer_empty();
+	spin_unlock_irqrestore(&speakup_info.spinlock, flags);
+	if (empty) {
+		speakup_start_ttys();
+		*pos = 0;
+	}
+	return chars_sent;
+}
+
+static ssize_t softsynth_read(struct file *fp, char __user *buf, size_t count,
+			      loff_t *pos)
+{
+	return softsynthx_read(fp, buf, count, pos, 0);
+}
+
+static ssize_t softsynthu_read(struct file *fp, char __user *buf, size_t count,
+			       loff_t *pos)
+{
+	return softsynthx_read(fp, buf, count, pos, 1);
+}
+
+static int last_index;
+
+static ssize_t softsynth_write(struct file *fp, const char __user *buf,
+			       size_t count, loff_t *pos)
+{
+	unsigned long supplied_index = 0;
+	int converted;
+
+	converted = kstrtoul_from_user(buf, count, 0, &supplied_index);
+
+	if (converted < 0)
+		return converted;
+
+	last_index = supplied_index;
+	return count;
+}
+
+static __poll_t softsynth_poll(struct file *fp, struct poll_table_struct *wait)
+{
+	unsigned long flags;
+	__poll_t ret = 0;
+
+	poll_wait(fp, &speakup_event, wait);
+
+	spin_lock_irqsave(&speakup_info.spinlock, flags);
+	if (synth_current() == &synth_soft &&
+	    (!synth_buffer_empty() || speakup_info.flushing))
+		ret = EPOLLIN | EPOLLRDNORM;
+	spin_unlock_irqrestore(&speakup_info.spinlock, flags);
+	return ret;
+}
+
+static unsigned char get_index(struct spk_synth *synth)
+{
+	int rv;
+
+	rv = last_index;
+	last_index = 0;
+	return rv;
+}
+
+static const struct file_operations softsynth_fops = {
+	.owner = THIS_MODULE,
+	.poll = softsynth_poll,
+	.read = softsynth_read,
+	.write = softsynth_write,
+	.open = softsynth_open,
+	.release = softsynth_close,
+};
+
+static const struct file_operations softsynthu_fops = {
+	.owner = THIS_MODULE,
+	.poll = softsynth_poll,
+	.read = softsynthu_read,
+	.write = softsynth_write,
+	.open = softsynth_open,
+	.release = softsynth_close,
+};
+
+static int softsynth_probe(struct spk_synth *synth)
+{
+	if (misc_registered != 0)
+		return 0;
+	memset(&synth_device, 0, sizeof(synth_device));
+	synth_device.minor = MISC_DYNAMIC_MINOR;
+	synth_device.name = "softsynth";
+	synth_device.fops = &softsynth_fops;
+	if (misc_register(&synth_device)) {
+		pr_warn("Couldn't initialize miscdevice /dev/softsynth.\n");
+		return -ENODEV;
+	}
+
+	memset(&synthu_device, 0, sizeof(synthu_device));
+	synthu_device.minor = MISC_DYNAMIC_MINOR;
+	synthu_device.name = "softsynthu";
+	synthu_device.fops = &softsynthu_fops;
+	if (misc_register(&synthu_device)) {
+		misc_deregister(&synth_device);
+		pr_warn("Couldn't initialize miscdevice /dev/softsynthu.\n");
+		return -ENODEV;
+	}
+
+	misc_registered = 1;
+	pr_info("initialized device: /dev/softsynth, node (MAJOR 10, MINOR %d)\n",
+		synth_device.minor);
+	pr_info("initialized device: /dev/softsynthu, node (MAJOR 10, MINOR %d)\n",
+		synthu_device.minor);
+	return 0;
+}
+
+static void softsynth_release(struct spk_synth *synth)
+{
+	misc_deregister(&synth_device);
+	misc_deregister(&synthu_device);
+	misc_registered = 0;
+	pr_info("unregistered /dev/softsynth\n");
+	pr_info("unregistered /dev/softsynthu\n");
+}
+
+static int softsynth_is_alive(struct spk_synth *synth)
+{
+	if (synth_soft.alive)
+		return 1;
+	return 0;
+}
+
+static int softsynth_adjust(struct spk_synth *synth, struct st_var_header *var)
+{
+	struct st_var_header *punc_level_var;
+	struct var_t *var_data;
+
+	if (var->var_id != PUNC_LEVEL)
+		return 0;
+
+	/* We want to set the the speech synthesis punctuation level
+	 * accordingly, so it properly tunes speaking A_PUNC characters */
+	var_data = var->data;
+	if (!var_data)
+		return 0;
+	punc_level_var = spk_get_var_header(PUNCT);
+	if (!punc_level_var)
+		return 0;
+	spk_set_num_var(var_data->u.n.value, punc_level_var, E_SET);
+
+	return 1;
+}
+
+module_param_named(start, synth_soft.startup, short, 0444);
+module_param_named(direct, vars[DIRECT_ID].u.n.default_val, int, 0444);
+module_param_named(rate, vars[RATE_ID].u.n.default_val, int, 0444);
+module_param_named(pitch, vars[PITCH_ID].u.n.default_val, int, 0444);
+module_param_named(inflection, vars[INFLECTION_ID].u.n.default_val, int, 0444);
+module_param_named(vol, vars[VOL_ID].u.n.default_val, int, 0444);
+module_param_named(tone, vars[TONE_ID].u.n.default_val, int, 0444);
+module_param_named(punct, vars[PUNCT_ID].u.n.default_val, int, 0444);
+module_param_named(voice, vars[VOICE_ID].u.n.default_val, int, 0444);
+module_param_named(frequency, vars[FREQUENCY_ID].u.n.default_val, int, 0444);
+
+
+
+MODULE_PARM_DESC(start, "Start the synthesizer once it is loaded.");
+MODULE_PARM_DESC(direct, "Set the direct variable on load.");
+MODULE_PARM_DESC(rate, "Sets the rate of the synthesizer.");
+MODULE_PARM_DESC(pitch, "Sets the pitch of the synthesizer.");
+MODULE_PARM_DESC(inflection, "Sets the inflection of the synthesizer.");
+MODULE_PARM_DESC(vol, "Sets the volume of the speech synthesizer.");
+MODULE_PARM_DESC(tone, "Sets the tone of the speech synthesizer.");
+MODULE_PARM_DESC(punct, "Sets the amount of punctuation spoken by the synthesizer.");
+MODULE_PARM_DESC(voice, "Sets the voice used by the synthesizer.");
+MODULE_PARM_DESC(frequency, "Sets the frequency of speech synthesizer.");
+
+module_spk_synth(synth_soft);
+
+MODULE_AUTHOR("Kirk Reiser <kirk@braille.uwo.ca>");
+MODULE_DESCRIPTION("Speakup userspace software synthesizer support");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(DRV_VERSION);
diff --git a/drivers/accessibility/speakup/speakup_spkout.c b/drivers/accessibility/speakup/speakup_spkout.c
new file mode 100644
index 000000000000..d3f26095b0ee
--- /dev/null
+++ b/drivers/accessibility/speakup/speakup_spkout.c
@@ -0,0 +1,164 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * originally written by: Kirk Reiser <kirk@braille.uwo.ca>
+ * this version considerably modified by David Borowski, david575@rogers.com
+ *
+ * Copyright (C) 1998-99  Kirk Reiser.
+ * Copyright (C) 2003 David Borowski.
+ *
+ * specifically written as a driver for the speakup screenreview
+ * s not a general device driver.
+ */
+#include "spk_priv.h"
+#include "speakup.h"
+
+#define DRV_VERSION "2.11"
+#define SYNTH_CLEAR 0x18
+#define PROCSPEECH '\r'
+
+static void synth_flush(struct spk_synth *synth);
+
+
+
+enum default_vars_id {
+	CAPS_START_ID = 0, CAPS_STOP_ID,
+	RATE_ID, PITCH_ID,
+	VOL_ID, TONE_ID, PUNCT_ID,
+	DIRECT_ID, V_LAST_VAR_ID,
+	NB_ID
+};
+
+
+static struct var_t vars[NB_ID] = {
+	[CAPS_START_ID] = { CAPS_START, .u.s = {"\x05P+" } },
+	[CAPS_STOP_ID] = { CAPS_STOP, .u.s = {"\x05P-" } },
+	[RATE_ID] = { RATE, .u.n = {"\x05R%d", 7, 0, 9, 0, 0, NULL } },
+	[PITCH_ID] = { PITCH, .u.n = {"\x05P%d", 3, 0, 9, 0, 0, NULL } },
+	[VOL_ID] = { VOL, .u.n = {"\x05V%d", 9, 0, 9, 0, 0, NULL } },
+	[TONE_ID] = { TONE, .u.n = {"\x05T%c", 8, 0, 25, 65, 0, NULL } },
+	[PUNCT_ID] = { PUNCT, .u.n = {"\x05M%c", 0, 0, 3, 0, 0, "nsma" } },
+	[DIRECT_ID] = { DIRECT, .u.n = {NULL, 0, 0, 1, 0, 0, NULL } },
+	V_LAST_VAR
+};
+
+/* These attributes will appear in /sys/accessibility/speakup/spkout. */
+
+static struct kobj_attribute caps_start_attribute =
+	__ATTR(caps_start, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute caps_stop_attribute =
+	__ATTR(caps_stop, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute pitch_attribute =
+	__ATTR(pitch, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute punct_attribute =
+	__ATTR(punct, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute rate_attribute =
+	__ATTR(rate, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute tone_attribute =
+	__ATTR(tone, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute vol_attribute =
+	__ATTR(vol, 0644, spk_var_show, spk_var_store);
+
+static struct kobj_attribute delay_time_attribute =
+	__ATTR(delay_time, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute direct_attribute =
+	__ATTR(direct, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute full_time_attribute =
+	__ATTR(full_time, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute jiffy_delta_attribute =
+	__ATTR(jiffy_delta, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute trigger_time_attribute =
+	__ATTR(trigger_time, 0644, spk_var_show, spk_var_store);
+
+/*
+ * Create a group of attributes so that we can create and destroy them all
+ * at once.
+ */
+static struct attribute *synth_attrs[] = {
+	&caps_start_attribute.attr,
+	&caps_stop_attribute.attr,
+	&pitch_attribute.attr,
+	&punct_attribute.attr,
+	&rate_attribute.attr,
+	&tone_attribute.attr,
+	&vol_attribute.attr,
+	&delay_time_attribute.attr,
+	&direct_attribute.attr,
+	&full_time_attribute.attr,
+	&jiffy_delta_attribute.attr,
+	&trigger_time_attribute.attr,
+	NULL,	/* need to NULL terminate the list of attributes */
+};
+
+static struct spk_synth synth_spkout = {
+	.name = "spkout",
+	.version = DRV_VERSION,
+	.long_name = "Speakout",
+	.init = "\005W1\005I2\005C3",
+	.procspeech = PROCSPEECH,
+	.clear = SYNTH_CLEAR,
+	.delay = 500,
+	.trigger = 50,
+	.jiffies = 50,
+	.full = 40000,
+	.dev_name = SYNTH_DEFAULT_DEV,
+	.startup = SYNTH_START,
+	.checkval = SYNTH_CHECK,
+	.vars = vars,
+	.io_ops = &spk_ttyio_ops,
+	.probe = spk_ttyio_synth_probe,
+	.release = spk_ttyio_release,
+	.synth_immediate = spk_ttyio_synth_immediate,
+	.catch_up = spk_do_catch_up,
+	.flush = synth_flush,
+	.is_alive = spk_synth_is_alive_restart,
+	.synth_adjust = NULL,
+	.read_buff_add = NULL,
+	.get_index = spk_synth_get_index,
+	.indexing = {
+		.command = "\x05[%c",
+		.lowindex = 1,
+		.highindex = 5,
+		.currindex = 1,
+	},
+	.attributes = {
+		.attrs = synth_attrs,
+		.name = "spkout",
+	},
+};
+
+static void synth_flush(struct spk_synth *synth)
+{
+	synth->io_ops->flush_buffer(synth);
+	synth->io_ops->send_xchar(synth, SYNTH_CLEAR);
+}
+
+module_param_named(ser, synth_spkout.ser, int, 0444);
+module_param_named(dev, synth_spkout.dev_name, charp, 0444);
+module_param_named(start, synth_spkout.startup, short, 0444);
+module_param_named(rate, vars[RATE_ID].u.n.default_val, int, 0444);
+module_param_named(vol, vars[PITCH_ID].u.n.default_val, int, 0444);
+module_param_named(tone, vars[TONE_ID].u.n.default_val, int, 0444);
+module_param_named(punct, vars[PUNCT_ID].u.n.default_val, int, 0444);
+module_param_named(direct, vars[DIRECT_ID].u.n.default_val, int, 0444);
+
+
+
+MODULE_PARM_DESC(ser, "Set the serial port for the synthesizer (0-based).");
+MODULE_PARM_DESC(dev, "Set the device e.g. ttyUSB0, for the synthesizer.");
+MODULE_PARM_DESC(start, "Start the synthesizer once it is loaded.");
+MODULE_PARM_DESC(rate, "Set the rate variable on load.");
+MODULE_PARM_DESC(vol, "Set the vol variable on load.");
+MODULE_PARM_DESC(tone, "Set the tone variable on load.");
+MODULE_PARM_DESC(punct, "Set the punct variable on load.");
+MODULE_PARM_DESC(direct, "Set the direct variable on load.");
+
+
+
+module_spk_synth(synth_spkout);
+
+MODULE_AUTHOR("Kirk Reiser <kirk@braille.uwo.ca>");
+MODULE_AUTHOR("David Borowski");
+MODULE_DESCRIPTION("Speakup support for Speak Out synthesizers");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(DRV_VERSION);
+
diff --git a/drivers/accessibility/speakup/speakup_txprt.c b/drivers/accessibility/speakup/speakup_txprt.c
new file mode 100644
index 000000000000..4d0a0d4c41f0
--- /dev/null
+++ b/drivers/accessibility/speakup/speakup_txprt.c
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * originally written by: Kirk Reiser <kirk@braille.uwo.ca>
+ * this version considerably modified by David Borowski, david575@rogers.com
+ *
+ * Copyright (C) 1998-99  Kirk Reiser.
+ * Copyright (C) 2003 David Borowski.
+ *
+ * specifically written as a driver for the speakup screenreview
+ * s not a general device driver.
+ */
+#include "spk_priv.h"
+#include "speakup.h"
+
+#define DRV_VERSION "2.11"
+#define SYNTH_CLEAR 0x18
+#define PROCSPEECH '\r' /* process speech char */
+
+
+
+
+enum default_vars_id {
+	CAPS_START_ID = 0, CAPS_STOP_ID,
+	RATE_ID, PITCH_ID,
+	VOL_ID, TONE_ID,
+	DIRECT_ID, V_LAST_VAR_ID,
+	NB_ID
+};
+
+
+
+
+
+static struct var_t vars[NB_ID] = {
+	[CAPS_START_ID] = { CAPS_START, .u.s = {"\x05P8" } },
+	[CAPS_STOP_ID] = { CAPS_STOP, .u.s = {"\x05P5" } },
+	[RATE_ID] = { RATE, .u.n = {"\x05R%d", 5, 0, 9, 0, 0, NULL } },
+	[PITCH_ID] = { PITCH, .u.n = {"\x05P%d", 5, 0, 9, 0, 0, NULL } },
+	[VOL_ID] = { VOL, .u.n = {"\x05V%d", 5, 0, 9, 0, 0, NULL } },
+	[TONE_ID] = { TONE, .u.n = {"\x05T%c", 12, 0, 25, 61, 0, NULL } },
+	[DIRECT_ID] = { DIRECT, .u.n = {NULL, 0, 0, 1, 0, 0, NULL } },
+	V_LAST_VAR
+	 };
+
+/* These attributes will appear in /sys/accessibility/speakup/txprt. */
+
+static struct kobj_attribute caps_start_attribute =
+	__ATTR(caps_start, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute caps_stop_attribute =
+	__ATTR(caps_stop, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute pitch_attribute =
+	__ATTR(pitch, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute rate_attribute =
+	__ATTR(rate, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute tone_attribute =
+	__ATTR(tone, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute vol_attribute =
+	__ATTR(vol, 0644, spk_var_show, spk_var_store);
+
+static struct kobj_attribute delay_time_attribute =
+	__ATTR(delay_time, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute direct_attribute =
+	__ATTR(direct, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute full_time_attribute =
+	__ATTR(full_time, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute jiffy_delta_attribute =
+	__ATTR(jiffy_delta, 0644, spk_var_show, spk_var_store);
+static struct kobj_attribute trigger_time_attribute =
+	__ATTR(trigger_time, 0644, spk_var_show, spk_var_store);
+
+/*
+ * Create a group of attributes so that we can create and destroy them all
+ * at once.
+ */
+static struct attribute *synth_attrs[] = {
+	&caps_start_attribute.attr,
+	&caps_stop_attribute.attr,
+	&pitch_attribute.attr,
+	&rate_attribute.attr,
+	&tone_attribute.attr,
+	&vol_attribute.attr,
+	&delay_time_attribute.attr,
+	&direct_attribute.attr,
+	&full_time_attribute.attr,
+	&jiffy_delta_attribute.attr,
+	&trigger_time_attribute.attr,
+	NULL,	/* need to NULL terminate the list of attributes */
+};
+
+static struct spk_synth synth_txprt = {
+	.name = "txprt",
+	.version = DRV_VERSION,
+	.long_name = "Transport",
+	.init = "\x05N1",
+	.procspeech = PROCSPEECH,
+	.clear = SYNTH_CLEAR,
+	.delay = 500,
+	.trigger = 50,
+	.jiffies = 50,
+	.full = 40000,
+	.dev_name = SYNTH_DEFAULT_DEV,
+	.startup = SYNTH_START,
+	.checkval = SYNTH_CHECK,
+	.vars = vars,
+	.io_ops = &spk_ttyio_ops,
+	.probe = spk_ttyio_synth_probe,
+	.release = spk_ttyio_release,
+	.synth_immediate = spk_ttyio_synth_immediate,
+	.catch_up = spk_do_catch_up,
+	.flush = spk_synth_flush,
+	.is_alive = spk_synth_is_alive_restart,
+	.synth_adjust = NULL,
+	.read_buff_add = NULL,
+	.get_index = NULL,
+	.indexing = {
+		.command = NULL,
+		.lowindex = 0,
+		.highindex = 0,
+		.currindex = 0,
+	},
+	.attributes = {
+		.attrs = synth_attrs,
+		.name = "txprt",
+	},
+};
+
+module_param_named(ser, synth_txprt.ser, int, 0444);
+module_param_named(dev, synth_txprt.dev_name, charp, 0444);
+module_param_named(start, synth_txprt.startup, short, 0444);
+module_param_named(rate, vars[RATE_ID].u.n.default_val, int, 0444);
+module_param_named(pitch, vars[PITCH_ID].u.n.default_val, int, 0444);
+module_param_named(vol, vars[VOL_ID].u.n.default_val, int, 0444);
+module_param_named(tone, vars[TONE_ID].u.n.default_val, int, 0444);
+module_param_named(direct, vars[DIRECT_ID].u.n.default_val, int, 0444);
+
+
+
+MODULE_PARM_DESC(ser, "Set the serial port for the synthesizer (0-based).");
+MODULE_PARM_DESC(dev, "Set the device e.g. ttyUSB0, for the synthesizer.");
+MODULE_PARM_DESC(start, "Start the synthesizer once it is loaded.");
+MODULE_PARM_DESC(rate, "Set the rate variable on load.");
+MODULE_PARM_DESC(pitch, "Set the pitch variable on load.");
+MODULE_PARM_DESC(vol, "Set the vol variable on load.");
+MODULE_PARM_DESC(tone, "Set the tone variable on load.");
+MODULE_PARM_DESC(direct, "Set the direct variable on load.");
+
+
+
+module_spk_synth(synth_txprt);
+
+MODULE_AUTHOR("Kirk Reiser <kirk@braille.uwo.ca>");
+MODULE_AUTHOR("David Borowski");
+MODULE_DESCRIPTION("Speakup support for Transport synthesizers");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(DRV_VERSION);
+
diff --git a/drivers/staging/speakup/speakupmap.map b/drivers/accessibility/speakup/speakupmap.map
index f10d44cf5d7a..f10d44cf5d7a 100644
--- a/drivers/staging/speakup/speakupmap.map
+++ b/drivers/accessibility/speakup/speakupmap.map
diff --git a/drivers/staging/speakup/spk_priv.h b/drivers/accessibility/speakup/spk_priv.h
index c75b40838794..9da57ead17cb 100644
--- a/drivers/staging/speakup/spk_priv.h
+++ b/drivers/accessibility/speakup/spk_priv.h
@@ -34,9 +34,8 @@
 
 const struct old_serial_port *spk_serial_init(int index);
 void spk_stop_serial_interrupt(void);
-int spk_wait_for_xmitr(struct spk_synth *in_synth);
-void spk_serial_release(void);
-void spk_ttyio_release(void);
+void spk_serial_release(struct spk_synth *synth);
+void spk_ttyio_release(struct spk_synth *synth);
 void spk_ttyio_register_ldisc(void);
 void spk_ttyio_unregister_ldisc(void);
 
diff --git a/drivers/staging/speakup/spk_priv_keyinfo.h b/drivers/accessibility/speakup/spk_priv_keyinfo.h
index 1f789bd1c678..1f789bd1c678 100644
--- a/drivers/staging/speakup/spk_priv_keyinfo.h
+++ b/drivers/accessibility/speakup/spk_priv_keyinfo.h
diff --git a/drivers/accessibility/speakup/spk_ttyio.c b/drivers/accessibility/speakup/spk_ttyio.c
new file mode 100644
index 000000000000..4c0a6e1f019d
--- /dev/null
+++ b/drivers/accessibility/speakup/spk_ttyio.c
@@ -0,0 +1,387 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <linux/types.h>
+#include <linux/tty.h>
+#include <linux/tty_flip.h>
+#include <linux/slab.h>
+
+#include "speakup.h"
+#include "spk_types.h"
+#include "spk_priv.h"
+
+struct spk_ldisc_data {
+	char buf;
+	struct completion completion;
+	bool buf_free;
+	struct spk_synth *synth;
+};
+
+/*
+ * This allows to catch within spk_ttyio_ldisc_open whether it is getting set
+ * on for a speakup-driven device.
+ */
+static struct tty_struct *speakup_tty;
+/* This mutex serializes the use of such global speakup_tty variable */
+static DEFINE_MUTEX(speakup_tty_mutex);
+
+static int ser_to_dev(int ser, dev_t *dev_no)
+{
+	if (ser < 0 || ser > (255 - 64)) {
+		pr_err("speakup: Invalid ser param. Must be between 0 and 191 inclusive.\n");
+		return -EINVAL;
+	}
+
+	*dev_no = MKDEV(4, (64 + ser));
+	return 0;
+}
+
+static int get_dev_to_use(struct spk_synth *synth, dev_t *dev_no)
+{
+	/* use ser only when dev is not specified */
+	if (strcmp(synth->dev_name, SYNTH_DEFAULT_DEV) ||
+	    synth->ser == SYNTH_DEFAULT_SER)
+		return tty_dev_name_to_number(synth->dev_name, dev_no);
+
+	return ser_to_dev(synth->ser, dev_no);
+}
+
+static int spk_ttyio_ldisc_open(struct tty_struct *tty)
+{
+	struct spk_ldisc_data *ldisc_data;
+
+	if (tty != speakup_tty)
+		/* Somebody tried to use this line discipline outside speakup */
+		return -ENODEV;
+
+	if (!tty->ops->write)
+		return -EOPNOTSUPP;
+
+	ldisc_data = kmalloc(sizeof(*ldisc_data), GFP_KERNEL);
+	if (!ldisc_data)
+		return -ENOMEM;
+
+	init_completion(&ldisc_data->completion);
+	ldisc_data->buf_free = true;
+	tty->disc_data = ldisc_data;
+
+	return 0;
+}
+
+static void spk_ttyio_ldisc_close(struct tty_struct *tty)
+{
+	kfree(tty->disc_data);
+}
+
+static size_t spk_ttyio_receive_buf2(struct tty_struct *tty, const u8 *cp,
+				     const u8 *fp, size_t count)
+{
+	struct spk_ldisc_data *ldisc_data = tty->disc_data;
+	struct spk_synth *synth = ldisc_data->synth;
+
+	if (synth->read_buff_add) {
+		unsigned int i;
+
+		for (i = 0; i < count; i++)
+			synth->read_buff_add(cp[i]);
+
+		return count;
+	}
+
+	if (!ldisc_data->buf_free)
+		/* ttyio_in will tty_flip_buffer_push */
+		return 0;
+
+	/* Make sure the consumer has read buf before we have seen
+	 * buf_free == true and overwrite buf
+	 */
+	mb();
+
+	ldisc_data->buf = cp[0];
+	ldisc_data->buf_free = false;
+	complete(&ldisc_data->completion);
+
+	return 1;
+}
+
+static struct tty_ldisc_ops spk_ttyio_ldisc_ops = {
+	.owner          = THIS_MODULE,
+	.num		= N_SPEAKUP,
+	.name           = "speakup_ldisc",
+	.open           = spk_ttyio_ldisc_open,
+	.close          = spk_ttyio_ldisc_close,
+	.receive_buf2	= spk_ttyio_receive_buf2,
+};
+
+static int spk_ttyio_out(struct spk_synth *in_synth, const char ch);
+static int spk_ttyio_out_unicode(struct spk_synth *in_synth, u16 ch);
+static void spk_ttyio_send_xchar(struct spk_synth *in_synth, char ch);
+static void spk_ttyio_tiocmset(struct spk_synth *in_synth, unsigned int set, unsigned int clear);
+static unsigned char spk_ttyio_in(struct spk_synth *in_synth);
+static unsigned char spk_ttyio_in_nowait(struct spk_synth *in_synth);
+static void spk_ttyio_flush_buffer(struct spk_synth *in_synth);
+static int spk_ttyio_wait_for_xmitr(struct spk_synth *in_synth);
+
+struct spk_io_ops spk_ttyio_ops = {
+	.synth_out = spk_ttyio_out,
+	.synth_out_unicode = spk_ttyio_out_unicode,
+	.send_xchar = spk_ttyio_send_xchar,
+	.tiocmset = spk_ttyio_tiocmset,
+	.synth_in = spk_ttyio_in,
+	.synth_in_nowait = spk_ttyio_in_nowait,
+	.flush_buffer = spk_ttyio_flush_buffer,
+	.wait_for_xmitr = spk_ttyio_wait_for_xmitr,
+};
+EXPORT_SYMBOL_GPL(spk_ttyio_ops);
+
+static inline void get_termios(struct tty_struct *tty,
+			       struct ktermios *out_termios)
+{
+	down_read(&tty->termios_rwsem);
+	*out_termios = tty->termios;
+	up_read(&tty->termios_rwsem);
+}
+
+static int spk_ttyio_initialise_ldisc(struct spk_synth *synth)
+{
+	int ret = 0;
+	struct tty_struct *tty;
+	struct ktermios tmp_termios;
+	dev_t dev;
+
+	ret = get_dev_to_use(synth, &dev);
+	if (ret)
+		return ret;
+
+	tty = tty_kopen_exclusive(dev);
+	if (IS_ERR(tty))
+		return PTR_ERR(tty);
+
+	if (tty->ops->open)
+		ret = tty->ops->open(tty, NULL);
+	else
+		ret = -ENODEV;
+
+	if (ret) {
+		tty_unlock(tty);
+		return ret;
+	}
+
+	clear_bit(TTY_HUPPED, &tty->flags);
+	/* ensure hardware flow control is enabled */
+	get_termios(tty, &tmp_termios);
+	if (!(tmp_termios.c_cflag & CRTSCTS)) {
+		tmp_termios.c_cflag |= CRTSCTS;
+		tty_set_termios(tty, &tmp_termios);
+		/*
+		 * check c_cflag to see if it's updated as tty_set_termios
+		 * may not return error even when no tty bits are
+		 * changed by the request.
+		 */
+		get_termios(tty, &tmp_termios);
+		if (!(tmp_termios.c_cflag & CRTSCTS))
+			pr_warn("speakup: Failed to set hardware flow control\n");
+	}
+
+	tty_unlock(tty);
+
+	mutex_lock(&speakup_tty_mutex);
+	speakup_tty = tty;
+	ret = tty_set_ldisc(tty, N_SPEAKUP);
+	speakup_tty = NULL;
+	mutex_unlock(&speakup_tty_mutex);
+
+	if (!ret) {
+		/* Success */
+		struct spk_ldisc_data *ldisc_data = tty->disc_data;
+
+		ldisc_data->synth = synth;
+		synth->dev = tty;
+		return 0;
+	}
+
+	pr_err("speakup: Failed to set N_SPEAKUP on tty\n");
+
+	tty_lock(tty);
+	if (tty->ops->close)
+		tty->ops->close(tty, NULL);
+	tty_unlock(tty);
+
+	tty_kclose(tty);
+
+	return ret;
+}
+
+void spk_ttyio_register_ldisc(void)
+{
+	if (tty_register_ldisc(&spk_ttyio_ldisc_ops))
+		pr_warn("speakup: Error registering line discipline. Most synths won't work.\n");
+}
+
+void spk_ttyio_unregister_ldisc(void)
+{
+	tty_unregister_ldisc(&spk_ttyio_ldisc_ops);
+}
+
+static int spk_ttyio_out(struct spk_synth *in_synth, const char ch)
+{
+	struct tty_struct *tty = in_synth->dev;
+	int ret;
+
+	if (!in_synth->alive || !tty->ops->write)
+		return 0;
+
+	ret = tty->ops->write(tty, &ch, 1);
+
+	if (ret == 0)
+		/* No room */
+		return 0;
+
+	if (ret > 0)
+		/* Success */
+		return 1;
+
+	pr_warn("%s: I/O error, deactivating speakup\n",
+		in_synth->long_name);
+	/* No synth any more, so nobody will restart TTYs,
+	 * and we thus need to do it ourselves.  Now that there
+	 * is no synth we can let application flood anyway
+	 */
+	in_synth->alive = 0;
+	speakup_start_ttys();
+	return 0;
+}
+
+static int spk_ttyio_out_unicode(struct spk_synth *in_synth, u16 ch)
+{
+	int ret;
+
+	if (ch < 0x80) {
+		ret = spk_ttyio_out(in_synth, ch);
+	} else if (ch < 0x800) {
+		ret  = spk_ttyio_out(in_synth, 0xc0 | (ch >> 6));
+		ret &= spk_ttyio_out(in_synth, 0x80 | (ch & 0x3f));
+	} else {
+		ret  = spk_ttyio_out(in_synth, 0xe0 | (ch >> 12));
+		ret &= spk_ttyio_out(in_synth, 0x80 | ((ch >> 6) & 0x3f));
+		ret &= spk_ttyio_out(in_synth, 0x80 | (ch & 0x3f));
+	}
+	return ret;
+}
+
+static void spk_ttyio_send_xchar(struct spk_synth *in_synth, char ch)
+{
+	struct tty_struct *tty = in_synth->dev;
+
+	if (tty->ops->send_xchar)
+		tty->ops->send_xchar(tty, ch);
+}
+
+static void spk_ttyio_tiocmset(struct spk_synth *in_synth, unsigned int set, unsigned int clear)
+{
+	struct tty_struct *tty = in_synth->dev;
+
+	if (tty->ops->tiocmset)
+		tty->ops->tiocmset(tty, set, clear);
+}
+
+static int spk_ttyio_wait_for_xmitr(struct spk_synth *in_synth)
+{
+	return 1;
+}
+
+static unsigned char ttyio_in(struct spk_synth *in_synth, int timeout)
+{
+	struct tty_struct *tty = in_synth->dev;
+	struct spk_ldisc_data *ldisc_data = tty->disc_data;
+	char rv;
+
+	if (!timeout) {
+		if (!try_wait_for_completion(&ldisc_data->completion))
+			return 0xff;
+	} else if (wait_for_completion_timeout(&ldisc_data->completion,
+					usecs_to_jiffies(timeout)) == 0) {
+		pr_warn("spk_ttyio: timeout (%d)  while waiting for input\n",
+			timeout);
+		return 0xff;
+	}
+
+	rv = ldisc_data->buf;
+	/* Make sure we have read buf before we set buf_free to let
+	 * the producer overwrite it
+	 */
+	mb();
+	ldisc_data->buf_free = true;
+	/* Let TTY push more characters */
+	tty_flip_buffer_push(tty->port);
+
+	return rv;
+}
+
+static unsigned char spk_ttyio_in(struct spk_synth *in_synth)
+{
+	return ttyio_in(in_synth, SPK_SYNTH_TIMEOUT);
+}
+
+static unsigned char spk_ttyio_in_nowait(struct spk_synth *in_synth)
+{
+	u8 rv = ttyio_in(in_synth, 0);
+
+	return (rv == 0xff) ? 0 : rv;
+}
+
+static void spk_ttyio_flush_buffer(struct spk_synth *in_synth)
+{
+	struct tty_struct *tty = in_synth->dev;
+
+	if (tty->ops->flush_buffer)
+		tty->ops->flush_buffer(tty);
+}
+
+int spk_ttyio_synth_probe(struct spk_synth *synth)
+{
+	int rv = spk_ttyio_initialise_ldisc(synth);
+
+	if (rv)
+		return rv;
+
+	synth->alive = 1;
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(spk_ttyio_synth_probe);
+
+void spk_ttyio_release(struct spk_synth *in_synth)
+{
+	struct tty_struct *tty = in_synth->dev;
+
+	if (tty == NULL)
+		return;
+
+	tty_lock(tty);
+
+	if (tty->ops->close)
+		tty->ops->close(tty, NULL);
+
+	tty_ldisc_flush(tty);
+	tty_unlock(tty);
+	tty_kclose(tty);
+
+	in_synth->dev = NULL;
+}
+EXPORT_SYMBOL_GPL(spk_ttyio_release);
+
+const char *spk_ttyio_synth_immediate(struct spk_synth *in_synth, const char *buff)
+{
+	struct tty_struct *tty = in_synth->dev;
+	u_char ch;
+
+	while ((ch = *buff)) {
+		if (ch == '\n')
+			ch = in_synth->procspeech;
+		if (tty_write_room(tty) < 1 ||
+		    !in_synth->io_ops->synth_out(in_synth, ch))
+			return buff;
+		buff++;
+	}
+	return NULL;
+}
+EXPORT_SYMBOL_GPL(spk_ttyio_synth_immediate);
diff --git a/drivers/staging/speakup/spk_types.h b/drivers/accessibility/speakup/spk_types.h
index fc6a9416829c..08011518a28a 100644
--- a/drivers/staging/speakup/spk_types.h
+++ b/drivers/accessibility/speakup/spk_types.h
@@ -32,6 +32,10 @@ enum {
 	E_NEW_DEFAULT,
 };
 
+/*
+ * Note: add new members at the end, speakupmap.h depends on the values of the
+ * enum starting from SPELL_DELAY (see inc_dec_var)
+ */
 enum var_id_t {
 	VERSION = 0, SYNTH, SILENT, SYNTH_DIRECT,
 	KEYMAP, CHARS,
@@ -42,9 +46,10 @@ enum var_id_t {
 	SAY_CONTROL, SAY_WORD_CTL, NO_INTERRUPT, KEY_ECHO,
 	SPELL_DELAY, PUNC_LEVEL, READING_PUNC,
 	ATTRIB_BLEEP, BLEEPS,
-	RATE, PITCH, VOL, TONE, PUNCT, VOICE, FREQUENCY, LANG, DIRECT, PAUSE,
-	CAPS_START, CAPS_STOP, CHARTAB,
-	MAXVARS
+	RATE, PITCH, VOL, TONE, PUNCT, VOICE, FREQUENCY, LANG,
+	DIRECT, PAUSE,
+	CAPS_START, CAPS_STOP, CHARTAB, INFLECTION, FLUSH,
+	CUR_PHONETIC, MAXVARS
 };
 
 typedef int (*special_func)(struct vc_data *vc, u_char type, u_char ch,
@@ -152,11 +157,12 @@ struct spk_synth;
 struct spk_io_ops {
 	int (*synth_out)(struct spk_synth *synth, const char ch);
 	int (*synth_out_unicode)(struct spk_synth *synth, u16 ch);
-	void (*send_xchar)(char ch);
-	void (*tiocmset)(unsigned int set, unsigned int clear);
-	unsigned char (*synth_in)(void);
-	unsigned char (*synth_in_nowait)(void);
-	void (*flush_buffer)(void);
+	void (*send_xchar)(struct spk_synth *synth, char ch);
+	void (*tiocmset)(struct spk_synth *synth, unsigned int set, unsigned int clear);
+	unsigned char (*synth_in)(struct spk_synth *synth);
+	unsigned char (*synth_in_nowait)(struct spk_synth *synth);
+	void (*flush_buffer)(struct spk_synth *synth);
+	int (*wait_for_xmitr)(struct spk_synth *synth);
 };
 
 struct spk_synth {
@@ -172,6 +178,7 @@ struct spk_synth {
 	int trigger;
 	int jiffies;
 	int full;
+	int flush_time;
 	int ser;
 	char *dev_name;
 	short flags;
@@ -182,18 +189,20 @@ struct spk_synth {
 	int *default_vol;
 	struct spk_io_ops *io_ops;
 	int (*probe)(struct spk_synth *synth);
-	void (*release)(void);
+	void (*release)(struct spk_synth *synth);
 	const char *(*synth_immediate)(struct spk_synth *synth,
 				       const char *buff);
 	void (*catch_up)(struct spk_synth *synth);
 	void (*flush)(struct spk_synth *synth);
 	int (*is_alive)(struct spk_synth *synth);
-	int (*synth_adjust)(struct st_var_header *var);
+	int (*synth_adjust)(struct spk_synth *synth, struct st_var_header *var);
 	void (*read_buff_add)(u_char c);
 	unsigned char (*get_index)(struct spk_synth *synth);
 	struct synth_indexing indexing;
 	int alive;
 	struct attribute_group attributes;
+
+	void *dev;
 };
 
 /*
diff --git a/drivers/accessibility/speakup/synth.c b/drivers/accessibility/speakup/synth.c
new file mode 100644
index 000000000000..d8addbf3ad0d
--- /dev/null
+++ b/drivers/accessibility/speakup/synth.c
@@ -0,0 +1,577 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <linux/types.h>
+#include <linux/ctype.h>	/* for isdigit() and friends */
+#include <linux/fs.h>
+#include <linux/mm.h>		/* for verify_area */
+#include <linux/errno.h>	/* for -EBUSY */
+#include <linux/ioport.h>	/* for check_region, request_region */
+#include <linux/interrupt.h>
+#include <linux/delay.h>	/* for loops_per_sec */
+#include <linux/kmod.h>
+#include <linux/jiffies.h>
+#include <linux/uaccess.h>	/* for copy_from_user */
+#include <linux/sched.h>
+#include <linux/timer.h>
+#include <linux/kthread.h>
+
+#include "spk_priv.h"
+#include "speakup.h"
+#include "serialio.h"
+
+static LIST_HEAD(synths);
+struct spk_synth *synth;
+char spk_pitch_buff[32] = "";
+static int module_status;
+bool spk_quiet_boot;
+
+struct speakup_info_t speakup_info = {
+	/*
+	 * This spinlock is used to protect the entire speakup machinery, and
+	 * must be taken at each kernel->speakup transition and released at
+	 * each corresponding speakup->kernel transition.
+	 *
+	 * The progression thread only interferes with the speakup machinery
+	 * through the synth buffer, so only needs to take the lock
+	 * while tinkering with the buffer.
+	 *
+	 * We use spin_lock/trylock_irqsave and spin_unlock_irqrestore with this
+	 * spinlock because speakup needs to disable the keyboard IRQ.
+	 */
+	.spinlock = __SPIN_LOCK_UNLOCKED(speakup_info.spinlock),
+	.flushing = 0,
+};
+EXPORT_SYMBOL_GPL(speakup_info);
+
+static int do_synth_init(struct spk_synth *in_synth);
+
+/*
+ * Main loop of the progression thread: keep eating from the buffer
+ * and push to the serial port, waiting as needed
+ *
+ * For devices that have a "full" notification mechanism, the driver can
+ * adapt the loop the way they prefer.
+ */
+static void _spk_do_catch_up(struct spk_synth *synth, int unicode)
+{
+	u16 ch;
+	unsigned long flags;
+	unsigned long jiff_max;
+	struct var_t *delay_time;
+	struct var_t *full_time;
+	struct var_t *jiffy_delta;
+	int jiffy_delta_val;
+	int delay_time_val;
+	int full_time_val;
+	int ret;
+
+	jiffy_delta = spk_get_var(JIFFY);
+	full_time = spk_get_var(FULL);
+	delay_time = spk_get_var(DELAY);
+
+	spin_lock_irqsave(&speakup_info.spinlock, flags);
+	jiffy_delta_val = jiffy_delta->u.n.value;
+	spin_unlock_irqrestore(&speakup_info.spinlock, flags);
+
+	jiff_max = jiffies + jiffy_delta_val;
+	while (!kthread_should_stop()) {
+		spin_lock_irqsave(&speakup_info.spinlock, flags);
+		if (speakup_info.flushing) {
+			speakup_info.flushing = 0;
+			spin_unlock_irqrestore(&speakup_info.spinlock, flags);
+			synth->flush(synth);
+			continue;
+		}
+		if (!unicode)
+			synth_buffer_skip_nonlatin1();
+		if (synth_buffer_empty()) {
+			spin_unlock_irqrestore(&speakup_info.spinlock, flags);
+			break;
+		}
+		ch = synth_buffer_peek();
+		set_current_state(TASK_INTERRUPTIBLE);
+		full_time_val = full_time->u.n.value;
+		spin_unlock_irqrestore(&speakup_info.spinlock, flags);
+		if (ch == '\n')
+			ch = synth->procspeech;
+		if (unicode)
+			ret = synth->io_ops->synth_out_unicode(synth, ch);
+		else
+			ret = synth->io_ops->synth_out(synth, ch);
+		if (!ret) {
+			schedule_timeout(msecs_to_jiffies(full_time_val));
+			continue;
+		}
+		if (time_after_eq(jiffies, jiff_max) && (ch == SPACE)) {
+			spin_lock_irqsave(&speakup_info.spinlock, flags);
+			jiffy_delta_val = jiffy_delta->u.n.value;
+			delay_time_val = delay_time->u.n.value;
+			full_time_val = full_time->u.n.value;
+			spin_unlock_irqrestore(&speakup_info.spinlock, flags);
+			if (synth->io_ops->synth_out(synth, synth->procspeech))
+				schedule_timeout(
+					msecs_to_jiffies(delay_time_val));
+			else
+				schedule_timeout(
+					msecs_to_jiffies(full_time_val));
+			jiff_max = jiffies + jiffy_delta_val;
+		}
+		set_current_state(TASK_RUNNING);
+		spin_lock_irqsave(&speakup_info.spinlock, flags);
+		synth_buffer_getc();
+		spin_unlock_irqrestore(&speakup_info.spinlock, flags);
+	}
+	synth->io_ops->synth_out(synth, synth->procspeech);
+}
+
+void spk_do_catch_up(struct spk_synth *synth)
+{
+	_spk_do_catch_up(synth, 0);
+}
+EXPORT_SYMBOL_GPL(spk_do_catch_up);
+
+void spk_do_catch_up_unicode(struct spk_synth *synth)
+{
+	_spk_do_catch_up(synth, 1);
+}
+EXPORT_SYMBOL_GPL(spk_do_catch_up_unicode);
+
+void spk_synth_flush(struct spk_synth *synth)
+{
+	synth->io_ops->flush_buffer(synth);
+	synth->io_ops->synth_out(synth, synth->clear);
+}
+EXPORT_SYMBOL_GPL(spk_synth_flush);
+
+unsigned char spk_synth_get_index(struct spk_synth *synth)
+{
+	return synth->io_ops->synth_in_nowait(synth);
+}
+EXPORT_SYMBOL_GPL(spk_synth_get_index);
+
+int spk_synth_is_alive_nop(struct spk_synth *synth)
+{
+	synth->alive = 1;
+	return 1;
+}
+EXPORT_SYMBOL_GPL(spk_synth_is_alive_nop);
+
+int spk_synth_is_alive_restart(struct spk_synth *synth)
+{
+	if (synth->alive)
+		return 1;
+	if (synth->io_ops->wait_for_xmitr(synth) > 0) {
+		/* restart */
+		synth->alive = 1;
+		synth_printf("%s", synth->init);
+		return 2; /* reenabled */
+	}
+	pr_warn("%s: can't restart synth\n", synth->long_name);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(spk_synth_is_alive_restart);
+
+static void thread_wake_up(struct timer_list *unused)
+{
+	wake_up_interruptible_all(&speakup_event);
+}
+
+static DEFINE_TIMER(thread_timer, thread_wake_up);
+
+void synth_start(void)
+{
+	struct var_t *trigger_time;
+
+	if (!synth->alive) {
+		synth_buffer_clear();
+		return;
+	}
+	trigger_time = spk_get_var(TRIGGER);
+	if (!timer_pending(&thread_timer))
+		mod_timer(&thread_timer, jiffies +
+			msecs_to_jiffies(trigger_time->u.n.value));
+}
+
+void spk_do_flush(void)
+{
+	if (!synth)
+		return;
+
+	speakup_info.flushing = 1;
+	synth_buffer_clear();
+	if (synth->alive) {
+		if (spk_pitch_shift) {
+			synth_printf("%s", spk_pitch_buff);
+			spk_pitch_shift = 0;
+		}
+	}
+	wake_up_interruptible_all(&speakup_event);
+	wake_up_process(speakup_task);
+}
+
+void synth_write(const char *_buf, size_t count)
+{
+	const unsigned char *buf = (const unsigned char *) _buf;
+
+	while (count--)
+		synth_buffer_add(*buf++);
+	synth_start();
+}
+
+/* Consume one utf-8 character from buf (that contains up to count bytes),
+ * returns the unicode codepoint if valid, -1 otherwise.
+ * In all cases, returns the number of consumed bytes in *consumed,
+ * and the minimum number of bytes that would be needed for the next character
+ * in *want.
+ */
+s32 synth_utf8_get(const char *buf, size_t count, size_t *consumed, size_t *want)
+{
+	unsigned char c = buf[0];
+	int nbytes = 8 - fls(c ^ 0xff);
+	u32 value;
+	size_t i;
+
+	switch (nbytes) {
+	case 8: /* 0xff */
+	case 7: /* 0xfe */
+	case 1: /* 0x80 */
+		/* Invalid, drop */
+		*consumed = 1;
+		*want = 1;
+		return -1;
+
+	case 0:
+		/* ASCII, take as such */
+		*consumed = 1;
+		*want = 1;
+		return c;
+
+	default:
+		/* 2..6-byte UTF-8 */
+
+		if (count < nbytes) {
+			/* We don't have it all */
+			*consumed = 0;
+			*want = nbytes;
+			return -1;
+		}
+
+		/* First byte */
+		value = c & ((1u << (7 - nbytes)) - 1);
+
+		/* Other bytes */
+		for (i = 1; i < nbytes; i++) {
+			c = buf[i];
+			if ((c & 0xc0) != 0x80)	{
+				/* Invalid, drop the head */
+				*consumed = i;
+				*want = 1;
+				return -1;
+			}
+			value = (value << 6) | (c & 0x3f);
+		}
+
+		*consumed = nbytes;
+		*want = 1;
+		return value;
+	}
+}
+
+void synth_writeu(const char *buf, size_t count)
+{
+	size_t i, consumed, want;
+
+	/* Convert to u16 */
+	for (i = 0; i < count; i++) {
+		s32 value;
+
+		value = synth_utf8_get(buf + i, count - i, &consumed, &want);
+		if (value == -1) {
+			/* Invalid or incomplete */
+
+			if (want > count - i)
+				/* We don't have it all, stop */
+				count = i;
+
+			continue;
+		}
+
+		if (value < 0x10000)
+			synth_buffer_add(value);
+	}
+
+	synth_start();
+}
+
+void synth_printf(const char *fmt, ...)
+{
+	va_list args;
+	unsigned char buf[160];
+	int r;
+
+	va_start(args, fmt);
+	r = vsnprintf(buf, sizeof(buf), fmt, args);
+	va_end(args);
+	if (r > sizeof(buf) - 1)
+		r = sizeof(buf) - 1;
+
+	synth_writeu(buf, r);
+}
+EXPORT_SYMBOL_GPL(synth_printf);
+
+void synth_putwc(u16 wc)
+{
+	synth_buffer_add(wc);
+}
+EXPORT_SYMBOL_GPL(synth_putwc);
+
+void synth_putwc_s(u16 wc)
+{
+	synth_buffer_add(wc);
+	synth_start();
+}
+EXPORT_SYMBOL_GPL(synth_putwc_s);
+
+void synth_putws(const u16 *buf)
+{
+	const u16 *p;
+
+	for (p = buf; *p; p++)
+		synth_buffer_add(*p);
+}
+EXPORT_SYMBOL_GPL(synth_putws);
+
+void synth_putws_s(const u16 *buf)
+{
+	synth_putws(buf);
+	synth_start();
+}
+EXPORT_SYMBOL_GPL(synth_putws_s);
+
+static int index_count;
+static int sentence_count;
+
+void spk_reset_index_count(int sc)
+{
+	static int first = 1;
+
+	if (first)
+		first = 0;
+	else
+		synth->get_index(synth);
+	index_count = 0;
+	sentence_count = sc;
+}
+
+int synth_supports_indexing(void)
+{
+	if (synth->get_index)
+		return 1;
+	return 0;
+}
+
+void synth_insert_next_index(int sent_num)
+{
+	int out;
+
+	if (synth->alive) {
+		if (sent_num == 0) {
+			synth->indexing.currindex++;
+			index_count++;
+			if (synth->indexing.currindex >
+					synth->indexing.highindex)
+				synth->indexing.currindex =
+					synth->indexing.lowindex;
+		}
+
+		out = synth->indexing.currindex * 10 + sent_num;
+		synth_printf(synth->indexing.command, out, out);
+	}
+}
+
+void spk_get_index_count(int *linecount, int *sentcount)
+{
+	int ind = synth->get_index(synth);
+
+	if (ind) {
+		sentence_count = ind % 10;
+
+		if ((ind / 10) <= synth->indexing.currindex)
+			index_count = synth->indexing.currindex - (ind / 10);
+		else
+			index_count = synth->indexing.currindex
+				- synth->indexing.lowindex
+				+ synth->indexing.highindex - (ind / 10) + 1;
+	}
+	*sentcount = sentence_count;
+	*linecount = index_count;
+}
+
+static struct resource synth_res;
+
+int synth_request_region(unsigned long start, unsigned long n)
+{
+	struct resource *parent = &ioport_resource;
+
+	memset(&synth_res, 0, sizeof(synth_res));
+	synth_res.name = synth->name;
+	synth_res.start = start;
+	synth_res.end = start + n - 1;
+	synth_res.flags = IORESOURCE_BUSY;
+	return request_resource(parent, &synth_res);
+}
+EXPORT_SYMBOL_GPL(synth_request_region);
+
+int synth_release_region(unsigned long start, unsigned long n)
+{
+	return release_resource(&synth_res);
+}
+EXPORT_SYMBOL_GPL(synth_release_region);
+
+struct var_t synth_time_vars[] = {
+	{ DELAY, .u.n = {NULL, 100, 100, 2000, 0, 0, NULL } },
+	{ TRIGGER, .u.n = {NULL, 20, 10, 2000, 0, 0, NULL } },
+	{ JIFFY, .u.n = {NULL, 50, 20, 200, 0, 0, NULL } },
+	{ FULL, .u.n = {NULL, 400, 200, 60000, 0, 0, NULL } },
+	{ FLUSH, .u.n = {NULL, 4000, 10, 4000, 0, 0, NULL } },
+	V_LAST_VAR
+};
+
+/* called by: speakup_init() */
+int synth_init(char *synth_name)
+{
+	int ret = 0;
+	struct spk_synth *tmp, *synth = NULL;
+
+	if (!synth_name)
+		return 0;
+
+	if (strcmp(synth_name, "none") == 0) {
+		mutex_lock(&spk_mutex);
+		synth_release();
+		mutex_unlock(&spk_mutex);
+		return 0;
+	}
+
+	mutex_lock(&spk_mutex);
+	/* First, check if we already have it loaded. */
+	list_for_each_entry(tmp, &synths, node) {
+		if (strcmp(tmp->name, synth_name) == 0)
+			synth = tmp;
+	}
+
+	/* If we got one, initialize it now. */
+	if (synth)
+		ret = do_synth_init(synth);
+	else
+		ret = -ENODEV;
+	mutex_unlock(&spk_mutex);
+
+	return ret;
+}
+
+/* called by: synth_add() */
+static int do_synth_init(struct spk_synth *in_synth)
+{
+	struct var_t *var;
+
+	synth_release();
+	if (in_synth->checkval != SYNTH_CHECK)
+		return -EINVAL;
+	synth = in_synth;
+	synth->alive = 0;
+	pr_warn("synth probe\n");
+	if (synth->probe(synth) < 0) {
+		pr_warn("%s: device probe failed\n", in_synth->name);
+		synth = NULL;
+		return -ENODEV;
+	}
+	synth_time_vars[0].u.n.value =
+		synth_time_vars[0].u.n.default_val = synth->delay;
+	synth_time_vars[1].u.n.value =
+		synth_time_vars[1].u.n.default_val = synth->trigger;
+	synth_time_vars[2].u.n.value =
+		synth_time_vars[2].u.n.default_val = synth->jiffies;
+	synth_time_vars[3].u.n.value =
+		synth_time_vars[3].u.n.default_val = synth->full;
+	synth_time_vars[4].u.n.value =
+		synth_time_vars[4].u.n.default_val = synth->flush_time;
+	synth_printf("%s", synth->init);
+	for (var = synth->vars;
+		(var->var_id >= 0) && (var->var_id < MAXVARS); var++)
+		speakup_register_var(var);
+	if (!spk_quiet_boot)
+		synth_printf("%s found\n", synth->long_name);
+	if (synth->attributes.name &&
+	    sysfs_create_group(speakup_kobj, &synth->attributes) < 0)
+		return -ENOMEM;
+	synth_flags = synth->flags;
+	wake_up_interruptible_all(&speakup_event);
+	if (speakup_task)
+		wake_up_process(speakup_task);
+	return 0;
+}
+
+void synth_release(void)
+{
+	struct var_t *var;
+	unsigned long flags;
+
+	if (!synth)
+		return;
+	spin_lock_irqsave(&speakup_info.spinlock, flags);
+	pr_info("releasing synth %s\n", synth->name);
+	synth->alive = 0;
+	timer_delete(&thread_timer);
+	spin_unlock_irqrestore(&speakup_info.spinlock, flags);
+	if (synth->attributes.name)
+		sysfs_remove_group(speakup_kobj, &synth->attributes);
+	for (var = synth->vars; var->var_id != MAXVARS; var++)
+		speakup_unregister_var(var->var_id);
+	synth->release(synth);
+	synth = NULL;
+}
+
+/* called by: all_driver_init() */
+int synth_add(struct spk_synth *in_synth)
+{
+	int status = 0;
+	struct spk_synth *tmp;
+
+	mutex_lock(&spk_mutex);
+
+	list_for_each_entry(tmp, &synths, node) {
+		if (tmp == in_synth) {
+			mutex_unlock(&spk_mutex);
+			return 0;
+		}
+	}
+
+	if (in_synth->startup)
+		status = do_synth_init(in_synth);
+
+	if (!status)
+		list_add_tail(&in_synth->node, &synths);
+
+	mutex_unlock(&spk_mutex);
+	return status;
+}
+EXPORT_SYMBOL_GPL(synth_add);
+
+void synth_remove(struct spk_synth *in_synth)
+{
+	mutex_lock(&spk_mutex);
+	if (synth == in_synth)
+		synth_release();
+	list_del(&in_synth->node);
+	module_status = 0;
+	mutex_unlock(&spk_mutex);
+}
+EXPORT_SYMBOL_GPL(synth_remove);
+
+struct spk_synth *synth_current(void)
+{
+	return synth;
+}
+EXPORT_SYMBOL_GPL(synth_current);
+
+short spk_punc_masks[] = { 0, SOME, MOST, PUNC, PUNC | B_SYM };
diff --git a/drivers/staging/speakup/thread.c b/drivers/accessibility/speakup/thread.c
index 2fc75e60fbac..2fc75e60fbac 100644
--- a/drivers/staging/speakup/thread.c
+++ b/drivers/accessibility/speakup/thread.c
diff --git a/drivers/accessibility/speakup/utils.h b/drivers/accessibility/speakup/utils.h
new file mode 100644
index 000000000000..4ce9a12f7664
--- /dev/null
+++ b/drivers/accessibility/speakup/utils.h
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/* utils.h
+ * originally written by: Kirk Reiser.
+ *
+ ** Copyright (C) 2002  Kirk Reiser.
+ *  Copyright (C) 2003  David Borowski.
+ */
+
+#include <stdio.h>
+
+#define MAXKEYS 512
+#define MAXKEYVAL 160
+#define HASHSIZE 101
+#define is_shift -3
+#define is_spk -2
+#define is_input -1
+
+struct st_key {
+	char *name;
+	struct st_key *next;
+	int value, shift;
+};
+
+struct st_key key_table[MAXKEYS];
+struct st_key *extra_keys = key_table+HASHSIZE;
+char *def_name, *def_val;
+FILE *infile;
+int lc;
+
+char filename[256];
+
+static inline void open_input(const char *dir_name, const char *name)
+{
+	if (dir_name)
+		snprintf(filename, sizeof(filename), "%s/%s", dir_name, name);
+	else
+		snprintf(filename, sizeof(filename), "%s", name);
+	infile = fopen(filename, "r");
+	if (infile == 0) {
+		fprintf(stderr, "can't open %s\n", filename);
+		exit(1);
+	}
+	lc = 0;
+}
+
+static inline int oops(const char *msg, const char *info)
+{
+	if (info == NULL)
+		info = "";
+	fprintf(stderr, "error: file %s line %d\n", filename, lc);
+	fprintf(stderr, "%s %s\n", msg, info);
+	exit(1);
+}
+
+static inline struct st_key *hash_name(char *name)
+{
+	unsigned char *pn = (unsigned char *)name;
+	int hash = 0;
+
+	while (*pn) {
+		hash = (hash * 17) & 0xfffffff;
+		if (isupper(*pn))
+			*pn = tolower(*pn);
+		hash += (int)*pn;
+		pn++;
+	}
+	hash %= HASHSIZE;
+	return &key_table[hash];
+}
+
+static inline struct st_key *find_key(char *name)
+{
+	struct st_key *this = hash_name(name);
+
+	while (this) {
+		if (this->name && !strcmp(name, this->name))
+			return this;
+		this = this->next;
+	}
+	return this;
+}
+
+static inline struct st_key *add_key(char *name, int value, int shift)
+{
+	struct st_key *this = hash_name(name);
+
+	if (extra_keys-key_table >= MAXKEYS)
+		oops("out of key table space, enlarge MAXKEYS", NULL);
+	if (this->name != NULL) {
+		while (this->next) {
+			if (!strcmp(name, this->name))
+				oops("attempt to add duplicate key", name);
+			this = this->next;
+		}
+		this->next = extra_keys++;
+		this = this->next;
+	}
+	this->name = strdup(name);
+	this->value = value;
+	this->shift = shift;
+	return this;
+}
diff --git a/drivers/staging/speakup/varhandlers.c b/drivers/accessibility/speakup/varhandlers.c
index 5741d1cb6227..462f8d879053 100644
--- a/drivers/staging/speakup/varhandlers.c
+++ b/drivers/accessibility/speakup/varhandlers.c
@@ -23,6 +23,7 @@ static struct st_var_header var_headers[] = {
 	{ "trigger_time", TRIGGER, VAR_TIME, NULL, NULL },
 	{ "jiffy_delta", JIFFY, VAR_TIME, NULL, NULL },
 	{ "full_time", FULL, VAR_TIME, NULL, NULL },
+	{ "flush_time", FLUSH, VAR_TIME, NULL, NULL },
 	{ "spell_delay", SPELL_DELAY, VAR_NUM, &spk_spell_delay, NULL },
 	{ "bleeps", BLEEPS, VAR_NUM, &spk_bleeps, NULL },
 	{ "attrib_bleep", ATTRIB_BLEEP, VAR_NUM, &spk_attrib_bleep, NULL },
@@ -37,6 +38,7 @@ static struct st_var_header var_headers[] = {
 	{ "bell_pos", BELL_POS, VAR_NUM, &spk_bell_pos, NULL },
 	{ "rate", RATE, VAR_NUM, NULL, NULL },
 	{ "pitch", PITCH, VAR_NUM, NULL, NULL },
+	{ "inflection", INFLECTION, VAR_NUM, NULL, NULL },
 	{ "vol", VOL, VAR_NUM, NULL, NULL },
 	{ "tone", TONE, VAR_NUM, NULL, NULL },
 	{ "punct", PUNCT, VAR_NUM, NULL, NULL   },
@@ -46,6 +48,7 @@ static struct st_var_header var_headers[] = {
 	{ "chartab", CHARTAB, VAR_PROC, NULL, NULL },
 	{ "direct", DIRECT, VAR_NUM, NULL, NULL },
 	{ "pause", PAUSE, VAR_STRING, spk_str_pause, NULL },
+	{ "cur_phonetic", CUR_PHONETIC, VAR_NUM, &spk_cur_phonetic, NULL },
 };
 
 static struct st_var_header *var_ptrs[MAXVARS] = { NULL, NULL, NULL };
@@ -136,6 +139,7 @@ struct st_var_header *spk_get_var_header(enum var_id_t var_id)
 		return NULL;
 	return p_header;
 }
+EXPORT_SYMBOL_GPL(spk_get_var_header);
 
 struct st_var_header *spk_var_header_by_name(const char *name)
 {
@@ -219,15 +223,17 @@ int spk_set_num_var(int input, struct st_var_header *var, int how)
 		*p_val = val;
 	if (var->var_id == PUNC_LEVEL) {
 		spk_punc_mask = spk_punc_masks[val];
-		return 0;
 	}
 	if (var_data->u.n.multiplier != 0)
 		val *= var_data->u.n.multiplier;
 	val += var_data->u.n.offset;
-	if (var->var_id < FIRST_SYNTH_VAR || !synth)
+
+	if (!synth)
+		return 0;
+	if (synth->synth_adjust && synth->synth_adjust(synth, var))
+		return 0;
+	if (var->var_id < FIRST_SYNTH_VAR)
 		return 0;
-	if (synth->synth_adjust)
-		return synth->synth_adjust(var);
 
 	if (!var_data->u.n.synth_fmt)
 		return 0;
@@ -243,6 +249,7 @@ int spk_set_num_var(int input, struct st_var_header *var, int how)
 	synth_printf("%s", cp);
 	return 0;
 }
+EXPORT_SYMBOL_GPL(spk_set_num_var);
 
 int spk_set_string_var(const char *page, struct st_var_header *var, int len)
 {
diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig
index ce2730d61a8f..ca00a5dbcf75 100644
--- a/drivers/acpi/Kconfig
+++ b/drivers/acpi/Kconfig
@@ -11,6 +11,8 @@ menuconfig ACPI
 	depends on ARCH_SUPPORTS_ACPI
 	select PNP
 	select NLS
+	select CRC32
+	select FIRMWARE_TABLE
 	default y if X86
 	help
 	  Advanced Configuration and Power Interface (ACPI) support for 
@@ -26,13 +28,10 @@ menuconfig ACPI
 	  Management (APM) specification.  If both ACPI and APM support 
 	  are configured, ACPI is used.
 
-	  The project home page for the Linux ACPI subsystem is here:
-	  <https://01.org/linux-acpi>
-
 	  Linux support for ACPI is based on Intel Corporation's ACPI
 	  Component Architecture (ACPI CA).  For more information on the
 	  ACPI CA, see:
-	  <http://acpica.org/>
+	  <https://acpica.org/>
 
 	  ACPI is an open industry specification originally co-developed by
 	  Hewlett-Packard, Intel, Microsoft, Phoenix, and Toshiba. Currently,
@@ -40,8 +39,7 @@ menuconfig ACPI
 	  the UEFI Forum and any UEFI member can join the ASWG and contribute
 	  to the ACPI specification.
 	  The specification is available at:
-	  <http://www.acpi.info>
-	  <http://www.uefi.org/acpi/specs>
+	  <https://uefi.org/specifications>
 
 if ACPI
 
@@ -60,6 +58,13 @@ config ACPI_SYSTEM_POWER_STATES_SUPPORT
 config ACPI_CCA_REQUIRED
 	bool
 
+config ACPI_TABLE_LIB
+	bool
+
+config ACPI_THERMAL_LIB
+       depends on THERMAL
+       bool
+
 config ACPI_DEBUGGER
 	bool "AML debugger interface"
 	select ACPI_DEBUG
@@ -72,7 +77,7 @@ config ACPI_DEBUGGER
 if ACPI_DEBUGGER
 
 config ACPI_DEBUGGER_USER
-	tristate "Userspace debugger accessiblity"
+	tristate "Userspace debugger accessibility"
 	depends on DEBUG_FS
 	help
 	  Export /sys/kernel/debug/acpi/acpidbg for userspace utilities
@@ -88,6 +93,14 @@ config ACPI_SPCR_TABLE
 	  This table provides information about the configuration of the
 	  earlycon console.
 
+config ACPI_FPDT
+	bool "ACPI Firmware Performance Data Table (FPDT) support"
+	depends on X86_64 || ARM64
+	help
+	  Enable support for the Firmware Performance Data Table (FPDT).
+	  This table provides information on the timing of the system
+	  boot, S3 suspend and S3 resume firmware code paths.
+
 config ACPI_LPIT
 	bool
 	depends on X86_64
@@ -99,23 +112,6 @@ config ACPI_SLEEP
 	depends on ACPI_SYSTEM_POWER_STATES_SUPPORT
 	default y
 
-config ACPI_PROCFS_POWER
-	bool "Deprecated power /proc/acpi directories"
-	depends on X86 && PROC_FS
-	help
-	  For backwards compatibility, this option allows
-	  deprecated power /proc/acpi/ directories to exist, even when
-	  they have been replaced by functions in /sys.
-	  The deprecated directories (and their replacements) include:
-	  /proc/acpi/battery/* (/sys/class/power_supply/*) and
-	  /proc/acpi/ac_adapter/* (sys/class/power_supply/*).
-	  This option has no effect on /proc/acpi/ directories
-	  and functions which do not yet exist in /sys.
-	  This option, together with the proc directories, will be
-	  deleted in the future.
-
-	  Say N to delete power /proc/acpi/ directories that have moved to /sys.
-
 config ACPI_REV_OVERRIDE_POSSIBLE
 	bool "Allow supported ACPI revision to be overridden"
 	depends on X86
@@ -136,8 +132,17 @@ config ACPI_REV_OVERRIDE_POSSIBLE
 	  makes it possible to force the kernel to return "5" as the supported
 	  ACPI revision via the "acpi_rev_override" command line switch.
 
+config ACPI_EC
+	bool "Embedded Controller"
+	depends on HAS_IOPORT
+	default X86 || LOONGARCH
+	help
+	  This driver handles communication with the microcontroller
+	  on many x86/LoongArch laptops and other machines.
+
 config ACPI_EC_DEBUGFS
 	tristate "EC read/write access through /sys/kernel/debug/ec"
+	depends on ACPI_EC
 	help
 	  Say N to disable Embedded Controller /sys/kernel/debug interface
 
@@ -216,8 +221,9 @@ config ACPI_TINY_POWER_BUTTON_SIGNAL
 
 config ACPI_VIDEO
 	tristate "Video"
-	depends on X86 && BACKLIGHT_CLASS_DEVICE
+	depends on BACKLIGHT_CLASS_DEVICE
 	depends on INPUT
+	depends on ACPI_WMI || !X86
 	select THERMAL
 	help
 	  This driver implements the ACPI Extensions For Display Adapters
@@ -261,12 +267,11 @@ config ACPI_DOCK
 
 config ACPI_CPU_FREQ_PSS
 	bool
-	select THERMAL
 
 config ACPI_PROCESSOR_CSTATE
 	def_bool y
 	depends on ACPI_PROCESSOR
-	depends on IA64 || X86
+	depends on X86
 
 config ACPI_PROCESSOR_IDLE
 	bool
@@ -290,9 +295,10 @@ config ACPI_CPPC_LIB
 
 config ACPI_PROCESSOR
 	tristate "Processor"
-	depends on X86 || IA64 || ARM64
+	depends on X86 || ARM64 || LOONGARCH || RISCV
 	select ACPI_PROCESSOR_IDLE
-	select ACPI_CPU_FREQ_PSS if X86 || IA64
+	select ACPI_CPU_FREQ_PSS if X86 || LOONGARCH
+	select THERMAL
 	default y
 	help
 	  This driver adds support for the ACPI Processor package. It is required
@@ -308,7 +314,7 @@ config ACPI_IPMI
 	help
 	  This driver enables the ACPI to access the BMC controller. And it
 	  uses the IPMI request/response message to communicate with BMC
-	  controller, which can be found on on the server.
+	  controller, which can be found on the server.
 
 	  To compile this driver as a module, choose M here:
 	  the module will be called as acpi_ipmi.
@@ -317,7 +323,6 @@ config ACPI_HOTPLUG_CPU
 	bool
 	depends on ACPI_PROCESSOR && HOTPLUG_CPU
 	select ACPI_CONTAINER
-	default y
 
 config ACPI_PROCESSOR_AGGREGATOR
 	tristate "Processor Aggregator"
@@ -334,6 +339,7 @@ config ACPI_THERMAL
 	tristate "Thermal Zone"
 	depends on ACPI_PROCESSOR
 	select THERMAL
+	select ACPI_THERMAL_LIB
 	default y
 	help
 	  This driver supports ACPI thermal zones.  Most mobile and
@@ -344,13 +350,15 @@ config ACPI_THERMAL
 	  To compile this driver as a module, choose M here:
 	  the module will be called thermal.
 
+config ACPI_PLATFORM_PROFILE
+	tristate
+
 config ACPI_CUSTOM_DSDT_FILE
 	string "Custom DSDT Table file to include"
 	default ""
 	depends on !STANDALONE
 	help
 	  This option supports a custom DSDT by linking it into the kernel.
-	  See Documentation/admin-guide/acpi/dsdt-override.rst
 
 	  Enter the full path name to the file which includes the AmlCode
 	  or dsdt_aml_code declaration.
@@ -377,7 +385,7 @@ config ACPI_TABLE_UPGRADE
 config ACPI_TABLE_OVERRIDE_VIA_BUILTIN_INITRD
 	bool "Override ACPI tables from built-in initrd"
 	depends on ACPI_TABLE_UPGRADE
-	depends on INITRAMFS_SOURCE!="" && INITRAMFS_COMPRESSION=""
+	depends on INITRAMFS_SOURCE!="" && INITRAMFS_COMPRESSION_NONE
 	help
 	  This option provides functionality to override arbitrary ACPI tables
 	  from built-in uncompressed initrd.
@@ -386,6 +394,7 @@ config ACPI_TABLE_OVERRIDE_VIA_BUILTIN_INITRD
 
 config ACPI_DEBUG
 	bool "Debug Statements"
+	default y
 	help
 	  The ACPI subsystem can produce debug output.  Saying Y enables this
 	  output and increases the kernel size by around 50K.
@@ -413,9 +422,6 @@ config ACPI_CONTAINER
 
 	  This helps support hotplug of nodes, CPUs, and memory.
 
-	  To compile this driver as a module, choose M here:
-	  the module will be called container.
-
 config ACPI_HOTPLUG_MEMORY
 	bool "Memory Hotplug"
 	depends on MEMORY_HOTPLUG
@@ -429,9 +435,6 @@ config ACPI_HOTPLUG_MEMORY
 	  removing memory devices at runtime, you need not enable
 	  this driver.
 
-	  To compile this driver as a module, choose M here:
-	  the module will be called acpi_memhotplug.
-
 config ACPI_HOTPLUG_IOAPIC
 	bool
 	depends on PCI
@@ -440,7 +443,7 @@ config ACPI_HOTPLUG_IOAPIC
 
 config ACPI_SBS
 	tristate "Smart Battery System"
-	depends on X86
+	depends on X86 && ACPI_EC
 	select POWER_SUPPLY
 	help
 	  This driver supports the Smart Battery System, another
@@ -450,29 +453,15 @@ config ACPI_SBS
 	  the modules will be called sbs and sbshc.
 
 config ACPI_HED
-	tristate "Hardware Error Device"
+	bool "Hardware Error Device"
 	help
 	  This driver supports the Hardware Error Device (PNP0C33),
 	  which is used to report some hardware errors notified via
 	  SCI, mainly the corrected errors.
 
-config ACPI_CUSTOM_METHOD
-	tristate "Allow ACPI methods to be inserted/replaced at run time"
-	depends on DEBUG_FS
-	help
-	  This debug facility allows ACPI AML methods to be inserted and/or
-	  replaced without rebooting the system. For details refer to:
-	  Documentation/firmware-guide/acpi/method-customizing.rst.
-
-	  NOTE: This option is security sensitive, because it allows arbitrary
-	  kernel memory to be written to by root (uid=0) users, allowing them
-	  to bypass certain security measures (e.g. if root is not allowed to
-	  load additional kernel modules after boot, this feature may be used
-	  to override that restriction).
-
 config ACPI_BGRT
 	bool "Boottime Graphics Resource Table support"
-	depends on EFI && (X86 || ARM64)
+	depends on EFI
 	help
 	  This driver adds support for exposing the ACPI Boottime Graphics
 	  Resource Table, which allows the operating system to obtain
@@ -481,7 +470,6 @@ config ACPI_BGRT
 
 config ACPI_REDUCED_HARDWARE_ONLY
 	bool "Hardware-reduced ACPI support only" if EXPERT
-	def_bool n
 	help
 	  This config item changes the way the ACPI code is built.  When this
 	  option is selected, the kernel will use a specialized version of
@@ -491,6 +479,9 @@ config ACPI_REDUCED_HARDWARE_ONLY
 
 	  If you are unsure what to do, do not enable this option.
 
+config ACPI_NHLT
+	bool
+
 source "drivers/acpi/nfit/Kconfig"
 source "drivers/acpi/numa/Kconfig"
 source "drivers/acpi/apei/Kconfig"
@@ -522,85 +513,96 @@ config ACPI_EXTLOG
 config ACPI_ADXL
 	bool
 
-menuconfig PMIC_OPREGION
-	bool "PMIC (Power Management Integrated Circuit) operation region support"
+config ACPI_CONFIGFS
+	tristate "ACPI configfs support"
+	select CONFIGFS_FS
 	help
-	  Select this option to enable support for ACPI operation
-	  region of the PMIC chip. The operation region can be used
-	  to control power rails and sensor reading/writing on the
-	  PMIC chip.
+	  Select this option to enable support for ACPI configuration from
+	  userspace. The configurable ACPI groups will be visible under
+	  /config/acpi, assuming configfs is mounted under /config.
 
-if PMIC_OPREGION
-config BYTCRC_PMIC_OPREGION
-	bool "ACPI operation region support for Bay Trail Crystal Cove PMIC"
-	depends on INTEL_SOC_PMIC
+config ACPI_PFRUT
+	tristate "ACPI Platform Firmware Runtime Update and Telemetry"
+	depends on 64BIT
 	help
-	  This config adds ACPI operation region support for the Bay Trail
-	  version of the Crystal Cove PMIC.
+	  This mechanism allows certain pieces of the platform firmware
+	  to be updated on the fly while the system is running (runtime)
+	  without the need to restart it, which is key in the cases when
+	  the system needs to be available 100% of the time and it cannot
+	  afford the downtime related to restarting it, or when the work
+	  carried out by the system is particularly important, so it cannot
+	  be interrupted, and it is not practical to wait until it is complete.
 
-config CHTCRC_PMIC_OPREGION
-	bool "ACPI operation region support for Cherry Trail Crystal Cove PMIC"
-	depends on INTEL_SOC_PMIC
-	help
-	  This config adds ACPI operation region support for the Cherry Trail
-	  version of the Crystal Cove PMIC.
+	  The existing firmware code can be modified (driver update) or
+	  extended by adding new code to the firmware (code injection).
 
-config XPOWER_PMIC_OPREGION
-	bool "ACPI operation region support for XPower AXP288 PMIC"
-	depends on MFD_AXP20X_I2C && IOSF_MBI=y
-	help
-	  This config adds ACPI operation region support for XPower AXP288 PMIC.
+	  Besides, the telemetry driver allows user space to fetch telemetry
+	  data from the firmware with the help of the Platform Firmware Runtime
+	  Telemetry interface.
 
-config BXT_WC_PMIC_OPREGION
-	bool "ACPI operation region support for BXT WhiskeyCove PMIC"
-	depends on INTEL_SOC_PMIC_BXTWC
-	help
-	  This config adds ACPI operation region support for BXT WhiskeyCove PMIC.
+	  To compile the drivers as modules, choose M here:
+	  the modules will be called pfr_update and pfr_telemetry.
 
-config CHT_WC_PMIC_OPREGION
-	bool "ACPI operation region support for CHT Whiskey Cove PMIC"
-	depends on INTEL_SOC_PMIC_CHTWC
-	help
-	  This config adds ACPI operation region support for CHT Whiskey Cove PMIC.
+if ARM64
+source "drivers/acpi/arm64/Kconfig"
+endif
 
-config CHT_DC_TI_PMIC_OPREGION
-	bool "ACPI operation region support for Dollar Cove TI PMIC"
-	depends on INTEL_SOC_PMIC_CHTDC_TI
+if RISCV
+source "drivers/acpi/riscv/Kconfig"
+endif
+
+config ACPI_PPTT
+	bool
+
+config ACPI_PCC
+	bool "ACPI PCC Address Space"
+	depends on PCC
+	default y
 	help
-	  This config adds ACPI operation region support for Dollar Cove TI PMIC.
+	  The PCC Address Space also referred as PCC Operation Region pertains
+	  to the region of PCC subspace that succeeds the PCC signature.
 
-endif
+	  The PCC Operation Region works in conjunction with the PCC Table
+	  (Platform Communications Channel Table). PCC subspaces that are
+	  marked for use as PCC Operation Regions must not be used as PCC
+	  subspaces for the standard ACPI features such as CPPC, RASF, PDTT and
+	  MPST. These standard features must always use the PCC Table instead.
 
-config ACPI_CONFIGFS
-	tristate "ACPI configfs support"
-	select CONFIGFS_FS
+	  Enable this feature if you want to set up and install the PCC Address
+	  Space handler to handle PCC OpRegion in the firmware.
+
+config ACPI_FFH
+	bool "ACPI FFH Address Space"
+	default n
 	help
-	  Select this option to enable support for ACPI configuration from
-	  userspace. The configurable ACPI groups will be visible under
-	  /config/acpi, assuming configfs is mounted under /config.
+	  The FFH(Fixed Function Hardware) Address Space also referred as FFH
+	  Operation Region allows to define platform specific opregion.
 
-if ARM64
-source "drivers/acpi/arm64/Kconfig"
+	  Enable this feature if you want to set up and install the FFH Address
+	  Space handler to handle FFH OpRegion in the firmware.
 
-config ACPI_PPTT
+config ACPI_MRRM
 	bool
-endif
 
-config TPS68470_PMIC_OPREGION
-	bool "ACPI operation region support for TPS68470 PMIC"
-	depends on MFD_TPS68470
-	help
-	  This config adds ACPI operation region support for TI TPS68470 PMIC.
-	  TPS68470 device is an advanced power management unit that powers
-	  a Compact Camera Module (CCM), generates clocks for image sensors,
-	  drives a dual LED for flash and incorporates two LED drivers for
-	  general purpose indicators.
-	  This driver enables ACPI operation region support control voltage
-	  regulators and clocks.
-
-	  This option is a bool as it provides an ACPI operation
-	  region, which must be available before any of the devices
-	  using this, are probed.
+source "drivers/acpi/pmic/Kconfig"
+
+config ACPI_VIOT
+	bool
+
+config ACPI_PRMT
+	bool "Platform Runtime Mechanism Support"
+	depends on EFI_RUNTIME_WRAPPERS && (X86_64 || ARM64)
+	default y
+	help
+	  Platform Runtime Mechanism (PRM) is a firmware interface exposing a
+	  set of binary executables that can be called from the AML interpreter
+	  or directly from device drivers.
+
+	  Say Y to enable the AML interpreter to execute the PRM code.
+
+	  While this feature is optional in principle, leaving it out may
+	  substantially increase computational overhead related to the
+	  initialization of some server systems.
 
 endif	# ACPI
 
diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile
index e81e1ebbfb32..d1b0affb844f 100644
--- a/drivers/acpi/Makefile
+++ b/drivers/acpi/Makefile
@@ -5,11 +5,19 @@
 
 ccflags-$(CONFIG_ACPI_DEBUG)	+= -DACPI_DEBUG_OUTPUT
 
+ifdef CONFIG_TRACE_BRANCH_PROFILING
+CFLAGS_processor_idle.o += -DDISABLE_BRANCH_PROFILING
+endif
+
 #
 # ACPI Boot-Time Table Parsing
 #
+ifeq ($(CONFIG_ACPI_CUSTOM_DSDT),y)
+tables.o: $(src)/../../include/$(CONFIG_ACPI_CUSTOM_DSDT_FILE) ;
+
+endif
+
 obj-$(CONFIG_ACPI)		+= tables.o
-obj-$(CONFIG_X86)		+= blacklist.o
 
 #
 # ACPI Core Subsystem (Interpreter)
@@ -32,34 +40,33 @@ acpi-$(CONFIG_ACPI_SLEEP)	+= proc.o
 # ACPI Bus and Device Drivers
 #
 acpi-y				+= bus.o glue.o
-acpi-y				+= scan.o
+acpi-y				+= scan.o mipi-disco-img.o
 acpi-y				+= resource.o
 acpi-y				+= acpi_processor.o
 acpi-y				+= processor_core.o
 acpi-$(CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC) += processor_pdc.o
-acpi-y				+= ec.o
+acpi-$(CONFIG_ACPI_EC)		+= ec.o
 acpi-$(CONFIG_ACPI_DOCK)	+= dock.o
 acpi-$(CONFIG_PCI)		+= pci_root.o pci_link.o pci_irq.o
 obj-$(CONFIG_ACPI_MCFG)		+= pci_mcfg.o
-acpi-$(CONFIG_PCI)		+= acpi_lpss.o
 acpi-y				+= acpi_apd.o
 acpi-y				+= acpi_platform.o
 acpi-y				+= acpi_pnp.o
-acpi-$(CONFIG_ARM_AMBA)	+= acpi_amba.o
 acpi-y				+= power.o
 acpi-y				+= event.o
 acpi-y				+= evged.o
 acpi-y				+= sysfs.o
 acpi-y				+= property.o
-acpi-$(CONFIG_X86)		+= acpi_cmos_rtc.o
-acpi-$(CONFIG_X86)		+= x86/apple.o
-acpi-$(CONFIG_X86)		+= x86/utils.o
 acpi-$(CONFIG_DEBUG_FS)		+= debugfs.o
-acpi-$(CONFIG_ACPI_PROCFS_POWER) += cm_sbs.o
 acpi-y				+= acpi_lpat.o
+acpi-$(CONFIG_ACPI_FPDT)	+= acpi_fpdt.o
 acpi-$(CONFIG_ACPI_LPIT)	+= acpi_lpit.o
 acpi-$(CONFIG_ACPI_GENERIC_GSI) += irq.o
 acpi-$(CONFIG_ACPI_WATCHDOG)	+= acpi_watchdog.o
+acpi-$(CONFIG_ACPI_PRMT)	+= prmt.o
+acpi-$(CONFIG_ACPI_PCC)		+= acpi_pcc.o
+acpi-$(CONFIG_ACPI_FFH)		+= acpi_ffh.o
+acpi-$(CONFIG_ACPI_MRRM)	+= acpi_mrrm.o
 
 # Address translation
 acpi-$(CONFIG_ACPI_ADXL)	+= acpi_adxl.o
@@ -73,13 +80,20 @@ obj-$(CONFIG_ACPI_AC) 		+= ac.o
 obj-$(CONFIG_ACPI_BUTTON)	+= button.o
 obj-$(CONFIG_ACPI_TINY_POWER_BUTTON)	+= tiny-power-button.o
 obj-$(CONFIG_ACPI_FAN)		+= fan.o
+fan-objs			:= fan_core.o
+fan-objs			+= fan_attr.o
+fan-$(CONFIG_HWMON)		+= fan_hwmon.o
+
 obj-$(CONFIG_ACPI_VIDEO)	+= video.o
 obj-$(CONFIG_ACPI_TAD)		+= acpi_tad.o
 obj-$(CONFIG_ACPI_PCI_SLOT)	+= pci_slot.o
 obj-$(CONFIG_ACPI_PROCESSOR)	+= processor.o
 obj-$(CONFIG_ACPI)		+= container.o
+obj-$(CONFIG_ACPI_THERMAL_LIB)	+= thermal_lib.o
 obj-$(CONFIG_ACPI_THERMAL)	+= thermal.o
+obj-$(CONFIG_ACPI_PLATFORM_PROFILE) 	+= platform_profile.o
 obj-$(CONFIG_ACPI_NFIT)		+= nfit/
+obj-$(CONFIG_ACPI_NHLT)		+= nhlt.o
 obj-$(CONFIG_ACPI_NUMA)		+= numa/
 obj-$(CONFIG_ACPI)		+= acpi_memhotplug.o
 obj-$(CONFIG_ACPI_HOTPLUG_IOAPIC) += ioapic.o
@@ -88,18 +102,17 @@ obj-$(CONFIG_ACPI_SBS)		+= sbshc.o
 obj-$(CONFIG_ACPI_SBS)		+= sbs.o
 obj-$(CONFIG_ACPI_HED)		+= hed.o
 obj-$(CONFIG_ACPI_EC_DEBUGFS)	+= ec_sys.o
-obj-$(CONFIG_ACPI_CUSTOM_METHOD)+= custom_method.o
 obj-$(CONFIG_ACPI_BGRT)		+= bgrt.o
 obj-$(CONFIG_ACPI_CPPC_LIB)	+= cppc_acpi.o
 obj-$(CONFIG_ACPI_SPCR_TABLE)	+= spcr.o
 obj-$(CONFIG_ACPI_DEBUGGER_USER) += acpi_dbg.o
 obj-$(CONFIG_ACPI_PPTT) 	+= pptt.o
+obj-$(CONFIG_ACPI_PFRUT)	+= pfr_update.o pfr_telemetry.o
 
 # processor has its own "processor." module_param namespace
-processor-y			:= processor_driver.o
+processor-y			:= processor_driver.o processor_thermal.o
 processor-$(CONFIG_ACPI_PROCESSOR_IDLE) += processor_idle.o
-processor-$(CONFIG_ACPI_CPU_FREQ_PSS)	+= processor_throttling.o	\
-	processor_thermal.o
+processor-$(CONFIG_ACPI_CPU_FREQ_PSS)	+= processor_throttling.o
 processor-$(CONFIG_CPU_FREQ)	+= processor_perflib.o
 
 obj-$(CONFIG_ACPI_PROCESSOR_AGGREGATOR) += acpi_pad.o
@@ -108,19 +121,16 @@ obj-$(CONFIG_ACPI_APEI)		+= apei/
 
 obj-$(CONFIG_ACPI_EXTLOG)	+= acpi_extlog.o
 
-obj-$(CONFIG_PMIC_OPREGION)	+= pmic/intel_pmic.o
-obj-$(CONFIG_BYTCRC_PMIC_OPREGION) += pmic/intel_pmic_bytcrc.o
-obj-$(CONFIG_CHTCRC_PMIC_OPREGION) += pmic/intel_pmic_chtcrc.o
-obj-$(CONFIG_XPOWER_PMIC_OPREGION) += pmic/intel_pmic_xpower.o
-obj-$(CONFIG_BXT_WC_PMIC_OPREGION) += pmic/intel_pmic_bxtwc.o
-obj-$(CONFIG_CHT_WC_PMIC_OPREGION) += pmic/intel_pmic_chtwc.o
-obj-$(CONFIG_CHT_DC_TI_PMIC_OPREGION) += pmic/intel_pmic_chtdc_ti.o
-
 obj-$(CONFIG_ACPI_CONFIGFS)	+= acpi_configfs.o
 
-obj-$(CONFIG_TPS68470_PMIC_OPREGION)	+= pmic/tps68470_pmic.o
+obj-y				+= pmic/
 
 video-objs			+= acpi_video.o video_detect.o
 obj-y				+= dptf/
 
 obj-$(CONFIG_ARM64)		+= arm64/
+
+obj-$(CONFIG_ACPI_VIOT)		+= viot.o
+
+obj-$(CONFIG_RISCV)		+= riscv/
+obj-$(CONFIG_X86)		+= x86/
diff --git a/drivers/acpi/ac.c b/drivers/acpi/ac.c
index 69d2db13886b..1f69be8f51a2 100644
--- a/drivers/acpi/ac.c
+++ b/drivers/acpi/ac.c
@@ -1,11 +1,13 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 /*
- *  acpi_ac.c - ACPI AC Adapter Driver ($Revision: 27 $)
+ *  acpi_ac.c - ACPI AC Adapter Driver (Revision: 27)
  *
  *  Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com>
  *  Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
  */
 
+#define pr_fmt(fmt) "ACPI: AC: " fmt
+
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/slab.h>
@@ -13,17 +15,12 @@
 #include <linux/types.h>
 #include <linux/dmi.h>
 #include <linux/delay.h>
-#ifdef CONFIG_ACPI_PROCFS_POWER
-#include <linux/proc_fs.h>
-#include <linux/seq_file.h>
-#endif
 #include <linux/platform_device.h>
 #include <linux/power_supply.h>
+#include <linux/string_choices.h>
 #include <linux/acpi.h>
 #include <acpi/battery.h>
 
-#define PREFIX "ACPI: "
-
 #define ACPI_AC_CLASS			"ac_adapter"
 #define ACPI_AC_DEVICE_NAME		"AC Adapter"
 #define ACPI_AC_FILE_STATE		"state"
@@ -32,22 +29,14 @@
 #define ACPI_AC_STATUS_ONLINE		0x01
 #define ACPI_AC_STATUS_UNKNOWN		0xFF
 
-#define _COMPONENT		ACPI_AC_COMPONENT
-ACPI_MODULE_NAME("ac");
-
 MODULE_AUTHOR("Paul Diefenbaugh");
 MODULE_DESCRIPTION("ACPI AC Adapter Driver");
 MODULE_LICENSE("GPL");
 
+static int acpi_ac_probe(struct platform_device *pdev);
+static void acpi_ac_remove(struct platform_device *pdev);
 
-static int acpi_ac_add(struct acpi_device *device);
-static int acpi_ac_remove(struct acpi_device *device);
-static void acpi_ac_notify(struct acpi_device *device, u32 event);
-
-struct acpi_ac_bl {
-	const char *hid;
-	int hrv;
-};
+static void acpi_ac_notify(acpi_handle handle, u32 event, void *data);
 
 static const struct acpi_device_id ac_device_ids[] = {
 	{"ACPI0003", 0},
@@ -55,53 +44,25 @@ static const struct acpi_device_id ac_device_ids[] = {
 };
 MODULE_DEVICE_TABLE(acpi, ac_device_ids);
 
-/* Lists of PMIC ACPI HIDs with an (often better) native charger driver */
-static const struct acpi_ac_bl acpi_ac_blacklist[] = {
-	{ "INT33F4", -1 }, /* X-Powers AXP288 PMIC */
-	{ "INT34D3",  3 }, /* Intel Cherrytrail Whiskey Cove PMIC */
-};
-
 #ifdef CONFIG_PM_SLEEP
 static int acpi_ac_resume(struct device *dev);
 #endif
 static SIMPLE_DEV_PM_OPS(acpi_ac_pm, NULL, acpi_ac_resume);
 
-#ifdef CONFIG_ACPI_PROCFS_POWER
-extern struct proc_dir_entry *acpi_lock_ac_dir(void);
-extern void *acpi_unlock_ac_dir(struct proc_dir_entry *acpi_ac_dir);
-#endif
-
-
 static int ac_sleep_before_get_state_ms;
-static int ac_check_pmic = 1;
-
-static struct acpi_driver acpi_ac_driver = {
-	.name = "ac",
-	.class = ACPI_AC_CLASS,
-	.ids = ac_device_ids,
-	.flags = ACPI_DRIVER_ALL_NOTIFY_EVENTS,
-	.ops = {
-		.add = acpi_ac_add,
-		.remove = acpi_ac_remove,
-		.notify = acpi_ac_notify,
-		},
-	.drv.pm = &acpi_ac_pm,
-};
+static int ac_only;
 
 struct acpi_ac {
 	struct power_supply *charger;
 	struct power_supply_desc charger_desc;
-	struct acpi_device * device;
+	struct acpi_device *device;
 	unsigned long long state;
 	struct notifier_block battery_nb;
 };
 
 #define to_acpi_ac(x) power_supply_get_drvdata(x)
 
-/* --------------------------------------------------------------------------
-                               AC Adapter Management
-   -------------------------------------------------------------------------- */
-
+/* AC Adapter Management */
 static int acpi_ac_get_state(struct acpi_ac *ac)
 {
 	acpi_status status = AE_OK;
@@ -109,11 +70,17 @@ static int acpi_ac_get_state(struct acpi_ac *ac)
 	if (!ac)
 		return -EINVAL;
 
+	if (ac_only) {
+		ac->state = 1;
+		return 0;
+	}
+
 	status = acpi_evaluate_integer(ac->device->handle, "_PSR", NULL,
 				       &ac->state);
 	if (ACPI_FAILURE(status)) {
-		ACPI_EXCEPTION((AE_INFO, status,
-				"Error reading AC Adapter state"));
+		acpi_handle_info(ac->device->handle,
+				"Error reading AC Adapter state: %s\n",
+				acpi_format_exception(status));
 		ac->state = ACPI_AC_STATUS_UNKNOWN;
 		return -ENODEV;
 	}
@@ -121,9 +88,7 @@ static int acpi_ac_get_state(struct acpi_ac *ac)
 	return 0;
 }
 
-/* --------------------------------------------------------------------------
-                            sysfs I/F
-   -------------------------------------------------------------------------- */
+/* sysfs I/F */
 static int get_ac_property(struct power_supply *psy,
 			   enum power_supply_property psp,
 			   union power_supply_propval *val)
@@ -143,100 +108,25 @@ static int get_ac_property(struct power_supply *psy,
 	default:
 		return -EINVAL;
 	}
+
 	return 0;
 }
 
-static enum power_supply_property ac_props[] = {
+static const enum power_supply_property ac_props[] = {
 	POWER_SUPPLY_PROP_ONLINE,
 };
 
-#ifdef CONFIG_ACPI_PROCFS_POWER
-/* --------------------------------------------------------------------------
-                              FS Interface (/proc)
-   -------------------------------------------------------------------------- */
-
-static struct proc_dir_entry *acpi_ac_dir;
-
-static int acpi_ac_seq_show(struct seq_file *seq, void *offset)
-{
-	struct acpi_ac *ac = seq->private;
-
-
-	if (!ac)
-		return 0;
-
-	if (acpi_ac_get_state(ac)) {
-		seq_puts(seq, "ERROR: Unable to read AC Adapter state\n");
-		return 0;
-	}
-
-	seq_puts(seq, "state:                   ");
-	switch (ac->state) {
-	case ACPI_AC_STATUS_OFFLINE:
-		seq_puts(seq, "off-line\n");
-		break;
-	case ACPI_AC_STATUS_ONLINE:
-		seq_puts(seq, "on-line\n");
-		break;
-	default:
-		seq_puts(seq, "unknown\n");
-		break;
-	}
-
-	return 0;
-}
-
-static int acpi_ac_add_fs(struct acpi_ac *ac)
-{
-	struct proc_dir_entry *entry = NULL;
-
-	printk(KERN_WARNING PREFIX "Deprecated procfs I/F for AC is loaded,"
-			" please retry with CONFIG_ACPI_PROCFS_POWER cleared\n");
-	if (!acpi_device_dir(ac->device)) {
-		acpi_device_dir(ac->device) =
-			proc_mkdir(acpi_device_bid(ac->device), acpi_ac_dir);
-		if (!acpi_device_dir(ac->device))
-			return -ENODEV;
-	}
-
-	/* 'state' [R] */
-	entry = proc_create_single_data(ACPI_AC_FILE_STATE, S_IRUGO,
-			acpi_device_dir(ac->device), acpi_ac_seq_show, ac);
-	if (!entry)
-		return -ENODEV;
-	return 0;
-}
-
-static int acpi_ac_remove_fs(struct acpi_ac *ac)
-{
-
-	if (acpi_device_dir(ac->device)) {
-		remove_proc_entry(ACPI_AC_FILE_STATE,
-				  acpi_device_dir(ac->device));
-		remove_proc_entry(acpi_device_bid(ac->device), acpi_ac_dir);
-		acpi_device_dir(ac->device) = NULL;
-	}
-
-	return 0;
-}
-#endif
-
-/* --------------------------------------------------------------------------
-                                   Driver Model
-   -------------------------------------------------------------------------- */
-
-static void acpi_ac_notify(struct acpi_device *device, u32 event)
+/* Driver Model */
+static void acpi_ac_notify(acpi_handle handle, u32 event, void *data)
 {
-	struct acpi_ac *ac = acpi_driver_data(device);
-
-	if (!ac)
-		return;
+	struct acpi_ac *ac = data;
+	struct acpi_device *adev = ac->device;
 
 	switch (event) {
 	default:
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-				  "Unsupported event [0x%x]\n", event));
-	/* fall through */
+		acpi_handle_debug(adev->handle, "Unsupported event [0x%x]\n",
+				  event);
+		fallthrough;
 	case ACPI_AC_NOTIFY_STATUS:
 	case ACPI_NOTIFY_BUS_CHECK:
 	case ACPI_NOTIFY_DEVICE_CHECK:
@@ -251,14 +141,12 @@ static void acpi_ac_notify(struct acpi_device *device, u32 event)
 			msleep(ac_sleep_before_get_state_ms);
 
 		acpi_ac_get_state(ac);
-		acpi_bus_generate_netlink_event(device->pnp.device_class,
-						  dev_name(&device->dev), event,
+		acpi_bus_generate_netlink_event(adev->pnp.device_class,
+						  dev_name(&adev->dev), event,
 						  (u32) ac->state);
-		acpi_notifier_call_chain(device, event, (u32) ac->state);
-		kobject_uevent(&ac->charger->dev.kobj, KOBJ_CHANGE);
+		acpi_notifier_call_chain(adev, event, (u32) ac->state);
+		power_supply_changed(ac->charger);
 	}
-
-	return;
 }
 
 static int acpi_ac_battery_notify(struct notifier_block *nb,
@@ -270,7 +158,7 @@ static int acpi_ac_battery_notify(struct notifier_block *nb,
 	/*
 	 * On HP Pavilion dv6-6179er AC status notifications aren't triggered
 	 * when adapter is plugged/unplugged. However, battery status
-	 * notifcations are triggered when battery starts charging or
+	 * notifications are triggered when battery starts charging or
 	 * discharging. Re-reading AC status triggers lost AC notifications,
 	 * if AC status has changed.
 	 */
@@ -287,28 +175,19 @@ static int __init thinkpad_e530_quirk(const struct dmi_system_id *d)
 	return 0;
 }
 
-static int __init ac_do_not_check_pmic_quirk(const struct dmi_system_id *d)
+static int __init ac_only_quirk(const struct dmi_system_id *d)
 {
-	ac_check_pmic = 0;
+	ac_only = 1;
 	return 0;
 }
 
 /* Please keep this list alphabetically sorted */
 static const struct dmi_system_id ac_dmi_table[]  __initconst = {
 	{
-		/* ECS EF20EA, AXP288 PMIC but uses separate fuel-gauge */
-		.callback = ac_do_not_check_pmic_quirk,
-		.matches = {
-			DMI_MATCH(DMI_PRODUCT_NAME, "EF20EA"),
-		},
-	},
-	{
-		/* Lenovo Ideapad Miix 320, AXP288 PMIC, separate fuel-gauge */
-		.callback = ac_do_not_check_pmic_quirk,
+		/* Kodlix GK45 returning incorrect state */
+		.callback = ac_only_quirk,
 		.matches = {
-			DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
-			DMI_MATCH(DMI_PRODUCT_NAME, "80XF"),
-			DMI_MATCH(DMI_PRODUCT_VERSION, "Lenovo MIIX 320-10ICR"),
+			DMI_MATCH(DMI_PRODUCT_NAME, "GK45"),
 		},
 	},
 	{
@@ -322,61 +201,59 @@ static const struct dmi_system_id ac_dmi_table[]  __initconst = {
 	{},
 };
 
-static int acpi_ac_add(struct acpi_device *device)
+static int acpi_ac_probe(struct platform_device *pdev)
 {
+	struct acpi_device *adev = ACPI_COMPANION(&pdev->dev);
 	struct power_supply_config psy_cfg = {};
-	int result = 0;
-	struct acpi_ac *ac = NULL;
-
-
-	if (!device)
-		return -EINVAL;
+	struct acpi_ac *ac;
+	int result;
 
 	ac = kzalloc(sizeof(struct acpi_ac), GFP_KERNEL);
 	if (!ac)
 		return -ENOMEM;
 
-	ac->device = device;
-	strcpy(acpi_device_name(device), ACPI_AC_DEVICE_NAME);
-	strcpy(acpi_device_class(device), ACPI_AC_CLASS);
-	device->driver_data = ac;
+	ac->device = adev;
+	strscpy(acpi_device_name(adev), ACPI_AC_DEVICE_NAME);
+	strscpy(acpi_device_class(adev), ACPI_AC_CLASS);
+
+	platform_set_drvdata(pdev, ac);
 
 	result = acpi_ac_get_state(ac);
 	if (result)
-		goto end;
+		goto err_release_ac;
 
 	psy_cfg.drv_data = ac;
 
-	ac->charger_desc.name = acpi_device_bid(device);
-#ifdef CONFIG_ACPI_PROCFS_POWER
-	result = acpi_ac_add_fs(ac);
-	if (result)
-		goto end;
-#endif
+	ac->charger_desc.name = acpi_device_bid(adev);
 	ac->charger_desc.type = POWER_SUPPLY_TYPE_MAINS;
 	ac->charger_desc.properties = ac_props;
 	ac->charger_desc.num_properties = ARRAY_SIZE(ac_props);
 	ac->charger_desc.get_property = get_ac_property;
-	ac->charger = power_supply_register(&ac->device->dev,
+	ac->charger = power_supply_register(&pdev->dev,
 					    &ac->charger_desc, &psy_cfg);
 	if (IS_ERR(ac->charger)) {
 		result = PTR_ERR(ac->charger);
-		goto end;
+		goto err_release_ac;
 	}
 
-	printk(KERN_INFO PREFIX "%s [%s] (%s)\n",
-	       acpi_device_name(device), acpi_device_bid(device),
-	       ac->state ? "on-line" : "off-line");
+	pr_info("%s [%s] (%s-line)\n", acpi_device_name(adev),
+		acpi_device_bid(adev), str_on_off(ac->state));
 
 	ac->battery_nb.notifier_call = acpi_ac_battery_notify;
 	register_acpi_notifier(&ac->battery_nb);
-end:
-	if (result) {
-#ifdef CONFIG_ACPI_PROCFS_POWER
-		acpi_ac_remove_fs(ac);
-#endif
-		kfree(ac);
-	}
+
+	result = acpi_dev_install_notify_handler(adev, ACPI_ALL_NOTIFY,
+						 acpi_ac_notify, ac);
+	if (result)
+		goto err_unregister;
+
+	return 0;
+
+err_unregister:
+	power_supply_unregister(ac->charger);
+	unregister_acpi_notifier(&ac->battery_nb);
+err_release_ac:
+	kfree(ac);
 
 	return result;
 }
@@ -384,93 +261,65 @@ end:
 #ifdef CONFIG_PM_SLEEP
 static int acpi_ac_resume(struct device *dev)
 {
-	struct acpi_ac *ac;
-	unsigned old_state;
-
-	if (!dev)
-		return -EINVAL;
-
-	ac = acpi_driver_data(to_acpi_device(dev));
-	if (!ac)
-		return -EINVAL;
+	struct acpi_ac *ac = dev_get_drvdata(dev);
+	unsigned int old_state;
 
 	old_state = ac->state;
 	if (acpi_ac_get_state(ac))
 		return 0;
 	if (old_state != ac->state)
-		kobject_uevent(&ac->charger->dev.kobj, KOBJ_CHANGE);
+		power_supply_changed(ac->charger);
+
 	return 0;
 }
 #else
 #define acpi_ac_resume NULL
 #endif
 
-static int acpi_ac_remove(struct acpi_device *device)
+static void acpi_ac_remove(struct platform_device *pdev)
 {
-	struct acpi_ac *ac = NULL;
-
-
-	if (!device || !acpi_driver_data(device))
-		return -EINVAL;
-
-	ac = acpi_driver_data(device);
+	struct acpi_ac *ac = platform_get_drvdata(pdev);
 
+	acpi_dev_remove_notify_handler(ac->device, ACPI_ALL_NOTIFY,
+				       acpi_ac_notify);
 	power_supply_unregister(ac->charger);
 	unregister_acpi_notifier(&ac->battery_nb);
 
-#ifdef CONFIG_ACPI_PROCFS_POWER
-	acpi_ac_remove_fs(ac);
-#endif
-
 	kfree(ac);
-
-	return 0;
 }
 
+static struct platform_driver acpi_ac_driver = {
+	.probe = acpi_ac_probe,
+	.remove = acpi_ac_remove,
+	.driver = {
+		.name = "ac",
+		.acpi_match_table = ac_device_ids,
+		.pm = &acpi_ac_pm,
+	},
+};
+
 static int __init acpi_ac_init(void)
 {
-	unsigned int i;
 	int result;
 
 	if (acpi_disabled)
 		return -ENODEV;
 
-	dmi_check_system(ac_dmi_table);
-
-	if (ac_check_pmic) {
-		for (i = 0; i < ARRAY_SIZE(acpi_ac_blacklist); i++)
-			if (acpi_dev_present(acpi_ac_blacklist[i].hid, "1",
-					     acpi_ac_blacklist[i].hrv)) {
-				pr_info(PREFIX "AC: found native %s PMIC, not loading\n",
-					acpi_ac_blacklist[i].hid);
-				return -ENODEV;
-			}
-	}
-
-#ifdef CONFIG_ACPI_PROCFS_POWER
-	acpi_ac_dir = acpi_lock_ac_dir();
-	if (!acpi_ac_dir)
+	if (acpi_quirk_skip_acpi_ac_and_battery())
 		return -ENODEV;
-#endif
 
+	dmi_check_system(ac_dmi_table);
 
-	result = acpi_bus_register_driver(&acpi_ac_driver);
-	if (result < 0) {
-#ifdef CONFIG_ACPI_PROCFS_POWER
-		acpi_unlock_ac_dir(acpi_ac_dir);
-#endif
+	result = platform_driver_register(&acpi_ac_driver);
+	if (result < 0)
 		return -ENODEV;
-	}
 
 	return 0;
 }
 
 static void __exit acpi_ac_exit(void)
 {
-	acpi_bus_unregister_driver(&acpi_ac_driver);
-#ifdef CONFIG_ACPI_PROCFS_POWER
-	acpi_unlock_ac_dir(acpi_ac_dir);
-#endif
+	platform_driver_unregister(&acpi_ac_driver);
 }
 module_init(acpi_ac_init);
 module_exit(acpi_ac_exit);
diff --git a/drivers/acpi/acpi_amba.c b/drivers/acpi/acpi_amba.c
deleted file mode 100644
index 49b781a9cd97..000000000000
--- a/drivers/acpi/acpi_amba.c
+++ /dev/null
@@ -1,127 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-
-/*
- * ACPI support for platform bus type.
- *
- * Copyright (C) 2015, Linaro Ltd
- * Author: Graeme Gregory <graeme.gregory@linaro.org>
- */
-
-#include <linux/acpi.h>
-#include <linux/amba/bus.h>
-#include <linux/clkdev.h>
-#include <linux/clk-provider.h>
-#include <linux/device.h>
-#include <linux/err.h>
-#include <linux/ioport.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-
-#include "internal.h"
-
-static const struct acpi_device_id amba_id_list[] = {
-	{"ARMH0061", 0}, /* PL061 GPIO Device */
-	{"ARMHC500", 0}, /* ARM CoreSight ETM4x */
-	{"ARMHC501", 0}, /* ARM CoreSight ETR */
-	{"ARMHC502", 0}, /* ARM CoreSight STM */
-	{"ARMHC503", 0}, /* ARM CoreSight Debug */
-	{"ARMHC979", 0}, /* ARM CoreSight TPIU */
-	{"ARMHC97C", 0}, /* ARM CoreSight SoC-400 TMC, SoC-600 ETF/ETB */
-	{"ARMHC98D", 0}, /* ARM CoreSight Dynamic Replicator */
-	{"ARMHC9CA", 0}, /* ARM CoreSight CATU */
-	{"ARMHC9FF", 0}, /* ARM CoreSight Dynamic Funnel */
-	{"", 0},
-};
-
-static void amba_register_dummy_clk(void)
-{
-	static struct clk *amba_dummy_clk;
-
-	/* If clock already registered */
-	if (amba_dummy_clk)
-		return;
-
-	amba_dummy_clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, 0, 0);
-	clk_register_clkdev(amba_dummy_clk, "apb_pclk", NULL);
-}
-
-static int amba_handler_attach(struct acpi_device *adev,
-				const struct acpi_device_id *id)
-{
-	struct amba_device *dev;
-	struct resource_entry *rentry;
-	struct list_head resource_list;
-	bool address_found = false;
-	int irq_no = 0;
-	int ret;
-
-	/* If the ACPI node already has a physical device attached, skip it. */
-	if (adev->physical_node_count)
-		return 0;
-
-	dev = amba_device_alloc(dev_name(&adev->dev), 0, 0);
-	if (!dev) {
-		dev_err(&adev->dev, "%s(): amba_device_alloc() failed\n",
-			__func__);
-		return -ENOMEM;
-	}
-
-	INIT_LIST_HEAD(&resource_list);
-	ret = acpi_dev_get_resources(adev, &resource_list, NULL, NULL);
-	if (ret < 0)
-		goto err_free;
-
-	list_for_each_entry(rentry, &resource_list, node) {
-		switch (resource_type(rentry->res)) {
-		case IORESOURCE_MEM:
-			if (!address_found) {
-				dev->res = *rentry->res;
-				address_found = true;
-			}
-			break;
-		case IORESOURCE_IRQ:
-			if (irq_no < AMBA_NR_IRQS)
-				dev->irq[irq_no++] = rentry->res->start;
-			break;
-		default:
-			dev_warn(&adev->dev, "Invalid resource\n");
-			break;
-		}
-	}
-
-	acpi_dev_free_resource_list(&resource_list);
-
-	/*
-	 * If the ACPI node has a parent and that parent has a physical device
-	 * attached to it, that physical device should be the parent of
-	 * the amba device we are about to create.
-	 */
-	if (adev->parent)
-		dev->dev.parent = acpi_get_first_physical_node(adev->parent);
-
-	ACPI_COMPANION_SET(&dev->dev, adev);
-
-	ret = amba_device_add(dev, &iomem_resource);
-	if (ret) {
-		dev_err(&adev->dev, "%s(): amba_device_add() failed (%d)\n",
-		       __func__, ret);
-		goto err_free;
-	}
-
-	return 1;
-
-err_free:
-	amba_device_put(dev);
-	return ret;
-}
-
-static struct acpi_scan_handler amba_handler = {
-	.ids = amba_id_list,
-	.attach = amba_handler_attach,
-};
-
-void __init acpi_amba_init(void)
-{
-	amba_register_dummy_clk();
-	acpi_scan_add_handler(&amba_handler);
-}
diff --git a/drivers/acpi/acpi_apd.c b/drivers/acpi/acpi_apd.c
index ba2612e9a0eb..49539f7528c6 100644
--- a/drivers/acpi/acpi_apd.c
+++ b/drivers/acpi/acpi_apd.c
@@ -7,39 +7,28 @@
  *	Wu, Jeff <Jeff.Wu@amd.com>
  */
 
-#include <linux/clk-provider.h>
-#include <linux/platform_data/clk-st.h>
-#include <linux/platform_device.h>
-#include <linux/pm_domain.h>
-#include <linux/clkdev.h>
 #include <linux/acpi.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
 #include <linux/err.h>
 #include <linux/io.h>
-#include <linux/pm.h>
+#include <linux/platform_data/clk-fch.h>
+#include <linux/platform_device.h>
 
 #include "internal.h"
 
-ACPI_MODULE_NAME("acpi_apd");
 struct apd_private_data;
 
 /**
- * ACPI_APD_SYSFS : add device attributes in sysfs
- * ACPI_APD_PM : attach power domain to device
- */
-#define ACPI_APD_SYSFS	BIT(0)
-#define ACPI_APD_PM	BIT(1)
-
-/**
  * struct apd_device_desc - a descriptor for apd device
- * @flags: device flags like %ACPI_APD_SYSFS, %ACPI_APD_PM
  * @fixed_clk_rate: fixed rate input clock source for acpi device;
  *			0 means no fixed rate input clock source
+ * @properties: build-in properties of the device such as UART
  * @setup: a hook routine to set device resource during create platform device
  *
  * Device description defined as acpi_device_id.driver_data
  */
 struct apd_device_desc {
-	unsigned int flags;
 	unsigned int fixed_clk_rate;
 	struct property_entry *properties;
 	int (*setup)(struct apd_private_data *pdata);
@@ -72,18 +61,12 @@ static int acpi_apd_setup(struct apd_private_data *pdata)
 
 #ifdef CONFIG_X86_AMD_PLATFORM_DEVICE
 
-static int misc_check_res(struct acpi_resource *ares, void *data)
-{
-	struct resource res;
-
-	return !acpi_dev_resource_memory(ares, &res);
-}
-
-static int st_misc_setup(struct apd_private_data *pdata)
+static int fch_misc_setup(struct apd_private_data *pdata)
 {
 	struct acpi_device *adev = pdata->adev;
+	const union acpi_object *obj;
 	struct platform_device *clkdev;
-	struct st_clk_data *clk_data;
+	struct fch_clk_data *clk_data;
 	struct resource_entry *rentry;
 	struct list_head resource_list;
 	int ret;
@@ -93,20 +76,33 @@ static int st_misc_setup(struct apd_private_data *pdata)
 		return -ENOMEM;
 
 	INIT_LIST_HEAD(&resource_list);
-	ret = acpi_dev_get_resources(adev, &resource_list, misc_check_res,
-				     NULL);
+	ret = acpi_dev_get_memory_resources(adev, &resource_list);
 	if (ret < 0)
 		return -ENOENT;
 
+	if (!acpi_dev_get_property(adev, "clk-name", ACPI_TYPE_STRING, &obj)) {
+		clk_data->name = devm_kzalloc(&adev->dev, obj->string.length,
+					      GFP_KERNEL);
+		if (!clk_data->name)
+			return -ENOMEM;
+
+		strscpy(clk_data->name, obj->string.pointer, obj->string.length);
+	} else {
+		/* Set default name to mclk if entry missing in firmware */
+		clk_data->name = "mclk";
+	}
+
 	list_for_each_entry(rentry, &resource_list, node) {
 		clk_data->base = devm_ioremap(&adev->dev, rentry->res->start,
 					      resource_size(rentry->res));
 		break;
 	}
+	if (!clk_data->base)
+		return -ENOMEM;
 
 	acpi_dev_free_resource_list(&resource_list);
 
-	clkdev = platform_device_register_data(&adev->dev, "clk-st",
+	clkdev = platform_device_register_data(&adev->dev, "clk-fch",
 					       PLATFORM_DEVID_NONE, clk_data,
 					       sizeof(*clk_data));
 	return PTR_ERR_OR_ZERO(clkdev);
@@ -122,6 +118,11 @@ static const struct apd_device_desc wt_i2c_desc = {
 	.fixed_clk_rate = 150000000,
 };
 
+static const struct apd_device_desc wt_i3c_desc = {
+	.setup = acpi_apd_setup,
+	.fixed_clk_rate = 125000000,
+};
+
 static struct property_entry uart_properties[] = {
 	PROPERTY_ENTRY_U32("reg-io-width", 4),
 	PROPERTY_ENTRY_U32("reg-shift", 2),
@@ -135,10 +136,10 @@ static const struct apd_device_desc cz_uart_desc = {
 	.properties = uart_properties,
 };
 
-static const struct apd_device_desc st_misc_desc = {
-	.setup = st_misc_setup,
+static const struct apd_device_desc fch_misc_desc = {
+	.setup = fch_misc_setup,
 };
-#endif
+#endif /* CONFIG_X86_AMD_PLATFORM_DEVICE */
 
 #ifdef CONFIG_ARM64
 static const struct apd_device_desc xgene_i2c_desc = {
@@ -180,18 +181,14 @@ static const struct apd_device_desc hip08_spi_desc = {
 	.setup = acpi_apd_setup,
 	.fixed_clk_rate = 250000000,
 };
-#endif
-
-#else
+#endif /* CONFIG_ARM64 */
 
-#define APD_ADDR(desc) (0UL)
-
-#endif /* CONFIG_X86_AMD_PLATFORM_DEVICE */
+#endif
 
-/**
-* Create platform device during acpi scan attach handle.
-* Return value > 0 on success of creating device.
-*/
+/*
+ * Create platform device during acpi scan attach handle.
+ * Return value > 0 on success of creating device.
+ */
 static int acpi_apd_create_device(struct acpi_device *adev,
 				   const struct acpi_device_id *id)
 {
@@ -235,11 +232,15 @@ static const struct acpi_device_id acpi_apd_device_ids[] = {
 	/* Generic apd devices */
 #ifdef CONFIG_X86_AMD_PLATFORM_DEVICE
 	{ "AMD0010", APD_ADDR(cz_i2c_desc) },
-	{ "AMDI0010", APD_ADDR(wt_i2c_desc) },
 	{ "AMD0020", APD_ADDR(cz_uart_desc) },
-	{ "AMDI0020", APD_ADDR(cz_uart_desc) },
 	{ "AMD0030", },
-	{ "AMD0040", APD_ADDR(st_misc_desc)},
+	{ "AMD0040", APD_ADDR(fch_misc_desc)},
+	{ "AMDI0010", APD_ADDR(wt_i2c_desc) },
+	{ "AMDI0015", APD_ADDR(wt_i3c_desc) },
+	{ "AMDI0019", APD_ADDR(wt_i2c_desc) },
+	{ "AMDI0020", APD_ADDR(cz_uart_desc) },
+	{ "AMDI0022", APD_ADDR(cz_uart_desc) },
+	{ "HYGO0010", APD_ADDR(wt_i2c_desc) },
 #endif
 #ifdef CONFIG_ARM64
 	{ "APMC0D0F", APD_ADDR(xgene_i2c_desc) },
diff --git a/drivers/acpi/acpi_cmos_rtc.c b/drivers/acpi/acpi_cmos_rtc.c
deleted file mode 100644
index 33ac6cb428fe..000000000000
--- a/drivers/acpi/acpi_cmos_rtc.c
+++ /dev/null
@@ -1,87 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * ACPI support for CMOS RTC Address Space access
- *
- * Copyright (C) 2013, Intel Corporation
- * Authors: Lan Tianyu <tianyu.lan@intel.com>
- */
-
-#include <linux/acpi.h>
-#include <linux/device.h>
-#include <linux/err.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/mc146818rtc.h>
-
-#include "internal.h"
-
-ACPI_MODULE_NAME("cmos rtc");
-
-static const struct acpi_device_id acpi_cmos_rtc_ids[] = {
-	{ "PNP0B00" },
-	{ "PNP0B01" },
-	{ "PNP0B02" },
-	{}
-};
-
-static acpi_status
-acpi_cmos_rtc_space_handler(u32 function, acpi_physical_address address,
-		      u32 bits, u64 *value64,
-		      void *handler_context, void *region_context)
-{
-	int i;
-	u8 *value = (u8 *)value64;
-
-	if (address > 0xff || !value64)
-		return AE_BAD_PARAMETER;
-
-	if (function != ACPI_WRITE && function != ACPI_READ)
-		return AE_BAD_PARAMETER;
-
-	spin_lock_irq(&rtc_lock);
-
-	for (i = 0; i < DIV_ROUND_UP(bits, 8); ++i, ++address, ++value)
-		if (function == ACPI_READ)
-			*value = CMOS_READ(address);
-		else
-			CMOS_WRITE(*value, address);
-
-	spin_unlock_irq(&rtc_lock);
-
-	return AE_OK;
-}
-
-static int acpi_install_cmos_rtc_space_handler(struct acpi_device *adev,
-		const struct acpi_device_id *id)
-{
-	acpi_status status;
-
-	status = acpi_install_address_space_handler(adev->handle,
-			ACPI_ADR_SPACE_CMOS,
-			&acpi_cmos_rtc_space_handler,
-			NULL, NULL);
-	if (ACPI_FAILURE(status)) {
-		pr_err(PREFIX "Error installing CMOS-RTC region handler\n");
-		return -ENODEV;
-	}
-
-	return 1;
-}
-
-static void acpi_remove_cmos_rtc_space_handler(struct acpi_device *adev)
-{
-	if (ACPI_FAILURE(acpi_remove_address_space_handler(adev->handle,
-			ACPI_ADR_SPACE_CMOS, &acpi_cmos_rtc_space_handler)))
-		pr_err(PREFIX "Error removing CMOS-RTC region handler\n");
-}
-
-static struct acpi_scan_handler cmos_rtc_handler = {
-	.ids = acpi_cmos_rtc_ids,
-	.attach = acpi_install_cmos_rtc_space_handler,
-	.detach = acpi_remove_cmos_rtc_space_handler,
-};
-
-void __init acpi_cmos_rtc_init(void)
-{
-	acpi_scan_add_handler(&cmos_rtc_handler);
-}
diff --git a/drivers/acpi/acpi_configfs.c b/drivers/acpi/acpi_configfs.c
index ece8c1a921cc..c970792b11a4 100644
--- a/drivers/acpi/acpi_configfs.c
+++ b/drivers/acpi/acpi_configfs.c
@@ -11,9 +11,7 @@
 #include <linux/module.h>
 #include <linux/configfs.h>
 #include <linux/acpi.h>
-
-#include "acpica/accommon.h"
-#include "acpica/actables.h"
+#include <linux/security.h>
 
 static struct config_group *acpi_table_group;
 
@@ -28,7 +26,10 @@ static ssize_t acpi_table_aml_write(struct config_item *cfg,
 {
 	const struct acpi_table_header *header = data;
 	struct acpi_table *table;
-	int ret;
+	int ret = security_locked_down(LOCKDOWN_ACPI_TABLES);
+
+	if (ret)
+		return ret;
 
 	table = container_of(cfg, struct acpi_table, cfg);
 
@@ -69,7 +70,7 @@ static inline struct acpi_table_header *get_header(struct config_item *cfg)
 	if (!table->header)
 		pr_err("table not loaded\n");
 
-	return table->header;
+	return table->header ?: ERR_PTR(-EINVAL);
 }
 
 static ssize_t acpi_table_aml_read(struct config_item *cfg,
@@ -77,8 +78,8 @@ static ssize_t acpi_table_aml_read(struct config_item *cfg,
 {
 	struct acpi_table_header *h = get_header(cfg);
 
-	if (!h)
-		return -EINVAL;
+	if (IS_ERR(h))
+		return PTR_ERR(h);
 
 	if (data)
 		memcpy(data, h, h->length);
@@ -99,60 +100,60 @@ static ssize_t acpi_table_signature_show(struct config_item *cfg, char *str)
 {
 	struct acpi_table_header *h = get_header(cfg);
 
-	if (!h)
-		return -EINVAL;
+	if (IS_ERR(h))
+		return PTR_ERR(h);
 
-	return sprintf(str, "%.*s\n", ACPI_NAMESEG_SIZE, h->signature);
+	return sysfs_emit(str, "%.*s\n", ACPI_NAMESEG_SIZE, h->signature);
 }
 
 static ssize_t acpi_table_length_show(struct config_item *cfg, char *str)
 {
 	struct acpi_table_header *h = get_header(cfg);
 
-	if (!h)
-		return -EINVAL;
+	if (IS_ERR(h))
+		return PTR_ERR(h);
 
-	return sprintf(str, "%d\n", h->length);
+	return sysfs_emit(str, "%d\n", h->length);
 }
 
 static ssize_t acpi_table_revision_show(struct config_item *cfg, char *str)
 {
 	struct acpi_table_header *h = get_header(cfg);
 
-	if (!h)
-		return -EINVAL;
+	if (IS_ERR(h))
+		return PTR_ERR(h);
 
-	return sprintf(str, "%d\n", h->revision);
+	return sysfs_emit(str, "%d\n", h->revision);
 }
 
 static ssize_t acpi_table_oem_id_show(struct config_item *cfg, char *str)
 {
 	struct acpi_table_header *h = get_header(cfg);
 
-	if (!h)
-		return -EINVAL;
+	if (IS_ERR(h))
+		return PTR_ERR(h);
 
-	return sprintf(str, "%.*s\n", ACPI_OEM_ID_SIZE, h->oem_id);
+	return sysfs_emit(str, "%.*s\n", ACPI_OEM_ID_SIZE, h->oem_id);
 }
 
 static ssize_t acpi_table_oem_table_id_show(struct config_item *cfg, char *str)
 {
 	struct acpi_table_header *h = get_header(cfg);
 
-	if (!h)
-		return -EINVAL;
+	if (IS_ERR(h))
+		return PTR_ERR(h);
 
-	return sprintf(str, "%.*s\n", ACPI_OEM_TABLE_ID_SIZE, h->oem_table_id);
+	return sysfs_emit(str, "%.*s\n", ACPI_OEM_TABLE_ID_SIZE, h->oem_table_id);
 }
 
 static ssize_t acpi_table_oem_revision_show(struct config_item *cfg, char *str)
 {
 	struct acpi_table_header *h = get_header(cfg);
 
-	if (!h)
-		return -EINVAL;
+	if (IS_ERR(h))
+		return PTR_ERR(h);
 
-	return sprintf(str, "%d\n", h->oem_revision);
+	return sysfs_emit(str, "%d\n", h->oem_revision);
 }
 
 static ssize_t acpi_table_asl_compiler_id_show(struct config_item *cfg,
@@ -160,10 +161,10 @@ static ssize_t acpi_table_asl_compiler_id_show(struct config_item *cfg,
 {
 	struct acpi_table_header *h = get_header(cfg);
 
-	if (!h)
-		return -EINVAL;
+	if (IS_ERR(h))
+		return PTR_ERR(h);
 
-	return sprintf(str, "%.*s\n", ACPI_NAMESEG_SIZE, h->asl_compiler_id);
+	return sysfs_emit(str, "%.*s\n", ACPI_NAMESEG_SIZE, h->asl_compiler_id);
 }
 
 static ssize_t acpi_table_asl_compiler_revision_show(struct config_item *cfg,
@@ -171,10 +172,10 @@ static ssize_t acpi_table_asl_compiler_revision_show(struct config_item *cfg,
 {
 	struct acpi_table_header *h = get_header(cfg);
 
-	if (!h)
-		return -EINVAL;
+	if (IS_ERR(h))
+		return PTR_ERR(h);
 
-	return sprintf(str, "%d\n", h->asl_compiler_revision);
+	return sysfs_emit(str, "%d\n", h->asl_compiler_revision);
 }
 
 CONFIGFS_ATTR_RO(acpi_table_, signature);
@@ -222,8 +223,9 @@ static void acpi_table_drop_item(struct config_group *group,
 {
 	struct acpi_table *table = container_of(cfg, struct acpi_table, cfg);
 
-	ACPI_INFO(("Host-directed Dynamic ACPI Table Unload"));
+	pr_debug("Host-directed Dynamic ACPI Table Unload\n");
 	acpi_unload_table(table->index);
+	config_item_put(cfg);
 }
 
 static struct configfs_group_operations acpi_table_group_ops = {
@@ -263,7 +265,12 @@ static int __init acpi_configfs_init(void)
 
 	acpi_table_group = configfs_register_default_group(root, "table",
 							   &acpi_tables_type);
-	return PTR_ERR_OR_ZERO(acpi_table_group);
+	if (IS_ERR(acpi_table_group)) {
+		configfs_unregister_subsystem(&acpi_configfs);
+		return PTR_ERR(acpi_table_group);
+	}
+
+	return 0;
 }
 module_init(acpi_configfs_init);
 
diff --git a/drivers/acpi/acpi_dbg.c b/drivers/acpi/acpi_dbg.c
index 7a265c2171c0..515b20d0b698 100644
--- a/drivers/acpi/acpi_dbg.c
+++ b/drivers/acpi/acpi_dbg.c
@@ -117,13 +117,6 @@ static inline bool __acpi_aml_busy(void)
 	return false;
 }
 
-static inline bool __acpi_aml_opened(void)
-{
-	if (acpi_aml_io.flags & ACPI_AML_OPEN)
-		return true;
-	return false;
-}
-
 static inline bool __acpi_aml_used(void)
 {
 	return acpi_aml_io.usages ? true : false;
@@ -576,11 +569,11 @@ static int acpi_aml_release(struct inode *inode, struct file *file)
 	return 0;
 }
 
-static int acpi_aml_read_user(char __user *buf, int len)
+static ssize_t acpi_aml_read_user(char __user *buf, size_t len)
 {
-	int ret;
 	struct circ_buf *crc = &acpi_aml_io.out_crc;
-	int n;
+	ssize_t ret;
+	size_t n;
 	char *p;
 
 	ret = acpi_aml_lock_read(crc, ACPI_AML_OUT_USER);
@@ -589,7 +582,7 @@ static int acpi_aml_read_user(char __user *buf, int len)
 	/* sync head before removing logs */
 	smp_rmb();
 	p = &crc->buf[crc->tail];
-	n = min(len, circ_count_to_end(crc));
+	n = min_t(size_t, len, circ_count_to_end(crc));
 	if (copy_to_user(buf, p, n)) {
 		ret = -EFAULT;
 		goto out;
@@ -606,8 +599,8 @@ out:
 static ssize_t acpi_aml_read(struct file *file, char __user *buf,
 			     size_t count, loff_t *ppos)
 {
-	int ret = 0;
-	int size = 0;
+	ssize_t ret = 0;
+	ssize_t size = 0;
 
 	if (!count)
 		return 0;
@@ -646,11 +639,11 @@ again:
 	return size > 0 ? size : ret;
 }
 
-static int acpi_aml_write_user(const char __user *buf, int len)
+static ssize_t acpi_aml_write_user(const char __user *buf, size_t len)
 {
-	int ret;
 	struct circ_buf *crc = &acpi_aml_io.in_crc;
-	int n;
+	ssize_t ret;
+	size_t n;
 	char *p;
 
 	ret = acpi_aml_lock_write(crc, ACPI_AML_IN_USER);
@@ -659,7 +652,7 @@ static int acpi_aml_write_user(const char __user *buf, int len)
 	/* sync tail before inserting cmds */
 	smp_mb();
 	p = &crc->buf[crc->head];
-	n = min(len, circ_space_to_end(crc));
+	n = min_t(size_t, len, circ_space_to_end(crc));
 	if (copy_from_user(p, buf, n)) {
 		ret = -EFAULT;
 		goto out;
@@ -670,14 +663,14 @@ static int acpi_aml_write_user(const char __user *buf, int len)
 	ret = n;
 out:
 	acpi_aml_unlock_fifo(ACPI_AML_IN_USER, ret >= 0);
-	return n;
+	return ret;
 }
 
 static ssize_t acpi_aml_write(struct file *file, const char __user *buf,
 			      size_t count, loff_t *ppos)
 {
-	int ret = 0;
-	int size = 0;
+	ssize_t ret = 0;
+	ssize_t size = 0;
 
 	if (!count)
 		return 0;
@@ -745,10 +738,13 @@ static const struct acpi_debugger_ops acpi_aml_debugger = {
 	.notify_command_complete = acpi_aml_notify_command_complete,
 };
 
-int __init acpi_aml_init(void)
+static int __init acpi_aml_init(void)
 {
 	int ret;
 
+	if (acpi_disabled)
+		return -ENODEV;
+
 	/* Initialize AML IO interface */
 	mutex_init(&acpi_aml_io.lock);
 	init_waitqueue_head(&acpi_aml_io.wait);
@@ -771,7 +767,7 @@ int __init acpi_aml_init(void)
 	return 0;
 }
 
-void __exit acpi_aml_exit(void)
+static void __exit acpi_aml_exit(void)
 {
 	if (acpi_aml_initialized) {
 		acpi_unregister_debugger(&acpi_aml_debugger);
diff --git a/drivers/acpi/acpi_extlog.c b/drivers/acpi/acpi_extlog.c
index 8596a106a933..f6b9562779de 100644
--- a/drivers/acpi/acpi_extlog.c
+++ b/drivers/acpi/acpi_extlog.c
@@ -12,8 +12,10 @@
 #include <linux/ratelimit.h>
 #include <linux/edac.h>
 #include <linux/ras.h>
+#include <acpi/ghes.h>
 #include <asm/cpu.h>
 #include <asm/mce.h>
+#include <asm/msr.h>
 
 #include "apei/apei-internal.h"
 #include <ras/ras_event.h>
@@ -42,8 +44,6 @@ struct extlog_l1_head {
 	u8  rev1[12];
 };
 
-static int old_edac_report_status;
-
 static u8 extlog_dsm_uuid[] __initdata = "663E35AF-CC10-41A4-88EA-5470AF055295";
 
 /* L1 table related physical address */
@@ -140,15 +140,20 @@ static int extlog_print(struct notifier_block *nb, unsigned long val,
 	int	cpu = mce->extcpu;
 	struct acpi_hest_generic_status *estatus, *tmp;
 	struct acpi_hest_generic_data *gdata;
-	const guid_t *fru_id = &guid_null;
-	char *fru_text = "";
+	const guid_t *fru_id;
+	char *fru_text;
 	guid_t *sec_type;
 	static u32 err_seq;
 
 	estatus = extlog_elog_entry_check(cpu, bank);
-	if (estatus == NULL)
+	if (!estatus)
 		return NOTIFY_DONE;
 
+	if (mce->kflags & MCE_HANDLED_CEC) {
+		estatus->block_status = 0;
+		return NOTIFY_DONE;
+	}
+
 	memcpy(elog_buf, (void *)estatus, ELOG_ENTRY_LEN);
 	/* clear record status to enable BIOS to update it again */
 	estatus->block_status = 0;
@@ -162,21 +167,28 @@ static int extlog_print(struct notifier_block *nb, unsigned long val,
 
 	/* log event via trace */
 	err_seq++;
-	gdata = (struct acpi_hest_generic_data *)(tmp + 1);
-	if (gdata->validation_bits & CPER_SEC_VALID_FRU_ID)
-		fru_id = (guid_t *)gdata->fru_id;
-	if (gdata->validation_bits & CPER_SEC_VALID_FRU_TEXT)
-		fru_text = gdata->fru_text;
-	sec_type = (guid_t *)gdata->section_type;
-	if (guid_equal(sec_type, &CPER_SEC_PLATFORM_MEM)) {
-		struct cper_sec_mem_err *mem = (void *)(gdata + 1);
-		if (gdata->error_data_length >= sizeof(*mem))
-			trace_extlog_mem_event(mem, err_seq, fru_id, fru_text,
-					       (u8)gdata->error_severity);
+	apei_estatus_for_each_section(tmp, gdata) {
+		if (gdata->validation_bits & CPER_SEC_VALID_FRU_ID)
+			fru_id = (guid_t *)gdata->fru_id;
+		else
+			fru_id = &guid_null;
+		if (gdata->validation_bits & CPER_SEC_VALID_FRU_TEXT)
+			fru_text = gdata->fru_text;
+		else
+			fru_text = "";
+		sec_type = (guid_t *)gdata->section_type;
+		if (guid_equal(sec_type, &CPER_SEC_PLATFORM_MEM)) {
+			struct cper_sec_mem_err *mem = acpi_hest_get_payload(gdata);
+
+			if (gdata->error_data_length >= sizeof(*mem))
+				trace_extlog_mem_event(mem, err_seq, fru_id, fru_text,
+						       (u8)gdata->error_severity);
+		}
 	}
 
 out:
-	return NOTIFY_STOP;
+	mce->kflags |= MCE_HANDLED_EXTLOG;
+	return NOTIFY_OK;
 }
 
 static bool __init extlog_get_l1addr(void)
@@ -223,16 +235,11 @@ static int __init extlog_init(void)
 	u64 cap;
 	int rc;
 
-	rdmsrl(MSR_IA32_MCG_CAP, cap);
-
-	if (!(cap & MCG_ELOG_P) || !extlog_get_l1addr())
+	if (rdmsrq_safe(MSR_IA32_MCG_CAP, &cap) ||
+	    !(cap & MCG_ELOG_P) ||
+	    !extlog_get_l1addr())
 		return -ENODEV;
 
-	if (edac_get_report_status() == EDAC_REPORTING_FORCE) {
-		pr_warn("Not loading eMCA, error reporting force-enabled through EDAC.\n");
-		return -EPERM;
-	}
-
 	rc = -EINVAL;
 	/* get L1 header to fetch necessary information */
 	l1_hdr_size = sizeof(struct extlog_l1_head);
@@ -245,6 +252,10 @@ static int __init extlog_init(void)
 	}
 
 	extlog_l1_hdr = acpi_os_map_iomem(l1_dirbase, l1_hdr_size);
+	if (!extlog_l1_hdr) {
+		rc = -ENOMEM;
+		goto err_release_l1_hdr;
+	}
 	l1_head = (struct extlog_l1_head *)extlog_l1_hdr;
 	l1_size = l1_head->total_len;
 	l1_percpu_entry = l1_head->entries;
@@ -262,6 +273,10 @@ static int __init extlog_init(void)
 		goto err;
 	}
 	extlog_l1_addr = acpi_os_map_iomem(l1_dirbase, l1_size);
+	if (!extlog_l1_addr) {
+		rc = -ENOMEM;
+		goto err_release_l1_dir;
+	}
 	l1_entry_base = (u64 *)((u8 *)extlog_l1_addr + l1_hdr_size);
 
 	/* remap elog table */
@@ -273,6 +288,10 @@ static int __init extlog_init(void)
 		goto err_release_l1_dir;
 	}
 	elog_addr = acpi_os_map_iomem(elog_base, elog_size);
+	if (!elog_addr) {
+		rc = -ENOMEM;
+		goto err_release_elog;
+	}
 
 	rc = -ENOMEM;
 	/* allocate buffer to save elog record */
@@ -280,12 +299,6 @@ static int __init extlog_init(void)
 	if (elog_buf == NULL)
 		goto err_release_elog;
 
-	/*
-	 * eMCA event report method has higher priority than EDAC method,
-	 * unless EDAC event report method is mandatory.
-	 */
-	old_edac_report_status = edac_get_report_status();
-	edac_set_report_status(EDAC_REPORTING_DISABLED);
 	mce_register_decode_chain(&extlog_mce_dec);
 	/* enable OS to be involved to take over management from BIOS */
 	((struct extlog_l1_head *)extlog_l1_addr)->flags |= FLAG_OS_OPTIN;
@@ -300,6 +313,8 @@ err_release_l1_dir:
 	if (extlog_l1_addr)
 		acpi_os_unmap_iomem(extlog_l1_addr, l1_size);
 	release_mem_region(l1_dirbase, l1_size);
+err_release_l1_hdr:
+	release_mem_region(l1_dirbase, l1_hdr_size);
 err:
 	pr_warn(FW_BUG "Extended error log disabled because of problems parsing f/w tables\n");
 	return rc;
@@ -307,11 +322,11 @@ err:
 
 static void __exit extlog_exit(void)
 {
-	edac_set_report_status(old_edac_report_status);
 	mce_unregister_decode_chain(&extlog_mce_dec);
-	((struct extlog_l1_head *)extlog_l1_addr)->flags &= ~FLAG_OS_OPTIN;
-	if (extlog_l1_addr)
+	if (extlog_l1_addr) {
+		((struct extlog_l1_head *)extlog_l1_addr)->flags &= ~FLAG_OS_OPTIN;
 		acpi_os_unmap_iomem(extlog_l1_addr, l1_size);
+	}
 	if (elog_addr)
 		acpi_os_unmap_iomem(elog_addr, elog_size);
 	release_mem_region(elog_base, elog_size);
diff --git a/drivers/acpi/acpi_ffh.c b/drivers/acpi/acpi_ffh.c
new file mode 100644
index 000000000000..8d5126963dc7
--- /dev/null
+++ b/drivers/acpi/acpi_ffh.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Author: Sudeep Holla <sudeep.holla@arm.com>
+ * Copyright 2022 Arm Limited
+ */
+#include <linux/kernel.h>
+#include <linux/acpi.h>
+#include <linux/completion.h>
+#include <linux/idr.h>
+#include <linux/io.h>
+
+static struct acpi_ffh_info ffh_ctx;
+
+int __weak acpi_ffh_address_space_arch_setup(void *handler_ctxt,
+					     void **region_ctxt)
+{
+	return -EOPNOTSUPP;
+}
+
+int __weak acpi_ffh_address_space_arch_handler(acpi_integer *value,
+					       void *region_context)
+{
+	return -EOPNOTSUPP;
+}
+
+static acpi_status
+acpi_ffh_address_space_setup(acpi_handle region_handle, u32 function,
+			     void *handler_context,  void **region_context)
+{
+	return acpi_ffh_address_space_arch_setup(handler_context,
+						 region_context);
+}
+
+static acpi_status
+acpi_ffh_address_space_handler(u32 function, acpi_physical_address addr,
+			       u32 bits, acpi_integer *value,
+			       void *handler_context, void *region_context)
+{
+	return acpi_ffh_address_space_arch_handler(value, region_context);
+}
+
+void __init acpi_init_ffh(void)
+{
+	acpi_status status;
+
+	status = acpi_install_address_space_handler(ACPI_ROOT_OBJECT,
+						    ACPI_ADR_SPACE_FIXED_HARDWARE,
+						    &acpi_ffh_address_space_handler,
+						    &acpi_ffh_address_space_setup,
+						    &ffh_ctx);
+	if (ACPI_FAILURE(status))
+		pr_alert("OperationRegion handler could not be installed\n");
+}
diff --git a/drivers/acpi/acpi_fpdt.c b/drivers/acpi/acpi_fpdt.c
new file mode 100644
index 000000000000..271092f2700a
--- /dev/null
+++ b/drivers/acpi/acpi_fpdt.c
@@ -0,0 +1,316 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/*
+ * FPDT support for exporting boot and suspend/resume performance data
+ *
+ * Copyright (C) 2021 Intel Corporation. All rights reserved.
+ */
+
+#define pr_fmt(fmt) "ACPI FPDT: " fmt
+
+#include <linux/acpi.h>
+
+/*
+ * FPDT contains ACPI table header and a number of fpdt_subtable_entries.
+ * Each fpdt_subtable_entry points to a subtable: FBPT or S3PT.
+ * Each FPDT subtable (FBPT/S3PT) is composed of a fpdt_subtable_header
+ * and a number of fpdt performance records.
+ * Each FPDT performance record is composed of a fpdt_record_header and
+ * performance data fields, for boot or suspend or resume phase.
+ */
+enum fpdt_subtable_type {
+	SUBTABLE_FBPT,
+	SUBTABLE_S3PT,
+};
+
+struct fpdt_subtable_entry {
+	u16 type;		/* refer to enum fpdt_subtable_type */
+	u8 length;
+	u8 revision;
+	u32 reserved;
+	u64 address;		/* physical address of the S3PT/FBPT table */
+};
+
+struct fpdt_subtable_header {
+	u32 signature;
+	u32 length;
+};
+
+enum fpdt_record_type {
+	RECORD_S3_RESUME,
+	RECORD_S3_SUSPEND,
+	RECORD_BOOT,
+};
+
+struct fpdt_record_header {
+	u16 type;		/* refer to enum fpdt_record_type */
+	u8 length;
+	u8 revision;
+};
+
+struct resume_performance_record {
+	struct fpdt_record_header header;
+	u32 resume_count;
+	u64 resume_prev;
+	u64 resume_avg;
+} __attribute__((packed));
+
+struct boot_performance_record {
+	struct fpdt_record_header header;
+	u32 reserved;
+	u64 firmware_start;
+	u64 bootloader_load;
+	u64 bootloader_launch;
+	u64 exitbootservice_start;
+	u64 exitbootservice_end;
+} __attribute__((packed));
+
+struct suspend_performance_record {
+	struct fpdt_record_header header;
+	u64 suspend_start;
+	u64 suspend_end;
+} __attribute__((packed));
+
+
+static struct resume_performance_record *record_resume;
+static struct suspend_performance_record *record_suspend;
+static struct boot_performance_record *record_boot;
+
+#define FPDT_ATTR(phase, name)	\
+static ssize_t name##_show(struct kobject *kobj,	\
+		 struct kobj_attribute *attr, char *buf)	\
+{	\
+	return sprintf(buf, "%llu\n", record_##phase->name);	\
+}	\
+static struct kobj_attribute name##_attr =	\
+__ATTR(name##_ns, 0444, name##_show, NULL)
+
+FPDT_ATTR(resume, resume_prev);
+FPDT_ATTR(resume, resume_avg);
+FPDT_ATTR(suspend, suspend_start);
+FPDT_ATTR(suspend, suspend_end);
+FPDT_ATTR(boot, firmware_start);
+FPDT_ATTR(boot, bootloader_load);
+FPDT_ATTR(boot, bootloader_launch);
+FPDT_ATTR(boot, exitbootservice_start);
+FPDT_ATTR(boot, exitbootservice_end);
+
+static ssize_t resume_count_show(struct kobject *kobj,
+				 struct kobj_attribute *attr, char *buf)
+{
+	return sprintf(buf, "%u\n", record_resume->resume_count);
+}
+
+static struct kobj_attribute resume_count_attr =
+__ATTR_RO(resume_count);
+
+static struct attribute *resume_attrs[] = {
+	&resume_count_attr.attr,
+	&resume_prev_attr.attr,
+	&resume_avg_attr.attr,
+	NULL
+};
+
+static const struct attribute_group resume_attr_group = {
+	.attrs = resume_attrs,
+	.name = "resume",
+};
+
+static struct attribute *suspend_attrs[] = {
+	&suspend_start_attr.attr,
+	&suspend_end_attr.attr,
+	NULL
+};
+
+static const struct attribute_group suspend_attr_group = {
+	.attrs = suspend_attrs,
+	.name = "suspend",
+};
+
+static struct attribute *boot_attrs[] = {
+	&firmware_start_attr.attr,
+	&bootloader_load_attr.attr,
+	&bootloader_launch_attr.attr,
+	&exitbootservice_start_attr.attr,
+	&exitbootservice_end_attr.attr,
+	NULL
+};
+
+static const struct attribute_group boot_attr_group = {
+	.attrs = boot_attrs,
+	.name = "boot",
+};
+
+static struct kobject *fpdt_kobj;
+
+#if defined CONFIG_X86 && defined CONFIG_PHYS_ADDR_T_64BIT
+#include <linux/processor.h>
+static bool fpdt_address_valid(u64 address)
+{
+	/*
+	 * On some systems the table contains invalid addresses
+	 * with unsuppored high address bits set, check for this.
+	 */
+	return !(address >> boot_cpu_data.x86_phys_bits);
+}
+#else
+static bool fpdt_address_valid(u64 address)
+{
+	return true;
+}
+#endif
+
+static int fpdt_process_subtable(u64 address, u32 subtable_type)
+{
+	struct fpdt_subtable_header *subtable_header;
+	struct fpdt_record_header *record_header;
+	char *signature = (subtable_type == SUBTABLE_FBPT ? "FBPT" : "S3PT");
+	u32 length, offset;
+	int result;
+
+	if (!fpdt_address_valid(address)) {
+		pr_info(FW_BUG "invalid physical address: 0x%llx!\n", address);
+		return -EINVAL;
+	}
+
+	subtable_header = acpi_os_map_memory(address, sizeof(*subtable_header));
+	if (!subtable_header)
+		return -ENOMEM;
+
+	if (strncmp((char *)&subtable_header->signature, signature, 4)) {
+		pr_info(FW_BUG "subtable signature and type mismatch!\n");
+		return -EINVAL;
+	}
+
+	length = subtable_header->length;
+	acpi_os_unmap_memory(subtable_header, sizeof(*subtable_header));
+
+	subtable_header = acpi_os_map_memory(address, length);
+	if (!subtable_header)
+		return -ENOMEM;
+
+	offset = sizeof(*subtable_header);
+	while (offset < length) {
+		record_header = (void *)subtable_header + offset;
+		offset += record_header->length;
+
+		if (!record_header->length) {
+			pr_err(FW_BUG "Zero-length record found in FPTD.\n");
+			result = -EINVAL;
+			goto err;
+		}
+
+		switch (record_header->type) {
+		case RECORD_S3_RESUME:
+			if (subtable_type != SUBTABLE_S3PT) {
+				pr_err(FW_BUG "Invalid record %d for subtable %s\n",
+				     record_header->type, signature);
+				result = -EINVAL;
+				goto err;
+			}
+			if (record_resume) {
+				pr_err("Duplicate resume performance record found.\n");
+				continue;
+			}
+			record_resume = (struct resume_performance_record *)record_header;
+			result = sysfs_create_group(fpdt_kobj, &resume_attr_group);
+			if (result)
+				goto err;
+			break;
+		case RECORD_S3_SUSPEND:
+			if (subtable_type != SUBTABLE_S3PT) {
+				pr_err(FW_BUG "Invalid %d for subtable %s\n",
+				     record_header->type, signature);
+				continue;
+			}
+			if (record_suspend) {
+				pr_err("Duplicate suspend performance record found.\n");
+				continue;
+			}
+			record_suspend = (struct suspend_performance_record *)record_header;
+			result = sysfs_create_group(fpdt_kobj, &suspend_attr_group);
+			if (result)
+				goto err;
+			break;
+		case RECORD_BOOT:
+			if (subtable_type != SUBTABLE_FBPT) {
+				pr_err(FW_BUG "Invalid %d for subtable %s\n",
+				     record_header->type, signature);
+				result = -EINVAL;
+				goto err;
+			}
+			if (record_boot) {
+				pr_err("Duplicate boot performance record found.\n");
+				continue;
+			}
+			record_boot = (struct boot_performance_record *)record_header;
+			result = sysfs_create_group(fpdt_kobj, &boot_attr_group);
+			if (result)
+				goto err;
+			break;
+
+		default:
+			/* Other types are reserved in ACPI 6.4 spec. */
+			break;
+		}
+	}
+	return 0;
+
+err:
+	if (record_boot)
+		sysfs_remove_group(fpdt_kobj, &boot_attr_group);
+
+	if (record_suspend)
+		sysfs_remove_group(fpdt_kobj, &suspend_attr_group);
+
+	if (record_resume)
+		sysfs_remove_group(fpdt_kobj, &resume_attr_group);
+
+	return result;
+}
+
+static int __init acpi_init_fpdt(void)
+{
+	acpi_status status;
+	struct acpi_table_header *header;
+	struct fpdt_subtable_entry *subtable;
+	u32 offset = sizeof(*header);
+	int result;
+
+	status = acpi_get_table(ACPI_SIG_FPDT, 0, &header);
+
+	if (ACPI_FAILURE(status))
+		return 0;
+
+	fpdt_kobj = kobject_create_and_add("fpdt", acpi_kobj);
+	if (!fpdt_kobj) {
+		result = -ENOMEM;
+		goto err_nomem;
+	}
+
+	while (offset < header->length) {
+		subtable = (void *)header + offset;
+		switch (subtable->type) {
+		case SUBTABLE_FBPT:
+		case SUBTABLE_S3PT:
+			result = fpdt_process_subtable(subtable->address,
+					      subtable->type);
+			if (result)
+				goto err_subtable;
+			break;
+		default:
+			/* Other types are reserved in ACPI 6.4 spec. */
+			break;
+		}
+		offset += sizeof(*subtable);
+	}
+	return 0;
+err_subtable:
+	kobject_put(fpdt_kobj);
+
+err_nomem:
+	acpi_put_table(header);
+	return result;
+}
+
+fs_initcall(acpi_init_fpdt);
diff --git a/drivers/acpi/acpi_ipmi.c b/drivers/acpi/acpi_ipmi.c
index 9d6c0fc120d7..5fba4dab5d08 100644
--- a/drivers/acpi/acpi_ipmi.c
+++ b/drivers/acpi/acpi_ipmi.c
@@ -22,6 +22,8 @@ MODULE_LICENSE("GPL");
 /* the IPMI timeout is 5s */
 #define IPMI_TIMEOUT			(5000)
 #define ACPI_IPMI_MAX_MSG_LENGTH	64
+/* 2s should be suffient for SMI being selected */
+#define ACPI_IPMI_SMI_SELECTION_TIMEOUT	(2 * HZ)
 
 struct acpi_ipmi_device {
 	/* the device list attached to driver_data.ipmi_devices */
@@ -54,6 +56,7 @@ struct ipmi_driver_data {
 	 * to this selected global IPMI system interface.
 	 */
 	struct acpi_ipmi_device *selected_smi;
+	struct completion smi_selection_done;
 };
 
 struct acpi_ipmi_msg {
@@ -353,29 +356,27 @@ static void ipmi_flush_tx_msg(struct acpi_ipmi_device *ipmi)
 static void ipmi_cancel_tx_msg(struct acpi_ipmi_device *ipmi,
 			       struct acpi_ipmi_msg *msg)
 {
-	struct acpi_ipmi_msg *tx_msg, *temp;
-	bool msg_found = false;
+	struct acpi_ipmi_msg *tx_msg = NULL, *iter, *temp;
 	unsigned long flags;
 
 	spin_lock_irqsave(&ipmi->tx_msg_lock, flags);
-	list_for_each_entry_safe(tx_msg, temp, &ipmi->tx_msg_list, head) {
-		if (msg == tx_msg) {
-			msg_found = true;
-			list_del(&tx_msg->head);
+	list_for_each_entry_safe(iter, temp, &ipmi->tx_msg_list, head) {
+		if (msg == iter) {
+			tx_msg = iter;
+			list_del(&iter->head);
 			break;
 		}
 	}
 	spin_unlock_irqrestore(&ipmi->tx_msg_lock, flags);
 
-	if (msg_found)
+	if (tx_msg)
 		acpi_ipmi_msg_put(tx_msg);
 }
 
 static void ipmi_msg_handler(struct ipmi_recv_msg *msg, void *user_msg_data)
 {
 	struct acpi_ipmi_device *ipmi_device = user_msg_data;
-	bool msg_found = false;
-	struct acpi_ipmi_msg *tx_msg, *temp;
+	struct acpi_ipmi_msg *tx_msg = NULL, *iter, *temp;
 	struct device *dev = ipmi_device->dev;
 	unsigned long flags;
 
@@ -387,16 +388,16 @@ static void ipmi_msg_handler(struct ipmi_recv_msg *msg, void *user_msg_data)
 	}
 
 	spin_lock_irqsave(&ipmi_device->tx_msg_lock, flags);
-	list_for_each_entry_safe(tx_msg, temp, &ipmi_device->tx_msg_list, head) {
-		if (msg->msgid == tx_msg->tx_msgid) {
-			msg_found = true;
-			list_del(&tx_msg->head);
+	list_for_each_entry_safe(iter, temp, &ipmi_device->tx_msg_list, head) {
+		if (msg->msgid == iter->tx_msgid) {
+			tx_msg = iter;
+			list_del(&iter->head);
 			break;
 		}
 	}
 	spin_unlock_irqrestore(&ipmi_device->tx_msg_lock, flags);
 
-	if (!msg_found) {
+	if (!tx_msg) {
 		dev_warn(dev,
 			 "Unexpected response (msg id %ld) is returned.\n",
 			 msg->msgid);
@@ -465,8 +466,10 @@ static void ipmi_register_bmc(int iface, struct device *dev)
 		if (temp->handle == handle)
 			goto err_lock;
 	}
-	if (!driver_data.selected_smi)
+	if (!driver_data.selected_smi) {
 		driver_data.selected_smi = ipmi_device;
+		complete(&driver_data.smi_selection_done);
+	}
 	list_add_tail(&ipmi_device->head, &driver_data.ipmi_devices);
 	mutex_unlock(&driver_data.ipmi_lock);
 
@@ -478,20 +481,18 @@ err_lock:
 	ipmi_dev_release(ipmi_device);
 err_ref:
 	put_device(smi_data.dev);
-	return;
 }
 
 static void ipmi_bmc_gone(int iface)
 {
-	struct acpi_ipmi_device *ipmi_device, *temp;
-	bool dev_found = false;
+	struct acpi_ipmi_device *ipmi_device = NULL, *iter, *temp;
 
 	mutex_lock(&driver_data.ipmi_lock);
-	list_for_each_entry_safe(ipmi_device, temp,
+	list_for_each_entry_safe(iter, temp,
 				 &driver_data.ipmi_devices, head) {
-		if (ipmi_device->ipmi_ifnum != iface) {
-			dev_found = true;
-			__ipmi_dev_kill(ipmi_device);
+		if (iter->ipmi_ifnum != iface) {
+			ipmi_device = iter;
+			__ipmi_dev_kill(iter);
 			break;
 		}
 	}
@@ -501,7 +502,7 @@ static void ipmi_bmc_gone(int iface)
 					struct acpi_ipmi_device, head);
 	mutex_unlock(&driver_data.ipmi_lock);
 
-	if (dev_found) {
+	if (ipmi_device) {
 		ipmi_flush_tx_msg(ipmi_device);
 		acpi_ipmi_dev_put(ipmi_device);
 	}
@@ -582,6 +583,20 @@ out_msg:
 	return status;
 }
 
+int acpi_wait_for_acpi_ipmi(void)
+{
+	long ret;
+
+	ret = wait_for_completion_interruptible_timeout(&driver_data.smi_selection_done,
+							ACPI_IPMI_SMI_SELECTION_TIMEOUT);
+
+	if (ret <= 0)
+		return -ETIMEDOUT;
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(acpi_wait_for_acpi_ipmi);
+
 static int __init acpi_ipmi_init(void)
 {
 	int result;
@@ -590,6 +605,8 @@ static int __init acpi_ipmi_init(void)
 	if (acpi_disabled)
 		return 0;
 
+	init_completion(&driver_data.smi_selection_done);
+
 	status = acpi_install_address_space_handler(ACPI_ROOT_OBJECT,
 						    ACPI_ADR_SPACE_IPMI,
 						    &acpi_ipmi_space_handler,
@@ -598,9 +615,14 @@ static int __init acpi_ipmi_init(void)
 		pr_warn("Can't register IPMI opregion space handle\n");
 		return -EINVAL;
 	}
+
 	result = ipmi_smi_watcher_register(&driver_data.bmc_events);
-	if (result)
+	if (result) {
+		acpi_remove_address_space_handler(ACPI_ROOT_OBJECT,
+										  ACPI_ADR_SPACE_IPMI,
+										  &acpi_ipmi_space_handler);
 		pr_err("Can't register IPMI system interface watcher\n");
+	}
 
 	return result;
 }
diff --git a/drivers/acpi/acpi_lpit.c b/drivers/acpi/acpi_lpit.c
index 953437a216f6..b8d98b1b48ae 100644
--- a/drivers/acpi/acpi_lpit.c
+++ b/drivers/acpi/acpi_lpit.c
@@ -10,6 +10,7 @@
 #include <linux/acpi.h>
 #include <asm/msr.h>
 #include <asm/tsc.h>
+#include "internal.h"
 
 struct lpit_residency_info {
 	struct acpi_generic_address gaddr;
@@ -38,7 +39,7 @@ static int lpit_read_residency_counter_us(u64 *counter, bool io_mem)
 		return 0;
 	}
 
-	err = rdmsrl_safe(residency_info_ffh.gaddr.address, counter);
+	err = rdmsrq_safe(residency_info_ffh.gaddr.address, counter);
 	if (!err) {
 		u64 mask = GENMASK_ULL(residency_info_ffh.gaddr.bit_offset +
 				       residency_info_ffh.gaddr. bit_width - 1,
@@ -97,8 +98,14 @@ EXPORT_SYMBOL_GPL(lpit_read_residency_count_address);
 static void lpit_update_residency(struct lpit_residency_info *info,
 				 struct acpi_lpit_native *lpit_native)
 {
+	struct device *dev_root = bus_get_dev_root(&cpu_subsys);
+
+	/* Silently fail, if cpuidle attribute group is not present */
+	if (!dev_root)
+		return;
+
 	info->frequency = lpit_native->counter_frequency ?
-				lpit_native->counter_frequency : tsc_khz * 1000;
+				lpit_native->counter_frequency : mul_u32_u32(tsc_khz, 1000U);
 	if (!info->frequency)
 		info->frequency = 1;
 
@@ -107,24 +114,18 @@ static void lpit_update_residency(struct lpit_residency_info *info,
 		info->iomem_addr = ioremap(info->gaddr.address,
 						   info->gaddr.bit_width / 8);
 		if (!info->iomem_addr)
-			return;
-
-		if (!(acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0))
-			return;
+			goto exit;
 
-		/* Silently fail, if cpuidle attribute group is not present */
-		sysfs_add_file_to_group(&cpu_subsys.dev_root->kobj,
+		sysfs_add_file_to_group(&dev_root->kobj,
 					&dev_attr_low_power_idle_system_residency_us.attr,
 					"cpuidle");
 	} else if (info->gaddr.space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) {
-		if (!(acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0))
-			return;
-
-		/* Silently fail, if cpuidle attribute group is not present */
-		sysfs_add_file_to_group(&cpu_subsys.dev_root->kobj,
+		sysfs_add_file_to_group(&dev_root->kobj,
 					&dev_attr_low_power_idle_cpu_residency_us.attr,
 					"cpuidle");
 	}
+exit:
+	put_device(dev_root);
 }
 
 static void lpit_process(u64 begin, u64 end)
@@ -151,10 +152,11 @@ void acpi_init_lpit(void)
 	struct acpi_table_lpit *lpit;
 
 	status = acpi_get_table(ACPI_SIG_LPIT, 0, (struct acpi_table_header **)&lpit);
-
 	if (ACPI_FAILURE(status))
 		return;
 
 	lpit_process((u64)lpit + sizeof(*lpit),
 		     (u64)lpit + lpit->header.length);
+
+	acpi_put_table((struct acpi_table_header *)lpit);
 }
diff --git a/drivers/acpi/acpi_lpss.c b/drivers/acpi/acpi_lpss.c
deleted file mode 100644
index dee999938213..000000000000
--- a/drivers/acpi/acpi_lpss.c
+++ /dev/null
@@ -1,1350 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * ACPI support for Intel Lynxpoint LPSS.
- *
- * Copyright (C) 2013, Intel Corporation
- * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
- *          Rafael J. Wysocki <rafael.j.wysocki@intel.com>
- */
-
-#include <linux/acpi.h>
-#include <linux/clkdev.h>
-#include <linux/clk-provider.h>
-#include <linux/dmi.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/mutex.h>
-#include <linux/pci.h>
-#include <linux/platform_device.h>
-#include <linux/platform_data/x86/clk-lpss.h>
-#include <linux/platform_data/x86/pmc_atom.h>
-#include <linux/pm_domain.h>
-#include <linux/pm_runtime.h>
-#include <linux/pwm.h>
-#include <linux/suspend.h>
-#include <linux/delay.h>
-
-#include "internal.h"
-
-ACPI_MODULE_NAME("acpi_lpss");
-
-#ifdef CONFIG_X86_INTEL_LPSS
-
-#include <asm/cpu_device_id.h>
-#include <asm/intel-family.h>
-#include <asm/iosf_mbi.h>
-
-#define LPSS_ADDR(desc) ((unsigned long)&desc)
-
-#define LPSS_CLK_SIZE	0x04
-#define LPSS_LTR_SIZE	0x18
-
-/* Offsets relative to LPSS_PRIVATE_OFFSET */
-#define LPSS_CLK_DIVIDER_DEF_MASK	(BIT(1) | BIT(16))
-#define LPSS_RESETS			0x04
-#define LPSS_RESETS_RESET_FUNC		BIT(0)
-#define LPSS_RESETS_RESET_APB		BIT(1)
-#define LPSS_GENERAL			0x08
-#define LPSS_GENERAL_LTR_MODE_SW	BIT(2)
-#define LPSS_GENERAL_UART_RTS_OVRD	BIT(3)
-#define LPSS_SW_LTR			0x10
-#define LPSS_AUTO_LTR			0x14
-#define LPSS_LTR_SNOOP_REQ		BIT(15)
-#define LPSS_LTR_SNOOP_MASK		0x0000FFFF
-#define LPSS_LTR_SNOOP_LAT_1US		0x800
-#define LPSS_LTR_SNOOP_LAT_32US		0xC00
-#define LPSS_LTR_SNOOP_LAT_SHIFT	5
-#define LPSS_LTR_SNOOP_LAT_CUTOFF	3000
-#define LPSS_LTR_MAX_VAL		0x3FF
-#define LPSS_TX_INT			0x20
-#define LPSS_TX_INT_MASK		BIT(1)
-
-#define LPSS_PRV_REG_COUNT		9
-
-/* LPSS Flags */
-#define LPSS_CLK			BIT(0)
-#define LPSS_CLK_GATE			BIT(1)
-#define LPSS_CLK_DIVIDER		BIT(2)
-#define LPSS_LTR			BIT(3)
-#define LPSS_SAVE_CTX			BIT(4)
-#define LPSS_NO_D3_DELAY		BIT(5)
-
-struct lpss_private_data;
-
-struct lpss_device_desc {
-	unsigned int flags;
-	const char *clk_con_id;
-	unsigned int prv_offset;
-	size_t prv_size_override;
-	struct property_entry *properties;
-	void (*setup)(struct lpss_private_data *pdata);
-	bool resume_from_noirq;
-};
-
-static const struct lpss_device_desc lpss_dma_desc = {
-	.flags = LPSS_CLK,
-};
-
-struct lpss_private_data {
-	struct acpi_device *adev;
-	void __iomem *mmio_base;
-	resource_size_t mmio_size;
-	unsigned int fixed_clk_rate;
-	struct clk *clk;
-	const struct lpss_device_desc *dev_desc;
-	u32 prv_reg_ctx[LPSS_PRV_REG_COUNT];
-};
-
-/* Devices which need to be in D3 before lpss_iosf_enter_d3_state() proceeds */
-static u32 pmc_atom_d3_mask = 0xfe000ffe;
-
-/* LPSS run time quirks */
-static unsigned int lpss_quirks;
-
-/*
- * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device.
- *
- * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover
- * it can be powered off automatically whenever the last LPSS device goes down.
- * In case of no power any access to the DMA controller will hang the system.
- * The behaviour is reproduced on some HP laptops based on Intel BayTrail as
- * well as on ASuS T100TA transformer.
- *
- * This quirk overrides power state of entire LPSS island to keep DMA powered
- * on whenever we have at least one other device in use.
- */
-#define LPSS_QUIRK_ALWAYS_POWER_ON	BIT(0)
-
-/* UART Component Parameter Register */
-#define LPSS_UART_CPR			0xF4
-#define LPSS_UART_CPR_AFCE		BIT(4)
-
-static void lpss_uart_setup(struct lpss_private_data *pdata)
-{
-	unsigned int offset;
-	u32 val;
-
-	offset = pdata->dev_desc->prv_offset + LPSS_TX_INT;
-	val = readl(pdata->mmio_base + offset);
-	writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset);
-
-	val = readl(pdata->mmio_base + LPSS_UART_CPR);
-	if (!(val & LPSS_UART_CPR_AFCE)) {
-		offset = pdata->dev_desc->prv_offset + LPSS_GENERAL;
-		val = readl(pdata->mmio_base + offset);
-		val |= LPSS_GENERAL_UART_RTS_OVRD;
-		writel(val, pdata->mmio_base + offset);
-	}
-}
-
-static void lpss_deassert_reset(struct lpss_private_data *pdata)
-{
-	unsigned int offset;
-	u32 val;
-
-	offset = pdata->dev_desc->prv_offset + LPSS_RESETS;
-	val = readl(pdata->mmio_base + offset);
-	val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC;
-	writel(val, pdata->mmio_base + offset);
-}
-
-/*
- * BYT PWM used for backlight control by the i915 driver on systems without
- * the Crystal Cove PMIC.
- */
-static struct pwm_lookup byt_pwm_lookup[] = {
-	PWM_LOOKUP_WITH_MODULE("80860F09:00", 0, "0000:00:02.0",
-			       "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL,
-			       "pwm-lpss-platform"),
-};
-
-static void byt_pwm_setup(struct lpss_private_data *pdata)
-{
-	struct acpi_device *adev = pdata->adev;
-
-	/* Only call pwm_add_table for the first PWM controller */
-	if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1"))
-		return;
-
-	pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup));
-}
-
-#define LPSS_I2C_ENABLE			0x6c
-
-static void byt_i2c_setup(struct lpss_private_data *pdata)
-{
-	const char *uid_str = acpi_device_uid(pdata->adev);
-	acpi_handle handle = pdata->adev->handle;
-	unsigned long long shared_host = 0;
-	acpi_status status;
-	long uid = 0;
-
-	/* Expected to always be true, but better safe then sorry */
-	if (uid_str)
-		uid = simple_strtol(uid_str, NULL, 10);
-
-	/* Detect I2C bus shared with PUNIT and ignore its d3 status */
-	status = acpi_evaluate_integer(handle, "_SEM", NULL, &shared_host);
-	if (ACPI_SUCCESS(status) && shared_host && uid)
-		pmc_atom_d3_mask &= ~(BIT_LPSS2_F1_I2C1 << (uid - 1));
-
-	lpss_deassert_reset(pdata);
-
-	if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset))
-		pdata->fixed_clk_rate = 133000000;
-
-	writel(0, pdata->mmio_base + LPSS_I2C_ENABLE);
-}
-
-/* BSW PWM used for backlight control by the i915 driver */
-static struct pwm_lookup bsw_pwm_lookup[] = {
-	PWM_LOOKUP_WITH_MODULE("80862288:00", 0, "0000:00:02.0",
-			       "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL,
-			       "pwm-lpss-platform"),
-};
-
-static void bsw_pwm_setup(struct lpss_private_data *pdata)
-{
-	struct acpi_device *adev = pdata->adev;
-
-	/* Only call pwm_add_table for the first PWM controller */
-	if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1"))
-		return;
-
-	pwm_add_table(bsw_pwm_lookup, ARRAY_SIZE(bsw_pwm_lookup));
-}
-
-static const struct lpss_device_desc lpt_dev_desc = {
-	.flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR
-			| LPSS_SAVE_CTX,
-	.prv_offset = 0x800,
-};
-
-static const struct lpss_device_desc lpt_i2c_dev_desc = {
-	.flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR | LPSS_SAVE_CTX,
-	.prv_offset = 0x800,
-};
-
-static struct property_entry uart_properties[] = {
-	PROPERTY_ENTRY_U32("reg-io-width", 4),
-	PROPERTY_ENTRY_U32("reg-shift", 2),
-	PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"),
-	{ },
-};
-
-static const struct lpss_device_desc lpt_uart_dev_desc = {
-	.flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR
-			| LPSS_SAVE_CTX,
-	.clk_con_id = "baudclk",
-	.prv_offset = 0x800,
-	.setup = lpss_uart_setup,
-	.properties = uart_properties,
-};
-
-static const struct lpss_device_desc lpt_sdio_dev_desc = {
-	.flags = LPSS_LTR,
-	.prv_offset = 0x1000,
-	.prv_size_override = 0x1018,
-};
-
-static const struct lpss_device_desc byt_pwm_dev_desc = {
-	.flags = LPSS_SAVE_CTX,
-	.prv_offset = 0x800,
-	.setup = byt_pwm_setup,
-};
-
-static const struct lpss_device_desc bsw_pwm_dev_desc = {
-	.flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
-	.prv_offset = 0x800,
-	.setup = bsw_pwm_setup,
-};
-
-static const struct lpss_device_desc byt_uart_dev_desc = {
-	.flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
-	.clk_con_id = "baudclk",
-	.prv_offset = 0x800,
-	.setup = lpss_uart_setup,
-	.properties = uart_properties,
-};
-
-static const struct lpss_device_desc bsw_uart_dev_desc = {
-	.flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
-			| LPSS_NO_D3_DELAY,
-	.clk_con_id = "baudclk",
-	.prv_offset = 0x800,
-	.setup = lpss_uart_setup,
-	.properties = uart_properties,
-};
-
-static const struct lpss_device_desc byt_spi_dev_desc = {
-	.flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
-	.prv_offset = 0x400,
-};
-
-static const struct lpss_device_desc byt_sdio_dev_desc = {
-	.flags = LPSS_CLK,
-};
-
-static const struct lpss_device_desc byt_i2c_dev_desc = {
-	.flags = LPSS_CLK | LPSS_SAVE_CTX,
-	.prv_offset = 0x800,
-	.setup = byt_i2c_setup,
-	.resume_from_noirq = true,
-};
-
-static const struct lpss_device_desc bsw_i2c_dev_desc = {
-	.flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
-	.prv_offset = 0x800,
-	.setup = byt_i2c_setup,
-	.resume_from_noirq = true,
-};
-
-static const struct lpss_device_desc bsw_spi_dev_desc = {
-	.flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
-			| LPSS_NO_D3_DELAY,
-	.prv_offset = 0x400,
-	.setup = lpss_deassert_reset,
-};
-
-static const struct x86_cpu_id lpss_cpu_ids[] = {
-	X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT,	NULL),
-	X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT,	NULL),
-	{}
-};
-
-#else
-
-#define LPSS_ADDR(desc) (0UL)
-
-#endif /* CONFIG_X86_INTEL_LPSS */
-
-static const struct acpi_device_id acpi_lpss_device_ids[] = {
-	/* Generic LPSS devices */
-	{ "INTL9C60", LPSS_ADDR(lpss_dma_desc) },
-
-	/* Lynxpoint LPSS devices */
-	{ "INT33C0", LPSS_ADDR(lpt_dev_desc) },
-	{ "INT33C1", LPSS_ADDR(lpt_dev_desc) },
-	{ "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) },
-	{ "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) },
-	{ "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) },
-	{ "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) },
-	{ "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) },
-	{ "INT33C7", },
-
-	/* BayTrail LPSS devices */
-	{ "80860F09", LPSS_ADDR(byt_pwm_dev_desc) },
-	{ "80860F0A", LPSS_ADDR(byt_uart_dev_desc) },
-	{ "80860F0E", LPSS_ADDR(byt_spi_dev_desc) },
-	{ "80860F14", LPSS_ADDR(byt_sdio_dev_desc) },
-	{ "80860F41", LPSS_ADDR(byt_i2c_dev_desc) },
-	{ "INT33B2", },
-	{ "INT33FC", },
-
-	/* Braswell LPSS devices */
-	{ "80862286", LPSS_ADDR(lpss_dma_desc) },
-	{ "80862288", LPSS_ADDR(bsw_pwm_dev_desc) },
-	{ "8086228A", LPSS_ADDR(bsw_uart_dev_desc) },
-	{ "8086228E", LPSS_ADDR(bsw_spi_dev_desc) },
-	{ "808622C0", LPSS_ADDR(lpss_dma_desc) },
-	{ "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) },
-
-	/* Broadwell LPSS devices */
-	{ "INT3430", LPSS_ADDR(lpt_dev_desc) },
-	{ "INT3431", LPSS_ADDR(lpt_dev_desc) },
-	{ "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) },
-	{ "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) },
-	{ "INT3434", LPSS_ADDR(lpt_uart_dev_desc) },
-	{ "INT3435", LPSS_ADDR(lpt_uart_dev_desc) },
-	{ "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) },
-	{ "INT3437", },
-
-	/* Wildcat Point LPSS devices */
-	{ "INT3438", LPSS_ADDR(lpt_dev_desc) },
-
-	{ }
-};
-
-#ifdef CONFIG_X86_INTEL_LPSS
-
-static int is_memory(struct acpi_resource *res, void *not_used)
-{
-	struct resource r;
-	return !acpi_dev_resource_memory(res, &r);
-}
-
-/* LPSS main clock device. */
-static struct platform_device *lpss_clk_dev;
-
-static inline void lpt_register_clock_device(void)
-{
-	lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0);
-}
-
-static int register_device_clock(struct acpi_device *adev,
-				 struct lpss_private_data *pdata)
-{
-	const struct lpss_device_desc *dev_desc = pdata->dev_desc;
-	const char *devname = dev_name(&adev->dev);
-	struct clk *clk;
-	struct lpss_clk_data *clk_data;
-	const char *parent, *clk_name;
-	void __iomem *prv_base;
-
-	if (!lpss_clk_dev)
-		lpt_register_clock_device();
-
-	clk_data = platform_get_drvdata(lpss_clk_dev);
-	if (!clk_data)
-		return -ENODEV;
-	clk = clk_data->clk;
-
-	if (!pdata->mmio_base
-	    || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE)
-		return -ENODATA;
-
-	parent = clk_data->name;
-	prv_base = pdata->mmio_base + dev_desc->prv_offset;
-
-	if (pdata->fixed_clk_rate) {
-		clk = clk_register_fixed_rate(NULL, devname, parent, 0,
-					      pdata->fixed_clk_rate);
-		goto out;
-	}
-
-	if (dev_desc->flags & LPSS_CLK_GATE) {
-		clk = clk_register_gate(NULL, devname, parent, 0,
-					prv_base, 0, 0, NULL);
-		parent = devname;
-	}
-
-	if (dev_desc->flags & LPSS_CLK_DIVIDER) {
-		/* Prevent division by zero */
-		if (!readl(prv_base))
-			writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base);
-
-		clk_name = kasprintf(GFP_KERNEL, "%s-div", devname);
-		if (!clk_name)
-			return -ENOMEM;
-		clk = clk_register_fractional_divider(NULL, clk_name, parent,
-						      0, prv_base,
-						      1, 15, 16, 15, 0, NULL);
-		parent = clk_name;
-
-		clk_name = kasprintf(GFP_KERNEL, "%s-update", devname);
-		if (!clk_name) {
-			kfree(parent);
-			return -ENOMEM;
-		}
-		clk = clk_register_gate(NULL, clk_name, parent,
-					CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
-					prv_base, 31, 0, NULL);
-		kfree(parent);
-		kfree(clk_name);
-	}
-out:
-	if (IS_ERR(clk))
-		return PTR_ERR(clk);
-
-	pdata->clk = clk;
-	clk_register_clkdev(clk, dev_desc->clk_con_id, devname);
-	return 0;
-}
-
-struct lpss_device_links {
-	const char *supplier_hid;
-	const char *supplier_uid;
-	const char *consumer_hid;
-	const char *consumer_uid;
-	u32 flags;
-	const struct dmi_system_id *dep_missing_ids;
-};
-
-/* Please keep this list sorted alphabetically by vendor and model */
-static const struct dmi_system_id i2c1_dep_missing_dmi_ids[] = {
-	{
-		.matches = {
-			DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
-			DMI_MATCH(DMI_PRODUCT_NAME, "T200TA"),
-		},
-	},
-	{}
-};
-
-/*
- * The _DEP method is used to identify dependencies but instead of creating
- * device links for every handle in _DEP, only links in the following list are
- * created. That is necessary because, in the general case, _DEP can refer to
- * devices that might not have drivers, or that are on different buses, or where
- * the supplier is not enumerated until after the consumer is probed.
- */
-static const struct lpss_device_links lpss_device_links[] = {
-	/* CHT External sdcard slot controller depends on PMIC I2C ctrl */
-	{"808622C1", "7", "80860F14", "3", DL_FLAG_PM_RUNTIME},
-	/* CHT iGPU depends on PMIC I2C controller */
-	{"808622C1", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME},
-	/* BYT iGPU depends on the Embedded Controller I2C controller (UID 1) */
-	{"80860F41", "1", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME,
-	 i2c1_dep_missing_dmi_ids},
-	/* BYT CR iGPU depends on PMIC I2C controller (UID 5 on CR) */
-	{"80860F41", "5", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME},
-	/* BYT iGPU depends on PMIC I2C controller (UID 7 on non CR) */
-	{"80860F41", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME},
-};
-
-static bool acpi_lpss_is_supplier(struct acpi_device *adev,
-				  const struct lpss_device_links *link)
-{
-	return acpi_dev_hid_uid_match(adev, link->supplier_hid, link->supplier_uid);
-}
-
-static bool acpi_lpss_is_consumer(struct acpi_device *adev,
-				  const struct lpss_device_links *link)
-{
-	return acpi_dev_hid_uid_match(adev, link->consumer_hid, link->consumer_uid);
-}
-
-struct hid_uid {
-	const char *hid;
-	const char *uid;
-};
-
-static int match_hid_uid(struct device *dev, const void *data)
-{
-	struct acpi_device *adev = ACPI_COMPANION(dev);
-	const struct hid_uid *id = data;
-
-	if (!adev)
-		return 0;
-
-	return acpi_dev_hid_uid_match(adev, id->hid, id->uid);
-}
-
-static struct device *acpi_lpss_find_device(const char *hid, const char *uid)
-{
-	struct device *dev;
-
-	struct hid_uid data = {
-		.hid = hid,
-		.uid = uid,
-	};
-
-	dev = bus_find_device(&platform_bus_type, NULL, &data, match_hid_uid);
-	if (dev)
-		return dev;
-
-	return bus_find_device(&pci_bus_type, NULL, &data, match_hid_uid);
-}
-
-static bool acpi_lpss_dep(struct acpi_device *adev, acpi_handle handle)
-{
-	struct acpi_handle_list dep_devices;
-	acpi_status status;
-	int i;
-
-	if (!acpi_has_method(adev->handle, "_DEP"))
-		return false;
-
-	status = acpi_evaluate_reference(adev->handle, "_DEP", NULL,
-					 &dep_devices);
-	if (ACPI_FAILURE(status)) {
-		dev_dbg(&adev->dev, "Failed to evaluate _DEP.\n");
-		return false;
-	}
-
-	for (i = 0; i < dep_devices.count; i++) {
-		if (dep_devices.handles[i] == handle)
-			return true;
-	}
-
-	return false;
-}
-
-static void acpi_lpss_link_consumer(struct device *dev1,
-				    const struct lpss_device_links *link)
-{
-	struct device *dev2;
-
-	dev2 = acpi_lpss_find_device(link->consumer_hid, link->consumer_uid);
-	if (!dev2)
-		return;
-
-	if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids))
-	    || acpi_lpss_dep(ACPI_COMPANION(dev2), ACPI_HANDLE(dev1)))
-		device_link_add(dev2, dev1, link->flags);
-
-	put_device(dev2);
-}
-
-static void acpi_lpss_link_supplier(struct device *dev1,
-				    const struct lpss_device_links *link)
-{
-	struct device *dev2;
-
-	dev2 = acpi_lpss_find_device(link->supplier_hid, link->supplier_uid);
-	if (!dev2)
-		return;
-
-	if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids))
-	    || acpi_lpss_dep(ACPI_COMPANION(dev1), ACPI_HANDLE(dev2)))
-		device_link_add(dev1, dev2, link->flags);
-
-	put_device(dev2);
-}
-
-static void acpi_lpss_create_device_links(struct acpi_device *adev,
-					  struct platform_device *pdev)
-{
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(lpss_device_links); i++) {
-		const struct lpss_device_links *link = &lpss_device_links[i];
-
-		if (acpi_lpss_is_supplier(adev, link))
-			acpi_lpss_link_consumer(&pdev->dev, link);
-
-		if (acpi_lpss_is_consumer(adev, link))
-			acpi_lpss_link_supplier(&pdev->dev, link);
-	}
-}
-
-static int acpi_lpss_create_device(struct acpi_device *adev,
-				   const struct acpi_device_id *id)
-{
-	const struct lpss_device_desc *dev_desc;
-	struct lpss_private_data *pdata;
-	struct resource_entry *rentry;
-	struct list_head resource_list;
-	struct platform_device *pdev;
-	int ret;
-
-	dev_desc = (const struct lpss_device_desc *)id->driver_data;
-	if (!dev_desc) {
-		pdev = acpi_create_platform_device(adev, NULL);
-		return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1;
-	}
-	pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
-	if (!pdata)
-		return -ENOMEM;
-
-	INIT_LIST_HEAD(&resource_list);
-	ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL);
-	if (ret < 0)
-		goto err_out;
-
-	list_for_each_entry(rentry, &resource_list, node)
-		if (resource_type(rentry->res) == IORESOURCE_MEM) {
-			if (dev_desc->prv_size_override)
-				pdata->mmio_size = dev_desc->prv_size_override;
-			else
-				pdata->mmio_size = resource_size(rentry->res);
-			pdata->mmio_base = ioremap(rentry->res->start,
-						   pdata->mmio_size);
-			break;
-		}
-
-	acpi_dev_free_resource_list(&resource_list);
-
-	if (!pdata->mmio_base) {
-		/* Avoid acpi_bus_attach() instantiating a pdev for this dev. */
-		adev->pnp.type.platform_id = 0;
-		/* Skip the device, but continue the namespace scan. */
-		ret = 0;
-		goto err_out;
-	}
-
-	pdata->adev = adev;
-	pdata->dev_desc = dev_desc;
-
-	if (dev_desc->setup)
-		dev_desc->setup(pdata);
-
-	if (dev_desc->flags & LPSS_CLK) {
-		ret = register_device_clock(adev, pdata);
-		if (ret) {
-			/* Skip the device, but continue the namespace scan. */
-			ret = 0;
-			goto err_out;
-		}
-	}
-
-	/*
-	 * This works around a known issue in ACPI tables where LPSS devices
-	 * have _PS0 and _PS3 without _PSC (and no power resources), so
-	 * acpi_bus_init_power() will assume that the BIOS has put them into D0.
-	 */
-	acpi_device_fix_up_power(adev);
-
-	adev->driver_data = pdata;
-	pdev = acpi_create_platform_device(adev, dev_desc->properties);
-	if (!IS_ERR_OR_NULL(pdev)) {
-		acpi_lpss_create_device_links(adev, pdev);
-		return 1;
-	}
-
-	ret = PTR_ERR(pdev);
-	adev->driver_data = NULL;
-
- err_out:
-	kfree(pdata);
-	return ret;
-}
-
-static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg)
-{
-	return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
-}
-
-static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata,
-			     unsigned int reg)
-{
-	writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
-}
-
-static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val)
-{
-	struct acpi_device *adev;
-	struct lpss_private_data *pdata;
-	unsigned long flags;
-	int ret;
-
-	ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev);
-	if (WARN_ON(ret))
-		return ret;
-
-	spin_lock_irqsave(&dev->power.lock, flags);
-	if (pm_runtime_suspended(dev)) {
-		ret = -EAGAIN;
-		goto out;
-	}
-	pdata = acpi_driver_data(adev);
-	if (WARN_ON(!pdata || !pdata->mmio_base)) {
-		ret = -ENODEV;
-		goto out;
-	}
-	*val = __lpss_reg_read(pdata, reg);
-
- out:
-	spin_unlock_irqrestore(&dev->power.lock, flags);
-	return ret;
-}
-
-static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr,
-			     char *buf)
-{
-	u32 ltr_value = 0;
-	unsigned int reg;
-	int ret;
-
-	reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR;
-	ret = lpss_reg_read(dev, reg, &ltr_value);
-	if (ret)
-		return ret;
-
-	return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value);
-}
-
-static ssize_t lpss_ltr_mode_show(struct device *dev,
-				  struct device_attribute *attr, char *buf)
-{
-	u32 ltr_mode = 0;
-	char *outstr;
-	int ret;
-
-	ret = lpss_reg_read(dev, LPSS_GENERAL, &ltr_mode);
-	if (ret)
-		return ret;
-
-	outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto";
-	return sprintf(buf, "%s\n", outstr);
-}
-
-static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL);
-static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL);
-static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL);
-
-static struct attribute *lpss_attrs[] = {
-	&dev_attr_auto_ltr.attr,
-	&dev_attr_sw_ltr.attr,
-	&dev_attr_ltr_mode.attr,
-	NULL,
-};
-
-static const struct attribute_group lpss_attr_group = {
-	.attrs = lpss_attrs,
-	.name = "lpss_ltr",
-};
-
-static void acpi_lpss_set_ltr(struct device *dev, s32 val)
-{
-	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
-	u32 ltr_mode, ltr_val;
-
-	ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL);
-	if (val < 0) {
-		if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) {
-			ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW;
-			__lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
-		}
-		return;
-	}
-	ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK;
-	if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) {
-		ltr_val |= LPSS_LTR_SNOOP_LAT_32US;
-		val = LPSS_LTR_MAX_VAL;
-	} else if (val > LPSS_LTR_MAX_VAL) {
-		ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ;
-		val >>= LPSS_LTR_SNOOP_LAT_SHIFT;
-	} else {
-		ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ;
-	}
-	ltr_val |= val;
-	__lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR);
-	if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) {
-		ltr_mode |= LPSS_GENERAL_LTR_MODE_SW;
-		__lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
-	}
-}
-
-#ifdef CONFIG_PM
-/**
- * acpi_lpss_save_ctx() - Save the private registers of LPSS device
- * @dev: LPSS device
- * @pdata: pointer to the private data of the LPSS device
- *
- * Most LPSS devices have private registers which may loose their context when
- * the device is powered down. acpi_lpss_save_ctx() saves those registers into
- * prv_reg_ctx array.
- */
-static void acpi_lpss_save_ctx(struct device *dev,
-			       struct lpss_private_data *pdata)
-{
-	unsigned int i;
-
-	for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
-		unsigned long offset = i * sizeof(u32);
-
-		pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset);
-		dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n",
-			pdata->prv_reg_ctx[i], offset);
-	}
-}
-
-/**
- * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device
- * @dev: LPSS device
- * @pdata: pointer to the private data of the LPSS device
- *
- * Restores the registers that were previously stored with acpi_lpss_save_ctx().
- */
-static void acpi_lpss_restore_ctx(struct device *dev,
-				  struct lpss_private_data *pdata)
-{
-	unsigned int i;
-
-	for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
-		unsigned long offset = i * sizeof(u32);
-
-		__lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset);
-		dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n",
-			pdata->prv_reg_ctx[i], offset);
-	}
-}
-
-static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data *pdata)
-{
-	/*
-	 * The following delay is needed or the subsequent write operations may
-	 * fail. The LPSS devices are actually PCI devices and the PCI spec
-	 * expects 10ms delay before the device can be accessed after D3 to D0
-	 * transition. However some platforms like BSW does not need this delay.
-	 */
-	unsigned int delay = 10;	/* default 10ms delay */
-
-	if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY)
-		delay = 0;
-
-	msleep(delay);
-}
-
-static int acpi_lpss_activate(struct device *dev)
-{
-	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
-	int ret;
-
-	ret = acpi_dev_resume(dev);
-	if (ret)
-		return ret;
-
-	acpi_lpss_d3_to_d0_delay(pdata);
-
-	/*
-	 * This is called only on ->probe() stage where a device is either in
-	 * known state defined by BIOS or most likely powered off. Due to this
-	 * we have to deassert reset line to be sure that ->probe() will
-	 * recognize the device.
-	 */
-	if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
-		lpss_deassert_reset(pdata);
-
-	return 0;
-}
-
-static void acpi_lpss_dismiss(struct device *dev)
-{
-	acpi_dev_suspend(dev, false);
-}
-
-/* IOSF SB for LPSS island */
-#define LPSS_IOSF_UNIT_LPIOEP		0xA0
-#define LPSS_IOSF_UNIT_LPIO1		0xAB
-#define LPSS_IOSF_UNIT_LPIO2		0xAC
-
-#define LPSS_IOSF_PMCSR			0x84
-#define LPSS_PMCSR_D0			0
-#define LPSS_PMCSR_D3hot		3
-#define LPSS_PMCSR_Dx_MASK		GENMASK(1, 0)
-
-#define LPSS_IOSF_GPIODEF0		0x154
-#define LPSS_GPIODEF0_DMA1_D3		BIT(2)
-#define LPSS_GPIODEF0_DMA2_D3		BIT(3)
-#define LPSS_GPIODEF0_DMA_D3_MASK	GENMASK(3, 2)
-#define LPSS_GPIODEF0_DMA_LLP		BIT(13)
-
-static DEFINE_MUTEX(lpss_iosf_mutex);
-static bool lpss_iosf_d3_entered = true;
-
-static void lpss_iosf_enter_d3_state(void)
-{
-	u32 value1 = 0;
-	u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;
-	u32 value2 = LPSS_PMCSR_D3hot;
-	u32 mask2 = LPSS_PMCSR_Dx_MASK;
-	/*
-	 * PMC provides an information about actual status of the LPSS devices.
-	 * Here we read the values related to LPSS power island, i.e. LPSS
-	 * devices, excluding both LPSS DMA controllers, along with SCC domain.
-	 */
-	u32 func_dis, d3_sts_0, pmc_status;
-	int ret;
-
-	ret = pmc_atom_read(PMC_FUNC_DIS, &func_dis);
-	if (ret)
-		return;
-
-	mutex_lock(&lpss_iosf_mutex);
-
-	ret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0);
-	if (ret)
-		goto exit;
-
-	/*
-	 * Get the status of entire LPSS power island per device basis.
-	 * Shutdown both LPSS DMA controllers if and only if all other devices
-	 * are already in D3hot.
-	 */
-	pmc_status = (~(d3_sts_0 | func_dis)) & pmc_atom_d3_mask;
-	if (pmc_status)
-		goto exit;
-
-	iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,
-			LPSS_IOSF_PMCSR, value2, mask2);
-
-	iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,
-			LPSS_IOSF_PMCSR, value2, mask2);
-
-	iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,
-			LPSS_IOSF_GPIODEF0, value1, mask1);
-
-	lpss_iosf_d3_entered = true;
-
-exit:
-	mutex_unlock(&lpss_iosf_mutex);
-}
-
-static void lpss_iosf_exit_d3_state(void)
-{
-	u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 |
-		     LPSS_GPIODEF0_DMA_LLP;
-	u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;
-	u32 value2 = LPSS_PMCSR_D0;
-	u32 mask2 = LPSS_PMCSR_Dx_MASK;
-
-	mutex_lock(&lpss_iosf_mutex);
-
-	if (!lpss_iosf_d3_entered)
-		goto exit;
-
-	lpss_iosf_d3_entered = false;
-
-	iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,
-			LPSS_IOSF_GPIODEF0, value1, mask1);
-
-	iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,
-			LPSS_IOSF_PMCSR, value2, mask2);
-
-	iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,
-			LPSS_IOSF_PMCSR, value2, mask2);
-
-exit:
-	mutex_unlock(&lpss_iosf_mutex);
-}
-
-static int acpi_lpss_suspend(struct device *dev, bool wakeup)
-{
-	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
-	int ret;
-
-	if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
-		acpi_lpss_save_ctx(dev, pdata);
-
-	ret = acpi_dev_suspend(dev, wakeup);
-
-	/*
-	 * This call must be last in the sequence, otherwise PMC will return
-	 * wrong status for devices being about to be powered off. See
-	 * lpss_iosf_enter_d3_state() for further information.
-	 */
-	if (acpi_target_system_state() == ACPI_STATE_S0 &&
-	    lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available())
-		lpss_iosf_enter_d3_state();
-
-	return ret;
-}
-
-static int acpi_lpss_resume(struct device *dev)
-{
-	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
-	int ret;
-
-	/*
-	 * This call is kept first to be in symmetry with
-	 * acpi_lpss_runtime_suspend() one.
-	 */
-	if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available())
-		lpss_iosf_exit_d3_state();
-
-	ret = acpi_dev_resume(dev);
-	if (ret)
-		return ret;
-
-	acpi_lpss_d3_to_d0_delay(pdata);
-
-	if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
-		acpi_lpss_restore_ctx(dev, pdata);
-
-	return 0;
-}
-
-#ifdef CONFIG_PM_SLEEP
-static int acpi_lpss_do_suspend_late(struct device *dev)
-{
-	int ret;
-
-	if (dev_pm_smart_suspend_and_suspended(dev))
-		return 0;
-
-	ret = pm_generic_suspend_late(dev);
-	return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev));
-}
-
-static int acpi_lpss_suspend_late(struct device *dev)
-{
-	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
-
-	if (pdata->dev_desc->resume_from_noirq)
-		return 0;
-
-	return acpi_lpss_do_suspend_late(dev);
-}
-
-static int acpi_lpss_suspend_noirq(struct device *dev)
-{
-	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
-	int ret;
-
-	if (pdata->dev_desc->resume_from_noirq) {
-		/*
-		 * The driver's ->suspend_late callback will be invoked by
-		 * acpi_lpss_do_suspend_late(), with the assumption that the
-		 * driver really wanted to run that code in ->suspend_noirq, but
-		 * it could not run after acpi_dev_suspend() and the driver
-		 * expected the latter to be called in the "late" phase.
-		 */
-		ret = acpi_lpss_do_suspend_late(dev);
-		if (ret)
-			return ret;
-	}
-
-	return acpi_subsys_suspend_noirq(dev);
-}
-
-static int acpi_lpss_do_resume_early(struct device *dev)
-{
-	int ret = acpi_lpss_resume(dev);
-
-	return ret ? ret : pm_generic_resume_early(dev);
-}
-
-static int acpi_lpss_resume_early(struct device *dev)
-{
-	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
-
-	if (pdata->dev_desc->resume_from_noirq)
-		return 0;
-
-	return acpi_lpss_do_resume_early(dev);
-}
-
-static int acpi_lpss_resume_noirq(struct device *dev)
-{
-	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
-	int ret;
-
-	/* Follow acpi_subsys_resume_noirq(). */
-	if (dev_pm_may_skip_resume(dev))
-		return 0;
-
-	if (dev_pm_smart_suspend_and_suspended(dev))
-		pm_runtime_set_active(dev);
-
-	ret = pm_generic_resume_noirq(dev);
-	if (ret)
-		return ret;
-
-	if (!pdata->dev_desc->resume_from_noirq)
-		return 0;
-
-	/*
-	 * The driver's ->resume_early callback will be invoked by
-	 * acpi_lpss_do_resume_early(), with the assumption that the driver
-	 * really wanted to run that code in ->resume_noirq, but it could not
-	 * run before acpi_dev_resume() and the driver expected the latter to be
-	 * called in the "early" phase.
-	 */
-	return acpi_lpss_do_resume_early(dev);
-}
-
-static int acpi_lpss_do_restore_early(struct device *dev)
-{
-	int ret = acpi_lpss_resume(dev);
-
-	return ret ? ret : pm_generic_restore_early(dev);
-}
-
-static int acpi_lpss_restore_early(struct device *dev)
-{
-	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
-
-	if (pdata->dev_desc->resume_from_noirq)
-		return 0;
-
-	return acpi_lpss_do_restore_early(dev);
-}
-
-static int acpi_lpss_restore_noirq(struct device *dev)
-{
-	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
-	int ret;
-
-	ret = pm_generic_restore_noirq(dev);
-	if (ret)
-		return ret;
-
-	if (!pdata->dev_desc->resume_from_noirq)
-		return 0;
-
-	/* This is analogous to what happens in acpi_lpss_resume_noirq(). */
-	return acpi_lpss_do_restore_early(dev);
-}
-
-static int acpi_lpss_do_poweroff_late(struct device *dev)
-{
-	int ret = pm_generic_poweroff_late(dev);
-
-	return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev));
-}
-
-static int acpi_lpss_poweroff_late(struct device *dev)
-{
-	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
-
-	if (dev_pm_smart_suspend_and_suspended(dev))
-		return 0;
-
-	if (pdata->dev_desc->resume_from_noirq)
-		return 0;
-
-	return acpi_lpss_do_poweroff_late(dev);
-}
-
-static int acpi_lpss_poweroff_noirq(struct device *dev)
-{
-	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
-
-	if (dev_pm_smart_suspend_and_suspended(dev))
-		return 0;
-
-	if (pdata->dev_desc->resume_from_noirq) {
-		/* This is analogous to the acpi_lpss_suspend_noirq() case. */
-		int ret = acpi_lpss_do_poweroff_late(dev);
-		if (ret)
-			return ret;
-	}
-
-	return pm_generic_poweroff_noirq(dev);
-}
-#endif /* CONFIG_PM_SLEEP */
-
-static int acpi_lpss_runtime_suspend(struct device *dev)
-{
-	int ret = pm_generic_runtime_suspend(dev);
-
-	return ret ? ret : acpi_lpss_suspend(dev, true);
-}
-
-static int acpi_lpss_runtime_resume(struct device *dev)
-{
-	int ret = acpi_lpss_resume(dev);
-
-	return ret ? ret : pm_generic_runtime_resume(dev);
-}
-#endif /* CONFIG_PM */
-
-static struct dev_pm_domain acpi_lpss_pm_domain = {
-#ifdef CONFIG_PM
-	.activate = acpi_lpss_activate,
-	.dismiss = acpi_lpss_dismiss,
-#endif
-	.ops = {
-#ifdef CONFIG_PM
-#ifdef CONFIG_PM_SLEEP
-		.prepare = acpi_subsys_prepare,
-		.complete = acpi_subsys_complete,
-		.suspend = acpi_subsys_suspend,
-		.suspend_late = acpi_lpss_suspend_late,
-		.suspend_noirq = acpi_lpss_suspend_noirq,
-		.resume_noirq = acpi_lpss_resume_noirq,
-		.resume_early = acpi_lpss_resume_early,
-		.freeze = acpi_subsys_freeze,
-		.poweroff = acpi_subsys_poweroff,
-		.poweroff_late = acpi_lpss_poweroff_late,
-		.poweroff_noirq = acpi_lpss_poweroff_noirq,
-		.restore_noirq = acpi_lpss_restore_noirq,
-		.restore_early = acpi_lpss_restore_early,
-#endif
-		.runtime_suspend = acpi_lpss_runtime_suspend,
-		.runtime_resume = acpi_lpss_runtime_resume,
-#endif
-	},
-};
-
-static int acpi_lpss_platform_notify(struct notifier_block *nb,
-				     unsigned long action, void *data)
-{
-	struct platform_device *pdev = to_platform_device(data);
-	struct lpss_private_data *pdata;
-	struct acpi_device *adev;
-	const struct acpi_device_id *id;
-
-	id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev);
-	if (!id || !id->driver_data)
-		return 0;
-
-	if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev))
-		return 0;
-
-	pdata = acpi_driver_data(adev);
-	if (!pdata)
-		return 0;
-
-	if (pdata->mmio_base &&
-	    pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) {
-		dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n");
-		return 0;
-	}
-
-	switch (action) {
-	case BUS_NOTIFY_BIND_DRIVER:
-		dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain);
-		break;
-	case BUS_NOTIFY_DRIVER_NOT_BOUND:
-	case BUS_NOTIFY_UNBOUND_DRIVER:
-		dev_pm_domain_set(&pdev->dev, NULL);
-		break;
-	case BUS_NOTIFY_ADD_DEVICE:
-		dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain);
-		if (pdata->dev_desc->flags & LPSS_LTR)
-			return sysfs_create_group(&pdev->dev.kobj,
-						  &lpss_attr_group);
-		break;
-	case BUS_NOTIFY_DEL_DEVICE:
-		if (pdata->dev_desc->flags & LPSS_LTR)
-			sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group);
-		dev_pm_domain_set(&pdev->dev, NULL);
-		break;
-	default:
-		break;
-	}
-
-	return 0;
-}
-
-static struct notifier_block acpi_lpss_nb = {
-	.notifier_call = acpi_lpss_platform_notify,
-};
-
-static void acpi_lpss_bind(struct device *dev)
-{
-	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
-
-	if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR))
-		return;
-
-	if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE)
-		dev->power.set_latency_tolerance = acpi_lpss_set_ltr;
-	else
-		dev_err(dev, "MMIO size insufficient to access LTR\n");
-}
-
-static void acpi_lpss_unbind(struct device *dev)
-{
-	dev->power.set_latency_tolerance = NULL;
-}
-
-static struct acpi_scan_handler lpss_handler = {
-	.ids = acpi_lpss_device_ids,
-	.attach = acpi_lpss_create_device,
-	.bind = acpi_lpss_bind,
-	.unbind = acpi_lpss_unbind,
-};
-
-void __init acpi_lpss_init(void)
-{
-	const struct x86_cpu_id *id;
-	int ret;
-
-	ret = lpt_clk_init();
-	if (ret)
-		return;
-
-	id = x86_match_cpu(lpss_cpu_ids);
-	if (id)
-		lpss_quirks |= LPSS_QUIRK_ALWAYS_POWER_ON;
-
-	bus_register_notifier(&platform_bus_type, &acpi_lpss_nb);
-	acpi_scan_add_handler(&lpss_handler);
-}
-
-#else
-
-static struct acpi_scan_handler lpss_handler = {
-	.ids = acpi_lpss_device_ids,
-};
-
-void __init acpi_lpss_init(void)
-{
-	acpi_scan_add_handler(&lpss_handler);
-}
-
-#endif /* CONFIG_X86_INTEL_LPSS */
diff --git a/drivers/acpi/acpi_memhotplug.c b/drivers/acpi/acpi_memhotplug.c
index e294f44a7850..d0c1a71007d0 100644
--- a/drivers/acpi/acpi_memhotplug.c
+++ b/drivers/acpi/acpi_memhotplug.c
@@ -22,13 +22,6 @@
 #define ACPI_MEMORY_DEVICE_HID			"PNP0C80"
 #define ACPI_MEMORY_DEVICE_NAME			"Hotplug Mem Device"
 
-#define _COMPONENT		ACPI_MEMORY_DEVICE_COMPONENT
-
-#undef PREFIX
-#define 	PREFIX		"ACPI:memory_hp:"
-
-ACPI_MODULE_NAME("acpi_memhotplug");
-
 static const struct acpi_device_id memory_device_ids[] = {
 	{ACPI_MEMORY_DEVICE_HID, 0},
 	{"", 0},
@@ -36,11 +29,6 @@ static const struct acpi_device_id memory_device_ids[] = {
 
 #ifdef CONFIG_ACPI_HOTPLUG_MEMORY
 
-/* Memory Device States */
-#define MEMORY_INVALID_STATE	0
-#define MEMORY_POWER_ON_STATE	1
-#define MEMORY_POWER_OFF_STATE	2
-
 static int acpi_memory_device_add(struct acpi_device *device,
 				  const struct acpi_device_id *not_used);
 static void acpi_memory_device_remove(struct acpi_device *device);
@@ -64,9 +52,9 @@ struct acpi_memory_info {
 };
 
 struct acpi_memory_device {
-	struct acpi_device * device;
-	unsigned int state;	/* State of the memory device */
+	struct acpi_device *device;
 	struct list_head res_list;
+	int mgid;
 };
 
 static acpi_status
@@ -182,11 +170,33 @@ static void acpi_unbind_memory_blocks(struct acpi_memory_info *info)
 static int acpi_memory_enable_device(struct acpi_memory_device *mem_device)
 {
 	acpi_handle handle = mem_device->device->handle;
+	mhp_t mhp_flags = MHP_NID_IS_MGID;
 	int result, num_enabled = 0;
 	struct acpi_memory_info *info;
-	int node;
+	u64 total_length = 0;
+	int node, mgid;
 
 	node = acpi_get_node(handle);
+
+	list_for_each_entry(info, &mem_device->res_list, list) {
+		if (!info->length)
+			continue;
+		/* We want a single node for the whole memory group */
+		if (node < 0)
+			node = memory_add_physaddr_to_nid(info->start_addr);
+		total_length += info->length;
+	}
+
+	if (!total_length) {
+		dev_err(&mem_device->device->dev, "device is empty\n");
+		return -EINVAL;
+	}
+
+	mgid = memory_group_register_static(node, PFN_UP(total_length));
+	if (mgid < 0)
+		return mgid;
+	mem_device->mgid = mgid;
+
 	/*
 	 * Tell the VM there is more memory here...
 	 * Note: Assume that this function returns zero on success
@@ -194,20 +204,16 @@ static int acpi_memory_enable_device(struct acpi_memory_device *mem_device)
 	 * (i.e. memory-hot-remove function)
 	 */
 	list_for_each_entry(info, &mem_device->res_list, list) {
-		if (info->enabled) { /* just sanity check...*/
-			num_enabled++;
-			continue;
-		}
 		/*
 		 * If the memory block size is zero, please ignore it.
 		 * Don't try to do the following memory hotplug flowchart.
 		 */
 		if (!info->length)
 			continue;
-		if (node < 0)
-			node = memory_add_physaddr_to_nid(info->start_addr);
 
-		result = __add_memory(node, info->start_addr, info->length);
+		mhp_flags |= MHP_MEMMAP_ON_MEMORY;
+		result = __add_memory(mgid, info->start_addr, info->length,
+				      mhp_flags);
 
 		/*
 		 * If the memory block has been used by the kernel, add_memory()
@@ -233,7 +239,6 @@ static int acpi_memory_enable_device(struct acpi_memory_device *mem_device)
 	}
 	if (!num_enabled) {
 		dev_err(&mem_device->device->dev, "add_memory failed\n");
-		mem_device->state = MEMORY_INVALID_STATE;
 		return -EINVAL;
 	}
 	/*
@@ -249,19 +254,14 @@ static int acpi_memory_enable_device(struct acpi_memory_device *mem_device)
 
 static void acpi_memory_remove_memory(struct acpi_memory_device *mem_device)
 {
-	acpi_handle handle = mem_device->device->handle;
 	struct acpi_memory_info *info, *n;
-	int nid = acpi_get_node(handle);
 
 	list_for_each_entry_safe(info, n, &mem_device->res_list, list) {
 		if (!info->enabled)
 			continue;
 
-		if (nid == NUMA_NO_NODE)
-			nid = memory_add_physaddr_to_nid(info->start_addr);
-
 		acpi_unbind_memory_blocks(info);
-		__remove_memory(nid, info->start_addr, info->length);
+		__remove_memory(info->start_addr, info->length);
 		list_del(&info->list);
 		kfree(info);
 	}
@@ -272,6 +272,10 @@ static void acpi_memory_device_free(struct acpi_memory_device *mem_device)
 	if (!mem_device)
 		return;
 
+	/* In case we succeeded adding *some* memory, unregistering fails. */
+	if (mem_device->mgid >= 0)
+		memory_group_unregister(mem_device->mgid);
+
 	acpi_memory_free_device_resources(mem_device);
 	mem_device->device->driver_data = NULL;
 	kfree(mem_device);
@@ -292,6 +296,7 @@ static int acpi_memory_device_add(struct acpi_device *device,
 
 	INIT_LIST_HEAD(&mem_device->res_list);
 	mem_device->device = device;
+	mem_device->mgid = -1;
 	sprintf(acpi_device_name(device), "%s", ACPI_MEMORY_DEVICE_NAME);
 	sprintf(acpi_device_class(device), "%s", ACPI_MEMORY_DEVICE_CLASS);
 	device->driver_data = mem_device;
@@ -304,9 +309,6 @@ static int acpi_memory_device_add(struct acpi_device *device,
 		return result;
 	}
 
-	/* Set the device state */
-	mem_device->state = MEMORY_POWER_ON_STATE;
-
 	result = acpi_memory_check_device(mem_device);
 	if (result) {
 		acpi_memory_device_free(mem_device);
diff --git a/drivers/acpi/acpi_mrrm.c b/drivers/acpi/acpi_mrrm.c
new file mode 100644
index 000000000000..6d69554c940e
--- /dev/null
+++ b/drivers/acpi/acpi_mrrm.c
@@ -0,0 +1,211 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2025, Intel Corporation.
+ *
+ * Memory Range and Region Mapping (MRRM) structure
+ *
+ * Parse and report the platform's MRRM table in /sys.
+ */
+
+#define pr_fmt(fmt) "acpi/mrrm: " fmt
+
+#include <linux/acpi.h>
+#include <linux/init.h>
+#include <linux/string.h>
+#include <linux/sysfs.h>
+
+/* Default assume one memory region covering all system memory, per the spec */
+static int max_mem_region = 1;
+
+/* Access for use by resctrl file system */
+int acpi_mrrm_max_mem_region(void)
+{
+	return max_mem_region;
+}
+
+struct mrrm_mem_range_entry {
+	u64 base;
+	u64 length;
+	int node;
+	u8  local_region_id;
+	u8  remote_region_id;
+};
+
+static struct mrrm_mem_range_entry *mrrm_mem_range_entry;
+static u32 mrrm_mem_entry_num;
+
+static int get_node_num(struct mrrm_mem_range_entry *e)
+{
+	unsigned int nid;
+
+	for_each_online_node(nid) {
+		for (int z = 0; z < MAX_NR_ZONES; z++) {
+			struct zone *zone = NODE_DATA(nid)->node_zones + z;
+
+			if (!populated_zone(zone))
+				continue;
+			if (zone_intersects(zone, PHYS_PFN(e->base), PHYS_PFN(e->length)))
+				return zone_to_nid(zone);
+		}
+	}
+
+	return -ENOENT;
+}
+
+static __init int acpi_parse_mrrm(struct acpi_table_header *table)
+{
+	struct acpi_mrrm_mem_range_entry *mre_entry;
+	struct acpi_table_mrrm *mrrm;
+	void *mre, *mrrm_end;
+	int mre_count = 0;
+
+	mrrm = (struct acpi_table_mrrm *)table;
+	if (!mrrm)
+		return -ENODEV;
+
+	if (mrrm->header.revision != 1)
+		return -EINVAL;
+
+	if (mrrm->flags & ACPI_MRRM_FLAGS_REGION_ASSIGNMENT_OS)
+		return -EOPNOTSUPP;
+
+	mrrm_end = (void *)mrrm + mrrm->header.length - 1;
+	mre = (void *)mrrm + sizeof(struct acpi_table_mrrm);
+	while (mre < mrrm_end) {
+		mre_entry = mre;
+		mre_count++;
+		mre += mre_entry->header.length;
+	}
+	if (!mre_count) {
+		pr_info(FW_BUG "No ranges listed in MRRM table\n");
+		return -EINVAL;
+	}
+
+	mrrm_mem_range_entry = kmalloc_array(mre_count, sizeof(*mrrm_mem_range_entry),
+					     GFP_KERNEL | __GFP_ZERO);
+	if (!mrrm_mem_range_entry)
+		return -ENOMEM;
+
+	mre = (void *)mrrm + sizeof(struct acpi_table_mrrm);
+	while (mre < mrrm_end) {
+		struct mrrm_mem_range_entry *e;
+
+		mre_entry = mre;
+		e = mrrm_mem_range_entry + mrrm_mem_entry_num;
+
+		e->base = mre_entry->addr_base;
+		e->length = mre_entry->addr_len;
+		e->node = get_node_num(e);
+
+		if (mre_entry->region_id_flags & ACPI_MRRM_VALID_REGION_ID_FLAGS_LOCAL)
+			e->local_region_id = mre_entry->local_region_id;
+		else
+			e->local_region_id = -1;
+		if (mre_entry->region_id_flags & ACPI_MRRM_VALID_REGION_ID_FLAGS_REMOTE)
+			e->remote_region_id = mre_entry->remote_region_id;
+		else
+			e->remote_region_id = -1;
+
+		mrrm_mem_entry_num++;
+		mre += mre_entry->header.length;
+	}
+
+	max_mem_region = mrrm->max_mem_region;
+
+	return 0;
+}
+
+#define RANGE_ATTR(name, fmt)						\
+static ssize_t name##_show(struct kobject *kobj,			\
+			  struct kobj_attribute *attr, char *buf)	\
+{									\
+	struct mrrm_mem_range_entry *mre;				\
+	const char *kname = kobject_name(kobj);				\
+	int n, ret;							\
+									\
+	ret = kstrtoint(kname + 5, 10, &n);				\
+	if (ret)							\
+		return ret;						\
+									\
+	mre = mrrm_mem_range_entry + n;					\
+									\
+	return sysfs_emit(buf, fmt, mre->name);				\
+}									\
+static struct kobj_attribute name##_attr = __ATTR_RO(name)
+
+RANGE_ATTR(base, "0x%llx\n");
+RANGE_ATTR(length, "0x%llx\n");
+RANGE_ATTR(node, "%d\n");
+RANGE_ATTR(local_region_id, "%d\n");
+RANGE_ATTR(remote_region_id, "%d\n");
+
+static struct attribute *memory_range_attrs[] = {
+	&base_attr.attr,
+	&length_attr.attr,
+	&node_attr.attr,
+	&local_region_id_attr.attr,
+	&remote_region_id_attr.attr,
+	NULL
+};
+
+ATTRIBUTE_GROUPS(memory_range);
+
+static __init int add_boot_memory_ranges(void)
+{
+	struct kobject *pkobj, *kobj, **kobjs;
+	int ret = -EINVAL;
+	char name[16];
+	int i;
+
+	pkobj = kobject_create_and_add("memory_ranges", acpi_kobj);
+	if (!pkobj)
+		return -ENOMEM;
+
+	kobjs = kcalloc(mrrm_mem_entry_num, sizeof(*kobjs), GFP_KERNEL);
+	if (!kobjs) {
+		kobject_put(pkobj);
+		return -ENOMEM;
+	}
+
+	for (i = 0; i < mrrm_mem_entry_num; i++) {
+		scnprintf(name, sizeof(name), "range%d", i);
+		kobj = kobject_create_and_add(name, pkobj);
+		if (!kobj) {
+			ret = -ENOMEM;
+			goto cleanup;
+		}
+
+		ret = sysfs_create_groups(kobj, memory_range_groups);
+		if (ret) {
+			kobject_put(kobj);
+			goto cleanup;
+		}
+		kobjs[i] = kobj;
+	}
+
+	kfree(kobjs);
+	return 0;
+
+cleanup:
+	for (int j = 0; j < i; j++) {
+		if (kobjs[j]) {
+			sysfs_remove_groups(kobjs[j], memory_range_groups);
+			kobject_put(kobjs[j]);
+		}
+	}
+	kfree(kobjs);
+	kobject_put(pkobj);
+	return ret;
+}
+
+static __init int mrrm_init(void)
+{
+	int ret;
+
+	ret = acpi_table_parse(ACPI_SIG_MRRM, acpi_parse_mrrm);
+	if (ret < 0)
+		return ret;
+
+	return add_boot_memory_ranges();
+}
+device_initcall(mrrm_init);
diff --git a/drivers/acpi/acpi_pad.c b/drivers/acpi/acpi_pad.c
index e7dc0133f817..c9a0bcaba2e4 100644
--- a/drivers/acpi/acpi_pad.c
+++ b/drivers/acpi/acpi_pad.c
@@ -17,16 +17,23 @@
 #include <linux/tick.h>
 #include <linux/slab.h>
 #include <linux/acpi.h>
+#include <linux/perf_event.h>
+#include <linux/platform_device.h>
+#include <asm/cpuid/api.h>
 #include <asm/mwait.h>
 #include <xen/xen.h>
 
 #define ACPI_PROCESSOR_AGGREGATOR_CLASS	"acpi_pad"
 #define ACPI_PROCESSOR_AGGREGATOR_DEVICE_NAME "Processor Aggregator"
 #define ACPI_PROCESSOR_AGGREGATOR_NOTIFY 0x80
+
+#define ACPI_PROCESSOR_AGGREGATOR_STATUS_SUCCESS	0
+#define ACPI_PROCESSOR_AGGREGATOR_STATUS_NO_ACTION	1
+
 static DEFINE_MUTEX(isolated_cpus_lock);
 static DEFINE_MUTEX(round_robin_lock);
 
-static unsigned long power_saving_mwait_eax;
+static unsigned int power_saving_mwait_eax;
 
 static unsigned char tsc_detected_unstable;
 static unsigned char tsc_marked_unstable;
@@ -40,10 +47,8 @@ static void power_saving_mwait_init(void)
 
 	if (!boot_cpu_has(X86_FEATURE_MWAIT))
 		return;
-	if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
-		return;
 
-	cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx);
+	cpuid(CPUID_LEAF_MWAIT, &eax, &ebx, &ecx, &edx);
 
 	if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
 	    !(ecx & CPUID5_ECX_INTERRUPT_BREAK))
@@ -65,6 +70,7 @@ static void power_saving_mwait_init(void)
 	case X86_VENDOR_AMD:
 	case X86_VENDOR_INTEL:
 	case X86_VENDOR_ZHAOXIN:
+	case X86_VENDOR_CENTAUR:
 		/*
 		 * AMD Fam10h TSC will tick in all
 		 * C/P/S0/S1 states when this bit is set.
@@ -88,7 +94,7 @@ static void round_robin_cpu(unsigned int tsk_index)
 	cpumask_var_t tmp;
 	int cpu;
 	unsigned long min_weight = -1;
-	unsigned long uninitialized_var(preferred_cpu);
+	unsigned long preferred_cpu;
 
 	if (!alloc_cpumask_var(&tmp, GFP_KERNEL))
 		return;
@@ -98,7 +104,7 @@ static void round_robin_cpu(unsigned int tsk_index)
 	for_each_cpu(cpu, pad_busy_cpus)
 		cpumask_or(tmp, tmp, topology_sibling_cpumask(cpu));
 	cpumask_andnot(tmp, cpu_online_mask, tmp);
-	/* avoid HT sibilings if possible */
+	/* avoid HT siblings if possible */
 	if (cpumask_empty(tmp))
 		cpumask_andnot(tmp, cpu_online_mask, pad_busy_cpus);
 	if (cpumask_empty(tmp)) {
@@ -128,20 +134,22 @@ static void round_robin_cpu(unsigned int tsk_index)
 static void exit_round_robin(unsigned int tsk_index)
 {
 	struct cpumask *pad_busy_cpus = to_cpumask(pad_busy_cpus_bits);
-	cpumask_clear_cpu(tsk_in_cpu[tsk_index], pad_busy_cpus);
-	tsk_in_cpu[tsk_index] = -1;
+
+	if (tsk_in_cpu[tsk_index] != -1) {
+		cpumask_clear_cpu(tsk_in_cpu[tsk_index], pad_busy_cpus);
+		tsk_in_cpu[tsk_index] = -1;
+	}
 }
 
 static unsigned int idle_pct = 5; /* percentage */
 static unsigned int round_robin_time = 1; /* second */
 static int power_saving_thread(void *data)
 {
-	struct sched_param param = {.sched_priority = 1};
 	int do_sleep;
 	unsigned int tsk_index = (unsigned long)data;
 	u64 last_jiffies = 0;
 
-	sched_setscheduler(current, SCHED_RR, &param);
+	sched_set_fifo_low(current);
 
 	while (!kthread_should_stop()) {
 		unsigned long expire_time;
@@ -164,6 +172,9 @@ static int power_saving_thread(void *data)
 				tsc_marked_unstable = 1;
 			}
 			local_irq_disable();
+
+			perf_lopwr_cb(true);
+
 			tick_broadcast_enable();
 			tick_broadcast_enter();
 			stop_critical_timings();
@@ -172,6 +183,9 @@ static int power_saving_thread(void *data)
 
 			start_critical_timings();
 			tick_broadcast_exit();
+
+			perf_lopwr_cb(false);
+
 			local_irq_enable();
 
 			if (time_before(expire_time, jiffies)) {
@@ -249,12 +263,12 @@ static void set_power_saving_task_num(unsigned int num)
 
 static void acpi_pad_idle_cpus(unsigned int num_cpus)
 {
-	get_online_cpus();
+	cpus_read_lock();
 
 	num_cpus = min_t(unsigned int, num_cpus, num_online_cpus());
 	set_power_saving_task_num(num_cpus);
 
-	put_online_cpus();
+	cpus_read_unlock();
 }
 
 static uint32_t acpi_pad_idle_cpus_num(void)
@@ -262,10 +276,11 @@ static uint32_t acpi_pad_idle_cpus_num(void)
 	return ps_tsk_num;
 }
 
-static ssize_t acpi_pad_rrtime_store(struct device *dev,
+static ssize_t rrtime_store(struct device *dev,
 	struct device_attribute *attr, const char *buf, size_t count)
 {
 	unsigned long num;
+
 	if (kstrtoul(buf, 0, &num))
 		return -EINVAL;
 	if (num < 1 || num >= 100)
@@ -276,19 +291,18 @@ static ssize_t acpi_pad_rrtime_store(struct device *dev,
 	return count;
 }
 
-static ssize_t acpi_pad_rrtime_show(struct device *dev,
+static ssize_t rrtime_show(struct device *dev,
 	struct device_attribute *attr, char *buf)
 {
-	return scnprintf(buf, PAGE_SIZE, "%d\n", round_robin_time);
+	return sysfs_emit(buf, "%d\n", round_robin_time);
 }
-static DEVICE_ATTR(rrtime, S_IRUGO|S_IWUSR,
-	acpi_pad_rrtime_show,
-	acpi_pad_rrtime_store);
+static DEVICE_ATTR_RW(rrtime);
 
-static ssize_t acpi_pad_idlepct_store(struct device *dev,
+static ssize_t idlepct_store(struct device *dev,
 	struct device_attribute *attr, const char *buf, size_t count)
 {
 	unsigned long num;
+
 	if (kstrtoul(buf, 0, &num))
 		return -EINVAL;
 	if (num < 1 || num >= 100)
@@ -299,19 +313,18 @@ static ssize_t acpi_pad_idlepct_store(struct device *dev,
 	return count;
 }
 
-static ssize_t acpi_pad_idlepct_show(struct device *dev,
+static ssize_t idlepct_show(struct device *dev,
 	struct device_attribute *attr, char *buf)
 {
-	return scnprintf(buf, PAGE_SIZE, "%d\n", idle_pct);
+	return sysfs_emit(buf, "%d\n", idle_pct);
 }
-static DEVICE_ATTR(idlepct, S_IRUGO|S_IWUSR,
-	acpi_pad_idlepct_show,
-	acpi_pad_idlepct_store);
+static DEVICE_ATTR_RW(idlepct);
 
-static ssize_t acpi_pad_idlecpus_store(struct device *dev,
+static ssize_t idlecpus_store(struct device *dev,
 	struct device_attribute *attr, const char *buf, size_t count)
 {
 	unsigned long num;
+
 	if (kstrtoul(buf, 0, &num))
 		return -EINVAL;
 	mutex_lock(&isolated_cpus_lock);
@@ -320,44 +333,23 @@ static ssize_t acpi_pad_idlecpus_store(struct device *dev,
 	return count;
 }
 
-static ssize_t acpi_pad_idlecpus_show(struct device *dev,
+static ssize_t idlecpus_show(struct device *dev,
 	struct device_attribute *attr, char *buf)
 {
 	return cpumap_print_to_pagebuf(false, buf,
 				       to_cpumask(pad_busy_cpus_bits));
 }
 
-static DEVICE_ATTR(idlecpus, S_IRUGO|S_IWUSR,
-	acpi_pad_idlecpus_show,
-	acpi_pad_idlecpus_store);
+static DEVICE_ATTR_RW(idlecpus);
 
-static int acpi_pad_add_sysfs(struct acpi_device *device)
-{
-	int result;
-
-	result = device_create_file(&device->dev, &dev_attr_idlecpus);
-	if (result)
-		return -ENODEV;
-	result = device_create_file(&device->dev, &dev_attr_idlepct);
-	if (result) {
-		device_remove_file(&device->dev, &dev_attr_idlecpus);
-		return -ENODEV;
-	}
-	result = device_create_file(&device->dev, &dev_attr_rrtime);
-	if (result) {
-		device_remove_file(&device->dev, &dev_attr_idlecpus);
-		device_remove_file(&device->dev, &dev_attr_idlepct);
-		return -ENODEV;
-	}
-	return 0;
-}
+static struct attribute *acpi_pad_attrs[] = {
+	&dev_attr_idlecpus.attr,
+	&dev_attr_idlepct.attr,
+	&dev_attr_rrtime.attr,
+	NULL
+};
 
-static void acpi_pad_remove_sysfs(struct acpi_device *device)
-{
-	device_remove_file(&device->dev, &dev_attr_idlecpus);
-	device_remove_file(&device->dev, &dev_attr_idlepct);
-	device_remove_file(&device->dev, &dev_attr_rrtime);
-}
+ATTRIBUTE_GROUPS(acpi_pad);
 
 /*
  * Query firmware how many CPUs should be idle
@@ -395,29 +387,36 @@ static void acpi_pad_handle_notify(acpi_handle handle)
 		.length = 4,
 		.pointer = (void *)&idle_cpus,
 	};
+	u32 status;
 
 	mutex_lock(&isolated_cpus_lock);
 	num_cpus = acpi_pad_pur(handle);
 	if (num_cpus < 0) {
-		mutex_unlock(&isolated_cpus_lock);
-		return;
+		/* The ACPI specification says that if no action was performed when
+		 * processing the _PUR object, _OST should still be evaluated, albeit
+		 * with a different status code.
+		 */
+		status = ACPI_PROCESSOR_AGGREGATOR_STATUS_NO_ACTION;
+	} else {
+		status = ACPI_PROCESSOR_AGGREGATOR_STATUS_SUCCESS;
+		acpi_pad_idle_cpus(num_cpus);
 	}
-	acpi_pad_idle_cpus(num_cpus);
+
 	idle_cpus = acpi_pad_idle_cpus_num();
-	acpi_evaluate_ost(handle, ACPI_PROCESSOR_AGGREGATOR_NOTIFY, 0, &param);
+	acpi_evaluate_ost(handle, ACPI_PROCESSOR_AGGREGATOR_NOTIFY, status, &param);
 	mutex_unlock(&isolated_cpus_lock);
 }
 
 static void acpi_pad_notify(acpi_handle handle, u32 event,
 	void *data)
 {
-	struct acpi_device *device = data;
+	struct acpi_device *adev = data;
 
 	switch (event) {
 	case ACPI_PROCESSOR_AGGREGATOR_NOTIFY:
 		acpi_pad_handle_notify(handle);
-		acpi_bus_generate_netlink_event(device->pnp.device_class,
-			dev_name(&device->dev), event, 0);
+		acpi_bus_generate_netlink_event(adev->pnp.device_class,
+			dev_name(&adev->dev), event, 0);
 		break;
 	default:
 		pr_warn("Unsupported event [0x%x]\n", event);
@@ -425,36 +424,33 @@ static void acpi_pad_notify(acpi_handle handle, u32 event,
 	}
 }
 
-static int acpi_pad_add(struct acpi_device *device)
+static int acpi_pad_probe(struct platform_device *pdev)
 {
+	struct acpi_device *adev = ACPI_COMPANION(&pdev->dev);
 	acpi_status status;
 
-	strcpy(acpi_device_name(device), ACPI_PROCESSOR_AGGREGATOR_DEVICE_NAME);
-	strcpy(acpi_device_class(device), ACPI_PROCESSOR_AGGREGATOR_CLASS);
+	strscpy(acpi_device_name(adev), ACPI_PROCESSOR_AGGREGATOR_DEVICE_NAME);
+	strscpy(acpi_device_class(adev), ACPI_PROCESSOR_AGGREGATOR_CLASS);
 
-	if (acpi_pad_add_sysfs(device))
-		return -ENODEV;
+	status = acpi_install_notify_handler(adev->handle,
+		ACPI_DEVICE_NOTIFY, acpi_pad_notify, adev);
 
-	status = acpi_install_notify_handler(device->handle,
-		ACPI_DEVICE_NOTIFY, acpi_pad_notify, device);
-	if (ACPI_FAILURE(status)) {
-		acpi_pad_remove_sysfs(device);
+	if (ACPI_FAILURE(status))
 		return -ENODEV;
-	}
 
 	return 0;
 }
 
-static int acpi_pad_remove(struct acpi_device *device)
+static void acpi_pad_remove(struct platform_device *pdev)
 {
+	struct acpi_device *adev = ACPI_COMPANION(&pdev->dev);
+
 	mutex_lock(&isolated_cpus_lock);
 	acpi_pad_idle_cpus(0);
 	mutex_unlock(&isolated_cpus_lock);
 
-	acpi_remove_notify_handler(device->handle,
+	acpi_remove_notify_handler(adev->handle,
 		ACPI_DEVICE_NOTIFY, acpi_pad_notify);
-	acpi_pad_remove_sysfs(device);
-	return 0;
 }
 
 static const struct acpi_device_id pad_device_ids[] = {
@@ -463,13 +459,13 @@ static const struct acpi_device_id pad_device_ids[] = {
 };
 MODULE_DEVICE_TABLE(acpi, pad_device_ids);
 
-static struct acpi_driver acpi_pad_driver = {
-	.name = "processor_aggregator",
-	.class = ACPI_PROCESSOR_AGGREGATOR_CLASS,
-	.ids = pad_device_ids,
-	.ops = {
-		.add = acpi_pad_add,
-		.remove = acpi_pad_remove,
+static struct platform_driver acpi_pad_driver = {
+	.probe = acpi_pad_probe,
+	.remove = acpi_pad_remove,
+	.driver = {
+		.dev_groups = acpi_pad_groups,
+		.name = "processor_aggregator",
+		.acpi_match_table = pad_device_ids,
 	},
 };
 
@@ -483,12 +479,12 @@ static int __init acpi_pad_init(void)
 	if (power_saving_mwait_eax == 0)
 		return -EINVAL;
 
-	return acpi_bus_register_driver(&acpi_pad_driver);
+	return platform_driver_register(&acpi_pad_driver);
 }
 
 static void __exit acpi_pad_exit(void)
 {
-	acpi_bus_unregister_driver(&acpi_pad_driver);
+	platform_driver_unregister(&acpi_pad_driver);
 }
 
 module_init(acpi_pad_init);
diff --git a/drivers/acpi/acpi_pcc.c b/drivers/acpi/acpi_pcc.c
new file mode 100644
index 000000000000..97064e943768
--- /dev/null
+++ b/drivers/acpi/acpi_pcc.c
@@ -0,0 +1,144 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Author: Sudeep Holla <sudeep.holla@arm.com>
+ * Copyright 2021 Arm Limited
+ *
+ * The PCC Address Space also referred as PCC Operation Region pertains to the
+ * region of PCC subspace that succeeds the PCC signature. The PCC Operation
+ * Region works in conjunction with the PCC Table(Platform Communications
+ * Channel Table). PCC subspaces that are marked for use as PCC Operation
+ * Regions must not be used as PCC subspaces for the standard ACPI features
+ * such as CPPC, RASF, PDTT and MPST. These standard features must always use
+ * the PCC Table instead.
+ *
+ * This driver sets up the PCC Address Space and installs an handler to enable
+ * handling of PCC OpRegion in the firmware.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/acpi.h>
+#include <linux/completion.h>
+#include <linux/idr.h>
+#include <linux/io.h>
+
+#include <acpi/pcc.h>
+
+/*
+ * Arbitrary retries in case the remote processor is slow to respond
+ * to PCC commands
+ */
+#define PCC_CMD_WAIT_RETRIES_NUM	500ULL
+
+struct pcc_data {
+	struct pcc_mbox_chan *pcc_chan;
+	struct completion done;
+	struct mbox_client cl;
+	struct acpi_pcc_info ctx;
+};
+
+static struct acpi_pcc_info pcc_ctx;
+
+static void pcc_rx_callback(struct mbox_client *cl, void *m)
+{
+	struct pcc_data *data = container_of(cl, struct pcc_data, cl);
+
+	complete(&data->done);
+}
+
+static acpi_status
+acpi_pcc_address_space_setup(acpi_handle region_handle, u32 function,
+			     void *handler_context,  void **region_context)
+{
+	struct pcc_data *data;
+	struct acpi_pcc_info *ctx = handler_context;
+	struct pcc_mbox_chan *pcc_chan;
+	static acpi_status ret;
+
+	data = kzalloc(sizeof(*data), GFP_KERNEL);
+	if (!data)
+		return AE_NO_MEMORY;
+
+	data->cl.rx_callback = pcc_rx_callback;
+	data->cl.knows_txdone = true;
+	data->ctx.length = ctx->length;
+	data->ctx.subspace_id = ctx->subspace_id;
+	data->ctx.internal_buffer = ctx->internal_buffer;
+
+	init_completion(&data->done);
+	data->pcc_chan = pcc_mbox_request_channel(&data->cl, ctx->subspace_id);
+	if (IS_ERR(data->pcc_chan)) {
+		pr_err("Failed to find PCC channel for subspace %d\n",
+		       ctx->subspace_id);
+		ret = AE_NOT_FOUND;
+		goto err_free_data;
+	}
+
+	pcc_chan = data->pcc_chan;
+	if (!pcc_chan->mchan->mbox->txdone_irq) {
+		pr_err("This channel-%d does not support interrupt.\n",
+		       ctx->subspace_id);
+		ret = AE_SUPPORT;
+		goto err_free_channel;
+	}
+
+	*region_context = data;
+	return AE_OK;
+
+err_free_channel:
+	pcc_mbox_free_channel(data->pcc_chan);
+err_free_data:
+	kfree(data);
+
+	return ret;
+}
+
+static acpi_status
+acpi_pcc_address_space_handler(u32 function, acpi_physical_address addr,
+			       u32 bits, acpi_integer *value,
+			       void *handler_context, void *region_context)
+{
+	int ret;
+	struct pcc_data *data = region_context;
+	u64 usecs_lat;
+
+	reinit_completion(&data->done);
+
+	/* Write to Shared Memory */
+	memcpy_toio(data->pcc_chan->shmem, (void *)value, data->ctx.length);
+
+	ret = mbox_send_message(data->pcc_chan->mchan, NULL);
+	if (ret < 0)
+		return AE_ERROR;
+
+	/*
+	 * pcc_chan->latency is just a Nominal value. In reality the remote
+	 * processor could be much slower to reply. So add an arbitrary
+	 * amount of wait on top of Nominal.
+	 */
+	usecs_lat = PCC_CMD_WAIT_RETRIES_NUM * data->pcc_chan->latency;
+	ret = wait_for_completion_timeout(&data->done,
+						usecs_to_jiffies(usecs_lat));
+	if (ret == 0) {
+		pr_err("PCC command executed timeout!\n");
+		return AE_TIME;
+	}
+
+	mbox_chan_txdone(data->pcc_chan->mchan, ret);
+
+	memcpy_fromio(value, data->pcc_chan->shmem, data->ctx.length);
+
+	return AE_OK;
+}
+
+void __init acpi_init_pcc(void)
+{
+	acpi_status status;
+
+	status = acpi_install_address_space_handler(ACPI_ROOT_OBJECT,
+						    ACPI_ADR_SPACE_PLATFORM_COMM,
+						    &acpi_pcc_address_space_handler,
+						    &acpi_pcc_address_space_setup,
+						    &pcc_ctx);
+	if (ACPI_FAILURE(status))
+		pr_alert("OperationRegion handler could not be installed\n");
+}
diff --git a/drivers/acpi/acpi_platform.c b/drivers/acpi/acpi_platform.c
index c05050f474cd..48d15dd785f6 100644
--- a/drivers/acpi/acpi_platform.c
+++ b/drivers/acpi/acpi_platform.c
@@ -9,6 +9,7 @@
  */
 
 #include <linux/acpi.h>
+#include <linux/bits.h>
 #include <linux/device.h>
 #include <linux/err.h>
 #include <linux/kernel.h>
@@ -19,16 +20,17 @@
 
 #include "internal.h"
 
-ACPI_MODULE_NAME("platform");
+/* Exclude devices that have no _CRS resources provided */
+#define ACPI_ALLOW_WO_RESOURCES		BIT(0)
 
 static const struct acpi_device_id forbidden_id_list[] = {
+	{"ACPI0009", 0},	/* IOxAPIC */
+	{"ACPI000A", 0},	/* IOAPIC */
 	{"PNP0000",  0},	/* PIC */
 	{"PNP0100",  0},	/* Timer */
 	{"PNP0200",  0},	/* AT DMA Controller */
-	{"ACPI0009", 0},	/* IOxAPIC */
-	{"ACPI000A", 0},	/* IOAPIC */
-	{"SMB0001",  0},	/* ACPI SMBUS virtual device */
-	{"", 0},
+	{ACPI_SMBUS_MS_HID,  ACPI_ALLOW_WO_RESOURCES},	/* ACPI SMBUS virtual device */
+	{ }
 };
 
 static struct platform_device *acpi_platform_device_find_by_companion(struct acpi_device *adev)
@@ -80,11 +82,20 @@ static void acpi_platform_fill_resource(struct acpi_device *adev,
 	 * If the device has parent we need to take its resources into
 	 * account as well because this device might consume part of those.
 	 */
-	parent = acpi_get_first_physical_node(adev->parent);
+	parent = acpi_get_first_physical_node(acpi_dev_parent(adev));
 	if (parent && dev_is_pci(parent))
 		dest->parent = pci_find_resource(to_pci_dev(parent), dest);
 }
 
+static unsigned int acpi_platform_resource_count(struct acpi_resource *ares, void *data)
+{
+	bool *has_resources = data;
+
+	*has_resources = true;
+
+	return AE_CTRL_TERMINATE;
+}
+
 /**
  * acpi_create_platform_device - Create platform device for ACPI device node
  * @adev: ACPI device node to create a platform device for.
@@ -97,10 +108,12 @@ static void acpi_platform_fill_resource(struct acpi_device *adev,
  * Name of the platform device will be the same as @adev's.
  */
 struct platform_device *acpi_create_platform_device(struct acpi_device *adev,
-					struct property_entry *properties)
+						    const struct property_entry *properties)
 {
+	struct acpi_device *parent = acpi_dev_parent(adev);
 	struct platform_device *pdev = NULL;
 	struct platform_device_info pdevinfo;
+	const struct acpi_device_id *match;
 	struct resource_entry *rentry;
 	struct list_head resource_list;
 	struct resource *resources = NULL;
@@ -110,18 +123,27 @@ struct platform_device *acpi_create_platform_device(struct acpi_device *adev,
 	if (adev->physical_node_count)
 		return NULL;
 
-	if (!acpi_match_device_ids(adev, forbidden_id_list))
-		return ERR_PTR(-EINVAL);
+	match = acpi_match_acpi_device(forbidden_id_list, adev);
+	if (match) {
+		if (match->driver_data & ACPI_ALLOW_WO_RESOURCES) {
+			bool has_resources = false;
+
+			acpi_walk_resources(adev->handle, METHOD_NAME__CRS,
+					    acpi_platform_resource_count, &has_resources);
+			if (has_resources)
+				return ERR_PTR(-EINVAL);
+		} else {
+			return ERR_PTR(-EINVAL);
+		}
+	}
 
 	INIT_LIST_HEAD(&resource_list);
 	count = acpi_dev_get_resources(adev, &resource_list, NULL, NULL);
-	if (count < 0) {
+	if (count < 0)
 		return NULL;
-	} else if (count > 0) {
-		resources = kcalloc(count, sizeof(struct resource),
-				    GFP_KERNEL);
+	if (count > 0) {
+		resources = kcalloc(count, sizeof(*resources), GFP_KERNEL);
 		if (!resources) {
-			dev_err(&adev->dev, "No memory for resources\n");
 			acpi_dev_free_resource_list(&resource_list);
 			return ERR_PTR(-ENOMEM);
 		}
@@ -139,10 +161,9 @@ struct platform_device *acpi_create_platform_device(struct acpi_device *adev,
 	 * attached to it, that physical device should be the parent of the
 	 * platform device we are about to create.
 	 */
-	pdevinfo.parent = adev->parent ?
-		acpi_get_first_physical_node(adev->parent) : NULL;
+	pdevinfo.parent = parent ? acpi_get_first_physical_node(parent) : NULL;
 	pdevinfo.name = dev_name(&adev->dev);
-	pdevinfo.id = -1;
+	pdevinfo.id = PLATFORM_DEVID_NONE;
 	pdevinfo.res = resources;
 	pdevinfo.num_res = count;
 	pdevinfo.fwnode = acpi_fwnode_handle(adev);
diff --git a/drivers/acpi/acpi_pnp.c b/drivers/acpi/acpi_pnp.c
index f3039b93ff61..4ad88187dc7a 100644
--- a/drivers/acpi/acpi_pnp.c
+++ b/drivers/acpi/acpi_pnp.c
@@ -11,6 +11,8 @@
 #include <linux/module.h>
 #include <linux/ctype.h>
 
+#include "internal.h"
+
 static const struct acpi_device_id acpi_pnp_device_ids[] = {
 	/* pata_isapnp */
 	{"PNP0600"},		/* Generic ESDI/IDE/ATA compatible hard disk controller */
@@ -118,8 +120,6 @@ static const struct acpi_device_id acpi_pnp_device_ids[] = {
 	{"IBM0071"},
 	/* smsc-ircc2 */
 	{"SMCf010"},
-	/* sb1000 */
-	{"GIC1000"},
 	/* parport_pc */
 	{"PNP0400"},		/* Standard LPT Printer Port */
 	{"PNP0401"},		/* ECP Printer Port */
@@ -154,8 +154,6 @@ static const struct acpi_device_id acpi_pnp_device_ids[] = {
 	{"BRI0A49"},		/* Boca Complete Ofc Communicator 14.4 Data-FAX */
 	{"BRI1400"},		/* Boca Research 33,600 ACF Modem */
 	{"BRI3400"},		/* Boca 33.6 Kbps Internal FD34FSVD */
-	{"BRI0A49"},		/* Boca 33.6 Kbps Internal FD34FSVD */
-	{"BDP3336"},		/* Best Data Products Inc. Smart One 336F PnP Modem */
 	{"CPI4050"},		/* Computer Peripherals Inc. EuroViVa CommCenter-33.6 SP PnP */
 	{"CTL3001"},		/* Creative Labs Phone Blaster 28.8 DSVD PnP Voice */
 	{"CTL3011"},		/* Creative Labs Modem Blaster 28.8 DSVD PnP Voice */
@@ -317,6 +315,9 @@ static bool matching_id(const char *idstr, const char *list_id)
 {
 	int i;
 
+	if (strlen(idstr) != strlen(list_id))
+		return false;
+
 	if (memcmp(idstr, list_id, 3))
 		return false;
 
@@ -345,10 +346,24 @@ static bool acpi_pnp_match(const char *idstr, const struct acpi_device_id **matc
 	return false;
 }
 
+/*
+ * If one of the device IDs below is present in the list of device IDs of a
+ * given ACPI device object, the PNP scan handler will not attach to that
+ * object, because there is a proper non-PNP driver in the kernel for the
+ * device represented by it.
+ */
+static const struct acpi_device_id acpi_nonpnp_device_ids[] = {
+	{"INT3F0D"},
+	{"INTC1080"},
+	{"INTC1081"},
+	{"INTC1099"},
+	{""},
+};
+
 static int acpi_pnp_attach(struct acpi_device *adev,
 			   const struct acpi_device_id *id)
 {
-	return 1;
+	return !!acpi_match_device_ids(adev, acpi_nonpnp_device_ids);
 }
 
 static struct acpi_scan_handler acpi_pnp_handler = {
diff --git a/drivers/acpi/acpi_processor.c b/drivers/acpi/acpi_processor.c
index 5379bc3f275d..7ec1dc04fd11 100644
--- a/drivers/acpi/acpi_processor.c
+++ b/drivers/acpi/acpi_processor.c
@@ -9,33 +9,43 @@
  * Copyright (C) 2013, Intel Corporation
  *                     Rafael J. Wysocki <rafael.j.wysocki@intel.com>
  */
+#define pr_fmt(fmt) "ACPI: " fmt
 
 #include <linux/acpi.h>
+#include <linux/cpu.h>
 #include <linux/device.h>
+#include <linux/dmi.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/pci.h>
+#include <linux/platform_device.h>
 
 #include <acpi/processor.h>
 
 #include <asm/cpu.h>
 
-#include "internal.h"
-
-#define _COMPONENT	ACPI_PROCESSOR_COMPONENT
+#include <xen/xen.h>
 
-ACPI_MODULE_NAME("processor");
+#include "internal.h"
 
 DEFINE_PER_CPU(struct acpi_processor *, processors);
 EXPORT_PER_CPU_SYMBOL(processors);
 
-/* --------------------------------------------------------------------------
-                                Errata Handling
-   -------------------------------------------------------------------------- */
-
+/* Errata Handling */
 struct acpi_processor_errata errata __read_mostly;
 EXPORT_SYMBOL_GPL(errata);
 
+acpi_handle acpi_get_processor_handle(int cpu)
+{
+	struct acpi_processor *pr;
+
+	pr = per_cpu(processors, cpu);
+	if (pr)
+		return pr->handle;
+
+	return NULL;
+}
+
 static int acpi_processor_errata_piix4(struct pci_dev *dev)
 {
 	u8 value1 = 0;
@@ -51,19 +61,19 @@ static int acpi_processor_errata_piix4(struct pci_dev *dev)
 
 	switch (dev->revision) {
 	case 0:
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found PIIX4 A-step\n"));
+		dev_dbg(&dev->dev, "Found PIIX4 A-step\n");
 		break;
 	case 1:
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found PIIX4 B-step\n"));
+		dev_dbg(&dev->dev, "Found PIIX4 B-step\n");
 		break;
 	case 2:
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found PIIX4E\n"));
+		dev_dbg(&dev->dev, "Found PIIX4E\n");
 		break;
 	case 3:
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found PIIX4M\n"));
+		dev_dbg(&dev->dev, "Found PIIX4M\n");
 		break;
 	default:
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found unknown PIIX4\n"));
+		dev_dbg(&dev->dev, "Found unknown PIIX4\n");
 		break;
 	}
 
@@ -79,7 +89,7 @@ static int acpi_processor_errata_piix4(struct pci_dev *dev)
 		 * PIIX4 models.
 		 */
 		errata.piix4.throttle = 1;
-		/* fall through*/
+		fallthrough;
 
 	case 2:		/* PIIX4E */
 	case 3:		/* PIIX4M */
@@ -129,11 +139,9 @@ static int acpi_processor_errata_piix4(struct pci_dev *dev)
 	}
 
 	if (errata.piix4.bmisx)
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-				  "Bus master activity detection (BM-IDE) erratum enabled\n"));
+		dev_dbg(&dev->dev, "Bus master activity detection (BM-IDE) erratum enabled\n");
 	if (errata.piix4.fdma)
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-				  "Type-F DMA livelock erratum (C3 disabled)\n"));
+		dev_dbg(&dev->dev, "Type-F DMA livelock erratum (C3 disabled)\n");
 
 	return 0;
 }
@@ -157,70 +165,109 @@ static int acpi_processor_errata(void)
 	return result;
 }
 
-/* --------------------------------------------------------------------------
-                                Initialization
-   -------------------------------------------------------------------------- */
-
-#ifdef CONFIG_ACPI_HOTPLUG_CPU
-int __weak acpi_map_cpu(acpi_handle handle,
-		phys_cpuid_t physid, u32 acpi_id, int *pcpu)
+/* Create a platform device to represent a CPU frequency control mechanism. */
+static void cpufreq_add_device(const char *name)
 {
-	return -ENODEV;
+	struct platform_device *pdev;
+
+	pdev = platform_device_register_simple(name, PLATFORM_DEVID_NONE, NULL, 0);
+	if (IS_ERR(pdev))
+		pr_info("%s device creation failed: %pe\n", name, pdev);
 }
 
-int __weak acpi_unmap_cpu(int cpu)
+#ifdef CONFIG_X86
+/* Check presence of Processor Clocking Control by searching for \_SB.PCCH. */
+static void __init acpi_pcc_cpufreq_init(void)
 {
-	return -ENODEV;
+	acpi_status status;
+	acpi_handle handle;
+
+	status = acpi_get_handle(NULL, "\\_SB", &handle);
+	if (ACPI_FAILURE(status))
+		return;
+
+	if (acpi_has_method(handle, "PCCH"))
+		cpufreq_add_device("pcc-cpufreq");
 }
+#else
+static void __init acpi_pcc_cpufreq_init(void) {}
+#endif /* CONFIG_X86 */
 
-int __weak arch_register_cpu(int cpu)
+/* Initialization */
+static DEFINE_PER_CPU(void *, processor_device_array);
+
+static int acpi_processor_set_per_cpu(struct acpi_processor *pr,
+				      struct acpi_device *device)
 {
-	return -ENODEV;
-}
+	BUG_ON(pr->id >= nr_cpu_ids);
+
+	/*
+	 * Buggy BIOS check.
+	 * ACPI id of processors can be reported wrongly by the BIOS.
+	 * Don't trust it blindly
+	 */
+	if (per_cpu(processor_device_array, pr->id) != NULL &&
+	    per_cpu(processor_device_array, pr->id) != device) {
+		dev_warn(&device->dev,
+			 "BIOS reported wrong ACPI id %d for the processor\n",
+			 pr->id);
+		return -EINVAL;
+	}
+	/*
+	 * processor_device_array is not cleared on errors to allow buggy BIOS
+	 * checks.
+	 */
+	per_cpu(processor_device_array, pr->id) = device;
+	per_cpu(processors, pr->id) = pr;
 
-void __weak arch_unregister_cpu(int cpu) {}
+	return 0;
+}
 
-static int acpi_processor_hotadd_init(struct acpi_processor *pr)
+#ifdef CONFIG_ACPI_HOTPLUG_CPU
+static int acpi_processor_hotadd_init(struct acpi_processor *pr,
+				      struct acpi_device *device)
 {
-	unsigned long long sta;
-	acpi_status status;
 	int ret;
 
 	if (invalid_phys_cpuid(pr->phys_id))
 		return -ENODEV;
 
-	status = acpi_evaluate_integer(pr->handle, "_STA", NULL, &sta);
-	if (ACPI_FAILURE(status) || !(sta & ACPI_STA_DEVICE_PRESENT))
-		return -ENODEV;
-
 	cpu_maps_update_begin();
-	cpu_hotplug_begin();
+	cpus_write_lock();
 
 	ret = acpi_map_cpu(pr->handle, pr->phys_id, pr->acpi_id, &pr->id);
 	if (ret)
 		goto out;
 
+	ret = acpi_processor_set_per_cpu(pr, device);
+	if (ret) {
+		acpi_unmap_cpu(pr->id);
+		goto out;
+	}
+
 	ret = arch_register_cpu(pr->id);
 	if (ret) {
+		/* Leave the processor device array in place to detect buggy bios */
+		per_cpu(processors, pr->id) = NULL;
 		acpi_unmap_cpu(pr->id);
 		goto out;
 	}
 
 	/*
-	 * CPU got hot-added, but cpu_data is not initialized yet.  Set a flag
-	 * to delay cpu_idle/throttling initialization and do it when the CPU
-	 * gets online for the first time.
+	 * CPU got hot-added, but cpu_data is not initialized yet. Do
+	 * cpu_idle/throttling initialization when the CPU gets online for
+	 * the first time.
 	 */
 	pr_info("CPU%d has been hot-added\n", pr->id);
-	pr->flags.need_hotplug_init = 1;
 
 out:
-	cpu_hotplug_done();
+	cpus_write_unlock();
 	cpu_maps_update_done();
 	return ret;
 }
 #else
-static inline int acpi_processor_hotadd_init(struct acpi_processor *pr)
+static inline int acpi_processor_hotadd_init(struct acpi_processor *pr,
+					     struct acpi_device *device)
 {
 	return -ENODEV;
 }
@@ -228,13 +275,14 @@ static inline int acpi_processor_hotadd_init(struct acpi_processor *pr)
 
 static int acpi_processor_get_info(struct acpi_device *device)
 {
-	union acpi_object object = { 0 };
+	union acpi_object object = { .processor = { 0 } };
 	struct acpi_buffer buffer = { sizeof(union acpi_object), &object };
 	struct acpi_processor *pr = acpi_driver_data(device);
 	int device_declaration = 0;
 	acpi_status status = AE_OK;
 	static int cpu0_initialized;
 	unsigned long long value;
+	int ret;
 
 	acpi_processor_errata();
 
@@ -244,11 +292,9 @@ static int acpi_processor_get_info(struct acpi_device *device)
 	 */
 	if (acpi_gbl_FADT.pm2_control_block && acpi_gbl_FADT.pm2_control_length) {
 		pr->flags.bm_control = 1;
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-				  "Bus mastering arbitration control present\n"));
+		dev_dbg(&device->dev, "Bus mastering arbitration control present\n");
 	} else
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-				  "No bus mastering arbitration control\n"));
+		dev_dbg(&device->dev, "No bus mastering arbitration control\n");
 
 	if (!strcmp(acpi_device_hid(device), ACPI_PROCESSOR_OBJECT_HID)) {
 		/* Declared with "Processor" statement; match ProcessorID */
@@ -264,7 +310,6 @@ static int acpi_processor_get_info(struct acpi_device *device)
 	} else {
 		/*
 		 * Declared with "Device" statement; match _UID.
-		 * Note that we don't handle string _UIDs yet.
 		 */
 		status = acpi_evaluate_integer(pr->handle, METHOD_NAME__UID,
 						NULL, &value);
@@ -292,32 +337,41 @@ static int acpi_processor_get_info(struct acpi_device *device)
 	pr->phys_id = acpi_get_phys_id(pr->handle, device_declaration,
 					pr->acpi_id);
 	if (invalid_phys_cpuid(pr->phys_id))
-		acpi_handle_debug(pr->handle, "failed to get CPU physical ID.\n");
+		dev_dbg(&device->dev, "Failed to get CPU physical ID.\n");
 
 	pr->id = acpi_map_cpuid(pr->phys_id, pr->acpi_id);
-	if (!cpu0_initialized && !acpi_has_cpu_in_madt()) {
+	if (!cpu0_initialized) {
 		cpu0_initialized = 1;
 		/*
 		 * Handle UP system running SMP kernel, with no CPU
 		 * entry in MADT
 		 */
-		if (invalid_logical_cpuid(pr->id) && (num_online_cpus() == 1))
+		if (!acpi_has_cpu_in_madt() && invalid_logical_cpuid(pr->id) &&
+		    (num_online_cpus() == 1))
 			pr->id = 0;
+		/*
+		 * Check availability of Processor Performance Control by
+		 * looking at the presence of the _PCT object under the first
+		 * processor definition.
+		 */
+		if (acpi_has_method(pr->handle, "_PCT"))
+			cpufreq_add_device("acpi-cpufreq");
 	}
 
 	/*
-	 *  Extra Processor objects may be enumerated on MP systems with
-	 *  less than the max # of CPUs. They should be ignored _iff
-	 *  they are physically not present.
-	 *
-	 *  NOTE: Even if the processor has a cpuid, it may not be present
-	 *  because cpuid <-> apicid mapping is persistent now.
+	 *  This code is not called unless we know the CPU is present and
+	 *  enabled. The two paths are:
+	 *  a) Initially present CPUs on architectures that do not defer
+	 *     their arch_register_cpu() calls until this point.
+	 *  b) Hotplugged CPUs (enabled bit in _STA has transitioned from not
+	 *     enabled to enabled)
 	 */
-	if (invalid_logical_cpuid(pr->id) || !cpu_present(pr->id)) {
-		int ret = acpi_processor_hotadd_init(pr);
-		if (ret)
-			return ret;
-	}
+	if (!get_cpu_device(pr->id))
+		ret = acpi_processor_hotadd_init(pr, device);
+	else
+		ret = acpi_processor_set_per_cpu(pr, device);
+	if (ret)
+		return ret;
 
 	/*
 	 * On some boxes several processors use the same processor bus id.
@@ -329,11 +383,10 @@ static int acpi_processor_get_info(struct acpi_device *device)
 	 * CPU+CPU ID.
 	 */
 	sprintf(acpi_device_bid(device), "CPU%X", pr->id);
-	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Processor [%d:%d]\n", pr->id,
-			  pr->acpi_id));
+	dev_dbg(&device->dev, "Processor [%d:%d]\n", pr->id, pr->acpi_id);
 
 	if (!object.processor.pblk_address)
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No PBLK (NULL address)\n"));
+		dev_dbg(&device->dev, "No PBLK (NULL address)\n");
 	else if (object.processor.pblk_length != 6)
 		dev_err(&device->dev, "Invalid PBLK length [%d]\n",
 			    object.processor.pblk_length);
@@ -363,8 +416,6 @@ static int acpi_processor_get_info(struct acpi_device *device)
  * (cpu_data(cpu)) values, like CPU feature flags, family, model, etc.
  * Such things have to be put in and set up by the processor driver's .probe().
  */
-static DEFINE_PER_CPU(void *, processor_device_array);
-
 static int acpi_processor_add(struct acpi_device *device,
 					const struct acpi_device_id *id)
 {
@@ -372,6 +423,9 @@ static int acpi_processor_add(struct acpi_device *device,
 	struct device *dev;
 	int result = 0;
 
+	if (!acpi_device_is_enabled(device))
+		return -ENODEV;
+
 	pr = kzalloc(sizeof(struct acpi_processor), GFP_KERNEL);
 	if (!pr)
 		return -ENOMEM;
@@ -382,45 +436,23 @@ static int acpi_processor_add(struct acpi_device *device,
 	}
 
 	pr->handle = device->handle;
-	strcpy(acpi_device_name(device), ACPI_PROCESSOR_DEVICE_NAME);
-	strcpy(acpi_device_class(device), ACPI_PROCESSOR_CLASS);
+	strscpy(acpi_device_name(device), ACPI_PROCESSOR_DEVICE_NAME);
+	strscpy(acpi_device_class(device), ACPI_PROCESSOR_CLASS);
 	device->driver_data = pr;
 
 	result = acpi_processor_get_info(device);
 	if (result) /* Processor is not physically present or unavailable */
-		return 0;
-
-	BUG_ON(pr->id >= nr_cpu_ids);
-
-	/*
-	 * Buggy BIOS check.
-	 * ACPI id of processors can be reported wrongly by the BIOS.
-	 * Don't trust it blindly
-	 */
-	if (per_cpu(processor_device_array, pr->id) != NULL &&
-	    per_cpu(processor_device_array, pr->id) != device) {
-		dev_warn(&device->dev,
-			"BIOS reported wrong ACPI id %d for the processor\n",
-			pr->id);
-		/* Give up, but do not abort the namespace scan. */
-		goto err;
-	}
-	/*
-	 * processor_device_array is not cleared on errors to allow buggy BIOS
-	 * checks.
-	 */
-	per_cpu(processor_device_array, pr->id) = device;
-	per_cpu(processors, pr->id) = pr;
+		goto err_clear_driver_data;
 
 	dev = get_cpu_device(pr->id);
 	if (!dev) {
 		result = -ENODEV;
-		goto err;
+		goto err_clear_per_cpu;
 	}
 
 	result = acpi_bind_one(dev, device);
 	if (result)
-		goto err;
+		goto err_clear_per_cpu;
 
 	pr->dev = dev;
 
@@ -431,21 +463,19 @@ static int acpi_processor_add(struct acpi_device *device,
 	dev_err(dev, "Processor driver could not be attached\n");
 	acpi_unbind_one(dev);
 
- err:
-	free_cpumask_var(pr->throttling.shared_cpu_map);
-	device->driver_data = NULL;
+ err_clear_per_cpu:
 	per_cpu(processors, pr->id) = NULL;
+ err_clear_driver_data:
+	device->driver_data = NULL;
+	free_cpumask_var(pr->throttling.shared_cpu_map);
  err_free_pr:
 	kfree(pr);
 	return result;
 }
 
 #ifdef CONFIG_ACPI_HOTPLUG_CPU
-/* --------------------------------------------------------------------------
-                                    Removal
-   -------------------------------------------------------------------------- */
-
-static void acpi_processor_remove(struct acpi_device *device)
+/* Removal */
+static void acpi_processor_post_eject(struct acpi_device *device)
 {
 	struct acpi_processor *pr;
 
@@ -467,18 +497,18 @@ static void acpi_processor_remove(struct acpi_device *device)
 	device_release_driver(pr->dev);
 	acpi_unbind_one(pr->dev);
 
-	/* Clean up. */
-	per_cpu(processor_device_array, pr->id) = NULL;
-	per_cpu(processors, pr->id) = NULL;
-
 	cpu_maps_update_begin();
-	cpu_hotplug_begin();
+	cpus_write_lock();
 
 	/* Remove the CPU. */
 	arch_unregister_cpu(pr->id);
 	acpi_unmap_cpu(pr->id);
 
-	cpu_hotplug_done();
+	/* Clean up. */
+	per_cpu(processor_device_array, pr->id) = NULL;
+	per_cpu(processors, pr->id) = NULL;
+
+	cpus_write_unlock();
 	cpu_maps_update_done();
 
 	try_offline_node(cpu_to_node(pr->id));
@@ -489,54 +519,110 @@ static void acpi_processor_remove(struct acpi_device *device)
 }
 #endif /* CONFIG_ACPI_HOTPLUG_CPU */
 
-#ifdef CONFIG_X86
-static bool acpi_hwp_native_thermal_lvt_set;
-static acpi_status __init acpi_hwp_native_thermal_lvt_osc(acpi_handle handle,
-							  u32 lvl,
-							  void *context,
-							  void **rv)
+#ifdef CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC
+bool __init processor_physically_present(acpi_handle handle)
 {
-	u8 sb_uuid_str[] = "4077A616-290C-47BE-9EBD-D87058713953";
-	u32 capbuf[2];
+	int cpuid, type;
+	u32 acpi_id;
+	acpi_status status;
+	acpi_object_type acpi_type;
+	unsigned long long tmp;
+	union acpi_object object = {};
+	struct acpi_buffer buffer = { sizeof(union acpi_object), &object };
+
+	status = acpi_get_type(handle, &acpi_type);
+	if (ACPI_FAILURE(status))
+		return false;
+
+	switch (acpi_type) {
+	case ACPI_TYPE_PROCESSOR:
+		status = acpi_evaluate_object(handle, NULL, NULL, &buffer);
+		if (ACPI_FAILURE(status))
+			return false;
+		acpi_id = object.processor.proc_id;
+		break;
+	case ACPI_TYPE_DEVICE:
+		status = acpi_evaluate_integer(handle, METHOD_NAME__UID,
+					       NULL, &tmp);
+		if (ACPI_FAILURE(status))
+			return false;
+		acpi_id = tmp;
+		break;
+	default:
+		return false;
+	}
+
+	if (xen_initial_domain())
+		/*
+		 * When running as a Xen dom0 the number of processors Linux
+		 * sees can be different from the real number of processors on
+		 * the system, and we still need to execute _PDC or _OSC for
+		 * all of them.
+		 */
+		return xen_processor_present(acpi_id);
+
+	type = (acpi_type == ACPI_TYPE_DEVICE) ? 1 : 0;
+	cpuid = acpi_get_cpuid(handle, type, acpi_id);
+
+	return !invalid_logical_cpuid(cpuid);
+}
+
+/* vendor specific UUID indicating an Intel platform */
+static u8 sb_uuid_str[] = "4077A616-290C-47BE-9EBD-D87058713953";
+
+static acpi_status __init acpi_processor_osc(acpi_handle handle, u32 lvl,
+					     void *context, void **rv)
+{
+	u32 capbuf[2] = {};
 	struct acpi_osc_context osc_context = {
 		.uuid_str = sb_uuid_str,
 		.rev = 1,
 		.cap.length = 8,
 		.cap.pointer = capbuf,
 	};
+	acpi_status status;
 
-	if (acpi_hwp_native_thermal_lvt_set)
-		return AE_CTRL_TERMINATE;
+	if (!processor_physically_present(handle))
+		return AE_OK;
 
-	capbuf[0] = 0x0000;
-	capbuf[1] = 0x1000; /* set bit 12 */
+	arch_acpi_set_proc_cap_bits(&capbuf[OSC_SUPPORT_DWORD]);
 
-	if (ACPI_SUCCESS(acpi_run_osc(handle, &osc_context))) {
-		if (osc_context.ret.pointer && osc_context.ret.length > 1) {
-			u32 *capbuf_ret = osc_context.ret.pointer;
+	status = acpi_run_osc(handle, &osc_context);
+	if (ACPI_FAILURE(status))
+		return status;
 
-			if (capbuf_ret[1] & 0x1000) {
-				acpi_handle_info(handle,
-					"_OSC native thermal LVT Acked\n");
-				acpi_hwp_native_thermal_lvt_set = true;
-			}
-		}
-		kfree(osc_context.ret.pointer);
-	}
+	kfree(osc_context.ret.pointer);
 
 	return AE_OK;
 }
 
-void __init acpi_early_processor_osc(void)
+static bool __init acpi_early_processor_osc(void)
+{
+	acpi_status status;
+
+	acpi_proc_quirk_mwait_check();
+
+	status = acpi_walk_namespace(ACPI_TYPE_PROCESSOR, ACPI_ROOT_OBJECT,
+				     ACPI_UINT32_MAX, acpi_processor_osc, NULL,
+				     NULL, NULL);
+	if (ACPI_FAILURE(status))
+		return false;
+
+	status = acpi_get_devices(ACPI_PROCESSOR_DEVICE_HID, acpi_processor_osc,
+				  NULL, NULL);
+	if (ACPI_FAILURE(status))
+		return false;
+
+	return true;
+}
+
+void __init acpi_early_processor_control_setup(void)
 {
-	if (boot_cpu_has(X86_FEATURE_HWP)) {
-		acpi_walk_namespace(ACPI_TYPE_PROCESSOR, ACPI_ROOT_OBJECT,
-				    ACPI_UINT32_MAX,
-				    acpi_hwp_native_thermal_lvt_osc,
-				    NULL, NULL, NULL);
-		acpi_get_devices(ACPI_PROCESSOR_DEVICE_HID,
-				 acpi_hwp_native_thermal_lvt_osc,
-				 NULL, NULL);
+	if (acpi_early_processor_osc()) {
+		pr_debug("_OSC evaluated successfully for all CPUs\n");
+	} else {
+		pr_debug("_OSC evaluation for CPUs failed, trying _PDC\n");
+		acpi_early_processor_set_pdc();
 	}
 }
 #endif
@@ -557,7 +643,7 @@ static struct acpi_scan_handler processor_handler = {
 	.ids = processor_device_ids,
 	.attach = acpi_processor_add,
 #ifdef CONFIG_ACPI_HOTPLUG_CPU
-	.detach = acpi_processor_remove,
+	.post_eject = acpi_processor_post_eject,
 #endif
 	.hotplug = {
 		.enabled = true,
@@ -704,6 +790,7 @@ void __init acpi_processor_init(void)
 	acpi_processor_check_duplicates();
 	acpi_scan_add_handler_with_hotplug(&processor_handler, "processor");
 	acpi_scan_add_handler(&processor_container_handler);
+	acpi_pcc_cpufreq_init();
 }
 
 #ifdef CONFIG_ACPI_PROCESSOR_CSTATE
@@ -728,7 +815,7 @@ bool acpi_processor_claim_cst_control(void)
 	cst_control_claimed = true;
 	return true;
 }
-EXPORT_SYMBOL_GPL(acpi_processor_claim_cst_control);
+EXPORT_SYMBOL_NS_GPL(acpi_processor_claim_cst_control, "ACPI_PROCESSOR_IDLE");
 
 /**
  * acpi_processor_evaluate_cst - Evaluate the processor _CST control method.
@@ -798,22 +885,34 @@ int acpi_processor_evaluate_cst(acpi_handle handle, u32 cpu,
 		memset(&cx, 0, sizeof(cx));
 
 		element = &cst->package.elements[i];
-		if (element->type != ACPI_TYPE_PACKAGE)
+		if (element->type != ACPI_TYPE_PACKAGE) {
+			acpi_handle_info(handle, "_CST C%d type(%x) is not package, skip...\n",
+					 i, element->type);
 			continue;
+		}
 
-		if (element->package.count != 4)
+		if (element->package.count != 4) {
+			acpi_handle_info(handle, "_CST C%d package count(%d) is not 4, skip...\n",
+					 i, element->package.count);
 			continue;
+		}
 
 		obj = &element->package.elements[0];
 
-		if (obj->type != ACPI_TYPE_BUFFER)
+		if (obj->type != ACPI_TYPE_BUFFER) {
+			acpi_handle_info(handle, "_CST C%d package element[0] type(%x) is not buffer, skip...\n",
+					 i, obj->type);
 			continue;
+		}
 
 		reg = (struct acpi_power_register *)obj->buffer.pointer;
 
 		obj = &element->package.elements[1];
-		if (obj->type != ACPI_TYPE_INTEGER)
+		if (obj->type != ACPI_TYPE_INTEGER) {
+			acpi_handle_info(handle, "_CST C[%d] package element[1] type(%x) is not integer, skip...\n",
+					 i, obj->type);
 			continue;
+		}
 
 		cx.type = obj->integer.value;
 		/*
@@ -850,6 +949,8 @@ int acpi_processor_evaluate_cst(acpi_handle handle, u32 cpu,
 				cx.entry_method = ACPI_CSTATE_HALT;
 				snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT");
 			} else {
+				acpi_handle_info(handle, "_CST C%d declares FIXED_HARDWARE C-state but not supported in hardware, skip...\n",
+						 i);
 				continue;
 			}
 		} else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
@@ -857,6 +958,8 @@ int acpi_processor_evaluate_cst(acpi_handle handle, u32 cpu,
 			snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI IOPORT 0x%x",
 				 cx.address);
 		} else {
+			acpi_handle_info(handle, "_CST C%d space_id(%x) neither FIXED_HARDWARE nor SYSTEM_IO, skip...\n",
+					 i, reg->space_id);
 			continue;
 		}
 
@@ -864,26 +967,32 @@ int acpi_processor_evaluate_cst(acpi_handle handle, u32 cpu,
 			cx.valid = 1;
 
 		obj = &element->package.elements[2];
-		if (obj->type != ACPI_TYPE_INTEGER)
+		if (obj->type != ACPI_TYPE_INTEGER) {
+			acpi_handle_info(handle, "_CST C%d package element[2] type(%x) not integer, skip...\n",
+					 i, obj->type);
 			continue;
+		}
 
 		cx.latency = obj->integer.value;
 
 		obj = &element->package.elements[3];
-		if (obj->type != ACPI_TYPE_INTEGER)
+		if (obj->type != ACPI_TYPE_INTEGER) {
+			acpi_handle_info(handle, "_CST C%d package element[3] type(%x) not integer, skip...\n",
+					 i, obj->type);
 			continue;
+		}
 
 		memcpy(&info->states[++last_index], &cx, sizeof(cx));
 	}
 
-	acpi_handle_info(handle, "Found %d idle states\n", last_index);
+	acpi_handle_debug(handle, "Found %d idle states\n", last_index);
 
 	info->count = last_index;
 
-      end:
+end:
 	kfree(buffer.pointer);
 
 	return ret;
 }
-EXPORT_SYMBOL_GPL(acpi_processor_evaluate_cst);
+EXPORT_SYMBOL_NS_GPL(acpi_processor_evaluate_cst, "ACPI_PROCESSOR_IDLE");
 #endif /* CONFIG_ACPI_PROCESSOR_CSTATE */
diff --git a/drivers/acpi/acpi_tad.c b/drivers/acpi/acpi_tad.c
index 33a4bcdaa4d7..6d870d97ada6 100644
--- a/drivers/acpi/acpi_tad.c
+++ b/drivers/acpi/acpi_tad.c
@@ -27,6 +27,7 @@
 #include <linux/pm_runtime.h>
 #include <linux/suspend.h>
 
+MODULE_DESCRIPTION("ACPI Time and Alarm (TAD) Device Driver");
 MODULE_LICENSE("GPL v2");
 MODULE_AUTHOR("Rafael J. Wysocki");
 
@@ -89,19 +90,18 @@ static int acpi_tad_set_real_time(struct device *dev, struct acpi_tad_rt *rt)
 	args[0].buffer.pointer = (u8 *)rt;
 	args[0].buffer.length = sizeof(*rt);
 
-	pm_runtime_get_sync(dev);
+	PM_RUNTIME_ACQUIRE(dev, pm);
+	if (PM_RUNTIME_ACQUIRE_ERR(&pm))
+		return -ENXIO;
 
 	status = acpi_evaluate_integer(handle, "_SRT", &arg_list, &retval);
-
-	pm_runtime_put_sync(dev);
-
 	if (ACPI_FAILURE(status) || retval)
 		return -EIO;
 
 	return 0;
 }
 
-static int acpi_tad_get_real_time(struct device *dev, struct acpi_tad_rt *rt)
+static int acpi_tad_evaluate_grt(struct device *dev, struct acpi_tad_rt *rt)
 {
 	acpi_handle handle = ACPI_HANDLE(dev);
 	struct acpi_buffer output = { ACPI_ALLOCATE_BUFFER };
@@ -110,12 +110,7 @@ static int acpi_tad_get_real_time(struct device *dev, struct acpi_tad_rt *rt)
 	acpi_status status;
 	int ret = -EIO;
 
-	pm_runtime_get_sync(dev);
-
 	status = acpi_evaluate_object(handle, "_GRT", NULL, &output);
-
-	pm_runtime_put_sync(dev);
-
 	if (ACPI_FAILURE(status))
 		goto out_free;
 
@@ -138,6 +133,21 @@ out_free:
 	return ret;
 }
 
+static int acpi_tad_get_real_time(struct device *dev, struct acpi_tad_rt *rt)
+{
+	int ret;
+
+	PM_RUNTIME_ACQUIRE(dev, pm);
+	if (PM_RUNTIME_ACQUIRE_ERR(&pm))
+		return -ENXIO;
+
+	ret = acpi_tad_evaluate_grt(dev, rt);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
 static char *acpi_tad_rt_next_field(char *s, int *val)
 {
 	char *p;
@@ -232,12 +242,12 @@ static ssize_t time_show(struct device *dev, struct device_attribute *attr,
 	if (ret)
 		return ret;
 
-	return sprintf(buf, "%u:%u:%u:%u:%u:%u:%d:%u\n",
+	return sysfs_emit(buf, "%u:%u:%u:%u:%u:%u:%d:%u\n",
 		       rt.year, rt.month, rt.day, rt.hour, rt.minute, rt.second,
 		       rt.tz, rt.daylight);
 }
 
-static DEVICE_ATTR(time, S_IRUSR | S_IWUSR, time_show, time_store);
+static DEVICE_ATTR_RW(time);
 
 static struct attribute *acpi_tad_time_attrs[] = {
 	&dev_attr_time.attr,
@@ -265,12 +275,11 @@ static int acpi_tad_wake_set(struct device *dev, char *method, u32 timer_id,
 	args[0].integer.value = timer_id;
 	args[1].integer.value = value;
 
-	pm_runtime_get_sync(dev);
+	PM_RUNTIME_ACQUIRE(dev, pm);
+	if (PM_RUNTIME_ACQUIRE_ERR(&pm))
+		return -ENXIO;
 
 	status = acpi_evaluate_integer(handle, method, &arg_list, &retval);
-
-	pm_runtime_put_sync(dev);
-
 	if (ACPI_FAILURE(status) || retval)
 		return -EIO;
 
@@ -313,12 +322,11 @@ static ssize_t acpi_tad_wake_read(struct device *dev, char *buf, char *method,
 
 	args[0].integer.value = timer_id;
 
-	pm_runtime_get_sync(dev);
+	PM_RUNTIME_ACQUIRE(dev, pm);
+	if (PM_RUNTIME_ACQUIRE_ERR(&pm))
+		return -ENXIO;
 
 	status = acpi_evaluate_integer(handle, method, &arg_list, &retval);
-
-	pm_runtime_put_sync(dev);
-
 	if (ACPI_FAILURE(status))
 		return -EIO;
 
@@ -369,12 +377,11 @@ static int acpi_tad_clear_status(struct device *dev, u32 timer_id)
 
 	args[0].integer.value = timer_id;
 
-	pm_runtime_get_sync(dev);
+	PM_RUNTIME_ACQUIRE(dev, pm);
+	if (PM_RUNTIME_ACQUIRE_ERR(&pm))
+		return -ENXIO;
 
 	status = acpi_evaluate_integer(handle, "_CWS", &arg_list, &retval);
-
-	pm_runtime_put_sync(dev);
-
 	if (ACPI_FAILURE(status) || retval)
 		return -EIO;
 
@@ -410,12 +417,11 @@ static ssize_t acpi_tad_status_read(struct device *dev, char *buf, u32 timer_id)
 
 	args[0].integer.value = timer_id;
 
-	pm_runtime_get_sync(dev);
+	PM_RUNTIME_ACQUIRE(dev, pm);
+	if (PM_RUNTIME_ACQUIRE_ERR(&pm))
+		return -ENXIO;
 
 	status = acpi_evaluate_integer(handle, "_GWS", &arg_list, &retval);
-
-	pm_runtime_put_sync(dev);
-
 	if (ACPI_FAILURE(status))
 		return -EIO;
 
@@ -427,7 +433,7 @@ static ssize_t caps_show(struct device *dev, struct device_attribute *attr,
 {
 	struct acpi_tad_driver_data *dd = dev_get_drvdata(dev);
 
-	return sprintf(buf, "0x%02X\n", dd->capabilities);
+	return sysfs_emit(buf, "0x%02X\n", dd->capabilities);
 }
 
 static DEVICE_ATTR_RO(caps);
@@ -446,7 +452,7 @@ static ssize_t ac_alarm_show(struct device *dev, struct device_attribute *attr,
 	return acpi_tad_alarm_read(dev, buf, ACPI_TAD_AC_TIMER);
 }
 
-static DEVICE_ATTR(ac_alarm, S_IRUSR | S_IWUSR, ac_alarm_show, ac_alarm_store);
+static DEVICE_ATTR_RW(ac_alarm);
 
 static ssize_t ac_policy_store(struct device *dev, struct device_attribute *attr,
 			       const char *buf, size_t count)
@@ -462,7 +468,7 @@ static ssize_t ac_policy_show(struct device *dev, struct device_attribute *attr,
 	return acpi_tad_policy_read(dev, buf, ACPI_TAD_AC_TIMER);
 }
 
-static DEVICE_ATTR(ac_policy, S_IRUSR | S_IWUSR, ac_policy_show, ac_policy_store);
+static DEVICE_ATTR_RW(ac_policy);
 
 static ssize_t ac_status_store(struct device *dev, struct device_attribute *attr,
 			       const char *buf, size_t count)
@@ -478,7 +484,7 @@ static ssize_t ac_status_show(struct device *dev, struct device_attribute *attr,
 	return acpi_tad_status_read(dev, buf, ACPI_TAD_AC_TIMER);
 }
 
-static DEVICE_ATTR(ac_status, S_IRUSR | S_IWUSR, ac_status_show, ac_status_store);
+static DEVICE_ATTR_RW(ac_status);
 
 static struct attribute *acpi_tad_attrs[] = {
 	&dev_attr_caps.attr,
@@ -505,7 +511,7 @@ static ssize_t dc_alarm_show(struct device *dev, struct device_attribute *attr,
 	return acpi_tad_alarm_read(dev, buf, ACPI_TAD_DC_TIMER);
 }
 
-static DEVICE_ATTR(dc_alarm, S_IRUSR | S_IWUSR, dc_alarm_show, dc_alarm_store);
+static DEVICE_ATTR_RW(dc_alarm);
 
 static ssize_t dc_policy_store(struct device *dev, struct device_attribute *attr,
 			       const char *buf, size_t count)
@@ -521,7 +527,7 @@ static ssize_t dc_policy_show(struct device *dev, struct device_attribute *attr,
 	return acpi_tad_policy_read(dev, buf, ACPI_TAD_DC_TIMER);
 }
 
-static DEVICE_ATTR(dc_policy, S_IRUSR | S_IWUSR, dc_policy_show, dc_policy_store);
+static DEVICE_ATTR_RW(dc_policy);
 
 static ssize_t dc_status_store(struct device *dev, struct device_attribute *attr,
 			       const char *buf, size_t count)
@@ -537,7 +543,7 @@ static ssize_t dc_status_show(struct device *dev, struct device_attribute *attr,
 	return acpi_tad_status_read(dev, buf, ACPI_TAD_DC_TIMER);
 }
 
-static DEVICE_ATTR(dc_status, S_IRUSR | S_IWUSR, dc_status_show, dc_status_store);
+static DEVICE_ATTR_RW(dc_status);
 
 static struct attribute *acpi_tad_dc_attrs[] = {
 	&dev_attr_dc_alarm.attr,
@@ -554,30 +560,34 @@ static int acpi_tad_disable_timer(struct device *dev, u32 timer_id)
 	return acpi_tad_wake_set(dev, "_STV", timer_id, ACPI_TAD_WAKE_DISABLED);
 }
 
-static int acpi_tad_remove(struct platform_device *pdev)
+static void acpi_tad_remove(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
+	acpi_handle handle = ACPI_HANDLE(dev);
 	struct acpi_tad_driver_data *dd = dev_get_drvdata(dev);
 
 	device_init_wakeup(dev, false);
 
-	pm_runtime_get_sync(dev);
+	if (dd->capabilities & ACPI_TAD_RT)
+		sysfs_remove_group(&dev->kobj, &acpi_tad_time_attr_group);
 
 	if (dd->capabilities & ACPI_TAD_DC_WAKE)
 		sysfs_remove_group(&dev->kobj, &acpi_tad_dc_attr_group);
 
 	sysfs_remove_group(&dev->kobj, &acpi_tad_attr_group);
 
-	acpi_tad_disable_timer(dev, ACPI_TAD_AC_TIMER);
-	acpi_tad_clear_status(dev, ACPI_TAD_AC_TIMER);
-	if (dd->capabilities & ACPI_TAD_DC_WAKE) {
-		acpi_tad_disable_timer(dev, ACPI_TAD_DC_TIMER);
-		acpi_tad_clear_status(dev, ACPI_TAD_DC_TIMER);
+	scoped_guard(pm_runtime_noresume, dev) {
+		acpi_tad_disable_timer(dev, ACPI_TAD_AC_TIMER);
+		acpi_tad_clear_status(dev, ACPI_TAD_AC_TIMER);
+		if (dd->capabilities & ACPI_TAD_DC_WAKE) {
+			acpi_tad_disable_timer(dev, ACPI_TAD_DC_TIMER);
+			acpi_tad_clear_status(dev, ACPI_TAD_DC_TIMER);
+		}
 	}
 
-	pm_runtime_put_sync(dev);
+	pm_runtime_suspend(dev);
 	pm_runtime_disable(dev);
-	return 0;
+	acpi_remove_cmos_rtc_space_handler(handle);
 }
 
 static int acpi_tad_probe(struct platform_device *pdev)
@@ -589,6 +599,11 @@ static int acpi_tad_probe(struct platform_device *pdev)
 	unsigned long long caps;
 	int ret;
 
+	ret = acpi_install_cmos_rtc_space_handler(handle);
+	if (ret < 0) {
+		dev_info(dev, "Unable to install space handler\n");
+		return -ENODEV;
+	}
 	/*
 	 * Initialization failure messages are mostly about firmware issues, so
 	 * print them at the "info" level.
@@ -596,22 +611,27 @@ static int acpi_tad_probe(struct platform_device *pdev)
 	status = acpi_evaluate_integer(handle, "_GCP", NULL, &caps);
 	if (ACPI_FAILURE(status)) {
 		dev_info(dev, "Unable to get capabilities\n");
-		return -ENODEV;
+		ret = -ENODEV;
+		goto remove_handler;
 	}
 
 	if (!(caps & ACPI_TAD_AC_WAKE)) {
 		dev_info(dev, "Unsupported capabilities\n");
-		return -ENODEV;
+		ret = -ENODEV;
+		goto remove_handler;
 	}
 
 	if (!acpi_has_method(handle, "_PRW")) {
 		dev_info(dev, "Missing _PRW\n");
-		return -ENODEV;
+		ret = -ENODEV;
+		goto remove_handler;
 	}
 
 	dd = devm_kzalloc(dev, sizeof(*dd), GFP_KERNEL);
-	if (!dd)
-		return -ENOMEM;
+	if (!dd) {
+		ret = -ENOMEM;
+		goto remove_handler;
+	}
 
 	dd->capabilities = caps;
 	dev_set_drvdata(dev, dd);
@@ -624,7 +644,7 @@ static int acpi_tad_probe(struct platform_device *pdev)
 	 */
 	device_init_wakeup(dev, true);
 	dev_pm_set_driver_flags(dev, DPM_FLAG_SMART_SUSPEND |
-				     DPM_FLAG_LEAVE_SUSPENDED);
+				     DPM_FLAG_MAY_SKIP_RESUME);
 	/*
 	 * The platform bus type layer tells the ACPI PM domain powers up the
 	 * device, so set the runtime PM status of it to "active".
@@ -653,6 +673,11 @@ static int acpi_tad_probe(struct platform_device *pdev)
 
 fail:
 	acpi_tad_remove(pdev);
+	/* Don't fallthrough because cmos rtc space handler is removed in acpi_tad_remove() */
+	return ret;
+
+remove_handler:
+	acpi_remove_cmos_rtc_space_handler(handle);
 	return ret;
 }
 
diff --git a/drivers/acpi/acpi_video.c b/drivers/acpi/acpi_video.c
index bc96457c9e25..be8e7e18abca 100644
--- a/drivers/acpi/acpi_video.c
+++ b/drivers/acpi/acpi_video.c
@@ -7,6 +7,8 @@
  *  Copyright (C) 2006 Thomas Tuttle <linux-kernel@ttuttle.net>
  */
 
+#define pr_fmt(fmt) "ACPI: video: " fmt
+
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/init.h>
@@ -25,17 +27,13 @@
 #include <linux/acpi.h>
 #include <acpi/video.h>
 #include <linux/uaccess.h>
-
-#define PREFIX "ACPI: "
+#include <linux/string_choices.h>
 
 #define ACPI_VIDEO_BUS_NAME		"Video Bus"
 #define ACPI_VIDEO_DEVICE_NAME		"Video Device"
 
 #define MAX_NAME_LEN	20
 
-#define _COMPONENT		ACPI_VIDEO_COMPONENT
-ACPI_MODULE_NAME("video");
-
 MODULE_AUTHOR("Bruno Ducrot");
 MODULE_DESCRIPTION("ACPI Video Driver");
 MODULE_LICENSE("GPL");
@@ -50,9 +48,6 @@ module_param(brightness_switch_enabled, bool, 0644);
 static bool allow_duplicates;
 module_param(allow_duplicates, bool, 0644);
 
-static int disable_backlight_sysfs_if = -1;
-module_param(disable_backlight_sysfs_if, int, 0444);
-
 #define REPORT_OUTPUT_KEY_EVENTS		0x01
 #define REPORT_BRIGHTNESS_KEY_EVENTS		0x02
 static int report_key_events = -1;
@@ -73,17 +68,17 @@ MODULE_PARM_DESC(hw_changes_brightness,
 static bool device_id_scheme = false;
 module_param(device_id_scheme, bool, 0444);
 
-static int only_lcd = -1;
+static int only_lcd;
 module_param(only_lcd, int, 0444);
 
+static bool may_report_brightness_keys;
 static int register_count;
 static DEFINE_MUTEX(register_count_mutex);
 static DEFINE_MUTEX(video_list_lock);
 static LIST_HEAD(video_bus_head);
 static int acpi_video_bus_add(struct acpi_device *device);
-static int acpi_video_bus_remove(struct acpi_device *device);
-static void acpi_video_bus_notify(struct acpi_device *device, u32 event);
-void acpi_video_detect_exit(void);
+static void acpi_video_bus_remove(struct acpi_device *device);
+static void acpi_video_bus_notify(acpi_handle handle, u32 event, void *data);
 
 /*
  * Indices in the _BCL method response: the first two items are special,
@@ -110,7 +105,6 @@ static struct acpi_driver acpi_video_bus = {
 	.ops = {
 		.add = acpi_video_bus_add,
 		.remove = acpi_video_bus_remove,
-		.notify = acpi_video_bus_notify,
 		},
 };
 
@@ -260,8 +254,7 @@ static const struct backlight_ops acpi_backlight_ops = {
 static int video_get_max_state(struct thermal_cooling_device *cooling_dev,
 			       unsigned long *state)
 {
-	struct acpi_device *device = cooling_dev->devdata;
-	struct acpi_video_device *video = acpi_driver_data(device);
+	struct acpi_video_device *video = cooling_dev->devdata;
 
 	*state = video->brightness->count - ACPI_VIDEO_FIRST_LEVEL - 1;
 	return 0;
@@ -270,8 +263,7 @@ static int video_get_max_state(struct thermal_cooling_device *cooling_dev,
 static int video_get_cur_state(struct thermal_cooling_device *cooling_dev,
 			       unsigned long *state)
 {
-	struct acpi_device *device = cooling_dev->devdata;
-	struct acpi_video_device *video = acpi_driver_data(device);
+	struct acpi_video_device *video = cooling_dev->devdata;
 	unsigned long long level;
 	int offset;
 
@@ -290,8 +282,7 @@ static int video_get_cur_state(struct thermal_cooling_device *cooling_dev,
 static int
 video_set_cur_state(struct thermal_cooling_device *cooling_dev, unsigned long state)
 {
-	struct acpi_device *device = cooling_dev->devdata;
-	struct acpi_video_device *video = acpi_driver_data(device);
+	struct acpi_video_device *video = cooling_dev->devdata;
 	int level;
 
 	if (state >= video->brightness->count - ACPI_VIDEO_FIRST_LEVEL)
@@ -326,11 +317,11 @@ acpi_video_device_lcd_query_levels(acpi_handle handle,
 	*levels = NULL;
 
 	status = acpi_evaluate_object(handle, "_BCL", NULL, &buffer);
-	if (!ACPI_SUCCESS(status))
+	if (ACPI_FAILURE(status))
 		return status;
 	obj = (union acpi_object *)buffer.pointer;
 	if (!obj || (obj->type != ACPI_TYPE_PACKAGE)) {
-		printk(KERN_ERR PREFIX "Invalid _BCL data\n");
+		acpi_handle_info(handle, "Invalid _BCL data\n");
 		status = -EFAULT;
 		goto err;
 	}
@@ -354,7 +345,7 @@ acpi_video_device_lcd_set_level(struct acpi_video_device *device, int level)
 	status = acpi_execute_simple_method(device->dev->handle,
 					    "_BCM", level);
 	if (ACPI_FAILURE(status)) {
-		ACPI_ERROR((AE_INFO, "Evaluating _BCM failed"));
+		acpi_handle_info(device->dev->handle, "_BCM evaluation failed\n");
 		return -EIO;
 	}
 
@@ -368,7 +359,7 @@ acpi_video_device_lcd_set_level(struct acpi_video_device *device, int level)
 			return 0;
 		}
 
-	ACPI_ERROR((AE_INFO, "Current brightness invalid"));
+	acpi_handle_info(device->dev->handle, "Current brightness invalid\n");
 	return -EINVAL;
 }
 
@@ -384,14 +375,6 @@ static int video_set_bqc_offset(const struct dmi_system_id *d)
 	return 0;
 }
 
-static int video_disable_backlight_sysfs_if(
-	const struct dmi_system_id *d)
-{
-	if (disable_backlight_sysfs_if == -1)
-		disable_backlight_sysfs_if = 1;
-	return 0;
-}
-
 static int video_set_device_id_scheme(const struct dmi_system_id *d)
 {
 	device_id_scheme = true;
@@ -465,40 +448,6 @@ static const struct dmi_system_id video_dmi_table[] = {
 	},
 
 	/*
-	 * Some machines have a broken acpi-video interface for brightness
-	 * control, but still need an acpi_video_device_lcd_set_level() call
-	 * on resume to turn the backlight power on.  We Enable backlight
-	 * control on these systems, but do not register a backlight sysfs
-	 * as brightness control does not work.
-	 */
-	{
-	 /* https://bugzilla.kernel.org/show_bug.cgi?id=21012 */
-	 .callback = video_disable_backlight_sysfs_if,
-	 .ident = "Toshiba Portege R700",
-	 .matches = {
-		DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
-		DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE R700"),
-		},
-	},
-	{
-	 /* https://bugs.freedesktop.org/show_bug.cgi?id=82634 */
-	 .callback = video_disable_backlight_sysfs_if,
-	 .ident = "Toshiba Portege R830",
-	 .matches = {
-		DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
-		DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE R830"),
-		},
-	},
-	{
-	 /* https://bugzilla.kernel.org/show_bug.cgi?id=21012 */
-	 .callback = video_disable_backlight_sysfs_if,
-	 .ident = "Toshiba Satellite R830",
-	 .matches = {
-		DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
-		DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE R830"),
-		},
-	},
-	/*
 	 * Some machine's _DOD IDs don't have bit 31(Device ID Scheme) set
 	 * but the IDs actually follow the Device ID Scheme.
 	 */
@@ -543,6 +492,24 @@ static const struct dmi_system_id video_dmi_table[] = {
 		DMI_MATCH(DMI_PRODUCT_NAME, "Vostro V131"),
 		},
 	},
+	{
+	 .callback = video_set_report_key_events,
+	 .driver_data = (void *)((uintptr_t)REPORT_BRIGHTNESS_KEY_EVENTS),
+	 .ident = "Dell Vostro 3350",
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
+		DMI_MATCH(DMI_PRODUCT_NAME, "Vostro 3350"),
+		},
+	},
+	{
+	 .callback = video_set_report_key_events,
+	 .driver_data = (void *)((uintptr_t)REPORT_BRIGHTNESS_KEY_EVENTS),
+	 .ident = "COLORFUL X15 AT 23",
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "COLORFUL"),
+		DMI_MATCH(DMI_PRODUCT_NAME, "X15 AT 23"),
+		},
+	},
 	/*
 	 * Some machines change the brightness themselves when a brightness
 	 * hotkey gets pressed, despite us telling them not to. In this case
@@ -578,7 +545,7 @@ acpi_video_bqc_value_to_level(struct acpi_video_device *device,
 				ACPI_VIDEO_FIRST_LEVEL - 1 - bqc_value;
 
 		level = device->brightness->levels[bqc_value +
-		                                   ACPI_VIDEO_FIRST_LEVEL];
+						   ACPI_VIDEO_FIRST_LEVEL];
 	} else {
 		level = bqc_value;
 	}
@@ -622,9 +589,8 @@ acpi_video_device_lcd_get_level_current(struct acpi_video_device *device,
 			 * BQC returned an invalid level.
 			 * Stop using it.
 			 */
-			ACPI_WARNING((AE_INFO,
-				      "%s returned an invalid level",
-				      buf));
+			acpi_handle_info(device->dev->handle,
+					 "%s returned an invalid level", buf);
 			device->cap._BQC = device->cap._BCQ = 0;
 		} else {
 			/*
@@ -635,7 +601,8 @@ acpi_video_device_lcd_get_level_current(struct acpi_video_device *device,
 			 * ACPI video backlight still works w/ buggy _BQC.
 			 * http://bugzilla.kernel.org/show_bug.cgi?id=12233
 			 */
-			ACPI_WARNING((AE_INFO, "Evaluating %s failed", buf));
+			acpi_handle_info(device->dev->handle,
+					 "%s evaluation failed", buf);
 			device->cap._BQC = device->cap._BCQ = 0;
 		}
 	}
@@ -644,43 +611,62 @@ acpi_video_device_lcd_get_level_current(struct acpi_video_device *device,
 	return 0;
 }
 
+/**
+ * acpi_video_device_EDID() - Get EDID from ACPI _DDC
+ * @device: video output device (LCD, CRT, ..)
+ * @edid: address for returned EDID pointer
+ * @length: _DDC length to request (must be a multiple of 128)
+ *
+ * Get EDID from ACPI _DDC. On success, a pointer to the EDID data is written
+ * to the @edid address, and the length of the EDID is returned. The caller is
+ * responsible for freeing the edid pointer.
+ *
+ * Return the length of EDID (positive value) on success or error (negative
+ * value).
+ */
 static int
-acpi_video_device_EDID(struct acpi_video_device *device,
-		       union acpi_object **edid, ssize_t length)
+acpi_video_device_EDID(struct acpi_video_device *device, void **edid, int length)
 {
-	int status;
+	acpi_status status;
 	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
 	union acpi_object *obj;
 	union acpi_object arg0 = { ACPI_TYPE_INTEGER };
 	struct acpi_object_list args = { 1, &arg0 };
-
+	int ret;
 
 	*edid = NULL;
 
 	if (!device)
 		return -ENODEV;
-	if (length == 128)
-		arg0.integer.value = 1;
-	else if (length == 256)
-		arg0.integer.value = 2;
-	else
+	if (!length || (length % 128))
 		return -EINVAL;
 
+	arg0.integer.value = length / 128;
+
 	status = acpi_evaluate_object(device->dev->handle, "_DDC", &args, &buffer);
 	if (ACPI_FAILURE(status))
 		return -ENODEV;
 
 	obj = buffer.pointer;
 
-	if (obj && obj->type == ACPI_TYPE_BUFFER)
-		*edid = obj;
-	else {
-		printk(KERN_ERR PREFIX "Invalid _DDC data\n");
-		status = -EFAULT;
-		kfree(obj);
+	/*
+	 * Some buggy implementations incorrectly return the EDID buffer in an ACPI package.
+	 * In this case, extract the buffer from the package.
+	 */
+	if (obj && obj->type == ACPI_TYPE_PACKAGE && obj->package.count == 1)
+		obj = &obj->package.elements[0];
+
+	if (obj && obj->type == ACPI_TYPE_BUFFER) {
+		*edid = kmemdup(obj->buffer.pointer, obj->buffer.length, GFP_KERNEL);
+		ret = *edid ? obj->buffer.length : -ENOMEM;
+	} else {
+		acpi_handle_debug(device->dev->handle,
+				 "Invalid _DDC data for length %d\n", length);
+		ret = -EFAULT;
 	}
 
-	return status;
+	kfree(buffer.pointer);
+	return ret;
 }
 
 /* bus */
@@ -827,10 +813,9 @@ int acpi_video_get_levels(struct acpi_device *device,
 	int result = 0;
 	u32 value;
 
-	if (!ACPI_SUCCESS(acpi_video_device_lcd_query_levels(device->handle,
-								&obj))) {
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Could not query available "
-						"LCD brightness level\n"));
+	if (ACPI_FAILURE(acpi_video_device_lcd_query_levels(device->handle, &obj))) {
+		acpi_handle_debug(device->handle,
+				  "Could not query available LCD brightness level\n");
 		result = -ENODEV;
 		goto out;
 	}
@@ -842,7 +827,6 @@ int acpi_video_get_levels(struct acpi_device *device,
 
 	br = kzalloc(sizeof(*br), GFP_KERNEL);
 	if (!br) {
-		printk(KERN_ERR "can't allocate memory\n");
 		result = -ENOMEM;
 		goto out;
 	}
@@ -863,7 +847,7 @@ int acpi_video_get_levels(struct acpi_device *device,
 	for (i = 0; i < obj->package.count; i++) {
 		o = (union acpi_object *)&obj->package.elements[i];
 		if (o->type != ACPI_TYPE_INTEGER) {
-			printk(KERN_ERR PREFIX "Invalid data\n");
+			acpi_handle_info(device->handle, "Invalid data\n");
 			continue;
 		}
 		value = (u32) o->integer.value;
@@ -900,7 +884,8 @@ int acpi_video_get_levels(struct acpi_device *device,
 			br->levels[i] = br->levels[i - level_ac_battery];
 		count += level_ac_battery;
 	} else if (level_ac_battery > ACPI_VIDEO_FIRST_LEVEL)
-		ACPI_ERROR((AE_INFO, "Too many duplicates in _BCL package"));
+		acpi_handle_info(device->handle,
+				 "Too many duplicates in _BCL package");
 
 	/* Check if the _BCL package is in a reversed order */
 	if (max_level == br->levels[ACPI_VIDEO_FIRST_LEVEL]) {
@@ -910,8 +895,8 @@ int acpi_video_get_levels(struct acpi_device *device,
 		     sizeof(br->levels[ACPI_VIDEO_FIRST_LEVEL]),
 		     acpi_video_cmp_level, NULL);
 	} else if (max_level != br->levels[count - 1])
-		ACPI_ERROR((AE_INFO,
-			    "Found unordered _BCL package"));
+		acpi_handle_info(device->handle,
+				 "Found unordered _BCL package");
 
 	br->count = count;
 	*dev_br = br;
@@ -989,9 +974,9 @@ set_level:
 	if (result)
 		goto out_free_levels;
 
-	ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-	                  "found %d brightness levels\n",
-	                  br->count - ACPI_VIDEO_FIRST_LEVEL));
+	acpi_handle_debug(device->dev->handle, "found %d brightness levels\n",
+			  br->count - ACPI_VIDEO_FIRST_LEVEL);
+
 	return 0;
 
 out_free_levels:
@@ -1023,7 +1008,8 @@ static void acpi_video_device_find_cap(struct acpi_video_device *device)
 	if (acpi_has_method(device->dev->handle, "_BQC")) {
 		device->cap._BQC = 1;
 	} else if (acpi_has_method(device->dev->handle, "_BCQ")) {
-		printk(KERN_WARNING FW_BUG "_BCQ is used instead of _BQC\n");
+		acpi_handle_info(device->dev->handle,
+				 "_BCQ is used instead of _BQC\n");
 		device->cap._BCQ = 1;
 	}
 
@@ -1083,8 +1069,7 @@ static int acpi_video_bus_check(struct acpi_video_bus *video)
 	/* Does this device support video switching? */
 	if (video->cap._DOS || video->cap._DOD) {
 		if (!video->cap._DOS) {
-			printk(KERN_WARNING FW_BUG
-				"ACPI(%s) defines _DOD but not _DOS\n",
+			pr_info(FW_BUG "ACPI(%s) defines _DOD but not _DOS\n",
 				acpi_device_bid(video->device));
 		}
 		video->flags.multihead = 1;
@@ -1144,28 +1129,28 @@ acpi_video_get_device_type(struct acpi_video_bus *video,
 	return 0;
 }
 
-static int
-acpi_video_bus_get_one_device(struct acpi_device *device,
-			      struct acpi_video_bus *video)
+static int acpi_video_bus_get_one_device(struct acpi_device *device, void *arg)
 {
-	unsigned long long device_id;
-	int status, device_type;
-	struct acpi_video_device *data;
+	struct acpi_video_bus *video = arg;
 	struct acpi_video_device_attrib *attribute;
+	struct acpi_video_device *data;
+	unsigned long long device_id;
+	acpi_status status;
+	int device_type;
 
-	status =
-	    acpi_evaluate_integer(device->handle, "_ADR", NULL, &device_id);
-	/* Some device omits _ADR, we skip them instead of fail */
+	status = acpi_evaluate_integer(device->handle, "_ADR", NULL, &device_id);
+	/* Skip devices without _ADR instead of failing. */
 	if (ACPI_FAILURE(status))
-		return 0;
+		goto exit;
 
 	data = kzalloc(sizeof(struct acpi_video_device), GFP_KERNEL);
-	if (!data)
+	if (!data) {
+		dev_dbg(&device->dev, "Cannot attach\n");
 		return -ENOMEM;
+	}
 
-	strcpy(acpi_device_name(device), ACPI_VIDEO_DEVICE_NAME);
-	strcpy(acpi_device_class(device), ACPI_VIDEO_CLASS);
-	device->driver_data = data;
+	strscpy(acpi_device_name(device), ACPI_VIDEO_DEVICE_NAME);
+	strscpy(acpi_device_class(device), ACPI_VIDEO_CLASS);
 
 	data->device_id = device_id;
 	data->video = video;
@@ -1217,11 +1202,16 @@ acpi_video_bus_get_one_device(struct acpi_device *device,
 	acpi_video_device_bind(video, data);
 	acpi_video_device_find_cap(data);
 
+	if (data->cap._BCM && data->cap._BCL)
+		may_report_brightness_keys = true;
+
 	mutex_lock(&video->device_list_lock);
 	list_add_tail(&data->entry, &video->video_device_list);
 	mutex_unlock(&video->device_list_lock);
 
-	return status;
+exit:
+	video->child_count++;
+	return 0;
 }
 
 /*
@@ -1272,7 +1262,8 @@ acpi_video_device_bind(struct acpi_video_bus *video,
 		ids = &video->attached_array[i];
 		if (device->device_id == (ids->value.int_val & 0xffff)) {
 			ids->bind_info = device;
-			ACPI_DEBUG_PRINT((ACPI_DB_INFO, "device_bind %d\n", i));
+			acpi_handle_debug(video->device->handle, "%s: %d\n",
+					  __func__, i);
 		}
 	}
 }
@@ -1324,20 +1315,22 @@ static int acpi_video_device_enumerate(struct acpi_video_bus *video)
 		return AE_NOT_EXIST;
 
 	status = acpi_evaluate_object(video->device->handle, "_DOD", NULL, &buffer);
-	if (!ACPI_SUCCESS(status)) {
-		ACPI_EXCEPTION((AE_INFO, status, "Evaluating _DOD"));
+	if (ACPI_FAILURE(status)) {
+		acpi_handle_info(video->device->handle,
+				 "_DOD evaluation failed: %s\n",
+				 acpi_format_exception(status));
 		return status;
 	}
 
 	dod = buffer.pointer;
 	if (!dod || (dod->type != ACPI_TYPE_PACKAGE)) {
-		ACPI_EXCEPTION((AE_INFO, status, "Invalid _DOD data"));
+		acpi_handle_info(video->device->handle, "Invalid _DOD data\n");
 		status = -EFAULT;
 		goto out;
 	}
 
-	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found %d video heads in _DOD\n",
-			  dod->package.count));
+	acpi_handle_debug(video->device->handle, "Found %d video heads in _DOD\n",
+			  dod->package.count);
 
 	active_list = kcalloc(1 + dod->package.count,
 			      sizeof(struct acpi_video_enumerated_device),
@@ -1352,15 +1345,18 @@ static int acpi_video_device_enumerate(struct acpi_video_bus *video)
 		obj = &dod->package.elements[i];
 
 		if (obj->type != ACPI_TYPE_INTEGER) {
-			printk(KERN_ERR PREFIX
-				"Invalid _DOD data in element %d\n", i);
+			acpi_handle_info(video->device->handle,
+					 "Invalid _DOD data in element %d\n", i);
 			continue;
 		}
 
 		active_list[count].value.int_val = obj->integer.value;
 		active_list[count].bind_info = NULL;
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "dod element[%d] = %d\n", i,
-				  (int)obj->integer.value));
+
+		acpi_handle_debug(video->device->handle,
+				  "_DOD element[%d] = %d\n", i,
+				  (int)obj->integer.value);
+
 		count++;
 	}
 
@@ -1390,7 +1386,7 @@ acpi_video_get_next_level(struct acpi_video_device *device,
 				break;
 		}
 	}
-	/* Ajust level_current to closest available level */
+	/* Adjust level_current to closest available level */
 	level_current += delta;
 	for (i = ACPI_VIDEO_FIRST_LEVEL; i < device->brightness->count; i++) {
 		l = device->brightness->levels[i];
@@ -1451,7 +1447,8 @@ acpi_video_switch_brightness(struct work_struct *work)
 
 out:
 	if (result)
-		printk(KERN_ERR PREFIX "Failed to switch the brightness\n");
+		acpi_handle_info(device->dev->handle,
+				 "Failed to switch brightness\n");
 }
 
 int acpi_video_get_edid(struct acpi_device *device, int type, int device_id,
@@ -1459,9 +1456,7 @@ int acpi_video_get_edid(struct acpi_device *device, int type, int device_id,
 {
 	struct acpi_video_bus *video;
 	struct acpi_video_device *video_device;
-	union acpi_object *buffer = NULL;
-	acpi_status status;
-	int i, length;
+	int i, length, ret;
 
 	if (!device || !acpi_driver_data(device))
 		return -EINVAL;
@@ -1470,7 +1465,6 @@ int acpi_video_get_edid(struct acpi_device *device, int type, int device_id,
 
 	for (i = 0; i < video->attached_count; i++) {
 		video_device = video->attached_array[i].bind_info;
-		length = 256;
 
 		if (!video_device)
 			continue;
@@ -1501,21 +1495,11 @@ int acpi_video_get_edid(struct acpi_device *device, int type, int device_id,
 			continue;
 		}
 
-		status = acpi_video_device_EDID(video_device, &buffer, length);
-
-		if (ACPI_FAILURE(status) || !buffer ||
-		    buffer->type != ACPI_TYPE_BUFFER) {
-			length = 128;
-			status = acpi_video_device_EDID(video_device, &buffer,
-							length);
-			if (ACPI_FAILURE(status) || !buffer ||
-			    buffer->type != ACPI_TYPE_BUFFER) {
-				continue;
-			}
+		for (length = 512; length > 0; length -= 128) {
+			ret = acpi_video_device_EDID(video_device, edid, length);
+			if (ret > 0)
+				return ret;
 		}
-
-		*edid = buffer->buffer.pointer;
-		return length;
 	}
 
 	return -ENODEV;
@@ -1526,9 +1510,6 @@ static int
 acpi_video_bus_get_devices(struct acpi_video_bus *video,
 			   struct acpi_device *device)
 {
-	int status = 0;
-	struct acpi_device *dev;
-
 	/*
 	 * There are systems where video module known to work fine regardless
 	 * of broken _DOD and ignoring returned value here doesn't cause
@@ -1536,23 +1517,14 @@ acpi_video_bus_get_devices(struct acpi_video_bus *video,
 	 */
 	acpi_video_device_enumerate(video);
 
-	list_for_each_entry(dev, &device->children, node) {
-
-		status = acpi_video_bus_get_one_device(dev, video);
-		if (status) {
-			dev_err(&dev->dev, "Can't attach device\n");
-			break;
-		}
-		video->child_count++;
-	}
-	return status;
+	return acpi_dev_for_each_child(device, acpi_video_bus_get_one_device, video);
 }
 
 /* acpi_video interface */
 
 /*
  * Win8 requires setting bit2 of _DOS to let firmware know it shouldn't
- * preform any automatic brightness change on receiving a notification.
+ * perform any automatic brightness change on receiving a notification.
  */
 static int acpi_video_bus_start_devices(struct acpi_video_bus *video)
 {
@@ -1566,8 +1538,9 @@ static int acpi_video_bus_stop_devices(struct acpi_video_bus *video)
 				  acpi_osi_is_win8() ? 0 : 1);
 }
 
-static void acpi_video_bus_notify(struct acpi_device *device, u32 event)
+static void acpi_video_bus_notify(acpi_handle handle, u32 event, void *data)
 {
+	struct acpi_device *device = data;
 	struct acpi_video_bus *video = acpi_driver_data(device);
 	struct input_dev *input;
 	int keycode = 0;
@@ -1601,8 +1574,8 @@ static void acpi_video_bus_notify(struct acpi_device *device, u32 event)
 		break;
 
 	default:
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-				  "Unsupported event [0x%x]\n", event));
+		acpi_handle_debug(device->handle, "Unsupported event [0x%x]\n",
+				  event);
 		break;
 	}
 
@@ -1616,8 +1589,6 @@ static void acpi_video_bus_notify(struct acpi_device *device, u32 event)
 		input_report_key(input, keycode, 0);
 		input_sync(input);
 	}
-
-	return;
 }
 
 static void brightness_switch_event(struct acpi_video_device *video_device,
@@ -1675,11 +1646,13 @@ static void acpi_video_device_notify(acpi_handle handle, u32 event, void *data)
 		keycode = KEY_DISPLAY_OFF;
 		break;
 	default:
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-				  "Unsupported event [0x%x]\n", event));
+		acpi_handle_debug(handle, "Unsupported event [0x%x]\n", event);
 		break;
 	}
 
+	if (keycode)
+		may_report_brightness_keys = true;
+
 	acpi_notifier_call_chain(device, event, 0);
 
 	if (keycode && (report_key_events & REPORT_BRIGHTNESS_KEY_EVENTS)) {
@@ -1688,8 +1661,6 @@ static void acpi_video_device_notify(acpi_handle handle, u32 event, void *data)
 		input_report_key(input, keycode, 0);
 		input_sync(input);
 	}
-
-	return;
 }
 
 static int acpi_video_resume(struct notifier_block *nb,
@@ -1700,24 +1671,23 @@ static int acpi_video_resume(struct notifier_block *nb,
 	int i;
 
 	switch (val) {
-	case PM_HIBERNATION_PREPARE:
-	case PM_SUSPEND_PREPARE:
-	case PM_RESTORE_PREPARE:
-		return NOTIFY_DONE;
-	}
-
-	video = container_of(nb, struct acpi_video_bus, pm_nb);
-
-	dev_info(&video->device->dev, "Restoring backlight state\n");
+	case PM_POST_HIBERNATION:
+	case PM_POST_SUSPEND:
+	case PM_POST_RESTORE:
+		video = container_of(nb, struct acpi_video_bus, pm_nb);
+
+		dev_info(&video->device->dev, "Restoring backlight state\n");
+
+		for (i = 0; i < video->attached_count; i++) {
+			video_device = video->attached_array[i].bind_info;
+			if (video_device && video_device->brightness)
+				acpi_video_device_lcd_set_level(video_device,
+						video_device->brightness->curr);
+		}
 
-	for (i = 0; i < video->attached_count; i++) {
-		video_device = video->attached_array[i].bind_info;
-		if (video_device && video_device->brightness)
-			acpi_video_device_lcd_set_level(video_device,
-					video_device->brightness->curr);
+		return NOTIFY_OK;
 	}
-
-	return NOTIFY_OK;
+	return NOTIFY_DONE;
 }
 
 static acpi_status
@@ -1726,13 +1696,12 @@ acpi_video_bus_match(acpi_handle handle, u32 level, void *context,
 {
 	struct acpi_device *device = context;
 	struct acpi_device *sibling;
-	int result;
 
 	if (handle == device->handle)
 		return AE_CTRL_TERMINATE;
 
-	result = acpi_bus_get_device(handle, &sibling);
-	if (result)
+	sibling = acpi_fetch_acpi_dev(handle);
+	if (!sibling)
 		return AE_OK;
 
 	if (!strcmp(acpi_device_name(sibling), ACPI_VIDEO_BUS_NAME))
@@ -1755,20 +1724,17 @@ static void acpi_video_dev_register_backlight(struct acpi_video_device *device)
 	if (result)
 		return;
 
-	if (disable_backlight_sysfs_if > 0)
-		return;
-
 	name = kasprintf(GFP_KERNEL, "acpi_video%d", count);
 	if (!name)
 		return;
 	count++;
 
-	acpi_get_parent(device->dev->handle, &acpi_parent);
-
-	pdev = acpi_get_pci_dev(acpi_parent);
-	if (pdev) {
-		parent = &pdev->dev;
-		pci_dev_put(pdev);
+	if (ACPI_SUCCESS(acpi_get_parent(device->dev->handle, &acpi_parent))) {
+		pdev = acpi_get_pci_dev(acpi_parent);
+		if (pdev) {
+			parent = &pdev->dev;
+			pci_dev_put(pdev);
+		}
 	}
 
 	memset(&props, 0, sizeof(struct backlight_properties));
@@ -1793,8 +1759,8 @@ static void acpi_video_dev_register_backlight(struct acpi_video_device *device)
 	device->backlight->props.brightness =
 			acpi_video_get_brightness(device->backlight);
 
-	device->cooling_dev = thermal_cooling_device_register("LCD",
-				device->dev, &video_cooling_ops);
+	device->cooling_dev = thermal_cooling_device_register("LCD", device,
+							      &video_cooling_ops);
 	if (IS_ERR(device->cooling_dev)) {
 		/*
 		 * Set cooling_dev to NULL so we don't crash trying to free it.
@@ -1812,11 +1778,12 @@ static void acpi_video_dev_register_backlight(struct acpi_video_device *device)
 			&device->cooling_dev->device.kobj,
 			"thermal_cooling");
 	if (result)
-		printk(KERN_ERR PREFIX "Create sysfs link\n");
+		pr_info("sysfs link creation failed\n");
+
 	result = sysfs_create_link(&device->cooling_dev->device.kobj,
 			&device->dev->dev.kobj, "device");
 	if (result)
-		printk(KERN_ERR PREFIX "Create sysfs link\n");
+		pr_info("Reverse sysfs link creation failed\n");
 }
 
 static void acpi_video_run_bcl_for_osi(struct acpi_video_bus *video)
@@ -1855,8 +1822,6 @@ static int acpi_video_bus_register_backlight(struct acpi_video_bus *video)
 	if (video->backlight_registered)
 		return 0;
 
-	acpi_video_run_bcl_for_osi(video);
-
 	if (acpi_video_get_backlight_type() != acpi_backlight_video)
 		return 0;
 
@@ -1994,8 +1959,10 @@ static void acpi_video_bus_remove_notify_handler(struct acpi_video_bus *video)
 	struct acpi_video_device *dev;
 
 	mutex_lock(&video->device_list_lock);
-	list_for_each_entry(dev, &video->video_device_list, entry)
+	list_for_each_entry(dev, &video->video_device_list, entry) {
 		acpi_video_dev_remove_notify_handler(dev);
+		cancel_delayed_work_sync(&dev->switch_brightness_work);
+	}
 	mutex_unlock(&video->device_list_lock);
 
 	acpi_video_bus_stop_devices(video);
@@ -2022,15 +1989,16 @@ static int instance;
 static int acpi_video_bus_add(struct acpi_device *device)
 {
 	struct acpi_video_bus *video;
+	bool auto_detect;
 	int error;
 	acpi_status status;
 
 	status = acpi_walk_namespace(ACPI_TYPE_DEVICE,
-				device->parent->handle, 1,
+				acpi_dev_parent(device)->handle, 1,
 				acpi_video_bus_match, NULL,
 				device, NULL);
 	if (status == AE_ALREADY_EXISTS) {
-		printk(KERN_WARNING FW_BUG
+		pr_info(FW_BUG
 			"Duplicate ACPI video bus devices for the"
 			" same VGA controller, please try module "
 			"parameter \"video.allow_duplicates=1\""
@@ -2057,8 +2025,8 @@ static int acpi_video_bus_add(struct acpi_device *device)
 	}
 
 	video->device = device;
-	strcpy(acpi_device_name(device), ACPI_VIDEO_BUS_NAME);
-	strcpy(acpi_device_class(device), ACPI_VIDEO_CLASS);
+	strscpy(acpi_device_name(device), ACPI_VIDEO_BUS_NAME);
+	strscpy(acpi_device_class(device), ACPI_VIDEO_CLASS);
 	device->driver_data = video;
 
 	acpi_video_bus_find_cap(video);
@@ -2073,20 +2041,54 @@ static int acpi_video_bus_add(struct acpi_device *device)
 	if (error)
 		goto err_put_video;
 
-	printk(KERN_INFO PREFIX "%s [%s] (multi-head: %s  rom: %s  post: %s)\n",
+	/*
+	 * HP ZBook Fury 16 G10 requires ACPI video's child devices have _PS0
+	 * evaluated to have functional panel brightness control.
+	 */
+	acpi_device_fix_up_power_children(device);
+
+	pr_info("%s [%s] (multi-head: %s  rom: %s  post: %s)\n",
 	       ACPI_VIDEO_DEVICE_NAME, acpi_device_bid(device),
-	       video->flags.multihead ? "yes" : "no",
-	       video->flags.rom ? "yes" : "no",
-	       video->flags.post ? "yes" : "no");
+	       str_yes_no(video->flags.multihead),
+	       str_yes_no(video->flags.rom),
+	       str_yes_no(video->flags.post));
 	mutex_lock(&video_list_lock);
 	list_add_tail(&video->entry, &video_bus_head);
 	mutex_unlock(&video_list_lock);
 
-	acpi_video_bus_register_backlight(video);
-	acpi_video_bus_add_notify_handler(video);
+	/*
+	 * If backlight-type auto-detection is used then a native backlight may
+	 * show up later and this may change the result from video to native.
+	 * Therefor normally the userspace visible /sys/class/backlight device
+	 * gets registered separately by the GPU driver calling
+	 * acpi_video_register_backlight() when an internal panel is detected.
+	 * Register the backlight now when not using auto-detection, so that
+	 * when the kernel cmdline or DMI-quirks are used the backlight will
+	 * get registered even if acpi_video_register_backlight() is not called.
+	 */
+	acpi_video_run_bcl_for_osi(video);
+	if (__acpi_video_get_backlight_type(false, &auto_detect) == acpi_backlight_video &&
+	    !auto_detect)
+		acpi_video_bus_register_backlight(video);
+
+	error = acpi_video_bus_add_notify_handler(video);
+	if (error)
+		goto err_del;
+
+	error = acpi_dev_install_notify_handler(device, ACPI_DEVICE_NOTIFY,
+						acpi_video_bus_notify, device);
+	if (error)
+		goto err_remove;
 
 	return 0;
 
+err_remove:
+	acpi_video_bus_remove_notify_handler(video);
+err_del:
+	mutex_lock(&video_list_lock);
+	list_del(&video->entry);
+	mutex_unlock(&video_list_lock);
+	acpi_video_bus_unregister_backlight(video);
 err_put_video:
 	acpi_video_bus_put_devices(video);
 	kfree(video->attached_array);
@@ -2097,28 +2099,29 @@ err_free_video:
 	return error;
 }
 
-static int acpi_video_bus_remove(struct acpi_device *device)
+static void acpi_video_bus_remove(struct acpi_device *device)
 {
 	struct acpi_video_bus *video = NULL;
 
 
 	if (!device || !acpi_driver_data(device))
-		return -EINVAL;
+		return;
 
 	video = acpi_driver_data(device);
 
-	acpi_video_bus_remove_notify_handler(video);
-	acpi_video_bus_unregister_backlight(video);
-	acpi_video_bus_put_devices(video);
+	acpi_dev_remove_notify_handler(device, ACPI_DEVICE_NOTIFY,
+				       acpi_video_bus_notify);
 
 	mutex_lock(&video_list_lock);
 	list_del(&video->entry);
 	mutex_unlock(&video_list_lock);
 
+	acpi_video_bus_remove_notify_handler(video);
+	acpi_video_bus_unregister_backlight(video);
+	acpi_video_bus_put_devices(video);
+
 	kfree(video->attached_array);
 	kfree(video);
-
-	return 0;
 }
 
 static int __init is_i740(struct pci_dev *dev)
@@ -2152,33 +2155,6 @@ static int __init intel_opregion_present(void)
 	return opregion;
 }
 
-/* Check if the chassis-type indicates there is no builtin LCD panel */
-static bool dmi_is_desktop(void)
-{
-	const char *chassis_type;
-	unsigned long type;
-
-	chassis_type = dmi_get_system_info(DMI_CHASSIS_TYPE);
-	if (!chassis_type)
-		return false;
-
-	if (kstrtoul(chassis_type, 10, &type) != 0)
-		return false;
-
-	switch (type) {
-	case 0x03: /* Desktop */
-	case 0x04: /* Low Profile Desktop */
-	case 0x05: /* Pizza Box */
-	case 0x06: /* Mini Tower */
-	case 0x07: /* Tower */
-	case 0x10: /* Lunch Box */
-	case 0x11: /* Main Server Chassis */
-		return true;
-	}
-
-	return false;
-}
-
 int acpi_video_register(void)
 {
 	int ret = 0;
@@ -2192,20 +2168,6 @@ int acpi_video_register(void)
 		goto leave;
 	}
 
-	/*
-	 * We're seeing a lot of bogus backlight interfaces on newer machines
-	 * without a LCD such as desktops, servers and HDMI sticks. Checking
-	 * the lcd flag fixes this, so enable this on any machines which are
-	 * win8 ready (where we also prefer the native backlight driver, so
-	 * normally the acpi_video code should not register there anyways).
-	 */
-	if (only_lcd == -1) {
-		if (dmi_is_desktop() && acpi_osi_is_win8())
-			only_lcd = true;
-		else
-			only_lcd = false;
-	}
-
 	dmi_check_system(video_dmi_table);
 
 	ret = acpi_bus_register_driver(&acpi_video_bus);
@@ -2230,34 +2192,26 @@ void acpi_video_unregister(void)
 	if (register_count) {
 		acpi_bus_unregister_driver(&acpi_video_bus);
 		register_count = 0;
+		may_report_brightness_keys = false;
 	}
 	mutex_unlock(&register_count_mutex);
 }
 EXPORT_SYMBOL(acpi_video_unregister);
 
-void acpi_video_unregister_backlight(void)
+void acpi_video_register_backlight(void)
 {
 	struct acpi_video_bus *video;
 
-	mutex_lock(&register_count_mutex);
-	if (register_count) {
-		mutex_lock(&video_list_lock);
-		list_for_each_entry(video, &video_bus_head, entry)
-			acpi_video_bus_unregister_backlight(video);
-		mutex_unlock(&video_list_lock);
-	}
-	mutex_unlock(&register_count_mutex);
+	mutex_lock(&video_list_lock);
+	list_for_each_entry(video, &video_bus_head, entry)
+		acpi_video_bus_register_backlight(video);
+	mutex_unlock(&video_list_lock);
 }
+EXPORT_SYMBOL(acpi_video_register_backlight);
 
 bool acpi_video_handles_brightness_key_presses(void)
 {
-	bool have_video_busses;
-
-	mutex_lock(&video_list_lock);
-	have_video_busses = !list_empty(&video_bus_head);
-	mutex_unlock(&video_list_lock);
-
-	return have_video_busses &&
+	return may_report_brightness_keys &&
 	       (report_key_events & REPORT_BRIGHTNESS_KEY_EVENTS);
 }
 EXPORT_SYMBOL(acpi_video_handles_brightness_key_presses);
@@ -2290,10 +2244,7 @@ static int __init acpi_video_init(void)
 
 static void __exit acpi_video_exit(void)
 {
-	acpi_video_detect_exit();
 	acpi_video_unregister();
-
-	return;
 }
 
 module_init(acpi_video_init);
diff --git a/drivers/acpi/acpi_watchdog.c b/drivers/acpi/acpi_watchdog.c
index 6e9ec6e3fe47..14b24157799c 100644
--- a/drivers/acpi/acpi_watchdog.c
+++ b/drivers/acpi/acpi_watchdog.c
@@ -73,6 +73,7 @@ static const struct acpi_table_wdat *acpi_watchdog_get_wdat(void)
 	}
 
 	if (acpi_watchdog_uses_rtc(wdat)) {
+		acpi_put_table((struct acpi_table_header *)wdat);
 		pr_info("Skipping WDAT on this system because it uses RTC SRAM\n");
 		return NULL;
 	}
@@ -80,7 +81,7 @@ static const struct acpi_table_wdat *acpi_watchdog_get_wdat(void)
 	return wdat;
 }
 
-/**
+/*
  * Returns true if this system should prefer ACPI based watchdog instead of
  * the native one (which are typically the same hardware).
  */
@@ -117,12 +118,12 @@ void __init acpi_watchdog_init(void)
 
 	/* Watchdog disabled by BIOS */
 	if (!(wdat->flags & ACPI_WDAT_ENABLED))
-		return;
+		goto fail_put_wdat;
 
 	/* Skip legacy PCI WDT devices */
 	if (wdat->pci_segment != 0xff || wdat->pci_bus != 0xff ||
 	    wdat->pci_device != 0xff || wdat->pci_function != 0xff)
-		return;
+		goto fail_put_wdat;
 
 	INIT_LIST_HEAD(&resource_list);
 
@@ -150,11 +151,7 @@ void __init acpi_watchdog_init(void)
 		found = false;
 		resource_list_for_each_entry(rentry, &resource_list) {
 			if (rentry->res->flags == res.flags &&
-			    resource_overlaps(rentry->res, &res)) {
-				if (res.start < rentry->res->start)
-					rentry->res->start = res.start;
-				if (res.end > rentry->res->end)
-					rentry->res->end = res.end;
+			    resource_union(rentry->res, &res, rentry->res)) {
 				found = true;
 				break;
 			}
@@ -182,10 +179,12 @@ void __init acpi_watchdog_init(void)
 	pdev = platform_device_register_simple("wdat_wdt", PLATFORM_DEVID_NONE,
 					       resources, nresources);
 	if (IS_ERR(pdev))
-		pr_err("Device creation failed: %ld\n", PTR_ERR(pdev));
+		pr_err("Device creation failed: %pe\n", pdev);
 
 	kfree(resources);
 
 fail_free_resource_list:
 	resource_list_free(&resource_list);
+fail_put_wdat:
+	acpi_put_table((struct acpi_table_header *)wdat);
 }
diff --git a/drivers/acpi/acpica/Makefile b/drivers/acpi/acpica/Makefile
index 59700433a96e..8d18af396de9 100644
--- a/drivers/acpi/acpica/Makefile
+++ b/drivers/acpi/acpica/Makefile
@@ -3,8 +3,9 @@
 # Makefile for ACPICA Core interpreter
 #
 
-ccflags-y			:= -Os -D_LINUX -DBUILDING_ACPICA
+ccflags-y			:= -D_LINUX -DBUILDING_ACPICA
 ccflags-$(CONFIG_ACPI_DEBUG)	+= -DACPI_DEBUG_OUTPUT
+CFLAGS_tbfind.o 		+= $(call cc-disable-warning, stringop-truncation)
 
 # use acpi.o to put all files here into acpi.o modparam namespace
 obj-y	+= acpi.o
@@ -155,6 +156,7 @@ acpi-y +=		\
 	utalloc.o	\
 	utascii.o	\
 	utbuffer.o	\
+	utcksum.o	\
 	utcopy.o	\
 	utexcep.o	\
 	utdebug.o	\
diff --git a/drivers/acpi/acpica/acapps.h b/drivers/acpi/acpica/acapps.h
index 173447d50acf..d7d4649ce66f 100644
--- a/drivers/acpi/acpica/acapps.h
+++ b/drivers/acpi/acpica/acapps.h
@@ -3,7 +3,7 @@
  *
  * Module Name: acapps - common include for ACPI applications/tools
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -17,7 +17,7 @@
 /* Common info for tool signons */
 
 #define ACPICA_NAME                 "Intel ACPI Component Architecture"
-#define ACPICA_COPYRIGHT            "Copyright (c) 2000 - 2020 Intel Corporation"
+#define ACPICA_COPYRIGHT            "Copyright (c) 2000 - 2025 Intel Corporation"
 
 #if ACPI_MACHINE_WIDTH == 64
 #define ACPI_WIDTH          " (64-bit version)"
diff --git a/drivers/acpi/acpica/accommon.h b/drivers/acpi/acpica/accommon.h
index 89101e53324b..662231f4f881 100644
--- a/drivers/acpi/acpica/accommon.h
+++ b/drivers/acpi/acpica/accommon.h
@@ -3,7 +3,7 @@
  *
  * Name: accommon.h - Common include files for generation of ACPICA source
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -13,7 +13,7 @@
 /*
  * Common set of includes for all ACPICA source files.
  * We put them here because we don't want to duplicate them
- * in the the source code again and again.
+ * in the source code again and again.
  *
  * Note: The order of these include files is important.
  */
diff --git a/drivers/acpi/acpica/acconvert.h b/drivers/acpi/acpica/acconvert.h
index cf85d66da6e7..24998f2d7539 100644
--- a/drivers/acpi/acpica/acconvert.h
+++ b/drivers/acpi/acpica/acconvert.h
@@ -3,7 +3,7 @@
  *
  * Module Name: acapps - common include for ACPI applications/tools
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/acdebug.h b/drivers/acpi/acpica/acdebug.h
index a676daaa2da5..91241bd6917a 100644
--- a/drivers/acpi/acpica/acdebug.h
+++ b/drivers/acpi/acpica/acdebug.h
@@ -3,7 +3,7 @@
  *
  * Name: acdebug.h - ACPI/AML debugger
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -37,12 +37,14 @@ struct acpi_db_argument_info {
 struct acpi_db_execute_walk {
 	u32 count;
 	u32 max_count;
+	char name_seg[ACPI_NAMESEG_SIZE + 1];
 };
 
 #define PARAM_LIST(pl)                  pl
 
 #define EX_NO_SINGLE_STEP               1
 #define EX_SINGLE_STEP                  2
+#define EX_ALL                          4
 
 /*
  * dbxface - external debugger interfaces
@@ -124,6 +126,8 @@ void acpi_db_disassemble_aml(char *statements, union acpi_parse_object *op);
 
 void acpi_db_evaluate_predefined_names(void);
 
+void acpi_db_evaluate_all(char *name_seg);
+
 /*
  * dbnames - namespace commands
  */
@@ -283,4 +287,6 @@ struct acpi_namespace_node *acpi_db_local_ns_lookup(char *name);
 
 void acpi_db_uint32_to_hex_string(u32 value, char *buffer);
 
+void acpi_db_generate_interrupt(char *gsiv_arg);
+
 #endif				/* __ACDEBUG_H__ */
diff --git a/drivers/acpi/acpica/acdispat.h b/drivers/acpi/acpica/acdispat.h
index 7ba6e308f146..5d48a344b35f 100644
--- a/drivers/acpi/acpica/acdispat.h
+++ b/drivers/acpi/acpica/acdispat.h
@@ -3,7 +3,7 @@
  *
  * Name: acdispat.h - dispatcher (parser to interpreter interface)
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/acevents.h b/drivers/acpi/acpica/acevents.h
index 79f292687bd6..b40fb3a5ac8a 100644
--- a/drivers/acpi/acpica/acevents.h
+++ b/drivers/acpi/acpica/acevents.h
@@ -3,7 +3,7 @@
  *
  * Name: acevents.h - Event subcomponent prototypes and defines
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -188,7 +188,7 @@ acpi_ev_detach_region(union acpi_operand_object *region_obj,
 		      u8 acpi_ns_is_locked);
 
 void
-acpi_ev_execute_reg_methods(struct acpi_namespace_node *node,
+acpi_ev_execute_reg_methods(struct acpi_namespace_node *node, u32 max_depth,
 			    acpi_adr_space_type space_id, u32 function);
 
 acpi_status
@@ -224,6 +224,11 @@ acpi_ev_pci_bar_region_setup(acpi_handle handle,
 			     void *handler_context, void **region_context);
 
 acpi_status
+acpi_ev_data_table_region_setup(acpi_handle handle,
+				u32 function,
+				void *handler_context, void **region_context);
+
+acpi_status
 acpi_ev_default_region_setup(acpi_handle handle,
 			     u32 function,
 			     void *handler_context, void **region_context);
diff --git a/drivers/acpi/acpica/acglobal.h b/drivers/acpi/acpica/acglobal.h
index 38ffa2c0a496..c8a750d2674c 100644
--- a/drivers/acpi/acpica/acglobal.h
+++ b/drivers/acpi/acpica/acglobal.h
@@ -3,7 +3,7 @@
  *
  * Name: acglobal.h - Declarations for global variables
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -24,15 +24,12 @@ ACPI_GLOBAL(struct acpi_table_list, acpi_gbl_root_table_list);
 
 ACPI_GLOBAL(struct acpi_table_header *, acpi_gbl_DSDT);
 ACPI_GLOBAL(struct acpi_table_header, acpi_gbl_original_dsdt_header);
+ACPI_INIT_GLOBAL(char *, acpi_gbl_CDAT, NULL);
 ACPI_INIT_GLOBAL(u32, acpi_gbl_dsdt_index, ACPI_INVALID_TABLE_INDEX);
 ACPI_INIT_GLOBAL(u32, acpi_gbl_facs_index, ACPI_INVALID_TABLE_INDEX);
 ACPI_INIT_GLOBAL(u32, acpi_gbl_xfacs_index, ACPI_INVALID_TABLE_INDEX);
 ACPI_INIT_GLOBAL(u32, acpi_gbl_fadt_index, ACPI_INVALID_TABLE_INDEX);
-
-#if (!ACPI_REDUCED_HARDWARE)
-ACPI_GLOBAL(struct acpi_table_facs *, acpi_gbl_FACS);
-
-#endif				/* !ACPI_REDUCED_HARDWARE */
+ACPI_INIT_GLOBAL(struct acpi_table_facs *, acpi_gbl_FACS, NULL);
 
 /* These addresses are calculated from the FADT Event Block addresses */
 
@@ -42,6 +39,12 @@ ACPI_GLOBAL(struct acpi_generic_address, acpi_gbl_xpm1a_enable);
 ACPI_GLOBAL(struct acpi_generic_address, acpi_gbl_xpm1b_status);
 ACPI_GLOBAL(struct acpi_generic_address, acpi_gbl_xpm1b_enable);
 
+#ifdef ACPI_GPE_USE_LOGICAL_ADDRESSES
+ACPI_GLOBAL(unsigned long, acpi_gbl_xgpe0_block_logical_address);
+ACPI_GLOBAL(unsigned long, acpi_gbl_xgpe1_block_logical_address);
+
+#endif				/* ACPI_GPE_USE_LOGICAL_ADDRESSES */
+
 /*
  * Handle both ACPI 1.0 and ACPI 2.0+ Integer widths. The integer width is
  * determined by the revision of the DSDT: If the DSDT revision is less than
@@ -122,6 +125,7 @@ ACPI_GLOBAL(acpi_table_handler, acpi_gbl_table_handler);
 ACPI_GLOBAL(void *, acpi_gbl_table_handler_context);
 ACPI_GLOBAL(acpi_interface_handler, acpi_gbl_interface_handler);
 ACPI_GLOBAL(struct acpi_sci_handler_info *, acpi_gbl_sci_handler_list);
+ACPI_GLOBAL(struct acpi_ged_handler_info *, acpi_gbl_ged_handler_list);
 
 /* Owner ID support */
 
@@ -220,6 +224,8 @@ extern struct acpi_bit_register_info
     acpi_gbl_bit_register_info[ACPI_NUM_BITREG];
 ACPI_GLOBAL(u8, acpi_gbl_sleep_type_a);
 ACPI_GLOBAL(u8, acpi_gbl_sleep_type_b);
+ACPI_GLOBAL(u8, acpi_gbl_sleep_type_a_s0);
+ACPI_GLOBAL(u8, acpi_gbl_sleep_type_b_s0);
 
 /*****************************************************************************
  *
@@ -290,6 +296,7 @@ ACPI_GLOBAL(struct acpi_external_file *, acpi_gbl_external_file_list);
 #ifdef ACPI_DEBUGGER
 ACPI_INIT_GLOBAL(u8, acpi_gbl_abort_method, FALSE);
 ACPI_INIT_GLOBAL(acpi_thread_id, acpi_gbl_db_thread_id, ACPI_INVALID_THREAD_ID);
+ACPI_INIT_GLOBAL(u32, acpi_gbl_next_cmd_num, 1);
 
 ACPI_GLOBAL(u8, acpi_gbl_db_opt_no_ini_methods);
 ACPI_GLOBAL(u8, acpi_gbl_db_opt_no_region_support);
diff --git a/drivers/acpi/acpica/achware.h b/drivers/acpi/acpica/achware.h
index ebf6453d0e21..6aec56c65fa0 100644
--- a/drivers/acpi/acpica/achware.h
+++ b/drivers/acpi/acpica/achware.h
@@ -3,7 +3,7 @@
  *
  * Name: achware.h -- hardware specific interfaces
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -73,9 +73,15 @@ acpi_status acpi_hw_read_port(acpi_io_address address, u32 *value, u32 width);
 
 acpi_status acpi_hw_write_port(acpi_io_address address, u32 value, u32 width);
 
+acpi_status acpi_hw_validate_io_block(u64 address, u32 bit_width, u32 count);
+
 /*
  * hwgpe - GPE support
  */
+acpi_status acpi_hw_gpe_read(u64 *value, struct acpi_gpe_address *reg);
+
+acpi_status acpi_hw_gpe_write(u64 value, struct acpi_gpe_address *reg);
+
 u32 acpi_hw_get_gpe_register_bit(struct acpi_gpe_event_info *gpe_event_info);
 
 acpi_status
@@ -95,12 +101,8 @@ acpi_status
 acpi_hw_get_gpe_status(struct acpi_gpe_event_info *gpe_event_info,
 		       acpi_event_status *event_status);
 
-acpi_status acpi_hw_disable_all_gpes(void);
-
 acpi_status acpi_hw_enable_all_runtime_gpes(void);
 
-acpi_status acpi_hw_enable_all_wakeup_gpes(void);
-
 u8 acpi_hw_check_all_gpes(acpi_handle gpe_skip_device, u32 gpe_skip_number);
 
 acpi_status
diff --git a/drivers/acpi/acpica/acinterp.h b/drivers/acpi/acpica/acinterp.h
index a6d896cda2a5..1ee6ac9b2baf 100644
--- a/drivers/acpi/acpica/acinterp.h
+++ b/drivers/acpi/acpica/acinterp.h
@@ -3,7 +3,7 @@
  *
  * Name: acinterp.h - Interpreter subcomponent prototypes and defines
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -120,6 +120,9 @@ void
 acpi_ex_trace_point(acpi_trace_event_type type,
 		    u8 begin, u8 *aml, char *pathname);
 
+void
+acpi_ex_trace_args(union acpi_operand_object **params, u32 count);
+
 /*
  * exfield - ACPI AML (p-code) execution - field manipulation
  */
diff --git a/drivers/acpi/acpica/aclocal.h b/drivers/acpi/acpica/aclocal.h
index af58cd2dc9d3..f98640086f4e 100644
--- a/drivers/acpi/acpica/aclocal.h
+++ b/drivers/acpi/acpica/aclocal.h
@@ -3,7 +3,7 @@
  *
  * Name: aclocal.h - Internal data types used across the ACPI subsystem
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -293,7 +293,7 @@ acpi_status (*acpi_internal_method) (struct acpi_walk_state * walk_state);
  * expected_return_btypes - Allowed type(s) for the return value
  */
 struct acpi_name_info {
-	char name[ACPI_NAMESEG_SIZE];
+	char name[ACPI_NAMESEG_SIZE] ACPI_NONSTRING;
 	u16 argument_list;
 	u8 expected_btypes;
 };
@@ -370,7 +370,7 @@ typedef acpi_status (*acpi_object_converter) (struct acpi_namespace_node *
 					      converted_object);
 
 struct acpi_simple_repair_info {
-	char name[ACPI_NAMESEG_SIZE];
+	char name[ACPI_NAMESEG_SIZE] ACPI_NONSTRING;
 	u32 unexpected_btypes;
 	u32 package_index;
 	acpi_object_converter object_converter;
@@ -454,11 +454,18 @@ struct acpi_gpe_event_info {
 	u8 disable_for_dispatch;	/* Masked during dispatching */
 };
 
+/* GPE register address */
+
+struct acpi_gpe_address {
+	u8 space_id;	/* Address space where the register exists */
+	u64 address;	/* 64-bit address of the register */
+};
+
 /* Information about a GPE register pair, one per each status/enable pair in an array */
 
 struct acpi_gpe_register_info {
-	struct acpi_generic_address status_address;	/* Address of status reg */
-	struct acpi_generic_address enable_address;	/* Address of enable reg */
+	struct acpi_gpe_address status_address;	/* Address of status reg */
+	struct acpi_gpe_address enable_address;	/* Address of enable reg */
 	u16 base_gpe_number;	/* Base GPE number for this register */
 	u8 enable_for_wake;	/* GPEs to keep enabled when sleeping */
 	u8 enable_for_run;	/* GPEs to keep enabled when running */
@@ -536,6 +543,14 @@ struct acpi_field_info {
 	u32 pkg_length;
 };
 
+/* Information about the interrupt ID and _EVT of a GED device */
+
+struct acpi_ged_handler_info {
+	struct acpi_ged_handler_info *next;
+	u32 int_id;		/* The interrupt ID that triggers the execution of the evt_method. */
+	struct acpi_namespace_node *evt_method;	/* The _EVT method to be executed when an interrupt with ID = int_ID is received */
+};
+
 /*****************************************************************************
  *
  * Generic "state" object for stacks
@@ -553,25 +568,28 @@ struct acpi_field_info {
 	u8                              descriptor_type; /* To differentiate various internal objs */\
 	u8                              flags; \
 	u16                             value; \
-	u16                             state;
+	u16                             state
 
 	/* There are 2 bytes available here until the next natural alignment boundary */
 
 struct acpi_common_state {
-ACPI_STATE_COMMON};
+	ACPI_STATE_COMMON;
+};
 
 /*
  * Update state - used to traverse complex objects such as packages
  */
 struct acpi_update_state {
-	ACPI_STATE_COMMON union acpi_operand_object *object;
+	ACPI_STATE_COMMON;
+	union acpi_operand_object *object;
 };
 
 /*
  * Pkg state - used to traverse nested package structures
  */
 struct acpi_pkg_state {
-	ACPI_STATE_COMMON u32 index;
+	ACPI_STATE_COMMON;
+	u32 index;
 	union acpi_operand_object *source_object;
 	union acpi_operand_object *dest_object;
 	struct acpi_walk_state *walk_state;
@@ -584,7 +602,8 @@ struct acpi_pkg_state {
  * Allows nesting of these constructs
  */
 struct acpi_control_state {
-	ACPI_STATE_COMMON u16 opcode;
+	ACPI_STATE_COMMON;
+	u16 opcode;
 	union acpi_parse_object *predicate_op;
 	u8 *aml_predicate_start;	/* Start of if/while predicate */
 	u8 *package_end;	/* End of if/while block */
@@ -595,11 +614,13 @@ struct acpi_control_state {
  * Scope state - current scope during namespace lookups
  */
 struct acpi_scope_state {
-	ACPI_STATE_COMMON struct acpi_namespace_node *node;
+	ACPI_STATE_COMMON;
+	struct acpi_namespace_node *node;
 };
 
 struct acpi_pscope_state {
-	ACPI_STATE_COMMON u32 arg_count;	/* Number of fixed arguments */
+	ACPI_STATE_COMMON;
+	u32 arg_count;		/* Number of fixed arguments */
 	union acpi_parse_object *op;	/* Current op being parsed */
 	u8 *arg_end;		/* Current argument end */
 	u8 *pkg_end;		/* Current package end */
@@ -611,7 +632,8 @@ struct acpi_pscope_state {
  * states are created when there are nested control methods executing.
  */
 struct acpi_thread_state {
-	ACPI_STATE_COMMON u8 current_sync_level;	/* Mutex Sync (nested acquire) level */
+	ACPI_STATE_COMMON;
+	u8 current_sync_level;	/* Mutex Sync (nested acquire) level */
 	struct acpi_walk_state *walk_state_list;	/* Head of list of walk_states for this thread */
 	union acpi_operand_object *acquired_mutex_list;	/* List of all currently acquired mutexes */
 	acpi_thread_id thread_id;	/* Running thread ID */
@@ -622,8 +644,8 @@ struct acpi_thread_state {
  * AML arguments
  */
 struct acpi_result_values {
-	ACPI_STATE_COMMON
-	    union acpi_operand_object *obj_desc[ACPI_RESULTS_FRAME_OBJ_NUM];
+	ACPI_STATE_COMMON;
+	union acpi_operand_object *obj_desc[ACPI_RESULTS_FRAME_OBJ_NUM];
 };
 
 typedef
@@ -645,7 +667,8 @@ struct acpi_global_notify_handler {
  * handler/dispatcher.
  */
 struct acpi_notify_info {
-	ACPI_STATE_COMMON u8 handler_list_id;
+	ACPI_STATE_COMMON;
+	u8 handler_list_id;
 	struct acpi_namespace_node *node;
 	union acpi_operand_object *handler_list_head;
 	struct acpi_global_notify_handler *global;
@@ -1067,6 +1090,8 @@ struct acpi_port_info {
 #define ACPI_ADDRESS_TYPE_IO_RANGE              1
 #define ACPI_ADDRESS_TYPE_BUS_NUMBER_RANGE      2
 
+#define ACPI_ADDRESS_TYPE_PCC_NUMBER            0xA
+
 /* Resource descriptor types and masks */
 
 #define ACPI_RESOURCE_NAME_LARGE                0x80
@@ -1115,7 +1140,8 @@ struct acpi_port_info {
 #define ACPI_RESOURCE_NAME_PIN_GROUP            0x90
 #define ACPI_RESOURCE_NAME_PIN_GROUP_FUNCTION   0x91
 #define ACPI_RESOURCE_NAME_PIN_GROUP_CONFIG     0x92
-#define ACPI_RESOURCE_NAME_LARGE_MAX            0x92
+#define ACPI_RESOURCE_NAME_CLOCK_INPUT          0x93
+#define ACPI_RESOURCE_NAME_LARGE_MAX            0x93
 
 /*****************************************************************************
  *
diff --git a/drivers/acpi/acpica/acmacros.h b/drivers/acpi/acpica/acmacros.h
index 168904ba3086..4e9402c02410 100644
--- a/drivers/acpi/acpica/acmacros.h
+++ b/drivers/acpi/acpica/acmacros.h
@@ -3,7 +3,7 @@
  *
  * Name: acmacros.h - C macros for the entire subsystem.
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/acnamesp.h b/drivers/acpi/acpica/acnamesp.h
index 40f6a3c33a15..13f050fecb49 100644
--- a/drivers/acpi/acpica/acnamesp.h
+++ b/drivers/acpi/acpica/acnamesp.h
@@ -3,7 +3,7 @@
  *
  * Name: acnamesp.h - Namespace subcomponent prototypes and defines
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/acobject.h b/drivers/acpi/acpica/acobject.h
index 9f0219a8cb98..6ffcc7a0a0c2 100644
--- a/drivers/acpi/acpica/acobject.h
+++ b/drivers/acpi/acpica/acobject.h
@@ -3,7 +3,7 @@
  *
  * Name: acobject.h - Definition of union acpi_operand_object  (Internal object only)
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -48,7 +48,7 @@
 	u8                              descriptor_type;    /* To differentiate various internal objs */\
 	u8                              type;               /* acpi_object_type */\
 	u16                             reference_count;    /* For object deletion management */\
-	u8                              flags;
+	u8                              flags
 	/*
 	 * Note: There are 3 bytes available here before the
 	 * next natural alignment boundary (for both 32/64 cases)
@@ -71,10 +71,12 @@
  *****************************************************************************/
 
 struct acpi_object_common {
-ACPI_OBJECT_COMMON_HEADER};
+	ACPI_OBJECT_COMMON_HEADER;
+};
 
 struct acpi_object_integer {
-	ACPI_OBJECT_COMMON_HEADER u8 fill[3];	/* Prevent warning on some compilers */
+	ACPI_OBJECT_COMMON_HEADER;
+	u8 fill[3];		/* Prevent warning on some compilers */
 	u64 value;
 };
 
@@ -86,23 +88,26 @@ struct acpi_object_integer {
  */
 #define ACPI_COMMON_BUFFER_INFO(_type) \
 	_type                           *pointer; \
-	u32                             length;
+	u32                             length
 
 /* Null terminated, ASCII characters only */
 
 struct acpi_object_string {
-	ACPI_OBJECT_COMMON_HEADER ACPI_COMMON_BUFFER_INFO(char)	/* String in AML stream or allocated string */
+	ACPI_OBJECT_COMMON_HEADER;
+	ACPI_COMMON_BUFFER_INFO(char);	/* String in AML stream or allocated string */
 };
 
 struct acpi_object_buffer {
-	ACPI_OBJECT_COMMON_HEADER ACPI_COMMON_BUFFER_INFO(u8)	/* Buffer in AML stream or allocated buffer */
+	ACPI_OBJECT_COMMON_HEADER;
+	ACPI_COMMON_BUFFER_INFO(u8);	/* Buffer in AML stream or allocated buffer */
 	u32 aml_length;
 	u8 *aml_start;
 	struct acpi_namespace_node *node;	/* Link back to parent node */
 };
 
 struct acpi_object_package {
-	ACPI_OBJECT_COMMON_HEADER struct acpi_namespace_node *node;	/* Link back to parent node */
+	ACPI_OBJECT_COMMON_HEADER;
+	struct acpi_namespace_node *node;	/* Link back to parent node */
 	union acpi_operand_object **elements;	/* Array of pointers to acpi_objects */
 	u8 *aml_start;
 	u32 aml_length;
@@ -116,11 +121,13 @@ struct acpi_object_package {
  *****************************************************************************/
 
 struct acpi_object_event {
-	ACPI_OBJECT_COMMON_HEADER acpi_semaphore os_semaphore;	/* Actual OS synchronization object */
+	ACPI_OBJECT_COMMON_HEADER;
+	acpi_semaphore os_semaphore;	/* Actual OS synchronization object */
 };
 
 struct acpi_object_mutex {
-	ACPI_OBJECT_COMMON_HEADER u8 sync_level;	/* 0-15, specified in Mutex() call */
+	ACPI_OBJECT_COMMON_HEADER;
+	u8 sync_level;		/* 0-15, specified in Mutex() call */
 	u16 acquisition_depth;	/* Allow multiple Acquires, same thread */
 	acpi_mutex os_mutex;	/* Actual OS synchronization object */
 	acpi_thread_id thread_id;	/* Current owner of the mutex */
@@ -132,16 +139,19 @@ struct acpi_object_mutex {
 };
 
 struct acpi_object_region {
-	ACPI_OBJECT_COMMON_HEADER u8 space_id;
+	ACPI_OBJECT_COMMON_HEADER;
+	u8 space_id;
 	struct acpi_namespace_node *node;	/* Containing namespace node */
 	union acpi_operand_object *handler;	/* Handler for region access */
 	union acpi_operand_object *next;
 	acpi_physical_address address;
 	u32 length;
+	void *pointer;		/* Only for data table regions */
 };
 
 struct acpi_object_method {
-	ACPI_OBJECT_COMMON_HEADER u8 info_flags;
+	ACPI_OBJECT_COMMON_HEADER;
+	u8 info_flags;
 	u8 param_count;
 	u8 sync_level;
 	union acpi_operand_object *mutex;
@@ -177,33 +187,43 @@ struct acpi_object_method {
  */
 #define ACPI_COMMON_NOTIFY_INFO \
 	union acpi_operand_object       *notify_list[2];    /* Handlers for system/device notifies */\
-	union acpi_operand_object       *handler;	/* Handler for Address space */
+	union acpi_operand_object       *handler	/* Handler for Address space */
 
 /* COMMON NOTIFY for POWER, PROCESSOR, DEVICE, and THERMAL */
 
 struct acpi_object_notify_common {
-ACPI_OBJECT_COMMON_HEADER ACPI_COMMON_NOTIFY_INFO};
+	ACPI_OBJECT_COMMON_HEADER;
+	ACPI_COMMON_NOTIFY_INFO;
+};
 
 struct acpi_object_device {
-	ACPI_OBJECT_COMMON_HEADER
-	    ACPI_COMMON_NOTIFY_INFO struct acpi_gpe_block_info *gpe_block;
+	ACPI_OBJECT_COMMON_HEADER;
+	ACPI_COMMON_NOTIFY_INFO;
+	struct acpi_gpe_block_info *gpe_block;
 };
 
 struct acpi_object_power_resource {
-	ACPI_OBJECT_COMMON_HEADER ACPI_COMMON_NOTIFY_INFO u32 system_level;
+	ACPI_OBJECT_COMMON_HEADER;
+	ACPI_COMMON_NOTIFY_INFO;
+	u32 system_level;
 	u32 resource_order;
 };
 
 struct acpi_object_processor {
-	ACPI_OBJECT_COMMON_HEADER
-	    /* The next two fields take advantage of the 3-byte space before NOTIFY_INFO */
+	ACPI_OBJECT_COMMON_HEADER;
+
+	/* The next two fields take advantage of the 3-byte space before NOTIFY_INFO */
+
 	u8 proc_id;
 	u8 length;
-	ACPI_COMMON_NOTIFY_INFO acpi_io_address address;
+	ACPI_COMMON_NOTIFY_INFO;
+	acpi_io_address address;
 };
 
 struct acpi_object_thermal_zone {
-ACPI_OBJECT_COMMON_HEADER ACPI_COMMON_NOTIFY_INFO};
+	ACPI_OBJECT_COMMON_HEADER;
+	ACPI_COMMON_NOTIFY_INFO;
+};
 
 /******************************************************************************
  *
@@ -225,17 +245,21 @@ ACPI_OBJECT_COMMON_HEADER ACPI_COMMON_NOTIFY_INFO};
 	u32                             base_byte_offset;   /* Byte offset within containing object */\
 	u32                             value;              /* Value to store into the Bank or Index register */\
 	u8                              start_field_bit_offset;/* Bit offset within first field datum (0-63) */\
-	u8                              access_length;	/* For serial regions/fields */
+	u8                              access_length	/* For serial regions/fields */
 
 
 /* COMMON FIELD (for BUFFER, REGION, BANK, and INDEX fields) */
 
 struct acpi_object_field_common {
-	ACPI_OBJECT_COMMON_HEADER ACPI_COMMON_FIELD_INFO union acpi_operand_object *region_obj;	/* Parent Operation Region object (REGION/BANK fields only) */
+	ACPI_OBJECT_COMMON_HEADER;
+	ACPI_COMMON_FIELD_INFO;
+	union acpi_operand_object *region_obj;	/* Parent Operation Region object (REGION/BANK fields only) */
 };
 
 struct acpi_object_region_field {
-	ACPI_OBJECT_COMMON_HEADER ACPI_COMMON_FIELD_INFO u16 resource_length;
+	ACPI_OBJECT_COMMON_HEADER;
+	ACPI_COMMON_FIELD_INFO;
+	u16 resource_length;
 	union acpi_operand_object *region_obj;	/* Containing op_region object */
 	u8 *resource_buffer;	/* resource_template for serial regions/fields */
 	u16 pin_number_index;	/* Index relative to previous Connection/Template */
@@ -243,16 +267,20 @@ struct acpi_object_region_field {
 };
 
 struct acpi_object_bank_field {
-	ACPI_OBJECT_COMMON_HEADER ACPI_COMMON_FIELD_INFO union acpi_operand_object *region_obj;	/* Containing op_region object */
+	ACPI_OBJECT_COMMON_HEADER;
+	ACPI_COMMON_FIELD_INFO;
+	union acpi_operand_object *region_obj;	/* Containing op_region object */
 	union acpi_operand_object *bank_obj;	/* bank_select Register object */
 };
 
 struct acpi_object_index_field {
-	ACPI_OBJECT_COMMON_HEADER ACPI_COMMON_FIELD_INFO
-	    /*
-	     * No "RegionObj" pointer needed since the Index and Data registers
-	     * are each field definitions unto themselves.
-	     */
+	ACPI_OBJECT_COMMON_HEADER;
+	ACPI_COMMON_FIELD_INFO;
+
+	/*
+	 * No "RegionObj" pointer needed since the Index and Data registers
+	 * are each field definitions unto themselves.
+	 */
 	union acpi_operand_object *index_obj;	/* Index register */
 	union acpi_operand_object *data_obj;	/* Data register */
 };
@@ -260,7 +288,9 @@ struct acpi_object_index_field {
 /* The buffer_field is different in that it is part of a Buffer, not an op_region */
 
 struct acpi_object_buffer_field {
-	ACPI_OBJECT_COMMON_HEADER ACPI_COMMON_FIELD_INFO u8 is_create_field;	/* Special case for objects created by create_field() */
+	ACPI_OBJECT_COMMON_HEADER;
+	ACPI_COMMON_FIELD_INFO;
+	u8 is_create_field;	/* Special case for objects created by create_field() */
 	union acpi_operand_object *buffer_obj;	/* Containing Buffer object */
 };
 
@@ -271,7 +301,8 @@ struct acpi_object_buffer_field {
  *****************************************************************************/
 
 struct acpi_object_notify_handler {
-	ACPI_OBJECT_COMMON_HEADER struct acpi_namespace_node *node;	/* Parent device */
+	ACPI_OBJECT_COMMON_HEADER;
+	struct acpi_namespace_node *node;	/* Parent device */
 	u32 handler_type;	/* Type: Device/System/Both */
 	acpi_notify_handler handler;	/* Handler address */
 	void *context;
@@ -279,11 +310,13 @@ struct acpi_object_notify_handler {
 };
 
 struct acpi_object_addr_handler {
-	ACPI_OBJECT_COMMON_HEADER u8 space_id;
+	ACPI_OBJECT_COMMON_HEADER;
+	u8 space_id;
 	u8 handler_flags;
 	acpi_adr_space_handler handler;
 	struct acpi_namespace_node *node;	/* Parent device */
 	void *context;
+	acpi_mutex context_mutex;
 	acpi_adr_space_setup setup;
 	union acpi_operand_object *region_list;	/* Regions using this handler */
 	union acpi_operand_object *next;
@@ -305,7 +338,8 @@ struct acpi_object_addr_handler {
  * The Reference.Class differentiates these types.
  */
 struct acpi_object_reference {
-	ACPI_OBJECT_COMMON_HEADER u8 class;	/* Reference Class */
+	ACPI_OBJECT_COMMON_HEADER;
+	u8 class;		/* Reference Class */
 	u8 target_type;		/* Used for Index Op */
 	u8 resolved;		/* Reference has been resolved to a value */
 	void *object;		/* name_op=>HANDLE to obj, index_op=>union acpi_operand_object */
@@ -338,7 +372,8 @@ typedef enum {
  * Currently: Region and field_unit types
  */
 struct acpi_object_extra {
-	ACPI_OBJECT_COMMON_HEADER struct acpi_namespace_node *method_REG;	/* _REG method for this region (if any) */
+	ACPI_OBJECT_COMMON_HEADER;
+	struct acpi_namespace_node *method_REG;	/* _REG method for this region (if any) */
 	struct acpi_namespace_node *scope_node;
 	void *region_context;	/* Region-specific data */
 	u8 *aml_start;
@@ -348,14 +383,16 @@ struct acpi_object_extra {
 /* Additional data that can be attached to namespace nodes */
 
 struct acpi_object_data {
-	ACPI_OBJECT_COMMON_HEADER acpi_object_handler handler;
+	ACPI_OBJECT_COMMON_HEADER;
+	acpi_object_handler handler;
 	void *pointer;
 };
 
 /* Structure used when objects are cached for reuse */
 
 struct acpi_object_cache_list {
-	ACPI_OBJECT_COMMON_HEADER union acpi_operand_object *next;	/* Link for object cache and internal lists */
+	ACPI_OBJECT_COMMON_HEADER;
+	union acpi_operand_object *next;	/* Link for object cache and internal lists */
 };
 
 /******************************************************************************
diff --git a/drivers/acpi/acpica/acopcode.h b/drivers/acpi/acpica/acopcode.h
index 8825394be9ab..a2a9e51d7ac6 100644
--- a/drivers/acpi/acpica/acopcode.h
+++ b/drivers/acpi/acpica/acopcode.h
@@ -3,7 +3,7 @@
  *
  * Name: acopcode.h - AML opcode information for the AML parser and interpreter
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/acparser.h b/drivers/acpi/acpica/acparser.h
index bc00b85c0a8f..65a15dee092b 100644
--- a/drivers/acpi/acpica/acparser.h
+++ b/drivers/acpi/acpica/acparser.h
@@ -3,7 +3,7 @@
  *
  * Module Name: acparser.h - AML Parser subcomponent prototypes and defines
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/acpredef.h b/drivers/acpi/acpica/acpredef.h
index cd0f5df0ea23..da2c45880cc7 100644
--- a/drivers/acpi/acpica/acpredef.h
+++ b/drivers/acpi/acpica/acpredef.h
@@ -3,7 +3,7 @@
  *
  * Name: acpredef - Information table for ACPI predefined methods and objects
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -101,7 +101,7 @@ enum acpi_return_package_types {
 
 /* Support macros for users of the predefined info table */
 
-#define METHOD_PREDEF_ARGS_MAX          4
+#define METHOD_PREDEF_ARGS_MAX          5
 #define METHOD_ARG_BIT_WIDTH            3
 #define METHOD_ARG_MASK                 0x0007
 #define ARG_COUNT_IS_MINIMUM            0x8000
@@ -117,6 +117,7 @@ enum acpi_return_package_types {
 #define METHOD_2ARGS(a1,a2)             (2 | (a1 << 3) | (a2 << 6))
 #define METHOD_3ARGS(a1,a2,a3)          (3 | (a1 << 3) | (a2 << 6) | (a3 << 9))
 #define METHOD_4ARGS(a1,a2,a3,a4)       (4 | (a1 << 3) | (a2 << 6) | (a3 << 9) | (a4 << 12))
+#define METHOD_5ARGS(a1,a2,a3,a4,a5)    (5 | (a1 << 3) | (a2 << 6) | (a3 << 9) | (a4 << 12) | (a5 << 15))
 
 #define METHOD_RETURNS(type)            (type)
 #define METHOD_NO_RETURN_VALUE          0
@@ -327,6 +328,17 @@ const union acpi_predefined_info acpi_gbl_predefined_methods[] = {
 	{{"_BMS", METHOD_1ARGS(ACPI_TYPE_INTEGER),
 	  METHOD_RETURNS(ACPI_RTYPE_INTEGER)}},
 
+	{{"_BPC", METHOD_0ARGS,
+	  METHOD_RETURNS(ACPI_RTYPE_PACKAGE)}},	/* Fixed-length (4 Int) */
+	PACKAGE_INFO(ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 4, 0, 0, 0),
+
+	{{"_BPS", METHOD_0ARGS,
+	  METHOD_RETURNS(ACPI_RTYPE_PACKAGE)}},	/* Fixed-length (5 Int) */
+	PACKAGE_INFO(ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 5, 0, 0, 0),
+
+	{{"_BPT", METHOD_1ARGS(ACPI_TYPE_PACKAGE),
+	  METHOD_RETURNS(ACPI_RTYPE_INTEGER)}},
+
 	{{"_BQC", METHOD_0ARGS,
 	  METHOD_RETURNS(ACPI_RTYPE_INTEGER)}},
 
@@ -346,6 +358,10 @@ const union acpi_predefined_info acpi_gbl_predefined_methods[] = {
 	{{"_CBA", METHOD_0ARGS,
 	  METHOD_RETURNS(ACPI_RTYPE_INTEGER)}},	/* See PCI firmware spec 3.0 */
 
+	{{"_CBR", METHOD_0ARGS,
+	  METHOD_RETURNS(ACPI_RTYPE_PACKAGE)}},	/* Fixed-length (3 Int) */
+	PACKAGE_INFO(ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 3, 0, 0, 0),
+
 	{{"_CCA", METHOD_0ARGS,
 	  METHOD_RETURNS(ACPI_RTYPE_INTEGER)}},	/* ACPI 5.1 */
 
@@ -424,6 +440,9 @@ const union acpi_predefined_info acpi_gbl_predefined_methods[] = {
 	{{"_DOS", METHOD_1ARGS(ACPI_TYPE_INTEGER),
 	  METHOD_NO_RETURN_VALUE}},
 
+	{{"_DSC", METHOD_0ARGS,
+	  METHOD_RETURNS(ACPI_RTYPE_INTEGER)}},
+
 	{{"_DSD", METHOD_0ARGS,	/* ACPI 6.0 */
 	  METHOD_RETURNS(ACPI_RTYPE_PACKAGE)}},	/* Variable-length (Pkgs) each: 1 Buf, 1 Pkg */
 	PACKAGE_INFO(ACPI_PTYPE2_UUID_PAIR, ACPI_RTYPE_BUFFER, 1,
@@ -431,7 +450,8 @@ const union acpi_predefined_info acpi_gbl_predefined_methods[] = {
 
 	{{"_DSM",
 	  METHOD_4ARGS(ACPI_TYPE_BUFFER, ACPI_TYPE_INTEGER, ACPI_TYPE_INTEGER,
-		       ACPI_TYPE_PACKAGE),
+		       ACPI_TYPE_ANY | ACPI_TYPE_PACKAGE) |
+		       ARG_COUNT_IS_MINIMUM,
 	  METHOD_RETURNS(ACPI_RTYPE_ALL)}},	/* Must return a value, but it can be of any type */
 
 	{{"_DSS", METHOD_1ARGS(ACPI_TYPE_INTEGER),
@@ -640,10 +660,10 @@ const union acpi_predefined_info acpi_gbl_predefined_methods[] = {
 	{{"_NIC", METHOD_0ARGS,	/* ACPI 6.3 */
 	  METHOD_RETURNS(ACPI_RTYPE_BUFFER)}},
 
-	{{"_NIG", METHOD_1ARGS(ACPI_TYPE_BUFFER),	/* ACPI 6.3 */
+	{{"_NIG", METHOD_0ARGS, /* ACPI 6.3 */
 	  METHOD_RETURNS(ACPI_RTYPE_BUFFER)}},
 
-	{{"_NIH", METHOD_0ARGS,	/* ACPI 6.3 */
+	{{"_NIH", METHOD_1ARGS(ACPI_TYPE_BUFFER), /* ACPI 6.3 */
 	  METHOD_RETURNS(ACPI_RTYPE_BUFFER)}},
 
 	{{"_NTT", METHOD_0ARGS,
@@ -902,9 +922,39 @@ const union acpi_predefined_info acpi_gbl_predefined_methods[] = {
 	{{"_S4W", METHOD_0ARGS,
 	  METHOD_RETURNS(ACPI_RTYPE_INTEGER)}},
 
+	{{"_SBA", METHOD_0ARGS,
+	  METHOD_RETURNS(ACPI_RTYPE_PACKAGE)}},	/* Fixed-length (4 Int) */
+	PACKAGE_INFO(ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 4, 0, 0, 0),
+
+	{{"_SBI", METHOD_0ARGS,
+	  METHOD_RETURNS(ACPI_RTYPE_PACKAGE)}},	/* Fixed-length (1 Int, 1 Buf) */
+	PACKAGE_INFO(ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 1,
+		     ACPI_RTYPE_BUFFER, 1, 0),
+
+	{{"_SBR",
+	  METHOD_3ARGS(ACPI_TYPE_INTEGER, ACPI_TYPE_INTEGER,
+			ACPI_TYPE_INTEGER),
+	   METHOD_RETURNS(ACPI_RTYPE_PACKAGE)}},	/* Fixed-length (2 Int) */
+	PACKAGE_INFO(ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 2,
+		     ACPI_RTYPE_BUFFER | ACPI_RTYPE_INTEGER, 1, 0),
+
 	{{"_SBS", METHOD_0ARGS,
 	  METHOD_RETURNS(ACPI_RTYPE_INTEGER)}},
 
+	{{"_SBT",
+	  METHOD_4ARGS(ACPI_TYPE_INTEGER, ACPI_TYPE_INTEGER, ACPI_TYPE_INTEGER,
+			ACPI_TYPE_ANY),
+	   METHOD_RETURNS(ACPI_RTYPE_PACKAGE)}},	/* Fixed-length (2 Int, 1 Buf | Int) */
+	PACKAGE_INFO(ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 2,
+		     ACPI_RTYPE_BUFFER | ACPI_RTYPE_INTEGER, 1, 0),
+
+	{{"_SBW",
+	  METHOD_5ARGS(ACPI_TYPE_INTEGER, ACPI_TYPE_INTEGER, ACPI_TYPE_INTEGER,
+			ACPI_TYPE_INTEGER, ACPI_TYPE_ANY),
+	   METHOD_RETURNS(ACPI_RTYPE_PACKAGE)}},
+	PACKAGE_INFO(ACPI_PTYPE1_FIXED, ACPI_RTYPE_BUFFER | ACPI_RTYPE_INTEGER,
+		     1, 0, 0, 0),
+
 	{{"_SCP", METHOD_1ARGS(ACPI_TYPE_INTEGER) | ARG_COUNT_IS_MINIMUM,
 	  METHOD_NO_RETURN_VALUE}},	/* Acpi 1.0 allowed 1 integer arg. Acpi 3.0 expanded to 3 args. Allow both. */
 
diff --git a/drivers/acpi/acpica/acresrc.h b/drivers/acpi/acpica/acresrc.h
index 6de8a1650d3d..e8a92be5adae 100644
--- a/drivers/acpi/acpica/acresrc.h
+++ b/drivers/acpi/acpica/acresrc.h
@@ -3,7 +3,7 @@
  *
  * Name: acresrc.h - Resource Manager function prototypes
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -46,6 +46,7 @@ typedef enum {
 	ACPI_RSC_1BITFLAG,
 	ACPI_RSC_2BITFLAG,
 	ACPI_RSC_3BITFLAG,
+	ACPI_RSC_6BITFLAG,
 	ACPI_RSC_ADDRESS,
 	ACPI_RSC_BITMASK,
 	ACPI_RSC_BITMASK16,
@@ -102,6 +103,7 @@ typedef enum {
 	ACPI_RSD_1BITFLAG,
 	ACPI_RSD_2BITFLAG,
 	ACPI_RSD_3BITFLAG,
+	ACPI_RSD_6BITFLAG,
 	ACPI_RSD_ADDRESS,
 	ACPI_RSD_DWORDLIST,
 	ACPI_RSD_LITERAL,
@@ -295,6 +297,7 @@ extern struct acpi_rsconvert_info acpi_rs_convert_address64[];
 extern struct acpi_rsconvert_info acpi_rs_convert_ext_address64[];
 extern struct acpi_rsconvert_info acpi_rs_convert_gpio[];
 extern struct acpi_rsconvert_info acpi_rs_convert_fixed_dma[];
+extern struct acpi_rsconvert_info acpi_rs_convert_csi2_serial_bus[];
 extern struct acpi_rsconvert_info acpi_rs_convert_i2c_serial_bus[];
 extern struct acpi_rsconvert_info acpi_rs_convert_spi_serial_bus[];
 extern struct acpi_rsconvert_info acpi_rs_convert_uart_serial_bus[];
@@ -303,6 +306,7 @@ extern struct acpi_rsconvert_info acpi_rs_convert_pin_config[];
 extern struct acpi_rsconvert_info acpi_rs_convert_pin_group[];
 extern struct acpi_rsconvert_info acpi_rs_convert_pin_group_function[];
 extern struct acpi_rsconvert_info acpi_rs_convert_pin_group_config[];
+extern struct acpi_rsconvert_info acpi_rs_convert_clock_input[];
 
 /* These resources require separate get/set tables */
 
@@ -349,6 +353,7 @@ extern struct acpi_rsdump_info acpi_rs_dump_gpio[];
 extern struct acpi_rsdump_info acpi_rs_dump_pin_function[];
 extern struct acpi_rsdump_info acpi_rs_dump_fixed_dma[];
 extern struct acpi_rsdump_info acpi_rs_dump_common_serial_bus[];
+extern struct acpi_rsdump_info acpi_rs_dump_csi2_serial_bus[];
 extern struct acpi_rsdump_info acpi_rs_dump_i2c_serial_bus[];
 extern struct acpi_rsdump_info acpi_rs_dump_spi_serial_bus[];
 extern struct acpi_rsdump_info acpi_rs_dump_uart_serial_bus[];
@@ -357,6 +362,7 @@ extern struct acpi_rsdump_info acpi_rs_dump_pin_config[];
 extern struct acpi_rsdump_info acpi_rs_dump_pin_group[];
 extern struct acpi_rsdump_info acpi_rs_dump_pin_group_function[];
 extern struct acpi_rsdump_info acpi_rs_dump_pin_group_config[];
+extern struct acpi_rsdump_info acpi_rs_dump_clock_input[];
 #endif
 
 #endif				/* __ACRESRC_H__ */
diff --git a/drivers/acpi/acpica/acstruct.h b/drivers/acpi/acpica/acstruct.h
index 4c900c108f3f..e690f604cfa0 100644
--- a/drivers/acpi/acpica/acstruct.h
+++ b/drivers/acpi/acpica/acstruct.h
@@ -3,7 +3,7 @@
  *
  * Name: acstruct.h - Internal structs
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/actables.h b/drivers/acpi/acpica/actables.h
index 734624facda3..ebef72bf58d0 100644
--- a/drivers/acpi/acpica/actables.h
+++ b/drivers/acpi/acpica/actables.h
@@ -3,7 +3,7 @@
  *
  * Name: actables.h - ACPI table management
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -35,7 +35,8 @@ acpi_tb_init_table_descriptor(struct acpi_table_desc *table_desc,
 
 acpi_status
 acpi_tb_acquire_temp_table(struct acpi_table_desc *table_desc,
-			   acpi_physical_address address, u8 flags);
+			   acpi_physical_address address,
+			   u8 flags, struct acpi_table_header *table);
 
 void acpi_tb_release_temp_table(struct acpi_table_desc *table_desc);
 
@@ -86,6 +87,7 @@ acpi_tb_release_table(struct acpi_table_header *table,
 acpi_status
 acpi_tb_install_standard_table(acpi_physical_address address,
 			       u8 flags,
+			       struct acpi_table_header *table,
 			       u8 reload, u8 override, u32 *table_index);
 
 void acpi_tb_uninstall_table(struct acpi_table_desc *table_desc);
@@ -95,7 +97,9 @@ acpi_tb_load_table(u32 table_index, struct acpi_namespace_node *parent_node);
 
 acpi_status
 acpi_tb_install_and_load_table(acpi_physical_address address,
-			       u8 flags, u8 override, u32 *table_index);
+			       u8 flags,
+			       struct acpi_table_header *table,
+			       u8 override, u32 *table_index);
 
 acpi_status acpi_tb_unload_table(u32 table_index);
 
@@ -120,11 +124,6 @@ void
 acpi_tb_print_table_header(acpi_physical_address address,
 			   struct acpi_table_header *header);
 
-u8 acpi_tb_checksum(u8 *buffer, u32 length);
-
-acpi_status
-acpi_tb_verify_checksum(struct acpi_table_header *table, u32 length);
-
 void acpi_tb_check_dsdt_header(void);
 
 struct acpi_table_header *acpi_tb_copy_dsdt(u32 table_index);
diff --git a/drivers/acpi/acpica/acutils.h b/drivers/acpi/acpica/acutils.h
index 7c89b470ec81..3990d509bbab 100644
--- a/drivers/acpi/acpica/acutils.h
+++ b/drivers/acpi/acpica/acutils.h
@@ -3,7 +3,7 @@
  *
  * Name: acutils.h -- prototypes for the common (subsystem-wide) procedures
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -28,6 +28,7 @@ extern const char *acpi_gbl_max_decode[];
 extern const char *acpi_gbl_mem_decode[];
 extern const char *acpi_gbl_min_decode[];
 extern const char *acpi_gbl_mtp_decode[];
+extern const char *acpi_gbl_phy_decode[];
 extern const char *acpi_gbl_rng_decode[];
 extern const char *acpi_gbl_rw_decode[];
 extern const char *acpi_gbl_shr_decode[];
@@ -52,6 +53,8 @@ extern const char *acpi_gbl_sb_decode[];
 extern const char *acpi_gbl_fc_decode[];
 extern const char *acpi_gbl_pt_decode[];
 extern const char *acpi_gbl_ptyp_decode[];
+extern const char *acpi_gbl_clock_input_mode[];
+extern const char *acpi_gbl_clock_input_scale[];
 #endif
 
 /*
@@ -158,6 +161,19 @@ u8 acpi_ut_valid_name_char(char character, u32 position);
 void acpi_ut_check_and_repair_ascii(u8 *name, char *repaired_name, u32 count);
 
 /*
+ * utcksum - Checksum utilities
+ */
+u8 acpi_ut_generate_checksum(void *table, u32 length, u8 original_checksum);
+
+u8 acpi_ut_checksum(u8 *buffer, u32 length);
+
+acpi_status
+acpi_ut_verify_cdat_checksum(struct acpi_table_cdat *cdat_table, u32 length);
+
+acpi_status
+acpi_ut_verify_checksum(struct acpi_table_header *table, u32 length);
+
+/*
  * utnonansi - Non-ANSI C library functions
  */
 void acpi_ut_strupr(char *src_string);
@@ -736,6 +752,8 @@ const char *acpi_ah_match_uuid(u8 *data);
  */
 #if (defined ACPI_ASL_COMPILER || defined ACPI_EXEC_APP || defined ACPI_HELP_APP)
 void acpi_ut_convert_string_to_uuid(char *in_string, u8 *uuid_buffer);
+
+acpi_status acpi_ut_convert_uuid_to_string(char *uuid_buffer, char *out_string);
 #endif
 
 #endif				/* _ACUTILS_H */
diff --git a/drivers/acpi/acpica/amlcode.h b/drivers/acpi/acpica/amlcode.h
index 1d541bbac4a3..c5b544a006c5 100644
--- a/drivers/acpi/acpica/amlcode.h
+++ b/drivers/acpi/acpica/amlcode.h
@@ -5,7 +5,7 @@
  *                   Declarations and definitions contained herein are derived
  *                   directly from the ACPI specification.
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/amlresrc.h b/drivers/acpi/acpica/amlresrc.h
index e5234e001acf..54d6e51e0b9a 100644
--- a/drivers/acpi/acpica/amlresrc.h
+++ b/drivers/acpi/acpica/amlresrc.h
@@ -3,7 +3,7 @@
  *
  * Module Name: amlresrc.h - AML resource descriptors
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -40,6 +40,7 @@
 #define ACPI_RESTAG_IORESTRICTION               "_IOR"
 #define ACPI_RESTAG_LENGTH                      "_LEN"
 #define ACPI_RESTAG_LINE                        "_LIN"
+#define ACPI_RESTAG_LOCALPORT                   "_PRT"
 #define ACPI_RESTAG_MEMATTRIBUTES               "_MTP"	/* Memory(0), Reserved(1), ACPI(2), NVS(3) */
 #define ACPI_RESTAG_MEMTYPE                     "_MEM"	/* non_cache(0), Cacheable(1) Cache+combine(2), Cache+prefetch(3) */
 #define ACPI_RESTAG_MAXADDR                     "_MAX"
@@ -49,6 +50,7 @@
 #define ACPI_RESTAG_MODE                        "_MOD"
 #define ACPI_RESTAG_PARITY                      "_PAR"
 #define ACPI_RESTAG_PHASE                       "_PHA"
+#define ACPI_RESTAG_PHYTYPE                     "_PHY"
 #define ACPI_RESTAG_PIN                         "_PIN"
 #define ACPI_RESTAG_PINCONFIG                   "_PPI"
 #define ACPI_RESTAG_PINCONFIG_TYPE              "_TYP"
@@ -68,6 +70,8 @@
 #define ACPI_RESTAG_TYPE                        "_TTP"	/* Translation(1), Static (0) */
 #define ACPI_RESTAG_XFERTYPE                    "_SIZ"	/* 8(0), 8And16(1), 16(2) */
 #define ACPI_RESTAG_VENDORDATA                  "_VEN"
+#define ACPI_RESTAG_FQN                         "_FQN"
+#define ACPI_RESTAG_FQD                         "_FQD"
 
 /* Default sizes for "small" resource descriptors */
 
@@ -257,7 +261,10 @@ struct aml_resource_address16 {
 struct aml_resource_extended_irq {
 	AML_RESOURCE_LARGE_HEADER_COMMON u8 flags;
 	u8 interrupt_count;
-	u32 interrupts[1];
+	union {
+		u32 interrupt;
+		 ACPI_FLEX_ARRAY(u32, interrupts);
+	};
 	/* res_source_index, res_source optional fields follow */
 };
 
@@ -316,12 +323,26 @@ struct aml_resource_gpio {
 #define AML_RESOURCE_I2C_SERIALBUSTYPE          1
 #define AML_RESOURCE_SPI_SERIALBUSTYPE          2
 #define AML_RESOURCE_UART_SERIALBUSTYPE         3
-#define AML_RESOURCE_MAX_SERIALBUSTYPE          3
+#define AML_RESOURCE_CSI2_SERIALBUSTYPE         4
+#define AML_RESOURCE_MAX_SERIALBUSTYPE          4
 #define AML_RESOURCE_VENDOR_SERIALBUSTYPE       192	/* Vendor defined is 0xC0-0xFF (NOT SUPPORTED) */
 
 struct aml_resource_common_serialbus {
 AML_RESOURCE_LARGE_HEADER_COMMON AML_RESOURCE_SERIAL_COMMON};
 
+struct aml_resource_csi2_serialbus {
+	AML_RESOURCE_LARGE_HEADER_COMMON AML_RESOURCE_SERIAL_COMMON
+	    /*
+	     * Optional fields follow immediately:
+	     * 1) Vendor Data bytes
+	     * 2) Resource Source String
+	     */
+};
+
+#define AML_RESOURCE_CSI2_REVISION              1	/* ACPI 6.4 */
+#define AML_RESOURCE_CSI2_TYPE_REVISION         1	/* ACPI 6.4 */
+#define AML_RESOURCE_CSI2_MIN_DATA_LEN          0	/* ACPI 6.4 */
+
 struct aml_resource_i2c_serialbus {
 	AML_RESOURCE_LARGE_HEADER_COMMON
 	    AML_RESOURCE_SERIAL_COMMON u32 connection_speed;
@@ -411,6 +432,20 @@ struct aml_resource_pin_config {
 	 */
 };
 
+#define AML_RESOURCE_CLOCK_INPUT_REVISION      1	/* ACPI 6.5 */
+
+struct aml_resource_clock_input {
+	AML_RESOURCE_LARGE_HEADER_COMMON u8 revision_id;
+	u16 flags;
+	u16 frequency_divisor;
+	u32 frequency_numerator;
+	/*
+	 * Optional fields follow immediately:
+	 * 1) Resource Source index
+	 * 2) Resource Source String
+	 */
+};
+
 #define AML_RESOURCE_PIN_CONFIG_REVISION      1	/* ACPI 6.2 */
 
 struct aml_resource_pin_group {
@@ -469,10 +504,6 @@ struct aml_resource_pin_group_config {
 
 #define AML_RESOURCE_PIN_GROUP_CONFIG_REVISION    1	/* ACPI 6.2 */
 
-/* restore default alignment */
-
-#pragma pack()
-
 /* Union of all resource descriptors, so we can allocate the worst case */
 
 union aml_resource {
@@ -510,12 +541,14 @@ union aml_resource {
 	struct aml_resource_i2c_serialbus i2c_serial_bus;
 	struct aml_resource_spi_serialbus spi_serial_bus;
 	struct aml_resource_uart_serialbus uart_serial_bus;
+	struct aml_resource_csi2_serialbus csi2_serial_bus;
 	struct aml_resource_common_serialbus common_serial_bus;
 	struct aml_resource_pin_function pin_function;
 	struct aml_resource_pin_config pin_config;
 	struct aml_resource_pin_group pin_group;
 	struct aml_resource_pin_group_function pin_group_function;
 	struct aml_resource_pin_group_config pin_group_config;
+	struct aml_resource_clock_input clock_input;
 
 	/* Utility overlays */
 
@@ -525,6 +558,10 @@ union aml_resource {
 	u8 byte_item;
 };
 
+/* restore default alignment */
+
+#pragma pack()
+
 /* Interfaces used by both the disassembler and compiler */
 
 void
diff --git a/drivers/acpi/acpica/dbcmds.c b/drivers/acpi/acpica/dbcmds.c
index 9eb68e0751c7..3d99a9048585 100644
--- a/drivers/acpi/acpica/dbcmds.c
+++ b/drivers/acpi/acpica/dbcmds.c
@@ -1010,6 +1010,64 @@ void acpi_db_display_resources(char *object_arg)
 	acpi_db_set_output_destination(ACPI_DB_CONSOLE_OUTPUT);
 }
 
+/*******************************************************************************
+ *
+ * FUNCTION:    acpi_db_generate_ged
+ *
+ * PARAMETERS:  ged_arg             - Raw GED number, ascii string
+ *
+ * RETURN:      None
+ *
+ * DESCRIPTION: Simulate firing of a GED
+ *
+ ******************************************************************************/
+
+void acpi_db_generate_interrupt(char *gsiv_arg)
+{
+	u32 gsiv_number;
+	struct acpi_ged_handler_info *ged_info = acpi_gbl_ged_handler_list;
+
+	if (!ged_info) {
+		acpi_os_printf("No GED handling present\n");
+	}
+
+	gsiv_number = strtoul(gsiv_arg, NULL, 0);
+
+	while (ged_info) {
+
+		if (ged_info->int_id == gsiv_number) {
+			struct acpi_object_list arg_list;
+			union acpi_object arg0;
+			acpi_handle evt_handle = ged_info->evt_method;
+			acpi_status status;
+
+			acpi_os_printf("Evaluate GED _EVT (GSIV=%d)\n",
+				       gsiv_number);
+
+			if (!evt_handle) {
+				acpi_os_printf("Undefined _EVT method\n");
+				return;
+			}
+
+			arg0.integer.type = ACPI_TYPE_INTEGER;
+			arg0.integer.value = gsiv_number;
+
+			arg_list.count = 1;
+			arg_list.pointer = &arg0;
+
+			status =
+			    acpi_evaluate_object(evt_handle, NULL, &arg_list,
+						 NULL);
+			if (ACPI_FAILURE(status)) {
+				acpi_os_printf("Could not evaluate _EVT\n");
+				return;
+			}
+
+		}
+		ged_info = ged_info->next;
+	}
+}
+
 #if (!ACPI_REDUCED_HARDWARE)
 /*******************************************************************************
  *
diff --git a/drivers/acpi/acpica/dbconvert.c b/drivers/acpi/acpica/dbconvert.c
index 2b84ac093698..8dbab6932049 100644
--- a/drivers/acpi/acpica/dbconvert.c
+++ b/drivers/acpi/acpica/dbconvert.c
@@ -174,6 +174,8 @@ acpi_status acpi_db_convert_to_package(char *string, union acpi_object *object)
 	elements =
 	    ACPI_ALLOCATE_ZEROED(DB_DEFAULT_PKG_ELEMENTS *
 				 sizeof(union acpi_object));
+	if (!elements)
+		return (AE_NO_MEMORY);
 
 	this = string;
 	for (i = 0; i < (DB_DEFAULT_PKG_ELEMENTS - 1); i++) {
diff --git a/drivers/acpi/acpica/dbdisply.c b/drivers/acpi/acpica/dbdisply.c
index f2df416d0d2d..d41eb9e67500 100644
--- a/drivers/acpi/acpica/dbdisply.c
+++ b/drivers/acpi/acpica/dbdisply.c
@@ -51,6 +51,8 @@ static acpi_adr_space_type acpi_gbl_space_id_list[] = {
 	ACPI_ADR_SPACE_IPMI,
 	ACPI_ADR_SPACE_GPIO,
 	ACPI_ADR_SPACE_GSBUS,
+	ACPI_ADR_SPACE_PLATFORM_COMM,
+	ACPI_ADR_SPACE_PLATFORM_RT,
 	ACPI_ADR_SPACE_DATA_TABLE,
 	ACPI_ADR_SPACE_FIXED_HARDWARE
 };
diff --git a/drivers/acpi/acpica/dbexec.c b/drivers/acpi/acpica/dbexec.c
index 4027eaab18a4..d3a9521e2dc8 100644
--- a/drivers/acpi/acpica/dbexec.c
+++ b/drivers/acpi/acpica/dbexec.c
@@ -86,7 +86,8 @@ void acpi_db_delete_objects(u32 count, union acpi_object *objects)
  *
  * RETURN:      Status
  *
- * DESCRIPTION: Execute a control method.
+ * DESCRIPTION: Execute a control method. Used to evaluate objects via the
+ *              "EXECUTE" or "EVALUATE" commands.
  *
  ******************************************************************************/
 
@@ -314,11 +315,12 @@ acpi_db_execution_walk(acpi_handle obj_handle,
 
 	status = acpi_evaluate_object(node, NULL, NULL, &return_obj);
 
+	acpi_gbl_method_executing = FALSE;
+
 	acpi_os_printf("Evaluation of [%4.4s] returned %s\n",
 		       acpi_ut_get_node_name(node),
 		       acpi_format_exception(status));
 
-	acpi_gbl_method_executing = FALSE;
 	return (AE_OK);
 }
 
@@ -334,7 +336,8 @@ acpi_db_execution_walk(acpi_handle obj_handle,
  * RETURN:      None
  *
  * DESCRIPTION: Execute a control method. Name is relative to the current
- *              scope.
+ *              scope. Function used for the "EXECUTE", "EVALUATE", and
+ *              "ALL" commands
  *
  ******************************************************************************/
 
@@ -372,6 +375,12 @@ acpi_db_execute(char *name, char **args, acpi_object_type *types, u32 flags)
 		return;
 	}
 
+	if ((flags & EX_ALL) && (strlen(name) > 4)) {
+		acpi_os_printf("Input name (%s) must be a 4-char NameSeg\n",
+			       name);
+		return;
+	}
+
 	name_string = ACPI_ALLOCATE(strlen(name) + 1);
 	if (!name_string) {
 		return;
@@ -389,13 +398,24 @@ acpi_db_execute(char *name, char **args, acpi_object_type *types, u32 flags)
 		return;
 	}
 
-	acpi_gbl_db_method_info.name = name_string;
-	acpi_gbl_db_method_info.args = args;
-	acpi_gbl_db_method_info.types = types;
-	acpi_gbl_db_method_info.flags = flags;
+	/* Command (ALL <nameseg>) to execute all methods of a particular name */
 
-	return_obj.pointer = NULL;
-	return_obj.length = ACPI_ALLOCATE_BUFFER;
+	else if (flags & EX_ALL) {
+		acpi_gbl_db_method_info.name = name_string;
+		return_obj.pointer = NULL;
+		return_obj.length = ACPI_ALLOCATE_BUFFER;
+		acpi_db_evaluate_all(name_string);
+		ACPI_FREE(name_string);
+		return;
+	} else {
+		acpi_gbl_db_method_info.name = name_string;
+		acpi_gbl_db_method_info.args = args;
+		acpi_gbl_db_method_info.types = types;
+		acpi_gbl_db_method_info.flags = flags;
+
+		return_obj.pointer = NULL;
+		return_obj.length = ACPI_ALLOCATE_BUFFER;
+	}
 
 	status = acpi_db_execute_setup(&acpi_gbl_db_method_info);
 	if (ACPI_FAILURE(status)) {
@@ -450,6 +470,7 @@ acpi_db_execute(char *name, char **args, acpi_object_type *types, u32 flags)
 				       (u32)return_obj.length);
 
 			acpi_db_dump_external_object(return_obj.pointer, 1);
+			acpi_os_printf("\n");
 
 			/* Dump a _PLD buffer if present */
 
diff --git a/drivers/acpi/acpica/dbhistry.c b/drivers/acpi/acpica/dbhistry.c
index bb9600b867ee..554ae35108bd 100644
--- a/drivers/acpi/acpica/dbhistry.c
+++ b/drivers/acpi/acpica/dbhistry.c
@@ -3,7 +3,7 @@
  *
  * Module Name: dbhistry - debugger HISTORY command
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -27,7 +27,6 @@ static HISTORY_INFO acpi_gbl_history_buffer[HISTORY_SIZE];
 static u16 acpi_gbl_lo_history = 0;
 static u16 acpi_gbl_num_history = 0;
 static u16 acpi_gbl_next_history_index = 0;
-u32 acpi_gbl_next_cmd_num = 1;
 
 /*******************************************************************************
  *
diff --git a/drivers/acpi/acpica/dbinput.c b/drivers/acpi/acpica/dbinput.c
index ee6a1b77af3f..861b12c334ab 100644
--- a/drivers/acpi/acpica/dbinput.c
+++ b/drivers/acpi/acpica/dbinput.c
@@ -37,6 +37,7 @@ acpi_db_match_command_help(const char *command,
 enum acpi_ex_debugger_commands {
 	CMD_NOT_FOUND = 0,
 	CMD_NULL,
+	CMD_ALL,
 	CMD_ALLOCATIONS,
 	CMD_ARGS,
 	CMD_ARGUMENTS,
@@ -105,6 +106,7 @@ enum acpi_ex_debugger_commands {
 	CMD_THREADS,
 
 	CMD_TEST,
+	CMD_INTERRUPT,
 #endif
 };
 
@@ -115,6 +117,7 @@ enum acpi_ex_debugger_commands {
 static const struct acpi_db_command_info acpi_gbl_db_commands[] = {
 	{"<NOT FOUND>", 0},
 	{"<NULL>", 0},
+	{"ALL", 1},
 	{"ALLOCATIONS", 0},
 	{"ARGS", 0},
 	{"ARGUMENTS", 0},
@@ -183,6 +186,7 @@ static const struct acpi_db_command_info acpi_gbl_db_commands[] = {
 	{"THREADS", 3},
 
 	{"TEST", 1},
+	{"INTERRUPT", 1},
 #endif
 	{NULL, 0}
 };
@@ -222,6 +226,7 @@ static const struct acpi_db_command_help acpi_gbl_db_command_help[] = {
 	{1, "  Type <Object>", "Display object type\n"},
 
 	{0, "\nControl Method Execution:", "\n"},
+	{1, "  All <NameSeg>", "Evaluate all objects named NameSeg\n"},
 	{1, "  Evaluate <Namepath> [Arguments]",
 	 "Evaluate object or control method\n"},
 	{1, "  Execute <Namepath> [Arguments]", "Synonym for Evaluate\n"},
@@ -315,6 +320,7 @@ static const struct acpi_db_command_help acpi_gbl_db_command_help[] = {
 	{1, "  Gpes", "Display info on all GPE devices\n"},
 	{1, "  Sci", "Generate an SCI\n"},
 	{1, "  Sleep [SleepState]", "Simulate sleep/wake sequence(s) (0-5)\n"},
+	{1, "  Interrupt <GSIV>", "Simulate an interrupt\n"},
 #endif
 	{0, NULL, NULL}
 };
@@ -436,7 +442,7 @@ static void acpi_db_display_help(char *command)
 		acpi_os_printf("\n");
 
 	} else {
-		/* Display help for all commands that match the subtring */
+		/* Display help for all commands that match the substring */
 
 		acpi_db_display_command_info(command, TRUE);
 	}
@@ -470,7 +476,7 @@ char *acpi_db_get_next_token(char *string,
 
 	/* Remove any spaces at the beginning, ignore blank lines */
 
-	while (*string && isspace(*string)) {
+	while (*string && isspace((int)*string)) {
 		string++;
 	}
 
@@ -568,7 +574,7 @@ char *acpi_db_get_next_token(char *string,
 
 		/* Find end of token */
 
-		while (*string && !isspace(*string)) {
+		while (*string && !isspace((int)*string)) {
 			string++;
 		}
 		break;
@@ -740,6 +746,15 @@ acpi_db_command_dispatch(char *input_buffer,
 		}
 		break;
 
+	case CMD_ALL:
+
+		acpi_os_printf("Executing all objects with NameSeg: %s\n",
+			       acpi_gbl_db_args[1]);
+		acpi_db_execute(acpi_gbl_db_args[1], &acpi_gbl_db_args[2],
+				&acpi_gbl_db_arg_types[2],
+				EX_NO_SINGLE_STEP | EX_ALL);
+		break;
+
 	case CMD_ALLOCATIONS:
 
 #ifdef ACPI_DBG_TRACK_ALLOCATIONS
@@ -1052,6 +1067,11 @@ acpi_db_command_dispatch(char *input_buffer,
 		acpi_os_printf("Event command not implemented\n");
 		break;
 
+	case CMD_INTERRUPT:
+
+		acpi_db_generate_interrupt(acpi_gbl_db_args[1]);
+		break;
+
 	case CMD_GPE:
 
 		acpi_db_generate_gpe(acpi_gbl_db_args[1], acpi_gbl_db_args[2]);
diff --git a/drivers/acpi/acpica/dbmethod.c b/drivers/acpi/acpica/dbmethod.c
index 4e48a7de7413..889d13828e49 100644
--- a/drivers/acpi/acpica/dbmethod.c
+++ b/drivers/acpi/acpica/dbmethod.c
@@ -21,6 +21,8 @@ static acpi_status
 acpi_db_walk_for_execute(acpi_handle obj_handle,
 			 u32 nesting_level, void *context, void **return_value);
 
+static acpi_status acpi_db_evaluate_object(struct acpi_namespace_node *node);
+
 /*******************************************************************************
  *
  * FUNCTION:    acpi_db_set_method_breakpoint
@@ -346,42 +348,26 @@ acpi_status acpi_db_disassemble_method(char *name)
 
 /*******************************************************************************
  *
- * FUNCTION:    acpi_db_walk_for_execute
+ * FUNCTION:    acpi_db_evaluate_object
  *
- * PARAMETERS:  Callback from walk_namespace
+ * PARAMETERS:  node                - Namespace node for the object
  *
  * RETURN:      Status
  *
- * DESCRIPTION: Batch execution module. Currently only executes predefined
- *              ACPI names.
+ * DESCRIPTION: Main execution function for the Evaluate/Execute/All debugger
+ *              commands.
  *
  ******************************************************************************/
 
-static acpi_status
-acpi_db_walk_for_execute(acpi_handle obj_handle,
-			 u32 nesting_level, void *context, void **return_value)
+static acpi_status acpi_db_evaluate_object(struct acpi_namespace_node *node)
 {
-	struct acpi_namespace_node *node =
-	    (struct acpi_namespace_node *)obj_handle;
-	struct acpi_db_execute_walk *info =
-	    (struct acpi_db_execute_walk *)context;
-	struct acpi_buffer return_obj;
-	acpi_status status;
 	char *pathname;
 	u32 i;
 	struct acpi_device_info *obj_info;
 	struct acpi_object_list param_objects;
 	union acpi_object params[ACPI_METHOD_NUM_ARGS];
-	const union acpi_predefined_info *predefined;
-
-	predefined = acpi_ut_match_predefined_method(node->name.ascii);
-	if (!predefined) {
-		return (AE_OK);
-	}
-
-	if (node->type == ACPI_TYPE_LOCAL_SCOPE) {
-		return (AE_OK);
-	}
+	struct acpi_buffer return_obj;
+	acpi_status status;
 
 	pathname = acpi_ns_get_external_pathname(node);
 	if (!pathname) {
@@ -390,7 +376,7 @@ acpi_db_walk_for_execute(acpi_handle obj_handle,
 
 	/* Get the object info for number of method parameters */
 
-	status = acpi_get_object_info(obj_handle, &obj_info);
+	status = acpi_get_object_info(node, &obj_info);
 	if (ACPI_FAILURE(status)) {
 		ACPI_FREE(pathname);
 		return (status);
@@ -421,14 +407,67 @@ acpi_db_walk_for_execute(acpi_handle obj_handle,
 	acpi_gbl_method_executing = TRUE;
 
 	status = acpi_evaluate_object(node, NULL, &param_objects, &return_obj);
+	acpi_gbl_method_executing = FALSE;
 
 	acpi_os_printf("%-32s returned %s\n", pathname,
 		       acpi_format_exception(status));
-	acpi_gbl_method_executing = FALSE;
+	if (return_obj.length) {
+		acpi_os_printf("Evaluation of %s returned object %p, "
+			       "external buffer length %X\n",
+			       pathname, return_obj.pointer,
+			       (u32)return_obj.length);
+
+		acpi_db_dump_external_object(return_obj.pointer, 1);
+		acpi_os_printf("\n");
+	}
+
 	ACPI_FREE(pathname);
 
 	/* Ignore status from method execution */
 
+	return (AE_OK);
+
+	/* Update count, check if we have executed enough methods */
+
+}
+
+/*******************************************************************************
+ *
+ * FUNCTION:    acpi_db_walk_for_execute
+ *
+ * PARAMETERS:  Callback from walk_namespace
+ *
+ * RETURN:      Status
+ *
+ * DESCRIPTION: Batch execution function. Evaluates all "predefined" objects --
+ *              the nameseg begins with an underscore.
+ *
+ ******************************************************************************/
+
+static acpi_status
+acpi_db_walk_for_execute(acpi_handle obj_handle,
+			 u32 nesting_level, void *context, void **return_value)
+{
+	struct acpi_namespace_node *node =
+	    (struct acpi_namespace_node *)obj_handle;
+	struct acpi_db_execute_walk *info =
+	    (struct acpi_db_execute_walk *)context;
+	acpi_status status;
+	const union acpi_predefined_info *predefined;
+
+	predefined = acpi_ut_match_predefined_method(node->name.ascii);
+	if (!predefined) {
+		return (AE_OK);
+	}
+
+	if (node->type == ACPI_TYPE_LOCAL_SCOPE) {
+		return (AE_OK);
+	}
+
+	acpi_db_evaluate_object(node);
+
+	/* Ignore status from object evaluation */
+
 	status = AE_OK;
 
 	/* Update count, check if we have executed enough methods */
@@ -443,6 +482,52 @@ acpi_db_walk_for_execute(acpi_handle obj_handle,
 
 /*******************************************************************************
  *
+ * FUNCTION:    acpi_db_walk_for_execute_all
+ *
+ * PARAMETERS:  Callback from walk_namespace
+ *
+ * RETURN:      Status
+ *
+ * DESCRIPTION: Batch execution function. Evaluates all objects whose path ends
+ *              with the nameseg "Info->NameSeg". Used for the "ALL" command.
+ *
+ ******************************************************************************/
+
+static acpi_status
+acpi_db_walk_for_execute_all(acpi_handle obj_handle,
+			     u32 nesting_level,
+			     void *context, void **return_value)
+{
+	struct acpi_namespace_node *node =
+	    (struct acpi_namespace_node *)obj_handle;
+	struct acpi_db_execute_walk *info =
+	    (struct acpi_db_execute_walk *)context;
+	acpi_status status;
+
+	if (!ACPI_COMPARE_NAMESEG(node->name.ascii, info->name_seg)) {
+		return (AE_OK);
+	}
+
+	if (node->type == ACPI_TYPE_LOCAL_SCOPE) {
+		return (AE_OK);
+	}
+
+	/* Now evaluate the input object (node) */
+
+	acpi_db_evaluate_object(node);
+
+	/* Ignore status from method execution */
+
+	status = AE_OK;
+
+	/* Update count of executed methods/objects */
+
+	info->count++;
+	return (status);
+}
+
+/*******************************************************************************
+ *
  * FUNCTION:    acpi_db_evaluate_predefined_names
  *
  * PARAMETERS:  None
@@ -470,3 +555,35 @@ void acpi_db_evaluate_predefined_names(void)
 	acpi_os_printf("Evaluated %u predefined names in the namespace\n",
 		       info.count);
 }
+
+/*******************************************************************************
+ *
+ * FUNCTION:    acpi_db_evaluate_all
+ *
+ * PARAMETERS:  none_acpi_gbl_db_method_info
+ *
+ * RETURN:      None
+ *
+ * DESCRIPTION: Namespace batch execution. Implements the "ALL" command.
+ *              Execute all namepaths whose final nameseg matches the
+ *              input nameseg.
+ *
+ ******************************************************************************/
+
+void acpi_db_evaluate_all(char *name_seg)
+{
+	struct acpi_db_execute_walk info;
+
+	info.count = 0;
+	info.max_count = ACPI_UINT32_MAX;
+	ACPI_COPY_NAMESEG(info.name_seg, name_seg);
+	info.name_seg[ACPI_NAMESEG_SIZE] = 0;
+
+	/* Search all nodes in namespace */
+
+	(void)acpi_walk_namespace(ACPI_TYPE_ANY, ACPI_ROOT_OBJECT,
+				  ACPI_UINT32_MAX, acpi_db_walk_for_execute_all,
+				  NULL, (void *)&info, NULL);
+
+	acpi_os_printf("Evaluated %u names in the namespace\n", info.count);
+}
diff --git a/drivers/acpi/acpica/dbnames.c b/drivers/acpi/acpica/dbnames.c
index 3615e1a6efd8..c9131259f717 100644
--- a/drivers/acpi/acpica/dbnames.c
+++ b/drivers/acpi/acpica/dbnames.c
@@ -550,8 +550,12 @@ acpi_db_walk_for_fields(acpi_handle obj_handle,
 	ACPI_FREE(buffer.pointer);
 
 	buffer.length = ACPI_ALLOCATE_LOCAL_BUFFER;
-	acpi_evaluate_object(obj_handle, NULL, NULL, &buffer);
-
+	status = acpi_evaluate_object(obj_handle, NULL, NULL, &buffer);
+	if (ACPI_FAILURE(status)) {
+		acpi_os_printf("Could Not evaluate object %p\n",
+			       obj_handle);
+		return (AE_OK);
+	}
 	/*
 	 * Since this is a field unit, surround the output in braces
 	 */
@@ -652,6 +656,9 @@ acpi_status acpi_db_display_objects(char *obj_type_arg, char *display_count_arg)
 		object_info =
 		    ACPI_ALLOCATE_ZEROED(sizeof(struct acpi_object_info));
 
+		if (!object_info)
+			return (AE_NO_MEMORY);
+
 		/* Walk the namespace from the root */
 
 		(void)acpi_walk_namespace(ACPI_TYPE_ANY, ACPI_ROOT_OBJECT,
diff --git a/drivers/acpi/acpica/dbobject.c b/drivers/acpi/acpica/dbobject.c
index 4b4c530a0654..95ab91b35f29 100644
--- a/drivers/acpi/acpica/dbobject.c
+++ b/drivers/acpi/acpica/dbobject.c
@@ -47,7 +47,7 @@ acpi_db_dump_method_info(acpi_status status, struct acpi_walk_state *walk_state)
 
 	/* Ignore control codes, they are not errors */
 
-	if ((status & AE_CODE_MASK) == AE_CODE_CONTROL) {
+	if (ACPI_CNTL_EXCEPTION(status)) {
 		return;
 	}
 
diff --git a/drivers/acpi/acpica/dsargs.c b/drivers/acpi/acpica/dsargs.c
index ad17f62e51d9..e2f00c54cb36 100644
--- a/drivers/acpi/acpica/dsargs.c
+++ b/drivers/acpi/acpica/dsargs.c
@@ -4,7 +4,7 @@
  * Module Name: dsargs - Support for execution of dynamic arguments for static
  *                       objects (regions, fields, buffer fields, etc.)
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/dscontrol.c b/drivers/acpi/acpica/dscontrol.c
index 4b5b6e859f62..c1f79d7a2026 100644
--- a/drivers/acpi/acpica/dscontrol.c
+++ b/drivers/acpi/acpica/dscontrol.c
@@ -4,7 +4,7 @@
  * Module Name: dscontrol - Support for execution control opcodes -
  *                          if/else/while/return
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -62,7 +62,7 @@ acpi_ds_exec_begin_control_op(struct acpi_walk_state *walk_state,
 			}
 		}
 
-		/*lint -fallthrough */
+		ACPI_FALLTHROUGH;
 
 	case AML_IF_OP:
 		/*
diff --git a/drivers/acpi/acpica/dsdebug.c b/drivers/acpi/acpica/dsdebug.c
index 63bc5f19fb82..274b74255551 100644
--- a/drivers/acpi/acpica/dsdebug.c
+++ b/drivers/acpi/acpica/dsdebug.c
@@ -3,7 +3,7 @@
  *
  * Module Name: dsdebug - Parser/Interpreter interface - debugging
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -100,7 +100,7 @@ acpi_ds_dump_method_stack(acpi_status status,
 
 	/* Ignore control codes, they are not errors */
 
-	if ((status & AE_CODE_MASK) == AE_CODE_CONTROL) {
+	if (ACPI_CNTL_EXCEPTION(status)) {
 		return_VOID;
 	}
 
diff --git a/drivers/acpi/acpica/dsfield.c b/drivers/acpi/acpica/dsfield.c
index c901f5aec739..df132c9089c7 100644
--- a/drivers/acpi/acpica/dsfield.c
+++ b/drivers/acpi/acpica/dsfield.c
@@ -3,7 +3,7 @@
  *
  * Module Name: dsfield - Dispatcher field routines
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -177,7 +177,10 @@ acpi_ds_create_buffer_field(union acpi_parse_object *op,
 					arg->common.value.string, ACPI_TYPE_ANY,
 					ACPI_IMODE_LOAD_PASS1, flags,
 					walk_state, &node);
-		if (ACPI_FAILURE(status)) {
+		if ((walk_state->parse_flags & ACPI_PARSE_DISASSEMBLE)
+		    && status == AE_ALREADY_EXISTS) {
+			status = AE_OK;
+		} else if (ACPI_FAILURE(status)) {
 			ACPI_ERROR_NAMESPACE(walk_state->scope_info,
 					     arg->common.value.string, status);
 			return_ACPI_STATUS(status);
@@ -514,13 +517,20 @@ acpi_ds_create_field(union acpi_parse_object *op,
 	info.region_node = region_node;
 
 	status = acpi_ds_get_field_names(&info, walk_state, arg->common.next);
+	if (ACPI_FAILURE(status)) {
+		return_ACPI_STATUS(status);
+	}
+
 	if (info.region_node->object->region.space_id ==
-	    ACPI_ADR_SPACE_PLATFORM_COMM
-	    && !(region_node->object->field.internal_pcc_buffer =
-		 ACPI_ALLOCATE_ZEROED(info.region_node->object->region.
-				      length))) {
-		return_ACPI_STATUS(AE_NO_MEMORY);
+	    ACPI_ADR_SPACE_PLATFORM_COMM) {
+		region_node->object->field.internal_pcc_buffer =
+		    ACPI_ALLOCATE_ZEROED(info.region_node->object->region.
+					 length);
+		if (!region_node->object->field.internal_pcc_buffer) {
+			return_ACPI_STATUS(AE_NO_MEMORY);
+		}
 	}
+
 	return_ACPI_STATUS(status);
 }
 
diff --git a/drivers/acpi/acpica/dsinit.c b/drivers/acpi/acpica/dsinit.c
index 9be2a309424c..57cd9e2d1109 100644
--- a/drivers/acpi/acpica/dsinit.c
+++ b/drivers/acpi/acpica/dsinit.c
@@ -3,7 +3,7 @@
  *
  * Module Name: dsinit - Object initialization namespace walk
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/dsmethod.c b/drivers/acpi/acpica/dsmethod.c
index cf67caff878a..45ec32e81903 100644
--- a/drivers/acpi/acpica/dsmethod.c
+++ b/drivers/acpi/acpica/dsmethod.c
@@ -3,7 +3,7 @@
  *
  * Module Name: dsmethod - Parser/Interpreter interface - control method parsing
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -462,7 +462,6 @@ acpi_ds_call_control_method(struct acpi_thread_state *thread,
 	struct acpi_walk_state *next_walk_state = NULL;
 	union acpi_operand_object *obj_desc;
 	struct acpi_evaluate_info *info;
-	u32 i;
 
 	ACPI_FUNCTION_TRACE_PTR(ds_call_control_method, this_walk_state);
 
@@ -483,6 +482,20 @@ acpi_ds_call_control_method(struct acpi_thread_state *thread,
 		return_ACPI_STATUS(AE_NULL_OBJECT);
 	}
 
+	if (this_walk_state->num_operands < obj_desc->method.param_count) {
+		ACPI_ERROR((AE_INFO, "Missing argument(s) for method [%4.4s]",
+			    acpi_ut_get_node_name(method_node)));
+
+		return_ACPI_STATUS(AE_AML_TOO_FEW_ARGUMENTS);
+	}
+
+	else if (this_walk_state->num_operands > obj_desc->method.param_count) {
+		ACPI_ERROR((AE_INFO, "Too many arguments for method [%4.4s]",
+			    acpi_ut_get_node_name(method_node)));
+
+		return_ACPI_STATUS(AE_AML_TOO_MANY_ARGUMENTS);
+	}
+
 	/* Init for new method, possibly wait on method mutex */
 
 	status =
@@ -517,7 +530,7 @@ acpi_ds_call_control_method(struct acpi_thread_state *thread,
 	info = ACPI_ALLOCATE_ZEROED(sizeof(struct acpi_evaluate_info));
 	if (!info) {
 		status = AE_NO_MEMORY;
-		goto cleanup;
+		goto pop_walk_state;
 	}
 
 	info->parameters = &this_walk_state->operands[0];
@@ -529,7 +542,7 @@ acpi_ds_call_control_method(struct acpi_thread_state *thread,
 
 	ACPI_FREE(info);
 	if (ACPI_FAILURE(status)) {
-		goto cleanup;
+		goto pop_walk_state;
 	}
 
 	next_walk_state->method_nesting_depth =
@@ -539,14 +552,7 @@ acpi_ds_call_control_method(struct acpi_thread_state *thread,
 	 * Delete the operands on the previous walkstate operand stack
 	 * (they were copied to new objects)
 	 */
-	for (i = 0; i < obj_desc->method.param_count; i++) {
-		acpi_ut_remove_reference(this_walk_state->operands[i]);
-		this_walk_state->operands[i] = NULL;
-	}
-
-	/* Clear the operand stack */
-
-	this_walk_state->num_operands = 0;
+	acpi_ds_clear_operands(this_walk_state);
 
 	ACPI_DEBUG_PRINT((ACPI_DB_DISPATCH,
 			  "**** Begin nested execution of [%4.4s] **** WalkState=%p\n",
@@ -575,6 +581,12 @@ acpi_ds_call_control_method(struct acpi_thread_state *thread,
 
 	return_ACPI_STATUS(status);
 
+pop_walk_state:
+
+	/* On error, pop the walk state to be deleted from thread */
+
+	acpi_ds_pop_walk_state(thread);
+
 cleanup:
 
 	/* On error, we must terminate the method properly */
diff --git a/drivers/acpi/acpica/dsmthdat.c b/drivers/acpi/acpica/dsmthdat.c
index eca50517ad82..5393de4dbc4c 100644
--- a/drivers/acpi/acpica/dsmthdat.c
+++ b/drivers/acpi/acpica/dsmthdat.c
@@ -188,6 +188,7 @@ acpi_ds_method_data_init_args(union acpi_operand_object **params,
 
 		index++;
 	}
+	acpi_ex_trace_args(params, index);
 
 	ACPI_DEBUG_PRINT((ACPI_DB_EXEC, "%u args passed to method\n", index));
 	return_ACPI_STATUS(AE_OK);
diff --git a/drivers/acpi/acpica/dsobject.c b/drivers/acpi/acpica/dsobject.c
index c0a14a6a2c20..1bf7eec49899 100644
--- a/drivers/acpi/acpica/dsobject.c
+++ b/drivers/acpi/acpica/dsobject.c
@@ -3,7 +3,7 @@
  *
  * Module Name: dsobject - Dispatcher object management routines
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/dsopcode.c b/drivers/acpi/acpica/dsopcode.c
index d9c26e720cb7..5699b0872848 100644
--- a/drivers/acpi/acpica/dsopcode.c
+++ b/drivers/acpi/acpica/dsopcode.c
@@ -3,7 +3,7 @@
  *
  * Module Name: dsopcode - Dispatcher support for regions and fields
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -531,6 +531,7 @@ acpi_ds_eval_table_region_operands(struct acpi_walk_state *walk_state,
 
 	obj_desc->region.address = ACPI_PTR_TO_PHYSADDR(table);
 	obj_desc->region.length = table->length;
+	obj_desc->region.pointer = table;
 
 	ACPI_DEBUG_PRINT((ACPI_DB_EXEC, "RgnObj %p Addr %8.8X%8.8X Len %X\n",
 			  obj_desc,
diff --git a/drivers/acpi/acpica/dspkginit.c b/drivers/acpi/acpica/dspkginit.c
index d869568d55c2..1ed2386fab82 100644
--- a/drivers/acpi/acpica/dspkginit.c
+++ b/drivers/acpi/acpica/dspkginit.c
@@ -3,7 +3,7 @@
  *
  * Module Name: dspkginit - Completion of deferred package initialization
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/dsutils.c b/drivers/acpi/acpica/dsutils.c
index fb9ed5e1da89..baf6a1f27605 100644
--- a/drivers/acpi/acpica/dsutils.c
+++ b/drivers/acpi/acpica/dsutils.c
@@ -668,6 +668,8 @@ acpi_ds_create_operands(struct acpi_walk_state *walk_state,
 	union acpi_parse_object *arguments[ACPI_OBJ_NUM_OPERANDS];
 	u32 arg_count = 0;
 	u32 index = walk_state->num_operands;
+	u32 prev_num_operands = walk_state->num_operands;
+	u32 new_num_operands;
 	u32 i;
 
 	ACPI_FUNCTION_TRACE_PTR(ds_create_operands, first_arg);
@@ -696,6 +698,7 @@ acpi_ds_create_operands(struct acpi_walk_state *walk_state,
 
 	/* Create the interpreter arguments, in reverse order */
 
+	new_num_operands = index;
 	index--;
 	for (i = 0; i < arg_count; i++) {
 		arg = arguments[index];
@@ -720,7 +723,11 @@ cleanup:
 	 * pop everything off of the operand stack and delete those
 	 * objects
 	 */
-	acpi_ds_obj_stack_pop_and_delete(arg_count, walk_state);
+	walk_state->num_operands = (u8)(i);
+	acpi_ds_obj_stack_pop_and_delete(new_num_operands, walk_state);
+
+	/* Restore operand count */
+	walk_state->num_operands = (u8)(prev_num_operands);
 
 	ACPI_EXCEPTION((AE_INFO, status, "While creating Arg %u", index));
 	return_ACPI_STATUS(status);
diff --git a/drivers/acpi/acpica/dswexec.c b/drivers/acpi/acpica/dswexec.c
index 1d4f8c81028c..5c5c6d8a4e48 100644
--- a/drivers/acpi/acpica/dswexec.c
+++ b/drivers/acpi/acpica/dswexec.c
@@ -4,7 +4,7 @@
  * Module Name: dswexec - Dispatcher method execution callbacks;
  *                        dispatch to interpreter.
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -30,7 +30,7 @@ static acpi_execute_op acpi_gbl_op_type_dispatch[] = {
 	acpi_ex_opcode_0A_0T_1R,
 	acpi_ex_opcode_1A_0T_0R,
 	acpi_ex_opcode_1A_0T_1R,
-	acpi_ex_opcode_1A_1T_0R,
+	NULL,			/* Was: acpi_ex_opcode_1A_0T_0R (Was for Load operator) */
 	acpi_ex_opcode_1A_1T_1R,
 	acpi_ex_opcode_2A_0T_0R,
 	acpi_ex_opcode_2A_0T_1R,
@@ -389,9 +389,11 @@ acpi_status acpi_ds_exec_end_op(struct acpi_walk_state *walk_state)
 
 		/*
 		 * All opcodes require operand resolution, with the only exceptions
-		 * being the object_type and size_of operators.
+		 * being the object_type and size_of operators as well as opcodes that
+		 * take no arguments.
 		 */
-		if (!(walk_state->op_info->flags & AML_NO_OPERAND_RESOLVE)) {
+		if (!(walk_state->op_info->flags & AML_NO_OPERAND_RESOLVE) &&
+		    (walk_state->op_info->flags & AML_HAS_ARGS)) {
 
 			/* Resolve all operands */
 
@@ -561,11 +563,10 @@ acpi_status acpi_ds_exec_end_op(struct acpi_walk_state *walk_state)
 								op->common.
 								node->object,
 								NULL);
-				if ACPI_FAILURE
-					(status) {
+				if (ACPI_FAILURE(status)) {
 					ACPI_EXCEPTION((AE_INFO, status,
 							"While writing to buffer field"));
-					}
+				}
 			}
 			ACPI_FREE(namepath);
 			status = AE_OK;
@@ -598,8 +599,7 @@ acpi_status acpi_ds_exec_end_op(struct acpi_walk_state *walk_state)
 					break;
 				}
 
-				/* Fall through */
-				/*lint -fallthrough */
+				ACPI_FALLTHROUGH;
 
 			case AML_INT_EVAL_SUBTREE_OP:
 
diff --git a/drivers/acpi/acpica/dswload.c b/drivers/acpi/acpica/dswload.c
index 27069325b6de..666419b6a5c6 100644
--- a/drivers/acpi/acpica/dswload.c
+++ b/drivers/acpi/acpica/dswload.c
@@ -3,7 +3,7 @@
  *
  * Module Name: dswload - Dispatcher first pass namespace load callbacks
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -224,7 +224,7 @@ acpi_ds_load1_begin_op(struct acpi_walk_state *walk_state,
 				break;
 			}
 
-			/*lint -fallthrough */
+			ACPI_FALLTHROUGH;
 
 		default:
 
diff --git a/drivers/acpi/acpica/dswload2.c b/drivers/acpi/acpica/dswload2.c
index edadbe146506..bfc54c914757 100644
--- a/drivers/acpi/acpica/dswload2.c
+++ b/drivers/acpi/acpica/dswload2.c
@@ -3,7 +3,7 @@
  *
  * Module Name: dswload2 - Dispatcher second pass namespace load callbacks
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -214,7 +214,7 @@ acpi_ds_load2_begin_op(struct acpi_walk_state *walk_state,
 				break;
 			}
 
-			/*lint -fallthrough */
+			ACPI_FALLTHROUGH;
 
 		default:
 
diff --git a/drivers/acpi/acpica/dswscope.c b/drivers/acpi/acpica/dswscope.c
index 9c397642fed7..375a8fa43d9d 100644
--- a/drivers/acpi/acpica/dswscope.c
+++ b/drivers/acpi/acpica/dswscope.c
@@ -3,7 +3,7 @@
  *
  * Module Name: dswscope - Scope stack manipulation
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/dswstate.c b/drivers/acpi/acpica/dswstate.c
index 809a0c0536b5..02aaddb89df9 100644
--- a/drivers/acpi/acpica/dswstate.c
+++ b/drivers/acpi/acpica/dswstate.c
@@ -3,7 +3,7 @@
  *
  * Module Name: dswstate - Dispatcher parse tree walk management routines
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -146,8 +146,8 @@ acpi_ds_result_push(union acpi_operand_object *object,
 
 	if (!object) {
 		ACPI_ERROR((AE_INFO,
-			    "Null Object! Obj=%p State=%p Num=%u",
-			    object, walk_state, walk_state->result_count));
+			    "Null Object! State=%p Num=%u",
+			    walk_state, walk_state->result_count));
 		return (AE_BAD_PARAMETER);
 	}
 
@@ -576,9 +576,14 @@ acpi_ds_init_aml_walk(struct acpi_walk_state *walk_state,
 	ACPI_FUNCTION_TRACE(ds_init_aml_walk);
 
 	walk_state->parser_state.aml =
-	    walk_state->parser_state.aml_start = aml_start;
-	walk_state->parser_state.aml_end =
-	    walk_state->parser_state.pkg_end = aml_start + aml_length;
+	    walk_state->parser_state.aml_start =
+	    walk_state->parser_state.aml_end =
+	    walk_state->parser_state.pkg_end = aml_start;
+	/* Avoid undefined behavior: applying zero offset to null pointer */
+	if (aml_length != 0) {
+		walk_state->parser_state.aml_end += aml_length;
+		walk_state->parser_state.pkg_end += aml_length;
+	}
 
 	/* The next_op of the next_walk will be the beginning of the method */
 
diff --git a/drivers/acpi/acpica/evevent.c b/drivers/acpi/acpica/evevent.c
index 9efca54c51ac..6cdd39c987b8 100644
--- a/drivers/acpi/acpica/evevent.c
+++ b/drivers/acpi/acpica/evevent.c
@@ -3,7 +3,7 @@
  *
  * Module Name: evevent - Fixed Event handling and dispatch
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/evglock.c b/drivers/acpi/acpica/evglock.c
index 0ced84ae13e4..df2a4ab0e0da 100644
--- a/drivers/acpi/acpica/evglock.c
+++ b/drivers/acpi/acpica/evglock.c
@@ -3,7 +3,7 @@
  *
  * Module Name: evglock - Global Lock support
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -42,6 +42,10 @@ acpi_status acpi_ev_init_global_lock_handler(void)
 		return_ACPI_STATUS(AE_OK);
 	}
 
+	if (!acpi_gbl_use_global_lock) {
+		return_ACPI_STATUS(AE_OK);
+	}
+
 	/* Attempt installation of the global lock handler */
 
 	status = acpi_install_fixed_event_handler(ACPI_EVENT_GLOBAL,
diff --git a/drivers/acpi/acpica/evgpe.c b/drivers/acpi/acpica/evgpe.c
index 3e39907fedd9..ba65b2ea49b2 100644
--- a/drivers/acpi/acpica/evgpe.c
+++ b/drivers/acpi/acpica/evgpe.c
@@ -3,7 +3,7 @@
  *
  * Module Name: evgpe - General Purpose Event handling and dispatch
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -656,14 +656,14 @@ acpi_ev_detect_gpe(struct acpi_namespace_node *gpe_device,
 
 	/* GPE currently enabled (enable bit == 1)? */
 
-	status = acpi_hw_read(&enable_reg, &gpe_register_info->enable_address);
+	status = acpi_hw_gpe_read(&enable_reg, &gpe_register_info->enable_address);
 	if (ACPI_FAILURE(status)) {
 		goto error_exit;
 	}
 
 	/* GPE currently active (status bit == 1)? */
 
-	status = acpi_hw_read(&status_reg, &gpe_register_info->status_address);
+	status = acpi_hw_gpe_read(&status_reg, &gpe_register_info->status_address);
 	if (ACPI_FAILURE(status)) {
 		goto error_exit;
 	}
diff --git a/drivers/acpi/acpica/evgpeblk.c b/drivers/acpi/acpica/evgpeblk.c
index 132adff1e131..fadd93caf1d5 100644
--- a/drivers/acpi/acpica/evgpeblk.c
+++ b/drivers/acpi/acpica/evgpeblk.c
@@ -3,7 +3,7 @@
  *
  * Module Name: evgpeblk - GPE block creation and initialization.
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -233,12 +233,6 @@ acpi_ev_create_gpe_info_blocks(struct acpi_gpe_block_info *gpe_block)
 
 		this_register->status_address.space_id = gpe_block->space_id;
 		this_register->enable_address.space_id = gpe_block->space_id;
-		this_register->status_address.bit_width =
-		    ACPI_GPE_REGISTER_WIDTH;
-		this_register->enable_address.bit_width =
-		    ACPI_GPE_REGISTER_WIDTH;
-		this_register->status_address.bit_offset = 0;
-		this_register->enable_address.bit_offset = 0;
 
 		/* Init the event_info for each GPE within this register */
 
@@ -251,14 +245,14 @@ acpi_ev_create_gpe_info_blocks(struct acpi_gpe_block_info *gpe_block)
 
 		/* Disable all GPEs within this register */
 
-		status = acpi_hw_write(0x00, &this_register->enable_address);
+		status = acpi_hw_gpe_write(0x00, &this_register->enable_address);
 		if (ACPI_FAILURE(status)) {
 			goto error_exit;
 		}
 
 		/* Clear any pending GPE events within this register */
 
-		status = acpi_hw_write(0xFF, &this_register->status_address);
+		status = acpi_hw_gpe_write(0xFF, &this_register->status_address);
 		if (ACPI_FAILURE(status)) {
 			goto error_exit;
 		}
@@ -317,6 +311,23 @@ acpi_ev_create_gpe_block(struct acpi_namespace_node *gpe_device,
 		return_ACPI_STATUS(AE_OK);
 	}
 
+	/* Validate the space_ID */
+
+	if ((space_id != ACPI_ADR_SPACE_SYSTEM_MEMORY) &&
+	    (space_id != ACPI_ADR_SPACE_SYSTEM_IO)) {
+		ACPI_ERROR((AE_INFO,
+			    "Unsupported address space: 0x%X", space_id));
+		return_ACPI_STATUS(AE_SUPPORT);
+	}
+
+	if (space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
+		status = acpi_hw_validate_io_block(address,
+						   ACPI_GPE_REGISTER_WIDTH,
+						   register_count);
+		if (ACPI_FAILURE(status))
+			return_ACPI_STATUS(status);
+	}
+
 	/* Allocate a new GPE block */
 
 	gpe_block = ACPI_ALLOCATE_ZEROED(sizeof(struct acpi_gpe_block_info));
diff --git a/drivers/acpi/acpica/evgpeinit.c b/drivers/acpi/acpica/evgpeinit.c
index 6effd8076dcc..eb769739420e 100644
--- a/drivers/acpi/acpica/evgpeinit.c
+++ b/drivers/acpi/acpica/evgpeinit.c
@@ -3,7 +3,7 @@
  *
  * Module Name: evgpeinit - System GPE initialization and update
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -32,6 +32,16 @@ ACPI_MODULE_NAME("evgpeinit")
  * kernel boot time as well.
  */
 
+#ifdef ACPI_GPE_USE_LOGICAL_ADDRESSES
+#define ACPI_FADT_GPE_BLOCK_ADDRESS(N)	\
+	acpi_gbl_FADT.xgpe##N##_block.space_id == \
+					ACPI_ADR_SPACE_SYSTEM_MEMORY ? \
+		(u64)acpi_gbl_xgpe##N##_block_logical_address : \
+		acpi_gbl_FADT.xgpe##N##_block.address
+#else
+#define ACPI_FADT_GPE_BLOCK_ADDRESS(N)	acpi_gbl_FADT.xgpe##N##_block.address
+#endif		/* ACPI_GPE_USE_LOGICAL_ADDRESSES */
+
 /*******************************************************************************
  *
  * FUNCTION:    acpi_ev_gpe_initialize
@@ -49,6 +59,7 @@ acpi_status acpi_ev_gpe_initialize(void)
 	u32 register_count1 = 0;
 	u32 gpe_number_max = 0;
 	acpi_status status;
+	u64 address;
 
 	ACPI_FUNCTION_TRACE(ev_gpe_initialize);
 
@@ -85,8 +96,9 @@ acpi_status acpi_ev_gpe_initialize(void)
 	 * If EITHER the register length OR the block address are zero, then that
 	 * particular block is not supported.
 	 */
-	if (acpi_gbl_FADT.gpe0_block_length &&
-	    acpi_gbl_FADT.xgpe0_block.address) {
+	address = ACPI_FADT_GPE_BLOCK_ADDRESS(0);
+
+	if (acpi_gbl_FADT.gpe0_block_length && address) {
 
 		/* GPE block 0 exists (has both length and address > 0) */
 
@@ -97,7 +109,6 @@ acpi_status acpi_ev_gpe_initialize(void)
 		/* Install GPE Block 0 */
 
 		status = acpi_ev_create_gpe_block(acpi_gbl_fadt_gpe_device,
-						  acpi_gbl_FADT.xgpe0_block.
 						  address,
 						  acpi_gbl_FADT.xgpe0_block.
 						  space_id, register_count0, 0,
@@ -110,8 +121,9 @@ acpi_status acpi_ev_gpe_initialize(void)
 		}
 	}
 
-	if (acpi_gbl_FADT.gpe1_block_length &&
-	    acpi_gbl_FADT.xgpe1_block.address) {
+	address = ACPI_FADT_GPE_BLOCK_ADDRESS(1);
+
+	if (acpi_gbl_FADT.gpe1_block_length && address) {
 
 		/* GPE block 1 exists (has both length and address > 0) */
 
@@ -137,7 +149,6 @@ acpi_status acpi_ev_gpe_initialize(void)
 
 			status =
 			    acpi_ev_create_gpe_block(acpi_gbl_fadt_gpe_device,
-						     acpi_gbl_FADT.xgpe1_block.
 						     address,
 						     acpi_gbl_FADT.xgpe1_block.
 						     space_id, register_count1,
@@ -402,6 +413,7 @@ acpi_ev_match_gpe_method(acpi_handle obj_handle,
 	gpe_event_info->flags &= ~(ACPI_GPE_DISPATCH_MASK);
 	gpe_event_info->flags |= (u8)(type | ACPI_GPE_DISPATCH_METHOD);
 	gpe_event_info->dispatch.method_node = method_node;
+	walk_info->count++;
 
 	ACPI_DEBUG_PRINT((ACPI_DB_LOAD,
 			  "Registered GPE method %s as GPE number 0x%.2X\n",
diff --git a/drivers/acpi/acpica/evgpeutil.c b/drivers/acpi/acpica/evgpeutil.c
index 738873e876ca..d15b1d75c8ec 100644
--- a/drivers/acpi/acpica/evgpeutil.c
+++ b/drivers/acpi/acpica/evgpeutil.c
@@ -3,7 +3,7 @@
  *
  * Module Name: evgpeutil - GPE utilities
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/evhandler.c b/drivers/acpi/acpica/evhandler.c
index 5884eba047f7..5a35dae945e2 100644
--- a/drivers/acpi/acpica/evhandler.c
+++ b/drivers/acpi/acpica/evhandler.c
@@ -3,7 +3,7 @@
  *
  * Module Name: evhandler - Support for Address Space handlers
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -386,7 +386,7 @@ acpi_ev_install_space_handler(struct acpi_namespace_node *node,
 		case ACPI_ADR_SPACE_DATA_TABLE:
 
 			handler = acpi_ex_data_table_space_handler;
-			setup = NULL;
+			setup = acpi_ev_data_table_region_setup;
 			break;
 
 		default:
@@ -489,6 +489,13 @@ acpi_ev_install_space_handler(struct acpi_namespace_node *node,
 
 	/* Init handler obj */
 
+	status =
+	    acpi_os_create_mutex(&handler_obj->address_space.context_mutex);
+	if (ACPI_FAILURE(status)) {
+		acpi_ut_remove_reference(handler_obj);
+		goto unlock_and_exit;
+	}
+
 	handler_obj->address_space.space_id = (u8)space_id;
 	handler_obj->address_space.handler_flags = flags;
 	handler_obj->address_space.region_list = NULL;
diff --git a/drivers/acpi/acpica/evmisc.c b/drivers/acpi/acpica/evmisc.c
index ce1eda6beb84..04a23a6c3bb1 100644
--- a/drivers/acpi/acpica/evmisc.c
+++ b/drivers/acpi/acpica/evmisc.c
@@ -3,7 +3,7 @@
  *
  * Module Name: evmisc - Miscellaneous event manager support functions
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/evregion.c b/drivers/acpi/acpica/evregion.c
index 738d4b231f34..fa3475da7ea9 100644
--- a/drivers/acpi/acpica/evregion.c
+++ b/drivers/acpi/acpica/evregion.c
@@ -3,7 +3,7 @@
  *
  * Module Name: evregion - Operation Region support
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -21,7 +21,8 @@ extern u8 acpi_gbl_default_address_spaces[];
 /* Local prototypes */
 
 static void
-acpi_ev_orphan_ec_reg_method(struct acpi_namespace_node *ec_device_node);
+acpi_ev_execute_orphan_reg_method(struct acpi_namespace_node *device_node,
+				  acpi_adr_space_type space_id);
 
 static acpi_status
 acpi_ev_reg_run(acpi_handle obj_handle,
@@ -64,6 +65,7 @@ acpi_status acpi_ev_initialize_op_regions(void)
 						acpi_gbl_default_address_spaces
 						[i])) {
 			acpi_ev_execute_reg_methods(acpi_gbl_root_node,
+						    ACPI_UINT32_MAX,
 						    acpi_gbl_default_address_spaces
 						    [i], ACPI_REG_CONNECT);
 		}
@@ -111,6 +113,8 @@ acpi_ev_address_space_dispatch(union acpi_operand_object *region_obj,
 	union acpi_operand_object *region_obj2;
 	void *region_context = NULL;
 	struct acpi_connection_info *context;
+	acpi_mutex context_mutex;
+	u8 context_locked;
 	acpi_physical_address address;
 
 	ACPI_FUNCTION_TRACE(ev_address_space_dispatch);
@@ -135,6 +139,8 @@ acpi_ev_address_space_dispatch(union acpi_operand_object *region_obj,
 	}
 
 	context = handler_desc->address_space.context;
+	context_mutex = handler_desc->address_space.context_mutex;
+	context_locked = FALSE;
 
 	/*
 	 * It may be the case that the region has never been initialized.
@@ -157,6 +163,25 @@ acpi_ev_address_space_dispatch(union acpi_operand_object *region_obj,
 			return_ACPI_STATUS(AE_NOT_EXIST);
 		}
 
+		if (region_obj->region.space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
+			struct acpi_pcc_info *ctx =
+			    handler_desc->address_space.context;
+
+			ctx->internal_buffer =
+			    field_obj->field.internal_pcc_buffer;
+			ctx->length = (u16)region_obj->region.length;
+			ctx->subspace_id = (u8)region_obj->region.address;
+		}
+
+		if (region_obj->region.space_id ==
+		    ACPI_ADR_SPACE_FIXED_HARDWARE) {
+			struct acpi_ffh_info *ctx =
+			    handler_desc->address_space.context;
+
+			ctx->length = region_obj->region.length;
+			ctx->offset = region_obj->region.address;
+		}
+
 		/*
 		 * We must exit the interpreter because the region setup will
 		 * potentially execute control methods (for example, the _REG method
@@ -203,6 +228,23 @@ acpi_ev_address_space_dispatch(union acpi_operand_object *region_obj,
 	handler = handler_desc->address_space.handler;
 	address = (region_obj->region.address + region_offset);
 
+	ACPI_DEBUG_PRINT((ACPI_DB_OPREGION,
+			  "Handler %p (@%p) Address %8.8X%8.8X [%s]\n",
+			  &region_obj->region.handler->address_space, handler,
+			  ACPI_FORMAT_UINT64(address),
+			  acpi_ut_get_region_name(region_obj->region.
+						  space_id)));
+
+	if (!(handler_desc->address_space.handler_flags &
+	      ACPI_ADDR_HANDLER_DEFAULT_INSTALLED)) {
+		/*
+		 * For handlers other than the default (supplied) handlers, we must
+		 * exit the interpreter because the handler *might* block -- we don't
+		 * know what it will do, so we can't hold the lock on the interpreter.
+		 */
+		acpi_ex_exit_interpreter();
+	}
+
 	/*
 	 * Special handling for generic_serial_bus and general_purpose_io:
 	 * There are three extra parameters that must be passed to the
@@ -211,48 +253,39 @@ acpi_ev_address_space_dispatch(union acpi_operand_object *region_obj,
 	 *   2) Length of the above buffer
 	 *   3) Actual access length from the access_as() op
 	 *
+	 * Since we pass these extra parameters via the context, which is
+	 * shared between threads, we must lock the context to avoid these
+	 * parameters being changed from another thread before the handler
+	 * has completed running.
+	 *
 	 * In addition, for general_purpose_io, the Address and bit_width fields
 	 * are defined as follows:
 	 *   1) Address is the pin number index of the field (bit offset from
 	 *      the previous Connection)
 	 *   2) bit_width is the actual bit length of the field (number of pins)
 	 */
-	if ((region_obj->region.space_id == ACPI_ADR_SPACE_GSBUS) &&
+	if ((region_obj->region.space_id == ACPI_ADR_SPACE_GSBUS ||
+	     region_obj->region.space_id == ACPI_ADR_SPACE_GPIO) &&
 	    context && field_obj) {
 
-		/* Get the Connection (resource_template) buffer */
+		status =
+		    acpi_os_acquire_mutex(context_mutex, ACPI_WAIT_FOREVER);
+		if (ACPI_FAILURE(status)) {
+			goto re_enter_interpreter;
+		}
 
-		context->connection = field_obj->field.resource_buffer;
-		context->length = field_obj->field.resource_length;
-		context->access_length = field_obj->field.access_length;
-	}
-	if ((region_obj->region.space_id == ACPI_ADR_SPACE_GPIO) &&
-	    context && field_obj) {
+		context_locked = TRUE;
 
 		/* Get the Connection (resource_template) buffer */
 
 		context->connection = field_obj->field.resource_buffer;
 		context->length = field_obj->field.resource_length;
 		context->access_length = field_obj->field.access_length;
-		address = field_obj->field.pin_number_index;
-		bit_width = field_obj->field.bit_length;
-	}
-
-	ACPI_DEBUG_PRINT((ACPI_DB_OPREGION,
-			  "Handler %p (@%p) Address %8.8X%8.8X [%s]\n",
-			  &region_obj->region.handler->address_space, handler,
-			  ACPI_FORMAT_UINT64(address),
-			  acpi_ut_get_region_name(region_obj->region.
-						  space_id)));
 
-	if (!(handler_desc->address_space.handler_flags &
-	      ACPI_ADDR_HANDLER_DEFAULT_INSTALLED)) {
-		/*
-		 * For handlers other than the default (supplied) handlers, we must
-		 * exit the interpreter because the handler *might* block -- we don't
-		 * know what it will do, so we can't hold the lock on the interpreter.
-		 */
-		acpi_ex_exit_interpreter();
+		if (region_obj->region.space_id == ACPI_ADR_SPACE_GPIO) {
+			address = field_obj->field.pin_number_index;
+			bit_width = field_obj->field.bit_length;
+		}
 	}
 
 	/* Call the handler */
@@ -260,6 +293,10 @@ acpi_ev_address_space_dispatch(union acpi_operand_object *region_obj,
 	status = handler(function, address, bit_width, value, context,
 			 region_obj2->extra.region_context);
 
+	if (context_locked) {
+		acpi_os_release_mutex(context_mutex);
+	}
+
 	if (ACPI_FAILURE(status)) {
 		ACPI_EXCEPTION((AE_INFO, status, "Returned by Handler for [%s]",
 				acpi_ut_get_region_name(region_obj->region.
@@ -276,6 +313,7 @@ acpi_ev_address_space_dispatch(union acpi_operand_object *region_obj,
 		}
 	}
 
+re_enter_interpreter:
 	if (!(handler_desc->address_space.handler_flags &
 	      ACPI_ADDR_HANDLER_DEFAULT_INSTALLED)) {
 		/*
@@ -635,6 +673,7 @@ cleanup1:
  * FUNCTION:    acpi_ev_execute_reg_methods
  *
  * PARAMETERS:  node            - Namespace node for the device
+ *              max_depth       - Depth to which search for _REG
  *              space_id        - The address space ID
  *              function        - Passed to _REG: On (1) or Off (0)
  *
@@ -646,7 +685,7 @@ cleanup1:
  ******************************************************************************/
 
 void
-acpi_ev_execute_reg_methods(struct acpi_namespace_node *node,
+acpi_ev_execute_reg_methods(struct acpi_namespace_node *node, u32 max_depth,
 			    acpi_adr_space_type space_id, u32 function)
 {
 	struct acpi_reg_walk_info info;
@@ -680,14 +719,16 @@ acpi_ev_execute_reg_methods(struct acpi_namespace_node *node,
 	 * regions and _REG methods. (i.e. handlers must be installed for all
 	 * regions of this Space ID before we can run any _REG methods)
 	 */
-	(void)acpi_ns_walk_namespace(ACPI_TYPE_ANY, node, ACPI_UINT32_MAX,
+	(void)acpi_ns_walk_namespace(ACPI_TYPE_ANY, node, max_depth,
 				     ACPI_NS_WALK_UNLOCK, acpi_ev_reg_run, NULL,
 				     &info, NULL);
 
-	/* Special case for EC: handle "orphan" _REG methods with no region */
-
-	if (space_id == ACPI_ADR_SPACE_EC) {
-		acpi_ev_orphan_ec_reg_method(node);
+	/*
+	 * Special case for EC and GPIO: handle "orphan" _REG methods with
+	 * no region.
+	 */
+	if (space_id == ACPI_ADR_SPACE_EC || space_id == ACPI_ADR_SPACE_GPIO) {
+		acpi_ev_execute_orphan_reg_method(node, space_id);
 	}
 
 	ACPI_DEBUG_PRINT_RAW((ACPI_DB_NAMES,
@@ -760,31 +801,28 @@ acpi_ev_reg_run(acpi_handle obj_handle,
 
 /*******************************************************************************
  *
- * FUNCTION:    acpi_ev_orphan_ec_reg_method
+ * FUNCTION:    acpi_ev_execute_orphan_reg_method
  *
- * PARAMETERS:  ec_device_node      - Namespace node for an EC device
+ * PARAMETERS:  device_node         - Namespace node for an ACPI device
+ *              space_id            - The address space ID
  *
  * RETURN:      None
  *
- * DESCRIPTION: Execute an "orphan" _REG method that appears under the EC
+ * DESCRIPTION: Execute an "orphan" _REG method that appears under an ACPI
  *              device. This is a _REG method that has no corresponding region
- *              within the EC device scope. The orphan _REG method appears to
- *              have been enabled by the description of the ECDT in the ACPI
- *              specification: "The availability of the region space can be
- *              detected by providing a _REG method object underneath the
- *              Embedded Controller device."
- *
- *              To quickly access the EC device, we use the ec_device_node used
- *              during EC handler installation. Otherwise, we would need to
- *              perform a time consuming namespace walk, executing _HID
- *              methods to find the EC device.
+ *              within the device's scope. ACPI tables depending on these
+ *              "orphan" _REG methods have been seen for both EC and GPIO
+ *              Operation Regions. Presumably the Windows ACPI implementation
+ *              always calls the _REG method independent of the presence of
+ *              an actual Operation Region with the correct address space ID.
  *
  *  MUTEX:      Assumes the namespace is locked
  *
  ******************************************************************************/
 
 static void
-acpi_ev_orphan_ec_reg_method(struct acpi_namespace_node *ec_device_node)
+acpi_ev_execute_orphan_reg_method(struct acpi_namespace_node *device_node,
+				  acpi_adr_space_type space_id)
 {
 	acpi_handle reg_method;
 	struct acpi_namespace_node *next_node;
@@ -792,9 +830,9 @@ acpi_ev_orphan_ec_reg_method(struct acpi_namespace_node *ec_device_node)
 	struct acpi_object_list args;
 	union acpi_object objects[2];
 
-	ACPI_FUNCTION_TRACE(ev_orphan_ec_reg_method);
+	ACPI_FUNCTION_TRACE(ev_execute_orphan_reg_method);
 
-	if (!ec_device_node) {
+	if (!device_node) {
 		return_VOID;
 	}
 
@@ -804,7 +842,7 @@ acpi_ev_orphan_ec_reg_method(struct acpi_namespace_node *ec_device_node)
 
 	/* Get a handle to a _REG method immediately under the EC device */
 
-	status = acpi_get_handle(ec_device_node, METHOD_NAME__REG, &reg_method);
+	status = acpi_get_handle(device_node, METHOD_NAME__REG, &reg_method);
 	if (ACPI_FAILURE(status)) {
 		goto exit;	/* There is no _REG method present */
 	}
@@ -816,23 +854,23 @@ acpi_ev_orphan_ec_reg_method(struct acpi_namespace_node *ec_device_node)
 	 * with other space IDs to be present; but the code below will then
 	 * execute the _REG method with the embedded_control space_ID argument.
 	 */
-	next_node = acpi_ns_get_next_node(ec_device_node, NULL);
+	next_node = acpi_ns_get_next_node(device_node, NULL);
 	while (next_node) {
 		if ((next_node->type == ACPI_TYPE_REGION) &&
 		    (next_node->object) &&
-		    (next_node->object->region.space_id == ACPI_ADR_SPACE_EC)) {
+		    (next_node->object->region.space_id == space_id)) {
 			goto exit;	/* Do not execute the _REG */
 		}
 
-		next_node = acpi_ns_get_next_node(ec_device_node, next_node);
+		next_node = acpi_ns_get_next_node(device_node, next_node);
 	}
 
-	/* Evaluate the _REG(embedded_control,Connect) method */
+	/* Evaluate the _REG(space_id,Connect) method */
 
 	args.count = 2;
 	args.pointer = objects;
 	objects[0].type = ACPI_TYPE_INTEGER;
-	objects[0].integer.value = ACPI_ADR_SPACE_EC;
+	objects[0].integer.value = space_id;
 	objects[1].type = ACPI_TYPE_INTEGER;
 	objects[1].integer.value = ACPI_REG_CONNECT;
 
diff --git a/drivers/acpi/acpica/evrgnini.c b/drivers/acpi/acpica/evrgnini.c
index aefc0145e583..b03952798af5 100644
--- a/drivers/acpi/acpica/evrgnini.c
+++ b/drivers/acpi/acpica/evrgnini.c
@@ -3,7 +3,7 @@
  *
  * Module Name: evrgnini- ACPI address_space (op_region) init
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -38,6 +38,7 @@ acpi_ev_system_memory_region_setup(acpi_handle handle,
 	union acpi_operand_object *region_desc =
 	    (union acpi_operand_object *)handle;
 	struct acpi_mem_space_context *local_region_context;
+	struct acpi_mem_mapping *mm;
 
 	ACPI_FUNCTION_TRACE(ev_system_memory_region_setup);
 
@@ -46,13 +47,14 @@ acpi_ev_system_memory_region_setup(acpi_handle handle,
 			local_region_context =
 			    (struct acpi_mem_space_context *)*region_context;
 
-			/* Delete a cached mapping if present */
+			/* Delete memory mappings if present */
 
-			if (local_region_context->mapped_length) {
-				acpi_os_unmap_memory(local_region_context->
-						     mapped_logical_address,
-						     local_region_context->
-						     mapped_length);
+			while (local_region_context->first_mm) {
+				mm = local_region_context->first_mm;
+				local_region_context->first_mm = mm->next_mm;
+				acpi_os_unmap_memory(mm->logical_address,
+						     mm->length);
+				ACPI_FREE(mm);
 			}
 			ACPI_FREE(local_region_context);
 			*region_context = NULL;
@@ -406,6 +408,58 @@ acpi_ev_cmos_region_setup(acpi_handle handle,
 
 /*******************************************************************************
  *
+ * FUNCTION:    acpi_ev_data_table_region_setup
+ *
+ * PARAMETERS:  handle              - Region we are interested in
+ *              function            - Start or stop
+ *              handler_context     - Address space handler context
+ *              region_context      - Region specific context
+ *
+ * RETURN:      Status
+ *
+ * DESCRIPTION: Setup a data_table_region
+ *
+ * MUTEX:       Assumes namespace is not locked
+ *
+ ******************************************************************************/
+
+acpi_status
+acpi_ev_data_table_region_setup(acpi_handle handle,
+				u32 function,
+				void *handler_context, void **region_context)
+{
+	union acpi_operand_object *region_desc =
+	    (union acpi_operand_object *)handle;
+	struct acpi_data_table_mapping *local_region_context;
+
+	ACPI_FUNCTION_TRACE(ev_data_table_region_setup);
+
+	if (function == ACPI_REGION_DEACTIVATE) {
+		if (*region_context) {
+			ACPI_FREE(*region_context);
+			*region_context = NULL;
+		}
+		return_ACPI_STATUS(AE_OK);
+	}
+
+	/* Create a new context */
+
+	local_region_context =
+	    ACPI_ALLOCATE_ZEROED(sizeof(struct acpi_data_table_mapping));
+	if (!(local_region_context)) {
+		return_ACPI_STATUS(AE_NO_MEMORY);
+	}
+
+	/* Save the data table pointer for use in the handler */
+
+	local_region_context->pointer = region_desc->region.pointer;
+
+	*region_context = local_region_context;
+	return_ACPI_STATUS(AE_OK);
+}
+
+/*******************************************************************************
+ *
  * FUNCTION:    acpi_ev_default_region_setup
  *
  * PARAMETERS:  handle              - Region we are interested in
diff --git a/drivers/acpi/acpica/evxface.c b/drivers/acpi/acpica/evxface.c
index e4e012297eee..86a8d41c079c 100644
--- a/drivers/acpi/acpica/evxface.c
+++ b/drivers/acpi/acpica/evxface.c
@@ -3,7 +3,7 @@
  *
  * Module Name: evxface - External interfaces for ACPI events
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/evxfevnt.c b/drivers/acpi/acpica/evxfevnt.c
index 1a15b0087379..4b052908d2e7 100644
--- a/drivers/acpi/acpica/evxfevnt.c
+++ b/drivers/acpi/acpica/evxfevnt.c
@@ -3,7 +3,7 @@
  *
  * Module Name: evxfevnt - External Interfaces, ACPI event disable/enable
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/evxfgpe.c b/drivers/acpi/acpica/evxfgpe.c
index 3be60673e461..60dacec1b121 100644
--- a/drivers/acpi/acpica/evxfgpe.c
+++ b/drivers/acpi/acpica/evxfgpe.c
@@ -3,7 +3,7 @@
  *
  * Module Name: evxfgpe - External Interfaces for General Purpose Events (GPEs)
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/evxfregn.c b/drivers/acpi/acpica/evxfregn.c
index da97fd0c6b51..bccc672c934c 100644
--- a/drivers/acpi/acpica/evxfregn.c
+++ b/drivers/acpi/acpica/evxfregn.c
@@ -4,7 +4,7 @@
  * Module Name: evxfregn - External Interfaces, ACPI Operation Regions and
  *                         Address Spaces.
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -20,13 +20,14 @@ ACPI_MODULE_NAME("evxfregn")
 
 /*******************************************************************************
  *
- * FUNCTION:    acpi_install_address_space_handler
+ * FUNCTION:    acpi_install_address_space_handler_internal
  *
  * PARAMETERS:  device          - Handle for the device
  *              space_id        - The address space ID
  *              handler         - Address of the handler
  *              setup           - Address of the setup function
  *              context         - Value passed to the handler on each access
+ *              Run_reg         - Run _REG methods for this address space?
  *
  * RETURN:      Status
  *
@@ -37,13 +38,16 @@ ACPI_MODULE_NAME("evxfregn")
  * are executed here, and these methods can only be safely executed after
  * the default handlers have been installed and the hardware has been
  * initialized (via acpi_enable_subsystem.)
+ * To avoid this problem pass FALSE for Run_Reg and later on call
+ * acpi_execute_reg_methods() to execute _REG.
  *
  ******************************************************************************/
-acpi_status
-acpi_install_address_space_handler(acpi_handle device,
-				   acpi_adr_space_type space_id,
-				   acpi_adr_space_handler handler,
-				   acpi_adr_space_setup setup, void *context)
+static acpi_status
+acpi_install_address_space_handler_internal(acpi_handle device,
+					    acpi_adr_space_type space_id,
+					    acpi_adr_space_handler handler,
+					    acpi_adr_space_setup setup,
+					    void *context, u8 run_reg)
 {
 	struct acpi_namespace_node *node;
 	acpi_status status;
@@ -80,14 +84,41 @@ acpi_install_address_space_handler(acpi_handle device,
 
 	/* Run all _REG methods for this address space */
 
-	acpi_ev_execute_reg_methods(node, space_id, ACPI_REG_CONNECT);
+	if (run_reg) {
+		acpi_ev_execute_reg_methods(node, ACPI_UINT32_MAX, space_id,
+					    ACPI_REG_CONNECT);
+	}
 
 unlock_and_exit:
 	(void)acpi_ut_release_mutex(ACPI_MTX_NAMESPACE);
 	return_ACPI_STATUS(status);
 }
 
+acpi_status
+acpi_install_address_space_handler(acpi_handle device,
+				   acpi_adr_space_type space_id,
+				   acpi_adr_space_handler handler,
+				   acpi_adr_space_setup setup, void *context)
+{
+	return acpi_install_address_space_handler_internal(device, space_id,
+							   handler, setup,
+							   context, TRUE);
+}
+
 ACPI_EXPORT_SYMBOL(acpi_install_address_space_handler)
+acpi_status
+acpi_install_address_space_handler_no_reg(acpi_handle device,
+					  acpi_adr_space_type space_id,
+					  acpi_adr_space_handler handler,
+					  acpi_adr_space_setup setup,
+					  void *context)
+{
+	return acpi_install_address_space_handler_internal(device, space_id,
+							   handler, setup,
+							   context, FALSE);
+}
+
+ACPI_EXPORT_SYMBOL(acpi_install_address_space_handler_no_reg)
 
 /*******************************************************************************
  *
@@ -226,3 +257,54 @@ unlock_and_exit:
 }
 
 ACPI_EXPORT_SYMBOL(acpi_remove_address_space_handler)
+/*******************************************************************************
+ *
+ * FUNCTION:    acpi_execute_reg_methods
+ *
+ * PARAMETERS:  device          - Handle for the device
+ *              max_depth       - Depth to which search for _REG
+ *              space_id        - The address space ID
+ *
+ * RETURN:      Status
+ *
+ * DESCRIPTION: Execute _REG for all op_regions of a given space_id.
+ *
+ ******************************************************************************/
+acpi_status
+acpi_execute_reg_methods(acpi_handle device, u32 max_depth,
+			 acpi_adr_space_type space_id)
+{
+	struct acpi_namespace_node *node;
+	acpi_status status;
+
+	ACPI_FUNCTION_TRACE(acpi_execute_reg_methods);
+
+	/* Parameter validation */
+
+	if (!device) {
+		return_ACPI_STATUS(AE_BAD_PARAMETER);
+	}
+
+	status = acpi_ut_acquire_mutex(ACPI_MTX_NAMESPACE);
+	if (ACPI_FAILURE(status)) {
+		return_ACPI_STATUS(status);
+	}
+
+	/* Convert and validate the device handle */
+
+	node = acpi_ns_validate_handle(device);
+	if (node) {
+
+		/* Run all _REG methods for this address space */
+
+		acpi_ev_execute_reg_methods(node, max_depth, space_id,
+					    ACPI_REG_CONNECT);
+	} else {
+		status = AE_BAD_PARAMETER;
+	}
+
+	(void)acpi_ut_release_mutex(ACPI_MTX_NAMESPACE);
+	return_ACPI_STATUS(status);
+}
+
+ACPI_EXPORT_SYMBOL(acpi_execute_reg_methods)
diff --git a/drivers/acpi/acpica/exconcat.c b/drivers/acpi/acpica/exconcat.c
index 43711412722f..c248c9b162fa 100644
--- a/drivers/acpi/acpica/exconcat.c
+++ b/drivers/acpi/acpica/exconcat.c
@@ -3,7 +3,7 @@
  *
  * Module Name: exconcat - Concatenate-type AML operators
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/exconfig.c b/drivers/acpi/acpica/exconfig.c
index 68efd704e2dc..4d7dd0fc6b07 100644
--- a/drivers/acpi/acpica/exconfig.c
+++ b/drivers/acpi/acpica/exconfig.c
@@ -3,7 +3,7 @@
  *
  * Module Name: exconfig - Namespace reconfiguration (Load/Unload opcodes)
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -87,11 +87,21 @@ acpi_ex_load_table_op(struct acpi_walk_state *walk_state,
 	struct acpi_namespace_node *parent_node;
 	struct acpi_namespace_node *start_node;
 	struct acpi_namespace_node *parameter_node = NULL;
+	union acpi_operand_object *return_obj;
 	union acpi_operand_object *ddb_handle;
 	u32 table_index;
 
 	ACPI_FUNCTION_TRACE(ex_load_table_op);
 
+	/* Create the return object */
+
+	return_obj = acpi_ut_create_integer_object((u64)0);
+	if (!return_obj) {
+		return_ACPI_STATUS(AE_NO_MEMORY);
+	}
+
+	*return_desc = return_obj;
+
 	/* Find the ACPI table in the RSDT/XSDT */
 
 	acpi_ex_exit_interpreter();
@@ -106,12 +116,6 @@ acpi_ex_load_table_op(struct acpi_walk_state *walk_state,
 
 		/* Table not found, return an Integer=0 and AE_OK */
 
-		ddb_handle = acpi_ut_create_integer_object((u64) 0);
-		if (!ddb_handle) {
-			return_ACPI_STATUS(AE_NO_MEMORY);
-		}
-
-		*return_desc = ddb_handle;
 		return_ACPI_STATUS(AE_OK);
 	}
 
@@ -198,7 +202,13 @@ acpi_ex_load_table_op(struct acpi_walk_state *walk_state,
 		}
 	}
 
-	*return_desc = ddb_handle;
+	/* Remove the reference to ddb_handle created by acpi_ex_add_table above */
+
+	acpi_ut_remove_reference(ddb_handle);
+
+	/* Return -1 (non-zero) indicates success */
+
+	return_obj->integer.value = 0xFFFFFFFFFFFFFFFF;
 	return_ACPI_STATUS(status);
 }
 
@@ -249,7 +259,7 @@ acpi_ex_region_read(union acpi_operand_object *obj_desc, u32 length, u8 *buffer)
  *
  * PARAMETERS:  obj_desc        - Region or Buffer/Field where the table will be
  *                                obtained
- *              target          - Where a handle to the table will be stored
+ *              target          - Where the status of the load will be stored
  *              walk_state      - Current state
  *
  * RETURN:      Status
@@ -278,6 +288,20 @@ acpi_ex_load_op(union acpi_operand_object *obj_desc,
 
 	ACPI_FUNCTION_TRACE(ex_load_op);
 
+	if (target->common.descriptor_type == ACPI_DESC_TYPE_NAMED) {
+		target =
+		    acpi_ns_get_attached_object(ACPI_CAST_PTR
+						(struct acpi_namespace_node,
+						 target));
+	}
+	if (target->common.type != ACPI_TYPE_INTEGER) {
+		ACPI_ERROR((AE_INFO, "Type not integer: %X",
+			    target->common.type));
+		return_ACPI_STATUS(AE_AML_OPERAND_TYPE);
+	}
+
+	target->integer.value = 0;
+
 	/* Source Object can be either an op_region or a Buffer/Field */
 
 	switch (obj_desc->common.type) {
@@ -411,7 +435,7 @@ acpi_ex_load_op(union acpi_operand_object *obj_desc,
 	acpi_ex_exit_interpreter();
 	status = acpi_tb_install_and_load_table(ACPI_PTR_TO_PHYSADDR(table),
 						ACPI_TABLE_ORIGIN_INTERNAL_VIRTUAL,
-						TRUE, &table_index);
+						table, TRUE, &table_index);
 	acpi_ex_enter_interpreter();
 	if (ACPI_FAILURE(status)) {
 
@@ -430,9 +454,6 @@ acpi_ex_load_op(union acpi_operand_object *obj_desc,
 	 */
 	status = acpi_ex_add_table(table_index, &ddb_handle);
 	if (ACPI_FAILURE(status)) {
-
-		/* On error, table_ptr was deallocated above */
-
 		return_ACPI_STATUS(status);
 	}
 
@@ -442,21 +463,13 @@ acpi_ex_load_op(union acpi_operand_object *obj_desc,
 	acpi_ns_initialize_objects();
 	acpi_ex_enter_interpreter();
 
-	/* Store the ddb_handle into the Target operand */
+	/* Remove the reference to ddb_handle created by acpi_ex_add_table above */
 
-	status = acpi_ex_store(ddb_handle, target, walk_state);
-	if (ACPI_FAILURE(status)) {
-		(void)acpi_ex_unload_table(ddb_handle);
-
-		/* table_ptr was deallocated above */
-
-		acpi_ut_remove_reference(ddb_handle);
-		return_ACPI_STATUS(status);
-	}
+	acpi_ut_remove_reference(ddb_handle);
 
-	/* Remove the reference by added by acpi_ex_store above */
+	/* Return -1 (non-zero) indicates success */
 
-	acpi_ut_remove_reference(ddb_handle);
+	target->integer.value = 0xFFFFFFFFFFFFFFFF;
 	return_ACPI_STATUS(status);
 }
 
diff --git a/drivers/acpi/acpica/exconvrt.c b/drivers/acpi/acpica/exconvrt.c
index 50c7aad2e86d..fded9bfc2436 100644
--- a/drivers/acpi/acpica/exconvrt.c
+++ b/drivers/acpi/acpica/exconvrt.c
@@ -3,7 +3,7 @@
  *
  * Module Name: exconvrt - Object conversion routines
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -17,7 +17,8 @@ ACPI_MODULE_NAME("exconvrt")
 
 /* Local prototypes */
 static u32
-acpi_ex_convert_to_ascii(u64 integer, u16 base, u8 *string, u8 max_length);
+acpi_ex_convert_to_ascii(u64 integer,
+			 u16 base, u8 *string, u8 max_length, u8 leading_zeros);
 
 /*******************************************************************************
  *
@@ -225,8 +226,8 @@ acpi_ex_convert_to_buffer(union acpi_operand_object *obj_desc,
 		/* Copy the string to the buffer */
 
 		new_buf = return_desc->buffer.pointer;
-		strncpy((char *)new_buf, (char *)obj_desc->string.pointer,
-			obj_desc->string.length);
+		memcpy((char *)new_buf, (char *)obj_desc->string.pointer,
+		       obj_desc->string.length);
 		break;
 
 	default:
@@ -249,6 +250,7 @@ acpi_ex_convert_to_buffer(union acpi_operand_object *obj_desc,
  *              base            - ACPI_STRING_DECIMAL or ACPI_STRING_HEX
  *              string          - Where the string is returned
  *              data_width      - Size of data item to be converted, in bytes
+ *              leading_zeros   - Allow leading zeros
  *
  * RETURN:      Actual string length
  *
@@ -257,7 +259,8 @@ acpi_ex_convert_to_buffer(union acpi_operand_object *obj_desc,
  ******************************************************************************/
 
 static u32
-acpi_ex_convert_to_ascii(u64 integer, u16 base, u8 *string, u8 data_width)
+acpi_ex_convert_to_ascii(u64 integer,
+			 u16 base, u8 *string, u8 data_width, u8 leading_zeros)
 {
 	u64 digit;
 	u32 i;
@@ -266,7 +269,8 @@ acpi_ex_convert_to_ascii(u64 integer, u16 base, u8 *string, u8 data_width)
 	u32 hex_length;
 	u32 decimal_length;
 	u32 remainder;
-	u8 supress_zeros;
+	u8 supress_zeros = !leading_zeros;
+	u8 hex_char;
 
 	ACPI_FUNCTION_ENTRY();
 
@@ -293,7 +297,6 @@ acpi_ex_convert_to_ascii(u64 integer, u16 base, u8 *string, u8 data_width)
 			break;
 		}
 
-		supress_zeros = TRUE;	/* No leading zeros */
 		remainder = 0;
 
 		for (i = decimal_length; i > 0; i--) {
@@ -328,8 +331,17 @@ acpi_ex_convert_to_ascii(u64 integer, u16 base, u8 *string, u8 data_width)
 
 			/* Get one hex digit, most significant digits first */
 
-			string[k] = (u8)
+			hex_char = (u8)
 			    acpi_ut_hex_to_ascii_char(integer, ACPI_MUL_4(j));
+
+			/* Supress leading zeros until the first non-zero character */
+
+			if (hex_char == ACPI_ASCII_ZERO && supress_zeros) {
+				continue;
+			}
+
+			supress_zeros = FALSE;
+			string[k] = hex_char;
 			k++;
 		}
 		break;
@@ -379,6 +391,7 @@ acpi_ex_convert_to_string(union acpi_operand_object * obj_desc,
 	u32 string_length = 0;
 	u16 base = 16;
 	u8 separator = ',';
+	u8 leading_zeros;
 
 	ACPI_FUNCTION_TRACE_PTR(ex_convert_to_string, obj_desc);
 
@@ -400,14 +413,26 @@ acpi_ex_convert_to_string(union acpi_operand_object * obj_desc,
 			 * Make room for the maximum decimal number size
 			 */
 			string_length = ACPI_MAX_DECIMAL_DIGITS;
+			leading_zeros = FALSE;
 			base = 10;
 			break;
 
+		case ACPI_EXPLICIT_CONVERT_HEX:
+			/*
+			 * From to_hex_string.
+			 *
+			 * Supress leading zeros and append "0x"
+			 */
+			string_length =
+			    ACPI_MUL_2(acpi_gbl_integer_byte_width) + 2;
+			leading_zeros = FALSE;
+			break;
 		default:
 
 			/* Two hex string characters for each integer byte */
 
 			string_length = ACPI_MUL_2(acpi_gbl_integer_byte_width);
+			leading_zeros = TRUE;
 			break;
 		}
 
@@ -422,17 +447,32 @@ acpi_ex_convert_to_string(union acpi_operand_object * obj_desc,
 		}
 
 		new_buf = return_desc->buffer.pointer;
+		if (type == ACPI_EXPLICIT_CONVERT_HEX) {
+
+			/* Append "0x" prefix for explicit hex conversion */
+
+			*new_buf++ = '0';
+			*new_buf++ = 'x';
+		}
 
 		/* Convert integer to string */
 
 		string_length =
 		    acpi_ex_convert_to_ascii(obj_desc->integer.value, base,
 					     new_buf,
-					     acpi_gbl_integer_byte_width);
+					     acpi_gbl_integer_byte_width,
+					     leading_zeros);
 
 		/* Null terminate at the correct place */
 
 		return_desc->string.length = string_length;
+		if (type == ACPI_EXPLICIT_CONVERT_HEX) {
+
+			/* Take "0x" prefix into account */
+
+			return_desc->string.length += 2;
+		}
+
 		new_buf[string_length] = 0;
 		break;
 
@@ -448,6 +488,7 @@ acpi_ex_convert_to_string(union acpi_operand_object * obj_desc,
 			 * From ACPI: "If the input is a buffer, it is converted to a
 			 * a string of decimal values separated by commas."
 			 */
+			leading_zeros = FALSE;
 			base = 10;
 
 			/*
@@ -475,6 +516,7 @@ acpi_ex_convert_to_string(union acpi_operand_object * obj_desc,
 			 *
 			 * Each hex number is prefixed with 0x (11/2018)
 			 */
+			leading_zeros = TRUE;
 			separator = ' ';
 			string_length = (obj_desc->buffer.length * 5);
 			break;
@@ -488,6 +530,7 @@ acpi_ex_convert_to_string(union acpi_operand_object * obj_desc,
 			 *
 			 * Each hex number is prefixed with 0x (11/2018)
 			 */
+			leading_zeros = TRUE;
 			separator = ',';
 			string_length = (obj_desc->buffer.length * 5);
 			break;
@@ -528,7 +571,8 @@ acpi_ex_convert_to_string(union acpi_operand_object * obj_desc,
 
 			new_buf += acpi_ex_convert_to_ascii((u64) obj_desc->
 							    buffer.pointer[i],
-							    base, new_buf, 1);
+							    base, new_buf, 1,
+							    leading_zeros);
 
 			/* Each digit is separated by either a comma or space */
 
diff --git a/drivers/acpi/acpica/excreate.c b/drivers/acpi/acpica/excreate.c
index a17482428b46..052c69567997 100644
--- a/drivers/acpi/acpica/excreate.c
+++ b/drivers/acpi/acpica/excreate.c
@@ -3,7 +3,7 @@
  *
  * Module Name: excreate - Named object creation
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -279,6 +279,7 @@ acpi_ex_create_region(u8 * aml_start,
 	obj_desc->region.space_id = space_id;
 	obj_desc->region.address = 0;
 	obj_desc->region.length = 0;
+	obj_desc->region.pointer = NULL;
 	obj_desc->region.node = node;
 	obj_desc->region.handler = NULL;
 	obj_desc->common.flags &=
diff --git a/drivers/acpi/acpica/exdebug.c b/drivers/acpi/acpica/exdebug.c
index a5223dcaee70..81a07a52b73c 100644
--- a/drivers/acpi/acpica/exdebug.c
+++ b/drivers/acpi/acpica/exdebug.c
@@ -3,7 +3,7 @@
  *
  * Module Name: exdebug - Support for stores to the AML Debug Object
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/exdump.c b/drivers/acpi/acpica/exdump.c
index 47a4d9a40d6b..d8aeebaab70a 100644
--- a/drivers/acpi/acpica/exdump.c
+++ b/drivers/acpi/acpica/exdump.c
@@ -3,7 +3,7 @@
  *
  * Module Name: exdump - Interpreter debug output routines
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/exfield.c b/drivers/acpi/acpica/exfield.c
index e85eb31e5075..ced3ff9d0a86 100644
--- a/drivers/acpi/acpica/exfield.c
+++ b/drivers/acpi/acpica/exfield.c
@@ -3,7 +3,7 @@
  *
  * Module Name: exfield - AML execution - field_unit read/write
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -22,7 +22,7 @@ ACPI_MODULE_NAME("exfield")
  */
 #define ACPI_INVALID_PROTOCOL_ID        0x80
 #define ACPI_MAX_PROTOCOL_ID            0x0F
-const u8 acpi_protocol_lengths[] = {
+static const u8 acpi_protocol_lengths[] = {
 	ACPI_INVALID_PROTOCOL_ID,	/* 0 - reserved */
 	ACPI_INVALID_PROTOCOL_ID,	/* 1 - reserved */
 	0x00,			/* 2 - ATTRIB_QUICK */
@@ -139,7 +139,11 @@ acpi_ex_read_data_from_field(struct acpi_walk_state *walk_state,
 		    || obj_desc->field.region_obj->region.space_id ==
 		    ACPI_ADR_SPACE_GSBUS
 		    || obj_desc->field.region_obj->region.space_id ==
-		    ACPI_ADR_SPACE_IPMI)) {
+		    ACPI_ADR_SPACE_IPMI
+		    || obj_desc->field.region_obj->region.space_id ==
+		    ACPI_ADR_SPACE_PLATFORM_RT
+		    || obj_desc->field.region_obj->region.space_id ==
+		    ACPI_ADR_SPACE_FIXED_HARDWARE)) {
 
 		/* SMBus, GSBus, IPMI serial */
 
@@ -301,7 +305,11 @@ acpi_ex_write_data_to_field(union acpi_operand_object *source_desc,
 		    || obj_desc->field.region_obj->region.space_id ==
 		    ACPI_ADR_SPACE_GSBUS
 		    || obj_desc->field.region_obj->region.space_id ==
-		    ACPI_ADR_SPACE_IPMI)) {
+		    ACPI_ADR_SPACE_IPMI
+		    || obj_desc->field.region_obj->region.space_id ==
+		    ACPI_ADR_SPACE_PLATFORM_RT
+		    || obj_desc->field.region_obj->region.space_id ==
+		    ACPI_ADR_SPACE_FIXED_HARDWARE)) {
 
 		/* SMBus, GSBus, IPMI serial */
 
@@ -326,12 +334,7 @@ acpi_ex_write_data_to_field(union acpi_operand_object *source_desc,
 		       obj_desc->field.base_byte_offset,
 		       source_desc->buffer.pointer, data_length);
 
-		if ((obj_desc->field.region_obj->region.address ==
-		     PCC_MASTER_SUBSPACE
-		     && MASTER_SUBSPACE_COMMAND(obj_desc->field.
-						base_byte_offset))
-		    || GENERIC_SUBSPACE_COMMAND(obj_desc->field.
-						base_byte_offset)) {
+		if (MASTER_SUBSPACE_COMMAND(obj_desc->field.base_byte_offset)) {
 
 			/* Perform the write */
 
diff --git a/drivers/acpi/acpica/exfldio.c b/drivers/acpi/acpica/exfldio.c
index ade35ff1c7ba..0771934c0455 100644
--- a/drivers/acpi/acpica/exfldio.c
+++ b/drivers/acpi/acpica/exfldio.c
@@ -3,7 +3,7 @@
  *
  * Module Name: exfldio - Aml Field I/O
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -104,7 +104,7 @@ acpi_ex_setup_region(union acpi_operand_object *obj_desc,
 #ifdef ACPI_UNDER_DEVELOPMENT
 	/*
 	 * If the Field access is any_acc, we can now compute the optimal
-	 * access (because we know know the length of the parent region)
+	 * access (because we know the length of the parent region)
 	 */
 	if (!(obj_desc->common.flags & AOPOBJ_DATA_VALID)) {
 		if (ACPI_FAILURE(status)) {
@@ -434,7 +434,7 @@ acpi_ex_field_datum_io(union acpi_operand_object *obj_desc,
 		 * region_field case and write the datum to the Operation Region
 		 */
 
-		/*lint -fallthrough */
+		ACPI_FALLTHROUGH;
 
 	case ACPI_TYPE_LOCAL_REGION_FIELD:
 		/*
diff --git a/drivers/acpi/acpica/exmisc.c b/drivers/acpi/acpica/exmisc.c
index 717e3998fd77..07cbac58ed21 100644
--- a/drivers/acpi/acpica/exmisc.c
+++ b/drivers/acpi/acpica/exmisc.c
@@ -3,7 +3,7 @@
  *
  * Module Name: exmisc - ACPI AML (p-code) execution - specific opcodes
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/exmutex.c b/drivers/acpi/acpica/exmutex.c
index 9ff247cba571..1fa013197fcf 100644
--- a/drivers/acpi/acpica/exmutex.c
+++ b/drivers/acpi/acpica/exmutex.c
@@ -3,7 +3,7 @@
  *
  * Module Name: exmutex - ASL Mutex Acquire/Release functions
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/exnames.c b/drivers/acpi/acpica/exnames.c
index 74f8b0d0452b..76ab73c37e90 100644
--- a/drivers/acpi/acpica/exnames.c
+++ b/drivers/acpi/acpica/exnames.c
@@ -3,7 +3,7 @@
  *
  * Module Name: exnames - interpreter/scanner name load/execute
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/exoparg1.c b/drivers/acpi/acpica/exoparg1.c
index a46d685a3ffc..6ac7e0ca5c9d 100644
--- a/drivers/acpi/acpica/exoparg1.c
+++ b/drivers/acpi/acpica/exoparg1.c
@@ -3,7 +3,7 @@
  *
  * Module Name: exoparg1 - AML execution - opcodes with 1 argument
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -163,6 +163,7 @@ acpi_status acpi_ex_opcode_1A_0T_0R(struct acpi_walk_state *walk_state)
 	return_ACPI_STATUS(status);
 }
 
+#ifdef _OBSOLETE_CODE		/* Was originally used for Load() operator */
 /*******************************************************************************
  *
  * FUNCTION:    acpi_ex_opcode_1A_1T_0R
@@ -187,10 +188,12 @@ acpi_status acpi_ex_opcode_1A_1T_0R(struct acpi_walk_state *walk_state)
 	/* Examine the AML opcode */
 
 	switch (walk_state->opcode) {
+#ifdef _OBSOLETE_CODE
 	case AML_LOAD_OP:
 
 		status = acpi_ex_load_op(operand[0], operand[1], walk_state);
 		break;
+#endif
 
 	default:		/* Unknown opcode */
 
@@ -204,6 +207,7 @@ cleanup:
 
 	return_ACPI_STATUS(status);
 }
+#endif
 
 /*******************************************************************************
  *
@@ -215,6 +219,8 @@ cleanup:
  *
  * DESCRIPTION: Execute opcode with one argument, one target, and a
  *              return value.
+ *              January 2022: Added Load operator, with new ACPI 6.4
+ *              semantics.
  *
  ******************************************************************************/
 
@@ -239,6 +245,7 @@ acpi_status acpi_ex_opcode_1A_1T_1R(struct acpi_walk_state *walk_state)
 	case AML_FIND_SET_LEFT_BIT_OP:
 	case AML_FIND_SET_RIGHT_BIT_OP:
 	case AML_FROM_BCD_OP:
+	case AML_LOAD_OP:
 	case AML_TO_BCD_OP:
 	case AML_CONDITIONAL_REF_OF_OP:
 
@@ -338,6 +345,20 @@ acpi_status acpi_ex_opcode_1A_1T_1R(struct acpi_walk_state *walk_state)
 			}
 			break;
 
+		case AML_LOAD_OP:	/* Result1 = Load (Operand[0], Result1) */
+
+			return_desc->integer.value = 0;
+			status =
+			    acpi_ex_load_op(operand[0], return_desc,
+					    walk_state);
+			if (ACPI_SUCCESS(status)) {
+
+				/* Return -1 (non-zero) indicates success */
+
+				return_desc->integer.value = 0xFFFFFFFFFFFFFFFF;
+			}
+			break;
+
 		case AML_TO_BCD_OP:	/* to_bcd (Operand, Result) */
 
 			return_desc->integer.value = 0;
@@ -1007,7 +1028,8 @@ acpi_status acpi_ex_opcode_1A_0T_1R(struct acpi_walk_state *walk_state)
 						    (walk_state, return_desc,
 						     &temp_desc);
 						if (ACPI_FAILURE(status)) {
-							goto cleanup;
+							return_ACPI_STATUS
+							    (status);
 						}
 
 						return_desc = temp_desc;
diff --git a/drivers/acpi/acpica/exoparg2.c b/drivers/acpi/acpica/exoparg2.c
index 03241d18ac1d..a94fa4d70e99 100644
--- a/drivers/acpi/acpica/exoparg2.c
+++ b/drivers/acpi/acpica/exoparg2.c
@@ -3,7 +3,7 @@
  *
  * Module Name: exoparg2 - AML execution - opcodes with 2 arguments
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/exoparg3.c b/drivers/acpi/acpica/exoparg3.c
index c8d0d75fc450..bf08110ed6d2 100644
--- a/drivers/acpi/acpica/exoparg3.c
+++ b/drivers/acpi/acpica/exoparg3.c
@@ -3,7 +3,7 @@
  *
  * Module Name: exoparg3 - AML execution - opcodes with 3 arguments
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/exoparg6.c b/drivers/acpi/acpica/exoparg6.c
index 55d0fa056fe7..cb078e39abf7 100644
--- a/drivers/acpi/acpica/exoparg6.c
+++ b/drivers/acpi/acpica/exoparg6.c
@@ -3,7 +3,7 @@
  *
  * Module Name: exoparg6 - AML execution - opcodes with 6 arguments
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/exprep.c b/drivers/acpi/acpica/exprep.c
index a4e306690a21..1b1a006e82de 100644
--- a/drivers/acpi/acpica/exprep.c
+++ b/drivers/acpi/acpica/exprep.c
@@ -3,7 +3,7 @@
  *
  * Module Name: exprep - ACPI AML field prep utilities
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -437,6 +437,9 @@ acpi_status acpi_ex_prep_field_value(struct acpi_create_field_info *info)
 
 		if (info->connection_node) {
 			second_desc = info->connection_node->object;
+			if (second_desc == NULL) {
+				break;
+			}
 			if (!(second_desc->common.flags & AOPOBJ_DATA_VALID)) {
 				status =
 				    acpi_ds_get_buffer_arguments(second_desc);
@@ -473,10 +476,6 @@ acpi_status acpi_ex_prep_field_value(struct acpi_create_field_info *info)
 				    (u8)access_byte_width;
 			}
 		}
-		/* An additional reference for the container */
-
-		acpi_ut_add_reference(obj_desc->field.region_obj);
-
 		ACPI_DEBUG_PRINT((ACPI_DB_BFIELD,
 				  "RegionField: BitOff %X, Off %X, Gran %X, Region %p\n",
 				  obj_desc->field.start_field_bit_offset,
diff --git a/drivers/acpi/acpica/exregion.c b/drivers/acpi/acpica/exregion.c
index d15a66de26c0..a390a1c2b0ab 100644
--- a/drivers/acpi/acpica/exregion.c
+++ b/drivers/acpi/acpica/exregion.c
@@ -3,7 +3,7 @@
  *
  * Module Name: exregion - ACPI default op_region (address space) handlers
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -41,9 +41,9 @@ acpi_ex_system_memory_space_handler(u32 function,
 	acpi_status status = AE_OK;
 	void *logical_addr_ptr = NULL;
 	struct acpi_mem_space_context *mem_info = region_context;
+	struct acpi_mem_mapping *mm = mem_info->cur_mm;
 	u32 length;
 	acpi_size map_length;
-	acpi_size page_boundary_map_length;
 #ifdef ACPI_MISALIGNMENT_NOT_SUPPORTED
 	u32 remainder;
 #endif
@@ -96,20 +96,37 @@ acpi_ex_system_memory_space_handler(u32 function,
 	 * Is 1) Address below the current mapping? OR
 	 *    2) Address beyond the current mapping?
 	 */
-	if ((address < mem_info->mapped_physical_address) ||
-	    (((u64) address + length) > ((u64)
-					 mem_info->mapped_physical_address +
-					 mem_info->mapped_length))) {
+	if (!mm || (address < mm->physical_address) ||
+	    ((u64) address + length > (u64) mm->physical_address + mm->length)) {
 		/*
-		 * The request cannot be resolved by the current memory mapping;
-		 * Delete the existing mapping and create a new one.
+		 * The request cannot be resolved by the current memory mapping.
+		 *
+		 * Look for an existing saved mapping covering the address range
+		 * at hand.  If found, save it as the current one and carry out
+		 * the access.
 		 */
-		if (mem_info->mapped_length) {
+		for (mm = mem_info->first_mm; mm; mm = mm->next_mm) {
+			if (mm == mem_info->cur_mm)
+				continue;
+
+			if (address < mm->physical_address)
+				continue;
 
-			/* Valid mapping, delete it */
+			if ((u64) address + length >
+					(u64) mm->physical_address + mm->length)
+				continue;
 
-			acpi_os_unmap_memory(mem_info->mapped_logical_address,
-					     mem_info->mapped_length);
+			mem_info->cur_mm = mm;
+			goto access;
+		}
+
+		/* Create a new mappings list entry */
+		mm = ACPI_ALLOCATE_ZEROED(sizeof(*mm));
+		if (!mm) {
+			ACPI_ERROR((AE_INFO,
+				    "Unable to save memory mapping at 0x%8.8X%8.8X, size %u",
+				    ACPI_FORMAT_UINT64(address), length));
+			return_ACPI_STATUS(AE_NO_MEMORY);
 		}
 
 		/*
@@ -120,52 +137,44 @@ acpi_ex_system_memory_space_handler(u32 function,
 		map_length = (acpi_size)
 		    ((mem_info->address + mem_info->length) - address);
 
-		/*
-		 * If mapping the entire remaining portion of the region will cross
-		 * a page boundary, just map up to the page boundary, do not cross.
-		 * On some systems, crossing a page boundary while mapping regions
-		 * can cause warnings if the pages have different attributes
-		 * due to resource management.
-		 *
-		 * This has the added benefit of constraining a single mapping to
-		 * one page, which is similar to the original code that used a 4k
-		 * maximum window.
-		 */
-		page_boundary_map_length = (acpi_size)
-		    (ACPI_ROUND_UP(address, ACPI_DEFAULT_PAGE_SIZE) - address);
-		if (page_boundary_map_length == 0) {
-			page_boundary_map_length = ACPI_DEFAULT_PAGE_SIZE;
-		}
-
-		if (map_length > page_boundary_map_length) {
-			map_length = page_boundary_map_length;
-		}
+		if (map_length > ACPI_DEFAULT_PAGE_SIZE)
+			map_length = ACPI_DEFAULT_PAGE_SIZE;
 
 		/* Create a new mapping starting at the address given */
 
-		mem_info->mapped_logical_address =
-		    acpi_os_map_memory(address, map_length);
-		if (!mem_info->mapped_logical_address) {
+		logical_addr_ptr = acpi_os_map_memory(address, map_length);
+		if (!logical_addr_ptr) {
 			ACPI_ERROR((AE_INFO,
 				    "Could not map memory at 0x%8.8X%8.8X, size %u",
 				    ACPI_FORMAT_UINT64(address),
 				    (u32)map_length));
-			mem_info->mapped_length = 0;
+			ACPI_FREE(mm);
 			return_ACPI_STATUS(AE_NO_MEMORY);
 		}
 
 		/* Save the physical address and mapping size */
 
-		mem_info->mapped_physical_address = address;
-		mem_info->mapped_length = map_length;
+		mm->logical_address = logical_addr_ptr;
+		mm->physical_address = address;
+		mm->length = map_length;
+
+		/*
+		 * Add the new entry to the mappigs list and save it as the
+		 * current mapping.
+		 */
+		mm->next_mm = mem_info->first_mm;
+		mem_info->first_mm = mm;
+
+		mem_info->cur_mm = mm;
 	}
 
+access:
 	/*
 	 * Generate a logical pointer corresponding to the address we want to
 	 * access
 	 */
-	logical_addr_ptr = mem_info->mapped_logical_address +
-	    ((u64) address - (u64) mem_info->mapped_physical_address);
+	logical_addr_ptr = mm->logical_address +
+		((u64) address - (u64) mm->physical_address);
 
 	ACPI_DEBUG_PRINT((ACPI_DB_INFO,
 			  "System-Memory (width %u) R/W %u Address=%8.8X%8.8X\n",
@@ -481,8 +490,15 @@ acpi_ex_data_table_space_handler(u32 function,
 				 u64 *value,
 				 void *handler_context, void *region_context)
 {
+	struct acpi_data_table_mapping *mapping;
+	char *pointer;
+
 	ACPI_FUNCTION_TRACE(ex_data_table_space_handler);
 
+	mapping = (struct acpi_data_table_mapping *) region_context;
+	pointer = ACPI_CAST_PTR(char, mapping->pointer) +
+	    (address - ACPI_PTR_TO_PHYSADDR(mapping->pointer));
+
 	/*
 	 * Perform the memory read or write. The bit_width was already
 	 * validated.
@@ -490,14 +506,14 @@ acpi_ex_data_table_space_handler(u32 function,
 	switch (function) {
 	case ACPI_READ:
 
-		memcpy(ACPI_CAST_PTR(char, value),
-		       ACPI_PHYSADDR_TO_PTR(address), ACPI_DIV_8(bit_width));
+		memcpy(ACPI_CAST_PTR(char, value), pointer,
+		       ACPI_DIV_8(bit_width));
 		break;
 
 	case ACPI_WRITE:
 
-		memcpy(ACPI_PHYSADDR_TO_PTR(address),
-		       ACPI_CAST_PTR(char, value), ACPI_DIV_8(bit_width));
+		memcpy(pointer, ACPI_CAST_PTR(char, value),
+		       ACPI_DIV_8(bit_width));
 		break;
 
 	default:
diff --git a/drivers/acpi/acpica/exresnte.c b/drivers/acpi/acpica/exresnte.c
index 3e4018678c09..dd83631090fc 100644
--- a/drivers/acpi/acpica/exresnte.c
+++ b/drivers/acpi/acpica/exresnte.c
@@ -3,7 +3,7 @@
  *
  * Module Name: exresnte - AML Interpreter object resolution
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/exresolv.c b/drivers/acpi/acpica/exresolv.c
index 912a078c60a4..4589de3f3012 100644
--- a/drivers/acpi/acpica/exresolv.c
+++ b/drivers/acpi/acpica/exresolv.c
@@ -3,7 +3,7 @@
  *
  * Module Name: exresolv - AML Interpreter object resolution
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/exresop.c b/drivers/acpi/acpica/exresop.c
index 4d1b22971d58..782ee353a709 100644
--- a/drivers/acpi/acpica/exresop.c
+++ b/drivers/acpi/acpica/exresop.c
@@ -3,7 +3,7 @@
  *
  * Module Name: exresop - AML Interpreter operand/object resolution
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -198,7 +198,7 @@ acpi_ex_resolve_operands(u16 opcode,
 
 					target_op = AML_DEBUG_OP;
 
-					/*lint -fallthrough */
+					ACPI_FALLTHROUGH;
 
 				case ACPI_REFCLASS_ARG:
 				case ACPI_REFCLASS_LOCAL:
@@ -264,7 +264,7 @@ acpi_ex_resolve_operands(u16 opcode,
 			 * Else not a string - fall through to the normal Reference
 			 * case below
 			 */
-			/*lint -fallthrough */
+			ACPI_FALLTHROUGH;
 
 		case ARGI_REFERENCE:	/* References: */
 		case ARGI_INTEGER_REF:
diff --git a/drivers/acpi/acpica/exserial.c b/drivers/acpi/acpica/exserial.c
index 760bc7cef55a..6d2581ec22ad 100644
--- a/drivers/acpi/acpica/exserial.c
+++ b/drivers/acpi/acpica/exserial.c
@@ -3,7 +3,7 @@
  *
  * Module Name: exserial - field_unit support for serial address spaces
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -195,6 +195,18 @@ acpi_ex_read_serial_bus(union acpi_operand_object *obj_desc,
 		function = ACPI_READ | (accessor_type << 16);
 		break;
 
+	case ACPI_ADR_SPACE_PLATFORM_RT:
+
+		buffer_length = ACPI_PRM_INPUT_BUFFER_SIZE;
+		function = ACPI_READ;
+		break;
+
+	case ACPI_ADR_SPACE_FIXED_HARDWARE:
+
+		buffer_length = ACPI_FFH_INPUT_BUFFER_SIZE;
+		function = ACPI_READ;
+		break;
+
 	default:
 		return_ACPI_STATUS(AE_AML_INVALID_SPACE_ID);
 	}
@@ -311,6 +323,18 @@ acpi_ex_write_serial_bus(union acpi_operand_object *source_desc,
 		function = ACPI_WRITE | (accessor_type << 16);
 		break;
 
+	case ACPI_ADR_SPACE_PLATFORM_RT:
+
+		buffer_length = ACPI_PRM_INPUT_BUFFER_SIZE;
+		function = ACPI_WRITE;
+		break;
+
+	case ACPI_ADR_SPACE_FIXED_HARDWARE:
+
+		buffer_length = ACPI_FFH_INPUT_BUFFER_SIZE;
+		function = ACPI_WRITE;
+		break;
+
 	default:
 		return_ACPI_STATUS(AE_AML_INVALID_SPACE_ID);
 	}
@@ -325,8 +349,7 @@ acpi_ex_write_serial_bus(union acpi_operand_object *source_desc,
 	/* Copy the input buffer data to the transfer buffer */
 
 	buffer = buffer_desc->buffer.pointer;
-	data_length = (buffer_length < source_desc->buffer.length ?
-		       buffer_length : source_desc->buffer.length);
+	data_length = ACPI_MIN(buffer_length, source_desc->buffer.length);
 	memcpy(buffer, source_desc->buffer.pointer, data_length);
 
 	/* Lock entire transaction if requested */
diff --git a/drivers/acpi/acpica/exstore.c b/drivers/acpi/acpica/exstore.c
index 3adc0a29d890..cbc42207496d 100644
--- a/drivers/acpi/acpica/exstore.c
+++ b/drivers/acpi/acpica/exstore.c
@@ -3,7 +3,7 @@
  *
  * Module Name: exstore - AML Interpreter object store support
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -96,7 +96,7 @@ acpi_ex_store(union acpi_operand_object *source_desc,
 			return_ACPI_STATUS(AE_OK);
 		}
 
-		/*lint -fallthrough */
+		ACPI_FALLTHROUGH;
 
 	default:
 
@@ -422,7 +422,7 @@ acpi_ex_store_object_to_node(union acpi_operand_object *source_desc,
 				break;
 			}
 
-			/* Fallthrough */
+			ACPI_FALLTHROUGH;
 
 		case ACPI_TYPE_DEVICE:
 		case ACPI_TYPE_EVENT:
diff --git a/drivers/acpi/acpica/exstoren.c b/drivers/acpi/acpica/exstoren.c
index 8c34f4e2ab8f..0470b2639831 100644
--- a/drivers/acpi/acpica/exstoren.c
+++ b/drivers/acpi/acpica/exstoren.c
@@ -4,7 +4,7 @@
  * Module Name: exstoren - AML Interpreter object store support,
  *                        Store to Node (namespace object)
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/exstorob.c b/drivers/acpi/acpica/exstorob.c
index dc66696080a5..5b168fbc03e8 100644
--- a/drivers/acpi/acpica/exstorob.c
+++ b/drivers/acpi/acpica/exstorob.c
@@ -3,7 +3,7 @@
  *
  * Module Name: exstorob - AML object store support, store to object
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/exsystem.c b/drivers/acpi/acpica/exsystem.c
index f329b01672bb..7f843c9d8a06 100644
--- a/drivers/acpi/acpica/exsystem.c
+++ b/drivers/acpi/acpica/exsystem.c
@@ -3,7 +3,7 @@
  *
  * Module Name: exsystem - Interface to OS services
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -107,7 +107,7 @@ acpi_status acpi_ex_system_wait_mutex(acpi_mutex mutex, u16 timeout)
  *
  * FUNCTION:    acpi_ex_system_do_stall
  *
- * PARAMETERS:  how_long        - The amount of time to stall,
+ * PARAMETERS:  how_long_us     - The amount of time to stall,
  *                                in microseconds
  *
  * RETURN:      Status
@@ -120,24 +120,30 @@ acpi_status acpi_ex_system_wait_mutex(acpi_mutex mutex, u16 timeout)
  *
  ******************************************************************************/
 
-acpi_status acpi_ex_system_do_stall(u32 how_long)
+acpi_status acpi_ex_system_do_stall(u32 how_long_us)
 {
 	acpi_status status = AE_OK;
 
 	ACPI_FUNCTION_ENTRY();
 
-	if (how_long > 255) {	/* 255 microseconds */
+	if (how_long_us > 255) {
 		/*
-		 * Longer than 255 usec, this is an error
+		 * Longer than 255 microseconds, this is an error
 		 *
 		 * (ACPI specifies 100 usec as max, but this gives some slack in
 		 * order to support existing BIOSs)
 		 */
-		ACPI_ERROR((AE_INFO,
-			    "Time parameter is too large (%u)", how_long));
+		ACPI_ERROR_ONCE((AE_INFO,
+				 "Time parameter is too large (%u)",
+				 how_long_us));
 		status = AE_AML_OPERAND_VALUE;
 	} else {
-		acpi_os_stall(how_long);
+		if (how_long_us > 100) {
+			ACPI_WARNING_ONCE((AE_INFO,
+					   "Time parameter %u us > 100 us violating ACPI spec, please fix the firmware.",
+					   how_long_us));
+		}
+		acpi_os_stall(how_long_us);
 	}
 
 	return (status);
@@ -147,7 +153,7 @@ acpi_status acpi_ex_system_do_stall(u32 how_long)
  *
  * FUNCTION:    acpi_ex_system_do_sleep
  *
- * PARAMETERS:  how_long        - The amount of time to sleep,
+ * PARAMETERS:  how_long_ms     - The amount of time to sleep,
  *                                in milliseconds
  *
  * RETURN:      None
@@ -156,7 +162,7 @@ acpi_status acpi_ex_system_do_stall(u32 how_long)
  *
  ******************************************************************************/
 
-acpi_status acpi_ex_system_do_sleep(u64 how_long)
+acpi_status acpi_ex_system_do_sleep(u64 how_long_ms)
 {
 	ACPI_FUNCTION_ENTRY();
 
@@ -168,11 +174,11 @@ acpi_status acpi_ex_system_do_sleep(u64 how_long)
 	 * For compatibility with other ACPI implementations and to prevent
 	 * accidental deep sleeps, limit the sleep time to something reasonable.
 	 */
-	if (how_long > ACPI_MAX_SLEEP) {
-		how_long = ACPI_MAX_SLEEP;
+	if (how_long_ms > ACPI_MAX_SLEEP) {
+		how_long_ms = ACPI_MAX_SLEEP;
 	}
 
-	acpi_os_sleep(how_long);
+	acpi_os_sleep(how_long_ms);
 
 	/* And now we must get the interpreter again */
 
diff --git a/drivers/acpi/acpica/extrace.c b/drivers/acpi/acpica/extrace.c
index 832a47885b99..36934d4f26fb 100644
--- a/drivers/acpi/acpica/extrace.c
+++ b/drivers/acpi/acpica/extrace.c
@@ -3,7 +3,7 @@
  *
  * Module Name: extrace - Support for interpreter execution tracing
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -136,9 +136,9 @@ acpi_ex_trace_point(acpi_trace_event_type type,
 
 	if (pathname) {
 		ACPI_DEBUG_PRINT((ACPI_DB_TRACE_POINT,
-				  "%s %s [0x%p:%s] execution.\n",
+				  "%s %s [%s] execution.\n",
 				  acpi_ex_get_trace_event_name(type),
-				  begin ? "Begin" : "End", aml, pathname));
+				  begin ? "Begin" : "End", pathname));
 	} else {
 		ACPI_DEBUG_PRINT((ACPI_DB_TRACE_POINT,
 				  "%s %s [0x%p] execution.\n",
@@ -149,6 +149,57 @@ acpi_ex_trace_point(acpi_trace_event_type type,
 
 /*******************************************************************************
  *
+ * FUNCTION:    acpi_ex_trace_args
+ *
+ * PARAMETERS:  params            - AML method arguments
+ *              count             - numer of method arguments
+ *
+ * RETURN:      None
+ *
+ * DESCRIPTION: Trace any arguments
+ *
+ ******************************************************************************/
+
+void
+acpi_ex_trace_args(union acpi_operand_object **params, u32 count)
+{
+	u32 i;
+
+	ACPI_FUNCTION_NAME(ex_trace_args);
+
+	for (i = 0; i < count; i++) {
+		union acpi_operand_object *obj_desc = params[i];
+
+		if (!i) {
+			ACPI_DEBUG_PRINT((ACPI_DB_TRACE_POINT, " "));
+		}
+
+		switch (obj_desc->common.type) {
+		case ACPI_TYPE_INTEGER:
+			ACPI_DEBUG_PRINT_RAW((ACPI_DB_TRACE_POINT, "%llx", obj_desc->integer.value));
+			break;
+		case ACPI_TYPE_STRING:
+			if (!obj_desc->string.length) {
+				ACPI_DEBUG_PRINT_RAW((ACPI_DB_TRACE_POINT, "NULL"));
+				continue;
+			}
+			if (ACPI_IS_DEBUG_ENABLED(ACPI_LV_TRACE_POINT, _COMPONENT))
+				acpi_ut_print_string(obj_desc->string.pointer, ACPI_UINT8_MAX);
+			break;
+		default:
+			ACPI_DEBUG_PRINT_RAW((ACPI_DB_TRACE_POINT, "Unknown"));
+			break;
+		}
+		if (i+1 == count) {
+			ACPI_DEBUG_PRINT_RAW((ACPI_DB_TRACE_POINT, "\n"));
+		} else {
+			ACPI_DEBUG_PRINT_RAW((ACPI_DB_TRACE_POINT, ", "));
+		}
+	}
+}
+
+/*******************************************************************************
+ *
  * FUNCTION:    acpi_ex_start_trace_method
  *
  * PARAMETERS:  method_node         - Node of the method
diff --git a/drivers/acpi/acpica/exutils.c b/drivers/acpi/acpica/exutils.c
index 8fefa6feac2f..cc10c0732218 100644
--- a/drivers/acpi/acpica/exutils.c
+++ b/drivers/acpi/acpica/exutils.c
@@ -3,7 +3,7 @@
  *
  * Module Name: exutils - interpreter/scanner utilities
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/hwacpi.c b/drivers/acpi/acpica/hwacpi.c
index 9b9aac27ff7e..a1e1fa787566 100644
--- a/drivers/acpi/acpica/hwacpi.c
+++ b/drivers/acpi/acpica/hwacpi.c
@@ -3,7 +3,7 @@
  *
  * Module Name: hwacpi - ACPI Hardware Initialization/Mode Interface
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/hwesleep.c b/drivers/acpi/acpica/hwesleep.c
index d9be5d0545d4..631fd8e2b774 100644
--- a/drivers/acpi/acpica/hwesleep.c
+++ b/drivers/acpi/acpica/hwesleep.c
@@ -4,7 +4,7 @@
  * Name: hwesleep.c - ACPI Hardware Sleep/Wake Support functions for the
  *                    extended FADT-V5 sleep registers.
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -104,7 +104,9 @@ acpi_status acpi_hw_extended_sleep(u8 sleep_state)
 
 	/* Flush caches, as per ACPI specification */
 
-	ACPI_FLUSH_CPU_CACHE();
+	if (sleep_state < ACPI_STATE_S4) {
+		ACPI_FLUSH_CPU_CACHE();
+	}
 
 	status = acpi_os_enter_sleep(sleep_state, sleep_control, 0);
 	if (status == AE_CTRL_TERMINATE) {
@@ -147,17 +149,13 @@ acpi_status acpi_hw_extended_sleep(u8 sleep_state)
 
 acpi_status acpi_hw_extended_wake_prep(u8 sleep_state)
 {
-	acpi_status status;
 	u8 sleep_type_value;
 
 	ACPI_FUNCTION_TRACE(hw_extended_wake_prep);
 
-	status = acpi_get_sleep_type_data(ACPI_STATE_S0,
-					  &acpi_gbl_sleep_type_a,
-					  &acpi_gbl_sleep_type_b);
-	if (ACPI_SUCCESS(status)) {
+	if (acpi_gbl_sleep_type_a_s0 != ACPI_SLEEP_TYPE_INVALID) {
 		sleep_type_value =
-		    ((acpi_gbl_sleep_type_a << ACPI_X_SLEEP_TYPE_POSITION) &
+		    ((acpi_gbl_sleep_type_a_s0 << ACPI_X_SLEEP_TYPE_POSITION) &
 		     ACPI_X_SLEEP_TYPE_MASK);
 
 		(void)acpi_write((u64)(sleep_type_value | ACPI_X_SLEEP_ENABLE),
diff --git a/drivers/acpi/acpica/hwgpe.c b/drivers/acpi/acpica/hwgpe.c
index 49c46d4dd070..386f4759c317 100644
--- a/drivers/acpi/acpica/hwgpe.c
+++ b/drivers/acpi/acpica/hwgpe.c
@@ -3,7 +3,7 @@
  *
  * Module Name: hwgpe - Low level GPE enable/disable/clear functions
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -26,6 +26,76 @@ acpi_hw_gpe_enable_write(u8 enable_mask,
 
 /******************************************************************************
  *
+ * FUNCTION:    acpi_hw_gpe_read
+ *
+ * PARAMETERS:  value               - Where the value is returned
+ *              reg                 - GPE register structure
+ *
+ * RETURN:      Status
+ *
+ * DESCRIPTION: Read from a GPE register in either memory or IO space.
+ *
+ * LIMITATIONS: <These limitations also apply to acpi_hw_gpe_write>
+ *      space_ID must be system_memory or system_IO.
+ *
+ ******************************************************************************/
+
+acpi_status acpi_hw_gpe_read(u64 *value, struct acpi_gpe_address *reg)
+{
+	acpi_status status;
+	u32 value32;
+
+	if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
+#ifdef ACPI_GPE_USE_LOGICAL_ADDRESSES
+		*value = (u64)ACPI_GET8((unsigned long)reg->address);
+		return_ACPI_STATUS(AE_OK);
+#else
+		return acpi_os_read_memory((acpi_physical_address)reg->address,
+					    value, ACPI_GPE_REGISTER_WIDTH);
+#endif
+	}
+
+	status = acpi_os_read_port((acpi_io_address)reg->address,
+				   &value32, ACPI_GPE_REGISTER_WIDTH);
+	if (ACPI_FAILURE(status))
+		return_ACPI_STATUS(status);
+
+	*value = (u64)value32;
+
+	return_ACPI_STATUS(AE_OK);
+}
+
+/******************************************************************************
+ *
+ * FUNCTION:    acpi_hw_gpe_write
+ *
+ * PARAMETERS:  value               - Value to be written
+ *              reg                 - GPE register structure
+ *
+ * RETURN:      Status
+ *
+ * DESCRIPTION: Write to a GPE register in either memory or IO space.
+ *
+ ******************************************************************************/
+
+acpi_status acpi_hw_gpe_write(u64 value, struct acpi_gpe_address *reg)
+{
+	if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
+#ifdef ACPI_GPE_USE_LOGICAL_ADDRESSES
+		ACPI_SET8((unsigned long)reg->address, value);
+		return_ACPI_STATUS(AE_OK);
+#else
+		return acpi_os_write_memory((acpi_physical_address)reg->address,
+					    value, ACPI_GPE_REGISTER_WIDTH);
+#endif
+	}
+
+	return acpi_os_write_port((acpi_io_address)reg->address, (u32)value,
+				  ACPI_GPE_REGISTER_WIDTH);
+}
+
+/******************************************************************************
+ *
  * FUNCTION:	acpi_hw_get_gpe_register_bit
  *
  * PARAMETERS:	gpe_event_info	    - Info block for the GPE
@@ -79,7 +149,8 @@ acpi_hw_low_set_gpe(struct acpi_gpe_event_info *gpe_event_info, u32 action)
 
 	/* Get current value of the enable register that contains this GPE */
 
-	status = acpi_hw_read(&enable_mask, &gpe_register_info->enable_address);
+	status = acpi_hw_gpe_read(&enable_mask,
+				  &gpe_register_info->enable_address);
 	if (ACPI_FAILURE(status)) {
 		return (status);
 	}
@@ -96,7 +167,7 @@ acpi_hw_low_set_gpe(struct acpi_gpe_event_info *gpe_event_info, u32 action)
 			return (AE_BAD_PARAMETER);
 		}
 
-		/*lint -fallthrough */
+		ACPI_FALLTHROUGH;
 
 	case ACPI_GPE_ENABLE:
 
@@ -118,9 +189,8 @@ acpi_hw_low_set_gpe(struct acpi_gpe_event_info *gpe_event_info, u32 action)
 
 		/* Write the updated enable mask */
 
-		status =
-		    acpi_hw_write(enable_mask,
-				  &gpe_register_info->enable_address);
+		status = acpi_hw_gpe_write(enable_mask,
+					   &gpe_register_info->enable_address);
 	}
 	return (status);
 }
@@ -158,8 +228,8 @@ acpi_status acpi_hw_clear_gpe(struct acpi_gpe_event_info *gpe_event_info)
 	 */
 	register_bit = acpi_hw_get_gpe_register_bit(gpe_event_info);
 
-	status =
-	    acpi_hw_write(register_bit, &gpe_register_info->status_address);
+	status = acpi_hw_gpe_write(register_bit,
+				   &gpe_register_info->status_address);
 	return (status);
 }
 
@@ -227,7 +297,7 @@ acpi_hw_get_gpe_status(struct acpi_gpe_event_info *gpe_event_info,
 
 	/* GPE currently enabled (enable bit == 1)? */
 
-	status = acpi_hw_read(&in_byte, &gpe_register_info->enable_address);
+	status = acpi_hw_gpe_read(&in_byte, &gpe_register_info->enable_address);
 	if (ACPI_FAILURE(status)) {
 		return (status);
 	}
@@ -238,7 +308,7 @@ acpi_hw_get_gpe_status(struct acpi_gpe_event_info *gpe_event_info,
 
 	/* GPE currently active (status bit == 1)? */
 
-	status = acpi_hw_read(&in_byte, &gpe_register_info->status_address);
+	status = acpi_hw_gpe_read(&in_byte, &gpe_register_info->status_address);
 	if (ACPI_FAILURE(status)) {
 		return (status);
 	}
@@ -274,7 +344,8 @@ acpi_hw_gpe_enable_write(u8 enable_mask,
 
 	gpe_register_info->enable_mask = enable_mask;
 
-	status = acpi_hw_write(enable_mask, &gpe_register_info->enable_address);
+	status = acpi_hw_gpe_write(enable_mask,
+				   &gpe_register_info->enable_address);
 	return (status);
 }
 
@@ -341,9 +412,8 @@ acpi_hw_clear_gpe_block(struct acpi_gpe_xrupt_info *gpe_xrupt_info,
 
 		/* Clear status on all GPEs in this register */
 
-		status =
-		    acpi_hw_write(0xFF,
-				  &gpe_block->register_info[i].status_address);
+		status = acpi_hw_gpe_write(0xFF,
+					   &gpe_block->register_info[i].status_address);
 		if (ACPI_FAILURE(status)) {
 			return (status);
 		}
@@ -481,14 +551,14 @@ acpi_hw_get_gpe_block_status(struct acpi_gpe_xrupt_info *gpe_xrupt_info,
 	for (i = 0; i < gpe_block->register_count; i++) {
 		gpe_register_info = &gpe_block->register_info[i];
 
-		status = acpi_hw_read(&in_enable,
-				      &gpe_register_info->enable_address);
+		status = acpi_hw_gpe_read(&in_enable,
+					  &gpe_register_info->enable_address);
 		if (ACPI_FAILURE(status)) {
 			continue;
 		}
 
-		status = acpi_hw_read(&in_status,
-				      &gpe_register_info->status_address);
+		status = acpi_hw_gpe_read(&in_status,
+					  &gpe_register_info->status_address);
 		if (ACPI_FAILURE(status)) {
 			continue;
 		}
diff --git a/drivers/acpi/acpica/hwregs.c b/drivers/acpi/acpica/hwregs.c
index 69603ba52a3a..f62d5d024205 100644
--- a/drivers/acpi/acpica/hwregs.c
+++ b/drivers/acpi/acpica/hwregs.c
@@ -446,7 +446,7 @@ struct acpi_bit_register_info *acpi_hw_get_bit_register_info(u32 register_id)
  * RETURN:      Status
  *
  * DESCRIPTION: Write the PM1 A/B control registers. These registers are
- *              different than than the PM1 A/B status and enable registers
+ *              different than the PM1 A/B status and enable registers
  *              in that different values can be written to the A/B registers.
  *              Most notably, the SLP_TYP bits can be different, as per the
  *              values returned from the _Sx predefined methods.
diff --git a/drivers/acpi/acpica/hwsleep.c b/drivers/acpi/acpica/hwsleep.c
index 317ae870336b..87d78bef6323 100644
--- a/drivers/acpi/acpica/hwsleep.c
+++ b/drivers/acpi/acpica/hwsleep.c
@@ -4,7 +4,7 @@
  * Name: hwsleep.c - ACPI Hardware Sleep/Wake Support functions for the
  *                   original/legacy sleep/PM registers.
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -110,7 +110,9 @@ acpi_status acpi_hw_legacy_sleep(u8 sleep_state)
 
 	/* Flush caches, as per ACPI specification */
 
-	ACPI_FLUSH_CPU_CACHE();
+	if (sleep_state < ACPI_STATE_S4) {
+		ACPI_FLUSH_CPU_CACHE();
+	}
 
 	status = acpi_os_enter_sleep(sleep_state, pm1a_control, pm1b_control);
 	if (status == AE_CTRL_TERMINATE) {
@@ -179,7 +181,7 @@ acpi_status acpi_hw_legacy_sleep(u8 sleep_state)
 
 acpi_status acpi_hw_legacy_wake_prep(u8 sleep_state)
 {
-	acpi_status status;
+	acpi_status status = AE_OK;
 	struct acpi_bit_register_info *sleep_type_reg_info;
 	struct acpi_bit_register_info *sleep_enable_reg_info;
 	u32 pm1a_control;
@@ -192,10 +194,7 @@ acpi_status acpi_hw_legacy_wake_prep(u8 sleep_state)
 	 * This is unclear from the ACPI Spec, but it is required
 	 * by some machines.
 	 */
-	status = acpi_get_sleep_type_data(ACPI_STATE_S0,
-					  &acpi_gbl_sleep_type_a,
-					  &acpi_gbl_sleep_type_b);
-	if (ACPI_SUCCESS(status)) {
+	if (acpi_gbl_sleep_type_a_s0 != ACPI_SLEEP_TYPE_INVALID) {
 		sleep_type_reg_info =
 		    acpi_hw_get_bit_register_info(ACPI_BITREG_SLEEP_TYPE);
 		sleep_enable_reg_info =
@@ -216,9 +215,9 @@ acpi_status acpi_hw_legacy_wake_prep(u8 sleep_state)
 
 			/* Insert the SLP_TYP bits */
 
-			pm1a_control |= (acpi_gbl_sleep_type_a <<
+			pm1a_control |= (acpi_gbl_sleep_type_a_s0 <<
 					 sleep_type_reg_info->bit_position);
-			pm1b_control |= (acpi_gbl_sleep_type_b <<
+			pm1b_control |= (acpi_gbl_sleep_type_b_s0 <<
 					 sleep_type_reg_info->bit_position);
 
 			/* Write the control registers and ignore any errors */
diff --git a/drivers/acpi/acpica/hwtimer.c b/drivers/acpi/acpica/hwtimer.c
index 07473ddfa9a9..a5e0bccae6a4 100644
--- a/drivers/acpi/acpica/hwtimer.c
+++ b/drivers/acpi/acpica/hwtimer.c
@@ -3,7 +3,7 @@
  *
  * Name: hwtimer.c - ACPI Power Management Timer Interface
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/hwvalid.c b/drivers/acpi/acpica/hwvalid.c
index 4d94861e6093..496fd9e49f0b 100644
--- a/drivers/acpi/acpica/hwvalid.c
+++ b/drivers/acpi/acpica/hwvalid.c
@@ -3,7 +3,7 @@
  *
  * Module Name: hwvalid - I/O request validation
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -23,8 +23,8 @@ acpi_hw_validate_io_request(acpi_io_address address, u32 bit_width);
  *
  * The table is used to implement the Microsoft port access rules that
  * first appeared in Windows XP. Some ports are always illegal, and some
- * ports are only illegal if the BIOS calls _OSI with a win_XP string or
- * later (meaning that the BIOS itelf is post-XP.)
+ * ports are only illegal if the BIOS calls _OSI with nothing newer than
+ * the specific _OSI strings.
  *
  * This provides ACPICA with the desired port protections and
  * Microsoft compatibility.
@@ -145,7 +145,8 @@ acpi_hw_validate_io_request(acpi_io_address address, u32 bit_width)
 
 			/* Port illegality may depend on the _OSI calls made by the BIOS */
 
-			if (acpi_gbl_osi_data >= port_info->osi_dependency) {
+			if (port_info->osi_dependency == ACPI_ALWAYS_ILLEGAL ||
+			    acpi_gbl_osi_data == port_info->osi_dependency) {
 				ACPI_DEBUG_PRINT((ACPI_DB_VALUES,
 						  "Denied AML access to port 0x%8.8X%8.8X/%X (%s 0x%.4X-0x%.4X)\n",
 						  ACPI_FORMAT_UINT64(address),
@@ -292,3 +293,33 @@ acpi_status acpi_hw_write_port(acpi_io_address address, u32 value, u32 width)
 
 	return (AE_OK);
 }
+
+/******************************************************************************
+ *
+ * FUNCTION:    acpi_hw_validate_io_block
+ *
+ * PARAMETERS:  Address             Address of I/O port/register blobk
+ *              bit_width           Number of bits (8,16,32) in each register
+ *              count               Number of registers in the block
+ *
+ * RETURN:      Status
+ *
+ * DESCRIPTION: Validates a block of I/O ports/registers.
+ *
+ ******************************************************************************/
+
+acpi_status acpi_hw_validate_io_block(u64 address, u32 bit_width, u32 count)
+{
+	acpi_status status;
+
+	while (count--) {
+		status = acpi_hw_validate_io_request((acpi_io_address)address,
+						     bit_width);
+		if (ACPI_FAILURE(status))
+			return_ACPI_STATUS(status);
+
+		address += ACPI_DIV_8(bit_width);
+	}
+
+	return_ACPI_STATUS(AE_OK);
+}
diff --git a/drivers/acpi/acpica/hwxface.c b/drivers/acpi/acpica/hwxface.c
index 134dbfadcd15..847cd1b2493d 100644
--- a/drivers/acpi/acpica/hwxface.c
+++ b/drivers/acpi/acpica/hwxface.c
@@ -3,7 +3,7 @@
  *
  * Module Name: hwxface - Public ACPICA hardware interfaces
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/hwxfsleep.c b/drivers/acpi/acpica/hwxfsleep.c
index a4b66f4b2714..9aabe30416da 100644
--- a/drivers/acpi/acpica/hwxfsleep.c
+++ b/drivers/acpi/acpica/hwxfsleep.c
@@ -3,7 +3,7 @@
  *
  * Name: hwxfsleep.c - ACPI Hardware Sleep/Wake External Interfaces
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -16,20 +16,11 @@
 ACPI_MODULE_NAME("hwxfsleep")
 
 /* Local prototypes */
-#if (!ACPI_REDUCED_HARDWARE)
 static acpi_status
 acpi_hw_set_firmware_waking_vector(struct acpi_table_facs *facs,
 				   acpi_physical_address physical_address,
 				   acpi_physical_address physical_address64);
-#endif
 
-/*
- * These functions are removed for the ACPI_REDUCED_HARDWARE case:
- *      acpi_set_firmware_waking_vector
- *      acpi_enter_sleep_state_s4bios
- */
-
-#if (!ACPI_REDUCED_HARDWARE)
 /*******************************************************************************
  *
  * FUNCTION:    acpi_hw_set_firmware_waking_vector
@@ -115,6 +106,12 @@ acpi_set_firmware_waking_vector(acpi_physical_address physical_address,
 
 ACPI_EXPORT_SYMBOL(acpi_set_firmware_waking_vector)
 
+/*
+ * These functions are removed for the ACPI_REDUCED_HARDWARE case:
+ *      acpi_enter_sleep_state_s4bios
+ */
+
+#if (!ACPI_REDUCED_HARDWARE)
 /*******************************************************************************
  *
  * FUNCTION:    acpi_enter_sleep_state_s4bios
@@ -162,8 +159,6 @@ acpi_status acpi_enter_sleep_state_s4bios(void)
 		return_ACPI_STATUS(status);
 	}
 
-	ACPI_FLUSH_CPU_CACHE();
-
 	status = acpi_hw_write_port(acpi_gbl_FADT.smi_command,
 				    (u32)acpi_gbl_FADT.s4_bios_request, 8);
 	if (ACPI_FAILURE(status)) {
@@ -217,6 +212,13 @@ acpi_status acpi_enter_sleep_state_prep(u8 sleep_state)
 		return_ACPI_STATUS(status);
 	}
 
+	status = acpi_get_sleep_type_data(ACPI_STATE_S0,
+					  &acpi_gbl_sleep_type_a_s0,
+					  &acpi_gbl_sleep_type_b_s0);
+	if (ACPI_FAILURE(status)) {
+		acpi_gbl_sleep_type_a_s0 = ACPI_SLEEP_TYPE_INVALID;
+	}
+
 	/* Execute the _PTS method (Prepare To Sleep) */
 
 	arg_list.count = 1;
diff --git a/drivers/acpi/acpica/nsaccess.c b/drivers/acpi/acpica/nsaccess.c
index 3f045b5953b2..a0c1a665dfc1 100644
--- a/drivers/acpi/acpica/nsaccess.c
+++ b/drivers/acpi/acpica/nsaccess.c
@@ -99,13 +99,12 @@ acpi_status acpi_ns_root_initialize(void)
 		 * just create and link the new node(s) here.
 		 */
 		new_node =
-		    ACPI_ALLOCATE_ZEROED(sizeof(struct acpi_namespace_node));
+		    acpi_ns_create_node(*ACPI_CAST_PTR(u32, init_val->name));
 		if (!new_node) {
 			status = AE_NO_MEMORY;
 			goto unlock_and_exit;
 		}
 
-		ACPI_COPY_NAMESEG(new_node->name.ascii, init_val->name);
 		new_node->descriptor_type = ACPI_DESC_TYPE_NAMED;
 		new_node->type = init_val->type;
 
diff --git a/drivers/acpi/acpica/nsalloc.c b/drivers/acpi/acpica/nsalloc.c
index fe9b3639a87d..83d26abcf448 100644
--- a/drivers/acpi/acpica/nsalloc.c
+++ b/drivers/acpi/acpica/nsalloc.c
@@ -294,7 +294,7 @@ void acpi_ns_delete_children(struct acpi_namespace_node *parent_node)
 		node_to_delete = next_node;
 		next_node = next_node->peer;
 		acpi_ns_delete_node(node_to_delete);
-	};
+	}
 
 	/* Clear the parent's child pointer */
 
diff --git a/drivers/acpi/acpica/nsarguments.c b/drivers/acpi/acpica/nsarguments.c
index d5e8405e9d8f..366d54a1d157 100644
--- a/drivers/acpi/acpica/nsarguments.c
+++ b/drivers/acpi/acpica/nsarguments.c
@@ -3,7 +3,7 @@
  *
  * Module Name: nsarguments - Validation of args for ACPI predefined methods
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -55,7 +55,9 @@ void acpi_ns_check_argument_types(struct acpi_evaluate_info *info)
 		arg_type = METHOD_GET_NEXT_TYPE(arg_type_list);
 		user_arg_type = info->parameters[i]->common.type;
 
-		if (user_arg_type != arg_type) {
+		/* No typechecking for ACPI_TYPE_ANY */
+
+		if ((user_arg_type != arg_type) && (arg_type != ACPI_TYPE_ANY)) {
 			ACPI_WARN_PREDEFINED((AE_INFO, info->full_pathname,
 					      ACPI_WARN_ALWAYS,
 					      "Argument #%u type mismatch - "
diff --git a/drivers/acpi/acpica/nsconvert.c b/drivers/acpi/acpica/nsconvert.c
index c86c82939ebb..f05a92b88642 100644
--- a/drivers/acpi/acpica/nsconvert.c
+++ b/drivers/acpi/acpica/nsconvert.c
@@ -4,7 +4,7 @@
  * Module Name: nsconvert - Object conversions for objects returned by
  *                          predefined methods
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/nsdump.c b/drivers/acpi/acpica/nsdump.c
index 994f0b556c60..6dc20486ad51 100644
--- a/drivers/acpi/acpica/nsdump.c
+++ b/drivers/acpi/acpica/nsdump.c
@@ -3,7 +3,7 @@
  *
  * Module Name: nsdump - table dumping routines for debug
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/nsdumpdv.c b/drivers/acpi/acpica/nsdumpdv.c
index b691fe20e384..d5b16aaec233 100644
--- a/drivers/acpi/acpica/nsdumpdv.c
+++ b/drivers/acpi/acpica/nsdumpdv.c
@@ -3,7 +3,7 @@
  *
  * Module Name: nsdump - table dumping routines for debug
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/nsinit.c b/drivers/acpi/acpica/nsinit.c
index e16f6a0c2c3f..03373e7f7978 100644
--- a/drivers/acpi/acpica/nsinit.c
+++ b/drivers/acpi/acpica/nsinit.c
@@ -3,7 +3,7 @@
  *
  * Module Name: nsinit - namespace initialization
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/nsload.c b/drivers/acpi/acpica/nsload.c
index 9ba17891edb6..6ec4c646fff7 100644
--- a/drivers/acpi/acpica/nsload.c
+++ b/drivers/acpi/acpica/nsload.c
@@ -3,7 +3,7 @@
  *
  * Module Name: nsload - namespace loading/expanding/contracting procedures
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/nsnames.c b/drivers/acpi/acpica/nsnames.c
index d91153f65700..22aeeeb56cff 100644
--- a/drivers/acpi/acpica/nsnames.c
+++ b/drivers/acpi/acpica/nsnames.c
@@ -194,7 +194,7 @@ acpi_ns_build_normalized_path(struct acpi_namespace_node *node,
 			      char *full_path, u32 path_size, u8 no_trailing)
 {
 	u32 length = 0, i;
-	char name[ACPI_NAMESEG_SIZE];
+	char name[ACPI_NAMESEG_SIZE] ACPI_NONSTRING;
 	u8 do_no_trailing;
 	char c, *left, *right;
 	struct acpi_namespace_node *next_node;
diff --git a/drivers/acpi/acpica/nsparse.c b/drivers/acpi/acpica/nsparse.c
index 7e74a765e785..959e6379bc4c 100644
--- a/drivers/acpi/acpica/nsparse.c
+++ b/drivers/acpi/acpica/nsparse.c
@@ -3,7 +3,7 @@
  *
  * Module Name: nsparse - namespace interface to AML parser
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/nspredef.c b/drivers/acpi/acpica/nspredef.c
index 0cea9c363ace..81995ee48c49 100644
--- a/drivers/acpi/acpica/nspredef.c
+++ b/drivers/acpi/acpica/nspredef.c
@@ -3,7 +3,7 @@
  *
  * Module Name: nspredef - Validation of ACPI predefined methods and objects
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -71,11 +71,13 @@ acpi_ns_check_return_value(struct acpi_namespace_node *node,
 	acpi_status status;
 	const union acpi_predefined_info *predefined;
 
+	ACPI_FUNCTION_TRACE(ns_check_return_value);
+
 	/* If not a predefined name, we cannot validate the return object */
 
 	predefined = info->predefined;
 	if (!predefined) {
-		return (AE_OK);
+		return_ACPI_STATUS(AE_OK);
 	}
 
 	/*
@@ -83,7 +85,7 @@ acpi_ns_check_return_value(struct acpi_namespace_node *node,
 	 * validate the return object
 	 */
 	if ((return_status != AE_OK) && (return_status != AE_CTRL_RETURN_VALUE)) {
-		return (AE_OK);
+		return_ACPI_STATUS(AE_OK);
 	}
 
 	/*
@@ -102,7 +104,7 @@ acpi_ns_check_return_value(struct acpi_namespace_node *node,
 	if (acpi_gbl_disable_auto_repair ||
 	    (!predefined->info.expected_btypes) ||
 	    (predefined->info.expected_btypes == ACPI_RTYPE_ALL)) {
-		return (AE_OK);
+		return_ACPI_STATUS(AE_OK);
 	}
 
 	/*
@@ -163,7 +165,7 @@ exit:
 		node->flags |= ANOBJ_EVALUATED;
 	}
 
-	return (status);
+	return_ACPI_STATUS(status);
 }
 
 /*******************************************************************************
diff --git a/drivers/acpi/acpica/nsprepkg.c b/drivers/acpi/acpica/nsprepkg.c
index 237b3ddeb075..ca137ce5674f 100644
--- a/drivers/acpi/acpica/nsprepkg.c
+++ b/drivers/acpi/acpica/nsprepkg.c
@@ -3,7 +3,7 @@
  *
  * Module Name: nsprepkg - Validation of package objects for predefined names
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -59,7 +59,7 @@ acpi_ns_check_package(struct acpi_evaluate_info *info,
 	u32 count;
 	u32 i;
 
-	ACPI_FUNCTION_NAME(ns_check_package);
+	ACPI_FUNCTION_TRACE(ns_check_package);
 
 	/* The package info for this name is in the next table entry */
 
@@ -88,14 +88,14 @@ acpi_ns_check_package(struct acpi_evaluate_info *info,
 	 */
 	if (!count) {
 		if (package->ret_info.type == ACPI_PTYPE1_VAR) {
-			return (AE_OK);
+			return_ACPI_STATUS(AE_OK);
 		}
 
 		ACPI_WARN_PREDEFINED((AE_INFO, info->full_pathname,
 				      info->node_flags,
 				      "Return Package has no elements (empty)"));
 
-		return (AE_AML_OPERAND_VALUE);
+		return_ACPI_STATUS(AE_AML_OPERAND_VALUE);
 	}
 
 	/*
@@ -152,7 +152,7 @@ acpi_ns_check_package(struct acpi_evaluate_info *info,
 							   package->ret_info.
 							   object_type1, i);
 			if (ACPI_FAILURE(status)) {
-				return (status);
+				return_ACPI_STATUS(status);
 			}
 
 			elements++;
@@ -186,7 +186,7 @@ acpi_ns_check_package(struct acpi_evaluate_info *info,
 							      object_type[i],
 							      i);
 				if (ACPI_FAILURE(status)) {
-					return (status);
+					return_ACPI_STATUS(status);
 				}
 			} else {
 				/* These are the optional package elements */
@@ -198,7 +198,7 @@ acpi_ns_check_package(struct acpi_evaluate_info *info,
 							      tail_object_type,
 							      i);
 				if (ACPI_FAILURE(status)) {
-					return (status);
+					return_ACPI_STATUS(status);
 				}
 			}
 
@@ -214,7 +214,7 @@ acpi_ns_check_package(struct acpi_evaluate_info *info,
 		    acpi_ns_check_object_type(info, elements,
 					      ACPI_RTYPE_INTEGER, 0);
 		if (ACPI_FAILURE(status)) {
-			return (status);
+			return_ACPI_STATUS(status);
 		}
 
 		elements++;
@@ -234,7 +234,7 @@ acpi_ns_check_package(struct acpi_evaluate_info *info,
 		    acpi_ns_check_object_type(info, elements,
 					      ACPI_RTYPE_INTEGER, 0);
 		if (ACPI_FAILURE(status)) {
-			return (status);
+			return_ACPI_STATUS(status);
 		}
 
 		/*
@@ -279,7 +279,7 @@ acpi_ns_check_package(struct acpi_evaluate_info *info,
 			    acpi_ns_wrap_with_package(info, return_object,
 						      return_object_ptr);
 			if (ACPI_FAILURE(status)) {
-				return (status);
+				return_ACPI_STATUS(status);
 			}
 
 			/* Update locals to point to the new package (of 1 element) */
@@ -316,7 +316,7 @@ acpi_ns_check_package(struct acpi_evaluate_info *info,
 							   package->ret_info.
 							   object_type1, 0);
 			if (ACPI_FAILURE(status)) {
-				return (status);
+				return_ACPI_STATUS(status);
 			}
 
 			/* Validate length of the UUID buffer */
@@ -326,14 +326,14 @@ acpi_ns_check_package(struct acpi_evaluate_info *info,
 						      info->full_pathname,
 						      info->node_flags,
 						      "Invalid length for UUID Buffer"));
-				return (AE_AML_OPERAND_VALUE);
+				return_ACPI_STATUS(AE_AML_OPERAND_VALUE);
 			}
 
 			status = acpi_ns_check_object_type(info, elements + 1,
 							   package->ret_info.
 							   object_type2, 0);
 			if (ACPI_FAILURE(status)) {
-				return (status);
+				return_ACPI_STATUS(status);
 			}
 
 			elements += 2;
@@ -350,10 +350,10 @@ acpi_ns_check_package(struct acpi_evaluate_info *info,
 				      "Invalid internal return type in table entry: %X",
 				      package->ret_info.type));
 
-		return (AE_AML_INTERNAL);
+		return_ACPI_STATUS(AE_AML_INTERNAL);
 	}
 
-	return (status);
+	return_ACPI_STATUS(status);
 
 package_too_small:
 
@@ -363,7 +363,7 @@ package_too_small:
 			      "Return Package is too small - found %u elements, expected %u",
 			      count, expected_count));
 
-	return (AE_AML_OPERAND_VALUE);
+	return_ACPI_STATUS(AE_AML_OPERAND_VALUE);
 }
 
 /*******************************************************************************
@@ -708,6 +708,8 @@ acpi_ns_check_package_elements(struct acpi_evaluate_info *info,
 	acpi_status status;
 	u32 i;
 
+	ACPI_FUNCTION_TRACE(ns_check_package_elements);
+
 	/*
 	 * Up to two groups of package elements are supported by the data
 	 * structure. All elements in each group must be of the same type.
@@ -717,7 +719,7 @@ acpi_ns_check_package_elements(struct acpi_evaluate_info *info,
 		status = acpi_ns_check_object_type(info, this_element,
 						   type1, i + start_index);
 		if (ACPI_FAILURE(status)) {
-			return (status);
+			return_ACPI_STATUS(status);
 		}
 
 		this_element++;
@@ -728,11 +730,11 @@ acpi_ns_check_package_elements(struct acpi_evaluate_info *info,
 						   type2,
 						   (i + count1 + start_index));
 		if (ACPI_FAILURE(status)) {
-			return (status);
+			return_ACPI_STATUS(status);
 		}
 
 		this_element++;
 	}
 
-	return (AE_OK);
+	return_ACPI_STATUS(AE_OK);
 }
diff --git a/drivers/acpi/acpica/nsrepair.c b/drivers/acpi/acpica/nsrepair.c
index 90db2d85e7f5..accfdcfb7e62 100644
--- a/drivers/acpi/acpica/nsrepair.c
+++ b/drivers/acpi/acpica/nsrepair.c
@@ -3,7 +3,7 @@
  *
  * Module Name: nsrepair - Repair for objects returned by predefined methods
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -181,8 +181,9 @@ acpi_ns_simple_repair(struct acpi_evaluate_info *info,
 	 * Try to fix if there was no return object. Warning if failed to fix.
 	 */
 	if (!return_object) {
-		if (expected_btypes && (!(expected_btypes & ACPI_RTYPE_NONE))) {
-			if (package_index != ACPI_NOT_PACKAGE_ELEMENT) {
+		if (expected_btypes) {
+			if (!(expected_btypes & ACPI_RTYPE_NONE) &&
+			    package_index != ACPI_NOT_PACKAGE_ELEMENT) {
 				ACPI_WARN_PREDEFINED((AE_INFO,
 						      info->full_pathname,
 						      ACPI_WARN_ALWAYS,
@@ -196,14 +197,15 @@ acpi_ns_simple_repair(struct acpi_evaluate_info *info,
 				if (ACPI_SUCCESS(status)) {
 					return (AE_OK);	/* Repair was successful */
 				}
-			} else {
+			}
+
+			if (expected_btypes != ACPI_RTYPE_NONE) {
 				ACPI_WARN_PREDEFINED((AE_INFO,
 						      info->full_pathname,
 						      ACPI_WARN_ALWAYS,
 						      "Missing expected return value"));
+				return (AE_AML_NO_RETURN_VALUE);
 			}
-
-			return (AE_AML_NO_RETURN_VALUE);
 		}
 	}
 
diff --git a/drivers/acpi/acpica/nsrepair2.c b/drivers/acpi/acpica/nsrepair2.c
index 125143c41bb8..8dbb870f40d2 100644
--- a/drivers/acpi/acpica/nsrepair2.c
+++ b/drivers/acpi/acpica/nsrepair2.c
@@ -4,7 +4,7 @@
  * Module Name: nsrepair2 - Repair for objects returned by specific
  *                          predefined methods
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -25,7 +25,7 @@ acpi_status (*acpi_repair_function) (struct acpi_evaluate_info * info,
 				     return_object_ptr);
 
 typedef struct acpi_repair_info {
-	char name[ACPI_NAMESEG_SIZE];
+	char name[ACPI_NAMESEG_SIZE] ACPI_NONSTRING;
 	acpi_repair_function repair_function;
 
 } acpi_repair_info;
@@ -155,15 +155,17 @@ acpi_ns_complex_repairs(struct acpi_evaluate_info *info,
 	const struct acpi_repair_info *predefined;
 	acpi_status status;
 
+	ACPI_FUNCTION_TRACE(ns_complex_repairs);
+
 	/* Check if this name is in the list of repairable names */
 
 	predefined = acpi_ns_match_complex_repair(node);
 	if (!predefined) {
-		return (validate_status);
+		return_ACPI_STATUS(validate_status);
 	}
 
 	status = predefined->repair_function(info, return_object_ptr);
-	return (status);
+	return_ACPI_STATUS(status);
 }
 
 /******************************************************************************
@@ -344,17 +346,19 @@ acpi_ns_repair_CID(struct acpi_evaluate_info *info,
 	u16 original_ref_count;
 	u32 i;
 
+	ACPI_FUNCTION_TRACE(ns_repair_CID);
+
 	/* Check for _CID as a simple string */
 
 	if (return_object->common.type == ACPI_TYPE_STRING) {
 		status = acpi_ns_repair_HID(info, return_object_ptr);
-		return (status);
+		return_ACPI_STATUS(status);
 	}
 
 	/* Exit if not a Package */
 
 	if (return_object->common.type != ACPI_TYPE_PACKAGE) {
-		return (AE_OK);
+		return_ACPI_STATUS(AE_OK);
 	}
 
 	/* Examine each element of the _CID package */
@@ -366,7 +370,7 @@ acpi_ns_repair_CID(struct acpi_evaluate_info *info,
 
 		status = acpi_ns_repair_HID(info, element_ptr);
 		if (ACPI_FAILURE(status)) {
-			return (status);
+			return_ACPI_STATUS(status);
 		}
 
 		if (original_element != *element_ptr) {
@@ -380,7 +384,7 @@ acpi_ns_repair_CID(struct acpi_evaluate_info *info,
 		element_ptr++;
 	}
 
-	return (AE_OK);
+	return_ACPI_STATUS(AE_OK);
 }
 
 /******************************************************************************
@@ -495,12 +499,12 @@ acpi_ns_repair_HID(struct acpi_evaluate_info *info,
 	char *source;
 	char *dest;
 
-	ACPI_FUNCTION_NAME(ns_repair_HID);
+	ACPI_FUNCTION_TRACE(ns_repair_HID);
 
 	/* We only care about string _HID objects (not integers) */
 
 	if (return_object->common.type != ACPI_TYPE_STRING) {
-		return (AE_OK);
+		return_ACPI_STATUS(AE_OK);
 	}
 
 	if (return_object->string.length == 0) {
@@ -511,14 +515,14 @@ acpi_ns_repair_HID(struct acpi_evaluate_info *info,
 		/* Return AE_OK anyway, let driver handle it */
 
 		info->return_flags |= ACPI_OBJECT_REPAIRED;
-		return (AE_OK);
+		return_ACPI_STATUS(AE_OK);
 	}
 
 	/* It is simplest to always create a new string object */
 
 	new_string = acpi_ut_create_string_object(return_object->string.length);
 	if (!new_string) {
-		return (AE_NO_MEMORY);
+		return_ACPI_STATUS(AE_NO_MEMORY);
 	}
 
 	/*
@@ -551,7 +555,7 @@ acpi_ns_repair_HID(struct acpi_evaluate_info *info,
 
 	acpi_ut_remove_reference(return_object);
 	*return_object_ptr = new_string;
-	return (AE_OK);
+	return_ACPI_STATUS(AE_OK);
 }
 
 /******************************************************************************
diff --git a/drivers/acpi/acpica/nsutils.c b/drivers/acpi/acpica/nsutils.c
index e66abdab8f31..49cc07e2ac5a 100644
--- a/drivers/acpi/acpica/nsutils.c
+++ b/drivers/acpi/acpica/nsutils.c
@@ -4,7 +4,7 @@
  * Module Name: nsutils - Utilities for accessing ACPI namespace, accessing
  *                        parents and siblings and Scope manipulation
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/nswalk.c b/drivers/acpi/acpica/nswalk.c
index b7f3e8603ad8..5670ff5a43cd 100644
--- a/drivers/acpi/acpica/nswalk.c
+++ b/drivers/acpi/acpica/nswalk.c
@@ -3,7 +3,7 @@
  *
  * Module Name: nswalk - Functions for walking the ACPI namespace
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -171,6 +171,12 @@ acpi_ns_walk_namespace(acpi_object_type type,
 		start_node = acpi_gbl_root_node;
 	}
 
+	/* Avoid walking the namespace if the StartNode is NULL */
+
+	if (!start_node) {
+		return_ACPI_STATUS(AE_NO_NAMESPACE);
+	}
+
 	/* Null child means "get first node" */
 
 	parent_node = start_node;
diff --git a/drivers/acpi/acpica/nsxfname.c b/drivers/acpi/acpica/nsxfname.c
index 0e6aba81605b..1db831545ec8 100644
--- a/drivers/acpi/acpica/nsxfname.c
+++ b/drivers/acpi/acpica/nsxfname.c
@@ -4,7 +4,7 @@
  * Module Name: nsxfname - Public interfaces to the ACPI subsystem
  *                         ACPI Namespace oriented interfaces
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -44,7 +44,7 @@ static char *acpi_ns_copy_device_id(struct acpi_pnp_device_id *dest,
 
 acpi_status
 acpi_get_handle(acpi_handle parent,
-		acpi_string pathname, acpi_handle *ret_handle)
+		const char *pathname, acpi_handle *ret_handle)
 {
 	acpi_status status;
 	struct acpi_namespace_node *node = NULL;
diff --git a/drivers/acpi/acpica/nsxfobj.c b/drivers/acpi/acpica/nsxfobj.c
index c022bef263e5..324269481160 100644
--- a/drivers/acpi/acpica/nsxfobj.c
+++ b/drivers/acpi/acpica/nsxfobj.c
@@ -24,7 +24,8 @@ ACPI_MODULE_NAME("nsxfobj")
  *
  * RETURN:      Status
  *
- * DESCRIPTION: This routine returns the type associatd with a particular handle
+ * DESCRIPTION: This routine returns the type associated with a particular
+ *              handle
  *
  ******************************************************************************/
 acpi_status acpi_get_type(acpi_handle handle, acpi_object_type *ret_type)
diff --git a/drivers/acpi/acpica/psargs.c b/drivers/acpi/acpica/psargs.c
index 3b40db4ad9f3..6f6ae38ec044 100644
--- a/drivers/acpi/acpica/psargs.c
+++ b/drivers/acpi/acpica/psargs.c
@@ -3,7 +3,7 @@
  *
  * Module Name: psargs - Parse AML opcode arguments
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -25,6 +25,8 @@ acpi_ps_get_next_package_length(struct acpi_parse_state *parser_state);
 static union acpi_parse_object *acpi_ps_get_next_field(struct acpi_parse_state
 						       *parser_state);
 
+static void acpi_ps_free_field_list(union acpi_parse_object *start);
+
 /*******************************************************************************
  *
  * FUNCTION:    acpi_ps_get_next_package_length
@@ -685,6 +687,39 @@ static union acpi_parse_object *acpi_ps_get_next_field(struct acpi_parse_state
 
 /*******************************************************************************
  *
+ * FUNCTION:    acpi_ps_free_field_list
+ *
+ * PARAMETERS:  start               - First Op in field list
+ *
+ * RETURN:      None.
+ *
+ * DESCRIPTION: Free all Op objects inside a field list.
+ *
+ ******************************************************************************/
+
+static void acpi_ps_free_field_list(union acpi_parse_object *start)
+{
+	union acpi_parse_object *cur = start;
+	union acpi_parse_object *next;
+	union acpi_parse_object *arg;
+
+	while (cur) {
+		next = cur->common.next;
+
+		/* AML_INT_CONNECTION_OP can have a single argument */
+
+		arg = acpi_ps_get_arg(cur, 0);
+		if (arg) {
+			acpi_ps_free_op(arg);
+		}
+
+		acpi_ps_free_op(cur);
+		cur = next;
+	}
+}
+
+/*******************************************************************************
+ *
  * FUNCTION:    acpi_ps_get_next_arg
  *
  * PARAMETERS:  walk_state          - Current state
@@ -751,6 +786,10 @@ acpi_ps_get_next_arg(struct acpi_walk_state *walk_state,
 			while (parser_state->aml < parser_state->pkg_end) {
 				field = acpi_ps_get_next_field(parser_state);
 				if (!field) {
+					if (arg) {
+						acpi_ps_free_field_list(arg);
+					}
+
 					return_ACPI_STATUS(AE_NO_MEMORY);
 				}
 
@@ -820,6 +859,10 @@ acpi_ps_get_next_arg(struct acpi_walk_state *walk_state,
 			    acpi_ps_get_next_namepath(walk_state, parser_state,
 						      arg,
 						      ACPI_NOT_METHOD_CALL);
+			if (ACPI_FAILURE(status)) {
+				acpi_ps_free_op(arg);
+				return_ACPI_STATUS(status);
+			}
 		} else {
 			/* Single complex argument, nothing returned */
 
@@ -854,6 +897,10 @@ acpi_ps_get_next_arg(struct acpi_walk_state *walk_state,
 			    acpi_ps_get_next_namepath(walk_state, parser_state,
 						      arg,
 						      ACPI_POSSIBLE_METHOD_CALL);
+			if (ACPI_FAILURE(status)) {
+				acpi_ps_free_op(arg);
+				return_ACPI_STATUS(status);
+			}
 
 			if (arg->common.aml_opcode == AML_INT_METHODCALL_OP) {
 
diff --git a/drivers/acpi/acpica/psloop.c b/drivers/acpi/acpica/psloop.c
index 3cf0687b9915..c989cadf271c 100644
--- a/drivers/acpi/acpica/psloop.c
+++ b/drivers/acpi/acpica/psloop.c
@@ -3,7 +3,7 @@
  *
  * Module Name: psloop - Main AML parse loop
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -264,8 +264,7 @@ acpi_status acpi_ps_parse_loop(struct acpi_walk_state *walk_state)
 								ACPI_TO_POINTER
 								(TRUE));
 				if (ACPI_FAILURE(status)
-				    && ((status & AE_CODE_MASK) !=
-					AE_CODE_CONTROL)) {
+				    && !ACPI_CNTL_EXCEPTION(status)) {
 					if (status == AE_AML_NO_RETURN_VALUE) {
 						ACPI_EXCEPTION((AE_INFO, status,
 								"Invoked method did not return a value"));
diff --git a/drivers/acpi/acpica/psobject.c b/drivers/acpi/acpica/psobject.c
index 2480c26c5171..496a1c1d5b0b 100644
--- a/drivers/acpi/acpica/psobject.c
+++ b/drivers/acpi/acpica/psobject.c
@@ -3,7 +3,7 @@
  *
  * Module Name: psobject - Support for parse objects
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -636,7 +636,8 @@ acpi_status
 acpi_ps_complete_final_op(struct acpi_walk_state *walk_state,
 			  union acpi_parse_object *op, acpi_status status)
 {
-	acpi_status status2;
+	acpi_status return_status = status;
+	u8 ascending = TRUE;
 
 	ACPI_FUNCTION_TRACE_PTR(ps_complete_final_op, walk_state);
 
@@ -650,7 +651,7 @@ acpi_ps_complete_final_op(struct acpi_walk_state *walk_state,
 			  op));
 	do {
 		if (op) {
-			if (walk_state->ascending_callback != NULL) {
+			if (ascending && walk_state->ascending_callback != NULL) {
 				walk_state->op = op;
 				walk_state->op_info =
 				    acpi_ps_get_opcode_info(op->common.
@@ -672,49 +673,26 @@ acpi_ps_complete_final_op(struct acpi_walk_state *walk_state,
 				}
 
 				if (status == AE_CTRL_TERMINATE) {
-					status = AE_OK;
-
-					/* Clean up */
-					do {
-						if (op) {
-							status2 =
-							    acpi_ps_complete_this_op
-							    (walk_state, op);
-							if (ACPI_FAILURE
-							    (status2)) {
-								return_ACPI_STATUS
-								    (status2);
-							}
-						}
-
-						acpi_ps_pop_scope(&
-								  (walk_state->
-								   parser_state),
-								  &op,
-								  &walk_state->
-								  arg_types,
-								  &walk_state->
-								  arg_count);
-
-					} while (op);
-
-					return_ACPI_STATUS(status);
+					ascending = FALSE;
+					return_status = AE_CTRL_TERMINATE;
 				}
 
 				else if (ACPI_FAILURE(status)) {
 
 					/* First error is most important */
 
-					(void)
-					    acpi_ps_complete_this_op(walk_state,
-								     op);
-					return_ACPI_STATUS(status);
+					ascending = FALSE;
+					return_status = status;
 				}
 			}
 
-			status2 = acpi_ps_complete_this_op(walk_state, op);
-			if (ACPI_FAILURE(status2)) {
-				return_ACPI_STATUS(status2);
+			status = acpi_ps_complete_this_op(walk_state, op);
+			if (ACPI_FAILURE(status)) {
+				ascending = FALSE;
+				if (ACPI_SUCCESS(return_status) ||
+				    return_status == AE_CTRL_TERMINATE) {
+					return_status = status;
+				}
 			}
 		}
 
@@ -724,5 +702,5 @@ acpi_ps_complete_final_op(struct acpi_walk_state *walk_state,
 
 	} while (op);
 
-	return_ACPI_STATUS(status);
+	return_ACPI_STATUS(return_status);
 }
diff --git a/drivers/acpi/acpica/psopcode.c b/drivers/acpi/acpica/psopcode.c
index 28af49263ebf..bf6103986f48 100644
--- a/drivers/acpi/acpica/psopcode.c
+++ b/drivers/acpi/acpica/psopcode.c
@@ -3,7 +3,7 @@
  *
  * Module Name: psopcode - Parser/Interpreter opcode information table
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -408,8 +408,8 @@ const struct acpi_opcode_info acpi_gbl_aml_op_info[AML_NUM_OPCODES] = {
 			 AML_HAS_ARGS | AML_NSOBJECT | AML_NSNODE |
 			 AML_DEFER | AML_FIELD | AML_CREATE),
 /* 4A */ ACPI_OP("Load", ARGP_LOAD_OP, ARGI_LOAD_OP, ACPI_TYPE_ANY,
-			 AML_CLASS_EXECUTE, AML_TYPE_EXEC_1A_1T_0R,
-			 AML_FLAGS_EXEC_1A_1T_0R),
+			 AML_CLASS_EXECUTE, AML_TYPE_EXEC_1A_1T_1R,
+			 AML_FLAGS_EXEC_1A_1T_1R),
 /* 4B */ ACPI_OP("Stall", ARGP_STALL_OP, ARGI_STALL_OP, ACPI_TYPE_ANY,
 			 AML_CLASS_EXECUTE, AML_TYPE_EXEC_1A_0T_0R,
 			 AML_FLAGS_EXEC_1A_0T_0R),
@@ -603,7 +603,7 @@ const struct acpi_opcode_info acpi_gbl_aml_op_info[AML_NUM_OPCODES] = {
 
 /* 7E */ ACPI_OP("Timer", ARGP_TIMER_OP, ARGI_TIMER_OP, ACPI_TYPE_ANY,
 			 AML_CLASS_EXECUTE, AML_TYPE_EXEC_0A_0T_1R,
-			 AML_FLAGS_EXEC_0A_0T_1R),
+			 AML_FLAGS_EXEC_0A_0T_1R | AML_NO_OPERAND_RESOLVE),
 
 /* ACPI 5.0 opcodes */
 
diff --git a/drivers/acpi/acpica/psopinfo.c b/drivers/acpi/acpica/psopinfo.c
index ab9327f6a63c..532ea307a675 100644
--- a/drivers/acpi/acpica/psopinfo.c
+++ b/drivers/acpi/acpica/psopinfo.c
@@ -3,7 +3,7 @@
  *
  * Module Name: psopinfo - AML opcode information functions and dispatch tables
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -34,7 +34,7 @@ static const u8 acpi_gbl_argument_count[] =
 
 const struct acpi_opcode_info *acpi_ps_get_opcode_info(u16 opcode)
 {
-#ifdef ACPI_DEBUG_OUTPUT
+#if defined ACPI_ASL_COMPILER && defined ACPI_DEBUG_OUTPUT
 	const char *opcode_name = "Unknown AML opcode";
 #endif
 
@@ -102,11 +102,11 @@ const struct acpi_opcode_info *acpi_ps_get_opcode_info(u16 opcode)
 	default:
 		break;
 	}
-#endif
 
 	/* Unknown AML opcode */
 
 	ACPI_DEBUG_PRINT((ACPI_DB_EXEC, "%s [%4.4X]\n", opcode_name, opcode));
+#endif
 
 	return (&acpi_gbl_aml_op_info[_UNK]);
 }
diff --git a/drivers/acpi/acpica/psparse.c b/drivers/acpi/acpica/psparse.c
index c780046bf294..55a416e56fd8 100644
--- a/drivers/acpi/acpica/psparse.c
+++ b/drivers/acpi/acpica/psparse.c
@@ -3,7 +3,7 @@
  *
  * Module Name: psparse - Parser top level AML parse routines
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -383,7 +383,7 @@ acpi_ps_next_parse_state(struct acpi_walk_state *walk_state,
 	default:
 
 		status = callback_status;
-		if ((callback_status & AE_CODE_MASK) == AE_CODE_CONTROL) {
+		if (ACPI_CNTL_EXCEPTION(callback_status)) {
 			status = AE_OK;
 		}
 		break;
@@ -508,8 +508,8 @@ acpi_status acpi_ps_parse_aml(struct acpi_walk_state *walk_state)
 			}
 
 			/*
-			 * If the transfer to the new method method call worked
-			 *, a new walk state was created -- get it
+			 * If the transfer to the new method method call worked,
+			 * a new walk state was created -- get it
 			 */
 			walk_state = acpi_ds_get_current_walk_state(thread);
 			continue;
diff --git a/drivers/acpi/acpica/psscope.c b/drivers/acpi/acpica/psscope.c
index fceb311995e9..c4e4483f0a0b 100644
--- a/drivers/acpi/acpica/psscope.c
+++ b/drivers/acpi/acpica/psscope.c
@@ -3,7 +3,7 @@
  *
  * Module Name: psscope - Parser scope stack management routines
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/pstree.c b/drivers/acpi/acpica/pstree.c
index c8aef0694864..5a285d3f2cdb 100644
--- a/drivers/acpi/acpica/pstree.c
+++ b/drivers/acpi/acpica/pstree.c
@@ -3,7 +3,7 @@
  *
  * Module Name: pstree - Parser op tree manipulation/traversal/search
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/psutils.c b/drivers/acpi/acpica/psutils.c
index 00efae2f95ba..ada1dc304d25 100644
--- a/drivers/acpi/acpica/psutils.c
+++ b/drivers/acpi/acpica/psutils.c
@@ -3,7 +3,7 @@
  *
  * Module Name: psutils - Parser miscellaneous utilities (Parser only)
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/pswalk.c b/drivers/acpi/acpica/pswalk.c
index 0fe3adf6b0e5..2f3ebcd8aebe 100644
--- a/drivers/acpi/acpica/pswalk.c
+++ b/drivers/acpi/acpica/pswalk.c
@@ -3,7 +3,7 @@
  *
  * Module Name: pswalk - Parser routines to walk parsed op tree(s)
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/psxface.c b/drivers/acpi/acpica/psxface.c
index 1bbfc8def388..d480de075a90 100644
--- a/drivers/acpi/acpica/psxface.c
+++ b/drivers/acpi/acpica/psxface.c
@@ -3,7 +3,7 @@
  *
  * Module Name: psxface - Parser external interfaces
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/rsaddr.c b/drivers/acpi/acpica/rsaddr.c
index 5737c3af1902..f92010e667cd 100644
--- a/drivers/acpi/acpica/rsaddr.c
+++ b/drivers/acpi/acpica/rsaddr.c
@@ -277,7 +277,8 @@ acpi_rs_get_address_common(struct acpi_resource *resource,
 	/* Validate the Resource Type */
 
 	if ((aml->address.resource_type > 2) &&
-	    (aml->address.resource_type < 0xC0)) {
+	    (aml->address.resource_type < 0xC0) &&
+	    (aml->address.resource_type != 0x0A)) {
 		return (FALSE);
 	}
 
diff --git a/drivers/acpi/acpica/rscalc.c b/drivers/acpi/acpica/rscalc.c
index fcf129d27baa..242daf45e20e 100644
--- a/drivers/acpi/acpica/rscalc.c
+++ b/drivers/acpi/acpica/rscalc.c
@@ -320,6 +320,16 @@ acpi_rs_get_aml_length(struct acpi_resource *resource,
 
 			break;
 
+		case ACPI_RESOURCE_TYPE_CLOCK_INPUT:
+
+			total_size = (acpi_rs_length)(total_size +
+						      resource->data.
+						      clock_input.
+						      resource_source.
+						      string_length);
+
+			break;
+
 		case ACPI_RESOURCE_TYPE_SERIAL_BUS:
 
 			total_size =
@@ -596,15 +606,17 @@ acpi_rs_get_list_length(u8 *aml_buffer,
 			}
 			break;
 
-		case ACPI_RESOURCE_NAME_SERIAL_BUS:
+		case ACPI_RESOURCE_NAME_SERIAL_BUS:{
 
-			minimum_aml_resource_length =
-			    acpi_gbl_resource_aml_serial_bus_sizes
-			    [aml_resource->common_serial_bus.type];
-			extra_struct_bytes +=
-			    aml_resource->common_serial_bus.resource_length -
-			    minimum_aml_resource_length;
-			break;
+				minimum_aml_resource_length =
+				    acpi_gbl_resource_aml_serial_bus_sizes
+				    [aml_resource->common_serial_bus.type];
+				extra_struct_bytes +=
+				    aml_resource->common_serial_bus.
+				    resource_length -
+				    minimum_aml_resource_length;
+				break;
+			}
 
 		case ACPI_RESOURCE_NAME_PIN_CONFIG:
 
@@ -650,6 +662,13 @@ acpi_rs_get_list_length(u8 *aml_buffer,
 
 			break;
 
+		case ACPI_RESOURCE_NAME_CLOCK_INPUT:
+			extra_struct_bytes =
+			    acpi_rs_stream_option_length(resource_length,
+							 minimum_aml_resource_length);
+
+			break;
+
 		default:
 
 			break;
@@ -677,10 +696,10 @@ acpi_rs_get_list_length(u8 *aml_buffer,
 		*size_needed += buffer_size;
 
 		ACPI_DEBUG_PRINT((ACPI_DB_RESOURCES,
-				  "Type %.2X, AmlLength %.2X InternalLength %.2X\n",
+				  "Type %.2X, AmlLength %.2X InternalLength %.2X%8X\n",
 				  acpi_ut_get_resource_type(aml_buffer),
 				  acpi_ut_get_descriptor_length(aml_buffer),
-				  buffer_size));
+				  ACPI_FORMAT_UINT64(*size_needed)));
 
 		/*
 		 * Point to the next resource within the AML stream using the length
diff --git a/drivers/acpi/acpica/rsdump.c b/drivers/acpi/acpica/rsdump.c
index 6601e71b45e3..5b7d7074ce4f 100644
--- a/drivers/acpi/acpica/rsdump.c
+++ b/drivers/acpi/acpica/rsdump.c
@@ -48,6 +48,7 @@ static void acpi_rs_dump_address_common(union acpi_resource_data *resource);
 static void
 acpi_rs_dump_descriptor(void *resource, struct acpi_rsdump_info *table);
 
+#ifdef ACPI_DEBUGGER
 /*******************************************************************************
  *
  * FUNCTION:    acpi_rs_dump_resource_list
@@ -87,6 +88,9 @@ void acpi_rs_dump_resource_list(struct acpi_resource *resource_list)
 			    ("Invalid descriptor type (%X) in resource list\n",
 			     resource_list->type);
 			return;
+		} else if (!resource_list->type) {
+			ACPI_ERROR((AE_INFO, "Invalid Zero Resource Type"));
+			return;
 		}
 
 		/* Sanity check the length. It must not be zero, or we loop forever */
@@ -157,6 +161,7 @@ void acpi_rs_dump_irq_list(u8 *route_table)
 					   prt_element, prt_element->length);
 	}
 }
+#endif
 
 /*******************************************************************************
  *
@@ -258,6 +263,11 @@ acpi_rs_dump_descriptor(void *resource, struct acpi_rsdump_info *table)
 					   table->pointer[*target & 0x07]);
 			break;
 
+		case ACPI_RSD_6BITFLAG:
+
+			acpi_rs_out_integer8(name, (ACPI_GET8(target) & 0x3F));
+			break;
+
 		case ACPI_RSD_SHORTLIST:
 			/*
 			 * Short byte list (single line output) for DMA and IRQ resources
diff --git a/drivers/acpi/acpica/rsdumpinfo.c b/drivers/acpi/acpica/rsdumpinfo.c
index cafa8134b4c6..998a79cc09c2 100644
--- a/drivers/acpi/acpica/rsdumpinfo.c
+++ b/drivers/acpi/acpica/rsdumpinfo.c
@@ -301,6 +301,23 @@ struct acpi_rsdump_info acpi_rs_dump_pin_function[10] = {
 	 "VendorData", NULL},
 };
 
+struct acpi_rsdump_info acpi_rs_dump_clock_input[7] = {
+	{ACPI_RSD_TITLE, ACPI_RSD_TABLE_SIZE(acpi_rs_dump_clock_input),
+	 "ClockInput", NULL},
+	{ACPI_RSD_UINT8, ACPI_RSD_OFFSET(clock_input.revision_id), "RevisionId",
+	 NULL},
+	{ACPI_RSD_UINT32, ACPI_RSD_OFFSET(clock_input.frequency_numerator),
+	 "FrequencyNumerator", NULL},
+	{ACPI_RSD_UINT32, ACPI_RSD_OFFSET(clock_input.frequency_divisor),
+	 "FrequencyDivisor", NULL},
+	{ACPI_RSD_1BITFLAG, ACPI_RSD_OFFSET(clock_input.scale), "Scale",
+	 acpi_gbl_clock_input_scale},
+	{ACPI_RSD_1BITFLAG, ACPI_RSD_OFFSET(clock_input.mode), "Mode",
+	 acpi_gbl_clock_input_mode},
+	{ACPI_RSD_SOURCE, ACPI_RSD_OFFSET(clock_input.resource_source),
+	 "ResourceSource", NULL},
+};
+
 struct acpi_rsdump_info acpi_rs_dump_pin_config[11] = {
 	{ACPI_RSD_TITLE, ACPI_RSD_TABLE_SIZE(acpi_rs_dump_pin_config),
 	 "PinConfig", NULL},
@@ -421,6 +438,32 @@ struct acpi_rsdump_info acpi_rs_dump_common_serial_bus[11] = {
 	ACPI_RS_DUMP_COMMON_SERIAL_BUS
 };
 
+struct acpi_rsdump_info acpi_rs_dump_csi2_serial_bus[11] = {
+	{ ACPI_RSD_TITLE, ACPI_RSD_TABLE_SIZE(acpi_rs_dump_csi2_serial_bus),
+	 "Camera Serial Bus", NULL },
+	{ ACPI_RSD_UINT8, ACPI_RSD_OFFSET(csi2_serial_bus.revision_id),
+	 "RevisionId", NULL },
+	{ ACPI_RSD_UINT8, ACPI_RSD_OFFSET(csi2_serial_bus.type), "Type",
+	 acpi_gbl_sbt_decode },
+	{ ACPI_RSD_1BITFLAG, ACPI_RSD_OFFSET(csi2_serial_bus.producer_consumer),
+	 "ProducerConsumer", acpi_gbl_consume_decode },
+	{ ACPI_RSD_1BITFLAG, ACPI_RSD_OFFSET(csi2_serial_bus.slave_mode),
+	 "SlaveMode", acpi_gbl_sm_decode },
+	{ ACPI_RSD_2BITFLAG, ACPI_RSD_OFFSET(csi2_serial_bus.phy_type),
+	 "PhyType", acpi_gbl_phy_decode },
+	{ ACPI_RSD_6BITFLAG,
+	 ACPI_RSD_OFFSET(csi2_serial_bus.local_port_instance),
+	 "LocalPortInstance", NULL },
+	{ ACPI_RSD_UINT8, ACPI_RSD_OFFSET(csi2_serial_bus.type_revision_id),
+	 "TypeRevisionId", NULL },
+	{ ACPI_RSD_UINT16, ACPI_RSD_OFFSET(csi2_serial_bus.vendor_length),
+	 "VendorLength", NULL },
+	{ ACPI_RSD_SHORTLISTX, ACPI_RSD_OFFSET(csi2_serial_bus.vendor_data),
+	 "VendorData", NULL },
+	{ ACPI_RSD_SOURCE, ACPI_RSD_OFFSET(csi2_serial_bus.resource_source),
+	 "ResourceSource", NULL },
+};
+
 struct acpi_rsdump_info acpi_rs_dump_i2c_serial_bus[14] = {
 	{ACPI_RSD_TITLE, ACPI_RSD_TABLE_SIZE(acpi_rs_dump_i2c_serial_bus),
 	 "I2C Serial Bus", NULL},
diff --git a/drivers/acpi/acpica/rsinfo.c b/drivers/acpi/acpica/rsinfo.c
index 6e2e596902eb..ad7465ddfe13 100644
--- a/drivers/acpi/acpica/rsinfo.c
+++ b/drivers/acpi/acpica/rsinfo.c
@@ -49,6 +49,7 @@ struct acpi_rsconvert_info *acpi_gbl_set_resource_dispatch[] = {
 	acpi_rs_convert_pin_group,	/* 0x16, ACPI_RESOURCE_TYPE_PIN_GROUP */
 	acpi_rs_convert_pin_group_function,	/* 0x17, ACPI_RESOURCE_TYPE_PIN_GROUP_FUNCTION */
 	acpi_rs_convert_pin_group_config,	/* 0x18, ACPI_RESOURCE_TYPE_PIN_GROUP_CONFIG */
+	acpi_rs_convert_clock_input,	/* 0x19, ACPI_RESOURCE_TYPE_CLOCK_INPUT */
 };
 
 /* Dispatch tables for AML-to-resource (Get Resource) conversion functions */
@@ -94,15 +95,17 @@ struct acpi_rsconvert_info *acpi_gbl_get_resource_dispatch[] = {
 	acpi_rs_convert_pin_group,	/* 0x10, ACPI_RESOURCE_NAME_PIN_GROUP */
 	acpi_rs_convert_pin_group_function,	/* 0x11, ACPI_RESOURCE_NAME_PIN_GROUP_FUNCTION */
 	acpi_rs_convert_pin_group_config,	/* 0x12, ACPI_RESOURCE_NAME_PIN_GROUP_CONFIG */
+	acpi_rs_convert_clock_input,	/* 0x13, ACPI_RESOURCE_NAME_CLOCK_INPUT */
 };
 
-/* Subtype table for serial_bus -- I2C, SPI, and UART */
+/* Subtype table for serial_bus -- I2C, SPI, UART, and CSI2 */
 
 struct acpi_rsconvert_info *acpi_gbl_convert_resource_serial_bus_dispatch[] = {
 	NULL,
 	acpi_rs_convert_i2c_serial_bus,
 	acpi_rs_convert_spi_serial_bus,
 	acpi_rs_convert_uart_serial_bus,
+	acpi_rs_convert_csi2_serial_bus
 };
 
 #if defined(ACPI_DEBUG_OUTPUT) || defined(ACPI_DISASSEMBLER) || defined(ACPI_DEBUGGER)
@@ -135,6 +138,7 @@ struct acpi_rsdump_info *acpi_gbl_dump_resource_dispatch[] = {
 	acpi_rs_dump_pin_group,	/* ACPI_RESOURCE_TYPE_PIN_GROUP */
 	acpi_rs_dump_pin_group_function,	/* ACPI_RESOURCE_TYPE_PIN_GROUP_FUNCTION */
 	acpi_rs_dump_pin_group_config,	/* ACPI_RESOURCE_TYPE_PIN_GROUP_CONFIG */
+	acpi_rs_dump_clock_input,	/* ACPI_RESOURCE_TYPE_CLOCK_INPUT */
 };
 
 struct acpi_rsdump_info *acpi_gbl_dump_serial_bus_dispatch[] = {
@@ -142,6 +146,7 @@ struct acpi_rsdump_info *acpi_gbl_dump_serial_bus_dispatch[] = {
 	acpi_rs_dump_i2c_serial_bus,	/* AML_RESOURCE_I2C_BUS_TYPE */
 	acpi_rs_dump_spi_serial_bus,	/* AML_RESOURCE_SPI_BUS_TYPE */
 	acpi_rs_dump_uart_serial_bus,	/* AML_RESOURCE_UART_BUS_TYPE */
+	acpi_rs_dump_csi2_serial_bus,	/* AML_RESOURCE_CSI2_BUS_TYPE */
 };
 #endif
 
@@ -176,6 +181,7 @@ const u8 acpi_gbl_aml_resource_sizes[] = {
 	sizeof(struct aml_resource_pin_group),	/* ACPI_RESOURCE_TYPE_PIN_GROUP */
 	sizeof(struct aml_resource_pin_group_function),	/* ACPI_RESOURCE_TYPE_PIN_GROUP_FUNCTION */
 	sizeof(struct aml_resource_pin_group_config),	/* ACPI_RESOURCE_TYPE_PIN_GROUP_CONFIG */
+	sizeof(struct aml_resource_clock_input),	/* ACPI_RESOURCE_TYPE_CLOCK_INPUT */
 };
 
 const u8 acpi_gbl_resource_struct_sizes[] = {
@@ -219,6 +225,7 @@ const u8 acpi_gbl_resource_struct_sizes[] = {
 	ACPI_RS_SIZE(struct acpi_resource_pin_group),
 	ACPI_RS_SIZE(struct acpi_resource_pin_group_function),
 	ACPI_RS_SIZE(struct acpi_resource_pin_group_config),
+	ACPI_RS_SIZE(struct acpi_resource_clock_input),
 };
 
 const u8 acpi_gbl_aml_resource_serial_bus_sizes[] = {
@@ -226,6 +233,7 @@ const u8 acpi_gbl_aml_resource_serial_bus_sizes[] = {
 	sizeof(struct aml_resource_i2c_serialbus),
 	sizeof(struct aml_resource_spi_serialbus),
 	sizeof(struct aml_resource_uart_serialbus),
+	sizeof(struct aml_resource_csi2_serialbus),
 };
 
 const u8 acpi_gbl_resource_struct_serial_bus_sizes[] = {
@@ -233,4 +241,5 @@ const u8 acpi_gbl_resource_struct_serial_bus_sizes[] = {
 	ACPI_RS_SIZE(struct acpi_resource_i2c_serialbus),
 	ACPI_RS_SIZE(struct acpi_resource_spi_serialbus),
 	ACPI_RS_SIZE(struct acpi_resource_uart_serialbus),
+	ACPI_RS_SIZE(struct acpi_resource_csi2_serialbus),
 };
diff --git a/drivers/acpi/acpica/rslist.c b/drivers/acpi/acpica/rslist.c
index 0307675d37be..e46efaa889cd 100644
--- a/drivers/acpi/acpica/rslist.c
+++ b/drivers/acpi/acpica/rslist.c
@@ -59,7 +59,7 @@ acpi_rs_convert_aml_to_resources(u8 * aml,
 		    AML_RESOURCE_MAX_SERIALBUSTYPE) {
 			conversion_table = NULL;
 		} else {
-			/* This is an I2C, SPI, or UART serial_bus descriptor */
+			/* This is an I2C, SPI, UART, or CSI2 serial_bus descriptor */
 
 			conversion_table =
 			    acpi_gbl_convert_resource_serial_bus_dispatch
@@ -89,6 +89,11 @@ acpi_rs_convert_aml_to_resources(u8 * aml,
 		return_ACPI_STATUS(status);
 	}
 
+	if (!resource->length) {
+		ACPI_EXCEPTION((AE_INFO, status,
+				"Zero-length resource returned from RsConvertAmlToResource"));
+	}
+
 	ACPI_DEBUG_PRINT((ACPI_DB_RESOURCES,
 			  "Type %.2X, AmlLength %.2X InternalLength %.2X\n",
 			  acpi_ut_get_resource_type(aml), length,
@@ -158,7 +163,7 @@ acpi_rs_convert_resources_to_aml(struct acpi_resource *resource,
 			    AML_RESOURCE_MAX_SERIALBUSTYPE) {
 				conversion_table = NULL;
 			} else {
-				/* This is an I2C, SPI, or UART serial_bus descriptor */
+				/* This is an I2C, SPI, UART or CSI2 serial_bus descriptor */
 
 				conversion_table =
 				    acpi_gbl_convert_resource_serial_bus_dispatch
diff --git a/drivers/acpi/acpica/rsmisc.c b/drivers/acpi/acpica/rsmisc.c
index 1763a3dbc9b1..6e8e98cf598d 100644
--- a/drivers/acpi/acpica/rsmisc.c
+++ b/drivers/acpi/acpica/rsmisc.c
@@ -70,6 +70,8 @@ acpi_rs_convert_aml_to_resource(struct acpi_resource *resource,
 	 */
 	count = INIT_TABLE_LENGTH(info);
 	while (count) {
+		target = NULL;
+
 		/*
 		 * Source is the external AML byte stream buffer,
 		 * destination is the internal resource descriptor
@@ -120,6 +122,14 @@ acpi_rs_convert_aml_to_resource(struct acpi_resource *resource,
 				  ((ACPI_GET8(source) >> info->value) & 0x07));
 			break;
 
+		case ACPI_RSC_6BITFLAG:
+			/*
+			 * Mask and shift the flag bits
+			 */
+			ACPI_SET8(destination,
+				  ((ACPI_GET8(source) >> info->value) & 0x3F));
+			break;
+
 		case ACPI_RSC_COUNT:
 
 			item_count = ACPI_GET8(source);
@@ -184,7 +194,8 @@ acpi_rs_convert_aml_to_resource(struct acpi_resource *resource,
 
 		case ACPI_RSC_COUNT_SERIAL_VEN:
 
-			item_count = ACPI_GET16(source) - info->value;
+			ACPI_MOVE_16_TO_16(&temp16, source);
+			item_count = temp16 - info->value;
 
 			resource->length = resource->length + item_count;
 			ACPI_SET16(destination, item_count);
@@ -192,9 +203,10 @@ acpi_rs_convert_aml_to_resource(struct acpi_resource *resource,
 
 		case ACPI_RSC_COUNT_SERIAL_RES:
 
+			ACPI_MOVE_16_TO_16(&temp16, source);
 			item_count = (aml_resource_length +
 				      sizeof(struct aml_resource_large_header))
-			    - ACPI_GET16(source) - info->value;
+			    - temp16 - info->value;
 
 			resource->length = resource->length + item_count;
 			ACPI_SET16(destination, item_count);
@@ -279,9 +291,9 @@ acpi_rs_convert_aml_to_resource(struct acpi_resource *resource,
 
 			/* Copy the resource_source string */
 
+			ACPI_MOVE_16_TO_16(&temp16, source);
 			source =
-			    ACPI_ADD_PTR(void, aml,
-					 (ACPI_GET16(source) + info->value));
+			    ACPI_ADD_PTR(void, aml, (temp16 + info->value));
 			acpi_rs_move_data(target, source, item_count,
 					  info->opcode);
 			break;
@@ -509,6 +521,15 @@ acpi_rs_convert_resource_to_aml(struct acpi_resource *resource,
 				      value));
 			break;
 
+		case ACPI_RSC_6BITFLAG:
+			/*
+			 * Mask and shift the flag bits
+			 */
+			ACPI_SET_BIT(*ACPI_CAST8(destination), (u8)
+				     ((ACPI_GET8(source) & 0x3F) << info->
+				      value));
+			break;
+
 		case ACPI_RSC_COUNT:
 
 			item_count = ACPI_GET8(source);
diff --git a/drivers/acpi/acpica/rsserial.c b/drivers/acpi/acpica/rsserial.c
index 1b937d88980f..279bfa27da94 100644
--- a/drivers/acpi/acpica/rsserial.c
+++ b/drivers/acpi/acpica/rsserial.c
@@ -111,6 +111,55 @@ struct acpi_rsconvert_info acpi_rs_convert_gpio[18] = {
 
 /*******************************************************************************
  *
+ * acpi_rs_convert_clock_input
+ *
+ ******************************************************************************/
+
+struct acpi_rsconvert_info acpi_rs_convert_clock_input[8] = {
+	{ACPI_RSC_INITGET, ACPI_RESOURCE_TYPE_CLOCK_INPUT,
+	 ACPI_RS_SIZE(struct acpi_resource_clock_input),
+	 ACPI_RSC_TABLE_SIZE(acpi_rs_convert_clock_input)},
+
+	{ACPI_RSC_INITSET, ACPI_RESOURCE_NAME_CLOCK_INPUT,
+	 sizeof(struct aml_resource_clock_input),
+	 0}
+	,
+
+	{ACPI_RSC_MOVE8, ACPI_RS_OFFSET(data.clock_input.revision_id),
+	 AML_OFFSET(clock_input.revision_id),
+	 1}
+	,
+
+	{ACPI_RSC_1BITFLAG, ACPI_RS_OFFSET(data.clock_input.mode),
+	 AML_OFFSET(clock_input.flags),
+	 0}
+	,
+
+	{ACPI_RSC_2BITFLAG, ACPI_RS_OFFSET(data.clock_input.scale),
+	 AML_OFFSET(clock_input.flags),
+	 1}
+	,
+
+	{ACPI_RSC_MOVE16, ACPI_RS_OFFSET(data.clock_input.frequency_divisor),
+	 AML_OFFSET(clock_input.frequency_divisor),
+	 2}
+	,
+
+	{ACPI_RSC_MOVE32, ACPI_RS_OFFSET(data.clock_input.frequency_numerator),
+	 AML_OFFSET(clock_input.frequency_numerator),
+	 4}
+	,
+
+	/* Resource Source */
+	{ACPI_RSC_SOURCE, ACPI_RS_OFFSET(data.clock_input.resource_source),
+	 0,
+	 sizeof(struct aml_resource_clock_input)}
+	,
+
+};
+
+/*******************************************************************************
+ *
  * acpi_rs_convert_pinfunction
  *
  ******************************************************************************/
@@ -187,6 +236,81 @@ struct acpi_rsconvert_info acpi_rs_convert_pin_function[13] = {
 
 /*******************************************************************************
  *
+ * acpi_rs_convert_csi2_serial_bus
+ *
+ ******************************************************************************/
+
+struct acpi_rsconvert_info acpi_rs_convert_csi2_serial_bus[14] = {
+	{ ACPI_RSC_INITGET, ACPI_RESOURCE_TYPE_SERIAL_BUS,
+	 ACPI_RS_SIZE(struct acpi_resource_csi2_serialbus),
+	 ACPI_RSC_TABLE_SIZE(acpi_rs_convert_csi2_serial_bus) },
+
+	{ ACPI_RSC_INITSET, ACPI_RESOURCE_NAME_SERIAL_BUS,
+	 sizeof(struct aml_resource_csi2_serialbus),
+	 0 },
+
+	{ ACPI_RSC_MOVE8, ACPI_RS_OFFSET(data.common_serial_bus.revision_id),
+	 AML_OFFSET(common_serial_bus.revision_id),
+	 1 },
+
+	{ ACPI_RSC_MOVE8, ACPI_RS_OFFSET(data.csi2_serial_bus.type),
+	 AML_OFFSET(csi2_serial_bus.type),
+	 1 },
+
+	{ ACPI_RSC_1BITFLAG,
+	 ACPI_RS_OFFSET(data.csi2_serial_bus.producer_consumer),
+	 AML_OFFSET(csi2_serial_bus.flags),
+	 1 },
+
+	{ ACPI_RSC_1BITFLAG, ACPI_RS_OFFSET(data.csi2_serial_bus.slave_mode),
+	 AML_OFFSET(csi2_serial_bus.flags),
+	 0 },
+
+	{ ACPI_RSC_2BITFLAG, ACPI_RS_OFFSET(data.csi2_serial_bus.phy_type),
+	 AML_OFFSET(csi2_serial_bus.type_specific_flags),
+	 0 },
+
+	{ ACPI_RSC_6BITFLAG,
+	 ACPI_RS_OFFSET(data.csi2_serial_bus.local_port_instance),
+	 AML_OFFSET(csi2_serial_bus.type_specific_flags),
+	 2 },
+
+	{ ACPI_RSC_MOVE8, ACPI_RS_OFFSET(data.csi2_serial_bus.type_revision_id),
+	 AML_OFFSET(csi2_serial_bus.type_revision_id),
+	 1 },
+
+	/* Vendor data */
+
+	{ ACPI_RSC_COUNT_SERIAL_VEN,
+	 ACPI_RS_OFFSET(data.csi2_serial_bus.vendor_length),
+	 AML_OFFSET(csi2_serial_bus.type_data_length),
+	 AML_RESOURCE_CSI2_MIN_DATA_LEN },
+
+	{ ACPI_RSC_MOVE_SERIAL_VEN,
+	 ACPI_RS_OFFSET(data.csi2_serial_bus.vendor_data),
+	 0,
+	 sizeof(struct aml_resource_csi2_serialbus) },
+
+	/* Resource Source */
+
+	{ ACPI_RSC_MOVE8,
+	 ACPI_RS_OFFSET(data.csi2_serial_bus.resource_source.index),
+	 AML_OFFSET(csi2_serial_bus.res_source_index),
+	 1 },
+
+	{ ACPI_RSC_COUNT_SERIAL_RES,
+	 ACPI_RS_OFFSET(data.csi2_serial_bus.resource_source.string_length),
+	 AML_OFFSET(csi2_serial_bus.type_data_length),
+	 sizeof(struct aml_resource_csi2_serialbus) },
+
+	{ ACPI_RSC_MOVE_SERIAL_RES,
+	 ACPI_RS_OFFSET(data.csi2_serial_bus.resource_source.string_ptr),
+	 AML_OFFSET(csi2_serial_bus.type_data_length),
+	 sizeof(struct aml_resource_csi2_serialbus) },
+};
+
+/*******************************************************************************
+ *
  * acpi_rs_convert_i2c_serial_bus
  *
  ******************************************************************************/
diff --git a/drivers/acpi/acpica/tbdata.c b/drivers/acpi/acpica/tbdata.c
index 523b1e9b98d4..5b98e09fff76 100644
--- a/drivers/acpi/acpica/tbdata.c
+++ b/drivers/acpi/acpica/tbdata.c
@@ -3,7 +3,7 @@
  *
  * Module Name: tbdata - Table manager data structure functions
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -89,14 +89,27 @@ acpi_tb_init_table_descriptor(struct acpi_table_desc *table_desc,
 {
 
 	/*
-	 * Initialize the table descriptor. Set the pointer to NULL, since the
-	 * table is not fully mapped at this time.
+	 * Initialize the table descriptor. Set the pointer to NULL for external
+	 * tables, since the table is not fully mapped at this time.
 	 */
 	memset(table_desc, 0, sizeof(struct acpi_table_desc));
 	table_desc->address = address;
 	table_desc->length = table->length;
 	table_desc->flags = flags;
 	ACPI_MOVE_32_TO_32(table_desc->signature.ascii, table->signature);
+
+	switch (table_desc->flags & ACPI_TABLE_ORIGIN_MASK) {
+	case ACPI_TABLE_ORIGIN_INTERNAL_VIRTUAL:
+	case ACPI_TABLE_ORIGIN_EXTERNAL_VIRTUAL:
+
+		table_desc->pointer = table;
+		break;
+
+	case ACPI_TABLE_ORIGIN_INTERNAL_PHYSICAL:
+	default:
+
+		break;
+	}
 }
 
 /*******************************************************************************
@@ -132,9 +145,7 @@ acpi_tb_acquire_table(struct acpi_table_desc *table_desc,
 	case ACPI_TABLE_ORIGIN_INTERNAL_VIRTUAL:
 	case ACPI_TABLE_ORIGIN_EXTERNAL_VIRTUAL:
 
-		table = ACPI_CAST_PTR(struct acpi_table_header,
-				      ACPI_PHYSADDR_TO_PTR(table_desc->
-							   address));
+		table = table_desc->pointer;
 		break;
 
 	default:
@@ -196,6 +207,8 @@ acpi_tb_release_table(struct acpi_table_header *table,
  * PARAMETERS:  table_desc          - Table descriptor to be acquired
  *              address             - Address of the table
  *              flags               - Allocation flags of the table
+ *              table               - Pointer to the table (required for virtual
+ *                                    origins, optional for physical)
  *
  * RETURN:      Status
  *
@@ -208,49 +221,52 @@ acpi_tb_release_table(struct acpi_table_header *table,
 
 acpi_status
 acpi_tb_acquire_temp_table(struct acpi_table_desc *table_desc,
-			   acpi_physical_address address, u8 flags)
+			   acpi_physical_address address,
+			   u8 flags, struct acpi_table_header *table)
 {
-	struct acpi_table_header *table_header;
+	u8 mapped_table = FALSE;
 
 	switch (flags & ACPI_TABLE_ORIGIN_MASK) {
 	case ACPI_TABLE_ORIGIN_INTERNAL_PHYSICAL:
 
 		/* Get the length of the full table from the header */
 
-		table_header =
-		    acpi_os_map_memory(address,
-				       sizeof(struct acpi_table_header));
-		if (!table_header) {
-			return (AE_NO_MEMORY);
+		if (!table) {
+			table =
+			    acpi_os_map_memory(address,
+					       sizeof(struct
+						      acpi_table_header));
+			if (!table) {
+				return (AE_NO_MEMORY);
+			}
+
+			mapped_table = TRUE;
 		}
 
-		acpi_tb_init_table_descriptor(table_desc, address, flags,
-					      table_header);
-		acpi_os_unmap_memory(table_header,
-				     sizeof(struct acpi_table_header));
-		return (AE_OK);
+		break;
 
 	case ACPI_TABLE_ORIGIN_INTERNAL_VIRTUAL:
 	case ACPI_TABLE_ORIGIN_EXTERNAL_VIRTUAL:
 
-		table_header = ACPI_CAST_PTR(struct acpi_table_header,
-					     ACPI_PHYSADDR_TO_PTR(address));
-		if (!table_header) {
-			return (AE_NO_MEMORY);
+		if (!table) {
+			return (AE_BAD_PARAMETER);
 		}
 
-		acpi_tb_init_table_descriptor(table_desc, address, flags,
-					      table_header);
-		return (AE_OK);
+		break;
 
 	default:
 
-		break;
+		/* Table is not valid yet */
+
+		return (AE_NO_MEMORY);
 	}
 
-	/* Table is not valid yet */
+	acpi_tb_init_table_descriptor(table_desc, address, flags, table);
+	if (mapped_table) {
+		acpi_os_unmap_memory(table, sizeof(struct acpi_table_header));
+	}
 
-	return (AE_NO_MEMORY);
+	return (AE_OK);
 }
 
 /*******************************************************************************
@@ -335,7 +351,19 @@ void acpi_tb_invalidate_table(struct acpi_table_desc *table_desc)
 
 	acpi_tb_release_table(table_desc->pointer, table_desc->length,
 			      table_desc->flags);
-	table_desc->pointer = NULL;
+
+	switch (table_desc->flags & ACPI_TABLE_ORIGIN_MASK) {
+	case ACPI_TABLE_ORIGIN_INTERNAL_PHYSICAL:
+
+		table_desc->pointer = NULL;
+		break;
+
+	case ACPI_TABLE_ORIGIN_INTERNAL_VIRTUAL:
+	case ACPI_TABLE_ORIGIN_EXTERNAL_VIRTUAL:
+	default:
+
+		break;
+	}
 
 	return_VOID;
 }
@@ -494,7 +522,7 @@ acpi_tb_verify_temp_table(struct acpi_table_desc *table_desc,
 		/* Verify the checksum */
 
 		status =
-		    acpi_tb_verify_checksum(table_desc->pointer,
+		    acpi_ut_verify_checksum(table_desc->pointer,
 					    table_desc->length);
 		if (ACPI_FAILURE(status)) {
 			ACPI_EXCEPTION((AE_INFO, AE_NO_MEMORY,
@@ -959,6 +987,9 @@ acpi_tb_load_table(u32 table_index, struct acpi_namespace_node *parent_node)
  *
  * PARAMETERS:  address                 - Physical address of the table
  *              flags                   - Allocation flags of the table
+ *              table                   - Pointer to the table (required for
+ *                                        virtual origins, optional for
+ *                                        physical)
  *              override                - Whether override should be performed
  *              table_index             - Where table index is returned
  *
@@ -970,7 +1001,9 @@ acpi_tb_load_table(u32 table_index, struct acpi_namespace_node *parent_node)
 
 acpi_status
 acpi_tb_install_and_load_table(acpi_physical_address address,
-			       u8 flags, u8 override, u32 *table_index)
+			       u8 flags,
+			       struct acpi_table_header *table,
+			       u8 override, u32 *table_index)
 {
 	acpi_status status;
 	u32 i;
@@ -979,7 +1012,7 @@ acpi_tb_install_and_load_table(acpi_physical_address address,
 
 	/* Install the table and load it into the namespace */
 
-	status = acpi_tb_install_standard_table(address, flags, TRUE,
+	status = acpi_tb_install_standard_table(address, flags, table, TRUE,
 						override, &i);
 	if (ACPI_FAILURE(status)) {
 		goto exit;
diff --git a/drivers/acpi/acpica/tbfadt.c b/drivers/acpi/acpica/tbfadt.c
index 907edc5edba7..c6658b2f3027 100644
--- a/drivers/acpi/acpica/tbfadt.c
+++ b/drivers/acpi/acpica/tbfadt.c
@@ -3,7 +3,7 @@
  *
  * Module Name: tbfadt   - FADT table utilities
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -298,7 +298,7 @@ void acpi_tb_parse_fadt(void)
 	 * Validate the FADT checksum before we copy the table. Ignore
 	 * checksum error as we want to try to get the DSDT and FACS.
 	 */
-	(void)acpi_tb_verify_checksum(table, length);
+	(void)acpi_ut_verify_checksum(table, length);
 
 	/* Create a local copy of the FADT in common ACPI 2.0+ format */
 
@@ -313,25 +313,21 @@ void acpi_tb_parse_fadt(void)
 	acpi_tb_install_standard_table((acpi_physical_address)acpi_gbl_FADT.
 				       Xdsdt,
 				       ACPI_TABLE_ORIGIN_INTERNAL_PHYSICAL,
-				       FALSE, TRUE, &acpi_gbl_dsdt_index);
-
-	/* If Hardware Reduced flag is set, there is no FACS */
-
-	if (!acpi_gbl_reduced_hardware) {
-		if (acpi_gbl_FADT.facs) {
-			acpi_tb_install_standard_table((acpi_physical_address)
-						       acpi_gbl_FADT.facs,
-						       ACPI_TABLE_ORIGIN_INTERNAL_PHYSICAL,
-						       FALSE, TRUE,
-						       &acpi_gbl_facs_index);
-		}
-		if (acpi_gbl_FADT.Xfacs) {
-			acpi_tb_install_standard_table((acpi_physical_address)
-						       acpi_gbl_FADT.Xfacs,
-						       ACPI_TABLE_ORIGIN_INTERNAL_PHYSICAL,
-						       FALSE, TRUE,
-						       &acpi_gbl_xfacs_index);
-		}
+				       NULL, FALSE, TRUE, &acpi_gbl_dsdt_index);
+
+	if (acpi_gbl_FADT.facs) {
+		acpi_tb_install_standard_table((acpi_physical_address)
+					       acpi_gbl_FADT.facs,
+					       ACPI_TABLE_ORIGIN_INTERNAL_PHYSICAL,
+					       NULL, FALSE, TRUE,
+					       &acpi_gbl_facs_index);
+	}
+	if (acpi_gbl_FADT.Xfacs) {
+		acpi_tb_install_standard_table((acpi_physical_address)
+					       acpi_gbl_FADT.Xfacs,
+					       ACPI_TABLE_ORIGIN_INTERNAL_PHYSICAL,
+					       NULL, FALSE, TRUE,
+					       &acpi_gbl_xfacs_index);
 	}
 }
 
diff --git a/drivers/acpi/acpica/tbfind.c b/drivers/acpi/acpica/tbfind.c
index 56d81e490a5c..d71a73216380 100644
--- a/drivers/acpi/acpica/tbfind.c
+++ b/drivers/acpi/acpica/tbfind.c
@@ -3,7 +3,7 @@
  *
  * Module Name: tbfind   - find table
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -57,8 +57,8 @@ acpi_tb_find_table(char *signature,
 
 	memset(&header, 0, sizeof(struct acpi_table_header));
 	ACPI_COPY_NAMESEG(header.signature, signature);
-	strncpy(header.oem_id, oem_id, ACPI_OEM_ID_SIZE);
-	strncpy(header.oem_table_id, oem_table_id, ACPI_OEM_TABLE_ID_SIZE);
+	memcpy(header.oem_id, oem_id, ACPI_OEM_ID_SIZE);
+	memcpy(header.oem_table_id, oem_table_id, ACPI_OEM_TABLE_ID_SIZE);
 
 	/* Search for the table */
 
diff --git a/drivers/acpi/acpica/tbinstal.c b/drivers/acpi/acpica/tbinstal.c
index 0bb15add2245..ee9b85bc238b 100644
--- a/drivers/acpi/acpica/tbinstal.c
+++ b/drivers/acpi/acpica/tbinstal.c
@@ -3,7 +3,7 @@
  *
  * Module Name: tbinstal - ACPI table installation and removal
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -79,6 +79,8 @@ acpi_tb_install_table_with_override(struct acpi_table_desc *new_table_desc,
  * PARAMETERS:  address             - Address of the table (might be a virtual
  *                                    address depending on the table_flags)
  *              flags               - Flags for the table
+ *              table               - Pointer to the table (required for virtual
+ *                                    origins, optional for physical)
  *              reload              - Whether reload should be performed
  *              override            - Whether override should be performed
  *              table_index         - Where the table index is returned
@@ -96,6 +98,7 @@ acpi_tb_install_table_with_override(struct acpi_table_desc *new_table_desc,
 acpi_status
 acpi_tb_install_standard_table(acpi_physical_address address,
 			       u8 flags,
+			       struct acpi_table_header *table,
 			       u8 reload, u8 override, u32 *table_index)
 {
 	u32 i;
@@ -106,7 +109,8 @@ acpi_tb_install_standard_table(acpi_physical_address address,
 
 	/* Acquire a temporary table descriptor for validation */
 
-	status = acpi_tb_acquire_temp_table(&new_table_desc, address, flags);
+	status =
+	    acpi_tb_acquire_temp_table(&new_table_desc, address, flags, table);
 	if (ACPI_FAILURE(status)) {
 		ACPI_ERROR((AE_INFO,
 			    "Could not acquire table length at %8.8X%8.8X",
@@ -209,7 +213,8 @@ void acpi_tb_override_table(struct acpi_table_desc *old_table_desc)
 	if (ACPI_SUCCESS(status) && table) {
 		acpi_tb_acquire_temp_table(&new_table_desc,
 					   ACPI_PTR_TO_PHYSADDR(table),
-					   ACPI_TABLE_ORIGIN_EXTERNAL_VIRTUAL);
+					   ACPI_TABLE_ORIGIN_EXTERNAL_VIRTUAL,
+					   table);
 		ACPI_ERROR_ONLY(override_type = "Logical");
 		goto finish_override;
 	}
@@ -220,7 +225,8 @@ void acpi_tb_override_table(struct acpi_table_desc *old_table_desc)
 						 &address, &length);
 	if (ACPI_SUCCESS(status) && address && length) {
 		acpi_tb_acquire_temp_table(&new_table_desc, address,
-					   ACPI_TABLE_ORIGIN_INTERNAL_PHYSICAL);
+					   ACPI_TABLE_ORIGIN_INTERNAL_PHYSICAL,
+					   NULL);
 		ACPI_ERROR_ONLY(override_type = "Physical");
 		goto finish_override;
 	}
@@ -289,7 +295,8 @@ void acpi_tb_uninstall_table(struct acpi_table_desc *table_desc)
 
 	if ((table_desc->flags & ACPI_TABLE_ORIGIN_MASK) ==
 	    ACPI_TABLE_ORIGIN_INTERNAL_VIRTUAL) {
-		ACPI_FREE(ACPI_PHYSADDR_TO_PTR(table_desc->address));
+		ACPI_FREE(table_desc->pointer);
+		table_desc->pointer = NULL;
 	}
 
 	table_desc->address = ACPI_PTR_TO_PHYSADDR(NULL);
diff --git a/drivers/acpi/acpica/tbprint.c b/drivers/acpi/acpica/tbprint.c
index 0b3494ad9a70..e5631027f7f1 100644
--- a/drivers/acpi/acpica/tbprint.c
+++ b/drivers/acpi/acpica/tbprint.c
@@ -3,13 +3,14 @@
  *
  * Module Name: tbprint - Table output utilities
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
 #include <acpi/acpi.h>
 #include "accommon.h"
 #include "actables.h"
+#include "acutils.h"
 
 #define _COMPONENT          ACPI_TABLES
 ACPI_MODULE_NAME("tbprint")
@@ -39,7 +40,7 @@ static void acpi_tb_fix_string(char *string, acpi_size length)
 {
 
 	while (length && *string) {
-		if (!isprint((int)*string)) {
+		if (!isprint((int)(u8)*string)) {
 			*string = '?';
 		}
 
@@ -94,6 +95,11 @@ acpi_tb_print_table_header(acpi_physical_address address,
 {
 	struct acpi_table_header local_header;
 
+#pragma GCC diagnostic push
+#if defined(__GNUC__) && __GNUC__ >= 11
+#pragma GCC diagnostic ignored "-Wstringop-overread"
+#endif
+
 	if (ACPI_COMPARE_NAMESEG(header->signature, ACPI_SIG_FACS)) {
 
 		/* FACS only has signature and length fields */
@@ -101,7 +107,8 @@ acpi_tb_print_table_header(acpi_physical_address address,
 		ACPI_INFO(("%-4.4s 0x%8.8X%8.8X %06X",
 			   header->signature, ACPI_FORMAT_UINT64(address),
 			   header->length));
-	} else if (ACPI_VALIDATE_RSDP_SIG(header->signature)) {
+	} else if (ACPI_VALIDATE_RSDP_SIG(ACPI_CAST_PTR(struct acpi_table_rsdp,
+							header)->signature)) {
 
 		/* RSDP has no common fields */
 
@@ -119,6 +126,14 @@ acpi_tb_print_table_header(acpi_physical_address address,
 			   ACPI_CAST_PTR(struct acpi_table_rsdp,
 					 header)->revision,
 			   local_header.oem_id));
+	} else if (acpi_gbl_CDAT && !acpi_ut_valid_nameseg(header->signature)) {
+
+		/* CDAT does not use the common ACPI table header */
+
+		ACPI_INFO(("%-4.4s 0x%8.8X%8.8X %06X",
+			   ACPI_SIG_CDAT, ACPI_FORMAT_UINT64(address),
+			   ACPI_CAST_PTR(struct acpi_table_cdat,
+					 header)->length));
 	} else {
 		/* Standard ACPI table with full common header */
 
@@ -133,78 +148,5 @@ acpi_tb_print_table_header(acpi_physical_address address,
 			   local_header.asl_compiler_id,
 			   local_header.asl_compiler_revision));
 	}
-}
-
-/*******************************************************************************
- *
- * FUNCTION:    acpi_tb_validate_checksum
- *
- * PARAMETERS:  table               - ACPI table to verify
- *              length              - Length of entire table
- *
- * RETURN:      Status
- *
- * DESCRIPTION: Verifies that the table checksums to zero. Optionally returns
- *              exception on bad checksum.
- *
- ******************************************************************************/
-
-acpi_status acpi_tb_verify_checksum(struct acpi_table_header *table, u32 length)
-{
-	u8 checksum;
-
-	/*
-	 * FACS/S3PT:
-	 * They are the odd tables, have no standard ACPI header and no checksum
-	 */
-
-	if (ACPI_COMPARE_NAMESEG(table->signature, ACPI_SIG_S3PT) ||
-	    ACPI_COMPARE_NAMESEG(table->signature, ACPI_SIG_FACS)) {
-		return (AE_OK);
-	}
-
-	/* Compute the checksum on the table */
-
-	checksum = acpi_tb_checksum(ACPI_CAST_PTR(u8, table), length);
-
-	/* Checksum ok? (should be zero) */
-
-	if (checksum) {
-		ACPI_BIOS_WARNING((AE_INFO,
-				   "Incorrect checksum in table [%4.4s] - 0x%2.2X, "
-				   "should be 0x%2.2X",
-				   table->signature, table->checksum,
-				   (u8)(table->checksum - checksum)));
-
-#if (ACPI_CHECKSUM_ABORT)
-		return (AE_BAD_CHECKSUM);
-#endif
-	}
-
-	return (AE_OK);
-}
-
-/*******************************************************************************
- *
- * FUNCTION:    acpi_tb_checksum
- *
- * PARAMETERS:  buffer          - Pointer to memory region to be checked
- *              length          - Length of this memory region
- *
- * RETURN:      Checksum (u8)
- *
- * DESCRIPTION: Calculates circular checksum of memory region.
- *
- ******************************************************************************/
-
-u8 acpi_tb_checksum(u8 *buffer, u32 length)
-{
-	u8 sum = 0;
-	u8 *end = buffer + length;
-
-	while (buffer < end) {
-		sum = (u8)(sum + *(buffer++));
-	}
-
-	return (sum);
+#pragma GCC diagnostic pop
 }
diff --git a/drivers/acpi/acpica/tbutils.c b/drivers/acpi/acpica/tbutils.c
index dfe1ac3ae34a..fa64851c7b62 100644
--- a/drivers/acpi/acpica/tbutils.c
+++ b/drivers/acpi/acpica/tbutils.c
@@ -3,7 +3,7 @@
  *
  * Module Name: tbutils - ACPI Table utilities
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -18,7 +18,6 @@ ACPI_MODULE_NAME("tbutils")
 static acpi_physical_address
 acpi_tb_get_root_table_entry(u8 *table_entry, u32 table_entry_size);
 
-#if (!ACPI_REDUCED_HARDWARE)
 /*******************************************************************************
  *
  * FUNCTION:    acpi_tb_initialize_facs
@@ -36,12 +35,7 @@ acpi_status acpi_tb_initialize_facs(void)
 {
 	struct acpi_table_facs *facs;
 
-	/* If Hardware Reduced flag is set, there is no FACS */
-
-	if (acpi_gbl_reduced_hardware) {
-		acpi_gbl_FACS = NULL;
-		return (AE_OK);
-	} else if (acpi_gbl_FADT.Xfacs &&
+	if (acpi_gbl_FADT.Xfacs &&
 		   (!acpi_gbl_FADT.facs
 		    || !acpi_gbl_use32_bit_facs_addresses)) {
 		(void)acpi_get_table_by_index(acpi_gbl_xfacs_index,
@@ -61,7 +55,6 @@ acpi_status acpi_tb_initialize_facs(void)
 
 	return (AE_OK);
 }
-#endif				/* !ACPI_REDUCED_HARDWARE */
 
 /*******************************************************************************
  *
@@ -165,6 +158,7 @@ struct acpi_table_header *acpi_tb_copy_dsdt(u32 table_index)
 static acpi_physical_address
 acpi_tb_get_root_table_entry(u8 *table_entry, u32 table_entry_size)
 {
+	u32 address32;
 	u64 address64;
 
 	/*
@@ -176,8 +170,8 @@ acpi_tb_get_root_table_entry(u8 *table_entry, u32 table_entry_size)
 		 * 32-bit platform, RSDT: Return 32-bit table entry
 		 * 64-bit platform, RSDT: Expand 32-bit to 64-bit and return
 		 */
-		return ((acpi_physical_address)
-			(*ACPI_CAST_PTR(u32, table_entry)));
+		ACPI_MOVE_32_TO_32(&address32, table_entry);
+		return address32;
 	} else {
 		/*
 		 * 32-bit platform, XSDT: Truncate 64-bit to 32-bit and return
@@ -299,7 +293,7 @@ acpi_tb_parse_root_table(acpi_physical_address rsdp_address)
 
 	/* Validate the root table checksum */
 
-	status = acpi_tb_verify_checksum(table, length);
+	status = acpi_ut_verify_checksum(table, length);
 	if (ACPI_FAILURE(status)) {
 		acpi_os_unmap_memory(table, length);
 		return_ACPI_STATUS(status);
@@ -328,7 +322,7 @@ acpi_tb_parse_root_table(acpi_physical_address rsdp_address)
 
 		status = acpi_tb_install_standard_table(address,
 							ACPI_TABLE_ORIGIN_INTERNAL_PHYSICAL,
-							FALSE, TRUE,
+							NULL, FALSE, TRUE,
 							&table_index);
 
 		if (ACPI_SUCCESS(status) &&
diff --git a/drivers/acpi/acpica/tbxface.c b/drivers/acpi/acpica/tbxface.c
index 7490429ddbf6..a8f07d2641b6 100644
--- a/drivers/acpi/acpica/tbxface.c
+++ b/drivers/acpi/acpica/tbxface.c
@@ -3,7 +3,7 @@
  *
  * Module Name: tbxface - ACPI table-oriented external interfaces
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/tbxfload.c b/drivers/acpi/acpica/tbxfload.c
index bcba993d4dac..2a17c60a9a39 100644
--- a/drivers/acpi/acpica/tbxfload.c
+++ b/drivers/acpi/acpica/tbxfload.c
@@ -3,7 +3,7 @@
  *
  * Module Name: tbxfload - Table load/unload external interfaces
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -227,9 +227,7 @@ unlock_and_exit:
  *
  * FUNCTION:    acpi_install_table
  *
- * PARAMETERS:  address             - Address of the ACPI table to be installed.
- *              physical            - Whether the address is a physical table
- *                                    address or not
+ * PARAMETERS:  table               - Pointer to the ACPI table to be installed.
  *
  * RETURN:      Status
  *
@@ -240,22 +238,17 @@ unlock_and_exit:
  ******************************************************************************/
 
 acpi_status ACPI_INIT_FUNCTION
-acpi_install_table(acpi_physical_address address, u8 physical)
+acpi_install_table(struct acpi_table_header *table)
 {
 	acpi_status status;
-	u8 flags;
 	u32 table_index;
 
 	ACPI_FUNCTION_TRACE(acpi_install_table);
 
-	if (physical) {
-		flags = ACPI_TABLE_ORIGIN_INTERNAL_PHYSICAL;
-	} else {
-		flags = ACPI_TABLE_ORIGIN_EXTERNAL_VIRTUAL;
-	}
-
-	status = acpi_tb_install_standard_table(address, flags,
-						FALSE, FALSE, &table_index);
+	status = acpi_tb_install_standard_table(ACPI_PTR_TO_PHYSADDR(table),
+						ACPI_TABLE_ORIGIN_EXTERNAL_VIRTUAL,
+						table, FALSE, FALSE,
+						&table_index);
 
 	return_ACPI_STATUS(status);
 }
@@ -264,6 +257,37 @@ ACPI_EXPORT_SYMBOL_INIT(acpi_install_table)
 
 /*******************************************************************************
  *
+ * FUNCTION:    acpi_install_physical_table
+ *
+ * PARAMETERS:  address             - Address of the ACPI table to be installed.
+ *
+ * RETURN:      Status
+ *
+ * DESCRIPTION: Dynamically install an ACPI table.
+ *              Note: This function should only be invoked after
+ *                    acpi_initialize_tables() and before acpi_load_tables().
+ *
+ ******************************************************************************/
+acpi_status ACPI_INIT_FUNCTION
+acpi_install_physical_table(acpi_physical_address address)
+{
+	acpi_status status;
+	u32 table_index;
+
+	ACPI_FUNCTION_TRACE(acpi_install_physical_table);
+
+	status = acpi_tb_install_standard_table(address,
+						ACPI_TABLE_ORIGIN_INTERNAL_PHYSICAL,
+						NULL, FALSE, FALSE,
+						&table_index);
+
+	return_ACPI_STATUS(status);
+}
+
+ACPI_EXPORT_SYMBOL_INIT(acpi_install_physical_table)
+
+/*******************************************************************************
+ *
  * FUNCTION:    acpi_load_table
  *
  * PARAMETERS:  table               - Pointer to a buffer containing the ACPI
@@ -298,7 +322,7 @@ acpi_status acpi_load_table(struct acpi_table_header *table, u32 *table_idx)
 	ACPI_INFO(("Host-directed Dynamic ACPI Table Load:"));
 	status = acpi_tb_install_and_load_table(ACPI_PTR_TO_PHYSADDR(table),
 						ACPI_TABLE_ORIGIN_EXTERNAL_VIRTUAL,
-						FALSE, &table_index);
+						table, FALSE, &table_index);
 	if (table_idx) {
 		*table_idx = table_index;
 	}
diff --git a/drivers/acpi/acpica/tbxfroot.c b/drivers/acpi/acpica/tbxfroot.c
index 0edc6ef5d46d..961577ba9486 100644
--- a/drivers/acpi/acpica/tbxfroot.c
+++ b/drivers/acpi/acpica/tbxfroot.c
@@ -3,7 +3,7 @@
  *
  * Module Name: tbxfroot - Find the root ACPI table (RSDT)
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -74,14 +74,14 @@ acpi_status acpi_tb_validate_rsdp(struct acpi_table_rsdp *rsdp)
 
 	/* Check the standard checksum */
 
-	if (acpi_tb_checksum((u8 *) rsdp, ACPI_RSDP_CHECKSUM_LENGTH) != 0) {
+	if (acpi_ut_checksum((u8 *)rsdp, ACPI_RSDP_CHECKSUM_LENGTH) != 0) {
 		return (AE_BAD_CHECKSUM);
 	}
 
 	/* Check extended checksum if table version >= 2 */
 
 	if ((rsdp->revision >= 2) &&
-	    (acpi_tb_checksum((u8 *) rsdp, ACPI_RSDP_XCHECKSUM_LENGTH) != 0)) {
+	    (acpi_ut_checksum((u8 *)rsdp, ACPI_RSDP_XCHECKSUM_LENGTH) != 0)) {
 		return (AE_BAD_CHECKSUM);
 	}
 
@@ -114,6 +114,7 @@ acpi_find_root_pointer(acpi_physical_address *table_address)
 	u8 *table_ptr;
 	u8 *mem_rover;
 	u32 physical_address;
+	u32 ebda_window_size;
 
 	ACPI_FUNCTION_TRACE(acpi_find_root_pointer);
 
@@ -139,26 +140,37 @@ acpi_find_root_pointer(acpi_physical_address *table_address)
 
 	/* EBDA present? */
 
-	if (physical_address > 0x400) {
+	/*
+	 * Check that the EBDA pointer from memory is sane and does not point
+	 * above valid low memory
+	 */
+	if (physical_address > 0x400 && physical_address < 0xA0000) {
+		/*
+		 * Calculate the scan window size
+		 * The EBDA is not guaranteed to be larger than a ki_b and in case
+		 * that it is smaller, the scanning function would leave the low
+		 * memory and continue to the VGA range.
+		 */
+		ebda_window_size = ACPI_MIN(ACPI_EBDA_WINDOW_SIZE,
+					    0xA0000 - physical_address);
+
 		/*
-		 * 1b) Search EBDA paragraphs (EBDA is required to be a
-		 *     minimum of 1K length)
+		 * 1b) Search EBDA paragraphs
 		 */
 		table_ptr = acpi_os_map_memory((acpi_physical_address)
 					       physical_address,
-					       ACPI_EBDA_WINDOW_SIZE);
+					       ebda_window_size);
 		if (!table_ptr) {
 			ACPI_ERROR((AE_INFO,
 				    "Could not map memory at 0x%8.8X for length %u",
-				    physical_address, ACPI_EBDA_WINDOW_SIZE));
+				    physical_address, ebda_window_size));
 
 			return_ACPI_STATUS(AE_NO_MEMORY);
 		}
 
 		mem_rover =
-		    acpi_tb_scan_memory_for_rsdp(table_ptr,
-						 ACPI_EBDA_WINDOW_SIZE);
-		acpi_os_unmap_memory(table_ptr, ACPI_EBDA_WINDOW_SIZE);
+		    acpi_tb_scan_memory_for_rsdp(table_ptr, ebda_window_size);
+		acpi_os_unmap_memory(table_ptr, ebda_window_size);
 
 		if (mem_rover) {
 
diff --git a/drivers/acpi/acpica/utaddress.c b/drivers/acpi/acpica/utaddress.c
index 99fa48722cf6..c673d6c95e0a 100644
--- a/drivers/acpi/acpica/utaddress.c
+++ b/drivers/acpi/acpica/utaddress.c
@@ -3,7 +3,7 @@
  *
  * Module Name: utaddress - op_region address range check
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/utalloc.c b/drivers/acpi/acpica/utalloc.c
index 303ab51b4fcf..2418a312733a 100644
--- a/drivers/acpi/acpica/utalloc.c
+++ b/drivers/acpi/acpica/utalloc.c
@@ -3,7 +3,7 @@
  *
  * Module Name: utalloc - local memory allocation routines
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/utascii.c b/drivers/acpi/acpica/utascii.c
index d78656d960e8..259c28d3fecd 100644
--- a/drivers/acpi/acpica/utascii.c
+++ b/drivers/acpi/acpica/utascii.c
@@ -3,7 +3,7 @@
  *
  * Module Name: utascii - Utility ascii functions
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/utbuffer.c b/drivers/acpi/acpica/utbuffer.c
index f2ec427f4e29..f6e6e98e9523 100644
--- a/drivers/acpi/acpica/utbuffer.c
+++ b/drivers/acpi/acpica/utbuffer.c
@@ -3,7 +3,7 @@
  *
  * Module Name: utbuffer - Buffer dump routines
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/utcache.c b/drivers/acpi/acpica/utcache.c
index 1b03a2747401..cabec193febb 100644
--- a/drivers/acpi/acpica/utcache.c
+++ b/drivers/acpi/acpica/utcache.c
@@ -3,7 +3,7 @@
  *
  * Module Name: utcache - local cache allocation routines
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -251,9 +251,9 @@ void *acpi_os_acquire_object(struct acpi_memory_list *cache)
 	} else {
 		/* The cache is empty, create a new object */
 
+#ifdef ACPI_DBG_TRACK_ALLOCATIONS
 		ACPI_MEM_TRACKING(cache->total_allocated++);
 
-#ifdef ACPI_DBG_TRACK_ALLOCATIONS
 		if ((cache->total_allocated - cache->total_freed) >
 		    cache->max_occupied) {
 			cache->max_occupied =
diff --git a/drivers/acpi/acpica/utcksum.c b/drivers/acpi/acpica/utcksum.c
new file mode 100644
index 000000000000..e6f6030b3a3f
--- /dev/null
+++ b/drivers/acpi/acpica/utcksum.c
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
+/******************************************************************************
+ *
+ * Module Name: utcksum - Support generating table checksums
+ *
+ * Copyright (C) 2000 - 2025, Intel Corp.
+ *
+ *****************************************************************************/
+
+#include <acpi/acpi.h>
+#include "accommon.h"
+#include "acutils.h"
+
+/* This module used for application-level code only */
+
+#define _COMPONENT          ACPI_CA_DISASSEMBLER
+ACPI_MODULE_NAME("utcksum")
+
+/*******************************************************************************
+ *
+ * FUNCTION:    acpi_ut_verify_checksum
+ *
+ * PARAMETERS:  table               - ACPI table to verify
+ *              length              - Length of entire table
+ *
+ * RETURN:      Status
+ *
+ * DESCRIPTION: Verifies that the table checksums to zero. Optionally returns
+ *              exception on bad checksum.
+ *              Note: We don't have to check for a CDAT here, since CDAT is
+ *              not in the RSDT/XSDT, and the CDAT table is never installed
+ *              via ACPICA.
+ *
+ ******************************************************************************/
+acpi_status acpi_ut_verify_checksum(struct acpi_table_header *table, u32 length)
+{
+	u8 checksum;
+
+	/*
+	 * FACS/S3PT:
+	 * They are the odd tables, have no standard ACPI header and no checksum
+	 */
+	if (ACPI_COMPARE_NAMESEG(table->signature, ACPI_SIG_S3PT) ||
+	    ACPI_COMPARE_NAMESEG(table->signature, ACPI_SIG_FACS)) {
+		return (AE_OK);
+	}
+
+	/* Compute the checksum on the table */
+
+	length = table->length;
+	checksum =
+	    acpi_ut_generate_checksum(ACPI_CAST_PTR(u8, table), length,
+				      table->checksum);
+
+	/* Computed checksum matches table? */
+
+	if (checksum != table->checksum) {
+		ACPI_BIOS_WARNING((AE_INFO,
+				   "Incorrect checksum in table [%4.4s] - 0x%2.2X, "
+				   "should be 0x%2.2X",
+				   table->signature, table->checksum,
+				   table->checksum - checksum));
+
+#if (ACPI_CHECKSUM_ABORT)
+		return (AE_BAD_CHECKSUM);
+#endif
+	}
+
+	return (AE_OK);
+}
+
+/*******************************************************************************
+ *
+ * FUNCTION:    acpi_ut_verify_cdat_checksum
+ *
+ * PARAMETERS:  table               - CDAT ACPI table to verify
+ *              length              - Length of entire table
+ *
+ * RETURN:      Status
+ *
+ * DESCRIPTION: Verifies that the CDAT table checksums to zero. Optionally
+ *              returns an exception on bad checksum.
+ *
+ ******************************************************************************/
+
+acpi_status
+acpi_ut_verify_cdat_checksum(struct acpi_table_cdat *cdat_table, u32 length)
+{
+	u8 checksum;
+
+	/* Compute the checksum on the table */
+
+	checksum = acpi_ut_generate_checksum(ACPI_CAST_PTR(u8, cdat_table),
+					     cdat_table->length,
+					     cdat_table->checksum);
+
+	/* Computed checksum matches table? */
+
+	if (checksum != cdat_table->checksum) {
+		ACPI_BIOS_WARNING((AE_INFO,
+				   "Incorrect checksum in table [%4.4s] - 0x%2.2X, "
+				   "should be 0x%2.2X",
+				   acpi_gbl_CDAT, cdat_table->checksum,
+				   checksum));
+
+#if (ACPI_CHECKSUM_ABORT)
+		return (AE_BAD_CHECKSUM);
+#endif
+	}
+
+	cdat_table->checksum = checksum;
+	return (AE_OK);
+}
+
+/*******************************************************************************
+ *
+ * FUNCTION:    acpi_ut_generate_checksum
+ *
+ * PARAMETERS:  table               - Pointer to table to be checksummed
+ *              length              - Length of the table
+ *              original_checksum   - Value of the checksum field
+ *
+ * RETURN:      8 bit checksum of buffer
+ *
+ * DESCRIPTION: Computes an 8 bit checksum of the table.
+ *
+ ******************************************************************************/
+
+u8 acpi_ut_generate_checksum(void *table, u32 length, u8 original_checksum)
+{
+	u8 checksum;
+
+	/* Sum the entire table as-is */
+
+	checksum = acpi_ut_checksum((u8 *)table, length);
+
+	/* Subtract off the existing checksum value in the table */
+
+	checksum = (u8)(checksum - original_checksum);
+
+	/* Compute and return the final checksum */
+
+	checksum = (u8)(0 - checksum);
+	return (checksum);
+}
+
+/*******************************************************************************
+ *
+ * FUNCTION:    acpi_ut_checksum
+ *
+ * PARAMETERS:  buffer          - Pointer to memory region to be checked
+ *              length          - Length of this memory region
+ *
+ * RETURN:      Checksum (u8)
+ *
+ * DESCRIPTION: Calculates circular checksum of memory region.
+ *
+ ******************************************************************************/
+
+u8 acpi_ut_checksum(u8 *buffer, u32 length)
+{
+	u8 sum = 0;
+	u8 *end = buffer + length;
+
+	while (buffer < end) {
+		sum = (u8)(sum + *(buffer++));
+	}
+
+	return (sum);
+}
diff --git a/drivers/acpi/acpica/utcopy.c b/drivers/acpi/acpica/utcopy.c
index 41bdd0278dd8..80458e70ac2b 100644
--- a/drivers/acpi/acpica/utcopy.c
+++ b/drivers/acpi/acpica/utcopy.c
@@ -3,7 +3,7 @@
  *
  * Module Name: utcopy - Internal to external object translation utilities
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -916,13 +916,6 @@ acpi_ut_copy_ipackage_to_ipackage(union acpi_operand_object *source_obj,
 	status = acpi_ut_walk_package_tree(source_obj, dest_obj,
 					   acpi_ut_copy_ielement_to_ielement,
 					   walk_state);
-	if (ACPI_FAILURE(status)) {
-
-		/* On failure, delete the destination package object */
-
-		acpi_ut_remove_reference(dest_obj);
-	}
-
 	return_ACPI_STATUS(status);
 }
 
diff --git a/drivers/acpi/acpica/utdebug.c b/drivers/acpi/acpica/utdebug.c
index 0c8cb0612414..9f197e293c7e 100644
--- a/drivers/acpi/acpica/utdebug.c
+++ b/drivers/acpi/acpica/utdebug.c
@@ -3,7 +3,7 @@
  *
  * Module Name: utdebug - Debug print/trace routines
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -37,7 +37,12 @@ void acpi_ut_init_stack_ptr_trace(void)
 {
 	acpi_size current_sp;
 
+#pragma GCC diagnostic push
+#if defined(__GNUC__) && __GNUC__ >= 12
+#pragma GCC diagnostic ignored "-Wdangling-pointer="
+#endif
 	acpi_gbl_entry_stack_pointer = &current_sp;
+#pragma GCC diagnostic pop
 }
 
 /*******************************************************************************
@@ -57,7 +62,12 @@ void acpi_ut_track_stack_ptr(void)
 	acpi_size current_sp;
 
 	if (&current_sp < acpi_gbl_lowest_stack_pointer) {
+#pragma GCC diagnostic push
+#if defined(__GNUC__) && __GNUC__ >= 12
+#pragma GCC diagnostic ignored "-Wdangling-pointer="
+#endif
 		acpi_gbl_lowest_stack_pointer = &current_sp;
+#pragma GCC diagnostic pop
 	}
 
 	if (acpi_gbl_nesting_level > acpi_gbl_deepest_nesting) {
diff --git a/drivers/acpi/acpica/utdecode.c b/drivers/acpi/acpica/utdecode.c
index 177ab88d95de..b82130d1a8bc 100644
--- a/drivers/acpi/acpica/utdecode.c
+++ b/drivers/acpi/acpica/utdecode.c
@@ -3,7 +3,7 @@
  *
  * Module Name: utdecode - Utility decoding routines (value-to-string)
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -78,7 +78,8 @@ const char *acpi_gbl_region_types[ACPI_NUM_PREDEFINED_REGIONS] = {
 	"IPMI",			/* 0x07 */
 	"GeneralPurposeIo",	/* 0x08 */
 	"GenericSerialBus",	/* 0x09 */
-	"PCC"			/* 0x0A */
+	"PCC",			/* 0x0A */
+	"PlatformRtMechanism"	/* 0x0B */
 };
 
 const char *acpi_ut_get_region_name(u8 space_id)
diff --git a/drivers/acpi/acpica/utdelete.c b/drivers/acpi/acpica/utdelete.c
index c365faf4e6cd..e8180099d01f 100644
--- a/drivers/acpi/acpica/utdelete.c
+++ b/drivers/acpi/acpica/utdelete.c
@@ -112,7 +112,7 @@ static void acpi_ut_delete_internal_obj(union acpi_operand_object *object)
 						       gpe_block);
 		}
 
-		/*lint -fallthrough */
+		ACPI_FALLTHROUGH;
 
 	case ACPI_TYPE_PROCESSOR:
 	case ACPI_TYPE_THERMAL:
@@ -140,7 +140,7 @@ static void acpi_ut_delete_internal_obj(union acpi_operand_object *object)
 			(void)
 			    acpi_os_delete_semaphore
 			    (acpi_gbl_global_lock_semaphore);
-			acpi_gbl_global_lock_semaphore = NULL;
+			acpi_gbl_global_lock_semaphore = ACPI_SEMAPHORE_NULL;
 
 			acpi_os_delete_mutex(object->mutex.os_mutex);
 			acpi_gbl_global_lock_mutex = NULL;
@@ -157,7 +157,7 @@ static void acpi_ut_delete_internal_obj(union acpi_operand_object *object)
 				  object, object->event.os_semaphore));
 
 		(void)acpi_os_delete_semaphore(object->event.os_semaphore);
-		object->event.os_semaphore = NULL;
+		object->event.os_semaphore = ACPI_SEMAPHORE_NULL;
 		break;
 
 	case ACPI_TYPE_METHOD:
@@ -285,6 +285,14 @@ static void acpi_ut_delete_internal_obj(union acpi_operand_object *object)
 		}
 		break;
 
+	case ACPI_TYPE_LOCAL_ADDRESS_HANDLER:
+
+		ACPI_DEBUG_PRINT((ACPI_DB_ALLOCATIONS,
+				  "***** Address handler %p\n", object));
+
+		acpi_os_delete_mutex(object->address_space.context_mutex);
+		break;
+
 	default:
 
 		break;
@@ -396,7 +404,7 @@ acpi_ut_update_ref_count(union acpi_operand_object *object, u32 action)
 				  object, object->common.type,
 				  acpi_ut_get_object_type_name(object),
 				  new_count));
-		message = "Incremement";
+		message = "Increment";
 		break;
 
 	case REF_DECREMENT:
@@ -414,6 +422,7 @@ acpi_ut_update_ref_count(union acpi_operand_object *object, u32 action)
 			ACPI_WARNING((AE_INFO,
 				      "Obj %p, Reference Count is already zero, cannot decrement\n",
 				      object));
+			return;
 		}
 
 		ACPI_DEBUG_PRINT_RAW((ACPI_DB_ALLOCATIONS,
@@ -568,11 +577,6 @@ acpi_ut_update_object_reference(union acpi_operand_object *object, u16 action)
 			next_object = object->buffer_field.buffer_obj;
 			break;
 
-		case ACPI_TYPE_LOCAL_REGION_FIELD:
-
-			next_object = object->field.region_obj;
-			break;
-
 		case ACPI_TYPE_LOCAL_BANK_FIELD:
 
 			next_object = object->bank_field.bank_obj;
@@ -613,6 +617,7 @@ acpi_ut_update_object_reference(union acpi_operand_object *object, u16 action)
 			}
 			break;
 
+		case ACPI_TYPE_LOCAL_REGION_FIELD:
 		case ACPI_TYPE_REGION:
 		default:
 
diff --git a/drivers/acpi/acpica/uteval.c b/drivers/acpi/acpica/uteval.c
index 8180d1a458f5..abc6583ed369 100644
--- a/drivers/acpi/acpica/uteval.c
+++ b/drivers/acpi/acpica/uteval.c
@@ -3,7 +3,7 @@
  *
  * Module Name: uteval - Object evaluation
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/utglobal.c b/drivers/acpi/acpica/utglobal.c
index e6dcbdc3fc6e..97c55a113bae 100644
--- a/drivers/acpi/acpica/utglobal.c
+++ b/drivers/acpi/acpica/utglobal.c
@@ -3,7 +3,7 @@
  *
  * Module Name: utglobal - Global variables for the ACPI subsystem
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/uthex.c b/drivers/acpi/acpica/uthex.c
index 0e02f12513dc..8cd050e9cad5 100644
--- a/drivers/acpi/acpica/uthex.c
+++ b/drivers/acpi/acpica/uthex.c
@@ -3,7 +3,7 @@
  *
  * Module Name: uthex -- Hex/ASCII support functions
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/utids.c b/drivers/acpi/acpica/utids.c
index 3bb06935a2ad..eb88335dea2c 100644
--- a/drivers/acpi/acpica/utids.c
+++ b/drivers/acpi/acpica/utids.c
@@ -3,7 +3,7 @@
  *
  * Module Name: utids - support for device Ids - HID, UID, CID, SUB, CLS
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -263,8 +263,7 @@ acpi_ut_execute_CID(struct acpi_namespace_node *device_node,
 	 * 3) Size of the actual CID strings
 	 */
 	cid_list_size = sizeof(struct acpi_pnp_device_id_list) +
-	    ((count - 1) * sizeof(struct acpi_pnp_device_id)) +
-	    string_area_size;
+	    (count * sizeof(struct acpi_pnp_device_id)) + string_area_size;
 
 	cid_list = ACPI_ALLOCATE_ZEROED(cid_list_size);
 	if (!cid_list) {
diff --git a/drivers/acpi/acpica/utinit.c b/drivers/acpi/acpica/utinit.c
index fdbc397c038d..4bef97e8223a 100644
--- a/drivers/acpi/acpica/utinit.c
+++ b/drivers/acpi/acpica/utinit.c
@@ -3,7 +3,7 @@
  *
  * Module Name: utinit - Common ACPI subsystem initialization
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -154,7 +154,7 @@ acpi_status acpi_ut_init_globals(void)
 
 	/* Global Lock support */
 
-	acpi_gbl_global_lock_semaphore = NULL;
+	acpi_gbl_global_lock_semaphore = ACPI_SEMAPHORE_NULL;
 	acpi_gbl_global_lock_mutex = NULL;
 	acpi_gbl_global_lock_acquired = FALSE;
 	acpi_gbl_global_lock_handle = 0;
diff --git a/drivers/acpi/acpica/utlock.c b/drivers/acpi/acpica/utlock.c
index 46be549539e7..123dbcbc60bc 100644
--- a/drivers/acpi/acpica/utlock.c
+++ b/drivers/acpi/acpica/utlock.c
@@ -3,7 +3,7 @@
  *
  * Module Name: utlock - Reader/Writer lock interfaces
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/utobject.c b/drivers/acpi/acpica/utobject.c
index bbec04c291d2..272e46208263 100644
--- a/drivers/acpi/acpica/utobject.c
+++ b/drivers/acpi/acpica/utobject.c
@@ -3,7 +3,7 @@
  *
  * Module Name: utobject - ACPI object create/delete/size/cache routines
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/utosi.c b/drivers/acpi/acpica/utosi.c
index 0a01c08dad8a..f6ac16729e42 100644
--- a/drivers/acpi/acpica/utosi.c
+++ b/drivers/acpi/acpica/utosi.c
@@ -3,7 +3,7 @@
  *
  * Module Name: utosi - Support for the _OSI predefined control method
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -73,6 +73,9 @@ static struct acpi_interface_info acpi_default_supported_interfaces[] = {
 	{"Windows 2018", NULL, 0, ACPI_OSI_WIN_10_RS4},	/* Windows 10 version 1803 - Added 11/2018 */
 	{"Windows 2018.2", NULL, 0, ACPI_OSI_WIN_10_RS5},	/* Windows 10 version 1809 - Added 11/2018 */
 	{"Windows 2019", NULL, 0, ACPI_OSI_WIN_10_19H1},	/* Windows 10 version 1903 - Added 08/2019 */
+	{"Windows 2020", NULL, 0, ACPI_OSI_WIN_10_20H1},	/* Windows 10 version 2004 - Added 08/2021 */
+	{"Windows 2021", NULL, 0, ACPI_OSI_WIN_11},	/* Windows 11 - Added 01/2022 */
+	{"Windows 2022", NULL, 0, ACPI_OSI_WIN_11_22H2},	/* Windows 11 version 22H2 - Added 04/2024 */
 
 	/* Feature Group Strings */
 
diff --git a/drivers/acpi/acpica/utpredef.c b/drivers/acpi/acpica/utpredef.c
index 05fe3470fb93..d9bd80e2d32a 100644
--- a/drivers/acpi/acpica/utpredef.c
+++ b/drivers/acpi/acpica/utpredef.c
@@ -3,7 +3,7 @@
  *
  * Module Name: utpredef - support functions for predefined names
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -151,7 +151,7 @@ static u32 acpi_ut_get_argument_types(char *buffer, u16 argument_types);
 
 static const char *ut_external_type_names[] =	/* Indexed by ACPI_TYPE_* */
 {
-	", UNSUPPORTED-TYPE",
+	", Type_ANY",
 	", Integer",
 	", String",
 	", Buffer",
@@ -311,8 +311,7 @@ static u32 acpi_ut_get_argument_types(char *buffer, u16 argument_types)
 	for (i = 0; i < arg_count; i++) {
 		this_argument_type = METHOD_GET_NEXT_TYPE(argument_types);
 
-		if (!this_argument_type
-		    || (this_argument_type > METHOD_MAX_ARG_TYPE)) {
+		if (this_argument_type > METHOD_MAX_ARG_TYPE) {
 			printf("**** Invalid argument type (%u) "
 			       "in predefined info structure\n",
 			       this_argument_type);
diff --git a/drivers/acpi/acpica/utprint.c b/drivers/acpi/acpica/utprint.c
index 681c11f4af4e..423d10569736 100644
--- a/drivers/acpi/acpica/utprint.c
+++ b/drivers/acpi/acpica/utprint.c
@@ -3,7 +3,7 @@
  *
  * Module Name: utprint - Formatted printing routines
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -333,11 +333,8 @@ int vsnprintf(char *string, acpi_size size, const char *format, va_list args)
 
 	pos = string;
 
-	if (size != ACPI_UINT32_MAX) {
-		end = string + size;
-	} else {
-		end = ACPI_CAST_PTR(char, ACPI_UINT32_MAX);
-	}
+	size = ACPI_MIN(size, ACPI_PTR_DIFF(ACPI_MAX_PTR, string));
+	end = string + size;
 
 	for (; *format; ++format) {
 		if (*format != '%') {
@@ -475,7 +472,7 @@ int vsnprintf(char *string, acpi_size size, const char *format, va_list args)
 		case 'X':
 
 			type |= ACPI_FORMAT_UPPER;
-			/* FALLTHROUGH */
+			ACPI_FALLTHROUGH;
 
 		case 'x':
 
diff --git a/drivers/acpi/acpica/utresdecode.c b/drivers/acpi/acpica/utresdecode.c
index 0a9c337346e8..d801d9069841 100644
--- a/drivers/acpi/acpica/utresdecode.c
+++ b/drivers/acpi/acpica/utresdecode.c
@@ -82,6 +82,13 @@ const char *acpi_gbl_mtp_decode[] = {
 	"AddressRangeNVS"
 };
 
+const char *acpi_gbl_phy_decode[] = {
+	"Type C",
+	"Type D",
+	"Unknown Type",
+	"Unknown Type"
+};
+
 const char *acpi_gbl_rng_decode[] = {
 	"InvalidRanges",
 	"NonISAOnlyRanges",
@@ -161,7 +168,8 @@ const char *acpi_gbl_sbt_decode[] = {
 	"/* UNKNOWN serial bus type */",
 	"I2C",
 	"SPI",
-	"UART"
+	"UART",
+	"CSI2"
 };
 
 /* I2C serial bus access mode */
@@ -276,4 +284,15 @@ const char *acpi_gbl_ptyp_decode[] = {
 	"Input Schmitt Trigger",
 };
 
+const char *acpi_gbl_clock_input_mode[] = {
+	"Fixed",
+	"Variable",
+};
+
+const char *acpi_gbl_clock_input_scale[] = {
+	"Hz",
+	"KHz",
+	"MHz",
+};
+
 #endif
diff --git a/drivers/acpi/acpica/utresrc.c b/drivers/acpi/acpica/utresrc.c
index cba5505171da..e1cc3d348750 100644
--- a/drivers/acpi/acpica/utresrc.c
+++ b/drivers/acpi/acpica/utresrc.c
@@ -57,6 +57,8 @@ const u8 acpi_gbl_resource_aml_sizes[] = {
 	ACPI_AML_SIZE_LARGE(struct aml_resource_pin_group),
 	ACPI_AML_SIZE_LARGE(struct aml_resource_pin_group_function),
 	ACPI_AML_SIZE_LARGE(struct aml_resource_pin_group_config),
+	ACPI_AML_SIZE_LARGE(struct aml_resource_clock_input),
+
 };
 
 const u8 acpi_gbl_resource_aml_serial_bus_sizes[] = {
@@ -64,6 +66,7 @@ const u8 acpi_gbl_resource_aml_serial_bus_sizes[] = {
 	ACPI_AML_SIZE_LARGE(struct aml_resource_i2c_serialbus),
 	ACPI_AML_SIZE_LARGE(struct aml_resource_spi_serialbus),
 	ACPI_AML_SIZE_LARGE(struct aml_resource_uart_serialbus),
+	ACPI_AML_SIZE_LARGE(struct aml_resource_csi2_serialbus),
 };
 
 /*
@@ -113,6 +116,7 @@ static const u8 acpi_gbl_resource_types[] = {
 	ACPI_VARIABLE_LENGTH,	/* 10 pin_group */
 	ACPI_VARIABLE_LENGTH,	/* 11 pin_group_function */
 	ACPI_VARIABLE_LENGTH,	/* 12 pin_group_config */
+	ACPI_VARIABLE_LENGTH,	/* 13 clock_input */
 };
 
 /*******************************************************************************
diff --git a/drivers/acpi/acpica/utstring.c b/drivers/acpi/acpica/utstring.c
index c39b5483045d..aae71b8c55d2 100644
--- a/drivers/acpi/acpica/utstring.c
+++ b/drivers/acpi/acpica/utstring.c
@@ -145,7 +145,7 @@ void acpi_ut_repair_name(char *name)
 		return;
 	}
 
-	ACPI_COPY_NAMESEG(&original_name, name);
+	ACPI_COPY_NAMESEG(&original_name, &name[0]);
 
 	/* Check each character in the name */
 
@@ -156,10 +156,10 @@ void acpi_ut_repair_name(char *name)
 
 		/*
 		 * Replace a bad character with something printable, yet technically
-		 * still invalid. This prevents any collisions with existing "good"
+		 * "odd". This prevents any collisions with existing "good"
 		 * names in the namespace.
 		 */
-		name[i] = '*';
+		name[i] = '_';
 		found_bad_char = TRUE;
 	}
 
@@ -169,8 +169,8 @@ void acpi_ut_repair_name(char *name)
 
 		if (!acpi_gbl_enable_interpreter_slack) {
 			ACPI_WARNING((AE_INFO,
-				      "Invalid character(s) in name (0x%.8X), repaired: [%4.4s]",
-				      original_name, name));
+				      "Invalid character(s) in name (0x%.8X) %p, repaired: [%4.4s]",
+				      original_name, name, &name[0]));
 		} else {
 			ACPI_DEBUG_PRINT((ACPI_DB_INFO,
 					  "Invalid character(s) in name (0x%.8X), repaired: [%4.4s]",
diff --git a/drivers/acpi/acpica/utstrsuppt.c b/drivers/acpi/acpica/utstrsuppt.c
index 05ff20049b87..199982a6fb16 100644
--- a/drivers/acpi/acpica/utstrsuppt.c
+++ b/drivers/acpi/acpica/utstrsuppt.c
@@ -45,10 +45,15 @@ acpi_status acpi_ut_convert_octal_string(char *string, u64 *return_value_ptr)
 	/* Convert each ASCII byte in the input string */
 
 	while (*string) {
-
-		/* Character must be ASCII 0-7, otherwise terminate with no error */
-
+		/*
+		 * Character must be ASCII 0-7, otherwise:
+		 * 1) Runtime: terminate with no error, per the ACPI spec
+		 * 2) Compiler: return an error
+		 */
 		if (!(ACPI_IS_OCTAL_DIGIT(*string))) {
+#ifdef ACPI_ASL_COMPILER
+			status = AE_BAD_OCTAL_CONSTANT;
+#endif
 			break;
 		}
 
@@ -94,10 +99,15 @@ acpi_status acpi_ut_convert_decimal_string(char *string, u64 *return_value_ptr)
 	/* Convert each ASCII byte in the input string */
 
 	while (*string) {
-
-		/* Character must be ASCII 0-9, otherwise terminate with no error */
-
-		if (!isdigit(*string)) {
+		/*
+		 * Character must be ASCII 0-9, otherwise:
+		 * 1) Runtime: terminate with no error, per the ACPI spec
+		 * 2) Compiler: return an error
+		 */
+		if (!isdigit((int)*string)) {
+#ifdef ACPI_ASL_COMPILER
+			status = AE_BAD_DECIMAL_CONSTANT;
+#endif
 			break;
 		}
 
@@ -143,10 +153,15 @@ acpi_status acpi_ut_convert_hex_string(char *string, u64 *return_value_ptr)
 	/* Convert each ASCII byte in the input string */
 
 	while (*string) {
-
-		/* Must be ASCII A-F, a-f, or 0-9, otherwise terminate with no error */
-
-		if (!isxdigit(*string)) {
+		/*
+		 * Character must be ASCII A-F, a-f, or 0-9, otherwise:
+		 * 1) Runtime: terminate with no error, per the ACPI spec
+		 * 2) Compiler: return an error
+		 */
+		if (!isxdigit((int)*string)) {
+#ifdef ACPI_ASL_COMPILER
+			status = AE_BAD_HEX_CONSTANT;
+#endif
 			break;
 		}
 
diff --git a/drivers/acpi/acpica/uttrack.c b/drivers/acpi/acpica/uttrack.c
index d366be431a84..a99c4c9e3d39 100644
--- a/drivers/acpi/acpica/uttrack.c
+++ b/drivers/acpi/acpica/uttrack.c
@@ -3,7 +3,7 @@
  *
  * Module Name: uttrack - Memory allocation tracking routines (debug only)
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/utuuid.c b/drivers/acpi/acpica/utuuid.c
index b8039954b0d1..0682554934ca 100644
--- a/drivers/acpi/acpica/utuuid.c
+++ b/drivers/acpi/acpica/utuuid.c
@@ -3,7 +3,7 @@
  *
  * Module Name: utuuid -- UUID support functions
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -61,4 +61,45 @@ void acpi_ut_convert_string_to_uuid(char *in_string, u8 *uuid_buffer)
 					       1]);
 	}
 }
+
+/*******************************************************************************
+ *
+ * FUNCTION:    acpi_ut_convert_uuid_to_string
+ *
+ * PARAMETERS:  uuid_buffer         - 16-byte UUID buffer
+ *              out_string          - 36-byte formatted UUID string
+ *
+ * RETURN:      Status
+ *
+ * DESCRIPTION: Convert 16-byte UUID buffer to 36-byte formatted UUID string
+ *              out_string must be 37 bytes to include null terminator.
+ *
+ ******************************************************************************/
+
+acpi_status acpi_ut_convert_uuid_to_string(char *uuid_buffer, char *out_string)
+{
+	u32 i;
+
+	if (!uuid_buffer || !out_string) {
+		return (AE_BAD_PARAMETER);
+	}
+
+	for (i = 0; i < UUID_BUFFER_LENGTH; i++) {
+		out_string[acpi_gbl_map_to_uuid_offset[i]] =
+		    acpi_ut_hex_to_ascii_char(uuid_buffer[i], 4);
+
+		out_string[acpi_gbl_map_to_uuid_offset[i] + 1] =
+		    acpi_ut_hex_to_ascii_char(uuid_buffer[i], 0);
+	}
+
+	/* Insert required hyphens (dashes) */
+
+	out_string[UUID_HYPHEN1_OFFSET] =
+	    out_string[UUID_HYPHEN2_OFFSET] =
+	    out_string[UUID_HYPHEN3_OFFSET] =
+	    out_string[UUID_HYPHEN4_OFFSET] = '-';
+
+	out_string[UUID_STRING_LENGTH] = 0;	/* Null terminate */
+	return (AE_OK);
+}
 #endif
diff --git a/drivers/acpi/acpica/utxface.c b/drivers/acpi/acpica/utxface.c
index ca7c9f0144ef..56942b5f026b 100644
--- a/drivers/acpi/acpica/utxface.c
+++ b/drivers/acpi/acpica/utxface.c
@@ -3,7 +3,7 @@
  *
  * Module Name: utxface - External interfaces, miscellaneous utility functions
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
diff --git a/drivers/acpi/acpica/utxfinit.c b/drivers/acpi/acpica/utxfinit.c
index 653e3bb20036..c1702f8fba67 100644
--- a/drivers/acpi/acpica/utxfinit.c
+++ b/drivers/acpi/acpica/utxfinit.c
@@ -3,7 +3,7 @@
  *
  * Module Name: utxfinit - External interfaces for ACPICA initialization
  *
- * Copyright (C) 2000 - 2020, Intel Corp.
+ * Copyright (C) 2000 - 2025, Intel Corp.
  *
  *****************************************************************************/
 
@@ -120,6 +120,18 @@ acpi_status ACPI_INIT_FUNCTION acpi_enable_subsystem(u32 flags)
 	 */
 	acpi_gbl_early_initialization = FALSE;
 
+	/*
+	 * Obtain a permanent mapping for the FACS. This is required for the
+	 * Global Lock and the Firmware Waking Vector
+	 */
+	if (!(flags & ACPI_NO_FACS_INIT)) {
+		status = acpi_tb_initialize_facs();
+		if (ACPI_FAILURE(status)) {
+			ACPI_WARNING((AE_INFO, "Could not map the FACS table"));
+			return_ACPI_STATUS(status);
+		}
+	}
+
 #if (!ACPI_REDUCED_HARDWARE)
 
 	/* Enable ACPI mode */
@@ -138,18 +150,6 @@ acpi_status ACPI_INIT_FUNCTION acpi_enable_subsystem(u32 flags)
 	}
 
 	/*
-	 * Obtain a permanent mapping for the FACS. This is required for the
-	 * Global Lock and the Firmware Waking Vector
-	 */
-	if (!(flags & ACPI_NO_FACS_INIT)) {
-		status = acpi_tb_initialize_facs();
-		if (ACPI_FAILURE(status)) {
-			ACPI_WARNING((AE_INFO, "Could not map the FACS table"));
-			return_ACPI_STATUS(status);
-		}
-	}
-
-	/*
 	 * Initialize ACPI Event handling (Fixed and General Purpose)
 	 *
 	 * Note1: We must have the hardware and events initialized before we can
diff --git a/drivers/acpi/apei/Kconfig b/drivers/acpi/apei/Kconfig
index 6b18f8bc7be3..070c07d68dfb 100644
--- a/drivers/acpi/apei/Kconfig
+++ b/drivers/acpi/apei/Kconfig
@@ -23,6 +23,7 @@ config ACPI_APEI_GHES
 	select ACPI_HED
 	select IRQ_WORK
 	select GENERIC_ALLOCATOR
+	select ARM_SDE_INTERFACE if ARM64
 	help
 	  Generic Hardware Error Source provides a way to report
 	  platform hardware errors (such as that from chipset). It
@@ -60,6 +61,19 @@ config ACPI_APEI_EINJ
 	  mainly used for debugging and testing the other parts of
 	  APEI and some other RAS features.
 
+config ACPI_APEI_EINJ_CXL
+	bool "CXL Error INJection Support"
+	default ACPI_APEI_EINJ
+	depends on ACPI_APEI_EINJ
+	depends on CXL_BUS && CXL_BUS <= ACPI_APEI_EINJ
+	help
+	  Support for CXL protocol Error INJection through debugfs/cxl.
+	  Availability and which errors are supported is dependent on
+	  the host platform. Look to ACPI v6.5 section 18.6.4 and kernel
+	  EINJ documentation for more information.
+
+	  If unsure say 'n'
+
 config ACPI_APEI_ERST_DEBUG
 	tristate "APEI Error Record Serialization Table (ERST) Debug Support"
 	depends on ACPI_APEI
diff --git a/drivers/acpi/apei/Makefile b/drivers/acpi/apei/Makefile
index 4dfac2128737..2c474e6477e1 100644
--- a/drivers/acpi/apei/Makefile
+++ b/drivers/acpi/apei/Makefile
@@ -2,6 +2,8 @@
 obj-$(CONFIG_ACPI_APEI)		+= apei.o
 obj-$(CONFIG_ACPI_APEI_GHES)	+= ghes.o
 obj-$(CONFIG_ACPI_APEI_EINJ)	+= einj.o
+einj-y				:= einj-core.o
+einj-$(CONFIG_ACPI_APEI_EINJ_CXL) += einj-cxl.o
 obj-$(CONFIG_ACPI_APEI_ERST_DEBUG) += erst-dbg.o
 
 apei-y := apei-base.o hest.o erst.o bert.o
diff --git a/drivers/acpi/apei/apei-base.c b/drivers/acpi/apei/apei-base.c
index e358d0046494..9c84f3da7c09 100644
--- a/drivers/acpi/apei/apei-base.c
+++ b/drivers/acpi/apei/apei-base.c
@@ -3,7 +3,7 @@
  * apei-base.c - ACPI Platform Error Interface (APEI) supporting
  * infrastructure
  *
- * APEI allows to report errors (for example from the chipset) to the
+ * APEI allows to report errors (for example from the chipset) to
  * the operating system. This improves NMI handling especially. In
  * addition it supports error serialization and error injection.
  *
@@ -25,10 +25,10 @@
 #include <linux/slab.h>
 #include <linux/io.h>
 #include <linux/kref.h>
-#include <linux/rculist.h>
 #include <linux/interrupt.h>
 #include <linux/debugfs.h>
-#include <asm/unaligned.h>
+#include <acpi/apei.h>
+#include <linux/unaligned.h>
 
 #include "apei-internal.h"
 
@@ -125,12 +125,9 @@ EXPORT_SYMBOL_GPL(apei_exec_write_register);
 int apei_exec_write_register_value(struct apei_exec_context *ctx,
 				   struct acpi_whea_header *entry)
 {
-	int rc;
-
 	ctx->value = entry->value;
-	rc = apei_exec_write_register(ctx, entry);
 
-	return rc;
+	return apei_exec_write_register(ctx, entry);
 }
 EXPORT_SYMBOL_GPL(apei_exec_write_register_value);
 
@@ -287,7 +284,7 @@ struct apei_res {
 };
 
 /* Collect all resources requested, to avoid conflict */
-struct apei_resources apei_resources_all = {
+static struct apei_resources apei_resources_all = {
 	.iomem = LIST_HEAD_INIT(apei_resources_all.iomem),
 	.ioport = LIST_HEAD_INIT(apei_resources_all.ioport),
 };
@@ -319,7 +316,7 @@ repeat:
 	if (res_ins)
 		list_add(&res_ins->list, res_list);
 	else {
-		res_ins = kmalloc(sizeof(*res), GFP_KERNEL);
+		res_ins = kmalloc(sizeof(*res_ins), GFP_KERNEL);
 		if (!res_ins)
 			return -ENOMEM;
 		res_ins->start = start;
@@ -632,7 +629,15 @@ int apei_map_generic_address(struct acpi_generic_address *reg)
 	rc = apei_check_gar(reg, &address, &access_bit_width);
 	if (rc)
 		return rc;
-	return acpi_os_map_generic_address(reg);
+
+	/* IO space doesn't need mapping */
+	if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO)
+		return 0;
+
+	if (!acpi_os_map_generic_address(reg))
+		return -ENXIO;
+
+	return 0;
 }
 EXPORT_SYMBOL_GPL(apei_map_generic_address);
 
diff --git a/drivers/acpi/apei/apei-internal.h b/drivers/acpi/apei/apei-internal.h
index 1d6ef9654725..77c10a7a7a9f 100644
--- a/drivers/acpi/apei/apei-internal.h
+++ b/drivers/acpi/apei/apei-internal.h
@@ -7,7 +7,6 @@
 #ifndef APEI_INTERNAL_H
 #define APEI_INTERNAL_H
 
-#include <linux/cper.h>
 #include <linux/acpi.h>
 
 struct apei_exec_context;
@@ -130,10 +129,23 @@ static inline u32 cper_estatus_len(struct acpi_hest_generic_status *estatus)
 		return sizeof(*estatus) + estatus->data_length;
 }
 
-void cper_estatus_print(const char *pfx,
-			const struct acpi_hest_generic_status *estatus);
-int cper_estatus_check_header(const struct acpi_hest_generic_status *estatus);
-int cper_estatus_check(const struct acpi_hest_generic_status *estatus);
-
 int apei_osc_setup(void);
+
+int einj_get_available_error_type(u32 *type, int einj_action);
+int einj_error_inject(u32 type, u32 flags, u64 param1, u64 param2, u64 param3,
+		      u64 param4);
+int einj_cxl_rch_error_inject(u32 type, u32 flags, u64 param1, u64 param2,
+			      u64 param3, u64 param4);
+bool einj_is_cxl_error_type(u64 type);
+int einj_validate_error_type(u64 type);
+
+#ifndef ACPI_EINJ_CXL_CACHE_CORRECTABLE
+#define ACPI_EINJ_CXL_CACHE_CORRECTABLE     BIT(12)
+#define ACPI_EINJ_CXL_CACHE_UNCORRECTABLE   BIT(13)
+#define ACPI_EINJ_CXL_CACHE_FATAL           BIT(14)
+#define ACPI_EINJ_CXL_MEM_CORRECTABLE       BIT(15)
+#define ACPI_EINJ_CXL_MEM_UNCORRECTABLE     BIT(16)
+#define ACPI_EINJ_CXL_MEM_FATAL             BIT(17)
+#endif
+
 #endif
diff --git a/drivers/acpi/apei/bert.c b/drivers/acpi/apei/bert.c
index 1155fb9dcc3a..5427e49e646b 100644
--- a/drivers/acpi/apei/bert.c
+++ b/drivers/acpi/apei/bert.c
@@ -23,6 +23,7 @@
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/acpi.h>
+#include <linux/cper.h>
 #include <linux/io.h>
 
 #include "apei-internal.h"
@@ -30,14 +31,25 @@
 #undef pr_fmt
 #define pr_fmt(fmt) "BERT: " fmt
 
-static int bert_disable;
+#define ACPI_BERT_PRINT_MAX_RECORDS 5
+#define ACPI_BERT_PRINT_MAX_LEN 1024
 
+static int bert_disable __initdata;
+
+/*
+ * Print "all" the error records in the BERT table, but avoid huge spam to
+ * the console if the BIOS included oversize records, or too many records.
+ * Skipping some records here does not lose anything because the full
+ * data is available to user tools in:
+ *	/sys/firmware/acpi/tables/data/BERT
+ */
 static void __init bert_print_all(struct acpi_bert_region *region,
 				  unsigned int region_len)
 {
 	struct acpi_hest_generic_status *estatus =
 		(struct acpi_hest_generic_status *)region;
 	int remain = region_len;
+	int printed = 0, skipped = 0;
 	u32 estatus_len;
 
 	while (remain >= sizeof(struct acpi_bert_region)) {
@@ -45,21 +57,26 @@ static void __init bert_print_all(struct acpi_bert_region *region,
 		if (remain < estatus_len) {
 			pr_err(FW_BUG "Truncated status block (length: %u).\n",
 			       estatus_len);
-			return;
+			break;
 		}
 
 		/* No more error records. */
 		if (!estatus->block_status)
-			return;
+			break;
 
 		if (cper_estatus_check(estatus)) {
 			pr_err(FW_BUG "Invalid error record.\n");
-			return;
+			break;
 		}
 
-		pr_info_once("Error records from previous boot:\n");
-
-		cper_estatus_print(KERN_INFO HW_ERR, estatus);
+		if (estatus_len < ACPI_BERT_PRINT_MAX_LEN &&
+		    printed < ACPI_BERT_PRINT_MAX_RECORDS) {
+			pr_info_once("Error records from previous boot:\n");
+			cper_estatus_print(KERN_INFO HW_ERR, estatus);
+			printed++;
+		} else {
+			skipped++;
+		}
 
 		/*
 		 * Because the boot error source is "one-time polled" type,
@@ -71,13 +88,19 @@ static void __init bert_print_all(struct acpi_bert_region *region,
 		estatus = (void *)estatus + estatus_len;
 		remain -= estatus_len;
 	}
+
+	if (skipped)
+		pr_info(HW_ERR "Skipped %d error records\n", skipped);
+
+	if (printed + skipped)
+		pr_info("Total records found: %d\n", printed + skipped);
 }
 
 static int __init setup_bert_disable(char *str)
 {
 	bert_disable = 1;
 
-	return 0;
+	return 1;
 }
 __setup("bert_disable", setup_bert_disable);
 
@@ -119,7 +142,7 @@ static int __init bert_init(void)
 	rc = bert_check_table(bert_tab);
 	if (rc) {
 		pr_err(FW_BUG "table invalid.\n");
-		return rc;
+		goto out_put_bert_tab;
 	}
 
 	region_len = bert_tab->region_length;
@@ -127,7 +150,7 @@ static int __init bert_init(void)
 	rc = apei_resources_add(&bert_resources, bert_tab->address,
 				region_len, true);
 	if (rc)
-		return rc;
+		goto out_put_bert_tab;
 	rc = apei_resources_request(&bert_resources, "APEI BERT");
 	if (rc)
 		goto out_fini;
@@ -142,6 +165,8 @@ static int __init bert_init(void)
 	apei_resources_release(&bert_resources);
 out_fini:
 	apei_resources_fini(&bert_resources);
+out_put_bert_tab:
+	acpi_put_table((struct acpi_table_header *)bert_tab);
 
 	return rc;
 }
diff --git a/drivers/acpi/apei/einj-core.c b/drivers/acpi/apei/einj-core.c
new file mode 100644
index 000000000000..305c240a303f
--- /dev/null
+++ b/drivers/acpi/apei/einj-core.c
@@ -0,0 +1,1201 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * APEI Error INJection support
+ *
+ * EINJ provides a hardware error injection mechanism, this is useful
+ * for debugging and testing of other APEI and RAS features.
+ *
+ * For more information about EINJ, please refer to ACPI Specification
+ * version 4.0, section 17.5.
+ *
+ * Copyright 2009-2010 Intel Corp.
+ *   Author: Huang Ying <ying.huang@intel.com>
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#include <linux/nmi.h>
+#include <linux/delay.h>
+#include <linux/mm.h>
+#include <linux/device/faux.h>
+#include <linux/unaligned.h>
+
+#include "apei-internal.h"
+
+#undef pr_fmt
+#define pr_fmt(fmt) "EINJ: " fmt
+
+#define SLEEP_UNIT_MIN		1000			/* 1ms */
+#define SLEEP_UNIT_MAX		5000			/* 5ms */
+/* Firmware should respond within 1 seconds */
+#define FIRMWARE_TIMEOUT	(1 * USEC_PER_SEC)
+#define COMPONENT_LEN		16
+#define ACPI65_EINJV2_SUPP	BIT(30)
+#define ACPI5_VENDOR_BIT	BIT(31)
+#define MEM_ERROR_MASK		(ACPI_EINJ_MEMORY_CORRECTABLE | \
+				ACPI_EINJ_MEMORY_UNCORRECTABLE | \
+				ACPI_EINJ_MEMORY_FATAL)
+#define CXL_ERROR_MASK		(ACPI_EINJ_CXL_CACHE_CORRECTABLE | \
+				ACPI_EINJ_CXL_CACHE_UNCORRECTABLE | \
+				ACPI_EINJ_CXL_CACHE_FATAL | \
+				ACPI_EINJ_CXL_MEM_CORRECTABLE | \
+				ACPI_EINJ_CXL_MEM_UNCORRECTABLE | \
+				ACPI_EINJ_CXL_MEM_FATAL)
+
+/*
+ * ACPI version 5 provides a SET_ERROR_TYPE_WITH_ADDRESS action.
+ */
+static int acpi5;
+
+struct syndrome_array {
+	union {
+		u8	acpi_id[COMPONENT_LEN];
+		u8	device_id[COMPONENT_LEN];
+		u8	pcie_sbdf[COMPONENT_LEN];
+		u8	vendor_id[COMPONENT_LEN];
+	} comp_id;
+	union {
+		u8	proc_synd[COMPONENT_LEN];
+		u8	mem_synd[COMPONENT_LEN];
+		u8	pcie_synd[COMPONENT_LEN];
+		u8	vendor_synd[COMPONENT_LEN];
+	} comp_synd;
+};
+
+struct einjv2_extension_struct {
+	u32 length;
+	u16 revision;
+	u16 component_arr_count;
+	struct syndrome_array component_arr[] __counted_by(component_arr_count);
+};
+
+struct set_error_type_with_address {
+	u32	type;
+	u32	vendor_extension;
+	u32	flags;
+	u32	apicid;
+	u64	memory_address;
+	u64	memory_address_range;
+	u32	pcie_sbdf;
+	struct	einjv2_extension_struct einjv2_struct;
+};
+enum {
+	SETWA_FLAGS_APICID = 1,
+	SETWA_FLAGS_MEM = 2,
+	SETWA_FLAGS_PCIE_SBDF = 4,
+	SETWA_FLAGS_EINJV2 = 8,
+};
+
+/*
+ * Vendor extensions for platform specific operations
+ */
+struct vendor_error_type_extension {
+	u32	length;
+	u32	pcie_sbdf;
+	u16	vendor_id;
+	u16	device_id;
+	u8	rev_id;
+	u8	reserved[3];
+};
+
+static u32 notrigger;
+
+static u32 vendor_flags;
+static struct debugfs_blob_wrapper vendor_blob;
+static struct debugfs_blob_wrapper vendor_errors;
+static char vendor_dev[64];
+
+static u32 max_nr_components;
+static u32 available_error_type;
+static u32 available_error_type_v2;
+static struct syndrome_array *syndrome_data;
+
+/*
+ * Some BIOSes allow parameters to the SET_ERROR_TYPE entries in the
+ * EINJ table through an unpublished extension. Use with caution as
+ * most will ignore the parameter and make their own choice of address
+ * for error injection.  This extension is used only if
+ * param_extension module parameter is specified.
+ */
+struct einj_parameter {
+	u64 type;
+	u64 reserved1;
+	u64 reserved2;
+	u64 param1;
+	u64 param2;
+};
+
+#define EINJ_OP_BUSY			0x1
+#define EINJ_STATUS_SUCCESS		0x0
+#define EINJ_STATUS_FAIL		0x1
+#define EINJ_STATUS_INVAL		0x2
+
+#define EINJ_TAB_ENTRY(tab)						\
+	((struct acpi_whea_header *)((char *)(tab) +			\
+				    sizeof(struct acpi_table_einj)))
+
+static bool param_extension;
+module_param(param_extension, bool, 0);
+
+static struct acpi_table_einj *einj_tab;
+
+static struct apei_resources einj_resources;
+
+static struct apei_exec_ins_type einj_ins_type[] = {
+	[ACPI_EINJ_READ_REGISTER] = {
+		.flags = APEI_EXEC_INS_ACCESS_REGISTER,
+		.run   = apei_exec_read_register,
+	},
+	[ACPI_EINJ_READ_REGISTER_VALUE] = {
+		.flags = APEI_EXEC_INS_ACCESS_REGISTER,
+		.run   = apei_exec_read_register_value,
+	},
+	[ACPI_EINJ_WRITE_REGISTER] = {
+		.flags = APEI_EXEC_INS_ACCESS_REGISTER,
+		.run   = apei_exec_write_register,
+	},
+	[ACPI_EINJ_WRITE_REGISTER_VALUE] = {
+		.flags = APEI_EXEC_INS_ACCESS_REGISTER,
+		.run   = apei_exec_write_register_value,
+	},
+	[ACPI_EINJ_NOOP] = {
+		.flags = 0,
+		.run   = apei_exec_noop,
+	},
+};
+
+/*
+ * Prevent EINJ interpreter to run simultaneously, because the
+ * corresponding firmware implementation may not work properly when
+ * invoked simultaneously.
+ */
+static DEFINE_MUTEX(einj_mutex);
+
+/*
+ * Exported APIs use this flag to exit early if einj_probe() failed.
+ */
+bool einj_initialized __ro_after_init;
+
+static void __iomem *einj_param;
+static u32 v5param_size;
+static u32 v66param_size;
+static bool is_v2;
+
+static void einj_exec_ctx_init(struct apei_exec_context *ctx)
+{
+	apei_exec_ctx_init(ctx, einj_ins_type, ARRAY_SIZE(einj_ins_type),
+			   EINJ_TAB_ENTRY(einj_tab), einj_tab->entries);
+}
+
+static int __einj_get_available_error_type(u32 *type, int einj_action)
+{
+	struct apei_exec_context ctx;
+	int rc;
+
+	einj_exec_ctx_init(&ctx);
+	rc = apei_exec_run(&ctx, einj_action);
+	if (rc)
+		return rc;
+	*type = apei_exec_ctx_get_output(&ctx);
+
+	return 0;
+}
+
+/* Get error injection capabilities of the platform */
+int einj_get_available_error_type(u32 *type, int einj_action)
+{
+	int rc;
+
+	mutex_lock(&einj_mutex);
+	rc = __einj_get_available_error_type(type, einj_action);
+	mutex_unlock(&einj_mutex);
+
+	return rc;
+}
+
+static int einj_get_available_error_types(u32 *type1, u32 *type2)
+{
+	int rc;
+
+	rc = einj_get_available_error_type(type1, ACPI_EINJ_GET_ERROR_TYPE);
+	if (rc)
+		return rc;
+	if (*type1 & ACPI65_EINJV2_SUPP) {
+		rc = einj_get_available_error_type(type2,
+						   ACPI_EINJV2_GET_ERROR_TYPE);
+		if (rc)
+			return rc;
+	}
+
+	return 0;
+}
+
+static int einj_timedout(u64 *t)
+{
+	if ((s64)*t < SLEEP_UNIT_MIN) {
+		pr_warn(FW_WARN "Firmware does not respond in time\n");
+		return 1;
+	}
+	*t -= SLEEP_UNIT_MIN;
+	usleep_range(SLEEP_UNIT_MIN, SLEEP_UNIT_MAX);
+
+	return 0;
+}
+
+static void get_oem_vendor_struct(u64 paddr, int offset,
+				  struct vendor_error_type_extension *v)
+{
+	unsigned long vendor_size;
+	u64 target_pa = paddr + offset + sizeof(struct vendor_error_type_extension);
+
+	vendor_size = v->length - sizeof(struct vendor_error_type_extension);
+
+	if (vendor_size)
+		vendor_errors.data = acpi_os_map_memory(target_pa, vendor_size);
+
+	if (vendor_errors.data)
+		vendor_errors.size = vendor_size;
+}
+
+static void check_vendor_extension(u64 paddr,
+				   struct set_error_type_with_address *v5param)
+{
+	int	offset = v5param->vendor_extension;
+	struct	vendor_error_type_extension v;
+	struct vendor_error_type_extension __iomem *p;
+	u32	sbdf;
+
+	if (!offset)
+		return;
+	p = acpi_os_map_iomem(paddr + offset, sizeof(*p));
+	if (!p)
+		return;
+	memcpy_fromio(&v, p, sizeof(v));
+	get_oem_vendor_struct(paddr, offset, &v);
+	sbdf = v.pcie_sbdf;
+	sprintf(vendor_dev, "%x:%x:%x.%x vendor_id=%x device_id=%x rev_id=%x\n",
+		sbdf >> 24, (sbdf >> 16) & 0xff,
+		(sbdf >> 11) & 0x1f, (sbdf >> 8) & 0x7,
+		 v.vendor_id, v.device_id, v.rev_id);
+	acpi_os_unmap_iomem(p, sizeof(v));
+}
+
+static u32 einjv2_init(struct einjv2_extension_struct *e)
+{
+	if (e->revision != 1) {
+		pr_info("Unknown v2 extension revision %u\n", e->revision);
+		return 0;
+	}
+	if (e->length < sizeof(*e) || e->length > PAGE_SIZE) {
+		pr_info(FW_BUG "Bad1 v2 extension length %u\n", e->length);
+		return 0;
+	}
+	if ((e->length - sizeof(*e)) % sizeof(e->component_arr[0])) {
+		pr_info(FW_BUG "Bad2 v2 extension length %u\n", e->length);
+		return 0;
+	}
+
+	return (e->length - sizeof(*e)) / sizeof(e->component_arr[0]);
+}
+
+static void __iomem *einj_get_parameter_address(void)
+{
+	int i;
+	u64 pa_v4 = 0, pa_v5 = 0;
+	struct acpi_whea_header *entry;
+
+	entry = EINJ_TAB_ENTRY(einj_tab);
+	for (i = 0; i < einj_tab->entries; i++) {
+		if (entry->action == ACPI_EINJ_SET_ERROR_TYPE &&
+		    entry->instruction == ACPI_EINJ_WRITE_REGISTER &&
+		    entry->register_region.space_id ==
+		    ACPI_ADR_SPACE_SYSTEM_MEMORY)
+			pa_v4 = get_unaligned(&entry->register_region.address);
+		if (entry->action == ACPI_EINJ_SET_ERROR_TYPE_WITH_ADDRESS &&
+		    entry->instruction == ACPI_EINJ_WRITE_REGISTER &&
+		    entry->register_region.space_id ==
+		    ACPI_ADR_SPACE_SYSTEM_MEMORY)
+			pa_v5 = get_unaligned(&entry->register_region.address);
+		entry++;
+	}
+	if (pa_v5) {
+		struct set_error_type_with_address v5param;
+		struct set_error_type_with_address __iomem *p;
+
+		v5param_size = sizeof(v5param);
+		p = acpi_os_map_iomem(pa_v5, sizeof(*p));
+		if (p) {
+			memcpy_fromio(&v5param, p, v5param_size);
+			acpi5 = 1;
+			check_vendor_extension(pa_v5, &v5param);
+			if (available_error_type & ACPI65_EINJV2_SUPP) {
+				struct einjv2_extension_struct *e;
+
+				e = &v5param.einjv2_struct;
+				max_nr_components = einjv2_init(e);
+
+				/* remap including einjv2_extension_struct */
+				acpi_os_unmap_iomem(p, v5param_size);
+				v66param_size = v5param_size - sizeof(*e) + e->length;
+				p = acpi_os_map_iomem(pa_v5, v66param_size);
+			}
+
+			return p;
+		}
+	}
+	if (param_extension && pa_v4) {
+		struct einj_parameter v4param;
+		struct einj_parameter __iomem *p;
+
+		p = acpi_os_map_iomem(pa_v4, sizeof(*p));
+		if (!p)
+			return NULL;
+		memcpy_fromio(&v4param, p, sizeof(v4param));
+		if (v4param.reserved1 || v4param.reserved2) {
+			acpi_os_unmap_iomem(p, sizeof(v4param));
+			return NULL;
+		}
+		return p;
+	}
+
+	return NULL;
+}
+
+/* do sanity check to trigger table */
+static int einj_check_trigger_header(struct acpi_einj_trigger *trigger_tab)
+{
+	if (trigger_tab->header_size != sizeof(struct acpi_einj_trigger))
+		return -EINVAL;
+	if (trigger_tab->table_size > PAGE_SIZE ||
+	    trigger_tab->table_size < trigger_tab->header_size)
+		return -EINVAL;
+	if (trigger_tab->entry_count !=
+	    (trigger_tab->table_size - trigger_tab->header_size) /
+	    sizeof(struct acpi_einj_entry))
+		return -EINVAL;
+
+	return 0;
+}
+
+static struct acpi_generic_address *einj_get_trigger_parameter_region(
+	struct acpi_einj_trigger *trigger_tab, u64 param1, u64 param2)
+{
+	int i;
+	struct acpi_whea_header *entry;
+
+	entry = (struct acpi_whea_header *)
+		((char *)trigger_tab + sizeof(struct acpi_einj_trigger));
+	for (i = 0; i < trigger_tab->entry_count; i++) {
+		if (entry->action == ACPI_EINJ_TRIGGER_ERROR &&
+		entry->instruction <= ACPI_EINJ_WRITE_REGISTER_VALUE &&
+		entry->register_region.space_id ==
+			ACPI_ADR_SPACE_SYSTEM_MEMORY &&
+		(entry->register_region.address & param2) == (param1 & param2))
+			return &entry->register_region;
+		entry++;
+	}
+
+	return NULL;
+}
+/* Execute instructions in trigger error action table */
+static int __einj_error_trigger(u64 trigger_paddr, u32 type,
+				u64 param1, u64 param2)
+{
+	struct acpi_einj_trigger trigger_tab;
+	struct acpi_einj_trigger *full_trigger_tab;
+	struct apei_exec_context trigger_ctx;
+	struct apei_resources trigger_resources;
+	struct acpi_whea_header *trigger_entry;
+	struct resource *r;
+	u32 table_size;
+	int rc = -EIO;
+	struct acpi_generic_address *trigger_param_region = NULL;
+	struct acpi_einj_trigger __iomem *p = NULL;
+
+	r = request_mem_region(trigger_paddr, sizeof(trigger_tab),
+			       "APEI EINJ Trigger Table");
+	if (!r) {
+		pr_err("Can not request [mem %#010llx-%#010llx] for Trigger table\n",
+		       (unsigned long long)trigger_paddr,
+		       (unsigned long long)trigger_paddr +
+			    sizeof(trigger_tab) - 1);
+		goto out;
+	}
+	p = ioremap_cache(trigger_paddr, sizeof(*p));
+	if (!p) {
+		pr_err("Failed to map trigger table!\n");
+		goto out_rel_header;
+	}
+	memcpy_fromio(&trigger_tab, p, sizeof(trigger_tab));
+	rc = einj_check_trigger_header(&trigger_tab);
+	if (rc) {
+		pr_warn(FW_BUG "Invalid trigger error action table.\n");
+		goto out_rel_header;
+	}
+
+	/* No action structures in the TRIGGER_ERROR table, nothing to do */
+	if (!trigger_tab.entry_count)
+		goto out_rel_header;
+
+	rc = -EIO;
+	table_size = trigger_tab.table_size;
+	full_trigger_tab = kmalloc(table_size, GFP_KERNEL);
+	if (!full_trigger_tab)
+		goto out_rel_header;
+	r = request_mem_region(trigger_paddr + sizeof(trigger_tab),
+			       table_size - sizeof(trigger_tab),
+			       "APEI EINJ Trigger Table");
+	if (!r) {
+		pr_err("Can not request [mem %#010llx-%#010llx] for Trigger Table Entry\n",
+		       (unsigned long long)trigger_paddr + sizeof(trigger_tab),
+		       (unsigned long long)trigger_paddr + table_size - 1);
+		goto out_free_trigger_tab;
+	}
+	iounmap(p);
+	p = ioremap_cache(trigger_paddr, table_size);
+	if (!p) {
+		pr_err("Failed to map trigger table!\n");
+		goto out_rel_entry;
+	}
+	memcpy_fromio(full_trigger_tab, p, table_size);
+	trigger_entry = (struct acpi_whea_header *)
+		((char *)full_trigger_tab + sizeof(struct acpi_einj_trigger));
+	apei_resources_init(&trigger_resources);
+	apei_exec_ctx_init(&trigger_ctx, einj_ins_type,
+			   ARRAY_SIZE(einj_ins_type),
+			   trigger_entry, trigger_tab.entry_count);
+	rc = apei_exec_collect_resources(&trigger_ctx, &trigger_resources);
+	if (rc)
+		goto out_fini;
+	rc = apei_resources_sub(&trigger_resources, &einj_resources);
+	if (rc)
+		goto out_fini;
+	/*
+	 * Some firmware will access target address specified in
+	 * param1 to trigger the error when injecting memory error.
+	 * This will cause resource conflict with regular memory.  So
+	 * remove it from trigger table resources.
+	 */
+	if ((param_extension || acpi5) && (type & MEM_ERROR_MASK) && param2) {
+		struct apei_resources addr_resources;
+
+		apei_resources_init(&addr_resources);
+		trigger_param_region = einj_get_trigger_parameter_region(
+			full_trigger_tab, param1, param2);
+		if (trigger_param_region) {
+			rc = apei_resources_add(&addr_resources,
+				trigger_param_region->address,
+				trigger_param_region->bit_width/8, true);
+			if (rc)
+				goto out_fini;
+			rc = apei_resources_sub(&trigger_resources,
+					&addr_resources);
+		}
+		apei_resources_fini(&addr_resources);
+		if (rc)
+			goto out_fini;
+	}
+	rc = apei_resources_request(&trigger_resources, "APEI EINJ Trigger");
+	if (rc)
+		goto out_fini;
+	rc = apei_exec_pre_map_gars(&trigger_ctx);
+	if (rc)
+		goto out_release;
+
+	rc = apei_exec_run(&trigger_ctx, ACPI_EINJ_TRIGGER_ERROR);
+
+	apei_exec_post_unmap_gars(&trigger_ctx);
+out_release:
+	apei_resources_release(&trigger_resources);
+out_fini:
+	apei_resources_fini(&trigger_resources);
+out_rel_entry:
+	release_mem_region(trigger_paddr + sizeof(trigger_tab),
+			   table_size - sizeof(trigger_tab));
+out_free_trigger_tab:
+	kfree(full_trigger_tab);
+out_rel_header:
+	release_mem_region(trigger_paddr, sizeof(trigger_tab));
+out:
+	if (p)
+		iounmap(p);
+
+	return rc;
+}
+
+static bool is_end_of_list(u8 *val)
+{
+	for (int i = 0; i < COMPONENT_LEN; ++i) {
+		if (val[i] != 0xFF)
+			return false;
+	}
+	return true;
+}
+static int __einj_error_inject(u32 type, u32 flags, u64 param1, u64 param2,
+			       u64 param3, u64 param4)
+{
+	struct apei_exec_context ctx;
+	u32 param_size = is_v2 ? v66param_size : v5param_size;
+	u64 val, trigger_paddr, timeout = FIRMWARE_TIMEOUT;
+	int i, rc;
+
+	einj_exec_ctx_init(&ctx);
+
+	rc = apei_exec_run_optional(&ctx, ACPI_EINJ_BEGIN_OPERATION);
+	if (rc)
+		return rc;
+	apei_exec_ctx_set_input(&ctx, type);
+	if (acpi5) {
+		struct set_error_type_with_address *v5param;
+
+		v5param = kmalloc(param_size, GFP_KERNEL);
+		if (!v5param)
+			return -ENOMEM;
+
+		memcpy_fromio(v5param, einj_param, param_size);
+		v5param->type = type;
+		if (type & ACPI5_VENDOR_BIT) {
+			switch (vendor_flags) {
+			case SETWA_FLAGS_APICID:
+				v5param->apicid = param1;
+				break;
+			case SETWA_FLAGS_MEM:
+				v5param->memory_address = param1;
+				v5param->memory_address_range = param2;
+				break;
+			case SETWA_FLAGS_PCIE_SBDF:
+				v5param->pcie_sbdf = param1;
+				break;
+			}
+			v5param->flags = vendor_flags;
+		} else if (flags) {
+			v5param->flags = flags;
+			v5param->memory_address = param1;
+			v5param->memory_address_range = param2;
+
+			if (is_v2) {
+				for (i = 0; i < max_nr_components; i++) {
+					if (is_end_of_list(syndrome_data[i].comp_id.acpi_id))
+						break;
+					v5param->einjv2_struct.component_arr[i].comp_id =
+						syndrome_data[i].comp_id;
+					v5param->einjv2_struct.component_arr[i].comp_synd =
+						syndrome_data[i].comp_synd;
+				}
+				v5param->einjv2_struct.component_arr_count = i;
+			} else {
+				v5param->apicid = param3;
+				v5param->pcie_sbdf = param4;
+			}
+		} else {
+			switch (type) {
+			case ACPI_EINJ_PROCESSOR_CORRECTABLE:
+			case ACPI_EINJ_PROCESSOR_UNCORRECTABLE:
+			case ACPI_EINJ_PROCESSOR_FATAL:
+				v5param->apicid = param1;
+				v5param->flags = SETWA_FLAGS_APICID;
+				break;
+			case ACPI_EINJ_MEMORY_CORRECTABLE:
+			case ACPI_EINJ_MEMORY_UNCORRECTABLE:
+			case ACPI_EINJ_MEMORY_FATAL:
+				v5param->memory_address = param1;
+				v5param->memory_address_range = param2;
+				v5param->flags = SETWA_FLAGS_MEM;
+				break;
+			case ACPI_EINJ_PCIX_CORRECTABLE:
+			case ACPI_EINJ_PCIX_UNCORRECTABLE:
+			case ACPI_EINJ_PCIX_FATAL:
+				v5param->pcie_sbdf = param1;
+				v5param->flags = SETWA_FLAGS_PCIE_SBDF;
+				break;
+			}
+		}
+		memcpy_toio(einj_param, v5param, param_size);
+		kfree(v5param);
+	} else {
+		rc = apei_exec_run(&ctx, ACPI_EINJ_SET_ERROR_TYPE);
+		if (rc)
+			return rc;
+		if (einj_param) {
+			struct einj_parameter v4param;
+
+			memcpy_fromio(&v4param, einj_param, sizeof(v4param));
+			v4param.param1 = param1;
+			v4param.param2 = param2;
+			memcpy_toio(einj_param, &v4param, sizeof(v4param));
+		}
+	}
+	rc = apei_exec_run(&ctx, ACPI_EINJ_EXECUTE_OPERATION);
+	if (rc)
+		return rc;
+	for (;;) {
+		rc = apei_exec_run(&ctx, ACPI_EINJ_CHECK_BUSY_STATUS);
+		if (rc)
+			return rc;
+		val = apei_exec_ctx_get_output(&ctx);
+		if (!(val & EINJ_OP_BUSY))
+			break;
+		if (einj_timedout(&timeout))
+			return -EIO;
+	}
+	rc = apei_exec_run(&ctx, ACPI_EINJ_GET_COMMAND_STATUS);
+	if (rc)
+		return rc;
+	val = apei_exec_ctx_get_output(&ctx);
+	if (val == EINJ_STATUS_FAIL)
+		return -EBUSY;
+	else if (val == EINJ_STATUS_INVAL)
+		return -EINVAL;
+
+	/*
+	 * The error is injected into the platform successfully, then it needs
+	 * to trigger the error.
+	 */
+	rc = apei_exec_run(&ctx, ACPI_EINJ_GET_TRIGGER_TABLE);
+	if (rc)
+		return rc;
+	trigger_paddr = apei_exec_ctx_get_output(&ctx);
+	if (notrigger == 0) {
+		rc = __einj_error_trigger(trigger_paddr, type, param1, param2);
+		if (rc)
+			return rc;
+	}
+	rc = apei_exec_run_optional(&ctx, ACPI_EINJ_END_OPERATION);
+
+	return rc;
+}
+
+/* Allow almost all types of address except MMIO. */
+static bool is_allowed_range(u64 base_addr, u64 size)
+{
+	int i;
+	/*
+	 * MMIO region is usually claimed with IORESOURCE_MEM + IORES_DESC_NONE.
+	 * However, IORES_DESC_NONE is treated like a wildcard when we check if
+	 * region intersects with known resource. So do an allow list check for
+	 * IORES_DESCs that definitely or most likely not MMIO.
+	 */
+	int non_mmio_desc[] = {
+		IORES_DESC_CRASH_KERNEL,
+		IORES_DESC_ACPI_TABLES,
+		IORES_DESC_ACPI_NV_STORAGE,
+		IORES_DESC_PERSISTENT_MEMORY,
+		IORES_DESC_PERSISTENT_MEMORY_LEGACY,
+		/* Treat IORES_DESC_DEVICE_PRIVATE_MEMORY as MMIO. */
+		IORES_DESC_RESERVED,
+		IORES_DESC_SOFT_RESERVED,
+	};
+
+	if (region_intersects(base_addr, size, IORESOURCE_SYSTEM_RAM, IORES_DESC_NONE)
+			      == REGION_INTERSECTS)
+		return true;
+
+	for (i = 0; i < ARRAY_SIZE(non_mmio_desc); ++i) {
+		if (region_intersects(base_addr, size, IORESOURCE_MEM, non_mmio_desc[i])
+				      == REGION_INTERSECTS)
+			return true;
+	}
+
+	if (arch_is_platform_page(base_addr))
+		return true;
+
+	return false;
+}
+
+/* Inject the specified hardware error */
+int einj_error_inject(u32 type, u32 flags, u64 param1, u64 param2, u64 param3,
+		      u64 param4)
+{
+	int rc;
+	u64 base_addr, size;
+
+	/* If user manually set "flags", make sure it is legal */
+	if (flags && (flags & ~(SETWA_FLAGS_APICID | SETWA_FLAGS_MEM |
+		      SETWA_FLAGS_PCIE_SBDF | SETWA_FLAGS_EINJV2)))
+		return -EINVAL;
+
+	/* check if type is a valid EINJv2 error type */
+	if (is_v2) {
+		if (!(type & available_error_type_v2))
+			return -EINVAL;
+	}
+	/*
+	 * We need extra sanity checks for memory errors.
+	 * Other types leap directly to injection.
+	 */
+
+	/* ensure param1/param2 existed */
+	if (!(param_extension || acpi5))
+		goto inject;
+
+	/* ensure injection is memory related */
+	if (type & ACPI5_VENDOR_BIT) {
+		if (vendor_flags != SETWA_FLAGS_MEM)
+			goto inject;
+	} else if (!(type & MEM_ERROR_MASK) && !(flags & SETWA_FLAGS_MEM)) {
+		goto inject;
+	}
+
+	/*
+	 * Injections targeting a CXL 1.0/1.1 port have to be injected
+	 * via the einj_cxl_rch_error_inject() path as that does the proper
+	 * validation of the given RCRB base (MMIO) address.
+	 */
+	if (einj_is_cxl_error_type(type) && (flags & SETWA_FLAGS_MEM))
+		return -EINVAL;
+
+	/*
+	 * Disallow crazy address masks that give BIOS leeway to pick
+	 * injection address almost anywhere. Insist on page or
+	 * better granularity and that target address is normal RAM or
+	 * as long as is not MMIO.
+	 */
+	base_addr = param1 & param2;
+	size = ~param2 + 1;
+
+	if ((param2 & PAGE_MASK) != PAGE_MASK)
+		return -EINVAL;
+
+	if (!is_allowed_range(base_addr, size))
+		return -EINVAL;
+
+	if (is_zero_pfn(base_addr >> PAGE_SHIFT))
+		return -EADDRINUSE;
+
+inject:
+	mutex_lock(&einj_mutex);
+	rc = __einj_error_inject(type, flags, param1, param2, param3, param4);
+	mutex_unlock(&einj_mutex);
+
+	return rc;
+}
+
+int einj_cxl_rch_error_inject(u32 type, u32 flags, u64 param1, u64 param2,
+			      u64 param3, u64 param4)
+{
+	int rc;
+
+	if (!(einj_is_cxl_error_type(type) && (flags & SETWA_FLAGS_MEM)))
+		return -EINVAL;
+
+	mutex_lock(&einj_mutex);
+	rc = __einj_error_inject(type, flags, param1, param2, param3, param4);
+	mutex_unlock(&einj_mutex);
+
+	return rc;
+}
+
+static u32 error_type;
+static u32 error_flags;
+static u64 error_param1;
+static u64 error_param2;
+static u64 error_param3;
+static u64 error_param4;
+static struct dentry *einj_debug_dir;
+static char einj_buf[32];
+static bool einj_v2_enabled;
+static struct { u32 mask; const char *str; } const einj_error_type_string[] = {
+	{ BIT(0), "Processor Correctable" },
+	{ BIT(1), "Processor Uncorrectable non-fatal" },
+	{ BIT(2), "Processor Uncorrectable fatal" },
+	{ BIT(3), "Memory Correctable" },
+	{ BIT(4), "Memory Uncorrectable non-fatal" },
+	{ BIT(5), "Memory Uncorrectable fatal" },
+	{ BIT(6), "PCI Express Correctable" },
+	{ BIT(7), "PCI Express Uncorrectable non-fatal" },
+	{ BIT(8), "PCI Express Uncorrectable fatal" },
+	{ BIT(9), "Platform Correctable" },
+	{ BIT(10), "Platform Uncorrectable non-fatal" },
+	{ BIT(11), "Platform Uncorrectable fatal"},
+	{ BIT(31), "Vendor Defined Error Types" },
+};
+
+static struct { u32 mask; const char *str; } const einjv2_error_type_string[] = {
+	{ BIT(0), "EINJV2 Processor Error" },
+	{ BIT(1), "EINJV2 Memory Error" },
+	{ BIT(2), "EINJV2 PCI Express Error" },
+};
+
+static int available_error_type_show(struct seq_file *m, void *v)
+{
+
+	for (int pos = 0; pos < ARRAY_SIZE(einj_error_type_string); pos++)
+		if (available_error_type & einj_error_type_string[pos].mask)
+			seq_printf(m, "0x%08x\t%s\n", einj_error_type_string[pos].mask,
+				   einj_error_type_string[pos].str);
+	if ((available_error_type & ACPI65_EINJV2_SUPP) && einj_v2_enabled) {
+		for (int pos = 0; pos < ARRAY_SIZE(einjv2_error_type_string); pos++) {
+			if (available_error_type_v2 & einjv2_error_type_string[pos].mask)
+				seq_printf(m, "V2_0x%08x\t%s\n", einjv2_error_type_string[pos].mask,
+					   einjv2_error_type_string[pos].str);
+		}
+	}
+	return 0;
+}
+
+DEFINE_SHOW_ATTRIBUTE(available_error_type);
+
+static ssize_t error_type_get(struct file *file, char __user *buf,
+				size_t count, loff_t *ppos)
+{
+	return simple_read_from_buffer(buf, count, ppos, einj_buf, strlen(einj_buf));
+}
+
+bool einj_is_cxl_error_type(u64 type)
+{
+	return (type & CXL_ERROR_MASK) && (!(type & ACPI5_VENDOR_BIT));
+}
+
+int einj_validate_error_type(u64 type)
+{
+	u32 tval, vendor;
+
+	/* Only low 32 bits for error type are valid */
+	if (type & GENMASK_ULL(63, 32))
+		return -EINVAL;
+
+	/*
+	 * Vendor defined types have 0x80000000 bit set, and
+	 * are not enumerated by ACPI_EINJ_GET_ERROR_TYPE
+	 */
+	vendor = type & ACPI5_VENDOR_BIT;
+	tval = type & GENMASK(30, 0);
+
+	/* Only one error type can be specified */
+	if (tval & (tval - 1))
+		return -EINVAL;
+	if (!vendor)
+		if (!(type & (available_error_type | available_error_type_v2)))
+			return -EINVAL;
+
+	return 0;
+}
+
+static ssize_t error_type_set(struct file *file, const char __user *buf,
+				size_t count, loff_t *ppos)
+{
+	int rc;
+	u64 val;
+
+	/* Leave the last character for the NUL terminator */
+	if (count > sizeof(einj_buf) - 1)
+		return -EINVAL;
+
+	memset(einj_buf, 0, sizeof(einj_buf));
+	if (copy_from_user(einj_buf, buf, count))
+		return -EFAULT;
+
+	if (strncmp(einj_buf, "V2_", 3) == 0) {
+		if (!sscanf(einj_buf, "V2_%llx", &val))
+			return -EINVAL;
+		is_v2 = true;
+	} else {
+		if (!sscanf(einj_buf, "%llx", &val))
+			return -EINVAL;
+		is_v2 = false;
+	}
+
+	rc = einj_validate_error_type(val);
+	if (rc)
+		return rc;
+
+	error_type = val;
+
+	return count;
+}
+
+static const struct file_operations error_type_fops = {
+	.read		= error_type_get,
+	.write		= error_type_set,
+};
+
+static int error_inject_set(void *data, u64 val)
+{
+	if (!error_type)
+		return -EINVAL;
+
+	if (is_v2)
+		error_flags |= SETWA_FLAGS_EINJV2;
+	else
+		error_flags &= ~SETWA_FLAGS_EINJV2;
+
+	return einj_error_inject(error_type, error_flags, error_param1, error_param2,
+		error_param3, error_param4);
+}
+
+DEFINE_DEBUGFS_ATTRIBUTE(error_inject_fops, NULL, error_inject_set, "%llu\n");
+
+static int einj_check_table(struct acpi_table_einj *einj_tab)
+{
+	if ((einj_tab->header_length !=
+	     (sizeof(struct acpi_table_einj) - sizeof(einj_tab->header)))
+	    && (einj_tab->header_length != sizeof(struct acpi_table_einj)))
+		return -EINVAL;
+	if (einj_tab->header.length < sizeof(struct acpi_table_einj))
+		return -EINVAL;
+	if (einj_tab->entries !=
+	    (einj_tab->header.length - sizeof(struct acpi_table_einj)) /
+	    sizeof(struct acpi_einj_entry))
+		return -EINVAL;
+
+	return 0;
+}
+
+static ssize_t u128_read(struct file *f, char __user *buf, size_t count, loff_t *off)
+{
+	char output[2 * COMPONENT_LEN + 1];
+	u8 *data = f->f_inode->i_private;
+	int i;
+
+	if (*off >= sizeof(output))
+		return 0;
+
+	for (i = 0; i < COMPONENT_LEN; i++)
+		sprintf(output + 2 * i, "%.02x", data[COMPONENT_LEN - i - 1]);
+	output[2 * COMPONENT_LEN] = '\n';
+
+	return simple_read_from_buffer(buf, count, off, output, sizeof(output));
+}
+
+static ssize_t u128_write(struct file *f, const char __user *buf, size_t count, loff_t *off)
+{
+	char input[2 + 2 * COMPONENT_LEN + 2];
+	u8 *save = f->f_inode->i_private;
+	u8 tmp[COMPONENT_LEN];
+	char byte[3] = {};
+	char *s, *e;
+	ssize_t c;
+	long val;
+	int i;
+
+	/* Require that user supply whole input line in one write(2) syscall */
+	if (*off)
+		return -EINVAL;
+
+	c = simple_write_to_buffer(input, sizeof(input), off, buf, count);
+	if (c < 0)
+		return c;
+
+	if (c < 1 || input[c - 1] != '\n')
+		return -EINVAL;
+
+	/* Empty line means invalidate this entry */
+	if (c == 1) {
+		memset(save, 0xff, COMPONENT_LEN);
+		return c;
+	}
+
+	if (input[0] == '0' && (input[1] == 'x' || input[1] == 'X'))
+		s = input + 2;
+	else
+		s = input;
+	e = input + c - 1;
+
+	for (i = 0; i < COMPONENT_LEN; i++) {
+		byte[1] = *--e;
+		byte[0] = e > s ? *--e : '0';
+		if (kstrtol(byte, 16, &val))
+			return -EINVAL;
+		tmp[i] = val;
+		if (e <= s)
+			break;
+	}
+	while (++i < COMPONENT_LEN)
+		tmp[i] = 0;
+
+	memcpy(save, tmp, COMPONENT_LEN);
+
+	return c;
+}
+
+static const struct file_operations u128_fops = {
+	.read	= u128_read,
+	.write	= u128_write,
+};
+
+static bool setup_einjv2_component_files(void)
+{
+	char name[32];
+
+	syndrome_data = kcalloc(max_nr_components, sizeof(syndrome_data[0]), GFP_KERNEL);
+	if (!syndrome_data)
+		return false;
+
+	for (int i = 0; i < max_nr_components; i++) {
+		sprintf(name, "component_id%d", i);
+		debugfs_create_file(name, 0600, einj_debug_dir,
+				    &syndrome_data[i].comp_id, &u128_fops);
+		sprintf(name, "component_syndrome%d", i);
+		debugfs_create_file(name, 0600, einj_debug_dir,
+				    &syndrome_data[i].comp_synd, &u128_fops);
+	}
+
+	return true;
+}
+
+static int __init einj_probe(struct faux_device *fdev)
+{
+	int rc;
+	acpi_status status;
+	struct apei_exec_context ctx;
+
+	status = acpi_get_table(ACPI_SIG_EINJ, 0,
+				(struct acpi_table_header **)&einj_tab);
+	if (status == AE_NOT_FOUND) {
+		pr_debug("EINJ table not found.\n");
+		return -ENODEV;
+	} else if (ACPI_FAILURE(status)) {
+		pr_err("Failed to get EINJ table: %s\n",
+				acpi_format_exception(status));
+		return -EINVAL;
+	}
+
+	rc = einj_check_table(einj_tab);
+	if (rc) {
+		pr_warn(FW_BUG "Invalid EINJ table.\n");
+		goto err_put_table;
+	}
+
+	rc = einj_get_available_error_types(&available_error_type, &available_error_type_v2);
+	if (rc)
+		goto err_put_table;
+
+	rc = -ENOMEM;
+	einj_debug_dir = debugfs_create_dir("einj", apei_get_debugfs_dir());
+
+	debugfs_create_file("available_error_type", S_IRUSR, einj_debug_dir,
+			    NULL, &available_error_type_fops);
+	debugfs_create_file_unsafe("error_type", 0600, einj_debug_dir,
+				   NULL, &error_type_fops);
+	debugfs_create_file_unsafe("error_inject", 0200, einj_debug_dir,
+				   NULL, &error_inject_fops);
+
+	apei_resources_init(&einj_resources);
+	einj_exec_ctx_init(&ctx);
+	rc = apei_exec_collect_resources(&ctx, &einj_resources);
+	if (rc) {
+		pr_err("Error collecting EINJ resources.\n");
+		goto err_fini;
+	}
+
+	rc = apei_resources_request(&einj_resources, "APEI EINJ");
+	if (rc) {
+		pr_err("Error requesting memory/port resources.\n");
+		goto err_fini;
+	}
+
+	rc = apei_exec_pre_map_gars(&ctx);
+	if (rc) {
+		pr_err("Error pre-mapping GARs.\n");
+		goto err_release;
+	}
+
+	einj_param = einj_get_parameter_address();
+	if ((param_extension || acpi5) && einj_param) {
+		debugfs_create_x32("flags", S_IRUSR | S_IWUSR, einj_debug_dir,
+				   &error_flags);
+		debugfs_create_x64("param1", S_IRUSR | S_IWUSR, einj_debug_dir,
+				   &error_param1);
+		debugfs_create_x64("param2", S_IRUSR | S_IWUSR, einj_debug_dir,
+				   &error_param2);
+		debugfs_create_x64("param3", S_IRUSR | S_IWUSR, einj_debug_dir,
+				   &error_param3);
+		debugfs_create_x64("param4", S_IRUSR | S_IWUSR, einj_debug_dir,
+				   &error_param4);
+		debugfs_create_x32("notrigger", S_IRUSR | S_IWUSR,
+				   einj_debug_dir, &notrigger);
+		if (available_error_type & ACPI65_EINJV2_SUPP)
+			einj_v2_enabled = setup_einjv2_component_files();
+	}
+
+	if (vendor_dev[0]) {
+		vendor_blob.data = vendor_dev;
+		vendor_blob.size = strlen(vendor_dev);
+		debugfs_create_blob("vendor", S_IRUSR, einj_debug_dir,
+				    &vendor_blob);
+		debugfs_create_x32("vendor_flags", S_IRUSR | S_IWUSR,
+				   einj_debug_dir, &vendor_flags);
+	}
+
+	if (vendor_errors.size)
+		debugfs_create_blob("oem_error", 0600, einj_debug_dir,
+				    &vendor_errors);
+
+	pr_info("Error INJection is initialized.\n");
+
+	return 0;
+
+err_release:
+	apei_resources_release(&einj_resources);
+err_fini:
+	apei_resources_fini(&einj_resources);
+	debugfs_remove_recursive(einj_debug_dir);
+err_put_table:
+	acpi_put_table((struct acpi_table_header *)einj_tab);
+
+	return rc;
+}
+
+static void einj_remove(struct faux_device *fdev)
+{
+	struct apei_exec_context ctx;
+
+	if (einj_param) {
+		acpi_size size;
+
+		if (v66param_size)
+			size = v66param_size;
+		else if (acpi5)
+			size = v5param_size;
+		else
+			size = sizeof(struct einj_parameter);
+
+		acpi_os_unmap_iomem(einj_param, size);
+		if (vendor_errors.size)
+			acpi_os_unmap_memory(vendor_errors.data, vendor_errors.size);
+	}
+	einj_exec_ctx_init(&ctx);
+	apei_exec_post_unmap_gars(&ctx);
+	apei_resources_release(&einj_resources);
+	apei_resources_fini(&einj_resources);
+	debugfs_remove_recursive(einj_debug_dir);
+	kfree(syndrome_data);
+	acpi_put_table((struct acpi_table_header *)einj_tab);
+}
+
+static struct faux_device *einj_dev;
+static struct faux_device_ops einj_device_ops = {
+	.probe = einj_probe,
+	.remove = einj_remove,
+};
+
+static int __init einj_init(void)
+{
+	if (acpi_disabled) {
+		pr_debug("ACPI disabled.\n");
+		return -ENODEV;
+	}
+
+	einj_dev = faux_device_create("acpi-einj", NULL, &einj_device_ops);
+
+	if (einj_dev)
+		einj_initialized = true;
+
+	return 0;
+}
+
+static void __exit einj_exit(void)
+{
+	faux_device_destroy(einj_dev);
+}
+
+module_init(einj_init);
+module_exit(einj_exit);
+
+MODULE_AUTHOR("Huang Ying");
+MODULE_DESCRIPTION("APEI Error INJection support");
+MODULE_LICENSE("GPL");
diff --git a/drivers/acpi/apei/einj-cxl.c b/drivers/acpi/apei/einj-cxl.c
new file mode 100644
index 000000000000..e70a416ec925
--- /dev/null
+++ b/drivers/acpi/apei/einj-cxl.c
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * CXL Error INJection support. Used by CXL core to inject
+ * protocol errors into CXL ports.
+ *
+ * Copyright (C) 2023 Advanced Micro Devices, Inc.
+ *
+ * Author: Ben Cheatham <benjamin.cheatham@amd.com>
+ */
+#include <linux/seq_file.h>
+#include <linux/pci.h>
+#include <cxl/einj.h>
+
+#include "apei-internal.h"
+
+/* Defined in einj-core.c */
+extern bool einj_initialized;
+
+static struct { u32 mask; const char *str; } const einj_cxl_error_type_string[] = {
+	{ ACPI_EINJ_CXL_CACHE_CORRECTABLE, "CXL.cache Protocol Correctable" },
+	{ ACPI_EINJ_CXL_CACHE_UNCORRECTABLE, "CXL.cache Protocol Uncorrectable non-fatal" },
+	{ ACPI_EINJ_CXL_CACHE_FATAL, "CXL.cache Protocol Uncorrectable fatal" },
+	{ ACPI_EINJ_CXL_MEM_CORRECTABLE, "CXL.mem Protocol Correctable" },
+	{ ACPI_EINJ_CXL_MEM_UNCORRECTABLE, "CXL.mem Protocol Uncorrectable non-fatal" },
+	{ ACPI_EINJ_CXL_MEM_FATAL, "CXL.mem Protocol Uncorrectable fatal" },
+};
+
+int einj_cxl_available_error_type_show(struct seq_file *m, void *v)
+{
+	int cxl_err, rc;
+	u32 available_error_type = 0;
+
+	rc = einj_get_available_error_type(&available_error_type, ACPI_EINJ_GET_ERROR_TYPE);
+	if (rc)
+		return rc;
+
+	for (int pos = 0; pos < ARRAY_SIZE(einj_cxl_error_type_string); pos++) {
+		cxl_err = ACPI_EINJ_CXL_CACHE_CORRECTABLE << pos;
+
+		if (available_error_type & cxl_err)
+			seq_printf(m, "0x%08x\t%s\n",
+				   einj_cxl_error_type_string[pos].mask,
+				   einj_cxl_error_type_string[pos].str);
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL_NS_GPL(einj_cxl_available_error_type_show, "CXL");
+
+static int cxl_dport_get_sbdf(struct pci_dev *dport_dev, u64 *sbdf)
+{
+	struct pci_bus *pbus;
+	struct pci_host_bridge *bridge;
+	u64 seg = 0, bus;
+
+	pbus = dport_dev->bus;
+	bridge = pci_find_host_bridge(pbus);
+
+	if (!bridge)
+		return -ENODEV;
+
+	if (bridge->domain_nr != PCI_DOMAIN_NR_NOT_SET)
+		seg = bridge->domain_nr;
+
+	bus = pbus->number;
+	*sbdf = (seg << 24) | (bus << 16) | (dport_dev->devfn << 8);
+
+	return 0;
+}
+
+int einj_cxl_inject_rch_error(u64 rcrb, u64 type)
+{
+	int rc;
+
+	/* Only CXL error types can be specified */
+	if (!einj_is_cxl_error_type(type))
+		return -EINVAL;
+
+	rc = einj_validate_error_type(type);
+	if (rc)
+		return rc;
+
+	return einj_cxl_rch_error_inject(type, 0x2, rcrb, GENMASK_ULL(63, 0),
+					 0, 0);
+}
+EXPORT_SYMBOL_NS_GPL(einj_cxl_inject_rch_error, "CXL");
+
+int einj_cxl_inject_error(struct pci_dev *dport, u64 type)
+{
+	u64 param4 = 0;
+	int rc;
+
+	/* Only CXL error types can be specified */
+	if (!einj_is_cxl_error_type(type))
+		return -EINVAL;
+
+	rc = einj_validate_error_type(type);
+	if (rc)
+		return rc;
+
+	rc = cxl_dport_get_sbdf(dport, &param4);
+	if (rc)
+		return rc;
+
+	return einj_error_inject(type, 0x4, 0, 0, 0, param4);
+}
+EXPORT_SYMBOL_NS_GPL(einj_cxl_inject_error, "CXL");
+
+bool einj_cxl_is_initialized(void)
+{
+	return einj_initialized;
+}
+EXPORT_SYMBOL_NS_GPL(einj_cxl_is_initialized, "CXL");
diff --git a/drivers/acpi/apei/einj.c b/drivers/acpi/apei/einj.c
deleted file mode 100644
index 086373f8ccb1..000000000000
--- a/drivers/acpi/apei/einj.c
+++ /dev/null
@@ -1,790 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * APEI Error INJection support
- *
- * EINJ provides a hardware error injection mechanism, this is useful
- * for debugging and testing of other APEI and RAS features.
- *
- * For more information about EINJ, please refer to ACPI Specification
- * version 4.0, section 17.5.
- *
- * Copyright 2009-2010 Intel Corp.
- *   Author: Huang Ying <ying.huang@intel.com>
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/debugfs.h>
-#include <linux/seq_file.h>
-#include <linux/nmi.h>
-#include <linux/delay.h>
-#include <linux/mm.h>
-#include <asm/unaligned.h>
-
-#include "apei-internal.h"
-
-#undef pr_fmt
-#define pr_fmt(fmt) "EINJ: " fmt
-
-#define SPIN_UNIT		100			/* 100ns */
-/* Firmware should respond within 1 milliseconds */
-#define FIRMWARE_TIMEOUT	(1 * NSEC_PER_MSEC)
-#define ACPI5_VENDOR_BIT	BIT(31)
-#define MEM_ERROR_MASK		(ACPI_EINJ_MEMORY_CORRECTABLE | \
-				ACPI_EINJ_MEMORY_UNCORRECTABLE | \
-				ACPI_EINJ_MEMORY_FATAL)
-
-/*
- * ACPI version 5 provides a SET_ERROR_TYPE_WITH_ADDRESS action.
- */
-static int acpi5;
-
-struct set_error_type_with_address {
-	u32	type;
-	u32	vendor_extension;
-	u32	flags;
-	u32	apicid;
-	u64	memory_address;
-	u64	memory_address_range;
-	u32	pcie_sbdf;
-};
-enum {
-	SETWA_FLAGS_APICID = 1,
-	SETWA_FLAGS_MEM = 2,
-	SETWA_FLAGS_PCIE_SBDF = 4,
-};
-
-/*
- * Vendor extensions for platform specific operations
- */
-struct vendor_error_type_extension {
-	u32	length;
-	u32	pcie_sbdf;
-	u16	vendor_id;
-	u16	device_id;
-	u8	rev_id;
-	u8	reserved[3];
-};
-
-static u32 notrigger;
-
-static u32 vendor_flags;
-static struct debugfs_blob_wrapper vendor_blob;
-static char vendor_dev[64];
-
-/*
- * Some BIOSes allow parameters to the SET_ERROR_TYPE entries in the
- * EINJ table through an unpublished extension. Use with caution as
- * most will ignore the parameter and make their own choice of address
- * for error injection.  This extension is used only if
- * param_extension module parameter is specified.
- */
-struct einj_parameter {
-	u64 type;
-	u64 reserved1;
-	u64 reserved2;
-	u64 param1;
-	u64 param2;
-};
-
-#define EINJ_OP_BUSY			0x1
-#define EINJ_STATUS_SUCCESS		0x0
-#define EINJ_STATUS_FAIL		0x1
-#define EINJ_STATUS_INVAL		0x2
-
-#define EINJ_TAB_ENTRY(tab)						\
-	((struct acpi_whea_header *)((char *)(tab) +			\
-				    sizeof(struct acpi_table_einj)))
-
-static bool param_extension;
-module_param(param_extension, bool, 0);
-
-static struct acpi_table_einj *einj_tab;
-
-static struct apei_resources einj_resources;
-
-static struct apei_exec_ins_type einj_ins_type[] = {
-	[ACPI_EINJ_READ_REGISTER] = {
-		.flags = APEI_EXEC_INS_ACCESS_REGISTER,
-		.run   = apei_exec_read_register,
-	},
-	[ACPI_EINJ_READ_REGISTER_VALUE] = {
-		.flags = APEI_EXEC_INS_ACCESS_REGISTER,
-		.run   = apei_exec_read_register_value,
-	},
-	[ACPI_EINJ_WRITE_REGISTER] = {
-		.flags = APEI_EXEC_INS_ACCESS_REGISTER,
-		.run   = apei_exec_write_register,
-	},
-	[ACPI_EINJ_WRITE_REGISTER_VALUE] = {
-		.flags = APEI_EXEC_INS_ACCESS_REGISTER,
-		.run   = apei_exec_write_register_value,
-	},
-	[ACPI_EINJ_NOOP] = {
-		.flags = 0,
-		.run   = apei_exec_noop,
-	},
-};
-
-/*
- * Prevent EINJ interpreter to run simultaneously, because the
- * corresponding firmware implementation may not work properly when
- * invoked simultaneously.
- */
-static DEFINE_MUTEX(einj_mutex);
-
-static void *einj_param;
-
-static void einj_exec_ctx_init(struct apei_exec_context *ctx)
-{
-	apei_exec_ctx_init(ctx, einj_ins_type, ARRAY_SIZE(einj_ins_type),
-			   EINJ_TAB_ENTRY(einj_tab), einj_tab->entries);
-}
-
-static int __einj_get_available_error_type(u32 *type)
-{
-	struct apei_exec_context ctx;
-	int rc;
-
-	einj_exec_ctx_init(&ctx);
-	rc = apei_exec_run(&ctx, ACPI_EINJ_GET_ERROR_TYPE);
-	if (rc)
-		return rc;
-	*type = apei_exec_ctx_get_output(&ctx);
-
-	return 0;
-}
-
-/* Get error injection capabilities of the platform */
-static int einj_get_available_error_type(u32 *type)
-{
-	int rc;
-
-	mutex_lock(&einj_mutex);
-	rc = __einj_get_available_error_type(type);
-	mutex_unlock(&einj_mutex);
-
-	return rc;
-}
-
-static int einj_timedout(u64 *t)
-{
-	if ((s64)*t < SPIN_UNIT) {
-		pr_warn(FW_WARN "Firmware does not respond in time\n");
-		return 1;
-	}
-	*t -= SPIN_UNIT;
-	ndelay(SPIN_UNIT);
-	touch_nmi_watchdog();
-	return 0;
-}
-
-static void check_vendor_extension(u64 paddr,
-				   struct set_error_type_with_address *v5param)
-{
-	int	offset = v5param->vendor_extension;
-	struct	vendor_error_type_extension *v;
-	u32	sbdf;
-
-	if (!offset)
-		return;
-	v = acpi_os_map_iomem(paddr + offset, sizeof(*v));
-	if (!v)
-		return;
-	sbdf = v->pcie_sbdf;
-	sprintf(vendor_dev, "%x:%x:%x.%x vendor_id=%x device_id=%x rev_id=%x\n",
-		sbdf >> 24, (sbdf >> 16) & 0xff,
-		(sbdf >> 11) & 0x1f, (sbdf >> 8) & 0x7,
-		 v->vendor_id, v->device_id, v->rev_id);
-	acpi_os_unmap_iomem(v, sizeof(*v));
-}
-
-static void *einj_get_parameter_address(void)
-{
-	int i;
-	u64 pa_v4 = 0, pa_v5 = 0;
-	struct acpi_whea_header *entry;
-
-	entry = EINJ_TAB_ENTRY(einj_tab);
-	for (i = 0; i < einj_tab->entries; i++) {
-		if (entry->action == ACPI_EINJ_SET_ERROR_TYPE &&
-		    entry->instruction == ACPI_EINJ_WRITE_REGISTER &&
-		    entry->register_region.space_id ==
-		    ACPI_ADR_SPACE_SYSTEM_MEMORY)
-			pa_v4 = get_unaligned(&entry->register_region.address);
-		if (entry->action == ACPI_EINJ_SET_ERROR_TYPE_WITH_ADDRESS &&
-		    entry->instruction == ACPI_EINJ_WRITE_REGISTER &&
-		    entry->register_region.space_id ==
-		    ACPI_ADR_SPACE_SYSTEM_MEMORY)
-			pa_v5 = get_unaligned(&entry->register_region.address);
-		entry++;
-	}
-	if (pa_v5) {
-		struct set_error_type_with_address *v5param;
-
-		v5param = acpi_os_map_iomem(pa_v5, sizeof(*v5param));
-		if (v5param) {
-			acpi5 = 1;
-			check_vendor_extension(pa_v5, v5param);
-			return v5param;
-		}
-	}
-	if (param_extension && pa_v4) {
-		struct einj_parameter *v4param;
-
-		v4param = acpi_os_map_iomem(pa_v4, sizeof(*v4param));
-		if (!v4param)
-			return NULL;
-		if (v4param->reserved1 || v4param->reserved2) {
-			acpi_os_unmap_iomem(v4param, sizeof(*v4param));
-			return NULL;
-		}
-		return v4param;
-	}
-
-	return NULL;
-}
-
-/* do sanity check to trigger table */
-static int einj_check_trigger_header(struct acpi_einj_trigger *trigger_tab)
-{
-	if (trigger_tab->header_size != sizeof(struct acpi_einj_trigger))
-		return -EINVAL;
-	if (trigger_tab->table_size > PAGE_SIZE ||
-	    trigger_tab->table_size < trigger_tab->header_size)
-		return -EINVAL;
-	if (trigger_tab->entry_count !=
-	    (trigger_tab->table_size - trigger_tab->header_size) /
-	    sizeof(struct acpi_einj_entry))
-		return -EINVAL;
-
-	return 0;
-}
-
-static struct acpi_generic_address *einj_get_trigger_parameter_region(
-	struct acpi_einj_trigger *trigger_tab, u64 param1, u64 param2)
-{
-	int i;
-	struct acpi_whea_header *entry;
-
-	entry = (struct acpi_whea_header *)
-		((char *)trigger_tab + sizeof(struct acpi_einj_trigger));
-	for (i = 0; i < trigger_tab->entry_count; i++) {
-		if (entry->action == ACPI_EINJ_TRIGGER_ERROR &&
-		entry->instruction <= ACPI_EINJ_WRITE_REGISTER_VALUE &&
-		entry->register_region.space_id ==
-			ACPI_ADR_SPACE_SYSTEM_MEMORY &&
-		(entry->register_region.address & param2) == (param1 & param2))
-			return &entry->register_region;
-		entry++;
-	}
-
-	return NULL;
-}
-/* Execute instructions in trigger error action table */
-static int __einj_error_trigger(u64 trigger_paddr, u32 type,
-				u64 param1, u64 param2)
-{
-	struct acpi_einj_trigger *trigger_tab = NULL;
-	struct apei_exec_context trigger_ctx;
-	struct apei_resources trigger_resources;
-	struct acpi_whea_header *trigger_entry;
-	struct resource *r;
-	u32 table_size;
-	int rc = -EIO;
-	struct acpi_generic_address *trigger_param_region = NULL;
-
-	r = request_mem_region(trigger_paddr, sizeof(*trigger_tab),
-			       "APEI EINJ Trigger Table");
-	if (!r) {
-		pr_err("Can not request [mem %#010llx-%#010llx] for Trigger table\n",
-		       (unsigned long long)trigger_paddr,
-		       (unsigned long long)trigger_paddr +
-			    sizeof(*trigger_tab) - 1);
-		goto out;
-	}
-	trigger_tab = ioremap_cache(trigger_paddr, sizeof(*trigger_tab));
-	if (!trigger_tab) {
-		pr_err("Failed to map trigger table!\n");
-		goto out_rel_header;
-	}
-	rc = einj_check_trigger_header(trigger_tab);
-	if (rc) {
-		pr_warn(FW_BUG "Invalid trigger error action table.\n");
-		goto out_rel_header;
-	}
-
-	/* No action structures in the TRIGGER_ERROR table, nothing to do */
-	if (!trigger_tab->entry_count)
-		goto out_rel_header;
-
-	rc = -EIO;
-	table_size = trigger_tab->table_size;
-	r = request_mem_region(trigger_paddr + sizeof(*trigger_tab),
-			       table_size - sizeof(*trigger_tab),
-			       "APEI EINJ Trigger Table");
-	if (!r) {
-		pr_err("Can not request [mem %#010llx-%#010llx] for Trigger Table Entry\n",
-		       (unsigned long long)trigger_paddr + sizeof(*trigger_tab),
-		       (unsigned long long)trigger_paddr + table_size - 1);
-		goto out_rel_header;
-	}
-	iounmap(trigger_tab);
-	trigger_tab = ioremap_cache(trigger_paddr, table_size);
-	if (!trigger_tab) {
-		pr_err("Failed to map trigger table!\n");
-		goto out_rel_entry;
-	}
-	trigger_entry = (struct acpi_whea_header *)
-		((char *)trigger_tab + sizeof(struct acpi_einj_trigger));
-	apei_resources_init(&trigger_resources);
-	apei_exec_ctx_init(&trigger_ctx, einj_ins_type,
-			   ARRAY_SIZE(einj_ins_type),
-			   trigger_entry, trigger_tab->entry_count);
-	rc = apei_exec_collect_resources(&trigger_ctx, &trigger_resources);
-	if (rc)
-		goto out_fini;
-	rc = apei_resources_sub(&trigger_resources, &einj_resources);
-	if (rc)
-		goto out_fini;
-	/*
-	 * Some firmware will access target address specified in
-	 * param1 to trigger the error when injecting memory error.
-	 * This will cause resource conflict with regular memory.  So
-	 * remove it from trigger table resources.
-	 */
-	if ((param_extension || acpi5) && (type & MEM_ERROR_MASK) && param2) {
-		struct apei_resources addr_resources;
-		apei_resources_init(&addr_resources);
-		trigger_param_region = einj_get_trigger_parameter_region(
-			trigger_tab, param1, param2);
-		if (trigger_param_region) {
-			rc = apei_resources_add(&addr_resources,
-				trigger_param_region->address,
-				trigger_param_region->bit_width/8, true);
-			if (rc)
-				goto out_fini;
-			rc = apei_resources_sub(&trigger_resources,
-					&addr_resources);
-		}
-		apei_resources_fini(&addr_resources);
-		if (rc)
-			goto out_fini;
-	}
-	rc = apei_resources_request(&trigger_resources, "APEI EINJ Trigger");
-	if (rc)
-		goto out_fini;
-	rc = apei_exec_pre_map_gars(&trigger_ctx);
-	if (rc)
-		goto out_release;
-
-	rc = apei_exec_run(&trigger_ctx, ACPI_EINJ_TRIGGER_ERROR);
-
-	apei_exec_post_unmap_gars(&trigger_ctx);
-out_release:
-	apei_resources_release(&trigger_resources);
-out_fini:
-	apei_resources_fini(&trigger_resources);
-out_rel_entry:
-	release_mem_region(trigger_paddr + sizeof(*trigger_tab),
-			   table_size - sizeof(*trigger_tab));
-out_rel_header:
-	release_mem_region(trigger_paddr, sizeof(*trigger_tab));
-out:
-	if (trigger_tab)
-		iounmap(trigger_tab);
-
-	return rc;
-}
-
-static int __einj_error_inject(u32 type, u32 flags, u64 param1, u64 param2,
-			       u64 param3, u64 param4)
-{
-	struct apei_exec_context ctx;
-	u64 val, trigger_paddr, timeout = FIRMWARE_TIMEOUT;
-	int rc;
-
-	einj_exec_ctx_init(&ctx);
-
-	rc = apei_exec_run_optional(&ctx, ACPI_EINJ_BEGIN_OPERATION);
-	if (rc)
-		return rc;
-	apei_exec_ctx_set_input(&ctx, type);
-	if (acpi5) {
-		struct set_error_type_with_address *v5param = einj_param;
-
-		v5param->type = type;
-		if (type & ACPI5_VENDOR_BIT) {
-			switch (vendor_flags) {
-			case SETWA_FLAGS_APICID:
-				v5param->apicid = param1;
-				break;
-			case SETWA_FLAGS_MEM:
-				v5param->memory_address = param1;
-				v5param->memory_address_range = param2;
-				break;
-			case SETWA_FLAGS_PCIE_SBDF:
-				v5param->pcie_sbdf = param1;
-				break;
-			}
-			v5param->flags = vendor_flags;
-		} else if (flags) {
-				v5param->flags = flags;
-				v5param->memory_address = param1;
-				v5param->memory_address_range = param2;
-				v5param->apicid = param3;
-				v5param->pcie_sbdf = param4;
-		} else {
-			switch (type) {
-			case ACPI_EINJ_PROCESSOR_CORRECTABLE:
-			case ACPI_EINJ_PROCESSOR_UNCORRECTABLE:
-			case ACPI_EINJ_PROCESSOR_FATAL:
-				v5param->apicid = param1;
-				v5param->flags = SETWA_FLAGS_APICID;
-				break;
-			case ACPI_EINJ_MEMORY_CORRECTABLE:
-			case ACPI_EINJ_MEMORY_UNCORRECTABLE:
-			case ACPI_EINJ_MEMORY_FATAL:
-				v5param->memory_address = param1;
-				v5param->memory_address_range = param2;
-				v5param->flags = SETWA_FLAGS_MEM;
-				break;
-			case ACPI_EINJ_PCIX_CORRECTABLE:
-			case ACPI_EINJ_PCIX_UNCORRECTABLE:
-			case ACPI_EINJ_PCIX_FATAL:
-				v5param->pcie_sbdf = param1;
-				v5param->flags = SETWA_FLAGS_PCIE_SBDF;
-				break;
-			}
-		}
-	} else {
-		rc = apei_exec_run(&ctx, ACPI_EINJ_SET_ERROR_TYPE);
-		if (rc)
-			return rc;
-		if (einj_param) {
-			struct einj_parameter *v4param = einj_param;
-			v4param->param1 = param1;
-			v4param->param2 = param2;
-		}
-	}
-	rc = apei_exec_run(&ctx, ACPI_EINJ_EXECUTE_OPERATION);
-	if (rc)
-		return rc;
-	for (;;) {
-		rc = apei_exec_run(&ctx, ACPI_EINJ_CHECK_BUSY_STATUS);
-		if (rc)
-			return rc;
-		val = apei_exec_ctx_get_output(&ctx);
-		if (!(val & EINJ_OP_BUSY))
-			break;
-		if (einj_timedout(&timeout))
-			return -EIO;
-	}
-	rc = apei_exec_run(&ctx, ACPI_EINJ_GET_COMMAND_STATUS);
-	if (rc)
-		return rc;
-	val = apei_exec_ctx_get_output(&ctx);
-	if (val != EINJ_STATUS_SUCCESS)
-		return -EBUSY;
-
-	rc = apei_exec_run(&ctx, ACPI_EINJ_GET_TRIGGER_TABLE);
-	if (rc)
-		return rc;
-	trigger_paddr = apei_exec_ctx_get_output(&ctx);
-	if (notrigger == 0) {
-		rc = __einj_error_trigger(trigger_paddr, type, param1, param2);
-		if (rc)
-			return rc;
-	}
-	rc = apei_exec_run_optional(&ctx, ACPI_EINJ_END_OPERATION);
-
-	return rc;
-}
-
-/* Inject the specified hardware error */
-static int einj_error_inject(u32 type, u32 flags, u64 param1, u64 param2,
-			     u64 param3, u64 param4)
-{
-	int rc;
-	u64 base_addr, size;
-
-	/* If user manually set "flags", make sure it is legal */
-	if (flags && (flags &
-		~(SETWA_FLAGS_APICID|SETWA_FLAGS_MEM|SETWA_FLAGS_PCIE_SBDF)))
-		return -EINVAL;
-
-	/*
-	 * We need extra sanity checks for memory errors.
-	 * Other types leap directly to injection.
-	 */
-
-	/* ensure param1/param2 existed */
-	if (!(param_extension || acpi5))
-		goto inject;
-
-	/* ensure injection is memory related */
-	if (type & ACPI5_VENDOR_BIT) {
-		if (vendor_flags != SETWA_FLAGS_MEM)
-			goto inject;
-	} else if (!(type & MEM_ERROR_MASK) && !(flags & SETWA_FLAGS_MEM))
-		goto inject;
-
-	/*
-	 * Disallow crazy address masks that give BIOS leeway to pick
-	 * injection address almost anywhere. Insist on page or
-	 * better granularity and that target address is normal RAM or
-	 * NVDIMM.
-	 */
-	base_addr = param1 & param2;
-	size = ~param2 + 1;
-
-	if (((param2 & PAGE_MASK) != PAGE_MASK) ||
-	    ((region_intersects(base_addr, size, IORESOURCE_SYSTEM_RAM, IORES_DESC_NONE)
-				!= REGION_INTERSECTS) &&
-	     (region_intersects(base_addr, size, IORESOURCE_MEM, IORES_DESC_PERSISTENT_MEMORY)
-				!= REGION_INTERSECTS)))
-		return -EINVAL;
-
-inject:
-	mutex_lock(&einj_mutex);
-	rc = __einj_error_inject(type, flags, param1, param2, param3, param4);
-	mutex_unlock(&einj_mutex);
-
-	return rc;
-}
-
-static u32 error_type;
-static u32 error_flags;
-static u64 error_param1;
-static u64 error_param2;
-static u64 error_param3;
-static u64 error_param4;
-static struct dentry *einj_debug_dir;
-
-static int available_error_type_show(struct seq_file *m, void *v)
-{
-	int rc;
-	u32 available_error_type = 0;
-
-	rc = einj_get_available_error_type(&available_error_type);
-	if (rc)
-		return rc;
-	if (available_error_type & 0x0001)
-		seq_printf(m, "0x00000001\tProcessor Correctable\n");
-	if (available_error_type & 0x0002)
-		seq_printf(m, "0x00000002\tProcessor Uncorrectable non-fatal\n");
-	if (available_error_type & 0x0004)
-		seq_printf(m, "0x00000004\tProcessor Uncorrectable fatal\n");
-	if (available_error_type & 0x0008)
-		seq_printf(m, "0x00000008\tMemory Correctable\n");
-	if (available_error_type & 0x0010)
-		seq_printf(m, "0x00000010\tMemory Uncorrectable non-fatal\n");
-	if (available_error_type & 0x0020)
-		seq_printf(m, "0x00000020\tMemory Uncorrectable fatal\n");
-	if (available_error_type & 0x0040)
-		seq_printf(m, "0x00000040\tPCI Express Correctable\n");
-	if (available_error_type & 0x0080)
-		seq_printf(m, "0x00000080\tPCI Express Uncorrectable non-fatal\n");
-	if (available_error_type & 0x0100)
-		seq_printf(m, "0x00000100\tPCI Express Uncorrectable fatal\n");
-	if (available_error_type & 0x0200)
-		seq_printf(m, "0x00000200\tPlatform Correctable\n");
-	if (available_error_type & 0x0400)
-		seq_printf(m, "0x00000400\tPlatform Uncorrectable non-fatal\n");
-	if (available_error_type & 0x0800)
-		seq_printf(m, "0x00000800\tPlatform Uncorrectable fatal\n");
-
-	return 0;
-}
-
-DEFINE_SHOW_ATTRIBUTE(available_error_type);
-
-static int error_type_get(void *data, u64 *val)
-{
-	*val = error_type;
-
-	return 0;
-}
-
-static int error_type_set(void *data, u64 val)
-{
-	int rc;
-	u32 available_error_type = 0;
-	u32 tval, vendor;
-
-	/*
-	 * Vendor defined types have 0x80000000 bit set, and
-	 * are not enumerated by ACPI_EINJ_GET_ERROR_TYPE
-	 */
-	vendor = val & ACPI5_VENDOR_BIT;
-	tval = val & 0x7fffffff;
-
-	/* Only one error type can be specified */
-	if (tval & (tval - 1))
-		return -EINVAL;
-	if (!vendor) {
-		rc = einj_get_available_error_type(&available_error_type);
-		if (rc)
-			return rc;
-		if (!(val & available_error_type))
-			return -EINVAL;
-	}
-	error_type = val;
-
-	return 0;
-}
-
-DEFINE_DEBUGFS_ATTRIBUTE(error_type_fops, error_type_get, error_type_set,
-			 "0x%llx\n");
-
-static int error_inject_set(void *data, u64 val)
-{
-	if (!error_type)
-		return -EINVAL;
-
-	return einj_error_inject(error_type, error_flags, error_param1, error_param2,
-		error_param3, error_param4);
-}
-
-DEFINE_DEBUGFS_ATTRIBUTE(error_inject_fops, NULL, error_inject_set, "%llu\n");
-
-static int einj_check_table(struct acpi_table_einj *einj_tab)
-{
-	if ((einj_tab->header_length !=
-	     (sizeof(struct acpi_table_einj) - sizeof(einj_tab->header)))
-	    && (einj_tab->header_length != sizeof(struct acpi_table_einj)))
-		return -EINVAL;
-	if (einj_tab->header.length < sizeof(struct acpi_table_einj))
-		return -EINVAL;
-	if (einj_tab->entries !=
-	    (einj_tab->header.length - sizeof(struct acpi_table_einj)) /
-	    sizeof(struct acpi_einj_entry))
-		return -EINVAL;
-
-	return 0;
-}
-
-static int __init einj_init(void)
-{
-	int rc;
-	acpi_status status;
-	struct apei_exec_context ctx;
-
-	if (acpi_disabled) {
-		pr_warn("ACPI disabled.\n");
-		return -ENODEV;
-	}
-
-	status = acpi_get_table(ACPI_SIG_EINJ, 0,
-				(struct acpi_table_header **)&einj_tab);
-	if (status == AE_NOT_FOUND) {
-		pr_warn("EINJ table not found.\n");
-		return -ENODEV;
-	}
-	else if (ACPI_FAILURE(status)) {
-		pr_err("Failed to get EINJ table: %s\n",
-				acpi_format_exception(status));
-		return -EINVAL;
-	}
-
-	rc = einj_check_table(einj_tab);
-	if (rc) {
-		pr_warn(FW_BUG "Invalid EINJ table.\n");
-		return -EINVAL;
-	}
-
-	rc = -ENOMEM;
-	einj_debug_dir = debugfs_create_dir("einj", apei_get_debugfs_dir());
-
-	debugfs_create_file("available_error_type", S_IRUSR, einj_debug_dir,
-			    NULL, &available_error_type_fops);
-	debugfs_create_file_unsafe("error_type", 0600, einj_debug_dir,
-				   NULL, &error_type_fops);
-	debugfs_create_file_unsafe("error_inject", 0200, einj_debug_dir,
-				   NULL, &error_inject_fops);
-
-	apei_resources_init(&einj_resources);
-	einj_exec_ctx_init(&ctx);
-	rc = apei_exec_collect_resources(&ctx, &einj_resources);
-	if (rc) {
-		pr_err("Error collecting EINJ resources.\n");
-		goto err_fini;
-	}
-
-	rc = apei_resources_request(&einj_resources, "APEI EINJ");
-	if (rc) {
-		pr_err("Error requesting memory/port resources.\n");
-		goto err_fini;
-	}
-
-	rc = apei_exec_pre_map_gars(&ctx);
-	if (rc) {
-		pr_err("Error pre-mapping GARs.\n");
-		goto err_release;
-	}
-
-	rc = -ENOMEM;
-	einj_param = einj_get_parameter_address();
-	if ((param_extension || acpi5) && einj_param) {
-		debugfs_create_x32("flags", S_IRUSR | S_IWUSR, einj_debug_dir,
-				   &error_flags);
-		debugfs_create_x64("param1", S_IRUSR | S_IWUSR, einj_debug_dir,
-				   &error_param1);
-		debugfs_create_x64("param2", S_IRUSR | S_IWUSR, einj_debug_dir,
-				   &error_param2);
-		debugfs_create_x64("param3", S_IRUSR | S_IWUSR, einj_debug_dir,
-				   &error_param3);
-		debugfs_create_x64("param4", S_IRUSR | S_IWUSR, einj_debug_dir,
-				   &error_param4);
-		debugfs_create_x32("notrigger", S_IRUSR | S_IWUSR,
-				   einj_debug_dir, &notrigger);
-	}
-
-	if (vendor_dev[0]) {
-		vendor_blob.data = vendor_dev;
-		vendor_blob.size = strlen(vendor_dev);
-		debugfs_create_blob("vendor", S_IRUSR, einj_debug_dir,
-				    &vendor_blob);
-		debugfs_create_x32("vendor_flags", S_IRUSR | S_IWUSR,
-				   einj_debug_dir, &vendor_flags);
-	}
-
-	pr_info("Error INJection is initialized.\n");
-
-	return 0;
-
-err_release:
-	apei_resources_release(&einj_resources);
-err_fini:
-	apei_resources_fini(&einj_resources);
-	debugfs_remove_recursive(einj_debug_dir);
-
-	return rc;
-}
-
-static void __exit einj_exit(void)
-{
-	struct apei_exec_context ctx;
-
-	if (einj_param) {
-		acpi_size size = (acpi5) ?
-			sizeof(struct set_error_type_with_address) :
-			sizeof(struct einj_parameter);
-
-		acpi_os_unmap_iomem(einj_param, size);
-	}
-	einj_exec_ctx_init(&ctx);
-	apei_exec_post_unmap_gars(&ctx);
-	apei_resources_release(&einj_resources);
-	apei_resources_fini(&einj_resources);
-	debugfs_remove_recursive(einj_debug_dir);
-}
-
-module_init(einj_init);
-module_exit(einj_exit);
-
-MODULE_AUTHOR("Huang Ying");
-MODULE_DESCRIPTION("APEI Error INJection support");
-MODULE_LICENSE("GPL");
diff --git a/drivers/acpi/apei/erst-dbg.c b/drivers/acpi/apei/erst-dbg.c
index c740f0faad39..ff0e8bf8e97a 100644
--- a/drivers/acpi/apei/erst-dbg.c
+++ b/drivers/acpi/apei/erst-dbg.c
@@ -60,9 +60,8 @@ static long erst_dbg_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
 
 	switch (cmd) {
 	case APEI_ERST_CLEAR_RECORD:
-		rc = copy_from_user(&record_id, (void __user *)arg,
-				    sizeof(record_id));
-		if (rc)
+		if (copy_from_user(&record_id, (void __user *)arg,
+				   sizeof(record_id)))
 			return -EFAULT;
 		return erst_clear(record_id);
 	case APEI_ERST_GET_RECORD_COUNT:
@@ -111,7 +110,8 @@ retry_next:
 		goto out;
 	}
 retry:
-	rc = len = erst_read(id, erst_dbg_buf, erst_dbg_buf_len);
+	rc = len = erst_read_record(id, erst_dbg_buf, erst_dbg_buf_len,
+			erst_dbg_buf_len, NULL);
 	/* The record may be cleared by others, try read next record */
 	if (rc == -ENOENT)
 		goto retry_next;
@@ -174,8 +174,7 @@ static ssize_t erst_dbg_write(struct file *filp, const char __user *ubuf,
 		erst_dbg_buf = p;
 		erst_dbg_buf_len = usize;
 	}
-	rc = copy_from_user(erst_dbg_buf, ubuf, usize);
-	if (rc) {
+	if (copy_from_user(erst_dbg_buf, ubuf, usize)) {
 		rc = -EFAULT;
 		goto out;
 	}
@@ -198,7 +197,6 @@ static const struct file_operations erst_dbg_ops = {
 	.read		= erst_dbg_read,
 	.write		= erst_dbg_write,
 	.unlocked_ioctl	= erst_dbg_ioctl,
-	.llseek		= no_llseek,
 };
 
 static struct miscdevice erst_dbg_dev = {
diff --git a/drivers/acpi/apei/erst.c b/drivers/acpi/apei/erst.c
index 2015a0967cbb..bf65e3461531 100644
--- a/drivers/acpi/apei/erst.c
+++ b/drivers/acpi/apei/erst.c
@@ -54,11 +54,15 @@ EXPORT_SYMBOL_GPL(erst_disable);
 
 static struct acpi_table_erst *erst_tab;
 
-/* ERST Error Log Address Range atrributes */
+/* ERST Error Log Address Range attributes */
 #define ERST_RANGE_RESERVED	0x0001
 #define ERST_RANGE_NVRAM	0x0002
 #define ERST_RANGE_SLOW		0x0004
 
+/* ERST Exec max timings */
+#define ERST_EXEC_TIMING_MAX_MASK      0xFFFFFFFF00000000
+#define ERST_EXEC_TIMING_MAX_SHIFT     32
+
 /*
  * ERST Error Log Address Range, used as buffer for reading/writing
  * error records.
@@ -68,6 +72,7 @@ static struct erst_erange {
 	u64 size;
 	void __iomem *vaddr;
 	u32 attr;
+	u64 timings;
 } erst_erange;
 
 /*
@@ -97,6 +102,19 @@ static inline int erst_errno(int command_status)
 	}
 }
 
+static inline u64 erst_get_timeout(void)
+{
+	u64 timeout = FIRMWARE_TIMEOUT;
+
+	if (erst_erange.attr & ERST_RANGE_SLOW) {
+		timeout = ((erst_erange.timings & ERST_EXEC_TIMING_MAX_MASK) >>
+			ERST_EXEC_TIMING_MAX_SHIFT) * NSEC_PER_MSEC;
+		if (timeout < FIRMWARE_TIMEOUT)
+			timeout = FIRMWARE_TIMEOUT;
+	}
+	return timeout;
+}
+
 static int erst_timedout(u64 *t, u64 spin_unit)
 {
 	if ((s64)*t < spin_unit) {
@@ -191,9 +209,11 @@ static int erst_exec_stall_while_true(struct apei_exec_context *ctx,
 {
 	int rc;
 	u64 val;
-	u64 timeout = FIRMWARE_TIMEOUT;
+	u64 timeout;
 	u64 stall_time;
 
+	timeout = erst_get_timeout();
+
 	if (ctx->var1 > FIRMWARE_MAX_STALL) {
 		if (!in_nmi())
 			pr_warn(FW_WARN
@@ -389,6 +409,13 @@ static int erst_get_erange(struct erst_erange *range)
 	if (rc)
 		return rc;
 	range->attr = apei_exec_ctx_get_output(&ctx);
+	rc = apei_exec_run(&ctx, ACPI_ERST_EXECUTE_TIMINGS);
+	if (rc == 0)
+		range->timings = apei_exec_ctx_get_output(&ctx);
+	else if (rc == -ENOENT)
+		range->timings = 0;
+	else
+		return rc;
 
 	return 0;
 }
@@ -621,10 +648,12 @@ EXPORT_SYMBOL_GPL(erst_get_record_id_end);
 static int __erst_write_to_storage(u64 offset)
 {
 	struct apei_exec_context ctx;
-	u64 timeout = FIRMWARE_TIMEOUT;
+	u64 timeout;
 	u64 val;
 	int rc;
 
+	timeout = erst_get_timeout();
+
 	erst_exec_ctx_init(&ctx);
 	rc = apei_exec_run_optional(&ctx, ACPI_ERST_BEGIN_WRITE);
 	if (rc)
@@ -660,10 +689,12 @@ static int __erst_write_to_storage(u64 offset)
 static int __erst_read_from_storage(u64 record_id, u64 offset)
 {
 	struct apei_exec_context ctx;
-	u64 timeout = FIRMWARE_TIMEOUT;
+	u64 timeout;
 	u64 val;
 	int rc;
 
+	timeout = erst_get_timeout();
+
 	erst_exec_ctx_init(&ctx);
 	rc = apei_exec_run_optional(&ctx, ACPI_ERST_BEGIN_READ);
 	if (rc)
@@ -688,7 +719,7 @@ static int __erst_read_from_storage(u64 record_id, u64 offset)
 			break;
 		if (erst_timedout(&timeout, SPIN_UNIT))
 			return -EIO;
-	};
+	}
 	rc = apei_exec_run(&ctx, ACPI_ERST_GET_COMMAND_STATUS);
 	if (rc)
 		return rc;
@@ -703,10 +734,12 @@ static int __erst_read_from_storage(u64 record_id, u64 offset)
 static int __erst_clear_from_storage(u64 record_id)
 {
 	struct apei_exec_context ctx;
-	u64 timeout = FIRMWARE_TIMEOUT;
+	u64 timeout;
 	u64 val;
 	int rc;
 
+	timeout = erst_get_timeout();
+
 	erst_exec_ctx_init(&ctx);
 	rc = apei_exec_run_optional(&ctx, ACPI_ERST_BEGIN_CLEAR);
 	if (rc)
@@ -856,6 +889,74 @@ ssize_t erst_read(u64 record_id, struct cper_record_header *record,
 }
 EXPORT_SYMBOL_GPL(erst_read);
 
+static void erst_clear_cache(u64 record_id)
+{
+	int i;
+	u64 *entries;
+
+	mutex_lock(&erst_record_id_cache.lock);
+
+	entries = erst_record_id_cache.entries;
+	for (i = 0; i < erst_record_id_cache.len; i++) {
+		if (entries[i] == record_id)
+			entries[i] = APEI_ERST_INVALID_RECORD_ID;
+	}
+	__erst_record_id_cache_compact();
+
+	mutex_unlock(&erst_record_id_cache.lock);
+}
+
+ssize_t erst_read_record(u64 record_id, struct cper_record_header *record,
+		size_t buflen, size_t recordlen, const guid_t *creatorid)
+{
+	ssize_t len;
+
+	/*
+	 * if creatorid is NULL, read any record for erst-dbg module
+	 */
+	if (creatorid == NULL) {
+		len = erst_read(record_id, record, buflen);
+		if (len == -ENOENT)
+			erst_clear_cache(record_id);
+
+		return len;
+	}
+
+	len = erst_read(record_id, record, buflen);
+	/*
+	 * if erst_read return value is -ENOENT skip to next record_id,
+	 * and clear the record_id cache.
+	 */
+	if (len == -ENOENT) {
+		erst_clear_cache(record_id);
+		goto out;
+	}
+
+	if (len < 0)
+		goto out;
+
+	/*
+	 * if erst_read return value is less than record head length,
+	 * consider it as -EIO, and clear the record_id cache.
+	 */
+	if (len < recordlen) {
+		len = -EIO;
+		erst_clear_cache(record_id);
+		goto out;
+	}
+
+	/*
+	 * if creatorid is not wanted, consider it as not found,
+	 * for skipping to next record_id.
+	 */
+	if (!guid_equal(&record->creator_id, creatorid))
+		len = -ENOENT;
+
+out:
+	return len;
+}
+EXPORT_SYMBOL_GPL(erst_read_record);
+
 int erst_clear(u64 record_id)
 {
 	int rc, i;
@@ -891,7 +992,7 @@ EXPORT_SYMBOL_GPL(erst_clear);
 static int __init setup_erst_disable(char *str)
 {
 	erst_disable = 1;
-	return 0;
+	return 1;
 }
 
 __setup("erst_disable", setup_erst_disable);
@@ -952,14 +1053,10 @@ static int reader_pos;
 
 static int erst_open_pstore(struct pstore_info *psi)
 {
-	int rc;
-
 	if (erst_disable)
 		return -ENODEV;
 
-	rc = erst_get_record_id_begin(&reader_pos);
-
-	return rc;
+	return erst_get_record_id_begin(&reader_pos);
 }
 
 static int erst_close_pstore(struct pstore_info *psi)
@@ -996,16 +1093,13 @@ skip:
 		goto out;
 	}
 
-	len = erst_read(record_id, &rcd->hdr, rcd_len);
+	len = erst_read_record(record_id, &rcd->hdr, rcd_len, sizeof(*rcd),
+			&CPER_CREATOR_PSTORE);
 	/* The record may be cleared by others, try read next record */
 	if (len == -ENOENT)
 		goto skip;
-	else if (len < 0 || len < sizeof(*rcd)) {
-		rc = -EIO;
+	else if (len < 0)
 		goto out;
-	}
-	if (!guid_equal(&rcd->hdr.creator_id, &CPER_CREATOR_PSTORE))
-		goto skip;
 
 	record->buf = kmalloc(len, GFP_KERNEL);
 	if (record->buf == NULL) {
@@ -1122,7 +1216,7 @@ static int __init erst_init(void)
 	rc = erst_check_table(erst_tab);
 	if (rc) {
 		pr_err(FW_BUG "ERST table is invalid.\n");
-		goto err;
+		goto err_put_erst_tab;
 	}
 
 	apei_resources_init(&erst_resources);
@@ -1196,6 +1290,8 @@ err_release:
 	apei_resources_release(&erst_resources);
 err_fini:
 	apei_resources_fini(&erst_resources);
+err_put_erst_tab:
+	acpi_put_table((struct acpi_table_header *)erst_tab);
 err:
 	erst_disable = 1;
 	return rc;
diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c
index 24c9642e8fc7..0dc767392a6c 100644
--- a/drivers/acpi/apei/ghes.c
+++ b/drivers/acpi/apei/ghes.c
@@ -22,10 +22,12 @@
 #include <linux/moduleparam.h>
 #include <linux/init.h>
 #include <linux/acpi.h>
+#include <linux/bitfield.h>
 #include <linux/io.h>
 #include <linux/interrupt.h>
 #include <linux/timer.h>
 #include <linux/cper.h>
+#include <linux/cleanup.h>
 #include <linux/platform_device.h>
 #include <linux/mutex.h>
 #include <linux/ratelimit.h>
@@ -33,6 +35,7 @@
 #include <linux/irq_work.h>
 #include <linux/llist.h>
 #include <linux/genalloc.h>
+#include <linux/kfifo.h>
 #include <linux/pci.h>
 #include <linux/pfn.h>
 #include <linux/aer.h>
@@ -40,12 +43,15 @@
 #include <linux/sched/clock.h>
 #include <linux/uuid.h>
 #include <linux/ras.h>
+#include <linux/task_work.h>
+#include <linux/vmcore_info.h>
 
 #include <acpi/actbl1.h>
 #include <acpi/ghes.h>
 #include <acpi/apei.h>
 #include <asm/fixmap.h>
 #include <asm/tlbflush.h>
+#include <cxl/event.h>
 #include <ras/ras_event.h>
 
 #include "apei-internal.h"
@@ -78,6 +84,12 @@
 	((struct acpi_hest_generic_status *)				\
 	 ((struct ghes_estatus_node *)(estatus_node) + 1))
 
+#define GHES_VENDOR_ENTRY_LEN(gdata_len)                               \
+	(sizeof(struct ghes_vendor_record_entry) + (gdata_len))
+#define GHES_GDATA_FROM_VENDOR_ENTRY(vendor_entry)                     \
+	((struct acpi_hest_generic_data *)                              \
+	((struct ghes_vendor_record_entry *)(vendor_entry) + 1))
+
 /*
  *  NMI-like notifications vary by architecture, before the compiler can prune
  *  unused static functions it needs a value for these enums.
@@ -87,12 +99,28 @@
 #define FIX_APEI_GHES_SDEI_CRITICAL	__end_of_fixed_addresses
 #endif
 
+static ATOMIC_NOTIFIER_HEAD(ghes_report_chain);
+
 static inline bool is_hest_type_generic_v2(struct ghes *ghes)
 {
 	return ghes->generic->header.type == ACPI_HEST_TYPE_GENERIC_ERROR_V2;
 }
 
 /*
+ * A platform may describe one error source for the handling of synchronous
+ * errors (e.g. MCE or SEA), or for handling asynchronous errors (e.g. SCI
+ * or External Interrupt). On x86, the HEST notifications are always
+ * asynchronous, so only SEA on ARM is delivered as a synchronous
+ * notification.
+ */
+static inline bool is_hest_sync_notify(struct ghes *ghes)
+{
+	u8 notify_type = ghes->generic->notify.type;
+
+	return notify_type == ACPI_HEST_NOTIFY_SEA;
+}
+
+/*
  * This driver isn't really modular, however for the time being,
  * continuing to use module_param is the easiest way to remain
  * compatible with existing boot arg use cases.
@@ -101,6 +129,13 @@ bool ghes_disable;
 module_param_named(disable, ghes_disable, bool, 0);
 
 /*
+ * "ghes.edac_force_enable" forcibly enables ghes_edac and skips the platform
+ * check.
+ */
+static bool ghes_edac_force_enable;
+module_param_named(edac_force_enable, ghes_edac_force_enable, bool, 0);
+
+/*
  * All error sources notified with HED (Hardware Error Device) share a
  * single notifier callback, so they need to be linked and checked one
  * by one. This holds true for NMI too.
@@ -112,6 +147,13 @@ static LIST_HEAD(ghes_hed);
 static DEFINE_MUTEX(ghes_list_mutex);
 
 /*
+ * A list of GHES devices which are given to the corresponding EDAC driver
+ * ghes_edac for further use.
+ */
+static LIST_HEAD(ghes_devs);
+static DEFINE_MUTEX(ghes_devs_mutex);
+
+/*
  * Because the memory area used to transfer hardware error information
  * from BIOS to Linux can be determined only in NMI, IRQ or timer
  * handler, but general ioremap can not be used in atomic context, so
@@ -122,14 +164,17 @@ static DEFINE_MUTEX(ghes_list_mutex);
  */
 static DEFINE_SPINLOCK(ghes_notify_lock_irq);
 
+struct ghes_vendor_record_entry {
+	struct work_struct work;
+	int error_severity;
+	char vendor_record[];
+};
+
 static struct gen_pool *ghes_estatus_pool;
-static unsigned long ghes_estatus_pool_size_request;
 
-static struct ghes_estatus_cache *ghes_estatus_caches[GHES_ESTATUS_CACHES_SIZE];
+static struct ghes_estatus_cache __rcu *ghes_estatus_caches[GHES_ESTATUS_CACHES_SIZE];
 static atomic_t ghes_estatus_cache_alloced;
 
-static int ghes_panic_timeout __read_mostly = 30;
-
 static void __iomem *ghes_map(u64 pfn, enum fixed_addresses fixmap_idx)
 {
 	phys_addr_t paddr;
@@ -150,7 +195,7 @@ static void ghes_unmap(void __iomem *vaddr, enum fixed_addresses fixmap_idx)
 	clear_fixmap(fixmap_idx);
 }
 
-int ghes_estatus_pool_init(int num_ghes)
+int ghes_estatus_pool_init(unsigned int num_ghes)
 {
 	unsigned long addr, len;
 	int rc;
@@ -162,17 +207,10 @@ int ghes_estatus_pool_init(int num_ghes)
 	len = GHES_ESTATUS_CACHE_AVG_SIZE * GHES_ESTATUS_CACHE_ALLOCED_MAX;
 	len += (num_ghes * GHES_ESOURCE_PREALLOC_MAX_SIZE);
 
-	ghes_estatus_pool_size_request = PAGE_ALIGN(len);
 	addr = (unsigned long)vmalloc(PAGE_ALIGN(len));
 	if (!addr)
 		goto err_pool_alloc;
 
-	/*
-	 * New allocation must be visible in all pgd before it can be found by
-	 * an NMI allocating from the pool.
-	 */
-	vmalloc_sync_mappings();
-
 	rc = gen_pool_add(ghes_estatus_pool, addr, PAGE_ALIGN(len), -1);
 	if (rc)
 		goto err_pool_add;
@@ -188,6 +226,20 @@ err_pool_alloc:
 	return -ENOMEM;
 }
 
+/**
+ * ghes_estatus_pool_region_free - free previously allocated memory
+ *				   from the ghes_estatus_pool.
+ * @addr: address of memory to free.
+ * @size: size of memory to free.
+ *
+ * Returns none.
+ */
+void ghes_estatus_pool_region_free(unsigned long addr, u32 size)
+{
+	gen_pool_free(ghes_estatus_pool, addr, size);
+}
+EXPORT_SYMBOL_GPL(ghes_estatus_pool_region_free);
+
 static int map_gen_v2(struct ghes *ghes)
 {
 	return apei_map_generic_address(&ghes->generic_v2->read_ack_register);
@@ -414,35 +466,133 @@ static void ghes_clear_estatus(struct ghes *ghes,
 		ghes_ack_error(ghes->generic_v2);
 }
 
-static void ghes_handle_memory_failure(struct acpi_hest_generic_data *gdata, int sev)
+/**
+ * struct ghes_task_work - for synchronous RAS event
+ *
+ * @twork:                callback_head for task work
+ * @pfn:                  page frame number of corrupted page
+ * @flags:                work control flags
+ *
+ * Structure to pass task work to be handled before
+ * returning to user-space via task_work_add().
+ */
+struct ghes_task_work {
+	struct callback_head twork;
+	u64 pfn;
+	int flags;
+};
+
+static void memory_failure_cb(struct callback_head *twork)
+{
+	struct ghes_task_work *twcb = container_of(twork, struct ghes_task_work, twork);
+	int ret;
+
+	ret = memory_failure(twcb->pfn, twcb->flags);
+	gen_pool_free(ghes_estatus_pool, (unsigned long)twcb, sizeof(*twcb));
+
+	if (!ret || ret == -EHWPOISON || ret == -EOPNOTSUPP)
+		return;
+
+	pr_err("%#llx: Sending SIGBUS to %s:%d due to hardware memory corruption\n",
+			twcb->pfn, current->comm, task_pid_nr(current));
+	force_sig(SIGBUS);
+}
+
+static bool ghes_do_memory_failure(u64 physical_addr, int flags)
 {
-#ifdef CONFIG_ACPI_APEI_MEMORY_FAILURE
+	struct ghes_task_work *twcb;
 	unsigned long pfn;
+
+	if (!IS_ENABLED(CONFIG_ACPI_APEI_MEMORY_FAILURE))
+		return false;
+
+	pfn = PHYS_PFN(physical_addr);
+
+	if (flags == MF_ACTION_REQUIRED && current->mm) {
+		twcb = (void *)gen_pool_alloc(ghes_estatus_pool, sizeof(*twcb));
+		if (!twcb)
+			return false;
+
+		twcb->pfn = pfn;
+		twcb->flags = flags;
+		init_task_work(&twcb->twork, memory_failure_cb);
+		task_work_add(current, &twcb->twork, TWA_RESUME);
+		return true;
+	}
+
+	memory_failure_queue(pfn, flags);
+	return true;
+}
+
+static bool ghes_handle_memory_failure(struct acpi_hest_generic_data *gdata,
+				       int sev, bool sync)
+{
 	int flags = -1;
 	int sec_sev = ghes_severity(gdata->error_severity);
 	struct cper_sec_mem_err *mem_err = acpi_hest_get_payload(gdata);
 
 	if (!(mem_err->validation_bits & CPER_MEM_VALID_PA))
-		return;
-
-	pfn = mem_err->physical_addr >> PAGE_SHIFT;
-	if (!pfn_valid(pfn)) {
-		pr_warn_ratelimited(FW_WARN GHES_PFX
-		"Invalid address in generic error data: %#llx\n",
-		mem_err->physical_addr);
-		return;
-	}
+		return false;
 
 	/* iff following two events can be handled properly by now */
 	if (sec_sev == GHES_SEV_CORRECTED &&
 	    (gdata->flags & CPER_SEC_ERROR_THRESHOLD_EXCEEDED))
 		flags = MF_SOFT_OFFLINE;
 	if (sev == GHES_SEV_RECOVERABLE && sec_sev == GHES_SEV_RECOVERABLE)
-		flags = 0;
+		flags = sync ? MF_ACTION_REQUIRED : 0;
 
 	if (flags != -1)
-		memory_failure_queue(pfn, flags);
-#endif
+		return ghes_do_memory_failure(mem_err->physical_addr, flags);
+
+	return false;
+}
+
+static bool ghes_handle_arm_hw_error(struct acpi_hest_generic_data *gdata,
+				     int sev, bool sync)
+{
+	struct cper_sec_proc_arm *err = acpi_hest_get_payload(gdata);
+	int flags = sync ? MF_ACTION_REQUIRED : 0;
+	char error_type[120];
+	bool queued = false;
+	int sec_sev, i;
+	char *p;
+
+	sec_sev = ghes_severity(gdata->error_severity);
+	log_arm_hw_error(err, sec_sev);
+	if (sev != GHES_SEV_RECOVERABLE || sec_sev != GHES_SEV_RECOVERABLE)
+		return false;
+
+	p = (char *)(err + 1);
+	for (i = 0; i < err->err_info_num; i++) {
+		struct cper_arm_err_info *err_info = (struct cper_arm_err_info *)p;
+		bool is_cache = err_info->type & CPER_ARM_CACHE_ERROR;
+		bool has_pa = (err_info->validation_bits & CPER_ARM_INFO_VALID_PHYSICAL_ADDR);
+
+		/*
+		 * The field (err_info->error_info & BIT(26)) is fixed to set to
+		 * 1 in some old firmware of HiSilicon Kunpeng920. We assume that
+		 * firmware won't mix corrected errors in an uncorrected section,
+		 * and don't filter out 'corrected' error here.
+		 */
+		if (is_cache && has_pa) {
+			queued = ghes_do_memory_failure(err_info->physical_fault_addr, flags);
+			p += err_info->length;
+			continue;
+		}
+
+		cper_bits_to_str(error_type, sizeof(error_type),
+				 FIELD_GET(CPER_ARM_ERR_TYPE_MASK, err_info->type),
+				 cper_proc_error_type_strs,
+				 ARRAY_SIZE(cper_proc_error_type_strs));
+
+		pr_warn_ratelimited(FW_WARN GHES_PFX
+				    "Unhandled processor error type 0x%02x: %s%s\n",
+				    err_info->type, error_type,
+				    (err_info->type & ~CPER_ARM_ERR_TYPE_MASK) ? " with reserved bit(s)" : "");
+		p += err_info->length;
+	}
+
+	return queued;
 }
 
 /*
@@ -468,6 +618,7 @@ static void ghes_handle_aer(struct acpi_hest_generic_data *gdata)
 	    pcie_err->validation_bits & CPER_PCIE_VALID_AER_INFO) {
 		unsigned int devfn;
 		int aer_severity;
+		u8 *aer_info;
 
 		devfn = PCI_DEVFN(pcie_err->device_id.device,
 				  pcie_err->device_id.function);
@@ -481,15 +632,273 @@ static void ghes_handle_aer(struct acpi_hest_generic_data *gdata)
 		if (gdata->flags & CPER_SEC_RESET)
 			aer_severity = AER_FATAL;
 
+		aer_info = (void *)gen_pool_alloc(ghes_estatus_pool,
+						  sizeof(struct aer_capability_regs));
+		if (!aer_info)
+			return;
+		memcpy(aer_info, pcie_err->aer_info, sizeof(struct aer_capability_regs));
+
 		aer_recover_queue(pcie_err->device_id.segment,
 				  pcie_err->device_id.bus,
 				  devfn, aer_severity,
 				  (struct aer_capability_regs *)
-				  pcie_err->aer_info);
+				  aer_info);
+	}
+#endif
+}
+
+static BLOCKING_NOTIFIER_HEAD(vendor_record_notify_list);
+
+int ghes_register_vendor_record_notifier(struct notifier_block *nb)
+{
+	return blocking_notifier_chain_register(&vendor_record_notify_list, nb);
+}
+EXPORT_SYMBOL_GPL(ghes_register_vendor_record_notifier);
+
+void ghes_unregister_vendor_record_notifier(struct notifier_block *nb)
+{
+	blocking_notifier_chain_unregister(&vendor_record_notify_list, nb);
+}
+EXPORT_SYMBOL_GPL(ghes_unregister_vendor_record_notifier);
+
+static void ghes_vendor_record_work_func(struct work_struct *work)
+{
+	struct ghes_vendor_record_entry *entry;
+	struct acpi_hest_generic_data *gdata;
+	u32 len;
+
+	entry = container_of(work, struct ghes_vendor_record_entry, work);
+	gdata = GHES_GDATA_FROM_VENDOR_ENTRY(entry);
+
+	blocking_notifier_call_chain(&vendor_record_notify_list,
+				     entry->error_severity, gdata);
+
+	len = GHES_VENDOR_ENTRY_LEN(acpi_hest_get_record_size(gdata));
+	gen_pool_free(ghes_estatus_pool, (unsigned long)entry, len);
+}
+
+static void ghes_defer_non_standard_event(struct acpi_hest_generic_data *gdata,
+					  int sev)
+{
+	struct acpi_hest_generic_data *copied_gdata;
+	struct ghes_vendor_record_entry *entry;
+	u32 len;
+
+	len = GHES_VENDOR_ENTRY_LEN(acpi_hest_get_record_size(gdata));
+	entry = (void *)gen_pool_alloc(ghes_estatus_pool, len);
+	if (!entry)
+		return;
+
+	copied_gdata = GHES_GDATA_FROM_VENDOR_ENTRY(entry);
+	memcpy(copied_gdata, gdata, acpi_hest_get_record_size(gdata));
+	entry->error_severity = sev;
+
+	INIT_WORK(&entry->work, ghes_vendor_record_work_func);
+	schedule_work(&entry->work);
+}
+
+/* Room for 8 entries */
+#define CXL_CPER_PROT_ERR_FIFO_DEPTH 8
+static DEFINE_KFIFO(cxl_cper_prot_err_fifo, struct cxl_cper_prot_err_work_data,
+		    CXL_CPER_PROT_ERR_FIFO_DEPTH);
+
+/* Synchronize schedule_work() with cxl_cper_prot_err_work changes */
+static DEFINE_SPINLOCK(cxl_cper_prot_err_work_lock);
+struct work_struct *cxl_cper_prot_err_work;
+
+static void cxl_cper_post_prot_err(struct cxl_cper_sec_prot_err *prot_err,
+				   int severity)
+{
+#ifdef CONFIG_ACPI_APEI_PCIEAER
+	struct cxl_cper_prot_err_work_data wd;
+	u8 *dvsec_start, *cap_start;
+
+	if (!(prot_err->valid_bits & PROT_ERR_VALID_AGENT_ADDRESS)) {
+		pr_err_ratelimited("CXL CPER invalid agent type\n");
+		return;
 	}
+
+	if (!(prot_err->valid_bits & PROT_ERR_VALID_ERROR_LOG)) {
+		pr_err_ratelimited("CXL CPER invalid protocol error log\n");
+		return;
+	}
+
+	if (prot_err->err_len != sizeof(struct cxl_ras_capability_regs)) {
+		pr_err_ratelimited("CXL CPER invalid RAS Cap size (%u)\n",
+				   prot_err->err_len);
+		return;
+	}
+
+	if (!(prot_err->valid_bits & PROT_ERR_VALID_SERIAL_NUMBER))
+		pr_warn(FW_WARN "CXL CPER no device serial number\n");
+
+	guard(spinlock_irqsave)(&cxl_cper_prot_err_work_lock);
+
+	if (!cxl_cper_prot_err_work)
+		return;
+
+	switch (prot_err->agent_type) {
+	case RCD:
+	case DEVICE:
+	case LD:
+	case FMLD:
+	case RP:
+	case DSP:
+	case USP:
+		memcpy(&wd.prot_err, prot_err, sizeof(wd.prot_err));
+
+		dvsec_start = (u8 *)(prot_err + 1);
+		cap_start = dvsec_start + prot_err->dvsec_len;
+
+		memcpy(&wd.ras_cap, cap_start, sizeof(wd.ras_cap));
+		wd.severity = cper_severity_to_aer(severity);
+		break;
+	default:
+		pr_err_ratelimited("CXL CPER invalid agent type: %d\n",
+				   prot_err->agent_type);
+		return;
+	}
+
+	if (!kfifo_put(&cxl_cper_prot_err_fifo, wd)) {
+		pr_err_ratelimited("CXL CPER kfifo overflow\n");
+		return;
+	}
+
+	schedule_work(cxl_cper_prot_err_work);
 #endif
 }
 
+int cxl_cper_register_prot_err_work(struct work_struct *work)
+{
+	if (cxl_cper_prot_err_work)
+		return -EINVAL;
+
+	guard(spinlock)(&cxl_cper_prot_err_work_lock);
+	cxl_cper_prot_err_work = work;
+	return 0;
+}
+EXPORT_SYMBOL_NS_GPL(cxl_cper_register_prot_err_work, "CXL");
+
+int cxl_cper_unregister_prot_err_work(struct work_struct *work)
+{
+	if (cxl_cper_prot_err_work != work)
+		return -EINVAL;
+
+	guard(spinlock)(&cxl_cper_prot_err_work_lock);
+	cxl_cper_prot_err_work = NULL;
+	return 0;
+}
+EXPORT_SYMBOL_NS_GPL(cxl_cper_unregister_prot_err_work, "CXL");
+
+int cxl_cper_prot_err_kfifo_get(struct cxl_cper_prot_err_work_data *wd)
+{
+	return kfifo_get(&cxl_cper_prot_err_fifo, wd);
+}
+EXPORT_SYMBOL_NS_GPL(cxl_cper_prot_err_kfifo_get, "CXL");
+
+/* Room for 8 entries for each of the 4 event log queues */
+#define CXL_CPER_FIFO_DEPTH 32
+DEFINE_KFIFO(cxl_cper_fifo, struct cxl_cper_work_data, CXL_CPER_FIFO_DEPTH);
+
+/* Synchronize schedule_work() with cxl_cper_work changes */
+static DEFINE_SPINLOCK(cxl_cper_work_lock);
+struct work_struct *cxl_cper_work;
+
+static void cxl_cper_post_event(enum cxl_event_type event_type,
+				struct cxl_cper_event_rec *rec)
+{
+	struct cxl_cper_work_data wd;
+
+	if (rec->hdr.length <= sizeof(rec->hdr) ||
+	    rec->hdr.length > sizeof(*rec)) {
+		pr_err(FW_WARN "CXL CPER Invalid section length (%u)\n",
+		       rec->hdr.length);
+		return;
+	}
+
+	if (!(rec->hdr.validation_bits & CPER_CXL_COMP_EVENT_LOG_VALID)) {
+		pr_err(FW_WARN "CXL CPER invalid event\n");
+		return;
+	}
+
+	guard(spinlock_irqsave)(&cxl_cper_work_lock);
+
+	if (!cxl_cper_work)
+		return;
+
+	wd.event_type = event_type;
+	memcpy(&wd.rec, rec, sizeof(wd.rec));
+
+	if (!kfifo_put(&cxl_cper_fifo, wd)) {
+		pr_err_ratelimited("CXL CPER kfifo overflow\n");
+		return;
+	}
+
+	schedule_work(cxl_cper_work);
+}
+
+int cxl_cper_register_work(struct work_struct *work)
+{
+	if (cxl_cper_work)
+		return -EINVAL;
+
+	guard(spinlock)(&cxl_cper_work_lock);
+	cxl_cper_work = work;
+	return 0;
+}
+EXPORT_SYMBOL_NS_GPL(cxl_cper_register_work, "CXL");
+
+int cxl_cper_unregister_work(struct work_struct *work)
+{
+	if (cxl_cper_work != work)
+		return -EINVAL;
+
+	guard(spinlock)(&cxl_cper_work_lock);
+	cxl_cper_work = NULL;
+	return 0;
+}
+EXPORT_SYMBOL_NS_GPL(cxl_cper_unregister_work, "CXL");
+
+int cxl_cper_kfifo_get(struct cxl_cper_work_data *wd)
+{
+	return kfifo_get(&cxl_cper_fifo, wd);
+}
+EXPORT_SYMBOL_NS_GPL(cxl_cper_kfifo_get, "CXL");
+
+static void ghes_log_hwerr(int sev, guid_t *sec_type)
+{
+	if (sev != CPER_SEV_RECOVERABLE)
+		return;
+
+	if (guid_equal(sec_type, &CPER_SEC_PROC_ARM) ||
+	    guid_equal(sec_type, &CPER_SEC_PROC_GENERIC) ||
+	    guid_equal(sec_type, &CPER_SEC_PROC_IA)) {
+		hwerr_log_error_type(HWERR_RECOV_CPU);
+		return;
+	}
+
+	if (guid_equal(sec_type, &CPER_SEC_CXL_PROT_ERR) ||
+	    guid_equal(sec_type, &CPER_SEC_CXL_GEN_MEDIA_GUID) ||
+	    guid_equal(sec_type, &CPER_SEC_CXL_DRAM_GUID) ||
+	    guid_equal(sec_type, &CPER_SEC_CXL_MEM_MODULE_GUID)) {
+		hwerr_log_error_type(HWERR_RECOV_CXL);
+		return;
+	}
+
+	if (guid_equal(sec_type, &CPER_SEC_PCIE) ||
+	    guid_equal(sec_type, &CPER_SEC_PCI_X_BUS)) {
+		hwerr_log_error_type(HWERR_RECOV_PCI);
+		return;
+	}
+
+	if (guid_equal(sec_type, &CPER_SEC_PLATFORM_MEM)) {
+		hwerr_log_error_type(HWERR_RECOV_MEMORY);
+		return;
+	}
+
+	hwerr_log_error_type(HWERR_RECOV_OTHERS);
+}
+
 static void ghes_do_proc(struct ghes *ghes,
 			 const struct acpi_hest_generic_status *estatus)
 {
@@ -498,6 +907,8 @@ static void ghes_do_proc(struct ghes *ghes,
 	guid_t *sec_type;
 	const guid_t *fru_id = &guid_null;
 	char *fru_text = "";
+	bool queued = false;
+	bool sync = is_hest_sync_notify(ghes);
 
 	sev = ghes_severity(estatus->error_severity);
 	apei_estatus_for_each_section(estatus, gdata) {
@@ -509,29 +920,54 @@ static void ghes_do_proc(struct ghes *ghes,
 		if (gdata->validation_bits & CPER_SEC_VALID_FRU_TEXT)
 			fru_text = gdata->fru_text;
 
+		ghes_log_hwerr(sev, sec_type);
 		if (guid_equal(sec_type, &CPER_SEC_PLATFORM_MEM)) {
 			struct cper_sec_mem_err *mem_err = acpi_hest_get_payload(gdata);
 
-			ghes_edac_report_mem_error(sev, mem_err);
+			atomic_notifier_call_chain(&ghes_report_chain, sev, mem_err);
 
 			arch_apei_report_mem_error(sev, mem_err);
-			ghes_handle_memory_failure(gdata, sev);
-		}
-		else if (guid_equal(sec_type, &CPER_SEC_PCIE)) {
+			queued = ghes_handle_memory_failure(gdata, sev, sync);
+		} else if (guid_equal(sec_type, &CPER_SEC_PCIE)) {
 			ghes_handle_aer(gdata);
-		}
-		else if (guid_equal(sec_type, &CPER_SEC_PROC_ARM)) {
-			struct cper_sec_proc_arm *err = acpi_hest_get_payload(gdata);
+		} else if (guid_equal(sec_type, &CPER_SEC_PROC_ARM)) {
+			queued = ghes_handle_arm_hw_error(gdata, sev, sync);
+		} else if (guid_equal(sec_type, &CPER_SEC_CXL_PROT_ERR)) {
+			struct cxl_cper_sec_prot_err *prot_err = acpi_hest_get_payload(gdata);
+
+			cxl_cper_post_prot_err(prot_err, gdata->error_severity);
+		} else if (guid_equal(sec_type, &CPER_SEC_CXL_GEN_MEDIA_GUID)) {
+			struct cxl_cper_event_rec *rec = acpi_hest_get_payload(gdata);
+
+			cxl_cper_post_event(CXL_CPER_EVENT_GEN_MEDIA, rec);
+		} else if (guid_equal(sec_type, &CPER_SEC_CXL_DRAM_GUID)) {
+			struct cxl_cper_event_rec *rec = acpi_hest_get_payload(gdata);
+
+			cxl_cper_post_event(CXL_CPER_EVENT_DRAM, rec);
+		} else if (guid_equal(sec_type, &CPER_SEC_CXL_MEM_MODULE_GUID)) {
+			struct cxl_cper_event_rec *rec = acpi_hest_get_payload(gdata);
 
-			log_arm_hw_error(err);
+			cxl_cper_post_event(CXL_CPER_EVENT_MEM_MODULE, rec);
 		} else {
 			void *err = acpi_hest_get_payload(gdata);
 
+			ghes_defer_non_standard_event(gdata, sev);
 			log_non_standard_event(sec_type, fru_id, fru_text,
 					       sec_sev, err,
 					       gdata->error_data_length);
 		}
 	}
+
+	/*
+	 * If no memory failure work is queued for abnormal synchronous
+	 * errors, do a force kill.
+	 */
+	if (sync && !queued) {
+		dev_err(ghes->dev,
+			HW_ERR GHES_PFX "%s:%d: synchronous unrecoverable error (SIGBUS)\n",
+			current->comm, task_pid_nr(current));
+		force_sig(SIGBUS);
+	}
 }
 
 static void __ghes_print_estatus(const char *pfx,
@@ -639,48 +1075,42 @@ static struct ghes_estatus_cache *ghes_estatus_cache_alloc(
 	return cache;
 }
 
-static void ghes_estatus_cache_free(struct ghes_estatus_cache *cache)
+static void ghes_estatus_cache_rcu_free(struct rcu_head *head)
 {
+	struct ghes_estatus_cache *cache;
 	u32 len;
 
+	cache = container_of(head, struct ghes_estatus_cache, rcu);
 	len = cper_estatus_len(GHES_ESTATUS_FROM_CACHE(cache));
 	len = GHES_ESTATUS_CACHE_LEN(len);
 	gen_pool_free(ghes_estatus_pool, (unsigned long)cache, len);
 	atomic_dec(&ghes_estatus_cache_alloced);
 }
 
-static void ghes_estatus_cache_rcu_free(struct rcu_head *head)
+static void
+ghes_estatus_cache_add(struct acpi_hest_generic *generic,
+		       struct acpi_hest_generic_status *estatus)
 {
-	struct ghes_estatus_cache *cache;
-
-	cache = container_of(head, struct ghes_estatus_cache, rcu);
-	ghes_estatus_cache_free(cache);
-}
-
-static void ghes_estatus_cache_add(
-	struct acpi_hest_generic *generic,
-	struct acpi_hest_generic_status *estatus)
-{
-	int i, slot = -1, count;
 	unsigned long long now, duration, period, max_period = 0;
-	struct ghes_estatus_cache *cache, *slot_cache = NULL, *new_cache;
+	struct ghes_estatus_cache *cache, *new_cache;
+	struct ghes_estatus_cache __rcu *victim;
+	int i, slot = -1, count;
 
 	new_cache = ghes_estatus_cache_alloc(generic, estatus);
-	if (new_cache == NULL)
+	if (!new_cache)
 		return;
+
 	rcu_read_lock();
 	now = sched_clock();
 	for (i = 0; i < GHES_ESTATUS_CACHES_SIZE; i++) {
 		cache = rcu_dereference(ghes_estatus_caches[i]);
 		if (cache == NULL) {
 			slot = i;
-			slot_cache = NULL;
 			break;
 		}
 		duration = now - cache->time_in;
 		if (duration >= GHES_ESTATUS_IN_CACHE_MAX_NSEC) {
 			slot = i;
-			slot_cache = cache;
 			break;
 		}
 		count = atomic_read(&cache->count);
@@ -689,32 +1119,48 @@ static void ghes_estatus_cache_add(
 		if (period > max_period) {
 			max_period = period;
 			slot = i;
-			slot_cache = cache;
 		}
 	}
-	/* new_cache must be put into array after its contents are written */
-	smp_wmb();
-	if (slot != -1 && cmpxchg(ghes_estatus_caches + slot,
-				  slot_cache, new_cache) == slot_cache) {
-		if (slot_cache)
-			call_rcu(&slot_cache->rcu, ghes_estatus_cache_rcu_free);
-	} else
-		ghes_estatus_cache_free(new_cache);
 	rcu_read_unlock();
+
+	if (slot != -1) {
+		/*
+		 * Use release semantics to ensure that ghes_estatus_cached()
+		 * running on another CPU will see the updated cache fields if
+		 * it can see the new value of the pointer.
+		 */
+		victim = xchg_release(&ghes_estatus_caches[slot],
+				      RCU_INITIALIZER(new_cache));
+
+		/*
+		 * At this point, victim may point to a cached item different
+		 * from the one based on which we selected the slot. Instead of
+		 * going to the loop again to pick another slot, let's just
+		 * drop the other item anyway: this may cause a false cache
+		 * miss later on, but that won't cause any problems.
+		 */
+		if (victim)
+			call_rcu(&unrcu_pointer(victim)->rcu,
+				 ghes_estatus_cache_rcu_free);
+	}
 }
 
 static void __ghes_panic(struct ghes *ghes,
 			 struct acpi_hest_generic_status *estatus,
 			 u64 buf_paddr, enum fixed_addresses fixmap_idx)
 {
+	const char *msg = GHES_PFX "Fatal hardware error";
+
 	__ghes_print_estatus(KERN_EMERG, ghes->generic, estatus);
 
+	add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
+
 	ghes_clear_estatus(ghes, estatus, buf_paddr, fixmap_idx);
 
-	/* reboot to log the error! */
 	if (!panic_timeout)
-		panic_timeout = ghes_panic_timeout;
-	panic("Fatal hardware error!");
+		pr_emerg("%s but panic disabled\n", msg);
+
+	panic(msg);
 }
 
 static int ghes_proc(struct ghes *ghes)
@@ -759,7 +1205,7 @@ static void ghes_add_timer(struct ghes *ghes)
 
 static void ghes_poll_func(struct timer_list *t)
 {
-	struct ghes *ghes = from_timer(ghes, t, timer);
+	struct ghes *ghes = timer_container_of(ghes, t, timer);
 	unsigned long flags;
 
 	spin_lock_irqsave(&ghes_notify_lock_irq, flags);
@@ -792,12 +1238,10 @@ static int ghes_notify_hed(struct notifier_block *this, unsigned long event,
 	int ret = NOTIFY_DONE;
 
 	spin_lock_irqsave(&ghes_notify_lock_irq, flags);
-	rcu_read_lock();
 	list_for_each_entry_rcu(ghes, &ghes_hed, list) {
 		if (!ghes_proc(ghes))
 			ret = NOTIFY_OK;
 	}
-	rcu_read_unlock();
 	spin_unlock_irqrestore(&ghes_notify_lock_irq, flags);
 
 	return ret;
@@ -842,7 +1286,9 @@ static void ghes_proc_in_irq(struct irq_work *irq_work)
 		estatus = GHES_ESTATUS_FROM_NODE(estatus_node);
 		len = cper_estatus_len(estatus);
 		node_len = GHES_ESTATUS_NODE_LEN(len);
+
 		ghes_do_proc(estatus_node->ghes, estatus);
+
 		if (!ghes_estatus_cached(estatus)) {
 			generic = estatus_node->generic;
 			if (ghes_print_estatus(NULL, generic, estatus))
@@ -850,6 +1296,7 @@ static void ghes_proc_in_irq(struct irq_work *irq_work)
 		}
 		gen_pool_free(ghes_estatus_pool, (unsigned long)estatus_node,
 			      node_len);
+
 		llnode = next;
 	}
 }
@@ -1227,7 +1674,11 @@ static int ghes_probe(struct platform_device *ghes_dev)
 
 	platform_set_drvdata(ghes_dev, ghes);
 
-	ghes_edac_register(ghes, &ghes_dev->dev);
+	ghes->dev = &ghes_dev->dev;
+
+	mutex_lock(&ghes_devs_mutex);
+	list_add_tail(&ghes->elist, &ghes_devs);
+	mutex_unlock(&ghes_devs_mutex);
 
 	/* Handle any pending errors right away */
 	spin_lock_irqsave(&ghes_notify_lock_irq, flags);
@@ -1244,7 +1695,7 @@ err:
 	return rc;
 }
 
-static int ghes_remove(struct platform_device *ghes_dev)
+static void ghes_remove(struct platform_device *ghes_dev)
 {
 	int rc;
 	struct ghes *ghes;
@@ -1256,7 +1707,7 @@ static int ghes_remove(struct platform_device *ghes_dev)
 	ghes->flags |= GHES_EXITING;
 	switch (generic->notify.type) {
 	case ACPI_HEST_NOTIFY_POLLED:
-		del_timer_sync(&ghes->timer);
+		timer_shutdown_sync(&ghes->timer);
 		break;
 	case ACPI_HEST_NOTIFY_EXTERNAL:
 		free_irq(ghes->irq, ghes);
@@ -1281,8 +1732,15 @@ static int ghes_remove(struct platform_device *ghes_dev)
 		break;
 	case ACPI_HEST_NOTIFY_SOFTWARE_DELEGATED:
 		rc = apei_sdei_unregister_ghes(ghes);
-		if (rc)
-			return rc;
+		if (rc) {
+			/*
+			 * Returning early results in a resource leak, but we're
+			 * only here if stopping the hardware failed.
+			 */
+			dev_err(&ghes_dev->dev, "Failed to unregister ghes (%pe)\n",
+				ERR_PTR(rc));
+			return;
+		}
 		break;
 	default:
 		BUG();
@@ -1291,13 +1749,11 @@ static int ghes_remove(struct platform_device *ghes_dev)
 
 	ghes_fini(ghes);
 
-	ghes_edac_unregister(ghes);
+	mutex_lock(&ghes_devs_mutex);
+	list_del(&ghes->elist);
+	mutex_unlock(&ghes_devs_mutex);
 
 	kfree(ghes);
-
-	platform_set_drvdata(ghes_dev, NULL);
-
-	return 0;
 }
 
 static struct platform_driver ghes_platform_driver = {
@@ -1308,33 +1764,35 @@ static struct platform_driver ghes_platform_driver = {
 	.remove		= ghes_remove,
 };
 
-static int __init ghes_init(void)
+void __init acpi_ghes_init(void)
 {
 	int rc;
 
+	acpi_sdei_init();
+
 	if (acpi_disabled)
-		return -ENODEV;
+		return;
 
 	switch (hest_disable) {
 	case HEST_NOT_FOUND:
-		return -ENODEV;
+		return;
 	case HEST_DISABLED:
 		pr_info(GHES_PFX "HEST is not enabled!\n");
-		return -EINVAL;
+		return;
 	default:
 		break;
 	}
 
 	if (ghes_disable) {
 		pr_info(GHES_PFX "GHES is not enabled!\n");
-		return -EINVAL;
+		return;
 	}
 
 	ghes_nmi_init_cxt();
 
 	rc = platform_driver_register(&ghes_platform_driver);
 	if (rc)
-		goto err;
+		return;
 
 	rc = apei_osc_setup();
 	if (rc == 0 && osc_sb_apei_support_acked)
@@ -1345,9 +1803,44 @@ static int __init ghes_init(void)
 		pr_info(GHES_PFX "APEI firmware first mode is enabled by APEI bit.\n");
 	else
 		pr_info(GHES_PFX "Failed to enable APEI firmware first mode.\n");
+}
 
-	return 0;
-err:
-	return rc;
+/*
+ * Known x86 systems that prefer GHES error reporting:
+ */
+static struct acpi_platform_list plat_list[] = {
+	{"HPE   ", "Server  ", 0, ACPI_SIG_FADT, all_versions},
+	{ } /* End */
+};
+
+struct list_head *ghes_get_devices(void)
+{
+	int idx = -1;
+
+	if (IS_ENABLED(CONFIG_X86)) {
+		idx = acpi_match_platform_list(plat_list);
+		if (idx < 0) {
+			if (!ghes_edac_force_enable)
+				return NULL;
+
+			pr_warn_once("Force-loading ghes_edac on an unsupported platform. You're on your own!\n");
+		}
+	} else if (list_empty(&ghes_devs)) {
+		return NULL;
+	}
+
+	return &ghes_devs;
+}
+EXPORT_SYMBOL_GPL(ghes_get_devices);
+
+void ghes_register_report_chain(struct notifier_block *nb)
+{
+	atomic_notifier_chain_register(&ghes_report_chain, nb);
+}
+EXPORT_SYMBOL_GPL(ghes_register_report_chain);
+
+void ghes_unregister_report_chain(struct notifier_block *nb)
+{
+	atomic_notifier_chain_unregister(&ghes_report_chain, nb);
 }
-device_initcall(ghes_init);
+EXPORT_SYMBOL_GPL(ghes_unregister_report_chain);
diff --git a/drivers/acpi/apei/hest.c b/drivers/acpi/apei/hest.c
index 822402480f7d..20d757687e3d 100644
--- a/drivers/acpi/apei/hest.c
+++ b/drivers/acpi/apei/hest.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * APEI Hardware Error Souce Table support
+ * APEI Hardware Error Source Table support
  *
  * HEST describes error sources in detail; communicates operational
  * parameters (i.e. severity levels, masking bits, and threshold
@@ -37,6 +37,20 @@ EXPORT_SYMBOL_GPL(hest_disable);
 
 static struct acpi_table_hest *__read_mostly hest_tab;
 
+/*
+ * Since GHES_ASSIST is not supported, skip initialization of GHES_ASSIST
+ * structures for MCA.
+ * During HEST parsing, detected MCA error sources are cached from early
+ * table entries so that the Flags and Source Id fields from these cached
+ * values are then referred to in later table entries to determine if the
+ * encountered GHES_ASSIST structure should be initialized.
+ */
+static struct {
+	struct acpi_hest_ia_corrected *cmc;
+	struct acpi_hest_ia_machine_check *mc;
+	struct acpi_hest_ia_deferred_check *dmc;
+} mces;
+
 static const int hest_esrc_len_tab[ACPI_HEST_TYPE_RESERVED] = {
 	[ACPI_HEST_TYPE_IA32_CHECK] = -1,	/* need further calculation */
 	[ACPI_HEST_TYPE_IA32_CORRECTED_CHECK] = -1,
@@ -49,6 +63,12 @@ static const int hest_esrc_len_tab[ACPI_HEST_TYPE_RESERVED] = {
 	[ACPI_HEST_TYPE_IA32_DEFERRED_CHECK] = -1,
 };
 
+static inline bool is_generic_error(struct acpi_hest_header *hest_hdr)
+{
+	return hest_hdr->type == ACPI_HEST_TYPE_GENERIC_ERROR ||
+	       hest_hdr->type == ACPI_HEST_TYPE_GENERIC_ERROR_V2;
+}
+
 static int hest_esrc_len(struct acpi_hest_header *hest_hdr)
 {
 	u16 hest_type = hest_hdr->type;
@@ -64,23 +84,57 @@ static int hest_esrc_len(struct acpi_hest_header *hest_hdr)
 		cmc = (struct acpi_hest_ia_corrected *)hest_hdr;
 		len = sizeof(*cmc) + cmc->num_hardware_banks *
 			sizeof(struct acpi_hest_ia_error_bank);
+		mces.cmc = cmc;
 	} else if (hest_type == ACPI_HEST_TYPE_IA32_CHECK) {
 		struct acpi_hest_ia_machine_check *mc;
 		mc = (struct acpi_hest_ia_machine_check *)hest_hdr;
 		len = sizeof(*mc) + mc->num_hardware_banks *
 			sizeof(struct acpi_hest_ia_error_bank);
+		mces.mc = mc;
 	} else if (hest_type == ACPI_HEST_TYPE_IA32_DEFERRED_CHECK) {
 		struct acpi_hest_ia_deferred_check *mc;
 		mc = (struct acpi_hest_ia_deferred_check *)hest_hdr;
 		len = sizeof(*mc) + mc->num_hardware_banks *
 			sizeof(struct acpi_hest_ia_error_bank);
+		mces.dmc = mc;
 	}
 	BUG_ON(len == -1);
 
 	return len;
 };
 
-int apei_hest_parse(apei_hest_func_t func, void *data)
+/*
+ * GHES and GHESv2 structures share the same format, starting from
+ * Source Id and ending in Error Status Block Length (inclusive).
+ */
+static bool is_ghes_assist_struct(struct acpi_hest_header *hest_hdr)
+{
+	struct acpi_hest_generic *ghes;
+	u16 related_source_id;
+
+	if (hest_hdr->type != ACPI_HEST_TYPE_GENERIC_ERROR &&
+	    hest_hdr->type != ACPI_HEST_TYPE_GENERIC_ERROR_V2)
+		return false;
+
+	ghes = (struct acpi_hest_generic *)hest_hdr;
+	related_source_id = ghes->related_source_id;
+
+	if (mces.cmc && mces.cmc->flags & ACPI_HEST_GHES_ASSIST &&
+	    related_source_id == mces.cmc->header.source_id)
+		return true;
+	if (mces.mc && mces.mc->flags & ACPI_HEST_GHES_ASSIST &&
+	    related_source_id == mces.mc->header.source_id)
+		return true;
+	if (mces.dmc && mces.dmc->flags & ACPI_HEST_GHES_ASSIST &&
+	    related_source_id == mces.dmc->header.source_id)
+		return true;
+
+	return false;
+}
+
+typedef int (*apei_hest_func_t)(struct acpi_hest_header *hest_hdr, void *data);
+
+static int apei_hest_parse(apei_hest_func_t func, void *data)
 {
 	struct acpi_hest_header *hest_hdr;
 	int i, rc, len;
@@ -106,6 +160,11 @@ int apei_hest_parse(apei_hest_func_t func, void *data)
 			return -EINVAL;
 		}
 
+		if (is_ghes_assist_struct(hest_hdr)) {
+			hest_hdr = (void *)hest_hdr + len;
+			continue;
+		}
+
 		rc = func(hest_hdr, data);
 		if (rc)
 			return rc;
@@ -115,7 +174,6 @@ int apei_hest_parse(apei_hest_func_t func, void *data)
 
 	return 0;
 }
-EXPORT_SYMBOL_GPL(apei_hest_parse);
 
 /*
  * Check if firmware advertises firmware first mode. We need FF bit to be set
@@ -141,8 +199,7 @@ static int __init hest_parse_ghes_count(struct acpi_hest_header *hest_hdr, void
 {
 	int *count = data;
 
-	if (hest_hdr->type == ACPI_HEST_TYPE_GENERIC_ERROR ||
-	    hest_hdr->type == ACPI_HEST_TYPE_GENERIC_ERROR_V2)
+	if (is_generic_error(hest_hdr))
 		(*count)++;
 	return 0;
 }
@@ -153,8 +210,7 @@ static int __init hest_parse_ghes(struct acpi_hest_header *hest_hdr, void *data)
 	struct ghes_arr *ghes_arr = data;
 	int rc, i;
 
-	if (hest_hdr->type != ACPI_HEST_TYPE_GENERIC_ERROR &&
-	    hest_hdr->type != ACPI_HEST_TYPE_GENERIC_ERROR_V2)
+	if (!is_generic_error(hest_hdr))
 		return 0;
 
 	if (!((struct acpi_hest_generic *)hest_hdr)->enabled)
@@ -219,7 +275,7 @@ err:
 static int __init setup_hest_disable(char *str)
 {
 	hest_disable = HEST_DISABLED;
-	return 0;
+	return 1;
 }
 
 __setup("hest_disable", setup_hest_disable);
@@ -227,7 +283,7 @@ __setup("hest_disable", setup_hest_disable);
 void __init acpi_hest_init(void)
 {
 	acpi_status status;
-	int rc = -ENODEV;
+	int rc;
 	unsigned int ghes_count = 0;
 
 	if (hest_disable) {
@@ -243,8 +299,8 @@ void __init acpi_hest_init(void)
 	} else if (ACPI_FAILURE(status)) {
 		const char *msg = acpi_format_exception(status);
 		pr_err(HEST_PFX "Failed to get table, %s\n", msg);
-		rc = -EINVAL;
-		goto err;
+		hest_disable = HEST_DISABLED;
+		return;
 	}
 
 	rc = apei_hest_parse(hest_parse_cmc, NULL);
@@ -266,4 +322,5 @@ void __init acpi_hest_init(void)
 	return;
 err:
 	hest_disable = HEST_DISABLED;
+	acpi_put_table((struct acpi_table_header *)hest_tab);
 }
diff --git a/drivers/acpi/arm64/Kconfig b/drivers/acpi/arm64/Kconfig
index 6dba187f4f2e..f2fd79f22e7d 100644
--- a/drivers/acpi/arm64/Kconfig
+++ b/drivers/acpi/arm64/Kconfig
@@ -8,3 +8,19 @@ config ACPI_IORT
 
 config ACPI_GTDT
 	bool
+
+config ACPI_AGDI
+	bool "Arm Generic Diagnostic Dump and Reset Device Interface"
+	depends on ARM_SDE_INTERFACE
+	help
+	  Arm Generic Diagnostic Dump and Reset Device Interface (AGDI) is
+	  a standard that enables issuing a non-maskable diagnostic dump and
+	  reset command.
+
+	  If set, the kernel parses AGDI table and listens for the command.
+
+config ACPI_APMT
+	bool
+
+config ACPI_MPAM
+	bool
diff --git a/drivers/acpi/arm64/Makefile b/drivers/acpi/arm64/Makefile
index 6ff50f4ed947..9390b57cb564 100644
--- a/drivers/acpi/arm64/Makefile
+++ b/drivers/acpi/arm64/Makefile
@@ -1,3 +1,11 @@
 # SPDX-License-Identifier: GPL-2.0-only
-obj-$(CONFIG_ACPI_IORT) 	+= iort.o
+obj-$(CONFIG_ACPI_AGDI) 	+= agdi.o
+obj-$(CONFIG_ACPI_APMT) 	+= apmt.o
+obj-$(CONFIG_ACPI_FFH)		+= ffh.o
 obj-$(CONFIG_ACPI_GTDT) 	+= gtdt.o
+obj-$(CONFIG_ACPI_IORT) 	+= iort.o
+obj-$(CONFIG_ACPI_MPAM) 	+= mpam.o
+obj-$(CONFIG_ACPI_PROCESSOR_IDLE) += cpuidle.o
+obj-$(CONFIG_ARM_AMBA)		+= amba.o
+obj-y				+= dma.o init.o
+obj-y				+= thermal_cpufreq.o
diff --git a/drivers/acpi/arm64/agdi.c b/drivers/acpi/arm64/agdi.c
new file mode 100644
index 000000000000..e0df3daa4abf
--- /dev/null
+++ b/drivers/acpi/arm64/agdi.c
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * This file implements handling of
+ * Arm Generic Diagnostic Dump and Reset Interface table (AGDI)
+ *
+ * Copyright (c) 2022, Ampere Computing LLC
+ */
+
+#define pr_fmt(fmt) "ACPI: AGDI: " fmt
+
+#include <linux/acpi.h>
+#include <linux/arm_sdei.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include "init.h"
+
+struct agdi_data {
+	int sdei_event;
+};
+
+static int agdi_sdei_handler(u32 sdei_event, struct pt_regs *regs, void *arg)
+{
+	nmi_panic(regs, "Arm Generic Diagnostic Dump and Reset SDEI event issued");
+	return 0;
+}
+
+static int agdi_sdei_probe(struct platform_device *pdev,
+			   struct agdi_data *adata)
+{
+	int err;
+
+	err = sdei_event_register(adata->sdei_event, agdi_sdei_handler, pdev);
+	if (err) {
+		dev_err(&pdev->dev, "Failed to register for SDEI event %d",
+			adata->sdei_event);
+		return err;
+	}
+
+	err = sdei_event_enable(adata->sdei_event);
+	if (err)  {
+		sdei_event_unregister(adata->sdei_event);
+		dev_err(&pdev->dev, "Failed to enable event %d\n",
+			adata->sdei_event);
+		return err;
+	}
+
+	return 0;
+}
+
+static int agdi_probe(struct platform_device *pdev)
+{
+	struct agdi_data *adata = dev_get_platdata(&pdev->dev);
+
+	if (!adata)
+		return -EINVAL;
+
+	return agdi_sdei_probe(pdev, adata);
+}
+
+static void agdi_remove(struct platform_device *pdev)
+{
+	struct agdi_data *adata = dev_get_platdata(&pdev->dev);
+	int err, i;
+
+	err = sdei_event_disable(adata->sdei_event);
+	if (err) {
+		dev_err(&pdev->dev, "Failed to disable sdei-event #%d (%pe)\n",
+			adata->sdei_event, ERR_PTR(err));
+		return;
+	}
+
+	for (i = 0; i < 3; i++) {
+		err = sdei_event_unregister(adata->sdei_event);
+		if (err != -EINPROGRESS)
+			break;
+
+		schedule();
+	}
+
+	if (err)
+		dev_err(&pdev->dev, "Failed to unregister sdei-event #%d (%pe)\n",
+			adata->sdei_event, ERR_PTR(err));
+}
+
+static struct platform_driver agdi_driver = {
+	.driver = {
+		.name = "agdi",
+	},
+	.probe = agdi_probe,
+	.remove = agdi_remove,
+};
+
+void __init acpi_agdi_init(void)
+{
+	struct acpi_table_agdi *agdi_table;
+	struct agdi_data pdata;
+	struct platform_device *pdev;
+	acpi_status status;
+
+	status = acpi_get_table(ACPI_SIG_AGDI, 0,
+				(struct acpi_table_header **) &agdi_table);
+	if (ACPI_FAILURE(status))
+		return;
+
+	if (agdi_table->flags & ACPI_AGDI_SIGNALING_MODE) {
+		pr_warn("Interrupt signaling is not supported");
+		goto err_put_table;
+	}
+
+	pdata.sdei_event = agdi_table->sdei_event;
+
+	pdev = platform_device_register_data(NULL, "agdi", 0, &pdata, sizeof(pdata));
+	if (IS_ERR(pdev))
+		goto err_put_table;
+
+	if (platform_driver_register(&agdi_driver))
+		platform_device_unregister(pdev);
+
+err_put_table:
+	acpi_put_table((struct acpi_table_header *)agdi_table);
+}
diff --git a/drivers/acpi/arm64/amba.c b/drivers/acpi/arm64/amba.c
new file mode 100644
index 000000000000..1350083bce5f
--- /dev/null
+++ b/drivers/acpi/arm64/amba.c
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/*
+ * ACPI support for platform bus type.
+ *
+ * Copyright (C) 2015, Linaro Ltd
+ * Author: Graeme Gregory <graeme.gregory@linaro.org>
+ */
+
+#include <linux/acpi.h>
+#include <linux/amba/bus.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/ioport.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#include "init.h"
+
+static const struct acpi_device_id amba_id_list[] = {
+	{"ARMH0061", 0}, /* PL061 GPIO Device */
+	{"ARMH0330", 0}, /* ARM DMA Controller DMA-330 */
+	{"", 0},
+};
+
+static void amba_register_dummy_clk(void)
+{
+	struct clk *amba_dummy_clk;
+
+	amba_dummy_clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, 0, 0);
+	clk_register_clkdev(amba_dummy_clk, "apb_pclk", NULL);
+}
+
+static int amba_handler_attach(struct acpi_device *adev,
+				const struct acpi_device_id *id)
+{
+	struct acpi_device *parent = acpi_dev_parent(adev);
+	struct amba_device *dev;
+	struct resource_entry *rentry;
+	struct list_head resource_list;
+	bool address_found = false;
+	int irq_no = 0;
+	int ret;
+
+	/* If the ACPI node already has a physical device attached, skip it. */
+	if (adev->physical_node_count)
+		return 0;
+
+	dev = amba_device_alloc(dev_name(&adev->dev), 0, 0);
+	if (!dev) {
+		dev_err(&adev->dev, "%s(): amba_device_alloc() failed\n",
+			__func__);
+		return -ENOMEM;
+	}
+
+	INIT_LIST_HEAD(&resource_list);
+	ret = acpi_dev_get_resources(adev, &resource_list, NULL, NULL);
+	if (ret < 0)
+		goto err_free;
+
+	list_for_each_entry(rentry, &resource_list, node) {
+		switch (resource_type(rentry->res)) {
+		case IORESOURCE_MEM:
+			if (!address_found) {
+				dev->res = *rentry->res;
+				dev->res.name = dev_name(&dev->dev);
+				address_found = true;
+			}
+			break;
+		case IORESOURCE_IRQ:
+			if (irq_no < AMBA_NR_IRQS)
+				dev->irq[irq_no++] = rentry->res->start;
+			break;
+		default:
+			dev_warn(&adev->dev, "Invalid resource\n");
+			break;
+		}
+	}
+
+	acpi_dev_free_resource_list(&resource_list);
+
+	/*
+	 * If the ACPI node has a parent and that parent has a physical device
+	 * attached to it, that physical device should be the parent of
+	 * the amba device we are about to create.
+	 */
+	if (parent)
+		dev->dev.parent = acpi_get_first_physical_node(parent);
+
+	device_set_node(&dev->dev, acpi_fwnode_handle(adev));
+
+	ret = amba_device_add(dev, &iomem_resource);
+	if (ret) {
+		dev_err(&adev->dev, "%s(): amba_device_add() failed (%d)\n",
+		       __func__, ret);
+		goto err_free;
+	}
+
+	return 1;
+
+err_free:
+	amba_device_put(dev);
+	return ret;
+}
+
+static struct acpi_scan_handler amba_handler = {
+	.ids = amba_id_list,
+	.attach = amba_handler_attach,
+};
+
+void __init acpi_amba_init(void)
+{
+	amba_register_dummy_clk();
+	acpi_scan_add_handler(&amba_handler);
+}
diff --git a/drivers/acpi/arm64/apmt.c b/drivers/acpi/arm64/apmt.c
new file mode 100644
index 000000000000..bb010f6164e5
--- /dev/null
+++ b/drivers/acpi/arm64/apmt.c
@@ -0,0 +1,180 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ARM APMT table support.
+ * Design document number: ARM DEN0117.
+ *
+ * Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES.
+ *
+ */
+
+#define pr_fmt(fmt)	"ACPI: APMT: " fmt
+
+#include <linux/acpi.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include "init.h"
+
+#define DEV_NAME "arm-cs-arch-pmu"
+
+/* There can be up to 3 resources: page 0 and 1 address, and interrupt. */
+#define DEV_MAX_RESOURCE_COUNT 3
+
+/* Root pointer to the mapped APMT table */
+static struct acpi_table_header *apmt_table;
+
+static int __init apmt_init_resources(struct resource *res,
+				      struct acpi_apmt_node *node)
+{
+	int irq, trigger;
+	int num_res = 0;
+
+	res[num_res].start = node->base_address0;
+	res[num_res].end = node->base_address0 + SZ_4K - 1;
+	res[num_res].flags = IORESOURCE_MEM;
+
+	num_res++;
+
+	if (node->flags & ACPI_APMT_FLAGS_DUAL_PAGE) {
+		res[num_res].start = node->base_address1;
+		res[num_res].end = node->base_address1 + SZ_4K - 1;
+		res[num_res].flags = IORESOURCE_MEM;
+
+		num_res++;
+	}
+
+	if (node->ovflw_irq != 0) {
+		trigger = (node->ovflw_irq_flags & ACPI_APMT_OVFLW_IRQ_FLAGS_MODE);
+		trigger = (trigger == ACPI_APMT_OVFLW_IRQ_FLAGS_MODE_LEVEL) ?
+			ACPI_LEVEL_SENSITIVE : ACPI_EDGE_SENSITIVE;
+		irq = acpi_register_gsi(NULL, node->ovflw_irq, trigger,
+						ACPI_ACTIVE_HIGH);
+
+		if (irq <= 0) {
+			pr_warn("APMT could not register gsi hwirq %d\n", irq);
+			return num_res;
+		}
+
+		res[num_res].start = irq;
+		res[num_res].end = irq;
+		res[num_res].flags = IORESOURCE_IRQ;
+
+		num_res++;
+	}
+
+	return num_res;
+}
+
+/**
+ * apmt_add_platform_device() - Allocate a platform device for APMT node
+ * @node: Pointer to device ACPI APMT node
+ * @fwnode: fwnode associated with the APMT node
+ *
+ * Returns: 0 on success, <0 failure
+ */
+static int __init apmt_add_platform_device(struct acpi_apmt_node *node,
+					   struct fwnode_handle *fwnode)
+{
+	struct platform_device *pdev;
+	int ret, count;
+	struct resource res[DEV_MAX_RESOURCE_COUNT];
+
+	pdev = platform_device_alloc(DEV_NAME, PLATFORM_DEVID_AUTO);
+	if (!pdev)
+		return -ENOMEM;
+
+	memset(res, 0, sizeof(res));
+
+	count = apmt_init_resources(res, node);
+
+	ret = platform_device_add_resources(pdev, res, count);
+	if (ret)
+		goto dev_put;
+
+	/*
+	 * Add a copy of APMT node pointer to platform_data to be used to
+	 * retrieve APMT data information.
+	 */
+	ret = platform_device_add_data(pdev, &node, sizeof(node));
+	if (ret)
+		goto dev_put;
+
+	pdev->dev.fwnode = fwnode;
+
+	ret = platform_device_add(pdev);
+
+	if (ret)
+		goto dev_put;
+
+	return 0;
+
+dev_put:
+	platform_device_put(pdev);
+
+	return ret;
+}
+
+static int __init apmt_init_platform_devices(void)
+{
+	struct acpi_apmt_node *apmt_node;
+	struct acpi_table_apmt *apmt;
+	struct fwnode_handle *fwnode;
+	u64 offset, end;
+	int ret;
+
+	/*
+	 * apmt_table and apmt both point to the start of APMT table, but
+	 * have different struct types
+	 */
+	apmt = (struct acpi_table_apmt *)apmt_table;
+	offset = sizeof(*apmt);
+	end = apmt->header.length;
+
+	while (offset < end) {
+		apmt_node = ACPI_ADD_PTR(struct acpi_apmt_node, apmt,
+				 offset);
+
+		fwnode = acpi_alloc_fwnode_static();
+		if (!fwnode)
+			return -ENOMEM;
+
+		ret = apmt_add_platform_device(apmt_node, fwnode);
+		if (ret) {
+			acpi_free_fwnode_static(fwnode);
+			return ret;
+		}
+
+		offset += apmt_node->length;
+	}
+
+	return 0;
+}
+
+void __init acpi_apmt_init(void)
+{
+	acpi_status status;
+	int ret;
+
+	/**
+	 * APMT table nodes will be used at runtime after the apmt init,
+	 * so we don't need to call acpi_put_table() to release
+	 * the APMT table mapping.
+	 */
+	status = acpi_get_table(ACPI_SIG_APMT, 0, &apmt_table);
+
+	if (ACPI_FAILURE(status)) {
+		if (status != AE_NOT_FOUND) {
+			const char *msg = acpi_format_exception(status);
+
+			pr_err("Failed to get APMT table, %s\n", msg);
+		}
+
+		return;
+	}
+
+	ret = apmt_init_platform_devices();
+	if (ret) {
+		pr_err("Failed to initialize APMT platform devices, ret: %d\n", ret);
+		acpi_put_table(apmt_table);
+	}
+}
diff --git a/drivers/acpi/arm64/cpuidle.c b/drivers/acpi/arm64/cpuidle.c
new file mode 100644
index 000000000000..801f9c450142
--- /dev/null
+++ b/drivers/acpi/arm64/cpuidle.c
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * ARM64 CPU idle arch support
+ *
+ * Copyright (C) 2014 ARM Ltd.
+ * Author: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+ */
+
+#include <linux/acpi.h>
+#include <linux/cpuidle.h>
+#include <linux/cpu_pm.h>
+#include <linux/psci.h>
+#include <acpi/processor.h>
+
+#define ARM64_LPI_IS_RETENTION_STATE(arch_flags) (!(arch_flags))
+
+static int psci_acpi_cpu_init_idle(unsigned int cpu)
+{
+	int i, count;
+	struct acpi_lpi_state *lpi;
+	struct acpi_processor *pr = per_cpu(processors, cpu);
+
+	if (unlikely(!pr || !pr->flags.has_lpi))
+		return -EINVAL;
+
+	/*
+	 * If the PSCI cpu_suspend function hook has not been initialized
+	 * idle states must not be enabled, so bail out
+	 */
+	if (!psci_ops.cpu_suspend)
+		return -EOPNOTSUPP;
+
+	count = pr->power.count - 1;
+	if (count <= 0)
+		return -ENODEV;
+
+	for (i = 0; i < count; i++) {
+		u32 state;
+
+		lpi = &pr->power.lpi_states[i + 1];
+		/*
+		 * Only bits[31:0] represent a PSCI power_state while
+		 * bits[63:32] must be 0x0 as per ARM ACPI FFH Specification
+		 */
+		state = lpi->address;
+		if (!psci_power_state_is_valid(state)) {
+			pr_warn("Invalid PSCI power state %#x\n", state);
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
+int acpi_processor_ffh_lpi_probe(unsigned int cpu)
+{
+	return psci_acpi_cpu_init_idle(cpu);
+}
+
+__cpuidle int acpi_processor_ffh_lpi_enter(struct acpi_lpi_state *lpi)
+{
+	u32 state = lpi->address;
+
+	if (ARM64_LPI_IS_RETENTION_STATE(lpi->arch_flags))
+		return CPU_PM_CPU_IDLE_ENTER_RETENTION_PARAM_RCU(psci_cpu_suspend_enter,
+						lpi->index, state);
+	else
+		return CPU_PM_CPU_IDLE_ENTER_PARAM_RCU(psci_cpu_suspend_enter,
+					     lpi->index, state);
+}
diff --git a/drivers/acpi/arm64/dma.c b/drivers/acpi/arm64/dma.c
new file mode 100644
index 000000000000..f30f138352b7
--- /dev/null
+++ b/drivers/acpi/arm64/dma.c
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include <linux/acpi.h>
+#include <linux/acpi_iort.h>
+#include <linux/device.h>
+#include <linux/dma-direct.h>
+
+void acpi_arch_dma_setup(struct device *dev)
+{
+	int ret;
+	u64 end, mask;
+	const struct bus_dma_region *map = NULL;
+
+	/*
+	 * If @dev is expected to be DMA-capable then the bus code that created
+	 * it should have initialised its dma_mask pointer by this point. For
+	 * now, we'll continue the legacy behaviour of coercing it to the
+	 * coherent mask if not, but we'll no longer do so quietly.
+	 */
+	if (!dev->dma_mask) {
+		dev_warn(dev, "DMA mask not set\n");
+		dev->dma_mask = &dev->coherent_dma_mask;
+	}
+
+	if (dev->coherent_dma_mask)
+		end = dev->coherent_dma_mask;
+	else
+		end = (1ULL << 32) - 1;
+
+	if (dev->dma_range_map) {
+		dev_dbg(dev, "dma_range_map already set\n");
+		return;
+	}
+
+	ret = acpi_dma_get_range(dev, &map);
+	if (!ret && map) {
+		end = dma_range_map_max(map);
+		dev->dma_range_map = map;
+	}
+
+	if (ret == -ENODEV)
+		ret = iort_dma_get_ranges(dev, &end);
+	if (!ret) {
+		/*
+		 * Limit coherent and dma mask based on size retrieved from
+		 * firmware.
+		 */
+		mask = DMA_BIT_MASK(ilog2(end) + 1);
+		dev->bus_dma_limit = end;
+		dev->coherent_dma_mask = min(dev->coherent_dma_mask, mask);
+		*dev->dma_mask = min(*dev->dma_mask, mask);
+	}
+}
diff --git a/drivers/acpi/arm64/ffh.c b/drivers/acpi/arm64/ffh.c
new file mode 100644
index 000000000000..877edc6557e9
--- /dev/null
+++ b/drivers/acpi/arm64/ffh.c
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include <linux/acpi.h>
+#include <linux/arm-smccc.h>
+#include <linux/slab.h>
+
+/*
+ * Implements ARM64 specific callbacks to support ACPI FFH Operation Region as
+ * specified in https://developer.arm.com/docs/den0048/latest
+ */
+struct acpi_ffh_data {
+	struct acpi_ffh_info info;
+	void (*invoke_ffh_fn)(unsigned long a0, unsigned long a1,
+			      unsigned long a2, unsigned long a3,
+			      unsigned long a4, unsigned long a5,
+			      unsigned long a6, unsigned long a7,
+			      struct arm_smccc_res *args,
+			      struct arm_smccc_quirk *res);
+	void (*invoke_ffh64_fn)(const struct arm_smccc_1_2_regs *args,
+				struct arm_smccc_1_2_regs *res);
+};
+
+int acpi_ffh_address_space_arch_setup(void *handler_ctxt, void **region_ctxt)
+{
+	enum arm_smccc_conduit conduit;
+	struct acpi_ffh_data *ffh_ctxt;
+
+	if (arm_smccc_get_version() < ARM_SMCCC_VERSION_1_2)
+		return -EOPNOTSUPP;
+
+	conduit = arm_smccc_1_1_get_conduit();
+	if (conduit == SMCCC_CONDUIT_NONE) {
+		pr_err("%s: invalid SMCCC conduit\n", __func__);
+		return -EOPNOTSUPP;
+	}
+
+	ffh_ctxt = kzalloc(sizeof(*ffh_ctxt), GFP_KERNEL);
+	if (!ffh_ctxt)
+		return -ENOMEM;
+
+	if (conduit == SMCCC_CONDUIT_SMC) {
+		ffh_ctxt->invoke_ffh_fn = __arm_smccc_smc;
+		ffh_ctxt->invoke_ffh64_fn = arm_smccc_1_2_smc;
+	} else {
+		ffh_ctxt->invoke_ffh_fn = __arm_smccc_hvc;
+		ffh_ctxt->invoke_ffh64_fn = arm_smccc_1_2_hvc;
+	}
+
+	memcpy(ffh_ctxt, handler_ctxt, sizeof(ffh_ctxt->info));
+
+	*region_ctxt = ffh_ctxt;
+	return AE_OK;
+}
+
+static bool acpi_ffh_smccc_owner_allowed(u32 fid)
+{
+	int owner = ARM_SMCCC_OWNER_NUM(fid);
+
+	if (owner == ARM_SMCCC_OWNER_STANDARD ||
+	    owner == ARM_SMCCC_OWNER_SIP || owner == ARM_SMCCC_OWNER_OEM)
+		return true;
+
+	return false;
+}
+
+int acpi_ffh_address_space_arch_handler(acpi_integer *value, void *region_context)
+{
+	int ret = 0;
+	struct acpi_ffh_data *ffh_ctxt = region_context;
+
+	if (ffh_ctxt->info.offset == 0) {
+		/* SMC/HVC 32bit call */
+		struct arm_smccc_res res;
+		u32 a[8] = { 0 }, *ptr = (u32 *)value;
+
+		if (!ARM_SMCCC_IS_FAST_CALL(*ptr) || ARM_SMCCC_IS_64(*ptr) ||
+		    !acpi_ffh_smccc_owner_allowed(*ptr) ||
+		    ffh_ctxt->info.length > 32) {
+			ret = AE_ERROR;
+		} else {
+			int idx, len = ffh_ctxt->info.length >> 2;
+
+			for (idx = 0; idx < len; idx++)
+				a[idx] = *(ptr + idx);
+
+			ffh_ctxt->invoke_ffh_fn(a[0], a[1], a[2], a[3], a[4],
+						a[5], a[6], a[7], &res, NULL);
+			memcpy(value, &res, sizeof(res));
+		}
+
+	} else if (ffh_ctxt->info.offset == 1) {
+		/* SMC/HVC 64bit call */
+		struct arm_smccc_1_2_regs *r = (struct arm_smccc_1_2_regs *)value;
+
+		if (!ARM_SMCCC_IS_FAST_CALL(r->a0) || !ARM_SMCCC_IS_64(r->a0) ||
+		    !acpi_ffh_smccc_owner_allowed(r->a0) ||
+		    ffh_ctxt->info.length > sizeof(*r)) {
+			ret = AE_ERROR;
+		} else {
+			ffh_ctxt->invoke_ffh64_fn(r, r);
+			memcpy(value, r, ffh_ctxt->info.length);
+		}
+	} else {
+		ret = AE_ERROR;
+	}
+
+	return ret;
+}
diff --git a/drivers/acpi/arm64/gtdt.c b/drivers/acpi/arm64/gtdt.c
index f2d0e5915dab..ffc867bac2d6 100644
--- a/drivers/acpi/arm64/gtdt.c
+++ b/drivers/acpi/arm64/gtdt.c
@@ -36,19 +36,25 @@ struct acpi_gtdt_descriptor {
 
 static struct acpi_gtdt_descriptor acpi_gtdt_desc __initdata;
 
-static inline void *next_platform_timer(void *platform_timer)
+static __init bool platform_timer_valid(void *platform_timer)
 {
 	struct acpi_gtdt_header *gh = platform_timer;
 
-	platform_timer += gh->length;
-	if (platform_timer < acpi_gtdt_desc.gtdt_end)
-		return platform_timer;
+	return (platform_timer >= (void *)(acpi_gtdt_desc.gtdt + 1) &&
+		platform_timer < acpi_gtdt_desc.gtdt_end &&
+		gh->length != 0 &&
+		platform_timer + gh->length <= acpi_gtdt_desc.gtdt_end);
+}
+
+static __init void *next_platform_timer(void *platform_timer)
+{
+	struct acpi_gtdt_header *gh = platform_timer;
 
-	return NULL;
+	return platform_timer + gh->length;
 }
 
 #define for_each_platform_timer(_g)				\
-	for (_g = acpi_gtdt_desc.platform_timer; _g;	\
+	for (_g = acpi_gtdt_desc.platform_timer; platform_timer_valid(_g);\
 	     _g = next_platform_timer(_g))
 
 static inline bool is_timer_block(void *platform_timer)
@@ -157,6 +163,7 @@ int __init acpi_gtdt_init(struct acpi_table_header *table,
 {
 	void *platform_timer;
 	struct acpi_table_gtdt *gtdt;
+	u32 cnt = 0;
 
 	gtdt = container_of(table, struct acpi_table_gtdt, header);
 	acpi_gtdt_desc.gtdt = gtdt;
@@ -176,14 +183,22 @@ int __init acpi_gtdt_init(struct acpi_table_header *table,
 		return 0;
 	}
 
-	platform_timer = (void *)gtdt + gtdt->platform_timer_offset;
-	if (platform_timer < (void *)table + sizeof(struct acpi_table_gtdt)) {
-		pr_err(FW_BUG "invalid timer data.\n");
-		return -EINVAL;
+	acpi_gtdt_desc.platform_timer = (void *)gtdt + gtdt->platform_timer_offset;
+	for_each_platform_timer(platform_timer)
+		cnt++;
+
+	if (cnt != gtdt->platform_timer_count) {
+		cnt = min(cnt, gtdt->platform_timer_count);
+		pr_err(FW_BUG "limiting Platform Timer count to %d\n", cnt);
 	}
-	acpi_gtdt_desc.platform_timer = platform_timer;
+
+	if (!cnt) {
+		acpi_gtdt_desc.platform_timer = NULL;
+		return 0;
+	}
+
 	if (platform_timer_count)
-		*platform_timer_count = gtdt->platform_timer_count;
+		*platform_timer_count = cnt;
 
 	return 0;
 }
@@ -283,45 +298,11 @@ error:
 		if (frame->virt_irq > 0)
 			acpi_unregister_gsi(gtdt_frame->virtual_timer_interrupt);
 		frame->virt_irq = 0;
-	} while (i-- >= 0 && gtdt_frame--);
+	} while (i-- > 0 && gtdt_frame--);
 
 	return -EINVAL;
 }
 
-/**
- * acpi_arch_timer_mem_init() - Get the info of all GT blocks in GTDT table.
- * @timer_mem:	The pointer to the array of struct arch_timer_mem for returning
- *		the result of parsing. The element number of this array should
- *		be platform_timer_count(the total number of platform timers).
- * @timer_count: It points to a integer variable which is used for storing the
- *		number of GT blocks we have parsed.
- *
- * Return: 0 if success, -EINVAL/-ENODEV if error.
- */
-int __init acpi_arch_timer_mem_init(struct arch_timer_mem *timer_mem,
-				    int *timer_count)
-{
-	int ret;
-	void *platform_timer;
-
-	*timer_count = 0;
-	for_each_platform_timer(platform_timer) {
-		if (is_timer_block(platform_timer)) {
-			ret = gtdt_parse_timer_block(platform_timer, timer_mem);
-			if (ret)
-				return ret;
-			timer_mem++;
-			(*timer_count)++;
-		}
-	}
-
-	if (*timer_count)
-		pr_info("found %d memory-mapped timer block(s).\n",
-			*timer_count);
-
-	return 0;
-}
-
 /*
  * Initialize a SBSA generic Watchdog platform device info from GTDT
  */
@@ -329,7 +310,7 @@ static int __init gtdt_import_sbsa_gwdt(struct acpi_gtdt_watchdog *wd,
 					int index)
 {
 	struct platform_device *pdev;
-	int irq = map_gt_gsi(wd->timer_interrupt, wd->timer_flags);
+	int irq;
 
 	/*
 	 * According to SBSA specification the size of refresh and control
@@ -338,7 +319,7 @@ static int __init gtdt_import_sbsa_gwdt(struct acpi_gtdt_watchdog *wd,
 	struct resource res[] = {
 		DEFINE_RES_MEM(wd->control_frame_address, SZ_4K),
 		DEFINE_RES_MEM(wd->refresh_frame_address, SZ_4K),
-		DEFINE_RES_IRQ(irq),
+		{},
 	};
 	int nr_res = ARRAY_SIZE(res);
 
@@ -348,10 +329,11 @@ static int __init gtdt_import_sbsa_gwdt(struct acpi_gtdt_watchdog *wd,
 
 	if (!(wd->refresh_frame_address && wd->control_frame_address)) {
 		pr_err(FW_BUG "failed to get the Watchdog base address.\n");
-		acpi_unregister_gsi(wd->timer_interrupt);
 		return -EINVAL;
 	}
 
+	irq = map_gt_gsi(wd->timer_interrupt, wd->timer_flags);
+	res[2] = DEFINE_RES_IRQ(irq);
 	if (irq <= 0) {
 		pr_warn("failed to map the Watchdog interrupt.\n");
 		nr_res--;
@@ -364,18 +346,19 @@ static int __init gtdt_import_sbsa_gwdt(struct acpi_gtdt_watchdog *wd,
 	 */
 	pdev = platform_device_register_simple("sbsa-gwdt", index, res, nr_res);
 	if (IS_ERR(pdev)) {
-		acpi_unregister_gsi(wd->timer_interrupt);
+		if (irq > 0)
+			acpi_unregister_gsi(wd->timer_interrupt);
 		return PTR_ERR(pdev);
 	}
 
 	return 0;
 }
 
-static int __init gtdt_sbsa_gwdt_init(void)
+static int __init gtdt_platform_timer_init(void)
 {
 	void *platform_timer;
 	struct acpi_table_header *table;
-	int ret, timer_count, gwdt_count = 0;
+	int ret, timer_count, gwdt_count = 0, mmio_timer_count = 0;
 
 	if (acpi_disabled)
 		return 0;
@@ -397,20 +380,41 @@ static int __init gtdt_sbsa_gwdt_init(void)
 		goto out_put_gtdt;
 
 	for_each_platform_timer(platform_timer) {
+		ret = 0;
+
 		if (is_non_secure_watchdog(platform_timer)) {
 			ret = gtdt_import_sbsa_gwdt(platform_timer, gwdt_count);
 			if (ret)
-				break;
+				continue;
 			gwdt_count++;
+		} else 	if (is_timer_block(platform_timer)) {
+			struct arch_timer_mem atm = {};
+			struct platform_device *pdev;
+
+			ret = gtdt_parse_timer_block(platform_timer, &atm);
+			if (ret)
+				continue;
+
+			pdev = platform_device_register_data(NULL, "gtdt-arm-mmio-timer",
+							     mmio_timer_count, &atm,
+							     sizeof(atm));
+			if (IS_ERR(pdev)) {
+				pr_err("Can't register timer %d\n", mmio_timer_count);
+				continue;
+			}
+
+			mmio_timer_count++;
 		}
 	}
 
 	if (gwdt_count)
 		pr_info("found %d SBSA generic Watchdog(s).\n", gwdt_count);
+	if (mmio_timer_count)
+		pr_info("found %d Generic MMIO timer(s).\n", mmio_timer_count);
 
 out_put_gtdt:
 	acpi_put_table(table);
 	return ret;
 }
 
-device_initcall(gtdt_sbsa_gwdt_init);
+device_initcall(gtdt_platform_timer_init);
diff --git a/drivers/acpi/arm64/init.c b/drivers/acpi/arm64/init.c
new file mode 100644
index 000000000000..7a47d8095a7d
--- /dev/null
+++ b/drivers/acpi/arm64/init.c
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include <linux/acpi.h>
+#include "init.h"
+
+void __init acpi_arch_init(void)
+{
+	if (IS_ENABLED(CONFIG_ACPI_AGDI))
+		acpi_agdi_init();
+	if (IS_ENABLED(CONFIG_ACPI_APMT))
+		acpi_apmt_init();
+	if (IS_ENABLED(CONFIG_ACPI_IORT))
+		acpi_iort_init();
+	if (IS_ENABLED(CONFIG_ARM_AMBA))
+		acpi_amba_init();
+}
diff --git a/drivers/acpi/arm64/init.h b/drivers/acpi/arm64/init.h
new file mode 100644
index 000000000000..dcc277977194
--- /dev/null
+++ b/drivers/acpi/arm64/init.h
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#include <linux/init.h>
+
+void __init acpi_agdi_init(void);
+void __init acpi_apmt_init(void);
+void __init acpi_iort_init(void);
+void __init acpi_amba_init(void);
diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c
index 6e445bc55537..65f0f56ad753 100644
--- a/drivers/acpi/arm64/iort.c
+++ b/drivers/acpi/arm64/iort.c
@@ -18,6 +18,8 @@
 #include <linux/pci.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
+#include <linux/dma-map-ops.h>
+#include "init.h"
 
 #define IORT_TYPE_MASK(type)	(1 << (type))
 #define IORT_MSI_TYPE		(1 << ACPI_IORT_NODE_ITS_GROUP)
@@ -43,7 +45,7 @@ static DEFINE_SPINLOCK(iort_fwnode_lock);
  * iort_set_fwnode() - Create iort_fwnode and use it to register
  *		       iommu data in the iort_fwnode_list
  *
- * @node: IORT table node associated with the IOMMU
+ * @iort_node: IORT table node associated with the IOMMU
  * @fwnode: fwnode associated with the IORT node
  *
  * Returns: 0 on success
@@ -264,15 +266,31 @@ static acpi_status iort_match_node_callback(struct acpi_iort_node *node,
 
 	if (node->type == ACPI_IORT_NODE_NAMED_COMPONENT) {
 		struct acpi_buffer buf = { ACPI_ALLOCATE_BUFFER, NULL };
-		struct acpi_device *adev = to_acpi_device_node(dev->fwnode);
+		struct acpi_device *adev;
 		struct acpi_iort_named_component *ncomp;
+		struct device *nc_dev = dev;
+
+		/*
+		 * Walk the device tree to find a device with an
+		 * ACPI companion; there is no point in scanning
+		 * IORT for a device matching a named component if
+		 * the device does not have an ACPI companion to
+		 * start with.
+		 */
+		do {
+			adev = ACPI_COMPANION(nc_dev);
+			if (adev)
+				break;
+
+			nc_dev = nc_dev->parent;
+		} while (nc_dev);
 
 		if (!adev)
 			goto out;
 
 		status = acpi_get_name(adev->handle, ACPI_FULL_PATHNAME, &buf);
 		if (ACPI_FAILURE(status)) {
-			dev_warn(dev, "Can't get device full path name\n");
+			dev_warn(nc_dev, "Can't get device full path name\n");
 			goto out;
 		}
 
@@ -385,9 +403,14 @@ static struct acpi_iort_node *iort_node_get_id(struct acpi_iort_node *node,
 	return NULL;
 }
 
+#ifndef ACPI_IORT_SMMU_V3_DEVICEID_VALID
+#define ACPI_IORT_SMMU_V3_DEVICEID_VALID (1 << 4)
+#endif
+
 static int iort_get_id_mapping_index(struct acpi_iort_node *node)
 {
 	struct acpi_iort_smmu_v3 *smmu;
+	struct acpi_iort_pmcg *pmcg;
 
 	switch (node->type) {
 	case ACPI_IORT_NODE_SMMU_V3:
@@ -400,12 +423,16 @@ static int iort_get_id_mapping_index(struct acpi_iort_node *node)
 
 		smmu = (struct acpi_iort_smmu_v3 *)node->node_data;
 		/*
-		 * ID mapping index is only ignored if all interrupts are
-		 * GSIV based
+		 * Until IORT E.e (node rev. 5), the ID mapping index was
+		 * defined to be valid unless all interrupts are GSIV-based.
 		 */
-		if (smmu->event_gsiv && smmu->pri_gsiv && smmu->gerr_gsiv
-		    && smmu->sync_gsiv)
+		if (node->revision < 5) {
+			if (smmu->event_gsiv && smmu->pri_gsiv &&
+			    smmu->gerr_gsiv && smmu->sync_gsiv)
+				return -EINVAL;
+		} else if (!(smmu->flags & ACPI_IORT_SMMU_V3_DEVICEID_VALID)) {
 			return -EINVAL;
+		}
 
 		if (smmu->id_mapping_index >= node->mapping_count) {
 			pr_err(FW_BUG "[node %p type %d] ID mapping index overflows valid mappings\n",
@@ -415,6 +442,10 @@ static int iort_get_id_mapping_index(struct acpi_iort_node *node)
 
 		return smmu->id_mapping_index;
 	case ACPI_IORT_NODE_PMCG:
+		pmcg = (struct acpi_iort_pmcg *)node->node_data;
+		if (pmcg->overflow_gsiv || node->mapping_count == 0)
+			return -EINVAL;
+
 		return 0;
 	default:
 		return -EINVAL;
@@ -529,7 +560,6 @@ static struct acpi_iort_node *iort_find_dev_node(struct device *dev)
 		node = iort_get_iort_node(dev->fwnode);
 		if (node)
 			return node;
-
 		/*
 		 * if not, then it should be a platform device defined in
 		 * DSDT/SSDT (with Named Component node in IORT)
@@ -538,32 +568,29 @@ static struct acpi_iort_node *iort_find_dev_node(struct device *dev)
 				      iort_match_node_callback, dev);
 	}
 
-	/* Find a PCI root bus */
 	pbus = to_pci_dev(dev)->bus;
-	while (!pci_is_root_bus(pbus))
-		pbus = pbus->parent;
 
 	return iort_scan_node(ACPI_IORT_NODE_PCI_ROOT_COMPLEX,
 			      iort_match_node_callback, &pbus->dev);
 }
 
 /**
- * iort_msi_map_rid() - Map a MSI requester ID for a device
+ * iort_msi_map_id() - Map a MSI input ID for a device
  * @dev: The device for which the mapping is to be done.
- * @req_id: The device requester ID.
+ * @input_id: The device input ID.
  *
- * Returns: mapped MSI RID on success, input requester ID otherwise
+ * Returns: mapped MSI ID on success, input ID otherwise
  */
-u32 iort_msi_map_rid(struct device *dev, u32 req_id)
+u32 iort_msi_map_id(struct device *dev, u32 input_id)
 {
 	struct acpi_iort_node *node;
 	u32 dev_id;
 
 	node = iort_find_dev_node(dev);
 	if (!node)
-		return req_id;
+		return input_id;
 
-	iort_node_map_id(node, req_id, &dev_id, IORT_MSI_TYPE);
+	iort_node_map_id(node, input_id, &dev_id, IORT_MSI_TYPE);
 	return dev_id;
 }
 
@@ -620,13 +647,13 @@ static int __maybe_unused iort_find_its_base(u32 its_id, phys_addr_t *base)
 /**
  * iort_dev_find_its_id() - Find the ITS identifier for a device
  * @dev: The device.
- * @req_id: Device's requester ID
+ * @id: Device's ID
  * @idx: Index of the ITS identifier list.
  * @its_id: ITS identifier.
  *
  * Returns: 0 on success, appropriate error value otherwise
  */
-static int iort_dev_find_its_id(struct device *dev, u32 req_id,
+static int iort_dev_find_its_id(struct device *dev, u32 id,
 				unsigned int idx, int *its_id)
 {
 	struct acpi_iort_its_group *its;
@@ -636,7 +663,7 @@ static int iort_dev_find_its_id(struct device *dev, u32 req_id,
 	if (!node)
 		return -ENXIO;
 
-	node = iort_node_map_id(node, req_id, NULL, IORT_MSI_TYPE);
+	node = iort_node_map_id(node, id, NULL, IORT_MSI_TYPE);
 	if (!node)
 		return -ENXIO;
 
@@ -655,23 +682,25 @@ static int iort_dev_find_its_id(struct device *dev, u32 req_id,
 /**
  * iort_get_device_domain() - Find MSI domain related to a device
  * @dev: The device.
- * @req_id: Requester ID for the device.
+ * @id: Requester ID for the device.
+ * @bus_token: irq domain bus token.
  *
  * Returns: the MSI domain for this device, NULL otherwise
  */
-struct irq_domain *iort_get_device_domain(struct device *dev, u32 req_id)
+struct irq_domain *iort_get_device_domain(struct device *dev, u32 id,
+					  enum irq_domain_bus_token bus_token)
 {
 	struct fwnode_handle *handle;
 	int its_id;
 
-	if (iort_dev_find_its_id(dev, req_id, 0, &its_id))
+	if (iort_dev_find_its_id(dev, id, 0, &its_id))
 		return NULL;
 
 	handle = iort_find_domain_token(its_id);
 	if (!handle)
 		return NULL;
 
-	return irq_find_matching_fwnode(handle, DOMAIN_BUS_PCI_MSI);
+	return irq_find_matching_fwnode(handle, bus_token);
 }
 
 static void iort_set_device_domain(struct device *dev,
@@ -767,73 +796,328 @@ void acpi_configure_pmsi_domain(struct device *dev)
 		dev_set_msi_domain(dev, msi_domain);
 }
 
-static int __maybe_unused __get_pci_rid(struct pci_dev *pdev, u16 alias,
-					void *data)
+#ifdef CONFIG_IOMMU_API
+static void iort_rmr_free(struct device *dev,
+			  struct iommu_resv_region *region)
 {
-	u32 *rid = data;
+	struct iommu_iort_rmr_data *rmr_data;
 
-	*rid = alias;
-	return 0;
+	rmr_data = container_of(region, struct iommu_iort_rmr_data, rr);
+	kfree(rmr_data->sids);
+	kfree(rmr_data);
 }
 
-#ifdef CONFIG_IOMMU_API
-static struct acpi_iort_node *iort_get_msi_resv_iommu(struct device *dev)
+static struct iommu_iort_rmr_data *iort_rmr_alloc(
+					struct acpi_iort_rmr_desc *rmr_desc,
+					int prot, enum iommu_resv_type type,
+					u32 *sids, u32 num_sids)
 {
-	struct acpi_iort_node *iommu;
-	struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
+	struct iommu_iort_rmr_data *rmr_data;
+	struct iommu_resv_region *region;
+	u32 *sids_copy;
+	u64 addr = rmr_desc->base_address, size = rmr_desc->length;
 
-	iommu = iort_get_iort_node(fwspec->iommu_fwnode);
+	rmr_data = kmalloc(sizeof(*rmr_data), GFP_KERNEL);
+	if (!rmr_data)
+		return NULL;
 
-	if (iommu && (iommu->type == ACPI_IORT_NODE_SMMU_V3)) {
-		struct acpi_iort_smmu_v3 *smmu;
+	/* Create a copy of SIDs array to associate with this rmr_data */
+	sids_copy = kmemdup_array(sids, num_sids, sizeof(*sids), GFP_KERNEL);
+	if (!sids_copy) {
+		kfree(rmr_data);
+		return NULL;
+	}
+	rmr_data->sids = sids_copy;
+	rmr_data->num_sids = num_sids;
+
+	if (!IS_ALIGNED(addr, SZ_64K) || !IS_ALIGNED(size, SZ_64K)) {
+		/* PAGE align base addr and size */
+		addr &= PAGE_MASK;
+		size = PAGE_ALIGN(size + offset_in_page(rmr_desc->base_address));
+
+		pr_err(FW_BUG "RMR descriptor[0x%llx - 0x%llx] not aligned to 64K, continue with [0x%llx - 0x%llx]\n",
+		       rmr_desc->base_address,
+		       rmr_desc->base_address + rmr_desc->length - 1,
+		       addr, addr + size - 1);
+	}
 
-		smmu = (struct acpi_iort_smmu_v3 *)iommu->node_data;
-		if (smmu->model == ACPI_IORT_SMMU_V3_HISILICON_HI161X)
-			return iommu;
+	region = &rmr_data->rr;
+	INIT_LIST_HEAD(&region->list);
+	region->start = addr;
+	region->length = size;
+	region->prot = prot;
+	region->type = type;
+	region->free = iort_rmr_free;
+
+	return rmr_data;
+}
+
+static void iort_rmr_desc_check_overlap(struct acpi_iort_rmr_desc *desc,
+					u32 count)
+{
+	int i, j;
+
+	for (i = 0; i < count; i++) {
+		u64 end, start = desc[i].base_address, length = desc[i].length;
+
+		if (!length) {
+			pr_err(FW_BUG "RMR descriptor[0x%llx] with zero length, continue anyway\n",
+			       start);
+			continue;
+		}
+
+		end = start + length - 1;
+
+		/* Check for address overlap */
+		for (j = i + 1; j < count; j++) {
+			u64 e_start = desc[j].base_address;
+			u64 e_end = e_start + desc[j].length - 1;
+
+			if (start <= e_end && end >= e_start)
+				pr_err(FW_BUG "RMR descriptor[0x%llx - 0x%llx] overlaps, continue anyway\n",
+				       start, end);
+		}
 	}
+}
 
-	return NULL;
+/*
+ * Please note, we will keep the already allocated RMR reserve
+ * regions in case of a memory allocation failure.
+ */
+static void iort_get_rmrs(struct acpi_iort_node *node,
+			  struct acpi_iort_node *smmu,
+			  u32 *sids, u32 num_sids,
+			  struct list_head *head)
+{
+	struct acpi_iort_rmr *rmr = (struct acpi_iort_rmr *)node->node_data;
+	struct acpi_iort_rmr_desc *rmr_desc;
+	int i;
+
+	rmr_desc = ACPI_ADD_PTR(struct acpi_iort_rmr_desc, node,
+				rmr->rmr_offset);
+
+	iort_rmr_desc_check_overlap(rmr_desc, rmr->rmr_count);
+
+	for (i = 0; i < rmr->rmr_count; i++, rmr_desc++) {
+		struct iommu_iort_rmr_data *rmr_data;
+		enum iommu_resv_type type;
+		int prot = IOMMU_READ | IOMMU_WRITE;
+
+		if (rmr->flags & ACPI_IORT_RMR_REMAP_PERMITTED)
+			type = IOMMU_RESV_DIRECT_RELAXABLE;
+		else
+			type = IOMMU_RESV_DIRECT;
+
+		if (rmr->flags & ACPI_IORT_RMR_ACCESS_PRIVILEGE)
+			prot |= IOMMU_PRIV;
+
+		/* Attributes 0x00 - 0x03 represents device memory */
+		if (ACPI_IORT_RMR_ACCESS_ATTRIBUTES(rmr->flags) <=
+				ACPI_IORT_RMR_ATTR_DEVICE_GRE)
+			prot |= IOMMU_MMIO;
+		else if (ACPI_IORT_RMR_ACCESS_ATTRIBUTES(rmr->flags) ==
+				ACPI_IORT_RMR_ATTR_NORMAL_IWB_OWB)
+			prot |= IOMMU_CACHE;
+
+		rmr_data = iort_rmr_alloc(rmr_desc, prot, type,
+					  sids, num_sids);
+		if (!rmr_data)
+			return;
+
+		list_add_tail(&rmr_data->rr.list, head);
+	}
 }
 
-static inline const struct iommu_ops *iort_fwspec_iommu_ops(struct device *dev)
+static u32 *iort_rmr_alloc_sids(u32 *sids, u32 count, u32 id_start,
+				u32 new_count)
 {
+	u32 *new_sids;
+	u32 total_count = count + new_count;
+	int i;
+
+	new_sids = krealloc_array(sids, count + new_count,
+				  sizeof(*new_sids), GFP_KERNEL);
+	if (!new_sids) {
+		kfree(sids);
+		return NULL;
+	}
+
+	for (i = count; i < total_count; i++)
+		new_sids[i] = id_start++;
+
+	return new_sids;
+}
+
+static bool iort_rmr_has_dev(struct device *dev, u32 id_start,
+			     u32 id_count)
+{
+	int i;
 	struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 
-	return (fwspec && fwspec->ops) ? fwspec->ops : NULL;
+	/*
+	 * Make sure the kernel has preserved the boot firmware PCIe
+	 * configuration. This is required to ensure that the RMR PCIe
+	 * StreamIDs are still valid (Refer: ARM DEN 0049E.d Section 3.1.1.5).
+	 */
+	if (dev_is_pci(dev)) {
+		struct pci_dev *pdev = to_pci_dev(dev);
+		struct pci_host_bridge *host = pci_find_host_bridge(pdev->bus);
+
+		if (!host->preserve_config)
+			return false;
+	}
+
+	for (i = 0; i < fwspec->num_ids; i++) {
+		if (fwspec->ids[i] >= id_start &&
+		    fwspec->ids[i] <= id_start + id_count)
+			return true;
+	}
+
+	return false;
 }
 
-static inline int iort_add_device_replay(const struct iommu_ops *ops,
-					 struct device *dev)
+static void iort_node_get_rmr_info(struct acpi_iort_node *node,
+				   struct acpi_iort_node *iommu,
+				   struct device *dev, struct list_head *head)
 {
-	int err = 0;
+	struct acpi_iort_node *smmu = NULL;
+	struct acpi_iort_rmr *rmr;
+	struct acpi_iort_id_mapping *map;
+	u32 *sids = NULL;
+	u32 num_sids = 0;
+	int i;
+
+	if (!node->mapping_offset || !node->mapping_count) {
+		pr_err(FW_BUG "Invalid ID mapping, skipping RMR node %p\n",
+		       node);
+		return;
+	}
 
-	if (dev->bus && !device_iommu_mapped(dev))
-		err = iommu_probe_device(dev);
+	rmr = (struct acpi_iort_rmr *)node->node_data;
+	if (!rmr->rmr_offset || !rmr->rmr_count)
+		return;
 
-	return err;
+	map = ACPI_ADD_PTR(struct acpi_iort_id_mapping, node,
+			   node->mapping_offset);
+
+	/*
+	 * Go through the ID mappings and see if we have a match for SMMU
+	 * and dev(if !NULL). If found, get the sids for the Node.
+	 * Please note, id_count is equal to the number of IDs  in the
+	 * range minus one.
+	 */
+	for (i = 0; i < node->mapping_count; i++, map++) {
+		struct acpi_iort_node *parent;
+
+		parent = ACPI_ADD_PTR(struct acpi_iort_node, iort_table,
+				      map->output_reference);
+		if (parent != iommu)
+			continue;
+
+		/* If dev is valid, check RMR node corresponds to the dev SID */
+		if (dev && !iort_rmr_has_dev(dev, map->output_base,
+					     map->id_count))
+			continue;
+
+		/* Retrieve SIDs associated with the Node. */
+		sids = iort_rmr_alloc_sids(sids, num_sids, map->output_base,
+					   map->id_count + 1);
+		if (!sids)
+			return;
+
+		num_sids += map->id_count + 1;
+	}
+
+	if (!sids)
+		return;
+
+	iort_get_rmrs(node, smmu, sids, num_sids, head);
+	kfree(sids);
 }
 
-/**
- * iort_iommu_msi_get_resv_regions - Reserved region driver helper
- * @dev: Device from iommu_get_resv_regions()
- * @head: Reserved region list from iommu_get_resv_regions()
- *
- * Returns: Number of msi reserved regions on success (0 if platform
- *          doesn't require the reservation or no associated msi regions),
- *          appropriate error value otherwise. The ITS interrupt translation
- *          spaces (ITS_base + SZ_64K, SZ_64K) associated with the device
- *          are the msi reserved regions.
+static void iort_find_rmrs(struct acpi_iort_node *iommu, struct device *dev,
+			   struct list_head *head)
+{
+	struct acpi_table_iort *iort;
+	struct acpi_iort_node *iort_node, *iort_end;
+	int i;
+
+	/* Only supports ARM DEN 0049E.d onwards */
+	if (iort_table->revision < 5)
+		return;
+
+	iort = (struct acpi_table_iort *)iort_table;
+
+	iort_node = ACPI_ADD_PTR(struct acpi_iort_node, iort,
+				 iort->node_offset);
+	iort_end = ACPI_ADD_PTR(struct acpi_iort_node, iort,
+				iort_table->length);
+
+	for (i = 0; i < iort->node_count; i++) {
+		if (WARN_TAINT(iort_node >= iort_end, TAINT_FIRMWARE_WORKAROUND,
+			       "IORT node pointer overflows, bad table!\n"))
+			return;
+
+		if (iort_node->type == ACPI_IORT_NODE_RMR)
+			iort_node_get_rmr_info(iort_node, iommu, dev, head);
+
+		iort_node = ACPI_ADD_PTR(struct acpi_iort_node, iort_node,
+					 iort_node->length);
+	}
+}
+
+/*
+ * Populate the RMR list associated with a given IOMMU and dev(if provided).
+ * If dev is NULL, the function populates all the RMRs associated with the
+ * given IOMMU.
  */
-int iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head)
+static void iort_iommu_rmr_get_resv_regions(struct fwnode_handle *iommu_fwnode,
+					    struct device *dev,
+					    struct list_head *head)
+{
+	struct acpi_iort_node *iommu;
+
+	iommu = iort_get_iort_node(iommu_fwnode);
+	if (!iommu)
+		return;
+
+	iort_find_rmrs(iommu, dev, head);
+}
+
+static struct acpi_iort_node *iort_get_msi_resv_iommu(struct device *dev)
+{
+	struct acpi_iort_node *iommu;
+	struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
+
+	iommu = iort_get_iort_node(fwspec->iommu_fwnode);
+
+	if (iommu && (iommu->type == ACPI_IORT_NODE_SMMU_V3)) {
+		struct acpi_iort_smmu_v3 *smmu;
+
+		smmu = (struct acpi_iort_smmu_v3 *)iommu->node_data;
+		if (smmu->model == ACPI_IORT_SMMU_V3_HISILICON_HI161X)
+			return iommu;
+	}
+
+	return NULL;
+}
+
+/*
+ * Retrieve platform specific HW MSI reserve regions.
+ * The ITS interrupt translation spaces (ITS_base + SZ_64K, SZ_64K)
+ * associated with the device are the HW MSI reserved regions.
+ */
+static void iort_iommu_msi_get_resv_regions(struct device *dev,
+					    struct list_head *head)
 {
 	struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 	struct acpi_iort_its_group *its;
 	struct acpi_iort_node *iommu_node, *its_node = NULL;
-	int i, resv = 0;
+	int i;
 
 	iommu_node = iort_get_msi_resv_iommu(dev);
 	if (!iommu_node)
-		return 0;
+		return;
 
 	/*
 	 * Current logic to reserve ITS regions relies on HW topologies
@@ -853,7 +1137,7 @@ int iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head)
 	}
 
 	if (!its_node)
-		return 0;
+		return;
 
 	/* Move to ITS specific data */
 	its = (struct acpi_iort_its_group *)its_node->node_data;
@@ -866,16 +1150,54 @@ int iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head)
 			struct iommu_resv_region *region;
 
 			region = iommu_alloc_resv_region(base + SZ_64K, SZ_64K,
-							 prot, IOMMU_RESV_MSI);
-			if (region) {
+							 prot, IOMMU_RESV_MSI,
+							 GFP_KERNEL);
+			if (region)
 				list_add_tail(&region->list, head);
-				resv++;
-			}
 		}
 	}
+}
 
-	return (resv == its->its_count) ? resv : -ENODEV;
+/**
+ * iort_iommu_get_resv_regions - Generic helper to retrieve reserved regions.
+ * @dev: Device from iommu_get_resv_regions()
+ * @head: Reserved region list from iommu_get_resv_regions()
+ */
+void iort_iommu_get_resv_regions(struct device *dev, struct list_head *head)
+{
+	struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
+
+	iort_iommu_msi_get_resv_regions(dev, head);
+	iort_iommu_rmr_get_resv_regions(fwspec->iommu_fwnode, dev, head);
+}
+
+/**
+ * iort_get_rmr_sids - Retrieve IORT RMR node reserved regions with
+ *                     associated StreamIDs information.
+ * @iommu_fwnode: fwnode associated with IOMMU
+ * @head: Resereved region list
+ */
+void iort_get_rmr_sids(struct fwnode_handle *iommu_fwnode,
+		       struct list_head *head)
+{
+	iort_iommu_rmr_get_resv_regions(iommu_fwnode, NULL, head);
 }
+EXPORT_SYMBOL_GPL(iort_get_rmr_sids);
+
+/**
+ * iort_put_rmr_sids - Free memory allocated for RMR reserved regions.
+ * @iommu_fwnode: fwnode associated with IOMMU
+ * @head: Resereved region list
+ */
+void iort_put_rmr_sids(struct fwnode_handle *iommu_fwnode,
+		       struct list_head *head)
+{
+	struct iommu_resv_region *entry, *next;
+
+	list_for_each_entry_safe(entry, next, head, list)
+		entry->free(NULL, entry);
+}
+EXPORT_SYMBOL_GPL(iort_put_rmr_sids);
 
 static inline bool iort_iommu_driver_enabled(u8 type)
 {
@@ -890,33 +1212,32 @@ static inline bool iort_iommu_driver_enabled(u8 type)
 	}
 }
 
-static int arm_smmu_iort_xlate(struct device *dev, u32 streamid,
-			       struct fwnode_handle *fwnode,
-			       const struct iommu_ops *ops)
+static bool iort_pci_rc_supports_ats(struct acpi_iort_node *node)
 {
-	int ret = iommu_fwspec_init(dev, fwnode, ops);
-
-	if (!ret)
-		ret = iommu_fwspec_add_ids(dev, &streamid, 1);
+	struct acpi_iort_root_complex *pci_rc;
 
-	return ret;
+	pci_rc = (struct acpi_iort_root_complex *)node->node_data;
+	return pci_rc->ats_attribute & ACPI_IORT_ATS_SUPPORTED;
 }
 
-static bool iort_pci_rc_supports_ats(struct acpi_iort_node *node)
+static bool iort_pci_rc_supports_canwbs(struct acpi_iort_node *node)
 {
+	struct acpi_iort_memory_access *memory_access;
 	struct acpi_iort_root_complex *pci_rc;
 
 	pci_rc = (struct acpi_iort_root_complex *)node->node_data;
-	return pci_rc->ats_attribute & ACPI_IORT_ATS_SUPPORTED;
+	memory_access =
+		(struct acpi_iort_memory_access *)&pci_rc->memory_properties;
+	return memory_access->memory_flags & ACPI_IORT_MF_CANWBS;
 }
 
 static int iort_iommu_xlate(struct device *dev, struct acpi_iort_node *node,
 			    u32 streamid)
 {
-	const struct iommu_ops *ops;
 	struct fwnode_handle *iort_fwnode;
 
-	if (!node)
+	/* If there's no SMMU driver at all, give up now */
+	if (!node || !iort_iommu_driver_enabled(node->type))
 		return -ENODEV;
 
 	iort_fwnode = iort_get_fwnode(node);
@@ -924,19 +1245,10 @@ static int iort_iommu_xlate(struct device *dev, struct acpi_iort_node *node,
 		return -ENODEV;
 
 	/*
-	 * If the ops look-up fails, this means that either
-	 * the SMMU drivers have not been probed yet or that
-	 * the SMMU drivers are not built in the kernel;
-	 * Depending on whether the SMMU drivers are built-in
-	 * in the kernel or not, defer the IOMMU configuration
-	 * or just abort it.
+	 * If the SMMU drivers are enabled but not loaded/probed
+	 * yet, this will defer.
 	 */
-	ops = iommu_ops_from_fwnode(iort_fwnode);
-	if (!ops)
-		return iort_iommu_driver_enabled(node->type) ?
-		       -EPROBE_DEFER : -ENODEV;
-
-	return arm_smmu_iort_xlate(dev, streamid, iort_fwnode, ops);
+	return acpi_iommu_fwspec_init(dev, streamid, iort_fwnode);
 }
 
 struct iort_pci_alias_info {
@@ -958,40 +1270,67 @@ static int iort_pci_iommu_init(struct pci_dev *pdev, u16 alias, void *data)
 static void iort_named_component_init(struct device *dev,
 				      struct acpi_iort_node *node)
 {
+	struct property_entry props[3] = {};
 	struct acpi_iort_named_component *nc;
-	struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
-
-	if (!fwspec)
-		return;
 
 	nc = (struct acpi_iort_named_component *)node->node_data;
-	fwspec->num_pasid_bits = FIELD_GET(ACPI_IORT_NC_PASID_BITS,
-					   nc->node_flags);
+	props[0] = PROPERTY_ENTRY_U32("pasid-num-bits",
+				      FIELD_GET(ACPI_IORT_NC_PASID_BITS,
+						nc->node_flags));
+	if (nc->node_flags & ACPI_IORT_NC_STALL_SUPPORTED)
+		props[1] = PROPERTY_ENTRY_BOOL("dma-can-stall");
+
+	if (device_create_managed_software_node(dev, props, NULL))
+		dev_warn(dev, "Could not add device properties\n");
 }
 
+static int iort_nc_iommu_map(struct device *dev, struct acpi_iort_node *node)
+{
+	struct acpi_iort_node *parent;
+	int err = -ENODEV, i = 0;
+	u32 streamid = 0;
+
+	do {
+
+		parent = iort_node_map_platform_id(node, &streamid,
+						   IORT_IOMMU_TYPE,
+						   i++);
+
+		if (parent)
+			err = iort_iommu_xlate(dev, parent, streamid);
+	} while (parent && !err);
+
+	return err;
+}
+
+static int iort_nc_iommu_map_id(struct device *dev,
+				struct acpi_iort_node *node,
+				const u32 *in_id)
+{
+	struct acpi_iort_node *parent;
+	u32 streamid;
+
+	parent = iort_node_map_id(node, *in_id, &streamid, IORT_IOMMU_TYPE);
+	if (parent)
+		return iort_iommu_xlate(dev, parent, streamid);
+
+	return -ENODEV;
+}
+
+
 /**
- * iort_iommu_configure - Set-up IOMMU configuration for a device.
+ * iort_iommu_configure_id - Set-up IOMMU configuration for a device.
  *
  * @dev: device to configure
+ * @id_in: optional input id const value pointer
  *
- * Returns: iommu_ops pointer on configuration success
- *          NULL on configuration failure
+ * Returns: 0 on success, <0 on failure
  */
-const struct iommu_ops *iort_iommu_configure(struct device *dev)
+int iort_iommu_configure_id(struct device *dev, const u32 *id_in)
 {
-	struct acpi_iort_node *node, *parent;
-	const struct iommu_ops *ops;
-	u32 streamid = 0;
+	struct acpi_iort_node *node;
 	int err = -ENODEV;
 
-	/*
-	 * If we already translated the fwspec there
-	 * is nothing left to do, return the iommu_ops.
-	 */
-	ops = iort_fwspec_iommu_ops(dev);
-	if (ops)
-		return ops;
-
 	if (dev_is_pci(dev)) {
 		struct iommu_fwspec *fwspec;
 		struct pci_bus *bus = to_pci_dev(dev)->bus;
@@ -1000,7 +1339,7 @@ const struct iommu_ops *iort_iommu_configure(struct device *dev)
 		node = iort_scan_node(ACPI_IORT_NODE_PCI_ROOT_COMPLEX,
 				      iort_match_node_callback, &bus->dev);
 		if (!node)
-			return NULL;
+			return -ENODEV;
 
 		info.node = node;
 		err = pci_for_each_dma_alias(to_pci_dev(dev),
@@ -1009,59 +1348,32 @@ const struct iommu_ops *iort_iommu_configure(struct device *dev)
 		fwspec = dev_iommu_fwspec_get(dev);
 		if (fwspec && iort_pci_rc_supports_ats(node))
 			fwspec->flags |= IOMMU_FWSPEC_PCI_RC_ATS;
+		if (fwspec && iort_pci_rc_supports_canwbs(node))
+			fwspec->flags |= IOMMU_FWSPEC_PCI_RC_CANWBS;
 	} else {
-		int i = 0;
-
 		node = iort_scan_node(ACPI_IORT_NODE_NAMED_COMPONENT,
 				      iort_match_node_callback, dev);
 		if (!node)
-			return NULL;
-
-		do {
-			parent = iort_node_map_platform_id(node, &streamid,
-							   IORT_IOMMU_TYPE,
-							   i++);
+			return -ENODEV;
 
-			if (parent)
-				err = iort_iommu_xlate(dev, parent, streamid);
-		} while (parent && !err);
+		err = id_in ? iort_nc_iommu_map_id(dev, node, id_in) :
+			      iort_nc_iommu_map(dev, node);
 
 		if (!err)
 			iort_named_component_init(dev, node);
 	}
 
-	/*
-	 * If we have reason to believe the IOMMU driver missed the initial
-	 * add_device callback for dev, replay it to get things in order.
-	 */
-	if (!err) {
-		ops = iort_fwspec_iommu_ops(dev);
-		err = iort_add_device_replay(ops, dev);
-	}
-
-	/* Ignore all other errors apart from EPROBE_DEFER */
-	if (err == -EPROBE_DEFER) {
-		ops = ERR_PTR(err);
-	} else if (err) {
-		dev_dbg(dev, "Adding to IOMMU failed: %d\n", err);
-		ops = NULL;
-	}
-
-	return ops;
+	return err;
 }
+
 #else
-static inline const struct iommu_ops *iort_fwspec_iommu_ops(struct device *dev)
-{ return NULL; }
-static inline int iort_add_device_replay(const struct iommu_ops *ops,
-					 struct device *dev)
-{ return 0; }
-int iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head)
-{ return 0; }
-const struct iommu_ops *iort_iommu_configure(struct device *dev)
-{ return NULL; }
+void iort_iommu_get_resv_regions(struct device *dev, struct list_head *head)
+{ }
+int iort_iommu_configure_id(struct device *dev, const u32 *input_id)
+{ return -ENODEV; }
 #endif
 
-static int nc_dma_get_range(struct device *dev, u64 *size)
+static int nc_dma_get_range(struct device *dev, u64 *limit)
 {
 	struct acpi_iort_node *node;
 	struct acpi_iort_named_component *ncomp;
@@ -1073,13 +1385,18 @@ static int nc_dma_get_range(struct device *dev, u64 *size)
 
 	ncomp = (struct acpi_iort_named_component *)node->node_data;
 
-	*size = ncomp->memory_address_limit >= 64 ? U64_MAX :
-			1ULL<<ncomp->memory_address_limit;
+	if (!ncomp->memory_address_limit) {
+		pr_warn(FW_BUG "Named component missing memory address limit\n");
+		return -EINVAL;
+	}
+
+	*limit = ncomp->memory_address_limit >= 64 ? U64_MAX :
+			(1ULL << ncomp->memory_address_limit) - 1;
 
 	return 0;
 }
 
-static int rc_dma_get_range(struct device *dev, u64 *size)
+static int rc_dma_get_range(struct device *dev, u64 *limit)
 {
 	struct acpi_iort_node *node;
 	struct acpi_iort_root_complex *rc;
@@ -1092,62 +1409,30 @@ static int rc_dma_get_range(struct device *dev, u64 *size)
 
 	rc = (struct acpi_iort_root_complex *)node->node_data;
 
-	*size = rc->memory_address_limit >= 64 ? U64_MAX :
-			1ULL<<rc->memory_address_limit;
+	if (!rc->memory_address_limit) {
+		pr_warn(FW_BUG "Root complex missing memory address limit\n");
+		return -EINVAL;
+	}
+
+	*limit = rc->memory_address_limit >= 64 ? U64_MAX :
+			(1ULL << rc->memory_address_limit) - 1;
 
 	return 0;
 }
 
 /**
- * iort_dma_setup() - Set-up device DMA parameters.
+ * iort_dma_get_ranges() - Look up DMA addressing limit for the device
+ * @dev: device to lookup
+ * @limit: DMA limit result pointer
  *
- * @dev: device to configure
- * @dma_addr: device DMA address result pointer
- * @size: DMA range size result pointer
+ * Return: 0 on success, an error otherwise.
  */
-void iort_dma_setup(struct device *dev, u64 *dma_addr, u64 *dma_size)
+int iort_dma_get_ranges(struct device *dev, u64 *limit)
 {
-	u64 end, mask, dmaaddr = 0, size = 0, offset = 0;
-	int ret;
-
-	/*
-	 * If @dev is expected to be DMA-capable then the bus code that created
-	 * it should have initialised its dma_mask pointer by this point. For
-	 * now, we'll continue the legacy behaviour of coercing it to the
-	 * coherent mask if not, but we'll no longer do so quietly.
-	 */
-	if (!dev->dma_mask) {
-		dev_warn(dev, "DMA mask not set\n");
-		dev->dma_mask = &dev->coherent_dma_mask;
-	}
-
-	if (dev->coherent_dma_mask)
-		size = max(dev->coherent_dma_mask, dev->coherent_dma_mask + 1);
+	if (dev_is_pci(dev))
+		return rc_dma_get_range(dev, limit);
 	else
-		size = 1ULL << 32;
-
-	ret = acpi_dma_get_range(dev, &dmaaddr, &offset, &size);
-	if (ret == -ENODEV)
-		ret = dev_is_pci(dev) ? rc_dma_get_range(dev, &size)
-				      : nc_dma_get_range(dev, &size);
-
-	if (!ret) {
-		/*
-		 * Limit coherent and dma mask based on size retrieved from
-		 * firmware.
-		 */
-		end = dmaaddr + size - 1;
-		mask = DMA_BIT_MASK(ilog2(end) + 1);
-		dev->bus_dma_limit = end;
-		dev->coherent_dma_mask = mask;
-		*dev->dma_mask = mask;
-	}
-
-	*dma_addr = dmaaddr;
-	*dma_size = size;
-
-	dev->dma_pfn_offset = PFN_DOWN(offset);
-	dev_dbg(dev, "dma_pfn_offset(%#08llx)\n", offset);
+		return nc_dma_get_range(dev, limit);
 }
 
 static void __init acpi_iort_register_irq(int hwirq, const char *name,
@@ -1297,7 +1582,7 @@ static int  __init arm_smmu_v3_set_proximity(struct device *dev,
 
 	smmu = (struct acpi_iort_smmu_v3 *)node->node_data;
 	if (smmu->flags & ACPI_IORT_SMMU_V3_PXM_VALID) {
-		int dev_node = acpi_map_pxm_to_node(smmu->pxm);
+		int dev_node = pxm_to_node(smmu->pxm);
 
 		if (dev_node != NUMA_NO_NODE && !node_online(dev_node))
 			return -EINVAL;
@@ -1409,9 +1694,17 @@ static void __init arm_smmu_v3_pmcg_init_resources(struct resource *res,
 	res[0].start = pmcg->page0_base_address;
 	res[0].end = pmcg->page0_base_address + SZ_4K - 1;
 	res[0].flags = IORESOURCE_MEM;
-	res[1].start = pmcg->page1_base_address;
-	res[1].end = pmcg->page1_base_address + SZ_4K - 1;
-	res[1].flags = IORESOURCE_MEM;
+	/*
+	 * The initial version in DEN0049C lacked a way to describe register
+	 * page 1, which makes it broken for most PMCG implementations; in
+	 * that case, just let the driver fail gracefully if it expects to
+	 * find a second memory resource.
+	 */
+	if (node->revision > 0) {
+		res[1].start = pmcg->page1_base_address;
+		res[1].end = pmcg->page1_base_address + SZ_4K - 1;
+		res[1].flags = IORESOURCE_MEM;
+	}
 
 	if (pmcg->overflow_gsiv)
 		acpi_iort_register_irq(pmcg->overflow_gsiv, "overflow",
@@ -1421,7 +1714,19 @@ static void __init arm_smmu_v3_pmcg_init_resources(struct resource *res,
 static struct acpi_platform_list pmcg_plat_info[] __initdata = {
 	/* HiSilicon Hip08 Platform */
 	{"HISI  ", "HIP08   ", 0, ACPI_SIG_IORT, greater_than_or_equal,
-	 "Erratum #162001800", IORT_SMMU_V3_PMCG_HISI_HIP08},
+	 "Erratum #162001800, Erratum #162001900", IORT_SMMU_V3_PMCG_HISI_HIP08},
+	/* HiSilicon Hip09 Platform */
+	{"HISI  ", "HIP09   ", 0, ACPI_SIG_IORT, greater_than_or_equal,
+	 "Erratum #162001900", IORT_SMMU_V3_PMCG_HISI_HIP09},
+	{"HISI  ", "HIP09A  ", 0, ACPI_SIG_IORT, greater_than_or_equal,
+	 "Erratum #162001900", IORT_SMMU_V3_PMCG_HISI_HIP09},
+	/* HiSilicon Hip10/11 Platform uses the same SMMU IP with Hip09 */
+	{"HISI  ", "HIP10   ", 0, ACPI_SIG_IORT, greater_than_or_equal,
+	 "Erratum #162001900", IORT_SMMU_V3_PMCG_HISI_HIP09},
+	{"HISI  ", "HIP10C  ", 0, ACPI_SIG_IORT, greater_than_or_equal,
+	 "Erratum #162001900", IORT_SMMU_V3_PMCG_HISI_HIP09},
+	{"HISI  ", "HIP11   ", 0, ACPI_SIG_IORT, greater_than_or_equal,
+	 "Erratum #162001900", IORT_SMMU_V3_PMCG_HISI_HIP09},
 	{ }
 };
 
@@ -1492,6 +1797,7 @@ static __init const struct iort_dev_config *iort_get_dev_cfg(
 /**
  * iort_add_platform_device() - Allocate a platform device for IORT node
  * @node: Pointer to device ACPI IORT node
+ * @ops: Pointer to IORT device config struct
  *
  * Returns: 0 on success, <0 failure
  */
@@ -1667,6 +1973,10 @@ void __init acpi_iort_init(void)
 {
 	acpi_status status;
 
+	/* iort_table will be used at runtime after the iort init,
+	 * so we don't need to call acpi_put_table() to release
+	 * the IORT table mapping.
+	 */
 	status = acpi_get_table(ACPI_SIG_IORT, 0, &iort_table);
 	if (ACPI_FAILURE(status)) {
 		if (status != AE_NOT_FOUND) {
@@ -1680,3 +1990,58 @@ void __init acpi_iort_init(void)
 
 	iort_init_platform_devices();
 }
+
+#ifdef CONFIG_ZONE_DMA
+/*
+ * Extract the highest CPU physical address accessible to all DMA masters in
+ * the system. PHYS_ADDR_MAX is returned when no constrained device is found.
+ */
+phys_addr_t __init acpi_iort_dma_get_max_cpu_address(void)
+{
+	phys_addr_t limit = PHYS_ADDR_MAX;
+	struct acpi_iort_node *node, *end;
+	struct acpi_table_iort *iort;
+	acpi_status status;
+	int i;
+
+	if (acpi_disabled)
+		return limit;
+
+	status = acpi_get_table(ACPI_SIG_IORT, 0,
+				(struct acpi_table_header **)&iort);
+	if (ACPI_FAILURE(status))
+		return limit;
+
+	node = ACPI_ADD_PTR(struct acpi_iort_node, iort, iort->node_offset);
+	end = ACPI_ADD_PTR(struct acpi_iort_node, iort, iort->header.length);
+
+	for (i = 0; i < iort->node_count; i++) {
+		if (node >= end)
+			break;
+
+		switch (node->type) {
+			struct acpi_iort_named_component *ncomp;
+			struct acpi_iort_root_complex *rc;
+			phys_addr_t local_limit;
+
+		case ACPI_IORT_NODE_NAMED_COMPONENT:
+			ncomp = (struct acpi_iort_named_component *)node->node_data;
+			local_limit = DMA_BIT_MASK(ncomp->memory_address_limit);
+			limit = min_not_zero(limit, local_limit);
+			break;
+
+		case ACPI_IORT_NODE_PCI_ROOT_COMPLEX:
+			if (node->revision < 1)
+				break;
+
+			rc = (struct acpi_iort_root_complex *)node->node_data;
+			local_limit = DMA_BIT_MASK(rc->memory_address_limit);
+			limit = min_not_zero(limit, local_limit);
+			break;
+		}
+		node = ACPI_ADD_PTR(struct acpi_iort_node, node, node->length);
+	}
+	acpi_put_table(&iort->header);
+	return limit;
+}
+#endif
diff --git a/drivers/acpi/arm64/mpam.c b/drivers/acpi/arm64/mpam.c
new file mode 100644
index 000000000000..84963a20c3e7
--- /dev/null
+++ b/drivers/acpi/arm64/mpam.c
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2025 Arm Ltd.
+
+/* Parse the MPAM ACPI table feeding the discovered nodes into the driver */
+
+#define pr_fmt(fmt) "ACPI MPAM: " fmt
+
+#include <linux/acpi.h>
+#include <linux/arm_mpam.h>
+#include <linux/bits.h>
+#include <linux/cpu.h>
+#include <linux/cpumask.h>
+#include <linux/platform_device.h>
+
+#include <acpi/processor.h>
+
+/*
+ * Flags for acpi_table_mpam_msc.*_interrupt_flags.
+ * See 2.1.1 Interrupt Flags, Table 5, of DEN0065B_MPAM_ACPI_3.0-bet.
+ */
+#define ACPI_MPAM_MSC_IRQ_MODE                              BIT(0)
+#define ACPI_MPAM_MSC_IRQ_TYPE_MASK                         GENMASK(2, 1)
+#define ACPI_MPAM_MSC_IRQ_TYPE_WIRED                        0
+#define ACPI_MPAM_MSC_IRQ_AFFINITY_TYPE_MASK                BIT(3)
+#define ACPI_MPAM_MSC_IRQ_AFFINITY_TYPE_PROCESSOR           0
+#define ACPI_MPAM_MSC_IRQ_AFFINITY_TYPE_PROCESSOR_CONTAINER 1
+#define ACPI_MPAM_MSC_IRQ_AFFINITY_VALID                    BIT(4)
+
+/*
+ * Encodings for the MSC node body interface type field.
+ * See 2.1 MPAM MSC node, Table 4 of DEN0065B_MPAM_ACPI_3.0-bet.
+ */
+#define ACPI_MPAM_MSC_IFACE_MMIO   0x00
+#define ACPI_MPAM_MSC_IFACE_PCC    0x0a
+
+static bool _is_ppi_partition(u32 flags)
+{
+	u32 aff_type, is_ppi;
+	bool ret;
+
+	is_ppi = FIELD_GET(ACPI_MPAM_MSC_IRQ_AFFINITY_VALID, flags);
+	if (!is_ppi)
+		return false;
+
+	aff_type = FIELD_GET(ACPI_MPAM_MSC_IRQ_AFFINITY_TYPE_MASK, flags);
+	ret = (aff_type == ACPI_MPAM_MSC_IRQ_AFFINITY_TYPE_PROCESSOR_CONTAINER);
+	if (ret)
+		pr_err_once("Partitioned interrupts not supported\n");
+
+	return ret;
+}
+
+static int acpi_mpam_register_irq(struct platform_device *pdev,
+				  u32 intid, u32 flags)
+{
+	int irq;
+	u32 int_type;
+	int trigger;
+
+	if (!intid)
+		return -EINVAL;
+
+	if (_is_ppi_partition(flags))
+		return -EINVAL;
+
+	trigger = FIELD_GET(ACPI_MPAM_MSC_IRQ_MODE, flags);
+	int_type = FIELD_GET(ACPI_MPAM_MSC_IRQ_TYPE_MASK, flags);
+	if (int_type != ACPI_MPAM_MSC_IRQ_TYPE_WIRED)
+		return -EINVAL;
+
+	irq = acpi_register_gsi(&pdev->dev, intid, trigger, ACPI_ACTIVE_HIGH);
+	if (irq < 0)
+		pr_err_once("Failed to register interrupt 0x%x with ACPI\n", intid);
+
+	return irq;
+}
+
+static void acpi_mpam_parse_irqs(struct platform_device *pdev,
+				 struct acpi_mpam_msc_node *tbl_msc,
+				 struct resource *res, int *res_idx)
+{
+	u32 flags, intid;
+	int irq;
+
+	intid = tbl_msc->overflow_interrupt;
+	flags = tbl_msc->overflow_interrupt_flags;
+	irq = acpi_mpam_register_irq(pdev, intid, flags);
+	if (irq > 0)
+		res[(*res_idx)++] = DEFINE_RES_IRQ_NAMED(irq, "overflow");
+
+	intid = tbl_msc->error_interrupt;
+	flags = tbl_msc->error_interrupt_flags;
+	irq = acpi_mpam_register_irq(pdev, intid, flags);
+	if (irq > 0)
+		res[(*res_idx)++] = DEFINE_RES_IRQ_NAMED(irq, "error");
+}
+
+static int acpi_mpam_parse_resource(struct mpam_msc *msc,
+				    struct acpi_mpam_resource_node *res)
+{
+	int level, nid;
+	u32 cache_id;
+
+	switch (res->locator_type) {
+	case ACPI_MPAM_LOCATION_TYPE_PROCESSOR_CACHE:
+		cache_id = res->locator.cache_locator.cache_reference;
+		level = find_acpi_cache_level_from_id(cache_id);
+		if (level <= 0) {
+			pr_err_once("Bad level (%d) for cache with id %u\n", level, cache_id);
+			return -EINVAL;
+		}
+		return mpam_ris_create(msc, res->ris_index, MPAM_CLASS_CACHE,
+				       level, cache_id);
+	case ACPI_MPAM_LOCATION_TYPE_MEMORY:
+		nid = pxm_to_node(res->locator.memory_locator.proximity_domain);
+		if (nid == NUMA_NO_NODE) {
+			pr_debug("Bad proximity domain %lld, using node 0 instead\n",
+				 res->locator.memory_locator.proximity_domain);
+			nid = 0;
+		}
+		return mpam_ris_create(msc, res->ris_index, MPAM_CLASS_MEMORY,
+				       MPAM_CLASS_ID_DEFAULT, nid);
+	default:
+		/* These get discovered later and are treated as unknown */
+		return 0;
+	}
+}
+
+int acpi_mpam_parse_resources(struct mpam_msc *msc,
+			      struct acpi_mpam_msc_node *tbl_msc)
+{
+	int i, err;
+	char *ptr, *table_end;
+	struct acpi_mpam_resource_node *resource;
+
+	table_end = (char *)tbl_msc + tbl_msc->length;
+	ptr = (char *)(tbl_msc + 1);
+	for (i = 0; i < tbl_msc->num_resource_nodes; i++) {
+		u64 max_deps, remaining_table;
+
+		if (ptr + sizeof(*resource) > table_end)
+			return -EINVAL;
+
+		resource = (struct acpi_mpam_resource_node *)ptr;
+
+		remaining_table = table_end - ptr;
+		max_deps = remaining_table / sizeof(struct acpi_mpam_func_deps);
+		if (resource->num_functional_deps > max_deps) {
+			pr_debug("MSC has impossible number of functional dependencies\n");
+			return -EINVAL;
+		}
+
+		err = acpi_mpam_parse_resource(msc, resource);
+		if (err)
+			return err;
+
+		ptr += sizeof(*resource);
+		ptr += resource->num_functional_deps * sizeof(struct acpi_mpam_func_deps);
+	}
+
+	return 0;
+}
+
+/*
+ * Creates the device power management link and returns true if the
+ * acpi id is valid and usable for cpu affinity.  This is the case
+ * when the linked device is a processor or a processor container.
+ */
+static bool __init parse_msc_pm_link(struct acpi_mpam_msc_node *tbl_msc,
+				     struct platform_device *pdev,
+				     u32 *acpi_id)
+{
+	char hid[sizeof(tbl_msc->hardware_id_linked_device) + 1] = { 0 };
+	bool acpi_id_valid = false;
+	struct acpi_device *buddy;
+	char uid[11];
+	int len;
+
+	memcpy(hid, &tbl_msc->hardware_id_linked_device,
+	       sizeof(tbl_msc->hardware_id_linked_device));
+
+	if (!strcmp(hid, ACPI_PROCESSOR_CONTAINER_HID)) {
+		*acpi_id = tbl_msc->instance_id_linked_device;
+		acpi_id_valid = true;
+	}
+
+	len = snprintf(uid, sizeof(uid), "%u",
+		       tbl_msc->instance_id_linked_device);
+	if (len >= sizeof(uid)) {
+		pr_debug("Failed to convert uid of device for power management.");
+		return acpi_id_valid;
+	}
+
+	buddy = acpi_dev_get_first_match_dev(hid, uid, -1);
+	if (buddy) {
+		device_link_add(&pdev->dev, &buddy->dev, DL_FLAG_STATELESS);
+		acpi_dev_put(buddy);
+	}
+
+	return acpi_id_valid;
+}
+
+static int decode_interface_type(struct acpi_mpam_msc_node *tbl_msc,
+				 enum mpam_msc_iface *iface)
+{
+	switch (tbl_msc->interface_type) {
+	case ACPI_MPAM_MSC_IFACE_MMIO:
+		*iface = MPAM_IFACE_MMIO;
+		return 0;
+	case ACPI_MPAM_MSC_IFACE_PCC:
+		*iface = MPAM_IFACE_PCC;
+		return 0;
+	default:
+		return -EINVAL;
+	}
+}
+
+static struct platform_device * __init acpi_mpam_parse_msc(struct acpi_mpam_msc_node *tbl_msc)
+{
+	struct platform_device *pdev __free(platform_device_put) =
+		platform_device_alloc("mpam_msc", tbl_msc->identifier);
+	int next_res = 0, next_prop = 0, err;
+	/* pcc, nrdy, affinity and a sentinel */
+	struct property_entry props[4] = { 0 };
+	/* mmio, 2xirq, no sentinel. */
+	struct resource res[3] = { 0 };
+	struct acpi_device *companion;
+	enum mpam_msc_iface iface;
+	char uid[16];
+	u32 acpi_id;
+
+	if (!pdev)
+		return ERR_PTR(-ENOMEM);
+
+	/* Some power management is described in the namespace: */
+	err = snprintf(uid, sizeof(uid), "%u", tbl_msc->identifier);
+	if (err > 0 && err < sizeof(uid)) {
+		companion = acpi_dev_get_first_match_dev("ARMHAA5C", uid, -1);
+		if (companion) {
+			ACPI_COMPANION_SET(&pdev->dev, companion);
+			acpi_dev_put(companion);
+		} else {
+			pr_debug("MSC.%u: missing namespace entry\n", tbl_msc->identifier);
+		}
+	}
+
+	if (decode_interface_type(tbl_msc, &iface)) {
+		pr_debug("MSC.%u: unknown interface type\n", tbl_msc->identifier);
+		return ERR_PTR(-EINVAL);
+	}
+
+	if (iface == MPAM_IFACE_MMIO) {
+		res[next_res++] = DEFINE_RES_MEM_NAMED(tbl_msc->base_address,
+						       tbl_msc->mmio_size,
+						       "MPAM:MSC");
+	} else if (iface == MPAM_IFACE_PCC) {
+		props[next_prop++] = PROPERTY_ENTRY_U32("pcc-channel",
+							tbl_msc->base_address);
+	}
+
+	acpi_mpam_parse_irqs(pdev, tbl_msc, res, &next_res);
+
+	WARN_ON_ONCE(next_res > ARRAY_SIZE(res));
+	err = platform_device_add_resources(pdev, res, next_res);
+	if (err)
+		return ERR_PTR(err);
+
+	props[next_prop++] = PROPERTY_ENTRY_U32("arm,not-ready-us",
+						tbl_msc->max_nrdy_usec);
+
+	/*
+	 * The MSC's CPU affinity is described via its linked power
+	 * management device, but only if it points at a Processor or
+	 * Processor Container.
+	 */
+	if (parse_msc_pm_link(tbl_msc, pdev, &acpi_id))
+		props[next_prop++] = PROPERTY_ENTRY_U32("cpu_affinity", acpi_id);
+
+	WARN_ON_ONCE(next_prop > ARRAY_SIZE(props) - 1);
+	err = device_create_managed_software_node(&pdev->dev, props, NULL);
+	if (err)
+		return ERR_PTR(err);
+
+	/*
+	 * Stash the table entry for acpi_mpam_parse_resources() to discover
+	 * what this MSC controls.
+	 */
+	err = platform_device_add_data(pdev, tbl_msc, tbl_msc->length);
+	if (err)
+		return ERR_PTR(err);
+
+	err = platform_device_add(pdev);
+	if (err)
+		return ERR_PTR(err);
+
+	return_ptr(pdev);
+}
+
+static int __init acpi_mpam_parse(void)
+{
+	char *table_end, *table_offset;
+	struct acpi_mpam_msc_node *tbl_msc;
+	struct platform_device *pdev;
+
+	if (acpi_disabled || !system_supports_mpam())
+		return 0;
+
+	struct acpi_table_header *table __free(acpi_put_table) =
+		acpi_get_table_pointer(ACPI_SIG_MPAM, 0);
+
+	if (IS_ERR(table))
+		return 0;
+
+	if (table->revision < 1) {
+		pr_debug("MPAM ACPI table revision %d not supported\n", table->revision);
+		return 0;
+	}
+
+	table_offset = (char *)(table + 1);
+	table_end = (char *)table + table->length;
+
+	while (table_offset < table_end) {
+		tbl_msc = (struct acpi_mpam_msc_node *)table_offset;
+		if (table_offset + sizeof(*tbl_msc) > table_end ||
+		    table_offset + tbl_msc->length > table_end) {
+			pr_err("MSC entry overlaps end of ACPI table\n");
+			return -EINVAL;
+		}
+		table_offset += tbl_msc->length;
+
+		/*
+		 * If any of the reserved fields are set, make no attempt to
+		 * parse the MSC structure. This MSC will still be counted by
+		 * acpi_mpam_count_msc(), meaning the MPAM driver can't probe
+		 * against all MSC, and will never be enabled. There is no way
+		 * to enable it safely, because we cannot determine safe
+		 * system-wide partid and pmg ranges in this situation.
+		 */
+		if (tbl_msc->reserved || tbl_msc->reserved1 || tbl_msc->reserved2) {
+			pr_err_once("Unrecognised MSC, MPAM not usable\n");
+			pr_debug("MSC.%u: reserved field set\n", tbl_msc->identifier);
+			continue;
+		}
+
+		if (!tbl_msc->mmio_size) {
+			pr_debug("MSC.%u: marked as disabled\n", tbl_msc->identifier);
+			continue;
+		}
+
+		pdev = acpi_mpam_parse_msc(tbl_msc);
+		if (IS_ERR(pdev))
+			return PTR_ERR(pdev);
+	}
+
+	return 0;
+}
+
+/**
+ * acpi_mpam_count_msc() - Count the number of MSC described by firmware.
+ *
+ * Returns the number of MSCs, or zero for an error.
+ *
+ * This can be called before or in parallel with acpi_mpam_parse().
+ */
+int acpi_mpam_count_msc(void)
+{
+	char *table_end, *table_offset;
+	struct acpi_mpam_msc_node *tbl_msc;
+	int count = 0;
+
+	if (acpi_disabled || !system_supports_mpam())
+		return 0;
+
+	struct acpi_table_header *table __free(acpi_put_table) =
+		acpi_get_table_pointer(ACPI_SIG_MPAM, 0);
+
+	if (IS_ERR(table))
+		return 0;
+
+	if (table->revision < 1)
+		return 0;
+
+	table_offset = (char *)(table + 1);
+	table_end = (char *)table + table->length;
+
+	while (table_offset < table_end) {
+		tbl_msc = (struct acpi_mpam_msc_node *)table_offset;
+
+		if (table_offset + sizeof(*tbl_msc) > table_end)
+			return -EINVAL;
+		if (tbl_msc->length < sizeof(*tbl_msc))
+			return -EINVAL;
+		if (tbl_msc->length > table_end - table_offset)
+			return -EINVAL;
+		table_offset += tbl_msc->length;
+
+		if (!tbl_msc->mmio_size)
+			continue;
+
+		count++;
+	}
+
+	return count;
+}
+
+/*
+ * Call after ACPI devices have been created, which happens behind acpi_scan_init()
+ * called from subsys_initcall(). PCC requires the mailbox driver, which is
+ * initialised from postcore_initcall().
+ */
+subsys_initcall_sync(acpi_mpam_parse);
diff --git a/drivers/acpi/arm64/thermal_cpufreq.c b/drivers/acpi/arm64/thermal_cpufreq.c
new file mode 100644
index 000000000000..582854914c5c
--- /dev/null
+++ b/drivers/acpi/arm64/thermal_cpufreq.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include <linux/acpi.h>
+#include <linux/export.h>
+
+#include "../internal.h"
+
+#define SMCCC_SOC_ID_T241      0x036b0241
+
+int acpi_arch_thermal_cpufreq_pctg(void)
+{
+	s32 soc_id = arm_smccc_get_soc_id_version();
+
+	/*
+	 * Check JEP106 code for NVIDIA Tegra241 chip (036b:0241) and
+	 * reduce the CPUFREQ Thermal reduction percentage to 5%.
+	 */
+	if (soc_id == SMCCC_SOC_ID_T241)
+		return 5;
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(acpi_arch_thermal_cpufreq_pctg);
diff --git a/drivers/acpi/battery.c b/drivers/acpi/battery.c
index 366c389175d8..34181fa52e93 100644
--- a/drivers/acpi/battery.c
+++ b/drivers/acpi/battery.c
@@ -8,9 +8,8 @@
  *  Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
  */
 
-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+#define pr_fmt(fmt) "ACPI: battery: " fmt
 
-#include <linux/async.h>
 #include <linux/delay.h>
 #include <linux/dmi.h>
 #include <linux/jiffies.h>
@@ -22,21 +21,13 @@
 #include <linux/suspend.h>
 #include <linux/types.h>
 
-#include <asm/unaligned.h>
-
-#ifdef CONFIG_ACPI_PROCFS_POWER
-#include <linux/proc_fs.h>
-#include <linux/seq_file.h>
-#include <linux/uaccess.h>
-#endif
+#include <linux/unaligned.h>
 
 #include <linux/acpi.h>
 #include <linux/power_supply.h>
 
 #include <acpi/battery.h>
 
-#define PREFIX "ACPI: "
-
 #define ACPI_BATTERY_VALUE_UNKNOWN 0xFFFFFFFF
 #define ACPI_BATTERY_CAPACITY_VALID(capacity) \
 	((capacity) != 0 && (capacity) != ACPI_BATTERY_VALUE_UNKNOWN)
@@ -46,61 +37,52 @@
 /* Battery power unit: 0 means mW, 1 means mA */
 #define ACPI_BATTERY_POWER_UNIT_MA	1
 
-#define ACPI_BATTERY_STATE_DISCHARGING	0x1
-#define ACPI_BATTERY_STATE_CHARGING	0x2
-#define ACPI_BATTERY_STATE_CRITICAL	0x4
+#define ACPI_BATTERY_STATE_DISCHARGING		0x1
+#define ACPI_BATTERY_STATE_CHARGING		0x2
+#define ACPI_BATTERY_STATE_CRITICAL		0x4
+#define ACPI_BATTERY_STATE_CHARGE_LIMITING	0x8
 
-#define _COMPONENT		ACPI_BATTERY_COMPONENT
-
-ACPI_MODULE_NAME("battery");
+#define MAX_STRING_LENGTH	64
 
 MODULE_AUTHOR("Paul Diefenbaugh");
 MODULE_AUTHOR("Alexey Starikovskiy <astarikovskiy@suse.de>");
 MODULE_DESCRIPTION("ACPI Battery Driver");
 MODULE_LICENSE("GPL");
 
-static async_cookie_t async_cookie;
-static bool battery_driver_registered;
 static int battery_bix_broken_package;
 static int battery_notification_delay_ms;
 static int battery_ac_is_broken;
-static int battery_check_pmic = 1;
 static unsigned int cache_time = 1000;
 module_param(cache_time, uint, 0644);
 MODULE_PARM_DESC(cache_time, "cache time in milliseconds");
 
-#ifdef CONFIG_ACPI_PROCFS_POWER
-extern struct proc_dir_entry *acpi_lock_battery_dir(void);
-extern void *acpi_unlock_battery_dir(struct proc_dir_entry *acpi_battery_dir);
-#endif
-
 static const struct acpi_device_id battery_device_ids[] = {
 	{"PNP0C0A", 0},
+
+	/* Microsoft Surface Go 3 */
+	{"MSHW0146", 0},
+
 	{"", 0},
 };
 
 MODULE_DEVICE_TABLE(acpi, battery_device_ids);
 
-/* Lists of PMIC ACPI HIDs with an (often better) native battery driver */
-static const char * const acpi_battery_blacklist[] = {
-	"INT33F4", /* X-Powers AXP288 PMIC */
-};
-
 enum {
 	ACPI_BATTERY_ALARM_PRESENT,
 	ACPI_BATTERY_XINFO_PRESENT,
 	ACPI_BATTERY_QUIRK_PERCENTAGE_CAPACITY,
 	/* On Lenovo Thinkpad models from 2010 and 2011, the power unit
-	   switches between mWh and mAh depending on whether the system
-	   is running on battery or not.  When mAh is the unit, most
-	   reported values are incorrect and need to be adjusted by
-	   10000/design_voltage.  Verified on x201, t410, t410s, and x220.
-	   Pre-2010 and 2012 models appear to always report in mWh and
-	   are thus unaffected (tested with t42, t61, t500, x200, x300,
-	   and x230).  Also, in mid-2012 Lenovo issued a BIOS update for
-	   the 2011 models that fixes the issue (tested on x220 with a
-	   post-1.29 BIOS), but as of Nov. 2012, no such update is
-	   available for the 2010 models.  */
+	 * switches between mWh and mAh depending on whether the system
+	 * is running on battery or not.  When mAh is the unit, most
+	 * reported values are incorrect and need to be adjusted by
+	 * 10000/design_voltage.  Verified on x201, t410, t410s, and x220.
+	 * Pre-2010 and 2012 models appear to always report in mWh and
+	 * are thus unaffected (tested with t42, t61, t500, x200, x300,
+	 * and x230).  Also, in mid-2012 Lenovo issued a BIOS update for
+	 *  the 2011 models that fixes the issue (tested on x220 with a
+	 * post-1.29 BIOS), but as of Nov. 2012, no such update is
+	 * available for the 2010 models.
+	 */
 	ACPI_BATTERY_QUIRK_THINKPAD_MAH,
 	/* for batteries reporting current capacity with design capacity
 	 * on a full charge, but showing degradation in full charge cap.
@@ -109,8 +91,7 @@ enum {
 };
 
 struct acpi_battery {
-	struct mutex lock;
-	struct mutex sysfs_lock;
+	struct mutex update_lock;
 	struct power_supply *bat;
 	struct power_supply_desc bat_desc;
 	struct acpi_device *device;
@@ -136,10 +117,10 @@ struct acpi_battery {
 	int capacity_granularity_1;
 	int capacity_granularity_2;
 	int alarm;
-	char model_number[32];
-	char serial_number[32];
-	char type[32];
-	char oem_info[32];
+	char model_number[MAX_STRING_LENGTH];
+	char serial_number[MAX_STRING_LENGTH];
+	char type[MAX_STRING_LENGTH];
+	char oem_info[MAX_STRING_LENGTH];
 	int state;
 	int power_unit;
 	unsigned long flags;
@@ -171,7 +152,7 @@ static int acpi_battery_get_state(struct acpi_battery *battery);
 
 static int acpi_battery_is_charged(struct acpi_battery *battery)
 {
-	/* charging, discharging or critical low */
+	/* charging, discharging, critical low or charge limited */
 	if (battery->state != 0)
 		return 0;
 
@@ -185,7 +166,7 @@ static int acpi_battery_is_charged(struct acpi_battery *battery)
 		return 1;
 
 	/* fallback to using design values for broken batteries */
-	if (battery->design_capacity == battery->capacity_now)
+	if (battery->design_capacity <= battery->capacity_now)
 		return 1;
 
 	/* we don't do any sort of metric based on percentages */
@@ -231,10 +212,12 @@ static int acpi_battery_get_property(struct power_supply *psy,
 			val->intval = acpi_battery_handle_discharging(battery);
 		else if (battery->state & ACPI_BATTERY_STATE_CHARGING)
 			val->intval = POWER_SUPPLY_STATUS_CHARGING;
+		else if (battery->state & ACPI_BATTERY_STATE_CHARGE_LIMITING)
+			val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING;
 		else if (acpi_battery_is_charged(battery))
 			val->intval = POWER_SUPPLY_STATUS_FULL;
 		else
-			val->intval = POWER_SUPPLY_STATUS_UNKNOWN;
+			val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING;
 		break;
 	case POWER_SUPPLY_PROP_PRESENT:
 		val->intval = acpi_battery_present(battery);
@@ -295,8 +278,8 @@ static int acpi_battery_get_property(struct power_supply *psy,
 		    full_capacity == ACPI_BATTERY_VALUE_UNKNOWN)
 			ret = -ENODEV;
 		else
-			val->intval = battery->capacity_now * 100/
-					full_capacity;
+			val->intval = DIV_ROUND_CLOSEST_ULL(battery->capacity_now * 100ULL,
+					full_capacity);
 		break;
 	case POWER_SUPPLY_PROP_CAPACITY_LEVEL:
 		if (battery->state & ACPI_BATTERY_STATE_CRITICAL)
@@ -324,7 +307,7 @@ static int acpi_battery_get_property(struct power_supply *psy,
 	return ret;
 }
 
-static enum power_supply_property charge_battery_props[] = {
+static const enum power_supply_property charge_battery_props[] = {
 	POWER_SUPPLY_PROP_STATUS,
 	POWER_SUPPLY_PROP_PRESENT,
 	POWER_SUPPLY_PROP_TECHNOLOGY,
@@ -342,7 +325,7 @@ static enum power_supply_property charge_battery_props[] = {
 	POWER_SUPPLY_PROP_SERIAL_NUMBER,
 };
 
-static enum power_supply_property charge_battery_full_cap_broken_props[] = {
+static const enum power_supply_property charge_battery_full_cap_broken_props[] = {
 	POWER_SUPPLY_PROP_STATUS,
 	POWER_SUPPLY_PROP_PRESENT,
 	POWER_SUPPLY_PROP_TECHNOLOGY,
@@ -356,7 +339,7 @@ static enum power_supply_property charge_battery_full_cap_broken_props[] = {
 	POWER_SUPPLY_PROP_SERIAL_NUMBER,
 };
 
-static enum power_supply_property energy_battery_props[] = {
+static const enum power_supply_property energy_battery_props[] = {
 	POWER_SUPPLY_PROP_STATUS,
 	POWER_SUPPLY_PROP_PRESENT,
 	POWER_SUPPLY_PROP_TECHNOLOGY,
@@ -374,7 +357,7 @@ static enum power_supply_property energy_battery_props[] = {
 	POWER_SUPPLY_PROP_SERIAL_NUMBER,
 };
 
-static enum power_supply_property energy_battery_full_cap_broken_props[] = {
+static const enum power_supply_property energy_battery_full_cap_broken_props[] = {
 	POWER_SUPPLY_PROP_STATUS,
 	POWER_SUPPLY_PROP_PRESENT,
 	POWER_SUPPLY_PROP_TECHNOLOGY,
@@ -388,9 +371,7 @@ static enum power_supply_property energy_battery_full_cap_broken_props[] = {
 	POWER_SUPPLY_PROP_SERIAL_NUMBER,
 };
 
-/* --------------------------------------------------------------------------
-                               Battery Management
-   -------------------------------------------------------------------------- */
+/* Battery Management */
 struct acpi_offsets {
 	size_t offset;		/* offset inside struct acpi_sbs_battery */
 	u8 mode;		/* int or string? */
@@ -448,6 +429,7 @@ static int extract_package(struct acpi_battery *battery,
 {
 	int i;
 	union acpi_object *element;
+
 	if (package->type != ACPI_TYPE_PACKAGE)
 		return -EFAULT;
 	for (i = 0; i < num; ++i) {
@@ -456,15 +438,25 @@ static int extract_package(struct acpi_battery *battery,
 		element = &package->package.elements[i];
 		if (offsets[i].mode) {
 			u8 *ptr = (u8 *)battery + offsets[i].offset;
-			if (element->type == ACPI_TYPE_STRING ||
-			    element->type == ACPI_TYPE_BUFFER)
-				strncpy(ptr, element->string.pointer, 32);
-			else if (element->type == ACPI_TYPE_INTEGER) {
-				strncpy(ptr, (u8 *)&element->integer.value,
-					sizeof(u64));
-				ptr[sizeof(u64)] = 0;
-			} else
+			u32 len = MAX_STRING_LENGTH;
+
+			switch (element->type) {
+			case ACPI_TYPE_BUFFER:
+				if (len > element->buffer.length + 1)
+					len = element->buffer.length + 1;
+
+				fallthrough;
+			case ACPI_TYPE_STRING:
+				strscpy(ptr, element->string.pointer, len);
+
+				break;
+			case ACPI_TYPE_INTEGER:
+				strscpy(ptr, (u8 *)&element->integer.value, sizeof(u64) + 1);
+
+				break;
+			default:
 				*ptr = 0; /* don't have value */
+			}
 		} else {
 			int *x = (int *)((u8 *)battery + offsets[i].offset);
 			*x = (element->type == ACPI_TYPE_INTEGER) ?
@@ -477,7 +469,8 @@ static int extract_package(struct acpi_battery *battery,
 static int acpi_battery_get_status(struct acpi_battery *battery)
 {
 	if (acpi_bus_get_status(battery->device)) {
-		ACPI_EXCEPTION((AE_INFO, AE_ERROR, "Evaluating _STA"));
+		acpi_handle_info(battery->device->handle,
+				 "_STA evaluation failed\n");
 		return -ENODEV;
 	}
 	return 0;
@@ -513,10 +506,12 @@ static int extract_battery_info(const int use_bix,
 		    battery->design_capacity_warning *
 		    10000 / battery->design_voltage;
 		/* Curiously, design_capacity_low, unlike the rest of them,
-		   is correct.  */
+		 *  is correct.
+		 */
 		/* capacity_granularity_* equal 1 on the systems tested, so
-		   it's impossible to tell if they would need an adjustment
-		   or not if their values were higher.  */
+		 * it's impossible to tell if they would need an adjustment
+		 * or not if their values were higher.
+		 */
 	}
 	if (test_bit(ACPI_BATTERY_QUIRK_DEGRADED_FULL_CHARGE, &battery->flags) &&
 	    battery->capacity_now > battery->full_charge_capacity)
@@ -539,15 +534,15 @@ static int acpi_battery_get_info(struct acpi_battery *battery)
 		struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
 		acpi_status status = AE_ERROR;
 
-		mutex_lock(&battery->lock);
 		status = acpi_evaluate_object(battery->device->handle,
 					      use_bix ? "_BIX":"_BIF",
 					      NULL, &buffer);
-		mutex_unlock(&battery->lock);
 
 		if (ACPI_FAILURE(status)) {
-			ACPI_EXCEPTION((AE_INFO, status, "Evaluating %s",
-					use_bix ? "_BIX":"_BIF"));
+			acpi_handle_info(battery->device->handle,
+					 "%s evaluation failed: %s\n",
+					 use_bix ? "_BIX":"_BIF",
+					 acpi_format_exception(status));
 		} else {
 			result = extract_battery_info(use_bix,
 						      battery,
@@ -578,13 +573,12 @@ static int acpi_battery_get_state(struct acpi_battery *battery)
 			msecs_to_jiffies(cache_time)))
 		return 0;
 
-	mutex_lock(&battery->lock);
 	status = acpi_evaluate_object(battery->device->handle, "_BST",
 				      NULL, &buffer);
-	mutex_unlock(&battery->lock);
-
 	if (ACPI_FAILURE(status)) {
-		ACPI_EXCEPTION((AE_INFO, status, "Evaluating _BST"));
+		acpi_handle_info(battery->device->handle,
+				 "_BST evaluation failed: %s",
+				 acpi_format_exception(status));
 		return -ENODEV;
 	}
 
@@ -601,7 +595,7 @@ static int acpi_battery_get_state(struct acpi_battery *battery)
 		battery->rate_now != ACPI_BATTERY_VALUE_UNKNOWN &&
 		(s16)(battery->rate_now) < 0) {
 		battery->rate_now = abs((s16)battery->rate_now);
-		pr_warn_once(FW_BUG "battery: (dis)charge rate invalid.\n");
+		pr_warn_once(FW_BUG "(dis)charge rate invalid.\n");
 	}
 
 	if (test_bit(ACPI_BATTERY_QUIRK_PERCENTAGE_CAPACITY, &battery->flags)
@@ -628,15 +622,14 @@ static int acpi_battery_set_alarm(struct acpi_battery *battery)
 	    !test_bit(ACPI_BATTERY_ALARM_PRESENT, &battery->flags))
 		return -ENODEV;
 
-	mutex_lock(&battery->lock);
 	status = acpi_execute_simple_method(battery->device->handle, "_BTP",
 					    battery->alarm);
-	mutex_unlock(&battery->lock);
-
 	if (ACPI_FAILURE(status))
 		return -ENODEV;
 
-	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Alarm set to %d\n", battery->alarm));
+	acpi_handle_debug(battery->device->handle, "Alarm set to %d\n",
+			  battery->alarm);
+
 	return 0;
 }
 
@@ -658,7 +651,8 @@ static ssize_t acpi_battery_alarm_show(struct device *dev,
 					char *buf)
 {
 	struct acpi_battery *battery = to_acpi_battery(dev_get_drvdata(dev));
-	return sprintf(buf, "%d\n", battery->alarm * 1000);
+
+	return sysfs_emit(buf, "%d\n", battery->alarm * 1000);
 }
 
 static ssize_t acpi_battery_alarm_store(struct device *dev,
@@ -667,6 +661,7 @@ static ssize_t acpi_battery_alarm_store(struct device *dev,
 {
 	unsigned long x;
 	struct acpi_battery *battery = to_acpi_battery(dev_get_drvdata(dev));
+
 	if (sscanf(buf, "%lu\n", &x) == 1)
 		battery->alarm = x/1000;
 	if (acpi_battery_present(battery))
@@ -674,12 +669,18 @@ static ssize_t acpi_battery_alarm_store(struct device *dev,
 	return count;
 }
 
-static const struct device_attribute alarm_attr = {
+static struct device_attribute alarm_attr = {
 	.attr = {.name = "alarm", .mode = 0644},
 	.show = acpi_battery_alarm_show,
 	.store = acpi_battery_alarm_store,
 };
 
+static struct attribute *acpi_battery_attrs[] = {
+	&alarm_attr.attr,
+	NULL
+};
+ATTRIBUTE_GROUPS(acpi_battery);
+
 /*
  * The Battery Hooking API
  *
@@ -693,27 +694,35 @@ static LIST_HEAD(acpi_battery_list);
 static LIST_HEAD(battery_hook_list);
 static DEFINE_MUTEX(hook_mutex);
 
-static void __battery_hook_unregister(struct acpi_battery_hook *hook, int lock)
+static void battery_hook_unregister_unlocked(struct acpi_battery_hook *hook)
 {
 	struct acpi_battery *battery;
+
 	/*
 	 * In order to remove a hook, we first need to
 	 * de-register all the batteries that are registered.
 	 */
-	if (lock)
-		mutex_lock(&hook_mutex);
 	list_for_each_entry(battery, &acpi_battery_list, list) {
-		hook->remove_battery(battery->bat);
+		if (!hook->remove_battery(battery->bat, hook))
+			power_supply_changed(battery->bat);
 	}
-	list_del(&hook->list);
-	if (lock)
-		mutex_unlock(&hook_mutex);
-	pr_info("extension unregistered: %s\n", hook->name);
+	list_del_init(&hook->list);
+
+	pr_info("hook unregistered: %s\n", hook->name);
 }
 
 void battery_hook_unregister(struct acpi_battery_hook *hook)
 {
-	__battery_hook_unregister(hook, 1);
+	mutex_lock(&hook_mutex);
+	/*
+	 * Ignore already unregistered battery hooks. This might happen
+	 * if a battery hook was previously unloaded due to an error when
+	 * adding a new battery.
+	 */
+	if (!list_empty(&hook->list))
+		battery_hook_unregister_unlocked(hook);
+
+	mutex_unlock(&hook_mutex);
 }
 EXPORT_SYMBOL_GPL(battery_hook_unregister);
 
@@ -722,7 +731,6 @@ void battery_hook_register(struct acpi_battery_hook *hook)
 	struct acpi_battery *battery;
 
 	mutex_lock(&hook_mutex);
-	INIT_LIST_HEAD(&hook->list);
 	list_add(&hook->list, &battery_hook_list);
 	/*
 	 * Now that the driver is registered, we need
@@ -731,29 +739,46 @@ void battery_hook_register(struct acpi_battery_hook *hook)
 	 * its attributes.
 	 */
 	list_for_each_entry(battery, &acpi_battery_list, list) {
-		if (hook->add_battery(battery->bat)) {
+		if (hook->add_battery(battery->bat, hook)) {
 			/*
 			 * If a add-battery returns non-zero,
-			 * the registration of the extension has failed,
+			 * the registration of the hook has failed,
 			 * and we will not add it to the list of loaded
 			 * hooks.
 			 */
-			pr_err("extension failed to load: %s", hook->name);
-			__battery_hook_unregister(hook, 0);
+			pr_err("hook failed to load: %s", hook->name);
+			battery_hook_unregister_unlocked(hook);
 			goto end;
 		}
+
+		power_supply_changed(battery->bat);
 	}
-	pr_info("new extension: %s\n", hook->name);
+	pr_info("new hook: %s\n", hook->name);
 end:
 	mutex_unlock(&hook_mutex);
 }
 EXPORT_SYMBOL_GPL(battery_hook_register);
 
+static void devm_battery_hook_unregister(void *data)
+{
+	struct acpi_battery_hook *hook = data;
+
+	battery_hook_unregister(hook);
+}
+
+int devm_battery_hook_register(struct device *dev, struct acpi_battery_hook *hook)
+{
+	battery_hook_register(hook);
+
+	return devm_add_action_or_reset(dev, devm_battery_hook_unregister, hook);
+}
+EXPORT_SYMBOL_GPL(devm_battery_hook_register);
+
 /*
  * This function gets called right after the battery sysfs
  * attributes have been added, so that the drivers that
  * define custom sysfs attributes can add their own.
-*/
+ */
 static void battery_hook_add_battery(struct acpi_battery *battery)
 {
 	struct acpi_battery_hook *hook_node, *tmp;
@@ -769,14 +794,14 @@ static void battery_hook_add_battery(struct acpi_battery *battery)
 	 * during the battery module initialization.
 	 */
 	list_for_each_entry_safe(hook_node, tmp, &battery_hook_list, list) {
-		if (hook_node->add_battery(battery->bat)) {
+		if (hook_node->add_battery(battery->bat, hook_node)) {
 			/*
-			 * The notification of the extensions has failed, to
-			 * prevent further errors we will unload the extension.
+			 * The notification of the hook has failed, to
+			 * prevent further errors we will unload the hook.
 			 */
-			pr_err("error in extension, unloading: %s",
+			pr_err("error in hook, unloading: %s",
 					hook_node->name);
-			__battery_hook_unregister(hook_node, 0);
+			battery_hook_unregister_unlocked(hook_node);
 		}
 	}
 	mutex_unlock(&hook_mutex);
@@ -792,7 +817,7 @@ static void battery_hook_remove_battery(struct acpi_battery *battery)
 	 * custom attributes from the battery.
 	 */
 	list_for_each_entry(hook, &battery_hook_list, list) {
-		hook->remove_battery(battery->bat);
+		hook->remove_battery(battery->bat, hook);
 	}
 	/* Then, just remove the battery from the list */
 	list_del(&battery->list);
@@ -809,14 +834,18 @@ static void __exit battery_hook_exit(void)
 	 * need to remove the hooks.
 	 */
 	list_for_each_entry_safe(hook, ptr, &battery_hook_list, list) {
-		__battery_hook_unregister(hook, 1);
+		battery_hook_unregister(hook);
 	}
 	mutex_destroy(&hook_mutex);
 }
 
 static int sysfs_add_battery(struct acpi_battery *battery)
 {
-	struct power_supply_config psy_cfg = { .drv_data = battery, };
+	struct power_supply_config psy_cfg = {
+		.drv_data = battery,
+		.attr_grp = acpi_battery_groups,
+		.no_wakeup_source = true,
+	};
 	bool full_cap_broken = false;
 
 	if (!ACPI_BATTERY_CAPACITY_VALID(battery->full_charge_capacity) &&
@@ -851,7 +880,7 @@ static int sysfs_add_battery(struct acpi_battery *battery)
 	battery->bat_desc.type = POWER_SUPPLY_TYPE_BATTERY;
 	battery->bat_desc.get_property = acpi_battery_get_property;
 
-	battery->bat = power_supply_register_no_ws(&battery->device->dev,
+	battery->bat = power_supply_register(&battery->device->dev,
 				&battery->bat_desc, &psy_cfg);
 
 	if (IS_ERR(battery->bat)) {
@@ -861,31 +890,29 @@ static int sysfs_add_battery(struct acpi_battery *battery)
 		return result;
 	}
 	battery_hook_add_battery(battery);
-	return device_create_file(&battery->bat->dev, &alarm_attr);
+	return 0;
 }
 
 static void sysfs_remove_battery(struct acpi_battery *battery)
 {
-	mutex_lock(&battery->sysfs_lock);
-	if (!battery->bat) {
-		mutex_unlock(&battery->sysfs_lock);
+	if (!battery->bat)
 		return;
-	}
+
 	battery_hook_remove_battery(battery);
-	device_remove_file(&battery->bat->dev, &alarm_attr);
 	power_supply_unregister(battery->bat);
 	battery->bat = NULL;
-	mutex_unlock(&battery->sysfs_lock);
 }
 
 static void find_battery(const struct dmi_header *dm, void *private)
 {
 	struct acpi_battery *battery = (struct acpi_battery *)private;
 	/* Note: the hardcoded offsets below have been extracted from
-	   the source code of dmidecode.  */
+	 * the source code of dmidecode.
+	 */
 	if (dm->type == DMI_ENTRY_PORTABLE_BATTERY && dm->length >= 8) {
 		const u8 *dmi_data = (const u8 *)(dm + 1);
 		int dmi_capacity = get_unaligned((const u16 *)(dmi_data + 6));
+
 		if (dm->length >= 18)
 			dmi_capacity *= dmi_data[17];
 		if (battery->design_capacity * battery->design_voltage / 1000
@@ -927,6 +954,7 @@ static void acpi_battery_quirks(struct acpi_battery *battery)
 
 	if (battery->power_unit && dmi_name_in_vendors("LENOVO")) {
 		const char *s;
+
 		s = dmi_get_system_info(DMI_PRODUCT_VERSION);
 		if (s && !strncasecmp(s, "ThinkPad", 8)) {
 			dmi_walk(find_battery, battery);
@@ -998,7 +1026,7 @@ static int acpi_battery_update(struct acpi_battery *battery, bool resume)
 	 */
 	if ((battery->state & ACPI_BATTERY_STATE_CRITICAL) ||
 	    (test_bit(ACPI_BATTERY_ALARM_PRESENT, &battery->flags) &&
-            (battery->capacity_now <= battery->alarm)))
+	     (battery->capacity_now <= battery->alarm)))
 		acpi_pm_wakeup_event(&battery->device->dev);
 
 	return result;
@@ -1023,244 +1051,25 @@ static void acpi_battery_refresh(struct acpi_battery *battery)
 	sysfs_add_battery(battery);
 }
 
-/* --------------------------------------------------------------------------
-                              FS Interface (/proc)
-   -------------------------------------------------------------------------- */
-
-#ifdef CONFIG_ACPI_PROCFS_POWER
-static struct proc_dir_entry *acpi_battery_dir;
-
-static const char *acpi_battery_units(const struct acpi_battery *battery)
-{
-	return (battery->power_unit == ACPI_BATTERY_POWER_UNIT_MA) ?
-		"mA" : "mW";
-}
-
-static int acpi_battery_info_proc_show(struct seq_file *seq, void *offset)
-{
-	struct acpi_battery *battery = seq->private;
-	int result = acpi_battery_update(battery, false);
-
-	if (result)
-		goto end;
-
-	seq_printf(seq, "present:                 %s\n",
-		   acpi_battery_present(battery) ? "yes" : "no");
-	if (!acpi_battery_present(battery))
-		goto end;
-	if (battery->design_capacity == ACPI_BATTERY_VALUE_UNKNOWN)
-		seq_printf(seq, "design capacity:         unknown\n");
-	else
-		seq_printf(seq, "design capacity:         %d %sh\n",
-			   battery->design_capacity,
-			   acpi_battery_units(battery));
-
-	if (battery->full_charge_capacity == ACPI_BATTERY_VALUE_UNKNOWN)
-		seq_printf(seq, "last full capacity:      unknown\n");
-	else
-		seq_printf(seq, "last full capacity:      %d %sh\n",
-			   battery->full_charge_capacity,
-			   acpi_battery_units(battery));
-
-	seq_printf(seq, "battery technology:      %srechargeable\n",
-		   battery->technology ? "" : "non-");
-
-	if (battery->design_voltage == ACPI_BATTERY_VALUE_UNKNOWN)
-		seq_printf(seq, "design voltage:          unknown\n");
-	else
-		seq_printf(seq, "design voltage:          %d mV\n",
-			   battery->design_voltage);
-	seq_printf(seq, "design capacity warning: %d %sh\n",
-		   battery->design_capacity_warning,
-		   acpi_battery_units(battery));
-	seq_printf(seq, "design capacity low:     %d %sh\n",
-		   battery->design_capacity_low,
-		   acpi_battery_units(battery));
-	seq_printf(seq, "cycle count:		  %i\n", battery->cycle_count);
-	seq_printf(seq, "capacity granularity 1:  %d %sh\n",
-		   battery->capacity_granularity_1,
-		   acpi_battery_units(battery));
-	seq_printf(seq, "capacity granularity 2:  %d %sh\n",
-		   battery->capacity_granularity_2,
-		   acpi_battery_units(battery));
-	seq_printf(seq, "model number:            %s\n", battery->model_number);
-	seq_printf(seq, "serial number:           %s\n", battery->serial_number);
-	seq_printf(seq, "battery type:            %s\n", battery->type);
-	seq_printf(seq, "OEM info:                %s\n", battery->oem_info);
-      end:
-	if (result)
-		seq_printf(seq, "ERROR: Unable to read battery info\n");
-	return result;
-}
-
-static int acpi_battery_state_proc_show(struct seq_file *seq, void *offset)
-{
-	struct acpi_battery *battery = seq->private;
-	int result = acpi_battery_update(battery, false);
-
-	if (result)
-		goto end;
-
-	seq_printf(seq, "present:                 %s\n",
-		   acpi_battery_present(battery) ? "yes" : "no");
-	if (!acpi_battery_present(battery))
-		goto end;
-
-	seq_printf(seq, "capacity state:          %s\n",
-			(battery->state & 0x04) ? "critical" : "ok");
-	if ((battery->state & 0x01) && (battery->state & 0x02))
-		seq_printf(seq,
-			   "charging state:          charging/discharging\n");
-	else if (battery->state & 0x01)
-		seq_printf(seq, "charging state:          discharging\n");
-	else if (battery->state & 0x02)
-		seq_printf(seq, "charging state:          charging\n");
-	else
-		seq_printf(seq, "charging state:          charged\n");
-
-	if (battery->rate_now == ACPI_BATTERY_VALUE_UNKNOWN)
-		seq_printf(seq, "present rate:            unknown\n");
-	else
-		seq_printf(seq, "present rate:            %d %s\n",
-			   battery->rate_now, acpi_battery_units(battery));
-
-	if (battery->capacity_now == ACPI_BATTERY_VALUE_UNKNOWN)
-		seq_printf(seq, "remaining capacity:      unknown\n");
-	else
-		seq_printf(seq, "remaining capacity:      %d %sh\n",
-			   battery->capacity_now, acpi_battery_units(battery));
-	if (battery->voltage_now == ACPI_BATTERY_VALUE_UNKNOWN)
-		seq_printf(seq, "present voltage:         unknown\n");
-	else
-		seq_printf(seq, "present voltage:         %d mV\n",
-			   battery->voltage_now);
-      end:
-	if (result)
-		seq_printf(seq, "ERROR: Unable to read battery state\n");
-
-	return result;
-}
-
-static int acpi_battery_alarm_proc_show(struct seq_file *seq, void *offset)
-{
-	struct acpi_battery *battery = seq->private;
-	int result = acpi_battery_update(battery, false);
-
-	if (result)
-		goto end;
-
-	if (!acpi_battery_present(battery)) {
-		seq_printf(seq, "present:                 no\n");
-		goto end;
-	}
-	seq_printf(seq, "alarm:                   ");
-	if (battery->alarm) {
-		seq_printf(seq, "%u %sh\n", battery->alarm,
-				acpi_battery_units(battery));
-	} else {
-		seq_printf(seq, "unsupported\n");
-	}
-      end:
-	if (result)
-		seq_printf(seq, "ERROR: Unable to read battery alarm\n");
-	return result;
-}
-
-static ssize_t acpi_battery_write_alarm(struct file *file,
-					const char __user * buffer,
-					size_t count, loff_t * ppos)
-{
-	int result = 0;
-	char alarm_string[12] = { '\0' };
-	struct seq_file *m = file->private_data;
-	struct acpi_battery *battery = m->private;
-
-	if (!battery || (count > sizeof(alarm_string) - 1))
-		return -EINVAL;
-	if (!acpi_battery_present(battery)) {
-		result = -ENODEV;
-		goto end;
-	}
-	if (copy_from_user(alarm_string, buffer, count)) {
-		result = -EFAULT;
-		goto end;
-	}
-	alarm_string[count] = '\0';
-	if (kstrtoint(alarm_string, 0, &battery->alarm)) {
-		result = -EINVAL;
-		goto end;
-	}
-	result = acpi_battery_set_alarm(battery);
-      end:
-	if (result)
-		return result;
-	return count;
-}
-
-static int acpi_battery_alarm_proc_open(struct inode *inode, struct file *file)
-{
-	return single_open(file, acpi_battery_alarm_proc_show, PDE_DATA(inode));
-}
-
-static const struct proc_ops acpi_battery_alarm_proc_ops = {
-	.proc_open	= acpi_battery_alarm_proc_open,
-	.proc_read	= seq_read,
-	.proc_write	= acpi_battery_write_alarm,
-	.proc_lseek	= seq_lseek,
-	.proc_release	= single_release,
-};
-
-static int acpi_battery_add_fs(struct acpi_device *device)
-{
-	pr_warn(PREFIX "Deprecated procfs I/F for battery is loaded, please retry with CONFIG_ACPI_PROCFS_POWER cleared\n");
-	if (!acpi_device_dir(device)) {
-		acpi_device_dir(device) = proc_mkdir(acpi_device_bid(device),
-						     acpi_battery_dir);
-		if (!acpi_device_dir(device))
-			return -ENODEV;
-	}
-
-	if (!proc_create_single_data("info", S_IRUGO, acpi_device_dir(device),
-			acpi_battery_info_proc_show, acpi_driver_data(device)))
-		return -ENODEV;
-	if (!proc_create_single_data("state", S_IRUGO, acpi_device_dir(device),
-			acpi_battery_state_proc_show, acpi_driver_data(device)))
-		return -ENODEV;
-	if (!proc_create_data("alarm", S_IFREG | S_IRUGO | S_IWUSR,
-			acpi_device_dir(device), &acpi_battery_alarm_proc_ops,
-			acpi_driver_data(device)))
-		return -ENODEV;
-	return 0;
-}
-
-static void acpi_battery_remove_fs(struct acpi_device *device)
-{
-	if (!acpi_device_dir(device))
-		return;
-	remove_proc_subtree(acpi_device_bid(device), acpi_battery_dir);
-	acpi_device_dir(device) = NULL;
-}
-
-#endif
-
-/* --------------------------------------------------------------------------
-                                 Driver Interface
-   -------------------------------------------------------------------------- */
-
-static void acpi_battery_notify(struct acpi_device *device, u32 event)
+/* Driver Interface */
+static void acpi_battery_notify(acpi_handle handle, u32 event, void *data)
 {
+	struct acpi_device *device = data;
 	struct acpi_battery *battery = acpi_driver_data(device);
 	struct power_supply *old;
 
 	if (!battery)
 		return;
+
+	guard(mutex)(&battery->update_lock);
+
 	old = battery->bat;
 	/*
-	* On Acer Aspire V5-573G notifications are sometimes triggered too
-	* early. For example, when AC is unplugged and notification is
-	* triggered, battery state is still reported as "Full", and changes to
-	* "Discharging" only after short delay, without any notification.
-	*/
+	 * On Acer Aspire V5-573G notifications are sometimes triggered too
+	 * early. For example, when AC is unplugged and notification is
+	 * triggered, battery state is still reported as "Full", and changes to
+	 * "Discharging" only after short delay, without any notification.
+	 */
 	if (battery_notification_delay_ms > 0)
 		msleep(battery_notification_delay_ms);
 	if (event == ACPI_BATTERY_NOTIFY_INFO)
@@ -1276,21 +1085,22 @@ static void acpi_battery_notify(struct acpi_device *device, u32 event)
 }
 
 static int battery_notify(struct notifier_block *nb,
-			       unsigned long mode, void *_unused)
+			  unsigned long mode, void *_unused)
 {
 	struct acpi_battery *battery = container_of(nb, struct acpi_battery,
 						    pm_nb);
-	int result;
 
-	switch (mode) {
-	case PM_POST_HIBERNATION:
-	case PM_POST_SUSPEND:
+	if (mode == PM_POST_SUSPEND || mode == PM_POST_HIBERNATION) {
+		guard(mutex)(&battery->update_lock);
+
 		if (!acpi_battery_present(battery))
 			return 0;
 
 		if (battery->bat) {
 			acpi_battery_refresh(battery);
 		} else {
+			int result;
+
 			result = acpi_battery_get_info(battery);
 			if (result)
 				return result;
@@ -1302,7 +1112,6 @@ static int battery_notify(struct notifier_block *nb,
 
 		acpi_battery_init_alarm(battery);
 		acpi_battery_get_state(battery);
-		break;
 	}
 
 	return 0;
@@ -1329,13 +1138,6 @@ battery_ac_is_broken_quirk(const struct dmi_system_id *d)
 	return 0;
 }
 
-static int __init
-battery_do_not_check_pmic_quirk(const struct dmi_system_id *d)
-{
-	battery_check_pmic = 0;
-	return 0;
-}
-
 static const struct dmi_system_id bat_dmi_table[] __initconst = {
 	{
 		/* NEC LZ750/LS */
@@ -1365,19 +1167,11 @@ static const struct dmi_system_id bat_dmi_table[] __initconst = {
 		},
 	},
 	{
-		/* ECS EF20EA, AXP288 PMIC but uses separate fuel-gauge */
-		.callback = battery_do_not_check_pmic_quirk,
-		.matches = {
-			DMI_MATCH(DMI_PRODUCT_NAME, "EF20EA"),
-		},
-	},
-	{
-		/* Lenovo Ideapad Miix 320, AXP288 PMIC, separate fuel-gauge */
-		.callback = battery_do_not_check_pmic_quirk,
+		/* Microsoft Surface Go 3 */
+		.callback = battery_notification_delay_quirk,
 		.matches = {
-			DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
-			DMI_MATCH(DMI_PRODUCT_NAME, "80XF"),
-			DMI_MATCH(DMI_PRODUCT_VERSION, "Lenovo MIIX 320-10ICR"),
+			DMI_MATCH(DMI_SYS_VENDOR, "Microsoft Corporation"),
+			DMI_MATCH(DMI_PRODUCT_NAME, "Surface Go 3"),
 		},
 	},
 	{},
@@ -1395,6 +1189,8 @@ static int acpi_battery_update_retry(struct acpi_battery *battery)
 {
 	int retry, ret;
 
+	guard(mutex)(&battery->update_lock);
+
 	for (retry = 5; retry; retry--) {
 		ret = acpi_battery_update(battery, false);
 		if (!ret)
@@ -1405,10 +1201,17 @@ static int acpi_battery_update_retry(struct acpi_battery *battery)
 	return ret;
 }
 
+static void sysfs_battery_cleanup(struct acpi_battery *battery)
+{
+	guard(mutex)(&battery->update_lock);
+
+	sysfs_remove_battery(battery);
+}
+
 static int acpi_battery_add(struct acpi_device *device)
 {
 	int result = 0;
-	struct acpi_battery *battery = NULL;
+	struct acpi_battery *battery;
 
 	if (!device)
 		return -EINVAL;
@@ -1416,15 +1219,18 @@ static int acpi_battery_add(struct acpi_device *device)
 	if (device->dep_unmet)
 		return -EPROBE_DEFER;
 
-	battery = kzalloc(sizeof(struct acpi_battery), GFP_KERNEL);
+	battery = devm_kzalloc(&device->dev, sizeof(*battery), GFP_KERNEL);
 	if (!battery)
 		return -ENOMEM;
 	battery->device = device;
-	strcpy(acpi_device_name(device), ACPI_BATTERY_DEVICE_NAME);
-	strcpy(acpi_device_class(device), ACPI_BATTERY_CLASS);
+	strscpy(acpi_device_name(device), ACPI_BATTERY_DEVICE_NAME);
+	strscpy(acpi_device_class(device), ACPI_BATTERY_CLASS);
 	device->driver_data = battery;
-	mutex_init(&battery->lock);
-	mutex_init(&battery->sysfs_lock);
+
+	result = devm_mutex_init(&device->dev, &battery->update_lock);
+	if (result)
+		return result;
+
 	if (acpi_has_method(battery->device->handle, "_BIX"))
 		set_bit(ACPI_BATTERY_XINFO_PRESENT, &battery->flags);
 
@@ -1432,53 +1238,52 @@ static int acpi_battery_add(struct acpi_device *device)
 	if (result)
 		goto fail;
 
-#ifdef CONFIG_ACPI_PROCFS_POWER
-	result = acpi_battery_add_fs(device);
-	if (result) {
-		acpi_battery_remove_fs(device);
-		goto fail;
-	}
-#endif
-
-	pr_info(PREFIX "%s Slot [%s] (battery %s)\n",
-		ACPI_BATTERY_DEVICE_NAME, acpi_device_bid(device),
+	pr_info("Slot [%s] (battery %s)\n", acpi_device_bid(device),
 		device->status.battery_present ? "present" : "absent");
 
 	battery->pm_nb.notifier_call = battery_notify;
-	register_pm_notifier(&battery->pm_nb);
+	result = register_pm_notifier(&battery->pm_nb);
+	if (result)
+		goto fail;
 
 	device_init_wakeup(&device->dev, 1);
 
-	return result;
+	result = acpi_dev_install_notify_handler(device, ACPI_ALL_NOTIFY,
+						 acpi_battery_notify, device);
+	if (result)
+		goto fail_pm;
 
+	return 0;
+
+fail_pm:
+	device_init_wakeup(&device->dev, 0);
+	unregister_pm_notifier(&battery->pm_nb);
 fail:
-	sysfs_remove_battery(battery);
-	mutex_destroy(&battery->lock);
-	mutex_destroy(&battery->sysfs_lock);
-	kfree(battery);
+	sysfs_battery_cleanup(battery);
+
 	return result;
 }
 
-static int acpi_battery_remove(struct acpi_device *device)
+static void acpi_battery_remove(struct acpi_device *device)
 {
-	struct acpi_battery *battery = NULL;
+	struct acpi_battery *battery;
 
 	if (!device || !acpi_driver_data(device))
-		return -EINVAL;
-	device_init_wakeup(&device->dev, 0);
+		return;
+
 	battery = acpi_driver_data(device);
+
+	acpi_dev_remove_notify_handler(device, ACPI_ALL_NOTIFY,
+				       acpi_battery_notify);
+
+	device_init_wakeup(&device->dev, 0);
 	unregister_pm_notifier(&battery->pm_nb);
-#ifdef CONFIG_ACPI_PROCFS_POWER
-	acpi_battery_remove_fs(device);
-#endif
+
+	guard(mutex)(&battery->update_lock);
+
 	sysfs_remove_battery(battery);
-	mutex_destroy(&battery->lock);
-	mutex_destroy(&battery->sysfs_lock);
-	kfree(battery);
-	return 0;
 }
 
-#ifdef CONFIG_PM_SLEEP
 /* this is needed to learn about changes made in suspended state */
 static int acpi_battery_resume(struct device *dev)
 {
@@ -1492,78 +1297,41 @@ static int acpi_battery_resume(struct device *dev)
 		return -EINVAL;
 
 	battery->update_time = 0;
+
+	guard(mutex)(&battery->update_lock);
+
 	acpi_battery_update(battery, true);
 	return 0;
 }
-#else
-#define acpi_battery_resume NULL
-#endif
 
-static SIMPLE_DEV_PM_OPS(acpi_battery_pm, NULL, acpi_battery_resume);
+static DEFINE_SIMPLE_DEV_PM_OPS(acpi_battery_pm, NULL, acpi_battery_resume);
 
 static struct acpi_driver acpi_battery_driver = {
 	.name = "battery",
 	.class = ACPI_BATTERY_CLASS,
 	.ids = battery_device_ids,
-	.flags = ACPI_DRIVER_ALL_NOTIFY_EVENTS,
 	.ops = {
 		.add = acpi_battery_add,
 		.remove = acpi_battery_remove,
-		.notify = acpi_battery_notify,
 		},
-	.drv.pm = &acpi_battery_pm,
+	.drv.pm = pm_sleep_ptr(&acpi_battery_pm),
+	.drv.probe_type = PROBE_PREFER_ASYNCHRONOUS,
 };
 
-static void __init acpi_battery_init_async(void *unused, async_cookie_t cookie)
-{
-	unsigned int i;
-	int result;
-
-	dmi_check_system(bat_dmi_table);
-
-	if (battery_check_pmic) {
-		for (i = 0; i < ARRAY_SIZE(acpi_battery_blacklist); i++)
-			if (acpi_dev_present(acpi_battery_blacklist[i], "1", -1)) {
-				pr_info(PREFIX ACPI_BATTERY_DEVICE_NAME
-					": found native %s PMIC, not loading\n",
-					acpi_battery_blacklist[i]);
-				return;
-			}
-	}
-
-#ifdef CONFIG_ACPI_PROCFS_POWER
-	acpi_battery_dir = acpi_lock_battery_dir();
-	if (!acpi_battery_dir)
-		return;
-#endif
-	result = acpi_bus_register_driver(&acpi_battery_driver);
-#ifdef CONFIG_ACPI_PROCFS_POWER
-	if (result < 0)
-		acpi_unlock_battery_dir(acpi_battery_dir);
-#endif
-	battery_driver_registered = (result == 0);
-}
-
 static int __init acpi_battery_init(void)
 {
-	if (acpi_disabled)
+	if (acpi_disabled || acpi_quirk_skip_acpi_ac_and_battery())
 		return -ENODEV;
 
-	async_cookie = async_schedule(acpi_battery_init_async, NULL);
-	return 0;
+	dmi_check_system(bat_dmi_table);
+
+	return acpi_bus_register_driver(&acpi_battery_driver);
 }
 
 static void __exit acpi_battery_exit(void)
 {
-	async_synchronize_cookie(async_cookie + 1);
-	if (battery_driver_registered) {
-		acpi_bus_unregister_driver(&acpi_battery_driver);
-		battery_hook_exit();
-	}
-#ifdef CONFIG_ACPI_PROCFS_POWER
-	if (acpi_battery_dir)
-		acpi_unlock_battery_dir(acpi_battery_dir);
-#endif
+	acpi_bus_unregister_driver(&acpi_battery_driver);
+	battery_hook_exit();
 }
 
 module_init(acpi_battery_init);
diff --git a/drivers/acpi/bgrt.c b/drivers/acpi/bgrt.c
index 251f961c28cc..0fdd581ef96f 100644
--- a/drivers/acpi/bgrt.c
+++ b/drivers/acpi/bgrt.c
@@ -15,60 +15,32 @@
 static void *bgrt_image;
 static struct kobject *bgrt_kobj;
 
-static ssize_t show_version(struct device *dev,
-			    struct device_attribute *attr, char *buf)
-{
-	return snprintf(buf, PAGE_SIZE, "%d\n", bgrt_tab.version);
-}
-static DEVICE_ATTR(version, S_IRUGO, show_version, NULL);
-
-static ssize_t show_status(struct device *dev,
-			   struct device_attribute *attr, char *buf)
-{
-	return snprintf(buf, PAGE_SIZE, "%d\n", bgrt_tab.status);
-}
-static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
-
-static ssize_t show_type(struct device *dev,
-			 struct device_attribute *attr, char *buf)
-{
-	return snprintf(buf, PAGE_SIZE, "%d\n", bgrt_tab.image_type);
-}
-static DEVICE_ATTR(type, S_IRUGO, show_type, NULL);
-
-static ssize_t show_xoffset(struct device *dev,
-			    struct device_attribute *attr, char *buf)
-{
-	return snprintf(buf, PAGE_SIZE, "%d\n", bgrt_tab.image_offset_x);
-}
-static DEVICE_ATTR(xoffset, S_IRUGO, show_xoffset, NULL);
-
-static ssize_t show_yoffset(struct device *dev,
-			    struct device_attribute *attr, char *buf)
-{
-	return snprintf(buf, PAGE_SIZE, "%d\n", bgrt_tab.image_offset_y);
-}
-static DEVICE_ATTR(yoffset, S_IRUGO, show_yoffset, NULL);
-
-static ssize_t image_read(struct file *file, struct kobject *kobj,
-	       struct bin_attribute *attr, char *buf, loff_t off, size_t count)
-{
-	memcpy(buf, attr->private + off, count);
-	return count;
-}
-
-static BIN_ATTR_RO(image, 0);	/* size gets filled in later */
+#define BGRT_SHOW(_name, _member) \
+	static ssize_t _name##_show(struct kobject *kobj,			\
+				    struct kobj_attribute *attr, char *buf)	\
+	{									\
+		return sysfs_emit(buf, "%d\n", bgrt_tab._member);		\
+	}									\
+	static struct kobj_attribute bgrt_attr_##_name = __ATTR_RO(_name)
+
+BGRT_SHOW(version, version);
+BGRT_SHOW(status, status);
+BGRT_SHOW(type, image_type);
+BGRT_SHOW(xoffset, image_offset_x);
+BGRT_SHOW(yoffset, image_offset_y);
+
+static __ro_after_init BIN_ATTR_SIMPLE_RO(image);
 
 static struct attribute *bgrt_attributes[] = {
-	&dev_attr_version.attr,
-	&dev_attr_status.attr,
-	&dev_attr_type.attr,
-	&dev_attr_xoffset.attr,
-	&dev_attr_yoffset.attr,
+	&bgrt_attr_version.attr,
+	&bgrt_attr_status.attr,
+	&bgrt_attr_type.attr,
+	&bgrt_attr_xoffset.attr,
+	&bgrt_attr_yoffset.attr,
 	NULL,
 };
 
-static struct bin_attribute *bgrt_bin_attributes[] = {
+static const struct bin_attribute *const bgrt_bin_attributes[] = {
 	&bin_attr_image,
 	NULL,
 };
diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c
index 54002670cb7a..a984ccd4a2a0 100644
--- a/drivers/acpi/bus.c
+++ b/drivers/acpi/bus.c
@@ -5,6 +5,8 @@
  *  Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
  */
 
+#define pr_fmt(fmt) "ACPI: " fmt
+
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/ioport.h>
@@ -24,16 +26,14 @@
 #include <asm/mpspec.h>
 #include <linux/dmi.h>
 #endif
-#include <linux/acpi_iort.h>
+#include <linux/acpi_viot.h>
 #include <linux/pci.h>
 #include <acpi/apei.h>
 #include <linux/suspend.h>
+#include <linux/prmt.h>
 
 #include "internal.h"
 
-#define _COMPONENT		ACPI_BUS_COMPONENT
-ACPI_MODULE_NAME("bus");
-
 struct acpi_device *acpi_root;
 struct proc_dir_entry *acpi_root_dir;
 EXPORT_SYMBOL(acpi_root_dir);
@@ -47,8 +47,7 @@ static inline int set_copy_dsdt(const struct dmi_system_id *id)
 #else
 static int set_copy_dsdt(const struct dmi_system_id *id)
 {
-	printk(KERN_NOTICE "%s detected - "
-		"force copy of DSDT to local memory\n", id->ident);
+	pr_notice("%s detected - force copy of DSDT to local memory\n", id->ident);
 	acpi_gbl_copy_dsdt_locally = 1;
 	return 0;
 }
@@ -98,8 +97,8 @@ int acpi_bus_get_status(struct acpi_device *device)
 	acpi_status status;
 	unsigned long long sta;
 
-	if (acpi_device_always_present(device)) {
-		acpi_set_device_status(device, ACPI_STA_DEFAULT);
+	if (acpi_device_override_status(device, &sta)) {
+		acpi_set_device_status(device, sta);
 		return 0;
 	}
 
@@ -113,16 +112,25 @@ int acpi_bus_get_status(struct acpi_device *device)
 	if (ACPI_FAILURE(status))
 		return -ENODEV;
 
+	if (!device->status.present && device->status.enabled) {
+		pr_info(FW_BUG "Device [%s] status [%08x]: not present and enabled\n",
+			device->pnp.bus_id, (u32)sta);
+		device->status.enabled = 0;
+		/*
+		 * The status is clearly invalid, so clear the functional bit as
+		 * well to avoid attempting to use the device.
+		 */
+		device->status.functional = 0;
+	}
+
 	acpi_set_device_status(device, sta);
 
 	if (device->status.functional && !device->status.present) {
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Device [%s] status [%08x]: "
-		       "functional but not present;\n",
-			device->pnp.bus_id, (u32)sta));
+		pr_debug("Device [%s] status [%08x]: functional but not present\n",
+			 device->pnp.bus_id, (u32)sta);
 	}
 
-	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Device [%s] status [%08x]\n",
-			  device->pnp.bus_id, (u32)sta));
+	pr_debug("Device [%s] status [%08x]\n", device->pnp.bus_id, (u32)sta);
 	return 0;
 }
 EXPORT_SYMBOL(acpi_bus_get_status);
@@ -266,8 +274,6 @@ out_success:
 
 out_kfree:
 	kfree(output.pointer);
-	if (status != AE_OK)
-		context->ret.pointer = NULL;
 	return status;
 }
 EXPORT_SYMBOL(acpi_run_osc);
@@ -281,10 +287,32 @@ bool osc_sb_apei_support_acked;
 bool osc_pc_lpi_support_confirmed;
 EXPORT_SYMBOL_GPL(osc_pc_lpi_support_confirmed);
 
+/*
+ * ACPI 6.2 Section 6.2.11.2 'Platform-Wide OSPM Capabilities':
+ *   Starting with ACPI Specification 6.2, all _CPC registers can be in
+ *   PCC, System Memory, System IO, or Functional Fixed Hardware address
+ *   spaces. OSPM support for this more flexible register space scheme is
+ *   indicated by the “Flexible Address Space for CPPC Registers” _OSC bit.
+ *
+ * Otherwise (cf ACPI 6.1, s8.4.7.1.1.X), _CPC registers must be in:
+ * - PCC or Functional Fixed Hardware address space if defined
+ * - SystemMemory address space (NULL register) if not defined
+ */
+bool osc_cpc_flexible_adr_space_confirmed;
+EXPORT_SYMBOL_GPL(osc_cpc_flexible_adr_space_confirmed);
+
+/*
+ * ACPI 6.4 Operating System Capabilities for USB.
+ */
+bool osc_sb_native_usb4_support_confirmed;
+EXPORT_SYMBOL_GPL(osc_sb_native_usb4_support_confirmed);
+
+bool osc_sb_cppc2_support_acked;
+
 static u8 sb_uuid_str[] = "0811B06E-4A27-44F9-8D60-3CBBC22E7B48";
-static void acpi_bus_osc_support(void)
+static void acpi_bus_osc_negotiate_platform_control(void)
 {
-	u32 capbuf[2];
+	u32 capbuf[2], *capbuf_ret;
 	struct acpi_osc_context context = {
 		.uuid_str = sb_uuid_str,
 		.rev = 1,
@@ -299,35 +327,173 @@ static void acpi_bus_osc_support(void)
 		capbuf[OSC_SUPPORT_DWORD] |= OSC_SB_PAD_SUPPORT;
 	if (IS_ENABLED(CONFIG_ACPI_PROCESSOR))
 		capbuf[OSC_SUPPORT_DWORD] |= OSC_SB_PPC_OST_SUPPORT;
+	if (IS_ENABLED(CONFIG_ACPI_THERMAL))
+		capbuf[OSC_SUPPORT_DWORD] |= OSC_SB_FAST_THERMAL_SAMPLING_SUPPORT;
+	if (IS_ENABLED(CONFIG_ACPI_BATTERY))
+		capbuf[OSC_SUPPORT_DWORD] |= OSC_SB_BATTERY_CHARGE_LIMITING_SUPPORT;
 
 	capbuf[OSC_SUPPORT_DWORD] |= OSC_SB_HOTPLUG_OST_SUPPORT;
 	capbuf[OSC_SUPPORT_DWORD] |= OSC_SB_PCLPI_SUPPORT;
-
+	capbuf[OSC_SUPPORT_DWORD] |= OSC_SB_OVER_16_PSTATES_SUPPORT;
+	capbuf[OSC_SUPPORT_DWORD] |= OSC_SB_GED_SUPPORT;
+	capbuf[OSC_SUPPORT_DWORD] |= OSC_SB_IRQ_RESOURCE_SOURCE_SUPPORT;
+	if (IS_ENABLED(CONFIG_ACPI_PRMT))
+		capbuf[OSC_SUPPORT_DWORD] |= OSC_SB_PRM_SUPPORT;
+	if (IS_ENABLED(CONFIG_ACPI_FFH))
+		capbuf[OSC_SUPPORT_DWORD] |= OSC_SB_FFH_OPR_SUPPORT;
+
+#ifdef CONFIG_ARM64
+	capbuf[OSC_SUPPORT_DWORD] |= OSC_SB_GENERIC_INITIATOR_SUPPORT;
+#endif
 #ifdef CONFIG_X86
-	if (boot_cpu_has(X86_FEATURE_HWP)) {
-		capbuf[OSC_SUPPORT_DWORD] |= OSC_SB_CPC_SUPPORT;
-		capbuf[OSC_SUPPORT_DWORD] |= OSC_SB_CPCV2_SUPPORT;
-	}
+	capbuf[OSC_SUPPORT_DWORD] |= OSC_SB_GENERIC_INITIATOR_SUPPORT;
 #endif
 
+#ifdef CONFIG_ACPI_CPPC_LIB
+	capbuf[OSC_SUPPORT_DWORD] |= OSC_SB_CPC_SUPPORT;
+	capbuf[OSC_SUPPORT_DWORD] |= OSC_SB_CPCV2_SUPPORT;
+#endif
+
+	capbuf[OSC_SUPPORT_DWORD] |= OSC_SB_CPC_FLEXIBLE_ADR_SPACE;
+
 	if (IS_ENABLED(CONFIG_SCHED_MC_PRIO))
 		capbuf[OSC_SUPPORT_DWORD] |= OSC_SB_CPC_DIVERSE_HIGH_SUPPORT;
 
+	if (IS_ENABLED(CONFIG_USB4))
+		capbuf[OSC_SUPPORT_DWORD] |= OSC_SB_NATIVE_USB4_SUPPORT;
+
 	if (!ghes_disable)
 		capbuf[OSC_SUPPORT_DWORD] |= OSC_SB_APEI_SUPPORT;
 	if (ACPI_FAILURE(acpi_get_handle(NULL, "\\_SB", &handle)))
 		return;
-	if (ACPI_SUCCESS(acpi_run_osc(handle, &context))) {
-		u32 *capbuf_ret = context.ret.pointer;
-		if (context.ret.length > OSC_SUPPORT_DWORD) {
-			osc_sb_apei_support_acked =
-				capbuf_ret[OSC_SUPPORT_DWORD] & OSC_SB_APEI_SUPPORT;
-			osc_pc_lpi_support_confirmed =
-				capbuf_ret[OSC_SUPPORT_DWORD] & OSC_SB_PCLPI_SUPPORT;
-		}
+
+	if (ACPI_FAILURE(acpi_run_osc(handle, &context)))
+		return;
+
+	capbuf_ret = context.ret.pointer;
+	if (context.ret.length <= OSC_SUPPORT_DWORD) {
 		kfree(context.ret.pointer);
+		return;
+	}
+
+	/*
+	 * Now run _OSC again with query flag clear and with the caps
+	 * supported by both the OS and the platform.
+	 */
+	capbuf[OSC_QUERY_DWORD] = 0;
+	capbuf[OSC_SUPPORT_DWORD] = capbuf_ret[OSC_SUPPORT_DWORD];
+	kfree(context.ret.pointer);
+
+	if (ACPI_FAILURE(acpi_run_osc(handle, &context)))
+		return;
+
+	capbuf_ret = context.ret.pointer;
+	if (context.ret.length > OSC_SUPPORT_DWORD) {
+#ifdef CONFIG_ACPI_CPPC_LIB
+		osc_sb_cppc2_support_acked = capbuf_ret[OSC_SUPPORT_DWORD] & OSC_SB_CPCV2_SUPPORT;
+#endif
+
+		osc_sb_apei_support_acked =
+			capbuf_ret[OSC_SUPPORT_DWORD] & OSC_SB_APEI_SUPPORT;
+		osc_pc_lpi_support_confirmed =
+			capbuf_ret[OSC_SUPPORT_DWORD] & OSC_SB_PCLPI_SUPPORT;
+		osc_sb_native_usb4_support_confirmed =
+			capbuf_ret[OSC_SUPPORT_DWORD] & OSC_SB_NATIVE_USB4_SUPPORT;
+		osc_cpc_flexible_adr_space_confirmed =
+			capbuf_ret[OSC_SUPPORT_DWORD] & OSC_SB_CPC_FLEXIBLE_ADR_SPACE;
+	}
+
+	kfree(context.ret.pointer);
+}
+
+/*
+ * Native control of USB4 capabilities. If any of the tunneling bits is
+ * set it means OS is in control and we use software based connection
+ * manager.
+ */
+u32 osc_sb_native_usb4_control;
+EXPORT_SYMBOL_GPL(osc_sb_native_usb4_control);
+
+static void acpi_bus_decode_usb_osc(const char *msg, u32 bits)
+{
+	pr_info("%s USB3%c DisplayPort%c PCIe%c XDomain%c\n", msg,
+	       (bits & OSC_USB_USB3_TUNNELING) ? '+' : '-',
+	       (bits & OSC_USB_DP_TUNNELING) ? '+' : '-',
+	       (bits & OSC_USB_PCIE_TUNNELING) ? '+' : '-',
+	       (bits & OSC_USB_XDOMAIN) ? '+' : '-');
+}
+
+static u8 sb_usb_uuid_str[] = "23A0D13A-26AB-486C-9C5F-0FFA525A575A";
+static void acpi_bus_osc_negotiate_usb_control(void)
+{
+	u32 capbuf[3], *capbuf_ret;
+	struct acpi_osc_context context = {
+		.uuid_str = sb_usb_uuid_str,
+		.rev = 1,
+		.cap.length = sizeof(capbuf),
+		.cap.pointer = capbuf,
+	};
+	acpi_handle handle;
+	acpi_status status;
+	u32 control;
+
+	if (!osc_sb_native_usb4_support_confirmed)
+		return;
+
+	if (ACPI_FAILURE(acpi_get_handle(NULL, "\\_SB", &handle)))
+		return;
+
+	control = OSC_USB_USB3_TUNNELING | OSC_USB_DP_TUNNELING |
+		  OSC_USB_PCIE_TUNNELING | OSC_USB_XDOMAIN;
+
+	/*
+	 * Run _OSC first with query bit set, trying to get control over
+	 * all tunneling. The platform can then clear out bits in the
+	 * control dword that it does not want to grant to the OS.
+	 */
+	capbuf[OSC_QUERY_DWORD] = OSC_QUERY_ENABLE;
+	capbuf[OSC_SUPPORT_DWORD] = 0;
+	capbuf[OSC_CONTROL_DWORD] = control;
+
+	status = acpi_run_osc(handle, &context);
+	if (ACPI_FAILURE(status))
+		return;
+
+	if (context.ret.length != sizeof(capbuf)) {
+		pr_info("USB4 _OSC: returned invalid length buffer\n");
+		goto out_free;
+	}
+
+	/*
+	 * Run _OSC again now with query bit clear and the control dword
+	 * matching what the platform granted (which may not have all
+	 * the control bits set).
+	 */
+	capbuf_ret = context.ret.pointer;
+
+	capbuf[OSC_QUERY_DWORD] = 0;
+	capbuf[OSC_CONTROL_DWORD] = capbuf_ret[OSC_CONTROL_DWORD];
+
+	kfree(context.ret.pointer);
+
+	status = acpi_run_osc(handle, &context);
+	if (ACPI_FAILURE(status))
+		return;
+
+	if (context.ret.length != sizeof(capbuf)) {
+		pr_info("USB4 _OSC: returned invalid length buffer\n");
+		goto out_free;
 	}
-	/* do we need to check other returned cap? Sounds no */
+
+	osc_sb_native_usb4_control =
+		control & acpi_osc_ctx_get_pci_control(&context);
+
+	acpi_bus_decode_usb_osc("USB4 _OSC: OS supports", control);
+	acpi_bus_decode_usb_osc("USB4 _OSC: OS controls",
+				osc_sb_native_usb4_control);
+
+out_free:
+	kfree(context.ret.pointer);
 }
 
 /* --------------------------------------------------------------------------
@@ -335,142 +501,126 @@ static void acpi_bus_osc_support(void)
    -------------------------------------------------------------------------- */
 
 /**
- * acpi_bus_notify
- * ---------------
- * Callback for all 'system-level' device notifications (values 0x00-0x7F).
+ * acpi_bus_notify - Global system-level (0x00-0x7F) notifications handler
+ * @handle: Target ACPI object.
+ * @type: Notification type.
+ * @data: Ignored.
+ *
+ * This only handles notifications related to device hotplug.
  */
 static void acpi_bus_notify(acpi_handle handle, u32 type, void *data)
 {
 	struct acpi_device *adev;
-	struct acpi_driver *driver;
-	u32 ost_code = ACPI_OST_SC_NON_SPECIFIC_FAILURE;
-	bool hotplug_event = false;
 
 	switch (type) {
 	case ACPI_NOTIFY_BUS_CHECK:
 		acpi_handle_debug(handle, "ACPI_NOTIFY_BUS_CHECK event\n");
-		hotplug_event = true;
 		break;
 
 	case ACPI_NOTIFY_DEVICE_CHECK:
 		acpi_handle_debug(handle, "ACPI_NOTIFY_DEVICE_CHECK event\n");
-		hotplug_event = true;
 		break;
 
 	case ACPI_NOTIFY_DEVICE_WAKE:
 		acpi_handle_debug(handle, "ACPI_NOTIFY_DEVICE_WAKE event\n");
-		break;
+		return;
 
 	case ACPI_NOTIFY_EJECT_REQUEST:
 		acpi_handle_debug(handle, "ACPI_NOTIFY_EJECT_REQUEST event\n");
-		hotplug_event = true;
 		break;
 
 	case ACPI_NOTIFY_DEVICE_CHECK_LIGHT:
 		acpi_handle_debug(handle, "ACPI_NOTIFY_DEVICE_CHECK_LIGHT event\n");
 		/* TBD: Exactly what does 'light' mean? */
-		break;
+		return;
 
 	case ACPI_NOTIFY_FREQUENCY_MISMATCH:
 		acpi_handle_err(handle, "Device cannot be configured due "
 				"to a frequency mismatch\n");
-		break;
+		return;
 
 	case ACPI_NOTIFY_BUS_MODE_MISMATCH:
 		acpi_handle_err(handle, "Device cannot be configured due "
 				"to a bus mode mismatch\n");
-		break;
+		return;
 
 	case ACPI_NOTIFY_POWER_FAULT:
 		acpi_handle_err(handle, "Device has suffered a power fault\n");
-		break;
+		return;
 
 	default:
 		acpi_handle_debug(handle, "Unknown event type 0x%x\n", type);
-		break;
-	}
-
-	adev = acpi_bus_get_acpi_device(handle);
-	if (!adev)
-		goto err;
-
-	driver = adev->driver;
-	if (driver && driver->ops.notify &&
-	    (driver->flags & ACPI_DRIVER_ALL_NOTIFY_EVENTS))
-		driver->ops.notify(adev, type);
-
-	if (!hotplug_event) {
-		acpi_bus_put_acpi_device(adev);
 		return;
 	}
 
-	if (ACPI_SUCCESS(acpi_hotplug_schedule(adev, type)))
+	adev = acpi_get_acpi_dev(handle);
+
+	if (adev && ACPI_SUCCESS(acpi_hotplug_schedule(adev, type)))
 		return;
 
-	acpi_bus_put_acpi_device(adev);
+	acpi_put_acpi_dev(adev);
 
- err:
-	acpi_evaluate_ost(handle, type, ost_code, NULL);
+	acpi_evaluate_ost(handle, type, ACPI_OST_SC_NON_SPECIFIC_FAILURE, NULL);
 }
 
-static void acpi_device_notify(acpi_handle handle, u32 event, void *data)
+static void acpi_notify_device(acpi_handle handle, u32 event, void *data)
 {
 	struct acpi_device *device = data;
+	struct acpi_driver *acpi_drv = to_acpi_driver(device->dev.driver);
 
-	device->driver->ops.notify(device, event);
+	acpi_drv->ops.notify(device, event);
 }
 
-static void acpi_device_notify_fixed(void *data)
+static int acpi_device_install_notify_handler(struct acpi_device *device,
+					      struct acpi_driver *acpi_drv)
 {
-	struct acpi_device *device = data;
+	u32 type = acpi_drv->flags & ACPI_DRIVER_ALL_NOTIFY_EVENTS ?
+				ACPI_ALL_NOTIFY : ACPI_DEVICE_NOTIFY;
+	acpi_status status;
+
+	status = acpi_install_notify_handler(device->handle, type,
+					     acpi_notify_device, device);
+	if (ACPI_FAILURE(status))
+		return -EINVAL;
 
-	/* Fixed hardware devices have no handles */
-	acpi_device_notify(NULL, ACPI_FIXED_HARDWARE_EVENT, device);
+	return 0;
 }
 
-static u32 acpi_device_fixed_event(void *data)
+static void acpi_device_remove_notify_handler(struct acpi_device *device,
+					      struct acpi_driver *acpi_drv)
 {
-	acpi_os_execute(OSL_NOTIFY_HANDLER, acpi_device_notify_fixed, data);
-	return ACPI_INTERRUPT_HANDLED;
+	u32 type = acpi_drv->flags & ACPI_DRIVER_ALL_NOTIFY_EVENTS ?
+				ACPI_ALL_NOTIFY : ACPI_DEVICE_NOTIFY;
+
+	acpi_remove_notify_handler(device->handle, type,
+				   acpi_notify_device);
+
+	acpi_os_wait_events_complete();
 }
 
-static int acpi_device_install_notify_handler(struct acpi_device *device)
+int acpi_dev_install_notify_handler(struct acpi_device *adev,
+				    u32 handler_type,
+				    acpi_notify_handler handler, void *context)
 {
 	acpi_status status;
 
-	if (device->device_type == ACPI_BUS_TYPE_POWER_BUTTON)
-		status =
-		    acpi_install_fixed_event_handler(ACPI_EVENT_POWER_BUTTON,
-						     acpi_device_fixed_event,
-						     device);
-	else if (device->device_type == ACPI_BUS_TYPE_SLEEP_BUTTON)
-		status =
-		    acpi_install_fixed_event_handler(ACPI_EVENT_SLEEP_BUTTON,
-						     acpi_device_fixed_event,
-						     device);
-	else
-		status = acpi_install_notify_handler(device->handle,
-						     ACPI_DEVICE_NOTIFY,
-						     acpi_device_notify,
-						     device);
-
+	status = acpi_install_notify_handler(adev->handle, handler_type,
+					     handler, context);
 	if (ACPI_FAILURE(status))
-		return -EINVAL;
+		return -ENODEV;
+
 	return 0;
 }
+EXPORT_SYMBOL_GPL(acpi_dev_install_notify_handler);
 
-static void acpi_device_remove_notify_handler(struct acpi_device *device)
+void acpi_dev_remove_notify_handler(struct acpi_device *adev,
+				    u32 handler_type,
+				    acpi_notify_handler handler)
 {
-	if (device->device_type == ACPI_BUS_TYPE_POWER_BUTTON)
-		acpi_remove_fixed_event_handler(ACPI_EVENT_POWER_BUTTON,
-						acpi_device_fixed_event);
-	else if (device->device_type == ACPI_BUS_TYPE_SLEEP_BUTTON)
-		acpi_remove_fixed_event_handler(ACPI_EVENT_SLEEP_BUTTON,
-						acpi_device_fixed_event);
-	else
-		acpi_remove_notify_handler(device->handle, ACPI_DEVICE_NOTIFY,
-					   acpi_device_notify);
+	acpi_remove_notify_handler(adev->handle, handler_type, handler);
+	acpi_os_wait_events_complete();
 }
+EXPORT_SYMBOL_GPL(acpi_dev_remove_notify_handler);
 
 /* Handle events targeting \_SB device (at present only graceful shutdown) */
 
@@ -504,8 +654,9 @@ static void acpi_sb_notify(acpi_handle handle, u32 event, void *data)
 	if (event == ACPI_SB_NOTIFY_SHUTDOWN_REQUEST) {
 		if (!work_busy(&acpi_sb_work))
 			schedule_work(&acpi_sb_work);
-	} else
+	} else {
 		pr_warn("event %x is not supported by \\_SB device\n", event);
+	}
 }
 
 static int __init acpi_setup_sb_notify_handler(void)
@@ -551,6 +702,7 @@ struct device *acpi_get_first_physical_node(struct acpi_device *adev)
 	mutex_unlock(physical_node_lock);
 	return phys_dev;
 }
+EXPORT_SYMBOL_GPL(acpi_get_first_physical_node);
 
 static struct acpi_device *acpi_primary_dev_companion(struct acpi_device *adev,
 						      const struct device *dev)
@@ -598,7 +750,7 @@ bool acpi_device_is_first_physical_node(struct acpi_device *adev,
  * resources available from it but they will be matched normally using functions
  * provided by their bus types (and analogously for their modalias).
  */
-struct acpi_device *acpi_companion_match(const struct device *dev)
+const struct acpi_device *acpi_companion_match(const struct device *dev)
 {
 	struct acpi_device *adev;
 
@@ -622,7 +774,7 @@ struct acpi_device *acpi_companion_match(const struct device *dev)
  * identifiers and a _DSD object with the "compatible" property, use that
  * property to match against the given list of identifiers.
  */
-static bool acpi_of_match_device(struct acpi_device *adev,
+static bool acpi_of_match_device(const struct acpi_device *adev,
 				 const struct of_device_id *of_match_table,
 				 const struct of_device_id **of_id)
 {
@@ -676,7 +828,7 @@ static bool acpi_of_modalias(struct acpi_device *adev,
 
 	str = obj->string.pointer;
 	chr = strchr(str, ',');
-	strlcpy(modalias, chr ? chr + 1 : str, len);
+	strscpy(modalias, chr ? chr + 1 : str, len);
 
 	return true;
 }
@@ -688,15 +840,16 @@ static bool acpi_of_modalias(struct acpi_device *adev,
  * @modalias:   Pointer to buffer that modalias value will be copied into
  * @len:	Length of modalias buffer
  *
- * This is a counterpart of of_modalias_node() for struct acpi_device objects.
- * If there is a compatible string for @adev, it will be copied to @modalias
- * with the vendor prefix stripped; otherwise, @default_id will be used.
+ * This is a counterpart of of_alias_from_compatible() for struct acpi_device
+ * objects. If there is a compatible string for @adev, it will be copied to
+ * @modalias with the vendor prefix stripped; otherwise, @default_id will be
+ * used.
  */
 void acpi_set_modalias(struct acpi_device *adev, const char *default_id,
 		       char *modalias, size_t len)
 {
 	if (!acpi_of_modalias(adev, modalias, len))
-		strlcpy(modalias, default_id, len);
+		strscpy(modalias, default_id, len);
 }
 EXPORT_SYMBOL_GPL(acpi_set_modalias);
 
@@ -723,7 +876,7 @@ static bool __acpi_match_device_cls(const struct acpi_device_id *id,
 	return true;
 }
 
-static bool __acpi_match_device(struct acpi_device *device,
+static bool __acpi_match_device(const struct acpi_device *device,
 				const struct acpi_device_id *acpi_ids,
 				const struct of_device_id *of_ids,
 				const struct acpi_device_id **acpi_id,
@@ -766,6 +919,26 @@ out_acpi_match:
 }
 
 /**
+ * acpi_match_acpi_device - Match an ACPI device against a given list of ACPI IDs
+ * @ids: Array of struct acpi_device_id objects to match against.
+ * @adev: The ACPI device pointer to match.
+ *
+ * Match the ACPI device @adev against a given list of ACPI IDs @ids.
+ *
+ * Return:
+ * a pointer to the first matching ACPI ID on success or %NULL on failure.
+ */
+const struct acpi_device_id *acpi_match_acpi_device(const struct acpi_device_id *ids,
+						    const struct acpi_device *adev)
+{
+	const struct acpi_device_id *id = NULL;
+
+	__acpi_match_device(adev, ids, NULL, &id, NULL);
+	return id;
+}
+EXPORT_SYMBOL_GPL(acpi_match_acpi_device);
+
+/**
  * acpi_match_device - Match a struct device against a given list of ACPI IDs
  * @ids: Array of struct acpi_device_id object to match against.
  * @dev: The device structure to match.
@@ -779,10 +952,7 @@ out_acpi_match:
 const struct acpi_device_id *acpi_match_device(const struct acpi_device_id *ids,
 					       const struct device *dev)
 {
-	const struct acpi_device_id *id = NULL;
-
-	__acpi_match_device(acpi_companion_match(dev), ids, NULL, &id, NULL);
-	return id;
+	return acpi_match_acpi_device(ids, acpi_companion_match(dev));
 }
 EXPORT_SYMBOL_GPL(acpi_match_device);
 
@@ -799,12 +969,13 @@ static const void *acpi_of_device_get_match_data(const struct device *dev)
 
 const void *acpi_device_get_match_data(const struct device *dev)
 {
+	const struct acpi_device_id *acpi_ids = dev->driver->acpi_match_table;
 	const struct acpi_device_id *match;
 
-	if (!dev->driver->acpi_match_table)
+	if (!acpi_ids)
 		return acpi_of_device_get_match_data(dev);
 
-	match = acpi_match_device(dev->driver->acpi_match_table, dev);
+	match = acpi_match_device(acpi_ids, dev);
 	if (!match)
 		return NULL;
 
@@ -822,14 +993,13 @@ EXPORT_SYMBOL(acpi_match_device_ids);
 bool acpi_driver_match_device(struct device *dev,
 			      const struct device_driver *drv)
 {
-	if (!drv->acpi_match_table)
-		return acpi_of_match_device(ACPI_COMPANION(dev),
-					    drv->of_match_table,
-					    NULL);
-
-	return __acpi_match_device(acpi_companion_match(dev),
-				   drv->acpi_match_table, drv->of_match_table,
-				   NULL, NULL);
+	const struct acpi_device_id *acpi_ids = drv->acpi_match_table;
+	const struct of_device_id *of_ids = drv->of_match_table;
+
+	if (!acpi_ids)
+		return acpi_of_match_device(ACPI_COMPANION(dev), of_ids, NULL);
+
+	return __acpi_match_device(acpi_companion_match(dev), acpi_ids, of_ids, NULL, NULL);
 }
 EXPORT_SYMBOL_GPL(acpi_driver_match_device);
 
@@ -838,28 +1008,26 @@ EXPORT_SYMBOL_GPL(acpi_driver_match_device);
    -------------------------------------------------------------------------- */
 
 /**
- * acpi_bus_register_driver - register a driver with the ACPI bus
+ * __acpi_bus_register_driver - register a driver with the ACPI bus
  * @driver: driver being registered
+ * @owner: owning module/driver
  *
  * Registers a driver with the ACPI bus.  Searches the namespace for all
  * devices that match the driver's criteria and binds.  Returns zero for
  * success or a negative error status for failure.
  */
-int acpi_bus_register_driver(struct acpi_driver *driver)
+int __acpi_bus_register_driver(struct acpi_driver *driver, struct module *owner)
 {
-	int ret;
-
 	if (acpi_disabled)
 		return -ENODEV;
 	driver->drv.name = driver->name;
 	driver->drv.bus = &acpi_bus_type;
-	driver->drv.owner = driver->owner;
+	driver->drv.owner = owner;
 
-	ret = driver_register(&driver->drv);
-	return ret;
+	return driver_register(&driver->drv);
 }
 
-EXPORT_SYMBOL(acpi_bus_register_driver);
+EXPORT_SYMBOL(__acpi_bus_register_driver);
 
 /**
  * acpi_bus_unregister_driver - unregisters a driver with the ACPI bus
@@ -879,16 +1047,16 @@ EXPORT_SYMBOL(acpi_bus_unregister_driver);
                               ACPI Bus operations
    -------------------------------------------------------------------------- */
 
-static int acpi_bus_match(struct device *dev, struct device_driver *drv)
+static int acpi_bus_match(struct device *dev, const struct device_driver *drv)
 {
 	struct acpi_device *acpi_dev = to_acpi_device(dev);
-	struct acpi_driver *acpi_drv = to_acpi_driver(drv);
+	const struct acpi_driver *acpi_drv = to_acpi_driver(drv);
 
 	return acpi_dev->flags.match_driver
 		&& !acpi_match_device_ids(acpi_dev, acpi_drv->ids);
 }
 
-static int acpi_device_uevent(struct device *dev, struct kobj_uevent_env *env)
+static int acpi_device_uevent(const struct device *dev, struct kobj_uevent_env *env)
 {
 	return __acpi_device_uevent_modalias(to_acpi_device(dev), env);
 }
@@ -906,51 +1074,49 @@ static int acpi_device_probe(struct device *dev)
 		return -ENOSYS;
 
 	ret = acpi_drv->ops.add(acpi_dev);
-	if (ret)
+	if (ret) {
+		acpi_dev->driver_data = NULL;
 		return ret;
+	}
 
-	acpi_dev->driver = acpi_drv;
-	ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-			  "Driver [%s] successfully bound to device [%s]\n",
-			  acpi_drv->name, acpi_dev->pnp.bus_id));
+	pr_debug("Driver [%s] successfully bound to device [%s]\n",
+		 acpi_drv->name, acpi_dev->pnp.bus_id);
 
 	if (acpi_drv->ops.notify) {
-		ret = acpi_device_install_notify_handler(acpi_dev);
+		ret = acpi_device_install_notify_handler(acpi_dev, acpi_drv);
 		if (ret) {
 			if (acpi_drv->ops.remove)
 				acpi_drv->ops.remove(acpi_dev);
 
-			acpi_dev->driver = NULL;
 			acpi_dev->driver_data = NULL;
 			return ret;
 		}
 	}
 
-	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found driver [%s] for device [%s]\n",
-			  acpi_drv->name, acpi_dev->pnp.bus_id));
+	pr_debug("Found driver [%s] for device [%s]\n", acpi_drv->name,
+		 acpi_dev->pnp.bus_id);
+
 	get_device(dev);
 	return 0;
 }
 
-static int acpi_device_remove(struct device *dev)
+static void acpi_device_remove(struct device *dev)
 {
 	struct acpi_device *acpi_dev = to_acpi_device(dev);
-	struct acpi_driver *acpi_drv = acpi_dev->driver;
+	struct acpi_driver *acpi_drv = to_acpi_driver(dev->driver);
+
+	if (acpi_drv->ops.notify)
+		acpi_device_remove_notify_handler(acpi_dev, acpi_drv);
+
+	if (acpi_drv->ops.remove)
+		acpi_drv->ops.remove(acpi_dev);
 
-	if (acpi_drv) {
-		if (acpi_drv->ops.notify)
-			acpi_device_remove_notify_handler(acpi_dev);
-		if (acpi_drv->ops.remove)
-			acpi_drv->ops.remove(acpi_dev);
-	}
-	acpi_dev->driver = NULL;
 	acpi_dev->driver_data = NULL;
 
 	put_device(dev);
-	return 0;
 }
 
-struct bus_type acpi_bus_type = {
+const struct bus_type acpi_bus_type = {
 	.name		= "acpi",
 	.match		= acpi_bus_match,
 	.probe		= acpi_device_probe,
@@ -958,6 +1124,51 @@ struct bus_type acpi_bus_type = {
 	.uevent		= acpi_device_uevent,
 };
 
+int acpi_bus_for_each_dev(int (*fn)(struct device *, void *), void *data)
+{
+	return bus_for_each_dev(&acpi_bus_type, NULL, data, fn);
+}
+EXPORT_SYMBOL_GPL(acpi_bus_for_each_dev);
+
+struct acpi_dev_walk_context {
+	int (*fn)(struct acpi_device *, void *);
+	void *data;
+};
+
+static int acpi_dev_for_one_check(struct device *dev, void *context)
+{
+	struct acpi_dev_walk_context *adwc = context;
+
+	if (dev->bus != &acpi_bus_type)
+		return 0;
+
+	return adwc->fn(to_acpi_device(dev), adwc->data);
+}
+EXPORT_SYMBOL_GPL(acpi_dev_for_each_child);
+
+int acpi_dev_for_each_child(struct acpi_device *adev,
+			    int (*fn)(struct acpi_device *, void *), void *data)
+{
+	struct acpi_dev_walk_context adwc = {
+		.fn = fn,
+		.data = data,
+	};
+
+	return device_for_each_child(&adev->dev, &adwc, acpi_dev_for_one_check);
+}
+
+int acpi_dev_for_each_child_reverse(struct acpi_device *adev,
+				    int (*fn)(struct acpi_device *, void *),
+				    void *data)
+{
+	struct acpi_dev_walk_context adwc = {
+		.fn = fn,
+		.data = data,
+	};
+
+	return device_for_each_child_reverse(&adev->dev, &adwc, acpi_dev_for_one_check);
+}
+
 /* --------------------------------------------------------------------------
                              Initialization/Cleanup
    -------------------------------------------------------------------------- */
@@ -989,16 +1200,22 @@ static int __init acpi_bus_init_irq(void)
 	case ACPI_IRQ_MODEL_PLATFORM:
 		message = "platform specific model";
 		break;
+	case ACPI_IRQ_MODEL_LPIC:
+		message = "LPIC";
+		break;
+	case ACPI_IRQ_MODEL_RINTC:
+		message = "RINTC";
+		break;
 	default:
-		printk(KERN_WARNING PREFIX "Unknown interrupt routing model\n");
+		pr_info("Unknown interrupt routing model\n");
 		return -ENODEV;
 	}
 
-	printk(KERN_INFO PREFIX "Using %s for interrupt routing\n", message);
+	pr_info("Using %s for interrupt routing\n", message);
 
 	status = acpi_execute_simple_method(NULL, "\\_PIC", acpi_irq_model);
 	if (ACPI_FAILURE(status) && (status != AE_NOT_FOUND)) {
-		ACPI_EXCEPTION((AE_INFO, status, "Evaluating _PIC"));
+		pr_info("_PIC evaluation failed: %s\n", acpi_format_exception(status));
 		return -ENODEV;
 	}
 
@@ -1022,7 +1239,7 @@ void __init acpi_early_init(void)
 	if (acpi_disabled)
 		return;
 
-	printk(KERN_INFO PREFIX "Core revision %08x\n", ACPI_CA_VERSION);
+	pr_info("Core revision %08x\n", ACPI_CA_VERSION);
 
 	/* enable workarounds, unless strict ACPI spec. compliance */
 	if (!acpi_strict)
@@ -1043,15 +1260,13 @@ void __init acpi_early_init(void)
 
 	status = acpi_reallocate_root_table();
 	if (ACPI_FAILURE(status)) {
-		printk(KERN_ERR PREFIX
-		       "Unable to reallocate ACPI tables\n");
+		pr_err("Unable to reallocate ACPI tables\n");
 		goto error0;
 	}
 
 	status = acpi_initialize_subsystem();
 	if (ACPI_FAILURE(status)) {
-		printk(KERN_ERR PREFIX
-		       "Unable to initialize the ACPI Interpreter\n");
+		pr_err("Unable to initialize the ACPI Interpreter\n");
 		goto error0;
 	}
 
@@ -1097,7 +1312,7 @@ void __init acpi_subsystem_init(void)
 
 	status = acpi_enable_subsystem(~ACPI_NO_ACPI_ENABLE);
 	if (ACPI_FAILURE(status)) {
-		printk(KERN_ERR PREFIX "Unable to enable ACPI\n");
+		pr_err("Unable to enable ACPI\n");
 		disable_acpi();
 	} else {
 		/*
@@ -1112,7 +1327,8 @@ void __init acpi_subsystem_init(void)
 
 static acpi_status acpi_bus_table_handler(u32 event, void *table, void *context)
 {
-	acpi_scan_table_handler(event, table, context);
+	if (event == ACPI_TABLE_EVENT_LOAD)
+		acpi_scan_table_notify();
 
 	return acpi_sysfs_table_handler(event, table, context);
 }
@@ -1126,8 +1342,7 @@ static int __init acpi_bus_init(void)
 
 	status = acpi_load_tables();
 	if (ACPI_FAILURE(status)) {
-		printk(KERN_ERR PREFIX
-		       "Unable to load the System Description Tables\n");
+		pr_err("Unable to load the System Description Tables\n");
 		goto error1;
 	}
 
@@ -1145,25 +1360,22 @@ static int __init acpi_bus_init(void)
 
 	status = acpi_enable_subsystem(ACPI_NO_ACPI_ENABLE);
 	if (ACPI_FAILURE(status)) {
-		printk(KERN_ERR PREFIX
-		       "Unable to start the ACPI Interpreter\n");
+		pr_err("Unable to start the ACPI Interpreter\n");
 		goto error1;
 	}
 
 	status = acpi_initialize_objects(ACPI_FULL_INITIALIZATION);
 	if (ACPI_FAILURE(status)) {
-		printk(KERN_ERR PREFIX "Unable to initialize ACPI objects\n");
+		pr_err("Unable to initialize ACPI objects\n");
 		goto error1;
 	}
 
-	/* Set capability bits for _OSC under processor scope */
-	acpi_early_processor_osc();
-
 	/*
 	 * _OSC method may exist in module level code,
 	 * so it must be run after ACPI_FULL_INITIALIZATION
 	 */
-	acpi_bus_osc_support();
+	acpi_bus_osc_negotiate_platform_control();
+	acpi_bus_osc_negotiate_usb_control();
 
 	/*
 	 * _PDC control method may load dynamic SSDT tables,
@@ -1173,7 +1385,7 @@ static int __init acpi_bus_init(void)
 
 	acpi_sysfs_init();
 
-	acpi_early_processor_set_pdc();
+	acpi_early_processor_control_setup();
 
 	/*
 	 * Maybe EC region is required at bus_scan/acpi_get_devices. So it
@@ -1181,7 +1393,7 @@ static int __init acpi_bus_init(void)
 	 */
 	acpi_ec_dsdt_probe();
 
-	printk(KERN_INFO PREFIX "Interpreter enabled\n");
+	pr_info("Interpreter enabled\n");
 
 	/* Initialize sleep structures */
 	acpi_sleep_init();
@@ -1194,14 +1406,13 @@ static int __init acpi_bus_init(void)
 		goto error1;
 
 	/*
-	 * Register the for all standard device notifications.
+	 * Register for all standard device notifications.
 	 */
 	status =
 	    acpi_install_notify_handler(ACPI_ROOT_OBJECT, ACPI_SYSTEM_NOTIFY,
 					&acpi_bus_notify, NULL);
 	if (ACPI_FAILURE(status)) {
-		printk(KERN_ERR PREFIX
-		       "Unable to register for device notifications\n");
+		pr_err("Unable to register for system notifications\n");
 		goto error1;
 	}
 
@@ -1223,29 +1434,38 @@ static int __init acpi_bus_init(void)
 struct kobject *acpi_kobj;
 EXPORT_SYMBOL_GPL(acpi_kobj);
 
+void __weak __init acpi_arch_init(void) { }
+
 static int __init acpi_init(void)
 {
 	int result;
 
 	if (acpi_disabled) {
-		printk(KERN_INFO PREFIX "Interpreter disabled.\n");
+		pr_info("Interpreter disabled.\n");
 		return -ENODEV;
 	}
 
 	acpi_kobj = kobject_create_and_add("acpi", firmware_kobj);
 	if (!acpi_kobj) {
-		printk(KERN_WARNING "%s: kset create error\n", __func__);
-		acpi_kobj = NULL;
+		pr_err("Failed to register kobject\n");
+		return -ENOMEM;
 	}
 
+	init_prmt();
+	acpi_init_pcc();
 	result = acpi_bus_init();
 	if (result) {
+		kobject_put(acpi_kobj);
 		disable_acpi();
 		return result;
 	}
+	acpi_init_ffh();
 
 	pci_mmcfg_late_init();
-	acpi_iort_init();
+	acpi_viot_early_init();
+	acpi_hest_init();
+	acpi_ghes_init();
+	acpi_arch_init();
 	acpi_scan_init();
 	acpi_ec_init();
 	acpi_debugfs_init();
@@ -1253,6 +1473,7 @@ static int __init acpi_init(void)
 	acpi_wakeup_device_init();
 	acpi_debugger_init();
 	acpi_setup_sb_notify_handler();
+	acpi_viot_init();
 	return 0;
 }
 
diff --git a/drivers/acpi/button.c b/drivers/acpi/button.c
index 78cfc70cb320..3c6dd9b4ba0a 100644
--- a/drivers/acpi/button.c
+++ b/drivers/acpi/button.c
@@ -21,12 +21,10 @@
 #include <linux/dmi.h>
 #include <acpi/button.h>
 
-#define PREFIX "ACPI: "
-
 #define ACPI_BUTTON_CLASS		"button"
-#define ACPI_BUTTON_FILE_INFO		"info"
 #define ACPI_BUTTON_FILE_STATE		"state"
 #define ACPI_BUTTON_TYPE_UNKNOWN	0x00
+#define ACPI_BUTTON_NOTIFY_WAKE		0x02
 #define ACPI_BUTTON_NOTIFY_STATUS	0x80
 
 #define ACPI_BUTTON_SUBCLASS_POWER	"power"
@@ -55,9 +53,6 @@ static const char * const lid_init_state_str[] = {
 	[ACPI_BUTTON_LID_INIT_DISABLED]		= "disabled",
 };
 
-#define _COMPONENT		ACPI_BUTTON_COMPONENT
-ACPI_MODULE_NAME("button");
-
 MODULE_AUTHOR("Paul Diefenbaugh");
 MODULE_DESCRIPTION("ACPI Button Driver");
 MODULE_LICENSE("GPL");
@@ -75,35 +70,53 @@ MODULE_DEVICE_TABLE(acpi, button_device_ids);
 /* Please keep this list sorted alphabetically by vendor and model */
 static const struct dmi_system_id dmi_lid_quirks[] = {
 	{
-		/*
-		 * Acer Switch 10 SW5-012. _LID method messes with home and
-		 * power button GPIO IRQ settings causing an interrupt storm on
-		 * both GPIOs. This is unfixable without a DSDT override, so we
-		 * have to disable the lid-switch functionality altogether :|
-		 */
+		/* GP-electronic T701, _LID method points to a floating GPIO */
 		.matches = {
-			DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
-			DMI_MATCH(DMI_PRODUCT_NAME, "Aspire SW5-012"),
+			DMI_MATCH(DMI_SYS_VENDOR, "Insyde"),
+			DMI_MATCH(DMI_PRODUCT_NAME, "T701"),
+			DMI_MATCH(DMI_BIOS_VERSION, "BYT70A.YNCHENG.WIN.007"),
 		},
 		.driver_data = (void *)(long)ACPI_BUTTON_LID_INIT_DISABLED,
 	},
 	{
-		/* GP-electronic T701, _LID method points to a floating GPIO */
+		/* Nextbook Ares 8A tablet, _LID device always reports lid closed */
 		.matches = {
 			DMI_MATCH(DMI_SYS_VENDOR, "Insyde"),
-			DMI_MATCH(DMI_PRODUCT_NAME, "T701"),
-			DMI_MATCH(DMI_BIOS_VERSION, "BYT70A.YNCHENG.WIN.007"),
+			DMI_MATCH(DMI_PRODUCT_NAME, "CherryTrail"),
+			DMI_MATCH(DMI_BIOS_VERSION, "M882"),
 		},
 		.driver_data = (void *)(long)ACPI_BUTTON_LID_INIT_DISABLED,
 	},
 	{
 		/*
+		 * Lenovo Yoga 9 14ITL5, initial notification of the LID device
+		 * never happens.
+		 */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
+			DMI_MATCH(DMI_PRODUCT_NAME, "82BG"),
+		},
+		.driver_data = (void *)(long)ACPI_BUTTON_LID_INIT_OPEN,
+	},
+	{
+		/*
 		 * Medion Akoya E2215T, notification of the LID device only
 		 * happens on close, not on open and _LID always returns closed.
 		 */
 		.matches = {
 			DMI_MATCH(DMI_SYS_VENDOR, "MEDION"),
-			DMI_MATCH(DMI_PRODUCT_NAME, "E2215T MD60198"),
+			DMI_MATCH(DMI_PRODUCT_NAME, "E2215T"),
+		},
+		.driver_data = (void *)(long)ACPI_BUTTON_LID_INIT_OPEN,
+	},
+	{
+		/*
+		 * Medion Akoya E2228T, notification of the LID device only
+		 * happens on close, not on open and _LID always returns closed.
+		 */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "MEDION"),
+			DMI_MATCH(DMI_PRODUCT_NAME, "E2228T"),
 		},
 		.driver_data = (void *)(long)ACPI_BUTTON_LID_INIT_OPEN,
 	},
@@ -118,12 +131,22 @@ static const struct dmi_system_id dmi_lid_quirks[] = {
 		},
 		.driver_data = (void *)(long)ACPI_BUTTON_LID_INIT_OPEN,
 	},
+	{
+		/*
+		 * Samsung galaxybook2 ,initial _LID device notification returns
+		 * lid closed.
+		 */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "SAMSUNG ELECTRONICS CO., LTD."),
+			DMI_MATCH(DMI_PRODUCT_NAME, "750XED"),
+		},
+		.driver_data = (void *)(long)ACPI_BUTTON_LID_INIT_OPEN,
+	},
 	{}
 };
 
 static int acpi_button_add(struct acpi_device *device);
-static int acpi_button_remove(struct acpi_device *device);
-static void acpi_button_notify(struct acpi_device *device, u32 event);
+static void acpi_button_remove(struct acpi_device *device);
 
 #ifdef CONFIG_PM_SLEEP
 static int acpi_button_suspend(struct device *dev);
@@ -141,7 +164,6 @@ static struct acpi_driver acpi_button_driver = {
 	.ops = {
 		.add = acpi_button_add,
 		.remove = acpi_button_remove,
-		.notify = acpi_button_notify,
 	},
 	.drv.pm = &acpi_button_pm,
 };
@@ -154,6 +176,7 @@ struct acpi_button {
 	int last_state;
 	ktime_t last_time;
 	bool suspended;
+	bool lid_state_initialized;
 };
 
 static struct acpi_device *lid_device;
@@ -163,10 +186,7 @@ static unsigned long lid_report_interval __read_mostly = 500;
 module_param(lid_report_interval, ulong, 0644);
 MODULE_PARM_DESC(lid_report_interval, "Interval (ms) between lid key events");
 
-/* --------------------------------------------------------------------------
-                              FS Interface (/proc)
-   -------------------------------------------------------------------------- */
-
+/* FS Interface (/proc) */
 static struct proc_dir_entry *acpi_button_dir;
 static struct proc_dir_entry *acpi_lid_dir;
 
@@ -287,7 +307,7 @@ static int acpi_button_add_fs(struct acpi_device *device)
 		return 0;
 
 	if (acpi_button_dir || acpi_lid_dir) {
-		printk(KERN_ERR PREFIX "More than one Lid device found!\n");
+		pr_info("More than one Lid device found!\n");
 		return -EEXIST;
 	}
 
@@ -355,9 +375,7 @@ static int acpi_button_remove_fs(struct acpi_device *device)
 	return 0;
 }
 
-/* --------------------------------------------------------------------------
-                                Driver Interface
-   -------------------------------------------------------------------------- */
+/* Driver Interface */
 int acpi_lid_open(void)
 {
 	if (!lid_device)
@@ -384,6 +402,8 @@ static int acpi_lid_update_state(struct acpi_device *device,
 
 static void acpi_lid_initialize_state(struct acpi_device *device)
 {
+	struct acpi_button *button = acpi_driver_data(device);
+
 	switch (lid_init_state) {
 	case ACPI_BUTTON_LID_INIT_OPEN:
 		(void)acpi_lid_notify_state(device, 1);
@@ -395,51 +415,74 @@ static void acpi_lid_initialize_state(struct acpi_device *device)
 	default:
 		break;
 	}
+
+	button->lid_state_initialized = true;
 }
 
-static void acpi_button_notify(struct acpi_device *device, u32 event)
+static void acpi_lid_notify(acpi_handle handle, u32 event, void *data)
 {
-	struct acpi_button *button = acpi_driver_data(device);
+	struct acpi_device *device = data;
+	struct acpi_button *button;
+
+	if (event != ACPI_BUTTON_NOTIFY_STATUS) {
+		acpi_handle_debug(device->handle, "Unsupported event [0x%x]\n",
+				  event);
+		return;
+	}
+
+	button = acpi_driver_data(device);
+	if (!button->lid_state_initialized)
+		return;
+
+	acpi_lid_update_state(device, true);
+}
+
+static void acpi_button_notify(acpi_handle handle, u32 event, void *data)
+{
+	struct acpi_device *device = data;
+	struct acpi_button *button;
 	struct input_dev *input;
-	int users;
+	int keycode;
 
 	switch (event) {
-	case ACPI_FIXED_HARDWARE_EVENT:
-		event = ACPI_BUTTON_NOTIFY_STATUS;
-		/* fall through */
 	case ACPI_BUTTON_NOTIFY_STATUS:
-		input = button->input;
-		if (button->type == ACPI_BUTTON_TYPE_LID) {
-			mutex_lock(&button->input->mutex);
-			users = button->input->users;
-			mutex_unlock(&button->input->mutex);
-			if (users)
-				acpi_lid_update_state(device, true);
-		} else {
-			int keycode;
-
-			acpi_pm_wakeup_event(&device->dev);
-			if (button->suspended)
-				break;
-
-			keycode = test_bit(KEY_SLEEP, input->keybit) ?
-						KEY_SLEEP : KEY_POWER;
-			input_report_key(input, keycode, 1);
-			input_sync(input);
-			input_report_key(input, keycode, 0);
-			input_sync(input);
-
-			acpi_bus_generate_netlink_event(
-					device->pnp.device_class,
-					dev_name(&device->dev),
-					event, ++button->pushed);
-		}
 		break;
-	default:
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-				  "Unsupported event [0x%x]\n", event));
+	case ACPI_BUTTON_NOTIFY_WAKE:
 		break;
+	default:
+		acpi_handle_debug(device->handle, "Unsupported event [0x%x]\n",
+				  event);
+		return;
 	}
+
+	acpi_pm_wakeup_event(&device->dev);
+
+	button = acpi_driver_data(device);
+	if (button->suspended || event == ACPI_BUTTON_NOTIFY_WAKE)
+		return;
+
+	input = button->input;
+	keycode = test_bit(KEY_SLEEP, input->keybit) ? KEY_SLEEP : KEY_POWER;
+
+	input_report_key(input, keycode, 1);
+	input_sync(input);
+	input_report_key(input, keycode, 0);
+	input_sync(input);
+
+	acpi_bus_generate_netlink_event(device->pnp.device_class,
+					dev_name(&device->dev),
+					event, ++button->pushed);
+}
+
+static void acpi_button_notify_run(void *data)
+{
+	acpi_button_notify(NULL, ACPI_BUTTON_NOTIFY_STATUS, data);
+}
+
+static u32 acpi_button_event(void *data)
+{
+	acpi_os_execute(OSL_NOTIFY_HANDLER, acpi_button_notify_run, data);
+	return ACPI_INTERRUPT_HANDLED;
 }
 
 #ifdef CONFIG_PM_SLEEP
@@ -454,15 +497,24 @@ static int acpi_button_suspend(struct device *dev)
 
 static int acpi_button_resume(struct device *dev)
 {
+	struct input_dev *input;
 	struct acpi_device *device = to_acpi_device(dev);
 	struct acpi_button *button = acpi_driver_data(device);
 
 	button->suspended = false;
-	if (button->type == ACPI_BUTTON_TYPE_LID && button->input->users) {
+	if (button->type == ACPI_BUTTON_TYPE_LID) {
 		button->last_state = !!acpi_lid_evaluate_state(device);
 		button->last_time = ktime_get();
 		acpi_lid_initialize_state(device);
 	}
+
+	if (button->type == ACPI_BUTTON_TYPE_POWER) {
+		input = button->input;
+		input_report_key(input, KEY_WAKEUP, 1);
+		input_sync(input);
+		input_report_key(input, KEY_WAKEUP, 0);
+		input_sync(input);
+	}
 	return 0;
 }
 #endif
@@ -481,11 +533,13 @@ static int acpi_lid_input_open(struct input_dev *input)
 
 static int acpi_button_add(struct acpi_device *device)
 {
+	acpi_notify_handler handler;
 	struct acpi_button *button;
 	struct input_dev *input;
 	const char *hid = acpi_device_hid(device);
+	acpi_status status;
 	char *name, *class;
-	int error;
+	int error = 0;
 
 	if (!strcmp(hid, ACPI_BUTTON_HID_LID) &&
 	     lid_init_state == ACPI_BUTTON_LID_INIT_DISABLED)
@@ -509,30 +563,36 @@ static int acpi_button_add(struct acpi_device *device)
 	if (!strcmp(hid, ACPI_BUTTON_HID_POWER) ||
 	    !strcmp(hid, ACPI_BUTTON_HID_POWERF)) {
 		button->type = ACPI_BUTTON_TYPE_POWER;
-		strcpy(name, ACPI_BUTTON_DEVICE_NAME_POWER);
+		handler = acpi_button_notify;
+		strscpy(name, ACPI_BUTTON_DEVICE_NAME_POWER, MAX_ACPI_DEVICE_NAME_LEN);
 		sprintf(class, "%s/%s",
 			ACPI_BUTTON_CLASS, ACPI_BUTTON_SUBCLASS_POWER);
 	} else if (!strcmp(hid, ACPI_BUTTON_HID_SLEEP) ||
 		   !strcmp(hid, ACPI_BUTTON_HID_SLEEPF)) {
 		button->type = ACPI_BUTTON_TYPE_SLEEP;
-		strcpy(name, ACPI_BUTTON_DEVICE_NAME_SLEEP);
+		handler = acpi_button_notify;
+		strscpy(name, ACPI_BUTTON_DEVICE_NAME_SLEEP, MAX_ACPI_DEVICE_NAME_LEN);
 		sprintf(class, "%s/%s",
 			ACPI_BUTTON_CLASS, ACPI_BUTTON_SUBCLASS_SLEEP);
 	} else if (!strcmp(hid, ACPI_BUTTON_HID_LID)) {
 		button->type = ACPI_BUTTON_TYPE_LID;
-		strcpy(name, ACPI_BUTTON_DEVICE_NAME_LID);
+		handler = acpi_lid_notify;
+		strscpy(name, ACPI_BUTTON_DEVICE_NAME_LID, MAX_ACPI_DEVICE_NAME_LEN);
 		sprintf(class, "%s/%s",
 			ACPI_BUTTON_CLASS, ACPI_BUTTON_SUBCLASS_LID);
 		input->open = acpi_lid_input_open;
 	} else {
-		printk(KERN_ERR PREFIX "Unsupported hid [%s]\n", hid);
+		pr_info("Unsupported hid [%s]\n", hid);
 		error = -ENODEV;
-		goto err_free_input;
 	}
 
-	error = acpi_button_add_fs(device);
-	if (error)
-		goto err_free_input;
+	if (!error)
+		error = acpi_button_add_fs(device);
+
+	if (error) {
+		input_free_device(input);
+		goto err_free_button;
+	}
 
 	snprintf(button->phys, sizeof(button->phys), "%s/button/input0", hid);
 
@@ -545,6 +605,7 @@ static int acpi_button_add(struct acpi_device *device)
 	switch (button->type) {
 	case ACPI_BUTTON_TYPE_POWER:
 		input_set_capability(input, EV_KEY, KEY_POWER);
+		input_set_capability(input, EV_KEY, KEY_WAKEUP);
 		break;
 
 	case ACPI_BUTTON_TYPE_SLEEP:
@@ -558,8 +619,33 @@ static int acpi_button_add(struct acpi_device *device)
 
 	input_set_drvdata(input, device);
 	error = input_register_device(input);
-	if (error)
+	if (error) {
+		input_free_device(input);
 		goto err_remove_fs;
+	}
+
+	switch (device->device_type) {
+	case ACPI_BUS_TYPE_POWER_BUTTON:
+		status = acpi_install_fixed_event_handler(ACPI_EVENT_POWER_BUTTON,
+							  acpi_button_event,
+							  device);
+		break;
+	case ACPI_BUS_TYPE_SLEEP_BUTTON:
+		status = acpi_install_fixed_event_handler(ACPI_EVENT_SLEEP_BUTTON,
+							  acpi_button_event,
+							  device);
+		break;
+	default:
+		status = acpi_install_notify_handler(device->handle,
+						     ACPI_ALL_NOTIFY, handler,
+						     device);
+		break;
+	}
+	if (ACPI_FAILURE(status)) {
+		error = -ENODEV;
+		goto err_input_unregister;
+	}
+
 	if (button->type == ACPI_BUTTON_TYPE_LID) {
 		/*
 		 * This assumes there's only one lid device, or if there are
@@ -569,26 +655,43 @@ static int acpi_button_add(struct acpi_device *device)
 	}
 
 	device_init_wakeup(&device->dev, true);
-	printk(KERN_INFO PREFIX "%s [%s]\n", name, acpi_device_bid(device));
+	pr_info("%s [%s]\n", name, acpi_device_bid(device));
 	return 0;
 
- err_remove_fs:
+err_input_unregister:
+	input_unregister_device(input);
+err_remove_fs:
 	acpi_button_remove_fs(device);
- err_free_input:
-	input_free_device(input);
- err_free_button:
+err_free_button:
 	kfree(button);
 	return error;
 }
 
-static int acpi_button_remove(struct acpi_device *device)
+static void acpi_button_remove(struct acpi_device *device)
 {
 	struct acpi_button *button = acpi_driver_data(device);
 
+	switch (device->device_type) {
+	case ACPI_BUS_TYPE_POWER_BUTTON:
+		acpi_remove_fixed_event_handler(ACPI_EVENT_POWER_BUTTON,
+						acpi_button_event);
+		break;
+	case ACPI_BUS_TYPE_SLEEP_BUTTON:
+		acpi_remove_fixed_event_handler(ACPI_EVENT_SLEEP_BUTTON,
+						acpi_button_event);
+		break;
+	default:
+		acpi_remove_notify_handler(device->handle, ACPI_DEVICE_NOTIFY,
+					   button->type == ACPI_BUTTON_TYPE_LID ?
+						acpi_lid_notify :
+						acpi_button_notify);
+		break;
+	}
+	acpi_os_wait_events_complete();
+
 	acpi_button_remove_fs(device);
 	input_unregister_device(button->input);
 	kfree(button);
-	return 0;
 }
 
 static int param_set_lid_init_state(const char *val,
diff --git a/drivers/acpi/cm_sbs.c b/drivers/acpi/cm_sbs.c
deleted file mode 100644
index 0ca9f82de8ba..000000000000
--- a/drivers/acpi/cm_sbs.c
+++ /dev/null
@@ -1,87 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/acpi.h>
-#include <linux/types.h>
-#include <linux/proc_fs.h>
-#include <linux/seq_file.h>
-#include <acpi/acpi_bus.h>
-#include <acpi/acpi_drivers.h>
-
-#define PREFIX "ACPI: "
-
-ACPI_MODULE_NAME("cm_sbs");
-#define ACPI_AC_CLASS		"ac_adapter"
-#define ACPI_BATTERY_CLASS	"battery"
-#define _COMPONENT		ACPI_SBS_COMPONENT
-static struct proc_dir_entry *acpi_ac_dir;
-static struct proc_dir_entry *acpi_battery_dir;
-
-static DEFINE_MUTEX(cm_sbs_mutex);
-
-static int lock_ac_dir_cnt;
-static int lock_battery_dir_cnt;
-
-struct proc_dir_entry *acpi_lock_ac_dir(void)
-{
-	mutex_lock(&cm_sbs_mutex);
-	if (!acpi_ac_dir)
-		acpi_ac_dir = proc_mkdir(ACPI_AC_CLASS, acpi_root_dir);
-	if (acpi_ac_dir) {
-		lock_ac_dir_cnt++;
-	} else {
-		printk(KERN_ERR PREFIX
-				  "Cannot create %s\n", ACPI_AC_CLASS);
-	}
-	mutex_unlock(&cm_sbs_mutex);
-	return acpi_ac_dir;
-}
-EXPORT_SYMBOL(acpi_lock_ac_dir);
-
-void acpi_unlock_ac_dir(struct proc_dir_entry *acpi_ac_dir_param)
-{
-	mutex_lock(&cm_sbs_mutex);
-	if (acpi_ac_dir_param)
-		lock_ac_dir_cnt--;
-	if (lock_ac_dir_cnt == 0 && acpi_ac_dir_param && acpi_ac_dir) {
-		remove_proc_entry(ACPI_AC_CLASS, acpi_root_dir);
-		acpi_ac_dir = NULL;
-	}
-	mutex_unlock(&cm_sbs_mutex);
-}
-EXPORT_SYMBOL(acpi_unlock_ac_dir);
-
-struct proc_dir_entry *acpi_lock_battery_dir(void)
-{
-	mutex_lock(&cm_sbs_mutex);
-	if (!acpi_battery_dir) {
-		acpi_battery_dir =
-		    proc_mkdir(ACPI_BATTERY_CLASS, acpi_root_dir);
-	}
-	if (acpi_battery_dir) {
-		lock_battery_dir_cnt++;
-	} else {
-		printk(KERN_ERR PREFIX
-				  "Cannot create %s\n", ACPI_BATTERY_CLASS);
-	}
-	mutex_unlock(&cm_sbs_mutex);
-	return acpi_battery_dir;
-}
-EXPORT_SYMBOL(acpi_lock_battery_dir);
-
-void acpi_unlock_battery_dir(struct proc_dir_entry *acpi_battery_dir_param)
-{
-	mutex_lock(&cm_sbs_mutex);
-	if (acpi_battery_dir_param)
-		lock_battery_dir_cnt--;
-	if (lock_battery_dir_cnt == 0 && acpi_battery_dir_param
-	    && acpi_battery_dir) {
-		remove_proc_entry(ACPI_BATTERY_CLASS, acpi_root_dir);
-		acpi_battery_dir = NULL;
-	}
-	mutex_unlock(&cm_sbs_mutex);
-	return;
-}
-EXPORT_SYMBOL(acpi_unlock_battery_dir);
diff --git a/drivers/acpi/container.c b/drivers/acpi/container.c
index 9ea5f55d97e3..5b7e3b9ae370 100644
--- a/drivers/acpi/container.c
+++ b/drivers/acpi/container.c
@@ -14,9 +14,6 @@
 
 #include "internal.h"
 
-#define _COMPONENT			ACPI_CONTAINER_COMPONENT
-ACPI_MODULE_NAME("container");
-
 static const struct acpi_device_id container_device_ids[] = {
 	{"ACPI0004", 0},
 	{"PNP0A05", 0},
@@ -26,17 +23,18 @@ static const struct acpi_device_id container_device_ids[] = {
 
 #ifdef CONFIG_ACPI_CONTAINER
 
-static int acpi_container_offline(struct container_dev *cdev)
+static int check_offline(struct acpi_device *adev, void *not_used)
 {
-	struct acpi_device *adev = ACPI_COMPANION(&cdev->dev);
-	struct acpi_device *child;
+	if (acpi_scan_is_offline(adev, false))
+		return 0;
 
-	/* Check all of the dependent devices' physical companions. */
-	list_for_each_entry(child, &adev->children, node)
-		if (!acpi_scan_is_offline(child, false))
-			return -EBUSY;
+	return -EBUSY;
+}
 
-	return 0;
+static int acpi_container_offline(struct container_dev *cdev)
+{
+	/* Check all of the dependent devices' physical companions. */
+	return acpi_dev_for_each_child(ACPI_COMPANION(&cdev->dev), check_offline, NULL);
 }
 
 static void acpi_container_release(struct device *dev)
diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
index 8b2e89c20c11..3bdeeee3414e 100644
--- a/drivers/acpi/cppc_acpi.c
+++ b/drivers/acpi/cppc_acpi.c
@@ -33,18 +33,20 @@
 
 #define pr_fmt(fmt)	"ACPI CPPC: " fmt
 
-#include <linux/cpufreq.h>
 #include <linux/delay.h>
 #include <linux/iopoll.h>
 #include <linux/ktime.h>
 #include <linux/rwsem.h>
 #include <linux/wait.h>
+#include <linux/topology.h>
+#include <linux/dmi.h>
+#include <linux/units.h>
+#include <linux/unaligned.h>
 
 #include <acpi/cppc_acpi.h>
 
 struct cppc_pcc_data {
-	struct mbox_chan *pcc_channel;
-	void __iomem *pcc_comm_addr;
+	struct pcc_mbox_chan *pcc_channel;
 	bool pcc_channel_acquired;
 	unsigned int deadline_us;
 	unsigned int pcc_mpar, pcc_mrtt, pcc_nominal;
@@ -92,7 +94,7 @@ static DEFINE_PER_CPU(int, cpu_pcc_subspace_idx);
 static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
 
 /* pcc mapped address + header size + offset within PCC subspace */
-#define GET_PCC_VADDR(offs, pcc_ss_id) (pcc_data[pcc_ss_id]->pcc_comm_addr + \
+#define GET_PCC_VADDR(offs, pcc_ss_id) (pcc_data[pcc_ss_id]->pcc_channel->shmem + \
 						0x8 + (offs))
 
 /* Check if a CPC register is in PCC */
@@ -100,17 +102,46 @@ static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
 				(cpc)->cpc_entry.reg.space_id ==	\
 				ACPI_ADR_SPACE_PLATFORM_COMM)
 
-/* Evalutes to True if reg is a NULL register descriptor */
+/* Check if a CPC register is in FFH */
+#define CPC_IN_FFH(cpc) ((cpc)->type == ACPI_TYPE_BUFFER &&		\
+				(cpc)->cpc_entry.reg.space_id ==	\
+				ACPI_ADR_SPACE_FIXED_HARDWARE)
+
+/* Check if a CPC register is in SystemMemory */
+#define CPC_IN_SYSTEM_MEMORY(cpc) ((cpc)->type == ACPI_TYPE_BUFFER &&	\
+				(cpc)->cpc_entry.reg.space_id ==	\
+				ACPI_ADR_SPACE_SYSTEM_MEMORY)
+
+/* Check if a CPC register is in SystemIo */
+#define CPC_IN_SYSTEM_IO(cpc) ((cpc)->type == ACPI_TYPE_BUFFER &&	\
+				(cpc)->cpc_entry.reg.space_id ==	\
+				ACPI_ADR_SPACE_SYSTEM_IO)
+
+/* Evaluates to True if reg is a NULL register descriptor */
 #define IS_NULL_REG(reg) ((reg)->space_id ==  ACPI_ADR_SPACE_SYSTEM_MEMORY && \
 				(reg)->address == 0 &&			\
 				(reg)->bit_width == 0 &&		\
 				(reg)->bit_offset == 0 &&		\
 				(reg)->access_width == 0)
 
-/* Evalutes to True if an optional cpc field is supported */
+/* Evaluates to True if an optional cpc field is supported */
 #define CPC_SUPPORTED(cpc) ((cpc)->type == ACPI_TYPE_INTEGER ?		\
 				!!(cpc)->cpc_entry.int_value :		\
 				!IS_NULL_REG(&(cpc)->cpc_entry.reg))
+
+/*
+ * Each bit indicates the optionality of the register in per-cpu
+ * cpc_regs[] with the corresponding index. 0 means mandatory and 1
+ * means optional.
+ */
+#define REG_OPTIONAL (0x1FC7D0)
+
+/*
+ * Use the index of the register in per-cpu cpc_regs[] to check if
+ * it's an optional one.
+ */
+#define IS_OPTIONAL_CPC_REG(reg_idx) (REG_OPTIONAL & (1U << (reg_idx)))
+
 /*
  * Arbitrary Retries in case the remote processor is slow to respond
  * to PCC commands. Keeping it high enough to cover emulators where
@@ -118,23 +149,17 @@ static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
  */
 #define NUM_RETRIES 500ULL
 
-struct cppc_attr {
-	struct attribute attr;
-	ssize_t (*show)(struct kobject *kobj,
-			struct attribute *attr, char *buf);
-	ssize_t (*store)(struct kobject *kobj,
-			struct attribute *attr, const char *c, ssize_t count);
-};
+#define OVER_16BTS_MASK ~0xFFFFULL
 
 #define define_one_cppc_ro(_name)		\
-static struct cppc_attr _name =			\
+static struct kobj_attribute _name =		\
 __ATTR(_name, 0444, show_##_name, NULL)
 
 #define to_cpc_desc(a) container_of(a, struct cpc_desc, kobj)
 
 #define show_cppc_data(access_fn, struct_name, member_name)		\
 	static ssize_t show_##member_name(struct kobject *kobj,		\
-					struct attribute *attr,	char *buf) \
+				struct kobj_attribute *attr, char *buf)	\
 	{								\
 		struct cpc_desc *cpc_ptr = to_cpc_desc(kobj);		\
 		struct struct_name st_name = {0};			\
@@ -144,7 +169,7 @@ __ATTR(_name, 0444, show_##_name, NULL)
 		if (ret)						\
 			return ret;					\
 									\
-		return scnprintf(buf, PAGE_SIZE, "%llu\n",		\
+		return sysfs_emit(buf, "%llu\n",		\
 				(u64)st_name.member_name);		\
 	}								\
 	define_one_cppc_ro(member_name)
@@ -153,14 +178,25 @@ show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, highest_perf);
 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_perf);
 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_perf);
 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_nonlinear_perf);
+show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, guaranteed_perf);
 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_freq);
 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_freq);
 
 show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, reference_perf);
 show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time);
 
+/* Check for valid access_width, otherwise, fallback to using bit_width */
+#define GET_BIT_WIDTH(reg) ((reg)->access_width ? (8 << ((reg)->access_width - 1)) : (reg)->bit_width)
+
+/* Shift and apply the mask for CPC reads/writes */
+#define MASK_VAL_READ(reg, val) (((val) >> (reg)->bit_offset) &				\
+					GENMASK(((reg)->bit_width) - 1, 0))
+#define MASK_VAL_WRITE(reg, prev_val, val)						\
+	((((val) & GENMASK(((reg)->bit_width) - 1, 0)) << (reg)->bit_offset) |		\
+	((prev_val) & ~(GENMASK(((reg)->bit_width) - 1, 0) << (reg)->bit_offset)))	\
+
 static ssize_t show_feedback_ctrs(struct kobject *kobj,
-		struct attribute *attr, char *buf)
+		struct kobj_attribute *attr, char *buf)
 {
 	struct cpc_desc *cpc_ptr = to_cpc_desc(kobj);
 	struct cppc_perf_fb_ctrs fb_ctrs = {0};
@@ -170,7 +206,7 @@ static ssize_t show_feedback_ctrs(struct kobject *kobj,
 	if (ret)
 		return ret;
 
-	return scnprintf(buf, PAGE_SIZE, "ref:%llu del:%llu\n",
+	return sysfs_emit(buf, "ref:%llu del:%llu\n",
 			fb_ctrs.reference, fb_ctrs.delivered);
 }
 define_one_cppc_ro(feedback_ctrs);
@@ -182,15 +218,17 @@ static struct attribute *cppc_attrs[] = {
 	&highest_perf.attr,
 	&lowest_perf.attr,
 	&lowest_nonlinear_perf.attr,
+	&guaranteed_perf.attr,
 	&nominal_perf.attr,
 	&nominal_freq.attr,
 	&lowest_freq.attr,
 	NULL
 };
+ATTRIBUTE_GROUPS(cppc);
 
-static struct kobj_type cppc_ktype = {
+static const struct kobj_type cppc_ktype = {
 	.sysfs_ops = &kobj_sysfs_ops,
-	.default_attrs = cppc_attrs,
+	.default_groups = cppc_groups,
 };
 
 static int check_pcc_chan(int pcc_ss_id, bool chk_err_bit)
@@ -198,7 +236,7 @@ static int check_pcc_chan(int pcc_ss_id, bool chk_err_bit)
 	int ret, status;
 	struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
 	struct acpi_pcct_shared_memory __iomem *generic_comm_base =
-		pcc_ss_data->pcc_comm_addr;
+					pcc_ss_data->pcc_channel->shmem;
 
 	if (!pcc_ss_data->platform_owns_pcc)
 		return 0;
@@ -232,8 +270,8 @@ static int send_pcc_cmd(int pcc_ss_id, u16 cmd)
 {
 	int ret = -EIO, i;
 	struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
-	struct acpi_pcct_shared_memory *generic_comm_base =
-		(struct acpi_pcct_shared_memory *)pcc_ss_data->pcc_comm_addr;
+	struct acpi_pcct_shared_memory __iomem *generic_comm_base =
+					pcc_ss_data->pcc_channel->shmem;
 	unsigned int time_delta;
 
 	/*
@@ -303,29 +341,30 @@ static int send_pcc_cmd(int pcc_ss_id, u16 cmd)
 	pcc_ss_data->platform_owns_pcc = true;
 
 	/* Ring doorbell */
-	ret = mbox_send_message(pcc_ss_data->pcc_channel, &cmd);
+	ret = mbox_send_message(pcc_ss_data->pcc_channel->mchan, &cmd);
 	if (ret < 0) {
 		pr_err("Err sending PCC mbox message. ss: %d cmd:%d, ret:%d\n",
 		       pcc_ss_id, cmd, ret);
 		goto end;
 	}
 
-	/* wait for completion and check for PCC errro bit */
+	/* wait for completion and check for PCC error bit */
 	ret = check_pcc_chan(pcc_ss_id, true);
 
 	if (pcc_ss_data->pcc_mrtt)
 		pcc_ss_data->last_cmd_cmpl_time = ktime_get();
 
-	if (pcc_ss_data->pcc_channel->mbox->txdone_irq)
-		mbox_chan_txdone(pcc_ss_data->pcc_channel, ret);
+	if (pcc_ss_data->pcc_channel->mchan->mbox->txdone_irq)
+		mbox_chan_txdone(pcc_ss_data->pcc_channel->mchan, ret);
 	else
-		mbox_client_txdone(pcc_ss_data->pcc_channel, ret);
+		mbox_client_txdone(pcc_ss_data->pcc_channel->mchan, ret);
 
 end:
 	if (cmd == CMD_WRITE) {
 		if (unlikely(ret)) {
 			for_each_possible_cpu(i) {
 				struct cpc_desc *desc = per_cpu(cpc_desc_ptr, i);
+
 				if (!desc)
 					continue;
 
@@ -350,7 +389,7 @@ static void cppc_chan_tx_done(struct mbox_client *cl, void *msg, int ret)
 				*(u16 *)msg, ret);
 }
 
-struct mbox_client cppc_mbox_cl = {
+static struct mbox_client cppc_mbox_cl = {
 	.tx_done = cppc_chan_tx_done,
 	.knows_txdone = true,
 };
@@ -413,159 +452,137 @@ end:
 	return result;
 }
 
+bool acpi_cpc_valid(void)
+{
+	struct cpc_desc *cpc_ptr;
+	int cpu;
+
+	if (acpi_disabled)
+		return false;
+
+	for_each_online_cpu(cpu) {
+		cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
+		if (!cpc_ptr)
+			return false;
+	}
+
+	return true;
+}
+EXPORT_SYMBOL_GPL(acpi_cpc_valid);
+
+bool cppc_allow_fast_switch(void)
+{
+	struct cpc_register_resource *desired_reg;
+	struct cpc_desc *cpc_ptr;
+	int cpu;
+
+	for_each_online_cpu(cpu) {
+		cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
+		desired_reg = &cpc_ptr->cpc_regs[DESIRED_PERF];
+		if (!CPC_IN_SYSTEM_MEMORY(desired_reg) &&
+				!CPC_IN_SYSTEM_IO(desired_reg))
+			return false;
+	}
+
+	return true;
+}
+EXPORT_SYMBOL_GPL(cppc_allow_fast_switch);
+
 /**
- * acpi_get_psd_map - Map the CPUs in a common freq domain.
- * @all_cpu_data: Ptrs to CPU specific CPPC data including PSD info.
+ * acpi_get_psd_map - Map the CPUs in the freq domain of a given cpu
+ * @cpu: Find all CPUs that share a domain with cpu.
+ * @cpu_data: Pointer to CPU specific CPPC data including PSD info.
  *
  *	Return: 0 for success or negative value for err.
  */
-int acpi_get_psd_map(struct cppc_cpudata **all_cpu_data)
+int acpi_get_psd_map(unsigned int cpu, struct cppc_cpudata *cpu_data)
 {
-	int count_target;
-	int retval = 0;
-	unsigned int i, j;
-	cpumask_var_t covered_cpus;
-	struct cppc_cpudata *pr, *match_pr;
-	struct acpi_psd_package *pdomain;
-	struct acpi_psd_package *match_pdomain;
 	struct cpc_desc *cpc_ptr, *match_cpc_ptr;
-
-	if (!zalloc_cpumask_var(&covered_cpus, GFP_KERNEL))
-		return -ENOMEM;
+	struct acpi_psd_package *match_pdomain;
+	struct acpi_psd_package *pdomain;
+	int count_target, i;
 
 	/*
 	 * Now that we have _PSD data from all CPUs, let's setup P-state
 	 * domain info.
 	 */
-	for_each_possible_cpu(i) {
-		if (cpumask_test_cpu(i, covered_cpus))
-			continue;
-
-		pr = all_cpu_data[i];
-		cpc_ptr = per_cpu(cpc_desc_ptr, i);
-		if (!cpc_ptr) {
-			retval = -EFAULT;
-			goto err_ret;
-		}
+	cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
+	if (!cpc_ptr)
+		return -EFAULT;
 
-		pdomain = &(cpc_ptr->domain_info);
-		cpumask_set_cpu(i, pr->shared_cpu_map);
-		cpumask_set_cpu(i, covered_cpus);
-		if (pdomain->num_processors <= 1)
-			continue;
+	pdomain = &(cpc_ptr->domain_info);
+	cpumask_set_cpu(cpu, cpu_data->shared_cpu_map);
+	if (pdomain->num_processors <= 1)
+		return 0;
 
-		/* Validate the Domain info */
-		count_target = pdomain->num_processors;
-		if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ALL)
-			pr->shared_type = CPUFREQ_SHARED_TYPE_ALL;
-		else if (pdomain->coord_type == DOMAIN_COORD_TYPE_HW_ALL)
-			pr->shared_type = CPUFREQ_SHARED_TYPE_HW;
-		else if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ANY)
-			pr->shared_type = CPUFREQ_SHARED_TYPE_ANY;
-
-		for_each_possible_cpu(j) {
-			if (i == j)
-				continue;
-
-			match_cpc_ptr = per_cpu(cpc_desc_ptr, j);
-			if (!match_cpc_ptr) {
-				retval = -EFAULT;
-				goto err_ret;
-			}
+	/* Validate the Domain info */
+	count_target = pdomain->num_processors;
+	if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ALL)
+		cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ALL;
+	else if (pdomain->coord_type == DOMAIN_COORD_TYPE_HW_ALL)
+		cpu_data->shared_type = CPUFREQ_SHARED_TYPE_HW;
+	else if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ANY)
+		cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ANY;
 
-			match_pdomain = &(match_cpc_ptr->domain_info);
-			if (match_pdomain->domain != pdomain->domain)
-				continue;
+	for_each_possible_cpu(i) {
+		if (i == cpu)
+			continue;
 
-			/* Here i and j are in the same domain */
-			if (match_pdomain->num_processors != count_target) {
-				retval = -EFAULT;
-				goto err_ret;
-			}
+		match_cpc_ptr = per_cpu(cpc_desc_ptr, i);
+		if (!match_cpc_ptr)
+			goto err_fault;
 
-			if (pdomain->coord_type != match_pdomain->coord_type) {
-				retval = -EFAULT;
-				goto err_ret;
-			}
+		match_pdomain = &(match_cpc_ptr->domain_info);
+		if (match_pdomain->domain != pdomain->domain)
+			continue;
 
-			cpumask_set_cpu(j, covered_cpus);
-			cpumask_set_cpu(j, pr->shared_cpu_map);
-		}
+		/* Here i and cpu are in the same domain */
+		if (match_pdomain->num_processors != count_target)
+			goto err_fault;
 
-		for_each_cpu(j, pr->shared_cpu_map) {
-			if (i == j)
-				continue;
+		if (pdomain->coord_type != match_pdomain->coord_type)
+			goto err_fault;
 
-			match_pr = all_cpu_data[j];
-			match_pr->shared_type = pr->shared_type;
-			cpumask_copy(match_pr->shared_cpu_map,
-				     pr->shared_cpu_map);
-		}
+		cpumask_set_cpu(i, cpu_data->shared_cpu_map);
 	}
-	goto out;
 
-err_ret:
-	for_each_possible_cpu(i) {
-		pr = all_cpu_data[i];
+	return 0;
 
-		/* Assume no coordination on any error parsing domain info */
-		cpumask_clear(pr->shared_cpu_map);
-		cpumask_set_cpu(i, pr->shared_cpu_map);
-		pr->shared_type = CPUFREQ_SHARED_TYPE_ALL;
-	}
-out:
-	free_cpumask_var(covered_cpus);
-	return retval;
+err_fault:
+	/* Assume no coordination on any error parsing domain info */
+	cpumask_clear(cpu_data->shared_cpu_map);
+	cpumask_set_cpu(cpu, cpu_data->shared_cpu_map);
+	cpu_data->shared_type = CPUFREQ_SHARED_TYPE_NONE;
+
+	return -EFAULT;
 }
 EXPORT_SYMBOL_GPL(acpi_get_psd_map);
 
 static int register_pcc_channel(int pcc_ss_idx)
 {
-	struct acpi_pcct_hw_reduced *cppc_ss;
+	struct pcc_mbox_chan *pcc_chan;
 	u64 usecs_lat;
 
 	if (pcc_ss_idx >= 0) {
-		pcc_data[pcc_ss_idx]->pcc_channel =
-			pcc_mbox_request_channel(&cppc_mbox_cl,	pcc_ss_idx);
+		pcc_chan = pcc_mbox_request_channel(&cppc_mbox_cl, pcc_ss_idx);
 
-		if (IS_ERR(pcc_data[pcc_ss_idx]->pcc_channel)) {
+		if (IS_ERR(pcc_chan)) {
 			pr_err("Failed to find PCC channel for subspace %d\n",
 			       pcc_ss_idx);
 			return -ENODEV;
 		}
 
-		/*
-		 * The PCC mailbox controller driver should
-		 * have parsed the PCCT (global table of all
-		 * PCC channels) and stored pointers to the
-		 * subspace communication region in con_priv.
-		 */
-		cppc_ss = (pcc_data[pcc_ss_idx]->pcc_channel)->con_priv;
-
-		if (!cppc_ss) {
-			pr_err("No PCC subspace found for %d CPPC\n",
-			       pcc_ss_idx);
-			return -ENODEV;
-		}
-
+		pcc_data[pcc_ss_idx]->pcc_channel = pcc_chan;
 		/*
 		 * cppc_ss->latency is just a Nominal value. In reality
 		 * the remote processor could be much slower to reply.
 		 * So add an arbitrary amount of wait on top of Nominal.
 		 */
-		usecs_lat = NUM_RETRIES * cppc_ss->latency;
+		usecs_lat = NUM_RETRIES * pcc_chan->latency;
 		pcc_data[pcc_ss_idx]->deadline_us = usecs_lat;
-		pcc_data[pcc_ss_idx]->pcc_mrtt = cppc_ss->min_turnaround_time;
-		pcc_data[pcc_ss_idx]->pcc_mpar = cppc_ss->max_access_rate;
-		pcc_data[pcc_ss_idx]->pcc_nominal = cppc_ss->latency;
-
-		pcc_data[pcc_ss_idx]->pcc_comm_addr =
-			acpi_os_ioremap(cppc_ss->base_address, cppc_ss->length);
-		if (!pcc_data[pcc_ss_idx]->pcc_comm_addr) {
-			pr_err("Failed to ioremap PCC comm region mem for %d\n",
-			       pcc_ss_idx);
-			return -ENOMEM;
-		}
+		pcc_data[pcc_ss_idx]->pcc_mrtt = pcc_chan->min_turnaround_time;
+		pcc_data[pcc_ss_idx]->pcc_mpar = pcc_chan->max_access_rate;
+		pcc_data[pcc_ss_idx]->pcc_nominal = pcc_chan->latency;
 
 		/* Set flag so that we don't come here for each CPU. */
 		pcc_data[pcc_ss_idx]->pcc_channel_acquired = true;
@@ -588,7 +605,21 @@ bool __weak cpc_ffh_supported(void)
 }
 
 /**
+ * cpc_supported_by_cpu() - check if CPPC is supported by CPU
+ *
+ * Check if the architectural support for CPPC is present even
+ * if the _OSC hasn't prescribed it
+ *
+ * Return: true for supported, false for not supported
+ */
+bool __weak cpc_supported_by_cpu(void)
+{
+	return false;
+}
+
+/**
  * pcc_data_alloc() - Allocate the pcc_data memory for pcc subspace
+ * @pcc_ss_id: PCC Subspace index as in the PCC client ACPI package.
  *
  * Check and allocate the cppc_pcc_data memory.
  * In some processor configurations it is possible that same subspace
@@ -597,7 +628,7 @@ bool __weak cpc_ffh_supported(void)
  *
  * Return: 0 for success, errno for failure
  */
-int pcc_data_alloc(int pcc_ss_id)
+static int pcc_data_alloc(int pcc_ss_id)
 {
 	if (pcc_ss_id < 0 || pcc_ss_id >= MAX_PCC_SUBSPACES)
 		return -EINVAL;
@@ -615,77 +646,33 @@ int pcc_data_alloc(int pcc_ss_id)
 	return 0;
 }
 
-/* Check if CPPC revision + num_ent combination is supported */
-static bool is_cppc_supported(int revision, int num_ent)
-{
-	int expected_num_ent;
-
-	switch (revision) {
-	case CPPC_V2_REV:
-		expected_num_ent = CPPC_V2_NUM_ENT;
-		break;
-	case CPPC_V3_REV:
-		expected_num_ent = CPPC_V3_NUM_ENT;
-		break;
-	default:
-		pr_debug("Firmware exports unsupported CPPC revision: %d\n",
-			revision);
-		return false;
-	}
-
-	if (expected_num_ent != num_ent) {
-		pr_debug("Firmware exports %d entries. Expected: %d for CPPC rev:%d\n",
-			num_ent, expected_num_ent, revision);
-		return false;
-	}
-
-	return true;
-}
-
 /*
  * An example CPC table looks like the following.
  *
- *	Name(_CPC, Package()
- *			{
- *			17,
- *			NumEntries
- *			1,
- *			// Revision
- *			ResourceTemplate(){Register(PCC, 32, 0, 0x120, 2)},
- *			// Highest Performance
- *			ResourceTemplate(){Register(PCC, 32, 0, 0x124, 2)},
- *			// Nominal Performance
- *			ResourceTemplate(){Register(PCC, 32, 0, 0x128, 2)},
- *			// Lowest Nonlinear Performance
- *			ResourceTemplate(){Register(PCC, 32, 0, 0x12C, 2)},
- *			// Lowest Performance
- *			ResourceTemplate(){Register(PCC, 32, 0, 0x130, 2)},
- *			// Guaranteed Performance Register
- *			ResourceTemplate(){Register(PCC, 32, 0, 0x110, 2)},
- *			// Desired Performance Register
- *			ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)},
- *			..
- *			..
- *			..
- *
- *		}
+ *  Name (_CPC, Package() {
+ *      17,							// NumEntries
+ *      1,							// Revision
+ *      ResourceTemplate() {Register(PCC, 32, 0, 0x120, 2)},	// Highest Performance
+ *      ResourceTemplate() {Register(PCC, 32, 0, 0x124, 2)},	// Nominal Performance
+ *      ResourceTemplate() {Register(PCC, 32, 0, 0x128, 2)},	// Lowest Nonlinear Performance
+ *      ResourceTemplate() {Register(PCC, 32, 0, 0x12C, 2)},	// Lowest Performance
+ *      ResourceTemplate() {Register(PCC, 32, 0, 0x130, 2)},	// Guaranteed Performance Register
+ *      ResourceTemplate() {Register(PCC, 32, 0, 0x110, 2)},	// Desired Performance Register
+ *      ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)},
+ *      ...
+ *      ...
+ *      ...
+ *  }
  * Each Register() encodes how to access that specific register.
  * e.g. a sample PCC entry has the following encoding:
  *
- *	Register (
- *		PCC,
- *		AddressSpaceKeyword
- *		8,
- *		//RegisterBitWidth
- *		8,
- *		//RegisterBitOffset
- *		0x30,
- *		//RegisterAddress
- *		9
- *		//AccessSize (subspace ID)
- *		0
- *		)
- *	}
+ *  Register (
+ *      PCC,	// AddressSpaceKeyword
+ *      8,	// RegisterBitWidth
+ *      8,	// RegisterBitOffset
+ *      0x30,	// RegisterAddress
+ *      9,	// AccessSize (subspace ID)
+ *  )
  */
 
 /**
@@ -705,7 +692,15 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 	unsigned int num_ent, i, cpc_rev;
 	int pcc_subspace_id = -1;
 	acpi_status status;
-	int ret = -EFAULT;
+	int ret = -ENODATA;
+
+	if (!osc_sb_cppc2_support_acked) {
+		pr_debug("CPPC v2 _OSC not acked\n");
+		if (!cpc_supported_by_cpu()) {
+			pr_debug("CPPC is not supported by the CPU\n");
+			return -ENODEV;
+		}
+	}
 
 	/* Parse the ACPI _CPC table for this CPU. */
 	status = acpi_evaluate_object_typed(handle, "_CPC", NULL, &output,
@@ -727,26 +722,52 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 	cpc_obj = &out_obj->package.elements[0];
 	if (cpc_obj->type == ACPI_TYPE_INTEGER)	{
 		num_ent = cpc_obj->integer.value;
+		if (num_ent <= 1) {
+			pr_debug("Unexpected _CPC NumEntries value (%d) for CPU:%d\n",
+				 num_ent, pr->id);
+			goto out_free;
+		}
 	} else {
-		pr_debug("Unexpected entry type(%d) for NumEntries\n",
-				cpc_obj->type);
+		pr_debug("Unexpected _CPC NumEntries entry type (%d) for CPU:%d\n",
+			 cpc_obj->type, pr->id);
 		goto out_free;
 	}
-	cpc_ptr->num_entries = num_ent;
 
 	/* Second entry should be revision. */
 	cpc_obj = &out_obj->package.elements[1];
 	if (cpc_obj->type == ACPI_TYPE_INTEGER)	{
 		cpc_rev = cpc_obj->integer.value;
 	} else {
-		pr_debug("Unexpected entry type(%d) for Revision\n",
-				cpc_obj->type);
+		pr_debug("Unexpected _CPC Revision entry type (%d) for CPU:%d\n",
+			 cpc_obj->type, pr->id);
+		goto out_free;
+	}
+
+	if (cpc_rev < CPPC_V2_REV) {
+		pr_debug("Unsupported _CPC Revision (%d) for CPU:%d\n", cpc_rev,
+			 pr->id);
 		goto out_free;
 	}
-	cpc_ptr->version = cpc_rev;
 
-	if (!is_cppc_supported(cpc_rev, num_ent))
+	/*
+	 * Disregard _CPC if the number of entries in the return package is not
+	 * as expected, but support future revisions being proper supersets of
+	 * the v3 and only causing more entries to be returned by _CPC.
+	 */
+	if ((cpc_rev == CPPC_V2_REV && num_ent != CPPC_V2_NUM_ENT) ||
+	    (cpc_rev == CPPC_V3_REV && num_ent != CPPC_V3_NUM_ENT) ||
+	    (cpc_rev > CPPC_V3_REV && num_ent <= CPPC_V3_NUM_ENT)) {
+		pr_debug("Unexpected number of _CPC return package entries (%d) for CPU:%d\n",
+			 num_ent, pr->id);
 		goto out_free;
+	}
+	if (cpc_rev > CPPC_V3_REV) {
+		num_ent = CPPC_V3_NUM_ENT;
+		cpc_rev = CPPC_V3_REV;
+	}
+
+	cpc_ptr->num_entries = num_ent;
+	cpc_ptr->version = cpc_rev;
 
 	/* Iterate through remaining entries in _CPC */
 	for (i = 2; i < num_ent; i++) {
@@ -771,22 +792,54 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 					if (pcc_data_alloc(pcc_subspace_id))
 						goto out_free;
 				} else if (pcc_subspace_id != gas_t->access_width) {
-					pr_debug("Mismatched PCC ids.\n");
+					pr_debug("Mismatched PCC ids in _CPC for CPU:%d\n",
+						 pr->id);
 					goto out_free;
 				}
 			} else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
 				if (gas_t->address) {
 					void __iomem *addr;
+					size_t access_width;
+
+					if (!osc_cpc_flexible_adr_space_confirmed) {
+						pr_debug("Flexible address space capability not supported\n");
+						if (!cpc_supported_by_cpu())
+							goto out_free;
+					}
 
-					addr = ioremap(gas_t->address, gas_t->bit_width/8);
+					access_width = GET_BIT_WIDTH(gas_t) / 8;
+					addr = ioremap(gas_t->address, access_width);
 					if (!addr)
 						goto out_free;
 					cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr;
 				}
+			} else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
+				if (gas_t->access_width < 1 || gas_t->access_width > 3) {
+					/*
+					 * 1 = 8-bit, 2 = 16-bit, and 3 = 32-bit.
+					 * SystemIO doesn't implement 64-bit
+					 * registers.
+					 */
+					pr_debug("Invalid access width %d for SystemIO register in _CPC\n",
+						 gas_t->access_width);
+					goto out_free;
+				}
+				if (gas_t->address & OVER_16BTS_MASK) {
+					/* SystemIO registers use 16-bit integer addresses */
+					pr_debug("Invalid IO port %llu for SystemIO register in _CPC\n",
+						 gas_t->address);
+					goto out_free;
+				}
+				if (!osc_cpc_flexible_adr_space_confirmed) {
+					pr_debug("Flexible address space capability not supported\n");
+					if (!cpc_supported_by_cpu())
+						goto out_free;
+				}
 			} else {
 				if (gas_t->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE || !cpc_ffh_supported()) {
-					/* Support only PCC ,SYS MEM and FFH type regs */
-					pr_debug("Unsupported register type: %d\n", gas_t->space_id);
+					/* Support only PCC, SystemMemory, SystemIO, and FFH type regs. */
+					pr_debug("Unsupported register type (%d) in _CPC\n",
+						 gas_t->space_id);
 					goto out_free;
 				}
 			}
@@ -794,7 +847,8 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 			cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_BUFFER;
 			memcpy(&cpc_ptr->cpc_regs[i-2].cpc_entry.reg, gas_t, sizeof(*gas_t));
 		} else {
-			pr_debug("Err in entry:%d in CPC table of CPU:%d \n", i, pr->id);
+			pr_debug("Invalid entry type (%d) in _CPC for CPU:%d\n",
+				 i, pr->id);
 			goto out_free;
 		}
 	}
@@ -813,6 +867,7 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 
 	/* Store CPU Logical ID */
 	cpc_ptr->cpu_id = pr->id;
+	raw_spin_lock_init(&cpc_ptr->rmw_lock);
 
 	/* Parse PSD data for this CPU */
 	ret = acpi_get_psd(cpc_ptr, handle);
@@ -846,6 +901,7 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 			"acpi_cppc");
 	if (ret) {
 		per_cpu(cpc_desc_ptr, pr->id) = NULL;
+		kobject_put(&cpc_ptr->kobj);
 		goto out_free;
 	}
 
@@ -881,7 +937,7 @@ void acpi_cppc_processor_exit(struct acpi_processor *pr)
 	void __iomem *addr;
 	int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, pr->id);
 
-	if (pcc_ss_id >=0 && pcc_data[pcc_ss_id]) {
+	if (pcc_ss_id >= 0 && pcc_data[pcc_ss_id]) {
 		if (pcc_data[pcc_ss_id]->pcc_channel_acquired) {
 			pcc_data[pcc_ss_id]->refcount--;
 			if (!pcc_data[pcc_ss_id]->refcount) {
@@ -946,132 +1002,337 @@ int __weak cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val)
 
 static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val)
 {
-	int ret_val = 0;
-	void __iomem *vaddr = 0;
+	void __iomem *vaddr = NULL;
+	int size;
 	int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
 	struct cpc_reg *reg = &reg_res->cpc_entry.reg;
 
 	if (reg_res->type == ACPI_TYPE_INTEGER) {
 		*val = reg_res->cpc_entry.int_value;
-		return ret_val;
+		return 0;
 	}
 
 	*val = 0;
-	if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0)
+	size = GET_BIT_WIDTH(reg);
+
+	if (IS_ENABLED(CONFIG_HAS_IOPORT) &&
+	    reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
+		u32 val_u32;
+		acpi_status status;
+
+		status = acpi_os_read_port((acpi_io_address)reg->address,
+					   &val_u32, size);
+		if (ACPI_FAILURE(status)) {
+			pr_debug("Error: Failed to read SystemIO port %llx\n",
+				 reg->address);
+			return -EFAULT;
+		}
+
+		*val = val_u32;
+		return 0;
+	} else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) {
+		/*
+		 * For registers in PCC space, the register size is determined
+		 * by the bit width field; the access size is used to indicate
+		 * the PCC subspace id.
+		 */
+		size = reg->bit_width;
 		vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
+	}
 	else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
 		vaddr = reg_res->sys_mem_vaddr;
 	else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
 		return cpc_read_ffh(cpu, reg, val);
 	else
 		return acpi_os_read_memory((acpi_physical_address)reg->address,
-				val, reg->bit_width);
+				val, size);
 
-	switch (reg->bit_width) {
-		case 8:
-			*val = readb_relaxed(vaddr);
-			break;
-		case 16:
-			*val = readw_relaxed(vaddr);
-			break;
-		case 32:
-			*val = readl_relaxed(vaddr);
-			break;
-		case 64:
-			*val = readq_relaxed(vaddr);
-			break;
-		default:
+	switch (size) {
+	case 8:
+		*val = readb_relaxed(vaddr);
+		break;
+	case 16:
+		*val = readw_relaxed(vaddr);
+		break;
+	case 32:
+		*val = readl_relaxed(vaddr);
+		break;
+	case 64:
+		*val = readq_relaxed(vaddr);
+		break;
+	default:
+		if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
+			pr_debug("Error: Cannot read %u bit width from system memory: 0x%llx\n",
+				size, reg->address);
+		} else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
 			pr_debug("Error: Cannot read %u bit width from PCC for ss: %d\n",
-				 reg->bit_width, pcc_ss_id);
-			ret_val = -EFAULT;
+				size, pcc_ss_id);
+		}
+		return -EFAULT;
 	}
 
-	return ret_val;
+	if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
+		*val = MASK_VAL_READ(reg, *val);
+
+	return 0;
 }
 
 static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
 {
 	int ret_val = 0;
-	void __iomem *vaddr = 0;
+	int size;
+	u64 prev_val;
+	void __iomem *vaddr = NULL;
 	int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
 	struct cpc_reg *reg = &reg_res->cpc_entry.reg;
+	struct cpc_desc *cpc_desc;
+	unsigned long flags;
+
+	size = GET_BIT_WIDTH(reg);
+
+	if (IS_ENABLED(CONFIG_HAS_IOPORT) &&
+	    reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
+		acpi_status status;
 
-	if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0)
+		status = acpi_os_write_port((acpi_io_address)reg->address,
+					    (u32)val, size);
+		if (ACPI_FAILURE(status)) {
+			pr_debug("Error: Failed to write SystemIO port %llx\n",
+				 reg->address);
+			return -EFAULT;
+		}
+
+		return 0;
+	} else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) {
+		/*
+		 * For registers in PCC space, the register size is determined
+		 * by the bit width field; the access size is used to indicate
+		 * the PCC subspace id.
+		 */
+		size = reg->bit_width;
 		vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
+	}
 	else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
 		vaddr = reg_res->sys_mem_vaddr;
 	else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
 		return cpc_write_ffh(cpu, reg, val);
 	else
 		return acpi_os_write_memory((acpi_physical_address)reg->address,
-				val, reg->bit_width);
+				val, size);
+
+	if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
+		cpc_desc = per_cpu(cpc_desc_ptr, cpu);
+		if (!cpc_desc) {
+			pr_debug("No CPC descriptor for CPU:%d\n", cpu);
+			return -ENODEV;
+		}
 
-	switch (reg->bit_width) {
+		raw_spin_lock_irqsave(&cpc_desc->rmw_lock, flags);
+		switch (size) {
 		case 8:
-			writeb_relaxed(val, vaddr);
+			prev_val = readb_relaxed(vaddr);
 			break;
 		case 16:
-			writew_relaxed(val, vaddr);
+			prev_val = readw_relaxed(vaddr);
 			break;
 		case 32:
-			writel_relaxed(val, vaddr);
+			prev_val = readl_relaxed(vaddr);
 			break;
 		case 64:
-			writeq_relaxed(val, vaddr);
+			prev_val = readq_relaxed(vaddr);
 			break;
 		default:
+			raw_spin_unlock_irqrestore(&cpc_desc->rmw_lock, flags);
+			return -EFAULT;
+		}
+		val = MASK_VAL_WRITE(reg, prev_val, val);
+	}
+
+	switch (size) {
+	case 8:
+		writeb_relaxed(val, vaddr);
+		break;
+	case 16:
+		writew_relaxed(val, vaddr);
+		break;
+	case 32:
+		writel_relaxed(val, vaddr);
+		break;
+	case 64:
+		writeq_relaxed(val, vaddr);
+		break;
+	default:
+		if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
+			pr_debug("Error: Cannot write %u bit width to system memory: 0x%llx\n",
+				size, reg->address);
+		} else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
 			pr_debug("Error: Cannot write %u bit width to PCC for ss: %d\n",
-				 reg->bit_width, pcc_ss_id);
-			ret_val = -EFAULT;
-			break;
+				size, pcc_ss_id);
+		}
+		ret_val = -EFAULT;
+		break;
 	}
 
+	if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
+		raw_spin_unlock_irqrestore(&cpc_desc->rmw_lock, flags);
+
 	return ret_val;
 }
 
-/**
- * cppc_get_desired_perf - Get the value of desired performance register.
- * @cpunum: CPU from which to get desired performance.
- * @desired_perf: address of a variable to store the returned desired performance
- *
- * Return: 0 for success, -EIO otherwise.
- */
-int cppc_get_desired_perf(int cpunum, u64 *desired_perf)
+static int cppc_get_reg_val_in_pcc(int cpu, struct cpc_register_resource *reg, u64 *val)
 {
-	struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
-	int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
-	struct cpc_register_resource *desired_reg;
+	int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
 	struct cppc_pcc_data *pcc_ss_data = NULL;
+	int ret;
 
-	desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
+	if (pcc_ss_id < 0) {
+		pr_debug("Invalid pcc_ss_id\n");
+		return -ENODEV;
+	}
 
-	if (CPC_IN_PCC(desired_reg)) {
-		int ret = 0;
+	pcc_ss_data = pcc_data[pcc_ss_id];
 
-		if (pcc_ss_id < 0)
-			return -EIO;
+	down_write(&pcc_ss_data->pcc_lock);
 
-		pcc_ss_data = pcc_data[pcc_ss_id];
+	if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0)
+		ret = cpc_read(cpu, reg, val);
+	else
+		ret = -EIO;
 
-		down_write(&pcc_ss_data->pcc_lock);
+	up_write(&pcc_ss_data->pcc_lock);
 
-		if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0)
-			cpc_read(cpunum, desired_reg, desired_perf);
-		else
-			ret = -EIO;
+	return ret;
+}
 
-		up_write(&pcc_ss_data->pcc_lock);
+static int cppc_get_reg_val(int cpu, enum cppc_regs reg_idx, u64 *val)
+{
+	struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
+	struct cpc_register_resource *reg;
+
+	if (val == NULL)
+		return -EINVAL;
+
+	if (!cpc_desc) {
+		pr_debug("No CPC descriptor for CPU:%d\n", cpu);
+		return -ENODEV;
+	}
+
+	reg = &cpc_desc->cpc_regs[reg_idx];
+
+	if ((reg->type == ACPI_TYPE_INTEGER && IS_OPTIONAL_CPC_REG(reg_idx) &&
+	     !reg->cpc_entry.int_value) || (reg->type != ACPI_TYPE_INTEGER &&
+	     IS_NULL_REG(&reg->cpc_entry.reg))) {
+		pr_debug("CPC register is not supported\n");
+		return -EOPNOTSUPP;
+	}
+
+	if (CPC_IN_PCC(reg))
+		return cppc_get_reg_val_in_pcc(cpu, reg, val);
+
+	return cpc_read(cpu, reg, val);
+}
+
+static int cppc_set_reg_val_in_pcc(int cpu, struct cpc_register_resource *reg, u64 val)
+{
+	int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
+	struct cppc_pcc_data *pcc_ss_data = NULL;
+	int ret;
 
+	if (pcc_ss_id < 0) {
+		pr_debug("Invalid pcc_ss_id\n");
+		return -ENODEV;
+	}
+
+	ret = cpc_write(cpu, reg, val);
+	if (ret)
 		return ret;
+
+	pcc_ss_data = pcc_data[pcc_ss_id];
+
+	down_write(&pcc_ss_data->pcc_lock);
+	/* after writing CPC, transfer the ownership of PCC to platform */
+	ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
+	up_write(&pcc_ss_data->pcc_lock);
+
+	return ret;
+}
+
+static int cppc_set_reg_val(int cpu, enum cppc_regs reg_idx, u64 val)
+{
+	struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
+	struct cpc_register_resource *reg;
+
+	if (!cpc_desc) {
+		pr_debug("No CPC descriptor for CPU:%d\n", cpu);
+		return -ENODEV;
 	}
 
-	cpc_read(cpunum, desired_reg, desired_perf);
+	reg = &cpc_desc->cpc_regs[reg_idx];
 
-	return 0;
+	/* if a register is writeable, it must be a buffer and not null */
+	if ((reg->type != ACPI_TYPE_BUFFER) || IS_NULL_REG(&reg->cpc_entry.reg)) {
+		pr_debug("CPC register is not supported\n");
+		return -EOPNOTSUPP;
+	}
+
+	if (CPC_IN_PCC(reg))
+		return cppc_set_reg_val_in_pcc(cpu, reg, val);
+
+	return cpc_write(cpu, reg, val);
+}
+
+/**
+ * cppc_get_desired_perf - Get the desired performance register value.
+ * @cpunum: CPU from which to get desired performance.
+ * @desired_perf: Return address.
+ *
+ * Return: 0 for success, -EIO otherwise.
+ */
+int cppc_get_desired_perf(int cpunum, u64 *desired_perf)
+{
+	return cppc_get_reg_val(cpunum, DESIRED_PERF, desired_perf);
 }
 EXPORT_SYMBOL_GPL(cppc_get_desired_perf);
 
 /**
+ * cppc_get_nominal_perf - Get the nominal performance register value.
+ * @cpunum: CPU from which to get nominal performance.
+ * @nominal_perf: Return address.
+ *
+ * Return: 0 for success, -EIO otherwise.
+ */
+int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf)
+{
+	return cppc_get_reg_val(cpunum, NOMINAL_PERF, nominal_perf);
+}
+
+/**
+ * cppc_get_highest_perf - Get the highest performance register value.
+ * @cpunum: CPU from which to get highest performance.
+ * @highest_perf: Return address.
+ *
+ * Return: 0 for success, -EIO otherwise.
+ */
+int cppc_get_highest_perf(int cpunum, u64 *highest_perf)
+{
+	return cppc_get_reg_val(cpunum, HIGHEST_PERF, highest_perf);
+}
+EXPORT_SYMBOL_GPL(cppc_get_highest_perf);
+
+/**
+ * cppc_get_epp_perf - Get the epp register value.
+ * @cpunum: CPU from which to get epp preference value.
+ * @epp_perf: Return address.
+ *
+ * Return: 0 for success, -EIO otherwise.
+ */
+int cppc_get_epp_perf(int cpunum, u64 *epp_perf)
+{
+	return cppc_get_reg_val(cpunum, ENERGY_PERF, epp_perf);
+}
+EXPORT_SYMBOL_GPL(cppc_get_epp_perf);
+
+/**
  * cppc_get_perf_caps - Get a CPU's performance capabilities.
  * @cpunum: CPU from which to get capabilities info.
  * @perf_caps: ptr to cppc_perf_caps. See cppc_acpi.h
@@ -1162,6 +1423,48 @@ out_err:
 EXPORT_SYMBOL_GPL(cppc_get_perf_caps);
 
 /**
+ * cppc_perf_ctrs_in_pcc - Check if any perf counters are in a PCC region.
+ *
+ * CPPC has flexibility about how CPU performance counters are accessed.
+ * One of the choices is PCC regions, which can have a high access latency. This
+ * routine allows callers of cppc_get_perf_ctrs() to know this ahead of time.
+ *
+ * Return: true if any of the counters are in PCC regions, false otherwise
+ */
+bool cppc_perf_ctrs_in_pcc(void)
+{
+	int cpu;
+
+	for_each_online_cpu(cpu) {
+		struct cpc_register_resource *ref_perf_reg;
+		struct cpc_desc *cpc_desc;
+
+		cpc_desc = per_cpu(cpc_desc_ptr, cpu);
+
+		if (CPC_IN_PCC(&cpc_desc->cpc_regs[DELIVERED_CTR]) ||
+		    CPC_IN_PCC(&cpc_desc->cpc_regs[REFERENCE_CTR]) ||
+		    CPC_IN_PCC(&cpc_desc->cpc_regs[CTR_WRAP_TIME]))
+			return true;
+
+
+		ref_perf_reg = &cpc_desc->cpc_regs[REFERENCE_PERF];
+
+		/*
+		 * If reference perf register is not supported then we should
+		 * use the nominal perf value
+		 */
+		if (!CPC_SUPPORTED(ref_perf_reg))
+			ref_perf_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
+
+		if (CPC_IN_PCC(ref_perf_reg))
+			return true;
+	}
+
+	return false;
+}
+EXPORT_SYMBOL_GPL(cppc_perf_ctrs_in_pcc);
+
+/**
  * cppc_get_perf_ctrs - Read a CPU's performance feedback counters.
  * @cpunum: CPU from which to read counters.
  * @perf_fb_ctrs: ptr to cppc_perf_fb_ctrs. See cppc_acpi.h
@@ -1241,6 +1544,194 @@ out_err:
 }
 EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs);
 
+/*
+ * Set Energy Performance Preference Register value through
+ * Performance Controls Interface
+ */
+int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable)
+{
+	int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
+	struct cpc_register_resource *epp_set_reg;
+	struct cpc_register_resource *auto_sel_reg;
+	struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
+	struct cppc_pcc_data *pcc_ss_data = NULL;
+	int ret;
+
+	if (!cpc_desc) {
+		pr_debug("No CPC descriptor for CPU:%d\n", cpu);
+		return -ENODEV;
+	}
+
+	auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
+	epp_set_reg = &cpc_desc->cpc_regs[ENERGY_PERF];
+
+	if (CPC_IN_PCC(epp_set_reg) || CPC_IN_PCC(auto_sel_reg)) {
+		if (pcc_ss_id < 0) {
+			pr_debug("Invalid pcc_ss_id for CPU:%d\n", cpu);
+			return -ENODEV;
+		}
+
+		if (CPC_SUPPORTED(auto_sel_reg)) {
+			ret = cpc_write(cpu, auto_sel_reg, enable);
+			if (ret)
+				return ret;
+		}
+
+		if (CPC_SUPPORTED(epp_set_reg)) {
+			ret = cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf);
+			if (ret)
+				return ret;
+		}
+
+		pcc_ss_data = pcc_data[pcc_ss_id];
+
+		down_write(&pcc_ss_data->pcc_lock);
+		/* after writing CPC, transfer the ownership of PCC to platform */
+		ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
+		up_write(&pcc_ss_data->pcc_lock);
+	} else if (osc_cpc_flexible_adr_space_confirmed &&
+		   CPC_SUPPORTED(epp_set_reg) && CPC_IN_FFH(epp_set_reg)) {
+		ret = cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf);
+	} else {
+		ret = -ENOTSUPP;
+		pr_debug("_CPC in PCC and _CPC in FFH are not supported\n");
+	}
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(cppc_set_epp_perf);
+
+/**
+ * cppc_set_epp() - Write the EPP register.
+ * @cpu: CPU on which to write register.
+ * @epp_val: Value to write to the EPP register.
+ */
+int cppc_set_epp(int cpu, u64 epp_val)
+{
+	if (epp_val > CPPC_ENERGY_PERF_MAX)
+		return -EINVAL;
+
+	return cppc_set_reg_val(cpu, ENERGY_PERF, epp_val);
+}
+EXPORT_SYMBOL_GPL(cppc_set_epp);
+
+/**
+ * cppc_get_auto_act_window() - Read autonomous activity window register.
+ * @cpu: CPU from which to read register.
+ * @auto_act_window: Return address.
+ *
+ * According to ACPI 6.5, s8.4.6.1.6, the value read from the autonomous
+ * activity window register consists of two parts: a 7 bits value indicate
+ * significand and a 3 bits value indicate exponent.
+ */
+int cppc_get_auto_act_window(int cpu, u64 *auto_act_window)
+{
+	unsigned int exp;
+	u64 val, sig;
+	int ret;
+
+	if (auto_act_window == NULL)
+		return -EINVAL;
+
+	ret = cppc_get_reg_val(cpu, AUTO_ACT_WINDOW, &val);
+	if (ret)
+		return ret;
+
+	sig = val & CPPC_AUTO_ACT_WINDOW_MAX_SIG;
+	exp = (val >> CPPC_AUTO_ACT_WINDOW_SIG_BIT_SIZE) & CPPC_AUTO_ACT_WINDOW_MAX_EXP;
+	*auto_act_window = sig * int_pow(10, exp);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(cppc_get_auto_act_window);
+
+/**
+ * cppc_set_auto_act_window() - Write autonomous activity window register.
+ * @cpu: CPU on which to write register.
+ * @auto_act_window: usec value to write to the autonomous activity window register.
+ *
+ * According to ACPI 6.5, s8.4.6.1.6, the value to write to the autonomous
+ * activity window register consists of two parts: a 7 bits value indicate
+ * significand and a 3 bits value indicate exponent.
+ */
+int cppc_set_auto_act_window(int cpu, u64 auto_act_window)
+{
+	/* The max value to store is 1270000000 */
+	u64 max_val = CPPC_AUTO_ACT_WINDOW_MAX_SIG * int_pow(10, CPPC_AUTO_ACT_WINDOW_MAX_EXP);
+	int exp = 0;
+	u64 val;
+
+	if (auto_act_window > max_val)
+		return -EINVAL;
+
+	/*
+	 * The max significand is 127, when auto_act_window is larger than
+	 * 129, discard the precision of the last digit and increase the
+	 * exponent by 1.
+	 */
+	while (auto_act_window > CPPC_AUTO_ACT_WINDOW_SIG_CARRY_THRESH) {
+		auto_act_window /= 10;
+		exp += 1;
+	}
+
+	/* For 128 and 129, cut it to 127. */
+	if (auto_act_window > CPPC_AUTO_ACT_WINDOW_MAX_SIG)
+		auto_act_window = CPPC_AUTO_ACT_WINDOW_MAX_SIG;
+
+	val = (exp << CPPC_AUTO_ACT_WINDOW_SIG_BIT_SIZE) + auto_act_window;
+
+	return cppc_set_reg_val(cpu, AUTO_ACT_WINDOW, val);
+}
+EXPORT_SYMBOL_GPL(cppc_set_auto_act_window);
+
+/**
+ * cppc_get_auto_sel() - Read autonomous selection register.
+ * @cpu: CPU from which to read register.
+ * @enable: Return address.
+ */
+int cppc_get_auto_sel(int cpu, bool *enable)
+{
+	u64 auto_sel;
+	int ret;
+
+	if (enable == NULL)
+		return -EINVAL;
+
+	ret = cppc_get_reg_val(cpu, AUTO_SEL_ENABLE, &auto_sel);
+	if (ret)
+		return ret;
+
+	*enable = (bool)auto_sel;
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(cppc_get_auto_sel);
+
+/**
+ * cppc_set_auto_sel - Write autonomous selection register.
+ * @cpu    : CPU to which to write register.
+ * @enable : the desired value of autonomous selection resiter to be updated.
+ */
+int cppc_set_auto_sel(int cpu, bool enable)
+{
+	return cppc_set_reg_val(cpu, AUTO_SEL_ENABLE, enable);
+}
+EXPORT_SYMBOL_GPL(cppc_set_auto_sel);
+
+/**
+ * cppc_set_enable - Set to enable CPPC on the processor by writing the
+ * Continuous Performance Control package EnableRegister field.
+ * @cpu: CPU for which to enable CPPC register.
+ * @enable: 0 - disable, 1 - enable CPPC feature on the processor.
+ *
+ * Return: 0 for success, -ERRNO or -EIO otherwise.
+ */
+int cppc_set_enable(int cpu, bool enable)
+{
+	return cppc_set_reg_val(cpu, ENABLE, enable);
+}
+EXPORT_SYMBOL_GPL(cppc_set_enable);
+
 /**
  * cppc_set_perf - Set a CPU's performance controls.
  * @cpu: CPU for which to set performance controls.
@@ -1251,7 +1742,7 @@ EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs);
 int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
 {
 	struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
-	struct cpc_register_resource *desired_reg;
+	struct cpc_register_resource *desired_reg, *min_perf_reg, *max_perf_reg;
 	int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
 	struct cppc_pcc_data *pcc_ss_data = NULL;
 	int ret = 0;
@@ -1262,6 +1753,8 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
 	}
 
 	desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
+	min_perf_reg = &cpc_desc->cpc_regs[MIN_PERF];
+	max_perf_reg = &cpc_desc->cpc_regs[MAX_PERF];
 
 	/*
 	 * This is Phase-I where we want to write to CPC registers
@@ -1270,7 +1763,7 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
 	 * Since read_lock can be acquired by multiple CPUs simultaneously we
 	 * achieve that goal here
 	 */
-	if (CPC_IN_PCC(desired_reg)) {
+	if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max_perf_reg)) {
 		if (pcc_ss_id < 0) {
 			pr_debug("Invalid pcc_ss_id\n");
 			return -ENODEV;
@@ -1293,13 +1786,19 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
 		cpc_desc->write_cmd_status = 0;
 	}
 
+	cpc_write(cpu, desired_reg, perf_ctrls->desired_perf);
+
 	/*
-	 * Skip writing MIN/MAX until Linux knows how to come up with
-	 * useful values.
+	 * Only write if min_perf and max_perf not zero. Some drivers pass zero
+	 * value to min and max perf, but they don't mean to set the zero value,
+	 * they just don't want to write to those registers.
 	 */
-	cpc_write(cpu, desired_reg, perf_ctrls->desired_perf);
+	if (perf_ctrls->min_perf)
+		cpc_write(cpu, min_perf_reg, perf_ctrls->min_perf);
+	if (perf_ctrls->max_perf)
+		cpc_write(cpu, max_perf_reg, perf_ctrls->max_perf);
 
-	if (CPC_IN_PCC(desired_reg))
+	if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max_perf_reg))
 		up_read(&pcc_ss_data->pcc_lock);	/* END Phase-I */
 	/*
 	 * This is Phase-II where we transfer the ownership of PCC to Platform
@@ -1343,11 +1842,11 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
 	 * is still with OSPM.
 	 *   pending_pcc_write_cmd can also be cleared by a different CPU, if
 	 * there was a pcc CMD_READ waiting on down_write and it steals the lock
-	 * before the pcc CMD_WRITE is completed. pcc_send_cmd checks for this
+	 * before the pcc CMD_WRITE is completed. send_pcc_cmd checks for this
 	 * case during a CMD_READ and if there are pending writes it delivers
 	 * the write command before servicing the read command
 	 */
-	if (CPC_IN_PCC(desired_reg)) {
+	if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max_perf_reg)) {
 		if (down_write_trylock(&pcc_ss_data->pcc_lock)) {/* BEGIN Phase-II */
 			/* Update only if there are pending write commands */
 			if (pcc_ss_data->pending_pcc_write_cmd)
@@ -1367,13 +1866,17 @@ EXPORT_SYMBOL_GPL(cppc_set_perf);
 
 /**
  * cppc_get_transition_latency - returns frequency transition latency in ns
+ * @cpu_num: CPU number for per_cpu().
  *
- * ACPI CPPC does not explicitly specifiy how a platform can specify the
- * transition latency for perfromance change requests. The closest we have
+ * ACPI CPPC does not explicitly specify how a platform can specify the
+ * transition latency for performance change requests. The closest we have
  * is the timing information from the PCCT tables which provides the info
  * on the number and frequency of PCC commands the platform can handle.
+ *
+ * If desired_reg is in the SystemMemory or SystemIo ACPI address space,
+ * then assume there is no latency.
  */
-unsigned int cppc_get_transition_latency(int cpu_num)
+int cppc_get_transition_latency(int cpu_num)
 {
 	/*
 	 * Expected transition latency is based on the PCCT timing values
@@ -1386,30 +1889,143 @@ unsigned int cppc_get_transition_latency(int cpu_num)
 	 *              completion of a command before issuing the next command,
 	 *              in microseconds.
 	 */
-	unsigned int latency_ns = 0;
 	struct cpc_desc *cpc_desc;
 	struct cpc_register_resource *desired_reg;
 	int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu_num);
 	struct cppc_pcc_data *pcc_ss_data;
+	int latency_ns = 0;
 
 	cpc_desc = per_cpu(cpc_desc_ptr, cpu_num);
 	if (!cpc_desc)
-		return CPUFREQ_ETERNAL;
+		return -ENODATA;
 
 	desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
-	if (!CPC_IN_PCC(desired_reg))
-		return CPUFREQ_ETERNAL;
+	if (CPC_IN_SYSTEM_MEMORY(desired_reg) || CPC_IN_SYSTEM_IO(desired_reg))
+		return 0;
 
-	if (pcc_ss_id < 0)
-		return CPUFREQ_ETERNAL;
+	if (!CPC_IN_PCC(desired_reg) || pcc_ss_id < 0)
+		return -ENODATA;
 
 	pcc_ss_data = pcc_data[pcc_ss_id];
 	if (pcc_ss_data->pcc_mpar)
 		latency_ns = 60 * (1000 * 1000 * 1000 / pcc_ss_data->pcc_mpar);
 
-	latency_ns = max(latency_ns, pcc_ss_data->pcc_nominal * 1000);
-	latency_ns = max(latency_ns, pcc_ss_data->pcc_mrtt * 1000);
+	latency_ns = max_t(int, latency_ns, pcc_ss_data->pcc_nominal * 1000);
+	latency_ns = max_t(int, latency_ns, pcc_ss_data->pcc_mrtt * 1000);
 
 	return latency_ns;
 }
 EXPORT_SYMBOL_GPL(cppc_get_transition_latency);
+
+/* Minimum struct length needed for the DMI processor entry we want */
+#define DMI_ENTRY_PROCESSOR_MIN_LENGTH	48
+
+/* Offset in the DMI processor structure for the max frequency */
+#define DMI_PROCESSOR_MAX_SPEED		0x14
+
+/* Callback function used to retrieve the max frequency from DMI */
+static void cppc_find_dmi_mhz(const struct dmi_header *dm, void *private)
+{
+	const u8 *dmi_data = (const u8 *)dm;
+	u16 *mhz = (u16 *)private;
+
+	if (dm->type == DMI_ENTRY_PROCESSOR &&
+	    dm->length >= DMI_ENTRY_PROCESSOR_MIN_LENGTH) {
+		u16 val = (u16)get_unaligned((const u16 *)
+				(dmi_data + DMI_PROCESSOR_MAX_SPEED));
+		*mhz = umax(val, *mhz);
+	}
+}
+
+/* Look up the max frequency in DMI */
+static u64 cppc_get_dmi_max_khz(void)
+{
+	u16 mhz = 0;
+
+	dmi_walk(cppc_find_dmi_mhz, &mhz);
+
+	/*
+	 * Real stupid fallback value, just in case there is no
+	 * actual value set.
+	 */
+	mhz = mhz ? mhz : 1;
+
+	return KHZ_PER_MHZ * mhz;
+}
+
+/*
+ * If CPPC lowest_freq and nominal_freq registers are exposed then we can
+ * use them to convert perf to freq and vice versa. The conversion is
+ * extrapolated as an affine function passing by the 2 points:
+ *  - (Low perf, Low freq)
+ *  - (Nominal perf, Nominal freq)
+ */
+unsigned int cppc_perf_to_khz(struct cppc_perf_caps *caps, unsigned int perf)
+{
+	s64 retval, offset = 0;
+	static u64 max_khz;
+	u64 mul, div;
+
+	if (caps->lowest_freq && caps->nominal_freq) {
+		/* Avoid special case when nominal_freq is equal to lowest_freq */
+		if (caps->lowest_freq == caps->nominal_freq) {
+			mul = caps->nominal_freq;
+			div = caps->nominal_perf;
+		} else {
+			mul = caps->nominal_freq - caps->lowest_freq;
+			div = caps->nominal_perf - caps->lowest_perf;
+		}
+		mul *= KHZ_PER_MHZ;
+		offset = caps->nominal_freq * KHZ_PER_MHZ -
+			 div64_u64(caps->nominal_perf * mul, div);
+	} else {
+		if (!max_khz)
+			max_khz = cppc_get_dmi_max_khz();
+		mul = max_khz;
+		div = caps->highest_perf;
+	}
+
+	retval = offset + div64_u64(perf * mul, div);
+	if (retval >= 0)
+		return retval;
+	return 0;
+}
+EXPORT_SYMBOL_GPL(cppc_perf_to_khz);
+
+unsigned int cppc_khz_to_perf(struct cppc_perf_caps *caps, unsigned int freq)
+{
+	s64 retval, offset = 0;
+	static u64 max_khz;
+	u64 mul, div;
+
+	if (caps->lowest_freq && caps->nominal_freq) {
+		/* Avoid special case when nominal_freq is equal to lowest_freq */
+		if (caps->lowest_freq == caps->nominal_freq) {
+			mul = caps->nominal_perf;
+			div = caps->nominal_freq;
+		} else {
+			mul = caps->nominal_perf - caps->lowest_perf;
+			div = caps->nominal_freq - caps->lowest_freq;
+		}
+		/*
+		 * We don't need to convert to kHz for computing offset and can
+		 * directly use nominal_freq and lowest_freq as the div64_u64
+		 * will remove the frequency unit.
+		 */
+		offset = caps->nominal_perf -
+			 div64_u64(caps->nominal_freq * mul, div);
+		/* But we need it for computing the perf level. */
+		div *= KHZ_PER_MHZ;
+	} else {
+		if (!max_khz)
+			max_khz = cppc_get_dmi_max_khz();
+		mul = caps->highest_perf;
+		div = max_khz;
+	}
+
+	retval = offset + div64_u64(freq * mul, div);
+	if (retval >= 0)
+		return retval;
+	return 0;
+}
+EXPORT_SYMBOL_GPL(cppc_khz_to_perf);
diff --git a/drivers/acpi/custom_method.c b/drivers/acpi/custom_method.c
deleted file mode 100644
index b097ef209313..000000000000
--- a/drivers/acpi/custom_method.c
+++ /dev/null
@@ -1,103 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * custom_method.c - debugfs interface for customizing ACPI control method
- */
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/uaccess.h>
-#include <linux/debugfs.h>
-#include <linux/acpi.h>
-#include <linux/security.h>
-
-#include "internal.h"
-
-#define _COMPONENT		ACPI_SYSTEM_COMPONENT
-ACPI_MODULE_NAME("custom_method");
-MODULE_LICENSE("GPL");
-
-static struct dentry *cm_dentry;
-
-/* /sys/kernel/debug/acpi/custom_method */
-
-static ssize_t cm_write(struct file *file, const char __user * user_buf,
-			size_t count, loff_t *ppos)
-{
-	static char *buf;
-	static u32 max_size;
-	static u32 uncopied_bytes;
-
-	struct acpi_table_header table;
-	acpi_status status;
-	int ret;
-
-	ret = security_locked_down(LOCKDOWN_ACPI_TABLES);
-	if (ret)
-		return ret;
-
-	if (!(*ppos)) {
-		/* parse the table header to get the table length */
-		if (count <= sizeof(struct acpi_table_header))
-			return -EINVAL;
-		if (copy_from_user(&table, user_buf,
-				   sizeof(struct acpi_table_header)))
-			return -EFAULT;
-		uncopied_bytes = max_size = table.length;
-		buf = kzalloc(max_size, GFP_KERNEL);
-		if (!buf)
-			return -ENOMEM;
-	}
-
-	if (buf == NULL)
-		return -EINVAL;
-
-	if ((*ppos > max_size) ||
-	    (*ppos + count > max_size) ||
-	    (*ppos + count < count) ||
-	    (count > uncopied_bytes)) {
-		kfree(buf);
-		return -EINVAL;
-	}
-
-	if (copy_from_user(buf + (*ppos), user_buf, count)) {
-		kfree(buf);
-		buf = NULL;
-		return -EFAULT;
-	}
-
-	uncopied_bytes -= count;
-	*ppos += count;
-
-	if (!uncopied_bytes) {
-		status = acpi_install_method(buf);
-		kfree(buf);
-		buf = NULL;
-		if (ACPI_FAILURE(status))
-			return -EINVAL;
-		add_taint(TAINT_OVERRIDDEN_ACPI_TABLE, LOCKDEP_NOW_UNRELIABLE);
-	}
-
-	kfree(buf);
-	return count;
-}
-
-static const struct file_operations cm_fops = {
-	.write = cm_write,
-	.llseek = default_llseek,
-};
-
-static int __init acpi_custom_method_init(void)
-{
-	cm_dentry = debugfs_create_file("custom_method", S_IWUSR,
-					acpi_debugfs_dir, NULL, &cm_fops);
-	return 0;
-}
-
-static void __exit acpi_custom_method_exit(void)
-{
-	debugfs_remove(cm_dentry);
-}
-
-module_init(acpi_custom_method_init);
-module_exit(acpi_custom_method_exit);
diff --git a/drivers/acpi/debugfs.c b/drivers/acpi/debugfs.c
index d5ecea3715f8..074eb98d213e 100644
--- a/drivers/acpi/debugfs.c
+++ b/drivers/acpi/debugfs.c
@@ -10,9 +10,6 @@
 
 #include "internal.h"
 
-#define _COMPONENT		ACPI_SYSTEM_COMPONENT
-ACPI_MODULE_NAME("debugfs");
-
 struct dentry *acpi_debugfs_dir;
 EXPORT_SYMBOL_GPL(acpi_debugfs_dir);
 
diff --git a/drivers/acpi/device_pm.c b/drivers/acpi/device_pm.c
index b2263ec67b43..4e0583274b8f 100644
--- a/drivers/acpi/device_pm.c
+++ b/drivers/acpi/device_pm.c
@@ -10,6 +10,8 @@
  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  */
 
+#define pr_fmt(fmt) "PM: " fmt
+
 #include <linux/acpi.h>
 #include <linux/export.h>
 #include <linux/mutex.h>
@@ -18,11 +20,9 @@
 #include <linux/pm_runtime.h>
 #include <linux/suspend.h>
 
+#include "fan.h"
 #include "internal.h"
 
-#define _COMPONENT	ACPI_POWER_COMPONENT
-ACPI_MODULE_NAME("device_pm");
-
 /**
  * acpi_power_state_string - String representation of ACPI device power state.
  * @state: ACPI device power state to return the string representation of.
@@ -75,15 +75,17 @@ static int acpi_dev_pm_explicit_get(struct acpi_device *device, int *state)
 int acpi_device_get_power(struct acpi_device *device, int *state)
 {
 	int result = ACPI_STATE_UNKNOWN;
+	struct acpi_device *parent;
 	int error;
 
 	if (!device || !state)
 		return -EINVAL;
 
+	parent = acpi_dev_parent(device);
+
 	if (!device->flags.power_manageable) {
 		/* TBD: Non-recursive algorithm for walking up hierarchy. */
-		*state = device->parent ?
-			device->parent->power.state : ACPI_STATE_D0;
+		*state = parent ? parent->power.state : ACPI_STATE_D0;
 		goto out;
 	}
 
@@ -122,16 +124,16 @@ int acpi_device_get_power(struct acpi_device *device, int *state)
 	 * point, the fact that the device is in D0 implies that the parent has
 	 * to be in D0 too, except if ignore_parent is set.
 	 */
-	if (!device->power.flags.ignore_parent && device->parent
-	    && device->parent->power.state == ACPI_STATE_UNKNOWN
-	    && result == ACPI_STATE_D0)
-		device->parent->power.state = ACPI_STATE_D0;
+	if (!device->power.flags.ignore_parent && parent &&
+	    parent->power.state == ACPI_STATE_UNKNOWN &&
+	    result == ACPI_STATE_D0)
+		parent->power.state = ACPI_STATE_D0;
 
 	*state = result;
 
  out:
-	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Device [%s] power state is %s\n",
-			  device->pnp.bus_id, acpi_power_state_string(*state)));
+	acpi_handle_debug(device->handle, "Power state: %s\n",
+			  acpi_power_state_string(*state));
 
 	return 0;
 }
@@ -173,12 +175,8 @@ int acpi_device_set_power(struct acpi_device *device, int state)
 	/* Make sure this is a valid target state */
 
 	/* There is a special case for D0 addressed below. */
-	if (state > ACPI_STATE_D0 && state == device->power.state) {
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Device [%s] already in %s\n",
-				  device->pnp.bus_id,
-				  acpi_power_state_string(state)));
-		return 0;
-	}
+	if (state > ACPI_STATE_D0 && state == device->power.state)
+		goto no_change;
 
 	if (state == ACPI_STATE_D3_COLD) {
 		/*
@@ -186,22 +184,26 @@ int acpi_device_set_power(struct acpi_device *device, int state)
 		 * possibly drop references to the power resources in use.
 		 */
 		state = ACPI_STATE_D3_HOT;
-		/* If _PR3 is not available, use D3hot as the target state. */
+		/* If D3cold is not supported, use D3hot as the target state. */
 		if (!device->power.states[ACPI_STATE_D3_COLD].flags.valid)
 			target_state = state;
 	} else if (!device->power.states[state].flags.valid) {
-		dev_warn(&device->dev, "Power state %s not supported\n",
-			 acpi_power_state_string(state));
+		acpi_handle_debug(device->handle, "Power state %s not supported\n",
+				  acpi_power_state_string(state));
 		return -ENODEV;
 	}
 
-	if (!device->power.flags.ignore_parent &&
-	    device->parent && (state < device->parent->power.state)) {
-		dev_warn(&device->dev,
-			 "Cannot transition to power state %s for parent in %s\n",
-			 acpi_power_state_string(state),
-			 acpi_power_state_string(device->parent->power.state));
-		return -ENODEV;
+	if (!device->power.flags.ignore_parent) {
+		struct acpi_device *parent;
+
+		parent = acpi_dev_parent(device);
+		if (parent && state < parent->power.state) {
+			acpi_handle_debug(device->handle,
+					  "Cannot transition to %s for parent in %s\n",
+					  acpi_power_state_string(state),
+					  acpi_power_state_string(parent->power.state));
+			return -ENODEV;
+		}
 	}
 
 	/*
@@ -217,9 +219,10 @@ int acpi_device_set_power(struct acpi_device *device, int state)
 		 * (deeper) states to higher-power (shallower) states.
 		 */
 		if (state < device->power.state) {
-			dev_warn(&device->dev, "Cannot transition from %s to %s\n",
-				 acpi_power_state_string(device->power.state),
-				 acpi_power_state_string(state));
+			acpi_handle_debug(device->handle,
+					  "Cannot transition from %s to %s\n",
+					  acpi_power_state_string(device->power.state),
+					  acpi_power_state_string(state));
 			return -ENODEV;
 		}
 
@@ -249,7 +252,7 @@ int acpi_device_set_power(struct acpi_device *device, int state)
 
 			/* Nothing to do here if _PSC is not present. */
 			if (!device->power.flags.explicit_get)
-				return 0;
+				goto no_change;
 
 			/*
 			 * The power state of the device was set to D0 last
@@ -264,38 +267,40 @@ int acpi_device_set_power(struct acpi_device *device, int state)
 			 */
 			result = acpi_dev_pm_explicit_get(device, &psc);
 			if (result || psc == ACPI_STATE_D0)
-				return 0;
+				goto no_change;
 		}
 
 		result = acpi_dev_pm_explicit_set(device, ACPI_STATE_D0);
 	}
 
- end:
+end:
 	if (result) {
-		dev_warn(&device->dev, "Failed to change power state to %s\n",
-			 acpi_power_state_string(state));
+		acpi_handle_debug(device->handle,
+				  "Failed to change power state to %s\n",
+				  acpi_power_state_string(target_state));
 	} else {
 		device->power.state = target_state;
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-				  "Device [%s] transitioned to %s\n",
-				  device->pnp.bus_id,
-				  acpi_power_state_string(state)));
+		acpi_handle_debug(device->handle, "Power state changed to %s\n",
+				  acpi_power_state_string(target_state));
 	}
 
 	return result;
+
+no_change:
+	acpi_handle_debug(device->handle, "Already in %s\n",
+			  acpi_power_state_string(state));
+	return 0;
 }
 EXPORT_SYMBOL(acpi_device_set_power);
 
 int acpi_bus_set_power(acpi_handle handle, int state)
 {
-	struct acpi_device *device;
-	int result;
+	struct acpi_device *device = acpi_fetch_acpi_dev(handle);
 
-	result = acpi_bus_get_device(handle, &device);
-	if (result)
-		return result;
+	if (device)
+		return acpi_device_set_power(device, state);
 
-	return acpi_device_set_power(device, state);
+	return -ENODEV;
 }
 EXPORT_SYMBOL(acpi_bus_set_power);
 
@@ -370,6 +375,41 @@ int acpi_device_fix_up_power(struct acpi_device *device)
 }
 EXPORT_SYMBOL_GPL(acpi_device_fix_up_power);
 
+static int fix_up_power_if_applicable(struct acpi_device *adev, void *not_used)
+{
+	if (adev->status.present && adev->status.enabled)
+		acpi_device_fix_up_power(adev);
+
+	return 0;
+}
+
+/**
+ * acpi_device_fix_up_power_extended - Force device and its children into D0.
+ * @adev: Parent device object whose power state is to be fixed up.
+ *
+ * Call acpi_device_fix_up_power() for @adev and its children so long as they
+ * are reported as present and enabled.
+ */
+void acpi_device_fix_up_power_extended(struct acpi_device *adev)
+{
+	acpi_device_fix_up_power(adev);
+	acpi_dev_for_each_child(adev, fix_up_power_if_applicable, NULL);
+}
+EXPORT_SYMBOL_GPL(acpi_device_fix_up_power_extended);
+
+/**
+ * acpi_device_fix_up_power_children - Force a device's children into D0.
+ * @adev: Parent device object whose children's power state is to be fixed up.
+ *
+ * Call acpi_device_fix_up_power() for @adev's children so long as they
+ * are reported as present and enabled.
+ */
+void acpi_device_fix_up_power_children(struct acpi_device *adev)
+{
+	acpi_dev_for_each_child(adev, fix_up_power_if_applicable, NULL);
+}
+EXPORT_SYMBOL_GPL(acpi_device_fix_up_power_children);
+
 int acpi_device_update_power(struct acpi_device *device, int *state_p)
 {
 	int state;
@@ -413,24 +453,69 @@ EXPORT_SYMBOL_GPL(acpi_device_update_power);
 
 int acpi_bus_update_power(acpi_handle handle, int *state_p)
 {
-	struct acpi_device *device;
-	int result;
+	struct acpi_device *device = acpi_fetch_acpi_dev(handle);
+
+	if (device)
+		return acpi_device_update_power(device, state_p);
 
-	result = acpi_bus_get_device(handle, &device);
-	return result ? result : acpi_device_update_power(device, state_p);
+	return -ENODEV;
 }
 EXPORT_SYMBOL_GPL(acpi_bus_update_power);
 
 bool acpi_bus_power_manageable(acpi_handle handle)
 {
-	struct acpi_device *device;
-	int result;
+	struct acpi_device *device = acpi_fetch_acpi_dev(handle);
 
-	result = acpi_bus_get_device(handle, &device);
-	return result ? false : device->flags.power_manageable;
+	return device && device->flags.power_manageable;
 }
 EXPORT_SYMBOL(acpi_bus_power_manageable);
 
+static int acpi_power_up_if_adr_present(struct acpi_device *adev, void *not_used)
+{
+	if (!(adev->flags.power_manageable && adev->pnp.type.bus_address))
+		return 0;
+
+	acpi_handle_debug(adev->handle, "Power state: %s\n",
+			  acpi_power_state_string(adev->power.state));
+
+	if (adev->power.state == ACPI_STATE_D3_COLD)
+		return acpi_device_set_power(adev, ACPI_STATE_D0);
+
+	return 0;
+}
+
+/**
+ * acpi_dev_power_up_children_with_adr - Power up childres with valid _ADR
+ * @adev: Parent ACPI device object.
+ *
+ * Change the power states of the direct children of @adev that are in D3cold
+ * and hold valid _ADR objects to D0 in order to allow bus (e.g. PCI)
+ * enumeration code to access them.
+ */
+void acpi_dev_power_up_children_with_adr(struct acpi_device *adev)
+{
+	acpi_dev_for_each_child(adev, acpi_power_up_if_adr_present, NULL);
+}
+
+/**
+ * acpi_dev_power_state_for_wake - Deepest power state for wakeup signaling
+ * @adev: ACPI companion of the target device.
+ *
+ * Evaluate _S0W for @adev and return the value produced by it or return
+ * ACPI_STATE_UNKNOWN on errors (including _S0W not present).
+ */
+u8 acpi_dev_power_state_for_wake(struct acpi_device *adev)
+{
+	unsigned long long state;
+	acpi_status status;
+
+	status = acpi_evaluate_integer(adev->handle, "_S0W", NULL, &state);
+	if (ACPI_FAILURE(status))
+		return ACPI_STATE_UNKNOWN;
+
+	return state;
+}
+
 #ifdef CONFIG_PM
 static DEFINE_MUTEX(acpi_pm_notifier_lock);
 static DEFINE_MUTEX(acpi_pm_notifier_install_lock);
@@ -450,7 +535,7 @@ static void acpi_pm_notify_handler(acpi_handle handle, u32 val, void *not_used)
 
 	acpi_handle_debug(handle, "Wake notify\n");
 
-	adev = acpi_bus_get_acpi_device(handle);
+	adev = acpi_get_acpi_dev(handle);
 	if (!adev)
 		return;
 
@@ -468,7 +553,7 @@ static void acpi_pm_notify_handler(acpi_handle handle, u32 val, void *not_used)
 
 	mutex_unlock(&acpi_pm_notifier_lock);
 
-	acpi_bus_put_acpi_device(adev);
+	acpi_put_acpi_dev(adev);
 }
 
 /**
@@ -546,11 +631,9 @@ acpi_status acpi_remove_pm_notifier(struct acpi_device *adev)
 
 bool acpi_bus_can_wakeup(acpi_handle handle)
 {
-	struct acpi_device *device;
-	int result;
+	struct acpi_device *device = acpi_fetch_acpi_dev(handle);
 
-	result = acpi_bus_get_device(handle, &device);
-	return result ? false : device->wakeup.flags.valid;
+	return device && device->wakeup.flags.valid;
 }
 EXPORT_SYMBOL(acpi_bus_can_wakeup);
 
@@ -636,7 +719,22 @@ static int acpi_dev_pm_get_state(struct device *dev, struct acpi_device *adev,
 		d_min = ret;
 		wakeup = device_may_wakeup(dev) && adev->wakeup.flags.valid
 			&& adev->wakeup.sleep_state >= target_state;
+	} else if (device_may_wakeup(dev) && dev->power.wakeirq) {
+		/*
+		 * The ACPI subsystem doesn't manage the wake bit for IRQs
+		 * defined with ExclusiveAndWake and SharedAndWake. Instead we
+		 * expect them to be managed via the PM subsystem. Drivers
+		 * should call dev_pm_set_wake_irq to register an IRQ as a wake
+		 * source.
+		 *
+		 * If a device has a wake IRQ attached we need to check the
+		 * _S0W method to get the correct wake D-state. Otherwise we
+		 * end up putting the device into D3Cold which will more than
+		 * likely disable wake functionality.
+		 */
+		wakeup = true;
 	} else {
+		/* ACPI GPE is specified in _PRW. */
 		wakeup = adev->wakeup.flags.valid;
 	}
 
@@ -749,7 +847,7 @@ static void acpi_pm_notify_work_func(struct acpi_device_wakeup_context *context)
 static DEFINE_MUTEX(acpi_wakeup_lock);
 
 static int __acpi_device_wakeup_enable(struct acpi_device *adev,
-				       u32 target_state, int max_count)
+				       u32 target_state)
 {
 	struct acpi_device_wakeup *wakeup = &adev->wakeup;
 	acpi_status status;
@@ -757,15 +855,26 @@ static int __acpi_device_wakeup_enable(struct acpi_device *adev,
 
 	mutex_lock(&acpi_wakeup_lock);
 
-	if (wakeup->enable_count >= max_count)
-		goto out;
-
+	/*
+	 * If the device wakeup power is already enabled, disable it and enable
+	 * it again in case it depends on the configuration of subordinate
+	 * devices and the conditions have changed since it was enabled last
+	 * time.
+	 */
 	if (wakeup->enable_count > 0)
-		goto inc;
+		acpi_disable_wakeup_device_power(adev);
 
 	error = acpi_enable_wakeup_device_power(adev, target_state);
-	if (error)
+	if (error) {
+		if (wakeup->enable_count > 0) {
+			acpi_disable_gpe(wakeup->gpe_device, wakeup->gpe_number);
+			wakeup->enable_count = 0;
+		}
 		goto out;
+	}
+
+	if (wakeup->enable_count > 0)
+		goto inc;
 
 	status = acpi_enable_gpe(wakeup->gpe_device, wakeup->gpe_number);
 	if (ACPI_FAILURE(status)) {
@@ -778,7 +887,10 @@ static int __acpi_device_wakeup_enable(struct acpi_device *adev,
 			  (unsigned int)wakeup->gpe_number);
 
 inc:
-	wakeup->enable_count++;
+	if (wakeup->enable_count < INT_MAX)
+		wakeup->enable_count++;
+	else
+		acpi_handle_info(adev->handle, "Wakeup enable count out of bounds!\n");
 
 out:
 	mutex_unlock(&acpi_wakeup_lock);
@@ -799,7 +911,7 @@ out:
  */
 static int acpi_device_wakeup_enable(struct acpi_device *adev, u32 target_state)
 {
-	return __acpi_device_wakeup_enable(adev, target_state, 1);
+	return __acpi_device_wakeup_enable(adev, target_state);
 }
 
 /**
@@ -829,8 +941,12 @@ out:
 	mutex_unlock(&acpi_wakeup_lock);
 }
 
-static int __acpi_pm_set_device_wakeup(struct device *dev, bool enable,
-				       int max_count)
+/**
+ * acpi_pm_set_device_wakeup - Enable/disable remote wakeup for given device.
+ * @dev: Device to enable/disable to generate wakeup events.
+ * @enable: Whether to enable or disable the wakeup functionality.
+ */
+int acpi_pm_set_device_wakeup(struct device *dev, bool enable)
 {
 	struct acpi_device *adev;
 	int error;
@@ -850,37 +966,15 @@ static int __acpi_pm_set_device_wakeup(struct device *dev, bool enable,
 		return 0;
 	}
 
-	error = __acpi_device_wakeup_enable(adev, acpi_target_system_state(),
-					    max_count);
+	error = __acpi_device_wakeup_enable(adev, acpi_target_system_state());
 	if (!error)
 		dev_dbg(dev, "Wakeup enabled by ACPI\n");
 
 	return error;
 }
-
-/**
- * acpi_pm_set_device_wakeup - Enable/disable remote wakeup for given device.
- * @dev: Device to enable/disable to generate wakeup events.
- * @enable: Whether to enable or disable the wakeup functionality.
- */
-int acpi_pm_set_device_wakeup(struct device *dev, bool enable)
-{
-	return __acpi_pm_set_device_wakeup(dev, enable, 1);
-}
 EXPORT_SYMBOL_GPL(acpi_pm_set_device_wakeup);
 
 /**
- * acpi_pm_set_bridge_wakeup - Enable/disable remote wakeup for given bridge.
- * @dev: Bridge device to enable/disable to generate wakeup events.
- * @enable: Whether to enable or disable the wakeup functionality.
- */
-int acpi_pm_set_bridge_wakeup(struct device *dev, bool enable)
-{
-	return __acpi_pm_set_device_wakeup(dev, enable, INT_MAX);
-}
-EXPORT_SYMBOL_GPL(acpi_pm_set_bridge_wakeup);
-
-/**
  * acpi_dev_pm_low_power - Put ACPI device into a low-power state.
  * @dev: Device to put into a low-power state.
  * @adev: ACPI device node corresponding to @dev.
@@ -974,6 +1068,7 @@ EXPORT_SYMBOL_GPL(acpi_dev_resume);
 int acpi_subsys_runtime_suspend(struct device *dev)
 {
 	int ret = pm_generic_runtime_suspend(dev);
+
 	return ret ? ret : acpi_dev_suspend(dev, true);
 }
 EXPORT_SYMBOL_GPL(acpi_subsys_runtime_suspend);
@@ -988,6 +1083,7 @@ EXPORT_SYMBOL_GPL(acpi_subsys_runtime_suspend);
 int acpi_subsys_runtime_resume(struct device *dev)
 {
 	int ret = acpi_dev_resume(dev);
+
 	return ret ? ret : pm_generic_runtime_resume(dev);
 }
 EXPORT_SYMBOL_GPL(acpi_subsys_runtime_resume);
@@ -1023,6 +1119,8 @@ int acpi_subsys_prepare(struct device *dev)
 {
 	struct acpi_device *adev = ACPI_COMPANION(dev);
 
+	dev_pm_set_strict_midlayer(dev, true);
+
 	if (dev->driver && dev->driver->pm && dev->driver->pm->prepare) {
 		int ret = dev->driver->pm->prepare(dev);
 
@@ -1051,6 +1149,8 @@ void acpi_subsys_complete(struct device *dev)
 	 */
 	if (pm_runtime_suspended(dev) && pm_resume_via_firmware())
 		pm_request_resume(dev);
+
+	dev_pm_set_strict_midlayer(dev, false);
 }
 EXPORT_SYMBOL_GPL(acpi_subsys_complete);
 
@@ -1065,7 +1165,7 @@ EXPORT_SYMBOL_GPL(acpi_subsys_complete);
  */
 int acpi_subsys_suspend(struct device *dev)
 {
-	if (!dev_pm_test_driver_flags(dev, DPM_FLAG_SMART_SUSPEND) ||
+	if (!dev_pm_smart_suspend(dev) ||
 	    acpi_dev_needs_resume(dev, ACPI_COMPANION(dev)))
 		pm_runtime_resume(dev);
 
@@ -1084,7 +1184,7 @@ int acpi_subsys_suspend_late(struct device *dev)
 {
 	int ret;
 
-	if (dev_pm_smart_suspend_and_suspended(dev))
+	if (dev_pm_skip_suspend(dev))
 		return 0;
 
 	ret = pm_generic_suspend_late(dev);
@@ -1100,10 +1200,8 @@ int acpi_subsys_suspend_noirq(struct device *dev)
 {
 	int ret;
 
-	if (dev_pm_smart_suspend_and_suspended(dev)) {
-		dev->power.may_skip_resume = true;
+	if (dev_pm_skip_suspend(dev))
 		return 0;
-	}
 
 	ret = pm_generic_suspend_noirq(dev);
 	if (ret)
@@ -1116,8 +1214,8 @@ int acpi_subsys_suspend_noirq(struct device *dev)
 	 * acpi_subsys_complete() to take care of fixing up the device's state
 	 * anyway, if need be.
 	 */
-	dev->power.may_skip_resume = device_may_wakeup(dev) ||
-					!device_can_wakeup(dev);
+	if (device_can_wakeup(dev) && !device_may_wakeup(dev))
+		dev->power.may_skip_resume = false;
 
 	return 0;
 }
@@ -1129,17 +1227,9 @@ EXPORT_SYMBOL_GPL(acpi_subsys_suspend_noirq);
  */
 static int acpi_subsys_resume_noirq(struct device *dev)
 {
-	if (dev_pm_may_skip_resume(dev))
+	if (dev_pm_skip_resume(dev))
 		return 0;
 
-	/*
-	 * Devices with DPM_FLAG_SMART_SUSPEND may be left in runtime suspend
-	 * during system suspend, so update their runtime PM status to "active"
-	 * as they will be put into D0 going forward.
-	 */
-	if (dev_pm_smart_suspend_and_suspended(dev))
-		pm_runtime_set_active(dev);
-
 	return pm_generic_resume_noirq(dev);
 }
 
@@ -1149,15 +1239,49 @@ static int acpi_subsys_resume_noirq(struct device *dev)
  *
  * Use ACPI to put the given device into the full-power state and carry out the
  * generic early resume procedure for it during system transition into the
- * working state.
+ * working state, but only do that if device either defines early resume
+ * handler, or does not define power operations at all. Otherwise powering up
+ * of the device is postponed to the normal resume phase.
  */
 static int acpi_subsys_resume_early(struct device *dev)
 {
-	int ret = acpi_dev_resume(dev);
+	const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
+	int ret;
+
+	if (dev_pm_skip_resume(dev))
+		return 0;
+
+	if (pm && !pm->resume_early) {
+		dev_dbg(dev, "postponing D0 transition to normal resume stage\n");
+		return 0;
+	}
+
+	ret = acpi_dev_resume(dev);
 	return ret ? ret : pm_generic_resume_early(dev);
 }
 
 /**
+ * acpi_subsys_resume - Resume device using ACPI.
+ * @dev: Device to Resume.
+ *
+ * Use ACPI to put the given device into the full-power state if it has not been
+ * powered up during early resume phase, and carry out the generic resume
+ * procedure for it during system transition into the working state.
+ */
+static int acpi_subsys_resume(struct device *dev)
+{
+	const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
+	int ret = 0;
+
+	if (!dev_pm_skip_resume(dev) && pm && !pm->resume_early) {
+		dev_dbg(dev, "executing postponed D0 transition\n");
+		ret = acpi_dev_resume(dev);
+	}
+
+	return ret ? ret : pm_generic_resume(dev);
+}
+
+/**
  * acpi_subsys_freeze - Run the device driver's freeze callback.
  * @dev: Device to handle.
  */
@@ -1184,6 +1308,7 @@ EXPORT_SYMBOL_GPL(acpi_subsys_freeze);
 int acpi_subsys_restore_early(struct device *dev)
 {
 	int ret = acpi_dev_resume(dev);
+
 	return ret ? ret : pm_generic_restore_early(dev);
 }
 EXPORT_SYMBOL_GPL(acpi_subsys_restore_early);
@@ -1199,7 +1324,7 @@ EXPORT_SYMBOL_GPL(acpi_subsys_restore_early);
  */
 int acpi_subsys_poweroff(struct device *dev)
 {
-	if (!dev_pm_test_driver_flags(dev, DPM_FLAG_SMART_SUSPEND) ||
+	if (!dev_pm_smart_suspend(dev) ||
 	    acpi_dev_needs_resume(dev, ACPI_COMPANION(dev)))
 		pm_runtime_resume(dev);
 
@@ -1218,7 +1343,7 @@ static int acpi_subsys_poweroff_late(struct device *dev)
 {
 	int ret;
 
-	if (dev_pm_smart_suspend_and_suspended(dev))
+	if (dev_pm_skip_suspend(dev))
 		return 0;
 
 	ret = pm_generic_poweroff_late(dev);
@@ -1234,13 +1359,15 @@ static int acpi_subsys_poweroff_late(struct device *dev)
  */
 static int acpi_subsys_poweroff_noirq(struct device *dev)
 {
-	if (dev_pm_smart_suspend_and_suspended(dev))
+	if (dev_pm_skip_suspend(dev))
 		return 0;
 
 	return pm_generic_poweroff_noirq(dev);
 }
 #endif /* CONFIG_PM_SLEEP */
 
+static void acpi_dev_pm_detach(struct device *dev, bool power_off);
+
 static struct dev_pm_domain acpi_general_pm_domain = {
 	.ops = {
 		.runtime_suspend = acpi_subsys_runtime_suspend,
@@ -1249,6 +1376,7 @@ static struct dev_pm_domain acpi_general_pm_domain = {
 		.prepare = acpi_subsys_prepare,
 		.complete = acpi_subsys_complete,
 		.suspend = acpi_subsys_suspend,
+		.resume = acpi_subsys_resume,
 		.suspend_late = acpi_subsys_suspend_late,
 		.suspend_noirq = acpi_subsys_suspend_noirq,
 		.resume_noirq = acpi_subsys_resume_noirq,
@@ -1260,6 +1388,7 @@ static struct dev_pm_domain acpi_general_pm_domain = {
 		.restore_early = acpi_subsys_restore_early,
 #endif
 	},
+	.detach = acpi_dev_pm_detach,
 };
 
 /**
@@ -1320,9 +1449,7 @@ int acpi_dev_pm_attach(struct device *dev, bool power_on)
 	 * with the generic ACPI PM domain.
 	 */
 	static const struct acpi_device_id special_pm_ids[] = {
-		{"PNP0C0B", }, /* Generic ACPI fan */
-		{"INT3404", }, /* Fan */
-		{"INTC1044", }, /* Fan for Tiger Lake generation */
+		ACPI_FAN_DEVICE_IDS,
 		{}
 	};
 	struct acpi_device *adev = ACPI_COMPANION(dev);
@@ -1345,8 +1472,65 @@ int acpi_dev_pm_attach(struct device *dev, bool power_on)
 		acpi_device_wakeup_disable(adev);
 	}
 
-	dev->pm_domain->detach = acpi_dev_pm_detach;
 	return 1;
 }
 EXPORT_SYMBOL_GPL(acpi_dev_pm_attach);
+
+/**
+ * acpi_storage_d3 - Check if D3 should be used in the suspend path
+ * @dev: Device to check
+ *
+ * Return %true if the platform firmware wants @dev to be programmed
+ * into D3hot or D3cold (if supported) in the suspend path, or %false
+ * when there is no specific preference. On some platforms, if this
+ * hint is ignored, @dev may remain unresponsive after suspending the
+ * platform as a whole.
+ *
+ * Although the property has storage in the name it actually is
+ * applied to the PCIe slot and plugging in a non-storage device the
+ * same platform restrictions will likely apply.
+ */
+bool acpi_storage_d3(struct device *dev)
+{
+	struct acpi_device *adev = ACPI_COMPANION(dev);
+	u8 val;
+
+	if (force_storage_d3())
+		return true;
+
+	if (!adev)
+		return false;
+	if (fwnode_property_read_u8(acpi_fwnode_handle(adev), "StorageD3Enable",
+			&val))
+		return false;
+	return val == 1;
+}
+EXPORT_SYMBOL_GPL(acpi_storage_d3);
+
+/**
+ * acpi_dev_state_d0 - Tell if the device is in D0 power state
+ * @dev: Physical device the ACPI power state of which to check
+ *
+ * On a system without ACPI, return true. On a system with ACPI, return true if
+ * the current ACPI power state of the device is D0, or false otherwise.
+ *
+ * Note that the power state of a device is not well-defined after it has been
+ * passed to acpi_device_set_power() and before that function returns, so it is
+ * not valid to ask for the ACPI power state of the device in that time frame.
+ *
+ * This function is intended to be used in a driver's probe or remove
+ * function. See Documentation/firmware-guide/acpi/non-d0-probe.rst for
+ * more information.
+ */
+bool acpi_dev_state_d0(struct device *dev)
+{
+	struct acpi_device *adev = ACPI_COMPANION(dev);
+
+	if (!adev)
+		return true;
+
+	return adev->power.state == ACPI_STATE_D0;
+}
+EXPORT_SYMBOL_GPL(acpi_dev_state_d0);
+
 #endif /* CONFIG_PM */
diff --git a/drivers/acpi/device_sysfs.c b/drivers/acpi/device_sysfs.c
index 96869f1538b9..cd199fbe4dc9 100644
--- a/drivers/acpi/device_sysfs.c
+++ b/drivers/acpi/device_sysfs.c
@@ -53,6 +53,7 @@ static struct attribute *acpi_data_node_default_attrs[] = {
 	&data_node_path.attr,
 	NULL
 };
+ATTRIBUTE_GROUPS(acpi_data_node_default);
 
 #define to_data_node(k) container_of(k, struct acpi_data_node, kobj)
 #define to_attr(a) container_of(a, struct acpi_data_node_attr, attr)
@@ -73,12 +74,13 @@ static const struct sysfs_ops acpi_data_node_sysfs_ops = {
 static void acpi_data_node_release(struct kobject *kobj)
 {
 	struct acpi_data_node *dn = to_data_node(kobj);
+
 	complete(&dn->kobj_done);
 }
 
-static struct kobj_type acpi_data_node_ktype = {
+static const struct kobj_type acpi_data_node_ktype = {
 	.sysfs_ops = &acpi_data_node_sysfs_ops,
-	.default_attrs = acpi_data_node_default_attrs,
+	.default_groups = acpi_data_node_default_groups,
 	.release = acpi_data_node_release,
 };
 
@@ -130,8 +132,8 @@ static void acpi_hide_nondev_subnodes(struct acpi_device_data *data)
  * Return: 0: no _HID and no _CID
  *         -EINVAL: output error
  *         -ENOMEM: output is truncated
-*/
-static int create_pnp_modalias(struct acpi_device *acpi_dev, char *modalias,
+ */
+static int create_pnp_modalias(const struct acpi_device *acpi_dev, char *modalias,
 			       int size)
 {
 	int len;
@@ -156,8 +158,8 @@ static int create_pnp_modalias(struct acpi_device *acpi_dev, char *modalias,
 		return 0;
 
 	len = snprintf(modalias, size, "acpi:");
-	if (len <= 0)
-		return len;
+	if (len >= size)
+		return -ENOMEM;
 
 	size -= len;
 
@@ -166,8 +168,6 @@ static int create_pnp_modalias(struct acpi_device *acpi_dev, char *modalias,
 			continue;
 
 		count = snprintf(&modalias[len], size, "%s:", id->id);
-		if (count < 0)
-			return -EINVAL;
 
 		if (count >= size)
 			return -ENOMEM;
@@ -175,7 +175,7 @@ static int create_pnp_modalias(struct acpi_device *acpi_dev, char *modalias,
 		len += count;
 		size -= count;
 	}
-	modalias[len] = '\0';
+
 	return len;
 }
 
@@ -189,7 +189,7 @@ static int create_pnp_modalias(struct acpi_device *acpi_dev, char *modalias,
  * only be called for devices having ACPI_DT_NAMESPACE_HID in their list of
  * ACPI/PNP IDs.
  */
-static int create_of_modalias(struct acpi_device *acpi_dev, char *modalias,
+static int create_of_modalias(const struct acpi_device *acpi_dev, char *modalias,
 			      int size)
 {
 	struct acpi_buffer buf = { ACPI_ALLOCATE_BUFFER };
@@ -210,8 +210,10 @@ static int create_of_modalias(struct acpi_device *acpi_dev, char *modalias,
 	len = snprintf(modalias, size, "of:N%sT", (char *)buf.pointer);
 	ACPI_FREE(buf.pointer);
 
-	if (len <= 0)
-		return len;
+	if (len >= size)
+		return -ENOMEM;
+
+	size -= len;
 
 	of_compatible = acpi_dev->data.of_compatible;
 	if (of_compatible->type == ACPI_TYPE_PACKAGE) {
@@ -224,8 +226,6 @@ static int create_of_modalias(struct acpi_device *acpi_dev, char *modalias,
 	for (i = 0; i < nval; i++, obj++) {
 		count = snprintf(&modalias[len], size, "C%s",
 				 obj->string.pointer);
-		if (count < 0)
-			return -EINVAL;
 
 		if (count >= size)
 			return -ENOMEM;
@@ -233,11 +233,11 @@ static int create_of_modalias(struct acpi_device *acpi_dev, char *modalias,
 		len += count;
 		size -= count;
 	}
-	modalias[len] = '\0';
+
 	return len;
 }
 
-int __acpi_device_uevent_modalias(struct acpi_device *adev,
+int __acpi_device_uevent_modalias(const struct acpi_device *adev,
 				  struct kobj_uevent_env *env)
 {
 	int len;
@@ -251,20 +251,12 @@ int __acpi_device_uevent_modalias(struct acpi_device *adev,
 	if (add_uevent_var(env, "MODALIAS="))
 		return -ENOMEM;
 
-	len = create_pnp_modalias(adev, &env->buf[env->buflen - 1],
-				  sizeof(env->buf) - env->buflen);
-	if (len < 0)
-		return len;
-
-	env->buflen += len;
-	if (!adev->data.of_compatible)
-		return 0;
-
-	if (len > 0 && add_uevent_var(env, "MODALIAS="))
-		return -ENOMEM;
-
-	len = create_of_modalias(adev, &env->buf[env->buflen - 1],
-				 sizeof(env->buf) - env->buflen);
+	if (adev->data.of_compatible)
+		len = create_of_modalias(adev, &env->buf[env->buflen - 1],
+					 sizeof(env->buf) - env->buflen);
+	else
+		len = create_pnp_modalias(adev, &env->buf[env->buflen - 1],
+					  sizeof(env->buf) - env->buflen);
 	if (len < 0)
 		return len;
 
@@ -275,19 +267,21 @@ int __acpi_device_uevent_modalias(struct acpi_device *adev,
 
 /**
  * acpi_device_uevent_modalias - uevent modalias for ACPI-enumerated devices.
+ * @dev: Struct device to get ACPI device node.
+ * @env: Environment variables of the kobject uevent.
  *
  * Create the uevent modalias field for ACPI-enumerated devices.
  *
  * Because other buses do not support ACPI HIDs & CIDs, e.g. for a device with
  * hid:IBM0001 and cid:ACPI0001 you get: "acpi:IBM0001:ACPI0001".
  */
-int acpi_device_uevent_modalias(struct device *dev, struct kobj_uevent_env *env)
+int acpi_device_uevent_modalias(const struct device *dev, struct kobj_uevent_env *env)
 {
 	return __acpi_device_uevent_modalias(acpi_companion_match(dev), env);
 }
 EXPORT_SYMBOL_GPL(acpi_device_uevent_modalias);
 
-static int __acpi_device_modalias(struct acpi_device *adev, char *buf, int size)
+static int __acpi_device_modalias(const struct acpi_device *adev, char *buf, int size)
 {
 	int len, count;
 
@@ -320,6 +314,9 @@ static int __acpi_device_modalias(struct acpi_device *adev, char *buf, int size)
 
 /**
  * acpi_device_modalias - modalias sysfs attribute for ACPI-enumerated devices.
+ * @dev: Struct device to get ACPI device node.
+ * @buf: The buffer to save pnp_modalias and of_modalias.
+ * @size: Size of buffer.
  *
  * Create the modalias sysfs attribute for ACPI-enumerated devices.
  *
@@ -333,11 +330,11 @@ int acpi_device_modalias(struct device *dev, char *buf, int size)
 EXPORT_SYMBOL_GPL(acpi_device_modalias);
 
 static ssize_t
-acpi_device_modalias_show(struct device *dev, struct device_attribute *attr, char *buf)
+modalias_show(struct device *dev, struct device_attribute *attr, char *buf)
 {
 	return __acpi_device_modalias(to_acpi_device(dev), buf, 1024);
 }
-static DEVICE_ATTR(modalias, 0444, acpi_device_modalias_show, NULL);
+static DEVICE_ATTR_RO(modalias);
 
 static ssize_t real_power_state_show(struct device *dev,
 				     struct device_attribute *attr, char *buf)
@@ -366,8 +363,8 @@ static ssize_t power_state_show(struct device *dev,
 static DEVICE_ATTR_RO(power_state);
 
 static ssize_t
-acpi_eject_store(struct device *d, struct device_attribute *attr,
-		const char *buf, size_t count)
+eject_store(struct device *d, struct device_attribute *attr,
+	    const char *buf, size_t count)
 {
 	struct acpi_device *acpi_device = to_acpi_device(d);
 	acpi_object_type not_used;
@@ -377,46 +374,46 @@ acpi_eject_store(struct device *d, struct device_attribute *attr,
 		return -EINVAL;
 
 	if ((!acpi_device->handler || !acpi_device->handler->hotplug.enabled)
-	    && !acpi_device->driver)
+	    && !d->driver)
 		return -ENODEV;
 
 	status = acpi_get_type(acpi_device->handle, &not_used);
 	if (ACPI_FAILURE(status) || !acpi_device->flags.ejectable)
 		return -ENODEV;
 
-	get_device(&acpi_device->dev);
+	acpi_dev_get(acpi_device);
 	status = acpi_hotplug_schedule(acpi_device, ACPI_OST_EC_OSPM_EJECT);
 	if (ACPI_SUCCESS(status))
 		return count;
 
-	put_device(&acpi_device->dev);
+	acpi_dev_put(acpi_device);
 	acpi_evaluate_ost(acpi_device->handle, ACPI_OST_EC_OSPM_EJECT,
 			  ACPI_OST_SC_NON_SPECIFIC_FAILURE, NULL);
 	return status == AE_NO_MEMORY ? -ENOMEM : -EAGAIN;
 }
 
-static DEVICE_ATTR(eject, 0200, NULL, acpi_eject_store);
+static DEVICE_ATTR_WO(eject);
 
 static ssize_t
-acpi_device_hid_show(struct device *dev, struct device_attribute *attr, char *buf)
+hid_show(struct device *dev, struct device_attribute *attr, char *buf)
 {
 	struct acpi_device *acpi_dev = to_acpi_device(dev);
 
 	return sprintf(buf, "%s\n", acpi_device_hid(acpi_dev));
 }
-static DEVICE_ATTR(hid, 0444, acpi_device_hid_show, NULL);
+static DEVICE_ATTR_RO(hid);
 
-static ssize_t acpi_device_uid_show(struct device *dev,
-				    struct device_attribute *attr, char *buf)
+static ssize_t uid_show(struct device *dev,
+			struct device_attribute *attr, char *buf)
 {
 	struct acpi_device *acpi_dev = to_acpi_device(dev);
 
-	return sprintf(buf, "%s\n", acpi_dev->pnp.unique_id);
+	return sprintf(buf, "%s\n", acpi_device_uid(acpi_dev));
 }
-static DEVICE_ATTR(uid, 0444, acpi_device_uid_show, NULL);
+static DEVICE_ATTR_RO(uid);
 
-static ssize_t acpi_device_adr_show(struct device *dev,
-				    struct device_attribute *attr, char *buf)
+static ssize_t adr_show(struct device *dev,
+			struct device_attribute *attr, char *buf)
 {
 	struct acpi_device *acpi_dev = to_acpi_device(dev);
 
@@ -425,46 +422,58 @@ static ssize_t acpi_device_adr_show(struct device *dev,
 	else
 		return sprintf(buf, "0x%08llx\n", acpi_dev->pnp.bus_address);
 }
-static DEVICE_ATTR(adr, 0444, acpi_device_adr_show, NULL);
+static DEVICE_ATTR_RO(adr);
 
-static ssize_t acpi_device_path_show(struct device *dev,
-				     struct device_attribute *attr, char *buf)
+static ssize_t path_show(struct device *dev,
+			 struct device_attribute *attr, char *buf)
 {
 	struct acpi_device *acpi_dev = to_acpi_device(dev);
 
 	return acpi_object_path(acpi_dev->handle, buf);
 }
-static DEVICE_ATTR(path, 0444, acpi_device_path_show, NULL);
+static DEVICE_ATTR_RO(path);
 
 /* sysfs file that shows description text from the ACPI _STR method */
 static ssize_t description_show(struct device *dev,
 				struct device_attribute *attr,
-				char *buf) {
+				char *buf)
+{
 	struct acpi_device *acpi_dev = to_acpi_device(dev);
+	struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL};
+	union acpi_object *str_obj;
+	acpi_status status;
 	int result;
 
-	if (acpi_dev->pnp.str_obj == NULL)
-		return 0;
+	status = acpi_evaluate_object_typed(acpi_dev->handle, "_STR",
+					    NULL, &buffer,
+					    ACPI_TYPE_BUFFER);
+	if (ACPI_FAILURE(status))
+		return -EIO;
+
+	str_obj = buffer.pointer;
 
 	/*
 	 * The _STR object contains a Unicode identifier for a device.
 	 * We need to convert to utf-8 so it can be displayed.
 	 */
 	result = utf16s_to_utf8s(
-		(wchar_t *)acpi_dev->pnp.str_obj->buffer.pointer,
-		acpi_dev->pnp.str_obj->buffer.length,
+		(wchar_t *)str_obj->buffer.pointer,
+		str_obj->buffer.length,
 		UTF16_LITTLE_ENDIAN, buf,
-		PAGE_SIZE);
+		PAGE_SIZE - 1);
 
 	buf[result++] = '\n';
 
+	ACPI_FREE(str_obj);
+
 	return result;
 }
 static DEVICE_ATTR_RO(description);
 
 static ssize_t
-acpi_device_sun_show(struct device *dev, struct device_attribute *attr,
-		     char *buf) {
+sun_show(struct device *dev, struct device_attribute *attr,
+	 char *buf)
+{
 	struct acpi_device *acpi_dev = to_acpi_device(dev);
 	acpi_status status;
 	unsigned long long sun;
@@ -475,11 +484,12 @@ acpi_device_sun_show(struct device *dev, struct device_attribute *attr,
 
 	return sprintf(buf, "%llu\n", sun);
 }
-static DEVICE_ATTR(sun, 0444, acpi_device_sun_show, NULL);
+static DEVICE_ATTR_RO(sun);
 
 static ssize_t
-acpi_device_hrv_show(struct device *dev, struct device_attribute *attr,
-		     char *buf) {
+hrv_show(struct device *dev, struct device_attribute *attr,
+	 char *buf)
+{
 	struct acpi_device *acpi_dev = to_acpi_device(dev);
 	acpi_status status;
 	unsigned long long hrv;
@@ -490,10 +500,11 @@ acpi_device_hrv_show(struct device *dev, struct device_attribute *attr,
 
 	return sprintf(buf, "%llu\n", hrv);
 }
-static DEVICE_ATTR(hrv, 0444, acpi_device_hrv_show, NULL);
+static DEVICE_ATTR_RO(hrv);
 
 static ssize_t status_show(struct device *dev, struct device_attribute *attr,
-				char *buf) {
+				char *buf)
+{
 	struct acpi_device *acpi_dev = to_acpi_device(dev);
 	acpi_status status;
 	unsigned long long sta;
@@ -506,96 +517,97 @@ static ssize_t status_show(struct device *dev, struct device_attribute *attr,
 }
 static DEVICE_ATTR_RO(status);
 
-/**
- * acpi_device_setup_files - Create sysfs attributes of an ACPI device.
- * @dev: ACPI device object.
- */
-int acpi_device_setup_files(struct acpi_device *dev)
-{
-	struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL};
-	acpi_status status;
-	int result = 0;
+static struct attribute *acpi_attrs[] = {
+	&dev_attr_path.attr,
+	&dev_attr_hid.attr,
+	&dev_attr_modalias.attr,
+	&dev_attr_description.attr,
+	&dev_attr_adr.attr,
+	&dev_attr_uid.attr,
+	&dev_attr_sun.attr,
+	&dev_attr_hrv.attr,
+	&dev_attr_status.attr,
+	&dev_attr_eject.attr,
+	&dev_attr_power_state.attr,
+	&dev_attr_real_power_state.attr,
+	NULL
+};
 
+static bool acpi_show_attr(struct acpi_device *dev, const struct device_attribute *attr)
+{
 	/*
 	 * Devices gotten from FADT don't have a "path" attribute
 	 */
-	if (dev->handle) {
-		result = device_create_file(&dev->dev, &dev_attr_path);
-		if (result)
-			goto end;
-	}
+	if (attr == &dev_attr_path)
+		return dev->handle;
 
-	if (!list_empty(&dev->pnp.ids)) {
-		result = device_create_file(&dev->dev, &dev_attr_hid);
-		if (result)
-			goto end;
+	if (attr == &dev_attr_hid || attr == &dev_attr_modalias)
+		return !list_empty(&dev->pnp.ids);
 
-		result = device_create_file(&dev->dev, &dev_attr_modalias);
-		if (result)
-			goto end;
-	}
+	if (attr == &dev_attr_description)
+		return acpi_has_method(dev->handle, "_STR");
 
-	/*
-	 * If device has _STR, 'description' file is created
-	 */
-	if (acpi_has_method(dev->handle, "_STR")) {
-		status = acpi_evaluate_object(dev->handle, "_STR",
-					NULL, &buffer);
-		if (ACPI_FAILURE(status))
-			buffer.pointer = NULL;
-		dev->pnp.str_obj = buffer.pointer;
-		result = device_create_file(&dev->dev, &dev_attr_description);
-		if (result)
-			goto end;
-	}
+	if (attr == &dev_attr_adr)
+		return dev->pnp.type.bus_address;
 
-	if (dev->pnp.type.bus_address)
-		result = device_create_file(&dev->dev, &dev_attr_adr);
-	if (dev->pnp.unique_id)
-		result = device_create_file(&dev->dev, &dev_attr_uid);
+	if (attr == &dev_attr_uid)
+		return acpi_device_uid(dev);
 
-	if (acpi_has_method(dev->handle, "_SUN")) {
-		result = device_create_file(&dev->dev, &dev_attr_sun);
-		if (result)
-			goto end;
-	}
+	if (attr == &dev_attr_sun)
+		return acpi_has_method(dev->handle, "_SUN");
 
-	if (acpi_has_method(dev->handle, "_HRV")) {
-		result = device_create_file(&dev->dev, &dev_attr_hrv);
-		if (result)
-			goto end;
-	}
+	if (attr == &dev_attr_hrv)
+		return acpi_has_method(dev->handle, "_HRV");
 
-	if (acpi_has_method(dev->handle, "_STA")) {
-		result = device_create_file(&dev->dev, &dev_attr_status);
-		if (result)
-			goto end;
-	}
+	if (attr == &dev_attr_status)
+		return acpi_has_method(dev->handle, "_STA");
 
 	/*
 	 * If device has _EJ0, 'eject' file is created that is used to trigger
 	 * hot-removal function from userland.
 	 */
-	if (acpi_has_method(dev->handle, "_EJ0")) {
-		result = device_create_file(&dev->dev, &dev_attr_eject);
-		if (result)
-			return result;
-	}
+	if (attr == &dev_attr_eject)
+		return acpi_has_method(dev->handle, "_EJ0");
 
-	if (dev->flags.power_manageable) {
-		result = device_create_file(&dev->dev, &dev_attr_power_state);
-		if (result)
-			return result;
+	if (attr == &dev_attr_power_state)
+		return dev->flags.power_manageable;
 
-		if (dev->power.flags.power_resources)
-			result = device_create_file(&dev->dev,
-						    &dev_attr_real_power_state);
-	}
+	if (attr == &dev_attr_real_power_state)
+		return dev->flags.power_manageable && dev->power.flags.power_resources;
 
-	acpi_expose_nondev_subnodes(&dev->dev.kobj, &dev->data);
+	dev_warn_once(&dev->dev, "Unexpected attribute: %s\n", attr->attr.name);
+	return false;
+}
 
-end:
-	return result;
+static umode_t acpi_attr_is_visible(struct kobject *kobj,
+				    struct attribute *attr,
+				    int attrno)
+{
+	struct acpi_device *dev = to_acpi_device(kobj_to_dev(kobj));
+
+	if (acpi_show_attr(dev, container_of(attr, struct device_attribute, attr)))
+		return attr->mode;
+	else
+		return 0;
+}
+
+static const struct attribute_group acpi_group = {
+	.attrs = acpi_attrs,
+	.is_visible = acpi_attr_is_visible,
+};
+
+const struct attribute_group *acpi_groups[] = {
+	&acpi_group,
+	NULL
+};
+
+/**
+ * acpi_device_setup_files - Create sysfs attributes of an ACPI device.
+ * @dev: ACPI device object.
+ */
+void acpi_device_setup_files(struct acpi_device *dev)
+{
+	acpi_expose_nondev_subnodes(&dev->dev.kobj, &dev->data);
 }
 
 /**
@@ -605,41 +617,4 @@ end:
 void acpi_device_remove_files(struct acpi_device *dev)
 {
 	acpi_hide_nondev_subnodes(&dev->data);
-
-	if (dev->flags.power_manageable) {
-		device_remove_file(&dev->dev, &dev_attr_power_state);
-		if (dev->power.flags.power_resources)
-			device_remove_file(&dev->dev,
-					   &dev_attr_real_power_state);
-	}
-
-	/*
-	 * If device has _STR, remove 'description' file
-	 */
-	if (acpi_has_method(dev->handle, "_STR")) {
-		kfree(dev->pnp.str_obj);
-		device_remove_file(&dev->dev, &dev_attr_description);
-	}
-	/*
-	 * If device has _EJ0, remove 'eject' file.
-	 */
-	if (acpi_has_method(dev->handle, "_EJ0"))
-		device_remove_file(&dev->dev, &dev_attr_eject);
-
-	if (acpi_has_method(dev->handle, "_SUN"))
-		device_remove_file(&dev->dev, &dev_attr_sun);
-
-	if (acpi_has_method(dev->handle, "_HRV"))
-		device_remove_file(&dev->dev, &dev_attr_hrv);
-
-	if (dev->pnp.unique_id)
-		device_remove_file(&dev->dev, &dev_attr_uid);
-	if (dev->pnp.type.bus_address)
-		device_remove_file(&dev->dev, &dev_attr_adr);
-	device_remove_file(&dev->dev, &dev_attr_modalias);
-	device_remove_file(&dev->dev, &dev_attr_hid);
-	if (acpi_has_method(dev->handle, "_STA"))
-		device_remove_file(&dev->dev, &dev_attr_status);
-	if (dev->handle)
-		device_remove_file(&dev->dev, &dev_attr_path);
 }
diff --git a/drivers/acpi/dock.c b/drivers/acpi/dock.c
index e3414131bfca..34affbda295e 100644
--- a/drivers/acpi/dock.c
+++ b/drivers/acpi/dock.c
@@ -20,8 +20,6 @@
 
 #include "internal.h"
 
-ACPI_MODULE_NAME("dock");
-
 static bool immediate_undock = 1;
 module_param(immediate_undock, bool, 0644);
 MODULE_PARM_DESC(immediate_undock, "1 (default) will cause the driver to "
@@ -90,43 +88,29 @@ static void dock_hotplug_event(struct dock_dependent_device *dd, u32 event,
 			       enum dock_callback_type cb_type)
 {
 	struct acpi_device *adev = dd->adev;
+	acpi_hp_fixup fixup = NULL;
+	acpi_hp_uevent uevent = NULL;
+	acpi_hp_notify notify = NULL;
 
 	acpi_lock_hp_context();
 
-	if (!adev->hp)
-		goto out;
-
-	if (cb_type == DOCK_CALL_FIXUP) {
-		void (*fixup)(struct acpi_device *);
-
-		fixup = adev->hp->fixup;
-		if (fixup) {
-			acpi_unlock_hp_context();
-			fixup(adev);
-			return;
-		}
-	} else if (cb_type == DOCK_CALL_UEVENT) {
-		void (*uevent)(struct acpi_device *, u32);
-
-		uevent = adev->hp->uevent;
-		if (uevent) {
-			acpi_unlock_hp_context();
-			uevent(adev, event);
-			return;
-		}
-	} else {
-		int (*notify)(struct acpi_device *, u32);
-
-		notify = adev->hp->notify;
-		if (notify) {
-			acpi_unlock_hp_context();
-			notify(adev, event);
-			return;
-		}
+	if (adev->hp) {
+		if (cb_type == DOCK_CALL_FIXUP)
+			fixup = adev->hp->fixup;
+		else if (cb_type == DOCK_CALL_UEVENT)
+			uevent = adev->hp->uevent;
+		else
+			notify = adev->hp->notify;
 	}
 
- out:
 	acpi_unlock_hp_context();
+
+	if (fixup)
+		fixup(adev);
+	else if (uevent)
+		uevent(adev, event);
+	else if (notify)
+		notify(adev, event);
 }
 
 static struct dock_station *find_dock_station(acpi_handle handle)
@@ -233,7 +217,8 @@ static void hot_remove_dock_devices(struct dock_station *ds)
 	 * between them).
 	 */
 	list_for_each_entry_reverse(dd, &ds->dependent_devices, list)
-		dock_hotplug_event(dd, ACPI_NOTIFY_EJECT_REQUEST, false);
+		dock_hotplug_event(dd, ACPI_NOTIFY_EJECT_REQUEST,
+				   DOCK_CALL_HANDLER);
 
 	list_for_each_entry_reverse(dd, &ds->dependent_devices, list)
 		acpi_bus_trim(dd->adev);
@@ -272,6 +257,7 @@ static void hotplug_dock_devices(struct dock_station *ds, u32 event)
 
 		if (!acpi_device_enumerated(adev)) {
 			int ret = acpi_bus_scan(adev->handle);
+
 			if (ret)
 				dev_dbg(&adev->dev, "scan error %d\n", -ret);
 		}
@@ -380,6 +366,8 @@ static int dock_in_progress(struct dock_station *ds)
 
 /**
  * handle_eject_request - handle an undock request checking for error conditions
+ * @ds: The dock station to undock.
+ * @event: The ACPI event number associated with the undock request.
  *
  * Check to make sure the dock device is still present, then undock and
  * hotremove all the devices that may need removing.
@@ -469,7 +457,7 @@ int dock_notify(struct acpi_device *adev, u32 event)
 		surprise_removal = 1;
 		event = ACPI_NOTIFY_EJECT_REQUEST;
 		/* Fall back */
-		/* fall through */
+		fallthrough;
 	case ACPI_NOTIFY_EJECT_REQUEST:
 		begin_undock(ds);
 		if ((immediate_undock && !(ds->flags & DOCK_IS_ATA))
@@ -485,34 +473,34 @@ int dock_notify(struct acpi_device *adev, u32 event)
 /*
  * show_docked - read method for "docked" file in sysfs
  */
-static ssize_t show_docked(struct device *dev,
+static ssize_t docked_show(struct device *dev,
 			   struct device_attribute *attr, char *buf)
 {
 	struct dock_station *dock_station = dev->platform_data;
-	struct acpi_device *adev = NULL;
+	struct acpi_device *adev = acpi_fetch_acpi_dev(dock_station->handle);
 
-	acpi_bus_get_device(dock_station->handle, &adev);
-	return snprintf(buf, PAGE_SIZE, "%u\n", acpi_device_enumerated(adev));
+	return sysfs_emit(buf, "%u\n", acpi_device_enumerated(adev));
 }
-static DEVICE_ATTR(docked, S_IRUGO, show_docked, NULL);
+static DEVICE_ATTR_RO(docked);
 
 /*
  * show_flags - read method for flags file in sysfs
  */
-static ssize_t show_flags(struct device *dev,
+static ssize_t flags_show(struct device *dev,
 			  struct device_attribute *attr, char *buf)
 {
 	struct dock_station *dock_station = dev->platform_data;
-	return snprintf(buf, PAGE_SIZE, "%d\n", dock_station->flags);
+
+	return sysfs_emit(buf, "%d\n", dock_station->flags);
 
 }
-static DEVICE_ATTR(flags, S_IRUGO, show_flags, NULL);
+static DEVICE_ATTR_RO(flags);
 
 /*
  * write_undock - write method for "undock" file in sysfs
  */
-static ssize_t write_undock(struct device *dev, struct device_attribute *attr,
-			   const char *buf, size_t count)
+static ssize_t undock_store(struct device *dev, struct device_attribute *attr,
+			    const char *buf, size_t count)
 {
 	int ret;
 	struct dock_station *dock_station = dev->platform_data;
@@ -524,29 +512,30 @@ static ssize_t write_undock(struct device *dev, struct device_attribute *attr,
 	begin_undock(dock_station);
 	ret = handle_eject_request(dock_station, ACPI_NOTIFY_EJECT_REQUEST);
 	acpi_scan_lock_release();
-	return ret ? ret: count;
+	return ret ? ret : count;
 }
-static DEVICE_ATTR(undock, S_IWUSR, NULL, write_undock);
+static DEVICE_ATTR_WO(undock);
 
 /*
  * show_dock_uid - read method for "uid" file in sysfs
  */
-static ssize_t show_dock_uid(struct device *dev,
-			     struct device_attribute *attr, char *buf)
+static ssize_t uid_show(struct device *dev,
+			struct device_attribute *attr, char *buf)
 {
 	unsigned long long lbuf;
 	struct dock_station *dock_station = dev->platform_data;
+
 	acpi_status status = acpi_evaluate_integer(dock_station->handle,
 					"_UID", NULL, &lbuf);
 	if (ACPI_FAILURE(status))
-	    return 0;
+		return 0;
 
-	return snprintf(buf, PAGE_SIZE, "%llx\n", lbuf);
+	return sysfs_emit(buf, "%llx\n", lbuf);
 }
-static DEVICE_ATTR(uid, S_IRUGO, show_dock_uid, NULL);
+static DEVICE_ATTR_RO(uid);
 
-static ssize_t show_dock_type(struct device *dev,
-		struct device_attribute *attr, char *buf)
+static ssize_t type_show(struct device *dev,
+			 struct device_attribute *attr, char *buf)
 {
 	struct dock_station *dock_station = dev->platform_data;
 	char *type;
@@ -560,9 +549,9 @@ static ssize_t show_dock_type(struct device *dev,
 	else
 		type = "unknown";
 
-	return snprintf(buf, PAGE_SIZE, "%s\n", type);
+	return sysfs_emit(buf, "%s\n", type);
 }
-static DEVICE_ATTR(type, S_IRUGO, show_dock_type, NULL);
+static DEVICE_ATTR_RO(type);
 
 static struct attribute *dock_attributes[] = {
 	&dev_attr_docked.attr,
diff --git a/drivers/acpi/dptf/Kconfig b/drivers/acpi/dptf/Kconfig
index 90a2fd979282..4b3fdc03e4ed 100644
--- a/drivers/acpi/dptf/Kconfig
+++ b/drivers/acpi/dptf/Kconfig
@@ -1,8 +1,22 @@
 # SPDX-License-Identifier: GPL-2.0
-config DPTF_POWER
-	tristate "DPTF Platform Power Participant"
+
+menuconfig ACPI_DPTF
+	bool "Intel DPTF (Dynamic Platform and Thermal Framework) Support"
 	depends on X86
 	help
+	  Intel Dynamic Platform and Thermal Framework (DPTF) is a platform
+	  level hardware/software solution for power and thermal management.
+
+	  As a container for multiple power/thermal technologies, DPTF provides
+	  a coordinated approach for different policies to effect the hardware
+	  state of a system.
+
+if ACPI_DPTF
+
+config DPTF_POWER
+	tristate "Platform Power DPTF Participant"
+	default m
+	help
 	  This driver adds support for Dynamic Platform and Thermal Framework
 	  (DPTF) Platform Power Participant device (INT3407) support.
 	  This participant is responsible for exposing platform telemetry:
@@ -14,3 +28,19 @@ config DPTF_POWER
 
 	  To compile this driver as a module, choose M here:
 	  the module will be called dptf_power.
+
+config DPTF_PCH_FIVR
+	tristate "PCH FIVR DPTF Participant"
+	default m
+	help
+	  This driver adds support for Dynamic Platform and Thermal Framework
+	  (DPTF) PCH FIVR Participant device support. This driver allows to
+	  switch the PCH FIVR (Fully Integrated Voltage Regulator) frequency.
+	  This participant is responsible for exposing:
+		freq_mhz_low_clock
+		freq_mhz_high_clock
+
+	  To compile this driver as a module, choose M here:
+	  the module will be called dptf_pch_fivr.
+
+endif
diff --git a/drivers/acpi/dptf/Makefile b/drivers/acpi/dptf/Makefile
index 1a9b0a2b25bf..e912a3be1d28 100644
--- a/drivers/acpi/dptf/Makefile
+++ b/drivers/acpi/dptf/Makefile
@@ -1,3 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0-only
-obj-$(CONFIG_ACPI)             += int340x_thermal.o
 obj-$(CONFIG_DPTF_POWER)	+= dptf_power.o
+obj-$(CONFIG_DPTF_PCH_FIVR)	+= dptf_pch_fivr.o
diff --git a/drivers/acpi/dptf/dptf_pch_fivr.c b/drivers/acpi/dptf/dptf_pch_fivr.c
new file mode 100644
index 000000000000..8d7e555929d3
--- /dev/null
+++ b/drivers/acpi/dptf/dptf_pch_fivr.c
@@ -0,0 +1,173 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * dptf_pch_fivr:  DPTF PCH FIVR Participant driver
+ * Copyright (c) 2020, Intel Corporation.
+ */
+
+#include <linux/acpi.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+struct pch_fivr_resp {
+	u64 status;
+	u64 result;
+};
+
+static int pch_fivr_read(acpi_handle handle, char *method, struct pch_fivr_resp *fivr_resp)
+{
+	struct acpi_buffer resp = { sizeof(struct pch_fivr_resp), fivr_resp};
+	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
+	struct acpi_buffer format = { sizeof("NN"), "NN" };
+	union acpi_object *obj;
+	acpi_status status;
+	int ret = -EFAULT;
+
+	status = acpi_evaluate_object(handle, method, NULL, &buffer);
+	if (ACPI_FAILURE(status))
+		return ret;
+
+	obj = buffer.pointer;
+	if (!obj || obj->type != ACPI_TYPE_PACKAGE)
+		goto release_buffer;
+
+	status = acpi_extract_package(obj, &format, &resp);
+	if (ACPI_FAILURE(status))
+		goto release_buffer;
+
+	if (fivr_resp->status)
+		goto release_buffer;
+
+	ret = 0;
+
+release_buffer:
+	ACPI_FREE(buffer.pointer);
+	return ret;
+}
+
+/*
+ * Presentation of attributes which are defined for INTC10xx
+ * They are:
+ * freq_mhz_low_clock : Set PCH FIVR switching freq for
+ *			FIVR clock 19.2MHz and 24MHz
+ * freq_mhz_high_clock : Set PCH FIVR switching freq for
+ *			FIVR clock 38.4MHz
+ */
+#define PCH_FIVR_SHOW(name, method) \
+static ssize_t name##_show(struct device *dev,\
+			   struct device_attribute *attr,\
+			   char *buf)\
+{\
+	struct acpi_device *acpi_dev = dev_get_drvdata(dev);\
+	struct pch_fivr_resp fivr_resp;\
+	int status;\
+\
+	status = pch_fivr_read(acpi_dev->handle, #method, &fivr_resp);\
+	if (status)\
+		return status;\
+\
+	return sprintf(buf, "%llu\n", fivr_resp.result);\
+}
+
+#define PCH_FIVR_STORE(name, method) \
+static ssize_t name##_store(struct device *dev,\
+			    struct device_attribute *attr,\
+			    const char *buf, size_t count)\
+{\
+	struct acpi_device *acpi_dev = dev_get_drvdata(dev);\
+	acpi_status status;\
+	u32 val;\
+\
+	if (kstrtouint(buf, 0, &val) < 0)\
+		return -EINVAL;\
+\
+	status = acpi_execute_simple_method(acpi_dev->handle, #method, val);\
+	if (ACPI_SUCCESS(status))\
+		return count;\
+\
+	return -EINVAL;\
+}
+
+PCH_FIVR_SHOW(freq_mhz_low_clock, GFC0)
+PCH_FIVR_SHOW(freq_mhz_high_clock, GFC1)
+PCH_FIVR_SHOW(ssc_clock_info, GEMI)
+PCH_FIVR_SHOW(fivr_switching_freq_mhz, GFCS)
+PCH_FIVR_SHOW(fivr_switching_fault_status, GFFS)
+PCH_FIVR_STORE(freq_mhz_low_clock, RFC0)
+PCH_FIVR_STORE(freq_mhz_high_clock, RFC1)
+
+static DEVICE_ATTR_RW(freq_mhz_low_clock);
+static DEVICE_ATTR_RW(freq_mhz_high_clock);
+static DEVICE_ATTR_RO(ssc_clock_info);
+static DEVICE_ATTR_RO(fivr_switching_freq_mhz);
+static DEVICE_ATTR_RO(fivr_switching_fault_status);
+
+static struct attribute *fivr_attrs[] = {
+	&dev_attr_freq_mhz_low_clock.attr,
+	&dev_attr_freq_mhz_high_clock.attr,
+	&dev_attr_ssc_clock_info.attr,
+	&dev_attr_fivr_switching_freq_mhz.attr,
+	&dev_attr_fivr_switching_fault_status.attr,
+	NULL
+};
+
+static const struct attribute_group pch_fivr_attribute_group = {
+	.attrs = fivr_attrs,
+	.name = "pch_fivr_switch_frequency"
+};
+
+static int pch_fivr_add(struct platform_device *pdev)
+{
+	struct acpi_device *acpi_dev;
+	unsigned long long ptype;
+	acpi_status status;
+	int result;
+
+	acpi_dev = ACPI_COMPANION(&(pdev->dev));
+	if (!acpi_dev)
+		return -ENODEV;
+
+	status = acpi_evaluate_integer(acpi_dev->handle, "PTYP", NULL, &ptype);
+	if (ACPI_FAILURE(status) || ptype != 0x05)
+		return -ENODEV;
+
+	result = sysfs_create_group(&pdev->dev.kobj,
+				    &pch_fivr_attribute_group);
+	if (result)
+		return result;
+
+	platform_set_drvdata(pdev, acpi_dev);
+
+	return 0;
+}
+
+static void pch_fivr_remove(struct platform_device *pdev)
+{
+	sysfs_remove_group(&pdev->dev.kobj, &pch_fivr_attribute_group);
+}
+
+static const struct acpi_device_id pch_fivr_device_ids[] = {
+	{"INTC1045", 0},
+	{"INTC1049", 0},
+	{"INTC1064", 0},
+	{"INTC106B", 0},
+	{"INTC10A3", 0},
+	{"INTC10D7", 0},
+	{"", 0},
+};
+MODULE_DEVICE_TABLE(acpi, pch_fivr_device_ids);
+
+static struct platform_driver pch_fivr_driver = {
+	.probe = pch_fivr_add,
+	.remove = pch_fivr_remove,
+	.driver = {
+		.name = "dptf_pch_fivr",
+		.acpi_match_table = pch_fivr_device_ids,
+	},
+};
+
+module_platform_driver(pch_fivr_driver);
+
+MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("ACPI DPTF PCH FIVR driver");
diff --git a/drivers/acpi/dptf/dptf_power.c b/drivers/acpi/dptf/dptf_power.c
index e4e8b75d39f0..55ccbb8ddbe3 100644
--- a/drivers/acpi/dptf/dptf_power.c
+++ b/drivers/acpi/dptf/dptf_power.c
@@ -10,12 +10,17 @@
 #include <linux/platform_device.h>
 
 /*
- * Presentation of attributes which are defined for INT3407. They are:
- * PMAX : Maximum platform powe
+ * Presentation of attributes which are defined for INT3407 and INT3532.
+ * They are:
+ * PMAX : Maximum platform power
  * PSRC : Platform power source
  * ARTG : Adapter rating
  * CTYP : Charger type
- * PBSS : Battery steady power
+ * PROP : Rest of worst case platform Power
+ * PBSS : Power Battery Steady State
+ * RBHF : High Frequency Impedance
+ * VBNL : Instantaneous No-Load Voltage
+ * CMPP : Current Discharge Capability
  */
 #define DPTF_POWER_SHOW(name, object) \
 static ssize_t name##_show(struct device *dev,\
@@ -39,12 +44,42 @@ DPTF_POWER_SHOW(platform_power_source, PSRC)
 DPTF_POWER_SHOW(adapter_rating_mw, ARTG)
 DPTF_POWER_SHOW(battery_steady_power_mw, PBSS)
 DPTF_POWER_SHOW(charger_type, CTYP)
+DPTF_POWER_SHOW(rest_of_platform_power_mw, PROP)
+DPTF_POWER_SHOW(max_steady_state_power_mw, PBSS)
+DPTF_POWER_SHOW(high_freq_impedance_mohm, RBHF)
+DPTF_POWER_SHOW(no_load_voltage_mv, VBNL)
+DPTF_POWER_SHOW(current_discharge_capbility_ma, CMPP);
 
 static DEVICE_ATTR_RO(max_platform_power_mw);
 static DEVICE_ATTR_RO(platform_power_source);
 static DEVICE_ATTR_RO(adapter_rating_mw);
 static DEVICE_ATTR_RO(battery_steady_power_mw);
 static DEVICE_ATTR_RO(charger_type);
+static DEVICE_ATTR_RO(rest_of_platform_power_mw);
+static DEVICE_ATTR_RO(max_steady_state_power_mw);
+static DEVICE_ATTR_RO(high_freq_impedance_mohm);
+static DEVICE_ATTR_RO(no_load_voltage_mv);
+static DEVICE_ATTR_RO(current_discharge_capbility_ma);
+
+static ssize_t prochot_confirm_store(struct device *dev,
+				     struct device_attribute *attr,
+				     const char *buf, size_t count)
+{
+	struct acpi_device *acpi_dev = dev_get_drvdata(dev);
+	acpi_status status;
+	int seq_no;
+
+	if (kstrtouint(buf, 0, &seq_no) < 0)
+		return -EINVAL;
+
+	status = acpi_execute_simple_method(acpi_dev->handle, "PBOK", seq_no);
+	if (ACPI_SUCCESS(status))
+		return count;
+
+	return -EINVAL;
+}
+
+static DEVICE_ATTR_WO(prochot_confirm);
 
 static struct attribute *dptf_power_attrs[] = {
 	&dev_attr_max_platform_power_mw.attr,
@@ -52,6 +87,8 @@ static struct attribute *dptf_power_attrs[] = {
 	&dev_attr_adapter_rating_mw.attr,
 	&dev_attr_battery_steady_power_mw.attr,
 	&dev_attr_charger_type.attr,
+	&dev_attr_rest_of_platform_power_mw.attr,
+	&dev_attr_prochot_confirm.attr,
 	NULL
 };
 
@@ -60,10 +97,82 @@ static const struct attribute_group dptf_power_attribute_group = {
 	.name = "dptf_power"
 };
 
+static struct attribute *dptf_battery_attrs[] = {
+	&dev_attr_max_platform_power_mw.attr,
+	&dev_attr_max_steady_state_power_mw.attr,
+	&dev_attr_high_freq_impedance_mohm.attr,
+	&dev_attr_no_load_voltage_mv.attr,
+	&dev_attr_current_discharge_capbility_ma.attr,
+	NULL
+};
+
+static const struct attribute_group dptf_battery_attribute_group = {
+	.attrs = dptf_battery_attrs,
+	.name = "dptf_battery"
+};
+
+#define MAX_POWER_CHANGED		0x80
+#define POWER_STATE_CHANGED		0x81
+#define STEADY_STATE_POWER_CHANGED	0x83
+#define POWER_PROP_CHANGE_EVENT	0x84
+#define IMPEDANCE_CHANGED		0x85
+#define VOLTAGE_CURRENT_CHANGED	0x86
+
+static long long dptf_participant_type(acpi_handle handle)
+{
+	unsigned long long ptype;
+	acpi_status status;
+
+	status = acpi_evaluate_integer(handle, "PTYP", NULL, &ptype);
+	if (ACPI_FAILURE(status))
+		return -ENODEV;
+
+	return ptype;
+}
+
+static void dptf_power_notify(acpi_handle handle, u32 event, void *data)
+{
+	struct platform_device *pdev = data;
+	char *attr;
+
+	switch (event) {
+	case POWER_STATE_CHANGED:
+		attr = "platform_power_source";
+		break;
+	case POWER_PROP_CHANGE_EVENT:
+		attr = "rest_of_platform_power_mw";
+		break;
+	case MAX_POWER_CHANGED:
+		attr = "max_platform_power_mw";
+		break;
+	case STEADY_STATE_POWER_CHANGED:
+		attr = "max_steady_state_power_mw";
+		break;
+	case IMPEDANCE_CHANGED:
+		attr = "high_freq_impedance_mohm";
+		break;
+	case VOLTAGE_CURRENT_CHANGED:
+		attr = "no_load_voltage_mv";
+		break;
+	default:
+		dev_err(&pdev->dev, "Unsupported event [0x%x]\n", event);
+		return;
+	}
+
+	/*
+	 * Notify that an attribute is changed, so that user space can read
+	 * again.
+	 */
+	if (dptf_participant_type(handle) == 0x0CULL)
+		sysfs_notify(&pdev->dev.kobj, "dptf_battery", attr);
+	else
+		sysfs_notify(&pdev->dev.kobj, "dptf_power", attr);
+}
+
 static int dptf_power_add(struct platform_device *pdev)
 {
+	const struct attribute_group *attr_group;
 	struct acpi_device *acpi_dev;
-	acpi_status status;
 	unsigned long long ptype;
 	int result;
 
@@ -71,34 +180,68 @@ static int dptf_power_add(struct platform_device *pdev)
 	if (!acpi_dev)
 		return -ENODEV;
 
-	status = acpi_evaluate_integer(acpi_dev->handle, "PTYP", NULL, &ptype);
-	if (ACPI_FAILURE(status))
+	ptype = dptf_participant_type(acpi_dev->handle);
+	if (ptype == 0x11)
+		attr_group = &dptf_power_attribute_group;
+	else if (ptype == 0x0C)
+		attr_group = &dptf_battery_attribute_group;
+	else
 		return -ENODEV;
 
-	if (ptype != 0x11)
-		return -ENODEV;
+	result = acpi_install_notify_handler(acpi_dev->handle,
+					     ACPI_DEVICE_NOTIFY,
+					     dptf_power_notify,
+					     (void *)pdev);
+	if (result)
+		return result;
 
 	result = sysfs_create_group(&pdev->dev.kobj,
-				    &dptf_power_attribute_group);
-	if (result)
+				    attr_group);
+	if (result) {
+		acpi_remove_notify_handler(acpi_dev->handle,
+					   ACPI_DEVICE_NOTIFY,
+					   dptf_power_notify);
 		return result;
+	}
 
 	platform_set_drvdata(pdev, acpi_dev);
 
 	return 0;
 }
 
-static int dptf_power_remove(struct platform_device *pdev)
+static void dptf_power_remove(struct platform_device *pdev)
 {
+	struct acpi_device *acpi_dev = platform_get_drvdata(pdev);
 
-	sysfs_remove_group(&pdev->dev.kobj, &dptf_power_attribute_group);
+	acpi_remove_notify_handler(acpi_dev->handle,
+				   ACPI_DEVICE_NOTIFY,
+				   dptf_power_notify);
 
-	return 0;
+	if (dptf_participant_type(acpi_dev->handle) == 0x0CULL)
+		sysfs_remove_group(&pdev->dev.kobj, &dptf_battery_attribute_group);
+	else
+		sysfs_remove_group(&pdev->dev.kobj, &dptf_power_attribute_group);
 }
 
 static const struct acpi_device_id int3407_device_ids[] = {
 	{"INT3407", 0},
+	{"INT3532", 0},
 	{"INTC1047", 0},
+	{"INTC1050", 0},
+	{"INTC1060", 0},
+	{"INTC1061", 0},
+	{"INTC1065", 0},
+	{"INTC1066", 0},
+	{"INTC106C", 0},
+	{"INTC106D", 0},
+	{"INTC10A4", 0},
+	{"INTC10A5", 0},
+	{"INTC10D8", 0},
+	{"INTC10D9", 0},
+	{"INTC1100", 0},
+	{"INTC1101", 0},
+	{"INTC10F7", 0},
+	{"INTC10F8", 0},
 	{"", 0},
 };
 MODULE_DEVICE_TABLE(acpi, int3407_device_ids);
@@ -107,7 +250,7 @@ static struct platform_driver dptf_power_driver = {
 	.probe = dptf_power_add,
 	.remove = dptf_power_remove,
 	.driver = {
-		.name = "DPTF Platform Power",
+		.name = "dptf_power",
 		.acpi_match_table = int3407_device_ids,
 	},
 };
diff --git a/drivers/acpi/dptf/int340x_thermal.c b/drivers/acpi/dptf/int340x_thermal.c
deleted file mode 100644
index bc71a6a60334..000000000000
--- a/drivers/acpi/dptf/int340x_thermal.c
+++ /dev/null
@@ -1,54 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * ACPI support for int340x thermal drivers
- *
- * Copyright (C) 2014, Intel Corporation
- * Authors: Zhang Rui <rui.zhang@intel.com>
- */
-
-#include <linux/acpi.h>
-#include <linux/module.h>
-
-#include "../internal.h"
-
-#define INT3401_DEVICE 0X01
-static const struct acpi_device_id int340x_thermal_device_ids[] = {
-	{"INT3400"},
-	{"INT3401", INT3401_DEVICE},
-	{"INT3402"},
-	{"INT3403"},
-	{"INT3404"},
-	{"INT3406"},
-	{"INT3407"},
-	{"INT3408"},
-	{"INT3409"},
-	{"INT340A"},
-	{"INT340B"},
-	{"INTC1040"},
-	{"INTC1043"},
-	{"INTC1044"},
-	{"INTC1047"},
-	{""},
-};
-
-static int int340x_thermal_handler_attach(struct acpi_device *adev,
-					const struct acpi_device_id *id)
-{
-	if (IS_ENABLED(CONFIG_INT340X_THERMAL))
-		acpi_create_platform_device(adev, NULL);
-	/* Intel SoC DTS thermal driver needs INT3401 to set IRQ descriptor */
-	else if (IS_ENABLED(CONFIG_INTEL_SOC_DTS_THERMAL) &&
-		 id->driver_data == INT3401_DEVICE)
-		acpi_create_platform_device(adev, NULL);
-	return 1;
-}
-
-static struct acpi_scan_handler int340x_thermal_handler = {
-	.ids = int340x_thermal_device_ids,
-	.attach = int340x_thermal_handler_attach,
-};
-
-void __init acpi_int340x_thermal_init(void)
-{
-	acpi_scan_add_handler(&int340x_thermal_handler);
-}
diff --git a/drivers/acpi/ec.c b/drivers/acpi/ec.c
index b4c0152e92aa..59b3d50ff01e 100644
--- a/drivers/acpi/ec.c
+++ b/drivers/acpi/ec.c
@@ -23,8 +23,10 @@
 #include <linux/delay.h>
 #include <linux/interrupt.h>
 #include <linux/list.h>
+#include <linux/printk.h>
 #include <linux/spinlock.h>
 #include <linux/slab.h>
+#include <linux/string.h>
 #include <linux/suspend.h>
 #include <linux/acpi.h>
 #include <linux/dmi.h>
@@ -34,7 +36,6 @@
 
 #define ACPI_EC_CLASS			"embedded_controller"
 #define ACPI_EC_DEVICE_NAME		"Embedded Controller"
-#define ACPI_EC_FILE_INFO		"info"
 
 /* EC status register */
 #define ACPI_EC_FLAG_OBF	0x01	/* Output buffer full */
@@ -93,10 +94,9 @@ enum ec_command {
 
 enum {
 	EC_FLAGS_QUERY_ENABLED,		/* Query is enabled */
-	EC_FLAGS_QUERY_PENDING,		/* Query is pending */
-	EC_FLAGS_QUERY_GUARDING,	/* Guard for SCI_EVT check */
 	EC_FLAGS_EVENT_HANDLER_INSTALLED,	/* Event handler installed */
 	EC_FLAGS_EC_HANDLER_INSTALLED,	/* OpReg handler installed */
+	EC_FLAGS_EC_REG_CALLED,		/* OpReg ACPI _REG method called */
 	EC_FLAGS_QUERY_METHODS_INSTALLED, /* _Qxx handlers installed */
 	EC_FLAGS_STARTED,		/* Driver is started */
 	EC_FLAGS_STOPPED,		/* Driver is stopped */
@@ -134,7 +134,7 @@ static unsigned int ec_storm_threshold  __read_mostly = 8;
 module_param(ec_storm_threshold, uint, 0644);
 MODULE_PARM_DESC(ec_storm_threshold, "Maxim false GPE numbers not considered as GPE storm");
 
-static bool ec_freeze_events __read_mostly = false;
+static bool ec_freeze_events __read_mostly;
 module_param(ec_freeze_events, bool, 0644);
 MODULE_PARM_DESC(ec_freeze_events, "Disabling event handling during suspend/resume");
 
@@ -167,23 +167,23 @@ struct acpi_ec_query {
 	struct transaction transaction;
 	struct work_struct work;
 	struct acpi_ec_query_handler *handler;
+	struct acpi_ec *ec;
 };
 
-static int acpi_ec_query(struct acpi_ec *ec, u8 *data);
-static void advance_transaction(struct acpi_ec *ec);
+static int acpi_ec_submit_query(struct acpi_ec *ec);
+static void advance_transaction(struct acpi_ec *ec, bool interrupt);
 static void acpi_ec_event_handler(struct work_struct *work);
-static void acpi_ec_event_processor(struct work_struct *work);
 
 struct acpi_ec *first_ec;
 EXPORT_SYMBOL(first_ec);
 
 static struct acpi_ec *boot_ec;
-static bool boot_ec_is_ecdt = false;
+static bool boot_ec_is_ecdt;
 static struct workqueue_struct *ec_wq;
 static struct workqueue_struct *ec_query_wq;
 
 static int EC_FLAGS_CORRECT_ECDT; /* Needs ECDT port address correction */
-static int EC_FLAGS_IGNORE_DSDT_GPE; /* Needs ECDT GPE as correction setting */
+static int EC_FLAGS_TRUST_DSDT_GPE; /* Needs DSDT GPE as correction setting */
 static int EC_FLAGS_CLEAR_ON_RESUME; /* Needs acpi_ec_clear() on boot/resume */
 
 /* --------------------------------------------------------------------------
@@ -336,12 +336,12 @@ static const char *acpi_ec_cmd_string(u8 cmd)
  *                           GPE Registers
  * -------------------------------------------------------------------------- */
 
-static inline bool acpi_ec_is_gpe_raised(struct acpi_ec *ec)
+static inline bool acpi_ec_gpe_status_set(struct acpi_ec *ec)
 {
 	acpi_event_status gpe_status = 0;
 
 	(void)acpi_get_gpe_status(NULL, ec->gpe, &gpe_status);
-	return (gpe_status & ACPI_EVENT_FLAG_STATUS_SET) ? true : false;
+	return !!(gpe_status & ACPI_EVENT_FLAG_STATUS_SET);
 }
 
 static inline void acpi_ec_enable_gpe(struct acpi_ec *ec, bool open)
@@ -352,14 +352,14 @@ static inline void acpi_ec_enable_gpe(struct acpi_ec *ec, bool open)
 		BUG_ON(ec->reference_count < 1);
 		acpi_set_gpe(NULL, ec->gpe, ACPI_GPE_ENABLE);
 	}
-	if (acpi_ec_is_gpe_raised(ec)) {
+	if (acpi_ec_gpe_status_set(ec)) {
 		/*
 		 * On some platforms, EN=1 writes cannot trigger GPE. So
 		 * software need to manually trigger a pseudo GPE event on
 		 * EN=1 writes.
 		 */
 		ec_dbg_raw("Polling quirk");
-		advance_transaction(ec);
+		advance_transaction(ec, false);
 	}
 }
 
@@ -373,23 +373,6 @@ static inline void acpi_ec_disable_gpe(struct acpi_ec *ec, bool close)
 	}
 }
 
-static inline void acpi_ec_clear_gpe(struct acpi_ec *ec)
-{
-	/*
-	 * GPE STS is a W1C register, which means:
-	 * 1. Software can clear it without worrying about clearing other
-	 *    GPEs' STS bits when the hardware sets them in parallel.
-	 * 2. As long as software can ensure only clearing it when it is
-	 *    set, hardware won't set it in parallel.
-	 * So software can clear GPE in any contexts.
-	 * Warning: do not move the check into advance_transaction() as the
-	 * EC commands will be sent without GPE raised.
-	 */
-	if (!acpi_ec_is_gpe_raised(ec))
-		return;
-	acpi_clear_gpe(NULL, ec->gpe);
-}
-
 /* --------------------------------------------------------------------------
  *                           Transaction Management
  * -------------------------------------------------------------------------- */
@@ -460,24 +443,50 @@ static bool acpi_ec_submit_flushable_request(struct acpi_ec *ec)
 	return true;
 }
 
-static void acpi_ec_submit_query(struct acpi_ec *ec)
+static void acpi_ec_submit_event(struct acpi_ec *ec)
 {
+	/*
+	 * It is safe to mask the events here, because acpi_ec_close_event()
+	 * will run at least once after this.
+	 */
 	acpi_ec_mask_events(ec);
 	if (!acpi_ec_event_enabled(ec))
 		return;
-	if (!test_and_set_bit(EC_FLAGS_QUERY_PENDING, &ec->flags)) {
-		ec_dbg_evt("Command(%s) submitted/blocked",
-			   acpi_ec_cmd_string(ACPI_EC_COMMAND_QUERY));
-		ec->nr_pending_queries++;
-		queue_work(ec_wq, &ec->work);
-	}
+
+	if (ec->event_state != EC_EVENT_READY)
+		return;
+
+	ec_dbg_evt("Command(%s) submitted/blocked",
+		   acpi_ec_cmd_string(ACPI_EC_COMMAND_QUERY));
+
+	ec->event_state = EC_EVENT_IN_PROGRESS;
+	/*
+	 * If events_to_process is greater than 0 at this point, the while ()
+	 * loop in acpi_ec_event_handler() is still running and incrementing
+	 * events_to_process will cause it to invoke acpi_ec_submit_query() once
+	 * more, so it is not necessary to queue up the event work to start the
+	 * same loop again.
+	 */
+	if (ec->events_to_process++ > 0)
+		return;
+
+	ec->events_in_progress++;
+	queue_work(ec_wq, &ec->work);
+}
+
+static void acpi_ec_complete_event(struct acpi_ec *ec)
+{
+	if (ec->event_state == EC_EVENT_IN_PROGRESS)
+		ec->event_state = EC_EVENT_COMPLETE;
 }
 
-static void acpi_ec_complete_query(struct acpi_ec *ec)
+static void acpi_ec_close_event(struct acpi_ec *ec)
 {
-	if (test_and_clear_bit(EC_FLAGS_QUERY_PENDING, &ec->flags))
+	if (ec->event_state != EC_EVENT_READY)
 		ec_dbg_evt("Command(%s) unblocked",
 			   acpi_ec_cmd_string(ACPI_EC_COMMAND_QUERY));
+
+	ec->event_state = EC_EVENT_READY;
 	acpi_ec_unmask_events(ec);
 }
 
@@ -489,7 +498,7 @@ static inline void __acpi_ec_enable_event(struct acpi_ec *ec)
 	 * Unconditionally invoke this once after enabling the event
 	 * handling mechanism to detect the pending events.
 	 */
-	advance_transaction(ec);
+	advance_transaction(ec, false);
 }
 
 static inline void __acpi_ec_disable_event(struct acpi_ec *ec)
@@ -504,12 +513,10 @@ static inline void __acpi_ec_disable_event(struct acpi_ec *ec)
  */
 static void acpi_ec_clear(struct acpi_ec *ec)
 {
-	int i, status;
-	u8 value = 0;
+	int i;
 
 	for (i = 0; i < ACPI_EC_CLEAR_MAX; i++) {
-		status = acpi_ec_query(ec, &value);
-		if (status || !value)
+		if (acpi_ec_submit_query(ec))
 			break;
 	}
 	if (unlikely(i == ACPI_EC_CLEAR_MAX))
@@ -535,7 +542,7 @@ static void acpi_ec_enable_event(struct acpi_ec *ec)
 #ifdef CONFIG_PM_SLEEP
 static void __acpi_ec_flush_work(void)
 {
-	drain_workqueue(ec_wq); /* flush ec->work */
+	flush_workqueue(ec_wq); /* flush ec->work */
 	flush_workqueue(ec_query_wq); /* flush queries */
 }
 
@@ -566,8 +573,8 @@ void acpi_ec_flush_work(void)
 
 static bool acpi_ec_guard_event(struct acpi_ec *ec)
 {
-	bool guarded = true;
 	unsigned long flags;
+	bool guarded;
 
 	spin_lock_irqsave(&ec->lock, flags);
 	/*
@@ -576,19 +583,15 @@ static bool acpi_ec_guard_event(struct acpi_ec *ec)
 	 * evaluating _Qxx, so we need to re-check SCI_EVT after waiting an
 	 * acceptable period.
 	 *
-	 * The guarding period begins when EC_FLAGS_QUERY_PENDING is
-	 * flagged, which means SCI_EVT check has just been performed.
-	 * But if the current transaction is ACPI_EC_COMMAND_QUERY, the
-	 * guarding should have already been performed (via
-	 * EC_FLAGS_QUERY_GUARDING) and should not be applied so that the
-	 * ACPI_EC_COMMAND_QUERY transaction can be transitioned into
-	 * ACPI_EC_COMMAND_POLL state immediately.
+	 * The guarding period is applicable if the event state is not
+	 * EC_EVENT_READY, but otherwise if the current transaction is of the
+	 * ACPI_EC_COMMAND_QUERY type, the guarding should have elapsed already
+	 * and it should not be applied to let the transaction transition into
+	 * the ACPI_EC_COMMAND_POLL state immediately.
 	 */
-	if (ec_event_clearing == ACPI_EC_EVT_TIMING_STATUS ||
-	    ec_event_clearing == ACPI_EC_EVT_TIMING_QUERY ||
-	    !test_bit(EC_FLAGS_QUERY_PENDING, &ec->flags) ||
-	    (ec->curr && ec->curr->command == ACPI_EC_COMMAND_QUERY))
-		guarded = false;
+	guarded = ec_event_clearing == ACPI_EC_EVT_TIMING_EVENT &&
+		ec->event_state != EC_EVENT_READY &&
+		(!ec->curr || ec->curr->command != ACPI_EC_COMMAND_QUERY);
 	spin_unlock_irqrestore(&ec->lock, flags);
 	return guarded;
 }
@@ -620,98 +623,95 @@ static int ec_transaction_completed(struct acpi_ec *ec)
 static inline void ec_transaction_transition(struct acpi_ec *ec, unsigned long flag)
 {
 	ec->curr->flags |= flag;
-	if (ec->curr->command == ACPI_EC_COMMAND_QUERY) {
-		if (ec_event_clearing == ACPI_EC_EVT_TIMING_STATUS &&
-		    flag == ACPI_EC_COMMAND_POLL)
-			acpi_ec_complete_query(ec);
-		if (ec_event_clearing == ACPI_EC_EVT_TIMING_QUERY &&
-		    flag == ACPI_EC_COMMAND_COMPLETE)
-			acpi_ec_complete_query(ec);
-		if (ec_event_clearing == ACPI_EC_EVT_TIMING_EVENT &&
-		    flag == ACPI_EC_COMMAND_COMPLETE)
-			set_bit(EC_FLAGS_QUERY_GUARDING, &ec->flags);
+
+	if (ec->curr->command != ACPI_EC_COMMAND_QUERY)
+		return;
+
+	switch (ec_event_clearing) {
+	case ACPI_EC_EVT_TIMING_STATUS:
+		if (flag == ACPI_EC_COMMAND_POLL)
+			acpi_ec_close_event(ec);
+
+		return;
+
+	case ACPI_EC_EVT_TIMING_QUERY:
+		if (flag == ACPI_EC_COMMAND_COMPLETE)
+			acpi_ec_close_event(ec);
+
+		return;
+
+	case ACPI_EC_EVT_TIMING_EVENT:
+		if (flag == ACPI_EC_COMMAND_COMPLETE)
+			acpi_ec_complete_event(ec);
 	}
 }
 
-static void advance_transaction(struct acpi_ec *ec)
+static void acpi_ec_spurious_interrupt(struct acpi_ec *ec, struct transaction *t)
 {
-	struct transaction *t;
-	u8 status;
+	if (t->irq_count < ec_storm_threshold)
+		++t->irq_count;
+
+	/* Trigger if the threshold is 0 too. */
+	if (t->irq_count == ec_storm_threshold)
+		acpi_ec_mask_events(ec);
+}
+
+static void advance_transaction(struct acpi_ec *ec, bool interrupt)
+{
+	struct transaction *t = ec->curr;
 	bool wakeup = false;
+	u8 status;
 
-	ec_dbg_stm("%s (%d)", in_interrupt() ? "IRQ" : "TASK",
-		   smp_processor_id());
-	/*
-	 * By always clearing STS before handling all indications, we can
-	 * ensure a hardware STS 0->1 change after this clearing can always
-	 * trigger a GPE interrupt.
-	 */
-	if (ec->gpe >= 0)
-		acpi_ec_clear_gpe(ec);
+	ec_dbg_stm("%s (%d)", interrupt ? "IRQ" : "TASK", smp_processor_id());
 
 	status = acpi_ec_read_status(ec);
-	t = ec->curr;
+
 	/*
 	 * Another IRQ or a guarded polling mode advancement is detected,
 	 * the next QR_EC submission is then allowed.
 	 */
 	if (!t || !(t->flags & ACPI_EC_COMMAND_POLL)) {
 		if (ec_event_clearing == ACPI_EC_EVT_TIMING_EVENT &&
-		    (!ec->nr_pending_queries ||
-		     test_bit(EC_FLAGS_QUERY_GUARDING, &ec->flags))) {
-			clear_bit(EC_FLAGS_QUERY_GUARDING, &ec->flags);
-			acpi_ec_complete_query(ec);
-		}
+		    ec->event_state == EC_EVENT_COMPLETE)
+			acpi_ec_close_event(ec);
+
+		if (!t)
+			goto out;
 	}
-	if (!t)
-		goto err;
+
 	if (t->flags & ACPI_EC_COMMAND_POLL) {
 		if (t->wlen > t->wi) {
-			if ((status & ACPI_EC_FLAG_IBF) == 0)
+			if (!(status & ACPI_EC_FLAG_IBF))
 				acpi_ec_write_data(ec, t->wdata[t->wi++]);
-			else
-				goto err;
+			else if (interrupt && !(status & ACPI_EC_FLAG_SCI))
+				acpi_ec_spurious_interrupt(ec, t);
 		} else if (t->rlen > t->ri) {
-			if ((status & ACPI_EC_FLAG_OBF) == 1) {
+			if (status & ACPI_EC_FLAG_OBF) {
 				t->rdata[t->ri++] = acpi_ec_read_data(ec);
 				if (t->rlen == t->ri) {
 					ec_transaction_transition(ec, ACPI_EC_COMMAND_COMPLETE);
+					wakeup = true;
 					if (t->command == ACPI_EC_COMMAND_QUERY)
 						ec_dbg_evt("Command(%s) completed by hardware",
 							   acpi_ec_cmd_string(ACPI_EC_COMMAND_QUERY));
-					wakeup = true;
 				}
-			} else
-				goto err;
-		} else if (t->wlen == t->wi &&
-			   (status & ACPI_EC_FLAG_IBF) == 0) {
+			} else if (interrupt && !(status & ACPI_EC_FLAG_SCI)) {
+				acpi_ec_spurious_interrupt(ec, t);
+			}
+		} else if (t->wlen == t->wi && !(status & ACPI_EC_FLAG_IBF)) {
 			ec_transaction_transition(ec, ACPI_EC_COMMAND_COMPLETE);
 			wakeup = true;
 		}
-		goto out;
 	} else if (!(status & ACPI_EC_FLAG_IBF)) {
 		acpi_ec_write_cmd(ec, t->command);
 		ec_transaction_transition(ec, ACPI_EC_COMMAND_POLL);
-		goto out;
-	}
-err:
-	/*
-	 * If SCI bit is set, then don't think it's a false IRQ
-	 * otherwise will take a not handled IRQ as a false one.
-	 */
-	if (!(status & ACPI_EC_FLAG_SCI)) {
-		if (in_interrupt() && t) {
-			if (t->irq_count < ec_storm_threshold)
-				++t->irq_count;
-			/* Allow triggering on 0 threshold */
-			if (t->irq_count == ec_storm_threshold)
-				acpi_ec_mask_events(ec);
-		}
 	}
+
 out:
 	if (status & ACPI_EC_FLAG_SCI)
-		acpi_ec_submit_query(ec);
-	if (wakeup && in_interrupt())
+		acpi_ec_submit_event(ec);
+
+	if (wakeup && interrupt)
 		wake_up(&ec->wait);
 }
 
@@ -768,7 +768,7 @@ static int ec_poll(struct acpi_ec *ec)
 			if (!ec_guard(ec))
 				return 0;
 			spin_lock_irqsave(&ec->lock, flags);
-			advance_transaction(ec);
+			advance_transaction(ec, false);
 			spin_unlock_irqrestore(&ec->lock, flags);
 		} while (time_before(jiffies, delay));
 		pr_debug("controller reset, restart transaction\n");
@@ -785,6 +785,9 @@ static int acpi_ec_transaction_unlocked(struct acpi_ec *ec,
 	unsigned long tmp;
 	int ret = 0;
 
+	if (t->rdata)
+		memset(t->rdata, 0, t->rlen);
+
 	/* start transaction */
 	spin_lock_irqsave(&ec->lock, tmp);
 	/* Enable GPE for command processing (IBF=0/OBF=1) */
@@ -821,8 +824,6 @@ static int acpi_ec_transaction(struct acpi_ec *ec, struct transaction *t)
 
 	if (!ec || (!t) || (t->wlen && !t->wdata) || (t->rlen && !t->rdata))
 		return -EINVAL;
-	if (t->rdata)
-		memset(t->rdata, 0, t->rlen);
 
 	mutex_lock(&ec->mutex);
 	if (ec->global_lock) {
@@ -849,7 +850,7 @@ static int acpi_ec_burst_enable(struct acpi_ec *ec)
 				.wdata = NULL, .rdata = &d,
 				.wlen = 0, .rlen = 1};
 
-	return acpi_ec_transaction(ec, &t);
+	return acpi_ec_transaction_unlocked(ec, &t);
 }
 
 static int acpi_ec_burst_disable(struct acpi_ec *ec)
@@ -859,7 +860,7 @@ static int acpi_ec_burst_disable(struct acpi_ec *ec)
 				.wlen = 0, .rlen = 0};
 
 	return (acpi_ec_read_status(ec) & ACPI_EC_FLAG_BURST) ?
-				acpi_ec_transaction(ec, &t) : 0;
+				acpi_ec_transaction_unlocked(ec, &t) : 0;
 }
 
 static int acpi_ec_read(struct acpi_ec *ec, u8 address, u8 *data)
@@ -875,6 +876,19 @@ static int acpi_ec_read(struct acpi_ec *ec, u8 address, u8 *data)
 	return result;
 }
 
+static int acpi_ec_read_unlocked(struct acpi_ec *ec, u8 address, u8 *data)
+{
+	int result;
+	u8 d;
+	struct transaction t = {.command = ACPI_EC_COMMAND_READ,
+				.wdata = &address, .rdata = &d,
+				.wlen = 1, .rlen = 1};
+
+	result = acpi_ec_transaction_unlocked(ec, &t);
+	*data = d;
+	return result;
+}
+
 static int acpi_ec_write(struct acpi_ec *ec, u8 address, u8 data)
 {
 	u8 wdata[2] = { address, data };
@@ -885,6 +899,16 @@ static int acpi_ec_write(struct acpi_ec *ec, u8 address, u8 data)
 	return acpi_ec_transaction(ec, &t);
 }
 
+static int acpi_ec_write_unlocked(struct acpi_ec *ec, u8 address, u8 data)
+{
+	u8 wdata[2] = { address, data };
+	struct transaction t = {.command = ACPI_EC_COMMAND_WRITE,
+				.wdata = wdata, .rdata = NULL,
+				.wlen = 2, .rlen = 0};
+
+	return acpi_ec_transaction_unlocked(ec, &t);
+}
+
 int ec_read(u8 addr, u8 *val)
 {
 	int err;
@@ -905,14 +929,10 @@ EXPORT_SYMBOL(ec_read);
 
 int ec_write(u8 addr, u8 val)
 {
-	int err;
-
 	if (!first_ec)
 		return -ENODEV;
 
-	err = acpi_ec_write(first_ec, addr, val);
-
-	return err;
+	return acpi_ec_write(first_ec, addr, val);
 }
 EXPORT_SYMBOL(ec_write);
 
@@ -1074,9 +1094,12 @@ int acpi_ec_add_query_handler(struct acpi_ec *ec, u8 query_bit,
 			      acpi_handle handle, acpi_ec_query_func func,
 			      void *data)
 {
-	struct acpi_ec_query_handler *handler =
-	    kzalloc(sizeof(struct acpi_ec_query_handler), GFP_KERNEL);
+	struct acpi_ec_query_handler *handler;
+
+	if (!handle && !func)
+		return -EINVAL;
 
+	handler = kzalloc(sizeof(*handler), GFP_KERNEL);
 	if (!handler)
 		return -ENOMEM;
 
@@ -1088,6 +1111,7 @@ int acpi_ec_add_query_handler(struct acpi_ec *ec, u8 query_bit,
 	kref_init(&handler->kref);
 	list_add(&handler->node, &ec->list);
 	mutex_unlock(&ec->mutex);
+
 	return 0;
 }
 EXPORT_SYMBOL_GPL(acpi_ec_add_query_handler);
@@ -1100,9 +1124,16 @@ static void acpi_ec_remove_query_handlers(struct acpi_ec *ec,
 
 	mutex_lock(&ec->mutex);
 	list_for_each_entry_safe(handler, tmp, &ec->list, node) {
-		if (remove_all || query_bit == handler->query_bit) {
+		/*
+		 * When remove_all is false, only remove custom query handlers
+		 * which have handler->func set. This is done to preserve query
+		 * handlers discovered thru ACPI, as they should continue handling
+		 * EC queries.
+		 */
+		if (remove_all || (handler->func && handler->query_bit == query_bit)) {
 			list_del_init(&handler->node);
 			list_add(&handler->node, &free_list);
+
 		}
 	}
 	mutex_unlock(&ec->mutex);
@@ -1113,10 +1144,34 @@ static void acpi_ec_remove_query_handlers(struct acpi_ec *ec,
 void acpi_ec_remove_query_handler(struct acpi_ec *ec, u8 query_bit)
 {
 	acpi_ec_remove_query_handlers(ec, false, query_bit);
+	flush_workqueue(ec_query_wq);
 }
 EXPORT_SYMBOL_GPL(acpi_ec_remove_query_handler);
 
-static struct acpi_ec_query *acpi_ec_create_query(u8 *pval)
+static void acpi_ec_event_processor(struct work_struct *work)
+{
+	struct acpi_ec_query *q = container_of(work, struct acpi_ec_query, work);
+	struct acpi_ec_query_handler *handler = q->handler;
+	struct acpi_ec *ec = q->ec;
+
+	ec_dbg_evt("Query(0x%02x) started", handler->query_bit);
+
+	if (handler->func)
+		handler->func(handler->data);
+	else if (handler->handle)
+		acpi_evaluate_object(handler->handle, NULL, NULL, NULL);
+
+	ec_dbg_evt("Query(0x%02x) stopped", handler->query_bit);
+
+	spin_lock_irq(&ec->lock);
+	ec->queries_in_progress--;
+	spin_unlock_irq(&ec->lock);
+
+	acpi_ec_put_query_handler(handler);
+	kfree(q);
+}
+
+static struct acpi_ec_query *acpi_ec_create_query(struct acpi_ec *ec, u8 *pval)
 {
 	struct acpi_ec_query *q;
 	struct transaction *t;
@@ -1124,44 +1179,23 @@ static struct acpi_ec_query *acpi_ec_create_query(u8 *pval)
 	q = kzalloc(sizeof (struct acpi_ec_query), GFP_KERNEL);
 	if (!q)
 		return NULL;
+
 	INIT_WORK(&q->work, acpi_ec_event_processor);
 	t = &q->transaction;
 	t->command = ACPI_EC_COMMAND_QUERY;
 	t->rdata = pval;
 	t->rlen = 1;
+	q->ec = ec;
 	return q;
 }
 
-static void acpi_ec_delete_query(struct acpi_ec_query *q)
-{
-	if (q) {
-		if (q->handler)
-			acpi_ec_put_query_handler(q->handler);
-		kfree(q);
-	}
-}
-
-static void acpi_ec_event_processor(struct work_struct *work)
-{
-	struct acpi_ec_query *q = container_of(work, struct acpi_ec_query, work);
-	struct acpi_ec_query_handler *handler = q->handler;
-
-	ec_dbg_evt("Query(0x%02x) started", handler->query_bit);
-	if (handler->func)
-		handler->func(handler->data);
-	else if (handler->handle)
-		acpi_evaluate_object(handler->handle, NULL, NULL, NULL);
-	ec_dbg_evt("Query(0x%02x) stopped", handler->query_bit);
-	acpi_ec_delete_query(q);
-}
-
-static int acpi_ec_query(struct acpi_ec *ec, u8 *data)
+static int acpi_ec_submit_query(struct acpi_ec *ec)
 {
+	struct acpi_ec_query *q;
 	u8 value = 0;
 	int result;
-	struct acpi_ec_query *q;
 
-	q = acpi_ec_create_query(&value);
+	q = acpi_ec_create_query(ec, &value);
 	if (!q)
 		return -ENOMEM;
 
@@ -1171,11 +1205,14 @@ static int acpi_ec_query(struct acpi_ec *ec, u8 *data)
 	 * bit to be cleared (and thus clearing the interrupt source).
 	 */
 	result = acpi_ec_transaction(ec, &q->transaction);
-	if (!value)
-		result = -ENODATA;
 	if (result)
 		goto err_exit;
 
+	if (!value) {
+		result = -ENODATA;
+		goto err_exit;
+	}
+
 	q->handler = acpi_ec_get_query_handler_by_value(ec, value);
 	if (!q->handler) {
 		result = -ENODATA;
@@ -1183,76 +1220,97 @@ static int acpi_ec_query(struct acpi_ec *ec, u8 *data)
 	}
 
 	/*
-	 * It is reported that _Qxx are evaluated in a parallel way on
-	 * Windows:
+	 * It is reported that _Qxx are evaluated in a parallel way on Windows:
 	 * https://bugzilla.kernel.org/show_bug.cgi?id=94411
 	 *
-	 * Put this log entry before schedule_work() in order to make
-	 * it appearing before any other log entries occurred during the
-	 * work queue execution.
+	 * Put this log entry before queue_work() to make it appear in the log
+	 * before any other messages emitted during workqueue handling.
 	 */
 	ec_dbg_evt("Query(0x%02x) scheduled", value);
-	if (!queue_work(ec_query_wq, &q->work)) {
-		ec_dbg_evt("Query(0x%02x) overlapped", value);
-		result = -EBUSY;
-	}
 
-err_exit:
-	if (result)
-		acpi_ec_delete_query(q);
-	if (data)
-		*data = value;
-	return result;
-}
+	spin_lock_irq(&ec->lock);
 
-static void acpi_ec_check_event(struct acpi_ec *ec)
-{
-	unsigned long flags;
+	ec->queries_in_progress++;
+	queue_work(ec_query_wq, &q->work);
 
-	if (ec_event_clearing == ACPI_EC_EVT_TIMING_EVENT) {
-		if (ec_guard(ec)) {
-			spin_lock_irqsave(&ec->lock, flags);
-			/*
-			 * Take care of the SCI_EVT unless no one else is
-			 * taking care of it.
-			 */
-			if (!ec->curr)
-				advance_transaction(ec);
-			spin_unlock_irqrestore(&ec->lock, flags);
-		}
-	}
+	spin_unlock_irq(&ec->lock);
+
+	return 0;
+
+err_exit:
+	kfree(q);
+
+	return result;
 }
 
 static void acpi_ec_event_handler(struct work_struct *work)
 {
-	unsigned long flags;
 	struct acpi_ec *ec = container_of(work, struct acpi_ec, work);
 
 	ec_dbg_evt("Event started");
 
-	spin_lock_irqsave(&ec->lock, flags);
-	while (ec->nr_pending_queries) {
-		spin_unlock_irqrestore(&ec->lock, flags);
-		(void)acpi_ec_query(ec, NULL);
-		spin_lock_irqsave(&ec->lock, flags);
-		ec->nr_pending_queries--;
-		/*
-		 * Before exit, make sure that this work item can be
-		 * scheduled again. There might be QR_EC failures, leaving
-		 * EC_FLAGS_QUERY_PENDING uncleared and preventing this work
-		 * item from being scheduled again.
-		 */
-		if (!ec->nr_pending_queries) {
-			if (ec_event_clearing == ACPI_EC_EVT_TIMING_STATUS ||
-			    ec_event_clearing == ACPI_EC_EVT_TIMING_QUERY)
-				acpi_ec_complete_query(ec);
-		}
+	spin_lock_irq(&ec->lock);
+
+	while (ec->events_to_process) {
+		spin_unlock_irq(&ec->lock);
+
+		acpi_ec_submit_query(ec);
+
+		spin_lock_irq(&ec->lock);
+
+		ec->events_to_process--;
 	}
-	spin_unlock_irqrestore(&ec->lock, flags);
 
-	ec_dbg_evt("Event stopped");
+	/*
+	 * Before exit, make sure that the it will be possible to queue up the
+	 * event handling work again regardless of whether or not the query
+	 * queued up above is processed successfully.
+	 */
+	if (ec_event_clearing == ACPI_EC_EVT_TIMING_EVENT) {
+		bool guard_timeout;
+
+		acpi_ec_complete_event(ec);
+
+		ec_dbg_evt("Event stopped");
+
+		spin_unlock_irq(&ec->lock);
+
+		guard_timeout = !!ec_guard(ec);
+
+		spin_lock_irq(&ec->lock);
+
+		/* Take care of SCI_EVT unless someone else is doing that. */
+		if (guard_timeout && !ec->curr)
+			advance_transaction(ec, false);
+	} else {
+		acpi_ec_close_event(ec);
+
+		ec_dbg_evt("Event stopped");
+	}
+
+	ec->events_in_progress--;
+
+	spin_unlock_irq(&ec->lock);
+}
+
+static void clear_gpe_and_advance_transaction(struct acpi_ec *ec, bool interrupt)
+{
+	/*
+	 * Clear GPE_STS upfront to allow subsequent hardware GPE_STS 0->1
+	 * changes to always trigger a GPE interrupt.
+	 *
+	 * GPE STS is a W1C register, which means:
+	 *
+	 * 1. Software can clear it without worrying about clearing the other
+	 *    GPEs' STS bits when the hardware sets them in parallel.
+	 *
+	 * 2. As long as software can ensure only clearing it when it is set,
+	 *    hardware won't set it in parallel.
+	 */
+	if (ec->gpe >= 0 && acpi_ec_gpe_status_set(ec))
+		acpi_clear_gpe(NULL, ec->gpe);
 
-	acpi_ec_check_event(ec);
+	advance_transaction(ec, true);
 }
 
 static void acpi_ec_handle_interrupt(struct acpi_ec *ec)
@@ -1260,7 +1318,9 @@ static void acpi_ec_handle_interrupt(struct acpi_ec *ec)
 	unsigned long flags;
 
 	spin_lock_irqsave(&ec->lock, flags);
-	advance_transaction(ec);
+
+	clear_gpe_and_advance_transaction(ec, true);
+
 	spin_unlock_irqrestore(&ec->lock, flags);
 }
 
@@ -1289,6 +1349,7 @@ acpi_ec_space_handler(u32 function, acpi_physical_address address,
 	struct acpi_ec *ec = handler_context;
 	int result = 0, i, bytes = bits / 8;
 	u8 *value = (u8 *)value64;
+	u32 glk;
 
 	if ((address > 0xFF) || !value || !handler_context)
 		return AE_BAD_PARAMETER;
@@ -1296,17 +1357,38 @@ acpi_ec_space_handler(u32 function, acpi_physical_address address,
 	if (function != ACPI_READ && function != ACPI_WRITE)
 		return AE_BAD_PARAMETER;
 
+	mutex_lock(&ec->mutex);
+
+	if (ec->global_lock) {
+		acpi_status status;
+
+		status = acpi_acquire_global_lock(ACPI_EC_UDELAY_GLK, &glk);
+		if (ACPI_FAILURE(status)) {
+			result = -ENODEV;
+			goto unlock;
+		}
+	}
+
 	if (ec->busy_polling || bits > 8)
 		acpi_ec_burst_enable(ec);
 
-	for (i = 0; i < bytes; ++i, ++address, ++value)
+	for (i = 0; i < bytes; ++i, ++address, ++value) {
 		result = (function == ACPI_READ) ?
-			acpi_ec_read(ec, address, value) :
-			acpi_ec_write(ec, address, *value);
+			acpi_ec_read_unlocked(ec, address, value) :
+			acpi_ec_write_unlocked(ec, address, *value);
+		if (result < 0)
+			break;
+	}
 
 	if (ec->busy_polling || bits > 8)
 		acpi_ec_burst_disable(ec);
 
+	if (ec->global_lock)
+		acpi_release_global_lock(glk);
+
+unlock:
+	mutex_unlock(&ec->mutex);
+
 	switch (result) {
 	case -EINVAL:
 		return AE_BAD_PARAMETER;
@@ -1314,8 +1396,10 @@ acpi_ec_space_handler(u32 function, acpi_physical_address address,
 		return AE_NOT_FOUND;
 	case -ETIME:
 		return AE_TIME;
-	default:
+	case 0:
 		return AE_OK;
+	default:
+		return AE_ERROR;
 	}
 }
 
@@ -1388,24 +1472,16 @@ ec_parse_device(acpi_handle handle, u32 Level, void *context, void **retval)
 	if (ec->data_addr == 0 || ec->command_addr == 0)
 		return AE_OK;
 
-	if (boot_ec && boot_ec_is_ecdt && EC_FLAGS_IGNORE_DSDT_GPE) {
-		/*
-		 * Always inherit the GPE number setting from the ECDT
-		 * EC.
-		 */
-		ec->gpe = boot_ec->gpe;
-	} else {
-		/* Get GPE bit assignment (EC events). */
-		/* TODO: Add support for _GPE returning a package */
-		status = acpi_evaluate_integer(handle, "_GPE", NULL, &tmp);
-		if (ACPI_SUCCESS(status))
-			ec->gpe = tmp;
+	/* Get GPE bit assignment (EC events). */
+	/* TODO: Add support for _GPE returning a package */
+	status = acpi_evaluate_integer(handle, "_GPE", NULL, &tmp);
+	if (ACPI_SUCCESS(status))
+		ec->gpe = tmp;
+	/*
+	 * Errors are non-fatal, allowing for ACPI Reduced Hardware
+	 * platforms which use GpioInt instead of GPE.
+	 */
 
-		/*
-		 * Errors are non-fatal, allowing for ACPI Reduced Hardware
-		 * platforms which use GpioInt instead of GPE.
-		 */
-	}
 	/* Use the global lock for all EC transactions? */
 	tmp = 0;
 	acpi_evaluate_integer(handle, "_GLK", NULL, &tmp);
@@ -1432,14 +1508,15 @@ static bool install_gpe_event_handler(struct acpi_ec *ec)
 
 static bool install_gpio_irq_event_handler(struct acpi_ec *ec)
 {
-	return request_irq(ec->irq, acpi_ec_irq_handler, IRQF_SHARED,
-			   "ACPI EC", ec) >= 0;
+	return request_threaded_irq(ec->irq, NULL, acpi_ec_irq_handler,
+				    IRQF_SHARED | IRQF_ONESHOT, "ACPI EC", ec) >= 0;
 }
 
 /**
  * ec_install_handlers - Install service callbacks and register query methods.
  * @ec: Target EC.
  * @device: ACPI device object corresponding to @ec.
+ * @call_reg: If _REG should be called to notify OpRegion availability
  *
  * Install a handler for the EC address space type unless it has been installed
  * already.  If @device is not NULL, also look for EC query methods in the
@@ -1452,18 +1529,21 @@ static bool install_gpio_irq_event_handler(struct acpi_ec *ec)
  * -EPROBE_DEFER if GPIO IRQ acquisition needs to be deferred,
  * or 0 (success) otherwise.
  */
-static int ec_install_handlers(struct acpi_ec *ec, struct acpi_device *device)
+static int ec_install_handlers(struct acpi_ec *ec, struct acpi_device *device,
+			       bool call_reg)
 {
 	acpi_status status;
 
 	acpi_ec_start(ec, false);
 
 	if (!test_bit(EC_FLAGS_EC_HANDLER_INSTALLED, &ec->flags)) {
+		acpi_handle scope_handle = ec == first_ec ? ACPI_ROOT_OBJECT : ec->handle;
+
 		acpi_ec_enter_noirq(ec);
-		status = acpi_install_address_space_handler(ec->handle,
-							    ACPI_ADR_SPACE_EC,
-							    &acpi_ec_space_handler,
-							    NULL, ec);
+		status = acpi_install_address_space_handler_no_reg(scope_handle,
+								   ACPI_ADR_SPACE_EC,
+								   &acpi_ec_space_handler,
+								   NULL, ec);
 		if (ACPI_FAILURE(status)) {
 			acpi_ec_stop(ec, false);
 			return -ENODEV;
@@ -1471,6 +1551,11 @@ static int ec_install_handlers(struct acpi_ec *ec, struct acpi_device *device)
 		set_bit(EC_FLAGS_EC_HANDLER_INSTALLED, &ec->flags);
 	}
 
+	if (call_reg && !test_bit(EC_FLAGS_EC_REG_CALLED, &ec->flags)) {
+		acpi_execute_reg_methods(ec->handle, ACPI_UINT32_MAX, ACPI_ADR_SPACE_EC);
+		set_bit(EC_FLAGS_EC_REG_CALLED, &ec->flags);
+	}
+
 	if (!device)
 		return 0;
 
@@ -1519,9 +1604,13 @@ static int ec_install_handlers(struct acpi_ec *ec, struct acpi_device *device)
 
 static void ec_remove_handlers(struct acpi_ec *ec)
 {
+	acpi_handle scope_handle = ec == first_ec ? ACPI_ROOT_OBJECT : ec->handle;
+
 	if (test_bit(EC_FLAGS_EC_HANDLER_INSTALLED, &ec->flags)) {
-		if (ACPI_FAILURE(acpi_remove_address_space_handler(ec->handle,
-					ACPI_ADR_SPACE_EC, &acpi_ec_space_handler)))
+		if (ACPI_FAILURE(acpi_remove_address_space_handler(
+						scope_handle,
+						ACPI_ADR_SPACE_EC,
+						&acpi_ec_space_handler)))
 			pr_err("failed to remove space handler\n");
 		clear_bit(EC_FLAGS_EC_HANDLER_INSTALLED, &ec->flags);
 	}
@@ -1556,18 +1645,22 @@ static void ec_remove_handlers(struct acpi_ec *ec)
 	}
 }
 
-static int acpi_ec_setup(struct acpi_ec *ec, struct acpi_device *device)
+static int acpi_ec_setup(struct acpi_ec *ec, struct acpi_device *device, bool call_reg)
 {
 	int ret;
 
-	ret = ec_install_handlers(ec, device);
-	if (ret)
-		return ret;
-
 	/* First EC capable of handling transactions */
 	if (!first_ec)
 		first_ec = ec;
 
+	ret = ec_install_handlers(ec, device, call_reg);
+	if (ret) {
+		if (ec == first_ec)
+			first_ec = NULL;
+
+		return ret;
+	}
+
 	pr_info("EC_CMD/EC_SC=0x%lx, EC_DATA=0x%lx\n", ec->command_addr,
 		ec->data_addr);
 
@@ -1586,8 +1679,8 @@ static int acpi_ec_add(struct acpi_device *device)
 	struct acpi_ec *ec;
 	int ret;
 
-	strcpy(acpi_device_name(device), ACPI_EC_DEVICE_NAME);
-	strcpy(acpi_device_class(device), ACPI_EC_CLASS);
+	strscpy(acpi_device_name(device), ACPI_EC_DEVICE_NAME);
+	strscpy(acpi_device_class(device), ACPI_EC_CLASS);
 
 	if (boot_ec && (boot_ec->handle == device->handle ||
 	    !strcmp(acpi_device_hid(device), ACPI_ECDT_HID))) {
@@ -1609,19 +1702,23 @@ static int acpi_ec_add(struct acpi_device *device)
 		if (boot_ec && ec->command_addr == boot_ec->command_addr &&
 		    ec->data_addr == boot_ec->data_addr) {
 			/*
-			 * Trust PNP0C09 namespace location rather than
-			 * ECDT ID. But trust ECDT GPE rather than _GPE
-			 * because of ASUS quirks, so do not change
-			 * boot_ec->gpe to ec->gpe.
+			 * Trust PNP0C09 namespace location rather than ECDT ID.
+			 * But trust ECDT GPE rather than _GPE because of ASUS
+			 * quirks. So do not change boot_ec->gpe to ec->gpe,
+			 * except when the TRUST_DSDT_GPE quirk is set.
 			 */
 			boot_ec->handle = ec->handle;
+
+			if (EC_FLAGS_TRUST_DSDT_GPE)
+				boot_ec->gpe = ec->gpe;
+
 			acpi_handle_debug(ec->handle, "duplicated.\n");
 			acpi_ec_free(ec);
 			ec = boot_ec;
 		}
 	}
 
-	ret = acpi_ec_setup(ec, device);
+	ret = acpi_ec_setup(ec, device, true);
 	if (ret)
 		goto err;
 
@@ -1641,7 +1738,7 @@ static int acpi_ec_add(struct acpi_device *device)
 	WARN(!ret, "Could not request EC cmd io port 0x%lx", ec->command_addr);
 
 	/* Reprobe devices depending on the EC */
-	acpi_walk_dep_device_list(ec->handle);
+	acpi_dev_clear_dependencies(device);
 
 	acpi_handle_debug(ec->handle, "enumerated.\n");
 	return 0;
@@ -1653,12 +1750,12 @@ err:
 	return ret;
 }
 
-static int acpi_ec_remove(struct acpi_device *device)
+static void acpi_ec_remove(struct acpi_device *device)
 {
 	struct acpi_ec *ec;
 
 	if (!device)
-		return -EINVAL;
+		return;
 
 	ec = acpi_driver_data(device);
 	release_region(ec->data_addr, 1);
@@ -1668,7 +1765,12 @@ static int acpi_ec_remove(struct acpi_device *device)
 		ec_remove_handlers(ec);
 		acpi_ec_free(ec);
 	}
-	return 0;
+}
+
+void acpi_ec_register_opregions(struct acpi_device *adev)
+{
+	if (first_ec && first_ec->handle != adev->handle)
+		acpi_execute_reg_methods(adev->handle, 1, ACPI_ADR_SPACE_EC);
 }
 
 static acpi_status
@@ -1741,7 +1843,7 @@ void __init acpi_ec_dsdt_probe(void)
 	 * At this point, the GPE is not fully initialized, so do not to
 	 * handle the events.
 	 */
-	ret = acpi_ec_setup(ec, NULL);
+	ret = acpi_ec_setup(ec, NULL, true);
 	if (ret) {
 		acpi_ec_free(ec);
 		return;
@@ -1783,13 +1885,14 @@ static void __init acpi_ec_ecdt_start(void)
 		return;
 
 	status = acpi_get_handle(NULL, ecdt_ptr->id, &handle);
-	if (ACPI_FAILURE(status))
-		return;
+	if (ACPI_SUCCESS(status)) {
+		boot_ec->handle = handle;
 
-	boot_ec->handle = handle;
+		/* Add a special ACPI device object to represent the boot EC. */
+		acpi_bus_register_early_device(ACPI_BUS_TYPE_ECDT_EC);
+	}
 
-	/* Add a special ACPI device object to represent the boot EC. */
-	acpi_bus_register_early_device(ACPI_BUS_TYPE_ECDT_EC);
+	acpi_put_table((struct acpi_table_header *)ecdt_ptr);
 }
 
 /*
@@ -1830,46 +1933,82 @@ static int ec_correct_ecdt(const struct dmi_system_id *id)
 }
 
 /*
- * Some DSDTs contain wrong GPE setting.
- * Asus FX502VD/VE, GL702VMK, X550VXK, X580VD
- * https://bugzilla.kernel.org/show_bug.cgi?id=195651
+ * Some ECDTs contain wrong GPE setting, but they share the same port addresses
+ * with DSDT EC, don't duplicate the DSDT EC with ECDT EC in this case.
+ * https://bugzilla.kernel.org/show_bug.cgi?id=209989
  */
-static int ec_honor_ecdt_gpe(const struct dmi_system_id *id)
+static int ec_honor_dsdt_gpe(const struct dmi_system_id *id)
 {
-	pr_debug("Detected system needing ignore DSDT GPE setting.\n");
-	EC_FLAGS_IGNORE_DSDT_GPE = 1;
+	pr_debug("Detected system needing DSDT GPE setting.\n");
+	EC_FLAGS_TRUST_DSDT_GPE = 1;
 	return 0;
 }
 
 static const struct dmi_system_id ec_dmi_table[] __initconst = {
 	{
-	ec_correct_ecdt, "MSI MS-171F", {
-	DMI_MATCH(DMI_SYS_VENDOR, "Micro-Star"),
-	DMI_MATCH(DMI_PRODUCT_NAME, "MS-171F"),}, NULL},
-	{
-	ec_honor_ecdt_gpe, "ASUS FX502VD", {
-	DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
-	DMI_MATCH(DMI_PRODUCT_NAME, "FX502VD"),}, NULL},
+		/*
+		 * MSI MS-171F
+		 * https://bugzilla.kernel.org/show_bug.cgi?id=12461
+		 */
+		.callback = ec_correct_ecdt,
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "Micro-Star"),
+			DMI_MATCH(DMI_PRODUCT_NAME, "MS-171F"),
+		},
+	},
 	{
-	ec_honor_ecdt_gpe, "ASUS FX502VE", {
-	DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
-	DMI_MATCH(DMI_PRODUCT_NAME, "FX502VE"),}, NULL},
+		/*
+		 * HP Pavilion Gaming Laptop 15-cx0xxx
+		 * https://bugzilla.kernel.org/show_bug.cgi?id=209989
+		 */
+		.callback = ec_honor_dsdt_gpe,
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
+			DMI_MATCH(DMI_PRODUCT_NAME, "HP Pavilion Gaming Laptop 15-cx0xxx"),
+		},
+	},
 	{
-	ec_honor_ecdt_gpe, "ASUS GL702VMK", {
-	DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
-	DMI_MATCH(DMI_PRODUCT_NAME, "GL702VMK"),}, NULL},
+		/*
+		 * HP Pavilion Gaming Laptop 15-cx0041ur
+		 */
+		.callback = ec_honor_dsdt_gpe,
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
+			DMI_MATCH(DMI_PRODUCT_NAME, "HP 15-cx0041ur"),
+		},
+	},
 	{
-	ec_honor_ecdt_gpe, "ASUS X550VXK", {
-	DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
-	DMI_MATCH(DMI_PRODUCT_NAME, "X550VXK"),}, NULL},
+		/*
+		 * HP Pavilion Gaming Laptop 15-dk1xxx
+		 * https://github.com/systemd/systemd/issues/28942
+		 */
+		.callback = ec_honor_dsdt_gpe,
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
+			DMI_MATCH(DMI_PRODUCT_NAME, "HP Pavilion Gaming Laptop 15-dk1xxx"),
+		},
+	},
 	{
-	ec_honor_ecdt_gpe, "ASUS X580VD", {
-	DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
-	DMI_MATCH(DMI_PRODUCT_NAME, "X580VD"),}, NULL},
+		/*
+		 * HP 250 G7 Notebook PC
+		 */
+		.callback = ec_honor_dsdt_gpe,
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
+			DMI_MATCH(DMI_PRODUCT_NAME, "HP 250 G7 Notebook PC"),
+		},
+	},
 	{
-	ec_clear_on_resume, "Samsung hardware", {
-	DMI_MATCH(DMI_SYS_VENDOR, "SAMSUNG ELECTRONICS CO., LTD.")}, NULL},
-	{},
+		/*
+		 * Samsung hardware
+		 * https://bugzilla.kernel.org/show_bug.cgi?id=44161
+		 */
+		.callback = ec_clear_on_resume,
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "SAMSUNG ELECTRONICS CO., LTD."),
+		},
+	},
+	{}
 };
 
 void __init acpi_ec_ecdt_probe(void)
@@ -1891,12 +2030,31 @@ void __init acpi_ec_ecdt_probe(void)
 		 * Asus X50GL:
 		 * https://bugzilla.kernel.org/show_bug.cgi?id=11880
 		 */
-		return;
+		goto out;
+	}
+
+	if (!strlen(ecdt_ptr->id)) {
+		/*
+		 * The ECDT table on some MSI notebooks contains invalid data, together
+		 * with an empty ID string ("").
+		 *
+		 * Section 5.2.15 of the ACPI specification requires the ID string to be
+		 * a "fully qualified reference to the (...) embedded controller device",
+		 * so this string always has to start with a backslash.
+		 *
+		 * However some ThinkBook machines have a ECDT table with a valid EC
+		 * description but an invalid ID string ("_SB.PC00.LPCB.EC0").
+		 *
+		 * Because of this we only check if the ID string is empty in order to
+		 * avoid the obvious cases.
+		 */
+		pr_err(FW_BUG "Ignoring ECDT due to empty ID string\n");
+		goto out;
 	}
 
 	ec = acpi_ec_alloc();
 	if (!ec)
-		return;
+		goto out;
 
 	if (EC_FLAGS_CORRECT_ECDT) {
 		ec->command_addr = ecdt_ptr->data.address;
@@ -1919,16 +2077,19 @@ void __init acpi_ec_ecdt_probe(void)
 	 * At this point, the namespace is not initialized, so do not find
 	 * the namespace objects, or handle the events.
 	 */
-	ret = acpi_ec_setup(ec, NULL);
+	ret = acpi_ec_setup(ec, NULL, false);
 	if (ret) {
 		acpi_ec_free(ec);
-		return;
+		goto out;
 	}
 
 	boot_ec = ec;
 	boot_ec_is_ecdt = true;
 
 	pr_info("Boot ECDT EC used to handle transactions\n");
+
+out:
+	acpi_put_table((struct acpi_table_header *)ecdt_ptr);
 }
 
 #ifdef CONFIG_PM_SLEEP
@@ -1994,23 +2155,68 @@ void acpi_ec_set_gpe_wake_mask(u8 action)
 		acpi_set_gpe_wake_mask(NULL, first_ec->gpe, action);
 }
 
-bool acpi_ec_other_gpes_active(void)
+static bool acpi_ec_work_in_progress(struct acpi_ec *ec)
 {
-	return acpi_any_gpe_status_set(first_ec ? first_ec->gpe : U32_MAX);
+	return ec->events_in_progress + ec->queries_in_progress > 0;
 }
 
 bool acpi_ec_dispatch_gpe(void)
 {
-	u32 ret;
+	bool work_in_progress = false;
 
 	if (!first_ec)
-		return false;
+		return acpi_any_gpe_status_set(U32_MAX);
 
-	ret = acpi_dispatch_gpe(NULL, first_ec->gpe);
-	if (ret == ACPI_INTERRUPT_HANDLED) {
-		pm_pr_dbg("EC GPE dispatched\n");
+	/*
+	 * Report wakeup if the status bit is set for any enabled GPE other
+	 * than the EC one.
+	 */
+	if (acpi_any_gpe_status_set(first_ec->gpe))
 		return true;
+
+	/*
+	 * Cancel the SCI wakeup and process all pending events in case there
+	 * are any wakeup ones in there.
+	 *
+	 * Note that if any non-EC GPEs are active at this point, the SCI will
+	 * retrigger after the rearming in acpi_s2idle_wake(), so no events
+	 * should be missed by canceling the wakeup here.
+	 */
+	pm_system_cancel_wakeup();
+
+	/*
+	 * Dispatch the EC GPE in-band, but do not report wakeup in any case
+	 * to allow the caller to process events properly after that.
+	 */
+	spin_lock_irq(&first_ec->lock);
+
+	if (acpi_ec_gpe_status_set(first_ec)) {
+		pm_pr_dbg("ACPI EC GPE status set\n");
+
+		clear_gpe_and_advance_transaction(first_ec, false);
+		work_in_progress = acpi_ec_work_in_progress(first_ec);
 	}
+
+	spin_unlock_irq(&first_ec->lock);
+
+	if (!work_in_progress)
+		return false;
+
+	pm_pr_dbg("ACPI EC GPE dispatched\n");
+
+	/* Drain EC work. */
+	do {
+		acpi_ec_flush_work();
+
+		pm_pr_dbg("ACPI EC work flushed\n");
+
+		spin_lock_irq(&first_ec->lock);
+
+		work_in_progress = acpi_ec_work_in_progress(first_ec);
+
+		spin_unlock_irq(&first_ec->lock);
+	} while (work_in_progress && !pm_wakeup_pending());
+
 	return false;
 }
 #endif /* CONFIG_PM_SLEEP */
@@ -2044,13 +2250,13 @@ static int param_get_event_clearing(char *buffer,
 {
 	switch (ec_event_clearing) {
 	case ACPI_EC_EVT_TIMING_STATUS:
-		return sprintf(buffer, "status");
+		return sprintf(buffer, "status\n");
 	case ACPI_EC_EVT_TIMING_QUERY:
-		return sprintf(buffer, "query");
+		return sprintf(buffer, "query\n");
 	case ACPI_EC_EVT_TIMING_EVENT:
-		return sprintf(buffer, "event");
+		return sprintf(buffer, "event\n");
 	default:
-		return sprintf(buffer, "invalid");
+		return sprintf(buffer, "invalid\n");
 	}
 	return 0;
 }
@@ -2088,7 +2294,8 @@ static int acpi_ec_init_workqueues(void)
 		ec_wq = alloc_ordered_workqueue("kec", 0);
 
 	if (!ec_query_wq)
-		ec_query_wq = alloc_workqueue("kec_query", 0, ec_max_queries);
+		ec_query_wq = alloc_workqueue("kec_query", WQ_PERCPU,
+					      ec_max_queries);
 
 	if (!ec_wq || !ec_query_wq) {
 		acpi_ec_destroy_workqueues();
@@ -2099,24 +2306,55 @@ static int acpi_ec_init_workqueues(void)
 
 static const struct dmi_system_id acpi_ec_no_wakeup[] = {
 	{
-		.ident = "Thinkpad X1 Carbon 6th",
 		.matches = {
 			DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
 			DMI_MATCH(DMI_PRODUCT_FAMILY, "Thinkpad X1 Carbon 6th"),
 		},
 	},
 	{
-		.ident = "ThinkPad X1 Carbon 6th",
 		.matches = {
 			DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
-			DMI_MATCH(DMI_PRODUCT_FAMILY, "ThinkPad X1 Carbon 6th"),
+			DMI_MATCH(DMI_PRODUCT_FAMILY, "ThinkPad X1 Yoga 3rd"),
 		},
 	},
 	{
-		.ident = "ThinkPad X1 Yoga 3rd",
 		.matches = {
-			DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
-			DMI_MATCH(DMI_PRODUCT_FAMILY, "ThinkPad X1 Yoga 3rd"),
+			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
+			DMI_MATCH(DMI_PRODUCT_FAMILY, "103C_5336AN HP ZHAN 66 Pro"),
+		},
+	},
+	/*
+	 * Lenovo Legion Go S; touchscreen blocks HW sleep when woken up from EC
+	 * https://gitlab.freedesktop.org/drm/amd/-/issues/3929
+	 */
+	{
+		.matches = {
+			DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
+			DMI_MATCH(DMI_PRODUCT_NAME, "83L3"),
+		}
+	},
+	{
+		.matches = {
+			DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
+			DMI_MATCH(DMI_PRODUCT_NAME, "83N6"),
+		}
+	},
+	{
+		.matches = {
+			DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
+			DMI_MATCH(DMI_PRODUCT_NAME, "83Q2"),
+		}
+	},
+	{
+		.matches = {
+			DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
+			DMI_MATCH(DMI_PRODUCT_NAME, "83Q3"),
+		}
+	},
+	{
+		// TUXEDO InfinityBook Pro AMD Gen9
+		.matches = {
+			DMI_MATCH(DMI_BOARD_NAME, "GXxHRXx"),
 		},
 	},
 	{ },
diff --git a/drivers/acpi/ec_sys.c b/drivers/acpi/ec_sys.c
index fd39c14493ab..c074a0fae059 100644
--- a/drivers/acpi/ec_sys.c
+++ b/drivers/acpi/ec_sys.c
@@ -19,7 +19,7 @@ MODULE_DESCRIPTION("ACPI EC sysfs access driver");
 MODULE_LICENSE("GPL");
 
 static bool write_support;
-module_param(write_support, bool, 0644);
+module_param_hw(write_support, bool, other, 0644);
 MODULE_PARM_DESC(write_support, "Dangerous, reboot and removal of battery may "
 		 "be needed.");
 
diff --git a/drivers/acpi/event.c b/drivers/acpi/event.c
index 47f21599f2ab..96a9aaaaf9f7 100644
--- a/drivers/acpi/event.c
+++ b/drivers/acpi/event.c
@@ -7,6 +7,8 @@
  *
  */
 
+#define pr_fmt(fmt) "ACPI: " fmt
+
 #include <linux/spinlock.h>
 #include <linux/export.h>
 #include <linux/proc_fs.h>
@@ -19,9 +21,6 @@
 
 #include "internal.h"
 
-#define _COMPONENT		ACPI_SYSTEM_COMPONENT
-ACPI_MODULE_NAME("event");
-
 /* ACPI notifier chain */
 static BLOCKING_NOTIFIER_HEAD(acpi_chain_head);
 
@@ -29,12 +28,12 @@ int acpi_notifier_call_chain(struct acpi_device *dev, u32 type, u32 data)
 {
 	struct acpi_bus_event event;
 
-	strcpy(event.device_class, dev->pnp.device_class);
-	strcpy(event.bus_id, dev->pnp.bus_id);
+	strscpy(event.device_class, dev->pnp.device_class);
+	strscpy(event.bus_id, dev->pnp.bus_id);
 	event.type = type;
 	event.data = data;
 	return (blocking_notifier_call_chain(&acpi_chain_head, 0, (void *)&event)
-                        == NOTIFY_BAD) ? -EINVAL : 0;
+			== NOTIFY_BAD) ? -EINVAL : 0;
 }
 EXPORT_SYMBOL(acpi_notifier_call_chain);
 
@@ -168,7 +167,7 @@ static int acpi_event_genetlink_init(void)
 
 static int __init acpi_event_init(void)
 {
-	int error = 0;
+	int error;
 
 	if (acpi_disabled)
 		return 0;
@@ -176,8 +175,8 @@ static int __init acpi_event_init(void)
 	/* create genetlink for acpi event */
 	error = acpi_event_genetlink_init();
 	if (error)
-		printk(KERN_WARNING PREFIX
-		       "Failed to create genetlink family for ACPI event\n");
+		pr_warn("Failed to create genetlink family for ACPI event\n");
+
 	return 0;
 }
 
diff --git a/drivers/acpi/evged.c b/drivers/acpi/evged.c
index aba0d0027586..5c35cbc7f6ff 100644
--- a/drivers/acpi/evged.c
+++ b/drivers/acpi/evged.c
@@ -79,6 +79,8 @@ static acpi_status acpi_ged_request_interrupt(struct acpi_resource *ares,
 	struct resource r;
 	struct acpi_resource_irq *p = &ares->data.irq;
 	struct acpi_resource_extended_irq *pext = &ares->data.extended_irq;
+	char ev_name[5];
+	u8 trigger;
 
 	if (ares->type == ACPI_RESOURCE_TYPE_END_TAG)
 		return AE_OK;
@@ -87,14 +89,28 @@ static acpi_status acpi_ged_request_interrupt(struct acpi_resource *ares,
 		dev_err(dev, "unable to parse IRQ resource\n");
 		return AE_ERROR;
 	}
-	if (ares->type == ACPI_RESOURCE_TYPE_IRQ)
+	if (ares->type == ACPI_RESOURCE_TYPE_IRQ) {
 		gsi = p->interrupts[0];
-	else
+		trigger = p->triggering;
+	} else {
 		gsi = pext->interrupts[0];
+		trigger = pext->triggering;
+	}
 
 	irq = r.start;
 
-	if (ACPI_FAILURE(acpi_get_handle(handle, "_EVT", &evt_handle))) {
+	switch (gsi) {
+	case 0 ... 255:
+		sprintf(ev_name, "_%c%02X",
+			trigger == ACPI_EDGE_SENSITIVE ? 'E' : 'L', gsi);
+
+		if (ACPI_SUCCESS(acpi_get_handle(handle, ev_name, &evt_handle)))
+			break;
+		fallthrough;
+	default:
+		if (ACPI_SUCCESS(acpi_get_handle(handle, "_EVT", &evt_handle)))
+			break;
+
 		dev_err(dev, "cannot locate _EVT method\n");
 		return AE_ERROR;
 	}
@@ -157,10 +173,9 @@ static void ged_shutdown(struct platform_device *pdev)
 	}
 }
 
-static int ged_remove(struct platform_device *pdev)
+static void ged_remove(struct platform_device *pdev)
 {
 	ged_shutdown(pdev);
-	return 0;
 }
 
 static const struct acpi_device_id ged_acpi_ids[] = {
diff --git a/drivers/acpi/fan.c b/drivers/acpi/fan.c
deleted file mode 100644
index 873e039ad4b7..000000000000
--- a/drivers/acpi/fan.c
+++ /dev/null
@@ -1,495 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- *  acpi_fan.c - ACPI Fan Driver ($Revision: 29 $)
- *
- *  Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com>
- *  Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/uaccess.h>
-#include <linux/thermal.h>
-#include <linux/acpi.h>
-#include <linux/platform_device.h>
-#include <linux/sort.h>
-
-MODULE_AUTHOR("Paul Diefenbaugh");
-MODULE_DESCRIPTION("ACPI Fan Driver");
-MODULE_LICENSE("GPL");
-
-static int acpi_fan_probe(struct platform_device *pdev);
-static int acpi_fan_remove(struct platform_device *pdev);
-
-static const struct acpi_device_id fan_device_ids[] = {
-	{"PNP0C0B", 0},
-	{"INT1044", 0},
-	{"INT3404", 0},
-	{"", 0},
-};
-MODULE_DEVICE_TABLE(acpi, fan_device_ids);
-
-#ifdef CONFIG_PM_SLEEP
-static int acpi_fan_suspend(struct device *dev);
-static int acpi_fan_resume(struct device *dev);
-static const struct dev_pm_ops acpi_fan_pm = {
-	.resume = acpi_fan_resume,
-	.freeze = acpi_fan_suspend,
-	.thaw = acpi_fan_resume,
-	.restore = acpi_fan_resume,
-};
-#define FAN_PM_OPS_PTR (&acpi_fan_pm)
-#else
-#define FAN_PM_OPS_PTR NULL
-#endif
-
-#define ACPI_FPS_NAME_LEN	20
-
-struct acpi_fan_fps {
-	u64 control;
-	u64 trip_point;
-	u64 speed;
-	u64 noise_level;
-	u64 power;
-	char name[ACPI_FPS_NAME_LEN];
-	struct device_attribute dev_attr;
-};
-
-struct acpi_fan_fif {
-	u64 revision;
-	u64 fine_grain_ctrl;
-	u64 step_size;
-	u64 low_speed_notification;
-};
-
-struct acpi_fan {
-	bool acpi4;
-	struct acpi_fan_fif fif;
-	struct acpi_fan_fps *fps;
-	int fps_count;
-	struct thermal_cooling_device *cdev;
-};
-
-static struct platform_driver acpi_fan_driver = {
-	.probe = acpi_fan_probe,
-	.remove = acpi_fan_remove,
-	.driver = {
-		.name = "acpi-fan",
-		.acpi_match_table = fan_device_ids,
-		.pm = FAN_PM_OPS_PTR,
-	},
-};
-
-/* thermal cooling device callbacks */
-static int fan_get_max_state(struct thermal_cooling_device *cdev, unsigned long
-			     *state)
-{
-	struct acpi_device *device = cdev->devdata;
-	struct acpi_fan *fan = acpi_driver_data(device);
-
-	if (fan->acpi4)
-		*state = fan->fps_count - 1;
-	else
-		*state = 1;
-	return 0;
-}
-
-static int fan_get_state_acpi4(struct acpi_device *device, unsigned long *state)
-{
-	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
-	struct acpi_fan *fan = acpi_driver_data(device);
-	union acpi_object *obj;
-	acpi_status status;
-	int control, i;
-
-	status = acpi_evaluate_object(device->handle, "_FST", NULL, &buffer);
-	if (ACPI_FAILURE(status)) {
-		dev_err(&device->dev, "Get fan state failed\n");
-		return status;
-	}
-
-	obj = buffer.pointer;
-	if (!obj || obj->type != ACPI_TYPE_PACKAGE ||
-	    obj->package.count != 3 ||
-	    obj->package.elements[1].type != ACPI_TYPE_INTEGER) {
-		dev_err(&device->dev, "Invalid _FST data\n");
-		status = -EINVAL;
-		goto err;
-	}
-
-	control = obj->package.elements[1].integer.value;
-	for (i = 0; i < fan->fps_count; i++) {
-		/*
-		 * When Fine Grain Control is set, return the state
-		 * corresponding to maximum fan->fps[i].control
-		 * value compared to the current speed. Here the
-		 * fan->fps[] is sorted array with increasing speed.
-		 */
-		if (fan->fif.fine_grain_ctrl && control < fan->fps[i].control) {
-			i = (i > 0) ? i - 1 : 0;
-			break;
-		} else if (control == fan->fps[i].control) {
-			break;
-		}
-	}
-	if (i == fan->fps_count) {
-		dev_dbg(&device->dev, "Invalid control value returned\n");
-		status = -EINVAL;
-		goto err;
-	}
-
-	*state = i;
-
-err:
-	kfree(obj);
-	return status;
-}
-
-static int fan_get_state(struct acpi_device *device, unsigned long *state)
-{
-	int result;
-	int acpi_state = ACPI_STATE_D0;
-
-	result = acpi_device_update_power(device, &acpi_state);
-	if (result)
-		return result;
-
-	*state = acpi_state == ACPI_STATE_D3_COLD
-			|| acpi_state == ACPI_STATE_D3_HOT ?
-		0 : (acpi_state == ACPI_STATE_D0 ? 1 : -1);
-	return 0;
-}
-
-static int fan_get_cur_state(struct thermal_cooling_device *cdev, unsigned long
-			     *state)
-{
-	struct acpi_device *device = cdev->devdata;
-	struct acpi_fan *fan = acpi_driver_data(device);
-
-	if (fan->acpi4)
-		return fan_get_state_acpi4(device, state);
-	else
-		return fan_get_state(device, state);
-}
-
-static int fan_set_state(struct acpi_device *device, unsigned long state)
-{
-	if (state != 0 && state != 1)
-		return -EINVAL;
-
-	return acpi_device_set_power(device,
-				     state ? ACPI_STATE_D0 : ACPI_STATE_D3_COLD);
-}
-
-static int fan_set_state_acpi4(struct acpi_device *device, unsigned long state)
-{
-	struct acpi_fan *fan = acpi_driver_data(device);
-	acpi_status status;
-
-	if (state >= fan->fps_count)
-		return -EINVAL;
-
-	status = acpi_execute_simple_method(device->handle, "_FSL",
-					    fan->fps[state].control);
-	if (ACPI_FAILURE(status)) {
-		dev_dbg(&device->dev, "Failed to set state by _FSL\n");
-		return status;
-	}
-
-	return 0;
-}
-
-static int
-fan_set_cur_state(struct thermal_cooling_device *cdev, unsigned long state)
-{
-	struct acpi_device *device = cdev->devdata;
-	struct acpi_fan *fan = acpi_driver_data(device);
-
-	if (fan->acpi4)
-		return fan_set_state_acpi4(device, state);
-	else
-		return fan_set_state(device, state);
-}
-
-static const struct thermal_cooling_device_ops fan_cooling_ops = {
-	.get_max_state = fan_get_max_state,
-	.get_cur_state = fan_get_cur_state,
-	.set_cur_state = fan_set_cur_state,
-};
-
-/* --------------------------------------------------------------------------
- *                               Driver Interface
- * --------------------------------------------------------------------------
-*/
-
-static bool acpi_fan_is_acpi4(struct acpi_device *device)
-{
-	return acpi_has_method(device->handle, "_FIF") &&
-	       acpi_has_method(device->handle, "_FPS") &&
-	       acpi_has_method(device->handle, "_FSL") &&
-	       acpi_has_method(device->handle, "_FST");
-}
-
-static int acpi_fan_get_fif(struct acpi_device *device)
-{
-	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
-	struct acpi_fan *fan = acpi_driver_data(device);
-	struct acpi_buffer format = { sizeof("NNNN"), "NNNN" };
-	struct acpi_buffer fif = { sizeof(fan->fif), &fan->fif };
-	union acpi_object *obj;
-	acpi_status status;
-
-	status = acpi_evaluate_object(device->handle, "_FIF", NULL, &buffer);
-	if (ACPI_FAILURE(status))
-		return status;
-
-	obj = buffer.pointer;
-	if (!obj || obj->type != ACPI_TYPE_PACKAGE) {
-		dev_err(&device->dev, "Invalid _FIF data\n");
-		status = -EINVAL;
-		goto err;
-	}
-
-	status = acpi_extract_package(obj, &format, &fif);
-	if (ACPI_FAILURE(status)) {
-		dev_err(&device->dev, "Invalid _FIF element\n");
-		status = -EINVAL;
-	}
-
-err:
-	kfree(obj);
-	return status;
-}
-
-static int acpi_fan_speed_cmp(const void *a, const void *b)
-{
-	const struct acpi_fan_fps *fps1 = a;
-	const struct acpi_fan_fps *fps2 = b;
-	return fps1->speed - fps2->speed;
-}
-
-static ssize_t show_state(struct device *dev, struct device_attribute *attr, char *buf)
-{
-	struct acpi_fan_fps *fps = container_of(attr, struct acpi_fan_fps, dev_attr);
-	int count;
-
-	if (fps->control == 0xFFFFFFFF || fps->control > 100)
-		count = scnprintf(buf, PAGE_SIZE, "not-defined:");
-	else
-		count = scnprintf(buf, PAGE_SIZE, "%lld:", fps->control);
-
-	if (fps->trip_point == 0xFFFFFFFF || fps->trip_point > 9)
-		count += scnprintf(&buf[count], PAGE_SIZE - count, "not-defined:");
-	else
-		count += scnprintf(&buf[count], PAGE_SIZE - count, "%lld:", fps->trip_point);
-
-	if (fps->speed == 0xFFFFFFFF)
-		count += scnprintf(&buf[count], PAGE_SIZE - count, "not-defined:");
-	else
-		count += scnprintf(&buf[count], PAGE_SIZE - count, "%lld:", fps->speed);
-
-	if (fps->noise_level == 0xFFFFFFFF)
-		count += scnprintf(&buf[count], PAGE_SIZE - count, "not-defined:");
-	else
-		count += scnprintf(&buf[count], PAGE_SIZE - count, "%lld:", fps->noise_level * 100);
-
-	if (fps->power == 0xFFFFFFFF)
-		count += scnprintf(&buf[count], PAGE_SIZE - count, "not-defined\n");
-	else
-		count += scnprintf(&buf[count], PAGE_SIZE - count, "%lld\n", fps->power);
-
-	return count;
-}
-
-static int acpi_fan_get_fps(struct acpi_device *device)
-{
-	struct acpi_fan *fan = acpi_driver_data(device);
-	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
-	union acpi_object *obj;
-	acpi_status status;
-	int i;
-
-	status = acpi_evaluate_object(device->handle, "_FPS", NULL, &buffer);
-	if (ACPI_FAILURE(status))
-		return status;
-
-	obj = buffer.pointer;
-	if (!obj || obj->type != ACPI_TYPE_PACKAGE || obj->package.count < 2) {
-		dev_err(&device->dev, "Invalid _FPS data\n");
-		status = -EINVAL;
-		goto err;
-	}
-
-	fan->fps_count = obj->package.count - 1; /* minus revision field */
-	fan->fps = devm_kcalloc(&device->dev,
-				fan->fps_count, sizeof(struct acpi_fan_fps),
-				GFP_KERNEL);
-	if (!fan->fps) {
-		dev_err(&device->dev, "Not enough memory\n");
-		status = -ENOMEM;
-		goto err;
-	}
-	for (i = 0; i < fan->fps_count; i++) {
-		struct acpi_buffer format = { sizeof("NNNNN"), "NNNNN" };
-		struct acpi_buffer fps = { offsetof(struct acpi_fan_fps, name),
-						&fan->fps[i] };
-		status = acpi_extract_package(&obj->package.elements[i + 1],
-					      &format, &fps);
-		if (ACPI_FAILURE(status)) {
-			dev_err(&device->dev, "Invalid _FPS element\n");
-			goto err;
-		}
-	}
-
-	/* sort the state array according to fan speed in increase order */
-	sort(fan->fps, fan->fps_count, sizeof(*fan->fps),
-	     acpi_fan_speed_cmp, NULL);
-
-	for (i = 0; i < fan->fps_count; ++i) {
-		struct acpi_fan_fps *fps = &fan->fps[i];
-
-		snprintf(fps->name, ACPI_FPS_NAME_LEN, "state%d", i);
-		fps->dev_attr.show = show_state;
-		fps->dev_attr.store = NULL;
-		fps->dev_attr.attr.name = fps->name;
-		fps->dev_attr.attr.mode = 0444;
-		status = sysfs_create_file(&device->dev.kobj, &fps->dev_attr.attr);
-		if (status) {
-			int j;
-
-			for (j = 0; j < i; ++j)
-				sysfs_remove_file(&device->dev.kobj, &fan->fps[j].dev_attr.attr);
-			break;
-		}
-	}
-
-err:
-	kfree(obj);
-	return status;
-}
-
-static int acpi_fan_probe(struct platform_device *pdev)
-{
-	int result = 0;
-	struct thermal_cooling_device *cdev;
-	struct acpi_fan *fan;
-	struct acpi_device *device = ACPI_COMPANION(&pdev->dev);
-	char *name;
-
-	fan = devm_kzalloc(&pdev->dev, sizeof(*fan), GFP_KERNEL);
-	if (!fan) {
-		dev_err(&device->dev, "No memory for fan\n");
-		return -ENOMEM;
-	}
-	device->driver_data = fan;
-	platform_set_drvdata(pdev, fan);
-
-	if (acpi_fan_is_acpi4(device)) {
-		result = acpi_fan_get_fif(device);
-		if (result)
-			return result;
-
-		result = acpi_fan_get_fps(device);
-		if (result)
-			return result;
-
-		fan->acpi4 = true;
-	} else {
-		result = acpi_device_update_power(device, NULL);
-		if (result) {
-			dev_err(&device->dev, "Failed to set initial power state\n");
-			goto err_end;
-		}
-	}
-
-	if (!strncmp(pdev->name, "PNP0C0B", strlen("PNP0C0B")))
-		name = "Fan";
-	else
-		name = acpi_device_bid(device);
-
-	cdev = thermal_cooling_device_register(name, device,
-						&fan_cooling_ops);
-	if (IS_ERR(cdev)) {
-		result = PTR_ERR(cdev);
-		goto err_end;
-	}
-
-	dev_dbg(&pdev->dev, "registered as cooling_device%d\n", cdev->id);
-
-	fan->cdev = cdev;
-	result = sysfs_create_link(&pdev->dev.kobj,
-				   &cdev->device.kobj,
-				   "thermal_cooling");
-	if (result)
-		dev_err(&pdev->dev, "Failed to create sysfs link 'thermal_cooling'\n");
-
-	result = sysfs_create_link(&cdev->device.kobj,
-				   &pdev->dev.kobj,
-				   "device");
-	if (result) {
-		dev_err(&pdev->dev, "Failed to create sysfs link 'device'\n");
-		goto err_end;
-	}
-
-	return 0;
-
-err_end:
-	if (fan->acpi4) {
-		int i;
-
-		for (i = 0; i < fan->fps_count; ++i)
-			sysfs_remove_file(&device->dev.kobj, &fan->fps[i].dev_attr.attr);
-	}
-
-	return result;
-}
-
-static int acpi_fan_remove(struct platform_device *pdev)
-{
-	struct acpi_fan *fan = platform_get_drvdata(pdev);
-
-	if (fan->acpi4) {
-		struct acpi_device *device = ACPI_COMPANION(&pdev->dev);
-		int i;
-
-		for (i = 0; i < fan->fps_count; ++i)
-			sysfs_remove_file(&device->dev.kobj, &fan->fps[i].dev_attr.attr);
-	}
-	sysfs_remove_link(&pdev->dev.kobj, "thermal_cooling");
-	sysfs_remove_link(&fan->cdev->device.kobj, "device");
-	thermal_cooling_device_unregister(fan->cdev);
-
-	return 0;
-}
-
-#ifdef CONFIG_PM_SLEEP
-static int acpi_fan_suspend(struct device *dev)
-{
-	struct acpi_fan *fan = dev_get_drvdata(dev);
-	if (fan->acpi4)
-		return 0;
-
-	acpi_device_set_power(ACPI_COMPANION(dev), ACPI_STATE_D0);
-
-	return AE_OK;
-}
-
-static int acpi_fan_resume(struct device *dev)
-{
-	int result;
-	struct acpi_fan *fan = dev_get_drvdata(dev);
-
-	if (fan->acpi4)
-		return 0;
-
-	result = acpi_device_update_power(ACPI_COMPANION(dev), NULL);
-	if (result)
-		dev_err(dev, "Error updating fan power state\n");
-
-	return result;
-}
-#endif
-
-module_platform_driver(acpi_fan_driver);
diff --git a/drivers/acpi/fan.h b/drivers/acpi/fan.h
new file mode 100644
index 000000000000..97ce3212edf3
--- /dev/null
+++ b/drivers/acpi/fan.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * ACPI fan device IDs are shared between the fan driver and the device power
+ * management code.
+ *
+ * Add new device IDs before the generic ACPI fan one.
+ */
+
+#ifndef _ACPI_FAN_H_
+#define _ACPI_FAN_H_
+
+#include <linux/kconfig.h>
+#include <linux/limits.h>
+
+#define ACPI_FAN_DEVICE_IDS	\
+	{"INT3404", }, /* Fan */ \
+	{"INTC1044", }, /* Fan for Tiger Lake generation */ \
+	{"INTC1048", }, /* Fan for Alder Lake generation */ \
+	{"INTC1063", }, /* Fan for Meteor Lake generation */ \
+	{"INTC106A", }, /* Fan for Lunar Lake generation */ \
+	{"INTC10A2", }, /* Fan for Raptor Lake generation */ \
+	{"INTC10D6", }, /* Fan for Panther Lake generation */ \
+	{"INTC10FE", }, /* Fan for Wildcat Lake generation */ \
+	{"INTC10F5", }, /* Fan for Nova Lake generation */ \
+	{"PNP0C0B", } /* Generic ACPI fan */
+
+#define ACPI_FPS_NAME_LEN	20
+
+struct acpi_fan_fps {
+	u64 control;
+	u64 trip_point;
+	u64 speed;
+	u64 noise_level;
+	u64 power;
+	char name[ACPI_FPS_NAME_LEN];
+	struct device_attribute dev_attr;
+};
+
+struct acpi_fan_fif {
+	u8 revision;
+	u8 fine_grain_ctrl;
+	u8 step_size;
+	u8 low_speed_notification;
+};
+
+struct acpi_fan_fst {
+	u64 revision;
+	u64 control;
+	u64 speed;
+};
+
+struct acpi_fan {
+	acpi_handle handle;
+	bool acpi4;
+	bool has_fst;
+	struct acpi_fan_fif fif;
+	struct acpi_fan_fps *fps;
+	int fps_count;
+	/* A value of 0 means that trippoint-related functions are not supported */
+	u32 fan_trip_granularity;
+#if IS_REACHABLE(CONFIG_HWMON)
+	struct device *hdev;
+#endif
+	struct thermal_cooling_device *cdev;
+	struct device_attribute fst_speed;
+	struct device_attribute fine_grain_control;
+};
+
+/**
+ * acpi_fan_speed_valid - Check if fan speed value is valid
+ * @speeed: Speed value returned by the ACPI firmware
+ *
+ * Check if the fan speed value returned by the ACPI firmware is valid. This function is
+ * necessary as ACPI firmware implementations can return 0xFFFFFFFF to signal that the
+ * ACPI fan does not support speed reporting. Additionally, some buggy ACPI firmware
+ * implementations return a value larger than the 32-bit integer value defined by
+ * the ACPI specification when using placeholder values. Such invalid values are also
+ * detected by this function.
+ *
+ * Returns: True if the fan speed value is valid, false otherwise.
+ */
+static inline bool acpi_fan_speed_valid(u64 speed)
+{
+	return speed < U32_MAX;
+}
+
+/**
+ * acpi_fan_power_valid - Check if fan power value is valid
+ * @power: Power value returned by the ACPI firmware
+ *
+ * Check if the fan power value returned by the ACPI firmware is valid.
+ * See acpi_fan_speed_valid() for details.
+ *
+ * Returns: True if the fan power value is valid, false otherwise.
+ */
+static inline bool acpi_fan_power_valid(u64 power)
+{
+	return power < U32_MAX;
+}
+
+int acpi_fan_get_fst(acpi_handle handle, struct acpi_fan_fst *fst);
+int acpi_fan_create_attributes(struct acpi_device *device);
+void acpi_fan_delete_attributes(struct acpi_device *device);
+
+#if IS_REACHABLE(CONFIG_HWMON)
+int devm_acpi_fan_create_hwmon(struct device *dev);
+void acpi_fan_notify_hwmon(struct device *dev);
+#else
+static inline int devm_acpi_fan_create_hwmon(struct device *dev) { return 0; };
+static inline void acpi_fan_notify_hwmon(struct device *dev) { };
+#endif
+
+#endif
diff --git a/drivers/acpi/fan_attr.c b/drivers/acpi/fan_attr.c
new file mode 100644
index 000000000000..9b7fa52f3c2a
--- /dev/null
+++ b/drivers/acpi/fan_attr.c
@@ -0,0 +1,144 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ *  fan_attr.c - Create extra attributes for ACPI Fan driver
+ *
+ *  Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com>
+ *  Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
+ *  Copyright (C) 2022 Intel Corporation. All rights reserved.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/acpi.h>
+
+#include "fan.h"
+
+MODULE_LICENSE("GPL");
+
+static ssize_t show_state(struct device *dev, struct device_attribute *attr, char *buf)
+{
+	struct acpi_fan_fps *fps = container_of(attr, struct acpi_fan_fps, dev_attr);
+	int count;
+
+	if (fps->control == 0xFFFFFFFF || fps->control > 100)
+		count = sysfs_emit(buf, "not-defined:");
+	else
+		count = sysfs_emit(buf, "%lld:", fps->control);
+
+	if (fps->trip_point == 0xFFFFFFFF || fps->trip_point > 9)
+		count += sysfs_emit_at(buf, count, "not-defined:");
+	else
+		count += sysfs_emit_at(buf, count, "%lld:", fps->trip_point);
+
+	if (fps->speed == 0xFFFFFFFF)
+		count += sysfs_emit_at(buf, count, "not-defined:");
+	else
+		count += sysfs_emit_at(buf, count, "%lld:", fps->speed);
+
+	if (fps->noise_level == 0xFFFFFFFF)
+		count += sysfs_emit_at(buf, count, "not-defined:");
+	else
+		count += sysfs_emit_at(buf, count, "%lld:", fps->noise_level * 100);
+
+	if (fps->power == 0xFFFFFFFF)
+		count += sysfs_emit_at(buf, count, "not-defined\n");
+	else
+		count += sysfs_emit_at(buf, count, "%lld\n", fps->power);
+
+	return count;
+}
+
+static ssize_t show_fan_speed(struct device *dev, struct device_attribute *attr, char *buf)
+{
+	struct acpi_device *acpi_dev = container_of(dev, struct acpi_device, dev);
+	struct acpi_fan_fst fst;
+	int status;
+
+	status = acpi_fan_get_fst(acpi_dev->handle, &fst);
+	if (status)
+		return status;
+
+	return sysfs_emit(buf, "%lld\n", fst.speed);
+}
+
+static ssize_t show_fine_grain_control(struct device *dev, struct device_attribute *attr, char *buf)
+{
+	struct acpi_device *acpi_dev = container_of(dev, struct acpi_device, dev);
+	struct acpi_fan *fan = acpi_driver_data(acpi_dev);
+
+	return sysfs_emit(buf, "%d\n", fan->fif.fine_grain_ctrl);
+}
+
+int acpi_fan_create_attributes(struct acpi_device *device)
+{
+	struct acpi_fan *fan = acpi_driver_data(device);
+	int i, status;
+
+	/* _FST is present if we are here */
+	sysfs_attr_init(&fan->fst_speed.attr);
+	fan->fst_speed.show = show_fan_speed;
+	fan->fst_speed.store = NULL;
+	fan->fst_speed.attr.name = "fan_speed_rpm";
+	fan->fst_speed.attr.mode = 0444;
+	status = sysfs_create_file(&device->dev.kobj, &fan->fst_speed.attr);
+	if (status)
+		return status;
+
+	if (!fan->acpi4)
+		return 0;
+
+	sysfs_attr_init(&fan->fine_grain_control.attr);
+	fan->fine_grain_control.show = show_fine_grain_control;
+	fan->fine_grain_control.store = NULL;
+	fan->fine_grain_control.attr.name = "fine_grain_control";
+	fan->fine_grain_control.attr.mode = 0444;
+	status = sysfs_create_file(&device->dev.kobj, &fan->fine_grain_control.attr);
+	if (status)
+		goto rem_fst_attr;
+
+	for (i = 0; i < fan->fps_count; ++i) {
+		struct acpi_fan_fps *fps = &fan->fps[i];
+
+		snprintf(fps->name, ACPI_FPS_NAME_LEN, "state%d", i);
+		sysfs_attr_init(&fps->dev_attr.attr);
+		fps->dev_attr.show = show_state;
+		fps->dev_attr.store = NULL;
+		fps->dev_attr.attr.name = fps->name;
+		fps->dev_attr.attr.mode = 0444;
+		status = sysfs_create_file(&device->dev.kobj, &fps->dev_attr.attr);
+		if (status) {
+			int j;
+
+			for (j = 0; j < i; ++j)
+				sysfs_remove_file(&device->dev.kobj, &fan->fps[j].dev_attr.attr);
+			goto rem_fine_grain_attr;
+		}
+	}
+
+	return 0;
+
+rem_fine_grain_attr:
+	sysfs_remove_file(&device->dev.kobj, &fan->fine_grain_control.attr);
+
+rem_fst_attr:
+	sysfs_remove_file(&device->dev.kobj, &fan->fst_speed.attr);
+
+	return status;
+}
+
+void acpi_fan_delete_attributes(struct acpi_device *device)
+{
+	struct acpi_fan *fan = acpi_driver_data(device);
+	int i;
+
+	sysfs_remove_file(&device->dev.kobj, &fan->fst_speed.attr);
+
+	if (!fan->acpi4)
+		return;
+
+	for (i = 0; i < fan->fps_count; ++i)
+		sysfs_remove_file(&device->dev.kobj, &fan->fps[i].dev_attr.attr);
+
+	sysfs_remove_file(&device->dev.kobj, &fan->fine_grain_control.attr);
+}
diff --git a/drivers/acpi/fan_core.c b/drivers/acpi/fan_core.c
new file mode 100644
index 000000000000..fb08b8549ed7
--- /dev/null
+++ b/drivers/acpi/fan_core.c
@@ -0,0 +1,701 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ *  fan_core.c - ACPI Fan core Driver
+ *
+ *  Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com>
+ *  Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
+ *  Copyright (C) 2022 Intel Corporation. All rights reserved.
+ */
+
+#include <linux/bits.h>
+#include <linux/kernel.h>
+#include <linux/limits.h>
+#include <linux/math.h>
+#include <linux/math64.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/uaccess.h>
+#include <linux/uuid.h>
+#include <linux/thermal.h>
+#include <linux/acpi.h>
+#include <linux/platform_device.h>
+#include <linux/sort.h>
+
+#include "fan.h"
+
+#define ACPI_FAN_NOTIFY_STATE_CHANGED	0x80
+
+/*
+ * Defined inside the "Fan Noise Signal" section at
+ * https://learn.microsoft.com/en-us/windows-hardware/design/device-experiences/design-guide.
+ */
+static const guid_t acpi_fan_microsoft_guid = GUID_INIT(0xA7611840, 0x99FE, 0x41AE, 0xA4, 0x88,
+							0x35, 0xC7, 0x59, 0x26, 0xC8, 0xEB);
+#define ACPI_FAN_DSM_GET_TRIP_POINT_GRANULARITY 1
+#define ACPI_FAN_DSM_SET_TRIP_POINTS		2
+#define ACPI_FAN_DSM_GET_OPERATING_RANGES	3
+
+/*
+ * Ensures that fans with a very low trip point granularity
+ * do not send too many notifications.
+ */
+static uint min_trip_distance = 100;
+module_param(min_trip_distance, uint, 0);
+MODULE_PARM_DESC(min_trip_distance, "Minimum distance between fan speed trip points in RPM");
+
+static const struct acpi_device_id fan_device_ids[] = {
+	ACPI_FAN_DEVICE_IDS,
+	{"", 0},
+};
+MODULE_DEVICE_TABLE(acpi, fan_device_ids);
+
+/* thermal cooling device callbacks */
+static int fan_get_max_state(struct thermal_cooling_device *cdev, unsigned long
+			     *state)
+{
+	struct acpi_device *device = cdev->devdata;
+	struct acpi_fan *fan = acpi_driver_data(device);
+
+	if (fan->acpi4) {
+		if (fan->fif.fine_grain_ctrl)
+			*state = 100 / fan->fif.step_size;
+		else
+			*state = fan->fps_count - 1;
+	} else {
+		*state = 1;
+	}
+
+	return 0;
+}
+
+int acpi_fan_get_fst(acpi_handle handle, struct acpi_fan_fst *fst)
+{
+	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
+	union acpi_object *obj;
+	acpi_status status;
+	int ret = 0;
+
+	status = acpi_evaluate_object(handle, "_FST", NULL, &buffer);
+	if (ACPI_FAILURE(status))
+		return -EIO;
+
+	obj = buffer.pointer;
+	if (!obj)
+		return -ENODATA;
+
+	if (obj->type != ACPI_TYPE_PACKAGE || obj->package.count != 3) {
+		ret = -EPROTO;
+		goto err;
+	}
+
+	if (obj->package.elements[0].type != ACPI_TYPE_INTEGER ||
+	    obj->package.elements[1].type != ACPI_TYPE_INTEGER ||
+	    obj->package.elements[2].type != ACPI_TYPE_INTEGER) {
+		ret = -EPROTO;
+		goto err;
+	}
+
+	fst->revision = obj->package.elements[0].integer.value;
+	fst->control = obj->package.elements[1].integer.value;
+	fst->speed = obj->package.elements[2].integer.value;
+
+err:
+	kfree(obj);
+	return ret;
+}
+
+static int fan_get_state_acpi4(struct acpi_device *device, unsigned long *state)
+{
+	struct acpi_fan *fan = acpi_driver_data(device);
+	struct acpi_fan_fst fst;
+	int status, i;
+
+	status = acpi_fan_get_fst(device->handle, &fst);
+	if (status)
+		return status;
+
+	if (fan->fif.fine_grain_ctrl) {
+		/* This control should be same what we set using _FSL by spec */
+		if (fst.control > 100) {
+			dev_dbg(&device->dev, "Invalid control value returned\n");
+			goto match_fps;
+		}
+
+		*state = (int) fst.control / fan->fif.step_size;
+		return 0;
+	}
+
+match_fps:
+	for (i = 0; i < fan->fps_count; i++) {
+		if (fst.control == fan->fps[i].control)
+			break;
+	}
+	if (i == fan->fps_count) {
+		dev_dbg(&device->dev, "No matching fps control value\n");
+		return -EINVAL;
+	}
+
+	*state = i;
+
+	return status;
+}
+
+static int fan_get_state(struct acpi_device *device, unsigned long *state)
+{
+	int result;
+	int acpi_state = ACPI_STATE_D0;
+
+	result = acpi_device_update_power(device, &acpi_state);
+	if (result)
+		return result;
+
+	*state = acpi_state == ACPI_STATE_D3_COLD
+			|| acpi_state == ACPI_STATE_D3_HOT ?
+		0 : (acpi_state == ACPI_STATE_D0 ? 1 : -1);
+	return 0;
+}
+
+static int fan_get_cur_state(struct thermal_cooling_device *cdev, unsigned long
+			     *state)
+{
+	struct acpi_device *device = cdev->devdata;
+	struct acpi_fan *fan = acpi_driver_data(device);
+
+	if (fan->acpi4)
+		return fan_get_state_acpi4(device, state);
+	else
+		return fan_get_state(device, state);
+}
+
+static int fan_set_state(struct acpi_device *device, unsigned long state)
+{
+	if (state != 0 && state != 1)
+		return -EINVAL;
+
+	return acpi_device_set_power(device,
+				     state ? ACPI_STATE_D0 : ACPI_STATE_D3_COLD);
+}
+
+static int fan_set_state_acpi4(struct acpi_device *device, unsigned long state)
+{
+	struct acpi_fan *fan = acpi_driver_data(device);
+	acpi_status status;
+	u64 value = state;
+	int max_state;
+
+	if (fan->fif.fine_grain_ctrl)
+		max_state = 100 / fan->fif.step_size;
+	else
+		max_state = fan->fps_count - 1;
+
+	if (state > max_state)
+		return -EINVAL;
+
+	if (fan->fif.fine_grain_ctrl) {
+		value *= fan->fif.step_size;
+		/* Spec allows compensate the last step only */
+		if (value + fan->fif.step_size > 100)
+			value = 100;
+	} else {
+		value = fan->fps[state].control;
+	}
+
+	status = acpi_execute_simple_method(device->handle, "_FSL", value);
+	if (ACPI_FAILURE(status)) {
+		dev_dbg(&device->dev, "Failed to set state by _FSL\n");
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+static int
+fan_set_cur_state(struct thermal_cooling_device *cdev, unsigned long state)
+{
+	struct acpi_device *device = cdev->devdata;
+	struct acpi_fan *fan = acpi_driver_data(device);
+
+	if (fan->acpi4)
+		return fan_set_state_acpi4(device, state);
+	else
+		return fan_set_state(device, state);
+}
+
+static const struct thermal_cooling_device_ops fan_cooling_ops = {
+	.get_max_state = fan_get_max_state,
+	.get_cur_state = fan_get_cur_state,
+	.set_cur_state = fan_set_cur_state,
+};
+
+/* --------------------------------------------------------------------------
+ *                               Driver Interface
+ * --------------------------------------------------------------------------
+*/
+
+static int acpi_fan_get_fif(struct acpi_device *device)
+{
+	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
+	struct acpi_fan *fan = acpi_driver_data(device);
+	struct acpi_buffer format = { sizeof("NNNN"), "NNNN" };
+	u64 fields[4];
+	struct acpi_buffer fif = { sizeof(fields), fields };
+	union acpi_object *obj;
+	acpi_status status;
+
+	status = acpi_evaluate_object(device->handle, "_FIF", NULL, &buffer);
+	if (ACPI_FAILURE(status))
+		return status;
+
+	obj = buffer.pointer;
+	if (!obj || obj->type != ACPI_TYPE_PACKAGE) {
+		dev_err(&device->dev, "Invalid _FIF data\n");
+		status = -EINVAL;
+		goto err;
+	}
+
+	status = acpi_extract_package(obj, &format, &fif);
+	if (ACPI_FAILURE(status)) {
+		dev_err(&device->dev, "Invalid _FIF element\n");
+		status = -EINVAL;
+		goto err;
+	}
+
+	fan->fif.revision = fields[0];
+	fan->fif.fine_grain_ctrl = fields[1];
+	fan->fif.step_size = fields[2];
+	fan->fif.low_speed_notification = fields[3];
+
+	/* If there is a bug in step size and set as 0, change to 1 */
+	if (!fan->fif.step_size)
+		fan->fif.step_size = 1;
+	/* If step size > 9, change to 9 (by spec valid values 1-9) */
+	else if (fan->fif.step_size > 9)
+		fan->fif.step_size = 9;
+err:
+	kfree(obj);
+	return status;
+}
+
+static int acpi_fan_speed_cmp(const void *a, const void *b)
+{
+	const struct acpi_fan_fps *fps1 = a;
+	const struct acpi_fan_fps *fps2 = b;
+	return fps1->speed - fps2->speed;
+}
+
+static int acpi_fan_get_fps(struct acpi_device *device)
+{
+	struct acpi_fan *fan = acpi_driver_data(device);
+	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
+	union acpi_object *obj;
+	acpi_status status;
+	int i;
+
+	status = acpi_evaluate_object(device->handle, "_FPS", NULL, &buffer);
+	if (ACPI_FAILURE(status))
+		return status;
+
+	obj = buffer.pointer;
+	if (!obj || obj->type != ACPI_TYPE_PACKAGE || obj->package.count < 2) {
+		dev_err(&device->dev, "Invalid _FPS data\n");
+		status = -EINVAL;
+		goto err;
+	}
+
+	fan->fps_count = obj->package.count - 1; /* minus revision field */
+	fan->fps = devm_kcalloc(&device->dev,
+				fan->fps_count, sizeof(struct acpi_fan_fps),
+				GFP_KERNEL);
+	if (!fan->fps) {
+		dev_err(&device->dev, "Not enough memory\n");
+		status = -ENOMEM;
+		goto err;
+	}
+	for (i = 0; i < fan->fps_count; i++) {
+		struct acpi_buffer format = { sizeof("NNNNN"), "NNNNN" };
+		struct acpi_buffer fps = { offsetof(struct acpi_fan_fps, name),
+						&fan->fps[i] };
+		status = acpi_extract_package(&obj->package.elements[i + 1],
+					      &format, &fps);
+		if (ACPI_FAILURE(status)) {
+			dev_err(&device->dev, "Invalid _FPS element\n");
+			goto err;
+		}
+	}
+
+	/* sort the state array according to fan speed in increase order */
+	sort(fan->fps, fan->fps_count, sizeof(*fan->fps),
+	     acpi_fan_speed_cmp, NULL);
+
+err:
+	kfree(obj);
+	return status;
+}
+
+static int acpi_fan_dsm_init(struct device *dev)
+{
+	union acpi_object dummy = {
+		.package = {
+			.type = ACPI_TYPE_PACKAGE,
+			.count = 0,
+			.elements = NULL,
+		},
+	};
+	struct acpi_fan *fan = dev_get_drvdata(dev);
+	union acpi_object *obj;
+	int ret = 0;
+
+	if (!acpi_check_dsm(fan->handle, &acpi_fan_microsoft_guid, 0,
+			    BIT(ACPI_FAN_DSM_GET_TRIP_POINT_GRANULARITY) |
+			    BIT(ACPI_FAN_DSM_SET_TRIP_POINTS)))
+		return 0;
+
+	dev_info(dev, "Using Microsoft fan extensions\n");
+
+	obj = acpi_evaluate_dsm_typed(fan->handle, &acpi_fan_microsoft_guid, 0,
+				      ACPI_FAN_DSM_GET_TRIP_POINT_GRANULARITY, &dummy,
+				      ACPI_TYPE_INTEGER);
+	if (!obj)
+		return -EIO;
+
+	if (obj->integer.value > U32_MAX)
+		ret = -EOVERFLOW;
+	else
+		fan->fan_trip_granularity = obj->integer.value;
+
+	kfree(obj);
+
+	return ret;
+}
+
+static int acpi_fan_dsm_set_trip_points(struct device *dev, u64 upper, u64 lower)
+{
+	union acpi_object args[2] = {
+		{
+			.integer = {
+				.type = ACPI_TYPE_INTEGER,
+				.value = lower,
+			},
+		},
+		{
+			.integer = {
+				.type = ACPI_TYPE_INTEGER,
+				.value = upper,
+			},
+		},
+	};
+	struct acpi_fan *fan = dev_get_drvdata(dev);
+	union acpi_object in = {
+		.package = {
+			.type = ACPI_TYPE_PACKAGE,
+			.count = ARRAY_SIZE(args),
+			.elements = args,
+		},
+	};
+	union acpi_object *obj;
+
+	obj = acpi_evaluate_dsm(fan->handle, &acpi_fan_microsoft_guid, 0,
+				ACPI_FAN_DSM_SET_TRIP_POINTS, &in);
+	kfree(obj);
+
+	return 0;
+}
+
+static int acpi_fan_dsm_start(struct device *dev)
+{
+	struct acpi_fan *fan = dev_get_drvdata(dev);
+	int ret;
+
+	if (!fan->fan_trip_granularity)
+		return 0;
+
+	/*
+	 * Some firmware implementations only update the values returned by the
+	 * _FST control method when a notification is received. This usually
+	 * works with Microsoft Windows as setting up trip points will keep
+	 * triggering said notifications, but will cause issues when using _FST
+	 * without the Microsoft-specific trip point extension.
+	 *
+	 * Because of this, an initial notification needs to be triggered to
+	 * start the cycle of trip points updates. This is achieved by setting
+	 * the trip points sequencially to two separate ranges. As by the
+	 * Microsoft specification the firmware should trigger a notification
+	 * immediately if the fan speed is outside the trip point range. This
+	 * _should_ result in at least one notification as both ranges do not
+	 * overlap, meaning that the current fan speed needs to be outside at
+	 * least one range.
+	 */
+	ret = acpi_fan_dsm_set_trip_points(dev, fan->fan_trip_granularity, 0);
+	if (ret < 0)
+		return ret;
+
+	return acpi_fan_dsm_set_trip_points(dev, fan->fan_trip_granularity * 3,
+					    fan->fan_trip_granularity * 2);
+}
+
+static int acpi_fan_dsm_update_trips_points(struct device *dev, struct acpi_fan_fst *fst)
+{
+	struct acpi_fan *fan = dev_get_drvdata(dev);
+	u64 upper, lower;
+
+	if (!fan->fan_trip_granularity)
+		return 0;
+
+	if (!acpi_fan_speed_valid(fst->speed))
+		return -EINVAL;
+
+	upper = roundup_u64(fst->speed + min_trip_distance, fan->fan_trip_granularity);
+	if (fst->speed <= min_trip_distance) {
+		lower = 0;
+	} else {
+		/*
+		 * Valid fan speed values cannot be larger than 32 bit, so
+		 * we can safely assume that no overflow will happen here.
+		 */
+		lower = rounddown((u32)fst->speed - min_trip_distance, fan->fan_trip_granularity);
+	}
+
+	return acpi_fan_dsm_set_trip_points(dev, upper, lower);
+}
+
+static void acpi_fan_notify_handler(acpi_handle handle, u32 event, void *context)
+{
+	struct device *dev = context;
+	struct acpi_fan_fst fst;
+	int ret;
+
+	switch (event) {
+	case ACPI_FAN_NOTIFY_STATE_CHANGED:
+		/*
+		 * The ACPI specification says that we must evaluate _FST when we
+		 * receive an ACPI event indicating that the fan state has changed.
+		 */
+		ret = acpi_fan_get_fst(handle, &fst);
+		if (ret < 0) {
+			dev_err(dev, "Error retrieving current fan status: %d\n", ret);
+		} else {
+			ret = acpi_fan_dsm_update_trips_points(dev, &fst);
+			if (ret < 0)
+				dev_err(dev, "Failed to update trip points: %d\n", ret);
+		}
+
+		acpi_fan_notify_hwmon(dev);
+		acpi_bus_generate_netlink_event("fan", dev_name(dev), event, 0);
+		break;
+	default:
+		dev_dbg(dev, "Unsupported ACPI notification 0x%x\n", event);
+		break;
+	}
+}
+
+static void acpi_fan_notify_remove(void *data)
+{
+	struct acpi_fan *fan = data;
+
+	acpi_remove_notify_handler(fan->handle, ACPI_DEVICE_NOTIFY, acpi_fan_notify_handler);
+}
+
+static int devm_acpi_fan_notify_init(struct device *dev)
+{
+	struct acpi_fan *fan = dev_get_drvdata(dev);
+	acpi_status status;
+
+	status = acpi_install_notify_handler(fan->handle, ACPI_DEVICE_NOTIFY,
+					     acpi_fan_notify_handler, dev);
+	if (ACPI_FAILURE(status))
+		return -EIO;
+
+	return devm_add_action_or_reset(dev, acpi_fan_notify_remove, fan);
+}
+
+static int acpi_fan_probe(struct platform_device *pdev)
+{
+	int result = 0;
+	struct thermal_cooling_device *cdev;
+	struct acpi_fan *fan;
+	struct acpi_device *device = ACPI_COMPANION(&pdev->dev);
+	char *name;
+
+	if (!device)
+		return -ENODEV;
+
+	fan = devm_kzalloc(&pdev->dev, sizeof(*fan), GFP_KERNEL);
+	if (!fan) {
+		dev_err(&device->dev, "No memory for fan\n");
+		return -ENOMEM;
+	}
+
+	fan->handle = device->handle;
+	device->driver_data = fan;
+	platform_set_drvdata(pdev, fan);
+
+	if (acpi_has_method(device->handle, "_FST")) {
+		fan->has_fst = true;
+		fan->acpi4 = acpi_has_method(device->handle, "_FIF") &&
+				acpi_has_method(device->handle, "_FPS") &&
+				acpi_has_method(device->handle, "_FSL");
+	}
+
+	if (fan->acpi4) {
+		result = acpi_fan_get_fif(device);
+		if (result)
+			return result;
+
+		result = acpi_fan_get_fps(device);
+		if (result)
+			return result;
+	}
+
+	if (fan->has_fst) {
+		result = acpi_fan_dsm_init(&pdev->dev);
+		if (result)
+			return result;
+
+		result = devm_acpi_fan_create_hwmon(&pdev->dev);
+		if (result)
+			return result;
+
+		result = devm_acpi_fan_notify_init(&pdev->dev);
+		if (result)
+			return result;
+
+		result = acpi_fan_dsm_start(&pdev->dev);
+		if (result) {
+			dev_err(&pdev->dev, "Failed to start Microsoft fan extensions\n");
+			return result;
+		}
+
+		result = acpi_fan_create_attributes(device);
+		if (result)
+			return result;
+	}
+
+	if (!fan->acpi4) {
+		result = acpi_device_update_power(device, NULL);
+		if (result) {
+			dev_err(&device->dev, "Failed to set initial power state\n");
+			goto err_end;
+		}
+	}
+
+	if (!strncmp(pdev->name, "PNP0C0B", strlen("PNP0C0B")))
+		name = "Fan";
+	else
+		name = acpi_device_bid(device);
+
+	cdev = thermal_cooling_device_register(name, device,
+						&fan_cooling_ops);
+	if (IS_ERR(cdev)) {
+		result = PTR_ERR(cdev);
+		goto err_end;
+	}
+
+	dev_dbg(&pdev->dev, "registered as cooling_device%d\n", cdev->id);
+
+	fan->cdev = cdev;
+	result = sysfs_create_link(&pdev->dev.kobj,
+				   &cdev->device.kobj,
+				   "thermal_cooling");
+	if (result) {
+		dev_err(&pdev->dev, "Failed to create sysfs link 'thermal_cooling'\n");
+		goto err_unregister;
+	}
+
+	result = sysfs_create_link(&cdev->device.kobj,
+				   &pdev->dev.kobj,
+				   "device");
+	if (result) {
+		dev_err(&pdev->dev, "Failed to create sysfs link 'device'\n");
+		goto err_remove_link;
+	}
+
+	return 0;
+
+err_remove_link:
+	sysfs_remove_link(&pdev->dev.kobj, "thermal_cooling");
+err_unregister:
+	thermal_cooling_device_unregister(cdev);
+err_end:
+	if (fan->has_fst)
+		acpi_fan_delete_attributes(device);
+
+	return result;
+}
+
+static void acpi_fan_remove(struct platform_device *pdev)
+{
+	struct acpi_fan *fan = platform_get_drvdata(pdev);
+
+	if (fan->has_fst) {
+		struct acpi_device *device = ACPI_COMPANION(&pdev->dev);
+
+		acpi_fan_delete_attributes(device);
+	}
+	sysfs_remove_link(&pdev->dev.kobj, "thermal_cooling");
+	sysfs_remove_link(&fan->cdev->device.kobj, "device");
+	thermal_cooling_device_unregister(fan->cdev);
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int acpi_fan_suspend(struct device *dev)
+{
+	struct acpi_fan *fan = dev_get_drvdata(dev);
+	if (fan->acpi4)
+		return 0;
+
+	acpi_device_set_power(ACPI_COMPANION(dev), ACPI_STATE_D0);
+
+	return AE_OK;
+}
+
+static int acpi_fan_resume(struct device *dev)
+{
+	struct acpi_fan *fan = dev_get_drvdata(dev);
+	int result;
+
+	if (fan->has_fst) {
+		result = acpi_fan_dsm_start(dev);
+		if (result)
+			dev_err(dev, "Failed to start Microsoft fan extensions: %d\n", result);
+	}
+
+	if (fan->acpi4)
+		return 0;
+
+	result = acpi_device_update_power(ACPI_COMPANION(dev), NULL);
+	if (result)
+		dev_err(dev, "Error updating fan power state\n");
+
+	return result;
+}
+
+static const struct dev_pm_ops acpi_fan_pm = {
+	.resume = acpi_fan_resume,
+	.freeze = acpi_fan_suspend,
+	.thaw = acpi_fan_resume,
+	.restore = acpi_fan_resume,
+};
+#define FAN_PM_OPS_PTR (&acpi_fan_pm)
+
+#else
+
+#define FAN_PM_OPS_PTR NULL
+
+#endif
+
+static struct platform_driver acpi_fan_driver = {
+	.probe = acpi_fan_probe,
+	.remove = acpi_fan_remove,
+	.driver = {
+		.name = "acpi-fan",
+		.acpi_match_table = fan_device_ids,
+		.pm = FAN_PM_OPS_PTR,
+	},
+};
+
+module_platform_driver(acpi_fan_driver);
+
+MODULE_AUTHOR("Paul Diefenbaugh");
+MODULE_DESCRIPTION("ACPI Fan Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/acpi/fan_hwmon.c b/drivers/acpi/fan_hwmon.c
new file mode 100644
index 000000000000..d3374f8f524b
--- /dev/null
+++ b/drivers/acpi/fan_hwmon.c
@@ -0,0 +1,180 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * hwmon interface for the ACPI Fan driver.
+ *
+ * Copyright (C) 2024 Armin Wolf <W_Armin@gmx.de>
+ */
+
+#include <linux/acpi.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/hwmon.h>
+#include <linux/limits.h>
+#include <linux/types.h>
+#include <linux/units.h>
+
+#include "fan.h"
+
+static struct acpi_fan_fps *acpi_fan_get_current_fps(struct acpi_fan *fan, u64 control)
+{
+	unsigned int i;
+
+	for (i = 0; i < fan->fps_count; i++) {
+		if (fan->fps[i].control == control)
+			return &fan->fps[i];
+	}
+
+	return NULL;
+}
+
+static umode_t acpi_fan_hwmon_is_visible(const void *drvdata, enum hwmon_sensor_types type,
+					 u32 attr, int channel)
+{
+	const struct acpi_fan *fan = drvdata;
+	unsigned int i;
+
+	switch (type) {
+	case hwmon_fan:
+		switch (attr) {
+		case hwmon_fan_input:
+			return 0444;
+		case hwmon_fan_target:
+			/* Only acpi4 fans support fan control. */
+			if (!fan->acpi4)
+				return 0;
+
+			/*
+			 * When in fine grain control mode, not every fan control value
+			 * has an associated fan performance state.
+			 */
+			if (fan->fif.fine_grain_ctrl)
+				return 0;
+
+			return 0444;
+		default:
+			return 0;
+		}
+	case hwmon_power:
+		switch (attr) {
+		case hwmon_power_input:
+			/* Only acpi4 fans support fan control. */
+			if (!fan->acpi4)
+				return 0;
+
+			/*
+			 * When in fine grain control mode, not every fan control value
+			 * has an associated fan performance state.
+			 */
+			if (fan->fif.fine_grain_ctrl)
+				return 0;
+
+			/*
+			 * When all fan performance states contain no valid power data,
+			 * when the associated attribute should not be created.
+			 */
+			for (i = 0; i < fan->fps_count; i++) {
+				if (acpi_fan_power_valid(fan->fps[i].power))
+					return 0444;
+			}
+
+			return 0;
+		default:
+			return 0;
+		}
+	default:
+		return 0;
+	}
+}
+
+static int acpi_fan_hwmon_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
+			       int channel, long *val)
+{
+	struct acpi_fan *fan = dev_get_drvdata(dev);
+	struct acpi_fan_fps *fps;
+	struct acpi_fan_fst fst;
+	int ret;
+
+	ret = acpi_fan_get_fst(fan->handle, &fst);
+	if (ret < 0)
+		return ret;
+
+	switch (type) {
+	case hwmon_fan:
+		switch (attr) {
+		case hwmon_fan_input:
+			if (!acpi_fan_speed_valid(fst.speed))
+				return -ENODEV;
+
+			if (fst.speed > LONG_MAX)
+				return -EOVERFLOW;
+
+			*val = fst.speed;
+			return 0;
+		case hwmon_fan_target:
+			fps = acpi_fan_get_current_fps(fan, fst.control);
+			if (!fps)
+				return -EIO;
+
+			if (fps->speed > LONG_MAX)
+				return -EOVERFLOW;
+
+			*val = fps->speed;
+			return 0;
+		default:
+			return -EOPNOTSUPP;
+		}
+	case hwmon_power:
+		switch (attr) {
+		case hwmon_power_input:
+			fps = acpi_fan_get_current_fps(fan, fst.control);
+			if (!fps)
+				return -EIO;
+
+			if (!acpi_fan_power_valid(fps->power))
+				return -ENODEV;
+
+			if (fps->power > LONG_MAX / MICROWATT_PER_MILLIWATT)
+				return -EOVERFLOW;
+
+			*val = fps->power * MICROWATT_PER_MILLIWATT;
+			return 0;
+		default:
+			return -EOPNOTSUPP;
+		}
+	default:
+		return -EOPNOTSUPP;
+	}
+}
+
+static const struct hwmon_ops acpi_fan_hwmon_ops = {
+	.is_visible = acpi_fan_hwmon_is_visible,
+	.read = acpi_fan_hwmon_read,
+};
+
+static const struct hwmon_channel_info * const acpi_fan_hwmon_info[] = {
+	HWMON_CHANNEL_INFO(fan, HWMON_F_INPUT | HWMON_F_TARGET),
+	HWMON_CHANNEL_INFO(power, HWMON_P_INPUT),
+	NULL
+};
+
+static const struct hwmon_chip_info acpi_fan_hwmon_chip_info = {
+	.ops = &acpi_fan_hwmon_ops,
+	.info = acpi_fan_hwmon_info,
+};
+
+void acpi_fan_notify_hwmon(struct device *dev)
+{
+	struct acpi_fan *fan = dev_get_drvdata(dev);
+
+	hwmon_notify_event(fan->hdev, hwmon_fan, hwmon_fan_input, 0);
+}
+
+int devm_acpi_fan_create_hwmon(struct device *dev)
+{
+	struct acpi_fan *fan = dev_get_drvdata(dev);
+
+	fan->hdev = devm_hwmon_device_register_with_info(dev, "acpi_fan", fan,
+							 &acpi_fan_hwmon_chip_info, NULL);
+
+	return PTR_ERR_OR_ZERO(fan->hdev);
+}
diff --git a/drivers/acpi/glue.c b/drivers/acpi/glue.c
index 36b24b0658cb..a194f30876c5 100644
--- a/drivers/acpi/glue.c
+++ b/drivers/acpi/glue.c
@@ -6,6 +6,8 @@
  * Copyright (c) 2005 Intel Corp.
  */
 
+#define pr_fmt(fmt) "ACPI: " fmt
+
 #include <linux/acpi_iort.h>
 #include <linux/export.h>
 #include <linux/init.h>
@@ -15,21 +17,12 @@
 #include <linux/rwsem.h>
 #include <linux/acpi.h>
 #include <linux/dma-mapping.h>
+#include <linux/pci.h>
+#include <linux/pci-acpi.h>
 #include <linux/platform_device.h>
 
 #include "internal.h"
 
-#define ACPI_GLUE_DEBUG	0
-#if ACPI_GLUE_DEBUG
-#define DBG(fmt, ...)						\
-	printk(KERN_DEBUG PREFIX fmt, ##__VA_ARGS__)
-#else
-#define DBG(fmt, ...)						\
-do {								\
-	if (0)							\
-		printk(KERN_DEBUG PREFIX fmt, ##__VA_ARGS__);	\
-} while (0)
-#endif
 static LIST_HEAD(bus_type_list);
 static DECLARE_RWSEM(bus_type_sem);
 
@@ -44,7 +37,7 @@ int register_acpi_bus_type(struct acpi_bus_type *type)
 		down_write(&bus_type_sem);
 		list_add_tail(&type->list, &bus_type_list);
 		up_write(&bus_type_sem);
-		printk(KERN_INFO PREFIX "bus type %s registered\n", type->name);
+		pr_info("bus type %s registered\n", type->name);
 		return 0;
 	}
 	return -ENODEV;
@@ -59,8 +52,7 @@ int unregister_acpi_bus_type(struct acpi_bus_type *type)
 		down_write(&bus_type_sem);
 		list_del_init(&type->list);
 		up_write(&bus_type_sem);
-		printk(KERN_INFO PREFIX "bus type %s unregistered\n",
-		       type->name);
+		pr_info("bus type %s unregistered\n", type->name);
 		return 0;
 	}
 	return -ENODEV;
@@ -83,21 +75,41 @@ static struct acpi_bus_type *acpi_get_bus_type(struct device *dev)
 }
 
 #define FIND_CHILD_MIN_SCORE	1
-#define FIND_CHILD_MAX_SCORE	2
+#define FIND_CHILD_MID_SCORE	2
+#define FIND_CHILD_MAX_SCORE	3
+
+static int match_any(struct acpi_device *adev, void *not_used)
+{
+	return 1;
+}
+
+static bool acpi_dev_has_children(struct acpi_device *adev)
+{
+	return acpi_dev_for_each_child(adev, match_any, NULL) > 0;
+}
 
 static int find_child_checks(struct acpi_device *adev, bool check_children)
 {
-	bool sta_present = true;
 	unsigned long long sta;
 	acpi_status status;
 
-	status = acpi_evaluate_integer(adev->handle, "_STA", NULL, &sta);
-	if (status == AE_NOT_FOUND)
-		sta_present = false;
-	else if (ACPI_FAILURE(status) || !(sta & ACPI_STA_DEVICE_ENABLED))
+	if (check_children && !acpi_dev_has_children(adev))
 		return -ENODEV;
 
-	if (check_children && list_empty(&adev->children))
+	status = acpi_evaluate_integer(adev->handle, "_STA", NULL, &sta);
+	if (status == AE_NOT_FOUND) {
+		/*
+		 * Special case: backlight device objects without _STA are
+		 * preferred to other objects with the same _ADR value, because
+		 * it is more likely that they are actually useful.
+		 */
+		if (adev->pnp.type.backlight)
+			return FIND_CHILD_MID_SCORE;
+
+		return FIND_CHILD_MIN_SCORE;
+	}
+
+	if (ACPI_FAILURE(status) || !(sta & ACPI_STA_DEVICE_ENABLED))
 		return -ENODEV;
 
 	/*
@@ -107,61 +119,103 @@ static int find_child_checks(struct acpi_device *adev, bool check_children)
 	 * matched going forward.  [This means a second spec violation in a row,
 	 * so whatever we do here is best effort anyway.]
 	 */
-	return sta_present && !adev->pnp.type.platform_id ?
-			FIND_CHILD_MAX_SCORE : FIND_CHILD_MIN_SCORE;
+	if (adev->pnp.type.platform_id)
+		return FIND_CHILD_MIN_SCORE;
+
+	return FIND_CHILD_MAX_SCORE;
 }
 
-struct acpi_device *acpi_find_child_device(struct acpi_device *parent,
-					   u64 address, bool check_children)
+struct find_child_walk_data {
+	struct acpi_device *adev;
+	u64 address;
+	int score;
+	bool check_sta;
+	bool check_children;
+};
+
+static int check_one_child(struct acpi_device *adev, void *data)
 {
-	struct acpi_device *adev, *ret = NULL;
-	int ret_score = 0;
-
-	if (!parent)
-		return NULL;
-
-	list_for_each_entry(adev, &parent->children, node) {
-		unsigned long long addr;
-		acpi_status status;
-		int score;
-
-		status = acpi_evaluate_integer(adev->handle, METHOD_NAME__ADR,
-					       NULL, &addr);
-		if (ACPI_FAILURE(status) || addr != address)
-			continue;
-
-		if (!ret) {
-			/* This is the first matching object.  Save it. */
-			ret = adev;
-			continue;
-		}
+	struct find_child_walk_data *wd = data;
+	int score;
+
+	if (!adev->pnp.type.bus_address || acpi_device_adr(adev) != wd->address)
+		return 0;
+
+	if (!wd->adev) {
 		/*
-		 * There is more than one matching device object with the same
-		 * _ADR value.  That really is unexpected, so we are kind of
-		 * beyond the scope of the spec here.  We have to choose which
-		 * one to return, though.
-		 *
-		 * First, check if the previously found object is good enough
-		 * and return it if so.  Second, do the same for the object that
-		 * we've just found.
+		 * This is the first matching object, so save it.  If it is not
+		 * necessary to look for any other matching objects, stop the
+		 * search.
 		 */
-		if (!ret_score) {
-			ret_score = find_child_checks(ret, check_children);
-			if (ret_score == FIND_CHILD_MAX_SCORE)
-				return ret;
-		}
-		score = find_child_checks(adev, check_children);
-		if (score == FIND_CHILD_MAX_SCORE) {
-			return adev;
-		} else if (score > ret_score) {
-			ret = adev;
-			ret_score = score;
-		}
+		wd->adev = adev;
+		return !(wd->check_sta || wd->check_children);
 	}
-	return ret;
+
+	/*
+	 * There is more than one matching device object with the same _ADR
+	 * value.  That really is unexpected, so we are kind of beyond the scope
+	 * of the spec here.  We have to choose which one to return, though.
+	 *
+	 * First, get the score for the previously found object and terminate
+	 * the walk if it is maximum.
+	*/
+	if (!wd->score) {
+		score = find_child_checks(wd->adev, wd->check_children);
+		if (score == FIND_CHILD_MAX_SCORE)
+			return 1;
+
+		wd->score = score;
+	}
+	/*
+	 * Second, if the object that has just been found has a better score,
+	 * replace the previously found one with it and terminate the walk if
+	 * the new score is maximum.
+	 */
+	score = find_child_checks(adev, wd->check_children);
+	if (score > wd->score) {
+		wd->adev = adev;
+		if (score == FIND_CHILD_MAX_SCORE)
+			return 1;
+
+		wd->score = score;
+	}
+
+	/* Continue, because there may be better matches. */
+	return 0;
+}
+
+static struct acpi_device *acpi_find_child(struct acpi_device *parent,
+					   u64 address, bool check_children,
+					   bool check_sta)
+{
+	struct find_child_walk_data wd = {
+		.address = address,
+		.check_children = check_children,
+		.check_sta = check_sta,
+		.adev = NULL,
+		.score = 0,
+	};
+
+	if (parent)
+		acpi_dev_for_each_child(parent, check_one_child, &wd);
+
+	return wd.adev;
+}
+
+struct acpi_device *acpi_find_child_device(struct acpi_device *parent,
+					   u64 address, bool check_children)
+{
+	return acpi_find_child(parent, address, check_children, true);
 }
 EXPORT_SYMBOL_GPL(acpi_find_child_device);
 
+struct acpi_device *acpi_find_child_by_adr(struct acpi_device *adev,
+					   acpi_bus_address adr)
+{
+	return acpi_find_child(adev, adr, false, false);
+}
+EXPORT_SYMBOL_GPL(acpi_find_child_by_adr);
+
 static void acpi_physnode_link_name(char *buf, unsigned int node_id)
 {
 	if (node_id > 0)
@@ -190,7 +244,7 @@ int acpi_bind_one(struct device *dev, struct acpi_device *acpi_dev)
 	if (!acpi_dev)
 		return -EINVAL;
 
-	get_device(&acpi_dev->dev);
+	acpi_dev_get(acpi_dev);
 	get_device(dev);
 	physical_node = kzalloc(sizeof(*physical_node), GFP_KERNEL);
 	if (!physical_node) {
@@ -217,7 +271,7 @@ int acpi_bind_one(struct device *dev, struct acpi_device *acpi_dev)
 				goto err;
 
 			put_device(dev);
-			put_device(&acpi_dev->dev);
+			acpi_dev_put(acpi_dev);
 			return 0;
 		}
 		if (pn->node_id == node_id) {
@@ -257,7 +311,7 @@ int acpi_bind_one(struct device *dev, struct acpi_device *acpi_dev)
  err:
 	ACPI_COMPANION_SET(dev, NULL);
 	put_device(dev);
-	put_device(&acpi_dev->dev);
+	acpi_dev_put(acpi_dev);
 	return retval;
 }
 EXPORT_SYMBOL_GPL(acpi_bind_one);
@@ -285,7 +339,7 @@ int acpi_unbind_one(struct device *dev)
 			ACPI_COMPANION_SET(dev, NULL);
 			/* Drop references taken by acpi_bind_one(). */
 			put_device(dev);
-			put_device(&acpi_dev->dev);
+			acpi_dev_put(acpi_dev);
 			kfree(entry);
 			break;
 		}
@@ -295,82 +349,66 @@ int acpi_unbind_one(struct device *dev)
 }
 EXPORT_SYMBOL_GPL(acpi_unbind_one);
 
-static int acpi_device_notify(struct device *dev)
+void acpi_device_notify(struct device *dev)
 {
-	struct acpi_bus_type *type = acpi_get_bus_type(dev);
 	struct acpi_device *adev;
 	int ret;
 
 	ret = acpi_bind_one(dev, NULL);
-	if (ret && type) {
-		struct acpi_device *adev;
+	if (ret) {
+		struct acpi_bus_type *type = acpi_get_bus_type(dev);
+
+		if (!type)
+			goto err;
 
 		adev = type->find_companion(dev);
 		if (!adev) {
-			DBG("Unable to get handle for %s\n", dev_name(dev));
-			ret = -ENODEV;
-			goto out;
+			dev_dbg(dev, "ACPI companion not found\n");
+			goto err;
 		}
 		ret = acpi_bind_one(dev, adev);
 		if (ret)
-			goto out;
-	}
-	adev = ACPI_COMPANION(dev);
-	if (!adev)
-		goto out;
+			goto err;
 
-	if (dev_is_platform(dev))
-		acpi_configure_pmsi_domain(dev);
+		if (type->setup) {
+			type->setup(dev);
+			goto done;
+		}
+	} else {
+		adev = ACPI_COMPANION(dev);
+
+		if (dev_is_pci(dev)) {
+			pci_acpi_setup(dev, adev);
+			goto done;
+		} else if (dev_is_platform(dev)) {
+			acpi_configure_pmsi_domain(dev);
+		}
+	}
 
-	if (type && type->setup)
-		type->setup(dev);
-	else if (adev->handler && adev->handler->bind)
+	if (adev->handler && adev->handler->bind)
 		adev->handler->bind(dev);
 
- out:
-#if ACPI_GLUE_DEBUG
-	if (!ret) {
-		struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
+done:
+	acpi_handle_debug(ACPI_HANDLE(dev), "Bound to device %s\n",
+			  dev_name(dev));
 
-		acpi_get_name(ACPI_HANDLE(dev), ACPI_FULL_PATHNAME, &buffer);
-		DBG("Device %s -> %s\n", dev_name(dev), (char *)buffer.pointer);
-		kfree(buffer.pointer);
-	} else
-		DBG("Device %s -> No ACPI support\n", dev_name(dev));
-#endif
+	return;
 
-	return ret;
+err:
+	dev_dbg(dev, "No ACPI support\n");
 }
 
-static int acpi_device_notify_remove(struct device *dev)
+void acpi_device_notify_remove(struct device *dev)
 {
 	struct acpi_device *adev = ACPI_COMPANION(dev);
-	struct acpi_bus_type *type;
 
 	if (!adev)
-		return 0;
+		return;
 
-	type = acpi_get_bus_type(dev);
-	if (type && type->cleanup)
-		type->cleanup(dev);
+	if (dev_is_pci(dev))
+		pci_acpi_cleanup(dev, adev);
 	else if (adev->handler && adev->handler->unbind)
 		adev->handler->unbind(dev);
 
 	acpi_unbind_one(dev);
-	return 0;
-}
-
-int acpi_platform_notify(struct device *dev, enum kobject_action action)
-{
-	switch (action) {
-	case KOBJ_ADD:
-		acpi_device_notify(dev);
-		break;
-	case KOBJ_REMOVE:
-		acpi_device_notify_remove(dev);
-		break;
-	default:
-		break;
-	}
-	return 0;
 }
diff --git a/drivers/acpi/hed.c b/drivers/acpi/hed.c
index cf148287e2ba..3499f86c411e 100644
--- a/drivers/acpi/hed.c
+++ b/drivers/acpi/hed.c
@@ -42,24 +42,33 @@ EXPORT_SYMBOL_GPL(unregister_acpi_hed_notifier);
  * it is used by HEST Generic Hardware Error Source with notify type
  * SCI.
  */
-static void acpi_hed_notify(struct acpi_device *device, u32 event)
+static void acpi_hed_notify(acpi_handle handle, u32 event, void *data)
 {
 	blocking_notifier_call_chain(&acpi_hed_notify_list, 0, NULL);
 }
 
 static int acpi_hed_add(struct acpi_device *device)
 {
+	int err;
+
 	/* Only one hardware error device */
 	if (hed_handle)
 		return -EINVAL;
 	hed_handle = device->handle;
-	return 0;
+
+	err = acpi_dev_install_notify_handler(device, ACPI_DEVICE_NOTIFY,
+					      acpi_hed_notify, device);
+	if (err)
+		hed_handle = NULL;
+
+	return err;
 }
 
-static int acpi_hed_remove(struct acpi_device *device)
+static void acpi_hed_remove(struct acpi_device *device)
 {
+	acpi_dev_remove_notify_handler(device, ACPI_DEVICE_NOTIFY,
+				       acpi_hed_notify);
 	hed_handle = NULL;
-	return 0;
 }
 
 static struct acpi_driver acpi_hed_driver = {
@@ -69,12 +78,15 @@ static struct acpi_driver acpi_hed_driver = {
 	.ops = {
 		.add = acpi_hed_add,
 		.remove = acpi_hed_remove,
-		.notify = acpi_hed_notify,
 	},
 };
-module_acpi_driver(acpi_hed_driver);
 
-ACPI_MODULE_NAME("hed");
+static int __init acpi_hed_driver_init(void)
+{
+	return acpi_bus_register_driver(&acpi_hed_driver);
+}
+subsys_initcall(acpi_hed_driver_init);
+
 MODULE_AUTHOR("Huang Ying");
 MODULE_DESCRIPTION("ACPI Hardware Error Device Driver");
 MODULE_LICENSE("GPL");
diff --git a/drivers/acpi/internal.h b/drivers/acpi/internal.h
index e387517d3354..40f875b265a9 100644
--- a/drivers/acpi/internal.h
+++ b/drivers/acpi/internal.h
@@ -9,12 +9,14 @@
 #ifndef _ACPI_INTERNAL_H_
 #define _ACPI_INTERNAL_H_
 
-#define PREFIX "ACPI: "
+#include <linux/idr.h>
+
+extern struct acpi_device *acpi_root;
 
 int early_acpi_osi_init(void);
 int acpi_osi_init(void);
 acpi_status acpi_os_initialize1(void);
-int acpi_scan_init(void);
+void acpi_scan_init(void);
 #ifdef CONFIG_PCI
 void acpi_pci_root_init(void);
 void acpi_pci_link_init(void);
@@ -25,12 +27,6 @@ static inline void acpi_pci_link_init(void) {}
 void acpi_processor_init(void);
 void acpi_platform_init(void);
 void acpi_pnp_init(void);
-void acpi_int340x_thermal_init(void);
-#ifdef CONFIG_ARM_AMBA
-void acpi_amba_init(void);
-#else
-static inline void acpi_amba_init(void) {}
-#endif
 int acpi_sysfs_init(void);
 void acpi_gpe_apply_masked_gpes(void);
 void acpi_container_init(void);
@@ -72,7 +68,8 @@ void acpi_debugfs_init(void);
 #else
 static inline void acpi_debugfs_init(void) { return; }
 #endif
-#ifdef CONFIG_PCI
+
+#if defined(CONFIG_X86) && defined(CONFIG_PCI)
 void acpi_lpss_init(void);
 #else
 static inline void acpi_lpss_init(void) {}
@@ -86,7 +83,21 @@ void acpi_device_hotplug(struct acpi_device *adev, u32 src);
 bool acpi_scan_is_offline(struct acpi_device *adev, bool uevent);
 
 acpi_status acpi_sysfs_table_handler(u32 event, void *table, void *context);
-void acpi_scan_table_handler(u32 event, void *table, void *context);
+void acpi_scan_table_notify(void);
+
+int acpi_active_trip_temp(struct acpi_device *adev, int id, int *ret_temp);
+int acpi_passive_trip_temp(struct acpi_device *adev, int *ret_temp);
+int acpi_hot_trip_temp(struct acpi_device *adev, int *ret_temp);
+int acpi_critical_trip_temp(struct acpi_device *adev, int *ret_temp);
+
+#ifdef CONFIG_ARM64
+int acpi_arch_thermal_cpufreq_pctg(void);
+#else
+static inline int acpi_arch_thermal_cpufreq_pctg(void)
+{
+	return 0;
+}
+#endif
 
 /* --------------------------------------------------------------------------
                      Device Node Initialization / Removal
@@ -97,19 +108,21 @@ void acpi_scan_table_handler(u32 event, void *table, void *context);
 extern struct list_head acpi_bus_id_list;
 
 struct acpi_device_bus_id {
-	char bus_id[15];
-	unsigned int instance_no;
+	const char *bus_id;
+	struct ida instance_ida;
 	struct list_head node;
 };
 
-int acpi_device_add(struct acpi_device *device,
-		    void (*release)(struct device *));
 void acpi_init_device_object(struct acpi_device *device, acpi_handle handle,
-			     int type, unsigned long long sta);
-int acpi_device_setup_files(struct acpi_device *dev);
+			     int type, void (*release)(struct device *));
+int acpi_tie_acpi_dev(struct acpi_device *adev);
+int acpi_device_add(struct acpi_device *device);
+void acpi_device_setup_files(struct acpi_device *dev);
 void acpi_device_remove_files(struct acpi_device *dev);
+extern const struct attribute_group *acpi_groups[];
 void acpi_device_add_finalize(struct acpi_device *device);
 void acpi_free_pnp_ids(struct acpi_device_pnp *pnp);
+bool acpi_device_is_enabled(const struct acpi_device *adev);
 bool acpi_device_is_present(const struct acpi_device *adev);
 bool acpi_device_is_battery(struct acpi_device *adev);
 bool acpi_device_is_first_physical_node(struct acpi_device *adev,
@@ -119,25 +132,26 @@ int acpi_bus_register_early_device(int type);
 /* --------------------------------------------------------------------------
                      Device Matching and Notification
    -------------------------------------------------------------------------- */
-struct acpi_device *acpi_companion_match(const struct device *dev);
-int __acpi_device_uevent_modalias(struct acpi_device *adev,
+const struct acpi_device *acpi_companion_match(const struct device *dev);
+int __acpi_device_uevent_modalias(const struct acpi_device *adev,
 				  struct kobj_uevent_env *env);
 
 /* --------------------------------------------------------------------------
                                   Power Resource
    -------------------------------------------------------------------------- */
-int acpi_power_init(void);
+void acpi_power_resources_init(void);
 void acpi_power_resources_list_free(struct list_head *list);
 int acpi_extract_power_resources(union acpi_object *package, unsigned int start,
 				 struct list_head *list);
-int acpi_add_power_resource(acpi_handle handle);
+struct acpi_device *acpi_add_power_resource(acpi_handle handle);
 void acpi_power_add_remove_device(struct acpi_device *adev, bool add);
 int acpi_power_wakeup_list_init(struct list_head *list, int *system_level);
 int acpi_device_sleep_wake(struct acpi_device *dev,
-                           int enable, int sleep_state, int dev_state);
+			   int enable, int sleep_state, int dev_state);
 int acpi_power_get_inferred_state(struct acpi_device *device, int *state);
 int acpi_power_on_resources(struct acpi_device *device, int state);
 int acpi_power_transition(struct acpi_device *device, int state);
+void acpi_turn_off_unused_power_resources(void);
 
 /* --------------------------------------------------------------------------
                               Device Power Management
@@ -149,20 +163,34 @@ int acpi_wakeup_device_init(void);
                                   Processor
    -------------------------------------------------------------------------- */
 #ifdef CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC
+void acpi_early_processor_control_setup(void);
 void acpi_early_processor_set_pdc(void);
+#ifdef CONFIG_X86
+void acpi_proc_quirk_mwait_check(void);
+#else
+static inline void acpi_proc_quirk_mwait_check(void) {}
+#endif
+bool processor_physically_present(acpi_handle handle);
 #else
-static inline void acpi_early_processor_set_pdc(void) {}
+static inline void acpi_early_processor_control_setup(void) {}
 #endif
 
-#ifdef CONFIG_X86
-void acpi_early_processor_osc(void);
+#ifdef CONFIG_ACPI_PROCESSOR_CSTATE
+void acpi_idle_rescan_dead_smt_siblings(void);
 #else
-static inline void acpi_early_processor_osc(void) {}
+static inline void acpi_idle_rescan_dead_smt_siblings(void) {}
 #endif
 
 /* --------------------------------------------------------------------------
                                   Embedded Controller
    -------------------------------------------------------------------------- */
+
+enum acpi_ec_event_state {
+	EC_EVENT_READY = 0,	/* Event work can be submitted */
+	EC_EVENT_IN_PROGRESS,	/* Event work is pending or being processed */
+	EC_EVENT_COMPLETE,	/* Event work processing has completed */
+};
+
 struct acpi_ec {
 	acpi_handle handle;
 	int gpe;
@@ -179,7 +207,10 @@ struct acpi_ec {
 	spinlock_t lock;
 	struct work_struct work;
 	unsigned long timestamp;
-	unsigned long nr_pending_queries;
+	enum acpi_ec_event_state event_state;
+	unsigned int events_to_process;
+	unsigned int events_in_progress;
+	unsigned int queries_in_progress;
 	bool busy_polling;
 	unsigned int polling_guard;
 };
@@ -190,6 +221,8 @@ extern struct acpi_ec *first_ec;
 /* External interfaces use first EC only, so remember */
 typedef int (*acpi_ec_query_func) (void *data);
 
+#ifdef CONFIG_ACPI_EC
+
 void acpi_ec_init(void);
 void acpi_ec_ecdt_probe(void);
 void acpi_ec_dsdt_probe(void);
@@ -199,13 +232,36 @@ int acpi_ec_add_query_handler(struct acpi_ec *ec, u8 query_bit,
 			      acpi_handle handle, acpi_ec_query_func func,
 			      void *data);
 void acpi_ec_remove_query_handler(struct acpi_ec *ec, u8 query_bit);
+void acpi_ec_register_opregions(struct acpi_device *adev);
 
 #ifdef CONFIG_PM_SLEEP
 void acpi_ec_flush_work(void);
-bool acpi_ec_other_gpes_active(void);
 bool acpi_ec_dispatch_gpe(void);
 #endif
 
+#else
+
+static inline void acpi_ec_init(void) {}
+static inline void acpi_ec_ecdt_probe(void) {}
+static inline void acpi_ec_dsdt_probe(void) {}
+static inline void acpi_ec_block_transactions(void) {}
+static inline void acpi_ec_unblock_transactions(void) {}
+static inline int acpi_ec_add_query_handler(struct acpi_ec *ec, u8 query_bit,
+			      acpi_handle handle, acpi_ec_query_func func,
+			      void *data)
+{
+	return -ENXIO;
+}
+static inline void acpi_ec_remove_query_handler(struct acpi_ec *ec, u8 query_bit) {}
+static inline void acpi_ec_register_opregions(struct acpi_device *adev) {}
+
+static inline void acpi_ec_flush_work(void) {}
+static inline bool acpi_ec_dispatch_gpe(void)
+{
+	return false;
+}
+
+#endif
 
 /*--------------------------------------------------------------------------
                                   Suspend/Resume
@@ -232,6 +288,15 @@ static inline int suspend_nvs_save(void) { return 0; }
 static inline void suspend_nvs_restore(void) {}
 #endif
 
+#ifdef CONFIG_X86
+bool force_storage_d3(void);
+#else
+static inline bool force_storage_d3(void)
+{
+	return false;
+}
+#endif
+
 /*--------------------------------------------------------------------------
 				Device properties
   -------------------------------------------------------------------------- */
@@ -262,4 +327,18 @@ void acpi_init_lpit(void);
 static inline void acpi_init_lpit(void) { }
 #endif
 
+/*--------------------------------------------------------------------------
+		ACPI _CRS CSI-2 and MIPI DisCo for Imaging
+  -------------------------------------------------------------------------- */
+
+void acpi_mipi_check_crs_csi2(acpi_handle handle);
+void acpi_mipi_scan_crs_csi2(void);
+void acpi_mipi_init_crs_csi2_swnodes(void);
+void acpi_mipi_crs_csi2_cleanup(void);
+#ifdef CONFIG_X86
+bool acpi_graph_ignore_port(acpi_handle handle);
+#else
+static inline bool acpi_graph_ignore_port(acpi_handle handle) { return false; }
+#endif
+
 #endif /* _ACPI_INTERNAL_H_ */
diff --git a/drivers/acpi/ioapic.c b/drivers/acpi/ioapic.c
index a690c7b18623..6677955b4a8e 100644
--- a/drivers/acpi/ioapic.c
+++ b/drivers/acpi/ioapic.c
@@ -24,6 +24,7 @@
 #include <linux/acpi.h>
 #include <linux/pci.h>
 #include <acpi/acpi.h>
+#include "internal.h"
 
 struct acpi_pci_ioapic {
 	acpi_handle	root_handle;
diff --git a/drivers/acpi/irq.c b/drivers/acpi/irq.c
index e209081d644b..d1595156c86a 100644
--- a/drivers/acpi/irq.c
+++ b/drivers/acpi/irq.c
@@ -12,7 +12,8 @@
 
 enum acpi_irq_model_id acpi_irq_model;
 
-static struct fwnode_handle *acpi_gsi_domain_id;
+static acpi_gsi_domain_disp_fn acpi_get_gsi_domain_id;
+static u32 (*acpi_gsi_to_irq_fallback)(u32 gsi);
 
 /**
  * acpi_gsi_to_irq() - Retrieve the linux irq number for a given GSI
@@ -26,14 +27,18 @@ static struct fwnode_handle *acpi_gsi_domain_id;
  */
 int acpi_gsi_to_irq(u32 gsi, unsigned int *irq)
 {
-	struct irq_domain *d = irq_find_matching_fwnode(acpi_gsi_domain_id,
-							DOMAIN_BUS_ANY);
+	struct irq_domain *d;
 
+	d = irq_find_matching_fwnode(acpi_get_gsi_domain_id(gsi),
+					DOMAIN_BUS_ANY);
 	*irq = irq_find_mapping(d, gsi);
 	/*
-	 * *irq == 0 means no mapping, that should
-	 * be reported as a failure
+	 * *irq == 0 means no mapping, that should be reported as a
+	 * failure, unless there is an arch-specific fallback handler.
 	 */
+	if (!*irq && acpi_gsi_to_irq_fallback)
+		*irq = acpi_gsi_to_irq_fallback(gsi);
+
 	return (*irq > 0) ? 0 : -EINVAL;
 }
 EXPORT_SYMBOL_GPL(acpi_gsi_to_irq);
@@ -52,18 +57,23 @@ int acpi_register_gsi(struct device *dev, u32 gsi, int trigger,
 		      int polarity)
 {
 	struct irq_fwspec fwspec;
+	unsigned int irq;
 
-	if (WARN_ON(!acpi_gsi_domain_id)) {
+	fwspec.fwnode = acpi_get_gsi_domain_id(gsi);
+	if (WARN_ON(!fwspec.fwnode)) {
 		pr_warn("GSI: No registered irqchip, giving up\n");
 		return -EINVAL;
 	}
 
-	fwspec.fwnode = acpi_gsi_domain_id;
 	fwspec.param[0] = gsi;
 	fwspec.param[1] = acpi_dev_get_irq_type(trigger, polarity);
 	fwspec.param_count = 2;
 
-	return irq_create_fwspec_mapping(&fwspec);
+	irq = irq_create_fwspec_mapping(&fwspec);
+	if (!irq)
+		return -EINVAL;
+
+	return irq;
 }
 EXPORT_SYMBOL_GPL(acpi_register_gsi);
 
@@ -73,10 +83,15 @@ EXPORT_SYMBOL_GPL(acpi_register_gsi);
  */
 void acpi_unregister_gsi(u32 gsi)
 {
-	struct irq_domain *d = irq_find_matching_fwnode(acpi_gsi_domain_id,
-							DOMAIN_BUS_ANY);
-	int irq = irq_find_mapping(d, gsi);
+	struct irq_domain *d;
+	int irq;
+
+	if (WARN_ON(acpi_irq_model == ACPI_IRQ_MODEL_GIC && gsi < 16))
+		return;
 
+	d = irq_find_matching_fwnode(acpi_get_gsi_domain_id(gsi),
+				     DOMAIN_BUS_ANY);
+	irq = irq_find_mapping(d, gsi);
 	irq_dispose_mapping(irq);
 }
 EXPORT_SYMBOL_GPL(acpi_unregister_gsi);
@@ -84,6 +99,7 @@ EXPORT_SYMBOL_GPL(acpi_unregister_gsi);
 /**
  * acpi_get_irq_source_fwhandle() - Retrieve fwhandle from IRQ resource source.
  * @source: acpi_resource_source to use for the lookup.
+ * @gsi: GSI IRQ number
  *
  * Description:
  * Retrieve the fwhandle of the device referenced by the given IRQ resource
@@ -93,7 +109,8 @@ EXPORT_SYMBOL_GPL(acpi_unregister_gsi);
  * The referenced device fwhandle or NULL on failure
  */
 static struct fwnode_handle *
-acpi_get_irq_source_fwhandle(const struct acpi_resource_source *source)
+acpi_get_irq_source_fwhandle(const struct acpi_resource_source *source,
+			     u32 gsi)
 {
 	struct fwnode_handle *result;
 	struct acpi_device *device;
@@ -101,18 +118,18 @@ acpi_get_irq_source_fwhandle(const struct acpi_resource_source *source)
 	acpi_status status;
 
 	if (!source->string_length)
-		return acpi_gsi_domain_id;
+		return acpi_get_gsi_domain_id(gsi);
 
 	status = acpi_get_handle(NULL, source->string_ptr, &handle);
 	if (WARN_ON(ACPI_FAILURE(status)))
 		return NULL;
 
-	device = acpi_bus_get_acpi_device(handle);
+	device = acpi_get_acpi_dev(handle);
 	if (WARN_ON(!device))
 		return NULL;
 
 	result = &device->fwnode;
-	acpi_bus_put_acpi_device(device);
+	acpi_put_acpi_dev(device);
 	return result;
 }
 
@@ -136,6 +153,7 @@ struct acpi_irq_parse_one_ctx {
  * @polarity: polarity attributes of hwirq
  * @polarity: polarity attributes of hwirq
  * @shareable: shareable attributes of hwirq
+ * @wake_capable: wake capable attribute of hwirq
  * @ctx: acpi_irq_parse_one_ctx updated by this function
  *
  * Description:
@@ -145,12 +163,13 @@ struct acpi_irq_parse_one_ctx {
 static inline void acpi_irq_parse_one_match(struct fwnode_handle *fwnode,
 					    u32 hwirq, u8 triggering,
 					    u8 polarity, u8 shareable,
+					    u8 wake_capable,
 					    struct acpi_irq_parse_one_ctx *ctx)
 {
 	if (!fwnode)
 		return;
 	ctx->rc = 0;
-	*ctx->res_flags = acpi_dev_irq_flags(triggering, polarity, shareable);
+	*ctx->res_flags = acpi_dev_irq_flags(triggering, polarity, shareable, wake_capable);
 	ctx->fwspec->fwnode = fwnode;
 	ctx->fwspec->param[0] = hwirq;
 	ctx->fwspec->param[1] = acpi_dev_get_irq_type(triggering, polarity);
@@ -190,10 +209,10 @@ static acpi_status acpi_irq_parse_one_cb(struct acpi_resource *ares,
 			ctx->index -= irq->interrupt_count;
 			return AE_OK;
 		}
-		fwnode = acpi_gsi_domain_id;
+		fwnode = acpi_get_gsi_domain_id(irq->interrupts[ctx->index]);
 		acpi_irq_parse_one_match(fwnode, irq->interrupts[ctx->index],
 					 irq->triggering, irq->polarity,
-					 irq->shareable, ctx);
+					 irq->shareable, irq->wake_capable, ctx);
 		return AE_CTRL_TERMINATE;
 	case ACPI_RESOURCE_TYPE_EXTENDED_IRQ:
 		eirq = &ares->data.extended_irq;
@@ -203,10 +222,11 @@ static acpi_status acpi_irq_parse_one_cb(struct acpi_resource *ares,
 			ctx->index -= eirq->interrupt_count;
 			return AE_OK;
 		}
-		fwnode = acpi_get_irq_source_fwhandle(&eirq->resource_source);
+		fwnode = acpi_get_irq_source_fwhandle(&eirq->resource_source,
+						      eirq->interrupts[ctx->index]);
 		acpi_irq_parse_one_match(fwnode, eirq->interrupts[ctx->index],
 					 eirq->triggering, eirq->polarity,
-					 eirq->shareable, ctx);
+					 eirq->shareable, eirq->wake_capable, ctx);
 		return AE_CTRL_TERMINATE;
 	}
 
@@ -280,17 +300,58 @@ int acpi_irq_get(acpi_handle handle, unsigned int index, struct resource *res)
 }
 EXPORT_SYMBOL_GPL(acpi_irq_get);
 
+const struct cpumask *acpi_irq_get_affinity(acpi_handle handle,
+					    unsigned int index)
+{
+	struct irq_fwspec_info info;
+	struct irq_fwspec fwspec;
+	unsigned long flags;
+
+	if (acpi_irq_parse_one(handle, index, &fwspec, &flags))
+		return NULL;
+
+	if (irq_populate_fwspec_info(&fwspec, &info))
+		return NULL;
+
+	if (!(info.flags & IRQ_FWSPEC_INFO_AFFINITY_VALID))
+		return NULL;
+
+	return info.affinity;
+}
+
 /**
  * acpi_set_irq_model - Setup the GSI irqdomain information
  * @model: the value assigned to acpi_irq_model
- * @fwnode: the irq_domain identifier for mapping and looking up
- *          GSI interrupts
+ * @fn: a dispatcher function that will return the domain fwnode
+ *	for a given GSI
  */
 void __init acpi_set_irq_model(enum acpi_irq_model_id model,
-			       struct fwnode_handle *fwnode)
+			       acpi_gsi_domain_disp_fn fn)
 {
 	acpi_irq_model = model;
-	acpi_gsi_domain_id = fwnode;
+	acpi_get_gsi_domain_id = fn;
+}
+
+/*
+ * acpi_get_gsi_dispatcher() - Get the GSI dispatcher function
+ *
+ * Return the dispatcher function that computes the domain fwnode for
+ * a given GSI.
+ */
+acpi_gsi_domain_disp_fn acpi_get_gsi_dispatcher(void)
+{
+	return acpi_get_gsi_domain_id;
+}
+EXPORT_SYMBOL_GPL(acpi_get_gsi_dispatcher);
+
+/**
+ * acpi_set_gsi_to_irq_fallback - Register a GSI transfer
+ * callback to fallback to arch specified implementation.
+ * @fn: arch-specific fallback handler
+ */
+void __init acpi_set_gsi_to_irq_fallback(u32 (*fn)(u32))
+{
+	acpi_gsi_to_irq_fallback = fn;
 }
 
 /**
@@ -308,8 +369,14 @@ struct irq_domain *acpi_irq_create_hierarchy(unsigned int flags,
 					     const struct irq_domain_ops *ops,
 					     void *host_data)
 {
-	struct irq_domain *d = irq_find_matching_fwnode(acpi_gsi_domain_id,
-							DOMAIN_BUS_ANY);
+	struct irq_domain *d;
+
+	/* This only works for the GIC model... */
+	if (acpi_irq_model != ACPI_IRQ_MODEL_GIC)
+		return NULL;
+
+	d = irq_find_matching_fwnode(acpi_get_gsi_domain_id(0),
+				     DOMAIN_BUS_ANY);
 
 	if (!d)
 		return NULL;
diff --git a/drivers/acpi/mipi-disco-img.c b/drivers/acpi/mipi-disco-img.c
new file mode 100644
index 000000000000..5b85989f96be
--- /dev/null
+++ b/drivers/acpi/mipi-disco-img.c
@@ -0,0 +1,805 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * MIPI DisCo for Imaging support.
+ *
+ * Copyright (C) 2023 Intel Corporation
+ *
+ * Support MIPI DisCo for Imaging by parsing ACPI _CRS CSI-2 records defined in
+ * Section 6.4.3.8.2.4 "Camera Serial Interface (CSI-2) Connection Resource
+ * Descriptor" of ACPI 6.5 and using device properties defined by the MIPI DisCo
+ * for Imaging specification.
+ *
+ * The implementation looks for the information in the ACPI namespace (CSI-2
+ * resource descriptors in _CRS) and constructs software nodes compatible with
+ * Documentation/firmware-guide/acpi/dsd/graph.rst to represent the CSI-2
+ * connection graph.  The software nodes are then populated with the data
+ * extracted from the _CRS CSI-2 resource descriptors and the MIPI DisCo
+ * for Imaging device properties present in _DSD for the ACPI device objects
+ * with CSI-2 connections.
+ */
+
+#include <linux/acpi.h>
+#include <linux/dmi.h>
+#include <linux/limits.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/overflow.h>
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+
+#include <media/v4l2-fwnode.h>
+
+#include "internal.h"
+
+static LIST_HEAD(acpi_mipi_crs_csi2_list);
+
+static void acpi_mipi_data_tag(acpi_handle handle, void *context)
+{
+}
+
+/* Connection data extracted from one _CRS CSI-2 resource descriptor. */
+struct crs_csi2_connection {
+	struct list_head entry;
+	struct acpi_resource_csi2_serialbus csi2_data;
+	acpi_handle remote_handle;
+	char remote_name[];
+};
+
+/* Data extracted from _CRS CSI-2 resource descriptors for one device. */
+struct crs_csi2 {
+	struct list_head entry;
+	acpi_handle handle;
+	struct acpi_device_software_nodes *swnodes;
+	struct list_head connections;
+	u32 port_count;
+};
+
+struct csi2_resources_walk_data {
+	acpi_handle handle;
+	struct list_head connections;
+};
+
+static acpi_status parse_csi2_resource(struct acpi_resource *res, void *context)
+{
+	struct csi2_resources_walk_data *crwd = context;
+	struct acpi_resource_csi2_serialbus *csi2_res;
+	struct acpi_resource_source *csi2_res_src;
+	u16 csi2_res_src_length;
+	struct crs_csi2_connection *conn;
+	acpi_handle remote_handle;
+
+	if (res->type != ACPI_RESOURCE_TYPE_SERIAL_BUS)
+		return AE_OK;
+
+	csi2_res = &res->data.csi2_serial_bus;
+
+	if (csi2_res->type != ACPI_RESOURCE_SERIAL_TYPE_CSI2)
+		return AE_OK;
+
+	csi2_res_src = &csi2_res->resource_source;
+	if (ACPI_FAILURE(acpi_get_handle(NULL, csi2_res_src->string_ptr,
+					 &remote_handle))) {
+		acpi_handle_debug(crwd->handle,
+				  "unable to find resource source\n");
+		return AE_OK;
+	}
+	csi2_res_src_length = csi2_res_src->string_length;
+	if (!csi2_res_src_length) {
+		acpi_handle_debug(crwd->handle,
+				  "invalid resource source string length\n");
+		return AE_OK;
+	}
+
+	conn = kmalloc(struct_size(conn, remote_name, csi2_res_src_length + 1),
+		       GFP_KERNEL);
+	if (!conn)
+		return AE_OK;
+
+	conn->csi2_data = *csi2_res;
+	strscpy(conn->remote_name, csi2_res_src->string_ptr, csi2_res_src_length);
+	conn->csi2_data.resource_source.string_ptr = conn->remote_name;
+	conn->remote_handle = remote_handle;
+
+	list_add(&conn->entry, &crwd->connections);
+
+	return AE_OK;
+}
+
+static struct crs_csi2 *acpi_mipi_add_crs_csi2(acpi_handle handle,
+					       struct list_head *list)
+{
+	struct crs_csi2 *csi2;
+
+	csi2 = kzalloc(sizeof(*csi2), GFP_KERNEL);
+	if (!csi2)
+		return NULL;
+
+	csi2->handle = handle;
+	INIT_LIST_HEAD(&csi2->connections);
+	csi2->port_count = 1;
+
+	if (ACPI_FAILURE(acpi_attach_data(handle, acpi_mipi_data_tag, csi2))) {
+		kfree(csi2);
+		return NULL;
+	}
+
+	list_add(&csi2->entry, list);
+
+	return csi2;
+}
+
+static struct crs_csi2 *acpi_mipi_get_crs_csi2(acpi_handle handle)
+{
+	struct crs_csi2 *csi2;
+
+	if (ACPI_FAILURE(acpi_get_data_full(handle, acpi_mipi_data_tag,
+					    (void **)&csi2, NULL)))
+		return NULL;
+
+	return csi2;
+}
+
+static void csi_csr2_release_connections(struct list_head *list)
+{
+	struct crs_csi2_connection *conn, *conn_tmp;
+
+	list_for_each_entry_safe(conn, conn_tmp, list, entry) {
+		list_del(&conn->entry);
+		kfree(conn);
+	}
+}
+
+static void acpi_mipi_del_crs_csi2(struct crs_csi2 *csi2)
+{
+	list_del(&csi2->entry);
+	acpi_detach_data(csi2->handle, acpi_mipi_data_tag);
+	kfree(csi2->swnodes);
+	csi_csr2_release_connections(&csi2->connections);
+	kfree(csi2);
+}
+
+/**
+ * acpi_mipi_check_crs_csi2 - Look for CSI-2 resources in _CRS
+ * @handle: Device object handle to evaluate _CRS for.
+ *
+ * Find all CSI-2 resource descriptors in the given device's _CRS
+ * and collect them into a list.
+ */
+void acpi_mipi_check_crs_csi2(acpi_handle handle)
+{
+	struct csi2_resources_walk_data crwd = {
+		.handle = handle,
+		.connections = LIST_HEAD_INIT(crwd.connections),
+	};
+	struct crs_csi2 *csi2;
+
+	/*
+	 * Avoid allocating _CRS CSI-2 objects for devices without any CSI-2
+	 * resource descriptions in _CRS to reduce overhead.
+	 */
+	acpi_walk_resources(handle, METHOD_NAME__CRS, parse_csi2_resource, &crwd);
+	if (list_empty(&crwd.connections))
+		return;
+
+	/*
+	 * Create a _CRS CSI-2 entry to store the extracted connection
+	 * information and add it to the global list.
+	 */
+	csi2 = acpi_mipi_add_crs_csi2(handle, &acpi_mipi_crs_csi2_list);
+	if (!csi2) {
+		csi_csr2_release_connections(&crwd.connections);
+		return; /* Nothing really can be done about this. */
+	}
+
+	list_replace(&crwd.connections, &csi2->connections);
+}
+
+#define NO_CSI2_PORT (UINT_MAX - 1)
+
+static void alloc_crs_csi2_swnodes(struct crs_csi2 *csi2)
+{
+	size_t port_count = csi2->port_count;
+	struct acpi_device_software_nodes *swnodes;
+	size_t alloc_size;
+	unsigned int i;
+
+	/*
+	 * Allocate memory for ports, node pointers (number of nodes +
+	 * 1 (guardian), nodes (root + number of ports * 2 (because for
+	 * every port there is an endpoint)).
+	 */
+	if (check_mul_overflow(sizeof(*swnodes->ports) +
+			       sizeof(*swnodes->nodes) * 2 +
+			       sizeof(*swnodes->nodeptrs) * 2,
+			       port_count, &alloc_size) ||
+	    check_add_overflow(sizeof(*swnodes) +
+			       sizeof(*swnodes->nodes) +
+			       sizeof(*swnodes->nodeptrs) * 2,
+			       alloc_size, &alloc_size)) {
+		acpi_handle_info(csi2->handle,
+				 "too many _CRS CSI-2 resource handles (%zu)",
+				 port_count);
+		return;
+	}
+
+	swnodes = kmalloc(alloc_size, GFP_KERNEL);
+	if (!swnodes)
+		return;
+
+	swnodes->ports = (struct acpi_device_software_node_port *)(swnodes + 1);
+	swnodes->nodes = (struct software_node *)(swnodes->ports + port_count);
+	swnodes->nodeptrs = (const struct software_node **)(swnodes->nodes + 1 +
+				2 * port_count);
+	swnodes->num_ports = port_count;
+
+	for (i = 0; i < 2 * port_count + 1; i++)
+		swnodes->nodeptrs[i] = &swnodes->nodes[i];
+
+	swnodes->nodeptrs[i] = NULL;
+
+	for (i = 0; i < port_count; i++)
+		swnodes->ports[i].port_nr = NO_CSI2_PORT;
+
+	csi2->swnodes = swnodes;
+}
+
+#define ACPI_CRS_CSI2_PHY_TYPE_C	0
+#define ACPI_CRS_CSI2_PHY_TYPE_D	1
+
+static unsigned int next_csi2_port_index(struct acpi_device_software_nodes *swnodes,
+					 unsigned int port_nr)
+{
+	unsigned int i;
+
+	for (i = 0; i < swnodes->num_ports; i++) {
+		struct acpi_device_software_node_port *port = &swnodes->ports[i];
+
+		if (port->port_nr == port_nr)
+			return i;
+
+		if (port->port_nr == NO_CSI2_PORT) {
+			port->port_nr = port_nr;
+			return i;
+		}
+	}
+
+	return NO_CSI2_PORT;
+}
+
+/* Print graph port name into a buffer, return non-zero on failure. */
+#define GRAPH_PORT_NAME(var, num)					    \
+	(snprintf((var), sizeof(var), SWNODE_GRAPH_PORT_NAME_FMT, (num)) >= \
+	 sizeof(var))
+
+static void extract_crs_csi2_conn_info(acpi_handle local_handle,
+				       struct acpi_device_software_nodes *local_swnodes,
+				       struct crs_csi2_connection *conn)
+{
+	struct crs_csi2 *remote_csi2 = acpi_mipi_get_crs_csi2(conn->remote_handle);
+	struct acpi_device_software_nodes *remote_swnodes;
+	struct acpi_device_software_node_port *local_port, *remote_port;
+	struct software_node *local_node, *remote_node;
+	unsigned int local_index, remote_index;
+	unsigned int bus_type;
+
+	/*
+	 * If the previous steps have failed to make room for a _CRS CSI-2
+	 * representation for the remote end of the given connection, skip it.
+	 */
+	if (!remote_csi2)
+		return;
+
+	remote_swnodes = remote_csi2->swnodes;
+	if (!remote_swnodes)
+		return;
+
+	switch (conn->csi2_data.phy_type) {
+	case ACPI_CRS_CSI2_PHY_TYPE_C:
+		bus_type = V4L2_FWNODE_BUS_TYPE_CSI2_CPHY;
+		break;
+
+	case ACPI_CRS_CSI2_PHY_TYPE_D:
+		bus_type = V4L2_FWNODE_BUS_TYPE_CSI2_DPHY;
+		break;
+
+	default:
+		acpi_handle_info(local_handle, "unknown CSI-2 PHY type %u\n",
+				 conn->csi2_data.phy_type);
+		return;
+	}
+
+	local_index = next_csi2_port_index(local_swnodes,
+					   conn->csi2_data.local_port_instance);
+	if (WARN_ON_ONCE(local_index >= local_swnodes->num_ports))
+		return;
+
+	remote_index = next_csi2_port_index(remote_swnodes,
+					    conn->csi2_data.resource_source.index);
+	if (WARN_ON_ONCE(remote_index >= remote_swnodes->num_ports))
+		return;
+
+	local_port = &local_swnodes->ports[local_index];
+	local_node = &local_swnodes->nodes[ACPI_DEVICE_SWNODE_EP(local_index)];
+	local_port->crs_csi2_local = true;
+
+	remote_port = &remote_swnodes->ports[remote_index];
+	remote_node = &remote_swnodes->nodes[ACPI_DEVICE_SWNODE_EP(remote_index)];
+
+	local_port->remote_ep[0] = SOFTWARE_NODE_REFERENCE(remote_node);
+	remote_port->remote_ep[0] = SOFTWARE_NODE_REFERENCE(local_node);
+
+	local_port->ep_props[ACPI_DEVICE_SWNODE_EP_REMOTE_EP] =
+			PROPERTY_ENTRY_REF_ARRAY("remote-endpoint",
+						 local_port->remote_ep);
+
+	local_port->ep_props[ACPI_DEVICE_SWNODE_EP_BUS_TYPE] =
+			PROPERTY_ENTRY_U32("bus-type", bus_type);
+
+	local_port->ep_props[ACPI_DEVICE_SWNODE_EP_REG] =
+			PROPERTY_ENTRY_U32("reg", 0);
+
+	local_port->port_props[ACPI_DEVICE_SWNODE_PORT_REG] =
+			PROPERTY_ENTRY_U32("reg", conn->csi2_data.local_port_instance);
+
+	if (GRAPH_PORT_NAME(local_port->port_name,
+			    conn->csi2_data.local_port_instance))
+		acpi_handle_info(local_handle, "local port %u name too long",
+				 conn->csi2_data.local_port_instance);
+
+	remote_port->ep_props[ACPI_DEVICE_SWNODE_EP_REMOTE_EP] =
+			PROPERTY_ENTRY_REF_ARRAY("remote-endpoint",
+						 remote_port->remote_ep);
+
+	remote_port->ep_props[ACPI_DEVICE_SWNODE_EP_BUS_TYPE] =
+			PROPERTY_ENTRY_U32("bus-type", bus_type);
+
+	remote_port->ep_props[ACPI_DEVICE_SWNODE_EP_REG] =
+			PROPERTY_ENTRY_U32("reg", 0);
+
+	remote_port->port_props[ACPI_DEVICE_SWNODE_PORT_REG] =
+			PROPERTY_ENTRY_U32("reg", conn->csi2_data.resource_source.index);
+
+	if (GRAPH_PORT_NAME(remote_port->port_name,
+			    conn->csi2_data.resource_source.index))
+		acpi_handle_info(local_handle, "remote port %u name too long",
+				 conn->csi2_data.resource_source.index);
+}
+
+static void prepare_crs_csi2_swnodes(struct crs_csi2 *csi2)
+{
+	struct acpi_device_software_nodes *local_swnodes = csi2->swnodes;
+	acpi_handle local_handle = csi2->handle;
+	struct crs_csi2_connection *conn;
+
+	/* Bail out if the allocation of swnodes has failed. */
+	if (!local_swnodes)
+		return;
+
+	list_for_each_entry(conn, &csi2->connections, entry)
+		extract_crs_csi2_conn_info(local_handle, local_swnodes, conn);
+}
+
+/**
+ * acpi_mipi_scan_crs_csi2 - Create ACPI _CRS CSI-2 software nodes
+ *
+ * Note that this function must be called before any struct acpi_device objects
+ * are bound to any ACPI drivers or scan handlers, so it cannot assume the
+ * existence of struct acpi_device objects for every device present in the ACPI
+ * namespace.
+ *
+ * acpi_scan_lock in scan.c must be held when calling this function.
+ */
+void acpi_mipi_scan_crs_csi2(void)
+{
+	struct crs_csi2 *csi2;
+	LIST_HEAD(aux_list);
+
+	/* Count references to each ACPI handle in the CSI-2 connection graph. */
+	list_for_each_entry(csi2, &acpi_mipi_crs_csi2_list, entry) {
+		struct crs_csi2_connection *conn;
+
+		list_for_each_entry(conn, &csi2->connections, entry) {
+			struct crs_csi2 *remote_csi2;
+
+			csi2->port_count++;
+
+			remote_csi2 = acpi_mipi_get_crs_csi2(conn->remote_handle);
+			if (remote_csi2) {
+				remote_csi2->port_count++;
+				continue;
+			}
+			/*
+			 * The remote endpoint has no _CRS CSI-2 list entry yet,
+			 * so create one for it and add it to the list.
+			 */
+			acpi_mipi_add_crs_csi2(conn->remote_handle, &aux_list);
+		}
+	}
+	list_splice(&aux_list, &acpi_mipi_crs_csi2_list);
+
+	/*
+	 * Allocate software nodes for representing the CSI-2 information.
+	 *
+	 * This needs to be done for all of the list entries in one go, because
+	 * they may point to each other without restrictions and the next step
+	 * relies on the availability of swnodes memory for each list entry.
+	 */
+	list_for_each_entry(csi2, &acpi_mipi_crs_csi2_list, entry)
+		alloc_crs_csi2_swnodes(csi2);
+
+	/*
+	 * Set up software node properties using data from _CRS CSI-2 resource
+	 * descriptors.
+	 */
+	list_for_each_entry(csi2, &acpi_mipi_crs_csi2_list, entry)
+		prepare_crs_csi2_swnodes(csi2);
+}
+
+/*
+ * Get the index of the next property in the property array, with a given
+ * maximum value.
+ */
+#define NEXT_PROPERTY(index, max)			\
+	(WARN_ON((index) > ACPI_DEVICE_SWNODE_##max) ?	\
+	 ACPI_DEVICE_SWNODE_##max : (index)++)
+
+static void init_csi2_port_local(struct acpi_device *adev,
+				 struct acpi_device_software_node_port *port,
+				 struct fwnode_handle *port_fwnode,
+				 unsigned int index)
+{
+	acpi_handle handle = acpi_device_handle(adev);
+	unsigned int num_link_freqs;
+	int ret;
+
+	ret = fwnode_property_count_u64(port_fwnode, "mipi-img-link-frequencies");
+	if (ret <= 0)
+		return;
+
+	num_link_freqs = ret;
+	if (num_link_freqs > ACPI_DEVICE_CSI2_DATA_LANES) {
+		acpi_handle_info(handle, "Too many link frequencies: %u\n",
+				 num_link_freqs);
+		num_link_freqs = ACPI_DEVICE_CSI2_DATA_LANES;
+	}
+
+	ret = fwnode_property_read_u64_array(port_fwnode,
+					     "mipi-img-link-frequencies",
+					     port->link_frequencies,
+					     num_link_freqs);
+	if (ret) {
+		acpi_handle_info(handle, "Unable to get link frequencies (%d)\n",
+				 ret);
+		return;
+	}
+
+	port->ep_props[NEXT_PROPERTY(index, EP_LINK_FREQUENCIES)] =
+				PROPERTY_ENTRY_U64_ARRAY_LEN("link-frequencies",
+							     port->link_frequencies,
+							     num_link_freqs);
+}
+
+static void init_csi2_port(struct acpi_device *adev,
+			   struct acpi_device_software_nodes *swnodes,
+			   struct acpi_device_software_node_port *port,
+			   struct fwnode_handle *port_fwnode,
+			   unsigned int port_index)
+{
+	unsigned int ep_prop_index = ACPI_DEVICE_SWNODE_EP_CLOCK_LANES;
+	acpi_handle handle = acpi_device_handle(adev);
+	u8 val[ACPI_DEVICE_CSI2_DATA_LANES];
+	int num_lanes = 0;
+	int ret;
+
+	if (GRAPH_PORT_NAME(port->port_name, port->port_nr))
+		return;
+
+	swnodes->nodes[ACPI_DEVICE_SWNODE_PORT(port_index)] =
+			SOFTWARE_NODE(port->port_name, port->port_props,
+				      &swnodes->nodes[ACPI_DEVICE_SWNODE_ROOT]);
+
+	ret = fwnode_property_read_u8(port_fwnode, "mipi-img-clock-lane", val);
+	if (!ret)
+		port->ep_props[NEXT_PROPERTY(ep_prop_index, EP_CLOCK_LANES)] =
+			PROPERTY_ENTRY_U32("clock-lanes", val[0]);
+
+	ret = fwnode_property_count_u8(port_fwnode, "mipi-img-data-lanes");
+	if (ret > 0) {
+		num_lanes = ret;
+
+		if (num_lanes > ACPI_DEVICE_CSI2_DATA_LANES) {
+			acpi_handle_info(handle, "Too many data lanes: %u\n",
+					 num_lanes);
+			num_lanes = ACPI_DEVICE_CSI2_DATA_LANES;
+		}
+
+		ret = fwnode_property_read_u8_array(port_fwnode,
+						    "mipi-img-data-lanes",
+						    val, num_lanes);
+		if (!ret) {
+			unsigned int i;
+
+			for (i = 0; i < num_lanes; i++)
+				port->data_lanes[i] = val[i];
+
+			port->ep_props[NEXT_PROPERTY(ep_prop_index, EP_DATA_LANES)] =
+				PROPERTY_ENTRY_U32_ARRAY_LEN("data-lanes",
+							     port->data_lanes,
+							     num_lanes);
+		}
+	}
+
+	ret = fwnode_property_count_u8(port_fwnode, "mipi-img-lane-polarities");
+	if (ret < 0) {
+		acpi_handle_debug(handle, "Lane polarity bytes missing\n");
+	} else if (ret * BITS_PER_TYPE(u8) < num_lanes + 1) {
+		acpi_handle_info(handle, "Too few lane polarity bits (%zu vs. %d)\n",
+				 ret * BITS_PER_TYPE(u8), num_lanes + 1);
+	} else {
+		unsigned long mask = 0;
+		int byte_count = ret;
+		unsigned int i;
+
+		/*
+		 * The total number of lanes is ACPI_DEVICE_CSI2_DATA_LANES + 1
+		 * (data lanes + clock lane).  It is not expected to ever be
+		 * greater than the number of bits in an unsigned long
+		 * variable, but ensure that this is the case.
+		 */
+		BUILD_BUG_ON(BITS_PER_TYPE(unsigned long) <= ACPI_DEVICE_CSI2_DATA_LANES);
+
+		if (byte_count > sizeof(mask)) {
+			acpi_handle_info(handle, "Too many lane polarities: %d\n",
+					 byte_count);
+			byte_count = sizeof(mask);
+		}
+		fwnode_property_read_u8_array(port_fwnode, "mipi-img-lane-polarities",
+					      val, byte_count);
+
+		for (i = 0; i < byte_count; i++)
+			mask |= (unsigned long)val[i] << BITS_PER_TYPE(u8) * i;
+
+		for (i = 0; i <= num_lanes; i++)
+			port->lane_polarities[i] = test_bit(i, &mask);
+
+		port->ep_props[NEXT_PROPERTY(ep_prop_index, EP_LANE_POLARITIES)] =
+				PROPERTY_ENTRY_U32_ARRAY_LEN("lane-polarities",
+							     port->lane_polarities,
+							     num_lanes + 1);
+	}
+
+	swnodes->nodes[ACPI_DEVICE_SWNODE_EP(port_index)] =
+		SOFTWARE_NODE("endpoint@0", swnodes->ports[port_index].ep_props,
+			      &swnodes->nodes[ACPI_DEVICE_SWNODE_PORT(port_index)]);
+
+	if (port->crs_csi2_local)
+		init_csi2_port_local(adev, port, port_fwnode, ep_prop_index);
+}
+
+#define MIPI_IMG_PORT_PREFIX "mipi-img-port-"
+
+static struct fwnode_handle *get_mipi_port_handle(struct fwnode_handle *adev_fwnode,
+						  unsigned int port_nr)
+{
+	char port_name[sizeof(MIPI_IMG_PORT_PREFIX) + 2];
+
+	if (snprintf(port_name, sizeof(port_name), "%s%u",
+		     MIPI_IMG_PORT_PREFIX, port_nr) >= sizeof(port_name))
+		return NULL;
+
+	return fwnode_get_named_child_node(adev_fwnode, port_name);
+}
+
+static void init_crs_csi2_swnodes(struct crs_csi2 *csi2)
+{
+	struct acpi_buffer buffer = { .length = ACPI_ALLOCATE_BUFFER };
+	struct acpi_device_software_nodes *swnodes = csi2->swnodes;
+	acpi_handle handle = csi2->handle;
+	unsigned int prop_index = 0;
+	struct fwnode_handle *adev_fwnode;
+	struct acpi_device *adev;
+	acpi_status status;
+	unsigned int i;
+	u32 val;
+	int ret;
+
+	/*
+	 * Bail out if the swnodes are not available (either they have not been
+	 * allocated or they have been assigned to the device already).
+	 */
+	if (!swnodes)
+		return;
+
+	adev = acpi_fetch_acpi_dev(handle);
+	if (!adev)
+		return;
+
+	adev_fwnode = acpi_fwnode_handle(adev);
+
+	/*
+	 * If the "rotation" property is not present, but _PLD is there,
+	 * evaluate it to get the "rotation" value.
+	 */
+	if (!fwnode_property_present(adev_fwnode, "rotation")) {
+		struct acpi_pld_info *pld;
+
+		if (acpi_get_physical_device_location(handle, &pld)) {
+			swnodes->dev_props[NEXT_PROPERTY(prop_index, DEV_ROTATION)] =
+					PROPERTY_ENTRY_U32("rotation",
+							   pld->rotation * 45U);
+			kfree(pld);
+		}
+	}
+
+	if (!fwnode_property_read_u32(adev_fwnode, "mipi-img-clock-frequency", &val))
+		swnodes->dev_props[NEXT_PROPERTY(prop_index, DEV_CLOCK_FREQUENCY)] =
+			PROPERTY_ENTRY_U32("clock-frequency", val);
+
+	if (!fwnode_property_read_u32(adev_fwnode, "mipi-img-led-max-current", &val))
+		swnodes->dev_props[NEXT_PROPERTY(prop_index, DEV_LED_MAX_MICROAMP)] =
+			PROPERTY_ENTRY_U32("led-max-microamp", val);
+
+	if (!fwnode_property_read_u32(adev_fwnode, "mipi-img-flash-max-current", &val))
+		swnodes->dev_props[NEXT_PROPERTY(prop_index, DEV_FLASH_MAX_MICROAMP)] =
+			PROPERTY_ENTRY_U32("flash-max-microamp", val);
+
+	if (!fwnode_property_read_u32(adev_fwnode, "mipi-img-flash-max-timeout-us", &val))
+		swnodes->dev_props[NEXT_PROPERTY(prop_index, DEV_FLASH_MAX_TIMEOUT_US)] =
+			PROPERTY_ENTRY_U32("flash-max-timeout-us", val);
+
+	status = acpi_get_name(handle, ACPI_FULL_PATHNAME, &buffer);
+	if (ACPI_FAILURE(status)) {
+		acpi_handle_info(handle, "Unable to get the path name\n");
+		return;
+	}
+
+	swnodes->nodes[ACPI_DEVICE_SWNODE_ROOT] =
+			SOFTWARE_NODE(buffer.pointer, swnodes->dev_props, NULL);
+
+	for (i = 0; i < swnodes->num_ports; i++) {
+		struct acpi_device_software_node_port *port = &swnodes->ports[i];
+		struct fwnode_handle *port_fwnode;
+
+		/*
+		 * The MIPI DisCo for Imaging specification defines _DSD device
+		 * properties for providing CSI-2 port parameters that can be
+		 * accessed through the generic device properties framework.  To
+		 * access them, it is first necessary to find the data node
+		 * representing the port under the given ACPI device object.
+		 */
+		port_fwnode = get_mipi_port_handle(adev_fwnode, port->port_nr);
+		if (!port_fwnode) {
+			acpi_handle_info(handle,
+					 "MIPI port name too long for port %u\n",
+					 port->port_nr);
+			continue;
+		}
+
+		init_csi2_port(adev, swnodes, port, port_fwnode, i);
+
+		fwnode_handle_put(port_fwnode);
+	}
+
+	ret = software_node_register_node_group(swnodes->nodeptrs);
+	if (ret < 0) {
+		acpi_handle_info(handle,
+				 "Unable to register software nodes (%d)\n", ret);
+		return;
+	}
+
+	adev->swnodes = swnodes;
+	adev_fwnode->secondary = software_node_fwnode(swnodes->nodes);
+
+	/*
+	 * Prevents the swnodes from this csi2 entry from being assigned again
+	 * or freed prematurely.
+	 */
+	csi2->swnodes = NULL;
+}
+
+/**
+ * acpi_mipi_init_crs_csi2_swnodes - Initialize _CRS CSI-2 software nodes
+ *
+ * Use MIPI DisCo for Imaging device properties to finalize the initialization
+ * of CSI-2 software nodes for all ACPI device objects that have been already
+ * enumerated.
+ */
+void acpi_mipi_init_crs_csi2_swnodes(void)
+{
+	struct crs_csi2 *csi2, *csi2_tmp;
+
+	list_for_each_entry_safe(csi2, csi2_tmp, &acpi_mipi_crs_csi2_list, entry)
+		init_crs_csi2_swnodes(csi2);
+}
+
+/**
+ * acpi_mipi_crs_csi2_cleanup - Free _CRS CSI-2 temporary data
+ */
+void acpi_mipi_crs_csi2_cleanup(void)
+{
+	struct crs_csi2 *csi2, *csi2_tmp;
+
+	list_for_each_entry_safe(csi2, csi2_tmp, &acpi_mipi_crs_csi2_list, entry)
+		acpi_mipi_del_crs_csi2(csi2);
+}
+
+#ifdef CONFIG_X86
+#include <asm/cpu_device_id.h>
+#include <asm/intel-family.h>
+
+/* CPU matches for Dell generations with broken ACPI MIPI DISCO info */
+static const struct x86_cpu_id dell_broken_mipi_disco_cpu_gens[] = {
+	X86_MATCH_VFM(INTEL_TIGERLAKE, NULL),
+	X86_MATCH_VFM(INTEL_TIGERLAKE_L, NULL),
+	X86_MATCH_VFM(INTEL_ALDERLAKE, NULL),
+	X86_MATCH_VFM(INTEL_ALDERLAKE_L, NULL),
+	X86_MATCH_VFM(INTEL_RAPTORLAKE, NULL),
+	X86_MATCH_VFM(INTEL_RAPTORLAKE_P, NULL),
+	X86_MATCH_VFM(INTEL_RAPTORLAKE_S, NULL),
+	{}
+};
+
+static const char *strnext(const char *s1, const char *s2)
+{
+	s1 = strstr(s1, s2);
+
+	if (!s1)
+		return NULL;
+
+	return s1 + strlen(s2);
+}
+
+/**
+ * acpi_graph_ignore_port - Tell whether a port node should be ignored
+ * @handle: The ACPI handle of the node (which may be a port node)
+ *
+ * Return: true if a port node should be ignored and the data to that should
+ * come from other sources instead (Windows ACPI definitions and
+ * ipu-bridge). This is currently used to ignore bad port nodes related to IPU6
+ * ("IPU?") and camera sensor devices ("LNK?") in certain Dell systems with
+ * Intel VSC.
+ */
+bool acpi_graph_ignore_port(acpi_handle handle)
+{
+	const char *path = NULL, *orig_path;
+	static bool dmi_tested, ignore_port;
+
+	if (!dmi_tested) {
+		if (dmi_name_in_vendors("Dell Inc.") &&
+		    x86_match_cpu(dell_broken_mipi_disco_cpu_gens))
+			ignore_port = true;
+
+		dmi_tested = true;
+	}
+
+	if (!ignore_port)
+		return false;
+
+	/* Check if the device is either "IPU" or "LNK" (sensor). */
+	orig_path = acpi_handle_path(handle);
+	if (!orig_path)
+		return false;
+	path = strnext(orig_path, "IPU");
+	if (!path)
+		path = strnext(orig_path, "LNK");
+	if (!path)
+		goto out_free;
+
+	if (!(isdigit(path[0]) && path[1] == '.'))
+		goto out_free;
+
+	/* Check if the node has a "PRT" prefix. */
+	path = strnext(path, "PRT");
+	if (path && isdigit(path[0]) && !path[1]) {
+		acpi_handle_debug(handle, "ignoring data node\n");
+
+		kfree(orig_path);
+		return true;
+	}
+
+out_free:
+	kfree(orig_path);
+	return false;
+}
+#endif
diff --git a/drivers/acpi/nfit/core.c b/drivers/acpi/nfit/core.c
index fa4500f9cfd1..3eb56b77cb6d 100644
--- a/drivers/acpi/nfit/core.c
+++ b/drivers/acpi/nfit/core.c
@@ -5,6 +5,7 @@
 #include <linux/list_sort.h>
 #include <linux/libnvdimm.h>
 #include <linux/module.h>
+#include <linux/nospec.h>
 #include <linux/mutex.h>
 #include <linux/ndctl.h>
 #include <linux/sysfs.h>
@@ -73,6 +74,18 @@ const guid_t *to_nfit_uuid(enum nfit_uuids id)
 }
 EXPORT_SYMBOL(to_nfit_uuid);
 
+static const guid_t *to_nfit_bus_uuid(int family)
+{
+	if (WARN_ONCE(family == NVDIMM_BUS_FAMILY_NFIT,
+			"only secondary bus families can be translated\n"))
+		return NULL;
+	/*
+	 * The index of bus UUIDs starts immediately following the last
+	 * NVDIMM/leaf family.
+	 */
+	return to_nfit_uuid(family + NVDIMM_FAMILY_MAX);
+}
+
 static struct acpi_device *to_acpi_dev(struct acpi_nfit_desc *acpi_desc)
 {
 	struct nvdimm_bus_descriptor *nd_desc = &acpi_desc->nd_desc;
@@ -270,18 +283,19 @@ err:
 
 static union acpi_object *int_to_buf(union acpi_object *integer)
 {
-	union acpi_object *buf = ACPI_ALLOCATE(sizeof(*buf) + 4);
+	union acpi_object *buf = NULL;
 	void *dst = NULL;
 
-	if (!buf)
-		goto err;
-
 	if (integer->type != ACPI_TYPE_INTEGER) {
 		WARN_ONCE(1, "BIOS bug, unexpected element type: %d\n",
 				integer->type);
 		goto err;
 	}
 
+	buf = ACPI_ALLOCATE(sizeof(*buf) + 4);
+	if (!buf)
+		goto err;
+
 	dst = buf + 1;
 	buf->type = ACPI_TYPE_BUFFER;
 	buf->buffer.length = 4;
@@ -362,24 +376,8 @@ static u8 nfit_dsm_revid(unsigned family, unsigned func)
 {
 	static const u8 revid_table[NVDIMM_FAMILY_MAX+1][NVDIMM_CMD_MAX+1] = {
 		[NVDIMM_FAMILY_INTEL] = {
-			[NVDIMM_INTEL_GET_MODES] = 2,
-			[NVDIMM_INTEL_GET_FWINFO] = 2,
-			[NVDIMM_INTEL_START_FWUPDATE] = 2,
-			[NVDIMM_INTEL_SEND_FWUPDATE] = 2,
-			[NVDIMM_INTEL_FINISH_FWUPDATE] = 2,
-			[NVDIMM_INTEL_QUERY_FWUPDATE] = 2,
-			[NVDIMM_INTEL_SET_THRESHOLD] = 2,
-			[NVDIMM_INTEL_INJECT_ERROR] = 2,
-			[NVDIMM_INTEL_GET_SECURITY_STATE] = 2,
-			[NVDIMM_INTEL_SET_PASSPHRASE] = 2,
-			[NVDIMM_INTEL_DISABLE_PASSPHRASE] = 2,
-			[NVDIMM_INTEL_UNLOCK_UNIT] = 2,
-			[NVDIMM_INTEL_FREEZE_LOCK] = 2,
-			[NVDIMM_INTEL_SECURE_ERASE] = 2,
-			[NVDIMM_INTEL_OVERWRITE] = 2,
-			[NVDIMM_INTEL_QUERY_OVERWRITE] = 2,
-			[NVDIMM_INTEL_SET_MASTER_PASSPHRASE] = 2,
-			[NVDIMM_INTEL_MASTER_SECURE_ERASE] = 2,
+			[NVDIMM_INTEL_GET_MODES ...
+				NVDIMM_INTEL_FW_ACTIVATE_ARM] = 2,
 		},
 	};
 	u8 id;
@@ -406,7 +404,7 @@ static bool payload_dumpable(struct nvdimm *nvdimm, unsigned int func)
 }
 
 static int cmd_to_func(struct nfit_mem *nfit_mem, unsigned int cmd,
-		struct nd_cmd_pkg *call_pkg)
+		struct nd_cmd_pkg *call_pkg, int *family)
 {
 	if (call_pkg) {
 		int i;
@@ -417,6 +415,7 @@ static int cmd_to_func(struct nfit_mem *nfit_mem, unsigned int cmd,
 		for (i = 0; i < ARRAY_SIZE(call_pkg->nd_reserved2); i++)
 			if (call_pkg->nd_reserved2[i])
 				return -EINVAL;
+		*family = call_pkg->nd_family;
 		return call_pkg->nd_command;
 	}
 
@@ -450,13 +449,19 @@ int acpi_nfit_ctl(struct nvdimm_bus_descriptor *nd_desc, struct nvdimm *nvdimm,
 	acpi_handle handle;
 	const guid_t *guid;
 	int func, rc, i;
+	int family = 0;
 
 	if (cmd_rc)
 		*cmd_rc = -EINVAL;
 
-	if (cmd == ND_CMD_CALL)
+	if (cmd == ND_CMD_CALL) {
+		if (!buf || buf_len < sizeof(*call_pkg))
+			return -EINVAL;
+
 		call_pkg = buf;
-	func = cmd_to_func(nfit_mem, cmd, call_pkg);
+	}
+
+	func = cmd_to_func(nfit_mem, cmd, call_pkg, &family);
 	if (func < 0)
 		return func;
 
@@ -478,9 +483,20 @@ int acpi_nfit_ctl(struct nvdimm_bus_descriptor *nd_desc, struct nvdimm *nvdimm,
 
 		cmd_name = nvdimm_bus_cmd_name(cmd);
 		cmd_mask = nd_desc->cmd_mask;
-		dsm_mask = nd_desc->bus_dsm_mask;
+		if (cmd == ND_CMD_CALL && call_pkg->nd_family) {
+			family = call_pkg->nd_family;
+			if (call_pkg->nd_family > NVDIMM_BUS_FAMILY_MAX ||
+			    !test_bit(family, &nd_desc->bus_family_mask))
+				return -EINVAL;
+			family = array_index_nospec(family,
+						    NVDIMM_BUS_FAMILY_MAX + 1);
+			dsm_mask = acpi_desc->family_dsm_mask[family];
+			guid = to_nfit_bus_uuid(family);
+		} else {
+			dsm_mask = acpi_desc->bus_dsm_mask;
+			guid = to_nfit_uuid(NFIT_DEV_BUS);
+		}
 		desc = nd_cmd_bus_desc(cmd);
-		guid = to_nfit_uuid(NFIT_DEV_BUS);
 		handle = adev->handle;
 		dimm_name = "bus";
 	}
@@ -516,8 +532,8 @@ int acpi_nfit_ctl(struct nvdimm_bus_descriptor *nd_desc, struct nvdimm *nvdimm,
 		in_buf.buffer.length = call_pkg->nd_size_in;
 	}
 
-	dev_dbg(dev, "%s cmd: %d: func: %d input length: %d\n",
-		dimm_name, cmd, func, in_buf.buffer.length);
+	dev_dbg(dev, "%s cmd: %d: family: %d func: %d input length: %d\n",
+		dimm_name, cmd, family, func, in_buf.buffer.length);
 	if (payload_dumpable(nvdimm, func))
 		print_hex_dump_debug("nvdimm in  ", DUMP_PREFIX_OFFSET, 4, 4,
 				in_buf.buffer.pointer,
@@ -667,14 +683,23 @@ static const char *spa_type_name(u16 type)
 
 int nfit_spa_type(struct acpi_nfit_system_address *spa)
 {
+	guid_t guid;
 	int i;
 
+	import_guid(&guid, spa->range_guid);
 	for (i = 0; i < NFIT_UUID_MAX; i++)
-		if (guid_equal(to_nfit_uuid(i), (guid_t *)&spa->range_guid))
+		if (guid_equal(to_nfit_uuid(i), &guid))
 			return i;
 	return -1;
 }
 
+static size_t sizeof_spa(struct acpi_nfit_system_address *spa)
+{
+	if (spa->flags & ACPI_NFIT_LOCATION_COOKIE_VALID)
+		return sizeof(*spa);
+	return sizeof(*spa) - 8;
+}
+
 static bool add_spa(struct acpi_nfit_desc *acpi_desc,
 		struct nfit_table_prev *prev,
 		struct acpi_nfit_system_address *spa)
@@ -682,22 +707,22 @@ static bool add_spa(struct acpi_nfit_desc *acpi_desc,
 	struct device *dev = acpi_desc->dev;
 	struct nfit_spa *nfit_spa;
 
-	if (spa->header.length != sizeof(*spa))
+	if (spa->header.length != sizeof_spa(spa))
 		return false;
 
 	list_for_each_entry(nfit_spa, &prev->spas, list) {
-		if (memcmp(nfit_spa->spa, spa, sizeof(*spa)) == 0) {
+		if (memcmp(nfit_spa->spa, spa, sizeof_spa(spa)) == 0) {
 			list_move_tail(&nfit_spa->list, &acpi_desc->spas);
 			return true;
 		}
 	}
 
-	nfit_spa = devm_kzalloc(dev, sizeof(*nfit_spa) + sizeof(*spa),
+	nfit_spa = devm_kzalloc(dev, sizeof(*nfit_spa) + sizeof_spa(spa),
 			GFP_KERNEL);
 	if (!nfit_spa)
 		return false;
 	INIT_LIST_HEAD(&nfit_spa->list);
-	memcpy(nfit_spa->spa, spa, sizeof(*spa));
+	memcpy(nfit_spa->spa, spa, sizeof_spa(spa));
 	list_add_tail(&nfit_spa->list, &acpi_desc->spas);
 	dev_dbg(dev, "spa index: %d type: %s\n",
 			spa->range_index,
@@ -835,7 +860,7 @@ static size_t sizeof_idt(struct acpi_nfit_interleave *idt)
 {
 	if (idt->header.length < sizeof(*idt))
 		return 0;
-	return sizeof(*idt) + sizeof(u32) * (idt->line_count - 1);
+	return sizeof(*idt) + sizeof(u32) * idt->line_count;
 }
 
 static bool add_idt(struct acpi_nfit_desc *acpi_desc,
@@ -874,7 +899,7 @@ static size_t sizeof_flush(struct acpi_nfit_flush_address *flush)
 {
 	if (flush->header.length < sizeof(*flush))
 		return 0;
-	return sizeof(*flush) + sizeof(u64) * (flush->hint_count - 1);
+	return struct_size(flush, hint_address, flush->hint_count);
 }
 
 static bool add_flush(struct acpi_nfit_desc *acpi_desc,
@@ -979,80 +1004,6 @@ static void *add_table(struct acpi_nfit_desc *acpi_desc,
 	return table + hdr->length;
 }
 
-static void nfit_mem_find_spa_bdw(struct acpi_nfit_desc *acpi_desc,
-		struct nfit_mem *nfit_mem)
-{
-	u32 device_handle = __to_nfit_memdev(nfit_mem)->device_handle;
-	u16 dcr = nfit_mem->dcr->region_index;
-	struct nfit_spa *nfit_spa;
-
-	list_for_each_entry(nfit_spa, &acpi_desc->spas, list) {
-		u16 range_index = nfit_spa->spa->range_index;
-		int type = nfit_spa_type(nfit_spa->spa);
-		struct nfit_memdev *nfit_memdev;
-
-		if (type != NFIT_SPA_BDW)
-			continue;
-
-		list_for_each_entry(nfit_memdev, &acpi_desc->memdevs, list) {
-			if (nfit_memdev->memdev->range_index != range_index)
-				continue;
-			if (nfit_memdev->memdev->device_handle != device_handle)
-				continue;
-			if (nfit_memdev->memdev->region_index != dcr)
-				continue;
-
-			nfit_mem->spa_bdw = nfit_spa->spa;
-			return;
-		}
-	}
-
-	dev_dbg(acpi_desc->dev, "SPA-BDW not found for SPA-DCR %d\n",
-			nfit_mem->spa_dcr->range_index);
-	nfit_mem->bdw = NULL;
-}
-
-static void nfit_mem_init_bdw(struct acpi_nfit_desc *acpi_desc,
-		struct nfit_mem *nfit_mem, struct acpi_nfit_system_address *spa)
-{
-	u16 dcr = __to_nfit_memdev(nfit_mem)->region_index;
-	struct nfit_memdev *nfit_memdev;
-	struct nfit_bdw *nfit_bdw;
-	struct nfit_idt *nfit_idt;
-	u16 idt_idx, range_index;
-
-	list_for_each_entry(nfit_bdw, &acpi_desc->bdws, list) {
-		if (nfit_bdw->bdw->region_index != dcr)
-			continue;
-		nfit_mem->bdw = nfit_bdw->bdw;
-		break;
-	}
-
-	if (!nfit_mem->bdw)
-		return;
-
-	nfit_mem_find_spa_bdw(acpi_desc, nfit_mem);
-
-	if (!nfit_mem->spa_bdw)
-		return;
-
-	range_index = nfit_mem->spa_bdw->range_index;
-	list_for_each_entry(nfit_memdev, &acpi_desc->memdevs, list) {
-		if (nfit_memdev->memdev->range_index != range_index ||
-				nfit_memdev->memdev->region_index != dcr)
-			continue;
-		nfit_mem->memdev_bdw = nfit_memdev->memdev;
-		idt_idx = nfit_memdev->memdev->interleave_index;
-		list_for_each_entry(nfit_idt, &acpi_desc->idts, list) {
-			if (nfit_idt->idt->interleave_index != idt_idx)
-				continue;
-			nfit_mem->idt_bdw = nfit_idt->idt;
-			break;
-		}
-		break;
-	}
-}
-
 static int __nfit_mem_init(struct acpi_nfit_desc *acpi_desc,
 		struct acpi_nfit_system_address *spa)
 {
@@ -1169,7 +1120,6 @@ static int __nfit_mem_init(struct acpi_nfit_desc *acpi_desc,
 				nfit_mem->idt_dcr = nfit_idt->idt;
 				break;
 			}
-			nfit_mem_init_bdw(acpi_desc, nfit_mem, spa);
 		} else if (type == NFIT_SPA_PM) {
 			/*
 			 * A single dimm may belong to multiple SPA-PM
@@ -1184,7 +1134,8 @@ static int __nfit_mem_init(struct acpi_nfit_desc *acpi_desc,
 	return 0;
 }
 
-static int nfit_mem_cmp(void *priv, struct list_head *_a, struct list_head *_b)
+static int nfit_mem_cmp(void *priv, const struct list_head *_a,
+		const struct list_head *_b)
 {
 	struct nfit_mem *a = container_of(_a, typeof(*a), list);
 	struct nfit_mem *b = container_of(_b, typeof(*b), list);
@@ -1238,8 +1189,9 @@ static ssize_t bus_dsm_mask_show(struct device *dev,
 {
 	struct nvdimm_bus *nvdimm_bus = to_nvdimm_bus(dev);
 	struct nvdimm_bus_descriptor *nd_desc = to_nd_desc(nvdimm_bus);
+	struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc);
 
-	return sprintf(buf, "%#lx\n", nd_desc->bus_dsm_mask);
+	return sysfs_emit(buf, "%#lx\n", acpi_desc->bus_dsm_mask);
 }
 static struct device_attribute dev_attr_bus_dsm_mask =
 		__ATTR(dsm_mask, 0444, bus_dsm_mask_show, NULL);
@@ -1251,7 +1203,7 @@ static ssize_t revision_show(struct device *dev,
 	struct nvdimm_bus_descriptor *nd_desc = to_nd_desc(nvdimm_bus);
 	struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc);
 
-	return sprintf(buf, "%d\n", acpi_desc->acpi_header.revision);
+	return sysfs_emit(buf, "%d\n", acpi_desc->acpi_header.revision);
 }
 static DEVICE_ATTR_RO(revision);
 
@@ -1262,7 +1214,7 @@ static ssize_t hw_error_scrub_show(struct device *dev,
 	struct nvdimm_bus_descriptor *nd_desc = to_nd_desc(nvdimm_bus);
 	struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc);
 
-	return sprintf(buf, "%d\n", acpi_desc->scrub_mode);
+	return sysfs_emit(buf, "%d\n", acpi_desc->scrub_mode);
 }
 
 /*
@@ -1283,7 +1235,7 @@ static ssize_t hw_error_scrub_store(struct device *dev,
 	if (rc)
 		return rc;
 
-	nfit_device_lock(dev);
+	device_lock(dev);
 	nd_desc = dev_get_drvdata(dev);
 	if (nd_desc) {
 		struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc);
@@ -1300,7 +1252,7 @@ static ssize_t hw_error_scrub_store(struct device *dev,
 			break;
 		}
 	}
-	nfit_device_unlock(dev);
+	device_unlock(dev);
 	if (rc)
 		return rc;
 	return size;
@@ -1320,10 +1272,10 @@ static ssize_t scrub_show(struct device *dev,
 	ssize_t rc = -ENXIO;
 	bool busy;
 
-	nfit_device_lock(dev);
+	device_lock(dev);
 	nd_desc = dev_get_drvdata(dev);
 	if (!nd_desc) {
-		nfit_device_unlock(dev);
+		device_unlock(dev);
 		return rc;
 	}
 	acpi_desc = to_acpi_desc(nd_desc);
@@ -1331,7 +1283,7 @@ static ssize_t scrub_show(struct device *dev,
 	mutex_lock(&acpi_desc->init_mutex);
 	busy = test_bit(ARS_BUSY, &acpi_desc->scrub_flags)
 		&& !test_bit(ARS_CANCEL, &acpi_desc->scrub_flags);
-	rc = sprintf(buf, "%d%s", acpi_desc->scrub_count, busy ? "+\n" : "\n");
+	rc = sysfs_emit(buf, "%d%s", acpi_desc->scrub_count, busy ? "+\n" : "\n");
 	/* Allow an admin to poll the busy state at a higher rate */
 	if (busy && capable(CAP_SYS_RAWIO) && !test_and_set_bit(ARS_POLL,
 				&acpi_desc->scrub_flags)) {
@@ -1340,7 +1292,7 @@ static ssize_t scrub_show(struct device *dev,
 	}
 
 	mutex_unlock(&acpi_desc->init_mutex);
-	nfit_device_unlock(dev);
+	device_unlock(dev);
 	return rc;
 }
 
@@ -1357,14 +1309,14 @@ static ssize_t scrub_store(struct device *dev,
 	if (val != 1)
 		return -EINVAL;
 
-	nfit_device_lock(dev);
+	device_lock(dev);
 	nd_desc = dev_get_drvdata(dev);
 	if (nd_desc) {
 		struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc);
 
 		rc = acpi_nfit_ars_rescan(acpi_desc, ARS_REQ_LONG);
 	}
-	nfit_device_unlock(dev);
+	device_unlock(dev);
 	if (rc)
 		return rc;
 	return size;
@@ -1382,11 +1334,15 @@ static bool ars_supported(struct nvdimm_bus *nvdimm_bus)
 
 static umode_t nfit_visible(struct kobject *kobj, struct attribute *a, int n)
 {
-	struct device *dev = container_of(kobj, struct device, kobj);
+	struct device *dev = kobj_to_dev(kobj);
 	struct nvdimm_bus *nvdimm_bus = to_nvdimm_bus(dev);
 
-	if (a == &dev_attr_scrub.attr && !ars_supported(nvdimm_bus))
-		return 0;
+	if (a == &dev_attr_scrub.attr)
+		return ars_supported(nvdimm_bus) ? a->mode : 0;
+
+	if (a == &dev_attr_firmware_activate_noidle.attr)
+		return intel_fwa_supported(nvdimm_bus) ? a->mode : 0;
+
 	return a->mode;
 }
 
@@ -1395,6 +1351,7 @@ static struct attribute *acpi_nfit_attributes[] = {
 	&dev_attr_scrub.attr,
 	&dev_attr_hw_error_scrub.attr,
 	&dev_attr_bus_dsm_mask.attr,
+	&dev_attr_firmware_activate_noidle.attr,
 	NULL,
 };
 
@@ -1430,7 +1387,7 @@ static ssize_t handle_show(struct device *dev,
 {
 	struct acpi_nfit_memory_map *memdev = to_nfit_memdev(dev);
 
-	return sprintf(buf, "%#x\n", memdev->device_handle);
+	return sysfs_emit(buf, "%#x\n", memdev->device_handle);
 }
 static DEVICE_ATTR_RO(handle);
 
@@ -1439,7 +1396,7 @@ static ssize_t phys_id_show(struct device *dev,
 {
 	struct acpi_nfit_memory_map *memdev = to_nfit_memdev(dev);
 
-	return sprintf(buf, "%#x\n", memdev->physical_id);
+	return sysfs_emit(buf, "%#x\n", memdev->physical_id);
 }
 static DEVICE_ATTR_RO(phys_id);
 
@@ -1448,7 +1405,7 @@ static ssize_t vendor_show(struct device *dev,
 {
 	struct acpi_nfit_control_region *dcr = to_nfit_dcr(dev);
 
-	return sprintf(buf, "0x%04x\n", be16_to_cpu(dcr->vendor_id));
+	return sysfs_emit(buf, "0x%04x\n", be16_to_cpu(dcr->vendor_id));
 }
 static DEVICE_ATTR_RO(vendor);
 
@@ -1457,7 +1414,7 @@ static ssize_t rev_id_show(struct device *dev,
 {
 	struct acpi_nfit_control_region *dcr = to_nfit_dcr(dev);
 
-	return sprintf(buf, "0x%04x\n", be16_to_cpu(dcr->revision_id));
+	return sysfs_emit(buf, "0x%04x\n", be16_to_cpu(dcr->revision_id));
 }
 static DEVICE_ATTR_RO(rev_id);
 
@@ -1466,7 +1423,7 @@ static ssize_t device_show(struct device *dev,
 {
 	struct acpi_nfit_control_region *dcr = to_nfit_dcr(dev);
 
-	return sprintf(buf, "0x%04x\n", be16_to_cpu(dcr->device_id));
+	return sysfs_emit(buf, "0x%04x\n", be16_to_cpu(dcr->device_id));
 }
 static DEVICE_ATTR_RO(device);
 
@@ -1475,7 +1432,7 @@ static ssize_t subsystem_vendor_show(struct device *dev,
 {
 	struct acpi_nfit_control_region *dcr = to_nfit_dcr(dev);
 
-	return sprintf(buf, "0x%04x\n", be16_to_cpu(dcr->subsystem_vendor_id));
+	return sysfs_emit(buf, "0x%04x\n", be16_to_cpu(dcr->subsystem_vendor_id));
 }
 static DEVICE_ATTR_RO(subsystem_vendor);
 
@@ -1484,7 +1441,7 @@ static ssize_t subsystem_rev_id_show(struct device *dev,
 {
 	struct acpi_nfit_control_region *dcr = to_nfit_dcr(dev);
 
-	return sprintf(buf, "0x%04x\n",
+	return sysfs_emit(buf, "0x%04x\n",
 			be16_to_cpu(dcr->subsystem_revision_id));
 }
 static DEVICE_ATTR_RO(subsystem_rev_id);
@@ -1494,7 +1451,7 @@ static ssize_t subsystem_device_show(struct device *dev,
 {
 	struct acpi_nfit_control_region *dcr = to_nfit_dcr(dev);
 
-	return sprintf(buf, "0x%04x\n", be16_to_cpu(dcr->subsystem_device_id));
+	return sysfs_emit(buf, "0x%04x\n", be16_to_cpu(dcr->subsystem_device_id));
 }
 static DEVICE_ATTR_RO(subsystem_device);
 
@@ -1505,8 +1462,6 @@ static int num_nvdimm_formats(struct nvdimm *nvdimm)
 
 	if (nfit_mem->memdev_pmem)
 		formats++;
-	if (nfit_mem->memdev_bdw)
-		formats++;
 	return formats;
 }
 
@@ -1515,7 +1470,7 @@ static ssize_t format_show(struct device *dev,
 {
 	struct acpi_nfit_control_region *dcr = to_nfit_dcr(dev);
 
-	return sprintf(buf, "0x%04x\n", le16_to_cpu(dcr->code));
+	return sysfs_emit(buf, "0x%04x\n", le16_to_cpu(dcr->code));
 }
 static DEVICE_ATTR_RO(format);
 
@@ -1548,11 +1503,11 @@ static ssize_t format1_show(struct device *dev,
 				continue;
 			if (nfit_dcr->dcr->code == dcr->code)
 				continue;
-			rc = sprintf(buf, "0x%04x\n",
+			rc = sysfs_emit(buf, "0x%04x\n",
 					le16_to_cpu(nfit_dcr->dcr->code));
 			break;
 		}
-		if (rc != ENXIO)
+		if (rc != -ENXIO)
 			break;
 	}
 	mutex_unlock(&acpi_desc->init_mutex);
@@ -1565,7 +1520,7 @@ static ssize_t formats_show(struct device *dev,
 {
 	struct nvdimm *nvdimm = to_nvdimm(dev);
 
-	return sprintf(buf, "%d\n", num_nvdimm_formats(nvdimm));
+	return sysfs_emit(buf, "%d\n", num_nvdimm_formats(nvdimm));
 }
 static DEVICE_ATTR_RO(formats);
 
@@ -1574,7 +1529,7 @@ static ssize_t serial_show(struct device *dev,
 {
 	struct acpi_nfit_control_region *dcr = to_nfit_dcr(dev);
 
-	return sprintf(buf, "0x%08x\n", be32_to_cpu(dcr->serial_number));
+	return sysfs_emit(buf, "0x%08x\n", be32_to_cpu(dcr->serial_number));
 }
 static DEVICE_ATTR_RO(serial);
 
@@ -1586,7 +1541,7 @@ static ssize_t family_show(struct device *dev,
 
 	if (nfit_mem->family < 0)
 		return -ENXIO;
-	return sprintf(buf, "%d\n", nfit_mem->family);
+	return sysfs_emit(buf, "%d\n", nfit_mem->family);
 }
 static DEVICE_ATTR_RO(family);
 
@@ -1598,7 +1553,7 @@ static ssize_t dsm_mask_show(struct device *dev,
 
 	if (nfit_mem->family < 0)
 		return -ENXIO;
-	return sprintf(buf, "%#lx\n", nfit_mem->dsm_mask);
+	return sysfs_emit(buf, "%#lx\n", nfit_mem->dsm_mask);
 }
 static DEVICE_ATTR_RO(dsm_mask);
 
@@ -1612,7 +1567,7 @@ static ssize_t flags_show(struct device *dev,
 	if (test_bit(NFIT_MEM_DIRTY, &nfit_mem->flags))
 		flags |= ACPI_NFIT_MEM_FLUSH_FAILED;
 
-	return sprintf(buf, "%s%s%s%s%s%s%s\n",
+	return sysfs_emit(buf, "%s%s%s%s%s%s%s\n",
 		flags & ACPI_NFIT_MEM_SAVE_FAILED ? "save_fail " : "",
 		flags & ACPI_NFIT_MEM_RESTORE_FAILED ? "restore_fail " : "",
 		flags & ACPI_NFIT_MEM_FLUSH_FAILED ? "flush_fail " : "",
@@ -1629,7 +1584,7 @@ static ssize_t id_show(struct device *dev,
 	struct nvdimm *nvdimm = to_nvdimm(dev);
 	struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm);
 
-	return sprintf(buf, "%s\n", nfit_mem->id);
+	return sysfs_emit(buf, "%s\n", nfit_mem->id);
 }
 static DEVICE_ATTR_RO(id);
 
@@ -1639,7 +1594,7 @@ static ssize_t dirty_shutdown_show(struct device *dev,
 	struct nvdimm *nvdimm = to_nvdimm(dev);
 	struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm);
 
-	return sprintf(buf, "%d\n", nfit_mem->dirty_shutdown);
+	return sysfs_emit(buf, "%d\n", nfit_mem->dirty_shutdown);
 }
 static DEVICE_ATTR_RO(dirty_shutdown);
 
@@ -1667,7 +1622,7 @@ static struct attribute *acpi_nfit_dimm_attributes[] = {
 static umode_t acpi_nfit_dimm_attr_visible(struct kobject *kobj,
 		struct attribute *a, int n)
 {
-	struct device *dev = container_of(kobj, struct device, kobj);
+	struct device *dev = kobj_to_dev(kobj);
 	struct nvdimm *nvdimm = to_nvdimm(dev);
 	struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm);
 
@@ -1747,9 +1702,9 @@ static void acpi_nvdimm_notify(acpi_handle handle, u32 event, void *data)
 	struct acpi_device *adev = data;
 	struct device *dev = &adev->dev;
 
-	nfit_device_lock(dev->parent);
+	device_lock(dev->parent);
 	__acpi_nvdimm_notify(dev, event);
-	nfit_device_unlock(dev->parent);
+	device_unlock(dev->parent);
 }
 
 static bool acpi_nvdimm_has_method(struct acpi_device *adev, char *method)
@@ -1787,9 +1742,8 @@ __weak void nfit_intel_shutdown_status(struct nfit_mem *nfit_mem)
 	if ((nfit_mem->dsm_mask & (1 << func)) == 0)
 		return;
 
-	out_obj = acpi_evaluate_dsm(handle, guid, revid, func, &in_obj);
-	if (!out_obj || out_obj->type != ACPI_TYPE_BUFFER
-			|| out_obj->buffer.length < sizeof(smart)) {
+	out_obj = acpi_evaluate_dsm_typed(handle, guid, revid, func, &in_obj, ACPI_TYPE_BUFFER);
+	if (!out_obj || out_obj->buffer.length < sizeof(smart)) {
 		dev_dbg(dev->parent, "%s: failed to retrieve initial health\n",
 				dev_name(dev));
 		ACPI_FREE(out_obj);
@@ -1823,6 +1777,7 @@ static void populate_shutdown_status(struct nfit_mem *nfit_mem)
 static int acpi_nfit_add_dimm(struct acpi_nfit_desc *acpi_desc,
 		struct nfit_mem *nfit_mem, u32 device_handle)
 {
+	struct nvdimm_bus_descriptor *nd_desc = &acpi_desc->nd_desc;
 	struct acpi_device *adev, *adev_dimm;
 	struct device *dev = acpi_desc->dev;
 	unsigned long dsm_mask, label_mask;
@@ -1834,6 +1789,7 @@ static int acpi_nfit_add_dimm(struct acpi_nfit_desc *acpi_desc,
 	/* nfit test assumes 1:1 relationship between commands and dsms */
 	nfit_mem->dsm_mask = acpi_desc->dimm_cmd_force_en;
 	nfit_mem->family = NVDIMM_FAMILY_INTEL;
+	set_bit(NVDIMM_FAMILY_INTEL, &nd_desc->dimm_family_mask);
 
 	if (dcr->valid_fields & ACPI_NFIT_CONTROL_MFG_INFO_VALID)
 		sprintf(nfit_mem->id, "%04x-%02x-%04x-%08x",
@@ -1886,10 +1842,13 @@ static int acpi_nfit_add_dimm(struct acpi_nfit_desc *acpi_desc,
 	 * Note, that checking for function0 (bit0) tells us if any commands
 	 * are reachable through this GUID.
 	 */
+	clear_bit(NVDIMM_FAMILY_INTEL, &nd_desc->dimm_family_mask);
 	for (i = 0; i <= NVDIMM_FAMILY_MAX; i++)
-		if (acpi_check_dsm(adev_dimm->handle, to_nfit_uuid(i), 1, 1))
+		if (acpi_check_dsm(adev_dimm->handle, to_nfit_uuid(i), 1, 1)) {
+			set_bit(i, &nd_desc->dimm_family_mask);
 			if (family < 0 || i == default_dsm_family)
 				family = i;
+		}
 
 	/* limit the supported commands to those that are publicly documented */
 	nfit_mem->family = family;
@@ -2007,6 +1966,26 @@ static const struct nvdimm_security_ops *acpi_nfit_get_security_ops(int family)
 	}
 }
 
+static const struct nvdimm_fw_ops *acpi_nfit_get_fw_ops(
+		struct nfit_mem *nfit_mem)
+{
+	unsigned long mask;
+	struct acpi_nfit_desc *acpi_desc = nfit_mem->acpi_desc;
+	struct nvdimm_bus_descriptor *nd_desc = &acpi_desc->nd_desc;
+
+	if (!nd_desc->fw_ops)
+		return NULL;
+
+	if (nfit_mem->family != NVDIMM_FAMILY_INTEL)
+		return NULL;
+
+	mask = nfit_mem->dsm_mask & NVDIMM_INTEL_FW_ACTIVATE_CMDMASK;
+	if (mask != NVDIMM_INTEL_FW_ACTIVATE_CMDMASK)
+		return NULL;
+
+	return intel_fw_ops;
+}
+
 static int acpi_nfit_register_dimms(struct acpi_nfit_desc *acpi_desc)
 {
 	struct nfit_mem *nfit_mem;
@@ -2027,11 +2006,6 @@ static int acpi_nfit_register_dimms(struct acpi_nfit_desc *acpi_desc)
 			continue;
 		}
 
-		if (nfit_mem->bdw && nfit_mem->memdev_pmem) {
-			set_bit(NDD_ALIASING, &flags);
-			set_bit(NDD_LABELING, &flags);
-		}
-
 		/* collate flags across all memdevs for this dimm */
 		list_for_each_entry(nfit_memdev, &acpi_desc->memdevs, list) {
 			struct acpi_nfit_memory_map *dimm_memdev;
@@ -2066,10 +2040,6 @@ static int acpi_nfit_register_dimms(struct acpi_nfit_desc *acpi_desc)
 			cmd_mask |= nfit_mem->dsm_mask & NVDIMM_STANDARD_CMDMASK;
 		}
 
-		/* Quirk to ignore LOCAL for labels on HYPERV DIMMs */
-		if (nfit_mem->family == NVDIMM_FAMILY_HYPERV)
-			set_bit(NDD_NOBLK, &flags);
-
 		if (test_bit(NFIT_MEM_LSR, &nfit_mem->flags)) {
 			set_bit(ND_CMD_GET_CONFIG_SIZE, &cmd_mask);
 			set_bit(ND_CMD_GET_CONFIG_DATA, &cmd_mask);
@@ -2083,7 +2053,8 @@ static int acpi_nfit_register_dimms(struct acpi_nfit_desc *acpi_desc)
 				acpi_nfit_dimm_attribute_groups,
 				flags, cmd_mask, flush ? flush->hint_count : 0,
 				nfit_mem->flush_wpq, &nfit_mem->id[0],
-				acpi_nfit_get_security_ops(nfit_mem->family));
+				acpi_nfit_get_security_ops(nfit_mem->family),
+				acpi_nfit_get_fw_ops(nfit_mem));
 		if (!nvdimm)
 			return -ENOMEM;
 
@@ -2137,22 +2108,33 @@ static int acpi_nfit_register_dimms(struct acpi_nfit_desc *acpi_desc)
  * these commands.
  */
 enum nfit_aux_cmds {
-        NFIT_CMD_TRANSLATE_SPA = 5,
-        NFIT_CMD_ARS_INJECT_SET = 7,
-        NFIT_CMD_ARS_INJECT_CLEAR = 8,
-        NFIT_CMD_ARS_INJECT_GET = 9,
+	NFIT_CMD_TRANSLATE_SPA = 5,
+	NFIT_CMD_ARS_INJECT_SET = 7,
+	NFIT_CMD_ARS_INJECT_CLEAR = 8,
+	NFIT_CMD_ARS_INJECT_GET = 9,
 };
 
 static void acpi_nfit_init_dsms(struct acpi_nfit_desc *acpi_desc)
 {
 	struct nvdimm_bus_descriptor *nd_desc = &acpi_desc->nd_desc;
 	const guid_t *guid = to_nfit_uuid(NFIT_DEV_BUS);
+	unsigned long dsm_mask, *mask;
 	struct acpi_device *adev;
-	unsigned long dsm_mask;
 	int i;
 
-	nd_desc->cmd_mask = acpi_desc->bus_cmd_force_en;
-	nd_desc->bus_dsm_mask = acpi_desc->bus_nfit_cmd_force_en;
+	set_bit(ND_CMD_CALL, &nd_desc->cmd_mask);
+	set_bit(NVDIMM_BUS_FAMILY_NFIT, &nd_desc->bus_family_mask);
+
+	/* enable nfit_test to inject bus command emulation */
+	if (acpi_desc->bus_cmd_force_en) {
+		nd_desc->cmd_mask = acpi_desc->bus_cmd_force_en;
+		mask = &nd_desc->bus_family_mask;
+		if (acpi_desc->family_dsm_mask[NVDIMM_BUS_FAMILY_INTEL]) {
+			set_bit(NVDIMM_BUS_FAMILY_INTEL, mask);
+			nd_desc->fw_ops = intel_bus_fw_ops;
+		}
+	}
+
 	adev = to_acpi_dev(acpi_desc);
 	if (!adev)
 		return;
@@ -2160,7 +2142,6 @@ static void acpi_nfit_init_dsms(struct acpi_nfit_desc *acpi_desc)
 	for (i = ND_CMD_ARS_CAP; i <= ND_CMD_CLEAR_ERROR; i++)
 		if (acpi_check_dsm(adev->handle, guid, 1, 1ULL << i))
 			set_bit(i, &nd_desc->cmd_mask);
-	set_bit(ND_CMD_CALL, &nd_desc->cmd_mask);
 
 	dsm_mask =
 		(1 << ND_CMD_ARS_CAP) |
@@ -2173,7 +2154,20 @@ static void acpi_nfit_init_dsms(struct acpi_nfit_desc *acpi_desc)
 		(1 << NFIT_CMD_ARS_INJECT_GET);
 	for_each_set_bit(i, &dsm_mask, BITS_PER_LONG)
 		if (acpi_check_dsm(adev->handle, guid, 1, 1ULL << i))
-			set_bit(i, &nd_desc->bus_dsm_mask);
+			set_bit(i, &acpi_desc->bus_dsm_mask);
+
+	/* Enumerate allowed NVDIMM_BUS_FAMILY_INTEL commands */
+	dsm_mask = NVDIMM_BUS_INTEL_FW_ACTIVATE_CMDMASK;
+	guid = to_nfit_bus_uuid(NVDIMM_BUS_FAMILY_INTEL);
+	mask = &acpi_desc->family_dsm_mask[NVDIMM_BUS_FAMILY_INTEL];
+	for_each_set_bit(i, &dsm_mask, BITS_PER_LONG)
+		if (acpi_check_dsm(adev->handle, guid, 1, 1ULL << i))
+			set_bit(i, mask);
+
+	if (*mask == dsm_mask) {
+		set_bit(NVDIMM_BUS_FAMILY_INTEL, &nd_desc->bus_family_mask);
+		nd_desc->fw_ops = intel_bus_fw_ops;
+	}
 }
 
 static ssize_t range_index_show(struct device *dev,
@@ -2182,7 +2176,7 @@ static ssize_t range_index_show(struct device *dev,
 	struct nd_region *nd_region = to_nd_region(dev);
 	struct nfit_spa *nfit_spa = nd_region_provider_data(nd_region);
 
-	return sprintf(buf, "%d\n", nfit_spa->spa->range_index);
+	return sysfs_emit(buf, "%d\n", nfit_spa->spa->range_index);
 }
 static DEVICE_ATTR_RO(range_index);
 
@@ -2203,40 +2197,24 @@ static const struct attribute_group *acpi_nfit_region_attribute_groups[] = {
 
 /* enough info to uniquely specify an interleave set */
 struct nfit_set_info {
-	struct nfit_set_info_map {
-		u64 region_offset;
-		u32 serial_number;
-		u32 pad;
-	} mapping[0];
+	u64 region_offset;
+	u32 serial_number;
+	u32 pad;
 };
 
 struct nfit_set_info2 {
-	struct nfit_set_info_map2 {
-		u64 region_offset;
-		u32 serial_number;
-		u16 vendor_id;
-		u16 manufacturing_date;
-		u8  manufacturing_location;
-		u8  reserved[31];
-	} mapping[0];
+	u64 region_offset;
+	u32 serial_number;
+	u16 vendor_id;
+	u16 manufacturing_date;
+	u8 manufacturing_location;
+	u8 reserved[31];
 };
 
-static size_t sizeof_nfit_set_info(int num_mappings)
-{
-	return sizeof(struct nfit_set_info)
-		+ num_mappings * sizeof(struct nfit_set_info_map);
-}
-
-static size_t sizeof_nfit_set_info2(int num_mappings)
-{
-	return sizeof(struct nfit_set_info2)
-		+ num_mappings * sizeof(struct nfit_set_info_map2);
-}
-
 static int cmp_map_compat(const void *m0, const void *m1)
 {
-	const struct nfit_set_info_map *map0 = m0;
-	const struct nfit_set_info_map *map1 = m1;
+	const struct nfit_set_info *map0 = m0;
+	const struct nfit_set_info *map1 = m1;
 
 	return memcmp(&map0->region_offset, &map1->region_offset,
 			sizeof(u64));
@@ -2244,8 +2222,8 @@ static int cmp_map_compat(const void *m0, const void *m1)
 
 static int cmp_map(const void *m0, const void *m1)
 {
-	const struct nfit_set_info_map *map0 = m0;
-	const struct nfit_set_info_map *map1 = m1;
+	const struct nfit_set_info *map0 = m0;
+	const struct nfit_set_info *map1 = m1;
 
 	if (map0->region_offset < map1->region_offset)
 		return -1;
@@ -2256,8 +2234,8 @@ static int cmp_map(const void *m0, const void *m1)
 
 static int cmp_map2(const void *m0, const void *m1)
 {
-	const struct nfit_set_info_map2 *map0 = m0;
-	const struct nfit_set_info_map2 *map1 = m1;
+	const struct nfit_set_info2 *map0 = m0;
+	const struct nfit_set_info2 *map1 = m1;
 
 	if (map0->region_offset < map1->region_offset)
 		return -1;
@@ -2283,34 +2261,31 @@ static int acpi_nfit_init_interleave_set(struct acpi_nfit_desc *acpi_desc,
 		struct nd_region_desc *ndr_desc,
 		struct acpi_nfit_system_address *spa)
 {
+	u16 nr = ndr_desc->num_mappings;
+	struct nfit_set_info2 *info2 __free(kfree) =
+		kcalloc(nr, sizeof(*info2), GFP_KERNEL);
+	struct nfit_set_info *info __free(kfree) =
+		kcalloc(nr, sizeof(*info), GFP_KERNEL);
 	struct device *dev = acpi_desc->dev;
 	struct nd_interleave_set *nd_set;
-	u16 nr = ndr_desc->num_mappings;
-	struct nfit_set_info2 *info2;
-	struct nfit_set_info *info;
 	int i;
 
-	nd_set = devm_kzalloc(dev, sizeof(*nd_set), GFP_KERNEL);
-	if (!nd_set)
+	if (!info || !info2)
 		return -ENOMEM;
-	guid_copy(&nd_set->type_guid, (guid_t *) spa->range_guid);
 
-	info = devm_kzalloc(dev, sizeof_nfit_set_info(nr), GFP_KERNEL);
-	if (!info)
-		return -ENOMEM;
-
-	info2 = devm_kzalloc(dev, sizeof_nfit_set_info2(nr), GFP_KERNEL);
-	if (!info2)
+	nd_set = devm_kzalloc(dev, sizeof(*nd_set), GFP_KERNEL);
+	if (!nd_set)
 		return -ENOMEM;
+	import_guid(&nd_set->type_guid, spa->range_guid);
 
 	for (i = 0; i < nr; i++) {
 		struct nd_mapping_desc *mapping = &ndr_desc->mapping[i];
-		struct nfit_set_info_map *map = &info->mapping[i];
-		struct nfit_set_info_map2 *map2 = &info2->mapping[i];
 		struct nvdimm *nvdimm = mapping->nvdimm;
 		struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm);
-		struct acpi_nfit_memory_map *memdev = memdev_from_spa(acpi_desc,
-				spa->range_index, i);
+		struct nfit_set_info *map = &info[i];
+		struct nfit_set_info2 *map2 = &info2[i];
+		struct acpi_nfit_memory_map *memdev =
+			memdev_from_spa(acpi_desc, spa->range_index, i);
 		struct acpi_nfit_control_region *dcr = nfit_mem->dcr;
 
 		if (!memdev || !nfit_mem->dcr) {
@@ -2329,23 +2304,20 @@ static int acpi_nfit_init_interleave_set(struct acpi_nfit_desc *acpi_desc,
 	}
 
 	/* v1.1 namespaces */
-	sort(&info->mapping[0], nr, sizeof(struct nfit_set_info_map),
-			cmp_map, NULL);
-	nd_set->cookie1 = nd_fletcher64(info, sizeof_nfit_set_info(nr), 0);
+	sort(info, nr, sizeof(*info), cmp_map, NULL);
+	nd_set->cookie1 = nd_fletcher64(info, sizeof(*info) * nr, 0);
 
 	/* v1.2 namespaces */
-	sort(&info2->mapping[0], nr, sizeof(struct nfit_set_info_map2),
-			cmp_map2, NULL);
-	nd_set->cookie2 = nd_fletcher64(info2, sizeof_nfit_set_info2(nr), 0);
+	sort(info2, nr, sizeof(*info2), cmp_map2, NULL);
+	nd_set->cookie2 = nd_fletcher64(info2, sizeof(*info2) * nr, 0);
 
 	/* support v1.1 namespaces created with the wrong sort order */
-	sort(&info->mapping[0], nr, sizeof(struct nfit_set_info_map),
-			cmp_map_compat, NULL);
-	nd_set->altcookie = nd_fletcher64(info, sizeof_nfit_set_info(nr), 0);
+	sort(info, nr, sizeof(*info), cmp_map_compat, NULL);
+	nd_set->altcookie = nd_fletcher64(info, sizeof(*info) * nr, 0);
 
 	/* record the result of the sort for the mapping position */
 	for (i = 0; i < nr; i++) {
-		struct nfit_set_info_map2 *map2 = &info2->mapping[i];
+		struct nfit_set_info2 *map2 = &info2[i];
 		int j;
 
 		for (j = 0; j < nr; j++) {
@@ -2366,274 +2338,6 @@ static int acpi_nfit_init_interleave_set(struct acpi_nfit_desc *acpi_desc,
 	}
 
 	ndr_desc->nd_set = nd_set;
-	devm_kfree(dev, info);
-	devm_kfree(dev, info2);
-
-	return 0;
-}
-
-static u64 to_interleave_offset(u64 offset, struct nfit_blk_mmio *mmio)
-{
-	struct acpi_nfit_interleave *idt = mmio->idt;
-	u32 sub_line_offset, line_index, line_offset;
-	u64 line_no, table_skip_count, table_offset;
-
-	line_no = div_u64_rem(offset, mmio->line_size, &sub_line_offset);
-	table_skip_count = div_u64_rem(line_no, mmio->num_lines, &line_index);
-	line_offset = idt->line_offset[line_index]
-		* mmio->line_size;
-	table_offset = table_skip_count * mmio->table_size;
-
-	return mmio->base_offset + line_offset + table_offset + sub_line_offset;
-}
-
-static u32 read_blk_stat(struct nfit_blk *nfit_blk, unsigned int bw)
-{
-	struct nfit_blk_mmio *mmio = &nfit_blk->mmio[DCR];
-	u64 offset = nfit_blk->stat_offset + mmio->size * bw;
-	const u32 STATUS_MASK = 0x80000037;
-
-	if (mmio->num_lines)
-		offset = to_interleave_offset(offset, mmio);
-
-	return readl(mmio->addr.base + offset) & STATUS_MASK;
-}
-
-static void write_blk_ctl(struct nfit_blk *nfit_blk, unsigned int bw,
-		resource_size_t dpa, unsigned int len, unsigned int write)
-{
-	u64 cmd, offset;
-	struct nfit_blk_mmio *mmio = &nfit_blk->mmio[DCR];
-
-	enum {
-		BCW_OFFSET_MASK = (1ULL << 48)-1,
-		BCW_LEN_SHIFT = 48,
-		BCW_LEN_MASK = (1ULL << 8) - 1,
-		BCW_CMD_SHIFT = 56,
-	};
-
-	cmd = (dpa >> L1_CACHE_SHIFT) & BCW_OFFSET_MASK;
-	len = len >> L1_CACHE_SHIFT;
-	cmd |= ((u64) len & BCW_LEN_MASK) << BCW_LEN_SHIFT;
-	cmd |= ((u64) write) << BCW_CMD_SHIFT;
-
-	offset = nfit_blk->cmd_offset + mmio->size * bw;
-	if (mmio->num_lines)
-		offset = to_interleave_offset(offset, mmio);
-
-	writeq(cmd, mmio->addr.base + offset);
-	nvdimm_flush(nfit_blk->nd_region, NULL);
-
-	if (nfit_blk->dimm_flags & NFIT_BLK_DCR_LATCH)
-		readq(mmio->addr.base + offset);
-}
-
-static int acpi_nfit_blk_single_io(struct nfit_blk *nfit_blk,
-		resource_size_t dpa, void *iobuf, size_t len, int rw,
-		unsigned int lane)
-{
-	struct nfit_blk_mmio *mmio = &nfit_blk->mmio[BDW];
-	unsigned int copied = 0;
-	u64 base_offset;
-	int rc;
-
-	base_offset = nfit_blk->bdw_offset + dpa % L1_CACHE_BYTES
-		+ lane * mmio->size;
-	write_blk_ctl(nfit_blk, lane, dpa, len, rw);
-	while (len) {
-		unsigned int c;
-		u64 offset;
-
-		if (mmio->num_lines) {
-			u32 line_offset;
-
-			offset = to_interleave_offset(base_offset + copied,
-					mmio);
-			div_u64_rem(offset, mmio->line_size, &line_offset);
-			c = min_t(size_t, len, mmio->line_size - line_offset);
-		} else {
-			offset = base_offset + nfit_blk->bdw_offset;
-			c = len;
-		}
-
-		if (rw)
-			memcpy_flushcache(mmio->addr.aperture + offset, iobuf + copied, c);
-		else {
-			if (nfit_blk->dimm_flags & NFIT_BLK_READ_FLUSH)
-				arch_invalidate_pmem((void __force *)
-					mmio->addr.aperture + offset, c);
-
-			memcpy(iobuf + copied, mmio->addr.aperture + offset, c);
-		}
-
-		copied += c;
-		len -= c;
-	}
-
-	if (rw)
-		nvdimm_flush(nfit_blk->nd_region, NULL);
-
-	rc = read_blk_stat(nfit_blk, lane) ? -EIO : 0;
-	return rc;
-}
-
-static int acpi_nfit_blk_region_do_io(struct nd_blk_region *ndbr,
-		resource_size_t dpa, void *iobuf, u64 len, int rw)
-{
-	struct nfit_blk *nfit_blk = nd_blk_region_provider_data(ndbr);
-	struct nfit_blk_mmio *mmio = &nfit_blk->mmio[BDW];
-	struct nd_region *nd_region = nfit_blk->nd_region;
-	unsigned int lane, copied = 0;
-	int rc = 0;
-
-	lane = nd_region_acquire_lane(nd_region);
-	while (len) {
-		u64 c = min(len, mmio->size);
-
-		rc = acpi_nfit_blk_single_io(nfit_blk, dpa + copied,
-				iobuf + copied, c, rw, lane);
-		if (rc)
-			break;
-
-		copied += c;
-		len -= c;
-	}
-	nd_region_release_lane(nd_region, lane);
-
-	return rc;
-}
-
-static int nfit_blk_init_interleave(struct nfit_blk_mmio *mmio,
-		struct acpi_nfit_interleave *idt, u16 interleave_ways)
-{
-	if (idt) {
-		mmio->num_lines = idt->line_count;
-		mmio->line_size = idt->line_size;
-		if (interleave_ways == 0)
-			return -ENXIO;
-		mmio->table_size = mmio->num_lines * interleave_ways
-			* mmio->line_size;
-	}
-
-	return 0;
-}
-
-static int acpi_nfit_blk_get_flags(struct nvdimm_bus_descriptor *nd_desc,
-		struct nvdimm *nvdimm, struct nfit_blk *nfit_blk)
-{
-	struct nd_cmd_dimm_flags flags;
-	int rc;
-
-	memset(&flags, 0, sizeof(flags));
-	rc = nd_desc->ndctl(nd_desc, nvdimm, ND_CMD_DIMM_FLAGS, &flags,
-			sizeof(flags), NULL);
-
-	if (rc >= 0 && flags.status == 0)
-		nfit_blk->dimm_flags = flags.flags;
-	else if (rc == -ENOTTY) {
-		/* fall back to a conservative default */
-		nfit_blk->dimm_flags = NFIT_BLK_DCR_LATCH | NFIT_BLK_READ_FLUSH;
-		rc = 0;
-	} else
-		rc = -ENXIO;
-
-	return rc;
-}
-
-static int acpi_nfit_blk_region_enable(struct nvdimm_bus *nvdimm_bus,
-		struct device *dev)
-{
-	struct nvdimm_bus_descriptor *nd_desc = to_nd_desc(nvdimm_bus);
-	struct nd_blk_region *ndbr = to_nd_blk_region(dev);
-	struct nfit_blk_mmio *mmio;
-	struct nfit_blk *nfit_blk;
-	struct nfit_mem *nfit_mem;
-	struct nvdimm *nvdimm;
-	int rc;
-
-	nvdimm = nd_blk_region_to_dimm(ndbr);
-	nfit_mem = nvdimm_provider_data(nvdimm);
-	if (!nfit_mem || !nfit_mem->dcr || !nfit_mem->bdw) {
-		dev_dbg(dev, "missing%s%s%s\n",
-				nfit_mem ? "" : " nfit_mem",
-				(nfit_mem && nfit_mem->dcr) ? "" : " dcr",
-				(nfit_mem && nfit_mem->bdw) ? "" : " bdw");
-		return -ENXIO;
-	}
-
-	nfit_blk = devm_kzalloc(dev, sizeof(*nfit_blk), GFP_KERNEL);
-	if (!nfit_blk)
-		return -ENOMEM;
-	nd_blk_region_set_provider_data(ndbr, nfit_blk);
-	nfit_blk->nd_region = to_nd_region(dev);
-
-	/* map block aperture memory */
-	nfit_blk->bdw_offset = nfit_mem->bdw->offset;
-	mmio = &nfit_blk->mmio[BDW];
-	mmio->addr.base = devm_nvdimm_memremap(dev, nfit_mem->spa_bdw->address,
-                        nfit_mem->spa_bdw->length, nd_blk_memremap_flags(ndbr));
-	if (!mmio->addr.base) {
-		dev_dbg(dev, "%s failed to map bdw\n",
-				nvdimm_name(nvdimm));
-		return -ENOMEM;
-	}
-	mmio->size = nfit_mem->bdw->size;
-	mmio->base_offset = nfit_mem->memdev_bdw->region_offset;
-	mmio->idt = nfit_mem->idt_bdw;
-	mmio->spa = nfit_mem->spa_bdw;
-	rc = nfit_blk_init_interleave(mmio, nfit_mem->idt_bdw,
-			nfit_mem->memdev_bdw->interleave_ways);
-	if (rc) {
-		dev_dbg(dev, "%s failed to init bdw interleave\n",
-				nvdimm_name(nvdimm));
-		return rc;
-	}
-
-	/* map block control memory */
-	nfit_blk->cmd_offset = nfit_mem->dcr->command_offset;
-	nfit_blk->stat_offset = nfit_mem->dcr->status_offset;
-	mmio = &nfit_blk->mmio[DCR];
-	mmio->addr.base = devm_nvdimm_ioremap(dev, nfit_mem->spa_dcr->address,
-			nfit_mem->spa_dcr->length);
-	if (!mmio->addr.base) {
-		dev_dbg(dev, "%s failed to map dcr\n",
-				nvdimm_name(nvdimm));
-		return -ENOMEM;
-	}
-	mmio->size = nfit_mem->dcr->window_size;
-	mmio->base_offset = nfit_mem->memdev_dcr->region_offset;
-	mmio->idt = nfit_mem->idt_dcr;
-	mmio->spa = nfit_mem->spa_dcr;
-	rc = nfit_blk_init_interleave(mmio, nfit_mem->idt_dcr,
-			nfit_mem->memdev_dcr->interleave_ways);
-	if (rc) {
-		dev_dbg(dev, "%s failed to init dcr interleave\n",
-				nvdimm_name(nvdimm));
-		return rc;
-	}
-
-	rc = acpi_nfit_blk_get_flags(nd_desc, nvdimm, nfit_blk);
-	if (rc < 0) {
-		dev_dbg(dev, "%s failed get DIMM flags\n",
-				nvdimm_name(nvdimm));
-		return rc;
-	}
-
-	if (nvdimm_has_flush(nfit_blk->nd_region) < 0)
-		dev_warn(dev, "unable to guarantee persistence of writes\n");
-
-	if (mmio->line_size == 0)
-		return 0;
-
-	if ((u32) nfit_blk->cmd_offset % mmio->line_size
-			+ 8 > mmio->line_size) {
-		dev_dbg(dev, "cmd_offset crosses interleave boundary\n");
-		return -ENXIO;
-	} else if ((u32) nfit_blk->stat_offset % mmio->line_size
-			+ 8 > mmio->line_size) {
-		dev_dbg(dev, "stat_offset crosses interleave boundary\n");
-		return -ENXIO;
-	}
 
 	return 0;
 }
@@ -2854,9 +2558,6 @@ static int acpi_nfit_init_mapping(struct acpi_nfit_desc *acpi_desc,
 	struct nvdimm *nvdimm = acpi_nfit_dimm_by_handle(acpi_desc,
 			memdev->device_handle);
 	struct acpi_nfit_system_address *spa = nfit_spa->spa;
-	struct nd_blk_region_desc *ndbr_desc;
-	struct nfit_mem *nfit_mem;
-	int rc;
 
 	if (!nvdimm) {
 		dev_err(acpi_desc->dev, "spa%d dimm: %#x not found\n",
@@ -2871,30 +2572,6 @@ static int acpi_nfit_init_mapping(struct acpi_nfit_desc *acpi_desc,
 		mapping->start = memdev->address;
 		mapping->size = memdev->region_size;
 		break;
-	case NFIT_SPA_DCR:
-		nfit_mem = nvdimm_provider_data(nvdimm);
-		if (!nfit_mem || !nfit_mem->bdw) {
-			dev_dbg(acpi_desc->dev, "spa%d %s missing bdw\n",
-					spa->range_index, nvdimm_name(nvdimm));
-			break;
-		}
-
-		mapping->size = nfit_mem->bdw->capacity;
-		mapping->start = nfit_mem->bdw->start_address;
-		ndr_desc->num_lanes = nfit_mem->bdw->windows;
-		ndr_desc->mapping = mapping;
-		ndr_desc->num_mappings = 1;
-		ndbr_desc = to_blk_region_desc(ndr_desc);
-		ndbr_desc->enable = acpi_nfit_blk_region_enable;
-		ndbr_desc->do_io = acpi_desc->blk_do_io;
-		rc = acpi_nfit_init_interleave_set(acpi_desc, ndr_desc, spa);
-		if (rc)
-			return rc;
-		nfit_spa->nd_region = nvdimm_blk_region_create(acpi_desc->nvdimm_bus,
-				ndr_desc);
-		if (!nfit_spa->nd_region)
-			return -ENOMEM;
-		break;
 	}
 
 	return 0;
@@ -2920,8 +2597,7 @@ static int acpi_nfit_register_region(struct acpi_nfit_desc *acpi_desc,
 {
 	static struct nd_mapping_desc mappings[ND_MAX_MAPPINGS];
 	struct acpi_nfit_system_address *spa = nfit_spa->spa;
-	struct nd_blk_region_desc ndbr_desc;
-	struct nd_region_desc *ndr_desc;
+	struct nd_region_desc *ndr_desc, _ndr_desc;
 	struct nfit_memdev *nfit_memdev;
 	struct nvdimm_bus *nvdimm_bus;
 	struct resource res;
@@ -2937,23 +2613,33 @@ static int acpi_nfit_register_region(struct acpi_nfit_desc *acpi_desc,
 
 	memset(&res, 0, sizeof(res));
 	memset(&mappings, 0, sizeof(mappings));
-	memset(&ndbr_desc, 0, sizeof(ndbr_desc));
+	memset(&_ndr_desc, 0, sizeof(_ndr_desc));
 	res.start = spa->address;
 	res.end = res.start + spa->length - 1;
-	ndr_desc = &ndbr_desc.ndr_desc;
+	ndr_desc = &_ndr_desc;
 	ndr_desc->res = &res;
 	ndr_desc->provider_data = nfit_spa;
 	ndr_desc->attr_groups = acpi_nfit_region_attribute_groups;
 	if (spa->flags & ACPI_NFIT_PROXIMITY_VALID) {
-		ndr_desc->numa_node = acpi_map_pxm_to_online_node(
-						spa->proximity_domain);
-		ndr_desc->target_node = acpi_map_pxm_to_node(
-				spa->proximity_domain);
+		ndr_desc->numa_node = pxm_to_online_node(spa->proximity_domain);
+		ndr_desc->target_node = pxm_to_node(spa->proximity_domain);
 	} else {
 		ndr_desc->numa_node = NUMA_NO_NODE;
 		ndr_desc->target_node = NUMA_NO_NODE;
 	}
 
+	/* Fallback to address based numa information if node lookup failed */
+	if (ndr_desc->numa_node == NUMA_NO_NODE) {
+		ndr_desc->numa_node = memory_add_physaddr_to_nid(spa->address);
+		dev_info(acpi_desc->dev, "changing numa node from %d to %d for nfit region [%pa-%pa]",
+			NUMA_NO_NODE, ndr_desc->numa_node, &res.start, &res.end);
+	}
+	if (ndr_desc->target_node == NUMA_NO_NODE) {
+		ndr_desc->target_node = phys_to_target_node(spa->address);
+		dev_info(acpi_desc->dev, "changing target node from %d to %d for nfit region [%pa-%pa]",
+			NUMA_NO_NODE, ndr_desc->target_node, &res.start, &res.end);
+	}
+
 	/*
 	 * Persistence domain bits are hierarchical, if
 	 * ACPI_NFIT_CAPABILITY_CACHE_FLUSH is set then
@@ -2968,6 +2654,9 @@ static int acpi_nfit_register_region(struct acpi_nfit_desc *acpi_desc,
 		struct acpi_nfit_memory_map *memdev = nfit_memdev->memdev;
 		struct nd_mapping_desc *mapping;
 
+		/* range index 0 == unmapped in SPA or invalid-SPA */
+		if (memdev->range_index == 0 || spa->range_index == 0)
+			continue;
 		if (memdev->range_index != spa->range_index)
 			continue;
 		if (count >= ND_MAX_MAPPINGS) {
@@ -3273,7 +2962,7 @@ static void acpi_nfit_init_ars(struct acpi_nfit_desc *acpi_desc,
 static int acpi_nfit_register_regions(struct acpi_nfit_desc *acpi_desc)
 {
 	struct nfit_spa *nfit_spa;
-	int rc;
+	int rc, do_sched_ars = 0;
 
 	set_bit(ARS_VALID, &acpi_desc->scrub_flags);
 	list_for_each_entry(nfit_spa, &acpi_desc->spas, list) {
@@ -3285,7 +2974,7 @@ static int acpi_nfit_register_regions(struct acpi_nfit_desc *acpi_desc)
 		}
 	}
 
-	list_for_each_entry(nfit_spa, &acpi_desc->spas, list)
+	list_for_each_entry(nfit_spa, &acpi_desc->spas, list) {
 		switch (nfit_spa_type(nfit_spa->spa)) {
 		case NFIT_SPA_VOLATILE:
 		case NFIT_SPA_PM:
@@ -3293,6 +2982,13 @@ static int acpi_nfit_register_regions(struct acpi_nfit_desc *acpi_desc)
 			rc = ars_register(acpi_desc, nfit_spa);
 			if (rc)
 				return rc;
+
+			/*
+			 * Kick off background ARS if at least one
+			 * region successfully registered ARS
+			 */
+			if (!test_bit(ARS_FAILED, &nfit_spa->ars_state))
+				do_sched_ars++;
 			break;
 		case NFIT_SPA_BDW:
 			/* nothing to register */
@@ -3311,8 +3007,10 @@ static int acpi_nfit_register_regions(struct acpi_nfit_desc *acpi_desc)
 			/* don't register unknown regions */
 			break;
 		}
+	}
 
-	sched_ars(acpi_desc);
+	if (do_sched_ars)
+		sched_ars(acpi_desc);
 	return 0;
 }
 
@@ -3453,8 +3151,8 @@ static int acpi_nfit_flush_probe(struct nvdimm_bus_descriptor *nd_desc)
 	struct device *dev = acpi_desc->dev;
 
 	/* Bounce the device lock to flush acpi_nfit_add / acpi_nfit_notify */
-	nfit_device_lock(dev);
-	nfit_device_unlock(dev);
+	device_lock(dev);
+	device_unlock(dev);
 
 	/* Bounce the init_mutex to complete initial registration */
 	mutex_lock(&acpi_desc->init_mutex);
@@ -3485,7 +3183,10 @@ static int __acpi_nfit_clear_to_send(struct nvdimm_bus_descriptor *nd_desc,
 	return 0;
 }
 
-/* prevent security commands from being issued via ioctl */
+/*
+ * Prevent security and firmware activate commands from being issued via
+ * ioctl.
+ */
 static int acpi_nfit_clear_to_send(struct nvdimm_bus_descriptor *nd_desc,
 		struct nvdimm *nvdimm, unsigned int cmd, void *buf)
 {
@@ -3496,10 +3197,15 @@ static int acpi_nfit_clear_to_send(struct nvdimm_bus_descriptor *nd_desc,
 			call_pkg->nd_family == NVDIMM_FAMILY_INTEL) {
 		func = call_pkg->nd_command;
 		if (func > NVDIMM_CMD_MAX ||
-		    (1 << func) & NVDIMM_INTEL_SECURITY_CMDMASK)
+		    (1 << func) & NVDIMM_INTEL_DENY_CMDMASK)
 			return -EOPNOTSUPP;
 	}
 
+	/* block all non-nfit bus commands */
+	if (!nvdimm && cmd == ND_CMD_CALL &&
+			call_pkg->nd_family != NVDIMM_BUS_FAMILY_NFIT)
+		return -EOPNOTSUPP;
+
 	return __acpi_nfit_clear_to_send(nd_desc, nvdimm, cmd);
 }
 
@@ -3548,7 +3254,6 @@ void acpi_nfit_desc_init(struct acpi_nfit_desc *acpi_desc, struct device *dev)
 
 	dev_set_drvdata(dev, acpi_desc);
 	acpi_desc->dev = dev;
-	acpi_desc->blk_do_io = acpi_nfit_blk_region_do_io;
 	nd_desc = &acpi_desc->nd_desc;
 	nd_desc->provider_name = "ACPI.NFIT";
 	nd_desc->module = THIS_MODULE;
@@ -3576,6 +3281,23 @@ static void acpi_nfit_put_table(void *table)
 	acpi_put_table(table);
 }
 
+static void acpi_nfit_notify(acpi_handle handle, u32 event, void *data)
+{
+	struct acpi_device *adev = data;
+
+	device_lock(&adev->dev);
+	__acpi_nfit_notify(&adev->dev, handle, event);
+	device_unlock(&adev->dev);
+}
+
+static void acpi_nfit_remove_notify_handler(void *data)
+{
+	struct acpi_device *adev = data;
+
+	acpi_dev_remove_notify_handler(adev, ACPI_DEVICE_NOTIFY,
+				       acpi_nfit_notify);
+}
+
 void acpi_nfit_shutdown(void *data)
 {
 	struct acpi_nfit_desc *acpi_desc = data;
@@ -3591,16 +3313,16 @@ void acpi_nfit_shutdown(void *data)
 
 	mutex_lock(&acpi_desc->init_mutex);
 	set_bit(ARS_CANCEL, &acpi_desc->scrub_flags);
-	cancel_delayed_work_sync(&acpi_desc->dwork);
 	mutex_unlock(&acpi_desc->init_mutex);
+	cancel_delayed_work_sync(&acpi_desc->dwork);
 
 	/*
 	 * Bounce the nvdimm bus lock to make sure any in-flight
 	 * acpi_nfit_ars_rescan() submissions have had a chance to
 	 * either submit or see ->cancel set.
 	 */
-	nfit_device_lock(bus_dev);
-	nfit_device_unlock(bus_dev);
+	device_lock(bus_dev);
+	device_unlock(bus_dev);
 
 	flush_workqueue(nfit_wq);
 }
@@ -3616,6 +3338,16 @@ static int acpi_nfit_add(struct acpi_device *adev)
 	acpi_size sz;
 	int rc = 0;
 
+	rc = acpi_dev_install_notify_handler(adev, ACPI_DEVICE_NOTIFY,
+					     acpi_nfit_notify, adev);
+	if (rc)
+		return rc;
+
+	rc = devm_add_action_or_reset(dev, acpi_nfit_remove_notify_handler,
+					adev);
+	if (rc)
+		return rc;
+
 	status = acpi_get_table(ACPI_SIG_NFIT, 0, &tbl);
 	if (ACPI_FAILURE(status)) {
 		/* The NVDIMM root device allows OS to trigger enumeration of
@@ -3662,13 +3394,8 @@ static int acpi_nfit_add(struct acpi_device *adev)
 
 	if (rc)
 		return rc;
-	return devm_add_action_or_reset(dev, acpi_nfit_shutdown, acpi_desc);
-}
 
-static int acpi_nfit_remove(struct acpi_device *adev)
-{
-	/* see acpi_nfit_unregister */
-	return 0;
+	return devm_add_action_or_reset(dev, acpi_nfit_shutdown, acpi_desc);
 }
 
 static void acpi_nfit_update_notify(struct device *dev, acpi_handle handle)
@@ -3741,13 +3468,6 @@ void __acpi_nfit_notify(struct device *dev, acpi_handle handle, u32 event)
 }
 EXPORT_SYMBOL_GPL(__acpi_nfit_notify);
 
-static void acpi_nfit_notify(struct acpi_device *adev, u32 event)
-{
-	nfit_device_lock(&adev->dev);
-	__acpi_nfit_notify(&adev->dev, adev->handle, event);
-	nfit_device_unlock(&adev->dev);
-}
-
 static const struct acpi_device_id acpi_nfit_ids[] = {
 	{ "ACPI0012", 0 },
 	{ "", 0 },
@@ -3759,8 +3479,6 @@ static struct acpi_driver acpi_nfit_driver = {
 	.ids = acpi_nfit_ids,
 	.ops = {
 		.add = acpi_nfit_add,
-		.remove = acpi_nfit_remove,
-		.notify = acpi_nfit_notify,
 	},
 };
 
@@ -3769,10 +3487,10 @@ static __init int nfit_init(void)
 	int ret;
 
 	BUILD_BUG_ON(sizeof(struct acpi_table_nfit) != 40);
-	BUILD_BUG_ON(sizeof(struct acpi_nfit_system_address) != 56);
+	BUILD_BUG_ON(sizeof(struct acpi_nfit_system_address) != 64);
 	BUILD_BUG_ON(sizeof(struct acpi_nfit_memory_map) != 48);
-	BUILD_BUG_ON(sizeof(struct acpi_nfit_interleave) != 20);
-	BUILD_BUG_ON(sizeof(struct acpi_nfit_smbios) != 9);
+	BUILD_BUG_ON(sizeof(struct acpi_nfit_interleave) != 16);
+	BUILD_BUG_ON(sizeof(struct acpi_nfit_smbios) != 8);
 	BUILD_BUG_ON(sizeof(struct acpi_nfit_control_region) != 80);
 	BUILD_BUG_ON(sizeof(struct acpi_nfit_data_region) != 40);
 	BUILD_BUG_ON(sizeof(struct acpi_nfit_capabilities) != 16);
@@ -3791,6 +3509,7 @@ static __init int nfit_init(void)
 	guid_parse(UUID_NFIT_DIMM_N_HPE2, &nfit_uuid[NFIT_DEV_DIMM_N_HPE2]);
 	guid_parse(UUID_NFIT_DIMM_N_MSFT, &nfit_uuid[NFIT_DEV_DIMM_N_MSFT]);
 	guid_parse(UUID_NFIT_DIMM_N_HYPERV, &nfit_uuid[NFIT_DEV_DIMM_N_HYPERV]);
+	guid_parse(UUID_INTEL_BUS, &nfit_uuid[NFIT_BUS_INTEL]);
 
 	nfit_wq = create_singlethread_workqueue("nfit");
 	if (!nfit_wq)
@@ -3817,5 +3536,6 @@ static __exit void nfit_exit(void)
 
 module_init(nfit_init);
 module_exit(nfit_exit);
+MODULE_DESCRIPTION("ACPI NVDIMM Firmware Interface Table (NFIT) driver");
 MODULE_LICENSE("GPL v2");
 MODULE_AUTHOR("Intel Corporation");
diff --git a/drivers/acpi/nfit/intel.c b/drivers/acpi/nfit/intel.c
index 1113b679cd7b..bce6f6a18426 100644
--- a/drivers/acpi/nfit/intel.c
+++ b/drivers/acpi/nfit/intel.c
@@ -3,19 +3,61 @@
 #include <linux/libnvdimm.h>
 #include <linux/ndctl.h>
 #include <linux/acpi.h>
+#include <linux/memregion.h>
 #include <asm/smp.h>
 #include "intel.h"
 #include "nfit.h"
 
+static ssize_t firmware_activate_noidle_show(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct nvdimm_bus *nvdimm_bus = to_nvdimm_bus(dev);
+	struct nvdimm_bus_descriptor *nd_desc = to_nd_desc(nvdimm_bus);
+	struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc);
+
+	return sprintf(buf, "%s\n", acpi_desc->fwa_noidle ? "Y" : "N");
+}
+
+static ssize_t firmware_activate_noidle_store(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t size)
+{
+	struct nvdimm_bus *nvdimm_bus = to_nvdimm_bus(dev);
+	struct nvdimm_bus_descriptor *nd_desc = to_nd_desc(nvdimm_bus);
+	struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc);
+	ssize_t rc;
+	bool val;
+
+	rc = kstrtobool(buf, &val);
+	if (rc)
+		return rc;
+	if (val != acpi_desc->fwa_noidle)
+		acpi_desc->fwa_cap = NVDIMM_FWA_CAP_INVALID;
+	acpi_desc->fwa_noidle = val;
+	return size;
+}
+DEVICE_ATTR_RW(firmware_activate_noidle);
+
+bool intel_fwa_supported(struct nvdimm_bus *nvdimm_bus)
+{
+	struct nvdimm_bus_descriptor *nd_desc = to_nd_desc(nvdimm_bus);
+	struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc);
+	unsigned long *mask;
+
+	if (!test_bit(NVDIMM_BUS_FAMILY_INTEL, &nd_desc->bus_family_mask))
+		return false;
+
+	mask = &acpi_desc->family_dsm_mask[NVDIMM_BUS_FAMILY_INTEL];
+	return *mask == NVDIMM_BUS_INTEL_FW_ACTIVATE_CMDMASK;
+}
+
 static unsigned long intel_security_flags(struct nvdimm *nvdimm,
 		enum nvdimm_passphrase_type ptype)
 {
 	struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm);
 	unsigned long security_flags = 0;
-	struct {
-		struct nd_cmd_pkg pkg;
+	TRAILING_OVERLAP(struct nd_cmd_pkg, pkg, nd_payload,
 		struct nd_intel_get_security_state cmd;
-	} nd_cmd = {
+	) nd_cmd = {
 		.pkg = {
 			.nd_command = NVDIMM_INTEL_GET_SECURITY_STATE,
 			.nd_family = NVDIMM_FAMILY_INTEL,
@@ -77,10 +119,9 @@ static unsigned long intel_security_flags(struct nvdimm *nvdimm,
 static int intel_security_freeze(struct nvdimm *nvdimm)
 {
 	struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm);
-	struct {
-		struct nd_cmd_pkg pkg;
+	TRAILING_OVERLAP(struct nd_cmd_pkg, pkg, nd_payload,
 		struct nd_intel_freeze_lock cmd;
-	} nd_cmd = {
+	) nd_cmd = {
 		.pkg = {
 			.nd_command = NVDIMM_INTEL_FREEZE_LOCK,
 			.nd_family = NVDIMM_FAMILY_INTEL,
@@ -110,10 +151,9 @@ static int intel_security_change_key(struct nvdimm *nvdimm,
 	unsigned int cmd = ptype == NVDIMM_MASTER ?
 		NVDIMM_INTEL_SET_MASTER_PASSPHRASE :
 		NVDIMM_INTEL_SET_PASSPHRASE;
-	struct {
-		struct nd_cmd_pkg pkg;
+	TRAILING_OVERLAP(struct nd_cmd_pkg, pkg, nd_payload,
 		struct nd_intel_set_passphrase cmd;
-	} nd_cmd = {
+	) nd_cmd = {
 		.pkg = {
 			.nd_family = NVDIMM_FAMILY_INTEL,
 			.nd_size_in = ND_INTEL_PASSPHRASE_SIZE * 2,
@@ -148,16 +188,13 @@ static int intel_security_change_key(struct nvdimm *nvdimm,
 	}
 }
 
-static void nvdimm_invalidate_cache(void);
-
 static int __maybe_unused intel_security_unlock(struct nvdimm *nvdimm,
 		const struct nvdimm_key_data *key_data)
 {
 	struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm);
-	struct {
-		struct nd_cmd_pkg pkg;
+	TRAILING_OVERLAP(struct nd_cmd_pkg, pkg, nd_payload,
 		struct nd_intel_unlock_unit cmd;
-	} nd_cmd = {
+	) nd_cmd = {
 		.pkg = {
 			.nd_command = NVDIMM_INTEL_UNLOCK_UNIT,
 			.nd_family = NVDIMM_FAMILY_INTEL,
@@ -185,9 +222,6 @@ static int __maybe_unused intel_security_unlock(struct nvdimm *nvdimm,
 		return -EIO;
 	}
 
-	/* DIMM unlocked, invalidate all CPU caches before we read it */
-	nvdimm_invalidate_cache();
-
 	return 0;
 }
 
@@ -196,10 +230,9 @@ static int intel_security_disable(struct nvdimm *nvdimm,
 {
 	int rc;
 	struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm);
-	struct {
-		struct nd_cmd_pkg pkg;
+	TRAILING_OVERLAP(struct nd_cmd_pkg, pkg, nd_payload,
 		struct nd_intel_disable_passphrase cmd;
-	} nd_cmd = {
+	) nd_cmd = {
 		.pkg = {
 			.nd_command = NVDIMM_INTEL_DISABLE_PASSPHRASE,
 			.nd_family = NVDIMM_FAMILY_INTEL,
@@ -239,10 +272,9 @@ static int __maybe_unused intel_security_erase(struct nvdimm *nvdimm,
 	struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm);
 	unsigned int cmd = ptype == NVDIMM_MASTER ?
 		NVDIMM_INTEL_MASTER_SECURE_ERASE : NVDIMM_INTEL_SECURE_ERASE;
-	struct {
-		struct nd_cmd_pkg pkg;
+	TRAILING_OVERLAP(struct nd_cmd_pkg, pkg, nd_payload,
 		struct nd_intel_secure_erase cmd;
-	} nd_cmd = {
+	) nd_cmd = {
 		.pkg = {
 			.nd_family = NVDIMM_FAMILY_INTEL,
 			.nd_size_in = ND_INTEL_PASSPHRASE_SIZE,
@@ -255,8 +287,6 @@ static int __maybe_unused intel_security_erase(struct nvdimm *nvdimm,
 	if (!test_bit(cmd, &nfit_mem->dsm_mask))
 		return -ENOTTY;
 
-	/* flush all cache before we erase DIMM */
-	nvdimm_invalidate_cache();
 	memcpy(nd_cmd.cmd.passphrase, key->data,
 			sizeof(nd_cmd.cmd.passphrase));
 	rc = nvdimm_ctl(nvdimm, ND_CMD_CALL, &nd_cmd, sizeof(nd_cmd), NULL);
@@ -275,8 +305,6 @@ static int __maybe_unused intel_security_erase(struct nvdimm *nvdimm,
 		return -ENXIO;
 	}
 
-	/* DIMM erased, invalidate all CPU caches before we read it */
-	nvdimm_invalidate_cache();
 	return 0;
 }
 
@@ -284,10 +312,9 @@ static int __maybe_unused intel_security_query_overwrite(struct nvdimm *nvdimm)
 {
 	int rc;
 	struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm);
-	struct {
-		struct nd_cmd_pkg pkg;
+	TRAILING_OVERLAP(struct nd_cmd_pkg, pkg, nd_payload,
 		struct nd_intel_query_overwrite cmd;
-	} nd_cmd = {
+	) nd_cmd = {
 		.pkg = {
 			.nd_command = NVDIMM_INTEL_QUERY_OVERWRITE,
 			.nd_family = NVDIMM_FAMILY_INTEL,
@@ -312,8 +339,6 @@ static int __maybe_unused intel_security_query_overwrite(struct nvdimm *nvdimm)
 		return -ENXIO;
 	}
 
-	/* flush all cache before we make the nvdimms available */
-	nvdimm_invalidate_cache();
 	return 0;
 }
 
@@ -322,10 +347,9 @@ static int __maybe_unused intel_security_overwrite(struct nvdimm *nvdimm,
 {
 	int rc;
 	struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm);
-	struct {
-		struct nd_cmd_pkg pkg;
+	TRAILING_OVERLAP(struct nd_cmd_pkg, pkg, nd_payload,
 		struct nd_intel_overwrite cmd;
-	} nd_cmd = {
+	) nd_cmd = {
 		.pkg = {
 			.nd_command = NVDIMM_INTEL_OVERWRITE,
 			.nd_family = NVDIMM_FAMILY_INTEL,
@@ -338,8 +362,6 @@ static int __maybe_unused intel_security_overwrite(struct nvdimm *nvdimm,
 	if (!test_bit(NVDIMM_INTEL_OVERWRITE, &nfit_mem->dsm_mask))
 		return -ENOTTY;
 
-	/* flush all cache before we erase DIMM */
-	nvdimm_invalidate_cache();
 	memcpy(nd_cmd.cmd.passphrase, nkey->data,
 			sizeof(nd_cmd.cmd.passphrase));
 	rc = nvdimm_ctl(nvdimm, ND_CMD_CALL, &nd_cmd, sizeof(nd_cmd), NULL);
@@ -359,22 +381,6 @@ static int __maybe_unused intel_security_overwrite(struct nvdimm *nvdimm,
 	}
 }
 
-/*
- * TODO: define a cross arch wbinvd equivalent when/if
- * NVDIMM_FAMILY_INTEL command support arrives on another arch.
- */
-#ifdef CONFIG_X86
-static void nvdimm_invalidate_cache(void)
-{
-	wbinvd_on_all_cpus();
-}
-#else
-static void nvdimm_invalidate_cache(void)
-{
-	WARN_ON_ONCE("cache invalidation required after unlock\n");
-}
-#endif
-
 static const struct nvdimm_security_ops __intel_security_ops = {
 	.get_flags = intel_security_flags,
 	.freeze = intel_security_freeze,
@@ -389,3 +395,340 @@ static const struct nvdimm_security_ops __intel_security_ops = {
 };
 
 const struct nvdimm_security_ops *intel_security_ops = &__intel_security_ops;
+
+static int intel_bus_fwa_businfo(struct nvdimm_bus_descriptor *nd_desc,
+		struct nd_intel_bus_fw_activate_businfo *info)
+{
+	TRAILING_OVERLAP(struct nd_cmd_pkg, pkg, nd_payload,
+		struct nd_intel_bus_fw_activate_businfo cmd;
+	) nd_cmd = {
+		.pkg = {
+			.nd_command = NVDIMM_BUS_INTEL_FW_ACTIVATE_BUSINFO,
+			.nd_family = NVDIMM_BUS_FAMILY_INTEL,
+			.nd_size_out =
+				sizeof(struct nd_intel_bus_fw_activate_businfo),
+			.nd_fw_size =
+				sizeof(struct nd_intel_bus_fw_activate_businfo),
+		},
+	};
+	int rc;
+
+	rc = nd_desc->ndctl(nd_desc, NULL, ND_CMD_CALL, &nd_cmd, sizeof(nd_cmd),
+			NULL);
+	*info = nd_cmd.cmd;
+	return rc;
+}
+
+/* The fw_ops expect to be called with the nvdimm_bus_lock() held */
+static enum nvdimm_fwa_state intel_bus_fwa_state(
+		struct nvdimm_bus_descriptor *nd_desc)
+{
+	struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc);
+	struct nd_intel_bus_fw_activate_businfo info;
+	struct device *dev = acpi_desc->dev;
+	enum nvdimm_fwa_state state;
+	int rc;
+
+	/*
+	 * It should not be possible for platform firmware to return
+	 * busy because activate is a synchronous operation. Treat it
+	 * similar to invalid, i.e. always refresh / poll the status.
+	 */
+	switch (acpi_desc->fwa_state) {
+	case NVDIMM_FWA_INVALID:
+	case NVDIMM_FWA_BUSY:
+		break;
+	default:
+		/* check if capability needs to be refreshed */
+		if (acpi_desc->fwa_cap == NVDIMM_FWA_CAP_INVALID)
+			break;
+		return acpi_desc->fwa_state;
+	}
+
+	/* Refresh with platform firmware */
+	rc = intel_bus_fwa_businfo(nd_desc, &info);
+	if (rc)
+		return NVDIMM_FWA_INVALID;
+
+	switch (info.state) {
+	case ND_INTEL_FWA_IDLE:
+		state = NVDIMM_FWA_IDLE;
+		break;
+	case ND_INTEL_FWA_BUSY:
+		state = NVDIMM_FWA_BUSY;
+		break;
+	case ND_INTEL_FWA_ARMED:
+		if (info.activate_tmo > info.max_quiesce_tmo)
+			state = NVDIMM_FWA_ARM_OVERFLOW;
+		else
+			state = NVDIMM_FWA_ARMED;
+		break;
+	default:
+		dev_err_once(dev, "invalid firmware activate state %d\n",
+				info.state);
+		return NVDIMM_FWA_INVALID;
+	}
+
+	/*
+	 * Capability data is available in the same payload as state. It
+	 * is expected to be static.
+	 */
+	if (acpi_desc->fwa_cap == NVDIMM_FWA_CAP_INVALID) {
+		if (info.capability & ND_INTEL_BUS_FWA_CAP_FWQUIESCE)
+			acpi_desc->fwa_cap = NVDIMM_FWA_CAP_QUIESCE;
+		else if (info.capability & ND_INTEL_BUS_FWA_CAP_OSQUIESCE) {
+			/*
+			 * Skip hibernate cycle by default if platform
+			 * indicates that it does not need devices to be
+			 * quiesced.
+			 */
+			acpi_desc->fwa_cap = NVDIMM_FWA_CAP_LIVE;
+		} else
+			acpi_desc->fwa_cap = NVDIMM_FWA_CAP_NONE;
+	}
+
+	acpi_desc->fwa_state = state;
+
+	return state;
+}
+
+static enum nvdimm_fwa_capability intel_bus_fwa_capability(
+		struct nvdimm_bus_descriptor *nd_desc)
+{
+	struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc);
+
+	if (acpi_desc->fwa_cap > NVDIMM_FWA_CAP_INVALID)
+		return acpi_desc->fwa_cap;
+
+	if (intel_bus_fwa_state(nd_desc) > NVDIMM_FWA_INVALID)
+		return acpi_desc->fwa_cap;
+
+	return NVDIMM_FWA_CAP_INVALID;
+}
+
+static int intel_bus_fwa_activate(struct nvdimm_bus_descriptor *nd_desc)
+{
+	struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc);
+	TRAILING_OVERLAP(struct nd_cmd_pkg, pkg, nd_payload,
+		struct nd_intel_bus_fw_activate cmd;
+	) nd_cmd;
+	int rc;
+
+	nd_cmd.pkg = (struct nd_cmd_pkg) {
+		.nd_command = NVDIMM_BUS_INTEL_FW_ACTIVATE,
+		.nd_family = NVDIMM_BUS_FAMILY_INTEL,
+		.nd_size_in = sizeof(nd_cmd.cmd.iodev_state),
+		.nd_size_out =
+			sizeof(struct nd_intel_bus_fw_activate),
+		.nd_fw_size =
+			sizeof(struct nd_intel_bus_fw_activate),
+	};
+	nd_cmd.cmd = (struct nd_intel_bus_fw_activate) {
+		/*
+		 * Even though activate is run from a suspended context,
+		 * for safety, still ask platform firmware to force
+		 * quiesce devices by default. Let a module
+		 * parameter override that policy.
+		 */
+		.iodev_state = acpi_desc->fwa_noidle
+			? ND_INTEL_BUS_FWA_IODEV_OS_IDLE
+			: ND_INTEL_BUS_FWA_IODEV_FORCE_IDLE,
+	};
+	switch (intel_bus_fwa_state(nd_desc)) {
+	case NVDIMM_FWA_ARMED:
+	case NVDIMM_FWA_ARM_OVERFLOW:
+		break;
+	default:
+		return -ENXIO;
+	}
+
+	rc = nd_desc->ndctl(nd_desc, NULL, ND_CMD_CALL, &nd_cmd, sizeof(nd_cmd),
+			NULL);
+
+	/*
+	 * Whether the command succeeded, or failed, the agent checking
+	 * for the result needs to query the DIMMs individually.
+	 * Increment the activation count to invalidate all the DIMM
+	 * states at once (it's otherwise not possible to take
+	 * acpi_desc->init_mutex in this context)
+	 */
+	acpi_desc->fwa_state = NVDIMM_FWA_INVALID;
+	acpi_desc->fwa_count++;
+
+	dev_dbg(acpi_desc->dev, "result: %d\n", rc);
+
+	return rc;
+}
+
+static const struct nvdimm_bus_fw_ops __intel_bus_fw_ops = {
+	.activate_state = intel_bus_fwa_state,
+	.capability = intel_bus_fwa_capability,
+	.activate = intel_bus_fwa_activate,
+};
+
+const struct nvdimm_bus_fw_ops *intel_bus_fw_ops = &__intel_bus_fw_ops;
+
+static int intel_fwa_dimminfo(struct nvdimm *nvdimm,
+		struct nd_intel_fw_activate_dimminfo *info)
+{
+	TRAILING_OVERLAP(struct nd_cmd_pkg, pkg, nd_payload,
+		struct nd_intel_fw_activate_dimminfo cmd;
+	) nd_cmd = {
+		.pkg = {
+			.nd_command = NVDIMM_INTEL_FW_ACTIVATE_DIMMINFO,
+			.nd_family = NVDIMM_FAMILY_INTEL,
+			.nd_size_out =
+				sizeof(struct nd_intel_fw_activate_dimminfo),
+			.nd_fw_size =
+				sizeof(struct nd_intel_fw_activate_dimminfo),
+		},
+	};
+	int rc;
+
+	rc = nvdimm_ctl(nvdimm, ND_CMD_CALL, &nd_cmd, sizeof(nd_cmd), NULL);
+	*info = nd_cmd.cmd;
+	return rc;
+}
+
+static enum nvdimm_fwa_state intel_fwa_state(struct nvdimm *nvdimm)
+{
+	struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm);
+	struct acpi_nfit_desc *acpi_desc = nfit_mem->acpi_desc;
+	struct nd_intel_fw_activate_dimminfo info;
+	int rc;
+
+	/*
+	 * Similar to the bus state, since activate is synchronous the
+	 * busy state should resolve within the context of 'activate'.
+	 */
+	switch (nfit_mem->fwa_state) {
+	case NVDIMM_FWA_INVALID:
+	case NVDIMM_FWA_BUSY:
+		break;
+	default:
+		/* If no activations occurred the old state is still valid */
+		if (nfit_mem->fwa_count == acpi_desc->fwa_count)
+			return nfit_mem->fwa_state;
+	}
+
+	rc = intel_fwa_dimminfo(nvdimm, &info);
+	if (rc)
+		return NVDIMM_FWA_INVALID;
+
+	switch (info.state) {
+	case ND_INTEL_FWA_IDLE:
+		nfit_mem->fwa_state = NVDIMM_FWA_IDLE;
+		break;
+	case ND_INTEL_FWA_BUSY:
+		nfit_mem->fwa_state = NVDIMM_FWA_BUSY;
+		break;
+	case ND_INTEL_FWA_ARMED:
+		nfit_mem->fwa_state = NVDIMM_FWA_ARMED;
+		break;
+	default:
+		nfit_mem->fwa_state = NVDIMM_FWA_INVALID;
+		break;
+	}
+
+	switch (info.result) {
+	case ND_INTEL_DIMM_FWA_NONE:
+		nfit_mem->fwa_result = NVDIMM_FWA_RESULT_NONE;
+		break;
+	case ND_INTEL_DIMM_FWA_SUCCESS:
+		nfit_mem->fwa_result = NVDIMM_FWA_RESULT_SUCCESS;
+		break;
+	case ND_INTEL_DIMM_FWA_NOTSTAGED:
+		nfit_mem->fwa_result = NVDIMM_FWA_RESULT_NOTSTAGED;
+		break;
+	case ND_INTEL_DIMM_FWA_NEEDRESET:
+		nfit_mem->fwa_result = NVDIMM_FWA_RESULT_NEEDRESET;
+		break;
+	case ND_INTEL_DIMM_FWA_MEDIAFAILED:
+	case ND_INTEL_DIMM_FWA_ABORT:
+	case ND_INTEL_DIMM_FWA_NOTSUPP:
+	case ND_INTEL_DIMM_FWA_ERROR:
+	default:
+		nfit_mem->fwa_result = NVDIMM_FWA_RESULT_FAIL;
+		break;
+	}
+
+	nfit_mem->fwa_count = acpi_desc->fwa_count;
+
+	return nfit_mem->fwa_state;
+}
+
+static enum nvdimm_fwa_result intel_fwa_result(struct nvdimm *nvdimm)
+{
+	struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm);
+	struct acpi_nfit_desc *acpi_desc = nfit_mem->acpi_desc;
+
+	if (nfit_mem->fwa_count == acpi_desc->fwa_count
+			&& nfit_mem->fwa_result > NVDIMM_FWA_RESULT_INVALID)
+		return nfit_mem->fwa_result;
+
+	if (intel_fwa_state(nvdimm) > NVDIMM_FWA_INVALID)
+		return nfit_mem->fwa_result;
+
+	return NVDIMM_FWA_RESULT_INVALID;
+}
+
+static int intel_fwa_arm(struct nvdimm *nvdimm, enum nvdimm_fwa_trigger arm)
+{
+	struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm);
+	struct acpi_nfit_desc *acpi_desc = nfit_mem->acpi_desc;
+	TRAILING_OVERLAP(struct nd_cmd_pkg, pkg, nd_payload,
+		struct nd_intel_fw_activate_arm cmd;
+	) nd_cmd;
+	int rc;
+
+	nd_cmd.pkg = (struct nd_cmd_pkg) {
+		.nd_command = NVDIMM_INTEL_FW_ACTIVATE_ARM,
+		.nd_family = NVDIMM_FAMILY_INTEL,
+		.nd_size_in = sizeof(nd_cmd.cmd.activate_arm),
+		.nd_size_out = sizeof(struct nd_intel_fw_activate_arm),
+		.nd_fw_size = sizeof(struct nd_intel_fw_activate_arm),
+	};
+	nd_cmd.cmd = (struct nd_intel_fw_activate_arm) {
+		.activate_arm = arm == NVDIMM_FWA_ARM ?
+					ND_INTEL_DIMM_FWA_ARM :
+					ND_INTEL_DIMM_FWA_DISARM,
+	};
+
+	switch (intel_fwa_state(nvdimm)) {
+	case NVDIMM_FWA_INVALID:
+		return -ENXIO;
+	case NVDIMM_FWA_BUSY:
+		return -EBUSY;
+	case NVDIMM_FWA_IDLE:
+		if (arm == NVDIMM_FWA_DISARM)
+			return 0;
+		break;
+	case NVDIMM_FWA_ARMED:
+		if (arm == NVDIMM_FWA_ARM)
+			return 0;
+		break;
+	default:
+		return -ENXIO;
+	}
+
+	/*
+	 * Invalidate the bus-level state, now that we're committed to
+	 * changing the 'arm' state.
+	 */
+	acpi_desc->fwa_state = NVDIMM_FWA_INVALID;
+	nfit_mem->fwa_state = NVDIMM_FWA_INVALID;
+
+	rc = nvdimm_ctl(nvdimm, ND_CMD_CALL, &nd_cmd, sizeof(nd_cmd), NULL);
+
+	dev_dbg(acpi_desc->dev, "%s result: %d\n", arm == NVDIMM_FWA_ARM
+			? "arm" : "disarm", rc);
+	return rc;
+}
+
+static const struct nvdimm_fw_ops __intel_fw_ops = {
+	.activate_state = intel_fwa_state,
+	.activate_result = intel_fwa_result,
+	.arm = intel_fwa_arm,
+};
+
+const struct nvdimm_fw_ops *intel_fw_ops = &__intel_fw_ops;
diff --git a/drivers/acpi/nfit/intel.h b/drivers/acpi/nfit/intel.h
index 0aca682ab9d7..b768234ccebc 100644
--- a/drivers/acpi/nfit/intel.h
+++ b/drivers/acpi/nfit/intel.h
@@ -111,4 +111,65 @@ struct nd_intel_master_secure_erase {
 	u8 passphrase[ND_INTEL_PASSPHRASE_SIZE];
 	u32 status;
 } __packed;
+
+#define ND_INTEL_FWA_IDLE 0
+#define ND_INTEL_FWA_ARMED 1
+#define ND_INTEL_FWA_BUSY 2
+
+#define ND_INTEL_DIMM_FWA_NONE 0
+#define ND_INTEL_DIMM_FWA_NOTSTAGED 1
+#define ND_INTEL_DIMM_FWA_SUCCESS 2
+#define ND_INTEL_DIMM_FWA_NEEDRESET 3
+#define ND_INTEL_DIMM_FWA_MEDIAFAILED 4
+#define ND_INTEL_DIMM_FWA_ABORT 5
+#define ND_INTEL_DIMM_FWA_NOTSUPP 6
+#define ND_INTEL_DIMM_FWA_ERROR 7
+
+struct nd_intel_fw_activate_dimminfo {
+	u32 status;
+	u16 result;
+	u8 state;
+	u8 reserved[7];
+} __packed;
+
+#define ND_INTEL_DIMM_FWA_ARM 1
+#define ND_INTEL_DIMM_FWA_DISARM 0
+
+struct nd_intel_fw_activate_arm {
+	u8 activate_arm;
+	u32 status;
+} __packed;
+
+/* Root device command payloads */
+#define ND_INTEL_BUS_FWA_CAP_FWQUIESCE (1 << 0)
+#define ND_INTEL_BUS_FWA_CAP_OSQUIESCE (1 << 1)
+#define ND_INTEL_BUS_FWA_CAP_RESET     (1 << 2)
+
+struct nd_intel_bus_fw_activate_businfo {
+	u32 status;
+	u16 reserved;
+	u8 state;
+	u8 capability;
+	u64 activate_tmo;
+	u64 cpu_quiesce_tmo;
+	u64 io_quiesce_tmo;
+	u64 max_quiesce_tmo;
+} __packed;
+
+#define ND_INTEL_BUS_FWA_STATUS_NOARM  (6 | 1 << 16)
+#define ND_INTEL_BUS_FWA_STATUS_BUSY   (6 | 2 << 16)
+#define ND_INTEL_BUS_FWA_STATUS_NOFW   (6 | 3 << 16)
+#define ND_INTEL_BUS_FWA_STATUS_TMO    (6 | 4 << 16)
+#define ND_INTEL_BUS_FWA_STATUS_NOIDLE (6 | 5 << 16)
+#define ND_INTEL_BUS_FWA_STATUS_ABORT  (6 | 6 << 16)
+
+#define ND_INTEL_BUS_FWA_IODEV_FORCE_IDLE (0)
+#define ND_INTEL_BUS_FWA_IODEV_OS_IDLE (1)
+struct nd_intel_bus_fw_activate {
+	u8 iodev_state;
+	u32 status;
+} __packed;
+
+extern const struct nvdimm_fw_ops *intel_fw_ops;
+extern const struct nvdimm_bus_fw_ops *intel_bus_fw_ops;
 #endif
diff --git a/drivers/acpi/nfit/mce.c b/drivers/acpi/nfit/mce.c
index f0ae48515b48..d48a388b796e 100644
--- a/drivers/acpi/nfit/mce.c
+++ b/drivers/acpi/nfit/mce.c
@@ -32,6 +32,7 @@ static int nfit_handle_mce(struct notifier_block *nb, unsigned long val,
 	 */
 	mutex_lock(&acpi_desc_lock);
 	list_for_each_entry(acpi_desc, &acpi_descs, list) {
+		unsigned int align = 1UL << MCI_MISC_ADDR_LSB(mce->misc);
 		struct device *dev = acpi_desc->dev;
 		int found_match = 0;
 
@@ -63,8 +64,7 @@ static int nfit_handle_mce(struct notifier_block *nb, unsigned long val,
 
 		/* If this fails due to an -ENOMEM, there is little we can do */
 		nvdimm_bus_add_badrange(acpi_desc->nvdimm_bus,
-				ALIGN(mce->addr, L1_CACHE_BYTES),
-				L1_CACHE_BYTES);
+				ALIGN_DOWN(mce->addr, align), align);
 		nvdimm_region_notify(nfit_spa->nd_region,
 				NVDIMM_REVALIDATE_POISON);
 
@@ -76,6 +76,7 @@ static int nfit_handle_mce(struct notifier_block *nb, unsigned long val,
 			 */
 			acpi_nfit_ars_rescan(acpi_desc, 0);
 		}
+		mce->kflags |= MCE_HANDLED_NFIT;
 		break;
 	}
 
diff --git a/drivers/acpi/nfit/nfit.h b/drivers/acpi/nfit/nfit.h
index f5525f8bb770..573bc0de2990 100644
--- a/drivers/acpi/nfit/nfit.h
+++ b/drivers/acpi/nfit/nfit.h
@@ -16,8 +16,9 @@
 /* ACPI 6.1 */
 #define UUID_NFIT_BUS "2f10e7a4-9e91-11e4-89d3-123b93f75cba"
 
-/* http://pmem.io/documents/NVDIMM_DSM_Interface-V1.6.pdf */
+/* https://pmem.io/documents/NVDIMM_DSM_Interface-V1.6.pdf */
 #define UUID_NFIT_DIMM "4309ac30-0d11-11e4-9191-0800200c9a66"
+#define UUID_INTEL_BUS "c7d8acd4-2df8-4b82-9f65-a325335af149"
 
 /* https://github.com/HewlettPackard/hpe-nvm/blob/master/Documentation/ */
 #define UUID_NFIT_DIMM_N_HPE1 "9002c334-acf3-4c0e-9642-a235f0d53bc6"
@@ -33,7 +34,6 @@
 		| ACPI_NFIT_MEM_RESTORE_FAILED | ACPI_NFIT_MEM_FLUSH_FAILED \
 		| ACPI_NFIT_MEM_NOT_ARMED | ACPI_NFIT_MEM_MAP_FAILED)
 
-#define NVDIMM_FAMILY_MAX NVDIMM_FAMILY_HYPERV
 #define NVDIMM_CMD_MAX 31
 
 #define NVDIMM_STANDARD_CMDMASK \
@@ -66,6 +66,13 @@ enum nvdimm_family_cmds {
 	NVDIMM_INTEL_QUERY_OVERWRITE = 26,
 	NVDIMM_INTEL_SET_MASTER_PASSPHRASE = 27,
 	NVDIMM_INTEL_MASTER_SECURE_ERASE = 28,
+	NVDIMM_INTEL_FW_ACTIVATE_DIMMINFO = 29,
+	NVDIMM_INTEL_FW_ACTIVATE_ARM = 30,
+};
+
+enum nvdimm_bus_family_cmds {
+	NVDIMM_BUS_INTEL_FW_ACTIVATE_BUSINFO = 1,
+	NVDIMM_BUS_INTEL_FW_ACTIVATE = 2,
 };
 
 #define NVDIMM_INTEL_SECURITY_CMDMASK \
@@ -76,13 +83,22 @@ enum nvdimm_family_cmds {
 | 1 << NVDIMM_INTEL_SET_MASTER_PASSPHRASE \
 | 1 << NVDIMM_INTEL_MASTER_SECURE_ERASE)
 
+#define NVDIMM_INTEL_FW_ACTIVATE_CMDMASK \
+(1 << NVDIMM_INTEL_FW_ACTIVATE_DIMMINFO | 1 << NVDIMM_INTEL_FW_ACTIVATE_ARM)
+
+#define NVDIMM_BUS_INTEL_FW_ACTIVATE_CMDMASK \
+(1 << NVDIMM_BUS_INTEL_FW_ACTIVATE_BUSINFO | 1 << NVDIMM_BUS_INTEL_FW_ACTIVATE)
+
 #define NVDIMM_INTEL_CMDMASK \
 (NVDIMM_STANDARD_CMDMASK | 1 << NVDIMM_INTEL_GET_MODES \
  | 1 << NVDIMM_INTEL_GET_FWINFO | 1 << NVDIMM_INTEL_START_FWUPDATE \
  | 1 << NVDIMM_INTEL_SEND_FWUPDATE | 1 << NVDIMM_INTEL_FINISH_FWUPDATE \
  | 1 << NVDIMM_INTEL_QUERY_FWUPDATE | 1 << NVDIMM_INTEL_SET_THRESHOLD \
  | 1 << NVDIMM_INTEL_INJECT_ERROR | 1 << NVDIMM_INTEL_LATCH_SHUTDOWN \
- | NVDIMM_INTEL_SECURITY_CMDMASK)
+ | NVDIMM_INTEL_SECURITY_CMDMASK | NVDIMM_INTEL_FW_ACTIVATE_CMDMASK)
+
+#define NVDIMM_INTEL_DENY_CMDMASK \
+(NVDIMM_INTEL_SECURITY_CMDMASK | NVDIMM_INTEL_FW_ACTIVATE_CMDMASK)
 
 enum nfit_uuids {
 	/* for simplicity alias the uuid index with the family id */
@@ -91,6 +107,11 @@ enum nfit_uuids {
 	NFIT_DEV_DIMM_N_HPE2 = NVDIMM_FAMILY_HPE2,
 	NFIT_DEV_DIMM_N_MSFT = NVDIMM_FAMILY_MSFT,
 	NFIT_DEV_DIMM_N_HYPERV = NVDIMM_FAMILY_HYPERV,
+	/*
+	 * to_nfit_bus_uuid() expects to translate bus uuid family ids
+	 * to a UUID index using NVDIMM_FAMILY_MAX as an offset
+	 */
+	NFIT_BUS_INTEL = NVDIMM_FAMILY_MAX + NVDIMM_BUS_FAMILY_INTEL,
 	NFIT_SPA_VOLATILE,
 	NFIT_SPA_PM,
 	NFIT_SPA_DCR,
@@ -187,18 +208,17 @@ struct nfit_mem {
 	struct nvdimm *nvdimm;
 	struct acpi_nfit_memory_map *memdev_dcr;
 	struct acpi_nfit_memory_map *memdev_pmem;
-	struct acpi_nfit_memory_map *memdev_bdw;
 	struct acpi_nfit_control_region *dcr;
-	struct acpi_nfit_data_region *bdw;
 	struct acpi_nfit_system_address *spa_dcr;
-	struct acpi_nfit_system_address *spa_bdw;
 	struct acpi_nfit_interleave *idt_dcr;
-	struct acpi_nfit_interleave *idt_bdw;
 	struct kernfs_node *flags_attr;
 	struct nfit_flush *nfit_flush;
 	struct list_head list;
 	struct acpi_device *adev;
 	struct acpi_nfit_desc *acpi_desc;
+	enum nvdimm_fwa_state fwa_state;
+	enum nvdimm_fwa_result fwa_result;
+	int fwa_count;
 	char id[NFIT_DIMM_ID_LEN+1];
 	struct resource *flush_wpq;
 	unsigned long dsm_mask;
@@ -238,11 +258,15 @@ struct acpi_nfit_desc {
 	unsigned long scrub_flags;
 	unsigned long dimm_cmd_force_en;
 	unsigned long bus_cmd_force_en;
-	unsigned long bus_nfit_cmd_force_en;
+	unsigned long bus_dsm_mask;
+	unsigned long family_dsm_mask[NVDIMM_BUS_FAMILY_MAX + 1];
 	unsigned int platform_cap;
 	unsigned int scrub_tmo;
-	int (*blk_do_io)(struct nd_blk_region *ndbr, resource_size_t dpa,
-			void *iobuf, u64 len, int rw);
+	enum nvdimm_fwa_state fwa_state;
+	enum nvdimm_fwa_capability fwa_cap;
+	int fwa_count;
+	bool fwa_noidle;
+	bool fwa_nosuspend;
 };
 
 enum scrub_mode {
@@ -313,30 +337,6 @@ static inline struct acpi_nfit_desc *to_acpi_desc(
 	return container_of(nd_desc, struct acpi_nfit_desc, nd_desc);
 }
 
-#ifdef CONFIG_PROVE_LOCKING
-static inline void nfit_device_lock(struct device *dev)
-{
-	device_lock(dev);
-	mutex_lock(&dev->lockdep_mutex);
-}
-
-static inline void nfit_device_unlock(struct device *dev)
-{
-	mutex_unlock(&dev->lockdep_mutex);
-	device_unlock(dev);
-}
-#else
-static inline void nfit_device_lock(struct device *dev)
-{
-	device_lock(dev);
-}
-
-static inline void nfit_device_unlock(struct device *dev)
-{
-	device_unlock(dev);
-}
-#endif
-
 const guid_t *to_nfit_uuid(enum nfit_uuids id);
 int acpi_nfit_init(struct acpi_nfit_desc *acpi_desc, void *nfit, acpi_size sz);
 void acpi_nfit_shutdown(void *data);
@@ -345,4 +345,8 @@ void __acpi_nvdimm_notify(struct device *dev, u32 event);
 int acpi_nfit_ctl(struct nvdimm_bus_descriptor *nd_desc, struct nvdimm *nvdimm,
 		unsigned int cmd, void *buf, unsigned int buf_len, int *cmd_rc);
 void acpi_nfit_desc_init(struct acpi_nfit_desc *acpi_desc, struct device *dev);
+bool intel_fwa_supported(struct nvdimm_bus *nvdimm_bus);
+extern struct device_attribute dev_attr_firmware_activate_noidle;
+void nfit_intel_shutdown_status(struct nfit_mem *nfit_mem);
+
 #endif /* __NFIT_H__ */
diff --git a/drivers/acpi/nhlt.c b/drivers/acpi/nhlt.c
new file mode 100644
index 000000000000..dc1bd0df9228
--- /dev/null
+++ b/drivers/acpi/nhlt.c
@@ -0,0 +1,289 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright(c) 2023-2024 Intel Corporation
+ *
+ * Authors: Cezary Rojewski <cezary.rojewski@intel.com>
+ *          Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com>
+ */
+
+#define pr_fmt(fmt) "ACPI: NHLT: " fmt
+
+#include <linux/acpi.h>
+#include <linux/errno.h>
+#include <linux/export.h>
+#include <linux/minmax.h>
+#include <linux/printk.h>
+#include <linux/types.h>
+#include <acpi/nhlt.h>
+
+static struct acpi_table_nhlt *acpi_gbl_nhlt;
+
+static struct acpi_table_nhlt empty_nhlt = {
+	.header = {
+		.signature = ACPI_SIG_NHLT,
+	},
+};
+
+/**
+ * acpi_nhlt_get_gbl_table - Retrieve a pointer to the first NHLT table.
+ *
+ * If there is no NHLT in the system, acpi_gbl_nhlt will instead point to an
+ * empty table.
+ *
+ * Return: ACPI status code of the operation.
+ */
+acpi_status acpi_nhlt_get_gbl_table(void)
+{
+	acpi_status status;
+
+	status = acpi_get_table(ACPI_SIG_NHLT, 0, (struct acpi_table_header **)(&acpi_gbl_nhlt));
+	if (!acpi_gbl_nhlt)
+		acpi_gbl_nhlt = &empty_nhlt;
+	return status;
+}
+EXPORT_SYMBOL_GPL(acpi_nhlt_get_gbl_table);
+
+/**
+ * acpi_nhlt_put_gbl_table - Release the global NHLT table.
+ */
+void acpi_nhlt_put_gbl_table(void)
+{
+	acpi_put_table((struct acpi_table_header *)acpi_gbl_nhlt);
+}
+EXPORT_SYMBOL_GPL(acpi_nhlt_put_gbl_table);
+
+/**
+ * acpi_nhlt_endpoint_match - Verify if an endpoint matches criteria.
+ * @ep:			the endpoint to check.
+ * @link_type:		the hardware link type, e.g.: PDM or SSP.
+ * @dev_type:		the device type.
+ * @dir:		stream direction.
+ * @bus_id:		the ID of virtual bus hosting the endpoint.
+ *
+ * Either of @link_type, @dev_type, @dir or @bus_id may be set to a negative
+ * value to ignore the parameter when matching.
+ *
+ * Return: %true if endpoint matches specified criteria or %false otherwise.
+ */
+bool acpi_nhlt_endpoint_match(const struct acpi_nhlt_endpoint *ep,
+			      int link_type, int dev_type, int dir, int bus_id)
+{
+	return ep &&
+	       (link_type < 0 || ep->link_type == link_type) &&
+	       (dev_type < 0 || ep->device_type == dev_type) &&
+	       (bus_id < 0 || ep->virtual_bus_id == bus_id) &&
+	       (dir < 0 || ep->direction == dir);
+}
+EXPORT_SYMBOL_GPL(acpi_nhlt_endpoint_match);
+
+/**
+ * acpi_nhlt_tb_find_endpoint - Search a NHLT table for an endpoint.
+ * @tb:			the table to search.
+ * @link_type:		the hardware link type, e.g.: PDM or SSP.
+ * @dev_type:		the device type.
+ * @dir:		stream direction.
+ * @bus_id:		the ID of virtual bus hosting the endpoint.
+ *
+ * Either of @link_type, @dev_type, @dir or @bus_id may be set to a negative
+ * value to ignore the parameter during the search.
+ *
+ * Return: A pointer to endpoint matching the criteria, %NULL if not found or
+ * an ERR_PTR() otherwise.
+ */
+struct acpi_nhlt_endpoint *
+acpi_nhlt_tb_find_endpoint(const struct acpi_table_nhlt *tb,
+			   int link_type, int dev_type, int dir, int bus_id)
+{
+	struct acpi_nhlt_endpoint *ep;
+
+	for_each_nhlt_endpoint(tb, ep)
+		if (acpi_nhlt_endpoint_match(ep, link_type, dev_type, dir, bus_id))
+			return ep;
+	return NULL;
+}
+EXPORT_SYMBOL_GPL(acpi_nhlt_tb_find_endpoint);
+
+/**
+ * acpi_nhlt_find_endpoint - Search all NHLT tables for an endpoint.
+ * @link_type:		the hardware link type, e.g.: PDM or SSP.
+ * @dev_type:		the device type.
+ * @dir:		stream direction.
+ * @bus_id:		the ID of virtual bus hosting the endpoint.
+ *
+ * Either of @link_type, @dev_type, @dir or @bus_id may be set to a negative
+ * value to ignore the parameter during the search.
+ *
+ * Return: A pointer to endpoint matching the criteria, %NULL if not found or
+ * an ERR_PTR() otherwise.
+ */
+struct acpi_nhlt_endpoint *
+acpi_nhlt_find_endpoint(int link_type, int dev_type, int dir, int bus_id)
+{
+	/* TODO: Currently limited to table of index 0. */
+	return acpi_nhlt_tb_find_endpoint(acpi_gbl_nhlt, link_type, dev_type, dir, bus_id);
+}
+EXPORT_SYMBOL_GPL(acpi_nhlt_find_endpoint);
+
+/**
+ * acpi_nhlt_endpoint_find_fmtcfg - Search endpoint's formats configuration space
+ *                                  for a specific format.
+ * @ep:			the endpoint to search.
+ * @ch:			number of channels.
+ * @rate:		samples per second.
+ * @vbps:		valid bits per sample.
+ * @bps:		bits per sample.
+ *
+ * Return: A pointer to format matching the criteria, %NULL if not found or
+ * an ERR_PTR() otherwise.
+ */
+struct acpi_nhlt_format_config *
+acpi_nhlt_endpoint_find_fmtcfg(const struct acpi_nhlt_endpoint *ep,
+			       u16 ch, u32 rate, u16 vbps, u16 bps)
+{
+	struct acpi_nhlt_wave_formatext *wav;
+	struct acpi_nhlt_format_config *fmt;
+
+	for_each_nhlt_endpoint_fmtcfg(ep, fmt) {
+		wav = &fmt->format;
+
+		if (wav->valid_bits_per_sample == vbps &&
+		    wav->samples_per_sec == rate &&
+		    wav->bits_per_sample == bps &&
+		    wav->channel_count == ch)
+			return fmt;
+	}
+
+	return NULL;
+}
+EXPORT_SYMBOL_GPL(acpi_nhlt_endpoint_find_fmtcfg);
+
+/**
+ * acpi_nhlt_tb_find_fmtcfg - Search a NHLT table for a specific format.
+ * @tb:			the table to search.
+ * @link_type:		the hardware link type, e.g.: PDM or SSP.
+ * @dev_type:		the device type.
+ * @dir:		stream direction.
+ * @bus_id:		the ID of virtual bus hosting the endpoint.
+ *
+ * @ch:			number of channels.
+ * @rate:		samples per second.
+ * @vbps:		valid bits per sample.
+ * @bps:		bits per sample.
+ *
+ * Either of @link_type, @dev_type, @dir or @bus_id may be set to a negative
+ * value to ignore the parameter during the search.
+ *
+ * Return: A pointer to format matching the criteria, %NULL if not found or
+ * an ERR_PTR() otherwise.
+ */
+struct acpi_nhlt_format_config *
+acpi_nhlt_tb_find_fmtcfg(const struct acpi_table_nhlt *tb,
+			 int link_type, int dev_type, int dir, int bus_id,
+			 u16 ch, u32 rate, u16 vbps, u16 bps)
+{
+	struct acpi_nhlt_format_config *fmt;
+	struct acpi_nhlt_endpoint *ep;
+
+	for_each_nhlt_endpoint(tb, ep) {
+		if (!acpi_nhlt_endpoint_match(ep, link_type, dev_type, dir, bus_id))
+			continue;
+
+		fmt = acpi_nhlt_endpoint_find_fmtcfg(ep, ch, rate, vbps, bps);
+		if (fmt)
+			return fmt;
+	}
+
+	return NULL;
+}
+EXPORT_SYMBOL_GPL(acpi_nhlt_tb_find_fmtcfg);
+
+/**
+ * acpi_nhlt_find_fmtcfg - Search all NHLT tables for a specific format.
+ * @link_type:		the hardware link type, e.g.: PDM or SSP.
+ * @dev_type:		the device type.
+ * @dir:		stream direction.
+ * @bus_id:		the ID of virtual bus hosting the endpoint.
+ *
+ * @ch:			number of channels.
+ * @rate:		samples per second.
+ * @vbps:		valid bits per sample.
+ * @bps:		bits per sample.
+ *
+ * Either of @link_type, @dev_type, @dir or @bus_id may be set to a negative
+ * value to ignore the parameter during the search.
+ *
+ * Return: A pointer to format matching the criteria, %NULL if not found or
+ * an ERR_PTR() otherwise.
+ */
+struct acpi_nhlt_format_config *
+acpi_nhlt_find_fmtcfg(int link_type, int dev_type, int dir, int bus_id,
+		      u16 ch, u32 rate, u16 vbps, u16 bps)
+{
+	/* TODO: Currently limited to table of index 0. */
+	return acpi_nhlt_tb_find_fmtcfg(acpi_gbl_nhlt, link_type, dev_type, dir, bus_id,
+					ch, rate, vbps, bps);
+}
+EXPORT_SYMBOL_GPL(acpi_nhlt_find_fmtcfg);
+
+static bool acpi_nhlt_config_is_micdevice(struct acpi_nhlt_config *cfg)
+{
+	return cfg->capabilities_size >= sizeof(struct acpi_nhlt_micdevice_config);
+}
+
+static bool acpi_nhlt_config_is_vendor_micdevice(struct acpi_nhlt_config *cfg)
+{
+	struct acpi_nhlt_vendor_micdevice_config *devcfg = __acpi_nhlt_config_caps(cfg);
+
+	return cfg->capabilities_size >= sizeof(*devcfg) &&
+	       cfg->capabilities_size == struct_size(devcfg, mics, devcfg->mics_count);
+}
+
+/**
+ * acpi_nhlt_endpoint_mic_count - Retrieve number of digital microphones for a PDM endpoint.
+ * @ep:			the endpoint to return microphones count for.
+ *
+ * Return: A number of microphones or an error code if an invalid endpoint is provided.
+ */
+int acpi_nhlt_endpoint_mic_count(const struct acpi_nhlt_endpoint *ep)
+{
+	union acpi_nhlt_device_config *devcfg;
+	struct acpi_nhlt_format_config *fmt;
+	struct acpi_nhlt_config *cfg;
+	u16 max_ch = 0;
+
+	if (!ep || ep->link_type != ACPI_NHLT_LINKTYPE_PDM)
+		return -EINVAL;
+
+	/* Find max number of channels based on formats configuration. */
+	for_each_nhlt_endpoint_fmtcfg(ep, fmt)
+		max_ch = max(fmt->format.channel_count, max_ch);
+
+	cfg = __acpi_nhlt_endpoint_config(ep);
+	devcfg = __acpi_nhlt_config_caps(cfg);
+
+	/* If @ep is not a mic array, fallback to channels count. */
+	if (!acpi_nhlt_config_is_micdevice(cfg) ||
+	    devcfg->gen.config_type != ACPI_NHLT_CONFIGTYPE_MICARRAY)
+		return max_ch;
+
+	switch (devcfg->mic.array_type) {
+	case ACPI_NHLT_ARRAYTYPE_LINEAR2_SMALL:
+	case ACPI_NHLT_ARRAYTYPE_LINEAR2_BIG:
+		return 2;
+
+	case ACPI_NHLT_ARRAYTYPE_LINEAR4_GEO1:
+	case ACPI_NHLT_ARRAYTYPE_PLANAR4_LSHAPED:
+	case ACPI_NHLT_ARRAYTYPE_LINEAR4_GEO2:
+		return 4;
+
+	case ACPI_NHLT_ARRAYTYPE_VENDOR:
+		if (!acpi_nhlt_config_is_vendor_micdevice(cfg))
+			return -EINVAL;
+		return devcfg->vendor_mic.mics_count;
+
+	default:
+		pr_warn("undefined mic array type: %#x\n", devcfg->mic.array_type);
+		return max_ch;
+	}
+}
+EXPORT_SYMBOL_GPL(acpi_nhlt_endpoint_mic_count);
diff --git a/drivers/acpi/numa/Kconfig b/drivers/acpi/numa/Kconfig
index fcf2e556d69d..f33194d1e43f 100644
--- a/drivers/acpi/numa/Kconfig
+++ b/drivers/acpi/numa/Kconfig
@@ -1,9 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 config ACPI_NUMA
-	bool "NUMA support"
-	depends on NUMA
-	depends on (X86 || IA64 || ARM64)
-	default y if IA64 || ARM64
+	def_bool NUMA && !X86
 
 config ACPI_HMAT
 	bool "ACPI Heterogeneous Memory Attribute Table Support"
diff --git a/drivers/acpi/numa/hmat.c b/drivers/acpi/numa/hmat.c
index 2c32cfb72370..77a81627aaef 100644
--- a/drivers/acpi/numa/hmat.c
+++ b/drivers/acpi/numa/hmat.c
@@ -9,7 +9,6 @@
  */
 
 #define pr_fmt(fmt) "acpi/hmat: " fmt
-#define dev_fmt(fmt) "acpi/hmat: " fmt
 
 #include <linux/acpi.h>
 #include <linux/bitops.h>
@@ -24,8 +23,16 @@
 #include <linux/mutex.h>
 #include <linux/node.h>
 #include <linux/sysfs.h>
+#include <linux/dax.h>
+#include <linux/memory-tiers.h>
 
 static u8 hmat_revision;
+static int hmat_disable __initdata;
+
+void __init disable_hmat(void)
+{
+	hmat_disable = 1;
+}
 
 static LIST_HEAD(targets);
 static LIST_HEAD(initiators);
@@ -51,20 +58,28 @@ struct target_cache {
 	struct node_cache_attrs cache_attrs;
 };
 
+enum {
+	NODE_ACCESS_CLASS_GENPORT_SINK_LOCAL = ACCESS_COORDINATE_MAX,
+	NODE_ACCESS_CLASS_GENPORT_SINK_CPU,
+	NODE_ACCESS_CLASS_MAX,
+};
+
 struct memory_target {
 	struct list_head node;
 	unsigned int memory_pxm;
 	unsigned int processor_pxm;
 	struct resource memregions;
-	struct node_hmem_attrs hmem_attrs;
+	struct access_coordinate coord[NODE_ACCESS_CLASS_MAX];
 	struct list_head caches;
 	struct node_cache_attrs cache_attrs;
+	u8 gen_port_device_handle[ACPI_SRAT_DEVICE_HANDLE_SIZE];
 	bool registered;
 };
 
 struct memory_initiator {
 	struct list_head node;
 	unsigned int processor_pxm;
+	bool has_cpu;
 };
 
 struct memory_locality {
@@ -92,6 +107,90 @@ static struct memory_target *find_mem_target(unsigned int mem_pxm)
 	return NULL;
 }
 
+/**
+ * hmat_get_extended_linear_cache_size - Retrieve the extended linear cache size
+ * @backing_res: resource from the backing media
+ * @nid: node id for the memory region
+ * @cache_size: (Output) size of extended linear cache.
+ *
+ * Return: 0 on success. Errno on failure.
+ *
+ */
+int hmat_get_extended_linear_cache_size(struct resource *backing_res, int nid,
+					resource_size_t *cache_size)
+{
+	unsigned int pxm = node_to_pxm(nid);
+	struct memory_target *target;
+	struct target_cache *tcache;
+	struct resource *res;
+
+	target = find_mem_target(pxm);
+	if (!target)
+		return -ENOENT;
+
+	list_for_each_entry(tcache, &target->caches, node) {
+		if (tcache->cache_attrs.address_mode !=
+				NODE_CACHE_ADDR_MODE_EXTENDED_LINEAR)
+			continue;
+
+		res = &target->memregions;
+		if (!resource_contains(res, backing_res))
+			continue;
+
+		*cache_size = tcache->cache_attrs.size;
+		return 0;
+	}
+
+	*cache_size = 0;
+	return 0;
+}
+EXPORT_SYMBOL_NS_GPL(hmat_get_extended_linear_cache_size, "CXL");
+
+static struct memory_target *acpi_find_genport_target(u32 uid)
+{
+	struct memory_target *target;
+	u32 target_uid;
+	u8 *uid_ptr;
+
+	list_for_each_entry(target, &targets, node) {
+		uid_ptr = target->gen_port_device_handle + 8;
+		target_uid = *(u32 *)uid_ptr;
+		if (uid == target_uid)
+			return target;
+	}
+
+	return NULL;
+}
+
+/**
+ * acpi_get_genport_coordinates - Retrieve the access coordinates for a generic port
+ * @uid: ACPI unique id
+ * @coord: The access coordinates written back out for the generic port.
+ *	   Expect 2 levels array.
+ *
+ * Return: 0 on success. Errno on failure.
+ *
+ * Only supports device handles that are ACPI. Assume ACPI0016 HID for CXL.
+ */
+int acpi_get_genport_coordinates(u32 uid,
+				 struct access_coordinate *coord)
+{
+	struct memory_target *target;
+
+	guard(mutex)(&target_lock);
+	target = acpi_find_genport_target(uid);
+	if (!target)
+		return -ENOENT;
+
+	coord[ACCESS_COORDINATE_LOCAL] =
+		target->coord[NODE_ACCESS_CLASS_GENPORT_SINK_LOCAL];
+	coord[ACCESS_COORDINATE_CPU] =
+		target->coord[NODE_ACCESS_CLASS_GENPORT_SINK_CPU];
+
+	return 0;
+}
+EXPORT_SYMBOL_NS_GPL(acpi_get_genport_coordinates, "CXL");
+
 static __init void alloc_memory_initiator(unsigned int cpu_pxm)
 {
 	struct memory_initiator *initiator;
@@ -108,11 +207,11 @@ static __init void alloc_memory_initiator(unsigned int cpu_pxm)
 		return;
 
 	initiator->processor_pxm = cpu_pxm;
+	initiator->has_cpu = node_state(pxm_to_node(cpu_pxm), N_CPU);
 	list_add_tail(&initiator->node, &initiators);
 }
 
-static __init void alloc_memory_target(unsigned int mem_pxm,
-		resource_size_t start, resource_size_t len)
+static __init struct memory_target *alloc_target(unsigned int mem_pxm)
 {
 	struct memory_target *target;
 
@@ -120,7 +219,7 @@ static __init void alloc_memory_target(unsigned int mem_pxm,
 	if (!target) {
 		target = kzalloc(sizeof(*target), GFP_KERNEL);
 		if (!target)
-			return;
+			return NULL;
 		target->memory_pxm = mem_pxm;
 		target->processor_pxm = PXM_INVAL;
 		target->memregions = (struct resource) {
@@ -133,6 +232,19 @@ static __init void alloc_memory_target(unsigned int mem_pxm,
 		INIT_LIST_HEAD(&target->caches);
 	}
 
+	return target;
+}
+
+static __init void alloc_memory_target(unsigned int mem_pxm,
+				       resource_size_t start,
+				       resource_size_t len)
+{
+	struct memory_target *target;
+
+	target = alloc_target(mem_pxm);
+	if (!target)
+		return;
+
 	/*
 	 * There are potentially multiple ranges per PXM, so record each
 	 * in the per-target memregions resource tree.
@@ -143,6 +255,18 @@ static __init void alloc_memory_target(unsigned int mem_pxm,
 				start, start + len, mem_pxm);
 }
 
+static __init void alloc_genport_target(unsigned int mem_pxm, u8 *handle)
+{
+	struct memory_target *target;
+
+	target = alloc_target(mem_pxm);
+	if (!target)
+		return;
+
+	memcpy(target->gen_port_device_handle, handle,
+	       ACPI_SRAT_DEVICE_HANDLE_SIZE);
+}
+
 static __init const char *hmat_data_type(u8 type)
 {
 	switch (type) {
@@ -215,28 +339,28 @@ static u32 hmat_normalize(u16 entry, u64 base, u8 type)
 }
 
 static void hmat_update_target_access(struct memory_target *target,
-					     u8 type, u32 value)
+				      u8 type, u32 value, int access)
 {
 	switch (type) {
 	case ACPI_HMAT_ACCESS_LATENCY:
-		target->hmem_attrs.read_latency = value;
-		target->hmem_attrs.write_latency = value;
+		target->coord[access].read_latency = value;
+		target->coord[access].write_latency = value;
 		break;
 	case ACPI_HMAT_READ_LATENCY:
-		target->hmem_attrs.read_latency = value;
+		target->coord[access].read_latency = value;
 		break;
 	case ACPI_HMAT_WRITE_LATENCY:
-		target->hmem_attrs.write_latency = value;
+		target->coord[access].write_latency = value;
 		break;
 	case ACPI_HMAT_ACCESS_BANDWIDTH:
-		target->hmem_attrs.read_bandwidth = value;
-		target->hmem_attrs.write_bandwidth = value;
+		target->coord[access].read_bandwidth = value;
+		target->coord[access].write_bandwidth = value;
 		break;
 	case ACPI_HMAT_READ_BANDWIDTH:
-		target->hmem_attrs.read_bandwidth = value;
+		target->coord[access].read_bandwidth = value;
 		break;
 	case ACPI_HMAT_WRITE_BANDWIDTH:
-		target->hmem_attrs.write_bandwidth = value;
+		target->coord[access].write_bandwidth = value;
 		break;
 	default:
 		break;
@@ -282,18 +406,35 @@ static __init void hmat_add_locality(struct acpi_hmat_locality *hmat_loc)
 	}
 }
 
+static __init void hmat_update_target(unsigned int tgt_pxm, unsigned int init_pxm,
+				      u8 mem_hier, u8 type, u32 value)
+{
+	struct memory_target *target = find_mem_target(tgt_pxm);
+
+	if (mem_hier != ACPI_HMAT_MEMORY)
+		return;
+
+	if (target && target->processor_pxm == init_pxm) {
+		hmat_update_target_access(target, type, value,
+					  ACCESS_COORDINATE_LOCAL);
+		/* If the node has a CPU, update access ACCESS_COORDINATE_CPU */
+		if (node_state(pxm_to_node(init_pxm), N_CPU))
+			hmat_update_target_access(target, type, value,
+						  ACCESS_COORDINATE_CPU);
+	}
+}
+
 static __init int hmat_parse_locality(union acpi_subtable_headers *header,
 				      const unsigned long end)
 {
 	struct acpi_hmat_locality *hmat_loc = (void *)header;
-	struct memory_target *target;
 	unsigned int init, targ, total_size, ipds, tpds;
 	u32 *inits, *targs, value;
 	u16 *entries;
 	u8 type, mem_hier;
 
 	if (hmat_loc->header.length < sizeof(*hmat_loc)) {
-		pr_notice("HMAT: Unexpected locality header length: %u\n",
+		pr_notice("Unexpected locality header length: %u\n",
 			 hmat_loc->header.length);
 		return -EINVAL;
 	}
@@ -305,14 +446,14 @@ static __init int hmat_parse_locality(union acpi_subtable_headers *header,
 	total_size = sizeof(*hmat_loc) + sizeof(*entries) * ipds * tpds +
 		     sizeof(*inits) * ipds + sizeof(*targs) * tpds;
 	if (hmat_loc->header.length < total_size) {
-		pr_notice("HMAT: Unexpected locality header length:%u, minimum required:%u\n",
+		pr_notice("Unexpected locality header length:%u, minimum required:%u\n",
 			 hmat_loc->header.length, total_size);
 		return -EINVAL;
 	}
 
-	pr_info("HMAT: Locality: Flags:%02x Type:%s Initiator Domains:%u Target Domains:%u Base:%lld\n",
-		hmat_loc->flags, hmat_data_type(type), ipds, tpds,
-		hmat_loc->entry_base_unit);
+	pr_debug("Locality: Flags:%02x Type:%s Initiator Domains:%u Target Domains:%u Base:%lld\n",
+		 hmat_loc->flags, hmat_data_type(type), ipds, tpds,
+		 hmat_loc->entry_base_unit);
 
 	inits = (u32 *)(hmat_loc + 1);
 	targs = inits + ipds;
@@ -323,15 +464,12 @@ static __init int hmat_parse_locality(union acpi_subtable_headers *header,
 			value = hmat_normalize(entries[init * tpds + targ],
 					       hmat_loc->entry_base_unit,
 					       type);
-			pr_info("  Initiator-Target[%u-%u]:%u%s\n",
-				inits[init], targs[targ], value,
-				hmat_data_type_suffix(type));
-
-			if (mem_hier == ACPI_HMAT_MEMORY) {
-				target = find_mem_target(targs[targ]);
-				if (target && target->processor_pxm == inits[init])
-					hmat_update_target_access(target, type, value);
-			}
+			pr_debug("  Initiator-Target[%u-%u]:%u%s\n",
+				 inits[init], targs[targ], value,
+				 hmat_data_type_suffix(type));
+
+			hmat_update_target(targs[targ], inits[init],
+					   mem_hier, type, value);
 		}
 	}
 
@@ -350,15 +488,15 @@ static __init int hmat_parse_cache(union acpi_subtable_headers *header,
 	u32 attrs;
 
 	if (cache->header.length < sizeof(*cache)) {
-		pr_notice("HMAT: Unexpected cache header length: %u\n",
+		pr_notice("Unexpected cache header length: %u\n",
 			 cache->header.length);
 		return -EINVAL;
 	}
 
 	attrs = cache->cache_attributes;
-	pr_info("HMAT: Cache: Domain:%u Size:%llu Attrs:%08x SMBIOS Handles:%d\n",
-		cache->memory_PD, cache->cache_size, attrs,
-		cache->number_of_SMBIOShandles);
+	pr_debug("Cache: Domain:%u Size:%llu Attrs:%08x SMBIOS Handles:%d\n",
+		 cache->memory_PD, cache->cache_size, attrs,
+		 cache->number_of_SMBIOShandles);
 
 	target = find_mem_target(cache->memory_PD);
 	if (!target)
@@ -377,6 +515,11 @@ static __init int hmat_parse_cache(union acpi_subtable_headers *header,
 	switch ((attrs & ACPI_HMAT_CACHE_ASSOCIATIVITY) >> 8) {
 	case ACPI_HMAT_CA_DIRECT_MAPPED:
 		tcache->cache_attrs.indexing = NODE_CACHE_DIRECT_MAP;
+		/* Extended Linear mode is only valid if cache is direct mapped */
+		if (cache->address_mode == ACPI_HMAT_CACHE_MODE_EXTENDED_LINEAR) {
+			tcache->cache_attrs.address_mode =
+				NODE_CACHE_ADDR_MODE_EXTENDED_LINEAR;
+		}
 		break;
 	case ACPI_HMAT_CA_COMPLEX_CACHE_INDEXING:
 		tcache->cache_attrs.indexing = NODE_CACHE_INDEXED;
@@ -411,23 +554,24 @@ static int __init hmat_parse_proximity_domain(union acpi_subtable_headers *heade
 	struct memory_target *target = NULL;
 
 	if (p->header.length != sizeof(*p)) {
-		pr_notice("HMAT: Unexpected address range header length: %u\n",
+		pr_notice("Unexpected address range header length: %u\n",
 			 p->header.length);
 		return -EINVAL;
 	}
 
 	if (hmat_revision == 1)
-		pr_info("HMAT: Memory (%#llx length %#llx) Flags:%04x Processor Domain:%u Memory Domain:%u\n",
-			p->reserved3, p->reserved4, p->flags, p->processor_PD,
-			p->memory_PD);
+		pr_debug("Memory (%#llx length %#llx) Flags:%04x Processor Domain:%u Memory Domain:%u\n",
+			 p->reserved3, p->reserved4, p->flags, p->processor_PD,
+			 p->memory_PD);
 	else
-		pr_info("HMAT: Memory Flags:%04x Processor Domain:%u Memory Domain:%u\n",
+		pr_info("Memory Flags:%04x Processor Domain:%u Memory Domain:%u\n",
 			p->flags, p->processor_PD, p->memory_PD);
 
-	if (p->flags & ACPI_HMAT_MEMORY_PD_VALID && hmat_revision == 1) {
+	if ((hmat_revision == 1 && p->flags & ACPI_HMAT_MEMORY_PD_VALID) ||
+	    hmat_revision > 1) {
 		target = find_mem_target(p->memory_PD);
 		if (!target) {
-			pr_debug("HMAT: Memory Domain missing from SRAT\n");
+			pr_debug("Memory Domain missing from SRAT\n");
 			return -EINVAL;
 		}
 	}
@@ -435,7 +579,7 @@ static int __init hmat_parse_proximity_domain(union acpi_subtable_headers *heade
 		int p_node = pxm_to_node(p->processor_PD);
 
 		if (p_node == NUMA_NO_NODE) {
-			pr_debug("HMAT: Invalid Processor Domain\n");
+			pr_debug("Invalid Processor Domain\n");
 			return -EINVAL;
 		}
 		target->processor_pxm = p->processor_PD;
@@ -477,6 +621,27 @@ static __init int srat_parse_mem_affinity(union acpi_subtable_headers *header,
 	return 0;
 }
 
+static __init int srat_parse_genport_affinity(union acpi_subtable_headers *header,
+					      const unsigned long end)
+{
+	struct acpi_srat_generic_affinity *ga = (void *)header;
+
+	if (!ga)
+		return -EINVAL;
+
+	if (!(ga->flags & ACPI_SRAT_GENERIC_AFFINITY_ENABLED))
+		return 0;
+
+	/* Skip PCI device_handle for now */
+	if (ga->device_handle_type != 0)
+		return 0;
+
+	alloc_genport_target(ga->proximity_domain,
+			     (u8 *)ga->device_handle);
+
+	return 0;
+}
+
 static u32 hmat_initiator_perf(struct memory_target *target,
 			       struct memory_initiator *initiator,
 			       struct acpi_hmat_locality *hmat_loc)
@@ -544,40 +709,59 @@ static bool hmat_update_best(u8 type, u32 value, u32 *best)
 	return updated;
 }
 
-static int initiator_cmp(void *priv, struct list_head *a, struct list_head *b)
+static int initiator_cmp(void *priv, const struct list_head *a,
+			 const struct list_head *b)
 {
 	struct memory_initiator *ia;
 	struct memory_initiator *ib;
-	unsigned long *p_nodes = priv;
 
 	ia = list_entry(a, struct memory_initiator, node);
 	ib = list_entry(b, struct memory_initiator, node);
 
-	set_bit(ia->processor_pxm, p_nodes);
-	set_bit(ib->processor_pxm, p_nodes);
-
 	return ia->processor_pxm - ib->processor_pxm;
 }
 
-static void hmat_register_target_initiators(struct memory_target *target)
+static int initiators_to_nodemask(unsigned long *p_nodes)
 {
-	static DECLARE_BITMAP(p_nodes, MAX_NUMNODES);
 	struct memory_initiator *initiator;
-	unsigned int mem_nid, cpu_nid;
+
+	if (list_empty(&initiators))
+		return -ENXIO;
+
+	list_for_each_entry(initiator, &initiators, node)
+		set_bit(initiator->processor_pxm, p_nodes);
+
+	return 0;
+}
+
+static void hmat_update_target_attrs(struct memory_target *target,
+				     unsigned long *p_nodes, int access)
+{
+	struct memory_initiator *initiator;
+	unsigned int cpu_nid;
 	struct memory_locality *loc = NULL;
 	u32 best = 0;
 	int i;
 
-	mem_nid = pxm_to_node(target->memory_pxm);
+	/* Don't update for generic port if there's no device handle */
+	if ((access == NODE_ACCESS_CLASS_GENPORT_SINK_LOCAL ||
+	     access == NODE_ACCESS_CLASS_GENPORT_SINK_CPU) &&
+	    !(*(u16 *)target->gen_port_device_handle))
+		return;
+
+	bitmap_zero(p_nodes, MAX_NUMNODES);
 	/*
-	 * If the Address Range Structure provides a local processor pxm, link
+	 * If the Address Range Structure provides a local processor pxm, set
 	 * only that one. Otherwise, find the best performance attributes and
-	 * register all initiators that match.
+	 * collect all initiators that match.
 	 */
 	if (target->processor_pxm != PXM_INVAL) {
 		cpu_nid = pxm_to_node(target->processor_pxm);
-		register_memory_node_under_compute_node(mem_nid, cpu_nid, 0);
-		return;
+		if (access == ACCESS_COORDINATE_LOCAL ||
+		    node_state(cpu_nid, N_CPU)) {
+			set_bit(target->processor_pxm, p_nodes);
+			return;
+		}
 	}
 
 	if (list_empty(&localities))
@@ -589,8 +773,10 @@ static void hmat_register_target_initiators(struct memory_target *target)
 	 * We'll also use the sorting to prime the candidate nodes with known
 	 * initiators.
 	 */
-	bitmap_zero(p_nodes, MAX_NUMNODES);
-	list_sort(p_nodes, &initiators, initiator_cmp);
+	list_sort(NULL, &initiators, initiator_cmp);
+	if (initiators_to_nodemask(p_nodes) < 0)
+		return;
+
 	for (i = WRITE_LATENCY; i <= READ_BANDWIDTH; i++) {
 		loc = localities_types[i];
 		if (!loc)
@@ -600,6 +786,12 @@ static void hmat_register_target_initiators(struct memory_target *target)
 		list_for_each_entry(initiator, &initiators, node) {
 			u32 value;
 
+			if ((access == ACCESS_COORDINATE_CPU ||
+			     access == NODE_ACCESS_CLASS_GENPORT_SINK_CPU) &&
+			    !initiator->has_cpu) {
+				clear_bit(initiator->processor_pxm, p_nodes);
+				continue;
+			}
 			if (!test_bit(initiator->processor_pxm, p_nodes))
 				continue;
 
@@ -610,15 +802,45 @@ static void hmat_register_target_initiators(struct memory_target *target)
 				clear_bit(initiator->processor_pxm, p_nodes);
 		}
 		if (best)
-			hmat_update_target_access(target, loc->hmat_loc->data_type, best);
+			hmat_update_target_access(target, loc->hmat_loc->data_type, best, access);
 	}
+}
 
+static void __hmat_register_target_initiators(struct memory_target *target,
+					      unsigned long *p_nodes,
+					      int access)
+{
+	unsigned int mem_nid, cpu_nid;
+	int i;
+
+	mem_nid = pxm_to_node(target->memory_pxm);
+	hmat_update_target_attrs(target, p_nodes, access);
 	for_each_set_bit(i, p_nodes, MAX_NUMNODES) {
 		cpu_nid = pxm_to_node(i);
-		register_memory_node_under_compute_node(mem_nid, cpu_nid, 0);
+		register_memory_node_under_compute_node(mem_nid, cpu_nid, access);
 	}
 }
 
+static void hmat_update_generic_target(struct memory_target *target)
+{
+	static DECLARE_BITMAP(p_nodes, MAX_NUMNODES);
+
+	hmat_update_target_attrs(target, p_nodes,
+				 NODE_ACCESS_CLASS_GENPORT_SINK_LOCAL);
+	hmat_update_target_attrs(target, p_nodes,
+				 NODE_ACCESS_CLASS_GENPORT_SINK_CPU);
+}
+
+static void hmat_register_target_initiators(struct memory_target *target)
+{
+	static DECLARE_BITMAP(p_nodes, MAX_NUMNODES);
+
+	__hmat_register_target_initiators(target, p_nodes,
+					  ACCESS_COORDINATE_LOCAL);
+	__hmat_register_target_initiators(target, p_nodes,
+					  ACCESS_COORDINATE_CPU);
+}
+
 static void hmat_register_target_cache(struct memory_target *target)
 {
 	unsigned mem_nid = pxm_to_node(target->memory_pxm);
@@ -628,91 +850,56 @@ static void hmat_register_target_cache(struct memory_target *target)
 		node_add_cache(mem_nid, &tcache->cache_attrs);
 }
 
-static void hmat_register_target_perf(struct memory_target *target)
+static void hmat_register_target_perf(struct memory_target *target, int access)
 {
 	unsigned mem_nid = pxm_to_node(target->memory_pxm);
-	node_set_perf_attrs(mem_nid, &target->hmem_attrs, 0);
+	node_set_perf_attrs(mem_nid, &target->coord[access], access);
 }
 
-static void hmat_register_target_device(struct memory_target *target,
-		struct resource *r)
+static void hmat_register_target_devices(struct memory_target *target)
 {
-	/* define a clean / non-busy resource for the platform device */
-	struct resource res = {
-		.start = r->start,
-		.end = r->end,
-		.flags = IORESOURCE_MEM,
-	};
-	struct platform_device *pdev;
-	struct memregion_info info;
-	int rc, id;
-
-	rc = region_intersects(res.start, resource_size(&res), IORESOURCE_MEM,
-			IORES_DESC_SOFT_RESERVED);
-	if (rc != REGION_INTERSECTS)
-		return;
+	struct resource *res;
 
-	id = memregion_alloc(GFP_KERNEL);
-	if (id < 0) {
-		pr_err("memregion allocation failure for %pr\n", &res);
+	/*
+	 * Do not bother creating devices if no driver is available to
+	 * consume them.
+	 */
+	if (!IS_ENABLED(CONFIG_DEV_DAX_HMEM))
 		return;
-	}
 
-	pdev = platform_device_alloc("hmem", id);
-	if (!pdev) {
-		pr_err("hmem device allocation failure for %pr\n", &res);
-		goto out_pdev;
-	}
-
-	pdev->dev.numa_node = acpi_map_pxm_to_online_node(target->memory_pxm);
-	info = (struct memregion_info) {
-		.target_node = acpi_map_pxm_to_node(target->memory_pxm),
-	};
-	rc = platform_device_add_data(pdev, &info, sizeof(info));
-	if (rc < 0) {
-		pr_err("hmem memregion_info allocation failure for %pr\n", &res);
-		goto out_pdev;
-	}
+	for (res = target->memregions.child; res; res = res->sibling) {
+		int target_nid = pxm_to_node(target->memory_pxm);
 
-	rc = platform_device_add_resources(pdev, &res, 1);
-	if (rc < 0) {
-		pr_err("hmem resource allocation failure for %pr\n", &res);
-		goto out_resource;
+		hmem_register_resource(target_nid, res);
 	}
-
-	rc = platform_device_add(pdev);
-	if (rc < 0) {
-		dev_err(&pdev->dev, "device add failed for %pr\n", &res);
-		goto out_resource;
-	}
-
-	return;
-
-out_resource:
-	put_device(&pdev->dev);
-out_pdev:
-	memregion_free(id);
 }
 
-static void hmat_register_target_devices(struct memory_target *target)
+static void hmat_hotplug_target(struct memory_target *target)
 {
-	struct resource *res;
+	int nid = pxm_to_node(target->memory_pxm);
 
 	/*
-	 * Do not bother creating devices if no driver is available to
-	 * consume them.
+	 * Skip offline nodes. This can happen when memory marked EFI_MEMORY_SP,
+	 * "specific purpose", is applied to all the memory in a proximity
+	 * domain leading to * the node being marked offline / unplugged, or if
+	 * memory-only "hotplug" node is offline.
 	 */
-	if (!IS_ENABLED(CONFIG_DEV_DAX_HMEM))
+	if (nid == NUMA_NO_NODE || !node_online(nid))
+		return;
+
+	guard(mutex)(&target_lock);
+	if (target->registered)
 		return;
 
-	for (res = target->memregions.child; res; res = res->sibling)
-		hmat_register_target_device(target, res);
+	hmat_register_target_initiators(target);
+	hmat_register_target_cache(target);
+	hmat_register_target_perf(target, ACCESS_COORDINATE_LOCAL);
+	hmat_register_target_perf(target, ACCESS_COORDINATE_CPU);
+	target->registered = true;
 }
 
 static void hmat_register_target(struct memory_target *target)
 {
-	int nid = pxm_to_node(target->memory_pxm);
-
 	/*
 	 * Devices may belong to either an offline or online
 	 * node, so unconditionally add them.
@@ -720,23 +907,18 @@ static void hmat_register_target(struct memory_target *target)
 	hmat_register_target_devices(target);
 
 	/*
-	 * Skip offline nodes. This can happen when memory
-	 * marked EFI_MEMORY_SP, "specific purpose", is applied
-	 * to all the memory in a promixity domain leading to
-	 * the node being marked offline / unplugged, or if
-	 * memory-only "hotplug" node is offline.
+	 * Register generic port perf numbers. The nid may not be
+	 * initialized and is still NUMA_NO_NODE.
 	 */
-	if (nid == NUMA_NO_NODE || !node_online(nid))
-		return;
-
-	mutex_lock(&target_lock);
-	if (!target->registered) {
-		hmat_register_target_initiators(target);
-		hmat_register_target_cache(target);
-		hmat_register_target_perf(target);
-		target->registered = true;
+	scoped_guard(mutex, &target_lock) {
+		if (*(u16 *)target->gen_port_device_handle) {
+			hmat_update_generic_target(target);
+			target->registered = true;
+			return;
+		}
 	}
-	mutex_unlock(&target_lock);
+
+	hmat_hotplug_target(target);
 }
 
 static void hmat_register_targets(void)
@@ -751,10 +933,10 @@ static int hmat_callback(struct notifier_block *self,
 			 unsigned long action, void *arg)
 {
 	struct memory_target *target;
-	struct memory_notify *mnb = arg;
-	int pxm, nid = mnb->status_change_nid;
+	struct node_notify *nn = arg;
+	int pxm, nid = nn->nid;
 
-	if (nid == NUMA_NO_NODE || action != MEM_ONLINE)
+	if (action != NODE_ADDED_FIRST_MEMORY)
 		return NOTIFY_OK;
 
 	pxm = node_to_pxm(nid);
@@ -762,13 +944,60 @@ static int hmat_callback(struct notifier_block *self,
 	if (!target)
 		return NOTIFY_OK;
 
-	hmat_register_target(target);
+	hmat_hotplug_target(target);
 	return NOTIFY_OK;
 }
 
-static struct notifier_block hmat_callback_nb = {
-	.notifier_call = hmat_callback,
-	.priority = 2,
+static int __init hmat_set_default_dram_perf(void)
+{
+	int rc;
+	int nid, pxm;
+	struct memory_target *target;
+	struct access_coordinate *attrs;
+
+	for_each_node_mask(nid, default_dram_nodes) {
+		pxm = node_to_pxm(nid);
+		target = find_mem_target(pxm);
+		if (!target)
+			continue;
+		attrs = &target->coord[ACCESS_COORDINATE_CPU];
+		rc = mt_set_default_dram_perf(nid, attrs, "ACPI HMAT");
+		if (rc)
+			return rc;
+	}
+
+	return 0;
+}
+
+static int hmat_calculate_adistance(struct notifier_block *self,
+				    unsigned long nid, void *data)
+{
+	static DECLARE_BITMAP(p_nodes, MAX_NUMNODES);
+	struct memory_target *target;
+	struct access_coordinate *perf;
+	int *adist = data;
+	int pxm;
+
+	pxm = node_to_pxm(nid);
+	target = find_mem_target(pxm);
+	if (!target)
+		return NOTIFY_OK;
+
+	mutex_lock(&target_lock);
+	hmat_update_target_attrs(target, p_nodes, ACCESS_COORDINATE_CPU);
+	mutex_unlock(&target_lock);
+
+	perf = &target->coord[ACCESS_COORDINATE_CPU];
+
+	if (mt_perf_to_adistance(perf, adist))
+		return NOTIFY_OK;
+
+	return NOTIFY_STOP;
+}
+
+static struct notifier_block hmat_adist_nb __meminitdata = {
+	.notifier_call = hmat_calculate_adistance,
+	.priority = 100,
 };
 
 static __init void hmat_free_structures(void)
@@ -814,7 +1043,7 @@ static __init int hmat_init(void)
 	enum acpi_hmat_type i;
 	acpi_status status;
 
-	if (srat_disabled())
+	if (srat_disabled() || hmat_disable)
 		return 0;
 
 	status = acpi_get_table(ACPI_SIG_SRAT, 0, &tbl);
@@ -826,6 +1055,13 @@ static __init int hmat_init(void)
 				ACPI_SRAT_TYPE_MEMORY_AFFINITY,
 				srat_parse_mem_affinity, 0) < 0)
 		goto out_put;
+
+	if (acpi_table_parse_entries(ACPI_SIG_SRAT,
+				     sizeof(struct acpi_table_srat),
+				     ACPI_SRAT_TYPE_GENERIC_PORT_AFFINITY,
+				     srat_parse_genport_affinity, 0) < 0)
+		goto out_put;
+
 	acpi_put_table(tbl);
 
 	status = acpi_get_table(ACPI_SIG_HMAT, 0, &tbl);
@@ -838,7 +1074,7 @@ static __init int hmat_init(void)
 	case 2:
 		break;
 	default:
-		pr_notice("Ignoring HMAT: Unknown revision:%d\n", hmat_revision);
+		pr_notice("Ignoring: Unknown revision:%d\n", hmat_revision);
 		goto out_put;
 	}
 
@@ -846,18 +1082,23 @@ static __init int hmat_init(void)
 		if (acpi_table_parse_entries(ACPI_SIG_HMAT,
 					     sizeof(struct acpi_table_hmat), i,
 					     hmat_parse_subtable, 0) < 0) {
-			pr_notice("Ignoring HMAT: Invalid table");
+			pr_notice("Ignoring: Invalid table");
 			goto out_put;
 		}
 	}
 	hmat_register_targets();
 
 	/* Keep the table and structures if the notifier may use them */
-	if (!register_hotmemory_notifier(&hmat_callback_nb))
-		return 0;
+	if (hotplug_node_notifier(hmat_callback, HMAT_CALLBACK_PRI))
+		goto out_put;
+
+	if (!hmat_set_default_dram_perf())
+		register_mt_adistance_algorithm(&hmat_adist_nb);
+
+	return 0;
 out_put:
 	hmat_free_structures();
 	acpi_put_table(tbl);
 	return 0;
 }
-device_initcall(hmat_init);
+subsys_initcall(hmat_init);
diff --git a/drivers/acpi/numa/srat.c b/drivers/acpi/numa/srat.c
index 47b4969d9b93..aa87ee1583a4 100644
--- a/drivers/acpi/numa/srat.c
+++ b/drivers/acpi/numa/srat.c
@@ -14,9 +14,12 @@
 #include <linux/errno.h>
 #include <linux/acpi.h>
 #include <linux/memblock.h>
+#include <linux/memory.h>
 #include <linux/numa.h>
 #include <linux/nodemask.h>
 #include <linux/topology.h>
+#include <linux/numa_memblks.h>
+#include <linux/string_choices.h>
 
 static nodemask_t nodes_found_map = NODE_MASK_NONE;
 
@@ -27,14 +30,22 @@ static int node_to_pxm_map[MAX_NUMNODES]
 			= { [0 ... MAX_NUMNODES - 1] = PXM_INVAL };
 
 unsigned char acpi_srat_revision __initdata;
-int acpi_numa __initdata;
+static int acpi_numa __initdata;
+
+static int last_real_pxm;
+
+void __init disable_srat(void)
+{
+	acpi_numa = -1;
+}
 
 int pxm_to_node(int pxm)
 {
-	if (pxm < 0)
+	if (pxm < 0 || pxm >= MAX_PXM_DOMAINS || numa_off)
 		return NUMA_NO_NODE;
 	return pxm_to_node_map[pxm];
 }
+EXPORT_SYMBOL(pxm_to_node);
 
 int node_to_pxm(int node)
 {
@@ -42,6 +53,7 @@ int node_to_pxm(int node)
 		return PXM_INVAL;
 	return node_to_pxm_map[node];
 }
+EXPORT_SYMBOL_GPL(node_to_pxm);
 
 static void __acpi_map_pxm_to_node(int pxm, int node)
 {
@@ -61,9 +73,9 @@ int acpi_map_pxm_to_node(int pxm)
 	node = pxm_to_node_map[pxm];
 
 	if (node == NUMA_NO_NODE) {
-		if (nodes_weight(nodes_found_map) >= MAX_NUMNODES)
-			return NUMA_NO_NODE;
 		node = first_unset_node(nodes_found_map);
+		if (node >= MAX_NUMNODES)
+			return NUMA_NO_NODE;
 		__acpi_map_pxm_to_node(pxm, node);
 		node_set(node, nodes_found_map);
 	}
@@ -72,6 +84,101 @@ int acpi_map_pxm_to_node(int pxm)
 }
 EXPORT_SYMBOL(acpi_map_pxm_to_node);
 
+#ifdef CONFIG_NUMA_EMU
+/*
+ * Take max_nid - 1 fake-numa nodes into account in both
+ * pxm_to_node_map()/node_to_pxm_map[] tables.
+ */
+int __init fix_pxm_node_maps(int max_nid)
+{
+	static int pxm_to_node_map_copy[MAX_PXM_DOMAINS] __initdata
+			= { [0 ... MAX_PXM_DOMAINS - 1] = NUMA_NO_NODE };
+	static int node_to_pxm_map_copy[MAX_NUMNODES] __initdata
+			= { [0 ... MAX_NUMNODES - 1] = PXM_INVAL };
+	int i, j, index = -1, count = 0;
+	nodemask_t nodes_to_enable;
+
+	if (numa_off)
+		return -1;
+
+	/* no or incomplete node/PXM mapping set, nothing to do */
+	if (srat_disabled())
+		return 0;
+
+	/* find fake nodes PXM mapping */
+	for (i = 0; i < MAX_NUMNODES; i++) {
+		if (node_to_pxm_map[i] != PXM_INVAL) {
+			for (j = 0; j <= max_nid; j++) {
+				if ((emu_nid_to_phys[j] == i) &&
+				    WARN(node_to_pxm_map_copy[j] != PXM_INVAL,
+					 "Node %d is already binded to PXM %d\n",
+					 j, node_to_pxm_map_copy[j]))
+					return -1;
+				if (emu_nid_to_phys[j] == i) {
+					node_to_pxm_map_copy[j] =
+						node_to_pxm_map[i];
+					if (j > index)
+						index = j;
+					count++;
+				}
+			}
+		}
+	}
+	if (index == -1) {
+		pr_debug("No node/PXM mapping has been set\n");
+		/* nothing more to be done */
+		return 0;
+	}
+	if (WARN(index != max_nid, "%d max nid  when expected %d\n",
+		      index, max_nid))
+		return -1;
+
+	nodes_clear(nodes_to_enable);
+
+	/* map phys nodes not used for fake nodes */
+	for (i = 0; i < MAX_NUMNODES; i++) {
+		if (node_to_pxm_map[i] != PXM_INVAL) {
+			for (j = 0; j <= max_nid; j++)
+				if (emu_nid_to_phys[j] == i)
+					break;
+			/* fake nodes PXM mapping has been done */
+			if (j <= max_nid)
+				continue;
+			/* find first hole */
+			for (j = 0;
+			     j < MAX_NUMNODES &&
+				 node_to_pxm_map_copy[j] != PXM_INVAL;
+			     j++)
+			;
+			if (WARN(j == MAX_NUMNODES,
+			    "Number of nodes exceeds MAX_NUMNODES\n"))
+				return -1;
+			node_to_pxm_map_copy[j] = node_to_pxm_map[i];
+			node_set(j, nodes_to_enable);
+			count++;
+		}
+	}
+
+	/* creating reverse mapping in pxm_to_node_map[] */
+	for (i = 0; i < MAX_NUMNODES; i++)
+		if (node_to_pxm_map_copy[i] != PXM_INVAL &&
+		    pxm_to_node_map_copy[node_to_pxm_map_copy[i]] == NUMA_NO_NODE)
+			pxm_to_node_map_copy[node_to_pxm_map_copy[i]] = i;
+
+	/* overwrite with new mapping */
+	for (i = 0; i < MAX_NUMNODES; i++) {
+		node_to_pxm_map[i] = node_to_pxm_map_copy[i];
+		pxm_to_node_map[i] = pxm_to_node_map_copy[i];
+	}
+
+	/* enable other nodes found in PXM for hotplug */
+	nodes_or(numa_nodes_parsed, nodes_to_enable, numa_nodes_parsed);
+
+	pr_debug("found %d total number of nodes\n", count);
+	return 0;
+}
+#endif
+
 static void __init
 acpi_table_print_srat_entry(struct acpi_subtable_header *header)
 {
@@ -83,8 +190,7 @@ acpi_table_print_srat_entry(struct acpi_subtable_header *header)
 			pr_debug("SRAT Processor (id[0x%02x] eid[0x%02x]) in proximity domain %d %s\n",
 				 p->apic_id, p->local_sapic_eid,
 				 p->proximity_domain_lo,
-				 (p->flags & ACPI_SRAT_CPU_ENABLED) ?
-				 "enabled" : "disabled");
+				 str_enabled_disabled(p->flags & ACPI_SRAT_CPU_ENABLED));
 		}
 		break;
 
@@ -96,8 +202,7 @@ acpi_table_print_srat_entry(struct acpi_subtable_header *header)
 				 (unsigned long long)p->base_address,
 				 (unsigned long long)p->length,
 				 p->proximity_domain,
-				 (p->flags & ACPI_SRAT_MEM_ENABLED) ?
-				 "enabled" : "disabled",
+				 str_enabled_disabled(p->flags & ACPI_SRAT_MEM_ENABLED),
 				 (p->flags & ACPI_SRAT_MEM_HOT_PLUGGABLE) ?
 				 " hot-pluggable" : "",
 				 (p->flags & ACPI_SRAT_MEM_NON_VOLATILE) ?
@@ -112,8 +217,7 @@ acpi_table_print_srat_entry(struct acpi_subtable_header *header)
 			pr_debug("SRAT Processor (x2apicid[0x%08x]) in proximity domain %d %s\n",
 				 p->apic_id,
 				 p->proximity_domain,
-				 (p->flags & ACPI_SRAT_CPU_ENABLED) ?
-				 "enabled" : "disabled");
+				 str_enabled_disabled(p->flags & ACPI_SRAT_CPU_ENABLED));
 		}
 		break;
 
@@ -124,8 +228,47 @@ acpi_table_print_srat_entry(struct acpi_subtable_header *header)
 			pr_debug("SRAT Processor (acpi id[0x%04x]) in proximity domain %d %s\n",
 				 p->acpi_processor_uid,
 				 p->proximity_domain,
-				 (p->flags & ACPI_SRAT_GICC_ENABLED) ?
-				 "enabled" : "disabled");
+				 str_enabled_disabled(p->flags & ACPI_SRAT_GICC_ENABLED));
+		}
+		break;
+
+	case ACPI_SRAT_TYPE_GENERIC_AFFINITY:
+	{
+		struct acpi_srat_generic_affinity *p =
+			(struct acpi_srat_generic_affinity *)header;
+
+		if (p->device_handle_type == 1) {
+			/*
+			 * For pci devices this may be the only place they
+			 * are assigned a proximity domain
+			 */
+			pr_debug("SRAT Generic Initiator(Seg:%u BDF:%u) in proximity domain %d %s\n",
+				 *(u16 *)(&p->device_handle[0]),
+				 *(u16 *)(&p->device_handle[2]),
+				 p->proximity_domain,
+				 str_enabled_disabled(p->flags & ACPI_SRAT_GENERIC_AFFINITY_ENABLED));
+		} else {
+			/*
+			 * In this case we can rely on the device having a
+			 * proximity domain reference
+			 */
+			pr_debug("SRAT Generic Initiator(HID=%.8s UID=%.4s) in proximity domain %d %s\n",
+				(char *)(&p->device_handle[0]),
+				(char *)(&p->device_handle[8]),
+				p->proximity_domain,
+				str_enabled_disabled(p->flags & ACPI_SRAT_GENERIC_AFFINITY_ENABLED));
+		}
+	}
+	break;
+
+	case ACPI_SRAT_TYPE_RINTC_AFFINITY:
+		{
+			struct acpi_srat_rintc_affinity *p =
+			    (struct acpi_srat_rintc_affinity *)header;
+			pr_debug("SRAT Processor (acpi id[0x%04x]) in proximity domain %d %s\n",
+				 p->acpi_processor_uid,
+				 p->proximity_domain,
+				 str_enabled_disabled(p->flags & ACPI_SRAT_RINTC_ENABLED));
 		}
 		break;
 
@@ -147,7 +290,7 @@ static int __init slit_valid(struct acpi_table_slit *slit)
 	int i, j;
 	int d = slit->locality_count;
 	for (i = 0; i < d; i++) {
-		for (j = 0; j < d; j++)  {
+		for (j = 0; j < d; j++) {
 			u8 val = slit->entry[d*i + j];
 			if (i == j) {
 				if (val != LOCAL_DISTANCE)
@@ -162,7 +305,7 @@ static int __init slit_valid(struct acpi_table_slit *slit)
 void __init bad_srat(void)
 {
 	pr_err("SRAT: SRAT not used.\n");
-	acpi_numa = -1;
+	disable_srat();
 }
 
 int __init srat_disabled(void)
@@ -170,16 +313,26 @@ int __init srat_disabled(void)
 	return acpi_numa < 0;
 }
 
-#if defined(CONFIG_X86) || defined(CONFIG_ARM64)
+__weak int __init numa_fill_memblks(u64 start, u64 end)
+{
+	return NUMA_NO_MEMBLK;
+}
+
 /*
  * Callback for SLIT parsing.  pxm_to_node() returns NUMA_NO_NODE for
  * I/O localities since SRAT does not list them.  I/O localities are
  * not supported at this point.
  */
-void __init acpi_numa_slit_init(struct acpi_table_slit *slit)
+static int __init acpi_parse_slit(struct acpi_table_header *table)
 {
+	struct acpi_table_slit *slit = (struct acpi_table_slit *)table;
 	int i, j;
 
+	if (!slit_valid(slit)) {
+		pr_info("SLIT table looks invalid. Not used.\n");
+		return -EINVAL;
+	}
+
 	for (i = 0; i < slit->locality_count; i++) {
 		const int from_node = pxm_to_node(i);
 
@@ -196,31 +349,36 @@ void __init acpi_numa_slit_init(struct acpi_table_slit *slit)
 				slit->entry[slit->locality_count * i + j]);
 		}
 	}
+
+	return 0;
 }
 
-/*
- * Default callback for parsing of the Proximity Domain <-> Memory
- * Area mappings
- */
-int __init
-acpi_numa_memory_affinity_init(struct acpi_srat_mem_affinity *ma)
+static int parsed_numa_memblks __initdata;
+
+static int __init
+acpi_parse_memory_affinity(union acpi_subtable_headers *header,
+			   const unsigned long table_end)
 {
+	struct acpi_srat_mem_affinity *ma;
 	u64 start, end;
 	u32 hotpluggable;
 	int node, pxm;
 
+	ma = (struct acpi_srat_mem_affinity *)header;
+
+	acpi_table_print_srat_entry(&header->common);
+
 	if (srat_disabled())
-		goto out_err;
+		return 0;
 	if (ma->header.length < sizeof(struct acpi_srat_mem_affinity)) {
 		pr_err("SRAT: Unexpected header length: %d\n",
 		       ma->header.length);
 		goto out_err_bad_srat;
 	}
 	if ((ma->flags & ACPI_SRAT_MEM_ENABLED) == 0)
-		goto out_err;
-	hotpluggable = ma->flags & ACPI_SRAT_MEM_HOT_PLUGGABLE;
-	if (hotpluggable && !IS_ENABLED(CONFIG_MEMORY_HOTPLUG))
-		goto out_err;
+		return 0;
+	hotpluggable = IS_ENABLED(CONFIG_MEMORY_HOTPLUG) &&
+		(ma->flags & ACPI_SRAT_MEM_HOT_PLUGGABLE);
 
 	start = ma->base_address;
 	end = start + ma->length;
@@ -229,7 +387,7 @@ acpi_numa_memory_affinity_init(struct acpi_srat_mem_affinity *ma)
 		pxm &= 0xff;
 
 	node = acpi_map_pxm_to_node(pxm);
-	if (node == NUMA_NO_NODE || node >= MAX_NUMNODES) {
+	if (node == NUMA_NO_NODE) {
 		pr_err("SRAT: Too many proximity domains.\n");
 		goto out_err_bad_srat;
 	}
@@ -256,24 +414,65 @@ acpi_numa_memory_affinity_init(struct acpi_srat_mem_affinity *ma)
 
 	max_possible_pfn = max(max_possible_pfn, PFN_UP(end - 1));
 
+	parsed_numa_memblks++;
+
 	return 0;
+
 out_err_bad_srat:
+	/* Just disable SRAT, but do not fail and ignore errors. */
 	bad_srat();
-out_err:
-	return -EINVAL;
+
+	return 0;
 }
-#endif /* defined(CONFIG_X86) || defined (CONFIG_ARM64) */
 
-static int __init acpi_parse_slit(struct acpi_table_header *table)
+static int __init acpi_parse_cfmws(union acpi_subtable_headers *header,
+				   void *arg, const unsigned long table_end)
 {
-	struct acpi_table_slit *slit = (struct acpi_table_slit *)table;
+	struct acpi_cedt_cfmws *cfmws;
+	int *fake_pxm = arg;
+	u64 start, end, align;
+	int node;
+	int err;
 
-	if (!slit_valid(slit)) {
-		pr_info("SLIT table looks invalid. Not used.\n");
+	cfmws = (struct acpi_cedt_cfmws *)header;
+	start = cfmws->base_hpa;
+	end = cfmws->base_hpa + cfmws->window_size;
+
+	/* Align memblock size to CFMW regions if possible */
+	align = 1UL << __ffs(start | end);
+	if (align >= SZ_256M) {
+		err = memory_block_advise_max_size(align);
+		if (err)
+			pr_warn("CFMWS: memblock size advise failed (%d)\n", err);
+	} else
+		pr_err("CFMWS: [BIOS BUG] base/size alignment violates spec\n");
+
+	/*
+	 * The SRAT may have already described NUMA details for all,
+	 * or a portion of, this CFMWS HPA range. Extend the memblks
+	 * found for any portion of the window to cover the entire
+	 * window.
+	 */
+	if (!numa_fill_memblks(start, end))
+		return 0;
+
+	/* No SRAT description. Create a new node. */
+	node = acpi_map_pxm_to_node(*fake_pxm);
+
+	if (node == NUMA_NO_NODE) {
+		pr_err("ACPI NUMA: Too many proximity domains while processing CFMWS.\n");
 		return -EINVAL;
 	}
-	acpi_numa_slit_init(slit);
 
+	if (numa_add_reserved_memblk(node, start, end) < 0) {
+		/* CXL driver must handle the NUMA_NO_NODE case */
+		pr_warn("ACPI NUMA: Failed to add memblk for CFMWS node %d [mem %#llx-%#llx]\n",
+			node, start, end);
+	}
+	node_set(node, numa_nodes_parsed);
+
+	/* Set the next available fake_pxm value */
+	(*fake_pxm)++;
 	return 0;
 }
 
@@ -290,8 +489,6 @@ acpi_parse_x2apic_affinity(union acpi_subtable_headers *header,
 	struct acpi_srat_x2apic_cpu_affinity *processor_affinity;
 
 	processor_affinity = (struct acpi_srat_x2apic_cpu_affinity *)header;
-	if (!processor_affinity)
-		return -EINVAL;
 
 	acpi_table_print_srat_entry(&header->common);
 
@@ -308,8 +505,6 @@ acpi_parse_processor_affinity(union acpi_subtable_headers *header,
 	struct acpi_srat_cpu_affinity *processor_affinity;
 
 	processor_affinity = (struct acpi_srat_cpu_affinity *)header;
-	if (!processor_affinity)
-		return -EINVAL;
 
 	acpi_table_print_srat_entry(&header->common);
 
@@ -326,8 +521,6 @@ acpi_parse_gicc_affinity(union acpi_subtable_headers *header,
 	struct acpi_srat_gicc_affinity *processor_affinity;
 
 	processor_affinity = (struct acpi_srat_gicc_affinity *)header;
-	if (!processor_affinity)
-		return -EINVAL;
 
 	acpi_table_print_srat_entry(&header->common);
 
@@ -337,23 +530,53 @@ acpi_parse_gicc_affinity(union acpi_subtable_headers *header,
 	return 0;
 }
 
-static int __initdata parsed_numa_memblks;
-
+#if defined(CONFIG_X86) || defined(CONFIG_ARM64)
 static int __init
-acpi_parse_memory_affinity(union acpi_subtable_headers * header,
-			   const unsigned long end)
+acpi_parse_gi_affinity(union acpi_subtable_headers *header,
+		       const unsigned long end)
 {
-	struct acpi_srat_mem_affinity *memory_affinity;
+	struct acpi_srat_generic_affinity *gi_affinity;
+	int node;
 
-	memory_affinity = (struct acpi_srat_mem_affinity *)header;
-	if (!memory_affinity)
+	gi_affinity = (struct acpi_srat_generic_affinity *)header;
+	if (!gi_affinity)
 		return -EINVAL;
+	acpi_table_print_srat_entry(&header->common);
+
+	if (!(gi_affinity->flags & ACPI_SRAT_GENERIC_AFFINITY_ENABLED))
+		return -EINVAL;
+
+	node = acpi_map_pxm_to_node(gi_affinity->proximity_domain);
+	if (node == NUMA_NO_NODE) {
+		pr_err("SRAT: Too many proximity domains.\n");
+		return -EINVAL;
+	}
+	node_set(node, numa_nodes_parsed);
+	node_set_state(node, N_GENERIC_INITIATOR);
+
+	return 0;
+}
+#else
+static int __init
+acpi_parse_gi_affinity(union acpi_subtable_headers *header,
+		       const unsigned long end)
+{
+	return 0;
+}
+#endif /* defined(CONFIG_X86) || defined (CONFIG_ARM64) */
+
+static int __init
+acpi_parse_rintc_affinity(union acpi_subtable_headers *header,
+			  const unsigned long end)
+{
+	struct acpi_srat_rintc_affinity *rintc_affinity;
 
+	rintc_affinity = (struct acpi_srat_rintc_affinity *)header;
 	acpi_table_print_srat_entry(&header->common);
 
 	/* let architecture-dependent part to do it */
-	if (!acpi_numa_memory_affinity_init(memory_affinity))
-		parsed_numa_memblks++;
+	acpi_numa_rintc_affinity_init(rintc_affinity);
+
 	return 0;
 }
 
@@ -379,7 +602,7 @@ acpi_table_parse_srat(enum acpi_srat_type id,
 
 int __init acpi_numa_init(void)
 {
-	int cnt = 0;
+	int i, fake_pxm, cnt = 0;
 
 	if (acpi_disabled)
 		return -EINVAL;
@@ -392,7 +615,7 @@ int __init acpi_numa_init(void)
 
 	/* SRAT: System Resource Affinity Table */
 	if (!acpi_table_parse(ACPI_SIG_SRAT, acpi_parse_srat)) {
-		struct acpi_subtable_proc srat_proc[3];
+		struct acpi_subtable_proc srat_proc[5];
 
 		memset(srat_proc, 0, sizeof(srat_proc));
 		srat_proc[0].id = ACPI_SRAT_TYPE_CPU_AFFINITY;
@@ -401,6 +624,10 @@ int __init acpi_numa_init(void)
 		srat_proc[1].handler = acpi_parse_x2apic_affinity;
 		srat_proc[2].id = ACPI_SRAT_TYPE_GICC_AFFINITY;
 		srat_proc[2].handler = acpi_parse_gicc_affinity;
+		srat_proc[3].id = ACPI_SRAT_TYPE_GENERIC_AFFINITY;
+		srat_proc[3].handler = acpi_parse_gi_affinity;
+		srat_proc[4].id = ACPI_SRAT_TYPE_RINTC_AFFINITY;
+		srat_proc[4].handler = acpi_parse_rintc_affinity;
 
 		acpi_table_parse_entries_array(ACPI_SIG_SRAT,
 					sizeof(struct acpi_table_srat),
@@ -413,6 +640,23 @@ int __init acpi_numa_init(void)
 	/* SLIT: System Locality Information Table */
 	acpi_table_parse(ACPI_SIG_SLIT, acpi_parse_slit);
 
+	/*
+	 * CXL Fixed Memory Window Structures (CFMWS) must be parsed
+	 * after the SRAT. Create NUMA Nodes for CXL memory ranges that
+	 * are defined in the CFMWS and not already defined in the SRAT.
+	 * Initialize a fake_pxm as the first available PXM to emulate.
+	 */
+
+	/* fake_pxm is the next unused PXM value after SRAT parsing */
+	for (i = 0, fake_pxm = -1; i < MAX_NUMNODES; i++) {
+		if (node_to_pxm_map[i] > fake_pxm)
+			fake_pxm = node_to_pxm_map[i];
+	}
+	last_real_pxm = fake_pxm;
+	fake_pxm++;
+	acpi_table_parse_cedt(ACPI_CEDT_TYPE_CFMWS, acpi_parse_cfmws,
+			      &fake_pxm);
+
 	if (cnt < 0)
 		return cnt;
 	else if (!parsed_numa_memblks)
@@ -420,6 +664,14 @@ int __init acpi_numa_init(void)
 	return 0;
 }
 
+bool acpi_node_backed_by_real_pxm(int nid)
+{
+	int pxm = node_to_pxm(nid);
+
+	return pxm <= last_real_pxm;
+}
+EXPORT_SYMBOL_GPL(acpi_node_backed_by_real_pxm);
+
 static int acpi_get_pxm(acpi_handle h)
 {
 	unsigned long long pxm;
@@ -443,6 +695,6 @@ int acpi_get_node(acpi_handle handle)
 
 	pxm = acpi_get_pxm(handle);
 
-	return acpi_map_pxm_to_node(pxm);
+	return pxm_to_node(pxm);
 }
 EXPORT_SYMBOL(acpi_get_node);
diff --git a/drivers/acpi/nvs.c b/drivers/acpi/nvs.c
index 9f8712a557b3..a2b11069e792 100644
--- a/drivers/acpi/nvs.c
+++ b/drivers/acpi/nvs.c
@@ -5,6 +5,8 @@
  * Copyright (C) 2008-2011 Rafael J. Wysocki <rjw@sisk.pl>, Novell Inc.
  */
 
+#define pr_fmt(fmt) "ACPI: PM: " fmt
+
 #include <linux/io.h>
 #include <linux/kernel.h>
 #include <linux/list.h>
@@ -82,19 +84,19 @@ struct nvs_page {
 static LIST_HEAD(nvs_list);
 
 /**
- *	suspend_nvs_register - register platform NVS memory region to save
- *	@start - physical address of the region
- *	@size - size of the region
+ * suspend_nvs_register - register platform NVS memory region to save
+ * @start: Physical address of the region.
+ * @size: Size of the region.
  *
- *	The NVS region need not be page-aligned (both ends) and we arrange
- *	things so that the data from page-aligned addresses in this region will
- *	be copied into separate RAM pages.
+ * The NVS region need not be page-aligned (both ends) and we arrange
+ * things so that the data from page-aligned addresses in this region will
+ * be copied into separate RAM pages.
  */
 static int suspend_nvs_register(unsigned long start, unsigned long size)
 {
 	struct nvs_page *entry, *next;
 
-	pr_info("PM: Registering ACPI NVS region [mem %#010lx-%#010lx] (%ld bytes)\n",
+	pr_info("Registering ACPI NVS region [mem %#010lx-%#010lx] (%ld bytes)\n",
 		start, start + size - 1, size);
 
 	while (size > 0) {
@@ -123,7 +125,7 @@ static int suspend_nvs_register(unsigned long start, unsigned long size)
 }
 
 /**
- *	suspend_nvs_free - free data pages allocated for saving NVS regions
+ * suspend_nvs_free - free data pages allocated for saving NVS regions
  */
 void suspend_nvs_free(void)
 {
@@ -147,7 +149,7 @@ void suspend_nvs_free(void)
 }
 
 /**
- *	suspend_nvs_alloc - allocate memory necessary for saving NVS regions
+ * suspend_nvs_alloc - allocate memory necessary for saving NVS regions
  */
 int suspend_nvs_alloc(void)
 {
@@ -164,13 +166,13 @@ int suspend_nvs_alloc(void)
 }
 
 /**
- *	suspend_nvs_save - save NVS memory regions
+ * suspend_nvs_save - save NVS memory regions
  */
 int suspend_nvs_save(void)
 {
 	struct nvs_page *entry;
 
-	printk(KERN_INFO "PM: Saving platform NVS memory\n");
+	pr_info("Saving platform NVS memory\n");
 
 	list_for_each_entry(entry, &nvs_list, node)
 		if (entry->data) {
@@ -193,16 +195,16 @@ int suspend_nvs_save(void)
 }
 
 /**
- *	suspend_nvs_restore - restore NVS memory regions
+ * suspend_nvs_restore - restore NVS memory regions
  *
- *	This function is going to be called with interrupts disabled, so it
- *	cannot iounmap the virtual addresses used to access the NVS region.
+ * This function is going to be called with interrupts disabled, so it
+ * cannot iounmap the virtual addresses used to access the NVS region.
  */
 void suspend_nvs_restore(void)
 {
 	struct nvs_page *entry;
 
-	printk(KERN_INFO "PM: Restoring platform NVS memory\n");
+	pr_info("Restoring platform NVS memory\n");
 
 	list_for_each_entry(entry, &nvs_list, node)
 		if (entry->data)
diff --git a/drivers/acpi/osi.c b/drivers/acpi/osi.c
index 9f6853809138..f2c943b934be 100644
--- a/drivers/acpi/osi.c
+++ b/drivers/acpi/osi.c
@@ -42,32 +42,7 @@ static struct acpi_osi_entry
 osi_setup_entries[OSI_STRING_ENTRIES_MAX] __initdata = {
 	{"Module Device", true},
 	{"Processor Device", true},
-	{"3.0 _SCP Extensions", true},
 	{"Processor Aggregator Device", true},
-	/*
-	 * Linux-Dell-Video is used by BIOS to disable RTD3 for NVidia graphics
-	 * cards as RTD3 is not supported by drivers now.  Systems with NVidia
-	 * cards will hang without RTD3 disabled.
-	 *
-	 * Once NVidia drivers officially support RTD3, this _OSI strings can
-	 * be removed if both new and old graphics cards are supported.
-	 */
-	{"Linux-Dell-Video", true},
-	/*
-	 * Linux-Lenovo-NV-HDMI-Audio is used by BIOS to power on NVidia's HDMI
-	 * audio device which is turned off for power-saving in Windows OS.
-	 * This power management feature observed on some Lenovo Thinkpad
-	 * systems which will not be able to output audio via HDMI without
-	 * a BIOS workaround.
-	 */
-	{"Linux-Lenovo-NV-HDMI-Audio", true},
-	/*
-	 * Linux-HPI-Hybrid-Graphics is used by BIOS to enable dGPU to
-	 * output video directly to external monitors on HP Inc. mobile
-	 * workstations as Nvidia and AMD VGA drivers provide limited
-	 * hybrid graphics supports.
-	 */
-	{"Linux-HPI-Hybrid-Graphics", true},
 };
 
 static u32 acpi_osi_handler(acpi_string interface, u32 supported)
@@ -134,7 +109,7 @@ void __init acpi_osi_setup(char *str)
 			break;
 		} else if (osi->string[0] == '\0') {
 			osi->enable = enable;
-			strncpy(osi->string, str, OSI_STRING_LENGTH_MAX);
+			strscpy(osi->string, str, OSI_STRING_LENGTH_MAX);
 			break;
 		}
 	}
diff --git a/drivers/acpi/osl.c b/drivers/acpi/osl.c
index 762c5d50b8fe..05393a7315fe 100644
--- a/drivers/acpi/osl.c
+++ b/drivers/acpi/osl.c
@@ -9,6 +9,8 @@
  *   Author: Matthew Wilcox <willy@linux.intel.com>
  */
 
+#define pr_fmt(fmt) "ACPI: OSL: " fmt
+
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/slab.h>
@@ -34,9 +36,9 @@
 #include <linux/io-64-nonatomic-lo-hi.h>
 
 #include "acpica/accommon.h"
-#include "acpica/acnamesp.h"
 #include "internal.h"
 
+/* Definitions for ACPI_DEBUG_PRINT() */
 #define _COMPONENT		ACPI_OS_SERVICES
 ACPI_MODULE_NAME("osl");
 
@@ -77,7 +79,10 @@ struct acpi_ioremap {
 	void __iomem *virt;
 	acpi_physical_address phys;
 	acpi_size size;
-	unsigned long refcount;
+	union {
+		unsigned long refcount;
+		struct rcu_work rwork;
+	} track;
 };
 
 static LIST_HEAD(acpi_ioremaps);
@@ -144,7 +149,7 @@ void acpi_os_printf(const char *fmt, ...)
 }
 EXPORT_SYMBOL(acpi_os_printf);
 
-void acpi_os_vprintf(const char *fmt, va_list args)
+void __printf(1, 0) acpi_os_vprintf(const char *fmt, va_list args)
 {
 	static char buffer[512];
 
@@ -206,7 +211,7 @@ acpi_physical_address __init acpi_os_get_root_pointer(void)
 			return efi.acpi20;
 		if (efi.acpi != EFI_INVALID_TABLE_ADDR)
 			return efi.acpi;
-		pr_err(PREFIX "System description tables not found\n");
+		pr_err("System description tables not found\n");
 	} else if (IS_ENABLED(CONFIG_ACPI_LEGACY_TABLES_LOOKUP)) {
 		acpi_find_root_pointer(&pa);
 	}
@@ -250,7 +255,7 @@ void __iomem *acpi_os_get_iomem(acpi_physical_address phys, unsigned int size)
 	map = acpi_map_lookup(phys, size);
 	if (map) {
 		virt = map->virt + (phys - map->phys);
-		map->refcount++;
+		map->track.refcount++;
 	}
 	mutex_unlock(&acpi_ioremap_lock);
 	return virt;
@@ -271,7 +276,7 @@ acpi_map_lookup_virt(void __iomem *virt, acpi_size size)
 	return NULL;
 }
 
-#if defined(CONFIG_IA64) || defined(CONFIG_ARM64)
+#if defined(CONFIG_ARM64) || defined(CONFIG_RISCV)
 /* ioremap will take care of cache attributes */
 #define should_use_kmap(pfn)   0
 #else
@@ -324,7 +329,7 @@ void __iomem __ref
 	acpi_size pg_sz;
 
 	if (phys > ULONG_MAX) {
-		printk(KERN_ERR PREFIX "Cannot map memory that high\n");
+		pr_err("Cannot map memory that high: 0x%llx\n", phys);
 		return NULL;
 	}
 
@@ -335,7 +340,7 @@ void __iomem __ref
 	/* Check if there's a suitable mapping already. */
 	map = acpi_map_lookup(phys, size);
 	if (map) {
-		map->refcount++;
+		map->track.refcount++;
 		goto out;
 	}
 
@@ -347,7 +352,7 @@ void __iomem __ref
 
 	pg_off = round_down(phys, PAGE_SIZE);
 	pg_sz = round_up(phys + size, PAGE_SIZE) - pg_off;
-	virt = acpi_map(pg_off, pg_sz);
+	virt = acpi_map(phys, size);
 	if (!virt) {
 		mutex_unlock(&acpi_ioremap_lock);
 		kfree(map);
@@ -355,10 +360,10 @@ void __iomem __ref
 	}
 
 	INIT_LIST_HEAD(&map->list);
-	map->virt = virt;
+	map->virt = (void __iomem __force *)((unsigned long)virt & PAGE_MASK);
 	map->phys = pg_off;
 	map->size = pg_sz;
-	map->refcount = 1;
+	map->track.refcount = 1;
 
 	list_add_tail_rcu(&map->list, &acpi_ioremaps);
 
@@ -374,21 +379,26 @@ void *__ref acpi_os_map_memory(acpi_physical_address phys, acpi_size size)
 }
 EXPORT_SYMBOL_GPL(acpi_os_map_memory);
 
-/* Must be called with mutex_lock(&acpi_ioremap_lock) */
-static unsigned long acpi_os_drop_map_ref(struct acpi_ioremap *map)
+static void acpi_os_map_remove(struct work_struct *work)
 {
-	unsigned long refcount = --map->refcount;
+	struct acpi_ioremap *map = container_of(to_rcu_work(work),
+						struct acpi_ioremap,
+						track.rwork);
 
-	if (!refcount)
-		list_del_rcu(&map->list);
-	return refcount;
+	acpi_unmap(map->phys, map->virt);
+	kfree(map);
 }
 
-static void acpi_os_map_cleanup(struct acpi_ioremap *map)
+/* Must be called with mutex_lock(&acpi_ioremap_lock) */
+static void acpi_os_drop_map_ref(struct acpi_ioremap *map)
 {
-	synchronize_rcu_expedited();
-	acpi_unmap(map->phys, map->virt);
-	kfree(map);
+	if (--map->track.refcount)
+		return;
+
+	list_del_rcu(&map->list);
+
+	INIT_RCU_WORK(&map->track.rwork, acpi_os_map_remove);
+	queue_rcu_work(system_percpu_wq, &map->track.rwork);
 }
 
 /**
@@ -397,8 +407,8 @@ static void acpi_os_map_cleanup(struct acpi_ioremap *map)
  * @size: Size of the address range to drop a reference to.
  *
  * Look up the given virtual address range in the list of existing ACPI memory
- * mappings, drop a reference to it and unmap it if there are no more active
- * references to it.
+ * mappings, drop a reference to it and if there are no more active references
+ * to it, queue it up for later removal.
  *
  * During early init (when acpi_permanent_mmap has not been set yet) this
  * routine simply calls __acpi_unmap_table() to get the job done.  Since
@@ -408,7 +418,6 @@ static void acpi_os_map_cleanup(struct acpi_ioremap *map)
 void __ref acpi_os_unmap_iomem(void __iomem *virt, acpi_size size)
 {
 	struct acpi_ioremap *map;
-	unsigned long refcount;
 
 	if (!acpi_permanent_mmap) {
 		__acpi_unmap_table(virt, size);
@@ -416,44 +425,43 @@ void __ref acpi_os_unmap_iomem(void __iomem *virt, acpi_size size)
 	}
 
 	mutex_lock(&acpi_ioremap_lock);
+
 	map = acpi_map_lookup_virt(virt, size);
 	if (!map) {
 		mutex_unlock(&acpi_ioremap_lock);
-		WARN(true, PREFIX "%s: bad address %p\n", __func__, virt);
+		WARN(true, "ACPI: %s: bad address %p\n", __func__, virt);
 		return;
 	}
-	refcount = acpi_os_drop_map_ref(map);
-	mutex_unlock(&acpi_ioremap_lock);
+	acpi_os_drop_map_ref(map);
 
-	if (!refcount)
-		acpi_os_map_cleanup(map);
+	mutex_unlock(&acpi_ioremap_lock);
 }
 EXPORT_SYMBOL_GPL(acpi_os_unmap_iomem);
 
+/**
+ * acpi_os_unmap_memory - Drop a memory mapping reference.
+ * @virt: Start of the address range to drop a reference to.
+ * @size: Size of the address range to drop a reference to.
+ */
 void __ref acpi_os_unmap_memory(void *virt, acpi_size size)
 {
-	return acpi_os_unmap_iomem((void __iomem *)virt, size);
+	acpi_os_unmap_iomem((void __iomem *)virt, size);
 }
 EXPORT_SYMBOL_GPL(acpi_os_unmap_memory);
 
-int acpi_os_map_generic_address(struct acpi_generic_address *gas)
+void __iomem *acpi_os_map_generic_address(struct acpi_generic_address *gas)
 {
 	u64 addr;
-	void __iomem *virt;
 
 	if (gas->space_id != ACPI_ADR_SPACE_SYSTEM_MEMORY)
-		return 0;
+		return NULL;
 
 	/* Handle possible alignment issues */
 	memcpy(&addr, &gas->address, sizeof(addr));
 	if (!addr || !gas->bit_width)
-		return -EINVAL;
-
-	virt = acpi_os_map_iomem(addr, gas->bit_width / 8);
-	if (!virt)
-		return -EIO;
+		return NULL;
 
-	return 0;
+	return acpi_os_map_iomem(addr, gas->bit_width / 8);
 }
 EXPORT_SYMBOL(acpi_os_map_generic_address);
 
@@ -461,7 +469,6 @@ void acpi_os_unmap_generic_address(struct acpi_generic_address *gas)
 {
 	u64 addr;
 	struct acpi_ioremap *map;
-	unsigned long refcount;
 
 	if (gas->space_id != ACPI_ADR_SPACE_SYSTEM_MEMORY)
 		return;
@@ -472,22 +479,21 @@ void acpi_os_unmap_generic_address(struct acpi_generic_address *gas)
 		return;
 
 	mutex_lock(&acpi_ioremap_lock);
+
 	map = acpi_map_lookup(addr, gas->bit_width / 8);
 	if (!map) {
 		mutex_unlock(&acpi_ioremap_lock);
 		return;
 	}
-	refcount = acpi_os_drop_map_ref(map);
-	mutex_unlock(&acpi_ioremap_lock);
+	acpi_os_drop_map_ref(map);
 
-	if (!refcount)
-		acpi_os_map_cleanup(map);
+	mutex_unlock(&acpi_ioremap_lock);
 }
 EXPORT_SYMBOL(acpi_os_unmap_generic_address);
 
 #ifdef ACPI_FUTURE_USAGE
 acpi_status
-acpi_os_get_physical_address(void *virt, acpi_physical_address * phys)
+acpi_os_get_physical_address(void *virt, acpi_physical_address *phys)
 {
 	if (!phys || !virt)
 		return AE_BAD_PARAMETER;
@@ -524,13 +530,12 @@ acpi_os_predefined_override(const struct acpi_predefined_names *init_val,
 
 	*new_val = NULL;
 	if (!memcmp(init_val->name, "_OS_", 4) && strlen(acpi_os_name)) {
-		printk(KERN_INFO PREFIX "Overriding _OS definition to '%s'\n",
-		       acpi_os_name);
+		pr_info("Overriding _OS definition to '%s'\n", acpi_os_name);
 		*new_val = acpi_os_name;
 	}
 
 	if (!memcmp(init_val->name, "_REV", 4) && acpi_rev_override) {
-		printk(KERN_INFO PREFIX "Overriding _REV return value to 5\n");
+		pr_info("Overriding _REV return value to 5\n");
 		*new_val = (char *)5;
 	}
 
@@ -539,11 +544,7 @@ acpi_os_predefined_override(const struct acpi_predefined_names *init_val,
 
 static irqreturn_t acpi_irq(int irq, void *dev_id)
 {
-	u32 handled;
-
-	handled = (*acpi_irq_handler) (acpi_irq_context);
-
-	if (handled) {
+	if ((*acpi_irq_handler)(acpi_irq_context)) {
 		acpi_irq_handled++;
 		return IRQ_HANDLED;
 	} else {
@@ -571,15 +572,15 @@ acpi_os_install_interrupt_handler(u32 gsi, acpi_osd_handler handler,
 		return AE_ALREADY_ACQUIRED;
 
 	if (acpi_gsi_to_irq(gsi, &irq) < 0) {
-		printk(KERN_ERR PREFIX "SCI (ACPI GSI %d) not registered\n",
-		       gsi);
+		pr_err("SCI (ACPI GSI %d) not registered\n", gsi);
 		return AE_OK;
 	}
 
 	acpi_irq_handler = handler;
 	acpi_irq_context = context;
-	if (request_irq(irq, acpi_irq, IRQF_SHARED, "acpi", acpi_irq)) {
-		printk(KERN_ERR PREFIX "SCI (IRQ%d) allocation failed\n", irq);
+	if (request_threaded_irq(irq, NULL, acpi_irq, IRQF_SHARED | IRQF_ONESHOT,
+			         "acpi", acpi_irq)) {
+		pr_err("SCI (IRQ%d) allocation failed\n", irq);
 		acpi_irq_handler = NULL;
 		return AE_NOT_ACQUIRED;
 	}
@@ -606,7 +607,27 @@ acpi_status acpi_os_remove_interrupt_handler(u32 gsi, acpi_osd_handler handler)
 
 void acpi_os_sleep(u64 ms)
 {
-	msleep(ms);
+	u64 usec = ms * USEC_PER_MSEC, delta_us = 50;
+
+	/*
+	 * Use a hrtimer because the timer wheel timers are optimized for
+	 * cancelation before they expire and this timer is not going to be
+	 * canceled.
+	 *
+	 * Set the delta between the requested sleep time and the effective
+	 * deadline to at least 50 us in case there is an opportunity for timer
+	 * coalescing.
+	 *
+	 * Moreover, longer sleeps can be assumed to need somewhat less timer
+	 * precision, so sacrifice some of it for making the timer a more likely
+	 * candidate for coalescing by setting the delta to 1% of the sleep time
+	 * if it is above 5 ms (this value is chosen so that the delta is a
+	 * continuous function of the sleep time).
+	 */
+	if (ms > 5)
+		delta_us = (USEC_PER_MSEC / 100) * ms;
+
+	usleep_range(usec, usec + delta_us);
 }
 
 void acpi_os_stall(u32 us)
@@ -637,22 +658,33 @@ u64 acpi_os_get_timer(void)
 		(ACPI_100NSEC_PER_SEC / HZ);
 }
 
-acpi_status acpi_os_read_port(acpi_io_address port, u32 * value, u32 width)
+acpi_status acpi_os_read_port(acpi_io_address port, u32 *value, u32 width)
 {
 	u32 dummy;
 
-	if (!value)
+	if (!IS_ENABLED(CONFIG_HAS_IOPORT)) {
+		/*
+		 * set all-1 result as if reading from non-existing
+		 * I/O port
+		 */
+		*value = GENMASK(width, 0);
+		return AE_NOT_IMPLEMENTED;
+	}
+
+	if (value)
+		*value = 0;
+	else
 		value = &dummy;
 
-	*value = 0;
 	if (width <= 8) {
-		*(u8 *) value = inb(port);
+		*value = inb(port);
 	} else if (width <= 16) {
-		*(u16 *) value = inw(port);
+		*value = inw(port);
 	} else if (width <= 32) {
-		*(u32 *) value = inl(port);
+		*value = inl(port);
 	} else {
-		BUG();
+		pr_debug("%s: Access width %d not supported\n", __func__, width);
+		return AE_BAD_PARAMETER;
 	}
 
 	return AE_OK;
@@ -662,6 +694,9 @@ EXPORT_SYMBOL(acpi_os_read_port);
 
 acpi_status acpi_os_write_port(acpi_io_address port, u32 value, u32 width)
 {
+	if (!IS_ENABLED(CONFIG_HAS_IOPORT))
+		return AE_NOT_IMPLEMENTED;
+
 	if (width <= 8) {
 		outb(value, port);
 	} else if (width <= 16) {
@@ -669,7 +704,8 @@ acpi_status acpi_os_write_port(acpi_io_address port, u32 value, u32 width)
 	} else if (width <= 32) {
 		outl(value, port);
 	} else {
-		BUG();
+		pr_debug("%s: Access width %d not supported\n", __func__, width);
+		return AE_BAD_PARAMETER;
 	}
 
 	return AE_OK;
@@ -777,7 +813,7 @@ acpi_os_write_memory(acpi_physical_address phys_addr, u64 value, u32 width)
 
 #ifdef CONFIG_PCI
 acpi_status
-acpi_os_read_pci_configuration(struct acpi_pci_id * pci_id, u32 reg,
+acpi_os_read_pci_configuration(struct acpi_pci_id *pci_id, u32 reg,
 			       u64 *value, u32 width)
 {
 	int result, size;
@@ -809,7 +845,7 @@ acpi_os_read_pci_configuration(struct acpi_pci_id * pci_id, u32 reg,
 }
 
 acpi_status
-acpi_os_write_pci_configuration(struct acpi_pci_id * pci_id, u32 reg,
+acpi_os_write_pci_configuration(struct acpi_pci_id *pci_id, u32 reg,
 				u64 value, u32 width)
 {
 	int result, size;
@@ -1056,10 +1092,9 @@ int __init acpi_debugger_init(void)
 acpi_status acpi_os_execute(acpi_execute_type type,
 			    acpi_osd_exec_callback function, void *context)
 {
-	acpi_status status = AE_OK;
 	struct acpi_os_dpc *dpc;
-	struct workqueue_struct *queue;
 	int ret;
+
 	ACPI_DEBUG_PRINT((ACPI_DB_EXEC,
 			  "Scheduling function [%p(%p)] for deferred execution.\n",
 			  function, context));
@@ -1067,10 +1102,10 @@ acpi_status acpi_os_execute(acpi_execute_type type,
 	if (type == OSL_DEBUGGER_MAIN_THREAD) {
 		ret = acpi_debugger_create_thread(function, context);
 		if (ret) {
-			pr_err("Call to kthread_create() failed.\n");
-			status = AE_ERROR;
+			pr_err("Kernel thread creation failed\n");
+			return AE_ERROR;
 		}
-		goto out_thread;
+		return AE_OK;
 	}
 
 	/*
@@ -1088,44 +1123,41 @@ acpi_status acpi_os_execute(acpi_execute_type type,
 
 	dpc->function = function;
 	dpc->context = context;
+	INIT_WORK(&dpc->work, acpi_os_execute_deferred);
 
 	/*
 	 * To prevent lockdep from complaining unnecessarily, make sure that
 	 * there is a different static lockdep key for each workqueue by using
 	 * INIT_WORK() for each of them separately.
 	 */
-	if (type == OSL_NOTIFY_HANDLER) {
-		queue = kacpi_notify_wq;
-		INIT_WORK(&dpc->work, acpi_os_execute_deferred);
-	} else if (type == OSL_GPE_HANDLER) {
-		queue = kacpid_wq;
-		INIT_WORK(&dpc->work, acpi_os_execute_deferred);
-	} else {
+	switch (type) {
+	case OSL_NOTIFY_HANDLER:
+		ret = queue_work(kacpi_notify_wq, &dpc->work);
+		break;
+	case OSL_GPE_HANDLER:
+		/*
+		 * On some machines, a software-initiated SMI causes corruption
+		 * unless the SMI runs on CPU 0.  An SMI can be initiated by
+		 * any AML, but typically it's done in GPE-related methods that
+		 * are run via workqueues, so we can avoid the known corruption
+		 * cases by always queueing on CPU 0.
+		 */
+		ret = queue_work_on(0, kacpid_wq, &dpc->work);
+		break;
+	default:
 		pr_err("Unsupported os_execute type %d.\n", type);
-		status = AE_ERROR;
+		goto err;
 	}
-
-	if (ACPI_FAILURE(status))
-		goto err_workqueue;
-
-	/*
-	 * On some machines, a software-initiated SMI causes corruption unless
-	 * the SMI runs on CPU 0.  An SMI can be initiated by any AML, but
-	 * typically it's done in GPE-related methods that are run via
-	 * workqueues, so we can avoid the known corruption cases by always
-	 * queueing on CPU 0.
-	 */
-	ret = queue_work_on(0, queue, &dpc->work);
 	if (!ret) {
-		printk(KERN_ERR PREFIX
-			  "Call to queue_work() failed.\n");
-		status = AE_ERROR;
+		pr_err("Unable to queue work\n");
+		goto err;
 	}
-err_workqueue:
-	if (ACPI_FAILURE(status))
-		kfree(dpc);
-out_thread:
-	return status;
+
+	return AE_OK;
+
+err:
+	kfree(dpc);
+	return AE_ERROR;
 }
 EXPORT_SYMBOL(acpi_os_execute);
 
@@ -1161,9 +1193,9 @@ acpi_status acpi_hotplug_schedule(struct acpi_device *adev, u32 src)
 {
 	struct acpi_hp_work *hpw;
 
-	ACPI_DEBUG_PRINT((ACPI_DB_EXEC,
-		  "Scheduling hotplug event (%p, %u) for deferred execution.\n",
-		  adev, src));
+	acpi_handle_debug(adev->handle,
+			  "Scheduling hotplug event %u for deferred handling\n",
+			   src);
 
 	hpw = kmalloc(sizeof(*hpw), GFP_KERNEL);
 	if (!hpw)
@@ -1191,7 +1223,7 @@ bool acpi_queue_hotplug_work(struct work_struct *work)
 }
 
 acpi_status
-acpi_os_create_semaphore(u32 max_units, u32 initial_units, acpi_handle * handle)
+acpi_os_create_semaphore(u32 max_units, u32 initial_units, acpi_handle *handle)
 {
 	struct semaphore *sem = NULL;
 
@@ -1351,7 +1383,7 @@ acpi_status acpi_os_signal(u32 function, void *info)
 {
 	switch (function) {
 	case ACPI_SIGNAL_FATAL:
-		printk(KERN_ERR PREFIX "Fatal opcode executed\n");
+		pr_err("Fatal opcode executed\n");
 		break;
 	case ACPI_SIGNAL_BREAKPOINT:
 		/*
@@ -1403,7 +1435,7 @@ __setup("acpi_os_name=", acpi_os_name_setup);
 static int __init acpi_no_auto_serialize_setup(char *str)
 {
 	acpi_gbl_auto_serialize_methods = FALSE;
-	pr_info("ACPI: auto-serialization disabled\n");
+	pr_info("Auto-serialization disabled\n");
 
 	return 1;
 }
@@ -1454,38 +1486,28 @@ __setup("acpi_enforce_resources=", acpi_enforce_resources_setup);
 int acpi_check_resource_conflict(const struct resource *res)
 {
 	acpi_adr_space_type space_id;
-	acpi_size length;
-	u8 warn = 0;
-	int clash = 0;
 
 	if (acpi_enforce_resources == ENFORCE_RESOURCES_NO)
 		return 0;
-	if (!(res->flags & IORESOURCE_IO) && !(res->flags & IORESOURCE_MEM))
-		return 0;
 
 	if (res->flags & IORESOURCE_IO)
 		space_id = ACPI_ADR_SPACE_SYSTEM_IO;
-	else
+	else if (res->flags & IORESOURCE_MEM)
 		space_id = ACPI_ADR_SPACE_SYSTEM_MEMORY;
+	else
+		return 0;
+
+	if (!acpi_check_address_range(space_id, res->start, resource_size(res), 1))
+		return 0;
+
+	pr_info("Resource conflict; ACPI support missing from driver?\n");
+
+	if (acpi_enforce_resources == ENFORCE_RESOURCES_STRICT)
+		return -EBUSY;
+
+	if (acpi_enforce_resources == ENFORCE_RESOURCES_LAX)
+		pr_notice("Resource conflict: System may be unstable or behave erratically\n");
 
-	length = resource_size(res);
-	if (acpi_enforce_resources != ENFORCE_RESOURCES_NO)
-		warn = 1;
-	clash = acpi_check_address_range(space_id, res->start, length, warn);
-
-	if (clash) {
-		if (acpi_enforce_resources != ENFORCE_RESOURCES_NO) {
-			if (acpi_enforce_resources == ENFORCE_RESOURCES_LAX)
-				printk(KERN_NOTICE "ACPI: This conflict may"
-				       " cause random problems and system"
-				       " instability\n");
-			printk(KERN_INFO "ACPI: If an ACPI driver is available"
-			       " for this device, you should use it instead of"
-			       " the native driver\n");
-		}
-		if (acpi_enforce_resources == ENFORCE_RESOURCES_STRICT)
-			return -EBUSY;
-	}
 	return 0;
 }
 EXPORT_SYMBOL(acpi_check_resource_conflict);
@@ -1493,87 +1515,12 @@ EXPORT_SYMBOL(acpi_check_resource_conflict);
 int acpi_check_region(resource_size_t start, resource_size_t n,
 		      const char *name)
 {
-	struct resource res = {
-		.start = start,
-		.end   = start + n - 1,
-		.name  = name,
-		.flags = IORESOURCE_IO,
-	};
+	struct resource res = DEFINE_RES_IO_NAMED(start, n, name);
 
 	return acpi_check_resource_conflict(&res);
 }
 EXPORT_SYMBOL(acpi_check_region);
 
-static acpi_status acpi_deactivate_mem_region(acpi_handle handle, u32 level,
-					      void *_res, void **return_value)
-{
-	struct acpi_mem_space_context **mem_ctx;
-	union acpi_operand_object *handler_obj;
-	union acpi_operand_object *region_obj2;
-	union acpi_operand_object *region_obj;
-	struct resource *res = _res;
-	acpi_status status;
-
-	region_obj = acpi_ns_get_attached_object(handle);
-	if (!region_obj)
-		return AE_OK;
-
-	handler_obj = region_obj->region.handler;
-	if (!handler_obj)
-		return AE_OK;
-
-	if (region_obj->region.space_id != ACPI_ADR_SPACE_SYSTEM_MEMORY)
-		return AE_OK;
-
-	if (!(region_obj->region.flags & AOPOBJ_SETUP_COMPLETE))
-		return AE_OK;
-
-	region_obj2 = acpi_ns_get_secondary_object(region_obj);
-	if (!region_obj2)
-		return AE_OK;
-
-	mem_ctx = (void *)&region_obj2->extra.region_context;
-
-	if (!(mem_ctx[0]->address >= res->start &&
-	      mem_ctx[0]->address < res->end))
-		return AE_OK;
-
-	status = handler_obj->address_space.setup(region_obj,
-						  ACPI_REGION_DEACTIVATE,
-						  NULL, (void **)mem_ctx);
-	if (ACPI_SUCCESS(status))
-		region_obj->region.flags &= ~(AOPOBJ_SETUP_COMPLETE);
-
-	return status;
-}
-
-/**
- * acpi_release_memory - Release any mappings done to a memory region
- * @handle: Handle to namespace node
- * @res: Memory resource
- * @level: A level that terminates the search
- *
- * Walks through @handle and unmaps all SystemMemory Operation Regions that
- * overlap with @res and that have already been activated (mapped).
- *
- * This is a helper that allows drivers to place special requirements on memory
- * region that may overlap with operation regions, primarily allowing them to
- * safely map the region as non-cached memory.
- *
- * The unmapped Operation Regions will be automatically remapped next time they
- * are called, so the drivers do not need to do anything else.
- */
-acpi_status acpi_release_memory(acpi_handle handle, struct resource *res,
-				u32 level)
-{
-	if (!(res->flags & IORESOURCE_MEM))
-		return AE_TYPE;
-
-	return acpi_walk_namespace(ACPI_TYPE_REGION, handle, level,
-				   acpi_deactivate_mem_region, NULL, res, NULL);
-}
-EXPORT_SYMBOL_GPL(acpi_release_memory);
-
 /*
  * Let drivers know whether the resource checks are effective
  */
@@ -1600,19 +1547,18 @@ void acpi_os_delete_lock(acpi_spinlock handle)
 acpi_cpu_flags acpi_os_acquire_lock(acpi_spinlock lockp)
 	__acquires(lockp)
 {
-	acpi_cpu_flags flags;
-	spin_lock_irqsave(lockp, flags);
-	return flags;
+	spin_lock(lockp);
+	return 0;
 }
 
 /*
  * Release a spinlock. See above.
  */
 
-void acpi_os_release_lock(acpi_spinlock lockp, acpi_cpu_flags flags)
+void acpi_os_release_lock(acpi_spinlock lockp, acpi_cpu_flags not_used)
 	__releases(lockp)
 {
-	spin_unlock_irqrestore(lockp, flags);
+	spin_unlock(lockp);
 }
 
 #ifndef ACPI_USE_LOCAL_CACHE
@@ -1633,7 +1579,7 @@ void acpi_os_release_lock(acpi_spinlock lockp, acpi_cpu_flags flags)
  ******************************************************************************/
 
 acpi_status
-acpi_os_create_cache(char *name, u16 size, u16 depth, acpi_cache_t ** cache)
+acpi_os_create_cache(char *name, u16 size, u16 depth, acpi_cache_t **cache)
 {
 	*cache = kmem_cache_create(name, size, 0, 0, NULL);
 	if (*cache == NULL)
@@ -1654,10 +1600,10 @@ acpi_os_create_cache(char *name, u16 size, u16 depth, acpi_cache_t ** cache)
  *
  ******************************************************************************/
 
-acpi_status acpi_os_purge_cache(acpi_cache_t * cache)
+acpi_status acpi_os_purge_cache(acpi_cache_t *cache)
 {
 	kmem_cache_shrink(cache);
-	return (AE_OK);
+	return AE_OK;
 }
 
 /*******************************************************************************
@@ -1673,10 +1619,10 @@ acpi_status acpi_os_purge_cache(acpi_cache_t * cache)
  *
  ******************************************************************************/
 
-acpi_status acpi_os_delete_cache(acpi_cache_t * cache)
+acpi_status acpi_os_delete_cache(acpi_cache_t *cache)
 {
 	kmem_cache_destroy(cache);
-	return (AE_OK);
+	return AE_OK;
 }
 
 /*******************************************************************************
@@ -1693,17 +1639,17 @@ acpi_status acpi_os_delete_cache(acpi_cache_t * cache)
  *
  ******************************************************************************/
 
-acpi_status acpi_os_release_object(acpi_cache_t * cache, void *object)
+acpi_status acpi_os_release_object(acpi_cache_t *cache, void *object)
 {
 	kmem_cache_free(cache, object);
-	return (AE_OK);
+	return AE_OK;
 }
 #endif
 
 static int __init acpi_no_static_ssdt_setup(char *s)
 {
 	acpi_gbl_disable_ssdt_table_install = TRUE;
-	pr_info("ACPI: static SSDT installation disabled\n");
+	pr_info("Static SSDT installation disabled\n");
 
 	return 0;
 }
@@ -1712,8 +1658,7 @@ early_param("acpi_no_static_ssdt", acpi_no_static_ssdt_setup);
 
 static int __init acpi_disable_return_repair(char *s)
 {
-	printk(KERN_NOTICE PREFIX
-	       "ACPI: Predefined validation mechanism disabled\n");
+	pr_notice("Predefined validation mechanism disabled\n");
 	acpi_gbl_disable_auto_repair = TRUE;
 
 	return 1;
@@ -1725,17 +1670,22 @@ acpi_status __init acpi_os_initialize(void)
 {
 	acpi_os_map_generic_address(&acpi_gbl_FADT.xpm1a_event_block);
 	acpi_os_map_generic_address(&acpi_gbl_FADT.xpm1b_event_block);
-	acpi_os_map_generic_address(&acpi_gbl_FADT.xgpe0_block);
-	acpi_os_map_generic_address(&acpi_gbl_FADT.xgpe1_block);
+
+	acpi_gbl_xgpe0_block_logical_address =
+		(unsigned long)acpi_os_map_generic_address(&acpi_gbl_FADT.xgpe0_block);
+	acpi_gbl_xgpe1_block_logical_address =
+		(unsigned long)acpi_os_map_generic_address(&acpi_gbl_FADT.xgpe1_block);
+
 	if (acpi_gbl_FADT.flags & ACPI_FADT_RESET_REGISTER) {
 		/*
 		 * Use acpi_os_map_generic_address to pre-map the reset
 		 * register if it's in system memory.
 		 */
-		int rv;
+		void *rv;
 
 		rv = acpi_os_map_generic_address(&acpi_gbl_FADT.reset_register);
-		pr_debug(PREFIX "%s: map reset_reg status %d\n", __func__, rv);
+		pr_debug("%s: Reset register mapping %s\n", __func__,
+			 rv ? "successful" : "failed");
 	}
 	acpi_os_initialized = true;
 
@@ -1744,8 +1694,8 @@ acpi_status __init acpi_os_initialize(void)
 
 acpi_status __init acpi_os_initialize1(void)
 {
-	kacpid_wq = alloc_workqueue("kacpid", 0, 1);
-	kacpi_notify_wq = alloc_workqueue("kacpi_notify", 0, 1);
+	kacpid_wq = alloc_workqueue("kacpid", WQ_PERCPU, 1);
+	kacpi_notify_wq = alloc_workqueue("kacpi_notify", WQ_PERCPU, 0);
 	kacpi_hotplug_wq = alloc_ordered_workqueue("kacpi_hotplug", 0);
 	BUG_ON(!kacpid_wq);
 	BUG_ON(!kacpi_notify_wq);
@@ -1763,8 +1713,12 @@ acpi_status acpi_os_terminate(void)
 
 	acpi_os_unmap_generic_address(&acpi_gbl_FADT.xgpe1_block);
 	acpi_os_unmap_generic_address(&acpi_gbl_FADT.xgpe0_block);
+	acpi_gbl_xgpe0_block_logical_address = 0UL;
+	acpi_gbl_xgpe1_block_logical_address = 0UL;
+
 	acpi_os_unmap_generic_address(&acpi_gbl_FADT.xpm1b_event_block);
 	acpi_os_unmap_generic_address(&acpi_gbl_FADT.xpm1a_event_block);
+
 	if (acpi_gbl_FADT.flags & ACPI_FADT_RESET_REGISTER)
 		acpi_os_unmap_generic_address(&acpi_gbl_FADT.reset_register);
 
@@ -1779,6 +1733,7 @@ acpi_status acpi_os_prepare_sleep(u8 sleep_state, u32 pm1a_control,
 				  u32 pm1b_control)
 {
 	int rc = 0;
+
 	if (__acpi_os_prepare_sleep)
 		rc = __acpi_os_prepare_sleep(sleep_state,
 					     pm1a_control, pm1b_control);
@@ -1801,6 +1756,7 @@ acpi_status acpi_os_prepare_extended_sleep(u8 sleep_state, u32 val_a,
 				  u32 val_b)
 {
 	int rc = 0;
+
 	if (__acpi_os_prepare_extended_sleep)
 		rc = __acpi_os_prepare_extended_sleep(sleep_state,
 					     val_a, val_b);
diff --git a/drivers/acpi/pci_irq.c b/drivers/acpi/pci_irq.c
index dea8a60e18a4..ad81aa03fe2f 100644
--- a/drivers/acpi/pci_irq.c
+++ b/drivers/acpi/pci_irq.c
@@ -9,6 +9,7 @@
  *	Bjorn Helgaas <bjorn.helgaas@hp.com>
  */
 
+#define pr_fmt(fmt) "ACPI: PCI: " fmt
 
 #include <linux/dmi.h>
 #include <linux/kernel.h>
@@ -21,11 +22,7 @@
 #include <linux/acpi.h>
 #include <linux/slab.h>
 #include <linux/interrupt.h>
-
-#define PREFIX "ACPI: "
-
-#define _COMPONENT		ACPI_PCI_COMPONENT
-ACPI_MODULE_NAME("pci_irq");
+#include <linux/string_choices.h>
 
 struct acpi_prt_entry {
 	struct acpi_pci_id	id;
@@ -126,7 +123,7 @@ static void do_prt_fixups(struct acpi_prt_entry *entry,
 		    entry->pin == quirk->pin &&
 		    !strcmp(prt->source, quirk->source) &&
 		    strlen(prt->source) >= strlen(quirk->actual_source)) {
-			printk(KERN_WARNING PREFIX "firmware reports "
+			pr_warn("Firmware reports "
 				"%04x:%02x:%02x PCI INT %c connected to %s; "
 				"changing to %s\n",
 				entry->id.segment, entry->id.bus,
@@ -175,7 +172,7 @@ static int acpi_pci_irq_check_entry(acpi_handle handle, struct pci_dev *dev,
 	 * configure the IRQ assigned to this slot|dev|pin.  The 'source_index'
 	 * indicates which resource descriptor in the resource template (of
 	 * the link device) this interrupt is allocated from.
-	 * 
+	 *
 	 * NOTE: Don't query the Link Device for IRQ information at this time
 	 *       because Link Device enumeration may not have occurred yet
 	 *       (e.g. exists somewhere 'below' this _PRT entry in the ACPI
@@ -191,12 +188,9 @@ static int acpi_pci_irq_check_entry(acpi_handle handle, struct pci_dev *dev,
 	 * the IRQ value, which is hardwired to specific interrupt inputs on
 	 * the interrupt controller.
 	 */
-
-	ACPI_DEBUG_PRINT_RAW((ACPI_DB_INFO,
-			      "      %04x:%02x:%02x[%c] -> %s[%d]\n",
-			      entry->id.segment, entry->id.bus,
-			      entry->id.device, pin_name(entry->pin),
-			      prt->source, entry->index));
+	pr_debug("%04x:%02x:%02x[%c] -> %s[%d]\n",
+		 entry->id.segment, entry->id.bus, entry->id.device,
+		 pin_name(entry->pin), prt->source, entry->index);
 
 	*entry_ptr = entry;
 
@@ -295,7 +289,7 @@ static int acpi_reroute_boot_interrupt(struct pci_dev *dev,
 }
 #endif /* CONFIG_X86_IO_APIC */
 
-static struct acpi_prt_entry *acpi_pci_irq_lookup(struct pci_dev *dev, int pin)
+struct acpi_prt_entry *acpi_pci_irq_lookup(struct pci_dev *dev, int pin)
 {
 	struct acpi_prt_entry *entry = NULL;
 	struct pci_dev *bridge;
@@ -307,8 +301,7 @@ static struct acpi_prt_entry *acpi_pci_irq_lookup(struct pci_dev *dev, int pin)
 #ifdef CONFIG_X86_IO_APIC
 		acpi_reroute_boot_interrupt(dev, entry);
 #endif /* CONFIG_X86_IO_APIC */
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found %s[%c] _PRT entry\n",
-				  pci_name(dev), pin_name(pin)));
+		dev_dbg(&dev->dev, "Found [%c] _PRT entry\n", pin_name(pin));
 		return entry;
 	}
 
@@ -324,9 +317,7 @@ static struct acpi_prt_entry *acpi_pci_irq_lookup(struct pci_dev *dev, int pin)
 			/* PC card has the same IRQ as its cardbridge */
 			bridge_pin = bridge->pin;
 			if (!bridge_pin) {
-				ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-						  "No interrupt pin configured for device %s\n",
-						  pci_name(bridge)));
+				dev_dbg(&bridge->dev, "No interrupt pin configured\n");
 				return NULL;
 			}
 			pin = bridge_pin;
@@ -334,10 +325,8 @@ static struct acpi_prt_entry *acpi_pci_irq_lookup(struct pci_dev *dev, int pin)
 
 		ret = acpi_pci_irq_find_prt_entry(bridge, pin, &entry);
 		if (!ret && entry) {
-			ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-					 "Derived GSI for %s INT %c from %s\n",
-					 pci_name(dev), pin_name(orig_pin),
-					 pci_name(bridge)));
+			dev_dbg(&dev->dev, "Derived GSI INT %c from %s\n",
+				pin_name(orig_pin), pci_name(bridge));
 			return entry;
 		}
 
@@ -399,13 +388,15 @@ int acpi_pci_irq_enable(struct pci_dev *dev)
 	u8 pin;
 	int triggering = ACPI_LEVEL_SENSITIVE;
 	/*
-	 * On ARM systems with the GIC interrupt model, level interrupts
+	 * On ARM systems with the GIC interrupt model, or LoongArch
+	 * systems with the LPIC interrupt model, level interrupts
 	 * are always polarity high by specification; PCI legacy
 	 * IRQs lines are inverted before reaching the interrupt
 	 * controller and must therefore be considered active high
 	 * as default.
 	 */
-	int polarity = acpi_irq_model == ACPI_IRQ_MODEL_GIC ?
+	int polarity = acpi_irq_model == ACPI_IRQ_MODEL_GIC ||
+		       acpi_irq_model == ACPI_IRQ_MODEL_LPIC ?
 				      ACPI_ACTIVE_HIGH : ACPI_ACTIVE_LOW;
 	char *link = NULL;
 	char link_desc[16];
@@ -413,9 +404,7 @@ int acpi_pci_irq_enable(struct pci_dev *dev)
 
 	pin = dev->pin;
 	if (!pin) {
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-				  "No interrupt pin configured for device %s\n",
-				  pci_name(dev)));
+		dev_dbg(&dev->dev, "No interrupt pin configured\n");
 		return 0;
 	}
 
@@ -480,7 +469,7 @@ int acpi_pci_irq_enable(struct pci_dev *dev)
 	dev_dbg(&dev->dev, "PCI INT %c%s -> GSI %u (%s, %s) -> IRQ %d\n",
 		pin_name(pin), link_desc, gsi,
 		(triggering == ACPI_LEVEL_SENSITIVE) ? "level" : "edge",
-		(polarity == ACPI_ACTIVE_LOW) ? "low" : "high", dev->irq);
+		str_low_high(polarity == ACPI_ACTIVE_LOW), dev->irq);
 
 	kfree(entry);
 	return 0;
diff --git a/drivers/acpi/pci_link.c b/drivers/acpi/pci_link.c
index ed3d2182cf2c..bed7dc85612e 100644
--- a/drivers/acpi/pci_link.c
+++ b/drivers/acpi/pci_link.c
@@ -6,12 +6,14 @@
  *  Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
  *  Copyright (C) 2002       Dominik Brodowski <devel@brodo.de>
  *
- * TBD: 
- *      1. Support more than one IRQ resource entry per link device (index).
+ * TBD:
+ *	1. Support more than one IRQ resource entry per link device (index).
  *	2. Implement start/stop mechanism and use ACPI Bus Driver facilities
  *	   for IRQ management (e.g. start()->_SRS).
  */
 
+#define pr_fmt(fmt) "ACPI: PCI: " fmt
+
 #include <linux/syscore_ops.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
@@ -27,12 +29,8 @@
 
 #include "internal.h"
 
-#define _COMPONENT			ACPI_PCI_COMPONENT
-ACPI_MODULE_NAME("pci_link");
 #define ACPI_PCI_LINK_CLASS		"pci_irq_routing"
 #define ACPI_PCI_LINK_DEVICE_NAME	"PCI Interrupt Link"
-#define ACPI_PCI_LINK_FILE_INFO		"info"
-#define ACPI_PCI_LINK_FILE_STATUS	"state"
 #define ACPI_PCI_LINK_MAX_POSSIBLE	16
 
 static int acpi_pci_link_add(struct acpi_device *device,
@@ -87,6 +85,7 @@ static acpi_status acpi_pci_link_check_possible(struct acpi_resource *resource,
 						void *context)
 {
 	struct acpi_pci_link *link = context;
+	acpi_handle handle = link->device->handle;
 	u32 i;
 
 	switch (resource->type) {
@@ -96,18 +95,18 @@ static acpi_status acpi_pci_link_check_possible(struct acpi_resource *resource,
 	case ACPI_RESOURCE_TYPE_IRQ:
 		{
 			struct acpi_resource_irq *p = &resource->data.irq;
-			if (!p || !p->interrupt_count) {
-				ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-						  "Blank _PRS IRQ resource\n"));
+			if (!p->interrupt_count) {
+				acpi_handle_debug(handle,
+						  "Blank _PRS IRQ resource\n");
 				return AE_OK;
 			}
 			for (i = 0;
 			     (i < p->interrupt_count
 			      && i < ACPI_PCI_LINK_MAX_POSSIBLE); i++) {
 				if (!p->interrupts[i]) {
-					printk(KERN_WARNING PREFIX
-					       "Invalid _PRS IRQ %d\n",
-					       p->interrupts[i]);
+					acpi_handle_debug(handle,
+							  "Invalid _PRS IRQ %d\n",
+							  p->interrupts[i]);
 					continue;
 				}
 				link->irq.possible[i] = p->interrupts[i];
@@ -122,18 +121,18 @@ static acpi_status acpi_pci_link_check_possible(struct acpi_resource *resource,
 		{
 			struct acpi_resource_extended_irq *p =
 			    &resource->data.extended_irq;
-			if (!p || !p->interrupt_count) {
-				printk(KERN_WARNING PREFIX
-					      "Blank _PRS EXT IRQ resource\n");
+			if (!p->interrupt_count) {
+				acpi_handle_debug(handle,
+						  "Blank _PRS EXT IRQ resource\n");
 				return AE_OK;
 			}
 			for (i = 0;
 			     (i < p->interrupt_count
 			      && i < ACPI_PCI_LINK_MAX_POSSIBLE); i++) {
 				if (!p->interrupts[i]) {
-					printk(KERN_WARNING PREFIX
-					       "Invalid _PRS IRQ %d\n",
-					       p->interrupts[i]);
+					acpi_handle_debug(handle,
+							  "Invalid _PRS IRQ %d\n",
+							  p->interrupts[i]);
 					continue;
 				}
 				link->irq.possible[i] = p->interrupts[i];
@@ -145,8 +144,8 @@ static acpi_status acpi_pci_link_check_possible(struct acpi_resource *resource,
 			break;
 		}
 	default:
-		printk(KERN_ERR PREFIX "_PRS resource type 0x%x isn't an IRQ\n",
-		       resource->type);
+		acpi_handle_debug(handle, "_PRS resource type 0x%x is not IRQ\n",
+				  resource->type);
 		return AE_OK;
 	}
 
@@ -155,18 +154,18 @@ static acpi_status acpi_pci_link_check_possible(struct acpi_resource *resource,
 
 static int acpi_pci_link_get_possible(struct acpi_pci_link *link)
 {
+	acpi_handle handle = link->device->handle;
 	acpi_status status;
 
-	status = acpi_walk_resources(link->device->handle, METHOD_NAME__PRS,
+	status = acpi_walk_resources(handle, METHOD_NAME__PRS,
 				     acpi_pci_link_check_possible, link);
 	if (ACPI_FAILURE(status)) {
-		acpi_handle_debug(link->device->handle, "_PRS not present or invalid");
+		acpi_handle_debug(handle, "_PRS not present or invalid");
 		return 0;
 	}
 
-	ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-			  "Found %d possible IRQs\n",
-			  link->irq.possible_count));
+	acpi_handle_debug(handle, "Found %d possible IRQs\n",
+			  link->irq.possible_count);
 
 	return 0;
 }
@@ -183,13 +182,12 @@ static acpi_status acpi_pci_link_check_current(struct acpi_resource *resource,
 	case ACPI_RESOURCE_TYPE_IRQ:
 		{
 			struct acpi_resource_irq *p = &resource->data.irq;
-			if (!p || !p->interrupt_count) {
+			if (!p->interrupt_count) {
 				/*
 				 * IRQ descriptors may have no IRQ# bits set,
-				 * particularly those those w/ _STA disabled
+				 * particularly those w/ _STA disabled
 				 */
-				ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-						  "Blank _CRS IRQ resource\n"));
+				pr_debug("Blank _CRS IRQ resource\n");
 				return AE_OK;
 			}
 			*irq = p->interrupts[0];
@@ -199,13 +197,12 @@ static acpi_status acpi_pci_link_check_current(struct acpi_resource *resource,
 		{
 			struct acpi_resource_extended_irq *p =
 			    &resource->data.extended_irq;
-			if (!p || !p->interrupt_count) {
+			if (!p->interrupt_count) {
 				/*
 				 * extended IRQ descriptors must
 				 * return at least 1 IRQ
 				 */
-				printk(KERN_WARNING PREFIX
-					      "Blank _CRS EXT IRQ resource\n");
+				pr_debug("Blank _CRS EXT IRQ resource\n");
 				return AE_OK;
 			}
 			*irq = p->interrupts[0];
@@ -213,8 +210,8 @@ static acpi_status acpi_pci_link_check_current(struct acpi_resource *resource,
 		}
 		break;
 	default:
-		printk(KERN_ERR PREFIX "_CRS resource type 0x%x isn't an IRQ\n",
-		       resource->type);
+		pr_debug("_CRS resource type 0x%x is not IRQ\n",
+			 resource->type);
 		return AE_OK;
 	}
 
@@ -230,8 +227,9 @@ static acpi_status acpi_pci_link_check_current(struct acpi_resource *resource,
  */
 static int acpi_pci_link_get_current(struct acpi_pci_link *link)
 {
-	int result = 0;
+	acpi_handle handle = link->device->handle;
 	acpi_status status;
+	int result = 0;
 	int irq = 0;
 
 	link->irq.active = 0;
@@ -241,36 +239,36 @@ static int acpi_pci_link_get_current(struct acpi_pci_link *link)
 		/* Query _STA, set link->device->status */
 		result = acpi_bus_get_status(link->device);
 		if (result) {
-			printk(KERN_ERR PREFIX "Unable to read status\n");
+			acpi_handle_err(handle, "Unable to read status\n");
 			goto end;
 		}
 
 		if (!link->device->status.enabled) {
-			ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Link disabled\n"));
+			acpi_handle_debug(handle, "Link disabled\n");
 			return 0;
 		}
 	}
 
-	/* 
-	 * Query and parse _CRS to get the current IRQ assignment. 
+	/*
+	 * Query and parse _CRS to get the current IRQ assignment.
 	 */
 
-	status = acpi_walk_resources(link->device->handle, METHOD_NAME__CRS,
+	status = acpi_walk_resources(handle, METHOD_NAME__CRS,
 				     acpi_pci_link_check_current, &irq);
 	if (ACPI_FAILURE(status)) {
-		ACPI_EXCEPTION((AE_INFO, status, "Evaluating _CRS"));
+		acpi_evaluation_failure_warn(handle, "_CRS", status);
 		result = -ENODEV;
 		goto end;
 	}
 
 	if (acpi_strict && !irq) {
-		printk(KERN_ERR PREFIX "_CRS returned 0\n");
+		acpi_handle_err(handle, "_CRS returned 0\n");
 		result = -ENODEV;
 	}
 
 	link->irq.active = irq;
 
-	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Link at IRQ %d \n", link->irq.active));
+	acpi_handle_debug(handle, "Link at IRQ %d\n", link->irq.active);
 
       end:
 	return result;
@@ -278,13 +276,14 @@ static int acpi_pci_link_get_current(struct acpi_pci_link *link)
 
 static int acpi_pci_link_set(struct acpi_pci_link *link, int irq)
 {
-	int result;
-	acpi_status status;
 	struct {
 		struct acpi_resource res;
 		struct acpi_resource end;
 	} *resource;
 	struct acpi_buffer buffer = { 0, NULL };
+	acpi_handle handle = link->device->handle;
+	acpi_status status;
+	int result;
 
 	if (!irq)
 		return -EINVAL;
@@ -331,7 +330,8 @@ static int acpi_pci_link_set(struct acpi_pci_link *link, int irq)
 		/* ignore resource_source, it's optional */
 		break;
 	default:
-		printk(KERN_ERR PREFIX "Invalid Resource_type %d\n", link->irq.resource_type);
+		acpi_handle_err(handle, "Invalid resource type %d\n",
+				link->irq.resource_type);
 		result = -EINVAL;
 		goto end;
 
@@ -344,7 +344,7 @@ static int acpi_pci_link_set(struct acpi_pci_link *link, int irq)
 
 	/* check for total failure */
 	if (ACPI_FAILURE(status)) {
-		ACPI_EXCEPTION((AE_INFO, status, "Evaluating _SRS"));
+		acpi_evaluation_failure_warn(handle, "_SRS", status);
 		result = -ENODEV;
 		goto end;
 	}
@@ -352,15 +352,11 @@ static int acpi_pci_link_set(struct acpi_pci_link *link, int irq)
 	/* Query _STA, set device->status */
 	result = acpi_bus_get_status(link->device);
 	if (result) {
-		printk(KERN_ERR PREFIX "Unable to read status\n");
+		acpi_handle_err(handle, "Unable to read status\n");
 		goto end;
 	}
-	if (!link->device->status.enabled) {
-		printk(KERN_WARNING PREFIX
-			      "%s [%s] disabled and referenced, BIOS bug\n",
-			      acpi_device_name(link->device),
-			      acpi_device_bid(link->device));
-	}
+	if (!link->device->status.enabled)
+		acpi_handle_warn(handle, "Disabled and referenced, BIOS bug\n");
 
 	/* Query _CRS, set link->irq.active */
 	result = acpi_pci_link_get_current(link);
@@ -377,14 +373,12 @@ static int acpi_pci_link_set(struct acpi_pci_link *link, int irq)
 		 * policy: when _CRS doesn't return what we just _SRS
 		 * assume _SRS worked and override _CRS value.
 		 */
-		printk(KERN_WARNING PREFIX
-			      "%s [%s] BIOS reported IRQ %d, using IRQ %d\n",
-			      acpi_device_name(link->device),
-			      acpi_device_bid(link->device), link->irq.active, irq);
+		acpi_handle_warn(handle, "BIOS reported IRQ %d, using IRQ %d\n",
+				 link->irq.active, irq);
 		link->irq.active = irq;
 	}
 
-	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Set IRQ %d\n", link->irq.active));
+	acpi_handle_debug(handle, "Set IRQ %d\n", link->irq.active);
 
       end:
 	kfree(resource);
@@ -398,7 +392,7 @@ static int acpi_pci_link_set(struct acpi_pci_link *link, int irq)
 /*
  * "acpi_irq_balance" (default in APIC mode) enables ACPI to use PIC Interrupt
  * Link Devices to move the PIRQs around to minimize sharing.
- * 
+ *
  * "acpi_irq_nobalance" (default in PIC mode) tells ACPI not to move any PIC IRQs
  * that the BIOS has already set to active.  This is necessary because
  * ACPI has no automatic means of knowing what ISA IRQs are used.  Note that
@@ -416,7 +410,7 @@ static int acpi_pci_link_set(struct acpi_pci_link *link, int irq)
  *
  * Note that PCI IRQ routers have a list of possible IRQs,
  * which may not include the IRQs this table says are available.
- * 
+ *
  * Since this heuristic can't tell the difference between a link
  * that no device will attach to, vs. a link which may be shared
  * by multiple active devices -- it is not optimal.
@@ -533,6 +527,7 @@ static int acpi_irq_balance = -1;	/* 0: static, 1: balance */
 
 static int acpi_pci_link_allocate(struct acpi_pci_link *link)
 {
+	acpi_handle handle = link->device->handle;
 	int irq;
 	int i;
 
@@ -555,8 +550,8 @@ static int acpi_pci_link_allocate(struct acpi_pci_link *link)
 	 */
 	if (i == link->irq.possible_count) {
 		if (acpi_strict)
-			printk(KERN_WARNING PREFIX "_CRS %d not found"
-				      " in _PRS\n", link->irq.active);
+			acpi_handle_warn(handle, "_CRS %d not found in _PRS\n",
+					 link->irq.active);
 		link->irq.active = 0;
 	}
 
@@ -580,28 +575,23 @@ static int acpi_pci_link_allocate(struct acpi_pci_link *link)
 		}
 	}
 	if (acpi_irq_get_penalty(irq) >= PIRQ_PENALTY_ISA_ALWAYS) {
-		printk(KERN_ERR PREFIX "No IRQ available for %s [%s]. "
-			    "Try pci=noacpi or acpi=off\n",
-			    acpi_device_name(link->device),
-			    acpi_device_bid(link->device));
+		acpi_handle_err(handle,
+				"No IRQ available. Try pci=noacpi or acpi=off\n");
 		return -ENODEV;
 	}
 
 	/* Attempt to enable the link device at this IRQ. */
 	if (acpi_pci_link_set(link, irq)) {
-		printk(KERN_ERR PREFIX "Unable to set IRQ for %s [%s]. "
-			    "Try pci=noacpi or acpi=off\n",
-			    acpi_device_name(link->device),
-			    acpi_device_bid(link->device));
+		acpi_handle_err(handle,
+				"Unable to set IRQ. Try pci=noacpi or acpi=off\n");
 		return -ENODEV;
 	} else {
 		if (link->irq.active < ACPI_MAX_ISA_IRQS)
 			acpi_isa_irq_penalty[link->irq.active] +=
 				PIRQ_PENALTY_PCI_USING;
 
-		pr_info("%s [%s] enabled at IRQ %d\n",
-		       acpi_device_name(link->device),
-		       acpi_device_bid(link->device), link->irq.active);
+		acpi_handle_info(handle, "Enabled at IRQ %d\n",
+				 link->irq.active);
 	}
 
 	link->irq.initialized = 1;
@@ -616,25 +606,23 @@ static int acpi_pci_link_allocate(struct acpi_pci_link *link)
 int acpi_pci_link_allocate_irq(acpi_handle handle, int index, int *triggering,
 			       int *polarity, char **name)
 {
-	int result;
-	struct acpi_device *device;
+	struct acpi_device *device = acpi_fetch_acpi_dev(handle);
 	struct acpi_pci_link *link;
 
-	result = acpi_bus_get_device(handle, &device);
-	if (result) {
-		printk(KERN_ERR PREFIX "Invalid link device\n");
+	if (!device) {
+		acpi_handle_err(handle, "Invalid link device\n");
 		return -1;
 	}
 
 	link = acpi_driver_data(device);
 	if (!link) {
-		printk(KERN_ERR PREFIX "Invalid link context\n");
+		acpi_handle_err(handle, "Invalid link context\n");
 		return -1;
 	}
 
 	/* TBD: Support multiple index (IRQ) entries per Link Device */
 	if (index) {
-		printk(KERN_ERR PREFIX "Invalid index %d\n", index);
+		acpi_handle_err(handle, "Invalid index %d\n", index);
 		return -1;
 	}
 
@@ -646,7 +634,7 @@ int acpi_pci_link_allocate_irq(acpi_handle handle, int index, int *triggering,
 
 	if (!link->irq.active) {
 		mutex_unlock(&acpi_link_lock);
-		printk(KERN_ERR PREFIX "Link active IRQ is 0!\n");
+		acpi_handle_err(handle, "Link active IRQ is 0!\n");
 		return -1;
 	}
 	link->refcnt++;
@@ -658,9 +646,7 @@ int acpi_pci_link_allocate_irq(acpi_handle handle, int index, int *triggering,
 		*polarity = link->irq.polarity;
 	if (name)
 		*name = acpi_device_bid(link->device);
-	ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-			  "Link %s is referenced\n",
-			  acpi_device_bid(link->device)));
+	acpi_handle_debug(handle, "Link is referenced\n");
 	return link->irq.active;
 }
 
@@ -670,26 +656,24 @@ int acpi_pci_link_allocate_irq(acpi_handle handle, int index, int *triggering,
  */
 int acpi_pci_link_free_irq(acpi_handle handle)
 {
-	struct acpi_device *device;
+	struct acpi_device *device = acpi_fetch_acpi_dev(handle);
 	struct acpi_pci_link *link;
-	acpi_status result;
 
-	result = acpi_bus_get_device(handle, &device);
-	if (result) {
-		printk(KERN_ERR PREFIX "Invalid link device\n");
+	if (!device) {
+		acpi_handle_err(handle, "Invalid link device\n");
 		return -1;
 	}
 
 	link = acpi_driver_data(device);
 	if (!link) {
-		printk(KERN_ERR PREFIX "Invalid link context\n");
+		acpi_handle_err(handle, "Invalid link context\n");
 		return -1;
 	}
 
 	mutex_lock(&acpi_link_lock);
 	if (!link->irq.initialized) {
 		mutex_unlock(&acpi_link_lock);
-		printk(KERN_ERR PREFIX "Link isn't initialized\n");
+		acpi_handle_err(handle, "Link isn't initialized\n");
 		return -1;
 	}
 #ifdef	FUTURE_USE
@@ -704,9 +688,7 @@ int acpi_pci_link_free_irq(acpi_handle handle)
 	 */
 	link->refcnt--;
 #endif
-	ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-			  "Link %s is dereferenced\n",
-			  acpi_device_bid(link->device)));
+	acpi_handle_debug(handle, "Link is dereferenced\n");
 
 	if (link->refcnt == 0)
 		acpi_evaluate_object(link->device->handle, "_DIS", NULL, NULL);
@@ -722,18 +704,18 @@ int acpi_pci_link_free_irq(acpi_handle handle)
 static int acpi_pci_link_add(struct acpi_device *device,
 			     const struct acpi_device_id *not_used)
 {
-	int result;
+	acpi_handle handle = device->handle;
 	struct acpi_pci_link *link;
+	int result;
 	int i;
-	int found = 0;
 
 	link = kzalloc(sizeof(struct acpi_pci_link), GFP_KERNEL);
 	if (!link)
 		return -ENOMEM;
 
 	link->device = device;
-	strcpy(acpi_device_name(device), ACPI_PCI_LINK_DEVICE_NAME);
-	strcpy(acpi_device_class(device), ACPI_PCI_LINK_CLASS);
+	strscpy(acpi_device_name(device), ACPI_PCI_LINK_DEVICE_NAME);
+	strscpy(acpi_device_class(device), ACPI_PCI_LINK_CLASS);
 	device->driver_data = link;
 
 	mutex_lock(&acpi_link_lock);
@@ -744,36 +726,30 @@ static int acpi_pci_link_add(struct acpi_device *device,
 	/* query and set link->irq.active */
 	acpi_pci_link_get_current(link);
 
-	printk(KERN_INFO PREFIX "%s [%s] (IRQs", acpi_device_name(device),
-	       acpi_device_bid(device));
+	pr_info("Interrupt link %s configured for IRQ %d\n",
+		acpi_device_bid(device), link->irq.active);
+
 	for (i = 0; i < link->irq.possible_count; i++) {
-		if (link->irq.active == link->irq.possible[i]) {
-			printk(KERN_CONT " *%d", link->irq.possible[i]);
-			found = 1;
-		} else
-			printk(KERN_CONT " %d", link->irq.possible[i]);
+		if (link->irq.active != link->irq.possible[i])
+			acpi_handle_debug(handle, "Possible IRQ %d\n",
+					  link->irq.possible[i]);
 	}
 
-	printk(KERN_CONT ")");
-
-	if (!found)
-		printk(KERN_CONT " *%d", link->irq.active);
-
 	if (!link->device->status.enabled)
-		printk(KERN_CONT ", disabled.");
-
-	printk(KERN_CONT "\n");
+		pr_info("Interrupt link %s disabled\n", acpi_device_bid(device));
 
 	list_add_tail(&link->list, &acpi_link_list);
 
       end:
 	/* disable all links -- to be activated on use */
-	acpi_evaluate_object(device->handle, "_DIS", NULL, NULL);
+	acpi_evaluate_object(handle, "_DIS", NULL, NULL);
 	mutex_unlock(&acpi_link_lock);
 
 	if (result)
 		kfree(link);
 
+	acpi_dev_clear_dependencies(device);
+
 	return result < 0 ? result : 1;
 }
 
@@ -785,7 +761,7 @@ static int acpi_pci_link_resume(struct acpi_pci_link *link)
 	return 0;
 }
 
-static void irqrouter_resume(void)
+static void irqrouter_resume(void *data)
 {
 	struct acpi_pci_link *link;
 
@@ -912,10 +888,14 @@ static int __init acpi_irq_balance_set(char *str)
 
 __setup("acpi_irq_balance", acpi_irq_balance_set);
 
-static struct syscore_ops irqrouter_syscore_ops = {
+static const struct syscore_ops irqrouter_syscore_ops = {
 	.resume = irqrouter_resume,
 };
 
+static struct syscore irqrouter_syscore = {
+	.ops = &irqrouter_syscore_ops,
+};
+
 void __init acpi_pci_link_init(void)
 {
 	if (acpi_noirq)
@@ -928,6 +908,6 @@ void __init acpi_pci_link_init(void)
 		else
 			acpi_irq_balance = 0;
 	}
-	register_syscore_ops(&irqrouter_syscore_ops);
+	register_syscore(&irqrouter_syscore);
 	acpi_scan_add_handler(&pci_link_handler);
 }
diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index 6b347d9920cc..58e10a980114 100644
--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
@@ -29,7 +29,7 @@ struct mcfg_fixup {
 	u32 oem_revision;
 	u16 segment;
 	struct resource bus_range;
-	struct pci_ecam_ops *ops;
+	const struct pci_ecam_ops *ops;
 	struct resource cfgres;
 };
 
@@ -41,6 +41,8 @@ struct mcfg_fixup {
 static struct mcfg_fixup mcfg_quirks[] = {
 /*	{ OEM_ID, OEM_TABLE_ID, REV, SEGMENT, BUS_RANGE, ops, cfgres }, */
 
+#ifdef CONFIG_ARM64
+
 #define AL_ECAM(table_id, rev, seg, ops) \
 	{ "AMAZON", table_id, rev, seg, MCFG_BUS_ANY, ops }
 
@@ -116,6 +118,13 @@ static struct mcfg_fixup mcfg_quirks[] = {
 	THUNDER_ECAM_QUIRK(2, 12),
 	THUNDER_ECAM_QUIRK(2, 13),
 
+	{ "NVIDIA", "TEGRA194", 1, 0, MCFG_BUS_ANY, &tegra194_pcie_ops},
+	{ "NVIDIA", "TEGRA194", 1, 1, MCFG_BUS_ANY, &tegra194_pcie_ops},
+	{ "NVIDIA", "TEGRA194", 1, 2, MCFG_BUS_ANY, &tegra194_pcie_ops},
+	{ "NVIDIA", "TEGRA194", 1, 3, MCFG_BUS_ANY, &tegra194_pcie_ops},
+	{ "NVIDIA", "TEGRA194", 1, 4, MCFG_BUS_ANY, &tegra194_pcie_ops},
+	{ "NVIDIA", "TEGRA194", 1, 5, MCFG_BUS_ANY, &tegra194_pcie_ops},
+
 #define XGENE_V1_ECAM_MCFG(rev, seg) \
 	{"APM   ", "XGENE   ", rev, seg, MCFG_BUS_ANY, \
 		&xgene_v1_pcie_ecam_ops }
@@ -142,6 +151,49 @@ static struct mcfg_fixup mcfg_quirks[] = {
 	XGENE_V2_ECAM_MCFG(4, 0),
 	XGENE_V2_ECAM_MCFG(4, 1),
 	XGENE_V2_ECAM_MCFG(4, 2),
+
+#define ALTRA_ECAM_QUIRK(rev, seg) \
+	{ "Ampere", "Altra   ", rev, seg, MCFG_BUS_ANY, &pci_32b_read_ops }
+
+	ALTRA_ECAM_QUIRK(1, 0),
+	ALTRA_ECAM_QUIRK(1, 1),
+	ALTRA_ECAM_QUIRK(1, 2),
+	ALTRA_ECAM_QUIRK(1, 3),
+	ALTRA_ECAM_QUIRK(1, 4),
+	ALTRA_ECAM_QUIRK(1, 5),
+	ALTRA_ECAM_QUIRK(1, 6),
+	ALTRA_ECAM_QUIRK(1, 7),
+	ALTRA_ECAM_QUIRK(1, 8),
+	ALTRA_ECAM_QUIRK(1, 9),
+	ALTRA_ECAM_QUIRK(1, 10),
+	ALTRA_ECAM_QUIRK(1, 11),
+	ALTRA_ECAM_QUIRK(1, 12),
+	ALTRA_ECAM_QUIRK(1, 13),
+	ALTRA_ECAM_QUIRK(1, 14),
+	ALTRA_ECAM_QUIRK(1, 15),
+#endif /* ARM64 */
+
+#ifdef CONFIG_LOONGARCH
+#define LOONGSON_ECAM_MCFG(table_id, seg) \
+	{ "LOONGS", table_id, 1, seg, MCFG_BUS_ANY, &loongson_pci_ecam_ops }
+
+	LOONGSON_ECAM_MCFG("\0", 0),
+	LOONGSON_ECAM_MCFG("LOONGSON", 0),
+	LOONGSON_ECAM_MCFG("\0", 1),
+	LOONGSON_ECAM_MCFG("LOONGSON", 1),
+	LOONGSON_ECAM_MCFG("\0", 2),
+	LOONGSON_ECAM_MCFG("LOONGSON", 2),
+	LOONGSON_ECAM_MCFG("\0", 3),
+	LOONGSON_ECAM_MCFG("LOONGSON", 3),
+	LOONGSON_ECAM_MCFG("\0", 4),
+	LOONGSON_ECAM_MCFG("LOONGSON", 4),
+	LOONGSON_ECAM_MCFG("\0", 5),
+	LOONGSON_ECAM_MCFG("LOONGSON", 5),
+	LOONGSON_ECAM_MCFG("\0", 6),
+	LOONGSON_ECAM_MCFG("LOONGSON", 6),
+	LOONGSON_ECAM_MCFG("\0", 7),
+	LOONGSON_ECAM_MCFG("LOONGSON", 7),
+#endif /* LOONGARCH */
 };
 
 static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
@@ -153,7 +205,7 @@ static int pci_mcfg_quirk_matches(struct mcfg_fixup *f, u16 segment,
 {
 	if (!memcmp(f->oem_id, mcfg_oem_id, ACPI_OEM_ID_SIZE) &&
 	    !memcmp(f->oem_table_id, mcfg_oem_table_id,
-	            ACPI_OEM_TABLE_ID_SIZE) &&
+		    ACPI_OEM_TABLE_ID_SIZE) &&
 	    f->oem_revision == mcfg_oem_revision &&
 	    f->segment == segment &&
 	    resource_contains(&f->bus_range, bus_range))
@@ -165,7 +217,7 @@ static int pci_mcfg_quirk_matches(struct mcfg_fixup *f, u16 segment,
 
 static void pci_mcfg_apply_quirks(struct acpi_pci_root *root,
 				  struct resource *cfgres,
-				  struct pci_ecam_ops **ecam_ops)
+				  const struct pci_ecam_ops **ecam_ops)
 {
 #ifdef CONFIG_PCI_QUIRKS
 	u16 segment = root->segment;
@@ -191,9 +243,9 @@ static void pci_mcfg_apply_quirks(struct acpi_pci_root *root,
 static LIST_HEAD(pci_mcfg_list);
 
 int pci_mcfg_lookup(struct acpi_pci_root *root, struct resource *cfgres,
-		    struct pci_ecam_ops **ecam_ops)
+		    const struct pci_ecam_ops **ecam_ops)
 {
-	struct pci_ecam_ops *ops = &pci_generic_ecam_ops;
+	const struct pci_ecam_ops *ops = &pci_generic_ecam_ops;
 	struct resource *bus_res = &root->secondary;
 	u16 seg = root->segment;
 	struct mcfg_entry *e;
@@ -280,5 +332,5 @@ void __init pci_mmcfg_late_init(void)
 {
 	int err = acpi_table_parse(ACPI_SIG_MCFG, pci_mcfg_parse);
 	if (err)
-		pr_err("Failed to parse MCFG (%d)\n", err);
+		pr_debug("Failed to parse MCFG (%d)\n", err);
 }
diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c
index ac8ad6cb82aa..74ade4160314 100644
--- a/drivers/acpi/pci_root.c
+++ b/drivers/acpi/pci_root.c
@@ -6,6 +6,8 @@
  *  Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
  */
 
+#define pr_fmt(fmt) "ACPI: " fmt
+
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/init.h>
@@ -20,12 +22,8 @@
 #include <linux/slab.h>
 #include <linux/dmi.h>
 #include <linux/platform_data/x86/apple.h>
-#include <acpi/apei.h>	/* for acpi_hest_init() */
-
 #include "internal.h"
 
-#define _COMPONENT		ACPI_PCI_COMPONENT
-ACPI_MODULE_NAME("pci_root");
 #define ACPI_PCI_ROOT_CLASS		"pci_bridge"
 #define ACPI_PCI_ROOT_DEVICE_NAME	"PCI Root Bridge"
 static int acpi_pci_root_add(struct acpi_device *device,
@@ -58,22 +56,19 @@ static struct acpi_scan_handler pci_root_handler = {
 	},
 };
 
-static DEFINE_MUTEX(osc_lock);
-
 /**
  * acpi_is_root_bridge - determine whether an ACPI CA node is a PCI root bridge
- * @handle - the ACPI CA node in question.
+ * @handle:  the ACPI CA node in question.
  *
  * Note: we could make this API take a struct acpi_device * instead, but
  * for now, it's more convenient to operate on an acpi_handle.
  */
 int acpi_is_root_bridge(acpi_handle handle)
 {
+	struct acpi_device *device = acpi_fetch_acpi_dev(handle);
 	int ret;
-	struct acpi_device *device;
 
-	ret = acpi_bus_get_device(handle, &device);
-	if (ret)
+	if (!device)
 		return 0;
 
 	ret = acpi_match_device_ids(device, root_device_ids);
@@ -145,6 +140,17 @@ static struct pci_osc_bit_struct pci_osc_control_bit[] = {
 	{ OSC_PCI_EXPRESS_DPC_CONTROL, "DPC" },
 };
 
+static struct pci_osc_bit_struct cxl_osc_support_bit[] = {
+	{ OSC_CXL_1_1_PORT_REG_ACCESS_SUPPORT, "CXL11PortRegAccess" },
+	{ OSC_CXL_2_0_PORT_DEV_REG_ACCESS_SUPPORT, "CXL20PortDevRegAccess" },
+	{ OSC_CXL_PROTOCOL_ERR_REPORTING_SUPPORT, "CXLProtocolErrorReporting" },
+	{ OSC_CXL_NATIVE_HP_SUPPORT, "CXLNativeHotPlug" },
+};
+
+static struct pci_osc_bit_struct cxl_osc_control_bit[] = {
+	{ OSC_CXL_ERROR_REPORTING_CONTROL, "CXLMemErrorReporting" },
+};
+
 static void decode_osc_bits(struct acpi_pci_root *root, char *msg, u32 word,
 			    struct pci_osc_bit_struct *table, int size)
 {
@@ -173,73 +179,112 @@ static void decode_osc_control(struct acpi_pci_root *root, char *msg, u32 word)
 			ARRAY_SIZE(pci_osc_control_bit));
 }
 
+static void decode_cxl_osc_support(struct acpi_pci_root *root, char *msg, u32 word)
+{
+	decode_osc_bits(root, msg, word, cxl_osc_support_bit,
+			ARRAY_SIZE(cxl_osc_support_bit));
+}
+
+static void decode_cxl_osc_control(struct acpi_pci_root *root, char *msg, u32 word)
+{
+	decode_osc_bits(root, msg, word, cxl_osc_control_bit,
+			ARRAY_SIZE(cxl_osc_control_bit));
+}
+
+static inline bool is_pcie(struct acpi_pci_root *root)
+{
+	return root->bridge_type == ACPI_BRIDGE_TYPE_PCIE;
+}
+
+static inline bool is_cxl(struct acpi_pci_root *root)
+{
+	return root->bridge_type == ACPI_BRIDGE_TYPE_CXL;
+}
+
 static u8 pci_osc_uuid_str[] = "33DB4D5B-1FF7-401C-9657-7441C03DD766";
+static u8 cxl_osc_uuid_str[] = "68F2D50B-C469-4d8A-BD3D-941A103FD3FC";
+
+static char *to_uuid(struct acpi_pci_root *root)
+{
+	if (is_cxl(root))
+		return cxl_osc_uuid_str;
+	return pci_osc_uuid_str;
+}
 
-static acpi_status acpi_pci_run_osc(acpi_handle handle,
-				    const u32 *capbuf, u32 *retval)
+static int cap_length(struct acpi_pci_root *root)
+{
+	if (is_cxl(root))
+		return sizeof(u32) * OSC_CXL_CAPABILITY_DWORDS;
+	return sizeof(u32) * OSC_PCI_CAPABILITY_DWORDS;
+}
+
+static acpi_status acpi_pci_run_osc(struct acpi_pci_root *root,
+				    const u32 *capbuf, u32 *pci_control,
+				    u32 *cxl_control)
 {
 	struct acpi_osc_context context = {
-		.uuid_str = pci_osc_uuid_str,
+		.uuid_str = to_uuid(root),
 		.rev = 1,
-		.cap.length = 12,
+		.cap.length = cap_length(root),
 		.cap.pointer = (void *)capbuf,
 	};
 	acpi_status status;
 
-	status = acpi_run_osc(handle, &context);
+	status = acpi_run_osc(root->device->handle, &context);
 	if (ACPI_SUCCESS(status)) {
-		*retval = *((u32 *)(context.ret.pointer + 8));
+		*pci_control = acpi_osc_ctx_get_pci_control(&context);
+		if (is_cxl(root))
+			*cxl_control = acpi_osc_ctx_get_cxl_control(&context);
 		kfree(context.ret.pointer);
 	}
 	return status;
 }
 
-static acpi_status acpi_pci_query_osc(struct acpi_pci_root *root,
-					u32 support,
-					u32 *control)
+static acpi_status acpi_pci_query_osc(struct acpi_pci_root *root, u32 support,
+				      u32 *control, u32 cxl_support,
+				      u32 *cxl_control)
 {
 	acpi_status status;
-	u32 result, capbuf[3];
+	u32 pci_result, cxl_result, capbuf[OSC_CXL_CAPABILITY_DWORDS];
 
-	support &= OSC_PCI_SUPPORT_MASKS;
 	support |= root->osc_support_set;
 
 	capbuf[OSC_QUERY_DWORD] = OSC_QUERY_ENABLE;
 	capbuf[OSC_SUPPORT_DWORD] = support;
-	if (control) {
-		*control &= OSC_PCI_CONTROL_MASKS;
-		capbuf[OSC_CONTROL_DWORD] = *control | root->osc_control_set;
-	} else {
-		/* Run _OSC query only with existing controls. */
-		capbuf[OSC_CONTROL_DWORD] = root->osc_control_set;
+	capbuf[OSC_CONTROL_DWORD] = *control | root->osc_control_set;
+
+	if (is_cxl(root)) {
+		cxl_support |= root->osc_ext_support_set;
+		capbuf[OSC_EXT_SUPPORT_DWORD] = cxl_support;
+		capbuf[OSC_EXT_CONTROL_DWORD] = *cxl_control | root->osc_ext_control_set;
 	}
 
-	status = acpi_pci_run_osc(root->device->handle, capbuf, &result);
+retry:
+	status = acpi_pci_run_osc(root, capbuf, &pci_result, &cxl_result);
 	if (ACPI_SUCCESS(status)) {
 		root->osc_support_set = support;
-		if (control)
-			*control = result;
+		*control = pci_result;
+		if (is_cxl(root)) {
+			root->osc_ext_support_set = cxl_support;
+			*cxl_control = cxl_result;
+		}
+	} else if (is_cxl(root)) {
+		/*
+		 * CXL _OSC is optional on CXL 1.1 hosts. Fall back to PCIe _OSC
+		 * upon any failure using CXL _OSC.
+		 */
+		root->bridge_type = ACPI_BRIDGE_TYPE_PCIE;
+		goto retry;
 	}
 	return status;
 }
 
-static acpi_status acpi_pci_osc_support(struct acpi_pci_root *root, u32 flags)
-{
-	acpi_status status;
-
-	mutex_lock(&osc_lock);
-	status = acpi_pci_query_osc(root, flags, NULL);
-	mutex_unlock(&osc_lock);
-	return status;
-}
-
 struct acpi_pci_root *acpi_pci_find_root(acpi_handle handle)
 {
+	struct acpi_device *device = acpi_fetch_acpi_dev(handle);
 	struct acpi_pci_root *root;
-	struct acpi_device *device;
 
-	if (acpi_bus_get_device(handle, &device) ||
-	    acpi_match_device_ids(device, root_device_ids))
+	if (!device || acpi_match_device_ids(device, root_device_ids))
 		return NULL;
 
 	root = acpi_driver_data(device);
@@ -248,11 +293,6 @@ struct acpi_pci_root *acpi_pci_find_root(acpi_handle handle)
 }
 EXPORT_SYMBOL_GPL(acpi_pci_find_root);
 
-struct acpi_handle_node {
-	struct list_head node;
-	acpi_handle handle;
-};
-
 /**
  * acpi_get_pci_dev - convert ACPI CA handle to struct pci_dev
  * @handle: the handle in question
@@ -267,76 +307,26 @@ struct acpi_handle_node {
  */
 struct pci_dev *acpi_get_pci_dev(acpi_handle handle)
 {
-	int dev, fn;
-	unsigned long long adr;
-	acpi_status status;
-	acpi_handle phandle;
-	struct pci_bus *pbus;
-	struct pci_dev *pdev = NULL;
-	struct acpi_handle_node *node, *tmp;
-	struct acpi_pci_root *root;
-	LIST_HEAD(device_list);
-
-	/*
-	 * Walk up the ACPI CA namespace until we reach a PCI root bridge.
-	 */
-	phandle = handle;
-	while (!acpi_is_root_bridge(phandle)) {
-		node = kzalloc(sizeof(struct acpi_handle_node), GFP_KERNEL);
-		if (!node)
-			goto out;
-
-		INIT_LIST_HEAD(&node->node);
-		node->handle = phandle;
-		list_add(&node->node, &device_list);
+	struct acpi_device *adev = acpi_fetch_acpi_dev(handle);
+	struct acpi_device_physical_node *pn;
+	struct pci_dev *pci_dev = NULL;
 
-		status = acpi_get_parent(phandle, &phandle);
-		if (ACPI_FAILURE(status))
-			goto out;
-	}
-
-	root = acpi_pci_find_root(phandle);
-	if (!root)
-		goto out;
-
-	pbus = root->bus;
+	if (!adev)
+		return NULL;
 
-	/*
-	 * Now, walk back down the PCI device tree until we return to our
-	 * original handle. Assumes that everything between the PCI root
-	 * bridge and the device we're looking for must be a P2P bridge.
-	 */
-	list_for_each_entry(node, &device_list, node) {
-		acpi_handle hnd = node->handle;
-		status = acpi_evaluate_integer(hnd, "_ADR", NULL, &adr);
-		if (ACPI_FAILURE(status))
-			goto out;
-		dev = (adr >> 16) & 0xffff;
-		fn  = adr & 0xffff;
+	mutex_lock(&adev->physical_node_lock);
 
-		pdev = pci_get_slot(pbus, PCI_DEVFN(dev, fn));
-		if (!pdev || hnd == handle)
-			break;
-
-		pbus = pdev->subordinate;
-		pci_dev_put(pdev);
-
-		/*
-		 * This function may be called for a non-PCI device that has a
-		 * PCI parent (eg. a disk under a PCI SATA controller).  In that
-		 * case pdev->subordinate will be NULL for the parent.
-		 */
-		if (!pbus) {
-			dev_dbg(&pdev->dev, "Not a PCI-to-PCI bridge\n");
-			pdev = NULL;
+	list_for_each_entry(pn, &adev->physical_node_list, node) {
+		if (dev_is_pci(pn->dev)) {
+			get_device(pn->dev);
+			pci_dev = to_pci_dev(pn->dev);
 			break;
 		}
 	}
-out:
-	list_for_each_entry_safe(node, tmp, &device_list, node)
-		kfree(node);
 
-	return pdev;
+	mutex_unlock(&adev->physical_node_lock);
+
+	return pci_dev;
 }
 EXPORT_SYMBOL_GPL(acpi_get_pci_dev);
 
@@ -344,7 +334,9 @@ EXPORT_SYMBOL_GPL(acpi_get_pci_dev);
  * acpi_pci_osc_control_set - Request control of PCI root _OSC features.
  * @handle: ACPI handle of a PCI root bridge (or PCIe Root Complex).
  * @mask: Mask of _OSC bits to request control of, place to store control mask.
- * @req: Mask of _OSC bits the control of is essential to the caller.
+ * @support: _OSC supported capability.
+ * @cxl_mask: Mask of CXL _OSC control bits, place to store control mask.
+ * @cxl_support: CXL _OSC supported capability.
  *
  * Run _OSC query for @mask and if that is successful, compare the returned
  * mask of control bits with @req.  If all of the @req bits are set in the
@@ -355,80 +347,89 @@ EXPORT_SYMBOL_GPL(acpi_get_pci_dev);
  * _OSC bits the BIOS has granted control of, but its contents are meaningless
  * on failure.
  **/
-acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask, u32 req)
+static acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask,
+					    u32 support, u32 *cxl_mask,
+					    u32 cxl_support)
 {
+	u32 req = OSC_PCI_EXPRESS_CAPABILITY_CONTROL;
 	struct acpi_pci_root *root;
-	acpi_status status = AE_OK;
-	u32 ctrl, capbuf[3];
+	acpi_status status;
+	u32 ctrl, cxl_ctrl = 0, capbuf[OSC_CXL_CAPABILITY_DWORDS];
 
 	if (!mask)
 		return AE_BAD_PARAMETER;
 
-	ctrl = *mask & OSC_PCI_CONTROL_MASKS;
-	if ((ctrl & req) != req)
-		return AE_TYPE;
-
 	root = acpi_pci_find_root(handle);
 	if (!root)
 		return AE_NOT_EXIST;
 
-	mutex_lock(&osc_lock);
+	ctrl   = *mask;
+	*mask |= root->osc_control_set;
 
-	*mask = ctrl | root->osc_control_set;
-	/* No need to evaluate _OSC if the control was already granted. */
-	if ((root->osc_control_set & ctrl) == ctrl)
-		goto out;
+	if (is_cxl(root)) {
+		cxl_ctrl = *cxl_mask;
+		*cxl_mask |= root->osc_ext_control_set;
+	}
 
 	/* Need to check the available controls bits before requesting them. */
-	while (*mask) {
-		status = acpi_pci_query_osc(root, root->osc_support_set, mask);
+	do {
+		u32 pci_missing = 0, cxl_missing = 0;
+
+		status = acpi_pci_query_osc(root, support, mask, cxl_support,
+					    cxl_mask);
 		if (ACPI_FAILURE(status))
-			goto out;
-		if (ctrl == *mask)
-			break;
-		decode_osc_control(root, "platform does not support",
-				   ctrl & ~(*mask));
+			return status;
+		if (is_cxl(root)) {
+			if (ctrl == *mask && cxl_ctrl == *cxl_mask)
+				break;
+			pci_missing = ctrl & ~(*mask);
+			cxl_missing = cxl_ctrl & ~(*cxl_mask);
+		} else {
+			if (ctrl == *mask)
+				break;
+			pci_missing = ctrl & ~(*mask);
+		}
+		if (pci_missing)
+			decode_osc_control(root, "platform does not support",
+					   pci_missing);
+		if (cxl_missing)
+			decode_cxl_osc_control(root, "CXL platform does not support",
+					   cxl_missing);
 		ctrl = *mask;
-	}
+		cxl_ctrl = *cxl_mask;
+	} while (*mask || *cxl_mask);
+
+	/* No need to request _OSC if the control was already granted. */
+	if ((root->osc_control_set & ctrl) == ctrl &&
+	    (root->osc_ext_control_set & cxl_ctrl) == cxl_ctrl)
+		return AE_OK;
 
 	if ((ctrl & req) != req) {
 		decode_osc_control(root, "not requesting control; platform does not support",
 				   req & ~(ctrl));
-		status = AE_SUPPORT;
-		goto out;
+		return AE_SUPPORT;
 	}
 
 	capbuf[OSC_QUERY_DWORD] = 0;
 	capbuf[OSC_SUPPORT_DWORD] = root->osc_support_set;
 	capbuf[OSC_CONTROL_DWORD] = ctrl;
-	status = acpi_pci_run_osc(handle, capbuf, mask);
-	if (ACPI_SUCCESS(status))
-		root->osc_control_set = *mask;
-out:
-	mutex_unlock(&osc_lock);
-	return status;
+	if (is_cxl(root)) {
+		capbuf[OSC_EXT_SUPPORT_DWORD] = root->osc_ext_support_set;
+		capbuf[OSC_EXT_CONTROL_DWORD] = cxl_ctrl;
+	}
+
+	status = acpi_pci_run_osc(root, capbuf, mask, cxl_mask);
+	if (ACPI_FAILURE(status))
+		return status;
+
+	root->osc_control_set = *mask;
+	root->osc_ext_control_set = *cxl_mask;
+	return AE_OK;
 }
-EXPORT_SYMBOL(acpi_pci_osc_control_set);
 
-static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm,
-				 bool is_pcie)
+static u32 calculate_support(void)
 {
-	u32 support, control, requested;
-	acpi_status status;
-	struct acpi_device *device = root->device;
-	acpi_handle handle = device->handle;
-
-	/*
-	 * Apple always return failure on _OSC calls when _OSI("Darwin") has
-	 * been called successfully. We know the feature set supported by the
-	 * platform, so avoid calling _OSC at all
-	 */
-	if (x86_apple_machine) {
-		root->osc_control_set = ~OSC_PCI_EXPRESS_PME_CONTROL;
-		decode_osc_control(root, "OS assumes control of",
-				   root->osc_control_set);
-		return;
-	}
+	u32 support;
 
 	/*
 	 * All supported architectures that use ACPI have support for
@@ -445,31 +446,60 @@ static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm,
 	if (IS_ENABLED(CONFIG_PCIE_EDR))
 		support |= OSC_PCI_EDR_SUPPORT;
 
-	decode_osc_support(root, "OS supports", support);
-	status = acpi_pci_osc_support(root, support);
-	if (ACPI_FAILURE(status)) {
-		*no_aspm = 1;
+	return support;
+}
 
-		/* _OSC is optional for PCI host bridges */
-		if ((status == AE_NOT_FOUND) && !is_pcie)
-			return;
+/*
+ * Background on hotplug support, and making it depend on only
+ * CONFIG_HOTPLUG_PCI_PCIE vs. also considering CONFIG_MEMORY_HOTPLUG:
+ *
+ * CONFIG_ACPI_HOTPLUG_MEMORY does depend on CONFIG_MEMORY_HOTPLUG, but
+ * there is no existing _OSC for memory hotplug support. The reason is that
+ * ACPI memory hotplug requires the OS to acknowledge / coordinate with
+ * memory plug events via a scan handler. On the CXL side the equivalent
+ * would be if Linux supported the Mechanical Retention Lock [1], or
+ * otherwise had some coordination for the driver of a PCI device
+ * undergoing hotplug to be consulted on whether the hotplug should
+ * proceed or not.
+ *
+ * The concern is that if Linux says no to supporting CXL hotplug then
+ * the BIOS may say no to giving the OS hotplug control of any other PCIe
+ * device. So the question here is not whether hotplug is enabled, it's
+ * whether it is handled natively by the at all OS, and if
+ * CONFIG_HOTPLUG_PCI_PCIE is enabled then the answer is "yes".
+ *
+ * Otherwise, the plan for CXL coordinated remove, since the kernel does
+ * not support blocking hotplug, is to require the memory device to be
+ * disabled before hotplug is attempted. When CONFIG_MEMORY_HOTPLUG is
+ * disabled that step will fail and the remove attempt cancelled by the
+ * user. If that is not honored and the card is removed anyway then it
+ * does not matter if CONFIG_MEMORY_HOTPLUG is enabled or not, it will
+ * cause a crash and other badness.
+ *
+ * Therefore, just say yes to CXL hotplug and require removal to
+ * be coordinated by userspace unless and until the kernel grows better
+ * mechanisms for doing "managed" removal of devices in consultation with
+ * the driver.
+ *
+ * [1]: https://lore.kernel.org/all/20201122014203.4706-1-ashok.raj@intel.com/
+ */
+static u32 calculate_cxl_support(void)
+{
+	u32 support;
 
-		dev_info(&device->dev, "_OSC failed (%s)%s\n",
-			 acpi_format_exception(status),
-			 pcie_aspm_support_enabled() ? "; disabling ASPM" : "");
-		return;
-	}
+	support = OSC_CXL_2_0_PORT_DEV_REG_ACCESS_SUPPORT;
+	support |= OSC_CXL_1_1_PORT_REG_ACCESS_SUPPORT;
+	if (pci_aer_available())
+		support |= OSC_CXL_PROTOCOL_ERR_REPORTING_SUPPORT;
+	if (IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE))
+		support |= OSC_CXL_NATIVE_HP_SUPPORT;
 
-	if (pcie_ports_disabled) {
-		dev_info(&device->dev, "PCIe port services disabled; not requesting _OSC control\n");
-		return;
-	}
+	return support;
+}
 
-	if ((support & ACPI_PCIE_REQ_SUPPORT) != ACPI_PCIE_REQ_SUPPORT) {
-		decode_osc_support(root, "not requesting OS control; OS requires",
-				   ACPI_PCIE_REQ_SUPPORT);
-		return;
-	}
+static u32 calculate_control(void)
+{
+	u32 control;
 
 	control = OSC_PCI_EXPRESS_CAPABILITY_CONTROL
 		| OSC_PCI_EXPRESS_PME_CONTROL;
@@ -483,13 +513,8 @@ static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm,
 	if (IS_ENABLED(CONFIG_HOTPLUG_PCI_SHPC))
 		control |= OSC_PCI_SHPC_NATIVE_HP_CONTROL;
 
-	if (pci_aer_available()) {
-		if (aer_acpi_firmware_first())
-			dev_info(&device->dev,
-				 "PCIe AER handled by firmware\n");
-		else
-			control |= OSC_PCI_EXPRESS_AER_CONTROL;
-	}
+	if (pci_aer_available())
+		control |= OSC_PCI_EXPRESS_AER_CONTROL;
 
 	/*
 	 * Per the Downstream Port Containment Related Enhancements ECN to
@@ -500,11 +525,79 @@ static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm,
 	if (IS_ENABLED(CONFIG_PCIE_DPC) && IS_ENABLED(CONFIG_PCIE_EDR))
 		control |= OSC_PCI_EXPRESS_DPC_CONTROL;
 
-	requested = control;
-	status = acpi_pci_osc_control_set(handle, &control,
-					  OSC_PCI_EXPRESS_CAPABILITY_CONTROL);
+	return control;
+}
+
+static u32 calculate_cxl_control(void)
+{
+	u32 control = 0;
+
+	if (IS_ENABLED(CONFIG_MEMORY_FAILURE))
+		control |= OSC_CXL_ERROR_REPORTING_CONTROL;
+
+	return control;
+}
+
+static bool os_control_query_checks(struct acpi_pci_root *root, u32 support)
+{
+	struct acpi_device *device = root->device;
+
+	if (pcie_ports_disabled) {
+		dev_info(&device->dev, "PCIe port services disabled; not requesting _OSC control\n");
+		return false;
+	}
+
+	if ((support & ACPI_PCIE_REQ_SUPPORT) != ACPI_PCIE_REQ_SUPPORT) {
+		decode_osc_support(root, "not requesting OS control; OS requires",
+				   ACPI_PCIE_REQ_SUPPORT);
+		return false;
+	}
+
+	return true;
+}
+
+static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm)
+{
+	u32 support, control = 0, requested = 0;
+	u32 cxl_support = 0, cxl_control = 0, cxl_requested = 0;
+	acpi_status status;
+	struct acpi_device *device = root->device;
+	acpi_handle handle = device->handle;
+
+	/*
+	 * Apple always return failure on _OSC calls when _OSI("Darwin") has
+	 * been called successfully. We know the feature set supported by the
+	 * platform, so avoid calling _OSC at all
+	 */
+	if (x86_apple_machine) {
+		root->osc_control_set = ~OSC_PCI_EXPRESS_PME_CONTROL;
+		decode_osc_control(root, "OS assumes control of",
+				   root->osc_control_set);
+		return;
+	}
+
+	support = calculate_support();
+
+	decode_osc_support(root, "OS supports", support);
+
+	if (os_control_query_checks(root, support))
+		requested = control = calculate_control();
+
+	if (is_cxl(root)) {
+		cxl_support = calculate_cxl_support();
+		decode_cxl_osc_support(root, "OS supports", cxl_support);
+		cxl_requested = cxl_control = calculate_cxl_control();
+	}
+
+	status = acpi_pci_osc_control_set(handle, &control, support,
+					  &cxl_control, cxl_support);
 	if (ACPI_SUCCESS(status)) {
-		decode_osc_control(root, "OS now controls", control);
+		if (control)
+			decode_osc_control(root, "OS now controls", control);
+		if (cxl_control)
+			decode_cxl_osc_control(root, "OS now controls",
+					   cxl_control);
+
 		if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_ASPM) {
 			/*
 			 * We have ASPM control, but the FADT indicates that
@@ -515,11 +608,6 @@ static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm,
 			*no_aspm = 1;
 		}
 	} else {
-		decode_osc_control(root, "OS requested", requested);
-		decode_osc_control(root, "platform willing to grant", control);
-		dev_info(&device->dev, "_OSC failed (%s); disabling ASPM\n",
-			acpi_format_exception(status));
-
 		/*
 		 * We want to disable ASPM here, but aspm_disabled
 		 * needs to remain in its state from boot so that we
@@ -528,6 +616,23 @@ static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm,
 		 * root scan.
 		 */
 		*no_aspm = 1;
+
+		/* _OSC is optional for PCI host bridges */
+		if (status == AE_NOT_FOUND && !is_pcie(root))
+			return;
+
+		if (control) {
+			decode_osc_control(root, "OS requested", requested);
+			decode_osc_control(root, "platform willing to grant", control);
+		}
+		if (cxl_control) {
+			decode_cxl_osc_control(root, "OS requested", cxl_requested);
+			decode_cxl_osc_control(root, "platform willing to grant",
+					   cxl_control);
+		}
+
+		dev_info(&device->dev, "_OSC: platform retains control of PCIe features (%s)\n",
+			 acpi_format_exception(status));
 	}
 }
 
@@ -541,7 +646,7 @@ static int acpi_pci_root_add(struct acpi_device *device,
 	acpi_handle handle = device->handle;
 	int no_aspm = 0;
 	bool hotadd = system_state == SYSTEM_RUNNING;
-	bool is_pcie;
+	const char *acpi_hid;
 
 	root = kzalloc(sizeof(struct acpi_pci_root), GFP_KERNEL);
 	if (!root)
@@ -584,8 +689,8 @@ static int acpi_pci_root_add(struct acpi_device *device,
 
 	root->device = device;
 	root->segment = segment & 0xFFFF;
-	strcpy(acpi_device_name(device), ACPI_PCI_ROOT_DEVICE_NAME);
-	strcpy(acpi_device_class(device), ACPI_PCI_ROOT_CLASS);
+	strscpy(acpi_device_name(device), ACPI_PCI_ROOT_DEVICE_NAME);
+	strscpy(acpi_device_class(device), ACPI_PCI_ROOT_CLASS);
 	device->driver_data = root;
 
 	if (hotadd && dmar_device_add(handle)) {
@@ -593,14 +698,21 @@ static int acpi_pci_root_add(struct acpi_device *device,
 		goto end;
 	}
 
-	pr_info(PREFIX "%s [%s] (domain %04x %pR)\n",
+	pr_info("%s [%s] (domain %04x %pR)\n",
 	       acpi_device_name(device), acpi_device_bid(device),
 	       root->segment, &root->secondary);
 
 	root->mcfg_addr = acpi_pci_root_get_mcfg_addr(handle);
 
-	is_pcie = strcmp(acpi_device_hid(device), "PNP0A08") == 0;
-	negotiate_os_control(root, &no_aspm, is_pcie);
+	acpi_hid = acpi_device_hid(root->device);
+	if (strcmp(acpi_hid, "PNP0A08") == 0)
+		root->bridge_type = ACPI_BRIDGE_TYPE_PCIE;
+	else if (strcmp(acpi_hid, "ACPI0016") == 0)
+		root->bridge_type = ACPI_BRIDGE_TYPE_CXL;
+	else
+		dev_dbg(&device->dev, "Assuming non-PCIe host bridge\n");
+
+	negotiate_os_control(root, &no_aspm);
 
 	/*
 	 * TBD: Need PCI interface for enumeration/configuration of roots.
@@ -729,9 +841,7 @@ static void acpi_pci_root_validate_resources(struct device *dev,
 			 * our resources no longer match the ACPI _CRS, but
 			 * the kernel resource tree doesn't allow overlaps.
 			 */
-			if (resource_overlaps(res1, res2)) {
-				res2->start = min(res1->start, res2->start);
-				res2->end = max(res1->end, res2->end);
+			if (resource_union(res1, res2, res2)) {
 				dev_info(dev, "host bridge window expanded to %pR; %pR ignored\n",
 					 res2, res1);
 				free = true;
@@ -748,7 +858,7 @@ next:
 	}
 }
 
-static void acpi_pci_root_remap_iospace(struct fwnode_handle *fwnode,
+static void acpi_pci_root_remap_iospace(const struct fwnode_handle *fwnode,
 			struct resource_entry *entry)
 {
 #ifdef PCI_IOBASE
@@ -893,7 +1003,6 @@ struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root,
 	int node = acpi_get_node(device->handle);
 	struct pci_bus *bus;
 	struct pci_host_bridge *host_bridge;
-	union acpi_object *obj;
 
 	info->root = root;
 	info->bridge = device;
@@ -932,16 +1041,10 @@ struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root,
 	if (!(root->osc_control_set & OSC_PCI_EXPRESS_DPC_CONTROL))
 		host_bridge->native_dpc = 0;
 
-	/*
-	 * Evaluate the "PCI Boot Configuration" _DSM Function.  If it
-	 * exists and returns 0, we must preserve any PCI resource
-	 * assignments made by firmware for this host bridge.
-	 */
-	obj = acpi_evaluate_dsm(ACPI_HANDLE(bus->bridge), &pci_acpi_dsm_guid, 1,
-	                        IGNORE_PCI_BOOT_CONFIG_DSM, NULL);
-	if (obj && obj->type == ACPI_TYPE_INTEGER && obj->integer.value == 0)
-		host_bridge->preserve_config = 1;
-	ACPI_FREE(obj);
+	if (!(root->osc_ext_control_set & OSC_CXL_ERROR_REPORTING_CONTROL))
+		host_bridge->native_cxl_error = 0;
+
+	acpi_dev_power_up_children_with_adr(device);
 
 	pci_scan_child_bus(bus);
 	pci_set_host_bridge_release(host_bridge, acpi_pci_root_release_info,
@@ -957,7 +1060,6 @@ out_release_info:
 
 void __init acpi_pci_root_init(void)
 {
-	acpi_hest_init();
 	if (acpi_pci_disabled)
 		return;
 
diff --git a/drivers/acpi/pci_slot.c b/drivers/acpi/pci_slot.c
index ca2461d1bf14..741bcc9d6d6a 100644
--- a/drivers/acpi/pci_slot.c
+++ b/drivers/acpi/pci_slot.c
@@ -28,9 +28,6 @@
 
 static int check_sta_before_sun;
 
-#define _COMPONENT		ACPI_PCI_COMPONENT
-ACPI_MODULE_NAME("pci_slot");
-
 #define SLOT_NAME_SIZE 21		/* Inspired by #define in acpiphp.h */
 
 struct acpi_pci_slot {
@@ -114,7 +111,7 @@ register_slot(acpi_handle handle, u32 lvl, void *context, void **rv)
 	snprintf(name, sizeof(name), "%llu", sun);
 	pci_slot = pci_create_slot(pci_bus, device, name, NULL);
 	if (IS_ERR(pci_slot)) {
-		pr_err("pci_create_slot returned %ld\n", PTR_ERR(pci_slot));
+		pr_err("pci_create_slot returned %pe\n", pci_slot);
 		kfree(slot);
 		return AE_OK;
 	}
diff --git a/drivers/acpi/pfr_telemetry.c b/drivers/acpi/pfr_telemetry.c
new file mode 100644
index 000000000000..32bdf8cbe8f2
--- /dev/null
+++ b/drivers/acpi/pfr_telemetry.c
@@ -0,0 +1,430 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ACPI Platform Firmware Runtime Telemetry driver
+ *
+ * Copyright (C) 2021 Intel Corporation
+ * Author: Chen Yu <yu.c.chen@intel.com>
+ *
+ * This driver allows user space to fetch telemetry data from the
+ * firmware with the help of the Platform Firmware Runtime Telemetry
+ * interface.
+ */
+#include <linux/acpi.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/file.h>
+#include <linux/fs.h>
+#include <linux/miscdevice.h>
+#include <linux/module.h>
+#include <linux/mm.h>
+#include <linux/platform_device.h>
+#include <linux/string.h>
+#include <linux/uaccess.h>
+#include <linux/uio.h>
+#include <linux/uuid.h>
+
+#include <uapi/linux/pfrut.h>
+
+#define PFRT_LOG_EXEC_IDX	0
+#define PFRT_LOG_HISTORY_IDX	1
+
+#define PFRT_LOG_ERR		0
+#define PFRT_LOG_WARN	1
+#define PFRT_LOG_INFO	2
+#define PFRT_LOG_VERB	4
+
+#define PFRT_FUNC_SET_LEV		1
+#define PFRT_FUNC_GET_LEV		2
+#define PFRT_FUNC_GET_DATA		3
+
+#define PFRT_REVID_1		1
+#define PFRT_REVID_2		2
+#define PFRT_DEFAULT_REV_ID	PFRT_REVID_1
+
+enum log_index {
+	LOG_STATUS_IDX = 0,
+	LOG_EXT_STATUS_IDX = 1,
+	LOG_MAX_SZ_IDX = 2,
+	LOG_CHUNK1_LO_IDX = 3,
+	LOG_CHUNK1_HI_IDX = 4,
+	LOG_CHUNK1_SZ_IDX = 5,
+	LOG_CHUNK2_LO_IDX = 6,
+	LOG_CHUNK2_HI_IDX = 7,
+	LOG_CHUNK2_SZ_IDX = 8,
+	LOG_ROLLOVER_CNT_IDX = 9,
+	LOG_RESET_CNT_IDX = 10,
+	LOG_NR_IDX
+};
+
+struct pfrt_log_device {
+	int index;
+	struct pfrt_log_info info;
+	struct device *parent_dev;
+	struct miscdevice miscdev;
+};
+
+/* pfrt_guid is the parameter for _DSM method */
+static const guid_t pfrt_log_guid =
+	GUID_INIT(0x75191659, 0x8178, 0x4D9D, 0xB8, 0x8F, 0xAC, 0x5E,
+		  0x5E, 0x93, 0xE8, 0xBF);
+
+static DEFINE_IDA(pfrt_log_ida);
+
+static inline struct pfrt_log_device *to_pfrt_log_dev(struct file *file)
+{
+	return container_of(file->private_data, struct pfrt_log_device, miscdev);
+}
+
+static int get_pfrt_log_data_info(struct pfrt_log_data_info *data_info,
+				  struct pfrt_log_device *pfrt_log_dev)
+{
+	acpi_handle handle = ACPI_HANDLE(pfrt_log_dev->parent_dev);
+	union acpi_object *out_obj, in_obj, in_buf;
+	int ret = -EBUSY;
+
+	memset(data_info, 0, sizeof(*data_info));
+	memset(&in_obj, 0, sizeof(in_obj));
+	memset(&in_buf, 0, sizeof(in_buf));
+	in_obj.type = ACPI_TYPE_PACKAGE;
+	in_obj.package.count = 1;
+	in_obj.package.elements = &in_buf;
+	in_buf.type = ACPI_TYPE_INTEGER;
+	in_buf.integer.value = pfrt_log_dev->info.log_type;
+
+	out_obj = acpi_evaluate_dsm_typed(handle, &pfrt_log_guid,
+					  pfrt_log_dev->info.log_revid, PFRT_FUNC_GET_DATA,
+					  &in_obj, ACPI_TYPE_PACKAGE);
+	if (!out_obj)
+		return -EINVAL;
+
+	if (out_obj->package.count < LOG_NR_IDX ||
+	    out_obj->package.elements[LOG_STATUS_IDX].type != ACPI_TYPE_INTEGER ||
+	    out_obj->package.elements[LOG_EXT_STATUS_IDX].type != ACPI_TYPE_INTEGER ||
+	    out_obj->package.elements[LOG_MAX_SZ_IDX].type != ACPI_TYPE_INTEGER ||
+	    out_obj->package.elements[LOG_CHUNK1_LO_IDX].type != ACPI_TYPE_INTEGER ||
+	    out_obj->package.elements[LOG_CHUNK1_HI_IDX].type != ACPI_TYPE_INTEGER ||
+	    out_obj->package.elements[LOG_CHUNK1_SZ_IDX].type != ACPI_TYPE_INTEGER ||
+	    out_obj->package.elements[LOG_CHUNK2_LO_IDX].type != ACPI_TYPE_INTEGER ||
+	    out_obj->package.elements[LOG_CHUNK2_HI_IDX].type != ACPI_TYPE_INTEGER ||
+	    out_obj->package.elements[LOG_CHUNK2_SZ_IDX].type != ACPI_TYPE_INTEGER ||
+	    out_obj->package.elements[LOG_ROLLOVER_CNT_IDX].type != ACPI_TYPE_INTEGER ||
+	    out_obj->package.elements[LOG_RESET_CNT_IDX].type != ACPI_TYPE_INTEGER)
+		goto free_acpi_buffer;
+
+	data_info->status = out_obj->package.elements[LOG_STATUS_IDX].integer.value;
+	data_info->ext_status =
+		out_obj->package.elements[LOG_EXT_STATUS_IDX].integer.value;
+	if (data_info->status != DSM_SUCCEED) {
+		dev_dbg(pfrt_log_dev->parent_dev, "Error Status:%d\n", data_info->status);
+		dev_dbg(pfrt_log_dev->parent_dev, "Error Extend Status:%d\n",
+			data_info->ext_status);
+		goto free_acpi_buffer;
+	}
+
+	data_info->max_data_size =
+		out_obj->package.elements[LOG_MAX_SZ_IDX].integer.value;
+	data_info->chunk1_addr_lo =
+		out_obj->package.elements[LOG_CHUNK1_LO_IDX].integer.value;
+	data_info->chunk1_addr_hi =
+		out_obj->package.elements[LOG_CHUNK1_HI_IDX].integer.value;
+	data_info->chunk1_size =
+		out_obj->package.elements[LOG_CHUNK1_SZ_IDX].integer.value;
+	data_info->chunk2_addr_lo =
+		out_obj->package.elements[LOG_CHUNK2_LO_IDX].integer.value;
+	data_info->chunk2_addr_hi =
+		out_obj->package.elements[LOG_CHUNK2_HI_IDX].integer.value;
+	data_info->chunk2_size =
+		out_obj->package.elements[LOG_CHUNK2_SZ_IDX].integer.value;
+	data_info->rollover_cnt =
+		out_obj->package.elements[LOG_ROLLOVER_CNT_IDX].integer.value;
+	data_info->reset_cnt =
+		out_obj->package.elements[LOG_RESET_CNT_IDX].integer.value;
+
+	ret = 0;
+
+free_acpi_buffer:
+	ACPI_FREE(out_obj);
+
+	return ret;
+}
+
+static int set_pfrt_log_level(int level, struct pfrt_log_device *pfrt_log_dev)
+{
+	acpi_handle handle = ACPI_HANDLE(pfrt_log_dev->parent_dev);
+	union acpi_object *out_obj, *obj, in_obj, in_buf;
+	enum pfru_dsm_status status, ext_status;
+	int ret = 0;
+
+	memset(&in_obj, 0, sizeof(in_obj));
+	memset(&in_buf, 0, sizeof(in_buf));
+	in_obj.type = ACPI_TYPE_PACKAGE;
+	in_obj.package.count = 1;
+	in_obj.package.elements = &in_buf;
+	in_buf.type = ACPI_TYPE_INTEGER;
+	in_buf.integer.value = level;
+
+	out_obj = acpi_evaluate_dsm_typed(handle, &pfrt_log_guid,
+					  pfrt_log_dev->info.log_revid, PFRT_FUNC_SET_LEV,
+					  &in_obj, ACPI_TYPE_PACKAGE);
+	if (!out_obj)
+		return -EINVAL;
+
+	obj = &out_obj->package.elements[0];
+	status = obj->integer.value;
+	if (status != DSM_SUCCEED) {
+		obj = &out_obj->package.elements[1];
+		ext_status = obj->integer.value;
+		dev_dbg(pfrt_log_dev->parent_dev, "Error Status:%d\n", status);
+		dev_dbg(pfrt_log_dev->parent_dev, "Error Extend Status:%d\n", ext_status);
+		ret = -EBUSY;
+	}
+
+	ACPI_FREE(out_obj);
+
+	return ret;
+}
+
+static int get_pfrt_log_level(struct pfrt_log_device *pfrt_log_dev)
+{
+	acpi_handle handle = ACPI_HANDLE(pfrt_log_dev->parent_dev);
+	union acpi_object *out_obj, *obj;
+	enum pfru_dsm_status status, ext_status;
+	int ret = -EBUSY;
+
+	out_obj = acpi_evaluate_dsm_typed(handle, &pfrt_log_guid,
+					  pfrt_log_dev->info.log_revid, PFRT_FUNC_GET_LEV,
+					  NULL, ACPI_TYPE_PACKAGE);
+	if (!out_obj)
+		return -EINVAL;
+
+	obj = &out_obj->package.elements[0];
+	if (obj->type != ACPI_TYPE_INTEGER)
+		goto free_acpi_buffer;
+
+	status = obj->integer.value;
+	if (status != DSM_SUCCEED) {
+		obj = &out_obj->package.elements[1];
+		ext_status = obj->integer.value;
+		dev_dbg(pfrt_log_dev->parent_dev, "Error Status:%d\n", status);
+		dev_dbg(pfrt_log_dev->parent_dev, "Error Extend Status:%d\n", ext_status);
+		goto free_acpi_buffer;
+	}
+
+	obj = &out_obj->package.elements[2];
+	if (obj->type != ACPI_TYPE_INTEGER)
+		goto free_acpi_buffer;
+
+	ret = obj->integer.value;
+
+free_acpi_buffer:
+	ACPI_FREE(out_obj);
+
+	return ret;
+}
+
+static int valid_log_level(u32 level)
+{
+	return level == PFRT_LOG_ERR || level == PFRT_LOG_WARN ||
+	       level == PFRT_LOG_INFO || level == PFRT_LOG_VERB;
+}
+
+static int valid_log_type(u32 type)
+{
+	return type == PFRT_LOG_EXEC_IDX || type == PFRT_LOG_HISTORY_IDX;
+}
+
+static inline int valid_log_revid(u32 id)
+{
+	return id == PFRT_REVID_1 || id == PFRT_REVID_2;
+}
+
+static long pfrt_log_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
+{
+	struct pfrt_log_device *pfrt_log_dev = to_pfrt_log_dev(file);
+	struct pfrt_log_data_info data_info;
+	struct pfrt_log_info info;
+	void __user *p;
+	int ret = 0;
+
+	p = (void __user *)arg;
+
+	switch (cmd) {
+	case PFRT_LOG_IOC_SET_INFO:
+		if (copy_from_user(&info, p, sizeof(info)))
+			return -EFAULT;
+
+		if (valid_log_revid(info.log_revid))
+			pfrt_log_dev->info.log_revid = info.log_revid;
+
+		if (valid_log_level(info.log_level)) {
+			ret = set_pfrt_log_level(info.log_level, pfrt_log_dev);
+			if (ret < 0)
+				return ret;
+
+			pfrt_log_dev->info.log_level = info.log_level;
+		}
+
+		if (valid_log_type(info.log_type))
+			pfrt_log_dev->info.log_type = info.log_type;
+
+		return 0;
+
+	case PFRT_LOG_IOC_GET_INFO:
+		info.log_level = get_pfrt_log_level(pfrt_log_dev);
+		info.log_type = pfrt_log_dev->info.log_type;
+		info.log_revid = pfrt_log_dev->info.log_revid;
+		if (copy_to_user(p, &info, sizeof(info)))
+			return -EFAULT;
+
+		return 0;
+
+	case PFRT_LOG_IOC_GET_DATA_INFO:
+		ret = get_pfrt_log_data_info(&data_info, pfrt_log_dev);
+		if (ret)
+			return ret;
+
+		if (copy_to_user(p, &data_info, sizeof(struct pfrt_log_data_info)))
+			return -EFAULT;
+
+		return 0;
+
+	default:
+		return -ENOTTY;
+	}
+}
+
+static int
+pfrt_log_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	struct pfrt_log_device *pfrt_log_dev;
+	struct pfrt_log_data_info info;
+	unsigned long psize, vsize;
+	phys_addr_t base_addr;
+	int ret;
+
+	if (vma->vm_flags & VM_WRITE)
+		return -EROFS;
+
+	/* changing from read to write with mprotect is not allowed */
+	vm_flags_clear(vma, VM_MAYWRITE);
+
+	pfrt_log_dev = to_pfrt_log_dev(file);
+
+	ret = get_pfrt_log_data_info(&info, pfrt_log_dev);
+	if (ret)
+		return ret;
+
+	base_addr = (phys_addr_t)((info.chunk2_addr_hi << 32) | info.chunk2_addr_lo);
+	/* pfrt update has not been launched yet */
+	if (!base_addr)
+		return -ENODEV;
+
+	psize = info.max_data_size;
+	/* base address and total buffer size must be page aligned */
+	if (!PAGE_ALIGNED(base_addr) || !PAGE_ALIGNED(psize))
+		return -ENODEV;
+
+	vsize = vma->vm_end - vma->vm_start;
+	if (vsize > psize)
+		return -EINVAL;
+
+	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+	if (io_remap_pfn_range(vma, vma->vm_start, PFN_DOWN(base_addr),
+			       vsize, vma->vm_page_prot))
+		return -EAGAIN;
+
+	return 0;
+}
+
+static const struct file_operations acpi_pfrt_log_fops = {
+	.owner		= THIS_MODULE,
+	.mmap		= pfrt_log_mmap,
+	.unlocked_ioctl = pfrt_log_ioctl,
+	.llseek		= noop_llseek,
+};
+
+static void acpi_pfrt_log_remove(struct platform_device *pdev)
+{
+	struct pfrt_log_device *pfrt_log_dev = platform_get_drvdata(pdev);
+
+	misc_deregister(&pfrt_log_dev->miscdev);
+}
+
+static void pfrt_log_put_idx(void *data)
+{
+	struct pfrt_log_device *pfrt_log_dev = data;
+
+	ida_free(&pfrt_log_ida, pfrt_log_dev->index);
+}
+
+static int acpi_pfrt_log_probe(struct platform_device *pdev)
+{
+	acpi_handle handle = ACPI_HANDLE(&pdev->dev);
+	struct pfrt_log_device *pfrt_log_dev;
+	int ret;
+
+	if (!acpi_has_method(handle, "_DSM")) {
+		dev_dbg(&pdev->dev, "Missing _DSM\n");
+		return -ENODEV;
+	}
+
+	pfrt_log_dev = devm_kzalloc(&pdev->dev, sizeof(*pfrt_log_dev), GFP_KERNEL);
+	if (!pfrt_log_dev)
+		return -ENOMEM;
+
+	ret = ida_alloc(&pfrt_log_ida, GFP_KERNEL);
+	if (ret < 0)
+		return ret;
+
+	pfrt_log_dev->index = ret;
+	ret = devm_add_action_or_reset(&pdev->dev, pfrt_log_put_idx, pfrt_log_dev);
+	if (ret)
+		return ret;
+
+	pfrt_log_dev->info.log_revid = PFRT_DEFAULT_REV_ID;
+	pfrt_log_dev->parent_dev = &pdev->dev;
+
+	pfrt_log_dev->miscdev.minor = MISC_DYNAMIC_MINOR;
+	pfrt_log_dev->miscdev.name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
+						    "pfrt%d",
+						    pfrt_log_dev->index);
+	if (!pfrt_log_dev->miscdev.name)
+		return -ENOMEM;
+
+	pfrt_log_dev->miscdev.nodename = devm_kasprintf(&pdev->dev, GFP_KERNEL,
+							"acpi_pfr_telemetry%d",
+							pfrt_log_dev->index);
+	if (!pfrt_log_dev->miscdev.nodename)
+		return -ENOMEM;
+
+	pfrt_log_dev->miscdev.fops = &acpi_pfrt_log_fops;
+	pfrt_log_dev->miscdev.parent = &pdev->dev;
+
+	ret = misc_register(&pfrt_log_dev->miscdev);
+	if (ret)
+		return ret;
+
+	platform_set_drvdata(pdev, pfrt_log_dev);
+
+	return 0;
+}
+
+static const struct acpi_device_id acpi_pfrt_log_ids[] = {
+	{"INTC1081"},
+	{}
+};
+MODULE_DEVICE_TABLE(acpi, acpi_pfrt_log_ids);
+
+static struct platform_driver acpi_pfrt_log_driver = {
+	.driver = {
+		.name = "pfr_telemetry",
+		.acpi_match_table = acpi_pfrt_log_ids,
+	},
+	.probe = acpi_pfrt_log_probe,
+	.remove = acpi_pfrt_log_remove,
+};
+module_platform_driver(acpi_pfrt_log_driver);
+
+MODULE_DESCRIPTION("Platform Firmware Runtime Update Telemetry driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/acpi/pfr_update.c b/drivers/acpi/pfr_update.c
new file mode 100644
index 000000000000..11b1c2828005
--- /dev/null
+++ b/drivers/acpi/pfr_update.c
@@ -0,0 +1,606 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ACPI Platform Firmware Runtime Update Device driver
+ *
+ * Copyright (C) 2021 Intel Corporation
+ * Author: Chen Yu <yu.c.chen@intel.com>
+ *
+ * pfr_update driver is used for Platform Firmware Runtime
+ * Update, which includes the code injection and driver update.
+ */
+#include <linux/acpi.h>
+#include <linux/device.h>
+#include <linux/efi.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/file.h>
+#include <linux/fs.h>
+#include <linux/idr.h>
+#include <linux/miscdevice.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/string.h>
+#include <linux/uaccess.h>
+#include <linux/uio.h>
+#include <linux/uuid.h>
+
+#include <uapi/linux/pfrut.h>
+
+#define PFRU_FUNC_STANDARD_QUERY	0
+#define PFRU_FUNC_QUERY_UPDATE_CAP	1
+#define PFRU_FUNC_QUERY_BUF		2
+#define PFRU_FUNC_START		3
+
+#define PFRU_CODE_INJECT_TYPE	1
+#define PFRU_DRIVER_UPDATE_TYPE	2
+
+#define PFRU_REVID_1		1
+#define PFRU_REVID_2		2
+#define PFRU_DEFAULT_REV_ID	PFRU_REVID_1
+
+enum cap_index {
+	CAP_STATUS_IDX = 0,
+	CAP_UPDATE_IDX = 1,
+	CAP_CODE_TYPE_IDX = 2,
+	CAP_FW_VER_IDX = 3,
+	CAP_CODE_RT_VER_IDX = 4,
+	CAP_DRV_TYPE_IDX = 5,
+	CAP_DRV_RT_VER_IDX = 6,
+	CAP_DRV_SVN_IDX = 7,
+	CAP_PLAT_ID_IDX = 8,
+	CAP_OEM_ID_IDX = 9,
+	CAP_OEM_INFO_IDX = 10,
+	CAP_NR_IDX
+};
+
+enum buf_index {
+	BUF_STATUS_IDX = 0,
+	BUF_EXT_STATUS_IDX = 1,
+	BUF_ADDR_LOW_IDX = 2,
+	BUF_ADDR_HI_IDX = 3,
+	BUF_SIZE_IDX = 4,
+	BUF_NR_IDX
+};
+
+enum update_index {
+	UPDATE_STATUS_IDX = 0,
+	UPDATE_EXT_STATUS_IDX = 1,
+	UPDATE_AUTH_TIME_LOW_IDX = 2,
+	UPDATE_AUTH_TIME_HI_IDX = 3,
+	UPDATE_EXEC_TIME_LOW_IDX = 4,
+	UPDATE_EXEC_TIME_HI_IDX = 5,
+	UPDATE_NR_IDX
+};
+
+enum pfru_start_action {
+	START_STAGE = 0,
+	START_ACTIVATE = 1,
+	START_STAGE_ACTIVATE = 2,
+};
+
+struct pfru_device {
+	u32 rev_id, index;
+	struct device *parent_dev;
+	struct miscdevice miscdev;
+};
+
+static DEFINE_IDA(pfru_ida);
+
+/*
+ * Manual reference:
+ * https://uefi.org/sites/default/files/resources/Intel_MM_OS_Interface_Spec_Rev100.pdf
+ *
+ * pfru_guid is the parameter for _DSM method
+ */
+static const guid_t pfru_guid =
+	GUID_INIT(0xECF9533B, 0x4A3C, 0x4E89, 0x93, 0x9E, 0xC7, 0x71,
+		  0x12, 0x60, 0x1C, 0x6D);
+
+/* pfru_code_inj_guid is the UUID to identify code injection EFI capsule file */
+static const guid_t pfru_code_inj_guid =
+	GUID_INIT(0xB2F84B79, 0x7B6E, 0x4E45, 0x88, 0x5F, 0x3F, 0xB9,
+		  0xBB, 0x18, 0x54, 0x02);
+
+/* pfru_drv_update_guid is the UUID to identify driver update EFI capsule file */
+static const guid_t pfru_drv_update_guid =
+	GUID_INIT(0x4569DD8C, 0x75F1, 0x429A, 0xA3, 0xD6, 0x24, 0xDE,
+		  0x80, 0x97, 0xA0, 0xDF);
+
+static inline int pfru_valid_revid(u32 id)
+{
+	return id == PFRU_REVID_1 || id == PFRU_REVID_2;
+}
+
+static inline struct pfru_device *to_pfru_dev(struct file *file)
+{
+	return container_of(file->private_data, struct pfru_device, miscdev);
+}
+
+static int query_capability(struct pfru_update_cap_info *cap_hdr,
+			    struct pfru_device *pfru_dev)
+{
+	acpi_handle handle = ACPI_HANDLE(pfru_dev->parent_dev);
+	union acpi_object *out_obj;
+	int ret = -EINVAL;
+
+	out_obj = acpi_evaluate_dsm_typed(handle, &pfru_guid,
+					  pfru_dev->rev_id,
+					  PFRU_FUNC_QUERY_UPDATE_CAP,
+					  NULL, ACPI_TYPE_PACKAGE);
+	if (!out_obj) {
+		dev_dbg(pfru_dev->parent_dev,
+			"Query cap failed with no object\n");
+		return ret;
+	}
+
+	if (out_obj->package.count < CAP_NR_IDX ||
+	    out_obj->package.elements[CAP_STATUS_IDX].type != ACPI_TYPE_INTEGER ||
+	    out_obj->package.elements[CAP_UPDATE_IDX].type != ACPI_TYPE_INTEGER ||
+	    out_obj->package.elements[CAP_CODE_TYPE_IDX].type != ACPI_TYPE_BUFFER ||
+	    out_obj->package.elements[CAP_FW_VER_IDX].type != ACPI_TYPE_INTEGER ||
+	    out_obj->package.elements[CAP_CODE_RT_VER_IDX].type != ACPI_TYPE_INTEGER ||
+	    out_obj->package.elements[CAP_DRV_TYPE_IDX].type != ACPI_TYPE_BUFFER ||
+	    out_obj->package.elements[CAP_DRV_RT_VER_IDX].type != ACPI_TYPE_INTEGER ||
+	    out_obj->package.elements[CAP_DRV_SVN_IDX].type != ACPI_TYPE_INTEGER ||
+	    out_obj->package.elements[CAP_PLAT_ID_IDX].type != ACPI_TYPE_BUFFER ||
+	    out_obj->package.elements[CAP_OEM_ID_IDX].type != ACPI_TYPE_BUFFER ||
+	    out_obj->package.elements[CAP_OEM_INFO_IDX].type != ACPI_TYPE_BUFFER) {
+		dev_dbg(pfru_dev->parent_dev,
+			"Query cap failed with invalid package count/type\n");
+		goto free_acpi_buffer;
+	}
+
+	cap_hdr->status = out_obj->package.elements[CAP_STATUS_IDX].integer.value;
+	if (cap_hdr->status != DSM_SUCCEED) {
+		ret = -EBUSY;
+		dev_dbg(pfru_dev->parent_dev, "Query cap Error Status:%d\n",
+			cap_hdr->status);
+		goto free_acpi_buffer;
+	}
+
+	cap_hdr->update_cap = out_obj->package.elements[CAP_UPDATE_IDX].integer.value;
+	memcpy(&cap_hdr->code_type,
+	       out_obj->package.elements[CAP_CODE_TYPE_IDX].buffer.pointer,
+	       out_obj->package.elements[CAP_CODE_TYPE_IDX].buffer.length);
+	cap_hdr->fw_version =
+		out_obj->package.elements[CAP_FW_VER_IDX].integer.value;
+	cap_hdr->code_rt_version =
+		out_obj->package.elements[CAP_CODE_RT_VER_IDX].integer.value;
+	memcpy(&cap_hdr->drv_type,
+	       out_obj->package.elements[CAP_DRV_TYPE_IDX].buffer.pointer,
+	       out_obj->package.elements[CAP_DRV_TYPE_IDX].buffer.length);
+	cap_hdr->drv_rt_version =
+		out_obj->package.elements[CAP_DRV_RT_VER_IDX].integer.value;
+	cap_hdr->drv_svn =
+		out_obj->package.elements[CAP_DRV_SVN_IDX].integer.value;
+	memcpy(&cap_hdr->platform_id,
+	       out_obj->package.elements[CAP_PLAT_ID_IDX].buffer.pointer,
+	       out_obj->package.elements[CAP_PLAT_ID_IDX].buffer.length);
+	memcpy(&cap_hdr->oem_id,
+	       out_obj->package.elements[CAP_OEM_ID_IDX].buffer.pointer,
+	       out_obj->package.elements[CAP_OEM_ID_IDX].buffer.length);
+	cap_hdr->oem_info_len =
+		out_obj->package.elements[CAP_OEM_INFO_IDX].buffer.length;
+
+	ret = 0;
+
+free_acpi_buffer:
+	ACPI_FREE(out_obj);
+
+	return ret;
+}
+
+static int query_buffer(struct pfru_com_buf_info *info,
+			struct pfru_device *pfru_dev)
+{
+	acpi_handle handle = ACPI_HANDLE(pfru_dev->parent_dev);
+	union acpi_object *out_obj;
+	int ret = -EINVAL;
+
+	out_obj = acpi_evaluate_dsm_typed(handle, &pfru_guid,
+					  pfru_dev->rev_id, PFRU_FUNC_QUERY_BUF,
+					  NULL, ACPI_TYPE_PACKAGE);
+	if (!out_obj) {
+		dev_dbg(pfru_dev->parent_dev,
+			"Query buf failed with no object\n");
+		return ret;
+	}
+
+	if (out_obj->package.count < BUF_NR_IDX ||
+	    out_obj->package.elements[BUF_STATUS_IDX].type != ACPI_TYPE_INTEGER ||
+	    out_obj->package.elements[BUF_EXT_STATUS_IDX].type != ACPI_TYPE_INTEGER ||
+	    out_obj->package.elements[BUF_ADDR_LOW_IDX].type != ACPI_TYPE_INTEGER ||
+	    out_obj->package.elements[BUF_ADDR_HI_IDX].type != ACPI_TYPE_INTEGER ||
+	    out_obj->package.elements[BUF_SIZE_IDX].type != ACPI_TYPE_INTEGER) {
+		dev_dbg(pfru_dev->parent_dev,
+			"Query buf failed with invalid package count/type\n");
+		goto free_acpi_buffer;
+	}
+
+	info->status = out_obj->package.elements[BUF_STATUS_IDX].integer.value;
+	info->ext_status =
+		out_obj->package.elements[BUF_EXT_STATUS_IDX].integer.value;
+	if (info->status != DSM_SUCCEED) {
+		ret = -EBUSY;
+		dev_dbg(pfru_dev->parent_dev,
+			"Query buf failed with Error Status:%d\n", info->status);
+		dev_dbg(pfru_dev->parent_dev,
+			"Query buf failed with Error Extended Status:%d\n", info->ext_status);
+
+		goto free_acpi_buffer;
+	}
+
+	info->addr_lo =
+		out_obj->package.elements[BUF_ADDR_LOW_IDX].integer.value;
+	info->addr_hi =
+		out_obj->package.elements[BUF_ADDR_HI_IDX].integer.value;
+	info->buf_size = out_obj->package.elements[BUF_SIZE_IDX].integer.value;
+
+	ret = 0;
+
+free_acpi_buffer:
+	ACPI_FREE(out_obj);
+
+	return ret;
+}
+
+static int get_image_type(const struct efi_manage_capsule_image_header *img_hdr,
+			  struct pfru_device *pfru_dev)
+{
+	const efi_guid_t *image_type_id = &img_hdr->image_type_id;
+
+	/* check whether this is a code injection or driver update */
+	if (guid_equal(image_type_id, &pfru_code_inj_guid))
+		return PFRU_CODE_INJECT_TYPE;
+
+	if (guid_equal(image_type_id, &pfru_drv_update_guid))
+		return PFRU_DRIVER_UPDATE_TYPE;
+
+	return -EINVAL;
+}
+
+static int adjust_efi_size(const struct efi_manage_capsule_image_header *img_hdr,
+			   int size)
+{
+	/*
+	 * The (u64 hw_ins) was introduced in UEFI spec version 2,
+	 * and (u64 capsule_support) was introduced in version 3.
+	 * The size needs to be adjusted accordingly. That is to
+	 * say, version 1 should subtract the size of hw_ins+capsule_support,
+	 * and version 2 should sbstract the size of capsule_support.
+	 */
+	size += sizeof(struct efi_manage_capsule_image_header);
+	switch (img_hdr->ver) {
+	case 1:
+		return size - 2 * sizeof(u64);
+
+	case 2:
+		return size - sizeof(u64);
+
+	default:
+		/* only support version 1 and 2 */
+		return -EINVAL;
+	}
+}
+
+static bool applicable_image(const void *data, struct pfru_update_cap_info *cap,
+			     struct pfru_device *pfru_dev)
+{
+	struct pfru_payload_hdr *payload_hdr;
+	const efi_capsule_header_t *cap_hdr = data;
+	const struct efi_manage_capsule_header *m_hdr;
+	const struct efi_manage_capsule_image_header *m_img_hdr;
+	const struct efi_image_auth *auth;
+	int type, size;
+
+	/*
+	 * If the code in the capsule is older than the current
+	 * firmware code, the update will be rejected by the firmware,
+	 * so check the version of it upfront without engaging the
+	 * Management Mode update mechanism which may be costly.
+	 */
+	size = cap_hdr->headersize;
+	m_hdr = data + size;
+	/*
+	 * Current data structure size plus variable array indicated
+	 * by number of (emb_drv_cnt + payload_cnt)
+	 */
+	size += offsetof(struct efi_manage_capsule_header, offset_list) +
+		(m_hdr->emb_drv_cnt + m_hdr->payload_cnt) * sizeof(u64);
+	m_img_hdr = data + size;
+
+	type = get_image_type(m_img_hdr, pfru_dev);
+	if (type < 0) {
+		dev_dbg(pfru_dev->parent_dev, "Invalid image type\n");
+		return false;
+	}
+
+	size = adjust_efi_size(m_img_hdr, size);
+	if (size < 0) {
+		dev_dbg(pfru_dev->parent_dev, "Invalid image size\n");
+		return false;
+	}
+
+	auth = data + size;
+	size += sizeof(u64) + auth->auth_info.hdr.len;
+	payload_hdr = (struct pfru_payload_hdr *)(data + size);
+
+	/* finally compare the version */
+	if (type == PFRU_CODE_INJECT_TYPE)
+		return payload_hdr->rt_ver >= cap->code_rt_version;
+
+	return payload_hdr->svn_ver >= cap->drv_svn;
+}
+
+static void print_update_debug_info(struct pfru_updated_result *result,
+				    struct pfru_device *pfru_dev)
+{
+	dev_dbg(pfru_dev->parent_dev, "Update result:\n");
+	dev_dbg(pfru_dev->parent_dev, "Authentication Time Low:%lld\n",
+		result->low_auth_time);
+	dev_dbg(pfru_dev->parent_dev, "Authentication Time High:%lld\n",
+		result->high_auth_time);
+	dev_dbg(pfru_dev->parent_dev, "Execution Time Low:%lld\n",
+		result->low_exec_time);
+	dev_dbg(pfru_dev->parent_dev, "Execution Time High:%lld\n",
+		result->high_exec_time);
+}
+
+static int start_update(int action, struct pfru_device *pfru_dev)
+{
+	union acpi_object *out_obj, in_obj, in_buf;
+	struct pfru_updated_result update_result;
+	acpi_handle handle;
+	int ret = -EINVAL;
+
+	memset(&in_obj, 0, sizeof(in_obj));
+	memset(&in_buf, 0, sizeof(in_buf));
+	in_obj.type = ACPI_TYPE_PACKAGE;
+	in_obj.package.count = 1;
+	in_obj.package.elements = &in_buf;
+	in_buf.type = ACPI_TYPE_INTEGER;
+	in_buf.integer.value = action;
+
+	handle = ACPI_HANDLE(pfru_dev->parent_dev);
+	out_obj = acpi_evaluate_dsm_typed(handle, &pfru_guid,
+					  pfru_dev->rev_id, PFRU_FUNC_START,
+					  &in_obj, ACPI_TYPE_PACKAGE);
+	if (!out_obj) {
+		dev_dbg(pfru_dev->parent_dev,
+			"Update failed to start with no object\n");
+		return ret;
+	}
+
+	if (out_obj->package.count < UPDATE_NR_IDX ||
+	    out_obj->package.elements[UPDATE_STATUS_IDX].type != ACPI_TYPE_INTEGER ||
+	    out_obj->package.elements[UPDATE_EXT_STATUS_IDX].type != ACPI_TYPE_INTEGER ||
+	    out_obj->package.elements[UPDATE_AUTH_TIME_LOW_IDX].type != ACPI_TYPE_INTEGER ||
+	    out_obj->package.elements[UPDATE_AUTH_TIME_HI_IDX].type != ACPI_TYPE_INTEGER ||
+	    out_obj->package.elements[UPDATE_EXEC_TIME_LOW_IDX].type != ACPI_TYPE_INTEGER ||
+	    out_obj->package.elements[UPDATE_EXEC_TIME_HI_IDX].type != ACPI_TYPE_INTEGER) {
+		dev_dbg(pfru_dev->parent_dev,
+			"Update failed with invalid package count/type\n");
+		goto free_acpi_buffer;
+	}
+
+	update_result.status =
+		out_obj->package.elements[UPDATE_STATUS_IDX].integer.value;
+	update_result.ext_status =
+		out_obj->package.elements[UPDATE_EXT_STATUS_IDX].integer.value;
+
+	if (update_result.status != DSM_SUCCEED) {
+		ret = -EBUSY;
+		dev_dbg(pfru_dev->parent_dev,
+			"Update failed with Error Status:%d\n", update_result.status);
+		dev_dbg(pfru_dev->parent_dev,
+			"Update failed with Error Extended Status:%d\n",
+			update_result.ext_status);
+
+		goto free_acpi_buffer;
+	}
+
+	update_result.low_auth_time =
+		out_obj->package.elements[UPDATE_AUTH_TIME_LOW_IDX].integer.value;
+	update_result.high_auth_time =
+		out_obj->package.elements[UPDATE_AUTH_TIME_HI_IDX].integer.value;
+	update_result.low_exec_time =
+		out_obj->package.elements[UPDATE_EXEC_TIME_LOW_IDX].integer.value;
+	update_result.high_exec_time =
+		out_obj->package.elements[UPDATE_EXEC_TIME_HI_IDX].integer.value;
+
+	print_update_debug_info(&update_result, pfru_dev);
+	ret = 0;
+
+free_acpi_buffer:
+	ACPI_FREE(out_obj);
+
+	return ret;
+}
+
+static long pfru_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
+{
+	struct pfru_update_cap_info cap_hdr;
+	struct pfru_device *pfru_dev = to_pfru_dev(file);
+	void __user *p = (void __user *)arg;
+	u32 rev;
+	int ret;
+
+	switch (cmd) {
+	case PFRU_IOC_QUERY_CAP:
+		ret = query_capability(&cap_hdr, pfru_dev);
+		if (ret)
+			return ret;
+
+		if (copy_to_user(p, &cap_hdr, sizeof(cap_hdr)))
+			return -EFAULT;
+
+		return 0;
+
+	case PFRU_IOC_SET_REV:
+		if (copy_from_user(&rev, p, sizeof(rev)))
+			return -EFAULT;
+
+		if (!pfru_valid_revid(rev))
+			return -EINVAL;
+
+		pfru_dev->rev_id = rev;
+
+		return 0;
+
+	case PFRU_IOC_STAGE:
+		return start_update(START_STAGE, pfru_dev);
+
+	case PFRU_IOC_ACTIVATE:
+		return start_update(START_ACTIVATE, pfru_dev);
+
+	case PFRU_IOC_STAGE_ACTIVATE:
+		return start_update(START_STAGE_ACTIVATE, pfru_dev);
+
+	default:
+		return -ENOTTY;
+	}
+}
+
+static ssize_t pfru_write(struct file *file, const char __user *buf,
+			  size_t len, loff_t *ppos)
+{
+	struct pfru_device *pfru_dev = to_pfru_dev(file);
+	struct pfru_update_cap_info cap;
+	struct pfru_com_buf_info buf_info;
+	phys_addr_t phy_addr;
+	struct iov_iter iter;
+	struct iovec iov;
+	char *buf_ptr;
+	int ret;
+
+	ret = query_buffer(&buf_info, pfru_dev);
+	if (ret)
+		return ret;
+
+	if (len > buf_info.buf_size) {
+		dev_dbg(pfru_dev->parent_dev, "Capsule image size too large\n");
+		return -EINVAL;
+	}
+
+	iov.iov_base = (void __user *)buf;
+	iov.iov_len = len;
+	iov_iter_init(&iter, ITER_SOURCE, &iov, 1, len);
+
+	/* map the communication buffer */
+	phy_addr = (phys_addr_t)((buf_info.addr_hi << 32) | buf_info.addr_lo);
+	buf_ptr = memremap(phy_addr, buf_info.buf_size, MEMREMAP_WB);
+	if (!buf_ptr) {
+		dev_dbg(pfru_dev->parent_dev, "Failed to remap the buffer\n");
+		return -ENOMEM;
+	}
+
+	if (!copy_from_iter_full(buf_ptr, len, &iter)) {
+		dev_dbg(pfru_dev->parent_dev,
+			"Failed to copy the data from the user space buffer\n");
+		ret = -EINVAL;
+		goto unmap;
+	}
+
+	/* check if the capsule header has a valid version number */
+	ret = query_capability(&cap, pfru_dev);
+	if (ret)
+		goto unmap;
+
+	if (!applicable_image(buf_ptr, &cap, pfru_dev))
+		ret = -EINVAL;
+
+unmap:
+	memunmap(buf_ptr);
+
+	return ret ?: len;
+}
+
+static const struct file_operations acpi_pfru_fops = {
+	.owner		= THIS_MODULE,
+	.write		= pfru_write,
+	.unlocked_ioctl = pfru_ioctl,
+	.llseek		= noop_llseek,
+};
+
+static void acpi_pfru_remove(struct platform_device *pdev)
+{
+	struct pfru_device *pfru_dev = platform_get_drvdata(pdev);
+
+	misc_deregister(&pfru_dev->miscdev);
+}
+
+static void pfru_put_idx(void *data)
+{
+	struct pfru_device *pfru_dev = data;
+
+	ida_free(&pfru_ida, pfru_dev->index);
+}
+
+static int acpi_pfru_probe(struct platform_device *pdev)
+{
+	acpi_handle handle = ACPI_HANDLE(&pdev->dev);
+	struct pfru_device *pfru_dev;
+	int ret;
+
+	if (!acpi_has_method(handle, "_DSM")) {
+		dev_dbg(&pdev->dev, "Missing _DSM\n");
+		return -ENODEV;
+	}
+
+	pfru_dev = devm_kzalloc(&pdev->dev, sizeof(*pfru_dev), GFP_KERNEL);
+	if (!pfru_dev)
+		return -ENOMEM;
+
+	ret = ida_alloc(&pfru_ida, GFP_KERNEL);
+	if (ret < 0)
+		return ret;
+
+	pfru_dev->index = ret;
+	ret = devm_add_action_or_reset(&pdev->dev, pfru_put_idx, pfru_dev);
+	if (ret)
+		return ret;
+
+	pfru_dev->rev_id = PFRU_DEFAULT_REV_ID;
+	pfru_dev->parent_dev = &pdev->dev;
+
+	pfru_dev->miscdev.minor = MISC_DYNAMIC_MINOR;
+	pfru_dev->miscdev.name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
+						"pfru%d", pfru_dev->index);
+	if (!pfru_dev->miscdev.name)
+		return -ENOMEM;
+
+	pfru_dev->miscdev.nodename = devm_kasprintf(&pdev->dev, GFP_KERNEL,
+						    "acpi_pfr_update%d", pfru_dev->index);
+	if (!pfru_dev->miscdev.nodename)
+		return -ENOMEM;
+
+	pfru_dev->miscdev.fops = &acpi_pfru_fops;
+	pfru_dev->miscdev.parent = &pdev->dev;
+
+	ret = misc_register(&pfru_dev->miscdev);
+	if (ret)
+		return ret;
+
+	platform_set_drvdata(pdev, pfru_dev);
+
+	return 0;
+}
+
+static const struct acpi_device_id acpi_pfru_ids[] = {
+	{"INTC1080"},
+	{}
+};
+MODULE_DEVICE_TABLE(acpi, acpi_pfru_ids);
+
+static struct platform_driver acpi_pfru_driver = {
+	.driver = {
+		.name = "pfr_update",
+		.acpi_match_table = acpi_pfru_ids,
+	},
+	.probe = acpi_pfru_probe,
+	.remove = acpi_pfru_remove,
+};
+module_platform_driver(acpi_pfru_driver);
+
+MODULE_DESCRIPTION("Platform Firmware Runtime Update device driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/acpi/platform_profile.c b/drivers/acpi/platform_profile.c
new file mode 100644
index 000000000000..ea04a8c69215
--- /dev/null
+++ b/drivers/acpi/platform_profile.c
@@ -0,0 +1,718 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/* Platform profile sysfs interface */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include <linux/acpi.h>
+#include <linux/bits.h>
+#include <linux/cleanup.h>
+#include <linux/init.h>
+#include <linux/mutex.h>
+#include <linux/platform_profile.h>
+#include <linux/sysfs.h>
+
+#define to_pprof_handler(d)	(container_of(d, struct platform_profile_handler, dev))
+
+static DEFINE_MUTEX(profile_lock);
+
+struct platform_profile_handler {
+	const char *name;
+	struct device dev;
+	int minor;
+	unsigned long choices[BITS_TO_LONGS(PLATFORM_PROFILE_LAST)];
+	unsigned long hidden_choices[BITS_TO_LONGS(PLATFORM_PROFILE_LAST)];
+	const struct platform_profile_ops *ops;
+};
+
+struct aggregate_choices_data {
+	unsigned long aggregate[BITS_TO_LONGS(PLATFORM_PROFILE_LAST)];
+	int count;
+};
+
+static const char * const profile_names[] = {
+	[PLATFORM_PROFILE_LOW_POWER] = "low-power",
+	[PLATFORM_PROFILE_COOL] = "cool",
+	[PLATFORM_PROFILE_QUIET] = "quiet",
+	[PLATFORM_PROFILE_BALANCED] = "balanced",
+	[PLATFORM_PROFILE_BALANCED_PERFORMANCE] = "balanced-performance",
+	[PLATFORM_PROFILE_PERFORMANCE] = "performance",
+	[PLATFORM_PROFILE_MAX_POWER] = "max-power",
+	[PLATFORM_PROFILE_CUSTOM] = "custom",
+};
+static_assert(ARRAY_SIZE(profile_names) == PLATFORM_PROFILE_LAST);
+
+static DEFINE_IDA(platform_profile_ida);
+
+/**
+ * _commmon_choices_show - Show the available profile choices
+ * @choices: The available profile choices
+ * @buf: The buffer to write to
+ *
+ * Return: The number of bytes written
+ */
+static ssize_t _commmon_choices_show(unsigned long *choices, char *buf)
+{
+	int i, len = 0;
+
+	for_each_set_bit(i, choices, PLATFORM_PROFILE_LAST) {
+		if (len == 0)
+			len += sysfs_emit_at(buf, len, "%s", profile_names[i]);
+		else
+			len += sysfs_emit_at(buf, len, " %s", profile_names[i]);
+	}
+	len += sysfs_emit_at(buf, len, "\n");
+
+	return len;
+}
+
+/**
+ * _store_class_profile - Set the profile for a class device
+ * @dev: The class device
+ * @data: The profile to set
+ *
+ * Return: 0 on success, -errno on failure
+ */
+static int _store_class_profile(struct device *dev, void *data)
+{
+	struct platform_profile_handler *handler;
+	int *bit = (int *)data;
+
+	lockdep_assert_held(&profile_lock);
+	handler = to_pprof_handler(dev);
+	if (!test_bit(*bit, handler->choices) && !test_bit(*bit, handler->hidden_choices))
+		return -EOPNOTSUPP;
+
+	return handler->ops->profile_set(dev, *bit);
+}
+
+/**
+ * _notify_class_profile - Notify the class device of a profile change
+ * @dev: The class device
+ * @data: Unused
+ *
+ * Return: 0 on success, -errno on failure
+ */
+static int _notify_class_profile(struct device *dev, void *data)
+{
+	struct platform_profile_handler *handler = to_pprof_handler(dev);
+
+	lockdep_assert_held(&profile_lock);
+	sysfs_notify(&handler->dev.kobj, NULL, "profile");
+	kobject_uevent(&handler->dev.kobj, KOBJ_CHANGE);
+
+	return 0;
+}
+
+/**
+ * get_class_profile - Show the current profile for a class device
+ * @dev: The class device
+ * @profile: The profile to return
+ *
+ * Return: 0 on success, -errno on failure
+ */
+static int get_class_profile(struct device *dev,
+			     enum platform_profile_option *profile)
+{
+	struct platform_profile_handler *handler;
+	enum platform_profile_option val;
+	int err;
+
+	lockdep_assert_held(&profile_lock);
+	handler = to_pprof_handler(dev);
+	err = handler->ops->profile_get(dev, &val);
+	if (err) {
+		pr_err("Failed to get profile for handler %s\n", handler->name);
+		return err;
+	}
+
+	if (WARN_ON(val >= PLATFORM_PROFILE_LAST))
+		return -EINVAL;
+	*profile = val;
+
+	return 0;
+}
+
+/**
+ * name_show - Show the name of the profile handler
+ * @dev: The device
+ * @attr: The attribute
+ * @buf: The buffer to write to
+ *
+ * Return: The number of bytes written
+ */
+static ssize_t name_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+	struct platform_profile_handler *handler = to_pprof_handler(dev);
+
+	return sysfs_emit(buf, "%s\n", handler->name);
+}
+static DEVICE_ATTR_RO(name);
+
+/**
+ * choices_show - Show the available profile choices
+ * @dev: The device
+ * @attr: The attribute
+ * @buf: The buffer to write to
+ *
+ * Return: The number of bytes written
+ */
+static ssize_t choices_show(struct device *dev,
+			    struct device_attribute *attr,
+			    char *buf)
+{
+	struct platform_profile_handler *handler = to_pprof_handler(dev);
+
+	return _commmon_choices_show(handler->choices, buf);
+}
+static DEVICE_ATTR_RO(choices);
+
+/**
+ * profile_show - Show the current profile for a class device
+ * @dev: The device
+ * @attr: The attribute
+ * @buf: The buffer to write to
+ *
+ * Return: The number of bytes written
+ */
+static ssize_t profile_show(struct device *dev,
+			    struct device_attribute *attr,
+			    char *buf)
+{
+	enum platform_profile_option profile = PLATFORM_PROFILE_LAST;
+	int err;
+
+	scoped_cond_guard(mutex_intr, return -ERESTARTSYS, &profile_lock) {
+		err = get_class_profile(dev, &profile);
+		if (err)
+			return err;
+	}
+
+	return sysfs_emit(buf, "%s\n", profile_names[profile]);
+}
+
+/**
+ * profile_store - Set the profile for a class device
+ * @dev: The device
+ * @attr: The attribute
+ * @buf: The buffer to read from
+ * @count: The number of bytes to read
+ *
+ * Return: The number of bytes read
+ */
+static ssize_t profile_store(struct device *dev,
+			     struct device_attribute *attr,
+			     const char *buf, size_t count)
+{
+	int index, ret;
+
+	index = sysfs_match_string(profile_names, buf);
+	if (index < 0)
+		return -EINVAL;
+
+	scoped_cond_guard(mutex_intr, return -ERESTARTSYS, &profile_lock) {
+		ret = _store_class_profile(dev, &index);
+		if (ret)
+			return ret;
+	}
+
+	sysfs_notify(acpi_kobj, NULL, "platform_profile");
+
+	return count;
+}
+static DEVICE_ATTR_RW(profile);
+
+static struct attribute *profile_attrs[] = {
+	&dev_attr_name.attr,
+	&dev_attr_choices.attr,
+	&dev_attr_profile.attr,
+	NULL
+};
+ATTRIBUTE_GROUPS(profile);
+
+static void pprof_device_release(struct device *dev)
+{
+	struct platform_profile_handler *pprof = to_pprof_handler(dev);
+
+	kfree(pprof);
+}
+
+static const struct class platform_profile_class = {
+	.name = "platform-profile",
+	.dev_groups = profile_groups,
+	.dev_release = pprof_device_release,
+};
+
+/**
+ * _aggregate_choices - Aggregate the available profile choices
+ * @dev: The device
+ * @arg: struct aggregate_choices_data, with it's aggregate member bitmap
+ *	 initially filled with ones
+ *
+ * Return: 0 on success, -errno on failure
+ */
+static int _aggregate_choices(struct device *dev, void *arg)
+{
+	unsigned long tmp[BITS_TO_LONGS(PLATFORM_PROFILE_LAST)];
+	struct aggregate_choices_data *data = arg;
+	struct platform_profile_handler *handler;
+
+	lockdep_assert_held(&profile_lock);
+
+	handler = to_pprof_handler(dev);
+	bitmap_or(tmp, handler->choices, handler->hidden_choices, PLATFORM_PROFILE_LAST);
+	bitmap_and(data->aggregate, tmp, data->aggregate, PLATFORM_PROFILE_LAST);
+	data->count++;
+
+	return 0;
+}
+
+/**
+ * _remove_hidden_choices - Remove hidden choices from aggregate data
+ * @dev: The device
+ * @arg: struct aggregate_choices_data
+ *
+ * Return: 0 on success, -errno on failure
+ */
+static int _remove_hidden_choices(struct device *dev, void *arg)
+{
+	struct aggregate_choices_data *data = arg;
+	struct platform_profile_handler *handler;
+
+	lockdep_assert_held(&profile_lock);
+	handler = to_pprof_handler(dev);
+	bitmap_andnot(data->aggregate, handler->choices,
+		      handler->hidden_choices, PLATFORM_PROFILE_LAST);
+
+	return 0;
+}
+
+/**
+ * platform_profile_choices_show - Show the available profile choices for legacy sysfs interface
+ * @kobj: The kobject
+ * @attr: The attribute
+ * @buf: The buffer to write to
+ *
+ * Return: The number of bytes written
+ */
+static ssize_t platform_profile_choices_show(struct kobject *kobj,
+					     struct kobj_attribute *attr,
+					     char *buf)
+{
+	struct aggregate_choices_data data = {
+		.aggregate = { [0 ... BITS_TO_LONGS(PLATFORM_PROFILE_LAST) - 1] = ~0UL },
+		.count = 0,
+	};
+	int err;
+
+	scoped_cond_guard(mutex_intr, return -ERESTARTSYS, &profile_lock) {
+		err = class_for_each_device(&platform_profile_class, NULL,
+					    &data, _aggregate_choices);
+		if (err)
+			return err;
+		if (data.count == 1) {
+			err = class_for_each_device(&platform_profile_class, NULL,
+						    &data, _remove_hidden_choices);
+			if (err)
+				return err;
+		}
+	}
+
+	/* no profile handler registered any more */
+	if (bitmap_empty(data.aggregate, PLATFORM_PROFILE_LAST))
+		return -EINVAL;
+
+	return _commmon_choices_show(data.aggregate, buf);
+}
+
+/**
+ * _aggregate_profiles - Aggregate the profiles for legacy sysfs interface
+ * @dev: The device
+ * @data: The profile to return
+ *
+ * Return: 0 on success, -errno on failure
+ */
+static int _aggregate_profiles(struct device *dev, void *data)
+{
+	enum platform_profile_option *profile = data;
+	enum platform_profile_option val;
+	int err;
+
+	err = get_class_profile(dev, &val);
+	if (err)
+		return err;
+
+	if (*profile != PLATFORM_PROFILE_LAST && *profile != val)
+		*profile = PLATFORM_PROFILE_CUSTOM;
+	else
+		*profile = val;
+
+	return 0;
+}
+
+/**
+ * _store_and_notify - Store and notify a class from legacy sysfs interface
+ * @dev: The device
+ * @data: The profile to return
+ *
+ * Return: 0 on success, -errno on failure
+ */
+static int _store_and_notify(struct device *dev, void *data)
+{
+	enum platform_profile_option *profile = data;
+	int err;
+
+	err = _store_class_profile(dev, profile);
+	if (err)
+		return err;
+	return _notify_class_profile(dev, NULL);
+}
+
+/**
+ * platform_profile_show - Show the current profile for legacy sysfs interface
+ * @kobj: The kobject
+ * @attr: The attribute
+ * @buf: The buffer to write to
+ *
+ * Return: The number of bytes written
+ */
+static ssize_t platform_profile_show(struct kobject *kobj,
+				     struct kobj_attribute *attr,
+				     char *buf)
+{
+	enum platform_profile_option profile = PLATFORM_PROFILE_LAST;
+	int err;
+
+	scoped_cond_guard(mutex_intr, return -ERESTARTSYS, &profile_lock) {
+		err = class_for_each_device(&platform_profile_class, NULL,
+					    &profile, _aggregate_profiles);
+		if (err)
+			return err;
+	}
+
+	/* no profile handler registered any more */
+	if (profile == PLATFORM_PROFILE_LAST)
+		return -EINVAL;
+
+	return sysfs_emit(buf, "%s\n", profile_names[profile]);
+}
+
+/**
+ * platform_profile_store - Set the profile for legacy sysfs interface
+ * @kobj: The kobject
+ * @attr: The attribute
+ * @buf: The buffer to read from
+ * @count: The number of bytes to read
+ *
+ * Return: The number of bytes read
+ */
+static ssize_t platform_profile_store(struct kobject *kobj,
+				      struct kobj_attribute *attr,
+				      const char *buf, size_t count)
+{
+	struct aggregate_choices_data data = {
+		.aggregate = { [0 ... BITS_TO_LONGS(PLATFORM_PROFILE_LAST) - 1] = ~0UL },
+		.count = 0,
+	};
+	int ret;
+	int i;
+
+	/* Scan for a matching profile */
+	i = sysfs_match_string(profile_names, buf);
+	if (i < 0 || i == PLATFORM_PROFILE_CUSTOM)
+		return -EINVAL;
+
+	scoped_cond_guard(mutex_intr, return -ERESTARTSYS, &profile_lock) {
+		ret = class_for_each_device(&platform_profile_class, NULL,
+					    &data, _aggregate_choices);
+		if (ret)
+			return ret;
+		if (!test_bit(i, data.aggregate))
+			return -EOPNOTSUPP;
+
+		ret = class_for_each_device(&platform_profile_class, NULL, &i,
+					    _store_and_notify);
+		if (ret)
+			return ret;
+	}
+
+	sysfs_notify(acpi_kobj, NULL, "platform_profile");
+
+	return count;
+}
+
+static struct kobj_attribute attr_platform_profile_choices = __ATTR_RO(platform_profile_choices);
+static struct kobj_attribute attr_platform_profile = __ATTR_RW(platform_profile);
+
+static struct attribute *platform_profile_attrs[] = {
+	&attr_platform_profile_choices.attr,
+	&attr_platform_profile.attr,
+	NULL
+};
+
+static int profile_class_registered(struct device *dev, const void *data)
+{
+	return 1;
+}
+
+static umode_t profile_class_is_visible(struct kobject *kobj, struct attribute *attr, int idx)
+{
+	struct device *dev;
+
+	dev = class_find_device(&platform_profile_class, NULL, NULL, profile_class_registered);
+	if (!dev)
+		return 0;
+
+	put_device(dev);
+
+	return attr->mode;
+}
+
+static const struct attribute_group platform_profile_group = {
+	.attrs = platform_profile_attrs,
+	.is_visible = profile_class_is_visible,
+};
+
+/**
+ * platform_profile_notify - Notify class device and legacy sysfs interface
+ * @dev: The class device
+ */
+void platform_profile_notify(struct device *dev)
+{
+	scoped_cond_guard(mutex_intr, return, &profile_lock) {
+		_notify_class_profile(dev, NULL);
+	}
+	sysfs_notify(acpi_kobj, NULL, "platform_profile");
+}
+EXPORT_SYMBOL_GPL(platform_profile_notify);
+
+/**
+ * platform_profile_cycle - Cycles profiles available on all registered class devices
+ *
+ * Return: 0 on success, -errno on failure
+ */
+int platform_profile_cycle(void)
+{
+	struct aggregate_choices_data data = {
+		.aggregate = { [0 ... BITS_TO_LONGS(PLATFORM_PROFILE_LAST) - 1] = ~0UL },
+		.count = 0,
+	};
+	enum platform_profile_option next = PLATFORM_PROFILE_LAST;
+	enum platform_profile_option profile = PLATFORM_PROFILE_LAST;
+	int err;
+
+	scoped_cond_guard(mutex_intr, return -ERESTARTSYS, &profile_lock) {
+		err = class_for_each_device(&platform_profile_class, NULL,
+					    &profile, _aggregate_profiles);
+		if (err)
+			return err;
+
+		if (profile == PLATFORM_PROFILE_MAX_POWER ||
+		    profile == PLATFORM_PROFILE_CUSTOM ||
+		    profile == PLATFORM_PROFILE_LAST)
+			return -EINVAL;
+
+		err = class_for_each_device(&platform_profile_class, NULL,
+					    &data, _aggregate_choices);
+		if (err)
+			return err;
+
+		/* never iterate into a custom or max power if all drivers supported it */
+		clear_bit(PLATFORM_PROFILE_MAX_POWER, data.aggregate);
+		clear_bit(PLATFORM_PROFILE_CUSTOM, data.aggregate);
+
+		next = find_next_bit_wrap(data.aggregate,
+					  PLATFORM_PROFILE_LAST,
+					  profile + 1);
+
+		err = class_for_each_device(&platform_profile_class, NULL, &next,
+					    _store_and_notify);
+
+		if (err)
+			return err;
+	}
+
+	sysfs_notify(acpi_kobj, NULL, "platform_profile");
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(platform_profile_cycle);
+
+/**
+ * platform_profile_register - Creates and registers a platform profile class device
+ * @dev: Parent device
+ * @name: Name of the class device
+ * @drvdata: Driver data that will be attached to the class device
+ * @ops: Platform profile's mandatory operations
+ *
+ * Return: pointer to the new class device on success, ERR_PTR on failure
+ */
+struct device *platform_profile_register(struct device *dev, const char *name,
+					 void *drvdata,
+					 const struct platform_profile_ops *ops)
+{
+	struct device *ppdev;
+	int minor;
+	int err;
+
+	/* Sanity check */
+	if (WARN_ON_ONCE(!dev || !name || !ops || !ops->profile_get ||
+	    !ops->profile_set || !ops->probe))
+		return ERR_PTR(-EINVAL);
+
+	struct platform_profile_handler *pprof __free(kfree) = kzalloc(
+		sizeof(*pprof), GFP_KERNEL);
+	if (!pprof)
+		return ERR_PTR(-ENOMEM);
+
+	err = ops->probe(drvdata, pprof->choices);
+	if (err) {
+		dev_err(dev, "platform_profile probe failed\n");
+		return ERR_PTR(err);
+	}
+
+	if (bitmap_empty(pprof->choices, PLATFORM_PROFILE_LAST)) {
+		dev_err(dev, "Failed to register platform_profile class device with empty choices\n");
+		return ERR_PTR(-EINVAL);
+	}
+
+	if (ops->hidden_choices) {
+		err = ops->hidden_choices(drvdata, pprof->hidden_choices);
+		if (err) {
+			dev_err(dev, "platform_profile hidden_choices failed\n");
+			return ERR_PTR(err);
+		}
+	}
+
+	guard(mutex)(&profile_lock);
+
+	/* create class interface for individual handler */
+	minor = ida_alloc(&platform_profile_ida, GFP_KERNEL);
+	if (minor < 0)
+		return ERR_PTR(minor);
+
+	pprof->name = name;
+	pprof->ops = ops;
+	pprof->minor = minor;
+	pprof->dev.class = &platform_profile_class;
+	pprof->dev.parent = dev;
+	dev_set_drvdata(&pprof->dev, drvdata);
+	dev_set_name(&pprof->dev, "platform-profile-%d", pprof->minor);
+	/* device_register() takes ownership of pprof/ppdev */
+	ppdev = &no_free_ptr(pprof)->dev;
+	err = device_register(ppdev);
+	if (err) {
+		put_device(ppdev);
+		goto cleanup_ida;
+	}
+
+	sysfs_notify(acpi_kobj, NULL, "platform_profile");
+
+	err = sysfs_update_group(acpi_kobj, &platform_profile_group);
+	if (err)
+		goto cleanup_cur;
+
+	return ppdev;
+
+cleanup_cur:
+	device_unregister(ppdev);
+
+cleanup_ida:
+	ida_free(&platform_profile_ida, minor);
+
+	return ERR_PTR(err);
+}
+EXPORT_SYMBOL_GPL(platform_profile_register);
+
+/**
+ * platform_profile_remove - Unregisters a platform profile class device
+ * @dev: Class device
+ */
+void platform_profile_remove(struct device *dev)
+{
+	struct platform_profile_handler *pprof;
+
+	if (IS_ERR_OR_NULL(dev))
+		return;
+
+	pprof = to_pprof_handler(dev);
+
+	guard(mutex)(&profile_lock);
+
+	ida_free(&platform_profile_ida, pprof->minor);
+	device_unregister(&pprof->dev);
+
+	sysfs_notify(acpi_kobj, NULL, "platform_profile");
+	sysfs_update_group(acpi_kobj, &platform_profile_group);
+}
+EXPORT_SYMBOL_GPL(platform_profile_remove);
+
+static void devm_platform_profile_release(struct device *dev, void *res)
+{
+	struct device **ppdev = res;
+
+	platform_profile_remove(*ppdev);
+}
+
+/**
+ * devm_platform_profile_register - Device managed version of platform_profile_register
+ * @dev: Parent device
+ * @name: Name of the class device
+ * @drvdata: Driver data that will be attached to the class device
+ * @ops: Platform profile's mandatory operations
+ *
+ * Return: pointer to the new class device on success, ERR_PTR on failure
+ */
+struct device *devm_platform_profile_register(struct device *dev, const char *name,
+					      void *drvdata,
+					      const struct platform_profile_ops *ops)
+{
+	struct device *ppdev;
+	struct device **dr;
+
+	dr = devres_alloc(devm_platform_profile_release, sizeof(*dr), GFP_KERNEL);
+	if (!dr)
+		return ERR_PTR(-ENOMEM);
+
+	ppdev = platform_profile_register(dev, name, drvdata, ops);
+	if (IS_ERR(ppdev)) {
+		devres_free(dr);
+		return ppdev;
+	}
+
+	*dr = ppdev;
+	devres_add(dev, dr);
+
+	return ppdev;
+}
+EXPORT_SYMBOL_GPL(devm_platform_profile_register);
+
+static int __init platform_profile_init(void)
+{
+	int err;
+
+	if (acpi_disabled)
+		return -EOPNOTSUPP;
+
+	err = class_register(&platform_profile_class);
+	if (err)
+		return err;
+
+	err = sysfs_create_group(acpi_kobj, &platform_profile_group);
+	if (err)
+		class_unregister(&platform_profile_class);
+
+	return err;
+}
+
+static void __exit platform_profile_exit(void)
+{
+	sysfs_remove_group(acpi_kobj, &platform_profile_group);
+	class_unregister(&platform_profile_class);
+}
+module_init(platform_profile_init);
+module_exit(platform_profile_exit);
+
+MODULE_AUTHOR("Mark Pearson <markpearson@lenovo.com>");
+MODULE_DESCRIPTION("ACPI platform profile sysfs interface");
+MODULE_LICENSE("GPL");
diff --git a/drivers/acpi/pmic/Kconfig b/drivers/acpi/pmic/Kconfig
new file mode 100644
index 000000000000..f84b8f6038dc
--- /dev/null
+++ b/drivers/acpi/pmic/Kconfig
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: GPL-2.0
+
+menuconfig PMIC_OPREGION
+	bool "PMIC (Power Management Integrated Circuit) operation region support"
+	help
+	  Select this option to enable support for ACPI operation
+	  region of the PMIC chip. The operation region can be used
+	  to control power rails and sensor reading/writing on the
+	  PMIC chip.
+
+if PMIC_OPREGION
+
+config BYTCRC_PMIC_OPREGION
+	bool "ACPI operation region support for Bay Trail Crystal Cove PMIC"
+	depends on INTEL_SOC_PMIC
+	help
+	  This config adds ACPI operation region support for the Bay Trail
+	  version of the Crystal Cove PMIC.
+
+config CHTCRC_PMIC_OPREGION
+	bool "ACPI operation region support for Cherry Trail Crystal Cove PMIC"
+	depends on INTEL_SOC_PMIC
+	help
+	  This config adds ACPI operation region support for the Cherry Trail
+	  version of the Crystal Cove PMIC.
+
+config XPOWER_PMIC_OPREGION
+	bool "ACPI operation region support for XPower AXP288 PMIC"
+	depends on MFD_AXP20X_I2C && IOSF_MBI=y
+	help
+	  This config adds ACPI operation region support for XPower AXP288 PMIC.
+
+config BXT_WC_PMIC_OPREGION
+	bool "ACPI operation region support for BXT WhiskeyCove PMIC"
+	depends on INTEL_SOC_PMIC_BXTWC
+	help
+	  This config adds ACPI operation region support for BXT WhiskeyCove PMIC.
+
+config CHT_WC_PMIC_OPREGION
+	bool "ACPI operation region support for CHT Whiskey Cove PMIC"
+	depends on INTEL_SOC_PMIC_CHTWC
+	help
+	  This config adds ACPI operation region support for CHT Whiskey Cove PMIC.
+
+config CHT_DC_TI_PMIC_OPREGION
+	bool "ACPI operation region support for Dollar Cove TI PMIC"
+	depends on INTEL_SOC_PMIC_CHTDC_TI
+	help
+	  This config adds ACPI operation region support for Dollar Cove TI PMIC.
+
+endif	# PMIC_OPREGION
+
+config TPS68470_PMIC_OPREGION
+	bool "ACPI operation region support for TPS68470 PMIC"
+	depends on INTEL_SKL_INT3472
+	help
+	  This config adds ACPI operation region support for TI TPS68470 PMIC.
+	  TPS68470 device is an advanced power management unit that powers
+	  a Compact Camera Module (CCM), generates clocks for image sensors,
+	  drives a dual LED for flash and incorporates two LED drivers for
+	  general purpose indicators.
+	  This driver enables ACPI operation region support control voltage
+	  regulators and clocks.
+
+	  This option is a bool as it provides an ACPI operation
+	  region, which must be available before any of the devices
+	  using this, are probed.
diff --git a/drivers/acpi/pmic/Makefile b/drivers/acpi/pmic/Makefile
new file mode 100644
index 000000000000..cd072c64920c
--- /dev/null
+++ b/drivers/acpi/pmic/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_PMIC_OPREGION)		+= intel_pmic.o
+obj-$(CONFIG_BYTCRC_PMIC_OPREGION)	+= intel_pmic_bytcrc.o
+obj-$(CONFIG_CHTCRC_PMIC_OPREGION)	+= intel_pmic_chtcrc.o
+obj-$(CONFIG_XPOWER_PMIC_OPREGION)	+= intel_pmic_xpower.o
+obj-$(CONFIG_BXT_WC_PMIC_OPREGION)	+= intel_pmic_bxtwc.o
+obj-$(CONFIG_CHT_WC_PMIC_OPREGION)	+= intel_pmic_chtwc.o
+obj-$(CONFIG_CHT_DC_TI_PMIC_OPREGION)	+= intel_pmic_chtdc_ti.o
+obj-$(CONFIG_TPS68470_PMIC_OPREGION)	+= tps68470_pmic.o
diff --git a/drivers/acpi/pmic/intel_pmic.c b/drivers/acpi/pmic/intel_pmic.c
index a371f273f99d..134e9ca8eaa2 100644
--- a/drivers/acpi/pmic/intel_pmic.c
+++ b/drivers/acpi/pmic/intel_pmic.c
@@ -25,13 +25,13 @@ struct intel_pmic_opregion {
 	struct mutex lock;
 	struct acpi_lpat_conversion_table *lpat_table;
 	struct regmap *regmap;
-	struct intel_pmic_opregion_data *data;
+	const struct intel_pmic_opregion_data *data;
 	struct intel_pmic_regs_handler_ctx ctx;
 };
 
 static struct intel_pmic_opregion *intel_pmic_opregion;
 
-static int pmic_get_reg_bit(int address, struct pmic_table *table,
+static int pmic_get_reg_bit(int address, const struct pmic_table *table,
 			    int count, int *reg, int *bit)
 {
 	int i;
@@ -53,7 +53,7 @@ static acpi_status intel_pmic_power_handler(u32 function,
 {
 	struct intel_pmic_opregion *opregion = region_context;
 	struct regmap *regmap = opregion->regmap;
-	struct intel_pmic_opregion_data *d = opregion->data;
+	const struct intel_pmic_opregion_data *d = opregion->data;
 	int reg, bit, result;
 
 	if (bits != 32 || !value64)
@@ -95,7 +95,7 @@ static int pmic_read_temp(struct intel_pmic_opregion *opregion,
 		return 0;
 	}
 
-	temp = acpi_lpat_raw_to_temp(opregion->lpat_table, raw_temp);
+	temp = opregion->data->lpat_raw_to_temp(opregion->lpat_table, raw_temp);
 	if (temp < 0)
 		return temp;
 
@@ -135,7 +135,7 @@ static int pmic_thermal_aux(struct intel_pmic_opregion *opregion, int reg,
 static int pmic_thermal_pen(struct intel_pmic_opregion *opregion, int reg,
 			    int bit, u32 function, u64 *value)
 {
-	struct intel_pmic_opregion_data *d = opregion->data;
+	const struct intel_pmic_opregion_data *d = opregion->data;
 	struct regmap *regmap = opregion->regmap;
 
 	if (!d->get_policy || !d->update_policy)
@@ -171,7 +171,7 @@ static acpi_status intel_pmic_thermal_handler(u32 function,
 		void *handler_context, void *region_context)
 {
 	struct intel_pmic_opregion *opregion = region_context;
-	struct intel_pmic_opregion_data *d = opregion->data;
+	const struct intel_pmic_opregion_data *d = opregion->data;
 	int reg, bit, result;
 
 	if (bits != 32 || !value64)
@@ -211,31 +211,36 @@ static acpi_status intel_pmic_regs_handler(u32 function,
 		void *handler_context, void *region_context)
 {
 	struct intel_pmic_opregion *opregion = region_context;
-	int result = 0;
+	int result = -EINVAL;
+
+	if (function == ACPI_WRITE) {
+		switch (address) {
+		case 0:
+			return AE_OK;
+		case 1:
+			opregion->ctx.addr |= (*value64 & 0xff) << 8;
+			return AE_OK;
+		case 2:
+			opregion->ctx.addr |= *value64 & 0xff;
+			return AE_OK;
+		case 3:
+			opregion->ctx.val = *value64 & 0xff;
+			return AE_OK;
+		case 4:
+			if (*value64) {
+				result = regmap_write(opregion->regmap, opregion->ctx.addr,
+						      opregion->ctx.val);
+			} else {
+				result = regmap_read(opregion->regmap, opregion->ctx.addr,
+						     &opregion->ctx.val);
+			}
+			opregion->ctx.addr = 0;
+		}
+	}
 
-	switch (address) {
-	case 0:
-		return AE_OK;
-	case 1:
-		opregion->ctx.addr |= (*value64 & 0xff) << 8;
-		return AE_OK;
-	case 2:
-		opregion->ctx.addr |= *value64 & 0xff;
+	if (function == ACPI_READ && address == 3) {
+		*value64 = opregion->ctx.val;
 		return AE_OK;
-	case 3:
-		opregion->ctx.val = *value64 & 0xff;
-		return AE_OK;
-	case 4:
-		if (*value64) {
-			result = regmap_write(opregion->regmap, opregion->ctx.addr,
-					      opregion->ctx.val);
-		} else {
-			result = regmap_read(opregion->regmap, opregion->ctx.addr,
-					     &opregion->ctx.val);
-			if (result == 0)
-				*value64 = opregion->ctx.val;
-		}
-		memset(&opregion->ctx, 0x00, sizeof(opregion->ctx));
 	}
 
 	if (result < 0) {
@@ -250,7 +255,7 @@ static acpi_status intel_pmic_regs_handler(u32 function,
 
 int intel_pmic_install_opregion_handler(struct device *dev, acpi_handle handle,
 					struct regmap *regmap,
-					struct intel_pmic_opregion_data *d)
+					const struct intel_pmic_opregion_data *d)
 {
 	acpi_status status = AE_OK;
 	struct intel_pmic_opregion *opregion;
@@ -339,7 +344,7 @@ EXPORT_SYMBOL_GPL(intel_pmic_install_opregion_handler);
 int intel_soc_pmic_exec_mipi_pmic_seq_element(u16 i2c_address, u32 reg_address,
 					      u32 value, u32 mask)
 {
-	struct intel_pmic_opregion_data *d;
+	const struct intel_pmic_opregion_data *d;
 	int ret;
 
 	if (!intel_pmic_opregion) {
diff --git a/drivers/acpi/pmic/intel_pmic.h b/drivers/acpi/pmic/intel_pmic.h
index 89379476a1df..006f0780ffab 100644
--- a/drivers/acpi/pmic/intel_pmic.h
+++ b/drivers/acpi/pmic/intel_pmic.h
@@ -2,6 +2,8 @@
 #ifndef __INTEL_PMIC_H
 #define __INTEL_PMIC_H
 
+#include <acpi/acpi_lpat.h>
+
 struct pmic_table {
 	int address;	/* operation region address */
 	int reg;	/* corresponding thermal register */
@@ -17,14 +19,18 @@ struct intel_pmic_opregion_data {
 	int (*update_policy)(struct regmap *r, int reg, int bit, int enable);
 	int (*exec_mipi_pmic_seq_element)(struct regmap *r, u16 i2c_address,
 					  u32 reg_address, u32 value, u32 mask);
-	struct pmic_table *power_table;
+	int (*lpat_raw_to_temp)(struct acpi_lpat_conversion_table *lpat_table,
+				int raw);
+	const struct pmic_table *power_table;
 	int power_table_count;
-	struct pmic_table *thermal_table;
+	const struct pmic_table *thermal_table;
 	int thermal_table_count;
 	/* For generic exec_mipi_pmic_seq_element handling */
 	int pmic_i2c_address;
 };
 
-int intel_pmic_install_opregion_handler(struct device *dev, acpi_handle handle, struct regmap *regmap, struct intel_pmic_opregion_data *d);
+int intel_pmic_install_opregion_handler(struct device *dev, acpi_handle handle,
+					struct regmap *regmap,
+					const struct intel_pmic_opregion_data *d);
 
 #endif
diff --git a/drivers/acpi/pmic/intel_pmic_bxtwc.c b/drivers/acpi/pmic/intel_pmic_bxtwc.c
index bd7621edd60b..c332afbf82bd 100644
--- a/drivers/acpi/pmic/intel_pmic_bxtwc.c
+++ b/drivers/acpi/pmic/intel_pmic_bxtwc.c
@@ -24,7 +24,7 @@
 #define VSWITCH1_OUTPUT         BIT(4)
 #define VUSBPHY_CHARGE          BIT(1)
 
-static struct pmic_table power_table[] = {
+static const struct pmic_table power_table[] = {
 	{
 		.address = 0x0,
 		.reg = 0x63,
@@ -177,7 +177,7 @@ static struct pmic_table power_table[] = {
 	} /* MOFF -> MODEMCTRL Bit 0 */
 };
 
-static struct pmic_table thermal_table[] = {
+static const struct pmic_table thermal_table[] = {
 	{
 		.address = 0x00,
 		.reg = 0x4F39
@@ -369,13 +369,14 @@ intel_bxtwc_pmic_update_policy(struct regmap *regmap,
 	return regmap_update_bits(regmap, reg, mask, val);
 }
 
-static struct intel_pmic_opregion_data intel_bxtwc_pmic_opregion_data = {
+static const struct intel_pmic_opregion_data intel_bxtwc_pmic_opregion_data = {
 	.get_power      = intel_bxtwc_pmic_get_power,
 	.update_power   = intel_bxtwc_pmic_update_power,
 	.get_raw_temp   = intel_bxtwc_pmic_get_raw_temp,
 	.update_aux     = intel_bxtwc_pmic_update_aux,
 	.get_policy     = intel_bxtwc_pmic_get_policy,
 	.update_policy  = intel_bxtwc_pmic_update_policy,
+	.lpat_raw_to_temp = acpi_lpat_raw_to_temp,
 	.power_table      = power_table,
 	.power_table_count = ARRAY_SIZE(power_table),
 	.thermal_table     = thermal_table,
diff --git a/drivers/acpi/pmic/intel_pmic_bytcrc.c b/drivers/acpi/pmic/intel_pmic_bytcrc.c
index 2a692cc4b7ae..b4c21a75294a 100644
--- a/drivers/acpi/pmic/intel_pmic_bytcrc.c
+++ b/drivers/acpi/pmic/intel_pmic_bytcrc.c
@@ -16,7 +16,7 @@
 
 #define PMIC_A0LOCK_REG		0xc5
 
-static struct pmic_table power_table[] = {
+static const struct pmic_table power_table[] = {
 /*	{
 		.address = 0x00,
 		.reg = ??,
@@ -134,7 +134,7 @@ static struct pmic_table power_table[] = {
 	}, /* V105 -> V1P05S, L2 SRAM */
 };
 
-static struct pmic_table thermal_table[] = {
+static const struct pmic_table thermal_table[] = {
 	{
 		.address = 0x00,
 		.reg = 0x75
@@ -271,17 +271,19 @@ static int intel_crc_pmic_update_policy(struct regmap *regmap,
 	return 0;
 }
 
-static struct intel_pmic_opregion_data intel_crc_pmic_opregion_data = {
+static const struct intel_pmic_opregion_data intel_crc_pmic_opregion_data = {
 	.get_power	= intel_crc_pmic_get_power,
 	.update_power	= intel_crc_pmic_update_power,
 	.get_raw_temp	= intel_crc_pmic_get_raw_temp,
 	.update_aux	= intel_crc_pmic_update_aux,
 	.get_policy	= intel_crc_pmic_get_policy,
 	.update_policy	= intel_crc_pmic_update_policy,
+	.lpat_raw_to_temp = acpi_lpat_raw_to_temp,
 	.power_table	= power_table,
 	.power_table_count= ARRAY_SIZE(power_table),
 	.thermal_table	= thermal_table,
 	.thermal_table_count = ARRAY_SIZE(thermal_table),
+	.pmic_i2c_address = 0x6e,
 };
 
 static int intel_crc_pmic_opregion_probe(struct platform_device *pdev)
diff --git a/drivers/acpi/pmic/intel_pmic_chtcrc.c b/drivers/acpi/pmic/intel_pmic_chtcrc.c
index ebf8d3187df1..f9301c6f098e 100644
--- a/drivers/acpi/pmic/intel_pmic_chtcrc.c
+++ b/drivers/acpi/pmic/intel_pmic_chtcrc.c
@@ -15,7 +15,7 @@
 /*
  * We have no docs for the CHT Crystal Cove PMIC. The Asus Zenfone-2 kernel
  * code has 2 Crystal Cove regulator drivers, one calls the PMIC a "Crystal
- * Cove Plus" PMIC and talks about Cherry Trail, so presuambly that one
+ * Cove Plus" PMIC and talks about Cherry Trail, so presumably that one
  * could be used to get register info for the regulators if we need to
  * implement regulator support in the future.
  *
@@ -23,7 +23,8 @@
  * intel_soc_pmic_exec_mipi_pmic_seq_element work on devices with a
  * CHT Crystal Cove PMIC.
  */
-static struct intel_pmic_opregion_data intel_chtcrc_pmic_opregion_data = {
+static const struct intel_pmic_opregion_data intel_chtcrc_pmic_opregion_data = {
+	.lpat_raw_to_temp = acpi_lpat_raw_to_temp,
 	.pmic_i2c_address = 0x6e,
 };
 
diff --git a/drivers/acpi/pmic/intel_pmic_chtdc_ti.c b/drivers/acpi/pmic/intel_pmic_chtdc_ti.c
index 7ccd7d9660bc..ecb36fbc1e7f 100644
--- a/drivers/acpi/pmic/intel_pmic_chtdc_ti.c
+++ b/drivers/acpi/pmic/intel_pmic_chtdc_ti.c
@@ -8,34 +8,38 @@
  */
 
 #include <linux/acpi.h>
+#include <linux/bits.h>
 #include <linux/init.h>
 #include <linux/mfd/intel_soc_pmic.h>
 #include <linux/platform_device.h>
+#include <asm/byteorder.h>
 #include "intel_pmic.h"
 
 /* registers stored in 16bit BE (high:low, total 10bit) */
+#define PMIC_REG_MASK		GENMASK(9, 0)
+
 #define CHTDC_TI_VBAT		0x54
 #define CHTDC_TI_DIETEMP	0x56
 #define CHTDC_TI_BPTHERM	0x58
 #define CHTDC_TI_GPADC		0x5a
 
-static struct pmic_table chtdc_ti_power_table[] = {
-	{ .address = 0x00, .reg = 0x41 },
-	{ .address = 0x04, .reg = 0x42 },
-	{ .address = 0x08, .reg = 0x43 },
-	{ .address = 0x0c, .reg = 0x45 },
-	{ .address = 0x10, .reg = 0x46 },
-	{ .address = 0x14, .reg = 0x47 },
-	{ .address = 0x18, .reg = 0x48 },
-	{ .address = 0x1c, .reg = 0x49 },
-	{ .address = 0x20, .reg = 0x4a },
-	{ .address = 0x24, .reg = 0x4b },
-	{ .address = 0x28, .reg = 0x4c },
-	{ .address = 0x2c, .reg = 0x4d },
-	{ .address = 0x30, .reg = 0x4e },
+static const struct pmic_table chtdc_ti_power_table[] = {
+	{ .address = 0x00, .reg = 0x41 }, /* LDO1 */
+	{ .address = 0x04, .reg = 0x42 }, /* LDO2 */
+	{ .address = 0x08, .reg = 0x43 }, /* LDO3 */
+	{ .address = 0x0c, .reg = 0x45 }, /* LDO5 */
+	{ .address = 0x10, .reg = 0x46 }, /* LDO6 */
+	{ .address = 0x14, .reg = 0x47 }, /* LDO7 */
+	{ .address = 0x18, .reg = 0x48 }, /* LDO8 */
+	{ .address = 0x1c, .reg = 0x49 }, /* LDO9 */
+	{ .address = 0x20, .reg = 0x4a }, /* LD10 */
+	{ .address = 0x24, .reg = 0x4b }, /* LD11 */
+	{ .address = 0x28, .reg = 0x4c }, /* LD12 */
+	{ .address = 0x2c, .reg = 0x4d }, /* LD13 */
+	{ .address = 0x30, .reg = 0x4e }, /* LD14 */
 };
 
-static struct pmic_table chtdc_ti_thermal_table[] = {
+static const struct pmic_table chtdc_ti_thermal_table[] = {
 	{
 		.address = 0x00,
 		.reg = CHTDC_TI_GPADC
@@ -73,7 +77,7 @@ static int chtdc_ti_pmic_get_power(struct regmap *regmap, int reg, int bit,
 	if (regmap_read(regmap, reg, &data))
 		return -EIO;
 
-	*value = data & 1;
+	*value = data & BIT(0);
 	return 0;
 }
 
@@ -85,23 +89,24 @@ static int chtdc_ti_pmic_update_power(struct regmap *regmap, int reg, int bit,
 
 static int chtdc_ti_pmic_get_raw_temp(struct regmap *regmap, int reg)
 {
-	u8 buf[2];
+	__be16 buf;
 
-	if (regmap_bulk_read(regmap, reg, buf, 2))
+	if (regmap_bulk_read(regmap, reg, &buf, sizeof(buf)))
 		return -EIO;
 
-	/* stored in big-endian */
-	return ((buf[0] & 0x03) << 8) | buf[1];
+	return be16_to_cpu(buf) & PMIC_REG_MASK;
 }
 
-static struct intel_pmic_opregion_data chtdc_ti_pmic_opregion_data = {
+static const struct intel_pmic_opregion_data chtdc_ti_pmic_opregion_data = {
 	.get_power = chtdc_ti_pmic_get_power,
 	.update_power = chtdc_ti_pmic_update_power,
 	.get_raw_temp = chtdc_ti_pmic_get_raw_temp,
+	.lpat_raw_to_temp = acpi_lpat_raw_to_temp,
 	.power_table = chtdc_ti_power_table,
 	.power_table_count = ARRAY_SIZE(chtdc_ti_power_table),
 	.thermal_table = chtdc_ti_thermal_table,
 	.thermal_table_count = ARRAY_SIZE(chtdc_ti_thermal_table),
+	.pmic_i2c_address = 0x5e,
 };
 
 static int chtdc_ti_pmic_opregion_probe(struct platform_device *pdev)
@@ -116,7 +121,7 @@ static int chtdc_ti_pmic_opregion_probe(struct platform_device *pdev)
 		return err;
 
 	/* Re-enumerate devices depending on PMIC */
-	acpi_walk_dep_device_list(ACPI_HANDLE(pdev->dev.parent));
+	acpi_dev_clear_dependencies(ACPI_COMPANION(pdev->dev.parent));
 	return 0;
 }
 
diff --git a/drivers/acpi/pmic/intel_pmic_chtwc.c b/drivers/acpi/pmic/intel_pmic_chtwc.c
index 7ffd5624b8e1..81caede51ca2 100644
--- a/drivers/acpi/pmic/intel_pmic_chtwc.c
+++ b/drivers/acpi/pmic/intel_pmic_chtwc.c
@@ -70,7 +70,7 @@
  * "regulator: whiskey_cove: implements Whiskey Cove pmic VRF support"
  * https://github.com/intel-aero/meta-intel-aero/blob/master/recipes-kernel/linux/linux-yocto/0019-regulator-whiskey_cove-implements-WhiskeyCove-pmic-V.patch
  */
-static struct pmic_table power_table[] = {
+static const struct pmic_table power_table[] = {
 	{
 		.address = 0x0,
 		.reg = CHT_WC_V1P8A_CTRL,
@@ -236,11 +236,12 @@ static int intel_cht_wc_exec_mipi_pmic_seq_element(struct regmap *regmap,
 						   u32 reg_address,
 						   u32 value, u32 mask)
 {
+	struct device *dev = regmap_get_device(regmap);
 	u32 address;
 
 	if (i2c_client_address > 0xff || reg_address > 0xff) {
-		pr_warn("%s warning addresses too big client 0x%x reg 0x%x\n",
-			__func__, i2c_client_address, reg_address);
+		dev_warn(dev, "warning addresses too big client 0x%x reg 0x%x\n",
+			 i2c_client_address, reg_address);
 		return -ERANGE;
 	}
 
@@ -253,10 +254,11 @@ static int intel_cht_wc_exec_mipi_pmic_seq_element(struct regmap *regmap,
  * The thermal table and ops are empty, we do not support the Thermal opregion
  * (DPTF) due to lacking documentation.
  */
-static struct intel_pmic_opregion_data intel_cht_wc_pmic_opregion_data = {
+static const struct intel_pmic_opregion_data intel_cht_wc_pmic_opregion_data = {
 	.get_power		= intel_cht_wc_pmic_get_power,
 	.update_power		= intel_cht_wc_pmic_update_power,
 	.exec_mipi_pmic_seq_element = intel_cht_wc_exec_mipi_pmic_seq_element,
+	.lpat_raw_to_temp	= acpi_lpat_raw_to_temp,
 	.power_table		= power_table,
 	.power_table_count	= ARRAY_SIZE(power_table),
 };
diff --git a/drivers/acpi/pmic/intel_pmic_xpower.c b/drivers/acpi/pmic/intel_pmic_xpower.c
index a091d5a8392c..49bda5e0c8aa 100644
--- a/drivers/acpi/pmic/intel_pmic_xpower.c
+++ b/drivers/acpi/pmic/intel_pmic_xpower.c
@@ -26,7 +26,7 @@
 #define AXP288_ADC_TS_CURRENT_ON_ONDEMAND		(2 << 0)
 #define AXP288_ADC_TS_CURRENT_ON			(3 << 0)
 
-static struct pmic_table power_table[] = {
+static const struct pmic_table power_table[] = {
 	{
 		.address = 0x00,
 		.reg = 0x13,
@@ -129,7 +129,7 @@ static struct pmic_table power_table[] = {
 };
 
 /* TMP0 - TMP5 are the same, all from GPADC */
-static struct pmic_table thermal_table[] = {
+static const struct pmic_table thermal_table[] = {
 	{
 		.address = 0x00,
 		.reg = XPOWER_GPADC_LOW
@@ -178,15 +178,17 @@ static int intel_xpower_pmic_update_power(struct regmap *regmap, int reg,
 {
 	int data, ret;
 
-	/* GPIO1 LDO regulator needs special handling */
-	if (reg == XPOWER_GPI1_CTRL)
-		return regmap_update_bits(regmap, reg, GPI1_LDO_MASK,
-					  on ? GPI1_LDO_ON : GPI1_LDO_OFF);
-
 	ret = iosf_mbi_block_punit_i2c_access();
 	if (ret)
 		return ret;
 
+	/* GPIO1 LDO regulator needs special handling */
+	if (reg == XPOWER_GPI1_CTRL) {
+		ret = regmap_update_bits(regmap, reg, GPI1_LDO_MASK,
+					 on ? GPI1_LDO_ON : GPI1_LDO_OFF);
+		goto out;
+	}
+
 	if (regmap_read(regmap, reg, &data)) {
 		ret = -EIO;
 		goto out;
@@ -234,6 +236,11 @@ static int intel_xpower_pmic_get_raw_temp(struct regmap *regmap, int reg)
 		return ret;
 
 	if (adc_ts_pin_ctrl & AXP288_ADC_TS_CURRENT_ON_OFF_MASK) {
+		/*
+		 * AXP288_ADC_TS_PIN_CTRL reads are cached by the regmap, so
+		 * this does to a single I2C-transfer, and thus there is no
+		 * need to explicitly call iosf_mbi_block_punit_i2c_access().
+		 */
 		ret = regmap_update_bits(regmap, AXP288_ADC_TS_PIN_CTRL,
 					 AXP288_ADC_TS_CURRENT_ON_OFF_MASK,
 					 AXP288_ADC_TS_CURRENT_ON_ONDEMAND);
@@ -244,7 +251,11 @@ static int intel_xpower_pmic_get_raw_temp(struct regmap *regmap, int reg)
 		usleep_range(6000, 10000);
 	}
 
-	ret = regmap_bulk_read(regmap, AXP288_GP_ADC_H, buf, 2);
+	ret = iosf_mbi_block_punit_i2c_access();
+	if (ret)
+		return ret;
+
+	ret = regmap_bulk_read(regmap, AXP288_GP_ADC_H, buf, sizeof(buf));
 	if (ret == 0)
 		ret = (buf[0] << 4) + ((buf[1] >> 4) & 0x0f);
 
@@ -254,13 +265,62 @@ static int intel_xpower_pmic_get_raw_temp(struct regmap *regmap, int reg)
 				   AXP288_ADC_TS_CURRENT_ON);
 	}
 
+	iosf_mbi_unblock_punit_i2c_access();
+
+	return ret;
+}
+
+static int intel_xpower_exec_mipi_pmic_seq_element(struct regmap *regmap,
+						   u16 i2c_address, u32 reg_address,
+						   u32 value, u32 mask)
+{
+	struct device *dev = regmap_get_device(regmap);
+	int ret;
+
+	if (i2c_address != 0x34) {
+		dev_err(dev, "Unexpected i2c-addr: 0x%02x (reg-addr 0x%x value 0x%x mask 0x%x)\n",
+			i2c_address, reg_address, value, mask);
+		return -ENXIO;
+	}
+
+	ret = iosf_mbi_block_punit_i2c_access();
+	if (ret)
+		return ret;
+
+	ret = regmap_update_bits(regmap, reg_address, mask, value);
+
+	iosf_mbi_unblock_punit_i2c_access();
+
 	return ret;
 }
 
-static struct intel_pmic_opregion_data intel_xpower_pmic_opregion_data = {
+static int intel_xpower_lpat_raw_to_temp(struct acpi_lpat_conversion_table *lpat_table,
+					 int raw)
+{
+	struct acpi_lpat first = lpat_table->lpat[0];
+	struct acpi_lpat last = lpat_table->lpat[lpat_table->lpat_count - 1];
+
+	/*
+	 * Some LPAT tables in the ACPI Device for the AXP288 PMIC for some
+	 * reason only describe a small temperature range, e.g. 27° - 37°
+	 * Celcius. Resulting in errors when the tablet is idle in a cool room.
+	 *
+	 * To avoid these errors clamp the raw value to be inside the LPAT.
+	 */
+	if (first.raw < last.raw)
+		raw = clamp(raw, first.raw, last.raw);
+	else
+		raw = clamp(raw, last.raw, first.raw);
+
+	return acpi_lpat_raw_to_temp(lpat_table, raw);
+}
+
+static const struct intel_pmic_opregion_data intel_xpower_pmic_opregion_data = {
 	.get_power = intel_xpower_pmic_get_power,
 	.update_power = intel_xpower_pmic_update_power,
 	.get_raw_temp = intel_xpower_pmic_get_raw_temp,
+	.exec_mipi_pmic_seq_element = intel_xpower_exec_mipi_pmic_seq_element,
+	.lpat_raw_to_temp = intel_xpower_lpat_raw_to_temp,
 	.power_table = power_table,
 	.power_table_count = ARRAY_SIZE(power_table),
 	.thermal_table = thermal_table,
diff --git a/drivers/acpi/pmic/tps68470_pmic.c b/drivers/acpi/pmic/tps68470_pmic.c
index ebd03e472955..0d1a82eeb4b0 100644
--- a/drivers/acpi/pmic/tps68470_pmic.c
+++ b/drivers/acpi/pmic/tps68470_pmic.c
@@ -376,10 +376,8 @@ static int tps68470_pmic_opregion_probe(struct platform_device *pdev)
 	struct tps68470_pmic_opregion *opregion;
 	acpi_status status;
 
-	if (!dev || !tps68470_regmap) {
-		dev_warn(dev, "dev or regmap is NULL\n");
-		return -EINVAL;
-	}
+	if (!tps68470_regmap)
+		return dev_err_probe(dev, -EINVAL, "regmap is missing\n");
 
 	if (!handle) {
 		dev_warn(dev, "acpi handle is NULL\n");
diff --git a/drivers/acpi/power.c b/drivers/acpi/power.c
index fe1e7bc91a5e..361a7721a6a8 100644
--- a/drivers/acpi/power.c
+++ b/drivers/acpi/power.c
@@ -13,7 +13,7 @@
  * 1. via "Device Specific (D-State) Control"
  * 2. via "Power Resource Control".
  * The code below deals with ACPI Power Resources control.
- * 
+ *
  * An ACPI "power resource object" represents a software controllable power
  * plane, clock plane, or other resource depended on by a device.
  *
@@ -21,23 +21,24 @@
  * may be shared by multiple devices.
  */
 
+#define pr_fmt(fmt) "ACPI: PM: " fmt
+
+#include <linux/delay.h>
+#include <linux/dmi.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/types.h>
 #include <linux/slab.h>
+#include <linux/string_choices.h>
 #include <linux/pm_runtime.h>
 #include <linux/sysfs.h>
 #include <linux/acpi.h>
 #include "sleep.h"
 #include "internal.h"
 
-#define _COMPONENT			ACPI_POWER_COMPONENT
-ACPI_MODULE_NAME("power");
 #define ACPI_POWER_CLASS		"power_resource"
 #define ACPI_POWER_DEVICE_NAME		"Power Resource"
-#define ACPI_POWER_FILE_INFO		"info"
-#define ACPI_POWER_FILE_STATUS		"state"
 #define ACPI_POWER_RESOURCE_STATE_OFF	0x00
 #define ACPI_POWER_RESOURCE_STATE_ON	0x01
 #define ACPI_POWER_RESOURCE_STATE_UNKNOWN 0xFF
@@ -50,11 +51,10 @@ struct acpi_power_dependent_device {
 struct acpi_power_resource {
 	struct acpi_device device;
 	struct list_head list_node;
-	char *name;
 	u32 system_level;
 	u32 order;
 	unsigned int ref_count;
-	bool wakeup_enabled;
+	u8 state;
 	struct mutex resource_lock;
 	struct list_head dependents;
 };
@@ -64,6 +64,9 @@ struct acpi_power_resource_entry {
 	struct acpi_power_resource *resource;
 };
 
+static bool hp_eb_gp12pxp_quirk;
+static bool unused_power_resources_quirk;
+
 static LIST_HEAD(acpi_power_resource_list);
 static DEFINE_MUTEX(power_resource_list_lock);
 
@@ -71,6 +74,11 @@ static DEFINE_MUTEX(power_resource_list_lock);
                              Power Resource Management
    -------------------------------------------------------------------------- */
 
+static inline const char *resource_dev_name(struct acpi_power_resource *pr)
+{
+	return dev_name(&pr->device.dev);
+}
+
 static inline
 struct acpi_power_resource *to_power_resource(struct acpi_device *device)
 {
@@ -79,9 +87,9 @@ struct acpi_power_resource *to_power_resource(struct acpi_device *device)
 
 static struct acpi_power_resource *acpi_power_get_context(acpi_handle handle)
 {
-	struct acpi_device *device;
+	struct acpi_device *device = acpi_fetch_acpi_dev(handle);
 
-	if (acpi_bus_get_device(handle, &device))
+	if (!device)
 		return NULL;
 
 	return to_power_resource(device);
@@ -149,6 +157,7 @@ int acpi_extract_power_resources(union acpi_object *package, unsigned int start,
 
 	for (i = start; i < package->package.count; i++) {
 		union acpi_object *element = &package->package.elements[i];
+		struct acpi_device *rdev;
 		acpi_handle rhandle;
 
 		if (element->type != ACPI_TYPE_LOCAL_REFERENCE) {
@@ -165,10 +174,11 @@ int acpi_extract_power_resources(union acpi_object *package, unsigned int start,
 		if (acpi_power_resource_is_dup(package, start, i))
 			continue;
 
-		err = acpi_add_power_resource(rhandle);
-		if (err)
+		rdev = acpi_add_power_resource(rhandle);
+		if (!rdev) {
+			err = -ENODEV;
 			break;
-
+		}
 		err = acpi_power_resources_list_add(rhandle, list);
 		if (err)
 			break;
@@ -179,50 +189,54 @@ int acpi_extract_power_resources(union acpi_object *package, unsigned int start,
 	return err;
 }
 
-static int acpi_power_get_state(acpi_handle handle, int *state)
+static int __get_state(acpi_handle handle, u8 *state)
 {
 	acpi_status status = AE_OK;
 	unsigned long long sta = 0;
-	char node_name[5];
-	struct acpi_buffer buffer = { sizeof(node_name), node_name };
-
-
-	if (!handle || !state)
-		return -EINVAL;
+	u8 cur_state;
 
 	status = acpi_evaluate_integer(handle, "_STA", NULL, &sta);
 	if (ACPI_FAILURE(status))
 		return -ENODEV;
 
-	*state = (sta & 0x01)?ACPI_POWER_RESOURCE_STATE_ON:
-			      ACPI_POWER_RESOURCE_STATE_OFF;
+	cur_state = sta & ACPI_POWER_RESOURCE_STATE_ON;
+
+	acpi_handle_debug(handle, "Power resource is %s\n",
+			  str_on_off(cur_state));
+
+	*state = cur_state;
+	return 0;
+}
 
-	acpi_get_name(handle, ACPI_SINGLE_NAME, &buffer);
+static int acpi_power_get_state(struct acpi_power_resource *resource, u8 *state)
+{
+	if (resource->state == ACPI_POWER_RESOURCE_STATE_UNKNOWN) {
+		int ret;
 
-	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Resource [%s] is %s\n",
-			  node_name,
-				*state ? "on" : "off"));
+		ret = __get_state(resource->device.handle, &resource->state);
+		if (ret)
+			return ret;
+	}
 
+	*state = resource->state;
 	return 0;
 }
 
-static int acpi_power_get_list_state(struct list_head *list, int *state)
+static int acpi_power_get_list_state(struct list_head *list, u8 *state)
 {
 	struct acpi_power_resource_entry *entry;
-	int cur_state;
+	u8 cur_state = ACPI_POWER_RESOURCE_STATE_OFF;
 
 	if (!list || !state)
 		return -EINVAL;
 
 	/* The state of the list is 'on' IFF all resources are 'on'. */
-	cur_state = 0;
 	list_for_each_entry(entry, list, node) {
 		struct acpi_power_resource *resource = entry->resource;
-		acpi_handle handle = resource->device.handle;
 		int result;
 
 		mutex_lock(&resource->resource_lock);
-		result = acpi_power_get_state(handle, &cur_state);
+		result = acpi_power_get_state(resource, &cur_state);
 		mutex_unlock(&resource->resource_lock);
 		if (result)
 			return result;
@@ -231,8 +245,7 @@ static int acpi_power_get_list_state(struct list_head *list, int *state)
 			break;
 	}
 
-	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Resource list is %s\n",
-			  cur_state ? "on" : "off"));
+	pr_debug("Power resource list is %s\n", str_on_off(cur_state));
 
 	*state = cur_state;
 	return 0;
@@ -260,7 +273,8 @@ acpi_power_resource_add_dependent(struct acpi_power_resource *resource,
 
 	dep->dev = dev;
 	list_add_tail(&dep->node, &resource->dependents);
-	dev_dbg(dev, "added power dependency to [%s]\n", resource->name);
+	dev_dbg(dev, "added power dependency to [%s]\n",
+		resource_dev_name(resource));
 
 unlock:
 	mutex_unlock(&resource->resource_lock);
@@ -279,7 +293,7 @@ acpi_power_resource_remove_dependent(struct acpi_power_resource *resource,
 			list_del(&dep->node);
 			kfree(dep);
 			dev_dbg(dev, "removed power dependency to [%s]\n",
-				resource->name);
+				resource_dev_name(resource));
 			break;
 		}
 	}
@@ -352,15 +366,19 @@ void acpi_device_power_remove_dependent(struct acpi_device *adev,
 
 static int __acpi_power_on(struct acpi_power_resource *resource)
 {
+	acpi_handle handle = resource->device.handle;
 	struct acpi_power_dependent_device *dep;
 	acpi_status status = AE_OK;
 
-	status = acpi_evaluate_object(resource->device.handle, "_ON", NULL, NULL);
-	if (ACPI_FAILURE(status))
+	status = acpi_evaluate_object(handle, "_ON", NULL, NULL);
+	if (ACPI_FAILURE(status)) {
+		resource->state = ACPI_POWER_RESOURCE_STATE_UNKNOWN;
 		return -ENODEV;
+	}
+
+	resource->state = ACPI_POWER_RESOURCE_STATE_ON;
 
-	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Power resource [%s] turned on\n",
-			  resource->name));
+	acpi_handle_debug(handle, "Power resource turned on\n");
 
 	/*
 	 * If there are other dependents on this power resource we need to
@@ -373,7 +391,7 @@ static int __acpi_power_on(struct acpi_power_resource *resource)
 
 	list_for_each_entry(dep, &resource->dependents, node) {
 		dev_dbg(dep->dev, "runtime resuming because [%s] turned on\n",
-			resource->name);
+			resource_dev_name(resource));
 		pm_request_resume(dep->dev);
 	}
 
@@ -385,9 +403,8 @@ static int acpi_power_on_unlocked(struct acpi_power_resource *resource)
 	int result = 0;
 
 	if (resource->ref_count++) {
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-				  "Power resource [%s] already on\n",
-				  resource->name));
+		acpi_handle_debug(resource->device.handle,
+				  "Power resource already on\n");
 	} else {
 		result = __acpi_power_on(resource);
 		if (result)
@@ -408,15 +425,19 @@ static int acpi_power_on(struct acpi_power_resource *resource)
 
 static int __acpi_power_off(struct acpi_power_resource *resource)
 {
+	acpi_handle handle = resource->device.handle;
 	acpi_status status;
 
-	status = acpi_evaluate_object(resource->device.handle, "_OFF",
-				      NULL, NULL);
-	if (ACPI_FAILURE(status))
+	status = acpi_evaluate_object(handle, "_OFF", NULL, NULL);
+	if (ACPI_FAILURE(status)) {
+		resource->state = ACPI_POWER_RESOURCE_STATE_UNKNOWN;
 		return -ENODEV;
+	}
+
+	resource->state = ACPI_POWER_RESOURCE_STATE_OFF;
+
+	acpi_handle_debug(handle, "Power resource turned off\n");
 
-	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Power resource [%s] turned off\n",
-			  resource->name));
 	return 0;
 }
 
@@ -425,16 +446,14 @@ static int acpi_power_off_unlocked(struct acpi_power_resource *resource)
 	int result = 0;
 
 	if (!resource->ref_count) {
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-				  "Power resource [%s] already off\n",
-				  resource->name));
+		acpi_handle_debug(resource->device.handle,
+				  "Power resource already off\n");
 		return 0;
 	}
 
 	if (--resource->ref_count) {
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-				  "Power resource [%s] still in use\n",
-				  resource->name));
+		acpi_handle_debug(resource->device.handle,
+				  "Power resource still in use\n");
 	} else {
 		result = __acpi_power_off(resource);
 		if (result)
@@ -601,21 +620,19 @@ int acpi_power_wakeup_list_init(struct list_head *list, int *system_level_p)
 
 	list_for_each_entry(entry, list, node) {
 		struct acpi_power_resource *resource = entry->resource;
-		acpi_handle handle = resource->device.handle;
-		int result;
-		int state;
+		u8 state;
 
 		mutex_lock(&resource->resource_lock);
 
-		result = acpi_power_get_state(handle, &state);
-		if (result) {
-			mutex_unlock(&resource->resource_lock);
-			return result;
-		}
-		if (state == ACPI_POWER_RESOURCE_STATE_ON) {
-			resource->ref_count++;
-			resource->wakeup_enabled = true;
-		}
+		/*
+		 * Make sure that the power resource state and its reference
+		 * counter value are consistent with each other.
+		 */
+		if (!resource->ref_count &&
+		    !acpi_power_get_state(resource, &state) &&
+		    state == ACPI_POWER_RESOURCE_STATE_ON)
+			__acpi_power_off(resource);
+
 		if (system_level > resource->system_level)
 			system_level = resource->system_level;
 
@@ -647,7 +664,7 @@ int acpi_power_wakeup_list_init(struct list_head *list, int *system_level_p)
  * -ENODEV if the execution of either _DSW or _PSW has failed
  */
 int acpi_device_sleep_wake(struct acpi_device *dev,
-                           int enable, int sleep_state, int dev_state)
+			   int enable, int sleep_state, int dev_state)
 {
 	union acpi_object in_arg[3];
 	struct acpi_object_list arg_list = { 3, in_arg };
@@ -674,7 +691,7 @@ int acpi_device_sleep_wake(struct acpi_device *dev,
 	if (ACPI_SUCCESS(status)) {
 		return 0;
 	} else if (status != AE_NOT_FOUND) {
-		printk(KERN_ERR PREFIX "_DSW execution failed\n");
+		acpi_handle_info(dev->handle, "_DSW execution failed\n");
 		dev->wakeup.flags.valid = 0;
 		return -ENODEV;
 	}
@@ -682,7 +699,7 @@ int acpi_device_sleep_wake(struct acpi_device *dev,
 	/* Execute _PSW */
 	status = acpi_execute_simple_method(dev->handle, "_PSW", enable);
 	if (ACPI_FAILURE(status) && (status != AE_NOT_FOUND)) {
-		printk(KERN_ERR PREFIX "_PSW execution failed\n");
+		acpi_handle_info(dev->handle, "_PSW execution failed\n");
 		dev->wakeup.flags.valid = 0;
 		return -ENODEV;
 	}
@@ -692,13 +709,12 @@ int acpi_device_sleep_wake(struct acpi_device *dev,
 
 /*
  * Prepare a wakeup device, two steps (Ref ACPI 2.0:P229):
- * 1. Power on the power resources required for the wakeup device 
+ * 1. Power on the power resources required for the wakeup device
  * 2. Execute _DSW (Device Sleep Wake) or (deprecated in ACPI 3.0) _PSW (Power
  *    State Wake) for the device, if present
  */
 int acpi_enable_wakeup_device_power(struct acpi_device *dev, int sleep_state)
 {
-	struct acpi_power_resource_entry *entry;
 	int err = 0;
 
 	if (!dev || !dev->wakeup.flags.valid)
@@ -706,36 +722,31 @@ int acpi_enable_wakeup_device_power(struct acpi_device *dev, int sleep_state)
 
 	mutex_lock(&acpi_device_lock);
 
+	dev_dbg(&dev->dev, "Enabling wakeup power (count %d)\n",
+		dev->wakeup.prepare_count);
+
 	if (dev->wakeup.prepare_count++)
 		goto out;
 
-	list_for_each_entry(entry, &dev->wakeup.resources, node) {
-		struct acpi_power_resource *resource = entry->resource;
-
-		mutex_lock(&resource->resource_lock);
-
-		if (!resource->wakeup_enabled) {
-			err = acpi_power_on_unlocked(resource);
-			if (!err)
-				resource->wakeup_enabled = true;
-		}
-
-		mutex_unlock(&resource->resource_lock);
-
-		if (err) {
-			dev_err(&dev->dev,
-				"Cannot turn wakeup power resources on\n");
-			dev->wakeup.flags.valid = 0;
-			goto out;
-		}
+	err = acpi_power_on_list(&dev->wakeup.resources);
+	if (err) {
+		dev_err(&dev->dev, "Cannot turn on wakeup power resources\n");
+		dev->wakeup.flags.valid = 0;
+		goto out;
 	}
+
 	/*
 	 * Passing 3 as the third argument below means the device may be
 	 * put into arbitrary power state afterward.
 	 */
 	err = acpi_device_sleep_wake(dev, 1, sleep_state, 3);
-	if (err)
+	if (err) {
+		acpi_power_off_list(&dev->wakeup.resources);
 		dev->wakeup.prepare_count = 0;
+		goto out;
+	}
+
+	dev_dbg(&dev->dev, "Wakeup power enabled\n");
 
  out:
 	mutex_unlock(&acpi_device_lock);
@@ -758,40 +769,38 @@ int acpi_disable_wakeup_device_power(struct acpi_device *dev)
 
 	mutex_lock(&acpi_device_lock);
 
-	if (--dev->wakeup.prepare_count > 0)
+	dev_dbg(&dev->dev, "Disabling wakeup power (count %d)\n",
+		dev->wakeup.prepare_count);
+
+	/* Do nothing if wakeup power has not been enabled for this device. */
+	if (dev->wakeup.prepare_count <= 0)
 		goto out;
 
-	/*
-	 * Executing the code below even if prepare_count is already zero when
-	 * the function is called may be useful, for example for initialisation.
-	 */
-	if (dev->wakeup.prepare_count < 0)
-		dev->wakeup.prepare_count = 0;
+	if (--dev->wakeup.prepare_count > 0)
+		goto out;
 
 	err = acpi_device_sleep_wake(dev, 0, 0, 0);
 	if (err)
 		goto out;
 
+	/*
+	 * All of the power resources in the list need to be turned off even if
+	 * there are errors.
+	 */
 	list_for_each_entry(entry, &dev->wakeup.resources, node) {
-		struct acpi_power_resource *resource = entry->resource;
+		int ret;
 
-		mutex_lock(&resource->resource_lock);
-
-		if (resource->wakeup_enabled) {
-			err = acpi_power_off_unlocked(resource);
-			if (!err)
-				resource->wakeup_enabled = false;
-		}
-
-		mutex_unlock(&resource->resource_lock);
-
-		if (err) {
-			dev_err(&dev->dev,
-				"Cannot turn wakeup power resources off\n");
-			dev->wakeup.flags.valid = 0;
-			break;
-		}
+		ret = acpi_power_off(entry->resource);
+		if (ret && !err)
+			err = ret;
 	}
+	if (err) {
+		dev_err(&dev->dev, "Cannot turn off wakeup power resources\n");
+		dev->wakeup.flags.valid = 0;
+		goto out;
+	}
+
+	dev_dbg(&dev->dev, "Wakeup power disabled\n");
 
  out:
 	mutex_unlock(&acpi_device_lock);
@@ -800,8 +809,8 @@ int acpi_disable_wakeup_device_power(struct acpi_device *dev)
 
 int acpi_power_get_inferred_state(struct acpi_device *device, int *state)
 {
+	u8 list_state = ACPI_POWER_RESOURCE_STATE_OFF;
 	int result = 0;
-	int list_state = 0;
 	int i = 0;
 
 	if (!device || !state)
@@ -888,15 +897,16 @@ static void acpi_release_power_resource(struct device *dev)
 	kfree(resource);
 }
 
-static ssize_t acpi_power_in_use_show(struct device *dev,
-				      struct device_attribute *attr,
-				      char *buf) {
+static ssize_t resource_in_use_show(struct device *dev,
+				    struct device_attribute *attr,
+				    char *buf)
+{
 	struct acpi_power_resource *resource;
 
 	resource = to_power_resource(to_acpi_device(dev));
 	return sprintf(buf, "%u\n", !!resource->ref_count);
 }
-static DEVICE_ATTR(resource_in_use, 0444, acpi_power_in_use_show, NULL);
+static DEVICE_ATTR_RO(resource_in_use);
 
 static void acpi_power_sysfs_remove(struct acpi_device *device)
 {
@@ -922,51 +932,54 @@ static void acpi_power_add_resource_to_list(struct acpi_power_resource *resource
 	mutex_unlock(&power_resource_list_lock);
 }
 
-int acpi_add_power_resource(acpi_handle handle)
+struct acpi_device *acpi_add_power_resource(acpi_handle handle)
 {
+	struct acpi_device *device = acpi_fetch_acpi_dev(handle);
 	struct acpi_power_resource *resource;
-	struct acpi_device *device = NULL;
 	union acpi_object acpi_object;
 	struct acpi_buffer buffer = { sizeof(acpi_object), &acpi_object };
 	acpi_status status;
-	int state, result = -ENODEV;
+	u8 state_dummy;
+	int result;
 
-	acpi_bus_get_device(handle, &device);
 	if (device)
-		return 0;
+		return device;
 
 	resource = kzalloc(sizeof(*resource), GFP_KERNEL);
 	if (!resource)
-		return -ENOMEM;
+		return NULL;
 
 	device = &resource->device;
 	acpi_init_device_object(device, handle, ACPI_BUS_TYPE_POWER,
-				ACPI_STA_DEFAULT);
+				acpi_release_power_resource);
 	mutex_init(&resource->resource_lock);
 	INIT_LIST_HEAD(&resource->list_node);
 	INIT_LIST_HEAD(&resource->dependents);
-	resource->name = device->pnp.bus_id;
-	strcpy(acpi_device_name(device), ACPI_POWER_DEVICE_NAME);
-	strcpy(acpi_device_class(device), ACPI_POWER_CLASS);
+	strscpy(acpi_device_name(device), ACPI_POWER_DEVICE_NAME);
+	strscpy(acpi_device_class(device), ACPI_POWER_CLASS);
 	device->power.state = ACPI_STATE_UNKNOWN;
+	device->flags.match_driver = true;
 
-	/* Evalute the object to get the system level and resource order. */
+	/* Evaluate the object to get the system level and resource order. */
 	status = acpi_evaluate_object(handle, NULL, NULL, &buffer);
 	if (ACPI_FAILURE(status))
 		goto err;
 
 	resource->system_level = acpi_object.power_resource.system_level;
 	resource->order = acpi_object.power_resource.resource_order;
+	resource->state = ACPI_POWER_RESOURCE_STATE_UNKNOWN;
 
-	result = acpi_power_get_state(handle, &state);
+	/* Get the initial state or just flip it on if that fails. */
+	if (acpi_power_get_state(resource, &state_dummy))
+		__acpi_power_on(resource);
+
+	acpi_handle_info(handle, "New power resource\n");
+
+	result = acpi_tie_acpi_dev(device);
 	if (result)
 		goto err;
 
-	printk(KERN_INFO PREFIX "%s [%s] (%s)\n", acpi_device_name(device),
-	       acpi_device_bid(device), state ? "on" : "off");
-
-	device->flags.match_driver = true;
-	result = acpi_device_add(device, acpi_release_power_resource);
+	result = acpi_device_add(device);
 	if (result)
 		goto err;
 
@@ -975,14 +988,46 @@ int acpi_add_power_resource(acpi_handle handle)
 
 	acpi_power_add_resource_to_list(resource);
 	acpi_device_add_finalize(device);
-	return 0;
+	return device;
 
  err:
 	acpi_release_power_resource(&device->dev);
-	return result;
+	return NULL;
 }
 
 #ifdef CONFIG_ACPI_SLEEP
+static bool resource_is_gp12pxp(acpi_handle handle)
+{
+	const char *path;
+	bool ret;
+
+	path = acpi_handle_path(handle);
+	ret = path && strcmp(path, "\\_SB_.PCI0.GP12.PXP_") == 0;
+	kfree(path);
+
+	return ret;
+}
+
+static void acpi_resume_on_eb_gp12pxp(struct acpi_power_resource *resource)
+{
+	acpi_handle_notice(resource->device.handle,
+			   "HP EB quirk - turning OFF then ON\n");
+
+	__acpi_power_off(resource);
+	__acpi_power_on(resource);
+
+	/*
+	 * Use the same delay as DSDT uses in modem _RST method.
+	 *
+	 * Otherwise we get "Unable to change power state from unknown to D0,
+	 * device inaccessible" error for the modem PCI device after thaw.
+	 *
+	 * This power resource is normally being enabled only during thaw (once)
+	 * so this wait is not a performance issue.
+	 */
+	msleep(200);
+}
+
 void acpi_resume_power_resources(void)
 {
 	struct acpi_power_resource *resource;
@@ -990,11 +1035,13 @@ void acpi_resume_power_resources(void)
 	mutex_lock(&power_resource_list_lock);
 
 	list_for_each_entry(resource, &acpi_power_resource_list, list_node) {
-		int result, state;
+		int result;
+		u8 state;
 
 		mutex_lock(&resource->resource_lock);
 
-		result = acpi_power_get_state(resource->device.handle, &state);
+		resource->state = ACPI_POWER_RESOURCE_STATE_UNKNOWN;
+		result = acpi_power_get_state(resource, &state);
 		if (result) {
 			mutex_unlock(&resource->resource_lock);
 			continue;
@@ -1002,8 +1049,14 @@ void acpi_resume_power_resources(void)
 
 		if (state == ACPI_POWER_RESOURCE_STATE_OFF
 		    && resource->ref_count) {
-			dev_info(&resource->device.dev, "Turning ON\n");
-			__acpi_power_on(resource);
+			if (hp_eb_gp12pxp_quirk &&
+			    resource_is_gp12pxp(resource->device.handle)) {
+				acpi_resume_on_eb_gp12pxp(resource);
+			} else {
+				acpi_handle_debug(resource->device.handle,
+						  "Turning ON\n");
+				__acpi_power_on(resource);
+			}
 		}
 
 		mutex_unlock(&resource->resource_lock);
@@ -1011,27 +1064,76 @@ void acpi_resume_power_resources(void)
 
 	mutex_unlock(&power_resource_list_lock);
 }
+#endif
 
+static const struct dmi_system_id dmi_hp_elitebook_gp12pxp_quirk[] = {
+/*
+ * This laptop (and possibly similar models too) has power resource called
+ * "GP12.PXP_" for its WWAN modem.
+ *
+ * For this power resource to turn ON power for the modem it needs certain
+ * internal flag called "ONEN" to be set.
+ * This flag only gets set from this power resource "_OFF" method, while the
+ * actual modem power gets turned off during suspend by "GP12.PTS" method
+ * called from the global "_PTS" (Prepare To Sleep) method.
+ * On the other hand, this power resource "_OFF" method implementation just
+ * sets the aforementioned flag without actually doing anything else (it
+ * doesn't contain any code to actually turn off power).
+ *
+ * The above means that when upon hibernation finish we try to set this
+ * power resource back ON since its "_STA" method returns 0 (while the resource
+ * is still considered in use) its "_ON" method won't do anything since
+ * that "ONEN" flag is not set.
+ * Overall, this means the modem is dead until laptop is rebooted since its
+ * power has been cut by "_PTS" and its PCI configuration was lost and not able
+ * to be restored.
+ *
+ * The easiest way to workaround the issue is to call this power resource
+ * "_OFF" method before calling the "_ON" method to make sure the "ONEN"
+ * flag gets properly set.
+ */
+	{
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
+			DMI_MATCH(DMI_PRODUCT_NAME, "HP EliteBook 855 G7 Notebook PC"),
+		},
+	},
+	{}
+};
+
+static const struct dmi_system_id dmi_leave_unused_power_resources_on[] = {
+	{
+		/*
+		 * The Toshiba Click Mini has a CPR3 power-resource which must
+		 * be on for the touchscreen to work, but which is not in any
+		 * _PR? lists. The other 2 affected power-resources are no-ops.
+		 */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
+			DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE Click Mini L9W-B"),
+		},
+	},
+	{}
+};
+
+/**
+ * acpi_turn_off_unused_power_resources - Turn off power resources not in use.
+ */
 void acpi_turn_off_unused_power_resources(void)
 {
 	struct acpi_power_resource *resource;
 
+	if (unused_power_resources_quirk)
+		return;
+
 	mutex_lock(&power_resource_list_lock);
 
 	list_for_each_entry_reverse(resource, &acpi_power_resource_list, list_node) {
-		int result, state;
-
 		mutex_lock(&resource->resource_lock);
 
-		result = acpi_power_get_state(resource->device.handle, &state);
-		if (result) {
-			mutex_unlock(&resource->resource_lock);
-			continue;
-		}
-
-		if (state == ACPI_POWER_RESOURCE_STATE_ON
-		    && !resource->ref_count) {
-			dev_info(&resource->device.dev, "Turning OFF\n");
+		if (!resource->ref_count &&
+		    resource->state == ACPI_POWER_RESOURCE_STATE_ON) {
+			acpi_handle_debug(resource->device.handle, "Turning OFF\n");
 			__acpi_power_off(resource);
 		}
 
@@ -1040,4 +1142,10 @@ void acpi_turn_off_unused_power_resources(void)
 
 	mutex_unlock(&power_resource_list_lock);
 }
-#endif
+
+void __init acpi_power_resources_init(void)
+{
+	hp_eb_gp12pxp_quirk = dmi_check_system(dmi_hp_elitebook_gp12pxp_quirk);
+	unused_power_resources_quirk =
+		dmi_check_system(dmi_leave_unused_power_resources_on);
+}
diff --git a/drivers/acpi/pptt.c b/drivers/acpi/pptt.c
index 4ae93350b70d..de5f8c018333 100644
--- a/drivers/acpi/pptt.c
+++ b/drivers/acpi/pptt.c
@@ -21,6 +21,25 @@
 #include <linux/cacheinfo.h>
 #include <acpi/processor.h>
 
+/*
+ * The acpi_pptt_cache_v1 in actbl2.h, which is imported from acpica,
+ * only contains the cache_id field rather than all the fields of the
+ * Cache Type Structure. Use this alternative structure until it is
+ * resolved in acpica.
+ */
+struct acpi_pptt_cache_v1_full {
+	struct acpi_subtable_header header;
+	u16 reserved;
+	u32 flags;
+	u32 next_level_of_cache;
+	u32 size;
+	u32 number_of_sets;
+	u8 associativity;
+	u8 attributes;
+	u16 line_size;
+	u32 cache_id;
+} __packed;
+
 static struct acpi_subtable_header *fetch_pptt_subtable(struct acpi_table_header *table_hdr,
 							u32 pptt_ref)
 {
@@ -56,6 +75,18 @@ static struct acpi_pptt_cache *fetch_pptt_cache(struct acpi_table_header *table_
 	return (struct acpi_pptt_cache *)fetch_pptt_subtable(table_hdr, pptt_ref);
 }
 
+static struct acpi_pptt_cache_v1_full *upgrade_pptt_cache(struct acpi_pptt_cache *cache)
+{
+	if (cache->header.length < sizeof(struct acpi_pptt_cache_v1_full))
+		return NULL;
+
+	/* No use for v1 if the only additional field is invalid */
+	if (!(cache->flags & ACPI_PPTT_CACHE_ID_VALID))
+		return NULL;
+
+	return (struct acpi_pptt_cache_v1_full *)cache;
+}
+
 static struct acpi_subtable_header *acpi_get_pptt_resource(struct acpi_table_header *table_hdr,
 							   struct acpi_pptt_processor *node,
 							   int resource)
@@ -81,6 +112,7 @@ static inline bool acpi_pptt_match_type(int table_type, int type)
  * acpi_pptt_walk_cache() - Attempt to find the requested acpi_pptt_cache
  * @table_hdr: Pointer to the head of the PPTT table
  * @local_level: passed res reflects this cache level
+ * @split_levels: Number of split cache levels (data/instruction).
  * @res: cache resource in the PPTT we want to walk
  * @found: returns a pointer to the requested level if found
  * @level: the requested cache level
@@ -100,6 +132,7 @@ static inline bool acpi_pptt_match_type(int table_type, int type)
  */
 static unsigned int acpi_pptt_walk_cache(struct acpi_table_header *table_hdr,
 					 unsigned int local_level,
+					 unsigned int *split_levels,
 					 struct acpi_subtable_header *res,
 					 struct acpi_pptt_cache **found,
 					 unsigned int level, int type)
@@ -113,8 +146,17 @@ static unsigned int acpi_pptt_walk_cache(struct acpi_table_header *table_hdr,
 	while (cache) {
 		local_level++;
 
+		if (!(cache->flags & ACPI_PPTT_CACHE_TYPE_VALID)) {
+			cache = fetch_pptt_cache(table_hdr, cache->next_level_of_cache);
+			continue;
+		}
+
+		if (split_levels &&
+		    (acpi_pptt_match_type(cache->attributes, ACPI_PPTT_CACHE_TYPE_DATA) ||
+		     acpi_pptt_match_type(cache->attributes, ACPI_PPTT_CACHE_TYPE_INSTR)))
+			*split_levels = local_level;
+
 		if (local_level == level &&
-		    cache->flags & ACPI_PPTT_CACHE_TYPE_VALID &&
 		    acpi_pptt_match_type(cache->attributes, type)) {
 			if (*found != NULL && cache != *found)
 				pr_warn("Found duplicate cache level/type unable to determine uniqueness\n");
@@ -135,8 +177,8 @@ static unsigned int acpi_pptt_walk_cache(struct acpi_table_header *table_hdr,
 static struct acpi_pptt_cache *
 acpi_find_cache_level(struct acpi_table_header *table_hdr,
 		      struct acpi_pptt_processor *cpu_node,
-		      unsigned int *starting_level, unsigned int level,
-		      int type)
+		      unsigned int *starting_level, unsigned int *split_levels,
+		      unsigned int level, int type)
 {
 	struct acpi_subtable_header *res;
 	unsigned int number_of_levels = *starting_level;
@@ -149,7 +191,8 @@ acpi_find_cache_level(struct acpi_table_header *table_hdr,
 		resource++;
 
 		local_level = acpi_pptt_walk_cache(table_hdr, *starting_level,
-						   res, &ret, level, type);
+						   split_levels, res, &ret,
+						   level, type);
 		/*
 		 * we are looking for the max depth. Since its potentially
 		 * possible for a given node to have resources with differing
@@ -165,29 +208,33 @@ acpi_find_cache_level(struct acpi_table_header *table_hdr,
 }
 
 /**
- * acpi_count_levels() - Given a PPTT table, and a CPU node, count the caches
+ * acpi_count_levels() - Given a PPTT table, and a CPU node, count the
+ * total number of levels and split cache levels (data/instruction).
  * @table_hdr: Pointer to the head of the PPTT table
  * @cpu_node: processor node we wish to count caches for
+ * @split_levels:	Number of split cache levels (data/instruction) if
+ *			success. Can by NULL.
  *
+ * Return: number of levels.
  * Given a processor node containing a processing unit, walk into it and count
  * how many levels exist solely for it, and then walk up each level until we hit
  * the root node (ignore the package level because it may be possible to have
- * caches that exist across packages). Count the number of cache levels that
- * exist at each level on the way up.
- *
- * Return: Total number of levels found.
+ * caches that exist across packages). Count the number of cache levels and
+ * split cache levels (data/instruction) that exist at each level on the way
+ * up.
  */
 static int acpi_count_levels(struct acpi_table_header *table_hdr,
-			     struct acpi_pptt_processor *cpu_node)
+			     struct acpi_pptt_processor *cpu_node,
+			     unsigned int *split_levels)
 {
-	int total_levels = 0;
+	int current_level = 0;
 
 	do {
-		acpi_find_cache_level(table_hdr, cpu_node, &total_levels, 0, 0);
+		acpi_find_cache_level(table_hdr, cpu_node, &current_level, split_levels, 0, 0);
 		cpu_node = fetch_pptt_node(table_hdr, cpu_node->parent);
 	} while (cpu_node);
 
-	return total_levels;
+	return current_level;
 }
 
 /**
@@ -217,18 +264,20 @@ static int acpi_pptt_leaf_node(struct acpi_table_header *table_hdr,
 	node_entry = ACPI_PTR_DIFF(node, table_hdr);
 	entry = ACPI_ADD_PTR(struct acpi_subtable_header, table_hdr,
 			     sizeof(struct acpi_table_pptt));
-	proc_sz = sizeof(struct acpi_pptt_processor *);
+	proc_sz = sizeof(struct acpi_pptt_processor);
 
-	while ((unsigned long)entry + proc_sz < table_end) {
+	/* ignore subtable types that are smaller than a processor node */
+	while ((unsigned long)entry + proc_sz <= table_end) {
 		cpu_node = (struct acpi_pptt_processor *)entry;
+
 		if (entry->type == ACPI_PPTT_TYPE_PROCESSOR &&
 		    cpu_node->parent == node_entry)
 			return 0;
 		if (entry->length == 0)
 			return 0;
+
 		entry = ACPI_ADD_PTR(struct acpi_subtable_header, entry,
 				     entry->length);
-
 	}
 	return 1;
 }
@@ -258,18 +307,21 @@ static struct acpi_pptt_processor *acpi_find_processor_node(struct acpi_table_he
 	table_end = (unsigned long)table_hdr + table_hdr->length;
 	entry = ACPI_ADD_PTR(struct acpi_subtable_header, table_hdr,
 			     sizeof(struct acpi_table_pptt));
-	proc_sz = sizeof(struct acpi_pptt_processor *);
+	proc_sz = sizeof(struct acpi_pptt_processor);
 
 	/* find the processor structure associated with this cpuid */
-	while ((unsigned long)entry + proc_sz < table_end) {
+	while ((unsigned long)entry + proc_sz <= table_end) {
 		cpu_node = (struct acpi_pptt_processor *)entry;
 
 		if (entry->length == 0) {
 			pr_warn("Invalid zero length subtable\n");
 			break;
 		}
+		/* entry->length may not equal proc_sz, revalidate the processor structure length */
 		if (entry->type == ACPI_PPTT_TYPE_PROCESSOR &&
 		    acpi_cpu_id == cpu_node->acpi_processor_id &&
+		    (unsigned long)entry + entry->length <= table_end &&
+		    entry->length == proc_sz + cpu_node->number_of_priv_resources * sizeof(u32) &&
 		     acpi_pptt_leaf_node(table_hdr, cpu_node)) {
 			return (struct acpi_pptt_processor *)entry;
 		}
@@ -281,19 +333,6 @@ static struct acpi_pptt_processor *acpi_find_processor_node(struct acpi_table_he
 	return NULL;
 }
 
-static int acpi_find_cache_levels(struct acpi_table_header *table_hdr,
-				  u32 acpi_cpu_id)
-{
-	int number_of_levels = 0;
-	struct acpi_pptt_processor *cpu;
-
-	cpu = acpi_find_processor_node(table_hdr, acpi_cpu_id);
-	if (cpu)
-		number_of_levels = acpi_count_levels(table_hdr, cpu);
-
-	return number_of_levels;
-}
-
 static u8 acpi_cache_type(enum cache_type type)
 {
 	switch (type) {
@@ -334,7 +373,7 @@ static struct acpi_pptt_cache *acpi_find_cache_node(struct acpi_table_header *ta
 
 	while (cpu_node && !found) {
 		found = acpi_find_cache_level(table_hdr, cpu_node,
-					      &total_levels, level, acpi_type);
+					      &total_levels, NULL, level, acpi_type);
 		*node = cpu_node;
 		cpu_node = fetch_pptt_node(table_hdr, cpu_node->parent);
 	}
@@ -358,6 +397,8 @@ static void update_cache_properties(struct cacheinfo *this_leaf,
 				    struct acpi_pptt_cache *found_cache,
 				    struct acpi_pptt_processor *cpu_node)
 {
+	struct acpi_pptt_cache_v1_full *found_cache_v1;
+
 	this_leaf->fw_token = cpu_node;
 	if (found_cache->flags & ACPI_PPTT_SIZE_PROPERTY_VALID)
 		this_leaf->size = found_cache->size;
@@ -405,6 +446,12 @@ static void update_cache_properties(struct cacheinfo *this_leaf,
 	if (this_leaf->type == CACHE_TYPE_NOCACHE &&
 	    found_cache->flags & ACPI_PPTT_CACHE_TYPE_VALID)
 		this_leaf->type = CACHE_TYPE_UNIFIED;
+
+	found_cache_v1 = upgrade_pptt_cache(found_cache);
+	if (found_cache_v1) {
+		this_leaf->id = found_cache_v1->cache_id;
+		this_leaf->attributes |= CACHE_ID;
+	}
 }
 
 static void cache_setup_acpi_cpu(struct acpi_table_header *table,
@@ -425,9 +472,8 @@ static void cache_setup_acpi_cpu(struct acpi_table_header *table,
 						   &cpu_node);
 		pr_debug("found = %p %p\n", found_cache, cpu_node);
 		if (found_cache)
-			update_cache_properties(this_leaf,
-						found_cache,
-						cpu_node);
+			update_cache_properties(this_leaf, found_cache,
+						ACPI_TO_POINTER(ACPI_PTR_DIFF(cpu_node, table)));
 
 		index++;
 	}
@@ -522,21 +568,40 @@ static int topology_get_acpi_cpu_tag(struct acpi_table_header *table,
 	return -ENOENT;
 }
 
+
+static struct acpi_table_header *acpi_get_pptt(void)
+{
+	static struct acpi_table_header *pptt;
+	static bool is_pptt_checked;
+	acpi_status status;
+
+	/*
+	 * PPTT will be used at runtime on every CPU hotplug in path, so we
+	 * don't need to call acpi_put_table() to release the table mapping.
+	 */
+	if (!pptt && !is_pptt_checked) {
+		status = acpi_get_table(ACPI_SIG_PPTT, 0, &pptt);
+		if (ACPI_FAILURE(status))
+			acpi_pptt_warn_missing();
+
+		is_pptt_checked = true;
+	}
+
+	return pptt;
+}
+
 static int find_acpi_cpu_topology_tag(unsigned int cpu, int level, int flag)
 {
 	struct acpi_table_header *table;
-	acpi_status status;
 	int retval;
 
-	status = acpi_get_table(ACPI_SIG_PPTT, 0, &table);
-	if (ACPI_FAILURE(status)) {
-		acpi_pptt_warn_missing();
+	table = acpi_get_pptt();
+	if (!table)
 		return -ENOENT;
-	}
+
 	retval = topology_get_acpi_cpu_tag(table, cpu, level, flag);
 	pr_debug("Topology Setup ACPI CPU %d, level %d ret = %d\n",
 		 cpu, level, retval);
-	acpi_put_table(table);
 
 	return retval;
 }
@@ -557,16 +622,13 @@ static int find_acpi_cpu_topology_tag(unsigned int cpu, int level, int flag)
 static int check_acpi_cpu_flag(unsigned int cpu, int rev, u32 flag)
 {
 	struct acpi_table_header *table;
-	acpi_status status;
 	u32 acpi_cpu_id = get_acpi_id_for_cpu(cpu);
 	struct acpi_pptt_processor *cpu_node = NULL;
 	int ret = -ENOENT;
 
-	status = acpi_get_table(ACPI_SIG_PPTT, 0, &table);
-	if (ACPI_FAILURE(status)) {
-		acpi_pptt_warn_missing();
-		return ret;
-	}
+	table = acpi_get_pptt();
+	if (!table)
+		return -ENOENT;
 
 	if (table->revision >= rev)
 		cpu_node = acpi_find_processor_node(table, acpi_cpu_id);
@@ -574,41 +636,52 @@ static int check_acpi_cpu_flag(unsigned int cpu, int rev, u32 flag)
 	if (cpu_node)
 		ret = (cpu_node->flags & flag) != 0;
 
-	acpi_put_table(table);
-
 	return ret;
 }
 
 /**
- * acpi_find_last_cache_level() - Determines the number of cache levels for a PE
+ * acpi_get_cache_info() - Determine the number of cache levels and
+ * split cache levels (data/instruction) and for a PE.
  * @cpu: Kernel logical CPU number
+ * @levels: Number of levels if success.
+ * @split_levels:	Number of levels being split (i.e. data/instruction)
+ *			if success. Can by NULL.
  *
  * Given a logical CPU number, returns the number of levels of cache represented
  * in the PPTT. Errors caused by lack of a PPTT table, or otherwise, return 0
  * indicating we didn't find any cache levels.
  *
- * Return: Cache levels visible to this core.
+ * Return: -ENOENT if no PPTT table or no PPTT processor struct found.
+ *	   0 on success.
  */
-int acpi_find_last_cache_level(unsigned int cpu)
+int acpi_get_cache_info(unsigned int cpu, unsigned int *levels,
+			unsigned int *split_levels)
 {
-	u32 acpi_cpu_id;
+	struct acpi_pptt_processor *cpu_node;
 	struct acpi_table_header *table;
-	int number_of_levels = 0;
-	acpi_status status;
+	u32 acpi_cpu_id;
+
+	*levels = 0;
+	if (split_levels)
+		*split_levels = 0;
+
+	table = acpi_get_pptt();
+	if (!table)
+		return -ENOENT;
 
-	pr_debug("Cache Setup find last level CPU=%d\n", cpu);
+	pr_debug("Cache Setup: find cache levels for CPU=%d\n", cpu);
 
 	acpi_cpu_id = get_acpi_id_for_cpu(cpu);
-	status = acpi_get_table(ACPI_SIG_PPTT, 0, &table);
-	if (ACPI_FAILURE(status)) {
-		acpi_pptt_warn_missing();
-	} else {
-		number_of_levels = acpi_find_cache_levels(table, acpi_cpu_id);
-		acpi_put_table(table);
-	}
-	pr_debug("Cache Setup find last level level=%d\n", number_of_levels);
+	cpu_node = acpi_find_processor_node(table, acpi_cpu_id);
+	if (!cpu_node)
+		return -ENOENT;
 
-	return number_of_levels;
+	*levels = acpi_count_levels(table, cpu_node, split_levels);
+
+	pr_debug("Cache Setup: last_level=%d split_levels=%d\n",
+		 *levels, split_levels ? *split_levels : -1);
+
+	return 0;
 }
 
 /**
@@ -627,20 +700,16 @@ int acpi_find_last_cache_level(unsigned int cpu)
 int cache_setup_acpi(unsigned int cpu)
 {
 	struct acpi_table_header *table;
-	acpi_status status;
 
-	pr_debug("Cache Setup ACPI CPU %d\n", cpu);
-
-	status = acpi_get_table(ACPI_SIG_PPTT, 0, &table);
-	if (ACPI_FAILURE(status)) {
-		acpi_pptt_warn_missing();
+	table = acpi_get_pptt();
+	if (!table)
 		return -ENOENT;
-	}
+
+	pr_debug("Cache Setup ACPI CPU %d\n", cpu);
 
 	cache_setup_acpi_cpu(table, cpu);
-	acpi_put_table(table);
 
-	return status;
+	return 0;
 }
 
 /**
@@ -681,59 +750,77 @@ int find_acpi_cpu_topology(unsigned int cpu, int level)
 }
 
 /**
- * find_acpi_cpu_cache_topology() - Determine a unique cache topology value
+ * find_acpi_cpu_topology_package() - Determine a unique CPU package value
  * @cpu: Kernel logical CPU number
- * @level: The cache level for which we would like a unique ID
  *
- * Determine a unique ID for each unified cache in the system
+ * Determine a topology unique package ID for the given CPU.
+ * This ID can then be used to group peers, which will have matching ids.
+ *
+ * The search terminates when either a level is found with the PHYSICAL_PACKAGE
+ * flag set or we reach a root node.
  *
  * Return: -ENOENT if the PPTT doesn't exist, or the CPU cannot be found.
- * Otherwise returns a value which represents a unique topological feature.
+ * Otherwise returns a value which represents the package for this CPU.
  */
-int find_acpi_cpu_cache_topology(unsigned int cpu, int level)
+int find_acpi_cpu_topology_package(unsigned int cpu)
 {
-	struct acpi_table_header *table;
-	struct acpi_pptt_cache *found_cache;
-	acpi_status status;
-	u32 acpi_cpu_id = get_acpi_id_for_cpu(cpu);
-	struct acpi_pptt_processor *cpu_node = NULL;
-	int ret = -1;
-
-	status = acpi_get_table(ACPI_SIG_PPTT, 0, &table);
-	if (ACPI_FAILURE(status)) {
-		acpi_pptt_warn_missing();
-		return -ENOENT;
-	}
-
-	found_cache = acpi_find_cache_node(table, acpi_cpu_id,
-					   CACHE_TYPE_UNIFIED,
-					   level,
-					   &cpu_node);
-	if (found_cache)
-		ret = ACPI_PTR_DIFF(cpu_node, table);
-
-	acpi_put_table(table);
-
-	return ret;
+	return find_acpi_cpu_topology_tag(cpu, PPTT_ABORT_PACKAGE,
+					  ACPI_PPTT_PHYSICAL_PACKAGE);
 }
 
 /**
- * find_acpi_cpu_topology_package() - Determine a unique CPU package value
+ * find_acpi_cpu_topology_cluster() - Determine a unique CPU cluster value
  * @cpu: Kernel logical CPU number
  *
- * Determine a topology unique package ID for the given CPU.
+ * Determine a topology unique cluster ID for the given CPU/thread.
  * This ID can then be used to group peers, which will have matching ids.
  *
- * The search terminates when either a level is found with the PHYSICAL_PACKAGE
- * flag set or we reach a root node.
+ * The cluster, if present is the level of topology above CPUs. In a
+ * multi-thread CPU, it will be the level above the CPU, not the thread.
+ * It may not exist in single CPU systems. In simple multi-CPU systems,
+ * it may be equal to the package topology level.
  *
- * Return: -ENOENT if the PPTT doesn't exist, or the CPU cannot be found.
+ * Return: -ENOENT if the PPTT doesn't exist, the CPU cannot be found
+ * or there is no toplogy level above the CPU..
  * Otherwise returns a value which represents the package for this CPU.
  */
-int find_acpi_cpu_topology_package(unsigned int cpu)
+
+int find_acpi_cpu_topology_cluster(unsigned int cpu)
 {
-	return find_acpi_cpu_topology_tag(cpu, PPTT_ABORT_PACKAGE,
-					  ACPI_PPTT_PHYSICAL_PACKAGE);
+	struct acpi_table_header *table;
+	struct acpi_pptt_processor *cpu_node, *cluster_node;
+	u32 acpi_cpu_id;
+	int retval;
+	int is_thread;
+
+	table = acpi_get_pptt();
+	if (!table)
+		return -ENOENT;
+
+	acpi_cpu_id = get_acpi_id_for_cpu(cpu);
+	cpu_node = acpi_find_processor_node(table, acpi_cpu_id);
+	if (!cpu_node || !cpu_node->parent)
+		return -ENOENT;
+
+	is_thread = cpu_node->flags & ACPI_PPTT_ACPI_PROCESSOR_IS_THREAD;
+	cluster_node = fetch_pptt_node(table, cpu_node->parent);
+	if (!cluster_node)
+		return -ENOENT;
+
+	if (is_thread) {
+		if (!cluster_node->parent)
+			return -ENOENT;
+
+		cluster_node = fetch_pptt_node(table, cluster_node->parent);
+		if (!cluster_node)
+			return -ENOENT;
+	}
+	if (cluster_node->flags & ACPI_PPTT_ACPI_PROCESSOR_ID_VALID)
+		retval = cluster_node->acpi_processor_id;
+	else
+		retval = ACPI_PTR_DIFF(cluster_node, table);
+
+	return retval;
 }
 
 /**
@@ -761,3 +848,218 @@ int find_acpi_cpu_topology_hetero_id(unsigned int cpu)
 	return find_acpi_cpu_topology_tag(cpu, PPTT_ABORT_PACKAGE,
 					  ACPI_PPTT_ACPI_IDENTICAL);
 }
+
+/**
+ * acpi_pptt_get_child_cpus() - Find all the CPUs below a PPTT
+ * processor hierarchy node
+ *
+ * @table_hdr:		A reference to the PPTT table
+ * @parent_node:	A pointer to the processor hierarchy node in the
+ *			table_hdr
+ * @cpus:		A cpumask to fill with the CPUs below @parent_node
+ *
+ * Walks up the PPTT from every possible CPU to find if the provided
+ * @parent_node is a parent of this CPU.
+ */
+static void acpi_pptt_get_child_cpus(struct acpi_table_header *table_hdr,
+				     struct acpi_pptt_processor *parent_node,
+				     cpumask_t *cpus)
+{
+	struct acpi_pptt_processor *cpu_node;
+	u32 acpi_id;
+	int cpu;
+
+	cpumask_clear(cpus);
+
+	for_each_possible_cpu(cpu) {
+		acpi_id = get_acpi_id_for_cpu(cpu);
+		cpu_node = acpi_find_processor_node(table_hdr, acpi_id);
+
+		while (cpu_node) {
+			if (cpu_node == parent_node) {
+				cpumask_set_cpu(cpu, cpus);
+				break;
+			}
+			cpu_node = fetch_pptt_node(table_hdr, cpu_node->parent);
+		}
+	}
+}
+
+/**
+ * acpi_pptt_get_cpus_from_container() - Populate a cpumask with all CPUs in a
+ *                                       processor container
+ * @acpi_cpu_id:	The UID of the processor container
+ * @cpus:		The resulting CPU mask
+ *
+ * Find the specified Processor Container, and fill @cpus with all the cpus
+ * below it.
+ *
+ * Not all 'Processor Hierarchy' entries in the PPTT are either a CPU
+ * or a Processor Container, they may exist purely to describe a
+ * Private resource. CPUs have to be leaves, so a Processor Container
+ * is a non-leaf that has the 'ACPI Processor ID valid' flag set.
+ */
+void acpi_pptt_get_cpus_from_container(u32 acpi_cpu_id, cpumask_t *cpus)
+{
+	struct acpi_table_header *table_hdr;
+	struct acpi_subtable_header *entry;
+	unsigned long table_end;
+	u32 proc_sz;
+
+	cpumask_clear(cpus);
+
+	table_hdr = acpi_get_pptt();
+	if (!table_hdr)
+		return;
+
+	table_end = (unsigned long)table_hdr + table_hdr->length;
+	entry = ACPI_ADD_PTR(struct acpi_subtable_header, table_hdr,
+			     sizeof(struct acpi_table_pptt));
+	proc_sz = sizeof(struct acpi_pptt_processor);
+	while ((unsigned long)entry + proc_sz <= table_end) {
+		if (entry->type == ACPI_PPTT_TYPE_PROCESSOR) {
+			struct acpi_pptt_processor *cpu_node;
+
+			cpu_node = (struct acpi_pptt_processor *)entry;
+			if (cpu_node->flags & ACPI_PPTT_ACPI_PROCESSOR_ID_VALID &&
+			    !acpi_pptt_leaf_node(table_hdr, cpu_node) &&
+			    cpu_node->acpi_processor_id == acpi_cpu_id) {
+				acpi_pptt_get_child_cpus(table_hdr, cpu_node, cpus);
+				break;
+			}
+		}
+		entry = ACPI_ADD_PTR(struct acpi_subtable_header, entry,
+				     entry->length);
+	}
+}
+
+/**
+ * find_acpi_cache_level_from_id() - Get the level of the specified cache
+ * @cache_id: The id field of the cache
+ *
+ * Determine the level relative to any CPU for the cache identified by
+ * cache_id. This allows the property to be found even if the CPUs are offline.
+ *
+ * The returned level can be used to group caches that are peers.
+ *
+ * The PPTT table must be rev 3 or later.
+ *
+ * If one CPU's L2 is shared with another CPU as L3, this function will return
+ * an unpredictable value.
+ *
+ * Return: -ENOENT if the PPTT doesn't exist, the revision isn't supported or
+ * the cache cannot be found.
+ * Otherwise returns a value which represents the level of the specified cache.
+ */
+int find_acpi_cache_level_from_id(u32 cache_id)
+{
+	int cpu;
+	struct acpi_table_header *table;
+
+	table = acpi_get_pptt();
+	if (!table)
+		return -ENOENT;
+
+	if (table->revision < 3)
+		return -ENOENT;
+
+	for_each_possible_cpu(cpu) {
+		bool empty;
+		int level = 1;
+		u32 acpi_cpu_id = get_acpi_id_for_cpu(cpu);
+		struct acpi_pptt_cache *cache;
+		struct acpi_pptt_processor *cpu_node;
+
+		cpu_node = acpi_find_processor_node(table, acpi_cpu_id);
+		if (!cpu_node)
+			continue;
+
+		do {
+			int cache_type[] = {CACHE_TYPE_INST, CACHE_TYPE_DATA, CACHE_TYPE_UNIFIED};
+
+			empty = true;
+			for (int i = 0; i < ARRAY_SIZE(cache_type); i++) {
+				struct acpi_pptt_cache_v1_full *cache_v1;
+
+				cache = acpi_find_cache_node(table, acpi_cpu_id, cache_type[i],
+							     level, &cpu_node);
+				if (!cache)
+					continue;
+
+				empty = false;
+
+				cache_v1 = upgrade_pptt_cache(cache);
+				if (cache_v1 && cache_v1->cache_id == cache_id)
+					return level;
+			}
+			level++;
+		} while (!empty);
+	}
+
+	return -ENOENT;
+}
+
+/**
+ * acpi_pptt_get_cpumask_from_cache_id() - Get the cpus associated with the
+ *					   specified cache
+ * @cache_id: The id field of the cache
+ * @cpus: Where to build the cpumask
+ *
+ * Determine which CPUs are below this cache in the PPTT. This allows the property
+ * to be found even if the CPUs are offline.
+ *
+ * The PPTT table must be rev 3 or later,
+ *
+ * Return: -ENOENT if the PPTT doesn't exist, or the cache cannot be found.
+ * Otherwise returns 0 and sets the cpus in the provided cpumask.
+ */
+int acpi_pptt_get_cpumask_from_cache_id(u32 cache_id, cpumask_t *cpus)
+{
+	int cpu;
+	struct acpi_table_header *table;
+
+	cpumask_clear(cpus);
+
+	table = acpi_get_pptt();
+	if (!table)
+		return -ENOENT;
+
+	if (table->revision < 3)
+		return -ENOENT;
+
+	for_each_possible_cpu(cpu) {
+		bool empty;
+		int level = 1;
+		u32 acpi_cpu_id = get_acpi_id_for_cpu(cpu);
+		struct acpi_pptt_cache *cache;
+		struct acpi_pptt_processor *cpu_node;
+
+		cpu_node = acpi_find_processor_node(table, acpi_cpu_id);
+		if (!cpu_node)
+			continue;
+
+		do {
+			int cache_type[] = {CACHE_TYPE_INST, CACHE_TYPE_DATA, CACHE_TYPE_UNIFIED};
+
+			empty = true;
+			for (int i = 0; i < ARRAY_SIZE(cache_type); i++) {
+				struct acpi_pptt_cache_v1_full *cache_v1;
+
+				cache = acpi_find_cache_node(table, acpi_cpu_id, cache_type[i],
+							     level, &cpu_node);
+
+				if (!cache)
+					continue;
+
+				empty = false;
+
+				cache_v1 = upgrade_pptt_cache(cache);
+				if (cache_v1 && cache_v1->cache_id == cache_id)
+					cpumask_set_cpu(cpu, cpus);
+			}
+			level++;
+		} while (!empty);
+	}
+
+	return 0;
+}
diff --git a/drivers/acpi/prmt.c b/drivers/acpi/prmt.c
new file mode 100644
index 000000000000..7b8b5d2015ec
--- /dev/null
+++ b/drivers/acpi/prmt.c
@@ -0,0 +1,424 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Author: Erik Kaneda <erik.kaneda@intel.com>
+ * Copyright 2020 Intel Corporation
+ *
+ * prmt.c
+ *
+ * Each PRM service is an executable that is run in a restricted environment
+ * that is invoked by writing to the PlatformRtMechanism OperationRegion from
+ * AML bytecode.
+ *
+ * init_prmt initializes the Platform Runtime Mechanism (PRM) services by
+ * processing data in the PRMT as well as registering an ACPI OperationRegion
+ * handler for the PlatformRtMechanism subtype.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/efi.h>
+#include <linux/acpi.h>
+#include <linux/prmt.h>
+#include <asm/efi.h>
+
+#pragma pack(1)
+struct prm_mmio_addr_range {
+	u64 phys_addr;
+	u64 virt_addr;
+	u32 length;
+};
+
+struct prm_mmio_info {
+	u64 mmio_count;
+	struct prm_mmio_addr_range addr_ranges[];
+};
+
+struct prm_buffer {
+	u8 prm_status;
+	u64 efi_status;
+	u8 prm_cmd;
+	guid_t handler_guid;
+};
+
+struct prm_context_buffer {
+	char signature[ACPI_NAMESEG_SIZE];
+	u16 revision;
+	u16 reserved;
+	guid_t identifier;
+	u64 static_data_buffer;
+	struct prm_mmio_info *mmio_ranges;
+};
+#pragma pack()
+
+static LIST_HEAD(prm_module_list);
+
+struct prm_handler_info {
+	efi_guid_t guid;
+	efi_status_t (__efiapi *handler_addr)(u64, void *);
+	u64 static_data_buffer_addr;
+	u64 acpi_param_buffer_addr;
+
+	struct list_head handler_list;
+};
+
+struct prm_module_info {
+	guid_t guid;
+	u16 major_rev;
+	u16 minor_rev;
+	u16 handler_count;
+	struct prm_mmio_info *mmio_info;
+	bool updatable;
+
+	struct list_head module_list;
+	struct prm_handler_info handlers[] __counted_by(handler_count);
+};
+
+static u64 efi_pa_va_lookup(efi_guid_t *guid, u64 pa)
+{
+	efi_memory_desc_t *md;
+	u64 pa_offset = pa & ~PAGE_MASK;
+	u64 page = pa & PAGE_MASK;
+
+	for_each_efi_memory_desc(md) {
+		if ((md->attribute & EFI_MEMORY_RUNTIME) &&
+		    (md->phys_addr < pa && pa < md->phys_addr + PAGE_SIZE * md->num_pages)) {
+			return pa_offset + md->virt_addr + page - md->phys_addr;
+		}
+	}
+
+	return 0;
+}
+
+#define get_first_handler(a) ((struct acpi_prmt_handler_info *) ((char *) (a) + a->handler_info_offset))
+#define get_next_handler(a) ((struct acpi_prmt_handler_info *) (sizeof(struct acpi_prmt_handler_info) + (char *) a))
+
+static int __init
+acpi_parse_prmt(union acpi_subtable_headers *header, const unsigned long end)
+{
+	struct acpi_prmt_module_info *module_info;
+	struct acpi_prmt_handler_info *handler_info;
+	struct prm_handler_info *th;
+	struct prm_module_info *tm;
+	u64 *mmio_count;
+	u64 cur_handler = 0;
+	u32 module_info_size = 0;
+	u64 mmio_range_size = 0;
+	void *temp_mmio;
+
+	module_info = (struct acpi_prmt_module_info *) header;
+	module_info_size = struct_size(tm, handlers, module_info->handler_info_count);
+	tm = kmalloc(module_info_size, GFP_KERNEL);
+	if (!tm)
+		goto parse_prmt_out1;
+
+	guid_copy(&tm->guid, (guid_t *) module_info->module_guid);
+	tm->major_rev = module_info->major_rev;
+	tm->minor_rev = module_info->minor_rev;
+	tm->handler_count = module_info->handler_info_count;
+	tm->updatable = true;
+
+	if (module_info->mmio_list_pointer) {
+		/*
+		 * Each module is associated with a list of addr
+		 * ranges that it can use during the service
+		 */
+		mmio_count = (u64 *) memremap(module_info->mmio_list_pointer, 8, MEMREMAP_WB);
+		if (!mmio_count)
+			goto parse_prmt_out2;
+
+		mmio_range_size = struct_size(tm->mmio_info, addr_ranges, *mmio_count);
+		tm->mmio_info = kmalloc(mmio_range_size, GFP_KERNEL);
+		if (!tm->mmio_info)
+			goto parse_prmt_out3;
+
+		temp_mmio = memremap(module_info->mmio_list_pointer, mmio_range_size, MEMREMAP_WB);
+		if (!temp_mmio)
+			goto parse_prmt_out4;
+		memmove(tm->mmio_info, temp_mmio, mmio_range_size);
+	} else {
+		tm->mmio_info = kmalloc(sizeof(*tm->mmio_info), GFP_KERNEL);
+		if (!tm->mmio_info)
+			goto parse_prmt_out2;
+
+		tm->mmio_info->mmio_count = 0;
+	}
+
+	INIT_LIST_HEAD(&tm->module_list);
+	list_add(&tm->module_list, &prm_module_list);
+
+	handler_info = get_first_handler(module_info);
+	do {
+		th = &tm->handlers[cur_handler];
+
+		guid_copy(&th->guid, (guid_t *)handler_info->handler_guid);
+
+		/*
+		 * Print an error message if handler_address is NULL, the parse of VA also
+		 * can be skipped.
+		 */
+		if (unlikely(!handler_info->handler_address)) {
+			pr_info("Skipping handler with NULL address for GUID: %pUL",
+					(guid_t *)handler_info->handler_guid);
+			continue;
+		}
+
+		th->handler_addr =
+			(void *)efi_pa_va_lookup(&th->guid, handler_info->handler_address);
+		/*
+		 * Print a warning message and skip the parse of VA if handler_addr is zero
+		 * which is not expected to ever happen.
+		 */
+		if (unlikely(!th->handler_addr)) {
+			pr_warn("Failed to find VA of handler for GUID: %pUL, PA: 0x%llx",
+				&th->guid, handler_info->handler_address);
+			continue;
+		}
+
+		th->static_data_buffer_addr =
+			efi_pa_va_lookup(&th->guid, handler_info->static_data_buffer_address);
+		/*
+		 * According to the PRM specification, static_data_buffer_address can be zero,
+		 * so avoid printing a warning message in that case.  Otherwise, if the
+		 * return value of efi_pa_va_lookup() is zero, print the message.
+		 */
+		if (unlikely(!th->static_data_buffer_addr && handler_info->static_data_buffer_address))
+			pr_warn("Failed to find VA of static data buffer for GUID: %pUL, PA: 0x%llx",
+				&th->guid, handler_info->static_data_buffer_address);
+
+		th->acpi_param_buffer_addr =
+			efi_pa_va_lookup(&th->guid, handler_info->acpi_param_buffer_address);
+
+		/*
+		 * According to the PRM specification, acpi_param_buffer_address can be zero,
+		 * so avoid printing a warning message in that case.  Otherwise, if the
+		 * return value of efi_pa_va_lookup() is zero, print the message.
+		 */
+		if (unlikely(!th->acpi_param_buffer_addr && handler_info->acpi_param_buffer_address))
+			pr_warn("Failed to find VA of acpi param buffer for GUID: %pUL, PA: 0x%llx",
+				&th->guid, handler_info->acpi_param_buffer_address);
+
+	} while (++cur_handler < tm->handler_count && (handler_info = get_next_handler(handler_info)));
+
+	return 0;
+
+parse_prmt_out4:
+	kfree(tm->mmio_info);
+parse_prmt_out3:
+	memunmap(mmio_count);
+parse_prmt_out2:
+	kfree(tm);
+parse_prmt_out1:
+	return -ENOMEM;
+}
+
+#define GET_MODULE	0
+#define GET_HANDLER	1
+
+static void *find_guid_info(const guid_t *guid, u8 mode)
+{
+	struct prm_handler_info *cur_handler;
+	struct prm_module_info *cur_module;
+	int i = 0;
+
+	list_for_each_entry(cur_module, &prm_module_list, module_list) {
+		for (i = 0; i < cur_module->handler_count; ++i) {
+			cur_handler = &cur_module->handlers[i];
+			if (guid_equal(guid, &cur_handler->guid)) {
+				if (mode == GET_MODULE)
+					return (void *)cur_module;
+				else
+					return (void *)cur_handler;
+			}
+		}
+	}
+
+	return NULL;
+}
+
+static struct prm_module_info *find_prm_module(const guid_t *guid)
+{
+	return (struct prm_module_info *)find_guid_info(guid, GET_MODULE);
+}
+
+static struct prm_handler_info *find_prm_handler(const guid_t *guid)
+{
+	return (struct prm_handler_info *) find_guid_info(guid, GET_HANDLER);
+}
+
+bool acpi_prm_handler_available(const guid_t *guid)
+{
+	return find_prm_handler(guid) && find_prm_module(guid);
+}
+EXPORT_SYMBOL_GPL(acpi_prm_handler_available);
+
+/* In-coming PRM commands */
+
+#define PRM_CMD_RUN_SERVICE		0
+#define PRM_CMD_START_TRANSACTION	1
+#define PRM_CMD_END_TRANSACTION		2
+
+/* statuses that can be passed back to ASL */
+
+#define PRM_HANDLER_SUCCESS 		0
+#define PRM_HANDLER_ERROR 		1
+#define INVALID_PRM_COMMAND 		2
+#define PRM_HANDLER_GUID_NOT_FOUND 	3
+#define UPDATE_LOCK_ALREADY_HELD 	4
+#define UPDATE_UNLOCK_WITHOUT_LOCK 	5
+
+int acpi_call_prm_handler(guid_t handler_guid, void *param_buffer)
+{
+	struct prm_handler_info *handler = find_prm_handler(&handler_guid);
+	struct prm_module_info *module = find_prm_module(&handler_guid);
+	struct prm_context_buffer context;
+	efi_status_t status;
+
+	if (!module || !handler)
+		return -ENODEV;
+
+	memset(&context, 0, sizeof(context));
+	ACPI_COPY_NAMESEG(context.signature, "PRMC");
+	context.identifier         = handler->guid;
+	context.static_data_buffer = handler->static_data_buffer_addr;
+	context.mmio_ranges        = module->mmio_info;
+
+	status = efi_call_acpi_prm_handler(handler->handler_addr,
+					   (u64)param_buffer,
+					   &context);
+
+	return efi_status_to_err(status);
+}
+EXPORT_SYMBOL_GPL(acpi_call_prm_handler);
+
+/*
+ * This is the PlatformRtMechanism opregion space handler.
+ * @function: indicates the read/write. In fact as the PlatformRtMechanism
+ * message is driven by command, only write is meaningful.
+ *
+ * @addr   : not used
+ * @bits   : not used.
+ * @value  : it is an in/out parameter. It points to the PRM message buffer.
+ * @handler_context: not used
+ */
+static acpi_status acpi_platformrt_space_handler(u32 function,
+						 acpi_physical_address addr,
+						 u32 bits, acpi_integer *value,
+						 void *handler_context,
+						 void *region_context)
+{
+	struct prm_buffer *buffer = ACPI_CAST_PTR(struct prm_buffer, value);
+	struct prm_handler_info *handler;
+	struct prm_module_info *module;
+	efi_status_t status;
+	struct prm_context_buffer context;
+
+	if (!efi_enabled(EFI_RUNTIME_SERVICES)) {
+		pr_err_ratelimited("PRM: EFI runtime services no longer available\n");
+		return AE_NO_HANDLER;
+	}
+
+	/*
+	 * The returned acpi_status will always be AE_OK. Error values will be
+	 * saved in the first byte of the PRM message buffer to be used by ASL.
+	 */
+	switch (buffer->prm_cmd) {
+	case PRM_CMD_RUN_SERVICE:
+
+		handler = find_prm_handler(&buffer->handler_guid);
+		module = find_prm_module(&buffer->handler_guid);
+		if (!handler || !module)
+			goto invalid_guid;
+
+		if (!handler->handler_addr) {
+			buffer->prm_status = PRM_HANDLER_ERROR;
+			return AE_OK;
+		}
+
+		ACPI_COPY_NAMESEG(context.signature, "PRMC");
+		context.revision = 0x0;
+		context.reserved = 0x0;
+		context.identifier = handler->guid;
+		context.static_data_buffer = handler->static_data_buffer_addr;
+		context.mmio_ranges = module->mmio_info;
+
+		status = efi_call_acpi_prm_handler(handler->handler_addr,
+						   handler->acpi_param_buffer_addr,
+						   &context);
+		if (status == EFI_SUCCESS) {
+			buffer->prm_status = PRM_HANDLER_SUCCESS;
+		} else {
+			buffer->prm_status = PRM_HANDLER_ERROR;
+			buffer->efi_status = status;
+		}
+		break;
+
+	case PRM_CMD_START_TRANSACTION:
+
+		module = find_prm_module(&buffer->handler_guid);
+		if (!module)
+			goto invalid_guid;
+
+		if (module->updatable)
+			module->updatable = false;
+		else
+			buffer->prm_status = UPDATE_LOCK_ALREADY_HELD;
+		break;
+
+	case PRM_CMD_END_TRANSACTION:
+
+		module = find_prm_module(&buffer->handler_guid);
+		if (!module)
+			goto invalid_guid;
+
+		if (module->updatable)
+			buffer->prm_status = UPDATE_UNLOCK_WITHOUT_LOCK;
+		else
+			module->updatable = true;
+		break;
+
+	default:
+
+		buffer->prm_status = INVALID_PRM_COMMAND;
+		break;
+	}
+
+	return AE_OK;
+
+invalid_guid:
+	buffer->prm_status = PRM_HANDLER_GUID_NOT_FOUND;
+	return AE_OK;
+}
+
+void __init init_prmt(void)
+{
+	struct acpi_table_header *tbl;
+	acpi_status status;
+	int mc;
+
+	status = acpi_get_table(ACPI_SIG_PRMT, 0, &tbl);
+	if (ACPI_FAILURE(status))
+		return;
+
+	mc = acpi_table_parse_entries(ACPI_SIG_PRMT, sizeof(struct acpi_table_prmt) +
+					  sizeof (struct acpi_table_prmt_header),
+					  0, acpi_parse_prmt, 0);
+	acpi_put_table(tbl);
+	/*
+	 * Return immediately if PRMT table is not present or no PRM module found.
+	 */
+	if (mc <= 0)
+		return;
+
+	pr_info("PRM: found %u modules\n", mc);
+
+	if (!efi_enabled(EFI_RUNTIME_SERVICES)) {
+		pr_err("PRM: EFI runtime services unavailable\n");
+		return;
+	}
+
+	status = acpi_install_address_space_handler(ACPI_ROOT_OBJECT,
+						    ACPI_ADR_SPACE_PLATFORM_RT,
+						    &acpi_platformrt_space_handler,
+						    NULL, NULL);
+	if (ACPI_FAILURE(status))
+		pr_alert("PRM: OperationRegion handler could not be installed\n");
+}
diff --git a/drivers/acpi/proc.c b/drivers/acpi/proc.c
index 7892980b3ce4..c08ead07252b 100644
--- a/drivers/acpi/proc.c
+++ b/drivers/acpi/proc.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 #include <linux/proc_fs.h>
 #include <linux/seq_file.h>
-#include <linux/export.h>
+#include <linux/string_choices.h>
 #include <linux/suspend.h>
 #include <linux/bcd.h>
 #include <linux/acpi.h>
@@ -10,15 +10,11 @@
 #include "sleep.h"
 #include "internal.h"
 
-#define _COMPONENT		ACPI_SYSTEM_COMPONENT
-
 /*
  * this file provides support for:
  * /proc/acpi/wakeup
  */
 
-ACPI_MODULE_NAME("sleep")
-
 static int
 acpi_system_wakeup_device_seq_show(struct seq_file *seq, void *offset)
 {
@@ -34,17 +30,16 @@ acpi_system_wakeup_device_seq_show(struct seq_file *seq, void *offset)
 		if (!dev->wakeup.flags.valid)
 			continue;
 
-		seq_printf(seq, "%s\t  S%d\t",
+		seq_printf(seq, "%s\t  S%llu\t",
 			   dev->pnp.bus_id,
-			   (u32) dev->wakeup.sleep_state);
+			   dev->wakeup.sleep_state);
 
 		mutex_lock(&dev->physical_node_lock);
 
 		if (!dev->physical_node_count) {
 			seq_printf(seq, "%c%-8s\n",
 				dev->wakeup.flags.valid ? '*' : ' ',
-				device_may_wakeup(&dev->dev) ?
-					"enabled" : "disabled");
+				str_enabled_disabled(device_may_wakeup(&dev->dev)));
 		} else {
 			struct device *ldev;
 			list_for_each_entry(entry, &dev->physical_node_list,
@@ -59,9 +54,8 @@ acpi_system_wakeup_device_seq_show(struct seq_file *seq, void *offset)
 
 				seq_printf(seq, "%c%-8s  %s:%s\n",
 					dev->wakeup.flags.valid ? '*' : ' ',
-					(device_may_wakeup(&dev->dev) ||
-					device_may_wakeup(ldev)) ?
-					"enabled" : "disabled",
+					str_enabled_disabled(device_may_wakeup(ldev) ||
+							     device_may_wakeup(&dev->dev)),
 					ldev->bus ? ldev->bus->name :
 					"no-bus", dev_name(ldev));
 				put_device(ldev);
@@ -131,7 +125,7 @@ static int
 acpi_system_wakeup_device_open_fs(struct inode *inode, struct file *file)
 {
 	return single_open(file, acpi_system_wakeup_device_seq_show,
-			   PDE_DATA(inode));
+			   pde_data(inode));
 }
 
 static const struct proc_ops acpi_system_wakeup_device_proc_ops = {
@@ -145,6 +139,5 @@ static const struct proc_ops acpi_system_wakeup_device_proc_ops = {
 void __init acpi_sleep_proc_init(void)
 {
 	/* 'wakeup device' [R/W] */
-	proc_create("wakeup", S_IFREG | S_IRUGO | S_IWUSR,
-		    acpi_root_dir, &acpi_system_wakeup_device_proc_ops);
+	proc_create("wakeup", 0644, acpi_root_dir, &acpi_system_wakeup_device_proc_ops);
 }
diff --git a/drivers/acpi/processor_core.c b/drivers/acpi/processor_core.c
index f32beb7d7882..a4498357bd16 100644
--- a/drivers/acpi/processor_core.c
+++ b/drivers/acpi/processor_core.c
@@ -14,9 +14,6 @@
 #include <linux/acpi.h>
 #include <acpi/processor.h>
 
-#define _COMPONENT		ACPI_PROCESSOR_COMPONENT
-ACPI_MODULE_NAME("processor_core");
-
 static struct acpi_table_madt *get_madt_table(void)
 {
 	static struct acpi_table_madt *madt;
@@ -57,7 +54,7 @@ static int map_x2apic_id(struct acpi_subtable_header *entry,
 	if (!(apic->lapic_flags & ACPI_MADT_ENABLED))
 		return -ENODEV;
 
-	if (device_declaration && (apic->uid == acpi_id)) {
+	if (apic->uid == acpi_id && (device_declaration || acpi_id < 255)) {
 		*apic_id = apic->local_apic_id;
 		return 0;
 	}
@@ -93,7 +90,8 @@ static int map_gicc_mpidr(struct acpi_subtable_header *entry,
 	struct acpi_madt_generic_interrupt *gicc =
 	    container_of(entry, struct acpi_madt_generic_interrupt, header);
 
-	if (!(gicc->flags & ACPI_MADT_ENABLED))
+	if (!(gicc->flags &
+	      (ACPI_MADT_ENABLED | ACPI_MADT_GICC_ONLINE_CAPABLE)))
 		return -ENODEV;
 
 	/* device_declaration means Device object in DSDT, in the
@@ -109,6 +107,56 @@ static int map_gicc_mpidr(struct acpi_subtable_header *entry,
 	return -EINVAL;
 }
 
+/*
+ * Retrieve the RISC-V hartid for the processor
+ */
+static int map_rintc_hartid(struct acpi_subtable_header *entry,
+			    int device_declaration, u32 acpi_id,
+			    phys_cpuid_t *hartid)
+{
+	struct acpi_madt_rintc *rintc =
+	    container_of(entry, struct acpi_madt_rintc, header);
+
+	if (!(rintc->flags & ACPI_MADT_ENABLED))
+		return -ENODEV;
+
+	/* device_declaration means Device object in DSDT, in the
+	 * RISC-V, logical processors are required to
+	 * have a Processor Device object in the DSDT, so we should
+	 * check device_declaration here
+	 */
+	if (device_declaration && rintc->uid == acpi_id) {
+		*hartid = rintc->hart_id;
+		return 0;
+	}
+
+	return -EINVAL;
+}
+
+/*
+ * Retrieve LoongArch CPU physical id
+ */
+static int map_core_pic_id(struct acpi_subtable_header *entry,
+		int device_declaration, u32 acpi_id, phys_cpuid_t *phys_id)
+{
+	struct acpi_madt_core_pic *core_pic =
+		container_of(entry, struct acpi_madt_core_pic, header);
+
+	if (!(core_pic->flags & ACPI_MADT_ENABLED))
+		return -ENODEV;
+
+	/* device_declaration means Device object in DSDT, in LoongArch
+	 * system, logical processor acpi_id is required in _UID property
+	 * of DSDT table, so we should check device_declaration here
+	 */
+	if (device_declaration && (core_pic->processor_id == acpi_id)) {
+		*phys_id = core_pic->core_id;
+		return 0;
+	}
+
+	return -EINVAL;
+}
+
 static phys_cpuid_t map_madt_entry(struct acpi_table_madt *madt,
 				   int type, u32 acpi_id)
 {
@@ -139,6 +187,12 @@ static phys_cpuid_t map_madt_entry(struct acpi_table_madt *madt,
 		} else if (header->type == ACPI_MADT_TYPE_GENERIC_INTERRUPT) {
 			if (!map_gicc_mpidr(header, type, acpi_id, &phys_id))
 				break;
+		} else if (header->type == ACPI_MADT_TYPE_RINTC) {
+			if (!map_rintc_hartid(header, type, acpi_id, &phys_id))
+				break;
+		} else if (header->type == ACPI_MADT_TYPE_CORE_PIC) {
+			if (!map_core_pic_id(header, type, acpi_id, &phys_id))
+				break;
 		}
 		entry += header->length;
 	}
@@ -162,6 +216,21 @@ phys_cpuid_t __init acpi_map_madt_entry(u32 acpi_id)
 	return rv;
 }
 
+int __init acpi_get_madt_revision(void)
+{
+	struct acpi_table_header *madt = NULL;
+	int revision;
+
+	if (ACPI_FAILURE(acpi_get_table(ACPI_SIG_MADT, 0, &madt)))
+		return -EINVAL;
+
+	revision = madt->revision;
+
+	acpi_put_table(madt);
+
+	return revision;
+}
+
 static phys_cpuid_t map_mat_entry(acpi_handle handle, int type, u32 acpi_id)
 {
 	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
@@ -190,6 +259,8 @@ static phys_cpuid_t map_mat_entry(acpi_handle handle, int type, u32 acpi_id)
 		map_x2apic_id(header, type, acpi_id, &phys_id);
 	else if (header->type == ACPI_MADT_TYPE_GENERIC_INTERRUPT)
 		map_gicc_mpidr(header, type, acpi_id, &phys_id);
+	else if (header->type == ACPI_MADT_TYPE_CORE_PIC)
+		map_core_pic_id(header, type, acpi_id, &phys_id);
 
 exit:
 	kfree(buffer.pointer);
diff --git a/drivers/acpi/processor_driver.c b/drivers/acpi/processor_driver.c
index 62114a03a51a..65e779be64ff 100644
--- a/drivers/acpi/processor_driver.c
+++ b/drivers/acpi/processor_driver.c
@@ -27,15 +27,12 @@
 #define ACPI_PROCESSOR_NOTIFY_PERFORMANCE 0x80
 #define ACPI_PROCESSOR_NOTIFY_POWER	0x81
 #define ACPI_PROCESSOR_NOTIFY_THROTTLING	0x82
-
-#define _COMPONENT		ACPI_PROCESSOR_COMPONENT
-ACPI_MODULE_NAME("processor_driver");
+#define ACPI_PROCESSOR_NOTIFY_HIGEST_PERF_CHANGED	0x85
 
 MODULE_AUTHOR("Paul Diefenbaugh");
 MODULE_DESCRIPTION("ACPI Processor Driver");
 MODULE_LICENSE("GPL");
 
-static int acpi_processor_start(struct device *dev);
 static int acpi_processor_stop(struct device *dev);
 
 static const struct acpi_device_id processor_device_ids[] = {
@@ -49,7 +46,6 @@ static struct device_driver acpi_processor_driver = {
 	.name = "processor",
 	.bus = &cpu_subsys,
 	.acpi_match_table = processor_device_ids,
-	.probe = acpi_processor_start,
 	.remove = acpi_processor_stop,
 };
 
@@ -86,9 +82,13 @@ static void acpi_processor_notify(acpi_handle handle, u32 event, void *data)
 		acpi_bus_generate_netlink_event(device->pnp.device_class,
 						  dev_name(&device->dev), event, 0);
 		break;
+	case ACPI_PROCESSOR_NOTIFY_HIGEST_PERF_CHANGED:
+		cpufreq_update_limits(pr->id);
+		acpi_bus_generate_netlink_event(device->pnp.device_class,
+						  dev_name(&device->dev), event, 0);
+		break;
 	default:
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-				  "Unsupported event [0x%x]\n", event));
+		acpi_handle_debug(handle, "Unsupported event [0x%x]\n", event);
 		break;
 	}
 
@@ -102,18 +102,20 @@ static int acpi_soft_cpu_online(unsigned int cpu)
 	struct acpi_processor *pr = per_cpu(processors, cpu);
 	struct acpi_device *device;
 
-	if (!pr || acpi_bus_get_device(pr->handle, &device))
+	if (!pr)
 		return 0;
+
+	device = acpi_fetch_acpi_dev(pr->handle);
+	if (!device)
+		return 0;
+
 	/*
 	 * CPU got physically hotplugged and onlined for the first time:
 	 * Initialize missing things.
 	 */
-	if (pr->flags.need_hotplug_init) {
+	if (!pr->flags.previously_online) {
 		int ret;
 
-		pr_info("Will online and init hotplugged CPU: %d\n",
-			pr->id);
-		pr->flags.need_hotplug_init = 0;
 		ret = __acpi_processor_start(device);
 		WARN(ret, "Failed to start CPU: %d\n", pr->id);
 	} else {
@@ -129,9 +131,8 @@ static int acpi_soft_cpu_online(unsigned int cpu)
 static int acpi_soft_cpu_dead(unsigned int cpu)
 {
 	struct acpi_processor *pr = per_cpu(processors, cpu);
-	struct acpi_device *device;
 
-	if (!pr || acpi_bus_get_device(pr->handle, &device))
+	if (!pr || !acpi_fetch_acpi_dev(pr->handle))
 		return 0;
 
 	acpi_processor_reevaluate_tstate(pr, true);
@@ -139,75 +140,17 @@ static int acpi_soft_cpu_dead(unsigned int cpu)
 }
 
 #ifdef CONFIG_ACPI_CPU_FREQ_PSS
-static int acpi_pss_perf_init(struct acpi_processor *pr,
-		struct acpi_device *device)
+static void acpi_pss_perf_init(struct acpi_processor *pr)
 {
-	int result = 0;
-
 	acpi_processor_ppc_has_changed(pr, 0);
 
 	acpi_processor_get_throttling_info(pr);
 
 	if (pr->flags.throttling)
 		pr->flags.limit = 1;
-
-	pr->cdev = thermal_cooling_device_register("Processor", device,
-						   &processor_cooling_ops);
-	if (IS_ERR(pr->cdev)) {
-		result = PTR_ERR(pr->cdev);
-		return result;
-	}
-
-	dev_dbg(&device->dev, "registered as cooling_device%d\n",
-		pr->cdev->id);
-
-	result = sysfs_create_link(&device->dev.kobj,
-				   &pr->cdev->device.kobj,
-				   "thermal_cooling");
-	if (result) {
-		dev_err(&device->dev,
-			"Failed to create sysfs link 'thermal_cooling'\n");
-		goto err_thermal_unregister;
-	}
-
-	result = sysfs_create_link(&pr->cdev->device.kobj,
-				   &device->dev.kobj,
-				   "device");
-	if (result) {
-		dev_err(&pr->cdev->device,
-			"Failed to create sysfs link 'device'\n");
-		goto err_remove_sysfs_thermal;
-	}
-
-	return 0;
-
- err_remove_sysfs_thermal:
-	sysfs_remove_link(&device->dev.kobj, "thermal_cooling");
- err_thermal_unregister:
-	thermal_cooling_device_unregister(pr->cdev);
-
-	return result;
-}
-
-static void acpi_pss_perf_exit(struct acpi_processor *pr,
-		struct acpi_device *device)
-{
-	if (pr->cdev) {
-		sysfs_remove_link(&device->dev.kobj, "thermal_cooling");
-		sysfs_remove_link(&pr->cdev->device.kobj, "device");
-		thermal_cooling_device_unregister(pr->cdev);
-		pr->cdev = NULL;
-	}
 }
 #else
-static inline int acpi_pss_perf_init(struct acpi_processor *pr,
-		struct acpi_device *device)
-{
-	return 0;
-}
-
-static inline void acpi_pss_perf_exit(struct acpi_processor *pr,
-		struct acpi_device *device) {}
+static inline void acpi_pss_perf_init(struct acpi_processor *pr) {}
 #endif /* CONFIG_ACPI_CPU_FREQ_PSS */
 
 static int __acpi_processor_start(struct acpi_device *device)
@@ -219,9 +162,6 @@ static int __acpi_processor_start(struct acpi_device *device)
 	if (!pr)
 		return -ENODEV;
 
-	if (pr->flags.need_hotplug_init)
-		return 0;
-
 	result = acpi_cppc_processor_probe(pr);
 	if (result && !IS_ENABLED(CONFIG_ACPI_CPU_FREQ_PSS))
 		dev_dbg(&device->dev, "CPPC data invalid or not present\n");
@@ -229,38 +169,29 @@ static int __acpi_processor_start(struct acpi_device *device)
 	if (!cpuidle_get_driver() || cpuidle_get_driver() == &acpi_idle_driver)
 		acpi_processor_power_init(pr);
 
-	result = acpi_pss_perf_init(pr, device);
+	acpi_pss_perf_init(pr);
+
+	result = acpi_processor_thermal_init(pr, device);
 	if (result)
 		goto err_power_exit;
 
 	status = acpi_install_notify_handler(device->handle, ACPI_DEVICE_NOTIFY,
 					     acpi_processor_notify, device);
-	if (ACPI_SUCCESS(status))
-		return 0;
+	if (!ACPI_SUCCESS(status)) {
+		result = -ENODEV;
+		goto err_thermal_exit;
+	}
+	pr->flags.previously_online = 1;
 
-	result = -ENODEV;
-	acpi_pss_perf_exit(pr, device);
+	return 0;
 
+err_thermal_exit:
+	acpi_processor_thermal_exit(pr, device);
 err_power_exit:
 	acpi_processor_power_exit(pr);
 	return result;
 }
 
-static int acpi_processor_start(struct device *dev)
-{
-	struct acpi_device *device = ACPI_COMPANION(dev);
-	int ret;
-
-	if (!device)
-		return -ENODEV;
-
-	/* Protect against concurrent CPU hotplug operations */
-	cpu_hotplug_disable();
-	ret = __acpi_processor_start(device);
-	cpu_hotplug_enable();
-	return ret;
-}
-
 static int acpi_processor_stop(struct device *dev)
 {
 	struct acpi_device *device = ACPI_COMPANION(dev);
@@ -277,10 +208,10 @@ static int acpi_processor_stop(struct device *dev)
 		return 0;
 	acpi_processor_power_exit(pr);
 
-	acpi_pss_perf_exit(pr, device);
-
 	acpi_cppc_processor_exit(pr);
 
+	acpi_processor_thermal_exit(pr, device);
+
 	return 0;
 }
 
@@ -306,6 +237,9 @@ static struct notifier_block acpi_processor_notifier_block = {
 	.notifier_call = acpi_processor_notifier,
 };
 
+void __weak acpi_processor_init_invariance_cppc(void)
+{ }
+
 /*
  * We keep the driver loaded even when ACPI is not running.
  * This is needed for the powernow-k8 driver, that works even without
@@ -319,26 +253,35 @@ static int __init acpi_processor_driver_init(void)
 	if (acpi_disabled)
 		return 0;
 
+	if (!cpufreq_register_notifier(&acpi_processor_notifier_block,
+				       CPUFREQ_POLICY_NOTIFIER)) {
+		acpi_processor_cpufreq_init = true;
+		acpi_processor_ignore_ppc_init();
+	}
+
 	result = driver_register(&acpi_processor_driver);
 	if (result < 0)
 		return result;
 
-	result = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN,
-					   "acpi/cpu-drv:online",
-					   acpi_soft_cpu_online, NULL);
+	result = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
+				   "acpi/cpu-drv:online",
+				   acpi_soft_cpu_online, NULL);
 	if (result < 0)
 		goto err;
 	hp_online = result;
 	cpuhp_setup_state_nocalls(CPUHP_ACPI_CPUDRV_DEAD, "acpi/cpu-drv:dead",
 				  NULL, acpi_soft_cpu_dead);
 
-	if (!cpufreq_register_notifier(&acpi_processor_notifier_block,
-				       CPUFREQ_POLICY_NOTIFIER)) {
-		acpi_processor_cpufreq_init = true;
-		acpi_processor_ignore_ppc_init();
-	}
-
 	acpi_processor_throttling_init();
+
+	/*
+	 * Frequency invariance calculations on AMD platforms can't be run until
+	 * after acpi_cppc_processor_probe() has been called for all online CPUs
+	 */
+	acpi_processor_init_invariance_cppc();
+
+	acpi_idle_rescan_dead_smt_siblings();
+
 	return 0;
 err:
 	driver_unregister(&acpi_processor_driver);
diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c
index dcc289e30166..89f2f08b2554 100644
--- a/drivers/acpi/processor_idle.c
+++ b/drivers/acpi/processor_idle.c
@@ -19,7 +19,12 @@
 #include <linux/tick.h>
 #include <linux/cpuidle.h>
 #include <linux/cpu.h>
+#include <linux/minmax.h>
+#include <linux/perf_event.h>
 #include <acpi/processor.h>
+#include <linux/context_tracking.h>
+
+#include "internal.h"
 
 /*
  * Include the apic definitions for x86 to have the APIC timer related defines
@@ -29,20 +34,17 @@
  */
 #ifdef CONFIG_X86
 #include <asm/apic.h>
+#include <asm/cpu.h>
 #endif
 
-#define ACPI_PROCESSOR_CLASS            "processor"
-#define _COMPONENT              ACPI_PROCESSOR_COMPONENT
-ACPI_MODULE_NAME("processor_idle");
-
 #define ACPI_IDLE_STATE_START	(IS_ENABLED(CONFIG_ARCH_HAS_CPU_RELAX) ? 1 : 0)
 
 static unsigned int max_cstate __read_mostly = ACPI_PROCESSOR_MAX_POWER;
-module_param(max_cstate, uint, 0000);
-static unsigned int nocst __read_mostly;
-module_param(nocst, uint, 0000);
-static int bm_check_disable __read_mostly;
-module_param(bm_check_disable, uint, 0000);
+module_param(max_cstate, uint, 0400);
+static bool nocst __read_mostly;
+module_param(nocst, bool, 0400);
+static bool bm_check_disable __read_mostly;
+module_param(bm_check_disable, bool, 0400);
 
 static unsigned int latency_factor __read_mostly = 2;
 module_param(latency_factor, uint, 0644);
@@ -55,6 +57,12 @@ struct cpuidle_driver acpi_idle_driver = {
 };
 
 #ifdef CONFIG_ACPI_PROCESSOR_CSTATE
+void acpi_idle_rescan_dead_smt_siblings(void)
+{
+	if (cpuidle_get_driver() == &acpi_idle_driver)
+		arch_cpu_rescan_dead_smt_siblings();
+}
+
 static
 DEFINE_PER_CPU(struct acpi_processor_cx * [CPUIDLE_STATE_MAX], acpi_cstate);
 
@@ -108,8 +116,8 @@ static const struct dmi_system_id processor_power_dmi_table[] = {
 static void __cpuidle acpi_safe_halt(void)
 {
 	if (!tif_need_resched()) {
-		safe_halt();
-		local_irq_disable();
+		raw_safe_halt();
+		raw_local_irq_disable();
 	}
 }
 
@@ -146,7 +154,7 @@ static void lapic_timer_check_state(int state, struct acpi_processor *pr,
 
 static void __lapic_timer_propagate_broadcast(void *arg)
 {
-	struct acpi_processor *pr = (struct acpi_processor *) arg;
+	struct acpi_processor *pr = arg;
 
 	if (pr->power.timer_broadcast_on_state < INT_MAX)
 		tick_broadcast_enable();
@@ -161,18 +169,10 @@ static void lapic_timer_propagate_broadcast(struct acpi_processor *pr)
 }
 
 /* Power(C) State timer broadcast control */
-static void lapic_timer_state_broadcast(struct acpi_processor *pr,
-				       struct acpi_processor_cx *cx,
-				       int broadcast)
+static bool lapic_timer_needs_broadcast(struct acpi_processor *pr,
+					struct acpi_processor_cx *cx)
 {
-	int state = cx - pr->power.states;
-
-	if (state >= pr->power.timer_broadcast_on_state) {
-		if (broadcast)
-			tick_broadcast_enter();
-		else
-			tick_broadcast_exit();
-	}
+	return cx - pr->power.states >= pr->power.timer_broadcast_on_state;
 }
 
 #else
@@ -180,10 +180,11 @@ static void lapic_timer_state_broadcast(struct acpi_processor *pr,
 static void lapic_timer_check_state(int state, struct acpi_processor *pr,
 				   struct acpi_processor_cx *cstate) { }
 static void lapic_timer_propagate_broadcast(struct acpi_processor *pr) { }
-static void lapic_timer_state_broadcast(struct acpi_processor *pr,
-				       struct acpi_processor_cx *cx,
-				       int broadcast)
+
+static bool lapic_timer_needs_broadcast(struct acpi_processor *pr,
+					struct acpi_processor_cx *cx)
 {
+	return false;
 }
 
 #endif
@@ -203,8 +204,7 @@ static void tsc_check_state(int state)
 		 */
 		if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
 			return;
-
-		/*FALL THROUGH*/
+		fallthrough;
 	default:
 		/* TSC could halt in idle, so notify users */
 		if (state > ACPI_STATE_C1)
@@ -248,8 +248,8 @@ static int acpi_processor_get_power_info_fadt(struct acpi_processor *pr)
 	 * 100 microseconds.
 	 */
 	if (acpi_gbl_FADT.c2_latency > ACPI_PROCESSOR_MAX_C2_LATENCY) {
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-			"C2 latency too large [%d]\n", acpi_gbl_FADT.c2_latency));
+		acpi_handle_debug(pr->handle, "C2 latency too large [%d]\n",
+				  acpi_gbl_FADT.c2_latency);
 		/* invalidate C2 */
 		pr->power.states[ACPI_STATE_C2].address = 0;
 	}
@@ -259,16 +259,15 @@ static int acpi_processor_get_power_info_fadt(struct acpi_processor *pr)
 	 * 1000 microseconds.
 	 */
 	if (acpi_gbl_FADT.c3_latency > ACPI_PROCESSOR_MAX_C3_LATENCY) {
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-			"C3 latency too large [%d]\n", acpi_gbl_FADT.c3_latency));
+		acpi_handle_debug(pr->handle, "C3 latency too large [%d]\n",
+				  acpi_gbl_FADT.c3_latency);
 		/* invalidate C3 */
 		pr->power.states[ACPI_STATE_C3].address = 0;
 	}
 
-	ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-			  "lvl2[0x%08x] lvl3[0x%08x]\n",
+	acpi_handle_debug(pr->handle, "lvl2[0x%08x] lvl3[0x%08x]\n",
 			  pr->power.states[ACPI_STATE_C2].address,
-			  pr->power.states[ACPI_STATE_C3].address));
+			  pr->power.states[ACPI_STATE_C3].address);
 
 	snprintf(pr->power.states[ACPI_STATE_C2].desc,
 			 ACPI_CX_DESC_LEN, "ACPI P_LVL2 IOPORT 0x%x",
@@ -277,6 +276,10 @@ static int acpi_processor_get_power_info_fadt(struct acpi_processor *pr)
 			 ACPI_CX_DESC_LEN, "ACPI P_LVL3 IOPORT 0x%x",
 			 pr->power.states[ACPI_STATE_C3].address);
 
+	if (!pr->power.states[ACPI_STATE_C2].address &&
+	    !pr->power.states[ACPI_STATE_C3].address)
+		return -ENODEV;
+
 	return 0;
 }
 
@@ -308,11 +311,7 @@ static int acpi_processor_get_power_info_cst(struct acpi_processor *pr)
 	if (ret)
 		return ret;
 
-	/*
-	 * It is expected that there will be at least 2 states, C1 and
-	 * something else (C2 or C3), so fail if that is not the case.
-	 */
-	if (pr->power.count < 2)
+	if (!pr->power.count)
 		return -EFAULT;
 
 	pr->flags.has_cst = 1;
@@ -336,9 +335,9 @@ static void acpi_processor_power_verify_c3(struct acpi_processor *pr,
 	 * the erratum), but this is known to disrupt certain ISA
 	 * devices thus we take the conservative approach.
 	 */
-	else if (errata.piix4.fdma) {
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-				  "C3 not supported on PIIX4 with Type-F DMA\n"));
+	if (errata.piix4.fdma) {
+		acpi_handle_debug(pr->handle,
+				  "C3 not supported on PIIX4 with Type-F DMA\n");
 		return;
 	}
 
@@ -357,13 +356,13 @@ static void acpi_processor_power_verify_c3(struct acpi_processor *pr,
 		if (!pr->flags.bm_control) {
 			if (pr->flags.has_cst != 1) {
 				/* bus mastering control is necessary */
-				ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-					"C3 support requires BM control\n"));
+				acpi_handle_debug(pr->handle,
+						  "C3 support requires BM control\n");
 				return;
 			} else {
 				/* Here we enter C3 without bus mastering */
-				ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-					"C3 support without BM control\n"));
+				acpi_handle_debug(pr->handle,
+						  "C3 support without BM control\n");
 			}
 		}
 	} else {
@@ -372,9 +371,9 @@ static void acpi_processor_power_verify_c3(struct acpi_processor *pr,
 		 * supported on when bm_check is not required.
 		 */
 		if (!(acpi_gbl_FADT.flags & ACPI_FADT_WBINVD)) {
-			ACPI_DEBUG_PRINT((ACPI_DB_INFO,
+			acpi_handle_debug(pr->handle,
 					  "Cache invalidation should work properly"
-					  " for C3 to be enabled on SMP systems\n"));
+					  " for C3 to be enabled on SMP systems\n");
 			return;
 		}
 	}
@@ -396,14 +395,35 @@ static void acpi_processor_power_verify_c3(struct acpi_processor *pr,
 	 * handle BM_RLD is to set it and leave it set.
 	 */
 	acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, 1);
+}
 
-	return;
+static void acpi_cst_latency_sort(struct acpi_processor_cx *states, size_t length)
+{
+	int i, j, k;
+
+	for (i = 1; i < length; i++) {
+		if (!states[i].valid)
+			continue;
+
+		for (j = i - 1, k = i; j >= 0; j--) {
+			if (!states[j].valid)
+				continue;
+
+			if (states[j].latency > states[k].latency)
+				swap(states[j].latency, states[k].latency);
+
+			k = j;
+		}
+	}
 }
 
 static int acpi_processor_power_verify(struct acpi_processor *pr)
 {
 	unsigned int i;
 	unsigned int working = 0;
+	unsigned int last_latency = 0;
+	unsigned int last_type = 0;
+	bool buggy_latency = false;
 
 	pr->power.timer_broadcast_on_state = INT_MAX;
 
@@ -427,23 +447,30 @@ static int acpi_processor_power_verify(struct acpi_processor *pr)
 		}
 		if (!cx->valid)
 			continue;
+		if (cx->type >= last_type && cx->latency < last_latency)
+			buggy_latency = true;
+		last_latency = cx->latency;
+		last_type = cx->type;
 
 		lapic_timer_check_state(i, pr, cx);
 		tsc_check_state(cx->type);
 		working++;
 	}
 
+	if (buggy_latency) {
+		pr_notice("FW issue: working around C-state latencies out of order\n");
+		acpi_cst_latency_sort(&pr->power.states[1], max_cstate);
+	}
+
 	lapic_timer_propagate_broadcast(pr);
 
-	return (working);
+	return working;
 }
 
 static int acpi_processor_get_cstate_info(struct acpi_processor *pr)
 {
-	unsigned int i;
 	int result;
 
-
 	/* NOTE: the idle thread may not be running while calling
 	 * this function */
 
@@ -460,18 +487,7 @@ static int acpi_processor_get_cstate_info(struct acpi_processor *pr)
 	acpi_processor_get_power_info_default(pr);
 
 	pr->power.count = acpi_processor_power_verify(pr);
-
-	/*
-	 * if one state of type C2 or C3 is available, mark this
-	 * CPU as being "idle manageable"
-	 */
-	for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) {
-		if (pr->power.states[i].valid) {
-			pr->power.count = i;
-			if (pr->power.states[i].type >= ACPI_STATE_C2)
-				pr->flags.power = 1;
-		}
-	}
+	pr->flags.power = 1;
 
 	return 0;
 }
@@ -502,16 +518,36 @@ static int acpi_idle_bm_check(void)
 	return bm_status;
 }
 
-static void wait_for_freeze(void)
+static __cpuidle void io_idle(unsigned long addr)
 {
+	/* IO port based C-state */
+	inb(addr);
+
 #ifdef	CONFIG_X86
 	/* No delay is needed if we are in guest */
 	if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
 		return;
+	/*
+	 * Modern (>=Nehalem) Intel systems use ACPI via intel_idle,
+	 * not this code.  Assume that any Intel systems using this
+	 * are ancient and may need the dummy wait.  This also assumes
+	 * that the motivating chipset issue was Intel-only.
+	 */
+	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
+		return;
 #endif
-	/* Dummy wait op - must do something useless after P_LVL2 read
-	   because chipsets cannot guarantee that STPCLK# signal
-	   gets asserted in time to freeze execution properly. */
+	/*
+	 * Dummy wait op - must do something useless after P_LVL2 read
+	 * because chipsets cannot guarantee that STPCLK# signal gets
+	 * asserted in time to freeze execution properly
+	 *
+	 * This workaround has been in place since the original ACPI
+	 * implementation was merged, circa 2002.
+	 *
+	 * If a profile is pointing to this instruction, please first
+	 * consider moving your system to a more modern idle
+	 * mechanism.
+	 */
 	inl(acpi_gbl_FADT.xpm_timer_block.address);
 }
 
@@ -523,16 +559,18 @@ static void wait_for_freeze(void)
  */
 static void __cpuidle acpi_idle_do_entry(struct acpi_processor_cx *cx)
 {
+	perf_lopwr_cb(true);
+
 	if (cx->entry_method == ACPI_CSTATE_FFH) {
 		/* Call into architectural FFH based C-state */
 		acpi_processor_ffh_cstate_enter(cx);
 	} else if (cx->entry_method == ACPI_CSTATE_HALT) {
 		acpi_safe_halt();
 	} else {
-		/* IO port based C-state */
-		inb(cx->address);
-		wait_for_freeze();
+		io_idle(cx->address);
 	}
+
+	perf_lopwr_cb(false);
 }
 
 /**
@@ -540,7 +578,7 @@ static void __cpuidle acpi_idle_do_entry(struct acpi_processor_cx *cx)
  * @dev: the target CPU
  * @index: the index of suggested state
  */
-static int acpi_idle_play_dead(struct cpuidle_device *dev, int index)
+static void acpi_idle_play_dead(struct cpuidle_device *dev, int index)
 {
 	struct acpi_processor_cx *cx = per_cpu(acpi_cstate[index], dev->cpu);
 
@@ -549,19 +587,17 @@ static int acpi_idle_play_dead(struct cpuidle_device *dev, int index)
 	while (1) {
 
 		if (cx->entry_method == ACPI_CSTATE_HALT)
-			safe_halt();
+			raw_safe_halt();
 		else if (cx->entry_method == ACPI_CSTATE_SYSTEMIO) {
-			inb(cx->address);
-			wait_for_freeze();
+			io_idle(cx->address);
+		} else if (cx->entry_method == ACPI_CSTATE_FFH) {
+			acpi_processor_ffh_play_dead(cx);
 		} else
-			return -ENODEV;
+			return;
 	}
-
-	/* Never reached */
-	return 0;
 }
 
-static bool acpi_idle_fallback_to_c1(struct acpi_processor *pr)
+static __always_inline bool acpi_idle_fallback_to_c1(struct acpi_processor *pr)
 {
 	return IS_ENABLED(CONFIG_HOTPLUG_CPU) && !pr->flags.has_cst &&
 		!(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED);
@@ -572,32 +608,45 @@ static DEFINE_RAW_SPINLOCK(c3_lock);
 
 /**
  * acpi_idle_enter_bm - enters C3 with proper BM handling
+ * @drv: cpuidle driver
  * @pr: Target processor
  * @cx: Target state context
- * @timer_bc: Whether or not to change timer mode to broadcast
+ * @index: index of target state
  */
-static void acpi_idle_enter_bm(struct acpi_processor *pr,
-			       struct acpi_processor_cx *cx, bool timer_bc)
+static int __cpuidle acpi_idle_enter_bm(struct cpuidle_driver *drv,
+			       struct acpi_processor *pr,
+			       struct acpi_processor_cx *cx,
+			       int index)
 {
-	acpi_unlazy_tlb(smp_processor_id());
-
-	/*
-	 * Must be done before busmaster disable as we might need to
-	 * access HPET !
-	 */
-	if (timer_bc)
-		lapic_timer_state_broadcast(pr, cx, 1);
+	static struct acpi_processor_cx safe_cx = {
+		.entry_method = ACPI_CSTATE_HALT,
+	};
 
 	/*
 	 * disable bus master
 	 * bm_check implies we need ARB_DIS
 	 * bm_control implies whether we can do ARB_DIS
 	 *
-	 * That leaves a case where bm_check is set and bm_control is
-	 * not set. In that case we cannot do much, we enter C3
-	 * without doing anything.
+	 * That leaves a case where bm_check is set and bm_control is not set.
+	 * In that case we cannot do much, we enter C3 without doing anything.
 	 */
-	if (pr->flags.bm_control) {
+	bool dis_bm = pr->flags.bm_control;
+
+	instrumentation_begin();
+
+	/* If we can skip BM, demote to a safe state. */
+	if (!cx->bm_sts_skip && acpi_idle_bm_check()) {
+		dis_bm = false;
+		index = drv->safe_state_index;
+		if (index >= 0) {
+			cx = this_cpu_read(acpi_cstate[index]);
+		} else {
+			cx = &safe_cx;
+			index = -EBUSY;
+		}
+	}
+
+	if (dis_bm) {
 		raw_spin_lock(&c3_lock);
 		c3_cpu_count++;
 		/* Disable bus master arbitration when all CPUs are in C3 */
@@ -606,21 +655,26 @@ static void acpi_idle_enter_bm(struct acpi_processor *pr,
 		raw_spin_unlock(&c3_lock);
 	}
 
+	ct_cpuidle_enter();
+
 	acpi_idle_do_entry(cx);
 
+	ct_cpuidle_exit();
+
 	/* Re-enable bus master arbitration */
-	if (pr->flags.bm_control) {
+	if (dis_bm) {
 		raw_spin_lock(&c3_lock);
 		acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 0);
 		c3_cpu_count--;
 		raw_spin_unlock(&c3_lock);
 	}
 
-	if (timer_bc)
-		lapic_timer_state_broadcast(pr, cx, 0);
+	instrumentation_end();
+
+	return index;
 }
 
-static int acpi_idle_enter(struct cpuidle_device *dev,
+static int __cpuidle acpi_idle_enter(struct cpuidle_device *dev,
 			   struct cpuidle_driver *drv, int index)
 {
 	struct acpi_processor_cx *cx = per_cpu(acpi_cstate[index], dev->cpu);
@@ -631,37 +685,26 @@ static int acpi_idle_enter(struct cpuidle_device *dev,
 		return -EINVAL;
 
 	if (cx->type != ACPI_STATE_C1) {
+		if (cx->type == ACPI_STATE_C3 && pr->flags.bm_check)
+			return acpi_idle_enter_bm(drv, pr, cx, index);
+
+		/* C2 to C1 demotion. */
 		if (acpi_idle_fallback_to_c1(pr) && num_online_cpus() > 1) {
 			index = ACPI_IDLE_STATE_START;
 			cx = per_cpu(acpi_cstate[index], dev->cpu);
-		} else if (cx->type == ACPI_STATE_C3 && pr->flags.bm_check) {
-			if (cx->bm_sts_skip || !acpi_idle_bm_check()) {
-				acpi_idle_enter_bm(pr, cx, true);
-				return index;
-			} else if (drv->safe_state_index >= 0) {
-				index = drv->safe_state_index;
-				cx = per_cpu(acpi_cstate[index], dev->cpu);
-			} else {
-				acpi_safe_halt();
-				return -EBUSY;
-			}
 		}
 	}
 
-	lapic_timer_state_broadcast(pr, cx, 1);
-
 	if (cx->type == ACPI_STATE_C3)
 		ACPI_FLUSH_CPU_CACHE();
 
 	acpi_idle_do_entry(cx);
 
-	lapic_timer_state_broadcast(pr, cx, 0);
-
 	return index;
 }
 
-static void acpi_idle_enter_s2idle(struct cpuidle_device *dev,
-				   struct cpuidle_driver *drv, int index)
+static int __cpuidle acpi_idle_enter_s2idle(struct cpuidle_device *dev,
+				  struct cpuidle_driver *drv, int index)
 {
 	struct acpi_processor_cx *cx = per_cpu(acpi_cstate[index], dev->cpu);
 
@@ -669,20 +712,28 @@ static void acpi_idle_enter_s2idle(struct cpuidle_device *dev,
 		struct acpi_processor *pr = __this_cpu_read(processors);
 
 		if (unlikely(!pr))
-			return;
+			return 0;
 
 		if (pr->flags.bm_check) {
-			acpi_idle_enter_bm(pr, cx, false);
-			return;
+			u8 bm_sts_skip = cx->bm_sts_skip;
+
+			/* Don't check BM_STS, do an unconditional ARB_DIS for S2IDLE */
+			cx->bm_sts_skip = 1;
+			acpi_idle_enter_bm(drv, pr, cx, index);
+			cx->bm_sts_skip = bm_sts_skip;
+
+			return 0;
 		} else {
 			ACPI_FLUSH_CPU_CACHE();
 		}
 	}
 	acpi_idle_do_entry(cx);
+
+	return 0;
 }
 
-static int acpi_processor_setup_cpuidle_cx(struct acpi_processor *pr,
-					   struct cpuidle_device *dev)
+static void acpi_processor_setup_cpuidle_cx(struct acpi_processor *pr,
+					    struct cpuidle_device *dev)
 {
 	int i, count = ACPI_IDLE_STATE_START;
 	struct acpi_processor_cx *cx;
@@ -702,14 +753,9 @@ static int acpi_processor_setup_cpuidle_cx(struct acpi_processor *pr,
 		if (count == CPUIDLE_STATE_MAX)
 			break;
 	}
-
-	if (!count)
-		return -EINVAL;
-
-	return 0;
 }
 
-static int acpi_processor_setup_cstates(struct acpi_processor *pr)
+static void acpi_processor_setup_cstates(struct acpi_processor *pr)
 {
 	int i, count;
 	struct acpi_processor_cx *cx;
@@ -734,16 +780,18 @@ static int acpi_processor_setup_cstates(struct acpi_processor *pr)
 
 		state = &drv->states[count];
 		snprintf(state->name, CPUIDLE_NAME_LEN, "C%d", i);
-		strlcpy(state->desc, cx->desc, CPUIDLE_DESC_LEN);
+		strscpy(state->desc, cx->desc, CPUIDLE_DESC_LEN);
 		state->exit_latency = cx->latency;
 		state->target_residency = cx->latency * latency_factor;
 		state->enter = acpi_idle_enter;
 
 		state->flags = 0;
-		if (cx->type == ACPI_STATE_C1 || cx->type == ACPI_STATE_C2) {
-			state->enter_dead = acpi_idle_play_dead;
+
+		state->enter_dead = acpi_idle_play_dead;
+
+		if (cx->type == ACPI_STATE_C1 || cx->type == ACPI_STATE_C2)
 			drv->safe_state_index = count;
-		}
+
 		/*
 		 * Halt-induced C1 is not good for ->enter_s2idle, because it
 		 * re-enables interrupts on exit.  Moreover, C1 is generally not
@@ -754,17 +802,21 @@ static int acpi_processor_setup_cstates(struct acpi_processor *pr)
 		if (cx->type != ACPI_STATE_C1 && !acpi_idle_fallback_to_c1(pr))
 			state->enter_s2idle = acpi_idle_enter_s2idle;
 
+		if (lapic_timer_needs_broadcast(pr, cx))
+			state->flags |= CPUIDLE_FLAG_TIMER_STOP;
+
+		if (cx->type == ACPI_STATE_C3) {
+			state->flags |= CPUIDLE_FLAG_TLB_FLUSHED;
+			if (pr->flags.bm_check)
+				state->flags |= CPUIDLE_FLAG_RCU_IDLE;
+		}
+
 		count++;
 		if (count == CPUIDLE_STATE_MAX)
 			break;
 	}
 
 	drv->state_count = count;
-
-	if (!count)
-		return -EINVAL;
-
-	return 0;
 }
 
 static inline void acpi_processor_cstate_first_run_checks(void)
@@ -776,8 +828,8 @@ static inline void acpi_processor_cstate_first_run_checks(void)
 	dmi_check_system(processor_power_dmi_table);
 	max_cstate = acpi_processor_cstate_check(max_cstate);
 	if (max_cstate < ACPI_C_STATES_MAX)
-		pr_notice("ACPI: processor limited to max C-state %d\n",
-			  max_cstate);
+		pr_notice("processor limited to max C-state %d\n", max_cstate);
+
 	first_run++;
 
 	if (nocst)
@@ -835,7 +887,7 @@ static int acpi_processor_evaluate_lpi(acpi_handle handle,
 
 	status = acpi_evaluate_object(handle, "_LPI", NULL, &buffer);
 	if (ACPI_FAILURE(status)) {
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No _LPI, giving up\n"));
+		acpi_handle_debug(handle, "No _LPI, giving up\n");
 		return -ENODEV;
 	}
 
@@ -901,7 +953,7 @@ static int acpi_processor_evaluate_lpi(acpi_handle handle,
 
 		obj = pkg_elem + 9;
 		if (obj->type == ACPI_TYPE_STRING)
-			strlcpy(lpi_state->desc, obj->string.pointer,
+			strscpy(lpi_state->desc, obj->string.pointer,
 				ACPI_CX_DESC_LEN);
 
 		lpi_state->index = state_idx;
@@ -934,11 +986,6 @@ end:
 	return ret;
 }
 
-/*
- * flat_state_cnt - the number of composite LPI states after the process of flattening
- */
-static int flat_state_cnt;
-
 /**
  * combine_lpi_states - combine local and parent LPI states to form a composite LPI state
  *
@@ -967,7 +1014,7 @@ static bool combine_lpi_states(struct acpi_lpi_state *local,
 	result->arch_flags = parent->arch_flags;
 	result->index = parent->index;
 
-	strlcpy(result->desc, local->desc, ACPI_CX_DESC_LEN);
+	strscpy(result->desc, local->desc, ACPI_CX_DESC_LEN);
 	strlcat(result->desc, "+", ACPI_CX_DESC_LEN);
 	strlcat(result->desc, parent->desc, ACPI_CX_DESC_LEN);
 	return true;
@@ -981,9 +1028,10 @@ static void stash_composite_state(struct acpi_lpi_states_array *curr_level,
 	curr_level->composite_states[curr_level->composite_states_size++] = t;
 }
 
-static int flatten_lpi_states(struct acpi_processor *pr,
-			      struct acpi_lpi_states_array *curr_level,
-			      struct acpi_lpi_states_array *prev_level)
+static unsigned int flatten_lpi_states(struct acpi_processor *pr,
+				       unsigned int flat_state_cnt,
+				       struct acpi_lpi_states_array *curr_level,
+				       struct acpi_lpi_states_array *prev_level)
 {
 	int i, j, state_count = curr_level->size;
 	struct acpi_lpi_state *p, *t = curr_level->entries;
@@ -1023,7 +1071,12 @@ static int flatten_lpi_states(struct acpi_processor *pr,
 	}
 
 	kfree(curr_level->entries);
-	return 0;
+	return flat_state_cnt;
+}
+
+int __weak acpi_processor_ffh_lpi_probe(unsigned int cpu)
+{
+	return -EOPNOTSUPP;
 }
 
 static int acpi_processor_get_lpi_info(struct acpi_processor *pr)
@@ -1033,6 +1086,12 @@ static int acpi_processor_get_lpi_info(struct acpi_processor *pr)
 	acpi_handle handle = pr->handle, pr_ahandle;
 	struct acpi_device *d = NULL;
 	struct acpi_lpi_states_array info[2], *tmp, *prev, *curr;
+	unsigned int state_count;
+
+	/* make sure our architecture has support */
+	ret = acpi_processor_ffh_lpi_probe(pr->id);
+	if (ret == -EOPNOTSUPP)
+		return ret;
 
 	if (!osc_pc_lpi_support_confirmed)
 		return -EOPNOTSUPP;
@@ -1040,18 +1099,20 @@ static int acpi_processor_get_lpi_info(struct acpi_processor *pr)
 	if (!acpi_has_method(handle, "_LPI"))
 		return -EINVAL;
 
-	flat_state_cnt = 0;
 	prev = &info[0];
 	curr = &info[1];
 	handle = pr->handle;
 	ret = acpi_processor_evaluate_lpi(handle, prev);
 	if (ret)
 		return ret;
-	flatten_lpi_states(pr, prev, NULL);
+	state_count = flatten_lpi_states(pr, 0, prev, NULL);
 
 	status = acpi_get_parent(handle, &pr_ahandle);
 	while (ACPI_SUCCESS(status)) {
-		acpi_bus_get_device(pr_ahandle, &d);
+		d = acpi_fetch_acpi_dev(pr_ahandle);
+		if (!d)
+			break;
+
 		handle = pr_ahandle;
 
 		if (strcmp(acpi_device_hid(d), ACPI_PROCESSOR_CONTAINER_HID))
@@ -1066,18 +1127,19 @@ static int acpi_processor_get_lpi_info(struct acpi_processor *pr)
 			break;
 
 		/* flatten all the LPI states in this level of hierarchy */
-		flatten_lpi_states(pr, curr, prev);
+		state_count = flatten_lpi_states(pr, state_count, curr, prev);
 
 		tmp = prev, prev = curr, curr = tmp;
 
 		status = acpi_get_parent(handle, &pr_ahandle);
 	}
 
-	pr->power.count = flat_state_cnt;
 	/* reset the index after flattening */
-	for (i = 0; i < pr->power.count; i++)
+	for (i = 0; i < state_count; i++)
 		pr->power.lpi_states[i].index = i;
 
+	pr->power.count = state_count;
+
 	/* Tell driver that _LPI is supported. */
 	pr->flags.has_lpi = 1;
 	pr->flags.power = 1;
@@ -1085,11 +1147,6 @@ static int acpi_processor_get_lpi_info(struct acpi_processor *pr)
 	return 0;
 }
 
-int __weak acpi_processor_ffh_lpi_probe(unsigned int cpu)
-{
-	return -ENODEV;
-}
-
 int __weak acpi_processor_ffh_lpi_enter(struct acpi_lpi_state *lpi)
 {
 	return -ENODEV;
@@ -1136,11 +1193,12 @@ static int acpi_processor_setup_lpi_states(struct acpi_processor *pr)
 
 		state = &drv->states[i];
 		snprintf(state->name, CPUIDLE_NAME_LEN, "LPI-%d", i);
-		strlcpy(state->desc, lpi->desc, CPUIDLE_DESC_LEN);
+		strscpy(state->desc, lpi->desc, CPUIDLE_DESC_LEN);
 		state->exit_latency = lpi->wake_latency;
 		state->target_residency = lpi->min_residency;
-		if (lpi->arch_flags)
-			state->flags |= CPUIDLE_FLAG_TIMER_STOP;
+		state->flags |= arch_get_idle_state_flags(lpi->arch_flags);
+		if (i != 0 && lpi->entry_method == ACPI_CSTATE_FFH)
+			state->flags |= CPUIDLE_FLAG_RCU_IDLE;
 		state->enter = acpi_idle_lpi_enter;
 		drv->safe_state_index = i;
 	}
@@ -1173,7 +1231,8 @@ static int acpi_processor_setup_cpuidle_states(struct acpi_processor *pr)
 	if (pr->flags.has_lpi)
 		return acpi_processor_setup_lpi_states(pr);
 
-	return acpi_processor_setup_cstates(pr);
+	acpi_processor_setup_cstates(pr);
+	return 0;
 }
 
 /**
@@ -1193,7 +1252,8 @@ static int acpi_processor_setup_cpuidle_dev(struct acpi_processor *pr,
 	if (pr->flags.has_lpi)
 		return acpi_processor_ffh_lpi_probe(pr->id);
 
-	return acpi_processor_setup_cpuidle_cx(pr, dev);
+	acpi_processor_setup_cpuidle_cx(pr, dev);
+	return 0;
 }
 
 static int acpi_processor_get_power_info(struct acpi_processor *pr)
@@ -1252,7 +1312,7 @@ int acpi_processor_power_state_has_changed(struct acpi_processor *pr)
 	if (pr->id == 0 && cpuidle_get_driver() == &acpi_idle_driver) {
 
 		/* Protect against cpu-hotplug */
-		get_online_cpus();
+		cpus_read_lock();
 		cpuidle_pause_and_lock();
 
 		/* Disable all cpuidle devices */
@@ -1281,7 +1341,7 @@ int acpi_processor_power_state_has_changed(struct acpi_processor *pr)
 			}
 		}
 		cpuidle_resume_and_unlock();
-		put_online_cpus();
+		cpus_read_unlock();
 	}
 
 	return 0;
@@ -1332,6 +1392,9 @@ int acpi_processor_power_init(struct acpi_processor *pr)
 		if (retval) {
 			if (acpi_processor_registered == 0)
 				cpuidle_unregister_driver(&acpi_idle_driver);
+
+			per_cpu(acpi_cpuidle_device, pr->id) = NULL;
+			kfree(dev);
 			return retval;
 		}
 		acpi_processor_registered++;
@@ -1351,8 +1414,12 @@ int acpi_processor_power_exit(struct acpi_processor *pr)
 		acpi_processor_registered--;
 		if (acpi_processor_registered == 0)
 			cpuidle_unregister_driver(&acpi_idle_driver);
+
+		kfree(dev);
 	}
 
 	pr->flags.power_setup_done = 0;
 	return 0;
 }
+
+MODULE_IMPORT_NS("ACPI_PROCESSOR_IDLE");
diff --git a/drivers/acpi/processor_pdc.c b/drivers/acpi/processor_pdc.c
index 813f1b78c16a..994091bd52de 100644
--- a/drivers/acpi/processor_pdc.c
+++ b/drivers/acpi/processor_pdc.c
@@ -9,63 +9,20 @@
 
 #define pr_fmt(fmt) "ACPI: " fmt
 
-#include <linux/dmi.h>
 #include <linux/slab.h>
 #include <linux/acpi.h>
 #include <acpi/processor.h>
 
 #include "internal.h"
 
-#define _COMPONENT              ACPI_PROCESSOR_COMPONENT
-ACPI_MODULE_NAME("processor_pdc");
-
-static bool __init processor_physically_present(acpi_handle handle)
-{
-	int cpuid, type;
-	u32 acpi_id;
-	acpi_status status;
-	acpi_object_type acpi_type;
-	unsigned long long tmp;
-	union acpi_object object = { 0 };
-	struct acpi_buffer buffer = { sizeof(union acpi_object), &object };
-
-	status = acpi_get_type(handle, &acpi_type);
-	if (ACPI_FAILURE(status))
-		return false;
-
-	switch (acpi_type) {
-	case ACPI_TYPE_PROCESSOR:
-		status = acpi_evaluate_object(handle, NULL, NULL, &buffer);
-		if (ACPI_FAILURE(status))
-			return false;
-		acpi_id = object.processor.proc_id;
-		break;
-	case ACPI_TYPE_DEVICE:
-		status = acpi_evaluate_integer(handle, "_UID", NULL, &tmp);
-		if (ACPI_FAILURE(status))
-			return false;
-		acpi_id = tmp;
-		break;
-	default:
-		return false;
-	}
-
-	type = (acpi_type == ACPI_TYPE_DEVICE) ? 1 : 0;
-	cpuid = acpi_get_cpuid(handle, type, acpi_id);
-
-	return !invalid_logical_cpuid(cpuid);
-}
-
 static void acpi_set_pdc_bits(u32 *buf)
 {
 	buf[0] = ACPI_PDC_REVISION_ID;
 	buf[1] = 1;
-
-	/* Enable coordination with firmware's _TSD info */
-	buf[2] = ACPI_PDC_SMP_T_SWCOORD;
+	buf[2] = 0;
 
 	/* Twiddle arch-specific bits needed for _PDC */
-	arch_acpi_set_pdc_bits(buf);
+	arch_acpi_set_proc_cap_bits(&buf[2]);
 }
 
 static struct acpi_object_list *acpi_processor_alloc_pdc(void)
@@ -115,25 +72,11 @@ acpi_processor_eval_pdc(acpi_handle handle, struct acpi_object_list *pdc_in)
 {
 	acpi_status status = AE_OK;
 
-	if (boot_option_idle_override == IDLE_NOMWAIT) {
-		/*
-		 * If mwait is disabled for CPU C-states, the C2C3_FFH access
-		 * mode will be disabled in the parameter of _PDC object.
-		 * Of course C1_FFH access mode will also be disabled.
-		 */
-		union acpi_object *obj;
-		u32 *buffer = NULL;
-
-		obj = pdc_in->pointer;
-		buffer = (u32 *)(obj->buffer.pointer);
-		buffer[2] &= ~(ACPI_PDC_C_C2C3_FFH | ACPI_PDC_C_C1_FFH);
-
-	}
 	status = acpi_evaluate_object(handle, "_PDC", pdc_in, NULL);
 
 	if (ACPI_FAILURE(status))
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-		    "Could not evaluate _PDC, using legacy perf. control.\n"));
+		acpi_handle_debug(handle,
+		    "Could not evaluate _PDC, using legacy perf control\n");
 
 	return status;
 }
@@ -166,36 +109,9 @@ early_init_pdc(acpi_handle handle, u32 lvl, void *context, void **rv)
 	return AE_OK;
 }
 
-static int __init set_no_mwait(const struct dmi_system_id *id)
-{
-	pr_notice("%s detected - disabling mwait for CPU C-states\n",
-		  id->ident);
-	boot_option_idle_override = IDLE_NOMWAIT;
-	return 0;
-}
-
-static const struct dmi_system_id processor_idle_dmi_table[] __initconst = {
-	{
-	set_no_mwait, "Extensa 5220", {
-	DMI_MATCH(DMI_BIOS_VENDOR, "Phoenix Technologies LTD"),
-	DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
-	DMI_MATCH(DMI_PRODUCT_VERSION, "0100"),
-	DMI_MATCH(DMI_BOARD_NAME, "Columbia") }, NULL},
-	{},
-};
-
-static void __init processor_dmi_check(void)
-{
-	/*
-	 * Check whether the system is DMI table. If yes, OSPM
-	 * should not use mwait for CPU-states.
-	 */
-	dmi_check_system(processor_idle_dmi_table);
-}
-
 void __init acpi_early_processor_set_pdc(void)
 {
-	processor_dmi_check();
+	acpi_proc_quirk_mwait_check();
 
 	acpi_walk_namespace(ACPI_TYPE_PROCESSOR, ACPI_ROOT_OBJECT,
 			    ACPI_UINT32_MAX,
diff --git a/drivers/acpi/processor_perflib.c b/drivers/acpi/processor_perflib.c
index 5909e8fa4013..8972446b7162 100644
--- a/drivers/acpi/processor_perflib.c
+++ b/drivers/acpi/processor_perflib.c
@@ -9,6 +9,8 @@
  *  			- Added processor hotplug support
  */
 
+#define pr_fmt(fmt) "ACPI: " fmt
+
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/init.h>
@@ -18,16 +20,10 @@
 #include <acpi/processor.h>
 #ifdef CONFIG_X86
 #include <asm/cpufeature.h>
+#include <asm/msr.h>
 #endif
 
-#define PREFIX "ACPI: "
-
-#define ACPI_PROCESSOR_CLASS		"processor"
 #define ACPI_PROCESSOR_FILE_PERFORMANCE	"performance"
-#define _COMPONENT		ACPI_PROCESSOR_COMPONENT
-ACPI_MODULE_NAME("processor_perflib");
-
-static DEFINE_MUTEX(performance_mutex);
 
 /*
  * _PPC support is implemented as a CPUfreq policy notifier:
@@ -56,6 +52,8 @@ static int acpi_processor_get_platform_limit(struct acpi_processor *pr)
 {
 	acpi_status status = 0;
 	unsigned long long ppc = 0;
+	s32 qos_value;
+	int index;
 	int ret;
 
 	if (!pr)
@@ -66,26 +64,39 @@ static int acpi_processor_get_platform_limit(struct acpi_processor *pr)
 	 * (e.g. 0 = states 0..n; 1 = states 1..n; etc.
 	 */
 	status = acpi_evaluate_integer(pr->handle, "_PPC", NULL, &ppc);
-
-	if (status != AE_NOT_FOUND)
+	if (status != AE_NOT_FOUND) {
 		acpi_processor_ppc_in_use = true;
 
-	if (ACPI_FAILURE(status) && status != AE_NOT_FOUND) {
-		ACPI_EXCEPTION((AE_INFO, status, "Evaluating _PPC"));
-		return -ENODEV;
+		if (ACPI_FAILURE(status)) {
+			acpi_evaluation_failure_warn(pr->handle, "_PPC", status);
+			return -ENODEV;
+		}
 	}
 
+	index = ppc;
+
+	if (pr->performance_platform_limit == index ||
+	    ppc >= pr->performance->state_count)
+		return 0;
+
 	pr_debug("CPU %d: _PPC is %d - frequency %s limited\n", pr->id,
-		       (int)ppc, ppc ? "" : "not");
+		 index, index ? "is" : "is not");
 
-	pr->performance_platform_limit = (int)ppc;
+	pr->performance_platform_limit = index;
 
-	if (ppc >= pr->performance->state_count ||
-	    unlikely(!freq_qos_request_active(&pr->perflib_req)))
+	if (unlikely(!freq_qos_request_active(&pr->perflib_req)))
 		return 0;
 
-	ret = freq_qos_update_request(&pr->perflib_req,
-			pr->performance->states[ppc].core_frequency * 1000);
+	/*
+	 * If _PPC returns 0, it means that all of the available states can be
+	 * used ("no limit").
+	 */
+	if (index == 0)
+		qos_value = FREQ_QOS_MAX_DEFAULT_VALUE;
+	else
+		qos_value = pr->performance->states[index].core_frequency * 1000;
+
+	ret = freq_qos_update_request(&pr->perflib_req, qos_value);
 	if (ret < 0) {
 		pr_warn("Failed to update perflib freq constraint: CPU%d (%d)\n",
 			pr->id, ret);
@@ -99,7 +110,7 @@ static int acpi_processor_get_platform_limit(struct acpi_processor *pr)
  * acpi_processor_ppc_ost: Notify firmware the _PPC evaluation status
  * @handle: ACPI processor handle
  * @status: the status code of _PPC evaluation
- *	0: success. OSPM is now using the performance state specificed.
+ *	0: success. OSPM is now using the performance state specified.
  *	1: failure. OSPM has not changed the number of P-states in use
  */
 static void acpi_processor_ppc_ost(acpi_handle handle, int status)
@@ -145,6 +156,7 @@ int acpi_processor_get_bios_limit(int cpu, unsigned int *limit)
 	pr = per_cpu(processors, cpu);
 	if (!pr || !pr->performance || !pr->performance->state_count)
 		return -ENODEV;
+
 	*limit = pr->performance->states[pr->performance_platform_limit].
 		core_frequency * 1000;
 	return 0;
@@ -161,6 +173,9 @@ void acpi_processor_ppc_init(struct cpufreq_policy *policy)
 {
 	unsigned int cpu;
 
+	if (ignore_ppc == 1)
+		return;
+
 	for_each_cpu(cpu, policy->related_cpus) {
 		struct acpi_processor *pr = per_cpu(processors, cpu);
 		int ret;
@@ -168,12 +183,27 @@ void acpi_processor_ppc_init(struct cpufreq_policy *policy)
 		if (!pr)
 			continue;
 
+		/*
+		 * Reset performance_platform_limit in case there is a stale
+		 * value in it, so as to make it match the "no limit" QoS value
+		 * below.
+		 */
+		pr->performance_platform_limit = 0;
+
 		ret = freq_qos_add_request(&policy->constraints,
-					   &pr->perflib_req,
-					   FREQ_QOS_MAX, INT_MAX);
+					   &pr->perflib_req, FREQ_QOS_MAX,
+					   FREQ_QOS_MAX_DEFAULT_VALUE);
 		if (ret < 0)
 			pr_err("Failed to add freq constraint for CPU%d (%d)\n",
 			       cpu, ret);
+
+		if (!pr->performance)
+			continue;
+
+		ret = acpi_processor_get_platform_limit(pr);
+		if (ret)
+			pr_err("Failed to update freq constraint for CPU%d (%d)\n",
+			       cpu, ret);
 	}
 }
 
@@ -189,6 +219,10 @@ void acpi_processor_ppc_exit(struct cpufreq_policy *policy)
 	}
 }
 
+#ifdef CONFIG_X86
+
+static DEFINE_MUTEX(performance_mutex);
+
 static int acpi_processor_get_performance_control(struct acpi_processor *pr)
 {
 	int result = 0;
@@ -197,17 +231,15 @@ static int acpi_processor_get_performance_control(struct acpi_processor *pr)
 	union acpi_object *pct = NULL;
 	union acpi_object obj = { 0 };
 
-
 	status = acpi_evaluate_object(pr->handle, "_PCT", NULL, &buffer);
 	if (ACPI_FAILURE(status)) {
-		ACPI_EXCEPTION((AE_INFO, status, "Evaluating _PCT"));
+		acpi_evaluation_failure_warn(pr->handle, "_PCT", status);
 		return -ENODEV;
 	}
 
 	pct = (union acpi_object *)buffer.pointer;
-	if (!pct || (pct->type != ACPI_TYPE_PACKAGE)
-	    || (pct->package.count != 2)) {
-		printk(KERN_ERR PREFIX "Invalid _PCT data\n");
+	if (!pct || pct->type != ACPI_TYPE_PACKAGE || pct->package.count != 2) {
+		pr_err("Invalid _PCT data\n");
 		result = -EFAULT;
 		goto end;
 	}
@@ -218,10 +250,9 @@ static int acpi_processor_get_performance_control(struct acpi_processor *pr)
 
 	obj = pct->package.elements[0];
 
-	if ((obj.type != ACPI_TYPE_BUFFER)
-	    || (obj.buffer.length < sizeof(struct acpi_pct_register))
-	    || (obj.buffer.pointer == NULL)) {
-		printk(KERN_ERR PREFIX "Invalid _PCT data (control_register)\n");
+	if (!obj.buffer.pointer || obj.type != ACPI_TYPE_BUFFER ||
+	    obj.buffer.length < sizeof(struct acpi_pct_register)) {
+		pr_err("Invalid _PCT data (control_register)\n");
 		result = -EFAULT;
 		goto end;
 	}
@@ -234,10 +265,9 @@ static int acpi_processor_get_performance_control(struct acpi_processor *pr)
 
 	obj = pct->package.elements[1];
 
-	if ((obj.type != ACPI_TYPE_BUFFER)
-	    || (obj.buffer.length < sizeof(struct acpi_pct_register))
-	    || (obj.buffer.pointer == NULL)) {
-		printk(KERN_ERR PREFIX "Invalid _PCT data (status_register)\n");
+	if (!obj.buffer.pointer || obj.type != ACPI_TYPE_BUFFER ||
+	    obj.buffer.length < sizeof(struct acpi_pct_register)) {
+		pr_err("Invalid _PCT data (status_register)\n");
 		result = -EFAULT;
 		goto end;
 	}
@@ -245,13 +275,12 @@ static int acpi_processor_get_performance_control(struct acpi_processor *pr)
 	memcpy(&pr->performance->status_register, obj.buffer.pointer,
 	       sizeof(struct acpi_pct_register));
 
-      end:
+end:
 	kfree(buffer.pointer);
 
 	return result;
 }
 
-#ifdef CONFIG_X86
 /*
  * Some AMDs have 50MHz frequency multiples, but only provide 100MHz rounding
  * in their ACPI data. Calculate the real values and fix up the _PSS data.
@@ -264,8 +293,8 @@ static void amd_fixup_frequency(struct acpi_processor_px *px, int i)
 	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
 		return;
 
-	if ((boot_cpu_data.x86 == 0x10 && boot_cpu_data.x86_model < 10)
-	    || boot_cpu_data.x86 == 0x11) {
+	if ((boot_cpu_data.x86 == 0x10 && boot_cpu_data.x86_model < 10) ||
+	    boot_cpu_data.x86 == 0x11) {
 		rdmsr(MSR_AMD_PSTATE_DEF_BASE + index, lo, hi);
 		/*
 		 * MSR C001_0064+:
@@ -282,9 +311,6 @@ static void amd_fixup_frequency(struct acpi_processor_px *px, int i)
 			px->core_frequency = (100 * (fid + 8)) >> did;
 	}
 }
-#else
-static void amd_fixup_frequency(struct acpi_processor_px *px, int i) {};
-#endif
 
 static int acpi_processor_get_performance_states(struct acpi_processor *pr)
 {
@@ -297,22 +323,21 @@ static int acpi_processor_get_performance_states(struct acpi_processor *pr)
 	int i;
 	int last_invalid = -1;
 
-
 	status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
 	if (ACPI_FAILURE(status)) {
-		ACPI_EXCEPTION((AE_INFO, status, "Evaluating _PSS"));
+		acpi_evaluation_failure_warn(pr->handle, "_PSS", status);
 		return -ENODEV;
 	}
 
 	pss = buffer.pointer;
-	if (!pss || (pss->type != ACPI_TYPE_PACKAGE)) {
-		printk(KERN_ERR PREFIX "Invalid _PSS data\n");
+	if (!pss || pss->type != ACPI_TYPE_PACKAGE) {
+		pr_err("Invalid _PSS data\n");
 		result = -EFAULT;
 		goto end;
 	}
 
-	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found %d performance states\n",
-			  pss->package.count));
+	acpi_handle_debug(pr->handle, "Found %d performance states\n",
+			  pss->package.count);
 
 	pr->performance->state_count = pss->package.count;
 	pr->performance->states =
@@ -331,12 +356,13 @@ static int acpi_processor_get_performance_states(struct acpi_processor *pr)
 		state.length = sizeof(struct acpi_processor_px);
 		state.pointer = px;
 
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Extracting state %d\n", i));
+		acpi_handle_debug(pr->handle, "Extracting state %d\n", i);
 
 		status = acpi_extract_package(&(pss->package.elements[i]),
 					      &format, &state);
 		if (ACPI_FAILURE(status)) {
-			ACPI_EXCEPTION((AE_INFO, status, "Invalid _PSS data"));
+			acpi_handle_warn(pr->handle, "Invalid _PSS data: %s\n",
+					 acpi_format_exception(status));
 			result = -EFAULT;
 			kfree(pr->performance->states);
 			goto end;
@@ -344,22 +370,21 @@ static int acpi_processor_get_performance_states(struct acpi_processor *pr)
 
 		amd_fixup_frequency(px, i);
 
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO,
+		acpi_handle_debug(pr->handle,
 				  "State [%d]: core_frequency[%d] power[%d] transition_latency[%d] bus_master_latency[%d] control[0x%x] status[0x%x]\n",
 				  i,
 				  (u32) px->core_frequency,
 				  (u32) px->power,
 				  (u32) px->transition_latency,
 				  (u32) px->bus_master_latency,
-				  (u32) px->control, (u32) px->status));
+				  (u32) px->control, (u32) px->status);
 
 		/*
- 		 * Check that ACPI's u64 MHz will be valid as u32 KHz in cpufreq
+		 * Check that ACPI's u64 MHz will be valid as u32 KHz in cpufreq
 		 */
 		if (!px->core_frequency ||
-		    ((u32)(px->core_frequency * 1000) !=
-		     (px->core_frequency * 1000))) {
-			printk(KERN_ERR FW_BUG PREFIX
+		    (u32)(px->core_frequency * 1000) != px->core_frequency * 1000) {
+			pr_err(FW_BUG
 			       "Invalid BIOS _PSS frequency found for processor %d: 0x%llx MHz\n",
 			       pr->id, px->core_frequency);
 			if (last_invalid == -1)
@@ -377,8 +402,8 @@ static int acpi_processor_get_performance_states(struct acpi_processor *pr)
 	}
 
 	if (last_invalid == 0) {
-		printk(KERN_ERR FW_BUG PREFIX
-		       "No valid BIOS _PSS frequency found for processor %d\n", pr->id);
+		pr_err(FW_BUG
+			   "No valid BIOS _PSS frequency found for processor %d\n", pr->id);
 		result = -EFAULT;
 		kfree(pr->performance->states);
 		pr->performance->states = NULL;
@@ -387,7 +412,7 @@ static int acpi_processor_get_performance_states(struct acpi_processor *pr)
 	if (last_invalid > 0)
 		pr->performance->state_count = last_invalid;
 
-      end:
+end:
 	kfree(buffer.pointer);
 
 	return result;
@@ -401,8 +426,8 @@ int acpi_processor_get_performance_info(struct acpi_processor *pr)
 		return -EINVAL;
 
 	if (!acpi_has_method(pr->handle, "_PCT")) {
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-				  "ACPI-based processor performance control unavailable\n"));
+		acpi_handle_debug(pr->handle,
+				  "ACPI-based processor performance control unavailable\n");
 		return -ENODEV;
 	}
 
@@ -425,13 +450,11 @@ int acpi_processor_get_performance_info(struct acpi_processor *pr)
 	 * the BIOS is older than the CPU and does not know its frequencies
 	 */
  update_bios:
-#ifdef CONFIG_X86
 	if (acpi_has_method(pr->handle, "_PPC")) {
 		if(boot_cpu_has(X86_FEATURE_EST))
-			printk(KERN_WARNING FW_BUG "BIOS needs update for CPU "
+			pr_warn(FW_BUG "BIOS needs update for CPU "
 			       "frequency support\n");
 	}
-#endif
 	return result;
 }
 EXPORT_SYMBOL_GPL(acpi_processor_get_performance_info);
@@ -443,25 +466,24 @@ int acpi_processor_pstate_control(void)
 	if (!acpi_gbl_FADT.smi_command || !acpi_gbl_FADT.pstate_control)
 		return 0;
 
-	ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-			  "Writing pstate_control [0x%x] to smi_command [0x%x]\n",
-			  acpi_gbl_FADT.pstate_control, acpi_gbl_FADT.smi_command));
+	pr_debug("Writing pstate_control [0x%x] to smi_command [0x%x]\n",
+		 acpi_gbl_FADT.pstate_control, acpi_gbl_FADT.smi_command);
 
 	status = acpi_os_write_port(acpi_gbl_FADT.smi_command,
 				    (u32)acpi_gbl_FADT.pstate_control, 8);
 	if (ACPI_SUCCESS(status))
 		return 1;
 
-	ACPI_EXCEPTION((AE_INFO, status,
-			"Failed to write pstate_control [0x%x] to smi_command [0x%x]",
-			acpi_gbl_FADT.pstate_control, acpi_gbl_FADT.smi_command));
+	pr_warn("Failed to write pstate_control [0x%x] to smi_command [0x%x]: %s\n",
+		acpi_gbl_FADT.pstate_control, acpi_gbl_FADT.smi_command,
+		acpi_format_exception(status));
 	return -EIO;
 }
 
 int acpi_processor_notify_smm(struct module *calling_module)
 {
-	static int is_done = 0;
-	int result;
+	static int is_done;
+	int result = 0;
 
 	if (!acpi_processor_cpufreq_init)
 		return -EBUSY;
@@ -469,42 +491,41 @@ int acpi_processor_notify_smm(struct module *calling_module)
 	if (!try_module_get(calling_module))
 		return -EINVAL;
 
-	/* is_done is set to negative if an error occurred,
-	 * and to postitive if _no_ error occurred, but SMM
-	 * was already notified. This avoids double notification
-	 * which might lead to unexpected results...
+	/*
+	 * is_done is set to negative if an error occurs and to 1 if no error
+	 * occurrs, but SMM has been notified already. This avoids repeated
+	 * notification which might lead to unexpected results.
 	 */
-	if (is_done > 0) {
-		module_put(calling_module);
-		return 0;
-	} else if (is_done < 0) {
-		module_put(calling_module);
-		return is_done;
-	}
+	if (is_done != 0) {
+		if (is_done < 0)
+			result = is_done;
 
-	is_done = -EIO;
+		goto out_put;
+	}
 
 	result = acpi_processor_pstate_control();
-	if (!result) {
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No SMI port or pstate_control\n"));
-		module_put(calling_module);
-		return 0;
-	}
-	if (result < 0) {
-		module_put(calling_module);
-		return result;
+	if (result <= 0) {
+		if (result) {
+			is_done = result;
+		} else {
+			pr_debug("No SMI port or pstate_control\n");
+			is_done = 1;
+		}
+		goto out_put;
 	}
 
-	/* Success. If there's no _PPC, we need to fear nothing, so
-	 * we can allow the cpufreq driver to be rmmod'ed. */
 	is_done = 1;
+	/*
+	 * Success. If there _PPC, unloading the cpufreq driver would be risky,
+	 * so disallow it in that case.
+	 */
+	if (acpi_processor_ppc_in_use)
+		return 0;
 
-	if (!acpi_processor_ppc_in_use)
-		module_put(calling_module);
-
-	return 0;
+out_put:
+	module_put(calling_module);
+	return result;
 }
-
 EXPORT_SYMBOL(acpi_processor_notify_smm);
 
 int acpi_processor_get_psd(acpi_handle handle, struct acpi_psd_package *pdomain)
@@ -522,14 +543,14 @@ int acpi_processor_get_psd(acpi_handle handle, struct acpi_psd_package *pdomain)
 	}
 
 	psd = buffer.pointer;
-	if (!psd || (psd->type != ACPI_TYPE_PACKAGE)) {
-		printk(KERN_ERR PREFIX "Invalid _PSD data\n");
+	if (!psd || psd->type != ACPI_TYPE_PACKAGE) {
+		pr_err("Invalid _PSD data\n");
 		result = -EFAULT;
 		goto end;
 	}
 
 	if (psd->package.count != 1) {
-		printk(KERN_ERR PREFIX "Invalid _PSD data\n");
+		pr_err("Invalid _PSD data\n");
 		result = -EFAULT;
 		goto end;
 	}
@@ -537,22 +558,21 @@ int acpi_processor_get_psd(acpi_handle handle, struct acpi_psd_package *pdomain)
 	state.length = sizeof(struct acpi_psd_package);
 	state.pointer = pdomain;
 
-	status = acpi_extract_package(&(psd->package.elements[0]),
-		&format, &state);
+	status = acpi_extract_package(&(psd->package.elements[0]), &format, &state);
 	if (ACPI_FAILURE(status)) {
-		printk(KERN_ERR PREFIX "Invalid _PSD data\n");
+		pr_err("Invalid _PSD data\n");
 		result = -EFAULT;
 		goto end;
 	}
 
 	if (pdomain->num_entries != ACPI_PSD_REV0_ENTRIES) {
-		printk(KERN_ERR PREFIX "Unknown _PSD:num_entries\n");
+		pr_err("Unknown _PSD:num_entries\n");
 		result = -EFAULT;
 		goto end;
 	}
 
 	if (pdomain->revision != ACPI_PSD_REV0_REVISION) {
-		printk(KERN_ERR PREFIX "Unknown _PSD:revision\n");
+		pr_err("Unknown _PSD:revision\n");
 		result = -EFAULT;
 		goto end;
 	}
@@ -560,7 +580,7 @@ int acpi_processor_get_psd(acpi_handle handle, struct acpi_psd_package *pdomain)
 	if (pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ALL &&
 	    pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ANY &&
 	    pdomain->coord_type != DOMAIN_COORD_TYPE_HW_ALL) {
-		printk(KERN_ERR PREFIX "Invalid _PSD:coord_type\n");
+		pr_err("Invalid _PSD:coord_type\n");
 		result = -EFAULT;
 		goto end;
 	}
@@ -616,7 +636,6 @@ int acpi_processor_preregister_performance(
 			continue;
 
 		pr->performance = per_cpu_ptr(performance, i);
-		cpumask_set_cpu(i, pr->performance->shared_cpu_map);
 		pdomain = &(pr->performance->domain_info);
 		if (acpi_processor_get_psd(pr->handle, pdomain)) {
 			retval = -EINVAL;
@@ -627,7 +646,7 @@ int acpi_processor_preregister_performance(
 		goto err_ret;
 
 	/*
-	 * Now that we have _PSD data from all CPUs, lets setup P-state 
+	 * Now that we have _PSD data from all CPUs, lets setup P-state
 	 * domain info.
 	 */
 	for_each_possible_cpu(i) {
@@ -693,7 +712,7 @@ int acpi_processor_preregister_performance(
 			if (match_pdomain->domain != pdomain->domain)
 				continue;
 
-			match_pr->performance->shared_type = 
+			match_pr->performance->shared_type =
 					pr->performance->shared_type;
 			cpumask_copy(match_pr->performance->shared_cpu_map,
 				     pr->performance->shared_cpu_map);
@@ -710,7 +729,7 @@ err_ret:
 		if (retval) {
 			cpumask_clear(pr->performance->shared_cpu_map);
 			cpumask_set_cpu(i, pr->performance->shared_cpu_map);
-			pr->performance->shared_type = CPUFREQ_SHARED_TYPE_ALL;
+			pr->performance->shared_type = CPUFREQ_SHARED_TYPE_NONE;
 		}
 		pr->performance = NULL; /* Will be set for real in register */
 	}
@@ -722,9 +741,8 @@ err_out:
 }
 EXPORT_SYMBOL(acpi_processor_preregister_performance);
 
-int
-acpi_processor_register_performance(struct acpi_processor_performance
-				    *performance, unsigned int cpu)
+int acpi_processor_register_performance(struct acpi_processor_performance
+					*performance, unsigned int cpu)
 {
 	struct acpi_processor *pr;
 
@@ -757,7 +775,6 @@ acpi_processor_register_performance(struct acpi_processor_performance
 	mutex_unlock(&performance_mutex);
 	return 0;
 }
-
 EXPORT_SYMBOL(acpi_processor_register_performance);
 
 void acpi_processor_unregister_performance(unsigned int cpu)
@@ -767,18 +784,16 @@ void acpi_processor_unregister_performance(unsigned int cpu)
 	mutex_lock(&performance_mutex);
 
 	pr = per_cpu(processors, cpu);
-	if (!pr) {
-		mutex_unlock(&performance_mutex);
-		return;
-	}
+	if (!pr)
+		goto unlock;
 
 	if (pr->performance)
 		kfree(pr->performance->states);
+
 	pr->performance = NULL;
 
+unlock:
 	mutex_unlock(&performance_mutex);
-
-	return;
 }
-
 EXPORT_SYMBOL(acpi_processor_unregister_performance);
+#endif
diff --git a/drivers/acpi/processor_thermal.c b/drivers/acpi/processor_thermal.c
index 41feb88ee92d..c7b1dc5687ec 100644
--- a/drivers/acpi/processor_thermal.c
+++ b/drivers/acpi/processor_thermal.c
@@ -17,11 +17,7 @@
 #include <acpi/processor.h>
 #include <linux/uaccess.h>
 
-#define PREFIX "ACPI: "
-
-#define ACPI_PROCESSOR_CLASS            "processor"
-#define _COMPONENT              ACPI_PROCESSOR_COMPONENT
-ACPI_MODULE_NAME("processor_thermal");
+#include "internal.h"
 
 #ifdef CONFIG_CPU_FREQ
 
@@ -32,12 +28,21 @@ ACPI_MODULE_NAME("processor_thermal");
  */
 
 #define CPUFREQ_THERMAL_MIN_STEP 0
-#define CPUFREQ_THERMAL_MAX_STEP 3
 
-static DEFINE_PER_CPU(unsigned int, cpufreq_thermal_reduction_pctg);
+static int cpufreq_thermal_max_step __read_mostly = 3;
+
+/*
+ * Minimum throttle percentage for processor_thermal cooling device.
+ * The processor_thermal driver uses it to calculate the percentage amount by
+ * which cpu frequency must be reduced for each cooling state. This is also used
+ * to calculate the maximum number of throttling steps or cooling states.
+ */
+static int cpufreq_thermal_reduction_pctg __read_mostly = 20;
+
+static DEFINE_PER_CPU(unsigned int, cpufreq_thermal_reduction_step);
 
-#define reduction_pctg(cpu) \
-	per_cpu(cpufreq_thermal_reduction_pctg, phys_package_first_cpu(cpu))
+#define reduction_step(cpu) \
+	per_cpu(cpufreq_thermal_reduction_step, phys_package_first_cpu(cpu))
 
 /*
  * Emulate "per package data" using per cpu data (which should really be
@@ -57,12 +62,14 @@ static int phys_package_first_cpu(int cpu)
 	return 0;
 }
 
-static int cpu_has_cpufreq(unsigned int cpu)
+static bool cpu_has_cpufreq(unsigned int cpu)
 {
-	struct cpufreq_policy policy;
-	if (!acpi_processor_cpufreq_init || cpufreq_get_policy(&policy, cpu))
+	if (!acpi_processor_cpufreq_init)
 		return 0;
-	return 1;
+
+	struct cpufreq_policy *policy __free(put_cpufreq_policy) = cpufreq_cpu_get(cpu);
+
+	return policy != NULL;
 }
 
 static int cpufreq_get_max_state(unsigned int cpu)
@@ -70,7 +77,7 @@ static int cpufreq_get_max_state(unsigned int cpu)
 	if (!cpu_has_cpufreq(cpu))
 		return 0;
 
-	return CPUFREQ_THERMAL_MAX_STEP;
+	return cpufreq_thermal_max_step;
 }
 
 static int cpufreq_get_cur_state(unsigned int cpu)
@@ -78,20 +85,39 @@ static int cpufreq_get_cur_state(unsigned int cpu)
 	if (!cpu_has_cpufreq(cpu))
 		return 0;
 
-	return reduction_pctg(cpu);
+	return reduction_step(cpu);
+}
+
+static bool cpufreq_update_thermal_limit(unsigned int cpu, struct acpi_processor *pr)
+{
+	unsigned long max_freq;
+	int ret;
+
+	struct cpufreq_policy *policy __free(put_cpufreq_policy) = cpufreq_cpu_get(cpu);
+	if (!policy)
+		return false;
+
+	max_freq = (policy->cpuinfo.max_freq *
+		(100 - reduction_step(cpu) * cpufreq_thermal_reduction_pctg)) / 100;
+
+	ret = freq_qos_update_request(&pr->thermal_req, max_freq);
+	if (ret < 0) {
+		pr_warn("Failed to update thermal freq constraint: CPU%d (%d)\n",
+			pr->id, ret);
+	}
+
+	return true;
 }
 
 static int cpufreq_set_cur_state(unsigned int cpu, int state)
 {
-	struct cpufreq_policy *policy;
 	struct acpi_processor *pr;
-	unsigned long max_freq;
-	int i, ret;
+	int i;
 
 	if (!cpu_has_cpufreq(cpu))
 		return 0;
 
-	reduction_pctg(cpu) = state;
+	reduction_step(cpu) = state;
 
 	/*
 	 * Update all the CPUs in the same package because they all
@@ -108,27 +134,35 @@ static int cpufreq_set_cur_state(unsigned int cpu, int state)
 		if (unlikely(!freq_qos_request_active(&pr->thermal_req)))
 			continue;
 
-		policy = cpufreq_cpu_get(i);
-		if (!policy)
+		if (!cpufreq_update_thermal_limit(i, pr))
 			return -EINVAL;
+	}
+	return 0;
+}
 
-		max_freq = (policy->cpuinfo.max_freq * (100 - reduction_pctg(i) * 20)) / 100;
+static void acpi_thermal_cpufreq_config(void)
+{
+	int cpufreq_pctg = acpi_arch_thermal_cpufreq_pctg();
 
-		cpufreq_cpu_put(policy);
+	if (!cpufreq_pctg)
+		return;
 
-		ret = freq_qos_update_request(&pr->thermal_req, max_freq);
-		if (ret < 0) {
-			pr_warn("Failed to update thermal freq constraint: CPU%d (%d)\n",
-				pr->id, ret);
-		}
-	}
-	return 0;
+	cpufreq_thermal_reduction_pctg = cpufreq_pctg;
+
+	/*
+	 * Derive the MAX_STEP from minimum throttle percentage so that the reduction
+	 * percentage doesn't end up becoming negative. Also, cap the MAX_STEP so that
+	 * the CPU performance doesn't become 0.
+	 */
+	cpufreq_thermal_max_step = (100 / cpufreq_pctg) - 2;
 }
 
 void acpi_thermal_cpufreq_init(struct cpufreq_policy *policy)
 {
 	unsigned int cpu;
 
+	acpi_thermal_cpufreq_config();
+
 	for_each_cpu(cpu, policy->related_cpus) {
 		struct acpi_processor *pr = per_cpu(processors, cpu);
 		int ret;
@@ -139,9 +173,13 @@ void acpi_thermal_cpufreq_init(struct cpufreq_policy *policy)
 		ret = freq_qos_add_request(&policy->constraints,
 					   &pr->thermal_req,
 					   FREQ_QOS_MAX, INT_MAX);
-		if (ret < 0)
+		if (ret < 0) {
 			pr_err("Failed to add freq constraint for CPU%d (%d)\n",
 			       cpu, ret);
+			continue;
+		}
+
+		thermal_cooling_device_update(pr->cdev);
 	}
 }
 
@@ -150,10 +188,14 @@ void acpi_thermal_cpufreq_exit(struct cpufreq_policy *policy)
 	unsigned int cpu;
 
 	for_each_cpu(cpu, policy->related_cpus) {
-		struct acpi_processor *pr = per_cpu(processors, policy->cpu);
+		struct acpi_processor *pr = per_cpu(processors, cpu);
+
+		if (!pr)
+			continue;
 
-		if (pr)
-			freq_qos_remove_request(&pr->thermal_req);
+		freq_qos_remove_request(&pr->thermal_req);
+
+		thermal_cooling_device_update(pr->cdev);
 	}
 }
 #else				/* ! CONFIG_CPU_FREQ */
@@ -181,7 +223,7 @@ static int acpi_processor_max_state(struct acpi_processor *pr)
 
 	/*
 	 * There exists four states according to
-	 * cpufreq_thermal_reduction_pctg. 0, 1, 2, 3
+	 * cpufreq_thermal_reduction_step. 0, 1, 2, 3
 	 */
 	max_state += cpufreq_get_max_state(pr->id);
 	if (pr->flags.throttling)
@@ -265,3 +307,57 @@ const struct thermal_cooling_device_ops processor_cooling_ops = {
 	.get_cur_state = processor_get_cur_state,
 	.set_cur_state = processor_set_cur_state,
 };
+
+int acpi_processor_thermal_init(struct acpi_processor *pr,
+				struct acpi_device *device)
+{
+	int result = 0;
+
+	pr->cdev = thermal_cooling_device_register("Processor", device,
+						   &processor_cooling_ops);
+	if (IS_ERR(pr->cdev)) {
+		result = PTR_ERR(pr->cdev);
+		return result;
+	}
+
+	dev_dbg(&device->dev, "registered as cooling_device%d\n",
+		pr->cdev->id);
+
+	result = sysfs_create_link(&device->dev.kobj,
+				   &pr->cdev->device.kobj,
+				   "thermal_cooling");
+	if (result) {
+		dev_err(&device->dev,
+			"Failed to create sysfs link 'thermal_cooling'\n");
+		goto err_thermal_unregister;
+	}
+
+	result = sysfs_create_link(&pr->cdev->device.kobj,
+				   &device->dev.kobj,
+				   "device");
+	if (result) {
+		dev_err(&pr->cdev->device,
+			"Failed to create sysfs link 'device'\n");
+		goto err_remove_sysfs_thermal;
+	}
+
+	return 0;
+
+err_remove_sysfs_thermal:
+	sysfs_remove_link(&device->dev.kobj, "thermal_cooling");
+err_thermal_unregister:
+	thermal_cooling_device_unregister(pr->cdev);
+
+	return result;
+}
+
+void acpi_processor_thermal_exit(struct acpi_processor *pr,
+				 struct acpi_device *device)
+{
+	if (pr->cdev) {
+		sysfs_remove_link(&device->dev.kobj, "thermal_cooling");
+		sysfs_remove_link(&pr->cdev->device.kobj, "device");
+		thermal_cooling_device_unregister(pr->cdev);
+		pr->cdev = NULL;
+	}
+}
diff --git a/drivers/acpi/processor_throttling.c b/drivers/acpi/processor_throttling.c
index a0bd56ece3ff..f9c2bc1d4a3a 100644
--- a/drivers/acpi/processor_throttling.c
+++ b/drivers/acpi/processor_throttling.c
@@ -6,9 +6,11 @@
  *  Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
  *  Copyright (C) 2004       Dominik Brodowski <linux@brodo.de>
  *  Copyright (C) 2004  Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
- *  			- Added processor hotplug support
+ *                      - Added processor hotplug support
  */
 
+#define pr_fmt(fmt) "ACPI: " fmt
+
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/slab.h>
@@ -16,15 +18,12 @@
 #include <linux/sched.h>
 #include <linux/cpufreq.h>
 #include <linux/acpi.h>
+#include <linux/uaccess.h>
 #include <acpi/processor.h>
 #include <asm/io.h>
-#include <linux/uaccess.h>
-
-#define PREFIX "ACPI: "
-
-#define ACPI_PROCESSOR_CLASS            "processor"
-#define _COMPONENT              ACPI_PROCESSOR_COMPONENT
-ACPI_MODULE_NAME("processor_throttling");
+#ifdef CONFIG_X86
+#include <asm/msr.h>
+#endif
 
 /* ignore_tpc:
  *  0 -> acpi processor driver doesn't ignore _TPC values
@@ -54,7 +53,7 @@ static int __acpi_processor_set_throttling(struct acpi_processor *pr,
 
 static int acpi_processor_update_tsd_coord(void)
 {
-	int count, count_target;
+	int count_target;
 	int retval = 0;
 	unsigned int i, j;
 	cpumask_var_t covered_cpus;
@@ -111,7 +110,6 @@ static int acpi_processor_update_tsd_coord(void)
 
 		/* Validate the Domain info */
 		count_target = pdomain->num_processors;
-		count = 1;
 
 		for_each_possible_cpu(j) {
 			if (i == j)
@@ -144,7 +142,6 @@ static int acpi_processor_update_tsd_coord(void)
 
 			cpumask_set_cpu(j, covered_cpus);
 			cpumask_set_cpu(j, pthrottling->shared_cpu_map);
-			count++;
 		}
 		for_each_possible_cpu(j) {
 			if (i == j)
@@ -197,19 +194,15 @@ err_ret:
  */
 void acpi_processor_throttling_init(void)
 {
-	if (acpi_processor_update_tsd_coord()) {
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-			"Assume no T-state coordination\n"));
-	}
-
-	return;
+	if (acpi_processor_update_tsd_coord())
+		pr_debug("Assume no T-state coordination\n");
 }
 
 static int acpi_processor_throttling_notifier(unsigned long event, void *data)
 {
 	struct throttling_tstate *p_tstate = data;
 	struct acpi_processor *pr;
-	unsigned int cpu ;
+	unsigned int cpu;
 	int target_state;
 	struct acpi_processor_limit *p_limit;
 	struct acpi_processor_throttling *p_throttling;
@@ -217,12 +210,13 @@ static int acpi_processor_throttling_notifier(unsigned long event, void *data)
 	cpu = p_tstate->cpu;
 	pr = per_cpu(processors, cpu);
 	if (!pr) {
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Invalid pr pointer\n"));
+		pr_debug("Invalid pr pointer\n");
 		return 0;
 	}
 	if (!pr->flags.throttling) {
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Throttling control is "
-				"unsupported on CPU %d\n", cpu));
+		acpi_handle_debug(pr->handle,
+				  "Throttling control unsupported on CPU %d\n",
+				  cpu);
 		return 0;
 	}
 	target_state = p_tstate->target_state;
@@ -241,14 +235,13 @@ static int acpi_processor_throttling_notifier(unsigned long event, void *data)
 		if (pr->throttling_platform_limit > target_state)
 			target_state = pr->throttling_platform_limit;
 		if (target_state >= p_throttling->state_count) {
-			printk(KERN_WARNING
-				"Exceed the limit of T-state \n");
+			pr_warn("Exceed the limit of T-state\n");
 			target_state = p_throttling->state_count - 1;
 		}
 		p_tstate->target_state = target_state;
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "PreChange Event:"
-				"target T-state of CPU %d is T%d\n",
-				cpu, target_state));
+		acpi_handle_debug(pr->handle,
+				  "PreChange Event: target T-state of CPU %d is T%d\n",
+				  cpu, target_state);
 		break;
 	case THROTTLING_POSTCHANGE:
 		/*
@@ -256,13 +249,12 @@ static int acpi_processor_throttling_notifier(unsigned long event, void *data)
 		 * T-state flag of acpi_processor_throttling.
 		 */
 		p_throttling->state = target_state;
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "PostChange Event:"
-				"CPU %d is switched to T%d\n",
-				cpu, target_state));
+		acpi_handle_debug(pr->handle,
+				  "PostChange Event: CPU %d is switched to T%d\n",
+				  cpu, target_state);
 		break;
 	default:
-		printk(KERN_WARNING
-			"Unsupported Throttling notifier event\n");
+		pr_warn("Unsupported Throttling notifier event\n");
 		break;
 	}
 
@@ -285,9 +277,9 @@ static int acpi_processor_get_platform_limit(struct acpi_processor *pr)
 
 	status = acpi_evaluate_integer(pr->handle, "_TPC", NULL, &tpc);
 	if (ACPI_FAILURE(status)) {
-		if (status != AE_NOT_FOUND) {
-			ACPI_EXCEPTION((AE_INFO, status, "Evaluating _TPC"));
-		}
+		if (status != AE_NOT_FOUND)
+			acpi_evaluation_failure_warn(pr->handle, "_TPC", status);
+
 		return -ENODEV;
 	}
 
@@ -413,21 +405,21 @@ static int acpi_processor_get_throttling_control(struct acpi_processor *pr)
 	acpi_status status = 0;
 	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
 	union acpi_object *ptc = NULL;
-	union acpi_object obj = { 0 };
+	union acpi_object obj;
 	struct acpi_processor_throttling *throttling;
 
 	status = acpi_evaluate_object(pr->handle, "_PTC", NULL, &buffer);
 	if (ACPI_FAILURE(status)) {
-		if (status != AE_NOT_FOUND) {
-			ACPI_EXCEPTION((AE_INFO, status, "Evaluating _PTC"));
-		}
+		if (status != AE_NOT_FOUND)
+			acpi_evaluation_failure_warn(pr->handle, "_PTC", status);
+
 		return -ENODEV;
 	}
 
 	ptc = (union acpi_object *)buffer.pointer;
 	if (!ptc || (ptc->type != ACPI_TYPE_PACKAGE)
 	    || (ptc->package.count != 2)) {
-		printk(KERN_ERR PREFIX "Invalid _PTC data\n");
+		pr_err("Invalid _PTC data\n");
 		result = -EFAULT;
 		goto end;
 	}
@@ -441,8 +433,7 @@ static int acpi_processor_get_throttling_control(struct acpi_processor *pr)
 	if ((obj.type != ACPI_TYPE_BUFFER)
 	    || (obj.buffer.length < sizeof(struct acpi_ptc_register))
 	    || (obj.buffer.pointer == NULL)) {
-		printk(KERN_ERR PREFIX
-		       "Invalid _PTC data (control_register)\n");
+		pr_err("Invalid _PTC data (control_register)\n");
 		result = -EFAULT;
 		goto end;
 	}
@@ -458,7 +449,7 @@ static int acpi_processor_get_throttling_control(struct acpi_processor *pr)
 	if ((obj.type != ACPI_TYPE_BUFFER)
 	    || (obj.buffer.length < sizeof(struct acpi_ptc_register))
 	    || (obj.buffer.pointer == NULL)) {
-		printk(KERN_ERR PREFIX "Invalid _PTC data (status_register)\n");
+		pr_err("Invalid _PTC data (status_register)\n");
 		result = -EFAULT;
 		goto end;
 	}
@@ -470,19 +461,19 @@ static int acpi_processor_get_throttling_control(struct acpi_processor *pr)
 
 	if ((throttling->control_register.bit_width +
 		throttling->control_register.bit_offset) > 32) {
-		printk(KERN_ERR PREFIX "Invalid _PTC control register\n");
+		pr_err("Invalid _PTC control register\n");
 		result = -EFAULT;
 		goto end;
 	}
 
 	if ((throttling->status_register.bit_width +
 		throttling->status_register.bit_offset) > 32) {
-		printk(KERN_ERR PREFIX "Invalid _PTC status register\n");
+		pr_err("Invalid _PTC status register\n");
 		result = -EFAULT;
 		goto end;
 	}
 
-      end:
+end:
 	kfree(buffer.pointer);
 
 	return result;
@@ -503,21 +494,21 @@ static int acpi_processor_get_throttling_states(struct acpi_processor *pr)
 
 	status = acpi_evaluate_object(pr->handle, "_TSS", NULL, &buffer);
 	if (ACPI_FAILURE(status)) {
-		if (status != AE_NOT_FOUND) {
-			ACPI_EXCEPTION((AE_INFO, status, "Evaluating _TSS"));
-		}
+		if (status != AE_NOT_FOUND)
+			acpi_evaluation_failure_warn(pr->handle, "_TSS", status);
+
 		return -ENODEV;
 	}
 
 	tss = buffer.pointer;
 	if (!tss || (tss->type != ACPI_TYPE_PACKAGE)) {
-		printk(KERN_ERR PREFIX "Invalid _TSS data\n");
+		pr_err("Invalid _TSS data\n");
 		result = -EFAULT;
 		goto end;
 	}
 
-	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found %d throttling states\n",
-			  tss->package.count));
+	acpi_handle_debug(pr->handle, "Found %d throttling states\n",
+			  tss->package.count);
 
 	pr->throttling.state_count = tss->package.count;
 	pr->throttling.states_tss =
@@ -538,27 +529,27 @@ static int acpi_processor_get_throttling_states(struct acpi_processor *pr)
 		state.length = sizeof(struct acpi_processor_tx_tss);
 		state.pointer = tx;
 
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Extracting state %d\n", i));
+		acpi_handle_debug(pr->handle, "Extracting state %d\n", i);
 
 		status = acpi_extract_package(&(tss->package.elements[i]),
 					      &format, &state);
 		if (ACPI_FAILURE(status)) {
-			ACPI_EXCEPTION((AE_INFO, status, "Invalid _TSS data"));
+			acpi_handle_warn(pr->handle, "Invalid _TSS data: %s\n",
+					 acpi_format_exception(status));
 			result = -EFAULT;
 			kfree(pr->throttling.states_tss);
 			goto end;
 		}
 
 		if (!tx->freqpercentage) {
-			printk(KERN_ERR PREFIX
-			       "Invalid _TSS data: freq is zero\n");
+			pr_err("Invalid _TSS data: freq is zero\n");
 			result = -EFAULT;
 			kfree(pr->throttling.states_tss);
 			goto end;
 		}
 	}
 
-      end:
+end:
 	kfree(buffer.pointer);
 
 	return result;
@@ -583,21 +574,21 @@ static int acpi_processor_get_tsd(struct acpi_processor *pr)
 
 	status = acpi_evaluate_object(pr->handle, "_TSD", NULL, &buffer);
 	if (ACPI_FAILURE(status)) {
-		if (status != AE_NOT_FOUND) {
-			ACPI_EXCEPTION((AE_INFO, status, "Evaluating _TSD"));
-		}
+		if (status != AE_NOT_FOUND)
+			acpi_evaluation_failure_warn(pr->handle, "_TSD", status);
+
 		return -ENODEV;
 	}
 
 	tsd = buffer.pointer;
 	if (!tsd || (tsd->type != ACPI_TYPE_PACKAGE)) {
-		printk(KERN_ERR PREFIX "Invalid _TSD data\n");
+		pr_err("Invalid _TSD data\n");
 		result = -EFAULT;
 		goto end;
 	}
 
 	if (tsd->package.count != 1) {
-		printk(KERN_ERR PREFIX "Invalid _TSD data\n");
+		pr_err("Invalid _TSD data\n");
 		result = -EFAULT;
 		goto end;
 	}
@@ -610,19 +601,19 @@ static int acpi_processor_get_tsd(struct acpi_processor *pr)
 	status = acpi_extract_package(&(tsd->package.elements[0]),
 				      &format, &state);
 	if (ACPI_FAILURE(status)) {
-		printk(KERN_ERR PREFIX "Invalid _TSD data\n");
+		pr_err("Invalid _TSD data\n");
 		result = -EFAULT;
 		goto end;
 	}
 
 	if (pdomain->num_entries != ACPI_TSD_REV0_ENTRIES) {
-		printk(KERN_ERR PREFIX "Unknown _TSD:num_entries\n");
+		pr_err("Unknown _TSD:num_entries\n");
 		result = -EFAULT;
 		goto end;
 	}
 
 	if (pdomain->revision != ACPI_TSD_REV0_REVISION) {
-		printk(KERN_ERR PREFIX "Unknown _TSD:revision\n");
+		pr_err("Unknown _TSD:revision\n");
 		result = -EFAULT;
 		goto end;
 	}
@@ -643,7 +634,7 @@ static int acpi_processor_get_tsd(struct acpi_processor *pr)
 		pthrottling->shared_type = DOMAIN_COORD_TYPE_SW_ALL;
 	}
 
-      end:
+end:
 	kfree(buffer.pointer);
 	return result;
 }
@@ -699,9 +690,9 @@ static int acpi_processor_get_throttling_fadt(struct acpi_processor *pr)
 
 	local_irq_enable();
 
-	ACPI_DEBUG_PRINT((ACPI_DB_INFO,
+	acpi_handle_debug(pr->handle,
 			  "Throttling state is T%d (%d%% throttling applied)\n",
-			  state, pr->throttling.states[state].performance));
+			  state, pr->throttling.states[state].performance);
 
 	return 0;
 }
@@ -715,13 +706,12 @@ static int acpi_throttling_rdmsr(u64 *value)
 
 	if ((this_cpu_read(cpu_info.x86_vendor) != X86_VENDOR_INTEL) ||
 		!this_cpu_has(X86_FEATURE_ACPI)) {
-		printk(KERN_ERR PREFIX
-			"HARDWARE addr space,NOT supported yet\n");
+		pr_err("HARDWARE addr space,NOT supported yet\n");
 	} else {
 		msr_low = 0;
 		msr_high = 0;
 		rdmsr_safe(MSR_IA32_THERM_CONTROL,
-			(u32 *)&msr_low , (u32 *) &msr_high);
+			(u32 *)&msr_low, (u32 *) &msr_high);
 		msr = (msr_high << 32) | msr_low;
 		*value = (u64) msr;
 		ret = 0;
@@ -736,8 +726,7 @@ static int acpi_throttling_wrmsr(u64 value)
 
 	if ((this_cpu_read(cpu_info.x86_vendor) != X86_VENDOR_INTEL) ||
 		!this_cpu_has(X86_FEATURE_ACPI)) {
-		printk(KERN_ERR PREFIX
-			"HARDWARE addr space,NOT supported yet\n");
+		pr_err("HARDWARE addr space,NOT supported yet\n");
 	} else {
 		msr = value;
 		wrmsr_safe(MSR_IA32_THERM_CONTROL,
@@ -749,15 +738,13 @@ static int acpi_throttling_wrmsr(u64 value)
 #else
 static int acpi_throttling_rdmsr(u64 *value)
 {
-	printk(KERN_ERR PREFIX
-		"HARDWARE addr space,NOT supported yet\n");
+	pr_err("HARDWARE addr space,NOT supported yet\n");
 	return -1;
 }
 
 static int acpi_throttling_wrmsr(u64 value)
 {
-	printk(KERN_ERR PREFIX
-		"HARDWARE addr space,NOT supported yet\n");
+	pr_err("HARDWARE addr space,NOT supported yet\n");
 	return -1;
 }
 #endif
@@ -788,7 +775,7 @@ static int acpi_read_throttling_status(struct acpi_processor *pr,
 		ret = acpi_throttling_rdmsr(value);
 		break;
 	default:
-		printk(KERN_ERR PREFIX "Unknown addr space %d\n",
+		pr_err("Unknown addr space %d\n",
 		       (u32) (throttling->status_register.space_id));
 	}
 	return ret;
@@ -821,7 +808,7 @@ static int acpi_write_throttling_state(struct acpi_processor *pr,
 		ret = acpi_throttling_wrmsr(value);
 		break;
 	default:
-		printk(KERN_ERR PREFIX "Unknown addr space %d\n",
+		pr_err("Unknown addr space %d\n",
 		       (u32) (throttling->control_register.space_id));
 	}
 	return ret;
@@ -876,8 +863,8 @@ static int acpi_processor_get_throttling_ptc(struct acpi_processor *pr)
 	if (ret >= 0) {
 		state = acpi_get_throttling_state(pr, value);
 		if (state == -1) {
-			ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-				"Invalid throttling state, reset\n"));
+			acpi_handle_debug(pr->handle,
+					  "Invalid throttling state, reset\n");
 			state = 0;
 			ret = __acpi_processor_set_throttling(pr, state, true,
 							      true);
@@ -922,15 +909,15 @@ static int acpi_processor_get_fadt_info(struct acpi_processor *pr)
 	int i, step;
 
 	if (!pr->throttling.address) {
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No throttling register\n"));
+		acpi_handle_debug(pr->handle, "No throttling register\n");
 		return -EINVAL;
 	} else if (!pr->throttling.duty_width) {
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No throttling states\n"));
+		acpi_handle_debug(pr->handle, "No throttling states\n");
 		return -EINVAL;
 	}
 	/* TBD: Support duty_cycle values that span bit 4. */
 	else if ((pr->throttling.duty_offset + pr->throttling.duty_width) > 4) {
-		printk(KERN_WARNING PREFIX "duty_cycle spans bit 4\n");
+		pr_warn("duty_cycle spans bit 4\n");
 		return -EINVAL;
 	}
 
@@ -1016,10 +1003,10 @@ static int acpi_processor_set_throttling_fadt(struct acpi_processor *pr,
 
 	local_irq_enable();
 
-	ACPI_DEBUG_PRINT((ACPI_DB_INFO,
+	acpi_handle_debug(pr->handle,
 			  "Throttling state set to T%d (%d%%)\n", state,
 			  (pr->throttling.states[state].performance ? pr->
-			   throttling.states[state].performance / 10 : 0)));
+			   throttling.states[state].performance / 10 : 0));
 
 	return 0;
 }
@@ -1130,8 +1117,8 @@ static int __acpi_processor_set_throttling(struct acpi_processor *pr,
 			 * error message and continue.
 			 */
 			if (!match_pr) {
-				ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-					"Invalid Pointer for CPU %d\n", i));
+				acpi_handle_debug(pr->handle,
+					"Invalid Pointer for CPU %d\n", i);
 				continue;
 			}
 			/*
@@ -1139,9 +1126,8 @@ static int __acpi_processor_set_throttling(struct acpi_processor *pr,
 			 * we will report the error message and continue.
 			 */
 			if (!match_pr->flags.throttling) {
-				ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-					"Throttling Control is unsupported "
-					"on CPU %d\n", i));
+				acpi_handle_debug(pr->handle,
+					"Throttling Control unsupported on CPU %d\n", i);
 				continue;
 			}
 
@@ -1178,11 +1164,11 @@ int acpi_processor_get_throttling_info(struct acpi_processor *pr)
 	int result = 0;
 	struct acpi_processor_throttling *pthrottling;
 
-	ACPI_DEBUG_PRINT((ACPI_DB_INFO,
+	acpi_handle_debug(pr->handle,
 			  "pblk_address[0x%08x] duty_offset[%d] duty_width[%d]\n",
 			  pr->throttling.address,
 			  pr->throttling.duty_offset,
-			  pr->throttling.duty_width));
+			  pr->throttling.duty_width);
 
 	/*
 	 * Evaluate _PTC, _TSS and _TPC
@@ -1190,8 +1176,7 @@ int acpi_processor_get_throttling_info(struct acpi_processor *pr)
 	 */
 	if (acpi_processor_get_throttling_control(pr) ||
 		acpi_processor_get_throttling_states(pr) ||
-		acpi_processor_get_platform_limit(pr))
-	{
+		acpi_processor_get_platform_limit(pr)) {
 		pr->throttling.acpi_processor_get_throttling =
 		    &acpi_processor_get_throttling_fadt;
 		pr->throttling.acpi_processor_set_throttling =
@@ -1222,13 +1207,13 @@ int acpi_processor_get_throttling_info(struct acpi_processor *pr)
 	 * used this part.
 	 */
 	if (errata.piix4.throttle) {
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-				  "Throttling not supported on PIIX4 A- or B-step\n"));
+		acpi_handle_debug(pr->handle,
+				  "Throttling not supported on PIIX4 A- or B-step\n");
 		return 0;
 	}
 
-	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found %d throttling states\n",
-			  pr->throttling.state_count));
+	acpi_handle_debug(pr->handle, "Found %d throttling states\n",
+			  pr->throttling.state_count);
 
 	pr->flags.throttling = 1;
 
@@ -1243,15 +1228,15 @@ int acpi_processor_get_throttling_info(struct acpi_processor *pr)
 		goto end;
 
 	if (pr->throttling.state) {
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO,
+		acpi_handle_debug(pr->handle,
 				  "Disabling throttling (was T%d)\n",
-				  pr->throttling.state));
+				  pr->throttling.state);
 		result = acpi_processor_set_throttling(pr, 0, false);
 		if (result)
 			goto end;
 	}
 
-      end:
+end:
 	if (result)
 		pr->flags.throttling = 0;
 
diff --git a/drivers/acpi/property.c b/drivers/acpi/property.c
index e601c4511a8b..18e90067d567 100644
--- a/drivers/acpi/property.c
+++ b/drivers/acpi/property.c
@@ -2,14 +2,17 @@
 /*
  * ACPI device specific properties support.
  *
- * Copyright (C) 2014, Intel Corporation
+ * Copyright (C) 2014 - 2023, Intel Corporation
  * All rights reserved.
  *
  * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
  *          Darren Hart <dvhart@linux.intel.com>
  *          Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+ *          Sakari Ailus <sakari.ailus@linux.intel.com>
  */
 
+#define pr_fmt(fmt) "ACPI: " fmt
+
 #include <linux/acpi.h>
 #include <linux/device.h>
 #include <linux/export.h>
@@ -28,9 +31,14 @@ static int acpi_data_get_property_array(const struct acpi_device_data *data,
  * not defined without a warning. For instance if any of the properties
  * from different GUID appear in a property list of another, it will be
  * accepted by the kernel. Firmware validation tools should catch these.
+ *
+ * References:
+ *
+ * [1] UEFI DSD Guide.
+ *     https://github.com/UEFI/DSD-Guide/blob/main/src/dsd-guide.adoc
  */
 static const guid_t prp_guids[] = {
-	/* ACPI _DSD device properties GUID: daffd814-6eba-4d8c-8a91-bc9bbf4aa301 */
+	/* ACPI _DSD device properties GUID [1]: daffd814-6eba-4d8c-8a91-bc9bbf4aa301 */
 	GUID_INIT(0xdaffd814, 0x6eba, 0x4d8c,
 		  0x8a, 0x91, 0xbc, 0x9b, 0xbf, 0x4a, 0xa3, 0x01),
 	/* Hotplug in D3 GUID: 6211e2c0-58a3-4af3-90e1-927a4e0c55a4 */
@@ -45,92 +53,91 @@ static const guid_t prp_guids[] = {
 	/* Thunderbolt GUID for WAKE_SUPPORTED: 6c501103-c189-4296-ba72-9bf5a26ebe5d */
 	GUID_INIT(0x6c501103, 0xc189, 0x4296,
 		  0xba, 0x72, 0x9b, 0xf5, 0xa2, 0x6e, 0xbe, 0x5d),
+	/* Storage device needs D3 GUID: 5025030f-842f-4ab4-a561-99a5189762d0 */
+	GUID_INIT(0x5025030f, 0x842f, 0x4ab4,
+		  0xa5, 0x61, 0x99, 0xa5, 0x18, 0x97, 0x62, 0xd0),
 };
 
-/* ACPI _DSD data subnodes GUID: dbb8e3e6-5886-4ba6-8795-1319f52a966b */
+/* ACPI _DSD data subnodes GUID [1]: dbb8e3e6-5886-4ba6-8795-1319f52a966b */
 static const guid_t ads_guid =
 	GUID_INIT(0xdbb8e3e6, 0x5886, 0x4ba6,
 		  0x87, 0x95, 0x13, 0x19, 0xf5, 0x2a, 0x96, 0x6b);
 
+/* ACPI _DSD data buffer GUID [1]: edb12dd0-363d-4085-a3d2-49522ca160c4 */
+static const guid_t buffer_prop_guid =
+	GUID_INIT(0xedb12dd0, 0x363d, 0x4085,
+		  0xa3, 0xd2, 0x49, 0x52, 0x2c, 0xa1, 0x60, 0xc4);
+
 static bool acpi_enumerate_nondev_subnodes(acpi_handle scope,
-					   const union acpi_object *desc,
+					   union acpi_object *desc,
 					   struct acpi_device_data *data,
 					   struct fwnode_handle *parent);
-static bool acpi_extract_properties(const union acpi_object *desc,
+static bool acpi_extract_properties(acpi_handle handle,
+				    union acpi_object *desc,
 				    struct acpi_device_data *data);
 
-static bool acpi_nondev_subnode_extract(const union acpi_object *desc,
+static bool acpi_nondev_subnode_extract(union acpi_object *desc,
 					acpi_handle handle,
 					const union acpi_object *link,
 					struct list_head *list,
 					struct fwnode_handle *parent)
 {
 	struct acpi_data_node *dn;
+	acpi_handle scope = NULL;
 	bool result;
 
+	if (acpi_graph_ignore_port(handle))
+		return false;
+
 	dn = kzalloc(sizeof(*dn), GFP_KERNEL);
 	if (!dn)
 		return false;
 
 	dn->name = link->package.elements[0].string.pointer;
-	dn->fwnode.ops = &acpi_data_fwnode_ops;
+	fwnode_init(&dn->fwnode, &acpi_data_fwnode_ops);
 	dn->parent = parent;
 	INIT_LIST_HEAD(&dn->data.properties);
 	INIT_LIST_HEAD(&dn->data.subnodes);
 
-	result = acpi_extract_properties(desc, &dn->data);
-
-	if (handle) {
-		acpi_handle scope;
-		acpi_status status;
+	/*
+	 * The scope for the completion of relative pathname segments and
+	 * subnode object lookup is the one of the namespace node (device)
+	 * containing the object that has returned the package.  That is, it's
+	 * the scope of that object's parent device.
+	 */
+	if (handle)
+		acpi_get_parent(handle, &scope);
 
-		/*
-		 * The scope for the subnode object lookup is the one of the
-		 * namespace node (device) containing the object that has
-		 * returned the package.  That is, it's the scope of that
-		 * object's parent.
-		 */
-		status = acpi_get_parent(handle, &scope);
-		if (ACPI_SUCCESS(status)
-		    && acpi_enumerate_nondev_subnodes(scope, desc, &dn->data,
-						      &dn->fwnode))
-			result = true;
-	} else if (acpi_enumerate_nondev_subnodes(NULL, desc, &dn->data,
-						  &dn->fwnode)) {
+	/*
+	 * Extract properties from the _DSD-equivalent package pointed to by
+	 * desc and use scope (if not NULL) for the completion of relative
+	 * pathname segments.
+	 *
+	 * The extracted properties will be held in the new data node dn.
+	 */
+	result = acpi_extract_properties(scope, desc, &dn->data);
+	/*
+	 * Look for subnodes in the _DSD-equivalent package pointed to by desc
+	 * and create child nodes of dn if there are any.
+	 */
+	if (acpi_enumerate_nondev_subnodes(scope, desc, &dn->data, &dn->fwnode))
 		result = true;
-	}
-
-	if (result) {
-		dn->handle = handle;
-		dn->data.pointer = desc;
-		list_add_tail(&dn->sibling, list);
-		return true;
-	}
-
-	kfree(dn);
-	acpi_handle_debug(handle, "Invalid properties/subnodes data, skipping\n");
-	return false;
-}
 
-static bool acpi_nondev_subnode_data_ok(acpi_handle handle,
-					const union acpi_object *link,
-					struct list_head *list,
-					struct fwnode_handle *parent)
-{
-	struct acpi_buffer buf = { ACPI_ALLOCATE_BUFFER };
-	acpi_status status;
-
-	status = acpi_evaluate_object_typed(handle, NULL, NULL, &buf,
-					    ACPI_TYPE_PACKAGE);
-	if (ACPI_FAILURE(status))
+	if (!result) {
+		kfree(dn);
+		acpi_handle_debug(handle, "Invalid properties/subnodes data, skipping\n");
 		return false;
+	}
 
-	if (acpi_nondev_subnode_extract(buf.pointer, handle, link, list,
-					parent))
-		return true;
+	/*
+	 * This will be NULL if the desc package is embedded in an outer
+	 * _DSD-equivalent package and its scope cannot be determined.
+	 */
+	dn->handle = handle;
+	dn->data.pointer = desc;
+	list_add_tail(&dn->sibling, list);
 
-	ACPI_FREE(buf.pointer);
-	return false;
+	return true;
 }
 
 static bool acpi_nondev_subnode_ok(acpi_handle scope,
@@ -138,9 +145,16 @@ static bool acpi_nondev_subnode_ok(acpi_handle scope,
 				   struct list_head *list,
 				   struct fwnode_handle *parent)
 {
+	struct acpi_buffer buf = { ACPI_ALLOCATE_BUFFER };
 	acpi_handle handle;
 	acpi_status status;
 
+	/*
+	 * If the scope is unknown, the _DSD-equivalent package being parsed
+	 * was embedded in an outer _DSD-equivalent package as a result of
+	 * direct evaluation of an object pointed to by a reference.  In that
+	 * case, using a pathname as the target object pointer is invalid.
+	 */
 	if (!scope)
 		return false;
 
@@ -149,20 +163,33 @@ static bool acpi_nondev_subnode_ok(acpi_handle scope,
 	if (ACPI_FAILURE(status))
 		return false;
 
-	return acpi_nondev_subnode_data_ok(handle, link, list, parent);
+	status = acpi_evaluate_object_typed(handle, NULL, NULL, &buf,
+					    ACPI_TYPE_PACKAGE);
+	if (ACPI_FAILURE(status))
+		return false;
+
+	if (acpi_nondev_subnode_extract(buf.pointer, handle, link, list,
+					parent))
+		return true;
+
+	ACPI_FREE(buf.pointer);
+	return false;
 }
 
-static int acpi_add_nondev_subnodes(acpi_handle scope,
-				    const union acpi_object *links,
-				    struct list_head *list,
-				    struct fwnode_handle *parent)
+static bool acpi_add_nondev_subnodes(acpi_handle scope,
+				     union acpi_object *links,
+				     struct list_head *list,
+				     struct fwnode_handle *parent)
 {
 	bool ret = false;
 	int i;
 
+	/*
+	 * Every element in the links package is expected to represent a link
+	 * to a non-device node in a tree containing device-specific data.
+	 */
 	for (i = 0; i < links->package.count; i++) {
-		const union acpi_object *link, *desc;
-		acpi_handle handle;
+		union acpi_object *link, *desc;
 		bool result;
 
 		link = &links->package.elements[i];
@@ -170,26 +197,53 @@ static int acpi_add_nondev_subnodes(acpi_handle scope,
 		if (link->package.count != 2)
 			continue;
 
-		/* The first one must be a string. */
+		/* The first one (the key) must be a string. */
 		if (link->package.elements[0].type != ACPI_TYPE_STRING)
 			continue;
 
-		/* The second one may be a string, a reference or a package. */
+		/* The second one (the target) may be a string or a package. */
 		switch (link->package.elements[1].type) {
 		case ACPI_TYPE_STRING:
+			/*
+			 * The string is expected to be a full pathname or a
+			 * pathname segment relative to the given scope.  That
+			 * pathname is expected to point to an object returning
+			 * a package that contains _DSD-equivalent information.
+			 */
 			result = acpi_nondev_subnode_ok(scope, link, list,
 							 parent);
 			break;
-		case ACPI_TYPE_LOCAL_REFERENCE:
-			handle = link->package.elements[1].reference.handle;
-			result = acpi_nondev_subnode_data_ok(handle, link, list,
-							     parent);
-			break;
 		case ACPI_TYPE_PACKAGE:
+			/*
+			 * This happens when a reference is used in AML to
+			 * point to the target.  Since the target is expected
+			 * to be a named object, a reference to it will cause it
+			 * to be avaluated in place and its return package will
+			 * be embedded in the links package at the location of
+			 * the reference.
+			 *
+			 * The target package is expected to contain _DSD-
+			 * equivalent information, but the scope in which it
+			 * is located in the original AML is unknown.  Thus
+			 * it cannot contain pathname segments represented as
+			 * strings because there is no way to build full
+			 * pathnames out of them.
+			 */
+			acpi_handle_debug(scope, "subnode %s: Unknown scope\n",
+					  link->package.elements[0].string.pointer);
 			desc = &link->package.elements[1];
 			result = acpi_nondev_subnode_extract(desc, NULL, link,
 							     list, parent);
 			break;
+		case ACPI_TYPE_LOCAL_REFERENCE:
+			/*
+			 * It is not expected to see any local references in
+			 * the links package because referencing a named object
+			 * should cause it to be evaluated in place.
+			 */
+			acpi_handle_info(scope, "subnode %s: Unexpected reference\n",
+					 link->package.elements[0].string.pointer);
+			fallthrough;
 		default:
 			result = false;
 			break;
@@ -201,7 +255,7 @@ static int acpi_add_nondev_subnodes(acpi_handle scope,
 }
 
 static bool acpi_enumerate_nondev_subnodes(acpi_handle scope,
-					   const union acpi_object *desc,
+					   union acpi_object *desc,
 					   struct acpi_device_data *data,
 					   struct fwnode_handle *parent)
 {
@@ -209,7 +263,8 @@ static bool acpi_enumerate_nondev_subnodes(acpi_handle scope,
 
 	/* Look for the ACPI data subnodes GUID. */
 	for (i = 0; i < desc->package.count; i += 2) {
-		const union acpi_object *guid, *links;
+		const union acpi_object *guid;
+		union acpi_object *links;
 
 		guid = &desc->package.elements[i];
 		links = &desc->package.elements[i + 1];
@@ -295,8 +350,10 @@ static void acpi_init_of_compatible(struct acpi_device *adev)
 		ret = acpi_dev_get_property(adev, "compatible",
 					    ACPI_TYPE_STRING, &of_compatible);
 		if (ret) {
-			if (adev->parent
-			    && adev->parent->flags.of_compatible_ok)
+			struct acpi_device *parent;
+
+			parent = acpi_dev_parent(adev);
+			if (parent && parent->flags.of_compatible_ok)
 				goto out;
 
 			return;
@@ -322,7 +379,7 @@ static bool acpi_is_property_guid(const guid_t *guid)
 
 struct acpi_device_properties *
 acpi_data_add_props(struct acpi_device_data *data, const guid_t *guid,
-		    const union acpi_object *properties)
+		    union acpi_object *properties)
 {
 	struct acpi_device_properties *props;
 
@@ -337,7 +394,147 @@ acpi_data_add_props(struct acpi_device_data *data, const guid_t *guid,
 	return props;
 }
 
-static bool acpi_extract_properties(const union acpi_object *desc,
+static void acpi_nondev_subnode_tag(acpi_handle handle, void *context)
+{
+}
+
+static void acpi_untie_nondev_subnodes(struct acpi_device_data *data)
+{
+	struct acpi_data_node *dn;
+
+	list_for_each_entry(dn, &data->subnodes, sibling) {
+		if (!dn->handle)
+			continue;
+
+		acpi_detach_data(dn->handle, acpi_nondev_subnode_tag);
+
+		acpi_untie_nondev_subnodes(&dn->data);
+	}
+}
+
+static bool acpi_tie_nondev_subnodes(struct acpi_device_data *data)
+{
+	struct acpi_data_node *dn;
+
+	list_for_each_entry(dn, &data->subnodes, sibling) {
+		acpi_status status;
+		bool ret;
+
+		if (!dn->handle)
+			continue;
+
+		status = acpi_attach_data(dn->handle, acpi_nondev_subnode_tag, dn);
+		if (ACPI_FAILURE(status) && status != AE_ALREADY_EXISTS) {
+			acpi_handle_err(dn->handle, "Can't tag data node\n");
+			return false;
+		}
+
+		ret = acpi_tie_nondev_subnodes(&dn->data);
+		if (!ret)
+			return ret;
+	}
+
+	return true;
+}
+
+static void acpi_data_add_buffer_props(acpi_handle handle,
+				       struct acpi_device_data *data,
+				       union acpi_object *properties)
+{
+	struct acpi_device_properties *props;
+	union acpi_object *package;
+	size_t alloc_size;
+	unsigned int i;
+	u32 *count;
+
+	if (check_mul_overflow((size_t)properties->package.count,
+			       sizeof(*package) + sizeof(void *),
+			       &alloc_size) ||
+	    check_add_overflow(sizeof(*props) + sizeof(*package), alloc_size,
+			       &alloc_size)) {
+		acpi_handle_warn(handle,
+				 "can't allocate memory for %u buffer props",
+				 properties->package.count);
+		return;
+	}
+
+	props = kvzalloc(alloc_size, GFP_KERNEL);
+	if (!props)
+		return;
+
+	props->guid = &buffer_prop_guid;
+	props->bufs = (void *)(props + 1);
+	props->properties = (void *)(props->bufs + properties->package.count);
+
+	/* Outer package */
+	package = props->properties;
+	package->type = ACPI_TYPE_PACKAGE;
+	package->package.elements = package + 1;
+	count = &package->package.count;
+	*count = 0;
+
+	/* Inner packages */
+	package++;
+
+	for (i = 0; i < properties->package.count; i++) {
+		struct acpi_buffer buf = { ACPI_ALLOCATE_BUFFER };
+		union acpi_object *property = &properties->package.elements[i];
+		union acpi_object *prop, *obj, *buf_obj;
+		acpi_status status;
+
+		if (property->type != ACPI_TYPE_PACKAGE ||
+		    property->package.count != 2) {
+			acpi_handle_warn(handle,
+					 "buffer property %u has %u entries\n",
+					 i, property->package.count);
+			continue;
+		}
+
+		prop = &property->package.elements[0];
+		obj = &property->package.elements[1];
+
+		if (prop->type != ACPI_TYPE_STRING ||
+		    obj->type != ACPI_TYPE_STRING) {
+			acpi_handle_warn(handle,
+					 "wrong object types %u and %u\n",
+					 prop->type, obj->type);
+			continue;
+		}
+
+		status = acpi_evaluate_object_typed(handle, obj->string.pointer,
+						    NULL, &buf,
+						    ACPI_TYPE_BUFFER);
+		if (ACPI_FAILURE(status)) {
+			acpi_handle_warn(handle,
+					 "can't evaluate \"%*pE\" as buffer\n",
+					 obj->string.length,
+					 obj->string.pointer);
+			continue;
+		}
+
+		package->type = ACPI_TYPE_PACKAGE;
+		package->package.elements = prop;
+		package->package.count = 2;
+
+		buf_obj = buf.pointer;
+
+		/* Replace the string object with a buffer object */
+		obj->type = ACPI_TYPE_BUFFER;
+		obj->buffer.length = buf_obj->buffer.length;
+		obj->buffer.pointer = buf_obj->buffer.pointer;
+
+		props->bufs[i] = buf.pointer;
+		package++;
+		(*count)++;
+	}
+
+	if (*count)
+		list_add(&props->list, &data->properties);
+	else
+		kvfree(props);
+}
+
+static bool acpi_extract_properties(acpi_handle scope, union acpi_object *desc,
 				    struct acpi_device_data *data)
 {
 	int i;
@@ -347,7 +544,8 @@ static bool acpi_extract_properties(const union acpi_object *desc,
 
 	/* Look for the device properties GUID. */
 	for (i = 0; i < desc->package.count; i += 2) {
-		const union acpi_object *guid, *properties;
+		const union acpi_object *guid;
+		union acpi_object *properties;
 
 		guid = &desc->package.elements[i];
 		properties = &desc->package.elements[i + 1];
@@ -361,6 +559,12 @@ static bool acpi_extract_properties(const union acpi_object *desc,
 		    properties->type != ACPI_TYPE_PACKAGE)
 			break;
 
+		if (guid_equal((guid_t *)guid->buffer.pointer,
+			       &buffer_prop_guid)) {
+			acpi_data_add_buffer_props(scope, data, properties);
+			continue;
+		}
+
 		if (!acpi_is_property_guid((guid_t *)guid->buffer.pointer))
 			continue;
 
@@ -407,7 +611,7 @@ void acpi_init_properties(struct acpi_device *adev)
 	if (ACPI_FAILURE(status))
 		goto out;
 
-	if (acpi_extract_properties(buf.pointer, &adev->data)) {
+	if (acpi_extract_properties(adev->handle, buf.pointer, &adev->data)) {
 		adev->data.pointer = buf.pointer;
 		if (acpi_of)
 			acpi_init_of_compatible(adev);
@@ -419,6 +623,9 @@ void acpi_init_properties(struct acpi_device *adev)
 	if (!adev->data.pointer) {
 		acpi_handle_debug(adev->handle, "Invalid _DSD data, skipping\n");
 		ACPI_FREE(buf.pointer);
+	} else {
+		if (!acpi_tie_nondev_subnodes(&adev->data))
+			acpi_untie_nondev_subnodes(&adev->data);
 	}
 
  out:
@@ -430,6 +637,22 @@ void acpi_init_properties(struct acpi_device *adev)
 		acpi_extract_apple_properties(adev);
 }
 
+static void acpi_free_device_properties(struct list_head *list)
+{
+	struct acpi_device_properties *props, *tmp;
+
+	list_for_each_entry_safe(props, tmp, list, list) {
+		u32 i;
+
+		list_del(&props->list);
+		/* Buffer data properties were separately allocated */
+		if (props->bufs)
+			for (i = 0; i < props->properties->package.count; i++)
+				ACPI_FREE(props->bufs[i]);
+		kvfree(props);
+	}
+}
+
 static void acpi_destroy_nondev_subnodes(struct list_head *list)
 {
 	struct acpi_data_node *dn, *next;
@@ -442,22 +665,19 @@ static void acpi_destroy_nondev_subnodes(struct list_head *list)
 		wait_for_completion(&dn->kobj_done);
 		list_del(&dn->sibling);
 		ACPI_FREE((void *)dn->data.pointer);
+		acpi_free_device_properties(&dn->data.properties);
 		kfree(dn);
 	}
 }
 
 void acpi_free_properties(struct acpi_device *adev)
 {
-	struct acpi_device_properties *props, *tmp;
-
+	acpi_untie_nondev_subnodes(&adev->data);
 	acpi_destroy_nondev_subnodes(&adev->data.subnodes);
 	ACPI_FREE((void *)adev->data.pointer);
 	adev->data.of_compatible = NULL;
 	adev->data.pointer = NULL;
-	list_for_each_entry_safe(props, tmp, &adev->data.properties, list) {
-		list_del(&props->list);
-		kfree(props);
-	}
+	acpi_free_device_properties(&adev->data.properties);
 }
 
 /**
@@ -538,7 +758,8 @@ acpi_device_data_of_node(const struct fwnode_handle *fwnode)
 	if (is_acpi_device_node(fwnode)) {
 		const struct acpi_device *adev = to_acpi_device_node(fwnode);
 		return &adev->data;
-	} else if (is_acpi_data_node(fwnode)) {
+	}
+	if (is_acpi_data_node(fwnode)) {
 		const struct acpi_data_node *dn = to_acpi_data_node(fwnode);
 		return &dn->data;
 	}
@@ -561,7 +782,7 @@ int acpi_node_prop_get(const struct fwnode_handle *fwnode,
 
 /**
  * acpi_data_get_property_array - return an ACPI array property with given name
- * @adev: ACPI data object to get the property from
+ * @data: ACPI data object to get the property from
  * @name: Name of the property
  * @type: Expected type of array elements
  * @obj: Location to store a pointer to the property value (if not NULL)
@@ -606,13 +827,7 @@ static struct fwnode_handle *
 acpi_fwnode_get_named_child_node(const struct fwnode_handle *fwnode,
 				 const char *childname)
 {
-	char name[ACPI_PATH_SEGMENT_LENGTH];
 	struct fwnode_handle *child;
-	struct acpi_buffer path;
-	acpi_status status;
-
-	path.length = sizeof(name);
-	path.pointer = name;
 
 	fwnode_for_each_child_node(fwnode, child) {
 		if (is_acpi_data_node(child)) {
@@ -621,60 +836,123 @@ acpi_fwnode_get_named_child_node(const struct fwnode_handle *fwnode,
 			continue;
 		}
 
-		status = acpi_get_name(ACPI_HANDLE_FWNODE(child),
-				       ACPI_SINGLE_NAME, &path);
-		if (ACPI_FAILURE(status))
-			break;
-
-		if (!strncmp(name, childname, ACPI_NAMESEG_SIZE))
+		if (!strncmp(acpi_device_bid(to_acpi_device_node(child)),
+			     childname, ACPI_NAMESEG_SIZE))
 			return child;
 	}
 
 	return NULL;
 }
 
-/**
- * __acpi_node_get_property_reference - returns handle to the referenced object
- * @fwnode: Firmware node to get the property from
- * @propname: Name of the property
- * @index: Index of the reference to return
- * @num_args: Maximum number of arguments after each reference
- * @args: Location to store the returned reference with optional arguments
- *
- * Find property with @name, verifify that it is a package containing at least
- * one object reference and if so, store the ACPI device object pointer to the
- * target object in @args->adev.  If the reference includes arguments, store
- * them in the @args->args[] array.
- *
- * If there's more than one reference in the property value package, @index is
- * used to select the one to return.
- *
- * It is possible to leave holes in the property value set like in the
- * example below:
- *
- * Package () {
- *     "cs-gpios",
- *     Package () {
- *        ^GPIO, 19, 0, 0,
- *        ^GPIO, 20, 0, 0,
- *        0,
- *        ^GPIO, 21, 0, 0,
- *     }
- * }
- *
- * Calling this function with index %2 or index %3 return %-ENOENT. If the
- * property does not contain any more values %-ENOENT is returned. The NULL
- * entry must be single integer and preferably contain value %0.
- *
- * Return: %0 on success, negative error code on failure.
- */
-int __acpi_node_get_property_reference(const struct fwnode_handle *fwnode,
-	const char *propname, size_t index, size_t num_args,
-	struct fwnode_reference_args *args)
+static unsigned int acpi_fwnode_get_args_count(struct fwnode_handle *fwnode,
+					       const char *nargs_prop)
+{
+	const struct acpi_device_data *data;
+	const union acpi_object *obj;
+	int ret;
+
+	data = acpi_device_data_of_node(fwnode);
+	if (!data)
+		return 0;
+
+	ret = acpi_data_get_property(data, nargs_prop, ACPI_TYPE_INTEGER, &obj);
+	if (ret)
+		return 0;
+
+	return obj->integer.value;
+}
+
+static int acpi_get_ref_args(struct fwnode_reference_args *args,
+			     struct fwnode_handle *ref_fwnode,
+			     const char *nargs_prop,
+			     const union acpi_object **element,
+			     const union acpi_object *end, size_t num_args)
+{
+	u32 nargs = 0, i;
+
+	if (nargs_prop)
+		num_args = acpi_fwnode_get_args_count(ref_fwnode, nargs_prop);
+
+	/*
+	 * Assume the following integer elements are all args. Stop counting on
+	 * the first reference (possibly represented as a string) or end of the
+	 * package arguments. In case of neither reference, nor integer, return
+	 * an error, we can't parse it.
+	 */
+	for (i = 0; (*element) + i < end && i < num_args; i++) {
+		acpi_object_type type = (*element)[i].type;
+
+		if (type == ACPI_TYPE_LOCAL_REFERENCE || type == ACPI_TYPE_STRING)
+			break;
+
+		if (type == ACPI_TYPE_INTEGER)
+			nargs++;
+		else
+			return -EINVAL;
+	}
+
+	if (nargs > NR_FWNODE_REFERENCE_ARGS)
+		return -EINVAL;
+
+	if (args) {
+		args->fwnode = ref_fwnode;
+		args->nargs = nargs;
+		for (i = 0; i < nargs; i++)
+			args->args[i] = (*element)[i].integer.value;
+	}
+
+	(*element) += nargs;
+
+	return 0;
+}
+
+static struct fwnode_handle *acpi_parse_string_ref(const struct fwnode_handle *fwnode,
+						   const char *refstring)
+{
+	acpi_handle scope, handle;
+	struct acpi_data_node *dn;
+	struct acpi_device *device;
+	acpi_status status;
+
+	if (is_acpi_device_node(fwnode)) {
+		scope = to_acpi_device_node(fwnode)->handle;
+	} else if (is_acpi_data_node(fwnode)) {
+		scope = to_acpi_data_node(fwnode)->handle;
+	} else {
+		pr_debug("Bad node type for node %pfw\n", fwnode);
+		return NULL;
+	}
+
+	status = acpi_get_handle(scope, refstring, &handle);
+	if (ACPI_FAILURE(status)) {
+		acpi_handle_debug(scope, "Unable to get an ACPI handle for %s\n",
+				  refstring);
+		return NULL;
+	}
+
+	device = acpi_fetch_acpi_dev(handle);
+	if (device)
+		return acpi_fwnode_handle(device);
+
+	status = acpi_get_data_full(handle, acpi_nondev_subnode_tag,
+				    (void **)&dn, NULL);
+	if (ACPI_FAILURE(status) || !dn) {
+		acpi_handle_debug(handle, "Subnode not found\n");
+		return NULL;
+	}
+
+	return &dn->fwnode;
+}
+
+static int acpi_fwnode_get_reference_args(const struct fwnode_handle *fwnode,
+					  const char *propname, const char *nargs_prop,
+					  unsigned int args_count, unsigned int index,
+					  struct fwnode_reference_args *args)
 {
 	const union acpi_object *element, *end;
 	const union acpi_object *obj;
 	const struct acpi_device_data *data;
+	struct fwnode_handle *ref_fwnode;
 	struct acpi_device *device;
 	int ret, idx = 0;
 
@@ -686,34 +964,51 @@ int __acpi_node_get_property_reference(const struct fwnode_handle *fwnode,
 	if (ret)
 		return ret == -EINVAL ? -ENOENT : -EINVAL;
 
-	/*
-	 * The simplest case is when the value is a single reference.  Just
-	 * return that reference then.
-	 */
-	if (obj->type == ACPI_TYPE_LOCAL_REFERENCE) {
+	switch (obj->type) {
+	case ACPI_TYPE_LOCAL_REFERENCE:
+		/* Plain single reference without arguments. */
 		if (index)
+			return -ENOENT;
+
+		device = acpi_fetch_acpi_dev(obj->reference.handle);
+		if (!device)
 			return -EINVAL;
 
-		ret = acpi_bus_get_device(obj->reference.handle, &device);
-		if (ret)
-			return ret == -ENODEV ? -EINVAL : ret;
+		if (!args)
+			return 0;
 
 		args->fwnode = acpi_fwnode_handle(device);
 		args->nargs = 0;
+
 		return 0;
-	}
+	case ACPI_TYPE_STRING:
+		if (index)
+			return -ENOENT;
 
-	/*
-	 * If it is not a single reference, then it is a package of
-	 * references followed by number of ints as follows:
-	 *
-	 *  Package () { REF, INT, REF, INT, INT }
-	 *
-	 * The index argument is then used to determine which reference
-	 * the caller wants (along with the arguments).
-	 */
-	if (obj->type != ACPI_TYPE_PACKAGE)
+		ref_fwnode = acpi_parse_string_ref(fwnode, obj->string.pointer);
+		if (!ref_fwnode)
+			return -EINVAL;
+
+		args->fwnode = ref_fwnode;
+		args->nargs = 0;
+
+		return 0;
+	case ACPI_TYPE_PACKAGE:
+		/*
+		 * If it is not a single reference, then it is a package of
+		 * references, followed by number of ints as follows:
+		 *
+		 *  Package () { REF, INT, REF, INT, INT }
+		 *
+		 * Here, REF may be either a local reference or a string. The
+		 * index argument is then used to determine which reference the
+		 * caller wants (along with the arguments).
+		 */
+		break;
+	default:
 		return -EINVAL;
+	}
+
 	if (index >= obj->package.count)
 		return -ENOENT;
 
@@ -721,62 +1016,47 @@ int __acpi_node_get_property_reference(const struct fwnode_handle *fwnode,
 	end = element + obj->package.count;
 
 	while (element < end) {
-		u32 nargs, i;
-
-		if (element->type == ACPI_TYPE_LOCAL_REFERENCE) {
-			struct fwnode_handle *ref_fwnode;
-
-			ret = acpi_bus_get_device(element->reference.handle,
-						  &device);
-			if (ret)
+		switch (element->type) {
+		case ACPI_TYPE_LOCAL_REFERENCE:
+			device = acpi_fetch_acpi_dev(element->reference.handle);
+			if (!device)
 				return -EINVAL;
 
-			nargs = 0;
 			element++;
+			ret = acpi_get_ref_args(idx == index ? args : NULL,
+						acpi_fwnode_handle(device),
+						nargs_prop, &element, end,
+						args_count);
+			if (ret < 0)
+				return ret;
 
-			/*
-			 * Find the referred data extension node under the
-			 * referred device node.
-			 */
-			for (ref_fwnode = acpi_fwnode_handle(device);
-			     element < end && element->type == ACPI_TYPE_STRING;
-			     element++) {
-				ref_fwnode = acpi_fwnode_get_named_child_node(
-					ref_fwnode, element->string.pointer);
-				if (!ref_fwnode)
-					return -EINVAL;
-			}
-
-			/* assume following integer elements are all args */
-			for (i = 0; element + i < end && i < num_args; i++) {
-				int type = element[i].type;
-
-				if (type == ACPI_TYPE_INTEGER)
-					nargs++;
-				else if (type == ACPI_TYPE_LOCAL_REFERENCE)
-					break;
-				else
-					return -EINVAL;
-			}
+			if (idx == index)
+				return 0;
 
-			if (nargs > NR_FWNODE_REFERENCE_ARGS)
+			break;
+		case ACPI_TYPE_STRING:
+			ref_fwnode = acpi_parse_string_ref(fwnode,
+							   element->string.pointer);
+			if (!ref_fwnode)
 				return -EINVAL;
 
-			if (idx == index) {
-				args->fwnode = ref_fwnode;
-				args->nargs = nargs;
-				for (i = 0; i < nargs; i++)
-					args->args[i] = element[i].integer.value;
+			element++;
+			ret = acpi_get_ref_args(idx == index ? args : NULL,
+						ref_fwnode, nargs_prop, &element, end,
+						args_count);
+			if (ret < 0)
+				return ret;
 
+			if (idx == index)
 				return 0;
-			}
 
-			element += nargs;
-		} else if (element->type == ACPI_TYPE_INTEGER) {
+			break;
+		case ACPI_TYPE_INTEGER:
 			if (idx == index)
 				return -ENOENT;
 			element++;
-		} else {
+			break;
+		default:
 			return -EINVAL;
 		}
 
@@ -785,6 +1065,50 @@ int __acpi_node_get_property_reference(const struct fwnode_handle *fwnode,
 
 	return -ENOENT;
 }
+
+/**
+ * __acpi_node_get_property_reference - returns handle to the referenced object
+ * @fwnode: Firmware node to get the property from
+ * @propname: Name of the property
+ * @index: Index of the reference to return
+ * @num_args: Maximum number of arguments after each reference
+ * @args: Location to store the returned reference with optional arguments
+ *	  (may be NULL)
+ *
+ * Find property with @name, verifify that it is a package containing at least
+ * one object reference and if so, store the ACPI device object pointer to the
+ * target object in @args->adev.  If the reference includes arguments, store
+ * them in the @args->args[] array.
+ *
+ * If there's more than one reference in the property value package, @index is
+ * used to select the one to return.
+ *
+ * It is possible to leave holes in the property value set like in the
+ * example below:
+ *
+ * Package () {
+ *     "cs-gpios",
+ *     Package () {
+ *        ^GPIO, 19, 0, 0,
+ *        ^GPIO, 20, 0, 0,
+ *        0,
+ *        ^GPIO, 21, 0, 0,
+ *     }
+ * }
+ *
+ * Calling this function with index %2 or index %3 return %-ENOENT. If the
+ * property does not contain any more values %-ENOENT is returned. The NULL
+ * entry must be single integer and preferably contain value %0.
+ *
+ * Return: %0 on success, negative error code on failure.
+ */
+int __acpi_node_get_property_reference(const struct fwnode_handle *fwnode,
+				       const char *propname, size_t index,
+				       size_t num_args,
+				       struct fwnode_reference_args *args)
+{
+	return acpi_fwnode_get_reference_args(fwnode, propname, NULL, num_args, index, args);
+}
 EXPORT_SYMBOL_GPL(__acpi_node_get_property_reference);
 
 static int acpi_data_prop_read_single(const struct acpi_device_data *data,
@@ -792,125 +1116,80 @@ static int acpi_data_prop_read_single(const struct acpi_device_data *data,
 				      enum dev_prop_type proptype, void *val)
 {
 	const union acpi_object *obj;
-	int ret;
-
-	if (!val)
-		return -EINVAL;
+	int ret = 0;
 
-	if (proptype >= DEV_PROP_U8 && proptype <= DEV_PROP_U64) {
+	if (proptype >= DEV_PROP_U8 && proptype <= DEV_PROP_U64)
 		ret = acpi_data_get_property(data, propname, ACPI_TYPE_INTEGER, &obj);
-		if (ret)
-			return ret;
+	else if (proptype == DEV_PROP_STRING)
+		ret = acpi_data_get_property(data, propname, ACPI_TYPE_STRING, &obj);
+	if (ret)
+		return ret;
 
-		switch (proptype) {
-		case DEV_PROP_U8:
-			if (obj->integer.value > U8_MAX)
-				return -EOVERFLOW;
+	switch (proptype) {
+	case DEV_PROP_U8:
+		if (obj->integer.value > U8_MAX)
+			return -EOVERFLOW;
+		if (val)
 			*(u8 *)val = obj->integer.value;
-			break;
-		case DEV_PROP_U16:
-			if (obj->integer.value > U16_MAX)
-				return -EOVERFLOW;
+		break;
+	case DEV_PROP_U16:
+		if (obj->integer.value > U16_MAX)
+			return -EOVERFLOW;
+		if (val)
 			*(u16 *)val = obj->integer.value;
-			break;
-		case DEV_PROP_U32:
-			if (obj->integer.value > U32_MAX)
-				return -EOVERFLOW;
+		break;
+	case DEV_PROP_U32:
+		if (obj->integer.value > U32_MAX)
+			return -EOVERFLOW;
+		if (val)
 			*(u32 *)val = obj->integer.value;
-			break;
-		default:
+		break;
+	case DEV_PROP_U64:
+		if (val)
 			*(u64 *)val = obj->integer.value;
-			break;
-		}
-	} else if (proptype == DEV_PROP_STRING) {
-		ret = acpi_data_get_property(data, propname, ACPI_TYPE_STRING, &obj);
-		if (ret)
-			return ret;
-
-		*(char **)val = obj->string.pointer;
-
+		break;
+	case DEV_PROP_STRING:
+		if (val)
+			*(char **)val = obj->string.pointer;
 		return 1;
-	} else {
-		ret = -EINVAL;
-	}
-	return ret;
-}
-
-int acpi_dev_prop_read_single(struct acpi_device *adev, const char *propname,
-			      enum dev_prop_type proptype, void *val)
-{
-	int ret;
-
-	if (!adev)
+	default:
 		return -EINVAL;
-
-	ret = acpi_data_prop_read_single(&adev->data, propname, proptype, val);
-	if (ret < 0 || proptype != ACPI_TYPE_STRING)
-		return ret;
-	return 0;
-}
-
-static int acpi_copy_property_array_u8(const union acpi_object *items, u8 *val,
-				       size_t nval)
-{
-	int i;
-
-	for (i = 0; i < nval; i++) {
-		if (items[i].type != ACPI_TYPE_INTEGER)
-			return -EPROTO;
-		if (items[i].integer.value > U8_MAX)
-			return -EOVERFLOW;
-
-		val[i] = items[i].integer.value;
-	}
-	return 0;
-}
-
-static int acpi_copy_property_array_u16(const union acpi_object *items,
-					u16 *val, size_t nval)
-{
-	int i;
-
-	for (i = 0; i < nval; i++) {
-		if (items[i].type != ACPI_TYPE_INTEGER)
-			return -EPROTO;
-		if (items[i].integer.value > U16_MAX)
-			return -EOVERFLOW;
-
-		val[i] = items[i].integer.value;
 	}
-	return 0;
-}
-
-static int acpi_copy_property_array_u32(const union acpi_object *items,
-					u32 *val, size_t nval)
-{
-	int i;
-
-	for (i = 0; i < nval; i++) {
-		if (items[i].type != ACPI_TYPE_INTEGER)
-			return -EPROTO;
-		if (items[i].integer.value > U32_MAX)
-			return -EOVERFLOW;
 
-		val[i] = items[i].integer.value;
-	}
-	return 0;
+	/* When no storage provided return number of available values */
+	return val ? 0 : 1;
 }
 
-static int acpi_copy_property_array_u64(const union acpi_object *items,
-					u64 *val, size_t nval)
-{
-	int i;
-
-	for (i = 0; i < nval; i++) {
-		if (items[i].type != ACPI_TYPE_INTEGER)
-			return -EPROTO;
-
-		val[i] = items[i].integer.value;
-	}
-	return 0;
-}
+#define acpi_copy_property_array_uint(items, val, nval)			\
+	({								\
+		typeof(items) __items = items;				\
+		typeof(val) __val = val;				\
+		typeof(nval) __nval = nval;				\
+		size_t i;						\
+		int ret = 0;						\
+									\
+		for (i = 0; i < __nval; i++) {				\
+			if (__items->type == ACPI_TYPE_BUFFER) {	\
+				__val[i] = __items->buffer.pointer[i];	\
+				continue;				\
+			}						\
+			if (__items[i].type != ACPI_TYPE_INTEGER) {	\
+				ret = -EPROTO;				\
+				break;					\
+			}						\
+			if (__items[i].integer.value > _Generic(__val,	\
+								u8 *: U8_MAX, \
+								u16 *: U16_MAX, \
+								u32 *: U32_MAX, \
+								u64 *: U64_MAX)) { \
+				ret = -EOVERFLOW;			\
+				break;					\
+			}						\
+									\
+			__val[i] = __items[i].integer.value;		\
+		}							\
+		ret;							\
+	})
 
 static int acpi_copy_property_array_string(const union acpi_object *items,
 					   char **val, size_t nval)
@@ -935,43 +1214,77 @@ static int acpi_data_prop_read(const struct acpi_device_data *data,
 	const union acpi_object *items;
 	int ret;
 
-	if (val && nval == 1) {
+	if (nval == 1 || !val) {
 		ret = acpi_data_prop_read_single(data, propname, proptype, val);
-		if (ret >= 0)
+		/*
+		 * The overflow error means that the property is there and it is
+		 * single-value, but its type does not match, so return.
+		 */
+		if (ret >= 0 || ret == -EOVERFLOW)
 			return ret;
+
+		/*
+		 * Reading this property as a single-value one failed, but its
+		 * value may still be represented as one-element array, so
+		 * continue.
+		 */
 	}
 
 	ret = acpi_data_get_property_array(data, propname, ACPI_TYPE_ANY, &obj);
+	if (ret && proptype >= DEV_PROP_U8 && proptype <= DEV_PROP_U64)
+		ret = acpi_data_get_property(data, propname, ACPI_TYPE_BUFFER,
+					     &obj);
 	if (ret)
 		return ret;
 
-	if (!val)
+	if (!val) {
+		if (obj->type == ACPI_TYPE_BUFFER)
+			return obj->buffer.length;
+
 		return obj->package.count;
+	}
 
-	if (proptype != DEV_PROP_STRING && nval > obj->package.count)
-		return -EOVERFLOW;
-	else if (nval <= 0)
-		return -EINVAL;
+	switch (proptype) {
+	case DEV_PROP_STRING:
+		break;
+	default:
+		if (obj->type == ACPI_TYPE_BUFFER) {
+			if (nval > obj->buffer.length)
+				return -EOVERFLOW;
+		} else {
+			if (nval > obj->package.count)
+				return -EOVERFLOW;
+		}
+		break;
+	}
 
-	items = obj->package.elements;
+	if (obj->type == ACPI_TYPE_BUFFER) {
+		if (proptype != DEV_PROP_U8)
+			return -EPROTO;
+		items = obj;
+	} else {
+		items = obj->package.elements;
+	}
 
 	switch (proptype) {
 	case DEV_PROP_U8:
-		ret = acpi_copy_property_array_u8(items, (u8 *)val, nval);
+		ret = acpi_copy_property_array_uint(items, (u8 *)val, nval);
 		break;
 	case DEV_PROP_U16:
-		ret = acpi_copy_property_array_u16(items, (u16 *)val, nval);
+		ret = acpi_copy_property_array_uint(items, (u16 *)val, nval);
 		break;
 	case DEV_PROP_U32:
-		ret = acpi_copy_property_array_u32(items, (u32 *)val, nval);
+		ret = acpi_copy_property_array_uint(items, (u32 *)val, nval);
 		break;
 	case DEV_PROP_U64:
-		ret = acpi_copy_property_array_u64(items, (u64 *)val, nval);
+		ret = acpi_copy_property_array_uint(items, (u64 *)val, nval);
 		break;
 	case DEV_PROP_STRING:
-		ret = acpi_copy_property_array_string(
-			items, (char **)val,
-			min_t(u32, nval, obj->package.count));
+		nval = min(nval, obj->package.count);
+		if (nval == 0)
+			return -ENODATA;
+
+		ret = acpi_copy_property_array_string(items, (char **)val, nval);
 		break;
 	default:
 		ret = -EINVAL;
@@ -980,12 +1293,6 @@ static int acpi_data_prop_read(const struct acpi_device_data *data,
 	return ret;
 }
 
-int acpi_dev_prop_read(const struct acpi_device *adev, const char *propname,
-		       enum dev_prop_type proptype, void *val, size_t nval)
-{
-	return adev ? acpi_data_prop_read(&adev->data, propname, proptype, val, nval) : -EINVAL;
-}
-
 /**
  * acpi_node_prop_read - retrieve the value of an ACPI property with given name.
  * @fwnode: Firmware node to get the property from.
@@ -998,55 +1305,55 @@ int acpi_dev_prop_read(const struct acpi_device *adev, const char *propname,
  * of the property.  Otherwise, read at most @nval values to the array at the
  * location pointed to by @val.
  */
-int acpi_node_prop_read(const struct fwnode_handle *fwnode,
-			const char *propname, enum dev_prop_type proptype,
-			void *val, size_t nval)
+static int acpi_node_prop_read(const struct fwnode_handle *fwnode,
+			       const char *propname, enum dev_prop_type proptype,
+			       void *val, size_t nval)
 {
 	return acpi_data_prop_read(acpi_device_data_of_node(fwnode),
 				   propname, proptype, val, nval);
 }
 
-/**
+static int stop_on_next(struct acpi_device *adev, void *data)
+{
+	struct acpi_device **ret_p = data;
+
+	if (!*ret_p) {
+		*ret_p = adev;
+		return 1;
+	}
+
+	/* Skip until the "previous" object is found. */
+	if (*ret_p == adev)
+		*ret_p = NULL;
+
+	return 0;
+}
+
+/*
  * acpi_get_next_subnode - Return the next child node handle for a fwnode
  * @fwnode: Firmware node to find the next child node for.
  * @child: Handle to one of the device's child nodes or a null handle.
  */
-struct fwnode_handle *acpi_get_next_subnode(const struct fwnode_handle *fwnode,
-					    struct fwnode_handle *child)
+static struct fwnode_handle *
+acpi_get_next_subnode(const struct fwnode_handle *fwnode,
+		      struct fwnode_handle *child)
 {
-	const struct acpi_device *adev = to_acpi_device_node(fwnode);
-	const struct list_head *head;
-	struct list_head *next;
-
-	if (!child || is_acpi_device_node(child)) {
-		struct acpi_device *child_adev;
+	struct acpi_device *adev = to_acpi_device_node(fwnode);
 
-		if (adev)
-			head = &adev->children;
-		else
-			goto nondev;
+	if ((!child || is_acpi_device_node(child)) && adev) {
+		struct acpi_device *child_adev = to_acpi_device_node(child);
 
-		if (list_empty(head))
-			goto nondev;
+		acpi_dev_for_each_child(adev, stop_on_next, &child_adev);
+		if (child_adev)
+			return acpi_fwnode_handle(child_adev);
 
-		if (child) {
-			adev = to_acpi_device_node(child);
-			next = adev->node.next;
-			if (next == head) {
-				child = NULL;
-				goto nondev;
-			}
-			child_adev = list_entry(next, struct acpi_device, node);
-		} else {
-			child_adev = list_first_entry(head, struct acpi_device,
-						      node);
-		}
-		return acpi_fwnode_handle(child_adev);
+		child = NULL;
 	}
 
- nondev:
 	if (!child || is_acpi_data_node(child)) {
 		const struct acpi_data_node *data = to_acpi_data_node(fwnode);
+		const struct list_head *head;
+		struct list_head *next;
 		struct acpi_data_node *dn;
 
 		/*
@@ -1082,6 +1389,28 @@ struct fwnode_handle *acpi_get_next_subnode(const struct fwnode_handle *fwnode,
 	return NULL;
 }
 
+/*
+ * acpi_get_next_present_subnode - Return the next present child node handle
+ * @fwnode: Firmware node to find the next child node for.
+ * @child: Handle to one of the device's child nodes or a null handle.
+ *
+ * Like acpi_get_next_subnode(), but the device nodes returned by
+ * acpi_get_next_present_subnode() are guaranteed to be present.
+ *
+ * Returns: The fwnode handle of the next present sub-node.
+ */
+static struct fwnode_handle *
+acpi_get_next_present_subnode(const struct fwnode_handle *fwnode,
+			      struct fwnode_handle *child)
+{
+	do {
+		child = acpi_get_next_subnode(fwnode, child);
+	} while (is_acpi_device_node(child) &&
+		 !acpi_device_is_present(to_acpi_device_node(child)));
+
+	return child;
+}
+
 /**
  * acpi_node_get_parent - Return parent fwnode of this fwnode
  * @fwnode: Firmware node whose parent to get
@@ -1089,21 +1418,19 @@ struct fwnode_handle *acpi_get_next_subnode(const struct fwnode_handle *fwnode,
  * Returns parent node of an ACPI device or data firmware node or %NULL if
  * not available.
  */
-struct fwnode_handle *acpi_node_get_parent(const struct fwnode_handle *fwnode)
+static struct fwnode_handle *
+acpi_node_get_parent(const struct fwnode_handle *fwnode)
 {
 	if (is_acpi_data_node(fwnode)) {
 		/* All data nodes have parent pointer so just return that */
 		return to_acpi_data_node(fwnode)->parent;
-	} else if (is_acpi_device_node(fwnode)) {
-		acpi_handle handle, parent_handle;
-
-		handle = to_acpi_device_node(fwnode)->handle;
-		if (ACPI_SUCCESS(acpi_get_parent(handle, &parent_handle))) {
-			struct acpi_device *adev;
+	}
+	if (is_acpi_device_node(fwnode)) {
+		struct acpi_device *parent;
 
-			if (!acpi_bus_get_device(parent_handle, &adev))
-				return acpi_fwnode_handle(adev);
-		}
+		parent = acpi_dev_parent(to_acpi_device_node(fwnode));
+		if (parent)
+			return acpi_fwnode_handle(parent);
 	}
 
 	return NULL;
@@ -1146,7 +1473,7 @@ static struct fwnode_handle *acpi_graph_get_next_endpoint(
 
 	if (!prev) {
 		do {
-			port = fwnode_get_next_child_node(fwnode, port);
+			port = acpi_get_next_subnode(fwnode, port);
 			/*
 			 * The names of the port nodes begin with "port@"
 			 * followed by the number of the port node and they also
@@ -1164,14 +1491,17 @@ static struct fwnode_handle *acpi_graph_get_next_endpoint(
 	if (!port)
 		return NULL;
 
-	endpoint = fwnode_get_next_child_node(port, prev);
-	while (!endpoint) {
-		port = fwnode_get_next_child_node(fwnode, port);
-		if (!port)
+	do {
+		endpoint = acpi_get_next_subnode(port, prev);
+		if (endpoint)
 			break;
-		if (is_acpi_graph_node(port, "port"))
-			endpoint = fwnode_get_next_child_node(port, NULL);
-	}
+
+		prev = NULL;
+
+		do {
+			port = acpi_get_next_subnode(fwnode, port);
+		} while (port && !is_acpi_graph_node(port, "port"));
+	} while (port);
 
 	/*
 	 * The names of the endpoint nodes begin with "endpoint@" followed by
@@ -1217,8 +1547,7 @@ static struct fwnode_handle *acpi_graph_get_child_prop_value(
 
 /**
  * acpi_graph_get_remote_endpoint - Parses and returns remote end of an endpoint
- * @fwnode: Endpoint firmware node pointing to a remote device
- * @endpoint: Firmware node of remote endpoint is filled here if not %NULL
+ * @__fwnode: Endpoint firmware node pointing to a remote device
  *
  * Returns the remote endpoint corresponding to @__fwnode. NULL on error.
  */
@@ -1259,11 +1588,29 @@ acpi_graph_get_remote_endpoint(const struct fwnode_handle *__fwnode)
 static bool acpi_fwnode_device_is_available(const struct fwnode_handle *fwnode)
 {
 	if (!is_acpi_device_node(fwnode))
-		return false;
+		return true;
 
 	return acpi_device_is_present(to_acpi_device_node(fwnode));
 }
 
+static const void *
+acpi_fwnode_device_get_match_data(const struct fwnode_handle *fwnode,
+				  const struct device *dev)
+{
+	return acpi_device_get_match_data(dev);
+}
+
+static bool acpi_fwnode_device_dma_supported(const struct fwnode_handle *fwnode)
+{
+	return acpi_dma_supported(to_acpi_device_node(fwnode));
+}
+
+static enum dev_dma_attr
+acpi_fwnode_device_get_dma_attr(const struct fwnode_handle *fwnode)
+{
+	return acpi_get_dma_attr(to_acpi_device_node(fwnode));
+}
+
 static bool acpi_fwnode_property_present(const struct fwnode_handle *fwnode,
 					 const char *propname)
 {
@@ -1307,16 +1654,6 @@ acpi_fwnode_property_read_string_array(const struct fwnode_handle *fwnode,
 				   val, nval);
 }
 
-static int
-acpi_fwnode_get_reference_args(const struct fwnode_handle *fwnode,
-			       const char *prop, const char *nargs_prop,
-			       unsigned int args_count, unsigned int index,
-			       struct fwnode_reference_args *args)
-{
-	return __acpi_node_get_property_reference(fwnode, prop, index,
-						  args_count, args);
-}
-
 static const char *acpi_fwnode_get_name(const struct fwnode_handle *fwnode)
 {
 	const struct acpi_device *adev;
@@ -1381,27 +1718,38 @@ static int acpi_fwnode_graph_parse_endpoint(const struct fwnode_handle *fwnode,
 	if (fwnode_property_read_u32(fwnode, "reg", &endpoint->id))
 		fwnode_property_read_u32(fwnode, "endpoint", &endpoint->id);
 
+	fwnode_handle_put(port_fwnode);
 	return 0;
 }
 
-static const void *
-acpi_fwnode_device_get_match_data(const struct fwnode_handle *fwnode,
-				  const struct device *dev)
+static int acpi_fwnode_irq_get(const struct fwnode_handle *fwnode,
+			       unsigned int index)
 {
-	return acpi_device_get_match_data(dev);
+	struct resource res;
+	int ret;
+
+	ret = acpi_irq_get(ACPI_HANDLE_FWNODE(fwnode), index, &res);
+	if (ret)
+		return ret;
+
+	return res.start;
 }
 
 #define DECLARE_ACPI_FWNODE_OPS(ops) \
 	const struct fwnode_operations ops = {				\
 		.device_is_available = acpi_fwnode_device_is_available, \
 		.device_get_match_data = acpi_fwnode_device_get_match_data, \
+		.device_dma_supported =				\
+			acpi_fwnode_device_dma_supported,		\
+		.device_get_dma_attr = acpi_fwnode_device_get_dma_attr,	\
 		.property_present = acpi_fwnode_property_present,	\
+		.property_read_bool = acpi_fwnode_property_present,	\
 		.property_read_int_array =				\
 			acpi_fwnode_property_read_int_array,		\
 		.property_read_string_array =				\
 			acpi_fwnode_property_read_string_array,		\
 		.get_parent = acpi_node_get_parent,			\
-		.get_next_child_node = acpi_get_next_subnode,		\
+		.get_next_child_node = acpi_get_next_present_subnode,	\
 		.get_named_child_node = acpi_fwnode_get_named_child_node, \
 		.get_name = acpi_fwnode_get_name,			\
 		.get_name_prefix = acpi_fwnode_get_name_prefix,		\
@@ -1412,6 +1760,7 @@ acpi_fwnode_device_get_match_data(const struct fwnode_handle *fwnode,
 			acpi_graph_get_remote_endpoint,			\
 		.graph_get_port_parent = acpi_fwnode_get_parent,	\
 		.graph_parse_endpoint = acpi_fwnode_graph_parse_endpoint, \
+		.irq_get = acpi_fwnode_irq_get,				\
 	};								\
 	EXPORT_SYMBOL_GPL(ops)
 
diff --git a/drivers/acpi/reboot.c b/drivers/acpi/reboot.c
index ca707f5b521d..b79b7c99c237 100644
--- a/drivers/acpi/reboot.c
+++ b/drivers/acpi/reboot.c
@@ -1,8 +1,11 @@
 // SPDX-License-Identifier: GPL-2.0
 
+#define pr_fmt(fmt) "ACPI: " fmt
+
 #include <linux/pci.h>
 #include <linux/acpi.h>
 #include <acpi/reboot.h>
+#include <linux/delay.h>
 
 #ifdef CONFIG_PCI
 static void acpi_pci_reboot(struct acpi_generic_address *rr, u8 reset_value)
@@ -62,8 +65,18 @@ void acpi_reboot(void)
 
 	case ACPI_ADR_SPACE_SYSTEM_MEMORY:
 	case ACPI_ADR_SPACE_SYSTEM_IO:
-		printk(KERN_DEBUG "ACPI MEMORY or I/O RESET_REG.\n");
+		pr_debug("ACPI MEMORY or I/O RESET_REG.\n");
 		acpi_reset();
 		break;
 	}
+
+	/*
+	 * Some platforms do not shut down immediately after writing to the
+	 * ACPI reset register, and this results in racing with the
+	 * subsequent reboot mechanism.
+	 *
+	 * The 15ms delay has been found to be long enough for the system
+	 * to reboot on the affected platforms.
+	 */
+	mdelay(15);
 }
diff --git a/drivers/acpi/resource.c b/drivers/acpi/resource.c
index 3b4448972374..d16906f46484 100644
--- a/drivers/acpi/resource.c
+++ b/drivers/acpi/resource.c
@@ -16,6 +16,8 @@
 #include <linux/ioport.h>
 #include <linux/slab.h>
 #include <linux/irq.h>
+#include <linux/dmi.h>
+#include <linux/string_choices.h>
 
 #ifdef CONFIG_X86
 #define valid_IRQ(i) (((i) != 0) && ((i) != 2))
@@ -249,6 +251,9 @@ static bool acpi_decode_space(struct resource_win *win,
 	switch (addr->resource_type) {
 	case ACPI_MEMORY_RANGE:
 		acpi_dev_memresource_flags(res, len, wp);
+
+		if (addr->info.mem.caching == ACPI_PREFETCHABLE_MEMORY)
+			res->flags |= IORESOURCE_PREFETCH;
 		break;
 	case ACPI_IO_RANGE:
 		acpi_dev_ioresource_flags(res, len, iodec,
@@ -264,9 +269,6 @@ static bool acpi_decode_space(struct resource_win *win,
 	if (addr->producer_consumer == ACPI_PRODUCER)
 		res->flags |= IORESOURCE_WINDOW;
 
-	if (addr->info.mem.caching == ACPI_PREFETCHABLE_MEMORY)
-		res->flags |= IORESOURCE_PREFETCH;
-
 	return !(res->flags & IORESOURCE_DISABLED);
 }
 
@@ -335,8 +337,9 @@ EXPORT_SYMBOL_GPL(acpi_dev_resource_ext_address_space);
  * @triggering: Triggering type as provided by ACPI.
  * @polarity: Interrupt polarity as provided by ACPI.
  * @shareable: Whether or not the interrupt is shareable.
+ * @wake_capable: Wake capability as provided by ACPI.
  */
-unsigned long acpi_dev_irq_flags(u8 triggering, u8 polarity, u8 shareable)
+unsigned long acpi_dev_irq_flags(u8 triggering, u8 polarity, u8 shareable, u8 wake_capable)
 {
 	unsigned long flags;
 
@@ -350,6 +353,9 @@ unsigned long acpi_dev_irq_flags(u8 triggering, u8 polarity, u8 shareable)
 	if (shareable == ACPI_SHARED)
 		flags |= IORESOURCE_IRQ_SHAREABLE;
 
+	if (wake_capable == ACPI_WAKE_CAPABLE)
+		flags |= IORESOURCE_IRQ_WAKECAPABLE;
+
 	return flags | IORESOURCE_IRQ;
 }
 EXPORT_SYMBOL_GPL(acpi_dev_irq_flags);
@@ -373,28 +379,385 @@ unsigned int acpi_dev_get_irq_type(int triggering, int polarity)
 	case ACPI_ACTIVE_BOTH:
 		if (triggering == ACPI_EDGE_SENSITIVE)
 			return IRQ_TYPE_EDGE_BOTH;
-		/* fall through */
+		fallthrough;
 	default:
 		return IRQ_TYPE_NONE;
 	}
 }
 EXPORT_SYMBOL_GPL(acpi_dev_get_irq_type);
 
-static void acpi_dev_irqresource_disabled(struct resource *res, u32 gsi)
+/*
+ * DMI matches for boards where the DSDT specifies the kbd IRQ as
+ * level active-low and using the override changes this to rising edge,
+ * stopping the keyboard from working.
+ */
+static const struct dmi_system_id irq1_level_low_skip_override[] = {
+	{
+		/* MEDION P15651 */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "MEDION"),
+			DMI_MATCH(DMI_BOARD_NAME, "M15T"),
+		},
+	},
+	{
+		/* MEDION S17405 */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "MEDION"),
+			DMI_MATCH(DMI_BOARD_NAME, "M17T"),
+		},
+	},
+	{
+		/* MEDION S17413 */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "MEDION"),
+			DMI_MATCH(DMI_BOARD_NAME, "M1xA"),
+		},
+	},
+	{
+		/* Asus Vivobook K3402ZA */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
+			DMI_MATCH(DMI_BOARD_NAME, "K3402ZA"),
+		},
+	},
+	{
+		/* Asus Vivobook K3502ZA */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
+			DMI_MATCH(DMI_BOARD_NAME, "K3502ZA"),
+		},
+	},
+	{
+		/* Asus Vivobook S5402ZA */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
+			DMI_MATCH(DMI_BOARD_NAME, "S5402ZA"),
+		},
+	},
+	{
+		/* Asus Vivobook S5602ZA */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
+			DMI_MATCH(DMI_BOARD_NAME, "S5602ZA"),
+		},
+	},
+	{
+		/* Asus Vivobook X1404VAP */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
+			DMI_MATCH(DMI_BOARD_NAME, "X1404VAP"),
+		},
+	},
+	{
+		/* Asus Vivobook X1504VAP */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
+			DMI_MATCH(DMI_BOARD_NAME, "X1504VAP"),
+		},
+	},
+	{
+		/* Asus Vivobook X1704VAP */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
+			DMI_MATCH(DMI_BOARD_NAME, "X1704VAP"),
+		},
+	},
+	{
+		/* Asus ExpertBook B1402C* */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
+			DMI_MATCH(DMI_BOARD_NAME, "B1402C"),
+		},
+	},
+	{
+		/* Asus ExpertBook B1502C* */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
+			DMI_MATCH(DMI_BOARD_NAME, "B1502C"),
+		},
+	},
+	{
+		/* Asus ExpertBook B2402 (B2402CBA / B2402FBA / B2402CVA / B2402FVA) */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
+			DMI_MATCH(DMI_BOARD_NAME, "B2402"),
+		},
+	},
+	{
+		/* Asus ExpertBook B2502 (B2502CBA / B2502FBA / B2502CVA / B2502FVA) */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
+			DMI_MATCH(DMI_BOARD_NAME, "B2502"),
+		},
+	},
+	{
+		/* Asus Vivobook Go E1404GA* */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
+			DMI_MATCH(DMI_BOARD_NAME, "E1404GA"),
+		},
+	},
+	{
+		/* Asus Vivobook E1504GA* */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
+			DMI_MATCH(DMI_BOARD_NAME, "E1504GA"),
+		},
+	},
+	{
+		/* Asus Vivobook Pro N6506M* */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
+			DMI_MATCH(DMI_BOARD_NAME, "N6506M"),
+		},
+	},
+	{
+		/* Asus Vivobook Pro N6506CU* */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
+			DMI_MATCH(DMI_BOARD_NAME, "N6506CU"),
+		},
+	},
+	{
+		/* LG Electronics 17U70P */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "LG Electronics"),
+			DMI_MATCH(DMI_BOARD_NAME, "17U70P"),
+		},
+	},
+	{
+		/* LG Electronics 16T90SP */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "LG Electronics"),
+			DMI_MATCH(DMI_BOARD_NAME, "16T90SP"),
+		},
+	},
+	{ }
+};
+
+/*
+ * DMI matches for AMD Zen boards where the DSDT specifies the kbd IRQ
+ * as falling edge and this must be overridden to rising edge,
+ * to have a working keyboard.
+ */
+static const struct dmi_system_id irq1_edge_low_force_override[] = {
+	{
+		/* MECHREVO Jiaolong17KS Series GM7XG0M */
+		.matches = {
+			DMI_MATCH(DMI_BOARD_NAME, "GM7XG0M"),
+		},
+	},
+	{
+		/* XMG APEX 17 (M23) */
+		.matches = {
+			DMI_MATCH(DMI_BOARD_NAME, "GMxBGxx"),
+		},
+	},
+	{
+		/* TongFang GMxRGxx/XMG CORE 15 (M22)/TUXEDO Stellaris 15 Gen4 AMD */
+		.matches = {
+			DMI_MATCH(DMI_BOARD_NAME, "GMxRGxx"),
+		},
+	},
+	{
+		/* TongFang GMxXGxx/TUXEDO Polaris 15 Gen5 AMD */
+		.matches = {
+			DMI_MATCH(DMI_BOARD_NAME, "GMxXGxx"),
+		},
+	},
+	{
+		/* TongFang GMxXGxX/TUXEDO Polaris 15 Gen5 AMD */
+		.matches = {
+			DMI_MATCH(DMI_BOARD_NAME, "GMxXGxX"),
+		},
+	},
+	{
+		/* TongFang GMxXGxx sold as Eluktronics Inc. RP-15 */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "Eluktronics Inc."),
+			DMI_MATCH(DMI_BOARD_NAME, "RP-15"),
+		},
+	},
+	{
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "Eluktronics Inc."),
+			DMI_MATCH(DMI_BOARD_NAME, "MECH-17"),
+		},
+	},
+	{
+		/* TongFang GM6XGxX/TUXEDO Stellaris 16 Gen5 AMD */
+		.matches = {
+			DMI_MATCH(DMI_BOARD_NAME, "GM6XGxX"),
+		},
+	},
+	{
+		/* MAINGEAR Vector Pro 2 15 */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "Micro Electronics Inc"),
+			DMI_MATCH(DMI_PRODUCT_NAME, "MG-VCP2-15A3070T"),
+		}
+	},
+	{
+		/* MAINGEAR Vector Pro 2 17 */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "Micro Electronics Inc"),
+			DMI_MATCH(DMI_PRODUCT_NAME, "MG-VCP2-17A3070T"),
+		},
+	},
+	{
+		/* TongFang GM6BGEQ / PCSpecialist Elimina Pro 16 M, RTX 3050 */
+		.matches = {
+			DMI_MATCH(DMI_BOARD_NAME, "GM6BGEQ"),
+		},
+	},
+	{
+		/* TongFang GM6BG5Q, RTX 4050 */
+		.matches = {
+			DMI_MATCH(DMI_BOARD_NAME, "GM6BG5Q"),
+		},
+	},
+	{
+		/* TongFang GM6BG0Q / PCSpecialist Elimina Pro 16 M, RTX 4060 */
+		.matches = {
+			DMI_MATCH(DMI_BOARD_NAME, "GM6BG0Q"),
+		},
+	},
+	{
+		/* Infinity E15-5A165-BM */
+		.matches = {
+			DMI_MATCH(DMI_BOARD_NAME, "GM5RG1E0009COM"),
+		},
+	},
+	{
+		/* Infinity E15-5A305-1M */
+		.matches = {
+			DMI_MATCH(DMI_BOARD_NAME, "GM5RGEE0016COM"),
+		},
+	},
+	{
+		/* Lunnen Ground 15 / AMD Ryzen 5 5500U */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "Lunnen"),
+			DMI_MATCH(DMI_BOARD_NAME, "LLL5DAW"),
+		},
+	},
+	{
+		/* Lunnen Ground 16 / AMD Ryzen 7 5800U */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "Lunnen"),
+			DMI_MATCH(DMI_BOARD_NAME, "LL6FA"),
+		},
+	},
+	{
+		/* MAIBENBEN X577 */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "MAIBENBEN"),
+			DMI_MATCH(DMI_BOARD_NAME, "X577"),
+		},
+	},
+	{
+		/* Maibenben X565 */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "MAIBENBEN"),
+			DMI_MATCH(DMI_BOARD_NAME, "X565"),
+		},
+	},
+	{
+		/* TongFang GXxHRXx/TUXEDO InfinityBook Pro Gen9 AMD */
+		.matches = {
+			DMI_MATCH(DMI_BOARD_NAME, "GXxHRXx"),
+		},
+	},
+	{
+		/* TongFang GMxHGxx/TUXEDO Stellaris Slim Gen1 AMD */
+		.matches = {
+			DMI_MATCH(DMI_BOARD_NAME, "GMxHGxx"),
+		},
+	},
+	{
+		/* MACHENIKE L16P/L16P */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "MACHENIKE"),
+			DMI_MATCH(DMI_BOARD_NAME, "L16P"),
+		},
+	},
+	{
+		/*
+		 * TongFang GM5HG0A in case of the SKIKK Vanaheim relabel the
+		 * board-name is changed, so check OEM strings instead. Note
+		 * OEM string matches are always exact matches.
+		 * https://bugzilla.kernel.org/show_bug.cgi?id=219614
+		 */
+		.matches = {
+			DMI_EXACT_MATCH(DMI_OEM_STRING, "GM5HG0A"),
+		},
+	},
+	{ }
+};
+
+struct irq_override_cmp {
+	const struct dmi_system_id *system;
+	unsigned char irq;
+	unsigned char triggering;
+	unsigned char polarity;
+	unsigned char shareable;
+	bool override;
+};
+
+static const struct irq_override_cmp override_table[] = {
+	{ irq1_level_low_skip_override, 1, ACPI_LEVEL_SENSITIVE, ACPI_ACTIVE_LOW, 0, false },
+	{ irq1_edge_low_force_override, 1, ACPI_EDGE_SENSITIVE, ACPI_ACTIVE_LOW, 1, true },
+};
+
+static bool acpi_dev_irq_override(u32 gsi, u8 triggering, u8 polarity,
+				  u8 shareable)
 {
-	res->start = gsi;
-	res->end = gsi;
-	res->flags = IORESOURCE_IRQ | IORESOURCE_DISABLED | IORESOURCE_UNSET;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(override_table); i++) {
+		const struct irq_override_cmp *entry = &override_table[i];
+
+		if (entry->irq == gsi &&
+		    entry->triggering == triggering &&
+		    entry->polarity == polarity &&
+		    entry->shareable == shareable &&
+		    dmi_check_system(entry->system))
+			return entry->override;
+	}
+
+#ifdef CONFIG_X86
+	/*
+	 * Always use the MADT override info, except for the i8042 PS/2 ctrl
+	 * IRQs (1 and 12). For these the DSDT IRQ settings should sometimes
+	 * be used otherwise PS/2 keyboards / mice will not work.
+	 */
+	if (gsi != 1 && gsi != 12)
+		return true;
+
+	/* If the override comes from an INT_SRC_OVR MADT entry, honor it. */
+	if (acpi_int_src_ovr[gsi])
+		return true;
+
+	/*
+	 * IRQ override isn't needed on modern AMD Zen systems and
+	 * this override breaks active low IRQs on AMD Ryzen 6000 and
+	 * newer systems. Skip it.
+	 */
+	if (boot_cpu_has(X86_FEATURE_ZEN))
+		return false;
+#endif
+
+	return true;
 }
 
 static void acpi_dev_get_irqresource(struct resource *res, u32 gsi,
 				     u8 triggering, u8 polarity, u8 shareable,
-				     bool legacy)
+				     u8 wake_capable, bool check_override)
 {
 	int irq, p, t;
 
 	if (!valid_IRQ(gsi)) {
-		acpi_dev_irqresource_disabled(res, gsi);
+		irqresource_disabled(res, gsi);
 		return;
 	}
 
@@ -408,25 +771,30 @@ static void acpi_dev_get_irqresource(struct resource *res, u32 gsi,
 	 * using extended IRQ descriptors we take the IRQ configuration
 	 * from _CRS directly.
 	 */
-	if (legacy && !acpi_get_override_irq(gsi, &t, &p)) {
+	if (check_override &&
+	    acpi_dev_irq_override(gsi, triggering, polarity, shareable) &&
+	    !acpi_get_override_irq(gsi, &t, &p)) {
 		u8 trig = t ? ACPI_LEVEL_SENSITIVE : ACPI_EDGE_SENSITIVE;
 		u8 pol = p ? ACPI_ACTIVE_LOW : ACPI_ACTIVE_HIGH;
 
 		if (triggering != trig || polarity != pol) {
-			pr_warn("ACPI: IRQ %d override to %s, %s\n", gsi,
-				t ? "level" : "edge", p ? "low" : "high");
+			pr_warn("ACPI: IRQ %d override to %s%s, %s%s\n", gsi,
+				t ? "level" : "edge",
+				trig == triggering ? "" : "(!)",
+				str_low_high(p),
+				pol == polarity ? "" : "(!)");
 			triggering = trig;
 			polarity = pol;
 		}
 	}
 
-	res->flags = acpi_dev_irq_flags(triggering, polarity, shareable);
+	res->flags = acpi_dev_irq_flags(triggering, polarity, shareable, wake_capable);
 	irq = acpi_register_gsi(NULL, gsi, triggering, polarity);
 	if (irq >= 0) {
 		res->start = irq;
 		res->end = irq;
 	} else {
-		acpi_dev_irqresource_disabled(res, gsi);
+		irqresource_disabled(res, gsi);
 	}
 }
 
@@ -463,25 +831,27 @@ bool acpi_dev_resource_interrupt(struct acpi_resource *ares, int index,
 		 */
 		irq = &ares->data.irq;
 		if (index >= irq->interrupt_count) {
-			acpi_dev_irqresource_disabled(res, 0);
+			irqresource_disabled(res, 0);
 			return false;
 		}
 		acpi_dev_get_irqresource(res, irq->interrupts[index],
 					 irq->triggering, irq->polarity,
-					 irq->shareable, true);
+					 irq->shareable, irq->wake_capable,
+					 true);
 		break;
 	case ACPI_RESOURCE_TYPE_EXTENDED_IRQ:
 		ext_irq = &ares->data.extended_irq;
 		if (index >= ext_irq->interrupt_count) {
-			acpi_dev_irqresource_disabled(res, 0);
+			irqresource_disabled(res, 0);
 			return false;
 		}
 		if (is_gsi(ext_irq))
 			acpi_dev_get_irqresource(res, ext_irq->interrupts[index],
 					 ext_irq->triggering, ext_irq->polarity,
-					 ext_irq->shareable, false);
+					 ext_irq->shareable, ext_irq->wake_capable,
+					 false);
 		else
-			acpi_dev_irqresource_disabled(res, 0);
+			irqresource_disabled(res, 0);
 		break;
 	default:
 		res->flags = 0;
@@ -541,7 +911,7 @@ static acpi_status acpi_dev_process_resource(struct acpi_resource *ares,
 		ret = c->preproc(ares, c->preproc_data);
 		if (ret < 0) {
 			c->error = ret;
-			return AE_CTRL_TERMINATE;
+			return AE_ABORT_METHOD;
 		} else if (ret > 0) {
 			return AE_OK;
 		}
@@ -603,7 +973,7 @@ static int __acpi_dev_get_resources(struct acpi_device *adev,
  * @preproc_data: Pointer passed to the caller's preprocessing routine.
  *
  * Evaluate the _CRS method for the given device node and process its output by
- * (1) executing the @preproc() rountine provided by the caller, passing the
+ * (1) executing the @preproc() routine provided by the caller, passing the
  * resource pointer and @preproc_data to it as arguments, for each ACPI resource
  * returned and (2) converting all of the returned ACPI resources into struct
  * resource objects if possible.  If the return value of @preproc() in step (1)
@@ -635,6 +1005,9 @@ static int is_memory(struct acpi_resource *ares, void *not_used)
 
 	memset(&win, 0, sizeof(win));
 
+	if (acpi_dev_filter_resource_type(ares, IORESOURCE_MEM))
+		return 1;
+
 	return !(acpi_dev_resource_memory(ares, res)
 	       || acpi_dev_resource_address_space(ares, &win)
 	       || acpi_dev_resource_ext_address_space(ares, &win));
@@ -664,6 +1037,23 @@ int acpi_dev_get_dma_resources(struct acpi_device *adev, struct list_head *list)
 EXPORT_SYMBOL_GPL(acpi_dev_get_dma_resources);
 
 /**
+ * acpi_dev_get_memory_resources - Get current memory resources of a device.
+ * @adev: ACPI device node to get the resources for.
+ * @list: Head of the resultant list of resources (must be empty).
+ *
+ * This is a helper function that locates all memory type resources of @adev
+ * with acpi_dev_get_resources().
+ *
+ * The number of resources in the output list is returned on success, an error
+ * code reflecting the error condition is returned otherwise.
+ */
+int acpi_dev_get_memory_resources(struct acpi_device *adev, struct list_head *list)
+{
+	return acpi_dev_get_resources(adev, list, is_memory, NULL);
+}
+EXPORT_SYMBOL_GPL(acpi_dev_get_memory_resources);
+
+/**
  * acpi_dev_filter_resource_type - Filter ACPI resource according to resource
  *				   types
  * @ares: Input ACPI resource object.
@@ -746,9 +1136,9 @@ static acpi_status acpi_res_consumer_cb(acpi_handle handle, u32 depth,
 {
 	struct resource *res = context;
 	struct acpi_device **consumer = (struct acpi_device **) ret;
-	struct acpi_device *adev;
+	struct acpi_device *adev = acpi_fetch_acpi_dev(handle);
 
-	if (acpi_bus_get_device(handle, &adev))
+	if (!adev)
 		return AE_OK;
 
 	if (acpi_dev_consumes_res(adev, res)) {
diff --git a/drivers/acpi/riscv/Kconfig b/drivers/acpi/riscv/Kconfig
new file mode 100644
index 000000000000..046296a18d00
--- /dev/null
+++ b/drivers/acpi/riscv/Kconfig
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# ACPI Configuration for RISC-V
+#
+
+config ACPI_RIMT
+	bool
diff --git a/drivers/acpi/riscv/Makefile b/drivers/acpi/riscv/Makefile
new file mode 100644
index 000000000000..1284a076fa88
--- /dev/null
+++ b/drivers/acpi/riscv/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-y					+= rhct.o init.o irq.o
+obj-$(CONFIG_ACPI_PROCESSOR_IDLE)	+= cpuidle.o
+obj-$(CONFIG_ACPI_CPPC_LIB)		+= cppc.o
+obj-$(CONFIG_ACPI_RIMT)			+= rimt.o
diff --git a/drivers/acpi/riscv/cppc.c b/drivers/acpi/riscv/cppc.c
new file mode 100644
index 000000000000..42c1a9052470
--- /dev/null
+++ b/drivers/acpi/riscv/cppc.c
@@ -0,0 +1,155 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Implement CPPC FFH helper routines for RISC-V.
+ *
+ * Copyright (C) 2024 Ventana Micro Systems Inc.
+ */
+
+#include <acpi/cppc_acpi.h>
+#include <asm/csr.h>
+#include <asm/sbi.h>
+
+#define SBI_EXT_CPPC 0x43505043
+
+/* CPPC interfaces defined in SBI spec */
+#define SBI_CPPC_PROBE			0x0
+#define SBI_CPPC_READ			0x1
+#define SBI_CPPC_READ_HI		0x2
+#define SBI_CPPC_WRITE			0x3
+
+/* RISC-V FFH definitions from RISC-V FFH spec */
+#define FFH_CPPC_TYPE(r)		(((r) & GENMASK_ULL(63, 60)) >> 60)
+#define FFH_CPPC_SBI_REG(r)		((r) & GENMASK(31, 0))
+#define FFH_CPPC_CSR_NUM(r)		((r) & GENMASK(11, 0))
+
+#define FFH_CPPC_SBI			0x1
+#define FFH_CPPC_CSR			0x2
+
+struct sbi_cppc_data {
+	u64 val;
+	u32 reg;
+	struct sbiret ret;
+};
+
+static bool cppc_ext_present;
+
+static int __init sbi_cppc_init(void)
+{
+	if (sbi_spec_version >= sbi_mk_version(2, 0) &&
+	    sbi_probe_extension(SBI_EXT_CPPC) > 0) {
+		cppc_ext_present = true;
+	} else {
+		cppc_ext_present = false;
+	}
+
+	return 0;
+}
+device_initcall(sbi_cppc_init);
+
+static void sbi_cppc_read(void *read_data)
+{
+	struct sbi_cppc_data *data = (struct sbi_cppc_data *)read_data;
+
+	data->ret = sbi_ecall(SBI_EXT_CPPC, SBI_CPPC_READ,
+			      data->reg, 0, 0, 0, 0, 0);
+}
+
+static void sbi_cppc_write(void *write_data)
+{
+	struct sbi_cppc_data *data = (struct sbi_cppc_data *)write_data;
+
+	data->ret = sbi_ecall(SBI_EXT_CPPC, SBI_CPPC_WRITE,
+			      data->reg, data->val, 0, 0, 0, 0);
+}
+
+static void cppc_ffh_csr_read(void *read_data)
+{
+	struct sbi_cppc_data *data = (struct sbi_cppc_data *)read_data;
+
+	switch (data->reg) {
+	/* Support only TIME CSR for now */
+	case CSR_TIME:
+		data->ret.value = csr_read(CSR_TIME);
+		data->ret.error = 0;
+		break;
+	default:
+		data->ret.error = -EINVAL;
+		break;
+	}
+}
+
+static void cppc_ffh_csr_write(void *write_data)
+{
+	struct sbi_cppc_data *data = (struct sbi_cppc_data *)write_data;
+
+	data->ret.error = -EINVAL;
+}
+
+/*
+ * Refer to drivers/acpi/cppc_acpi.c for the description of the functions
+ * below.
+ */
+bool cpc_ffh_supported(void)
+{
+	return true;
+}
+
+int cpc_read_ffh(int cpu, struct cpc_reg *reg, u64 *val)
+{
+	struct sbi_cppc_data data;
+
+	if (WARN_ON_ONCE(irqs_disabled()))
+		return -EPERM;
+
+	if (FFH_CPPC_TYPE(reg->address) == FFH_CPPC_SBI) {
+		if (!cppc_ext_present)
+			return -EINVAL;
+
+		data.reg = FFH_CPPC_SBI_REG(reg->address);
+
+		smp_call_function_single(cpu, sbi_cppc_read, &data, 1);
+
+		*val = data.ret.value;
+
+		return (data.ret.error) ? sbi_err_map_linux_errno(data.ret.error) : 0;
+	} else if (FFH_CPPC_TYPE(reg->address) == FFH_CPPC_CSR) {
+		data.reg = FFH_CPPC_CSR_NUM(reg->address);
+
+		smp_call_function_single(cpu, cppc_ffh_csr_read, &data, 1);
+
+		*val = data.ret.value;
+
+		return data.ret.error;
+	}
+
+	return -EINVAL;
+}
+
+int cpc_write_ffh(int cpu, struct cpc_reg *reg, u64 val)
+{
+	struct sbi_cppc_data data;
+
+	if (WARN_ON_ONCE(irqs_disabled()))
+		return -EPERM;
+
+	if (FFH_CPPC_TYPE(reg->address) == FFH_CPPC_SBI) {
+		if (!cppc_ext_present)
+			return -EINVAL;
+
+		data.reg = FFH_CPPC_SBI_REG(reg->address);
+		data.val = val;
+
+		smp_call_function_single(cpu, sbi_cppc_write, &data, 1);
+
+		return (data.ret.error) ? sbi_err_map_linux_errno(data.ret.error) : 0;
+	} else if (FFH_CPPC_TYPE(reg->address) == FFH_CPPC_CSR) {
+		data.reg = FFH_CPPC_CSR_NUM(reg->address);
+		data.val = val;
+
+		smp_call_function_single(cpu, cppc_ffh_csr_write, &data, 1);
+
+		return data.ret.error;
+	}
+
+	return -EINVAL;
+}
diff --git a/drivers/acpi/riscv/cpuidle.c b/drivers/acpi/riscv/cpuidle.c
new file mode 100644
index 000000000000..624f9bbdb58c
--- /dev/null
+++ b/drivers/acpi/riscv/cpuidle.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2024, Ventana Micro Systems Inc
+ *	Author: Sunil V L <sunilvl@ventanamicro.com>
+ *
+ */
+
+#include <linux/acpi.h>
+#include <acpi/processor.h>
+#include <linux/cpu_pm.h>
+#include <linux/cpuidle.h>
+#include <linux/suspend.h>
+#include <asm/cpuidle.h>
+#include <asm/sbi.h>
+#include <asm/suspend.h>
+
+#define RISCV_FFH_LPI_TYPE_MASK	GENMASK_ULL(63, 60)
+#define RISCV_FFH_LPI_RSVD_MASK	GENMASK_ULL(59, 32)
+
+#define RISCV_FFH_LPI_TYPE_SBI	BIT_ULL(60)
+
+static int acpi_cpu_init_idle(unsigned int cpu)
+{
+	int i;
+	struct acpi_lpi_state *lpi;
+	struct acpi_processor *pr = per_cpu(processors, cpu);
+
+	if (unlikely(!pr || !pr->flags.has_lpi))
+		return -EINVAL;
+
+	if (!riscv_sbi_hsm_is_supported())
+		return -ENODEV;
+
+	if (pr->power.count <= 1)
+		return -ENODEV;
+
+	for (i = 1; i < pr->power.count; i++) {
+		u32 state;
+
+		lpi = &pr->power.lpi_states[i];
+
+		/*
+		 * Validate Entry Method as per FFH spec.
+		 * bits[63:60] should be 0x1
+		 * bits[59:32] should be 0x0
+		 * bits[31:0] represent a SBI power_state
+		 */
+		if (((lpi->address & RISCV_FFH_LPI_TYPE_MASK) != RISCV_FFH_LPI_TYPE_SBI) ||
+		    (lpi->address & RISCV_FFH_LPI_RSVD_MASK)) {
+			pr_warn("Invalid LPI entry method %#llx\n", lpi->address);
+			return -EINVAL;
+		}
+
+		state = lpi->address;
+		if (!riscv_sbi_suspend_state_is_valid(state)) {
+			pr_warn("Invalid SBI power state %#x\n", state);
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
+int acpi_processor_ffh_lpi_probe(unsigned int cpu)
+{
+	return acpi_cpu_init_idle(cpu);
+}
+
+int acpi_processor_ffh_lpi_enter(struct acpi_lpi_state *lpi)
+{
+	u32 state = lpi->address;
+
+	if (state & SBI_HSM_SUSP_NON_RET_BIT)
+		return CPU_PM_CPU_IDLE_ENTER_PARAM(riscv_sbi_hart_suspend,
+						   lpi->index,
+						   state);
+	else
+		return CPU_PM_CPU_IDLE_ENTER_RETENTION_PARAM(riscv_sbi_hart_suspend,
+							     lpi->index,
+							     state);
+}
diff --git a/drivers/acpi/riscv/init.c b/drivers/acpi/riscv/init.c
new file mode 100644
index 000000000000..7c00f7995e86
--- /dev/null
+++ b/drivers/acpi/riscv/init.c
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2023-2024, Ventana Micro Systems Inc
+ *	Author: Sunil V L <sunilvl@ventanamicro.com>
+ */
+
+#include <linux/acpi.h>
+#include "init.h"
+
+void __init acpi_arch_init(void)
+{
+	riscv_acpi_init_gsi_mapping();
+	if (IS_ENABLED(CONFIG_ACPI_RIMT))
+		riscv_acpi_rimt_init();
+}
diff --git a/drivers/acpi/riscv/init.h b/drivers/acpi/riscv/init.h
new file mode 100644
index 000000000000..1680aa2aaf23
--- /dev/null
+++ b/drivers/acpi/riscv/init.h
@@ -0,0 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#include <linux/init.h>
+
+void __init riscv_acpi_init_gsi_mapping(void);
+void __init riscv_acpi_rimt_init(void);
diff --git a/drivers/acpi/riscv/irq.c b/drivers/acpi/riscv/irq.c
new file mode 100644
index 000000000000..d9a2154d6c6a
--- /dev/null
+++ b/drivers/acpi/riscv/irq.c
@@ -0,0 +1,404 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2023-2024, Ventana Micro Systems Inc
+ *	Author: Sunil V L <sunilvl@ventanamicro.com>
+ */
+
+#include <linux/acpi.h>
+#include <linux/sort.h>
+#include <linux/irq.h>
+
+#include "init.h"
+
+#define RISCV_ACPI_INTC_FLAG_PENDING BIT(0)
+
+struct riscv_ext_intc_list {
+	acpi_handle		handle;
+	u32			gsi_base;
+	u32			nr_irqs;
+	u32			nr_idcs;
+	u32			id;
+	u32			type;
+	u32			flag;
+	struct list_head	list;
+};
+
+struct acpi_irq_dep_ctx {
+	int		rc;
+	unsigned int	index;
+	acpi_handle	handle;
+};
+
+LIST_HEAD(ext_intc_list);
+
+static int irqchip_cmp_func(const void *in0, const void *in1)
+{
+	struct acpi_probe_entry *elem0 = (struct acpi_probe_entry *)in0;
+	struct acpi_probe_entry *elem1 = (struct acpi_probe_entry *)in1;
+
+	return (elem0->type > elem1->type) - (elem0->type < elem1->type);
+}
+
+/*
+ * On RISC-V, RINTC structures in MADT should be probed before any other
+ * interrupt controller structures and IMSIC before APLIC. The interrupt
+ * controller subtypes in MADT of ACPI spec for RISC-V are defined in
+ * the incremental order like RINTC(24)->IMSIC(25)->APLIC(26)->PLIC(27).
+ * Hence, simply sorting the subtypes in incremental order will
+ * establish the required order.
+ */
+void arch_sort_irqchip_probe(struct acpi_probe_entry *ap_head, int nr)
+{
+	struct acpi_probe_entry *ape = ap_head;
+
+	if (nr == 1 || !ACPI_COMPARE_NAMESEG(ACPI_SIG_MADT, ape->id))
+		return;
+	sort(ape, nr, sizeof(*ape), irqchip_cmp_func, NULL);
+}
+
+static acpi_status riscv_acpi_update_gsi_handle(u32 gsi_base, acpi_handle handle)
+{
+	struct riscv_ext_intc_list *ext_intc_element;
+	struct list_head *i, *tmp;
+
+	list_for_each_safe(i, tmp, &ext_intc_list) {
+		ext_intc_element = list_entry(i, struct riscv_ext_intc_list, list);
+		if (gsi_base == ext_intc_element->gsi_base) {
+			ext_intc_element->handle = handle;
+			return AE_OK;
+		}
+	}
+
+	return AE_NOT_FOUND;
+}
+
+int riscv_acpi_update_gsi_range(u32 gsi_base, u32 nr_irqs)
+{
+	struct riscv_ext_intc_list *ext_intc_element;
+
+	list_for_each_entry(ext_intc_element, &ext_intc_list, list) {
+		if (gsi_base == ext_intc_element->gsi_base &&
+		    (ext_intc_element->flag & RISCV_ACPI_INTC_FLAG_PENDING)) {
+			ext_intc_element->nr_irqs = nr_irqs;
+			ext_intc_element->flag &= ~RISCV_ACPI_INTC_FLAG_PENDING;
+			return 0;
+		}
+	}
+
+	return -ENODEV;
+}
+
+int riscv_acpi_get_gsi_info(struct fwnode_handle *fwnode, u32 *gsi_base,
+			    u32 *id, u32 *nr_irqs, u32 *nr_idcs)
+{
+	struct riscv_ext_intc_list *ext_intc_element;
+	struct list_head *i;
+
+	list_for_each(i, &ext_intc_list) {
+		ext_intc_element = list_entry(i, struct riscv_ext_intc_list, list);
+		if (ext_intc_element->handle == ACPI_HANDLE_FWNODE(fwnode)) {
+			*gsi_base = ext_intc_element->gsi_base;
+			*id = ext_intc_element->id;
+			*nr_irqs = ext_intc_element->nr_irqs;
+			if (nr_idcs)
+				*nr_idcs = ext_intc_element->nr_idcs;
+
+			return 0;
+		}
+	}
+
+	return -ENODEV;
+}
+
+struct fwnode_handle *riscv_acpi_get_gsi_domain_id(u32 gsi)
+{
+	struct riscv_ext_intc_list *ext_intc_element;
+	struct acpi_device *adev;
+	struct list_head *i;
+
+	list_for_each(i, &ext_intc_list) {
+		ext_intc_element = list_entry(i, struct riscv_ext_intc_list, list);
+		if (gsi >= ext_intc_element->gsi_base &&
+		    gsi < (ext_intc_element->gsi_base + ext_intc_element->nr_irqs)) {
+			adev = acpi_fetch_acpi_dev(ext_intc_element->handle);
+			if (!adev)
+				return NULL;
+
+			return acpi_fwnode_handle(adev);
+		}
+	}
+
+	return NULL;
+}
+
+static int __init riscv_acpi_register_ext_intc(u32 gsi_base, u32 nr_irqs, u32 nr_idcs,
+					       u32 id, u32 type)
+{
+	struct riscv_ext_intc_list *ext_intc_element, *node, *prev;
+
+	ext_intc_element = kzalloc(sizeof(*ext_intc_element), GFP_KERNEL);
+	if (!ext_intc_element)
+		return -ENOMEM;
+
+	ext_intc_element->gsi_base = gsi_base;
+
+	/* If nr_irqs is zero, indicate it in flag and set to max range possible */
+	if (nr_irqs) {
+		ext_intc_element->nr_irqs = nr_irqs;
+	} else {
+		ext_intc_element->flag |= RISCV_ACPI_INTC_FLAG_PENDING;
+		ext_intc_element->nr_irqs = U32_MAX - ext_intc_element->gsi_base;
+	}
+
+	ext_intc_element->nr_idcs = nr_idcs;
+	ext_intc_element->id = id;
+	list_for_each_entry(node, &ext_intc_list, list) {
+		if (node->gsi_base < ext_intc_element->gsi_base)
+			break;
+	}
+
+	/* Adjust the previous node's GSI range if that has pending registration */
+	prev = list_prev_entry(node, list);
+	if (!list_entry_is_head(prev, &ext_intc_list, list)) {
+		if (prev->flag & RISCV_ACPI_INTC_FLAG_PENDING)
+			prev->nr_irqs = ext_intc_element->gsi_base - prev->gsi_base;
+	}
+
+	list_add_tail(&ext_intc_element->list, &node->list);
+	return 0;
+}
+
+static acpi_status __init riscv_acpi_create_gsi_map_smsi(acpi_handle handle, u32 level,
+							 void *context, void **return_value)
+{
+	acpi_status status;
+	u64 gbase;
+
+	if (!acpi_has_method(handle, "_GSB")) {
+		acpi_handle_err(handle, "_GSB method not found\n");
+		return AE_ERROR;
+	}
+
+	status = acpi_evaluate_integer(handle, "_GSB", NULL, &gbase);
+	if (ACPI_FAILURE(status)) {
+		acpi_handle_err(handle, "failed to evaluate _GSB method\n");
+		return status;
+	}
+
+	riscv_acpi_register_ext_intc(gbase, 0, 0, 0, ACPI_RISCV_IRQCHIP_SMSI);
+	status = riscv_acpi_update_gsi_handle((u32)gbase, handle);
+	if (ACPI_FAILURE(status)) {
+		acpi_handle_err(handle, "failed to find the GSI mapping entry\n");
+		return status;
+	}
+
+	return AE_OK;
+}
+
+static acpi_status __init riscv_acpi_create_gsi_map(acpi_handle handle, u32 level,
+						    void *context, void **return_value)
+{
+	acpi_status status;
+	u64 gbase;
+
+	if (!acpi_has_method(handle, "_GSB")) {
+		acpi_handle_err(handle, "_GSB method not found\n");
+		return AE_ERROR;
+	}
+
+	status = acpi_evaluate_integer(handle, "_GSB", NULL, &gbase);
+	if (ACPI_FAILURE(status)) {
+		acpi_handle_err(handle, "failed to evaluate _GSB method\n");
+		return status;
+	}
+
+	status = riscv_acpi_update_gsi_handle((u32)gbase, handle);
+	if (ACPI_FAILURE(status)) {
+		acpi_handle_err(handle, "failed to find the GSI mapping entry\n");
+		return status;
+	}
+
+	return AE_OK;
+}
+
+static int __init riscv_acpi_aplic_parse_madt(union acpi_subtable_headers *header,
+					      const unsigned long end)
+{
+	struct acpi_madt_aplic *aplic = (struct acpi_madt_aplic *)header;
+
+	return riscv_acpi_register_ext_intc(aplic->gsi_base, aplic->num_sources, aplic->num_idcs,
+					    aplic->id, ACPI_RISCV_IRQCHIP_APLIC);
+}
+
+static int __init riscv_acpi_plic_parse_madt(union acpi_subtable_headers *header,
+					     const unsigned long end)
+{
+	struct acpi_madt_plic *plic = (struct acpi_madt_plic *)header;
+
+	return riscv_acpi_register_ext_intc(plic->gsi_base, plic->num_irqs, 0,
+					    plic->id, ACPI_RISCV_IRQCHIP_PLIC);
+}
+
+void __init riscv_acpi_init_gsi_mapping(void)
+{
+	/* There can be either PLIC or APLIC */
+	if (acpi_table_parse_madt(ACPI_MADT_TYPE_PLIC, riscv_acpi_plic_parse_madt, 0) > 0) {
+		acpi_get_devices("RSCV0001", riscv_acpi_create_gsi_map, NULL, NULL);
+		return;
+	}
+
+	if (acpi_table_parse_madt(ACPI_MADT_TYPE_APLIC, riscv_acpi_aplic_parse_madt, 0) > 0)
+		acpi_get_devices("RSCV0002", riscv_acpi_create_gsi_map, NULL, NULL);
+
+	/* Unlike PLIC/APLIC, SYSMSI doesn't have MADT */
+	acpi_get_devices("RSCV0006", riscv_acpi_create_gsi_map_smsi, NULL, NULL);
+}
+
+static acpi_handle riscv_acpi_get_gsi_handle(u32 gsi)
+{
+	struct riscv_ext_intc_list *ext_intc_element;
+	struct list_head *i;
+
+	list_for_each(i, &ext_intc_list) {
+		ext_intc_element = list_entry(i, struct riscv_ext_intc_list, list);
+		if (gsi >= ext_intc_element->gsi_base &&
+		    gsi < (ext_intc_element->gsi_base + ext_intc_element->nr_irqs))
+			return ext_intc_element->handle;
+	}
+
+	return NULL;
+}
+
+static acpi_status riscv_acpi_irq_get_parent(struct acpi_resource *ares, void *context)
+{
+	struct acpi_irq_dep_ctx *ctx = context;
+	struct acpi_resource_irq *irq;
+	struct acpi_resource_extended_irq *eirq;
+
+	switch (ares->type) {
+	case ACPI_RESOURCE_TYPE_IRQ:
+		irq = &ares->data.irq;
+		if (ctx->index >= irq->interrupt_count) {
+			ctx->index -= irq->interrupt_count;
+			return AE_OK;
+		}
+		ctx->handle = riscv_acpi_get_gsi_handle(irq->interrupts[ctx->index]);
+		return AE_CTRL_TERMINATE;
+	case ACPI_RESOURCE_TYPE_EXTENDED_IRQ:
+		eirq = &ares->data.extended_irq;
+		if (eirq->producer_consumer == ACPI_PRODUCER)
+			return AE_OK;
+
+		if (ctx->index >= eirq->interrupt_count) {
+			ctx->index -= eirq->interrupt_count;
+			return AE_OK;
+		}
+
+		/* Support GSIs only */
+		if (eirq->resource_source.string_length)
+			return AE_OK;
+
+		ctx->handle = riscv_acpi_get_gsi_handle(eirq->interrupts[ctx->index]);
+		return AE_CTRL_TERMINATE;
+	}
+
+	return AE_OK;
+}
+
+static int riscv_acpi_irq_get_dep(acpi_handle handle, unsigned int index, acpi_handle *gsi_handle)
+{
+	struct acpi_irq_dep_ctx ctx = {-EINVAL, index, NULL};
+
+	if (!gsi_handle)
+		return 0;
+
+	acpi_walk_resources(handle, METHOD_NAME__CRS, riscv_acpi_irq_get_parent, &ctx);
+	*gsi_handle = ctx.handle;
+	if (*gsi_handle)
+		return 1;
+
+	return 0;
+}
+
+static u32 riscv_acpi_add_prt_dep(acpi_handle handle)
+{
+	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
+	struct acpi_pci_routing_table *entry;
+	struct acpi_handle_list dep_devices;
+	acpi_handle gsi_handle;
+	acpi_handle link_handle;
+	acpi_status status;
+	u32 count = 0;
+
+	status = acpi_get_irq_routing_table(handle, &buffer);
+	if (ACPI_FAILURE(status)) {
+		acpi_handle_err(handle, "failed to get IRQ routing table\n");
+		kfree(buffer.pointer);
+		return 0;
+	}
+
+	entry = buffer.pointer;
+	while (entry && (entry->length > 0)) {
+		if (entry->source[0]) {
+			acpi_get_handle(handle, entry->source, &link_handle);
+			dep_devices.count = 1;
+			dep_devices.handles = kcalloc(1, sizeof(*dep_devices.handles), GFP_KERNEL);
+			if (!dep_devices.handles) {
+				acpi_handle_err(handle, "failed to allocate memory\n");
+				continue;
+			}
+
+			dep_devices.handles[0] = link_handle;
+			count += acpi_scan_add_dep(handle, &dep_devices);
+		} else {
+			gsi_handle = riscv_acpi_get_gsi_handle(entry->source_index);
+			dep_devices.count = 1;
+			dep_devices.handles = kcalloc(1, sizeof(*dep_devices.handles), GFP_KERNEL);
+			if (!dep_devices.handles) {
+				acpi_handle_err(handle, "failed to allocate memory\n");
+				continue;
+			}
+
+			dep_devices.handles[0] = gsi_handle;
+			count += acpi_scan_add_dep(handle, &dep_devices);
+		}
+
+		entry = (struct acpi_pci_routing_table *)
+			((unsigned long)entry + entry->length);
+	}
+
+	kfree(buffer.pointer);
+	return count;
+}
+
+static u32 riscv_acpi_add_irq_dep(acpi_handle handle)
+{
+	struct acpi_handle_list dep_devices;
+	acpi_handle gsi_handle;
+	u32 count = 0;
+	int i;
+
+	for (i = 0;
+	     riscv_acpi_irq_get_dep(handle, i, &gsi_handle);
+	     i++) {
+		dep_devices.count = 1;
+		dep_devices.handles = kcalloc(1, sizeof(*dep_devices.handles), GFP_KERNEL);
+		if (!dep_devices.handles) {
+			acpi_handle_err(handle, "failed to allocate memory\n");
+			continue;
+		}
+
+		dep_devices.handles[0] = gsi_handle;
+		count += acpi_scan_add_dep(handle, &dep_devices);
+	}
+
+	return count;
+}
+
+u32 arch_acpi_add_auto_dep(acpi_handle handle)
+{
+	if (acpi_has_method(handle, "_PRT"))
+		return riscv_acpi_add_prt_dep(handle);
+
+	return riscv_acpi_add_irq_dep(handle);
+}
diff --git a/drivers/acpi/riscv/rhct.c b/drivers/acpi/riscv/rhct.c
new file mode 100644
index 000000000000..caa2c16e1697
--- /dev/null
+++ b/drivers/acpi/riscv/rhct.c
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2022-2023, Ventana Micro Systems Inc
+ *	Author: Sunil V L <sunilvl@ventanamicro.com>
+ *
+ */
+
+#define pr_fmt(fmt)     "ACPI: RHCT: " fmt
+
+#include <linux/acpi.h>
+#include <linux/bits.h>
+
+static struct acpi_table_rhct *acpi_get_rhct(void)
+{
+	static struct acpi_table_header *rhct;
+	acpi_status status;
+
+	/*
+	 * RHCT will be used at runtime on every CPU, so we
+	 * don't need to call acpi_put_table() to release the table mapping.
+	 */
+	if (!rhct) {
+		status = acpi_get_table(ACPI_SIG_RHCT, 0, &rhct);
+		if (ACPI_FAILURE(status)) {
+			pr_warn_once("No RHCT table found\n");
+			return NULL;
+		}
+	}
+
+	return (struct acpi_table_rhct *)rhct;
+}
+
+/*
+ * During early boot, the caller should call acpi_get_table() and pass its pointer to
+ * these functions(and free up later). At run time, since this table can be used
+ * multiple times, NULL may be passed in order to use the cached table.
+ */
+int acpi_get_riscv_isa(struct acpi_table_header *table, unsigned int cpu, const char **isa)
+{
+	struct acpi_rhct_node_header *node, *ref_node, *end;
+	u32 size_hdr = sizeof(struct acpi_rhct_node_header);
+	u32 size_hartinfo = sizeof(struct acpi_rhct_hart_info);
+	struct acpi_rhct_hart_info *hart_info;
+	struct acpi_rhct_isa_string *isa_node;
+	struct acpi_table_rhct *rhct;
+	u32 *hart_info_node_offset;
+	u32 acpi_cpu_id = get_acpi_id_for_cpu(cpu);
+
+	BUG_ON(acpi_disabled);
+
+	if (!table) {
+		rhct = acpi_get_rhct();
+		if (!rhct)
+			return -ENOENT;
+	} else {
+		rhct = (struct acpi_table_rhct *)table;
+	}
+
+	end = ACPI_ADD_PTR(struct acpi_rhct_node_header, rhct, rhct->header.length);
+
+	for (node = ACPI_ADD_PTR(struct acpi_rhct_node_header, rhct, rhct->node_offset);
+	     node < end;
+	     node = ACPI_ADD_PTR(struct acpi_rhct_node_header, node, node->length)) {
+		if (node->type == ACPI_RHCT_NODE_TYPE_HART_INFO) {
+			hart_info = ACPI_ADD_PTR(struct acpi_rhct_hart_info, node, size_hdr);
+			hart_info_node_offset = ACPI_ADD_PTR(u32, hart_info, size_hartinfo);
+			if (acpi_cpu_id != hart_info->uid)
+				continue;
+
+			for (int i = 0; i < hart_info->num_offsets; i++) {
+				ref_node = ACPI_ADD_PTR(struct acpi_rhct_node_header,
+							rhct, hart_info_node_offset[i]);
+				if (ref_node->type == ACPI_RHCT_NODE_TYPE_ISA_STRING) {
+					isa_node = ACPI_ADD_PTR(struct acpi_rhct_isa_string,
+								ref_node, size_hdr);
+					*isa = isa_node->isa;
+					return 0;
+				}
+			}
+		}
+	}
+
+	return -1;
+}
+
+static void acpi_parse_hart_info_cmo_node(struct acpi_table_rhct *rhct,
+					  struct acpi_rhct_hart_info *hart_info,
+					  u32 *cbom_size, u32 *cboz_size, u32 *cbop_size)
+{
+	u32 size_hartinfo = sizeof(struct acpi_rhct_hart_info);
+	u32 size_hdr = sizeof(struct acpi_rhct_node_header);
+	struct acpi_rhct_node_header *ref_node;
+	struct acpi_rhct_cmo_node *cmo_node;
+	u32 *hart_info_node_offset;
+
+	hart_info_node_offset = ACPI_ADD_PTR(u32, hart_info, size_hartinfo);
+	for (int i = 0; i < hart_info->num_offsets; i++) {
+		ref_node = ACPI_ADD_PTR(struct acpi_rhct_node_header,
+					rhct, hart_info_node_offset[i]);
+		if (ref_node->type == ACPI_RHCT_NODE_TYPE_CMO) {
+			cmo_node = ACPI_ADD_PTR(struct acpi_rhct_cmo_node,
+						ref_node, size_hdr);
+			if (cbom_size && cmo_node->cbom_size <= 30) {
+				if (!*cbom_size)
+					*cbom_size = BIT(cmo_node->cbom_size);
+				else if (*cbom_size != BIT(cmo_node->cbom_size))
+					pr_warn("CBOM size is not the same across harts\n");
+			}
+
+			if (cboz_size && cmo_node->cboz_size <= 30) {
+				if (!*cboz_size)
+					*cboz_size = BIT(cmo_node->cboz_size);
+				else if (*cboz_size != BIT(cmo_node->cboz_size))
+					pr_warn("CBOZ size is not the same across harts\n");
+			}
+
+			if (cbop_size && cmo_node->cbop_size <= 30) {
+				if (!*cbop_size)
+					*cbop_size = BIT(cmo_node->cbop_size);
+				else if (*cbop_size != BIT(cmo_node->cbop_size))
+					pr_warn("CBOP size is not the same across harts\n");
+			}
+		}
+	}
+}
+
+/*
+ * During early boot, the caller should call acpi_get_table() and pass its pointer to
+ * these functions (and free up later). At run time, since this table can be used
+ * multiple times, pass NULL so that the table remains in memory.
+ */
+void acpi_get_cbo_block_size(struct acpi_table_header *table, u32 *cbom_size,
+			     u32 *cboz_size, u32 *cbop_size)
+{
+	u32 size_hdr = sizeof(struct acpi_rhct_node_header);
+	struct acpi_rhct_node_header *node, *end;
+	struct acpi_rhct_hart_info *hart_info;
+	struct acpi_table_rhct *rhct;
+
+	if (acpi_disabled)
+		return;
+
+	if (table) {
+		rhct = (struct acpi_table_rhct *)table;
+	} else {
+		rhct = acpi_get_rhct();
+		if (!rhct)
+			return;
+	}
+
+	if (cbom_size)
+		*cbom_size = 0;
+
+	if (cboz_size)
+		*cboz_size = 0;
+
+	if (cbop_size)
+		*cbop_size = 0;
+
+	end = ACPI_ADD_PTR(struct acpi_rhct_node_header, rhct, rhct->header.length);
+	for (node = ACPI_ADD_PTR(struct acpi_rhct_node_header, rhct, rhct->node_offset);
+	     node < end;
+	     node = ACPI_ADD_PTR(struct acpi_rhct_node_header, node, node->length)) {
+		if (node->type == ACPI_RHCT_NODE_TYPE_HART_INFO) {
+			hart_info = ACPI_ADD_PTR(struct acpi_rhct_hart_info, node, size_hdr);
+			acpi_parse_hart_info_cmo_node(rhct, hart_info, cbom_size,
+						      cboz_size, cbop_size);
+		}
+	}
+}
diff --git a/drivers/acpi/riscv/rimt.c b/drivers/acpi/riscv/rimt.c
new file mode 100644
index 000000000000..7f423405e5ef
--- /dev/null
+++ b/drivers/acpi/riscv/rimt.c
@@ -0,0 +1,520 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2024-2025, Ventana Micro Systems Inc
+ *	Author: Sunil V L <sunilvl@ventanamicro.com>
+ *
+ */
+
+#define pr_fmt(fmt)	"ACPI: RIMT: " fmt
+
+#include <linux/acpi.h>
+#include <linux/acpi_rimt.h>
+#include <linux/iommu.h>
+#include <linux/list.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+#include "init.h"
+
+struct rimt_fwnode {
+	struct list_head list;
+	struct acpi_rimt_node *rimt_node;
+	struct fwnode_handle *fwnode;
+};
+
+static LIST_HEAD(rimt_fwnode_list);
+static DEFINE_SPINLOCK(rimt_fwnode_lock);
+
+#define RIMT_TYPE_MASK(type)	(1 << (type))
+#define RIMT_IOMMU_TYPE		BIT(0)
+
+/* Root pointer to the mapped RIMT table */
+static struct acpi_table_header *rimt_table;
+
+/**
+ * rimt_set_fwnode() - Create rimt_fwnode and use it to register
+ *		       iommu data in the rimt_fwnode_list
+ *
+ * @rimt_node: RIMT table node associated with the IOMMU
+ * @fwnode: fwnode associated with the RIMT node
+ *
+ * Returns: 0 on success
+ *          <0 on failure
+ */
+static int rimt_set_fwnode(struct acpi_rimt_node *rimt_node,
+			   struct fwnode_handle *fwnode)
+{
+	struct rimt_fwnode *np;
+
+	np = kzalloc(sizeof(*np), GFP_ATOMIC);
+
+	if (WARN_ON(!np))
+		return -ENOMEM;
+
+	INIT_LIST_HEAD(&np->list);
+	np->rimt_node = rimt_node;
+	np->fwnode = fwnode;
+
+	spin_lock(&rimt_fwnode_lock);
+	list_add_tail(&np->list, &rimt_fwnode_list);
+	spin_unlock(&rimt_fwnode_lock);
+
+	return 0;
+}
+
+static acpi_status rimt_match_node_callback(struct acpi_rimt_node *node,
+					    void *context)
+{
+	acpi_status status = AE_NOT_FOUND;
+	struct device *dev = context;
+
+	if (node->type == ACPI_RIMT_NODE_TYPE_IOMMU) {
+		struct acpi_rimt_iommu *iommu_node = (struct acpi_rimt_iommu *)&node->node_data;
+
+		if (dev_is_pci(dev)) {
+			struct pci_dev *pdev;
+			u16 bdf;
+
+			pdev = to_pci_dev(dev);
+			bdf = PCI_DEVID(pdev->bus->number, pdev->devfn);
+			if ((pci_domain_nr(pdev->bus) == iommu_node->pcie_segment_number) &&
+			    bdf == iommu_node->pcie_bdf) {
+				status = AE_OK;
+			} else {
+				status = AE_NOT_FOUND;
+			}
+		} else {
+			struct platform_device *pdev = to_platform_device(dev);
+			struct resource *res;
+
+			res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+			if (res && res->start == iommu_node->base_address)
+				status = AE_OK;
+			else
+				status = AE_NOT_FOUND;
+		}
+	} else if (node->type == ACPI_RIMT_NODE_TYPE_PCIE_ROOT_COMPLEX) {
+		struct acpi_rimt_pcie_rc *pci_rc;
+		struct pci_bus *bus;
+
+		bus = to_pci_bus(dev);
+		pci_rc = (struct acpi_rimt_pcie_rc *)node->node_data;
+
+		/*
+		 * It is assumed that PCI segment numbers maps one-to-one
+		 * with root complexes. Each segment number can represent only
+		 * one root complex.
+		 */
+		status = pci_rc->pcie_segment_number == pci_domain_nr(bus) ?
+							AE_OK : AE_NOT_FOUND;
+	} else if (node->type == ACPI_RIMT_NODE_TYPE_PLAT_DEVICE) {
+		struct acpi_buffer buf = { ACPI_ALLOCATE_BUFFER, NULL };
+		struct acpi_rimt_platform_device *ncomp;
+		struct device *plat_dev = dev;
+		struct acpi_device *adev;
+
+		/*
+		 * Walk the device tree to find a device with an
+		 * ACPI companion; there is no point in scanning
+		 * RIMT for a device matching a platform device if
+		 * the device does not have an ACPI companion to
+		 * start with.
+		 */
+		do {
+			adev = ACPI_COMPANION(plat_dev);
+			if (adev)
+				break;
+
+			plat_dev = plat_dev->parent;
+		} while (plat_dev);
+
+		if (!adev)
+			return status;
+
+		status = acpi_get_name(adev->handle, ACPI_FULL_PATHNAME, &buf);
+		if (ACPI_FAILURE(status)) {
+			dev_warn(plat_dev, "Can't get device full path name\n");
+			return status;
+		}
+
+		ncomp = (struct acpi_rimt_platform_device *)node->node_data;
+		status = !strcmp(ncomp->device_name, buf.pointer) ?
+							AE_OK : AE_NOT_FOUND;
+		acpi_os_free(buf.pointer);
+	}
+
+	return status;
+}
+
+static struct acpi_rimt_node *rimt_scan_node(enum acpi_rimt_node_type type,
+					     void *context)
+{
+	struct acpi_rimt_node *rimt_node, *rimt_end;
+	struct acpi_table_rimt *rimt;
+	int i;
+
+	if (!rimt_table)
+		return NULL;
+
+	/* Get the first RIMT node */
+	rimt = (struct acpi_table_rimt *)rimt_table;
+	rimt_node = ACPI_ADD_PTR(struct acpi_rimt_node, rimt,
+				 rimt->node_offset);
+	rimt_end = ACPI_ADD_PTR(struct acpi_rimt_node, rimt_table,
+				rimt_table->length);
+
+	for (i = 0; i < rimt->num_nodes; i++) {
+		if (WARN_TAINT(rimt_node >= rimt_end, TAINT_FIRMWARE_WORKAROUND,
+			       "RIMT node pointer overflows, bad table!\n"))
+			return NULL;
+
+		if (rimt_node->type == type &&
+		    ACPI_SUCCESS(rimt_match_node_callback(rimt_node, context)))
+			return rimt_node;
+
+		rimt_node = ACPI_ADD_PTR(struct acpi_rimt_node, rimt_node,
+					 rimt_node->length);
+	}
+
+	return NULL;
+}
+
+/*
+ * RISC-V supports IOMMU as a PCI device or a platform device.
+ * When it is a platform device, there should be a namespace device as
+ * well along with RIMT. To create the link between RIMT information and
+ * the platform device, the IOMMU driver should register itself with the
+ * RIMT module. This is true for PCI based IOMMU as well.
+ */
+int rimt_iommu_register(struct device *dev)
+{
+	struct fwnode_handle *rimt_fwnode;
+	struct acpi_rimt_node *node;
+
+	node = rimt_scan_node(ACPI_RIMT_NODE_TYPE_IOMMU, dev);
+	if (!node) {
+		pr_err("Could not find IOMMU node in RIMT\n");
+		return -ENODEV;
+	}
+
+	if (dev_is_pci(dev)) {
+		rimt_fwnode = acpi_alloc_fwnode_static();
+		if (!rimt_fwnode)
+			return -ENOMEM;
+
+		rimt_fwnode->dev = dev;
+		if (!dev->fwnode)
+			dev->fwnode = rimt_fwnode;
+
+		rimt_set_fwnode(node, rimt_fwnode);
+	} else {
+		rimt_set_fwnode(node, dev->fwnode);
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_IOMMU_API
+
+/**
+ * rimt_get_fwnode() - Retrieve fwnode associated with an RIMT node
+ *
+ * @node: RIMT table node to be looked-up
+ *
+ * Returns: fwnode_handle pointer on success, NULL on failure
+ */
+static struct fwnode_handle *rimt_get_fwnode(struct acpi_rimt_node *node)
+{
+	struct fwnode_handle *fwnode = NULL;
+	struct rimt_fwnode *curr;
+
+	spin_lock(&rimt_fwnode_lock);
+	list_for_each_entry(curr, &rimt_fwnode_list, list) {
+		if (curr->rimt_node == node) {
+			fwnode = curr->fwnode;
+			break;
+		}
+	}
+	spin_unlock(&rimt_fwnode_lock);
+
+	return fwnode;
+}
+
+static bool rimt_pcie_rc_supports_ats(struct acpi_rimt_node *node)
+{
+	struct acpi_rimt_pcie_rc *pci_rc;
+
+	pci_rc = (struct acpi_rimt_pcie_rc *)node->node_data;
+	return pci_rc->flags & ACPI_RIMT_PCIE_ATS_SUPPORTED;
+}
+
+static int rimt_iommu_xlate(struct device *dev, struct acpi_rimt_node *node, u32 deviceid)
+{
+	struct fwnode_handle *rimt_fwnode;
+
+	if (!node)
+		return -ENODEV;
+
+	rimt_fwnode = rimt_get_fwnode(node);
+
+	/*
+	 * The IOMMU drivers may not be probed yet.
+	 * Defer the IOMMU configuration
+	 */
+	if (!rimt_fwnode)
+		return -EPROBE_DEFER;
+
+	return acpi_iommu_fwspec_init(dev, deviceid, rimt_fwnode);
+}
+
+struct rimt_pci_alias_info {
+	struct device *dev;
+	struct acpi_rimt_node *node;
+	const struct iommu_ops *ops;
+};
+
+static int rimt_id_map(struct acpi_rimt_id_mapping *map, u8 type, u32 rid_in, u32 *rid_out)
+{
+	if (rid_in < map->source_id_base ||
+	    (rid_in > map->source_id_base + map->num_ids))
+		return -ENXIO;
+
+	*rid_out = map->dest_id_base + (rid_in - map->source_id_base);
+	return 0;
+}
+
+static struct acpi_rimt_node *rimt_node_get_id(struct acpi_rimt_node *node,
+					       u32 *id_out, int index)
+{
+	struct acpi_rimt_platform_device *plat_node;
+	u32 id_mapping_offset, num_id_mapping;
+	struct acpi_rimt_pcie_rc *pci_node;
+	struct acpi_rimt_id_mapping *map;
+	struct acpi_rimt_node *parent;
+
+	if (node->type == ACPI_RIMT_NODE_TYPE_PCIE_ROOT_COMPLEX) {
+		pci_node = (struct acpi_rimt_pcie_rc *)&node->node_data;
+		id_mapping_offset = pci_node->id_mapping_offset;
+		num_id_mapping = pci_node->num_id_mappings;
+	} else if (node->type == ACPI_RIMT_NODE_TYPE_PLAT_DEVICE) {
+		plat_node = (struct acpi_rimt_platform_device *)&node->node_data;
+		id_mapping_offset = plat_node->id_mapping_offset;
+		num_id_mapping = plat_node->num_id_mappings;
+	} else {
+		return NULL;
+	}
+
+	if (!id_mapping_offset || !num_id_mapping || index >= num_id_mapping)
+		return NULL;
+
+	map = ACPI_ADD_PTR(struct acpi_rimt_id_mapping, node,
+			   id_mapping_offset + index * sizeof(*map));
+
+	/* Firmware bug! */
+	if (!map->dest_offset) {
+		pr_err(FW_BUG "[node %p type %d] ID map has NULL parent reference\n",
+		       node, node->type);
+		return NULL;
+	}
+
+	parent = ACPI_ADD_PTR(struct acpi_rimt_node, rimt_table, map->dest_offset);
+
+	if (node->type == ACPI_RIMT_NODE_TYPE_PLAT_DEVICE ||
+	    node->type == ACPI_RIMT_NODE_TYPE_PCIE_ROOT_COMPLEX) {
+		*id_out = map->dest_id_base;
+		return parent;
+	}
+
+	return NULL;
+}
+
+static struct acpi_rimt_node *rimt_node_map_id(struct acpi_rimt_node *node,
+					       u32 id_in, u32 *id_out,
+					       u8 type_mask)
+{
+	struct acpi_rimt_platform_device *plat_node;
+	u32 id_mapping_offset, num_id_mapping;
+	struct acpi_rimt_pcie_rc *pci_node;
+	u32 id = id_in;
+
+	/* Parse the ID mapping tree to find specified node type */
+	while (node) {
+		struct acpi_rimt_id_mapping *map;
+		int i, rc = 0;
+		u32 map_id = id;
+
+		if (RIMT_TYPE_MASK(node->type) & type_mask) {
+			if (id_out)
+				*id_out = id;
+			return node;
+		}
+
+		if (node->type == ACPI_RIMT_NODE_TYPE_PCIE_ROOT_COMPLEX) {
+			pci_node = (struct acpi_rimt_pcie_rc *)&node->node_data;
+			id_mapping_offset = pci_node->id_mapping_offset;
+			num_id_mapping = pci_node->num_id_mappings;
+		} else if (node->type == ACPI_RIMT_NODE_TYPE_PLAT_DEVICE) {
+			plat_node = (struct acpi_rimt_platform_device *)&node->node_data;
+			id_mapping_offset = plat_node->id_mapping_offset;
+			num_id_mapping = plat_node->num_id_mappings;
+		} else {
+			goto fail_map;
+		}
+
+		if (!id_mapping_offset || !num_id_mapping)
+			goto fail_map;
+
+		map = ACPI_ADD_PTR(struct acpi_rimt_id_mapping, node,
+				   id_mapping_offset);
+
+		/* Firmware bug! */
+		if (!map->dest_offset) {
+			pr_err(FW_BUG "[node %p type %d] ID map has NULL parent reference\n",
+			       node, node->type);
+			goto fail_map;
+		}
+
+		/* Do the ID translation */
+		for (i = 0; i < num_id_mapping; i++, map++) {
+			rc = rimt_id_map(map, node->type, map_id, &id);
+			if (!rc)
+				break;
+		}
+
+		if (i == num_id_mapping)
+			goto fail_map;
+
+		node = ACPI_ADD_PTR(struct acpi_rimt_node, rimt_table,
+				    rc ? 0 : map->dest_offset);
+	}
+
+fail_map:
+	/* Map input ID to output ID unchanged on mapping failure */
+	if (id_out)
+		*id_out = id_in;
+
+	return NULL;
+}
+
+static struct acpi_rimt_node *rimt_node_map_platform_id(struct acpi_rimt_node *node, u32 *id_out,
+							u8 type_mask, int index)
+{
+	struct acpi_rimt_node *parent;
+	u32 id;
+
+	parent = rimt_node_get_id(node, &id, index);
+	if (!parent)
+		return NULL;
+
+	if (!(RIMT_TYPE_MASK(parent->type) & type_mask))
+		parent = rimt_node_map_id(parent, id, id_out, type_mask);
+	else
+		if (id_out)
+			*id_out = id;
+
+	return parent;
+}
+
+static int rimt_pci_iommu_init(struct pci_dev *pdev, u16 alias, void *data)
+{
+	struct rimt_pci_alias_info *info = data;
+	struct acpi_rimt_node *parent;
+	u32 deviceid;
+
+	parent = rimt_node_map_id(info->node, alias, &deviceid, RIMT_IOMMU_TYPE);
+	return rimt_iommu_xlate(info->dev, parent, deviceid);
+}
+
+static int rimt_plat_iommu_map(struct device *dev, struct acpi_rimt_node *node)
+{
+	struct acpi_rimt_node *parent;
+	int err = -ENODEV, i = 0;
+	u32 deviceid = 0;
+
+	do {
+		parent = rimt_node_map_platform_id(node, &deviceid,
+						   RIMT_IOMMU_TYPE,
+						   i++);
+
+		if (parent)
+			err = rimt_iommu_xlate(dev, parent, deviceid);
+	} while (parent && !err);
+
+	return err;
+}
+
+static int rimt_plat_iommu_map_id(struct device *dev,
+				  struct acpi_rimt_node *node,
+				  const u32 *in_id)
+{
+	struct acpi_rimt_node *parent;
+	u32 deviceid;
+
+	parent = rimt_node_map_id(node, *in_id, &deviceid, RIMT_IOMMU_TYPE);
+	if (parent)
+		return rimt_iommu_xlate(dev, parent, deviceid);
+
+	return -ENODEV;
+}
+
+/**
+ * rimt_iommu_configure_id - Set-up IOMMU configuration for a device.
+ *
+ * @dev: device to configure
+ * @id_in: optional input id const value pointer
+ *
+ * Returns: 0 on success, <0 on failure
+ */
+int rimt_iommu_configure_id(struct device *dev, const u32 *id_in)
+{
+	struct acpi_rimt_node *node;
+	int err = -ENODEV;
+
+	if (dev_is_pci(dev)) {
+		struct iommu_fwspec *fwspec;
+		struct pci_bus *bus = to_pci_dev(dev)->bus;
+		struct rimt_pci_alias_info info = { .dev = dev };
+
+		node = rimt_scan_node(ACPI_RIMT_NODE_TYPE_PCIE_ROOT_COMPLEX, &bus->dev);
+		if (!node)
+			return -ENODEV;
+
+		info.node = node;
+		err = pci_for_each_dma_alias(to_pci_dev(dev),
+					     rimt_pci_iommu_init, &info);
+
+		fwspec = dev_iommu_fwspec_get(dev);
+		if (fwspec && rimt_pcie_rc_supports_ats(node))
+			fwspec->flags |= IOMMU_FWSPEC_PCI_RC_ATS;
+	} else {
+		node = rimt_scan_node(ACPI_RIMT_NODE_TYPE_PLAT_DEVICE, dev);
+		if (!node)
+			return -ENODEV;
+
+		err = id_in ? rimt_plat_iommu_map_id(dev, node, id_in) :
+			      rimt_plat_iommu_map(dev, node);
+	}
+
+	return err;
+}
+
+#endif
+
+void __init riscv_acpi_rimt_init(void)
+{
+	acpi_status status;
+
+	/* rimt_table will be used at runtime after the rimt init,
+	 * so we don't need to call acpi_put_table() to release
+	 * the RIMT table mapping.
+	 */
+	status = acpi_get_table(ACPI_SIG_RIMT, 0, &rimt_table);
+	if (ACPI_FAILURE(status)) {
+		if (status != AE_NOT_FOUND) {
+			const char *msg = acpi_format_exception(status);
+
+			pr_err("Failed to get table, %s\n", msg);
+		}
+
+		return;
+	}
+}
diff --git a/drivers/acpi/sbs.c b/drivers/acpi/sbs.c
index 6e88224f60f0..d3edc3bcbf01 100644
--- a/drivers/acpi/sbs.c
+++ b/drivers/acpi/sbs.c
@@ -7,6 +7,8 @@
  *  Copyright (c) 2005 Rich Townsend <rhdt@bartol.udel.edu>
  */
 
+#define pr_fmt(fmt) "ACPI: " fmt
+
 #include <linux/init.h>
 #include <linux/slab.h>
 #include <linux/module.h>
@@ -23,14 +25,9 @@
 
 #include "sbshc.h"
 
-#define PREFIX "ACPI: "
-
 #define ACPI_SBS_CLASS			"sbs"
 #define ACPI_AC_CLASS			"ac_adapter"
 #define ACPI_SBS_DEVICE_NAME		"Smart Battery System"
-#define ACPI_SBS_FILE_INFO		"info"
-#define ACPI_SBS_FILE_STATE		"state"
-#define ACPI_SBS_FILE_ALARM		"alarm"
 #define ACPI_BATTERY_DIR_NAME		"BAT%i"
 #define ACPI_AC_DIR_NAME		"AC0"
 
@@ -80,7 +77,6 @@ struct acpi_battery {
 	u16 spec;
 	u8 id;
 	u8 present:1;
-	u8 have_sysfs_alarm:1;
 };
 
 #define to_acpi_battery(x) power_supply_get_drvdata(x)
@@ -99,7 +95,7 @@ struct acpi_sbs {
 
 #define to_acpi_sbs(x) power_supply_get_drvdata(x)
 
-static int acpi_sbs_remove(struct acpi_device *device);
+static void acpi_sbs_remove(struct acpi_device *device);
 static int acpi_battery_get_state(struct acpi_battery *battery);
 
 static inline int battery_scale(int log)
@@ -244,11 +240,11 @@ static int acpi_sbs_battery_get_property(struct power_supply *psy,
 	return 0;
 }
 
-static enum power_supply_property sbs_ac_props[] = {
+static const enum power_supply_property sbs_ac_props[] = {
 	POWER_SUPPLY_PROP_ONLINE,
 };
 
-static enum power_supply_property sbs_charge_battery_props[] = {
+static const enum power_supply_property sbs_charge_battery_props[] = {
 	POWER_SUPPLY_PROP_STATUS,
 	POWER_SUPPLY_PROP_PRESENT,
 	POWER_SUPPLY_PROP_TECHNOLOGY,
@@ -266,7 +262,7 @@ static enum power_supply_property sbs_charge_battery_props[] = {
 	POWER_SUPPLY_PROP_MANUFACTURER,
 };
 
-static enum power_supply_property sbs_energy_battery_props[] = {
+static const enum power_supply_property sbs_energy_battery_props[] = {
 	POWER_SUPPLY_PROP_STATUS,
 	POWER_SUPPLY_PROP_PRESENT,
 	POWER_SUPPLY_PROP_TECHNOLOGY,
@@ -369,7 +365,7 @@ static int acpi_battery_get_state(struct acpi_battery *battery)
 					 state_readers[i].mode,
 					 ACPI_SBS_BATTERY,
 					 state_readers[i].command,
-				         (u8 *)battery +
+					 (u8 *)battery +
 						state_readers[i].offset);
 		if (result)
 			goto end;
@@ -465,34 +461,49 @@ static ssize_t acpi_battery_alarm_store(struct device *dev,
 	return count;
 }
 
-static const struct device_attribute alarm_attr = {
+static struct device_attribute alarm_attr = {
 	.attr = {.name = "alarm", .mode = 0644},
 	.show = acpi_battery_alarm_show,
 	.store = acpi_battery_alarm_store,
 };
 
+static struct attribute *acpi_battery_attrs[] = {
+	&alarm_attr.attr,
+	NULL
+};
+ATTRIBUTE_GROUPS(acpi_battery);
+
 /* --------------------------------------------------------------------------
                                  Driver Interface
    -------------------------------------------------------------------------- */
 static int acpi_battery_read(struct acpi_battery *battery)
 {
-	int result = 0, saved_present = battery->present;
+	int result, saved_present = battery->present;
 	u16 state;
 
 	if (battery->sbs->manager_present) {
 		result = acpi_smbus_read(battery->sbs->hc, SMBUS_READ_WORD,
 				ACPI_SBS_MANAGER, 0x01, (u8 *)&state);
-		if (!result)
-			battery->present = state & (1 << battery->id);
-		state &= 0x0fff;
+		if (result)
+			return result;
+
+		battery->present = !!(state & (1 << battery->id));
+		if (!battery->present)
+			return 0;
+
+		/* Masking necessary for Smart Battery Selectors */
+		state = 0x0fff;
 		state |= 1 << (battery->id + 12);
 		acpi_smbus_write(battery->sbs->hc, SMBUS_WRITE_WORD,
 				  ACPI_SBS_MANAGER, 0x01, (u8 *)&state, 2);
-	} else if (battery->id == 0)
-		battery->present = 1;
-
-	if (result || !battery->present)
-		return result;
+	} else {
+		if (battery->id == 0) {
+			battery->present = 1;
+		} else {
+			if (!battery->present)
+				return 0;
+		}
+	}
 
 	if (saved_present != battery->present) {
 		battery->update_time = 0;
@@ -512,7 +523,10 @@ static int acpi_battery_read(struct acpi_battery *battery)
 static int acpi_battery_add(struct acpi_sbs *sbs, int id)
 {
 	struct acpi_battery *battery = &sbs->battery[id];
-	struct power_supply_config psy_cfg = { .drv_data = battery, };
+	struct power_supply_config psy_cfg = {
+		.drv_data = battery,
+		.attr_grp = acpi_battery_groups,
+	};
 	int result;
 
 	battery->id = id;
@@ -542,12 +556,8 @@ static int acpi_battery_add(struct acpi_sbs *sbs, int id)
 		goto end;
 	}
 
-	result = device_create_file(&battery->bat->dev, &alarm_attr);
-	if (result)
-		goto end;
-	battery->have_sysfs_alarm = 1;
       end:
-	printk(KERN_INFO PREFIX "%s [%s]: Battery Slot [%s] (battery %s)\n",
+	pr_info("%s [%s]: Battery Slot [%s] (battery %s)\n",
 	       ACPI_SBS_DEVICE_NAME, acpi_device_bid(sbs->device),
 	       battery->name, battery->present ? "present" : "absent");
 	return result;
@@ -557,11 +567,8 @@ static void acpi_battery_remove(struct acpi_sbs *sbs, int id)
 {
 	struct acpi_battery *battery = &sbs->battery[id];
 
-	if (battery->bat) {
-		if (battery->have_sysfs_alarm)
-			device_remove_file(&battery->bat->dev, &alarm_attr);
+	if (battery->bat)
 		power_supply_unregister(battery->bat);
-	}
 }
 
 static int acpi_charger_add(struct acpi_sbs *sbs)
@@ -580,10 +587,10 @@ static int acpi_charger_add(struct acpi_sbs *sbs)
 		result = PTR_ERR(sbs->charger);
 		sbs->charger = NULL;
 	}
-	printk(KERN_INFO PREFIX "%s [%s]: AC Adapter [%s] (%s)\n",
+	pr_info("%s [%s]: AC Adapter [%s] (%s)\n",
 	       ACPI_SBS_DEVICE_NAME, acpi_device_bid(sbs->device),
 	       ACPI_AC_DIR_NAME, sbs->charger_present ? "on-line" : "off-line");
-      end:
+end:
 	return result;
 }
 
@@ -604,7 +611,7 @@ static void acpi_sbs_callback(void *context)
 	if (sbs->charger_exists) {
 		acpi_ac_get_present(sbs);
 		if (sbs->charger_present != saved_charger_state)
-			kobject_uevent(&sbs->charger->dev.kobj, KOBJ_CHANGE);
+			power_supply_changed(sbs->charger);
 	}
 
 	if (sbs->manager_present) {
@@ -616,7 +623,7 @@ static void acpi_sbs_callback(void *context)
 			acpi_battery_read(bat);
 			if (saved_battery_state == bat->present)
 				continue;
-			kobject_uevent(&bat->bat->dev.kobj, KOBJ_CHANGE);
+			power_supply_changed(bat->bat);
 		}
 	}
 }
@@ -635,10 +642,10 @@ static int acpi_sbs_add(struct acpi_device *device)
 
 	mutex_init(&sbs->lock);
 
-	sbs->hc = acpi_driver_data(device->parent);
+	sbs->hc = acpi_driver_data(acpi_dev_parent(device));
 	sbs->device = device;
-	strcpy(acpi_device_name(device), ACPI_SBS_DEVICE_NAME);
-	strcpy(acpi_device_class(device), ACPI_SBS_CLASS);
+	strscpy(acpi_device_name(device), ACPI_SBS_DEVICE_NAME);
+	strscpy(acpi_device_class(device), ACPI_SBS_CLASS);
 	device->driver_data = sbs;
 
 	result = acpi_charger_add(sbs);
@@ -661,22 +668,22 @@ static int acpi_sbs_add(struct acpi_device *device)
 		acpi_battery_add(sbs, 0);
 
 	acpi_smbus_register_callback(sbs->hc, acpi_sbs_callback, sbs);
-      end:
+end:
 	if (result)
 		acpi_sbs_remove(device);
 	return result;
 }
 
-static int acpi_sbs_remove(struct acpi_device *device)
+static void acpi_sbs_remove(struct acpi_device *device)
 {
 	struct acpi_sbs *sbs;
 	int id;
 
 	if (!device)
-		return -EINVAL;
+		return;
 	sbs = acpi_driver_data(device);
 	if (!sbs)
-		return -EINVAL;
+		return;
 	mutex_lock(&sbs->lock);
 	acpi_smbus_unregister_callback(sbs->hc);
 	for (id = 0; id < MAX_SBS_BAT; ++id)
@@ -685,7 +692,6 @@ static int acpi_sbs_remove(struct acpi_device *device)
 	mutex_unlock(&sbs->lock);
 	mutex_destroy(&sbs->lock);
 	kfree(sbs);
-	return 0;
 }
 
 #ifdef CONFIG_PM_SLEEP
@@ -714,26 +720,4 @@ static struct acpi_driver acpi_sbs_driver = {
 		},
 	.drv.pm = &acpi_sbs_pm,
 };
-
-static int __init acpi_sbs_init(void)
-{
-	int result = 0;
-
-	if (acpi_disabled)
-		return -ENODEV;
-
-	result = acpi_bus_register_driver(&acpi_sbs_driver);
-	if (result < 0)
-		return -ENODEV;
-
-	return 0;
-}
-
-static void __exit acpi_sbs_exit(void)
-{
-	acpi_bus_unregister_driver(&acpi_sbs_driver);
-	return;
-}
-
-module_init(acpi_sbs_init);
-module_exit(acpi_sbs_exit);
+module_acpi_driver(acpi_sbs_driver);
diff --git a/drivers/acpi/sbshc.c b/drivers/acpi/sbshc.c
index 87b74e9015e5..1a2bf520be23 100644
--- a/drivers/acpi/sbshc.c
+++ b/drivers/acpi/sbshc.c
@@ -5,6 +5,8 @@
  * Copyright (c) 2007 Alexey Starikovskiy
  */
 
+#define pr_fmt(fmt) "ACPI: " fmt
+
 #include <linux/acpi.h>
 #include <linux/wait.h>
 #include <linux/slab.h>
@@ -12,8 +14,7 @@
 #include <linux/module.h>
 #include <linux/interrupt.h>
 #include "sbshc.h"
-
-#define PREFIX "ACPI: "
+#include "internal.h"
 
 #define ACPI_SMB_HC_CLASS	"smbus_host_ctl"
 #define ACPI_SMB_HC_DEVICE_NAME	"ACPI SMBus HC"
@@ -30,7 +31,7 @@ struct acpi_smb_hc {
 };
 
 static int acpi_smbus_hc_add(struct acpi_device *device);
-static int acpi_smbus_hc_remove(struct acpi_device *device);
+static void acpi_smbus_hc_remove(struct acpi_device *device);
 
 static const struct acpi_device_id sbs_device_ids[] = {
 	{"ACPI0001", 0},
@@ -109,7 +110,7 @@ static int acpi_smbus_transaction(struct acpi_smb_hc *hc, u8 protocol,
 	u8 temp, sz = 0;
 
 	if (!hc) {
-		printk(KERN_ERR PREFIX "host controller is not configured\n");
+		pr_err("host controller is not configured\n");
 		return ret;
 	}
 
@@ -176,7 +177,7 @@ int acpi_smbus_write(struct acpi_smb_hc *hc, u8 protocol, u8 address,
 EXPORT_SYMBOL_GPL(acpi_smbus_write);
 
 int acpi_smbus_register_callback(struct acpi_smb_hc *hc,
-			         smbus_alarm_callback callback, void *context)
+				 smbus_alarm_callback callback, void *context)
 {
 	mutex_lock(&hc->lock);
 	hc->callback = callback;
@@ -231,18 +232,11 @@ static int smbus_alarm(void *context)
 		case ACPI_SBS_BATTERY:
 			acpi_os_execute(OSL_NOTIFY_HANDLER,
 					acpi_smbus_callback, hc);
-		default:;
 	}
 	mutex_unlock(&hc->lock);
 	return 0;
 }
 
-typedef int (*acpi_ec_query_func) (void *data);
-
-extern int acpi_ec_add_query_handler(struct acpi_ec *ec, u8 query_bit,
-			      acpi_handle handle, acpi_ec_query_func func,
-			      void *data);
-
 static int acpi_smbus_hc_add(struct acpi_device *device)
 {
 	int status;
@@ -254,12 +248,12 @@ static int acpi_smbus_hc_add(struct acpi_device *device)
 
 	status = acpi_evaluate_integer(device->handle, "_EC", NULL, &val);
 	if (ACPI_FAILURE(status)) {
-		printk(KERN_ERR PREFIX "error obtaining _EC.\n");
+		pr_err("error obtaining _EC.\n");
 		return -EIO;
 	}
 
-	strcpy(acpi_device_name(device), ACPI_SMB_HC_DEVICE_NAME);
-	strcpy(acpi_device_class(device), ACPI_SMB_HC_CLASS);
+	strscpy(acpi_device_name(device), ACPI_SMB_HC_DEVICE_NAME);
+	strscpy(acpi_device_class(device), ACPI_SMB_HC_CLASS);
 
 	hc = kzalloc(sizeof(struct acpi_smb_hc), GFP_KERNEL);
 	if (!hc)
@@ -267,7 +261,7 @@ static int acpi_smbus_hc_add(struct acpi_device *device)
 	mutex_init(&hc->lock);
 	init_waitqueue_head(&hc->wait);
 
-	hc->ec = acpi_driver_data(device->parent);
+	hc->ec = acpi_driver_data(acpi_dev_parent(device));
 	hc->offset = (val >> 8) & 0xff;
 	hc->query_bit = val & 0xff;
 	device->driver_data = hc;
@@ -279,21 +273,18 @@ static int acpi_smbus_hc_add(struct acpi_device *device)
 	return 0;
 }
 
-extern void acpi_ec_remove_query_handler(struct acpi_ec *ec, u8 query_bit);
-
-static int acpi_smbus_hc_remove(struct acpi_device *device)
+static void acpi_smbus_hc_remove(struct acpi_device *device)
 {
 	struct acpi_smb_hc *hc;
 
 	if (!device)
-		return -EINVAL;
+		return;
 
 	hc = acpi_driver_data(device);
 	acpi_ec_remove_query_handler(hc->ec, hc->query_bit);
 	acpi_os_wait_events_complete();
 	kfree(hc);
 	device->driver_data = NULL;
-	return 0;
 }
 
 module_acpi_driver(acpi_smb_hc_driver);
diff --git a/drivers/acpi/sbshc.h b/drivers/acpi/sbshc.h
index c3522bb82792..695c390e2884 100644
--- a/drivers/acpi/sbshc.h
+++ b/drivers/acpi/sbshc.h
@@ -24,9 +24,9 @@ enum acpi_sbs_device_addr {
 typedef void (*smbus_alarm_callback)(void *context);
 
 extern int acpi_smbus_read(struct acpi_smb_hc *hc, u8 protocol, u8 address,
-	       u8 command, u8 * data);
+		u8 command, u8 *data);
 extern int acpi_smbus_write(struct acpi_smb_hc *hc, u8 protocol, u8 slave_address,
-		u8 command, u8 * data, u8 length);
+		u8 command, u8 *data, u8 length);
 extern int acpi_smbus_register_callback(struct acpi_smb_hc *hc,
-			         smbus_alarm_callback callback, void *context);
+		smbus_alarm_callback callback, void *context);
 extern int acpi_smbus_unregister_callback(struct acpi_smb_hc *hc);
diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c
index 6d3448895382..416d87f9bd10 100644
--- a/drivers/acpi/scan.c
+++ b/drivers/acpi/scan.c
@@ -3,34 +3,34 @@
  * scan.c - support for transforming the ACPI namespace into individual objects
  */
 
+#define pr_fmt(fmt) "ACPI: " fmt
+
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/slab.h>
 #include <linux/kernel.h>
 #include <linux/acpi.h>
 #include <linux/acpi_iort.h>
+#include <linux/acpi_rimt.h>
+#include <linux/acpi_viot.h>
+#include <linux/iommu.h>
 #include <linux/signal.h>
 #include <linux/kthread.h>
 #include <linux/dmi.h>
-#include <linux/nls.h>
-#include <linux/dma-mapping.h>
+#include <linux/dma-map-ops.h>
 #include <linux/platform_data/x86/apple.h>
-
-#include <asm/pgtable.h>
+#include <linux/pgtable.h>
+#include <linux/crc32.h>
+#include <linux/dma-direct.h>
 
 #include "internal.h"
-
-#define _COMPONENT		ACPI_BUS_COMPONENT
-ACPI_MODULE_NAME("scan");
-extern struct acpi_device *acpi_root;
+#include "sleep.h"
 
 #define ACPI_BUS_CLASS			"system_bus"
 #define ACPI_BUS_HID			"LNXSYBUS"
 #define ACPI_BUS_DEVICE_NAME		"System Bus"
 
-#define ACPI_IS_ROOT_DEVICE(device)    (!(device)->parent)
-
-#define INVALID_ACPI_HANDLE	((acpi_handle)empty_zero_page)
+#define INVALID_ACPI_HANDLE	((acpi_handle)ZERO_PAGE(0))
 
 static const char *dummy_hid = "device";
 
@@ -50,12 +50,6 @@ static DEFINE_MUTEX(acpi_hp_context_lock);
  */
 static u64 spcr_uart_addr;
 
-struct acpi_dep_data {
-	struct list_head node;
-	acpi_handle master;
-	acpi_handle slave;
-};
-
 void acpi_scan_lock_acquire(void)
 {
 	mutex_lock(&acpi_scan_lock);
@@ -80,8 +74,7 @@ void acpi_unlock_hp_context(void)
 
 void acpi_initialize_hp_context(struct acpi_device *adev,
 				struct acpi_hotplug_context *hp,
-				int (*notify)(struct acpi_device *, u32),
-				void (*uevent)(struct acpi_device *, u32))
+				acpi_hp_notify notify, acpi_hp_uevent uevent)
 {
 	acpi_lock_hp_context();
 	hp->notify = notify;
@@ -141,12 +134,12 @@ bool acpi_scan_is_offline(struct acpi_device *adev, bool uevent)
 static acpi_status acpi_bus_offline(acpi_handle handle, u32 lvl, void *data,
 				    void **ret_p)
 {
-	struct acpi_device *device = NULL;
+	struct acpi_device *device = acpi_fetch_acpi_dev(handle);
 	struct acpi_device_physical_node *pn;
 	bool second_pass = (bool)data;
 	acpi_status status = AE_OK;
 
-	if (acpi_bus_get_device(handle, &device))
+	if (!device)
 		return AE_OK;
 
 	if (device->handler && !device->handler->hotplug.enabled) {
@@ -186,10 +179,10 @@ static acpi_status acpi_bus_offline(acpi_handle handle, u32 lvl, void *data,
 static acpi_status acpi_bus_online(acpi_handle handle, u32 lvl, void *data,
 				   void **ret_p)
 {
-	struct acpi_device *device = NULL;
+	struct acpi_device *device = acpi_fetch_acpi_dev(handle);
 	struct acpi_device_physical_node *pn;
 
-	if (acpi_bus_get_device(handle, &device))
+	if (!device)
 		return AE_OK;
 
 	mutex_lock(&device->physical_node_lock);
@@ -251,11 +244,85 @@ static int acpi_scan_try_to_offline(struct acpi_device *device)
 	return 0;
 }
 
+#define ACPI_SCAN_CHECK_FLAG_STATUS	BIT(0)
+#define ACPI_SCAN_CHECK_FLAG_EJECT	BIT(1)
+
+static int acpi_scan_check_and_detach(struct acpi_device *adev, void *p)
+{
+	struct acpi_scan_handler *handler = adev->handler;
+	uintptr_t flags = (uintptr_t)p;
+
+	acpi_dev_for_each_child_reverse(adev, acpi_scan_check_and_detach, p);
+
+	if (flags & ACPI_SCAN_CHECK_FLAG_STATUS) {
+		acpi_bus_get_status(adev);
+		/*
+		 * Skip devices that are still there and take the enabled
+		 * flag into account.
+		 */
+		if (acpi_device_is_enabled(adev))
+			return 0;
+
+		/* Skip device that have not been enumerated. */
+		if (!acpi_device_enumerated(adev)) {
+			dev_dbg(&adev->dev, "Still not enumerated\n");
+			return 0;
+		}
+	}
+
+	adev->flags.match_driver = false;
+	if (handler) {
+		if (handler->detach)
+			handler->detach(adev);
+	} else {
+		device_release_driver(&adev->dev);
+	}
+	/*
+	 * Most likely, the device is going away, so put it into D3cold before
+	 * that.
+	 */
+	acpi_device_set_power(adev, ACPI_STATE_D3_COLD);
+	adev->flags.initialized = false;
+
+	/* For eject this is deferred to acpi_bus_post_eject() */
+	if (!(flags & ACPI_SCAN_CHECK_FLAG_EJECT)) {
+		adev->handler = NULL;
+		acpi_device_clear_enumerated(adev);
+	}
+	return 0;
+}
+
+static int acpi_bus_post_eject(struct acpi_device *adev, void *not_used)
+{
+	struct acpi_scan_handler *handler = adev->handler;
+
+	acpi_dev_for_each_child_reverse(adev, acpi_bus_post_eject, NULL);
+
+	if (handler) {
+		if (handler->post_eject)
+			handler->post_eject(adev);
+
+		adev->handler = NULL;
+	}
+
+	acpi_device_clear_enumerated(adev);
+
+	return 0;
+}
+
+static void acpi_scan_check_subtree(struct acpi_device *adev)
+{
+	uintptr_t flags = ACPI_SCAN_CHECK_FLAG_STATUS;
+
+	acpi_scan_check_and_detach(adev, (void *)flags);
+}
+
 static int acpi_scan_hot_remove(struct acpi_device *device)
 {
 	acpi_handle handle = device->handle;
 	unsigned long long sta;
 	acpi_status status;
+	uintptr_t flags = ACPI_SCAN_CHECK_FLAG_EJECT;
 
 	if (device->handler && device->handler->hotplug.demand_offline) {
 		if (!acpi_scan_is_offline(device, true))
@@ -266,10 +333,9 @@ static int acpi_scan_hot_remove(struct acpi_device *device)
 			return error;
 	}
 
-	ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-		"Hot-removing device %s...\n", dev_name(&device->dev)));
+	acpi_handle_debug(handle, "Ejecting\n");
 
-	acpi_bus_trim(device);
+	acpi_scan_check_and_detach(device, (void *)flags);
 
 	acpi_evaluate_lck(handle, 0);
 	/*
@@ -292,79 +358,62 @@ static int acpi_scan_hot_remove(struct acpi_device *device)
 	} else if (sta & ACPI_STA_DEVICE_ENABLED) {
 		acpi_handle_warn(handle,
 			"Eject incomplete - status 0x%llx\n", sta);
+	} else {
+		acpi_bus_post_eject(device, NULL);
 	}
 
 	return 0;
 }
 
-static int acpi_scan_device_not_present(struct acpi_device *adev)
+static int acpi_scan_rescan_bus(struct acpi_device *adev)
 {
-	if (!acpi_device_enumerated(adev)) {
-		dev_warn(&adev->dev, "Still not present\n");
-		return -EALREADY;
-	}
-	acpi_bus_trim(adev);
-	return 0;
+	struct acpi_scan_handler *handler = adev->handler;
+	int ret;
+
+	if (handler && handler->hotplug.scan_dependent)
+		ret = handler->hotplug.scan_dependent(adev);
+	else
+		ret = acpi_bus_scan(adev->handle);
+
+	if (ret)
+		dev_info(&adev->dev, "Namespace scan failure\n");
+
+	return ret;
 }
 
 static int acpi_scan_device_check(struct acpi_device *adev)
 {
-	int error;
+	struct acpi_device *parent;
 
-	acpi_bus_get_status(adev);
-	if (adev->status.present || adev->status.functional) {
-		/*
-		 * This function is only called for device objects for which
-		 * matching scan handlers exist.  The only situation in which
-		 * the scan handler is not attached to this device object yet
-		 * is when the device has just appeared (either it wasn't
-		 * present at all before or it was removed and then added
-		 * again).
-		 */
-		if (adev->handler) {
-			dev_warn(&adev->dev, "Already enumerated\n");
-			return -EALREADY;
-		}
-		error = acpi_bus_scan(adev->handle);
-		if (error) {
-			dev_warn(&adev->dev, "Namespace scan failure\n");
-			return error;
-		}
-		if (!adev->handler) {
-			dev_warn(&adev->dev, "Enumeration failure\n");
-			error = -ENODEV;
-		}
-	} else {
-		error = acpi_scan_device_not_present(adev);
+	acpi_scan_check_subtree(adev);
+
+	if (!acpi_device_is_present(adev))
+		return 0;
+
+	/*
+	 * This function is only called for device objects for which matching
+	 * scan handlers exist.  The only situation in which the scan handler
+	 * is not attached to this device object yet is when the device has
+	 * just appeared (either it wasn't present at all before or it was
+	 * removed and then added again).
+	 */
+	if (adev->handler) {
+		dev_dbg(&adev->dev, "Already enumerated\n");
+		return 0;
 	}
-	return error;
+
+	parent = acpi_dev_parent(adev);
+	if (!parent)
+		parent = adev;
+
+	return acpi_scan_rescan_bus(parent);
 }
 
 static int acpi_scan_bus_check(struct acpi_device *adev)
 {
-	struct acpi_scan_handler *handler = adev->handler;
-	struct acpi_device *child;
-	int error;
+	acpi_scan_check_subtree(adev);
 
-	acpi_bus_get_status(adev);
-	if (!(adev->status.present || adev->status.functional)) {
-		acpi_scan_device_not_present(adev);
-		return 0;
-	}
-	if (handler && handler->hotplug.scan_dependent)
-		return handler->hotplug.scan_dependent(adev);
-
-	error = acpi_bus_scan(adev->handle);
-	if (error) {
-		dev_warn(&adev->dev, "Namespace scan failure\n");
-		return error;
-	}
-	list_for_each_entry(child, &adev->children, node) {
-		error = acpi_scan_bus_check(child);
-		if (error)
-			return error;
-	}
-	return 0;
+	return acpi_scan_rescan_bus(adev);
 }
 
 static int acpi_generic_hotplug_event(struct acpi_device *adev, u32 type)
@@ -408,7 +457,7 @@ void acpi_device_hotplug(struct acpi_device *adev, u32 src)
 	} else if (adev->flags.hotplug_notify) {
 		error = acpi_generic_hotplug_event(adev, src);
 	} else {
-		int (*notify)(struct acpi_device *, u32);
+		acpi_hp_notify notify;
 
 		acpi_lock_hp_context();
 		notify = adev->hp ? adev->hp->notify : NULL;
@@ -441,7 +490,7 @@ void acpi_device_hotplug(struct acpi_device *adev, u32 src)
 	acpi_evaluate_ost(adev->handle, src, ost_code, NULL);
 
  out:
-	acpi_bus_put_acpi_device(adev);
+	acpi_put_acpi_dev(adev);
 	mutex_unlock(&acpi_scan_lock);
 	unlock_device_hotplug();
 }
@@ -477,22 +526,22 @@ static void acpi_device_del(struct acpi_device *device)
 	struct acpi_device_bus_id *acpi_device_bus_id;
 
 	mutex_lock(&acpi_device_lock);
-	if (device->parent)
-		list_del(&device->node);
 
 	list_for_each_entry(acpi_device_bus_id, &acpi_bus_id_list, node)
 		if (!strcmp(acpi_device_bus_id->bus_id,
 			    acpi_device_hid(device))) {
-			if (acpi_device_bus_id->instance_no > 0)
-				acpi_device_bus_id->instance_no--;
-			else {
+			ida_free(&acpi_device_bus_id->instance_ida,
+				 device->pnp.instance_no);
+			if (ida_is_empty(&acpi_device_bus_id->instance_ida)) {
 				list_del(&acpi_device_bus_id->node);
+				kfree_const(acpi_device_bus_id->bus_id);
 				kfree(acpi_device_bus_id);
 			}
 			break;
 		}
 
 	list_del(&device->wakeup_list);
+
 	mutex_unlock(&acpi_device_lock);
 
 	acpi_power_add_remove_device(device, false);
@@ -534,7 +583,7 @@ static void acpi_device_del_work_fn(struct work_struct *work_not_used)
 		 * used by the device.
 		 */
 		acpi_power_transition(adev, ACPI_STATE_D3_COLD);
-		put_device(&adev->dev);
+		acpi_dev_put(adev);
 	}
 }
 
@@ -564,7 +613,7 @@ static void acpi_scan_drop_device(acpi_handle handle, void *context)
 	 * prevents attempts to register device objects identical to those being
 	 * deleted from happening concurrently (such attempts result from
 	 * hotplug events handled via the ACPI hotplug workqueue).  It also will
-	 * run after all of the work items submitted previosuly, which helps
+	 * run after all of the work items submitted previously, which helps
 	 * those work items to ensure that they are not accessing stale device
 	 * objects.
 	 */
@@ -578,152 +627,249 @@ static void acpi_scan_drop_device(acpi_handle handle, void *context)
 	mutex_unlock(&acpi_device_del_lock);
 }
 
-static int acpi_get_device_data(acpi_handle handle, struct acpi_device **device,
-				void (*callback)(void *))
+static struct acpi_device *handle_to_device(acpi_handle handle,
+					    void (*callback)(void *))
 {
+	struct acpi_device *adev = NULL;
 	acpi_status status;
 
-	if (!device)
-		return -EINVAL;
-
 	status = acpi_get_data_full(handle, acpi_scan_drop_device,
-				    (void **)device, callback);
-	if (ACPI_FAILURE(status) || !*device) {
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No context for object [%p]\n",
-				  handle));
-		return -ENODEV;
+				    (void **)&adev, callback);
+	if (ACPI_FAILURE(status) || !adev) {
+		acpi_handle_debug(handle, "No context!\n");
+		return NULL;
 	}
-	return 0;
+	return adev;
 }
 
-int acpi_bus_get_device(acpi_handle handle, struct acpi_device **device)
+/**
+ * acpi_fetch_acpi_dev - Retrieve ACPI device object.
+ * @handle: ACPI handle associated with the requested ACPI device object.
+ *
+ * Return a pointer to the ACPI device object associated with @handle, if
+ * present, or NULL otherwise.
+ */
+struct acpi_device *acpi_fetch_acpi_dev(acpi_handle handle)
 {
-	return acpi_get_device_data(handle, device, NULL);
+	return handle_to_device(handle, NULL);
 }
-EXPORT_SYMBOL(acpi_bus_get_device);
+EXPORT_SYMBOL_GPL(acpi_fetch_acpi_dev);
 
 static void get_acpi_device(void *dev)
 {
-	if (dev)
-		get_device(&((struct acpi_device *)dev)->dev);
+	acpi_dev_get(dev);
 }
 
-struct acpi_device *acpi_bus_get_acpi_device(acpi_handle handle)
+/**
+ * acpi_get_acpi_dev - Retrieve ACPI device object and reference count it.
+ * @handle: ACPI handle associated with the requested ACPI device object.
+ *
+ * Return a pointer to the ACPI device object associated with @handle and bump
+ * up that object's reference counter (under the ACPI Namespace lock), if
+ * present, or return NULL otherwise.
+ *
+ * The ACPI device object reference acquired by this function needs to be
+ * dropped via acpi_dev_put().
+ */
+struct acpi_device *acpi_get_acpi_dev(acpi_handle handle)
 {
-	struct acpi_device *adev = NULL;
-
-	acpi_get_device_data(handle, &adev, get_acpi_device);
-	return adev;
+	return handle_to_device(handle, get_acpi_device);
 }
+EXPORT_SYMBOL_GPL(acpi_get_acpi_dev);
 
-void acpi_bus_put_acpi_device(struct acpi_device *adev)
+static struct acpi_device_bus_id *acpi_device_bus_id_match(const char *dev_id)
 {
-	put_device(&adev->dev);
+	struct acpi_device_bus_id *acpi_device_bus_id;
+
+	/* Find suitable bus_id and instance number in acpi_bus_id_list. */
+	list_for_each_entry(acpi_device_bus_id, &acpi_bus_id_list, node) {
+		if (!strcmp(acpi_device_bus_id->bus_id, dev_id))
+			return acpi_device_bus_id;
+	}
+	return NULL;
 }
 
-int acpi_device_add(struct acpi_device *device,
-		    void (*release)(struct device *))
+static int acpi_device_set_name(struct acpi_device *device,
+				struct acpi_device_bus_id *acpi_device_bus_id)
 {
+	struct ida *instance_ida = &acpi_device_bus_id->instance_ida;
 	int result;
-	struct acpi_device_bus_id *acpi_device_bus_id, *new_bus_id;
-	int found = 0;
 
-	if (device->handle) {
-		acpi_status status;
+	result = ida_alloc(instance_ida, GFP_KERNEL);
+	if (result < 0)
+		return result;
 
-		status = acpi_attach_data(device->handle, acpi_scan_drop_device,
-					  device);
-		if (ACPI_FAILURE(status)) {
-			acpi_handle_err(device->handle,
-					"Unable to attach device data\n");
-			return -ENODEV;
-		}
+	device->pnp.instance_no = result;
+	dev_set_name(&device->dev, "%s:%02x", acpi_device_bus_id->bus_id, result);
+	return 0;
+}
+
+int acpi_tie_acpi_dev(struct acpi_device *adev)
+{
+	acpi_handle handle = adev->handle;
+	acpi_status status;
+
+	if (!handle)
+		return 0;
+
+	status = acpi_attach_data(handle, acpi_scan_drop_device, adev);
+	if (ACPI_FAILURE(status)) {
+		acpi_handle_err(handle, "Unable to attach device data\n");
+		return -ENODEV;
 	}
 
+	return 0;
+}
+
+static void acpi_store_pld_crc(struct acpi_device *adev)
+{
+	struct acpi_pld_info *pld;
+
+	if (!acpi_get_physical_device_location(adev->handle, &pld))
+		return;
+
+	adev->pld_crc = crc32(~0, pld, sizeof(*pld));
+	ACPI_FREE(pld);
+}
+
+int acpi_device_add(struct acpi_device *device)
+{
+	struct acpi_device_bus_id *acpi_device_bus_id;
+	int result;
+
 	/*
 	 * Linkage
 	 * -------
 	 * Link this device to its parent and siblings.
 	 */
-	INIT_LIST_HEAD(&device->children);
-	INIT_LIST_HEAD(&device->node);
 	INIT_LIST_HEAD(&device->wakeup_list);
 	INIT_LIST_HEAD(&device->physical_node_list);
 	INIT_LIST_HEAD(&device->del_list);
 	mutex_init(&device->physical_node_lock);
 
-	new_bus_id = kzalloc(sizeof(struct acpi_device_bus_id), GFP_KERNEL);
-	if (!new_bus_id) {
-		pr_err(PREFIX "Memory allocation error\n");
-		result = -ENOMEM;
-		goto err_detach;
-	}
-
 	mutex_lock(&acpi_device_lock);
-	/*
-	 * Find suitable bus_id and instance number in acpi_bus_id_list
-	 * If failed, create one and link it into acpi_bus_id_list
-	 */
-	list_for_each_entry(acpi_device_bus_id, &acpi_bus_id_list, node) {
-		if (!strcmp(acpi_device_bus_id->bus_id,
-			    acpi_device_hid(device))) {
-			acpi_device_bus_id->instance_no++;
-			found = 1;
-			kfree(new_bus_id);
-			break;
+
+	acpi_device_bus_id = acpi_device_bus_id_match(acpi_device_hid(device));
+	if (acpi_device_bus_id) {
+		result = acpi_device_set_name(device, acpi_device_bus_id);
+		if (result)
+			goto err_unlock;
+	} else {
+		acpi_device_bus_id = kzalloc(sizeof(*acpi_device_bus_id),
+					     GFP_KERNEL);
+		if (!acpi_device_bus_id) {
+			result = -ENOMEM;
+			goto err_unlock;
 		}
-	}
-	if (!found) {
-		acpi_device_bus_id = new_bus_id;
-		strcpy(acpi_device_bus_id->bus_id, acpi_device_hid(device));
-		acpi_device_bus_id->instance_no = 0;
+		acpi_device_bus_id->bus_id =
+			kstrdup_const(acpi_device_hid(device), GFP_KERNEL);
+		if (!acpi_device_bus_id->bus_id) {
+			kfree(acpi_device_bus_id);
+			result = -ENOMEM;
+			goto err_unlock;
+		}
+
+		ida_init(&acpi_device_bus_id->instance_ida);
+
+		result = acpi_device_set_name(device, acpi_device_bus_id);
+		if (result) {
+			kfree_const(acpi_device_bus_id->bus_id);
+			kfree(acpi_device_bus_id);
+			goto err_unlock;
+		}
+
 		list_add_tail(&acpi_device_bus_id->node, &acpi_bus_id_list);
 	}
-	dev_set_name(&device->dev, "%s:%02x", acpi_device_bus_id->bus_id, acpi_device_bus_id->instance_no);
-
-	if (device->parent)
-		list_add_tail(&device->node, &device->parent->children);
 
 	if (device->wakeup.flags.valid)
 		list_add_tail(&device->wakeup_list, &acpi_wakeup_device_list);
+
+	acpi_store_pld_crc(device);
+
 	mutex_unlock(&acpi_device_lock);
 
-	if (device->parent)
-		device->dev.parent = &device->parent->dev;
-	device->dev.bus = &acpi_bus_type;
-	device->dev.release = release;
 	result = device_add(&device->dev);
 	if (result) {
 		dev_err(&device->dev, "Error registering device\n");
 		goto err;
 	}
 
-	result = acpi_device_setup_files(device);
-	if (result)
-		printk(KERN_ERR PREFIX "Error creating sysfs interface for device %s\n",
-		       dev_name(&device->dev));
+	acpi_device_setup_files(device);
 
 	return 0;
 
- err:
+err:
 	mutex_lock(&acpi_device_lock);
-	if (device->parent)
-		list_del(&device->node);
+
 	list_del(&device->wakeup_list);
+
+err_unlock:
 	mutex_unlock(&acpi_device_lock);
 
- err_detach:
 	acpi_detach_data(device->handle, acpi_scan_drop_device);
+
 	return result;
 }
 
 /* --------------------------------------------------------------------------
                                  Device Enumeration
    -------------------------------------------------------------------------- */
-static struct acpi_device *acpi_bus_get_parent(acpi_handle handle)
+static bool acpi_info_matches_ids(struct acpi_device_info *info,
+				  const char * const ids[])
 {
-	struct acpi_device *device = NULL;
-	acpi_status status;
+	struct acpi_pnp_device_id_list *cid_list = NULL;
+	int i, index;
+
+	if (!(info->valid & ACPI_VALID_HID))
+		return false;
+
+	index = match_string(ids, -1, info->hardware_id.string);
+	if (index >= 0)
+		return true;
+
+	if (info->valid & ACPI_VALID_CID)
+		cid_list = &info->compatible_id_list;
+
+	if (!cid_list)
+		return false;
+
+	for (i = 0; i < cid_list->count; i++) {
+		index = match_string(ids, -1, cid_list->ids[i].string);
+		if (index >= 0)
+			return true;
+	}
+
+	return false;
+}
+
+/* List of HIDs for which we ignore matching ACPI devices, when checking _DEP lists. */
+static const char * const acpi_ignore_dep_ids[] = {
+	"PNP0D80", /* Windows-compatible System Power Management Controller */
+	"INT33BD", /* Intel Baytrail Mailbox Device */
+	"INTC10DE", /* Intel CVS LNL */
+	"INTC10E0", /* Intel CVS ARL */
+	"LATT2021", /* Lattice FW Update Client Driver */
+	NULL
+};
+
+/* List of HIDs for which we honor deps of matching ACPI devs, when checking _DEP lists. */
+static const char * const acpi_honor_dep_ids[] = {
+	"INT3472", /* Camera sensor PMIC / clk and regulator info */
+	"INTC1059", /* IVSC (TGL) driver must be loaded to allow i2c access to camera sensors */
+	"INTC1095", /* IVSC (ADL) driver must be loaded to allow i2c access to camera sensors */
+	"INTC100A", /* IVSC (RPL) driver must be loaded to allow i2c access to camera sensors */
+	"INTC10CF", /* IVSC (MTL) driver must be loaded to allow i2c access to camera sensors */
+	"RSCV0001", /* RISC-V PLIC */
+	"RSCV0002", /* RISC-V APLIC */
+	"RSCV0005", /* RISC-V SBI MPXY MBOX */
+	"RSCV0006", /* RISC-V RPMI SYSMSI */
+	"PNP0C0F",  /* PCI Link Device */
+	NULL
+};
+
+static struct acpi_device *acpi_find_parent_acpi_dev(acpi_handle handle)
+{
+	struct acpi_device *adev;
 
 	/*
 	 * Fixed hardware devices do not appear in the namespace and do not
@@ -734,11 +880,18 @@ static struct acpi_device *acpi_bus_get_parent(acpi_handle handle)
 		return acpi_root;
 
 	do {
+		acpi_status status;
+
 		status = acpi_get_parent(handle, &handle);
-		if (ACPI_FAILURE(status))
-			return status == AE_NULL_ENTRY ? NULL : acpi_root;
-	} while (acpi_bus_get_device(handle, &device));
-	return device;
+		if (ACPI_FAILURE(status)) {
+			if (status != AE_NULL_ENTRY)
+				return acpi_root;
+
+			return NULL;
+		}
+		adev = acpi_fetch_acpi_dev(handle);
+	} while (!adev);
+	return adev;
 }
 
 acpi_status
@@ -779,7 +932,8 @@ static int acpi_bus_extract_wakeup_device_power_package(struct acpi_device *dev)
 	/* _PRW */
 	status = acpi_evaluate_object(handle, "_PRW", NULL, &buffer);
 	if (ACPI_FAILURE(status)) {
-		ACPI_EXCEPTION((AE_INFO, status, "Evaluating _PRW"));
+		acpi_handle_info(handle, "_PRW evaluation failed: %s\n",
+				 acpi_format_exception(status));
 		return err;
 	}
 
@@ -844,26 +998,29 @@ static int acpi_bus_extract_wakeup_device_power_package(struct acpi_device *dev)
 	return err;
 }
 
+/* Do not use a button for S5 wakeup */
+#define ACPI_AVOID_WAKE_FROM_S5		BIT(0)
+
 static bool acpi_wakeup_gpe_init(struct acpi_device *device)
 {
 	static const struct acpi_device_id button_device_ids[] = {
-		{"PNP0C0C", 0},		/* Power button */
-		{"PNP0C0D", 0},		/* Lid */
-		{"PNP0C0E", 0},		/* Sleep button */
+		{"PNP0C0C", 0},				/* Power button */
+		{"PNP0C0D", ACPI_AVOID_WAKE_FROM_S5},	/* Lid */
+		{"PNP0C0E", ACPI_AVOID_WAKE_FROM_S5},	/* Sleep button */
 		{"", 0},
 	};
 	struct acpi_device_wakeup *wakeup = &device->wakeup;
+	const struct acpi_device_id *match;
 	acpi_status status;
 
 	wakeup->flags.notifier_present = 0;
 
 	/* Power button, Lid switch always enable wakeup */
-	if (!acpi_match_device_ids(device, button_device_ids)) {
-		if (!acpi_match_device_ids(device, &button_device_ids[1])) {
-			/* Do not use Lid/sleep button for S5 wakeup */
-			if (wakeup->sleep_state == ACPI_STATE_S5)
-				wakeup->sleep_state = ACPI_STATE_S4;
-		}
+	match = acpi_match_acpi_device(button_device_ids, device);
+	if (match) {
+		if ((match->driver_data & ACPI_AVOID_WAKE_FROM_S5) &&
+		    wakeup->sleep_state == ACPI_STATE_S5)
+			wakeup->sleep_state = ACPI_STATE_S4;
 		acpi_mark_gpe_for_wake(wakeup->gpe_device, wakeup->gpe_number);
 		device_set_wakeup_capable(&device->dev, true);
 		return true;
@@ -884,7 +1041,7 @@ static void acpi_bus_get_wakeup_device_flags(struct acpi_device *device)
 
 	err = acpi_bus_extract_wakeup_device_power_package(device);
 	if (err) {
-		dev_err(&device->dev, "_PRW evaluation error: %d\n", err);
+		dev_err(&device->dev, "Unable to extract wakeup power resources");
 		return;
 	}
 
@@ -899,8 +1056,7 @@ static void acpi_bus_get_wakeup_device_flags(struct acpi_device *device)
 	 */
 	err = acpi_device_sleep_wake(device, 0, 0, 0);
 	if (err)
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-				"error in _DSW or _PSW evaluation\n"));
+		pr_debug("error in _DSW or _PSW evaluation\n");
 }
 
 static void acpi_bus_init_power_state(struct acpi_device *device, int state)
@@ -919,12 +1075,9 @@ static void acpi_bus_init_power_state(struct acpi_device *device, int state)
 
 		if (buffer.length && package
 		    && package->type == ACPI_TYPE_PACKAGE
-		    && package->package.count) {
-			int err = acpi_extract_power_resources(package, 0,
-							       &ps->resources);
-			if (!err)
-				device->power.flags.power_resources = 1;
-		}
+		    && package->package.count)
+			acpi_extract_power_resources(package, 0, &ps->resources);
+
 		ACPI_FREE(buffer.pointer);
 	}
 
@@ -943,6 +1096,7 @@ static void acpi_bus_init_power_state(struct acpi_device *device, int state)
 
 static void acpi_bus_get_power_flags(struct acpi_device *device)
 {
+	unsigned long long dsc = ACPI_STATE_D0;
 	u32 i;
 
 	/* Presence of _PS0|_PR0 indicates 'power manageable' */
@@ -964,6 +1118,9 @@ static void acpi_bus_get_power_flags(struct acpi_device *device)
 	if (acpi_has_method(device->handle, "_DSW"))
 		device->power.flags.dsw_present = 1;
 
+	acpi_evaluate_integer(device->handle, "_DSC", NULL, &dsc);
+	device->power.state_for_enumeration = dsc;
+
 	/*
 	 * Enumerate supported power management states
 	 */
@@ -971,14 +1128,27 @@ static void acpi_bus_get_power_flags(struct acpi_device *device)
 		acpi_bus_init_power_state(device, i);
 
 	INIT_LIST_HEAD(&device->power.states[ACPI_STATE_D3_COLD].resources);
-	if (!list_empty(&device->power.states[ACPI_STATE_D3_HOT].resources))
-		device->power.states[ACPI_STATE_D3_COLD].flags.valid = 1;
 
-	/* Set defaults for D0 and D3hot states (always valid) */
+	/* Set the defaults for D0 and D3hot (always supported). */
 	device->power.states[ACPI_STATE_D0].flags.valid = 1;
 	device->power.states[ACPI_STATE_D0].power = 100;
 	device->power.states[ACPI_STATE_D3_HOT].flags.valid = 1;
 
+	/*
+	 * Use power resources only if the D0 list of them is populated, because
+	 * some platforms may provide _PR3 only to indicate D3cold support and
+	 * in those cases the power resources list returned by it may be bogus.
+	 */
+	if (!list_empty(&device->power.states[ACPI_STATE_D0].resources)) {
+		device->power.flags.power_resources = 1;
+		/*
+		 * D3cold is supported if the D3hot list of power resources is
+		 * not empty.
+		 */
+		if (!list_empty(&device->power.states[ACPI_STATE_D3_HOT].resources))
+			device->power.states[ACPI_STATE_D3_COLD].flags.valid = 1;
+	}
+
 	if (acpi_bus_init_power(device))
 		device->flags.power_manageable = 0;
 }
@@ -1011,20 +1181,20 @@ static void acpi_device_get_busid(struct acpi_device *device)
 	 * The device's Bus ID is simply the object name.
 	 * TBD: Shouldn't this value be unique (within the ACPI namespace)?
 	 */
-	if (ACPI_IS_ROOT_DEVICE(device)) {
-		strcpy(device->pnp.bus_id, "ACPI");
+	if (!acpi_dev_parent(device)) {
+		strscpy(device->pnp.bus_id, "ACPI");
 		return;
 	}
 
 	switch (device->device_type) {
 	case ACPI_BUS_TYPE_POWER_BUTTON:
-		strcpy(device->pnp.bus_id, "PWRF");
+		strscpy(device->pnp.bus_id, "PWRF");
 		break;
 	case ACPI_BUS_TYPE_SLEEP_BUTTON:
-		strcpy(device->pnp.bus_id, "SLPF");
+		strscpy(device->pnp.bus_id, "SLPF");
 		break;
 	case ACPI_BUS_TYPE_ECDT_EC:
-		strcpy(device->pnp.bus_id, "ECDT");
+		strscpy(device->pnp.bus_id, "ECDT");
 		break;
 	default:
 		acpi_get_name(device->handle, ACPI_SINGLE_NAME, &buffer);
@@ -1035,7 +1205,7 @@ static void acpi_device_get_busid(struct acpi_device *device)
 			else
 				break;
 		}
-		strcpy(device->pnp.bus_id, bus_id);
+		strscpy(device->pnp.bus_id, bus_id);
 		break;
 	}
 }
@@ -1111,8 +1281,7 @@ acpi_backlight_cap_match(acpi_handle handle, u32 level, void *context,
 
 	if (acpi_has_method(handle, "_BCM") &&
 	    acpi_has_method(handle, "_BCL")) {
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found generic backlight "
-				  "support\n"));
+		acpi_handle_debug(handle, "Found generic backlight support\n");
 		*cap |= ACPI_VIDEO_BACKLIGHT;
 		/* We have backlight support, no need to scan further */
 		return AE_CTRL_TERMINATE;
@@ -1160,10 +1329,10 @@ const char *acpi_device_hid(struct acpi_device *device)
 {
 	struct acpi_hardware_id *hid;
 
-	if (list_empty(&device->pnp.ids))
+	hid = list_first_entry_or_null(&device->pnp.ids, struct acpi_hardware_id, list);
+	if (!hid)
 		return dummy_hid;
 
-	hid = list_first_entry(&device->pnp.ids, struct acpi_hardware_id, list);
 	return hid->id;
 }
 EXPORT_SYMBOL(acpi_device_hid);
@@ -1228,10 +1397,9 @@ static bool acpi_object_is_system_bus(acpi_handle handle)
 }
 
 static void acpi_set_pnp_ids(acpi_handle handle, struct acpi_device_pnp *pnp,
-				int device_type)
+			     int device_type)
 {
-	acpi_status status;
-	struct acpi_device_info *info;
+	struct acpi_device_info *info = NULL;
 	struct acpi_pnp_device_id_list *cid_list;
 	int i;
 
@@ -1242,10 +1410,9 @@ static void acpi_set_pnp_ids(acpi_handle handle, struct acpi_device_pnp *pnp,
 			break;
 		}
 
-		status = acpi_get_object_info(handle, &info);
-		if (ACPI_FAILURE(status)) {
-			pr_err(PREFIX "%s: Error reading device info\n",
-					__func__);
+		acpi_get_object_info(handle, &info);
+		if (!info) {
+			pr_err("%s: Error reading device info\n", __func__);
 			return;
 		}
 
@@ -1274,9 +1441,12 @@ static void acpi_set_pnp_ids(acpi_handle handle, struct acpi_device_pnp *pnp,
 		 * Some devices don't reliably have _HIDs & _CIDs, so add
 		 * synthetic HIDs to make sure drivers can find them.
 		 */
-		if (acpi_is_video_device(handle))
+		if (acpi_is_video_device(handle)) {
 			acpi_add_id(pnp, ACPI_VIDEO_HID);
-		else if (acpi_bay_match(handle))
+			pnp->type.backlight = 1;
+			break;
+		}
+		if (acpi_bay_match(handle))
 			acpi_add_id(pnp, ACPI_BAY_HID);
 		else if (acpi_dock_match(handle))
 			acpi_add_id(pnp, ACPI_DOCK_HID);
@@ -1286,8 +1456,8 @@ static void acpi_set_pnp_ids(acpi_handle handle, struct acpi_device_pnp *pnp,
 			 acpi_object_is_system_bus(handle)) {
 			/* \_SB, \_TZ, LNXSYBUS */
 			acpi_add_id(pnp, ACPI_BUS_HID);
-			strcpy(pnp->device_name, ACPI_BUS_DEVICE_NAME);
-			strcpy(pnp->device_class, ACPI_BUS_CLASS);
+			strscpy(pnp->device_name, ACPI_BUS_DEVICE_NAME);
+			strscpy(pnp->device_class, ACPI_BUS_CLASS);
 		}
 
 		break;
@@ -1329,7 +1499,7 @@ void acpi_free_pnp_ids(struct acpi_device_pnp *pnp)
  *
  * Return false if DMA is not supported. Otherwise, return true
  */
-bool acpi_dma_supported(struct acpi_device *adev)
+bool acpi_dma_supported(const struct acpi_device *adev)
 {
 	if (!adev)
 		return false;
@@ -1369,25 +1539,21 @@ enum dev_dma_attr acpi_get_dma_attr(struct acpi_device *adev)
  * acpi_dma_get_range() - Get device DMA parameters.
  *
  * @dev: device to configure
- * @dma_addr: pointer device DMA address result
- * @offset: pointer to the DMA offset result
- * @size: pointer to DMA range size result
+ * @map: pointer to DMA ranges result
  *
- * Evaluate DMA regions and return respectively DMA region start, offset
- * and size in dma_addr, offset and size on parsing success; it does not
- * update the passed in values on failure.
+ * Evaluate DMA regions and return pointer to DMA regions on
+ * parsing success; it does not update the passed in values on failure.
  *
  * Return 0 on success, < 0 on failure.
  */
-int acpi_dma_get_range(struct device *dev, u64 *dma_addr, u64 *offset,
-		       u64 *size)
+int acpi_dma_get_range(struct device *dev, const struct bus_dma_region **map)
 {
 	struct acpi_device *adev;
 	LIST_HEAD(list);
 	struct resource_entry *rentry;
 	int ret;
 	struct device *dma_dev = dev;
-	u64 len, dma_start = U64_MAX, dma_end = 0, dma_offset = 0;
+	struct bus_dma_region *r;
 
 	/*
 	 * Walk the device tree chasing an ACPI companion with a _DMA
@@ -1412,31 +1578,28 @@ int acpi_dma_get_range(struct device *dev, u64 *dma_addr, u64 *offset,
 
 	ret = acpi_dev_get_dma_resources(adev, &list);
 	if (ret > 0) {
+		r = kcalloc(ret + 1, sizeof(*r), GFP_KERNEL);
+		if (!r) {
+			ret = -ENOMEM;
+			goto out;
+		}
+
+		*map = r;
+
 		list_for_each_entry(rentry, &list, node) {
-			if (dma_offset && rentry->offset != dma_offset) {
+			if (rentry->res->start >= rentry->res->end) {
+				kfree(*map);
+				*map = NULL;
 				ret = -EINVAL;
-				dev_warn(dma_dev, "Can't handle multiple windows with different offsets\n");
+				dev_dbg(dma_dev, "Invalid DMA regions configuration\n");
 				goto out;
 			}
-			dma_offset = rentry->offset;
 
-			/* Take lower and upper limits */
-			if (rentry->res->start < dma_start)
-				dma_start = rentry->res->start;
-			if (rentry->res->end > dma_end)
-				dma_end = rentry->res->end;
+			r->cpu_start = rentry->res->start;
+			r->dma_start = rentry->res->start - rentry->offset;
+			r->size = resource_size(rentry->res);
+			r++;
 		}
-
-		if (dma_start >= dma_end) {
-			ret = -EINVAL;
-			dev_dbg(dma_dev, "Invalid DMA regions configuration\n");
-			goto out;
-		}
-
-		*dma_addr = dma_start - dma_offset;
-		len = dma_end - dma_start;
-		*size = max(len, len + 1);
-		*offset = dma_offset;
 	}
  out:
 	acpi_dev_free_resource_list(&list);
@@ -1444,39 +1607,93 @@ int acpi_dma_get_range(struct device *dev, u64 *dma_addr, u64 *offset,
 	return ret >= 0 ? 0 : ret;
 }
 
+#ifdef CONFIG_IOMMU_API
+int acpi_iommu_fwspec_init(struct device *dev, u32 id,
+			   struct fwnode_handle *fwnode)
+{
+	int ret;
+
+	ret = iommu_fwspec_init(dev, fwnode);
+	if (ret)
+		return ret;
+
+	return iommu_fwspec_add_ids(dev, &id, 1);
+}
+
+static int acpi_iommu_configure_id(struct device *dev, const u32 *id_in)
+{
+	int err;
+
+	/* Serialise to make dev->iommu stable under our potential fwspec */
+	mutex_lock(&iommu_probe_device_lock);
+	/* If we already translated the fwspec there is nothing left to do */
+	if (dev_iommu_fwspec_get(dev)) {
+		mutex_unlock(&iommu_probe_device_lock);
+		return 0;
+	}
+
+	err = iort_iommu_configure_id(dev, id_in);
+	if (err && err != -EPROBE_DEFER)
+		err = rimt_iommu_configure_id(dev, id_in);
+	if (err && err != -EPROBE_DEFER)
+		err = viot_iommu_configure(dev);
+
+	mutex_unlock(&iommu_probe_device_lock);
+
+	return err;
+}
+
+#else /* !CONFIG_IOMMU_API */
+
+int acpi_iommu_fwspec_init(struct device *dev, u32 id,
+			   struct fwnode_handle *fwnode)
+{
+	return -ENODEV;
+}
+
+static int acpi_iommu_configure_id(struct device *dev, const u32 *id_in)
+{
+	return -ENODEV;
+}
+
+#endif /* !CONFIG_IOMMU_API */
+
 /**
- * acpi_dma_configure - Set-up DMA configuration for the device.
+ * acpi_dma_configure_id - Set-up DMA configuration for the device.
  * @dev: The pointer to the device
  * @attr: device dma attributes
+ * @input_id: input device id const value pointer
  */
-int acpi_dma_configure(struct device *dev, enum dev_dma_attr attr)
+int acpi_dma_configure_id(struct device *dev, enum dev_dma_attr attr,
+			  const u32 *input_id)
 {
-	const struct iommu_ops *iommu;
-	u64 dma_addr = 0, size = 0;
+	int ret;
 
 	if (attr == DEV_DMA_NOT_SUPPORTED) {
 		set_dma_ops(dev, &dma_dummy_ops);
 		return 0;
 	}
 
-	iort_dma_setup(dev, &dma_addr, &size);
+	acpi_arch_dma_setup(dev);
 
-	iommu = iort_iommu_configure(dev);
-	if (PTR_ERR(iommu) == -EPROBE_DEFER)
+	/* Ignore all other errors apart from EPROBE_DEFER */
+	ret = acpi_iommu_configure_id(dev, input_id);
+	if (ret == -EPROBE_DEFER)
 		return -EPROBE_DEFER;
+	if (ret)
+		dev_dbg(dev, "Adding to IOMMU failed: %d\n", ret);
 
-	arch_setup_dma_ops(dev, dma_addr, size,
-				iommu, attr == DEV_DMA_COHERENT);
+	arch_setup_dma_ops(dev, attr == DEV_DMA_COHERENT);
 
 	return 0;
 }
-EXPORT_SYMBOL_GPL(acpi_dma_configure);
+EXPORT_SYMBOL_GPL(acpi_dma_configure_id);
 
 static void acpi_init_coherency(struct acpi_device *adev)
 {
 	unsigned long long cca = 0;
 	acpi_status status;
-	struct acpi_device *parent = adev->parent;
+	struct acpi_device *parent = acpi_dev_parent(adev);
 
 	if (parent && parent->flags.cca_seen) {
 		/*
@@ -1520,7 +1737,7 @@ static int acpi_check_serial_bus_slave(struct acpi_resource *ares, void *data)
 
 static bool acpi_is_indirect_io_slave(struct acpi_device *device)
 {
-	struct acpi_device *parent = device->parent;
+	struct acpi_device *parent = acpi_dev_parent(device);
 	static const struct acpi_device_id indirect_io_hosts[] = {
 		{"HISI0191", 0},
 		{}
@@ -1533,19 +1750,42 @@ static bool acpi_device_enumeration_by_parent(struct acpi_device *device)
 {
 	struct list_head resource_list;
 	bool is_serial_bus_slave = false;
+	static const struct acpi_device_id ignore_serial_bus_ids[] = {
 	/*
-	 * These devices have multiple I2cSerialBus resources and an i2c-client
-	 * must be instantiated for each, each with its own i2c_device_id.
-	 * Normally we only instantiate an i2c-client for the first resource,
-	 * using the ACPI HID as id. These special cases are handled by the
-	 * drivers/platform/x86/i2c-multi-instantiate.c driver, which knows
-	 * which i2c_device_id to use for each resource.
+	 * These devices have multiple SerialBus resources and a client
+	 * device must be instantiated for each of them, each with
+	 * its own device id.
+	 * Normally we only instantiate one client device for the first
+	 * resource, using the ACPI HID as id. These special cases are handled
+	 * by the drivers/platform/x86/serial-multi-instantiate.c driver, which
+	 * knows which client device id to use for each resource.
 	 */
-	static const struct acpi_device_id i2c_multi_instantiate_ids[] = {
 		{"BSG1160", },
 		{"BSG2150", },
+		{"CSC3551", },
+		{"CSC3554", },
+		{"CSC3556", },
+		{"CSC3557", },
 		{"INT33FE", },
 		{"INT3515", },
+		{"TXNW2781", },
+		/* Non-conforming _HID for Cirrus Logic already released */
+		{"CLSA0100", },
+		{"CLSA0101", },
+	/*
+	 * Some ACPI devs contain SerialBus resources even though they are not
+	 * attached to a serial bus at all.
+	 */
+		{ACPI_VIDEO_HID, },
+		{"MSHW0028", },
+	/*
+	 * HIDs of device with an UartSerialBusV2 resource for which userspace
+	 * expects a regular tty cdev to be created (instead of the in kernel
+	 * serdev) and which have a kernel driver which expects a platform_dev
+	 * such as the rfkill-gpio driver.
+	 */
+		{"BCM4752", },
+		{"LNV4752", },
 		{}
 	};
 
@@ -1559,8 +1799,7 @@ static bool acpi_device_enumeration_by_parent(struct acpi_device *device)
 	     fwnode_property_present(&device->fwnode, "baud")))
 		return true;
 
-	/* Instantiate a pdev for the i2c-multi-instantiate drv to bind to */
-	if (!acpi_match_device_ids(device, i2c_multi_instantiate_ids))
+	if (!acpi_match_device_ids(device, ignore_serial_bus_ids))
 		return false;
 
 	INIT_LIST_HEAD(&resource_list);
@@ -1573,14 +1812,19 @@ static bool acpi_device_enumeration_by_parent(struct acpi_device *device)
 }
 
 void acpi_init_device_object(struct acpi_device *device, acpi_handle handle,
-			     int type, unsigned long long sta)
+			     int type, void (*release)(struct device *))
 {
+	struct acpi_device *parent = acpi_find_parent_acpi_dev(handle);
+
 	INIT_LIST_HEAD(&device->pnp.ids);
 	device->device_type = type;
 	device->handle = handle;
-	device->parent = acpi_bus_get_parent(handle);
-	device->fwnode.ops = &acpi_device_fwnode_ops;
-	acpi_set_device_status(device, sta);
+	device->dev.parent = parent ? &parent->dev : NULL;
+	device->dev.release = release;
+	device->dev.bus = &acpi_bus_type;
+	device->dev.groups = acpi_groups;
+	fwnode_init(&device->fwnode, &acpi_device_fwnode_ops);
+	acpi_set_device_status(device, ACPI_STA_DEFAULT);
 	acpi_device_get_busid(device);
 	acpi_set_pnp_ids(handle, &device->pnp, type);
 	acpi_init_properties(device);
@@ -1593,8 +1837,21 @@ void acpi_init_device_object(struct acpi_device *device, acpi_handle handle,
 	device_initialize(&device->dev);
 	dev_set_uevent_suppress(&device->dev, true);
 	acpi_init_coherency(device);
-	/* Assume there are unmet deps until acpi_device_dep_initialize() runs */
-	device->dep_unmet = 1;
+}
+
+static void acpi_scan_dep_init(struct acpi_device *adev)
+{
+	struct acpi_dep_data *dep;
+
+	list_for_each_entry(dep, &acpi_dep_list, node) {
+		if (dep->consumer == adev->handle) {
+			if (dep->honor_dep)
+				adev->flags.honor_deps = 1;
+
+			if (!dep->met)
+				adev->dep_unmet++;
+		}
+	}
 }
 
 void acpi_device_add_finalize(struct acpi_device *device)
@@ -1603,34 +1860,55 @@ void acpi_device_add_finalize(struct acpi_device *device)
 	kobject_uevent(&device->dev.kobj, KOBJ_ADD);
 }
 
+static void acpi_scan_init_status(struct acpi_device *adev)
+{
+	if (acpi_bus_get_status(adev))
+		acpi_set_device_status(adev, 0);
+}
+
 static int acpi_add_single_object(struct acpi_device **child,
-				  acpi_handle handle, int type,
-				  unsigned long long sta)
+				  acpi_handle handle, int type, bool dep_init)
 {
-	int result;
 	struct acpi_device *device;
-	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
+	bool release_dep_lock = false;
+	int result;
 
 	device = kzalloc(sizeof(struct acpi_device), GFP_KERNEL);
-	if (!device) {
-		printk(KERN_ERR PREFIX "Memory allocation error\n");
+	if (!device)
 		return -ENOMEM;
-	}
 
-	acpi_init_device_object(device, handle, type, sta);
+	acpi_init_device_object(device, handle, type, acpi_device_release);
 	/*
-	 * For ACPI_BUS_TYPE_DEVICE getting the status is delayed till here so
-	 * that we can call acpi_bus_get_status() and use its quirk handling.
-	 * Note this must be done before the get power-/wakeup_dev-flags calls.
+	 * Getting the status is delayed till here so that we can call
+	 * acpi_bus_get_status() and use its quirk handling.  Note that
+	 * this must be done before the get power-/wakeup_dev-flags calls.
 	 */
-	if (type == ACPI_BUS_TYPE_DEVICE)
-		if (acpi_bus_get_status(device) < 0)
-			acpi_set_device_status(device, 0);
+	if (type == ACPI_BUS_TYPE_DEVICE || type == ACPI_BUS_TYPE_PROCESSOR) {
+		if (dep_init) {
+			mutex_lock(&acpi_dep_list_lock);
+			/*
+			 * Hold the lock until the acpi_tie_acpi_dev() call
+			 * below to prevent concurrent acpi_scan_clear_dep()
+			 * from deleting a dependency list entry without
+			 * updating dep_unmet for the device.
+			 */
+			release_dep_lock = true;
+			acpi_scan_dep_init(device);
+		}
+		acpi_scan_init_status(device);
+	}
 
 	acpi_bus_get_power_flags(device);
 	acpi_bus_get_wakeup_device_flags(device);
 
-	result = acpi_device_add(device, acpi_device_release);
+	result = acpi_tie_acpi_dev(device);
+
+	if (release_dep_lock)
+		mutex_unlock(&acpi_dep_list_lock);
+
+	if (!result)
+		result = acpi_device_add(device);
+
 	if (result) {
 		acpi_device_release(&device->dev);
 		return result;
@@ -1638,11 +1916,11 @@ static int acpi_add_single_object(struct acpi_device **child,
 
 	acpi_power_add_remove_device(device, true);
 	acpi_device_add_finalize(device);
-	acpi_get_name(handle, ACPI_FULL_PATHNAME, &buffer);
-	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Added %s [%s] parent %s\n",
-		dev_name(&device->dev), (char *) buffer.pointer,
-		device->parent ? dev_name(&device->parent->dev) : "(null)"));
-	kfree(buffer.pointer);
+
+	acpi_handle_debug(handle, "Added as %s, parent %s\n",
+			  dev_name(&device->dev), device->dev.parent ?
+				dev_name(device->dev.parent) : "(null)");
+
 	*child = device;
 	return 0;
 }
@@ -1682,53 +1960,14 @@ static bool acpi_device_should_be_hidden(acpi_handle handle)
 	return true;
 }
 
-static int acpi_bus_type_and_status(acpi_handle handle, int *type,
-				    unsigned long long *sta)
+bool acpi_device_is_present(const struct acpi_device *adev)
 {
-	acpi_status status;
-	acpi_object_type acpi_type;
-
-	status = acpi_get_type(handle, &acpi_type);
-	if (ACPI_FAILURE(status))
-		return -ENODEV;
-
-	switch (acpi_type) {
-	case ACPI_TYPE_ANY:		/* for ACPI_ROOT_OBJECT */
-	case ACPI_TYPE_DEVICE:
-		if (acpi_device_should_be_hidden(handle))
-			return -ENODEV;
-
-		*type = ACPI_BUS_TYPE_DEVICE;
-		/*
-		 * acpi_add_single_object updates this once we've an acpi_device
-		 * so that acpi_bus_get_status' quirk handling can be used.
-		 */
-		*sta = ACPI_STA_DEFAULT;
-		break;
-	case ACPI_TYPE_PROCESSOR:
-		*type = ACPI_BUS_TYPE_PROCESSOR;
-		status = acpi_bus_get_status_handle(handle, sta);
-		if (ACPI_FAILURE(status))
-			return -ENODEV;
-		break;
-	case ACPI_TYPE_THERMAL:
-		*type = ACPI_BUS_TYPE_THERMAL;
-		*sta = ACPI_STA_DEFAULT;
-		break;
-	case ACPI_TYPE_POWER:
-		*type = ACPI_BUS_TYPE_POWER;
-		*sta = ACPI_STA_DEFAULT;
-		break;
-	default:
-		return -ENODEV;
-	}
-
-	return 0;
+	return adev->status.present || adev->status.functional;
 }
 
-bool acpi_device_is_present(const struct acpi_device *adev)
+bool acpi_device_is_enabled(const struct acpi_device *adev)
 {
-	return adev->status.present || adev->status.functional;
+	return adev->status.enabled;
 }
 
 static bool acpi_scan_handler_matching(struct acpi_scan_handler *handler,
@@ -1775,6 +2014,49 @@ void acpi_scan_hotplug_enabled(struct acpi_hotplug_profile *hotplug, bool val)
 	mutex_unlock(&acpi_scan_lock);
 }
 
+int acpi_scan_add_dep(acpi_handle handle, struct acpi_handle_list *dep_devices)
+{
+	u32 count;
+	int i;
+
+	for (count = 0, i = 0; i < dep_devices->count; i++) {
+		struct acpi_device_info *info;
+		struct acpi_dep_data *dep;
+		bool skip, honor_dep;
+		acpi_status status;
+
+		status = acpi_get_object_info(dep_devices->handles[i], &info);
+		if (ACPI_FAILURE(status)) {
+			acpi_handle_debug(handle, "Error reading _DEP device info\n");
+			continue;
+		}
+
+		skip = acpi_info_matches_ids(info, acpi_ignore_dep_ids);
+		honor_dep = acpi_info_matches_ids(info, acpi_honor_dep_ids);
+		kfree(info);
+
+		if (skip)
+			continue;
+
+		dep = kzalloc(sizeof(*dep), GFP_KERNEL);
+		if (!dep)
+			continue;
+
+		count++;
+
+		dep->supplier = dep_devices->handles[i];
+		dep->consumer = handle;
+		dep->honor_dep = honor_dep;
+
+		mutex_lock(&acpi_dep_list_lock);
+		list_add_tail(&dep->node, &acpi_dep_list);
+		mutex_unlock(&acpi_dep_list_lock);
+	}
+
+	acpi_handle_list_free(dep_devices);
+	return count;
+}
+
 static void acpi_scan_init_hotplug(struct acpi_device *adev)
 {
 	struct acpi_hardware_id *hwid;
@@ -1794,96 +2076,133 @@ static void acpi_scan_init_hotplug(struct acpi_device *adev)
 	}
 }
 
-static void acpi_device_dep_initialize(struct acpi_device *adev)
+u32 __weak arch_acpi_add_auto_dep(acpi_handle handle) { return 0; }
+
+static u32 acpi_scan_check_dep(acpi_handle handle)
 {
-	struct acpi_dep_data *dep;
 	struct acpi_handle_list dep_devices;
-	acpi_status status;
-	int i;
+	u32 count = 0;
 
-	adev->dep_unmet = 0;
+	/*
+	 * Some architectures like RISC-V need to add dependencies for
+	 * all devices which use GSI to the interrupt controller so that
+	 * interrupt controller is probed before any of those devices.
+	 * Instead of mandating _DEP on all the devices, detect the
+	 * dependency and add automatically.
+	 */
+	count += arch_acpi_add_auto_dep(handle);
 
-	if (!acpi_has_method(adev->handle, "_DEP"))
-		return;
+	/*
+	 * Check for _HID here to avoid deferring the enumeration of:
+	 * 1. PCI devices.
+	 * 2. ACPI nodes describing USB ports.
+	 * Still, checking for _HID catches more then just these cases ...
+	 */
+	if (!acpi_has_method(handle, "_DEP") || !acpi_has_method(handle, "_HID"))
+		return count;
 
-	status = acpi_evaluate_reference(adev->handle, "_DEP", NULL,
-					&dep_devices);
-	if (ACPI_FAILURE(status)) {
-		dev_dbg(&adev->dev, "Failed to evaluate _DEP.\n");
-		return;
+	if (!acpi_evaluate_reference(handle, "_DEP", NULL, &dep_devices)) {
+		acpi_handle_debug(handle, "Failed to evaluate _DEP.\n");
+		return count;
 	}
 
-	for (i = 0; i < dep_devices.count; i++) {
-		struct acpi_device_info *info;
-		int skip;
-
-		status = acpi_get_object_info(dep_devices.handles[i], &info);
-		if (ACPI_FAILURE(status)) {
-			dev_dbg(&adev->dev, "Error reading _DEP device info\n");
-			continue;
-		}
-
-		/*
-		 * Skip the dependency of Windows System Power
-		 * Management Controller
-		 */
-		skip = info->valid & ACPI_VALID_HID &&
-			!strcmp(info->hardware_id.string, "INT3396");
-
-		kfree(info);
-
-		if (skip)
-			continue;
-
-		dep = kzalloc(sizeof(struct acpi_dep_data), GFP_KERNEL);
-		if (!dep)
-			return;
-
-		dep->master = dep_devices.handles[i];
-		dep->slave  = adev->handle;
-		adev->dep_unmet++;
+	count += acpi_scan_add_dep(handle, &dep_devices);
+	return count;
+}
 
-		mutex_lock(&acpi_dep_list_lock);
-		list_add_tail(&dep->node , &acpi_dep_list);
-		mutex_unlock(&acpi_dep_list_lock);
-	}
+static acpi_status acpi_scan_check_crs_csi2_cb(acpi_handle handle, u32 a, void *b, void **c)
+{
+	acpi_mipi_check_crs_csi2(handle);
+	return AE_OK;
 }
 
-static acpi_status acpi_bus_check_add(acpi_handle handle, u32 lvl_not_used,
-				      void *not_used, void **return_value)
+static acpi_status acpi_bus_check_add(acpi_handle handle, bool first_pass,
+				      struct acpi_device **adev_p)
 {
-	struct acpi_device *device = NULL;
+	struct acpi_device *device = acpi_fetch_acpi_dev(handle);
+	acpi_object_type acpi_type;
 	int type;
-	unsigned long long sta;
-	int result;
 
-	acpi_bus_get_device(handle, &device);
 	if (device)
 		goto out;
 
-	result = acpi_bus_type_and_status(handle, &type, &sta);
-	if (result)
+	if (ACPI_FAILURE(acpi_get_type(handle, &acpi_type)))
 		return AE_OK;
 
-	if (type == ACPI_BUS_TYPE_POWER) {
+	switch (acpi_type) {
+	case ACPI_TYPE_DEVICE:
+		if (acpi_device_should_be_hidden(handle))
+			return AE_OK;
+
+		if (first_pass) {
+			acpi_mipi_check_crs_csi2(handle);
+
+			/* Bail out if there are dependencies. */
+			if (acpi_scan_check_dep(handle) > 0) {
+				/*
+				 * The entire CSI-2 connection graph needs to be
+				 * extracted before any drivers or scan handlers
+				 * are bound to struct device objects, so scan
+				 * _CRS CSI-2 resource descriptors for all
+				 * devices below the current handle.
+				 */
+				acpi_walk_namespace(ACPI_TYPE_DEVICE, handle,
+						    ACPI_UINT32_MAX,
+						    acpi_scan_check_crs_csi2_cb,
+						    NULL, NULL, NULL);
+				return AE_CTRL_DEPTH;
+			}
+		}
+
+		fallthrough;
+	case ACPI_TYPE_ANY:	/* for ACPI_ROOT_OBJECT */
+		type = ACPI_BUS_TYPE_DEVICE;
+		break;
+
+	case ACPI_TYPE_PROCESSOR:
+		type = ACPI_BUS_TYPE_PROCESSOR;
+		break;
+
+	case ACPI_TYPE_THERMAL:
+		type = ACPI_BUS_TYPE_THERMAL;
+		break;
+
+	case ACPI_TYPE_POWER:
 		acpi_add_power_resource(handle);
+		fallthrough;
+	default:
 		return AE_OK;
 	}
 
-	acpi_add_single_object(&device, handle, type, sta);
+	/*
+	 * If first_pass is true at this point, the device has no dependencies,
+	 * or the creation of the device object would have been postponed above.
+	 */
+	acpi_add_single_object(&device, handle, type, !first_pass);
 	if (!device)
 		return AE_CTRL_DEPTH;
 
 	acpi_scan_init_hotplug(device);
-	acpi_device_dep_initialize(device);
 
- out:
-	if (!*return_value)
-		*return_value = device;
+out:
+	if (!*adev_p)
+		*adev_p = device;
 
 	return AE_OK;
 }
 
+static acpi_status acpi_bus_check_add_1(acpi_handle handle, u32 lvl_not_used,
+					void *not_used, void **ret_p)
+{
+	return acpi_bus_check_add(handle, true, (struct acpi_device **)ret_p);
+}
+
+static acpi_status acpi_bus_check_add_2(acpi_handle handle, u32 lvl_not_used,
+					void *not_used, void **ret_p)
+{
+	return acpi_bus_check_add(handle, false, (struct acpi_device **)ret_p);
+}
+
 static void acpi_default_enumeration(struct acpi_device *device)
 {
 	/*
@@ -1951,26 +2270,31 @@ static int acpi_scan_attach_handler(struct acpi_device *device)
 	return ret;
 }
 
-static void acpi_bus_attach(struct acpi_device *device)
+static int acpi_bus_attach(struct acpi_device *device, void *first_pass)
 {
-	struct acpi_device *child;
+	bool skip = !first_pass && device->flags.visited;
 	acpi_handle ejd;
 	int ret;
 
+	if (skip)
+		goto ok;
+
 	if (ACPI_SUCCESS(acpi_bus_get_ejd(device->handle, &ejd)))
 		register_dock_dependent_device(device, ejd);
 
 	acpi_bus_get_status(device);
-	/* Skip devices that are not present. */
-	if (!acpi_device_is_present(device)) {
+	/* Skip devices that are not ready for enumeration (e.g. not present) */
+	if (!acpi_dev_ready_for_enumeration(device)) {
 		device->flags.initialized = false;
 		acpi_device_clear_enumerated(device);
 		device->flags.power_manageable = 0;
-		return;
+		return 0;
 	}
 	if (device->handler)
 		goto ok;
 
+	acpi_ec_register_opregions(device);
+
 	if (!device->flags.initialized) {
 		device->flags.power_manageable =
 			device->power.states[ACPI_STATE_D0].flags.valid;
@@ -1984,7 +2308,7 @@ static void acpi_bus_attach(struct acpi_device *device)
 
 	ret = acpi_scan_attach_handler(device);
 	if (ret < 0)
-		return;
+		return 0;
 
 	device->flags.match_driver = true;
 	if (ret > 0 && !device->flags.enumeration_by_parent) {
@@ -1994,43 +2318,258 @@ static void acpi_bus_attach(struct acpi_device *device)
 
 	ret = device_attach(&device->dev);
 	if (ret < 0)
-		return;
+		return 0;
 
 	if (device->pnp.type.platform_id || device->flags.enumeration_by_parent)
 		acpi_default_enumeration(device);
 	else
 		acpi_device_set_enumerated(device);
 
- ok:
-	list_for_each_entry(child, &device->children, node)
-		acpi_bus_attach(child);
+ok:
+	acpi_dev_for_each_child(device, acpi_bus_attach, first_pass);
 
-	if (device->handler && device->handler->hotplug.notify_online)
+	if (!skip && device->handler && device->handler->hotplug.notify_online)
 		device->handler->hotplug.notify_online(device);
+
+	return 0;
 }
 
-void acpi_walk_dep_device_list(acpi_handle handle)
+static int acpi_dev_get_next_consumer_dev_cb(struct acpi_dep_data *dep, void *data)
 {
-	struct acpi_dep_data *dep, *tmp;
+	struct acpi_device **adev_p = data;
+	struct acpi_device *adev = *adev_p;
+
+	/*
+	 * If we're passed a 'previous' consumer device then we need to skip
+	 * any consumers until we meet the previous one, and then NULL @data
+	 * so the next one can be returned.
+	 */
+	if (adev) {
+		if (dep->consumer == adev->handle)
+			*adev_p = NULL;
+
+		return 0;
+	}
+
+	adev = acpi_get_acpi_dev(dep->consumer);
+	if (adev) {
+		*(struct acpi_device **)data = adev;
+		return 1;
+	}
+	/* Continue parsing if the device object is not present. */
+	return 0;
+}
+
+struct acpi_scan_clear_dep_work {
+	struct work_struct work;
 	struct acpi_device *adev;
+};
+
+static void acpi_scan_clear_dep_fn(struct work_struct *work)
+{
+	struct acpi_scan_clear_dep_work *cdw;
+
+	cdw = container_of(work, struct acpi_scan_clear_dep_work, work);
+
+	acpi_scan_lock_acquire();
+	acpi_bus_attach(cdw->adev, (void *)true);
+	acpi_scan_lock_release();
+
+	acpi_dev_put(cdw->adev);
+	kfree(cdw);
+}
+
+static bool acpi_scan_clear_dep_queue(struct acpi_device *adev)
+{
+	struct acpi_scan_clear_dep_work *cdw;
+
+	if (adev->dep_unmet)
+		return false;
+
+	cdw = kmalloc(sizeof(*cdw), GFP_KERNEL);
+	if (!cdw)
+		return false;
+
+	cdw->adev = adev;
+	INIT_WORK(&cdw->work, acpi_scan_clear_dep_fn);
+	/*
+	 * Since the work function may block on the lock until the entire
+	 * initial enumeration of devices is complete, put it into the unbound
+	 * workqueue.
+	 */
+	queue_work(system_dfl_wq, &cdw->work);
+
+	return true;
+}
+
+static void acpi_scan_delete_dep_data(struct acpi_dep_data *dep)
+{
+	list_del(&dep->node);
+	kfree(dep);
+}
+
+static int acpi_scan_clear_dep(struct acpi_dep_data *dep, void *data)
+{
+	struct acpi_device *adev = acpi_get_acpi_dev(dep->consumer);
+
+	if (adev) {
+		adev->dep_unmet--;
+		if (!acpi_scan_clear_dep_queue(adev))
+			acpi_dev_put(adev);
+	}
+
+	if (dep->free_when_met)
+		acpi_scan_delete_dep_data(dep);
+	else
+		dep->met = true;
+
+	return 0;
+}
+
+/**
+ * acpi_walk_dep_device_list - Apply a callback to every entry in acpi_dep_list
+ * @handle:	The ACPI handle of the supplier device
+ * @callback:	Pointer to the callback function to apply
+ * @data:	Pointer to some data to pass to the callback
+ *
+ * The return value of the callback determines this function's behaviour. If 0
+ * is returned we continue to iterate over acpi_dep_list. If a positive value
+ * is returned then the loop is broken but this function returns 0. If a
+ * negative value is returned by the callback then the loop is broken and that
+ * value is returned as the final error.
+ */
+static int acpi_walk_dep_device_list(acpi_handle handle,
+				int (*callback)(struct acpi_dep_data *, void *),
+				void *data)
+{
+	struct acpi_dep_data *dep, *tmp;
+	int ret = 0;
 
 	mutex_lock(&acpi_dep_list_lock);
 	list_for_each_entry_safe(dep, tmp, &acpi_dep_list, node) {
-		if (dep->master == handle) {
-			acpi_bus_get_device(dep->slave, &adev);
-			if (!adev)
-				continue;
+		if (dep->supplier == handle) {
+			ret = callback(dep, data);
+			if (ret)
+				break;
+		}
+	}
+	mutex_unlock(&acpi_dep_list_lock);
+
+	return ret > 0 ? 0 : ret;
+}
+
+/**
+ * acpi_dev_clear_dependencies - Inform consumers that the device is now active
+ * @supplier: Pointer to the supplier &struct acpi_device
+ *
+ * Clear dependencies on the given device.
+ */
+void acpi_dev_clear_dependencies(struct acpi_device *supplier)
+{
+	acpi_walk_dep_device_list(supplier->handle, acpi_scan_clear_dep, NULL);
+}
+EXPORT_SYMBOL_GPL(acpi_dev_clear_dependencies);
+
+/**
+ * acpi_dev_ready_for_enumeration - Check if the ACPI device is ready for enumeration
+ * @device: Pointer to the &struct acpi_device to check
+ *
+ * Check if the device is present and has no unmet dependencies.
+ *
+ * Return true if the device is ready for enumeratino. Otherwise, return false.
+ */
+bool acpi_dev_ready_for_enumeration(const struct acpi_device *device)
+{
+	if (device->flags.honor_deps && device->dep_unmet)
+		return false;
+
+	return acpi_device_is_present(device);
+}
+EXPORT_SYMBOL_GPL(acpi_dev_ready_for_enumeration);
+
+/**
+ * acpi_dev_get_next_consumer_dev - Return the next adev dependent on @supplier
+ * @supplier: Pointer to the dependee device
+ * @start: Pointer to the current dependent device
+ *
+ * Returns the next &struct acpi_device which declares itself dependent on
+ * @supplier via the _DEP buffer, parsed from the acpi_dep_list.
+ *
+ * If the returned adev is not passed as @start to this function, the caller is
+ * responsible for putting the reference to adev when it is no longer needed.
+ */
+struct acpi_device *acpi_dev_get_next_consumer_dev(struct acpi_device *supplier,
+						   struct acpi_device *start)
+{
+	struct acpi_device *adev = start;
+
+	acpi_walk_dep_device_list(supplier->handle,
+				  acpi_dev_get_next_consumer_dev_cb, &adev);
+
+	acpi_dev_put(start);
+
+	if (adev == start)
+		return NULL;
+
+	return adev;
+}
+EXPORT_SYMBOL_GPL(acpi_dev_get_next_consumer_dev);
+
+static void acpi_scan_postponed_branch(acpi_handle handle)
+{
+	struct acpi_device *adev = NULL;
+
+	if (ACPI_FAILURE(acpi_bus_check_add(handle, false, &adev)))
+		return;
+
+	acpi_walk_namespace(ACPI_TYPE_ANY, handle, ACPI_UINT32_MAX,
+			    acpi_bus_check_add_2, NULL, NULL, (void **)&adev);
+
+	/*
+	 * Populate the ACPI _CRS CSI-2 software nodes for the ACPI devices that
+	 * have been added above.
+	 */
+	acpi_mipi_init_crs_csi2_swnodes();
+
+	acpi_bus_attach(adev, NULL);
+}
+
+static void acpi_scan_postponed(void)
+{
+	struct acpi_dep_data *dep, *tmp;
+
+	mutex_lock(&acpi_dep_list_lock);
+
+	list_for_each_entry_safe(dep, tmp, &acpi_dep_list, node) {
+		acpi_handle handle = dep->consumer;
 
-			adev->dep_unmet--;
-			if (!adev->dep_unmet)
-				acpi_bus_attach(adev);
-			list_del(&dep->node);
-			kfree(dep);
+		/*
+		 * In case there are multiple acpi_dep_list entries with the
+		 * same consumer, skip the current entry if the consumer device
+		 * object corresponding to it is present already.
+		 */
+		if (!acpi_fetch_acpi_dev(handle)) {
+			/*
+			 * Even though the lock is released here, tmp is
+			 * guaranteed to be valid, because none of the list
+			 * entries following dep is marked as "free when met"
+			 * and so they cannot be deleted.
+			 */
+			mutex_unlock(&acpi_dep_list_lock);
+
+			acpi_scan_postponed_branch(handle);
+
+			mutex_lock(&acpi_dep_list_lock);
 		}
+
+		if (dep->met)
+			acpi_scan_delete_dep_data(dep);
+		else
+			dep->free_when_met = true;
 	}
+
 	mutex_unlock(&acpi_dep_list_lock);
 }
-EXPORT_SYMBOL_GPL(acpi_walk_dep_device_list);
 
 /**
  * acpi_bus_scan - Add ACPI device node objects in a given namespace scope.
@@ -2048,17 +2587,35 @@ EXPORT_SYMBOL_GPL(acpi_walk_dep_device_list);
  */
 int acpi_bus_scan(acpi_handle handle)
 {
-	void *device = NULL;
+	struct acpi_device *device = NULL;
+
+	/* Pass 1: Avoid enumerating devices with missing dependencies. */
 
-	if (ACPI_SUCCESS(acpi_bus_check_add(handle, 0, NULL, &device)))
+	if (ACPI_SUCCESS(acpi_bus_check_add(handle, true, &device)))
 		acpi_walk_namespace(ACPI_TYPE_ANY, handle, ACPI_UINT32_MAX,
-				    acpi_bus_check_add, NULL, NULL, &device);
+				    acpi_bus_check_add_1, NULL, NULL,
+				    (void **)&device);
 
-	if (device) {
-		acpi_bus_attach(device);
-		return 0;
-	}
-	return -ENODEV;
+	if (!device)
+		return -ENODEV;
+
+	/*
+	 * Set up ACPI _CRS CSI-2 software nodes using information extracted
+	 * from the _CRS CSI-2 resource descriptors during the ACPI namespace
+	 * walk above and MIPI DisCo for Imaging device properties.
+	 */
+	acpi_mipi_scan_crs_csi2();
+	acpi_mipi_init_crs_csi2_swnodes();
+
+	acpi_bus_attach(device, (void *)true);
+
+	/* Pass 2: Enumerate all of the remaining devices. */
+
+	acpi_scan_postponed();
+
+	acpi_mipi_crs_csi2_cleanup();
+
+	return 0;
 }
 EXPORT_SYMBOL(acpi_bus_scan);
 
@@ -2070,28 +2627,9 @@ EXPORT_SYMBOL(acpi_bus_scan);
  */
 void acpi_bus_trim(struct acpi_device *adev)
 {
-	struct acpi_scan_handler *handler = adev->handler;
-	struct acpi_device *child;
-
-	list_for_each_entry_reverse(child, &adev->children, node)
-		acpi_bus_trim(child);
-
-	adev->flags.match_driver = false;
-	if (handler) {
-		if (handler->detach)
-			handler->detach(adev);
+	uintptr_t flags = 0;
 
-		adev->handler = NULL;
-	} else {
-		device_release_driver(&adev->dev);
-	}
-	/*
-	 * Most likely, the device is going away, so put it into D3cold before
-	 * that.
-	 */
-	acpi_device_set_power(adev, ACPI_STATE_D3_COLD);
-	adev->flags.initialized = false;
-	acpi_device_clear_enumerated(adev);
+	acpi_scan_check_and_detach(adev, (void *)flags);
 }
 EXPORT_SYMBOL_GPL(acpi_bus_trim);
 
@@ -2100,8 +2638,7 @@ int acpi_bus_register_early_device(int type)
 	struct acpi_device *device = NULL;
 	int result;
 
-	result = acpi_add_single_object(&device, NULL,
-					type, ACPI_STA_DEFAULT);
+	result = acpi_add_single_object(&device, NULL, type, false);
 	if (result)
 		return result;
 
@@ -2110,44 +2647,33 @@ int acpi_bus_register_early_device(int type)
 }
 EXPORT_SYMBOL_GPL(acpi_bus_register_early_device);
 
-static int acpi_bus_scan_fixed(void)
+static void acpi_bus_scan_fixed(void)
 {
-	int result = 0;
-
-	/*
-	 * Enumerate all fixed-feature devices.
-	 */
 	if (!(acpi_gbl_FADT.flags & ACPI_FADT_POWER_BUTTON)) {
-		struct acpi_device *device = NULL;
-
-		result = acpi_add_single_object(&device, NULL,
-						ACPI_BUS_TYPE_POWER_BUTTON,
-						ACPI_STA_DEFAULT);
-		if (result)
-			return result;
-
-		device->flags.match_driver = true;
-		result = device_attach(&device->dev);
-		if (result < 0)
-			return result;
-
-		device_init_wakeup(&device->dev, true);
+		struct acpi_device *adev = NULL;
+
+		acpi_add_single_object(&adev, NULL, ACPI_BUS_TYPE_POWER_BUTTON,
+				       false);
+		if (adev) {
+			adev->flags.match_driver = true;
+			if (device_attach(&adev->dev) >= 0)
+				device_init_wakeup(&adev->dev, true);
+			else
+				dev_dbg(&adev->dev, "No driver\n");
+		}
 	}
 
 	if (!(acpi_gbl_FADT.flags & ACPI_FADT_SLEEP_BUTTON)) {
-		struct acpi_device *device = NULL;
-
-		result = acpi_add_single_object(&device, NULL,
-						ACPI_BUS_TYPE_SLEEP_BUTTON,
-						ACPI_STA_DEFAULT);
-		if (result)
-			return result;
-
-		device->flags.match_driver = true;
-		result = device_attach(&device->dev);
+		struct acpi_device *adev = NULL;
+
+		acpi_add_single_object(&adev, NULL, ACPI_BUS_TYPE_SLEEP_BUTTON,
+				       false);
+		if (adev) {
+			adev->flags.match_driver = true;
+			if (device_attach(&adev->dev) < 0)
+				dev_dbg(&adev->dev, "No driver\n");
+		}
 	}
-
-	return result < 0 ? result : 0;
 }
 
 static void __init acpi_get_spcr_uart_addr(void)
@@ -2157,17 +2683,19 @@ static void __init acpi_get_spcr_uart_addr(void)
 
 	status = acpi_get_table(ACPI_SIG_SPCR, 0,
 				(struct acpi_table_header **)&spcr_ptr);
-	if (ACPI_SUCCESS(status))
-		spcr_uart_addr = spcr_ptr->serial_port.address;
-	else
-		printk(KERN_WARNING PREFIX "STAO table present, but SPCR is missing\n");
+	if (ACPI_FAILURE(status)) {
+		pr_warn("STAO table present, but SPCR is missing\n");
+		return;
+	}
+
+	spcr_uart_addr = spcr_ptr->serial_port.address;
+	acpi_put_table((struct acpi_table_header *)spcr_ptr);
 }
 
 static bool acpi_scan_initialized;
 
-int __init acpi_scan_init(void)
+void __init acpi_scan_init(void)
 {
-	int result;
 	acpi_status status;
 	struct acpi_table_stao *stao_ptr;
 
@@ -2182,8 +2710,7 @@ int __init acpi_scan_init(void)
 	acpi_memory_hotplug_init();
 	acpi_watchdog_init();
 	acpi_pnp_init();
-	acpi_int340x_thermal_init();
-	acpi_amba_init();
+	acpi_power_resources_init();
 	acpi_init_lpit();
 
 	acpi_scan_add_handler(&generic_device_handler);
@@ -2196,10 +2723,12 @@ int __init acpi_scan_init(void)
 				(struct acpi_table_header **)&stao_ptr);
 	if (ACPI_SUCCESS(status)) {
 		if (stao_ptr->header.length > sizeof(struct acpi_table_stao))
-			printk(KERN_INFO PREFIX "STAO Name List not yet supported.");
+			pr_info("STAO Name List not yet supported.\n");
 
 		if (stao_ptr->ignore_uart)
 			acpi_get_spcr_uart_addr();
+
+		acpi_put_table((struct acpi_table_header *)stao_ptr);
 	}
 
 	acpi_gpe_apply_masked_gpes();
@@ -2215,31 +2744,23 @@ int __init acpi_scan_init(void)
 	/*
 	 * Enumerate devices in the ACPI namespace.
 	 */
-	result = acpi_bus_scan(ACPI_ROOT_OBJECT);
-	if (result)
-		goto out;
+	if (acpi_bus_scan(ACPI_ROOT_OBJECT))
+		goto unlock;
 
-	result = acpi_bus_get_device(ACPI_ROOT_OBJECT, &acpi_root);
-	if (result)
-		goto out;
+	acpi_root = acpi_fetch_acpi_dev(ACPI_ROOT_OBJECT);
+	if (!acpi_root)
+		goto unlock;
 
 	/* Fixed feature devices do not exist on HW-reduced platform */
-	if (!acpi_gbl_reduced_hardware) {
-		result = acpi_bus_scan_fixed();
-		if (result) {
-			acpi_detach_data(acpi_root->handle,
-					 acpi_scan_drop_device);
-			acpi_device_del(acpi_root);
-			put_device(&acpi_root->dev);
-			goto out;
-		}
-	}
+	if (!acpi_gbl_reduced_hardware)
+		acpi_bus_scan_fixed();
+
+	acpi_turn_off_unused_power_resources();
 
 	acpi_scan_initialized = true;
 
- out:
+unlock:
 	mutex_unlock(&acpi_scan_lock);
-	return result;
 }
 
 static struct acpi_probe_entry *ape;
@@ -2256,6 +2777,8 @@ static int __init acpi_match_madt(union acpi_subtable_headers *header,
 	return 0;
 }
 
+void __weak arch_sort_irqchip_probe(struct acpi_probe_entry *ap_head, int nr) { }
+
 int __init __acpi_probe_device_table(struct acpi_probe_entry *ap_head, int nr)
 {
 	int count = 0;
@@ -2264,6 +2787,7 @@ int __init __acpi_probe_device_table(struct acpi_probe_entry *ap_head, int nr)
 		return 0;
 
 	mutex_lock(&acpi_probe_mutex);
+	arch_sort_irqchip_probe(ap_head, nr);
 	for (ape = ap_head; nr; ape++, nr--) {
 		if (ACPI_COMPARE_NAMESEG(ACPI_SIG_MADT, ape->id)) {
 			acpi_probe_count = 0;
@@ -2281,46 +2805,28 @@ int __init __acpi_probe_device_table(struct acpi_probe_entry *ap_head, int nr)
 	return count;
 }
 
-struct acpi_table_events_work {
-	struct work_struct work;
-	void *table;
-	u32 event;
-};
-
 static void acpi_table_events_fn(struct work_struct *work)
 {
-	struct acpi_table_events_work *tew;
+	acpi_scan_lock_acquire();
+	acpi_bus_scan(ACPI_ROOT_OBJECT);
+	acpi_scan_lock_release();
 
-	tew = container_of(work, struct acpi_table_events_work, work);
-
-	if (tew->event == ACPI_TABLE_EVENT_LOAD) {
-		acpi_scan_lock_acquire();
-		acpi_bus_scan(ACPI_ROOT_OBJECT);
-		acpi_scan_lock_release();
-	}
-
-	kfree(tew);
+	kfree(work);
 }
 
-void acpi_scan_table_handler(u32 event, void *table, void *context)
+void acpi_scan_table_notify(void)
 {
-	struct acpi_table_events_work *tew;
+	struct work_struct *work;
 
 	if (!acpi_scan_initialized)
 		return;
 
-	if (event != ACPI_TABLE_EVENT_LOAD)
-		return;
-
-	tew = kmalloc(sizeof(*tew), GFP_KERNEL);
-	if (!tew)
+	work = kmalloc(sizeof(*work), GFP_KERNEL);
+	if (!work)
 		return;
 
-	INIT_WORK(&tew->work, acpi_table_events_fn);
-	tew->table = table;
-	tew->event = event;
-
-	schedule_work(&tew->work);
+	INIT_WORK(work, acpi_table_events_fn);
+	schedule_work(work);
 }
 
 int acpi_reconfig_notifier_register(struct notifier_block *nb)
diff --git a/drivers/acpi/sleep.c b/drivers/acpi/sleep.c
index 4edc8a3ce40f..66ec81e306d4 100644
--- a/drivers/acpi/sleep.c
+++ b/drivers/acpi/sleep.c
@@ -8,6 +8,8 @@
  * Copyright (c) 2003 Open Source Development Lab
  */
 
+#define pr_fmt(fmt) "ACPI: PM: " fmt
+
 #include <linux/delay.h>
 #include <linux/irq.h>
 #include <linux/dmi.h>
@@ -41,7 +43,7 @@ static void acpi_sleep_tts_switch(u32 acpi_state)
 		 * OS can't evaluate the _TTS object correctly. Some warning
 		 * message will be printed. But it won't break anything.
 		 */
-		printk(KERN_NOTICE "Failure in evaluating _TTS object\n");
+		pr_notice("Failure in evaluating _TTS object\n");
 	}
 }
 
@@ -58,23 +60,25 @@ static struct notifier_block tts_notifier = {
 	.priority	= 0,
 };
 
+#ifndef acpi_skip_set_wakeup_address
+#define acpi_skip_set_wakeup_address() false
+#endif
+
 static int acpi_sleep_prepare(u32 acpi_state)
 {
 #ifdef CONFIG_ACPI_SLEEP
 	unsigned long acpi_wakeup_address;
 
 	/* do we have a wakeup address for S2 and S3? */
-	if (acpi_state == ACPI_STATE_S3) {
+	if (acpi_state == ACPI_STATE_S3 && !acpi_skip_set_wakeup_address()) {
 		acpi_wakeup_address = acpi_get_wakeup_address();
 		if (!acpi_wakeup_address)
 			return -EFAULT;
 		acpi_set_waking_vector(acpi_wakeup_address);
 
 	}
-	ACPI_FLUSH_CPU_CACHE();
 #endif
-	printk(KERN_INFO PREFIX "Preparing to enter system sleep state S%d\n",
-		acpi_state);
+	pr_info("Preparing to enter system sleep state S%d\n", acpi_state);
 	acpi_enable_wakeup_devices(acpi_state);
 	acpi_enter_sleep_state_prep(acpi_state);
 	return 0;
@@ -92,10 +96,6 @@ bool acpi_sleep_state_supported(u8 sleep_state)
 }
 
 #ifdef CONFIG_ACPI_SLEEP
-static bool sleep_no_lps0 __read_mostly;
-module_param(sleep_no_lps0, bool, 0644);
-MODULE_PARM_DESC(sleep_no_lps0, "Do not use the special LPS0 device interface");
-
 static u32 acpi_target_sleep_state = ACPI_STATE_S0;
 
 u32 acpi_target_system_state(void)
@@ -165,7 +165,7 @@ static int __init init_nvs_nosave(const struct dmi_system_id *d)
 	return 0;
 }
 
-static bool acpi_sleep_default_s3;
+bool acpi_sleep_default_s3;
 
 static int __init init_default_s3(const struct dmi_system_id *d)
 {
@@ -352,6 +352,20 @@ static const struct dmi_system_id acpisleep_dmi_table[] __initconst = {
 		},
 	},
 	/*
+	 * The ASUS ROG M16 from 2023 has many events which wake it from s2idle
+	 * resulting in excessive battery drain and risk of laptop overheating,
+	 * these events can be caused by the MMC or  y AniMe display if installed.
+	 * The match is valid for all of the GU604V<x> range.
+	 */
+	{
+	.callback = init_default_s3,
+	.ident = "ASUS ROG Zephyrus M16 (2023)",
+	.matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
+		DMI_MATCH(DMI_PRODUCT_NAME, "ROG Zephyrus M16 GU604V"),
+		},
+	},
+	/*
 	 * https://bugzilla.kernel.org/show_bug.cgi?id=189431
 	 * Lenovo G50-45 is a platform later than 2012, but needs nvs memory
 	 * saving during S3.
@@ -364,6 +378,14 @@ static const struct dmi_system_id acpisleep_dmi_table[] __initconst = {
 		DMI_MATCH(DMI_PRODUCT_NAME, "80E3"),
 		},
 	},
+	{
+	.callback = init_nvs_save_s3,
+	.ident = "Lenovo G40-45",
+	.matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
+		DMI_MATCH(DMI_PRODUCT_NAME, "80E1"),
+		},
+	},
 	/*
 	 * ThinkPad X1 Tablet(2016) cannot do suspend-to-idle using
 	 * the Low Power S0 Idle firmware interface (see
@@ -410,7 +432,7 @@ static int acpi_pm_freeze(void)
 }
 
 /**
- * acpi_pre_suspend - Enable wakeup devices, "freeze" EC and save NVS.
+ * acpi_pm_pre_suspend - Enable wakeup devices, "freeze" EC and save NVS.
  */
 static int acpi_pm_pre_suspend(void)
 {
@@ -463,8 +485,7 @@ static void acpi_pm_finish(void)
 	if (acpi_state == ACPI_STATE_S0)
 		return;
 
-	printk(KERN_INFO PREFIX "Waking up from system sleep state S%d\n",
-		acpi_state);
+	pr_info("Waking up from system sleep state S%d\n", acpi_state);
 	acpi_disable_wakeup_devices(acpi_state);
 	acpi_leave_sleep_state(acpi_state);
 
@@ -495,6 +516,7 @@ static void acpi_pm_finish(void)
 
 /**
  * acpi_pm_start - Start system PM transition.
+ * @acpi_state: The target ACPI power state to transition to.
  */
 static void acpi_pm_start(u32 acpi_state)
 {
@@ -533,8 +555,9 @@ static u32 acpi_suspend_states[] = {
 };
 
 /**
- *	acpi_suspend_begin - Set the target system sleep state to the state
- *		associated with given @pm_state, if supported.
+ * acpi_suspend_begin - Set the target system sleep state to the state
+ *	associated with given @pm_state, if supported.
+ * @pm_state: The target system power management state.
  */
 static int acpi_suspend_begin(suspend_state_t pm_state)
 {
@@ -570,8 +593,6 @@ static int acpi_suspend_enter(suspend_state_t pm_state)
 	u32 acpi_state = acpi_target_sleep_state;
 	int error;
 
-	ACPI_FLUSH_CPU_CACHE();
-
 	trace_suspend_resume(TPS("acpi_suspend"), acpi_state, true);
 	switch (acpi_state) {
 	case ACPI_STATE_S1:
@@ -585,7 +606,7 @@ static int acpi_suspend_enter(suspend_state_t pm_state)
 		error = acpi_suspend_lowlevel();
 		if (error)
 			return error;
-		pr_info(PREFIX "Low-level resume complete\n");
+		pr_info("Low-level resume complete\n");
 		pm_set_resume_via_firmware();
 		break;
 	}
@@ -619,11 +640,19 @@ static int acpi_suspend_enter(suspend_state_t pm_state)
 	}
 
 	/*
-	 * Disable and clear GPE status before interrupt is enabled. Some GPEs
-	 * (like wakeup GPE) haven't handler, this can avoid such GPE misfire.
-	 * acpi_leave_sleep_state will reenable specific GPEs later
+	 * Disable all GPE and clear their status bits before interrupts are
+	 * enabled. Some GPEs (like wakeup GPEs) have no handlers and this can
+	 * prevent them from producing spurious interrupts.
+	 *
+	 * acpi_leave_sleep_state() will reenable specific GPEs later.
+	 *
+	 * Because this code runs on one CPU with disabled interrupts (all of
+	 * the other CPUs are offline at this time), it need not acquire any
+	 * sleeping locks which may trigger an implicit preemption point even
+	 * if there is no contention, so avoid doing that by using a low-level
+	 * library routine here.
 	 */
-	acpi_disable_all_gpes();
+	acpi_hw_disable_all_gpes();
 	/* Allow EC transactions to happen. */
 	acpi_ec_unblock_transactions();
 
@@ -658,10 +687,11 @@ static const struct platform_suspend_ops acpi_suspend_ops = {
 };
 
 /**
- *	acpi_suspend_begin_old - Set the target system sleep state to the
- *		state associated with given @pm_state, if supported, and
- *		execute the _PTS control method.  This function is used if the
- *		pre-ACPI 2.0 suspend ordering has been requested.
+ * acpi_suspend_begin_old - Set the target system sleep state to the
+ *	state associated with given @pm_state, if supported, and
+ *	execute the _PTS control method.  This function is used if the
+ *	pre-ACPI 2.0 suspend ordering has been requested.
+ * @pm_state: The target suspend state for the system.
  */
 static int acpi_suspend_begin_old(suspend_state_t pm_state)
 {
@@ -688,271 +718,22 @@ static const struct platform_suspend_ops acpi_suspend_ops_old = {
 
 static bool s2idle_wakeup;
 
-/*
- * On platforms supporting the Low Power S0 Idle interface there is an ACPI
- * device object with the PNP0D80 compatible device ID (System Power Management
- * Controller) and a specific _DSM method under it.  That method, if present,
- * can be used to indicate to the platform that the OS is transitioning into a
- * low-power state in which certain types of activity are not desirable or that
- * it is leaving such a state, which allows the platform to adjust its operation
- * mode accordingly.
- */
-static const struct acpi_device_id lps0_device_ids[] = {
-	{"PNP0D80", },
-	{"", },
-};
-
-#define ACPI_LPS0_DSM_UUID	"c4eb40a0-6cd2-11e2-bcfd-0800200c9a66"
-
-#define ACPI_LPS0_GET_DEVICE_CONSTRAINTS	1
-#define ACPI_LPS0_SCREEN_OFF	3
-#define ACPI_LPS0_SCREEN_ON	4
-#define ACPI_LPS0_ENTRY		5
-#define ACPI_LPS0_EXIT		6
-
-static acpi_handle lps0_device_handle;
-static guid_t lps0_dsm_guid;
-static char lps0_dsm_func_mask;
-
-/* Device constraint entry structure */
-struct lpi_device_info {
-	char *name;
-	int enabled;
-	union acpi_object *package;
-};
-
-/* Constraint package structure */
-struct lpi_device_constraint {
-	int uid;
-	int min_dstate;
-	int function_states;
-};
-
-struct lpi_constraints {
-	acpi_handle handle;
-	int min_dstate;
-};
-
-static struct lpi_constraints *lpi_constraints_table;
-static int lpi_constraints_table_size;
-
-static void lpi_device_get_constraints(void)
-{
-	union acpi_object *out_obj;
-	int i;
-
-	out_obj = acpi_evaluate_dsm_typed(lps0_device_handle, &lps0_dsm_guid,
-					  1, ACPI_LPS0_GET_DEVICE_CONSTRAINTS,
-					  NULL, ACPI_TYPE_PACKAGE);
-
-	acpi_handle_debug(lps0_device_handle, "_DSM function 1 eval %s\n",
-			  out_obj ? "successful" : "failed");
-
-	if (!out_obj)
-		return;
-
-	lpi_constraints_table = kcalloc(out_obj->package.count,
-					sizeof(*lpi_constraints_table),
-					GFP_KERNEL);
-	if (!lpi_constraints_table)
-		goto free_acpi_buffer;
-
-	acpi_handle_debug(lps0_device_handle, "LPI: constraints list begin:\n");
-
-	for (i = 0; i < out_obj->package.count; i++) {
-		struct lpi_constraints *constraint;
-		acpi_status status;
-		union acpi_object *package = &out_obj->package.elements[i];
-		struct lpi_device_info info = { };
-		int package_count = 0, j;
-
-		if (!package)
-			continue;
-
-		for (j = 0; j < package->package.count; ++j) {
-			union acpi_object *element =
-					&(package->package.elements[j]);
-
-			switch (element->type) {
-			case ACPI_TYPE_INTEGER:
-				info.enabled = element->integer.value;
-				break;
-			case ACPI_TYPE_STRING:
-				info.name = element->string.pointer;
-				break;
-			case ACPI_TYPE_PACKAGE:
-				package_count = element->package.count;
-				info.package = element->package.elements;
-				break;
-			}
-		}
-
-		if (!info.enabled || !info.package || !info.name)
-			continue;
-
-		constraint = &lpi_constraints_table[lpi_constraints_table_size];
-
-		status = acpi_get_handle(NULL, info.name, &constraint->handle);
-		if (ACPI_FAILURE(status))
-			continue;
-
-		acpi_handle_debug(lps0_device_handle,
-				  "index:%d Name:%s\n", i, info.name);
-
-		constraint->min_dstate = -1;
-
-		for (j = 0; j < package_count; ++j) {
-			union acpi_object *info_obj = &info.package[j];
-			union acpi_object *cnstr_pkg;
-			union acpi_object *obj;
-			struct lpi_device_constraint dev_info;
-
-			switch (info_obj->type) {
-			case ACPI_TYPE_INTEGER:
-				/* version */
-				break;
-			case ACPI_TYPE_PACKAGE:
-				if (info_obj->package.count < 2)
-					break;
-
-				cnstr_pkg = info_obj->package.elements;
-				obj = &cnstr_pkg[0];
-				dev_info.uid = obj->integer.value;
-				obj = &cnstr_pkg[1];
-				dev_info.min_dstate = obj->integer.value;
-
-				acpi_handle_debug(lps0_device_handle,
-					"uid:%d min_dstate:%s\n",
-					dev_info.uid,
-					acpi_power_state_string(dev_info.min_dstate));
-
-				constraint->min_dstate = dev_info.min_dstate;
-				break;
-			}
-		}
-
-		if (constraint->min_dstate < 0) {
-			acpi_handle_debug(lps0_device_handle,
-					  "Incomplete constraint defined\n");
-			continue;
-		}
-
-		lpi_constraints_table_size++;
-	}
-
-	acpi_handle_debug(lps0_device_handle, "LPI: constraints list end\n");
-
-free_acpi_buffer:
-	ACPI_FREE(out_obj);
-}
-
-static void lpi_check_constraints(void)
-{
-	int i;
-
-	for (i = 0; i < lpi_constraints_table_size; ++i) {
-		acpi_handle handle = lpi_constraints_table[i].handle;
-		struct acpi_device *adev;
-
-		if (!handle || acpi_bus_get_device(handle, &adev))
-			continue;
-
-		acpi_handle_debug(handle,
-			"LPI: required min power state:%s current power state:%s\n",
-			acpi_power_state_string(lpi_constraints_table[i].min_dstate),
-			acpi_power_state_string(adev->power.state));
-
-		if (!adev->flags.power_manageable) {
-			acpi_handle_info(handle, "LPI: Device not power manageable\n");
-			lpi_constraints_table[i].handle = NULL;
-			continue;
-		}
-
-		if (adev->power.state < lpi_constraints_table[i].min_dstate)
-			acpi_handle_info(handle,
-				"LPI: Constraint not met; min power state:%s current power state:%s\n",
-				acpi_power_state_string(lpi_constraints_table[i].min_dstate),
-				acpi_power_state_string(adev->power.state));
-	}
-}
-
-static void acpi_sleep_run_lps0_dsm(unsigned int func)
-{
-	union acpi_object *out_obj;
-
-	if (!(lps0_dsm_func_mask & (1 << func)))
-		return;
-
-	out_obj = acpi_evaluate_dsm(lps0_device_handle, &lps0_dsm_guid, 1, func, NULL);
-	ACPI_FREE(out_obj);
-
-	acpi_handle_debug(lps0_device_handle, "_DSM function %u evaluation %s\n",
-			  func, out_obj ? "successful" : "failed");
-}
-
-static int lps0_device_attach(struct acpi_device *adev,
-			      const struct acpi_device_id *not_used)
-{
-	union acpi_object *out_obj;
-
-	if (lps0_device_handle)
-		return 0;
-
-	if (!(acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0))
-		return 0;
-
-	guid_parse(ACPI_LPS0_DSM_UUID, &lps0_dsm_guid);
-	/* Check if the _DSM is present and as expected. */
-	out_obj = acpi_evaluate_dsm(adev->handle, &lps0_dsm_guid, 1, 0, NULL);
-	if (!out_obj || out_obj->type != ACPI_TYPE_BUFFER) {
-		acpi_handle_debug(adev->handle,
-				  "_DSM function 0 evaluation failed\n");
-		return 0;
-	}
-
-	lps0_dsm_func_mask = *(char *)out_obj->buffer.pointer;
-
-	ACPI_FREE(out_obj);
-
-	acpi_handle_debug(adev->handle, "_DSM function mask: 0x%x\n",
-			  lps0_dsm_func_mask);
-
-	lps0_device_handle = adev->handle;
-
-	lpi_device_get_constraints();
-
-	/*
-	 * Use suspend-to-idle by default if the default suspend mode was not
-	 * set from the command line.
-	 */
-	if (mem_sleep_default > PM_SUSPEND_MEM && !acpi_sleep_default_s3)
-		mem_sleep_current = PM_SUSPEND_TO_IDLE;
-
-	/*
-	 * Some LPS0 systems, like ASUS Zenbook UX430UNR/i7-8550U, require the
-	 * EC GPE to be enabled while suspended for certain wakeup devices to
-	 * work, so mark it as wakeup-capable.
-	 */
-	acpi_ec_mark_gpe_for_wake();
-
-	return 0;
-}
-
-static struct acpi_scan_handler lps0_handler = {
-	.ids = lps0_device_ids,
-	.attach = lps0_device_attach,
-};
-
-static int acpi_s2idle_begin(void)
+int acpi_s2idle_begin(void)
 {
 	acpi_scan_lock_acquire();
 	return 0;
 }
 
-static int acpi_s2idle_prepare(void)
+int acpi_s2idle_prepare(void)
 {
 	if (acpi_sci_irq_valid()) {
-		enable_irq_wake(acpi_sci_irq);
+		int error;
+
+		error = enable_irq_wake(acpi_sci_irq);
+		if (error)
+			pr_warn("Warning: Failed to enable wakeup from IRQ %d: %d\n",
+				acpi_sci_irq, error);
+
 		acpi_ec_set_gpe_wake_mask(ACPI_GPE_ENABLE);
 	}
 
@@ -966,28 +747,7 @@ static int acpi_s2idle_prepare(void)
 	return 0;
 }
 
-static int acpi_s2idle_prepare_late(void)
-{
-	if (!lps0_device_handle || sleep_no_lps0)
-		return 0;
-
-	if (pm_debug_messages_on)
-		lpi_check_constraints();
-
-	acpi_sleep_run_lps0_dsm(ACPI_LPS0_SCREEN_OFF);
-	acpi_sleep_run_lps0_dsm(ACPI_LPS0_ENTRY);
-
-	return 0;
-}
-
-static void acpi_s2idle_sync(void)
-{
-	/* The EC driver uses special workqueues that need to be flushed. */
-	acpi_ec_flush_work();
-	acpi_os_wait_events_complete(); /* synchronize Notify handling */
-}
-
-static bool acpi_s2idle_wake(void)
+bool acpi_s2idle_wake(void)
 {
 	if (!acpi_sci_irq_valid())
 		return pm_wakeup_pending();
@@ -999,45 +759,36 @@ static bool acpi_s2idle_wake(void)
 		 * wakeup is pending anyway and the SCI is not the source of
 		 * it).
 		 */
-		if (irqd_is_wakeup_armed(irq_get_irq_data(acpi_sci_irq)))
+		if (irqd_is_wakeup_armed(irq_get_irq_data(acpi_sci_irq))) {
+			pm_pr_dbg("Wakeup unrelated to ACPI SCI\n");
 			return true;
+		}
 
 		/*
 		 * If the status bit of any enabled fixed event is set, the
 		 * wakeup is regarded as valid.
 		 */
-		if (acpi_any_fixed_event_status_set())
+		if (acpi_any_fixed_event_status_set()) {
+			pm_pr_dbg("ACPI fixed event wakeup\n");
 			return true;
+		}
 
 		/* Check wakeups from drivers sharing the SCI. */
-		if (acpi_check_wakeup_handlers())
+		if (acpi_check_wakeup_handlers()) {
+			pm_pr_dbg("ACPI custom handler wakeup\n");
 			return true;
+		}
 
 		/*
-		 * If the status bit is set for any enabled GPE other than the
-		 * EC one, the wakeup is regarded as a genuine one.
+		 * Check non-EC GPE wakeups and if there are none, cancel the
+		 * SCI-related wakeup and dispatch the EC GPE.
 		 */
-		if (acpi_ec_other_gpes_active())
+		if (acpi_ec_dispatch_gpe()) {
+			pm_pr_dbg("ACPI non-EC GPE wakeup\n");
 			return true;
+		}
 
-		/*
-		 * If the EC GPE status bit has not been set, the wakeup is
-		 * regarded as a spurious one.
-		 */
-		if (!acpi_ec_dispatch_gpe())
-			return false;
-
-		/*
-		 * Cancel the wakeup and process all pending events in case
-		 * there are any wakeup ones in there.
-		 *
-		 * Note that if any non-EC GPEs are active at this point, the
-		 * SCI will retrigger after the rearming below, so no events
-		 * should be missed by canceling the wakeup here.
-		 */
-		pm_system_cancel_wakeup();
-
-		acpi_s2idle_sync();
+		acpi_os_wait_events_complete();
 
 		/*
 		 * The SCI is in the "suspended" state now and it cannot produce
@@ -1045,32 +796,29 @@ static bool acpi_s2idle_wake(void)
 		 * are pending here, they must be resulting from the processing
 		 * of EC events above or coming from somewhere else.
 		 */
-		if (pm_wakeup_pending())
+		if (pm_wakeup_pending()) {
+			pm_pr_dbg("Wakeup after ACPI Notify sync\n");
 			return true;
+		}
 
+		pm_pr_dbg("Rearming ACPI SCI for wakeup\n");
+
+		pm_wakeup_clear(acpi_sci_irq);
 		rearm_wake_irq(acpi_sci_irq);
 	}
 
 	return false;
 }
 
-static void acpi_s2idle_restore_early(void)
-{
-	if (!lps0_device_handle || sleep_no_lps0)
-		return;
-
-	acpi_sleep_run_lps0_dsm(ACPI_LPS0_EXIT);
-	acpi_sleep_run_lps0_dsm(ACPI_LPS0_SCREEN_ON);
-}
-
-static void acpi_s2idle_restore(void)
+void acpi_s2idle_restore(void)
 {
 	/*
 	 * Drain pending events before restoring the working-state configuration
 	 * of GPEs.
 	 */
 	acpi_os_wait_events_complete(); /* synchronize GPE processing */
-	acpi_s2idle_sync();
+	acpi_ec_flush_work(); /* flush the EC driver's workqueues */
+	acpi_os_wait_events_complete(); /* synchronize Notify handling */
 
 	s2idle_wakeup = false;
 
@@ -1084,7 +832,7 @@ static void acpi_s2idle_restore(void)
 	}
 }
 
-static void acpi_s2idle_end(void)
+void acpi_s2idle_end(void)
 {
 	acpi_scan_lock_release();
 }
@@ -1092,31 +840,39 @@ static void acpi_s2idle_end(void)
 static const struct platform_s2idle_ops acpi_s2idle_ops = {
 	.begin = acpi_s2idle_begin,
 	.prepare = acpi_s2idle_prepare,
-	.prepare_late = acpi_s2idle_prepare_late,
 	.wake = acpi_s2idle_wake,
-	.restore_early = acpi_s2idle_restore_early,
 	.restore = acpi_s2idle_restore,
 	.end = acpi_s2idle_end,
 };
 
-static void acpi_sleep_suspend_setup(void)
+void __weak acpi_s2idle_setup(void)
+{
+	if (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)
+		pr_info("Efficient low-power S0 idle declared\n");
+
+	s2idle_set_ops(&acpi_s2idle_ops);
+}
+
+static void __init acpi_sleep_suspend_setup(void)
 {
+	bool suspend_ops_needed = false;
 	int i;
 
 	for (i = ACPI_STATE_S1; i < ACPI_STATE_S4; i++)
-		if (acpi_sleep_state_supported(i))
+		if (acpi_sleep_state_supported(i)) {
 			sleep_states[i] = 1;
+			suspend_ops_needed = true;
+		}
 
-	suspend_set_ops(old_suspend_ordering ?
-		&acpi_suspend_ops_old : &acpi_suspend_ops);
+	if (suspend_ops_needed)
+		suspend_set_ops(old_suspend_ordering ?
+				&acpi_suspend_ops_old : &acpi_suspend_ops);
 
-	acpi_scan_add_handler(&lps0_handler);
-	s2idle_set_ops(&acpi_s2idle_ops);
+	acpi_s2idle_setup();
 }
 
 #else /* !CONFIG_SUSPEND */
 #define s2idle_wakeup		(false)
-#define lps0_device_handle	(NULL)
 static inline void acpi_sleep_suspend_setup(void) {}
 #endif /* !CONFIG_SUSPEND */
 
@@ -1128,13 +884,13 @@ bool acpi_s2idle_wakeup(void)
 #ifdef CONFIG_PM_SLEEP
 static u32 saved_bm_rld;
 
-static int  acpi_save_bm_rld(void)
+static int  acpi_save_bm_rld(void *data)
 {
 	acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_RLD, &saved_bm_rld);
 	return 0;
 }
 
-static void  acpi_restore_bm_rld(void)
+static void  acpi_restore_bm_rld(void *data)
 {
 	u32 resumed_bm_rld = 0;
 
@@ -1145,14 +901,18 @@ static void  acpi_restore_bm_rld(void)
 	acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, saved_bm_rld);
 }
 
-static struct syscore_ops acpi_sleep_syscore_ops = {
+static const struct syscore_ops acpi_sleep_syscore_ops = {
 	.suspend = acpi_save_bm_rld,
 	.resume = acpi_restore_bm_rld,
 };
 
+static struct syscore acpi_sleep_syscore = {
+	.ops = &acpi_sleep_syscore_ops,
+};
+
 static void acpi_sleep_syscore_init(void)
 {
-	register_syscore_ops(&acpi_sleep_syscore_ops);
+	register_syscore(&acpi_sleep_syscore);
 }
 #else
 static inline void acpi_sleep_syscore_init(void) {}
@@ -1161,12 +921,7 @@ static inline void acpi_sleep_syscore_init(void) {}
 #ifdef CONFIG_HIBERNATION
 static unsigned long s4_hardware_signature;
 static struct acpi_table_facs *facs;
-static bool nosigcheck;
-
-void __init acpi_no_s4_hw_signature(void)
-{
-	nosigcheck = true;
-}
+int acpi_check_s4_hw_signature = -1; /* Default behaviour is just to warn */
 
 static int acpi_hibernation_begin(pm_message_t stage)
 {
@@ -1187,8 +942,6 @@ static int acpi_hibernation_enter(void)
 {
 	acpi_status status = AE_OK;
 
-	ACPI_FLUSH_CPU_CACHE();
-
 	/* This shouldn't return.  If it returns, we have a problem */
 	status = acpi_enter_sleep_state(ACPI_STATE_S4);
 	/* Reprogram control registers */
@@ -1209,7 +962,7 @@ static void acpi_hibernation_leave(void)
 	acpi_leave_sleep_state_prep(ACPI_STATE_S4);
 	/* Check the hardware signature */
 	if (facs && s4_hardware_signature != facs->hardware_signature)
-		pr_crit("ACPI: Hardware changed while hibernated, success doubtful!\n");
+		pr_crit("Hardware changed while hibernated, success doubtful!\n");
 	/* Restore the NVS memory area */
 	suspend_nvs_restore();
 	/* Allow EC transactions to happen. */
@@ -1235,10 +988,11 @@ static const struct platform_hibernation_ops acpi_hibernation_ops = {
 };
 
 /**
- *	acpi_hibernation_begin_old - Set the target system sleep state to
- *		ACPI_STATE_S4 and execute the _PTS control method.  This
- *		function is used if the pre-ACPI 2.0 suspend ordering has been
- *		requested.
+ * acpi_hibernation_begin_old - Set the target system sleep state to
+ *	ACPI_STATE_S4 and execute the _PTS control method.  This
+ *	function is used if the pre-ACPI 2.0 suspend ordering has been
+ *	requested.
+ * @stage: The power management event message.
  */
 static int acpi_hibernation_begin_old(pm_message_t stage)
 {
@@ -1293,31 +1047,49 @@ static void acpi_sleep_hibernate_setup(void)
 	hibernation_set_ops(old_suspend_ordering ?
 			&acpi_hibernation_ops_old : &acpi_hibernation_ops);
 	sleep_states[ACPI_STATE_S4] = 1;
-	if (nosigcheck)
+	if (!acpi_check_s4_hw_signature)
 		return;
 
 	acpi_get_table(ACPI_SIG_FACS, 1, (struct acpi_table_header **)&facs);
-	if (facs)
+	if (facs) {
+		/*
+		 * s4_hardware_signature is the local variable which is just
+		 * used to warn about mismatch after we're attempting to
+		 * resume (in violation of the ACPI specification.)
+		 */
 		s4_hardware_signature = facs->hardware_signature;
+
+		if (acpi_check_s4_hw_signature > 0) {
+			/*
+			 * If we're actually obeying the ACPI specification
+			 * then the signature is written out as part of the
+			 * swsusp header, in order to allow the boot kernel
+			 * to gracefully decline to resume.
+			 */
+			swsusp_hardware_signature = facs->hardware_signature;
+		}
+	}
 }
 #else /* !CONFIG_HIBERNATION */
 static inline void acpi_sleep_hibernate_setup(void) {}
 #endif /* !CONFIG_HIBERNATION */
 
-static void acpi_power_off_prepare(void)
+static int acpi_power_off_prepare(struct sys_off_data *data)
 {
 	/* Prepare to power off the system */
 	acpi_sleep_prepare(ACPI_STATE_S5);
 	acpi_disable_all_gpes();
 	acpi_os_wait_events_complete();
+	return NOTIFY_DONE;
 }
 
-static void acpi_power_off(void)
+static int acpi_power_off(struct sys_off_data *data)
 {
 	/* acpi_sleep_prepare(ACPI_STATE_S5) should have already been called */
-	printk(KERN_DEBUG "%s called\n", __func__);
+	pr_debug("%s called\n", __func__);
 	local_irq_disable();
 	acpi_enter_sleep_state(ACPI_STATE_S5);
+	return NOTIFY_DONE;
 }
 
 int __init acpi_sleep_init(void)
@@ -1336,8 +1108,22 @@ int __init acpi_sleep_init(void)
 
 	if (acpi_sleep_state_supported(ACPI_STATE_S5)) {
 		sleep_states[ACPI_STATE_S5] = 1;
-		pm_power_off_prepare = acpi_power_off_prepare;
-		pm_power_off = acpi_power_off;
+
+		register_sys_off_handler(SYS_OFF_MODE_POWER_OFF_PREPARE,
+					 SYS_OFF_PRIO_FIRMWARE,
+					 acpi_power_off_prepare, NULL);
+
+		register_sys_off_handler(SYS_OFF_MODE_POWER_OFF,
+					 SYS_OFF_PRIO_FIRMWARE,
+					 acpi_power_off, NULL);
+
+		/*
+		 * Windows uses S5 for reboot, so some BIOSes depend on it to
+		 * perform proper reboot.
+		 */
+		register_sys_off_handler(SYS_OFF_MODE_RESTART_PREPARE,
+					 SYS_OFF_PRIO_FIRMWARE,
+					 acpi_power_off_prepare, NULL);
 	} else {
 		acpi_no_s5 = true;
 	}
@@ -1347,7 +1133,7 @@ int __init acpi_sleep_init(void)
 		if (sleep_states[i])
 			pos += sprintf(pos, " S%d", i);
 	}
-	pr_info(PREFIX "(supports%s)\n", supported);
+	pr_info("(supports%s)\n", supported);
 
 	/*
 	 * Register the tts_notifier to reboot notifier list so that the _TTS
diff --git a/drivers/acpi/sleep.h b/drivers/acpi/sleep.h
index 3d90480ce1b1..9c3cb109c5d2 100644
--- a/drivers/acpi/sleep.h
+++ b/drivers/acpi/sleep.h
@@ -8,10 +8,23 @@ extern struct list_head acpi_wakeup_device_list;
 extern struct mutex acpi_device_lock;
 
 extern void acpi_resume_power_resources(void);
-extern void acpi_turn_off_unused_power_resources(void);
 
 static inline acpi_status acpi_set_waking_vector(u32 wakeup_address)
 {
 	return acpi_set_firmware_waking_vector(
 				(acpi_physical_address)wakeup_address, 0);
 }
+
+extern int acpi_s2idle_begin(void);
+extern int acpi_s2idle_prepare(void);
+extern bool acpi_s2idle_wake(void);
+extern void acpi_s2idle_restore(void);
+extern void acpi_s2idle_end(void);
+
+extern void acpi_s2idle_setup(void);
+
+#ifdef CONFIG_ACPI_SLEEP
+extern bool acpi_sleep_default_s3;
+#else
+#define acpi_sleep_default_s3	(1)
+#endif
diff --git a/drivers/acpi/spcr.c b/drivers/acpi/spcr.c
index d73b4535e79d..73cb933fdc89 100644
--- a/drivers/acpi/spcr.c
+++ b/drivers/acpi/spcr.c
@@ -71,7 +71,6 @@ static bool xgene_8250_erratum_present(struct acpi_table_spcr *tb)
 
 /**
  * acpi_parse_spcr() - parse ACPI SPCR table and add preferred console
- *
  * @enable_earlycon: set up earlycon for the console specified by the table
  * @enable_console: setup the console specified by the table.
  *
@@ -82,7 +81,6 @@ static bool xgene_8250_erratum_present(struct acpi_table_spcr *tb)
  *
  * When CONFIG_ACPI_SPCR_TABLE is defined, this function should be called
  * from arch initialization code as soon as the DT/ACPI decision is made.
- *
  */
 int __init acpi_parse_spcr(bool enable_earlycon, bool enable_console)
 {
@@ -97,9 +95,7 @@ int __init acpi_parse_spcr(bool enable_earlycon, bool enable_console)
 	if (acpi_disabled)
 		return -ENODEV;
 
-	status = acpi_get_table(ACPI_SIG_SPCR, 0,
-				(struct acpi_table_header **)&table);
-
+	status = acpi_get_table(ACPI_SIG_SPCR, 0, (struct acpi_table_header **)&table);
 	if (ACPI_FAILURE(status))
 		return -ENOENT;
 
@@ -107,11 +103,16 @@ int __init acpi_parse_spcr(bool enable_earlycon, bool enable_console)
 		pr_info("SPCR table version %d\n", table->header.revision);
 
 	if (table->serial_port.space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
-		switch (ACPI_ACCESS_BIT_WIDTH((
-			table->serial_port.access_width))) {
+		u32 bit_width = table->serial_port.access_width;
+
+		if (bit_width > ACPI_ACCESS_BIT_MAX) {
+			pr_err(FW_BUG "Unacceptable wide SPCR Access Width. Defaulting to byte size\n");
+			bit_width = ACPI_ACCESS_BIT_DEFAULT;
+		}
+		switch (ACPI_ACCESS_BIT_WIDTH((bit_width))) {
 		default:
-			pr_err("Unexpected SPCR Access Width.  Defaulting to byte size\n");
-			/* fall through */
+			pr_err(FW_BUG "Unexpected SPCR Access Width. Defaulting to byte size\n");
+			fallthrough;
 		case 8:
 			iotype = "mmio";
 			break;
@@ -128,7 +129,7 @@ int __init acpi_parse_spcr(bool enable_earlycon, bool enable_console)
 	switch (table->interface_type) {
 	case ACPI_DBG2_ARM_SBSA_32BIT:
 		iotype = "mmio32";
-		/* fall through */
+		fallthrough;
 	case ACPI_DBG2_ARM_PL011:
 	case ACPI_DBG2_ARM_SBSA_GENERIC:
 	case ACPI_DBG2_BCM2835:
@@ -136,14 +137,27 @@ int __init acpi_parse_spcr(bool enable_earlycon, bool enable_console)
 		break;
 	case ACPI_DBG2_16550_COMPATIBLE:
 	case ACPI_DBG2_16550_SUBSET:
+	case ACPI_DBG2_16550_WITH_GAS:
+	case ACPI_DBG2_16550_NVIDIA:
 		uart = "uart";
 		break;
+	case ACPI_DBG2_RISCV_SBI_CON:
+		uart = "sbi";
+		break;
 	default:
 		err = -ENOENT;
 		goto done;
 	}
 
-	switch (table->baud_rate) {
+	/*
+	 * SPCR 1.09 defines Precise Baud Rate Filed contains a specific
+	 * non-zero baud rate which overrides the value of the Configured
+	 * Baud Rate field. If this field is zero or not present, Configured
+	 * Baud Rate is used.
+	 */
+	if (table->header.revision >= 4 && table->precise_baudrate)
+		baud_rate = table->precise_baudrate;
+	else switch (table->baud_rate) {
 	case 0:
 		/*
 		 * SPCR 1.04 defines 0 as a preconfigured state of UART.
@@ -195,7 +209,8 @@ int __init acpi_parse_spcr(bool enable_earlycon, bool enable_console)
 	if (xgene_8250_erratum_present(table)) {
 		iotype = "mmio32";
 
-		/* for xgene v1 and v2 we don't know the clock rate of the
+		/*
+		 * For xgene v1 and v2 we don't know the clock rate of the
 		 * UART so don't attempt to change to the baud rate state
 		 * in the table because driver cannot calculate the dividers
 		 */
diff --git a/drivers/acpi/sysfs.c b/drivers/acpi/sysfs.c
index c60d2c6d31d6..e596224302f4 100644
--- a/drivers/acpi/sysfs.c
+++ b/drivers/acpi/sysfs.c
@@ -5,16 +5,15 @@
 
 #define pr_fmt(fmt) "ACPI: " fmt
 
+#include <linux/acpi.h>
+#include <linux/bitmap.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/kstrtox.h>
 #include <linux/moduleparam.h>
-#include <linux/acpi.h>
 
 #include "internal.h"
 
-#define _COMPONENT		ACPI_SYSTEM_COMPONENT
-ACPI_MODULE_NAME("sysfs");
-
 #ifdef CONFIG_ACPI_DEBUG
 /*
  * ACPI debug sysfs I/F, including:
@@ -51,21 +50,6 @@ static const struct acpi_dlayer acpi_debug_layers[] = {
 	ACPI_DEBUG_INIT(ACPI_CA_DISASSEMBLER),
 	ACPI_DEBUG_INIT(ACPI_COMPILER),
 	ACPI_DEBUG_INIT(ACPI_TOOLS),
-
-	ACPI_DEBUG_INIT(ACPI_BUS_COMPONENT),
-	ACPI_DEBUG_INIT(ACPI_AC_COMPONENT),
-	ACPI_DEBUG_INIT(ACPI_BATTERY_COMPONENT),
-	ACPI_DEBUG_INIT(ACPI_BUTTON_COMPONENT),
-	ACPI_DEBUG_INIT(ACPI_SBS_COMPONENT),
-	ACPI_DEBUG_INIT(ACPI_FAN_COMPONENT),
-	ACPI_DEBUG_INIT(ACPI_PCI_COMPONENT),
-	ACPI_DEBUG_INIT(ACPI_POWER_COMPONENT),
-	ACPI_DEBUG_INIT(ACPI_CONTAINER_COMPONENT),
-	ACPI_DEBUG_INIT(ACPI_SYSTEM_COMPONENT),
-	ACPI_DEBUG_INIT(ACPI_THERMAL_COMPONENT),
-	ACPI_DEBUG_INIT(ACPI_MEMORY_DEVICE_COMPONENT),
-	ACPI_DEBUG_INIT(ACPI_VIDEO_COMPONENT),
-	ACPI_DEBUG_INIT(ACPI_PROCESSOR_COMPONENT),
 };
 
 static const struct acpi_dlevel acpi_debug_levels[] = {
@@ -214,7 +198,7 @@ static int param_set_trace_method_name(const char *val,
 
 static int param_get_trace_method_name(char *buffer, const struct kernel_param *kp)
 {
-	return scnprintf(buffer, PAGE_SIZE, "%s", acpi_gbl_trace_method_name);
+	return sysfs_emit(buffer, "%s\n", acpi_gbl_trace_method_name);
 }
 
 static const struct kernel_param_ops param_ops_trace_method = {
@@ -271,17 +255,13 @@ static int param_set_trace_state(const char *val,
 static int param_get_trace_state(char *buffer, const struct kernel_param *kp)
 {
 	if (!(acpi_gbl_trace_flags & ACPI_TRACE_ENABLED))
-		return sprintf(buffer, "disable");
-	else {
-		if (acpi_gbl_trace_method_name) {
-			if (acpi_gbl_trace_flags & ACPI_TRACE_ONESHOT)
-				return sprintf(buffer, "method-once");
-			else
-				return sprintf(buffer, "method");
-		} else
-			return sprintf(buffer, "enable");
-	}
-	return 0;
+		return sprintf(buffer, "disable\n");
+	if (!acpi_gbl_trace_method_name)
+		return sprintf(buffer, "enable\n");
+	if (acpi_gbl_trace_flags & ACPI_TRACE_ONESHOT)
+		return sprintf(buffer, "method-once\n");
+	else
+		return sprintf(buffer, "method\n");
 }
 
 module_param_call(trace_state, param_set_trace_state, param_get_trace_state,
@@ -302,7 +282,7 @@ static int param_get_acpica_version(char *buffer,
 {
 	int result;
 
-	result = sprintf(buffer, "%x", ACPI_CA_VERSION);
+	result = sprintf(buffer, "%x\n", ACPI_CA_VERSION);
 
 	return result;
 }
@@ -339,7 +319,7 @@ struct acpi_data_attr {
 };
 
 static ssize_t acpi_table_show(struct file *filp, struct kobject *kobj,
-			       struct bin_attribute *bin_attr, char *buf,
+			       const struct bin_attribute *bin_attr, char *buf,
 			       loff_t offset, size_t count)
 {
 	struct acpi_table_attr *table_attr =
@@ -377,8 +357,7 @@ static int acpi_table_attr_init(struct kobject *tables_obj,
 	}
 	table_attr->instance++;
 	if (table_attr->instance > ACPI_MAX_TABLE_INSTANCES) {
-		pr_warn("%4.4s: too many table instances\n",
-			table_attr->name);
+		pr_warn("%4.4s: too many table instances\n", table_attr->name);
 		return -ERANGE;
 	}
 
@@ -406,8 +385,7 @@ acpi_status acpi_sysfs_table_handler(u32 event, void *table, void *context)
 
 	switch (event) {
 	case ACPI_TABLE_EVENT_INSTALL:
-		table_attr =
-		    kzalloc(sizeof(struct acpi_table_attr), GFP_KERNEL);
+		table_attr = kzalloc(sizeof(*table_attr), GFP_KERNEL);
 		if (!table_attr)
 			return AE_NO_MEMORY;
 
@@ -434,23 +412,34 @@ acpi_status acpi_sysfs_table_handler(u32 event, void *table, void *context)
 }
 
 static ssize_t acpi_data_show(struct file *filp, struct kobject *kobj,
-			      struct bin_attribute *bin_attr, char *buf,
+			      const struct bin_attribute *bin_attr, char *buf,
 			      loff_t offset, size_t count)
 {
 	struct acpi_data_attr *data_attr;
 	void __iomem *base;
-	ssize_t rc;
+	ssize_t size;
 
 	data_attr = container_of(bin_attr, struct acpi_data_attr, attr);
+	size = data_attr->attr.size;
 
-	base = acpi_os_map_memory(data_attr->addr, data_attr->attr.size);
+	if (offset < 0)
+		return -EINVAL;
+
+	if (offset >= size)
+		return 0;
+
+	if (count > size - offset)
+		count = size - offset;
+
+	base = acpi_os_map_iomem(data_attr->addr, size);
 	if (!base)
 		return -ENOMEM;
-	rc = memory_read_from_buffer(buf, count, &offset, base,
-				     data_attr->attr.size);
-	acpi_os_unmap_memory(base, data_attr->attr.size);
 
-	return rc;
+	memcpy_fromio(buf, base + offset, count);
+
+	acpi_os_unmap_iomem(base, size);
+
+	return count;
 }
 
 static int acpi_bert_data_init(void *th, struct acpi_data_attr *data_attr)
@@ -469,11 +458,28 @@ static int acpi_bert_data_init(void *th, struct acpi_data_attr *data_attr)
 	return sysfs_create_bin_file(tables_data_kobj, &data_attr->attr);
 }
 
+static int acpi_ccel_data_init(void *th, struct acpi_data_attr *data_attr)
+{
+	struct acpi_table_ccel *ccel = th;
+
+	if (ccel->header.length < sizeof(struct acpi_table_ccel) ||
+	    !ccel->log_area_start_address || !ccel->log_area_minimum_length) {
+		kfree(data_attr);
+		return -EINVAL;
+	}
+	data_attr->addr = ccel->log_area_start_address;
+	data_attr->attr.size = ccel->log_area_minimum_length;
+	data_attr->attr.attr.name = "CCEL";
+
+	return sysfs_create_bin_file(tables_data_kobj, &data_attr->attr);
+}
+
 static struct acpi_data_obj {
 	char *name;
 	int (*fn)(void *, struct acpi_data_attr *);
 } acpi_data_objs[] = {
 	{ ACPI_SIG_BERT, acpi_bert_data_init },
+	{ ACPI_SIG_CCEL, acpi_ccel_data_init },
 };
 
 #define NUM_ACPI_DATA_OBJS ARRAY_SIZE(acpi_data_objs)
@@ -600,8 +606,6 @@ static void delete_gpe_attr_array(void)
 		kfree(counter_attrs);
 	}
 	kfree(all_attrs);
-
-	return;
 }
 
 static void gpe_count(u32 gpe_number)
@@ -616,8 +620,6 @@ static void gpe_count(u32 gpe_number)
 	else
 		all_counters[num_gpes + ACPI_NUM_FIXED_EVENTS +
 			     COUNT_ERROR].count++;
-
-	return;
 }
 
 static void fixed_event_count(u32 event_number)
@@ -630,8 +632,6 @@ static void fixed_event_count(u32 event_number)
 	else
 		all_counters[num_gpes + ACPI_NUM_FIXED_EVENTS +
 			     COUNT_ERROR].count++;
-
-	return;
 }
 
 static void acpi_global_event_handler(u32 event_type, acpi_handle device,
@@ -659,8 +659,7 @@ static int get_status(u32 index, acpi_event_status *ret,
 	if (index < num_gpes) {
 		status = acpi_get_gpe_device(index, handle);
 		if (ACPI_FAILURE(status)) {
-			ACPI_EXCEPTION((AE_INFO, AE_NOT_FOUND,
-					"Invalid GPE 0x%x", index));
+			pr_warn("Invalid GPE 0x%x", index);
 			return -ENXIO;
 		}
 		status = acpi_get_gpe_status(*handle, index, ret);
@@ -756,8 +755,7 @@ static ssize_t counter_set(struct kobject *kobj,
 		goto end;
 
 	if (!(status & ACPI_EVENT_FLAG_HAS_HANDLER)) {
-		printk(KERN_WARNING PREFIX
-		       "Can not change Invalid GPE/Fixed Event status\n");
+		pr_warn("Can not change Invalid GPE/Fixed Event status\n");
 		return -EINVAL;
 	}
 
@@ -815,6 +813,7 @@ end:
  * the GPE flooding for GPE 00, they need to specify the following boot
  * parameter:
  *   acpi_mask_gpe=0x00
+ * Note, the parameter can be a list (see bitmap_parselist() for the details).
  * The masking status can be modified by the following runtime controlling
  * interface:
  *   echo unmask > /sys/firmware/acpi/interrupts/gpe00
@@ -824,11 +823,16 @@ static DECLARE_BITMAP(acpi_masked_gpes_map, ACPI_MASKABLE_GPE_MAX) __initdata;
 
 static int __init acpi_gpe_set_masked_gpes(char *val)
 {
+	int ret;
 	u8 gpe;
 
-	if (kstrtou8(val, 0, &gpe))
-		return -EINVAL;
-	set_bit(gpe, acpi_masked_gpes_map);
+	ret = kstrtou8(val, 0, &gpe);
+	if (ret) {
+		ret = bitmap_parselist(val, acpi_masked_gpes_map, ACPI_MASKABLE_GPE_MAX);
+		if (ret)
+			return ret;
+	} else
+		set_bit(gpe, acpi_masked_gpes_map);
 
 	return 1;
 }
@@ -860,13 +864,11 @@ void acpi_irq_stats_init(void)
 	num_gpes = acpi_current_gpe_count;
 	num_counters = num_gpes + ACPI_NUM_FIXED_EVENTS + NUM_COUNTERS_EXTRA;
 
-	all_attrs = kcalloc(num_counters + 1, sizeof(struct attribute *),
-			    GFP_KERNEL);
+	all_attrs = kcalloc(num_counters + 1, sizeof(*all_attrs), GFP_KERNEL);
 	if (all_attrs == NULL)
 		return;
 
-	all_counters = kcalloc(num_counters, sizeof(struct event_counter),
-			       GFP_KERNEL);
+	all_counters = kcalloc(num_counters, sizeof(*all_counters), GFP_KERNEL);
 	if (all_counters == NULL)
 		goto fail;
 
@@ -874,8 +876,7 @@ void acpi_irq_stats_init(void)
 	if (ACPI_FAILURE(status))
 		goto fail;
 
-	counter_attrs = kcalloc(num_counters, sizeof(struct kobj_attribute),
-				GFP_KERNEL);
+	counter_attrs = kcalloc(num_counters, sizeof(*counter_attrs), GFP_KERNEL);
 	if (counter_attrs == NULL)
 		goto fail;
 
@@ -925,7 +926,6 @@ void acpi_irq_stats_init(void)
 
 fail:
 	delete_gpe_attr_array();
-	return;
 }
 
 static void __exit interrupt_stats_exit(void)
@@ -933,31 +933,24 @@ static void __exit interrupt_stats_exit(void)
 	sysfs_remove_group(acpi_kobj, &interrupt_stats_attr_group);
 
 	delete_gpe_attr_array();
-
-	return;
 }
 
-static ssize_t
-acpi_show_profile(struct device *dev, struct device_attribute *attr,
-		  char *buf)
+static ssize_t pm_profile_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
 {
 	return sprintf(buf, "%d\n", acpi_gbl_FADT.preferred_profile);
 }
 
-static const struct device_attribute pm_profile_attr =
-	__ATTR(pm_profile, S_IRUGO, acpi_show_profile, NULL);
+static const struct kobj_attribute pm_profile_attr = __ATTR_RO(pm_profile);
 
-static ssize_t hotplug_enabled_show(struct kobject *kobj,
-				    struct kobj_attribute *attr, char *buf)
+static ssize_t enabled_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
 {
 	struct acpi_hotplug_profile *hotplug = to_acpi_hotplug_profile(kobj);
 
 	return sprintf(buf, "%d\n", hotplug->enabled);
 }
 
-static ssize_t hotplug_enabled_store(struct kobject *kobj,
-				     struct kobj_attribute *attr,
-				     const char *buf, size_t size)
+static ssize_t enabled_store(struct kobject *kobj, struct kobj_attribute *attr,
+			     const char *buf, size_t size)
 {
 	struct acpi_hotplug_profile *hotplug = to_acpi_hotplug_profile(kobj);
 	unsigned int val;
@@ -969,18 +962,17 @@ static ssize_t hotplug_enabled_store(struct kobject *kobj,
 	return size;
 }
 
-static struct kobj_attribute hotplug_enabled_attr =
-	__ATTR(enabled, S_IRUGO | S_IWUSR, hotplug_enabled_show,
-		hotplug_enabled_store);
+static struct kobj_attribute hotplug_enabled_attr = __ATTR_RW(enabled);
 
 static struct attribute *hotplug_profile_attrs[] = {
 	&hotplug_enabled_attr.attr,
 	NULL
 };
+ATTRIBUTE_GROUPS(hotplug_profile);
 
-static struct kobj_type acpi_hotplug_profile_ktype = {
+static const struct kobj_type acpi_hotplug_profile_ktype = {
 	.sysfs_ops = &kobj_sysfs_ops,
-	.default_attrs = hotplug_profile_attrs,
+	.default_groups = hotplug_profile_groups,
 };
 
 void acpi_sysfs_add_hotplug_profile(struct acpi_hotplug_profile *hotplug,
@@ -993,14 +985,16 @@ void acpi_sysfs_add_hotplug_profile(struct acpi_hotplug_profile *hotplug,
 
 	error = kobject_init_and_add(&hotplug->kobj,
 		&acpi_hotplug_profile_ktype, hotplug_kobj, "%s", name);
-	if (error)
+	if (error) {
+		kobject_put(&hotplug->kobj);
 		goto err_out;
+	}
 
 	kobject_uevent(&hotplug->kobj, KOBJ_ADD);
 	return;
 
  err_out:
-	pr_err(PREFIX "Unable to add hotplug profile '%s'\n", name);
+	pr_err("Unable to add hotplug profile '%s'\n", name);
 }
 
 static ssize_t force_remove_show(struct kobject *kobj,
@@ -1016,7 +1010,7 @@ static ssize_t force_remove_store(struct kobject *kobj,
 	bool val;
 	int ret;
 
-	ret = strtobool(buf, &val);
+	ret = kstrtobool(buf, &val);
 	if (ret < 0)
 		return ret;
 
@@ -1027,9 +1021,7 @@ static ssize_t force_remove_store(struct kobject *kobj,
 	return size;
 }
 
-static const struct kobj_attribute force_remove_attr =
-	__ATTR(force_remove, S_IRUGO | S_IWUSR, force_remove_show,
-	       force_remove_store);
+static const struct kobj_attribute force_remove_attr = __ATTR_RW(force_remove);
 
 int __init acpi_sysfs_init(void)
 {
diff --git a/drivers/acpi/tables.c b/drivers/acpi/tables.c
index 0e905c3d1645..4286e4af1092 100644
--- a/drivers/acpi/tables.c
+++ b/drivers/acpi/tables.c
@@ -21,6 +21,7 @@
 #include <linux/earlycpio.h>
 #include <linux/initrd.h>
 #include <linux/security.h>
+#include <linux/kmemleak.h>
 #include "internal.h"
 
 #ifdef CONFIG_ACPI_CUSTOM_DSDT
@@ -34,23 +35,13 @@ static char *mps_inti_flags_trigger[] = { "dfl", "edge", "res", "level" };
 
 static struct acpi_table_desc initial_tables[ACPI_MAX_TABLES] __initdata;
 
-static int acpi_apic_instance __initdata;
-
-enum acpi_subtable_type {
-	ACPI_SUBTABLE_COMMON,
-	ACPI_SUBTABLE_HMAT,
-};
-
-struct acpi_subtable_entry {
-	union acpi_subtable_headers *hdr;
-	enum acpi_subtable_type type;
-};
+static int acpi_apic_instance __initdata_or_acpilib;
 
 /*
  * Disable table checksum verification for the early stage due to the size
  * limitation of the current x86 early mapping implementation.
  */
-static bool acpi_verify_table_checksum __initdata = false;
+static bool acpi_verify_table_checksum __initdata_or_acpilib = false;
 
 void acpi_table_print_madt_entry(struct acpi_subtable_header *header)
 {
@@ -65,7 +56,7 @@ void acpi_table_print_madt_entry(struct acpi_subtable_header *header)
 			    (struct acpi_madt_local_apic *)header;
 			pr_debug("LAPIC (acpi_id[0x%02x] lapic_id[0x%02x] %s)\n",
 				 p->processor_id, p->id,
-				 (p->lapic_flags & ACPI_MADT_ENABLED) ? "enabled" : "disabled");
+				 str_enabled_disabled(p->lapic_flags & ACPI_MADT_ENABLED));
 		}
 		break;
 
@@ -75,7 +66,7 @@ void acpi_table_print_madt_entry(struct acpi_subtable_header *header)
 			    (struct acpi_madt_local_x2apic *)header;
 			pr_debug("X2APIC (apic_id[0x%02x] uid[0x%02x] %s)\n",
 				 p->local_apic_id, p->uid,
-				 (p->lapic_flags & ACPI_MADT_ENABLED) ? "enabled" : "disabled");
+				 str_enabled_disabled(p->lapic_flags & ACPI_MADT_ENABLED));
 		}
 		break;
 
@@ -148,8 +139,8 @@ void acpi_table_print_madt_entry(struct acpi_subtable_header *header)
 		{
 			struct acpi_madt_local_apic_override *p =
 			    (struct acpi_madt_local_apic_override *)header;
-			pr_info("LAPIC_ADDR_OVR (address[%p])\n",
-				(void *)(unsigned long)p->address);
+			pr_info("LAPIC_ADDR_OVR (address[0x%llx])\n",
+				p->address);
 		}
 		break;
 
@@ -169,7 +160,7 @@ void acpi_table_print_madt_entry(struct acpi_subtable_header *header)
 			    (struct acpi_madt_local_sapic *)header;
 			pr_debug("LSAPIC (acpi_id[0x%02x] lsapic_id[0x%02x] lsapic_eid[0x%02x] %s)\n",
 				 p->processor_id, p->id, p->eid,
-				 (p->lapic_flags & ACPI_MADT_ENABLED) ? "enabled" : "disabled");
+				 str_enabled_disabled(p->lapic_flags & ACPI_MADT_ENABLED));
 		}
 		break;
 
@@ -192,7 +183,7 @@ void acpi_table_print_madt_entry(struct acpi_subtable_header *header)
 			pr_debug("GICC (acpi_id[0x%04x] address[%llx] MPIDR[0x%llx] %s)\n",
 				 p->uid, p->base_address,
 				 p->arm_mpidr,
-				 (p->flags & ACPI_MADT_ENABLED) ? "enabled" : "disabled");
+				 str_enabled_disabled(p->flags & ACPI_MADT_ENABLED));
 
 		}
 		break;
@@ -207,159 +198,50 @@ void acpi_table_print_madt_entry(struct acpi_subtable_header *header)
 		}
 		break;
 
-	default:
-		pr_warn("Found unsupported MADT entry (type = 0x%x)\n",
-			header->type);
-		break;
-	}
-}
-
-static unsigned long __init
-acpi_get_entry_type(struct acpi_subtable_entry *entry)
-{
-	switch (entry->type) {
-	case ACPI_SUBTABLE_COMMON:
-		return entry->hdr->common.type;
-	case ACPI_SUBTABLE_HMAT:
-		return entry->hdr->hmat.type;
-	}
-	return 0;
-}
-
-static unsigned long __init
-acpi_get_entry_length(struct acpi_subtable_entry *entry)
-{
-	switch (entry->type) {
-	case ACPI_SUBTABLE_COMMON:
-		return entry->hdr->common.length;
-	case ACPI_SUBTABLE_HMAT:
-		return entry->hdr->hmat.length;
-	}
-	return 0;
-}
-
-static unsigned long __init
-acpi_get_subtable_header_length(struct acpi_subtable_entry *entry)
-{
-	switch (entry->type) {
-	case ACPI_SUBTABLE_COMMON:
-		return sizeof(entry->hdr->common);
-	case ACPI_SUBTABLE_HMAT:
-		return sizeof(entry->hdr->hmat);
-	}
-	return 0;
-}
-
-static enum acpi_subtable_type __init
-acpi_get_subtable_type(char *id)
-{
-	if (strncmp(id, ACPI_SIG_HMAT, 4) == 0)
-		return ACPI_SUBTABLE_HMAT;
-	return ACPI_SUBTABLE_COMMON;
-}
-
-/**
- * acpi_parse_entries_array - for each proc_num find a suitable subtable
- *
- * @id: table id (for debugging purposes)
- * @table_size: size of the root table
- * @table_header: where does the table start?
- * @proc: array of acpi_subtable_proc struct containing entry id
- *        and associated handler with it
- * @proc_num: how big proc is?
- * @max_entries: how many entries can we process?
- *
- * For each proc_num find a subtable with proc->id and run proc->handler
- * on it. Assumption is that there's only single handler for particular
- * entry id.
- *
- * The table_size is not the size of the complete ACPI table (the length
- * field in the header struct), but only the size of the root table; i.e.,
- * the offset from the very first byte of the complete ACPI table, to the
- * first byte of the very first subtable.
- *
- * On success returns sum of all matching entries for all proc handlers.
- * Otherwise, -ENODEV or -EINVAL is returned.
- */
-static int __init acpi_parse_entries_array(char *id, unsigned long table_size,
-		struct acpi_table_header *table_header,
-		struct acpi_subtable_proc *proc, int proc_num,
-		unsigned int max_entries)
-{
-	struct acpi_subtable_entry entry;
-	unsigned long table_end, subtable_len, entry_len;
-	int count = 0;
-	int errs = 0;
-	int i;
-
-	if (acpi_disabled)
-		return -ENODEV;
-
-	if (!id)
-		return -EINVAL;
-
-	if (!table_size)
-		return -EINVAL;
-
-	if (!table_header) {
-		pr_warn("%4.4s not present\n", id);
-		return -ENODEV;
-	}
-
-	table_end = (unsigned long)table_header + table_header->length;
-
-	/* Parse all entries looking for a match. */
+	case ACPI_MADT_TYPE_MULTIPROC_WAKEUP:
+		{
+			struct acpi_madt_multiproc_wakeup *p =
+				(struct acpi_madt_multiproc_wakeup *)header;
+			u64 reset_vector = 0;
 
-	entry.type = acpi_get_subtable_type(id);
-	entry.hdr = (union acpi_subtable_headers *)
-	    ((unsigned long)table_header + table_size);
-	subtable_len = acpi_get_subtable_header_length(&entry);
+			if (p->version >= ACPI_MADT_MP_WAKEUP_VERSION_V1)
+				reset_vector = p->reset_vector;
 
-	while (((unsigned long)entry.hdr) + subtable_len  < table_end) {
-		if (max_entries && count >= max_entries)
-			break;
+			pr_debug("MP Wakeup (version[%d], mailbox[%#llx], reset[%#llx])\n",
+				 p->version, p->mailbox_address, reset_vector);
+		}
+		break;
 
-		for (i = 0; i < proc_num; i++) {
-			if (acpi_get_entry_type(&entry) != proc[i].id)
-				continue;
-			if (!proc[i].handler ||
-			     (!errs && proc[i].handler(entry.hdr, table_end))) {
-				errs++;
-				continue;
-			}
+	case ACPI_MADT_TYPE_CORE_PIC:
+		{
+			struct acpi_madt_core_pic *p = (struct acpi_madt_core_pic *)header;
 
-			proc[i].count++;
-			break;
+			pr_debug("CORE PIC (processor_id[0x%02x] core_id[0x%02x] %s)\n",
+				 p->processor_id, p->core_id,
+				 str_enabled_disabled(p->flags & ACPI_MADT_ENABLED));
 		}
-		if (i != proc_num)
-			count++;
+		break;
 
-		/*
-		 * If entry->length is 0, break from this loop to avoid
-		 * infinite loop.
-		 */
-		entry_len = acpi_get_entry_length(&entry);
-		if (entry_len == 0) {
-			pr_err("[%4.4s:0x%02x] Invalid zero length\n", id, proc->id);
-			return -EINVAL;
-		}
+	case ACPI_MADT_TYPE_RINTC:
+		{
+			struct acpi_madt_rintc *p = (struct acpi_madt_rintc *)header;
 
-		entry.hdr = (union acpi_subtable_headers *)
-		    ((unsigned long)entry.hdr + entry_len);
-	}
+			pr_debug("RISC-V INTC (acpi_uid[0x%04x] hart_id[0x%llx] %s)\n",
+				 p->uid, p->hart_id,
+				 str_enabled_disabled(p->flags & ACPI_MADT_ENABLED));
+		}
+		break;
 
-	if (max_entries && count > max_entries) {
-		pr_warn("[%4.4s:0x%02x] found the maximum %i entries\n",
-			id, proc->id, count);
+	default:
+		pr_warn("Found unsupported MADT entry (type = 0x%x)\n",
+			header->type);
+		break;
 	}
-
-	return errs ? -EINVAL : count;
 }
 
-int __init acpi_table_parse_entries_array(char *id,
-			 unsigned long table_size,
-			 struct acpi_subtable_proc *proc, int proc_num,
-			 unsigned int max_entries)
+int __init_or_acpilib acpi_table_parse_entries_array(
+	char *id, unsigned long table_size, struct acpi_subtable_proc *proc,
+	int proc_num, unsigned int max_entries)
 {
 	struct acpi_table_header *table_header = NULL;
 	int count;
@@ -371,37 +253,61 @@ int __init acpi_table_parse_entries_array(char *id,
 	if (!id)
 		return -EINVAL;
 
+	if (!table_size)
+		return -EINVAL;
+
 	if (!strncmp(id, ACPI_SIG_MADT, 4))
 		instance = acpi_apic_instance;
 
 	acpi_get_table(id, instance, &table_header);
 	if (!table_header) {
-		pr_warn("%4.4s not present\n", id);
+		pr_debug("%4.4s not present\n", id);
 		return -ENODEV;
 	}
 
-	count = acpi_parse_entries_array(id, table_size, table_header,
-			proc, proc_num, max_entries);
+	count = acpi_parse_entries_array(id, table_size,
+					 (union fw_table_header *)table_header,
+					 0, proc, proc_num, max_entries);
 
 	acpi_put_table(table_header);
 	return count;
 }
 
-int __init acpi_table_parse_entries(char *id,
-			unsigned long table_size,
-			int entry_id,
-			acpi_tbl_entry_handler handler,
-			unsigned int max_entries)
+static int __init_or_acpilib __acpi_table_parse_entries(
+	char *id, unsigned long table_size, int entry_id,
+	acpi_tbl_entry_handler handler, acpi_tbl_entry_handler_arg handler_arg,
+	void *arg, unsigned int max_entries)
 {
 	struct acpi_subtable_proc proc = {
 		.id		= entry_id,
 		.handler	= handler,
+		.handler_arg	= handler_arg,
+		.arg		= arg,
 	};
 
 	return acpi_table_parse_entries_array(id, table_size, &proc, 1,
 						max_entries);
 }
 
+int __init_or_acpilib
+acpi_table_parse_cedt(enum acpi_cedt_type id,
+		      acpi_tbl_entry_handler_arg handler_arg, void *arg)
+{
+	return __acpi_table_parse_entries(ACPI_SIG_CEDT,
+					  sizeof(struct acpi_table_cedt), id,
+					  NULL, handler_arg, arg, 0);
+}
+EXPORT_SYMBOL_ACPI_LIB(acpi_table_parse_cedt);
+
+int __init acpi_table_parse_entries(char *id, unsigned long table_size,
+				    int entry_id,
+				    acpi_tbl_entry_handler handler,
+				    unsigned int max_entries)
+{
+	return __acpi_table_parse_entries(id, table_size, entry_id, handler,
+					  NULL, NULL, max_entries);
+}
+
 int __init acpi_table_parse_madt(enum acpi_madt_type id,
 		      acpi_tbl_entry_handler handler, unsigned int max_entries)
 {
@@ -490,7 +396,7 @@ static u8 __init acpi_table_checksum(u8 *buffer, u32 length)
 }
 
 /* All but ACPI_SIG_RSDP and ACPI_SIG_FACS: */
-static const char * const table_sigs[] = {
+static const char table_sigs[][ACPI_NAMESEG_SIZE] __nonstring_array __initconst = {
 	ACPI_SIG_BERT, ACPI_SIG_BGRT, ACPI_SIG_CPEP, ACPI_SIG_ECDT,
 	ACPI_SIG_EINJ, ACPI_SIG_ERST, ACPI_SIG_HEST, ACPI_SIG_MADT,
 	ACPI_SIG_MSCT, ACPI_SIG_SBST, ACPI_SIG_SLIT, ACPI_SIG_SRAT,
@@ -501,7 +407,8 @@ static const char * const table_sigs[] = {
 	ACPI_SIG_WDDT, ACPI_SIG_WDRT, ACPI_SIG_DSDT, ACPI_SIG_FADT,
 	ACPI_SIG_PSDT, ACPI_SIG_RSDT, ACPI_SIG_XSDT, ACPI_SIG_SSDT,
 	ACPI_SIG_IORT, ACPI_SIG_NFIT, ACPI_SIG_HMAT, ACPI_SIG_PPTT,
-	ACPI_SIG_NHLT, NULL };
+	ACPI_SIG_NHLT, ACPI_SIG_AEST, ACPI_SIG_CEDT, ACPI_SIG_AGDI,
+	ACPI_SIG_NBFT, ACPI_SIG_SWFT, ACPI_SIG_MPAM};
 
 #define ACPI_HEADER_SIZE sizeof(struct acpi_table_header)
 
@@ -548,11 +455,11 @@ void __init acpi_table_upgrade(void)
 
 		table = file.data;
 
-		for (sig = 0; table_sigs[sig]; sig++)
+		for (sig = 0; sig < ARRAY_SIZE(table_sigs); sig++)
 			if (!memcmp(table->signature, table_sigs[sig], 4))
 				break;
 
-		if (!table_sigs[sig]) {
+		if (sig >= ARRAY_SIZE(table_sigs)) {
 			pr_err("ACPI OVERRIDE: Unknown signature [%s%s]\n",
 				cpio_path, file.name);
 			continue;
@@ -585,8 +492,8 @@ void __init acpi_table_upgrade(void)
 	}
 
 	acpi_tables_addr =
-		memblock_find_in_range(0, ACPI_TABLE_UPGRADE_MAX_PHYS,
-				       all_tables_size, PAGE_SIZE);
+		memblock_phys_alloc_range(all_tables_size, PAGE_SIZE,
+					  0, ACPI_TABLE_UPGRADE_MAX_PHYS);
 	if (!acpi_tables_addr) {
 		WARN_ON(1);
 		return;
@@ -601,9 +508,10 @@ void __init acpi_table_upgrade(void)
 	 * Both memblock_reserve and e820__range_add (via arch_reserve_mem_area)
 	 * works fine.
 	 */
-	memblock_reserve(acpi_tables_addr, all_tables_size);
 	arch_reserve_mem_area(acpi_tables_addr, all_tables_size);
 
+	kmemleak_ignore_phys(acpi_tables_addr);
+
 	/*
 	 * early_ioremap only can remap 256k one time. If we map all
 	 * tables one time, we will hit the limit. Need to map chunks
@@ -723,7 +631,7 @@ static void __init acpi_table_initrd_scan(void)
 		/*
 		 * Mark the table to avoid being used in
 		 * acpi_table_initrd_override(). Though this is not possible
-		 * because override is disabled in acpi_install_table().
+		 * because override is disabled in acpi_install_physical_table().
 		 */
 		if (test_and_set_bit(table_index, acpi_initrd_installed)) {
 			acpi_os_unmap_memory(table, ACPI_HEADER_SIZE);
@@ -734,7 +642,7 @@ static void __init acpi_table_initrd_scan(void)
 			table->signature, table->oem_id,
 			table->oem_table_id);
 		acpi_os_unmap_memory(table, ACPI_HEADER_SIZE);
-		acpi_install_table(acpi_tables_addr + table_offset, TRUE);
+		acpi_install_physical_table(acpi_tables_addr + table_offset);
 next_table:
 		table_offset += table_length;
 		table_index++;
@@ -791,15 +699,14 @@ acpi_status acpi_os_table_override(struct acpi_table_header *existing_table,
 }
 
 /*
- * acpi_table_init()
+ * acpi_locate_initial_tables()
  *
- * find RSDP, find and checksum SDT/XSDT.
- * checksum all tables, print SDT/XSDT
+ * Get the RSDP, then find and checksum all the ACPI tables.
  *
- * result: sdt_entry[] is initialized
+ * result: initial_tables[] is initialized, and points to
+ * a list of ACPI tables.
  */
-
-int __init acpi_table_init(void)
+int __init acpi_locate_initial_tables(void)
 {
 	acpi_status status;
 
@@ -812,11 +719,51 @@ int __init acpi_table_init(void)
 	}
 
 	status = acpi_initialize_tables(initial_tables, ACPI_MAX_TABLES, 0);
-	if (ACPI_FAILURE(status))
+	if (ACPI_FAILURE(status)) {
+		const char *msg = acpi_format_exception(status);
+
+		pr_warn("Failed to initialize tables, status=0x%x (%s)", status, msg);
 		return -EINVAL;
-	acpi_table_initrd_scan();
+	}
+
+	return 0;
+}
+
+void __init acpi_reserve_initial_tables(void)
+{
+	int i;
+
+	for (i = 0; i < ACPI_MAX_TABLES; i++) {
+		struct acpi_table_desc *table_desc = &initial_tables[i];
+		u64 start = table_desc->address;
+		u64 size = table_desc->length;
+
+		if (!start || !size)
+			break;
 
+		pr_info("Reserving %4s table memory at [mem 0x%llx-0x%llx]\n",
+			table_desc->signature.ascii, start, start + size - 1);
+
+		memblock_reserve(start, size);
+	}
+}
+
+void __init acpi_table_init_complete(void)
+{
+	acpi_table_initrd_scan();
 	check_multiple_madt();
+}
+
+int __init acpi_table_init(void)
+{
+	int ret;
+
+	ret = acpi_locate_initial_tables();
+	if (ret)
+		return ret;
+
+	acpi_table_init_complete();
+
 	return 0;
 }
 
diff --git a/drivers/acpi/thermal.c b/drivers/acpi/thermal.c
index 19067a5e5293..a511f9ea0267 100644
--- a/drivers/acpi/thermal.c
+++ b/drivers/acpi/thermal.c
@@ -13,6 +13,8 @@
  *          concepts of 'multiple limiters', upper/lower limits, etc.
  */
 
+#define pr_fmt(fmt) "ACPI: thermal: " fmt
+
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/dmi.h>
@@ -29,7 +31,7 @@
 #include <linux/uaccess.h>
 #include <linux/units.h>
 
-#define PREFIX "ACPI: "
+#include "internal.h"
 
 #define ACPI_THERMAL_CLASS		"thermal_zone"
 #define ACPI_THERMAL_DEVICE_NAME	"Thermal Zone"
@@ -40,15 +42,26 @@
 #define ACPI_THERMAL_NOTIFY_HOT		0xF1
 #define ACPI_THERMAL_MODE_ACTIVE	0x00
 
-#define ACPI_THERMAL_MAX_ACTIVE	10
-#define ACPI_THERMAL_MAX_LIMIT_STR_LEN 65
+#define ACPI_THERMAL_MAX_ACTIVE		10
+#define ACPI_THERMAL_MAX_LIMIT_STR_LEN	65
 
-#define _COMPONENT		ACPI_THERMAL_COMPONENT
-ACPI_MODULE_NAME("thermal");
+#define ACPI_THERMAL_TRIP_PASSIVE	(-1)
 
-MODULE_AUTHOR("Paul Diefenbaugh");
-MODULE_DESCRIPTION("ACPI Thermal Zone Driver");
-MODULE_LICENSE("GPL");
+#define ACPI_THERMAL_MAX_NR_TRIPS	(ACPI_THERMAL_MAX_ACTIVE + 3)
+
+/*
+ * This exception is thrown out in two cases:
+ * 1.An invalid trip point becomes invalid or a valid trip point becomes invalid
+ *   when re-evaluating the AML code.
+ * 2.TODO: Devices listed in _PSL, _ALx, _TZD may change.
+ *   We need to re-bind the cooling devices of a thermal zone when this occurs.
+ */
+#define ACPI_THERMAL_TRIPS_EXCEPTION(tz, str) \
+do { \
+	acpi_handle_info(tz->device->handle, \
+			 "ACPI thermal trip point %s changed\n" \
+			 "Please report to linux-acpi@vger.kernel.org\n", str); \
+} while (0)
 
 static int act;
 module_param(act, int, 0644);
@@ -62,10 +75,6 @@ static int tzp;
 module_param(tzp, int, 0444);
 MODULE_PARM_DESC(tzp, "Thermal zone polling frequency, in 1/10 seconds.");
 
-static int nocrt;
-module_param(nocrt, int, 0);
-MODULE_PARM_DESC(nocrt, "Set to take no action upon ACPI thermal zone critical trips points.");
-
 static int off;
 module_param(off, int, 0);
 MODULE_PARM_DESC(off, "Set to disable ACPI thermal support.");
@@ -76,105 +85,40 @@ MODULE_PARM_DESC(psv, "Disable or override all passive trip points.");
 
 static struct workqueue_struct *acpi_thermal_pm_queue;
 
-static int acpi_thermal_add(struct acpi_device *device);
-static int acpi_thermal_remove(struct acpi_device *device);
-static void acpi_thermal_notify(struct acpi_device *device, u32 event);
-
-static const struct acpi_device_id  thermal_device_ids[] = {
-	{ACPI_THERMAL_HID, 0},
-	{"", 0},
-};
-MODULE_DEVICE_TABLE(acpi, thermal_device_ids);
-
-#ifdef CONFIG_PM_SLEEP
-static int acpi_thermal_suspend(struct device *dev);
-static int acpi_thermal_resume(struct device *dev);
-#else
-#define acpi_thermal_suspend NULL
-#define acpi_thermal_resume NULL
-#endif
-static SIMPLE_DEV_PM_OPS(acpi_thermal_pm, acpi_thermal_suspend, acpi_thermal_resume);
-
-static struct acpi_driver acpi_thermal_driver = {
-	.name = "thermal",
-	.class = ACPI_THERMAL_CLASS,
-	.ids = thermal_device_ids,
-	.ops = {
-		.add = acpi_thermal_add,
-		.remove = acpi_thermal_remove,
-		.notify = acpi_thermal_notify,
-		},
-	.drv.pm = &acpi_thermal_pm,
-};
-
-struct acpi_thermal_state {
-	u8 critical:1;
-	u8 hot:1;
-	u8 passive:1;
-	u8 active:1;
-	u8 reserved:4;
-	int active_index;
-};
-
-struct acpi_thermal_state_flags {
-	u8 valid:1;
-	u8 enabled:1;
-	u8 reserved:6;
-};
-
-struct acpi_thermal_critical {
-	struct acpi_thermal_state_flags flags;
-	unsigned long temperature;
-};
-
-struct acpi_thermal_hot {
-	struct acpi_thermal_state_flags flags;
-	unsigned long temperature;
+struct acpi_thermal_trip {
+	unsigned long temp_dk;
+	struct acpi_handle_list devices;
 };
 
 struct acpi_thermal_passive {
-	struct acpi_thermal_state_flags flags;
-	unsigned long temperature;
+	struct acpi_thermal_trip trip;
 	unsigned long tc1;
 	unsigned long tc2;
-	unsigned long tsp;
-	struct acpi_handle_list devices;
+	unsigned long delay;
 };
 
 struct acpi_thermal_active {
-	struct acpi_thermal_state_flags flags;
-	unsigned long temperature;
-	struct acpi_handle_list devices;
+	struct acpi_thermal_trip trip;
 };
 
 struct acpi_thermal_trips {
-	struct acpi_thermal_critical critical;
-	struct acpi_thermal_hot hot;
 	struct acpi_thermal_passive passive;
 	struct acpi_thermal_active active[ACPI_THERMAL_MAX_ACTIVE];
 };
 
-struct acpi_thermal_flags {
-	u8 cooling_mode:1;	/* _SCP */
-	u8 devices:1;		/* _TZD */
-	u8 reserved:6;
-};
-
 struct acpi_thermal {
-	struct acpi_device * device;
+	struct acpi_device *device;
 	acpi_bus_id name;
-	unsigned long temperature;
-	unsigned long last_temperature;
+	unsigned long temp_dk;
+	unsigned long last_temp_dk;
 	unsigned long polling_frequency;
 	volatile u8 zombie;
-	struct acpi_thermal_flags flags;
-	struct acpi_thermal_state state;
 	struct acpi_thermal_trips trips;
-	struct acpi_handle_list devices;
 	struct thermal_zone_device *thermal_zone;
-	int tz_enabled;
 	int kelvin_offset;	/* in millidegrees */
 	struct work_struct thermal_check_work;
+	struct mutex thermal_check_lock;
+	refcount_t thermal_check_count;
 };
 
 /* --------------------------------------------------------------------------
@@ -189,15 +133,16 @@ static int acpi_thermal_get_temperature(struct acpi_thermal *tz)
 	if (!tz)
 		return -EINVAL;
 
-	tz->last_temperature = tz->temperature;
+	tz->last_temp_dk = tz->temp_dk;
 
 	status = acpi_evaluate_integer(tz->device->handle, "_TMP", NULL, &tmp);
 	if (ACPI_FAILURE(status))
 		return -ENODEV;
 
-	tz->temperature = tmp;
-	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Temperature is %lu dK\n",
-			  tz->temperature));
+	tz->temp_dk = tmp;
+
+	acpi_handle_debug(tz->device->handle, "Temperature is %lu dK\n",
+			  tz->temp_dk);
 
 	return 0;
 }
@@ -215,718 +160,507 @@ static int acpi_thermal_get_polling_frequency(struct acpi_thermal *tz)
 		return -ENODEV;
 
 	tz->polling_frequency = tmp;
-	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Polling frequency is %lu dS\n",
-			  tz->polling_frequency));
+	acpi_handle_debug(tz->device->handle, "Polling frequency is %lu dS\n",
+			  tz->polling_frequency);
 
 	return 0;
 }
 
-static int acpi_thermal_set_cooling_mode(struct acpi_thermal *tz, int mode)
+static int acpi_thermal_temp(struct acpi_thermal *tz, int temp_deci_k)
 {
-	if (!tz)
-		return -EINVAL;
+	int temp;
 
-	if (ACPI_FAILURE(acpi_execute_simple_method(tz->device->handle,
-						    "_SCP", mode)))
-		return -ENODEV;
+	if (temp_deci_k == THERMAL_TEMP_INVALID)
+		return THERMAL_TEMP_INVALID;
 
-	return 0;
+	temp = deci_kelvin_to_millicelsius_with_offset(temp_deci_k,
+						       tz->kelvin_offset);
+	if (temp <= 0)
+		return THERMAL_TEMP_INVALID;
+
+	return temp;
 }
 
-#define ACPI_TRIPS_CRITICAL	0x01
-#define ACPI_TRIPS_HOT		0x02
-#define ACPI_TRIPS_PASSIVE	0x04
-#define ACPI_TRIPS_ACTIVE	0x08
-#define ACPI_TRIPS_DEVICES	0x10
+static bool acpi_thermal_trip_valid(struct acpi_thermal_trip *acpi_trip)
+{
+	return acpi_trip->temp_dk != THERMAL_TEMP_INVALID;
+}
 
-#define ACPI_TRIPS_REFRESH_THRESHOLDS	(ACPI_TRIPS_PASSIVE | ACPI_TRIPS_ACTIVE)
-#define ACPI_TRIPS_REFRESH_DEVICES	ACPI_TRIPS_DEVICES
+static int active_trip_index(struct acpi_thermal *tz,
+			     struct acpi_thermal_trip *acpi_trip)
+{
+	struct acpi_thermal_active *active;
 
-#define ACPI_TRIPS_INIT      (ACPI_TRIPS_CRITICAL | ACPI_TRIPS_HOT |	\
-			      ACPI_TRIPS_PASSIVE | ACPI_TRIPS_ACTIVE |	\
-			      ACPI_TRIPS_DEVICES)
+	active = container_of(acpi_trip, struct acpi_thermal_active, trip);
+	return active - tz->trips.active;
+}
 
-/*
- * This exception is thrown out in two cases:
- * 1.An invalid trip point becomes invalid or a valid trip point becomes invalid
- *   when re-evaluating the AML code.
- * 2.TODO: Devices listed in _PSL, _ALx, _TZD may change.
- *   We need to re-bind the cooling devices of a thermal zone when this occurs.
- */
-#define ACPI_THERMAL_TRIPS_EXCEPTION(flags, str)	\
-do {	\
-	if (flags != ACPI_TRIPS_INIT)	\
-		ACPI_EXCEPTION((AE_INFO, AE_ERROR,	\
-		"ACPI thermal trip point %s changed\n"	\
-		"Please send acpidump to linux-acpi@vger.kernel.org", str)); \
-} while (0)
+static long get_passive_temp(struct acpi_thermal *tz)
+{
+	int temp;
+
+	if (acpi_passive_trip_temp(tz->device, &temp))
+		return THERMAL_TEMP_INVALID;
+
+	return temp;
+}
 
-static int acpi_thermal_trips_update(struct acpi_thermal *tz, int flag)
+static long get_active_temp(struct acpi_thermal *tz, int index)
 {
-	acpi_status status = AE_OK;
-	unsigned long long tmp;
-	struct acpi_handle_list devices;
-	int valid = 0;
-	int i;
+	int temp;
 
-	/* Critical Shutdown */
-	if (flag & ACPI_TRIPS_CRITICAL) {
-		status = acpi_evaluate_integer(tz->device->handle,
-				"_CRT", NULL, &tmp);
-		tz->trips.critical.temperature = tmp;
-		/*
-		 * Treat freezing temperatures as invalid as well; some
-		 * BIOSes return really low values and cause reboots at startup.
-		 * Below zero (Celsius) values clearly aren't right for sure..
-		 * ... so lets discard those as invalid.
-		 */
-		if (ACPI_FAILURE(status)) {
-			tz->trips.critical.flags.valid = 0;
-			ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-					  "No critical threshold\n"));
-		} else if (tmp <= 2732) {
-			pr_warn(FW_BUG "Invalid critical threshold (%llu)\n",
-				tmp);
-			tz->trips.critical.flags.valid = 0;
-		} else {
-			tz->trips.critical.flags.valid = 1;
-			ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-					  "Found critical threshold [%lu]\n",
-					  tz->trips.critical.temperature));
-		}
-		if (tz->trips.critical.flags.valid == 1) {
-			if (crt == -1) {
-				tz->trips.critical.flags.valid = 0;
-			} else if (crt > 0) {
-				unsigned long crt_k = celsius_to_deci_kelvin(crt);
-
-				/*
-				 * Allow override critical threshold
-				 */
-				if (crt_k > tz->trips.critical.temperature)
-					pr_warn(PREFIX "Critical threshold %d C\n",
-						crt);
-				tz->trips.critical.temperature = crt_k;
-			}
-		}
-	}
+	if (acpi_active_trip_temp(tz->device, index, &temp))
+		return THERMAL_TEMP_INVALID;
 
-	/* Critical Sleep (optional) */
-	if (flag & ACPI_TRIPS_HOT) {
-		status = acpi_evaluate_integer(tz->device->handle,
-				"_HOT", NULL, &tmp);
-		if (ACPI_FAILURE(status)) {
-			tz->trips.hot.flags.valid = 0;
-			ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-					"No hot threshold\n"));
-		} else {
-			tz->trips.hot.temperature = tmp;
-			tz->trips.hot.flags.valid = 1;
-			ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-					"Found hot threshold [%lu]\n",
-					tz->trips.hot.temperature));
-		}
-	}
+	/*
+	 * If an override has been provided, apply it so there are no active
+	 * trips with thresholds greater than the override.
+	 */
+	if (act > 0) {
+		unsigned long long override = celsius_to_deci_kelvin(act);
 
-	/* Passive (optional) */
-	if (((flag & ACPI_TRIPS_PASSIVE) && tz->trips.passive.flags.valid) ||
-		(flag == ACPI_TRIPS_INIT)) {
-		valid = tz->trips.passive.flags.valid;
-		if (psv == -1) {
-			status = AE_SUPPORT;
-		} else if (psv > 0) {
-			tmp = celsius_to_deci_kelvin(psv);
-			status = AE_OK;
-		} else {
-			status = acpi_evaluate_integer(tz->device->handle,
-				"_PSV", NULL, &tmp);
-		}
-
-		if (ACPI_FAILURE(status))
-			tz->trips.passive.flags.valid = 0;
-		else {
-			tz->trips.passive.temperature = tmp;
-			tz->trips.passive.flags.valid = 1;
-			if (flag == ACPI_TRIPS_INIT) {
-				status = acpi_evaluate_integer(
-						tz->device->handle, "_TC1",
-						NULL, &tmp);
-				if (ACPI_FAILURE(status))
-					tz->trips.passive.flags.valid = 0;
-				else
-					tz->trips.passive.tc1 = tmp;
-				status = acpi_evaluate_integer(
-						tz->device->handle, "_TC2",
-						NULL, &tmp);
-				if (ACPI_FAILURE(status))
-					tz->trips.passive.flags.valid = 0;
-				else
-					tz->trips.passive.tc2 = tmp;
-				status = acpi_evaluate_integer(
-						tz->device->handle, "_TSP",
-						NULL, &tmp);
-				if (ACPI_FAILURE(status))
-					tz->trips.passive.flags.valid = 0;
-				else
-					tz->trips.passive.tsp = tmp;
-			}
-		}
-	}
-	if ((flag & ACPI_TRIPS_DEVICES) && tz->trips.passive.flags.valid) {
-		memset(&devices, 0, sizeof(struct acpi_handle_list));
-		status = acpi_evaluate_reference(tz->device->handle, "_PSL",
-							NULL, &devices);
-		if (ACPI_FAILURE(status)) {
-			pr_warn(PREFIX "Invalid passive threshold\n");
-			tz->trips.passive.flags.valid = 0;
-		}
-		else
-			tz->trips.passive.flags.valid = 1;
-
-		if (memcmp(&tz->trips.passive.devices, &devices,
-				sizeof(struct acpi_handle_list))) {
-			memcpy(&tz->trips.passive.devices, &devices,
-				sizeof(struct acpi_handle_list));
-			ACPI_THERMAL_TRIPS_EXCEPTION(flag, "device");
-		}
-	}
-	if ((flag & ACPI_TRIPS_PASSIVE) || (flag & ACPI_TRIPS_DEVICES)) {
-		if (valid != tz->trips.passive.flags.valid)
-				ACPI_THERMAL_TRIPS_EXCEPTION(flag, "state");
+		if (temp > override)
+			return override;
 	}
+	return temp;
+}
 
-	/* Active (optional) */
-	for (i = 0; i < ACPI_THERMAL_MAX_ACTIVE; i++) {
-		char name[5] = { '_', 'A', 'C', ('0' + i), '\0' };
-		valid = tz->trips.active[i].flags.valid;
+static void acpi_thermal_update_trip(struct acpi_thermal *tz,
+				     const struct thermal_trip *trip)
+{
+	struct acpi_thermal_trip *acpi_trip = trip->priv;
 
-		if (act == -1)
-			break; /* disable all active trip points */
-
-		if ((flag == ACPI_TRIPS_INIT) || ((flag & ACPI_TRIPS_ACTIVE) &&
-			tz->trips.active[i].flags.valid)) {
-			status = acpi_evaluate_integer(tz->device->handle,
-							name, NULL, &tmp);
-			if (ACPI_FAILURE(status)) {
-				tz->trips.active[i].flags.valid = 0;
-				if (i == 0)
-					break;
-				if (act <= 0)
-					break;
-				if (i == 1)
-					tz->trips.active[0].temperature =
-						celsius_to_deci_kelvin(act);
-				else
-					/*
-					 * Don't allow override higher than
-					 * the next higher trip point
-					 */
-					tz->trips.active[i - 1].temperature =
-						(tz->trips.active[i - 2].temperature <
-						celsius_to_deci_kelvin(act) ?
-						tz->trips.active[i - 2].temperature :
-						celsius_to_deci_kelvin(act));
-				break;
-			} else {
-				tz->trips.active[i].temperature = tmp;
-				tz->trips.active[i].flags.valid = 1;
-			}
-		}
-
-		name[2] = 'L';
-		if ((flag & ACPI_TRIPS_DEVICES) && tz->trips.active[i].flags.valid ) {
-			memset(&devices, 0, sizeof(struct acpi_handle_list));
-			status = acpi_evaluate_reference(tz->device->handle,
-						name, NULL, &devices);
-			if (ACPI_FAILURE(status)) {
-				pr_warn(PREFIX "Invalid active%d threshold\n",
-					i);
-				tz->trips.active[i].flags.valid = 0;
-			}
-			else
-				tz->trips.active[i].flags.valid = 1;
-
-			if (memcmp(&tz->trips.active[i].devices, &devices,
-					sizeof(struct acpi_handle_list))) {
-				memcpy(&tz->trips.active[i].devices, &devices,
-					sizeof(struct acpi_handle_list));
-				ACPI_THERMAL_TRIPS_EXCEPTION(flag, "device");
-			}
-		}
-		if ((flag & ACPI_TRIPS_ACTIVE) || (flag & ACPI_TRIPS_DEVICES))
-			if (valid != tz->trips.active[i].flags.valid)
-				ACPI_THERMAL_TRIPS_EXCEPTION(flag, "state");
-
-		if (!tz->trips.active[i].flags.valid)
-			break;
-	}
+	if (trip->type == THERMAL_TRIP_PASSIVE) {
+		if (psv > 0)
+			return;
 
-	if (flag & ACPI_TRIPS_DEVICES) {
-		memset(&devices, 0, sizeof(devices));
-		status = acpi_evaluate_reference(tz->device->handle, "_TZD",
-						NULL, &devices);
-		if (ACPI_SUCCESS(status)
-		    && memcmp(&tz->devices, &devices, sizeof(devices))) {
-			tz->devices = devices;
-			ACPI_THERMAL_TRIPS_EXCEPTION(flag, "device");
-		}
+		acpi_trip->temp_dk = get_passive_temp(tz);
+	} else {
+		int index = active_trip_index(tz, acpi_trip);
+
+		acpi_trip->temp_dk = get_active_temp(tz, index);
 	}
 
-	return 0;
+	if (!acpi_thermal_trip_valid(acpi_trip))
+		ACPI_THERMAL_TRIPS_EXCEPTION(tz, "state");
 }
 
-static int acpi_thermal_get_trip_points(struct acpi_thermal *tz)
+static bool update_trip_devices(struct acpi_thermal *tz,
+				struct acpi_thermal_trip *acpi_trip,
+				int index, bool compare)
 {
-	int i, valid, ret = acpi_thermal_trips_update(tz, ACPI_TRIPS_INIT);
-
-	if (ret)
-		return ret;
+	struct acpi_handle_list devices = { 0 };
+	char method[] = "_PSL";
 
-	valid = tz->trips.critical.flags.valid |
-		tz->trips.hot.flags.valid |
-		tz->trips.passive.flags.valid;
+	if (index != ACPI_THERMAL_TRIP_PASSIVE) {
+		method[1] = 'A';
+		method[2] = 'L';
+		method[3] = '0' + index;
+	}
 
-	for (i = 0; i < ACPI_THERMAL_MAX_ACTIVE; i++)
-		valid |= tz->trips.active[i].flags.valid;
+	if (!acpi_evaluate_reference(tz->device->handle, method, NULL, &devices)) {
+		acpi_handle_info(tz->device->handle, "%s evaluation failure\n", method);
+		return false;
+	}
 
-	if (!valid) {
-		pr_warn(FW_BUG "No valid trip found\n");
-		return -ENODEV;
+	if (acpi_handle_list_equal(&acpi_trip->devices, &devices)) {
+		acpi_handle_list_free(&devices);
+		return true;
 	}
-	return 0;
+
+	if (compare)
+		ACPI_THERMAL_TRIPS_EXCEPTION(tz, "device");
+
+	acpi_handle_list_replace(&acpi_trip->devices, &devices);
+	return true;
 }
 
-static void acpi_thermal_check(void *data)
+static void acpi_thermal_update_trip_devices(struct acpi_thermal *tz,
+					     const struct thermal_trip *trip)
 {
-	struct acpi_thermal *tz = data;
+	struct acpi_thermal_trip *acpi_trip = trip->priv;
+	int index = trip->type == THERMAL_TRIP_PASSIVE ?
+			ACPI_THERMAL_TRIP_PASSIVE : active_trip_index(tz, acpi_trip);
 
-	if (!tz->tz_enabled)
+	if (update_trip_devices(tz, acpi_trip, index, true))
 		return;
 
-	thermal_zone_device_update(tz->thermal_zone,
-				   THERMAL_EVENT_UNSPECIFIED);
+	acpi_trip->temp_dk = THERMAL_TEMP_INVALID;
+	ACPI_THERMAL_TRIPS_EXCEPTION(tz, "state");
 }
 
-/* sys I/F for generic thermal sysfs support */
+struct adjust_trip_data {
+	struct acpi_thermal *tz;
+	u32 event;
+};
 
-static int thermal_get_temp(struct thermal_zone_device *thermal, int *temp)
+static int acpi_thermal_adjust_trip(struct thermal_trip *trip, void *data)
 {
-	struct acpi_thermal *tz = thermal->devdata;
-	int result;
+	struct acpi_thermal_trip *acpi_trip = trip->priv;
+	struct adjust_trip_data *atd = data;
+	struct acpi_thermal *tz = atd->tz;
+	int temp;
 
-	if (!tz)
-		return -EINVAL;
-
-	result = acpi_thermal_get_temperature(tz);
-	if (result)
-		return result;
-
-	*temp = deci_kelvin_to_millicelsius_with_offset(tz->temperature,
-							tz->kelvin_offset);
-	return 0;
-}
+	if (!acpi_trip || !acpi_thermal_trip_valid(acpi_trip))
+		return 0;
 
-static int thermal_get_mode(struct thermal_zone_device *thermal,
-				enum thermal_device_mode *mode)
-{
-	struct acpi_thermal *tz = thermal->devdata;
+	if (atd->event == ACPI_THERMAL_NOTIFY_THRESHOLDS)
+		acpi_thermal_update_trip(tz, trip);
+	else
+		acpi_thermal_update_trip_devices(tz, trip);
 
-	if (!tz)
-		return -EINVAL;
+	if (acpi_thermal_trip_valid(acpi_trip))
+		temp = acpi_thermal_temp(tz, acpi_trip->temp_dk);
+	else
+		temp = THERMAL_TEMP_INVALID;
 
-	*mode = tz->tz_enabled ? THERMAL_DEVICE_ENABLED :
-		THERMAL_DEVICE_DISABLED;
+	thermal_zone_set_trip_temp(tz->thermal_zone, trip, temp);
 
 	return 0;
 }
 
-static int thermal_set_mode(struct thermal_zone_device *thermal,
-				enum thermal_device_mode mode)
+static void acpi_queue_thermal_check(struct acpi_thermal *tz)
 {
-	struct acpi_thermal *tz = thermal->devdata;
-	int enable;
+	if (!work_pending(&tz->thermal_check_work))
+		queue_work(acpi_thermal_pm_queue, &tz->thermal_check_work);
+}
 
-	if (!tz)
-		return -EINVAL;
+static void acpi_thermal_trips_update(struct acpi_thermal *tz, u32 event)
+{
+	struct adjust_trip_data atd = { .tz = tz, .event = event };
+	struct acpi_device *adev = tz->device;
 
 	/*
-	 * enable/disable thermal management from ACPI thermal driver
+	 * Use thermal_zone_for_each_trip() to carry out the trip points
+	 * update, so as to protect thermal_get_trend() from getting stale
+	 * trip point temperatures and to prevent thermal_zone_device_update()
+	 * invoked from acpi_thermal_check_fn() from producing inconsistent
+	 * results.
 	 */
-	if (mode == THERMAL_DEVICE_ENABLED)
-		enable = 1;
-	else if (mode == THERMAL_DEVICE_DISABLED) {
-		enable = 0;
-		pr_warn("thermal zone will be disabled\n");
-	} else
-		return -EINVAL;
-
-	if (enable != tz->tz_enabled) {
-		tz->tz_enabled = enable;
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-			"%s kernel ACPI thermal control\n",
-			tz->tz_enabled ? "Enable" : "Disable"));
-		acpi_thermal_check(tz);
-	}
-	return 0;
+	thermal_zone_for_each_trip(tz->thermal_zone,
+				   acpi_thermal_adjust_trip, &atd);
+	acpi_queue_thermal_check(tz);
+	acpi_bus_generate_netlink_event(adev->pnp.device_class,
+					dev_name(&adev->dev), event, 0);
 }
 
-static int thermal_get_trip_type(struct thermal_zone_device *thermal,
-				 int trip, enum thermal_trip_type *type)
+static int acpi_thermal_get_critical_trip(struct acpi_thermal *tz)
 {
-	struct acpi_thermal *tz = thermal->devdata;
-	int i;
-
-	if (!tz || trip < 0)
-		return -EINVAL;
+	int temp;
 
-	if (tz->trips.critical.flags.valid) {
-		if (!trip) {
-			*type = THERMAL_TRIP_CRITICAL;
-			return 0;
-		}
-		trip--;
+	if (crt > 0) {
+		temp = celsius_to_deci_kelvin(crt);
+		goto set;
 	}
-
-	if (tz->trips.hot.flags.valid) {
-		if (!trip) {
-			*type = THERMAL_TRIP_HOT;
-			return 0;
-		}
-		trip--;
+	if (crt == -1) {
+		acpi_handle_debug(tz->device->handle, "Critical threshold disabled\n");
+		return THERMAL_TEMP_INVALID;
 	}
 
-	if (tz->trips.passive.flags.valid) {
-		if (!trip) {
-			*type = THERMAL_TRIP_PASSIVE;
-			return 0;
-		}
-		trip--;
+	if (acpi_critical_trip_temp(tz->device, &temp))
+		return THERMAL_TEMP_INVALID;
+
+	if (temp <= 2732) {
+		/*
+		 * Below zero (Celsius) values clearly aren't right for sure,
+		 * so discard them as invalid.
+		 */
+		pr_info(FW_BUG "Invalid critical threshold (%d)\n", temp);
+		return THERMAL_TEMP_INVALID;
 	}
 
-	for (i = 0; i < ACPI_THERMAL_MAX_ACTIVE &&
-		tz->trips.active[i].flags.valid; i++) {
-		if (!trip) {
-			*type = THERMAL_TRIP_ACTIVE;
-			return 0;
-		}
-		trip--;
+set:
+	acpi_handle_debug(tz->device->handle, "Critical threshold [%d]\n", temp);
+	return temp;
+}
+
+static int acpi_thermal_get_hot_trip(struct acpi_thermal *tz)
+{
+	int temp;
+
+	if (acpi_hot_trip_temp(tz->device, &temp) || temp == THERMAL_TEMP_INVALID) {
+		acpi_handle_debug(tz->device->handle, "No hot threshold\n");
+		return THERMAL_TEMP_INVALID;
 	}
 
-	return -EINVAL;
+	acpi_handle_debug(tz->device->handle, "Hot threshold [%d]\n", temp);
+	return temp;
 }
 
-static int thermal_get_trip_temp(struct thermal_zone_device *thermal,
-				 int trip, int *temp)
+static bool passive_trip_params_init(struct acpi_thermal *tz)
 {
-	struct acpi_thermal *tz = thermal->devdata;
-	int i;
+	unsigned long long tmp;
+	acpi_status status;
 
-	if (!tz || trip < 0)
-		return -EINVAL;
+	status = acpi_evaluate_integer(tz->device->handle, "_TC1", NULL, &tmp);
+	if (ACPI_FAILURE(status))
+		return false;
 
-	if (tz->trips.critical.flags.valid) {
-		if (!trip) {
-			*temp = deci_kelvin_to_millicelsius_with_offset(
-				tz->trips.critical.temperature,
-				tz->kelvin_offset);
-			return 0;
-		}
-		trip--;
-	}
+	tz->trips.passive.tc1 = tmp;
 
-	if (tz->trips.hot.flags.valid) {
-		if (!trip) {
-			*temp = deci_kelvin_to_millicelsius_with_offset(
-				tz->trips.hot.temperature,
-				tz->kelvin_offset);
-			return 0;
-		}
-		trip--;
-	}
+	status = acpi_evaluate_integer(tz->device->handle, "_TC2", NULL, &tmp);
+	if (ACPI_FAILURE(status))
+		return false;
 
-	if (tz->trips.passive.flags.valid) {
-		if (!trip) {
-			*temp = deci_kelvin_to_millicelsius_with_offset(
-				tz->trips.passive.temperature,
-				tz->kelvin_offset);
-			return 0;
-		}
-		trip--;
-	}
+	tz->trips.passive.tc2 = tmp;
 
-	for (i = 0; i < ACPI_THERMAL_MAX_ACTIVE &&
-		tz->trips.active[i].flags.valid; i++) {
-		if (!trip) {
-			*temp = deci_kelvin_to_millicelsius_with_offset(
-				tz->trips.active[i].temperature,
-				tz->kelvin_offset);
-			return 0;
-		}
-		trip--;
+	status = acpi_evaluate_integer(tz->device->handle, "_TFP", NULL, &tmp);
+	if (ACPI_SUCCESS(status)) {
+		tz->trips.passive.delay = tmp;
+		return true;
 	}
 
-	return -EINVAL;
+	status = acpi_evaluate_integer(tz->device->handle, "_TSP", NULL, &tmp);
+	if (ACPI_FAILURE(status))
+		return false;
+
+	tz->trips.passive.delay = tmp * 100;
+
+	return true;
 }
 
-static int thermal_get_crit_temp(struct thermal_zone_device *thermal,
-				int *temperature)
+static bool acpi_thermal_init_trip(struct acpi_thermal *tz, int index)
 {
-	struct acpi_thermal *tz = thermal->devdata;
+	struct acpi_thermal_trip *acpi_trip;
+	long temp;
 
-	if (tz->trips.critical.flags.valid) {
-		*temperature = deci_kelvin_to_millicelsius_with_offset(
-				tz->trips.critical.temperature,
-				tz->kelvin_offset);
-		return 0;
-	} else
-		return -EINVAL;
+	if (index == ACPI_THERMAL_TRIP_PASSIVE) {
+		acpi_trip = &tz->trips.passive.trip;
+
+		if (psv == -1)
+			goto fail;
+
+		if (!passive_trip_params_init(tz))
+			goto fail;
+
+		temp = psv > 0 ? celsius_to_deci_kelvin(psv) :
+				 get_passive_temp(tz);
+	} else {
+		acpi_trip = &tz->trips.active[index].trip;
+
+		if (act == -1)
+			goto fail;
+
+		temp = get_active_temp(tz, index);
+	}
+
+	if (temp == THERMAL_TEMP_INVALID)
+		goto fail;
+
+	if (!update_trip_devices(tz, acpi_trip, index, false))
+		goto fail;
+
+	acpi_trip->temp_dk = temp;
+	return true;
+
+fail:
+	acpi_trip->temp_dk = THERMAL_TEMP_INVALID;
+	return false;
 }
 
-static int thermal_get_trend(struct thermal_zone_device *thermal,
-				int trip, enum thermal_trend *trend)
+static void acpi_thermal_get_trip_points(struct acpi_thermal *tz)
 {
-	struct acpi_thermal *tz = thermal->devdata;
-	enum thermal_trip_type type;
 	int i;
 
-	if (thermal_get_trip_type(thermal, trip, &type))
-		return -EINVAL;
-
-	if (type == THERMAL_TRIP_ACTIVE) {
-		int trip_temp;
-		int temp = deci_kelvin_to_millicelsius_with_offset(
-					tz->temperature, tz->kelvin_offset);
-		if (thermal_get_trip_temp(thermal, trip, &trip_temp))
-			return -EINVAL;
+	acpi_thermal_init_trip(tz, ACPI_THERMAL_TRIP_PASSIVE);
 
-		if (temp > trip_temp) {
-			*trend = THERMAL_TREND_RAISING;
-			return 0;
-		} else {
-			/* Fall back on default trend */
-			return -EINVAL;
-		}
+	for (i = 0; i < ACPI_THERMAL_MAX_ACTIVE; i++) {
+		if (!acpi_thermal_init_trip(tz, i))
+			break;
 	}
 
-	/*
-	 * tz->temperature has already been updated by generic thermal layer,
-	 * before this callback being invoked
-	 */
-	i = (tz->trips.passive.tc1 * (tz->temperature - tz->last_temperature))
-		+ (tz->trips.passive.tc2
-		* (tz->temperature - tz->trips.passive.temperature));
-
-	if (i > 0)
-		*trend = THERMAL_TREND_RAISING;
-	else if (i < 0)
-		*trend = THERMAL_TREND_DROPPING;
-	else
-		*trend = THERMAL_TREND_STABLE;
-	return 0;
+	while (++i < ACPI_THERMAL_MAX_ACTIVE)
+		tz->trips.active[i].trip.temp_dk = THERMAL_TEMP_INVALID;
 }
 
+/* sys I/F for generic thermal sysfs support */
 
-static int thermal_notify(struct thermal_zone_device *thermal, int trip,
-			   enum thermal_trip_type trip_type)
+static int thermal_get_temp(struct thermal_zone_device *thermal, int *temp)
 {
-	u8 type = 0;
-	struct acpi_thermal *tz = thermal->devdata;
-
-	if (trip_type == THERMAL_TRIP_CRITICAL)
-		type = ACPI_THERMAL_NOTIFY_CRITICAL;
-	else if (trip_type == THERMAL_TRIP_HOT)
-		type = ACPI_THERMAL_NOTIFY_HOT;
-	else
-		return 0;
+	struct acpi_thermal *tz = thermal_zone_device_priv(thermal);
+	int result;
 
-	acpi_bus_generate_netlink_event(tz->device->pnp.device_class,
-					dev_name(&tz->device->dev), type, 1);
+	if (!tz)
+		return -EINVAL;
 
-	if (trip_type == THERMAL_TRIP_CRITICAL && nocrt)
-		return 1;
+	result = acpi_thermal_get_temperature(tz);
+	if (result)
+		return result;
 
+	*temp = deci_kelvin_to_millicelsius_with_offset(tz->temp_dk,
+							tz->kelvin_offset);
 	return 0;
 }
 
-static int acpi_thermal_cooling_device_cb(struct thermal_zone_device *thermal,
-					struct thermal_cooling_device *cdev,
-					bool bind)
+static int thermal_get_trend(struct thermal_zone_device *thermal,
+			     const struct thermal_trip *trip,
+			     enum thermal_trend *trend)
 {
-	struct acpi_device *device = cdev->devdata;
-	struct acpi_thermal *tz = thermal->devdata;
-	struct acpi_device *dev;
-	acpi_status status;
-	acpi_handle handle;
-	int i;
-	int j;
-	int trip = -1;
-	int result = 0;
+	struct acpi_thermal *tz = thermal_zone_device_priv(thermal);
+	struct acpi_thermal_trip *acpi_trip;
+	int t;
 
-	if (tz->trips.critical.flags.valid)
-		trip++;
+	if (!tz || !trip)
+		return -EINVAL;
 
-	if (tz->trips.hot.flags.valid)
-		trip++;
+	acpi_trip = trip->priv;
+	if (!acpi_trip || !acpi_thermal_trip_valid(acpi_trip))
+		return -EINVAL;
 
-	if (tz->trips.passive.flags.valid) {
-		trip++;
-		for (i = 0; i < tz->trips.passive.devices.count;
-		    i++) {
-			handle = tz->trips.passive.devices.handles[i];
-			status = acpi_bus_get_device(handle, &dev);
-			if (ACPI_FAILURE(status) || dev != device)
-				continue;
-			if (bind)
-				result =
-					thermal_zone_bind_cooling_device
-					(thermal, trip, cdev,
-					 THERMAL_NO_LIMIT, THERMAL_NO_LIMIT,
-					 THERMAL_WEIGHT_DEFAULT);
-			else
-				result =
-					thermal_zone_unbind_cooling_device
-					(thermal, trip, cdev);
-			if (result)
-				goto failed;
-		}
-	}
+	switch (trip->type) {
+	case THERMAL_TRIP_PASSIVE:
+		t = tz->trips.passive.tc1 * (tz->temp_dk -
+						tz->last_temp_dk) +
+			tz->trips.passive.tc2 * (tz->temp_dk -
+						acpi_trip->temp_dk);
+		if (t > 0)
+			*trend = THERMAL_TREND_RAISING;
+		else if (t < 0)
+			*trend = THERMAL_TREND_DROPPING;
+		else
+			*trend = THERMAL_TREND_STABLE;
 
-	for (i = 0; i < ACPI_THERMAL_MAX_ACTIVE; i++) {
-		if (!tz->trips.active[i].flags.valid)
+		return 0;
+
+	case THERMAL_TRIP_ACTIVE:
+		t = acpi_thermal_temp(tz, tz->temp_dk);
+		if (t <= trip->temperature)
 			break;
-		trip++;
-		for (j = 0;
-		    j < tz->trips.active[i].devices.count;
-		    j++) {
-			handle = tz->trips.active[i].devices.handles[j];
-			status = acpi_bus_get_device(handle, &dev);
-			if (ACPI_FAILURE(status) || dev != device)
-				continue;
-			if (bind)
-				result = thermal_zone_bind_cooling_device
-					(thermal, trip, cdev,
-					 THERMAL_NO_LIMIT, THERMAL_NO_LIMIT,
-					 THERMAL_WEIGHT_DEFAULT);
-			else
-				result = thermal_zone_unbind_cooling_device
-					(thermal, trip, cdev);
-			if (result)
-				goto failed;
-		}
-	}
 
-	for (i = 0; i < tz->devices.count; i++) {
-		handle = tz->devices.handles[i];
-		status = acpi_bus_get_device(handle, &dev);
-		if (ACPI_SUCCESS(status) && (dev == device)) {
-			if (bind)
-				result = thermal_zone_bind_cooling_device
-						(thermal, THERMAL_TRIPS_NONE,
-						 cdev, THERMAL_NO_LIMIT,
-						 THERMAL_NO_LIMIT,
-						 THERMAL_WEIGHT_DEFAULT);
-			else
-				result = thermal_zone_unbind_cooling_device
-						(thermal, THERMAL_TRIPS_NONE,
-						 cdev);
-			if (result)
-				goto failed;
-		}
+		*trend = THERMAL_TREND_RAISING;
+
+		return 0;
+
+	default:
+		break;
 	}
 
-failed:
-	return result;
+	return -EINVAL;
 }
 
-static int
-acpi_thermal_bind_cooling_device(struct thermal_zone_device *thermal,
-					struct thermal_cooling_device *cdev)
+static void acpi_thermal_zone_device_hot(struct thermal_zone_device *thermal)
 {
-	return acpi_thermal_cooling_device_cb(thermal, cdev, true);
+	struct acpi_thermal *tz = thermal_zone_device_priv(thermal);
+
+	acpi_bus_generate_netlink_event(tz->device->pnp.device_class,
+					dev_name(&tz->device->dev),
+					ACPI_THERMAL_NOTIFY_HOT, 1);
+}
+
+static void acpi_thermal_zone_device_critical(struct thermal_zone_device *thermal)
+{
+	struct acpi_thermal *tz = thermal_zone_device_priv(thermal);
+
+	acpi_bus_generate_netlink_event(tz->device->pnp.device_class,
+					dev_name(&tz->device->dev),
+					ACPI_THERMAL_NOTIFY_CRITICAL, 1);
+
+	thermal_zone_device_critical(thermal);
 }
 
-static int
-acpi_thermal_unbind_cooling_device(struct thermal_zone_device *thermal,
-					struct thermal_cooling_device *cdev)
+static bool acpi_thermal_should_bind_cdev(struct thermal_zone_device *thermal,
+					  const struct thermal_trip *trip,
+					  struct thermal_cooling_device *cdev,
+					  struct cooling_spec *c)
 {
-	return acpi_thermal_cooling_device_cb(thermal, cdev, false);
+	struct acpi_thermal_trip *acpi_trip = trip->priv;
+	struct acpi_device *cdev_adev = cdev->devdata;
+	int i;
+
+	/* Skip critical and hot trips. */
+	if (!acpi_trip)
+		return false;
+
+	for (i = 0; i < acpi_trip->devices.count; i++) {
+		acpi_handle handle = acpi_trip->devices.handles[i];
+
+		if (acpi_fetch_acpi_dev(handle) == cdev_adev)
+			return true;
+	}
+
+	return false;
 }
 
-static struct thermal_zone_device_ops acpi_thermal_zone_ops = {
-	.bind = acpi_thermal_bind_cooling_device,
-	.unbind	= acpi_thermal_unbind_cooling_device,
+static const struct thermal_zone_device_ops acpi_thermal_zone_ops = {
+	.should_bind = acpi_thermal_should_bind_cdev,
 	.get_temp = thermal_get_temp,
-	.get_mode = thermal_get_mode,
-	.set_mode = thermal_set_mode,
-	.get_trip_type = thermal_get_trip_type,
-	.get_trip_temp = thermal_get_trip_temp,
-	.get_crit_temp = thermal_get_crit_temp,
 	.get_trend = thermal_get_trend,
-	.notify = thermal_notify,
+	.hot = acpi_thermal_zone_device_hot,
+	.critical = acpi_thermal_zone_device_critical,
 };
 
-static int acpi_thermal_register_thermal_zone(struct acpi_thermal *tz)
+static int acpi_thermal_zone_sysfs_add(struct acpi_thermal *tz)
 {
-	int trips = 0;
-	int result;
-	acpi_status status;
-	int i;
+	struct device *tzdev = thermal_zone_device(tz->thermal_zone);
+	int ret;
 
-	if (tz->trips.critical.flags.valid)
-		trips++;
+	ret = sysfs_create_link(&tz->device->dev.kobj,
+				&tzdev->kobj, "thermal_zone");
+	if (ret)
+		return ret;
 
-	if (tz->trips.hot.flags.valid)
-		trips++;
+	ret = sysfs_create_link(&tzdev->kobj,
+				   &tz->device->dev.kobj, "device");
+	if (ret)
+		sysfs_remove_link(&tz->device->dev.kobj, "thermal_zone");
 
-	if (tz->trips.passive.flags.valid)
-		trips++;
+	return ret;
+}
 
-	for (i = 0; i < ACPI_THERMAL_MAX_ACTIVE &&
-			tz->trips.active[i].flags.valid; i++, trips++);
+static void acpi_thermal_zone_sysfs_remove(struct acpi_thermal *tz)
+{
+	struct device *tzdev = thermal_zone_device(tz->thermal_zone);
 
-	if (tz->trips.passive.flags.valid)
-		tz->thermal_zone =
-			thermal_zone_device_register("acpitz", trips, 0, tz,
-						&acpi_thermal_zone_ops, NULL,
-						     tz->trips.passive.tsp*100,
-						     tz->polling_frequency*100);
+	sysfs_remove_link(&tz->device->dev.kobj, "thermal_zone");
+	sysfs_remove_link(&tzdev->kobj, "device");
+}
+
+static int acpi_thermal_register_thermal_zone(struct acpi_thermal *tz,
+					      const struct thermal_trip *trip_table,
+					      unsigned int trip_count,
+					      int passive_delay)
+{
+	int result;
+
+	if (trip_count)
+		tz->thermal_zone = thermal_zone_device_register_with_trips(
+					"acpitz", trip_table, trip_count, tz,
+					&acpi_thermal_zone_ops, NULL, passive_delay,
+					tz->polling_frequency * 100);
 	else
-		tz->thermal_zone =
-			thermal_zone_device_register("acpitz", trips, 0, tz,
-						&acpi_thermal_zone_ops, NULL,
-						0, tz->polling_frequency*100);
+		tz->thermal_zone = thermal_tripless_zone_device_register(
+					"acpitz", tz, &acpi_thermal_zone_ops, NULL);
+
 	if (IS_ERR(tz->thermal_zone))
-		return -ENODEV;
+		return PTR_ERR(tz->thermal_zone);
 
-	result = sysfs_create_link(&tz->device->dev.kobj,
-				   &tz->thermal_zone->device.kobj, "thermal_zone");
+	result = acpi_thermal_zone_sysfs_add(tz);
 	if (result)
-		return result;
+		goto unregister_tzd;
 
-	result = sysfs_create_link(&tz->thermal_zone->device.kobj,
-				   &tz->device->dev.kobj, "device");
+	result = thermal_zone_device_enable(tz->thermal_zone);
 	if (result)
-		return result;
-
-	status =  acpi_bus_attach_private_data(tz->device->handle,
-					       tz->thermal_zone);
-	if (ACPI_FAILURE(status))
-		return -ENODEV;
-
-	tz->tz_enabled = 1;
+		goto remove_links;
 
 	dev_info(&tz->device->dev, "registered as thermal_zone%d\n",
-		 tz->thermal_zone->id);
+		 thermal_zone_device_id(tz->thermal_zone));
+
 	return 0;
+
+remove_links:
+	acpi_thermal_zone_sysfs_remove(tz);
+unregister_tzd:
+	thermal_zone_device_unregister(tz->thermal_zone);
+
+	return result;
 }
 
 static void acpi_thermal_unregister_thermal_zone(struct acpi_thermal *tz)
 {
-	sysfs_remove_link(&tz->device->dev.kobj, "thermal_zone");
-	sysfs_remove_link(&tz->thermal_zone->device.kobj, "device");
+	thermal_zone_device_disable(tz->thermal_zone);
+	acpi_thermal_zone_sysfs_remove(tz);
 	thermal_zone_device_unregister(tz->thermal_zone);
 	tz->thermal_zone = NULL;
-	acpi_bus_detach_private_data(tz->device->handle);
 }
 
 
@@ -934,33 +668,25 @@ static void acpi_thermal_unregister_thermal_zone(struct acpi_thermal *tz)
                                  Driver Interface
    -------------------------------------------------------------------------- */
 
-static void acpi_thermal_notify(struct acpi_device *device, u32 event)
+static void acpi_thermal_notify(acpi_handle handle, u32 event, void *data)
 {
+	struct acpi_device *device = data;
 	struct acpi_thermal *tz = acpi_driver_data(device);
 
-
 	if (!tz)
 		return;
 
 	switch (event) {
 	case ACPI_THERMAL_NOTIFY_TEMPERATURE:
-		acpi_thermal_check(tz);
+		acpi_queue_thermal_check(tz);
 		break;
 	case ACPI_THERMAL_NOTIFY_THRESHOLDS:
-		acpi_thermal_trips_update(tz, ACPI_TRIPS_REFRESH_THRESHOLDS);
-		acpi_thermal_check(tz);
-		acpi_bus_generate_netlink_event(device->pnp.device_class,
-						  dev_name(&device->dev), event, 0);
-		break;
 	case ACPI_THERMAL_NOTIFY_DEVICES:
-		acpi_thermal_trips_update(tz, ACPI_TRIPS_REFRESH_DEVICES);
-		acpi_thermal_check(tz);
-		acpi_bus_generate_netlink_event(device->pnp.device_class,
-						  dev_name(&device->dev), event, 0);
+		acpi_thermal_trips_update(tz, event);
 		break;
 	default:
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-				  "Unsupported event [0x%x]\n", event));
+		acpi_handle_debug(device->handle, "Unsupported event [0x%x]\n",
+				  event);
 		break;
 	}
 }
@@ -997,40 +723,6 @@ static void acpi_thermal_aml_dependency_fix(struct acpi_thermal *tz)
 	acpi_evaluate_integer(handle, "_TMP", NULL, &value);
 }
 
-static int acpi_thermal_get_info(struct acpi_thermal *tz)
-{
-	int result = 0;
-
-
-	if (!tz)
-		return -EINVAL;
-
-	acpi_thermal_aml_dependency_fix(tz);
-
-	/* Get trip points [_CRT, _PSV, etc.] (required) */
-	result = acpi_thermal_get_trip_points(tz);
-	if (result)
-		return result;
-
-	/* Get temperature [_TMP] (required) */
-	result = acpi_thermal_get_temperature(tz);
-	if (result)
-		return result;
-
-	/* Set the cooling mode [_SCP] to active cooling (default) */
-	result = acpi_thermal_set_cooling_mode(tz, ACPI_THERMAL_MODE_ACTIVE);
-	if (!result)
-		tz->flags.cooling_mode = 1;
-
-	/* Get default polling frequency [_TZP] (optional) */
-	if (tzp)
-		tz->polling_frequency = tzp;
-	else
-		acpi_thermal_get_polling_frequency(tz);
-
-	return 0;
-}
-
 /*
  * The exact offset between Kelvin and degree Celsius is 273.15. However ACPI
  * handles temperature values with a single decimal place. As a consequence,
@@ -1041,10 +733,9 @@ static int acpi_thermal_get_info(struct acpi_thermal *tz)
  * The heuristic below should work for all ACPI thermal zones which have a
  * critical trip point with a value being a multiple of 0.5 degree Celsius.
  */
-static void acpi_thermal_guess_offset(struct acpi_thermal *tz)
+static void acpi_thermal_guess_offset(struct acpi_thermal *tz, long crit_temp)
 {
-	if (tz->trips.critical.flags.valid &&
-	    (tz->trips.critical.temperature % 5) == 1)
+	if (crit_temp != THERMAL_TEMP_INVALID && crit_temp % 5 == 1)
 		tz->kelvin_offset = 273100;
 	else
 		tz->kelvin_offset = 273200;
@@ -1054,14 +745,48 @@ static void acpi_thermal_check_fn(struct work_struct *work)
 {
 	struct acpi_thermal *tz = container_of(work, struct acpi_thermal,
 					       thermal_check_work);
-	acpi_thermal_check(tz);
+
+	/*
+	 * In general, it is not sufficient to check the pending bit, because
+	 * subsequent instances of this function may be queued after one of them
+	 * has started running (e.g. if _TMP sleeps).  Avoid bailing out if just
+	 * one of them is running, though, because it may have done the actual
+	 * check some time ago, so allow at least one of them to block on the
+	 * mutex while another one is running the update.
+	 */
+	if (!refcount_dec_not_one(&tz->thermal_check_count))
+		return;
+
+	mutex_lock(&tz->thermal_check_lock);
+
+	thermal_zone_device_update(tz->thermal_zone, THERMAL_EVENT_UNSPECIFIED);
+
+	refcount_inc(&tz->thermal_check_count);
+
+	mutex_unlock(&tz->thermal_check_lock);
 }
 
-static int acpi_thermal_add(struct acpi_device *device)
+static void acpi_thermal_free_thermal_zone(struct acpi_thermal *tz)
 {
-	int result = 0;
-	struct acpi_thermal *tz = NULL;
+	int i;
+
+	acpi_handle_list_free(&tz->trips.passive.trip.devices);
+	for (i = 0; i < ACPI_THERMAL_MAX_ACTIVE; i++)
+		acpi_handle_list_free(&tz->trips.active[i].trip.devices);
 
+	kfree(tz);
+}
+
+static int acpi_thermal_add(struct acpi_device *device)
+{
+	struct thermal_trip trip_table[ACPI_THERMAL_MAX_NR_TRIPS] = { 0 };
+	struct acpi_thermal_trip *acpi_trip;
+	struct thermal_trip *trip;
+	struct acpi_thermal *tz;
+	int crit_temp, hot_temp;
+	int passive_delay = 0;
+	int result;
+	int i;
 
 	if (!device)
 		return -EINVAL;
@@ -1071,46 +796,121 @@ static int acpi_thermal_add(struct acpi_device *device)
 		return -ENOMEM;
 
 	tz->device = device;
-	strcpy(tz->name, device->pnp.bus_id);
-	strcpy(acpi_device_name(device), ACPI_THERMAL_DEVICE_NAME);
-	strcpy(acpi_device_class(device), ACPI_THERMAL_CLASS);
+	strscpy(tz->name, device->pnp.bus_id);
+	strscpy(acpi_device_name(device), ACPI_THERMAL_DEVICE_NAME);
+	strscpy(acpi_device_class(device), ACPI_THERMAL_CLASS);
 	device->driver_data = tz;
 
-	result = acpi_thermal_get_info(tz);
+	acpi_thermal_aml_dependency_fix(tz);
+
+	/*
+	 * Set the cooling mode [_SCP] to active cooling. This needs to happen before
+	 * we retrieve the trip point values.
+	 */
+	acpi_execute_simple_method(tz->device->handle, "_SCP", ACPI_THERMAL_MODE_ACTIVE);
+
+	/* Get trip points [_ACi, _PSV, etc.] (required). */
+	acpi_thermal_get_trip_points(tz);
+
+	crit_temp = acpi_thermal_get_critical_trip(tz);
+	hot_temp = acpi_thermal_get_hot_trip(tz);
+
+	/* Get temperature [_TMP] (required). */
+	result = acpi_thermal_get_temperature(tz);
 	if (result)
 		goto free_memory;
 
-	acpi_thermal_guess_offset(tz);
+	/* Determine the default polling frequency [_TZP]. */
+	if (tzp)
+		tz->polling_frequency = tzp;
+	else
+		acpi_thermal_get_polling_frequency(tz);
+
+	acpi_thermal_guess_offset(tz, crit_temp);
+
+	trip = trip_table;
+
+	if (crit_temp != THERMAL_TEMP_INVALID) {
+		trip->type = THERMAL_TRIP_CRITICAL;
+		trip->temperature = acpi_thermal_temp(tz, crit_temp);
+		trip++;
+	}
+
+	if (hot_temp != THERMAL_TEMP_INVALID) {
+		trip->type = THERMAL_TRIP_HOT;
+		trip->temperature = acpi_thermal_temp(tz, hot_temp);
+		trip++;
+	}
+
+	acpi_trip = &tz->trips.passive.trip;
+	if (acpi_thermal_trip_valid(acpi_trip)) {
+		passive_delay = tz->trips.passive.delay;
+
+		trip->type = THERMAL_TRIP_PASSIVE;
+		trip->temperature = acpi_thermal_temp(tz, acpi_trip->temp_dk);
+		trip->priv = acpi_trip;
+		trip++;
+	}
+
+	for (i = 0; i < ACPI_THERMAL_MAX_ACTIVE; i++) {
+		acpi_trip =  &tz->trips.active[i].trip;
+
+		if (!acpi_thermal_trip_valid(acpi_trip))
+			break;
+
+		trip->type = THERMAL_TRIP_ACTIVE;
+		trip->temperature = acpi_thermal_temp(tz, acpi_trip->temp_dk);
+		trip->priv = acpi_trip;
+		trip++;
+	}
 
-	result = acpi_thermal_register_thermal_zone(tz);
+	if (trip == trip_table)
+		pr_warn(FW_BUG "No valid trip points!\n");
+
+	result = acpi_thermal_register_thermal_zone(tz, trip_table,
+						    trip - trip_table,
+						    passive_delay);
 	if (result)
 		goto free_memory;
 
+	refcount_set(&tz->thermal_check_count, 3);
+	mutex_init(&tz->thermal_check_lock);
 	INIT_WORK(&tz->thermal_check_work, acpi_thermal_check_fn);
 
-	pr_info(PREFIX "%s [%s] (%ld C)\n", acpi_device_name(device),
-		acpi_device_bid(device), deci_kelvin_to_celsius(tz->temperature));
-	goto end;
+	pr_info("%s [%s] (%ld C)\n", acpi_device_name(device),
+		acpi_device_bid(device), deci_kelvin_to_celsius(tz->temp_dk));
+
+	result = acpi_dev_install_notify_handler(device, ACPI_DEVICE_NOTIFY,
+						 acpi_thermal_notify, device);
+	if (result)
+		goto flush_wq;
+
+	return 0;
 
+flush_wq:
+	flush_workqueue(acpi_thermal_pm_queue);
+	acpi_thermal_unregister_thermal_zone(tz);
 free_memory:
-	kfree(tz);
-end:
+	acpi_thermal_free_thermal_zone(tz);
+
 	return result;
 }
 
-static int acpi_thermal_remove(struct acpi_device *device)
+static void acpi_thermal_remove(struct acpi_device *device)
 {
-	struct acpi_thermal *tz = NULL;
+	struct acpi_thermal *tz;
 
 	if (!device || !acpi_driver_data(device))
-		return -EINVAL;
+		return;
 
-	flush_workqueue(acpi_thermal_pm_queue);
 	tz = acpi_driver_data(device);
 
+	acpi_dev_remove_notify_handler(device, ACPI_DEVICE_NOTIFY,
+				       acpi_thermal_notify);
+
+	flush_workqueue(acpi_thermal_pm_queue);
 	acpi_thermal_unregister_thermal_zone(tz);
-	kfree(tz);
-	return 0;
+	acpi_thermal_free_thermal_zone(tz);
 }
 
 #ifdef CONFIG_PM_SLEEP
@@ -1124,7 +924,7 @@ static int acpi_thermal_suspend(struct device *dev)
 static int acpi_thermal_resume(struct device *dev)
 {
 	struct acpi_thermal *tz;
-	int i, j, power_state, result;
+	int i, j;
 
 	if (!dev)
 		return -EINVAL;
@@ -1134,59 +934,75 @@ static int acpi_thermal_resume(struct device *dev)
 		return -EINVAL;
 
 	for (i = 0; i < ACPI_THERMAL_MAX_ACTIVE; i++) {
-		if (!(&tz->trips.active[i]))
-			break;
-		if (!tz->trips.active[i].flags.valid)
+		struct acpi_thermal_trip *acpi_trip = &tz->trips.active[i].trip;
+
+		if (!acpi_thermal_trip_valid(acpi_trip))
 			break;
-		tz->trips.active[i].flags.enabled = 1;
-		for (j = 0; j < tz->trips.active[i].devices.count; j++) {
-			result = acpi_bus_update_power(
-					tz->trips.active[i].devices.handles[j],
-					&power_state);
-			if (result || (power_state != ACPI_STATE_D0)) {
-				tz->trips.active[i].flags.enabled = 0;
-				break;
-			}
-		}
-		tz->state.active |= tz->trips.active[i].flags.enabled;
+
+		for (j = 0; j < acpi_trip->devices.count; j++)
+			acpi_bus_update_power(acpi_trip->devices.handles[j], NULL);
 	}
 
-	queue_work(acpi_thermal_pm_queue, &tz->thermal_check_work);
+	acpi_queue_thermal_check(tz);
 
 	return AE_OK;
 }
+#else
+#define acpi_thermal_suspend	NULL
+#define acpi_thermal_resume	NULL
 #endif
+static SIMPLE_DEV_PM_OPS(acpi_thermal_pm, acpi_thermal_suspend, acpi_thermal_resume);
+
+static const struct acpi_device_id  thermal_device_ids[] = {
+	{ACPI_THERMAL_HID, 0},
+	{"", 0},
+};
+MODULE_DEVICE_TABLE(acpi, thermal_device_ids);
 
-static int thermal_act(const struct dmi_system_id *d) {
+static struct acpi_driver acpi_thermal_driver = {
+	.name = "thermal",
+	.class = ACPI_THERMAL_CLASS,
+	.ids = thermal_device_ids,
+	.ops = {
+		.add = acpi_thermal_add,
+		.remove = acpi_thermal_remove,
+		},
+	.drv.pm = &acpi_thermal_pm,
+};
 
+static int thermal_act(const struct dmi_system_id *d)
+{
 	if (act == 0) {
-		pr_notice(PREFIX "%s detected: "
-			  "disabling all active thermal trip points\n", d->ident);
+		pr_notice("%s detected: disabling all active thermal trip points\n",
+			  d->ident);
 		act = -1;
 	}
 	return 0;
 }
-static int thermal_nocrt(const struct dmi_system_id *d) {
 
-	pr_notice(PREFIX "%s detected: "
-		  "disabling all critical thermal trip point actions.\n", d->ident);
-	nocrt = 1;
+static int thermal_nocrt(const struct dmi_system_id *d)
+{
+	pr_notice("%s detected: disabling all critical thermal trip point actions.\n",
+		  d->ident);
+	crt = -1;
 	return 0;
 }
-static int thermal_tzp(const struct dmi_system_id *d) {
 
+static int thermal_tzp(const struct dmi_system_id *d)
+{
 	if (tzp == 0) {
-		pr_notice(PREFIX "%s detected: "
-			  "enabling thermal zone polling\n", d->ident);
+		pr_notice("%s detected: enabling thermal zone polling\n",
+			  d->ident);
 		tzp = 300;	/* 300 dS = 30 Seconds */
 	}
 	return 0;
 }
-static int thermal_psv(const struct dmi_system_id *d) {
 
+static int thermal_psv(const struct dmi_system_id *d)
+{
 	if (psv == 0) {
-		pr_notice(PREFIX "%s detected: "
-			  "disabling all passive thermal trip points\n", d->ident);
+		pr_notice("%s detected: disabling all passive thermal trip points\n",
+			  d->ident);
 		psv = -1;
 	}
 	return 0;
@@ -1234,17 +1050,18 @@ static const struct dmi_system_id thermal_dmi_table[] __initconst = {
 
 static int __init acpi_thermal_init(void)
 {
-	int result = 0;
+	int result;
 
 	dmi_check_system(thermal_dmi_table);
 
 	if (off) {
-		pr_notice(PREFIX "thermal control disabled\n");
+		pr_notice("thermal control disabled\n");
 		return -ENODEV;
 	}
 
 	acpi_thermal_pm_queue = alloc_workqueue("acpi_thermal_pm",
-						WQ_HIGHPRI | WQ_MEM_RECLAIM, 0);
+						WQ_HIGHPRI | WQ_MEM_RECLAIM | WQ_PERCPU,
+						0);
 	if (!acpi_thermal_pm_queue)
 		return -ENODEV;
 
@@ -1261,9 +1078,12 @@ static void __exit acpi_thermal_exit(void)
 {
 	acpi_bus_unregister_driver(&acpi_thermal_driver);
 	destroy_workqueue(acpi_thermal_pm_queue);
-
-	return;
 }
 
 module_init(acpi_thermal_init);
 module_exit(acpi_thermal_exit);
+
+MODULE_IMPORT_NS("ACPI_THERMAL");
+MODULE_AUTHOR("Paul Diefenbaugh");
+MODULE_DESCRIPTION("ACPI Thermal Zone Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/acpi/thermal_lib.c b/drivers/acpi/thermal_lib.c
new file mode 100644
index 000000000000..f81591927e86
--- /dev/null
+++ b/drivers/acpi/thermal_lib.c
@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2023 Linaro Limited
+ * Copyright 2023 Intel Corporation
+ *
+ * Library routines for retrieving trip point temperature values from the
+ * platform firmware via ACPI.
+ */
+#include <linux/acpi.h>
+#include <linux/units.h>
+#include <linux/thermal.h>
+#include "internal.h"
+
+/*
+ * Minimum temperature for full military grade is 218°K (-55°C) and
+ * max temperature is 448°K (175°C). We can consider those values as
+ * the boundaries for the [trips] temperature returned by the
+ * firmware. Any values out of these boundaries may be considered
+ * bogus and we can assume the firmware has no data to provide.
+ */
+#define TEMP_MIN_DECIK	2180ULL
+#define TEMP_MAX_DECIK	4480ULL
+
+static int acpi_trip_temp(struct acpi_device *adev, char *obj_name,
+			  int *ret_temp)
+{
+	unsigned long long temp;
+	acpi_status status;
+
+	status = acpi_evaluate_integer(adev->handle, obj_name, NULL, &temp);
+	if (ACPI_FAILURE(status)) {
+		acpi_handle_debug(adev->handle, "%s evaluation failed\n", obj_name);
+		return -ENODATA;
+	}
+
+	if (temp >= TEMP_MIN_DECIK && temp <= TEMP_MAX_DECIK) {
+		*ret_temp = temp;
+	} else {
+		acpi_handle_debug(adev->handle, "%s result %llu out of range\n",
+				  obj_name, temp);
+		*ret_temp = THERMAL_TEMP_INVALID;
+	}
+
+	return 0;
+}
+
+int acpi_active_trip_temp(struct acpi_device *adev, int id, int *ret_temp)
+{
+	char obj_name[] = {'_', 'A', 'C', '0' + id, '\0'};
+
+	if (id < 0 || id > 9)
+		return -EINVAL;
+
+	return acpi_trip_temp(adev, obj_name, ret_temp);
+}
+EXPORT_SYMBOL_NS_GPL(acpi_active_trip_temp, "ACPI_THERMAL");
+
+int acpi_passive_trip_temp(struct acpi_device *adev, int *ret_temp)
+{
+	return acpi_trip_temp(adev, "_PSV", ret_temp);
+}
+EXPORT_SYMBOL_NS_GPL(acpi_passive_trip_temp, "ACPI_THERMAL");
+
+int acpi_hot_trip_temp(struct acpi_device *adev, int *ret_temp)
+{
+	return acpi_trip_temp(adev, "_HOT", ret_temp);
+}
+EXPORT_SYMBOL_NS_GPL(acpi_hot_trip_temp, "ACPI_THERMAL");
+
+int acpi_critical_trip_temp(struct acpi_device *adev, int *ret_temp)
+{
+	return acpi_trip_temp(adev, "_CRT", ret_temp);
+}
+EXPORT_SYMBOL_NS_GPL(acpi_critical_trip_temp, "ACPI_THERMAL");
+
+static int thermal_temp(int error, int temp_decik, int *ret_temp)
+{
+	if (error)
+		return error;
+
+	if (temp_decik == THERMAL_TEMP_INVALID)
+		*ret_temp = THERMAL_TEMP_INVALID;
+	else
+		*ret_temp = deci_kelvin_to_millicelsius(temp_decik);
+
+	return 0;
+}
+
+/**
+ * thermal_acpi_active_trip_temp - Retrieve active trip point temperature
+ * @adev: Target thermal zone ACPI device object.
+ * @id: Active cooling level (0 - 9).
+ * @ret_temp: Address to store the retrieved temperature value on success.
+ *
+ * Evaluate the _ACx object for the thermal zone represented by @adev to obtain
+ * the temperature of the active cooling trip point corresponding to the active
+ * cooling level given by @id.
+ *
+ * Return 0 on success or a negative error value on failure.
+ */
+int thermal_acpi_active_trip_temp(struct acpi_device *adev, int id, int *ret_temp)
+{
+	int temp_decik = 0;
+	int ret = acpi_active_trip_temp(adev, id, &temp_decik);
+
+	return thermal_temp(ret, temp_decik, ret_temp);
+}
+EXPORT_SYMBOL_GPL(thermal_acpi_active_trip_temp);
+
+/**
+ * thermal_acpi_passive_trip_temp - Retrieve passive trip point temperature
+ * @adev: Target thermal zone ACPI device object.
+ * @ret_temp: Address to store the retrieved temperature value on success.
+ *
+ * Evaluate the _PSV object for the thermal zone represented by @adev to obtain
+ * the temperature of the passive cooling trip point.
+ *
+ * Return 0 on success or -ENODATA on failure.
+ */
+int thermal_acpi_passive_trip_temp(struct acpi_device *adev, int *ret_temp)
+{
+	int temp_decik = 0;
+	int ret = acpi_passive_trip_temp(adev, &temp_decik);
+
+	return thermal_temp(ret, temp_decik, ret_temp);
+}
+EXPORT_SYMBOL_GPL(thermal_acpi_passive_trip_temp);
+
+/**
+ * thermal_acpi_hot_trip_temp - Retrieve hot trip point temperature
+ * @adev: Target thermal zone ACPI device object.
+ * @ret_temp: Address to store the retrieved temperature value on success.
+ *
+ * Evaluate the _HOT object for the thermal zone represented by @adev to obtain
+ * the temperature of the trip point at which the system is expected to be put
+ * into the S4 sleep state.
+ *
+ * Return 0 on success or -ENODATA on failure.
+ */
+int thermal_acpi_hot_trip_temp(struct acpi_device *adev, int *ret_temp)
+{
+	int temp_decik = 0;
+	int ret = acpi_hot_trip_temp(adev, &temp_decik);
+
+	return thermal_temp(ret, temp_decik, ret_temp);
+}
+EXPORT_SYMBOL_GPL(thermal_acpi_hot_trip_temp);
+
+/**
+ * thermal_acpi_critical_trip_temp - Retrieve critical trip point temperature
+ * @adev: Target thermal zone ACPI device object.
+ * @ret_temp: Address to store the retrieved temperature value on success.
+ *
+ * Evaluate the _CRT object for the thermal zone represented by @adev to obtain
+ * the temperature of the critical cooling trip point.
+ *
+ * Return 0 on success or -ENODATA on failure.
+ */
+int thermal_acpi_critical_trip_temp(struct acpi_device *adev, int *ret_temp)
+{
+	int temp_decik = 0;
+	int ret = acpi_critical_trip_temp(adev, &temp_decik);
+
+	return thermal_temp(ret, temp_decik, ret_temp);
+}
+EXPORT_SYMBOL_GPL(thermal_acpi_critical_trip_temp);
diff --git a/drivers/acpi/tiny-power-button.c b/drivers/acpi/tiny-power-button.c
index 6273d73c0b59..6353be6fec69 100644
--- a/drivers/acpi/tiny-power-button.c
+++ b/drivers/acpi/tiny-power-button.c
@@ -4,7 +4,6 @@
 #include <linux/acpi.h>
 #include <acpi/button.h>
 
-ACPI_MODULE_NAME("tiny-power-button");
 MODULE_AUTHOR("Josh Triplett");
 MODULE_DESCRIPTION("ACPI Tiny Power Button Driver");
 MODULE_LICENSE("GPL");
@@ -20,14 +19,52 @@ static const struct acpi_device_id tiny_power_button_device_ids[] = {
 };
 MODULE_DEVICE_TABLE(acpi, tiny_power_button_device_ids);
 
-static int acpi_noop_add_remove(struct acpi_device *device)
+static void acpi_tiny_power_button_notify(acpi_handle handle, u32 event, void *data)
 {
+	kill_cad_pid(power_signal, 1);
+}
+
+static void acpi_tiny_power_button_notify_run(void *not_used)
+{
+	acpi_tiny_power_button_notify(NULL, ACPI_FIXED_HARDWARE_EVENT, NULL);
+}
+
+static u32 acpi_tiny_power_button_event(void *not_used)
+{
+	acpi_os_execute(OSL_NOTIFY_HANDLER, acpi_tiny_power_button_notify_run, NULL);
+	return ACPI_INTERRUPT_HANDLED;
+}
+
+static int acpi_tiny_power_button_add(struct acpi_device *device)
+{
+	acpi_status status;
+
+	if (device->device_type == ACPI_BUS_TYPE_POWER_BUTTON) {
+		status = acpi_install_fixed_event_handler(ACPI_EVENT_POWER_BUTTON,
+							  acpi_tiny_power_button_event,
+							  NULL);
+	} else {
+		status = acpi_install_notify_handler(device->handle,
+						     ACPI_DEVICE_NOTIFY,
+						     acpi_tiny_power_button_notify,
+						     NULL);
+	}
+	if (ACPI_FAILURE(status))
+		return -ENODEV;
+
 	return 0;
 }
 
-static void acpi_tiny_power_button_notify(struct acpi_device *device, u32 event)
+static void acpi_tiny_power_button_remove(struct acpi_device *device)
 {
-	kill_cad_pid(power_signal, 1);
+	if (device->device_type == ACPI_BUS_TYPE_POWER_BUTTON) {
+		acpi_remove_fixed_event_handler(ACPI_EVENT_POWER_BUTTON,
+						acpi_tiny_power_button_event);
+	} else {
+		acpi_remove_notify_handler(device->handle, ACPI_DEVICE_NOTIFY,
+					   acpi_tiny_power_button_notify);
+	}
+	acpi_os_wait_events_complete();
 }
 
 static struct acpi_driver acpi_tiny_power_button_driver = {
@@ -35,12 +72,9 @@ static struct acpi_driver acpi_tiny_power_button_driver = {
 	.class = "tiny-power-button",
 	.ids = tiny_power_button_device_ids,
 	.ops = {
-		.add = acpi_noop_add_remove,
-		.remove = acpi_noop_add_remove,
-		.notify = acpi_tiny_power_button_notify,
+		.add = acpi_tiny_power_button_add,
+		.remove = acpi_tiny_power_button_remove,
 	},
 };
 
-module_driver(acpi_tiny_power_button_driver,
-		acpi_bus_register_driver,
-		acpi_bus_unregister_driver);
+module_acpi_driver(acpi_tiny_power_button_driver);
diff --git a/drivers/acpi/utils.c b/drivers/acpi/utils.c
index 804ac0df58ec..526563a0d188 100644
--- a/drivers/acpi/utils.c
+++ b/drivers/acpi/utils.c
@@ -6,6 +6,8 @@
  *  Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
  */
 
+#define pr_fmt(fmt) "ACPI: utils: " fmt
+
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/slab.h>
@@ -18,24 +20,12 @@
 #include "internal.h"
 #include "sleep.h"
 
-#define _COMPONENT		ACPI_BUS_COMPONENT
-ACPI_MODULE_NAME("utils");
-
 /* --------------------------------------------------------------------------
                             Object Evaluation Helpers
    -------------------------------------------------------------------------- */
-static void
-acpi_util_eval_error(acpi_handle h, acpi_string p, acpi_status s)
-{
-#ifdef ACPI_DEBUG_OUTPUT
-	char prefix[80] = {'\0'};
-	struct acpi_buffer buffer = {sizeof(prefix), prefix};
-	acpi_get_name(h, ACPI_FULL_PATHNAME, &buffer);
-	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Evaluate [%s.%s]: %s\n",
-		(char *) prefix, p, acpi_format_exception(s)));
-#else
-	return;
-#endif
+static void acpi_util_eval_error(acpi_handle h, acpi_string p, acpi_status s)
+{
+	acpi_handle_debug(h, "Evaluate [%s]: %s\n", p, acpi_format_exception(s));
 }
 
 acpi_status
@@ -53,25 +43,24 @@ acpi_extract_package(union acpi_object *package,
 
 	if (!package || (package->type != ACPI_TYPE_PACKAGE)
 	    || (package->package.count < 1)) {
-		printk(KERN_WARNING PREFIX "Invalid package argument\n");
+		pr_debug("Invalid package argument\n");
 		return AE_BAD_PARAMETER;
 	}
 
 	if (!format || !format->pointer || (format->length < 1)) {
-		printk(KERN_WARNING PREFIX "Invalid format argument\n");
+		pr_debug("Invalid format argument\n");
 		return AE_BAD_PARAMETER;
 	}
 
 	if (!buffer) {
-		printk(KERN_WARNING PREFIX "Invalid buffer argument\n");
+		pr_debug("Invalid buffer argument\n");
 		return AE_BAD_PARAMETER;
 	}
 
 	format_count = (format->length / sizeof(char)) - 1;
 	if (format_count > package->package.count) {
-		printk(KERN_WARNING PREFIX "Format specifies more objects [%d]"
-			      " than exist in package [%d].\n",
-			      format_count, package->package.count);
+		pr_debug("Format specifies more objects [%d] than present [%d]\n",
+			 format_count, package->package.count);
 		return AE_BAD_DATA;
 	}
 
@@ -99,12 +88,9 @@ acpi_extract_package(union acpi_object *package,
 				tail_offset += sizeof(char *);
 				break;
 			default:
-				printk(KERN_WARNING PREFIX "Invalid package element"
-					      " [%d]: got number, expecting"
-					      " [%c]\n",
-					      i, format_string[i]);
+				pr_debug("Invalid package element [%d]: got number, expected [%c]\n",
+					 i, format_string[i]);
 				return AE_BAD_DATA;
-				break;
 			}
 			break;
 
@@ -124,12 +110,9 @@ acpi_extract_package(union acpi_object *package,
 				tail_offset += sizeof(u8 *);
 				break;
 			default:
-				printk(KERN_WARNING PREFIX "Invalid package element"
-					      " [%d] got string/buffer,"
-					      " expecting [%c]\n",
-					      i, format_string[i]);
+				pr_debug("Invalid package element [%d] got string/buffer, expected [%c]\n",
+					 i, format_string[i]);
 				return AE_BAD_DATA;
-				break;
 			}
 			break;
 		case ACPI_TYPE_LOCAL_REFERENCE:
@@ -139,23 +122,17 @@ acpi_extract_package(union acpi_object *package,
 				tail_offset += sizeof(void *);
 				break;
 			default:
-				printk(KERN_WARNING PREFIX "Invalid package element"
-					      " [%d] got reference,"
-					      " expecting [%c]\n",
-					      i, format_string[i]);
+				pr_debug("Invalid package element [%d] got reference, expected [%c]\n",
+					 i, format_string[i]);
 				return AE_BAD_DATA;
-				break;
 			}
 			break;
 
 		case ACPI_TYPE_PACKAGE:
 		default:
-			ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-					  "Found unsupported element at index=%d\n",
-					  i));
+			pr_debug("Unsupported element at index=%d\n", i);
 			/* TBD: handle nested packages... */
 			return AE_SUPPORT;
-			break;
 		}
 	}
 
@@ -293,30 +270,88 @@ acpi_evaluate_integer(acpi_handle handle,
 
 	*data = element.integer.value;
 
-	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Return value [%llu]\n", *data));
+	acpi_handle_debug(handle, "Return value [%llu]\n", *data);
 
 	return AE_OK;
 }
 
 EXPORT_SYMBOL(acpi_evaluate_integer);
 
-acpi_status
-acpi_evaluate_reference(acpi_handle handle,
-			acpi_string pathname,
-			struct acpi_object_list *arguments,
-			struct acpi_handle_list *list)
+int acpi_get_local_u64_address(acpi_handle handle, u64 *addr)
+{
+	acpi_status status;
+
+	status = acpi_evaluate_integer(handle, METHOD_NAME__ADR, NULL, addr);
+	if (ACPI_FAILURE(status))
+		return -ENODATA;
+	return 0;
+}
+EXPORT_SYMBOL(acpi_get_local_u64_address);
+
+int acpi_get_local_address(acpi_handle handle, u32 *addr)
+{
+	u64 adr;
+	int ret;
+
+	ret = acpi_get_local_u64_address(handle, &adr);
+	if (ret < 0)
+		return ret;
+	*addr = (u32)adr;
+	return 0;
+}
+EXPORT_SYMBOL(acpi_get_local_address);
+
+#define ACPI_MAX_SUB_BUF_SIZE	9
+
+const char *acpi_get_subsystem_id(acpi_handle handle)
 {
-	acpi_status status = AE_OK;
-	union acpi_object *package = NULL;
-	union acpi_object *element = NULL;
 	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
-	u32 i = 0;
+	union acpi_object *obj;
+	acpi_status status;
+	const char *sub;
+	size_t len;
 
+	status = acpi_evaluate_object(handle, METHOD_NAME__SUB, NULL, &buffer);
+	if (ACPI_FAILURE(status)) {
+		acpi_handle_debug(handle, "Reading ACPI _SUB failed: %#x\n", status);
+		return ERR_PTR(-ENODATA);
+	}
 
-	if (!list) {
-		return AE_BAD_PARAMETER;
+	obj = buffer.pointer;
+	if (obj->type == ACPI_TYPE_STRING) {
+		len = strlen(obj->string.pointer);
+		if (len < ACPI_MAX_SUB_BUF_SIZE && len > 0) {
+			sub = kstrdup(obj->string.pointer, GFP_KERNEL);
+			if (!sub)
+				sub = ERR_PTR(-ENOMEM);
+		} else {
+			acpi_handle_err(handle, "ACPI _SUB Length %zu is Invalid\n", len);
+			sub = ERR_PTR(-ENODATA);
+		}
+	} else {
+		acpi_handle_warn(handle, "Warning ACPI _SUB did not return a string\n");
+		sub = ERR_PTR(-ENODATA);
 	}
 
+	acpi_os_free(buffer.pointer);
+
+	return sub;
+}
+EXPORT_SYMBOL_GPL(acpi_get_subsystem_id);
+
+bool acpi_evaluate_reference(acpi_handle handle, acpi_string pathname,
+			     struct acpi_object_list *arguments,
+			     struct acpi_handle_list *list)
+{
+	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
+	union acpi_object *package;
+	acpi_status status;
+	bool ret = false;
+	u32 i;
+
+	if (!list)
+		return false;
+
 	/* Evaluate object. */
 
 	status = acpi_evaluate_object(handle, pathname, arguments, &buffer);
@@ -325,66 +360,141 @@ acpi_evaluate_reference(acpi_handle handle,
 
 	package = buffer.pointer;
 
-	if ((buffer.length == 0) || !package) {
-		status = AE_BAD_DATA;
-		acpi_util_eval_error(handle, pathname, status);
-		goto end;
-	}
-	if (package->type != ACPI_TYPE_PACKAGE) {
-		status = AE_BAD_DATA;
-		acpi_util_eval_error(handle, pathname, status);
-		goto end;
-	}
-	if (!package->package.count) {
-		status = AE_BAD_DATA;
-		acpi_util_eval_error(handle, pathname, status);
-		goto end;
-	}
+	if (buffer.length == 0 || !package ||
+	    package->type != ACPI_TYPE_PACKAGE || !package->package.count)
+		goto err;
 
-	if (package->package.count > ACPI_MAX_HANDLES) {
-		kfree(package);
-		return AE_NO_MEMORY;
-	}
 	list->count = package->package.count;
+	list->handles = kcalloc(list->count, sizeof(*list->handles), GFP_KERNEL);
+	if (!list->handles)
+		goto err_clear;
 
 	/* Extract package data. */
 
 	for (i = 0; i < list->count; i++) {
+		union acpi_object *element = &(package->package.elements[i]);
 
-		element = &(package->package.elements[i]);
-
-		if (element->type != ACPI_TYPE_LOCAL_REFERENCE) {
-			status = AE_BAD_DATA;
-			acpi_util_eval_error(handle, pathname, status);
-			break;
-		}
+		if (element->type != ACPI_TYPE_LOCAL_REFERENCE ||
+		    !element->reference.handle)
+			goto err_free;
 
-		if (!element->reference.handle) {
-			status = AE_NULL_ENTRY;
-			acpi_util_eval_error(handle, pathname, status);
-			break;
-		}
 		/* Get the  acpi_handle. */
 
 		list->handles[i] = element->reference.handle;
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found reference [%p]\n",
-				  list->handles[i]));
+		acpi_handle_debug(list->handles[i], "Found in reference list\n");
 	}
 
-      end:
-	if (ACPI_FAILURE(status)) {
-		list->count = 0;
-		//kfree(list->handles);
-	}
+	ret = true;
 
+end:
 	kfree(buffer.pointer);
 
-	return status;
+	return ret;
+
+err_free:
+	kfree(list->handles);
+	list->handles = NULL;
+
+err_clear:
+	list->count = 0;
+
+err:
+	acpi_util_eval_error(handle, pathname, status);
+	goto end;
 }
 
 EXPORT_SYMBOL(acpi_evaluate_reference);
 
-acpi_status
+/**
+ * acpi_handle_list_equal - Check if two ACPI handle lists are the same
+ * @list1: First list to compare.
+ * @list2: Second list to compare.
+ *
+ * Return true if the given ACPI handle lists are of the same size and
+ * contain the same ACPI handles in the same order.  Otherwise, return false.
+ */
+bool acpi_handle_list_equal(struct acpi_handle_list *list1,
+			    struct acpi_handle_list *list2)
+{
+	return list1->count == list2->count &&
+		!memcmp(list1->handles, list2->handles,
+		        list1->count * sizeof(*list1->handles));
+}
+EXPORT_SYMBOL_GPL(acpi_handle_list_equal);
+
+/**
+ * acpi_handle_list_replace - Replace one ACPI handle list with another
+ * @dst: ACPI handle list to replace.
+ * @src: Source ACPI handle list.
+ *
+ * Free the handles table in @dst, move the handles table from @src to @dst,
+ * copy count from @src to @dst and clear @src.
+ */
+void acpi_handle_list_replace(struct acpi_handle_list *dst,
+			      struct acpi_handle_list *src)
+{
+	if (dst->count)
+		kfree(dst->handles);
+
+	dst->count = src->count;
+	dst->handles = src->handles;
+
+	src->handles = NULL;
+	src->count = 0;
+}
+EXPORT_SYMBOL_GPL(acpi_handle_list_replace);
+
+/**
+ * acpi_handle_list_free - Free the handles table in an ACPI handle list
+ * @list: ACPI handle list to free.
+ *
+ * Free the handles table in @list and clear its count field.
+ */
+void acpi_handle_list_free(struct acpi_handle_list *list)
+{
+	if (!list->count)
+		return;
+
+	kfree(list->handles);
+	list->count = 0;
+}
+EXPORT_SYMBOL_GPL(acpi_handle_list_free);
+
+/**
+ * acpi_device_dep - Check ACPI device dependency
+ * @target: ACPI handle of the target ACPI device.
+ * @match: ACPI handle to look up in the target's _DEP list.
+ *
+ * Return true if @match is present in the list returned by _DEP for
+ * @target or false otherwise.
+ */
+bool acpi_device_dep(acpi_handle target, acpi_handle match)
+{
+	struct acpi_handle_list dep_devices;
+	bool ret = false;
+	int i;
+
+	if (!acpi_has_method(target, "_DEP"))
+		return false;
+
+	if (!acpi_evaluate_reference(target, "_DEP", NULL, &dep_devices)) {
+		acpi_handle_debug(target, "Failed to evaluate _DEP.\n");
+		return false;
+	}
+
+	for (i = 0; i < dep_devices.count; i++) {
+		if (dep_devices.handles[i] == match) {
+			ret = true;
+			break;
+		}
+	}
+
+	acpi_handle_list_free(&dep_devices);
+	return ret;
+}
+EXPORT_SYMBOL_GPL(acpi_device_dep);
+
+bool
 acpi_get_physical_device_location(acpi_handle handle, struct acpi_pld_info **pld)
 {
 	acpi_status status;
@@ -392,9 +502,8 @@ acpi_get_physical_device_location(acpi_handle handle, struct acpi_pld_info **pld
 	union acpi_object *output;
 
 	status = acpi_evaluate_object(handle, "_PLD", NULL, &buffer);
-
 	if (ACPI_FAILURE(status))
-		return status;
+		return false;
 
 	output = buffer.pointer;
 
@@ -413,7 +522,7 @@ acpi_get_physical_device_location(acpi_handle handle, struct acpi_pld_info **pld
 
 out:
 	kfree(buffer.pointer);
-	return status;
+	return ACPI_SUCCESS(status);
 }
 EXPORT_SYMBOL(acpi_get_physical_device_location);
 
@@ -459,7 +568,7 @@ EXPORT_SYMBOL(acpi_evaluate_ost);
  *
  * Caller must free the returned buffer
  */
-static char *acpi_handle_path(acpi_handle handle)
+char *acpi_handle_path(acpi_handle handle)
 {
 	struct acpi_buffer buffer = {
 		.length = ACPI_ALLOCATE_BUFFER,
@@ -495,7 +604,7 @@ acpi_handle_printk(const char *level, acpi_handle handle, const char *fmt, ...)
 	vaf.va = &args;
 
 	path = acpi_handle_path(handle);
-	printk("%sACPI: %s: %pV", level, path ? path : "<n/a>" , &vaf);
+	printk("%sACPI: %s: %pV", level, path ? path : "<n/a>", &vaf);
 
 	va_end(args);
 	kfree(path);
@@ -536,6 +645,20 @@ EXPORT_SYMBOL(__acpi_handle_debug);
 #endif
 
 /**
+ * acpi_evaluation_failure_warn - Log evaluation failure warning.
+ * @handle: Parent object handle.
+ * @name: Name of the object whose evaluation has failed.
+ * @status: Status value returned by the failing object evaluation.
+ */
+void acpi_evaluation_failure_warn(acpi_handle handle, const char *name,
+				  acpi_status status)
+{
+	acpi_handle_warn(handle, "%s evaluation failed: %s\n", name,
+			 acpi_format_exception(status));
+}
+EXPORT_SYMBOL_GPL(acpi_evaluation_failure_warn);
+
+/**
  * acpi_has_method: Check whether @handle has a method named @name
  * @handle: ACPI device handle
  * @name: name of object or method
@@ -606,6 +729,31 @@ acpi_status acpi_evaluate_lck(acpi_handle handle, int lock)
 }
 
 /**
+ * acpi_evaluate_reg: Evaluate _REG method to register OpRegion presence
+ * @handle: ACPI device handle
+ * @space_id: ACPI address space id to register OpRegion presence for
+ * @function: Parameter to pass to _REG one of ACPI_REG_CONNECT or
+ *            ACPI_REG_DISCONNECT
+ *
+ * Evaluate device's _REG method to register OpRegion presence.
+ */
+acpi_status acpi_evaluate_reg(acpi_handle handle, u8 space_id, u32 function)
+{
+	struct acpi_object_list arg_list;
+	union acpi_object params[2];
+
+	params[0].type = ACPI_TYPE_INTEGER;
+	params[0].integer.value = space_id;
+	params[1].type = ACPI_TYPE_INTEGER;
+	params[1].integer.value = function;
+	arg_list.count = 2;
+	arg_list.pointer = params;
+
+	return acpi_evaluate_object(handle, "_REG", &arg_list, NULL);
+}
+EXPORT_SYMBOL(acpi_evaluate_reg);
+
+/**
  * acpi_evaluate_dsm - evaluate device's _DSM method
  * @handle: ACPI device handle
  * @guid: GUID of requested functions, should be 16 bytes
@@ -652,7 +800,8 @@ acpi_evaluate_dsm(acpi_handle handle, const guid_t *guid, u64 rev, u64 func,
 
 	if (ret != AE_NOT_FOUND)
 		acpi_handle_warn(handle,
-				"failed to evaluate _DSM (0x%x)\n", ret);
+				 "failed to evaluate _DSM %pUb rev:%lld func:%lld (0x%x)\n",
+				 guid, rev, func, ret);
 
 	return NULL;
 }
@@ -702,29 +851,28 @@ bool acpi_check_dsm(acpi_handle handle, const guid_t *guid, u64 rev, u64 funcs)
 EXPORT_SYMBOL(acpi_check_dsm);
 
 /**
- * acpi_dev_hid_uid_match - Match device by supplied HID and UID
- * @adev: ACPI device to match.
- * @hid2: Hardware ID of the device.
- * @uid2: Unique ID of the device, pass NULL to not check _UID.
+ * acpi_dev_uid_to_integer - treat ACPI device _UID as integer
+ * @adev: ACPI device to get _UID from
+ * @integer: output buffer for integer
  *
- * Matches HID and UID in @adev with given @hid2 and @uid2.
- * Returns true if matches.
+ * Considers _UID as integer and converts it to @integer.
+ *
+ * Returns 0 on success, or negative error code otherwise.
  */
-bool acpi_dev_hid_uid_match(struct acpi_device *adev,
-			    const char *hid2, const char *uid2)
+int acpi_dev_uid_to_integer(struct acpi_device *adev, u64 *integer)
 {
-	const char *hid1 = acpi_device_hid(adev);
-	const char *uid1 = acpi_device_uid(adev);
+	const char *uid;
 
-	if (strcmp(hid1, hid2))
-		return false;
+	if (!adev)
+		return -ENODEV;
 
-	if (!uid2)
-		return true;
+	uid = acpi_device_uid(adev);
+	if (!uid)
+		return -ENODATA;
 
-	return uid1 && !strcmp(uid1, uid2);
+	return kstrtou64(uid, 0, integer);
 }
-EXPORT_SYMBOL(acpi_dev_hid_uid_match);
+EXPORT_SYMBOL(acpi_dev_uid_to_integer);
 
 /**
  * acpi_dev_found - Detect presence of a given ACPI device in the namespace.
@@ -772,8 +920,7 @@ static int acpi_dev_match_cb(struct device *dev, const void *data)
 	if (acpi_match_device_ids(adev, match->hid))
 		return 0;
 
-	if (match->uid && (!adev->pnp.unique_id ||
-	    strcmp(adev->pnp.unique_id, match->uid)))
+	if (match->uid && !acpi_dev_uid_match(adev, match->uid))
 		return 0;
 
 	if (match->hrv == -1)
@@ -796,7 +943,7 @@ static int acpi_dev_match_cb(struct device *dev, const void *data)
  * Note that if the device is pluggable, it may since have disappeared.
  *
  * Note that unlike acpi_dev_found() this function checks the status
- * of the device. So for devices which are present in the dsdt, but
+ * of the device. So for devices which are present in the DSDT, but
  * which are disabled (their _STA callback returns 0) this function
  * will return false.
  *
@@ -811,7 +958,7 @@ bool acpi_dev_present(const char *hid, const char *uid, s64 hrv)
 	struct acpi_dev_match_info match = {};
 	struct device *dev;
 
-	strlcpy(match.hid[0].id, hid, sizeof(match.hid[0].id));
+	strscpy(match.hid[0].id, hid, sizeof(match.hid[0].id));
 	match.uid = uid;
 	match.hrv = hrv;
 
@@ -822,33 +969,69 @@ bool acpi_dev_present(const char *hid, const char *uid, s64 hrv)
 EXPORT_SYMBOL(acpi_dev_present);
 
 /**
- * acpi_dev_get_first_match_dev - Return the first match of ACPI device
+ * acpi_dev_get_next_match_dev - Return the next match of ACPI device
+ * @adev: Pointer to the previous ACPI device matching this @hid, @uid and @hrv
  * @hid: Hardware ID of the device.
  * @uid: Unique ID of the device, pass NULL to not check _UID
  * @hrv: Hardware Revision of the device, pass -1 to not check _HRV
  *
- * Return the first match of ACPI device if a matching device was present
+ * Return the next match of ACPI device if another matching device was present
  * at the moment of invocation, or NULL otherwise.
  *
- * The caller is responsible to call put_device() on the returned device.
+ * The caller is responsible for invoking acpi_dev_put() on the returned device.
+ * On the other hand the function invokes  acpi_dev_put() on the given @adev
+ * assuming that its reference counter had been increased beforehand.
  *
  * See additional information in acpi_dev_present() as well.
  */
 struct acpi_device *
-acpi_dev_get_first_match_dev(const char *hid, const char *uid, s64 hrv)
+acpi_dev_get_next_match_dev(struct acpi_device *adev, const char *hid, const char *uid, s64 hrv)
 {
+	struct device *start = adev ? &adev->dev : NULL;
 	struct acpi_dev_match_info match = {};
 	struct device *dev;
 
-	strlcpy(match.hid[0].id, hid, sizeof(match.hid[0].id));
+	strscpy(match.hid[0].id, hid, sizeof(match.hid[0].id));
 	match.uid = uid;
 	match.hrv = hrv;
 
-	dev = bus_find_device(&acpi_bus_type, NULL, &match, acpi_dev_match_cb);
+	dev = bus_find_device(&acpi_bus_type, start, &match, acpi_dev_match_cb);
+	acpi_dev_put(adev);
 	return dev ? to_acpi_device(dev) : NULL;
 }
+EXPORT_SYMBOL(acpi_dev_get_next_match_dev);
+
+/**
+ * acpi_dev_get_first_match_dev - Return the first match of ACPI device
+ * @hid: Hardware ID of the device.
+ * @uid: Unique ID of the device, pass NULL to not check _UID
+ * @hrv: Hardware Revision of the device, pass -1 to not check _HRV
+ *
+ * Return the first match of ACPI device if a matching device was present
+ * at the moment of invocation, or NULL otherwise.
+ *
+ * The caller is responsible for invoking acpi_dev_put() on the returned device.
+ *
+ * See additional information in acpi_dev_present() as well.
+ */
+struct acpi_device *
+acpi_dev_get_first_match_dev(const char *hid, const char *uid, s64 hrv)
+{
+	return acpi_dev_get_next_match_dev(NULL, hid, uid, hrv);
+}
 EXPORT_SYMBOL(acpi_dev_get_first_match_dev);
 
+/**
+ * acpi_reduced_hardware - Return if this is an ACPI-reduced-hw machine
+ *
+ * Return true when running on an ACPI-reduced-hw machine, false otherwise.
+ */
+bool acpi_reduced_hardware(void)
+{
+	return acpi_gbl_reduced_hardware;
+}
+EXPORT_SYMBOL_GPL(acpi_reduced_hardware);
+
 /*
  * acpi_backlight= handling, this is done here rather then in video_detect.c
  * because __setup cannot be used in modules.
@@ -858,7 +1041,7 @@ EXPORT_SYMBOL(acpi_video_backlight_string);
 
 static int __init acpi_backlight(char *str)
 {
-	strlcpy(acpi_video_backlight_string, str,
+	strscpy(acpi_video_backlight_string, str,
 		sizeof(acpi_video_backlight_string));
 	return 1;
 }
diff --git a/drivers/acpi/video_detect.c b/drivers/acpi/video_detect.c
index b4994e50608d..4cf74f173c78 100644
--- a/drivers/acpi/video_detect.c
+++ b/drivers/acpi/video_detect.c
@@ -17,8 +17,9 @@
  * Otherwise vendor specific drivers like thinkpad_acpi, asus-laptop,
  * sony_acpi,... can take care about backlight brightness.
  *
- * Backlight drivers can use acpi_video_get_backlight_type() to determine
- * which driver should handle the backlight.
+ * Backlight drivers can use acpi_video_get_backlight_type() to determine which
+ * driver should handle the backlight. RAW/GPU-driver backlight drivers must
+ * use the acpi_video_backlight_use_native() helper for this.
  *
  * If CONFIG_ACPI_VIDEO is neither set as "compiled in" (y) nor as a module (m)
  * this file will not be compiled and acpi_video_get_backlight_type() will
@@ -27,23 +28,17 @@
 
 #include <linux/export.h>
 #include <linux/acpi.h>
+#include <linux/apple-gmux.h>
 #include <linux/backlight.h>
 #include <linux/dmi.h>
 #include <linux/module.h>
 #include <linux/pci.h>
+#include <linux/platform_data/x86/nvidia-wmi-ec-backlight.h>
+#include <linux/pnp.h>
 #include <linux/types.h>
 #include <linux/workqueue.h>
 #include <acpi/video.h>
 
-ACPI_MODULE_NAME("video");
-#define _COMPONENT		ACPI_VIDEO_COMPONENT
-
-void acpi_video_unregister_backlight(void);
-
-static bool backlight_notifier_registered;
-static struct notifier_block backlight_nb;
-static struct work_struct backlight_notify_work;
-
 static enum acpi_backlight_type acpi_backlight_cmdline = acpi_backlight_undef;
 static enum acpi_backlight_type acpi_backlight_dmi = acpi_backlight_undef;
 
@@ -55,6 +50,12 @@ static void acpi_video_parse_cmdline(void)
 		acpi_backlight_cmdline = acpi_backlight_video;
 	if (!strcmp("native", acpi_video_backlight_string))
 		acpi_backlight_cmdline = acpi_backlight_native;
+	if (!strcmp("nvidia_wmi_ec", acpi_video_backlight_string))
+		acpi_backlight_cmdline = acpi_backlight_nvidia_wmi_ec;
+	if (!strcmp("apple_gmux", acpi_video_backlight_string))
+		acpi_backlight_cmdline = acpi_backlight_apple_gmux;
+	if (!strcmp("dell_uart", acpi_video_backlight_string))
+		acpi_backlight_cmdline = acpi_backlight_dell_uart;
 	if (!strcmp("none", acpi_video_backlight_string))
 		acpi_backlight_cmdline = acpi_backlight_none;
 }
@@ -62,18 +63,16 @@ static void acpi_video_parse_cmdline(void)
 static acpi_status
 find_video(acpi_handle handle, u32 lvl, void *context, void **rv)
 {
+	struct acpi_device *acpi_dev = acpi_fetch_acpi_dev(handle);
 	long *cap = context;
 	struct pci_dev *dev;
-	struct acpi_device *acpi_dev;
 
 	static const struct acpi_device_id video_ids[] = {
 		{ACPI_VIDEO_HID, 0},
 		{"", 0},
 	};
-	if (acpi_bus_get_device(handle, &acpi_dev))
-		return AE_OK;
 
-	if (!acpi_match_device_ids(acpi_dev, video_ids)) {
+	if (acpi_dev && !acpi_match_device_ids(acpi_dev, video_ids)) {
 		dev = acpi_get_pci_dev(handle);
 		if (!dev)
 			return AE_OK;
@@ -83,6 +82,36 @@ find_video(acpi_handle handle, u32 lvl, void *context, void **rv)
 	return AE_OK;
 }
 
+/* This depends on ACPI_WMI which is X86 only */
+#ifdef CONFIG_X86
+static bool nvidia_wmi_ec_supported(void)
+{
+	struct wmi_brightness_args args = {
+		.mode = WMI_BRIGHTNESS_MODE_GET,
+		.val = 0,
+		.ret = 0,
+	};
+	struct acpi_buffer buf = { (acpi_size)sizeof(args), &args };
+	acpi_status status;
+
+	status = wmi_evaluate_method(WMI_BRIGHTNESS_GUID, 0,
+				     WMI_BRIGHTNESS_METHOD_SOURCE, &buf, &buf);
+	if (ACPI_FAILURE(status))
+		return false;
+
+	/*
+	 * If brightness is handled by the EC then nvidia-wmi-ec-backlight
+	 * should be used, else the GPU driver(s) should be used.
+	 */
+	return args.ret == WMI_BRIGHTNESS_SOURCE_EC;
+}
+#else
+static bool nvidia_wmi_ec_supported(void)
+{
+	return false;
+}
+#endif
+
 /* Force to use vendor driver when the ACPI device is known to be
  * buggy */
 static int video_detect_force_vendor(const struct dmi_system_id *d)
@@ -103,50 +132,192 @@ static int video_detect_force_native(const struct dmi_system_id *d)
 	return 0;
 }
 
-static int video_detect_force_none(const struct dmi_system_id *d)
+static int video_detect_portege_r100(const struct dmi_system_id *d)
 {
-	acpi_backlight_dmi = acpi_backlight_none;
+	struct pci_dev *dev;
+	/* Search for Trident CyberBlade XP4m32 to confirm Portégé R100 */
+	dev = pci_get_device(PCI_VENDOR_ID_TRIDENT, 0x2100, NULL);
+	if (dev)
+		acpi_backlight_dmi = acpi_backlight_vendor;
 	return 0;
 }
 
 static const struct dmi_system_id video_detect_dmi_table[] = {
-	/* On Samsung X360, the BIOS will set a flag (VDRV) if generic
-	 * ACPI backlight device is used. This flag will definitively break
-	 * the backlight interface (even the vendor interface) until next
-	 * reboot. It's why we should prevent video.ko from being used here
-	 * and we can't rely on a later call to acpi_video_unregister().
+	/*
+	 * Models which should use the vendor backlight interface,
+	 * because of broken ACPI video backlight control.
 	 */
 	{
+	 /* https://bugzilla.redhat.com/show_bug.cgi?id=1128309 */
 	 .callback = video_detect_force_vendor,
-	 .ident = "X360",
+	 /* Acer KAV80 */
 	 .matches = {
-		DMI_MATCH(DMI_SYS_VENDOR, "SAMSUNG ELECTRONICS CO., LTD."),
-		DMI_MATCH(DMI_PRODUCT_NAME, "X360"),
-		DMI_MATCH(DMI_BOARD_NAME, "X360"),
+		DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
+		DMI_MATCH(DMI_PRODUCT_NAME, "KAV80"),
 		},
 	},
 	{
-	.callback = video_detect_force_vendor,
-	.ident = "Asus UL30VT",
-	.matches = {
+	 .callback = video_detect_force_vendor,
+	 /* Asus UL30VT */
+	 .matches = {
 		DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."),
 		DMI_MATCH(DMI_PRODUCT_NAME, "UL30VT"),
 		},
 	},
 	{
-	.callback = video_detect_force_vendor,
-	.ident = "Asus UL30A",
-	.matches = {
+	 .callback = video_detect_force_vendor,
+	 /* Asus UL30A */
+	 .matches = {
 		DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."),
 		DMI_MATCH(DMI_PRODUCT_NAME, "UL30A"),
 		},
 	},
 	{
-	.callback = video_detect_force_vendor,
-	.ident = "Sony VPCEH3U1E",
-	.matches = {
+	 .callback = video_detect_force_vendor,
+	 /* Asus X55U */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
+		DMI_MATCH(DMI_PRODUCT_NAME, "X55U"),
+		},
+	},
+	{
+	 /* https://bugs.launchpad.net/bugs/1000146 */
+	 .callback = video_detect_force_vendor,
+	 /* Asus X101CH */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
+		DMI_MATCH(DMI_PRODUCT_NAME, "X101CH"),
+		},
+	},
+	{
+	 .callback = video_detect_force_vendor,
+	 /* Asus X401U */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
+		DMI_MATCH(DMI_PRODUCT_NAME, "X401U"),
+		},
+	},
+	{
+	 .callback = video_detect_force_vendor,
+	 /* Asus X501U */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
+		DMI_MATCH(DMI_PRODUCT_NAME, "X501U"),
+		},
+	},
+	{
+	 /* https://bugs.launchpad.net/bugs/1000146 */
+	 .callback = video_detect_force_vendor,
+	 /* Asus 1015CX */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
+		DMI_MATCH(DMI_PRODUCT_NAME, "1015CX"),
+		},
+	},
+	{
+	 .callback = video_detect_force_vendor,
+	 /* Samsung N150/N210/N220 */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "SAMSUNG ELECTRONICS CO., LTD."),
+		DMI_MATCH(DMI_PRODUCT_NAME, "N150/N210/N220"),
+		DMI_MATCH(DMI_BOARD_NAME, "N150/N210/N220"),
+		},
+	},
+	{
+	 .callback = video_detect_force_vendor,
+	 /* Samsung NF110/NF210/NF310 */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "SAMSUNG ELECTRONICS CO., LTD."),
+		DMI_MATCH(DMI_PRODUCT_NAME, "NF110/NF210/NF310"),
+		DMI_MATCH(DMI_BOARD_NAME, "NF110/NF210/NF310"),
+		},
+	},
+	{
+	 .callback = video_detect_force_vendor,
+	 /* Samsung NC210 */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "SAMSUNG ELECTRONICS CO., LTD."),
+		DMI_MATCH(DMI_PRODUCT_NAME, "NC210/NC110"),
+		DMI_MATCH(DMI_BOARD_NAME, "NC210/NC110"),
+		},
+	},
+
+	/*
+	 * Models which should use the vendor backlight interface,
+	 * because of broken native backlight control.
+	 */
+	{
+	 .callback = video_detect_force_vendor,
+	 /* Sony Vaio PCG-FRV35 */
+	 .matches = {
 		DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"),
-		DMI_MATCH(DMI_PRODUCT_NAME, "VPCEH3U1E"),
+		DMI_MATCH(DMI_PRODUCT_NAME, "PCG-FRV35"),
+		},
+	},
+	{
+	 .callback = video_detect_force_vendor,
+	 /* Panasonic Toughbook CF-18 */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "Matsushita Electric Industrial"),
+		DMI_MATCH(DMI_PRODUCT_NAME, "CF-18"),
+		},
+	},
+
+	/*
+	 * Toshiba models with Transflective display, these need to use
+	 * the toshiba_acpi vendor driver for proper Transflective handling.
+	 */
+	{
+	 .callback = video_detect_force_vendor,
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
+		DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE R500"),
+		},
+	},
+	{
+	 .callback = video_detect_force_vendor,
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
+		DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE R600"),
+		},
+	},
+
+	/*
+	 * Toshiba Portégé R100 has working both acpi_video and toshiba_acpi
+	 * vendor driver. But none of them gets activated as it has a VGA with
+	 * no kernel driver (Trident CyberBlade XP4m32).
+	 * The DMI strings are generic so check for the VGA chip in callback.
+	 */
+	{
+	 .callback = video_detect_portege_r100,
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
+		DMI_MATCH(DMI_PRODUCT_NAME, "Portable PC"),
+		DMI_MATCH(DMI_PRODUCT_VERSION, "Version 1.0"),
+		DMI_MATCH(DMI_BOARD_NAME, "Portable PC")
+		},
+	},
+
+	/*
+	 * Models which need acpi_video backlight control where the GPU drivers
+	 * do not call acpi_video_register_backlight() because no internal panel
+	 * is detected. Typically these are all-in-ones (monitors with builtin
+	 * PC) where the panel connection shows up as regular DP instead of eDP.
+	 */
+	{
+	 .callback = video_detect_force_video,
+	 /* Apple iMac14,1 */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
+		DMI_MATCH(DMI_PRODUCT_NAME, "iMac14,1"),
+		},
+	},
+	{
+	 .callback = video_detect_force_video,
+	 /* Apple iMac14,2 */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
+		DMI_MATCH(DMI_PRODUCT_NAME, "iMac14,2"),
 		},
 	},
 
@@ -159,7 +330,7 @@ static const struct dmi_system_id video_detect_dmi_table[] = {
 	 */
 	{
 	 .callback = video_detect_force_video,
-	 .ident = "ThinkPad T420",
+	 /* ThinkPad T420 */
 	 .matches = {
 		DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
 		DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T420"),
@@ -167,7 +338,7 @@ static const struct dmi_system_id video_detect_dmi_table[] = {
 	},
 	{
 	 .callback = video_detect_force_video,
-	 .ident = "ThinkPad T520",
+	 /* ThinkPad T520 */
 	 .matches = {
 		DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
 		DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T520"),
@@ -175,26 +346,26 @@ static const struct dmi_system_id video_detect_dmi_table[] = {
 	},
 	{
 	 .callback = video_detect_force_video,
-	 .ident = "ThinkPad X201s",
+	 /* ThinkPad X201s */
 	 .matches = {
 		DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
 		DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X201s"),
 		},
 	},
-        {
-         .callback = video_detect_force_video,
-         .ident = "ThinkPad X201T",
-         .matches = {
-                DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
-                DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X201T"),
-                },
-        },
+	{
+	 .callback = video_detect_force_video,
+	 /* ThinkPad X201T */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
+		DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X201T"),
+		},
+	},
 
 	/* The native backlight controls do not work on some older machines */
 	{
 	 /* https://bugs.freedesktop.org/show_bug.cgi?id=81515 */
 	 .callback = video_detect_force_video,
-	 .ident = "HP ENVY 15 Notebook",
+	 /* HP ENVY 15 Notebook */
 	 .matches = {
 		DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
 		DMI_MATCH(DMI_PRODUCT_NAME, "HP ENVY 15 Notebook PC"),
@@ -202,7 +373,7 @@ static const struct dmi_system_id video_detect_dmi_table[] = {
 	},
 	{
 	 .callback = video_detect_force_video,
-	 .ident = "SAMSUNG 870Z5E/880Z5E/680Z5E",
+	 /* SAMSUNG 870Z5E/880Z5E/680Z5E */
 	 .matches = {
 		DMI_MATCH(DMI_SYS_VENDOR, "SAMSUNG ELECTRONICS CO., LTD."),
 		DMI_MATCH(DMI_PRODUCT_NAME, "870Z5E/880Z5E/680Z5E"),
@@ -210,7 +381,7 @@ static const struct dmi_system_id video_detect_dmi_table[] = {
 	},
 	{
 	 .callback = video_detect_force_video,
-	 .ident = "SAMSUNG 370R4E/370R4V/370R5E/3570RE/370R5V",
+	 /* SAMSUNG 370R4E/370R4V/370R5E/3570RE/370R5V */
 	 .matches = {
 		DMI_MATCH(DMI_SYS_VENDOR, "SAMSUNG ELECTRONICS CO., LTD."),
 		DMI_MATCH(DMI_PRODUCT_NAME,
@@ -220,7 +391,7 @@ static const struct dmi_system_id video_detect_dmi_table[] = {
 	{
 	 /* https://bugzilla.redhat.com/show_bug.cgi?id=1186097 */
 	 .callback = video_detect_force_video,
-	 .ident = "SAMSUNG 3570R/370R/470R/450R/510R/4450RV",
+	 /* SAMSUNG 3570R/370R/470R/450R/510R/4450RV */
 	 .matches = {
 		DMI_MATCH(DMI_SYS_VENDOR, "SAMSUNG ELECTRONICS CO., LTD."),
 		DMI_MATCH(DMI_PRODUCT_NAME,
@@ -230,7 +401,7 @@ static const struct dmi_system_id video_detect_dmi_table[] = {
 	{
 	 /* https://bugzilla.redhat.com/show_bug.cgi?id=1557060 */
 	 .callback = video_detect_force_video,
-	 .ident = "SAMSUNG 670Z5E",
+	 /* SAMSUNG 670Z5E */
 	 .matches = {
 		DMI_MATCH(DMI_SYS_VENDOR, "SAMSUNG ELECTRONICS CO., LTD."),
 		DMI_MATCH(DMI_PRODUCT_NAME, "670Z5E"),
@@ -239,7 +410,7 @@ static const struct dmi_system_id video_detect_dmi_table[] = {
 	{
 	 /* https://bugzilla.redhat.com/show_bug.cgi?id=1094948 */
 	 .callback = video_detect_force_video,
-	 .ident = "SAMSUNG 730U3E/740U3E",
+	 /* SAMSUNG 730U3E/740U3E */
 	 .matches = {
 		DMI_MATCH(DMI_SYS_VENDOR, "SAMSUNG ELECTRONICS CO., LTD."),
 		DMI_MATCH(DMI_PRODUCT_NAME, "730U3E/740U3E"),
@@ -248,7 +419,7 @@ static const struct dmi_system_id video_detect_dmi_table[] = {
 	{
 	 /* https://bugs.freedesktop.org/show_bug.cgi?id=87286 */
 	 .callback = video_detect_force_video,
-	 .ident = "SAMSUNG 900X3C/900X3D/900X3E/900X4C/900X4D",
+	 /* SAMSUNG 900X3C/900X3D/900X3E/900X4C/900X4D */
 	 .matches = {
 		DMI_MATCH(DMI_SYS_VENDOR, "SAMSUNG ELECTRONICS CO., LTD."),
 		DMI_MATCH(DMI_PRODUCT_NAME,
@@ -258,7 +429,7 @@ static const struct dmi_system_id video_detect_dmi_table[] = {
 	{
 	 /* https://bugzilla.redhat.com/show_bug.cgi?id=1272633 */
 	 .callback = video_detect_force_video,
-	 .ident = "Dell XPS14 L421X",
+	 /* Dell XPS14 L421X */
 	 .matches = {
 		DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 		DMI_MATCH(DMI_PRODUCT_NAME, "XPS L421X"),
@@ -267,7 +438,7 @@ static const struct dmi_system_id video_detect_dmi_table[] = {
 	{
 	 /* https://bugzilla.redhat.com/show_bug.cgi?id=1163574 */
 	 .callback = video_detect_force_video,
-	 .ident = "Dell XPS15 L521X",
+	 /* Dell XPS15 L521X */
 	 .matches = {
 		DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 		DMI_MATCH(DMI_PRODUCT_NAME, "XPS L521X"),
@@ -276,35 +447,53 @@ static const struct dmi_system_id video_detect_dmi_table[] = {
 	{
 	 /* https://bugzilla.kernel.org/show_bug.cgi?id=108971 */
 	 .callback = video_detect_force_video,
-	 .ident = "SAMSUNG 530U4E/540U4E",
+	 /* SAMSUNG 530U4E/540U4E */
 	 .matches = {
 		DMI_MATCH(DMI_SYS_VENDOR, "SAMSUNG ELECTRONICS CO., LTD."),
 		DMI_MATCH(DMI_PRODUCT_NAME, "530U4E/540U4E"),
 		},
 	},
+	{
+	 /* https://bugs.launchpad.net/bugs/1894667 */
+	 .callback = video_detect_force_video,
+	 /* HP 635 Notebook */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
+		DMI_MATCH(DMI_PRODUCT_NAME, "HP 635 Notebook PC"),
+		},
+	},
 
 	/* Non win8 machines which need native backlight nevertheless */
 	{
 	 /* https://bugzilla.redhat.com/show_bug.cgi?id=1201530 */
 	 .callback = video_detect_force_native,
-	 .ident = "Lenovo Ideapad S405",
+	 /* Lenovo Ideapad S405 */
 	 .matches = {
 		DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
 		DMI_MATCH(DMI_BOARD_NAME, "Lenovo IdeaPad S405"),
 		},
 	},
 	{
+	 /* https://bugzilla.suse.com/show_bug.cgi?id=1208724 */
+	 .callback = video_detect_force_native,
+	 /* Lenovo Ideapad Z470 */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
+		DMI_MATCH(DMI_PRODUCT_VERSION, "IdeaPad Z470"),
+		},
+	},
+	{
 	 /* https://bugzilla.redhat.com/show_bug.cgi?id=1187004 */
 	 .callback = video_detect_force_native,
-	 .ident = "Lenovo Ideapad Z570",
+	 /* Lenovo Ideapad Z570 */
 	 .matches = {
 		DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
-		DMI_MATCH(DMI_PRODUCT_NAME, "102434U"),
+		DMI_MATCH(DMI_PRODUCT_VERSION, "Ideapad Z570"),
 		},
 	},
 	{
 	 .callback = video_detect_force_native,
-	 .ident = "Lenovo E41-25",
+	 /* Lenovo E41-25 */
 	 .matches = {
 		DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
 		DMI_MATCH(DMI_PRODUCT_NAME, "81FS"),
@@ -312,16 +501,90 @@ static const struct dmi_system_id video_detect_dmi_table[] = {
 	},
 	{
 	 .callback = video_detect_force_native,
-	 .ident = "Lenovo E41-45",
+	 /* Lenovo E41-45 */
 	 .matches = {
 		DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
 		DMI_MATCH(DMI_PRODUCT_NAME, "82BK"),
 		},
 	},
 	{
+	 .callback = video_detect_force_native,
+	 /* Lenovo Slim 7 16ARH7 */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
+		DMI_MATCH(DMI_PRODUCT_NAME, "82UX"),
+		},
+	},
+	{
+	 .callback = video_detect_force_native,
+	 /* Lenovo ThinkPad X131e (3371 AMD version) */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
+		DMI_MATCH(DMI_PRODUCT_NAME, "3371"),
+		},
+	},
+	{
+	 .callback = video_detect_force_native,
+	 /* Apple iMac11,3 */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
+		DMI_MATCH(DMI_PRODUCT_NAME, "iMac11,3"),
+		},
+	},
+	{
+	 /* https://gitlab.freedesktop.org/drm/amd/-/issues/1838 */
+	 .callback = video_detect_force_native,
+	 /* Apple iMac12,1 */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
+		DMI_MATCH(DMI_PRODUCT_NAME, "iMac12,1"),
+		},
+	},
+	{
+	 /* https://gitlab.freedesktop.org/drm/amd/-/issues/2753 */
+	 .callback = video_detect_force_native,
+	 /* Apple iMac12,2 */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
+		DMI_MATCH(DMI_PRODUCT_NAME, "iMac12,2"),
+		},
+	},
+	{
+	 .callback = video_detect_force_native,
+	 /* Apple MacBook Air 7,2 */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
+		DMI_MATCH(DMI_PRODUCT_NAME, "MacBookAir7,2"),
+		},
+	},
+	{
+	 .callback = video_detect_force_native,
+	 /* Apple MacBook Air 9,1 */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
+		DMI_MATCH(DMI_PRODUCT_NAME, "MacBookAir9,1"),
+		},
+	},
+	{
+	 .callback = video_detect_force_native,
+	 /* Apple MacBook Pro 9,2 */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
+		DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,2"),
+		},
+	},
+	{
+	 .callback = video_detect_force_native,
+	 /* Apple MacBook Pro 11,2 */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
+		DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro11,2"),
+		},
+	},
+	{
 	 /* https://bugzilla.redhat.com/show_bug.cgi?id=1217249 */
 	 .callback = video_detect_force_native,
-	 .ident = "Apple MacBook Pro 12,1",
+	 /* Apple MacBook Pro 12,1 */
 	 .matches = {
 		DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 		DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro12,1"),
@@ -329,7 +592,23 @@ static const struct dmi_system_id video_detect_dmi_table[] = {
 	},
 	{
 	 .callback = video_detect_force_native,
-	 .ident = "Dell Vostro V131",
+	 /* Apple MacBook Pro 16,2 */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
+		DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro16,2"),
+		},
+	},
+	{
+	 .callback = video_detect_force_native,
+	 /* Dell Inspiron N4010 */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
+		DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron N4010"),
+		},
+	},
+	{
+	 .callback = video_detect_force_native,
+	 /* Dell Vostro V131 */
 	 .matches = {
 		DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 		DMI_MATCH(DMI_PRODUCT_NAME, "Vostro V131"),
@@ -338,7 +617,7 @@ static const struct dmi_system_id video_detect_dmi_table[] = {
 	{
 	 /* https://bugzilla.redhat.com/show_bug.cgi?id=1123661 */
 	 .callback = video_detect_force_native,
-	 .ident = "Dell XPS 17 L702X",
+	 /* Dell XPS 17 L702X */
 	 .matches = {
 		DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 		DMI_MATCH(DMI_PRODUCT_NAME, "Dell System XPS L702X"),
@@ -346,7 +625,7 @@ static const struct dmi_system_id video_detect_dmi_table[] = {
 	},
 	{
 	 .callback = video_detect_force_native,
-	 .ident = "Dell Precision 7510",
+	 /* Dell Precision 7510 */
 	 .matches = {
 		DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 		DMI_MATCH(DMI_PRODUCT_NAME, "Precision 7510"),
@@ -354,74 +633,358 @@ static const struct dmi_system_id video_detect_dmi_table[] = {
 	},
 	{
 	 .callback = video_detect_force_native,
-	 .ident = "Acer Aspire 5738z",
+	 /* Dell Studio 1569 */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
+		DMI_MATCH(DMI_PRODUCT_NAME, "Studio 1569"),
+		},
+	},
+	{
+	 .callback = video_detect_force_native,
+	 /* Acer Aspire 3830TG */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
+		DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3830TG"),
+		},
+	},
+	{
+	 .callback = video_detect_force_native,
+	 /* Acer Aspire 4810T */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
+		DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 4810T"),
+		},
+	},
+	{
+	 .callback = video_detect_force_native,
+	 /* Acer Aspire 5738z */
 	 .matches = {
 		DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
 		DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 5738"),
 		DMI_MATCH(DMI_BOARD_NAME, "JV50"),
 		},
 	},
+	{
+	 /* https://bugzilla.redhat.com/show_bug.cgi?id=1012674 */
+	 .callback = video_detect_force_native,
+	 /* Acer Aspire 5741 */
+	 .matches = {
+		DMI_MATCH(DMI_BOARD_VENDOR, "Acer"),
+		DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 5741"),
+		},
+	},
+	{
+	 /* https://bugzilla.kernel.org/show_bug.cgi?id=42993 */
+	 .callback = video_detect_force_native,
+	 /* Acer Aspire 5750 */
+	 .matches = {
+		DMI_MATCH(DMI_BOARD_VENDOR, "Acer"),
+		DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 5750"),
+		},
+	},
+	{
+	 /* https://bugzilla.kernel.org/show_bug.cgi?id=42833 */
+	 .callback = video_detect_force_native,
+	 /* Acer Extensa 5235 */
+	 .matches = {
+		DMI_MATCH(DMI_BOARD_VENDOR, "Acer"),
+		DMI_MATCH(DMI_PRODUCT_NAME, "Extensa 5235"),
+		},
+	},
+	{
+	 .callback = video_detect_force_native,
+	 /* Acer TravelMate 4750 */
+	 .matches = {
+		DMI_MATCH(DMI_BOARD_VENDOR, "Acer"),
+		DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 4750"),
+		},
+	},
+	{
+	 /* https://bugzilla.kernel.org/show_bug.cgi?id=207835 */
+	 .callback = video_detect_force_native,
+	 /* Acer TravelMate 5735Z */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
+		DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 5735Z"),
+		DMI_MATCH(DMI_BOARD_NAME, "BA51_MV"),
+		},
+	},
+	{
+	 /* https://bugzilla.kernel.org/show_bug.cgi?id=36322 */
+	 .callback = video_detect_force_native,
+	 /* Acer TravelMate 5760 */
+	 .matches = {
+		DMI_MATCH(DMI_BOARD_VENDOR, "Acer"),
+		DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 5760"),
+		},
+	},
+	{
+	 .callback = video_detect_force_native,
+	 /* ASUSTeK COMPUTER INC. GA401 */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
+		DMI_MATCH(DMI_PRODUCT_NAME, "GA401"),
+		},
+	},
+	{
+	 .callback = video_detect_force_native,
+	 /* ASUSTeK COMPUTER INC. GA502 */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
+		DMI_MATCH(DMI_PRODUCT_NAME, "GA502"),
+		},
+	},
+	{
+	 .callback = video_detect_force_native,
+	 /* ASUSTeK COMPUTER INC. GA503 */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
+		DMI_MATCH(DMI_PRODUCT_NAME, "GA503"),
+		},
+	},
+	{
+	 .callback = video_detect_force_native,
+	 /* Asus U46E */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."),
+		DMI_MATCH(DMI_PRODUCT_NAME, "U46E"),
+		},
+	},
+	{
+	 .callback = video_detect_force_native,
+	 /* Asus UX303UB */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
+		DMI_MATCH(DMI_PRODUCT_NAME, "UX303UB"),
+		},
+	},
+	{
+	 .callback = video_detect_force_native,
+	 /* HP EliteBook 8460p */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
+		DMI_MATCH(DMI_PRODUCT_NAME, "HP EliteBook 8460p"),
+		},
+	},
+	{
+	 .callback = video_detect_force_native,
+	 /* HP Pavilion g6-1d80nr / B4U19UA */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
+		DMI_MATCH(DMI_PRODUCT_NAME, "HP Pavilion g6 Notebook PC"),
+		DMI_MATCH(DMI_PRODUCT_SKU, "B4U19UA"),
+		},
+	},
+	{
+	 .callback = video_detect_force_native,
+	 /* Samsung N150P */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "SAMSUNG ELECTRONICS CO., LTD."),
+		DMI_MATCH(DMI_PRODUCT_NAME, "N150P"),
+		DMI_MATCH(DMI_BOARD_NAME, "N150P"),
+		},
+	},
+	{
+	 .callback = video_detect_force_native,
+	 /* Samsung N145P/N250P/N260P */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "SAMSUNG ELECTRONICS CO., LTD."),
+		DMI_MATCH(DMI_PRODUCT_NAME, "N145P/N250P/N260P"),
+		DMI_MATCH(DMI_BOARD_NAME, "N145P/N250P/N260P"),
+		},
+	},
+	{
+	 .callback = video_detect_force_native,
+	 /* Samsung N250P */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "SAMSUNG ELECTRONICS CO., LTD."),
+		DMI_MATCH(DMI_PRODUCT_NAME, "N250P"),
+		DMI_MATCH(DMI_BOARD_NAME, "N250P"),
+		},
+	},
+	{
+	 /* https://bugzilla.kernel.org/show_bug.cgi?id=202401 */
+	 .callback = video_detect_force_native,
+	 /* Sony Vaio VPCEH3U1E */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"),
+		DMI_MATCH(DMI_PRODUCT_NAME, "VPCEH3U1E"),
+		},
+	},
+	{
+	 .callback = video_detect_force_native,
+	 /* Sony Vaio VPCY11S1E */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"),
+		DMI_MATCH(DMI_PRODUCT_NAME, "VPCY11S1E"),
+		},
+	},
+
+	/*
+	 * These Toshibas have a broken acpi-video interface for brightness
+	 * control. They also have an issue where the panel is off after
+	 * suspend until a special firmware call is made to turn it back
+	 * on. This is handled by the toshiba_acpi kernel module, so that
+	 * module must be enabled for these models to work correctly.
+	 */
+	{
+	 /* https://bugzilla.kernel.org/show_bug.cgi?id=21012 */
+	 .callback = video_detect_force_native,
+	 /* Toshiba Portégé R700 */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
+		DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE R700"),
+		},
+	},
+	{
+	 /* Portégé: https://bugs.freedesktop.org/show_bug.cgi?id=82634 */
+	 /* Satellite: https://bugzilla.kernel.org/show_bug.cgi?id=21012 */
+	 .callback = video_detect_force_native,
+	 /* Toshiba Satellite/Portégé R830 */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
+		DMI_MATCH(DMI_PRODUCT_NAME, "R830"),
+		},
+	},
+	{
+	 .callback = video_detect_force_native,
+	 /* Toshiba Satellite/Portégé Z830 */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
+		DMI_MATCH(DMI_PRODUCT_NAME, "Z830"),
+		},
+	},
 
 	/*
-	 * Desktops which falsely report a backlight and which our heuristics
-	 * for this do not catch.
+	 * Dell AIO (All in Ones) which advertise an UART attached backlight
+	 * controller board in their ACPI tables (and may even have one), but
+	 * which need native backlight control nevertheless.
 	 */
 	{
-	 .callback = video_detect_force_none,
-	 .ident = "Dell OptiPlex 9020M",
+	 /* https://github.com/zabbly/linux/issues/26 */
+	 .callback = video_detect_force_native,
+	 /* Dell OptiPlex 5480 AIO */
 	 .matches = {
 		DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
-		DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex 9020M"),
+		DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex 5480 AIO"),
 		},
 	},
 	{
-	 .callback = video_detect_force_none,
-	 .ident = "MSI MS-7721",
+	 /* https://bugzilla.redhat.com/show_bug.cgi?id=2303936 */
+	 .callback = video_detect_force_native,
+	 /* Dell OptiPlex 7760 AIO */
 	 .matches = {
-		DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
-		DMI_MATCH(DMI_PRODUCT_NAME, "MS-7721"),
+		DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
+		DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex 7760 AIO"),
+		},
+	},
+
+	/*
+	 * Models which have nvidia-ec-wmi support, but should not use it.
+	 * Note this indicates a likely firmware bug on these models and should
+	 * be revisited if/when Linux gets support for dynamic mux mode.
+	 */
+	{
+	 .callback = video_detect_force_native,
+	 /* Dell G15 5515 */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
+		DMI_MATCH(DMI_PRODUCT_NAME, "Dell G15 5515"),
+		},
+	},
+	{
+	 .callback = video_detect_force_native,
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
+		DMI_MATCH(DMI_PRODUCT_NAME, "Vostro 15 3535"),
+		},
+	},
+
+	/*
+	 * x86 android tablets which directly control the backlight through
+	 * an external backlight controller, typically TI's LP8557.
+	 * The backlight is directly controlled by the lp855x driver on these.
+	 * This setup means that neither i915's native nor acpi_video backlight
+	 * control works. Add a "vendor" quirk to disable both. Note these
+	 * devices do not use vendor control in the typical meaning of
+	 * vendor specific SMBIOS or ACPI calls being used.
+	 */
+	{
+	 .callback = video_detect_force_vendor,
+	 /* Lenovo Yoga Book X90F / X90L */
+	 .matches = {
+		DMI_EXACT_MATCH(DMI_SYS_VENDOR, "Intel Corporation"),
+		DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "CHERRYVIEW D1 PLATFORM"),
+		DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "YETI-11"),
+		},
+	},
+	{
+	 .callback = video_detect_force_vendor,
+	 /*
+	  * Lenovo Yoga Tablet 2 830F/L or 1050F/L (The 8" and 10"
+	  * Lenovo Yoga Tablet 2 use the same mainboard)
+	  */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "Intel Corp."),
+		DMI_MATCH(DMI_PRODUCT_NAME, "VALLEYVIEW C0 PLATFORM"),
+		DMI_MATCH(DMI_BOARD_NAME, "BYT-T FFD8"),
+		/* Partial match on beginning of BIOS version */
+		DMI_MATCH(DMI_BIOS_VERSION, "BLADE_21"),
+		},
+	},
+	{
+	 .callback = video_detect_force_vendor,
+	 /* Lenovo Yoga Tab 3 Pro YT3-X90F */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "Intel Corporation"),
+		DMI_MATCH(DMI_PRODUCT_VERSION, "Blade3-10A-001"),
+		},
+	},
+	{
+	 .callback = video_detect_force_vendor,
+	 /* Xiaomi Mi Pad 2 */
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "Xiaomi Inc"),
+		DMI_MATCH(DMI_PRODUCT_NAME, "Mipad2"),
+		},
+	},
+	/* https://gitlab.freedesktop.org/drm/amd/-/issues/4512 */
+	{
+	 .callback = video_detect_force_native,
+	 .matches = {
+		DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
+		DMI_MATCH(DMI_PRODUCT_NAME, "82K8"),
 		},
 	},
 	{ },
 };
 
-/* This uses a workqueue to avoid various locking ordering issues */
-static void acpi_video_backlight_notify_work(struct work_struct *work)
+static bool google_cros_ec_present(void)
 {
-	if (acpi_video_get_backlight_type() != acpi_backlight_video)
-		acpi_video_unregister_backlight();
+	return acpi_dev_found("GOOG0004") || acpi_dev_found("GOOG000C");
 }
 
-static int acpi_video_backlight_notify(struct notifier_block *nb,
-				       unsigned long val, void *bd)
+/*
+ * Windows 8 and newer no longer use the ACPI video interface, so it often
+ * does not work. So on win8+ systems prefer native brightness control.
+ * Chromebooks should always prefer native backlight control.
+ */
+static bool prefer_native_over_acpi_video(void)
 {
-	struct backlight_device *backlight = bd;
-
-	/* A raw bl registering may change video -> native */
-	if (backlight->props.type == BACKLIGHT_RAW &&
-	    val == BACKLIGHT_REGISTERED)
-		schedule_work(&backlight_notify_work);
-
-	return NOTIFY_OK;
+	return acpi_osi_is_win8() || google_cros_ec_present();
 }
 
 /*
  * Determine which type of backlight interface to use on this system,
  * First check cmdline, then dmi quirks, then do autodetect.
- *
- * The autodetect order is:
- * 1) Is the acpi-video backlight interface supported ->
- *  no, use a vendor interface
- * 2) Is this a win8 "ready" BIOS and do we have a native interface ->
- *  yes, use a native interface
- * 3) Else use the acpi-video interface
- *
- * Arguably the native on win8 check should be done first, but that would
- * be a behavior change, which may causes issues.
  */
-enum acpi_backlight_type acpi_video_get_backlight_type(void)
+enum acpi_backlight_type __acpi_video_get_backlight_type(bool native, bool *auto_detect)
 {
 	static DEFINE_MUTEX(init_mutex);
+	static bool nvidia_wmi_ec_present;
+	static bool apple_gmux_present;
+	static bool dell_uart_present;
+	static bool native_available;
 	static bool init_done;
 	static long video_caps;
 
@@ -433,48 +996,73 @@ enum acpi_backlight_type acpi_video_get_backlight_type(void)
 		acpi_walk_namespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT,
 				    ACPI_UINT32_MAX, find_video, NULL,
 				    &video_caps, NULL);
-		INIT_WORK(&backlight_notify_work,
-			  acpi_video_backlight_notify_work);
-		backlight_nb.notifier_call = acpi_video_backlight_notify;
-		backlight_nb.priority = 0;
-		if (backlight_register_notifier(&backlight_nb) == 0)
-			backlight_notifier_registered = true;
+		nvidia_wmi_ec_present = nvidia_wmi_ec_supported();
+		apple_gmux_present = apple_gmux_detect(NULL, NULL);
+		dell_uart_present = acpi_dev_present("DELL0501", NULL, -1);
 		init_done = true;
 	}
+	if (native)
+		native_available = true;
 	mutex_unlock(&init_mutex);
 
+	if (auto_detect)
+		*auto_detect = false;
+
+	/*
+	 * The below heuristics / detection steps are in order of descending
+	 * presedence. The commandline takes presedence over anything else.
+	 */
 	if (acpi_backlight_cmdline != acpi_backlight_undef)
 		return acpi_backlight_cmdline;
 
+	/* DMI quirks override any autodetection. */
 	if (acpi_backlight_dmi != acpi_backlight_undef)
 		return acpi_backlight_dmi;
 
-	if (!(video_caps & ACPI_VIDEO_BACKLIGHT))
-		return acpi_backlight_vendor;
+	if (auto_detect)
+		*auto_detect = true;
 
-	if (acpi_osi_is_win8() && backlight_device_get_by_type(BACKLIGHT_RAW))
-		return acpi_backlight_native;
+	/* Special cases such as nvidia_wmi_ec and apple gmux. */
+	if (nvidia_wmi_ec_present)
+		return acpi_backlight_nvidia_wmi_ec;
 
-	return acpi_backlight_video;
-}
-EXPORT_SYMBOL(acpi_video_get_backlight_type);
+	if (apple_gmux_present)
+		return acpi_backlight_apple_gmux;
 
-/*
- * Set the preferred backlight interface type based on DMI info.
- * This function allows DMI blacklists to be implemented by external
- * platform drivers instead of putting a big blacklist in video_detect.c
- */
-void acpi_video_set_dmi_backlight_type(enum acpi_backlight_type type)
-{
-	acpi_backlight_dmi = type;
-	/* Remove acpi-video backlight interface if it is no longer desired */
-	if (acpi_video_get_backlight_type() != acpi_backlight_video)
-		acpi_video_unregister_backlight();
-}
-EXPORT_SYMBOL(acpi_video_set_dmi_backlight_type);
+	if (dell_uart_present)
+		return acpi_backlight_dell_uart;
 
-void __exit acpi_video_detect_exit(void)
-{
-	if (backlight_notifier_registered)
-		backlight_unregister_notifier(&backlight_nb);
+	/* Use ACPI video if available, except when native should be preferred. */
+	if ((video_caps & ACPI_VIDEO_BACKLIGHT) &&
+	     !(native_available && prefer_native_over_acpi_video()))
+		return acpi_backlight_video;
+
+	/* Use native if available */
+	if (native_available)
+		return acpi_backlight_native;
+
+	/*
+	 * The vendor specific BIOS interfaces are only necessary for
+	 * laptops from before ~2008.
+	 *
+	 * For laptops from ~2008 till ~2023 this point is never reached
+	 * because on those (video_caps & ACPI_VIDEO_BACKLIGHT) above is true.
+	 *
+	 * Laptops from after ~2023 no longer support ACPI_VIDEO_BACKLIGHT,
+	 * if this point is reached on those, this likely means that
+	 * the GPU kms driver which sets native_available has not loaded yet.
+	 *
+	 * Returning acpi_backlight_vendor in this case is known to sometimes
+	 * cause a non working vendor specific /sys/class/backlight device to
+	 * get registered.
+	 *
+	 * Return acpi_backlight_none on laptops with ACPI tables written
+	 * for Windows 8 (laptops from after ~2012) to avoid this problem.
+	 */
+	if (acpi_osi_is_win8())
+		return acpi_backlight_none;
+
+	/* No ACPI video/native (old hw), use vendor specific fw methods. */
+	return acpi_backlight_vendor;
 }
+EXPORT_SYMBOL(__acpi_video_get_backlight_type);
diff --git a/drivers/acpi/viot.c b/drivers/acpi/viot.c
new file mode 100644
index 000000000000..c13a20365c2c
--- /dev/null
+++ b/drivers/acpi/viot.c
@@ -0,0 +1,373 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Virtual I/O topology
+ *
+ * The Virtual I/O Translation Table (VIOT) describes the topology of
+ * para-virtual IOMMUs and the endpoints they manage. The OS uses it to
+ * initialize devices in the right order, preventing endpoints from issuing DMA
+ * before their IOMMU is ready.
+ *
+ * When binding a driver to a device, before calling the device driver's probe()
+ * method, the driver infrastructure calls dma_configure(). At that point the
+ * VIOT driver looks for an IOMMU associated to the device in the VIOT table.
+ * If an IOMMU exists and has been initialized, the VIOT driver initializes the
+ * device's IOMMU fwspec, allowing the DMA infrastructure to invoke the IOMMU
+ * ops when the device driver configures DMA mappings. If an IOMMU exists and
+ * hasn't yet been initialized, VIOT returns -EPROBE_DEFER to postpone probing
+ * the device until the IOMMU is available.
+ */
+#define pr_fmt(fmt) "ACPI: VIOT: " fmt
+
+#include <linux/acpi_viot.h>
+#include <linux/iommu.h>
+#include <linux/list.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
+
+struct viot_iommu {
+	/* Node offset within the table */
+	unsigned int			offset;
+	struct fwnode_handle		*fwnode;
+	struct list_head		list;
+};
+
+struct viot_endpoint {
+	union {
+		/* PCI range */
+		struct {
+			u16		segment_start;
+			u16		segment_end;
+			u16		bdf_start;
+			u16		bdf_end;
+		};
+		/* MMIO */
+		u64			address;
+	};
+	u32				endpoint_id;
+	struct viot_iommu		*viommu;
+	struct list_head		list;
+};
+
+static struct acpi_table_viot *viot;
+static LIST_HEAD(viot_iommus);
+static LIST_HEAD(viot_pci_ranges);
+static LIST_HEAD(viot_mmio_endpoints);
+
+static int __init viot_check_bounds(const struct acpi_viot_header *hdr)
+{
+	struct acpi_viot_header *start, *end, *hdr_end;
+
+	start = ACPI_ADD_PTR(struct acpi_viot_header, viot,
+			     max_t(size_t, sizeof(*viot), viot->node_offset));
+	end = ACPI_ADD_PTR(struct acpi_viot_header, viot, viot->header.length);
+	hdr_end = ACPI_ADD_PTR(struct acpi_viot_header, hdr, sizeof(*hdr));
+
+	if (hdr < start || hdr_end > end) {
+		pr_err(FW_BUG "Node pointer overflows\n");
+		return -EOVERFLOW;
+	}
+	if (hdr->length < sizeof(*hdr)) {
+		pr_err(FW_BUG "Empty node\n");
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static int __init viot_get_pci_iommu_fwnode(struct viot_iommu *viommu,
+					    u16 segment, u16 bdf)
+{
+	struct pci_dev *pdev;
+	struct fwnode_handle *fwnode;
+
+	pdev = pci_get_domain_bus_and_slot(segment, PCI_BUS_NUM(bdf),
+					   bdf & 0xff);
+	if (!pdev) {
+		pr_err("Could not find PCI IOMMU\n");
+		return -ENODEV;
+	}
+
+	fwnode = dev_fwnode(&pdev->dev);
+	if (!fwnode) {
+		/*
+		 * PCI devices aren't necessarily described by ACPI. Create a
+		 * fwnode so the IOMMU subsystem can identify this device.
+		 */
+		fwnode = acpi_alloc_fwnode_static();
+		if (!fwnode) {
+			pci_dev_put(pdev);
+			return -ENOMEM;
+		}
+		set_primary_fwnode(&pdev->dev, fwnode);
+	}
+	viommu->fwnode = dev_fwnode(&pdev->dev);
+	pci_dev_put(pdev);
+	return 0;
+}
+
+static int __init viot_get_mmio_iommu_fwnode(struct viot_iommu *viommu,
+					     u64 address)
+{
+	struct acpi_device *adev;
+	struct resource res = {
+		.start	= address,
+		.end	= address,
+		.flags	= IORESOURCE_MEM,
+	};
+
+	adev = acpi_resource_consumer(&res);
+	if (!adev) {
+		pr_err("Could not find MMIO IOMMU\n");
+		return -EINVAL;
+	}
+	viommu->fwnode = &adev->fwnode;
+	return 0;
+}
+
+static struct viot_iommu * __init viot_get_iommu(unsigned int offset)
+{
+	int ret;
+	struct viot_iommu *viommu;
+	struct acpi_viot_header *hdr = ACPI_ADD_PTR(struct acpi_viot_header,
+						    viot, offset);
+	union {
+		struct acpi_viot_virtio_iommu_pci pci;
+		struct acpi_viot_virtio_iommu_mmio mmio;
+	} *node = (void *)hdr;
+
+	list_for_each_entry(viommu, &viot_iommus, list)
+		if (viommu->offset == offset)
+			return viommu;
+
+	if (viot_check_bounds(hdr))
+		return NULL;
+
+	viommu = kzalloc(sizeof(*viommu), GFP_KERNEL);
+	if (!viommu)
+		return NULL;
+
+	viommu->offset = offset;
+	switch (hdr->type) {
+	case ACPI_VIOT_NODE_VIRTIO_IOMMU_PCI:
+		if (hdr->length < sizeof(node->pci))
+			goto err_free;
+
+		ret = viot_get_pci_iommu_fwnode(viommu, node->pci.segment,
+						node->pci.bdf);
+		break;
+	case ACPI_VIOT_NODE_VIRTIO_IOMMU_MMIO:
+		if (hdr->length < sizeof(node->mmio))
+			goto err_free;
+
+		ret = viot_get_mmio_iommu_fwnode(viommu,
+						 node->mmio.base_address);
+		break;
+	default:
+		ret = -EINVAL;
+	}
+	if (ret)
+		goto err_free;
+
+	list_add(&viommu->list, &viot_iommus);
+	return viommu;
+
+err_free:
+	kfree(viommu);
+	return NULL;
+}
+
+static int __init viot_parse_node(const struct acpi_viot_header *hdr)
+{
+	int ret = -EINVAL;
+	struct list_head *list;
+	struct viot_endpoint *ep;
+	union {
+		struct acpi_viot_mmio mmio;
+		struct acpi_viot_pci_range pci;
+	} *node = (void *)hdr;
+
+	if (viot_check_bounds(hdr))
+		return -EINVAL;
+
+	if (hdr->type == ACPI_VIOT_NODE_VIRTIO_IOMMU_PCI ||
+	    hdr->type == ACPI_VIOT_NODE_VIRTIO_IOMMU_MMIO)
+		return 0;
+
+	ep = kzalloc(sizeof(*ep), GFP_KERNEL);
+	if (!ep)
+		return -ENOMEM;
+
+	switch (hdr->type) {
+	case ACPI_VIOT_NODE_PCI_RANGE:
+		if (hdr->length < sizeof(node->pci)) {
+			pr_err(FW_BUG "Invalid PCI node size\n");
+			goto err_free;
+		}
+
+		ep->segment_start = node->pci.segment_start;
+		ep->segment_end = node->pci.segment_end;
+		ep->bdf_start = node->pci.bdf_start;
+		ep->bdf_end = node->pci.bdf_end;
+		ep->endpoint_id = node->pci.endpoint_start;
+		ep->viommu = viot_get_iommu(node->pci.output_node);
+		list = &viot_pci_ranges;
+		break;
+	case ACPI_VIOT_NODE_MMIO:
+		if (hdr->length < sizeof(node->mmio)) {
+			pr_err(FW_BUG "Invalid MMIO node size\n");
+			goto err_free;
+		}
+
+		ep->address = node->mmio.base_address;
+		ep->endpoint_id = node->mmio.endpoint;
+		ep->viommu = viot_get_iommu(node->mmio.output_node);
+		list = &viot_mmio_endpoints;
+		break;
+	default:
+		pr_warn("Unsupported node %x\n", hdr->type);
+		ret = 0;
+		goto err_free;
+	}
+
+	if (!ep->viommu) {
+		pr_warn("No IOMMU node found\n");
+		/*
+		 * A future version of the table may use the node for other
+		 * purposes. Keep parsing.
+		 */
+		ret = 0;
+		goto err_free;
+	}
+
+	list_add(&ep->list, list);
+	return 0;
+
+err_free:
+	kfree(ep);
+	return ret;
+}
+
+/**
+ * acpi_viot_early_init - Test the presence of VIOT and enable ACS
+ *
+ * If the VIOT does exist, ACS must be enabled. This cannot be
+ * done in acpi_viot_init() which is called after the bus scan
+ */
+void __init acpi_viot_early_init(void)
+{
+#ifdef CONFIG_PCI
+	acpi_status status;
+	struct acpi_table_header *hdr;
+
+	status = acpi_get_table(ACPI_SIG_VIOT, 0, &hdr);
+	if (ACPI_FAILURE(status))
+		return;
+	pci_request_acs();
+	acpi_put_table(hdr);
+#endif
+}
+
+/**
+ * acpi_viot_init - Parse the VIOT table
+ *
+ * Parse the VIOT table, prepare the list of endpoints to be used during DMA
+ * setup of devices.
+ */
+void __init acpi_viot_init(void)
+{
+	int i;
+	acpi_status status;
+	struct acpi_table_header *hdr;
+	struct acpi_viot_header *node;
+
+	status = acpi_get_table(ACPI_SIG_VIOT, 0, &hdr);
+	if (ACPI_FAILURE(status)) {
+		if (status != AE_NOT_FOUND) {
+			const char *msg = acpi_format_exception(status);
+
+			pr_err("Failed to get table, %s\n", msg);
+		}
+		return;
+	}
+
+	viot = (void *)hdr;
+
+	node = ACPI_ADD_PTR(struct acpi_viot_header, viot, viot->node_offset);
+	for (i = 0; i < viot->node_count; i++) {
+		if (viot_parse_node(node))
+			return;
+
+		node = ACPI_ADD_PTR(struct acpi_viot_header, node,
+				    node->length);
+	}
+
+	acpi_put_table(hdr);
+}
+
+static int viot_dev_iommu_init(struct device *dev, struct viot_iommu *viommu,
+			       u32 epid)
+{
+	if (!viommu || !IS_ENABLED(CONFIG_VIRTIO_IOMMU))
+		return -ENODEV;
+
+	/* We're not translating ourself */
+	if (device_match_fwnode(dev, viommu->fwnode))
+		return -EINVAL;
+
+	return acpi_iommu_fwspec_init(dev, epid, viommu->fwnode);
+}
+
+static int viot_pci_dev_iommu_init(struct pci_dev *pdev, u16 dev_id, void *data)
+{
+	u32 epid;
+	struct viot_endpoint *ep;
+	struct device *aliased_dev = data;
+	u32 domain_nr = pci_domain_nr(pdev->bus);
+
+	list_for_each_entry(ep, &viot_pci_ranges, list) {
+		if (domain_nr >= ep->segment_start &&
+		    domain_nr <= ep->segment_end &&
+		    dev_id >= ep->bdf_start &&
+		    dev_id <= ep->bdf_end) {
+			epid = ((domain_nr - ep->segment_start) << 16) +
+				dev_id - ep->bdf_start + ep->endpoint_id;
+
+			return viot_dev_iommu_init(aliased_dev, ep->viommu,
+						   epid);
+		}
+	}
+	return -ENODEV;
+}
+
+static int viot_mmio_dev_iommu_init(struct platform_device *pdev)
+{
+	struct resource *mem;
+	struct viot_endpoint *ep;
+
+	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!mem)
+		return -ENODEV;
+
+	list_for_each_entry(ep, &viot_mmio_endpoints, list) {
+		if (ep->address == mem->start)
+			return viot_dev_iommu_init(&pdev->dev, ep->viommu,
+						   ep->endpoint_id);
+	}
+	return -ENODEV;
+}
+
+/**
+ * viot_iommu_configure - Setup IOMMU ops for an endpoint described by VIOT
+ * @dev: the endpoint
+ *
+ * Return: 0 on success, <0 on failure
+ */
+int viot_iommu_configure(struct device *dev)
+{
+	if (dev_is_pci(dev))
+		return pci_for_each_dma_alias(to_pci_dev(dev),
+					      viot_pci_dev_iommu_init, dev);
+	else if (dev_is_platform(dev))
+		return viot_mmio_dev_iommu_init(to_platform_device(dev));
+	return -ENODEV;
+}
diff --git a/drivers/acpi/wakeup.c b/drivers/acpi/wakeup.c
index 0b2e42530adf..ff6dc957bc11 100644
--- a/drivers/acpi/wakeup.c
+++ b/drivers/acpi/wakeup.c
@@ -26,8 +26,6 @@ static DEFINE_MUTEX(acpi_wakeup_handler_mutex);
  * suspend/resume and isn't really required as this is called in S-state. At
  * that time, there is no device hotplug
  **/
-#define _COMPONENT		ACPI_SYSTEM_COMPONENT
-ACPI_MODULE_NAME("wakeup_devices")
 
 /**
  * acpi_enable_wakeup_devices - Enable wake-up device GPEs.
@@ -44,9 +42,9 @@ void acpi_enable_wakeup_devices(u8 sleep_state)
 	list_for_each_entry_safe(dev, tmp, &acpi_wakeup_device_list,
 				 wakeup_list) {
 		if (!dev->wakeup.flags.valid
-		    || sleep_state > (u32) dev->wakeup.sleep_state
+		    || sleep_state > dev->wakeup.sleep_state
 		    || !(device_may_wakeup(&dev->dev)
-		        || dev->wakeup.prepare_count))
+			 || dev->wakeup.prepare_count))
 			continue;
 
 		if (device_may_wakeup(&dev->dev))
@@ -69,9 +67,9 @@ void acpi_disable_wakeup_devices(u8 sleep_state)
 	list_for_each_entry_safe(dev, tmp, &acpi_wakeup_device_list,
 				 wakeup_list) {
 		if (!dev->wakeup.flags.valid
-		    || sleep_state > (u32) dev->wakeup.sleep_state
+		    || sleep_state > dev->wakeup.sleep_state
 		    || !(device_may_wakeup(&dev->dev)
-		        || dev->wakeup.prepare_count))
+			 || dev->wakeup.prepare_count))
 			continue;
 
 		acpi_set_gpe_wake_mask(dev->wakeup.gpe_device, dev->wakeup.gpe_number,
diff --git a/drivers/acpi/x86/Makefile b/drivers/acpi/x86/Makefile
new file mode 100644
index 000000000000..63c99509ed9d
--- /dev/null
+++ b/drivers/acpi/x86/Makefile
@@ -0,0 +1,8 @@
+obj-$(CONFIG_ACPI)	+= acpi-x86.o
+acpi-x86-y		+= apple.o
+acpi-x86-y		+= cmos_rtc.o
+acpi-x86-$(CONFIG_PCI)	+= lpss.o
+acpi-x86-y		+= s2idle.o
+acpi-x86-y		+= utils.o
+
+obj-$(CONFIG_X86)	+= blacklist.o
diff --git a/drivers/acpi/x86/apple.c b/drivers/acpi/x86/apple.c
index c285c91a5e9c..45d0f16f374f 100644
--- a/drivers/acpi/x86/apple.c
+++ b/drivers/acpi/x86/apple.c
@@ -8,6 +8,7 @@
 #include <linux/bitmap.h>
 #include <linux/platform_data/x86/apple.h>
 #include <linux/uuid.h>
+#include "../internal.h"
 
 /* Apple _DSM device properties GUID */
 static const guid_t apple_prp_guid =
@@ -70,13 +71,16 @@ void acpi_extract_apple_properties(struct acpi_device *adev)
 
 		if ( key->type != ACPI_TYPE_STRING ||
 		    (val->type != ACPI_TYPE_INTEGER &&
-		     val->type != ACPI_TYPE_BUFFER))
+		     val->type != ACPI_TYPE_BUFFER &&
+		     val->type != ACPI_TYPE_STRING))
 			continue; /* skip invalid properties */
 
 		__set_bit(i, valid);
 		newsize += key->string.length + 1;
 		if ( val->type == ACPI_TYPE_BUFFER)
 			newsize += val->buffer.length;
+		else if (val->type == ACPI_TYPE_STRING)
+			newsize += val->string.length + 1;
 	}
 
 	numvalid = bitmap_weight(valid, numprops);
@@ -118,6 +122,12 @@ void acpi_extract_apple_properties(struct acpi_device *adev)
 		newprops[v].type = val->type;
 		if (val->type == ACPI_TYPE_INTEGER) {
 			newprops[v].integer.value = val->integer.value;
+		} else if (val->type == ACPI_TYPE_STRING) {
+			newprops[v].string.length = val->string.length;
+			newprops[v].string.pointer = free_space;
+			memcpy(free_space, val->string.pointer,
+			       val->string.length);
+			free_space += val->string.length + 1;
 		} else {
 			newprops[v].buffer.length = val->buffer.length;
 			newprops[v].buffer.pointer = free_space;
diff --git a/drivers/acpi/blacklist.c b/drivers/acpi/x86/blacklist.c
index a86a770c9b79..55214d0a12b1 100644
--- a/drivers/acpi/blacklist.c
+++ b/drivers/acpi/x86/blacklist.c
@@ -10,12 +10,14 @@
  *  Copyright (C) 2002 Andy Grover <andrew.grover@intel.com>
  */
 
+#define pr_fmt(fmt) "ACPI: " fmt
+
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/acpi.h>
 #include <linux/dmi.h>
 
-#include "internal.h"
+#include "../internal.h"
 
 #ifdef CONFIG_DMI
 static const struct dmi_system_id acpi_rev_dmi_table[] __initconst;
@@ -49,12 +51,12 @@ int __init acpi_blacklisted(void)
 
 	i = acpi_match_platform_list(acpi_blacklist);
 	if (i >= 0) {
-		pr_err(PREFIX "Vendor \"%6.6s\" System \"%8.8s\" Revision 0x%x has a known ACPI BIOS problem.\n",
+		pr_err("Vendor \"%6.6s\" System \"%8.8s\" Revision 0x%x has a known ACPI BIOS problem.\n",
 		       acpi_blacklist[i].oem_id,
 		       acpi_blacklist[i].oem_table_id,
 		       acpi_blacklist[i].oem_revision);
 
-		pr_err(PREFIX "Reason: %s. This is a %s error\n",
+		pr_err("Reason: %s. This is a %s error\n",
 		       acpi_blacklist[i].reason,
 		       (acpi_blacklist[i].data ?
 			"non-recoverable" : "recoverable"));
@@ -73,8 +75,7 @@ int __init acpi_blacklisted(void)
 #ifdef CONFIG_ACPI_REV_OVERRIDE_POSSIBLE
 static int __init dmi_enable_rev_override(const struct dmi_system_id *d)
 {
-	printk(KERN_NOTICE PREFIX "DMI detected: %s (force ACPI _REV to 5)\n",
-	       d->ident);
+	pr_notice("DMI detected: %s (force ACPI _REV to 5)\n", d->ident);
 	acpi_rev_override_setup(NULL);
 	return 0;
 }
diff --git a/drivers/acpi/x86/cmos_rtc.c b/drivers/acpi/x86/cmos_rtc.c
new file mode 100644
index 000000000000..51643ff6fe5f
--- /dev/null
+++ b/drivers/acpi/x86/cmos_rtc.c
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * ACPI support for CMOS RTC Address Space access
+ *
+ * Copyright (C) 2013, Intel Corporation
+ * Authors: Lan Tianyu <tianyu.lan@intel.com>
+ */
+
+#define pr_fmt(fmt) "ACPI: " fmt
+
+#include <linux/acpi.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mc146818rtc.h>
+
+#include "../internal.h"
+
+static const struct acpi_device_id acpi_cmos_rtc_ids[] = {
+	{ "PNP0B00" },
+	{ "PNP0B01" },
+	{ "PNP0B02" },
+	{}
+};
+
+static acpi_status
+acpi_cmos_rtc_space_handler(u32 function, acpi_physical_address address,
+		      u32 bits, u64 *value64,
+		      void *handler_context, void *region_context)
+{
+	int i;
+	u8 *value = (u8 *)value64;
+
+	if (address > 0xff || !value64)
+		return AE_BAD_PARAMETER;
+
+	if (function != ACPI_WRITE && function != ACPI_READ)
+		return AE_BAD_PARAMETER;
+
+	spin_lock_irq(&rtc_lock);
+
+	for (i = 0; i < DIV_ROUND_UP(bits, 8); ++i, ++address, ++value)
+		if (function == ACPI_READ)
+			*value = CMOS_READ(address);
+		else
+			CMOS_WRITE(*value, address);
+
+	spin_unlock_irq(&rtc_lock);
+
+	return AE_OK;
+}
+
+int acpi_install_cmos_rtc_space_handler(acpi_handle handle)
+{
+	acpi_status status;
+
+	status = acpi_install_address_space_handler(handle,
+			ACPI_ADR_SPACE_CMOS,
+			&acpi_cmos_rtc_space_handler,
+			NULL, NULL);
+	if (ACPI_FAILURE(status)) {
+		pr_err("Error installing CMOS-RTC region handler\n");
+		return -ENODEV;
+	}
+
+	return 1;
+}
+EXPORT_SYMBOL_GPL(acpi_install_cmos_rtc_space_handler);
+
+void acpi_remove_cmos_rtc_space_handler(acpi_handle handle)
+{
+	if (ACPI_FAILURE(acpi_remove_address_space_handler(handle,
+			ACPI_ADR_SPACE_CMOS, &acpi_cmos_rtc_space_handler)))
+		pr_err("Error removing CMOS-RTC region handler\n");
+}
+EXPORT_SYMBOL_GPL(acpi_remove_cmos_rtc_space_handler);
+
+static int acpi_cmos_rtc_attach_handler(struct acpi_device *adev, const struct acpi_device_id *id)
+{
+	return acpi_install_cmos_rtc_space_handler(adev->handle);
+}
+
+static void acpi_cmos_rtc_detach_handler(struct acpi_device *adev)
+{
+	acpi_remove_cmos_rtc_space_handler(adev->handle);
+}
+
+static struct acpi_scan_handler cmos_rtc_handler = {
+	.ids = acpi_cmos_rtc_ids,
+	.attach = acpi_cmos_rtc_attach_handler,
+	.detach = acpi_cmos_rtc_detach_handler,
+};
+
+void __init acpi_cmos_rtc_init(void)
+{
+	acpi_scan_add_handler(&cmos_rtc_handler);
+}
diff --git a/drivers/acpi/x86/lpss.c b/drivers/acpi/x86/lpss.c
new file mode 100644
index 000000000000..1dcb80ab0d23
--- /dev/null
+++ b/drivers/acpi/x86/lpss.c
@@ -0,0 +1,1352 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * ACPI support for Intel Lynxpoint LPSS.
+ *
+ * Copyright (C) 2013, Intel Corporation
+ * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
+ *          Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+ */
+
+#include <linux/acpi.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/dmi.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/mutex.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+#include <linux/platform_data/x86/clk-lpss.h>
+#include <linux/platform_data/x86/pmc_atom.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_runtime.h>
+#include <linux/pwm.h>
+#include <linux/pxa2xx_ssp.h>
+#include <linux/suspend.h>
+#include <linux/delay.h>
+
+#include "../internal.h"
+
+#ifdef CONFIG_X86_INTEL_LPSS
+
+#include <asm/cpu_device_id.h>
+#include <asm/intel-family.h>
+#include <asm/iosf_mbi.h>
+
+#define LPSS_ADDR(desc) ((unsigned long)&desc)
+
+#define LPSS_CLK_SIZE	0x04
+#define LPSS_LTR_SIZE	0x18
+
+/* Offsets relative to LPSS_PRIVATE_OFFSET */
+#define LPSS_CLK_DIVIDER_DEF_MASK	(BIT(1) | BIT(16))
+#define LPSS_RESETS			0x04
+#define LPSS_RESETS_RESET_FUNC		BIT(0)
+#define LPSS_RESETS_RESET_APB		BIT(1)
+#define LPSS_GENERAL			0x08
+#define LPSS_GENERAL_LTR_MODE_SW	BIT(2)
+#define LPSS_GENERAL_UART_RTS_OVRD	BIT(3)
+#define LPSS_SW_LTR			0x10
+#define LPSS_AUTO_LTR			0x14
+#define LPSS_LTR_SNOOP_REQ		BIT(15)
+#define LPSS_LTR_SNOOP_MASK		0x0000FFFF
+#define LPSS_LTR_SNOOP_LAT_1US		0x800
+#define LPSS_LTR_SNOOP_LAT_32US		0xC00
+#define LPSS_LTR_SNOOP_LAT_SHIFT	5
+#define LPSS_LTR_SNOOP_LAT_CUTOFF	3000
+#define LPSS_LTR_MAX_VAL		0x3FF
+#define LPSS_TX_INT			0x20
+#define LPSS_TX_INT_MASK		BIT(1)
+
+#define LPSS_PRV_REG_COUNT		9
+
+/* LPSS Flags */
+#define LPSS_CLK			BIT(0)
+#define LPSS_CLK_GATE			BIT(1)
+#define LPSS_CLK_DIVIDER		BIT(2)
+#define LPSS_LTR			BIT(3)
+#define LPSS_SAVE_CTX			BIT(4)
+/*
+ * For some devices the DSDT AML code for another device turns off the device
+ * before our suspend handler runs, causing us to read/save all 1-s (0xffffffff)
+ * as ctx register values.
+ * Luckily these devices always use the same ctx register values, so we can
+ * work around this by saving the ctx registers once on activation.
+ */
+#define LPSS_SAVE_CTX_ONCE		BIT(5)
+#define LPSS_NO_D3_DELAY		BIT(6)
+
+struct lpss_private_data;
+
+struct lpss_device_desc {
+	unsigned int flags;
+	const char *clk_con_id;
+	unsigned int prv_offset;
+	size_t prv_size_override;
+	const struct property_entry *properties;
+	void (*setup)(struct lpss_private_data *pdata);
+	bool resume_from_noirq;
+};
+
+static const struct lpss_device_desc lpss_dma_desc = {
+	.flags = LPSS_CLK,
+};
+
+struct lpss_private_data {
+	struct acpi_device *adev;
+	void __iomem *mmio_base;
+	resource_size_t mmio_size;
+	unsigned int fixed_clk_rate;
+	struct clk *clk;
+	const struct lpss_device_desc *dev_desc;
+	u32 prv_reg_ctx[LPSS_PRV_REG_COUNT];
+};
+
+/* Devices which need to be in D3 before lpss_iosf_enter_d3_state() proceeds */
+static u32 pmc_atom_d3_mask = 0xfe000ffe;
+
+/* LPSS run time quirks */
+static unsigned int lpss_quirks;
+
+/*
+ * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device.
+ *
+ * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover
+ * it can be powered off automatically whenever the last LPSS device goes down.
+ * In case of no power any access to the DMA controller will hang the system.
+ * The behaviour is reproduced on some HP laptops based on Intel BayTrail as
+ * well as on ASuS T100TA transformer.
+ *
+ * This quirk overrides power state of entire LPSS island to keep DMA powered
+ * on whenever we have at least one other device in use.
+ */
+#define LPSS_QUIRK_ALWAYS_POWER_ON	BIT(0)
+
+/* UART Component Parameter Register */
+#define LPSS_UART_CPR			0xF4
+#define LPSS_UART_CPR_AFCE		BIT(4)
+
+static void lpss_uart_setup(struct lpss_private_data *pdata)
+{
+	unsigned int offset;
+	u32 val;
+
+	offset = pdata->dev_desc->prv_offset + LPSS_TX_INT;
+	val = readl(pdata->mmio_base + offset);
+	writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset);
+
+	val = readl(pdata->mmio_base + LPSS_UART_CPR);
+	if (!(val & LPSS_UART_CPR_AFCE)) {
+		offset = pdata->dev_desc->prv_offset + LPSS_GENERAL;
+		val = readl(pdata->mmio_base + offset);
+		val |= LPSS_GENERAL_UART_RTS_OVRD;
+		writel(val, pdata->mmio_base + offset);
+	}
+}
+
+static void lpss_deassert_reset(struct lpss_private_data *pdata)
+{
+	unsigned int offset;
+	u32 val;
+
+	offset = pdata->dev_desc->prv_offset + LPSS_RESETS;
+	val = readl(pdata->mmio_base + offset);
+	val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC;
+	writel(val, pdata->mmio_base + offset);
+}
+
+/*
+ * BYT PWM used for backlight control by the i915 driver on systems without
+ * the Crystal Cove PMIC.
+ */
+static struct pwm_lookup byt_pwm_lookup[] = {
+	PWM_LOOKUP_WITH_MODULE("80860F09:00", 0, "0000:00:02.0",
+			       "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL,
+			       "pwm-lpss-platform"),
+};
+
+static void byt_pwm_setup(struct lpss_private_data *pdata)
+{
+	/* Only call pwm_add_table for the first PWM controller */
+	if (acpi_dev_uid_match(pdata->adev, 1))
+		pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup));
+}
+
+#define LPSS_I2C_ENABLE			0x6c
+
+static void byt_i2c_setup(struct lpss_private_data *pdata)
+{
+	acpi_handle handle = pdata->adev->handle;
+	unsigned long long shared_host = 0;
+	acpi_status status;
+	u64 uid;
+
+	/* Expected to always be successful, but better safe then sorry */
+	if (!acpi_dev_uid_to_integer(pdata->adev, &uid) && uid) {
+		/* Detect I2C bus shared with PUNIT and ignore its d3 status */
+		status = acpi_evaluate_integer(handle, "_SEM", NULL, &shared_host);
+		if (ACPI_SUCCESS(status) && shared_host)
+			pmc_atom_d3_mask &= ~(BIT_LPSS2_F1_I2C1 << (uid - 1));
+	}
+
+	lpss_deassert_reset(pdata);
+
+	if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset))
+		pdata->fixed_clk_rate = 133000000;
+
+	writel(0, pdata->mmio_base + LPSS_I2C_ENABLE);
+}
+
+/*
+ * BSW PWM1 is used for backlight control by the i915 driver
+ * BSW PWM2 is used for backlight control for fixed (etched into the glass)
+ * touch controls on some models. These touch-controls have specialized
+ * drivers which know they need the "pwm_soc_lpss_2" con-id.
+ */
+static struct pwm_lookup bsw_pwm_lookup[] = {
+	PWM_LOOKUP_WITH_MODULE("80862288:00", 0, "0000:00:02.0",
+			       "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL,
+			       "pwm-lpss-platform"),
+	PWM_LOOKUP_WITH_MODULE("80862289:00", 0, NULL,
+			       "pwm_soc_lpss_2", 0, PWM_POLARITY_NORMAL,
+			       "pwm-lpss-platform"),
+};
+
+static void bsw_pwm_setup(struct lpss_private_data *pdata)
+{
+	/* Only call pwm_add_table for the first PWM controller */
+	if (acpi_dev_uid_match(pdata->adev, 1))
+		pwm_add_table(bsw_pwm_lookup, ARRAY_SIZE(bsw_pwm_lookup));
+}
+
+static const struct property_entry lpt_spi_properties[] = {
+	PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_LPT_SSP),
+	{ }
+};
+
+static const struct lpss_device_desc lpt_spi_dev_desc = {
+	.flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR
+			| LPSS_SAVE_CTX,
+	.prv_offset = 0x800,
+	.properties = lpt_spi_properties,
+};
+
+static const struct lpss_device_desc lpt_i2c_dev_desc = {
+	.flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR | LPSS_SAVE_CTX,
+	.prv_offset = 0x800,
+};
+
+static struct property_entry uart_properties[] = {
+	PROPERTY_ENTRY_U32("reg-io-width", 4),
+	PROPERTY_ENTRY_U32("reg-shift", 2),
+	PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"),
+	{ },
+};
+
+static const struct lpss_device_desc lpt_uart_dev_desc = {
+	.flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR
+			| LPSS_SAVE_CTX,
+	.clk_con_id = "baudclk",
+	.prv_offset = 0x800,
+	.setup = lpss_uart_setup,
+	.properties = uart_properties,
+};
+
+static const struct lpss_device_desc lpt_sdio_dev_desc = {
+	.flags = LPSS_LTR,
+	.prv_offset = 0x1000,
+	.prv_size_override = 0x1018,
+};
+
+static const struct lpss_device_desc byt_pwm_dev_desc = {
+	.flags = LPSS_SAVE_CTX,
+	.prv_offset = 0x800,
+	.setup = byt_pwm_setup,
+};
+
+static const struct lpss_device_desc bsw_pwm_dev_desc = {
+	.flags = LPSS_SAVE_CTX_ONCE | LPSS_NO_D3_DELAY,
+	.prv_offset = 0x800,
+	.setup = bsw_pwm_setup,
+	.resume_from_noirq = true,
+};
+
+static const struct lpss_device_desc bsw_pwm2_dev_desc = {
+	.flags = LPSS_SAVE_CTX_ONCE | LPSS_NO_D3_DELAY,
+	.prv_offset = 0x800,
+	.resume_from_noirq = true,
+};
+
+static const struct lpss_device_desc byt_uart_dev_desc = {
+	.flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
+	.clk_con_id = "baudclk",
+	.prv_offset = 0x800,
+	.setup = lpss_uart_setup,
+	.properties = uart_properties,
+};
+
+static const struct lpss_device_desc bsw_uart_dev_desc = {
+	.flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
+			| LPSS_NO_D3_DELAY,
+	.clk_con_id = "baudclk",
+	.prv_offset = 0x800,
+	.setup = lpss_uart_setup,
+	.properties = uart_properties,
+};
+
+static const struct property_entry byt_spi_properties[] = {
+	PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_BYT_SSP),
+	{ }
+};
+
+static const struct lpss_device_desc byt_spi_dev_desc = {
+	.flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
+	.prv_offset = 0x400,
+	.properties = byt_spi_properties,
+};
+
+static const struct lpss_device_desc byt_sdio_dev_desc = {
+	.flags = LPSS_CLK,
+};
+
+static const struct lpss_device_desc byt_i2c_dev_desc = {
+	.flags = LPSS_CLK | LPSS_SAVE_CTX,
+	.prv_offset = 0x800,
+	.setup = byt_i2c_setup,
+	.resume_from_noirq = true,
+};
+
+static const struct lpss_device_desc bsw_i2c_dev_desc = {
+	.flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
+	.prv_offset = 0x800,
+	.setup = byt_i2c_setup,
+	.resume_from_noirq = true,
+};
+
+static const struct property_entry bsw_spi_properties[] = {
+	PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_BSW_SSP),
+	PROPERTY_ENTRY_U32("num-cs", 2),
+	{ }
+};
+
+static const struct lpss_device_desc bsw_spi_dev_desc = {
+	.flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
+			| LPSS_NO_D3_DELAY,
+	.prv_offset = 0x400,
+	.setup = lpss_deassert_reset,
+	.properties = bsw_spi_properties,
+};
+
+static const struct x86_cpu_id lpss_cpu_ids[] = {
+	X86_MATCH_VFM(INTEL_ATOM_SILVERMONT,	NULL),
+	X86_MATCH_VFM(INTEL_ATOM_AIRMONT,	NULL),
+	{}
+};
+
+#else
+
+#define LPSS_ADDR(desc) (0UL)
+
+#endif /* CONFIG_X86_INTEL_LPSS */
+
+static const struct acpi_device_id acpi_lpss_device_ids[] = {
+	/* Generic LPSS devices */
+	{ "INTL9C60", LPSS_ADDR(lpss_dma_desc) },
+
+	/* Lynxpoint LPSS devices */
+	{ "INT33C0", LPSS_ADDR(lpt_spi_dev_desc) },
+	{ "INT33C1", LPSS_ADDR(lpt_spi_dev_desc) },
+	{ "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) },
+	{ "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) },
+	{ "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) },
+	{ "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) },
+	{ "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) },
+
+	/* BayTrail LPSS devices */
+	{ "80860F09", LPSS_ADDR(byt_pwm_dev_desc) },
+	{ "80860F0A", LPSS_ADDR(byt_uart_dev_desc) },
+	{ "80860F0E", LPSS_ADDR(byt_spi_dev_desc) },
+	{ "80860F14", LPSS_ADDR(byt_sdio_dev_desc) },
+	{ "80860F41", LPSS_ADDR(byt_i2c_dev_desc) },
+
+	/* Braswell LPSS devices */
+	{ "80862286", LPSS_ADDR(lpss_dma_desc) },
+	{ "80862288", LPSS_ADDR(bsw_pwm_dev_desc) },
+	{ "80862289", LPSS_ADDR(bsw_pwm2_dev_desc) },
+	{ "8086228A", LPSS_ADDR(bsw_uart_dev_desc) },
+	{ "8086228E", LPSS_ADDR(bsw_spi_dev_desc) },
+	{ "808622C0", LPSS_ADDR(lpss_dma_desc) },
+	{ "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) },
+
+	/* Broadwell LPSS devices */
+	{ "INT3430", LPSS_ADDR(lpt_spi_dev_desc) },
+	{ "INT3431", LPSS_ADDR(lpt_spi_dev_desc) },
+	{ "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) },
+	{ "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) },
+	{ "INT3434", LPSS_ADDR(lpt_uart_dev_desc) },
+	{ "INT3435", LPSS_ADDR(lpt_uart_dev_desc) },
+	{ "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) },
+
+	{ }
+};
+
+#ifdef CONFIG_X86_INTEL_LPSS
+
+/* LPSS main clock device. */
+static struct platform_device *lpss_clk_dev;
+
+static inline void lpt_register_clock_device(void)
+{
+	lpss_clk_dev = platform_device_register_simple("clk-lpss-atom",
+						       PLATFORM_DEVID_NONE,
+						       NULL, 0);
+}
+
+static int register_device_clock(struct acpi_device *adev,
+				 struct lpss_private_data *pdata)
+{
+	const struct lpss_device_desc *dev_desc = pdata->dev_desc;
+	const char *devname = dev_name(&adev->dev);
+	struct clk *clk;
+	struct lpss_clk_data *clk_data;
+	const char *parent, *clk_name;
+	void __iomem *prv_base;
+
+	if (!lpss_clk_dev)
+		lpt_register_clock_device();
+
+	if (IS_ERR(lpss_clk_dev))
+		return PTR_ERR(lpss_clk_dev);
+
+	clk_data = platform_get_drvdata(lpss_clk_dev);
+	if (!clk_data)
+		return -ENODEV;
+	clk = clk_data->clk;
+
+	if (!pdata->mmio_base
+	    || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE)
+		return -ENODATA;
+
+	parent = clk_data->name;
+	prv_base = pdata->mmio_base + dev_desc->prv_offset;
+
+	if (pdata->fixed_clk_rate) {
+		clk = clk_register_fixed_rate(NULL, devname, parent, 0,
+					      pdata->fixed_clk_rate);
+		goto out;
+	}
+
+	if (dev_desc->flags & LPSS_CLK_GATE) {
+		clk = clk_register_gate(NULL, devname, parent, 0,
+					prv_base, 0, 0, NULL);
+		parent = devname;
+	}
+
+	if (dev_desc->flags & LPSS_CLK_DIVIDER) {
+		/* Prevent division by zero */
+		if (!readl(prv_base))
+			writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base);
+
+		clk_name = kasprintf(GFP_KERNEL, "%s-div", devname);
+		if (!clk_name)
+			return -ENOMEM;
+		clk = clk_register_fractional_divider(NULL, clk_name, parent,
+						      0, prv_base, 1, 15, 16, 15,
+						      CLK_FRAC_DIVIDER_POWER_OF_TWO_PS,
+						      NULL);
+		parent = clk_name;
+
+		clk_name = kasprintf(GFP_KERNEL, "%s-update", devname);
+		if (!clk_name) {
+			kfree(parent);
+			return -ENOMEM;
+		}
+		clk = clk_register_gate(NULL, clk_name, parent,
+					CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
+					prv_base, 31, 0, NULL);
+		kfree(parent);
+		kfree(clk_name);
+	}
+out:
+	if (IS_ERR(clk))
+		return PTR_ERR(clk);
+
+	pdata->clk = clk;
+	clk_register_clkdev(clk, dev_desc->clk_con_id, devname);
+	return 0;
+}
+
+struct lpss_device_links {
+	const char *supplier_hid;
+	const char *supplier_uid;
+	const char *consumer_hid;
+	const char *consumer_uid;
+	u32 flags;
+	const struct dmi_system_id *dep_missing_ids;
+};
+
+/* Please keep this list sorted alphabetically by vendor and model */
+static const struct dmi_system_id i2c1_dep_missing_dmi_ids[] = {
+	{
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
+			DMI_MATCH(DMI_PRODUCT_NAME, "T200TA"),
+		},
+	},
+	{}
+};
+
+/*
+ * The _DEP method is used to identify dependencies but instead of creating
+ * device links for every handle in _DEP, only links in the following list are
+ * created. That is necessary because, in the general case, _DEP can refer to
+ * devices that might not have drivers, or that are on different buses, or where
+ * the supplier is not enumerated until after the consumer is probed.
+ */
+static const struct lpss_device_links lpss_device_links[] = {
+	/* CHT External sdcard slot controller depends on PMIC I2C ctrl */
+	{"808622C1", "7", "80860F14", "3", DL_FLAG_PM_RUNTIME},
+	/* CHT iGPU depends on PMIC I2C controller */
+	{"808622C1", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME},
+	/* BYT iGPU depends on the Embedded Controller I2C controller (UID 1) */
+	{"80860F41", "1", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME,
+	 i2c1_dep_missing_dmi_ids},
+	/* BYT CR iGPU depends on PMIC I2C controller (UID 5 on CR) */
+	{"80860F41", "5", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME},
+	/* BYT iGPU depends on PMIC I2C controller (UID 7 on non CR) */
+	{"80860F41", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME},
+};
+
+static bool acpi_lpss_is_supplier(struct acpi_device *adev,
+				  const struct lpss_device_links *link)
+{
+	return acpi_dev_hid_uid_match(adev, link->supplier_hid, link->supplier_uid);
+}
+
+static bool acpi_lpss_is_consumer(struct acpi_device *adev,
+				  const struct lpss_device_links *link)
+{
+	return acpi_dev_hid_uid_match(adev, link->consumer_hid, link->consumer_uid);
+}
+
+struct hid_uid {
+	const char *hid;
+	const char *uid;
+};
+
+static int match_hid_uid(struct device *dev, const void *data)
+{
+	struct acpi_device *adev = ACPI_COMPANION(dev);
+	const struct hid_uid *id = data;
+
+	if (!adev)
+		return 0;
+
+	return acpi_dev_hid_uid_match(adev, id->hid, id->uid);
+}
+
+static struct device *acpi_lpss_find_device(const char *hid, const char *uid)
+{
+	struct device *dev;
+
+	struct hid_uid data = {
+		.hid = hid,
+		.uid = uid,
+	};
+
+	dev = bus_find_device(&platform_bus_type, NULL, &data, match_hid_uid);
+	if (dev)
+		return dev;
+
+	return bus_find_device(&pci_bus_type, NULL, &data, match_hid_uid);
+}
+
+static void acpi_lpss_link_consumer(struct device *dev1,
+				    const struct lpss_device_links *link)
+{
+	struct device *dev2;
+
+	dev2 = acpi_lpss_find_device(link->consumer_hid, link->consumer_uid);
+	if (!dev2)
+		return;
+
+	if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids))
+	    || acpi_device_dep(ACPI_HANDLE(dev2), ACPI_HANDLE(dev1)))
+		device_link_add(dev2, dev1, link->flags);
+
+	put_device(dev2);
+}
+
+static void acpi_lpss_link_supplier(struct device *dev1,
+				    const struct lpss_device_links *link)
+{
+	struct device *dev2;
+
+	dev2 = acpi_lpss_find_device(link->supplier_hid, link->supplier_uid);
+	if (!dev2)
+		return;
+
+	if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids))
+	    || acpi_device_dep(ACPI_HANDLE(dev1), ACPI_HANDLE(dev2)))
+		device_link_add(dev1, dev2, link->flags);
+
+	put_device(dev2);
+}
+
+static void acpi_lpss_create_device_links(struct acpi_device *adev,
+					  struct platform_device *pdev)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(lpss_device_links); i++) {
+		const struct lpss_device_links *link = &lpss_device_links[i];
+
+		if (acpi_lpss_is_supplier(adev, link))
+			acpi_lpss_link_consumer(&pdev->dev, link);
+
+		if (acpi_lpss_is_consumer(adev, link))
+			acpi_lpss_link_supplier(&pdev->dev, link);
+	}
+}
+
+static int acpi_lpss_create_device(struct acpi_device *adev,
+				   const struct acpi_device_id *id)
+{
+	const struct lpss_device_desc *dev_desc;
+	struct lpss_private_data *pdata;
+	struct resource_entry *rentry;
+	struct list_head resource_list;
+	struct platform_device *pdev;
+	int ret;
+
+	dev_desc = (const struct lpss_device_desc *)id->driver_data;
+	if (!dev_desc)
+		return -EINVAL;
+
+	pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
+	if (!pdata)
+		return -ENOMEM;
+
+	INIT_LIST_HEAD(&resource_list);
+	ret = acpi_dev_get_memory_resources(adev, &resource_list);
+	if (ret < 0)
+		goto err_out;
+
+	rentry = list_first_entry_or_null(&resource_list, struct resource_entry, node);
+	if (rentry) {
+		if (dev_desc->prv_size_override)
+			pdata->mmio_size = dev_desc->prv_size_override;
+		else
+			pdata->mmio_size = resource_size(rentry->res);
+		pdata->mmio_base = ioremap(rentry->res->start, pdata->mmio_size);
+	}
+
+	acpi_dev_free_resource_list(&resource_list);
+
+	if (!pdata->mmio_base) {
+		/* Avoid acpi_bus_attach() instantiating a pdev for this dev. */
+		adev->pnp.type.platform_id = 0;
+		goto out_free;
+	}
+
+	pdata->adev = adev;
+	pdata->dev_desc = dev_desc;
+
+	if (dev_desc->setup)
+		dev_desc->setup(pdata);
+
+	if (dev_desc->flags & LPSS_CLK) {
+		ret = register_device_clock(adev, pdata);
+		if (ret)
+			goto out_free;
+	}
+
+	/*
+	 * This works around a known issue in ACPI tables where LPSS devices
+	 * have _PS0 and _PS3 without _PSC (and no power resources), so
+	 * acpi_bus_init_power() will assume that the BIOS has put them into D0.
+	 */
+	acpi_device_fix_up_power(adev);
+
+	adev->driver_data = pdata;
+	pdev = acpi_create_platform_device(adev, dev_desc->properties);
+	if (IS_ERR_OR_NULL(pdev)) {
+		adev->driver_data = NULL;
+		ret = PTR_ERR(pdev);
+		goto err_out;
+	}
+
+	acpi_lpss_create_device_links(adev, pdev);
+	return 1;
+
+out_free:
+	/* Skip the device, but continue the namespace scan */
+	ret = 0;
+err_out:
+	kfree(pdata);
+	return ret;
+}
+
+static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg)
+{
+	return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
+}
+
+static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata,
+			     unsigned int reg)
+{
+	writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
+}
+
+static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val)
+{
+	struct acpi_device *adev = ACPI_COMPANION(dev);
+	struct lpss_private_data *pdata;
+	unsigned long flags;
+	int ret;
+
+	if (WARN_ON(!adev))
+		return -ENODEV;
+
+	spin_lock_irqsave(&dev->power.lock, flags);
+	if (pm_runtime_suspended(dev)) {
+		ret = -EAGAIN;
+		goto out;
+	}
+	pdata = acpi_driver_data(adev);
+	if (WARN_ON(!pdata || !pdata->mmio_base)) {
+		ret = -ENODEV;
+		goto out;
+	}
+	*val = __lpss_reg_read(pdata, reg);
+	ret = 0;
+
+ out:
+	spin_unlock_irqrestore(&dev->power.lock, flags);
+	return ret;
+}
+
+static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr,
+			     char *buf)
+{
+	u32 ltr_value = 0;
+	unsigned int reg;
+	int ret;
+
+	reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR;
+	ret = lpss_reg_read(dev, reg, &ltr_value);
+	if (ret)
+		return ret;
+
+	return sysfs_emit(buf, "%08x\n", ltr_value);
+}
+
+static ssize_t lpss_ltr_mode_show(struct device *dev,
+				  struct device_attribute *attr, char *buf)
+{
+	u32 ltr_mode = 0;
+	char *outstr;
+	int ret;
+
+	ret = lpss_reg_read(dev, LPSS_GENERAL, &ltr_mode);
+	if (ret)
+		return ret;
+
+	outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto";
+	return sprintf(buf, "%s\n", outstr);
+}
+
+static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL);
+static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL);
+static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL);
+
+static struct attribute *lpss_attrs[] = {
+	&dev_attr_auto_ltr.attr,
+	&dev_attr_sw_ltr.attr,
+	&dev_attr_ltr_mode.attr,
+	NULL,
+};
+
+static const struct attribute_group lpss_attr_group = {
+	.attrs = lpss_attrs,
+	.name = "lpss_ltr",
+};
+
+static void acpi_lpss_set_ltr(struct device *dev, s32 val)
+{
+	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
+	u32 ltr_mode, ltr_val;
+
+	ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL);
+	if (val < 0) {
+		if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) {
+			ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW;
+			__lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
+		}
+		return;
+	}
+	ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK;
+	if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) {
+		ltr_val |= LPSS_LTR_SNOOP_LAT_32US;
+		val = LPSS_LTR_MAX_VAL;
+	} else if (val > LPSS_LTR_MAX_VAL) {
+		ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ;
+		val >>= LPSS_LTR_SNOOP_LAT_SHIFT;
+	} else {
+		ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ;
+	}
+	ltr_val |= val;
+	__lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR);
+	if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) {
+		ltr_mode |= LPSS_GENERAL_LTR_MODE_SW;
+		__lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
+	}
+}
+
+#ifdef CONFIG_PM
+/**
+ * acpi_lpss_save_ctx() - Save the private registers of LPSS device
+ * @dev: LPSS device
+ * @pdata: pointer to the private data of the LPSS device
+ *
+ * Most LPSS devices have private registers which may loose their context when
+ * the device is powered down. acpi_lpss_save_ctx() saves those registers into
+ * prv_reg_ctx array.
+ */
+static void acpi_lpss_save_ctx(struct device *dev,
+			       struct lpss_private_data *pdata)
+{
+	unsigned int i;
+
+	for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
+		unsigned long offset = i * sizeof(u32);
+
+		pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset);
+		dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n",
+			pdata->prv_reg_ctx[i], offset);
+	}
+}
+
+/**
+ * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device
+ * @dev: LPSS device
+ * @pdata: pointer to the private data of the LPSS device
+ *
+ * Restores the registers that were previously stored with acpi_lpss_save_ctx().
+ */
+static void acpi_lpss_restore_ctx(struct device *dev,
+				  struct lpss_private_data *pdata)
+{
+	unsigned int i;
+
+	for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
+		unsigned long offset = i * sizeof(u32);
+
+		__lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset);
+		dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n",
+			pdata->prv_reg_ctx[i], offset);
+	}
+}
+
+static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data *pdata)
+{
+	/*
+	 * The following delay is needed or the subsequent write operations may
+	 * fail. The LPSS devices are actually PCI devices and the PCI spec
+	 * expects 10ms delay before the device can be accessed after D3 to D0
+	 * transition. However some platforms like BSW does not need this delay.
+	 */
+	unsigned int delay = 10;	/* default 10ms delay */
+
+	if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY)
+		delay = 0;
+
+	msleep(delay);
+}
+
+static int acpi_lpss_activate(struct device *dev)
+{
+	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
+	int ret;
+
+	ret = acpi_dev_resume(dev);
+	if (ret)
+		return ret;
+
+	acpi_lpss_d3_to_d0_delay(pdata);
+
+	/*
+	 * This is called only on ->probe() stage where a device is either in
+	 * known state defined by BIOS or most likely powered off. Due to this
+	 * we have to deassert reset line to be sure that ->probe() will
+	 * recognize the device.
+	 */
+	if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE))
+		lpss_deassert_reset(pdata);
+
+	if (pdata->dev_desc->flags & LPSS_SAVE_CTX_ONCE)
+		acpi_lpss_save_ctx(dev, pdata);
+
+	return 0;
+}
+
+static void acpi_lpss_dismiss(struct device *dev)
+{
+	acpi_dev_suspend(dev, false);
+}
+
+/* IOSF SB for LPSS island */
+#define LPSS_IOSF_UNIT_LPIOEP		0xA0
+#define LPSS_IOSF_UNIT_LPIO1		0xAB
+#define LPSS_IOSF_UNIT_LPIO2		0xAC
+
+#define LPSS_IOSF_PMCSR			0x84
+#define LPSS_PMCSR_D0			0
+#define LPSS_PMCSR_D3hot		3
+#define LPSS_PMCSR_Dx_MASK		GENMASK(1, 0)
+
+#define LPSS_IOSF_GPIODEF0		0x154
+#define LPSS_GPIODEF0_DMA1_D3		BIT(2)
+#define LPSS_GPIODEF0_DMA2_D3		BIT(3)
+#define LPSS_GPIODEF0_DMA_D3_MASK	GENMASK(3, 2)
+#define LPSS_GPIODEF0_DMA_LLP		BIT(13)
+
+static DEFINE_MUTEX(lpss_iosf_mutex);
+static bool lpss_iosf_d3_entered = true;
+
+static void lpss_iosf_enter_d3_state(void)
+{
+	u32 value1 = 0;
+	u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;
+	u32 value2 = LPSS_PMCSR_D3hot;
+	u32 mask2 = LPSS_PMCSR_Dx_MASK;
+	/*
+	 * PMC provides an information about actual status of the LPSS devices.
+	 * Here we read the values related to LPSS power island, i.e. LPSS
+	 * devices, excluding both LPSS DMA controllers, along with SCC domain.
+	 */
+	u32 func_dis, d3_sts_0, pmc_status;
+	int ret;
+
+	ret = pmc_atom_read(PMC_FUNC_DIS, &func_dis);
+	if (ret)
+		return;
+
+	mutex_lock(&lpss_iosf_mutex);
+
+	ret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0);
+	if (ret)
+		goto exit;
+
+	/*
+	 * Get the status of entire LPSS power island per device basis.
+	 * Shutdown both LPSS DMA controllers if and only if all other devices
+	 * are already in D3hot.
+	 */
+	pmc_status = (~(d3_sts_0 | func_dis)) & pmc_atom_d3_mask;
+	if (pmc_status)
+		goto exit;
+
+	iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,
+			LPSS_IOSF_PMCSR, value2, mask2);
+
+	iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,
+			LPSS_IOSF_PMCSR, value2, mask2);
+
+	iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,
+			LPSS_IOSF_GPIODEF0, value1, mask1);
+
+	lpss_iosf_d3_entered = true;
+
+exit:
+	mutex_unlock(&lpss_iosf_mutex);
+}
+
+static void lpss_iosf_exit_d3_state(void)
+{
+	u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 |
+		     LPSS_GPIODEF0_DMA_LLP;
+	u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;
+	u32 value2 = LPSS_PMCSR_D0;
+	u32 mask2 = LPSS_PMCSR_Dx_MASK;
+
+	mutex_lock(&lpss_iosf_mutex);
+
+	if (!lpss_iosf_d3_entered)
+		goto exit;
+
+	lpss_iosf_d3_entered = false;
+
+	iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,
+			LPSS_IOSF_GPIODEF0, value1, mask1);
+
+	iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,
+			LPSS_IOSF_PMCSR, value2, mask2);
+
+	iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,
+			LPSS_IOSF_PMCSR, value2, mask2);
+
+exit:
+	mutex_unlock(&lpss_iosf_mutex);
+}
+
+static int acpi_lpss_suspend(struct device *dev, bool wakeup)
+{
+	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
+	int ret;
+
+	if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
+		acpi_lpss_save_ctx(dev, pdata);
+
+	ret = acpi_dev_suspend(dev, wakeup);
+
+	/*
+	 * This call must be last in the sequence, otherwise PMC will return
+	 * wrong status for devices being about to be powered off. See
+	 * lpss_iosf_enter_d3_state() for further information.
+	 */
+	if (acpi_target_system_state() == ACPI_STATE_S0 &&
+	    lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available())
+		lpss_iosf_enter_d3_state();
+
+	return ret;
+}
+
+static int acpi_lpss_resume(struct device *dev)
+{
+	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
+	int ret;
+
+	/*
+	 * This call is kept first to be in symmetry with
+	 * acpi_lpss_runtime_suspend() one.
+	 */
+	if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available())
+		lpss_iosf_exit_d3_state();
+
+	ret = acpi_dev_resume(dev);
+	if (ret)
+		return ret;
+
+	acpi_lpss_d3_to_d0_delay(pdata);
+
+	if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE))
+		acpi_lpss_restore_ctx(dev, pdata);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int acpi_lpss_do_suspend_late(struct device *dev)
+{
+	int ret;
+
+	if (dev_pm_skip_suspend(dev))
+		return 0;
+
+	ret = pm_generic_suspend_late(dev);
+	return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev));
+}
+
+static int acpi_lpss_suspend_late(struct device *dev)
+{
+	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
+
+	if (pdata->dev_desc->resume_from_noirq)
+		return 0;
+
+	return acpi_lpss_do_suspend_late(dev);
+}
+
+static int acpi_lpss_suspend_noirq(struct device *dev)
+{
+	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
+	int ret;
+
+	if (pdata->dev_desc->resume_from_noirq) {
+		/*
+		 * The driver's ->suspend_late callback will be invoked by
+		 * acpi_lpss_do_suspend_late(), with the assumption that the
+		 * driver really wanted to run that code in ->suspend_noirq, but
+		 * it could not run after acpi_dev_suspend() and the driver
+		 * expected the latter to be called in the "late" phase.
+		 */
+		ret = acpi_lpss_do_suspend_late(dev);
+		if (ret)
+			return ret;
+	}
+
+	return acpi_subsys_suspend_noirq(dev);
+}
+
+static int acpi_lpss_do_resume_early(struct device *dev)
+{
+	int ret = acpi_lpss_resume(dev);
+
+	return ret ? ret : pm_generic_resume_early(dev);
+}
+
+static int acpi_lpss_resume_early(struct device *dev)
+{
+	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
+
+	if (pdata->dev_desc->resume_from_noirq)
+		return 0;
+
+	if (dev_pm_skip_resume(dev))
+		return 0;
+
+	return acpi_lpss_do_resume_early(dev);
+}
+
+static int acpi_lpss_resume_noirq(struct device *dev)
+{
+	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
+	int ret;
+
+	/* Follow acpi_subsys_resume_noirq(). */
+	if (dev_pm_skip_resume(dev))
+		return 0;
+
+	ret = pm_generic_resume_noirq(dev);
+	if (ret)
+		return ret;
+
+	if (!pdata->dev_desc->resume_from_noirq)
+		return 0;
+
+	/*
+	 * The driver's ->resume_early callback will be invoked by
+	 * acpi_lpss_do_resume_early(), with the assumption that the driver
+	 * really wanted to run that code in ->resume_noirq, but it could not
+	 * run before acpi_dev_resume() and the driver expected the latter to be
+	 * called in the "early" phase.
+	 */
+	return acpi_lpss_do_resume_early(dev);
+}
+
+static int acpi_lpss_do_restore_early(struct device *dev)
+{
+	int ret = acpi_lpss_resume(dev);
+
+	return ret ? ret : pm_generic_restore_early(dev);
+}
+
+static int acpi_lpss_restore_early(struct device *dev)
+{
+	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
+
+	if (pdata->dev_desc->resume_from_noirq)
+		return 0;
+
+	return acpi_lpss_do_restore_early(dev);
+}
+
+static int acpi_lpss_restore_noirq(struct device *dev)
+{
+	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
+	int ret;
+
+	ret = pm_generic_restore_noirq(dev);
+	if (ret)
+		return ret;
+
+	if (!pdata->dev_desc->resume_from_noirq)
+		return 0;
+
+	/* This is analogous to what happens in acpi_lpss_resume_noirq(). */
+	return acpi_lpss_do_restore_early(dev);
+}
+
+static int acpi_lpss_do_poweroff_late(struct device *dev)
+{
+	int ret = pm_generic_poweroff_late(dev);
+
+	return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev));
+}
+
+static int acpi_lpss_poweroff_late(struct device *dev)
+{
+	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
+
+	if (dev_pm_skip_suspend(dev))
+		return 0;
+
+	if (pdata->dev_desc->resume_from_noirq)
+		return 0;
+
+	return acpi_lpss_do_poweroff_late(dev);
+}
+
+static int acpi_lpss_poweroff_noirq(struct device *dev)
+{
+	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
+
+	if (dev_pm_skip_suspend(dev))
+		return 0;
+
+	if (pdata->dev_desc->resume_from_noirq) {
+		/* This is analogous to the acpi_lpss_suspend_noirq() case. */
+		int ret = acpi_lpss_do_poweroff_late(dev);
+
+		if (ret)
+			return ret;
+	}
+
+	return pm_generic_poweroff_noirq(dev);
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static int acpi_lpss_runtime_suspend(struct device *dev)
+{
+	int ret = pm_generic_runtime_suspend(dev);
+
+	return ret ? ret : acpi_lpss_suspend(dev, true);
+}
+
+static int acpi_lpss_runtime_resume(struct device *dev)
+{
+	int ret = acpi_lpss_resume(dev);
+
+	return ret ? ret : pm_generic_runtime_resume(dev);
+}
+#endif /* CONFIG_PM */
+
+static struct dev_pm_domain acpi_lpss_pm_domain = {
+#ifdef CONFIG_PM
+	.activate = acpi_lpss_activate,
+	.dismiss = acpi_lpss_dismiss,
+#endif
+	.ops = {
+#ifdef CONFIG_PM
+#ifdef CONFIG_PM_SLEEP
+		.prepare = acpi_subsys_prepare,
+		.complete = acpi_subsys_complete,
+		.suspend = acpi_subsys_suspend,
+		.suspend_late = acpi_lpss_suspend_late,
+		.suspend_noirq = acpi_lpss_suspend_noirq,
+		.resume_noirq = acpi_lpss_resume_noirq,
+		.resume_early = acpi_lpss_resume_early,
+		.freeze = acpi_subsys_freeze,
+		.poweroff = acpi_subsys_poweroff,
+		.poweroff_late = acpi_lpss_poweroff_late,
+		.poweroff_noirq = acpi_lpss_poweroff_noirq,
+		.restore_noirq = acpi_lpss_restore_noirq,
+		.restore_early = acpi_lpss_restore_early,
+#endif
+		.runtime_suspend = acpi_lpss_runtime_suspend,
+		.runtime_resume = acpi_lpss_runtime_resume,
+#endif
+	},
+};
+
+static int acpi_lpss_platform_notify(struct notifier_block *nb,
+				     unsigned long action, void *data)
+{
+	struct platform_device *pdev = to_platform_device(data);
+	struct lpss_private_data *pdata;
+	struct acpi_device *adev;
+	const struct acpi_device_id *id;
+
+	id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev);
+	if (!id || !id->driver_data)
+		return 0;
+
+	adev = ACPI_COMPANION(&pdev->dev);
+	if (!adev)
+		return 0;
+
+	pdata = acpi_driver_data(adev);
+	if (!pdata)
+		return 0;
+
+	if (pdata->mmio_base &&
+	    pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) {
+		dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n");
+		return 0;
+	}
+
+	switch (action) {
+	case BUS_NOTIFY_BIND_DRIVER:
+		dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain);
+		break;
+	case BUS_NOTIFY_DRIVER_NOT_BOUND:
+	case BUS_NOTIFY_UNBOUND_DRIVER:
+		dev_pm_domain_set(&pdev->dev, NULL);
+		break;
+	case BUS_NOTIFY_ADD_DEVICE:
+		dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain);
+		if (pdata->dev_desc->flags & LPSS_LTR)
+			return sysfs_create_group(&pdev->dev.kobj,
+						  &lpss_attr_group);
+		break;
+	case BUS_NOTIFY_DEL_DEVICE:
+		if (pdata->dev_desc->flags & LPSS_LTR)
+			sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group);
+		dev_pm_domain_set(&pdev->dev, NULL);
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static struct notifier_block acpi_lpss_nb = {
+	.notifier_call = acpi_lpss_platform_notify,
+};
+
+static void acpi_lpss_bind(struct device *dev)
+{
+	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
+
+	if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR))
+		return;
+
+	if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE)
+		dev->power.set_latency_tolerance = acpi_lpss_set_ltr;
+	else
+		dev_err(dev, "MMIO size insufficient to access LTR\n");
+}
+
+static void acpi_lpss_unbind(struct device *dev)
+{
+	dev->power.set_latency_tolerance = NULL;
+}
+
+static struct acpi_scan_handler lpss_handler = {
+	.ids = acpi_lpss_device_ids,
+	.attach = acpi_lpss_create_device,
+	.bind = acpi_lpss_bind,
+	.unbind = acpi_lpss_unbind,
+};
+
+void __init acpi_lpss_init(void)
+{
+	const struct x86_cpu_id *id;
+	int ret;
+
+	ret = lpss_atom_clk_init();
+	if (ret)
+		return;
+
+	id = x86_match_cpu(lpss_cpu_ids);
+	if (id)
+		lpss_quirks |= LPSS_QUIRK_ALWAYS_POWER_ON;
+
+	bus_register_notifier(&platform_bus_type, &acpi_lpss_nb);
+	acpi_scan_add_handler(&lpss_handler);
+}
+
+#else
+
+static struct acpi_scan_handler lpss_handler = {
+	.ids = acpi_lpss_device_ids,
+};
+
+void __init acpi_lpss_init(void)
+{
+	acpi_scan_add_handler(&lpss_handler);
+}
+
+#endif /* CONFIG_X86_INTEL_LPSS */
diff --git a/drivers/acpi/x86/s2idle.c b/drivers/acpi/x86/s2idle.c
new file mode 100644
index 000000000000..6d4d06236f61
--- /dev/null
+++ b/drivers/acpi/x86/s2idle.c
@@ -0,0 +1,676 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Architecture-specific ACPI-based support for suspend-to-idle.
+ *
+ * Author: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+ * Author: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
+ * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
+ *
+ * On platforms supporting the Low Power S0 Idle interface there is an ACPI
+ * device object with the PNP0D80 compatible device ID (System Power Management
+ * Controller) and a specific _DSM method under it.  That method, if present,
+ * can be used to indicate to the platform that the OS is transitioning into a
+ * low-power state in which certain types of activity are not desirable or that
+ * it is leaving such a state, which allows the platform to adjust its operation
+ * mode accordingly.
+ */
+
+#include <linux/acpi.h>
+#include <linux/device.h>
+#include <linux/dmi.h>
+#include <linux/suspend.h>
+
+#include "../sleep.h"
+
+#ifdef CONFIG_SUSPEND
+
+static bool sleep_no_lps0 __read_mostly;
+module_param(sleep_no_lps0, bool, 0644);
+MODULE_PARM_DESC(sleep_no_lps0, "Do not use the special LPS0 device interface");
+
+static const struct acpi_device_id lps0_device_ids[] = {
+	{"PNP0D80", },
+	{"", },
+};
+
+/* Microsoft platform agnostic UUID */
+#define ACPI_LPS0_DSM_UUID_MICROSOFT      "11e00d56-ce64-47ce-837b-1f898f9aa461"
+
+#define ACPI_LPS0_DSM_UUID	"c4eb40a0-6cd2-11e2-bcfd-0800200c9a66"
+
+#define ACPI_LPS0_GET_DEVICE_CONSTRAINTS	1
+#define ACPI_LPS0_SCREEN_OFF	3
+#define ACPI_LPS0_SCREEN_ON	4
+#define ACPI_LPS0_ENTRY		5
+#define ACPI_LPS0_EXIT		6
+#define ACPI_LPS0_MS_ENTRY      7
+#define ACPI_LPS0_MS_EXIT       8
+
+/* AMD */
+#define ACPI_LPS0_DSM_UUID_AMD      "e3f32452-febc-43ce-9039-932122d37721"
+#define ACPI_LPS0_ENTRY_AMD         2
+#define ACPI_LPS0_EXIT_AMD          3
+#define ACPI_LPS0_SCREEN_OFF_AMD    4
+#define ACPI_LPS0_SCREEN_ON_AMD     5
+
+static acpi_handle lps0_device_handle;
+static guid_t lps0_dsm_guid;
+static int lps0_dsm_func_mask;
+
+static guid_t lps0_dsm_guid_microsoft;
+static int lps0_dsm_func_mask_microsoft;
+static int lps0_dsm_state;
+
+/* Device constraint entry structure */
+struct lpi_device_info {
+	char *name;
+	int enabled;
+	union acpi_object *package;
+};
+
+/* Constraint package structure */
+struct lpi_device_constraint {
+	int uid;
+	int min_dstate;
+	int function_states;
+};
+
+struct lpi_constraints {
+	acpi_handle handle;
+	int min_dstate;
+};
+
+/* AMD Constraint package structure */
+struct lpi_device_constraint_amd {
+	char *name;
+	int enabled;
+	int function_states;
+	int min_dstate;
+};
+
+static LIST_HEAD(lps0_s2idle_devops_head);
+
+static struct lpi_constraints *lpi_constraints_table;
+static int lpi_constraints_table_size;
+static int rev_id;
+
+#define for_each_lpi_constraint(entry)						\
+	for (int i = 0;								\
+	     entry = &lpi_constraints_table[i], i < lpi_constraints_table_size;	\
+	     i++)
+
+static void lpi_device_get_constraints_amd(void)
+{
+	union acpi_object *out_obj;
+	int i, j, k;
+
+	out_obj = acpi_evaluate_dsm_typed(lps0_device_handle, &lps0_dsm_guid,
+					  rev_id, ACPI_LPS0_GET_DEVICE_CONSTRAINTS,
+					  NULL, ACPI_TYPE_PACKAGE);
+
+	acpi_handle_debug(lps0_device_handle, "_DSM function 1 eval %s\n",
+			  out_obj ? "successful" : "failed");
+
+	if (!out_obj)
+		return;
+
+	for (i = 0; i < out_obj->package.count; i++) {
+		union acpi_object *package = &out_obj->package.elements[i];
+
+		if (package->type == ACPI_TYPE_PACKAGE) {
+			if (lpi_constraints_table) {
+				acpi_handle_err(lps0_device_handle,
+						"Duplicate constraints list\n");
+				goto free_acpi_buffer;
+			}
+
+			lpi_constraints_table = kcalloc(package->package.count,
+							sizeof(*lpi_constraints_table),
+							GFP_KERNEL);
+
+			if (!lpi_constraints_table)
+				goto free_acpi_buffer;
+
+			acpi_handle_debug(lps0_device_handle,
+					  "LPI: constraints list begin:\n");
+
+			for (j = 0; j < package->package.count; j++) {
+				union acpi_object *info_obj = &package->package.elements[j];
+				struct lpi_device_constraint_amd dev_info = {};
+				struct lpi_constraints *list;
+				acpi_status status;
+
+				list = &lpi_constraints_table[lpi_constraints_table_size];
+
+				for (k = 0; k < info_obj->package.count; k++) {
+					union acpi_object *obj = &info_obj->package.elements[k];
+
+					switch (k) {
+					case 0:
+						dev_info.enabled = obj->integer.value;
+						break;
+					case 1:
+						dev_info.name = obj->string.pointer;
+						break;
+					case 2:
+						dev_info.function_states = obj->integer.value;
+						break;
+					case 3:
+						dev_info.min_dstate = obj->integer.value;
+						break;
+					}
+				}
+
+				acpi_handle_debug(lps0_device_handle,
+						  "Name:%s, Enabled: %d, States: %d, MinDstate: %d\n",
+						  dev_info.name,
+						  dev_info.enabled,
+						  dev_info.function_states,
+						  dev_info.min_dstate);
+
+				if (!dev_info.enabled || !dev_info.name ||
+				    !dev_info.min_dstate)
+					continue;
+
+				status = acpi_get_handle(NULL, dev_info.name, &list->handle);
+				if (ACPI_FAILURE(status))
+					continue;
+
+				list->min_dstate = dev_info.min_dstate;
+
+				lpi_constraints_table_size++;
+			}
+		}
+	}
+
+	acpi_handle_debug(lps0_device_handle, "LPI: constraints list end\n");
+
+free_acpi_buffer:
+	ACPI_FREE(out_obj);
+}
+
+static void lpi_device_get_constraints(void)
+{
+	union acpi_object *out_obj;
+	int i;
+
+	out_obj = acpi_evaluate_dsm_typed(lps0_device_handle, &lps0_dsm_guid,
+					  1, ACPI_LPS0_GET_DEVICE_CONSTRAINTS,
+					  NULL, ACPI_TYPE_PACKAGE);
+
+	acpi_handle_debug(lps0_device_handle, "_DSM function 1 eval %s\n",
+			  out_obj ? "successful" : "failed");
+
+	if (!out_obj)
+		return;
+
+	lpi_constraints_table = kcalloc(out_obj->package.count,
+					sizeof(*lpi_constraints_table),
+					GFP_KERNEL);
+	if (!lpi_constraints_table)
+		goto free_acpi_buffer;
+
+	acpi_handle_debug(lps0_device_handle, "LPI: constraints list begin:\n");
+
+	for (i = 0; i < out_obj->package.count; i++) {
+		struct lpi_constraints *constraint;
+		acpi_status status;
+		union acpi_object *package = &out_obj->package.elements[i];
+		struct lpi_device_info info = { };
+		int package_count = 0, j;
+
+		if (!package)
+			continue;
+
+		for (j = 0; j < package->package.count; j++) {
+			union acpi_object *element =
+					&(package->package.elements[j]);
+
+			switch (element->type) {
+			case ACPI_TYPE_INTEGER:
+				info.enabled = element->integer.value;
+				break;
+			case ACPI_TYPE_STRING:
+				info.name = element->string.pointer;
+				break;
+			case ACPI_TYPE_PACKAGE:
+				package_count = element->package.count;
+				info.package = element->package.elements;
+				break;
+			}
+		}
+
+		if (!info.enabled || !info.package || !info.name)
+			continue;
+
+		constraint = &lpi_constraints_table[lpi_constraints_table_size];
+
+		status = acpi_get_handle(NULL, info.name, &constraint->handle);
+		if (ACPI_FAILURE(status))
+			continue;
+
+		acpi_handle_debug(lps0_device_handle,
+				  "index:%d Name:%s\n", i, info.name);
+
+		constraint->min_dstate = -1;
+
+		for (j = 0; j < package_count; j++) {
+			union acpi_object *info_obj = &info.package[j];
+			union acpi_object *cnstr_pkg;
+			union acpi_object *obj;
+			struct lpi_device_constraint dev_info;
+
+			switch (info_obj->type) {
+			case ACPI_TYPE_INTEGER:
+				/* version */
+				break;
+			case ACPI_TYPE_PACKAGE:
+				if (info_obj->package.count < 2)
+					break;
+
+				cnstr_pkg = info_obj->package.elements;
+				obj = &cnstr_pkg[0];
+				dev_info.uid = obj->integer.value;
+				obj = &cnstr_pkg[1];
+				dev_info.min_dstate = obj->integer.value;
+
+				acpi_handle_debug(lps0_device_handle,
+					"uid:%d min_dstate:%s\n",
+					dev_info.uid,
+					acpi_power_state_string(dev_info.min_dstate));
+
+				constraint->min_dstate = dev_info.min_dstate;
+				break;
+			}
+		}
+
+		if (constraint->min_dstate < 0) {
+			acpi_handle_debug(lps0_device_handle,
+					  "Incomplete constraint defined\n");
+			continue;
+		}
+
+		lpi_constraints_table_size++;
+	}
+
+	acpi_handle_debug(lps0_device_handle, "LPI: constraints list end\n");
+
+free_acpi_buffer:
+	ACPI_FREE(out_obj);
+}
+
+static void lpi_check_constraints(void)
+{
+	struct lpi_constraints *entry;
+
+	if (IS_ERR_OR_NULL(lpi_constraints_table))
+		return;
+
+	for_each_lpi_constraint(entry) {
+		struct acpi_device *adev = acpi_fetch_acpi_dev(entry->handle);
+
+		if (!adev)
+			continue;
+
+		acpi_handle_debug(entry->handle,
+			"LPI: required min power state:%s current power state:%s\n",
+			acpi_power_state_string(entry->min_dstate),
+			acpi_power_state_string(adev->power.state));
+
+		if (!adev->flags.power_manageable) {
+			acpi_handle_info(entry->handle, "LPI: Device not power manageable\n");
+			entry->handle = NULL;
+			continue;
+		}
+
+		if (adev->power.state < entry->min_dstate)
+			acpi_handle_info(entry->handle,
+				"LPI: Constraint not met; min power state:%s current power state:%s\n",
+				acpi_power_state_string(entry->min_dstate),
+				acpi_power_state_string(adev->power.state));
+	}
+}
+
+static bool acpi_s2idle_vendor_amd(void)
+{
+	return boot_cpu_data.x86_vendor == X86_VENDOR_AMD;
+}
+
+static const char *acpi_sleep_dsm_state_to_str(unsigned int state)
+{
+	if (lps0_dsm_func_mask_microsoft || !acpi_s2idle_vendor_amd()) {
+		switch (state) {
+		case ACPI_LPS0_SCREEN_OFF:
+			return "screen off";
+		case ACPI_LPS0_SCREEN_ON:
+			return "screen on";
+		case ACPI_LPS0_ENTRY:
+			return "lps0 entry";
+		case ACPI_LPS0_EXIT:
+			return "lps0 exit";
+		case ACPI_LPS0_MS_ENTRY:
+			return "lps0 ms entry";
+		case ACPI_LPS0_MS_EXIT:
+			return "lps0 ms exit";
+		}
+	} else {
+		switch (state) {
+		case ACPI_LPS0_SCREEN_ON_AMD:
+			return "screen on";
+		case ACPI_LPS0_SCREEN_OFF_AMD:
+			return "screen off";
+		case ACPI_LPS0_ENTRY_AMD:
+			return "lps0 entry";
+		case ACPI_LPS0_EXIT_AMD:
+			return "lps0 exit";
+		}
+	}
+
+	return "unknown";
+}
+
+static void acpi_sleep_run_lps0_dsm(unsigned int func, unsigned int func_mask, guid_t dsm_guid)
+{
+	union acpi_object *out_obj;
+
+	if (!(func_mask & (1 << func)))
+		return;
+
+	out_obj = acpi_evaluate_dsm(lps0_device_handle, &dsm_guid,
+					rev_id, func, NULL);
+	ACPI_FREE(out_obj);
+
+	lps0_dsm_state = func;
+	if (pm_debug_messages_on) {
+		acpi_handle_info(lps0_device_handle,
+				"%s transitioned to state %s\n",
+				 out_obj ? "Successfully" : "Failed to",
+				 acpi_sleep_dsm_state_to_str(lps0_dsm_state));
+	}
+}
+
+
+static int validate_dsm(acpi_handle handle, const char *uuid, int rev, guid_t *dsm_guid)
+{
+	union acpi_object *obj;
+	int ret = -EINVAL;
+
+	guid_parse(uuid, dsm_guid);
+
+	/* Check if the _DSM is present and as expected. */
+	obj = acpi_evaluate_dsm_typed(handle, dsm_guid, rev, 0, NULL, ACPI_TYPE_BUFFER);
+	if (!obj || obj->buffer.length == 0 || obj->buffer.length > sizeof(u32)) {
+		acpi_handle_debug(handle,
+				"_DSM UUID %s rev %d function 0 evaluation failed\n", uuid, rev);
+		goto out;
+	}
+
+	ret = *(int *)obj->buffer.pointer;
+	acpi_handle_debug(handle, "_DSM UUID %s rev %d function mask: 0x%x\n", uuid, rev, ret);
+
+out:
+	ACPI_FREE(obj);
+	return ret;
+}
+
+struct amd_lps0_hid_device_data {
+	const bool check_off_by_one;
+};
+
+static const struct amd_lps0_hid_device_data amd_picasso = {
+	.check_off_by_one = true,
+};
+
+static const struct amd_lps0_hid_device_data amd_cezanne = {
+	.check_off_by_one = false,
+};
+
+static const struct acpi_device_id amd_hid_ids[] = {
+	{"AMD0004",	(kernel_ulong_t)&amd_picasso,	},
+	{"AMD0005",	(kernel_ulong_t)&amd_picasso,	},
+	{"AMDI0005",	(kernel_ulong_t)&amd_picasso,	},
+	{"AMDI0006",	(kernel_ulong_t)&amd_cezanne,	},
+	{}
+};
+
+static int lps0_device_attach(struct acpi_device *adev,
+			      const struct acpi_device_id *not_used)
+{
+	if (lps0_device_handle)
+		return 0;
+
+	lps0_dsm_func_mask_microsoft = validate_dsm(adev->handle,
+						    ACPI_LPS0_DSM_UUID_MICROSOFT, 0,
+						    &lps0_dsm_guid_microsoft);
+	if (acpi_s2idle_vendor_amd()) {
+		static const struct acpi_device_id *dev_id;
+		const struct amd_lps0_hid_device_data *data;
+
+		for (dev_id = &amd_hid_ids[0]; dev_id->id[0]; dev_id++)
+			if (acpi_dev_hid_uid_match(adev, dev_id->id, NULL))
+				break;
+		if (dev_id->id[0])
+			data = (const struct amd_lps0_hid_device_data *) dev_id->driver_data;
+		else
+			data = &amd_cezanne;
+		lps0_dsm_func_mask = validate_dsm(adev->handle,
+					ACPI_LPS0_DSM_UUID_AMD, rev_id, &lps0_dsm_guid);
+		if (lps0_dsm_func_mask > 0x3 && data->check_off_by_one) {
+			lps0_dsm_func_mask = (lps0_dsm_func_mask << 1) | 0x1;
+			acpi_handle_debug(adev->handle, "_DSM UUID %s: Adjusted function mask: 0x%x\n",
+					  ACPI_LPS0_DSM_UUID_AMD, lps0_dsm_func_mask);
+		} else if (lps0_dsm_func_mask_microsoft > 0 && rev_id) {
+			lps0_dsm_func_mask_microsoft = -EINVAL;
+			acpi_handle_debug(adev->handle, "_DSM Using AMD method\n");
+		}
+	} else {
+		rev_id = 1;
+		lps0_dsm_func_mask = validate_dsm(adev->handle,
+					ACPI_LPS0_DSM_UUID, rev_id, &lps0_dsm_guid);
+		if (lps0_dsm_func_mask > 0 && lps0_dsm_func_mask_microsoft > 0) {
+			unsigned int func_mask;
+
+			/*
+			 * Log a message if the _DSM function sets for two
+			 * different UUIDs overlap.
+			 */
+			func_mask = lps0_dsm_func_mask & lps0_dsm_func_mask_microsoft;
+			if (func_mask)
+				acpi_handle_info(adev->handle,
+						 "Duplicate LPS0 _DSM functions (mask: 0x%x)\n",
+						 func_mask);
+		}
+	}
+
+	if (lps0_dsm_func_mask < 0 && lps0_dsm_func_mask_microsoft < 0)
+		return 0; //function evaluation failed
+
+	lps0_device_handle = adev->handle;
+
+	/*
+	 * Use suspend-to-idle by default if ACPI_FADT_LOW_POWER_S0 is set in
+	 * the FADT and the default suspend mode was not set from the command
+	 * line.
+	 */
+	if ((acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0) &&
+	    mem_sleep_default > PM_SUSPEND_MEM && !acpi_sleep_default_s3) {
+		mem_sleep_current = PM_SUSPEND_TO_IDLE;
+		pr_info("Low-power S0 idle used by default for system suspend\n");
+	}
+
+	/*
+	 * Some LPS0 systems, like ASUS Zenbook UX430UNR/i7-8550U, require the
+	 * EC GPE to be enabled while suspended for certain wakeup devices to
+	 * work, so mark it as wakeup-capable.
+	 */
+	acpi_ec_mark_gpe_for_wake();
+
+	return 0;
+}
+
+static struct acpi_scan_handler lps0_handler = {
+	.ids = lps0_device_ids,
+	.attach = lps0_device_attach,
+};
+
+static int acpi_s2idle_begin_lps0(void)
+{
+	if (pm_debug_messages_on && !lpi_constraints_table) {
+		if (acpi_s2idle_vendor_amd())
+			lpi_device_get_constraints_amd();
+		else
+			lpi_device_get_constraints();
+
+		/*
+		 * Try to retrieve the constraints only once because failures
+		 * to do so usually are sticky.
+		 */
+		if (!lpi_constraints_table)
+			lpi_constraints_table = ERR_PTR(-ENODATA);
+	}
+
+	return acpi_s2idle_begin();
+}
+
+static int acpi_s2idle_prepare_late_lps0(void)
+{
+	struct acpi_s2idle_dev_ops *handler;
+
+	if (!lps0_device_handle || sleep_no_lps0)
+		return 0;
+
+	if (pm_debug_messages_on)
+		lpi_check_constraints();
+
+	/* Screen off */
+	if (lps0_dsm_func_mask > 0)
+		acpi_sleep_run_lps0_dsm(acpi_s2idle_vendor_amd() ?
+					ACPI_LPS0_SCREEN_OFF_AMD :
+					ACPI_LPS0_SCREEN_OFF,
+					lps0_dsm_func_mask, lps0_dsm_guid);
+
+	if (lps0_dsm_func_mask_microsoft > 0)
+		acpi_sleep_run_lps0_dsm(ACPI_LPS0_SCREEN_OFF,
+				lps0_dsm_func_mask_microsoft, lps0_dsm_guid_microsoft);
+
+	/* LPS0 entry */
+	if (lps0_dsm_func_mask > 0 && acpi_s2idle_vendor_amd())
+		acpi_sleep_run_lps0_dsm(ACPI_LPS0_ENTRY_AMD,
+					lps0_dsm_func_mask, lps0_dsm_guid);
+
+	if (lps0_dsm_func_mask_microsoft > 0) {
+		/* Modern Standby entry */
+		acpi_sleep_run_lps0_dsm(ACPI_LPS0_MS_ENTRY,
+				lps0_dsm_func_mask_microsoft, lps0_dsm_guid_microsoft);
+		acpi_sleep_run_lps0_dsm(ACPI_LPS0_ENTRY,
+				lps0_dsm_func_mask_microsoft, lps0_dsm_guid_microsoft);
+	}
+
+	if (lps0_dsm_func_mask > 0 && !acpi_s2idle_vendor_amd())
+		acpi_sleep_run_lps0_dsm(ACPI_LPS0_ENTRY,
+					lps0_dsm_func_mask, lps0_dsm_guid);
+
+	list_for_each_entry(handler, &lps0_s2idle_devops_head, list_node) {
+		if (handler->prepare)
+			handler->prepare();
+	}
+
+	return 0;
+}
+
+static void acpi_s2idle_check_lps0(void)
+{
+	struct acpi_s2idle_dev_ops *handler;
+
+	if (!lps0_device_handle || sleep_no_lps0)
+		return;
+
+	list_for_each_entry(handler, &lps0_s2idle_devops_head, list_node) {
+		if (handler->check)
+			handler->check();
+	}
+}
+
+static void acpi_s2idle_restore_early_lps0(void)
+{
+	struct acpi_s2idle_dev_ops *handler;
+
+	if (!lps0_device_handle || sleep_no_lps0)
+		return;
+
+	list_for_each_entry(handler, &lps0_s2idle_devops_head, list_node)
+		if (handler->restore)
+			handler->restore();
+
+	/* LPS0 exit */
+	if (lps0_dsm_func_mask > 0)
+		acpi_sleep_run_lps0_dsm(acpi_s2idle_vendor_amd() ?
+					ACPI_LPS0_EXIT_AMD :
+					ACPI_LPS0_EXIT,
+					lps0_dsm_func_mask, lps0_dsm_guid);
+
+	if (lps0_dsm_func_mask_microsoft > 0) {
+		acpi_sleep_run_lps0_dsm(ACPI_LPS0_EXIT,
+				lps0_dsm_func_mask_microsoft, lps0_dsm_guid_microsoft);
+		/* Modern Standby exit */
+		acpi_sleep_run_lps0_dsm(ACPI_LPS0_MS_EXIT,
+				lps0_dsm_func_mask_microsoft, lps0_dsm_guid_microsoft);
+	}
+
+	/* Screen on */
+	if (lps0_dsm_func_mask_microsoft > 0)
+		acpi_sleep_run_lps0_dsm(ACPI_LPS0_SCREEN_ON,
+				lps0_dsm_func_mask_microsoft, lps0_dsm_guid_microsoft);
+	if (lps0_dsm_func_mask > 0)
+		acpi_sleep_run_lps0_dsm(acpi_s2idle_vendor_amd() ?
+					ACPI_LPS0_SCREEN_ON_AMD :
+					ACPI_LPS0_SCREEN_ON,
+					lps0_dsm_func_mask, lps0_dsm_guid);
+}
+
+static const struct platform_s2idle_ops acpi_s2idle_ops_lps0 = {
+	.begin = acpi_s2idle_begin_lps0,
+	.prepare = acpi_s2idle_prepare,
+	.prepare_late = acpi_s2idle_prepare_late_lps0,
+	.check = acpi_s2idle_check_lps0,
+	.wake = acpi_s2idle_wake,
+	.restore_early = acpi_s2idle_restore_early_lps0,
+	.restore = acpi_s2idle_restore,
+	.end = acpi_s2idle_end,
+};
+
+void __init acpi_s2idle_setup(void)
+{
+	acpi_scan_add_handler(&lps0_handler);
+	s2idle_set_ops(&acpi_s2idle_ops_lps0);
+}
+
+int acpi_register_lps0_dev(struct acpi_s2idle_dev_ops *arg)
+{
+	unsigned int sleep_flags;
+
+	if (!lps0_device_handle || sleep_no_lps0)
+		return -ENODEV;
+
+	sleep_flags = lock_system_sleep();
+	list_add(&arg->list_node, &lps0_s2idle_devops_head);
+	unlock_system_sleep(sleep_flags);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(acpi_register_lps0_dev);
+
+void acpi_unregister_lps0_dev(struct acpi_s2idle_dev_ops *arg)
+{
+	unsigned int sleep_flags;
+
+	if (!lps0_device_handle || sleep_no_lps0)
+		return;
+
+	sleep_flags = lock_system_sleep();
+	list_del(&arg->list_node);
+	unlock_system_sleep(sleep_flags);
+}
+EXPORT_SYMBOL_GPL(acpi_unregister_lps0_dev);
+
+#endif /* CONFIG_SUSPEND */
diff --git a/drivers/acpi/x86/utils.c b/drivers/acpi/x86/utils.c
index bdc1ba00aee9..4ee30c2897a2 100644
--- a/drivers/acpi/x86/utils.c
+++ b/drivers/acpi/x86/utils.c
@@ -8,8 +8,12 @@
  * Copyright (C) 2013-2015 Intel Corporation. All rights reserved.
  */
 
+#define pr_fmt(fmt) "ACPI: " fmt
+
 #include <linux/acpi.h>
 #include <linux/dmi.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
 #include <asm/cpu_device_id.h>
 #include <asm/intel-family.h>
 #include "../internal.h"
@@ -22,116 +26,630 @@
  * Some BIOS-es (temporarily) hide specific APCI devices to work around Windows
  * driver bugs. We use DMI matching to match known cases of this.
  *
- * We work around this by always reporting ACPI_STA_DEFAULT for these
- * devices. Note this MUST only be done for devices where this is safe.
+ * Likewise sometimes some not-actually present devices are sometimes
+ * reported as present, which may cause issues.
+ *
+ * We work around this by using the below quirk list to override the status
+ * reported by the _STA method with a fixed value (ACPI_STA_DEFAULT or 0).
+ * Note this MUST only be done for devices where this is safe.
  *
- * This forcing of devices to be present is limited to specific CPU (SoC)
- * models both to avoid potentially causing trouble on other models and
- * because some HIDs are re-used on different SoCs for completely
- * different devices.
+ * This status overriding is limited to specific CPU (SoC) models both to
+ * avoid potentially causing trouble on other models and because some HIDs
+ * are re-used on different SoCs for completely different devices.
  */
-struct always_present_id {
+struct override_status_id {
 	struct acpi_device_id hid[2];
 	struct x86_cpu_id cpu_ids[2];
 	struct dmi_system_id dmi_ids[2]; /* Optional */
 	const char *uid;
+	const char *path;
+	unsigned long long status;
 };
 
-#define X86_MATCH(model)	X86_MATCH_INTEL_FAM6_MODEL(model, NULL)
-
-#define ENTRY(hid, uid, cpu_models, dmi...) {				\
+#define ENTRY(status, hid, uid, path, cpu_vfm, dmi...) {		\
 	{ { hid, }, {} },						\
-	{ cpu_models, {} },						\
+	{ X86_MATCH_VFM(cpu_vfm, NULL), {} },				\
 	{ { .matches = dmi }, {} },					\
 	uid,								\
+	path,								\
+	status,								\
 }
 
-static const struct always_present_id always_present_ids[] = {
+#define PRESENT_ENTRY_HID(hid, uid, cpu_vfm, dmi...) \
+	ENTRY(ACPI_STA_DEFAULT, hid, uid, NULL, cpu_vfm, dmi)
+
+#define NOT_PRESENT_ENTRY_HID(hid, uid, cpu_vfm, dmi...) \
+	ENTRY(0, hid, uid, NULL, cpu_vfm, dmi)
+
+#define PRESENT_ENTRY_PATH(path, cpu_vfm, dmi...) \
+	ENTRY(ACPI_STA_DEFAULT, "", NULL, path, cpu_vfm, dmi)
+
+#define NOT_PRESENT_ENTRY_PATH(path, cpu_vfm, dmi...) \
+	ENTRY(0, "", NULL, path, cpu_vfm, dmi)
+
+static const struct override_status_id override_status_ids[] = {
 	/*
 	 * Bay / Cherry Trail PWM directly poked by GPU driver in win10,
 	 * but Linux uses a separate PWM driver, harmless if not used.
 	 */
-	ENTRY("80860F09", "1", X86_MATCH(ATOM_SILVERMONT), {}),
-	ENTRY("80862288", "1", X86_MATCH(ATOM_AIRMONT), {}),
+	PRESENT_ENTRY_HID("80860F09", "1", INTEL_ATOM_SILVERMONT, {}),
+	PRESENT_ENTRY_HID("80862288", "1", INTEL_ATOM_AIRMONT, {}),
+
+	/* The Xiaomi Mi Pad 2 uses PWM2 for touchkeys backlight control */
+	PRESENT_ENTRY_HID("80862289", "2", INTEL_ATOM_AIRMONT, {
+		DMI_MATCH(DMI_SYS_VENDOR, "Xiaomi Inc"),
+		DMI_MATCH(DMI_PRODUCT_NAME, "Mipad2"),
+	      }),
 
-	/* Lenovo Yoga Book uses PWM2 for keyboard backlight control */
-	ENTRY("80862289", "2", X86_MATCH(ATOM_AIRMONT), {
-			DMI_MATCH(DMI_PRODUCT_NAME, "Lenovo YB1-X9"),
-		}),
 	/*
 	 * The INT0002 device is necessary to clear wakeup interrupt sources
 	 * on Cherry Trail devices, without it we get nobody cared IRQ msgs.
 	 */
-	ENTRY("INT0002", "1", X86_MATCH(ATOM_AIRMONT), {}),
+	PRESENT_ENTRY_HID("INT0002", "1", INTEL_ATOM_AIRMONT, {}),
 	/*
 	 * On the Dell Venue 11 Pro 7130 and 7139, the DSDT hides
 	 * the touchscreen ACPI device until a certain time
 	 * after _SB.PCI0.GFX0.LCD.LCD1._ON gets called has passed
 	 * *and* _STA has been called at least 3 times since.
 	 */
-	ENTRY("SYNA7500", "1", X86_MATCH(HASWELL_L), {
+	PRESENT_ENTRY_HID("SYNA7500", "1", INTEL_HASWELL_L, {
 		DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 		DMI_MATCH(DMI_PRODUCT_NAME, "Venue 11 Pro 7130"),
 	      }),
-	ENTRY("SYNA7500", "1", X86_MATCH(HASWELL_L), {
+	PRESENT_ENTRY_HID("SYNA7500", "1", INTEL_HASWELL_L, {
 		DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 		DMI_MATCH(DMI_PRODUCT_NAME, "Venue 11 Pro 7139"),
 	      }),
 
 	/*
+	 * The Dell XPS 15 9550 has a SMO8110 accelerometer /
+	 * HDD freefall sensor which is wrongly marked as not present.
+	 */
+	PRESENT_ENTRY_HID("SMO8810", "1", INTEL_SKYLAKE, {
+		DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
+		DMI_MATCH(DMI_PRODUCT_NAME, "XPS 15 9550"),
+	      }),
+
+	/*
 	 * The GPD win BIOS dated 20170221 has disabled the accelerometer, the
 	 * drivers sometimes cause crashes under Windows and this is how the
-	 * manufacturer has solved this :| Note that the the DMI data is less
-	 * generic then it seems, a board_vendor of "AMI Corporation" is quite
-	 * rare and a board_name of "Default String" also is rare.
+	 * manufacturer has solved this :|  The DMI match may not seem unique,
+	 * but it is. In the 67000+ DMI decode dumps from linux-hardware.org
+	 * only 116 have board_vendor set to "AMI Corporation" and of those 116
+	 * only the GPD win and pocket entries' board_name is "Default string".
 	 *
 	 * Unfortunately the GPD pocket also uses these strings and its BIOS
 	 * was copy-pasted from the GPD win, so it has a disabled KIOX000A
 	 * node which we should not enable, thus we also check the BIOS date.
 	 */
-	ENTRY("KIOX000A", "1", X86_MATCH(ATOM_AIRMONT), {
+	PRESENT_ENTRY_HID("KIOX000A", "1", INTEL_ATOM_AIRMONT, {
 		DMI_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"),
 		DMI_MATCH(DMI_BOARD_NAME, "Default string"),
 		DMI_MATCH(DMI_PRODUCT_NAME, "Default string"),
 		DMI_MATCH(DMI_BIOS_DATE, "02/21/2017")
 	      }),
-	ENTRY("KIOX000A", "1", X86_MATCH(ATOM_AIRMONT), {
+	PRESENT_ENTRY_HID("KIOX000A", "1", INTEL_ATOM_AIRMONT, {
 		DMI_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"),
 		DMI_MATCH(DMI_BOARD_NAME, "Default string"),
 		DMI_MATCH(DMI_PRODUCT_NAME, "Default string"),
 		DMI_MATCH(DMI_BIOS_DATE, "03/20/2017")
 	      }),
-	ENTRY("KIOX000A", "1", X86_MATCH(ATOM_AIRMONT), {
+	PRESENT_ENTRY_HID("KIOX000A", "1", INTEL_ATOM_AIRMONT, {
 		DMI_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"),
 		DMI_MATCH(DMI_BOARD_NAME, "Default string"),
 		DMI_MATCH(DMI_PRODUCT_NAME, "Default string"),
 		DMI_MATCH(DMI_BIOS_DATE, "05/25/2017")
 	      }),
+
+	/*
+	 * The GPD win/pocket have a PCI wifi card, but its DSDT has the SDIO
+	 * mmc controller enabled and that has a child-device which _PS3
+	 * method sets a GPIO causing the PCI wifi card to turn off.
+	 * See above remark about uniqueness of the DMI match.
+	 */
+	NOT_PRESENT_ENTRY_PATH("\\_SB_.PCI0.SDHB.BRC1", INTEL_ATOM_AIRMONT, {
+		DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"),
+		DMI_EXACT_MATCH(DMI_BOARD_NAME, "Default string"),
+		DMI_EXACT_MATCH(DMI_BOARD_SERIAL, "Default string"),
+		DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Default string"),
+	      }),
+
+	/*
+	 * The LSM303D on the Lenovo Yoga Tablet 2 series is present
+	 * as both ACCL0001 and MAGN0001. As we can only ever register an
+	 * i2c client for one of them, ignore MAGN0001.
+	 */
+	NOT_PRESENT_ENTRY_HID("MAGN0001", "1", INTEL_ATOM_SILVERMONT, {
+		DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
+		DMI_MATCH(DMI_PRODUCT_FAMILY, "YOGATablet2"),
+	      }),
 };
 
-bool acpi_device_always_present(struct acpi_device *adev)
+bool acpi_device_override_status(struct acpi_device *adev, unsigned long long *status)
 {
 	bool ret = false;
 	unsigned int i;
 
-	for (i = 0; i < ARRAY_SIZE(always_present_ids); i++) {
-		if (acpi_match_device_ids(adev, always_present_ids[i].hid))
+	for (i = 0; i < ARRAY_SIZE(override_status_ids); i++) {
+		if (!x86_match_cpu(override_status_ids[i].cpu_ids))
 			continue;
 
-		if (!adev->pnp.unique_id ||
-		    strcmp(adev->pnp.unique_id, always_present_ids[i].uid))
+		if (override_status_ids[i].dmi_ids[0].matches[0].slot &&
+		    !dmi_check_system(override_status_ids[i].dmi_ids))
 			continue;
 
-		if (!x86_match_cpu(always_present_ids[i].cpu_ids))
-			continue;
+		if (override_status_ids[i].path) {
+			struct acpi_buffer path = { ACPI_ALLOCATE_BUFFER, NULL };
+			bool match;
 
-		if (always_present_ids[i].dmi_ids[0].matches[0].slot &&
-		    !dmi_check_system(always_present_ids[i].dmi_ids))
-			continue;
+			if (acpi_get_name(adev->handle, ACPI_FULL_PATHNAME, &path))
+				continue;
+
+			match = strcmp((char *)path.pointer, override_status_ids[i].path) == 0;
+			kfree(path.pointer);
+
+			if (!match)
+				continue;
+		} else {
+			if (acpi_match_device_ids(adev, override_status_ids[i].hid))
+				continue;
 
+			if (!acpi_dev_uid_match(adev, override_status_ids[i].uid))
+				continue;
+		}
+
+		*status = override_status_ids[i].status;
 		ret = true;
 		break;
 	}
 
 	return ret;
 }
+
+/*
+ * AMD systems from Renoir onwards *require* that the NVME controller
+ * is put into D3 over a Modern Standby / suspend-to-idle cycle.
+ *
+ * This is "typically" accomplished using the `StorageD3Enable`
+ * property in the _DSD that is checked via the `acpi_storage_d3` function
+ * but some OEM systems still don't have it in their BIOS.
+ *
+ * The Microsoft documentation for StorageD3Enable mentioned that Windows has
+ * a hardcoded allowlist for D3 support as well as a registry key to override
+ * the BIOS, which has been used for these cases.
+ *
+ * This allows quirking on Linux in a similar fashion.
+ *
+ * Cezanne systems shouldn't *normally* need this as the BIOS includes
+ * StorageD3Enable.  But for two reasons we have added it.
+ * 1) The BIOS on a number of Dell systems have ambiguity
+ *    between the same value used for _ADR on ACPI nodes GPP1.DEV0 and GPP1.NVME.
+ *    GPP1.NVME is needed to get StorageD3Enable node set properly.
+ *    https://bugzilla.kernel.org/show_bug.cgi?id=216440
+ *    https://bugzilla.kernel.org/show_bug.cgi?id=216773
+ *    https://bugzilla.kernel.org/show_bug.cgi?id=217003
+ * 2) On at least one HP system StorageD3Enable is missing on the second NVME
+ *    disk in the system.
+ * 3) On at least one HP Rembrandt system StorageD3Enable is missing on the only
+ *    NVME device.
+ */
+bool force_storage_d3(void)
+{
+	if (!cpu_feature_enabled(X86_FEATURE_ZEN))
+		return false;
+	return acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0;
+}
+
+/*
+ * x86 ACPI boards which ship with only Android as their factory image usually
+ * declare a whole bunch of bogus I2C devices in their ACPI tables and sometimes
+ * there are issues with serdev devices on these boards too, e.g. the resource
+ * points to the wrong serdev_controller.
+ *
+ * Instantiating I2C / serdev devs for these bogus devs causes various issues,
+ * e.g. GPIO/IRQ resource conflicts because sometimes drivers do bind to them.
+ * The Android x86 kernel fork shipped on these devices has some special code
+ * to remove the bogus I2C clients (and AFAICT serdevs are ignored completely).
+ *
+ * The acpi_quirk_skip_*_enumeration() functions below are used by the I2C or
+ * serdev code to skip instantiating any I2C or serdev devs on broken boards.
+ *
+ * In case of I2C an exception is made for HIDs on the i2c_acpi_known_good_ids
+ * list. These are known to always be correct (and in case of the audio-codecs
+ * the drivers heavily rely on the codec being enumerated through ACPI).
+ *
+ * Note these boards typically do actually have I2C and serdev devices,
+ * just different ones then the ones described in their DSDT. The devices
+ * which are actually present are manually instantiated by the
+ * drivers/platform/x86/x86-android-tablets.c kernel module.
+ */
+#define ACPI_QUIRK_SKIP_I2C_CLIENTS				BIT(0)
+#define ACPI_QUIRK_UART1_SKIP					BIT(1)
+#define ACPI_QUIRK_UART1_TTY_UART2_SKIP				BIT(2)
+#define ACPI_QUIRK_PNP_UART1_SKIP				BIT(3)
+#define ACPI_QUIRK_SKIP_ACPI_AC_AND_BATTERY			BIT(4)
+#define ACPI_QUIRK_USE_ACPI_AC_AND_BATTERY			BIT(5)
+#define ACPI_QUIRK_SKIP_GPIO_EVENT_HANDLERS			BIT(6)
+
+static const struct dmi_system_id acpi_quirk_skip_dmi_ids[] = {
+	/*
+	 * 1. Devices with only the skip / don't-skip AC and battery quirks,
+	 *    sorted alphabetically.
+	 */
+	{
+		/* ECS EF20EA, AXP288 PMIC but uses separate fuel-gauge */
+		.matches = {
+			DMI_MATCH(DMI_PRODUCT_NAME, "EF20EA"),
+		},
+		.driver_data = (void *)ACPI_QUIRK_USE_ACPI_AC_AND_BATTERY
+	},
+	{
+		/* Lenovo Ideapad Miix 320, AXP288 PMIC, separate fuel-gauge */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
+			DMI_MATCH(DMI_PRODUCT_NAME, "80XF"),
+			DMI_MATCH(DMI_PRODUCT_VERSION, "Lenovo MIIX 320-10ICR"),
+		},
+		.driver_data = (void *)ACPI_QUIRK_USE_ACPI_AC_AND_BATTERY
+	},
+
+	/*
+	 * 2. Devices which also have the skip i2c/serdev quirks and which
+	 *    need the x86-android-tablets module to properly work.
+	 *    Sorted alphabetically.
+	 */
+#if IS_ENABLED(CONFIG_X86_ANDROID_TABLETS)
+	{
+		/* Acer Iconia One 7 B1-750 */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "Insyde"),
+			DMI_MATCH(DMI_PRODUCT_NAME, "VESPA2"),
+		},
+		.driver_data = (void *)(ACPI_QUIRK_SKIP_I2C_CLIENTS |
+					ACPI_QUIRK_SKIP_ACPI_AC_AND_BATTERY |
+					ACPI_QUIRK_SKIP_GPIO_EVENT_HANDLERS),
+	},
+	{
+		/* Acer Iconia One 8 A1-840 (non FHD version) */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "Insyde"),
+			DMI_MATCH(DMI_PRODUCT_NAME, "BayTrail"),
+			/* Above strings are too generic also match BIOS date */
+			DMI_MATCH(DMI_BIOS_DATE, "04/01/2014"),
+		},
+		.driver_data = (void *)(ACPI_QUIRK_SKIP_I2C_CLIENTS |
+					ACPI_QUIRK_SKIP_ACPI_AC_AND_BATTERY |
+					ACPI_QUIRK_SKIP_GPIO_EVENT_HANDLERS),
+	},
+	{
+		/* Asus ME176C tablet */
+		.matches = {
+			DMI_EXACT_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
+			DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "ME176C"),
+		},
+		.driver_data = (void *)(ACPI_QUIRK_SKIP_I2C_CLIENTS |
+					ACPI_QUIRK_UART1_TTY_UART2_SKIP |
+					ACPI_QUIRK_SKIP_ACPI_AC_AND_BATTERY |
+					ACPI_QUIRK_SKIP_GPIO_EVENT_HANDLERS),
+	},
+	{
+		/* Asus TF103C transformer 2-in-1 */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
+			DMI_MATCH(DMI_PRODUCT_NAME, "TF103C"),
+		},
+		.driver_data = (void *)(ACPI_QUIRK_SKIP_I2C_CLIENTS |
+					ACPI_QUIRK_SKIP_ACPI_AC_AND_BATTERY |
+					ACPI_QUIRK_SKIP_GPIO_EVENT_HANDLERS),
+	},
+	{
+		/* Lenovo Yoga Book X90F/L */
+		.matches = {
+			DMI_EXACT_MATCH(DMI_SYS_VENDOR, "Intel Corporation"),
+			DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "CHERRYVIEW D1 PLATFORM"),
+			DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "YETI-11"),
+		},
+		.driver_data = (void *)(ACPI_QUIRK_SKIP_I2C_CLIENTS |
+					ACPI_QUIRK_UART1_SKIP |
+					ACPI_QUIRK_SKIP_ACPI_AC_AND_BATTERY |
+					ACPI_QUIRK_SKIP_GPIO_EVENT_HANDLERS),
+	},
+	{
+		/* Lenovo Yoga Tablet 2 1050F/L */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "Intel Corp."),
+			DMI_MATCH(DMI_PRODUCT_NAME, "VALLEYVIEW C0 PLATFORM"),
+			DMI_MATCH(DMI_BOARD_NAME, "BYT-T FFD8"),
+			/* Partial match on beginning of BIOS version */
+			DMI_MATCH(DMI_BIOS_VERSION, "BLADE_21"),
+		},
+		.driver_data = (void *)(ACPI_QUIRK_SKIP_I2C_CLIENTS |
+					ACPI_QUIRK_PNP_UART1_SKIP |
+					ACPI_QUIRK_SKIP_ACPI_AC_AND_BATTERY),
+	},
+	{
+		/* Lenovo Yoga Tab 3 Pro X90F */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "Intel Corporation"),
+			DMI_MATCH(DMI_PRODUCT_VERSION, "Blade3-10A-001"),
+		},
+		.driver_data = (void *)(ACPI_QUIRK_SKIP_I2C_CLIENTS |
+					ACPI_QUIRK_SKIP_ACPI_AC_AND_BATTERY |
+					ACPI_QUIRK_SKIP_GPIO_EVENT_HANDLERS),
+	},
+	{
+		/* Medion Lifetab S10346 */
+		.matches = {
+			DMI_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"),
+			DMI_MATCH(DMI_BOARD_NAME, "Aptio CRB"),
+			/* Way too generic, also match on BIOS data */
+			DMI_MATCH(DMI_BIOS_DATE, "10/22/2015"),
+		},
+		.driver_data = (void *)(ACPI_QUIRK_SKIP_I2C_CLIENTS |
+					ACPI_QUIRK_SKIP_ACPI_AC_AND_BATTERY),
+	},
+	{
+		/* Nextbook Ares 8 (BYT version)*/
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "Insyde"),
+			DMI_MATCH(DMI_PRODUCT_NAME, "M890BAP"),
+		},
+		.driver_data = (void *)(ACPI_QUIRK_SKIP_I2C_CLIENTS |
+					ACPI_QUIRK_SKIP_ACPI_AC_AND_BATTERY |
+					ACPI_QUIRK_SKIP_GPIO_EVENT_HANDLERS),
+	},
+	{
+		/* Nextbook Ares 8A (CHT version)*/
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "Insyde"),
+			DMI_MATCH(DMI_PRODUCT_NAME, "CherryTrail"),
+			DMI_MATCH(DMI_BIOS_VERSION, "M882"),
+		},
+		.driver_data = (void *)(ACPI_QUIRK_SKIP_I2C_CLIENTS |
+					ACPI_QUIRK_SKIP_ACPI_AC_AND_BATTERY),
+	},
+	{
+		/* Vexia Edu Atla 10 tablet 5V version */
+		.matches = {
+			/* Having all 3 of these not set is somewhat unique */
+			DMI_MATCH(DMI_SYS_VENDOR, "To be filled by O.E.M."),
+			DMI_MATCH(DMI_PRODUCT_NAME, "To be filled by O.E.M."),
+			DMI_MATCH(DMI_BOARD_NAME, "To be filled by O.E.M."),
+			/* Above strings are too generic, also match on BIOS date */
+			DMI_MATCH(DMI_BIOS_DATE, "05/14/2015"),
+		},
+		.driver_data = (void *)(ACPI_QUIRK_SKIP_I2C_CLIENTS |
+					ACPI_QUIRK_SKIP_ACPI_AC_AND_BATTERY),
+	},
+	{
+		/* Vexia Edu Atla 10 tablet 9V version */
+		.matches = {
+			DMI_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"),
+			DMI_MATCH(DMI_BOARD_NAME, "Aptio CRB"),
+			/* Above strings are too generic, also match on BIOS date */
+			DMI_MATCH(DMI_BIOS_DATE, "08/25/2014"),
+		},
+		.driver_data = (void *)(ACPI_QUIRK_SKIP_I2C_CLIENTS |
+					ACPI_QUIRK_UART1_SKIP |
+					ACPI_QUIRK_SKIP_ACPI_AC_AND_BATTERY |
+					ACPI_QUIRK_SKIP_GPIO_EVENT_HANDLERS),
+	},
+	{
+		/* Whitelabel (sold as various brands) TM800A550L */
+		.matches = {
+			DMI_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"),
+			DMI_MATCH(DMI_BOARD_NAME, "Aptio CRB"),
+			/* Above strings are too generic, also match on BIOS version */
+			DMI_MATCH(DMI_BIOS_VERSION, "ZY-8-BI-PX4S70VTR400-X423B-005-D"),
+		},
+		.driver_data = (void *)(ACPI_QUIRK_SKIP_I2C_CLIENTS |
+					ACPI_QUIRK_SKIP_ACPI_AC_AND_BATTERY),
+	},
+#endif
+	{}
+};
+
+#if IS_ENABLED(CONFIG_X86_ANDROID_TABLETS)
+static const struct acpi_device_id i2c_acpi_known_good_ids[] = {
+	{ "10EC5640", 0 }, /* RealTek ALC5640 audio codec */
+	{ "10EC5651", 0 }, /* RealTek ALC5651 audio codec */
+	{ "INT33F4", 0 },  /* X-Powers AXP288 PMIC */
+	{ "INT33F5", 0 },  /* TI Dollar Cove PMIC */
+	{ "INT33FD", 0 },  /* Intel Crystal Cove PMIC */
+	{ "INT34D3", 0 },  /* Intel Whiskey Cove PMIC */
+	{ "NPCE69A", 0 },  /* Asus Transformer keyboard dock */
+	{}
+};
+
+bool acpi_quirk_skip_i2c_client_enumeration(struct acpi_device *adev)
+{
+	const struct dmi_system_id *dmi_id;
+	long quirks;
+
+	dmi_id = dmi_first_match(acpi_quirk_skip_dmi_ids);
+	if (!dmi_id)
+		return false;
+
+	quirks = (unsigned long)dmi_id->driver_data;
+	if (!(quirks & ACPI_QUIRK_SKIP_I2C_CLIENTS))
+		return false;
+
+	return acpi_match_device_ids(adev, i2c_acpi_known_good_ids);
+}
+EXPORT_SYMBOL_GPL(acpi_quirk_skip_i2c_client_enumeration);
+
+static int acpi_dmi_skip_serdev_enumeration(struct device *controller_parent, bool *skip)
+{
+	struct acpi_device *adev = ACPI_COMPANION(controller_parent);
+	const struct dmi_system_id *dmi_id;
+	long quirks = 0;
+	u64 uid = 0;
+
+	dmi_id = dmi_first_match(acpi_quirk_skip_dmi_ids);
+	if (!dmi_id)
+		return 0;
+
+	quirks = (unsigned long)dmi_id->driver_data;
+
+	/* uid is left at 0 on errors and 0 is not a valid UART UID */
+	acpi_dev_uid_to_integer(adev, &uid);
+
+	/* For PCI UARTs without an UID */
+	if (!uid && dev_is_pci(controller_parent)) {
+		struct pci_dev *pdev = to_pci_dev(controller_parent);
+
+		/*
+		 * Devfn values for PCI UARTs on Bay Trail SoCs, which are
+		 * the only devices where this fallback is necessary.
+		 */
+		if (pdev->devfn == PCI_DEVFN(0x1e, 3))
+			uid = 1;
+		else if (pdev->devfn == PCI_DEVFN(0x1e, 4))
+			uid = 2;
+	}
+
+	if (!uid)
+		return 0;
+
+	if (!dev_is_platform(controller_parent) && !dev_is_pci(controller_parent)) {
+		/* PNP enumerated UARTs */
+		if ((quirks & ACPI_QUIRK_PNP_UART1_SKIP) && uid == 1)
+			*skip = true;
+
+		return 0;
+	}
+
+	if ((quirks & ACPI_QUIRK_UART1_SKIP) && uid == 1)
+		*skip = true;
+
+	if (quirks & ACPI_QUIRK_UART1_TTY_UART2_SKIP) {
+		if (uid == 1)
+			return -ENODEV; /* Create tty cdev instead of serdev */
+
+		if (uid == 2)
+			*skip = true;
+	}
+
+	return 0;
+}
+
+bool acpi_quirk_skip_gpio_event_handlers(void)
+{
+	const struct dmi_system_id *dmi_id;
+	long quirks;
+
+	dmi_id = dmi_first_match(acpi_quirk_skip_dmi_ids);
+	if (!dmi_id)
+		return false;
+
+	quirks = (unsigned long)dmi_id->driver_data;
+	return (quirks & ACPI_QUIRK_SKIP_GPIO_EVENT_HANDLERS);
+}
+EXPORT_SYMBOL_GPL(acpi_quirk_skip_gpio_event_handlers);
+#else
+static int acpi_dmi_skip_serdev_enumeration(struct device *controller_parent, bool *skip)
+{
+	return 0;
+}
+#endif
+
+int acpi_quirk_skip_serdev_enumeration(struct device *controller_parent, bool *skip)
+{
+	struct acpi_device *adev = ACPI_COMPANION(controller_parent);
+
+	*skip = false;
+
+	/*
+	 * The DELL0501 ACPI HID represents an UART (CID is set to PNP0501) with
+	 * a backlight-controller attached. There is no separate ACPI device with
+	 * an UartSerialBusV2() resource to model the backlight-controller.
+	 * Set skip to true so that the tty core creates a serdev ctrl device.
+	 * The backlight driver will manually create the serdev client device.
+	 */
+	if (adev && acpi_dev_hid_match(adev, "DELL0501")) {
+		*skip = true;
+		/*
+		 * Create a platform dev for dell-uart-backlight to bind to.
+		 * This is a static device, so no need to store the result.
+		 */
+		platform_device_register_simple("dell-uart-backlight", PLATFORM_DEVID_NONE,
+						NULL, 0);
+		return 0;
+	}
+
+	return acpi_dmi_skip_serdev_enumeration(controller_parent, skip);
+}
+EXPORT_SYMBOL_GPL(acpi_quirk_skip_serdev_enumeration);
+
+/* Lists of PMIC ACPI HIDs with an (often better) native charger driver */
+static const struct {
+	const char *hid;
+	int hrv;
+} acpi_skip_ac_and_battery_pmic_ids[] = {
+	{ "INT33F4", -1 }, /* X-Powers AXP288 PMIC */
+	{ "INT34D3",  3 }, /* Intel Cherrytrail Whiskey Cove PMIC */
+};
+
+bool acpi_quirk_skip_acpi_ac_and_battery(void)
+{
+	const struct dmi_system_id *dmi_id;
+	long quirks = 0;
+	int i;
+
+	dmi_id = dmi_first_match(acpi_quirk_skip_dmi_ids);
+	if (dmi_id)
+		quirks = (unsigned long)dmi_id->driver_data;
+
+	if (quirks & ACPI_QUIRK_SKIP_ACPI_AC_AND_BATTERY)
+		return true;
+
+	if (quirks & ACPI_QUIRK_USE_ACPI_AC_AND_BATTERY)
+		return false;
+
+	for (i = 0; i < ARRAY_SIZE(acpi_skip_ac_and_battery_pmic_ids); i++) {
+		if (acpi_dev_present(acpi_skip_ac_and_battery_pmic_ids[i].hid, "1",
+				     acpi_skip_ac_and_battery_pmic_ids[i].hrv)) {
+			pr_info_once("found native %s PMIC, skipping ACPI AC and battery devices\n",
+				     acpi_skip_ac_and_battery_pmic_ids[i].hid);
+			return true;
+		}
+	}
+
+	return false;
+}
+EXPORT_SYMBOL_GPL(acpi_quirk_skip_acpi_ac_and_battery);
+
+/* This section provides a workaround for a specific x86 system
+ * which requires disabling of mwait to work correctly.
+ */
+static int __init acpi_proc_quirk_set_no_mwait(const struct dmi_system_id *id)
+{
+	pr_notice("%s detected - disabling mwait for CPU C-states\n",
+		  id->ident);
+	boot_option_idle_override = IDLE_NOMWAIT;
+	return 0;
+}
+
+static const struct dmi_system_id acpi_proc_quirk_mwait_dmi_table[] __initconst = {
+	{
+		.callback = acpi_proc_quirk_set_no_mwait,
+		.ident = "Extensa 5220",
+		.matches =  {
+			DMI_MATCH(DMI_BIOS_VENDOR, "Phoenix Technologies LTD"),
+			DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
+			DMI_MATCH(DMI_PRODUCT_VERSION, "0100"),
+			DMI_MATCH(DMI_BOARD_NAME, "Columbia"),
+		},
+		.driver_data = NULL,
+	},
+	{}
+};
+
+void __init acpi_proc_quirk_mwait_check(void)
+{
+	/*
+	 * Check whether the system is DMI table. If yes, OSPM
+	 * should not use mwait for CPU-states.
+	 */
+	dmi_check_system(acpi_proc_quirk_mwait_dmi_table);
+}
diff --git a/drivers/amba/Kconfig b/drivers/amba/Kconfig
index fb6c7e0b4cce..14bb61ff801e 100644
--- a/drivers/amba/Kconfig
+++ b/drivers/amba/Kconfig
@@ -5,7 +5,7 @@ config ARM_AMBA
 if ARM_AMBA
 
 config TEGRA_AHB
-	bool
+	bool "Enable AHB driver for NVIDIA Tegra SoCs" if COMPILE_TEST
 	default y if ARCH_TEGRA
 	help
 	  Adds AHB configuration functionality for NVIDIA Tegra SoCs,
diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c
index fe1523664816..952c45ca6e48 100644
--- a/drivers/amba/bus.c
+++ b/drivers/amba/bus.c
@@ -18,11 +18,15 @@
 #include <linux/limits.h>
 #include <linux/clk/clk-conf.h>
 #include <linux/platform_device.h>
+#include <linux/property.h>
 #include <linux/reset.h>
+#include <linux/of_irq.h>
+#include <linux/of_device.h>
+#include <linux/acpi.h>
+#include <linux/iommu.h>
+#include <linux/dma-map-ops.h>
 
-#include <asm/irq.h>
-
-#define to_amba_driver(d)	container_of(d, struct amba_driver, drv)
+#define to_amba_driver(d)	container_of_const(d, struct amba_driver, drv)
 
 /* called on periphid match and class 0x9 coresight device. */
 static int
@@ -56,31 +60,28 @@ amba_lookup(const struct amba_id *table, struct amba_device *dev)
 	return NULL;
 }
 
-static int amba_match(struct device *dev, struct device_driver *drv)
+static int amba_get_enable_pclk(struct amba_device *pcdev)
 {
-	struct amba_device *pcdev = to_amba_device(dev);
-	struct amba_driver *pcdrv = to_amba_driver(drv);
+	int ret;
 
-	/* When driver_override is set, only bind to the matching driver */
-	if (pcdev->driver_override)
-		return !strcmp(pcdev->driver_override, drv->name);
+	pcdev->pclk = clk_get(&pcdev->dev, "apb_pclk");
+	if (IS_ERR(pcdev->pclk))
+		return PTR_ERR(pcdev->pclk);
 
-	return amba_lookup(pcdrv->id_table, pcdev) != NULL;
+	ret = clk_prepare_enable(pcdev->pclk);
+	if (ret)
+		clk_put(pcdev->pclk);
+
+	return ret;
 }
 
-static int amba_uevent(struct device *dev, struct kobj_uevent_env *env)
+static void amba_put_disable_pclk(struct amba_device *pcdev)
 {
-	struct amba_device *pcdev = to_amba_device(dev);
-	int retval = 0;
-
-	retval = add_uevent_var(env, "AMBA_ID=%08x", pcdev->periphid);
-	if (retval)
-		return retval;
-
-	retval = add_uevent_var(env, "MODALIAS=amba:d%08X", pcdev->periphid);
-	return retval;
+	clk_disable_unprepare(pcdev->pclk);
+	clk_put(pcdev->pclk);
 }
 
+
 static ssize_t driver_override_show(struct device *_dev,
 				    struct device_attribute *attr, char *buf)
 {
@@ -98,31 +99,11 @@ static ssize_t driver_override_store(struct device *_dev,
 				     const char *buf, size_t count)
 {
 	struct amba_device *dev = to_amba_device(_dev);
-	char *driver_override, *old, *cp;
-
-	/* We need to keep extra room for a newline */
-	if (count >= (PAGE_SIZE - 1))
-		return -EINVAL;
-
-	driver_override = kstrndup(buf, count, GFP_KERNEL);
-	if (!driver_override)
-		return -ENOMEM;
-
-	cp = strchr(driver_override, '\n');
-	if (cp)
-		*cp = '\0';
-
-	device_lock(_dev);
-	old = dev->driver_override;
-	if (strlen(driver_override)) {
-		dev->driver_override = driver_override;
-	} else {
-		kfree(driver_override);
-		dev->driver_override = NULL;
-	}
-	device_unlock(_dev);
+	int ret;
 
-	kfree(old);
+	ret = driver_set_override(_dev, &dev->driver_override, buf, count);
+	if (ret)
+		return ret;
 
 	return count;
 }
@@ -138,8 +119,6 @@ static ssize_t name##_show(struct device *_dev,				\
 static DEVICE_ATTR_RO(name)
 
 amba_attr_func(id, "%08x\n", dev->periphid);
-amba_attr_func(irq0, "%u\n", dev->irq[0]);
-amba_attr_func(irq1, "%u\n", dev->irq[1]);
 amba_attr_func(resource, "\t%016llx\t%016llx\t%016lx\n",
 	 (unsigned long long)dev->res.start, (unsigned long long)dev->res.end,
 	 dev->res.flags);
@@ -152,102 +131,144 @@ static struct attribute *amba_dev_attrs[] = {
 };
 ATTRIBUTE_GROUPS(amba_dev);
 
-#ifdef CONFIG_PM
-/*
- * Hooks to provide runtime PM of the pclk (bus clock).  It is safe to
- * enable/disable the bus clock at runtime PM suspend/resume as this
- * does not result in loss of context.
- */
-static int amba_pm_runtime_suspend(struct device *dev)
+static int amba_read_periphid(struct amba_device *dev)
 {
-	struct amba_device *pcdev = to_amba_device(dev);
-	int ret = pm_generic_runtime_suspend(dev);
+	struct reset_control *rstc;
+	u32 size, pid, cid;
+	void __iomem *tmp;
+	int i, ret;
 
-	if (ret == 0 && dev->driver) {
-		if (pm_runtime_is_irq_safe(dev))
-			clk_disable(pcdev->pclk);
-		else
-			clk_disable_unprepare(pcdev->pclk);
+	ret = dev_pm_domain_attach(&dev->dev, PD_FLAG_ATTACH_POWER_ON);
+	if (ret) {
+		dev_dbg(&dev->dev, "can't get PM domain: %d\n", ret);
+		goto err_out;
+	}
+
+	ret = amba_get_enable_pclk(dev);
+	if (ret) {
+		dev_dbg(&dev->dev, "can't get pclk: %d\n", ret);
+		goto err_pm;
+	}
+
+	/*
+	 * Find reset control(s) of the amba bus and de-assert them.
+	 */
+	rstc = of_reset_control_array_get_optional_shared(dev->dev.of_node);
+	if (IS_ERR(rstc)) {
+		ret = PTR_ERR(rstc);
+		if (ret != -EPROBE_DEFER)
+			dev_err(&dev->dev, "can't get reset: %d\n", ret);
+		goto err_clk;
 	}
+	reset_control_deassert(rstc);
+	reset_control_put(rstc);
 
+	size = resource_size(&dev->res);
+	tmp = ioremap(dev->res.start, size);
+	if (!tmp) {
+		ret = -ENOMEM;
+		goto err_clk;
+	}
+
+	/*
+	 * Read pid and cid based on size of resource
+	 * they are located at end of region
+	 */
+	for (pid = 0, i = 0; i < 4; i++)
+		pid |= (readl(tmp + size - 0x20 + 4 * i) & 255) << (i * 8);
+	for (cid = 0, i = 0; i < 4; i++)
+		cid |= (readl(tmp + size - 0x10 + 4 * i) & 255) << (i * 8);
+
+	if (cid == CORESIGHT_CID) {
+		/* set the base to the start of the last 4k block */
+		void __iomem *csbase = tmp + size - 4096;
+
+		dev->uci.devarch = readl(csbase + UCI_REG_DEVARCH_OFFSET);
+		dev->uci.devtype = readl(csbase + UCI_REG_DEVTYPE_OFFSET) & 0xff;
+	}
+
+	if (cid == AMBA_CID || cid == CORESIGHT_CID) {
+		dev->periphid = pid;
+		dev->cid = cid;
+	}
+
+	if (!dev->periphid)
+		ret = -ENODEV;
+
+	iounmap(tmp);
+
+err_clk:
+	amba_put_disable_pclk(dev);
+err_pm:
+	dev_pm_domain_detach(&dev->dev, true);
+err_out:
 	return ret;
 }
 
-static int amba_pm_runtime_resume(struct device *dev)
+static int amba_match(struct device *dev, const struct device_driver *drv)
 {
 	struct amba_device *pcdev = to_amba_device(dev);
-	int ret;
+	const struct amba_driver *pcdrv = to_amba_driver(drv);
 
-	if (dev->driver) {
-		if (pm_runtime_is_irq_safe(dev))
-			ret = clk_enable(pcdev->pclk);
-		else
-			ret = clk_prepare_enable(pcdev->pclk);
-		/* Failure is probably fatal to the system, but... */
-		if (ret)
-			return ret;
+	mutex_lock(&pcdev->periphid_lock);
+	if (!pcdev->periphid) {
+		int ret = amba_read_periphid(pcdev);
+
+		/*
+		 * Returning any error other than -EPROBE_DEFER from bus match
+		 * can cause driver registration failure. So, if there's a
+		 * permanent failure in reading pid and cid, simply map it to
+		 * -EPROBE_DEFER.
+		 */
+		if (ret) {
+			mutex_unlock(&pcdev->periphid_lock);
+			return -EPROBE_DEFER;
+		}
+		dev_set_uevent_suppress(dev, false);
+		kobject_uevent(&dev->kobj, KOBJ_ADD);
 	}
+	mutex_unlock(&pcdev->periphid_lock);
 
-	return pm_generic_runtime_resume(dev);
+	/* When driver_override is set, only bind to the matching driver */
+	if (pcdev->driver_override)
+		return !strcmp(pcdev->driver_override, drv->name);
+
+	return amba_lookup(pcdrv->id_table, pcdev) != NULL;
 }
-#endif /* CONFIG_PM */
 
-static const struct dev_pm_ops amba_pm = {
-	.suspend	= pm_generic_suspend,
-	.resume		= pm_generic_resume,
-	.freeze		= pm_generic_freeze,
-	.thaw		= pm_generic_thaw,
-	.poweroff	= pm_generic_poweroff,
-	.restore	= pm_generic_restore,
-	SET_RUNTIME_PM_OPS(
-		amba_pm_runtime_suspend,
-		amba_pm_runtime_resume,
-		NULL
-	)
-};
+static int amba_uevent(const struct device *dev, struct kobj_uevent_env *env)
+{
+	const struct amba_device *pcdev = to_amba_device(dev);
+	int retval = 0;
 
-/*
- * Primecells are part of the Advanced Microcontroller Bus Architecture,
- * so we call the bus "amba".
- * DMA configuration for platform and AMBA bus is same. So here we reuse
- * platform's DMA config routine.
- */
-struct bus_type amba_bustype = {
-	.name		= "amba",
-	.dev_groups	= amba_dev_groups,
-	.match		= amba_match,
-	.uevent		= amba_uevent,
-	.dma_configure	= platform_dma_configure,
-	.pm		= &amba_pm,
-};
-EXPORT_SYMBOL_GPL(amba_bustype);
+	retval = add_uevent_var(env, "AMBA_ID=%08x", pcdev->periphid);
+	if (retval)
+		return retval;
 
-static int __init amba_init(void)
-{
-	return bus_register(&amba_bustype);
+	retval = add_uevent_var(env, "MODALIAS=amba:d%08X", pcdev->periphid);
+	return retval;
 }
 
-postcore_initcall(amba_init);
-
-static int amba_get_enable_pclk(struct amba_device *pcdev)
+static int of_amba_device_decode_irq(struct amba_device *dev)
 {
-	int ret;
+	struct device_node *node = dev->dev.of_node;
+	int i, irq = 0;
 
-	pcdev->pclk = clk_get(&pcdev->dev, "apb_pclk");
-	if (IS_ERR(pcdev->pclk))
-		return PTR_ERR(pcdev->pclk);
-
-	ret = clk_prepare_enable(pcdev->pclk);
-	if (ret)
-		clk_put(pcdev->pclk);
+	if (IS_ENABLED(CONFIG_OF_IRQ) && node) {
+		/* Decode the IRQs and address ranges */
+		for (i = 0; i < AMBA_NR_IRQS; i++) {
+			irq = of_irq_get(node, i);
+			if (irq < 0) {
+				if (irq == -EPROBE_DEFER)
+					return irq;
+				irq = 0;
+			}
 
-	return ret;
-}
+			dev->irq[i] = irq;
+		}
+	}
 
-static void amba_put_disable_pclk(struct amba_device *pcdev)
-{
-	clk_disable_unprepare(pcdev->pclk);
-	clk_put(pcdev->pclk);
+	return 0;
 }
 
 /*
@@ -262,19 +283,22 @@ static int amba_probe(struct device *dev)
 	int ret;
 
 	do {
+		ret = of_amba_device_decode_irq(pcdev);
+		if (ret)
+			break;
+
 		ret = of_clk_set_defaults(dev->of_node, false);
 		if (ret < 0)
 			break;
 
-		ret = dev_pm_domain_attach(dev, true);
+		ret = dev_pm_domain_attach(dev, PD_FLAG_ATTACH_POWER_ON |
+						PD_FLAG_DETACH_POWER_OFF);
 		if (ret)
 			break;
 
 		ret = amba_get_enable_pclk(pcdev);
-		if (ret) {
-			dev_pm_domain_detach(dev, true);
+		if (ret)
 			break;
-		}
 
 		pm_runtime_get_noresume(dev);
 		pm_runtime_set_active(dev);
@@ -289,20 +313,19 @@ static int amba_probe(struct device *dev)
 		pm_runtime_put_noidle(dev);
 
 		amba_put_disable_pclk(pcdev);
-		dev_pm_domain_detach(dev, true);
 	} while (0);
 
 	return ret;
 }
 
-static int amba_remove(struct device *dev)
+static void amba_remove(struct device *dev)
 {
 	struct amba_device *pcdev = to_amba_device(dev);
 	struct amba_driver *drv = to_amba_driver(dev->driver);
-	int ret;
 
 	pm_runtime_get_sync(dev);
-	ret = drv->remove(pcdev);
+	if (drv->remove)
+		drv->remove(pcdev);
 	pm_runtime_put_noidle(dev);
 
 	/* Undo the runtime PM settings in amba_probe() */
@@ -311,221 +334,213 @@ static int amba_remove(struct device *dev)
 	pm_runtime_put_noidle(dev);
 
 	amba_put_disable_pclk(pcdev);
-	dev_pm_domain_detach(dev, true);
-
-	return ret;
 }
 
 static void amba_shutdown(struct device *dev)
 {
-	struct amba_driver *drv = to_amba_driver(dev->driver);
-	drv->shutdown(to_amba_device(dev));
-}
-
-/**
- *	amba_driver_register - register an AMBA device driver
- *	@drv: amba device driver structure
- *
- *	Register an AMBA device driver with the Linux device model
- *	core.  If devices pre-exist, the drivers probe function will
- *	be called.
- */
-int amba_driver_register(struct amba_driver *drv)
-{
-	drv->drv.bus = &amba_bustype;
+	struct amba_driver *drv;
 
-#define SETFN(fn)	if (drv->fn) drv->drv.fn = amba_##fn
-	SETFN(probe);
-	SETFN(remove);
-	SETFN(shutdown);
+	if (!dev->driver)
+		return;
 
-	return driver_register(&drv->drv);
+	drv = to_amba_driver(dev->driver);
+	if (drv->shutdown)
+		drv->shutdown(to_amba_device(dev));
 }
 
-/**
- *	amba_driver_unregister - remove an AMBA device driver
- *	@drv: AMBA device driver structure to remove
- *
- *	Unregister an AMBA device driver from the Linux device
- *	model.  The device model will call the drivers remove function
- *	for each device the device driver is currently handling.
- */
-void amba_driver_unregister(struct amba_driver *drv)
+static int amba_dma_configure(struct device *dev)
 {
-	driver_unregister(&drv->drv);
-}
+	struct amba_driver *drv = to_amba_driver(dev->driver);
+	enum dev_dma_attr attr;
+	int ret = 0;
 
+	if (dev->of_node) {
+		ret = of_dma_configure(dev, dev->of_node, true);
+	} else if (has_acpi_companion(dev)) {
+		attr = acpi_get_dma_attr(to_acpi_device_node(dev->fwnode));
+		ret = acpi_dma_configure(dev, attr);
+	}
 
-static void amba_device_release(struct device *dev)
-{
-	struct amba_device *d = to_amba_device(dev);
+	/* @drv may not be valid when we're called from the IOMMU layer */
+	if (!ret && dev->driver && !drv->driver_managed_dma) {
+		ret = iommu_device_use_default_domain(dev);
+		if (ret)
+			arch_teardown_dma_ops(dev);
+	}
 
-	if (d->res.parent)
-		release_resource(&d->res);
-	kfree(d);
+	return ret;
 }
 
-static int amba_device_try_add(struct amba_device *dev, struct resource *parent)
+static void amba_dma_cleanup(struct device *dev)
 {
-	u32 size;
-	void __iomem *tmp;
-	int i, ret;
-
-	WARN_ON(dev->irq[0] == (unsigned int)-1);
-	WARN_ON(dev->irq[1] == (unsigned int)-1);
-
-	ret = request_resource(parent, &dev->res);
-	if (ret)
-		goto err_out;
+	struct amba_driver *drv = to_amba_driver(dev->driver);
 
-	/* Hard-coded primecell ID instead of plug-n-play */
-	if (dev->periphid != 0)
-		goto skip_probe;
+	if (!drv->driver_managed_dma)
+		iommu_device_unuse_default_domain(dev);
+}
 
-	/*
-	 * Dynamically calculate the size of the resource
-	 * and use this for iomap
-	 */
-	size = resource_size(&dev->res);
-	tmp = ioremap(dev->res.start, size);
-	if (!tmp) {
-		ret = -ENOMEM;
-		goto err_release;
-	}
+#ifdef CONFIG_PM
+/*
+ * Hooks to provide runtime PM of the pclk (bus clock).  It is safe to
+ * enable/disable the bus clock at runtime PM suspend/resume as this
+ * does not result in loss of context.
+ */
+static int amba_pm_runtime_suspend(struct device *dev)
+{
+	struct amba_device *pcdev = to_amba_device(dev);
+	int ret = pm_generic_runtime_suspend(dev);
 
-	ret = dev_pm_domain_attach(&dev->dev, true);
-	if (ret) {
-		iounmap(tmp);
-		goto err_release;
+	if (ret == 0 && dev->driver) {
+		if (pm_runtime_is_irq_safe(dev))
+			clk_disable(pcdev->pclk);
+		else
+			clk_disable_unprepare(pcdev->pclk);
 	}
 
-	ret = amba_get_enable_pclk(dev);
-	if (ret == 0) {
-		u32 pid, cid;
-		struct reset_control *rstc;
-
-		/*
-		 * Find reset control(s) of the amba bus and de-assert them.
-		 */
-		rstc = of_reset_control_array_get_optional_shared(dev->dev.of_node);
-		if (IS_ERR(rstc)) {
-			ret = PTR_ERR(rstc);
-			if (ret != -EPROBE_DEFER)
-				dev_err(&dev->dev, "can't get reset: %d\n",
-					ret);
-			goto err_reset;
-		}
-		reset_control_deassert(rstc);
-		reset_control_put(rstc);
-
-		/*
-		 * Read pid and cid based on size of resource
-		 * they are located at end of region
-		 */
-		for (pid = 0, i = 0; i < 4; i++)
-			pid |= (readl(tmp + size - 0x20 + 4 * i) & 255) <<
-				(i * 8);
-		for (cid = 0, i = 0; i < 4; i++)
-			cid |= (readl(tmp + size - 0x10 + 4 * i) & 255) <<
-				(i * 8);
-
-		if (cid == CORESIGHT_CID) {
-			/* set the base to the start of the last 4k block */
-			void __iomem *csbase = tmp + size - 4096;
-
-			dev->uci.devarch =
-				readl(csbase + UCI_REG_DEVARCH_OFFSET);
-			dev->uci.devtype =
-				readl(csbase + UCI_REG_DEVTYPE_OFFSET) & 0xff;
-		}
-
-		amba_put_disable_pclk(dev);
+	return ret;
+}
 
-		if (cid == AMBA_CID || cid == CORESIGHT_CID) {
-			dev->periphid = pid;
-			dev->cid = cid;
-		}
+static int amba_pm_runtime_resume(struct device *dev)
+{
+	struct amba_device *pcdev = to_amba_device(dev);
+	int ret;
 
-		if (!dev->periphid)
-			ret = -ENODEV;
+	if (dev->driver) {
+		if (pm_runtime_is_irq_safe(dev))
+			ret = clk_enable(pcdev->pclk);
+		else
+			ret = clk_prepare_enable(pcdev->pclk);
+		/* Failure is probably fatal to the system, but... */
+		if (ret)
+			return ret;
 	}
 
-	iounmap(tmp);
-	dev_pm_domain_detach(&dev->dev, true);
+	return pm_generic_runtime_resume(dev);
+}
+#endif /* CONFIG_PM */
 
-	if (ret)
-		goto err_release;
+static const struct dev_pm_ops amba_pm = {
+	SET_RUNTIME_PM_OPS(
+		amba_pm_runtime_suspend,
+		amba_pm_runtime_resume,
+		NULL
+	)
+};
 
- skip_probe:
-	ret = device_add(&dev->dev);
-	if (ret)
-		goto err_release;
+/*
+ * Primecells are part of the Advanced Microcontroller Bus Architecture,
+ * so we call the bus "amba".
+ * DMA configuration for platform and AMBA bus is same. So here we reuse
+ * platform's DMA config routine.
+ */
+const struct bus_type amba_bustype = {
+	.name		= "amba",
+	.dev_groups	= amba_dev_groups,
+	.match		= amba_match,
+	.uevent		= amba_uevent,
+	.probe		= amba_probe,
+	.remove		= amba_remove,
+	.shutdown	= amba_shutdown,
+	.dma_configure	= amba_dma_configure,
+	.dma_cleanup	= amba_dma_cleanup,
+	.pm		= &amba_pm,
+};
+EXPORT_SYMBOL_GPL(amba_bustype);
 
-	if (dev->irq[0])
-		ret = device_create_file(&dev->dev, &dev_attr_irq0);
-	if (ret == 0 && dev->irq[1])
-		ret = device_create_file(&dev->dev, &dev_attr_irq1);
-	if (ret == 0)
-		return ret;
+bool dev_is_amba(const struct device *dev)
+{
+	return dev->bus == &amba_bustype;
+}
+EXPORT_SYMBOL_GPL(dev_is_amba);
 
-	device_unregister(&dev->dev);
+static int __init amba_init(void)
+{
+	return bus_register(&amba_bustype);
+}
 
- err_release:
-	release_resource(&dev->res);
- err_out:
-	return ret;
+postcore_initcall(amba_init);
 
- err_reset:
-	amba_put_disable_pclk(dev);
-	iounmap(tmp);
-	dev_pm_domain_detach(&dev->dev, true);
-	goto err_release;
+static int amba_proxy_probe(struct amba_device *adev,
+			    const struct amba_id *id)
+{
+	WARN(1, "Stub driver should never match any device.\n");
+	return -ENODEV;
 }
 
-/*
- * Registration of AMBA device require reading its pid and cid registers.
- * To do this, the device must be turned on (if it is a part of power domain)
- * and have clocks enabled. However in some cases those resources might not be
- * yet available. Returning EPROBE_DEFER is not a solution in such case,
- * because callers don't handle this special error code. Instead such devices
- * are added to the special list and their registration is retried from
- * periodic worker, until all resources are available and registration succeeds.
- */
-struct deferred_device {
-	struct amba_device *dev;
-	struct resource *parent;
-	struct list_head node;
+static const struct amba_id amba_stub_drv_ids[] = {
+	{ 0, 0 },
 };
 
-static LIST_HEAD(deferred_devices);
-static DEFINE_MUTEX(deferred_devices_lock);
+static struct amba_driver amba_proxy_drv = {
+	.drv = {
+		.name = "amba-proxy",
+	},
+	.probe = amba_proxy_probe,
+	.id_table = amba_stub_drv_ids,
+};
 
-static void amba_deferred_retry_func(struct work_struct *dummy);
-static DECLARE_DELAYED_WORK(deferred_retry_work, amba_deferred_retry_func);
+static int __init amba_stub_drv_init(void)
+{
+	if (!IS_ENABLED(CONFIG_MODULES))
+		return 0;
 
-#define DEFERRED_DEVICE_TIMEOUT (msecs_to_jiffies(5 * 1000))
+	/*
+	 * The amba_match() function will get called only if there is at least
+	 * one amba driver registered. If all amba drivers are modules and are
+	 * only loaded based on uevents, then we'll hit a chicken-and-egg
+	 * situation where amba_match() is waiting on drivers and drivers are
+	 * waiting on amba_match(). So, register a stub driver to make sure
+	 * amba_match() is called even if no amba driver has been registered.
+	 */
+	return __amba_driver_register(&amba_proxy_drv, NULL);
+}
+late_initcall_sync(amba_stub_drv_init);
 
-static void amba_deferred_retry_func(struct work_struct *dummy)
+/**
+ *	__amba_driver_register - register an AMBA device driver
+ *	@drv: amba device driver structure
+ *	@owner: owning module/driver
+ *
+ *	Register an AMBA device driver with the Linux device model
+ *	core.  If devices pre-exist, the drivers probe function will
+ *	be called.
+ */
+int __amba_driver_register(struct amba_driver *drv,
+			   struct module *owner)
 {
-	struct deferred_device *ddev, *tmp;
-
-	mutex_lock(&deferred_devices_lock);
+	if (!drv->probe)
+		return -EINVAL;
 
-	list_for_each_entry_safe(ddev, tmp, &deferred_devices, node) {
-		int ret = amba_device_try_add(ddev->dev, ddev->parent);
+	drv->drv.owner = owner;
+	drv->drv.bus = &amba_bustype;
 
-		if (ret == -EPROBE_DEFER)
-			continue;
+	return driver_register(&drv->drv);
+}
+EXPORT_SYMBOL(__amba_driver_register);
 
-		list_del_init(&ddev->node);
-		kfree(ddev);
-	}
+/**
+ *	amba_driver_unregister - remove an AMBA device driver
+ *	@drv: AMBA device driver structure to remove
+ *
+ *	Unregister an AMBA device driver from the Linux device
+ *	model.  The device model will call the drivers remove function
+ *	for each device the device driver is currently handling.
+ */
+void amba_driver_unregister(struct amba_driver *drv)
+{
+	driver_unregister(&drv->drv);
+}
+EXPORT_SYMBOL(amba_driver_unregister);
 
-	if (!list_empty(&deferred_devices))
-		schedule_delayed_work(&deferred_retry_work,
-				      DEFERRED_DEVICE_TIMEOUT);
+static void amba_device_release(struct device *dev)
+{
+	struct amba_device *d = to_amba_device(dev);
 
-	mutex_unlock(&deferred_devices_lock);
+	fwnode_handle_put(dev_fwnode(&d->dev));
+	if (d->res.parent)
+		release_resource(&d->res);
+	mutex_destroy(&d->periphid_lock);
+	kfree(d);
 }
 
 /**
@@ -539,103 +554,35 @@ static void amba_deferred_retry_func(struct work_struct *dummy)
  */
 int amba_device_add(struct amba_device *dev, struct resource *parent)
 {
-	int ret = amba_device_try_add(dev, parent);
-
-	if (ret == -EPROBE_DEFER) {
-		struct deferred_device *ddev;
-
-		ddev = kmalloc(sizeof(*ddev), GFP_KERNEL);
-		if (!ddev)
-			return -ENOMEM;
-
-		ddev->dev = dev;
-		ddev->parent = parent;
-		ret = 0;
-
-		mutex_lock(&deferred_devices_lock);
-
-		if (list_empty(&deferred_devices))
-			schedule_delayed_work(&deferred_retry_work,
-					      DEFERRED_DEVICE_TIMEOUT);
-		list_add_tail(&ddev->node, &deferred_devices);
-
-		mutex_unlock(&deferred_devices_lock);
-	}
-	return ret;
-}
-EXPORT_SYMBOL_GPL(amba_device_add);
-
-static struct amba_device *
-amba_aphb_device_add(struct device *parent, const char *name,
-		     resource_size_t base, size_t size, int irq1, int irq2,
-		     void *pdata, unsigned int periphid, u64 dma_mask,
-		     struct resource *resbase)
-{
-	struct amba_device *dev;
 	int ret;
 
-	dev = amba_device_alloc(name, base, size);
-	if (!dev)
-		return ERR_PTR(-ENOMEM);
+	fwnode_handle_get(dev_fwnode(&dev->dev));
 
-	dev->dev.coherent_dma_mask = dma_mask;
-	dev->irq[0] = irq1;
-	dev->irq[1] = irq2;
-	dev->periphid = periphid;
-	dev->dev.platform_data = pdata;
-	dev->dev.parent = parent;
+	ret = request_resource(parent, &dev->res);
+	if (ret)
+		return ret;
 
-	ret = amba_device_add(dev, resbase);
-	if (ret) {
-		amba_device_put(dev);
-		return ERR_PTR(ret);
+	/* If primecell ID isn't hard-coded, figure it out */
+	if (!dev->periphid) {
+		/*
+		 * AMBA device uevents require reading its pid and cid
+		 * registers.  To do this, the device must be on, clocked and
+		 * out of reset.  However in some cases those resources might
+		 * not yet be available.  If that's the case, we suppress the
+		 * generation of uevents until we can read the pid and cid
+		 * registers.  See also amba_match().
+		 */
+		if (amba_read_periphid(dev))
+			dev_set_uevent_suppress(&dev->dev, true);
 	}
 
-	return dev;
-}
-
-struct amba_device *
-amba_apb_device_add(struct device *parent, const char *name,
-		    resource_size_t base, size_t size, int irq1, int irq2,
-		    void *pdata, unsigned int periphid)
-{
-	return amba_aphb_device_add(parent, name, base, size, irq1, irq2, pdata,
-				    periphid, 0, &iomem_resource);
-}
-EXPORT_SYMBOL_GPL(amba_apb_device_add);
-
-struct amba_device *
-amba_ahb_device_add(struct device *parent, const char *name,
-		    resource_size_t base, size_t size, int irq1, int irq2,
-		    void *pdata, unsigned int periphid)
-{
-	return amba_aphb_device_add(parent, name, base, size, irq1, irq2, pdata,
-				    periphid, ~0ULL, &iomem_resource);
-}
-EXPORT_SYMBOL_GPL(amba_ahb_device_add);
-
-struct amba_device *
-amba_apb_device_add_res(struct device *parent, const char *name,
-			resource_size_t base, size_t size, int irq1,
-			int irq2, void *pdata, unsigned int periphid,
-			struct resource *resbase)
-{
-	return amba_aphb_device_add(parent, name, base, size, irq1, irq2, pdata,
-				    periphid, 0, resbase);
-}
-EXPORT_SYMBOL_GPL(amba_apb_device_add_res);
+	ret = device_add(&dev->dev);
+	if (ret)
+		release_resource(&dev->res);
 
-struct amba_device *
-amba_ahb_device_add_res(struct device *parent, const char *name,
-			resource_size_t base, size_t size, int irq1,
-			int irq2, void *pdata, unsigned int periphid,
-			struct resource *resbase)
-{
-	return amba_aphb_device_add(parent, name, base, size, irq1, irq2, pdata,
-				    periphid, ~0ULL, resbase);
+	return ret;
 }
-EXPORT_SYMBOL_GPL(amba_ahb_device_add_res);
-
+EXPORT_SYMBOL_GPL(amba_device_add);
 
 static void amba_device_initialize(struct amba_device *dev, const char *name)
 {
@@ -645,7 +592,9 @@ static void amba_device_initialize(struct amba_device *dev, const char *name)
 	dev->dev.release = amba_device_release;
 	dev->dev.bus = &amba_bustype;
 	dev->dev.dma_mask = &dev->dev.coherent_dma_mask;
+	dev->dev.dma_parms = &dev->dma_parms;
 	dev->res.name = dev_name(&dev->dev);
+	mutex_init(&dev->periphid_lock);
 }
 
 /**
@@ -690,6 +639,7 @@ int amba_device_register(struct amba_device *dev, struct resource *parent)
 
 	return amba_device_add(dev, parent);
 }
+EXPORT_SYMBOL(amba_device_register);
 
 /**
  *	amba_device_put - put an AMBA device
@@ -716,66 +666,7 @@ void amba_device_unregister(struct amba_device *dev)
 {
 	device_unregister(&dev->dev);
 }
-
-
-struct find_data {
-	struct amba_device *dev;
-	struct device *parent;
-	const char *busid;
-	unsigned int id;
-	unsigned int mask;
-};
-
-static int amba_find_match(struct device *dev, void *data)
-{
-	struct find_data *d = data;
-	struct amba_device *pcdev = to_amba_device(dev);
-	int r;
-
-	r = (pcdev->periphid & d->mask) == d->id;
-	if (d->parent)
-		r &= d->parent == dev->parent;
-	if (d->busid)
-		r &= strcmp(dev_name(dev), d->busid) == 0;
-
-	if (r) {
-		get_device(dev);
-		d->dev = pcdev;
-	}
-
-	return r;
-}
-
-/**
- *	amba_find_device - locate an AMBA device given a bus id
- *	@busid: bus id for device (or NULL)
- *	@parent: parent device (or NULL)
- *	@id: peripheral ID (or 0)
- *	@mask: peripheral ID mask (or 0)
- *
- *	Return the AMBA device corresponding to the supplied parameters.
- *	If no device matches, returns NULL.
- *
- *	NOTE: When a valid device is found, its refcount is
- *	incremented, and must be decremented before the returned
- *	reference.
- */
-struct amba_device *
-amba_find_device(const char *busid, struct device *parent, unsigned int id,
-		 unsigned int mask)
-{
-	struct find_data data;
-
-	data.dev = NULL;
-	data.parent = parent;
-	data.busid = busid;
-	data.id = id;
-	data.mask = mask;
-
-	bus_for_each_dev(&amba_bustype, NULL, &data, amba_find_match);
-
-	return data.dev;
-}
+EXPORT_SYMBOL(amba_device_unregister);
 
 /**
  *	amba_request_regions - request all mem regions associated with device
@@ -797,6 +688,7 @@ int amba_request_regions(struct amba_device *dev, const char *name)
 
 	return ret;
 }
+EXPORT_SYMBOL(amba_request_regions);
 
 /**
  *	amba_release_regions - release mem regions associated with device
@@ -811,11 +703,4 @@ void amba_release_regions(struct amba_device *dev)
 	size = resource_size(&dev->res);
 	release_mem_region(dev->res.start, size);
 }
-
-EXPORT_SYMBOL(amba_driver_register);
-EXPORT_SYMBOL(amba_driver_unregister);
-EXPORT_SYMBOL(amba_device_register);
-EXPORT_SYMBOL(amba_device_unregister);
-EXPORT_SYMBOL(amba_find_device);
-EXPORT_SYMBOL(amba_request_regions);
 EXPORT_SYMBOL(amba_release_regions);
diff --git a/drivers/amba/tegra-ahb.c b/drivers/amba/tegra-ahb.c
index 57d3b2e2d007..f23c3ed01810 100644
--- a/drivers/amba/tegra-ahb.c
+++ b/drivers/amba/tegra-ahb.c
@@ -120,7 +120,7 @@ static const u32 tegra_ahb_gizmo[] = {
 struct tegra_ahb {
 	void __iomem	*regs;
 	struct device	*dev;
-	u32		ctx[0];
+	u32		ctx[];
 };
 
 static inline u32 gizmo_readl(struct tegra_ahb *ahb, u32 offset)
@@ -144,6 +144,7 @@ int tegra_ahb_enable_smmu(struct device_node *dn)
 	if (!dev)
 		return -EPROBE_DEFER;
 	ahb = dev_get_drvdata(dev);
+	put_device(dev);
 	val = gizmo_readl(ahb, AHB_ARBITRATION_XBAR_CTRL);
 	val |= AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE;
 	gizmo_writel(ahb, val, AHB_ARBITRATION_XBAR_CTRL);
@@ -285,5 +286,4 @@ module_platform_driver(tegra_ahb_driver);
 
 MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
 MODULE_DESCRIPTION("Tegra AHB driver");
-MODULE_LICENSE("GPL v2");
 MODULE_ALIAS("platform:" DRV_NAME);
diff --git a/drivers/android/Kconfig b/drivers/android/Kconfig
index 6fdf2abe4598..e2e402c9d175 100644
--- a/drivers/android/Kconfig
+++ b/drivers/android/Kconfig
@@ -1,18 +1,25 @@
 # SPDX-License-Identifier: GPL-2.0
 menu "Android"
 
-config ANDROID
-	bool "Android Drivers"
-	---help---
-	  Enable support for various drivers needed on the Android platform
-
-if ANDROID
-
 config ANDROID_BINDER_IPC
 	bool "Android Binder IPC Driver"
 	depends on MMU
+	depends on NET
 	default n
-	---help---
+	help
+	  Binder is used in Android for both communication between processes,
+	  and remote method invocation.
+
+	  This means one Android process can call a method/routine in another
+	  Android process, using Binder to identify, invoke and pass arguments
+	  between said processes.
+
+config ANDROID_BINDER_IPC_RUST
+	bool "Rust version of Android Binder IPC Driver"
+	depends on RUST && MMU && !ANDROID_BINDER_IPC
+	help
+	  This enables the Rust implementation of the Binder driver.
+
 	  Binder is used in Android for both communication between processes,
 	  and remote method invocation.
 
@@ -24,7 +31,7 @@ config ANDROID_BINDERFS
 	bool "Android Binderfs filesystem"
 	depends on ANDROID_BINDER_IPC
 	default n
-	---help---
+	help
 	  Binderfs is a pseudo-filesystem for the Android Binder IPC driver
 	  which can be mounted per-ipc namespace allowing to run multiple
 	  instances of Android.
@@ -34,9 +41,9 @@ config ANDROID_BINDERFS
 
 config ANDROID_BINDER_DEVICES
 	string "Android Binder devices"
-	depends on ANDROID_BINDER_IPC
+	depends on ANDROID_BINDER_IPC || ANDROID_BINDER_IPC_RUST
 	default "binder,hwbinder,vndbinder"
-	---help---
+	help
 	  Default value for the binder.devices parameter.
 
 	  The binder.devices parameter is a comma-separated list of strings
@@ -44,16 +51,15 @@ config ANDROID_BINDER_DEVICES
 	  created. Each binder device has its own context manager, and is
 	  therefore logically separated from the other devices.
 
-config ANDROID_BINDER_IPC_SELFTEST
-	bool "Android Binder IPC Driver Selftest"
-	depends on ANDROID_BINDER_IPC
-	---help---
-	  This feature allows binder selftest to run.
-
-	  Binder selftest checks the allocation and free of binder buffers
-	  exhaustively with combinations of various buffer sizes and
-	  alignments.
+config ANDROID_BINDER_ALLOC_KUNIT_TEST
+	tristate "KUnit Tests for Android Binder Alloc" if !KUNIT_ALL_TESTS
+	depends on ANDROID_BINDER_IPC && KUNIT
+	default KUNIT_ALL_TESTS
+	help
+	  This feature builds the binder alloc KUnit tests.
 
-endif # if ANDROID
+	  Each test case runs using a pared-down binder_alloc struct and
+	  test-specific freelist, which allows this KUnit module to be loaded
+	  for testing without interfering with a running system.
 
 endmenu
diff --git a/drivers/android/Makefile b/drivers/android/Makefile
index c9d3d0c99c25..e0c650d3898e 100644
--- a/drivers/android/Makefile
+++ b/drivers/android/Makefile
@@ -2,5 +2,6 @@
 ccflags-y += -I$(src)			# needed for trace events
 
 obj-$(CONFIG_ANDROID_BINDERFS)		+= binderfs.o
-obj-$(CONFIG_ANDROID_BINDER_IPC)	+= binder.o binder_alloc.o
-obj-$(CONFIG_ANDROID_BINDER_IPC_SELFTEST) += binder_alloc_selftest.o
+obj-$(CONFIG_ANDROID_BINDER_IPC)	+= binder.o binder_alloc.o binder_netlink.o
+obj-$(CONFIG_ANDROID_BINDER_ALLOC_KUNIT_TEST)	+= tests/
+obj-$(CONFIG_ANDROID_BINDER_IPC_RUST)	+= binder/
diff --git a/drivers/android/binder.c b/drivers/android/binder.c
index e47c8a4c83db..535fc881c8da 100644
--- a/drivers/android/binder.c
+++ b/drivers/android/binder.c
@@ -66,13 +66,15 @@
 #include <linux/syscalls.h>
 #include <linux/task_work.h>
 #include <linux/sizes.h>
+#include <linux/ktime.h>
+
+#include <kunit/visibility.h>
 
 #include <uapi/linux/android/binder.h>
-#include <uapi/linux/android/binderfs.h>
 
-#include <asm/cacheflush.h>
+#include <linux/cacheflush.h>
 
-#include "binder_alloc.h"
+#include "binder_netlink.h"
 #include "binder_internal.h"
 #include "binder_trace.h"
 
@@ -80,6 +82,8 @@ static HLIST_HEAD(binder_deferred_list);
 static DEFINE_MUTEX(binder_deferred_lock);
 
 static HLIST_HEAD(binder_devices);
+static DEFINE_SPINLOCK(binder_devices_lock);
+
 static HLIST_HEAD(binder_procs);
 static DEFINE_MUTEX(binder_procs_lock);
 
@@ -135,18 +139,45 @@ static int binder_set_stop_on_user_error(const char *val,
 module_param_call(stop_on_user_error, binder_set_stop_on_user_error,
 	param_get_int, &binder_stop_on_user_error, 0644);
 
-#define binder_debug(mask, x...) \
-	do { \
-		if (binder_debug_mask & mask) \
-			pr_info_ratelimited(x); \
-	} while (0)
+static __printf(2, 3) void binder_debug(int mask, const char *format, ...)
+{
+	struct va_format vaf;
+	va_list args;
+
+	if (binder_debug_mask & mask) {
+		va_start(args, format);
+		vaf.va = &args;
+		vaf.fmt = format;
+		pr_info_ratelimited("%pV", &vaf);
+		va_end(args);
+	}
+}
+
+#define binder_txn_error(x...) \
+	binder_debug(BINDER_DEBUG_FAILED_TRANSACTION, x)
+
+static __printf(1, 2) void binder_user_error(const char *format, ...)
+{
+	struct va_format vaf;
+	va_list args;
+
+	if (binder_debug_mask & BINDER_DEBUG_USER_ERROR) {
+		va_start(args, format);
+		vaf.va = &args;
+		vaf.fmt = format;
+		pr_info_ratelimited("%pV", &vaf);
+		va_end(args);
+	}
+
+	if (binder_stop_on_user_error)
+		binder_stop_on_user_error = 2;
+}
 
-#define binder_user_error(x...) \
+#define binder_set_extended_error(ee, _id, _command, _param) \
 	do { \
-		if (binder_debug_mask & BINDER_DEBUG_USER_ERROR) \
-			pr_info_ratelimited(x); \
-		if (binder_stop_on_user_error) \
-			binder_stop_on_user_error = 2; \
+		(ee)->id = _id; \
+		(ee)->command = _command; \
+		(ee)->param = _param; \
 	} while (0)
 
 #define to_flat_binder_object(hdr) \
@@ -160,24 +191,6 @@ module_param_call(stop_on_user_error, binder_set_stop_on_user_error,
 #define to_binder_fd_array_object(hdr) \
 	container_of(hdr, struct binder_fd_array_object, hdr)
 
-enum binder_stat_types {
-	BINDER_STAT_PROC,
-	BINDER_STAT_THREAD,
-	BINDER_STAT_NODE,
-	BINDER_STAT_REF,
-	BINDER_STAT_DEATH,
-	BINDER_STAT_TRANSACTION,
-	BINDER_STAT_TRANSACTION_COMPLETE,
-	BINDER_STAT_COUNT
-};
-
-struct binder_stats {
-	atomic_t br[_IOC_NR(BR_FAILED_REPLY) + 1];
-	atomic_t bc[_IOC_NR(BC_REPLY_SG) + 1];
-	atomic_t obj_created[BINDER_STAT_COUNT];
-	atomic_t obj_deleted[BINDER_STAT_COUNT];
-};
-
 static struct binder_stats binder_stats;
 
 static inline void binder_stats_deleted(enum binder_stat_types type)
@@ -190,8 +203,32 @@ static inline void binder_stats_created(enum binder_stat_types type)
 	atomic_inc(&binder_stats.obj_created[type]);
 }
 
-struct binder_transaction_log binder_transaction_log;
-struct binder_transaction_log binder_transaction_log_failed;
+struct binder_transaction_log_entry {
+	int debug_id;
+	int debug_id_done;
+	int call_type;
+	int from_proc;
+	int from_thread;
+	int target_handle;
+	int to_proc;
+	int to_thread;
+	int to_node;
+	int data_size;
+	int offsets_size;
+	int return_error_line;
+	uint32_t return_error;
+	uint32_t return_error_param;
+	char context_name[BINDERFS_MAX_NAME + 1];
+};
+
+struct binder_transaction_log {
+	atomic_t cur;
+	bool full;
+	struct binder_transaction_log_entry entry[32];
+};
+
+static struct binder_transaction_log binder_transaction_log;
+static struct binder_transaction_log binder_transaction_log_failed;
 
 static struct binder_transaction_log_entry *binder_transaction_log_add(
 	struct binder_transaction_log *log)
@@ -213,278 +250,11 @@ static struct binder_transaction_log_entry *binder_transaction_log_add(
 	return e;
 }
 
-/**
- * struct binder_work - work enqueued on a worklist
- * @entry:             node enqueued on list
- * @type:              type of work to be performed
- *
- * There are separate work lists for proc, thread, and node (async).
- */
-struct binder_work {
-	struct list_head entry;
-
-	enum {
-		BINDER_WORK_TRANSACTION = 1,
-		BINDER_WORK_TRANSACTION_COMPLETE,
-		BINDER_WORK_RETURN_ERROR,
-		BINDER_WORK_NODE,
-		BINDER_WORK_DEAD_BINDER,
-		BINDER_WORK_DEAD_BINDER_AND_CLEAR,
-		BINDER_WORK_CLEAR_DEATH_NOTIFICATION,
-	} type;
-};
-
-struct binder_error {
-	struct binder_work work;
-	uint32_t cmd;
-};
-
-/**
- * struct binder_node - binder node bookkeeping
- * @debug_id:             unique ID for debugging
- *                        (invariant after initialized)
- * @lock:                 lock for node fields
- * @work:                 worklist element for node work
- *                        (protected by @proc->inner_lock)
- * @rb_node:              element for proc->nodes tree
- *                        (protected by @proc->inner_lock)
- * @dead_node:            element for binder_dead_nodes list
- *                        (protected by binder_dead_nodes_lock)
- * @proc:                 binder_proc that owns this node
- *                        (invariant after initialized)
- * @refs:                 list of references on this node
- *                        (protected by @lock)
- * @internal_strong_refs: used to take strong references when
- *                        initiating a transaction
- *                        (protected by @proc->inner_lock if @proc
- *                        and by @lock)
- * @local_weak_refs:      weak user refs from local process
- *                        (protected by @proc->inner_lock if @proc
- *                        and by @lock)
- * @local_strong_refs:    strong user refs from local process
- *                        (protected by @proc->inner_lock if @proc
- *                        and by @lock)
- * @tmp_refs:             temporary kernel refs
- *                        (protected by @proc->inner_lock while @proc
- *                        is valid, and by binder_dead_nodes_lock
- *                        if @proc is NULL. During inc/dec and node release
- *                        it is also protected by @lock to provide safety
- *                        as the node dies and @proc becomes NULL)
- * @ptr:                  userspace pointer for node
- *                        (invariant, no lock needed)
- * @cookie:               userspace cookie for node
- *                        (invariant, no lock needed)
- * @has_strong_ref:       userspace notified of strong ref
- *                        (protected by @proc->inner_lock if @proc
- *                        and by @lock)
- * @pending_strong_ref:   userspace has acked notification of strong ref
- *                        (protected by @proc->inner_lock if @proc
- *                        and by @lock)
- * @has_weak_ref:         userspace notified of weak ref
- *                        (protected by @proc->inner_lock if @proc
- *                        and by @lock)
- * @pending_weak_ref:     userspace has acked notification of weak ref
- *                        (protected by @proc->inner_lock if @proc
- *                        and by @lock)
- * @has_async_transaction: async transaction to node in progress
- *                        (protected by @lock)
- * @accept_fds:           file descriptor operations supported for node
- *                        (invariant after initialized)
- * @min_priority:         minimum scheduling priority
- *                        (invariant after initialized)
- * @txn_security_ctx:     require sender's security context
- *                        (invariant after initialized)
- * @async_todo:           list of async work items
- *                        (protected by @proc->inner_lock)
- *
- * Bookkeeping structure for binder nodes.
- */
-struct binder_node {
-	int debug_id;
-	spinlock_t lock;
-	struct binder_work work;
-	union {
-		struct rb_node rb_node;
-		struct hlist_node dead_node;
-	};
-	struct binder_proc *proc;
-	struct hlist_head refs;
-	int internal_strong_refs;
-	int local_weak_refs;
-	int local_strong_refs;
-	int tmp_refs;
-	binder_uintptr_t ptr;
-	binder_uintptr_t cookie;
-	struct {
-		/*
-		 * bitfield elements protected by
-		 * proc inner_lock
-		 */
-		u8 has_strong_ref:1;
-		u8 pending_strong_ref:1;
-		u8 has_weak_ref:1;
-		u8 pending_weak_ref:1;
-	};
-	struct {
-		/*
-		 * invariant after initialization
-		 */
-		u8 accept_fds:1;
-		u8 txn_security_ctx:1;
-		u8 min_priority;
-	};
-	bool has_async_transaction;
-	struct list_head async_todo;
-};
-
-struct binder_ref_death {
-	/**
-	 * @work: worklist element for death notifications
-	 *        (protected by inner_lock of the proc that
-	 *        this ref belongs to)
-	 */
-	struct binder_work work;
-	binder_uintptr_t cookie;
-};
-
-/**
- * struct binder_ref_data - binder_ref counts and id
- * @debug_id:        unique ID for the ref
- * @desc:            unique userspace handle for ref
- * @strong:          strong ref count (debugging only if not locked)
- * @weak:            weak ref count (debugging only if not locked)
- *
- * Structure to hold ref count and ref id information. Since
- * the actual ref can only be accessed with a lock, this structure
- * is used to return information about the ref to callers of
- * ref inc/dec functions.
- */
-struct binder_ref_data {
-	int debug_id;
-	uint32_t desc;
-	int strong;
-	int weak;
-};
-
-/**
- * struct binder_ref - struct to track references on nodes
- * @data:        binder_ref_data containing id, handle, and current refcounts
- * @rb_node_desc: node for lookup by @data.desc in proc's rb_tree
- * @rb_node_node: node for lookup by @node in proc's rb_tree
- * @node_entry:  list entry for node->refs list in target node
- *               (protected by @node->lock)
- * @proc:        binder_proc containing ref
- * @node:        binder_node of target node. When cleaning up a
- *               ref for deletion in binder_cleanup_ref, a non-NULL
- *               @node indicates the node must be freed
- * @death:       pointer to death notification (ref_death) if requested
- *               (protected by @node->lock)
- *
- * Structure to track references from procA to target node (on procB). This
- * structure is unsafe to access without holding @proc->outer_lock.
- */
-struct binder_ref {
-	/* Lookups needed: */
-	/*   node + proc => ref (transaction) */
-	/*   desc + proc => ref (transaction, inc/dec ref) */
-	/*   node => refs + procs (proc exit) */
-	struct binder_ref_data data;
-	struct rb_node rb_node_desc;
-	struct rb_node rb_node_node;
-	struct hlist_node node_entry;
-	struct binder_proc *proc;
-	struct binder_node *node;
-	struct binder_ref_death *death;
-};
-
 enum binder_deferred_state {
 	BINDER_DEFERRED_FLUSH        = 0x01,
 	BINDER_DEFERRED_RELEASE      = 0x02,
 };
 
-/**
- * struct binder_proc - binder process bookkeeping
- * @proc_node:            element for binder_procs list
- * @threads:              rbtree of binder_threads in this proc
- *                        (protected by @inner_lock)
- * @nodes:                rbtree of binder nodes associated with
- *                        this proc ordered by node->ptr
- *                        (protected by @inner_lock)
- * @refs_by_desc:         rbtree of refs ordered by ref->desc
- *                        (protected by @outer_lock)
- * @refs_by_node:         rbtree of refs ordered by ref->node
- *                        (protected by @outer_lock)
- * @waiting_threads:      threads currently waiting for proc work
- *                        (protected by @inner_lock)
- * @pid                   PID of group_leader of process
- *                        (invariant after initialized)
- * @tsk                   task_struct for group_leader of process
- *                        (invariant after initialized)
- * @deferred_work_node:   element for binder_deferred_list
- *                        (protected by binder_deferred_lock)
- * @deferred_work:        bitmap of deferred work to perform
- *                        (protected by binder_deferred_lock)
- * @is_dead:              process is dead and awaiting free
- *                        when outstanding transactions are cleaned up
- *                        (protected by @inner_lock)
- * @todo:                 list of work for this process
- *                        (protected by @inner_lock)
- * @stats:                per-process binder statistics
- *                        (atomics, no lock needed)
- * @delivered_death:      list of delivered death notification
- *                        (protected by @inner_lock)
- * @max_threads:          cap on number of binder threads
- *                        (protected by @inner_lock)
- * @requested_threads:    number of binder threads requested but not
- *                        yet started. In current implementation, can
- *                        only be 0 or 1.
- *                        (protected by @inner_lock)
- * @requested_threads_started: number binder threads started
- *                        (protected by @inner_lock)
- * @tmp_ref:              temporary reference to indicate proc is in use
- *                        (protected by @inner_lock)
- * @default_priority:     default scheduler priority
- *                        (invariant after initialized)
- * @debugfs_entry:        debugfs node
- * @alloc:                binder allocator bookkeeping
- * @context:              binder_context for this proc
- *                        (invariant after initialized)
- * @inner_lock:           can nest under outer_lock and/or node lock
- * @outer_lock:           no nesting under innor or node lock
- *                        Lock order: 1) outer, 2) node, 3) inner
- * @binderfs_entry:       process-specific binderfs log file
- *
- * Bookkeeping structure for binder processes
- */
-struct binder_proc {
-	struct hlist_node proc_node;
-	struct rb_root threads;
-	struct rb_root nodes;
-	struct rb_root refs_by_desc;
-	struct rb_root refs_by_node;
-	struct list_head waiting_threads;
-	int pid;
-	struct task_struct *tsk;
-	struct hlist_node deferred_work_node;
-	int deferred_work;
-	bool is_dead;
-
-	struct list_head todo;
-	struct binder_stats stats;
-	struct list_head delivered_death;
-	int max_threads;
-	int requested_threads;
-	int requested_threads_started;
-	int tmp_ref;
-	long default_priority;
-	struct dentry *debugfs_entry;
-	struct binder_alloc alloc;
-	struct binder_context *context;
-	spinlock_t inner_lock;
-	spinlock_t outer_lock;
-	struct dentry *binderfs_entry;
-};
-
 enum {
 	BINDER_LOOPER_STATE_REGISTERED  = 0x01,
 	BINDER_LOOPER_STATE_ENTERED     = 0x02,
@@ -495,125 +265,6 @@ enum {
 };
 
 /**
- * struct binder_thread - binder thread bookkeeping
- * @proc:                 binder process for this thread
- *                        (invariant after initialization)
- * @rb_node:              element for proc->threads rbtree
- *                        (protected by @proc->inner_lock)
- * @waiting_thread_node:  element for @proc->waiting_threads list
- *                        (protected by @proc->inner_lock)
- * @pid:                  PID for this thread
- *                        (invariant after initialization)
- * @looper:               bitmap of looping state
- *                        (only accessed by this thread)
- * @looper_needs_return:  looping thread needs to exit driver
- *                        (no lock needed)
- * @transaction_stack:    stack of in-progress transactions for this thread
- *                        (protected by @proc->inner_lock)
- * @todo:                 list of work to do for this thread
- *                        (protected by @proc->inner_lock)
- * @process_todo:         whether work in @todo should be processed
- *                        (protected by @proc->inner_lock)
- * @return_error:         transaction errors reported by this thread
- *                        (only accessed by this thread)
- * @reply_error:          transaction errors reported by target thread
- *                        (protected by @proc->inner_lock)
- * @wait:                 wait queue for thread work
- * @stats:                per-thread statistics
- *                        (atomics, no lock needed)
- * @tmp_ref:              temporary reference to indicate thread is in use
- *                        (atomic since @proc->inner_lock cannot
- *                        always be acquired)
- * @is_dead:              thread is dead and awaiting free
- *                        when outstanding transactions are cleaned up
- *                        (protected by @proc->inner_lock)
- *
- * Bookkeeping structure for binder threads.
- */
-struct binder_thread {
-	struct binder_proc *proc;
-	struct rb_node rb_node;
-	struct list_head waiting_thread_node;
-	int pid;
-	int looper;              /* only modified by this thread */
-	bool looper_need_return; /* can be written by other thread */
-	struct binder_transaction *transaction_stack;
-	struct list_head todo;
-	bool process_todo;
-	struct binder_error return_error;
-	struct binder_error reply_error;
-	wait_queue_head_t wait;
-	struct binder_stats stats;
-	atomic_t tmp_ref;
-	bool is_dead;
-};
-
-/**
- * struct binder_txn_fd_fixup - transaction fd fixup list element
- * @fixup_entry:          list entry
- * @file:                 struct file to be associated with new fd
- * @offset:               offset in buffer data to this fixup
- *
- * List element for fd fixups in a transaction. Since file
- * descriptors need to be allocated in the context of the
- * target process, we pass each fd to be processed in this
- * struct.
- */
-struct binder_txn_fd_fixup {
-	struct list_head fixup_entry;
-	struct file *file;
-	size_t offset;
-};
-
-struct binder_transaction {
-	int debug_id;
-	struct binder_work work;
-	struct binder_thread *from;
-	struct binder_transaction *from_parent;
-	struct binder_proc *to_proc;
-	struct binder_thread *to_thread;
-	struct binder_transaction *to_parent;
-	unsigned need_reply:1;
-	/* unsigned is_dead:1; */	/* not used at the moment */
-
-	struct binder_buffer *buffer;
-	unsigned int	code;
-	unsigned int	flags;
-	long	priority;
-	long	saved_priority;
-	kuid_t	sender_euid;
-	struct list_head fd_fixups;
-	binder_uintptr_t security_ctx;
-	/**
-	 * @lock:  protects @from, @to_proc, and @to_thread
-	 *
-	 * @from, @to_proc, and @to_thread can be set to NULL
-	 * during thread teardown
-	 */
-	spinlock_t lock;
-};
-
-/**
- * struct binder_object - union of flat binder object types
- * @hdr:   generic object header
- * @fbo:   binder object (nodes and refs)
- * @fdo:   file descriptor object
- * @bbo:   binder buffer pointer
- * @fdao:  file descriptor array
- *
- * Used for type-independent object copies
- */
-struct binder_object {
-	union {
-		struct binder_object_header hdr;
-		struct flat_binder_object fbo;
-		struct binder_fd_object fdo;
-		struct binder_buffer_object bbo;
-		struct binder_fd_array_object fdao;
-	};
-};
-
-/**
  * binder_proc_lock() - Acquire outer lock for given binder_proc
  * @proc:         struct binder_proc to acquire
  *
@@ -631,12 +282,12 @@ _binder_proc_lock(struct binder_proc *proc, int line)
 }
 
 /**
- * binder_proc_unlock() - Release spinlock for given binder_proc
- * @proc:         struct binder_proc to acquire
+ * binder_proc_unlock() - Release outer lock for given binder_proc
+ * @proc:                struct binder_proc to acquire
  *
  * Release lock acquired via binder_proc_lock()
  */
-#define binder_proc_unlock(_proc) _binder_proc_unlock(_proc, __LINE__)
+#define binder_proc_unlock(proc) _binder_proc_unlock(proc, __LINE__)
 static void
 _binder_proc_unlock(struct binder_proc *proc, int line)
 	__releases(&proc->outer_lock)
@@ -733,7 +384,7 @@ _binder_node_inner_lock(struct binder_node *node, int line)
 }
 
 /**
- * binder_node_unlock() - Release node and inner locks
+ * binder_node_inner_unlock() - Release node and inner locks
  * @node:         struct binder_node to acquire
  *
  * Release lock acquired via binder_node_lock()
@@ -832,6 +483,16 @@ binder_enqueue_thread_work_ilocked(struct binder_thread *thread,
 {
 	WARN_ON(!list_empty(&thread->waiting_thread_node));
 	binder_enqueue_work_ilocked(work, &thread->todo);
+
+	/* (e)poll-based threads require an explicit wakeup signal when
+	 * queuing their own work; they rely on these events to consume
+	 * messages without I/O block. Without it, threads risk waiting
+	 * indefinitely without handling the work.
+	 */
+	if (thread->looper & BINDER_LOOPER_STATE_POLL &&
+	    thread->pid == current->pid && !thread->process_todo)
+		wake_up_interruptible_sync(&thread->wait);
+
 	thread->process_todo = true;
 }
 
@@ -885,27 +546,6 @@ static struct binder_work *binder_dequeue_work_head_ilocked(
 	return w;
 }
 
-/**
- * binder_dequeue_work_head() - Dequeues the item at head of list
- * @proc:         binder_proc associated with list
- * @list:         list to dequeue head
- *
- * Removes the head of the list if there are items on the list
- *
- * Return: pointer dequeued binder_work, NULL if list was empty
- */
-static struct binder_work *binder_dequeue_work_head(
-					struct binder_proc *proc,
-					struct list_head *list)
-{
-	struct binder_work *w;
-
-	binder_inner_proc_lock(proc);
-	w = binder_dequeue_work_head_ilocked(list);
-	binder_inner_proc_unlock(proc);
-	return w;
-}
-
 static void
 binder_defer_work(struct binder_proc *proc, enum binder_deferred_state defer);
 static void binder_free_thread(struct binder_thread *thread);
@@ -935,9 +575,7 @@ static bool binder_has_work(struct binder_thread *thread, bool do_proc_work)
 static bool binder_available_for_proc_work_ilocked(struct binder_thread *thread)
 {
 	return !thread->transaction_stack &&
-		binder_worklist_empty_ilocked(&thread->todo) &&
-		(thread->looper & (BINDER_LOOPER_STATE_ENTERED |
-				   BINDER_LOOPER_STATE_REGISTERED));
+		binder_worklist_empty_ilocked(&thread->todo);
 }
 
 static void binder_wakeup_poll_threads_ilocked(struct binder_proc *proc,
@@ -1213,17 +851,8 @@ static int binder_inc_node_nilocked(struct binder_node *node, int strong,
 	} else {
 		if (!internal)
 			node->local_weak_refs++;
-		if (!node->has_weak_ref && list_empty(&node->work.entry)) {
-			if (target_list == NULL) {
-				pr_err("invalid inc weak node for %d\n",
-					node->debug_id);
-				return -EINVAL;
-			}
-			/*
-			 * See comment above
-			 */
+		if (!node->has_weak_ref && target_list && list_empty(&node->work.entry))
 			binder_enqueue_work_ilocked(&node->work, target_list);
-		}
 	}
 	return 0;
 }
@@ -1410,6 +1039,63 @@ static struct binder_ref *binder_get_ref_olocked(struct binder_proc *proc,
 	return NULL;
 }
 
+/* Find the smallest unused descriptor the "slow way" */
+static u32 slow_desc_lookup_olocked(struct binder_proc *proc, u32 offset)
+{
+	struct binder_ref *ref;
+	struct rb_node *n;
+	u32 desc;
+
+	desc = offset;
+	for (n = rb_first(&proc->refs_by_desc); n; n = rb_next(n)) {
+		ref = rb_entry(n, struct binder_ref, rb_node_desc);
+		if (ref->data.desc > desc)
+			break;
+		desc = ref->data.desc + 1;
+	}
+
+	return desc;
+}
+
+/*
+ * Find an available reference descriptor ID. The proc->outer_lock might
+ * be released in the process, in which case -EAGAIN is returned and the
+ * @desc should be considered invalid.
+ */
+static int get_ref_desc_olocked(struct binder_proc *proc,
+				struct binder_node *node,
+				u32 *desc)
+{
+	struct dbitmap *dmap = &proc->dmap;
+	unsigned int nbits, offset;
+	unsigned long *new, bit;
+
+	/* 0 is reserved for the context manager */
+	offset = (node == proc->context->binder_context_mgr_node) ? 0 : 1;
+
+	if (!dbitmap_enabled(dmap)) {
+		*desc = slow_desc_lookup_olocked(proc, offset);
+		return 0;
+	}
+
+	if (dbitmap_acquire_next_zero_bit(dmap, offset, &bit) == 0) {
+		*desc = bit;
+		return 0;
+	}
+
+	/*
+	 * The dbitmap is full and needs to grow. The proc->outer_lock
+	 * is briefly released to allocate the new bitmap safely.
+	 */
+	nbits = dbitmap_grow_nbits(dmap);
+	binder_proc_unlock(proc);
+	new = bitmap_zalloc(nbits, GFP_KERNEL);
+	binder_proc_lock(proc);
+	dbitmap_grow(dmap, new, nbits);
+
+	return -EAGAIN;
+}
+
 /**
  * binder_get_ref_for_node_olocked() - get the ref associated with given node
  * @proc:	binder_proc that owns the ref
@@ -1433,12 +1119,14 @@ static struct binder_ref *binder_get_ref_for_node_olocked(
 					struct binder_node *node,
 					struct binder_ref *new_ref)
 {
-	struct binder_context *context = proc->context;
-	struct rb_node **p = &proc->refs_by_node.rb_node;
-	struct rb_node *parent = NULL;
 	struct binder_ref *ref;
-	struct rb_node *n;
+	struct rb_node *parent;
+	struct rb_node **p;
+	u32 desc;
 
+retry:
+	p = &proc->refs_by_node.rb_node;
+	parent = NULL;
 	while (*p) {
 		parent = *p;
 		ref = rb_entry(parent, struct binder_ref, rb_node_node);
@@ -1453,6 +1141,10 @@ static struct binder_ref *binder_get_ref_for_node_olocked(
 	if (!new_ref)
 		return NULL;
 
+	/* might release the proc->outer_lock */
+	if (get_ref_desc_olocked(proc, node, &desc) == -EAGAIN)
+		goto retry;
+
 	binder_stats_created(BINDER_STAT_REF);
 	new_ref->data.debug_id = atomic_inc_return(&binder_last_id);
 	new_ref->proc = proc;
@@ -1460,14 +1152,7 @@ static struct binder_ref *binder_get_ref_for_node_olocked(
 	rb_link_node(&new_ref->rb_node_node, parent, p);
 	rb_insert_color(&new_ref->rb_node_node, &proc->refs_by_node);
 
-	new_ref->data.desc = (node == context->binder_context_mgr_node) ? 0 : 1;
-	for (n = rb_first(&proc->refs_by_desc); n != NULL; n = rb_next(n)) {
-		ref = rb_entry(n, struct binder_ref, rb_node_desc);
-		if (ref->data.desc > new_ref->data.desc)
-			break;
-		new_ref->data.desc = ref->data.desc + 1;
-	}
-
+	new_ref->data.desc = desc;
 	p = &proc->refs_by_desc.rb_node;
 	while (*p) {
 		parent = *p;
@@ -1496,6 +1181,7 @@ static struct binder_ref *binder_get_ref_for_node_olocked(
 
 static void binder_cleanup_ref_olocked(struct binder_ref *ref)
 {
+	struct dbitmap *dmap = &ref->proc->dmap;
 	bool delete_node = false;
 
 	binder_debug(BINDER_DEBUG_INTERNAL_REFS,
@@ -1503,6 +1189,8 @@ static void binder_cleanup_ref_olocked(struct binder_ref *ref)
 		      ref->proc->pid, ref->data.debug_id, ref->data.desc,
 		      ref->node->debug_id);
 
+	if (dbitmap_enabled(dmap))
+		dbitmap_clear_bit(dmap, ref->data.desc);
 	rb_erase(&ref->rb_node_desc, &ref->proc->refs_by_desc);
 	rb_erase(&ref->rb_node_node, &ref->proc->refs_by_node);
 
@@ -1533,6 +1221,12 @@ static void binder_cleanup_ref_olocked(struct binder_ref *ref)
 		binder_dequeue_work(ref->proc, &ref->death->work);
 		binder_stats_deleted(BINDER_STAT_DEATH);
 	}
+
+	if (ref->freeze) {
+		binder_dequeue_work(ref->proc, &ref->freeze->work);
+		binder_stats_deleted(BINDER_STAT_FREEZE);
+	}
+
 	binder_stats_deleted(BINDER_STAT_REF);
 }
 
@@ -1570,13 +1264,13 @@ static int binder_inc_ref_olocked(struct binder_ref *ref, int strong,
 }
 
 /**
- * binder_dec_ref() - dec the ref for given handle
+ * binder_dec_ref_olocked() - dec the ref for given handle
  * @ref:	ref to be decremented
  * @strong:	if true, strong decrement, else weak
  *
  * Decrement the ref.
  *
- * Return: true if ref is cleaned up and ready to be freed
+ * Return: %true if ref is cleaned up and ready to be freed.
  */
 static bool binder_dec_ref_olocked(struct binder_ref *ref, int strong)
 {
@@ -1660,9 +1354,29 @@ static void binder_free_ref(struct binder_ref *ref)
 	if (ref->node)
 		binder_free_node(ref->node);
 	kfree(ref->death);
+	kfree(ref->freeze);
 	kfree(ref);
 }
 
+/* shrink descriptor bitmap if needed */
+static void try_shrink_dmap(struct binder_proc *proc)
+{
+	unsigned long *new;
+	int nbits;
+
+	binder_proc_lock(proc);
+	nbits = dbitmap_shrink_nbits(&proc->dmap);
+	binder_proc_unlock(proc);
+
+	if (!nbits)
+		return;
+
+	new = bitmap_zalloc(nbits, GFP_KERNEL);
+	binder_proc_lock(proc);
+	dbitmap_shrink(&proc->dmap, new, nbits);
+	binder_proc_unlock(proc);
+}
+
 /**
  * binder_update_ref_for_handle() - inc/dec the ref for given handle
  * @proc:	proc containing the ref
@@ -1699,8 +1413,10 @@ static int binder_update_ref_for_handle(struct binder_proc *proc,
 		*rdata = ref->data;
 	binder_proc_unlock(proc);
 
-	if (delete_ref)
+	if (delete_ref) {
 		binder_free_ref(ref);
+		try_shrink_dmap(proc);
+	}
 	return ret;
 
 err_no_ref:
@@ -1761,6 +1477,18 @@ static int binder_inc_ref_for_node(struct binder_proc *proc,
 	}
 	ret = binder_inc_ref_olocked(ref, strong, target_list);
 	*rdata = ref->data;
+	if (ret && ref == new_ref) {
+		/*
+		 * Cleanup the failed reference here as the target
+		 * could now be dead and have already released its
+		 * references by now. Calling on the new reference
+		 * with strong=0 and a tmp_refs will not decrement
+		 * the node. The new_ref gets kfree'd below.
+		 */
+		binder_cleanup_ref_olocked(new_ref);
+		ref = NULL;
+	}
+
 	binder_proc_unlock(proc);
 	if (new_ref && ref != new_ref)
 		/*
@@ -1821,7 +1549,7 @@ static void binder_thread_dec_tmpref(struct binder_thread *thread)
  * by threads that are being released. When done with the binder_proc,
  * this function is called to decrement the counter and free the
  * proc if appropriate (proc has been released, all threads have
- * been released and not currenly in-use to process a transaction).
+ * been released and not currently in-use to process a transaction).
  */
 static void binder_proc_dec_tmpref(struct binder_proc *proc)
 {
@@ -1851,11 +1579,10 @@ static struct binder_thread *binder_get_txn_from(
 {
 	struct binder_thread *from;
 
-	spin_lock(&t->lock);
+	guard(spinlock)(&t->lock);
 	from = t->from;
 	if (from)
 		atomic_inc(&from->tmp_ref);
-	spin_unlock(&t->lock);
 	return from;
 }
 
@@ -1908,21 +1635,45 @@ static void binder_free_txn_fixups(struct binder_transaction *t)
 
 	list_for_each_entry_safe(fixup, tmp, &t->fd_fixups, fixup_entry) {
 		fput(fixup->file);
+		if (fixup->target_fd >= 0)
+			put_unused_fd(fixup->target_fd);
 		list_del(&fixup->fixup_entry);
 		kfree(fixup);
 	}
 }
 
+static void binder_txn_latency_free(struct binder_transaction *t)
+{
+	int from_proc, from_thread, to_proc, to_thread;
+
+	spin_lock(&t->lock);
+	from_proc = t->from ? t->from->proc->pid : 0;
+	from_thread = t->from ? t->from->pid : 0;
+	to_proc = t->to_proc ? t->to_proc->pid : 0;
+	to_thread = t->to_thread ? t->to_thread->pid : 0;
+	spin_unlock(&t->lock);
+
+	trace_binder_txn_latency_free(t, from_proc, from_thread, to_proc, to_thread);
+}
+
 static void binder_free_transaction(struct binder_transaction *t)
 {
 	struct binder_proc *target_proc = t->to_proc;
 
 	if (target_proc) {
 		binder_inner_proc_lock(target_proc);
+		target_proc->outstanding_txns--;
+		if (target_proc->outstanding_txns < 0)
+			pr_warn("%s: Unexpected outstanding_txns %d\n",
+				__func__, target_proc->outstanding_txns);
+		if (!target_proc->outstanding_txns && target_proc->is_frozen)
+			wake_up_interruptible_all(&target_proc->freeze_wait);
 		if (t->buffer)
 			t->buffer->transaction = NULL;
 		binder_inner_proc_unlock(target_proc);
 	}
+	if (trace_binder_txn_latency_free_enabled())
+		binder_txn_latency_free(t);
 	/*
 	 * If the transaction has no target_proc, then
 	 * t->buffer->transaction has already been cleared.
@@ -1969,9 +1720,8 @@ static void binder_send_failed_reply(struct binder_transaction *t,
 			binder_thread_dec_tmpref(target_thread);
 			binder_free_transaction(t);
 			return;
-		} else {
-			__release(&target_thread->proc->inner_lock);
 		}
+		__release(&target_thread->proc->inner_lock);
 		next = t->from_parent;
 
 		binder_debug(BINDER_DEBUG_FAILED_TRANSACTION,
@@ -2014,15 +1764,21 @@ static void binder_cleanup_transaction(struct binder_transaction *t,
 /**
  * binder_get_object() - gets object and checks for valid metadata
  * @proc:	binder_proc owning the buffer
+ * @u:		sender's user pointer to base of buffer
  * @buffer:	binder_buffer that we're parsing.
  * @offset:	offset in the @buffer at which to validate an object.
  * @object:	struct binder_object to read into
  *
- * Return:	If there's a valid metadata object at @offset in @buffer, the
+ * Copy the binder object at the given offset into @object. If @u is
+ * provided then the copy is from the sender's buffer. If not, then
+ * it is copied from the target's @buffer.
+ *
+ * Return:	If there's a valid metadata object at @offset, the
  *		size of that object. Otherwise, it returns zero. The object
  *		is read into the struct binder_object pointed to by @object.
  */
 static size_t binder_get_object(struct binder_proc *proc,
+				const void __user *u,
 				struct binder_buffer *buffer,
 				unsigned long offset,
 				struct binder_object *object)
@@ -2033,10 +1789,18 @@ static size_t binder_get_object(struct binder_proc *proc,
 
 	read_size = min_t(size_t, sizeof(*object), buffer->data_size - offset);
 	if (offset > buffer->data_size || read_size < sizeof(*hdr) ||
-	    binder_alloc_copy_from_buffer(&proc->alloc, object, buffer,
-					  offset, read_size))
+	    !IS_ALIGNED(offset, sizeof(u32)))
 		return 0;
 
+	if (u) {
+		if (copy_from_user(object, u + offset, read_size))
+			return 0;
+	} else {
+		if (binder_alloc_copy_from_buffer(&proc->alloc, object, buffer,
+						  offset, read_size))
+			return 0;
+	}
+
 	/* Ok, now see if we read a complete object. */
 	hdr = &object->hdr;
 	switch (hdr->type) {
@@ -2108,7 +1872,7 @@ static struct binder_buffer_object *binder_validate_ptr(
 					  b, buffer_offset,
 					  sizeof(object_offset)))
 		return NULL;
-	object_size = binder_get_object(proc, b, object_offset, object);
+	object_size = binder_get_object(proc, NULL, b, object_offset, object);
 	if (!object_size || object->hdr.type != BINDER_TYPE_PTR)
 		return NULL;
 	if (object_offsetp)
@@ -2173,7 +1937,8 @@ static bool binder_validate_fixup(struct binder_proc *proc,
 		unsigned long buffer_offset;
 		struct binder_object last_object;
 		struct binder_buffer_object *last_bbo;
-		size_t object_size = binder_get_object(proc, b, last_obj_offset,
+		size_t object_size = binder_get_object(proc, NULL, b,
+						       last_obj_offset,
 						       &last_object);
 		if (object_size != sizeof(*last_bbo))
 			return false;
@@ -2201,7 +1966,7 @@ static bool binder_validate_fixup(struct binder_proc *proc,
  * struct binder_task_work_cb - for deferred close
  *
  * @twork:                callback_head for task work
- * @fd:                   fd to close
+ * @file:                 file to close
  *
  * Structure to pass task work to be handled after
  * returning from binder_ioctl() via task_work_add().
@@ -2248,35 +2013,37 @@ static void binder_deferred_fd_close(int fd)
 	if (!twcb)
 		return;
 	init_task_work(&twcb->twork, binder_do_fd_close);
-	__close_fd_get_file(fd, &twcb->file);
+	twcb->file = file_close_fd(fd);
 	if (twcb->file) {
+		// pin it until binder_do_fd_close(); see comments there
+		get_file(twcb->file);
 		filp_close(twcb->file, current->files);
-		task_work_add(current, &twcb->twork, true);
+		task_work_add(current, &twcb->twork, TWA_RESUME);
 	} else {
 		kfree(twcb);
 	}
 }
 
 static void binder_transaction_buffer_release(struct binder_proc *proc,
+					      struct binder_thread *thread,
 					      struct binder_buffer *buffer,
-					      binder_size_t failed_at,
+					      binder_size_t off_end_offset,
 					      bool is_failure)
 {
 	int debug_id = buffer->debug_id;
-	binder_size_t off_start_offset, buffer_offset, off_end_offset;
+	binder_size_t off_start_offset, buffer_offset;
 
 	binder_debug(BINDER_DEBUG_TRANSACTION,
 		     "%d buffer release %d, size %zd-%zd, failed at %llx\n",
 		     proc->pid, buffer->debug_id,
 		     buffer->data_size, buffer->offsets_size,
-		     (unsigned long long)failed_at);
+		     (unsigned long long)off_end_offset);
 
 	if (buffer->target_node)
 		binder_dec_node(buffer->target_node, 1, 0);
 
 	off_start_offset = ALIGN(buffer->data_size, sizeof(void *));
-	off_end_offset = is_failure ? failed_at :
-				off_start_offset + buffer->offsets_size;
+
 	for (buffer_offset = off_start_offset; buffer_offset < off_end_offset;
 	     buffer_offset += sizeof(binder_size_t)) {
 		struct binder_object_header *hdr;
@@ -2287,7 +2054,7 @@ static void binder_transaction_buffer_release(struct binder_proc *proc,
 		if (!binder_alloc_copy_from_buffer(&proc->alloc, &object_offset,
 						   buffer, buffer_offset,
 						   sizeof(object_offset)))
-			object_size = binder_get_object(proc, buffer,
+			object_size = binder_get_object(proc, NULL, buffer,
 							object_offset, &object);
 		if (object_size == 0) {
 			pr_err("transaction release %d bad object at offset %lld, size %zd\n",
@@ -2338,15 +2105,13 @@ static void binder_transaction_buffer_release(struct binder_proc *proc,
 		case BINDER_TYPE_FD: {
 			/*
 			 * No need to close the file here since user-space
-			 * closes it for for successfully delivered
+			 * closes it for successfully delivered
 			 * transactions. For transactions that weren't
 			 * delivered, the new fd was never allocated so
 			 * there is no need to close and the fput on the
 			 * file is done when the transaction is torn
 			 * down.
 			 */
-			WARN_ON(failed_at &&
-				proc->tsk == current->group_leader);
 		} break;
 		case BINDER_TYPE_PTR:
 			/*
@@ -2363,9 +2128,8 @@ static void binder_transaction_buffer_release(struct binder_proc *proc,
 			binder_size_t fd_buf_size;
 			binder_size_t num_valid;
 
-			if (proc->tsk != current->group_leader) {
+			if (is_failure) {
 				/*
-				 * Nothing to do if running in sender context
 				 * The fd fixups have not been applied so no
 				 * fds need to be closed.
 				 */
@@ -2405,9 +2169,8 @@ static void binder_transaction_buffer_release(struct binder_proc *proc,
 			 * Convert the address to an offset relative to
 			 * the base of the transaction buffer.
 			 */
-			fda_offset =
-			    (parent->buffer - (uintptr_t)buffer->user_data) +
-			    fda->parent_offset;
+			fda_offset = parent->buffer - buffer->user_data +
+				fda->parent_offset;
 			for (fd_index = 0; fd_index < fda->num_fds;
 			     fd_index++) {
 				u32 fd;
@@ -2419,8 +2182,16 @@ static void binder_transaction_buffer_release(struct binder_proc *proc,
 						&proc->alloc, &fd, buffer,
 						offset, sizeof(fd));
 				WARN_ON(err);
-				if (!err)
+				if (!err) {
 					binder_deferred_fd_close(fd);
+					/*
+					 * Need to make sure the thread goes
+					 * back to userspace to complete the
+					 * deferred close
+					 */
+					if (thread)
+						thread->looper_need_return = true;
+				}
 			}
 		} break;
 		default:
@@ -2431,6 +2202,21 @@ static void binder_transaction_buffer_release(struct binder_proc *proc,
 	}
 }
 
+/* Clean up all the objects in the buffer */
+static inline void binder_release_entire_buffer(struct binder_proc *proc,
+						struct binder_thread *thread,
+						struct binder_buffer *buffer,
+						bool is_failure)
+{
+	binder_size_t off_end_offset;
+
+	off_end_offset = ALIGN(buffer->data_size, sizeof(void *));
+	off_end_offset += buffer->offsets_size;
+
+	binder_transaction_buffer_release(proc, thread, buffer,
+					  off_end_offset, is_failure);
+}
+
 static int binder_translate_binder(struct flat_binder_object *fp,
 				   struct binder_transaction *t,
 				   struct binder_thread *thread)
@@ -2455,7 +2241,7 @@ static int binder_translate_binder(struct flat_binder_object *fp,
 		ret = -EINVAL;
 		goto done;
 	}
-	if (security_binder_transfer_binder(proc->tsk, target_proc->tsk)) {
+	if (security_binder_transfer_binder(proc->cred, target_proc->cred)) {
 		ret = -EPERM;
 		goto done;
 	}
@@ -2501,7 +2287,7 @@ static int binder_translate_handle(struct flat_binder_object *fp,
 				  proc->pid, thread->pid, fp->handle);
 		return -EINVAL;
 	}
-	if (security_binder_transfer_binder(proc->tsk, target_proc->tsk)) {
+	if (security_binder_transfer_binder(proc->cred, target_proc->cred)) {
 		ret = -EPERM;
 		goto done;
 	}
@@ -2589,7 +2375,7 @@ static int binder_translate_fd(u32 fd, binder_size_t fd_offset,
 		ret = -EBADF;
 		goto err_fget;
 	}
-	ret = security_binder_transfer_file(proc->tsk, target_proc->tsk, file);
+	ret = security_binder_transfer_file(proc->cred, target_proc->cred, file);
 	if (ret < 0) {
 		ret = -EPERM;
 		goto err_security;
@@ -2607,6 +2393,7 @@ static int binder_translate_fd(u32 fd, binder_size_t fd_offset,
 	}
 	fixup->file = file;
 	fixup->offset = fd_offset;
+	fixup->target_fd = -1;
 	trace_binder_transaction_fd_send(t, fd, fixup->offset);
 	list_add_tail(&fixup->fixup_entry, &t->fd_fixups);
 
@@ -2620,16 +2407,266 @@ err_fd_not_accepted:
 	return ret;
 }
 
-static int binder_translate_fd_array(struct binder_fd_array_object *fda,
+/**
+ * struct binder_ptr_fixup - data to be fixed-up in target buffer
+ * @offset:      offset in target buffer to fixup
+ * @skip_size:   bytes to skip in copy (fixup will be written later)
+ * @fixup_data:  data to write at fixup offset
+ * @node:        list node
+ *
+ * This is used for the pointer fixup list (pf) which is created and consumed
+ * during binder_transaction() and is only accessed locally. No
+ * locking is necessary.
+ *
+ * The list is ordered by @offset.
+ */
+struct binder_ptr_fixup {
+	binder_size_t offset;
+	size_t skip_size;
+	binder_uintptr_t fixup_data;
+	struct list_head node;
+};
+
+/**
+ * struct binder_sg_copy - scatter-gather data to be copied
+ * @offset:        offset in target buffer
+ * @sender_uaddr:  user address in source buffer
+ * @length:        bytes to copy
+ * @node:          list node
+ *
+ * This is used for the sg copy list (sgc) which is created and consumed
+ * during binder_transaction() and is only accessed locally. No
+ * locking is necessary.
+ *
+ * The list is ordered by @offset.
+ */
+struct binder_sg_copy {
+	binder_size_t offset;
+	const void __user *sender_uaddr;
+	size_t length;
+	struct list_head node;
+};
+
+/**
+ * binder_do_deferred_txn_copies() - copy and fixup scatter-gather data
+ * @alloc:	binder_alloc associated with @buffer
+ * @buffer:	binder buffer in target process
+ * @sgc_head:	list_head of scatter-gather copy list
+ * @pf_head:	list_head of pointer fixup list
+ *
+ * Processes all elements of @sgc_head, applying fixups from @pf_head
+ * and copying the scatter-gather data from the source process' user
+ * buffer to the target's buffer. It is expected that the list creation
+ * and processing all occurs during binder_transaction() so these lists
+ * are only accessed in local context.
+ *
+ * Return: 0=success, else -errno
+ */
+static int binder_do_deferred_txn_copies(struct binder_alloc *alloc,
+					 struct binder_buffer *buffer,
+					 struct list_head *sgc_head,
+					 struct list_head *pf_head)
+{
+	int ret = 0;
+	struct binder_sg_copy *sgc, *tmpsgc;
+	struct binder_ptr_fixup *tmppf;
+	struct binder_ptr_fixup *pf =
+		list_first_entry_or_null(pf_head, struct binder_ptr_fixup,
+					 node);
+
+	list_for_each_entry_safe(sgc, tmpsgc, sgc_head, node) {
+		size_t bytes_copied = 0;
+
+		while (bytes_copied < sgc->length) {
+			size_t copy_size;
+			size_t bytes_left = sgc->length - bytes_copied;
+			size_t offset = sgc->offset + bytes_copied;
+
+			/*
+			 * We copy up to the fixup (pointed to by pf)
+			 */
+			copy_size = pf ? min(bytes_left, (size_t)pf->offset - offset)
+				       : bytes_left;
+			if (!ret && copy_size)
+				ret = binder_alloc_copy_user_to_buffer(
+						alloc, buffer,
+						offset,
+						sgc->sender_uaddr + bytes_copied,
+						copy_size);
+			bytes_copied += copy_size;
+			if (copy_size != bytes_left) {
+				BUG_ON(!pf);
+				/* we stopped at a fixup offset */
+				if (pf->skip_size) {
+					/*
+					 * we are just skipping. This is for
+					 * BINDER_TYPE_FDA where the translated
+					 * fds will be fixed up when we get
+					 * to target context.
+					 */
+					bytes_copied += pf->skip_size;
+				} else {
+					/* apply the fixup indicated by pf */
+					if (!ret)
+						ret = binder_alloc_copy_to_buffer(
+							alloc, buffer,
+							pf->offset,
+							&pf->fixup_data,
+							sizeof(pf->fixup_data));
+					bytes_copied += sizeof(pf->fixup_data);
+				}
+				list_del(&pf->node);
+				kfree(pf);
+				pf = list_first_entry_or_null(pf_head,
+						struct binder_ptr_fixup, node);
+			}
+		}
+		list_del(&sgc->node);
+		kfree(sgc);
+	}
+	list_for_each_entry_safe(pf, tmppf, pf_head, node) {
+		BUG_ON(pf->skip_size == 0);
+		list_del(&pf->node);
+		kfree(pf);
+	}
+	BUG_ON(!list_empty(sgc_head));
+
+	return ret > 0 ? -EINVAL : ret;
+}
+
+/**
+ * binder_cleanup_deferred_txn_lists() - free specified lists
+ * @sgc_head:	list_head of scatter-gather copy list
+ * @pf_head:	list_head of pointer fixup list
+ *
+ * Called to clean up @sgc_head and @pf_head if there is an
+ * error.
+ */
+static void binder_cleanup_deferred_txn_lists(struct list_head *sgc_head,
+					      struct list_head *pf_head)
+{
+	struct binder_sg_copy *sgc, *tmpsgc;
+	struct binder_ptr_fixup *pf, *tmppf;
+
+	list_for_each_entry_safe(sgc, tmpsgc, sgc_head, node) {
+		list_del(&sgc->node);
+		kfree(sgc);
+	}
+	list_for_each_entry_safe(pf, tmppf, pf_head, node) {
+		list_del(&pf->node);
+		kfree(pf);
+	}
+}
+
+/**
+ * binder_defer_copy() - queue a scatter-gather buffer for copy
+ * @sgc_head:		list_head of scatter-gather copy list
+ * @offset:		binder buffer offset in target process
+ * @sender_uaddr:	user address in source process
+ * @length:		bytes to copy
+ *
+ * Specify a scatter-gather block to be copied. The actual copy must
+ * be deferred until all the needed fixups are identified and queued.
+ * Then the copy and fixups are done together so un-translated values
+ * from the source are never visible in the target buffer.
+ *
+ * We are guaranteed that repeated calls to this function will have
+ * monotonically increasing @offset values so the list will naturally
+ * be ordered.
+ *
+ * Return: 0=success, else -errno
+ */
+static int binder_defer_copy(struct list_head *sgc_head, binder_size_t offset,
+			     const void __user *sender_uaddr, size_t length)
+{
+	struct binder_sg_copy *bc = kzalloc(sizeof(*bc), GFP_KERNEL);
+
+	if (!bc)
+		return -ENOMEM;
+
+	bc->offset = offset;
+	bc->sender_uaddr = sender_uaddr;
+	bc->length = length;
+	INIT_LIST_HEAD(&bc->node);
+
+	/*
+	 * We are guaranteed that the deferred copies are in-order
+	 * so just add to the tail.
+	 */
+	list_add_tail(&bc->node, sgc_head);
+
+	return 0;
+}
+
+/**
+ * binder_add_fixup() - queue a fixup to be applied to sg copy
+ * @pf_head:	list_head of binder ptr fixup list
+ * @offset:	binder buffer offset in target process
+ * @fixup:	bytes to be copied for fixup
+ * @skip_size:	bytes to skip when copying (fixup will be applied later)
+ *
+ * Add the specified fixup to a list ordered by @offset. When copying
+ * the scatter-gather buffers, the fixup will be copied instead of
+ * data from the source buffer. For BINDER_TYPE_FDA fixups, the fixup
+ * will be applied later (in target process context), so we just skip
+ * the bytes specified by @skip_size. If @skip_size is 0, we copy the
+ * value in @fixup.
+ *
+ * This function is called *mostly* in @offset order, but there are
+ * exceptions. Since out-of-order inserts are relatively uncommon,
+ * we insert the new element by searching backward from the tail of
+ * the list.
+ *
+ * Return: 0=success, else -errno
+ */
+static int binder_add_fixup(struct list_head *pf_head, binder_size_t offset,
+			    binder_uintptr_t fixup, size_t skip_size)
+{
+	struct binder_ptr_fixup *pf = kzalloc(sizeof(*pf), GFP_KERNEL);
+	struct binder_ptr_fixup *tmppf;
+
+	if (!pf)
+		return -ENOMEM;
+
+	pf->offset = offset;
+	pf->fixup_data = fixup;
+	pf->skip_size = skip_size;
+	INIT_LIST_HEAD(&pf->node);
+
+	/* Fixups are *mostly* added in-order, but there are some
+	 * exceptions. Look backwards through list for insertion point.
+	 */
+	list_for_each_entry_reverse(tmppf, pf_head, node) {
+		if (tmppf->offset < pf->offset) {
+			list_add(&pf->node, &tmppf->node);
+			return 0;
+		}
+	}
+	/*
+	 * if we get here, then the new offset is the lowest so
+	 * insert at the head
+	 */
+	list_add(&pf->node, pf_head);
+	return 0;
+}
+
+static int binder_translate_fd_array(struct list_head *pf_head,
+				     struct binder_fd_array_object *fda,
+				     const void __user *sender_ubuffer,
 				     struct binder_buffer_object *parent,
+				     struct binder_buffer_object *sender_uparent,
 				     struct binder_transaction *t,
 				     struct binder_thread *thread,
 				     struct binder_transaction *in_reply_to)
 {
 	binder_size_t fdi, fd_buf_size;
 	binder_size_t fda_offset;
+	const void __user *sender_ufda_base;
 	struct binder_proc *proc = thread->proc;
-	struct binder_proc *target_proc = t->to_proc;
+	int ret;
+
+	if (fda->num_fds == 0)
+		return 0;
 
 	fd_buf_size = sizeof(u32) * fda->num_fds;
 	if (fda->num_fds >= SIZE_MAX / sizeof(u32)) {
@@ -2651,31 +2688,38 @@ static int binder_translate_fd_array(struct binder_fd_array_object *fda,
 	 * Convert the address to an offset relative to
 	 * the base of the transaction buffer.
 	 */
-	fda_offset = (parent->buffer - (uintptr_t)t->buffer->user_data) +
+	fda_offset = parent->buffer - t->buffer->user_data +
 		fda->parent_offset;
-	if (!IS_ALIGNED((unsigned long)fda_offset, sizeof(u32))) {
+	sender_ufda_base = (void __user *)(uintptr_t)sender_uparent->buffer +
+				fda->parent_offset;
+
+	if (!IS_ALIGNED((unsigned long)fda_offset, sizeof(u32)) ||
+	    !IS_ALIGNED((unsigned long)sender_ufda_base, sizeof(u32))) {
 		binder_user_error("%d:%d parent offset not aligned correctly.\n",
 				  proc->pid, thread->pid);
 		return -EINVAL;
 	}
+	ret = binder_add_fixup(pf_head, fda_offset, 0, fda->num_fds * sizeof(u32));
+	if (ret)
+		return ret;
+
 	for (fdi = 0; fdi < fda->num_fds; fdi++) {
 		u32 fd;
-		int ret;
 		binder_size_t offset = fda_offset + fdi * sizeof(fd);
+		binder_size_t sender_uoffset = fdi * sizeof(fd);
 
-		ret = binder_alloc_copy_from_buffer(&target_proc->alloc,
-						    &fd, t->buffer,
-						    offset, sizeof(fd));
+		ret = copy_from_user(&fd, sender_ufda_base + sender_uoffset, sizeof(fd));
 		if (!ret)
 			ret = binder_translate_fd(fd, offset, t, thread,
 						  in_reply_to);
-		if (ret < 0)
-			return ret;
+		if (ret)
+			return ret > 0 ? -EINVAL : ret;
 	}
 	return 0;
 }
 
-static int binder_fixup_parent(struct binder_transaction *t,
+static int binder_fixup_parent(struct list_head *pf_head,
+			       struct binder_transaction *t,
 			       struct binder_thread *thread,
 			       struct binder_buffer_object *bp,
 			       binder_size_t off_start_offset,
@@ -2719,16 +2763,60 @@ static int binder_fixup_parent(struct binder_transaction *t,
 				  proc->pid, thread->pid);
 		return -EINVAL;
 	}
-	buffer_offset = bp->parent_offset +
-			(uintptr_t)parent->buffer - (uintptr_t)b->user_data;
-	if (binder_alloc_copy_to_buffer(&target_proc->alloc, b, buffer_offset,
-					&bp->buffer, sizeof(bp->buffer))) {
-		binder_user_error("%d:%d got transaction with invalid parent offset\n",
-				  proc->pid, thread->pid);
-		return -EINVAL;
-	}
 
-	return 0;
+	buffer_offset = bp->parent_offset + parent->buffer - b->user_data;
+
+	return binder_add_fixup(pf_head, buffer_offset, bp->buffer, 0);
+}
+
+/**
+ * binder_can_update_transaction() - Can a txn be superseded by an updated one?
+ * @t1: the pending async txn in the frozen process
+ * @t2: the new async txn to supersede the outdated pending one
+ *
+ * Return:  true if t2 can supersede t1
+ *          false if t2 can not supersede t1
+ */
+static bool binder_can_update_transaction(struct binder_transaction *t1,
+					  struct binder_transaction *t2)
+{
+	if ((t1->flags & t2->flags & (TF_ONE_WAY | TF_UPDATE_TXN)) !=
+	    (TF_ONE_WAY | TF_UPDATE_TXN) || !t1->to_proc || !t2->to_proc)
+		return false;
+	if (t1->to_proc->tsk == t2->to_proc->tsk && t1->code == t2->code &&
+	    t1->flags == t2->flags && t1->buffer->pid == t2->buffer->pid &&
+	    t1->buffer->target_node->ptr == t2->buffer->target_node->ptr &&
+	    t1->buffer->target_node->cookie == t2->buffer->target_node->cookie)
+		return true;
+	return false;
+}
+
+/**
+ * binder_find_outdated_transaction_ilocked() - Find the outdated transaction
+ * @t:		 new async transaction
+ * @target_list: list to find outdated transaction
+ *
+ * Return: the outdated transaction if found
+ *         NULL if no outdated transacton can be found
+ *
+ * Requires the proc->inner_lock to be held.
+ */
+static struct binder_transaction *
+binder_find_outdated_transaction_ilocked(struct binder_transaction *t,
+					 struct list_head *target_list)
+{
+	struct binder_work *w;
+
+	list_for_each_entry(w, target_list, entry) {
+		struct binder_transaction *t_queued;
+
+		if (w->type != BINDER_WORK_TRANSACTION)
+			continue;
+		t_queued = container_of(w, struct binder_transaction, work);
+		if (binder_can_update_transaction(t_queued, t))
+			return t_queued;
+	}
+	return NULL;
 }
 
 /**
@@ -2745,60 +2833,103 @@ static int binder_fixup_parent(struct binder_transaction *t,
  * If the @thread parameter is not NULL, the transaction is always queued
  * to the waitlist of that specific thread.
  *
- * Return:	true if the transactions was successfully queued
- *		false if the target process or thread is dead
+ * Return:	0 if the transaction was successfully queued
+ *		BR_DEAD_REPLY if the target process or thread is dead
+ *		BR_FROZEN_REPLY if the target process or thread is frozen and
+ *			the sync transaction was rejected
+ *		BR_TRANSACTION_PENDING_FROZEN if the target process is frozen
+ *		and the async transaction was successfully queued
  */
-static bool binder_proc_transaction(struct binder_transaction *t,
+static int binder_proc_transaction(struct binder_transaction *t,
 				    struct binder_proc *proc,
 				    struct binder_thread *thread)
 {
 	struct binder_node *node = t->buffer->target_node;
 	bool oneway = !!(t->flags & TF_ONE_WAY);
 	bool pending_async = false;
+	struct binder_transaction *t_outdated = NULL;
+	bool frozen = false;
 
 	BUG_ON(!node);
 	binder_node_lock(node);
 	if (oneway) {
 		BUG_ON(thread);
-		if (node->has_async_transaction) {
+		if (node->has_async_transaction)
 			pending_async = true;
-		} else {
+		else
 			node->has_async_transaction = true;
-		}
 	}
 
 	binder_inner_proc_lock(proc);
+	if (proc->is_frozen) {
+		frozen = true;
+		proc->sync_recv |= !oneway;
+		proc->async_recv |= oneway;
+	}
 
-	if (proc->is_dead || (thread && thread->is_dead)) {
+	if ((frozen && !oneway) || proc->is_dead ||
+			(thread && thread->is_dead)) {
 		binder_inner_proc_unlock(proc);
 		binder_node_unlock(node);
-		return false;
+		return frozen ? BR_FROZEN_REPLY : BR_DEAD_REPLY;
 	}
 
 	if (!thread && !pending_async)
 		thread = binder_select_thread_ilocked(proc);
 
-	if (thread)
+	if (thread) {
 		binder_enqueue_thread_work_ilocked(thread, &t->work);
-	else if (!pending_async)
+	} else if (!pending_async) {
 		binder_enqueue_work_ilocked(&t->work, &proc->todo);
-	else
+	} else {
+		if ((t->flags & TF_UPDATE_TXN) && frozen) {
+			t_outdated = binder_find_outdated_transaction_ilocked(t,
+									      &node->async_todo);
+			if (t_outdated) {
+				binder_debug(BINDER_DEBUG_TRANSACTION,
+					     "txn %d supersedes %d\n",
+					     t->debug_id, t_outdated->debug_id);
+				list_del_init(&t_outdated->work.entry);
+				proc->outstanding_txns--;
+			}
+		}
 		binder_enqueue_work_ilocked(&t->work, &node->async_todo);
+	}
 
 	if (!pending_async)
 		binder_wakeup_thread_ilocked(proc, thread, !oneway /* sync */);
 
+	proc->outstanding_txns++;
 	binder_inner_proc_unlock(proc);
 	binder_node_unlock(node);
 
-	return true;
+	/*
+	 * To reduce potential contention, free the outdated transaction and
+	 * buffer after releasing the locks.
+	 */
+	if (t_outdated) {
+		struct binder_buffer *buffer = t_outdated->buffer;
+
+		t_outdated->buffer = NULL;
+		buffer->transaction = NULL;
+		trace_binder_transaction_update_buffer_release(buffer);
+		binder_release_entire_buffer(proc, NULL, buffer, false);
+		binder_alloc_free_buf(&proc->alloc, buffer);
+		kfree(t_outdated);
+		binder_stats_deleted(BINDER_STAT_TRANSACTION);
+	}
+
+	if (oneway && frozen)
+		return BR_TRANSACTION_PENDING_FROZEN;
+
+	return 0;
 }
 
 /**
  * binder_get_node_refs_for_txn() - Get required refs on node for txn
  * @node:         struct binder_node for which to get refs
- * @proc:         returns @node->proc if valid
- * @error:        if no @proc then returns BR_DEAD_REPLY
+ * @procp:        returns @node->proc if valid
+ * @error:        if no @procp then returns BR_DEAD_REPLY
  *
  * User-space normally keeps the node alive when creating a transaction
  * since it has a reference to the target. The local strong ref keeps it
@@ -2812,8 +2943,8 @@ static bool binder_proc_transaction(struct binder_transaction *t,
  * constructing the transaction, so we take that here as well.
  *
  * Return: The target_node with refs taken or NULL if no @node->proc is NULL.
- * Also sets @proc if valid. If the @node->proc is NULL indicating that the
- * target proc has died, @error is set to BR_DEAD_REPLY
+ * Also sets @procp if valid. If the @node->proc is NULL indicating that the
+ * target proc has died, @error is set to BR_DEAD_REPLY.
  */
 static struct binder_node *binder_get_node_refs_for_txn(
 		struct binder_node *node,
@@ -2836,6 +2967,87 @@ static struct binder_node *binder_get_node_refs_for_txn(
 	return target_node;
 }
 
+static void binder_set_txn_from_error(struct binder_transaction *t, int id,
+				      uint32_t command, int32_t param)
+{
+	struct binder_thread *from = binder_get_txn_from_and_acq_inner(t);
+
+	if (!from) {
+		/* annotation for sparse */
+		__release(&from->proc->inner_lock);
+		return;
+	}
+
+	/* don't override existing errors */
+	if (from->ee.command == BR_OK)
+		binder_set_extended_error(&from->ee, id, command, param);
+	binder_inner_proc_unlock(from->proc);
+	binder_thread_dec_tmpref(from);
+}
+
+/**
+ * binder_netlink_report() - report a transaction failure via netlink
+ * @proc:	the binder proc sending the transaction
+ * @t:		the binder transaction that failed
+ * @data_size:	the user provided data size for the transaction
+ * @error:	enum binder_driver_return_protocol returned to sender
+ */
+static void binder_netlink_report(struct binder_proc *proc,
+				  struct binder_transaction *t,
+				  u32 data_size,
+				  u32 error)
+{
+	const char *context = proc->context->name;
+	struct sk_buff *skb;
+	void *hdr;
+
+	if (!genl_has_listeners(&binder_nl_family, &init_net,
+				BINDER_NLGRP_REPORT))
+		return;
+
+	trace_binder_netlink_report(context, t, data_size, error);
+
+	skb = genlmsg_new(GENLMSG_DEFAULT_SIZE, GFP_KERNEL);
+	if (!skb)
+		return;
+
+	hdr = genlmsg_put(skb, 0, 0, &binder_nl_family, 0, BINDER_CMD_REPORT);
+	if (!hdr)
+		goto free_skb;
+
+	if (nla_put_u32(skb, BINDER_A_REPORT_ERROR, error) ||
+	    nla_put_string(skb, BINDER_A_REPORT_CONTEXT, context) ||
+	    nla_put_u32(skb, BINDER_A_REPORT_FROM_PID, t->from_pid) ||
+	    nla_put_u32(skb, BINDER_A_REPORT_FROM_TID, t->from_tid))
+		goto cancel_skb;
+
+	if (t->to_proc &&
+	    nla_put_u32(skb, BINDER_A_REPORT_TO_PID, t->to_proc->pid))
+		goto cancel_skb;
+
+	if (t->to_thread &&
+	    nla_put_u32(skb, BINDER_A_REPORT_TO_TID, t->to_thread->pid))
+		goto cancel_skb;
+
+	if (t->is_reply && nla_put_flag(skb, BINDER_A_REPORT_IS_REPLY))
+		goto cancel_skb;
+
+	if (nla_put_u32(skb, BINDER_A_REPORT_FLAGS, t->flags) ||
+	    nla_put_u32(skb, BINDER_A_REPORT_CODE, t->code) ||
+	    nla_put_u32(skb, BINDER_A_REPORT_DATA_SIZE, data_size))
+		goto cancel_skb;
+
+	genlmsg_end(skb, hdr);
+	genlmsg_multicast(&binder_nl_family, skb, 0, BINDER_NLGRP_REPORT,
+			  GFP_KERNEL);
+	return;
+
+cancel_skb:
+	genlmsg_cancel(skb, hdr);
+free_skb:
+	nlmsg_free(skb);
+}
+
 static void binder_transaction(struct binder_proc *proc,
 			       struct binder_thread *thread,
 			       struct binder_transaction_data *tr, int reply,
@@ -2849,6 +3061,7 @@ static void binder_transaction(struct binder_proc *proc,
 	binder_size_t off_start_offset, off_end_offset;
 	binder_size_t off_min;
 	binder_size_t sg_buf_offset, sg_buf_end_offset;
+	binder_size_t user_offset = 0;
 	struct binder_proc *target_proc = NULL;
 	struct binder_thread *target_thread = NULL;
 	struct binder_node *target_node = NULL;
@@ -2861,8 +3074,14 @@ static void binder_transaction(struct binder_proc *proc,
 	binder_size_t last_fixup_min_off = 0;
 	struct binder_context *context = proc->context;
 	int t_debug_id = atomic_inc_return(&binder_last_id);
-	char *secctx = NULL;
-	u32 secctx_sz = 0;
+	ktime_t t_start_time = ktime_get();
+	struct lsm_context lsmctx = { };
+	struct list_head sgc_head;
+	struct list_head pf_head;
+	const void __user *user_buffer = (const void __user *)
+				(uintptr_t)tr->data.ptr.buffer;
+	INIT_LIST_HEAD(&sgc_head);
+	INIT_LIST_HEAD(&pf_head);
 
 	e = binder_transaction_log_add(&binder_transaction_log);
 	e->debug_id = t_debug_id;
@@ -2874,6 +3093,36 @@ static void binder_transaction(struct binder_proc *proc,
 	e->offsets_size = tr->offsets_size;
 	strscpy(e->context_name, proc->context->name, BINDERFS_MAX_NAME);
 
+	binder_inner_proc_lock(proc);
+	binder_set_extended_error(&thread->ee, t_debug_id, BR_OK, 0);
+	binder_inner_proc_unlock(proc);
+
+	t = kzalloc(sizeof(*t), GFP_KERNEL);
+	if (!t) {
+		binder_txn_error("%d:%d cannot allocate transaction\n",
+				 thread->pid, proc->pid);
+		return_error = BR_FAILED_REPLY;
+		return_error_param = -ENOMEM;
+		return_error_line = __LINE__;
+		goto err_alloc_t_failed;
+	}
+	INIT_LIST_HEAD(&t->fd_fixups);
+	binder_stats_created(BINDER_STAT_TRANSACTION);
+	spin_lock_init(&t->lock);
+	t->debug_id = t_debug_id;
+	t->start_time = t_start_time;
+	t->from_pid = proc->pid;
+	t->from_tid = thread->pid;
+	t->sender_euid = task_euid(proc->tsk);
+	t->code = tr->code;
+	t->flags = tr->flags;
+	t->priority = task_nice(current);
+	t->work.type = BINDER_WORK_TRANSACTION;
+	t->is_async = !reply && (tr->flags & TF_ONE_WAY);
+	t->is_reply = reply;
+	if (!reply && !(tr->flags & TF_ONE_WAY))
+		t->from = thread;
+
 	if (reply) {
 		binder_inner_proc_lock(proc);
 		in_reply_to = thread->transaction_stack;
@@ -2909,6 +3158,8 @@ static void binder_transaction(struct binder_proc *proc,
 		if (target_thread == NULL) {
 			/* annotation for sparse */
 			__release(&target_thread->proc->inner_lock);
+			binder_txn_error("%d:%d reply target not found\n",
+				thread->pid, proc->pid);
 			return_error = BR_DEAD_REPLY;
 			return_error_line = __LINE__;
 			goto err_dead_binder;
@@ -2949,8 +3200,8 @@ static void binder_transaction(struct binder_proc *proc,
 						ref->node, &target_proc,
 						&return_error);
 			} else {
-				binder_user_error("%d:%d got transaction to invalid handle\n",
-						  proc->pid, thread->pid);
+				binder_user_error("%d:%d got transaction to invalid handle, %u\n",
+						  proc->pid, thread->pid, tr->target.handle);
 				return_error = BR_FAILED_REPLY;
 			}
 			binder_proc_unlock(proc);
@@ -2974,16 +3225,26 @@ static void binder_transaction(struct binder_proc *proc,
 			}
 		}
 		if (!target_node) {
-			/*
-			 * return_error is set above
-			 */
+			binder_txn_error("%d:%d cannot find target node\n",
+					 proc->pid, thread->pid);
+			/* return_error is set above */
 			return_error_param = -EINVAL;
 			return_error_line = __LINE__;
 			goto err_dead_binder;
 		}
 		e->to_node = target_node->debug_id;
-		if (security_binder_transaction(proc->tsk,
-						target_proc->tsk) < 0) {
+		if (WARN_ON(proc == target_proc)) {
+			binder_txn_error("%d:%d self transactions not allowed\n",
+				thread->pid, proc->pid);
+			return_error = BR_FAILED_REPLY;
+			return_error_param = -EINVAL;
+			return_error_line = __LINE__;
+			goto err_invalid_target_handle;
+		}
+		if (security_binder_transaction(proc->cred,
+						target_proc->cred) < 0) {
+			binder_txn_error("%d:%d transaction credentials failed\n",
+				thread->pid, proc->pid);
 			return_error = BR_FAILED_REPLY;
 			return_error_param = -EPERM;
 			return_error_line = __LINE__;
@@ -3048,24 +3309,17 @@ static void binder_transaction(struct binder_proc *proc,
 		}
 		binder_inner_proc_unlock(proc);
 	}
+
+	t->to_proc = target_proc;
+	t->to_thread = target_thread;
 	if (target_thread)
 		e->to_thread = target_thread->pid;
 	e->to_proc = target_proc->pid;
 
-	/* TODO: reuse incoming transaction for reply */
-	t = kzalloc(sizeof(*t), GFP_KERNEL);
-	if (t == NULL) {
-		return_error = BR_FAILED_REPLY;
-		return_error_param = -ENOMEM;
-		return_error_line = __LINE__;
-		goto err_alloc_t_failed;
-	}
-	INIT_LIST_HEAD(&t->fd_fixups);
-	binder_stats_created(BINDER_STAT_TRANSACTION);
-	spin_lock_init(&t->lock);
-
 	tcomplete = kzalloc(sizeof(*tcomplete), GFP_KERNEL);
 	if (tcomplete == NULL) {
+		binder_txn_error("%d:%d cannot allocate work for transaction\n",
+			thread->pid, proc->pid);
 		return_error = BR_FAILED_REPLY;
 		return_error_param = -ENOMEM;
 		return_error_line = __LINE__;
@@ -3073,56 +3327,42 @@ static void binder_transaction(struct binder_proc *proc,
 	}
 	binder_stats_created(BINDER_STAT_TRANSACTION_COMPLETE);
 
-	t->debug_id = t_debug_id;
-
 	if (reply)
 		binder_debug(BINDER_DEBUG_TRANSACTION,
-			     "%d:%d BC_REPLY %d -> %d:%d, data %016llx-%016llx size %lld-%lld-%lld\n",
+			     "%d:%d BC_REPLY %d -> %d:%d, data size %lld-%lld-%lld\n",
 			     proc->pid, thread->pid, t->debug_id,
 			     target_proc->pid, target_thread->pid,
-			     (u64)tr->data.ptr.buffer,
-			     (u64)tr->data.ptr.offsets,
 			     (u64)tr->data_size, (u64)tr->offsets_size,
 			     (u64)extra_buffers_size);
 	else
 		binder_debug(BINDER_DEBUG_TRANSACTION,
-			     "%d:%d BC_TRANSACTION %d -> %d - node %d, data %016llx-%016llx size %lld-%lld-%lld\n",
+			     "%d:%d BC_TRANSACTION %d -> %d - node %d, data size %lld-%lld-%lld\n",
 			     proc->pid, thread->pid, t->debug_id,
 			     target_proc->pid, target_node->debug_id,
-			     (u64)tr->data.ptr.buffer,
-			     (u64)tr->data.ptr.offsets,
 			     (u64)tr->data_size, (u64)tr->offsets_size,
 			     (u64)extra_buffers_size);
 
-	if (!reply && !(tr->flags & TF_ONE_WAY))
-		t->from = thread;
-	else
-		t->from = NULL;
-	t->sender_euid = task_euid(proc->tsk);
-	t->to_proc = target_proc;
-	t->to_thread = target_thread;
-	t->code = tr->code;
-	t->flags = tr->flags;
-	t->priority = task_nice(current);
-
 	if (target_node && target_node->txn_security_ctx) {
 		u32 secid;
 		size_t added_size;
 
-		security_task_getsecid(proc->tsk, &secid);
-		ret = security_secid_to_secctx(secid, &secctx, &secctx_sz);
-		if (ret) {
+		security_cred_getsecid(proc->cred, &secid);
+		ret = security_secid_to_secctx(secid, &lsmctx);
+		if (ret < 0) {
+			binder_txn_error("%d:%d failed to get security context\n",
+				thread->pid, proc->pid);
 			return_error = BR_FAILED_REPLY;
 			return_error_param = ret;
 			return_error_line = __LINE__;
 			goto err_get_secctx_failed;
 		}
-		added_size = ALIGN(secctx_sz, sizeof(u64));
+		added_size = ALIGN(lsmctx.len, sizeof(u64));
 		extra_buffers_size += added_size;
 		if (extra_buffers_size < added_size) {
-			/* integer overflow of extra_buffers_size */
+			binder_txn_error("%d:%d integer overflow of extra_buffers_size\n",
+				thread->pid, proc->pid);
 			return_error = BR_FAILED_REPLY;
-			return_error_param = EINVAL;
+			return_error_param = -EINVAL;
 			return_error_line = __LINE__;
 			goto err_bad_extra_size;
 		}
@@ -3134,9 +3374,15 @@ static void binder_transaction(struct binder_proc *proc,
 		tr->offsets_size, extra_buffers_size,
 		!reply && (t->flags & TF_ONE_WAY));
 	if (IS_ERR(t->buffer)) {
-		/*
-		 * -ESRCH indicates VMA cleared. The target is dying.
-		 */
+		char *s;
+
+		ret = PTR_ERR(t->buffer);
+		s = (ret == -ESRCH) ? ": vma cleared, target dead or dying"
+			: (ret == -ENOSPC) ? ": no space left"
+			: (ret == -ENOMEM) ? ": memory allocation failed"
+			: "";
+		binder_txn_error("cannot allocate buffer%s", s);
+
 		return_error_param = PTR_ERR(t->buffer);
 		return_error = return_error_param == -ESRCH ?
 			BR_DEAD_REPLY : BR_FAILED_REPLY;
@@ -3144,44 +3390,32 @@ static void binder_transaction(struct binder_proc *proc,
 		t->buffer = NULL;
 		goto err_binder_alloc_buf_failed;
 	}
-	if (secctx) {
+	if (lsmctx.context) {
 		int err;
 		size_t buf_offset = ALIGN(tr->data_size, sizeof(void *)) +
 				    ALIGN(tr->offsets_size, sizeof(void *)) +
 				    ALIGN(extra_buffers_size, sizeof(void *)) -
-				    ALIGN(secctx_sz, sizeof(u64));
+				    ALIGN(lsmctx.len, sizeof(u64));
 
-		t->security_ctx = (uintptr_t)t->buffer->user_data + buf_offset;
+		t->security_ctx = t->buffer->user_data + buf_offset;
 		err = binder_alloc_copy_to_buffer(&target_proc->alloc,
 						  t->buffer, buf_offset,
-						  secctx, secctx_sz);
+						  lsmctx.context, lsmctx.len);
 		if (err) {
 			t->security_ctx = 0;
 			WARN_ON(1);
 		}
-		security_release_secctx(secctx, secctx_sz);
-		secctx = NULL;
+		security_release_secctx(&lsmctx);
+		lsmctx.context = NULL;
 	}
 	t->buffer->debug_id = t->debug_id;
 	t->buffer->transaction = t;
 	t->buffer->target_node = target_node;
+	t->buffer->clear_on_free = !!(t->flags & TF_CLEAR_BUF);
 	trace_binder_transaction_alloc_buf(t->buffer);
 
 	if (binder_alloc_copy_user_to_buffer(
 				&target_proc->alloc,
-				t->buffer, 0,
-				(const void __user *)
-					(uintptr_t)tr->data.ptr.buffer,
-				tr->data_size)) {
-		binder_user_error("%d:%d got transaction with invalid data ptr\n",
-				proc->pid, thread->pid);
-		return_error = BR_FAILED_REPLY;
-		return_error_param = -EFAULT;
-		return_error_line = __LINE__;
-		goto err_copy_data_failed;
-	}
-	if (binder_alloc_copy_user_to_buffer(
-				&target_proc->alloc,
 				t->buffer,
 				ALIGN(tr->data_size, sizeof(void *)),
 				(const void __user *)
@@ -3216,7 +3450,7 @@ static void binder_transaction(struct binder_proc *proc,
 	off_end_offset = off_start_offset + tr->offsets_size;
 	sg_buf_offset = ALIGN(off_end_offset, sizeof(void *));
 	sg_buf_end_offset = sg_buf_offset + extra_buffers_size -
-		ALIGN(secctx_sz, sizeof(u64));
+		ALIGN(lsmctx.len, sizeof(u64));
 	off_min = 0;
 	for (buffer_offset = off_start_offset; buffer_offset < off_end_offset;
 	     buffer_offset += sizeof(binder_size_t)) {
@@ -3224,19 +3458,42 @@ static void binder_transaction(struct binder_proc *proc,
 		size_t object_size;
 		struct binder_object object;
 		binder_size_t object_offset;
+		binder_size_t copy_size;
 
 		if (binder_alloc_copy_from_buffer(&target_proc->alloc,
 						  &object_offset,
 						  t->buffer,
 						  buffer_offset,
 						  sizeof(object_offset))) {
+			binder_txn_error("%d:%d copy offset from buffer failed\n",
+				thread->pid, proc->pid);
 			return_error = BR_FAILED_REPLY;
 			return_error_param = -EINVAL;
 			return_error_line = __LINE__;
 			goto err_bad_offset;
 		}
-		object_size = binder_get_object(target_proc, t->buffer,
-						object_offset, &object);
+
+		/*
+		 * Copy the source user buffer up to the next object
+		 * that will be processed.
+		 */
+		copy_size = object_offset - user_offset;
+		if (copy_size && (user_offset > object_offset ||
+				object_offset > tr->data_size ||
+				binder_alloc_copy_user_to_buffer(
+					&target_proc->alloc,
+					t->buffer, user_offset,
+					user_buffer + user_offset,
+					copy_size))) {
+			binder_user_error("%d:%d got transaction with invalid data ptr\n",
+					proc->pid, thread->pid);
+			return_error = BR_FAILED_REPLY;
+			return_error_param = -EFAULT;
+			return_error_line = __LINE__;
+			goto err_copy_data_failed;
+		}
+		object_size = binder_get_object(target_proc, user_buffer,
+				t->buffer, object_offset, &object);
 		if (object_size == 0 || object_offset < off_min) {
 			binder_user_error("%d:%d got transaction with invalid offset (%lld, min %lld max %lld) or object.\n",
 					  proc->pid, thread->pid,
@@ -3248,6 +3505,11 @@ static void binder_transaction(struct binder_proc *proc,
 			return_error_line = __LINE__;
 			goto err_bad_offset;
 		}
+		/*
+		 * Set offset to the next buffer fragment to be
+		 * copied
+		 */
+		user_offset = object_offset + object_size;
 
 		hdr = &object.hdr;
 		off_min = object_offset + object_size;
@@ -3264,6 +3526,8 @@ static void binder_transaction(struct binder_proc *proc,
 							t->buffer,
 							object_offset,
 							fp, sizeof(*fp))) {
+				binder_txn_error("%d:%d translate binder failed\n",
+					thread->pid, proc->pid);
 				return_error = BR_FAILED_REPLY;
 				return_error_param = ret;
 				return_error_line = __LINE__;
@@ -3281,6 +3545,8 @@ static void binder_transaction(struct binder_proc *proc,
 							t->buffer,
 							object_offset,
 							fp, sizeof(*fp))) {
+				binder_txn_error("%d:%d translate handle failed\n",
+					thread->pid, proc->pid);
 				return_error = BR_FAILED_REPLY;
 				return_error_param = ret;
 				return_error_line = __LINE__;
@@ -3301,6 +3567,8 @@ static void binder_transaction(struct binder_proc *proc,
 							t->buffer,
 							object_offset,
 							fp, sizeof(*fp))) {
+				binder_txn_error("%d:%d translate fd failed\n",
+					thread->pid, proc->pid);
 				return_error = BR_FAILED_REPLY;
 				return_error_param = ret;
 				return_error_line = __LINE__;
@@ -3310,6 +3578,8 @@ static void binder_transaction(struct binder_proc *proc,
 		case BINDER_TYPE_FDA: {
 			struct binder_object ptr_object;
 			binder_size_t parent_offset;
+			struct binder_object user_object;
+			size_t user_parent_size;
 			struct binder_fd_array_object *fda =
 				to_binder_fd_array_object(hdr);
 			size_t num_valid = (buffer_offset - off_start_offset) /
@@ -3341,11 +3611,37 @@ static void binder_transaction(struct binder_proc *proc,
 				return_error_line = __LINE__;
 				goto err_bad_parent;
 			}
-			ret = binder_translate_fd_array(fda, parent, t, thread,
-							in_reply_to);
-			if (ret < 0) {
+			/*
+			 * We need to read the user version of the parent
+			 * object to get the original user offset
+			 */
+			user_parent_size =
+				binder_get_object(proc, user_buffer, t->buffer,
+						  parent_offset, &user_object);
+			if (user_parent_size != sizeof(user_object.bbo)) {
+				binder_user_error("%d:%d invalid ptr object size: %zd vs %zd\n",
+						  proc->pid, thread->pid,
+						  user_parent_size,
+						  sizeof(user_object.bbo));
 				return_error = BR_FAILED_REPLY;
-				return_error_param = ret;
+				return_error_param = -EINVAL;
+				return_error_line = __LINE__;
+				goto err_bad_parent;
+			}
+			ret = binder_translate_fd_array(&pf_head, fda,
+							user_buffer, parent,
+							&user_object.bbo, t,
+							thread, in_reply_to);
+			if (!ret)
+				ret = binder_alloc_copy_to_buffer(&target_proc->alloc,
+								  t->buffer,
+								  object_offset,
+								  fda, sizeof(*fda));
+			if (ret) {
+				binder_txn_error("%d:%d translate fd array failed\n",
+					thread->pid, proc->pid);
+				return_error = BR_FAILED_REPLY;
+				return_error_param = ret > 0 ? -EINVAL : ret;
 				return_error_line = __LINE__;
 				goto err_translate_failed;
 			}
@@ -3367,28 +3663,25 @@ static void binder_transaction(struct binder_proc *proc,
 				return_error_line = __LINE__;
 				goto err_bad_offset;
 			}
-			if (binder_alloc_copy_user_to_buffer(
-						&target_proc->alloc,
-						t->buffer,
-						sg_buf_offset,
-						(const void __user *)
-							(uintptr_t)bp->buffer,
-						bp->length)) {
-				binder_user_error("%d:%d got transaction with invalid offsets ptr\n",
-						  proc->pid, thread->pid);
-				return_error_param = -EFAULT;
+			ret = binder_defer_copy(&sgc_head, sg_buf_offset,
+				(const void __user *)(uintptr_t)bp->buffer,
+				bp->length);
+			if (ret) {
+				binder_txn_error("%d:%d deferred copy failed\n",
+					thread->pid, proc->pid);
 				return_error = BR_FAILED_REPLY;
+				return_error_param = ret;
 				return_error_line = __LINE__;
-				goto err_copy_data_failed;
+				goto err_translate_failed;
 			}
 			/* Fixup buffer pointer to target proc address space */
-			bp->buffer = (uintptr_t)
-				t->buffer->user_data + sg_buf_offset;
+			bp->buffer = t->buffer->user_data + sg_buf_offset;
 			sg_buf_offset += ALIGN(bp->length, sizeof(u64));
 
 			num_valid = (buffer_offset - off_start_offset) /
 					sizeof(binder_size_t);
-			ret = binder_fixup_parent(t, thread, bp,
+			ret = binder_fixup_parent(&pf_head, t,
+						  thread, bp,
 						  off_start_offset,
 						  num_valid,
 						  last_fixup_obj_off,
@@ -3398,6 +3691,8 @@ static void binder_transaction(struct binder_proc *proc,
 							t->buffer,
 							object_offset,
 							bp, sizeof(*bp))) {
+				binder_txn_error("%d:%d failed to fixup parent\n",
+					thread->pid, proc->pid);
 				return_error = BR_FAILED_REPLY;
 				return_error_param = ret;
 				return_error_line = __LINE__;
@@ -3415,19 +3710,50 @@ static void binder_transaction(struct binder_proc *proc,
 			goto err_bad_object_type;
 		}
 	}
-	tcomplete->type = BINDER_WORK_TRANSACTION_COMPLETE;
-	t->work.type = BINDER_WORK_TRANSACTION;
+	/* Done processing objects, copy the rest of the buffer */
+	if (binder_alloc_copy_user_to_buffer(
+				&target_proc->alloc,
+				t->buffer, user_offset,
+				user_buffer + user_offset,
+				tr->data_size - user_offset)) {
+		binder_user_error("%d:%d got transaction with invalid data ptr\n",
+				proc->pid, thread->pid);
+		return_error = BR_FAILED_REPLY;
+		return_error_param = -EFAULT;
+		return_error_line = __LINE__;
+		goto err_copy_data_failed;
+	}
+
+	ret = binder_do_deferred_txn_copies(&target_proc->alloc, t->buffer,
+					    &sgc_head, &pf_head);
+	if (ret) {
+		binder_user_error("%d:%d got transaction with invalid offsets ptr\n",
+				  proc->pid, thread->pid);
+		return_error = BR_FAILED_REPLY;
+		return_error_param = ret;
+		return_error_line = __LINE__;
+		goto err_copy_data_failed;
+	}
+	if (t->buffer->oneway_spam_suspect) {
+		tcomplete->type = BINDER_WORK_TRANSACTION_ONEWAY_SPAM_SUSPECT;
+		binder_netlink_report(proc, t, tr->data_size,
+				      BR_ONEWAY_SPAM_SUSPECT);
+	} else {
+		tcomplete->type = BINDER_WORK_TRANSACTION_COMPLETE;
+	}
 
 	if (reply) {
 		binder_enqueue_thread_work(thread, tcomplete);
 		binder_inner_proc_lock(target_proc);
 		if (target_thread->is_dead) {
+			return_error = BR_DEAD_REPLY;
 			binder_inner_proc_unlock(target_proc);
 			goto err_dead_proc_or_thread;
 		}
 		BUG_ON(t->buffer->async_transaction != 0);
 		binder_pop_transaction_ilocked(target_thread, in_reply_to);
 		binder_enqueue_thread_work_ilocked(target_thread, &t->work);
+		target_proc->outstanding_txns++;
 		binder_inner_proc_unlock(target_proc);
 		wake_up_interruptible_sync(&target_thread->wait);
 		binder_free_transaction(in_reply_to);
@@ -3442,11 +3768,12 @@ static void binder_transaction(struct binder_proc *proc,
 		 * the target replies (or there is an error).
 		 */
 		binder_enqueue_deferred_thread_work_ilocked(thread, tcomplete);
-		t->need_reply = 1;
 		t->from_parent = thread->transaction_stack;
 		thread->transaction_stack = t;
 		binder_inner_proc_unlock(proc);
-		if (!binder_proc_transaction(t, target_proc, target_thread)) {
+		return_error = binder_proc_transaction(t,
+				target_proc, target_thread);
+		if (return_error) {
 			binder_inner_proc_lock(proc);
 			binder_pop_transaction_ilocked(thread, t);
 			binder_inner_proc_unlock(proc);
@@ -3455,8 +3782,20 @@ static void binder_transaction(struct binder_proc *proc,
 	} else {
 		BUG_ON(target_node == NULL);
 		BUG_ON(t->buffer->async_transaction != 1);
+		return_error = binder_proc_transaction(t, target_proc, NULL);
+		/*
+		 * Let the caller know when async transaction reaches a frozen
+		 * process and is put in a pending queue, waiting for the target
+		 * process to be unfrozen.
+		 */
+		if (return_error == BR_TRANSACTION_PENDING_FROZEN) {
+			tcomplete->type = BINDER_WORK_TRANSACTION_PENDING;
+			binder_netlink_report(proc, t, tr->data_size,
+					      return_error);
+		}
 		binder_enqueue_thread_work(thread, tcomplete);
-		if (!binder_proc_transaction(t, target_proc, NULL))
+		if (return_error &&
+		    return_error != BR_TRANSACTION_PENDING_FROZEN)
 			goto err_dead_proc_or_thread;
 	}
 	if (target_thread)
@@ -3473,7 +3812,8 @@ static void binder_transaction(struct binder_proc *proc,
 	return;
 
 err_dead_proc_or_thread:
-	return_error = BR_DEAD_REPLY;
+	binder_txn_error("%d:%d dead process or thread\n",
+		thread->pid, proc->pid);
 	return_error_line = __LINE__;
 	binder_dequeue_work(proc, tcomplete);
 err_translate_failed:
@@ -3481,9 +3821,10 @@ err_bad_object_type:
 err_bad_offset:
 err_bad_parent:
 err_copy_data_failed:
+	binder_cleanup_deferred_txn_lists(&sgc_head, &pf_head);
 	binder_free_txn_fixups(t);
 	trace_binder_transaction_failed_buffer_release(t->buffer);
-	binder_transaction_buffer_release(target_proc, t->buffer,
+	binder_transaction_buffer_release(target_proc, NULL, t->buffer,
 					  buffer_offset, true);
 	if (target_node)
 		binder_dec_node_tmpref(target_node);
@@ -3492,35 +3833,44 @@ err_copy_data_failed:
 	binder_alloc_free_buf(&target_proc->alloc, t->buffer);
 err_binder_alloc_buf_failed:
 err_bad_extra_size:
-	if (secctx)
-		security_release_secctx(secctx, secctx_sz);
+	if (lsmctx.context)
+		security_release_secctx(&lsmctx);
 err_get_secctx_failed:
 	kfree(tcomplete);
 	binder_stats_deleted(BINDER_STAT_TRANSACTION_COMPLETE);
 err_alloc_tcomplete_failed:
-	kfree(t);
-	binder_stats_deleted(BINDER_STAT_TRANSACTION);
-err_alloc_t_failed:
+	if (trace_binder_txn_latency_free_enabled())
+		binder_txn_latency_free(t);
 err_bad_todo_list:
 err_bad_call_stack:
 err_empty_call_stack:
 err_dead_binder:
 err_invalid_target_handle:
-	if (target_thread)
-		binder_thread_dec_tmpref(target_thread);
-	if (target_proc)
-		binder_proc_dec_tmpref(target_proc);
 	if (target_node) {
 		binder_dec_node(target_node, 1, 0);
 		binder_dec_node_tmpref(target_node);
 	}
 
+	binder_netlink_report(proc, t, tr->data_size, return_error);
+	kfree(t);
+	binder_stats_deleted(BINDER_STAT_TRANSACTION);
+err_alloc_t_failed:
+
 	binder_debug(BINDER_DEBUG_FAILED_TRANSACTION,
-		     "%d:%d transaction failed %d/%d, size %lld-%lld line %d\n",
-		     proc->pid, thread->pid, return_error, return_error_param,
-		     (u64)tr->data_size, (u64)tr->offsets_size,
+		     "%d:%d transaction %s to %d:%d failed %d/%d/%d, code %u size %lld-%lld line %d\n",
+		     proc->pid, thread->pid, reply ? "reply" :
+		     (tr->flags & TF_ONE_WAY ? "async" : "call"),
+		     target_proc ? target_proc->pid : 0,
+		     target_thread ? target_thread->pid : 0,
+		     t_debug_id, return_error, return_error_param,
+		     tr->code, (u64)tr->data_size, (u64)tr->offsets_size,
 		     return_error_line);
 
+	if (target_thread)
+		binder_thread_dec_tmpref(target_thread);
+	if (target_proc)
+		binder_proc_dec_tmpref(target_proc);
+
 	{
 		struct binder_transaction_log_entry *fe;
 
@@ -3540,27 +3890,184 @@ err_invalid_target_handle:
 
 	BUG_ON(thread->return_error.cmd != BR_OK);
 	if (in_reply_to) {
+		binder_set_txn_from_error(in_reply_to, t_debug_id,
+				return_error, return_error_param);
 		thread->return_error.cmd = BR_TRANSACTION_COMPLETE;
 		binder_enqueue_thread_work(thread, &thread->return_error.work);
 		binder_send_failed_reply(in_reply_to, return_error);
 	} else {
+		binder_inner_proc_lock(proc);
+		binder_set_extended_error(&thread->ee, t_debug_id,
+				return_error, return_error_param);
+		binder_inner_proc_unlock(proc);
 		thread->return_error.cmd = return_error;
 		binder_enqueue_thread_work(thread, &thread->return_error.work);
 	}
 }
 
+static int
+binder_request_freeze_notification(struct binder_proc *proc,
+				   struct binder_thread *thread,
+				   struct binder_handle_cookie *handle_cookie)
+{
+	struct binder_ref_freeze *freeze;
+	struct binder_ref *ref;
+
+	freeze = kzalloc(sizeof(*freeze), GFP_KERNEL);
+	if (!freeze)
+		return -ENOMEM;
+	binder_proc_lock(proc);
+	ref = binder_get_ref_olocked(proc, handle_cookie->handle, false);
+	if (!ref) {
+		binder_user_error("%d:%d BC_REQUEST_FREEZE_NOTIFICATION invalid ref %d\n",
+				  proc->pid, thread->pid, handle_cookie->handle);
+		binder_proc_unlock(proc);
+		kfree(freeze);
+		return -EINVAL;
+	}
+
+	binder_node_lock(ref->node);
+	if (ref->freeze) {
+		binder_user_error("%d:%d BC_REQUEST_FREEZE_NOTIFICATION already set\n",
+				  proc->pid, thread->pid);
+		binder_node_unlock(ref->node);
+		binder_proc_unlock(proc);
+		kfree(freeze);
+		return -EINVAL;
+	}
+
+	binder_stats_created(BINDER_STAT_FREEZE);
+	INIT_LIST_HEAD(&freeze->work.entry);
+	freeze->cookie = handle_cookie->cookie;
+	freeze->work.type = BINDER_WORK_FROZEN_BINDER;
+	ref->freeze = freeze;
+
+	if (ref->node->proc) {
+		binder_inner_proc_lock(ref->node->proc);
+		freeze->is_frozen = ref->node->proc->is_frozen;
+		binder_inner_proc_unlock(ref->node->proc);
+
+		binder_inner_proc_lock(proc);
+		binder_enqueue_work_ilocked(&freeze->work, &proc->todo);
+		binder_wakeup_proc_ilocked(proc);
+		binder_inner_proc_unlock(proc);
+	}
+
+	binder_node_unlock(ref->node);
+	binder_proc_unlock(proc);
+	return 0;
+}
+
+static int
+binder_clear_freeze_notification(struct binder_proc *proc,
+				 struct binder_thread *thread,
+				 struct binder_handle_cookie *handle_cookie)
+{
+	struct binder_ref_freeze *freeze;
+	struct binder_ref *ref;
+
+	binder_proc_lock(proc);
+	ref = binder_get_ref_olocked(proc, handle_cookie->handle, false);
+	if (!ref) {
+		binder_user_error("%d:%d BC_CLEAR_FREEZE_NOTIFICATION invalid ref %d\n",
+				  proc->pid, thread->pid, handle_cookie->handle);
+		binder_proc_unlock(proc);
+		return -EINVAL;
+	}
+
+	binder_node_lock(ref->node);
+
+	if (!ref->freeze) {
+		binder_user_error("%d:%d BC_CLEAR_FREEZE_NOTIFICATION freeze notification not active\n",
+				  proc->pid, thread->pid);
+		binder_node_unlock(ref->node);
+		binder_proc_unlock(proc);
+		return -EINVAL;
+	}
+	freeze = ref->freeze;
+	binder_inner_proc_lock(proc);
+	if (freeze->cookie != handle_cookie->cookie) {
+		binder_user_error("%d:%d BC_CLEAR_FREEZE_NOTIFICATION freeze notification cookie mismatch %016llx != %016llx\n",
+				  proc->pid, thread->pid, (u64)freeze->cookie,
+				  (u64)handle_cookie->cookie);
+		binder_inner_proc_unlock(proc);
+		binder_node_unlock(ref->node);
+		binder_proc_unlock(proc);
+		return -EINVAL;
+	}
+	ref->freeze = NULL;
+	/*
+	 * Take the existing freeze object and overwrite its work type. There are three cases here:
+	 * 1. No pending notification. In this case just add the work to the queue.
+	 * 2. A notification was sent and is pending an ack from userspace. Once an ack arrives, we
+	 *    should resend with the new work type.
+	 * 3. A notification is pending to be sent. Since the work is already in the queue, nothing
+	 *    needs to be done here.
+	 */
+	freeze->work.type = BINDER_WORK_CLEAR_FREEZE_NOTIFICATION;
+	if (list_empty(&freeze->work.entry)) {
+		binder_enqueue_work_ilocked(&freeze->work, &proc->todo);
+		binder_wakeup_proc_ilocked(proc);
+	} else if (freeze->sent) {
+		freeze->resend = true;
+	}
+	binder_inner_proc_unlock(proc);
+	binder_node_unlock(ref->node);
+	binder_proc_unlock(proc);
+	return 0;
+}
+
+static int
+binder_freeze_notification_done(struct binder_proc *proc,
+				struct binder_thread *thread,
+				binder_uintptr_t cookie)
+{
+	struct binder_ref_freeze *freeze = NULL;
+	struct binder_work *w;
+
+	binder_inner_proc_lock(proc);
+	list_for_each_entry(w, &proc->delivered_freeze, entry) {
+		struct binder_ref_freeze *tmp_freeze =
+			container_of(w, struct binder_ref_freeze, work);
+
+		if (tmp_freeze->cookie == cookie) {
+			freeze = tmp_freeze;
+			break;
+		}
+	}
+	if (!freeze) {
+		binder_user_error("%d:%d BC_FREEZE_NOTIFICATION_DONE %016llx not found\n",
+				  proc->pid, thread->pid, (u64)cookie);
+		binder_inner_proc_unlock(proc);
+		return -EINVAL;
+	}
+	binder_dequeue_work_ilocked(&freeze->work);
+	freeze->sent = false;
+	if (freeze->resend) {
+		freeze->resend = false;
+		binder_enqueue_work_ilocked(&freeze->work, &proc->todo);
+		binder_wakeup_proc_ilocked(proc);
+	}
+	binder_inner_proc_unlock(proc);
+	return 0;
+}
+
 /**
  * binder_free_buf() - free the specified buffer
- * @proc:	binder proc that owns buffer
- * @buffer:	buffer to be freed
+ * @proc:       binder proc that owns buffer
+ * @thread:     binder thread performing the buffer release
+ * @buffer:     buffer to be freed
+ * @is_failure: failed to send transaction
  *
- * If buffer for an async transaction, enqueue the next async
+ * If the buffer is for an async transaction, enqueue the next async
  * transaction from the node.
  *
- * Cleanup buffer and free it.
+ * Cleanup the buffer and free it.
  */
 static void
-binder_free_buf(struct binder_proc *proc, struct binder_buffer *buffer)
+binder_free_buf(struct binder_proc *proc,
+		struct binder_thread *thread,
+		struct binder_buffer *buffer, bool is_failure)
 {
 	binder_inner_proc_lock(proc);
 	if (buffer->transaction) {
@@ -3588,7 +4095,7 @@ binder_free_buf(struct binder_proc *proc, struct binder_buffer *buffer)
 		binder_node_inner_unlock(buf_node);
 	}
 	trace_binder_transaction_buffer_release(buffer);
-	binder_transaction_buffer_release(proc, buffer, 0, false);
+	binder_release_entire_buffer(proc, thread, buffer, is_failure);
 	binder_alloc_free_buf(&proc->alloc, buffer);
 }
 
@@ -3633,12 +4140,20 @@ static int binder_thread_write(struct binder_proc *proc,
 			ret = -1;
 			if (increment && !target) {
 				struct binder_node *ctx_mgr_node;
+
 				mutex_lock(&context->context_mgr_node_lock);
 				ctx_mgr_node = context->binder_context_mgr_node;
-				if (ctx_mgr_node)
+				if (ctx_mgr_node) {
+					if (ctx_mgr_node->proc == proc) {
+						binder_user_error("%d:%d context manager tried to acquire desc 0\n",
+								  proc->pid, thread->pid);
+						mutex_unlock(&context->context_mgr_node_lock);
+						return -EINVAL;
+					}
 					ret = binder_inc_ref_for_node(
 							proc, ctx_mgr_node,
 							strong, NULL, &rdata);
+				}
 				mutex_unlock(&context->context_mgr_node_lock);
 			}
 			if (ret)
@@ -3766,23 +4281,24 @@ static int binder_thread_write(struct binder_proc *proc,
 			if (IS_ERR_OR_NULL(buffer)) {
 				if (PTR_ERR(buffer) == -EPERM) {
 					binder_user_error(
-						"%d:%d BC_FREE_BUFFER u%016llx matched unreturned or currently freeing buffer\n",
+						"%d:%d BC_FREE_BUFFER matched unreturned or currently freeing buffer at offset %lx\n",
 						proc->pid, thread->pid,
-						(u64)data_ptr);
+						(unsigned long)data_ptr - proc->alloc.vm_start);
 				} else {
 					binder_user_error(
-						"%d:%d BC_FREE_BUFFER u%016llx no match\n",
+						"%d:%d BC_FREE_BUFFER no match for buffer at offset %lx\n",
 						proc->pid, thread->pid,
-						(u64)data_ptr);
+						(unsigned long)data_ptr - proc->alloc.vm_start);
 				}
 				break;
 			}
 			binder_debug(BINDER_DEBUG_FREE_BUFFER,
-				     "%d:%d BC_FREE_BUFFER u%016llx found buffer %d for %s transaction\n",
-				     proc->pid, thread->pid, (u64)data_ptr,
+				     "%d:%d BC_FREE_BUFFER at offset %lx found buffer %d for %s transaction\n",
+				     proc->pid, thread->pid,
+				     (unsigned long)data_ptr - proc->alloc.vm_start,
 				     buffer->debug_id,
 				     buffer->transaction ? "active" : "finished");
-			binder_free_buf(proc, buffer);
+			binder_free_buf(proc, thread, buffer, false);
 			break;
 		}
 
@@ -4021,8 +4537,46 @@ static int binder_thread_write(struct binder_proc *proc,
 			binder_inner_proc_unlock(proc);
 		} break;
 
+		case BC_REQUEST_FREEZE_NOTIFICATION: {
+			struct binder_handle_cookie handle_cookie;
+			int error;
+
+			if (copy_from_user(&handle_cookie, ptr, sizeof(handle_cookie)))
+				return -EFAULT;
+			ptr += sizeof(handle_cookie);
+			error = binder_request_freeze_notification(proc, thread,
+								   &handle_cookie);
+			if (error)
+				return error;
+		} break;
+
+		case BC_CLEAR_FREEZE_NOTIFICATION: {
+			struct binder_handle_cookie handle_cookie;
+			int error;
+
+			if (copy_from_user(&handle_cookie, ptr, sizeof(handle_cookie)))
+				return -EFAULT;
+			ptr += sizeof(handle_cookie);
+			error = binder_clear_freeze_notification(proc, thread, &handle_cookie);
+			if (error)
+				return error;
+		} break;
+
+		case BC_FREEZE_NOTIFICATION_DONE: {
+			binder_uintptr_t cookie;
+			int error;
+
+			if (get_user(cookie, (binder_uintptr_t __user *)ptr))
+				return -EFAULT;
+
+			ptr += sizeof(cookie);
+			error = binder_freeze_notification_done(proc, thread, cookie);
+			if (error)
+				return error;
+		} break;
+
 		default:
-			pr_err("%d:%d unknown command %d\n",
+			pr_err("%d:%d unknown command %u\n",
 			       proc->pid, thread->pid, cmd);
 			return -EINVAL;
 		}
@@ -4080,10 +4634,9 @@ static int binder_wait_for_work(struct binder_thread *thread,
 	struct binder_proc *proc = thread->proc;
 	int ret = 0;
 
-	freezer_do_not_count();
 	binder_inner_proc_lock(proc);
 	for (;;) {
-		prepare_to_wait(&thread->wait, &wait, TASK_INTERRUPTIBLE);
+		prepare_to_wait(&thread->wait, &wait, TASK_INTERRUPTIBLE|TASK_FREEZABLE);
 		if (binder_has_work_ilocked(thread, do_proc_work))
 			break;
 		if (do_proc_work)
@@ -4094,13 +4647,12 @@ static int binder_wait_for_work(struct binder_thread *thread,
 		binder_inner_proc_lock(proc);
 		list_del_init(&thread->waiting_thread_node);
 		if (signal_pending(current)) {
-			ret = -ERESTARTSYS;
+			ret = -EINTR;
 			break;
 		}
 	}
 	finish_wait(&thread->wait, &wait);
 	binder_inner_proc_unlock(proc);
-	freezer_count();
 
 	return ret;
 }
@@ -4113,11 +4665,12 @@ static int binder_wait_for_work(struct binder_thread *thread,
  * Now that we are in the context of the transaction target
  * process, we can allocate and install fds. Process the
  * list of fds to translate and fixup the buffer with the
- * new fds.
+ * new fds first and only then install the files.
  *
- * If we fail to allocate an fd, then free the resources by
- * fput'ing files that have not been processed and ksys_close'ing
+ * If we fail to allocate an fd, skip the install and release
  * any fds that have already been allocated.
+ *
+ * Return: 0 on success, a negative errno code on failure.
  */
 static int binder_apply_fd_fixups(struct binder_proc *proc,
 				  struct binder_transaction *t)
@@ -4133,41 +4686,31 @@ static int binder_apply_fd_fixups(struct binder_proc *proc,
 				     "failed fd fixup txn %d fd %d\n",
 				     t->debug_id, fd);
 			ret = -ENOMEM;
-			break;
+			goto err;
 		}
 		binder_debug(BINDER_DEBUG_TRANSACTION,
 			     "fd fixup txn %d fd %d\n",
 			     t->debug_id, fd);
 		trace_binder_transaction_fd_recv(t, fd, fixup->offset);
-		fd_install(fd, fixup->file);
-		fixup->file = NULL;
+		fixup->target_fd = fd;
 		if (binder_alloc_copy_to_buffer(&proc->alloc, t->buffer,
 						fixup->offset, &fd,
 						sizeof(u32))) {
 			ret = -EINVAL;
-			break;
+			goto err;
 		}
 	}
 	list_for_each_entry_safe(fixup, tmp, &t->fd_fixups, fixup_entry) {
-		if (fixup->file) {
-			fput(fixup->file);
-		} else if (ret) {
-			u32 fd;
-			int err;
-
-			err = binder_alloc_copy_from_buffer(&proc->alloc, &fd,
-							    t->buffer,
-							    fixup->offset,
-							    sizeof(fd));
-			WARN_ON(err);
-			if (!err)
-				binder_deferred_fd_close(fd);
-		}
+		fd_install(fixup->target_fd, fixup->file);
 		list_del(&fixup->fixup_entry);
 		kfree(fixup);
 	}
 
 	return ret;
+
+err:
+	binder_free_txn_fixups(t);
+	return ret;
 }
 
 static int binder_thread_read(struct binder_proc *proc,
@@ -4273,9 +4816,17 @@ retry:
 
 			binder_stat_br(proc, thread, cmd);
 		} break;
-		case BINDER_WORK_TRANSACTION_COMPLETE: {
+		case BINDER_WORK_TRANSACTION_COMPLETE:
+		case BINDER_WORK_TRANSACTION_PENDING:
+		case BINDER_WORK_TRANSACTION_ONEWAY_SPAM_SUSPECT: {
+			if (proc->oneway_spam_detection_enabled &&
+				   w->type == BINDER_WORK_TRANSACTION_ONEWAY_SPAM_SUSPECT)
+				cmd = BR_ONEWAY_SPAM_SUSPECT;
+			else if (w->type == BINDER_WORK_TRANSACTION_PENDING)
+				cmd = BR_TRANSACTION_PENDING_FROZEN;
+			else
+				cmd = BR_TRANSACTION_COMPLETE;
 			binder_inner_proc_unlock(proc);
-			cmd = BR_TRANSACTION_COMPLETE;
 			kfree(w);
 			binder_stats_deleted(BINDER_STAT_TRANSACTION_COMPLETE);
 			if (put_user(cmd, (uint32_t __user *)ptr))
@@ -4415,6 +4966,46 @@ retry:
 			if (cmd == BR_DEAD_BINDER)
 				goto done; /* DEAD_BINDER notifications can cause transactions */
 		} break;
+
+		case BINDER_WORK_FROZEN_BINDER: {
+			struct binder_ref_freeze *freeze;
+			struct binder_frozen_state_info info;
+
+			memset(&info, 0, sizeof(info));
+			freeze = container_of(w, struct binder_ref_freeze, work);
+			info.is_frozen = freeze->is_frozen;
+			info.cookie = freeze->cookie;
+			freeze->sent = true;
+			binder_enqueue_work_ilocked(w, &proc->delivered_freeze);
+			binder_inner_proc_unlock(proc);
+
+			if (put_user(BR_FROZEN_BINDER, (uint32_t __user *)ptr))
+				return -EFAULT;
+			ptr += sizeof(uint32_t);
+			if (copy_to_user(ptr, &info, sizeof(info)))
+				return -EFAULT;
+			ptr += sizeof(info);
+			binder_stat_br(proc, thread, BR_FROZEN_BINDER);
+			goto done; /* BR_FROZEN_BINDER notifications can cause transactions */
+		} break;
+
+		case BINDER_WORK_CLEAR_FREEZE_NOTIFICATION: {
+			struct binder_ref_freeze *freeze =
+			    container_of(w, struct binder_ref_freeze, work);
+			binder_uintptr_t cookie = freeze->cookie;
+
+			binder_inner_proc_unlock(proc);
+			kfree(freeze);
+			binder_stats_deleted(BINDER_STAT_FREEZE);
+			if (put_user(BR_CLEAR_FREEZE_NOTIFICATION_DONE, (uint32_t __user *)ptr))
+				return -EFAULT;
+			ptr += sizeof(uint32_t);
+			if (put_user(cookie, (binder_uintptr_t __user *)ptr))
+				return -EFAULT;
+			ptr += sizeof(binder_uintptr_t);
+			binder_stat_br(proc, thread, BR_CLEAR_FREEZE_NOTIFICATION_DONE);
+		} break;
+
 		default:
 			binder_inner_proc_unlock(proc);
 			pr_err("%d:%d: bad work type %d\n",
@@ -4470,7 +5061,7 @@ retry:
 			buffer->transaction = NULL;
 			binder_cleanup_transaction(t, "fd fixups failed",
 						   BR_FAILED_REPLY);
-			binder_free_buf(proc, buffer);
+			binder_free_buf(proc, thread, buffer, true);
 			binder_debug(BINDER_DEBUG_FAILED_TRANSACTION,
 				     "%d:%d %stransaction %d fd fixups failed %d/%d, line %d\n",
 				     proc->pid, thread->pid,
@@ -4489,7 +5080,7 @@ retry:
 		}
 		trd->data_size = t->buffer->data_size;
 		trd->offsets_size = t->buffer->offsets_size;
-		trd->data.ptr.buffer = (uintptr_t)t->buffer->user_data;
+		trd->data.ptr.buffer = t->buffer->user_data;
 		trd->data.ptr.offsets = trd->data.ptr.buffer +
 					ALIGN(t->buffer->data_size,
 					    sizeof(void *));
@@ -4523,16 +5114,14 @@ retry:
 		trace_binder_transaction_received(t);
 		binder_stat_br(proc, thread, cmd);
 		binder_debug(BINDER_DEBUG_TRANSACTION,
-			     "%d:%d %s %d %d:%d, cmd %d size %zd-%zd ptr %016llx-%016llx\n",
+			     "%d:%d %s %d %d:%d, cmd %u size %zd-%zd\n",
 			     proc->pid, thread->pid,
 			     (cmd == BR_TRANSACTION) ? "BR_TRANSACTION" :
 				(cmd == BR_TRANSACTION_SEC_CTX) ?
 				     "BR_TRANSACTION_SEC_CTX" : "BR_REPLY",
 			     t->debug_id, t_from ? t_from->proc->pid : 0,
 			     t_from ? t_from->pid : 0, cmd,
-			     t->buffer->data_size, t->buffer->offsets_size,
-			     (u64)trd->data.ptr.buffer,
-			     (u64)trd->data.ptr.offsets);
+			     t->buffer->data_size, t->buffer->offsets_size);
 
 		if (t_from)
 			binder_thread_dec_tmpref(t_from);
@@ -4576,13 +5165,17 @@ static void binder_release_work(struct binder_proc *proc,
 				struct list_head *list)
 {
 	struct binder_work *w;
+	enum binder_work_type wtype;
 
 	while (1) {
-		w = binder_dequeue_work_head(proc, list);
+		binder_inner_proc_lock(proc);
+		w = binder_dequeue_work_head_ilocked(list);
+		wtype = w ? w->type : 0;
+		binder_inner_proc_unlock(proc);
 		if (!w)
 			return;
 
-		switch (w->type) {
+		switch (wtype) {
 		case BINDER_WORK_TRANSACTION: {
 			struct binder_transaction *t;
 
@@ -4599,6 +5192,8 @@ static void binder_release_work(struct binder_proc *proc,
 				"undelivered TRANSACTION_ERROR: %u\n",
 				e->cmd);
 		} break;
+		case BINDER_WORK_TRANSACTION_PENDING:
+		case BINDER_WORK_TRANSACTION_ONEWAY_SPAM_SUSPECT:
 		case BINDER_WORK_TRANSACTION_COMPLETE: {
 			binder_debug(BINDER_DEBUG_DEAD_TRANSACTION,
 				"undelivered TRANSACTION_COMPLETE\n");
@@ -4616,9 +5211,21 @@ static void binder_release_work(struct binder_proc *proc,
 			kfree(death);
 			binder_stats_deleted(BINDER_STAT_DEATH);
 		} break;
+		case BINDER_WORK_NODE:
+			break;
+		case BINDER_WORK_CLEAR_FREEZE_NOTIFICATION: {
+			struct binder_ref_freeze *freeze;
+
+			freeze = container_of(w, struct binder_ref_freeze, work);
+			binder_debug(BINDER_DEBUG_DEAD_TRANSACTION,
+				     "undelivered freeze notification, %016llx\n",
+				     (u64)freeze->cookie);
+			kfree(freeze);
+			binder_stats_deleted(BINDER_STAT_FREEZE);
+		} break;
 		default:
 			pr_err("unexpected work type, %d, not freed\n",
-			       w->type);
+			       wtype);
 			break;
 		}
 	}
@@ -4659,6 +5266,7 @@ static struct binder_thread *binder_get_thread_ilocked(
 	thread->return_error.cmd = BR_OK;
 	thread->reply_error.work.type = BINDER_WORK_RETURN_ERROR;
 	thread->reply_error.cmd = BR_OK;
+	thread->ee.command = BR_OK;
 	INIT_LIST_HEAD(&new_thread->waiting_thread_node);
 	return thread;
 }
@@ -4686,11 +5294,24 @@ static struct binder_thread *binder_get_thread(struct binder_proc *proc)
 
 static void binder_free_proc(struct binder_proc *proc)
 {
+	struct binder_device *device;
+
 	BUG_ON(!list_empty(&proc->todo));
 	BUG_ON(!list_empty(&proc->delivered_death));
+	if (proc->outstanding_txns)
+		pr_warn("%s: Unexpected outstanding_txns %d\n",
+			__func__, proc->outstanding_txns);
+	device = container_of(proc->context, struct binder_device, context);
+	if (refcount_dec_and_test(&device->ref)) {
+		binder_remove_device(device);
+		kfree(proc->context->name);
+		kfree(device);
+	}
 	binder_alloc_deferred_release(&proc->alloc);
 	put_task_struct(proc->tsk);
+	put_cred(proc->cred);
 	binder_stats_deleted(BINDER_STAT_PROC);
+	dbitmap_free(&proc->dmap);
 	kfree(proc);
 }
 
@@ -4744,6 +5365,7 @@ static int binder_thread_release(struct binder_proc *proc,
 			     (t->to_thread == thread) ? "in" : "out");
 
 		if (t->to_thread == thread) {
+			thread->proc->outstanding_txns--;
 			t->to_proc = NULL;
 			t->to_thread = NULL;
 			if (t->buffer) {
@@ -4766,23 +5388,20 @@ static int binder_thread_release(struct binder_proc *proc,
 	__release(&t->lock);
 
 	/*
-	 * If this thread used poll, make sure we remove the waitqueue
-	 * from any epoll data structures holding it with POLLFREE.
-	 * waitqueue_active() is safe to use here because we're holding
-	 * the inner lock.
+	 * If this thread used poll, make sure we remove the waitqueue from any
+	 * poll data structures holding it.
 	 */
-	if ((thread->looper & BINDER_LOOPER_STATE_POLL) &&
-	    waitqueue_active(&thread->wait)) {
-		wake_up_poll(&thread->wait, EPOLLHUP | POLLFREE);
-	}
+	if (thread->looper & BINDER_LOOPER_STATE_POLL)
+		wake_up_pollfree(&thread->wait);
 
 	binder_inner_proc_unlock(thread->proc);
 
 	/*
-	 * This is needed to avoid races between wake_up_poll() above and
-	 * and ep_remove_waitqueue() called for other reasons (eg the epoll file
-	 * descriptor being closed); ep_remove_waitqueue() holds an RCU read
-	 * lock, so we can be sure it's done after calling synchronize_rcu().
+	 * This is needed to avoid races between wake_up_pollfree() above and
+	 * someone else removing the last entry from the queue for other reasons
+	 * (e.g. ep_remove_wait_queue() being called due to an epoll file
+	 * descriptor being closed).  Such other users hold an RCU read lock, so
+	 * we can be sure they're done after we call synchronize_rcu().
 	 */
 	if (thread->looper & BINDER_LOOPER_STATE_POLL)
 		synchronize_rcu();
@@ -4803,7 +5422,7 @@ static __poll_t binder_poll(struct file *filp,
 
 	thread = binder_get_thread(proc);
 	if (!thread)
-		return POLLERR;
+		return EPOLLERR;
 
 	binder_inner_proc_lock(thread->proc);
 	thread->looper |= BINDER_LOOPER_STATE_POLL;
@@ -4819,24 +5438,17 @@ static __poll_t binder_poll(struct file *filp,
 	return 0;
 }
 
-static int binder_ioctl_write_read(struct file *filp,
-				unsigned int cmd, unsigned long arg,
+static int binder_ioctl_write_read(struct file *filp, unsigned long arg,
 				struct binder_thread *thread)
 {
 	int ret = 0;
 	struct binder_proc *proc = filp->private_data;
-	unsigned int size = _IOC_SIZE(cmd);
 	void __user *ubuf = (void __user *)arg;
 	struct binder_write_read bwr;
 
-	if (size != sizeof(struct binder_write_read)) {
-		ret = -EINVAL;
-		goto out;
-	}
-	if (copy_from_user(&bwr, ubuf, sizeof(bwr))) {
-		ret = -EFAULT;
-		goto out;
-	}
+	if (copy_from_user(&bwr, ubuf, sizeof(bwr)))
+		return -EFAULT;
+
 	binder_debug(BINDER_DEBUG_READ_WRITE,
 		     "%d:%d write %lld at %016llx, read %lld at %016llx\n",
 		     proc->pid, thread->pid,
@@ -4851,8 +5463,6 @@ static int binder_ioctl_write_read(struct file *filp,
 		trace_binder_write_done(ret);
 		if (ret < 0) {
 			bwr.read_consumed = 0;
-			if (copy_to_user(ubuf, &bwr, sizeof(bwr)))
-				ret = -EFAULT;
 			goto out;
 		}
 	}
@@ -4866,22 +5476,17 @@ static int binder_ioctl_write_read(struct file *filp,
 		if (!binder_worklist_empty_ilocked(&proc->todo))
 			binder_wakeup_proc_ilocked(proc);
 		binder_inner_proc_unlock(proc);
-		if (ret < 0) {
-			if (copy_to_user(ubuf, &bwr, sizeof(bwr)))
-				ret = -EFAULT;
+		if (ret < 0)
 			goto out;
-		}
 	}
 	binder_debug(BINDER_DEBUG_READ_WRITE,
 		     "%d:%d wrote %lld of %lld, read return %lld of %lld\n",
 		     proc->pid, thread->pid,
 		     (u64)bwr.write_consumed, (u64)bwr.write_size,
 		     (u64)bwr.read_consumed, (u64)bwr.read_size);
-	if (copy_to_user(ubuf, &bwr, sizeof(bwr))) {
-		ret = -EFAULT;
-		goto out;
-	}
 out:
+	if (copy_to_user(ubuf, &bwr, sizeof(bwr)))
+		ret = -EFAULT;
 	return ret;
 }
 
@@ -4894,32 +5499,28 @@ static int binder_ioctl_set_ctx_mgr(struct file *filp,
 	struct binder_node *new_node;
 	kuid_t curr_euid = current_euid();
 
-	mutex_lock(&context->context_mgr_node_lock);
+	guard(mutex)(&context->context_mgr_node_lock);
 	if (context->binder_context_mgr_node) {
 		pr_err("BINDER_SET_CONTEXT_MGR already set\n");
-		ret = -EBUSY;
-		goto out;
+		return -EBUSY;
 	}
-	ret = security_binder_set_context_mgr(proc->tsk);
+	ret = security_binder_set_context_mgr(proc->cred);
 	if (ret < 0)
-		goto out;
+		return ret;
 	if (uid_valid(context->binder_context_mgr_uid)) {
 		if (!uid_eq(context->binder_context_mgr_uid, curr_euid)) {
 			pr_err("BINDER_SET_CONTEXT_MGR bad uid %d != %d\n",
 			       from_kuid(&init_user_ns, curr_euid),
 			       from_kuid(&init_user_ns,
 					 context->binder_context_mgr_uid));
-			ret = -EPERM;
-			goto out;
+			return -EPERM;
 		}
 	} else {
 		context->binder_context_mgr_uid = curr_euid;
 	}
 	new_node = binder_new_node(proc, fbo);
-	if (!new_node) {
-		ret = -ENOMEM;
-		goto out;
-	}
+	if (!new_node)
+		return -ENOMEM;
 	binder_node_lock(new_node);
 	new_node->local_weak_refs++;
 	new_node->local_strong_refs++;
@@ -4928,8 +5529,6 @@ static int binder_ioctl_set_ctx_mgr(struct file *filp,
 	context->binder_context_mgr_node = new_node;
 	binder_node_unlock(new_node);
 	binder_put_node(new_node);
-out:
-	mutex_unlock(&context->context_mgr_node_lock);
 	return ret;
 }
 
@@ -4994,19 +5593,177 @@ static int binder_ioctl_get_node_debug_info(struct binder_proc *proc,
 	return 0;
 }
 
+static bool binder_txns_pending_ilocked(struct binder_proc *proc)
+{
+	struct rb_node *n;
+	struct binder_thread *thread;
+
+	if (proc->outstanding_txns > 0)
+		return true;
+
+	for (n = rb_first(&proc->threads); n; n = rb_next(n)) {
+		thread = rb_entry(n, struct binder_thread, rb_node);
+		if (thread->transaction_stack)
+			return true;
+	}
+	return false;
+}
+
+static void binder_add_freeze_work(struct binder_proc *proc, bool is_frozen)
+{
+	struct binder_node *prev = NULL;
+	struct rb_node *n;
+	struct binder_ref *ref;
+
+	binder_inner_proc_lock(proc);
+	for (n = rb_first(&proc->nodes); n; n = rb_next(n)) {
+		struct binder_node *node;
+
+		node = rb_entry(n, struct binder_node, rb_node);
+		binder_inc_node_tmpref_ilocked(node);
+		binder_inner_proc_unlock(proc);
+		if (prev)
+			binder_put_node(prev);
+		binder_node_lock(node);
+		hlist_for_each_entry(ref, &node->refs, node_entry) {
+			/*
+			 * Need the node lock to synchronize
+			 * with new notification requests and the
+			 * inner lock to synchronize with queued
+			 * freeze notifications.
+			 */
+			binder_inner_proc_lock(ref->proc);
+			if (!ref->freeze) {
+				binder_inner_proc_unlock(ref->proc);
+				continue;
+			}
+			ref->freeze->work.type = BINDER_WORK_FROZEN_BINDER;
+			if (list_empty(&ref->freeze->work.entry)) {
+				ref->freeze->is_frozen = is_frozen;
+				binder_enqueue_work_ilocked(&ref->freeze->work, &ref->proc->todo);
+				binder_wakeup_proc_ilocked(ref->proc);
+			} else {
+				if (ref->freeze->sent && ref->freeze->is_frozen != is_frozen)
+					ref->freeze->resend = true;
+				ref->freeze->is_frozen = is_frozen;
+			}
+			binder_inner_proc_unlock(ref->proc);
+		}
+		prev = node;
+		binder_node_unlock(node);
+		binder_inner_proc_lock(proc);
+		if (proc->is_dead)
+			break;
+	}
+	binder_inner_proc_unlock(proc);
+	if (prev)
+		binder_put_node(prev);
+}
+
+static int binder_ioctl_freeze(struct binder_freeze_info *info,
+			       struct binder_proc *target_proc)
+{
+	int ret = 0;
+
+	if (!info->enable) {
+		binder_inner_proc_lock(target_proc);
+		target_proc->sync_recv = false;
+		target_proc->async_recv = false;
+		target_proc->is_frozen = false;
+		binder_inner_proc_unlock(target_proc);
+		binder_add_freeze_work(target_proc, false);
+		return 0;
+	}
+
+	/*
+	 * Freezing the target. Prevent new transactions by
+	 * setting frozen state. If timeout specified, wait
+	 * for transactions to drain.
+	 */
+	binder_inner_proc_lock(target_proc);
+	target_proc->sync_recv = false;
+	target_proc->async_recv = false;
+	target_proc->is_frozen = true;
+	binder_inner_proc_unlock(target_proc);
+
+	if (info->timeout_ms > 0)
+		ret = wait_event_interruptible_timeout(
+			target_proc->freeze_wait,
+			(!target_proc->outstanding_txns),
+			msecs_to_jiffies(info->timeout_ms));
+
+	/* Check pending transactions that wait for reply */
+	if (ret >= 0) {
+		binder_inner_proc_lock(target_proc);
+		if (binder_txns_pending_ilocked(target_proc))
+			ret = -EAGAIN;
+		binder_inner_proc_unlock(target_proc);
+	}
+
+	if (ret < 0) {
+		binder_inner_proc_lock(target_proc);
+		target_proc->is_frozen = false;
+		binder_inner_proc_unlock(target_proc);
+	} else {
+		binder_add_freeze_work(target_proc, true);
+	}
+
+	return ret;
+}
+
+static int binder_ioctl_get_freezer_info(
+				struct binder_frozen_status_info *info)
+{
+	struct binder_proc *target_proc;
+	bool found = false;
+	__u32 txns_pending;
+
+	info->sync_recv = 0;
+	info->async_recv = 0;
+
+	mutex_lock(&binder_procs_lock);
+	hlist_for_each_entry(target_proc, &binder_procs, proc_node) {
+		if (target_proc->pid == info->pid) {
+			found = true;
+			binder_inner_proc_lock(target_proc);
+			txns_pending = binder_txns_pending_ilocked(target_proc);
+			info->sync_recv |= target_proc->sync_recv |
+					(txns_pending << 1);
+			info->async_recv |= target_proc->async_recv;
+			binder_inner_proc_unlock(target_proc);
+		}
+	}
+	mutex_unlock(&binder_procs_lock);
+
+	if (!found)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int binder_ioctl_get_extended_error(struct binder_thread *thread,
+					   void __user *ubuf)
+{
+	struct binder_extended_error ee;
+
+	binder_inner_proc_lock(thread->proc);
+	ee = thread->ee;
+	binder_set_extended_error(&thread->ee, 0, BR_OK, 0);
+	binder_inner_proc_unlock(thread->proc);
+
+	if (copy_to_user(ubuf, &ee, sizeof(ee)))
+		return -EFAULT;
+
+	return 0;
+}
+
 static long binder_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
 {
 	int ret;
 	struct binder_proc *proc = filp->private_data;
 	struct binder_thread *thread;
-	unsigned int size = _IOC_SIZE(cmd);
 	void __user *ubuf = (void __user *)arg;
 
-	/*pr_info("binder_ioctl: %d:%d %x %lx\n",
-			proc->pid, current->pid, cmd, arg);*/
-
-	binder_selftest_alloc(&proc->alloc);
-
 	trace_binder_ioctl(cmd, arg);
 
 	ret = wait_event_interruptible(binder_user_error_wait, binder_stop_on_user_error < 2);
@@ -5021,12 +5778,12 @@ static long binder_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
 
 	switch (cmd) {
 	case BINDER_WRITE_READ:
-		ret = binder_ioctl_write_read(filp, cmd, arg, thread);
+		ret = binder_ioctl_write_read(filp, arg, thread);
 		if (ret)
 			goto err;
 		break;
 	case BINDER_SET_MAX_THREADS: {
-		int max_threads;
+		u32 max_threads;
 
 		if (copy_from_user(&max_threads, ubuf,
 				   sizeof(max_threads))) {
@@ -5064,10 +5821,6 @@ static long binder_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
 	case BINDER_VERSION: {
 		struct binder_version __user *ver = ubuf;
 
-		if (size != sizeof(struct binder_version)) {
-			ret = -EINVAL;
-			goto err;
-		}
 		if (put_user(BINDER_CURRENT_PROTOCOL_VERSION,
 			     &ver->protocol_version)) {
 			ret = -EINVAL;
@@ -5112,6 +5865,101 @@ static long binder_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
 		}
 		break;
 	}
+	case BINDER_FREEZE: {
+		struct binder_freeze_info info;
+		struct binder_proc **target_procs = NULL, *target_proc;
+		int target_procs_count = 0, i = 0;
+
+		ret = 0;
+
+		if (copy_from_user(&info, ubuf, sizeof(info))) {
+			ret = -EFAULT;
+			goto err;
+		}
+
+		mutex_lock(&binder_procs_lock);
+		hlist_for_each_entry(target_proc, &binder_procs, proc_node) {
+			if (target_proc->pid == info.pid)
+				target_procs_count++;
+		}
+
+		if (target_procs_count == 0) {
+			mutex_unlock(&binder_procs_lock);
+			ret = -EINVAL;
+			goto err;
+		}
+
+		target_procs = kcalloc(target_procs_count,
+				       sizeof(struct binder_proc *),
+				       GFP_KERNEL);
+
+		if (!target_procs) {
+			mutex_unlock(&binder_procs_lock);
+			ret = -ENOMEM;
+			goto err;
+		}
+
+		hlist_for_each_entry(target_proc, &binder_procs, proc_node) {
+			if (target_proc->pid != info.pid)
+				continue;
+
+			binder_inner_proc_lock(target_proc);
+			target_proc->tmp_ref++;
+			binder_inner_proc_unlock(target_proc);
+
+			target_procs[i++] = target_proc;
+		}
+		mutex_unlock(&binder_procs_lock);
+
+		for (i = 0; i < target_procs_count; i++) {
+			if (ret >= 0)
+				ret = binder_ioctl_freeze(&info,
+							  target_procs[i]);
+
+			binder_proc_dec_tmpref(target_procs[i]);
+		}
+
+		kfree(target_procs);
+
+		if (ret < 0)
+			goto err;
+		break;
+	}
+	case BINDER_GET_FROZEN_INFO: {
+		struct binder_frozen_status_info info;
+
+		if (copy_from_user(&info, ubuf, sizeof(info))) {
+			ret = -EFAULT;
+			goto err;
+		}
+
+		ret = binder_ioctl_get_freezer_info(&info);
+		if (ret < 0)
+			goto err;
+
+		if (copy_to_user(ubuf, &info, sizeof(info))) {
+			ret = -EFAULT;
+			goto err;
+		}
+		break;
+	}
+	case BINDER_ENABLE_ONEWAY_SPAM_DETECTION: {
+		uint32_t enable;
+
+		if (copy_from_user(&enable, ubuf, sizeof(enable))) {
+			ret = -EFAULT;
+			goto err;
+		}
+		binder_inner_proc_lock(proc);
+		proc->oneway_spam_detection_enabled = (bool)enable;
+		binder_inner_proc_unlock(proc);
+		break;
+	}
+	case BINDER_GET_EXTENDED_ERROR:
+		ret = binder_ioctl_get_extended_error(thread, ubuf);
+		if (ret < 0)
+			goto err;
+		break;
 	default:
 		ret = -EINVAL;
 		goto err;
@@ -5121,7 +5969,7 @@ err:
 	if (thread)
 		thread->looper_need_return = false;
 	wait_event_interruptible(binder_user_error_wait, binder_stop_on_user_error < 2);
-	if (ret && ret != -ERESTARTSYS)
+	if (ret && ret != -EINTR)
 		pr_info("%d:%d ioctl %x %lx returned %d\n", proc->pid, current->pid, cmd, arg, ret);
 err_unlocked:
 	trace_binder_ioctl_done(ret);
@@ -5151,10 +5999,11 @@ static void binder_vma_close(struct vm_area_struct *vma)
 	binder_alloc_vma_close(&proc->alloc);
 }
 
-static vm_fault_t binder_vm_fault(struct vm_fault *vmf)
+VISIBLE_IF_KUNIT vm_fault_t binder_vm_fault(struct vm_fault *vmf)
 {
 	return VM_FAULT_SIGBUS;
 }
+EXPORT_SYMBOL_IF_KUNIT(binder_vm_fault);
 
 static const struct vm_operations_struct binder_vm_ops = {
 	.open = binder_vma_open,
@@ -5164,9 +6013,7 @@ static const struct vm_operations_struct binder_vm_ops = {
 
 static int binder_mmap(struct file *filp, struct vm_area_struct *vma)
 {
-	int ret;
 	struct binder_proc *proc = filp->private_data;
-	const char *failure_string;
 
 	if (proc->tsk != current->group_leader)
 		return -EINVAL;
@@ -5178,25 +6025,16 @@ static int binder_mmap(struct file *filp, struct vm_area_struct *vma)
 		     (unsigned long)pgprot_val(vma->vm_page_prot));
 
 	if (vma->vm_flags & FORBIDDEN_MMAP_FLAGS) {
-		ret = -EPERM;
-		failure_string = "bad vm_flags";
-		goto err_bad_arg;
+		pr_err("%s: %d %lx-%lx %s failed %d\n", __func__,
+		       proc->pid, vma->vm_start, vma->vm_end, "bad vm_flags", -EPERM);
+		return -EPERM;
 	}
-	vma->vm_flags |= VM_DONTCOPY | VM_MIXEDMAP;
-	vma->vm_flags &= ~VM_MAYWRITE;
+	vm_flags_mod(vma, VM_DONTCOPY | VM_MIXEDMAP, VM_MAYWRITE);
 
 	vma->vm_ops = &binder_vm_ops;
 	vma->vm_private_data = proc;
 
-	ret = binder_alloc_mmap_handler(&proc->alloc, vma);
-	if (ret)
-		return ret;
-	return 0;
-
-err_bad_arg:
-	pr_err("%s: %d %lx-%lx %s failed %d\n", __func__,
-	       proc->pid, vma->vm_start, vma->vm_end, failure_string, ret);
-	return ret;
+	return binder_alloc_mmap_handler(&proc->alloc, vma);
 }
 
 static int binder_open(struct inode *nodp, struct file *filp)
@@ -5213,11 +6051,15 @@ static int binder_open(struct inode *nodp, struct file *filp)
 	proc = kzalloc(sizeof(*proc), GFP_KERNEL);
 	if (proc == NULL)
 		return -ENOMEM;
+
+	dbitmap_init(&proc->dmap);
 	spin_lock_init(&proc->inner_lock);
 	spin_lock_init(&proc->outer_lock);
 	get_task_struct(current->group_leader);
 	proc->tsk = current->group_leader;
+	proc->cred = get_cred(filp->f_cred);
 	INIT_LIST_HEAD(&proc->todo);
+	init_waitqueue_head(&proc->freeze_wait);
 	proc->default_priority = task_nice(current);
 	/* binderfs stashes devices in i_private */
 	if (is_binderfs_device(nodp)) {
@@ -5235,6 +6077,7 @@ static int binder_open(struct inode *nodp, struct file *filp)
 	binder_stats_created(BINDER_STAT_PROC);
 	proc->pid = current->group_leader->pid;
 	INIT_LIST_HEAD(&proc->delivered_death);
+	INIT_LIST_HEAD(&proc->delivered_freeze);
 	INIT_LIST_HEAD(&proc->waiting_threads);
 	filp->private_data = proc;
 
@@ -5329,7 +6172,7 @@ static int binder_release(struct inode *nodp, struct file *filp)
 	debugfs_remove(proc->debugfs_entry);
 
 	if (proc->binderfs_entry) {
-		binderfs_remove_file(proc->binderfs_entry);
+		simple_recursive_removal(proc->binderfs_entry, NULL);
 		proc->binderfs_entry = NULL;
 	}
 
@@ -5406,7 +6249,6 @@ static int binder_node_release(struct binder_node *node, int refs)
 static void binder_deferred_release(struct binder_proc *proc)
 {
 	struct binder_context *context = proc->context;
-	struct binder_device *device;
 	struct rb_node *n;
 	int threads, nodes, incoming_refs, outgoing_refs, active_transactions;
 
@@ -5423,12 +6265,6 @@ static void binder_deferred_release(struct binder_proc *proc)
 		context->binder_context_mgr_node = NULL;
 	}
 	mutex_unlock(&context->context_mgr_node_lock);
-	device = container_of(proc->context, struct binder_device, context);
-	if (refcount_dec_and_test(&device->ref)) {
-		kfree(context->name);
-		kfree(device);
-	}
-	proc->context = NULL;
 	binder_inner_proc_lock(proc);
 	/*
 	 * Make sure proc stays alive after we
@@ -5437,6 +6273,9 @@ static void binder_deferred_release(struct binder_proc *proc)
 	proc->tmp_ref++;
 
 	proc->is_dead = true;
+	proc->is_frozen = false;
+	proc->sync_recv = false;
+	proc->async_recv = false;
 	threads = 0;
 	active_transactions = 0;
 	while ((n = rb_first(&proc->threads))) {
@@ -5485,6 +6324,7 @@ static void binder_deferred_release(struct binder_proc *proc)
 
 	binder_release_work(proc, &proc->todo);
 	binder_release_work(proc, &proc->delivered_death);
+	binder_release_work(proc, &proc->delivered_freeze);
 
 	binder_debug(BINDER_DEBUG_OPEN_CLOSE,
 		     "%s: %d threads %d, nodes %d (ref %d), refs %d, active transactions %d\n",
@@ -5526,14 +6366,13 @@ static DECLARE_WORK(binder_deferred_work, binder_deferred_func);
 static void
 binder_defer_work(struct binder_proc *proc, enum binder_deferred_state defer)
 {
-	mutex_lock(&binder_deferred_lock);
+	guard(mutex)(&binder_deferred_lock);
 	proc->deferred_work |= defer;
 	if (hlist_unhashed(&proc->deferred_work_node)) {
 		hlist_add_head(&proc->deferred_work_node,
 				&binder_deferred_list);
 		schedule_work(&binder_deferred_work);
 	}
-	mutex_unlock(&binder_deferred_lock);
 }
 
 static void print_binder_transaction_ilocked(struct seq_file *m,
@@ -5543,17 +6382,19 @@ static void print_binder_transaction_ilocked(struct seq_file *m,
 {
 	struct binder_proc *to_proc;
 	struct binder_buffer *buffer = t->buffer;
+	ktime_t current_time = ktime_get();
 
 	spin_lock(&t->lock);
 	to_proc = t->to_proc;
 	seq_printf(m,
-		   "%s %d: %pK from %d:%d to %d:%d code %x flags %x pri %ld r%d",
+		   "%s %d: %pK from %d:%d to %d:%d code %x flags %x pri %ld a%d r%d elapsed %lldms",
 		   prefix, t->debug_id, t,
-		   t->from ? t->from->proc->pid : 0,
-		   t->from ? t->from->pid : 0,
+		   t->from_pid,
+		   t->from_tid,
 		   to_proc ? to_proc->pid : 0,
 		   t->to_thread ? t->to_thread->pid : 0,
-		   t->code, t->flags, t->priority, t->need_reply);
+		   t->code, t->flags, t->priority, t->is_async, t->is_reply,
+		   ktime_ms_delta(current_time, t->start_time));
 	spin_unlock(&t->lock);
 
 	if (proc != to_proc) {
@@ -5571,16 +6412,16 @@ static void print_binder_transaction_ilocked(struct seq_file *m,
 	}
 	if (buffer->target_node)
 		seq_printf(m, " node %d", buffer->target_node->debug_id);
-	seq_printf(m, " size %zd:%zd data %pK\n",
+	seq_printf(m, " size %zd:%zd offset %lx\n",
 		   buffer->data_size, buffer->offsets_size,
-		   buffer->user_data);
+		   buffer->user_data - proc->alloc.vm_start);
 }
 
 static void print_binder_work_ilocked(struct seq_file *m,
-				     struct binder_proc *proc,
-				     const char *prefix,
-				     const char *transaction_prefix,
-				     struct binder_work *w)
+				      struct binder_proc *proc,
+				      const char *prefix,
+				      const char *transaction_prefix,
+				      struct binder_work *w, bool hash_ptrs)
 {
 	struct binder_node *node;
 	struct binder_transaction *t;
@@ -5603,9 +6444,15 @@ static void print_binder_work_ilocked(struct seq_file *m,
 		break;
 	case BINDER_WORK_NODE:
 		node = container_of(w, struct binder_node, work);
-		seq_printf(m, "%snode work %d: u%016llx c%016llx\n",
-			   prefix, node->debug_id,
-			   (u64)node->ptr, (u64)node->cookie);
+		if (hash_ptrs)
+			seq_printf(m, "%snode work %d: u%p c%p\n",
+				   prefix, node->debug_id,
+				   (void *)(long)node->ptr,
+				   (void *)(long)node->cookie);
+		else
+			seq_printf(m, "%snode work %d: u%016llx c%016llx\n",
+				   prefix, node->debug_id,
+				   (u64)node->ptr, (u64)node->cookie);
 		break;
 	case BINDER_WORK_DEAD_BINDER:
 		seq_printf(m, "%shas dead binder\n", prefix);
@@ -5616,6 +6463,12 @@ static void print_binder_work_ilocked(struct seq_file *m,
 	case BINDER_WORK_CLEAR_DEATH_NOTIFICATION:
 		seq_printf(m, "%shas cleared death notification\n", prefix);
 		break;
+	case BINDER_WORK_FROZEN_BINDER:
+		seq_printf(m, "%shas frozen binder\n", prefix);
+		break;
+	case BINDER_WORK_CLEAR_FREEZE_NOTIFICATION:
+		seq_printf(m, "%shas cleared freeze notification\n", prefix);
+		break;
 	default:
 		seq_printf(m, "%sunknown work: type %d\n", prefix, w->type);
 		break;
@@ -5624,7 +6477,7 @@ static void print_binder_work_ilocked(struct seq_file *m,
 
 static void print_binder_thread_ilocked(struct seq_file *m,
 					struct binder_thread *thread,
-					int print_always)
+					bool print_always, bool hash_ptrs)
 {
 	struct binder_transaction *t;
 	struct binder_work *w;
@@ -5654,25 +6507,30 @@ static void print_binder_thread_ilocked(struct seq_file *m,
 	}
 	list_for_each_entry(w, &thread->todo, entry) {
 		print_binder_work_ilocked(m, thread->proc, "    ",
-					  "    pending transaction", w);
+					  "    pending transaction",
+					  w, hash_ptrs);
 	}
 	if (!print_always && m->count == header_pos)
 		m->count = start_pos;
 }
 
 static void print_binder_node_nilocked(struct seq_file *m,
-				       struct binder_node *node)
+				       struct binder_node *node,
+				       bool hash_ptrs)
 {
 	struct binder_ref *ref;
 	struct binder_work *w;
 	int count;
 
-	count = 0;
-	hlist_for_each_entry(ref, &node->refs, node_entry)
-		count++;
+	count = hlist_count_nodes(&node->refs);
 
-	seq_printf(m, "  node %d: u%016llx c%016llx hs %d hw %d ls %d lw %d is %d iw %d tr %d",
-		   node->debug_id, (u64)node->ptr, (u64)node->cookie,
+	if (hash_ptrs)
+		seq_printf(m, "  node %d: u%p c%p", node->debug_id,
+			   (void *)(long)node->ptr, (void *)(long)node->cookie);
+	else
+		seq_printf(m, "  node %d: u%016llx c%016llx", node->debug_id,
+			   (u64)node->ptr, (u64)node->cookie);
+	seq_printf(m, " hs %d hw %d ls %d lw %d is %d iw %d tr %d",
 		   node->has_strong_ref, node->has_weak_ref,
 		   node->local_strong_refs, node->local_weak_refs,
 		   node->internal_strong_refs, count, node->tmp_refs);
@@ -5685,7 +6543,8 @@ static void print_binder_node_nilocked(struct seq_file *m,
 	if (node->proc) {
 		list_for_each_entry(w, &node->async_todo, entry)
 			print_binder_work_ilocked(m, node->proc, "    ",
-					  "    pending async transaction", w);
+					  "    pending async transaction",
+					  w, hash_ptrs);
 	}
 }
 
@@ -5701,8 +6560,54 @@ static void print_binder_ref_olocked(struct seq_file *m,
 	binder_node_unlock(ref->node);
 }
 
-static void print_binder_proc(struct seq_file *m,
-			      struct binder_proc *proc, int print_all)
+/**
+ * print_next_binder_node_ilocked() - Print binder_node from a locked list
+ * @m:          struct seq_file for output via seq_printf()
+ * @proc:       struct binder_proc we hold the inner_proc_lock to (if any)
+ * @node:       struct binder_node to print fields of
+ * @prev_node:	struct binder_node we hold a temporary reference to (if any)
+ * @hash_ptrs:  whether to hash @node's binder_uintptr_t fields
+ *
+ * Helper function to handle synchronization around printing a struct
+ * binder_node while iterating through @proc->nodes or the dead nodes list.
+ * Caller must hold either @proc->inner_lock (for live nodes) or
+ * binder_dead_nodes_lock. This lock will be released during the body of this
+ * function, but it will be reacquired before returning to the caller.
+ *
+ * Return:	pointer to the struct binder_node we hold a tmpref on
+ */
+static struct binder_node *
+print_next_binder_node_ilocked(struct seq_file *m, struct binder_proc *proc,
+			       struct binder_node *node,
+			       struct binder_node *prev_node, bool hash_ptrs)
+{
+	/*
+	 * Take a temporary reference on the node so that isn't freed while
+	 * we print it.
+	 */
+	binder_inc_node_tmpref_ilocked(node);
+	/*
+	 * Live nodes need to drop the inner proc lock and dead nodes need to
+	 * drop the binder_dead_nodes_lock before trying to take the node lock.
+	 */
+	if (proc)
+		binder_inner_proc_unlock(proc);
+	else
+		spin_unlock(&binder_dead_nodes_lock);
+	if (prev_node)
+		binder_put_node(prev_node);
+	binder_node_inner_lock(node);
+	print_binder_node_nilocked(m, node, hash_ptrs);
+	binder_node_inner_unlock(node);
+	if (proc)
+		binder_inner_proc_lock(proc);
+	else
+		spin_lock(&binder_dead_nodes_lock);
+	return node;
+}
+
+static void print_binder_proc(struct seq_file *m, struct binder_proc *proc,
+			      bool print_all, bool hash_ptrs)
 {
 	struct binder_work *w;
 	struct rb_node *n;
@@ -5715,31 +6620,19 @@ static void print_binder_proc(struct seq_file *m,
 	header_pos = m->count;
 
 	binder_inner_proc_lock(proc);
-	for (n = rb_first(&proc->threads); n != NULL; n = rb_next(n))
+	for (n = rb_first(&proc->threads); n; n = rb_next(n))
 		print_binder_thread_ilocked(m, rb_entry(n, struct binder_thread,
-						rb_node), print_all);
+						rb_node), print_all, hash_ptrs);
 
-	for (n = rb_first(&proc->nodes); n != NULL; n = rb_next(n)) {
+	for (n = rb_first(&proc->nodes); n; n = rb_next(n)) {
 		struct binder_node *node = rb_entry(n, struct binder_node,
 						    rb_node);
 		if (!print_all && !node->has_async_transaction)
 			continue;
 
-		/*
-		 * take a temporary reference on the node so it
-		 * survives and isn't removed from the tree
-		 * while we print it.
-		 */
-		binder_inc_node_tmpref_ilocked(node);
-		/* Need to drop inner lock to take node lock */
-		binder_inner_proc_unlock(proc);
-		if (last_node)
-			binder_put_node(last_node);
-		binder_node_inner_lock(node);
-		print_binder_node_nilocked(m, node);
-		binder_node_inner_unlock(node);
-		last_node = node;
-		binder_inner_proc_lock(proc);
+		last_node = print_next_binder_node_ilocked(m, proc, node,
+							   last_node,
+							   hash_ptrs);
 	}
 	binder_inner_proc_unlock(proc);
 	if (last_node)
@@ -5747,23 +6640,26 @@ static void print_binder_proc(struct seq_file *m,
 
 	if (print_all) {
 		binder_proc_lock(proc);
-		for (n = rb_first(&proc->refs_by_desc);
-		     n != NULL;
-		     n = rb_next(n))
+		for (n = rb_first(&proc->refs_by_desc); n; n = rb_next(n))
 			print_binder_ref_olocked(m, rb_entry(n,
-							    struct binder_ref,
-							    rb_node_desc));
+							     struct binder_ref,
+							     rb_node_desc));
 		binder_proc_unlock(proc);
 	}
 	binder_alloc_print_allocated(m, &proc->alloc);
 	binder_inner_proc_lock(proc);
 	list_for_each_entry(w, &proc->todo, entry)
 		print_binder_work_ilocked(m, proc, "  ",
-					  "  pending transaction", w);
+					  "  pending transaction", w,
+					  hash_ptrs);
 	list_for_each_entry(w, &proc->delivered_death, entry) {
 		seq_puts(m, "  has delivered dead binder\n");
 		break;
 	}
+	list_for_each_entry(w, &proc->delivered_freeze, entry) {
+		seq_puts(m, "  has delivered freeze binder\n");
+		break;
+	}
 	binder_inner_proc_unlock(proc);
 	if (!print_all && m->count == header_pos)
 		m->count = start_pos;
@@ -5787,7 +6683,12 @@ static const char * const binder_return_strings[] = {
 	"BR_FINISHED",
 	"BR_DEAD_BINDER",
 	"BR_CLEAR_DEATH_NOTIFICATION_DONE",
-	"BR_FAILED_REPLY"
+	"BR_FAILED_REPLY",
+	"BR_FROZEN_REPLY",
+	"BR_ONEWAY_SPAM_SUSPECT",
+	"BR_TRANSACTION_PENDING_FROZEN",
+	"BR_FROZEN_BINDER",
+	"BR_CLEAR_FREEZE_NOTIFICATION_DONE",
 };
 
 static const char * const binder_command_strings[] = {
@@ -5810,6 +6711,9 @@ static const char * const binder_command_strings[] = {
 	"BC_DEAD_BINDER_DONE",
 	"BC_TRANSACTION_SG",
 	"BC_REPLY_SG",
+	"BC_REQUEST_FREEZE_NOTIFICATION",
+	"BC_CLEAR_FREEZE_NOTIFICATION",
+	"BC_FREEZE_NOTIFICATION_DONE",
 };
 
 static const char * const binder_objstat_strings[] = {
@@ -5819,7 +6723,8 @@ static const char * const binder_objstat_strings[] = {
 	"ref",
 	"death",
 	"transaction",
-	"transaction_complete"
+	"transaction_complete",
+	"freeze",
 };
 
 static void print_binder_stats(struct seq_file *m, const char *prefix,
@@ -5879,7 +6784,7 @@ static void print_binder_proc_stats(struct seq_file *m,
 	count = 0;
 	ready_threads = 0;
 	binder_inner_proc_lock(proc);
-	for (n = rb_first(&proc->threads); n != NULL; n = rb_next(n))
+	for (n = rb_first(&proc->threads); n; n = rb_next(n))
 		count++;
 
 	list_for_each_entry(thread, &proc->waiting_threads, waiting_thread_node)
@@ -5893,7 +6798,7 @@ static void print_binder_proc_stats(struct seq_file *m,
 			ready_threads,
 			free_async_space);
 	count = 0;
-	for (n = rb_first(&proc->nodes); n != NULL; n = rb_next(n))
+	for (n = rb_first(&proc->nodes); n; n = rb_next(n))
 		count++;
 	binder_inner_proc_unlock(proc);
 	seq_printf(m, "  nodes: %d\n", count);
@@ -5901,7 +6806,7 @@ static void print_binder_proc_stats(struct seq_file *m,
 	strong = 0;
 	weak = 0;
 	binder_proc_lock(proc);
-	for (n = rb_first(&proc->refs_by_desc); n != NULL; n = rb_next(n)) {
+	for (n = rb_first(&proc->refs_by_desc); n; n = rb_next(n)) {
 		struct binder_ref *ref = rb_entry(n, struct binder_ref,
 						  rb_node_desc);
 		count++;
@@ -5928,8 +6833,7 @@ static void print_binder_proc_stats(struct seq_file *m,
 	print_binder_stats(m, "  ", &proc->stats);
 }
 
-
-int binder_state_show(struct seq_file *m, void *unused)
+static void print_binder_state(struct seq_file *m, bool hash_ptrs)
 {
 	struct binder_proc *proc;
 	struct binder_node *node;
@@ -5940,35 +6844,44 @@ int binder_state_show(struct seq_file *m, void *unused)
 	spin_lock(&binder_dead_nodes_lock);
 	if (!hlist_empty(&binder_dead_nodes))
 		seq_puts(m, "dead nodes:\n");
-	hlist_for_each_entry(node, &binder_dead_nodes, dead_node) {
-		/*
-		 * take a temporary reference on the node so it
-		 * survives and isn't removed from the list
-		 * while we print it.
-		 */
-		node->tmp_refs++;
-		spin_unlock(&binder_dead_nodes_lock);
-		if (last_node)
-			binder_put_node(last_node);
-		binder_node_lock(node);
-		print_binder_node_nilocked(m, node);
-		binder_node_unlock(node);
-		last_node = node;
-		spin_lock(&binder_dead_nodes_lock);
-	}
+	hlist_for_each_entry(node, &binder_dead_nodes, dead_node)
+		last_node = print_next_binder_node_ilocked(m, NULL, node,
+							   last_node,
+							   hash_ptrs);
 	spin_unlock(&binder_dead_nodes_lock);
 	if (last_node)
 		binder_put_node(last_node);
 
 	mutex_lock(&binder_procs_lock);
 	hlist_for_each_entry(proc, &binder_procs, proc_node)
-		print_binder_proc(m, proc, 1);
+		print_binder_proc(m, proc, true, hash_ptrs);
 	mutex_unlock(&binder_procs_lock);
+}
 
+static void print_binder_transactions(struct seq_file *m, bool hash_ptrs)
+{
+	struct binder_proc *proc;
+
+	seq_puts(m, "binder transactions:\n");
+	mutex_lock(&binder_procs_lock);
+	hlist_for_each_entry(proc, &binder_procs, proc_node)
+		print_binder_proc(m, proc, false, hash_ptrs);
+	mutex_unlock(&binder_procs_lock);
+}
+
+static int state_show(struct seq_file *m, void *unused)
+{
+	print_binder_state(m, false);
 	return 0;
 }
 
-int binder_stats_show(struct seq_file *m, void *unused)
+static int state_hashed_show(struct seq_file *m, void *unused)
+{
+	print_binder_state(m, true);
+	return 0;
+}
+
+static int stats_show(struct seq_file *m, void *unused)
 {
 	struct binder_proc *proc;
 
@@ -5984,16 +6897,15 @@ int binder_stats_show(struct seq_file *m, void *unused)
 	return 0;
 }
 
-int binder_transactions_show(struct seq_file *m, void *unused)
+static int transactions_show(struct seq_file *m, void *unused)
 {
-	struct binder_proc *proc;
-
-	seq_puts(m, "binder transactions:\n");
-	mutex_lock(&binder_procs_lock);
-	hlist_for_each_entry(proc, &binder_procs, proc_node)
-		print_binder_proc(m, proc, 0);
-	mutex_unlock(&binder_procs_lock);
+	print_binder_transactions(m, false);
+	return 0;
+}
 
+static int transactions_hashed_show(struct seq_file *m, void *unused)
+{
+	print_binder_transactions(m, true);
 	return 0;
 }
 
@@ -6002,14 +6914,13 @@ static int proc_show(struct seq_file *m, void *unused)
 	struct binder_proc *itr;
 	int pid = (unsigned long)m->private;
 
-	mutex_lock(&binder_procs_lock);
+	guard(mutex)(&binder_procs_lock);
 	hlist_for_each_entry(itr, &binder_procs, proc_node) {
 		if (itr->pid == pid) {
 			seq_puts(m, "binder proc state:\n");
-			print_binder_proc(m, itr, 1);
+			print_binder_proc(m, itr, true, false);
 		}
 	}
-	mutex_unlock(&binder_procs_lock);
 
 	return 0;
 }
@@ -6040,7 +6951,7 @@ static void print_binder_transaction_log_entry(struct seq_file *m,
 			"\n" : " (incomplete)\n");
 }
 
-int binder_transaction_log_show(struct seq_file *m, void *unused)
+static int transaction_log_show(struct seq_file *m, void *unused)
 {
 	struct binder_transaction_log *log = m->private;
 	unsigned int log_cur = atomic_read(&log->cur);
@@ -6072,6 +6983,71 @@ const struct file_operations binder_fops = {
 	.release = binder_release,
 };
 
+DEFINE_SHOW_ATTRIBUTE(state);
+DEFINE_SHOW_ATTRIBUTE(state_hashed);
+DEFINE_SHOW_ATTRIBUTE(stats);
+DEFINE_SHOW_ATTRIBUTE(transactions);
+DEFINE_SHOW_ATTRIBUTE(transactions_hashed);
+DEFINE_SHOW_ATTRIBUTE(transaction_log);
+
+const struct binder_debugfs_entry binder_debugfs_entries[] = {
+	{
+		.name = "state",
+		.mode = 0444,
+		.fops = &state_fops,
+		.data = NULL,
+	},
+	{
+		.name = "state_hashed",
+		.mode = 0444,
+		.fops = &state_hashed_fops,
+		.data = NULL,
+	},
+	{
+		.name = "stats",
+		.mode = 0444,
+		.fops = &stats_fops,
+		.data = NULL,
+	},
+	{
+		.name = "transactions",
+		.mode = 0444,
+		.fops = &transactions_fops,
+		.data = NULL,
+	},
+	{
+		.name = "transactions_hashed",
+		.mode = 0444,
+		.fops = &transactions_hashed_fops,
+		.data = NULL,
+	},
+	{
+		.name = "transaction_log",
+		.mode = 0444,
+		.fops = &transaction_log_fops,
+		.data = &binder_transaction_log,
+	},
+	{
+		.name = "failed_transaction_log",
+		.mode = 0444,
+		.fops = &transaction_log_fops,
+		.data = &binder_transaction_log_failed,
+	},
+	{} /* terminator */
+};
+
+void binder_add_device(struct binder_device *device)
+{
+	guard(spinlock)(&binder_devices_lock);
+	hlist_add_head(&device->hlist, &binder_devices);
+}
+
+void binder_remove_device(struct binder_device *device)
+{
+	guard(spinlock)(&binder_devices_lock);
+	hlist_del_init(&device->hlist);
+}
+
 static int __init init_binder_device(const char *name)
 {
 	int ret;
@@ -6096,7 +7072,7 @@ static int __init init_binder_device(const char *name)
 		return ret;
 	}
 
-	hlist_add_head(&binder_device->hlist, &binder_devices);
+	binder_add_device(binder_device);
 
 	return ret;
 }
@@ -6108,6 +7084,7 @@ static int __init binder_init(void)
 	struct binder_device *device;
 	struct hlist_node *tmp;
 	char *device_names = NULL;
+	const struct binder_debugfs_entry *db_entry;
 
 	ret = binder_alloc_shrinker_init();
 	if (ret)
@@ -6117,37 +7094,16 @@ static int __init binder_init(void)
 	atomic_set(&binder_transaction_log_failed.cur, ~0U);
 
 	binder_debugfs_dir_entry_root = debugfs_create_dir("binder", NULL);
-	if (binder_debugfs_dir_entry_root)
-		binder_debugfs_dir_entry_proc = debugfs_create_dir("proc",
-						 binder_debugfs_dir_entry_root);
-
-	if (binder_debugfs_dir_entry_root) {
-		debugfs_create_file("state",
-				    0444,
-				    binder_debugfs_dir_entry_root,
-				    NULL,
-				    &binder_state_fops);
-		debugfs_create_file("stats",
-				    0444,
-				    binder_debugfs_dir_entry_root,
-				    NULL,
-				    &binder_stats_fops);
-		debugfs_create_file("transactions",
-				    0444,
-				    binder_debugfs_dir_entry_root,
-				    NULL,
-				    &binder_transactions_fops);
-		debugfs_create_file("transaction_log",
-				    0444,
-				    binder_debugfs_dir_entry_root,
-				    &binder_transaction_log,
-				    &binder_transaction_log_fops);
-		debugfs_create_file("failed_transaction_log",
-				    0444,
-				    binder_debugfs_dir_entry_root,
-				    &binder_transaction_log_failed,
-				    &binder_transaction_log_fops);
-	}
+
+	binder_for_each_debugfs_entry(db_entry)
+		debugfs_create_file(db_entry->name,
+					db_entry->mode,
+					binder_debugfs_dir_entry_root,
+					db_entry->data,
+					db_entry->fops);
+
+	binder_debugfs_dir_entry_proc = debugfs_create_dir("proc",
+						binder_debugfs_dir_entry_root);
 
 	if (!IS_ENABLED(CONFIG_ANDROID_BINDERFS) &&
 	    strcmp(binder_devices_param, "") != 0) {
@@ -6169,16 +7125,23 @@ static int __init binder_init(void)
 		}
 	}
 
-	ret = init_binderfs();
+	ret = genl_register_family(&binder_nl_family);
 	if (ret)
 		goto err_init_binder_device_failed;
 
+	ret = init_binderfs();
+	if (ret)
+		goto err_init_binderfs_failed;
+
 	return ret;
 
+err_init_binderfs_failed:
+	genl_unregister_family(&binder_nl_family);
+
 err_init_binder_device_failed:
 	hlist_for_each_entry_safe(device, tmp, &binder_devices, hlist) {
 		misc_deregister(&device->miscdev);
-		hlist_del(&device->hlist);
+		binder_remove_device(device);
 		kfree(device);
 	}
 
@@ -6186,6 +7149,7 @@ err_init_binder_device_failed:
 
 err_alloc_device_names_failed:
 	debugfs_remove_recursive(binder_debugfs_dir_entry_root);
+	binder_alloc_shrinker_exit();
 
 	return ret;
 }
@@ -6194,5 +7158,3 @@ device_initcall(binder_init);
 
 #define CREATE_TRACE_POINTS
 #include "binder_trace.h"
-
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/android/binder/Makefile b/drivers/android/binder/Makefile
new file mode 100644
index 000000000000..09eabb527fa0
--- /dev/null
+++ b/drivers/android/binder/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-only
+ccflags-y += -I$(src)	# needed for trace events
+
+obj-$(CONFIG_ANDROID_BINDER_IPC_RUST) += rust_binder.o
+rust_binder-y := \
+	rust_binder_main.o	\
+	rust_binderfs.o		\
+	rust_binder_events.o	\
+	page_range_helper.o
diff --git a/drivers/android/binder/allocation.rs b/drivers/android/binder/allocation.rs
new file mode 100644
index 000000000000..7f65a9c3a0e5
--- /dev/null
+++ b/drivers/android/binder/allocation.rs
@@ -0,0 +1,602 @@
+// SPDX-License-Identifier: GPL-2.0
+
+// Copyright (C) 2025 Google LLC.
+
+use core::mem::{size_of, size_of_val, MaybeUninit};
+use core::ops::Range;
+
+use kernel::{
+    bindings,
+    fs::file::{File, FileDescriptorReservation},
+    prelude::*,
+    sync::{aref::ARef, Arc},
+    transmute::{AsBytes, FromBytes},
+    uaccess::UserSliceReader,
+    uapi,
+};
+
+use crate::{
+    deferred_close::DeferredFdCloser,
+    defs::*,
+    node::{Node, NodeRef},
+    process::Process,
+    DArc,
+};
+
+#[derive(Default)]
+pub(crate) struct AllocationInfo {
+    /// Range within the allocation where we can find the offsets to the object descriptors.
+    pub(crate) offsets: Option<Range<usize>>,
+    /// The target node of the transaction this allocation is associated to.
+    /// Not set for replies.
+    pub(crate) target_node: Option<NodeRef>,
+    /// When this allocation is dropped, call `pending_oneway_finished` on the node.
+    ///
+    /// This is used to serialize oneway transaction on the same node. Binder guarantees that
+    /// oneway transactions to the same node are delivered sequentially in the order they are sent.
+    pub(crate) oneway_node: Option<DArc<Node>>,
+    /// Zero the data in the buffer on free.
+    pub(crate) clear_on_free: bool,
+    /// List of files embedded in this transaction.
+    file_list: FileList,
+}
+
+/// Represents an allocation that the kernel is currently using.
+///
+/// When allocations are idle, the range allocator holds the data related to them.
+///
+/// # Invariants
+///
+/// This allocation corresponds to an allocation in the range allocator, so the relevant pages are
+/// marked in use in the page range.
+pub(crate) struct Allocation {
+    pub(crate) offset: usize,
+    size: usize,
+    pub(crate) ptr: usize,
+    pub(crate) process: Arc<Process>,
+    allocation_info: Option<AllocationInfo>,
+    free_on_drop: bool,
+    pub(crate) oneway_spam_detected: bool,
+    #[allow(dead_code)]
+    pub(crate) debug_id: usize,
+}
+
+impl Allocation {
+    pub(crate) fn new(
+        process: Arc<Process>,
+        debug_id: usize,
+        offset: usize,
+        size: usize,
+        ptr: usize,
+        oneway_spam_detected: bool,
+    ) -> Self {
+        Self {
+            process,
+            offset,
+            size,
+            ptr,
+            debug_id,
+            oneway_spam_detected,
+            allocation_info: None,
+            free_on_drop: true,
+        }
+    }
+
+    fn size_check(&self, offset: usize, size: usize) -> Result {
+        let overflow_fail = offset.checked_add(size).is_none();
+        let cmp_size_fail = offset.wrapping_add(size) > self.size;
+        if overflow_fail || cmp_size_fail {
+            return Err(EFAULT);
+        }
+        Ok(())
+    }
+
+    pub(crate) fn copy_into(
+        &self,
+        reader: &mut UserSliceReader,
+        offset: usize,
+        size: usize,
+    ) -> Result {
+        self.size_check(offset, size)?;
+
+        // SAFETY: While this object exists, the range allocator will keep the range allocated, and
+        // in turn, the pages will be marked as in use.
+        unsafe {
+            self.process
+                .pages
+                .copy_from_user_slice(reader, self.offset + offset, size)
+        }
+    }
+
+    pub(crate) fn read<T: FromBytes>(&self, offset: usize) -> Result<T> {
+        self.size_check(offset, size_of::<T>())?;
+
+        // SAFETY: While this object exists, the range allocator will keep the range allocated, and
+        // in turn, the pages will be marked as in use.
+        unsafe { self.process.pages.read(self.offset + offset) }
+    }
+
+    pub(crate) fn write<T: ?Sized>(&self, offset: usize, obj: &T) -> Result {
+        self.size_check(offset, size_of_val::<T>(obj))?;
+
+        // SAFETY: While this object exists, the range allocator will keep the range allocated, and
+        // in turn, the pages will be marked as in use.
+        unsafe { self.process.pages.write(self.offset + offset, obj) }
+    }
+
+    pub(crate) fn fill_zero(&self) -> Result {
+        // SAFETY: While this object exists, the range allocator will keep the range allocated, and
+        // in turn, the pages will be marked as in use.
+        unsafe { self.process.pages.fill_zero(self.offset, self.size) }
+    }
+
+    pub(crate) fn keep_alive(mut self) {
+        self.process
+            .buffer_make_freeable(self.offset, self.allocation_info.take());
+        self.free_on_drop = false;
+    }
+
+    pub(crate) fn set_info(&mut self, info: AllocationInfo) {
+        self.allocation_info = Some(info);
+    }
+
+    pub(crate) fn get_or_init_info(&mut self) -> &mut AllocationInfo {
+        self.allocation_info.get_or_insert_with(Default::default)
+    }
+
+    pub(crate) fn set_info_offsets(&mut self, offsets: Range<usize>) {
+        self.get_or_init_info().offsets = Some(offsets);
+    }
+
+    pub(crate) fn set_info_oneway_node(&mut self, oneway_node: DArc<Node>) {
+        self.get_or_init_info().oneway_node = Some(oneway_node);
+    }
+
+    pub(crate) fn set_info_clear_on_drop(&mut self) {
+        self.get_or_init_info().clear_on_free = true;
+    }
+
+    pub(crate) fn set_info_target_node(&mut self, target_node: NodeRef) {
+        self.get_or_init_info().target_node = Some(target_node);
+    }
+
+    /// Reserve enough space to push at least `num_fds` fds.
+    pub(crate) fn info_add_fd_reserve(&mut self, num_fds: usize) -> Result {
+        self.get_or_init_info()
+            .file_list
+            .files_to_translate
+            .reserve(num_fds, GFP_KERNEL)?;
+
+        Ok(())
+    }
+
+    pub(crate) fn info_add_fd(
+        &mut self,
+        file: ARef<File>,
+        buffer_offset: usize,
+        close_on_free: bool,
+    ) -> Result {
+        self.get_or_init_info().file_list.files_to_translate.push(
+            FileEntry {
+                file,
+                buffer_offset,
+                close_on_free,
+            },
+            GFP_KERNEL,
+        )?;
+
+        Ok(())
+    }
+
+    pub(crate) fn set_info_close_on_free(&mut self, cof: FdsCloseOnFree) {
+        self.get_or_init_info().file_list.close_on_free = cof.0;
+    }
+
+    pub(crate) fn translate_fds(&mut self) -> Result<TranslatedFds> {
+        let file_list = match self.allocation_info.as_mut() {
+            Some(info) => &mut info.file_list,
+            None => return Ok(TranslatedFds::new()),
+        };
+
+        let files = core::mem::take(&mut file_list.files_to_translate);
+
+        let num_close_on_free = files.iter().filter(|entry| entry.close_on_free).count();
+        let mut close_on_free = KVec::with_capacity(num_close_on_free, GFP_KERNEL)?;
+
+        let mut reservations = KVec::with_capacity(files.len(), GFP_KERNEL)?;
+        for file_info in files {
+            let res = FileDescriptorReservation::get_unused_fd_flags(bindings::O_CLOEXEC)?;
+            let fd = res.reserved_fd();
+            self.write::<u32>(file_info.buffer_offset, &fd)?;
+
+            reservations.push(
+                Reservation {
+                    res,
+                    file: file_info.file,
+                },
+                GFP_KERNEL,
+            )?;
+            if file_info.close_on_free {
+                close_on_free.push(fd, GFP_KERNEL)?;
+            }
+        }
+
+        Ok(TranslatedFds {
+            reservations,
+            close_on_free: FdsCloseOnFree(close_on_free),
+        })
+    }
+
+    /// Should the looper return to userspace when freeing this allocation?
+    pub(crate) fn looper_need_return_on_free(&self) -> bool {
+        // Closing fds involves pushing task_work for execution when we return to userspace. Hence,
+        // we should return to userspace asap if we are closing fds.
+        match self.allocation_info {
+            Some(ref info) => !info.file_list.close_on_free.is_empty(),
+            None => false,
+        }
+    }
+}
+
+impl Drop for Allocation {
+    fn drop(&mut self) {
+        if !self.free_on_drop {
+            return;
+        }
+
+        if let Some(mut info) = self.allocation_info.take() {
+            if let Some(oneway_node) = info.oneway_node.as_ref() {
+                oneway_node.pending_oneway_finished();
+            }
+
+            info.target_node = None;
+
+            if let Some(offsets) = info.offsets.clone() {
+                let view = AllocationView::new(self, offsets.start);
+                for i in offsets.step_by(size_of::<usize>()) {
+                    if view.cleanup_object(i).is_err() {
+                        pr_warn!("Error cleaning up object at offset {}\n", i)
+                    }
+                }
+            }
+
+            for &fd in &info.file_list.close_on_free {
+                let closer = match DeferredFdCloser::new(GFP_KERNEL) {
+                    Ok(closer) => closer,
+                    Err(kernel::alloc::AllocError) => {
+                        // Ignore allocation failures.
+                        break;
+                    }
+                };
+
+                // Here, we ignore errors. The operation can fail if the fd is not valid, or if the
+                // method is called from a kthread. However, this is always called from a syscall,
+                // so the latter case cannot happen, and we don't care about the first case.
+                let _ = closer.close_fd(fd);
+            }
+
+            if info.clear_on_free {
+                if let Err(e) = self.fill_zero() {
+                    pr_warn!("Failed to clear data on free: {:?}", e);
+                }
+            }
+        }
+
+        self.process.buffer_raw_free(self.ptr);
+    }
+}
+
+/// A wrapper around `Allocation` that is being created.
+///
+/// If the allocation is destroyed while wrapped in this wrapper, then the allocation will be
+/// considered to be part of a failed transaction. Successful transactions avoid that by calling
+/// `success`, which skips the destructor.
+#[repr(transparent)]
+pub(crate) struct NewAllocation(pub(crate) Allocation);
+
+impl NewAllocation {
+    pub(crate) fn success(self) -> Allocation {
+        // This skips the destructor.
+        //
+        // SAFETY: This type is `#[repr(transparent)]`, so the layout matches.
+        unsafe { core::mem::transmute(self) }
+    }
+}
+
+impl core::ops::Deref for NewAllocation {
+    type Target = Allocation;
+    fn deref(&self) -> &Allocation {
+        &self.0
+    }
+}
+
+impl core::ops::DerefMut for NewAllocation {
+    fn deref_mut(&mut self) -> &mut Allocation {
+        &mut self.0
+    }
+}
+
+/// A view into the beginning of an allocation.
+///
+/// All attempts to read or write outside of the view will fail. To intentionally access outside of
+/// this view, use the `alloc` field of this struct directly.
+pub(crate) struct AllocationView<'a> {
+    pub(crate) alloc: &'a mut Allocation,
+    limit: usize,
+}
+
+impl<'a> AllocationView<'a> {
+    pub(crate) fn new(alloc: &'a mut Allocation, limit: usize) -> Self {
+        AllocationView { alloc, limit }
+    }
+
+    pub(crate) fn read<T: FromBytes>(&self, offset: usize) -> Result<T> {
+        if offset.checked_add(size_of::<T>()).ok_or(EINVAL)? > self.limit {
+            return Err(EINVAL);
+        }
+        self.alloc.read(offset)
+    }
+
+    pub(crate) fn write<T: AsBytes>(&self, offset: usize, obj: &T) -> Result {
+        if offset.checked_add(size_of::<T>()).ok_or(EINVAL)? > self.limit {
+            return Err(EINVAL);
+        }
+        self.alloc.write(offset, obj)
+    }
+
+    pub(crate) fn copy_into(
+        &self,
+        reader: &mut UserSliceReader,
+        offset: usize,
+        size: usize,
+    ) -> Result {
+        if offset.checked_add(size).ok_or(EINVAL)? > self.limit {
+            return Err(EINVAL);
+        }
+        self.alloc.copy_into(reader, offset, size)
+    }
+
+    pub(crate) fn transfer_binder_object(
+        &self,
+        offset: usize,
+        obj: &uapi::flat_binder_object,
+        strong: bool,
+        node_ref: NodeRef,
+    ) -> Result {
+        let mut newobj = FlatBinderObject::default();
+        let node = node_ref.node.clone();
+        if Arc::ptr_eq(&node_ref.node.owner, &self.alloc.process) {
+            // The receiving process is the owner of the node, so send it a binder object (instead
+            // of a handle).
+            let (ptr, cookie) = node.get_id();
+            newobj.hdr.type_ = if strong {
+                BINDER_TYPE_BINDER
+            } else {
+                BINDER_TYPE_WEAK_BINDER
+            };
+            newobj.flags = obj.flags;
+            newobj.__bindgen_anon_1.binder = ptr as _;
+            newobj.cookie = cookie as _;
+            self.write(offset, &newobj)?;
+            // Increment the user ref count on the node. It will be decremented as part of the
+            // destruction of the buffer, when we see a binder or weak-binder object.
+            node.update_refcount(true, 1, strong);
+        } else {
+            // The receiving process is different from the owner, so we need to insert a handle to
+            // the binder object.
+            let handle = self
+                .alloc
+                .process
+                .as_arc_borrow()
+                .insert_or_update_handle(node_ref, false)?;
+            newobj.hdr.type_ = if strong {
+                BINDER_TYPE_HANDLE
+            } else {
+                BINDER_TYPE_WEAK_HANDLE
+            };
+            newobj.flags = obj.flags;
+            newobj.__bindgen_anon_1.handle = handle;
+            if self.write(offset, &newobj).is_err() {
+                // Decrement ref count on the handle we just created.
+                let _ = self
+                    .alloc
+                    .process
+                    .as_arc_borrow()
+                    .update_ref(handle, false, strong);
+                return Err(EINVAL);
+            }
+        }
+
+        Ok(())
+    }
+
+    fn cleanup_object(&self, index_offset: usize) -> Result {
+        let offset = self.alloc.read(index_offset)?;
+        let header = self.read::<BinderObjectHeader>(offset)?;
+        match header.type_ {
+            BINDER_TYPE_WEAK_BINDER | BINDER_TYPE_BINDER => {
+                let obj = self.read::<FlatBinderObject>(offset)?;
+                let strong = header.type_ == BINDER_TYPE_BINDER;
+                // SAFETY: The type is `BINDER_TYPE_{WEAK_}BINDER`, so the `binder` field is
+                // populated.
+                let ptr = unsafe { obj.__bindgen_anon_1.binder };
+                let cookie = obj.cookie;
+                self.alloc.process.update_node(ptr, cookie, strong);
+                Ok(())
+            }
+            BINDER_TYPE_WEAK_HANDLE | BINDER_TYPE_HANDLE => {
+                let obj = self.read::<FlatBinderObject>(offset)?;
+                let strong = header.type_ == BINDER_TYPE_HANDLE;
+                // SAFETY: The type is `BINDER_TYPE_{WEAK_}HANDLE`, so the `handle` field is
+                // populated.
+                let handle = unsafe { obj.__bindgen_anon_1.handle };
+                self.alloc
+                    .process
+                    .as_arc_borrow()
+                    .update_ref(handle, false, strong)
+            }
+            _ => Ok(()),
+        }
+    }
+}
+
+/// A binder object as it is serialized.
+///
+/// # Invariants
+///
+/// All bytes must be initialized, and the value of `self.hdr.type_` must be one of the allowed
+/// types.
+#[repr(C)]
+pub(crate) union BinderObject {
+    hdr: uapi::binder_object_header,
+    fbo: uapi::flat_binder_object,
+    fdo: uapi::binder_fd_object,
+    bbo: uapi::binder_buffer_object,
+    fdao: uapi::binder_fd_array_object,
+}
+
+/// A view into a `BinderObject` that can be used in a match statement.
+pub(crate) enum BinderObjectRef<'a> {
+    Binder(&'a mut uapi::flat_binder_object),
+    Handle(&'a mut uapi::flat_binder_object),
+    Fd(&'a mut uapi::binder_fd_object),
+    Ptr(&'a mut uapi::binder_buffer_object),
+    Fda(&'a mut uapi::binder_fd_array_object),
+}
+
+impl BinderObject {
+    pub(crate) fn read_from(reader: &mut UserSliceReader) -> Result<BinderObject> {
+        let object = Self::read_from_inner(|slice| {
+            let read_len = usize::min(slice.len(), reader.len());
+            reader.clone_reader().read_slice(&mut slice[..read_len])?;
+            Ok(())
+        })?;
+
+        // If we used a object type smaller than the largest object size, then we've read more
+        // bytes than we needed to. However, we used `.clone_reader()` to avoid advancing the
+        // original reader. Now, we call `skip` so that the caller's reader is advanced by the
+        // right amount.
+        //
+        // The `skip` call fails if the reader doesn't have `size` bytes available. This could
+        // happen if the type header corresponds to an object type that is larger than the rest of
+        // the reader.
+        //
+        // Any extra bytes beyond the size of the object are inaccessible after this call, so
+        // reading them again from the `reader` later does not result in TOCTOU bugs.
+        reader.skip(object.size())?;
+
+        Ok(object)
+    }
+
+    /// Use the provided reader closure to construct a `BinderObject`.
+    ///
+    /// The closure should write the bytes for the object into the provided slice.
+    pub(crate) fn read_from_inner<R>(reader: R) -> Result<BinderObject>
+    where
+        R: FnOnce(&mut [u8; size_of::<BinderObject>()]) -> Result<()>,
+    {
+        let mut obj = MaybeUninit::<BinderObject>::zeroed();
+
+        // SAFETY: The lengths of `BinderObject` and `[u8; size_of::<BinderObject>()]` are equal,
+        // and the byte array has an alignment requirement of one, so the pointer cast is okay.
+        // Additionally, `obj` was initialized to zeros, so the byte array will not be
+        // uninitialized.
+        (reader)(unsafe { &mut *obj.as_mut_ptr().cast() })?;
+
+        // SAFETY: The entire object is initialized, so accessing this field is safe.
+        let type_ = unsafe { obj.assume_init_ref().hdr.type_ };
+        if Self::type_to_size(type_).is_none() {
+            // The value of `obj.hdr_type_` was invalid.
+            return Err(EINVAL);
+        }
+
+        // SAFETY: All bytes are initialized (since we zeroed them at the start) and we checked
+        // that `self.hdr.type_` is one of the allowed types, so the type invariants are satisfied.
+        unsafe { Ok(obj.assume_init()) }
+    }
+
+    pub(crate) fn as_ref(&mut self) -> BinderObjectRef<'_> {
+        use BinderObjectRef::*;
+        // SAFETY: The constructor ensures that all bytes of `self` are initialized, and all
+        // variants of this union accept all initialized bit patterns.
+        unsafe {
+            match self.hdr.type_ {
+                BINDER_TYPE_WEAK_BINDER | BINDER_TYPE_BINDER => Binder(&mut self.fbo),
+                BINDER_TYPE_WEAK_HANDLE | BINDER_TYPE_HANDLE => Handle(&mut self.fbo),
+                BINDER_TYPE_FD => Fd(&mut self.fdo),
+                BINDER_TYPE_PTR => Ptr(&mut self.bbo),
+                BINDER_TYPE_FDA => Fda(&mut self.fdao),
+                // SAFETY: By the type invariant, the value of `self.hdr.type_` cannot have any
+                // other value than the ones checked above.
+                _ => core::hint::unreachable_unchecked(),
+            }
+        }
+    }
+
+    pub(crate) fn size(&self) -> usize {
+        // SAFETY: The entire object is initialized, so accessing this field is safe.
+        let type_ = unsafe { self.hdr.type_ };
+
+        // SAFETY: The type invariants guarantee that the type field is correct.
+        unsafe { Self::type_to_size(type_).unwrap_unchecked() }
+    }
+
+    fn type_to_size(type_: u32) -> Option<usize> {
+        match type_ {
+            BINDER_TYPE_WEAK_BINDER => Some(size_of::<uapi::flat_binder_object>()),
+            BINDER_TYPE_BINDER => Some(size_of::<uapi::flat_binder_object>()),
+            BINDER_TYPE_WEAK_HANDLE => Some(size_of::<uapi::flat_binder_object>()),
+            BINDER_TYPE_HANDLE => Some(size_of::<uapi::flat_binder_object>()),
+            BINDER_TYPE_FD => Some(size_of::<uapi::binder_fd_object>()),
+            BINDER_TYPE_PTR => Some(size_of::<uapi::binder_buffer_object>()),
+            BINDER_TYPE_FDA => Some(size_of::<uapi::binder_fd_array_object>()),
+            _ => None,
+        }
+    }
+}
+
+#[derive(Default)]
+struct FileList {
+    files_to_translate: KVec<FileEntry>,
+    close_on_free: KVec<u32>,
+}
+
+struct FileEntry {
+    /// The file for which a descriptor will be created in the recipient process.
+    file: ARef<File>,
+    /// The offset in the buffer where the file descriptor is stored.
+    buffer_offset: usize,
+    /// Whether this fd should be closed when the allocation is freed.
+    close_on_free: bool,
+}
+
+pub(crate) struct TranslatedFds {
+    reservations: KVec<Reservation>,
+    /// If commit is called, then these fds should be closed. (If commit is not called, then they
+    /// shouldn't be closed.)
+    close_on_free: FdsCloseOnFree,
+}
+
+struct Reservation {
+    res: FileDescriptorReservation,
+    file: ARef<File>,
+}
+
+impl TranslatedFds {
+    pub(crate) fn new() -> Self {
+        Self {
+            reservations: KVec::new(),
+            close_on_free: FdsCloseOnFree(KVec::new()),
+        }
+    }
+
+    pub(crate) fn commit(self) -> FdsCloseOnFree {
+        for entry in self.reservations {
+            entry.res.fd_install(entry.file);
+        }
+
+        self.close_on_free
+    }
+}
+
+pub(crate) struct FdsCloseOnFree(KVec<u32>);
diff --git a/drivers/android/binder/context.rs b/drivers/android/binder/context.rs
new file mode 100644
index 000000000000..3d135ec03ca7
--- /dev/null
+++ b/drivers/android/binder/context.rs
@@ -0,0 +1,180 @@
+// SPDX-License-Identifier: GPL-2.0
+
+// Copyright (C) 2025 Google LLC.
+
+use kernel::{
+    error::Error,
+    list::{List, ListArc, ListLinks},
+    prelude::*,
+    security,
+    str::{CStr, CString},
+    sync::{Arc, Mutex},
+    task::Kuid,
+};
+
+use crate::{error::BinderError, node::NodeRef, process::Process};
+
+kernel::sync::global_lock! {
+    // SAFETY: We call `init` in the module initializer, so it's initialized before first use.
+    pub(crate) unsafe(uninit) static CONTEXTS: Mutex<ContextList> = ContextList {
+        list: List::new(),
+    };
+}
+
+pub(crate) struct ContextList {
+    list: List<Context>,
+}
+
+pub(crate) fn get_all_contexts() -> Result<KVec<Arc<Context>>> {
+    let lock = CONTEXTS.lock();
+
+    let count = lock.list.iter().count();
+
+    let mut ctxs = KVec::with_capacity(count, GFP_KERNEL)?;
+    for ctx in &lock.list {
+        ctxs.push(Arc::from(ctx), GFP_KERNEL)?;
+    }
+    Ok(ctxs)
+}
+
+/// This struct keeps track of the processes using this context, and which process is the context
+/// manager.
+struct Manager {
+    node: Option<NodeRef>,
+    uid: Option<Kuid>,
+    all_procs: List<Process>,
+}
+
+/// There is one context per binder file (/dev/binder, /dev/hwbinder, etc)
+#[pin_data]
+pub(crate) struct Context {
+    #[pin]
+    manager: Mutex<Manager>,
+    pub(crate) name: CString,
+    #[pin]
+    links: ListLinks,
+}
+
+kernel::list::impl_list_arc_safe! {
+    impl ListArcSafe<0> for Context { untracked; }
+}
+kernel::list::impl_list_item! {
+    impl ListItem<0> for Context {
+        using ListLinks { self.links };
+    }
+}
+
+impl Context {
+    pub(crate) fn new(name: &CStr) -> Result<Arc<Self>> {
+        let name = CString::try_from(name)?;
+        let list_ctx = ListArc::pin_init::<Error>(
+            try_pin_init!(Context {
+                name,
+                links <- ListLinks::new(),
+                manager <- kernel::new_mutex!(Manager {
+                    all_procs: List::new(),
+                    node: None,
+                    uid: None,
+                }, "Context::manager"),
+            }),
+            GFP_KERNEL,
+        )?;
+
+        let ctx = list_ctx.clone_arc();
+        CONTEXTS.lock().list.push_back(list_ctx);
+
+        Ok(ctx)
+    }
+
+    /// Called when the file for this context is unlinked.
+    ///
+    /// No-op if called twice.
+    pub(crate) fn deregister(&self) {
+        // SAFETY: We never add the context to any other linked list than this one, so it is either
+        // in this list, or not in any list.
+        unsafe { CONTEXTS.lock().list.remove(self) };
+    }
+
+    pub(crate) fn register_process(self: &Arc<Self>, proc: ListArc<Process>) {
+        if !Arc::ptr_eq(self, &proc.ctx) {
+            pr_err!("Context::register_process called on the wrong context.");
+            return;
+        }
+        self.manager.lock().all_procs.push_back(proc);
+    }
+
+    pub(crate) fn deregister_process(self: &Arc<Self>, proc: &Process) {
+        if !Arc::ptr_eq(self, &proc.ctx) {
+            pr_err!("Context::deregister_process called on the wrong context.");
+            return;
+        }
+        // SAFETY: We just checked that this is the right list.
+        unsafe { self.manager.lock().all_procs.remove(proc) };
+    }
+
+    pub(crate) fn set_manager_node(&self, node_ref: NodeRef) -> Result {
+        let mut manager = self.manager.lock();
+        if manager.node.is_some() {
+            pr_warn!("BINDER_SET_CONTEXT_MGR already set");
+            return Err(EBUSY);
+        }
+        security::binder_set_context_mgr(&node_ref.node.owner.cred)?;
+
+        // If the context manager has been set before, ensure that we use the same euid.
+        let caller_uid = Kuid::current_euid();
+        if let Some(ref uid) = manager.uid {
+            if *uid != caller_uid {
+                return Err(EPERM);
+            }
+        }
+
+        manager.node = Some(node_ref);
+        manager.uid = Some(caller_uid);
+        Ok(())
+    }
+
+    pub(crate) fn unset_manager_node(&self) {
+        let node_ref = self.manager.lock().node.take();
+        drop(node_ref);
+    }
+
+    pub(crate) fn get_manager_node(&self, strong: bool) -> Result<NodeRef, BinderError> {
+        self.manager
+            .lock()
+            .node
+            .as_ref()
+            .ok_or_else(BinderError::new_dead)?
+            .clone(strong)
+            .map_err(BinderError::from)
+    }
+
+    pub(crate) fn for_each_proc<F>(&self, mut func: F)
+    where
+        F: FnMut(&Process),
+    {
+        let lock = self.manager.lock();
+        for proc in &lock.all_procs {
+            func(&proc);
+        }
+    }
+
+    pub(crate) fn get_all_procs(&self) -> Result<KVec<Arc<Process>>> {
+        let lock = self.manager.lock();
+        let count = lock.all_procs.iter().count();
+
+        let mut procs = KVec::with_capacity(count, GFP_KERNEL)?;
+        for proc in &lock.all_procs {
+            procs.push(Arc::from(proc), GFP_KERNEL)?;
+        }
+        Ok(procs)
+    }
+
+    pub(crate) fn get_procs_with_pid(&self, pid: i32) -> Result<KVec<Arc<Process>>> {
+        let orig = self.get_all_procs()?;
+        let mut backing = KVec::with_capacity(orig.len(), GFP_KERNEL)?;
+        for proc in orig.into_iter().filter(|proc| proc.task.pid() == pid) {
+            backing.push(proc, GFP_KERNEL)?;
+        }
+        Ok(backing)
+    }
+}
diff --git a/drivers/android/binder/deferred_close.rs b/drivers/android/binder/deferred_close.rs
new file mode 100644
index 000000000000..ac895c04d0cb
--- /dev/null
+++ b/drivers/android/binder/deferred_close.rs
@@ -0,0 +1,204 @@
+// SPDX-License-Identifier: GPL-2.0
+
+// Copyright (C) 2025 Google LLC.
+
+//! Logic for closing files in a deferred manner.
+//!
+//! This file could make sense to have in `kernel::fs`, but it was rejected for being too
+//! Binder-specific.
+
+use core::mem::MaybeUninit;
+use kernel::{
+    alloc::{AllocError, Flags},
+    bindings,
+    prelude::*,
+};
+
+/// Helper used for closing file descriptors in a way that is safe even if the file is currently
+/// held using `fdget`.
+///
+/// Additional motivation can be found in commit 80cd795630d6 ("binder: fix use-after-free due to
+/// ksys_close() during fdget()") and in the comments on `binder_do_fd_close`.
+pub(crate) struct DeferredFdCloser {
+    inner: KBox<DeferredFdCloserInner>,
+}
+
+/// SAFETY: This just holds an allocation with no real content, so there's no safety issue with
+/// moving it across threads.
+unsafe impl Send for DeferredFdCloser {}
+/// SAFETY: This just holds an allocation with no real content, so there's no safety issue with
+/// moving it across threads.
+unsafe impl Sync for DeferredFdCloser {}
+
+/// # Invariants
+///
+/// If the `file` pointer is non-null, then it points at a `struct file` and owns a refcount to
+/// that file.
+#[repr(C)]
+struct DeferredFdCloserInner {
+    twork: MaybeUninit<bindings::callback_head>,
+    file: *mut bindings::file,
+}
+
+impl DeferredFdCloser {
+    /// Create a new [`DeferredFdCloser`].
+    pub(crate) fn new(flags: Flags) -> Result<Self, AllocError> {
+        Ok(Self {
+            // INVARIANT: The `file` pointer is null, so the type invariant does not apply.
+            inner: KBox::new(
+                DeferredFdCloserInner {
+                    twork: MaybeUninit::uninit(),
+                    file: core::ptr::null_mut(),
+                },
+                flags,
+            )?,
+        })
+    }
+
+    /// Schedule a task work that closes the file descriptor when this task returns to userspace.
+    ///
+    /// Fails if this is called from a context where we cannot run work when returning to
+    /// userspace. (E.g., from a kthread.)
+    pub(crate) fn close_fd(self, fd: u32) -> Result<(), DeferredFdCloseError> {
+        use bindings::task_work_notify_mode_TWA_RESUME as TWA_RESUME;
+
+        // In this method, we schedule the task work before closing the file. This is because
+        // scheduling a task work is fallible, and we need to know whether it will fail before we
+        // attempt to close the file.
+
+        // Task works are not available on kthreads.
+        let current = kernel::current!();
+
+        // Check if this is a kthread.
+        // SAFETY: Reading `flags` from a task is always okay.
+        if unsafe { ((*current.as_ptr()).flags & bindings::PF_KTHREAD) != 0 } {
+            return Err(DeferredFdCloseError::TaskWorkUnavailable);
+        }
+
+        // Transfer ownership of the box's allocation to a raw pointer. This disables the
+        // destructor, so we must manually convert it back to a KBox to drop it.
+        //
+        // Until we convert it back to a `KBox`, there are no aliasing requirements on this
+        // pointer.
+        let inner = KBox::into_raw(self.inner);
+
+        // The `callback_head` field is first in the struct, so this cast correctly gives us a
+        // pointer to the field.
+        let callback_head = inner.cast::<bindings::callback_head>();
+        // SAFETY: This pointer offset operation does not go out-of-bounds.
+        let file_field = unsafe { core::ptr::addr_of_mut!((*inner).file) };
+
+        let current = current.as_ptr();
+
+        // SAFETY: This function currently has exclusive access to the `DeferredFdCloserInner`, so
+        // it is okay for us to perform unsynchronized writes to its `callback_head` field.
+        unsafe { bindings::init_task_work(callback_head, Some(Self::do_close_fd)) };
+
+        // SAFETY: This inserts the `DeferredFdCloserInner` into the task workqueue for the current
+        // task. If this operation is successful, then this transfers exclusive ownership of the
+        // `callback_head` field to the C side until it calls `do_close_fd`, and we don't touch or
+        // invalidate the field during that time.
+        //
+        // When the C side calls `do_close_fd`, the safety requirements of that method are
+        // satisfied because when a task work is executed, the callback is given ownership of the
+        // pointer.
+        //
+        // The file pointer is currently null. If it is changed to be non-null before `do_close_fd`
+        // is called, then that change happens due to the write at the end of this function, and
+        // that write has a safety comment that explains why the refcount can be dropped when
+        // `do_close_fd` runs.
+        let res = unsafe { bindings::task_work_add(current, callback_head, TWA_RESUME) };
+
+        if res != 0 {
+            // SAFETY: Scheduling the task work failed, so we still have ownership of the box, so
+            // we may destroy it.
+            unsafe { drop(KBox::from_raw(inner)) };
+
+            return Err(DeferredFdCloseError::TaskWorkUnavailable);
+        }
+
+        // This removes the fd from the fd table in `current`. The file is not fully closed until
+        // `filp_close` is called. We are given ownership of one refcount to the file.
+        //
+        // SAFETY: This is safe no matter what `fd` is. If the `fd` is valid (that is, if the
+        // pointer is non-null), then we call `filp_close` on the returned pointer as required by
+        // `file_close_fd`.
+        let file = unsafe { bindings::file_close_fd(fd) };
+        if file.is_null() {
+            // We don't clean up the task work since that might be expensive if the task work queue
+            // is long. Just let it execute and let it clean up for itself.
+            return Err(DeferredFdCloseError::BadFd);
+        }
+
+        // Acquire a second refcount to the file.
+        //
+        // SAFETY: The `file` pointer points at a file with a non-zero refcount.
+        unsafe { bindings::get_file(file) };
+
+        // This method closes the fd, consuming one of our two refcounts. There could be active
+        // light refcounts created from that fd, so we must ensure that the file has a positive
+        // refcount for the duration of those active light refcounts. We do that by holding on to
+        // the second refcount until the current task returns to userspace.
+        //
+        // SAFETY: The `file` pointer is valid. Passing `current->files` as the file table to close
+        // it in is correct, since we just got the `fd` from `file_close_fd` which also uses
+        // `current->files`.
+        //
+        // Note: fl_owner_t is currently a void pointer.
+        unsafe { bindings::filp_close(file, (*current).files as bindings::fl_owner_t) };
+
+        // We update the file pointer that the task work is supposed to fput. This transfers
+        // ownership of our last refcount.
+        //
+        // INVARIANT: This changes the `file` field of a `DeferredFdCloserInner` from null to
+        // non-null. This doesn't break the type invariant for `DeferredFdCloserInner` because we
+        // still own a refcount to the file, so we can pass ownership of that refcount to the
+        // `DeferredFdCloserInner`.
+        //
+        // When `do_close_fd` runs, it must be safe for it to `fput` the refcount. However, this is
+        // the case because all light refcounts that are associated with the fd we closed
+        // previously must be dropped when `do_close_fd`, since light refcounts must be dropped
+        // before returning to userspace.
+        //
+        // SAFETY: Task works are executed on the current thread right before we return to
+        // userspace, so this write is guaranteed to happen before `do_close_fd` is called, which
+        // means that a race is not possible here.
+        unsafe { *file_field = file };
+
+        Ok(())
+    }
+
+    /// # Safety
+    ///
+    /// The provided pointer must point at the `twork` field of a `DeferredFdCloserInner` stored in
+    /// a `KBox`, and the caller must pass exclusive ownership of that `KBox`. Furthermore, if the
+    /// file pointer is non-null, then it must be okay to release the refcount by calling `fput`.
+    unsafe extern "C" fn do_close_fd(inner: *mut bindings::callback_head) {
+        // SAFETY: The caller just passed us ownership of this box.
+        let inner = unsafe { KBox::from_raw(inner.cast::<DeferredFdCloserInner>()) };
+        if !inner.file.is_null() {
+            // SAFETY: By the type invariants, we own a refcount to this file, and the caller
+            // guarantees that dropping the refcount now is okay.
+            unsafe { bindings::fput(inner.file) };
+        }
+        // The allocation is freed when `inner` goes out of scope.
+    }
+}
+
+/// Represents a failure to close an fd in a deferred manner.
+#[derive(Copy, Clone, Debug, Eq, PartialEq)]
+pub(crate) enum DeferredFdCloseError {
+    /// Closing the fd failed because we were unable to schedule a task work.
+    TaskWorkUnavailable,
+    /// Closing the fd failed because the fd does not exist.
+    BadFd,
+}
+
+impl From<DeferredFdCloseError> for Error {
+    fn from(err: DeferredFdCloseError) -> Error {
+        match err {
+            DeferredFdCloseError::TaskWorkUnavailable => ESRCH,
+            DeferredFdCloseError::BadFd => EBADF,
+        }
+    }
+}
diff --git a/drivers/android/binder/defs.rs b/drivers/android/binder/defs.rs
new file mode 100644
index 000000000000..33f51b4139c7
--- /dev/null
+++ b/drivers/android/binder/defs.rs
@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: GPL-2.0
+
+// Copyright (C) 2025 Google LLC.
+
+use core::mem::MaybeUninit;
+use core::ops::{Deref, DerefMut};
+use kernel::{
+    transmute::{AsBytes, FromBytes},
+    uapi::{self, *},
+};
+
+macro_rules! pub_no_prefix {
+    ($prefix:ident, $($newname:ident),+ $(,)?) => {
+        $(pub(crate) const $newname: u32 = kernel::macros::concat_idents!($prefix, $newname);)+
+    };
+}
+
+pub_no_prefix!(
+    binder_driver_return_protocol_,
+    BR_TRANSACTION,
+    BR_TRANSACTION_SEC_CTX,
+    BR_REPLY,
+    BR_DEAD_REPLY,
+    BR_FAILED_REPLY,
+    BR_FROZEN_REPLY,
+    BR_NOOP,
+    BR_SPAWN_LOOPER,
+    BR_TRANSACTION_COMPLETE,
+    BR_TRANSACTION_PENDING_FROZEN,
+    BR_ONEWAY_SPAM_SUSPECT,
+    BR_OK,
+    BR_ERROR,
+    BR_INCREFS,
+    BR_ACQUIRE,
+    BR_RELEASE,
+    BR_DECREFS,
+    BR_DEAD_BINDER,
+    BR_CLEAR_DEATH_NOTIFICATION_DONE,
+    BR_FROZEN_BINDER,
+    BR_CLEAR_FREEZE_NOTIFICATION_DONE,
+);
+
+pub_no_prefix!(
+    binder_driver_command_protocol_,
+    BC_TRANSACTION,
+    BC_TRANSACTION_SG,
+    BC_REPLY,
+    BC_REPLY_SG,
+    BC_FREE_BUFFER,
+    BC_ENTER_LOOPER,
+    BC_EXIT_LOOPER,
+    BC_REGISTER_LOOPER,
+    BC_INCREFS,
+    BC_ACQUIRE,
+    BC_RELEASE,
+    BC_DECREFS,
+    BC_INCREFS_DONE,
+    BC_ACQUIRE_DONE,
+    BC_REQUEST_DEATH_NOTIFICATION,
+    BC_CLEAR_DEATH_NOTIFICATION,
+    BC_DEAD_BINDER_DONE,
+    BC_REQUEST_FREEZE_NOTIFICATION,
+    BC_CLEAR_FREEZE_NOTIFICATION,
+    BC_FREEZE_NOTIFICATION_DONE,
+);
+
+pub_no_prefix!(
+    flat_binder_object_flags_,
+    FLAT_BINDER_FLAG_ACCEPTS_FDS,
+    FLAT_BINDER_FLAG_TXN_SECURITY_CTX
+);
+
+pub_no_prefix!(
+    transaction_flags_,
+    TF_ONE_WAY,
+    TF_ACCEPT_FDS,
+    TF_CLEAR_BUF,
+    TF_UPDATE_TXN
+);
+
+pub(crate) use uapi::{
+    BINDER_TYPE_BINDER, BINDER_TYPE_FD, BINDER_TYPE_FDA, BINDER_TYPE_HANDLE, BINDER_TYPE_PTR,
+    BINDER_TYPE_WEAK_BINDER, BINDER_TYPE_WEAK_HANDLE,
+};
+
+macro_rules! decl_wrapper {
+    ($newname:ident, $wrapped:ty) => {
+        // Define a wrapper around the C type. Use `MaybeUninit` to enforce that the value of
+        // padding bytes must be preserved.
+        #[derive(Copy, Clone)]
+        #[repr(transparent)]
+        pub(crate) struct $newname(MaybeUninit<$wrapped>);
+
+        // SAFETY: This macro is only used with types where this is ok.
+        unsafe impl FromBytes for $newname {}
+        // SAFETY: This macro is only used with types where this is ok.
+        unsafe impl AsBytes for $newname {}
+
+        impl Deref for $newname {
+            type Target = $wrapped;
+            fn deref(&self) -> &Self::Target {
+                // SAFETY: We use `MaybeUninit` only to preserve padding. The value must still
+                // always be valid.
+                unsafe { self.0.assume_init_ref() }
+            }
+        }
+
+        impl DerefMut for $newname {
+            fn deref_mut(&mut self) -> &mut Self::Target {
+                // SAFETY: We use `MaybeUninit` only to preserve padding. The value must still
+                // always be valid.
+                unsafe { self.0.assume_init_mut() }
+            }
+        }
+
+        impl Default for $newname {
+            fn default() -> Self {
+                // Create a new value of this type where all bytes (including padding) are zeroed.
+                Self(MaybeUninit::zeroed())
+            }
+        }
+    };
+}
+
+decl_wrapper!(BinderNodeDebugInfo, uapi::binder_node_debug_info);
+decl_wrapper!(BinderNodeInfoForRef, uapi::binder_node_info_for_ref);
+decl_wrapper!(FlatBinderObject, uapi::flat_binder_object);
+decl_wrapper!(BinderFdObject, uapi::binder_fd_object);
+decl_wrapper!(BinderFdArrayObject, uapi::binder_fd_array_object);
+decl_wrapper!(BinderObjectHeader, uapi::binder_object_header);
+decl_wrapper!(BinderBufferObject, uapi::binder_buffer_object);
+decl_wrapper!(BinderTransactionData, uapi::binder_transaction_data);
+decl_wrapper!(
+    BinderTransactionDataSecctx,
+    uapi::binder_transaction_data_secctx
+);
+decl_wrapper!(BinderTransactionDataSg, uapi::binder_transaction_data_sg);
+decl_wrapper!(BinderWriteRead, uapi::binder_write_read);
+decl_wrapper!(BinderVersion, uapi::binder_version);
+decl_wrapper!(BinderFrozenStatusInfo, uapi::binder_frozen_status_info);
+decl_wrapper!(BinderFreezeInfo, uapi::binder_freeze_info);
+decl_wrapper!(BinderFrozenStateInfo, uapi::binder_frozen_state_info);
+decl_wrapper!(BinderHandleCookie, uapi::binder_handle_cookie);
+decl_wrapper!(ExtendedError, uapi::binder_extended_error);
+
+impl BinderVersion {
+    pub(crate) fn current() -> Self {
+        Self(MaybeUninit::new(uapi::binder_version {
+            protocol_version: BINDER_CURRENT_PROTOCOL_VERSION as _,
+        }))
+    }
+}
+
+impl BinderTransactionData {
+    pub(crate) fn with_buffers_size(self, buffers_size: u64) -> BinderTransactionDataSg {
+        BinderTransactionDataSg(MaybeUninit::new(uapi::binder_transaction_data_sg {
+            transaction_data: *self,
+            buffers_size,
+        }))
+    }
+}
+
+impl BinderTransactionDataSecctx {
+    /// View the inner data as wrapped in `BinderTransactionData`.
+    pub(crate) fn tr_data(&mut self) -> &mut BinderTransactionData {
+        // SAFETY: Transparent wrapper is safe to transmute.
+        unsafe {
+            &mut *(&mut self.transaction_data as *mut uapi::binder_transaction_data
+                as *mut BinderTransactionData)
+        }
+    }
+}
+
+impl ExtendedError {
+    pub(crate) fn new(id: u32, command: u32, param: i32) -> Self {
+        Self(MaybeUninit::new(uapi::binder_extended_error {
+            id,
+            command,
+            param,
+        }))
+    }
+}
diff --git a/drivers/android/binder/error.rs b/drivers/android/binder/error.rs
new file mode 100644
index 000000000000..b24497cfa292
--- /dev/null
+++ b/drivers/android/binder/error.rs
@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0
+
+// Copyright (C) 2025 Google LLC.
+
+use kernel::fmt;
+use kernel::prelude::*;
+
+use crate::defs::*;
+
+pub(crate) type BinderResult<T = ()> = core::result::Result<T, BinderError>;
+
+/// An error that will be returned to userspace via the `BINDER_WRITE_READ` ioctl rather than via
+/// errno.
+pub(crate) struct BinderError {
+    pub(crate) reply: u32,
+    source: Option<Error>,
+}
+
+impl BinderError {
+    pub(crate) fn new_dead() -> Self {
+        Self {
+            reply: BR_DEAD_REPLY,
+            source: None,
+        }
+    }
+
+    pub(crate) fn new_frozen() -> Self {
+        Self {
+            reply: BR_FROZEN_REPLY,
+            source: None,
+        }
+    }
+
+    pub(crate) fn new_frozen_oneway() -> Self {
+        Self {
+            reply: BR_TRANSACTION_PENDING_FROZEN,
+            source: None,
+        }
+    }
+
+    pub(crate) fn is_dead(&self) -> bool {
+        self.reply == BR_DEAD_REPLY
+    }
+
+    pub(crate) fn as_errno(&self) -> kernel::ffi::c_int {
+        self.source.unwrap_or(EINVAL).to_errno()
+    }
+
+    pub(crate) fn should_pr_warn(&self) -> bool {
+        self.source.is_some()
+    }
+}
+
+/// Convert an errno into a `BinderError` and store the errno used to construct it. The errno
+/// should be stored as the thread's extended error when given to userspace.
+impl From<Error> for BinderError {
+    fn from(source: Error) -> Self {
+        Self {
+            reply: BR_FAILED_REPLY,
+            source: Some(source),
+        }
+    }
+}
+
+impl From<kernel::fs::file::BadFdError> for BinderError {
+    fn from(source: kernel::fs::file::BadFdError) -> Self {
+        BinderError::from(Error::from(source))
+    }
+}
+
+impl From<kernel::alloc::AllocError> for BinderError {
+    fn from(_: kernel::alloc::AllocError) -> Self {
+        Self {
+            reply: BR_FAILED_REPLY,
+            source: Some(ENOMEM),
+        }
+    }
+}
+
+impl fmt::Debug for BinderError {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        match self.reply {
+            BR_FAILED_REPLY => match self.source.as_ref() {
+                Some(source) => f
+                    .debug_struct("BR_FAILED_REPLY")
+                    .field("source", source)
+                    .finish(),
+                None => f.pad("BR_FAILED_REPLY"),
+            },
+            BR_DEAD_REPLY => f.pad("BR_DEAD_REPLY"),
+            BR_FROZEN_REPLY => f.pad("BR_FROZEN_REPLY"),
+            BR_TRANSACTION_PENDING_FROZEN => f.pad("BR_TRANSACTION_PENDING_FROZEN"),
+            BR_TRANSACTION_COMPLETE => f.pad("BR_TRANSACTION_COMPLETE"),
+            _ => f
+                .debug_struct("BinderError")
+                .field("reply", &self.reply)
+                .finish(),
+        }
+    }
+}
diff --git a/drivers/android/binder/freeze.rs b/drivers/android/binder/freeze.rs
new file mode 100644
index 000000000000..53b60035639a
--- /dev/null
+++ b/drivers/android/binder/freeze.rs
@@ -0,0 +1,398 @@
+// SPDX-License-Identifier: GPL-2.0
+
+// Copyright (C) 2025 Google LLC.
+
+use kernel::{
+    alloc::AllocError,
+    list::ListArc,
+    prelude::*,
+    rbtree::{self, RBTreeNodeReservation},
+    seq_file::SeqFile,
+    seq_print,
+    sync::{Arc, UniqueArc},
+    uaccess::UserSliceReader,
+};
+
+use crate::{
+    defs::*, node::Node, process::Process, thread::Thread, BinderReturnWriter, DArc, DLArc,
+    DTRWrap, DeliverToRead,
+};
+
+#[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
+pub(crate) struct FreezeCookie(u64);
+
+/// Represents a listener for changes to the frozen state of a process.
+pub(crate) struct FreezeListener {
+    /// The node we are listening for.
+    pub(crate) node: DArc<Node>,
+    /// The cookie of this freeze listener.
+    cookie: FreezeCookie,
+    /// What value of `is_frozen` did we most recently tell userspace about?
+    last_is_frozen: Option<bool>,
+    /// We sent a `BR_FROZEN_BINDER` and we are waiting for `BC_FREEZE_NOTIFICATION_DONE` before
+    /// sending any other commands.
+    is_pending: bool,
+    /// Userspace sent `BC_CLEAR_FREEZE_NOTIFICATION` and we need to reply with
+    /// `BR_CLEAR_FREEZE_NOTIFICATION_DONE` as soon as possible. If `is_pending` is set, then we
+    /// must wait for it to be unset before we can reply.
+    is_clearing: bool,
+    /// Number of cleared duplicates that can't be deleted until userspace sends
+    /// `BC_FREEZE_NOTIFICATION_DONE`.
+    num_pending_duplicates: u64,
+    /// Number of cleared duplicates that can be deleted.
+    num_cleared_duplicates: u64,
+}
+
+impl FreezeListener {
+    /// Is it okay to create a new listener with the same cookie as this one for the provided node?
+    ///
+    /// Under some scenarios, userspace may delete a freeze listener and immediately recreate it
+    /// with the same cookie. This results in duplicate listeners. To avoid issues with ambiguity,
+    /// we allow this only if the new listener is for the same node, and we also require that the
+    /// old listener has already been cleared.
+    fn allow_duplicate(&self, node: &DArc<Node>) -> bool {
+        Arc::ptr_eq(&self.node, node) && self.is_clearing
+    }
+}
+
+type UninitFM = UniqueArc<core::mem::MaybeUninit<DTRWrap<FreezeMessage>>>;
+
+/// Represents a notification that the freeze state has changed.
+pub(crate) struct FreezeMessage {
+    cookie: FreezeCookie,
+}
+
+kernel::list::impl_list_arc_safe! {
+    impl ListArcSafe<0> for FreezeMessage {
+        untracked;
+    }
+}
+
+impl FreezeMessage {
+    fn new(flags: kernel::alloc::Flags) -> Result<UninitFM, AllocError> {
+        UniqueArc::new_uninit(flags)
+    }
+
+    fn init(ua: UninitFM, cookie: FreezeCookie) -> DLArc<FreezeMessage> {
+        match ua.pin_init_with(DTRWrap::new(FreezeMessage { cookie })) {
+            Ok(msg) => ListArc::from(msg),
+            Err(err) => match err {},
+        }
+    }
+}
+
+impl DeliverToRead for FreezeMessage {
+    fn do_work(
+        self: DArc<Self>,
+        thread: &Thread,
+        writer: &mut BinderReturnWriter<'_>,
+    ) -> Result<bool> {
+        let _removed_listener;
+        let mut node_refs = thread.process.node_refs.lock();
+        let Some(mut freeze_entry) = node_refs.freeze_listeners.find_mut(&self.cookie) else {
+            return Ok(true);
+        };
+        let freeze = freeze_entry.get_mut();
+
+        if freeze.num_cleared_duplicates > 0 {
+            freeze.num_cleared_duplicates -= 1;
+            drop(node_refs);
+            writer.write_code(BR_CLEAR_FREEZE_NOTIFICATION_DONE)?;
+            writer.write_payload(&self.cookie.0)?;
+            return Ok(true);
+        }
+
+        if freeze.is_pending {
+            return Ok(true);
+        }
+        if freeze.is_clearing {
+            kernel::warn_on!(freeze.num_cleared_duplicates != 0);
+            if freeze.num_pending_duplicates > 0 {
+                // The primary freeze listener was deleted, so convert a pending duplicate back
+                // into the primary one.
+                freeze.num_pending_duplicates -= 1;
+                freeze.is_pending = true;
+                freeze.is_clearing = true;
+            } else {
+                _removed_listener = freeze_entry.remove_node();
+            }
+            drop(node_refs);
+            writer.write_code(BR_CLEAR_FREEZE_NOTIFICATION_DONE)?;
+            writer.write_payload(&self.cookie.0)?;
+            Ok(true)
+        } else {
+            let is_frozen = freeze.node.owner.inner.lock().is_frozen.is_fully_frozen();
+            if freeze.last_is_frozen == Some(is_frozen) {
+                return Ok(true);
+            }
+
+            let mut state_info = BinderFrozenStateInfo::default();
+            state_info.is_frozen = is_frozen as u32;
+            state_info.cookie = freeze.cookie.0;
+            freeze.is_pending = true;
+            freeze.last_is_frozen = Some(is_frozen);
+            drop(node_refs);
+
+            writer.write_code(BR_FROZEN_BINDER)?;
+            writer.write_payload(&state_info)?;
+            // BR_FROZEN_BINDER notifications can cause transactions
+            Ok(false)
+        }
+    }
+
+    fn cancel(self: DArc<Self>) {}
+
+    fn should_sync_wakeup(&self) -> bool {
+        false
+    }
+
+    #[inline(never)]
+    fn debug_print(&self, m: &SeqFile, prefix: &str, _tprefix: &str) -> Result<()> {
+        seq_print!(m, "{}has frozen binder\n", prefix);
+        Ok(())
+    }
+}
+
+impl FreezeListener {
+    pub(crate) fn on_process_exit(&self, proc: &Arc<Process>) {
+        if !self.is_clearing {
+            self.node.remove_freeze_listener(proc);
+        }
+    }
+}
+
+impl Process {
+    pub(crate) fn request_freeze_notif(
+        self: &Arc<Self>,
+        reader: &mut UserSliceReader,
+    ) -> Result<()> {
+        let hc = reader.read::<BinderHandleCookie>()?;
+        let handle = hc.handle;
+        let cookie = FreezeCookie(hc.cookie);
+
+        let msg = FreezeMessage::new(GFP_KERNEL)?;
+        let alloc = RBTreeNodeReservation::new(GFP_KERNEL)?;
+
+        let mut node_refs_guard = self.node_refs.lock();
+        let node_refs = &mut *node_refs_guard;
+        let Some(info) = node_refs.by_handle.get_mut(&handle) else {
+            pr_warn!("BC_REQUEST_FREEZE_NOTIFICATION invalid ref {}\n", handle);
+            return Err(EINVAL);
+        };
+        if info.freeze().is_some() {
+            pr_warn!("BC_REQUEST_FREEZE_NOTIFICATION already set\n");
+            return Err(EINVAL);
+        }
+        let node_ref = info.node_ref();
+        let freeze_entry = node_refs.freeze_listeners.entry(cookie);
+
+        if let rbtree::Entry::Occupied(ref dupe) = freeze_entry {
+            if !dupe.get().allow_duplicate(&node_ref.node) {
+                pr_warn!("BC_REQUEST_FREEZE_NOTIFICATION duplicate cookie\n");
+                return Err(EINVAL);
+            }
+        }
+
+        // All failure paths must come before this call, and all modifications must come after this
+        // call.
+        node_ref.node.add_freeze_listener(self, GFP_KERNEL)?;
+
+        match freeze_entry {
+            rbtree::Entry::Vacant(entry) => {
+                entry.insert(
+                    FreezeListener {
+                        cookie,
+                        node: node_ref.node.clone(),
+                        last_is_frozen: None,
+                        is_pending: false,
+                        is_clearing: false,
+                        num_pending_duplicates: 0,
+                        num_cleared_duplicates: 0,
+                    },
+                    alloc,
+                );
+            }
+            rbtree::Entry::Occupied(mut dupe) => {
+                let dupe = dupe.get_mut();
+                if dupe.is_pending {
+                    dupe.num_pending_duplicates += 1;
+                } else {
+                    dupe.num_cleared_duplicates += 1;
+                }
+                dupe.last_is_frozen = None;
+                dupe.is_pending = false;
+                dupe.is_clearing = false;
+            }
+        }
+
+        *info.freeze() = Some(cookie);
+        let msg = FreezeMessage::init(msg, cookie);
+        drop(node_refs_guard);
+        let _ = self.push_work(msg);
+        Ok(())
+    }
+
+    pub(crate) fn freeze_notif_done(self: &Arc<Self>, reader: &mut UserSliceReader) -> Result<()> {
+        let cookie = FreezeCookie(reader.read()?);
+        let alloc = FreezeMessage::new(GFP_KERNEL)?;
+        let mut node_refs_guard = self.node_refs.lock();
+        let node_refs = &mut *node_refs_guard;
+        let Some(freeze) = node_refs.freeze_listeners.get_mut(&cookie) else {
+            pr_warn!("BC_FREEZE_NOTIFICATION_DONE {:016x} not found\n", cookie.0);
+            return Err(EINVAL);
+        };
+        let mut clear_msg = None;
+        if freeze.num_pending_duplicates > 0 {
+            clear_msg = Some(FreezeMessage::init(alloc, cookie));
+            freeze.num_pending_duplicates -= 1;
+            freeze.num_cleared_duplicates += 1;
+        } else {
+            if !freeze.is_pending {
+                pr_warn!(
+                    "BC_FREEZE_NOTIFICATION_DONE {:016x} not pending\n",
+                    cookie.0
+                );
+                return Err(EINVAL);
+            }
+            let is_frozen = freeze.node.owner.inner.lock().is_frozen.is_fully_frozen();
+            if freeze.is_clearing || freeze.last_is_frozen != Some(is_frozen) {
+                // Immediately send another FreezeMessage.
+                clear_msg = Some(FreezeMessage::init(alloc, cookie));
+            }
+            freeze.is_pending = false;
+        }
+        drop(node_refs_guard);
+        if let Some(clear_msg) = clear_msg {
+            let _ = self.push_work(clear_msg);
+        }
+        Ok(())
+    }
+
+    pub(crate) fn clear_freeze_notif(self: &Arc<Self>, reader: &mut UserSliceReader) -> Result<()> {
+        let hc = reader.read::<BinderHandleCookie>()?;
+        let handle = hc.handle;
+        let cookie = FreezeCookie(hc.cookie);
+
+        let alloc = FreezeMessage::new(GFP_KERNEL)?;
+        let mut node_refs_guard = self.node_refs.lock();
+        let node_refs = &mut *node_refs_guard;
+        let Some(info) = node_refs.by_handle.get_mut(&handle) else {
+            pr_warn!("BC_CLEAR_FREEZE_NOTIFICATION invalid ref {}\n", handle);
+            return Err(EINVAL);
+        };
+        let Some(info_cookie) = info.freeze() else {
+            pr_warn!("BC_CLEAR_FREEZE_NOTIFICATION freeze notification not active\n");
+            return Err(EINVAL);
+        };
+        if *info_cookie != cookie {
+            pr_warn!("BC_CLEAR_FREEZE_NOTIFICATION freeze notification cookie mismatch\n");
+            return Err(EINVAL);
+        }
+        let Some(listener) = node_refs.freeze_listeners.get_mut(&cookie) else {
+            pr_warn!("BC_CLEAR_FREEZE_NOTIFICATION invalid cookie {}\n", handle);
+            return Err(EINVAL);
+        };
+        listener.is_clearing = true;
+        listener.node.remove_freeze_listener(self);
+        *info.freeze() = None;
+        let mut msg = None;
+        if !listener.is_pending {
+            msg = Some(FreezeMessage::init(alloc, cookie));
+        }
+        drop(node_refs_guard);
+
+        if let Some(msg) = msg {
+            let _ = self.push_work(msg);
+        }
+        Ok(())
+    }
+
+    fn get_freeze_cookie(&self, node: &DArc<Node>) -> Option<FreezeCookie> {
+        let node_refs = &mut *self.node_refs.lock();
+        let handle = node_refs.by_node.get(&node.global_id())?;
+        let node_ref = node_refs.by_handle.get_mut(handle)?;
+        *node_ref.freeze()
+    }
+
+    /// Creates a vector of every freeze listener on this process.
+    ///
+    /// Returns pairs of the remote process listening for notifications and the local node it is
+    /// listening on.
+    #[expect(clippy::type_complexity)]
+    fn find_freeze_recipients(&self) -> Result<KVVec<(DArc<Node>, Arc<Process>)>, AllocError> {
+        // Defined before `inner` to drop after releasing spinlock if `push_within_capacity` fails.
+        let mut node_proc_pair;
+
+        // We pre-allocate space for up to 8 recipients before we take the spinlock. However, if
+        // the allocation fails, use a vector with a capacity of zero instead of failing. After
+        // all, there might not be any freeze listeners, in which case this operation could still
+        // succeed.
+        let mut recipients =
+            KVVec::with_capacity(8, GFP_KERNEL).unwrap_or_else(|_err| KVVec::new());
+
+        let mut inner = self.lock_with_nodes();
+        let mut curr = inner.nodes.cursor_front_mut();
+        while let Some(cursor) = curr {
+            let (key, node) = cursor.current();
+            let key = *key;
+            let list = node.freeze_list(&inner.inner);
+            let len = list.len();
+
+            if recipients.spare_capacity_mut().len() < len {
+                drop(inner);
+                recipients.reserve(len, GFP_KERNEL)?;
+                inner = self.lock_with_nodes();
+                // Find the node we were looking at and try again. If the set of nodes was changed,
+                // then just proceed to the next node. This is ok because we don't guarantee the
+                // inclusion of nodes that are added or removed in parallel with this operation.
+                curr = inner.nodes.cursor_lower_bound_mut(&key);
+                continue;
+            }
+
+            for proc in list {
+                node_proc_pair = (node.clone(), proc.clone());
+                recipients
+                    .push_within_capacity(node_proc_pair)
+                    .map_err(|_| {
+                        pr_err!(
+                            "push_within_capacity failed even though we checked the capacity\n"
+                        );
+                        AllocError
+                    })?;
+            }
+
+            curr = cursor.move_next();
+        }
+        Ok(recipients)
+    }
+
+    /// Prepare allocations for sending freeze messages.
+    pub(crate) fn prepare_freeze_messages(&self) -> Result<FreezeMessages, AllocError> {
+        let recipients = self.find_freeze_recipients()?;
+        let mut batch = KVVec::with_capacity(recipients.len(), GFP_KERNEL)?;
+        for (node, proc) in recipients {
+            let Some(cookie) = proc.get_freeze_cookie(&node) else {
+                // If the freeze listener was removed in the meantime, just discard the
+                // notification.
+                continue;
+            };
+            let msg_alloc = FreezeMessage::new(GFP_KERNEL)?;
+            let msg = FreezeMessage::init(msg_alloc, cookie);
+            batch.push((proc, msg), GFP_KERNEL)?;
+        }
+
+        Ok(FreezeMessages { batch })
+    }
+}
+
+pub(crate) struct FreezeMessages {
+    batch: KVVec<(Arc<Process>, DLArc<FreezeMessage>)>,
+}
+
+impl FreezeMessages {
+    pub(crate) fn send_messages(self) {
+        for (proc, msg) in self.batch {
+            let _ = proc.push_work(msg);
+        }
+    }
+}
diff --git a/drivers/android/binder/node.rs b/drivers/android/binder/node.rs
new file mode 100644
index 000000000000..c26d113ede96
--- /dev/null
+++ b/drivers/android/binder/node.rs
@@ -0,0 +1,1131 @@
+// SPDX-License-Identifier: GPL-2.0
+
+// Copyright (C) 2025 Google LLC.
+
+use kernel::{
+    list::{AtomicTracker, List, ListArc, ListLinks, TryNewListArc},
+    prelude::*,
+    seq_file::SeqFile,
+    seq_print,
+    sync::lock::{spinlock::SpinLockBackend, Guard},
+    sync::{Arc, LockedBy, SpinLock},
+};
+
+use crate::{
+    defs::*,
+    error::BinderError,
+    process::{NodeRefInfo, Process, ProcessInner},
+    thread::Thread,
+    transaction::Transaction,
+    BinderReturnWriter, DArc, DLArc, DTRWrap, DeliverToRead,
+};
+
+use core::mem;
+
+mod wrapper;
+pub(crate) use self::wrapper::CritIncrWrapper;
+
+#[derive(Debug)]
+pub(crate) struct CouldNotDeliverCriticalIncrement;
+
+/// Keeps track of how this node is scheduled.
+///
+/// There are two ways to schedule a node to a work list. Just schedule the node itself, or
+/// allocate a wrapper that references the node and schedule the wrapper. These wrappers exists to
+/// make it possible to "move" a node from one list to another - when `do_work` is called directly
+/// on the `Node`, then it's a no-op if there's also a pending wrapper.
+///
+/// Wrappers are generally only needed for zero-to-one refcount increments, and there are two cases
+/// of this: weak increments and strong increments. We call such increments "critical" because it
+/// is critical that they are delivered to the thread doing the increment. Some examples:
+///
+/// * One thread makes a zero-to-one strong increment, and another thread makes a zero-to-one weak
+///   increment. Delivering the node to the thread doing the weak increment is wrong, since the
+///   thread doing the strong increment may have ended a long time ago when the command is actually
+///   processed by userspace.
+///
+/// * We have a weak reference and are about to drop it on one thread. But then another thread does
+///   a zero-to-one strong increment. If the strong increment gets sent to the thread that was
+///   about to drop the weak reference, then the strong increment could be processed after the
+///   other thread has already exited, which would be too late.
+///
+/// Note that trying to create a `ListArc` to the node can succeed even if `has_normal_push` is
+/// set. This is because another thread might just have popped the node from a todo list, but not
+/// yet called `do_work`. However, if `has_normal_push` is false, then creating a `ListArc` should
+/// always succeed.
+///
+/// Like the other fields in `NodeInner`, the delivery state is protected by the process lock.
+struct DeliveryState {
+    /// Is the `Node` currently scheduled?
+    has_pushed_node: bool,
+
+    /// Is a wrapper currently scheduled?
+    ///
+    /// The wrapper is used only for strong zero2one increments.
+    has_pushed_wrapper: bool,
+
+    /// Is the currently scheduled `Node` scheduled due to a weak zero2one increment?
+    ///
+    /// Weak zero2one operations are always scheduled using the `Node`.
+    has_weak_zero2one: bool,
+
+    /// Is the currently scheduled wrapper/`Node` scheduled due to a strong zero2one increment?
+    ///
+    /// If `has_pushed_wrapper` is set, then the strong zero2one increment was scheduled using the
+    /// wrapper. Otherwise, `has_pushed_node` must be set and it was scheduled using the `Node`.
+    has_strong_zero2one: bool,
+}
+
+impl DeliveryState {
+    fn should_normal_push(&self) -> bool {
+        !self.has_pushed_node && !self.has_pushed_wrapper
+    }
+
+    fn did_normal_push(&mut self) {
+        assert!(self.should_normal_push());
+        self.has_pushed_node = true;
+    }
+
+    fn should_push_weak_zero2one(&self) -> bool {
+        !self.has_weak_zero2one && !self.has_strong_zero2one
+    }
+
+    fn can_push_weak_zero2one_normally(&self) -> bool {
+        !self.has_pushed_node
+    }
+
+    fn did_push_weak_zero2one(&mut self) {
+        assert!(self.should_push_weak_zero2one());
+        assert!(self.can_push_weak_zero2one_normally());
+        self.has_pushed_node = true;
+        self.has_weak_zero2one = true;
+    }
+
+    fn should_push_strong_zero2one(&self) -> bool {
+        !self.has_strong_zero2one
+    }
+
+    fn can_push_strong_zero2one_normally(&self) -> bool {
+        !self.has_pushed_node
+    }
+
+    fn did_push_strong_zero2one(&mut self) {
+        assert!(self.should_push_strong_zero2one());
+        assert!(self.can_push_strong_zero2one_normally());
+        self.has_pushed_node = true;
+        self.has_strong_zero2one = true;
+    }
+
+    fn did_push_strong_zero2one_wrapper(&mut self) {
+        assert!(self.should_push_strong_zero2one());
+        assert!(!self.can_push_strong_zero2one_normally());
+        self.has_pushed_wrapper = true;
+        self.has_strong_zero2one = true;
+    }
+}
+
+struct CountState {
+    /// The reference count.
+    count: usize,
+    /// Whether the process that owns this node thinks that we hold a refcount on it. (Note that
+    /// even if count is greater than one, we only increment it once in the owning process.)
+    has_count: bool,
+}
+
+impl CountState {
+    fn new() -> Self {
+        Self {
+            count: 0,
+            has_count: false,
+        }
+    }
+}
+
+struct NodeInner {
+    /// Strong refcounts held on this node by `NodeRef` objects.
+    strong: CountState,
+    /// Weak refcounts held on this node by `NodeRef` objects.
+    weak: CountState,
+    delivery_state: DeliveryState,
+    /// The binder driver guarantees that oneway transactions sent to the same node are serialized,
+    /// that is, userspace will not be given the next one until it has finished processing the
+    /// previous oneway transaction. This is done to avoid the case where two oneway transactions
+    /// arrive in opposite order from the order in which they were sent. (E.g., they could be
+    /// delivered to two different threads, which could appear as-if they were sent in opposite
+    /// order.)
+    ///
+    /// To fix that, we store pending oneway transactions in a separate list in the node, and don't
+    /// deliver the next oneway transaction until userspace signals that it has finished processing
+    /// the previous oneway transaction by calling the `BC_FREE_BUFFER` ioctl.
+    oneway_todo: List<DTRWrap<Transaction>>,
+    /// Keeps track of whether this node has a pending oneway transaction.
+    ///
+    /// When this is true, incoming oneway transactions are stored in `oneway_todo`, instead of
+    /// being delivered directly to the process.
+    has_oneway_transaction: bool,
+    /// List of processes to deliver a notification to when this node is destroyed (usually due to
+    /// the process dying).
+    death_list: List<DTRWrap<NodeDeath>, 1>,
+    /// List of processes to deliver freeze notifications to.
+    freeze_list: KVVec<Arc<Process>>,
+    /// The number of active BR_INCREFS or BR_ACQUIRE operations. (should be maximum two)
+    ///
+    /// If this is non-zero, then we postpone any BR_RELEASE or BR_DECREFS notifications until the
+    /// active operations have ended. This avoids the situation an increment and decrement get
+    /// reordered from userspace's perspective.
+    active_inc_refs: u8,
+    /// List of `NodeRefInfo` objects that reference this node.
+    refs: List<NodeRefInfo, { NodeRefInfo::LIST_NODE }>,
+}
+
+#[pin_data]
+pub(crate) struct Node {
+    pub(crate) debug_id: usize,
+    ptr: u64,
+    pub(crate) cookie: u64,
+    pub(crate) flags: u32,
+    pub(crate) owner: Arc<Process>,
+    inner: LockedBy<NodeInner, ProcessInner>,
+    #[pin]
+    links_track: AtomicTracker,
+}
+
+kernel::list::impl_list_arc_safe! {
+    impl ListArcSafe<0> for Node {
+        tracked_by links_track: AtomicTracker;
+    }
+}
+
+// Make `oneway_todo` work.
+kernel::list::impl_list_item! {
+    impl ListItem<0> for DTRWrap<Transaction> {
+        using ListLinks { self.links.inner };
+    }
+}
+
+impl Node {
+    pub(crate) fn new(
+        ptr: u64,
+        cookie: u64,
+        flags: u32,
+        owner: Arc<Process>,
+    ) -> impl PinInit<Self> {
+        pin_init!(Self {
+            inner: LockedBy::new(
+                &owner.inner,
+                NodeInner {
+                    strong: CountState::new(),
+                    weak: CountState::new(),
+                    delivery_state: DeliveryState {
+                        has_pushed_node: false,
+                        has_pushed_wrapper: false,
+                        has_weak_zero2one: false,
+                        has_strong_zero2one: false,
+                    },
+                    death_list: List::new(),
+                    oneway_todo: List::new(),
+                    freeze_list: KVVec::new(),
+                    has_oneway_transaction: false,
+                    active_inc_refs: 0,
+                    refs: List::new(),
+                },
+            ),
+            debug_id: super::next_debug_id(),
+            ptr,
+            cookie,
+            flags,
+            owner,
+            links_track <- AtomicTracker::new(),
+        })
+    }
+
+    pub(crate) fn has_oneway_transaction(&self, owner_inner: &mut ProcessInner) -> bool {
+        let inner = self.inner.access_mut(owner_inner);
+        inner.has_oneway_transaction
+    }
+
+    #[inline(never)]
+    pub(crate) fn full_debug_print(
+        &self,
+        m: &SeqFile,
+        owner_inner: &mut ProcessInner,
+    ) -> Result<()> {
+        let inner = self.inner.access_mut(owner_inner);
+        seq_print!(
+            m,
+            "  node {}: u{:016x} c{:016x} hs {} hw {} cs {} cw {}",
+            self.debug_id,
+            self.ptr,
+            self.cookie,
+            inner.strong.has_count,
+            inner.weak.has_count,
+            inner.strong.count,
+            inner.weak.count,
+        );
+        if !inner.refs.is_empty() {
+            seq_print!(m, " proc");
+            for node_ref in &inner.refs {
+                seq_print!(m, " {}", node_ref.process.task.pid());
+            }
+        }
+        seq_print!(m, "\n");
+        for t in &inner.oneway_todo {
+            t.debug_print_inner(m, "    pending async transaction ");
+        }
+        Ok(())
+    }
+
+    /// Insert the `NodeRef` into this `refs` list.
+    ///
+    /// # Safety
+    ///
+    /// It must be the case that `info.node_ref.node` is this node.
+    pub(crate) unsafe fn insert_node_info(
+        &self,
+        info: ListArc<NodeRefInfo, { NodeRefInfo::LIST_NODE }>,
+    ) {
+        self.inner
+            .access_mut(&mut self.owner.inner.lock())
+            .refs
+            .push_front(info);
+    }
+
+    /// Insert the `NodeRef` into this `refs` list.
+    ///
+    /// # Safety
+    ///
+    /// It must be the case that `info.node_ref.node` is this node.
+    pub(crate) unsafe fn remove_node_info(
+        &self,
+        info: &NodeRefInfo,
+    ) -> Option<ListArc<NodeRefInfo, { NodeRefInfo::LIST_NODE }>> {
+        // SAFETY: We always insert `NodeRefInfo` objects into the `refs` list of the node that it
+        // references in `info.node_ref.node`. That is this node, so `info` cannot possibly be in
+        // the `refs` list of another node.
+        unsafe {
+            self.inner
+                .access_mut(&mut self.owner.inner.lock())
+                .refs
+                .remove(info)
+        }
+    }
+
+    /// An id that is unique across all binder nodes on the system. Used as the key in the
+    /// `by_node` map.
+    pub(crate) fn global_id(&self) -> usize {
+        self as *const Node as usize
+    }
+
+    pub(crate) fn get_id(&self) -> (u64, u64) {
+        (self.ptr, self.cookie)
+    }
+
+    pub(crate) fn add_death(
+        &self,
+        death: ListArc<DTRWrap<NodeDeath>, 1>,
+        guard: &mut Guard<'_, ProcessInner, SpinLockBackend>,
+    ) {
+        self.inner.access_mut(guard).death_list.push_back(death);
+    }
+
+    pub(crate) fn inc_ref_done_locked(
+        self: &DArc<Node>,
+        _strong: bool,
+        owner_inner: &mut ProcessInner,
+    ) -> Option<DLArc<Node>> {
+        let inner = self.inner.access_mut(owner_inner);
+        if inner.active_inc_refs == 0 {
+            pr_err!("inc_ref_done called when no active inc_refs");
+            return None;
+        }
+
+        inner.active_inc_refs -= 1;
+        if inner.active_inc_refs == 0 {
+            // Having active inc_refs can inhibit dropping of ref-counts. Calculate whether we
+            // would send a refcount decrement, and if so, tell the caller to schedule us.
+            let strong = inner.strong.count > 0;
+            let has_strong = inner.strong.has_count;
+            let weak = strong || inner.weak.count > 0;
+            let has_weak = inner.weak.has_count;
+
+            let should_drop_weak = !weak && has_weak;
+            let should_drop_strong = !strong && has_strong;
+
+            // If we want to drop the ref-count again, tell the caller to schedule a work node for
+            // that.
+            let need_push = should_drop_weak || should_drop_strong;
+
+            if need_push && inner.delivery_state.should_normal_push() {
+                let list_arc = ListArc::try_from_arc(self.clone()).ok().unwrap();
+                inner.delivery_state.did_normal_push();
+                Some(list_arc)
+            } else {
+                None
+            }
+        } else {
+            None
+        }
+    }
+
+    pub(crate) fn update_refcount_locked(
+        self: &DArc<Node>,
+        inc: bool,
+        strong: bool,
+        count: usize,
+        owner_inner: &mut ProcessInner,
+    ) -> Option<DLArc<Node>> {
+        let is_dead = owner_inner.is_dead;
+        let inner = self.inner.access_mut(owner_inner);
+
+        // Get a reference to the state we'll update.
+        let state = if strong {
+            &mut inner.strong
+        } else {
+            &mut inner.weak
+        };
+
+        // Update the count and determine whether we need to push work.
+        let need_push = if inc {
+            state.count += count;
+            // TODO: This method shouldn't be used for zero-to-one increments.
+            !is_dead && !state.has_count
+        } else {
+            if state.count < count {
+                pr_err!("Failure: refcount underflow!");
+                return None;
+            }
+            state.count -= count;
+            !is_dead && state.count == 0 && state.has_count
+        };
+
+        if need_push && inner.delivery_state.should_normal_push() {
+            let list_arc = ListArc::try_from_arc(self.clone()).ok().unwrap();
+            inner.delivery_state.did_normal_push();
+            Some(list_arc)
+        } else {
+            None
+        }
+    }
+
+    pub(crate) fn incr_refcount_allow_zero2one(
+        self: &DArc<Self>,
+        strong: bool,
+        owner_inner: &mut ProcessInner,
+    ) -> Result<Option<DLArc<Node>>, CouldNotDeliverCriticalIncrement> {
+        let is_dead = owner_inner.is_dead;
+        let inner = self.inner.access_mut(owner_inner);
+
+        // Get a reference to the state we'll update.
+        let state = if strong {
+            &mut inner.strong
+        } else {
+            &mut inner.weak
+        };
+
+        // Update the count and determine whether we need to push work.
+        state.count += 1;
+        if is_dead || state.has_count {
+            return Ok(None);
+        }
+
+        // Userspace needs to be notified of this.
+        if !strong && inner.delivery_state.should_push_weak_zero2one() {
+            assert!(inner.delivery_state.can_push_weak_zero2one_normally());
+            let list_arc = ListArc::try_from_arc(self.clone()).ok().unwrap();
+            inner.delivery_state.did_push_weak_zero2one();
+            Ok(Some(list_arc))
+        } else if strong && inner.delivery_state.should_push_strong_zero2one() {
+            if inner.delivery_state.can_push_strong_zero2one_normally() {
+                let list_arc = ListArc::try_from_arc(self.clone()).ok().unwrap();
+                inner.delivery_state.did_push_strong_zero2one();
+                Ok(Some(list_arc))
+            } else {
+                state.count -= 1;
+                Err(CouldNotDeliverCriticalIncrement)
+            }
+        } else {
+            // Work is already pushed, and we don't need to push again.
+            Ok(None)
+        }
+    }
+
+    pub(crate) fn incr_refcount_allow_zero2one_with_wrapper(
+        self: &DArc<Self>,
+        strong: bool,
+        wrapper: CritIncrWrapper,
+        owner_inner: &mut ProcessInner,
+    ) -> Option<DLArc<dyn DeliverToRead>> {
+        match self.incr_refcount_allow_zero2one(strong, owner_inner) {
+            Ok(Some(node)) => Some(node as _),
+            Ok(None) => None,
+            Err(CouldNotDeliverCriticalIncrement) => {
+                assert!(strong);
+                let inner = self.inner.access_mut(owner_inner);
+                inner.strong.count += 1;
+                inner.delivery_state.did_push_strong_zero2one_wrapper();
+                Some(wrapper.init(self.clone()))
+            }
+        }
+    }
+
+    pub(crate) fn update_refcount(self: &DArc<Self>, inc: bool, count: usize, strong: bool) {
+        self.owner
+            .inner
+            .lock()
+            .update_node_refcount(self, inc, strong, count, None);
+    }
+
+    pub(crate) fn populate_counts(
+        &self,
+        out: &mut BinderNodeInfoForRef,
+        guard: &Guard<'_, ProcessInner, SpinLockBackend>,
+    ) {
+        let inner = self.inner.access(guard);
+        out.strong_count = inner.strong.count as _;
+        out.weak_count = inner.weak.count as _;
+    }
+
+    pub(crate) fn populate_debug_info(
+        &self,
+        out: &mut BinderNodeDebugInfo,
+        guard: &Guard<'_, ProcessInner, SpinLockBackend>,
+    ) {
+        out.ptr = self.ptr as _;
+        out.cookie = self.cookie as _;
+        let inner = self.inner.access(guard);
+        if inner.strong.has_count {
+            out.has_strong_ref = 1;
+        }
+        if inner.weak.has_count {
+            out.has_weak_ref = 1;
+        }
+    }
+
+    pub(crate) fn force_has_count(&self, guard: &mut Guard<'_, ProcessInner, SpinLockBackend>) {
+        let inner = self.inner.access_mut(guard);
+        inner.strong.has_count = true;
+        inner.weak.has_count = true;
+    }
+
+    fn write(&self, writer: &mut BinderReturnWriter<'_>, code: u32) -> Result {
+        writer.write_code(code)?;
+        writer.write_payload(&self.ptr)?;
+        writer.write_payload(&self.cookie)?;
+        Ok(())
+    }
+
+    pub(crate) fn submit_oneway(
+        &self,
+        transaction: DLArc<Transaction>,
+        guard: &mut Guard<'_, ProcessInner, SpinLockBackend>,
+    ) -> Result<(), (BinderError, DLArc<dyn DeliverToRead>)> {
+        if guard.is_dead {
+            return Err((BinderError::new_dead(), transaction));
+        }
+
+        let inner = self.inner.access_mut(guard);
+        if inner.has_oneway_transaction {
+            inner.oneway_todo.push_back(transaction);
+        } else {
+            inner.has_oneway_transaction = true;
+            guard.push_work(transaction)?;
+        }
+        Ok(())
+    }
+
+    pub(crate) fn release(&self) {
+        let mut guard = self.owner.inner.lock();
+        while let Some(work) = self.inner.access_mut(&mut guard).oneway_todo.pop_front() {
+            drop(guard);
+            work.into_arc().cancel();
+            guard = self.owner.inner.lock();
+        }
+
+        while let Some(death) = self.inner.access_mut(&mut guard).death_list.pop_front() {
+            drop(guard);
+            death.into_arc().set_dead();
+            guard = self.owner.inner.lock();
+        }
+    }
+
+    pub(crate) fn pending_oneway_finished(&self) {
+        let mut guard = self.owner.inner.lock();
+        if guard.is_dead {
+            // Cleanup will happen in `Process::deferred_release`.
+            return;
+        }
+
+        let inner = self.inner.access_mut(&mut guard);
+
+        let transaction = inner.oneway_todo.pop_front();
+        inner.has_oneway_transaction = transaction.is_some();
+        if let Some(transaction) = transaction {
+            match guard.push_work(transaction) {
+                Ok(()) => {}
+                Err((_err, work)) => {
+                    // Process is dead.
+                    // This shouldn't happen due to the `is_dead` check, but if it does, just drop
+                    // the transaction and return.
+                    drop(guard);
+                    drop(work);
+                }
+            }
+        }
+    }
+
+    /// Finds an outdated transaction that the given transaction can replace.
+    ///
+    /// If one is found, it is removed from the list and returned.
+    pub(crate) fn take_outdated_transaction(
+        &self,
+        new: &Transaction,
+        guard: &mut Guard<'_, ProcessInner, SpinLockBackend>,
+    ) -> Option<DLArc<Transaction>> {
+        let inner = self.inner.access_mut(guard);
+        let mut cursor = inner.oneway_todo.cursor_front();
+        while let Some(next) = cursor.peek_next() {
+            if new.can_replace(&next) {
+                return Some(next.remove());
+            }
+            cursor.move_next();
+        }
+        None
+    }
+
+    /// This is split into a separate function since it's called by both `Node::do_work` and
+    /// `NodeWrapper::do_work`.
+    fn do_work_locked(
+        &self,
+        writer: &mut BinderReturnWriter<'_>,
+        mut guard: Guard<'_, ProcessInner, SpinLockBackend>,
+    ) -> Result<bool> {
+        let inner = self.inner.access_mut(&mut guard);
+        let strong = inner.strong.count > 0;
+        let has_strong = inner.strong.has_count;
+        let weak = strong || inner.weak.count > 0;
+        let has_weak = inner.weak.has_count;
+
+        if weak && !has_weak {
+            inner.weak.has_count = true;
+            inner.active_inc_refs += 1;
+        }
+
+        if strong && !has_strong {
+            inner.strong.has_count = true;
+            inner.active_inc_refs += 1;
+        }
+
+        let no_active_inc_refs = inner.active_inc_refs == 0;
+        let should_drop_weak = no_active_inc_refs && (!weak && has_weak);
+        let should_drop_strong = no_active_inc_refs && (!strong && has_strong);
+        if should_drop_weak {
+            inner.weak.has_count = false;
+        }
+        if should_drop_strong {
+            inner.strong.has_count = false;
+        }
+        if no_active_inc_refs && !weak {
+            // Remove the node if there are no references to it.
+            guard.remove_node(self.ptr);
+        }
+        drop(guard);
+
+        if weak && !has_weak {
+            self.write(writer, BR_INCREFS)?;
+        }
+        if strong && !has_strong {
+            self.write(writer, BR_ACQUIRE)?;
+        }
+        if should_drop_strong {
+            self.write(writer, BR_RELEASE)?;
+        }
+        if should_drop_weak {
+            self.write(writer, BR_DECREFS)?;
+        }
+
+        Ok(true)
+    }
+
+    pub(crate) fn add_freeze_listener(
+        &self,
+        process: &Arc<Process>,
+        flags: kernel::alloc::Flags,
+    ) -> Result {
+        let mut vec_alloc = KVVec::<Arc<Process>>::new();
+        loop {
+            let mut guard = self.owner.inner.lock();
+            // Do not check for `guard.dead`. The `dead` flag that matters here is the owner of the
+            // listener, no the target.
+            let inner = self.inner.access_mut(&mut guard);
+            let len = inner.freeze_list.len();
+            if len >= inner.freeze_list.capacity() {
+                if len >= vec_alloc.capacity() {
+                    drop(guard);
+                    vec_alloc = KVVec::with_capacity((1 + len).next_power_of_two(), flags)?;
+                    continue;
+                }
+                mem::swap(&mut inner.freeze_list, &mut vec_alloc);
+                for elem in vec_alloc.drain_all() {
+                    inner.freeze_list.push_within_capacity(elem)?;
+                }
+            }
+            inner.freeze_list.push_within_capacity(process.clone())?;
+            return Ok(());
+        }
+    }
+
+    pub(crate) fn remove_freeze_listener(&self, p: &Arc<Process>) {
+        let _unused_capacity;
+        let mut guard = self.owner.inner.lock();
+        let inner = self.inner.access_mut(&mut guard);
+        let len = inner.freeze_list.len();
+        inner.freeze_list.retain(|proc| !Arc::ptr_eq(proc, p));
+        if len == inner.freeze_list.len() {
+            pr_warn!(
+                "Could not remove freeze listener for {}\n",
+                p.pid_in_current_ns()
+            );
+        }
+        if inner.freeze_list.is_empty() {
+            _unused_capacity = mem::take(&mut inner.freeze_list);
+        }
+    }
+
+    pub(crate) fn freeze_list<'a>(&'a self, guard: &'a ProcessInner) -> &'a [Arc<Process>] {
+        &self.inner.access(guard).freeze_list
+    }
+}
+
+impl DeliverToRead for Node {
+    fn do_work(
+        self: DArc<Self>,
+        _thread: &Thread,
+        writer: &mut BinderReturnWriter<'_>,
+    ) -> Result<bool> {
+        let mut owner_inner = self.owner.inner.lock();
+        let inner = self.inner.access_mut(&mut owner_inner);
+
+        assert!(inner.delivery_state.has_pushed_node);
+        if inner.delivery_state.has_pushed_wrapper {
+            // If the wrapper is scheduled, then we are either a normal push or weak zero2one
+            // increment, and the wrapper is a strong zero2one increment, so the wrapper always
+            // takes precedence over us.
+            assert!(inner.delivery_state.has_strong_zero2one);
+            inner.delivery_state.has_pushed_node = false;
+            inner.delivery_state.has_weak_zero2one = false;
+            return Ok(true);
+        }
+
+        inner.delivery_state.has_pushed_node = false;
+        inner.delivery_state.has_weak_zero2one = false;
+        inner.delivery_state.has_strong_zero2one = false;
+
+        self.do_work_locked(writer, owner_inner)
+    }
+
+    fn cancel(self: DArc<Self>) {}
+
+    fn should_sync_wakeup(&self) -> bool {
+        false
+    }
+
+    #[inline(never)]
+    fn debug_print(&self, m: &SeqFile, prefix: &str, _tprefix: &str) -> Result<()> {
+        seq_print!(
+            m,
+            "{}node work {}: u{:016x} c{:016x}\n",
+            prefix,
+            self.debug_id,
+            self.ptr,
+            self.cookie,
+        );
+        Ok(())
+    }
+}
+
+/// Represents something that holds one or more ref-counts to a `Node`.
+///
+/// Whenever process A holds a refcount to a node owned by a different process B, then process A
+/// will store a `NodeRef` that refers to the `Node` in process B. When process A releases the
+/// refcount, we destroy the NodeRef, which decrements the ref-count in process A.
+///
+/// This type is also used for some other cases. For example, a transaction allocation holds a
+/// refcount on the target node, and this is implemented by storing a `NodeRef` in the allocation
+/// so that the destructor of the allocation will drop a refcount of the `Node`.
+pub(crate) struct NodeRef {
+    pub(crate) node: DArc<Node>,
+    /// How many times does this NodeRef hold a refcount on the Node?
+    strong_node_count: usize,
+    weak_node_count: usize,
+    /// How many times does userspace hold a refcount on this NodeRef?
+    strong_count: usize,
+    weak_count: usize,
+}
+
+impl NodeRef {
+    pub(crate) fn new(node: DArc<Node>, strong_count: usize, weak_count: usize) -> Self {
+        Self {
+            node,
+            strong_node_count: strong_count,
+            weak_node_count: weak_count,
+            strong_count,
+            weak_count,
+        }
+    }
+
+    pub(crate) fn absorb(&mut self, mut other: Self) {
+        assert!(
+            Arc::ptr_eq(&self.node, &other.node),
+            "absorb called with differing nodes"
+        );
+        self.strong_node_count += other.strong_node_count;
+        self.weak_node_count += other.weak_node_count;
+        self.strong_count += other.strong_count;
+        self.weak_count += other.weak_count;
+        other.strong_count = 0;
+        other.weak_count = 0;
+        other.strong_node_count = 0;
+        other.weak_node_count = 0;
+
+        if self.strong_node_count >= 2 || self.weak_node_count >= 2 {
+            let mut guard = self.node.owner.inner.lock();
+            let inner = self.node.inner.access_mut(&mut guard);
+
+            if self.strong_node_count >= 2 {
+                inner.strong.count -= self.strong_node_count - 1;
+                self.strong_node_count = 1;
+                assert_ne!(inner.strong.count, 0);
+            }
+            if self.weak_node_count >= 2 {
+                inner.weak.count -= self.weak_node_count - 1;
+                self.weak_node_count = 1;
+                assert_ne!(inner.weak.count, 0);
+            }
+        }
+    }
+
+    pub(crate) fn get_count(&self) -> (usize, usize) {
+        (self.strong_count, self.weak_count)
+    }
+
+    pub(crate) fn clone(&self, strong: bool) -> Result<NodeRef> {
+        if strong && self.strong_count == 0 {
+            return Err(EINVAL);
+        }
+        Ok(self
+            .node
+            .owner
+            .inner
+            .lock()
+            .new_node_ref(self.node.clone(), strong, None))
+    }
+
+    /// Updates (increments or decrements) the number of references held against the node. If the
+    /// count being updated transitions from 0 to 1 or from 1 to 0, the node is notified by having
+    /// its `update_refcount` function called.
+    ///
+    /// Returns whether `self` should be removed (when both counts are zero).
+    pub(crate) fn update(&mut self, inc: bool, strong: bool) -> bool {
+        if strong && self.strong_count == 0 {
+            return false;
+        }
+        let (count, node_count, other_count) = if strong {
+            (
+                &mut self.strong_count,
+                &mut self.strong_node_count,
+                self.weak_count,
+            )
+        } else {
+            (
+                &mut self.weak_count,
+                &mut self.weak_node_count,
+                self.strong_count,
+            )
+        };
+        if inc {
+            if *count == 0 {
+                *node_count = 1;
+                self.node.update_refcount(true, 1, strong);
+            }
+            *count += 1;
+        } else {
+            if *count == 0 {
+                pr_warn!(
+                    "pid {} performed invalid decrement on ref\n",
+                    kernel::current!().pid()
+                );
+                return false;
+            }
+            *count -= 1;
+            if *count == 0 {
+                self.node.update_refcount(false, *node_count, strong);
+                *node_count = 0;
+                return other_count == 0;
+            }
+        }
+        false
+    }
+}
+
+impl Drop for NodeRef {
+    // This destructor is called conditionally from `Allocation::drop`. That branch is often
+    // mispredicted. Inlining this method call reduces the cost of those branch mispredictions.
+    #[inline(always)]
+    fn drop(&mut self) {
+        if self.strong_node_count > 0 {
+            self.node
+                .update_refcount(false, self.strong_node_count, true);
+        }
+        if self.weak_node_count > 0 {
+            self.node
+                .update_refcount(false, self.weak_node_count, false);
+        }
+    }
+}
+
+struct NodeDeathInner {
+    dead: bool,
+    cleared: bool,
+    notification_done: bool,
+    /// Indicates whether the normal flow was interrupted by removing the handle. In this case, we
+    /// need behave as if the death notification didn't exist (i.e., we don't deliver anything to
+    /// the user.
+    aborted: bool,
+}
+
+/// Used to deliver notifications when a process dies.
+///
+/// A process can request to be notified when a process dies using `BC_REQUEST_DEATH_NOTIFICATION`.
+/// This will make the driver send a `BR_DEAD_BINDER` to userspace when the process dies (or
+/// immediately if it is already dead). Userspace is supposed to respond with `BC_DEAD_BINDER_DONE`
+/// once it has processed the notification.
+///
+/// Userspace can unregister from death notifications using the `BC_CLEAR_DEATH_NOTIFICATION`
+/// command. In this case, the kernel will respond with `BR_CLEAR_DEATH_NOTIFICATION_DONE` once the
+/// notification has been removed. Note that if the remote process dies before the kernel has
+/// responded with `BR_CLEAR_DEATH_NOTIFICATION_DONE`, then the kernel will still send a
+/// `BR_DEAD_BINDER`, which userspace must be able to process. In this case, the kernel will wait
+/// for the `BC_DEAD_BINDER_DONE` command before it sends `BR_CLEAR_DEATH_NOTIFICATION_DONE`.
+///
+/// Note that even if the kernel sends a `BR_DEAD_BINDER`, this does not remove the death
+/// notification. Userspace must still remove it manually using `BC_CLEAR_DEATH_NOTIFICATION`.
+///
+/// If a process uses `BC_RELEASE` to destroy its last refcount on a node that has an active death
+/// registration, then the death registration is immediately deleted (we implement this using the
+/// `aborted` field). However, userspace is not supposed to delete a `NodeRef` without first
+/// deregistering death notifications, so this codepath is not executed under normal circumstances.
+#[pin_data]
+pub(crate) struct NodeDeath {
+    node: DArc<Node>,
+    process: Arc<Process>,
+    pub(crate) cookie: u64,
+    #[pin]
+    links_track: AtomicTracker<0>,
+    /// Used by the owner `Node` to store a list of registered death notifications.
+    ///
+    /// # Invariants
+    ///
+    /// Only ever used with the `death_list` list of `self.node`.
+    #[pin]
+    death_links: ListLinks<1>,
+    /// Used by the process to keep track of the death notifications for which we have sent a
+    /// `BR_DEAD_BINDER` but not yet received a `BC_DEAD_BINDER_DONE`.
+    ///
+    /// # Invariants
+    ///
+    /// Only ever used with the `delivered_deaths` list of `self.process`.
+    #[pin]
+    delivered_links: ListLinks<2>,
+    #[pin]
+    delivered_links_track: AtomicTracker<2>,
+    #[pin]
+    inner: SpinLock<NodeDeathInner>,
+}
+
+impl NodeDeath {
+    /// Constructs a new node death notification object.
+    pub(crate) fn new(
+        node: DArc<Node>,
+        process: Arc<Process>,
+        cookie: u64,
+    ) -> impl PinInit<DTRWrap<Self>> {
+        DTRWrap::new(pin_init!(
+            Self {
+                node,
+                process,
+                cookie,
+                links_track <- AtomicTracker::new(),
+                death_links <- ListLinks::new(),
+                delivered_links <- ListLinks::new(),
+                delivered_links_track <- AtomicTracker::new(),
+                inner <- kernel::new_spinlock!(NodeDeathInner {
+                    dead: false,
+                    cleared: false,
+                    notification_done: false,
+                    aborted: false,
+                }, "NodeDeath::inner"),
+            }
+        ))
+    }
+
+    /// Sets the cleared flag to `true`.
+    ///
+    /// It removes `self` from the node's death notification list if needed.
+    ///
+    /// Returns whether it needs to be queued.
+    pub(crate) fn set_cleared(self: &DArc<Self>, abort: bool) -> bool {
+        let (needs_removal, needs_queueing) = {
+            // Update state and determine if we need to queue a work item. We only need to do it
+            // when the node is not dead or if the user already completed the death notification.
+            let mut inner = self.inner.lock();
+            if abort {
+                inner.aborted = true;
+            }
+            if inner.cleared {
+                // Already cleared.
+                return false;
+            }
+            inner.cleared = true;
+            (!inner.dead, !inner.dead || inner.notification_done)
+        };
+
+        // Remove death notification from node.
+        if needs_removal {
+            let mut owner_inner = self.node.owner.inner.lock();
+            let node_inner = self.node.inner.access_mut(&mut owner_inner);
+            // SAFETY: A `NodeDeath` is never inserted into the death list of any node other than
+            // its owner, so it is either in this death list or in no death list.
+            unsafe { node_inner.death_list.remove(self) };
+        }
+        needs_queueing
+    }
+
+    /// Sets the 'notification done' flag to `true`.
+    pub(crate) fn set_notification_done(self: DArc<Self>, thread: &Thread) {
+        let needs_queueing = {
+            let mut inner = self.inner.lock();
+            inner.notification_done = true;
+            inner.cleared
+        };
+        if needs_queueing {
+            if let Some(death) = ListArc::try_from_arc_or_drop(self) {
+                let _ = thread.push_work_if_looper(death);
+            }
+        }
+    }
+
+    /// Sets the 'dead' flag to `true` and queues work item if needed.
+    pub(crate) fn set_dead(self: DArc<Self>) {
+        let needs_queueing = {
+            let mut inner = self.inner.lock();
+            if inner.cleared {
+                false
+            } else {
+                inner.dead = true;
+                true
+            }
+        };
+        if needs_queueing {
+            // Push the death notification to the target process. There is nothing else to do if
+            // it's already dead.
+            if let Some(death) = ListArc::try_from_arc_or_drop(self) {
+                let process = death.process.clone();
+                let _ = process.push_work(death);
+            }
+        }
+    }
+}
+
+kernel::list::impl_list_arc_safe! {
+    impl ListArcSafe<0> for NodeDeath {
+        tracked_by links_track: AtomicTracker;
+    }
+}
+
+kernel::list::impl_list_arc_safe! {
+    impl ListArcSafe<1> for DTRWrap<NodeDeath> { untracked; }
+}
+kernel::list::impl_list_item! {
+    impl ListItem<1> for DTRWrap<NodeDeath> {
+        using ListLinks { self.wrapped.death_links };
+    }
+}
+
+kernel::list::impl_list_arc_safe! {
+    impl ListArcSafe<2> for DTRWrap<NodeDeath> {
+        tracked_by wrapped: NodeDeath;
+    }
+}
+kernel::list::impl_list_arc_safe! {
+    impl ListArcSafe<2> for NodeDeath {
+        tracked_by delivered_links_track: AtomicTracker<2>;
+    }
+}
+kernel::list::impl_list_item! {
+    impl ListItem<2> for DTRWrap<NodeDeath> {
+        using ListLinks { self.wrapped.delivered_links };
+    }
+}
+
+impl DeliverToRead for NodeDeath {
+    fn do_work(
+        self: DArc<Self>,
+        _thread: &Thread,
+        writer: &mut BinderReturnWriter<'_>,
+    ) -> Result<bool> {
+        let done = {
+            let inner = self.inner.lock();
+            if inner.aborted {
+                return Ok(true);
+            }
+            inner.cleared && (!inner.dead || inner.notification_done)
+        };
+
+        let cookie = self.cookie;
+        let cmd = if done {
+            BR_CLEAR_DEATH_NOTIFICATION_DONE
+        } else {
+            let process = self.process.clone();
+            let mut process_inner = process.inner.lock();
+            let inner = self.inner.lock();
+            if inner.aborted {
+                return Ok(true);
+            }
+            // We're still holding the inner lock, so it cannot be aborted while we insert it into
+            // the delivered list.
+            process_inner.death_delivered(self.clone());
+            BR_DEAD_BINDER
+        };
+
+        writer.write_code(cmd)?;
+        writer.write_payload(&cookie)?;
+        // DEAD_BINDER notifications can cause transactions, so stop processing work items when we
+        // get to a death notification.
+        Ok(cmd != BR_DEAD_BINDER)
+    }
+
+    fn cancel(self: DArc<Self>) {}
+
+    fn should_sync_wakeup(&self) -> bool {
+        false
+    }
+
+    #[inline(never)]
+    fn debug_print(&self, m: &SeqFile, prefix: &str, _tprefix: &str) -> Result<()> {
+        let inner = self.inner.lock();
+
+        let dead_binder = inner.dead && !inner.notification_done;
+
+        if dead_binder {
+            if inner.cleared {
+                seq_print!(m, "{}has cleared dead binder\n", prefix);
+            } else {
+                seq_print!(m, "{}has dead binder\n", prefix);
+            }
+        } else {
+            seq_print!(m, "{}has cleared death notification\n", prefix);
+        }
+
+        Ok(())
+    }
+}
diff --git a/drivers/android/binder/node/wrapper.rs b/drivers/android/binder/node/wrapper.rs
new file mode 100644
index 000000000000..43294c050502
--- /dev/null
+++ b/drivers/android/binder/node/wrapper.rs
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0
+
+// Copyright (C) 2025 Google LLC.
+
+use kernel::{list::ListArc, prelude::*, seq_file::SeqFile, seq_print, sync::UniqueArc};
+
+use crate::{node::Node, thread::Thread, BinderReturnWriter, DArc, DLArc, DTRWrap, DeliverToRead};
+
+use core::mem::MaybeUninit;
+
+pub(crate) struct CritIncrWrapper {
+    inner: UniqueArc<MaybeUninit<DTRWrap<NodeWrapper>>>,
+}
+
+impl CritIncrWrapper {
+    pub(crate) fn new() -> Result<Self> {
+        Ok(CritIncrWrapper {
+            inner: UniqueArc::new_uninit(GFP_KERNEL)?,
+        })
+    }
+
+    pub(super) fn init(self, node: DArc<Node>) -> DLArc<dyn DeliverToRead> {
+        match self.inner.pin_init_with(DTRWrap::new(NodeWrapper { node })) {
+            Ok(initialized) => ListArc::from(initialized) as _,
+            Err(err) => match err {},
+        }
+    }
+}
+
+struct NodeWrapper {
+    node: DArc<Node>,
+}
+
+kernel::list::impl_list_arc_safe! {
+    impl ListArcSafe<0> for NodeWrapper {
+        untracked;
+    }
+}
+
+impl DeliverToRead for NodeWrapper {
+    fn do_work(
+        self: DArc<Self>,
+        _thread: &Thread,
+        writer: &mut BinderReturnWriter<'_>,
+    ) -> Result<bool> {
+        let node = &self.node;
+        let mut owner_inner = node.owner.inner.lock();
+        let inner = node.inner.access_mut(&mut owner_inner);
+
+        let ds = &mut inner.delivery_state;
+
+        assert!(ds.has_pushed_wrapper);
+        assert!(ds.has_strong_zero2one);
+        ds.has_pushed_wrapper = false;
+        ds.has_strong_zero2one = false;
+
+        node.do_work_locked(writer, owner_inner)
+    }
+
+    fn cancel(self: DArc<Self>) {}
+
+    fn should_sync_wakeup(&self) -> bool {
+        false
+    }
+
+    #[inline(never)]
+    fn debug_print(&self, m: &SeqFile, prefix: &str, _tprefix: &str) -> Result<()> {
+        seq_print!(
+            m,
+            "{}node work {}: u{:016x} c{:016x}\n",
+            prefix,
+            self.node.debug_id,
+            self.node.ptr,
+            self.node.cookie,
+        );
+        Ok(())
+    }
+}
diff --git a/drivers/android/binder/page_range.rs b/drivers/android/binder/page_range.rs
new file mode 100644
index 000000000000..9379038f61f5
--- /dev/null
+++ b/drivers/android/binder/page_range.rs
@@ -0,0 +1,734 @@
+// SPDX-License-Identifier: GPL-2.0
+
+// Copyright (C) 2025 Google LLC.
+
+//! This module has utilities for managing a page range where unused pages may be reclaimed by a
+//! vma shrinker.
+
+// To avoid deadlocks, locks are taken in the order:
+//
+//  1. mmap lock
+//  2. spinlock
+//  3. lru spinlock
+//
+// The shrinker will use trylock methods because it locks them in a different order.
+
+use core::{
+    marker::PhantomPinned,
+    mem::{size_of, size_of_val, MaybeUninit},
+    ptr,
+};
+
+use kernel::{
+    bindings,
+    error::Result,
+    ffi::{c_ulong, c_void},
+    mm::{virt, Mm, MmWithUser},
+    new_mutex, new_spinlock,
+    page::{Page, PAGE_SHIFT, PAGE_SIZE},
+    prelude::*,
+    str::CStr,
+    sync::{aref::ARef, Mutex, SpinLock},
+    task::Pid,
+    transmute::FromBytes,
+    types::Opaque,
+    uaccess::UserSliceReader,
+};
+
+/// Represents a shrinker that can be registered with the kernel.
+///
+/// Each shrinker can be used by many `ShrinkablePageRange` objects.
+#[repr(C)]
+pub(crate) struct Shrinker {
+    inner: Opaque<*mut bindings::shrinker>,
+    list_lru: Opaque<bindings::list_lru>,
+}
+
+// SAFETY: The shrinker and list_lru are thread safe.
+unsafe impl Send for Shrinker {}
+// SAFETY: The shrinker and list_lru are thread safe.
+unsafe impl Sync for Shrinker {}
+
+impl Shrinker {
+    /// Create a new shrinker.
+    ///
+    /// # Safety
+    ///
+    /// Before using this shrinker with a `ShrinkablePageRange`, the `register` method must have
+    /// been called exactly once, and it must not have returned an error.
+    pub(crate) const unsafe fn new() -> Self {
+        Self {
+            inner: Opaque::uninit(),
+            list_lru: Opaque::uninit(),
+        }
+    }
+
+    /// Register this shrinker with the kernel.
+    pub(crate) fn register(&'static self, name: &CStr) -> Result<()> {
+        // SAFETY: These fields are not yet used, so it's okay to zero them.
+        unsafe {
+            self.inner.get().write(ptr::null_mut());
+            self.list_lru.get().write_bytes(0, 1);
+        }
+
+        // SAFETY: The field is not yet used, so we can initialize it.
+        let ret = unsafe { bindings::__list_lru_init(self.list_lru.get(), false, ptr::null_mut()) };
+        if ret != 0 {
+            return Err(Error::from_errno(ret));
+        }
+
+        // SAFETY: The `name` points at a valid c string.
+        let shrinker = unsafe { bindings::shrinker_alloc(0, name.as_char_ptr()) };
+        if shrinker.is_null() {
+            // SAFETY: We initialized it, so its okay to destroy it.
+            unsafe { bindings::list_lru_destroy(self.list_lru.get()) };
+            return Err(Error::from_errno(ret));
+        }
+
+        // SAFETY: We're about to register the shrinker, and these are the fields we need to
+        // initialize. (All other fields are already zeroed.)
+        unsafe {
+            (&raw mut (*shrinker).count_objects).write(Some(rust_shrink_count));
+            (&raw mut (*shrinker).scan_objects).write(Some(rust_shrink_scan));
+            (&raw mut (*shrinker).private_data).write(self.list_lru.get().cast());
+        }
+
+        // SAFETY: The new shrinker has been fully initialized, so we can register it.
+        unsafe { bindings::shrinker_register(shrinker) };
+
+        // SAFETY: This initializes the pointer to the shrinker so that we can use it.
+        unsafe { self.inner.get().write(shrinker) };
+
+        Ok(())
+    }
+}
+
+/// A container that manages a page range in a vma.
+///
+/// The pages can be thought of as an array of booleans of whether the pages are usable. The
+/// methods `use_range` and `stop_using_range` set all booleans in a range to true or false
+/// respectively. Initially, no pages are allocated. When a page is not used, it is not freed
+/// immediately. Instead, it is made available to the memory shrinker to free it if the device is
+/// under memory pressure.
+///
+/// It's okay for `use_range` and `stop_using_range` to race with each other, although there's no
+/// way to know whether an index ends up with true or false if a call to `use_range` races with
+/// another call to `stop_using_range` on a given index.
+///
+/// It's also okay for the two methods to race with themselves, e.g. if two threads call
+/// `use_range` on the same index, then that's fine and neither call will return until the page is
+/// allocated and mapped.
+///
+/// The methods that read or write to a range require that the page is marked as in use. So it is
+/// _not_ okay to call `stop_using_range` on a page that is in use by the methods that read or
+/// write to the page.
+#[pin_data(PinnedDrop)]
+pub(crate) struct ShrinkablePageRange {
+    /// Shrinker object registered with the kernel.
+    shrinker: &'static Shrinker,
+    /// Pid using this page range. Only used as debugging information.
+    pid: Pid,
+    /// The mm for the relevant process.
+    mm: ARef<Mm>,
+    /// Used to synchronize calls to `vm_insert_page` and `zap_page_range_single`.
+    #[pin]
+    mm_lock: Mutex<()>,
+    /// Spinlock protecting changes to pages.
+    #[pin]
+    lock: SpinLock<Inner>,
+
+    /// Must not move, since page info has pointers back.
+    #[pin]
+    _pin: PhantomPinned,
+}
+
+struct Inner {
+    /// Array of pages.
+    ///
+    /// Since this is also accessed by the shrinker, we can't use a `Box`, which asserts exclusive
+    /// ownership. To deal with that, we manage it using raw pointers.
+    pages: *mut PageInfo,
+    /// Length of the `pages` array.
+    size: usize,
+    /// The address of the vma to insert the pages into.
+    vma_addr: usize,
+}
+
+// SAFETY: proper locking is in place for `Inner`
+unsafe impl Send for Inner {}
+
+type StableMmGuard =
+    kernel::sync::lock::Guard<'static, (), kernel::sync::lock::mutex::MutexBackend>;
+
+/// An array element that describes the current state of a page.
+///
+/// There are three states:
+///
+///  * Free. The page is None. The `lru` element is not queued.
+///  * Available. The page is Some. The `lru` element is queued to the shrinker's lru.
+///  * Used. The page is Some. The `lru` element is not queued.
+///
+/// When an element is available, the shrinker is able to free the page.
+#[repr(C)]
+struct PageInfo {
+    lru: bindings::list_head,
+    page: Option<Page>,
+    range: *const ShrinkablePageRange,
+}
+
+impl PageInfo {
+    /// # Safety
+    ///
+    /// The caller ensures that writing to `me.page` is ok, and that the page is not currently set.
+    unsafe fn set_page(me: *mut PageInfo, page: Page) {
+        // SAFETY: This pointer offset is in bounds.
+        let ptr = unsafe { &raw mut (*me).page };
+
+        // SAFETY: The pointer is valid for writing, so also valid for reading.
+        if unsafe { (*ptr).is_some() } {
+            pr_err!("set_page called when there is already a page");
+            // SAFETY: We will initialize the page again below.
+            unsafe { ptr::drop_in_place(ptr) };
+        }
+
+        // SAFETY: The pointer is valid for writing.
+        unsafe { ptr::write(ptr, Some(page)) };
+    }
+
+    /// # Safety
+    ///
+    /// The caller ensures that reading from `me.page` is ok for the duration of 'a.
+    unsafe fn get_page<'a>(me: *const PageInfo) -> Option<&'a Page> {
+        // SAFETY: This pointer offset is in bounds.
+        let ptr = unsafe { &raw const (*me).page };
+
+        // SAFETY: The pointer is valid for reading.
+        unsafe { (*ptr).as_ref() }
+    }
+
+    /// # Safety
+    ///
+    /// The caller ensures that writing to `me.page` is ok for the duration of 'a.
+    unsafe fn take_page(me: *mut PageInfo) -> Option<Page> {
+        // SAFETY: This pointer offset is in bounds.
+        let ptr = unsafe { &raw mut (*me).page };
+
+        // SAFETY: The pointer is valid for reading.
+        unsafe { (*ptr).take() }
+    }
+
+    /// Add this page to the lru list, if not already in the list.
+    ///
+    /// # Safety
+    ///
+    /// The pointer must be valid, and it must be the right shrinker and nid.
+    unsafe fn list_lru_add(me: *mut PageInfo, nid: i32, shrinker: &'static Shrinker) {
+        // SAFETY: This pointer offset is in bounds.
+        let lru_ptr = unsafe { &raw mut (*me).lru };
+        // SAFETY: The lru pointer is valid, and we're not using it with any other lru list.
+        unsafe { bindings::list_lru_add(shrinker.list_lru.get(), lru_ptr, nid, ptr::null_mut()) };
+    }
+
+    /// Remove this page from the lru list, if it is in the list.
+    ///
+    /// # Safety
+    ///
+    /// The pointer must be valid, and it must be the right shrinker and nid.
+    unsafe fn list_lru_del(me: *mut PageInfo, nid: i32, shrinker: &'static Shrinker) {
+        // SAFETY: This pointer offset is in bounds.
+        let lru_ptr = unsafe { &raw mut (*me).lru };
+        // SAFETY: The lru pointer is valid, and we're not using it with any other lru list.
+        unsafe { bindings::list_lru_del(shrinker.list_lru.get(), lru_ptr, nid, ptr::null_mut()) };
+    }
+}
+
+impl ShrinkablePageRange {
+    /// Create a new `ShrinkablePageRange` using the given shrinker.
+    pub(crate) fn new(shrinker: &'static Shrinker) -> impl PinInit<Self, Error> {
+        try_pin_init!(Self {
+            shrinker,
+            pid: kernel::current!().pid(),
+            mm: ARef::from(&**kernel::current!().mm().ok_or(ESRCH)?),
+            mm_lock <- new_mutex!((), "ShrinkablePageRange::mm"),
+            lock <- new_spinlock!(Inner {
+                pages: ptr::null_mut(),
+                size: 0,
+                vma_addr: 0,
+            }, "ShrinkablePageRange"),
+            _pin: PhantomPinned,
+        })
+    }
+
+    pub(crate) fn stable_trylock_mm(&self) -> Option<StableMmGuard> {
+        // SAFETY: This extends the duration of the reference. Since this call happens before
+        // `mm_lock` is taken in the destructor of `ShrinkablePageRange`, the destructor will block
+        // until the returned guard is dropped. This ensures that the guard is valid until dropped.
+        let mm_lock = unsafe { &*ptr::from_ref(&self.mm_lock) };
+
+        mm_lock.try_lock()
+    }
+
+    /// Register a vma with this page range. Returns the size of the region.
+    pub(crate) fn register_with_vma(&self, vma: &virt::VmaNew) -> Result<usize> {
+        let num_bytes = usize::min(vma.end() - vma.start(), bindings::SZ_4M as usize);
+        let num_pages = num_bytes >> PAGE_SHIFT;
+
+        if !ptr::eq::<Mm>(&*self.mm, &**vma.mm()) {
+            pr_debug!("Failed to register with vma: invalid vma->vm_mm");
+            return Err(EINVAL);
+        }
+        if num_pages == 0 {
+            pr_debug!("Failed to register with vma: size zero");
+            return Err(EINVAL);
+        }
+
+        let mut pages = KVVec::<PageInfo>::with_capacity(num_pages, GFP_KERNEL)?;
+
+        // SAFETY: This just initializes the pages array.
+        unsafe {
+            let self_ptr = self as *const ShrinkablePageRange;
+            for i in 0..num_pages {
+                let info = pages.as_mut_ptr().add(i);
+                (&raw mut (*info).range).write(self_ptr);
+                (&raw mut (*info).page).write(None);
+                let lru = &raw mut (*info).lru;
+                (&raw mut (*lru).next).write(lru);
+                (&raw mut (*lru).prev).write(lru);
+            }
+        }
+
+        let mut inner = self.lock.lock();
+        if inner.size > 0 {
+            pr_debug!("Failed to register with vma: already registered");
+            drop(inner);
+            return Err(EBUSY);
+        }
+
+        inner.pages = pages.into_raw_parts().0;
+        inner.size = num_pages;
+        inner.vma_addr = vma.start();
+
+        Ok(num_pages)
+    }
+
+    /// Make sure that the given pages are allocated and mapped.
+    ///
+    /// Must not be called from an atomic context.
+    pub(crate) fn use_range(&self, start: usize, end: usize) -> Result<()> {
+        if start >= end {
+            return Ok(());
+        }
+        let mut inner = self.lock.lock();
+        assert!(end <= inner.size);
+
+        for i in start..end {
+            // SAFETY: This pointer offset is in bounds.
+            let page_info = unsafe { inner.pages.add(i) };
+
+            // SAFETY: The pointer is valid, and we hold the lock so reading from the page is okay.
+            if let Some(page) = unsafe { PageInfo::get_page(page_info) } {
+                // Since we're going to use the page, we should remove it from the lru list so that
+                // the shrinker will not free it.
+                //
+                // SAFETY: The pointer is valid, and this is the right shrinker.
+                //
+                // The shrinker can't free the page between the check and this call to
+                // `list_lru_del` because we hold the lock.
+                unsafe { PageInfo::list_lru_del(page_info, page.nid(), self.shrinker) };
+            } else {
+                // We have to allocate a new page. Use the slow path.
+                drop(inner);
+                // SAFETY: `i < end <= inner.size` so `i` is in bounds.
+                match unsafe { self.use_page_slow(i) } {
+                    Ok(()) => {}
+                    Err(err) => {
+                        pr_warn!("Error in use_page_slow: {:?}", err);
+                        return Err(err);
+                    }
+                }
+                inner = self.lock.lock();
+            }
+        }
+        Ok(())
+    }
+
+    /// Mark the given page as in use, slow path.
+    ///
+    /// Must not be called from an atomic context.
+    ///
+    /// # Safety
+    ///
+    /// Assumes that `i` is in bounds.
+    #[cold]
+    unsafe fn use_page_slow(&self, i: usize) -> Result<()> {
+        let new_page = Page::alloc_page(GFP_KERNEL | __GFP_HIGHMEM | __GFP_ZERO)?;
+
+        let mm_mutex = self.mm_lock.lock();
+        let inner = self.lock.lock();
+
+        // SAFETY: This pointer offset is in bounds.
+        let page_info = unsafe { inner.pages.add(i) };
+
+        // SAFETY: The pointer is valid, and we hold the lock so reading from the page is okay.
+        if let Some(page) = unsafe { PageInfo::get_page(page_info) } {
+            // The page was already there, or someone else added the page while we didn't hold the
+            // spinlock.
+            //
+            // SAFETY: The pointer is valid, and this is the right shrinker.
+            //
+            // The shrinker can't free the page between the check and this call to
+            // `list_lru_del` because we hold the lock.
+            unsafe { PageInfo::list_lru_del(page_info, page.nid(), self.shrinker) };
+            return Ok(());
+        }
+
+        let vma_addr = inner.vma_addr;
+        // Release the spinlock while we insert the page into the vma.
+        drop(inner);
+
+        // No overflow since we stay in bounds of the vma.
+        let user_page_addr = vma_addr + (i << PAGE_SHIFT);
+
+        // We use `mmput_async` when dropping the `mm` because `use_page_slow` is usually used from
+        // a remote process. If the call to `mmput` races with the process shutting down, then the
+        // caller of `use_page_slow` becomes responsible for cleaning up the `mm`, which doesn't
+        // happen until it returns to userspace. However, the caller might instead go to sleep and
+        // wait for the owner of the `mm` to wake it up, which doesn't happen because it's in the
+        // middle of a shutdown process that won't complete until the `mm` is dropped. This can
+        // amount to a deadlock.
+        //
+        // Using `mmput_async` avoids this, because then the `mm` cleanup is instead queued to a
+        // workqueue.
+        MmWithUser::into_mmput_async(self.mm.mmget_not_zero().ok_or(ESRCH)?)
+            .mmap_read_lock()
+            .vma_lookup(vma_addr)
+            .ok_or(ESRCH)?
+            .as_mixedmap_vma()
+            .ok_or(ESRCH)?
+            .vm_insert_page(user_page_addr, &new_page)
+            .inspect_err(|err| {
+                pr_warn!(
+                    "Failed to vm_insert_page({}): vma_addr:{} i:{} err:{:?}",
+                    user_page_addr,
+                    vma_addr,
+                    i,
+                    err
+                )
+            })?;
+
+        let inner = self.lock.lock();
+
+        // SAFETY: The `page_info` pointer is valid and currently does not have a page. The page
+        // can be written to since we hold the lock.
+        //
+        // We released and reacquired the spinlock since we checked that the page is null, but we
+        // always hold the mm_lock mutex when setting the page to a non-null value, so it's not
+        // possible for someone else to have changed it since our check.
+        unsafe { PageInfo::set_page(page_info, new_page) };
+
+        drop(inner);
+        drop(mm_mutex);
+
+        Ok(())
+    }
+
+    /// If the given page is in use, then mark it as available so that the shrinker can free it.
+    ///
+    /// May be called from an atomic context.
+    pub(crate) fn stop_using_range(&self, start: usize, end: usize) {
+        if start >= end {
+            return;
+        }
+        let inner = self.lock.lock();
+        assert!(end <= inner.size);
+
+        for i in (start..end).rev() {
+            // SAFETY: The pointer is in bounds.
+            let page_info = unsafe { inner.pages.add(i) };
+
+            // SAFETY: Okay for reading since we have the lock.
+            if let Some(page) = unsafe { PageInfo::get_page(page_info) } {
+                // SAFETY: The pointer is valid, and it's the right shrinker.
+                unsafe { PageInfo::list_lru_add(page_info, page.nid(), self.shrinker) };
+            }
+        }
+    }
+
+    /// Helper for reading or writing to a range of bytes that may overlap with several pages.
+    ///
+    /// # Safety
+    ///
+    /// All pages touched by this operation must be in use for the duration of this call.
+    unsafe fn iterate<T>(&self, mut offset: usize, mut size: usize, mut cb: T) -> Result
+    where
+        T: FnMut(&Page, usize, usize) -> Result,
+    {
+        if size == 0 {
+            return Ok(());
+        }
+
+        let (pages, num_pages) = {
+            let inner = self.lock.lock();
+            (inner.pages, inner.size)
+        };
+        let num_bytes = num_pages << PAGE_SHIFT;
+
+        // Check that the request is within the buffer.
+        if offset.checked_add(size).ok_or(EFAULT)? > num_bytes {
+            return Err(EFAULT);
+        }
+
+        let mut page_index = offset >> PAGE_SHIFT;
+        offset &= PAGE_SIZE - 1;
+        while size > 0 {
+            let available = usize::min(size, PAGE_SIZE - offset);
+            // SAFETY: The pointer is in bounds.
+            let page_info = unsafe { pages.add(page_index) };
+            // SAFETY: The caller guarantees that this page is in the "in use" state for the
+            // duration of this call to `iterate`, so nobody will change the page.
+            let page = unsafe { PageInfo::get_page(page_info) };
+            if page.is_none() {
+                pr_warn!("Page is null!");
+            }
+            let page = page.ok_or(EFAULT)?;
+            cb(page, offset, available)?;
+            size -= available;
+            page_index += 1;
+            offset = 0;
+        }
+        Ok(())
+    }
+
+    /// Copy from userspace into this page range.
+    ///
+    /// # Safety
+    ///
+    /// All pages touched by this operation must be in use for the duration of this call.
+    pub(crate) unsafe fn copy_from_user_slice(
+        &self,
+        reader: &mut UserSliceReader,
+        offset: usize,
+        size: usize,
+    ) -> Result {
+        // SAFETY: `self.iterate` has the same safety requirements as `copy_from_user_slice`.
+        unsafe {
+            self.iterate(offset, size, |page, offset, to_copy| {
+                page.copy_from_user_slice_raw(reader, offset, to_copy)
+            })
+        }
+    }
+
+    /// Copy from this page range into kernel space.
+    ///
+    /// # Safety
+    ///
+    /// All pages touched by this operation must be in use for the duration of this call.
+    pub(crate) unsafe fn read<T: FromBytes>(&self, offset: usize) -> Result<T> {
+        let mut out = MaybeUninit::<T>::uninit();
+        let mut out_offset = 0;
+        // SAFETY: `self.iterate` has the same safety requirements as `read`.
+        unsafe {
+            self.iterate(offset, size_of::<T>(), |page, offset, to_copy| {
+                // SAFETY: The sum of `offset` and `to_copy` is bounded by the size of T.
+                let obj_ptr = (out.as_mut_ptr() as *mut u8).add(out_offset);
+                // SAFETY: The pointer points is in-bounds of the `out` variable, so it is valid.
+                page.read_raw(obj_ptr, offset, to_copy)?;
+                out_offset += to_copy;
+                Ok(())
+            })?;
+        }
+        // SAFETY: We just initialised the data.
+        Ok(unsafe { out.assume_init() })
+    }
+
+    /// Copy from kernel space into this page range.
+    ///
+    /// # Safety
+    ///
+    /// All pages touched by this operation must be in use for the duration of this call.
+    pub(crate) unsafe fn write<T: ?Sized>(&self, offset: usize, obj: &T) -> Result {
+        let mut obj_offset = 0;
+        // SAFETY: `self.iterate` has the same safety requirements as `write`.
+        unsafe {
+            self.iterate(offset, size_of_val(obj), |page, offset, to_copy| {
+                // SAFETY: The sum of `offset` and `to_copy` is bounded by the size of T.
+                let obj_ptr = (obj as *const T as *const u8).add(obj_offset);
+                // SAFETY: We have a reference to the object, so the pointer is valid.
+                page.write_raw(obj_ptr, offset, to_copy)?;
+                obj_offset += to_copy;
+                Ok(())
+            })
+        }
+    }
+
+    /// Write zeroes to the given range.
+    ///
+    /// # Safety
+    ///
+    /// All pages touched by this operation must be in use for the duration of this call.
+    pub(crate) unsafe fn fill_zero(&self, offset: usize, size: usize) -> Result {
+        // SAFETY: `self.iterate` has the same safety requirements as `copy_into`.
+        unsafe {
+            self.iterate(offset, size, |page, offset, len| {
+                page.fill_zero_raw(offset, len)
+            })
+        }
+    }
+}
+
+#[pinned_drop]
+impl PinnedDrop for ShrinkablePageRange {
+    fn drop(self: Pin<&mut Self>) {
+        let (pages, size) = {
+            let lock = self.lock.lock();
+            (lock.pages, lock.size)
+        };
+
+        if size == 0 {
+            return;
+        }
+
+        // Note: This call is also necessary for the safety of `stable_trylock_mm`.
+        let mm_lock = self.mm_lock.lock();
+
+        // This is the destructor, so unlike the other methods, we only need to worry about races
+        // with the shrinker here. Since we hold the `mm_lock`, we also can't race with the
+        // shrinker, and after this loop, the shrinker will not access any of our pages since we
+        // removed them from the lru list.
+        for i in 0..size {
+            // SAFETY: Loop is in-bounds of the size.
+            let p_ptr = unsafe { pages.add(i) };
+            // SAFETY: No other readers, so we can read.
+            if let Some(p) = unsafe { PageInfo::get_page(p_ptr) } {
+                // SAFETY: The pointer is valid and it's the right shrinker.
+                unsafe { PageInfo::list_lru_del(p_ptr, p.nid(), self.shrinker) };
+            }
+        }
+
+        drop(mm_lock);
+
+        // SAFETY: `pages` was allocated as an `KVVec<PageInfo>` with capacity `size`. Furthermore,
+        // all `size` elements are initialized. Also, the array is no longer shared with the
+        // shrinker due to the above loop.
+        drop(unsafe { KVVec::from_raw_parts(pages, size, size) });
+    }
+}
+
+/// # Safety
+/// Called by the shrinker.
+#[no_mangle]
+unsafe extern "C" fn rust_shrink_count(
+    shrink: *mut bindings::shrinker,
+    _sc: *mut bindings::shrink_control,
+) -> c_ulong {
+    // SAFETY: We can access our own private data.
+    let list_lru = unsafe { (*shrink).private_data.cast::<bindings::list_lru>() };
+    // SAFETY: Accessing the lru list is okay. Just an FFI call.
+    unsafe { bindings::list_lru_count(list_lru) }
+}
+
+/// # Safety
+/// Called by the shrinker.
+#[no_mangle]
+unsafe extern "C" fn rust_shrink_scan(
+    shrink: *mut bindings::shrinker,
+    sc: *mut bindings::shrink_control,
+) -> c_ulong {
+    // SAFETY: We can access our own private data.
+    let list_lru = unsafe { (*shrink).private_data.cast::<bindings::list_lru>() };
+    // SAFETY: Caller guarantees that it is safe to read this field.
+    let nr_to_scan = unsafe { (*sc).nr_to_scan };
+    // SAFETY: Accessing the lru list is okay. Just an FFI call.
+    unsafe {
+        bindings::list_lru_walk(
+            list_lru,
+            Some(bindings::rust_shrink_free_page_wrap),
+            ptr::null_mut(),
+            nr_to_scan,
+        )
+    }
+}
+
+const LRU_SKIP: bindings::lru_status = bindings::lru_status_LRU_SKIP;
+const LRU_REMOVED_ENTRY: bindings::lru_status = bindings::lru_status_LRU_REMOVED_RETRY;
+
+/// # Safety
+/// Called by the shrinker.
+#[no_mangle]
+unsafe extern "C" fn rust_shrink_free_page(
+    item: *mut bindings::list_head,
+    lru: *mut bindings::list_lru_one,
+    _cb_arg: *mut c_void,
+) -> bindings::lru_status {
+    // Fields that should survive after unlocking the lru lock.
+    let page;
+    let page_index;
+    let mm;
+    let mmap_read;
+    let mm_mutex;
+    let vma_addr;
+
+    {
+        // CAST: The `list_head` field is first in `PageInfo`.
+        let info = item as *mut PageInfo;
+        // SAFETY: The `range` field of `PageInfo` is immutable.
+        let range = unsafe { &*((*info).range) };
+
+        mm = match range.mm.mmget_not_zero() {
+            Some(mm) => MmWithUser::into_mmput_async(mm),
+            None => return LRU_SKIP,
+        };
+
+        mm_mutex = match range.stable_trylock_mm() {
+            Some(guard) => guard,
+            None => return LRU_SKIP,
+        };
+
+        mmap_read = match mm.mmap_read_trylock() {
+            Some(guard) => guard,
+            None => return LRU_SKIP,
+        };
+
+        // We can't lock it normally here, since we hold the lru lock.
+        let inner = match range.lock.try_lock() {
+            Some(inner) => inner,
+            None => return LRU_SKIP,
+        };
+
+        // SAFETY: The item is in this lru list, so it's okay to remove it.
+        unsafe { bindings::list_lru_isolate(lru, item) };
+
+        // SAFETY: Both pointers are in bounds of the same allocation.
+        page_index = unsafe { info.offset_from(inner.pages) } as usize;
+
+        // SAFETY: We hold the spinlock, so we can take the page.
+        //
+        // This sets the page pointer to zero before we unmap it from the vma. However, we call
+        // `zap_page_range` before we release the mmap lock, so `use_page_slow` will not be able to
+        // insert a new page until after our call to `zap_page_range`.
+        page = unsafe { PageInfo::take_page(info) };
+        vma_addr = inner.vma_addr;
+
+        // From this point on, we don't access this PageInfo or ShrinkablePageRange again, because
+        // they can be freed at any point after we unlock `lru_lock`. This is with the exception of
+        // `mm_mutex` which is kept alive by holding the lock.
+    }
+
+    // SAFETY: The lru lock is locked when this method is called.
+    unsafe { bindings::spin_unlock(&raw mut (*lru).lock) };
+
+    if let Some(vma) = mmap_read.vma_lookup(vma_addr) {
+        let user_page_addr = vma_addr + (page_index << PAGE_SHIFT);
+        vma.zap_page_range_single(user_page_addr, PAGE_SIZE);
+    }
+
+    drop(mmap_read);
+    drop(mm_mutex);
+    drop(mm);
+    drop(page);
+
+    // SAFETY: We just unlocked the lru lock, but it should be locked when we return.
+    unsafe { bindings::spin_lock(&raw mut (*lru).lock) };
+
+    LRU_REMOVED_ENTRY
+}
diff --git a/drivers/android/binder/page_range_helper.c b/drivers/android/binder/page_range_helper.c
new file mode 100644
index 000000000000..496887723ee0
--- /dev/null
+++ b/drivers/android/binder/page_range_helper.c
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* C helper for page_range.rs to work around a CFI violation.
+ *
+ * Bindgen currently pretends that `enum lru_status` is the same as an integer.
+ * This assumption is fine ABI-wise, but once you add CFI to the mix, it
+ * triggers a CFI violation because `enum lru_status` gets a different CFI tag.
+ *
+ * This file contains a workaround until bindgen can be fixed.
+ *
+ * Copyright (C) 2025 Google LLC.
+ */
+#include "page_range_helper.h"
+
+unsigned int rust_shrink_free_page(struct list_head *item,
+				   struct list_lru_one *list,
+				   void *cb_arg);
+
+enum lru_status
+rust_shrink_free_page_wrap(struct list_head *item, struct list_lru_one *list,
+			   void *cb_arg)
+{
+	return rust_shrink_free_page(item, list, cb_arg);
+}
diff --git a/drivers/android/binder/page_range_helper.h b/drivers/android/binder/page_range_helper.h
new file mode 100644
index 000000000000..18dd2dd117b2
--- /dev/null
+++ b/drivers/android/binder/page_range_helper.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2025 Google, Inc.
+ */
+
+#ifndef _LINUX_PAGE_RANGE_HELPER_H
+#define _LINUX_PAGE_RANGE_HELPER_H
+
+#include <linux/list_lru.h>
+
+enum lru_status
+rust_shrink_free_page_wrap(struct list_head *item, struct list_lru_one *list,
+			   void *cb_arg);
+
+#endif /* _LINUX_PAGE_RANGE_HELPER_H */
diff --git a/drivers/android/binder/process.rs b/drivers/android/binder/process.rs
new file mode 100644
index 000000000000..132055b4790f
--- /dev/null
+++ b/drivers/android/binder/process.rs
@@ -0,0 +1,1745 @@
+// SPDX-License-Identifier: GPL-2.0
+
+// Copyright (C) 2025 Google LLC.
+
+//! This module defines the `Process` type, which represents a process using a particular binder
+//! context.
+//!
+//! The `Process` object keeps track of all of the resources that this process owns in the binder
+//! context.
+//!
+//! There is one `Process` object for each binder fd that a process has opened, so processes using
+//! several binder contexts have several `Process` objects. This ensures that the contexts are
+//! fully separated.
+
+use core::mem::take;
+
+use kernel::{
+    bindings,
+    cred::Credential,
+    error::Error,
+    fs::file::{self, File},
+    id_pool::IdPool,
+    list::{List, ListArc, ListArcField, ListLinks},
+    mm,
+    prelude::*,
+    rbtree::{self, RBTree, RBTreeNode, RBTreeNodeReservation},
+    seq_file::SeqFile,
+    seq_print,
+    sync::poll::PollTable,
+    sync::{
+        lock::{spinlock::SpinLockBackend, Guard},
+        Arc, ArcBorrow, CondVar, CondVarTimeoutResult, Mutex, SpinLock, UniqueArc,
+    },
+    task::Task,
+    types::ARef,
+    uaccess::{UserSlice, UserSliceReader},
+    uapi,
+    workqueue::{self, Work},
+};
+
+use crate::{
+    allocation::{Allocation, AllocationInfo, NewAllocation},
+    context::Context,
+    defs::*,
+    error::{BinderError, BinderResult},
+    node::{CouldNotDeliverCriticalIncrement, CritIncrWrapper, Node, NodeDeath, NodeRef},
+    page_range::ShrinkablePageRange,
+    range_alloc::{RangeAllocator, ReserveNew, ReserveNewArgs},
+    stats::BinderStats,
+    thread::{PushWorkRes, Thread},
+    BinderfsProcFile, DArc, DLArc, DTRWrap, DeliverToRead,
+};
+
+#[path = "freeze.rs"]
+mod freeze;
+use self::freeze::{FreezeCookie, FreezeListener};
+
+struct Mapping {
+    address: usize,
+    alloc: RangeAllocator<AllocationInfo>,
+}
+
+impl Mapping {
+    fn new(address: usize, size: usize) -> Self {
+        Self {
+            address,
+            alloc: RangeAllocator::new(size),
+        }
+    }
+}
+
+// bitflags for defer_work.
+const PROC_DEFER_FLUSH: u8 = 1;
+const PROC_DEFER_RELEASE: u8 = 2;
+
+#[derive(Copy, Clone)]
+pub(crate) enum IsFrozen {
+    Yes,
+    No,
+    InProgress,
+}
+
+impl IsFrozen {
+    /// Whether incoming transactions should be rejected due to freeze.
+    pub(crate) fn is_frozen(self) -> bool {
+        match self {
+            IsFrozen::Yes => true,
+            IsFrozen::No => false,
+            IsFrozen::InProgress => true,
+        }
+    }
+
+    /// Whether freeze notifications consider this process frozen.
+    pub(crate) fn is_fully_frozen(self) -> bool {
+        match self {
+            IsFrozen::Yes => true,
+            IsFrozen::No => false,
+            IsFrozen::InProgress => false,
+        }
+    }
+}
+
+/// The fields of `Process` protected by the spinlock.
+pub(crate) struct ProcessInner {
+    is_manager: bool,
+    pub(crate) is_dead: bool,
+    threads: RBTree<i32, Arc<Thread>>,
+    /// INVARIANT: Threads pushed to this list must be owned by this process.
+    ready_threads: List<Thread>,
+    nodes: RBTree<u64, DArc<Node>>,
+    mapping: Option<Mapping>,
+    work: List<DTRWrap<dyn DeliverToRead>>,
+    delivered_deaths: List<DTRWrap<NodeDeath>, 2>,
+
+    /// The number of requested threads that haven't registered yet.
+    requested_thread_count: u32,
+    /// The maximum number of threads used by the process thread pool.
+    max_threads: u32,
+    /// The number of threads the started and registered with the thread pool.
+    started_thread_count: u32,
+
+    /// Bitmap of deferred work to do.
+    defer_work: u8,
+
+    /// Number of transactions to be transmitted before processes in freeze_wait
+    /// are woken up.
+    outstanding_txns: u32,
+    /// Process is frozen and unable to service binder transactions.
+    pub(crate) is_frozen: IsFrozen,
+    /// Process received sync transactions since last frozen.
+    pub(crate) sync_recv: bool,
+    /// Process received async transactions since last frozen.
+    pub(crate) async_recv: bool,
+    pub(crate) binderfs_file: Option<BinderfsProcFile>,
+    /// Check for oneway spam
+    oneway_spam_detection_enabled: bool,
+}
+
+impl ProcessInner {
+    fn new() -> Self {
+        Self {
+            is_manager: false,
+            is_dead: false,
+            threads: RBTree::new(),
+            ready_threads: List::new(),
+            mapping: None,
+            nodes: RBTree::new(),
+            work: List::new(),
+            delivered_deaths: List::new(),
+            requested_thread_count: 0,
+            max_threads: 0,
+            started_thread_count: 0,
+            defer_work: 0,
+            outstanding_txns: 0,
+            is_frozen: IsFrozen::No,
+            sync_recv: false,
+            async_recv: false,
+            binderfs_file: None,
+            oneway_spam_detection_enabled: false,
+        }
+    }
+
+    /// Schedule the work item for execution on this process.
+    ///
+    /// If any threads are ready for work, then the work item is given directly to that thread and
+    /// it is woken up. Otherwise, it is pushed to the process work list.
+    ///
+    /// This call can fail only if the process is dead. In this case, the work item is returned to
+    /// the caller so that the caller can drop it after releasing the inner process lock. This is
+    /// necessary since the destructor of `Transaction` will take locks that can't necessarily be
+    /// taken while holding the inner process lock.
+    pub(crate) fn push_work(
+        &mut self,
+        work: DLArc<dyn DeliverToRead>,
+    ) -> Result<(), (BinderError, DLArc<dyn DeliverToRead>)> {
+        // Try to find a ready thread to which to push the work.
+        if let Some(thread) = self.ready_threads.pop_front() {
+            // Push to thread while holding state lock. This prevents the thread from giving up
+            // (for example, because of a signal) when we're about to deliver work.
+            match thread.push_work(work) {
+                PushWorkRes::Ok => Ok(()),
+                PushWorkRes::FailedDead(work) => Err((BinderError::new_dead(), work)),
+            }
+        } else if self.is_dead {
+            Err((BinderError::new_dead(), work))
+        } else {
+            let sync = work.should_sync_wakeup();
+
+            // Didn't find a thread waiting for proc work; this can happen
+            // in two scenarios:
+            // 1. All threads are busy handling transactions
+            //    In that case, one of those threads should call back into
+            //    the kernel driver soon and pick up this work.
+            // 2. Threads are using the (e)poll interface, in which case
+            //    they may be blocked on the waitqueue without having been
+            //    added to waiting_threads. For this case, we just iterate
+            //    over all threads not handling transaction work, and
+            //    wake them all up. We wake all because we don't know whether
+            //    a thread that called into (e)poll is handling non-binder
+            //    work currently.
+            self.work.push_back(work);
+
+            // Wake up polling threads, if any.
+            for thread in self.threads.values() {
+                thread.notify_if_poll_ready(sync);
+            }
+
+            Ok(())
+        }
+    }
+
+    pub(crate) fn remove_node(&mut self, ptr: u64) {
+        self.nodes.remove(&ptr);
+    }
+
+    /// Updates the reference count on the given node.
+    pub(crate) fn update_node_refcount(
+        &mut self,
+        node: &DArc<Node>,
+        inc: bool,
+        strong: bool,
+        count: usize,
+        othread: Option<&Thread>,
+    ) {
+        let push = node.update_refcount_locked(inc, strong, count, self);
+
+        // If we decided that we need to push work, push either to the process or to a thread if
+        // one is specified.
+        if let Some(node) = push {
+            if let Some(thread) = othread {
+                thread.push_work_deferred(node);
+            } else {
+                let _ = self.push_work(node);
+                // Nothing to do: `push_work` may fail if the process is dead, but that's ok as in
+                // that case, it doesn't care about the notification.
+            }
+        }
+    }
+
+    pub(crate) fn new_node_ref(
+        &mut self,
+        node: DArc<Node>,
+        strong: bool,
+        thread: Option<&Thread>,
+    ) -> NodeRef {
+        self.update_node_refcount(&node, true, strong, 1, thread);
+        let strong_count = if strong { 1 } else { 0 };
+        NodeRef::new(node, strong_count, 1 - strong_count)
+    }
+
+    pub(crate) fn new_node_ref_with_thread(
+        &mut self,
+        node: DArc<Node>,
+        strong: bool,
+        thread: &Thread,
+        wrapper: Option<CritIncrWrapper>,
+    ) -> Result<NodeRef, CouldNotDeliverCriticalIncrement> {
+        let push = match wrapper {
+            None => node
+                .incr_refcount_allow_zero2one(strong, self)?
+                .map(|node| node as _),
+            Some(wrapper) => node.incr_refcount_allow_zero2one_with_wrapper(strong, wrapper, self),
+        };
+        if let Some(node) = push {
+            thread.push_work_deferred(node);
+        }
+        let strong_count = if strong { 1 } else { 0 };
+        Ok(NodeRef::new(node, strong_count, 1 - strong_count))
+    }
+
+    /// Returns an existing node with the given pointer and cookie, if one exists.
+    ///
+    /// Returns an error if a node with the given pointer but a different cookie exists.
+    fn get_existing_node(&self, ptr: u64, cookie: u64) -> Result<Option<DArc<Node>>> {
+        match self.nodes.get(&ptr) {
+            None => Ok(None),
+            Some(node) => {
+                let (_, node_cookie) = node.get_id();
+                if node_cookie == cookie {
+                    Ok(Some(node.clone()))
+                } else {
+                    Err(EINVAL)
+                }
+            }
+        }
+    }
+
+    fn register_thread(&mut self) -> bool {
+        if self.requested_thread_count == 0 {
+            return false;
+        }
+
+        self.requested_thread_count -= 1;
+        self.started_thread_count += 1;
+        true
+    }
+
+    /// Finds a delivered death notification with the given cookie, removes it from the thread's
+    /// delivered list, and returns it.
+    fn pull_delivered_death(&mut self, cookie: u64) -> Option<DArc<NodeDeath>> {
+        let mut cursor = self.delivered_deaths.cursor_front();
+        while let Some(next) = cursor.peek_next() {
+            if next.cookie == cookie {
+                return Some(next.remove().into_arc());
+            }
+            cursor.move_next();
+        }
+        None
+    }
+
+    pub(crate) fn death_delivered(&mut self, death: DArc<NodeDeath>) {
+        if let Some(death) = ListArc::try_from_arc_or_drop(death) {
+            self.delivered_deaths.push_back(death);
+        } else {
+            pr_warn!("Notification added to `delivered_deaths` twice.");
+        }
+    }
+
+    pub(crate) fn add_outstanding_txn(&mut self) {
+        self.outstanding_txns += 1;
+    }
+
+    fn txns_pending_locked(&self) -> bool {
+        if self.outstanding_txns > 0 {
+            return true;
+        }
+        for thread in self.threads.values() {
+            if thread.has_current_transaction() {
+                return true;
+            }
+        }
+        false
+    }
+}
+
+/// Used to keep track of a node that this process has a handle to.
+#[pin_data]
+pub(crate) struct NodeRefInfo {
+    debug_id: usize,
+    /// The refcount that this process owns to the node.
+    node_ref: ListArcField<NodeRef, { Self::LIST_PROC }>,
+    death: ListArcField<Option<DArc<NodeDeath>>, { Self::LIST_PROC }>,
+    /// Cookie of the active freeze listener for this node.
+    freeze: ListArcField<Option<FreezeCookie>, { Self::LIST_PROC }>,
+    /// Used to store this `NodeRefInfo` in the node's `refs` list.
+    #[pin]
+    links: ListLinks<{ Self::LIST_NODE }>,
+    /// The handle for this `NodeRefInfo`.
+    handle: u32,
+    /// The process that has a handle to the node.
+    pub(crate) process: Arc<Process>,
+}
+
+impl NodeRefInfo {
+    /// The id used for the `Node::refs` list.
+    pub(crate) const LIST_NODE: u64 = 0x2da16350fb724a10;
+    /// The id used for the `ListArc` in `ProcessNodeRefs`.
+    const LIST_PROC: u64 = 0xd703a5263dcc8650;
+
+    fn new(node_ref: NodeRef, handle: u32, process: Arc<Process>) -> impl PinInit<Self> {
+        pin_init!(Self {
+            debug_id: super::next_debug_id(),
+            node_ref: ListArcField::new(node_ref),
+            death: ListArcField::new(None),
+            freeze: ListArcField::new(None),
+            links <- ListLinks::new(),
+            handle,
+            process,
+        })
+    }
+
+    kernel::list::define_list_arc_field_getter! {
+        pub(crate) fn death(&mut self<{Self::LIST_PROC}>) -> &mut Option<DArc<NodeDeath>> { death }
+        pub(crate) fn freeze(&mut self<{Self::LIST_PROC}>) -> &mut Option<FreezeCookie> { freeze }
+        pub(crate) fn node_ref(&mut self<{Self::LIST_PROC}>) -> &mut NodeRef { node_ref }
+        pub(crate) fn node_ref2(&self<{Self::LIST_PROC}>) -> &NodeRef { node_ref }
+    }
+}
+
+kernel::list::impl_list_arc_safe! {
+    impl ListArcSafe<{Self::LIST_NODE}> for NodeRefInfo { untracked; }
+    impl ListArcSafe<{Self::LIST_PROC}> for NodeRefInfo { untracked; }
+}
+kernel::list::impl_list_item! {
+    impl ListItem<{Self::LIST_NODE}> for NodeRefInfo {
+        using ListLinks { self.links };
+    }
+}
+
+/// Keeps track of references this process has to nodes owned by other processes.
+///
+/// TODO: Currently, the rbtree requires two allocations per node reference, and two tree
+/// traversals to look up a node by `Node::global_id`. Once the rbtree is more powerful, these
+/// extra costs should be eliminated.
+struct ProcessNodeRefs {
+    /// Used to look up nodes using the 32-bit id that this process knows it by.
+    by_handle: RBTree<u32, ListArc<NodeRefInfo, { NodeRefInfo::LIST_PROC }>>,
+    /// Used to quickly find unused ids in `by_handle`.
+    handle_is_present: IdPool,
+    /// Used to look up nodes without knowing their local 32-bit id. The usize is the address of
+    /// the underlying `Node` struct as returned by `Node::global_id`.
+    by_node: RBTree<usize, u32>,
+    /// Used to look up a `FreezeListener` by cookie.
+    ///
+    /// There might be multiple freeze listeners for the same node, but at most one of them is
+    /// active.
+    freeze_listeners: RBTree<FreezeCookie, FreezeListener>,
+}
+
+impl ProcessNodeRefs {
+    fn new() -> Self {
+        Self {
+            by_handle: RBTree::new(),
+            handle_is_present: IdPool::new(),
+            by_node: RBTree::new(),
+            freeze_listeners: RBTree::new(),
+        }
+    }
+}
+
+/// A process using binder.
+///
+/// Strictly speaking, there can be multiple of these per process. There is one for each binder fd
+/// that a process has opened, so processes using several binder contexts have several `Process`
+/// objects. This ensures that the contexts are fully separated.
+#[pin_data]
+pub(crate) struct Process {
+    pub(crate) ctx: Arc<Context>,
+
+    // The task leader (process).
+    pub(crate) task: ARef<Task>,
+
+    // Credential associated with file when `Process` is created.
+    pub(crate) cred: ARef<Credential>,
+
+    #[pin]
+    pub(crate) inner: SpinLock<ProcessInner>,
+
+    #[pin]
+    pub(crate) pages: ShrinkablePageRange,
+
+    // Waitqueue of processes waiting for all outstanding transactions to be
+    // processed.
+    #[pin]
+    freeze_wait: CondVar,
+
+    // Node references are in a different lock to avoid recursive acquisition when
+    // incrementing/decrementing a node in another process.
+    #[pin]
+    node_refs: Mutex<ProcessNodeRefs>,
+
+    // Work node for deferred work item.
+    #[pin]
+    defer_work: Work<Process>,
+
+    // Links for process list in Context.
+    #[pin]
+    links: ListLinks,
+
+    pub(crate) stats: BinderStats,
+}
+
+kernel::impl_has_work! {
+    impl HasWork<Process> for Process { self.defer_work }
+}
+
+kernel::list::impl_list_arc_safe! {
+    impl ListArcSafe<0> for Process { untracked; }
+}
+kernel::list::impl_list_item! {
+    impl ListItem<0> for Process {
+        using ListLinks { self.links };
+    }
+}
+
+impl workqueue::WorkItem for Process {
+    type Pointer = Arc<Process>;
+
+    fn run(me: Arc<Self>) {
+        let defer;
+        {
+            let mut inner = me.inner.lock();
+            defer = inner.defer_work;
+            inner.defer_work = 0;
+        }
+
+        if defer & PROC_DEFER_FLUSH != 0 {
+            me.deferred_flush();
+        }
+        if defer & PROC_DEFER_RELEASE != 0 {
+            me.deferred_release();
+        }
+    }
+}
+
+impl Process {
+    fn new(ctx: Arc<Context>, cred: ARef<Credential>) -> Result<Arc<Self>> {
+        let current = kernel::current!();
+        let list_process = ListArc::pin_init::<Error>(
+            try_pin_init!(Process {
+                ctx,
+                cred,
+                inner <- kernel::new_spinlock!(ProcessInner::new(), "Process::inner"),
+                pages <- ShrinkablePageRange::new(&super::BINDER_SHRINKER),
+                node_refs <- kernel::new_mutex!(ProcessNodeRefs::new(), "Process::node_refs"),
+                freeze_wait <- kernel::new_condvar!("Process::freeze_wait"),
+                task: current.group_leader().into(),
+                defer_work <- kernel::new_work!("Process::defer_work"),
+                links <- ListLinks::new(),
+                stats: BinderStats::new(),
+            }),
+            GFP_KERNEL,
+        )?;
+
+        let process = list_process.clone_arc();
+        process.ctx.register_process(list_process);
+
+        Ok(process)
+    }
+
+    pub(crate) fn pid_in_current_ns(&self) -> kernel::task::Pid {
+        self.task.tgid_nr_ns(None)
+    }
+
+    #[inline(never)]
+    pub(crate) fn debug_print_stats(&self, m: &SeqFile, ctx: &Context) -> Result<()> {
+        seq_print!(m, "proc {}\n", self.pid_in_current_ns());
+        seq_print!(m, "context {}\n", &*ctx.name);
+
+        let inner = self.inner.lock();
+        seq_print!(m, "  threads: {}\n", inner.threads.iter().count());
+        seq_print!(
+            m,
+            "  requested threads: {}+{}/{}\n",
+            inner.requested_thread_count,
+            inner.started_thread_count,
+            inner.max_threads,
+        );
+        if let Some(mapping) = &inner.mapping {
+            seq_print!(
+                m,
+                "  free oneway space: {}\n",
+                mapping.alloc.free_oneway_space()
+            );
+            seq_print!(m, "  buffers: {}\n", mapping.alloc.count_buffers());
+        }
+        seq_print!(
+            m,
+            "  outstanding transactions: {}\n",
+            inner.outstanding_txns
+        );
+        seq_print!(m, "  nodes: {}\n", inner.nodes.iter().count());
+        drop(inner);
+
+        {
+            let mut refs = self.node_refs.lock();
+            let (mut count, mut weak, mut strong) = (0, 0, 0);
+            for r in refs.by_handle.values_mut() {
+                let node_ref = r.node_ref();
+                let (nstrong, nweak) = node_ref.get_count();
+                count += 1;
+                weak += nweak;
+                strong += nstrong;
+            }
+            seq_print!(m, "  refs: {count} s {strong} w {weak}\n");
+        }
+
+        self.stats.debug_print("  ", m);
+
+        Ok(())
+    }
+
+    #[inline(never)]
+    pub(crate) fn debug_print(&self, m: &SeqFile, ctx: &Context, print_all: bool) -> Result<()> {
+        seq_print!(m, "proc {}\n", self.pid_in_current_ns());
+        seq_print!(m, "context {}\n", &*ctx.name);
+
+        let mut all_threads = KVec::new();
+        let mut all_nodes = KVec::new();
+        loop {
+            let inner = self.inner.lock();
+            let num_threads = inner.threads.iter().count();
+            let num_nodes = inner.nodes.iter().count();
+
+            if all_threads.capacity() < num_threads || all_nodes.capacity() < num_nodes {
+                drop(inner);
+                all_threads.reserve(num_threads, GFP_KERNEL)?;
+                all_nodes.reserve(num_nodes, GFP_KERNEL)?;
+                continue;
+            }
+
+            for thread in inner.threads.values() {
+                assert!(all_threads.len() < all_threads.capacity());
+                let _ = all_threads.push(thread.clone(), GFP_ATOMIC);
+            }
+
+            for node in inner.nodes.values() {
+                assert!(all_nodes.len() < all_nodes.capacity());
+                let _ = all_nodes.push(node.clone(), GFP_ATOMIC);
+            }
+
+            break;
+        }
+
+        for thread in all_threads {
+            thread.debug_print(m, print_all)?;
+        }
+
+        let mut inner = self.inner.lock();
+        for node in all_nodes {
+            if print_all || node.has_oneway_transaction(&mut inner) {
+                node.full_debug_print(m, &mut inner)?;
+            }
+        }
+        drop(inner);
+
+        if print_all {
+            let mut refs = self.node_refs.lock();
+            for r in refs.by_handle.values_mut() {
+                let node_ref = r.node_ref();
+                let dead = node_ref.node.owner.inner.lock().is_dead;
+                let (strong, weak) = node_ref.get_count();
+                let debug_id = node_ref.node.debug_id;
+
+                seq_print!(
+                    m,
+                    "  ref {}: desc {} {}node {debug_id} s {strong} w {weak}",
+                    r.debug_id,
+                    r.handle,
+                    if dead { "dead " } else { "" }
+                );
+            }
+        }
+
+        let inner = self.inner.lock();
+        for work in &inner.work {
+            work.debug_print(m, "  ", "  pending transaction ")?;
+        }
+        for _death in &inner.delivered_deaths {
+            seq_print!(m, "  has delivered dead binder\n");
+        }
+        if let Some(mapping) = &inner.mapping {
+            mapping.alloc.debug_print(m)?;
+        }
+        drop(inner);
+
+        Ok(())
+    }
+
+    /// Attempts to fetch a work item from the process queue.
+    pub(crate) fn get_work(&self) -> Option<DLArc<dyn DeliverToRead>> {
+        self.inner.lock().work.pop_front()
+    }
+
+    /// Attempts to fetch a work item from the process queue. If none is available, it registers the
+    /// given thread as ready to receive work directly.
+    ///
+    /// This must only be called when the thread is not participating in a transaction chain; when
+    /// it is, work will always be delivered directly to the thread (and not through the process
+    /// queue).
+    pub(crate) fn get_work_or_register<'a>(
+        &'a self,
+        thread: &'a Arc<Thread>,
+    ) -> GetWorkOrRegister<'a> {
+        let mut inner = self.inner.lock();
+        // Try to get work from the process queue.
+        if let Some(work) = inner.work.pop_front() {
+            return GetWorkOrRegister::Work(work);
+        }
+
+        // Register the thread as ready.
+        GetWorkOrRegister::Register(Registration::new(thread, &mut inner))
+    }
+
+    fn get_current_thread(self: ArcBorrow<'_, Self>) -> Result<Arc<Thread>> {
+        let id = {
+            let current = kernel::current!();
+            if !core::ptr::eq(current.group_leader(), &*self.task) {
+                pr_err!("get_current_thread was called from the wrong process.");
+                return Err(EINVAL);
+            }
+            current.pid()
+        };
+
+        {
+            let inner = self.inner.lock();
+            if let Some(thread) = inner.threads.get(&id) {
+                return Ok(thread.clone());
+            }
+        }
+
+        // Allocate a new `Thread` without holding any locks.
+        let reservation = RBTreeNodeReservation::new(GFP_KERNEL)?;
+        let ta: Arc<Thread> = Thread::new(id, self.into())?;
+
+        let mut inner = self.inner.lock();
+        match inner.threads.entry(id) {
+            rbtree::Entry::Vacant(entry) => {
+                entry.insert(ta.clone(), reservation);
+                Ok(ta)
+            }
+            rbtree::Entry::Occupied(_entry) => {
+                pr_err!("Cannot create two threads with the same id.");
+                Err(EINVAL)
+            }
+        }
+    }
+
+    pub(crate) fn push_work(&self, work: DLArc<dyn DeliverToRead>) -> BinderResult {
+        // If push_work fails, drop the work item outside the lock.
+        let res = self.inner.lock().push_work(work);
+        match res {
+            Ok(()) => Ok(()),
+            Err((err, work)) => {
+                drop(work);
+                Err(err)
+            }
+        }
+    }
+
+    fn set_as_manager(
+        self: ArcBorrow<'_, Self>,
+        info: Option<FlatBinderObject>,
+        thread: &Thread,
+    ) -> Result {
+        let (ptr, cookie, flags) = if let Some(obj) = info {
+            (
+                // SAFETY: The object type for this ioctl is implicitly `BINDER_TYPE_BINDER`, so it
+                // is safe to access the `binder` field.
+                unsafe { obj.__bindgen_anon_1.binder },
+                obj.cookie,
+                obj.flags,
+            )
+        } else {
+            (0, 0, 0)
+        };
+        let node_ref = self.get_node(ptr, cookie, flags as _, true, thread)?;
+        let node = node_ref.node.clone();
+        self.ctx.set_manager_node(node_ref)?;
+        self.inner.lock().is_manager = true;
+
+        // Force the state of the node to prevent the delivery of acquire/increfs.
+        let mut owner_inner = node.owner.inner.lock();
+        node.force_has_count(&mut owner_inner);
+        Ok(())
+    }
+
+    fn get_node_inner(
+        self: ArcBorrow<'_, Self>,
+        ptr: u64,
+        cookie: u64,
+        flags: u32,
+        strong: bool,
+        thread: &Thread,
+        wrapper: Option<CritIncrWrapper>,
+    ) -> Result<Result<NodeRef, CouldNotDeliverCriticalIncrement>> {
+        // Try to find an existing node.
+        {
+            let mut inner = self.inner.lock();
+            if let Some(node) = inner.get_existing_node(ptr, cookie)? {
+                return Ok(inner.new_node_ref_with_thread(node, strong, thread, wrapper));
+            }
+        }
+
+        // Allocate the node before reacquiring the lock.
+        let node = DTRWrap::arc_pin_init(Node::new(ptr, cookie, flags, self.into()))?.into_arc();
+        let rbnode = RBTreeNode::new(ptr, node.clone(), GFP_KERNEL)?;
+        let mut inner = self.inner.lock();
+        if let Some(node) = inner.get_existing_node(ptr, cookie)? {
+            return Ok(inner.new_node_ref_with_thread(node, strong, thread, wrapper));
+        }
+
+        inner.nodes.insert(rbnode);
+        // This can only fail if someone has already pushed the node to a list, but we just created
+        // it and still hold the lock, so it can't fail right now.
+        let node_ref = inner
+            .new_node_ref_with_thread(node, strong, thread, wrapper)
+            .unwrap();
+
+        Ok(Ok(node_ref))
+    }
+
+    pub(crate) fn get_node(
+        self: ArcBorrow<'_, Self>,
+        ptr: u64,
+        cookie: u64,
+        flags: u32,
+        strong: bool,
+        thread: &Thread,
+    ) -> Result<NodeRef> {
+        let mut wrapper = None;
+        for _ in 0..2 {
+            match self.get_node_inner(ptr, cookie, flags, strong, thread, wrapper) {
+                Err(err) => return Err(err),
+                Ok(Ok(node_ref)) => return Ok(node_ref),
+                Ok(Err(CouldNotDeliverCriticalIncrement)) => {
+                    wrapper = Some(CritIncrWrapper::new()?);
+                }
+            }
+        }
+        // We only get a `CouldNotDeliverCriticalIncrement` error if `wrapper` is `None`, so the
+        // loop should run at most twice.
+        unreachable!()
+    }
+
+    pub(crate) fn insert_or_update_handle(
+        self: ArcBorrow<'_, Process>,
+        node_ref: NodeRef,
+        is_manager: bool,
+    ) -> Result<u32> {
+        {
+            let mut refs = self.node_refs.lock();
+
+            // Do a lookup before inserting.
+            if let Some(handle_ref) = refs.by_node.get(&node_ref.node.global_id()) {
+                let handle = *handle_ref;
+                let info = refs.by_handle.get_mut(&handle).unwrap();
+                info.node_ref().absorb(node_ref);
+                return Ok(handle);
+            }
+        }
+
+        // Reserve memory for tree nodes.
+        let reserve1 = RBTreeNodeReservation::new(GFP_KERNEL)?;
+        let reserve2 = RBTreeNodeReservation::new(GFP_KERNEL)?;
+        let info = UniqueArc::new_uninit(GFP_KERNEL)?;
+
+        let mut refs_lock = self.node_refs.lock();
+        let mut refs = &mut *refs_lock;
+
+        let (unused_id, by_handle_slot) = loop {
+            // ID 0 may only be used by the manager.
+            let start = if is_manager { 0 } else { 1 };
+
+            if let Some(res) = refs.handle_is_present.find_unused_id(start) {
+                match refs.by_handle.entry(res.as_u32()) {
+                    rbtree::Entry::Vacant(entry) => break (res, entry),
+                    rbtree::Entry::Occupied(_) => {
+                        pr_err!("Detected mismatch between handle_is_present and by_handle");
+                        res.acquire();
+                        kernel::warn_on!(true);
+                        return Err(EINVAL);
+                    }
+                }
+            }
+
+            let grow_request = refs.handle_is_present.grow_request().ok_or(ENOMEM)?;
+            drop(refs_lock);
+            let resizer = grow_request.realloc(GFP_KERNEL)?;
+            refs_lock = self.node_refs.lock();
+            refs = &mut *refs_lock;
+            refs.handle_is_present.grow(resizer);
+        };
+        let handle = unused_id.as_u32();
+
+        // Do a lookup again as node may have been inserted before the lock was reacquired.
+        if let Some(handle_ref) = refs.by_node.get(&node_ref.node.global_id()) {
+            let handle = *handle_ref;
+            let info = refs.by_handle.get_mut(&handle).unwrap();
+            info.node_ref().absorb(node_ref);
+            return Ok(handle);
+        }
+
+        let gid = node_ref.node.global_id();
+        let (info_proc, info_node) = {
+            let info_init = NodeRefInfo::new(node_ref, handle, self.into());
+            match info.pin_init_with(info_init) {
+                Ok(info) => ListArc::pair_from_pin_unique(info),
+                // error is infallible
+                Err(err) => match err {},
+            }
+        };
+
+        // Ensure the process is still alive while we insert a new reference.
+        //
+        // This releases the lock before inserting the nodes, but since `is_dead` is set as the
+        // first thing in `deferred_release`, process cleanup will not miss the items inserted into
+        // `refs` below.
+        if self.inner.lock().is_dead {
+            return Err(ESRCH);
+        }
+
+        // SAFETY: `info_proc` and `info_node` reference the same node, so we are inserting
+        // `info_node` into the right node's `refs` list.
+        unsafe { info_proc.node_ref2().node.insert_node_info(info_node) };
+
+        refs.by_node.insert(reserve1.into_node(gid, handle));
+        by_handle_slot.insert(info_proc, reserve2);
+        unused_id.acquire();
+        Ok(handle)
+    }
+
+    pub(crate) fn get_transaction_node(&self, handle: u32) -> BinderResult<NodeRef> {
+        // When handle is zero, try to get the context manager.
+        if handle == 0 {
+            Ok(self.ctx.get_manager_node(true)?)
+        } else {
+            Ok(self.get_node_from_handle(handle, true)?)
+        }
+    }
+
+    pub(crate) fn get_node_from_handle(&self, handle: u32, strong: bool) -> Result<NodeRef> {
+        self.node_refs
+            .lock()
+            .by_handle
+            .get_mut(&handle)
+            .ok_or(ENOENT)?
+            .node_ref()
+            .clone(strong)
+    }
+
+    pub(crate) fn remove_from_delivered_deaths(&self, death: &DArc<NodeDeath>) {
+        let mut inner = self.inner.lock();
+        // SAFETY: By the invariant on the `delivered_links` field, this is the right linked list.
+        let removed = unsafe { inner.delivered_deaths.remove(death) };
+        drop(inner);
+        drop(removed);
+    }
+
+    pub(crate) fn update_ref(
+        self: ArcBorrow<'_, Process>,
+        handle: u32,
+        inc: bool,
+        strong: bool,
+    ) -> Result {
+        if inc && handle == 0 {
+            if let Ok(node_ref) = self.ctx.get_manager_node(strong) {
+                if core::ptr::eq(&*self, &*node_ref.node.owner) {
+                    return Err(EINVAL);
+                }
+                let _ = self.insert_or_update_handle(node_ref, true);
+                return Ok(());
+            }
+        }
+
+        // To preserve original binder behaviour, we only fail requests where the manager tries to
+        // increment references on itself.
+        let mut refs = self.node_refs.lock();
+        if let Some(info) = refs.by_handle.get_mut(&handle) {
+            if info.node_ref().update(inc, strong) {
+                // Clean up death if there is one attached to this node reference.
+                if let Some(death) = info.death().take() {
+                    death.set_cleared(true);
+                    self.remove_from_delivered_deaths(&death);
+                }
+
+                // Remove reference from process tables, and from the node's `refs` list.
+
+                // SAFETY: We are removing the `NodeRefInfo` from the right node.
+                unsafe { info.node_ref2().node.remove_node_info(info) };
+
+                let id = info.node_ref().node.global_id();
+                refs.by_handle.remove(&handle);
+                refs.by_node.remove(&id);
+                refs.handle_is_present.release_id(handle as usize);
+
+                if let Some(shrink) = refs.handle_is_present.shrink_request() {
+                    drop(refs);
+                    // This intentionally ignores allocation failures.
+                    if let Ok(new_bitmap) = shrink.realloc(GFP_KERNEL) {
+                        refs = self.node_refs.lock();
+                        refs.handle_is_present.shrink(new_bitmap);
+                    }
+                }
+            }
+        } else {
+            // All refs are cleared in process exit, so this warning is expected in that case.
+            if !self.inner.lock().is_dead {
+                pr_warn!("{}: no such ref {handle}\n", self.pid_in_current_ns());
+            }
+        }
+        Ok(())
+    }
+
+    /// Decrements the refcount of the given node, if one exists.
+    pub(crate) fn update_node(&self, ptr: u64, cookie: u64, strong: bool) {
+        let mut inner = self.inner.lock();
+        if let Ok(Some(node)) = inner.get_existing_node(ptr, cookie) {
+            inner.update_node_refcount(&node, false, strong, 1, None);
+        }
+    }
+
+    pub(crate) fn inc_ref_done(&self, reader: &mut UserSliceReader, strong: bool) -> Result {
+        let ptr = reader.read::<u64>()?;
+        let cookie = reader.read::<u64>()?;
+        let mut inner = self.inner.lock();
+        if let Ok(Some(node)) = inner.get_existing_node(ptr, cookie) {
+            if let Some(node) = node.inc_ref_done_locked(strong, &mut inner) {
+                // This only fails if the process is dead.
+                let _ = inner.push_work(node);
+            }
+        }
+        Ok(())
+    }
+
+    pub(crate) fn buffer_alloc(
+        self: &Arc<Self>,
+        debug_id: usize,
+        size: usize,
+        is_oneway: bool,
+        from_pid: i32,
+    ) -> BinderResult<NewAllocation> {
+        use kernel::page::PAGE_SIZE;
+
+        let mut reserve_new_args = ReserveNewArgs {
+            debug_id,
+            size,
+            is_oneway,
+            pid: from_pid,
+            ..ReserveNewArgs::default()
+        };
+
+        let (new_alloc, addr) = loop {
+            let mut inner = self.inner.lock();
+            let mapping = inner.mapping.as_mut().ok_or_else(BinderError::new_dead)?;
+            let alloc_request = match mapping.alloc.reserve_new(reserve_new_args)? {
+                ReserveNew::Success(new_alloc) => break (new_alloc, mapping.address),
+                ReserveNew::NeedAlloc(request) => request,
+            };
+            drop(inner);
+            // We need to allocate memory and then call `reserve_new` again.
+            reserve_new_args = alloc_request.make_alloc()?;
+        };
+
+        let res = Allocation::new(
+            self.clone(),
+            debug_id,
+            new_alloc.offset,
+            size,
+            addr + new_alloc.offset,
+            new_alloc.oneway_spam_detected,
+        );
+
+        // This allocation will be marked as in use until the `Allocation` is used to free it.
+        //
+        // This method can't be called while holding a lock, so we release the lock first. It's
+        // okay for several threads to use the method on the same index at the same time. In that
+        // case, one of the calls will allocate the given page (if missing), and the other call
+        // will wait for the other call to finish allocating the page.
+        //
+        // We will not call `stop_using_range` in parallel with this on the same page, because the
+        // allocation can only be removed via the destructor of the `Allocation` object that we
+        // currently own.
+        match self.pages.use_range(
+            new_alloc.offset / PAGE_SIZE,
+            (new_alloc.offset + size).div_ceil(PAGE_SIZE),
+        ) {
+            Ok(()) => {}
+            Err(err) => {
+                pr_warn!("use_range failure {:?}", err);
+                return Err(err.into());
+            }
+        }
+
+        Ok(NewAllocation(res))
+    }
+
+    pub(crate) fn buffer_get(self: &Arc<Self>, ptr: usize) -> Option<Allocation> {
+        let mut inner = self.inner.lock();
+        let mapping = inner.mapping.as_mut()?;
+        let offset = ptr.checked_sub(mapping.address)?;
+        let (size, debug_id, odata) = mapping.alloc.reserve_existing(offset).ok()?;
+        let mut alloc = Allocation::new(self.clone(), debug_id, offset, size, ptr, false);
+        if let Some(data) = odata {
+            alloc.set_info(data);
+        }
+        Some(alloc)
+    }
+
+    pub(crate) fn buffer_raw_free(&self, ptr: usize) {
+        let mut inner = self.inner.lock();
+        if let Some(ref mut mapping) = &mut inner.mapping {
+            let offset = match ptr.checked_sub(mapping.address) {
+                Some(offset) => offset,
+                None => return,
+            };
+
+            let freed_range = match mapping.alloc.reservation_abort(offset) {
+                Ok(freed_range) => freed_range,
+                Err(_) => {
+                    pr_warn!(
+                        "Pointer {:x} failed to free, base = {:x}\n",
+                        ptr,
+                        mapping.address
+                    );
+                    return;
+                }
+            };
+
+            // No more allocations in this range. Mark them as not in use.
+            //
+            // Must be done before we release the lock so that `use_range` is not used on these
+            // indices until `stop_using_range` returns.
+            self.pages
+                .stop_using_range(freed_range.start_page_idx, freed_range.end_page_idx);
+        }
+    }
+
+    pub(crate) fn buffer_make_freeable(&self, offset: usize, mut data: Option<AllocationInfo>) {
+        let mut inner = self.inner.lock();
+        if let Some(ref mut mapping) = &mut inner.mapping {
+            if mapping.alloc.reservation_commit(offset, &mut data).is_err() {
+                pr_warn!("Offset {} failed to be marked freeable\n", offset);
+            }
+        }
+    }
+
+    fn create_mapping(&self, vma: &mm::virt::VmaNew) -> Result {
+        use kernel::page::PAGE_SIZE;
+        let size = usize::min(vma.end() - vma.start(), bindings::SZ_4M as usize);
+        let mapping = Mapping::new(vma.start(), size);
+        let page_count = self.pages.register_with_vma(vma)?;
+        if page_count * PAGE_SIZE != size {
+            return Err(EINVAL);
+        }
+
+        // Save range allocator for later.
+        self.inner.lock().mapping = Some(mapping);
+
+        Ok(())
+    }
+
+    fn version(&self, data: UserSlice) -> Result {
+        data.writer().write(&BinderVersion::current())
+    }
+
+    pub(crate) fn register_thread(&self) -> bool {
+        self.inner.lock().register_thread()
+    }
+
+    fn remove_thread(&self, thread: Arc<Thread>) {
+        self.inner.lock().threads.remove(&thread.id);
+        thread.release();
+    }
+
+    fn set_max_threads(&self, max: u32) {
+        self.inner.lock().max_threads = max;
+    }
+
+    fn set_oneway_spam_detection_enabled(&self, enabled: u32) {
+        self.inner.lock().oneway_spam_detection_enabled = enabled != 0;
+    }
+
+    pub(crate) fn is_oneway_spam_detection_enabled(&self) -> bool {
+        self.inner.lock().oneway_spam_detection_enabled
+    }
+
+    fn get_node_debug_info(&self, data: UserSlice) -> Result {
+        let (mut reader, mut writer) = data.reader_writer();
+
+        // Read the starting point.
+        let ptr = reader.read::<BinderNodeDebugInfo>()?.ptr;
+        let mut out = BinderNodeDebugInfo::default();
+
+        {
+            let inner = self.inner.lock();
+            for (node_ptr, node) in &inner.nodes {
+                if *node_ptr > ptr {
+                    node.populate_debug_info(&mut out, &inner);
+                    break;
+                }
+            }
+        }
+
+        writer.write(&out)
+    }
+
+    fn get_node_info_from_ref(&self, data: UserSlice) -> Result {
+        let (mut reader, mut writer) = data.reader_writer();
+        let mut out = reader.read::<BinderNodeInfoForRef>()?;
+
+        if out.strong_count != 0
+            || out.weak_count != 0
+            || out.reserved1 != 0
+            || out.reserved2 != 0
+            || out.reserved3 != 0
+        {
+            return Err(EINVAL);
+        }
+
+        // Only the context manager is allowed to use this ioctl.
+        if !self.inner.lock().is_manager {
+            return Err(EPERM);
+        }
+
+        {
+            let mut node_refs = self.node_refs.lock();
+            let node_info = node_refs.by_handle.get_mut(&out.handle).ok_or(ENOENT)?;
+            let node_ref = node_info.node_ref();
+            let owner_inner = node_ref.node.owner.inner.lock();
+            node_ref.node.populate_counts(&mut out, &owner_inner);
+        }
+
+        // Write the result back.
+        writer.write(&out)
+    }
+
+    pub(crate) fn needs_thread(&self) -> bool {
+        let mut inner = self.inner.lock();
+        let ret = inner.requested_thread_count == 0
+            && inner.ready_threads.is_empty()
+            && inner.started_thread_count < inner.max_threads;
+        if ret {
+            inner.requested_thread_count += 1
+        }
+        ret
+    }
+
+    pub(crate) fn request_death(
+        self: &Arc<Self>,
+        reader: &mut UserSliceReader,
+        thread: &Thread,
+    ) -> Result {
+        let handle: u32 = reader.read()?;
+        let cookie: u64 = reader.read()?;
+
+        // Queue BR_ERROR if we can't allocate memory for the death notification.
+        let death = UniqueArc::new_uninit(GFP_KERNEL).inspect_err(|_| {
+            thread.push_return_work(BR_ERROR);
+        })?;
+        let mut refs = self.node_refs.lock();
+        let Some(info) = refs.by_handle.get_mut(&handle) else {
+            pr_warn!("BC_REQUEST_DEATH_NOTIFICATION invalid ref {handle}\n");
+            return Ok(());
+        };
+
+        // Nothing to do if there is already a death notification request for this handle.
+        if info.death().is_some() {
+            pr_warn!("BC_REQUEST_DEATH_NOTIFICATION death notification already set\n");
+            return Ok(());
+        }
+
+        let death = {
+            let death_init = NodeDeath::new(info.node_ref().node.clone(), self.clone(), cookie);
+            match death.pin_init_with(death_init) {
+                Ok(death) => death,
+                // error is infallible
+                Err(err) => match err {},
+            }
+        };
+
+        // Register the death notification.
+        {
+            let owner = info.node_ref2().node.owner.clone();
+            let mut owner_inner = owner.inner.lock();
+            if owner_inner.is_dead {
+                let death = Arc::from(death);
+                *info.death() = Some(death.clone());
+                drop(owner_inner);
+                death.set_dead();
+            } else {
+                let death = ListArc::from(death);
+                *info.death() = Some(death.clone_arc());
+                info.node_ref().node.add_death(death, &mut owner_inner);
+            }
+        }
+        Ok(())
+    }
+
+    pub(crate) fn clear_death(&self, reader: &mut UserSliceReader, thread: &Thread) -> Result {
+        let handle: u32 = reader.read()?;
+        let cookie: u64 = reader.read()?;
+
+        let mut refs = self.node_refs.lock();
+        let Some(info) = refs.by_handle.get_mut(&handle) else {
+            pr_warn!("BC_CLEAR_DEATH_NOTIFICATION invalid ref {handle}\n");
+            return Ok(());
+        };
+
+        let Some(death) = info.death().take() else {
+            pr_warn!("BC_CLEAR_DEATH_NOTIFICATION death notification not active\n");
+            return Ok(());
+        };
+        if death.cookie != cookie {
+            *info.death() = Some(death);
+            pr_warn!("BC_CLEAR_DEATH_NOTIFICATION death notification cookie mismatch\n");
+            return Ok(());
+        }
+
+        // Update state and determine if we need to queue a work item. We only need to do it when
+        // the node is not dead or if the user already completed the death notification.
+        if death.set_cleared(false) {
+            if let Some(death) = ListArc::try_from_arc_or_drop(death) {
+                let _ = thread.push_work_if_looper(death);
+            }
+        }
+
+        Ok(())
+    }
+
+    pub(crate) fn dead_binder_done(&self, cookie: u64, thread: &Thread) {
+        if let Some(death) = self.inner.lock().pull_delivered_death(cookie) {
+            death.set_notification_done(thread);
+        }
+    }
+
+    /// Locks the spinlock and move the `nodes` rbtree out.
+    ///
+    /// This allows you to iterate through `nodes` while also allowing you to give other parts of
+    /// the codebase exclusive access to `ProcessInner`.
+    pub(crate) fn lock_with_nodes(&self) -> WithNodes<'_> {
+        let mut inner = self.inner.lock();
+        WithNodes {
+            nodes: take(&mut inner.nodes),
+            inner,
+        }
+    }
+
+    fn deferred_flush(&self) {
+        let inner = self.inner.lock();
+        for thread in inner.threads.values() {
+            thread.exit_looper();
+        }
+    }
+
+    fn deferred_release(self: Arc<Self>) {
+        let is_manager = {
+            let mut inner = self.inner.lock();
+            inner.is_dead = true;
+            inner.is_frozen = IsFrozen::No;
+            inner.sync_recv = false;
+            inner.async_recv = false;
+            inner.is_manager
+        };
+
+        if is_manager {
+            self.ctx.unset_manager_node();
+        }
+
+        self.ctx.deregister_process(&self);
+
+        let binderfs_file = self.inner.lock().binderfs_file.take();
+        drop(binderfs_file);
+
+        // Release threads.
+        let threads = {
+            let mut inner = self.inner.lock();
+            let threads = take(&mut inner.threads);
+            let ready = take(&mut inner.ready_threads);
+            drop(inner);
+            drop(ready);
+
+            for thread in threads.values() {
+                thread.release();
+            }
+            threads
+        };
+
+        // Release nodes.
+        {
+            while let Some(node) = {
+                let mut lock = self.inner.lock();
+                lock.nodes.cursor_front_mut().map(|c| c.remove_current().1)
+            } {
+                node.to_key_value().1.release();
+            }
+        }
+
+        // Clean up death listeners and remove nodes from external node info lists.
+        for info in self.node_refs.lock().by_handle.values_mut() {
+            // SAFETY: We are removing the `NodeRefInfo` from the right node.
+            unsafe { info.node_ref2().node.remove_node_info(info) };
+
+            // Remove all death notifications from the nodes (that belong to a different process).
+            let death = if let Some(existing) = info.death().take() {
+                existing
+            } else {
+                continue;
+            };
+            death.set_cleared(false);
+        }
+
+        // Clean up freeze listeners.
+        let freeze_listeners = take(&mut self.node_refs.lock().freeze_listeners);
+        for listener in freeze_listeners.values() {
+            listener.on_process_exit(&self);
+        }
+        drop(freeze_listeners);
+
+        // Release refs on foreign nodes.
+        {
+            let mut refs = self.node_refs.lock();
+            let by_handle = take(&mut refs.by_handle);
+            let by_node = take(&mut refs.by_node);
+            drop(refs);
+            drop(by_node);
+            drop(by_handle);
+        }
+
+        // Cancel all pending work items.
+        while let Some(work) = self.get_work() {
+            work.into_arc().cancel();
+        }
+
+        // Clear delivered_deaths list.
+        //
+        // Scope ensures that MutexGuard is dropped while executing the body.
+        while let Some(delivered_death) = { self.inner.lock().delivered_deaths.pop_front() } {
+            drop(delivered_death);
+        }
+
+        // Free any resources kept alive by allocated buffers.
+        let omapping = self.inner.lock().mapping.take();
+        if let Some(mut mapping) = omapping {
+            let address = mapping.address;
+            mapping
+                .alloc
+                .take_for_each(|offset, size, debug_id, odata| {
+                    let ptr = offset + address;
+                    let mut alloc =
+                        Allocation::new(self.clone(), debug_id, offset, size, ptr, false);
+                    if let Some(data) = odata {
+                        alloc.set_info(data);
+                    }
+                    drop(alloc)
+                });
+        }
+
+        // calls to synchronize_rcu() in thread drop will happen here
+        drop(threads);
+    }
+
+    pub(crate) fn drop_outstanding_txn(&self) {
+        let wake = {
+            let mut inner = self.inner.lock();
+            if inner.outstanding_txns == 0 {
+                pr_err!("outstanding_txns underflow");
+                return;
+            }
+            inner.outstanding_txns -= 1;
+            inner.is_frozen.is_frozen() && inner.outstanding_txns == 0
+        };
+
+        if wake {
+            self.freeze_wait.notify_all();
+        }
+    }
+
+    pub(crate) fn ioctl_freeze(&self, info: &BinderFreezeInfo) -> Result {
+        if info.enable == 0 {
+            let msgs = self.prepare_freeze_messages()?;
+            let mut inner = self.inner.lock();
+            inner.sync_recv = false;
+            inner.async_recv = false;
+            inner.is_frozen = IsFrozen::No;
+            drop(inner);
+            msgs.send_messages();
+            return Ok(());
+        }
+
+        let mut inner = self.inner.lock();
+        inner.sync_recv = false;
+        inner.async_recv = false;
+        inner.is_frozen = IsFrozen::InProgress;
+
+        if info.timeout_ms > 0 {
+            let mut jiffies = kernel::time::msecs_to_jiffies(info.timeout_ms);
+            while jiffies > 0 {
+                if inner.outstanding_txns == 0 {
+                    break;
+                }
+
+                match self
+                    .freeze_wait
+                    .wait_interruptible_timeout(&mut inner, jiffies)
+                {
+                    CondVarTimeoutResult::Signal { .. } => {
+                        inner.is_frozen = IsFrozen::No;
+                        return Err(ERESTARTSYS);
+                    }
+                    CondVarTimeoutResult::Woken { jiffies: remaining } => {
+                        jiffies = remaining;
+                    }
+                    CondVarTimeoutResult::Timeout => {
+                        jiffies = 0;
+                    }
+                }
+            }
+        }
+
+        if inner.txns_pending_locked() {
+            inner.is_frozen = IsFrozen::No;
+            Err(EAGAIN)
+        } else {
+            drop(inner);
+            match self.prepare_freeze_messages() {
+                Ok(batch) => {
+                    self.inner.lock().is_frozen = IsFrozen::Yes;
+                    batch.send_messages();
+                    Ok(())
+                }
+                Err(kernel::alloc::AllocError) => {
+                    self.inner.lock().is_frozen = IsFrozen::No;
+                    Err(ENOMEM)
+                }
+            }
+        }
+    }
+}
+
+fn get_frozen_status(data: UserSlice) -> Result {
+    let (mut reader, mut writer) = data.reader_writer();
+
+    let mut info = reader.read::<BinderFrozenStatusInfo>()?;
+    info.sync_recv = 0;
+    info.async_recv = 0;
+    let mut found = false;
+
+    for ctx in crate::context::get_all_contexts()? {
+        ctx.for_each_proc(|proc| {
+            if proc.task.pid() == info.pid as _ {
+                found = true;
+                let inner = proc.inner.lock();
+                let txns_pending = inner.txns_pending_locked();
+                info.async_recv |= inner.async_recv as u32;
+                info.sync_recv |= inner.sync_recv as u32;
+                info.sync_recv |= (txns_pending as u32) << 1;
+            }
+        });
+    }
+
+    if found {
+        writer.write(&info)?;
+        Ok(())
+    } else {
+        Err(EINVAL)
+    }
+}
+
+fn ioctl_freeze(reader: &mut UserSliceReader) -> Result {
+    let info = reader.read::<BinderFreezeInfo>()?;
+
+    // Very unlikely for there to be more than 3, since a process normally uses at most binder and
+    // hwbinder.
+    let mut procs = KVec::with_capacity(3, GFP_KERNEL)?;
+
+    let ctxs = crate::context::get_all_contexts()?;
+    for ctx in ctxs {
+        for proc in ctx.get_procs_with_pid(info.pid as i32)? {
+            procs.push(proc, GFP_KERNEL)?;
+        }
+    }
+
+    for proc in procs {
+        proc.ioctl_freeze(&info)?;
+    }
+    Ok(())
+}
+
+/// The ioctl handler.
+impl Process {
+    /// Ioctls that are write-only from the perspective of userspace.
+    ///
+    /// The kernel will only read from the pointer that userspace provided to us.
+    fn ioctl_write_only(
+        this: ArcBorrow<'_, Process>,
+        _file: &File,
+        cmd: u32,
+        reader: &mut UserSliceReader,
+    ) -> Result {
+        let thread = this.get_current_thread()?;
+        match cmd {
+            uapi::BINDER_SET_MAX_THREADS => this.set_max_threads(reader.read()?),
+            uapi::BINDER_THREAD_EXIT => this.remove_thread(thread),
+            uapi::BINDER_SET_CONTEXT_MGR => this.set_as_manager(None, &thread)?,
+            uapi::BINDER_SET_CONTEXT_MGR_EXT => {
+                this.set_as_manager(Some(reader.read()?), &thread)?
+            }
+            uapi::BINDER_ENABLE_ONEWAY_SPAM_DETECTION => {
+                this.set_oneway_spam_detection_enabled(reader.read()?)
+            }
+            uapi::BINDER_FREEZE => ioctl_freeze(reader)?,
+            _ => return Err(EINVAL),
+        }
+        Ok(())
+    }
+
+    /// Ioctls that are read/write from the perspective of userspace.
+    ///
+    /// The kernel will both read from and write to the pointer that userspace provided to us.
+    fn ioctl_write_read(
+        this: ArcBorrow<'_, Process>,
+        file: &File,
+        cmd: u32,
+        data: UserSlice,
+    ) -> Result {
+        let thread = this.get_current_thread()?;
+        let blocking = (file.flags() & file::flags::O_NONBLOCK) == 0;
+        match cmd {
+            uapi::BINDER_WRITE_READ => thread.write_read(data, blocking)?,
+            uapi::BINDER_GET_NODE_DEBUG_INFO => this.get_node_debug_info(data)?,
+            uapi::BINDER_GET_NODE_INFO_FOR_REF => this.get_node_info_from_ref(data)?,
+            uapi::BINDER_VERSION => this.version(data)?,
+            uapi::BINDER_GET_FROZEN_INFO => get_frozen_status(data)?,
+            uapi::BINDER_GET_EXTENDED_ERROR => thread.get_extended_error(data)?,
+            _ => return Err(EINVAL),
+        }
+        Ok(())
+    }
+}
+
+/// The file operations supported by `Process`.
+impl Process {
+    pub(crate) fn open(ctx: ArcBorrow<'_, Context>, file: &File) -> Result<Arc<Process>> {
+        Self::new(ctx.into(), ARef::from(file.cred()))
+    }
+
+    pub(crate) fn release(this: Arc<Process>, _file: &File) {
+        let binderfs_file;
+        let should_schedule;
+        {
+            let mut inner = this.inner.lock();
+            should_schedule = inner.defer_work == 0;
+            inner.defer_work |= PROC_DEFER_RELEASE;
+            binderfs_file = inner.binderfs_file.take();
+        }
+
+        if should_schedule {
+            // Ignore failures to schedule to the workqueue. Those just mean that we're already
+            // scheduled for execution.
+            let _ = workqueue::system().enqueue(this);
+        }
+
+        drop(binderfs_file);
+    }
+
+    pub(crate) fn flush(this: ArcBorrow<'_, Process>) -> Result {
+        let should_schedule;
+        {
+            let mut inner = this.inner.lock();
+            should_schedule = inner.defer_work == 0;
+            inner.defer_work |= PROC_DEFER_FLUSH;
+        }
+
+        if should_schedule {
+            // Ignore failures to schedule to the workqueue. Those just mean that we're already
+            // scheduled for execution.
+            let _ = workqueue::system().enqueue(Arc::from(this));
+        }
+        Ok(())
+    }
+
+    pub(crate) fn ioctl(this: ArcBorrow<'_, Process>, file: &File, cmd: u32, arg: usize) -> Result {
+        use kernel::ioctl::{_IOC_DIR, _IOC_SIZE};
+        use kernel::uapi::{_IOC_READ, _IOC_WRITE};
+
+        crate::trace::trace_ioctl(cmd, arg);
+
+        let user_slice = UserSlice::new(UserPtr::from_addr(arg), _IOC_SIZE(cmd));
+
+        const _IOC_READ_WRITE: u32 = _IOC_READ | _IOC_WRITE;
+
+        match _IOC_DIR(cmd) {
+            _IOC_WRITE => Self::ioctl_write_only(this, file, cmd, &mut user_slice.reader()),
+            _IOC_READ_WRITE => Self::ioctl_write_read(this, file, cmd, user_slice),
+            _ => Err(EINVAL),
+        }
+    }
+
+    pub(crate) fn mmap(
+        this: ArcBorrow<'_, Process>,
+        _file: &File,
+        vma: &mm::virt::VmaNew,
+    ) -> Result {
+        // We don't allow mmap to be used in a different process.
+        if !core::ptr::eq(kernel::current!().group_leader(), &*this.task) {
+            return Err(EINVAL);
+        }
+        if vma.start() == 0 {
+            return Err(EINVAL);
+        }
+
+        vma.try_clear_maywrite().map_err(|_| EPERM)?;
+        vma.set_dontcopy();
+        vma.set_mixedmap();
+
+        // TODO: Set ops. We need to learn when the user unmaps so that we can stop using it.
+        this.create_mapping(vma)
+    }
+
+    pub(crate) fn poll(
+        this: ArcBorrow<'_, Process>,
+        file: &File,
+        table: PollTable<'_>,
+    ) -> Result<u32> {
+        let thread = this.get_current_thread()?;
+        let (from_proc, mut mask) = thread.poll(file, table);
+        if mask == 0 && from_proc && !this.inner.lock().work.is_empty() {
+            mask |= bindings::POLLIN;
+        }
+        Ok(mask)
+    }
+}
+
+/// Represents that a thread has registered with the `ready_threads` list of its process.
+///
+/// The destructor of this type will unregister the thread from the list of ready threads.
+pub(crate) struct Registration<'a> {
+    thread: &'a Arc<Thread>,
+}
+
+impl<'a> Registration<'a> {
+    fn new(thread: &'a Arc<Thread>, guard: &mut Guard<'_, ProcessInner, SpinLockBackend>) -> Self {
+        assert!(core::ptr::eq(&thread.process.inner, guard.lock_ref()));
+        // INVARIANT: We are pushing this thread to the right `ready_threads` list.
+        if let Ok(list_arc) = ListArc::try_from_arc(thread.clone()) {
+            guard.ready_threads.push_front(list_arc);
+        } else {
+            // It is an error to hit this branch, and it should not be reachable. We try to do
+            // something reasonable when the failure path happens. Most likely, the thread in
+            // question will sleep forever.
+            pr_err!("Same thread registered with `ready_threads` twice.");
+        }
+        Self { thread }
+    }
+}
+
+impl Drop for Registration<'_> {
+    fn drop(&mut self) {
+        let mut inner = self.thread.process.inner.lock();
+        // SAFETY: The thread has the invariant that we never push it to any other linked list than
+        // the `ready_threads` list of its parent process. Therefore, the thread is either in that
+        // list, or in no list.
+        unsafe { inner.ready_threads.remove(self.thread) };
+    }
+}
+
+pub(crate) struct WithNodes<'a> {
+    pub(crate) inner: Guard<'a, ProcessInner, SpinLockBackend>,
+    pub(crate) nodes: RBTree<u64, DArc<Node>>,
+}
+
+impl Drop for WithNodes<'_> {
+    fn drop(&mut self) {
+        core::mem::swap(&mut self.nodes, &mut self.inner.nodes);
+        if self.nodes.iter().next().is_some() {
+            pr_err!("nodes array was modified while using lock_with_nodes\n");
+        }
+    }
+}
+
+pub(crate) enum GetWorkOrRegister<'a> {
+    Work(DLArc<dyn DeliverToRead>),
+    Register(Registration<'a>),
+}
diff --git a/drivers/android/binder/range_alloc/array.rs b/drivers/android/binder/range_alloc/array.rs
new file mode 100644
index 000000000000..07e1dec2ce63
--- /dev/null
+++ b/drivers/android/binder/range_alloc/array.rs
@@ -0,0 +1,251 @@
+// SPDX-License-Identifier: GPL-2.0
+
+// Copyright (C) 2025 Google LLC.
+
+use kernel::{
+    page::{PAGE_MASK, PAGE_SIZE},
+    prelude::*,
+    seq_file::SeqFile,
+    seq_print,
+    task::Pid,
+};
+
+use crate::range_alloc::{DescriptorState, FreedRange, Range};
+
+/// Keeps track of allocations in a process' mmap.
+///
+/// Each process has an mmap where the data for incoming transactions will be placed. This struct
+/// keeps track of allocations made in the mmap. For each allocation, we store a descriptor that
+/// has metadata related to the allocation. We also keep track of available free space.
+pub(super) struct ArrayRangeAllocator<T> {
+    /// This stores all ranges that are allocated. Unlike the tree based allocator, we do *not*
+    /// store the free ranges.
+    ///
+    /// Sorted by offset.
+    pub(super) ranges: KVec<Range<T>>,
+    size: usize,
+    free_oneway_space: usize,
+}
+
+struct FindEmptyRes {
+    /// Which index in `ranges` should we insert the new range at?
+    ///
+    /// Inserting the new range at this index keeps `ranges` sorted.
+    insert_at_idx: usize,
+    /// Which offset should we insert the new range at?
+    insert_at_offset: usize,
+}
+
+impl<T> ArrayRangeAllocator<T> {
+    pub(crate) fn new(size: usize, alloc: EmptyArrayAlloc<T>) -> Self {
+        Self {
+            ranges: alloc.ranges,
+            size,
+            free_oneway_space: size / 2,
+        }
+    }
+
+    pub(crate) fn free_oneway_space(&self) -> usize {
+        self.free_oneway_space
+    }
+
+    pub(crate) fn count_buffers(&self) -> usize {
+        self.ranges.len()
+    }
+
+    pub(crate) fn total_size(&self) -> usize {
+        self.size
+    }
+
+    pub(crate) fn is_full(&self) -> bool {
+        self.ranges.len() == self.ranges.capacity()
+    }
+
+    pub(crate) fn debug_print(&self, m: &SeqFile) -> Result<()> {
+        for range in &self.ranges {
+            seq_print!(
+                m,
+                "  buffer {}: {} size {} pid {} oneway {}",
+                0,
+                range.offset,
+                range.size,
+                range.state.pid(),
+                range.state.is_oneway(),
+            );
+            if let DescriptorState::Reserved(_) = range.state {
+                seq_print!(m, " reserved\n");
+            } else {
+                seq_print!(m, " allocated\n");
+            }
+        }
+        Ok(())
+    }
+
+    /// Find somewhere to put a new range.
+    ///
+    /// Unlike the tree implementation, we do not bother to find the smallest gap. The idea is that
+    /// fragmentation isn't a big issue when we don't have many ranges.
+    ///
+    /// Returns the index that the new range should have in `self.ranges` after insertion.
+    fn find_empty_range(&self, size: usize) -> Option<FindEmptyRes> {
+        let after_last_range = self.ranges.last().map(Range::endpoint).unwrap_or(0);
+
+        if size <= self.total_size() - after_last_range {
+            // We can put the range at the end, so just do that.
+            Some(FindEmptyRes {
+                insert_at_idx: self.ranges.len(),
+                insert_at_offset: after_last_range,
+            })
+        } else {
+            let mut end_of_prev = 0;
+            for (i, range) in self.ranges.iter().enumerate() {
+                // Does it fit before the i'th range?
+                if size <= range.offset - end_of_prev {
+                    return Some(FindEmptyRes {
+                        insert_at_idx: i,
+                        insert_at_offset: end_of_prev,
+                    });
+                }
+                end_of_prev = range.endpoint();
+            }
+            None
+        }
+    }
+
+    pub(crate) fn reserve_new(
+        &mut self,
+        debug_id: usize,
+        size: usize,
+        is_oneway: bool,
+        pid: Pid,
+    ) -> Result<usize> {
+        // Compute new value of free_oneway_space, which is set only on success.
+        let new_oneway_space = if is_oneway {
+            match self.free_oneway_space.checked_sub(size) {
+                Some(new_oneway_space) => new_oneway_space,
+                None => return Err(ENOSPC),
+            }
+        } else {
+            self.free_oneway_space
+        };
+
+        let FindEmptyRes {
+            insert_at_idx,
+            insert_at_offset,
+        } = self.find_empty_range(size).ok_or(ENOSPC)?;
+        self.free_oneway_space = new_oneway_space;
+
+        let new_range = Range {
+            offset: insert_at_offset,
+            size,
+            state: DescriptorState::new(is_oneway, debug_id, pid),
+        };
+        // Insert the value at the given index to keep the array sorted.
+        self.ranges
+            .insert_within_capacity(insert_at_idx, new_range)
+            .ok()
+            .unwrap();
+
+        Ok(insert_at_offset)
+    }
+
+    pub(crate) fn reservation_abort(&mut self, offset: usize) -> Result<FreedRange> {
+        // This could use a binary search, but linear scans are usually faster for small arrays.
+        let i = self
+            .ranges
+            .iter()
+            .position(|range| range.offset == offset)
+            .ok_or(EINVAL)?;
+        let range = &self.ranges[i];
+
+        if let DescriptorState::Allocated(_) = range.state {
+            return Err(EPERM);
+        }
+
+        let size = range.size;
+        let offset = range.offset;
+
+        if range.state.is_oneway() {
+            self.free_oneway_space += size;
+        }
+
+        // This computes the range of pages that are no longer used by *any* allocated range. The
+        // caller will mark them as unused, which means that they can be freed if the system comes
+        // under memory pressure.
+        let mut freed_range = FreedRange::interior_pages(offset, size);
+        #[expect(clippy::collapsible_if)] // reads better like this
+        if offset % PAGE_SIZE != 0 {
+            if i == 0 || self.ranges[i - 1].endpoint() <= (offset & PAGE_MASK) {
+                freed_range.start_page_idx -= 1;
+            }
+        }
+        if range.endpoint() % PAGE_SIZE != 0 {
+            let page_after = (range.endpoint() & PAGE_MASK) + PAGE_SIZE;
+            if i + 1 == self.ranges.len() || page_after <= self.ranges[i + 1].offset {
+                freed_range.end_page_idx += 1;
+            }
+        }
+
+        self.ranges.remove(i)?;
+        Ok(freed_range)
+    }
+
+    pub(crate) fn reservation_commit(&mut self, offset: usize, data: &mut Option<T>) -> Result {
+        // This could use a binary search, but linear scans are usually faster for small arrays.
+        let range = self
+            .ranges
+            .iter_mut()
+            .find(|range| range.offset == offset)
+            .ok_or(ENOENT)?;
+
+        let DescriptorState::Reserved(reservation) = &range.state else {
+            return Err(ENOENT);
+        };
+
+        range.state = DescriptorState::Allocated(reservation.clone().allocate(data.take()));
+        Ok(())
+    }
+
+    pub(crate) fn reserve_existing(&mut self, offset: usize) -> Result<(usize, usize, Option<T>)> {
+        // This could use a binary search, but linear scans are usually faster for small arrays.
+        let range = self
+            .ranges
+            .iter_mut()
+            .find(|range| range.offset == offset)
+            .ok_or(ENOENT)?;
+
+        let DescriptorState::Allocated(allocation) = &mut range.state else {
+            return Err(ENOENT);
+        };
+
+        let data = allocation.take();
+        let debug_id = allocation.reservation.debug_id;
+        range.state = DescriptorState::Reserved(allocation.reservation.clone());
+        Ok((range.size, debug_id, data))
+    }
+
+    pub(crate) fn take_for_each<F: Fn(usize, usize, usize, Option<T>)>(&mut self, callback: F) {
+        for range in self.ranges.iter_mut() {
+            if let DescriptorState::Allocated(allocation) = &mut range.state {
+                callback(
+                    range.offset,
+                    range.size,
+                    allocation.reservation.debug_id,
+                    allocation.data.take(),
+                );
+            }
+        }
+    }
+}
+
+pub(crate) struct EmptyArrayAlloc<T> {
+    ranges: KVec<Range<T>>,
+}
+
+impl<T> EmptyArrayAlloc<T> {
+    pub(crate) fn try_new(capacity: usize) -> Result<Self> {
+        Ok(Self {
+            ranges: KVec::with_capacity(capacity, GFP_KERNEL)?,
+        })
+    }
+}
diff --git a/drivers/android/binder/range_alloc/mod.rs b/drivers/android/binder/range_alloc/mod.rs
new file mode 100644
index 000000000000..2301e2bc1a1f
--- /dev/null
+++ b/drivers/android/binder/range_alloc/mod.rs
@@ -0,0 +1,329 @@
+// SPDX-License-Identifier: GPL-2.0
+
+// Copyright (C) 2025 Google LLC.
+
+use kernel::{page::PAGE_SIZE, prelude::*, seq_file::SeqFile, task::Pid};
+
+mod tree;
+use self::tree::{FromArrayAllocs, ReserveNewTreeAlloc, TreeRangeAllocator};
+
+mod array;
+use self::array::{ArrayRangeAllocator, EmptyArrayAlloc};
+
+enum DescriptorState<T> {
+    Reserved(Reservation),
+    Allocated(Allocation<T>),
+}
+
+impl<T> DescriptorState<T> {
+    fn new(is_oneway: bool, debug_id: usize, pid: Pid) -> Self {
+        DescriptorState::Reserved(Reservation {
+            debug_id,
+            is_oneway,
+            pid,
+        })
+    }
+
+    fn pid(&self) -> Pid {
+        match self {
+            DescriptorState::Reserved(inner) => inner.pid,
+            DescriptorState::Allocated(inner) => inner.reservation.pid,
+        }
+    }
+
+    fn is_oneway(&self) -> bool {
+        match self {
+            DescriptorState::Reserved(inner) => inner.is_oneway,
+            DescriptorState::Allocated(inner) => inner.reservation.is_oneway,
+        }
+    }
+}
+
+#[derive(Clone)]
+struct Reservation {
+    debug_id: usize,
+    is_oneway: bool,
+    pid: Pid,
+}
+
+impl Reservation {
+    fn allocate<T>(self, data: Option<T>) -> Allocation<T> {
+        Allocation {
+            data,
+            reservation: self,
+        }
+    }
+}
+
+struct Allocation<T> {
+    reservation: Reservation,
+    data: Option<T>,
+}
+
+impl<T> Allocation<T> {
+    fn deallocate(self) -> (Reservation, Option<T>) {
+        (self.reservation, self.data)
+    }
+
+    fn debug_id(&self) -> usize {
+        self.reservation.debug_id
+    }
+
+    fn take(&mut self) -> Option<T> {
+        self.data.take()
+    }
+}
+
+/// The array implementation must switch to the tree if it wants to go beyond this number of
+/// ranges.
+const TREE_THRESHOLD: usize = 8;
+
+/// Represents a range of pages that have just become completely free.
+#[derive(Copy, Clone)]
+pub(crate) struct FreedRange {
+    pub(crate) start_page_idx: usize,
+    pub(crate) end_page_idx: usize,
+}
+
+impl FreedRange {
+    fn interior_pages(offset: usize, size: usize) -> FreedRange {
+        FreedRange {
+            // Divide round up
+            start_page_idx: offset.div_ceil(PAGE_SIZE),
+            // Divide round down
+            end_page_idx: (offset + size) / PAGE_SIZE,
+        }
+    }
+}
+
+struct Range<T> {
+    offset: usize,
+    size: usize,
+    state: DescriptorState<T>,
+}
+
+impl<T> Range<T> {
+    fn endpoint(&self) -> usize {
+        self.offset + self.size
+    }
+}
+
+pub(crate) struct RangeAllocator<T> {
+    inner: Impl<T>,
+}
+
+enum Impl<T> {
+    Empty(usize),
+    Array(ArrayRangeAllocator<T>),
+    Tree(TreeRangeAllocator<T>),
+}
+
+impl<T> RangeAllocator<T> {
+    pub(crate) fn new(size: usize) -> Self {
+        Self {
+            inner: Impl::Empty(size),
+        }
+    }
+
+    pub(crate) fn free_oneway_space(&self) -> usize {
+        match &self.inner {
+            Impl::Empty(size) => size / 2,
+            Impl::Array(array) => array.free_oneway_space(),
+            Impl::Tree(tree) => tree.free_oneway_space(),
+        }
+    }
+
+    pub(crate) fn count_buffers(&self) -> usize {
+        match &self.inner {
+            Impl::Empty(_size) => 0,
+            Impl::Array(array) => array.count_buffers(),
+            Impl::Tree(tree) => tree.count_buffers(),
+        }
+    }
+
+    pub(crate) fn debug_print(&self, m: &SeqFile) -> Result<()> {
+        match &self.inner {
+            Impl::Empty(_size) => Ok(()),
+            Impl::Array(array) => array.debug_print(m),
+            Impl::Tree(tree) => tree.debug_print(m),
+        }
+    }
+
+    /// Try to reserve a new buffer, using the provided allocation if necessary.
+    pub(crate) fn reserve_new(&mut self, mut args: ReserveNewArgs<T>) -> Result<ReserveNew<T>> {
+        match &mut self.inner {
+            Impl::Empty(size) => {
+                let empty_array = match args.empty_array_alloc.take() {
+                    Some(empty_array) => ArrayRangeAllocator::new(*size, empty_array),
+                    None => {
+                        return Ok(ReserveNew::NeedAlloc(ReserveNewNeedAlloc {
+                            args,
+                            need_empty_array_alloc: true,
+                            need_new_tree_alloc: false,
+                            need_tree_alloc: false,
+                        }))
+                    }
+                };
+
+                self.inner = Impl::Array(empty_array);
+                self.reserve_new(args)
+            }
+            Impl::Array(array) if array.is_full() => {
+                let allocs = match args.new_tree_alloc {
+                    Some(ref mut allocs) => allocs,
+                    None => {
+                        return Ok(ReserveNew::NeedAlloc(ReserveNewNeedAlloc {
+                            args,
+                            need_empty_array_alloc: false,
+                            need_new_tree_alloc: true,
+                            need_tree_alloc: true,
+                        }))
+                    }
+                };
+
+                let new_tree =
+                    TreeRangeAllocator::from_array(array.total_size(), &mut array.ranges, allocs);
+
+                self.inner = Impl::Tree(new_tree);
+                self.reserve_new(args)
+            }
+            Impl::Array(array) => {
+                let offset =
+                    array.reserve_new(args.debug_id, args.size, args.is_oneway, args.pid)?;
+                Ok(ReserveNew::Success(ReserveNewSuccess {
+                    offset,
+                    oneway_spam_detected: false,
+                    _empty_array_alloc: args.empty_array_alloc,
+                    _new_tree_alloc: args.new_tree_alloc,
+                    _tree_alloc: args.tree_alloc,
+                }))
+            }
+            Impl::Tree(tree) => {
+                let alloc = match args.tree_alloc {
+                    Some(alloc) => alloc,
+                    None => {
+                        return Ok(ReserveNew::NeedAlloc(ReserveNewNeedAlloc {
+                            args,
+                            need_empty_array_alloc: false,
+                            need_new_tree_alloc: false,
+                            need_tree_alloc: true,
+                        }));
+                    }
+                };
+                let (offset, oneway_spam_detected) =
+                    tree.reserve_new(args.debug_id, args.size, args.is_oneway, args.pid, alloc)?;
+                Ok(ReserveNew::Success(ReserveNewSuccess {
+                    offset,
+                    oneway_spam_detected,
+                    _empty_array_alloc: args.empty_array_alloc,
+                    _new_tree_alloc: args.new_tree_alloc,
+                    _tree_alloc: None,
+                }))
+            }
+        }
+    }
+
+    /// Deletes the allocations at `offset`.
+    pub(crate) fn reservation_abort(&mut self, offset: usize) -> Result<FreedRange> {
+        match &mut self.inner {
+            Impl::Empty(_size) => Err(EINVAL),
+            Impl::Array(array) => array.reservation_abort(offset),
+            Impl::Tree(tree) => {
+                let freed_range = tree.reservation_abort(offset)?;
+                if tree.is_empty() {
+                    self.inner = Impl::Empty(tree.total_size());
+                }
+                Ok(freed_range)
+            }
+        }
+    }
+
+    /// Called when an allocation is no longer in use by the kernel.
+    ///
+    /// The value in `data` will be stored, if any. A mutable reference is used to avoid dropping
+    /// the `T` when an error is returned.
+    pub(crate) fn reservation_commit(&mut self, offset: usize, data: &mut Option<T>) -> Result {
+        match &mut self.inner {
+            Impl::Empty(_size) => Err(EINVAL),
+            Impl::Array(array) => array.reservation_commit(offset, data),
+            Impl::Tree(tree) => tree.reservation_commit(offset, data),
+        }
+    }
+
+    /// Called when the kernel starts using an allocation.
+    ///
+    /// Returns the size of the existing entry and the data associated with it.
+    pub(crate) fn reserve_existing(&mut self, offset: usize) -> Result<(usize, usize, Option<T>)> {
+        match &mut self.inner {
+            Impl::Empty(_size) => Err(EINVAL),
+            Impl::Array(array) => array.reserve_existing(offset),
+            Impl::Tree(tree) => tree.reserve_existing(offset),
+        }
+    }
+
+    /// Call the provided callback at every allocated region.
+    ///
+    /// This destroys the range allocator. Used only during shutdown.
+    pub(crate) fn take_for_each<F: Fn(usize, usize, usize, Option<T>)>(&mut self, callback: F) {
+        match &mut self.inner {
+            Impl::Empty(_size) => {}
+            Impl::Array(array) => array.take_for_each(callback),
+            Impl::Tree(tree) => tree.take_for_each(callback),
+        }
+    }
+}
+
+/// The arguments for `reserve_new`.
+#[derive(Default)]
+pub(crate) struct ReserveNewArgs<T> {
+    pub(crate) size: usize,
+    pub(crate) is_oneway: bool,
+    pub(crate) debug_id: usize,
+    pub(crate) pid: Pid,
+    pub(crate) empty_array_alloc: Option<EmptyArrayAlloc<T>>,
+    pub(crate) new_tree_alloc: Option<FromArrayAllocs<T>>,
+    pub(crate) tree_alloc: Option<ReserveNewTreeAlloc<T>>,
+}
+
+/// The return type of `ReserveNew`.
+pub(crate) enum ReserveNew<T> {
+    Success(ReserveNewSuccess<T>),
+    NeedAlloc(ReserveNewNeedAlloc<T>),
+}
+
+/// Returned by `reserve_new` when the reservation was successul.
+pub(crate) struct ReserveNewSuccess<T> {
+    pub(crate) offset: usize,
+    pub(crate) oneway_spam_detected: bool,
+
+    // If the user supplied an allocation that we did not end up using, then we return it here.
+    // The caller will kfree it outside of the lock.
+    _empty_array_alloc: Option<EmptyArrayAlloc<T>>,
+    _new_tree_alloc: Option<FromArrayAllocs<T>>,
+    _tree_alloc: Option<ReserveNewTreeAlloc<T>>,
+}
+
+/// Returned by `reserve_new` to request the caller to make an allocation before calling the method
+/// again.
+pub(crate) struct ReserveNewNeedAlloc<T> {
+    args: ReserveNewArgs<T>,
+    need_empty_array_alloc: bool,
+    need_new_tree_alloc: bool,
+    need_tree_alloc: bool,
+}
+
+impl<T> ReserveNewNeedAlloc<T> {
+    /// Make the necessary allocations for another call to `reserve_new`.
+    pub(crate) fn make_alloc(mut self) -> Result<ReserveNewArgs<T>> {
+        if self.need_empty_array_alloc && self.args.empty_array_alloc.is_none() {
+            self.args.empty_array_alloc = Some(EmptyArrayAlloc::try_new(TREE_THRESHOLD)?);
+        }
+        if self.need_new_tree_alloc && self.args.new_tree_alloc.is_none() {
+            self.args.new_tree_alloc = Some(FromArrayAllocs::try_new(TREE_THRESHOLD)?);
+        }
+        if self.need_tree_alloc && self.args.tree_alloc.is_none() {
+            self.args.tree_alloc = Some(ReserveNewTreeAlloc::try_new()?);
+        }
+        Ok(self.args)
+    }
+}
diff --git a/drivers/android/binder/range_alloc/tree.rs b/drivers/android/binder/range_alloc/tree.rs
new file mode 100644
index 000000000000..838fdd2b47ea
--- /dev/null
+++ b/drivers/android/binder/range_alloc/tree.rs
@@ -0,0 +1,488 @@
+// SPDX-License-Identifier: GPL-2.0
+
+// Copyright (C) 2025 Google LLC.
+
+use kernel::{
+    page::PAGE_SIZE,
+    prelude::*,
+    rbtree::{RBTree, RBTreeNode, RBTreeNodeReservation},
+    seq_file::SeqFile,
+    seq_print,
+    task::Pid,
+};
+
+use crate::range_alloc::{DescriptorState, FreedRange, Range};
+
+/// Keeps track of allocations in a process' mmap.
+///
+/// Each process has an mmap where the data for incoming transactions will be placed. This struct
+/// keeps track of allocations made in the mmap. For each allocation, we store a descriptor that
+/// has metadata related to the allocation. We also keep track of available free space.
+pub(super) struct TreeRangeAllocator<T> {
+    /// This collection contains descriptors for *both* ranges containing an allocation, *and* free
+    /// ranges between allocations. The free ranges get merged, so there are never two free ranges
+    /// next to each other.
+    tree: RBTree<usize, Descriptor<T>>,
+    /// Contains an entry for every free range in `self.tree`. This tree sorts the ranges by size,
+    /// letting us look up the smallest range whose size is at least some lower bound.
+    free_tree: RBTree<FreeKey, ()>,
+    size: usize,
+    free_oneway_space: usize,
+}
+
+impl<T> TreeRangeAllocator<T> {
+    pub(crate) fn from_array(
+        size: usize,
+        ranges: &mut KVec<Range<T>>,
+        alloc: &mut FromArrayAllocs<T>,
+    ) -> Self {
+        let mut tree = TreeRangeAllocator {
+            tree: RBTree::new(),
+            free_tree: RBTree::new(),
+            size,
+            free_oneway_space: size / 2,
+        };
+
+        let mut free_offset = 0;
+        for range in ranges.drain_all() {
+            let free_size = range.offset - free_offset;
+            if free_size > 0 {
+                let free_node = alloc.free_tree.pop().unwrap();
+                tree.free_tree
+                    .insert(free_node.into_node((free_size, free_offset), ()));
+                let tree_node = alloc.tree.pop().unwrap();
+                tree.tree.insert(
+                    tree_node.into_node(free_offset, Descriptor::new(free_offset, free_size)),
+                );
+            }
+            free_offset = range.endpoint();
+
+            if range.state.is_oneway() {
+                tree.free_oneway_space = tree.free_oneway_space.saturating_sub(range.size);
+            }
+
+            let free_res = alloc.free_tree.pop().unwrap();
+            let tree_node = alloc.tree.pop().unwrap();
+            let mut desc = Descriptor::new(range.offset, range.size);
+            desc.state = Some((range.state, free_res));
+            tree.tree.insert(tree_node.into_node(range.offset, desc));
+        }
+
+        // After the last range, we may need a free range.
+        if free_offset < size {
+            let free_size = size - free_offset;
+            let free_node = alloc.free_tree.pop().unwrap();
+            tree.free_tree
+                .insert(free_node.into_node((free_size, free_offset), ()));
+            let tree_node = alloc.tree.pop().unwrap();
+            tree.tree
+                .insert(tree_node.into_node(free_offset, Descriptor::new(free_offset, free_size)));
+        }
+
+        tree
+    }
+
+    pub(crate) fn is_empty(&self) -> bool {
+        let mut tree_iter = self.tree.values();
+        // There's always at least one range, because index zero is either the start of a free or
+        // allocated range.
+        let first_value = tree_iter.next().unwrap();
+        if tree_iter.next().is_some() {
+            // There are never two free ranges next to each other, so if there is more than one
+            // descriptor, then at least one of them must hold an allocated range.
+            return false;
+        }
+        // There is only one descriptor. Return true if it is for a free range.
+        first_value.state.is_none()
+    }
+
+    pub(crate) fn total_size(&self) -> usize {
+        self.size
+    }
+
+    pub(crate) fn free_oneway_space(&self) -> usize {
+        self.free_oneway_space
+    }
+
+    pub(crate) fn count_buffers(&self) -> usize {
+        self.tree
+            .values()
+            .filter(|desc| desc.state.is_some())
+            .count()
+    }
+
+    pub(crate) fn debug_print(&self, m: &SeqFile) -> Result<()> {
+        for desc in self.tree.values() {
+            let state = match &desc.state {
+                Some(state) => &state.0,
+                None => continue,
+            };
+            seq_print!(
+                m,
+                "  buffer: {} size {} pid {}",
+                desc.offset,
+                desc.size,
+                state.pid(),
+            );
+            if state.is_oneway() {
+                seq_print!(m, " oneway");
+            }
+            match state {
+                DescriptorState::Reserved(_res) => {
+                    seq_print!(m, " reserved\n");
+                }
+                DescriptorState::Allocated(_alloc) => {
+                    seq_print!(m, " allocated\n");
+                }
+            }
+        }
+        Ok(())
+    }
+
+    fn find_best_match(&mut self, size: usize) -> Option<&mut Descriptor<T>> {
+        let free_cursor = self.free_tree.cursor_lower_bound(&(size, 0))?;
+        let ((_, offset), ()) = free_cursor.current();
+        self.tree.get_mut(offset)
+    }
+
+    /// Try to reserve a new buffer, using the provided allocation if necessary.
+    pub(crate) fn reserve_new(
+        &mut self,
+        debug_id: usize,
+        size: usize,
+        is_oneway: bool,
+        pid: Pid,
+        alloc: ReserveNewTreeAlloc<T>,
+    ) -> Result<(usize, bool)> {
+        // Compute new value of free_oneway_space, which is set only on success.
+        let new_oneway_space = if is_oneway {
+            match self.free_oneway_space.checked_sub(size) {
+                Some(new_oneway_space) => new_oneway_space,
+                None => return Err(ENOSPC),
+            }
+        } else {
+            self.free_oneway_space
+        };
+
+        // Start detecting spammers once we have less than 20%
+        // of async space left (which is less than 10% of total
+        // buffer size).
+        //
+        // (This will short-circut, so `low_oneway_space` is
+        // only called when necessary.)
+        let oneway_spam_detected =
+            is_oneway && new_oneway_space < self.size / 10 && self.low_oneway_space(pid);
+
+        let (found_size, found_off, tree_node, free_tree_node) = match self.find_best_match(size) {
+            None => {
+                pr_warn!("ENOSPC from range_alloc.reserve_new - size: {}", size);
+                return Err(ENOSPC);
+            }
+            Some(desc) => {
+                let found_size = desc.size;
+                let found_offset = desc.offset;
+
+                // In case we need to break up the descriptor
+                let new_desc = Descriptor::new(found_offset + size, found_size - size);
+                let (tree_node, free_tree_node, desc_node_res) = alloc.initialize(new_desc);
+
+                desc.state = Some((
+                    DescriptorState::new(is_oneway, debug_id, pid),
+                    desc_node_res,
+                ));
+                desc.size = size;
+
+                (found_size, found_offset, tree_node, free_tree_node)
+            }
+        };
+        self.free_oneway_space = new_oneway_space;
+        self.free_tree.remove(&(found_size, found_off));
+
+        if found_size != size {
+            self.tree.insert(tree_node);
+            self.free_tree.insert(free_tree_node);
+        }
+
+        Ok((found_off, oneway_spam_detected))
+    }
+
+    pub(crate) fn reservation_abort(&mut self, offset: usize) -> Result<FreedRange> {
+        let mut cursor = self.tree.cursor_lower_bound_mut(&offset).ok_or_else(|| {
+            pr_warn!(
+                "EINVAL from range_alloc.reservation_abort - offset: {}",
+                offset
+            );
+            EINVAL
+        })?;
+
+        let (_, desc) = cursor.current_mut();
+
+        if desc.offset != offset {
+            pr_warn!(
+                "EINVAL from range_alloc.reservation_abort - offset: {}",
+                offset
+            );
+            return Err(EINVAL);
+        }
+
+        let (reservation, free_node_res) = desc.try_change_state(|state| match state {
+            Some((DescriptorState::Reserved(reservation), free_node_res)) => {
+                (None, Ok((reservation, free_node_res)))
+            }
+            None => {
+                pr_warn!(
+                    "EINVAL from range_alloc.reservation_abort - offset: {}",
+                    offset
+                );
+                (None, Err(EINVAL))
+            }
+            allocated => {
+                pr_warn!(
+                    "EPERM from range_alloc.reservation_abort - offset: {}",
+                    offset
+                );
+                (allocated, Err(EPERM))
+            }
+        })?;
+
+        let mut size = desc.size;
+        let mut offset = desc.offset;
+        let free_oneway_space_add = if reservation.is_oneway { size } else { 0 };
+
+        self.free_oneway_space += free_oneway_space_add;
+
+        let mut freed_range = FreedRange::interior_pages(offset, size);
+        // Compute how large the next free region needs to be to include one more page in
+        // the newly freed range.
+        let add_next_page_needed = match (offset + size) % PAGE_SIZE {
+            0 => usize::MAX,
+            unalign => PAGE_SIZE - unalign,
+        };
+        // Compute how large the previous free region needs to be to include one more page
+        // in the newly freed range.
+        let add_prev_page_needed = match offset % PAGE_SIZE {
+            0 => usize::MAX,
+            unalign => unalign,
+        };
+
+        // Merge next into current if next is free
+        let remove_next = match cursor.peek_next() {
+            Some((_, next)) if next.state.is_none() => {
+                if next.size >= add_next_page_needed {
+                    freed_range.end_page_idx += 1;
+                }
+                self.free_tree.remove(&(next.size, next.offset));
+                size += next.size;
+                true
+            }
+            _ => false,
+        };
+
+        if remove_next {
+            let (_, desc) = cursor.current_mut();
+            desc.size = size;
+            cursor.remove_next();
+        }
+
+        // Merge current into prev if prev is free
+        match cursor.peek_prev_mut() {
+            Some((_, prev)) if prev.state.is_none() => {
+                if prev.size >= add_prev_page_needed {
+                    freed_range.start_page_idx -= 1;
+                }
+                // merge previous with current, remove current
+                self.free_tree.remove(&(prev.size, prev.offset));
+                offset = prev.offset;
+                size += prev.size;
+                prev.size = size;
+                cursor.remove_current();
+            }
+            _ => {}
+        };
+
+        self.free_tree
+            .insert(free_node_res.into_node((size, offset), ()));
+
+        Ok(freed_range)
+    }
+
+    pub(crate) fn reservation_commit(&mut self, offset: usize, data: &mut Option<T>) -> Result {
+        let desc = self.tree.get_mut(&offset).ok_or(ENOENT)?;
+
+        desc.try_change_state(|state| match state {
+            Some((DescriptorState::Reserved(reservation), free_node_res)) => (
+                Some((
+                    DescriptorState::Allocated(reservation.allocate(data.take())),
+                    free_node_res,
+                )),
+                Ok(()),
+            ),
+            other => (other, Err(ENOENT)),
+        })
+    }
+
+    /// Takes an entry at the given offset from [`DescriptorState::Allocated`] to
+    /// [`DescriptorState::Reserved`].
+    ///
+    /// Returns the size of the existing entry and the data associated with it.
+    pub(crate) fn reserve_existing(&mut self, offset: usize) -> Result<(usize, usize, Option<T>)> {
+        let desc = self.tree.get_mut(&offset).ok_or_else(|| {
+            pr_warn!(
+                "ENOENT from range_alloc.reserve_existing - offset: {}",
+                offset
+            );
+            ENOENT
+        })?;
+
+        let (debug_id, data) = desc.try_change_state(|state| match state {
+            Some((DescriptorState::Allocated(allocation), free_node_res)) => {
+                let (reservation, data) = allocation.deallocate();
+                let debug_id = reservation.debug_id;
+                (
+                    Some((DescriptorState::Reserved(reservation), free_node_res)),
+                    Ok((debug_id, data)),
+                )
+            }
+            other => {
+                pr_warn!(
+                    "ENOENT from range_alloc.reserve_existing - offset: {}",
+                    offset
+                );
+                (other, Err(ENOENT))
+            }
+        })?;
+
+        Ok((desc.size, debug_id, data))
+    }
+
+    /// Call the provided callback at every allocated region.
+    ///
+    /// This destroys the range allocator. Used only during shutdown.
+    pub(crate) fn take_for_each<F: Fn(usize, usize, usize, Option<T>)>(&mut self, callback: F) {
+        for (_, desc) in self.tree.iter_mut() {
+            if let Some((DescriptorState::Allocated(allocation), _)) = &mut desc.state {
+                callback(
+                    desc.offset,
+                    desc.size,
+                    allocation.debug_id(),
+                    allocation.take(),
+                );
+            }
+        }
+    }
+
+    /// Find the amount and size of buffers allocated by the current caller.
+    ///
+    /// The idea is that once we cross the threshold, whoever is responsible
+    /// for the low async space is likely to try to send another async transaction,
+    /// and at some point we'll catch them in the act.  This is more efficient
+    /// than keeping a map per pid.
+    fn low_oneway_space(&self, calling_pid: Pid) -> bool {
+        let mut total_alloc_size = 0;
+        let mut num_buffers = 0;
+        for (_, desc) in self.tree.iter() {
+            if let Some((state, _)) = &desc.state {
+                if state.is_oneway() && state.pid() == calling_pid {
+                    total_alloc_size += desc.size;
+                    num_buffers += 1;
+                }
+            }
+        }
+
+        // Warn if this pid has more than 50 transactions, or more than 50% of
+        // async space (which is 25% of total buffer size). Oneway spam is only
+        // detected when the threshold is exceeded.
+        num_buffers > 50 || total_alloc_size > self.size / 4
+    }
+}
+
+type TreeDescriptorState<T> = (DescriptorState<T>, FreeNodeRes);
+struct Descriptor<T> {
+    size: usize,
+    offset: usize,
+    state: Option<TreeDescriptorState<T>>,
+}
+
+impl<T> Descriptor<T> {
+    fn new(offset: usize, size: usize) -> Self {
+        Self {
+            size,
+            offset,
+            state: None,
+        }
+    }
+
+    fn try_change_state<F, Data>(&mut self, f: F) -> Result<Data>
+    where
+        F: FnOnce(Option<TreeDescriptorState<T>>) -> (Option<TreeDescriptorState<T>>, Result<Data>),
+    {
+        let (new_state, result) = f(self.state.take());
+        self.state = new_state;
+        result
+    }
+}
+
+// (Descriptor.size, Descriptor.offset)
+type FreeKey = (usize, usize);
+type FreeNodeRes = RBTreeNodeReservation<FreeKey, ()>;
+
+/// An allocation for use by `reserve_new`.
+pub(crate) struct ReserveNewTreeAlloc<T> {
+    tree_node_res: RBTreeNodeReservation<usize, Descriptor<T>>,
+    free_tree_node_res: FreeNodeRes,
+    desc_node_res: FreeNodeRes,
+}
+
+impl<T> ReserveNewTreeAlloc<T> {
+    pub(crate) fn try_new() -> Result<Self> {
+        let tree_node_res = RBTreeNodeReservation::new(GFP_KERNEL)?;
+        let free_tree_node_res = RBTreeNodeReservation::new(GFP_KERNEL)?;
+        let desc_node_res = RBTreeNodeReservation::new(GFP_KERNEL)?;
+        Ok(Self {
+            tree_node_res,
+            free_tree_node_res,
+            desc_node_res,
+        })
+    }
+
+    fn initialize(
+        self,
+        desc: Descriptor<T>,
+    ) -> (
+        RBTreeNode<usize, Descriptor<T>>,
+        RBTreeNode<FreeKey, ()>,
+        FreeNodeRes,
+    ) {
+        let size = desc.size;
+        let offset = desc.offset;
+        (
+            self.tree_node_res.into_node(offset, desc),
+            self.free_tree_node_res.into_node((size, offset), ()),
+            self.desc_node_res,
+        )
+    }
+}
+
+/// An allocation for creating a tree from an `ArrayRangeAllocator`.
+pub(crate) struct FromArrayAllocs<T> {
+    tree: KVec<RBTreeNodeReservation<usize, Descriptor<T>>>,
+    free_tree: KVec<RBTreeNodeReservation<FreeKey, ()>>,
+}
+
+impl<T> FromArrayAllocs<T> {
+    pub(crate) fn try_new(len: usize) -> Result<Self> {
+        let num_descriptors = 2 * len + 1;
+
+        let mut tree = KVec::with_capacity(num_descriptors, GFP_KERNEL)?;
+        for _ in 0..num_descriptors {
+            tree.push(RBTreeNodeReservation::new(GFP_KERNEL)?, GFP_KERNEL)?;
+        }
+
+        let mut free_tree = KVec::with_capacity(num_descriptors, GFP_KERNEL)?;
+        for _ in 0..num_descriptors {
+            free_tree.push(RBTreeNodeReservation::new(GFP_KERNEL)?, GFP_KERNEL)?;
+        }
+
+        Ok(Self { tree, free_tree })
+    }
+}
diff --git a/drivers/android/binder/rust_binder.h b/drivers/android/binder/rust_binder.h
new file mode 100644
index 000000000000..31806890ed1a
--- /dev/null
+++ b/drivers/android/binder/rust_binder.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2025 Google, Inc.
+ */
+
+#ifndef _LINUX_RUST_BINDER_H
+#define _LINUX_RUST_BINDER_H
+
+#include <uapi/linux/android/binder.h>
+#include <uapi/linux/android/binderfs.h>
+
+/*
+ * These symbols are exposed by `rust_binderfs.c` and exist here so that Rust
+ * Binder can call them.
+ */
+int init_rust_binderfs(void);
+
+struct dentry;
+struct inode;
+struct dentry *rust_binderfs_create_proc_file(struct inode *nodp, int pid);
+void rust_binderfs_remove_file(struct dentry *dentry);
+
+#endif
diff --git a/drivers/android/binder/rust_binder_events.c b/drivers/android/binder/rust_binder_events.c
new file mode 100644
index 000000000000..488b1470060c
--- /dev/null
+++ b/drivers/android/binder/rust_binder_events.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* rust_binder_events.c
+ *
+ * Rust Binder tracepoints.
+ *
+ * Copyright 2025 Google LLC
+ */
+
+#include "rust_binder.h"
+
+const char * const binder_command_strings[] = {
+	"BC_TRANSACTION",
+	"BC_REPLY",
+	"BC_ACQUIRE_RESULT",
+	"BC_FREE_BUFFER",
+	"BC_INCREFS",
+	"BC_ACQUIRE",
+	"BC_RELEASE",
+	"BC_DECREFS",
+	"BC_INCREFS_DONE",
+	"BC_ACQUIRE_DONE",
+	"BC_ATTEMPT_ACQUIRE",
+	"BC_REGISTER_LOOPER",
+	"BC_ENTER_LOOPER",
+	"BC_EXIT_LOOPER",
+	"BC_REQUEST_DEATH_NOTIFICATION",
+	"BC_CLEAR_DEATH_NOTIFICATION",
+	"BC_DEAD_BINDER_DONE",
+	"BC_TRANSACTION_SG",
+	"BC_REPLY_SG",
+};
+
+const char * const binder_return_strings[] = {
+	"BR_ERROR",
+	"BR_OK",
+	"BR_TRANSACTION",
+	"BR_REPLY",
+	"BR_ACQUIRE_RESULT",
+	"BR_DEAD_REPLY",
+	"BR_TRANSACTION_COMPLETE",
+	"BR_INCREFS",
+	"BR_ACQUIRE",
+	"BR_RELEASE",
+	"BR_DECREFS",
+	"BR_ATTEMPT_ACQUIRE",
+	"BR_NOOP",
+	"BR_SPAWN_LOOPER",
+	"BR_FINISHED",
+	"BR_DEAD_BINDER",
+	"BR_CLEAR_DEATH_NOTIFICATION_DONE",
+	"BR_FAILED_REPLY",
+	"BR_FROZEN_REPLY",
+	"BR_ONEWAY_SPAM_SUSPECT",
+	"BR_TRANSACTION_PENDING_FROZEN"
+};
+
+#define CREATE_TRACE_POINTS
+#define CREATE_RUST_TRACE_POINTS
+#include "rust_binder_events.h"
diff --git a/drivers/android/binder/rust_binder_events.h b/drivers/android/binder/rust_binder_events.h
new file mode 100644
index 000000000000..2f3efbf9dba6
--- /dev/null
+++ b/drivers/android/binder/rust_binder_events.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2025 Google, Inc.
+ */
+
+#undef TRACE_SYSTEM
+#undef TRACE_INCLUDE_FILE
+#undef TRACE_INCLUDE_PATH
+#define TRACE_SYSTEM rust_binder
+#define TRACE_INCLUDE_FILE rust_binder_events
+#define TRACE_INCLUDE_PATH ../drivers/android/binder
+
+#if !defined(_RUST_BINDER_TRACE_H) || defined(TRACE_HEADER_MULTI_READ)
+#define _RUST_BINDER_TRACE_H
+
+#include <linux/tracepoint.h>
+
+TRACE_EVENT(rust_binder_ioctl,
+	TP_PROTO(unsigned int cmd, unsigned long arg),
+	TP_ARGS(cmd, arg),
+
+	TP_STRUCT__entry(
+		__field(unsigned int, cmd)
+		__field(unsigned long, arg)
+	),
+	TP_fast_assign(
+		__entry->cmd = cmd;
+		__entry->arg = arg;
+	),
+	TP_printk("cmd=0x%x arg=0x%lx", __entry->cmd, __entry->arg)
+);
+
+#endif /* _RUST_BINDER_TRACE_H */
+
+/* This part must be outside protection */
+#include <trace/define_trace.h>
diff --git a/drivers/android/binder/rust_binder_internal.h b/drivers/android/binder/rust_binder_internal.h
new file mode 100644
index 000000000000..78288fe7964d
--- /dev/null
+++ b/drivers/android/binder/rust_binder_internal.h
@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* rust_binder_internal.h
+ *
+ * This file contains internal data structures used by Rust Binder. Mostly,
+ * these are type definitions used only by binderfs or things that Rust Binder
+ * define and export to binderfs.
+ *
+ * It does not include things exported by binderfs to Rust Binder since this
+ * file is not included as input to bindgen.
+ *
+ * Copyright (C) 2025 Google LLC.
+ */
+
+#ifndef _LINUX_RUST_BINDER_INTERNAL_H
+#define _LINUX_RUST_BINDER_INTERNAL_H
+
+#define RUST_BINDERFS_SUPER_MAGIC	0x6c6f6f71
+
+#include <linux/seq_file.h>
+#include <uapi/linux/android/binder.h>
+#include <uapi/linux/android/binderfs.h>
+
+/*
+ * The internal data types in the Rust Binder driver are opaque to C, so we use
+ * void pointer typedefs for these types.
+ */
+typedef void *rust_binder_context;
+
+/**
+ * struct binder_device - information about a binder device node
+ * @minor:     the minor number used by this device
+ * @ctx:       the Rust Context used by this device, or null for binder-control
+ *
+ * This is used as the private data for files directly in binderfs, but not
+ * files in the binder_logs subdirectory. This struct owns a refcount on `ctx`
+ * and the entry for `minor` in `binderfs_minors`. For binder-control `ctx` is
+ * null.
+ */
+struct binder_device {
+	int minor;
+	rust_binder_context ctx;
+};
+
+int rust_binder_stats_show(struct seq_file *m, void *unused);
+int rust_binder_state_show(struct seq_file *m, void *unused);
+int rust_binder_transactions_show(struct seq_file *m, void *unused);
+int rust_binder_proc_show(struct seq_file *m, void *pid);
+
+extern const struct file_operations rust_binder_fops;
+rust_binder_context rust_binder_new_context(char *name);
+void rust_binder_remove_context(rust_binder_context device);
+
+/**
+ * binderfs_mount_opts - mount options for binderfs
+ * @max: maximum number of allocatable binderfs binder devices
+ * @stats_mode: enable binder stats in binderfs.
+ */
+struct binderfs_mount_opts {
+	int max;
+	int stats_mode;
+};
+
+/**
+ * binderfs_info - information about a binderfs mount
+ * @ipc_ns:         The ipc namespace the binderfs mount belongs to.
+ * @control_dentry: This records the dentry of this binderfs mount
+ *                  binder-control device.
+ * @root_uid:       uid that needs to be used when a new binder device is
+ *                  created.
+ * @root_gid:       gid that needs to be used when a new binder device is
+ *                  created.
+ * @mount_opts:     The mount options in use.
+ * @device_count:   The current number of allocated binder devices.
+ * @proc_log_dir:   Pointer to the directory dentry containing process-specific
+ *                  logs.
+ */
+struct binderfs_info {
+	struct ipc_namespace *ipc_ns;
+	struct dentry *control_dentry;
+	kuid_t root_uid;
+	kgid_t root_gid;
+	struct binderfs_mount_opts mount_opts;
+	int device_count;
+	struct dentry *proc_log_dir;
+};
+
+#endif /* _LINUX_RUST_BINDER_INTERNAL_H */
diff --git a/drivers/android/binder/rust_binder_main.rs b/drivers/android/binder/rust_binder_main.rs
new file mode 100644
index 000000000000..c79a9e742240
--- /dev/null
+++ b/drivers/android/binder/rust_binder_main.rs
@@ -0,0 +1,611 @@
+// SPDX-License-Identifier: GPL-2.0
+
+// Copyright (C) 2025 Google LLC.
+
+//! Binder -- the Android IPC mechanism.
+#![recursion_limit = "256"]
+#![allow(
+    clippy::as_underscore,
+    clippy::ref_as_ptr,
+    clippy::ptr_as_ptr,
+    clippy::cast_lossless
+)]
+
+use kernel::{
+    bindings::{self, seq_file},
+    fs::File,
+    list::{ListArc, ListArcSafe, ListLinksSelfPtr, TryNewListArc},
+    prelude::*,
+    seq_file::SeqFile,
+    seq_print,
+    sync::poll::PollTable,
+    sync::Arc,
+    task::Pid,
+    transmute::AsBytes,
+    types::ForeignOwnable,
+    uaccess::UserSliceWriter,
+};
+
+use crate::{context::Context, page_range::Shrinker, process::Process, thread::Thread};
+
+use core::{
+    ptr::NonNull,
+    sync::atomic::{AtomicBool, AtomicUsize, Ordering},
+};
+
+mod allocation;
+mod context;
+mod deferred_close;
+mod defs;
+mod error;
+mod node;
+mod page_range;
+mod process;
+mod range_alloc;
+mod stats;
+mod thread;
+mod trace;
+mod transaction;
+
+#[allow(warnings)] // generated bindgen code
+mod binderfs {
+    use kernel::bindings::{dentry, inode};
+
+    extern "C" {
+        pub fn init_rust_binderfs() -> kernel::ffi::c_int;
+    }
+    extern "C" {
+        pub fn rust_binderfs_create_proc_file(
+            nodp: *mut inode,
+            pid: kernel::ffi::c_int,
+        ) -> *mut dentry;
+    }
+    extern "C" {
+        pub fn rust_binderfs_remove_file(dentry: *mut dentry);
+    }
+    pub type rust_binder_context = *mut kernel::ffi::c_void;
+    #[repr(C)]
+    #[derive(Copy, Clone)]
+    pub struct binder_device {
+        pub minor: kernel::ffi::c_int,
+        pub ctx: rust_binder_context,
+    }
+    impl Default for binder_device {
+        fn default() -> Self {
+            let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
+            unsafe {
+                ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
+                s.assume_init()
+            }
+        }
+    }
+}
+
+module! {
+    type: BinderModule,
+    name: "rust_binder",
+    authors: ["Wedson Almeida Filho", "Alice Ryhl"],
+    description: "Android Binder",
+    license: "GPL",
+}
+
+fn next_debug_id() -> usize {
+    static NEXT_DEBUG_ID: AtomicUsize = AtomicUsize::new(0);
+
+    NEXT_DEBUG_ID.fetch_add(1, Ordering::Relaxed)
+}
+
+/// Provides a single place to write Binder return values via the
+/// supplied `UserSliceWriter`.
+pub(crate) struct BinderReturnWriter<'a> {
+    writer: UserSliceWriter,
+    thread: &'a Thread,
+}
+
+impl<'a> BinderReturnWriter<'a> {
+    fn new(writer: UserSliceWriter, thread: &'a Thread) -> Self {
+        BinderReturnWriter { writer, thread }
+    }
+
+    /// Write a return code back to user space.
+    /// Should be a `BR_` constant from [`defs`] e.g. [`defs::BR_TRANSACTION_COMPLETE`].
+    fn write_code(&mut self, code: u32) -> Result {
+        stats::GLOBAL_STATS.inc_br(code);
+        self.thread.process.stats.inc_br(code);
+        self.writer.write(&code)
+    }
+
+    /// Write something *other than* a return code to user space.
+    fn write_payload<T: AsBytes>(&mut self, payload: &T) -> Result {
+        self.writer.write(payload)
+    }
+
+    fn len(&self) -> usize {
+        self.writer.len()
+    }
+}
+
+/// Specifies how a type should be delivered to the read part of a BINDER_WRITE_READ ioctl.
+///
+/// When a value is pushed to the todo list for a process or thread, it is stored as a trait object
+/// with the type `Arc<dyn DeliverToRead>`. Trait objects are a Rust feature that lets you
+/// implement dynamic dispatch over many different types. This lets us store many different types
+/// in the todo list.
+trait DeliverToRead: ListArcSafe + Send + Sync {
+    /// Performs work. Returns true if remaining work items in the queue should be processed
+    /// immediately, or false if it should return to caller before processing additional work
+    /// items.
+    fn do_work(
+        self: DArc<Self>,
+        thread: &Thread,
+        writer: &mut BinderReturnWriter<'_>,
+    ) -> Result<bool>;
+
+    /// Cancels the given work item. This is called instead of [`DeliverToRead::do_work`] when work
+    /// won't be delivered.
+    fn cancel(self: DArc<Self>);
+
+    /// Should we use `wake_up_interruptible_sync` or `wake_up_interruptible` when scheduling this
+    /// work item?
+    ///
+    /// Generally only set to true for non-oneway transactions.
+    fn should_sync_wakeup(&self) -> bool;
+
+    fn debug_print(&self, m: &SeqFile, prefix: &str, transaction_prefix: &str) -> Result<()>;
+}
+
+// Wrapper around a `DeliverToRead` with linked list links.
+#[pin_data]
+struct DTRWrap<T: ?Sized> {
+    #[pin]
+    links: ListLinksSelfPtr<DTRWrap<dyn DeliverToRead>>,
+    #[pin]
+    wrapped: T,
+}
+kernel::list::impl_list_arc_safe! {
+    impl{T: ListArcSafe + ?Sized} ListArcSafe<0> for DTRWrap<T> {
+        tracked_by wrapped: T;
+    }
+}
+kernel::list::impl_list_item! {
+    impl ListItem<0> for DTRWrap<dyn DeliverToRead> {
+        using ListLinksSelfPtr { self.links };
+    }
+}
+
+impl<T: ?Sized> core::ops::Deref for DTRWrap<T> {
+    type Target = T;
+    fn deref(&self) -> &T {
+        &self.wrapped
+    }
+}
+
+type DArc<T> = kernel::sync::Arc<DTRWrap<T>>;
+type DLArc<T> = kernel::list::ListArc<DTRWrap<T>>;
+
+impl<T: ListArcSafe> DTRWrap<T> {
+    fn new(val: impl PinInit<T>) -> impl PinInit<Self> {
+        pin_init!(Self {
+            links <- ListLinksSelfPtr::new(),
+            wrapped <- val,
+        })
+    }
+
+    fn arc_try_new(val: T) -> Result<DLArc<T>, kernel::alloc::AllocError> {
+        ListArc::pin_init(
+            try_pin_init!(Self {
+                links <- ListLinksSelfPtr::new(),
+                wrapped: val,
+            }),
+            GFP_KERNEL,
+        )
+        .map_err(|_| kernel::alloc::AllocError)
+    }
+
+    fn arc_pin_init(init: impl PinInit<T>) -> Result<DLArc<T>, kernel::error::Error> {
+        ListArc::pin_init(
+            try_pin_init!(Self {
+                links <- ListLinksSelfPtr::new(),
+                wrapped <- init,
+            }),
+            GFP_KERNEL,
+        )
+    }
+}
+
+struct DeliverCode {
+    code: u32,
+    skip: AtomicBool,
+}
+
+kernel::list::impl_list_arc_safe! {
+    impl ListArcSafe<0> for DeliverCode { untracked; }
+}
+
+impl DeliverCode {
+    fn new(code: u32) -> Self {
+        Self {
+            code,
+            skip: AtomicBool::new(false),
+        }
+    }
+
+    /// Disable this DeliverCode and make it do nothing.
+    ///
+    /// This is used instead of removing it from the work list, since `LinkedList::remove` is
+    /// unsafe, whereas this method is not.
+    fn skip(&self) {
+        self.skip.store(true, Ordering::Relaxed);
+    }
+}
+
+impl DeliverToRead for DeliverCode {
+    fn do_work(
+        self: DArc<Self>,
+        _thread: &Thread,
+        writer: &mut BinderReturnWriter<'_>,
+    ) -> Result<bool> {
+        if !self.skip.load(Ordering::Relaxed) {
+            writer.write_code(self.code)?;
+        }
+        Ok(true)
+    }
+
+    fn cancel(self: DArc<Self>) {}
+
+    fn should_sync_wakeup(&self) -> bool {
+        false
+    }
+
+    fn debug_print(&self, m: &SeqFile, prefix: &str, _tprefix: &str) -> Result<()> {
+        seq_print!(m, "{}", prefix);
+        if self.skip.load(Ordering::Relaxed) {
+            seq_print!(m, "(skipped) ");
+        }
+        if self.code == defs::BR_TRANSACTION_COMPLETE {
+            seq_print!(m, "transaction complete\n");
+        } else {
+            seq_print!(m, "transaction error: {}\n", self.code);
+        }
+        Ok(())
+    }
+}
+
+fn ptr_align(value: usize) -> Option<usize> {
+    let size = core::mem::size_of::<usize>() - 1;
+    Some(value.checked_add(size)? & !size)
+}
+
+// SAFETY: We call register in `init`.
+static BINDER_SHRINKER: Shrinker = unsafe { Shrinker::new() };
+
+struct BinderModule {}
+
+impl kernel::Module for BinderModule {
+    fn init(_module: &'static kernel::ThisModule) -> Result<Self> {
+        // SAFETY: The module initializer never runs twice, so we only call this once.
+        unsafe { crate::context::CONTEXTS.init() };
+
+        pr_warn!("Loaded Rust Binder.");
+
+        BINDER_SHRINKER.register(kernel::c_str!("android-binder"))?;
+
+        // SAFETY: The module is being loaded, so we can initialize binderfs.
+        unsafe { kernel::error::to_result(binderfs::init_rust_binderfs())? };
+
+        Ok(Self {})
+    }
+}
+
+/// Makes the inner type Sync.
+#[repr(transparent)]
+pub struct AssertSync<T>(T);
+// SAFETY: Used only to insert `file_operations` into a global, which is safe.
+unsafe impl<T> Sync for AssertSync<T> {}
+
+/// File operations that rust_binderfs.c can use.
+#[no_mangle]
+#[used]
+pub static rust_binder_fops: AssertSync<kernel::bindings::file_operations> = {
+    // SAFETY: All zeroes is safe for the `file_operations` type.
+    let zeroed_ops = unsafe { core::mem::MaybeUninit::zeroed().assume_init() };
+
+    let ops = kernel::bindings::file_operations {
+        owner: THIS_MODULE.as_ptr(),
+        poll: Some(rust_binder_poll),
+        unlocked_ioctl: Some(rust_binder_ioctl),
+        compat_ioctl: Some(bindings::compat_ptr_ioctl),
+        mmap: Some(rust_binder_mmap),
+        open: Some(rust_binder_open),
+        release: Some(rust_binder_release),
+        flush: Some(rust_binder_flush),
+        ..zeroed_ops
+    };
+    AssertSync(ops)
+};
+
+/// # Safety
+/// Only called by binderfs.
+#[no_mangle]
+unsafe extern "C" fn rust_binder_new_context(
+    name: *const kernel::ffi::c_char,
+) -> *mut kernel::ffi::c_void {
+    // SAFETY: The caller will always provide a valid c string here.
+    let name = unsafe { kernel::str::CStr::from_char_ptr(name) };
+    match Context::new(name) {
+        Ok(ctx) => Arc::into_foreign(ctx),
+        Err(_err) => core::ptr::null_mut(),
+    }
+}
+
+/// # Safety
+/// Only called by binderfs.
+#[no_mangle]
+unsafe extern "C" fn rust_binder_remove_context(device: *mut kernel::ffi::c_void) {
+    if !device.is_null() {
+        // SAFETY: The caller ensures that the `device` pointer came from a previous call to
+        // `rust_binder_new_device`.
+        let ctx = unsafe { Arc::<Context>::from_foreign(device) };
+        ctx.deregister();
+        drop(ctx);
+    }
+}
+
+/// # Safety
+/// Only called by binderfs.
+unsafe extern "C" fn rust_binder_open(
+    inode: *mut bindings::inode,
+    file_ptr: *mut bindings::file,
+) -> kernel::ffi::c_int {
+    // SAFETY: The `rust_binderfs.c` file ensures that `i_private` is set to a
+    // `struct binder_device`.
+    let device = unsafe { (*inode).i_private } as *const binderfs::binder_device;
+
+    assert!(!device.is_null());
+
+    // SAFETY: The `rust_binderfs.c` file ensures that `device->ctx` holds a binder context when
+    // using the rust binder fops.
+    let ctx = unsafe { Arc::<Context>::borrow((*device).ctx) };
+
+    // SAFETY: The caller provides a valid file pointer to a new `struct file`.
+    let file = unsafe { File::from_raw_file(file_ptr) };
+    let process = match Process::open(ctx, file) {
+        Ok(process) => process,
+        Err(err) => return err.to_errno(),
+    };
+
+    // SAFETY: This is an `inode` for a newly created binder file.
+    match unsafe { BinderfsProcFile::new(inode, process.task.pid()) } {
+        Ok(Some(file)) => process.inner.lock().binderfs_file = Some(file),
+        Ok(None) => { /* pid already exists */ }
+        Err(err) => return err.to_errno(),
+    }
+
+    // SAFETY: This file is associated with Rust binder, so we own the `private_data` field.
+    unsafe { (*file_ptr).private_data = process.into_foreign() };
+    0
+}
+
+/// # Safety
+/// Only called by binderfs.
+unsafe extern "C" fn rust_binder_release(
+    _inode: *mut bindings::inode,
+    file: *mut bindings::file,
+) -> kernel::ffi::c_int {
+    // SAFETY: We previously set `private_data` in `rust_binder_open`.
+    let process = unsafe { Arc::<Process>::from_foreign((*file).private_data) };
+    // SAFETY: The caller ensures that the file is valid.
+    let file = unsafe { File::from_raw_file(file) };
+    Process::release(process, file);
+    0
+}
+
+/// # Safety
+/// Only called by binderfs.
+unsafe extern "C" fn rust_binder_ioctl(
+    file: *mut bindings::file,
+    cmd: kernel::ffi::c_uint,
+    arg: kernel::ffi::c_ulong,
+) -> kernel::ffi::c_long {
+    // SAFETY: We previously set `private_data` in `rust_binder_open`.
+    let f = unsafe { Arc::<Process>::borrow((*file).private_data) };
+    // SAFETY: The caller ensures that the file is valid.
+    match Process::ioctl(f, unsafe { File::from_raw_file(file) }, cmd as _, arg as _) {
+        Ok(()) => 0,
+        Err(err) => err.to_errno() as isize,
+    }
+}
+
+/// # Safety
+/// Only called by binderfs.
+unsafe extern "C" fn rust_binder_mmap(
+    file: *mut bindings::file,
+    vma: *mut bindings::vm_area_struct,
+) -> kernel::ffi::c_int {
+    // SAFETY: We previously set `private_data` in `rust_binder_open`.
+    let f = unsafe { Arc::<Process>::borrow((*file).private_data) };
+    // SAFETY: The caller ensures that the vma is valid.
+    let area = unsafe { kernel::mm::virt::VmaNew::from_raw(vma) };
+    // SAFETY: The caller ensures that the file is valid.
+    match Process::mmap(f, unsafe { File::from_raw_file(file) }, area) {
+        Ok(()) => 0,
+        Err(err) => err.to_errno(),
+    }
+}
+
+/// # Safety
+/// Only called by binderfs.
+unsafe extern "C" fn rust_binder_poll(
+    file: *mut bindings::file,
+    wait: *mut bindings::poll_table_struct,
+) -> bindings::__poll_t {
+    // SAFETY: We previously set `private_data` in `rust_binder_open`.
+    let f = unsafe { Arc::<Process>::borrow((*file).private_data) };
+    // SAFETY: The caller ensures that the file is valid.
+    let fileref = unsafe { File::from_raw_file(file) };
+    // SAFETY: The caller ensures that the `PollTable` is valid.
+    match Process::poll(f, fileref, unsafe { PollTable::from_raw(wait) }) {
+        Ok(v) => v,
+        Err(_) => bindings::POLLERR,
+    }
+}
+
+/// # Safety
+/// Only called by binderfs.
+unsafe extern "C" fn rust_binder_flush(
+    file: *mut bindings::file,
+    _id: bindings::fl_owner_t,
+) -> kernel::ffi::c_int {
+    // SAFETY: We previously set `private_data` in `rust_binder_open`.
+    let f = unsafe { Arc::<Process>::borrow((*file).private_data) };
+    match Process::flush(f) {
+        Ok(()) => 0,
+        Err(err) => err.to_errno(),
+    }
+}
+
+/// # Safety
+/// Only called by binderfs.
+#[no_mangle]
+unsafe extern "C" fn rust_binder_stats_show(
+    ptr: *mut seq_file,
+    _: *mut kernel::ffi::c_void,
+) -> kernel::ffi::c_int {
+    // SAFETY: The caller ensures that the pointer is valid and exclusive for the duration in which
+    // this method is called.
+    let m = unsafe { SeqFile::from_raw(ptr) };
+    if let Err(err) = rust_binder_stats_show_impl(m) {
+        seq_print!(m, "failed to generate state: {:?}\n", err);
+    }
+    0
+}
+
+/// # Safety
+/// Only called by binderfs.
+#[no_mangle]
+unsafe extern "C" fn rust_binder_state_show(
+    ptr: *mut seq_file,
+    _: *mut kernel::ffi::c_void,
+) -> kernel::ffi::c_int {
+    // SAFETY: The caller ensures that the pointer is valid and exclusive for the duration in which
+    // this method is called.
+    let m = unsafe { SeqFile::from_raw(ptr) };
+    if let Err(err) = rust_binder_state_show_impl(m) {
+        seq_print!(m, "failed to generate state: {:?}\n", err);
+    }
+    0
+}
+
+/// # Safety
+/// Only called by binderfs.
+#[no_mangle]
+unsafe extern "C" fn rust_binder_proc_show(
+    ptr: *mut seq_file,
+    _: *mut kernel::ffi::c_void,
+) -> kernel::ffi::c_int {
+    // SAFETY: Accessing the private field of `seq_file` is okay.
+    let pid = (unsafe { (*ptr).private }) as usize as Pid;
+    // SAFETY: The caller ensures that the pointer is valid and exclusive for the duration in which
+    // this method is called.
+    let m = unsafe { SeqFile::from_raw(ptr) };
+    if let Err(err) = rust_binder_proc_show_impl(m, pid) {
+        seq_print!(m, "failed to generate state: {:?}\n", err);
+    }
+    0
+}
+
+/// # Safety
+/// Only called by binderfs.
+#[no_mangle]
+unsafe extern "C" fn rust_binder_transactions_show(
+    ptr: *mut seq_file,
+    _: *mut kernel::ffi::c_void,
+) -> kernel::ffi::c_int {
+    // SAFETY: The caller ensures that the pointer is valid and exclusive for the duration in which
+    // this method is called.
+    let m = unsafe { SeqFile::from_raw(ptr) };
+    if let Err(err) = rust_binder_transactions_show_impl(m) {
+        seq_print!(m, "failed to generate state: {:?}\n", err);
+    }
+    0
+}
+
+fn rust_binder_transactions_show_impl(m: &SeqFile) -> Result<()> {
+    seq_print!(m, "binder transactions:\n");
+    let contexts = context::get_all_contexts()?;
+    for ctx in contexts {
+        let procs = ctx.get_all_procs()?;
+        for proc in procs {
+            proc.debug_print(m, &ctx, false)?;
+            seq_print!(m, "\n");
+        }
+    }
+    Ok(())
+}
+
+fn rust_binder_stats_show_impl(m: &SeqFile) -> Result<()> {
+    seq_print!(m, "binder stats:\n");
+    stats::GLOBAL_STATS.debug_print("", m);
+    let contexts = context::get_all_contexts()?;
+    for ctx in contexts {
+        let procs = ctx.get_all_procs()?;
+        for proc in procs {
+            proc.debug_print_stats(m, &ctx)?;
+            seq_print!(m, "\n");
+        }
+    }
+    Ok(())
+}
+
+fn rust_binder_state_show_impl(m: &SeqFile) -> Result<()> {
+    seq_print!(m, "binder state:\n");
+    let contexts = context::get_all_contexts()?;
+    for ctx in contexts {
+        let procs = ctx.get_all_procs()?;
+        for proc in procs {
+            proc.debug_print(m, &ctx, true)?;
+            seq_print!(m, "\n");
+        }
+    }
+    Ok(())
+}
+
+fn rust_binder_proc_show_impl(m: &SeqFile, pid: Pid) -> Result<()> {
+    seq_print!(m, "binder proc state:\n");
+    let contexts = context::get_all_contexts()?;
+    for ctx in contexts {
+        let procs = ctx.get_procs_with_pid(pid)?;
+        for proc in procs {
+            proc.debug_print(m, &ctx, true)?;
+            seq_print!(m, "\n");
+        }
+    }
+    Ok(())
+}
+
+struct BinderfsProcFile(NonNull<bindings::dentry>);
+
+// SAFETY: Safe to drop any thread.
+unsafe impl Send for BinderfsProcFile {}
+
+impl BinderfsProcFile {
+    /// # Safety
+    ///
+    /// Takes an inode from a newly created binder file.
+    unsafe fn new(nodp: *mut bindings::inode, pid: i32) -> Result<Option<Self>> {
+        // SAFETY: The caller passes an `inode` for a newly created binder file.
+        let dentry = unsafe { binderfs::rust_binderfs_create_proc_file(nodp, pid) };
+        match kernel::error::from_err_ptr(dentry) {
+            Ok(dentry) => Ok(NonNull::new(dentry).map(Self)),
+            Err(err) if err == EEXIST => Ok(None),
+            Err(err) => Err(err),
+        }
+    }
+}
+
+impl Drop for BinderfsProcFile {
+    fn drop(&mut self) {
+        // SAFETY: This is a dentry from `rust_binderfs_remove_file` that has not been deleted yet.
+        unsafe { binderfs::rust_binderfs_remove_file(self.0.as_ptr()) };
+    }
+}
diff --git a/drivers/android/binder/rust_binderfs.c b/drivers/android/binder/rust_binderfs.c
new file mode 100644
index 000000000000..c69026df775c
--- /dev/null
+++ b/drivers/android/binder/rust_binderfs.c
@@ -0,0 +1,795 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <linux/compiler_types.h>
+#include <linux/errno.h>
+#include <linux/fs.h>
+#include <linux/fsnotify.h>
+#include <linux/gfp.h>
+#include <linux/idr.h>
+#include <linux/init.h>
+#include <linux/ipc_namespace.h>
+#include <linux/kdev_t.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/namei.h>
+#include <linux/magic.h>
+#include <linux/major.h>
+#include <linux/miscdevice.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/mount.h>
+#include <linux/fs_parser.h>
+#include <linux/sched.h>
+#include <linux/seq_file.h>
+#include <linux/slab.h>
+#include <linux/spinlock_types.h>
+#include <linux/stddef.h>
+#include <linux/string.h>
+#include <linux/types.h>
+#include <linux/uaccess.h>
+#include <linux/user_namespace.h>
+#include <linux/xarray.h>
+#include <uapi/asm-generic/errno-base.h>
+#include <uapi/linux/android/binder.h>
+#include <uapi/linux/android/binderfs.h>
+
+#include "rust_binder.h"
+#include "rust_binder_internal.h"
+
+#define FIRST_INODE 1
+#define SECOND_INODE 2
+#define INODE_OFFSET 3
+#define BINDERFS_MAX_MINOR (1U << MINORBITS)
+/* Ensure that the initial ipc namespace always has devices available. */
+#define BINDERFS_MAX_MINOR_CAPPED (BINDERFS_MAX_MINOR - 4)
+
+DEFINE_SHOW_ATTRIBUTE(rust_binder_stats);
+DEFINE_SHOW_ATTRIBUTE(rust_binder_state);
+DEFINE_SHOW_ATTRIBUTE(rust_binder_transactions);
+DEFINE_SHOW_ATTRIBUTE(rust_binder_proc);
+
+char *rust_binder_devices_param = CONFIG_ANDROID_BINDER_DEVICES;
+module_param_named(rust_devices, rust_binder_devices_param, charp, 0444);
+
+static dev_t binderfs_dev;
+static DEFINE_MUTEX(binderfs_minors_mutex);
+static DEFINE_IDA(binderfs_minors);
+
+enum binderfs_param {
+	Opt_max,
+	Opt_stats_mode,
+};
+
+enum binderfs_stats_mode {
+	binderfs_stats_mode_unset,
+	binderfs_stats_mode_global,
+};
+
+struct binder_features {
+	bool oneway_spam_detection;
+	bool extended_error;
+	bool freeze_notification;
+};
+
+static const struct constant_table binderfs_param_stats[] = {
+	{ "global", binderfs_stats_mode_global },
+	{}
+};
+
+static const struct fs_parameter_spec binderfs_fs_parameters[] = {
+	fsparam_u32("max",	Opt_max),
+	fsparam_enum("stats",	Opt_stats_mode, binderfs_param_stats),
+	{}
+};
+
+static struct binder_features binder_features = {
+	.oneway_spam_detection = true,
+	.extended_error = true,
+	.freeze_notification = true,
+};
+
+static inline struct binderfs_info *BINDERFS_SB(const struct super_block *sb)
+{
+	return sb->s_fs_info;
+}
+
+/**
+ * binderfs_binder_device_create - allocate inode from super block of a
+ *                                 binderfs mount
+ * @ref_inode: inode from wich the super block will be taken
+ * @userp:     buffer to copy information about new device for userspace to
+ * @req:       struct binderfs_device as copied from userspace
+ *
+ * This function allocates a new binder_device and reserves a new minor
+ * number for it.
+ * Minor numbers are limited and tracked globally in binderfs_minors. The
+ * function will stash a struct binder_device for the specific binder
+ * device in i_private of the inode.
+ * It will go on to allocate a new inode from the super block of the
+ * filesystem mount, stash a struct binder_device in its i_private field
+ * and attach a dentry to that inode.
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+static int binderfs_binder_device_create(struct inode *ref_inode,
+					 struct binderfs_device __user *userp,
+					 struct binderfs_device *req)
+{
+	int minor, ret;
+	struct dentry *dentry, *root;
+	struct binder_device *device = NULL;
+	rust_binder_context ctx = NULL;
+	struct inode *inode = NULL;
+	struct super_block *sb = ref_inode->i_sb;
+	struct binderfs_info *info = sb->s_fs_info;
+#if defined(CONFIG_IPC_NS)
+	bool use_reserve = (info->ipc_ns == &init_ipc_ns);
+#else
+	bool use_reserve = true;
+#endif
+
+	/* Reserve new minor number for the new device. */
+	mutex_lock(&binderfs_minors_mutex);
+	if (++info->device_count <= info->mount_opts.max)
+		minor = ida_alloc_max(&binderfs_minors,
+				      use_reserve ? BINDERFS_MAX_MINOR :
+						    BINDERFS_MAX_MINOR_CAPPED,
+				      GFP_KERNEL);
+	else
+		minor = -ENOSPC;
+	if (minor < 0) {
+		--info->device_count;
+		mutex_unlock(&binderfs_minors_mutex);
+		return minor;
+	}
+	mutex_unlock(&binderfs_minors_mutex);
+
+	ret = -ENOMEM;
+	device = kzalloc(sizeof(*device), GFP_KERNEL);
+	if (!device)
+		goto err;
+
+	req->name[BINDERFS_MAX_NAME] = '\0'; /* NUL-terminate */
+
+	ctx = rust_binder_new_context(req->name);
+	if (!ctx)
+		goto err;
+
+	inode = new_inode(sb);
+	if (!inode)
+		goto err;
+
+	inode->i_ino = minor + INODE_OFFSET;
+	simple_inode_init_ts(inode);
+	init_special_inode(inode, S_IFCHR | 0600,
+			   MKDEV(MAJOR(binderfs_dev), minor));
+	inode->i_fop = &rust_binder_fops;
+	inode->i_uid = info->root_uid;
+	inode->i_gid = info->root_gid;
+
+	req->major = MAJOR(binderfs_dev);
+	req->minor = minor;
+	device->ctx = ctx;
+	device->minor = minor;
+
+	if (userp && copy_to_user(userp, req, sizeof(*req))) {
+		ret = -EFAULT;
+		goto err;
+	}
+
+	root = sb->s_root;
+	dentry = simple_start_creating(root, req->name);
+	if (IS_ERR(dentry)) {
+		ret = PTR_ERR(dentry);
+		goto err;
+	}
+
+	inode->i_private = device;
+	d_make_persistent(dentry, inode);
+
+	fsnotify_create(root->d_inode, dentry);
+	simple_done_creating(dentry);
+
+	return 0;
+
+err:
+	kfree(device);
+	rust_binder_remove_context(ctx);
+	mutex_lock(&binderfs_minors_mutex);
+	--info->device_count;
+	ida_free(&binderfs_minors, minor);
+	mutex_unlock(&binderfs_minors_mutex);
+	iput(inode);
+
+	return ret;
+}
+
+/**
+ * binder_ctl_ioctl - handle binder device node allocation requests
+ *
+ * The request handler for the binder-control device. All requests operate on
+ * the binderfs mount the binder-control device resides in:
+ * - BINDER_CTL_ADD
+ *   Allocate a new binder device.
+ *
+ * Return: %0 on success, negative errno on failure.
+ */
+static long binder_ctl_ioctl(struct file *file, unsigned int cmd,
+			     unsigned long arg)
+{
+	int ret = -EINVAL;
+	struct inode *inode = file_inode(file);
+	struct binderfs_device __user *device = (struct binderfs_device __user *)arg;
+	struct binderfs_device device_req;
+
+	switch (cmd) {
+	case BINDER_CTL_ADD:
+		ret = copy_from_user(&device_req, device, sizeof(device_req));
+		if (ret) {
+			ret = -EFAULT;
+			break;
+		}
+
+		ret = binderfs_binder_device_create(inode, device, &device_req);
+		break;
+	default:
+		break;
+	}
+
+	return ret;
+}
+
+static void binderfs_evict_inode(struct inode *inode)
+{
+	struct binder_device *device = inode->i_private;
+	struct binderfs_info *info = BINDERFS_SB(inode->i_sb);
+
+	clear_inode(inode);
+
+	if (!S_ISCHR(inode->i_mode) || !device)
+		return;
+
+	mutex_lock(&binderfs_minors_mutex);
+	--info->device_count;
+	ida_free(&binderfs_minors, device->minor);
+	mutex_unlock(&binderfs_minors_mutex);
+
+	/* ctx is null for binder-control, but this function ignores null pointers */
+	rust_binder_remove_context(device->ctx);
+
+	kfree(device);
+}
+
+static int binderfs_fs_context_parse_param(struct fs_context *fc,
+					   struct fs_parameter *param)
+{
+	int opt;
+	struct binderfs_mount_opts *ctx = fc->fs_private;
+	struct fs_parse_result result;
+
+	opt = fs_parse(fc, binderfs_fs_parameters, param, &result);
+	if (opt < 0)
+		return opt;
+
+	switch (opt) {
+	case Opt_max:
+		if (result.uint_32 > BINDERFS_MAX_MINOR)
+			return invalfc(fc, "Bad value for '%s'", param->key);
+
+		ctx->max = result.uint_32;
+		break;
+	case Opt_stats_mode:
+		if (!capable(CAP_SYS_ADMIN))
+			return -EPERM;
+
+		ctx->stats_mode = result.uint_32;
+		break;
+	default:
+		return invalfc(fc, "Unsupported parameter '%s'", param->key);
+	}
+
+	return 0;
+}
+
+static int binderfs_fs_context_reconfigure(struct fs_context *fc)
+{
+	struct binderfs_mount_opts *ctx = fc->fs_private;
+	struct binderfs_info *info = BINDERFS_SB(fc->root->d_sb);
+
+	if (info->mount_opts.stats_mode != ctx->stats_mode)
+		return invalfc(fc, "Binderfs stats mode cannot be changed during a remount");
+
+	info->mount_opts.stats_mode = ctx->stats_mode;
+	info->mount_opts.max = ctx->max;
+	return 0;
+}
+
+static int binderfs_show_options(struct seq_file *seq, struct dentry *root)
+{
+	struct binderfs_info *info = BINDERFS_SB(root->d_sb);
+
+	if (info->mount_opts.max <= BINDERFS_MAX_MINOR)
+		seq_printf(seq, ",max=%d", info->mount_opts.max);
+
+	switch (info->mount_opts.stats_mode) {
+	case binderfs_stats_mode_unset:
+		break;
+	case binderfs_stats_mode_global:
+		seq_puts(seq, ",stats=global");
+		break;
+	}
+
+	return 0;
+}
+
+static const struct super_operations binderfs_super_ops = {
+	.evict_inode    = binderfs_evict_inode,
+	.show_options	= binderfs_show_options,
+	.statfs         = simple_statfs,
+};
+
+static inline bool is_binderfs_control_device(const struct dentry *dentry)
+{
+	struct binderfs_info *info = dentry->d_sb->s_fs_info;
+
+	return info->control_dentry == dentry;
+}
+
+static int binderfs_rename(struct mnt_idmap *idmap,
+			   struct inode *old_dir, struct dentry *old_dentry,
+			   struct inode *new_dir, struct dentry *new_dentry,
+			   unsigned int flags)
+{
+	if (is_binderfs_control_device(old_dentry) ||
+	    is_binderfs_control_device(new_dentry))
+		return -EPERM;
+
+	return simple_rename(idmap, old_dir, old_dentry, new_dir,
+			     new_dentry, flags);
+}
+
+static int binderfs_unlink(struct inode *dir, struct dentry *dentry)
+{
+	if (is_binderfs_control_device(dentry))
+		return -EPERM;
+
+	return simple_unlink(dir, dentry);
+}
+
+static const struct file_operations binder_ctl_fops = {
+	.owner		= THIS_MODULE,
+	.open		= nonseekable_open,
+	.unlocked_ioctl	= binder_ctl_ioctl,
+	.compat_ioctl	= binder_ctl_ioctl,
+	.llseek		= noop_llseek,
+};
+
+/**
+ * binderfs_binder_ctl_create - create a new binder-control device
+ * @sb: super block of the binderfs mount
+ *
+ * This function creates a new binder-control device node in the binderfs mount
+ * referred to by @sb.
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+static int binderfs_binder_ctl_create(struct super_block *sb)
+{
+	int minor, ret;
+	struct dentry *dentry;
+	struct binder_device *device;
+	struct inode *inode = NULL;
+	struct dentry *root = sb->s_root;
+	struct binderfs_info *info = sb->s_fs_info;
+#if defined(CONFIG_IPC_NS)
+	bool use_reserve = (info->ipc_ns == &init_ipc_ns);
+#else
+	bool use_reserve = true;
+#endif
+
+	device = kzalloc(sizeof(*device), GFP_KERNEL);
+	if (!device)
+		return -ENOMEM;
+
+	/* If we have already created a binder-control node, return. */
+	if (info->control_dentry) {
+		ret = 0;
+		goto out;
+	}
+
+	ret = -ENOMEM;
+	inode = new_inode(sb);
+	if (!inode)
+		goto out;
+
+	/* Reserve a new minor number for the new device. */
+	mutex_lock(&binderfs_minors_mutex);
+	minor = ida_alloc_max(&binderfs_minors,
+			      use_reserve ? BINDERFS_MAX_MINOR :
+					    BINDERFS_MAX_MINOR_CAPPED,
+			      GFP_KERNEL);
+	mutex_unlock(&binderfs_minors_mutex);
+	if (minor < 0) {
+		ret = minor;
+		goto out;
+	}
+
+	inode->i_ino = SECOND_INODE;
+	simple_inode_init_ts(inode);
+	init_special_inode(inode, S_IFCHR | 0600,
+			   MKDEV(MAJOR(binderfs_dev), minor));
+	inode->i_fop = &binder_ctl_fops;
+	inode->i_uid = info->root_uid;
+	inode->i_gid = info->root_gid;
+
+	device->minor = minor;
+	device->ctx = NULL;
+
+	dentry = d_alloc_name(root, "binder-control");
+	if (!dentry)
+		goto out;
+
+	inode->i_private = device;
+	info->control_dentry = dentry;
+	d_add(dentry, inode);
+
+	return 0;
+
+out:
+	kfree(device);
+	iput(inode);
+
+	return ret;
+}
+
+static const struct inode_operations binderfs_dir_inode_operations = {
+	.lookup = simple_lookup,
+	.rename = binderfs_rename,
+	.unlink = binderfs_unlink,
+};
+
+static struct inode *binderfs_make_inode(struct super_block *sb, int mode)
+{
+	struct inode *ret;
+
+	ret = new_inode(sb);
+	if (ret) {
+		ret->i_ino = iunique(sb, BINDERFS_MAX_MINOR + INODE_OFFSET);
+		ret->i_mode = mode;
+		simple_inode_init_ts(ret);
+	}
+	return ret;
+}
+
+void rust_binderfs_remove_file(struct dentry *dentry)
+{
+	simple_recursive_removal(dentry, NULL);
+}
+
+static struct dentry *rust_binderfs_create_file(struct dentry *parent, const char *name,
+						const struct file_operations *fops,
+						void *data)
+{
+	struct dentry *dentry;
+	struct inode *new_inode;
+
+	new_inode = binderfs_make_inode(parent->d_sb, S_IFREG | 0444);
+	if (!new_inode)
+		return ERR_PTR(-ENOMEM);
+	new_inode->i_fop = fops;
+	new_inode->i_private = data;
+
+	dentry = simple_start_creating(parent, name);
+	if (IS_ERR(dentry)) {
+		iput(new_inode);
+		return dentry;
+	}
+
+	d_make_persistent(dentry, new_inode);
+	fsnotify_create(parent->d_inode, dentry);
+	simple_done_creating(dentry);
+	return dentry;
+}
+
+struct dentry *rust_binderfs_create_proc_file(struct inode *nodp, int pid)
+{
+	struct binderfs_info *info = nodp->i_sb->s_fs_info;
+	struct dentry *dir = info->proc_log_dir;
+	char strbuf[20 + 1];
+	void *data = (void *)(unsigned long) pid;
+
+	if (!dir)
+		return NULL;
+
+	snprintf(strbuf, sizeof(strbuf), "%u", pid);
+	return rust_binderfs_create_file(dir, strbuf, &rust_binder_proc_fops, data);
+}
+
+static struct dentry *binderfs_create_dir(struct dentry *parent,
+					  const char *name)
+{
+	struct dentry *dentry;
+	struct inode *new_inode;
+
+	new_inode = binderfs_make_inode(parent->d_sb, S_IFDIR | 0755);
+	if (!new_inode)
+		return ERR_PTR(-ENOMEM);
+
+	new_inode->i_fop = &simple_dir_operations;
+	new_inode->i_op = &simple_dir_inode_operations;
+
+	dentry = simple_start_creating(parent, name);
+	if (IS_ERR(dentry)) {
+		iput(new_inode);
+		return dentry;
+	}
+
+	inc_nlink(parent->d_inode);
+	set_nlink(new_inode, 2);
+	d_make_persistent(dentry, new_inode);
+	fsnotify_mkdir(parent->d_inode, dentry);
+	simple_done_creating(dentry);
+	return dentry;
+}
+
+static int binder_features_show(struct seq_file *m, void *unused)
+{
+	bool *feature = m->private;
+
+	seq_printf(m, "%d\n", *feature);
+
+	return 0;
+}
+DEFINE_SHOW_ATTRIBUTE(binder_features);
+
+static int init_binder_features(struct super_block *sb)
+{
+	struct dentry *dentry, *dir;
+
+	dir = binderfs_create_dir(sb->s_root, "features");
+	if (IS_ERR(dir))
+		return PTR_ERR(dir);
+
+	dentry = rust_binderfs_create_file(dir, "oneway_spam_detection",
+				      &binder_features_fops,
+				      &binder_features.oneway_spam_detection);
+	if (IS_ERR(dentry))
+		return PTR_ERR(dentry);
+
+	dentry = rust_binderfs_create_file(dir, "extended_error",
+				      &binder_features_fops,
+				      &binder_features.extended_error);
+	if (IS_ERR(dentry))
+		return PTR_ERR(dentry);
+
+	dentry = rust_binderfs_create_file(dir, "freeze_notification",
+				      &binder_features_fops,
+				      &binder_features.freeze_notification);
+	if (IS_ERR(dentry))
+		return PTR_ERR(dentry);
+
+	return 0;
+}
+
+static int init_binder_logs(struct super_block *sb)
+{
+	struct dentry *binder_logs_root_dir, *dentry, *proc_log_dir;
+	struct binderfs_info *info;
+	int ret = 0;
+
+	binder_logs_root_dir = binderfs_create_dir(sb->s_root,
+						   "binder_logs");
+	if (IS_ERR(binder_logs_root_dir)) {
+		ret = PTR_ERR(binder_logs_root_dir);
+		goto out;
+	}
+
+	dentry = rust_binderfs_create_file(binder_logs_root_dir, "stats",
+				      &rust_binder_stats_fops, NULL);
+	if (IS_ERR(dentry)) {
+		ret = PTR_ERR(dentry);
+		goto out;
+	}
+
+	dentry = rust_binderfs_create_file(binder_logs_root_dir, "state",
+				      &rust_binder_state_fops, NULL);
+	if (IS_ERR(dentry)) {
+		ret = PTR_ERR(dentry);
+		goto out;
+	}
+
+	dentry = rust_binderfs_create_file(binder_logs_root_dir, "transactions",
+				      &rust_binder_transactions_fops, NULL);
+	if (IS_ERR(dentry)) {
+		ret = PTR_ERR(dentry);
+		goto out;
+	}
+
+	proc_log_dir = binderfs_create_dir(binder_logs_root_dir, "proc");
+	if (IS_ERR(proc_log_dir)) {
+		ret = PTR_ERR(proc_log_dir);
+		goto out;
+	}
+	info = sb->s_fs_info;
+	info->proc_log_dir = proc_log_dir;
+
+out:
+	return ret;
+}
+
+static int binderfs_fill_super(struct super_block *sb, struct fs_context *fc)
+{
+	int ret;
+	struct binderfs_info *info;
+	struct binderfs_mount_opts *ctx = fc->fs_private;
+	struct inode *inode = NULL;
+	struct binderfs_device device_info = {};
+	const char *name;
+	size_t len;
+
+	sb->s_blocksize = PAGE_SIZE;
+	sb->s_blocksize_bits = PAGE_SHIFT;
+
+	/*
+	 * The binderfs filesystem can be mounted by userns root in a
+	 * non-initial userns. By default such mounts have the SB_I_NODEV flag
+	 * set in s_iflags to prevent security issues where userns root can
+	 * just create random device nodes via mknod() since it owns the
+	 * filesystem mount. But binderfs does not allow to create any files
+	 * including devices nodes. The only way to create binder devices nodes
+	 * is through the binder-control device which userns root is explicitly
+	 * allowed to do. So removing the SB_I_NODEV flag from s_iflags is both
+	 * necessary and safe.
+	 */
+	sb->s_iflags &= ~SB_I_NODEV;
+	sb->s_iflags |= SB_I_NOEXEC;
+	sb->s_magic = RUST_BINDERFS_SUPER_MAGIC;
+	sb->s_op = &binderfs_super_ops;
+	sb->s_time_gran = 1;
+
+	sb->s_fs_info = kzalloc(sizeof(struct binderfs_info), GFP_KERNEL);
+	if (!sb->s_fs_info)
+		return -ENOMEM;
+	info = sb->s_fs_info;
+
+	info->ipc_ns = get_ipc_ns(current->nsproxy->ipc_ns);
+
+	info->root_gid = make_kgid(sb->s_user_ns, 0);
+	if (!gid_valid(info->root_gid))
+		info->root_gid = GLOBAL_ROOT_GID;
+	info->root_uid = make_kuid(sb->s_user_ns, 0);
+	if (!uid_valid(info->root_uid))
+		info->root_uid = GLOBAL_ROOT_UID;
+	info->mount_opts.max = ctx->max;
+	info->mount_opts.stats_mode = ctx->stats_mode;
+
+	inode = new_inode(sb);
+	if (!inode)
+		return -ENOMEM;
+
+	inode->i_ino = FIRST_INODE;
+	inode->i_fop = &simple_dir_operations;
+	inode->i_mode = S_IFDIR | 0755;
+	simple_inode_init_ts(inode);
+	inode->i_op = &binderfs_dir_inode_operations;
+	set_nlink(inode, 2);
+
+	sb->s_root = d_make_root(inode);
+	if (!sb->s_root)
+		return -ENOMEM;
+
+	ret = binderfs_binder_ctl_create(sb);
+	if (ret)
+		return ret;
+
+	name = rust_binder_devices_param;
+	for (len = strcspn(name, ","); len > 0; len = strcspn(name, ",")) {
+		strscpy(device_info.name, name, len + 1);
+		ret = binderfs_binder_device_create(inode, NULL, &device_info);
+		if (ret)
+			return ret;
+		name += len;
+		if (*name == ',')
+			name++;
+	}
+
+	ret = init_binder_features(sb);
+	if (ret)
+		return ret;
+
+	if (info->mount_opts.stats_mode == binderfs_stats_mode_global)
+		return init_binder_logs(sb);
+
+	return 0;
+}
+
+static int binderfs_fs_context_get_tree(struct fs_context *fc)
+{
+	return get_tree_nodev(fc, binderfs_fill_super);
+}
+
+static void binderfs_fs_context_free(struct fs_context *fc)
+{
+	struct binderfs_mount_opts *ctx = fc->fs_private;
+
+	kfree(ctx);
+}
+
+static const struct fs_context_operations binderfs_fs_context_ops = {
+	.free		= binderfs_fs_context_free,
+	.get_tree	= binderfs_fs_context_get_tree,
+	.parse_param	= binderfs_fs_context_parse_param,
+	.reconfigure	= binderfs_fs_context_reconfigure,
+};
+
+static int binderfs_init_fs_context(struct fs_context *fc)
+{
+	struct binderfs_mount_opts *ctx;
+
+	ctx = kzalloc(sizeof(struct binderfs_mount_opts), GFP_KERNEL);
+	if (!ctx)
+		return -ENOMEM;
+
+	ctx->max = BINDERFS_MAX_MINOR;
+	ctx->stats_mode = binderfs_stats_mode_unset;
+
+	fc->fs_private = ctx;
+	fc->ops = &binderfs_fs_context_ops;
+
+	return 0;
+}
+
+static void binderfs_kill_super(struct super_block *sb)
+{
+	struct binderfs_info *info = sb->s_fs_info;
+
+	/*
+	 * During inode eviction struct binderfs_info is needed.
+	 * So first wipe the super_block then free struct binderfs_info.
+	 */
+	kill_anon_super(sb);
+
+	if (info && info->ipc_ns)
+		put_ipc_ns(info->ipc_ns);
+
+	kfree(info);
+}
+
+static struct file_system_type binder_fs_type = {
+	.name			= "binder",
+	.init_fs_context	= binderfs_init_fs_context,
+	.parameters		= binderfs_fs_parameters,
+	.kill_sb		= binderfs_kill_super,
+	.fs_flags		= FS_USERNS_MOUNT,
+};
+
+int init_rust_binderfs(void)
+{
+	int ret;
+	const char *name;
+	size_t len;
+
+	/* Verify that the default binderfs device names are valid. */
+	name = rust_binder_devices_param;
+	for (len = strcspn(name, ","); len > 0; len = strcspn(name, ",")) {
+		if (len > BINDERFS_MAX_NAME)
+			return -E2BIG;
+		name += len;
+		if (*name == ',')
+			name++;
+	}
+
+	/* Allocate new major number for binderfs. */
+	ret = alloc_chrdev_region(&binderfs_dev, 0, BINDERFS_MAX_MINOR,
+				  "rust_binder");
+	if (ret)
+		return ret;
+
+	ret = register_filesystem(&binder_fs_type);
+	if (ret) {
+		unregister_chrdev_region(binderfs_dev, BINDERFS_MAX_MINOR);
+		return ret;
+	}
+
+	return ret;
+}
diff --git a/drivers/android/binder/stats.rs b/drivers/android/binder/stats.rs
new file mode 100644
index 000000000000..037002651941
--- /dev/null
+++ b/drivers/android/binder/stats.rs
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0
+
+// Copyright (C) 2025 Google LLC.
+
+//! Keep track of statistics for binder_logs.
+
+use crate::defs::*;
+use core::sync::atomic::{AtomicU32, Ordering::Relaxed};
+use kernel::{ioctl::_IOC_NR, seq_file::SeqFile, seq_print};
+
+const BC_COUNT: usize = _IOC_NR(BC_REPLY_SG) as usize + 1;
+const BR_COUNT: usize = _IOC_NR(BR_TRANSACTION_PENDING_FROZEN) as usize + 1;
+
+pub(crate) static GLOBAL_STATS: BinderStats = BinderStats::new();
+
+pub(crate) struct BinderStats {
+    bc: [AtomicU32; BC_COUNT],
+    br: [AtomicU32; BR_COUNT],
+}
+
+impl BinderStats {
+    pub(crate) const fn new() -> Self {
+        #[expect(clippy::declare_interior_mutable_const)]
+        const ZERO: AtomicU32 = AtomicU32::new(0);
+
+        Self {
+            bc: [ZERO; BC_COUNT],
+            br: [ZERO; BR_COUNT],
+        }
+    }
+
+    pub(crate) fn inc_bc(&self, bc: u32) {
+        let idx = _IOC_NR(bc) as usize;
+        if let Some(bc_ref) = self.bc.get(idx) {
+            bc_ref.fetch_add(1, Relaxed);
+        }
+    }
+
+    pub(crate) fn inc_br(&self, br: u32) {
+        let idx = _IOC_NR(br) as usize;
+        if let Some(br_ref) = self.br.get(idx) {
+            br_ref.fetch_add(1, Relaxed);
+        }
+    }
+
+    pub(crate) fn debug_print(&self, prefix: &str, m: &SeqFile) {
+        for (i, cnt) in self.bc.iter().enumerate() {
+            let cnt = cnt.load(Relaxed);
+            if cnt > 0 {
+                seq_print!(m, "{}{}: {}\n", prefix, command_string(i), cnt);
+            }
+        }
+        for (i, cnt) in self.br.iter().enumerate() {
+            let cnt = cnt.load(Relaxed);
+            if cnt > 0 {
+                seq_print!(m, "{}{}: {}\n", prefix, return_string(i), cnt);
+            }
+        }
+    }
+}
+
+mod strings {
+    use core::str::from_utf8_unchecked;
+    use kernel::str::{CStr, CStrExt as _};
+
+    extern "C" {
+        static binder_command_strings: [*const u8; super::BC_COUNT];
+        static binder_return_strings: [*const u8; super::BR_COUNT];
+    }
+
+    pub(super) fn command_string(i: usize) -> &'static str {
+        // SAFETY: Accessing `binder_command_strings` is always safe.
+        let c_str_ptr = unsafe { binder_command_strings[i] };
+        // SAFETY: The `binder_command_strings` array only contains nul-terminated strings.
+        let bytes = unsafe { CStr::from_char_ptr(c_str_ptr) }.to_bytes();
+        // SAFETY: The `binder_command_strings` array only contains strings with ascii-chars.
+        unsafe { from_utf8_unchecked(bytes) }
+    }
+
+    pub(super) fn return_string(i: usize) -> &'static str {
+        // SAFETY: Accessing `binder_return_strings` is always safe.
+        let c_str_ptr = unsafe { binder_return_strings[i] };
+        // SAFETY: The `binder_command_strings` array only contains nul-terminated strings.
+        let bytes = unsafe { CStr::from_char_ptr(c_str_ptr) }.to_bytes();
+        // SAFETY: The `binder_command_strings` array only contains strings with ascii-chars.
+        unsafe { from_utf8_unchecked(bytes) }
+    }
+}
+use strings::{command_string, return_string};
diff --git a/drivers/android/binder/thread.rs b/drivers/android/binder/thread.rs
new file mode 100644
index 000000000000..1a8e6fdc0dc4
--- /dev/null
+++ b/drivers/android/binder/thread.rs
@@ -0,0 +1,1596 @@
+// SPDX-License-Identifier: GPL-2.0
+
+// Copyright (C) 2025 Google LLC.
+
+//! This module defines the `Thread` type, which represents a userspace thread that is using
+//! binder.
+//!
+//! The `Process` object stores all of the threads in an rb tree.
+
+use kernel::{
+    bindings,
+    fs::{File, LocalFile},
+    list::{AtomicTracker, List, ListArc, ListLinks, TryNewListArc},
+    prelude::*,
+    security,
+    seq_file::SeqFile,
+    seq_print,
+    sync::poll::{PollCondVar, PollTable},
+    sync::{Arc, SpinLock},
+    task::Task,
+    types::ARef,
+    uaccess::UserSlice,
+    uapi,
+};
+
+use crate::{
+    allocation::{Allocation, AllocationView, BinderObject, BinderObjectRef, NewAllocation},
+    defs::*,
+    error::BinderResult,
+    process::{GetWorkOrRegister, Process},
+    ptr_align,
+    stats::GLOBAL_STATS,
+    transaction::Transaction,
+    BinderReturnWriter, DArc, DLArc, DTRWrap, DeliverCode, DeliverToRead,
+};
+
+use core::{
+    mem::size_of,
+    sync::atomic::{AtomicU32, Ordering},
+};
+
+/// Stores the layout of the scatter-gather entries. This is used during the `translate_objects`
+/// call and is discarded when it returns.
+struct ScatterGatherState {
+    /// A struct that tracks the amount of unused buffer space.
+    unused_buffer_space: UnusedBufferSpace,
+    /// Scatter-gather entries to copy.
+    sg_entries: KVec<ScatterGatherEntry>,
+    /// Indexes into `sg_entries` corresponding to the last binder_buffer_object that
+    /// was processed and all of its ancestors. The array is in sorted order.
+    ancestors: KVec<usize>,
+}
+
+/// This entry specifies an additional buffer that should be copied using the scatter-gather
+/// mechanism.
+struct ScatterGatherEntry {
+    /// The index in the offset array of the BINDER_TYPE_PTR that this entry originates from.
+    obj_index: usize,
+    /// Offset in target buffer.
+    offset: usize,
+    /// User address in source buffer.
+    sender_uaddr: usize,
+    /// Number of bytes to copy.
+    length: usize,
+    /// The minimum offset of the next fixup in this buffer.
+    fixup_min_offset: usize,
+    /// The offsets within this buffer that contain pointers which should be translated.
+    pointer_fixups: KVec<PointerFixupEntry>,
+}
+
+/// This entry specifies that a fixup should happen at `target_offset` of the
+/// buffer. If `skip` is nonzero, then the fixup is a `binder_fd_array_object`
+/// and is applied later. Otherwise if `skip` is zero, then the size of the
+/// fixup is `sizeof::<u64>()` and `pointer_value` is written to the buffer.
+struct PointerFixupEntry {
+    /// The number of bytes to skip, or zero for a `binder_buffer_object` fixup.
+    skip: usize,
+    /// The translated pointer to write when `skip` is zero.
+    pointer_value: u64,
+    /// The offset at which the value should be written. The offset is relative
+    /// to the original buffer.
+    target_offset: usize,
+}
+
+/// Return type of `apply_and_validate_fixup_in_parent`.
+struct ParentFixupInfo {
+    /// The index of the parent buffer in `sg_entries`.
+    parent_sg_index: usize,
+    /// The number of ancestors of the buffer.
+    ///
+    /// The buffer is considered an ancestor of itself, so this is always at
+    /// least one.
+    num_ancestors: usize,
+    /// New value of `fixup_min_offset` if this fixup is applied.
+    new_min_offset: usize,
+    /// The offset of the fixup in the target buffer.
+    target_offset: usize,
+}
+
+impl ScatterGatherState {
+    /// Called when a `binder_buffer_object` or `binder_fd_array_object` tries
+    /// to access a region in its parent buffer. These accesses have various
+    /// restrictions, which this method verifies.
+    ///
+    /// The `parent_offset` and `length` arguments describe the offset and
+    /// length of the access in the parent buffer.
+    ///
+    /// # Detailed restrictions
+    ///
+    /// Obviously the fixup must be in-bounds for the parent buffer.
+    ///
+    /// For safety reasons, we only allow fixups inside a buffer to happen
+    /// at increasing offsets; additionally, we only allow fixup on the last
+    /// buffer object that was verified, or one of its parents.
+    ///
+    /// Example of what is allowed:
+    ///
+    /// A
+    ///   B (parent = A, offset = 0)
+    ///   C (parent = A, offset = 16)
+    ///     D (parent = C, offset = 0)
+    ///   E (parent = A, offset = 32) // min_offset is 16 (C.parent_offset)
+    ///
+    /// Examples of what is not allowed:
+    ///
+    /// Decreasing offsets within the same parent:
+    /// A
+    ///   C (parent = A, offset = 16)
+    ///   B (parent = A, offset = 0) // decreasing offset within A
+    ///
+    /// Arcerring to a parent that wasn't the last object or any of its parents:
+    /// A
+    ///   B (parent = A, offset = 0)
+    ///   C (parent = A, offset = 0)
+    ///   C (parent = A, offset = 16)
+    ///     D (parent = B, offset = 0) // B is not A or any of A's parents
+    fn validate_parent_fixup(
+        &self,
+        parent: usize,
+        parent_offset: usize,
+        length: usize,
+    ) -> Result<ParentFixupInfo> {
+        // Using `position` would also be correct, but `rposition` avoids
+        // quadratic running times.
+        let ancestors_i = self
+            .ancestors
+            .iter()
+            .copied()
+            .rposition(|sg_idx| self.sg_entries[sg_idx].obj_index == parent)
+            .ok_or(EINVAL)?;
+        let sg_idx = self.ancestors[ancestors_i];
+        let sg_entry = match self.sg_entries.get(sg_idx) {
+            Some(sg_entry) => sg_entry,
+            None => {
+                pr_err!(
+                    "self.ancestors[{}] is {}, but self.sg_entries.len() is {}",
+                    ancestors_i,
+                    sg_idx,
+                    self.sg_entries.len()
+                );
+                return Err(EINVAL);
+            }
+        };
+        if sg_entry.fixup_min_offset > parent_offset {
+            pr_warn!(
+                "validate_parent_fixup: fixup_min_offset={}, parent_offset={}",
+                sg_entry.fixup_min_offset,
+                parent_offset
+            );
+            return Err(EINVAL);
+        }
+        let new_min_offset = parent_offset.checked_add(length).ok_or(EINVAL)?;
+        if new_min_offset > sg_entry.length {
+            pr_warn!(
+                "validate_parent_fixup: new_min_offset={}, sg_entry.length={}",
+                new_min_offset,
+                sg_entry.length
+            );
+            return Err(EINVAL);
+        }
+        let target_offset = sg_entry.offset.checked_add(parent_offset).ok_or(EINVAL)?;
+        // The `ancestors_i + 1` operation can't overflow since the output of the addition is at
+        // most `self.ancestors.len()`, which also fits in a usize.
+        Ok(ParentFixupInfo {
+            parent_sg_index: sg_idx,
+            num_ancestors: ancestors_i + 1,
+            new_min_offset,
+            target_offset,
+        })
+    }
+}
+
+/// Keeps track of how much unused buffer space is left. The initial amount is the number of bytes
+/// requested by the user using the `buffers_size` field of `binder_transaction_data_sg`. Each time
+/// we translate an object of type `BINDER_TYPE_PTR`, some of the unused buffer space is consumed.
+struct UnusedBufferSpace {
+    /// The start of the remaining space.
+    offset: usize,
+    /// The end of the remaining space.
+    limit: usize,
+}
+impl UnusedBufferSpace {
+    /// Claim the next `size` bytes from the unused buffer space. The offset for the claimed chunk
+    /// into the buffer is returned.
+    fn claim_next(&mut self, size: usize) -> Result<usize> {
+        // We require every chunk to be aligned.
+        let size = ptr_align(size).ok_or(EINVAL)?;
+        let new_offset = self.offset.checked_add(size).ok_or(EINVAL)?;
+
+        if new_offset <= self.limit {
+            let offset = self.offset;
+            self.offset = new_offset;
+            Ok(offset)
+        } else {
+            Err(EINVAL)
+        }
+    }
+}
+
+pub(crate) enum PushWorkRes {
+    Ok,
+    FailedDead(DLArc<dyn DeliverToRead>),
+}
+
+impl PushWorkRes {
+    fn is_ok(&self) -> bool {
+        match self {
+            PushWorkRes::Ok => true,
+            PushWorkRes::FailedDead(_) => false,
+        }
+    }
+}
+
+/// The fields of `Thread` protected by the spinlock.
+struct InnerThread {
+    /// Determines the looper state of the thread. It is a bit-wise combination of the constants
+    /// prefixed with `LOOPER_`.
+    looper_flags: u32,
+
+    /// Determines whether the looper should return.
+    looper_need_return: bool,
+
+    /// Determines if thread is dead.
+    is_dead: bool,
+
+    /// Work item used to deliver error codes to the thread that started a transaction. Stored here
+    /// so that it can be reused.
+    reply_work: DArc<ThreadError>,
+
+    /// Work item used to deliver error codes to the current thread. Stored here so that it can be
+    /// reused.
+    return_work: DArc<ThreadError>,
+
+    /// Determines whether the work list below should be processed. When set to false, `work_list`
+    /// is treated as if it were empty.
+    process_work_list: bool,
+    /// List of work items to deliver to userspace.
+    work_list: List<DTRWrap<dyn DeliverToRead>>,
+    current_transaction: Option<DArc<Transaction>>,
+
+    /// Extended error information for this thread.
+    extended_error: ExtendedError,
+}
+
+const LOOPER_REGISTERED: u32 = 0x01;
+const LOOPER_ENTERED: u32 = 0x02;
+const LOOPER_EXITED: u32 = 0x04;
+const LOOPER_INVALID: u32 = 0x08;
+const LOOPER_WAITING: u32 = 0x10;
+const LOOPER_WAITING_PROC: u32 = 0x20;
+const LOOPER_POLL: u32 = 0x40;
+
+impl InnerThread {
+    fn new() -> Result<Self> {
+        fn next_err_id() -> u32 {
+            static EE_ID: AtomicU32 = AtomicU32::new(0);
+            EE_ID.fetch_add(1, Ordering::Relaxed)
+        }
+
+        Ok(Self {
+            looper_flags: 0,
+            looper_need_return: false,
+            is_dead: false,
+            process_work_list: false,
+            reply_work: ThreadError::try_new()?,
+            return_work: ThreadError::try_new()?,
+            work_list: List::new(),
+            current_transaction: None,
+            extended_error: ExtendedError::new(next_err_id(), BR_OK, 0),
+        })
+    }
+
+    fn pop_work(&mut self) -> Option<DLArc<dyn DeliverToRead>> {
+        if !self.process_work_list {
+            return None;
+        }
+
+        let ret = self.work_list.pop_front();
+        self.process_work_list = !self.work_list.is_empty();
+        ret
+    }
+
+    fn push_work(&mut self, work: DLArc<dyn DeliverToRead>) -> PushWorkRes {
+        if self.is_dead {
+            PushWorkRes::FailedDead(work)
+        } else {
+            self.work_list.push_back(work);
+            self.process_work_list = true;
+            PushWorkRes::Ok
+        }
+    }
+
+    fn push_reply_work(&mut self, code: u32) {
+        if let Ok(work) = ListArc::try_from_arc(self.reply_work.clone()) {
+            work.set_error_code(code);
+            self.push_work(work);
+        } else {
+            pr_warn!("Thread reply work is already in use.");
+        }
+    }
+
+    fn push_return_work(&mut self, reply: u32) {
+        if let Ok(work) = ListArc::try_from_arc(self.return_work.clone()) {
+            work.set_error_code(reply);
+            self.push_work(work);
+        } else {
+            pr_warn!("Thread return work is already in use.");
+        }
+    }
+
+    /// Used to push work items that do not need to be processed immediately and can wait until the
+    /// thread gets another work item.
+    fn push_work_deferred(&mut self, work: DLArc<dyn DeliverToRead>) {
+        self.work_list.push_back(work);
+    }
+
+    /// Fetches the transaction this thread can reply to. If the thread has a pending transaction
+    /// (that it could respond to) but it has also issued a transaction, it must first wait for the
+    /// previously-issued transaction to complete.
+    ///
+    /// The `thread` parameter should be the thread containing this `ThreadInner`.
+    fn pop_transaction_to_reply(&mut self, thread: &Thread) -> Result<DArc<Transaction>> {
+        let transaction = self.current_transaction.take().ok_or(EINVAL)?;
+        if core::ptr::eq(thread, transaction.from.as_ref()) {
+            self.current_transaction = Some(transaction);
+            return Err(EINVAL);
+        }
+        // Find a new current transaction for this thread.
+        self.current_transaction = transaction.find_from(thread).cloned();
+        Ok(transaction)
+    }
+
+    fn pop_transaction_replied(&mut self, transaction: &DArc<Transaction>) -> bool {
+        match self.current_transaction.take() {
+            None => false,
+            Some(old) => {
+                if !Arc::ptr_eq(transaction, &old) {
+                    self.current_transaction = Some(old);
+                    return false;
+                }
+                self.current_transaction = old.clone_next();
+                true
+            }
+        }
+    }
+
+    fn looper_enter(&mut self) {
+        self.looper_flags |= LOOPER_ENTERED;
+        if self.looper_flags & LOOPER_REGISTERED != 0 {
+            self.looper_flags |= LOOPER_INVALID;
+        }
+    }
+
+    fn looper_register(&mut self, valid: bool) {
+        self.looper_flags |= LOOPER_REGISTERED;
+        if !valid || self.looper_flags & LOOPER_ENTERED != 0 {
+            self.looper_flags |= LOOPER_INVALID;
+        }
+    }
+
+    fn looper_exit(&mut self) {
+        self.looper_flags |= LOOPER_EXITED;
+    }
+
+    /// Determines whether the thread is part of a pool, i.e., if it is a looper.
+    fn is_looper(&self) -> bool {
+        self.looper_flags & (LOOPER_ENTERED | LOOPER_REGISTERED) != 0
+    }
+
+    /// Determines whether the thread should attempt to fetch work items from the process queue.
+    /// This is generally case when the thread is registered as a looper and not part of a
+    /// transaction stack. But if there is local work, we want to return to userspace before we
+    /// deliver any remote work.
+    fn should_use_process_work_queue(&self) -> bool {
+        self.current_transaction.is_none() && !self.process_work_list && self.is_looper()
+    }
+
+    fn poll(&mut self) -> u32 {
+        self.looper_flags |= LOOPER_POLL;
+        if self.process_work_list || self.looper_need_return {
+            bindings::POLLIN
+        } else {
+            0
+        }
+    }
+}
+
+/// This represents a thread that's used with binder.
+#[pin_data]
+pub(crate) struct Thread {
+    pub(crate) id: i32,
+    pub(crate) process: Arc<Process>,
+    pub(crate) task: ARef<Task>,
+    #[pin]
+    inner: SpinLock<InnerThread>,
+    #[pin]
+    work_condvar: PollCondVar,
+    /// Used to insert this thread into the process' `ready_threads` list.
+    ///
+    /// INVARIANT: May never be used for any other list than the `self.process.ready_threads`.
+    #[pin]
+    links: ListLinks,
+    #[pin]
+    links_track: AtomicTracker,
+}
+
+kernel::list::impl_list_arc_safe! {
+    impl ListArcSafe<0> for Thread {
+        tracked_by links_track: AtomicTracker;
+    }
+}
+kernel::list::impl_list_item! {
+    impl ListItem<0> for Thread {
+        using ListLinks { self.links };
+    }
+}
+
+impl Thread {
+    pub(crate) fn new(id: i32, process: Arc<Process>) -> Result<Arc<Self>> {
+        let inner = InnerThread::new()?;
+
+        Arc::pin_init(
+            try_pin_init!(Thread {
+                id,
+                process,
+                task: ARef::from(&**kernel::current!()),
+                inner <- kernel::new_spinlock!(inner, "Thread::inner"),
+                work_condvar <- kernel::new_poll_condvar!("Thread::work_condvar"),
+                links <- ListLinks::new(),
+                links_track <- AtomicTracker::new(),
+            }),
+            GFP_KERNEL,
+        )
+    }
+
+    #[inline(never)]
+    pub(crate) fn debug_print(self: &Arc<Self>, m: &SeqFile, print_all: bool) -> Result<()> {
+        let inner = self.inner.lock();
+
+        if print_all || inner.current_transaction.is_some() || !inner.work_list.is_empty() {
+            seq_print!(
+                m,
+                "  thread {}: l {:02x} need_return {}\n",
+                self.id,
+                inner.looper_flags,
+                inner.looper_need_return,
+            );
+        }
+
+        let mut t_opt = inner.current_transaction.as_ref();
+        while let Some(t) = t_opt {
+            if Arc::ptr_eq(&t.from, self) {
+                t.debug_print_inner(m, "    outgoing transaction ");
+                t_opt = t.from_parent.as_ref();
+            } else if Arc::ptr_eq(&t.to, &self.process) {
+                t.debug_print_inner(m, "    incoming transaction ");
+                t_opt = t.find_from(self);
+            } else {
+                t.debug_print_inner(m, "    bad transaction ");
+                t_opt = None;
+            }
+        }
+
+        for work in &inner.work_list {
+            work.debug_print(m, "    ", "    pending transaction ")?;
+        }
+        Ok(())
+    }
+
+    pub(crate) fn get_extended_error(&self, data: UserSlice) -> Result {
+        let mut writer = data.writer();
+        let ee = self.inner.lock().extended_error;
+        writer.write(&ee)?;
+        Ok(())
+    }
+
+    pub(crate) fn set_current_transaction(&self, transaction: DArc<Transaction>) {
+        self.inner.lock().current_transaction = Some(transaction);
+    }
+
+    pub(crate) fn has_current_transaction(&self) -> bool {
+        self.inner.lock().current_transaction.is_some()
+    }
+
+    /// Attempts to fetch a work item from the thread-local queue. The behaviour if the queue is
+    /// empty depends on `wait`: if it is true, the function waits for some work to be queued (or a
+    /// signal); otherwise it returns indicating that none is available.
+    fn get_work_local(self: &Arc<Self>, wait: bool) -> Result<Option<DLArc<dyn DeliverToRead>>> {
+        {
+            let mut inner = self.inner.lock();
+            if inner.looper_need_return {
+                return Ok(inner.pop_work());
+            }
+        }
+
+        // Try once if the caller does not want to wait.
+        if !wait {
+            return self.inner.lock().pop_work().ok_or(EAGAIN).map(Some);
+        }
+
+        // Loop waiting only on the local queue (i.e., not registering with the process queue).
+        let mut inner = self.inner.lock();
+        loop {
+            if let Some(work) = inner.pop_work() {
+                return Ok(Some(work));
+            }
+
+            inner.looper_flags |= LOOPER_WAITING;
+            let signal_pending = self.work_condvar.wait_interruptible_freezable(&mut inner);
+            inner.looper_flags &= !LOOPER_WAITING;
+
+            if signal_pending {
+                return Err(EINTR);
+            }
+            if inner.looper_need_return {
+                return Ok(None);
+            }
+        }
+    }
+
+    /// Attempts to fetch a work item from the thread-local queue, falling back to the process-wide
+    /// queue if none is available locally.
+    ///
+    /// This must only be called when the thread is not participating in a transaction chain. If it
+    /// is, the local version (`get_work_local`) should be used instead.
+    fn get_work(self: &Arc<Self>, wait: bool) -> Result<Option<DLArc<dyn DeliverToRead>>> {
+        // Try to get work from the thread's work queue, using only a local lock.
+        {
+            let mut inner = self.inner.lock();
+            if let Some(work) = inner.pop_work() {
+                return Ok(Some(work));
+            }
+            if inner.looper_need_return {
+                drop(inner);
+                return Ok(self.process.get_work());
+            }
+        }
+
+        // If the caller doesn't want to wait, try to grab work from the process queue.
+        //
+        // We know nothing will have been queued directly to the thread queue because it is not in
+        // a transaction and it is not in the process' ready list.
+        if !wait {
+            return self.process.get_work().ok_or(EAGAIN).map(Some);
+        }
+
+        // Get work from the process queue. If none is available, atomically register as ready.
+        let reg = match self.process.get_work_or_register(self) {
+            GetWorkOrRegister::Work(work) => return Ok(Some(work)),
+            GetWorkOrRegister::Register(reg) => reg,
+        };
+
+        let mut inner = self.inner.lock();
+        loop {
+            if let Some(work) = inner.pop_work() {
+                return Ok(Some(work));
+            }
+
+            inner.looper_flags |= LOOPER_WAITING | LOOPER_WAITING_PROC;
+            let signal_pending = self.work_condvar.wait_interruptible_freezable(&mut inner);
+            inner.looper_flags &= !(LOOPER_WAITING | LOOPER_WAITING_PROC);
+
+            if signal_pending || inner.looper_need_return {
+                // We need to return now. We need to pull the thread off the list of ready threads
+                // (by dropping `reg`), then check the state again after it's off the list to
+                // ensure that something was not queued in the meantime. If something has been
+                // queued, we just return it (instead of the error).
+                drop(inner);
+                drop(reg);
+
+                let res = match self.inner.lock().pop_work() {
+                    Some(work) => Ok(Some(work)),
+                    None if signal_pending => Err(EINTR),
+                    None => Ok(None),
+                };
+                return res;
+            }
+        }
+    }
+
+    /// Push the provided work item to be delivered to user space via this thread.
+    ///
+    /// Returns whether the item was successfully pushed. This can only fail if the thread is dead.
+    pub(crate) fn push_work(&self, work: DLArc<dyn DeliverToRead>) -> PushWorkRes {
+        let sync = work.should_sync_wakeup();
+
+        let res = self.inner.lock().push_work(work);
+
+        if res.is_ok() {
+            if sync {
+                self.work_condvar.notify_sync();
+            } else {
+                self.work_condvar.notify_one();
+            }
+        }
+
+        res
+    }
+
+    /// Attempts to push to given work item to the thread if it's a looper thread (i.e., if it's
+    /// part of a thread pool) and is alive. Otherwise, push the work item to the process instead.
+    pub(crate) fn push_work_if_looper(&self, work: DLArc<dyn DeliverToRead>) -> BinderResult {
+        let mut inner = self.inner.lock();
+        if inner.is_looper() && !inner.is_dead {
+            inner.push_work(work);
+            Ok(())
+        } else {
+            drop(inner);
+            self.process.push_work(work)
+        }
+    }
+
+    pub(crate) fn push_work_deferred(&self, work: DLArc<dyn DeliverToRead>) {
+        self.inner.lock().push_work_deferred(work);
+    }
+
+    pub(crate) fn push_return_work(&self, reply: u32) {
+        self.inner.lock().push_return_work(reply);
+    }
+
+    fn translate_object(
+        &self,
+        obj_index: usize,
+        offset: usize,
+        object: BinderObjectRef<'_>,
+        view: &mut AllocationView<'_>,
+        allow_fds: bool,
+        sg_state: &mut ScatterGatherState,
+    ) -> BinderResult {
+        match object {
+            BinderObjectRef::Binder(obj) => {
+                let strong = obj.hdr.type_ == BINDER_TYPE_BINDER;
+                // SAFETY: `binder` is a `binder_uintptr_t`; any bit pattern is a valid
+                // representation.
+                let ptr = unsafe { obj.__bindgen_anon_1.binder } as _;
+                let cookie = obj.cookie as _;
+                let flags = obj.flags as _;
+                let node = self
+                    .process
+                    .as_arc_borrow()
+                    .get_node(ptr, cookie, flags, strong, self)?;
+                security::binder_transfer_binder(&self.process.cred, &view.alloc.process.cred)?;
+                view.transfer_binder_object(offset, obj, strong, node)?;
+            }
+            BinderObjectRef::Handle(obj) => {
+                let strong = obj.hdr.type_ == BINDER_TYPE_HANDLE;
+                // SAFETY: `handle` is a `u32`; any bit pattern is a valid representation.
+                let handle = unsafe { obj.__bindgen_anon_1.handle } as _;
+                let node = self.process.get_node_from_handle(handle, strong)?;
+                security::binder_transfer_binder(&self.process.cred, &view.alloc.process.cred)?;
+                view.transfer_binder_object(offset, obj, strong, node)?;
+            }
+            BinderObjectRef::Fd(obj) => {
+                if !allow_fds {
+                    return Err(EPERM.into());
+                }
+
+                // SAFETY: `fd` is a `u32`; any bit pattern is a valid representation.
+                let fd = unsafe { obj.__bindgen_anon_1.fd };
+                let file = LocalFile::fget(fd)?;
+                // SAFETY: The binder driver never calls `fdget_pos` and this code runs from an
+                // ioctl, so there are no active calls to `fdget_pos` on this thread.
+                let file = unsafe { LocalFile::assume_no_fdget_pos(file) };
+                security::binder_transfer_file(
+                    &self.process.cred,
+                    &view.alloc.process.cred,
+                    &file,
+                )?;
+
+                let mut obj_write = BinderFdObject::default();
+                obj_write.hdr.type_ = BINDER_TYPE_FD;
+                // This will be overwritten with the actual fd when the transaction is received.
+                obj_write.__bindgen_anon_1.fd = u32::MAX;
+                obj_write.cookie = obj.cookie;
+                view.write::<BinderFdObject>(offset, &obj_write)?;
+
+                const FD_FIELD_OFFSET: usize =
+                    core::mem::offset_of!(uapi::binder_fd_object, __bindgen_anon_1.fd);
+
+                let field_offset = offset + FD_FIELD_OFFSET;
+
+                view.alloc.info_add_fd(file, field_offset, false)?;
+            }
+            BinderObjectRef::Ptr(obj) => {
+                let obj_length = obj.length.try_into().map_err(|_| EINVAL)?;
+                let alloc_offset = match sg_state.unused_buffer_space.claim_next(obj_length) {
+                    Ok(alloc_offset) => alloc_offset,
+                    Err(err) => {
+                        pr_warn!(
+                            "Failed to claim space for a BINDER_TYPE_PTR. (offset: {}, limit: {}, size: {})",
+                            sg_state.unused_buffer_space.offset,
+                            sg_state.unused_buffer_space.limit,
+                            obj_length,
+                        );
+                        return Err(err.into());
+                    }
+                };
+
+                let sg_state_idx = sg_state.sg_entries.len();
+                sg_state.sg_entries.push(
+                    ScatterGatherEntry {
+                        obj_index,
+                        offset: alloc_offset,
+                        sender_uaddr: obj.buffer as _,
+                        length: obj_length,
+                        pointer_fixups: KVec::new(),
+                        fixup_min_offset: 0,
+                    },
+                    GFP_KERNEL,
+                )?;
+
+                let buffer_ptr_in_user_space = (view.alloc.ptr + alloc_offset) as u64;
+
+                if obj.flags & uapi::BINDER_BUFFER_FLAG_HAS_PARENT == 0 {
+                    sg_state.ancestors.clear();
+                    sg_state.ancestors.push(sg_state_idx, GFP_KERNEL)?;
+                } else {
+                    // Another buffer also has a pointer to this buffer, and we need to fixup that
+                    // pointer too.
+
+                    let parent_index = usize::try_from(obj.parent).map_err(|_| EINVAL)?;
+                    let parent_offset = usize::try_from(obj.parent_offset).map_err(|_| EINVAL)?;
+
+                    let info = sg_state.validate_parent_fixup(
+                        parent_index,
+                        parent_offset,
+                        size_of::<u64>(),
+                    )?;
+
+                    sg_state.ancestors.truncate(info.num_ancestors);
+                    sg_state.ancestors.push(sg_state_idx, GFP_KERNEL)?;
+
+                    let parent_entry = match sg_state.sg_entries.get_mut(info.parent_sg_index) {
+                        Some(parent_entry) => parent_entry,
+                        None => {
+                            pr_err!(
+                                "validate_parent_fixup returned index out of bounds for sg.entries"
+                            );
+                            return Err(EINVAL.into());
+                        }
+                    };
+
+                    parent_entry.fixup_min_offset = info.new_min_offset;
+                    parent_entry.pointer_fixups.push(
+                        PointerFixupEntry {
+                            skip: 0,
+                            pointer_value: buffer_ptr_in_user_space,
+                            target_offset: info.target_offset,
+                        },
+                        GFP_KERNEL,
+                    )?;
+                }
+
+                let mut obj_write = BinderBufferObject::default();
+                obj_write.hdr.type_ = BINDER_TYPE_PTR;
+                obj_write.flags = obj.flags;
+                obj_write.buffer = buffer_ptr_in_user_space;
+                obj_write.length = obj.length;
+                obj_write.parent = obj.parent;
+                obj_write.parent_offset = obj.parent_offset;
+                view.write::<BinderBufferObject>(offset, &obj_write)?;
+            }
+            BinderObjectRef::Fda(obj) => {
+                if !allow_fds {
+                    return Err(EPERM.into());
+                }
+                let parent_index = usize::try_from(obj.parent).map_err(|_| EINVAL)?;
+                let parent_offset = usize::try_from(obj.parent_offset).map_err(|_| EINVAL)?;
+                let num_fds = usize::try_from(obj.num_fds).map_err(|_| EINVAL)?;
+                let fds_len = num_fds.checked_mul(size_of::<u32>()).ok_or(EINVAL)?;
+
+                let info = sg_state.validate_parent_fixup(parent_index, parent_offset, fds_len)?;
+                view.alloc.info_add_fd_reserve(num_fds)?;
+
+                sg_state.ancestors.truncate(info.num_ancestors);
+                let parent_entry = match sg_state.sg_entries.get_mut(info.parent_sg_index) {
+                    Some(parent_entry) => parent_entry,
+                    None => {
+                        pr_err!(
+                            "validate_parent_fixup returned index out of bounds for sg.entries"
+                        );
+                        return Err(EINVAL.into());
+                    }
+                };
+
+                parent_entry.fixup_min_offset = info.new_min_offset;
+                parent_entry
+                    .pointer_fixups
+                    .push(
+                        PointerFixupEntry {
+                            skip: fds_len,
+                            pointer_value: 0,
+                            target_offset: info.target_offset,
+                        },
+                        GFP_KERNEL,
+                    )
+                    .map_err(|_| ENOMEM)?;
+
+                let fda_uaddr = parent_entry
+                    .sender_uaddr
+                    .checked_add(parent_offset)
+                    .ok_or(EINVAL)?;
+                let mut fda_bytes = KVec::new();
+                UserSlice::new(UserPtr::from_addr(fda_uaddr as _), fds_len)
+                    .read_all(&mut fda_bytes, GFP_KERNEL)?;
+
+                if fds_len != fda_bytes.len() {
+                    pr_err!("UserSlice::read_all returned wrong length in BINDER_TYPE_FDA");
+                    return Err(EINVAL.into());
+                }
+
+                for i in (0..fds_len).step_by(size_of::<u32>()) {
+                    let fd = {
+                        let mut fd_bytes = [0u8; size_of::<u32>()];
+                        fd_bytes.copy_from_slice(&fda_bytes[i..i + size_of::<u32>()]);
+                        u32::from_ne_bytes(fd_bytes)
+                    };
+
+                    let file = LocalFile::fget(fd)?;
+                    // SAFETY: The binder driver never calls `fdget_pos` and this code runs from an
+                    // ioctl, so there are no active calls to `fdget_pos` on this thread.
+                    let file = unsafe { LocalFile::assume_no_fdget_pos(file) };
+                    security::binder_transfer_file(
+                        &self.process.cred,
+                        &view.alloc.process.cred,
+                        &file,
+                    )?;
+
+                    // The `validate_parent_fixup` call ensuers that this addition will not
+                    // overflow.
+                    view.alloc.info_add_fd(file, info.target_offset + i, true)?;
+                }
+                drop(fda_bytes);
+
+                let mut obj_write = BinderFdArrayObject::default();
+                obj_write.hdr.type_ = BINDER_TYPE_FDA;
+                obj_write.num_fds = obj.num_fds;
+                obj_write.parent = obj.parent;
+                obj_write.parent_offset = obj.parent_offset;
+                view.write::<BinderFdArrayObject>(offset, &obj_write)?;
+            }
+        }
+        Ok(())
+    }
+
+    fn apply_sg(&self, alloc: &mut Allocation, sg_state: &mut ScatterGatherState) -> BinderResult {
+        for sg_entry in &mut sg_state.sg_entries {
+            let mut end_of_previous_fixup = sg_entry.offset;
+            let offset_end = sg_entry.offset.checked_add(sg_entry.length).ok_or(EINVAL)?;
+
+            let mut reader =
+                UserSlice::new(UserPtr::from_addr(sg_entry.sender_uaddr), sg_entry.length).reader();
+            for fixup in &mut sg_entry.pointer_fixups {
+                let fixup_len = if fixup.skip == 0 {
+                    size_of::<u64>()
+                } else {
+                    fixup.skip
+                };
+
+                let target_offset_end = fixup.target_offset.checked_add(fixup_len).ok_or(EINVAL)?;
+                if fixup.target_offset < end_of_previous_fixup || offset_end < target_offset_end {
+                    pr_warn!(
+                        "Fixups oob {} {} {} {}",
+                        fixup.target_offset,
+                        end_of_previous_fixup,
+                        offset_end,
+                        target_offset_end
+                    );
+                    return Err(EINVAL.into());
+                }
+
+                let copy_off = end_of_previous_fixup;
+                let copy_len = fixup.target_offset - end_of_previous_fixup;
+                if let Err(err) = alloc.copy_into(&mut reader, copy_off, copy_len) {
+                    pr_warn!("Failed copying into alloc: {:?}", err);
+                    return Err(err.into());
+                }
+                if fixup.skip == 0 {
+                    let res = alloc.write::<u64>(fixup.target_offset, &fixup.pointer_value);
+                    if let Err(err) = res {
+                        pr_warn!("Failed copying ptr into alloc: {:?}", err);
+                        return Err(err.into());
+                    }
+                }
+                if let Err(err) = reader.skip(fixup_len) {
+                    pr_warn!("Failed skipping {} from reader: {:?}", fixup_len, err);
+                    return Err(err.into());
+                }
+                end_of_previous_fixup = target_offset_end;
+            }
+            let copy_off = end_of_previous_fixup;
+            let copy_len = offset_end - end_of_previous_fixup;
+            if let Err(err) = alloc.copy_into(&mut reader, copy_off, copy_len) {
+                pr_warn!("Failed copying remainder into alloc: {:?}", err);
+                return Err(err.into());
+            }
+        }
+        Ok(())
+    }
+
+    /// This method copies the payload of a transaction into the target process.
+    ///
+    /// The resulting payload will have several different components, which will be stored next to
+    /// each other in the allocation. Furthermore, various objects can be embedded in the payload,
+    /// and those objects have to be translated so that they make sense to the target transaction.
+    pub(crate) fn copy_transaction_data(
+        &self,
+        to_process: Arc<Process>,
+        tr: &BinderTransactionDataSg,
+        debug_id: usize,
+        allow_fds: bool,
+        txn_security_ctx_offset: Option<&mut usize>,
+    ) -> BinderResult<NewAllocation> {
+        let trd = &tr.transaction_data;
+        let is_oneway = trd.flags & TF_ONE_WAY != 0;
+        let mut secctx = if let Some(offset) = txn_security_ctx_offset {
+            let secid = self.process.cred.get_secid();
+            let ctx = match security::SecurityCtx::from_secid(secid) {
+                Ok(ctx) => ctx,
+                Err(err) => {
+                    pr_warn!("Failed to get security ctx for id {}: {:?}", secid, err);
+                    return Err(err.into());
+                }
+            };
+            Some((offset, ctx))
+        } else {
+            None
+        };
+
+        let data_size = trd.data_size.try_into().map_err(|_| EINVAL)?;
+        let aligned_data_size = ptr_align(data_size).ok_or(EINVAL)?;
+        let offsets_size = trd.offsets_size.try_into().map_err(|_| EINVAL)?;
+        let aligned_offsets_size = ptr_align(offsets_size).ok_or(EINVAL)?;
+        let buffers_size = tr.buffers_size.try_into().map_err(|_| EINVAL)?;
+        let aligned_buffers_size = ptr_align(buffers_size).ok_or(EINVAL)?;
+        let aligned_secctx_size = match secctx.as_ref() {
+            Some((_offset, ctx)) => ptr_align(ctx.len()).ok_or(EINVAL)?,
+            None => 0,
+        };
+
+        // This guarantees that at least `sizeof(usize)` bytes will be allocated.
+        let len = usize::max(
+            aligned_data_size
+                .checked_add(aligned_offsets_size)
+                .and_then(|sum| sum.checked_add(aligned_buffers_size))
+                .and_then(|sum| sum.checked_add(aligned_secctx_size))
+                .ok_or(ENOMEM)?,
+            size_of::<usize>(),
+        );
+        let secctx_off = aligned_data_size + aligned_offsets_size + aligned_buffers_size;
+        let mut alloc =
+            match to_process.buffer_alloc(debug_id, len, is_oneway, self.process.task.pid()) {
+                Ok(alloc) => alloc,
+                Err(err) => {
+                    pr_warn!(
+                        "Failed to allocate buffer. len:{}, is_oneway:{}",
+                        len,
+                        is_oneway
+                    );
+                    return Err(err);
+                }
+            };
+
+        // SAFETY: This accesses a union field, but it's okay because the field's type is valid for
+        // all bit-patterns.
+        let trd_data_ptr = unsafe { &trd.data.ptr };
+        let mut buffer_reader =
+            UserSlice::new(UserPtr::from_addr(trd_data_ptr.buffer as _), data_size).reader();
+        let mut end_of_previous_object = 0;
+        let mut sg_state = None;
+
+        // Copy offsets if there are any.
+        if offsets_size > 0 {
+            {
+                let mut reader =
+                    UserSlice::new(UserPtr::from_addr(trd_data_ptr.offsets as _), offsets_size)
+                        .reader();
+                alloc.copy_into(&mut reader, aligned_data_size, offsets_size)?;
+            }
+
+            let offsets_start = aligned_data_size;
+            let offsets_end = aligned_data_size + aligned_offsets_size;
+
+            // This state is used for BINDER_TYPE_PTR objects.
+            let sg_state = sg_state.insert(ScatterGatherState {
+                unused_buffer_space: UnusedBufferSpace {
+                    offset: offsets_end,
+                    limit: len,
+                },
+                sg_entries: KVec::new(),
+                ancestors: KVec::new(),
+            });
+
+            // Traverse the objects specified.
+            let mut view = AllocationView::new(&mut alloc, data_size);
+            for (index, index_offset) in (offsets_start..offsets_end)
+                .step_by(size_of::<usize>())
+                .enumerate()
+            {
+                let offset = view.alloc.read(index_offset)?;
+
+                if offset < end_of_previous_object {
+                    pr_warn!("Got transaction with invalid offset.");
+                    return Err(EINVAL.into());
+                }
+
+                // Copy data between two objects.
+                if end_of_previous_object < offset {
+                    view.copy_into(
+                        &mut buffer_reader,
+                        end_of_previous_object,
+                        offset - end_of_previous_object,
+                    )?;
+                }
+
+                let mut object = BinderObject::read_from(&mut buffer_reader)?;
+
+                match self.translate_object(
+                    index,
+                    offset,
+                    object.as_ref(),
+                    &mut view,
+                    allow_fds,
+                    sg_state,
+                ) {
+                    Ok(()) => end_of_previous_object = offset + object.size(),
+                    Err(err) => {
+                        pr_warn!("Error while translating object.");
+                        return Err(err);
+                    }
+                }
+
+                // Update the indexes containing objects to clean up.
+                let offset_after_object = index_offset + size_of::<usize>();
+                view.alloc
+                    .set_info_offsets(offsets_start..offset_after_object);
+            }
+        }
+
+        // Copy remaining raw data.
+        alloc.copy_into(
+            &mut buffer_reader,
+            end_of_previous_object,
+            data_size - end_of_previous_object,
+        )?;
+
+        if let Some(sg_state) = sg_state.as_mut() {
+            if let Err(err) = self.apply_sg(&mut alloc, sg_state) {
+                pr_warn!("Failure in apply_sg: {:?}", err);
+                return Err(err);
+            }
+        }
+
+        if let Some((off_out, secctx)) = secctx.as_mut() {
+            if let Err(err) = alloc.write(secctx_off, secctx.as_bytes()) {
+                pr_warn!("Failed to write security context: {:?}", err);
+                return Err(err.into());
+            }
+            **off_out = secctx_off;
+        }
+        Ok(alloc)
+    }
+
+    fn unwind_transaction_stack(self: &Arc<Self>) {
+        let mut thread = self.clone();
+        while let Ok(transaction) = {
+            let mut inner = thread.inner.lock();
+            inner.pop_transaction_to_reply(thread.as_ref())
+        } {
+            let reply = Err(BR_DEAD_REPLY);
+            if !transaction.from.deliver_single_reply(reply, &transaction) {
+                break;
+            }
+
+            thread = transaction.from.clone();
+        }
+    }
+
+    pub(crate) fn deliver_reply(
+        &self,
+        reply: Result<DLArc<Transaction>, u32>,
+        transaction: &DArc<Transaction>,
+    ) {
+        if self.deliver_single_reply(reply, transaction) {
+            transaction.from.unwind_transaction_stack();
+        }
+    }
+
+    /// Delivers a reply to the thread that started a transaction. The reply can either be a
+    /// reply-transaction or an error code to be delivered instead.
+    ///
+    /// Returns whether the thread is dead. If it is, the caller is expected to unwind the
+    /// transaction stack by completing transactions for threads that are dead.
+    fn deliver_single_reply(
+        &self,
+        reply: Result<DLArc<Transaction>, u32>,
+        transaction: &DArc<Transaction>,
+    ) -> bool {
+        if let Ok(transaction) = &reply {
+            transaction.set_outstanding(&mut self.process.inner.lock());
+        }
+
+        {
+            let mut inner = self.inner.lock();
+            if !inner.pop_transaction_replied(transaction) {
+                return false;
+            }
+
+            if inner.is_dead {
+                return true;
+            }
+
+            match reply {
+                Ok(work) => {
+                    inner.push_work(work);
+                }
+                Err(code) => inner.push_reply_work(code),
+            }
+        }
+
+        // Notify the thread now that we've released the inner lock.
+        self.work_condvar.notify_sync();
+        false
+    }
+
+    /// Determines if the given transaction is the current transaction for this thread.
+    fn is_current_transaction(&self, transaction: &DArc<Transaction>) -> bool {
+        let inner = self.inner.lock();
+        match &inner.current_transaction {
+            None => false,
+            Some(current) => Arc::ptr_eq(current, transaction),
+        }
+    }
+
+    /// Determines the current top of the transaction stack. It fails if the top is in another
+    /// thread (i.e., this thread belongs to a stack but it has called another thread). The top is
+    /// [`None`] if the thread is not currently participating in a transaction stack.
+    fn top_of_transaction_stack(&self) -> Result<Option<DArc<Transaction>>> {
+        let inner = self.inner.lock();
+        if let Some(cur) = &inner.current_transaction {
+            if core::ptr::eq(self, cur.from.as_ref()) {
+                pr_warn!("got new transaction with bad transaction stack");
+                return Err(EINVAL);
+            }
+            Ok(Some(cur.clone()))
+        } else {
+            Ok(None)
+        }
+    }
+
+    fn transaction<T>(self: &Arc<Self>, tr: &BinderTransactionDataSg, inner: T)
+    where
+        T: FnOnce(&Arc<Self>, &BinderTransactionDataSg) -> BinderResult,
+    {
+        if let Err(err) = inner(self, tr) {
+            if err.should_pr_warn() {
+                let mut ee = self.inner.lock().extended_error;
+                ee.command = err.reply;
+                ee.param = err.as_errno();
+                pr_warn!(
+                    "Transaction failed: {:?} my_pid:{}",
+                    err,
+                    self.process.pid_in_current_ns()
+                );
+            }
+
+            self.push_return_work(err.reply);
+        }
+    }
+
+    fn transaction_inner(self: &Arc<Self>, tr: &BinderTransactionDataSg) -> BinderResult {
+        // SAFETY: Handle's type has no invalid bit patterns.
+        let handle = unsafe { tr.transaction_data.target.handle };
+        let node_ref = self.process.get_transaction_node(handle)?;
+        security::binder_transaction(&self.process.cred, &node_ref.node.owner.cred)?;
+        // TODO: We need to ensure that there isn't a pending transaction in the work queue. How
+        // could this happen?
+        let top = self.top_of_transaction_stack()?;
+        let list_completion = DTRWrap::arc_try_new(DeliverCode::new(BR_TRANSACTION_COMPLETE))?;
+        let completion = list_completion.clone_arc();
+        let transaction = Transaction::new(node_ref, top, self, tr)?;
+
+        // Check that the transaction stack hasn't changed while the lock was released, then update
+        // it with the new transaction.
+        {
+            let mut inner = self.inner.lock();
+            if !transaction.is_stacked_on(&inner.current_transaction) {
+                pr_warn!("Transaction stack changed during transaction!");
+                return Err(EINVAL.into());
+            }
+            inner.current_transaction = Some(transaction.clone_arc());
+            // We push the completion as a deferred work so that we wait for the reply before
+            // returning to userland.
+            inner.push_work_deferred(list_completion);
+        }
+
+        if let Err(e) = transaction.submit() {
+            completion.skip();
+            // Define `transaction` first to drop it after `inner`.
+            let transaction;
+            let mut inner = self.inner.lock();
+            transaction = inner.current_transaction.take().unwrap();
+            inner.current_transaction = transaction.clone_next();
+            Err(e)
+        } else {
+            Ok(())
+        }
+    }
+
+    fn reply_inner(self: &Arc<Self>, tr: &BinderTransactionDataSg) -> BinderResult {
+        let orig = self.inner.lock().pop_transaction_to_reply(self)?;
+        if !orig.from.is_current_transaction(&orig) {
+            return Err(EINVAL.into());
+        }
+
+        // We need to complete the transaction even if we cannot complete building the reply.
+        let out = (|| -> BinderResult<_> {
+            let completion = DTRWrap::arc_try_new(DeliverCode::new(BR_TRANSACTION_COMPLETE))?;
+            let process = orig.from.process.clone();
+            let allow_fds = orig.flags & TF_ACCEPT_FDS != 0;
+            let reply = Transaction::new_reply(self, process, tr, allow_fds)?;
+            self.inner.lock().push_work(completion);
+            orig.from.deliver_reply(Ok(reply), &orig);
+            Ok(())
+        })()
+        .map_err(|mut err| {
+            // At this point we only return `BR_TRANSACTION_COMPLETE` to the caller, and we must let
+            // the sender know that the transaction has completed (with an error in this case).
+            pr_warn!(
+                "Failure {:?} during reply - delivering BR_FAILED_REPLY to sender.",
+                err
+            );
+            let reply = Err(BR_FAILED_REPLY);
+            orig.from.deliver_reply(reply, &orig);
+            err.reply = BR_TRANSACTION_COMPLETE;
+            err
+        });
+
+        out
+    }
+
+    fn oneway_transaction_inner(self: &Arc<Self>, tr: &BinderTransactionDataSg) -> BinderResult {
+        // SAFETY: The `handle` field is valid for all possible byte values, so reading from the
+        // union is okay.
+        let handle = unsafe { tr.transaction_data.target.handle };
+        let node_ref = self.process.get_transaction_node(handle)?;
+        security::binder_transaction(&self.process.cred, &node_ref.node.owner.cred)?;
+        let transaction = Transaction::new(node_ref, None, self, tr)?;
+        let code = if self.process.is_oneway_spam_detection_enabled()
+            && transaction.oneway_spam_detected
+        {
+            BR_ONEWAY_SPAM_SUSPECT
+        } else {
+            BR_TRANSACTION_COMPLETE
+        };
+        let list_completion = DTRWrap::arc_try_new(DeliverCode::new(code))?;
+        let completion = list_completion.clone_arc();
+        self.inner.lock().push_work(list_completion);
+        match transaction.submit() {
+            Ok(()) => Ok(()),
+            Err(err) => {
+                completion.skip();
+                Err(err)
+            }
+        }
+    }
+
+    fn write(self: &Arc<Self>, req: &mut BinderWriteRead) -> Result {
+        let write_start = req.write_buffer.wrapping_add(req.write_consumed);
+        let write_len = req.write_size.saturating_sub(req.write_consumed);
+        let mut reader =
+            UserSlice::new(UserPtr::from_addr(write_start as _), write_len as _).reader();
+
+        while reader.len() >= size_of::<u32>() && self.inner.lock().return_work.is_unused() {
+            let before = reader.len();
+            let cmd = reader.read::<u32>()?;
+            GLOBAL_STATS.inc_bc(cmd);
+            self.process.stats.inc_bc(cmd);
+            match cmd {
+                BC_TRANSACTION => {
+                    let tr = reader.read::<BinderTransactionData>()?.with_buffers_size(0);
+                    if tr.transaction_data.flags & TF_ONE_WAY != 0 {
+                        self.transaction(&tr, Self::oneway_transaction_inner);
+                    } else {
+                        self.transaction(&tr, Self::transaction_inner);
+                    }
+                }
+                BC_TRANSACTION_SG => {
+                    let tr = reader.read::<BinderTransactionDataSg>()?;
+                    if tr.transaction_data.flags & TF_ONE_WAY != 0 {
+                        self.transaction(&tr, Self::oneway_transaction_inner);
+                    } else {
+                        self.transaction(&tr, Self::transaction_inner);
+                    }
+                }
+                BC_REPLY => {
+                    let tr = reader.read::<BinderTransactionData>()?.with_buffers_size(0);
+                    self.transaction(&tr, Self::reply_inner)
+                }
+                BC_REPLY_SG => {
+                    let tr = reader.read::<BinderTransactionDataSg>()?;
+                    self.transaction(&tr, Self::reply_inner)
+                }
+                BC_FREE_BUFFER => {
+                    let buffer = self.process.buffer_get(reader.read()?);
+                    if let Some(buffer) = buffer {
+                        if buffer.looper_need_return_on_free() {
+                            self.inner.lock().looper_need_return = true;
+                        }
+                        drop(buffer);
+                    }
+                }
+                BC_INCREFS => {
+                    self.process
+                        .as_arc_borrow()
+                        .update_ref(reader.read()?, true, false)?
+                }
+                BC_ACQUIRE => {
+                    self.process
+                        .as_arc_borrow()
+                        .update_ref(reader.read()?, true, true)?
+                }
+                BC_RELEASE => {
+                    self.process
+                        .as_arc_borrow()
+                        .update_ref(reader.read()?, false, true)?
+                }
+                BC_DECREFS => {
+                    self.process
+                        .as_arc_borrow()
+                        .update_ref(reader.read()?, false, false)?
+                }
+                BC_INCREFS_DONE => self.process.inc_ref_done(&mut reader, false)?,
+                BC_ACQUIRE_DONE => self.process.inc_ref_done(&mut reader, true)?,
+                BC_REQUEST_DEATH_NOTIFICATION => self.process.request_death(&mut reader, self)?,
+                BC_CLEAR_DEATH_NOTIFICATION => self.process.clear_death(&mut reader, self)?,
+                BC_DEAD_BINDER_DONE => self.process.dead_binder_done(reader.read()?, self),
+                BC_REGISTER_LOOPER => {
+                    let valid = self.process.register_thread();
+                    self.inner.lock().looper_register(valid);
+                }
+                BC_ENTER_LOOPER => self.inner.lock().looper_enter(),
+                BC_EXIT_LOOPER => self.inner.lock().looper_exit(),
+                BC_REQUEST_FREEZE_NOTIFICATION => self.process.request_freeze_notif(&mut reader)?,
+                BC_CLEAR_FREEZE_NOTIFICATION => self.process.clear_freeze_notif(&mut reader)?,
+                BC_FREEZE_NOTIFICATION_DONE => self.process.freeze_notif_done(&mut reader)?,
+
+                // Fail if given an unknown error code.
+                // BC_ATTEMPT_ACQUIRE and BC_ACQUIRE_RESULT are no longer supported.
+                _ => return Err(EINVAL),
+            }
+            // Update the number of write bytes consumed.
+            req.write_consumed += (before - reader.len()) as u64;
+        }
+
+        Ok(())
+    }
+
+    fn read(self: &Arc<Self>, req: &mut BinderWriteRead, wait: bool) -> Result {
+        let read_start = req.read_buffer.wrapping_add(req.read_consumed);
+        let read_len = req.read_size.saturating_sub(req.read_consumed);
+        let mut writer = BinderReturnWriter::new(
+            UserSlice::new(UserPtr::from_addr(read_start as _), read_len as _).writer(),
+            self,
+        );
+        let (in_pool, use_proc_queue) = {
+            let inner = self.inner.lock();
+            (inner.is_looper(), inner.should_use_process_work_queue())
+        };
+
+        let getter = if use_proc_queue {
+            Self::get_work
+        } else {
+            Self::get_work_local
+        };
+
+        // Reserve some room at the beginning of the read buffer so that we can send a
+        // BR_SPAWN_LOOPER if we need to.
+        let mut has_noop_placeholder = false;
+        if req.read_consumed == 0 {
+            if let Err(err) = writer.write_code(BR_NOOP) {
+                pr_warn!("Failure when writing BR_NOOP at beginning of buffer.");
+                return Err(err);
+            }
+            has_noop_placeholder = true;
+        }
+
+        // Loop doing work while there is room in the buffer.
+        let initial_len = writer.len();
+        while writer.len() >= size_of::<uapi::binder_transaction_data_secctx>() + 4 {
+            match getter(self, wait && initial_len == writer.len()) {
+                Ok(Some(work)) => match work.into_arc().do_work(self, &mut writer) {
+                    Ok(true) => {}
+                    Ok(false) => break,
+                    Err(err) => {
+                        return Err(err);
+                    }
+                },
+                Ok(None) => {
+                    break;
+                }
+                Err(err) => {
+                    // Propagate the error if we haven't written anything else.
+                    if err != EINTR && err != EAGAIN {
+                        pr_warn!("Failure in work getter: {:?}", err);
+                    }
+                    if initial_len == writer.len() {
+                        return Err(err);
+                    } else {
+                        break;
+                    }
+                }
+            }
+        }
+
+        req.read_consumed += read_len - writer.len() as u64;
+
+        // Write BR_SPAWN_LOOPER if the process needs more threads for its pool.
+        if has_noop_placeholder && in_pool && self.process.needs_thread() {
+            let mut writer =
+                UserSlice::new(UserPtr::from_addr(req.read_buffer as _), req.read_size as _)
+                    .writer();
+            writer.write(&BR_SPAWN_LOOPER)?;
+        }
+        Ok(())
+    }
+
+    pub(crate) fn write_read(self: &Arc<Self>, data: UserSlice, wait: bool) -> Result {
+        let (mut reader, mut writer) = data.reader_writer();
+        let mut req = reader.read::<BinderWriteRead>()?;
+
+        // Go through the write buffer.
+        let mut ret = Ok(());
+        if req.write_size > 0 {
+            ret = self.write(&mut req);
+            if let Err(err) = ret {
+                pr_warn!(
+                    "Write failure {:?} in pid:{}",
+                    err,
+                    self.process.pid_in_current_ns()
+                );
+                req.read_consumed = 0;
+                writer.write(&req)?;
+                self.inner.lock().looper_need_return = false;
+                return ret;
+            }
+        }
+
+        // Go through the work queue.
+        if req.read_size > 0 {
+            ret = self.read(&mut req, wait);
+            if ret.is_err() && ret != Err(EINTR) {
+                pr_warn!(
+                    "Read failure {:?} in pid:{}",
+                    ret,
+                    self.process.pid_in_current_ns()
+                );
+            }
+        }
+
+        // Write the request back so that the consumed fields are visible to the caller.
+        writer.write(&req)?;
+
+        self.inner.lock().looper_need_return = false;
+
+        ret
+    }
+
+    pub(crate) fn poll(&self, file: &File, table: PollTable<'_>) -> (bool, u32) {
+        table.register_wait(file, &self.work_condvar);
+        let mut inner = self.inner.lock();
+        (inner.should_use_process_work_queue(), inner.poll())
+    }
+
+    /// Make the call to `get_work` or `get_work_local` return immediately, if any.
+    pub(crate) fn exit_looper(&self) {
+        let mut inner = self.inner.lock();
+        let should_notify = inner.looper_flags & LOOPER_WAITING != 0;
+        if should_notify {
+            inner.looper_need_return = true;
+        }
+        drop(inner);
+
+        if should_notify {
+            self.work_condvar.notify_one();
+        }
+    }
+
+    pub(crate) fn notify_if_poll_ready(&self, sync: bool) {
+        // Determine if we need to notify. This requires the lock.
+        let inner = self.inner.lock();
+        let notify = inner.looper_flags & LOOPER_POLL != 0 && inner.should_use_process_work_queue();
+        drop(inner);
+
+        // Now that the lock is no longer held, notify the waiters if we have to.
+        if notify {
+            if sync {
+                self.work_condvar.notify_sync();
+            } else {
+                self.work_condvar.notify_one();
+            }
+        }
+    }
+
+    pub(crate) fn release(self: &Arc<Self>) {
+        self.inner.lock().is_dead = true;
+
+        //self.work_condvar.clear();
+        self.unwind_transaction_stack();
+
+        // Cancel all pending work items.
+        while let Ok(Some(work)) = self.get_work_local(false) {
+            work.into_arc().cancel();
+        }
+    }
+}
+
+#[pin_data]
+struct ThreadError {
+    error_code: AtomicU32,
+    #[pin]
+    links_track: AtomicTracker,
+}
+
+impl ThreadError {
+    fn try_new() -> Result<DArc<Self>> {
+        DTRWrap::arc_pin_init(pin_init!(Self {
+            error_code: AtomicU32::new(BR_OK),
+            links_track <- AtomicTracker::new(),
+        }))
+        .map(ListArc::into_arc)
+    }
+
+    fn set_error_code(&self, code: u32) {
+        self.error_code.store(code, Ordering::Relaxed);
+    }
+
+    fn is_unused(&self) -> bool {
+        self.error_code.load(Ordering::Relaxed) == BR_OK
+    }
+}
+
+impl DeliverToRead for ThreadError {
+    fn do_work(
+        self: DArc<Self>,
+        _thread: &Thread,
+        writer: &mut BinderReturnWriter<'_>,
+    ) -> Result<bool> {
+        let code = self.error_code.load(Ordering::Relaxed);
+        self.error_code.store(BR_OK, Ordering::Relaxed);
+        writer.write_code(code)?;
+        Ok(true)
+    }
+
+    fn cancel(self: DArc<Self>) {}
+
+    fn should_sync_wakeup(&self) -> bool {
+        false
+    }
+
+    fn debug_print(&self, m: &SeqFile, prefix: &str, _tprefix: &str) -> Result<()> {
+        seq_print!(
+            m,
+            "{}transaction error: {}\n",
+            prefix,
+            self.error_code.load(Ordering::Relaxed)
+        );
+        Ok(())
+    }
+}
+
+kernel::list::impl_list_arc_safe! {
+    impl ListArcSafe<0> for ThreadError {
+        tracked_by links_track: AtomicTracker;
+    }
+}
diff --git a/drivers/android/binder/trace.rs b/drivers/android/binder/trace.rs
new file mode 100644
index 000000000000..af0e4392805e
--- /dev/null
+++ b/drivers/android/binder/trace.rs
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0
+
+// Copyright (C) 2025 Google LLC.
+
+use kernel::ffi::{c_uint, c_ulong};
+use kernel::tracepoint::declare_trace;
+
+declare_trace! {
+    unsafe fn rust_binder_ioctl(cmd: c_uint, arg: c_ulong);
+}
+
+#[inline]
+pub(crate) fn trace_ioctl(cmd: u32, arg: usize) {
+    // SAFETY: Always safe to call.
+    unsafe { rust_binder_ioctl(cmd, arg as c_ulong) }
+}
diff --git a/drivers/android/binder/transaction.rs b/drivers/android/binder/transaction.rs
new file mode 100644
index 000000000000..4bd3c0e417eb
--- /dev/null
+++ b/drivers/android/binder/transaction.rs
@@ -0,0 +1,456 @@
+// SPDX-License-Identifier: GPL-2.0
+
+// Copyright (C) 2025 Google LLC.
+
+use core::sync::atomic::{AtomicBool, Ordering};
+use kernel::{
+    prelude::*,
+    seq_file::SeqFile,
+    seq_print,
+    sync::{Arc, SpinLock},
+    task::Kuid,
+    time::{Instant, Monotonic},
+    types::ScopeGuard,
+};
+
+use crate::{
+    allocation::{Allocation, TranslatedFds},
+    defs::*,
+    error::{BinderError, BinderResult},
+    node::{Node, NodeRef},
+    process::{Process, ProcessInner},
+    ptr_align,
+    thread::{PushWorkRes, Thread},
+    BinderReturnWriter, DArc, DLArc, DTRWrap, DeliverToRead,
+};
+
+#[pin_data(PinnedDrop)]
+pub(crate) struct Transaction {
+    pub(crate) debug_id: usize,
+    target_node: Option<DArc<Node>>,
+    pub(crate) from_parent: Option<DArc<Transaction>>,
+    pub(crate) from: Arc<Thread>,
+    pub(crate) to: Arc<Process>,
+    #[pin]
+    allocation: SpinLock<Option<Allocation>>,
+    is_outstanding: AtomicBool,
+    code: u32,
+    pub(crate) flags: u32,
+    data_size: usize,
+    offsets_size: usize,
+    data_address: usize,
+    sender_euid: Kuid,
+    txn_security_ctx_off: Option<usize>,
+    pub(crate) oneway_spam_detected: bool,
+    start_time: Instant<Monotonic>,
+}
+
+kernel::list::impl_list_arc_safe! {
+    impl ListArcSafe<0> for Transaction { untracked; }
+}
+
+impl Transaction {
+    pub(crate) fn new(
+        node_ref: NodeRef,
+        from_parent: Option<DArc<Transaction>>,
+        from: &Arc<Thread>,
+        tr: &BinderTransactionDataSg,
+    ) -> BinderResult<DLArc<Self>> {
+        let debug_id = super::next_debug_id();
+        let trd = &tr.transaction_data;
+        let allow_fds = node_ref.node.flags & FLAT_BINDER_FLAG_ACCEPTS_FDS != 0;
+        let txn_security_ctx = node_ref.node.flags & FLAT_BINDER_FLAG_TXN_SECURITY_CTX != 0;
+        let mut txn_security_ctx_off = if txn_security_ctx { Some(0) } else { None };
+        let to = node_ref.node.owner.clone();
+        let mut alloc = match from.copy_transaction_data(
+            to.clone(),
+            tr,
+            debug_id,
+            allow_fds,
+            txn_security_ctx_off.as_mut(),
+        ) {
+            Ok(alloc) => alloc,
+            Err(err) => {
+                if !err.is_dead() {
+                    pr_warn!("Failure in copy_transaction_data: {:?}", err);
+                }
+                return Err(err);
+            }
+        };
+        let oneway_spam_detected = alloc.oneway_spam_detected;
+        if trd.flags & TF_ONE_WAY != 0 {
+            if from_parent.is_some() {
+                pr_warn!("Oneway transaction should not be in a transaction stack.");
+                return Err(EINVAL.into());
+            }
+            alloc.set_info_oneway_node(node_ref.node.clone());
+        }
+        if trd.flags & TF_CLEAR_BUF != 0 {
+            alloc.set_info_clear_on_drop();
+        }
+        let target_node = node_ref.node.clone();
+        alloc.set_info_target_node(node_ref);
+        let data_address = alloc.ptr;
+
+        Ok(DTRWrap::arc_pin_init(pin_init!(Transaction {
+            debug_id,
+            target_node: Some(target_node),
+            from_parent,
+            sender_euid: from.process.task.euid(),
+            from: from.clone(),
+            to,
+            code: trd.code,
+            flags: trd.flags,
+            data_size: trd.data_size as _,
+            offsets_size: trd.offsets_size as _,
+            data_address,
+            allocation <- kernel::new_spinlock!(Some(alloc.success()), "Transaction::new"),
+            is_outstanding: AtomicBool::new(false),
+            txn_security_ctx_off,
+            oneway_spam_detected,
+            start_time: Instant::now(),
+        }))?)
+    }
+
+    pub(crate) fn new_reply(
+        from: &Arc<Thread>,
+        to: Arc<Process>,
+        tr: &BinderTransactionDataSg,
+        allow_fds: bool,
+    ) -> BinderResult<DLArc<Self>> {
+        let debug_id = super::next_debug_id();
+        let trd = &tr.transaction_data;
+        let mut alloc = match from.copy_transaction_data(to.clone(), tr, debug_id, allow_fds, None)
+        {
+            Ok(alloc) => alloc,
+            Err(err) => {
+                pr_warn!("Failure in copy_transaction_data: {:?}", err);
+                return Err(err);
+            }
+        };
+        let oneway_spam_detected = alloc.oneway_spam_detected;
+        if trd.flags & TF_CLEAR_BUF != 0 {
+            alloc.set_info_clear_on_drop();
+        }
+        Ok(DTRWrap::arc_pin_init(pin_init!(Transaction {
+            debug_id,
+            target_node: None,
+            from_parent: None,
+            sender_euid: from.process.task.euid(),
+            from: from.clone(),
+            to,
+            code: trd.code,
+            flags: trd.flags,
+            data_size: trd.data_size as _,
+            offsets_size: trd.offsets_size as _,
+            data_address: alloc.ptr,
+            allocation <- kernel::new_spinlock!(Some(alloc.success()), "Transaction::new"),
+            is_outstanding: AtomicBool::new(false),
+            txn_security_ctx_off: None,
+            oneway_spam_detected,
+            start_time: Instant::now(),
+        }))?)
+    }
+
+    #[inline(never)]
+    pub(crate) fn debug_print_inner(&self, m: &SeqFile, prefix: &str) {
+        seq_print!(
+            m,
+            "{}{}: from {}:{} to {} code {:x} flags {:x} elapsed {}ms",
+            prefix,
+            self.debug_id,
+            self.from.process.task.pid(),
+            self.from.id,
+            self.to.task.pid(),
+            self.code,
+            self.flags,
+            self.start_time.elapsed().as_millis(),
+        );
+        if let Some(target_node) = &self.target_node {
+            seq_print!(m, " node {}", target_node.debug_id);
+        }
+        seq_print!(m, " size {}:{}\n", self.data_size, self.offsets_size);
+    }
+
+    /// Determines if the transaction is stacked on top of the given transaction.
+    pub(crate) fn is_stacked_on(&self, onext: &Option<DArc<Self>>) -> bool {
+        match (&self.from_parent, onext) {
+            (None, None) => true,
+            (Some(from_parent), Some(next)) => Arc::ptr_eq(from_parent, next),
+            _ => false,
+        }
+    }
+
+    /// Returns a pointer to the next transaction on the transaction stack, if there is one.
+    pub(crate) fn clone_next(&self) -> Option<DArc<Self>> {
+        Some(self.from_parent.as_ref()?.clone())
+    }
+
+    /// Searches in the transaction stack for a thread that belongs to the target process. This is
+    /// useful when finding a target for a new transaction: if the node belongs to a process that
+    /// is already part of the transaction stack, we reuse the thread.
+    fn find_target_thread(&self) -> Option<Arc<Thread>> {
+        let mut it = &self.from_parent;
+        while let Some(transaction) = it {
+            if Arc::ptr_eq(&transaction.from.process, &self.to) {
+                return Some(transaction.from.clone());
+            }
+            it = &transaction.from_parent;
+        }
+        None
+    }
+
+    /// Searches in the transaction stack for a transaction originating at the given thread.
+    pub(crate) fn find_from(&self, thread: &Thread) -> Option<&DArc<Transaction>> {
+        let mut it = &self.from_parent;
+        while let Some(transaction) = it {
+            if core::ptr::eq(thread, transaction.from.as_ref()) {
+                return Some(transaction);
+            }
+
+            it = &transaction.from_parent;
+        }
+        None
+    }
+
+    pub(crate) fn set_outstanding(&self, to_process: &mut ProcessInner) {
+        // No race because this method is only called once.
+        if !self.is_outstanding.load(Ordering::Relaxed) {
+            self.is_outstanding.store(true, Ordering::Relaxed);
+            to_process.add_outstanding_txn();
+        }
+    }
+
+    /// Decrement `outstanding_txns` in `to` if it hasn't already been decremented.
+    fn drop_outstanding_txn(&self) {
+        // No race because this is called at most twice, and one of the calls are in the
+        // destructor, which is guaranteed to not race with any other operations on the
+        // transaction. It also cannot race with `set_outstanding`, since submission happens
+        // before delivery.
+        if self.is_outstanding.load(Ordering::Relaxed) {
+            self.is_outstanding.store(false, Ordering::Relaxed);
+            self.to.drop_outstanding_txn();
+        }
+    }
+
+    /// Submits the transaction to a work queue. Uses a thread if there is one in the transaction
+    /// stack, otherwise uses the destination process.
+    ///
+    /// Not used for replies.
+    pub(crate) fn submit(self: DLArc<Self>) -> BinderResult {
+        // Defined before `process_inner` so that the destructor runs after releasing the lock.
+        let mut _t_outdated;
+
+        let oneway = self.flags & TF_ONE_WAY != 0;
+        let process = self.to.clone();
+        let mut process_inner = process.inner.lock();
+
+        self.set_outstanding(&mut process_inner);
+
+        if oneway {
+            if let Some(target_node) = self.target_node.clone() {
+                if process_inner.is_frozen.is_frozen() {
+                    process_inner.async_recv = true;
+                    if self.flags & TF_UPDATE_TXN != 0 {
+                        if let Some(t_outdated) =
+                            target_node.take_outdated_transaction(&self, &mut process_inner)
+                        {
+                            // Save the transaction to be dropped after locks are released.
+                            _t_outdated = t_outdated;
+                        }
+                    }
+                }
+                match target_node.submit_oneway(self, &mut process_inner) {
+                    Ok(()) => {}
+                    Err((err, work)) => {
+                        drop(process_inner);
+                        // Drop work after releasing process lock.
+                        drop(work);
+                        return Err(err);
+                    }
+                }
+
+                if process_inner.is_frozen.is_frozen() {
+                    return Err(BinderError::new_frozen_oneway());
+                } else {
+                    return Ok(());
+                }
+            } else {
+                pr_err!("Failed to submit oneway transaction to node.");
+            }
+        }
+
+        if process_inner.is_frozen.is_frozen() {
+            process_inner.sync_recv = true;
+            return Err(BinderError::new_frozen());
+        }
+
+        let res = if let Some(thread) = self.find_target_thread() {
+            match thread.push_work(self) {
+                PushWorkRes::Ok => Ok(()),
+                PushWorkRes::FailedDead(me) => Err((BinderError::new_dead(), me)),
+            }
+        } else {
+            process_inner.push_work(self)
+        };
+        drop(process_inner);
+
+        match res {
+            Ok(()) => Ok(()),
+            Err((err, work)) => {
+                // Drop work after releasing process lock.
+                drop(work);
+                Err(err)
+            }
+        }
+    }
+
+    /// Check whether one oneway transaction can supersede another.
+    pub(crate) fn can_replace(&self, old: &Transaction) -> bool {
+        if self.from.process.task.pid() != old.from.process.task.pid() {
+            return false;
+        }
+
+        if self.flags & old.flags & (TF_ONE_WAY | TF_UPDATE_TXN) != (TF_ONE_WAY | TF_UPDATE_TXN) {
+            return false;
+        }
+
+        let target_node_match = match (self.target_node.as_ref(), old.target_node.as_ref()) {
+            (None, None) => true,
+            (Some(tn1), Some(tn2)) => Arc::ptr_eq(tn1, tn2),
+            _ => false,
+        };
+
+        self.code == old.code && self.flags == old.flags && target_node_match
+    }
+
+    fn prepare_file_list(&self) -> Result<TranslatedFds> {
+        let mut alloc = self.allocation.lock().take().ok_or(ESRCH)?;
+
+        match alloc.translate_fds() {
+            Ok(translated) => {
+                *self.allocation.lock() = Some(alloc);
+                Ok(translated)
+            }
+            Err(err) => {
+                // Free the allocation eagerly.
+                drop(alloc);
+                Err(err)
+            }
+        }
+    }
+}
+
+impl DeliverToRead for Transaction {
+    fn do_work(
+        self: DArc<Self>,
+        thread: &Thread,
+        writer: &mut BinderReturnWriter<'_>,
+    ) -> Result<bool> {
+        let send_failed_reply = ScopeGuard::new(|| {
+            if self.target_node.is_some() && self.flags & TF_ONE_WAY == 0 {
+                let reply = Err(BR_FAILED_REPLY);
+                self.from.deliver_reply(reply, &self);
+            }
+            self.drop_outstanding_txn();
+        });
+
+        let files = if let Ok(list) = self.prepare_file_list() {
+            list
+        } else {
+            // On failure to process the list, we send a reply back to the sender and ignore the
+            // transaction on the recipient.
+            return Ok(true);
+        };
+
+        let mut tr_sec = BinderTransactionDataSecctx::default();
+        let tr = tr_sec.tr_data();
+        if let Some(target_node) = &self.target_node {
+            let (ptr, cookie) = target_node.get_id();
+            tr.target.ptr = ptr as _;
+            tr.cookie = cookie as _;
+        };
+        tr.code = self.code;
+        tr.flags = self.flags;
+        tr.data_size = self.data_size as _;
+        tr.data.ptr.buffer = self.data_address as _;
+        tr.offsets_size = self.offsets_size as _;
+        if tr.offsets_size > 0 {
+            tr.data.ptr.offsets = (self.data_address + ptr_align(self.data_size).unwrap()) as _;
+        }
+        tr.sender_euid = self.sender_euid.into_uid_in_current_ns();
+        tr.sender_pid = 0;
+        if self.target_node.is_some() && self.flags & TF_ONE_WAY == 0 {
+            // Not a reply and not one-way.
+            tr.sender_pid = self.from.process.pid_in_current_ns();
+        }
+        let code = if self.target_node.is_none() {
+            BR_REPLY
+        } else if self.txn_security_ctx_off.is_some() {
+            BR_TRANSACTION_SEC_CTX
+        } else {
+            BR_TRANSACTION
+        };
+
+        // Write the transaction code and data to the user buffer.
+        writer.write_code(code)?;
+        if let Some(off) = self.txn_security_ctx_off {
+            tr_sec.secctx = (self.data_address + off) as u64;
+            writer.write_payload(&tr_sec)?;
+        } else {
+            writer.write_payload(&*tr)?;
+        }
+
+        let mut alloc = self.allocation.lock().take().ok_or(ESRCH)?;
+
+        // Dismiss the completion of transaction with a failure. No failure paths are allowed from
+        // here on out.
+        send_failed_reply.dismiss();
+
+        // Commit files, and set FDs in FDA to be closed on buffer free.
+        let close_on_free = files.commit();
+        alloc.set_info_close_on_free(close_on_free);
+
+        // It is now the user's responsibility to clear the allocation.
+        alloc.keep_alive();
+
+        self.drop_outstanding_txn();
+
+        // When this is not a reply and not a oneway transaction, update `current_transaction`. If
+        // it's a reply, `current_transaction` has already been updated appropriately.
+        if self.target_node.is_some() && tr_sec.transaction_data.flags & TF_ONE_WAY == 0 {
+            thread.set_current_transaction(self);
+        }
+
+        Ok(false)
+    }
+
+    fn cancel(self: DArc<Self>) {
+        let allocation = self.allocation.lock().take();
+        drop(allocation);
+
+        // If this is not a reply or oneway transaction, then send a dead reply.
+        if self.target_node.is_some() && self.flags & TF_ONE_WAY == 0 {
+            let reply = Err(BR_DEAD_REPLY);
+            self.from.deliver_reply(reply, &self);
+        }
+
+        self.drop_outstanding_txn();
+    }
+
+    fn should_sync_wakeup(&self) -> bool {
+        self.flags & TF_ONE_WAY == 0
+    }
+
+    fn debug_print(&self, m: &SeqFile, _prefix: &str, tprefix: &str) -> Result<()> {
+        self.debug_print_inner(m, tprefix);
+        Ok(())
+    }
+}
+
+#[pinned_drop]
+impl PinnedDrop for Transaction {
+    fn drop(self: Pin<&mut Self>) {
+        self.drop_outstanding_txn();
+    }
+}
diff --git a/drivers/android/binder_alloc.c b/drivers/android/binder_alloc.c
index 2d8b9b91dee0..979c96b74cad 100644
--- a/drivers/android/binder_alloc.c
+++ b/drivers/android/binder_alloc.c
@@ -23,10 +23,11 @@
 #include <linux/uaccess.h>
 #include <linux/highmem.h>
 #include <linux/sizes.h>
+#include <kunit/visibility.h>
 #include "binder_alloc.h"
 #include "binder_trace.h"
 
-struct list_lru binder_alloc_lru;
+static struct list_lru binder_freelist;
 
 static DEFINE_MUTEX(binder_alloc_mmap_lock);
 
@@ -57,13 +58,14 @@ static struct binder_buffer *binder_buffer_prev(struct binder_buffer *buffer)
 	return list_entry(buffer->entry.prev, struct binder_buffer, entry);
 }
 
-static size_t binder_alloc_buffer_size(struct binder_alloc *alloc,
-				       struct binder_buffer *buffer)
+VISIBLE_IF_KUNIT size_t binder_alloc_buffer_size(struct binder_alloc *alloc,
+						 struct binder_buffer *buffer)
 {
 	if (list_is_last(&buffer->entry, &alloc->buffers))
-		return alloc->buffer + alloc->buffer_size - buffer->user_data;
+		return alloc->vm_start + alloc->buffer_size - buffer->user_data;
 	return binder_buffer_next(buffer)->user_data - buffer->user_data;
 }
+EXPORT_SYMBOL_IF_KUNIT(binder_alloc_buffer_size);
 
 static void binder_insert_free_buffer(struct binder_alloc *alloc,
 				      struct binder_buffer *new_buffer)
@@ -125,23 +127,20 @@ static void binder_insert_allocated_buffer_locked(
 
 static struct binder_buffer *binder_alloc_prepare_to_free_locked(
 		struct binder_alloc *alloc,
-		uintptr_t user_ptr)
+		unsigned long user_ptr)
 {
 	struct rb_node *n = alloc->allocated_buffers.rb_node;
 	struct binder_buffer *buffer;
-	void __user *uptr;
-
-	uptr = (void __user *)user_ptr;
 
 	while (n) {
 		buffer = rb_entry(n, struct binder_buffer, rb_node);
 		BUG_ON(buffer->free);
 
-		if (uptr < buffer->user_data)
+		if (user_ptr < buffer->user_data) {
 			n = n->rb_left;
-		else if (uptr > buffer->user_data)
+		} else if (user_ptr > buffer->user_data) {
 			n = n->rb_right;
-		else {
+		} else {
 			/*
 			 * Guard against user threads attempting to
 			 * free the buffer when in use by kernel or
@@ -168,226 +167,372 @@ static struct binder_buffer *binder_alloc_prepare_to_free_locked(
  * Return:	Pointer to buffer or NULL
  */
 struct binder_buffer *binder_alloc_prepare_to_free(struct binder_alloc *alloc,
-						   uintptr_t user_ptr)
+						   unsigned long user_ptr)
 {
-	struct binder_buffer *buffer;
+	guard(mutex)(&alloc->mutex);
+	return binder_alloc_prepare_to_free_locked(alloc, user_ptr);
+}
 
-	mutex_lock(&alloc->mutex);
-	buffer = binder_alloc_prepare_to_free_locked(alloc, user_ptr);
-	mutex_unlock(&alloc->mutex);
-	return buffer;
+static inline void
+binder_set_installed_page(struct binder_alloc *alloc,
+			  unsigned long index,
+			  struct page *page)
+{
+	/* Pairs with acquire in binder_get_installed_page() */
+	smp_store_release(&alloc->pages[index], page);
 }
 
-static int binder_update_page_range(struct binder_alloc *alloc, int allocate,
-				    void __user *start, void __user *end)
+static inline struct page *
+binder_get_installed_page(struct binder_alloc *alloc, unsigned long index)
 {
-	void __user *page_addr;
-	unsigned long user_page_addr;
-	struct binder_lru_page *page;
-	struct vm_area_struct *vma = NULL;
-	struct mm_struct *mm = NULL;
-	bool need_mm = false;
+	/* Pairs with release in binder_set_installed_page() */
+	return smp_load_acquire(&alloc->pages[index]);
+}
 
-	binder_alloc_debug(BINDER_DEBUG_BUFFER_ALLOC,
-		     "%d: %s pages %pK-%pK\n", alloc->pid,
-		     allocate ? "allocate" : "free", start, end);
+static void binder_lru_freelist_add(struct binder_alloc *alloc,
+				    unsigned long start, unsigned long end)
+{
+	unsigned long page_addr;
+	struct page *page;
 
-	if (end <= start)
-		return 0;
+	trace_binder_update_page_range(alloc, false, start, end);
+
+	for (page_addr = start; page_addr < end; page_addr += PAGE_SIZE) {
+		size_t index;
+		int ret;
 
-	trace_binder_update_page_range(alloc, allocate, start, end);
+		index = (page_addr - alloc->vm_start) / PAGE_SIZE;
+		page = binder_get_installed_page(alloc, index);
+		if (!page)
+			continue;
 
-	if (allocate == 0)
-		goto free_range;
+		trace_binder_free_lru_start(alloc, index);
 
-	for (page_addr = start; page_addr < end; page_addr += PAGE_SIZE) {
-		page = &alloc->pages[(page_addr - alloc->buffer) / PAGE_SIZE];
-		if (!page->page_ptr) {
-			need_mm = true;
-			break;
-		}
+		ret = list_lru_add(alloc->freelist,
+				   page_to_lru(page),
+				   page_to_nid(page),
+				   NULL);
+		WARN_ON(!ret);
+
+		trace_binder_free_lru_end(alloc, index);
 	}
+}
 
-	if (need_mm && mmget_not_zero(alloc->vma_vm_mm))
-		mm = alloc->vma_vm_mm;
+static inline
+void binder_alloc_set_mapped(struct binder_alloc *alloc, bool state)
+{
+	/* pairs with smp_load_acquire in binder_alloc_is_mapped() */
+	smp_store_release(&alloc->mapped, state);
+}
+
+static inline bool binder_alloc_is_mapped(struct binder_alloc *alloc)
+{
+	/* pairs with smp_store_release in binder_alloc_set_mapped() */
+	return smp_load_acquire(&alloc->mapped);
+}
+
+static struct page *binder_page_lookup(struct binder_alloc *alloc,
+				       unsigned long addr)
+{
+	struct mm_struct *mm = alloc->mm;
+	struct page *page;
+	long npages = 0;
+
+	/*
+	 * Find an existing page in the remote mm. If missing,
+	 * don't attempt to fault-in just propagate an error.
+	 */
+	mmap_read_lock(mm);
+	if (binder_alloc_is_mapped(alloc))
+		npages = get_user_pages_remote(mm, addr, 1, FOLL_NOFAULT,
+					       &page, NULL);
+	mmap_read_unlock(mm);
+
+	return npages > 0 ? page : NULL;
+}
 
-	if (mm) {
-		down_read(&mm->mmap_sem);
-		vma = alloc->vma;
+static int binder_page_insert(struct binder_alloc *alloc,
+			      unsigned long addr,
+			      struct page *page)
+{
+	struct mm_struct *mm = alloc->mm;
+	struct vm_area_struct *vma;
+	int ret = -ESRCH;
+
+	/* attempt per-vma lock first */
+	vma = lock_vma_under_rcu(mm, addr);
+	if (vma) {
+		if (binder_alloc_is_mapped(alloc))
+			ret = vm_insert_page(vma, addr, page);
+		vma_end_read(vma);
+		return ret;
 	}
 
-	if (!vma && need_mm) {
-		binder_alloc_debug(BINDER_DEBUG_USER_ERROR,
-				   "%d: binder_alloc_buf failed to map pages in userspace, no vma\n",
-				   alloc->pid);
-		goto err_no_vma;
+	/* fall back to mmap_lock */
+	mmap_read_lock(mm);
+	vma = vma_lookup(mm, addr);
+	if (vma && binder_alloc_is_mapped(alloc))
+		ret = vm_insert_page(vma, addr, page);
+	mmap_read_unlock(mm);
+
+	return ret;
+}
+
+static struct page *binder_page_alloc(struct binder_alloc *alloc,
+				      unsigned long index)
+{
+	struct binder_shrinker_mdata *mdata;
+	struct page *page;
+
+	page = alloc_page(GFP_KERNEL | __GFP_HIGHMEM | __GFP_ZERO);
+	if (!page)
+		return NULL;
+
+	/* allocate and install shrinker metadata under page->private */
+	mdata = kzalloc(sizeof(*mdata), GFP_KERNEL);
+	if (!mdata) {
+		__free_page(page);
+		return NULL;
 	}
 
-	for (page_addr = start; page_addr < end; page_addr += PAGE_SIZE) {
-		int ret;
-		bool on_lru;
-		size_t index;
+	mdata->alloc = alloc;
+	mdata->page_index = index;
+	INIT_LIST_HEAD(&mdata->lru);
+	set_page_private(page, (unsigned long)mdata);
 
-		index = (page_addr - alloc->buffer) / PAGE_SIZE;
-		page = &alloc->pages[index];
+	return page;
+}
 
-		if (page->page_ptr) {
-			trace_binder_alloc_lru_start(alloc, index);
+static void binder_free_page(struct page *page)
+{
+	kfree((struct binder_shrinker_mdata *)page_private(page));
+	__free_page(page);
+}
 
-			on_lru = list_lru_del(&binder_alloc_lru, &page->lru);
-			WARN_ON(!on_lru);
+static int binder_install_single_page(struct binder_alloc *alloc,
+				      unsigned long index,
+				      unsigned long addr)
+{
+	struct page *page;
+	int ret;
 
-			trace_binder_alloc_lru_end(alloc, index);
-			continue;
+	if (!mmget_not_zero(alloc->mm))
+		return -ESRCH;
+
+	page = binder_page_alloc(alloc, index);
+	if (!page) {
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	ret = binder_page_insert(alloc, addr, page);
+	switch (ret) {
+	case -EBUSY:
+		/*
+		 * EBUSY is ok. Someone installed the pte first but the
+		 * alloc->pages[index] has not been updated yet. Discard
+		 * our page and look up the one already installed.
+		 */
+		ret = 0;
+		binder_free_page(page);
+		page = binder_page_lookup(alloc, addr);
+		if (!page) {
+			pr_err("%d: failed to find page at offset %lx\n",
+			       alloc->pid, addr - alloc->vm_start);
+			ret = -ESRCH;
+			break;
 		}
+		fallthrough;
+	case 0:
+		/* Mark page installation complete and safe to use */
+		binder_set_installed_page(alloc, index, page);
+		break;
+	default:
+		binder_free_page(page);
+		pr_err("%d: %s failed to insert page at offset %lx with %d\n",
+		       alloc->pid, __func__, addr - alloc->vm_start, ret);
+		break;
+	}
+out:
+	mmput_async(alloc->mm);
+	return ret;
+}
 
-		if (WARN_ON(!vma))
-			goto err_page_ptr_cleared;
+static int binder_install_buffer_pages(struct binder_alloc *alloc,
+				       struct binder_buffer *buffer,
+				       size_t size)
+{
+	unsigned long start, final;
+	unsigned long page_addr;
+
+	start = buffer->user_data & PAGE_MASK;
+	final = PAGE_ALIGN(buffer->user_data + size);
+
+	for (page_addr = start; page_addr < final; page_addr += PAGE_SIZE) {
+		unsigned long index;
+		int ret;
+
+		index = (page_addr - alloc->vm_start) / PAGE_SIZE;
+		if (binder_get_installed_page(alloc, index))
+			continue;
 
 		trace_binder_alloc_page_start(alloc, index);
-		page->page_ptr = alloc_page(GFP_KERNEL |
-					    __GFP_HIGHMEM |
-					    __GFP_ZERO);
-		if (!page->page_ptr) {
-			pr_err("%d: binder_alloc_buf failed for page at %pK\n",
-				alloc->pid, page_addr);
-			goto err_alloc_page_failed;
-		}
-		page->alloc = alloc;
-		INIT_LIST_HEAD(&page->lru);
-
-		user_page_addr = (uintptr_t)page_addr;
-		ret = vm_insert_page(vma, user_page_addr, page[0].page_ptr);
-		if (ret) {
-			pr_err("%d: binder_alloc_buf failed to map page at %lx in userspace\n",
-			       alloc->pid, user_page_addr);
-			goto err_vm_insert_page_failed;
-		}
 
-		if (index + 1 > alloc->pages_high)
-			alloc->pages_high = index + 1;
+		ret = binder_install_single_page(alloc, index, page_addr);
+		if (ret)
+			return ret;
 
 		trace_binder_alloc_page_end(alloc, index);
 	}
-	if (mm) {
-		up_read(&mm->mmap_sem);
-		mmput(mm);
-	}
+
 	return 0;
+}
 
-free_range:
-	for (page_addr = end - PAGE_SIZE; 1; page_addr -= PAGE_SIZE) {
-		bool ret;
-		size_t index;
+/* The range of pages should exclude those shared with other buffers */
+static void binder_lru_freelist_del(struct binder_alloc *alloc,
+				    unsigned long start, unsigned long end)
+{
+	unsigned long page_addr;
+	struct page *page;
 
-		index = (page_addr - alloc->buffer) / PAGE_SIZE;
-		page = &alloc->pages[index];
+	trace_binder_update_page_range(alloc, true, start, end);
 
-		trace_binder_free_lru_start(alloc, index);
+	for (page_addr = start; page_addr < end; page_addr += PAGE_SIZE) {
+		unsigned long index;
+		bool on_lru;
 
-		ret = list_lru_add(&binder_alloc_lru, &page->lru);
-		WARN_ON(!ret);
+		index = (page_addr - alloc->vm_start) / PAGE_SIZE;
+		page = binder_get_installed_page(alloc, index);
 
-		trace_binder_free_lru_end(alloc, index);
-		if (page_addr == start)
-			break;
-		continue;
-
-err_vm_insert_page_failed:
-		__free_page(page->page_ptr);
-		page->page_ptr = NULL;
-err_alloc_page_failed:
-err_page_ptr_cleared:
-		if (page_addr == start)
-			break;
-	}
-err_no_vma:
-	if (mm) {
-		up_read(&mm->mmap_sem);
-		mmput(mm);
+		if (page) {
+			trace_binder_alloc_lru_start(alloc, index);
+
+			on_lru = list_lru_del(alloc->freelist,
+					      page_to_lru(page),
+					      page_to_nid(page),
+					      NULL);
+			WARN_ON(!on_lru);
+
+			trace_binder_alloc_lru_end(alloc, index);
+			continue;
+		}
+
+		if (index + 1 > alloc->pages_high)
+			alloc->pages_high = index + 1;
 	}
-	return vma ? -ENOMEM : -ESRCH;
 }
 
+static void debug_no_space_locked(struct binder_alloc *alloc)
+{
+	size_t largest_alloc_size = 0;
+	struct binder_buffer *buffer;
+	size_t allocated_buffers = 0;
+	size_t largest_free_size = 0;
+	size_t total_alloc_size = 0;
+	size_t total_free_size = 0;
+	size_t free_buffers = 0;
+	size_t buffer_size;
+	struct rb_node *n;
+
+	for (n = rb_first(&alloc->allocated_buffers); n; n = rb_next(n)) {
+		buffer = rb_entry(n, struct binder_buffer, rb_node);
+		buffer_size = binder_alloc_buffer_size(alloc, buffer);
+		allocated_buffers++;
+		total_alloc_size += buffer_size;
+		if (buffer_size > largest_alloc_size)
+			largest_alloc_size = buffer_size;
+	}
+
+	for (n = rb_first(&alloc->free_buffers); n; n = rb_next(n)) {
+		buffer = rb_entry(n, struct binder_buffer, rb_node);
+		buffer_size = binder_alloc_buffer_size(alloc, buffer);
+		free_buffers++;
+		total_free_size += buffer_size;
+		if (buffer_size > largest_free_size)
+			largest_free_size = buffer_size;
+	}
+
+	binder_alloc_debug(BINDER_DEBUG_USER_ERROR,
+			   "allocated: %zd (num: %zd largest: %zd), free: %zd (num: %zd largest: %zd)\n",
+			   total_alloc_size, allocated_buffers,
+			   largest_alloc_size, total_free_size,
+			   free_buffers, largest_free_size);
+}
 
-static inline void binder_alloc_set_vma(struct binder_alloc *alloc,
-		struct vm_area_struct *vma)
+static bool debug_low_async_space_locked(struct binder_alloc *alloc)
 {
-	if (vma)
-		alloc->vma_vm_mm = vma->vm_mm;
 	/*
-	 * If we see alloc->vma is not NULL, buffer data structures set up
-	 * completely. Look at smp_rmb side binder_alloc_get_vma.
-	 * We also want to guarantee new alloc->vma_vm_mm is always visible
-	 * if alloc->vma is set.
+	 * Find the amount and size of buffers allocated by the current caller;
+	 * The idea is that once we cross the threshold, whoever is responsible
+	 * for the low async space is likely to try to send another async txn,
+	 * and at some point we'll catch them in the act. This is more efficient
+	 * than keeping a map per pid.
 	 */
-	smp_wmb();
-	alloc->vma = vma;
-}
+	struct binder_buffer *buffer;
+	size_t total_alloc_size = 0;
+	int pid = current->tgid;
+	size_t num_buffers = 0;
+	struct rb_node *n;
 
-static inline struct vm_area_struct *binder_alloc_get_vma(
-		struct binder_alloc *alloc)
-{
-	struct vm_area_struct *vma = NULL;
+	/*
+	 * Only start detecting spammers once we have less than 20% of async
+	 * space left (which is less than 10% of total buffer size).
+	 */
+	if (alloc->free_async_space >= alloc->buffer_size / 10) {
+		alloc->oneway_spam_detected = false;
+		return false;
+	}
+
+	for (n = rb_first(&alloc->allocated_buffers); n != NULL;
+		 n = rb_next(n)) {
+		buffer = rb_entry(n, struct binder_buffer, rb_node);
+		if (buffer->pid != pid)
+			continue;
+		if (!buffer->async_transaction)
+			continue;
+		total_alloc_size += binder_alloc_buffer_size(alloc, buffer);
+		num_buffers++;
+	}
 
-	if (alloc->vma) {
-		/* Look at description in binder_alloc_set_vma */
-		smp_rmb();
-		vma = alloc->vma;
+	/*
+	 * Warn if this pid has more than 50 transactions, or more than 50% of
+	 * async space (which is 25% of total buffer size). Oneway spam is only
+	 * detected when the threshold is exceeded.
+	 */
+	if (num_buffers > 50 || total_alloc_size > alloc->buffer_size / 4) {
+		binder_alloc_debug(BINDER_DEBUG_USER_ERROR,
+			     "%d: pid %d spamming oneway? %zd buffers allocated for a total size of %zd\n",
+			      alloc->pid, pid, num_buffers, total_alloc_size);
+		if (!alloc->oneway_spam_detected) {
+			alloc->oneway_spam_detected = true;
+			return true;
+		}
 	}
-	return vma;
+	return false;
 }
 
+/* Callers preallocate @new_buffer, it is freed by this function if unused */
 static struct binder_buffer *binder_alloc_new_buf_locked(
 				struct binder_alloc *alloc,
-				size_t data_size,
-				size_t offsets_size,
-				size_t extra_buffers_size,
+				struct binder_buffer *new_buffer,
+				size_t size,
 				int is_async)
 {
 	struct rb_node *n = alloc->free_buffers.rb_node;
+	struct rb_node *best_fit = NULL;
 	struct binder_buffer *buffer;
+	unsigned long next_used_page;
+	unsigned long curr_last_page;
 	size_t buffer_size;
-	struct rb_node *best_fit = NULL;
-	void __user *has_page_addr;
-	void __user *end_page_addr;
-	size_t size, data_offsets_size;
-	int ret;
 
-	if (!binder_alloc_get_vma(alloc)) {
-		binder_alloc_debug(BINDER_DEBUG_USER_ERROR,
-				   "%d: binder_alloc_buf, no vma\n",
-				   alloc->pid);
-		return ERR_PTR(-ESRCH);
-	}
-
-	data_offsets_size = ALIGN(data_size, sizeof(void *)) +
-		ALIGN(offsets_size, sizeof(void *));
-
-	if (data_offsets_size < data_size || data_offsets_size < offsets_size) {
-		binder_alloc_debug(BINDER_DEBUG_BUFFER_ALLOC,
-				"%d: got transaction with invalid size %zd-%zd\n",
-				alloc->pid, data_size, offsets_size);
-		return ERR_PTR(-EINVAL);
-	}
-	size = data_offsets_size + ALIGN(extra_buffers_size, sizeof(void *));
-	if (size < data_offsets_size || size < extra_buffers_size) {
-		binder_alloc_debug(BINDER_DEBUG_BUFFER_ALLOC,
-				"%d: got transaction with invalid extra_buffers_size %zd\n",
-				alloc->pid, extra_buffers_size);
-		return ERR_PTR(-EINVAL);
-	}
-	if (is_async &&
-	    alloc->free_async_space < size + sizeof(struct binder_buffer)) {
+	if (is_async && alloc->free_async_space < size) {
 		binder_alloc_debug(BINDER_DEBUG_BUFFER_ALLOC,
 			     "%d: binder_alloc_buf size %zd failed, no async space left\n",
 			      alloc->pid, size);
-		return ERR_PTR(-ENOSPC);
+		buffer = ERR_PTR(-ENOSPC);
+		goto out;
 	}
 
-	/* Pad 0-size buffers so they get assigned unique addresses */
-	size = max(size, sizeof(void *));
-
 	while (n) {
 		buffer = rb_entry(n, struct binder_buffer, rb_node);
 		BUG_ON(!buffer->free);
@@ -396,109 +541,92 @@ static struct binder_buffer *binder_alloc_new_buf_locked(
 		if (size < buffer_size) {
 			best_fit = n;
 			n = n->rb_left;
-		} else if (size > buffer_size)
+		} else if (size > buffer_size) {
 			n = n->rb_right;
-		else {
+		} else {
 			best_fit = n;
 			break;
 		}
 	}
-	if (best_fit == NULL) {
-		size_t allocated_buffers = 0;
-		size_t largest_alloc_size = 0;
-		size_t total_alloc_size = 0;
-		size_t free_buffers = 0;
-		size_t largest_free_size = 0;
-		size_t total_free_size = 0;
-
-		for (n = rb_first(&alloc->allocated_buffers); n != NULL;
-		     n = rb_next(n)) {
-			buffer = rb_entry(n, struct binder_buffer, rb_node);
-			buffer_size = binder_alloc_buffer_size(alloc, buffer);
-			allocated_buffers++;
-			total_alloc_size += buffer_size;
-			if (buffer_size > largest_alloc_size)
-				largest_alloc_size = buffer_size;
-		}
-		for (n = rb_first(&alloc->free_buffers); n != NULL;
-		     n = rb_next(n)) {
-			buffer = rb_entry(n, struct binder_buffer, rb_node);
-			buffer_size = binder_alloc_buffer_size(alloc, buffer);
-			free_buffers++;
-			total_free_size += buffer_size;
-			if (buffer_size > largest_free_size)
-				largest_free_size = buffer_size;
-		}
+
+	if (unlikely(!best_fit)) {
 		binder_alloc_debug(BINDER_DEBUG_USER_ERROR,
 				   "%d: binder_alloc_buf size %zd failed, no address space\n",
 				   alloc->pid, size);
-		binder_alloc_debug(BINDER_DEBUG_USER_ERROR,
-				   "allocated: %zd (num: %zd largest: %zd), free: %zd (num: %zd largest: %zd)\n",
-				   total_alloc_size, allocated_buffers,
-				   largest_alloc_size, total_free_size,
-				   free_buffers, largest_free_size);
-		return ERR_PTR(-ENOSPC);
+		debug_no_space_locked(alloc);
+		buffer = ERR_PTR(-ENOSPC);
+		goto out;
 	}
-	if (n == NULL) {
+
+	if (buffer_size != size) {
+		/* Found an oversized buffer and needs to be split */
 		buffer = rb_entry(best_fit, struct binder_buffer, rb_node);
 		buffer_size = binder_alloc_buffer_size(alloc, buffer);
+
+		WARN_ON(n || buffer_size == size);
+		new_buffer->user_data = buffer->user_data + size;
+		list_add(&new_buffer->entry, &buffer->entry);
+		new_buffer->free = 1;
+		binder_insert_free_buffer(alloc, new_buffer);
+		new_buffer = NULL;
 	}
 
 	binder_alloc_debug(BINDER_DEBUG_BUFFER_ALLOC,
 		     "%d: binder_alloc_buf size %zd got buffer %pK size %zd\n",
 		      alloc->pid, size, buffer, buffer_size);
 
-	has_page_addr = (void __user *)
-		(((uintptr_t)buffer->user_data + buffer_size) & PAGE_MASK);
-	WARN_ON(n && buffer_size != size);
-	end_page_addr =
-		(void __user *)PAGE_ALIGN((uintptr_t)buffer->user_data + size);
-	if (end_page_addr > has_page_addr)
-		end_page_addr = has_page_addr;
-	ret = binder_update_page_range(alloc, 1, (void __user *)
-		PAGE_ALIGN((uintptr_t)buffer->user_data), end_page_addr);
-	if (ret)
-		return ERR_PTR(ret);
-
-	if (buffer_size != size) {
-		struct binder_buffer *new_buffer;
-
-		new_buffer = kzalloc(sizeof(*buffer), GFP_KERNEL);
-		if (!new_buffer) {
-			pr_err("%s: %d failed to alloc new buffer struct\n",
-			       __func__, alloc->pid);
-			goto err_alloc_buf_struct_failed;
-		}
-		new_buffer->user_data = (u8 __user *)buffer->user_data + size;
-		list_add(&new_buffer->entry, &buffer->entry);
-		new_buffer->free = 1;
-		binder_insert_free_buffer(alloc, new_buffer);
-	}
+	/*
+	 * Now we remove the pages from the freelist. A clever calculation
+	 * with buffer_size determines if the last page is shared with an
+	 * adjacent in-use buffer. In such case, the page has been already
+	 * removed from the freelist so we trim our range short.
+	 */
+	next_used_page = (buffer->user_data + buffer_size) & PAGE_MASK;
+	curr_last_page = PAGE_ALIGN(buffer->user_data + size);
+	binder_lru_freelist_del(alloc, PAGE_ALIGN(buffer->user_data),
+				min(next_used_page, curr_last_page));
 
-	rb_erase(best_fit, &alloc->free_buffers);
+	rb_erase(&buffer->rb_node, &alloc->free_buffers);
 	buffer->free = 0;
 	buffer->allow_user_free = 0;
 	binder_insert_allocated_buffer_locked(alloc, buffer);
-	binder_alloc_debug(BINDER_DEBUG_BUFFER_ALLOC,
-		     "%d: binder_alloc_buf size %zd got %pK\n",
-		      alloc->pid, size, buffer);
-	buffer->data_size = data_size;
-	buffer->offsets_size = offsets_size;
 	buffer->async_transaction = is_async;
-	buffer->extra_buffers_size = extra_buffers_size;
+	buffer->oneway_spam_suspect = false;
 	if (is_async) {
-		alloc->free_async_space -= size + sizeof(struct binder_buffer);
+		alloc->free_async_space -= size;
 		binder_alloc_debug(BINDER_DEBUG_BUFFER_ALLOC_ASYNC,
 			     "%d: binder_alloc_buf size %zd async free %zd\n",
 			      alloc->pid, size, alloc->free_async_space);
+		if (debug_low_async_space_locked(alloc))
+			buffer->oneway_spam_suspect = true;
 	}
+
+out:
+	/* Discard possibly unused new_buffer */
+	kfree(new_buffer);
 	return buffer;
+}
 
-err_alloc_buf_struct_failed:
-	binder_update_page_range(alloc, 0, (void __user *)
-				 PAGE_ALIGN((uintptr_t)buffer->user_data),
-				 end_page_addr);
-	return ERR_PTR(-ENOMEM);
+/* Calculate the sanitized total size, returns 0 for invalid request */
+static inline size_t sanitized_size(size_t data_size,
+				    size_t offsets_size,
+				    size_t extra_buffers_size)
+{
+	size_t total, tmp;
+
+	/* Align to pointer size and check for overflows */
+	tmp = ALIGN(data_size, sizeof(void *)) +
+		ALIGN(offsets_size, sizeof(void *));
+	if (tmp < data_size || tmp < offsets_size)
+		return 0;
+	total = tmp + ALIGN(extra_buffers_size, sizeof(void *));
+	if (total < tmp || total < extra_buffers_size)
+		return 0;
+
+	/* Pad 0-sized buffers so they get a unique address */
+	total = max(total, sizeof(void *));
+
+	return total;
 }
 
 /**
@@ -514,7 +642,7 @@ err_alloc_buf_struct_failed:
  * is the sum of the three given sizes (each rounded up to
  * pointer-sized boundary)
  *
- * Return:	The allocated buffer or %NULL if error
+ * Return:	The allocated buffer or %ERR_PTR(-errno) if error
  */
 struct binder_buffer *binder_alloc_new_buf(struct binder_alloc *alloc,
 					   size_t data_size,
@@ -522,70 +650,88 @@ struct binder_buffer *binder_alloc_new_buf(struct binder_alloc *alloc,
 					   size_t extra_buffers_size,
 					   int is_async)
 {
-	struct binder_buffer *buffer;
+	struct binder_buffer *buffer, *next;
+	size_t size;
+	int ret;
+
+	/* Check binder_alloc is fully initialized */
+	if (!binder_alloc_is_mapped(alloc)) {
+		binder_alloc_debug(BINDER_DEBUG_USER_ERROR,
+				   "%d: binder_alloc_buf, no vma\n",
+				   alloc->pid);
+		return ERR_PTR(-ESRCH);
+	}
+
+	size = sanitized_size(data_size, offsets_size, extra_buffers_size);
+	if (unlikely(!size)) {
+		binder_alloc_debug(BINDER_DEBUG_BUFFER_ALLOC,
+				   "%d: got transaction with invalid size %zd-%zd-%zd\n",
+				   alloc->pid, data_size, offsets_size,
+				   extra_buffers_size);
+		return ERR_PTR(-EINVAL);
+	}
+
+	/* Preallocate the next buffer */
+	next = kzalloc(sizeof(*next), GFP_KERNEL);
+	if (!next)
+		return ERR_PTR(-ENOMEM);
 
 	mutex_lock(&alloc->mutex);
-	buffer = binder_alloc_new_buf_locked(alloc, data_size, offsets_size,
-					     extra_buffers_size, is_async);
+	buffer = binder_alloc_new_buf_locked(alloc, next, size, is_async);
+	if (IS_ERR(buffer)) {
+		mutex_unlock(&alloc->mutex);
+		goto out;
+	}
+
+	buffer->data_size = data_size;
+	buffer->offsets_size = offsets_size;
+	buffer->extra_buffers_size = extra_buffers_size;
+	buffer->pid = current->tgid;
 	mutex_unlock(&alloc->mutex);
+
+	ret = binder_install_buffer_pages(alloc, buffer, size);
+	if (ret) {
+		binder_alloc_free_buf(alloc, buffer);
+		buffer = ERR_PTR(ret);
+	}
+out:
 	return buffer;
 }
+EXPORT_SYMBOL_IF_KUNIT(binder_alloc_new_buf);
 
-static void __user *buffer_start_page(struct binder_buffer *buffer)
+static unsigned long buffer_start_page(struct binder_buffer *buffer)
 {
-	return (void __user *)((uintptr_t)buffer->user_data & PAGE_MASK);
+	return buffer->user_data & PAGE_MASK;
 }
 
-static void __user *prev_buffer_end_page(struct binder_buffer *buffer)
+static unsigned long prev_buffer_end_page(struct binder_buffer *buffer)
 {
-	return (void __user *)
-		(((uintptr_t)(buffer->user_data) - 1) & PAGE_MASK);
+	return (buffer->user_data - 1) & PAGE_MASK;
 }
 
 static void binder_delete_free_buffer(struct binder_alloc *alloc,
 				      struct binder_buffer *buffer)
 {
-	struct binder_buffer *prev, *next = NULL;
-	bool to_free = true;
+	struct binder_buffer *prev, *next;
+
+	if (PAGE_ALIGNED(buffer->user_data))
+		goto skip_freelist;
+
 	BUG_ON(alloc->buffers.next == &buffer->entry);
 	prev = binder_buffer_prev(buffer);
 	BUG_ON(!prev->free);
-	if (prev_buffer_end_page(prev) == buffer_start_page(buffer)) {
-		to_free = false;
-		binder_alloc_debug(BINDER_DEBUG_BUFFER_ALLOC,
-				   "%d: merge free, buffer %pK share page with %pK\n",
-				   alloc->pid, buffer->user_data,
-				   prev->user_data);
-	}
+	if (prev_buffer_end_page(prev) == buffer_start_page(buffer))
+		goto skip_freelist;
 
 	if (!list_is_last(&buffer->entry, &alloc->buffers)) {
 		next = binder_buffer_next(buffer);
-		if (buffer_start_page(next) == buffer_start_page(buffer)) {
-			to_free = false;
-			binder_alloc_debug(BINDER_DEBUG_BUFFER_ALLOC,
-					   "%d: merge free, buffer %pK share page with %pK\n",
-					   alloc->pid,
-					   buffer->user_data,
-					   next->user_data);
-		}
-	}
-
-	if (PAGE_ALIGNED(buffer->user_data)) {
-		binder_alloc_debug(BINDER_DEBUG_BUFFER_ALLOC,
-				   "%d: merge free, buffer start %pK is page aligned\n",
-				   alloc->pid, buffer->user_data);
-		to_free = false;
+		if (buffer_start_page(next) == buffer_start_page(buffer))
+			goto skip_freelist;
 	}
 
-	if (to_free) {
-		binder_alloc_debug(BINDER_DEBUG_BUFFER_ALLOC,
-				   "%d: merge free, buffer %pK do not share page with %pK or %pK\n",
-				   alloc->pid, buffer->user_data,
-				   prev->user_data,
-				   next ? next->user_data : NULL);
-		binder_update_page_range(alloc, 0, buffer_start_page(buffer),
-					 buffer_start_page(buffer) + PAGE_SIZE);
-	}
+	binder_lru_freelist_add(alloc, buffer_start_page(buffer),
+				buffer_start_page(buffer) + PAGE_SIZE);
+skip_freelist:
 	list_del(&buffer->entry);
 	kfree(buffer);
 }
@@ -608,21 +754,18 @@ static void binder_free_buf_locked(struct binder_alloc *alloc,
 	BUG_ON(buffer->free);
 	BUG_ON(size > buffer_size);
 	BUG_ON(buffer->transaction != NULL);
-	BUG_ON(buffer->user_data < alloc->buffer);
-	BUG_ON(buffer->user_data > alloc->buffer + alloc->buffer_size);
+	BUG_ON(buffer->user_data < alloc->vm_start);
+	BUG_ON(buffer->user_data > alloc->vm_start + alloc->buffer_size);
 
 	if (buffer->async_transaction) {
-		alloc->free_async_space += size + sizeof(struct binder_buffer);
-
+		alloc->free_async_space += buffer_size;
 		binder_alloc_debug(BINDER_DEBUG_BUFFER_ALLOC_ASYNC,
 			     "%d: binder_free_buf size %zd async free %zd\n",
 			      alloc->pid, size, alloc->free_async_space);
 	}
 
-	binder_update_page_range(alloc, 0,
-		(void __user *)PAGE_ALIGN((uintptr_t)buffer->user_data),
-		(void __user *)(((uintptr_t)
-			  buffer->user_data + buffer_size) & PAGE_MASK));
+	binder_lru_freelist_add(alloc, PAGE_ALIGN(buffer->user_data),
+				(buffer->user_data + buffer_size) & PAGE_MASK);
 
 	rb_erase(&buffer->rb_node, &alloc->allocated_buffers);
 	buffer->free = 1;
@@ -647,19 +790,93 @@ static void binder_free_buf_locked(struct binder_alloc *alloc,
 }
 
 /**
+ * binder_alloc_get_page() - get kernel pointer for given buffer offset
+ * @alloc: binder_alloc for this proc
+ * @buffer: binder buffer to be accessed
+ * @buffer_offset: offset into @buffer data
+ * @pgoffp: address to copy final page offset to
+ *
+ * Lookup the struct page corresponding to the address
+ * at @buffer_offset into @buffer->user_data. If @pgoffp is not
+ * NULL, the byte-offset into the page is written there.
+ *
+ * The caller is responsible to ensure that the offset points
+ * to a valid address within the @buffer and that @buffer is
+ * not freeable by the user. Since it can't be freed, we are
+ * guaranteed that the corresponding elements of @alloc->pages[]
+ * cannot change.
+ *
+ * Return: struct page
+ */
+static struct page *binder_alloc_get_page(struct binder_alloc *alloc,
+					  struct binder_buffer *buffer,
+					  binder_size_t buffer_offset,
+					  pgoff_t *pgoffp)
+{
+	binder_size_t buffer_space_offset = buffer_offset +
+		(buffer->user_data - alloc->vm_start);
+	pgoff_t pgoff = buffer_space_offset & ~PAGE_MASK;
+	size_t index = buffer_space_offset >> PAGE_SHIFT;
+
+	*pgoffp = pgoff;
+
+	return alloc->pages[index];
+}
+
+/**
+ * binder_alloc_clear_buf() - zero out buffer
+ * @alloc: binder_alloc for this proc
+ * @buffer: binder buffer to be cleared
+ *
+ * memset the given buffer to 0
+ */
+static void binder_alloc_clear_buf(struct binder_alloc *alloc,
+				   struct binder_buffer *buffer)
+{
+	size_t bytes = binder_alloc_buffer_size(alloc, buffer);
+	binder_size_t buffer_offset = 0;
+
+	while (bytes) {
+		unsigned long size;
+		struct page *page;
+		pgoff_t pgoff;
+
+		page = binder_alloc_get_page(alloc, buffer,
+					     buffer_offset, &pgoff);
+		size = min_t(size_t, bytes, PAGE_SIZE - pgoff);
+		memset_page(page, pgoff, 0, size);
+		bytes -= size;
+		buffer_offset += size;
+	}
+}
+
+/**
  * binder_alloc_free_buf() - free a binder buffer
  * @alloc:	binder_alloc for this proc
  * @buffer:	kernel pointer to buffer
  *
- * Free the buffer allocated via binder_alloc_new_buffer()
+ * Free the buffer allocated via binder_alloc_new_buf()
  */
 void binder_alloc_free_buf(struct binder_alloc *alloc,
 			    struct binder_buffer *buffer)
 {
+	/*
+	 * We could eliminate the call to binder_alloc_clear_buf()
+	 * from binder_alloc_deferred_release() by moving this to
+	 * binder_free_buf_locked(). However, that could
+	 * increase contention for the alloc mutex if clear_on_free
+	 * is used frequently for large buffers. The mutex is not
+	 * needed for correctness here.
+	 */
+	if (buffer->clear_on_free) {
+		binder_alloc_clear_buf(alloc, buffer);
+		buffer->clear_on_free = false;
+	}
 	mutex_lock(&alloc->mutex);
 	binder_free_buf_locked(alloc, buffer);
 	mutex_unlock(&alloc->mutex);
 }
+EXPORT_SYMBOL_IF_KUNIT(binder_alloc_free_buf);
 
 /**
  * binder_alloc_mmap_handler() - map virtual address space for proc
@@ -677,9 +894,15 @@ void binder_alloc_free_buf(struct binder_alloc *alloc,
 int binder_alloc_mmap_handler(struct binder_alloc *alloc,
 			      struct vm_area_struct *vma)
 {
-	int ret;
-	const char *failure_string;
 	struct binder_buffer *buffer;
+	const char *failure_string;
+	int ret;
+
+	if (unlikely(vma->vm_mm != alloc->mm)) {
+		ret = -EINVAL;
+		failure_string = "invalid vma->vm_mm";
+		goto err_invalid_mm;
+	}
 
 	mutex_lock(&binder_alloc_mmap_lock);
 	if (alloc->buffer_size) {
@@ -691,12 +914,12 @@ int binder_alloc_mmap_handler(struct binder_alloc *alloc,
 				   SZ_4M);
 	mutex_unlock(&binder_alloc_mmap_lock);
 
-	alloc->buffer = (void __user *)vma->vm_start;
+	alloc->vm_start = vma->vm_start;
 
-	alloc->pages = kcalloc(alloc->buffer_size / PAGE_SIZE,
-			       sizeof(alloc->pages[0]),
-			       GFP_KERNEL);
-	if (alloc->pages == NULL) {
+	alloc->pages = kvcalloc(alloc->buffer_size / PAGE_SIZE,
+				sizeof(alloc->pages[0]),
+				GFP_KERNEL);
+	if (!alloc->pages) {
 		ret = -ENOMEM;
 		failure_string = "alloc page array";
 		goto err_alloc_pages_failed;
@@ -709,32 +932,34 @@ int binder_alloc_mmap_handler(struct binder_alloc *alloc,
 		goto err_alloc_buf_struct_failed;
 	}
 
-	buffer->user_data = alloc->buffer;
+	buffer->user_data = alloc->vm_start;
 	list_add(&buffer->entry, &alloc->buffers);
 	buffer->free = 1;
 	binder_insert_free_buffer(alloc, buffer);
 	alloc->free_async_space = alloc->buffer_size / 2;
-	binder_alloc_set_vma(alloc, vma);
-	mmgrab(alloc->vma_vm_mm);
+
+	/* Signal binder_alloc is fully initialized */
+	binder_alloc_set_mapped(alloc, true);
 
 	return 0;
 
 err_alloc_buf_struct_failed:
-	kfree(alloc->pages);
+	kvfree(alloc->pages);
 	alloc->pages = NULL;
 err_alloc_pages_failed:
-	alloc->buffer = NULL;
+	alloc->vm_start = 0;
 	mutex_lock(&binder_alloc_mmap_lock);
 	alloc->buffer_size = 0;
 err_already_mapped:
 	mutex_unlock(&binder_alloc_mmap_lock);
+err_invalid_mm:
 	binder_alloc_debug(BINDER_DEBUG_USER_ERROR,
 			   "%s: %d %lx-%lx %s failed %d\n", __func__,
 			   alloc->pid, vma->vm_start, vma->vm_end,
 			   failure_string, ret);
 	return ret;
 }
-
+EXPORT_SYMBOL_IF_KUNIT(binder_alloc_mmap_handler);
 
 void binder_alloc_deferred_release(struct binder_alloc *alloc)
 {
@@ -744,7 +969,7 @@ void binder_alloc_deferred_release(struct binder_alloc *alloc)
 
 	buffers = 0;
 	mutex_lock(&alloc->mutex);
-	BUG_ON(alloc->vma);
+	BUG_ON(alloc->mapped);
 
 	while ((n = rb_first(&alloc->allocated_buffers))) {
 		buffer = rb_entry(n, struct binder_buffer, rb_node);
@@ -752,6 +977,10 @@ void binder_alloc_deferred_release(struct binder_alloc *alloc)
 		/* Transaction should already have been freed */
 		BUG_ON(buffer->transaction);
 
+		if (buffer->clear_on_free) {
+			binder_alloc_clear_buf(alloc, buffer);
+			buffer->clear_on_free = false;
+		}
 		binder_free_buf_locked(alloc, buffer);
 		buffers++;
 	}
@@ -771,42 +1000,35 @@ void binder_alloc_deferred_release(struct binder_alloc *alloc)
 		int i;
 
 		for (i = 0; i < alloc->buffer_size / PAGE_SIZE; i++) {
-			void __user *page_addr;
+			struct page *page;
 			bool on_lru;
 
-			if (!alloc->pages[i].page_ptr)
+			page = binder_get_installed_page(alloc, i);
+			if (!page)
 				continue;
 
-			on_lru = list_lru_del(&binder_alloc_lru,
-					      &alloc->pages[i].lru);
-			page_addr = alloc->buffer + i * PAGE_SIZE;
+			on_lru = list_lru_del(alloc->freelist,
+					      page_to_lru(page),
+					      page_to_nid(page),
+					      NULL);
 			binder_alloc_debug(BINDER_DEBUG_BUFFER_ALLOC,
-				     "%s: %d: page %d at %pK %s\n",
-				     __func__, alloc->pid, i, page_addr,
+				     "%s: %d: page %d %s\n",
+				     __func__, alloc->pid, i,
 				     on_lru ? "on lru" : "active");
-			__free_page(alloc->pages[i].page_ptr);
+			binder_free_page(page);
 			page_count++;
 		}
-		kfree(alloc->pages);
 	}
 	mutex_unlock(&alloc->mutex);
-	if (alloc->vma_vm_mm)
-		mmdrop(alloc->vma_vm_mm);
+	kvfree(alloc->pages);
+	if (alloc->mm)
+		mmdrop(alloc->mm);
 
 	binder_alloc_debug(BINDER_DEBUG_OPEN_CLOSE,
 		     "%s: %d buffers %d, pages %d\n",
 		     __func__, alloc->pid, buffers, page_count);
 }
-
-static void print_binder_buffer(struct seq_file *m, const char *prefix,
-				struct binder_buffer *buffer)
-{
-	seq_printf(m, "%s %d: %pK size %zd:%zd:%zd %s\n",
-		   prefix, buffer->debug_id, buffer->user_data,
-		   buffer->data_size, buffer->offsets_size,
-		   buffer->extra_buffers_size,
-		   buffer->transaction ? "active" : "delivered");
-}
+EXPORT_SYMBOL_IF_KUNIT(binder_alloc_deferred_release);
 
 /**
  * binder_alloc_print_allocated() - print buffer info
@@ -819,13 +1041,19 @@ static void print_binder_buffer(struct seq_file *m, const char *prefix,
 void binder_alloc_print_allocated(struct seq_file *m,
 				  struct binder_alloc *alloc)
 {
+	struct binder_buffer *buffer;
 	struct rb_node *n;
 
-	mutex_lock(&alloc->mutex);
-	for (n = rb_first(&alloc->allocated_buffers); n != NULL; n = rb_next(n))
-		print_binder_buffer(m, "  buffer",
-				    rb_entry(n, struct binder_buffer, rb_node));
-	mutex_unlock(&alloc->mutex);
+	guard(mutex)(&alloc->mutex);
+	for (n = rb_first(&alloc->allocated_buffers); n; n = rb_next(n)) {
+		buffer = rb_entry(n, struct binder_buffer, rb_node);
+		seq_printf(m, "  buffer %d: %lx size %zd:%zd:%zd %s\n",
+			   buffer->debug_id,
+			   buffer->user_data - alloc->vm_start,
+			   buffer->data_size, buffer->offsets_size,
+			   buffer->extra_buffers_size,
+			   buffer->transaction ? "active" : "delivered");
+	}
 }
 
 /**
@@ -836,7 +1064,7 @@ void binder_alloc_print_allocated(struct seq_file *m,
 void binder_alloc_print_pages(struct seq_file *m,
 			      struct binder_alloc *alloc)
 {
-	struct binder_lru_page *page;
+	struct page *page;
 	int i;
 	int active = 0;
 	int lru = 0;
@@ -847,12 +1075,12 @@ void binder_alloc_print_pages(struct seq_file *m,
 	 * Make sure the binder_alloc is fully initialized, otherwise we might
 	 * read inconsistent state.
 	 */
-	if (binder_alloc_get_vma(alloc) != NULL) {
+	if (binder_alloc_is_mapped(alloc)) {
 		for (i = 0; i < alloc->buffer_size / PAGE_SIZE; i++) {
-			page = &alloc->pages[i];
-			if (!page->page_ptr)
+			page = binder_get_installed_page(alloc, i);
+			if (!page)
 				free++;
-			else if (list_empty(&page->lru))
+			else if (list_empty(page_to_lru(page)))
 				active++;
 			else
 				lru++;
@@ -874,10 +1102,9 @@ int binder_alloc_get_allocated_count(struct binder_alloc *alloc)
 	struct rb_node *n;
 	int count = 0;
 
-	mutex_lock(&alloc->mutex);
+	guard(mutex)(&alloc->mutex);
 	for (n = rb_first(&alloc->allocated_buffers); n != NULL; n = rb_next(n))
 		count++;
-	mutex_unlock(&alloc->mutex);
 	return count;
 }
 
@@ -887,18 +1114,19 @@ int binder_alloc_get_allocated_count(struct binder_alloc *alloc)
  * @alloc: binder_alloc for this proc
  *
  * Called from binder_vma_close() when releasing address space.
- * Clears alloc->vma to prevent new incoming transactions from
+ * Clears alloc->mapped to prevent new incoming transactions from
  * allocating more buffers.
  */
 void binder_alloc_vma_close(struct binder_alloc *alloc)
 {
-	binder_alloc_set_vma(alloc, NULL);
+	binder_alloc_set_mapped(alloc, false);
 }
+EXPORT_SYMBOL_IF_KUNIT(binder_alloc_vma_close);
 
 /**
  * binder_alloc_free_page() - shrinker callback to free pages
  * @item:   item to free
- * @lock:   lock protecting the item
+ * @lru:    list_lru instance of the item
  * @cb_arg: callback argument
  *
  * Called from list_lru_walk() in binder_shrink_scan() to free
@@ -906,91 +1134,113 @@ void binder_alloc_vma_close(struct binder_alloc *alloc)
  */
 enum lru_status binder_alloc_free_page(struct list_head *item,
 				       struct list_lru_one *lru,
-				       spinlock_t *lock,
 				       void *cb_arg)
-	__must_hold(lock)
+	__must_hold(&lru->lock)
 {
-	struct mm_struct *mm = NULL;
-	struct binder_lru_page *page = container_of(item,
-						    struct binder_lru_page,
-						    lru);
-	struct binder_alloc *alloc;
-	uintptr_t page_addr;
-	size_t index;
+	struct binder_shrinker_mdata *mdata = container_of(item, typeof(*mdata), lru);
+	struct binder_alloc *alloc = mdata->alloc;
+	struct mm_struct *mm = alloc->mm;
 	struct vm_area_struct *vma;
+	struct page *page_to_free;
+	unsigned long page_addr;
+	int mm_locked = 0;
+	size_t index;
+
+	if (!mmget_not_zero(mm))
+		goto err_mmget;
+
+	index = mdata->page_index;
+	page_addr = alloc->vm_start + index * PAGE_SIZE;
+
+	/* attempt per-vma lock first */
+	vma = lock_vma_under_rcu(mm, page_addr);
+	if (!vma) {
+		/* fall back to mmap_lock */
+		if (!mmap_read_trylock(mm))
+			goto err_mmap_read_lock_failed;
+		mm_locked = 1;
+		vma = vma_lookup(mm, page_addr);
+	}
 
-	alloc = page->alloc;
 	if (!mutex_trylock(&alloc->mutex))
 		goto err_get_alloc_mutex_failed;
 
-	if (!page->page_ptr)
-		goto err_page_already_freed;
+	/*
+	 * Since a binder_alloc can only be mapped once, we ensure
+	 * the vma corresponds to this mapping by checking whether
+	 * the binder_alloc is still mapped.
+	 */
+	if (vma && !binder_alloc_is_mapped(alloc))
+		goto err_invalid_vma;
+
+	trace_binder_unmap_kernel_start(alloc, index);
 
-	index = page - alloc->pages;
-	page_addr = (uintptr_t)alloc->buffer + index * PAGE_SIZE;
+	page_to_free = alloc->pages[index];
+	binder_set_installed_page(alloc, index, NULL);
 
-	mm = alloc->vma_vm_mm;
-	if (!mmget_not_zero(mm))
-		goto err_mmget;
-	if (!down_read_trylock(&mm->mmap_sem))
-		goto err_down_read_mmap_sem_failed;
-	vma = binder_alloc_get_vma(alloc);
+	trace_binder_unmap_kernel_end(alloc, index);
 
 	list_lru_isolate(lru, item);
-	spin_unlock(lock);
+	spin_unlock(&lru->lock);
 
 	if (vma) {
 		trace_binder_unmap_user_start(alloc, index);
 
-		zap_page_range(vma, page_addr, PAGE_SIZE);
+		zap_page_range_single(vma, page_addr, PAGE_SIZE, NULL);
 
 		trace_binder_unmap_user_end(alloc, index);
 	}
-	up_read(&mm->mmap_sem);
-	mmput(mm);
-
-	trace_binder_unmap_kernel_start(alloc, index);
-
-	__free_page(page->page_ptr);
-	page->page_ptr = NULL;
-
-	trace_binder_unmap_kernel_end(alloc, index);
 
-	spin_lock(lock);
 	mutex_unlock(&alloc->mutex);
+	if (mm_locked)
+		mmap_read_unlock(mm);
+	else
+		vma_end_read(vma);
+	mmput_async(mm);
+	binder_free_page(page_to_free);
+
 	return LRU_REMOVED_RETRY;
 
-err_down_read_mmap_sem_failed:
-	mmput_async(mm);
-err_mmget:
-err_page_already_freed:
+err_invalid_vma:
 	mutex_unlock(&alloc->mutex);
 err_get_alloc_mutex_failed:
+	if (mm_locked)
+		mmap_read_unlock(mm);
+	else
+		vma_end_read(vma);
+err_mmap_read_lock_failed:
+	mmput_async(mm);
+err_mmget:
 	return LRU_SKIP;
 }
+EXPORT_SYMBOL_IF_KUNIT(binder_alloc_free_page);
 
 static unsigned long
 binder_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
 {
-	unsigned long ret = list_lru_count(&binder_alloc_lru);
-	return ret;
+	return list_lru_count(&binder_freelist);
 }
 
 static unsigned long
 binder_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
 {
-	unsigned long ret;
-
-	ret = list_lru_walk(&binder_alloc_lru, binder_alloc_free_page,
+	return list_lru_walk(&binder_freelist, binder_alloc_free_page,
 			    NULL, sc->nr_to_scan);
-	return ret;
 }
 
-static struct shrinker binder_shrinker = {
-	.count_objects = binder_shrink_count,
-	.scan_objects = binder_shrink_scan,
-	.seeks = DEFAULT_SEEKS,
-};
+static struct shrinker *binder_shrinker;
+
+VISIBLE_IF_KUNIT void __binder_alloc_init(struct binder_alloc *alloc,
+					  struct list_lru *freelist)
+{
+	alloc->pid = current->group_leader->pid;
+	alloc->mm = current->mm;
+	mmgrab(alloc->mm);
+	mutex_init(&alloc->mutex);
+	INIT_LIST_HEAD(&alloc->buffers);
+	alloc->freelist = freelist;
+}
+EXPORT_SYMBOL_IF_KUNIT(__binder_alloc_init);
 
 /**
  * binder_alloc_init() - called by binder_open() for per-proc initialization
@@ -1001,21 +1251,35 @@ static struct shrinker binder_shrinker = {
  */
 void binder_alloc_init(struct binder_alloc *alloc)
 {
-	alloc->pid = current->group_leader->pid;
-	mutex_init(&alloc->mutex);
-	INIT_LIST_HEAD(&alloc->buffers);
+	__binder_alloc_init(alloc, &binder_freelist);
 }
 
 int binder_alloc_shrinker_init(void)
 {
-	int ret = list_lru_init(&binder_alloc_lru);
+	int ret;
 
-	if (ret == 0) {
-		ret = register_shrinker(&binder_shrinker);
-		if (ret)
-			list_lru_destroy(&binder_alloc_lru);
+	ret = list_lru_init(&binder_freelist);
+	if (ret)
+		return ret;
+
+	binder_shrinker = shrinker_alloc(0, "android-binder");
+	if (!binder_shrinker) {
+		list_lru_destroy(&binder_freelist);
+		return -ENOMEM;
 	}
-	return ret;
+
+	binder_shrinker->count_objects = binder_shrink_count;
+	binder_shrinker->scan_objects = binder_shrink_scan;
+
+	shrinker_register(binder_shrinker);
+
+	return 0;
+}
+
+void binder_alloc_shrinker_exit(void)
+{
+	shrinker_free(binder_shrinker);
+	list_lru_destroy(&binder_freelist);
 }
 
 /**
@@ -1051,41 +1315,6 @@ static inline bool check_buffer(struct binder_alloc *alloc,
 }
 
 /**
- * binder_alloc_get_page() - get kernel pointer for given buffer offset
- * @alloc: binder_alloc for this proc
- * @buffer: binder buffer to be accessed
- * @buffer_offset: offset into @buffer data
- * @pgoffp: address to copy final page offset to
- *
- * Lookup the struct page corresponding to the address
- * at @buffer_offset into @buffer->user_data. If @pgoffp is not
- * NULL, the byte-offset into the page is written there.
- *
- * The caller is responsible to ensure that the offset points
- * to a valid address within the @buffer and that @buffer is
- * not freeable by the user. Since it can't be freed, we are
- * guaranteed that the corresponding elements of @alloc->pages[]
- * cannot change.
- *
- * Return: struct page
- */
-static struct page *binder_alloc_get_page(struct binder_alloc *alloc,
-					  struct binder_buffer *buffer,
-					  binder_size_t buffer_offset,
-					  pgoff_t *pgoffp)
-{
-	binder_size_t buffer_space_offset = buffer_offset +
-		(buffer->user_data - alloc->buffer);
-	pgoff_t pgoff = buffer_space_offset & ~PAGE_MASK;
-	size_t index = buffer_space_offset >> PAGE_SHIFT;
-	struct binder_lru_page *lru_page;
-
-	lru_page = &alloc->pages[index];
-	*pgoffp = pgoff;
-	return lru_page->page_ptr;
-}
-
-/**
  * binder_alloc_copy_user_to_buffer() - copy src user to tgt user
  * @alloc: binder_alloc for this proc
  * @buffer: binder buffer to be accessed
@@ -1117,9 +1346,9 @@ binder_alloc_copy_user_to_buffer(struct binder_alloc *alloc,
 		page = binder_alloc_get_page(alloc, buffer,
 					     buffer_offset, &pgoff);
 		size = min_t(size_t, bytes, PAGE_SIZE - pgoff);
-		kptr = kmap(page) + pgoff;
+		kptr = kmap_local_page(page) + pgoff;
 		ret = copy_from_user(kptr, from, size);
-		kunmap(page);
+		kunmap_local(kptr);
 		if (ret)
 			return bytes - size + ret;
 		bytes -= size;
@@ -1144,23 +1373,14 @@ static int binder_alloc_do_buffer_copy(struct binder_alloc *alloc,
 		unsigned long size;
 		struct page *page;
 		pgoff_t pgoff;
-		void *tmpptr;
-		void *base_ptr;
 
 		page = binder_alloc_get_page(alloc, buffer,
 					     buffer_offset, &pgoff);
 		size = min_t(size_t, bytes, PAGE_SIZE - pgoff);
-		base_ptr = kmap_atomic(page);
-		tmpptr = base_ptr + pgoff;
 		if (to_buffer)
-			memcpy(tmpptr, ptr, size);
+			memcpy_to_page(page, pgoff, ptr, size);
 		else
-			memcpy(ptr, tmpptr, size);
-		/*
-		 * kunmap_atomic() takes care of flushing the cache
-		 * if this device has VIVT cache arch
-		 */
-		kunmap_atomic(base_ptr);
+			memcpy_from_page(ptr, page, pgoff, size);
 		bytes -= size;
 		pgoff = 0;
 		ptr = ptr + size;
@@ -1188,4 +1408,3 @@ int binder_alloc_copy_from_buffer(struct binder_alloc *alloc,
 	return binder_alloc_do_buffer_copy(alloc, false, buffer, buffer_offset,
 					   dest, bytes);
 }
-
diff --git a/drivers/android/binder_alloc.h b/drivers/android/binder_alloc.h
index db9c1b984695..d6f1f6f2d00e 100644
--- a/drivers/android/binder_alloc.h
+++ b/drivers/android/binder_alloc.h
@@ -15,7 +15,6 @@
 #include <linux/list_lru.h>
 #include <uapi/linux/android/binder.h>
 
-extern struct list_lru binder_alloc_lru;
 struct binder_transaction;
 
 /**
@@ -23,8 +22,11 @@ struct binder_transaction;
  * @entry:              entry alloc->buffers
  * @rb_node:            node for allocated_buffers/free_buffers rb trees
  * @free:               %true if buffer is free
+ * @clear_on_free:      %true if buffer must be zeroed after use
  * @allow_user_free:    %true if user is allowed to free buffer
  * @async_transaction:  %true if buffer is in use for an async txn
+ * @oneway_spam_suspect: %true if total async allocate size just exceed
+ * spamming detect threshold
  * @debug_id:           unique ID for debugging
  * @transaction:        pointer to associated struct binder_transaction
  * @target_node:        struct binder_node associated with this buffer
@@ -32,6 +34,7 @@ struct binder_transaction;
  * @offsets_size:       size of array of offsets
  * @extra_buffers_size: size of space for other objects (like sg lists)
  * @user_data:          user pointer to base of buffer space
+ * @pid:                pid to attribute the buffer to (caller)
  *
  * Bookkeeping structure for binder transaction buffers
  */
@@ -40,49 +43,61 @@ struct binder_buffer {
 	struct rb_node rb_node; /* free entry by size or allocated entry */
 				/* by address */
 	unsigned free:1;
+	unsigned clear_on_free:1;
 	unsigned allow_user_free:1;
 	unsigned async_transaction:1;
-	unsigned debug_id:29;
-
+	unsigned oneway_spam_suspect:1;
+	unsigned debug_id:27;
 	struct binder_transaction *transaction;
-
 	struct binder_node *target_node;
 	size_t data_size;
 	size_t offsets_size;
 	size_t extra_buffers_size;
-	void __user *user_data;
+	unsigned long user_data;
+	int pid;
 };
 
 /**
- * struct binder_lru_page - page object used for binder shrinker
- * @page_ptr: pointer to physical page in mmap'd space
- * @lru:      entry in binder_alloc_lru
- * @alloc:    binder_alloc for a proc
+ * struct binder_shrinker_mdata - binder metadata used to reclaim pages
+ * @lru:         LRU entry in binder_freelist
+ * @alloc:       binder_alloc owning the page to reclaim
+ * @page_index:  offset in @alloc->pages[] into the page to reclaim
  */
-struct binder_lru_page {
+struct binder_shrinker_mdata {
 	struct list_head lru;
-	struct page *page_ptr;
 	struct binder_alloc *alloc;
+	unsigned long page_index;
 };
 
+static inline struct list_head *page_to_lru(struct page *p)
+{
+	struct binder_shrinker_mdata *mdata;
+
+	mdata = (struct binder_shrinker_mdata *)page_private(p);
+
+	return &mdata->lru;
+}
+
 /**
  * struct binder_alloc - per-binder proc state for binder allocator
- * @vma:                vm_area_struct passed to mmap_handler
- *                      (invarient after mmap)
- * @tsk:                tid for task that called init for this proc
- *                      (invariant after init)
- * @vma_vm_mm:          copy of vma->vm_mm (invarient after mmap)
- * @buffer:             base of per-proc address space mapped via mmap
+ * @mutex:              protects binder_alloc fields
+ * @mm:                 copy of task->mm (invariant after open)
+ * @vm_start:           base of per-proc address space mapped via mmap
  * @buffers:            list of all buffers for this proc
  * @free_buffers:       rb tree of buffers available for allocation
  *                      sorted by size
  * @allocated_buffers:  rb tree of allocated buffers sorted by address
  * @free_async_space:   VA space available for async buffers. This is
  *                      initialized at mmap time to 1/2 the full VA space
- * @pages:              array of binder_lru_page
+ * @pages:              array of struct page *
+ * @freelist:           lru list to use for free pages (invariant after init)
  * @buffer_size:        size of address space specified via mmap
  * @pid:                pid for associated binder_proc (invariant after init)
  * @pages_high:         high watermark of offset in @pages
+ * @mapped:             whether the vm area is mapped, each binder instance is
+ *                      allowed a single mapping throughout its lifetime
+ * @oneway_spam_detected: %true if oneway spam detection fired, clear that
+ * flag once the async buffer has returned to a healthy state
  *
  * Bookkeeping structure for per-proc address space management for binder
  * buffers. It is normally initialized during binder_init() and binder_mmap()
@@ -91,47 +106,44 @@ struct binder_lru_page {
  */
 struct binder_alloc {
 	struct mutex mutex;
-	struct vm_area_struct *vma;
-	struct mm_struct *vma_vm_mm;
-	void __user *buffer;
+	struct mm_struct *mm;
+	unsigned long vm_start;
 	struct list_head buffers;
 	struct rb_root free_buffers;
 	struct rb_root allocated_buffers;
 	size_t free_async_space;
-	struct binder_lru_page *pages;
+	struct page **pages;
+	struct list_lru *freelist;
 	size_t buffer_size;
-	uint32_t buffer_free;
 	int pid;
 	size_t pages_high;
+	bool mapped;
+	bool oneway_spam_detected;
 };
 
-#ifdef CONFIG_ANDROID_BINDER_IPC_SELFTEST
-void binder_selftest_alloc(struct binder_alloc *alloc);
-#else
-static inline void binder_selftest_alloc(struct binder_alloc *alloc) {}
-#endif
 enum lru_status binder_alloc_free_page(struct list_head *item,
 				       struct list_lru_one *lru,
-				       spinlock_t *lock, void *cb_arg);
-extern struct binder_buffer *binder_alloc_new_buf(struct binder_alloc *alloc,
-						  size_t data_size,
-						  size_t offsets_size,
-						  size_t extra_buffers_size,
-						  int is_async);
-extern void binder_alloc_init(struct binder_alloc *alloc);
-extern int binder_alloc_shrinker_init(void);
-extern void binder_alloc_vma_close(struct binder_alloc *alloc);
-extern struct binder_buffer *
+				       void *cb_arg);
+struct binder_buffer *binder_alloc_new_buf(struct binder_alloc *alloc,
+					   size_t data_size,
+					   size_t offsets_size,
+					   size_t extra_buffers_size,
+					   int is_async);
+void binder_alloc_init(struct binder_alloc *alloc);
+int binder_alloc_shrinker_init(void);
+void binder_alloc_shrinker_exit(void);
+void binder_alloc_vma_close(struct binder_alloc *alloc);
+struct binder_buffer *
 binder_alloc_prepare_to_free(struct binder_alloc *alloc,
-			     uintptr_t user_ptr);
-extern void binder_alloc_free_buf(struct binder_alloc *alloc,
-				  struct binder_buffer *buffer);
-extern int binder_alloc_mmap_handler(struct binder_alloc *alloc,
-				     struct vm_area_struct *vma);
-extern void binder_alloc_deferred_release(struct binder_alloc *alloc);
-extern int binder_alloc_get_allocated_count(struct binder_alloc *alloc);
-extern void binder_alloc_print_allocated(struct seq_file *m,
-					 struct binder_alloc *alloc);
+			     unsigned long user_ptr);
+void binder_alloc_free_buf(struct binder_alloc *alloc,
+			   struct binder_buffer *buffer);
+int binder_alloc_mmap_handler(struct binder_alloc *alloc,
+			      struct vm_area_struct *vma);
+void binder_alloc_deferred_release(struct binder_alloc *alloc);
+int binder_alloc_get_allocated_count(struct binder_alloc *alloc);
+void binder_alloc_print_allocated(struct seq_file *m,
+				  struct binder_alloc *alloc);
 void binder_alloc_print_pages(struct seq_file *m,
 			      struct binder_alloc *alloc);
 
@@ -144,12 +156,8 @@ void binder_alloc_print_pages(struct seq_file *m,
 static inline size_t
 binder_alloc_get_free_async_space(struct binder_alloc *alloc)
 {
-	size_t free_async_space;
-
-	mutex_lock(&alloc->mutex);
-	free_async_space = alloc->free_async_space;
-	mutex_unlock(&alloc->mutex);
-	return free_async_space;
+	guard(mutex)(&alloc->mutex);
+	return alloc->free_async_space;
 }
 
 unsigned long
@@ -171,5 +179,11 @@ int binder_alloc_copy_from_buffer(struct binder_alloc *alloc,
 				  binder_size_t buffer_offset,
 				  size_t bytes);
 
+#if IS_ENABLED(CONFIG_KUNIT)
+void __binder_alloc_init(struct binder_alloc *alloc, struct list_lru *freelist);
+size_t binder_alloc_buffer_size(struct binder_alloc *alloc,
+				struct binder_buffer *buffer);
+#endif
+
 #endif /* _LINUX_BINDER_ALLOC_H */
 
diff --git a/drivers/android/binder_alloc_selftest.c b/drivers/android/binder_alloc_selftest.c
deleted file mode 100644
index 4151d9938255..000000000000
--- a/drivers/android/binder_alloc_selftest.c
+++ /dev/null
@@ -1,302 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/* binder_alloc_selftest.c
- *
- * Android IPC Subsystem
- *
- * Copyright (C) 2017 Google, Inc.
- */
-
-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
-
-#include <linux/mm_types.h>
-#include <linux/err.h>
-#include "binder_alloc.h"
-
-#define BUFFER_NUM 5
-#define BUFFER_MIN_SIZE (PAGE_SIZE / 8)
-
-static bool binder_selftest_run = true;
-static int binder_selftest_failures;
-static DEFINE_MUTEX(binder_selftest_lock);
-
-/**
- * enum buf_end_align_type - Page alignment of a buffer
- * end with regard to the end of the previous buffer.
- *
- * In the pictures below, buf2 refers to the buffer we
- * are aligning. buf1 refers to previous buffer by addr.
- * Symbol [ means the start of a buffer, ] means the end
- * of a buffer, and | means page boundaries.
- */
-enum buf_end_align_type {
-	/**
-	 * @SAME_PAGE_UNALIGNED: The end of this buffer is on
-	 * the same page as the end of the previous buffer and
-	 * is not page aligned. Examples:
-	 * buf1 ][ buf2 ][ ...
-	 * buf1 ]|[ buf2 ][ ...
-	 */
-	SAME_PAGE_UNALIGNED = 0,
-	/**
-	 * @SAME_PAGE_ALIGNED: When the end of the previous buffer
-	 * is not page aligned, the end of this buffer is on the
-	 * same page as the end of the previous buffer and is page
-	 * aligned. When the previous buffer is page aligned, the
-	 * end of this buffer is aligned to the next page boundary.
-	 * Examples:
-	 * buf1 ][ buf2 ]| ...
-	 * buf1 ]|[ buf2 ]| ...
-	 */
-	SAME_PAGE_ALIGNED,
-	/**
-	 * @NEXT_PAGE_UNALIGNED: The end of this buffer is on
-	 * the page next to the end of the previous buffer and
-	 * is not page aligned. Examples:
-	 * buf1 ][ buf2 | buf2 ][ ...
-	 * buf1 ]|[ buf2 | buf2 ][ ...
-	 */
-	NEXT_PAGE_UNALIGNED,
-	/**
-	 * @NEXT_PAGE_ALIGNED: The end of this buffer is on
-	 * the page next to the end of the previous buffer and
-	 * is page aligned. Examples:
-	 * buf1 ][ buf2 | buf2 ]| ...
-	 * buf1 ]|[ buf2 | buf2 ]| ...
-	 */
-	NEXT_PAGE_ALIGNED,
-	/**
-	 * @NEXT_NEXT_UNALIGNED: The end of this buffer is on
-	 * the page that follows the page after the end of the
-	 * previous buffer and is not page aligned. Examples:
-	 * buf1 ][ buf2 | buf2 | buf2 ][ ...
-	 * buf1 ]|[ buf2 | buf2 | buf2 ][ ...
-	 */
-	NEXT_NEXT_UNALIGNED,
-	LOOP_END,
-};
-
-static void pr_err_size_seq(size_t *sizes, int *seq)
-{
-	int i;
-
-	pr_err("alloc sizes: ");
-	for (i = 0; i < BUFFER_NUM; i++)
-		pr_cont("[%zu]", sizes[i]);
-	pr_cont("\n");
-	pr_err("free seq: ");
-	for (i = 0; i < BUFFER_NUM; i++)
-		pr_cont("[%d]", seq[i]);
-	pr_cont("\n");
-}
-
-static bool check_buffer_pages_allocated(struct binder_alloc *alloc,
-					 struct binder_buffer *buffer,
-					 size_t size)
-{
-	void __user *page_addr;
-	void __user *end;
-	int page_index;
-
-	end = (void __user *)PAGE_ALIGN((uintptr_t)buffer->user_data + size);
-	page_addr = buffer->user_data;
-	for (; page_addr < end; page_addr += PAGE_SIZE) {
-		page_index = (page_addr - alloc->buffer) / PAGE_SIZE;
-		if (!alloc->pages[page_index].page_ptr ||
-		    !list_empty(&alloc->pages[page_index].lru)) {
-			pr_err("expect alloc but is %s at page index %d\n",
-			       alloc->pages[page_index].page_ptr ?
-			       "lru" : "free", page_index);
-			return false;
-		}
-	}
-	return true;
-}
-
-static void binder_selftest_alloc_buf(struct binder_alloc *alloc,
-				      struct binder_buffer *buffers[],
-				      size_t *sizes, int *seq)
-{
-	int i;
-
-	for (i = 0; i < BUFFER_NUM; i++) {
-		buffers[i] = binder_alloc_new_buf(alloc, sizes[i], 0, 0, 0);
-		if (IS_ERR(buffers[i]) ||
-		    !check_buffer_pages_allocated(alloc, buffers[i],
-						  sizes[i])) {
-			pr_err_size_seq(sizes, seq);
-			binder_selftest_failures++;
-		}
-	}
-}
-
-static void binder_selftest_free_buf(struct binder_alloc *alloc,
-				     struct binder_buffer *buffers[],
-				     size_t *sizes, int *seq, size_t end)
-{
-	int i;
-
-	for (i = 0; i < BUFFER_NUM; i++)
-		binder_alloc_free_buf(alloc, buffers[seq[i]]);
-
-	for (i = 0; i < end / PAGE_SIZE; i++) {
-		/**
-		 * Error message on a free page can be false positive
-		 * if binder shrinker ran during binder_alloc_free_buf
-		 * calls above.
-		 */
-		if (list_empty(&alloc->pages[i].lru)) {
-			pr_err_size_seq(sizes, seq);
-			pr_err("expect lru but is %s at page index %d\n",
-			       alloc->pages[i].page_ptr ? "alloc" : "free", i);
-			binder_selftest_failures++;
-		}
-	}
-}
-
-static void binder_selftest_free_page(struct binder_alloc *alloc)
-{
-	int i;
-	unsigned long count;
-
-	while ((count = list_lru_count(&binder_alloc_lru))) {
-		list_lru_walk(&binder_alloc_lru, binder_alloc_free_page,
-			      NULL, count);
-	}
-
-	for (i = 0; i < (alloc->buffer_size / PAGE_SIZE); i++) {
-		if (alloc->pages[i].page_ptr) {
-			pr_err("expect free but is %s at page index %d\n",
-			       list_empty(&alloc->pages[i].lru) ?
-			       "alloc" : "lru", i);
-			binder_selftest_failures++;
-		}
-	}
-}
-
-static void binder_selftest_alloc_free(struct binder_alloc *alloc,
-				       size_t *sizes, int *seq, size_t end)
-{
-	struct binder_buffer *buffers[BUFFER_NUM];
-
-	binder_selftest_alloc_buf(alloc, buffers, sizes, seq);
-	binder_selftest_free_buf(alloc, buffers, sizes, seq, end);
-
-	/* Allocate from lru. */
-	binder_selftest_alloc_buf(alloc, buffers, sizes, seq);
-	if (list_lru_count(&binder_alloc_lru))
-		pr_err("lru list should be empty but is not\n");
-
-	binder_selftest_free_buf(alloc, buffers, sizes, seq, end);
-	binder_selftest_free_page(alloc);
-}
-
-static bool is_dup(int *seq, int index, int val)
-{
-	int i;
-
-	for (i = 0; i < index; i++) {
-		if (seq[i] == val)
-			return true;
-	}
-	return false;
-}
-
-/* Generate BUFFER_NUM factorial free orders. */
-static void binder_selftest_free_seq(struct binder_alloc *alloc,
-				     size_t *sizes, int *seq,
-				     int index, size_t end)
-{
-	int i;
-
-	if (index == BUFFER_NUM) {
-		binder_selftest_alloc_free(alloc, sizes, seq, end);
-		return;
-	}
-	for (i = 0; i < BUFFER_NUM; i++) {
-		if (is_dup(seq, index, i))
-			continue;
-		seq[index] = i;
-		binder_selftest_free_seq(alloc, sizes, seq, index + 1, end);
-	}
-}
-
-static void binder_selftest_alloc_size(struct binder_alloc *alloc,
-				       size_t *end_offset)
-{
-	int i;
-	int seq[BUFFER_NUM] = {0};
-	size_t front_sizes[BUFFER_NUM];
-	size_t back_sizes[BUFFER_NUM];
-	size_t last_offset, offset = 0;
-
-	for (i = 0; i < BUFFER_NUM; i++) {
-		last_offset = offset;
-		offset = end_offset[i];
-		front_sizes[i] = offset - last_offset;
-		back_sizes[BUFFER_NUM - i - 1] = front_sizes[i];
-	}
-	/*
-	 * Buffers share the first or last few pages.
-	 * Only BUFFER_NUM - 1 buffer sizes are adjustable since
-	 * we need one giant buffer before getting to the last page.
-	 */
-	back_sizes[0] += alloc->buffer_size - end_offset[BUFFER_NUM - 1];
-	binder_selftest_free_seq(alloc, front_sizes, seq, 0,
-				 end_offset[BUFFER_NUM - 1]);
-	binder_selftest_free_seq(alloc, back_sizes, seq, 0, alloc->buffer_size);
-}
-
-static void binder_selftest_alloc_offset(struct binder_alloc *alloc,
-					 size_t *end_offset, int index)
-{
-	int align;
-	size_t end, prev;
-
-	if (index == BUFFER_NUM) {
-		binder_selftest_alloc_size(alloc, end_offset);
-		return;
-	}
-	prev = index == 0 ? 0 : end_offset[index - 1];
-	end = prev;
-
-	BUILD_BUG_ON(BUFFER_MIN_SIZE * BUFFER_NUM >= PAGE_SIZE);
-
-	for (align = SAME_PAGE_UNALIGNED; align < LOOP_END; align++) {
-		if (align % 2)
-			end = ALIGN(end, PAGE_SIZE);
-		else
-			end += BUFFER_MIN_SIZE;
-		end_offset[index] = end;
-		binder_selftest_alloc_offset(alloc, end_offset, index + 1);
-	}
-}
-
-/**
- * binder_selftest_alloc() - Test alloc and free of buffer pages.
- * @alloc: Pointer to alloc struct.
- *
- * Allocate BUFFER_NUM buffers to cover all page alignment cases,
- * then free them in all orders possible. Check that pages are
- * correctly allocated, put onto lru when buffers are freed, and
- * are freed when binder_alloc_free_page is called.
- */
-void binder_selftest_alloc(struct binder_alloc *alloc)
-{
-	size_t end_offset[BUFFER_NUM];
-
-	if (!binder_selftest_run)
-		return;
-	mutex_lock(&binder_selftest_lock);
-	if (!binder_selftest_run || !alloc->vma)
-		goto done;
-	pr_info("STARTED\n");
-	binder_selftest_alloc_offset(alloc, end_offset, 0);
-	binder_selftest_run = false;
-	if (binder_selftest_failures > 0)
-		pr_info("%d tests FAILED\n", binder_selftest_failures);
-	else
-		pr_info("PASSED\n");
-
-done:
-	mutex_unlock(&binder_selftest_lock);
-}
diff --git a/drivers/android/binder_internal.h b/drivers/android/binder_internal.h
index 283d3cb9c16e..342574bfd28a 100644
--- a/drivers/android/binder_internal.h
+++ b/drivers/android/binder_internal.h
@@ -3,7 +3,6 @@
 #ifndef _LINUX_BINDER_INTERNAL_H
 #define _LINUX_BINDER_INTERNAL_H
 
-#include <linux/export.h>
 #include <linux/fs.h>
 #include <linux/list.h>
 #include <linux/miscdevice.h>
@@ -12,6 +11,9 @@
 #include <linux/stddef.h>
 #include <linux/types.h>
 #include <linux/uidgid.h>
+#include <uapi/linux/android/binderfs.h>
+#include "binder_alloc.h"
+#include "dbitmap.h"
 
 struct binder_context {
 	struct binder_node *binder_context_mgr_node;
@@ -22,8 +24,7 @@ struct binder_context {
 
 /**
  * struct binder_device - information about a binder device node
- * @hlist:          list of binder devices (only used for devices requested via
- *                  CONFIG_ANDROID_BINDER_DEVICES)
+ * @hlist:          list of binder devices
  * @miscdev:        information about a binder character device node
  * @context:        binder context information
  * @binderfs_inode: This is the inode of the root dentry of the super block
@@ -80,7 +81,6 @@ extern bool is_binderfs_device(const struct inode *inode);
 extern struct dentry *binderfs_create_file(struct dentry *dir, const char *name,
 					   const struct file_operations *fops,
 					   void *data);
-extern void binderfs_remove_file(struct dentry *dentry);
 #else
 static inline bool is_binderfs_device(const struct inode *inode)
 {
@@ -93,7 +93,6 @@ static inline struct dentry *binderfs_create_file(struct dentry *dir,
 {
 	return NULL;
 }
-static inline void binderfs_remove_file(struct dentry *dentry) {}
 #endif
 
 #ifdef CONFIG_ANDROID_BINDERFS
@@ -105,42 +104,494 @@ static inline int __init init_binderfs(void)
 }
 #endif
 
-int binder_stats_show(struct seq_file *m, void *unused);
-DEFINE_SHOW_ATTRIBUTE(binder_stats);
+struct binder_debugfs_entry {
+	const char *name;
+	umode_t mode;
+	const struct file_operations *fops;
+	void *data;
+};
+
+extern const struct binder_debugfs_entry binder_debugfs_entries[];
+
+#define binder_for_each_debugfs_entry(entry)	\
+	for ((entry) = binder_debugfs_entries;	\
+	     (entry)->name;			\
+	     (entry)++)
 
-int binder_state_show(struct seq_file *m, void *unused);
-DEFINE_SHOW_ATTRIBUTE(binder_state);
+enum binder_stat_types {
+	BINDER_STAT_PROC,
+	BINDER_STAT_THREAD,
+	BINDER_STAT_NODE,
+	BINDER_STAT_REF,
+	BINDER_STAT_DEATH,
+	BINDER_STAT_TRANSACTION,
+	BINDER_STAT_TRANSACTION_COMPLETE,
+	BINDER_STAT_FREEZE,
+	BINDER_STAT_COUNT
+};
 
-int binder_transactions_show(struct seq_file *m, void *unused);
-DEFINE_SHOW_ATTRIBUTE(binder_transactions);
+struct binder_stats {
+	atomic_t br[_IOC_NR(BR_CLEAR_FREEZE_NOTIFICATION_DONE) + 1];
+	atomic_t bc[_IOC_NR(BC_FREEZE_NOTIFICATION_DONE) + 1];
+	atomic_t obj_created[BINDER_STAT_COUNT];
+	atomic_t obj_deleted[BINDER_STAT_COUNT];
+};
 
-int binder_transaction_log_show(struct seq_file *m, void *unused);
-DEFINE_SHOW_ATTRIBUTE(binder_transaction_log);
+/**
+ * struct binder_work - work enqueued on a worklist
+ * @entry:             node enqueued on list
+ * @type:              type of work to be performed
+ *
+ * There are separate work lists for proc, thread, and node (async).
+ */
+struct binder_work {
+	struct list_head entry;
 
-struct binder_transaction_log_entry {
+	enum binder_work_type {
+		BINDER_WORK_TRANSACTION = 1,
+		BINDER_WORK_TRANSACTION_COMPLETE,
+		BINDER_WORK_TRANSACTION_PENDING,
+		BINDER_WORK_TRANSACTION_ONEWAY_SPAM_SUSPECT,
+		BINDER_WORK_RETURN_ERROR,
+		BINDER_WORK_NODE,
+		BINDER_WORK_DEAD_BINDER,
+		BINDER_WORK_DEAD_BINDER_AND_CLEAR,
+		BINDER_WORK_CLEAR_DEATH_NOTIFICATION,
+		BINDER_WORK_FROZEN_BINDER,
+		BINDER_WORK_CLEAR_FREEZE_NOTIFICATION,
+	} type;
+};
+
+struct binder_error {
+	struct binder_work work;
+	uint32_t cmd;
+};
+
+/**
+ * struct binder_node - binder node bookkeeping
+ * @debug_id:             unique ID for debugging
+ *                        (invariant after initialized)
+ * @lock:                 lock for node fields
+ * @work:                 worklist element for node work
+ *                        (protected by @proc->inner_lock)
+ * @rb_node:              element for proc->nodes tree
+ *                        (protected by @proc->inner_lock)
+ * @dead_node:            element for binder_dead_nodes list
+ *                        (protected by binder_dead_nodes_lock)
+ * @proc:                 binder_proc that owns this node
+ *                        (invariant after initialized)
+ * @refs:                 list of references on this node
+ *                        (protected by @lock)
+ * @internal_strong_refs: used to take strong references when
+ *                        initiating a transaction
+ *                        (protected by @proc->inner_lock if @proc
+ *                        and by @lock)
+ * @local_weak_refs:      weak user refs from local process
+ *                        (protected by @proc->inner_lock if @proc
+ *                        and by @lock)
+ * @local_strong_refs:    strong user refs from local process
+ *                        (protected by @proc->inner_lock if @proc
+ *                        and by @lock)
+ * @tmp_refs:             temporary kernel refs
+ *                        (protected by @proc->inner_lock while @proc
+ *                        is valid, and by binder_dead_nodes_lock
+ *                        if @proc is NULL. During inc/dec and node release
+ *                        it is also protected by @lock to provide safety
+ *                        as the node dies and @proc becomes NULL)
+ * @ptr:                  userspace pointer for node
+ *                        (invariant, no lock needed)
+ * @cookie:               userspace cookie for node
+ *                        (invariant, no lock needed)
+ * @has_strong_ref:       userspace notified of strong ref
+ *                        (protected by @proc->inner_lock if @proc
+ *                        and by @lock)
+ * @pending_strong_ref:   userspace has acked notification of strong ref
+ *                        (protected by @proc->inner_lock if @proc
+ *                        and by @lock)
+ * @has_weak_ref:         userspace notified of weak ref
+ *                        (protected by @proc->inner_lock if @proc
+ *                        and by @lock)
+ * @pending_weak_ref:     userspace has acked notification of weak ref
+ *                        (protected by @proc->inner_lock if @proc
+ *                        and by @lock)
+ * @has_async_transaction: async transaction to node in progress
+ *                        (protected by @lock)
+ * @accept_fds:           file descriptor operations supported for node
+ *                        (invariant after initialized)
+ * @min_priority:         minimum scheduling priority
+ *                        (invariant after initialized)
+ * @txn_security_ctx:     require sender's security context
+ *                        (invariant after initialized)
+ * @async_todo:           list of async work items
+ *                        (protected by @proc->inner_lock)
+ *
+ * Bookkeeping structure for binder nodes.
+ */
+struct binder_node {
 	int debug_id;
-	int debug_id_done;
-	int call_type;
-	int from_proc;
-	int from_thread;
-	int target_handle;
-	int to_proc;
-	int to_thread;
-	int to_node;
-	int data_size;
-	int offsets_size;
-	int return_error_line;
-	uint32_t return_error;
-	uint32_t return_error_param;
-	char context_name[BINDERFS_MAX_NAME + 1];
-};
-
-struct binder_transaction_log {
-	atomic_t cur;
-	bool full;
-	struct binder_transaction_log_entry entry[32];
-};
-
-extern struct binder_transaction_log binder_transaction_log;
-extern struct binder_transaction_log binder_transaction_log_failed;
+	spinlock_t lock;
+	struct binder_work work;
+	union {
+		struct rb_node rb_node;
+		struct hlist_node dead_node;
+	};
+	struct binder_proc *proc;
+	struct hlist_head refs;
+	int internal_strong_refs;
+	int local_weak_refs;
+	int local_strong_refs;
+	int tmp_refs;
+	binder_uintptr_t ptr;
+	binder_uintptr_t cookie;
+	struct {
+		/*
+		 * bitfield elements protected by
+		 * proc inner_lock
+		 */
+		u8 has_strong_ref:1;
+		u8 pending_strong_ref:1;
+		u8 has_weak_ref:1;
+		u8 pending_weak_ref:1;
+	};
+	struct {
+		/*
+		 * invariant after initialization
+		 */
+		u8 accept_fds:1;
+		u8 txn_security_ctx:1;
+		u8 min_priority;
+	};
+	bool has_async_transaction;
+	struct list_head async_todo;
+};
+
+struct binder_ref_death {
+	/**
+	 * @work: worklist element for death notifications
+	 *        (protected by inner_lock of the proc that
+	 *        this ref belongs to)
+	 */
+	struct binder_work work;
+	binder_uintptr_t cookie;
+};
+
+struct binder_ref_freeze {
+	struct binder_work work;
+	binder_uintptr_t cookie;
+	bool is_frozen:1;
+	bool sent:1;
+	bool resend:1;
+};
+
+/**
+ * struct binder_ref_data - binder_ref counts and id
+ * @debug_id:        unique ID for the ref
+ * @desc:            unique userspace handle for ref
+ * @strong:          strong ref count (debugging only if not locked)
+ * @weak:            weak ref count (debugging only if not locked)
+ *
+ * Structure to hold ref count and ref id information. Since
+ * the actual ref can only be accessed with a lock, this structure
+ * is used to return information about the ref to callers of
+ * ref inc/dec functions.
+ */
+struct binder_ref_data {
+	int debug_id;
+	uint32_t desc;
+	int strong;
+	int weak;
+};
+
+/**
+ * struct binder_ref - struct to track references on nodes
+ * @data:        binder_ref_data containing id, handle, and current refcounts
+ * @rb_node_desc: node for lookup by @data.desc in proc's rb_tree
+ * @rb_node_node: node for lookup by @node in proc's rb_tree
+ * @node_entry:  list entry for node->refs list in target node
+ *               (protected by @node->lock)
+ * @proc:        binder_proc containing ref
+ * @node:        binder_node of target node. When cleaning up a
+ *               ref for deletion in binder_cleanup_ref, a non-NULL
+ *               @node indicates the node must be freed
+ * @death:       pointer to death notification (ref_death) if requested
+ *               (protected by @node->lock)
+ * @freeze:      pointer to freeze notification (ref_freeze) if requested
+ *               (protected by @node->lock)
+ *
+ * Structure to track references from procA to target node (on procB). This
+ * structure is unsafe to access without holding @proc->outer_lock.
+ */
+struct binder_ref {
+	/* Lookups needed: */
+	/*   node + proc => ref (transaction) */
+	/*   desc + proc => ref (transaction, inc/dec ref) */
+	/*   node => refs + procs (proc exit) */
+	struct binder_ref_data data;
+	struct rb_node rb_node_desc;
+	struct rb_node rb_node_node;
+	struct hlist_node node_entry;
+	struct binder_proc *proc;
+	struct binder_node *node;
+	struct binder_ref_death *death;
+	struct binder_ref_freeze *freeze;
+};
+
+/**
+ * struct binder_proc - binder process bookkeeping
+ * @proc_node:            element for binder_procs list
+ * @threads:              rbtree of binder_threads in this proc
+ *                        (protected by @inner_lock)
+ * @nodes:                rbtree of binder nodes associated with
+ *                        this proc ordered by node->ptr
+ *                        (protected by @inner_lock)
+ * @refs_by_desc:         rbtree of refs ordered by ref->desc
+ *                        (protected by @outer_lock)
+ * @refs_by_node:         rbtree of refs ordered by ref->node
+ *                        (protected by @outer_lock)
+ * @waiting_threads:      threads currently waiting for proc work
+ *                        (protected by @inner_lock)
+ * @pid                   PID of group_leader of process
+ *                        (invariant after initialized)
+ * @tsk                   task_struct for group_leader of process
+ *                        (invariant after initialized)
+ * @cred                  struct cred associated with the `struct file`
+ *                        in binder_open()
+ *                        (invariant after initialized)
+ * @deferred_work_node:   element for binder_deferred_list
+ *                        (protected by binder_deferred_lock)
+ * @deferred_work:        bitmap of deferred work to perform
+ *                        (protected by binder_deferred_lock)
+ * @outstanding_txns:     number of transactions to be transmitted before
+ *                        processes in freeze_wait are woken up
+ *                        (protected by @inner_lock)
+ * @is_dead:              process is dead and awaiting free
+ *                        when outstanding transactions are cleaned up
+ *                        (protected by @inner_lock)
+ * @is_frozen:            process is frozen and unable to service
+ *                        binder transactions
+ *                        (protected by @inner_lock)
+ * @sync_recv:            process received sync transactions since last frozen
+ *                        bit 0: received sync transaction after being frozen
+ *                        bit 1: new pending sync transaction during freezing
+ *                        (protected by @inner_lock)
+ * @async_recv:           process received async transactions since last frozen
+ *                        (protected by @inner_lock)
+ * @freeze_wait:          waitqueue of processes waiting for all outstanding
+ *                        transactions to be processed
+ *                        (protected by @inner_lock)
+ * @dmap                  dbitmap to manage available reference descriptors
+ *                        (protected by @outer_lock)
+ * @todo:                 list of work for this process
+ *                        (protected by @inner_lock)
+ * @stats:                per-process binder statistics
+ *                        (atomics, no lock needed)
+ * @delivered_death:      list of delivered death notification
+ *                        (protected by @inner_lock)
+ * @delivered_freeze:     list of delivered freeze notification
+ *                        (protected by @inner_lock)
+ * @max_threads:          cap on number of binder threads
+ *                        (protected by @inner_lock)
+ * @requested_threads:    number of binder threads requested but not
+ *                        yet started. In current implementation, can
+ *                        only be 0 or 1.
+ *                        (protected by @inner_lock)
+ * @requested_threads_started: number binder threads started
+ *                        (protected by @inner_lock)
+ * @tmp_ref:              temporary reference to indicate proc is in use
+ *                        (protected by @inner_lock)
+ * @default_priority:     default scheduler priority
+ *                        (invariant after initialized)
+ * @debugfs_entry:        debugfs node
+ * @alloc:                binder allocator bookkeeping
+ * @context:              binder_context for this proc
+ *                        (invariant after initialized)
+ * @inner_lock:           can nest under outer_lock and/or node lock
+ * @outer_lock:           no nesting under innor or node lock
+ *                        Lock order: 1) outer, 2) node, 3) inner
+ * @binderfs_entry:       process-specific binderfs log file
+ * @oneway_spam_detection_enabled: process enabled oneway spam detection
+ *                        or not
+ *
+ * Bookkeeping structure for binder processes
+ */
+struct binder_proc {
+	struct hlist_node proc_node;
+	struct rb_root threads;
+	struct rb_root nodes;
+	struct rb_root refs_by_desc;
+	struct rb_root refs_by_node;
+	struct list_head waiting_threads;
+	int pid;
+	struct task_struct *tsk;
+	const struct cred *cred;
+	struct hlist_node deferred_work_node;
+	int deferred_work;
+	int outstanding_txns;
+	bool is_dead;
+	bool is_frozen;
+	bool sync_recv;
+	bool async_recv;
+	wait_queue_head_t freeze_wait;
+	struct dbitmap dmap;
+	struct list_head todo;
+	struct binder_stats stats;
+	struct list_head delivered_death;
+	struct list_head delivered_freeze;
+	u32 max_threads;
+	int requested_threads;
+	int requested_threads_started;
+	int tmp_ref;
+	long default_priority;
+	struct dentry *debugfs_entry;
+	struct binder_alloc alloc;
+	struct binder_context *context;
+	spinlock_t inner_lock;
+	spinlock_t outer_lock;
+	struct dentry *binderfs_entry;
+	bool oneway_spam_detection_enabled;
+};
+
+/**
+ * struct binder_thread - binder thread bookkeeping
+ * @proc:                 binder process for this thread
+ *                        (invariant after initialization)
+ * @rb_node:              element for proc->threads rbtree
+ *                        (protected by @proc->inner_lock)
+ * @waiting_thread_node:  element for @proc->waiting_threads list
+ *                        (protected by @proc->inner_lock)
+ * @pid:                  PID for this thread
+ *                        (invariant after initialization)
+ * @looper:               bitmap of looping state
+ *                        (only accessed by this thread)
+ * @looper_needs_return:  looping thread needs to exit driver
+ *                        (no lock needed)
+ * @transaction_stack:    stack of in-progress transactions for this thread
+ *                        (protected by @proc->inner_lock)
+ * @todo:                 list of work to do for this thread
+ *                        (protected by @proc->inner_lock)
+ * @process_todo:         whether work in @todo should be processed
+ *                        (protected by @proc->inner_lock)
+ * @return_error:         transaction errors reported by this thread
+ *                        (only accessed by this thread)
+ * @reply_error:          transaction errors reported by target thread
+ *                        (protected by @proc->inner_lock)
+ * @ee:                   extended error information from this thread
+ *                        (protected by @proc->inner_lock)
+ * @wait:                 wait queue for thread work
+ * @stats:                per-thread statistics
+ *                        (atomics, no lock needed)
+ * @tmp_ref:              temporary reference to indicate thread is in use
+ *                        (atomic since @proc->inner_lock cannot
+ *                        always be acquired)
+ * @is_dead:              thread is dead and awaiting free
+ *                        when outstanding transactions are cleaned up
+ *                        (protected by @proc->inner_lock)
+ *
+ * Bookkeeping structure for binder threads.
+ */
+struct binder_thread {
+	struct binder_proc *proc;
+	struct rb_node rb_node;
+	struct list_head waiting_thread_node;
+	int pid;
+	int looper;              /* only modified by this thread */
+	bool looper_need_return; /* can be written by other thread */
+	struct binder_transaction *transaction_stack;
+	struct list_head todo;
+	bool process_todo;
+	struct binder_error return_error;
+	struct binder_error reply_error;
+	struct binder_extended_error ee;
+	wait_queue_head_t wait;
+	struct binder_stats stats;
+	atomic_t tmp_ref;
+	bool is_dead;
+};
+
+/**
+ * struct binder_txn_fd_fixup - transaction fd fixup list element
+ * @fixup_entry:          list entry
+ * @file:                 struct file to be associated with new fd
+ * @offset:               offset in buffer data to this fixup
+ * @target_fd:            fd to use by the target to install @file
+ *
+ * List element for fd fixups in a transaction. Since file
+ * descriptors need to be allocated in the context of the
+ * target process, we pass each fd to be processed in this
+ * struct.
+ */
+struct binder_txn_fd_fixup {
+	struct list_head fixup_entry;
+	struct file *file;
+	size_t offset;
+	int target_fd;
+};
+
+struct binder_transaction {
+	int debug_id;
+	struct binder_work work;
+	struct binder_thread *from;
+	pid_t from_pid;
+	pid_t from_tid;
+	struct binder_transaction *from_parent;
+	struct binder_proc *to_proc;
+	struct binder_thread *to_thread;
+	struct binder_transaction *to_parent;
+	unsigned is_async:1;
+	unsigned is_reply:1;
+
+	struct binder_buffer *buffer;
+	unsigned int    code;
+	unsigned int    flags;
+	long    priority;
+	long    saved_priority;
+	kuid_t  sender_euid;
+	ktime_t start_time;
+	struct list_head fd_fixups;
+	binder_uintptr_t security_ctx;
+	/**
+	 * @lock:  protects @from, @to_proc, and @to_thread
+	 *
+	 * @from, @to_proc, and @to_thread can be set to NULL
+	 * during thread teardown
+	 */
+	spinlock_t lock;
+};
+
+/**
+ * struct binder_object - union of flat binder object types
+ * @hdr:   generic object header
+ * @fbo:   binder object (nodes and refs)
+ * @fdo:   file descriptor object
+ * @bbo:   binder buffer pointer
+ * @fdao:  file descriptor array
+ *
+ * Used for type-independent object copies
+ */
+struct binder_object {
+	union {
+		struct binder_object_header hdr;
+		struct flat_binder_object fbo;
+		struct binder_fd_object fdo;
+		struct binder_buffer_object bbo;
+		struct binder_fd_array_object fdao;
+	};
+};
+
+/**
+ * Add a binder device to binder_devices
+ * @device: the new binder device to add to the global list
+ */
+void binder_add_device(struct binder_device *device);
+
+/**
+ * Remove a binder device to binder_devices
+ * @device: the binder device to remove from the global list
+ */
+void binder_remove_device(struct binder_device *device);
+
+#if IS_ENABLED(CONFIG_KUNIT)
+vm_fault_t binder_vm_fault(struct vm_fault *vmf);
+#endif
+
 #endif /* _LINUX_BINDER_INTERNAL_H */
diff --git a/drivers/android/binder_netlink.c b/drivers/android/binder_netlink.c
new file mode 100644
index 000000000000..81e8432b5904
--- /dev/null
+++ b/drivers/android/binder_netlink.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
+/* Do not edit directly, auto-generated from: */
+/*	Documentation/netlink/specs/binder.yaml */
+/* YNL-GEN kernel source */
+/* To regenerate run: tools/net/ynl/ynl-regen.sh */
+
+#include <net/netlink.h>
+#include <net/genetlink.h>
+
+#include "binder_netlink.h"
+
+#include <uapi/linux/android/binder_netlink.h>
+
+/* Ops table for binder */
+static const struct genl_split_ops binder_nl_ops[] = {
+};
+
+static const struct genl_multicast_group binder_nl_mcgrps[] = {
+	[BINDER_NLGRP_REPORT] = { "report", },
+};
+
+struct genl_family binder_nl_family __ro_after_init = {
+	.name		= BINDER_FAMILY_NAME,
+	.version	= BINDER_FAMILY_VERSION,
+	.netnsok	= true,
+	.parallel_ops	= true,
+	.module		= THIS_MODULE,
+	.split_ops	= binder_nl_ops,
+	.n_split_ops	= ARRAY_SIZE(binder_nl_ops),
+	.mcgrps		= binder_nl_mcgrps,
+	.n_mcgrps	= ARRAY_SIZE(binder_nl_mcgrps),
+};
diff --git a/drivers/android/binder_netlink.h b/drivers/android/binder_netlink.h
new file mode 100644
index 000000000000..57399942a5e3
--- /dev/null
+++ b/drivers/android/binder_netlink.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
+/* Do not edit directly, auto-generated from: */
+/*	Documentation/netlink/specs/binder.yaml */
+/* YNL-GEN kernel header */
+/* To regenerate run: tools/net/ynl/ynl-regen.sh */
+
+#ifndef _LINUX_BINDER_GEN_H
+#define _LINUX_BINDER_GEN_H
+
+#include <net/netlink.h>
+#include <net/genetlink.h>
+
+#include <uapi/linux/android/binder_netlink.h>
+
+enum {
+	BINDER_NLGRP_REPORT,
+};
+
+extern struct genl_family binder_nl_family;
+
+#endif /* _LINUX_BINDER_GEN_H */
diff --git a/drivers/android/binder_trace.h b/drivers/android/binder_trace.h
index 6731c3cd8145..fa5eb61cf580 100644
--- a/drivers/android/binder_trace.h
+++ b/drivers/android/binder_trace.h
@@ -34,27 +34,6 @@ TRACE_EVENT(binder_ioctl,
 	TP_printk("cmd=0x%x arg=0x%lx", __entry->cmd, __entry->arg)
 );
 
-DECLARE_EVENT_CLASS(binder_lock_class,
-	TP_PROTO(const char *tag),
-	TP_ARGS(tag),
-	TP_STRUCT__entry(
-		__field(const char *, tag)
-	),
-	TP_fast_assign(
-		__entry->tag = tag;
-	),
-	TP_printk("tag=%s", __entry->tag)
-);
-
-#define DEFINE_BINDER_LOCK_EVENT(name)	\
-DEFINE_EVENT(binder_lock_class, name,	\
-	TP_PROTO(const char *func), \
-	TP_ARGS(func))
-
-DEFINE_BINDER_LOCK_EVENT(binder_lock);
-DEFINE_BINDER_LOCK_EVENT(binder_locked);
-DEFINE_BINDER_LOCK_EVENT(binder_unlock);
-
 DECLARE_EVENT_CLASS(binder_function_return_class,
 	TP_PROTO(int ret),
 	TP_ARGS(ret),
@@ -95,6 +74,35 @@ TRACE_EVENT(binder_wait_for_work,
 		  __entry->thread_todo)
 );
 
+TRACE_EVENT(binder_txn_latency_free,
+	TP_PROTO(struct binder_transaction *t,
+		 int from_proc, int from_thread,
+		 int to_proc, int to_thread),
+	TP_ARGS(t, from_proc, from_thread, to_proc, to_thread),
+	TP_STRUCT__entry(
+		__field(int, debug_id)
+		__field(int, from_proc)
+		__field(int, from_thread)
+		__field(int, to_proc)
+		__field(int, to_thread)
+		__field(unsigned int, code)
+		__field(unsigned int, flags)
+	),
+	TP_fast_assign(
+		__entry->debug_id = t->debug_id;
+		__entry->from_proc = from_proc;
+		__entry->from_thread = from_thread;
+		__entry->to_proc = to_proc;
+		__entry->to_thread = to_thread;
+		__entry->code = t->code;
+		__entry->flags = t->flags;
+	),
+	TP_printk("transaction=%d from %d:%d to %d:%d flags=0x%x code=0x%x",
+		  __entry->debug_id, __entry->from_proc, __entry->from_thread,
+		  __entry->to_proc, __entry->to_thread, __entry->code,
+		  __entry->flags)
+);
+
 TRACE_EVENT(binder_transaction,
 	TP_PROTO(bool reply, struct binder_transaction *t,
 		 struct binder_node *target_node),
@@ -282,9 +290,13 @@ DEFINE_EVENT(binder_buffer_class, binder_transaction_failed_buffer_release,
 	TP_PROTO(struct binder_buffer *buffer),
 	TP_ARGS(buffer));
 
+DEFINE_EVENT(binder_buffer_class, binder_transaction_update_buffer_release,
+	     TP_PROTO(struct binder_buffer *buffer),
+	     TP_ARGS(buffer));
+
 TRACE_EVENT(binder_update_page_range,
 	TP_PROTO(struct binder_alloc *alloc, bool allocate,
-		 void __user *start, void __user *end),
+		 unsigned long start, unsigned long end),
 	TP_ARGS(alloc, allocate, start, end),
 	TP_STRUCT__entry(
 		__field(int, proc)
@@ -295,7 +307,7 @@ TRACE_EVENT(binder_update_page_range,
 	TP_fast_assign(
 		__entry->proc = alloc->pid;
 		__entry->allocate = allocate;
-		__entry->offset = start - alloc->buffer;
+		__entry->offset = start - alloc->vm_start;
 		__entry->size = end - start;
 	),
 	TP_printk("proc=%d allocate=%d offset=%zu size=%zu",
@@ -390,6 +402,43 @@ TRACE_EVENT(binder_return,
 			  "unknown")
 );
 
+TRACE_EVENT(binder_netlink_report,
+	TP_PROTO(const char *context,
+		 struct binder_transaction *t,
+		 u32 data_size,
+		 u32 error),
+	TP_ARGS(context, t, data_size, error),
+	TP_STRUCT__entry(
+		__field(const char *, context)
+		__field(u32, error)
+		__field(int, from_pid)
+		__field(int, from_tid)
+		__field(int, to_pid)
+		__field(int, to_tid)
+		__field(bool, is_reply)
+		__field(unsigned int, flags)
+		__field(unsigned int, code)
+		__field(size_t, data_size)
+	),
+	TP_fast_assign(
+		__entry->context = context;
+		__entry->error = error;
+		__entry->from_pid = t->from_pid;
+		__entry->from_tid = t->from_tid;
+		__entry->to_pid = t->to_proc ? t->to_proc->pid : 0;
+		__entry->to_tid = t->to_thread ? t->to_thread->pid : 0;
+		__entry->is_reply = t->is_reply;
+		__entry->flags = t->flags;
+		__entry->code = t->code;
+		__entry->data_size = data_size;
+	),
+	TP_printk("from %d:%d to %d:%d context=%s error=%d is_reply=%d flags=0x%x code=0x%x size=%zu",
+		  __entry->from_pid, __entry->from_tid,
+		  __entry->to_pid, __entry->to_tid,
+		  __entry->context, __entry->error, __entry->is_reply,
+		  __entry->flags, __entry->code, __entry->data_size)
+);
+
 #endif /* _BINDER_TRACE_H */
 
 #undef TRACE_INCLUDE_PATH
diff --git a/drivers/android/binderfs.c b/drivers/android/binderfs.c
index 9ecad74183a3..b46bcb91072d 100644
--- a/drivers/android/binderfs.c
+++ b/drivers/android/binderfs.c
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+// SPDX-License-Identifier: GPL-2.0
 
 #include <linux/compiler_types.h>
 #include <linux/errno.h>
@@ -19,7 +19,6 @@
 #include <linux/mutex.h>
 #include <linux/mount.h>
 #include <linux/fs_parser.h>
-#include <linux/radix-tree.h>
 #include <linux/sched.h>
 #include <linux/seq_file.h>
 #include <linux/slab.h>
@@ -30,7 +29,6 @@
 #include <linux/uaccess.h>
 #include <linux/user_namespace.h>
 #include <linux/xarray.h>
-#include <uapi/asm-generic/errno-base.h>
 #include <uapi/linux/android/binder.h>
 #include <uapi/linux/android/binderfs.h>
 
@@ -39,7 +37,6 @@
 #define FIRST_INODE 1
 #define SECOND_INODE 2
 #define INODE_OFFSET 3
-#define INTSTRLEN 21
 #define BINDERFS_MAX_MINOR (1U << MINORBITS)
 /* Ensure that the initial ipc namespace always has devices available. */
 #define BINDERFS_MAX_MINOR_CAPPED (BINDERFS_MAX_MINOR - 4)
@@ -58,17 +55,31 @@ enum binderfs_stats_mode {
 	binderfs_stats_mode_global,
 };
 
+struct binder_features {
+	bool oneway_spam_detection;
+	bool extended_error;
+	bool freeze_notification;
+	bool transaction_report;
+};
+
 static const struct constant_table binderfs_param_stats[] = {
 	{ "global", binderfs_stats_mode_global },
 	{}
 };
 
-const struct fs_parameter_spec binderfs_fs_parameters[] = {
+static const struct fs_parameter_spec binderfs_fs_parameters[] = {
 	fsparam_u32("max",	Opt_max),
 	fsparam_enum("stats",	Opt_stats_mode, binderfs_param_stats),
 	{}
 };
 
+static struct binder_features binder_features = {
+	.oneway_spam_detection = true,
+	.extended_error = true,
+	.freeze_notification = true,
+	.transaction_report = true,
+};
+
 static inline struct binderfs_info *BINDERFS_SB(const struct super_block *sb)
 {
 	return sb->s_fs_info;
@@ -85,7 +96,7 @@ bool is_binderfs_device(const struct inode *inode)
 /**
  * binderfs_binder_device_create - allocate inode from super block of a
  *                                 binderfs mount
- * @ref_inode: inode from wich the super block will be taken
+ * @ref_inode: inode from which the super block will be taken
  * @userp:     buffer to copy information about new device for userspace to
  * @req:       struct binderfs_device as copied from userspace
  *
@@ -108,7 +119,6 @@ static int binderfs_binder_device_create(struct inode *ref_inode,
 	struct dentry *dentry, *root;
 	struct binder_device *device;
 	char *name = NULL;
-	size_t name_len;
 	struct inode *inode = NULL;
 	struct super_block *sb = ref_inode->i_sb;
 	struct binderfs_info *info = sb->s_fs_info;
@@ -144,7 +154,7 @@ static int binderfs_binder_device_create(struct inode *ref_inode,
 		goto err;
 
 	inode->i_ino = minor + INODE_OFFSET;
-	inode->i_mtime = inode->i_atime = inode->i_ctime = current_time(inode);
+	simple_inode_init_ts(inode);
 	init_special_inode(inode, S_IFCHR | 0600,
 			   MKDEV(MAJOR(binderfs_dev), minor));
 	inode->i_fop = &binder_fops;
@@ -152,9 +162,7 @@ static int binderfs_binder_device_create(struct inode *ref_inode,
 	inode->i_gid = info->root_gid;
 
 	req->name[BINDERFS_MAX_NAME] = '\0'; /* NUL-terminate */
-	name_len = strlen(req->name);
-	/* Make sure to include terminating NUL byte */
-	name = kmemdup(req->name, name_len + 1, GFP_KERNEL);
+	name = kstrdup(req->name, GFP_KERNEL);
 	if (!name)
 		goto err;
 
@@ -175,28 +183,17 @@ static int binderfs_binder_device_create(struct inode *ref_inode,
 	}
 
 	root = sb->s_root;
-	inode_lock(d_inode(root));
-
-	/* look it up */
-	dentry = lookup_one_len(name, root, name_len);
+	dentry = simple_start_creating(root, name);
 	if (IS_ERR(dentry)) {
-		inode_unlock(d_inode(root));
 		ret = PTR_ERR(dentry);
 		goto err;
 	}
-
-	if (d_really_is_positive(dentry)) {
-		/* already exists */
-		dput(dentry);
-		inode_unlock(d_inode(root));
-		ret = -EEXIST;
-		goto err;
-	}
-
 	inode->i_private = device;
-	d_instantiate(dentry, inode);
+	d_make_persistent(dentry, inode);
 	fsnotify_create(root->d_inode, dentry);
-	inode_unlock(d_inode(root));
+	simple_done_creating(dentry);
+
+	binder_add_device(device);
 
 	return 0;
 
@@ -213,14 +210,17 @@ err:
 }
 
 /**
- * binderfs_ctl_ioctl - handle binder device node allocation requests
+ * binder_ctl_ioctl - handle binder device node allocation requests
+ * @file: The file pointer for the binder-control device node.
+ * @cmd: The ioctl command.
+ * @arg: The ioctl argument.
  *
  * The request handler for the binder-control device. All requests operate on
  * the binderfs mount the binder-control device resides in:
  * - BINDER_CTL_ADD
  *   Allocate a new binder device.
  *
- * Return: 0 on success, negative errno on failure
+ * Return: %0 on success, negative errno on failure.
  */
 static long binder_ctl_ioctl(struct file *file, unsigned int cmd,
 			     unsigned long arg)
@@ -263,6 +263,7 @@ static void binderfs_evict_inode(struct inode *inode)
 	mutex_unlock(&binderfs_minors_mutex);
 
 	if (refcount_dec_and_test(&device->ref)) {
+		binder_remove_device(device);
 		kfree(device->context.name);
 		kfree(device);
 	}
@@ -330,31 +331,21 @@ static int binderfs_show_options(struct seq_file *seq, struct dentry *root)
 	return 0;
 }
 
-static void binderfs_put_super(struct super_block *sb)
-{
-	struct binderfs_info *info = sb->s_fs_info;
-
-	if (info && info->ipc_ns)
-		put_ipc_ns(info->ipc_ns);
-
-	kfree(info);
-	sb->s_fs_info = NULL;
-}
-
 static const struct super_operations binderfs_super_ops = {
 	.evict_inode    = binderfs_evict_inode,
 	.show_options	= binderfs_show_options,
 	.statfs         = simple_statfs,
-	.put_super	= binderfs_put_super,
 };
 
 static inline bool is_binderfs_control_device(const struct dentry *dentry)
 {
 	struct binderfs_info *info = dentry->d_sb->s_fs_info;
+
 	return info->control_dentry == dentry;
 }
 
-static int binderfs_rename(struct inode *old_dir, struct dentry *old_dentry,
+static int binderfs_rename(struct mnt_idmap *idmap,
+			   struct inode *old_dir, struct dentry *old_dentry,
 			   struct inode *new_dir, struct dentry *new_dentry,
 			   unsigned int flags)
 {
@@ -362,7 +353,8 @@ static int binderfs_rename(struct inode *old_dir, struct dentry *old_dentry,
 	    is_binderfs_control_device(new_dentry))
 		return -EPERM;
 
-	return simple_rename(old_dir, old_dentry, new_dir, new_dentry, flags);
+	return simple_rename(idmap, old_dir, old_dentry, new_dir,
+			     new_dentry, flags);
 }
 
 static int binderfs_unlink(struct inode *dir, struct dentry *dentry)
@@ -408,12 +400,6 @@ static int binderfs_binder_ctl_create(struct super_block *sb)
 	if (!device)
 		return -ENOMEM;
 
-	/* If we have already created a binder-control node, return. */
-	if (info->control_dentry) {
-		ret = 0;
-		goto out;
-	}
-
 	ret = -ENOMEM;
 	inode = new_inode(sb);
 	if (!inode)
@@ -432,7 +418,7 @@ static int binderfs_binder_ctl_create(struct super_block *sb)
 	}
 
 	inode->i_ino = SECOND_INODE;
-	inode->i_mtime = inode->i_atime = inode->i_ctime = current_time(inode);
+	simple_inode_init_ts(inode);
 	init_special_inode(inode, S_IFCHR | 0600,
 			   MKDEV(MAJOR(binderfs_dev), minor));
 	inode->i_fop = &binder_ctl_fops;
@@ -449,7 +435,8 @@ static int binderfs_binder_ctl_create(struct super_block *sb)
 
 	inode->i_private = device;
 	info->control_dentry = dentry;
-	d_add(dentry, inode);
+	d_make_persistent(dentry, inode);
+	dput(dentry);
 
 	return 0;
 
@@ -474,44 +461,11 @@ static struct inode *binderfs_make_inode(struct super_block *sb, int mode)
 	if (ret) {
 		ret->i_ino = iunique(sb, BINDERFS_MAX_MINOR + INODE_OFFSET);
 		ret->i_mode = mode;
-		ret->i_atime = ret->i_mtime = ret->i_ctime = current_time(ret);
+		simple_inode_init_ts(ret);
 	}
 	return ret;
 }
 
-static struct dentry *binderfs_create_dentry(struct dentry *parent,
-					     const char *name)
-{
-	struct dentry *dentry;
-
-	dentry = lookup_one_len(name, parent, strlen(name));
-	if (IS_ERR(dentry))
-		return dentry;
-
-	/* Return error if the file/dir already exists. */
-	if (d_really_is_positive(dentry)) {
-		dput(dentry);
-		return ERR_PTR(-EEXIST);
-	}
-
-	return dentry;
-}
-
-void binderfs_remove_file(struct dentry *dentry)
-{
-	struct inode *parent_inode;
-
-	parent_inode = d_inode(dentry->d_parent);
-	inode_lock(parent_inode);
-	if (simple_positive(dentry)) {
-		dget(dentry);
-		simple_unlink(parent_inode, dentry);
-		d_delete(dentry);
-		dput(dentry);
-	}
-	inode_unlock(parent_inode);
-}
-
 struct dentry *binderfs_create_file(struct dentry *parent, const char *name,
 				    const struct file_operations *fops,
 				    void *data)
@@ -521,28 +475,24 @@ struct dentry *binderfs_create_file(struct dentry *parent, const char *name,
 	struct super_block *sb;
 
 	parent_inode = d_inode(parent);
-	inode_lock(parent_inode);
 
-	dentry = binderfs_create_dentry(parent, name);
+	dentry = simple_start_creating(parent, name);
 	if (IS_ERR(dentry))
-		goto out;
+		return dentry;
 
 	sb = parent_inode->i_sb;
 	new_inode = binderfs_make_inode(sb, S_IFREG | 0444);
 	if (!new_inode) {
-		dput(dentry);
-		dentry = ERR_PTR(-ENOMEM);
-		goto out;
+		simple_done_creating(dentry);
+		return ERR_PTR(-ENOMEM);
 	}
 
 	new_inode->i_fop = fops;
 	new_inode->i_private = data;
-	d_instantiate(dentry, new_inode);
+	d_make_persistent(dentry, new_inode);
 	fsnotify_create(parent_inode, dentry);
-
-out:
-	inode_unlock(parent_inode);
-	return dentry;
+	simple_done_creating(dentry);
+	return dentry; // borrowed
 }
 
 static struct dentry *binderfs_create_dir(struct dentry *parent,
@@ -553,36 +503,78 @@ static struct dentry *binderfs_create_dir(struct dentry *parent,
 	struct super_block *sb;
 
 	parent_inode = d_inode(parent);
-	inode_lock(parent_inode);
 
-	dentry = binderfs_create_dentry(parent, name);
+	dentry = simple_start_creating(parent, name);
 	if (IS_ERR(dentry))
-		goto out;
+		return dentry;
 
 	sb = parent_inode->i_sb;
 	new_inode = binderfs_make_inode(sb, S_IFDIR | 0755);
 	if (!new_inode) {
-		dput(dentry);
-		dentry = ERR_PTR(-ENOMEM);
-		goto out;
+		simple_done_creating(dentry);
+		return ERR_PTR(-ENOMEM);
 	}
 
 	new_inode->i_fop = &simple_dir_operations;
 	new_inode->i_op = &simple_dir_inode_operations;
 
 	set_nlink(new_inode, 2);
-	d_instantiate(dentry, new_inode);
+	d_make_persistent(dentry, new_inode);
 	inc_nlink(parent_inode);
 	fsnotify_mkdir(parent_inode, dentry);
-
-out:
-	inode_unlock(parent_inode);
+	simple_done_creating(dentry);
 	return dentry;
 }
 
+static int binder_features_show(struct seq_file *m, void *unused)
+{
+	bool *feature = m->private;
+
+	seq_printf(m, "%d\n", *feature);
+
+	return 0;
+}
+DEFINE_SHOW_ATTRIBUTE(binder_features);
+
+static int init_binder_features(struct super_block *sb)
+{
+	struct dentry *dentry, *dir;
+
+	dir = binderfs_create_dir(sb->s_root, "features");
+	if (IS_ERR(dir))
+		return PTR_ERR(dir);
+
+	dentry = binderfs_create_file(dir, "oneway_spam_detection",
+				      &binder_features_fops,
+				      &binder_features.oneway_spam_detection);
+	if (IS_ERR(dentry))
+		return PTR_ERR(dentry);
+
+	dentry = binderfs_create_file(dir, "extended_error",
+				      &binder_features_fops,
+				      &binder_features.extended_error);
+	if (IS_ERR(dentry))
+		return PTR_ERR(dentry);
+
+	dentry = binderfs_create_file(dir, "freeze_notification",
+				      &binder_features_fops,
+				      &binder_features.freeze_notification);
+	if (IS_ERR(dentry))
+		return PTR_ERR(dentry);
+
+	dentry = binderfs_create_file(dir, "transaction_report",
+				      &binder_features_fops,
+				      &binder_features.transaction_report);
+	if (IS_ERR(dentry))
+		return PTR_ERR(dentry);
+
+	return 0;
+}
+
 static int init_binder_logs(struct super_block *sb)
 {
 	struct dentry *binder_logs_root_dir, *dentry, *proc_log_dir;
+	const struct binder_debugfs_entry *db_entry;
 	struct binderfs_info *info;
 	int ret = 0;
 
@@ -593,43 +585,15 @@ static int init_binder_logs(struct super_block *sb)
 		goto out;
 	}
 
-	dentry = binderfs_create_file(binder_logs_root_dir, "stats",
-				      &binder_stats_fops, NULL);
-	if (IS_ERR(dentry)) {
-		ret = PTR_ERR(dentry);
-		goto out;
-	}
-
-	dentry = binderfs_create_file(binder_logs_root_dir, "state",
-				      &binder_state_fops, NULL);
-	if (IS_ERR(dentry)) {
-		ret = PTR_ERR(dentry);
-		goto out;
-	}
-
-	dentry = binderfs_create_file(binder_logs_root_dir, "transactions",
-				      &binder_transactions_fops, NULL);
-	if (IS_ERR(dentry)) {
-		ret = PTR_ERR(dentry);
-		goto out;
-	}
-
-	dentry = binderfs_create_file(binder_logs_root_dir,
-				      "transaction_log",
-				      &binder_transaction_log_fops,
-				      &binder_transaction_log);
-	if (IS_ERR(dentry)) {
-		ret = PTR_ERR(dentry);
-		goto out;
-	}
-
-	dentry = binderfs_create_file(binder_logs_root_dir,
-				      "failed_transaction_log",
-				      &binder_transaction_log_fops,
-				      &binder_transaction_log_failed);
-	if (IS_ERR(dentry)) {
-		ret = PTR_ERR(dentry);
-		goto out;
+	binder_for_each_debugfs_entry(db_entry) {
+		dentry = binderfs_create_file(binder_logs_root_dir,
+					      db_entry->name,
+					      db_entry->fops,
+					      db_entry->data);
+		if (IS_ERR(dentry)) {
+			ret = PTR_ERR(dentry);
+			goto out;
+		}
 	}
 
 	proc_log_dir = binderfs_create_dir(binder_logs_root_dir, "proc");
@@ -650,7 +614,7 @@ static int binderfs_fill_super(struct super_block *sb, struct fs_context *fc)
 	struct binderfs_info *info;
 	struct binderfs_mount_opts *ctx = fc->fs_private;
 	struct inode *inode = NULL;
-	struct binderfs_device device_info = { 0 };
+	struct binderfs_device device_info = {};
 	const char *name;
 	size_t len;
 
@@ -697,7 +661,7 @@ static int binderfs_fill_super(struct super_block *sb, struct fs_context *fc)
 	inode->i_ino = FIRST_INODE;
 	inode->i_fop = &simple_dir_operations;
 	inode->i_mode = S_IFDIR | 0755;
-	inode->i_mtime = inode->i_atime = inode->i_ctime = current_time(inode);
+	simple_inode_init_ts(inode);
 	inode->i_op = &binderfs_dir_inode_operations;
 	set_nlink(inode, 2);
 
@@ -720,6 +684,10 @@ static int binderfs_fill_super(struct super_block *sb, struct fs_context *fc)
 			name++;
 	}
 
+	ret = init_binder_features(sb);
+	if (ret)
+		return ret;
+
 	if (info->mount_opts.stats_mode == binderfs_stats_mode_global)
 		return init_binder_logs(sb);
 
@@ -747,7 +715,7 @@ static const struct fs_context_operations binderfs_fs_context_ops = {
 
 static int binderfs_init_fs_context(struct fs_context *fc)
 {
-	struct binderfs_mount_opts *ctx = fc->fs_private;
+	struct binderfs_mount_opts *ctx;
 
 	ctx = kzalloc(sizeof(struct binderfs_mount_opts), GFP_KERNEL);
 	if (!ctx)
@@ -762,11 +730,27 @@ static int binderfs_init_fs_context(struct fs_context *fc)
 	return 0;
 }
 
+static void binderfs_kill_super(struct super_block *sb)
+{
+	struct binderfs_info *info = sb->s_fs_info;
+
+	/*
+	 * During inode eviction struct binderfs_info is needed.
+	 * So first wipe the super_block then free struct binderfs_info.
+	 */
+	kill_anon_super(sb);
+
+	if (info && info->ipc_ns)
+		put_ipc_ns(info->ipc_ns);
+
+	kfree(info);
+}
+
 static struct file_system_type binder_fs_type = {
 	.name			= "binder",
 	.init_fs_context	= binderfs_init_fs_context,
 	.parameters		= binderfs_fs_parameters,
-	.kill_sb		= kill_litter_super,
+	.kill_sb		= binderfs_kill_super,
 	.fs_flags		= FS_USERNS_MOUNT,
 };
 
diff --git a/drivers/android/dbitmap.h b/drivers/android/dbitmap.h
new file mode 100644
index 000000000000..c7299ce8b374
--- /dev/null
+++ b/drivers/android/dbitmap.h
@@ -0,0 +1,169 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright 2024 Google LLC
+ *
+ * dbitmap - dynamically sized bitmap library.
+ *
+ * Used by the binder driver to optimize the allocation of the smallest
+ * available descriptor ID. Each bit in the bitmap represents the state
+ * of an ID.
+ *
+ * A dbitmap can grow or shrink as needed. This part has been designed
+ * considering that users might need to briefly release their locks in
+ * order to allocate memory for the new bitmap. These operations then,
+ * are verified to determine if the grow or shrink is sill valid.
+ *
+ * This library does not provide protection against concurrent access
+ * by itself. Binder uses the proc->outer_lock for this purpose.
+ */
+
+#ifndef _LINUX_DBITMAP_H
+#define _LINUX_DBITMAP_H
+#include <linux/bitmap.h>
+
+#define NBITS_MIN	BITS_PER_TYPE(unsigned long)
+
+struct dbitmap {
+	unsigned int nbits;
+	unsigned long *map;
+};
+
+static inline int dbitmap_enabled(struct dbitmap *dmap)
+{
+	return !!dmap->nbits;
+}
+
+static inline void dbitmap_free(struct dbitmap *dmap)
+{
+	dmap->nbits = 0;
+	kfree(dmap->map);
+	dmap->map = NULL;
+}
+
+/* Returns the nbits that a dbitmap can shrink to, 0 if not possible. */
+static inline unsigned int dbitmap_shrink_nbits(struct dbitmap *dmap)
+{
+	unsigned int bit;
+
+	if (dmap->nbits <= NBITS_MIN)
+		return 0;
+
+	/*
+	 * Determine if the bitmap can shrink based on the position of
+	 * its last set bit. If the bit is within the first quarter of
+	 * the bitmap then shrinking is possible. In this case, the
+	 * bitmap should shrink to half its current size.
+	 */
+	bit = find_last_bit(dmap->map, dmap->nbits);
+	if (bit < (dmap->nbits >> 2))
+		return dmap->nbits >> 1;
+
+	/* find_last_bit() returns dmap->nbits when no bits are set. */
+	if (bit == dmap->nbits)
+		return NBITS_MIN;
+
+	return 0;
+}
+
+/* Replace the internal bitmap with a new one of different size */
+static inline void
+dbitmap_replace(struct dbitmap *dmap, unsigned long *new, unsigned int nbits)
+{
+	bitmap_copy(new, dmap->map, min(dmap->nbits, nbits));
+	kfree(dmap->map);
+	dmap->map = new;
+	dmap->nbits = nbits;
+}
+
+static inline void
+dbitmap_shrink(struct dbitmap *dmap, unsigned long *new, unsigned int nbits)
+{
+	if (!new)
+		return;
+
+	/*
+	 * Verify that shrinking to @nbits is still possible. The @new
+	 * bitmap might have been allocated without locks, so this call
+	 * could now be outdated. In this case, free @new and move on.
+	 */
+	if (!dbitmap_enabled(dmap) || dbitmap_shrink_nbits(dmap) != nbits) {
+		kfree(new);
+		return;
+	}
+
+	dbitmap_replace(dmap, new, nbits);
+}
+
+/* Returns the nbits that a dbitmap can grow to. */
+static inline unsigned int dbitmap_grow_nbits(struct dbitmap *dmap)
+{
+	return dmap->nbits << 1;
+}
+
+static inline void
+dbitmap_grow(struct dbitmap *dmap, unsigned long *new, unsigned int nbits)
+{
+	/*
+	 * Verify that growing to @nbits is still possible. The @new
+	 * bitmap might have been allocated without locks, so this call
+	 * could now be outdated. In this case, free @new and move on.
+	 */
+	if (!dbitmap_enabled(dmap) || nbits <= dmap->nbits) {
+		kfree(new);
+		return;
+	}
+
+	/*
+	 * Check for ENOMEM after confirming the grow operation is still
+	 * required. This ensures we only disable the dbitmap when it's
+	 * necessary. Once the dbitmap is disabled, binder will fallback
+	 * to slow_desc_lookup_olocked().
+	 */
+	if (!new) {
+		dbitmap_free(dmap);
+		return;
+	}
+
+	dbitmap_replace(dmap, new, nbits);
+}
+
+/*
+ * Finds and sets the next zero bit in the bitmap. Upon success @bit
+ * is populated with the index and 0 is returned. Otherwise, -ENOSPC
+ * is returned to indicate that a dbitmap_grow() is needed.
+ */
+static inline int
+dbitmap_acquire_next_zero_bit(struct dbitmap *dmap, unsigned long offset,
+			      unsigned long *bit)
+{
+	unsigned long n;
+
+	n = find_next_zero_bit(dmap->map, dmap->nbits, offset);
+	if (n == dmap->nbits)
+		return -ENOSPC;
+
+	*bit = n;
+	set_bit(n, dmap->map);
+
+	return 0;
+}
+
+static inline void
+dbitmap_clear_bit(struct dbitmap *dmap, unsigned long bit)
+{
+	clear_bit(bit, dmap->map);
+}
+
+static inline int dbitmap_init(struct dbitmap *dmap)
+{
+	dmap->map = bitmap_zalloc(NBITS_MIN, GFP_KERNEL);
+	if (!dmap->map) {
+		dmap->nbits = 0;
+		return -ENOMEM;
+	}
+
+	dmap->nbits = NBITS_MIN;
+
+	return 0;
+}
+#endif
diff --git a/drivers/android/tests/.kunitconfig b/drivers/android/tests/.kunitconfig
new file mode 100644
index 000000000000..39b76bab9d9a
--- /dev/null
+++ b/drivers/android/tests/.kunitconfig
@@ -0,0 +1,7 @@
+#
+# Copyright 2025 Google LLC.
+#
+
+CONFIG_KUNIT=y
+CONFIG_ANDROID_BINDER_IPC=y
+CONFIG_ANDROID_BINDER_ALLOC_KUNIT_TEST=y
diff --git a/drivers/android/tests/Makefile b/drivers/android/tests/Makefile
new file mode 100644
index 000000000000..27268418eb03
--- /dev/null
+++ b/drivers/android/tests/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Copyright 2025 Google LLC.
+#
+
+obj-$(CONFIG_ANDROID_BINDER_ALLOC_KUNIT_TEST)	+= binder_alloc_kunit.o
diff --git a/drivers/android/tests/binder_alloc_kunit.c b/drivers/android/tests/binder_alloc_kunit.c
new file mode 100644
index 000000000000..7f9cc003bbe3
--- /dev/null
+++ b/drivers/android/tests/binder_alloc_kunit.c
@@ -0,0 +1,572 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Test cases for binder allocator code.
+ *
+ * Copyright 2025 Google LLC.
+ * Author: Tiffany Yang <ynaffit@google.com>
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include <kunit/test.h>
+#include <linux/anon_inodes.h>
+#include <linux/err.h>
+#include <linux/file.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/mman.h>
+#include <linux/seq_buf.h>
+#include <linux/sizes.h>
+
+#include "../binder_alloc.h"
+#include "../binder_internal.h"
+
+MODULE_IMPORT_NS("EXPORTED_FOR_KUNIT_TESTING");
+
+#define BINDER_MMAP_SIZE SZ_128K
+
+#define BUFFER_NUM 5
+#define BUFFER_MIN_SIZE (PAGE_SIZE / 8)
+
+#define FREESEQ_BUFLEN ((3 * BUFFER_NUM) + 1)
+
+#define ALIGN_TYPE_STRLEN (12)
+
+#define ALIGNMENTS_BUFLEN (((ALIGN_TYPE_STRLEN + 6) * BUFFER_NUM) + 1)
+
+#define PRINT_ALL_CASES (0)
+
+/* 5^5 alignment combinations * 2 places to share pages * 5! free sequences */
+#define TOTAL_EXHAUSTIVE_CASES (3125 * 2 * 120)
+
+/**
+ * enum buf_end_align_type - Page alignment of a buffer
+ * end with regard to the end of the previous buffer.
+ *
+ * In the pictures below, buf2 refers to the buffer we
+ * are aligning. buf1 refers to previous buffer by addr.
+ * Symbol [ means the start of a buffer, ] means the end
+ * of a buffer, and | means page boundaries.
+ */
+enum buf_end_align_type {
+	/**
+	 * @SAME_PAGE_UNALIGNED: The end of this buffer is on
+	 * the same page as the end of the previous buffer and
+	 * is not page aligned. Examples:
+	 * buf1 ][ buf2 ][ ...
+	 * buf1 ]|[ buf2 ][ ...
+	 */
+	SAME_PAGE_UNALIGNED = 0,
+	/**
+	 * @SAME_PAGE_ALIGNED: When the end of the previous buffer
+	 * is not page aligned, the end of this buffer is on the
+	 * same page as the end of the previous buffer and is page
+	 * aligned. When the previous buffer is page aligned, the
+	 * end of this buffer is aligned to the next page boundary.
+	 * Examples:
+	 * buf1 ][ buf2 ]| ...
+	 * buf1 ]|[ buf2 ]| ...
+	 */
+	SAME_PAGE_ALIGNED,
+	/**
+	 * @NEXT_PAGE_UNALIGNED: The end of this buffer is on
+	 * the page next to the end of the previous buffer and
+	 * is not page aligned. Examples:
+	 * buf1 ][ buf2 | buf2 ][ ...
+	 * buf1 ]|[ buf2 | buf2 ][ ...
+	 */
+	NEXT_PAGE_UNALIGNED,
+	/**
+	 * @NEXT_PAGE_ALIGNED: The end of this buffer is on
+	 * the page next to the end of the previous buffer and
+	 * is page aligned. Examples:
+	 * buf1 ][ buf2 | buf2 ]| ...
+	 * buf1 ]|[ buf2 | buf2 ]| ...
+	 */
+	NEXT_PAGE_ALIGNED,
+	/**
+	 * @NEXT_NEXT_UNALIGNED: The end of this buffer is on
+	 * the page that follows the page after the end of the
+	 * previous buffer and is not page aligned. Examples:
+	 * buf1 ][ buf2 | buf2 | buf2 ][ ...
+	 * buf1 ]|[ buf2 | buf2 | buf2 ][ ...
+	 */
+	NEXT_NEXT_UNALIGNED,
+	/**
+	 * @LOOP_END: The number of enum values in &buf_end_align_type.
+	 * It is used for controlling loop termination.
+	 */
+	LOOP_END,
+};
+
+static const char *const buf_end_align_type_strs[LOOP_END] = {
+	[SAME_PAGE_UNALIGNED] = "SP_UNALIGNED",
+	[SAME_PAGE_ALIGNED]   = " SP_ALIGNED ",
+	[NEXT_PAGE_UNALIGNED] = "NP_UNALIGNED",
+	[NEXT_PAGE_ALIGNED]   = " NP_ALIGNED ",
+	[NEXT_NEXT_UNALIGNED] = "NN_UNALIGNED",
+};
+
+struct binder_alloc_test_case_info {
+	char alignments[ALIGNMENTS_BUFLEN];
+	struct seq_buf alignments_sb;
+	size_t *buffer_sizes;
+	int *free_sequence;
+	bool front_pages;
+};
+
+static void stringify_free_seq(struct kunit *test, int *seq, struct seq_buf *sb)
+{
+	int i;
+
+	for (i = 0; i < BUFFER_NUM; i++)
+		seq_buf_printf(sb, "[%d]", seq[i]);
+
+	KUNIT_EXPECT_FALSE(test, seq_buf_has_overflowed(sb));
+}
+
+static void stringify_alignments(struct kunit *test, int *alignments,
+				 struct seq_buf *sb)
+{
+	int i;
+
+	for (i = 0; i < BUFFER_NUM; i++)
+		seq_buf_printf(sb, "[ %d:%s ]", i,
+			       buf_end_align_type_strs[alignments[i]]);
+
+	KUNIT_EXPECT_FALSE(test, seq_buf_has_overflowed(sb));
+}
+
+static bool check_buffer_pages_allocated(struct kunit *test,
+					 struct binder_alloc *alloc,
+					 struct binder_buffer *buffer,
+					 size_t size)
+{
+	unsigned long page_addr;
+	unsigned long end;
+	int page_index;
+
+	end = PAGE_ALIGN(buffer->user_data + size);
+	page_addr = buffer->user_data;
+	for (; page_addr < end; page_addr += PAGE_SIZE) {
+		page_index = (page_addr - alloc->vm_start) / PAGE_SIZE;
+		if (!alloc->pages[page_index] ||
+		    !list_empty(page_to_lru(alloc->pages[page_index]))) {
+			kunit_err(test, "expect alloc but is %s at page index %d\n",
+				  alloc->pages[page_index] ?
+				  "lru" : "free", page_index);
+			return false;
+		}
+	}
+	return true;
+}
+
+static unsigned long binder_alloc_test_alloc_buf(struct kunit *test,
+						 struct binder_alloc *alloc,
+						 struct binder_buffer *buffers[],
+						 size_t *sizes, int *seq)
+{
+	unsigned long failures = 0;
+	int i;
+
+	for (i = 0; i < BUFFER_NUM; i++) {
+		buffers[i] = binder_alloc_new_buf(alloc, sizes[i], 0, 0, 0);
+		if (IS_ERR(buffers[i]) ||
+		    !check_buffer_pages_allocated(test, alloc, buffers[i], sizes[i]))
+			failures++;
+	}
+
+	return failures;
+}
+
+static unsigned long binder_alloc_test_free_buf(struct kunit *test,
+						struct binder_alloc *alloc,
+						struct binder_buffer *buffers[],
+						size_t *sizes, int *seq, size_t end)
+{
+	unsigned long failures = 0;
+	int i;
+
+	for (i = 0; i < BUFFER_NUM; i++)
+		binder_alloc_free_buf(alloc, buffers[seq[i]]);
+
+	for (i = 0; i <= (end - 1) / PAGE_SIZE; i++) {
+		if (list_empty(page_to_lru(alloc->pages[i]))) {
+			kunit_err(test, "expect lru but is %s at page index %d\n",
+				  alloc->pages[i] ? "alloc" : "free", i);
+			failures++;
+		}
+	}
+
+	return failures;
+}
+
+static unsigned long binder_alloc_test_free_page(struct kunit *test,
+						 struct binder_alloc *alloc)
+{
+	unsigned long failures = 0;
+	unsigned long count;
+	int i;
+
+	while ((count = list_lru_count(alloc->freelist))) {
+		list_lru_walk(alloc->freelist, binder_alloc_free_page,
+			      NULL, count);
+	}
+
+	for (i = 0; i < (alloc->buffer_size / PAGE_SIZE); i++) {
+		if (alloc->pages[i]) {
+			kunit_err(test, "expect free but is %s at page index %d\n",
+				  list_empty(page_to_lru(alloc->pages[i])) ?
+				  "alloc" : "lru", i);
+			failures++;
+		}
+	}
+
+	return failures;
+}
+
+/* Executes one full test run for the given test case. */
+static bool binder_alloc_test_alloc_free(struct kunit *test,
+					 struct binder_alloc *alloc,
+					 struct binder_alloc_test_case_info *tc,
+					 size_t end)
+{
+	unsigned long pages = PAGE_ALIGN(end) / PAGE_SIZE;
+	struct binder_buffer *buffers[BUFFER_NUM];
+	unsigned long failures;
+	bool failed = false;
+
+	failures = binder_alloc_test_alloc_buf(test, alloc, buffers,
+					       tc->buffer_sizes,
+					       tc->free_sequence);
+	failed = failed || failures;
+	KUNIT_EXPECT_EQ_MSG(test, failures, 0,
+			    "Initial allocation failed: %lu/%u buffers with errors",
+			    failures, BUFFER_NUM);
+
+	failures = binder_alloc_test_free_buf(test, alloc, buffers,
+					      tc->buffer_sizes,
+					      tc->free_sequence, end);
+	failed = failed || failures;
+	KUNIT_EXPECT_EQ_MSG(test, failures, 0,
+			    "Initial buffers not freed correctly: %lu/%lu pages not on lru list",
+			    failures, pages);
+
+	/* Allocate from lru. */
+	failures = binder_alloc_test_alloc_buf(test, alloc, buffers,
+					       tc->buffer_sizes,
+					       tc->free_sequence);
+	failed = failed || failures;
+	KUNIT_EXPECT_EQ_MSG(test, failures, 0,
+			    "Reallocation failed: %lu/%u buffers with errors",
+			    failures, BUFFER_NUM);
+
+	failures = list_lru_count(alloc->freelist);
+	failed = failed || failures;
+	KUNIT_EXPECT_EQ_MSG(test, failures, 0,
+			    "lru list should be empty after reallocation but still has %lu pages",
+			    failures);
+
+	failures = binder_alloc_test_free_buf(test, alloc, buffers,
+					      tc->buffer_sizes,
+					      tc->free_sequence, end);
+	failed = failed || failures;
+	KUNIT_EXPECT_EQ_MSG(test, failures, 0,
+			    "Reallocated buffers not freed correctly: %lu/%lu pages not on lru list",
+			    failures, pages);
+
+	failures = binder_alloc_test_free_page(test, alloc);
+	failed = failed || failures;
+	KUNIT_EXPECT_EQ_MSG(test, failures, 0,
+			    "Failed to clean up allocated pages: %lu/%lu pages still installed",
+			    failures, (alloc->buffer_size / PAGE_SIZE));
+
+	return failed;
+}
+
+static bool is_dup(int *seq, int index, int val)
+{
+	int i;
+
+	for (i = 0; i < index; i++) {
+		if (seq[i] == val)
+			return true;
+	}
+	return false;
+}
+
+/* Generate BUFFER_NUM factorial free orders. */
+static void permute_frees(struct kunit *test, struct binder_alloc *alloc,
+			  struct binder_alloc_test_case_info *tc,
+			  unsigned long *runs, unsigned long *failures,
+			  int index, size_t end)
+{
+	bool case_failed;
+	int i;
+
+	if (index == BUFFER_NUM) {
+		DECLARE_SEQ_BUF(freeseq_sb, FREESEQ_BUFLEN);
+
+		case_failed = binder_alloc_test_alloc_free(test, alloc, tc, end);
+		*runs += 1;
+		*failures += case_failed;
+
+		if (case_failed || PRINT_ALL_CASES) {
+			stringify_free_seq(test, tc->free_sequence,
+					   &freeseq_sb);
+			kunit_err(test, "case %lu: [%s] | %s - %s - %s", *runs,
+				  case_failed ? "FAILED" : "PASSED",
+				  tc->front_pages ? "front" : "back ",
+				  seq_buf_str(&tc->alignments_sb),
+				  seq_buf_str(&freeseq_sb));
+		}
+
+		return;
+	}
+	for (i = 0; i < BUFFER_NUM; i++) {
+		if (is_dup(tc->free_sequence, index, i))
+			continue;
+		tc->free_sequence[index] = i;
+		permute_frees(test, alloc, tc, runs, failures, index + 1, end);
+	}
+}
+
+static void gen_buf_sizes(struct kunit *test,
+			  struct binder_alloc *alloc,
+			  struct binder_alloc_test_case_info *tc,
+			  size_t *end_offset, unsigned long *runs,
+			  unsigned long *failures)
+{
+	size_t last_offset, offset = 0;
+	size_t front_sizes[BUFFER_NUM];
+	size_t back_sizes[BUFFER_NUM];
+	int seq[BUFFER_NUM] = {0};
+	int i;
+
+	tc->free_sequence = seq;
+	for (i = 0; i < BUFFER_NUM; i++) {
+		last_offset = offset;
+		offset = end_offset[i];
+		front_sizes[i] = offset - last_offset;
+		back_sizes[BUFFER_NUM - i - 1] = front_sizes[i];
+	}
+	back_sizes[0] += alloc->buffer_size - end_offset[BUFFER_NUM - 1];
+
+	/*
+	 * Buffers share the first or last few pages.
+	 * Only BUFFER_NUM - 1 buffer sizes are adjustable since
+	 * we need one giant buffer before getting to the last page.
+	 */
+	tc->front_pages = true;
+	tc->buffer_sizes = front_sizes;
+	permute_frees(test, alloc, tc, runs, failures, 0,
+		      end_offset[BUFFER_NUM - 1]);
+
+	tc->front_pages = false;
+	tc->buffer_sizes = back_sizes;
+	permute_frees(test, alloc, tc, runs, failures, 0, alloc->buffer_size);
+}
+
+static void gen_buf_offsets(struct kunit *test, struct binder_alloc *alloc,
+			    size_t *end_offset, int *alignments,
+			    unsigned long *runs, unsigned long *failures,
+			    int index)
+{
+	size_t end, prev;
+	int align;
+
+	if (index == BUFFER_NUM) {
+		struct binder_alloc_test_case_info tc = {0};
+
+		seq_buf_init(&tc.alignments_sb, tc.alignments,
+			     ALIGNMENTS_BUFLEN);
+		stringify_alignments(test, alignments, &tc.alignments_sb);
+
+		gen_buf_sizes(test, alloc, &tc, end_offset, runs, failures);
+		return;
+	}
+	prev = index == 0 ? 0 : end_offset[index - 1];
+	end = prev;
+
+	BUILD_BUG_ON(BUFFER_MIN_SIZE * BUFFER_NUM >= PAGE_SIZE);
+
+	for (align = SAME_PAGE_UNALIGNED; align < LOOP_END; align++) {
+		if (align % 2)
+			end = ALIGN(end, PAGE_SIZE);
+		else
+			end += BUFFER_MIN_SIZE;
+		end_offset[index] = end;
+		alignments[index] = align;
+		gen_buf_offsets(test, alloc, end_offset, alignments, runs,
+				failures, index + 1);
+	}
+}
+
+struct binder_alloc_test {
+	struct binder_alloc alloc;
+	struct list_lru binder_test_freelist;
+	struct file *filp;
+	unsigned long mmap_uaddr;
+};
+
+static void binder_alloc_test_init_freelist(struct kunit *test)
+{
+	struct binder_alloc_test *priv = test->priv;
+
+	KUNIT_EXPECT_PTR_EQ(test, priv->alloc.freelist,
+			    &priv->binder_test_freelist);
+}
+
+static void binder_alloc_test_mmap(struct kunit *test)
+{
+	struct binder_alloc_test *priv = test->priv;
+	struct binder_alloc *alloc = &priv->alloc;
+	struct binder_buffer *buf;
+	struct rb_node *n;
+
+	KUNIT_EXPECT_EQ(test, alloc->mapped, true);
+	KUNIT_EXPECT_EQ(test, alloc->buffer_size, BINDER_MMAP_SIZE);
+
+	n = rb_first(&alloc->allocated_buffers);
+	KUNIT_EXPECT_PTR_EQ(test, n, NULL);
+
+	n = rb_first(&alloc->free_buffers);
+	buf = rb_entry(n, struct binder_buffer, rb_node);
+	KUNIT_EXPECT_EQ(test, binder_alloc_buffer_size(alloc, buf),
+			BINDER_MMAP_SIZE);
+	KUNIT_EXPECT_TRUE(test, list_is_last(&buf->entry, &alloc->buffers));
+}
+
+/**
+ * binder_alloc_exhaustive_test() - Exhaustively test alloc and free of buffer pages.
+ * @test: The test context object.
+ *
+ * Allocate BUFFER_NUM buffers to cover all page alignment cases,
+ * then free them in all orders possible. Check that pages are
+ * correctly allocated, put onto lru when buffers are freed, and
+ * are freed when binder_alloc_free_page() is called.
+ */
+static void binder_alloc_exhaustive_test(struct kunit *test)
+{
+	struct binder_alloc_test *priv = test->priv;
+	size_t end_offset[BUFFER_NUM];
+	int alignments[BUFFER_NUM];
+	unsigned long failures = 0;
+	unsigned long runs = 0;
+
+	gen_buf_offsets(test, &priv->alloc, end_offset, alignments, &runs,
+			&failures, 0);
+
+	KUNIT_EXPECT_EQ(test, runs, TOTAL_EXHAUSTIVE_CASES);
+	KUNIT_EXPECT_EQ(test, failures, 0);
+}
+
+/* ===== End test cases ===== */
+
+static void binder_alloc_test_vma_close(struct vm_area_struct *vma)
+{
+	struct binder_alloc *alloc = vma->vm_private_data;
+
+	binder_alloc_vma_close(alloc);
+}
+
+static const struct vm_operations_struct binder_alloc_test_vm_ops = {
+	.close = binder_alloc_test_vma_close,
+	.fault = binder_vm_fault,
+};
+
+static int binder_alloc_test_mmap_handler(struct file *filp,
+					  struct vm_area_struct *vma)
+{
+	struct binder_alloc *alloc = filp->private_data;
+
+	vm_flags_mod(vma, VM_DONTCOPY | VM_MIXEDMAP, VM_MAYWRITE);
+
+	vma->vm_ops = &binder_alloc_test_vm_ops;
+	vma->vm_private_data = alloc;
+
+	return binder_alloc_mmap_handler(alloc, vma);
+}
+
+static const struct file_operations binder_alloc_test_fops = {
+	.mmap = binder_alloc_test_mmap_handler,
+};
+
+static int binder_alloc_test_init(struct kunit *test)
+{
+	struct binder_alloc_test *priv;
+	int ret;
+
+	priv = kunit_kzalloc(test, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+	test->priv = priv;
+
+	ret = list_lru_init(&priv->binder_test_freelist);
+	if (ret) {
+		kunit_err(test, "Failed to initialize test freelist\n");
+		return ret;
+	}
+
+	/* __binder_alloc_init requires mm to be attached */
+	ret = kunit_attach_mm();
+	if (ret) {
+		kunit_err(test, "Failed to attach mm\n");
+		return ret;
+	}
+	__binder_alloc_init(&priv->alloc, &priv->binder_test_freelist);
+
+	priv->filp = anon_inode_getfile("binder_alloc_kunit",
+					&binder_alloc_test_fops, &priv->alloc,
+					O_RDWR | O_CLOEXEC);
+	if (IS_ERR_OR_NULL(priv->filp)) {
+		kunit_err(test, "Failed to open binder alloc test driver file\n");
+		return priv->filp ? PTR_ERR(priv->filp) : -ENOMEM;
+	}
+
+	priv->mmap_uaddr = kunit_vm_mmap(test, priv->filp, 0, BINDER_MMAP_SIZE,
+					 PROT_READ, MAP_PRIVATE | MAP_NORESERVE,
+					 0);
+	if (!priv->mmap_uaddr) {
+		kunit_err(test, "Could not map the test's transaction memory\n");
+		return -ENOMEM;
+	}
+
+	return 0;
+}
+
+static void binder_alloc_test_exit(struct kunit *test)
+{
+	struct binder_alloc_test *priv = test->priv;
+
+	/* Close the backing file to make sure binder_alloc_vma_close runs */
+	if (!IS_ERR_OR_NULL(priv->filp))
+		fput(priv->filp);
+
+	if (priv->alloc.mm)
+		binder_alloc_deferred_release(&priv->alloc);
+
+	/* Make sure freelist is empty */
+	KUNIT_EXPECT_EQ(test, list_lru_count(&priv->binder_test_freelist), 0);
+	list_lru_destroy(&priv->binder_test_freelist);
+}
+
+static struct kunit_case binder_alloc_test_cases[] = {
+	KUNIT_CASE(binder_alloc_test_init_freelist),
+	KUNIT_CASE(binder_alloc_test_mmap),
+	KUNIT_CASE_SLOW(binder_alloc_exhaustive_test),
+	{}
+};
+
+static struct kunit_suite binder_alloc_test_suite = {
+	.name = "binder_alloc",
+	.test_cases = binder_alloc_test_cases,
+	.init = binder_alloc_test_init,
+	.exit = binder_alloc_test_exit,
+};
+
+kunit_test_suite(binder_alloc_test_suite);
+
+MODULE_AUTHOR("Tiffany Yang <ynaffit@google.com>");
+MODULE_DESCRIPTION("Binder Alloc KUnit tests");
+MODULE_LICENSE("GPL");
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 05ecdce1b702..120a2b7067fc 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -17,7 +17,7 @@ menuconfig ATA
 	depends on BLOCK
 	select SCSI
 	select GLOB
-	---help---
+	help
 	  If you want to use an ATA hard disk, ATA tape drive, ATA CD-ROM or
 	  any other ATA device under Linux, say Y and make sure that you know
 	  the name of your ATA host adapter (the card inside your computer
@@ -116,23 +116,40 @@ config SATA_AHCI
 	  If unsure, say N.
 
 config SATA_MOBILE_LPM_POLICY
-	int "Default SATA Link Power Management policy for mobile chipsets"
-	range 0 4
-	default 0
+	int "Default SATA Link Power Management policy"
+	range 0 5
+	default 3
 	depends on SATA_AHCI
 	help
 	  Select the Default SATA Link Power Management (LPM) policy to use
-	  for mobile / laptop variants of chipsets / "South Bridges".
-
-	  The value set has the following meanings:
+	  for chipsets / "South Bridges" supporting low-power modes. Such
+	  chipsets are ubiquitous across laptops, desktops and servers.
+	  Each policy combines power saving states and features:
+	   - Partial: The Phy logic is powered but is in a reduced power
+                      state. The exit latency from this state is no longer than
+                      10us).
+	   - Slumber: The Phy logic is powered but is in an even lower power
+                      state. The exit latency from this state is potentially
+		      longer, but no longer than 10ms.
+	   - DevSleep: The Phy logic may be powered down. The exit latency from
+	               this state is no longer than 20 ms, unless otherwise
+		       specified by DETO in the device Identify Device Data log.
+	   - HIPM: Host Initiated Power Management (host automatically
+		   transitions to partial and slumber).
+	   - DIPM: Device Initiated Power Management (device automatically
+		   transitions to partial and slumber).
+
+	  The possible values for the default SATA link power management
+	  policies are:
 		0 => Keep firmware settings
-		1 => Maximum performance
-		2 => Medium power
-		3 => Medium power with Device Initiated PM enabled
-		4 => Minimum power
+		1 => No power savings (maximum performance)
+		2 => HIPM (Partial)
+		3 => HIPM (Partial) and DIPM (Partial and Slumber)
+		4 => HIPM (Partial and DevSleep) and DIPM (Partial and Slumber)
+		5 => HIPM (Slumber and DevSleep) and DIPM (Partial and Slumber)
 
-	  Note "Minimum power" is known to cause issues, including disk
-	  corruption, with some disks and should not be used.
+	  Excluding the value 0, higher values represent policies with higher
+	  power savings.
 
 config SATA_AHCI_PLATFORM
 	tristate "Platform AHCI SATA support"
@@ -146,7 +163,7 @@ config SATA_AHCI_PLATFORM
 config AHCI_BRCM
 	tristate "Broadcom AHCI SATA support"
 	depends on ARCH_BRCMSTB || BMIPS_GENERIC || ARCH_BCM_NSP || \
-		   ARCH_BCM_63XX
+		   ARCH_BCMBCA || COMPILE_TEST
 	select SATA_HOST
 	help
 	  This option enables support for the AHCI SATA3 controller found on
@@ -156,7 +173,7 @@ config AHCI_BRCM
 
 config AHCI_DA850
 	tristate "DaVinci DA850 AHCI SATA support"
-	depends on ARCH_DAVINCI_DA850
+	depends on ARCH_DAVINCI_DA850 || COMPILE_TEST
 	select SATA_HOST
 	help
 	  This option enables support for the DaVinci DA850 SoC's
@@ -166,7 +183,7 @@ config AHCI_DA850
 
 config AHCI_DM816
 	tristate "DaVinci DM816 AHCI SATA support"
-	depends on ARCH_OMAP2PLUS
+	depends on ARCH_OMAP2PLUS || COMPILE_TEST
 	select SATA_HOST
 	help
 	  This option enables support for the DaVinci DM816 SoC's
@@ -174,9 +191,19 @@ config AHCI_DM816
 
 	  If unsure, say N.
 
+config AHCI_DWC
+	tristate "Synopsys DWC AHCI SATA support"
+	select SATA_HOST
+	select MFD_SYSCON if (MIPS_BAIKAL_T1 || COMPILE_TEST)
+	help
+	  This option enables support for the Synopsys DWC AHCI SATA
+	  controller implementation.
+
+	  If unsure, say N.
+
 config AHCI_ST
 	tristate "ST AHCI SATA support"
-	depends on ARCH_STI
+	depends on ARCH_STI || COMPILE_TEST
 	select SATA_HOST
 	help
 	  This option enables support for ST AHCI SATA controller.
@@ -206,7 +233,7 @@ config AHCI_CEVA
 
 config AHCI_MTK
 	tristate "MediaTek AHCI SATA support"
-	depends on ARCH_MEDIATEK
+	depends on ARCH_MEDIATEK || COMPILE_TEST
 	select MFD_SYSCON
 	select SATA_HOST
 	help
@@ -217,7 +244,7 @@ config AHCI_MTK
 
 config AHCI_MVEBU
 	tristate "Marvell EBU AHCI SATA support"
-	depends on ARCH_MVEBU
+	depends on ARCH_MVEBU || COMPILE_TEST
 	select SATA_HOST
 	help
 	  This option enables support for the Marvebu EBU SoC's
@@ -236,7 +263,7 @@ config AHCI_OCTEON
 
 config AHCI_SUNXI
 	tristate "Allwinner sunxi AHCI SATA support"
-	depends on ARCH_SUNXI
+	depends on ARCH_SUNXI || COMPILE_TEST
 	select SATA_HOST
 	help
 	  This option enables support for the Allwinner sunxi SoC's
@@ -246,7 +273,7 @@ config AHCI_SUNXI
 
 config AHCI_TEGRA
 	tristate "NVIDIA Tegra AHCI SATA support"
-	depends on ARCH_TEGRA
+	depends on ARCH_TEGRA || COMPILE_TEST
 	select SATA_HOST
 	help
 	  This option enables support for the NVIDIA Tegra SoC's
@@ -256,7 +283,7 @@ config AHCI_TEGRA
 
 config AHCI_XGENE
 	tristate "APM X-Gene 6.0Gbps AHCI SATA host controller support"
-	depends on PHY_XGENE
+	depends on PHY_XGENE || COMPILE_TEST
 	select SATA_HOST
 	help
 	 This option enables support for APM X-Gene SoC SATA host controller.
@@ -264,6 +291,7 @@ config AHCI_XGENE
 config AHCI_QORIQ
 	tristate "Freescale QorIQ AHCI SATA support"
 	depends on OF
+	depends on SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST
 	select SATA_HOST
 	help
 	  This option enables support for the Freescale QorIQ AHCI SoC's
@@ -273,7 +301,7 @@ config AHCI_QORIQ
 
 config SATA_FSL
 	tristate "Freescale 3.0Gbps SATA support"
-	depends on FSL_SOC
+	depends on FSL_SOC || COMPILE_TEST
 	select SATA_HOST
 	help
 	  This option enables support for Freescale 3.0Gbps SATA controller.
@@ -294,7 +322,7 @@ config SATA_GEMINI
 
 config SATA_AHCI_SEATTLE
 	tristate "AMD Seattle 6.0Gbps AHCI SATA host controller support"
-	depends on ARCH_SEATTLE
+	depends on ARCH_SEATTLE || COMPILE_TEST
 	select SATA_HOST
 	help
 	 This option enables support for AMD Seattle SATA host controller.
@@ -432,18 +460,6 @@ config SATA_DWC_OLD_DMA
 	  This option enables support for old device trees without the
 	  "dmas" property.
 
-config SATA_DWC_DEBUG
-	bool "Debugging driver version"
-	depends on SATA_DWC
-	help
-	  This option enables debugging output in the driver.
-
-config SATA_DWC_VDEBUG
-	bool "Verbose debug output"
-	depends on SATA_DWC_DEBUG
-	help
-	  This option enables the taskfile dumping and NCQ debugging.
-
 config SATA_HIGHBANK
 	tristate "Calxeda Highbank SATA support"
 	depends on ARCH_HIGHBANK || COMPILE_TEST
@@ -556,7 +572,7 @@ comment "PATA SFF controllers with BMDMA"
 
 config PATA_ALI
 	tristate "ALi PATA support"
-	depends on PCI
+	depends on PCI && HAS_IOPORT
 	select PATA_TIMINGS
 	help
 	  This option enables support for the ALi ATA interfaces
@@ -566,7 +582,7 @@ config PATA_ALI
 
 config PATA_AMD
 	tristate "AMD/NVidia PATA support"
-	depends on PCI
+	depends on PCI && HAS_IOPORT
 	select PATA_TIMINGS
 	help
 	  This option enables support for the AMD and NVidia PATA
@@ -584,7 +600,7 @@ config PATA_ARASAN_CF
 
 config PATA_ARTOP
 	tristate "ARTOP 6210/6260 PATA support"
-	depends on PCI
+	depends on PCI && HAS_IOPORT
 	help
 	  This option enables support for ARTOP PATA controllers.
 
@@ -609,19 +625,9 @@ config PATA_ATP867X
 
 	  If unsure, say N.
 
-config PATA_BK3710
-	tristate "Palmchip BK3710 PATA support"
-	depends on ARCH_DAVINCI
-	select PATA_TIMINGS
-	help
-	  This option enables support for the integrated IDE controller on
-	  the TI DaVinci SoC.
-
-	  If unsure, say N.
-
 config PATA_CMD64X
 	tristate "CMD64x PATA support"
-	depends on PCI
+	depends on PCI && HAS_IOPORT
 	select PATA_TIMINGS
 	help
 	  This option enables support for the CMD64x series chips
@@ -649,7 +655,8 @@ config PATA_CS5530
 
 config PATA_CS5535
 	tristate "CS5535 PATA support (Experimental)"
-	depends on PCI && X86_32
+	depends on PCI && (X86_32 || (X86_64 && COMPILE_TEST))
+	depends on !UML
 	help
 	  This option enables support for the NatSemi/AMD CS5535
 	  companion chip used with the Geode processor family.
@@ -667,7 +674,7 @@ config PATA_CS5536
 
 config PATA_CYPRESS
 	tristate "Cypress CY82C693 PATA support (Very Experimental)"
-	depends on PCI
+	depends on PCI && HAS_IOPORT
 	select PATA_TIMINGS
 	help
 	  This option enables support for the Cypress/Contaq CY82C693
@@ -696,8 +703,7 @@ config PATA_EP93XX
 
 config PATA_FTIDE010
 	tristate "Faraday Technology FTIDE010 PATA support"
-	depends on OF
-	depends on ARM
+	depends on ARM || COMPILE_TEST
 	depends on SATA_GEMINI
 	help
 	  This option enables support for the Faraday FTIDE010
@@ -716,7 +722,7 @@ config PATA_HPT366
 
 config PATA_HPT37X
 	tristate "HPT 370/370A/371/372/374/302 PATA support"
-	depends on PCI
+	depends on PCI && HAS_IOPORT
 	help
 	  This option enables support for the majority of the later HPT
 	  PATA controllers via the new ATA layer.
@@ -725,7 +731,7 @@ config PATA_HPT37X
 
 config PATA_HPT3X2N
 	tristate "HPT 371N/372N/302N PATA support"
-	depends on PCI
+	depends on PCI && HAS_IOPORT
 	help
 	  This option enables support for the N variant HPT PATA
 	  controllers via the new ATA layer.
@@ -760,7 +766,7 @@ config PATA_ICSIDE
 
 config PATA_IMX
 	tristate "PATA support for Freescale iMX"
-	depends on ARCH_MXC
+	depends on ARCH_MXC || COMPILE_TEST
 	select PATA_TIMINGS
 	help
 	  This option enables support for the PATA host available on Freescale
@@ -828,7 +834,7 @@ config PATA_MPC52xx
 
 config PATA_NETCELL
 	tristate "NETCELL Revolution RAID support"
-	depends on PCI
+	depends on PCI && HAS_IOPORT
 	help
 	  This option enables support for the Netcell Revolution RAID
 	  PATA controller.
@@ -864,7 +870,7 @@ config PATA_OLDPIIX
 
 config PATA_OPTIDMA
 	tristate "OPTI FireStar PATA support (Very Experimental)"
-	depends on PCI
+	depends on PCI && HAS_IOPORT
 	help
 	  This option enables DMA/PIO support for the later OPTi
 	  controllers found on some old motherboards and in some
@@ -874,7 +880,7 @@ config PATA_OPTIDMA
 
 config PATA_PDC2027X
 	tristate "Promise PATA 2027x support"
-	depends on PCI
+	depends on PCI && HAS_IOPORT
 	help
 	  This option enables support for Promise PATA pdc20268 to pdc20277 host adapters.
 
@@ -882,7 +888,7 @@ config PATA_PDC2027X
 
 config PATA_PDC_OLD
 	tristate "Older Promise PATA controller support"
-	depends on PCI
+	depends on PCI && HAS_IOPORT
 	help
 	  This option enables support for the Promise 20246, 20262, 20263,
 	  20265 and 20267 adapters.
@@ -910,7 +916,7 @@ config PATA_RDC
 
 config PATA_SC1200
 	tristate "SC1200 PATA support"
-	depends on PCI && (X86_32 || COMPILE_TEST)
+	depends on PCI && (X86_32 || COMPILE_TEST) && HAS_IOPORT
 	help
 	  This option enables support for the NatSemi/AMD SC1200 SoC
 	  companion chip used with the Geode processor family.
@@ -928,7 +934,7 @@ config PATA_SCH
 
 config PATA_SERVERWORKS
 	tristate "SERVERWORKS OSB4/CSB5/CSB6/HT1000 PATA support"
-	depends on PCI
+	depends on PCI && HAS_IOPORT
 	help
 	  This option enables support for the Serverworks OSB4/CSB5/CSB6 and
 	  HT1000 PATA controllers, via the new ATA layer.
@@ -981,7 +987,7 @@ config PATA_VIA
 
 config PATA_PXA
 	tristate "PXA DMA-capable PATA support"
-	depends on ARCH_PXA
+	depends on ARCH_PXA || COMPILE_TEST
 	help
 	  This option enables support for harddrive attached to PXA CPU's bus.
 
@@ -1015,11 +1021,11 @@ config PATA_CMD640_PCI
 	  If unsure, say N.
 
 config PATA_FALCON
-	tristate "Atari Falcon PATA support"
-	depends on M68K && ATARI
+	tristate "Atari Falcon and Q40/Q60 PATA support"
+	depends on M68K && (ATARI || Q40)
 	help
 	  This option enables support for the on-board IDE
-	  interface on the Atari Falcon.
+	  interface on the Atari Falcon and Q40/Q60.
 
 	  If unsure, say N.
 
@@ -1058,7 +1064,7 @@ config PATA_ISAPNP
 
 config PATA_IXP4XX_CF
 	tristate "IXP4XX Compact Flash support"
-	depends on ARCH_IXP4XX
+	depends on ARCH_IXP4XX || COMPILE_TEST
 	help
 	  This option enables support for a Compact Flash connected on
 	  the ixp4xx expansion bus. This driver had been written for
@@ -1093,15 +1099,6 @@ config PATA_OPTI
 
 	  If unsure, say N.
 
-config PATA_PALMLD
-	tristate "Palm LifeDrive PATA support"
-	depends on MACH_PALMLD
-	help
-	  This option enables support for Palm LifeDrive's internal ATA
-	  port via the new ATA layer.
-
-	  If unsure, say N.
-
 config PATA_PCMCIA
 	tristate "PCMCIA PATA support"
 	depends on PCMCIA
@@ -1112,8 +1109,7 @@ config PATA_PCMCIA
 	  If unsure, say N.
 
 config PATA_PLATFORM
-	tristate "Generic platform device PATA support"
-	depends on EXPERT || PPC || HAVE_PATA_PLATFORM
+	tristate "Generic platform device PATA support" if HAVE_PATA_PLATFORM
 	help
 	  This option enables support for generic directly connected ATA
 	  devices commonly found on embedded systems.
@@ -1122,7 +1118,8 @@ config PATA_PLATFORM
 
 config PATA_OF_PLATFORM
 	tristate "OpenFirmware platform device PATA support"
-	depends on PATA_PLATFORM && OF
+	depends on OF
+	select PATA_PLATFORM
 	help
 	  This option enables support for generic directly connected ATA
 	  devices commonly found on embedded systems with OpenFirmware
@@ -1155,16 +1152,6 @@ config PATA_RZ1000
 
 	  If unsure, say N.
 
-config PATA_SAMSUNG_CF
-	tristate "Samsung SoC PATA support"
-	depends on SAMSUNG_DEV_IDE
-	select PATA_TIMINGS
-	help
-	  This option enables basic support for Samsung's S3C/S5P board
-	  PATA controllers via the new ATA layer
-
-	  If unsure, say N.
-
 config PATA_WINBOND_VLB
 	tristate "Winbond W83759A VLB PATA support (Experimental)"
 	depends on ISA
@@ -1173,6 +1160,20 @@ config PATA_WINBOND_VLB
 	  Support for the Winbond W83759A controller on Vesa Local Bus
 	  systems.
 
+config PATA_PARPORT
+	tristate "Parallel port IDE device support"
+	depends on PARPORT_PC
+	help
+	  There are many external CD-ROM and disk devices that connect through
+	  your computer's parallel port. Most of them are actually IDE devices
+	  using a parallel port IDE adapter. This option enables the
+	  PATA_PARPORT subsystem which contains drivers for many of these
+	  external drives.
+	  Read <file:Documentation/admin-guide/blockdev/paride.rst> for more
+	  information.
+
+source "drivers/ata/pata_parport/Kconfig"
+
 comment "Generic fallback / legacy drivers"
 
 config PATA_ACPI
@@ -1197,7 +1198,7 @@ config ATA_GENERIC
 
 config PATA_LEGACY
 	tristate "Legacy ISA PATA support (Experimental)"
-	depends on (ISA || PCI)
+	depends on (ISA || PCI) && HAS_IOPORT
 	select PATA_TIMINGS
 	help
 	  This option enables support for ISA/VLB/PCI bus legacy PATA
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index b8aebfb14e82..20e6645ab737 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_AHCI_BRCM)		+= ahci_brcm.o libahci.o libahci_platform.o
 obj-$(CONFIG_AHCI_CEVA)		+= ahci_ceva.o libahci.o libahci_platform.o
 obj-$(CONFIG_AHCI_DA850)	+= ahci_da850.o libahci.o libahci_platform.o
 obj-$(CONFIG_AHCI_DM816)	+= ahci_dm816.o libahci.o libahci_platform.o
+obj-$(CONFIG_AHCI_DWC)		+= ahci_dwc.o libahci.o libahci_platform.o
 obj-$(CONFIG_AHCI_IMX)		+= ahci_imx.o libahci.o libahci_platform.o
 obj-$(CONFIG_AHCI_MTK)		+= ahci_mtk.o libahci.o libahci_platform.o
 obj-$(CONFIG_AHCI_MVEBU)	+= ahci_mvebu.o libahci.o libahci_platform.o
@@ -53,7 +54,6 @@ obj-$(CONFIG_PATA_AMD)		+= pata_amd.o
 obj-$(CONFIG_PATA_ARTOP)	+= pata_artop.o
 obj-$(CONFIG_PATA_ATIIXP)	+= pata_atiixp.o
 obj-$(CONFIG_PATA_ATP867X)	+= pata_atp867x.o
-obj-$(CONFIG_PATA_BK3710)	+= pata_bk3710.o
 obj-$(CONFIG_PATA_CMD64X)	+= pata_cmd64x.o
 obj-$(CONFIG_PATA_CS5520)	+= pata_cs5520.o
 obj-$(CONFIG_PATA_CS5530)	+= pata_cs5530.o
@@ -105,15 +105,15 @@ obj-$(CONFIG_PATA_MPIIX)	+= pata_mpiix.o
 obj-$(CONFIG_PATA_NS87410)	+= pata_ns87410.o
 obj-$(CONFIG_PATA_OPTI)		+= pata_opti.o
 obj-$(CONFIG_PATA_PCMCIA)	+= pata_pcmcia.o
-obj-$(CONFIG_PATA_PALMLD)	+= pata_palmld.o
 obj-$(CONFIG_PATA_PLATFORM)	+= pata_platform.o
 obj-$(CONFIG_PATA_OF_PLATFORM)	+= pata_of_platform.o
 obj-$(CONFIG_PATA_RB532)	+= pata_rb532_cf.o
 obj-$(CONFIG_PATA_RZ1000)	+= pata_rz1000.o
-obj-$(CONFIG_PATA_SAMSUNG_CF)	+= pata_samsung_cf.o
 
 obj-$(CONFIG_PATA_PXA)		+= pata_pxa.o
 
+obj-$(CONFIG_PATA_PARPORT)	+= pata_parport/
+
 # Should be last but two libata driver
 obj-$(CONFIG_PATA_ACPI)		+= pata_acpi.o
 # Should be last but one libata driver
diff --git a/drivers/ata/acard-ahci.c b/drivers/ata/acard-ahci.c
index 2a04e8abd397..3999305b5356 100644
--- a/drivers/ata/acard-ahci.c
+++ b/drivers/ata/acard-ahci.c
@@ -57,7 +57,7 @@ struct acard_sg {
 };
 
 static enum ata_completion_errors acard_ahci_qc_prep(struct ata_queued_cmd *qc);
-static bool acard_ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
+static void acard_ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
 static int acard_ahci_port_start(struct ata_port *ap);
 static int acard_ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
 
@@ -66,7 +66,7 @@ static int acard_ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg
 static int acard_ahci_pci_device_resume(struct pci_dev *pdev);
 #endif
 
-static struct scsi_host_template acard_ahci_sht = {
+static const struct scsi_host_template acard_ahci_sht = {
 	AHCI_SHT("acard-ahci"),
 };
 
@@ -185,8 +185,6 @@ static unsigned int acard_ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
 	struct acard_sg *acard_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
 	unsigned int si, last_si = 0;
 
-	VPRINTK("ENTER\n");
-
 	/*
 	 * Next, the S/G list.
 	 */
@@ -250,7 +248,7 @@ static enum ata_completion_errors acard_ahci_qc_prep(struct ata_queued_cmd *qc)
 	return AC_ERR_OK;
 }
 
-static bool acard_ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
+static void acard_ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
 {
 	struct ahci_port_priv *pp = qc->ap->private_data;
 	u8 *rx_fis = pp->rx_fis;
@@ -265,13 +263,11 @@ static bool acard_ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
 	 * Setup FIS.
 	 */
 	if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
-	    !(qc->flags & ATA_QCFLAG_FAILED)) {
+	    !(qc->flags & ATA_QCFLAG_EH)) {
 		ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
-		qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
+		qc->result_tf.status = (rx_fis + RX_FIS_PIO_SETUP)[15];
 	} else
 		ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
-
-	return true;
 }
 
 static int acard_ahci_port_start(struct ata_port *ap)
@@ -362,8 +358,6 @@ static int acard_ahci_init_one(struct pci_dev *pdev, const struct pci_device_id
 	struct ata_host *host;
 	int n_ports, i, rc;
 
-	VPRINTK("ENTER\n");
-
 	WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
 
 	ata_print_version_once(&pdev->dev, DRV_VERSION);
@@ -376,7 +370,7 @@ static int acard_ahci_init_one(struct pci_dev *pdev, const struct pci_device_id
 	/* AHCI controllers often implement SFF compatible interface.
 	 * Grab all PCI BARs just in case.
 	 */
-	rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
+	rc = pcim_request_all_regions(pdev, DRV_NAME);
 	if (rc == -EBUSY)
 		pcim_pin_device(pdev);
 	if (rc)
@@ -392,7 +386,9 @@ static int acard_ahci_init_one(struct pci_dev *pdev, const struct pci_device_id
 	if (!(hpriv->flags & AHCI_HFLAG_NO_MSI))
 		pci_enable_msi(pdev);
 
-	hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
+	hpriv->mmio = pcim_iomap(pdev, AHCI_PCI_BAR, 0);
+	if (!hpriv->mmio)
+		return -ENOMEM;
 
 	/* save initial config */
 	ahci_save_initial_config(&pdev->dev, hpriv);
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 0c0a736eb861..7a7f88b3fa2b 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -26,7 +26,6 @@
 #include <linux/device.h>
 #include <linux/dmi.h>
 #include <linux/gfp.h>
-#include <linux/msi.h>
 #include <scsi/scsi_host.h>
 #include <scsi/scsi_cmnd.h>
 #include <linux/libata.h>
@@ -49,12 +48,22 @@ enum {
 enum board_ids {
 	/* board IDs by feature in alphabetical order */
 	board_ahci,
+	board_ahci_43bit_dma,
 	board_ahci_ign_iferr,
-	board_ahci_mobile,
-	board_ahci_nomsi,
-	board_ahci_noncq,
-	board_ahci_nosntf,
+	board_ahci_no_debounce_delay,
+	board_ahci_no_msi,
+	/*
+	 * board_ahci_pcs_quirk is for legacy Intel platforms.
+	 * Modern Intel platforms should use board_ahci instead.
+	 * (Some modern Intel platforms might have been added with
+	 * board_ahci_pcs_quirk, however, we cannot change them to board_ahci
+	 * without testing that the platform actually works without the quirk.)
+	 */
+	board_ahci_pcs_quirk,
+	board_ahci_pcs_quirk_no_devslp,
+	board_ahci_pcs_quirk_no_sntf,
 	board_ahci_yes_fbs,
+	board_ahci_yes_fbs_atapi_dma,
 
 	/* board IDs for specific chipsets in alphabetical order */
 	board_ahci_al,
@@ -67,12 +76,6 @@ enum board_ids {
 	board_ahci_sb700,	/* for SB700 and SB800 */
 	board_ahci_vt8251,
 
-	/*
-	 * board IDs for Intel chipsets that support more than 6 ports
-	 * *and* end up needing the PCS quirk.
-	 */
-	board_ahci_pcs7,
-
 	/* aliases */
 	board_ahci_mcp_linux	= board_ahci_mcp65,
 	board_ahci_mcp67	= board_ahci_mcp65,
@@ -83,6 +86,7 @@ enum board_ids {
 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
 static void ahci_remove_one(struct pci_dev *dev);
 static void ahci_shutdown_one(struct pci_dev *dev);
+static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv);
 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
 				 unsigned long deadline);
 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
@@ -100,23 +104,23 @@ static int ahci_pci_device_resume(struct device *dev);
 #endif
 #endif /* CONFIG_PM */
 
-static struct scsi_host_template ahci_sht = {
+static const struct scsi_host_template ahci_sht = {
 	AHCI_SHT("ahci"),
 };
 
 static struct ata_port_operations ahci_vt8251_ops = {
 	.inherits		= &ahci_ops,
-	.hardreset		= ahci_vt8251_hardreset,
+	.reset.hardreset	= ahci_vt8251_hardreset,
 };
 
 static struct ata_port_operations ahci_p5wdh_ops = {
 	.inherits		= &ahci_ops,
-	.hardreset		= ahci_p5wdh_hardreset,
+	.reset.hardreset	= ahci_p5wdh_hardreset,
 };
 
 static struct ata_port_operations ahci_avn_ops = {
 	.inherits		= &ahci_ops,
-	.hardreset		= ahci_avn_hardreset,
+	.reset.hardreset	= ahci_avn_hardreset,
 };
 
 static const struct ata_port_info ahci_port_info[] = {
@@ -127,6 +131,13 @@ static const struct ata_port_info ahci_port_info[] = {
 		.udma_mask	= ATA_UDMA6,
 		.port_ops	= &ahci_ops,
 	},
+	[board_ahci_43bit_dma] = {
+		AHCI_HFLAGS	(AHCI_HFLAG_43BIT_ONLY),
+		.flags		= AHCI_FLAG_COMMON,
+		.pio_mask	= ATA_PIO4,
+		.udma_mask	= ATA_UDMA6,
+		.port_ops	= &ahci_ops,
+	},
 	[board_ahci_ign_iferr] = {
 		AHCI_HFLAGS	(AHCI_HFLAG_IGN_IRQ_IF_ERR),
 		.flags		= AHCI_FLAG_COMMON,
@@ -134,29 +145,38 @@ static const struct ata_port_info ahci_port_info[] = {
 		.udma_mask	= ATA_UDMA6,
 		.port_ops	= &ahci_ops,
 	},
-	[board_ahci_mobile] = {
-		AHCI_HFLAGS	(AHCI_HFLAG_IS_MOBILE),
+	[board_ahci_no_debounce_delay] = {
 		.flags		= AHCI_FLAG_COMMON,
+		.link_flags	= ATA_LFLAG_NO_DEBOUNCE_DELAY,
 		.pio_mask	= ATA_PIO4,
 		.udma_mask	= ATA_UDMA6,
 		.port_ops	= &ahci_ops,
 	},
-	[board_ahci_nomsi] = {
+	[board_ahci_no_msi] = {
 		AHCI_HFLAGS	(AHCI_HFLAG_NO_MSI),
 		.flags		= AHCI_FLAG_COMMON,
 		.pio_mask	= ATA_PIO4,
 		.udma_mask	= ATA_UDMA6,
 		.port_ops	= &ahci_ops,
 	},
-	[board_ahci_noncq] = {
-		AHCI_HFLAGS	(AHCI_HFLAG_NO_NCQ),
+	[board_ahci_pcs_quirk] = {
+		AHCI_HFLAGS	(AHCI_HFLAG_INTEL_PCS_QUIRK),
 		.flags		= AHCI_FLAG_COMMON,
 		.pio_mask	= ATA_PIO4,
 		.udma_mask	= ATA_UDMA6,
 		.port_ops	= &ahci_ops,
 	},
-	[board_ahci_nosntf] = {
-		AHCI_HFLAGS	(AHCI_HFLAG_NO_SNTF),
+	[board_ahci_pcs_quirk_no_devslp] = {
+		AHCI_HFLAGS	(AHCI_HFLAG_INTEL_PCS_QUIRK |
+				 AHCI_HFLAG_NO_DEVSLP),
+		.flags		= AHCI_FLAG_COMMON,
+		.pio_mask	= ATA_PIO4,
+		.udma_mask	= ATA_UDMA6,
+		.port_ops	= &ahci_ops,
+	},
+	[board_ahci_pcs_quirk_no_sntf] = {
+		AHCI_HFLAGS	(AHCI_HFLAG_INTEL_PCS_QUIRK |
+				 AHCI_HFLAG_NO_SNTF),
 		.flags		= AHCI_FLAG_COMMON,
 		.pio_mask	= ATA_PIO4,
 		.udma_mask	= ATA_UDMA6,
@@ -169,6 +189,14 @@ static const struct ata_port_info ahci_port_info[] = {
 		.udma_mask	= ATA_UDMA6,
 		.port_ops	= &ahci_ops,
 	},
+	[board_ahci_yes_fbs_atapi_dma] = {
+		AHCI_HFLAGS	(AHCI_HFLAG_YES_FBS |
+				 AHCI_HFLAG_ATAPI_DMA_QUIRK),
+		.flags		= AHCI_FLAG_COMMON,
+		.pio_mask	= ATA_PIO4,
+		.udma_mask	= ATA_UDMA6,
+		.port_ops	= &ahci_ops,
+	},
 	/* by chipsets */
 	[board_ahci_al] = {
 		AHCI_HFLAGS	(AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI),
@@ -178,6 +206,7 @@ static const struct ata_port_info ahci_port_info[] = {
 		.port_ops	= &ahci_ops,
 	},
 	[board_ahci_avn] = {
+		AHCI_HFLAGS	(AHCI_HFLAG_INTEL_PCS_QUIRK),
 		.flags		= AHCI_FLAG_COMMON,
 		.pio_mask	= ATA_PIO4,
 		.udma_mask	= ATA_UDMA6,
@@ -236,120 +265,113 @@ static const struct ata_port_info ahci_port_info[] = {
 		.udma_mask	= ATA_UDMA6,
 		.port_ops	= &ahci_vt8251_ops,
 	},
-	[board_ahci_pcs7] = {
-		.flags		= AHCI_FLAG_COMMON,
-		.pio_mask	= ATA_PIO4,
-		.udma_mask	= ATA_UDMA6,
-		.port_ops	= &ahci_ops,
-	},
 };
 
 static const struct pci_device_id ahci_pci_tbl[] = {
 	/* Intel */
-	{ PCI_VDEVICE(INTEL, 0x06d6), board_ahci }, /* Comet Lake PCH-H RAID */
-	{ PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
-	{ PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
-	{ PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
-	{ PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
-	{ PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
+	{ PCI_VDEVICE(INTEL, 0x06d6), board_ahci_pcs_quirk }, /* Comet Lake PCH-H RAID */
+	{ PCI_VDEVICE(INTEL, 0x2652), board_ahci_pcs_quirk }, /* ICH6 */
+	{ PCI_VDEVICE(INTEL, 0x2653), board_ahci_pcs_quirk }, /* ICH6M */
+	{ PCI_VDEVICE(INTEL, 0x27c1), board_ahci_pcs_quirk }, /* ICH7 */
+	{ PCI_VDEVICE(INTEL, 0x27c5), board_ahci_pcs_quirk }, /* ICH7M */
+	{ PCI_VDEVICE(INTEL, 0x27c3), board_ahci_pcs_quirk }, /* ICH7R */
 	{ PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
-	{ PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
-	{ PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
-	{ PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
-	{ PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
-	{ PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
-	{ PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
-	{ PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
-	{ PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
-	{ PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
-	{ PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
-	{ PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
-	{ PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
-	{ PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
-	{ PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
-	{ PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */
-	{ PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */
-	{ PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */
-	{ PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */
-	{ PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */
-	{ PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
-	{ PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */
-	{ PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
-	{ PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
-	{ PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
-	{ PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
-	{ PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
-	{ PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
-	{ PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
-	{ PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
-	{ PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
-	{ PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */
-	{ PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
-	{ PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */
-	{ PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
-	{ PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */
-	{ PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */
-	{ PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */
-	{ PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */
-	{ PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */
-	{ PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */
-	{ PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */
-	{ PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */
-	{ PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */
-	{ PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */
-	{ PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */
-	{ PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */
-	{ PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */
-	{ PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */
-	{ PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */
-	{ PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */
-	{ PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */
-	{ PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */
-	{ PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */
-	{ PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */
-	{ PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
-	{ PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */
-	{ PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
-	{ PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */
-	{ PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
-	{ PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
-	{ PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
-	{ PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
-	{ PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
-	{ PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
-	{ PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
-	{ PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
-	{ PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */
-	{ PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
-	{ PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
-	{ PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
-	{ PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */
-	{ PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
-	{ PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
-	{ PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */
-	{ PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
-	{ PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */
-	{ PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
-	{ PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */
-	{ PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
-	{ PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */
-	{ PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */
-	{ PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */
-	{ PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */
-	{ PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */
-	{ PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */
-	{ PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */
-	{ PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */
-	{ PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */
-	{ PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_mobile }, /* Cannon Lake PCH-LP AHCI */
-	{ PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
-	{ PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
-	{ PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
-	{ PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
-	{ PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
-	{ PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
-	{ PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
-	{ PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
+	{ PCI_VDEVICE(INTEL, 0x2681), board_ahci_pcs_quirk }, /* ESB2 */
+	{ PCI_VDEVICE(INTEL, 0x2682), board_ahci_pcs_quirk }, /* ESB2 */
+	{ PCI_VDEVICE(INTEL, 0x2683), board_ahci_pcs_quirk }, /* ESB2 */
+	{ PCI_VDEVICE(INTEL, 0x27c6), board_ahci_pcs_quirk }, /* ICH7-M DH */
+	{ PCI_VDEVICE(INTEL, 0x2821), board_ahci_pcs_quirk }, /* ICH8 */
+	{ PCI_VDEVICE(INTEL, 0x2822), board_ahci_pcs_quirk_no_sntf }, /* ICH8/Lewisburg RAID*/
+	{ PCI_VDEVICE(INTEL, 0x2824), board_ahci_pcs_quirk }, /* ICH8 */
+	{ PCI_VDEVICE(INTEL, 0x2829), board_ahci_pcs_quirk }, /* ICH8M */
+	{ PCI_VDEVICE(INTEL, 0x282a), board_ahci_pcs_quirk }, /* ICH8M */
+	{ PCI_VDEVICE(INTEL, 0x2922), board_ahci_pcs_quirk }, /* ICH9 */
+	{ PCI_VDEVICE(INTEL, 0x2923), board_ahci_pcs_quirk }, /* ICH9 */
+	{ PCI_VDEVICE(INTEL, 0x2924), board_ahci_pcs_quirk }, /* ICH9 */
+	{ PCI_VDEVICE(INTEL, 0x2925), board_ahci_pcs_quirk }, /* ICH9 */
+	{ PCI_VDEVICE(INTEL, 0x2927), board_ahci_pcs_quirk }, /* ICH9 */
+	{ PCI_VDEVICE(INTEL, 0x2929), board_ahci_pcs_quirk }, /* ICH9M */
+	{ PCI_VDEVICE(INTEL, 0x292a), board_ahci_pcs_quirk }, /* ICH9M */
+	{ PCI_VDEVICE(INTEL, 0x292b), board_ahci_pcs_quirk }, /* ICH9M */
+	{ PCI_VDEVICE(INTEL, 0x292c), board_ahci_pcs_quirk }, /* ICH9M */
+	{ PCI_VDEVICE(INTEL, 0x292f), board_ahci_pcs_quirk }, /* ICH9M */
+	{ PCI_VDEVICE(INTEL, 0x294d), board_ahci_pcs_quirk }, /* ICH9 */
+	{ PCI_VDEVICE(INTEL, 0x294e), board_ahci_pcs_quirk }, /* ICH9M */
+	{ PCI_VDEVICE(INTEL, 0x502a), board_ahci_pcs_quirk }, /* Tolapai */
+	{ PCI_VDEVICE(INTEL, 0x502b), board_ahci_pcs_quirk }, /* Tolapai */
+	{ PCI_VDEVICE(INTEL, 0x3a05), board_ahci_pcs_quirk }, /* ICH10 */
+	{ PCI_VDEVICE(INTEL, 0x3a22), board_ahci_pcs_quirk }, /* ICH10 */
+	{ PCI_VDEVICE(INTEL, 0x3a25), board_ahci_pcs_quirk }, /* ICH10 */
+	{ PCI_VDEVICE(INTEL, 0x3b22), board_ahci_pcs_quirk }, /* PCH AHCI */
+	{ PCI_VDEVICE(INTEL, 0x3b23), board_ahci_pcs_quirk }, /* PCH AHCI */
+	{ PCI_VDEVICE(INTEL, 0x3b24), board_ahci_pcs_quirk }, /* PCH RAID */
+	{ PCI_VDEVICE(INTEL, 0x3b25), board_ahci_pcs_quirk }, /* PCH RAID */
+	{ PCI_VDEVICE(INTEL, 0x3b29), board_ahci_pcs_quirk }, /* PCH M AHCI */
+	{ PCI_VDEVICE(INTEL, 0x3b2b), board_ahci_pcs_quirk }, /* PCH RAID */
+	{ PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_pcs_quirk }, /* PCH M RAID */
+	{ PCI_VDEVICE(INTEL, 0x3b2f), board_ahci_pcs_quirk }, /* PCH AHCI */
+	{ PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */
+	{ PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */
+	{ PCI_VDEVICE(INTEL, 0x19b2), board_ahci }, /* DNV AHCI */
+	{ PCI_VDEVICE(INTEL, 0x19b3), board_ahci }, /* DNV AHCI */
+	{ PCI_VDEVICE(INTEL, 0x19b4), board_ahci }, /* DNV AHCI */
+	{ PCI_VDEVICE(INTEL, 0x19b5), board_ahci }, /* DNV AHCI */
+	{ PCI_VDEVICE(INTEL, 0x19b6), board_ahci }, /* DNV AHCI */
+	{ PCI_VDEVICE(INTEL, 0x19b7), board_ahci }, /* DNV AHCI */
+	{ PCI_VDEVICE(INTEL, 0x19bE), board_ahci }, /* DNV AHCI */
+	{ PCI_VDEVICE(INTEL, 0x19bF), board_ahci }, /* DNV AHCI */
+	{ PCI_VDEVICE(INTEL, 0x19c0), board_ahci }, /* DNV AHCI */
+	{ PCI_VDEVICE(INTEL, 0x19c1), board_ahci }, /* DNV AHCI */
+	{ PCI_VDEVICE(INTEL, 0x19c2), board_ahci }, /* DNV AHCI */
+	{ PCI_VDEVICE(INTEL, 0x19c3), board_ahci }, /* DNV AHCI */
+	{ PCI_VDEVICE(INTEL, 0x19c4), board_ahci }, /* DNV AHCI */
+	{ PCI_VDEVICE(INTEL, 0x19c5), board_ahci }, /* DNV AHCI */
+	{ PCI_VDEVICE(INTEL, 0x19c6), board_ahci }, /* DNV AHCI */
+	{ PCI_VDEVICE(INTEL, 0x19c7), board_ahci }, /* DNV AHCI */
+	{ PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */
+	{ PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */
+	{ PCI_VDEVICE(INTEL, 0x1c02), board_ahci_pcs_quirk }, /* CPT AHCI */
+	{ PCI_VDEVICE(INTEL, 0x1c03), board_ahci_pcs_quirk }, /* CPT M AHCI */
+	{ PCI_VDEVICE(INTEL, 0x1c04), board_ahci_pcs_quirk }, /* CPT RAID */
+	{ PCI_VDEVICE(INTEL, 0x1c05), board_ahci_pcs_quirk }, /* CPT M RAID */
+	{ PCI_VDEVICE(INTEL, 0x1c06), board_ahci_pcs_quirk }, /* CPT RAID */
+	{ PCI_VDEVICE(INTEL, 0x1c07), board_ahci_pcs_quirk }, /* CPT RAID */
+	{ PCI_VDEVICE(INTEL, 0x1d02), board_ahci_pcs_quirk }, /* PBG AHCI */
+	{ PCI_VDEVICE(INTEL, 0x1d04), board_ahci_pcs_quirk }, /* PBG RAID */
+	{ PCI_VDEVICE(INTEL, 0x1d06), board_ahci_pcs_quirk }, /* PBG RAID */
+	{ PCI_VDEVICE(INTEL, 0x2323), board_ahci_pcs_quirk }, /* DH89xxCC AHCI */
+	{ PCI_VDEVICE(INTEL, 0x1e02), board_ahci_pcs_quirk }, /* Panther Point AHCI */
+	{ PCI_VDEVICE(INTEL, 0x1e03), board_ahci_pcs_quirk }, /* Panther M AHCI */
+	{ PCI_VDEVICE(INTEL, 0x1e04), board_ahci_pcs_quirk }, /* Panther Point RAID */
+	{ PCI_VDEVICE(INTEL, 0x1e05), board_ahci_pcs_quirk }, /* Panther Point RAID */
+	{ PCI_VDEVICE(INTEL, 0x1e06), board_ahci_pcs_quirk }, /* Panther Point RAID */
+	{ PCI_VDEVICE(INTEL, 0x1e07), board_ahci_pcs_quirk }, /* Panther M RAID */
+	{ PCI_VDEVICE(INTEL, 0x1e0e), board_ahci_pcs_quirk }, /* Panther Point RAID */
+	{ PCI_VDEVICE(INTEL, 0x8c02), board_ahci_pcs_quirk }, /* Lynx Point AHCI */
+	{ PCI_VDEVICE(INTEL, 0x8c03), board_ahci_pcs_quirk }, /* Lynx M AHCI */
+	{ PCI_VDEVICE(INTEL, 0x8c04), board_ahci_pcs_quirk }, /* Lynx Point RAID */
+	{ PCI_VDEVICE(INTEL, 0x8c05), board_ahci_pcs_quirk }, /* Lynx M RAID */
+	{ PCI_VDEVICE(INTEL, 0x8c06), board_ahci_pcs_quirk }, /* Lynx Point RAID */
+	{ PCI_VDEVICE(INTEL, 0x8c07), board_ahci_pcs_quirk }, /* Lynx M RAID */
+	{ PCI_VDEVICE(INTEL, 0x8c0e), board_ahci_pcs_quirk }, /* Lynx Point RAID */
+	{ PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_pcs_quirk }, /* Lynx M RAID */
+	{ PCI_VDEVICE(INTEL, 0x9c02), board_ahci_pcs_quirk }, /* Lynx LP AHCI */
+	{ PCI_VDEVICE(INTEL, 0x9c03), board_ahci_pcs_quirk }, /* Lynx LP AHCI */
+	{ PCI_VDEVICE(INTEL, 0x9c04), board_ahci_pcs_quirk }, /* Lynx LP RAID */
+	{ PCI_VDEVICE(INTEL, 0x9c05), board_ahci_pcs_quirk }, /* Lynx LP RAID */
+	{ PCI_VDEVICE(INTEL, 0x9c06), board_ahci_pcs_quirk }, /* Lynx LP RAID */
+	{ PCI_VDEVICE(INTEL, 0x9c07), board_ahci_pcs_quirk }, /* Lynx LP RAID */
+	{ PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_pcs_quirk }, /* Lynx LP RAID */
+	{ PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_pcs_quirk }, /* Lynx LP RAID */
+	{ PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_pcs_quirk }, /* Cannon Lake PCH-LP AHCI */
+	{ PCI_VDEVICE(INTEL, 0x1f22), board_ahci_pcs_quirk }, /* Avoton AHCI */
+	{ PCI_VDEVICE(INTEL, 0x1f23), board_ahci_pcs_quirk }, /* Avoton AHCI */
+	{ PCI_VDEVICE(INTEL, 0x1f24), board_ahci_pcs_quirk }, /* Avoton RAID */
+	{ PCI_VDEVICE(INTEL, 0x1f25), board_ahci_pcs_quirk }, /* Avoton RAID */
+	{ PCI_VDEVICE(INTEL, 0x1f26), board_ahci_pcs_quirk }, /* Avoton RAID */
+	{ PCI_VDEVICE(INTEL, 0x1f27), board_ahci_pcs_quirk }, /* Avoton RAID */
+	{ PCI_VDEVICE(INTEL, 0x1f2e), board_ahci_pcs_quirk }, /* Avoton RAID */
+	{ PCI_VDEVICE(INTEL, 0x1f2f), board_ahci_pcs_quirk }, /* Avoton RAID */
 	{ PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
 	{ PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
 	{ PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
@@ -358,60 +380,64 @@ static const struct pci_device_id ahci_pci_tbl[] = {
 	{ PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
 	{ PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
 	{ PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
-	{ PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
-	{ PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
-	{ PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
-	{ PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
-	{ PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
-	{ PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
-	{ PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
-	{ PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
-	{ PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
-	{ PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
-	{ PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
-	{ PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */
-	{ PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */
-	{ PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */
-	{ PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */
-	{ PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
-	{ PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */
-	{ PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
-	{ PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */
-	{ PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
-	{ PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */
-	{ PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
-	{ PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */
-	{ PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */
-	{ PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */
-	{ PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */
-	{ PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
-	{ PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */
-	{ PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
-	{ PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
-	{ PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */
-	{ PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
-	{ PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
-	{ PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
-	{ PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
-	{ PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
-	{ PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
-	{ PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
-	{ PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
-	{ PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
-	{ PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
-	{ PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
-	{ PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
-	{ PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
-	{ PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
-	{ PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */
-	{ PCI_VDEVICE(INTEL, 0xa386), board_ahci }, /* Comet Lake PCH-V RAID */
-	{ PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */
-	{ PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */
-	{ PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */
-	{ PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */
-	{ PCI_VDEVICE(INTEL, 0x34d3), board_ahci_mobile }, /* Ice Lake LP AHCI */
-	{ PCI_VDEVICE(INTEL, 0x02d3), board_ahci_mobile }, /* Comet Lake PCH-U AHCI */
-	{ PCI_VDEVICE(INTEL, 0x02d7), board_ahci_mobile }, /* Comet Lake PCH RAID */
+	{ PCI_VDEVICE(INTEL, 0x2823), board_ahci_pcs_quirk }, /* Wellsburg/Lewisburg AHCI*/
+	{ PCI_VDEVICE(INTEL, 0x2826), board_ahci_pcs_quirk }, /* *burg SATA0 'RAID' */
+	{ PCI_VDEVICE(INTEL, 0x2827), board_ahci_pcs_quirk }, /* *burg SATA1 'RAID' */
+	{ PCI_VDEVICE(INTEL, 0x282f), board_ahci_pcs_quirk }, /* *burg SATA2 'RAID' */
+	{ PCI_VDEVICE(INTEL, 0x43d4), board_ahci_pcs_quirk }, /* Rocket Lake PCH-H RAID */
+	{ PCI_VDEVICE(INTEL, 0x43d5), board_ahci_pcs_quirk }, /* Rocket Lake PCH-H RAID */
+	{ PCI_VDEVICE(INTEL, 0x43d6), board_ahci_pcs_quirk }, /* Rocket Lake PCH-H RAID */
+	{ PCI_VDEVICE(INTEL, 0x43d7), board_ahci_pcs_quirk }, /* Rocket Lake PCH-H RAID */
+	{ PCI_VDEVICE(INTEL, 0x8d02), board_ahci_pcs_quirk }, /* Wellsburg AHCI */
+	{ PCI_VDEVICE(INTEL, 0x8d04), board_ahci_pcs_quirk }, /* Wellsburg RAID */
+	{ PCI_VDEVICE(INTEL, 0x8d06), board_ahci_pcs_quirk }, /* Wellsburg RAID */
+	{ PCI_VDEVICE(INTEL, 0x8d0e), board_ahci_pcs_quirk }, /* Wellsburg RAID */
+	{ PCI_VDEVICE(INTEL, 0x8d62), board_ahci_pcs_quirk }, /* Wellsburg AHCI */
+	{ PCI_VDEVICE(INTEL, 0x8d64), board_ahci_pcs_quirk }, /* Wellsburg RAID */
+	{ PCI_VDEVICE(INTEL, 0x8d66), board_ahci_pcs_quirk }, /* Wellsburg RAID */
+	{ PCI_VDEVICE(INTEL, 0x8d6e), board_ahci_pcs_quirk }, /* Wellsburg RAID */
+	{ PCI_VDEVICE(INTEL, 0x23a3), board_ahci_pcs_quirk }, /* Coleto Creek AHCI */
+	{ PCI_VDEVICE(INTEL, 0x9c83), board_ahci_pcs_quirk }, /* Wildcat LP AHCI */
+	{ PCI_VDEVICE(INTEL, 0x9c85), board_ahci_pcs_quirk }, /* Wildcat LP RAID */
+	{ PCI_VDEVICE(INTEL, 0x9c87), board_ahci_pcs_quirk }, /* Wildcat LP RAID */
+	{ PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_pcs_quirk }, /* Wildcat LP RAID */
+	{ PCI_VDEVICE(INTEL, 0x8c82), board_ahci_pcs_quirk }, /* 9 Series AHCI */
+	{ PCI_VDEVICE(INTEL, 0x8c83), board_ahci_pcs_quirk }, /* 9 Series M AHCI */
+	{ PCI_VDEVICE(INTEL, 0x8c84), board_ahci_pcs_quirk }, /* 9 Series RAID */
+	{ PCI_VDEVICE(INTEL, 0x8c85), board_ahci_pcs_quirk }, /* 9 Series M RAID */
+	{ PCI_VDEVICE(INTEL, 0x8c86), board_ahci_pcs_quirk }, /* 9 Series RAID */
+	{ PCI_VDEVICE(INTEL, 0x8c87), board_ahci_pcs_quirk }, /* 9 Series M RAID */
+	{ PCI_VDEVICE(INTEL, 0x8c8e), board_ahci_pcs_quirk }, /* 9 Series RAID */
+	{ PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_pcs_quirk }, /* 9 Series M RAID */
+	{ PCI_VDEVICE(INTEL, 0x9d03), board_ahci_pcs_quirk }, /* Sunrise LP AHCI */
+	{ PCI_VDEVICE(INTEL, 0x9d05), board_ahci_pcs_quirk }, /* Sunrise LP RAID */
+	{ PCI_VDEVICE(INTEL, 0x9d07), board_ahci_pcs_quirk }, /* Sunrise LP RAID */
+	{ PCI_VDEVICE(INTEL, 0xa102), board_ahci_pcs_quirk }, /* Sunrise Point-H AHCI */
+	{ PCI_VDEVICE(INTEL, 0xa103), board_ahci_pcs_quirk }, /* Sunrise M AHCI */
+	{ PCI_VDEVICE(INTEL, 0xa105), board_ahci_pcs_quirk }, /* Sunrise Point-H RAID */
+	{ PCI_VDEVICE(INTEL, 0xa106), board_ahci_pcs_quirk }, /* Sunrise Point-H RAID */
+	{ PCI_VDEVICE(INTEL, 0xa107), board_ahci_pcs_quirk }, /* Sunrise M RAID */
+	{ PCI_VDEVICE(INTEL, 0xa10f), board_ahci_pcs_quirk }, /* Sunrise Point-H RAID */
+	{ PCI_VDEVICE(INTEL, 0xa182), board_ahci_pcs_quirk }, /* Lewisburg AHCI*/
+	{ PCI_VDEVICE(INTEL, 0xa186), board_ahci_pcs_quirk }, /* Lewisburg RAID*/
+	{ PCI_VDEVICE(INTEL, 0xa1d2), board_ahci_pcs_quirk }, /* Lewisburg RAID*/
+	{ PCI_VDEVICE(INTEL, 0xa1d6), board_ahci_pcs_quirk }, /* Lewisburg RAID*/
+	{ PCI_VDEVICE(INTEL, 0xa202), board_ahci_pcs_quirk }, /* Lewisburg AHCI*/
+	{ PCI_VDEVICE(INTEL, 0xa206), board_ahci_pcs_quirk }, /* Lewisburg RAID*/
+	{ PCI_VDEVICE(INTEL, 0xa252), board_ahci_pcs_quirk }, /* Lewisburg RAID*/
+	{ PCI_VDEVICE(INTEL, 0xa256), board_ahci_pcs_quirk }, /* Lewisburg RAID*/
+	{ PCI_VDEVICE(INTEL, 0xa356), board_ahci_pcs_quirk }, /* Cannon Lake PCH-H RAID */
+	{ PCI_VDEVICE(INTEL, 0x06d7), board_ahci_pcs_quirk }, /* Comet Lake-H RAID */
+	{ PCI_VDEVICE(INTEL, 0xa386), board_ahci_pcs_quirk }, /* Comet Lake PCH-V RAID */
+	{ PCI_VDEVICE(INTEL, 0x0f22), board_ahci_pcs_quirk }, /* Bay Trail AHCI */
+	{ PCI_VDEVICE(INTEL, 0x0f23), board_ahci_pcs_quirk_no_devslp }, /* Bay Trail AHCI */
+	{ PCI_VDEVICE(INTEL, 0x22a3), board_ahci_pcs_quirk }, /* Cherry Tr. AHCI */
+	{ PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_pcs_quirk }, /* ApolloLake AHCI */
+	{ PCI_VDEVICE(INTEL, 0x34d3), board_ahci_pcs_quirk }, /* Ice Lake LP AHCI */
+	{ PCI_VDEVICE(INTEL, 0x02d3), board_ahci_pcs_quirk }, /* Comet Lake PCH-U AHCI */
+	{ PCI_VDEVICE(INTEL, 0x02d7), board_ahci_pcs_quirk }, /* Comet Lake PCH RAID */
+	/* Elkhart Lake IDs 0x4b60 & 0x4b62 https://sata-io.org/product/8803 not tested yet */
+	{ PCI_VDEVICE(INTEL, 0x4b63), board_ahci_pcs_quirk }, /* Elkhart Lake AHCI */
 
 	/* JMicron 360/1/3/5/6, match class to avoid IDE function */
 	{ PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
@@ -437,11 +463,17 @@ static const struct pci_device_id ahci_pci_tbl[] = {
 		board_ahci_al },
 	/* AMD */
 	{ PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
+	{ PCI_VDEVICE(AMD, 0x7801), board_ahci_no_debounce_delay }, /* AMD Hudson-2 (AHCI mode) */
 	{ PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
+	{ PCI_VDEVICE(AMD, 0x7901), board_ahci }, /* AMD Green Sardine */
 	/* AMD is using RAID class only for ahci controllers */
 	{ PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 	  PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
 
+	/* Dell S140/S150 */
+	{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_SUBVENDOR_ID_DELL, PCI_ANY_ID,
+	  PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci_pcs_quirk },
+
 	/* VIA */
 	{ PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
 	{ PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
@@ -566,8 +598,12 @@ static const struct pci_device_id ahci_pci_tbl[] = {
 	  .driver_data = board_ahci_yes_fbs },
 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
 	  .driver_data = board_ahci_yes_fbs },
+	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9215),
+	  .driver_data = board_ahci_yes_fbs_atapi_dma },
 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
 	  .driver_data = board_ahci_yes_fbs },
+	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9235),
+	  .driver_data = board_ahci_no_debounce_delay },
 	{ PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
 	  .driver_data = board_ahci_yes_fbs },
 	{ PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
@@ -577,20 +613,26 @@ static const struct pci_device_id ahci_pci_tbl[] = {
 	{ PCI_VDEVICE(PROMISE, 0x3f20), board_ahci },	/* PDC42819 */
 	{ PCI_VDEVICE(PROMISE, 0x3781), board_ahci },   /* FastTrak TX8660 ahci-mode */
 
-	/* Asmedia */
-	{ PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci },	/* ASM1060 */
-	{ PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci },	/* ASM1060 */
-	{ PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci },	/* ASM1061 */
-	{ PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci },	/* ASM1062 */
-	{ PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci },   /* ASM1061R */
-	{ PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci },   /* ASM1062R */
+	/* ASMedia */
+	{ PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci_43bit_dma },	/* ASM1060 */
+	{ PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci_43bit_dma },	/* ASM1060 */
+	{ PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci_43bit_dma },	/* ASM1061 */
+	{ PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci_43bit_dma },	/* ASM1061/1062 */
+	{ PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci_43bit_dma },	/* ASM1061R */
+	{ PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci_43bit_dma },	/* ASM1062R */
+	{ PCI_VDEVICE(ASMEDIA, 0x0624), board_ahci_43bit_dma },	/* ASM1062+JMB575 */
+	{ PCI_VDEVICE(ASMEDIA, 0x1062), board_ahci },	/* ASM1062A */
+	{ PCI_VDEVICE(ASMEDIA, 0x1064), board_ahci },	/* ASM1064 */
+	{ PCI_VDEVICE(ASMEDIA, 0x1164), board_ahci },   /* ASM1164 */
+	{ PCI_VDEVICE(ASMEDIA, 0x1165), board_ahci },   /* ASM1165 */
+	{ PCI_VDEVICE(ASMEDIA, 0x1166), board_ahci },   /* ASM1166 */
 
 	/*
 	 * Samsung SSDs found on some macbooks.  NCQ times out if MSI is
 	 * enabled.  https://bugzilla.kernel.org/show_bug.cgi?id=60731
 	 */
-	{ PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
-	{ PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
+	{ PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_no_msi },
+	{ PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_no_msi },
 
 	/* Enmotus */
 	{ PCI_DEVICE(0x1c44, 0x8000), board_ahci },
@@ -632,14 +674,109 @@ MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
 
 static int mobile_lpm_policy = -1;
 module_param(mobile_lpm_policy, int, 0644);
-MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
+MODULE_PARM_DESC(mobile_lpm_policy,
+		 "Default LPM policy. Despite its name, this parameter applies "
+		 "to all chipsets, including desktop and server chipsets");
+
+static char *ahci_mask_port_map;
+module_param_named(mask_port_map, ahci_mask_port_map, charp, 0444);
+MODULE_PARM_DESC(mask_port_map,
+		 "32-bits port map masks to ignore controllers ports. "
+		 "Valid values are: "
+		 "\"<mask>\" to apply the same mask to all AHCI controller "
+		 "devices, and \"<pci_dev>=<mask>,<pci_dev>=<mask>,...\" to "
+		 "specify different masks for the controllers specified, "
+		 "where <pci_dev> is the PCI ID of an AHCI controller in the "
+		 "form \"domain:bus:dev.func\"");
+
+static char *ahci_mask_port_ext;
+module_param_named(mask_port_ext, ahci_mask_port_ext, charp, 0444);
+MODULE_PARM_DESC(mask_port_ext,
+		 "32-bits mask to ignore the external/hotplug capability of ports. "
+		 "Valid values are: "
+		 "\"<mask>\" to apply the same mask to all AHCI controller "
+		 "devices, and \"<pci_dev>=<mask>,<pci_dev>=<mask>,...\" to "
+		 "specify different masks for the controllers specified, "
+		 "where <pci_dev> is the PCI ID of an AHCI controller in the "
+		 "form \"domain:bus:dev.func\"");
+
+static u32 ahci_port_mask(struct device *dev, char *mask_s)
+{
+	unsigned int mask;
+
+	if (kstrtouint(mask_s, 0, &mask)) {
+		dev_err(dev, "Invalid port map mask\n");
+		return 0;
+	}
+
+	return mask;
+}
+
+static u32 ahci_get_port_mask(struct device *dev, char *mask_p)
+{
+	char *param, *end, *str, *mask_s;
+	char *name;
+	u32 mask = 0;
+
+	if (!mask_p || !strlen(mask_p))
+		return 0;
+
+	str = kstrdup(mask_p, GFP_KERNEL);
+	if (!str)
+		return 0;
+
+	/* Handle single mask case */
+	if (!strchr(str, '=')) {
+		mask = ahci_port_mask(dev, str);
+		goto free;
+	}
+
+	/*
+	 * Mask list case: parse the parameter to get the mask only if
+	 * the device name matches.
+	 */
+	param = str;
+	end = param + strlen(param);
+	while (param && param < end && *param) {
+		name = param;
+		param = strchr(name, '=');
+		if (!param)
+			break;
+
+		*param = '\0';
+		param++;
+		if (param >= end)
+			break;
+
+		if (strcmp(dev_name(dev), name) != 0) {
+			param = strchr(param, ',');
+			if (param)
+				param++;
+			continue;
+		}
+
+		mask_s = param;
+		param = strchr(mask_s, ',');
+		if (param) {
+			*param = '\0';
+			param++;
+		}
+
+		mask = ahci_port_mask(dev, mask_s);
+	}
+
+free:
+	kfree(str);
+
+	return mask;
+}
 
 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
 					 struct ahci_host_priv *hpriv)
 {
 	if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
 		dev_info(&pdev->dev, "JMB361 has only one port\n");
-		hpriv->force_port_map = 1;
+		hpriv->saved_port_map = 1;
 	}
 
 	/*
@@ -656,9 +793,34 @@ static void ahci_pci_save_initial_config(struct pci_dev *pdev,
 			  "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
 	}
 
+	/* Handle port map masks passed as module parameter. */
+	hpriv->mask_port_map =
+		ahci_get_port_mask(&pdev->dev, ahci_mask_port_map);
+	hpriv->mask_port_ext =
+		ahci_get_port_mask(&pdev->dev, ahci_mask_port_ext);
+
 	ahci_save_initial_config(&pdev->dev, hpriv);
 }
 
+static int ahci_pci_reset_controller(struct ata_host *host)
+{
+	struct pci_dev *pdev = to_pci_dev(host->dev);
+	struct ahci_host_priv *hpriv = host->private_data;
+	int rc;
+
+	rc = ahci_reset_controller(host);
+	if (rc)
+		return rc;
+
+	/*
+	 * If platform firmware failed to enable ports, try to enable
+	 * them here.
+	 */
+	ahci_intel_pcs_quirk(pdev, hpriv);
+
+	return 0;
+}
+
 static void ahci_pci_init_controller(struct ata_host *host)
 {
 	struct ahci_host_priv *hpriv = host->private_data;
@@ -672,13 +834,13 @@ static void ahci_pci_init_controller(struct ata_host *host)
 			mv = 2;
 		else
 			mv = 4;
-		port_mmio = __ahci_port_base(host, mv);
+		port_mmio = __ahci_port_base(hpriv, mv);
 
 		writel(0, port_mmio + PORT_IRQ_MASK);
 
 		/* clear port IRQ */
 		tmp = readl(port_mmio + PORT_IRQ_STAT);
-		VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
+		dev_dbg(&pdev->dev, "PORT_IRQ_STAT 0x%x\n", tmp);
 		if (tmp)
 			writel(tmp, port_mmio + PORT_IRQ_STAT);
 	}
@@ -694,8 +856,6 @@ static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
 	bool online;
 	int rc;
 
-	DPRINTK("ENTER\n");
-
 	hpriv->stop_engine(ap);
 
 	rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
@@ -703,8 +863,6 @@ static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
 
 	hpriv->start_engine(ap);
 
-	DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
-
 	/* vt8251 doesn't clear BSY on signature FIS reception,
 	 * request follow-up softreset.
 	 */
@@ -726,7 +884,7 @@ static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
 
 	/* clear D2H reception area to properly wait for D2H FIS */
 	ata_tf_init(link->device, &tf);
-	tf.command = ATA_BUSY;
+	tf.status = ATA_BUSY;
 	ata_tf_to_fis(&tf, 0, 0, d2h_fis);
 
 	rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
@@ -774,7 +932,7 @@ static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
 			      unsigned long deadline)
 {
-	const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
+	const unsigned int *timing = sata_ehc_deb_timing(&link->eh_context);
 	struct ata_port *ap = link->ap;
 	struct ahci_port_priv *pp = ap->private_data;
 	struct ahci_host_priv *hpriv = ap->host->private_data;
@@ -784,8 +942,6 @@ static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
 	bool online;
 	int rc, i;
 
-	DPRINTK("ENTER\n");
-
 	hpriv->stop_engine(ap);
 
 	for (i = 0; i < 2; i++) {
@@ -797,7 +953,7 @@ static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
 
 		/* clear D2H reception area to properly wait for D2H FIS */
 		ata_tf_init(link->device, &tf);
-		tf.command = ATA_BUSY;
+		tf.status = ATA_BUSY;
 		ata_tf_to_fis(&tf, 0, 0, d2h_fis);
 
 		rc = sata_link_hardreset(link, timing, deadline, &online,
@@ -807,8 +963,7 @@ static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
 				(sstatus & 0xf) != 1)
 			break;
 
-		ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
-				port);
+		ata_link_info(link,  "avn bounce port%d\n", port);
 
 		pci_read_config_word(pdev, 0x92, &val);
 		val &= ~(1 << port);
@@ -824,7 +979,6 @@ static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
 	if (online)
 		*class = ahci_dev_classify(ap);
 
-	DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
 	return rc;
 }
 
@@ -861,7 +1015,7 @@ static int ahci_pci_device_runtime_resume(struct device *dev)
 	struct ata_host *host = pci_get_drvdata(pdev);
 	int rc;
 
-	rc = ahci_reset_controller(host);
+	rc = ahci_pci_reset_controller(host);
 	if (rc)
 		return rc;
 	ahci_pci_init_controller(host);
@@ -882,7 +1036,8 @@ static int ahci_pci_device_suspend(struct device *dev)
 	}
 
 	ahci_pci_disable_interrupts(host);
-	return ata_host_suspend(host, PMSG_SUSPEND);
+	ata_host_suspend(host, PMSG_SUSPEND);
+	return 0;
 }
 
 static int ahci_pci_device_resume(struct device *dev)
@@ -896,7 +1051,7 @@ static int ahci_pci_device_resume(struct device *dev)
 		ahci_mcp89_apple_enable(pdev);
 
 	if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
-		rc = ahci_reset_controller(host);
+		rc = ahci_pci_reset_controller(host);
 		if (rc)
 			return rc;
 
@@ -911,11 +1066,20 @@ static int ahci_pci_device_resume(struct device *dev)
 
 #endif /* CONFIG_PM */
 
-static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
+static int ahci_configure_dma_masks(struct pci_dev *pdev,
+				    struct ahci_host_priv *hpriv)
 {
-	const int dma_bits = using_dac ? 64 : 32;
+	int dma_bits;
 	int rc;
 
+	if (hpriv->cap & HOST_CAP_64) {
+		dma_bits = 64;
+		if (hpriv->flags & AHCI_HFLAG_43BIT_ONLY)
+			dma_bits = 43;
+	} else {
+		dma_bits = 32;
+	}
+
 	/*
 	 * If the device fixup already set the dma_mask to some non-standard
 	 * value, don't extend it here. This happens on STA2X11, for example.
@@ -1233,7 +1397,7 @@ static bool ahci_broken_suspend(struct pci_dev *pdev)
 		 * V1.03 is known to be broken.  V3.04 is known to
 		 * work.  Between, there are V1.06, V2.06 and V3.03
 		 * that we don't have much idea about.  For now,
-		 * blacklist anything older than V3.04.
+		 * assume that anything older than V3.04 is broken.
 		 *
 		 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
 		 */
@@ -1262,8 +1426,15 @@ static bool ahci_broken_suspend(struct pci_dev *pdev)
 
 static bool ahci_broken_lpm(struct pci_dev *pdev)
 {
+	/*
+	 * Platforms with LPM problems.
+	 * If driver_data is NULL, there is no existing BIOS version with
+	 * functioning LPM.
+	 * If driver_data is non-NULL, then driver_data contains the DMI BIOS
+	 * build date of the first BIOS version with functioning LPM (i.e. older
+	 * BIOS versions have broken LPM).
+	 */
 	static const struct dmi_system_id sysids[] = {
-		/* Various Lenovo 50 series have LPM issues with older BIOSen */
 		{
 			.matches = {
 				DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
@@ -1290,13 +1461,30 @@ static bool ahci_broken_lpm(struct pci_dev *pdev)
 				DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
 				DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
 			},
+			.driver_data = "20180409", /* 2.35 */
+		},
+		{
+			.matches = {
+				DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
+				DMI_MATCH(DMI_PRODUCT_NAME, "ASUSPRO D840MB_M840SA"),
+			},
+			/* 320 is broken, there is no known good version. */
+		},
+		{
 			/*
-			 * Note date based on release notes, 2.35 has been
-			 * reported to be good, but I've been unable to get
-			 * a hold of the reporter to get the DMI BIOS date.
-			 * TODO: fix this.
+			 * AMD 500 Series Chipset SATA Controller [1022:43eb]
+			 * on this motherboard timeouts on ports 5 and 6 when
+			 * LPM is enabled, at least with WDC WD20EFAX-68FB5N0
+			 * hard drives. LPM with the same drive works fine on
+			 * all other ports on the same controller.
 			 */
-			.driver_data = "20180310", /* 2.35 */
+			.matches = {
+				DMI_MATCH(DMI_BOARD_VENDOR,
+					  "ASUSTeK COMPUTER INC."),
+				DMI_MATCH(DMI_BOARD_NAME,
+					  "ROG STRIX B550-F GAMING (WI-FI)"),
+			},
+			/* 3621 is broken, there is no known good version. */
 		},
 		{ }	/* terminate list */
 	};
@@ -1307,6 +1495,9 @@ static bool ahci_broken_lpm(struct pci_dev *pdev)
 	if (!dmi)
 		return false;
 
+	if (!dmi->driver_data)
+		return true;
+
 	dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
 	snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
 
@@ -1363,17 +1554,6 @@ static bool ahci_broken_online(struct pci_dev *pdev)
 	return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
 }
 
-static bool ahci_broken_devslp(struct pci_dev *pdev)
-{
-	/* device with broken DEVSLP but still showing SDS capability */
-	static const struct pci_device_id ids[] = {
-		{ PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
-		{}
-	};
-
-	return pci_match_id(ids, pdev);
-}
-
 #ifdef CONFIG_ATA_ACPI
 static void ahci_gtf_filter_workaround(struct ata_host *host)
 {
@@ -1471,7 +1651,6 @@ static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
 	u32 irq_stat, irq_masked;
 	unsigned int handled = 1;
 
-	VPRINTK("ENTER\n");
 	hpriv = host->private_data;
 	mmio = hpriv->mmio;
 	irq_stat = readl(mmio + HOST_IRQ_STAT);
@@ -1488,7 +1667,6 @@ static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
 		irq_stat = readl(mmio + HOST_IRQ_STAT);
 		spin_unlock(&host->lock);
 	} while (irq_stat);
-	VPRINTK("EXIT\n");
 
 	return IRQ_RETVAL(handled);
 }
@@ -1541,18 +1719,20 @@ static int ahci_get_irq_vector(struct ata_host *host, int port)
 	return pci_irq_vector(to_pci_dev(host->dev), port);
 }
 
-static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
+static void ahci_init_irq(struct pci_dev *pdev, unsigned int n_ports,
 			struct ahci_host_priv *hpriv)
 {
 	int nvec;
 
-	if (hpriv->flags & AHCI_HFLAG_NO_MSI)
-		return -ENODEV;
+	if (hpriv->flags & AHCI_HFLAG_NO_MSI) {
+		pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_INTX);
+		return;
+	}
 
 	/*
 	 * If number of MSIs is less than number of ports then Sharing Last
 	 * Message mode could be enforced. In this case assume that advantage
-	 * of multipe MSIs is negated and use single MSI mode instead.
+	 * of multiple MSIs is negated and use single MSI mode instead.
 	 */
 	if (n_ports > 1) {
 		nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
@@ -1561,7 +1741,7 @@ static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
 			if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
 				hpriv->get_irq_vector = ahci_get_irq_vector;
 				hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
-				return nvec;
+				return;
 			}
 
 			/*
@@ -1576,23 +1756,71 @@ static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
 
 	/*
 	 * If the host is not capable of supporting per-port vectors, fall
-	 * back to single MSI before finally attempting single MSI-X.
+	 * back to single MSI before finally attempting single MSI-X or
+	 * a legacy INTx.
 	 */
 	nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
 	if (nvec == 1)
-		return nvec;
-	return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
+		return;
+	pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX | PCI_IRQ_INTX);
 }
 
-static void ahci_update_initial_lpm_policy(struct ata_port *ap,
-					   struct ahci_host_priv *hpriv)
+static void ahci_mark_external_port(struct ata_port *ap)
 {
+	struct ahci_host_priv *hpriv = ap->host->private_data;
+	void __iomem *port_mmio = ahci_port_base(ap);
+	u32 tmp;
+
+	/*
+	 * Mark external ports (hotplug-capable, eSATA), unless we were asked to
+	 * ignore this feature.
+	 */
+	tmp = readl(port_mmio + PORT_CMD);
+	if (((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS)) ||
+	    (tmp & PORT_CMD_HPCP)) {
+		if (hpriv->mask_port_ext & (1U << ap->port_no)) {
+			ata_port_info(ap,
+				"Ignoring external/hotplug capability\n");
+			return;
+		}
+		ap->pflags |= ATA_PFLAG_EXTERNAL;
+	}
+}
+
+static void ahci_update_initial_lpm_policy(struct ata_port *ap)
+{
+	struct ahci_host_priv *hpriv = ap->host->private_data;
 	int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
 
+	/*
+	 * AHCI contains a known incompatibility between LPM and hot-plug
+	 * removal events, see 7.3.1 Hot Plug Removal Detection and Power
+	 * Management Interaction in AHCI 1.3.1. Therefore, do not enable
+	 * LPM if the port advertises itself as an external port.
+	 */
+	if (ap->pflags & ATA_PFLAG_EXTERNAL) {
+		ap->flags |= ATA_FLAG_NO_LPM;
+		ap->target_lpm_policy = ATA_LPM_MAX_POWER;
+		return;
+	}
+
+	/* If no Partial or no Slumber, we cannot support DIPM. */
+	if ((ap->host->flags & ATA_HOST_NO_PART) ||
+	    (ap->host->flags & ATA_HOST_NO_SSC)) {
+		ata_port_dbg(ap, "Host does not support DIPM\n");
+		ap->flags |= ATA_FLAG_NO_DIPM;
+	}
 
-	/* Ignore processing for non mobile platforms */
-	if (!(hpriv->flags & AHCI_HFLAG_IS_MOBILE))
+	/* If no LPM states are supported by the HBA, do not bother with LPM */
+	if ((ap->host->flags & ATA_HOST_NO_PART) &&
+	    (ap->host->flags & ATA_HOST_NO_SSC) &&
+	    (ap->host->flags & ATA_HOST_NO_DEVSLP)) {
+		ata_port_dbg(ap,
+			"No LPM states supported, forcing LPM max_power\n");
+		ap->flags |= ATA_FLAG_NO_LPM;
+		ap->target_lpm_policy = ATA_LPM_MAX_POWER;
 		return;
+	}
 
 	/* user modified policy via module param */
 	if (mobile_lpm_policy != -1) {
@@ -1600,15 +1828,12 @@ static void ahci_update_initial_lpm_policy(struct ata_port *ap,
 		goto update_policy;
 	}
 
-#ifdef CONFIG_ACPI
-	if (policy > ATA_LPM_MED_POWER &&
-	    (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) {
+	if (policy > ATA_LPM_MED_POWER && pm_suspend_default_s2idle()) {
 		if (hpriv->cap & HOST_CAP_PART)
 			policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
 		else if (hpriv->cap & HOST_CAP_SSC)
 			policy = ATA_LPM_MIN_POWER;
 	}
-#endif
 
 update_policy:
 	if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
@@ -1617,17 +1842,9 @@ update_policy:
 
 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
 {
-	const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev);
 	u16 tmp16;
 
-	/*
-	 * Only apply the 6-port PCS quirk for known legacy platforms.
-	 */
-	if (!id || id->vendor != PCI_VENDOR_ID_INTEL)
-		return;
-
-	/* Skip applying the quirk on Denverton and beyond */
-	if (((enum board_ids) id->driver_data) >= board_ahci_pcs7)
+	if (!(hpriv->flags & AHCI_HFLAG_INTEL_PCS_QUIRK))
 		return;
 
 	/*
@@ -1652,7 +1869,7 @@ static ssize_t remapped_nvme_show(struct device *dev,
 	struct ata_host *host = dev_get_drvdata(dev);
 	struct ahci_host_priv *hpriv = host->private_data;
 
-	return sprintf(buf, "%u\n", hpriv->remapped_nvme);
+	return sysfs_emit(buf, "%u\n", hpriv->remapped_nvme);
 }
 
 static DEVICE_ATTR_RO(remapped_nvme);
@@ -1668,8 +1885,6 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 	int n_ports, i, rc;
 	int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
 
-	VPRINTK("ENTER\n");
-
 	WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
 
 	ata_print_version_once(&pdev->dev, DRV_VERSION);
@@ -1731,7 +1946,7 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 	/* AHCI controllers often implement SFF compatible interface.
 	 * Grab all PCI BARs just in case.
 	 */
-	rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
+	rc = pcim_request_all_regions(pdev, DRV_NAME);
 	if (rc == -EBUSY)
 		pcim_pin_device(pdev);
 	if (rc)
@@ -1755,7 +1970,9 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 	if (ahci_sb600_enable_64bit(pdev))
 		hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
 
-	hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
+	hpriv->mmio = pcim_iomap(pdev, ahci_pci_bar, 0);
+	if (!hpriv->mmio)
+		return -ENOMEM;
 
 	/* detect remapped nvme devices */
 	ahci_remap_check(pdev, ahci_pci_bar, hpriv);
@@ -1764,11 +1981,12 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 				&dev_attr_remapped_nvme.attr,
 				NULL);
 
-	/* must set flag prior to save config in order to take effect */
-	if (ahci_broken_devslp(pdev))
-		hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
-
 #ifdef CONFIG_ARM64
+	if (pdev->vendor == PCI_VENDOR_ID_HUAWEI &&
+	    pdev->device == 0xa235 &&
+	    pdev->revision < 0x30)
+		hpriv->flags |= AHCI_HFLAG_NO_SXS;
+
 	if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
 		hpriv->irq_handler = ahci_thunderx_irq_handler;
 #endif
@@ -1776,12 +1994,6 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 	/* save initial config */
 	ahci_pci_save_initial_config(pdev, hpriv);
 
-	/*
-	 * If platform firmware failed to enable ports, try to enable
-	 * them here.
-	 */
-	ahci_intel_pcs_quirk(pdev, hpriv);
-
 	/* prepare host */
 	if (hpriv->cap & HOST_CAP_NCQ) {
 		pi.flags |= ATA_FLAG_NCQ;
@@ -1844,14 +2056,14 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 	n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
 
 	host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
-	if (!host)
-		return -ENOMEM;
+	if (!host) {
+		rc = -ENOMEM;
+		goto err_rm_sysfs_file;
+	}
 	host->private_data = hpriv;
 
-	if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
-		/* legacy intx interrupts */
-		pci_intx(pdev, 1);
-	}
+	ahci_init_irq(pdev, n_ports, hpriv);
+
 	hpriv->irq = pci_irq_vector(pdev, 0);
 
 	if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
@@ -1859,6 +2071,15 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 	else
 		dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
 
+	if (!(hpriv->cap & HOST_CAP_PART))
+		host->flags |= ATA_HOST_NO_PART;
+
+	if (!(hpriv->cap & HOST_CAP_SSC))
+		host->flags |= ATA_HOST_NO_SSC;
+
+	if (!(hpriv->cap2 & HOST_CAP2_SDS))
+		host->flags |= ATA_HOST_NO_DEVSLP;
+
 	if (pi.flags & ATA_FLAG_EM)
 		ahci_reset_em(host);
 
@@ -1873,7 +2094,9 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 		if (ap->flags & ATA_FLAG_EM)
 			ap->em_message_type = hpriv->em_msg_type;
 
-		ahci_update_initial_lpm_policy(ap, hpriv);
+		ahci_mark_external_port(ap);
+
+		ahci_update_initial_lpm_policy(ap);
 
 		/* disabled/not-implemented port */
 		if (!(hpriv->port_map & (1 << i)))
@@ -1887,13 +2110,13 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 	ahci_gtf_filter_workaround(host);
 
 	/* initialize adapter */
-	rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
+	rc = ahci_configure_dma_masks(pdev, hpriv);
 	if (rc)
-		return rc;
+		goto err_rm_sysfs_file;
 
-	rc = ahci_reset_controller(host);
+	rc = ahci_pci_reset_controller(host);
 	if (rc)
-		return rc;
+		goto err_rm_sysfs_file;
 
 	ahci_pci_init_controller(host);
 	ahci_pci_print_info(host);
@@ -1902,10 +2125,15 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 
 	rc = ahci_host_activate(host, &ahci_sht);
 	if (rc)
-		return rc;
+		goto err_rm_sysfs_file;
 
 	pm_runtime_put_noidle(&pdev->dev);
 	return 0;
+
+err_rm_sysfs_file:
+	sysfs_remove_file_from_group(&pdev->dev.kobj,
+				     &dev_attr_remapped_nvme.attr, NULL);
+	return rc;
 }
 
 static void ahci_shutdown_one(struct pci_dev *pdev)
diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
index d991dd46e89c..293b7fb216b5 100644
--- a/drivers/ata/ahci.h
+++ b/drivers/ata/ahci.h
@@ -24,6 +24,7 @@
 #include <linux/libata.h>
 #include <linux/phy/phy.h>
 #include <linux/regulator/consumer.h>
+#include <linux/bits.h>
 
 /* Enclosure Management Control */
 #define EM_CTRL_MSG_TYPE              0x000f0000
@@ -38,7 +39,6 @@
 
 enum {
 	AHCI_MAX_PORTS		= 32,
-	AHCI_MAX_CLKS		= 5,
 	AHCI_MAX_SG		= 168, /* hardware max is 64K */
 	AHCI_DMA_BOUNDARY	= 0xffffffff,
 	AHCI_MAX_CMDS		= 32,
@@ -54,12 +54,12 @@ enum {
 	AHCI_PORT_PRIV_FBS_DMA_SZ	= AHCI_CMD_SLOT_SZ +
 					  AHCI_CMD_TBL_AR_SZ +
 					  (AHCI_RX_FIS_SZ * 16),
-	AHCI_IRQ_ON_SG		= (1 << 31),
-	AHCI_CMD_ATAPI		= (1 << 5),
-	AHCI_CMD_WRITE		= (1 << 6),
-	AHCI_CMD_PREFETCH	= (1 << 7),
-	AHCI_CMD_RESET		= (1 << 8),
-	AHCI_CMD_CLR_BUSY	= (1 << 10),
+	AHCI_IRQ_ON_SG		= BIT(31),
+	AHCI_CMD_ATAPI		= BIT(5),
+	AHCI_CMD_WRITE		= BIT(6),
+	AHCI_CMD_PREFETCH	= BIT(7),
+	AHCI_CMD_RESET		= BIT(8),
+	AHCI_CMD_CLR_BUSY	= BIT(10),
 
 	RX_FIS_PIO_SETUP	= 0x20,	/* offset of PIO Setup FIS data */
 	RX_FIS_D2H_REG		= 0x40,	/* offset of D2H Register FIS data */
@@ -77,37 +77,37 @@ enum {
 	HOST_CAP2		= 0x24, /* host capabilities, extended */
 
 	/* HOST_CTL bits */
-	HOST_RESET		= (1 << 0),  /* reset controller; self-clear */
-	HOST_IRQ_EN		= (1 << 1),  /* global IRQ enable */
-	HOST_MRSM		= (1 << 2),  /* MSI Revert to Single Message */
-	HOST_AHCI_EN		= (1 << 31), /* AHCI enabled */
+	HOST_RESET		= BIT(0),  /* reset controller; self-clear */
+	HOST_IRQ_EN		= BIT(1),  /* global IRQ enable */
+	HOST_MRSM		= BIT(2),  /* MSI Revert to Single Message */
+	HOST_AHCI_EN		= BIT(31), /* AHCI enabled */
 
 	/* HOST_CAP bits */
-	HOST_CAP_SXS		= (1 << 5),  /* Supports External SATA */
-	HOST_CAP_EMS		= (1 << 6),  /* Enclosure Management support */
-	HOST_CAP_CCC		= (1 << 7),  /* Command Completion Coalescing */
-	HOST_CAP_PART		= (1 << 13), /* Partial state capable */
-	HOST_CAP_SSC		= (1 << 14), /* Slumber state capable */
-	HOST_CAP_PIO_MULTI	= (1 << 15), /* PIO multiple DRQ support */
-	HOST_CAP_FBS		= (1 << 16), /* FIS-based switching support */
-	HOST_CAP_PMP		= (1 << 17), /* Port Multiplier support */
-	HOST_CAP_ONLY		= (1 << 18), /* Supports AHCI mode only */
-	HOST_CAP_CLO		= (1 << 24), /* Command List Override support */
-	HOST_CAP_LED		= (1 << 25), /* Supports activity LED */
-	HOST_CAP_ALPM		= (1 << 26), /* Aggressive Link PM support */
-	HOST_CAP_SSS		= (1 << 27), /* Staggered Spin-up */
-	HOST_CAP_MPS		= (1 << 28), /* Mechanical presence switch */
-	HOST_CAP_SNTF		= (1 << 29), /* SNotification register */
-	HOST_CAP_NCQ		= (1 << 30), /* Native Command Queueing */
-	HOST_CAP_64		= (1 << 31), /* PCI DAC (64-bit DMA) support */
+	HOST_CAP_SXS		= BIT(5),  /* Supports External SATA */
+	HOST_CAP_EMS		= BIT(6),  /* Enclosure Management support */
+	HOST_CAP_CCC		= BIT(7),  /* Command Completion Coalescing */
+	HOST_CAP_PART		= BIT(13), /* Partial state capable */
+	HOST_CAP_SSC		= BIT(14), /* Slumber state capable */
+	HOST_CAP_PIO_MULTI	= BIT(15), /* PIO multiple DRQ support */
+	HOST_CAP_FBS		= BIT(16), /* FIS-based switching support */
+	HOST_CAP_PMP		= BIT(17), /* Port Multiplier support */
+	HOST_CAP_ONLY		= BIT(18), /* Supports AHCI mode only */
+	HOST_CAP_CLO		= BIT(24), /* Command List Override support */
+	HOST_CAP_LED		= BIT(25), /* Supports activity LED */
+	HOST_CAP_ALPM		= BIT(26), /* Aggressive Link PM support */
+	HOST_CAP_SSS		= BIT(27), /* Staggered Spin-up */
+	HOST_CAP_MPS		= BIT(28), /* Mechanical presence switch */
+	HOST_CAP_SNTF		= BIT(29), /* SNotification register */
+	HOST_CAP_NCQ		= BIT(30), /* Native Command Queueing */
+	HOST_CAP_64		= BIT(31), /* PCI DAC (64-bit DMA) support */
 
 	/* HOST_CAP2 bits */
-	HOST_CAP2_BOH		= (1 << 0),  /* BIOS/OS handoff supported */
-	HOST_CAP2_NVMHCI	= (1 << 1),  /* NVMHCI supported */
-	HOST_CAP2_APST		= (1 << 2),  /* Automatic partial to slumber */
-	HOST_CAP2_SDS		= (1 << 3),  /* Support device sleep */
-	HOST_CAP2_SADM		= (1 << 4),  /* Support aggressive DevSlp */
-	HOST_CAP2_DESO		= (1 << 5),  /* DevSlp from slumber only */
+	HOST_CAP2_BOH		= BIT(0),  /* BIOS/OS handoff supported */
+	HOST_CAP2_NVMHCI	= BIT(1),  /* NVMHCI supported */
+	HOST_CAP2_APST		= BIT(2),  /* Automatic partial to slumber */
+	HOST_CAP2_SDS		= BIT(3),  /* Support device sleep */
+	HOST_CAP2_SADM		= BIT(4),  /* Support aggressive DevSlp */
+	HOST_CAP2_DESO		= BIT(5),  /* DevSlp from slumber only */
 
 	/* registers for each SATA port */
 	PORT_LST_ADDR		= 0x00, /* command list DMA addr */
@@ -129,24 +129,24 @@ enum {
 	PORT_DEVSLP		= 0x44, /* device sleep */
 
 	/* PORT_IRQ_{STAT,MASK} bits */
-	PORT_IRQ_COLD_PRES	= (1 << 31), /* cold presence detect */
-	PORT_IRQ_TF_ERR		= (1 << 30), /* task file error */
-	PORT_IRQ_HBUS_ERR	= (1 << 29), /* host bus fatal error */
-	PORT_IRQ_HBUS_DATA_ERR	= (1 << 28), /* host bus data error */
-	PORT_IRQ_IF_ERR		= (1 << 27), /* interface fatal error */
-	PORT_IRQ_IF_NONFATAL	= (1 << 26), /* interface non-fatal error */
-	PORT_IRQ_OVERFLOW	= (1 << 24), /* xfer exhausted available S/G */
-	PORT_IRQ_BAD_PMP	= (1 << 23), /* incorrect port multiplier */
-
-	PORT_IRQ_PHYRDY		= (1 << 22), /* PhyRdy changed */
-	PORT_IRQ_DEV_ILCK	= (1 << 7), /* device interlock */
-	PORT_IRQ_CONNECT	= (1 << 6), /* port connect change status */
-	PORT_IRQ_SG_DONE	= (1 << 5), /* descriptor processed */
-	PORT_IRQ_UNK_FIS	= (1 << 4), /* unknown FIS rx'd */
-	PORT_IRQ_SDB_FIS	= (1 << 3), /* Set Device Bits FIS rx'd */
-	PORT_IRQ_DMAS_FIS	= (1 << 2), /* DMA Setup FIS rx'd */
-	PORT_IRQ_PIOS_FIS	= (1 << 1), /* PIO Setup FIS rx'd */
-	PORT_IRQ_D2H_REG_FIS	= (1 << 0), /* D2H Register FIS rx'd */
+	PORT_IRQ_COLD_PRES	= BIT(31), /* cold presence detect */
+	PORT_IRQ_TF_ERR		= BIT(30), /* task file error */
+	PORT_IRQ_HBUS_ERR	= BIT(29), /* host bus fatal error */
+	PORT_IRQ_HBUS_DATA_ERR	= BIT(28), /* host bus data error */
+	PORT_IRQ_IF_ERR		= BIT(27), /* interface fatal error */
+	PORT_IRQ_IF_NONFATAL	= BIT(26), /* interface non-fatal error */
+	PORT_IRQ_OVERFLOW	= BIT(24), /* xfer exhausted available S/G */
+	PORT_IRQ_BAD_PMP	= BIT(23), /* incorrect port multiplier */
+
+	PORT_IRQ_PHYRDY		= BIT(22), /* PhyRdy changed */
+	PORT_IRQ_DMPS		= BIT(7),  /* mechanical presence status */
+	PORT_IRQ_CONNECT	= BIT(6),  /* port connect change status */
+	PORT_IRQ_SG_DONE	= BIT(5),  /* descriptor processed */
+	PORT_IRQ_UNK_FIS	= BIT(4),  /* unknown FIS rx'd */
+	PORT_IRQ_SDB_FIS	= BIT(3),  /* Set Device Bits FIS rx'd */
+	PORT_IRQ_DMAS_FIS	= BIT(2),  /* DMA Setup FIS rx'd */
+	PORT_IRQ_PIOS_FIS	= BIT(1),  /* PIO Setup FIS rx'd */
+	PORT_IRQ_D2H_REG_FIS	= BIT(0),  /* D2H Register FIS rx'd */
 
 	PORT_IRQ_FREEZE		= PORT_IRQ_HBUS_ERR |
 				  PORT_IRQ_IF_ERR |
@@ -162,34 +162,40 @@ enum {
 				  PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
 
 	/* PORT_CMD bits */
-	PORT_CMD_ASP		= (1 << 27), /* Aggressive Slumber/Partial */
-	PORT_CMD_ALPE		= (1 << 26), /* Aggressive Link PM enable */
-	PORT_CMD_ATAPI		= (1 << 24), /* Device is ATAPI */
-	PORT_CMD_FBSCP		= (1 << 22), /* FBS Capable Port */
-	PORT_CMD_ESP		= (1 << 21), /* External Sata Port */
-	PORT_CMD_HPCP		= (1 << 18), /* HotPlug Capable Port */
-	PORT_CMD_PMP		= (1 << 17), /* PMP attached */
-	PORT_CMD_LIST_ON	= (1 << 15), /* cmd list DMA engine running */
-	PORT_CMD_FIS_ON		= (1 << 14), /* FIS DMA engine running */
-	PORT_CMD_FIS_RX		= (1 << 4), /* Enable FIS receive DMA engine */
-	PORT_CMD_CLO		= (1 << 3), /* Command list override */
-	PORT_CMD_POWER_ON	= (1 << 2), /* Power up device */
-	PORT_CMD_SPIN_UP	= (1 << 1), /* Spin up device */
-	PORT_CMD_START		= (1 << 0), /* Enable port DMA engine */
-
-	PORT_CMD_ICC_MASK	= (0xf << 28), /* i/f ICC state mask */
-	PORT_CMD_ICC_ACTIVE	= (0x1 << 28), /* Put i/f in active state */
-	PORT_CMD_ICC_PARTIAL	= (0x2 << 28), /* Put i/f in partial state */
-	PORT_CMD_ICC_SLUMBER	= (0x6 << 28), /* Put i/f in slumber state */
+	PORT_CMD_ASP		= BIT(27), /* Aggressive Slumber/Partial */
+	PORT_CMD_ALPE		= BIT(26), /* Aggressive Link PM enable */
+	PORT_CMD_ATAPI		= BIT(24), /* Device is ATAPI */
+	PORT_CMD_FBSCP		= BIT(22), /* FBS Capable Port */
+	PORT_CMD_ESP		= BIT(21), /* External Sata Port */
+	PORT_CMD_CPD		= BIT(20), /* Cold Presence Detection */
+	PORT_CMD_MPSP		= BIT(19), /* Mechanical Presence Switch */
+	PORT_CMD_HPCP		= BIT(18), /* HotPlug Capable Port */
+	PORT_CMD_PMP		= BIT(17), /* PMP attached */
+	PORT_CMD_LIST_ON	= BIT(15), /* cmd list DMA engine running */
+	PORT_CMD_FIS_ON		= BIT(14), /* FIS DMA engine running */
+	PORT_CMD_FIS_RX		= BIT(4),  /* Enable FIS receive DMA engine */
+	PORT_CMD_CLO		= BIT(3),  /* Command list override */
+	PORT_CMD_POWER_ON	= BIT(2),  /* Power up device */
+	PORT_CMD_SPIN_UP	= BIT(1),  /* Spin up device */
+	PORT_CMD_START		= BIT(0),  /* Enable port DMA engine */
+
+	PORT_CMD_ICC_MASK	= (0xfu << 28), /* i/f ICC state mask */
+	PORT_CMD_ICC_ACTIVE	= (0x1u << 28), /* Put i/f in active state */
+	PORT_CMD_ICC_PARTIAL	= (0x2u << 28), /* Put i/f in partial state */
+	PORT_CMD_ICC_SLUMBER	= (0x6u << 28), /* Put i/f in slumber state */
+
+	/* PORT_CMD capabilities mask */
+	PORT_CMD_CAP		= PORT_CMD_HPCP | PORT_CMD_MPSP |
+				  PORT_CMD_CPD | PORT_CMD_ESP | PORT_CMD_FBSCP,
 
 	/* PORT_FBS bits */
 	PORT_FBS_DWE_OFFSET	= 16, /* FBS device with error offset */
 	PORT_FBS_ADO_OFFSET	= 12, /* FBS active dev optimization offset */
 	PORT_FBS_DEV_OFFSET	= 8,  /* FBS device to issue offset */
 	PORT_FBS_DEV_MASK	= (0xf << PORT_FBS_DEV_OFFSET),  /* FBS.DEV */
-	PORT_FBS_SDE		= (1 << 2), /* FBS single device error */
-	PORT_FBS_DEC		= (1 << 1), /* FBS device error clear */
-	PORT_FBS_EN		= (1 << 0), /* Enable FBS */
+	PORT_FBS_SDE		= BIT(2), /* FBS single device error */
+	PORT_FBS_DEC		= BIT(1), /* FBS device error clear */
+	PORT_FBS_EN		= BIT(0), /* Enable FBS */
 
 	/* PORT_DEVSLP bits */
 	PORT_DEVSLP_DM_OFFSET	= 25,             /* DITO multiplier offset */
@@ -197,49 +203,50 @@ enum {
 	PORT_DEVSLP_DITO_OFFSET	= 15,             /* DITO offset */
 	PORT_DEVSLP_MDAT_OFFSET	= 10,             /* Minimum assertion time */
 	PORT_DEVSLP_DETO_OFFSET	= 2,              /* DevSlp exit timeout */
-	PORT_DEVSLP_DSP		= (1 << 1),       /* DevSlp present */
-	PORT_DEVSLP_ADSE	= (1 << 0),       /* Aggressive DevSlp enable */
+	PORT_DEVSLP_DSP		= BIT(1),         /* DevSlp present */
+	PORT_DEVSLP_ADSE	= BIT(0),         /* Aggressive DevSlp enable */
 
 	/* hpriv->flags bits */
 
 #define AHCI_HFLAGS(flags)		.private_data	= (void *)(flags)
 
-	AHCI_HFLAG_NO_NCQ		= (1 << 0),
-	AHCI_HFLAG_IGN_IRQ_IF_ERR	= (1 << 1), /* ignore IRQ_IF_ERR */
-	AHCI_HFLAG_IGN_SERR_INTERNAL	= (1 << 2), /* ignore SERR_INTERNAL */
-	AHCI_HFLAG_32BIT_ONLY		= (1 << 3), /* force 32bit */
-	AHCI_HFLAG_MV_PATA		= (1 << 4), /* PATA port */
-	AHCI_HFLAG_NO_MSI		= (1 << 5), /* no PCI MSI */
-	AHCI_HFLAG_NO_PMP		= (1 << 6), /* no PMP */
-	AHCI_HFLAG_SECT255		= (1 << 8), /* max 255 sectors */
-	AHCI_HFLAG_YES_NCQ		= (1 << 9), /* force NCQ cap on */
-	AHCI_HFLAG_NO_SUSPEND		= (1 << 10), /* don't suspend */
-	AHCI_HFLAG_SRST_TOUT_IS_OFFLINE	= (1 << 11), /* treat SRST timeout as
-							link offline */
-	AHCI_HFLAG_NO_SNTF		= (1 << 12), /* no sntf */
-	AHCI_HFLAG_NO_FPDMA_AA		= (1 << 13), /* no FPDMA AA */
-	AHCI_HFLAG_YES_FBS		= (1 << 14), /* force FBS cap on */
-	AHCI_HFLAG_DELAY_ENGINE		= (1 << 15), /* do not start engine on
-						        port start (wait until
-						        error-handling stage) */
-	AHCI_HFLAG_NO_DEVSLP		= (1 << 17), /* no device sleep */
-	AHCI_HFLAG_NO_FBS		= (1 << 18), /* no FBS */
+	AHCI_HFLAG_NO_NCQ		= BIT(0),
+	AHCI_HFLAG_IGN_IRQ_IF_ERR	= BIT(1), /* ignore IRQ_IF_ERR */
+	AHCI_HFLAG_IGN_SERR_INTERNAL	= BIT(2), /* ignore SERR_INTERNAL */
+	AHCI_HFLAG_32BIT_ONLY		= BIT(3), /* force 32bit */
+	AHCI_HFLAG_MV_PATA		= BIT(4), /* PATA port */
+	AHCI_HFLAG_NO_MSI		= BIT(5), /* no PCI MSI */
+	AHCI_HFLAG_NO_PMP		= BIT(6), /* no PMP */
+	AHCI_HFLAG_SECT255		= BIT(8), /* max 255 sectors */
+	AHCI_HFLAG_YES_NCQ		= BIT(9), /* force NCQ cap on */
+	AHCI_HFLAG_NO_SUSPEND		= BIT(10), /* don't suspend */
+	AHCI_HFLAG_SRST_TOUT_IS_OFFLINE	= BIT(11), /* treat SRST timeout as
+						      link offline */
+	AHCI_HFLAG_NO_SNTF		= BIT(12), /* no sntf */
+	AHCI_HFLAG_NO_FPDMA_AA		= BIT(13), /* no FPDMA AA */
+	AHCI_HFLAG_YES_FBS		= BIT(14), /* force FBS cap on */
+	AHCI_HFLAG_DELAY_ENGINE		= BIT(15), /* do not start engine on
+						      port start (wait until
+						      error-handling stage) */
+	AHCI_HFLAG_NO_DEVSLP		= BIT(17), /* no device sleep */
+	AHCI_HFLAG_NO_FBS		= BIT(18), /* no FBS */
 
 #ifdef CONFIG_PCI_MSI
-	AHCI_HFLAG_MULTI_MSI		= (1 << 20), /* per-port MSI(-X) */
+	AHCI_HFLAG_MULTI_MSI		= BIT(20), /* per-port MSI(-X) */
 #else
 	/* compile out MSI infrastructure */
 	AHCI_HFLAG_MULTI_MSI		= 0,
 #endif
-	AHCI_HFLAG_WAKE_BEFORE_STOP	= (1 << 22), /* wake before DMA stop */
-	AHCI_HFLAG_YES_ALPM		= (1 << 23), /* force ALPM cap on */
-	AHCI_HFLAG_NO_WRITE_TO_RO	= (1 << 24), /* don't write to read
-							only registers */
-	AHCI_HFLAG_IS_MOBILE		= (1 << 25), /* mobile chipset, use
-							SATA_MOBILE_LPM_POLICY
-							as default lpm_policy */
-	AHCI_HFLAG_SUSPEND_PHYS		= (1 << 26), /* handle PHYs during
-							suspend/resume */
+	AHCI_HFLAG_WAKE_BEFORE_STOP	= BIT(22), /* wake before DMA stop */
+	AHCI_HFLAG_YES_ALPM		= BIT(23), /* force ALPM cap on */
+	AHCI_HFLAG_NO_WRITE_TO_RO	= BIT(24), /* don't write to read
+						      only registers */
+	AHCI_HFLAG_SUSPEND_PHYS		= BIT(25), /* handle PHYs during
+						      suspend/resume */
+	AHCI_HFLAG_NO_SXS		= BIT(26), /* SXS not supported */
+	AHCI_HFLAG_43BIT_ONLY		= BIT(27), /* 43bit DMA addr limit */
+	AHCI_HFLAG_INTEL_PCS_QUIRK	= BIT(28), /* apply Intel PCS quirk */
+	AHCI_HFLAG_ATAPI_DMA_QUIRK	= BIT(29), /* force ATAPI to use DMA */
 
 	/* ap->flags bits */
 
@@ -251,26 +258,26 @@ enum {
 	PCS_7				= 0x94, /* 7+ port PCS (Denverton) */
 
 	/* em constants */
-	EM_MAX_SLOTS			= 8,
+	EM_MAX_SLOTS			= SATA_PMP_MAX_PORTS,
 	EM_MAX_RETRY			= 5,
 
 	/* em_ctl bits */
-	EM_CTL_RST		= (1 << 9), /* Reset */
-	EM_CTL_TM		= (1 << 8), /* Transmit Message */
-	EM_CTL_MR		= (1 << 0), /* Message Received */
-	EM_CTL_ALHD		= (1 << 26), /* Activity LED */
-	EM_CTL_XMT		= (1 << 25), /* Transmit Only */
-	EM_CTL_SMB		= (1 << 24), /* Single Message Buffer */
-	EM_CTL_SGPIO		= (1 << 19), /* SGPIO messages supported */
-	EM_CTL_SES		= (1 << 18), /* SES-2 messages supported */
-	EM_CTL_SAFTE		= (1 << 17), /* SAF-TE messages supported */
-	EM_CTL_LED		= (1 << 16), /* LED messages supported */
+	EM_CTL_RST		= BIT(9), /* Reset */
+	EM_CTL_TM		= BIT(8), /* Transmit Message */
+	EM_CTL_MR		= BIT(0), /* Message Received */
+	EM_CTL_ALHD		= BIT(26), /* Activity LED */
+	EM_CTL_XMT		= BIT(25), /* Transmit Only */
+	EM_CTL_SMB		= BIT(24), /* Single Message Buffer */
+	EM_CTL_SGPIO		= BIT(19), /* SGPIO messages supported */
+	EM_CTL_SES		= BIT(18), /* SES-2 messages supported */
+	EM_CTL_SAFTE		= BIT(17), /* SAF-TE messages supported */
+	EM_CTL_LED		= BIT(16), /* LED messages supported */
 
 	/* em message type */
-	EM_MSG_TYPE_LED		= (1 << 0), /* LED */
-	EM_MSG_TYPE_SAFTE	= (1 << 1), /* SAF-TE */
-	EM_MSG_TYPE_SES2	= (1 << 2), /* SES-2 */
-	EM_MSG_TYPE_SGPIO	= (1 << 3), /* SGPIO */
+	EM_MSG_TYPE_LED		= BIT(0), /* LED */
+	EM_MSG_TYPE_SAFTE	= BIT(1), /* SAF-TE */
+	EM_MSG_TYPE_SES2	= BIT(2), /* SES-2 */
+	EM_MSG_TYPE_SGPIO	= BIT(3), /* SGPIO */
 };
 
 struct ahci_cmd_hdr {
@@ -322,8 +329,8 @@ struct ahci_port_priv {
 struct ahci_host_priv {
 	/* Input fields */
 	unsigned int		flags;		/* AHCI_HFLAG_* */
-	u32			force_port_map;	/* force port map */
-	u32			mask_port_map;	/* mask out particular bits */
+	u32			mask_port_map;	/* Mask of valid ports */
+	u32			mask_port_ext;	/* Mask of ports ext capability */
 
 	void __iomem *		mmio;		/* bus-independent mem map */
 	u32			cap;		/* cap to use */
@@ -333,12 +340,15 @@ struct ahci_host_priv {
 	u32			saved_cap;	/* saved initial cap */
 	u32			saved_cap2;	/* saved initial cap2 */
 	u32			saved_port_map;	/* saved initial port_map */
+	u32			saved_port_cap[AHCI_MAX_PORTS]; /* saved port_cap */
 	u32 			em_loc; /* enclosure management location */
 	u32			em_buf_sz;	/* EM buffer size in byte */
 	u32			em_msg_type;	/* EM message type */
 	u32			remapped_nvme;	/* NVMe remapped device count */
 	bool			got_runtime_pm; /* Did we do pm_runtime_get? */
-	struct clk		*clks[AHCI_MAX_CLKS]; /* Optional */
+	unsigned int		n_clks;
+	struct clk_bulk_data	*clks;		/* Optional */
+	unsigned int		f_rsts;
 	struct reset_control	*rsts;		/* Optional */
 	struct regulator	**target_pwrs;	/* Optional */
 	struct regulator	*ahci_regulator;/* Optional */
@@ -371,22 +381,40 @@ struct ahci_host_priv {
 						  int port);
 };
 
+/*
+ * Return true if a port should be ignored because it is excluded from
+ * the host port map.
+ */
+static inline bool ahci_ignore_port(struct ahci_host_priv *hpriv,
+				    unsigned int portid)
+{
+	if (portid >= hpriv->nports)
+		return true;
+	/* mask_port_map not set means that all ports are available */
+	if (!hpriv->mask_port_map)
+		return false;
+	return !(hpriv->mask_port_map & (1 << portid));
+}
+
 extern int ahci_ignore_sss;
 
-extern struct device_attribute *ahci_shost_attrs[];
-extern struct device_attribute *ahci_sdev_attrs[];
+extern const struct attribute_group *ahci_shost_groups[];
+extern const struct attribute_group *ahci_sdev_groups[];
 
 /*
  * This must be instantiated by the edge drivers.  Read the comments
  * for ATA_BASE_SHT
  */
 #define AHCI_SHT(drv_name)						\
-	ATA_NCQ_SHT(drv_name),						\
+	__ATA_BASE_SHT(drv_name),					\
 	.can_queue		= AHCI_MAX_CMDS,			\
 	.sg_tablesize		= AHCI_MAX_SG,				\
 	.dma_boundary		= AHCI_DMA_BOUNDARY,			\
-	.shost_attrs		= ahci_shost_attrs,			\
-	.sdev_attrs		= ahci_sdev_attrs
+	.shost_groups		= ahci_shost_groups,			\
+	.sdev_groups		= ahci_sdev_groups,			\
+	.change_queue_depth     = ata_scsi_change_queue_depth,		\
+	.tag_alloc_policy_rr	= true,					\
+	.sdev_configure		= ata_scsi_sdev_configure
 
 extern struct ata_port_operations ahci_ops;
 extern struct ata_port_operations ahci_platform_ops;
@@ -418,14 +446,13 @@ void ahci_set_em_messages(struct ahci_host_priv *hpriv,
 			  struct ata_port_info *pi);
 int ahci_reset_em(struct ata_host *host);
 void ahci_print_info(struct ata_host *host, const char *scc_s);
-int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht);
+int ahci_host_activate(struct ata_host *host, const struct scsi_host_template *sht);
 void ahci_error_handler(struct ata_port *ap);
 u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked);
 
-static inline void __iomem *__ahci_port_base(struct ata_host *host,
+static inline void __iomem *__ahci_port_base(struct ahci_host_priv *hpriv,
 					     unsigned int port_no)
 {
-	struct ahci_host_priv *hpriv = host->private_data;
 	void __iomem *mmio = hpriv->mmio;
 
 	return mmio + 0x100 + (port_no * 0x80);
@@ -433,7 +460,9 @@ static inline void __iomem *__ahci_port_base(struct ata_host *host,
 
 static inline void __iomem *ahci_port_base(struct ata_port *ap)
 {
-	return __ahci_port_base(ap->host, ap->port_no);
+	struct ahci_host_priv *hpriv = ap->host->private_data;
+
+	return __ahci_port_base(hpriv, ap->port_no);
 }
 
 static inline int ahci_nr_ports(u32 cap)
diff --git a/drivers/ata/ahci_brcm.c b/drivers/ata/ahci_brcm.c
index 6853dbb4131d..29be74fedcf0 100644
--- a/drivers/ata/ahci_brcm.c
+++ b/drivers/ata/ahci_brcm.c
@@ -86,7 +86,8 @@ struct brcm_ahci_priv {
 	u32 port_mask;
 	u32 quirks;
 	enum brcm_ahci_version version;
-	struct reset_control *rcdev;
+	struct reset_control *rcdev_rescal;
+	struct reset_control *rcdev_ahci;
 };
 
 static inline u32 brcm_sata_readreg(void __iomem *addr)
@@ -245,7 +246,7 @@ static void brcm_sata_init(struct brcm_ahci_priv *priv)
 }
 
 static unsigned int brcm_ahci_read_id(struct ata_device *dev,
-				      struct ata_taskfile *tf, u16 *id)
+				      struct ata_taskfile *tf, __le16 *id)
 {
 	struct ata_port *ap = dev->link->ap;
 	struct ata_host *host = ap->host;
@@ -287,6 +288,9 @@ static unsigned int brcm_ahci_read_id(struct ata_device *dev,
 
 	/* Re-initialize and calibrate the PHY */
 	for (i = 0; i < hpriv->nports; i++) {
+		if (ahci_ignore_port(hpriv, i))
+			continue;
+
 		rc = phy_init(hpriv->phys[i]);
 		if (rc)
 			goto disable_phys;
@@ -332,7 +336,7 @@ static struct ata_port_operations ahci_brcm_platform_ops = {
 
 static const struct ata_port_info ahci_brcm_port_info = {
 	.flags		= AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
-	.link_flags	= ATA_LFLAG_NO_DB_DELAY,
+	.link_flags	= ATA_LFLAG_NO_DEBOUNCE_DELAY,
 	.pio_mask	= ATA_PIO4,
 	.udma_mask	= ATA_UDMA6,
 	.port_ops	= &ahci_brcm_platform_ops,
@@ -352,8 +356,8 @@ static int brcm_ahci_suspend(struct device *dev)
 	else
 		ret = 0;
 
-	if (priv->version != BRCM_SATA_BCM7216)
-		reset_control_assert(priv->rcdev);
+	reset_control_assert(priv->rcdev_ahci);
+	reset_control_rearm(priv->rcdev_rescal);
 
 	return ret;
 }
@@ -365,10 +369,10 @@ static int __maybe_unused brcm_ahci_resume(struct device *dev)
 	struct brcm_ahci_priv *priv = hpriv->plat_data;
 	int ret = 0;
 
-	if (priv->version == BRCM_SATA_BCM7216)
-		ret = reset_control_reset(priv->rcdev);
-	else
-		ret = reset_control_deassert(priv->rcdev);
+	ret = reset_control_deassert(priv->rcdev_ahci);
+	if (ret)
+		return ret;
+	ret = reset_control_reset(priv->rcdev_rescal);
 	if (ret)
 		return ret;
 
@@ -377,6 +381,10 @@ static int __maybe_unused brcm_ahci_resume(struct device *dev)
 	if (ret)
 		return ret;
 
+	ret = ahci_platform_enable_regulators(hpriv);
+	if (ret)
+		goto out_disable_clks;
+
 	brcm_sata_init(priv);
 	brcm_sata_phys_enable(priv);
 	brcm_sata_alpm_init(hpriv);
@@ -406,11 +414,13 @@ out_disable_platform_phys:
 	ahci_platform_disable_phys(hpriv);
 out_disable_phys:
 	brcm_sata_phys_disable(priv);
+	ahci_platform_disable_regulators(hpriv);
+out_disable_clks:
 	ahci_platform_disable_clks(hpriv);
 	return ret;
 }
 
-static struct scsi_host_template ahci_platform_sht = {
+static const struct scsi_host_template ahci_platform_sht = {
 	AHCI_SHT(DRV_NAME),
 };
 
@@ -420,7 +430,7 @@ static const struct of_device_id ahci_of_match[] = {
 	{.compatible = "brcm,bcm63138-ahci", .data = (void *)BRCM_SATA_BCM7445},
 	{.compatible = "brcm,bcm-nsp-ahci", .data = (void *)BRCM_SATA_NSP},
 	{.compatible = "brcm,bcm7216-ahci", .data = (void *)BRCM_SATA_BCM7216},
-	{},
+	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, ahci_of_match);
 
@@ -428,10 +438,8 @@ static int brcm_ahci_probe(struct platform_device *pdev)
 {
 	const struct of_device_id *of_id;
 	struct device *dev = &pdev->dev;
-	const char *reset_name = NULL;
 	struct brcm_ahci_priv *priv;
 	struct ahci_host_priv *hpriv;
-	struct resource *res;
 	int ret;
 
 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
@@ -442,23 +450,22 @@ static int brcm_ahci_probe(struct platform_device *pdev)
 	if (!of_id)
 		return -ENODEV;
 
-	priv->version = (enum brcm_ahci_version)of_id->data;
+	priv->version = (unsigned long)of_id->data;
 	priv->dev = dev;
 
-	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "top-ctrl");
-	priv->top_ctrl = devm_ioremap_resource(dev, res);
+	priv->top_ctrl = devm_platform_ioremap_resource_byname(pdev, "top-ctrl");
 	if (IS_ERR(priv->top_ctrl))
 		return PTR_ERR(priv->top_ctrl);
 
-	/* Reset is optional depending on platform and named differently */
-	if (priv->version == BRCM_SATA_BCM7216)
-		reset_name = "rescal";
-	else
-		reset_name = "ahci";
-
-	priv->rcdev = devm_reset_control_get_optional(&pdev->dev, reset_name);
-	if (IS_ERR(priv->rcdev))
-		return PTR_ERR(priv->rcdev);
+	if (priv->version == BRCM_SATA_BCM7216) {
+		priv->rcdev_rescal = devm_reset_control_get_optional_shared(
+			&pdev->dev, "rescal");
+		if (IS_ERR(priv->rcdev_rescal))
+			return PTR_ERR(priv->rcdev_rescal);
+	}
+	priv->rcdev_ahci = devm_reset_control_get_optional(&pdev->dev, "ahci");
+	if (IS_ERR(priv->rcdev_ahci))
+		return PTR_ERR(priv->rcdev_ahci);
 
 	hpriv = ahci_platform_get_resources(pdev, 0);
 	if (IS_ERR(hpriv))
@@ -470,7 +477,7 @@ static int brcm_ahci_probe(struct platform_device *pdev)
 	switch (priv->version) {
 	case BRCM_SATA_BCM7425:
 		hpriv->flags |= AHCI_HFLAG_DELAY_ENGINE;
-		/* fall through */
+		fallthrough;
 	case BRCM_SATA_NSP:
 		hpriv->flags |= AHCI_HFLAG_NO_NCQ;
 		priv->quirks |= BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE;
@@ -479,10 +486,10 @@ static int brcm_ahci_probe(struct platform_device *pdev)
 		break;
 	}
 
-	if (priv->version == BRCM_SATA_BCM7216)
-		ret = reset_control_reset(priv->rcdev);
-	else
-		ret = reset_control_deassert(priv->rcdev);
+	ret = reset_control_reset(priv->rcdev_rescal);
+	if (ret)
+		return ret;
+	ret = reset_control_deassert(priv->rcdev_ahci);
 	if (ret)
 		return ret;
 
@@ -490,6 +497,10 @@ static int brcm_ahci_probe(struct platform_device *pdev)
 	if (ret)
 		goto out_reset;
 
+	ret = ahci_platform_enable_regulators(hpriv);
+	if (ret)
+		goto out_disable_clks;
+
 	/* Must be first so as to configure endianness including that
 	 * of the standard AHCI register space.
 	 */
@@ -499,7 +510,7 @@ static int brcm_ahci_probe(struct platform_device *pdev)
 	priv->port_mask = brcm_ahci_get_portmask(hpriv, priv);
 	if (!priv->port_mask) {
 		ret = -ENODEV;
-		goto out_disable_clks;
+		goto out_disable_regulators;
 	}
 
 	/* Must be done before ahci_platform_enable_phys() */
@@ -524,28 +535,25 @@ out_disable_platform_phys:
 	ahci_platform_disable_phys(hpriv);
 out_disable_phys:
 	brcm_sata_phys_disable(priv);
+out_disable_regulators:
+	ahci_platform_disable_regulators(hpriv);
 out_disable_clks:
 	ahci_platform_disable_clks(hpriv);
 out_reset:
-	if (priv->version != BRCM_SATA_BCM7216)
-		reset_control_assert(priv->rcdev);
+	reset_control_assert(priv->rcdev_ahci);
+	reset_control_rearm(priv->rcdev_rescal);
 	return ret;
 }
 
-static int brcm_ahci_remove(struct platform_device *pdev)
+static void brcm_ahci_remove(struct platform_device *pdev)
 {
 	struct ata_host *host = dev_get_drvdata(&pdev->dev);
 	struct ahci_host_priv *hpriv = host->private_data;
 	struct brcm_ahci_priv *priv = hpriv->plat_data;
-	int ret;
 
 	brcm_sata_phys_disable(priv);
 
-	ret = ata_platform_remove_one(pdev);
-	if (ret)
-		return ret;
-
-	return 0;
+	ata_platform_remove_one(pdev);
 }
 
 static void brcm_ahci_shutdown(struct platform_device *pdev)
diff --git a/drivers/ata/ahci_ceva.c b/drivers/ata/ahci_ceva.c
index b10fd4c8c853..2d6a08c23d6a 100644
--- a/drivers/ata/ahci_ceva.c
+++ b/drivers/ata/ahci_ceva.c
@@ -10,8 +10,9 @@
 #include <linux/kernel.h>
 #include <linux/libata.h>
 #include <linux/module.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
 #include <linux/platform_device.h>
+#include <linux/reset.h>
 #include "ahci.h"
 
 /* Vendor Specific Register Offsets */
@@ -90,7 +91,7 @@ struct ceva_ahci_priv {
 };
 
 static unsigned int ceva_ahci_read_id(struct ata_device *dev,
-					struct ata_taskfile *tf, u16 *id)
+				      struct ata_taskfile *tf, __le16 *id)
 {
 	u32 err_mask;
 
@@ -183,10 +184,70 @@ static void ahci_ceva_setup(struct ahci_host_priv *hpriv)
 	}
 }
 
-static struct scsi_host_template ahci_platform_sht = {
+static const struct scsi_host_template ahci_platform_sht = {
 	AHCI_SHT(DRV_NAME),
 };
 
+static int ceva_ahci_platform_enable_resources(struct ahci_host_priv *hpriv)
+{
+	int rc, i;
+
+	rc = ahci_platform_enable_regulators(hpriv);
+	if (rc)
+		return rc;
+
+	rc = ahci_platform_enable_clks(hpriv);
+	if (rc)
+		goto disable_regulator;
+
+	/* Assert the controller reset */
+	rc = ahci_platform_assert_rsts(hpriv);
+	if (rc)
+		goto disable_clks;
+
+	for (i = 0; i < hpriv->nports; i++) {
+		if (ahci_ignore_port(hpriv, i))
+			continue;
+
+		rc = phy_init(hpriv->phys[i]);
+		if (rc)
+			goto disable_rsts;
+	}
+
+	/* De-assert the controller reset */
+	ahci_platform_deassert_rsts(hpriv);
+
+	for (i = 0; i < hpriv->nports; i++) {
+		if (ahci_ignore_port(hpriv, i))
+			continue;
+
+		rc = phy_power_on(hpriv->phys[i]);
+		if (rc) {
+			phy_exit(hpriv->phys[i]);
+			goto disable_phys;
+		}
+	}
+
+	return 0;
+
+disable_rsts:
+	ahci_platform_deassert_rsts(hpriv);
+
+disable_phys:
+	while (--i >= 0) {
+		phy_power_off(hpriv->phys[i]);
+		phy_exit(hpriv->phys[i]);
+	}
+
+disable_clks:
+	ahci_platform_disable_clks(hpriv);
+
+disable_regulator:
+	ahci_platform_disable_regulators(hpriv);
+
+	return rc;
+}
+
 static int ceva_ahci_probe(struct platform_device *pdev)
 {
 	struct device_node *np = pdev->dev.of_node;
@@ -201,12 +262,17 @@ static int ceva_ahci_probe(struct platform_device *pdev)
 		return -ENOMEM;
 
 	cevapriv->ahci_pdev = pdev;
-
 	hpriv = ahci_platform_get_resources(pdev, 0);
 	if (IS_ERR(hpriv))
 		return PTR_ERR(hpriv);
 
-	rc = ahci_platform_enable_resources(hpriv);
+	hpriv->rsts = devm_reset_control_get_optional_exclusive(&pdev->dev,
+								NULL);
+	if (IS_ERR(hpriv->rsts))
+		return dev_err_probe(&pdev->dev, PTR_ERR(hpriv->rsts),
+				     "failed to get reset\n");
+
+	rc = ceva_ahci_platform_enable_resources(hpriv);
 	if (rc)
 		return rc;
 
@@ -217,52 +283,60 @@ static int ceva_ahci_probe(struct platform_device *pdev)
 	if (of_property_read_u8_array(np, "ceva,p0-cominit-params",
 					(u8 *)&cevapriv->pp2c[0], 4) < 0) {
 		dev_warn(dev, "ceva,p0-cominit-params property not defined\n");
-		return -EINVAL;
+		rc = -EINVAL;
+		goto disable_resources;
 	}
 
 	if (of_property_read_u8_array(np, "ceva,p1-cominit-params",
 					(u8 *)&cevapriv->pp2c[1], 4) < 0) {
 		dev_warn(dev, "ceva,p1-cominit-params property not defined\n");
-		return -EINVAL;
+		rc = -EINVAL;
+		goto disable_resources;
 	}
 
 	/* Read OOB timing value for COMWAKE from device-tree*/
 	if (of_property_read_u8_array(np, "ceva,p0-comwake-params",
 					(u8 *)&cevapriv->pp3c[0], 4) < 0) {
 		dev_warn(dev, "ceva,p0-comwake-params property not defined\n");
-		return -EINVAL;
+		rc = -EINVAL;
+		goto disable_resources;
 	}
 
 	if (of_property_read_u8_array(np, "ceva,p1-comwake-params",
 					(u8 *)&cevapriv->pp3c[1], 4) < 0) {
 		dev_warn(dev, "ceva,p1-comwake-params property not defined\n");
-		return -EINVAL;
+		rc = -EINVAL;
+		goto disable_resources;
 	}
 
 	/* Read phy BURST timing value from device-tree */
 	if (of_property_read_u8_array(np, "ceva,p0-burst-params",
 					(u8 *)&cevapriv->pp4c[0], 4) < 0) {
 		dev_warn(dev, "ceva,p0-burst-params property not defined\n");
-		return -EINVAL;
+		rc = -EINVAL;
+		goto disable_resources;
 	}
 
 	if (of_property_read_u8_array(np, "ceva,p1-burst-params",
 					(u8 *)&cevapriv->pp4c[1], 4) < 0) {
 		dev_warn(dev, "ceva,p1-burst-params property not defined\n");
-		return -EINVAL;
+		rc = -EINVAL;
+		goto disable_resources;
 	}
 
 	/* Read phy RETRY interval timing value from device-tree */
 	if (of_property_read_u16_array(np, "ceva,p0-retry-params",
 					(u16 *)&cevapriv->pp5c[0], 2) < 0) {
 		dev_warn(dev, "ceva,p0-retry-params property not defined\n");
-		return -EINVAL;
+		rc = -EINVAL;
+		goto disable_resources;
 	}
 
 	if (of_property_read_u16_array(np, "ceva,p1-retry-params",
 					(u16 *)&cevapriv->pp5c[1], 2) < 0) {
 		dev_warn(dev, "ceva,p1-retry-params property not defined\n");
-		return -EINVAL;
+		rc = -EINVAL;
+		goto disable_resources;
 	}
 
 	/*
@@ -300,7 +374,7 @@ static int __maybe_unused ceva_ahci_resume(struct device *dev)
 	struct ahci_host_priv *hpriv = host->private_data;
 	int rc;
 
-	rc = ahci_platform_enable_resources(hpriv);
+	rc = ceva_ahci_platform_enable_resources(hpriv);
 	if (rc)
 		return rc;
 
@@ -328,7 +402,7 @@ static SIMPLE_DEV_PM_OPS(ahci_ceva_pm_ops, ceva_ahci_suspend, ceva_ahci_resume);
 
 static const struct of_device_id ceva_ahci_of_match[] = {
 	{ .compatible = "ceva,ahci-1v84" },
-	{},
+	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, ceva_ahci_of_match);
 
diff --git a/drivers/ata/ahci_da850.c b/drivers/ata/ahci_da850.c
index 0e8276600712..f97566c420f8 100644
--- a/drivers/ata/ahci_da850.c
+++ b/drivers/ata/ahci_da850.c
@@ -137,13 +137,13 @@ static int ahci_da850_hardreset(struct ata_link *link,
 
 static struct ata_port_operations ahci_da850_port_ops = {
 	.inherits = &ahci_platform_ops,
-	.softreset = ahci_da850_softreset,
+	.reset.softreset = ahci_da850_softreset,
 	/*
 	 * No need to override .pmp_softreset - it's only used for actual
 	 * PMP-enabled ports.
 	 */
-	.hardreset = ahci_da850_hardreset,
-	.pmp_hardreset = ahci_da850_hardreset,
+	.reset.hardreset = ahci_da850_hardreset,
+	.pmp_reset.hardreset = ahci_da850_hardreset,
 };
 
 static const struct ata_port_info ahci_da850_port_info = {
@@ -153,7 +153,7 @@ static const struct ata_port_info ahci_da850_port_info = {
 	.port_ops	= &ahci_da850_port_ops,
 };
 
-static struct scsi_host_template ahci_platform_sht = {
+static const struct scsi_host_template ahci_platform_sht = {
 	AHCI_SHT(DRV_NAME),
 };
 
@@ -163,7 +163,6 @@ static int ahci_da850_probe(struct platform_device *pdev)
 	struct ahci_host_priv *hpriv;
 	void __iomem *pwrdn_reg;
 	struct resource *res;
-	struct clk *clk;
 	u32 mpy;
 	int rc;
 
@@ -172,36 +171,28 @@ static int ahci_da850_probe(struct platform_device *pdev)
 		return PTR_ERR(hpriv);
 
 	/*
-	 * Internally ahci_platform_get_resources() calls clk_get(dev, NULL)
-	 * when trying to obtain the functional clock. This SATA controller
-	 * uses two clocks for which we specify two connection ids. If we don't
-	 * have the functional clock at this point - call clk_get() again with
-	 * con_id = "fck".
+	 * Internally ahci_platform_get_resources() calls the bulk clocks
+	 * get method or falls back to using a single clk_get_optional().
+	 * This AHCI SATA controller uses two clocks: functional clock
+	 * with "fck" connection id and external reference clock with
+	 * "refclk" id. If we haven't got all of them re-try the clocks
+	 * getting procedure with the explicitly specified ids.
 	 */
-	if (!hpriv->clks[0]) {
-		clk = clk_get(dev, "fck");
-		if (IS_ERR(clk))
-			return PTR_ERR(clk);
-
-		hpriv->clks[0] = clk;
-	}
-
-	/*
-	 * The second clock used by ahci-da850 is the external REFCLK. If we
-	 * didn't get it from ahci_platform_get_resources(), let's try to
-	 * specify the con_id in clk_get().
-	 */
-	if (!hpriv->clks[1]) {
-		clk = clk_get(dev, "refclk");
-		if (IS_ERR(clk)) {
-			dev_err(dev, "unable to obtain the reference clock");
-			return -ENODEV;
-		}
-
-		hpriv->clks[1] = clk;
+	if (hpriv->n_clks < 2) {
+		hpriv->clks = devm_kcalloc(dev, 2, sizeof(*hpriv->clks), GFP_KERNEL);
+		if (!hpriv->clks)
+			return -ENOMEM;
+
+		hpriv->clks[0].id = "fck";
+		hpriv->clks[1].id = "refclk";
+		hpriv->n_clks = 2;
+
+		rc = devm_clk_bulk_get(dev, hpriv->n_clks, hpriv->clks);
+		if (rc)
+			return rc;
 	}
 
-	mpy = ahci_da850_calculate_mpy(clk_get_rate(hpriv->clks[1]));
+	mpy = ahci_da850_calculate_mpy(clk_get_rate(hpriv->clks[1].clk));
 	if (mpy == 0) {
 		dev_err(dev, "invalid REFCLK multiplier value: 0x%x", mpy);
 		return -EINVAL;
@@ -241,7 +232,7 @@ static SIMPLE_DEV_PM_OPS(ahci_da850_pm_ops, ahci_platform_suspend,
 
 static const struct of_device_id ahci_da850_of_match[] = {
 	{ .compatible = "ti,da850-ahci", },
-	{ },
+	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, ahci_da850_of_match);
 
diff --git a/drivers/ata/ahci_dm816.c b/drivers/ata/ahci_dm816.c
index 8bec41041671..93faed2cfeb6 100644
--- a/drivers/ata/ahci_dm816.c
+++ b/drivers/ata/ahci_dm816.c
@@ -69,12 +69,12 @@ static int ahci_dm816_phy_init(struct ahci_host_priv *hpriv, struct device *dev)
 	 * keep-alive clock and the external reference clock. We need the
 	 * rate of the latter to calculate the correct value of MPY bits.
 	 */
-	if (!hpriv->clks[1]) {
+	if (hpriv->n_clks < 2) {
 		dev_err(dev, "reference clock not supplied\n");
 		return -EINVAL;
 	}
 
-	refclk_rate = clk_get_rate(hpriv->clks[1]);
+	refclk_rate = clk_get_rate(hpriv->clks[1].clk);
 	if ((refclk_rate % 100) != 0) {
 		dev_err(dev, "reference clock rate must be divisible by 100\n");
 		return -EINVAL;
@@ -124,7 +124,7 @@ static int ahci_dm816_softreset(struct ata_link *link,
 
 static struct ata_port_operations ahci_dm816_port_ops = {
 	.inherits = &ahci_platform_ops,
-	.softreset = ahci_dm816_softreset,
+	.reset.softreset = ahci_dm816_softreset,
 };
 
 static const struct ata_port_info ahci_dm816_port_info = {
@@ -134,7 +134,7 @@ static const struct ata_port_info ahci_dm816_port_info = {
 	.port_ops	= &ahci_dm816_port_ops,
 };
 
-static struct scsi_host_template ahci_dm816_platform_sht = {
+static const struct scsi_host_template ahci_dm816_platform_sht = {
 	AHCI_SHT(AHCI_DM816_DRV_NAME),
 };
 
@@ -176,7 +176,7 @@ static SIMPLE_DEV_PM_OPS(ahci_dm816_pm_ops,
 
 static const struct of_device_id ahci_dm816_of_match[] = {
 	{ .compatible = "ti,dm816-ahci", },
-	{ },
+	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, ahci_dm816_of_match);
 
diff --git a/drivers/ata/ahci_dwc.c b/drivers/ata/ahci_dwc.c
new file mode 100644
index 000000000000..aec6d793f51a
--- /dev/null
+++ b/drivers/ata/ahci_dwc.c
@@ -0,0 +1,493 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * DWC AHCI SATA Platform driver
+ *
+ * Copyright (C) 2021 BAIKAL ELECTRONICS, JSC
+ */
+
+#include <linux/ahci_platform.h>
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/libata.h>
+#include <linux/log2.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <linux/regmap.h>
+
+#include "ahci.h"
+
+#define DRV_NAME "ahci-dwc"
+
+#define AHCI_DWC_FBS_PMPN_MAX		15
+
+/* DWC AHCI SATA controller specific registers */
+#define AHCI_DWC_HOST_OOBR		0xbc
+#define AHCI_DWC_HOST_OOB_WE		BIT(31)
+#define AHCI_DWC_HOST_CWMIN_MASK	GENMASK(30, 24)
+#define AHCI_DWC_HOST_CWMAX_MASK	GENMASK(23, 16)
+#define AHCI_DWC_HOST_CIMIN_MASK	GENMASK(15, 8)
+#define AHCI_DWC_HOST_CIMAX_MASK	GENMASK(7, 0)
+
+#define AHCI_DWC_HOST_GPCR		0xd0
+#define AHCI_DWC_HOST_GPSR		0xd4
+
+#define AHCI_DWC_HOST_TIMER1MS		0xe0
+#define AHCI_DWC_HOST_TIMV_MASK		GENMASK(19, 0)
+
+#define AHCI_DWC_HOST_GPARAM1R		0xe8
+#define AHCI_DWC_HOST_ALIGN_M		BIT(31)
+#define AHCI_DWC_HOST_RX_BUFFER		BIT(30)
+#define AHCI_DWC_HOST_PHY_DATA_MASK	GENMASK(29, 28)
+#define AHCI_DWC_HOST_PHY_RST		BIT(27)
+#define AHCI_DWC_HOST_PHY_CTRL_MASK	GENMASK(26, 21)
+#define AHCI_DWC_HOST_PHY_STAT_MASK	GENMASK(20, 15)
+#define AHCI_DWC_HOST_LATCH_M		BIT(14)
+#define AHCI_DWC_HOST_PHY_TYPE_MASK	GENMASK(13, 11)
+#define AHCI_DWC_HOST_RET_ERR		BIT(10)
+#define AHCI_DWC_HOST_AHB_ENDIAN_MASK	GENMASK(9, 8)
+#define AHCI_DWC_HOST_S_HADDR		BIT(7)
+#define AHCI_DWC_HOST_M_HADDR		BIT(6)
+#define AHCI_DWC_HOST_S_HDATA_MASK	GENMASK(5, 3)
+#define AHCI_DWC_HOST_M_HDATA_MASK	GENMASK(2, 0)
+
+#define AHCI_DWC_HOST_GPARAM2R		0xec
+#define AHCI_DWC_HOST_FBS_MEM_S		BIT(19)
+#define AHCI_DWC_HOST_FBS_PMPN_MASK	GENMASK(17, 16)
+#define AHCI_DWC_HOST_FBS_SUP		BIT(15)
+#define AHCI_DWC_HOST_DEV_CP		BIT(14)
+#define AHCI_DWC_HOST_DEV_MP		BIT(13)
+#define AHCI_DWC_HOST_ENCODE_M		BIT(12)
+#define AHCI_DWC_HOST_RXOOB_CLK_M	BIT(11)
+#define AHCI_DWC_HOST_RXOOB_M		BIT(10)
+#define AHCI_DWC_HOST_TXOOB_M		BIT(9)
+#define AHCI_DWC_HOST_RXOOB_M		BIT(10)
+#define AHCI_DWC_HOST_RXOOB_CLK_MASK	GENMASK(8, 0)
+
+#define AHCI_DWC_HOST_PPARAMR		0xf0
+#define AHCI_DWC_HOST_TX_MEM_M		BIT(11)
+#define AHCI_DWC_HOST_TX_MEM_S		BIT(10)
+#define AHCI_DWC_HOST_RX_MEM_M		BIT(9)
+#define AHCI_DWC_HOST_RX_MEM_S		BIT(8)
+#define AHCI_DWC_HOST_TXFIFO_DEPTH	GENMASK(7, 4)
+#define AHCI_DWC_HOST_RXFIFO_DEPTH	GENMASK(3, 0)
+
+#define AHCI_DWC_HOST_TESTR		0xf4
+#define AHCI_DWC_HOST_PSEL_MASK		GENMASK(18, 16)
+#define AHCI_DWC_HOST_TEST_IF		BIT(0)
+
+#define AHCI_DWC_HOST_VERSIONR		0xf8
+#define AHCI_DWC_HOST_IDR		0xfc
+
+#define AHCI_DWC_PORT_DMACR		0x70
+#define AHCI_DWC_PORT_RXABL_MASK	GENMASK(15, 12)
+#define AHCI_DWC_PORT_TXABL_MASK	GENMASK(11, 8)
+#define AHCI_DWC_PORT_RXTS_MASK		GENMASK(7, 4)
+#define AHCI_DWC_PORT_TXTS_MASK		GENMASK(3, 0)
+#define AHCI_DWC_PORT_PHYCR		0x74
+#define AHCI_DWC_PORT_PHYSR		0x78
+
+/* Baikal-T1 AHCI SATA specific registers */
+#define AHCI_BT1_HOST_PHYCR		AHCI_DWC_HOST_GPCR
+#define AHCI_BT1_HOST_MPLM_MASK		GENMASK(29, 23)
+#define AHCI_BT1_HOST_LOSDT_MASK	GENMASK(22, 20)
+#define AHCI_BT1_HOST_CRR		BIT(19)
+#define AHCI_BT1_HOST_CRW		BIT(18)
+#define AHCI_BT1_HOST_CRCD		BIT(17)
+#define AHCI_BT1_HOST_CRCA		BIT(16)
+#define AHCI_BT1_HOST_CRDI_MASK		GENMASK(15, 0)
+
+#define AHCI_BT1_HOST_PHYSR		AHCI_DWC_HOST_GPSR
+#define AHCI_BT1_HOST_CRA		BIT(16)
+#define AHCI_BT1_HOST_CRDO_MASK		GENMASK(15, 0)
+
+struct ahci_dwc_plat_data {
+	unsigned int pflags;
+	unsigned int hflags;
+	int (*init)(struct ahci_host_priv *hpriv);
+	int (*reinit)(struct ahci_host_priv *hpriv);
+	void (*clear)(struct ahci_host_priv *hpriv);
+};
+
+struct ahci_dwc_host_priv {
+	const struct ahci_dwc_plat_data *pdata;
+	struct platform_device *pdev;
+
+	u32 timv;
+	u32 dmacr[AHCI_MAX_PORTS];
+};
+
+static int ahci_bt1_init(struct ahci_host_priv *hpriv)
+{
+	struct ahci_dwc_host_priv *dpriv = hpriv->plat_data;
+	int ret;
+
+	/* APB, application and reference clocks are required */
+	if (!ahci_platform_find_clk(hpriv, "pclk") ||
+	    !ahci_platform_find_clk(hpriv, "aclk") ||
+	    !ahci_platform_find_clk(hpriv, "ref")) {
+		dev_err(&dpriv->pdev->dev, "No system clocks specified\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Fully reset the SATA AXI and ref clocks domain to ensure the state
+	 * machine is working from scratch especially if the reference clocks
+	 * source has been changed.
+	 */
+	ret = ahci_platform_assert_rsts(hpriv);
+	if (ret) {
+		dev_err(&dpriv->pdev->dev, "Couldn't assert the resets\n");
+		return ret;
+	}
+
+	ret = ahci_platform_deassert_rsts(hpriv);
+	if (ret) {
+		dev_err(&dpriv->pdev->dev, "Couldn't de-assert the resets\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static struct ahci_host_priv *ahci_dwc_get_resources(struct platform_device *pdev)
+{
+	struct ahci_dwc_host_priv *dpriv;
+	struct ahci_host_priv *hpriv;
+
+	dpriv = devm_kzalloc(&pdev->dev, sizeof(*dpriv), GFP_KERNEL);
+	if (!dpriv)
+		return ERR_PTR(-ENOMEM);
+
+	dpriv->pdev = pdev;
+	dpriv->pdata = device_get_match_data(&pdev->dev);
+	if (!dpriv->pdata)
+		return ERR_PTR(-EINVAL);
+
+	hpriv = ahci_platform_get_resources(pdev, dpriv->pdata->pflags);
+	if (IS_ERR(hpriv))
+		return hpriv;
+
+	hpriv->flags |= dpriv->pdata->hflags;
+	hpriv->plat_data = (void *)dpriv;
+
+	return hpriv;
+}
+
+static void ahci_dwc_check_cap(struct ahci_host_priv *hpriv)
+{
+	unsigned long port_map = hpriv->saved_port_map | hpriv->mask_port_map;
+	struct ahci_dwc_host_priv *dpriv = hpriv->plat_data;
+	bool dev_mp, dev_cp, fbs_sup;
+	unsigned int fbs_pmp;
+	u32 param;
+	int i;
+
+	param = readl(hpriv->mmio + AHCI_DWC_HOST_GPARAM2R);
+	dev_mp = !!(param & AHCI_DWC_HOST_DEV_MP);
+	dev_cp = !!(param & AHCI_DWC_HOST_DEV_CP);
+	fbs_sup = !!(param & AHCI_DWC_HOST_FBS_SUP);
+	fbs_pmp = 5 * FIELD_GET(AHCI_DWC_HOST_FBS_PMPN_MASK, param);
+
+	if (!dev_mp && hpriv->saved_cap & HOST_CAP_MPS) {
+		dev_warn(&dpriv->pdev->dev, "MPS is unsupported\n");
+		hpriv->saved_cap &= ~HOST_CAP_MPS;
+	}
+
+
+	if (fbs_sup && fbs_pmp < AHCI_DWC_FBS_PMPN_MAX) {
+		dev_warn(&dpriv->pdev->dev, "PMPn is limited up to %u ports\n",
+			 fbs_pmp);
+	}
+
+	for_each_set_bit(i, &port_map, AHCI_MAX_PORTS) {
+		if (!dev_mp && hpriv->saved_port_cap[i] & PORT_CMD_MPSP) {
+			dev_warn(&dpriv->pdev->dev, "MPS incapable port %d\n", i);
+			hpriv->saved_port_cap[i] &= ~PORT_CMD_MPSP;
+		}
+
+		if (!dev_cp && hpriv->saved_port_cap[i] & PORT_CMD_CPD) {
+			dev_warn(&dpriv->pdev->dev, "CPD incapable port %d\n", i);
+			hpriv->saved_port_cap[i] &= ~PORT_CMD_CPD;
+		}
+
+		if (!fbs_sup && hpriv->saved_port_cap[i] & PORT_CMD_FBSCP) {
+			dev_warn(&dpriv->pdev->dev, "FBS incapable port %d\n", i);
+			hpriv->saved_port_cap[i] &= ~PORT_CMD_FBSCP;
+		}
+	}
+}
+
+static void ahci_dwc_init_timer(struct ahci_host_priv *hpriv)
+{
+	struct ahci_dwc_host_priv *dpriv = hpriv->plat_data;
+	unsigned long rate;
+	struct clk *aclk;
+	u32 cap, cap2;
+
+	/* 1ms tick is generated only for the CCC or DevSleep features */
+	cap = readl(hpriv->mmio + HOST_CAP);
+	cap2 = readl(hpriv->mmio + HOST_CAP2);
+	if (!(cap & HOST_CAP_CCC) && !(cap2 & HOST_CAP2_SDS))
+		return;
+
+	/*
+	 * Tick is generated based on the AXI/AHB application clocks signal
+	 * so we need to be sure in the clock we are going to use.
+	 */
+	aclk = ahci_platform_find_clk(hpriv, "aclk");
+	if (!aclk)
+		return;
+
+	/* 1ms timer interval is set as TIMV = AMBA_FREQ[MHZ] * 1000 */
+	dpriv->timv = readl(hpriv->mmio + AHCI_DWC_HOST_TIMER1MS);
+	dpriv->timv = FIELD_GET(AHCI_DWC_HOST_TIMV_MASK, dpriv->timv);
+	rate = clk_get_rate(aclk) / 1000UL;
+	if (rate == dpriv->timv)
+		return;
+
+	dev_info(&dpriv->pdev->dev, "Update CCC/DevSlp timer for Fapp %lu MHz\n",
+		 rate / 1000UL);
+	dpriv->timv = FIELD_PREP(AHCI_DWC_HOST_TIMV_MASK, rate);
+	writel(dpriv->timv, hpriv->mmio + AHCI_DWC_HOST_TIMER1MS);
+}
+
+static int ahci_dwc_init_dmacr(struct ahci_host_priv *hpriv)
+{
+	struct ahci_dwc_host_priv *dpriv = hpriv->plat_data;
+	struct device_node *child;
+	void __iomem *port_mmio;
+	u32 port, dmacr, ts;
+
+	/*
+	 * Update the DMA Tx/Rx transaction sizes in accordance with the
+	 * platform setup. Note values exceeding maximal or minimal limits will
+	 * be automatically clamped. Also note the register isn't affected by
+	 * the HBA global reset so we can freely initialize it once until the
+	 * next system reset.
+	 */
+	for_each_child_of_node(dpriv->pdev->dev.of_node, child) {
+		if (!of_device_is_available(child))
+			continue;
+
+		if (of_property_read_u32(child, "reg", &port)) {
+			of_node_put(child);
+			return -EINVAL;
+		}
+
+		port_mmio = __ahci_port_base(hpriv, port);
+		dmacr = readl(port_mmio + AHCI_DWC_PORT_DMACR);
+
+		if (!of_property_read_u32(child, "snps,tx-ts-max", &ts)) {
+			ts = ilog2(ts);
+			dmacr &= ~AHCI_DWC_PORT_TXTS_MASK;
+			dmacr |= FIELD_PREP(AHCI_DWC_PORT_TXTS_MASK, ts);
+		}
+
+		if (!of_property_read_u32(child, "snps,rx-ts-max", &ts)) {
+			ts = ilog2(ts);
+			dmacr &= ~AHCI_DWC_PORT_RXTS_MASK;
+			dmacr |= FIELD_PREP(AHCI_DWC_PORT_RXTS_MASK, ts);
+		}
+
+		writel(dmacr, port_mmio + AHCI_DWC_PORT_DMACR);
+		dpriv->dmacr[port] = dmacr;
+	}
+
+	return 0;
+}
+
+static int ahci_dwc_init_host(struct ahci_host_priv *hpriv)
+{
+	struct ahci_dwc_host_priv *dpriv = hpriv->plat_data;
+	int rc;
+
+	rc = ahci_platform_enable_resources(hpriv);
+	if (rc)
+		return rc;
+
+	if (dpriv->pdata->init) {
+		rc = dpriv->pdata->init(hpriv);
+		if (rc)
+			goto err_disable_resources;
+	}
+
+	ahci_dwc_check_cap(hpriv);
+
+	ahci_dwc_init_timer(hpriv);
+
+	rc = ahci_dwc_init_dmacr(hpriv);
+	if (rc)
+		goto err_clear_platform;
+
+	return 0;
+
+err_clear_platform:
+	if (dpriv->pdata->clear)
+		dpriv->pdata->clear(hpriv);
+
+err_disable_resources:
+	ahci_platform_disable_resources(hpriv);
+
+	return rc;
+}
+
+static int ahci_dwc_reinit_host(struct ahci_host_priv *hpriv)
+{
+	struct ahci_dwc_host_priv *dpriv = hpriv->plat_data;
+	unsigned long port_map = hpriv->port_map;
+	void __iomem *port_mmio;
+	int i, rc;
+
+	rc = ahci_platform_enable_resources(hpriv);
+	if (rc)
+		return rc;
+
+	if (dpriv->pdata->reinit) {
+		rc = dpriv->pdata->reinit(hpriv);
+		if (rc)
+			goto err_disable_resources;
+	}
+
+	writel(dpriv->timv, hpriv->mmio + AHCI_DWC_HOST_TIMER1MS);
+
+	for_each_set_bit(i, &port_map, AHCI_MAX_PORTS) {
+		port_mmio = __ahci_port_base(hpriv, i);
+		writel(dpriv->dmacr[i], port_mmio + AHCI_DWC_PORT_DMACR);
+	}
+
+	return 0;
+
+err_disable_resources:
+	ahci_platform_disable_resources(hpriv);
+
+	return rc;
+}
+
+static void ahci_dwc_clear_host(struct ahci_host_priv *hpriv)
+{
+	struct ahci_dwc_host_priv *dpriv = hpriv->plat_data;
+
+	if (dpriv->pdata->clear)
+		dpriv->pdata->clear(hpriv);
+
+	ahci_platform_disable_resources(hpriv);
+}
+
+static void ahci_dwc_stop_host(struct ata_host *host)
+{
+	struct ahci_host_priv *hpriv = host->private_data;
+
+	ahci_dwc_clear_host(hpriv);
+}
+
+static struct ata_port_operations ahci_dwc_port_ops = {
+	.inherits	= &ahci_platform_ops,
+	.host_stop	= ahci_dwc_stop_host,
+};
+
+static const struct ata_port_info ahci_dwc_port_info = {
+	.flags		= AHCI_FLAG_COMMON,
+	.pio_mask	= ATA_PIO4,
+	.udma_mask	= ATA_UDMA6,
+	.port_ops	= &ahci_dwc_port_ops,
+};
+
+static const struct scsi_host_template ahci_dwc_scsi_info = {
+	AHCI_SHT(DRV_NAME),
+};
+
+static int ahci_dwc_probe(struct platform_device *pdev)
+{
+	struct ahci_host_priv *hpriv;
+	int rc;
+
+	hpriv = ahci_dwc_get_resources(pdev);
+	if (IS_ERR(hpriv))
+		return PTR_ERR(hpriv);
+
+	rc = ahci_dwc_init_host(hpriv);
+	if (rc)
+		return rc;
+
+	rc = ahci_platform_init_host(pdev, hpriv, &ahci_dwc_port_info,
+				     &ahci_dwc_scsi_info);
+	if (rc)
+		goto err_clear_host;
+
+	return 0;
+
+err_clear_host:
+	ahci_dwc_clear_host(hpriv);
+
+	return rc;
+}
+
+static int ahci_dwc_suspend(struct device *dev)
+{
+	struct ata_host *host = dev_get_drvdata(dev);
+	struct ahci_host_priv *hpriv = host->private_data;
+	int rc;
+
+	rc = ahci_platform_suspend_host(dev);
+	if (rc)
+		return rc;
+
+	ahci_dwc_clear_host(hpriv);
+
+	return 0;
+}
+
+static int ahci_dwc_resume(struct device *dev)
+{
+	struct ata_host *host = dev_get_drvdata(dev);
+	struct ahci_host_priv *hpriv = host->private_data;
+	int rc;
+
+	rc = ahci_dwc_reinit_host(hpriv);
+	if (rc)
+		return rc;
+
+	return ahci_platform_resume_host(dev);
+}
+
+static DEFINE_SIMPLE_DEV_PM_OPS(ahci_dwc_pm_ops, ahci_dwc_suspend,
+				ahci_dwc_resume);
+
+static struct ahci_dwc_plat_data ahci_dwc_plat = {
+	.pflags = AHCI_PLATFORM_GET_RESETS,
+};
+
+static struct ahci_dwc_plat_data ahci_bt1_plat = {
+	.pflags = AHCI_PLATFORM_GET_RESETS | AHCI_PLATFORM_RST_TRIGGER,
+	.init = ahci_bt1_init,
+};
+
+static const struct of_device_id ahci_dwc_of_match[] = {
+	{ .compatible = "snps,dwc-ahci", &ahci_dwc_plat },
+	{ .compatible = "snps,spear-ahci", &ahci_dwc_plat },
+	{ .compatible = "baikal,bt1-ahci", &ahci_bt1_plat },
+	{},
+};
+MODULE_DEVICE_TABLE(of, ahci_dwc_of_match);
+
+static struct platform_driver ahci_dwc_driver = {
+	.probe = ahci_dwc_probe,
+	.remove = ata_platform_remove_one,
+	.shutdown = ahci_platform_shutdown,
+	.driver = {
+		.name = DRV_NAME,
+		.of_match_table = ahci_dwc_of_match,
+		.pm = &ahci_dwc_pm_ops,
+	},
+};
+module_platform_driver(ahci_dwc_driver);
+
+MODULE_DESCRIPTION("DWC AHCI SATA platform driver");
+MODULE_AUTHOR("Serge Semin <Sergey.Semin@baikalelectronics.ru>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/ata/ahci_imx.c b/drivers/ata/ahci_imx.c
index 388baf528fa8..86aedd5923ac 100644
--- a/drivers/ata/ahci_imx.c
+++ b/drivers/ata/ahci_imx.c
@@ -9,15 +9,17 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
+#include <linux/property.h>
 #include <linux/regmap.h>
 #include <linux/ahci_platform.h>
 #include <linux/gpio/consumer.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
 #include <linux/mfd/syscon.h>
 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
 #include <linux/libata.h>
 #include <linux/hwmon.h>
 #include <linux/hwmon-sysfs.h>
+#include <linux/phy/phy.h>
 #include <linux/thermal.h>
 #include "ahci.h"
 
@@ -43,42 +45,10 @@ enum {
 	/* Clock Reset Register */
 	IMX_CLOCK_RESET				= 0x7f3f,
 	IMX_CLOCK_RESET_RESET			= 1 << 0,
-	/* IMX8QM HSIO AHCI definitions */
-	IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET	= 0x03,
-	IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET	= 0x09,
-	IMX8QM_SATA_PHY_IMPED_RATIO_85OHM	= 0x6c,
-	IMX8QM_LPCG_PHYX2_OFFSET		= 0x00000,
-	IMX8QM_CSR_PHYX2_OFFSET			= 0x90000,
-	IMX8QM_CSR_PHYX1_OFFSET			= 0xa0000,
-	IMX8QM_CSR_PHYX_STTS0_OFFSET		= 0x4,
-	IMX8QM_CSR_PCIEA_OFFSET			= 0xb0000,
-	IMX8QM_CSR_PCIEB_OFFSET			= 0xc0000,
-	IMX8QM_CSR_SATA_OFFSET			= 0xd0000,
-	IMX8QM_CSR_PCIE_CTRL2_OFFSET		= 0x8,
-	IMX8QM_CSR_MISC_OFFSET			= 0xe0000,
-
-	IMX8QM_LPCG_PHYX2_PCLK0_MASK		= (0x3 << 16),
-	IMX8QM_LPCG_PHYX2_PCLK1_MASK		= (0x3 << 20),
-	IMX8QM_PHY_APB_RSTN_0			= BIT(0),
-	IMX8QM_PHY_MODE_SATA			= BIT(19),
-	IMX8QM_PHY_MODE_MASK			= (0xf << 17),
-	IMX8QM_PHY_PIPE_RSTN_0			= BIT(24),
-	IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0		= BIT(25),
-	IMX8QM_PHY_PIPE_RSTN_1			= BIT(26),
-	IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1		= BIT(27),
-	IMX8QM_STTS0_LANE0_TX_PLL_LOCK		= BIT(4),
-	IMX8QM_MISC_IOB_RXENA			= BIT(0),
-	IMX8QM_MISC_IOB_TXENA			= BIT(1),
-	IMX8QM_MISC_PHYX1_EPCS_SEL		= BIT(12),
-	IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1	= BIT(24),
-	IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0	= BIT(25),
-	IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1	= BIT(28),
-	IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0	= BIT(29),
-	IMX8QM_SATA_CTRL_RESET_N		= BIT(12),
-	IMX8QM_SATA_CTRL_EPCS_PHYRESET_N	= BIT(7),
-	IMX8QM_CTRL_BUTTON_RST_N		= BIT(21),
-	IMX8QM_CTRL_POWER_UP_RST_N		= BIT(23),
-	IMX8QM_CTRL_LTSSM_ENABLE		= BIT(4),
+	/* IMX8QM SATA specific control registers */
+	IMX8QM_SATA_AHCI_PTC			= 0xc8,
+	IMX8QM_SATA_AHCI_PTC_RXWM_MASK		= GENMASK(6, 0),
+	IMX8QM_SATA_AHCI_PTC_RXWM		= 0x29,
 };
 
 enum ahci_imx_type {
@@ -94,14 +64,10 @@ struct imx_ahci_priv {
 	struct clk *sata_clk;
 	struct clk *sata_ref_clk;
 	struct clk *ahb_clk;
-	struct clk *epcs_tx_clk;
-	struct clk *epcs_rx_clk;
-	struct clk *phy_apbclk;
-	struct clk *phy_pclk0;
-	struct clk *phy_pclk1;
-	void __iomem *phy_base;
-	struct gpio_desc *clkreq_gpiod;
 	struct regmap *gpr;
+	struct phy *sata_phy;
+	struct phy *cali_phy0;
+	struct phy *cali_phy1;
 	bool no_device;
 	bool first_time;
 	u32 phy_params;
@@ -327,7 +293,7 @@ static int read_adc_sum(void *dev, u16 rtune_ctl_reg, void __iomem * mmio)
 }
 
 /* SATA AHCI temperature monitor */
-static int sata_ahci_read_temperature(void *dev, int *temp)
+static int __sata_ahci_read_temperature(void *dev, int *temp)
 {
 	u16 mpll_test_reg, rtune_ctl_reg, dac_ctl_reg, read_sum;
 	u32 str1, str2, str3, str4;
@@ -416,6 +382,11 @@ static int sata_ahci_read_temperature(void *dev, int *temp)
 	return 0;
 }
 
+static int sata_ahci_read_temperature(struct thermal_zone_device *tz, int *temp)
+{
+	return __sata_ahci_read_temperature(thermal_zone_device_priv(tz), temp);
+}
+
 static ssize_t sata_ahci_show_temp(struct device *dev,
 				   struct device_attribute *da,
 				   char *buf)
@@ -423,14 +394,14 @@ static ssize_t sata_ahci_show_temp(struct device *dev,
 	unsigned int temp = 0;
 	int err;
 
-	err = sata_ahci_read_temperature(dev, &temp);
+	err = __sata_ahci_read_temperature(dev, &temp);
 	if (err < 0)
 		return err;
 
 	return sprintf(buf, "%u\n", temp);
 }
 
-static const struct thermal_zone_of_device_ops fsl_sata_ahci_of_thermal_ops = {
+static const struct thermal_zone_device_ops fsl_sata_ahci_of_thermal_ops = {
 	.get_temp = sata_ahci_read_temperature,
 };
 
@@ -444,201 +415,79 @@ ATTRIBUTE_GROUPS(fsl_sata_ahci);
 
 static int imx8_sata_enable(struct ahci_host_priv *hpriv)
 {
-	u32 val, reg;
-	int i, ret;
+	u32 val;
+	int ret;
 	struct imx_ahci_priv *imxpriv = hpriv->plat_data;
 	struct device *dev = &imxpriv->ahci_pdev->dev;
 
-	/* configure the hsio for sata */
-	ret = clk_prepare_enable(imxpriv->phy_pclk0);
-	if (ret < 0) {
-		dev_err(dev, "can't enable phy_pclk0.\n");
+	/*
+	 * Since "REXT" pin is only present for first lane of i.MX8QM
+	 * PHY, its calibration results will be stored, passed through
+	 * to the second lane PHY, and shared with all three lane PHYs.
+	 *
+	 * Initialize the first two lane PHYs here, although only the
+	 * third lane PHY is used by SATA.
+	 */
+	ret = phy_init(imxpriv->cali_phy0);
+	if (ret) {
+		dev_err(dev, "cali PHY init failed\n");
 		return ret;
 	}
-	ret = clk_prepare_enable(imxpriv->phy_pclk1);
-	if (ret < 0) {
-		dev_err(dev, "can't enable phy_pclk1.\n");
-		goto disable_phy_pclk0;
+	ret = phy_power_on(imxpriv->cali_phy0);
+	if (ret) {
+		dev_err(dev, "cali PHY power on failed\n");
+		goto err_cali_phy0_exit;
 	}
-	ret = clk_prepare_enable(imxpriv->epcs_tx_clk);
-	if (ret < 0) {
-		dev_err(dev, "can't enable epcs_tx_clk.\n");
-		goto disable_phy_pclk1;
+	ret = phy_init(imxpriv->cali_phy1);
+	if (ret) {
+		dev_err(dev, "cali PHY1 init failed\n");
+		goto err_cali_phy0_off;
 	}
-	ret = clk_prepare_enable(imxpriv->epcs_rx_clk);
-	if (ret < 0) {
-		dev_err(dev, "can't enable epcs_rx_clk.\n");
-		goto disable_epcs_tx_clk;
+	ret = phy_power_on(imxpriv->cali_phy1);
+	if (ret) {
+		dev_err(dev, "cali PHY1 power on failed\n");
+		goto err_cali_phy1_exit;
 	}
-	ret = clk_prepare_enable(imxpriv->phy_apbclk);
-	if (ret < 0) {
-		dev_err(dev, "can't enable phy_apbclk.\n");
-		goto disable_epcs_rx_clk;
+	ret = phy_init(imxpriv->sata_phy);
+	if (ret) {
+		dev_err(dev, "sata PHY init failed\n");
+		goto err_cali_phy1_off;
 	}
-	/* Configure PHYx2 PIPE_RSTN */
-	regmap_read(imxpriv->gpr, IMX8QM_CSR_PCIEA_OFFSET +
-			IMX8QM_CSR_PCIE_CTRL2_OFFSET, &val);
-	if ((val & IMX8QM_CTRL_LTSSM_ENABLE) == 0) {
-		/* The link of the PCIEA of HSIO is down */
-		regmap_update_bits(imxpriv->gpr,
-				IMX8QM_CSR_PHYX2_OFFSET,
-				IMX8QM_PHY_PIPE_RSTN_0 |
-				IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0,
-				IMX8QM_PHY_PIPE_RSTN_0 |
-				IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0);
+	ret = phy_set_mode(imxpriv->sata_phy, PHY_MODE_SATA);
+	if (ret) {
+		dev_err(dev, "unable to set SATA PHY mode\n");
+		goto err_sata_phy_exit;
 	}
-	regmap_read(imxpriv->gpr, IMX8QM_CSR_PCIEB_OFFSET +
-			IMX8QM_CSR_PCIE_CTRL2_OFFSET, &reg);
-	if ((reg & IMX8QM_CTRL_LTSSM_ENABLE) == 0) {
-		/* The link of the PCIEB of HSIO is down */
-		regmap_update_bits(imxpriv->gpr,
-				IMX8QM_CSR_PHYX2_OFFSET,
-				IMX8QM_PHY_PIPE_RSTN_1 |
-				IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1,
-				IMX8QM_PHY_PIPE_RSTN_1 |
-				IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1);
-	}
-	if (((reg | val) & IMX8QM_CTRL_LTSSM_ENABLE) == 0) {
-		/* The links of both PCIA and PCIEB of HSIO are down */
-		regmap_update_bits(imxpriv->gpr,
-				IMX8QM_LPCG_PHYX2_OFFSET,
-				IMX8QM_LPCG_PHYX2_PCLK0_MASK |
-				IMX8QM_LPCG_PHYX2_PCLK1_MASK,
-				0);
+	ret = phy_power_on(imxpriv->sata_phy);
+	if (ret) {
+		dev_err(dev, "sata PHY power up failed\n");
+		goto err_sata_phy_exit;
 	}
 
-	/* set PWR_RST and BT_RST of csr_pciea */
-	val = IMX8QM_CSR_PCIEA_OFFSET + IMX8QM_CSR_PCIE_CTRL2_OFFSET;
-	regmap_update_bits(imxpriv->gpr,
-			val,
-			IMX8QM_CTRL_BUTTON_RST_N,
-			IMX8QM_CTRL_BUTTON_RST_N);
-	regmap_update_bits(imxpriv->gpr,
-			val,
-			IMX8QM_CTRL_POWER_UP_RST_N,
-			IMX8QM_CTRL_POWER_UP_RST_N);
-
-	/* PHYX1_MODE to SATA */
-	regmap_update_bits(imxpriv->gpr,
-			IMX8QM_CSR_PHYX1_OFFSET,
-			IMX8QM_PHY_MODE_MASK,
-			IMX8QM_PHY_MODE_SATA);
+	/* The cali_phy# can be turned off after SATA PHY is initialized. */
+	phy_power_off(imxpriv->cali_phy1);
+	phy_exit(imxpriv->cali_phy1);
+	phy_power_off(imxpriv->cali_phy0);
+	phy_exit(imxpriv->cali_phy0);
 
-	/*
-	 * BIT0 RXENA 1, BIT1 TXENA 0
-	 * BIT12 PHY_X1_EPCS_SEL 1.
-	 */
-	regmap_update_bits(imxpriv->gpr,
-			IMX8QM_CSR_MISC_OFFSET,
-			IMX8QM_MISC_IOB_RXENA,
-			IMX8QM_MISC_IOB_RXENA);
-	regmap_update_bits(imxpriv->gpr,
-			IMX8QM_CSR_MISC_OFFSET,
-			IMX8QM_MISC_IOB_TXENA,
-			0);
-	regmap_update_bits(imxpriv->gpr,
-			IMX8QM_CSR_MISC_OFFSET,
-			IMX8QM_MISC_PHYX1_EPCS_SEL,
-			IMX8QM_MISC_PHYX1_EPCS_SEL);
-	/*
-	 * It is possible, for PCIe and SATA are sharing
-	 * the same clock source, HPLL or external oscillator.
-	 * When PCIe is in low power modes (L1.X or L2 etc),
-	 * the clock source can be turned off. In this case,
-	 * if this clock source is required to be toggling by
-	 * SATA, then SATA functions will be abnormal.
-	 * Set the override here to avoid it.
-	 */
-	regmap_update_bits(imxpriv->gpr,
-			IMX8QM_CSR_MISC_OFFSET,
-			IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1 |
-			IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0 |
-			IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1 |
-			IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0,
-			IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1 |
-			IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0 |
-			IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1 |
-			IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0);
-
-	/* clear PHY RST, then set it */
-	regmap_update_bits(imxpriv->gpr,
-			IMX8QM_CSR_SATA_OFFSET,
-			IMX8QM_SATA_CTRL_EPCS_PHYRESET_N,
-			0);
-
-	regmap_update_bits(imxpriv->gpr,
-			IMX8QM_CSR_SATA_OFFSET,
-			IMX8QM_SATA_CTRL_EPCS_PHYRESET_N,
-			IMX8QM_SATA_CTRL_EPCS_PHYRESET_N);
-
-	/* CTRL RST: SET -> delay 1 us -> CLEAR -> SET */
-	regmap_update_bits(imxpriv->gpr,
-			IMX8QM_CSR_SATA_OFFSET,
-			IMX8QM_SATA_CTRL_RESET_N,
-			IMX8QM_SATA_CTRL_RESET_N);
-	udelay(1);
-	regmap_update_bits(imxpriv->gpr,
-			IMX8QM_CSR_SATA_OFFSET,
-			IMX8QM_SATA_CTRL_RESET_N,
-			0);
-	regmap_update_bits(imxpriv->gpr,
-			IMX8QM_CSR_SATA_OFFSET,
-			IMX8QM_SATA_CTRL_RESET_N,
-			IMX8QM_SATA_CTRL_RESET_N);
-
-	/* APB reset */
-	regmap_update_bits(imxpriv->gpr,
-			IMX8QM_CSR_PHYX1_OFFSET,
-			IMX8QM_PHY_APB_RSTN_0,
-			IMX8QM_PHY_APB_RSTN_0);
-
-	for (i = 0; i < 100; i++) {
-		reg = IMX8QM_CSR_PHYX1_OFFSET +
-			IMX8QM_CSR_PHYX_STTS0_OFFSET;
-		regmap_read(imxpriv->gpr, reg, &val);
-		val &= IMX8QM_STTS0_LANE0_TX_PLL_LOCK;
-		if (val == IMX8QM_STTS0_LANE0_TX_PLL_LOCK)
-			break;
-		udelay(1);
-	}
-
-	if (val != IMX8QM_STTS0_LANE0_TX_PLL_LOCK) {
-		dev_err(dev, "TX PLL of the PHY is not locked\n");
-		ret = -ENODEV;
-	} else {
-		writeb(imxpriv->imped_ratio, imxpriv->phy_base +
-				IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET);
-		writeb(imxpriv->imped_ratio, imxpriv->phy_base +
-				IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET);
-		reg = readb(imxpriv->phy_base +
-				IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET);
-		if (unlikely(reg != imxpriv->imped_ratio))
-			dev_info(dev, "Can't set PHY RX impedance ratio.\n");
-		reg = readb(imxpriv->phy_base +
-				IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET);
-		if (unlikely(reg != imxpriv->imped_ratio))
-			dev_info(dev, "Can't set PHY TX impedance ratio.\n");
-		usleep_range(50, 100);
+	/* RxWaterMark setting */
+	val = readl(hpriv->mmio + IMX8QM_SATA_AHCI_PTC);
+	val &= ~IMX8QM_SATA_AHCI_PTC_RXWM_MASK;
+	val |= IMX8QM_SATA_AHCI_PTC_RXWM;
+	writel(val, hpriv->mmio + IMX8QM_SATA_AHCI_PTC);
 
-		/*
-		 * To reduce the power consumption, gate off
-		 * the PHY clks
-		 */
-		clk_disable_unprepare(imxpriv->phy_apbclk);
-		clk_disable_unprepare(imxpriv->phy_pclk1);
-		clk_disable_unprepare(imxpriv->phy_pclk0);
-		return ret;
-	}
+	return 0;
 
-	clk_disable_unprepare(imxpriv->phy_apbclk);
-disable_epcs_rx_clk:
-	clk_disable_unprepare(imxpriv->epcs_rx_clk);
-disable_epcs_tx_clk:
-	clk_disable_unprepare(imxpriv->epcs_tx_clk);
-disable_phy_pclk1:
-	clk_disable_unprepare(imxpriv->phy_pclk1);
-disable_phy_pclk0:
-	clk_disable_unprepare(imxpriv->phy_pclk0);
+err_sata_phy_exit:
+	phy_exit(imxpriv->sata_phy);
+err_cali_phy1_off:
+	phy_power_off(imxpriv->cali_phy1);
+err_cali_phy1_exit:
+	phy_exit(imxpriv->cali_phy1);
+err_cali_phy0_off:
+	phy_power_off(imxpriv->cali_phy0);
+err_cali_phy0_exit:
+	phy_exit(imxpriv->cali_phy0);
 
 	return ret;
 }
@@ -662,7 +511,7 @@ static int imx_sata_enable(struct ahci_host_priv *hpriv)
 
 	if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) {
 		/*
-		 * set PHY Paremeters, two steps to configure the GPR13,
+		 * set PHY Parameters, two steps to configure the GPR13,
 		 * one write for rest of parameters, mask of first write
 		 * is 0x07ffffff, and the other one write for setting
 		 * the mpll_clk_en.
@@ -692,6 +541,9 @@ static int imx_sata_enable(struct ahci_host_priv *hpriv)
 		}
 	} else if (imxpriv->type == AHCI_IMX8QM) {
 		ret = imx8_sata_enable(hpriv);
+		if (ret)
+			goto disable_clk;
+
 	}
 
 	usleep_range(1000, 2000);
@@ -730,8 +582,10 @@ static void imx_sata_disable(struct ahci_host_priv *hpriv)
 		break;
 
 	case AHCI_IMX8QM:
-		clk_disable_unprepare(imxpriv->epcs_rx_clk);
-		clk_disable_unprepare(imxpriv->epcs_tx_clk);
+		if (imxpriv->sata_phy) {
+			phy_power_off(imxpriv->sata_phy);
+			phy_exit(imxpriv->sata_phy);
+		}
 		break;
 
 	default:
@@ -754,6 +608,9 @@ static void ahci_imx_error_handler(struct ata_port *ap)
 
 	ahci_error_handler(ap);
 
+	if (imxpriv->type == AHCI_IMX8QM)
+		return;
+
 	if (!(imxpriv->first_time) || ahci_imx_hotplug)
 		return;
 
@@ -785,18 +642,19 @@ static int ahci_imx_softreset(struct ata_link *link, unsigned int *class,
 	int ret;
 
 	if (imxpriv->type == AHCI_IMX53)
-		ret = ahci_pmp_retry_srst_ops.softreset(link, class, deadline);
+		ret = ahci_pmp_retry_srst_ops.reset.softreset(link, class,
+							      deadline);
 	else
-		ret = ahci_ops.softreset(link, class, deadline);
+		ret = ahci_ops.reset.softreset(link, class, deadline);
 
 	return ret;
 }
 
 static struct ata_port_operations ahci_imx_ops = {
-	.inherits	= &ahci_ops,
-	.host_stop	= ahci_imx_host_stop,
-	.error_handler	= ahci_imx_error_handler,
-	.softreset	= ahci_imx_softreset,
+	.inherits		= &ahci_ops,
+	.host_stop		= ahci_imx_host_stop,
+	.error_handler		= ahci_imx_error_handler,
+	.reset.softreset	= ahci_imx_softreset,
 };
 
 static const struct ata_port_info ahci_imx_port_info = {
@@ -811,7 +669,7 @@ static const struct of_device_id imx_ahci_of_match[] = {
 	{ .compatible = "fsl,imx6q-ahci", .data = (void *)AHCI_IMX6Q },
 	{ .compatible = "fsl,imx6qp-ahci", .data = (void *)AHCI_IMX6QP },
 	{ .compatible = "fsl,imx8qm-ahci", .data = (void *)AHCI_IMX8QM },
-	{},
+	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
 
@@ -974,87 +832,36 @@ static u32 imx_ahci_parse_props(struct device *dev,
 	return reg_value;
 }
 
-static struct scsi_host_template ahci_platform_sht = {
+static const struct scsi_host_template ahci_platform_sht = {
 	AHCI_SHT(DRV_NAME),
 };
 
 static int imx8_sata_probe(struct device *dev, struct imx_ahci_priv *imxpriv)
 {
-	struct resource *phy_res;
-	struct platform_device *pdev = imxpriv->ahci_pdev;
-	struct device_node *np = dev->of_node;
-
-	if (of_property_read_u32(np, "fsl,phy-imp", &imxpriv->imped_ratio))
-		imxpriv->imped_ratio = IMX8QM_SATA_PHY_IMPED_RATIO_85OHM;
-	phy_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
-	if (phy_res) {
-		imxpriv->phy_base = devm_ioremap(dev, phy_res->start,
-					resource_size(phy_res));
-		if (!imxpriv->phy_base) {
-			dev_err(dev, "error with ioremap\n");
-			return -ENOMEM;
-		}
-	} else {
-		dev_err(dev, "missing *phy* reg region.\n");
-		return -ENOMEM;
-	}
-	imxpriv->gpr =
-		 syscon_regmap_lookup_by_phandle(np, "hsio");
-	if (IS_ERR(imxpriv->gpr)) {
-		dev_err(dev, "unable to find gpr registers\n");
-		return PTR_ERR(imxpriv->gpr);
-	}
-
-	imxpriv->epcs_tx_clk = devm_clk_get(dev, "epcs_tx");
-	if (IS_ERR(imxpriv->epcs_tx_clk)) {
-		dev_err(dev, "can't get epcs_tx_clk clock.\n");
-		return PTR_ERR(imxpriv->epcs_tx_clk);
-	}
-	imxpriv->epcs_rx_clk = devm_clk_get(dev, "epcs_rx");
-	if (IS_ERR(imxpriv->epcs_rx_clk)) {
-		dev_err(dev, "can't get epcs_rx_clk clock.\n");
-		return PTR_ERR(imxpriv->epcs_rx_clk);
-	}
-	imxpriv->phy_pclk0 = devm_clk_get(dev, "phy_pclk0");
-	if (IS_ERR(imxpriv->phy_pclk0)) {
-		dev_err(dev, "can't get phy_pclk0 clock.\n");
-		return PTR_ERR(imxpriv->phy_pclk0);
-	}
-	imxpriv->phy_pclk1 = devm_clk_get(dev, "phy_pclk1");
-	if (IS_ERR(imxpriv->phy_pclk1)) {
-		dev_err(dev, "can't get phy_pclk1 clock.\n");
-		return PTR_ERR(imxpriv->phy_pclk1);
-	}
-	imxpriv->phy_apbclk = devm_clk_get(dev, "phy_apbclk");
-	if (IS_ERR(imxpriv->phy_apbclk)) {
-		dev_err(dev, "can't get phy_apbclk clock.\n");
-		return PTR_ERR(imxpriv->phy_apbclk);
-	}
-
-	/* Fetch GPIO, then enable the external OSC */
-	imxpriv->clkreq_gpiod = devm_gpiod_get_optional(dev, "clkreq",
-				GPIOD_OUT_LOW | GPIOD_FLAGS_BIT_NONEXCLUSIVE);
-	if (IS_ERR(imxpriv->clkreq_gpiod))
-		return PTR_ERR(imxpriv->clkreq_gpiod);
-	if (imxpriv->clkreq_gpiod)
-		gpiod_set_consumer_name(imxpriv->clkreq_gpiod, "SATA CLKREQ");
-
+	imxpriv->sata_phy = devm_phy_get(dev, "sata-phy");
+	if (IS_ERR(imxpriv->sata_phy))
+		return dev_err_probe(dev, PTR_ERR(imxpriv->sata_phy),
+				     "Failed to get sata_phy\n");
+
+	imxpriv->cali_phy0 = devm_phy_get(dev, "cali-phy0");
+	if (IS_ERR(imxpriv->cali_phy0))
+		return dev_err_probe(dev, PTR_ERR(imxpriv->cali_phy0),
+				     "Failed to get cali_phy0\n");
+	imxpriv->cali_phy1 = devm_phy_get(dev, "cali-phy1");
+	if (IS_ERR(imxpriv->cali_phy1))
+		return dev_err_probe(dev, PTR_ERR(imxpriv->cali_phy1),
+				     "Failed to get cali_phy1\n");
 	return 0;
 }
 
 static int imx_ahci_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
-	const struct of_device_id *of_id;
 	struct ahci_host_priv *hpriv;
 	struct imx_ahci_priv *imxpriv;
 	unsigned int reg_val;
 	int ret;
 
-	of_id = of_match_device(imx_ahci_of_match, dev);
-	if (!of_id)
-		return -EINVAL;
-
 	imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
 	if (!imxpriv)
 		return -ENOMEM;
@@ -1062,7 +869,7 @@ static int imx_ahci_probe(struct platform_device *pdev)
 	imxpriv->ahci_pdev = pdev;
 	imxpriv->no_device = false;
 	imxpriv->first_time = true;
-	imxpriv->type = (enum ahci_imx_type)of_id->data;
+	imxpriv->type = (enum ahci_imx_type)device_get_match_data(dev);
 
 	imxpriv->sata_clk = devm_clk_get(dev, "sata");
 	if (IS_ERR(imxpriv->sata_clk)) {
@@ -1076,12 +883,6 @@ static int imx_ahci_probe(struct platform_device *pdev)
 		return PTR_ERR(imxpriv->sata_ref_clk);
 	}
 
-	imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
-	if (IS_ERR(imxpriv->ahb_clk)) {
-		dev_err(dev, "can't get ahb clock.\n");
-		return PTR_ERR(imxpriv->ahb_clk);
-	}
-
 	if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) {
 		u32 reg_value;
 
@@ -1131,8 +932,8 @@ static int imx_ahci_probe(struct platform_device *pdev)
 			ret = PTR_ERR(hwmon_dev);
 			goto disable_clk;
 		}
-		devm_thermal_zone_of_sensor_register(hwmon_dev, 0, hwmon_dev,
-					     &fsl_sata_ahci_of_thermal_ops);
+		devm_thermal_of_zone_register(hwmon_dev, 0, hwmon_dev,
+					      &fsl_sata_ahci_of_thermal_ops);
 		dev_info(dev, "%s: sensor 'sata_ahci'\n", dev_name(hwmon_dev));
 	}
 
@@ -1141,11 +942,8 @@ static int imx_ahci_probe(struct platform_device *pdev)
 		goto disable_clk;
 
 	/*
-	 * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
-	 * and IP vendor specific register IMX_TIMER1MS.
-	 * Configure CAP_SSS (support stagered spin up).
-	 * Implement the port0.
-	 * Get the ahb clock rate, and configure the TIMER1MS register.
+	 * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL.
+	 * Set CAP_SSS (support stagered spin up) and Implement the port0.
 	 */
 	reg_val = readl(hpriv->mmio + HOST_CAP);
 	if (!(reg_val & HOST_CAP_SSS)) {
@@ -1158,8 +956,20 @@ static int imx_ahci_probe(struct platform_device *pdev)
 		writel(reg_val, hpriv->mmio + HOST_PORTS_IMPL);
 	}
 
-	reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
-	writel(reg_val, hpriv->mmio + IMX_TIMER1MS);
+	if (imxpriv->type != AHCI_IMX8QM) {
+		/*
+		 * Get AHB clock rate and configure the vendor specified
+		 * TIMER1MS register on i.MX53, i.MX6Q and i.MX6QP only.
+		 */
+		imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
+		if (IS_ERR(imxpriv->ahb_clk)) {
+			dev_err(dev, "Failed to get ahb clock\n");
+			ret = PTR_ERR(imxpriv->ahb_clk);
+			goto disable_sata;
+		}
+		reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
+		writel(reg_val, hpriv->mmio + IMX_TIMER1MS);
+	}
 
 	ret = ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info,
 				      &ahci_platform_sht);
@@ -1228,6 +1038,6 @@ static struct platform_driver imx_ahci_driver = {
 module_platform_driver(imx_ahci_driver);
 
 MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver");
-MODULE_AUTHOR("Richard Zhu <Hong-Xing.Zhu@freescale.com>");
+MODULE_AUTHOR("Richard Zhu <hongxing.zhu@nxp.com>");
 MODULE_LICENSE("GPL");
-MODULE_ALIAS("ahci:imx");
+MODULE_ALIAS("platform:" DRV_NAME);
diff --git a/drivers/ata/ahci_mtk.c b/drivers/ata/ahci_mtk.c
index d9b08ae7c3b2..7295b9066ae2 100644
--- a/drivers/ata/ahci_mtk.c
+++ b/drivers/ata/ahci_mtk.c
@@ -11,6 +11,7 @@
 #include <linux/libata.h>
 #include <linux/mfd/syscon.h>
 #include <linux/module.h>
+#include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/pm.h>
 #include <linux/regmap.h>
@@ -37,7 +38,7 @@ static const struct ata_port_info ahci_port_info = {
 	.port_ops	= &ahci_platform_ops,
 };
 
-static struct scsi_host_template ahci_platform_sht = {
+static const struct scsi_host_template ahci_platform_sht = {
 	AHCI_SHT(DRV_NAME),
 };
 
@@ -106,7 +107,7 @@ static int mtk_ahci_parse_property(struct ahci_host_priv *hpriv,
 	struct device_node *np = dev->of_node;
 
 	/* enable SATA function if needed */
-	if (of_find_property(np, "mediatek,phy-mode", NULL)) {
+	if (of_property_present(np, "mediatek,phy-mode")) {
 		plat->mode = syscon_regmap_lookup_by_phandle(
 					np, "mediatek,phy-mode");
 		if (IS_ERR(plat->mode)) {
@@ -118,8 +119,6 @@ static int mtk_ahci_parse_property(struct ahci_host_priv *hpriv,
 				   SYS_CFG_SATA_EN);
 	}
 
-	of_property_read_u32(np, "ports-implemented", &hpriv->force_port_map);
-
 	return 0;
 }
 
@@ -169,7 +168,7 @@ static SIMPLE_DEV_PM_OPS(ahci_pm_ops, ahci_platform_suspend,
 
 static const struct of_device_id ahci_of_match[] = {
 	{ .compatible = "mediatek,mtk-ahci", },
-	{},
+	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, ahci_of_match);
 
diff --git a/drivers/ata/ahci_mvebu.c b/drivers/ata/ahci_mvebu.c
index d4bba3ace45d..8744dae41612 100644
--- a/drivers/ata/ahci_mvebu.c
+++ b/drivers/ata/ahci_mvebu.c
@@ -15,7 +15,7 @@
 #include <linux/kernel.h>
 #include <linux/mbus.h>
 #include <linux/module.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
 #include <linux/platform_device.h>
 #include "ahci.h"
 
@@ -178,7 +178,7 @@ static const struct ata_port_info ahci_mvebu_port_info = {
 	.port_ops  = &ahci_platform_ops,
 };
 
-static struct scsi_host_template ahci_platform_sht = {
+static const struct scsi_host_template ahci_platform_sht = {
 	AHCI_SHT(DRV_NAME),
 };
 
@@ -239,7 +239,7 @@ static const struct of_device_id ahci_mvebu_of_match[] = {
 		.compatible = "marvell,armada-3700-ahci",
 		.data = &ahci_mvebu_armada_3700_plat_data,
 	},
-	{ },
+	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, ahci_mvebu_of_match);
 
diff --git a/drivers/ata/ahci_octeon.c b/drivers/ata/ahci_octeon.c
index 5a44e089c6bb..9accf8923891 100644
--- a/drivers/ata/ahci_octeon.c
+++ b/drivers/ata/ahci_octeon.c
@@ -16,7 +16,6 @@
 #include <linux/of_platform.h>
 
 #include <asm/octeon/octeon.h>
-#include <asm/bitfield.h>
 
 #define CVMX_SATA_UCTL_SHIM_CFG		0xE8
 
@@ -32,13 +31,11 @@ static int ahci_octeon_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct device_node *node = dev->of_node;
-	struct resource *res;
 	void __iomem *base;
 	u64 cfg;
 	int ret;
 
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	base = devm_ioremap_resource(&pdev->dev, res);
+	base = devm_platform_ioremap_resource(pdev, 0);
 	if (IS_ERR(base))
 		return PTR_ERR(base);
 
@@ -73,20 +70,14 @@ static int ahci_octeon_probe(struct platform_device *pdev)
 	return 0;
 }
 
-static int ahci_octeon_remove(struct platform_device *pdev)
-{
-	return 0;
-}
-
 static const struct of_device_id octeon_ahci_match[] = {
 	{ .compatible = "cavium,octeon-7130-sata-uctl", },
-	{},
+	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, octeon_ahci_match);
 
 static struct platform_driver ahci_octeon_driver = {
 	.probe          = ahci_octeon_probe,
-	.remove         = ahci_octeon_remove,
 	.driver         = {
 		.name   = "octeon-ahci",
 		.of_match_table = octeon_ahci_match,
diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
index 3aab2e3d57f3..c18054333f7c 100644
--- a/drivers/ata/ahci_platform.c
+++ b/drivers/ata/ahci_platform.c
@@ -9,14 +9,14 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/mod_devicetable.h>
 #include <linux/module.h>
 #include <linux/pm.h>
 #include <linux/device.h>
-#include <linux/of_device.h>
 #include <linux/platform_device.h>
+#include <linux/property.h>
 #include <linux/libata.h>
 #include <linux/ahci_platform.h>
-#include <linux/acpi.h>
 #include <linux/pci_ids.h>
 #include "ahci.h"
 
@@ -36,7 +36,7 @@ static const struct ata_port_info ahci_port_info_nolpm = {
 	.port_ops	= &ahci_platform_ops,
 };
 
-static struct scsi_host_template ahci_platform_sht = {
+static const struct scsi_host_template ahci_platform_sht = {
 	AHCI_SHT(DRV_NAME),
 };
 
@@ -56,13 +56,10 @@ static int ahci_probe(struct platform_device *pdev)
 	if (rc)
 		return rc;
 
-	of_property_read_u32(dev->of_node,
-			     "ports-implemented", &hpriv->force_port_map);
-
-	if (of_device_is_compatible(dev->of_node, "hisilicon,hisi-ahci"))
+	if (device_is_compatible(dev, "hisilicon,hisi-ahci"))
 		hpriv->flags |= AHCI_HFLAG_NO_FBS | AHCI_HFLAG_NO_NCQ;
 
-	port = acpi_device_get_match_data(dev);
+	port = device_get_match_data(dev);
 	if (!port)
 		port = &ahci_port_info;
 
@@ -83,12 +80,10 @@ static SIMPLE_DEV_PM_OPS(ahci_pm_ops, ahci_platform_suspend,
 static const struct of_device_id ahci_of_match[] = {
 	{ .compatible = "generic-ahci", },
 	/* Keep the following compatibles for device tree compatibility */
-	{ .compatible = "snps,spear-ahci", },
 	{ .compatible = "ibm,476gtr-ahci", },
-	{ .compatible = "snps,dwc-ahci", },
 	{ .compatible = "hisilicon,hisi-ahci", },
 	{ .compatible = "cavium,octeon-7130-ahci", },
-	{},
+	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, ahci_of_match);
 
diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c
index a330307d3201..0dec1a17e5b1 100644
--- a/drivers/ata/ahci_qoriq.c
+++ b/drivers/ata/ahci_qoriq.c
@@ -6,14 +6,13 @@
  *   Tang Yuantian <Yuantian.Tang@freescale.com>
  */
 
+#include <linux/acpi.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/pm.h>
 #include <linux/ahci_platform.h>
 #include <linux/device.h>
-#include <linux/of_address.h>
 #include <linux/of.h>
-#include <linux/of_device.h>
 #include <linux/platform_device.h>
 #include <linux/libata.h>
 #include "ahci.h"
@@ -76,14 +75,20 @@ static const struct of_device_id ahci_qoriq_of_match[] = {
 	{ .compatible = "fsl,ls1088a-ahci", .data = (void *)AHCI_LS1088A},
 	{ .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A},
 	{ .compatible = "fsl,lx2160a-ahci", .data = (void *)AHCI_LX2160A},
-	{},
+	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);
 
+static const struct acpi_device_id ahci_qoriq_acpi_match[] = {
+	{"NXP0004", .driver_data = (kernel_ulong_t)AHCI_LX2160A},
+	{ }
+};
+MODULE_DEVICE_TABLE(acpi, ahci_qoriq_acpi_match);
+
 static int ahci_qoriq_hardreset(struct ata_link *link, unsigned int *class,
 			  unsigned long deadline)
 {
-	const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
+	const unsigned int *timing = sata_ehc_deb_timing(&link->eh_context);
 	void __iomem *port_mmio = ahci_port_base(link->ap);
 	u32 px_cmd, px_is, px_val;
 	struct ata_port *ap = link->ap;
@@ -96,8 +101,6 @@ static int ahci_qoriq_hardreset(struct ata_link *link, unsigned int *class,
 	int rc;
 	bool ls1021a_workaround = (qoriq_priv->type == AHCI_LS1021A);
 
-	DPRINTK("ENTER\n");
-
 	hpriv->stop_engine(ap);
 
 	/*
@@ -118,7 +121,7 @@ static int ahci_qoriq_hardreset(struct ata_link *link, unsigned int *class,
 
 	/* clear D2H reception area to properly wait for D2H FIS */
 	ata_tf_init(link->device, &tf);
-	tf.command = ATA_BUSY;
+	tf.status = ATA_BUSY;
 	ata_tf_to_fis(&tf, 0, 0, d2h_fis);
 
 	rc = sata_link_hardreset(link, timing, deadline, &online,
@@ -139,14 +142,12 @@ static int ahci_qoriq_hardreset(struct ata_link *link, unsigned int *class,
 
 	if (online)
 		*class = ahci_dev_classify(ap);
-
-	DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
 	return rc;
 }
 
 static struct ata_port_operations ahci_qoriq_ops = {
-	.inherits	= &ahci_ops,
-	.hardreset	= ahci_qoriq_hardreset,
+	.inherits		= &ahci_ops,
+	.reset.hardreset	= ahci_qoriq_hardreset,
 };
 
 static const struct ata_port_info ahci_qoriq_port_info = {
@@ -156,7 +157,7 @@ static const struct ata_port_info ahci_qoriq_port_info = {
 	.port_ops	= &ahci_qoriq_ops,
 };
 
-static struct scsi_host_template ahci_qoriq_sht = {
+static const struct scsi_host_template ahci_qoriq_sht = {
 	AHCI_SHT(DRV_NAME),
 };
 
@@ -255,6 +256,7 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
 static int ahci_qoriq_probe(struct platform_device *pdev)
 {
 	struct device_node *np = pdev->dev.of_node;
+	const struct acpi_device_id *acpi_id;
 	struct device *dev = &pdev->dev;
 	struct ahci_host_priv *hpriv;
 	struct ahci_qoriq_priv *qoriq_priv;
@@ -267,14 +269,18 @@ static int ahci_qoriq_probe(struct platform_device *pdev)
 		return PTR_ERR(hpriv);
 
 	of_id = of_match_node(ahci_qoriq_of_match, np);
-	if (!of_id)
+	acpi_id = acpi_match_device(ahci_qoriq_acpi_match, &pdev->dev);
+	if (!(of_id || acpi_id))
 		return -ENODEV;
 
 	qoriq_priv = devm_kzalloc(dev, sizeof(*qoriq_priv), GFP_KERNEL);
 	if (!qoriq_priv)
 		return -ENOMEM;
 
-	qoriq_priv->type = (enum ahci_qoriq_type)of_id->data;
+	if (of_id)
+		qoriq_priv->type = (unsigned long)of_id->data;
+	else
+		qoriq_priv->type = (enum ahci_qoriq_type)acpi_id->driver_data;
 
 	if (unlikely(!ecc_initialized)) {
 		res = platform_get_resource_byname(pdev,
@@ -288,7 +294,8 @@ static int ahci_qoriq_probe(struct platform_device *pdev)
 		}
 	}
 
-	qoriq_priv->is_dmacoherent = of_dma_is_coherent(np);
+	if (device_get_dma_attr(&pdev->dev) == DEV_DMA_COHERENT)
+		qoriq_priv->is_dmacoherent = true;
 
 	rc = ahci_platform_enable_resources(hpriv);
 	if (rc)
@@ -354,6 +361,7 @@ static struct platform_driver ahci_qoriq_driver = {
 	.driver = {
 		.name = DRV_NAME,
 		.of_match_table = ahci_qoriq_of_match,
+		.acpi_match_table = ahci_qoriq_acpi_match,
 		.pm = &ahci_qoriq_pm_ops,
 	},
 };
diff --git a/drivers/ata/ahci_seattle.c b/drivers/ata/ahci_seattle.c
index ced12705ed9d..3f16c1678402 100644
--- a/drivers/ata/ahci_seattle.c
+++ b/drivers/ata/ahci_seattle.c
@@ -12,7 +12,6 @@
 #include <linux/module.h>
 #include <linux/pm.h>
 #include <linux/device.h>
-#include <linux/of_device.h>
 #include <linux/platform_device.h>
 #include <linux/libata.h>
 #include <linux/ahci_platform.h>
@@ -72,7 +71,7 @@ static const struct ata_port_info ahci_port_seattle_info = {
 	.port_ops	= &ahci_seattle_ops,
 };
 
-static struct scsi_host_template ahci_platform_sht = {
+static const struct scsi_host_template ahci_platform_sht = {
 	AHCI_SHT(DRV_NAME),
 };
 
@@ -132,8 +131,7 @@ static const struct ata_port_info *ahci_seattle_get_port_info(
 	if (!plat_data)
 		return &ahci_port_info;
 
-	plat_data->sgpio_ctrl = devm_ioremap_resource(dev,
-			      platform_get_resource(pdev, IORESOURCE_MEM, 1));
+	plat_data->sgpio_ctrl = devm_platform_ioremap_resource(pdev, 1);
 	if (IS_ERR(plat_data->sgpio_ctrl))
 		return &ahci_port_info;
 
diff --git a/drivers/ata/ahci_st.c b/drivers/ata/ahci_st.c
index c268264c2129..4336c8a6e208 100644
--- a/drivers/ata/ahci_st.c
+++ b/drivers/ata/ahci_st.c
@@ -30,7 +30,6 @@
 #define ST_AHCI_OOBR_CIMAX_SHIFT	0
 
 struct st_ahci_drv_data {
-	struct platform_device *ahci;
 	struct reset_control *pwr;
 	struct reset_control *sw_rst;
 	struct reset_control *pwr_rst;
@@ -138,13 +137,12 @@ static const struct ata_port_info st_ahci_port_info = {
 	.port_ops       = &st_ahci_port_ops,
 };
 
-static struct scsi_host_template ahci_platform_sht = {
+static const struct scsi_host_template ahci_platform_sht = {
 	AHCI_SHT(DRV_NAME),
 };
 
 static int st_ahci_probe(struct platform_device *pdev)
 {
-	struct device *dev = &pdev->dev;
 	struct st_ahci_drv_data *drv_data;
 	struct ahci_host_priv *hpriv;
 	int err;
@@ -168,9 +166,6 @@ static int st_ahci_probe(struct platform_device *pdev)
 
 	st_ahci_configure_oob(hpriv->mmio);
 
-	of_property_read_u32(dev->of_node,
-			     "ports-implemented", &hpriv->force_port_map);
-
 	err = ahci_platform_init_host(pdev, hpriv, &st_ahci_port_info,
 				      &ahci_platform_sht);
 	if (err) {
@@ -181,7 +176,6 @@ static int st_ahci_probe(struct platform_device *pdev)
 	return 0;
 }
 
-#ifdef CONFIG_PM_SLEEP
 static int st_ahci_suspend(struct device *dev)
 {
 	struct ata_host *host = dev_get_drvdata(dev);
@@ -226,21 +220,20 @@ static int st_ahci_resume(struct device *dev)
 
 	return ahci_platform_resume_host(dev);
 }
-#endif
 
-static SIMPLE_DEV_PM_OPS(st_ahci_pm_ops, st_ahci_suspend, st_ahci_resume);
+static DEFINE_SIMPLE_DEV_PM_OPS(st_ahci_pm_ops, st_ahci_suspend, st_ahci_resume);
 
 static const struct of_device_id st_ahci_match[] = {
 	{ .compatible = "st,ahci", },
-	{},
+	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, st_ahci_match);
 
 static struct platform_driver st_ahci_driver = {
 	.driver = {
 		.name = DRV_NAME,
-		.pm = &st_ahci_pm_ops,
-		.of_match_table = of_match_ptr(st_ahci_match),
+		.pm = pm_sleep_ptr(&st_ahci_pm_ops),
+		.of_match_table = st_ahci_match,
 	},
 	.probe = st_ahci_probe,
 	.remove = ata_platform_remove_one,
diff --git a/drivers/ata/ahci_sunxi.c b/drivers/ata/ahci_sunxi.c
index cb69b737cb49..5d4584570ae0 100644
--- a/drivers/ata/ahci_sunxi.c
+++ b/drivers/ata/ahci_sunxi.c
@@ -13,8 +13,8 @@
 #include <linux/clk.h>
 #include <linux/errno.h>
 #include <linux/kernel.h>
+#include <linux/mod_devicetable.h>
 #include <linux/module.h>
-#include <linux/of_device.h>
 #include <linux/platform_device.h>
 #include <linux/regulator/consumer.h>
 #include "ahci.h"
@@ -200,13 +200,13 @@ static void ahci_sunxi_start_engine(struct ata_port *ap)
 }
 
 static const struct ata_port_info ahci_sunxi_port_info = {
-	.flags		= AHCI_FLAG_COMMON | ATA_FLAG_NCQ,
+	.flags		= AHCI_FLAG_COMMON | ATA_FLAG_NCQ | ATA_FLAG_NO_DIPM,
 	.pio_mask	= ATA_PIO4,
 	.udma_mask	= ATA_UDMA6,
 	.port_ops	= &ahci_platform_ops,
 };
 
-static struct scsi_host_template ahci_platform_sht = {
+static const struct scsi_host_template ahci_platform_sht = {
 	AHCI_SHT(DRV_NAME),
 };
 
@@ -286,7 +286,7 @@ static SIMPLE_DEV_PM_OPS(ahci_sunxi_pm_ops, ahci_platform_suspend,
 static const struct of_device_id ahci_sunxi_of_match[] = {
 	{ .compatible = "allwinner,sun4i-a10-ahci", },
 	{ .compatible = "allwinner,sun8i-r40-ahci", },
-	{ },
+	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, ahci_sunxi_of_match);
 
diff --git a/drivers/ata/ahci_tegra.c b/drivers/ata/ahci_tegra.c
index cb55ebc1725b..44584eed6374 100644
--- a/drivers/ata/ahci_tegra.c
+++ b/drivers/ata/ahci_tegra.c
@@ -12,7 +12,7 @@
 #include <linux/errno.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/regulator/consumer.h>
 #include <linux/reset.h>
@@ -59,8 +59,6 @@
 #define T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN		BIT(22)
 
 #define T_SATA0_NVOOB                                   0x114
-#define T_SATA0_NVOOB_COMMA_CNT_MASK                    (0xff << 16)
-#define T_SATA0_NVOOB_COMMA_CNT                         (0x07 << 16)
 #define T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK          (0x3 << 24)
 #define T_SATA0_NVOOB_SQUELCH_FILTER_MODE               (0x1 << 24)
 #define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK        (0x3 << 26)
@@ -154,11 +152,18 @@ struct tegra_ahci_ops {
 	int (*init)(struct ahci_host_priv *hpriv);
 };
 
+struct tegra_ahci_regs {
+	unsigned int nvoob_comma_cnt_mask;
+	unsigned int nvoob_comma_cnt_val;
+};
+
 struct tegra_ahci_soc {
 	const char *const		*supply_names;
 	u32				num_supplies;
 	bool				supports_devslp;
+	bool				has_sata_oob_rst;
 	const struct tegra_ahci_ops	*ops;
+	const struct tegra_ahci_regs	*regs;
 };
 
 struct tegra_ahci_priv {
@@ -240,11 +245,13 @@ static int tegra_ahci_power_on(struct ahci_host_priv *hpriv)
 	if (ret)
 		return ret;
 
-	ret = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_SATA,
-						tegra->sata_clk,
-						tegra->sata_rst);
-	if (ret)
-		goto disable_regulators;
+	if (!tegra->pdev->dev.pm_domain) {
+		ret = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_SATA,
+							tegra->sata_clk,
+							tegra->sata_rst);
+		if (ret)
+			goto disable_regulators;
+	}
 
 	reset_control_assert(tegra->sata_oob_rst);
 	reset_control_assert(tegra->sata_cold_rst);
@@ -261,7 +268,8 @@ static int tegra_ahci_power_on(struct ahci_host_priv *hpriv)
 disable_power:
 	clk_disable_unprepare(tegra->sata_clk);
 
-	tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
+	if (!tegra->pdev->dev.pm_domain)
+		tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
 
 disable_regulators:
 	regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
@@ -280,7 +288,8 @@ static void tegra_ahci_power_off(struct ahci_host_priv *hpriv)
 	reset_control_assert(tegra->sata_cold_rst);
 
 	clk_disable_unprepare(tegra->sata_clk);
-	tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
+	if (!tegra->pdev->dev.pm_domain)
+		tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
 
 	regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
 }
@@ -330,10 +339,10 @@ static int tegra_ahci_controller_init(struct ahci_host_priv *hpriv)
 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA_CFG_PHY_0);
 
 	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB);
-	val &= ~(T_SATA0_NVOOB_COMMA_CNT_MASK |
+	val &= ~(tegra->soc->regs->nvoob_comma_cnt_mask |
 		 T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK |
 		 T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK);
-	val |= (T_SATA0_NVOOB_COMMA_CNT |
+	val |= (tegra->soc->regs->nvoob_comma_cnt_val |
 		T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH |
 		T_SATA0_NVOOB_SQUELCH_FILTER_MODE);
 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB);
@@ -449,15 +458,35 @@ static const struct tegra_ahci_ops tegra124_ahci_ops = {
 	.init = tegra124_ahci_init,
 };
 
+static const struct tegra_ahci_regs tegra124_ahci_regs = {
+	.nvoob_comma_cnt_mask = GENMASK(30, 28),
+	.nvoob_comma_cnt_val = (7 << 28),
+};
+
 static const struct tegra_ahci_soc tegra124_ahci_soc = {
 	.supply_names = tegra124_supply_names,
 	.num_supplies = ARRAY_SIZE(tegra124_supply_names),
 	.supports_devslp = false,
+	.has_sata_oob_rst = true,
 	.ops = &tegra124_ahci_ops,
+	.regs = &tegra124_ahci_regs,
 };
 
 static const struct tegra_ahci_soc tegra210_ahci_soc = {
 	.supports_devslp = false,
+	.has_sata_oob_rst = true,
+	.regs = &tegra124_ahci_regs,
+};
+
+static const struct tegra_ahci_regs tegra186_ahci_regs = {
+	.nvoob_comma_cnt_mask = GENMASK(23, 16),
+	.nvoob_comma_cnt_val = (7 << 16),
+};
+
+static const struct tegra_ahci_soc tegra186_ahci_soc = {
+	.supports_devslp = false,
+	.has_sata_oob_rst = false,
+	.regs = &tegra186_ahci_regs,
 };
 
 static const struct of_device_id tegra_ahci_of_match[] = {
@@ -469,11 +498,15 @@ static const struct of_device_id tegra_ahci_of_match[] = {
 		.compatible = "nvidia,tegra210-ahci",
 		.data = &tegra210_ahci_soc
 	},
+	{
+		.compatible = "nvidia,tegra186-ahci",
+		.data = &tegra186_ahci_soc
+	},
 	{}
 };
 MODULE_DEVICE_TABLE(of, tegra_ahci_of_match);
 
-static struct scsi_host_template ahci_platform_sht = {
+static const struct scsi_host_template ahci_platform_sht = {
 	AHCI_SHT(DRV_NAME),
 };
 
@@ -497,8 +530,7 @@ static int tegra_ahci_probe(struct platform_device *pdev)
 	tegra->pdev = pdev;
 	tegra->soc = of_device_get_match_data(&pdev->dev);
 
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-	tegra->sata_regs = devm_ioremap_resource(&pdev->dev, res);
+	tegra->sata_regs = devm_platform_ioremap_resource(pdev, 1);
 	if (IS_ERR(tegra->sata_regs))
 		return PTR_ERR(tegra->sata_regs);
 
@@ -518,10 +550,13 @@ static int tegra_ahci_probe(struct platform_device *pdev)
 		return PTR_ERR(tegra->sata_rst);
 	}
 
-	tegra->sata_oob_rst = devm_reset_control_get(&pdev->dev, "sata-oob");
-	if (IS_ERR(tegra->sata_oob_rst)) {
-		dev_err(&pdev->dev, "Failed to get sata-oob reset\n");
-		return PTR_ERR(tegra->sata_oob_rst);
+	if (tegra->soc->has_sata_oob_rst) {
+		tegra->sata_oob_rst = devm_reset_control_get(&pdev->dev,
+							     "sata-oob");
+		if (IS_ERR(tegra->sata_oob_rst)) {
+			dev_err(&pdev->dev, "Failed to get sata-oob reset\n");
+			return PTR_ERR(tegra->sata_oob_rst);
+		}
 	}
 
 	tegra->sata_cold_rst = devm_reset_control_get(&pdev->dev, "sata-cold");
diff --git a/drivers/ata/ahci_xgene.c b/drivers/ata/ahci_xgene.c
index 16246c843365..6b8844646fcd 100644
--- a/drivers/ata/ahci_xgene.c
+++ b/drivers/ata/ahci_xgene.c
@@ -13,9 +13,7 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/ahci_platform.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/of_irq.h>
+#include <linux/of.h>
 #include <linux/phy/phy.h>
 #include "ahci.h"
 
@@ -110,9 +108,8 @@ static int xgene_ahci_init_memram(struct xgene_ahci_context *ctx)
  * @timeout : timeout for achieving the value.
  */
 static int xgene_ahci_poll_reg_val(struct ata_port *ap,
-				   void __iomem *reg, unsigned
-				   int val, unsigned long interval,
-				   unsigned long timeout)
+				   void __iomem *reg, unsigned int val,
+				   unsigned int interval, unsigned int timeout)
 {
 	unsigned long deadline;
 	unsigned int tmp;
@@ -193,7 +190,7 @@ static unsigned int xgene_ahci_qc_issue(struct ata_queued_cmd *qc)
 	struct xgene_ahci_context *ctx = hpriv->plat_data;
 	int rc = 0;
 	u32 port_fbs;
-	void *port_mmio = ahci_port_base(ap);
+	void __iomem *port_mmio = ahci_port_base(ap);
 
 	/*
 	 * Write the pmp value to PxFBS.DEV
@@ -237,7 +234,7 @@ static bool xgene_ahci_is_memram_inited(struct xgene_ahci_context *ctx)
  * does not support DEVSLP.
  */
 static unsigned int xgene_ahci_read_id(struct ata_device *dev,
-				       struct ata_taskfile *tf, u16 *id)
+				       struct ata_taskfile *tf, __le16 *id)
 {
 	u32 err_mask;
 
@@ -350,7 +347,7 @@ static void xgene_ahci_set_phy_cfg(struct xgene_ahci_context *ctx, int channel)
 static int xgene_ahci_do_hardreset(struct ata_link *link,
 				   unsigned long deadline, bool *online)
 {
-	const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
+	const unsigned int *timing = sata_ehc_deb_timing(&link->eh_context);
 	struct ata_port *ap = link->ap;
 	struct ahci_host_priv *hpriv = ap->host->private_data;
 	struct xgene_ahci_context *ctx = hpriv->plat_data;
@@ -365,7 +362,7 @@ static int xgene_ahci_do_hardreset(struct ata_link *link,
 	do {
 		/* clear D2H reception area to properly wait for D2H FIS */
 		ata_tf_init(link->device, &tf);
-		tf.command = ATA_BUSY;
+		tf.status = ATA_BUSY;
 		ata_tf_to_fis(&tf, 0, 0, d2h_fis);
 		rc = sata_link_hardreset(link, timing, deadline, online,
 				 ahci_check_ready);
@@ -453,8 +450,7 @@ static int xgene_ahci_pmp_softreset(struct ata_link *link, unsigned int *class,
 {
 	int pmp = sata_srst_pmp(link);
 	struct ata_port *ap = link->ap;
-	u32 rc;
-	void *port_mmio = ahci_port_base(ap);
+	void __iomem *port_mmio = ahci_port_base(ap);
 	u32 port_fbs;
 
 	/*
@@ -466,9 +462,7 @@ static int xgene_ahci_pmp_softreset(struct ata_link *link, unsigned int *class,
 	port_fbs |= pmp << PORT_FBS_DEV_OFFSET;
 	writel(port_fbs, port_mmio + PORT_FBS);
 
-	rc = ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
-
-	return rc;
+	return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
 }
 
 /**
@@ -499,11 +493,11 @@ static int xgene_ahci_softreset(struct ata_link *link, unsigned int *class,
 	struct ata_port *ap = link->ap;
 	struct ahci_host_priv *hpriv = ap->host->private_data;
 	struct xgene_ahci_context *ctx = hpriv->plat_data;
-	void *port_mmio = ahci_port_base(ap);
+	void __iomem *port_mmio = ahci_port_base(ap);
 	u32 port_fbs;
 	u32 port_fbs_save;
 	u32 retry = 1;
-	u32 rc;
+	int rc;
 
 	port_fbs_save = readl(port_mmio + PORT_FBS);
 
@@ -537,7 +531,7 @@ softreset_retry:
 
 /**
  * xgene_ahci_handle_broken_edge_irq - Handle the broken irq.
- * @ata_host: Host that recieved the irq
+ * @host: Host that received the irq
  * @irq_masked: HOST_IRQ_STAT value
  *
  * For hardware with broken edge trigger latch
@@ -588,8 +582,6 @@ static irqreturn_t xgene_ahci_irq_intr(int irq, void *dev_instance)
 	void __iomem *mmio;
 	u32 irq_stat, irq_masked;
 
-	VPRINTK("ENTER\n");
-
 	hpriv = host->private_data;
 	mmio = hpriv->mmio;
 
@@ -612,19 +604,17 @@ static irqreturn_t xgene_ahci_irq_intr(int irq, void *dev_instance)
 
 	spin_unlock(&host->lock);
 
-	VPRINTK("EXIT\n");
-
 	return IRQ_RETVAL(rc);
 }
 
 static struct ata_port_operations xgene_ahci_v1_ops = {
 	.inherits = &ahci_ops,
 	.host_stop = xgene_ahci_host_stop,
-	.hardreset = xgene_ahci_hardreset,
+	.reset.hardreset = xgene_ahci_hardreset,
+	.reset.softreset = xgene_ahci_softreset,
+	.pmp_reset.softreset = xgene_ahci_pmp_softreset,
 	.read_id = xgene_ahci_read_id,
 	.qc_issue = xgene_ahci_qc_issue,
-	.softreset = xgene_ahci_softreset,
-	.pmp_softreset = xgene_ahci_pmp_softreset
 };
 
 static const struct ata_port_info xgene_ahci_v1_port_info = {
@@ -637,7 +627,7 @@ static const struct ata_port_info xgene_ahci_v1_port_info = {
 static struct ata_port_operations xgene_ahci_v2_ops = {
 	.inherits = &ahci_ops,
 	.host_stop = xgene_ahci_host_stop,
-	.hardreset = xgene_ahci_hardreset,
+	.reset.hardreset = xgene_ahci_hardreset,
 	.read_id = xgene_ahci_read_id,
 };
 
@@ -714,7 +704,7 @@ static int xgene_ahci_mux_select(struct xgene_ahci_context *ctx)
 	return val & CFG_SATA_ENET_SELECT_MASK ? -1 : 0;
 }
 
-static struct scsi_host_template ahci_platform_sht = {
+static const struct scsi_host_template ahci_platform_sht = {
 	AHCI_SHT(DRV_NAME),
 };
 
@@ -730,7 +720,7 @@ MODULE_DEVICE_TABLE(acpi, xgene_ahci_acpi_match);
 static const struct of_device_id xgene_ahci_of_match[] = {
 	{.compatible = "apm,xgene-ahci", .data = (void *) XGENE_AHCI_V1},
 	{.compatible = "apm,xgene-ahci-v2", .data = (void *) XGENE_AHCI_V2},
-	{},
+	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, xgene_ahci_of_match);
 
@@ -740,7 +730,6 @@ static int xgene_ahci_probe(struct platform_device *pdev)
 	struct ahci_host_priv *hpriv;
 	struct xgene_ahci_context *ctx;
 	struct resource *res;
-	const struct of_device_id *of_devid;
 	enum xgene_ahci_version version = XGENE_AHCI_V1;
 	const struct ata_port_info *ppi[] = { &xgene_ahci_v1_port_info,
 					      &xgene_ahci_v2_port_info };
@@ -759,20 +748,17 @@ static int xgene_ahci_probe(struct platform_device *pdev)
 	ctx->dev = dev;
 
 	/* Retrieve the IP core resource */
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-	ctx->csr_core = devm_ioremap_resource(dev, res);
+	ctx->csr_core = devm_platform_ioremap_resource(pdev, 1);
 	if (IS_ERR(ctx->csr_core))
 		return PTR_ERR(ctx->csr_core);
 
 	/* Retrieve the IP diagnostic resource */
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
-	ctx->csr_diag = devm_ioremap_resource(dev, res);
+	ctx->csr_diag = devm_platform_ioremap_resource(pdev, 2);
 	if (IS_ERR(ctx->csr_diag))
 		return PTR_ERR(ctx->csr_diag);
 
 	/* Retrieve the IP AXI resource */
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
-	ctx->csr_axi = devm_ioremap_resource(dev, res);
+	ctx->csr_axi = devm_platform_ioremap_resource(pdev, 3);
 	if (IS_ERR(ctx->csr_axi))
 		return PTR_ERR(ctx->csr_axi);
 
@@ -786,10 +772,8 @@ static int xgene_ahci_probe(struct platform_device *pdev)
 		ctx->csr_mux = csr;
 	}
 
-	of_devid = of_match_device(xgene_ahci_of_match, dev);
-	if (of_devid) {
-		if (of_devid->data)
-			version = (enum xgene_ahci_version) of_devid->data;
+	if (dev->of_node) {
+		version = (enum xgene_ahci_version)of_device_get_match_data(dev);
 	}
 #ifdef CONFIG_ACPI
 	else {
diff --git a/drivers/ata/ata_generic.c b/drivers/ata/ata_generic.c
index 9ff545ce8da3..e70b6c089cf1 100644
--- a/drivers/ata/ata_generic.c
+++ b/drivers/ata/ata_generic.c
@@ -95,7 +95,7 @@ static int generic_set_mode(struct ata_link *link, struct ata_device **unused)
 	return 0;
 }
 
-static struct scsi_host_template generic_sht = {
+static const struct scsi_host_template generic_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
@@ -151,7 +151,7 @@ static int is_intel_ider(struct pci_dev *dev)
 }
 
 /**
- *	ata_generic_init		-	attach generic IDE
+ *	ata_generic_init_one		-	attach generic IDE
  *	@dev: PCI device found
  *	@id: match entry
  *
@@ -209,7 +209,7 @@ static int ata_generic_init_one(struct pci_dev *dev, const struct pci_device_id
 	return ata_pci_bmdma_init_one(dev, ppi, &generic_sht, (void *)id, 0);
 }
 
-static struct pci_device_id ata_generic[] = {
+static const struct pci_device_id ata_generic[] = {
 	{ PCI_DEVICE(PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_SAMURAI_IDE), },
 	{ PCI_DEVICE(PCI_VENDOR_ID_HOLTEK, PCI_DEVICE_ID_HOLTEK_6565), },
 	{ PCI_DEVICE(PCI_VENDOR_ID_UMC,    PCI_DEVICE_ID_UMC_UM8673F), },
diff --git a/drivers/ata/ata_piix.c b/drivers/ata/ata_piix.c
index 3ca7720e7d8f..495fa096dd65 100644
--- a/drivers/ata/ata_piix.c
+++ b/drivers/ata/ata_piix.c
@@ -77,6 +77,7 @@
 #include <scsi/scsi_host.h>
 #include <linux/libata.h>
 #include <linux/dmi.h>
+#include <trace/events/libata.h>
 
 #define DRV_NAME	"ata_piix"
 #define DRV_VERSION	"2.13"
@@ -816,10 +817,15 @@ static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
 
 static bool piix_irq_check(struct ata_port *ap)
 {
+	unsigned char host_stat;
+
 	if (unlikely(!ap->ioaddr.bmdma_addr))
 		return false;
 
-	return ap->ops->bmdma_status(ap) & ATA_DMA_INTR;
+	host_stat = ap->ops->bmdma_status(ap);
+	trace_ata_bmdma_status(ap, host_stat);
+
+	return host_stat & ATA_DMA_INTR;
 }
 
 #ifdef CONFIG_PM_SLEEP
@@ -987,11 +993,8 @@ static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
 {
 	struct ata_host *host = pci_get_drvdata(pdev);
 	unsigned long flags;
-	int rc = 0;
 
-	rc = ata_host_suspend(host, mesg);
-	if (rc)
-		return rc;
+	ata_host_suspend(host, mesg);
 
 	/* Some braindamaged ACPI suspend implementations expect the
 	 * controller to be awake on entry; otherwise, it burns cpu
@@ -1056,7 +1059,7 @@ static u8 piix_vmw_bmdma_status(struct ata_port *ap)
 	return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
 }
 
-static struct scsi_host_template piix_sht = {
+static const struct scsi_host_template piix_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
@@ -1071,7 +1074,7 @@ static struct ata_port_operations piix_pata_ops = {
 	.cable_detect		= ata_cable_40wire,
 	.set_piomode		= piix_set_piomode,
 	.set_dmamode		= piix_set_dmamode,
-	.prereset		= piix_pata_prereset,
+	.reset.prereset		= piix_pata_prereset,
 };
 
 static struct ata_port_operations piix_vmw_ops = {
@@ -1085,19 +1088,22 @@ static struct ata_port_operations ich_pata_ops = {
 	.set_dmamode		= ich_set_dmamode,
 };
 
-static struct device_attribute *piix_sidpr_shost_attrs[] = {
-	&dev_attr_link_power_management_policy,
+static struct attribute *piix_sidpr_shost_attrs[] = {
+	&dev_attr_link_power_management_supported.attr,
+	&dev_attr_link_power_management_policy.attr,
 	NULL
 };
 
-static struct scsi_host_template piix_sidpr_sht = {
+ATTRIBUTE_GROUPS(piix_sidpr_shost);
+
+static const struct scsi_host_template piix_sidpr_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
-	.shost_attrs		= piix_sidpr_shost_attrs,
+	.shost_groups		= piix_sidpr_shost_groups,
 };
 
 static struct ata_port_operations piix_sidpr_sata_ops = {
 	.inherits		= &piix_sata_ops,
-	.hardreset		= sata_std_hardreset,
+	.reset.hardreset	= sata_std_hardreset,
 	.scr_read		= piix_sidpr_scr_read,
 	.scr_write		= piix_sidpr_scr_write,
 	.set_lpm		= piix_sidpr_set_lpm,
@@ -1343,7 +1349,6 @@ static void piix_init_pcs(struct ata_host *host,
 	new_pcs = pcs | map_db->port_enable;
 
 	if (new_pcs != pcs) {
-		DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
 		pci_write_config_word(pdev, ICH5_PCS, new_pcs);
 		msleep(150);
 	}
@@ -1442,7 +1447,6 @@ static int piix_init_sidpr(struct ata_host *host)
 		if (hpriv->map[i] == IDE)
 			return 0;
 
-	/* is it blacklisted? */
 	if (piix_no_sidpr(host))
 		return 0;
 
@@ -1641,7 +1645,7 @@ static int piix_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 	struct device *dev = &pdev->dev;
 	struct ata_port_info port_info[2];
 	const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
-	struct scsi_host_template *sht = &piix_sht;
+	const struct scsi_host_template *sht = &piix_sht;
 	unsigned long port_flags;
 	struct ata_host *host;
 	struct piix_host_priv *hpriv;
@@ -1722,7 +1726,7 @@ static int piix_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 	 * message-signalled interrupts currently).
 	 */
 	if (port_flags & PIIX_FLAG_CHECKINTR)
-		pci_intx(pdev, 1);
+		pcim_intx(pdev, 1);
 
 	if (piix_check_450nx_errata(pdev)) {
 		/* This writes into the master table but it does not
@@ -1767,14 +1771,12 @@ static int __init piix_init(void)
 {
 	int rc;
 
-	DPRINTK("pci_register_driver\n");
 	rc = pci_register_driver(&piix_pci_driver);
 	if (rc)
 		return rc;
 
 	in_module_init = 0;
 
-	DPRINTK("done\n");
 	return 0;
 }
 
diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c
index ea5bf5f4cbed..c79abdfcd7a9 100644
--- a/drivers/ata/libahci.c
+++ b/drivers/ata/libahci.c
@@ -16,6 +16,7 @@
  * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
  */
 
+#include <linux/bitops.h>
 #include <linux/kernel.h>
 #include <linux/gfp.h>
 #include <linux/module.h>
@@ -54,7 +55,8 @@ static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
 
 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
-static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
+static void ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
+static void ahci_qc_ncq_fill_rtf(struct ata_port *ap, u64 done_mask);
 static int ahci_port_start(struct ata_port *ap);
 static void ahci_port_stop(struct ata_port *ap);
 static enum ata_completion_errors ahci_qc_prep(struct ata_queued_cmd *qc);
@@ -108,27 +110,47 @@ static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
 		   ahci_read_em_buffer, ahci_store_em_buffer);
 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
 
-struct device_attribute *ahci_shost_attrs[] = {
-	&dev_attr_link_power_management_policy,
-	&dev_attr_em_message_type,
-	&dev_attr_em_message,
-	&dev_attr_ahci_host_caps,
-	&dev_attr_ahci_host_cap2,
-	&dev_attr_ahci_host_version,
-	&dev_attr_ahci_port_cmd,
-	&dev_attr_em_buffer,
-	&dev_attr_em_message_supported,
+static struct attribute *ahci_shost_attrs[] = {
+	&dev_attr_link_power_management_supported.attr,
+	&dev_attr_link_power_management_policy.attr,
+	&dev_attr_em_message_type.attr,
+	&dev_attr_em_message.attr,
+	&dev_attr_ahci_host_caps.attr,
+	&dev_attr_ahci_host_cap2.attr,
+	&dev_attr_ahci_host_version.attr,
+	&dev_attr_ahci_port_cmd.attr,
+	&dev_attr_em_buffer.attr,
+	&dev_attr_em_message_supported.attr,
 	NULL
 };
-EXPORT_SYMBOL_GPL(ahci_shost_attrs);
 
-struct device_attribute *ahci_sdev_attrs[] = {
-	&dev_attr_sw_activity,
-	&dev_attr_unload_heads,
-	&dev_attr_ncq_prio_enable,
+static const struct attribute_group ahci_shost_attr_group = {
+	.attrs = ahci_shost_attrs
+};
+
+const struct attribute_group *ahci_shost_groups[] = {
+	&ahci_shost_attr_group,
+	NULL
+};
+EXPORT_SYMBOL_GPL(ahci_shost_groups);
+
+static struct attribute *ahci_sdev_attrs[] = {
+	&dev_attr_sw_activity.attr,
+	&dev_attr_unload_heads.attr,
+	&dev_attr_ncq_prio_supported.attr,
+	&dev_attr_ncq_prio_enable.attr,
+	NULL
+};
+
+static const struct attribute_group ahci_sdev_attr_group = {
+	.attrs = ahci_sdev_attrs
+};
+
+const struct attribute_group *ahci_sdev_groups[] = {
+	&ahci_sdev_attr_group,
 	NULL
 };
-EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
+EXPORT_SYMBOL_GPL(ahci_sdev_groups);
 
 struct ata_port_operations ahci_ops = {
 	.inherits		= &sata_pmp_port_ops,
@@ -137,13 +159,14 @@ struct ata_port_operations ahci_ops = {
 	.qc_prep		= ahci_qc_prep,
 	.qc_issue		= ahci_qc_issue,
 	.qc_fill_rtf		= ahci_qc_fill_rtf,
+	.qc_ncq_fill_rtf	= ahci_qc_ncq_fill_rtf,
 
 	.freeze			= ahci_freeze,
 	.thaw			= ahci_thaw,
-	.softreset		= ahci_softreset,
-	.hardreset		= ahci_hardreset,
-	.postreset		= ahci_postreset,
-	.pmp_softreset		= ahci_softreset,
+	.reset.softreset	= ahci_softreset,
+	.reset.hardreset	= ahci_hardreset,
+	.reset.postreset	= ahci_postreset,
+	.pmp_reset.softreset	= ahci_softreset,
 	.error_handler		= ahci_error_handler,
 	.post_internal_cmd	= ahci_post_internal_cmd,
 	.dev_config		= ahci_dev_config,
@@ -170,7 +193,7 @@ EXPORT_SYMBOL_GPL(ahci_ops);
 
 struct ata_port_operations ahci_pmp_retry_srst_ops = {
 	.inherits		= &ahci_ops,
-	.softreset		= ahci_pmp_retry_softreset,
+	.reset.softreset	= ahci_pmp_retry_softreset,
 };
 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
 
@@ -424,17 +447,28 @@ static ssize_t ahci_show_em_supported(struct device *dev,
 void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
 {
 	void __iomem *mmio = hpriv->mmio;
-	u32 cap, cap2, vers, port_map;
+	void __iomem *port_mmio;
+	unsigned long port_map;
+	u32 cap, cap2, vers;
 	int i;
 
 	/* make sure AHCI mode is enabled before accessing CAP */
 	ahci_enable_ahci(mmio);
 
-	/* Values prefixed with saved_ are written back to host after
-	 * reset.  Values without are used for driver operation.
+	/*
+	 * Values prefixed with saved_ are written back to the HBA and ports
+	 * registers after reset. Values without are used for driver operation.
+	 */
+
+	/*
+	 * Override HW-init HBA capability fields with the platform-specific
+	 * values. The rest of the HBA capabilities are defined as Read-only
+	 * and can't be modified in CSR anyway.
 	 */
-	hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
-	hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
+	cap = readl(mmio + HOST_CAP);
+	if (hpriv->saved_cap)
+		cap = (cap & ~(HOST_CAP_SSS | HOST_CAP_MPS)) | hpriv->saved_cap;
+	hpriv->saved_cap = cap;
 
 	/* CAP2 register is only defined for AHCI 1.2 and later */
 	vers = readl(mmio + HOST_VERSION);
@@ -493,15 +527,24 @@ void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
 		cap |= HOST_CAP_ALPM;
 	}
 
-	if (hpriv->force_port_map && port_map != hpriv->force_port_map) {
-		dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
-			 port_map, hpriv->force_port_map);
-		port_map = hpriv->force_port_map;
+	if ((cap & HOST_CAP_SXS) && (hpriv->flags & AHCI_HFLAG_NO_SXS)) {
+		dev_info(dev, "controller does not support SXS, disabling CAP_SXS\n");
+		cap &= ~HOST_CAP_SXS;
+	}
+
+	/* Override the HBA ports mapping if the platform needs it */
+	port_map = readl(mmio + HOST_PORTS_IMPL);
+	if (hpriv->saved_port_map && port_map != hpriv->saved_port_map) {
+		dev_info(dev, "forcing port_map 0x%lx -> 0x%x\n",
+			 port_map, hpriv->saved_port_map);
+		port_map = hpriv->saved_port_map;
+	} else {
 		hpriv->saved_port_map = port_map;
 	}
 
+	/* mask_port_map not set means that all ports are available */
 	if (hpriv->mask_port_map) {
-		dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
+		dev_warn(dev, "masking port_map 0x%lx -> 0x%lx\n",
 			port_map,
 			port_map & hpriv->mask_port_map);
 		port_map &= hpriv->mask_port_map;
@@ -520,7 +563,7 @@ void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
 		 */
 		if (map_ports > ahci_nr_ports(cap)) {
 			dev_warn(dev,
-				 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
+				 "implemented port map (0x%lx) contains more ports than nr_ports (%u), using nr_ports\n",
 				 port_map, ahci_nr_ports(cap));
 			port_map = 0;
 		}
@@ -529,16 +572,30 @@ void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
 	/* fabricate port_map from cap.nr_ports for < AHCI 1.3 */
 	if (!port_map && vers < 0x10300) {
 		port_map = (1 << ahci_nr_ports(cap)) - 1;
-		dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
+		dev_warn(dev, "forcing PORTS_IMPL to 0x%lx\n", port_map);
 
 		/* write the fixed up value to the PI register */
 		hpriv->saved_port_map = port_map;
 	}
 
+	/*
+	 * Preserve the ports capabilities defined by the platform. Note there
+	 * is no need in storing the rest of the P#.CMD fields since they are
+	 * volatile.
+	 */
+	for_each_set_bit(i, &port_map, AHCI_MAX_PORTS) {
+		if (hpriv->saved_port_cap[i])
+			continue;
+
+		port_mmio = __ahci_port_base(hpriv, i);
+		hpriv->saved_port_cap[i] =
+			readl(port_mmio + PORT_CMD) & PORT_CMD_CAP;
+	}
+
 	/* record values to use during operation */
 	hpriv->cap = cap;
 	hpriv->cap2 = cap2;
-	hpriv->version = readl(mmio + HOST_VERSION);
+	hpriv->version = vers;
 	hpriv->port_map = port_map;
 
 	if (!hpriv->start_engine)
@@ -564,13 +621,21 @@ EXPORT_SYMBOL_GPL(ahci_save_initial_config);
 static void ahci_restore_initial_config(struct ata_host *host)
 {
 	struct ahci_host_priv *hpriv = host->private_data;
+	unsigned long port_map = hpriv->port_map;
 	void __iomem *mmio = hpriv->mmio;
+	void __iomem *port_mmio;
+	int i;
 
 	writel(hpriv->saved_cap, mmio + HOST_CAP);
 	if (hpriv->saved_cap2)
 		writel(hpriv->saved_cap2, mmio + HOST_CAP2);
 	writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
 	(void) readl(mmio + HOST_PORTS_IMPL);	/* flush */
+
+	for_each_set_bit(i, &port_map, AHCI_MAX_PORTS) {
+		port_mmio = __ahci_port_base(hpriv, i);
+		writel(hpriv->saved_port_cap[i], port_mmio + PORT_CMD);
+	}
 }
 
 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
@@ -912,44 +977,43 @@ int ahci_reset_controller(struct ata_host *host)
 	void __iomem *mmio = hpriv->mmio;
 	u32 tmp;
 
-	/* we must be in AHCI mode, before using anything
-	 * AHCI-specific, such as HOST_RESET.
+	/*
+	 * We must be in AHCI mode, before using anything AHCI-specific, such
+	 * as HOST_RESET.
 	 */
 	ahci_enable_ahci(mmio);
 
-	/* global controller reset */
-	if (!ahci_skip_host_reset) {
-		tmp = readl(mmio + HOST_CTL);
-		if ((tmp & HOST_RESET) == 0) {
-			writel(tmp | HOST_RESET, mmio + HOST_CTL);
-			readl(mmio + HOST_CTL); /* flush */
-		}
+	/* Global controller reset */
+	if (ahci_skip_host_reset) {
+		dev_info(host->dev, "Skipping global host reset\n");
+		return 0;
+	}
 
-		/*
-		 * to perform host reset, OS should set HOST_RESET
-		 * and poll until this bit is read to be "0".
-		 * reset must complete within 1 second, or
-		 * the hardware should be considered fried.
-		 */
-		tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
-					HOST_RESET, 10, 1000);
+	tmp = readl(mmio + HOST_CTL);
+	if (!(tmp & HOST_RESET)) {
+		writel(tmp | HOST_RESET, mmio + HOST_CTL);
+		readl(mmio + HOST_CTL); /* flush */
+	}
 
-		if (tmp & HOST_RESET) {
-			dev_err(host->dev, "controller reset failed (0x%x)\n",
-				tmp);
-			return -EIO;
-		}
+	/*
+	 * To perform host reset, OS should set HOST_RESET and poll until this
+	 * bit is read to be "0". Reset must complete within 1 second, or the
+	 * hardware should be considered fried.
+	 */
+	tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
+				HOST_RESET, 10, 1000);
+	if (tmp & HOST_RESET) {
+		dev_err(host->dev, "Controller reset failed (0x%x)\n",
+			tmp);
+		return -EIO;
+	}
 
-		/* turn on AHCI mode */
-		ahci_enable_ahci(mmio);
+	/* Turn on AHCI mode */
+	ahci_enable_ahci(mmio);
 
-		/* Some registers might be cleared on reset.  Restore
-		 * initial values.
-		 */
-		if (!(hpriv->flags & AHCI_HFLAG_NO_WRITE_TO_RO))
-			ahci_restore_initial_config(host);
-	} else
-		dev_info(host->dev, "skipping global host reset\n");
+	/* Some registers might be cleared on reset. Restore initial values. */
+	if (!(hpriv->flags & AHCI_HFLAG_NO_WRITE_TO_RO))
+		ahci_restore_initial_config(host);
 
 	return 0;
 }
@@ -971,7 +1035,7 @@ static void ahci_sw_activity(struct ata_link *link)
 
 static void ahci_sw_activity_blink(struct timer_list *t)
 {
-	struct ahci_em_priv *emp = from_timer(emp, t, timer);
+	struct ahci_em_priv *emp = timer_container_of(emp, t, timer);
 	struct ata_link *link = emp->link;
 	struct ata_port *ap = link->ap;
 
@@ -1194,37 +1258,39 @@ static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
 	return sprintf(buf, "%d\n", emp->blink_policy);
 }
 
-static void ahci_port_init(struct device *dev, struct ata_port *ap,
-			   int port_no, void __iomem *mmio,
-			   void __iomem *port_mmio)
+static void ahci_port_clear_pending_irq(struct ata_port *ap)
 {
 	struct ahci_host_priv *hpriv = ap->host->private_data;
-	const char *emsg = NULL;
-	int rc;
+	void __iomem *port_mmio = ahci_port_base(ap);
 	u32 tmp;
 
-	/* make sure port is not active */
-	rc = ahci_deinit_port(ap, &emsg);
-	if (rc)
-		dev_warn(dev, "%s (%d)\n", emsg, rc);
-
 	/* clear SError */
 	tmp = readl(port_mmio + PORT_SCR_ERR);
-	VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
+	dev_dbg(ap->host->dev, "PORT_SCR_ERR 0x%x\n", tmp);
 	writel(tmp, port_mmio + PORT_SCR_ERR);
 
 	/* clear port IRQ */
 	tmp = readl(port_mmio + PORT_IRQ_STAT);
-	VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
+	dev_dbg(ap->host->dev, "PORT_IRQ_STAT 0x%x\n", tmp);
 	if (tmp)
 		writel(tmp, port_mmio + PORT_IRQ_STAT);
 
-	writel(1 << port_no, mmio + HOST_IRQ_STAT);
+	writel(1 << ap->port_no, hpriv->mmio + HOST_IRQ_STAT);
+}
 
-	/* mark esata ports */
-	tmp = readl(port_mmio + PORT_CMD);
-	if ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS))
-		ap->pflags |= ATA_PFLAG_EXTERNAL;
+static void ahci_port_init(struct device *dev, struct ata_port *ap,
+			   int port_no, void __iomem *mmio,
+			   void __iomem *port_mmio)
+{
+	const char *emsg = NULL;
+	int rc;
+
+	/* make sure port is not active */
+	rc = ahci_deinit_port(ap, &emsg);
+	if (rc)
+		dev_warn(dev, "%s (%d)\n", emsg, rc);
+
+	ahci_port_clear_pending_irq(ap);
 }
 
 void ahci_init_controller(struct ata_host *host)
@@ -1246,10 +1312,10 @@ void ahci_init_controller(struct ata_host *host)
 	}
 
 	tmp = readl(mmio + HOST_CTL);
-	VPRINTK("HOST_CTL 0x%x\n", tmp);
+	dev_dbg(host->dev, "HOST_CTL 0x%x\n", tmp);
 	writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
 	tmp = readl(mmio + HOST_CTL);
-	VPRINTK("HOST_CTL 0x%x\n", tmp);
+	dev_dbg(host->dev, "HOST_CTL 0x%x\n", tmp);
 }
 EXPORT_SYMBOL_GPL(ahci_init_controller);
 
@@ -1257,6 +1323,10 @@ static void ahci_dev_config(struct ata_device *dev)
 {
 	struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
 
+	if ((dev->class == ATA_DEV_ATAPI) &&
+	    (hpriv->flags & AHCI_HFLAG_ATAPI_DMA_QUIRK))
+		dev->quirks |= ATA_QUIRK_ATAPI_MOD16_DMA;
+
 	if (hpriv->flags & AHCI_HFLAG_SECT255) {
 		dev->max_sectors = 255;
 		ata_dev_info(dev,
@@ -1276,7 +1346,7 @@ unsigned int ahci_dev_classify(struct ata_port *ap)
 	tf.lbal		= (tmp >> 8)	& 0xff;
 	tf.nsect	= (tmp)		& 0xff;
 
-	return ata_dev_classify(&tf);
+	return ata_port_classify(ap, &tf);
 }
 EXPORT_SYMBOL_GPL(ahci_dev_classify);
 
@@ -1341,7 +1411,7 @@ EXPORT_SYMBOL_GPL(ahci_kick_engine);
 
 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
 				struct ata_taskfile *tf, int is_cmd, u16 flags,
-				unsigned long timeout_msec)
+				unsigned int timeout_msec)
 {
 	const u32 cmd_fis_len = 5; /* five dwords */
 	struct ahci_port_priv *pp = ap->private_data;
@@ -1386,13 +1456,12 @@ int ahci_do_softreset(struct ata_link *link, unsigned int *class,
 	struct ahci_host_priv *hpriv = ap->host->private_data;
 	struct ahci_port_priv *pp = ap->private_data;
 	const char *reason = NULL;
-	unsigned long now, msecs;
+	unsigned long now;
+	unsigned int msecs;
 	struct ata_taskfile tf;
 	bool fbs_disabled = false;
 	int rc;
 
-	DPRINTK("ENTER\n");
-
 	/* prepare for SRST (AHCI-1.1 10.4.1) */
 	rc = ahci_kick_engine(ap);
 	if (rc && rc != -EOPNOTSUPP)
@@ -1452,7 +1521,6 @@ int ahci_do_softreset(struct ata_link *link, unsigned int *class,
 	if (fbs_disabled)
 		ahci_enable_fbs(ap);
 
-	DPRINTK("EXIT, class=%u\n", *class);
 	return 0;
 
  fail:
@@ -1474,8 +1542,6 @@ static int ahci_softreset(struct ata_link *link, unsigned int *class,
 {
 	int pmp = sata_srst_pmp(link);
 
-	DPRINTK("ENTER\n");
-
 	return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
 }
 EXPORT_SYMBOL_GPL(ahci_do_softreset);
@@ -1505,8 +1571,6 @@ static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
 	int rc;
 	u32 irq_sts;
 
-	DPRINTK("ENTER\n");
-
 	rc = ahci_do_softreset(link, class, pmp, deadline,
 			       ahci_bad_pmp_check_ready);
 
@@ -1532,7 +1596,7 @@ static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
 int ahci_do_hardreset(struct ata_link *link, unsigned int *class,
 		      unsigned long deadline, bool *online)
 {
-	const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
+	const unsigned int *timing = sata_ehc_deb_timing(&link->eh_context);
 	struct ata_port *ap = link->ap;
 	struct ahci_port_priv *pp = ap->private_data;
 	struct ahci_host_priv *hpriv = ap->host->private_data;
@@ -1540,15 +1604,15 @@ int ahci_do_hardreset(struct ata_link *link, unsigned int *class,
 	struct ata_taskfile tf;
 	int rc;
 
-	DPRINTK("ENTER\n");
-
 	hpriv->stop_engine(ap);
 
 	/* clear D2H reception area to properly wait for D2H FIS */
 	ata_tf_init(link->device, &tf);
-	tf.command = ATA_BUSY;
+	tf.status = ATA_BUSY;
 	ata_tf_to_fis(&tf, 0, 0, d2h_fis);
 
+	ahci_port_clear_pending_irq(ap);
+
 	rc = sata_link_hardreset(link, timing, deadline, online,
 				 ahci_check_ready);
 
@@ -1557,7 +1621,6 @@ int ahci_do_hardreset(struct ata_link *link, unsigned int *class,
 	if (*online)
 		*class = ahci_dev_classify(ap);
 
-	DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
 	return rc;
 }
 EXPORT_SYMBOL_GPL(ahci_do_hardreset);
@@ -1596,8 +1659,6 @@ static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
 	struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
 	unsigned int si;
 
-	VPRINTK("ENTER\n");
-
 	/*
 	 * Next, the S/G list.
 	 */
@@ -1671,7 +1732,6 @@ static void ahci_fbs_dec_intr(struct ata_port *ap)
 	u32 fbs = readl(port_mmio + PORT_FBS);
 	int retries = 3;
 
-	DPRINTK("ENTER\n");
 	BUG_ON(!pp->fbs_enabled);
 
 	/* time to wait for DEC is not specified by AHCI spec,
@@ -1799,18 +1859,47 @@ static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
 		ata_port_abort(ap);
 }
 
-static void ahci_handle_port_interrupt(struct ata_port *ap,
-				       void __iomem *port_mmio, u32 status)
+static void ahci_qc_complete(struct ata_port *ap, void __iomem *port_mmio)
 {
 	struct ata_eh_info *ehi = &ap->link.eh_info;
 	struct ahci_port_priv *pp = ap->private_data;
-	struct ahci_host_priv *hpriv = ap->host->private_data;
-	int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
 	u32 qc_active = 0;
 	int rc;
 
+	/*
+	 * pp->active_link is not reliable once FBS is enabled, both
+	 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
+	 * NCQ and non-NCQ commands may be in flight at the same time.
+	 */
+	if (pp->fbs_enabled) {
+		if (ap->qc_active) {
+			qc_active = readl(port_mmio + PORT_SCR_ACT);
+			qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
+		}
+	} else {
+		/* pp->active_link is valid iff any command is in flight */
+		if (ap->qc_active && pp->active_link->sactive)
+			qc_active = readl(port_mmio + PORT_SCR_ACT);
+		else
+			qc_active = readl(port_mmio + PORT_CMD_ISSUE);
+	}
+
+	rc = ata_qc_complete_multiple(ap, qc_active);
+	if (unlikely(rc < 0 && !(ap->pflags & ATA_PFLAG_RESETTING))) {
+		ehi->err_mask |= AC_ERR_HSM;
+		ehi->action |= ATA_EH_RESET;
+		ata_port_freeze(ap);
+	}
+}
+
+static void ahci_handle_port_interrupt(struct ata_port *ap,
+				       void __iomem *port_mmio, u32 status)
+{
+	struct ahci_port_priv *pp = ap->private_data;
+	struct ahci_host_priv *hpriv = ap->host->private_data;
+
 	/* ignore BAD_PMP while resetting */
-	if (unlikely(resetting))
+	if (unlikely(ap->pflags & ATA_PFLAG_RESETTING))
 		status &= ~PORT_IRQ_BAD_PMP;
 
 	if (sata_lpm_ignore_phy_events(&ap->link)) {
@@ -1819,6 +1908,12 @@ static void ahci_handle_port_interrupt(struct ata_port *ap,
 	}
 
 	if (unlikely(status & PORT_IRQ_ERROR)) {
+		/*
+		 * Before getting the error notification, we may have
+		 * received SDB FISes notifying successful completions.
+		 * Handle these first and then handle the error.
+		 */
+		ahci_qc_complete(ap, port_mmio);
 		ahci_error_intr(ap, status);
 		return;
 	}
@@ -1855,32 +1950,8 @@ static void ahci_handle_port_interrupt(struct ata_port *ap,
 		}
 	}
 
-	/* pp->active_link is not reliable once FBS is enabled, both
-	 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
-	 * NCQ and non-NCQ commands may be in flight at the same time.
-	 */
-	if (pp->fbs_enabled) {
-		if (ap->qc_active) {
-			qc_active = readl(port_mmio + PORT_SCR_ACT);
-			qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
-		}
-	} else {
-		/* pp->active_link is valid iff any command is in flight */
-		if (ap->qc_active && pp->active_link->sactive)
-			qc_active = readl(port_mmio + PORT_SCR_ACT);
-		else
-			qc_active = readl(port_mmio + PORT_CMD_ISSUE);
-	}
-
-
-	rc = ata_qc_complete_multiple(ap, qc_active);
-
-	/* while resetting, invalid completions are expected */
-	if (unlikely(rc < 0 && !resetting)) {
-		ehi->err_mask |= AC_ERR_HSM;
-		ehi->action |= ATA_EH_RESET;
-		ata_port_freeze(ap);
-	}
+	/* Handle completed commands */
+	ahci_qc_complete(ap, port_mmio);
 }
 
 static void ahci_port_intr(struct ata_port *ap)
@@ -1900,8 +1971,6 @@ static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance)
 	void __iomem *port_mmio = ahci_port_base(ap);
 	u32 status;
 
-	VPRINTK("ENTER\n");
-
 	status = readl(port_mmio + PORT_IRQ_STAT);
 	writel(status, port_mmio + PORT_IRQ_STAT);
 
@@ -1909,8 +1978,6 @@ static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance)
 	ahci_handle_port_interrupt(ap, port_mmio, status);
 	spin_unlock(ap->lock);
 
-	VPRINTK("EXIT\n");
-
 	return IRQ_HANDLED;
 }
 
@@ -1927,9 +1994,7 @@ u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked)
 		ap = host->ports[i];
 		if (ap) {
 			ahci_port_intr(ap);
-			VPRINTK("port %u\n", i);
 		} else {
-			VPRINTK("port %u (no irq)\n", i);
 			if (ata_ratelimit())
 				dev_warn(host->dev,
 					 "interrupt on disabled port %u\n", i);
@@ -1950,8 +2015,6 @@ static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)
 	void __iomem *mmio;
 	u32 irq_stat, irq_masked;
 
-	VPRINTK("ENTER\n");
-
 	hpriv = host->private_data;
 	mmio = hpriv->mmio;
 
@@ -1979,8 +2042,6 @@ static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)
 
 	spin_unlock(&host->lock);
 
-	VPRINTK("EXIT\n");
-
 	return IRQ_RETVAL(rc);
 }
 
@@ -2015,7 +2076,7 @@ unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
 }
 EXPORT_SYMBOL_GPL(ahci_qc_issue);
 
-static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
+static void ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
 {
 	struct ahci_port_priv *pp = qc->ap->private_data;
 	u8 *rx_fis = pp->rx_fis;
@@ -2030,13 +2091,99 @@ static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
 	 * Setup FIS.
 	 */
 	if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
-	    !(qc->flags & ATA_QCFLAG_FAILED)) {
+	    !(qc->flags & ATA_QCFLAG_EH)) {
 		ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
-		qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
-	} else
-		ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
+		qc->result_tf.status = (rx_fis + RX_FIS_PIO_SETUP)[15];
+		return;
+	}
+
+	/*
+	 * For NCQ commands, we never get a D2H FIS, so reading the D2H Register
+	 * FIS area of the Received FIS Structure (which contains a copy of the
+	 * last D2H FIS received) will contain an outdated status code.
+	 * For NCQ commands, we instead get a SDB FIS, so read the SDB FIS area
+	 * instead. However, the SDB FIS does not contain the LBA, so we can't
+	 * use the ata_tf_from_fis() helper.
+	 */
+	if (ata_is_ncq(qc->tf.protocol)) {
+		const u8 *fis = rx_fis + RX_FIS_SDB;
+
+		/*
+		 * Successful NCQ commands have been filled already.
+		 * A failed NCQ command will read the status here.
+		 * (Note that a failed NCQ command will get a more specific
+		 * error when reading the NCQ Command Error log.)
+		 */
+		qc->result_tf.status = fis[2];
+		qc->result_tf.error = fis[3];
+		return;
+	}
 
-	return true;
+	ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
+}
+
+static void ahci_qc_ncq_fill_rtf(struct ata_port *ap, u64 done_mask)
+{
+	struct ahci_port_priv *pp = ap->private_data;
+	const u8 *fis;
+
+	/* No outstanding commands. */
+	if (!ap->qc_active)
+		return;
+
+	/*
+	 * FBS not enabled, so read status and error once, since they are shared
+	 * for all QCs.
+	 */
+	if (!pp->fbs_enabled) {
+		u8 status, error;
+
+		/* No outstanding NCQ commands. */
+		if (!pp->active_link->sactive)
+			return;
+
+		fis = pp->rx_fis + RX_FIS_SDB;
+		status = fis[2];
+		error = fis[3];
+
+		while (done_mask) {
+			struct ata_queued_cmd *qc;
+			unsigned int tag = __ffs64(done_mask);
+
+			qc = ata_qc_from_tag(ap, tag);
+			if (qc && ata_is_ncq(qc->tf.protocol)) {
+				qc->result_tf.status = status;
+				qc->result_tf.error = error;
+				qc->result_tf.flags = qc->tf.flags;
+				qc->flags |= ATA_QCFLAG_RTF_FILLED;
+			}
+			done_mask &= ~(1ULL << tag);
+		}
+
+		return;
+	}
+
+	/*
+	 * FBS enabled, so read the status and error for each QC, since the QCs
+	 * can belong to different PMP links. (Each PMP link has its own FIS
+	 * Receive Area.)
+	 */
+	while (done_mask) {
+		struct ata_queued_cmd *qc;
+		unsigned int tag = __ffs64(done_mask);
+
+		qc = ata_qc_from_tag(ap, tag);
+		if (qc && ata_is_ncq(qc->tf.protocol)) {
+			fis = pp->rx_fis;
+			fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
+			fis += RX_FIS_SDB;
+			qc->result_tf.status = fis[2];
+			qc->result_tf.error = fis[3];
+			qc->result_tf.flags = qc->tf.flags;
+			qc->flags |= ATA_QCFLAG_RTF_FILLED;
+		}
+		done_mask &= ~(1ULL << tag);
+	}
 }
 
 static void ahci_freeze(struct ata_port *ap)
@@ -2068,7 +2215,7 @@ void ahci_error_handler(struct ata_port *ap)
 {
 	struct ahci_host_priv *hpriv = ap->host->private_data;
 
-	if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
+	if (!ata_port_is_frozen(ap)) {
 		/* restart engine */
 		hpriv->stop_engine(ap);
 		hpriv->start_engine(ap);
@@ -2086,7 +2233,7 @@ static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
 	struct ata_port *ap = qc->ap;
 
 	/* make DMA engine forget about the failed command */
-	if (qc->flags & ATA_QCFLAG_FAILED)
+	if (qc->flags & ATA_QCFLAG_EH)
 		ahci_kick_engine(ap);
 }
 
@@ -2259,7 +2406,7 @@ static void ahci_pmp_attach(struct ata_port *ap)
 	 * Note that during initialization, the port is marked as
 	 * frozen since the irq handler is not yet registered.
 	 */
-	if (!(ap->pflags & ATA_PFLAG_FROZEN))
+	if (!ata_port_is_frozen(ap))
 		writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
 }
 
@@ -2278,7 +2425,7 @@ static void ahci_pmp_detach(struct ata_port *ap)
 	pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
 
 	/* see comment above in ahci_pmp_attach() */
-	if (!(ap->pflags & ATA_PFLAG_FROZEN))
+	if (!ata_port_is_frozen(ap))
 		writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
 }
 
@@ -2299,6 +2446,18 @@ int ahci_port_resume(struct ata_port *ap)
 EXPORT_SYMBOL_GPL(ahci_port_resume);
 
 #ifdef CONFIG_PM
+static void ahci_handle_s2idle(struct ata_port *ap)
+{
+	void __iomem *port_mmio = ahci_port_base(ap);
+	u32 devslp;
+
+	if (pm_suspend_via_firmware())
+		return;
+	devslp = readl(port_mmio + PORT_DEVSLP);
+	if ((devslp & PORT_DEVSLP_ADSE))
+		ata_msleep(ap, devslp_idle_timeout);
+}
+
 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
 {
 	const char *emsg = NULL;
@@ -2312,6 +2471,9 @@ static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
 		ata_port_freeze(ap);
 	}
 
+	if (acpi_storage_d3(ap->host->dev))
+		ahci_handle_s2idle(ap);
+
 	ahci_rpm_put_port(ap);
 	return rc;
 }
@@ -2456,8 +2618,8 @@ void ahci_print_info(struct ata_host *host, const char *scc_s)
 		speed_s = "?";
 
 	dev_info(host->dev,
-		"AHCI %02x%02x.%02x%02x "
-		"%u slots %u ports %s Gbps 0x%x impl %s mode\n"
+		"AHCI vers %02x%02x.%02x%02x, "
+		"%u command slots, %s Gbps, %s mode\n"
 		,
 
 		(vers >> 24) & 0xff,
@@ -2466,12 +2628,18 @@ void ahci_print_info(struct ata_host *host, const char *scc_s)
 		vers & 0xff,
 
 		((cap >> 8) & 0x1f) + 1,
-		(cap & 0x1f) + 1,
 		speed_s,
-		impl,
 		scc_s);
 
 	dev_info(host->dev,
+		"%u/%u ports implemented (port mask 0x%x)\n"
+		,
+
+		hweight32(impl),
+		(cap & 0x1f) + 1,
+		impl);
+
+	dev_info(host->dev,
 		"flags: "
 		"%s%s%s%s%s%s%s"
 		"%s%s%s%s%s%s%s"
@@ -2532,7 +2700,7 @@ void ahci_set_em_messages(struct ahci_host_priv *hpriv,
 EXPORT_SYMBOL_GPL(ahci_set_em_messages);
 
 static int ahci_host_activate_multi_irqs(struct ata_host *host,
-					 struct scsi_host_template *sht)
+					 const struct scsi_host_template *sht)
 {
 	struct ahci_host_priv *hpriv = host->private_data;
 	int i, rc;
@@ -2559,7 +2727,7 @@ static int ahci_host_activate_multi_irqs(struct ata_host *host,
 
 		if (rc)
 			return rc;
-		ata_port_desc(host->ports[i], "irq %d", irq);
+		ata_port_desc_misc(host->ports[i], irq);
 	}
 
 	return ata_host_register(host, sht);
@@ -2576,7 +2744,7 @@ static int ahci_host_activate_multi_irqs(struct ata_host *host,
  *	RETURNS:
  *	0 on success, -errno otherwise.
  */
-int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht)
+int ahci_host_activate(struct ata_host *host, const struct scsi_host_template *sht)
 {
 	struct ahci_host_priv *hpriv = host->private_data;
 	int irq = hpriv->irq;
diff --git a/drivers/ata/libahci_platform.c b/drivers/ata/libahci_platform.c
index 129556fcf6be..91d44302eac9 100644
--- a/drivers/ata/libahci_platform.c
+++ b/drivers/ata/libahci_platform.c
@@ -20,6 +20,7 @@
 #include <linux/ahci_platform.h>
 #include <linux/phy/phy.h>
 #include <linux/pm_runtime.h>
+#include <linux/of.h>
 #include <linux/of_platform.h>
 #include <linux/reset.h>
 #include "ahci.h"
@@ -48,6 +49,9 @@ int ahci_platform_enable_phys(struct ahci_host_priv *hpriv)
 	int rc, i;
 
 	for (i = 0; i < hpriv->nports; i++) {
+		if (ahci_ignore_port(hpriv, i))
+			continue;
+
 		rc = phy_init(hpriv->phys[i]);
 		if (rc)
 			goto disable_phys;
@@ -69,6 +73,9 @@ int ahci_platform_enable_phys(struct ahci_host_priv *hpriv)
 
 disable_phys:
 	while (--i >= 0) {
+		if (ahci_ignore_port(hpriv, i))
+			continue;
+
 		phy_power_off(hpriv->phys[i]);
 		phy_exit(hpriv->phys[i]);
 	}
@@ -87,6 +94,9 @@ void ahci_platform_disable_phys(struct ahci_host_priv *hpriv)
 	int i;
 
 	for (i = 0; i < hpriv->nports; i++) {
+		if (ahci_ignore_port(hpriv, i))
+			continue;
+
 		phy_power_off(hpriv->phys[i]);
 		phy_exit(hpriv->phys[i]);
 	}
@@ -94,31 +104,41 @@ void ahci_platform_disable_phys(struct ahci_host_priv *hpriv)
 EXPORT_SYMBOL_GPL(ahci_platform_disable_phys);
 
 /**
- * ahci_platform_enable_clks - Enable platform clocks
+ * ahci_platform_find_clk - Find platform clock
  * @hpriv: host private area to store config values
+ * @con_id: clock connection ID
  *
- * This function enables all the clks found in hpriv->clks, starting at
- * index 0. If any clk fails to enable it disables all the clks already
- * enabled in reverse order, and then returns an error.
+ * This function returns a pointer to the clock descriptor of the clock with
+ * the passed ID.
  *
  * RETURNS:
- * 0 on success otherwise a negative error code
+ * Pointer to the clock descriptor on success otherwise NULL
  */
-int ahci_platform_enable_clks(struct ahci_host_priv *hpriv)
+struct clk *ahci_platform_find_clk(struct ahci_host_priv *hpriv, const char *con_id)
 {
-	int c, rc;
+	int i;
 
-	for (c = 0; c < AHCI_MAX_CLKS && hpriv->clks[c]; c++) {
-		rc = clk_prepare_enable(hpriv->clks[c]);
-		if (rc)
-			goto disable_unprepare_clk;
+	for (i = 0; i < hpriv->n_clks; i++) {
+		if (hpriv->clks[i].id && !strcmp(hpriv->clks[i].id, con_id))
+			return hpriv->clks[i].clk;
 	}
-	return 0;
 
-disable_unprepare_clk:
-	while (--c >= 0)
-		clk_disable_unprepare(hpriv->clks[c]);
-	return rc;
+	return NULL;
+}
+EXPORT_SYMBOL_GPL(ahci_platform_find_clk);
+
+/**
+ * ahci_platform_enable_clks - Enable platform clocks
+ * @hpriv: host private area to store config values
+ *
+ * This function enables all the clks found for the AHCI device.
+ *
+ * RETURNS:
+ * 0 on success otherwise a negative error code
+ */
+int ahci_platform_enable_clks(struct ahci_host_priv *hpriv)
+{
+	return clk_bulk_prepare_enable(hpriv->n_clks, hpriv->clks);
 }
 EXPORT_SYMBOL_GPL(ahci_platform_enable_clks);
 
@@ -126,20 +146,55 @@ EXPORT_SYMBOL_GPL(ahci_platform_enable_clks);
  * ahci_platform_disable_clks - Disable platform clocks
  * @hpriv: host private area to store config values
  *
- * This function disables all the clks found in hpriv->clks, in reverse
- * order of ahci_platform_enable_clks (starting at the end of the array).
+ * This function disables all the clocks enabled before
+ * (bulk-clocks-disable function is supposed to do that in reverse
+ * from the enabling procedure order).
  */
 void ahci_platform_disable_clks(struct ahci_host_priv *hpriv)
 {
-	int c;
-
-	for (c = AHCI_MAX_CLKS - 1; c >= 0; c--)
-		if (hpriv->clks[c])
-			clk_disable_unprepare(hpriv->clks[c]);
+	clk_bulk_disable_unprepare(hpriv->n_clks, hpriv->clks);
 }
 EXPORT_SYMBOL_GPL(ahci_platform_disable_clks);
 
 /**
+ * ahci_platform_deassert_rsts - Deassert/trigger platform resets
+ * @hpriv: host private area to store config values
+ *
+ * This function deasserts or triggers all the reset lines found for
+ * the AHCI device.
+ *
+ * RETURNS:
+ * 0 on success otherwise a negative error code
+ */
+int ahci_platform_deassert_rsts(struct ahci_host_priv *hpriv)
+{
+	if (hpriv->f_rsts & AHCI_PLATFORM_RST_TRIGGER)
+		return reset_control_reset(hpriv->rsts);
+
+	return reset_control_deassert(hpriv->rsts);
+}
+EXPORT_SYMBOL_GPL(ahci_platform_deassert_rsts);
+
+/**
+ * ahci_platform_assert_rsts - Assert/rearm platform resets
+ * @hpriv: host private area to store config values
+ *
+ * This function asserts or rearms (for self-deasserting resets) all
+ * the reset controls found for the AHCI device.
+ *
+ * RETURNS:
+ * 0 on success otherwise a negative error code
+ */
+int ahci_platform_assert_rsts(struct ahci_host_priv *hpriv)
+{
+	if (hpriv->f_rsts & AHCI_PLATFORM_RST_TRIGGER)
+		return reset_control_rearm(hpriv->rsts);
+
+	return reset_control_assert(hpriv->rsts);
+}
+EXPORT_SYMBOL_GPL(ahci_platform_assert_rsts);
+
+/**
  * ahci_platform_enable_regulators - Enable regulators
  * @hpriv: host private area to store config values
  *
@@ -236,18 +291,18 @@ int ahci_platform_enable_resources(struct ahci_host_priv *hpriv)
 	if (rc)
 		goto disable_regulator;
 
-	rc = reset_control_deassert(hpriv->rsts);
+	rc = ahci_platform_deassert_rsts(hpriv);
 	if (rc)
 		goto disable_clks;
 
 	rc = ahci_platform_enable_phys(hpriv);
 	if (rc)
-		goto disable_resets;
+		goto disable_rsts;
 
 	return 0;
 
-disable_resets:
-	reset_control_assert(hpriv->rsts);
+disable_rsts:
+	ahci_platform_assert_rsts(hpriv);
 
 disable_clks:
 	ahci_platform_disable_clks(hpriv);
@@ -274,7 +329,7 @@ void ahci_platform_disable_resources(struct ahci_host_priv *hpriv)
 {
 	ahci_platform_disable_phys(hpriv);
 
-	reset_control_assert(hpriv->rsts);
+	ahci_platform_assert_rsts(hpriv);
 
 	ahci_platform_disable_clks(hpriv);
 
@@ -292,8 +347,6 @@ static void ahci_platform_put_resources(struct device *dev, void *res)
 		pm_runtime_disable(dev);
 	}
 
-	for (c = 0; c < AHCI_MAX_CLKS && hpriv->clks[c]; c++)
-		clk_put(hpriv->clks[c]);
 	/*
 	 * The regulators are tied to child node device and not to the
 	 * SATA device itself. So we can't use devm for automatically
@@ -320,13 +373,13 @@ static int ahci_platform_get_phy(struct ahci_host_priv *hpriv, u32 port,
 	switch (rc) {
 	case -ENOSYS:
 		/* No PHY support. Check if PHY is required. */
-		if (of_find_property(node, "phys", NULL)) {
+		if (of_property_present(node, "phys")) {
 			dev_err(dev,
 				"couldn't get PHY in node %pOFn: ENOSYS\n",
 				node);
 			break;
 		}
-		/* fall through */
+		fallthrough;
 	case -ENODEV:
 		/* continue normally */
 		hpriv->phys[port] = NULL;
@@ -363,6 +416,45 @@ static int ahci_platform_get_regulator(struct ahci_host_priv *hpriv, u32 port,
 	return rc;
 }
 
+static int ahci_platform_get_firmware(struct ahci_host_priv *hpriv,
+				      struct device *dev)
+{
+	u32 port;
+
+	if (!of_property_read_u32(dev->of_node, "hba-cap", &hpriv->saved_cap))
+		hpriv->saved_cap &= (HOST_CAP_SSS | HOST_CAP_MPS);
+
+	of_property_read_u32(dev->of_node,
+			     "ports-implemented", &hpriv->saved_port_map);
+
+	for_each_child_of_node_scoped(dev->of_node, child) {
+		if (!of_device_is_available(child))
+			continue;
+
+		if (of_property_read_u32(child, "reg", &port))
+			return -EINVAL;
+
+		if (!of_property_read_u32(child, "hba-port-cap", &hpriv->saved_port_cap[port]))
+			hpriv->saved_port_cap[port] &= PORT_CMD_CAP;
+	}
+
+	return 0;
+}
+
+static u32 ahci_platform_find_max_port_id(struct device *dev)
+{
+	u32 max_port = 0;
+
+	for_each_child_of_node_scoped(dev->of_node, child) {
+		u32 port;
+
+		if (!of_property_read_u32(child, "reg", &port))
+			max_port = max(max_port, port);
+	}
+
+	return max_port;
+}
+
 /**
  * ahci_platform_get_resources - Get platform resources
  * @pdev: platform device to get resources for
@@ -374,8 +466,8 @@ static int ahci_platform_get_regulator(struct ahci_host_priv *hpriv, u32 port,
  * 1) mmio registers (IORESOURCE_MEM 0, mandatory)
  * 2) regulator for controlling the targets power (optional)
  *    regulator for controlling the AHCI controller (optional)
- * 3) 0 - AHCI_MAX_CLKS clocks, as specified in the devs devicetree node,
- *    or for non devicetree enabled platforms a single clock
+ * 3) all clocks specified in the devicetree node, or a single
+ *    clock for non-OF platforms (optional)
  * 4) resets, if flags has AHCI_PLATFORM_GET_RESETS (optional)
  * 5) phys (optional)
  *
@@ -385,12 +477,11 @@ static int ahci_platform_get_regulator(struct ahci_host_priv *hpriv, u32 port,
 struct ahci_host_priv *ahci_platform_get_resources(struct platform_device *pdev,
 						   unsigned int flags)
 {
+	int child_nodes, rc = -ENOMEM, enabled_ports = 0;
 	struct device *dev = &pdev->dev;
 	struct ahci_host_priv *hpriv;
-	struct clk *clk;
-	struct device_node *child;
-	int i, enabled_ports = 0, rc = -ENOMEM, child_nodes;
 	u32 mask_port_map = 0;
+	u32 max_port;
 
 	if (!devres_open_group(dev, NULL, GFP_KERNEL))
 		return ERR_PTR(-ENOMEM);
@@ -402,32 +493,51 @@ struct ahci_host_priv *ahci_platform_get_resources(struct platform_device *pdev,
 
 	devres_add(dev, hpriv);
 
-	hpriv->mmio = devm_ioremap_resource(dev,
-			      platform_get_resource(pdev, IORESOURCE_MEM, 0));
+	/*
+	 * If the DT provided an "ahci" named resource, use it. Otherwise,
+	 * fallback to using the default first resource for the device node.
+	 */
+	if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "ahci"))
+		hpriv->mmio = devm_platform_ioremap_resource_byname(pdev, "ahci");
+	else
+		hpriv->mmio = devm_platform_ioremap_resource(pdev, 0);
 	if (IS_ERR(hpriv->mmio)) {
 		rc = PTR_ERR(hpriv->mmio);
 		goto err_out;
 	}
 
-	for (i = 0; i < AHCI_MAX_CLKS; i++) {
+	/*
+	 * Bulk clocks getting procedure can fail to find any clock due to
+	 * running on a non-OF platform or due to the clocks being defined in
+	 * bypass of the DT firmware (like da850, spear13xx). In that case we
+	 * fallback to getting a single clock source right from the dev clocks
+	 * list.
+	 */
+	rc = devm_clk_bulk_get_all(dev, &hpriv->clks);
+	if (rc < 0)
+		goto err_out;
+
+	if (rc > 0) {
+		/* Got clocks in bulk */
+		hpriv->n_clks = rc;
+	} else {
 		/*
-		 * For now we must use clk_get(dev, NULL) for the first clock,
-		 * because some platforms (da850, spear13xx) are not yet
-		 * converted to use devicetree for clocks.  For new platforms
-		 * this is equivalent to of_clk_get(dev->of_node, 0).
+		 * No clock bulk found: fallback to manually getting
+		 * the optional clock.
 		 */
-		if (i == 0)
-			clk = clk_get(dev, NULL);
-		else
-			clk = of_clk_get(dev->of_node, i);
-
-		if (IS_ERR(clk)) {
-			rc = PTR_ERR(clk);
-			if (rc == -EPROBE_DEFER)
-				goto err_out;
-			break;
+		hpriv->clks = devm_kzalloc(dev, sizeof(*hpriv->clks), GFP_KERNEL);
+		if (!hpriv->clks) {
+			rc = -ENOMEM;
+			goto err_out;
+		}
+		hpriv->clks->clk = devm_clk_get_optional(dev, NULL);
+		if (IS_ERR(hpriv->clks->clk)) {
+			rc = PTR_ERR(hpriv->clks->clk);
+			goto err_out;
+		} else if (hpriv->clks->clk) {
+			hpriv->clks->id = "ahci";
+			hpriv->n_clks = 1;
 		}
-		hpriv->clks[i] = clk;
 	}
 
 	hpriv->ahci_regulator = devm_regulator_get(dev, "ahci");
@@ -440,10 +550,7 @@ struct ahci_host_priv *ahci_platform_get_resources(struct platform_device *pdev,
 	hpriv->phy_regulator = devm_regulator_get(dev, "phy");
 	if (IS_ERR(hpriv->phy_regulator)) {
 		rc = PTR_ERR(hpriv->phy_regulator);
-		if (rc == -EPROBE_DEFER)
-			goto err_out;
-		rc = 0;
-		hpriv->phy_regulator = NULL;
+		goto err_out;
 	}
 
 	if (flags & AHCI_PLATFORM_GET_RESETS) {
@@ -452,17 +559,31 @@ struct ahci_host_priv *ahci_platform_get_resources(struct platform_device *pdev,
 			rc = PTR_ERR(hpriv->rsts);
 			goto err_out;
 		}
+
+		hpriv->f_rsts = flags & AHCI_PLATFORM_RST_TRIGGER;
 	}
 
-	hpriv->nports = child_nodes = of_get_child_count(dev->of_node);
+	/*
+	 * Too many sub-nodes most likely means having something wrong with
+	 * the firmware.
+	 */
+	child_nodes = of_get_child_count(dev->of_node);
+	if (child_nodes > AHCI_MAX_PORTS) {
+		rc = -EINVAL;
+		goto err_out;
+	}
 
+	/* find maximum port id for allocating structures */
+	max_port = ahci_platform_find_max_port_id(dev);
 	/*
-	 * If no sub-node was found, we still need to set nports to
-	 * one in order to be able to use the
+	 * Set nports according to maximum port id. Clamp at
+	 * AHCI_MAX_PORTS, warning message for invalid port id
+	 * is generated later.
+	 * When DT has no sub-nodes max_port is 0, nports is 1,
+	 * in order to be able to use the
 	 * ahci_platform_[en|dis]able_[phys|regulators] functions.
 	 */
-	if (!child_nodes)
-		hpriv->nports = 1;
+	hpriv->nports = min(AHCI_MAX_PORTS, max_port + 1);
 
 	hpriv->phys = devm_kcalloc(dev, hpriv->nports, sizeof(*hpriv->phys), GFP_KERNEL);
 	if (!hpriv->phys) {
@@ -480,7 +601,7 @@ struct ahci_host_priv *ahci_platform_get_resources(struct platform_device *pdev,
 	}
 
 	if (child_nodes) {
-		for_each_child_of_node(dev->of_node, child) {
+		for_each_child_of_node_scoped(dev->of_node, child) {
 			u32 port;
 			struct platform_device *port_dev __maybe_unused;
 
@@ -489,7 +610,6 @@ struct ahci_host_priv *ahci_platform_get_resources(struct platform_device *pdev,
 
 			if (of_property_read_u32(child, "reg", &port)) {
 				rc = -EINVAL;
-				of_node_put(child);
 				goto err_out;
 			}
 
@@ -507,18 +627,14 @@ struct ahci_host_priv *ahci_platform_get_resources(struct platform_device *pdev,
 			if (port_dev) {
 				rc = ahci_platform_get_regulator(hpriv, port,
 								&port_dev->dev);
-				if (rc == -EPROBE_DEFER) {
-					of_node_put(child);
+				if (rc == -EPROBE_DEFER)
 					goto err_out;
-				}
 			}
 #endif
 
 			rc = ahci_platform_get_phy(hpriv, port, dev, child);
-			if (rc) {
-				of_node_put(child);
+			if (rc)
 				goto err_out;
-			}
 
 			enabled_ports++;
 		}
@@ -543,6 +659,15 @@ struct ahci_host_priv *ahci_platform_get_resources(struct platform_device *pdev,
 		if (rc == -EPROBE_DEFER)
 			goto err_out;
 	}
+
+	/*
+	 * Retrieve firmware-specific flags which then will be used to set
+	 * the HW-init fields of HBA and its ports
+	 */
+	rc = ahci_platform_get_firmware(hpriv, dev);
+	if (rc)
+		goto err_out;
+
 	pm_runtime_enable(dev);
 	pm_runtime_get_sync(dev);
 	hpriv->got_runtime_pm = true;
@@ -573,7 +698,7 @@ EXPORT_SYMBOL_GPL(ahci_platform_get_resources);
 int ahci_platform_init_host(struct platform_device *pdev,
 			    struct ahci_host_priv *hpriv,
 			    const struct ata_port_info *pi_template,
-			    struct scsi_host_template *sht)
+			    const struct scsi_host_template *sht)
 {
 	struct device *dev = &pdev->dev;
 	struct ata_port_info pi = *pi_template;
@@ -582,11 +707,10 @@ int ahci_platform_init_host(struct platform_device *pdev,
 	int i, irq, n_ports, rc;
 
 	irq = platform_get_irq(pdev, 0);
-	if (irq <= 0) {
-		if (irq != -EPROBE_DEFER)
-			dev_err(dev, "no irq\n");
+	if (irq < 0)
 		return irq;
-	}
+	if (!irq)
+		return -EINVAL;
 
 	hpriv->irq = irq;
 
@@ -643,13 +767,8 @@ int ahci_platform_init_host(struct platform_device *pdev,
 	if (hpriv->cap & HOST_CAP_64) {
 		rc = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(64));
 		if (rc) {
-			rc = dma_coerce_mask_and_coherent(dev,
-							  DMA_BIT_MASK(32));
-			if (rc) {
-				dev_err(dev, "Failed to enable 64-bit DMA.\n");
-				return rc;
-			}
-			dev_warn(dev, "Enable 32-bit DMA instead of 64-bit.\n");
+			dev_err(dev, "Failed to enable 64-bit DMA.\n");
+			return rc;
 		}
 	}
 
@@ -742,7 +861,8 @@ int ahci_platform_suspend_host(struct device *dev)
 	if (hpriv->flags & AHCI_HFLAG_SUSPEND_PHYS)
 		ahci_platform_disable_phys(hpriv);
 
-	return ata_host_suspend(host, PMSG_SUSPEND);
+	ata_host_suspend(host, PMSG_SUSPEND);
+	return 0;
 }
 EXPORT_SYMBOL_GPL(ahci_platform_suspend_host);
 
diff --git a/drivers/ata/libata-acpi.c b/drivers/ata/libata-acpi.c
index 224e3486e9a5..15e18d50dcc6 100644
--- a/drivers/ata/libata-acpi.c
+++ b/drivers/ata/libata-acpi.c
@@ -86,7 +86,7 @@ static void ata_acpi_detach_device(struct ata_port *ap, struct ata_device *dev)
  * @dev: ATA device ACPI event occurred (can be NULL)
  * @event: ACPI event which occurred
  *
- * All ACPI bay / device realted events end up in this function.  If
+ * All ACPI bay / device related events end up in this function.  If
  * the event is port-wide @dev is NULL.  If the event is specific to a
  * device, @dev points to it.
  *
@@ -246,6 +246,73 @@ void ata_acpi_bind_dev(struct ata_device *dev)
 }
 
 /**
+ * ata_acpi_dev_manage_restart - if the disk should be stopped (spun down) on
+ *                               system restart.
+ * @dev: target ATA device
+ *
+ * RETURNS:
+ * true if the disk should be stopped, otherwise false.
+ */
+bool ata_acpi_dev_manage_restart(struct ata_device *dev)
+{
+	struct device *tdev;
+
+	/*
+	 * If ATA_FLAG_ACPI_SATA is set, the acpi fwnode is attached to the
+	 * ata_device instead of the ata_port.
+	 */
+	if (dev->link->ap->flags & ATA_FLAG_ACPI_SATA)
+		tdev = &dev->tdev;
+	else
+		tdev = &dev->link->ap->tdev;
+
+	if (!is_acpi_device_node(tdev->fwnode))
+		return false;
+	return acpi_bus_power_manageable(ACPI_HANDLE(tdev));
+}
+
+/**
+ * ata_acpi_port_power_on - set the power state of the ata port to D0
+ * @ap: target ATA port
+ *
+ * This function is called at the beginning of ata_port_probe().
+ */
+void ata_acpi_port_power_on(struct ata_port *ap)
+{
+	acpi_handle handle;
+	int i;
+
+	/*
+	 * If ATA_FLAG_ACPI_SATA is set, the acpi fwnode is attached to the
+	 * ata_device instead of the ata_port.
+	 */
+	if (ap->flags & ATA_FLAG_ACPI_SATA) {
+		for (i = 0; i < ATA_MAX_DEVICES; i++) {
+			struct ata_device *dev = &ap->link.device[i];
+
+			if (!is_acpi_device_node(dev->tdev.fwnode))
+				continue;
+			handle = ACPI_HANDLE(&dev->tdev);
+			if (!acpi_bus_power_manageable(handle))
+				continue;
+			if (acpi_bus_set_power(handle, ACPI_STATE_D0))
+				ata_dev_err(dev,
+					    "acpi: failed to set power state to D0\n");
+		}
+		return;
+	}
+
+	if (!is_acpi_device_node(ap->tdev.fwnode))
+		return;
+	handle = ACPI_HANDLE(&ap->tdev);
+	if (!acpi_bus_power_manageable(handle))
+		return;
+
+	if (acpi_bus_set_power(handle, ACPI_STATE_D0))
+		ata_port_err(ap, "acpi: failed to set power state to D0\n");
+}
+
+/**
  * ata_acpi_dissociate - dissociate ATA host from ACPI objects
  * @host: target ATA host
  *
@@ -402,7 +469,6 @@ EXPORT_SYMBOL_GPL(ata_acpi_stm);
  */
 static int ata_dev_get_GTF(struct ata_device *dev, struct ata_acpi_gtf **gtf)
 {
-	struct ata_port *ap = dev->link->ap;
 	acpi_status status;
 	struct acpi_buffer output;
 	union acpi_object *out_obj;
@@ -418,10 +484,6 @@ static int ata_dev_get_GTF(struct ata_device *dev, struct ata_acpi_gtf **gtf)
 	output.length = ACPI_ALLOCATE_BUFFER;
 	output.pointer = NULL;	/* ACPI-CA sets this; save/free it later */
 
-	if (ata_msg_probe(ap))
-		ata_dev_dbg(dev, "%s: ENTER: port#: %d\n",
-			    __func__, ap->port_no);
-
 	/* _GTF has no input parameters */
 	status = acpi_evaluate_object(ata_dev_acpi_handle(dev), "_GTF", NULL,
 				      &output);
@@ -437,11 +499,9 @@ static int ata_dev_get_GTF(struct ata_device *dev, struct ata_acpi_gtf **gtf)
 	}
 
 	if (!output.length || !output.pointer) {
-		if (ata_msg_probe(ap))
-			ata_dev_dbg(dev, "%s: Run _GTF: length or ptr is NULL (0x%llx, 0x%p)\n",
-				    __func__,
-				    (unsigned long long)output.length,
-				    output.pointer);
+		ata_dev_dbg(dev, "Run _GTF: length or ptr is NULL (0x%llx, 0x%p)\n",
+			    (unsigned long long)output.length,
+			    output.pointer);
 		rc = -EINVAL;
 		goto out_free;
 	}
@@ -464,9 +524,8 @@ static int ata_dev_get_GTF(struct ata_device *dev, struct ata_acpi_gtf **gtf)
 	rc = out_obj->buffer.length / REGS_PER_GTF;
 	if (gtf) {
 		*gtf = (void *)out_obj->buffer.pointer;
-		if (ata_msg_probe(ap))
-			ata_dev_dbg(dev, "%s: returning gtf=%p, gtf_count=%d\n",
-				    __func__, *gtf, rc);
+		ata_dev_dbg(dev, "returning gtf=%p, gtf_count=%d\n",
+			    *gtf, rc);
 	}
 	return rc;
 
@@ -476,7 +535,7 @@ static int ata_dev_get_GTF(struct ata_device *dev, struct ata_acpi_gtf **gtf)
 }
 
 /**
- * ata_acpi_gtm_xfermode - determine xfermode from GTM parameter
+ * ata_acpi_gtm_xfermask - determine xfermode from GTM parameter
  * @dev: target device
  * @gtm: GTM parameter to use
  *
@@ -488,10 +547,10 @@ static int ata_dev_get_GTF(struct ata_device *dev, struct ata_acpi_gtf **gtf)
  * RETURNS:
  * Determined xfermask.
  */
-unsigned long ata_acpi_gtm_xfermask(struct ata_device *dev,
-				    const struct ata_acpi_gtm *gtm)
+unsigned int ata_acpi_gtm_xfermask(struct ata_device *dev,
+				   const struct ata_acpi_gtm *gtm)
 {
-	unsigned long xfer_mask = 0;
+	unsigned int xfer_mask = 0;
 	unsigned int type;
 	int unit;
 	u8 mode;
@@ -522,29 +581,37 @@ unsigned long ata_acpi_gtm_xfermask(struct ata_device *dev,
 EXPORT_SYMBOL_GPL(ata_acpi_gtm_xfermask);
 
 /**
- * ata_acpi_cbl_80wire		-	Check for 80 wire cable
+ * ata_acpi_cbl_pata_type - Return PATA cable type
  * @ap: Port to check
- * @gtm: GTM data to use
  *
- * Return 1 if the @gtm indicates the BIOS selected an 80wire mode.
+ * Return ATA_CBL_PATA* according to the transfer mode selected by BIOS
  */
-int ata_acpi_cbl_80wire(struct ata_port *ap, const struct ata_acpi_gtm *gtm)
+int ata_acpi_cbl_pata_type(struct ata_port *ap)
 {
 	struct ata_device *dev;
+	int ret = ATA_CBL_PATA_UNK;
+	const struct ata_acpi_gtm *gtm = ata_acpi_init_gtm(ap);
+
+	if (!gtm)
+		return ATA_CBL_PATA40;
 
 	ata_for_each_dev(dev, &ap->link, ENABLED) {
-		unsigned long xfer_mask, udma_mask;
+		unsigned int xfer_mask, udma_mask;
 
 		xfer_mask = ata_acpi_gtm_xfermask(dev, gtm);
 		ata_unpack_xfermask(xfer_mask, NULL, NULL, &udma_mask);
 
-		if (udma_mask & ~ATA_UDMA_MASK_40C)
-			return 1;
+		ret = ATA_CBL_PATA40;
+
+		if (udma_mask & ~ATA_UDMA_MASK_40C) {
+			ret = ATA_CBL_PATA80;
+			break;
+		}
 	}
 
-	return 0;
+	return ret;
 }
-EXPORT_SYMBOL_GPL(ata_acpi_cbl_80wire);
+EXPORT_SYMBOL_GPL(ata_acpi_cbl_pata_type);
 
 static void ata_acpi_gtf_to_tf(struct ata_device *dev,
 			       const struct ata_acpi_gtf *gtf,
@@ -554,13 +621,13 @@ static void ata_acpi_gtf_to_tf(struct ata_device *dev,
 
 	tf->flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
 	tf->protocol = ATA_PROT_NODATA;
-	tf->feature = gtf->tf[0];	/* 0x1f1 */
+	tf->error   = gtf->tf[0];	/* 0x1f1 */
 	tf->nsect   = gtf->tf[1];	/* 0x1f2 */
 	tf->lbal    = gtf->tf[2];	/* 0x1f3 */
 	tf->lbam    = gtf->tf[3];	/* 0x1f4 */
 	tf->lbah    = gtf->tf[4];	/* 0x1f5 */
 	tf->device  = gtf->tf[5];	/* 0x1f6 */
-	tf->command = gtf->tf[6];	/* 0x1f7 */
+	tf->status  = gtf->tf[6];	/* 0x1f7 */
 }
 
 static int ata_acpi_filter_tf(struct ata_device *dev,
@@ -624,6 +691,7 @@ static int ata_acpi_filter_tf(struct ata_device *dev,
  * ata_acpi_run_tf - send taskfile registers to host controller
  * @dev: target ATA device
  * @gtf: raw ATA taskfile register set (0x1f1 - 0x1f7)
+ * @prev_gtf: previous command
  *
  * Outputs ATA taskfile to standard ATA host controller.
  * Writes the control, feature, nsect, lbal, lbam, and lbah registers.
@@ -649,9 +717,7 @@ static int ata_acpi_run_tf(struct ata_device *dev,
 	struct ata_taskfile *pptf = NULL;
 	struct ata_taskfile tf, ptf, rtf;
 	unsigned int err_mask;
-	const char *level;
 	const char *descr;
-	char msg[60];
 	int rc;
 
 	if ((gtf->tf[0] == 0) && (gtf->tf[1] == 0) && (gtf->tf[2] == 0)
@@ -665,6 +731,8 @@ static int ata_acpi_run_tf(struct ata_device *dev,
 		pptf = &ptf;
 	}
 
+	descr = ata_get_cmd_name(tf.command);
+
 	if (!ata_acpi_filter_tf(dev, &tf, pptf)) {
 		rtf = tf;
 		err_mask = ata_exec_internal(dev, &rtf, NULL,
@@ -672,40 +740,42 @@ static int ata_acpi_run_tf(struct ata_device *dev,
 
 		switch (err_mask) {
 		case 0:
-			level = KERN_DEBUG;
-			snprintf(msg, sizeof(msg), "succeeded");
+			ata_dev_dbg(dev,
+				"ACPI cmd %02x/%02x:%02x:%02x:%02x:%02x:%02x"
+				"(%s) succeeded\n",
+				tf.command, tf.feature, tf.nsect, tf.lbal,
+				tf.lbam, tf.lbah, tf.device, descr);
 			rc = 1;
 			break;
 
 		case AC_ERR_DEV:
-			level = KERN_INFO;
-			snprintf(msg, sizeof(msg),
-				 "rejected by device (Stat=0x%02x Err=0x%02x)",
-				 rtf.command, rtf.feature);
+			ata_dev_info(dev,
+				"ACPI cmd %02x/%02x:%02x:%02x:%02x:%02x:%02x"
+				"(%s) rejected by device (Stat=0x%02x Err=0x%02x)",
+				tf.command, tf.feature, tf.nsect, tf.lbal,
+				tf.lbam, tf.lbah, tf.device, descr,
+				rtf.status, rtf.error);
 			rc = 0;
 			break;
 
 		default:
-			level = KERN_ERR;
-			snprintf(msg, sizeof(msg),
-				 "failed (Emask=0x%x Stat=0x%02x Err=0x%02x)",
-				 err_mask, rtf.command, rtf.feature);
+			ata_dev_err(dev,
+				"ACPI cmd %02x/%02x:%02x:%02x:%02x:%02x:%02x"
+				"(%s) failed (Emask=0x%x Stat=0x%02x Err=0x%02x)",
+				tf.command, tf.feature, tf.nsect, tf.lbal,
+				tf.lbam, tf.lbah, tf.device, descr,
+				err_mask, rtf.status, rtf.error);
 			rc = -EIO;
 			break;
 		}
 	} else {
-		level = KERN_INFO;
-		snprintf(msg, sizeof(msg), "filtered out");
+		ata_dev_info(dev,
+			"ACPI cmd %02x/%02x:%02x:%02x:%02x:%02x:%02x"
+			"(%s) filtered out\n",
+			tf.command, tf.feature, tf.nsect, tf.lbal,
+			tf.lbam, tf.lbah, tf.device, descr);
 		rc = 0;
 	}
-	descr = ata_get_cmd_descript(tf.command);
-
-	ata_dev_printk(dev, level,
-		       "ACPI cmd %02x/%02x:%02x:%02x:%02x:%02x:%02x (%s) %s\n",
-		       tf.command, tf.feature, tf.nsect, tf.lbal,
-		       tf.lbam, tf.lbah, tf.device,
-		       (descr ? descr : "unknown"), msg);
-
 	return rc;
 }
 
@@ -775,9 +845,8 @@ static int ata_acpi_push_id(struct ata_device *dev)
 	struct acpi_object_list input;
 	union acpi_object in_params[1];
 
-	if (ata_msg_probe(ap))
-		ata_dev_dbg(dev, "%s: ix = %d, port#: %d\n",
-			    __func__, dev->devno, ap->port_no);
+	ata_dev_dbg(dev, "%s: ix = %d, port#: %d\n",
+		    __func__, dev->devno, ap->port_no);
 
 	/* Give the drive Identify data to the drive via the _SDD method */
 	/* _SDD: set up input parameters */
@@ -806,27 +875,6 @@ static int ata_acpi_push_id(struct ata_device *dev)
 }
 
 /**
- * ata_acpi_on_suspend - ATA ACPI hook called on suspend
- * @ap: target ATA port
- *
- * This function is called when @ap is about to be suspended.  All
- * devices are already put to sleep but the port_suspend() callback
- * hasn't been executed yet.  Error return from this function aborts
- * suspend.
- *
- * LOCKING:
- * EH context.
- *
- * RETURNS:
- * 0 on success, -errno on failure.
- */
-int ata_acpi_on_suspend(struct ata_port *ap)
-{
-	/* nada */
-	return 0;
-}
-
-/**
  * ata_acpi_on_resume - ATA ACPI hook called on resume
  * @ap: target ATA port
  *
@@ -859,7 +907,7 @@ void ata_acpi_on_resume(struct ata_port *ap)
 				dev->flags |= ATA_DFLAG_ACPI_PENDING;
 		}
 	} else {
-		/* SATA _GTF needs to be evaulated after _SDD and
+		/* SATA _GTF needs to be evaluated after _SDD and
 		 * there's no reason to evaluate IDE _GTF early
 		 * without _STM.  Clear cache and schedule _GTF.
 		 */
@@ -1019,7 +1067,7 @@ int ata_acpi_on_devcfg(struct ata_device *dev)
 
  acpi_err:
 	/* ignore evaluation failure if we can continue safely */
-	if (rc == -EINVAL && !nr_executed && !(ap->pflags & ATA_PFLAG_FROZEN))
+	if (rc == -EINVAL && !nr_executed && !ata_port_is_frozen(ap))
 		return 0;
 
 	/* fail and let EH retry once more for unknown IO errors */
@@ -1034,7 +1082,7 @@ int ata_acpi_on_devcfg(struct ata_device *dev)
 	/* We can safely continue if no _GTF command has been executed
 	 * and port is not frozen.
 	 */
-	if (!nr_executed && !(ap->pflags & ATA_PFLAG_FROZEN))
+	if (!nr_executed && !ata_port_is_frozen(ap))
 		return 0;
 
 	return rc;
diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c
index beca5f91bb4c..0b24bd169d61 100644
--- a/drivers/ata/libata-core.c
+++ b/drivers/ata/libata-core.c
@@ -42,7 +42,6 @@
 #include <linux/workqueue.h>
 #include <linux/scatterlist.h>
 #include <linux/io.h>
-#include <linux/async.h>
 #include <linux/log2.h>
 #include <linux/slab.h>
 #include <linux/glob.h>
@@ -51,7 +50,7 @@
 #include <scsi/scsi_host.h>
 #include <linux/libata.h>
 #include <asm/byteorder.h>
-#include <asm/unaligned.h>
+#include <linux/unaligned.h>
 #include <linux/cdrom.h>
 #include <linux/ratelimit.h>
 #include <linux/leds.h>
@@ -66,38 +65,32 @@
 #include "libata-transport.h"
 
 const struct ata_port_operations ata_base_port_ops = {
-	.prereset		= ata_std_prereset,
-	.postreset		= ata_std_postreset,
+	.reset.prereset		= ata_std_prereset,
+	.reset.postreset	= ata_std_postreset,
 	.error_handler		= ata_std_error_handler,
 	.sched_eh		= ata_std_sched_eh,
 	.end_eh			= ata_std_end_eh,
 };
 
-const struct ata_port_operations sata_port_ops = {
-	.inherits		= &ata_base_port_ops,
-
-	.qc_defer		= ata_std_qc_defer,
-	.hardreset		= sata_std_hardreset,
-};
-EXPORT_SYMBOL_GPL(sata_port_ops);
-
 static unsigned int ata_dev_init_params(struct ata_device *dev,
 					u16 heads, u16 sectors);
 static unsigned int ata_dev_set_xfermode(struct ata_device *dev);
 static void ata_dev_xfermask(struct ata_device *dev);
-static unsigned long ata_dev_blacklisted(const struct ata_device *dev);
+static unsigned int ata_dev_quirks(const struct ata_device *dev);
 
-atomic_t ata_print_id = ATOMIC_INIT(0);
+static DEFINE_IDA(ata_ida);
 
 #ifdef CONFIG_ATA_FORCE
 struct ata_force_param {
 	const char	*name;
 	u8		cbl;
 	u8		spd_limit;
-	unsigned long	xfer_mask;
-	unsigned int	horkage_on;
-	unsigned int	horkage_off;
-	u16		lflags;
+	unsigned int	xfer_mask;
+	unsigned int	quirk_on;
+	unsigned int	quirk_off;
+	unsigned int	pflags_on;
+	u16		lflags_on;
+	u16		lflags_off;
 };
 
 struct ata_force_ent {
@@ -160,10 +153,11 @@ MODULE_DESCRIPTION("Library module for ATA devices");
 MODULE_LICENSE("GPL");
 MODULE_VERSION(DRV_VERSION);
 
-
-static bool ata_sstatus_online(u32 sstatus)
+static inline bool ata_dev_print_info(const struct ata_device *dev)
 {
-	return (sstatus & 0xf) == 0x3;
+	struct ata_eh_context *ehc = &dev->link->eh_context;
+
+	return ehc->i.flags & ATA_EHI_PRINTINFO;
 }
 
 /**
@@ -191,7 +185,7 @@ struct ata_link *ata_link_next(struct ata_link *link, struct ata_port *ap,
 		case ATA_LITER_PMP_FIRST:
 			if (sata_pmp_attached(ap))
 				return ap->pmp_link;
-			/* fall through */
+			fallthrough;
 		case ATA_LITER_HOST_FIRST:
 			return &ap->link;
 		}
@@ -202,11 +196,11 @@ struct ata_link *ata_link_next(struct ata_link *link, struct ata_port *ap,
 		case ATA_LITER_HOST_FIRST:
 			if (sata_pmp_attached(ap))
 				return ap->pmp_link;
-			/* fall through */
+			fallthrough;
 		case ATA_LITER_PMP_FIRST:
 			if (unlikely(ap->slave_link))
 				return ap->slave_link;
-			/* fall through */
+			fallthrough;
 		case ATA_LITER_EDGE:
 			return NULL;
 		}
@@ -339,6 +333,35 @@ void ata_force_cbl(struct ata_port *ap)
 }
 
 /**
+ *	ata_force_pflags - force port flags according to libata.force
+ *	@ap: ATA port of interest
+ *
+ *	Force port flags according to libata.force and whine about it.
+ *
+ *	LOCKING:
+ *	EH context.
+ */
+static void ata_force_pflags(struct ata_port *ap)
+{
+	int i;
+
+	for (i = ata_force_tbl_size - 1; i >= 0; i--) {
+		const struct ata_force_ent *fe = &ata_force_tbl[i];
+
+		if (fe->port != -1 && fe->port != ap->print_id)
+			continue;
+
+		/* let pflags stack */
+		if (fe->param.pflags_on) {
+			ap->pflags |= fe->param.pflags_on;
+			ata_port_notice(ap,
+					"FORCE: port flag 0x%x forced -> 0x%x\n",
+					fe->param.pflags_on, ap->pflags);
+		}
+	}
+}
+
+/**
  *	ata_force_link_limits - force link limits according to libata.force
  *	@link: ATA link of interest
  *
@@ -381,11 +404,17 @@ static void ata_force_link_limits(struct ata_link *link)
 		}
 
 		/* let lflags stack */
-		if (fe->param.lflags) {
-			link->flags |= fe->param.lflags;
+		if (fe->param.lflags_on) {
+			link->flags |= fe->param.lflags_on;
 			ata_link_notice(link,
 					"FORCE: link flag 0x%x forced -> 0x%x\n",
-					fe->param.lflags, link->flags);
+					fe->param.lflags_on, link->flags);
+		}
+		if (fe->param.lflags_off) {
+			link->flags &= ~fe->param.lflags_off;
+			ata_link_notice(link,
+				"FORCE: link flag 0x%x cleared -> 0x%x\n",
+				fe->param.lflags_off, link->flags);
 		}
 	}
 }
@@ -413,7 +442,7 @@ static void ata_force_xfermask(struct ata_device *dev)
 
 	for (i = ata_force_tbl_size - 1; i >= 0; i--) {
 		const struct ata_force_ent *fe = &ata_force_tbl[i];
-		unsigned long pio_mask, mwdma_mask, udma_mask;
+		unsigned int pio_mask, mwdma_mask, udma_mask;
 
 		if (fe->port != -1 && fe->port != dev->link->ap->print_id)
 			continue;
@@ -445,17 +474,17 @@ static void ata_force_xfermask(struct ata_device *dev)
 }
 
 /**
- *	ata_force_horkage - force horkage according to libata.force
+ *	ata_force_quirks - force quirks according to libata.force
  *	@dev: ATA device of interest
  *
- *	Force horkage according to libata.force and whine about it.
+ *	Force quirks according to libata.force and whine about it.
  *	For consistency with link selection, device number 15 selects
  *	the first device connected to the host link.
  *
  *	LOCKING:
  *	EH context.
  */
-static void ata_force_horkage(struct ata_device *dev)
+static void ata_force_quirks(struct ata_device *dev)
 {
 	int devno = dev->link->pmp + dev->devno;
 	int alt_devno = devno;
@@ -475,21 +504,22 @@ static void ata_force_horkage(struct ata_device *dev)
 		    fe->device != alt_devno)
 			continue;
 
-		if (!(~dev->horkage & fe->param.horkage_on) &&
-		    !(dev->horkage & fe->param.horkage_off))
+		if (!(~dev->quirks & fe->param.quirk_on) &&
+		    !(dev->quirks & fe->param.quirk_off))
 			continue;
 
-		dev->horkage |= fe->param.horkage_on;
-		dev->horkage &= ~fe->param.horkage_off;
+		dev->quirks |= fe->param.quirk_on;
+		dev->quirks &= ~fe->param.quirk_off;
 
-		ata_dev_notice(dev, "FORCE: horkage modified (%s)\n",
+		ata_dev_notice(dev, "FORCE: modified (%s)\n",
 			       fe->param.name);
 	}
 }
 #else
+static inline void ata_force_pflags(struct ata_port *ap) { }
 static inline void ata_force_link_limits(struct ata_link *link) { }
 static inline void ata_force_xfermask(struct ata_device *dev) { }
-static inline void ata_force_horkage(struct ata_device *dev) { }
+static inline void ata_force_quirks(struct ata_device *dev) { }
 #endif
 
 /**
@@ -524,7 +554,7 @@ int atapi_cmd_type(u8 opcode)
 	case ATA_12:
 		if (atapi_passthru16)
 			return ATAPI_PASS_THRU;
-		/* fall thru */
+		fallthrough;
 	default:
 		return ATAPI_MISC;
 	}
@@ -540,7 +570,7 @@ static const u8 ata_rw_cmds[] = {
 	0,
 	0,
 	0,
-	ATA_CMD_WRITE_MULTI_FUA_EXT,
+	0,
 	/* pio */
 	ATA_CMD_PIO_READ,
 	ATA_CMD_PIO_WRITE,
@@ -562,17 +592,18 @@ static const u8 ata_rw_cmds[] = {
 };
 
 /**
- *	ata_rwcmd_protocol - set taskfile r/w commands and protocol
- *	@tf: command to examine and configure
- *	@dev: device tf belongs to
+ *	ata_set_rwcmd_protocol - set taskfile r/w command and protocol
+ *	@dev: target device for the taskfile
+ *	@tf: taskfile to examine and configure
  *
- *	Examine the device configuration and tf->flags to calculate
- *	the proper read/write commands and protocol to use.
+ *	Examine the device configuration and tf->flags to determine
+ *	the proper read/write command and protocol to use for @tf.
  *
  *	LOCKING:
  *	caller.
  */
-static int ata_rwcmd_protocol(struct ata_taskfile *tf, struct ata_device *dev)
+static bool ata_set_rwcmd_protocol(struct ata_device *dev,
+				   struct ata_taskfile *tf)
 {
 	u8 cmd;
 
@@ -595,11 +626,12 @@ static int ata_rwcmd_protocol(struct ata_taskfile *tf, struct ata_device *dev)
 	}
 
 	cmd = ata_rw_cmds[index + fua + lba48 + write];
-	if (cmd) {
-		tf->command = cmd;
-		return 0;
-	}
-	return -1;
+	if (!cmd)
+		return false;
+
+	tf->command = cmd;
+
+	return true;
 }
 
 /**
@@ -651,35 +683,56 @@ u64 ata_tf_read_block(const struct ata_taskfile *tf, struct ata_device *dev)
 	return block;
 }
 
+/*
+ * Set a taskfile command duration limit index.
+ */
+static inline void ata_set_tf_cdl(struct ata_queued_cmd *qc, int cdl)
+{
+	struct ata_taskfile *tf = &qc->tf;
+
+	if (tf->protocol == ATA_PROT_NCQ)
+		tf->auxiliary |= cdl;
+	else
+		tf->feature |= cdl;
+
+	/*
+	 * Mark this command as having a CDL and request the result
+	 * task file so that we can inspect the sense data available
+	 * bit on completion.
+	 */
+	qc->flags |= ATA_QCFLAG_HAS_CDL | ATA_QCFLAG_RESULT_TF;
+}
+
 /**
  *	ata_build_rw_tf - Build ATA taskfile for given read/write request
- *	@tf: Target ATA taskfile
- *	@dev: ATA device @tf belongs to
+ *	@qc: Metadata associated with the taskfile to build
  *	@block: Block address
  *	@n_block: Number of blocks
  *	@tf_flags: RW/FUA etc...
- *	@tag: tag
+ *	@cdl: Command duration limit index
  *	@class: IO priority class
  *
  *	LOCKING:
  *	None.
  *
- *	Build ATA taskfile @tf for read/write request described by
- *	@block, @n_block, @tf_flags and @tag on @dev.
+ *	Build ATA taskfile for the command @qc for read/write request described
+ *	by @block, @n_block, @tf_flags and @class.
  *
  *	RETURNS:
  *
  *	0 on success, -ERANGE if the request is too large for @dev,
  *	-EINVAL if the request is invalid.
  */
-int ata_build_rw_tf(struct ata_taskfile *tf, struct ata_device *dev,
-		    u64 block, u32 n_block, unsigned int tf_flags,
-		    unsigned int tag, int class)
+int ata_build_rw_tf(struct ata_queued_cmd *qc, u64 block, u32 n_block,
+		    unsigned int tf_flags, int cdl, int class)
 {
+	struct ata_taskfile *tf = &qc->tf;
+	struct ata_device *dev = qc->dev;
+
 	tf->flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
 	tf->flags |= tf_flags;
 
-	if (ata_ncq_enabled(dev) && !ata_tag_internal(tag)) {
+	if (ata_ncq_enabled(dev)) {
 		/* yay, NCQ */
 		if (!lba_48_ok(block, n_block))
 			return -ERANGE;
@@ -692,7 +745,7 @@ int ata_build_rw_tf(struct ata_taskfile *tf, struct ata_device *dev,
 		else
 			tf->command = ATA_CMD_FPDMA_READ;
 
-		tf->nsect = tag << 3;
+		tf->nsect = qc->hw_tag << 3;
 		tf->hob_feature = (n_block >> 8) & 0xff;
 		tf->feature = n_block & 0xff;
 
@@ -707,15 +760,23 @@ int ata_build_rw_tf(struct ata_taskfile *tf, struct ata_device *dev,
 		if (tf->flags & ATA_TFLAG_FUA)
 			tf->device |= 1 << 7;
 
-		if (dev->flags & ATA_DFLAG_NCQ_PRIO) {
-			if (class == IOPRIO_CLASS_RT)
-				tf->hob_nsect |= ATA_PRIO_HIGH <<
-						 ATA_SHIFT_PRIO;
-		}
+		if (dev->flags & ATA_DFLAG_NCQ_PRIO_ENABLED &&
+		    class == IOPRIO_CLASS_RT)
+			tf->hob_nsect |= ATA_PRIO_HIGH << ATA_SHIFT_PRIO;
+
+		if ((dev->flags & ATA_DFLAG_CDL_ENABLED) && cdl)
+			ata_set_tf_cdl(qc, cdl);
+
 	} else if (dev->flags & ATA_DFLAG_LBA) {
 		tf->flags |= ATA_TFLAG_LBA;
 
-		if (lba_28_ok(block, n_block)) {
+		if ((dev->flags & ATA_DFLAG_CDL_ENABLED) && cdl)
+			ata_set_tf_cdl(qc, cdl);
+
+		/* Both FUA writes and a CDL index require 48-bit commands */
+		if (!(tf->flags & ATA_TFLAG_FUA) &&
+		    !(qc->flags & ATA_QCFLAG_HAS_CDL) &&
+		    lba_28_ok(block, n_block)) {
 			/* use LBA28 */
 			tf->device |= (block >> 24) & 0xf;
 		} else if (lba_48_ok(block, n_block)) {
@@ -730,11 +791,12 @@ int ata_build_rw_tf(struct ata_taskfile *tf, struct ata_device *dev,
 			tf->hob_lbah = (block >> 40) & 0xff;
 			tf->hob_lbam = (block >> 32) & 0xff;
 			tf->hob_lbal = (block >> 24) & 0xff;
-		} else
+		} else {
 			/* request too large even for LBA48 */
 			return -ERANGE;
+		}
 
-		if (unlikely(ata_rwcmd_protocol(tf, dev) < 0))
+		if (unlikely(!ata_set_rwcmd_protocol(dev, tf)))
 			return -EINVAL;
 
 		tf->nsect = n_block & 0xff;
@@ -752,7 +814,7 @@ int ata_build_rw_tf(struct ata_taskfile *tf, struct ata_device *dev,
 		if (!lba_28_ok(block, n_block))
 			return -ERANGE;
 
-		if (unlikely(ata_rwcmd_protocol(tf, dev) < 0))
+		if (unlikely(!ata_set_rwcmd_protocol(dev, tf)))
 			return -EINVAL;
 
 		/* Convert LBA to CHS */
@@ -761,9 +823,6 @@ int ata_build_rw_tf(struct ata_taskfile *tf, struct ata_device *dev,
 		head  = track % dev->heads;
 		sect  = (u32)block % dev->sectors + 1;
 
-		DPRINTK("block %u track %u cyl %u head %u sect %u\n",
-			(u32)block, track, cyl, head, sect);
-
 		/* Check whether the converted CHS can fit.
 		   Cylinder: 0-65535
 		   Head: 0-15
@@ -796,11 +855,11 @@ int ata_build_rw_tf(struct ata_taskfile *tf, struct ata_device *dev,
  *	RETURNS:
  *	Packed xfer_mask.
  */
-unsigned long ata_pack_xfermask(unsigned long pio_mask,
-				unsigned long mwdma_mask,
-				unsigned long udma_mask)
+unsigned int ata_pack_xfermask(unsigned int pio_mask,
+			       unsigned int mwdma_mask,
+			       unsigned int udma_mask)
 {
-	return ((pio_mask << ATA_SHIFT_PIO) & ATA_MASK_PIO) |
+	return	((pio_mask << ATA_SHIFT_PIO) & ATA_MASK_PIO) |
 		((mwdma_mask << ATA_SHIFT_MWDMA) & ATA_MASK_MWDMA) |
 		((udma_mask << ATA_SHIFT_UDMA) & ATA_MASK_UDMA);
 }
@@ -816,8 +875,8 @@ EXPORT_SYMBOL_GPL(ata_pack_xfermask);
  *	Unpack @xfer_mask into @pio_mask, @mwdma_mask and @udma_mask.
  *	Any NULL destination masks will be ignored.
  */
-void ata_unpack_xfermask(unsigned long xfer_mask, unsigned long *pio_mask,
-			 unsigned long *mwdma_mask, unsigned long *udma_mask)
+void ata_unpack_xfermask(unsigned int xfer_mask, unsigned int *pio_mask,
+			 unsigned int *mwdma_mask, unsigned int *udma_mask)
 {
 	if (pio_mask)
 		*pio_mask = (xfer_mask & ATA_MASK_PIO) >> ATA_SHIFT_PIO;
@@ -850,7 +909,7 @@ static const struct ata_xfer_ent {
  *	RETURNS:
  *	Matching XFER_* value, 0xff if no match found.
  */
-u8 ata_xfer_mask2mode(unsigned long xfer_mask)
+u8 ata_xfer_mask2mode(unsigned int xfer_mask)
 {
 	int highbit = fls(xfer_mask) - 1;
 	const struct ata_xfer_ent *ent;
@@ -874,7 +933,7 @@ EXPORT_SYMBOL_GPL(ata_xfer_mask2mode);
  *	RETURNS:
  *	Matching xfer_mask, 0 if no match found.
  */
-unsigned long ata_xfer_mode2mask(u8 xfer_mode)
+unsigned int ata_xfer_mode2mask(u8 xfer_mode)
 {
 	const struct ata_xfer_ent *ent;
 
@@ -898,7 +957,7 @@ EXPORT_SYMBOL_GPL(ata_xfer_mode2mask);
  *	RETURNS:
  *	Matching xfer_shift, -1 if no match found.
  */
-int ata_xfer_mode2shift(unsigned long xfer_mode)
+int ata_xfer_mode2shift(u8 xfer_mode)
 {
 	const struct ata_xfer_ent *ent;
 
@@ -923,7 +982,7 @@ EXPORT_SYMBOL_GPL(ata_xfer_mode2shift);
  *	Constant C string representing highest speed listed in
  *	@mode_mask, or the constant C string "<n/a>".
  */
-const char *ata_mode_string(unsigned long xfer_mask)
+const char *ata_mode_string(unsigned int xfer_mask)
 {
 	static const char * const xfer_mode_str[] = {
 		"PIO0",
@@ -1007,32 +1066,21 @@ unsigned int ata_dev_classify(const struct ata_taskfile *tf)
 	 * SEMB signature.  This is worked around in
 	 * ata_dev_read_id().
 	 */
-	if ((tf->lbam == 0) && (tf->lbah == 0)) {
-		DPRINTK("found ATA device by sig\n");
+	if (tf->lbam == 0 && tf->lbah == 0)
 		return ATA_DEV_ATA;
-	}
 
-	if ((tf->lbam == 0x14) && (tf->lbah == 0xeb)) {
-		DPRINTK("found ATAPI device by sig\n");
+	if (tf->lbam == 0x14 && tf->lbah == 0xeb)
 		return ATA_DEV_ATAPI;
-	}
 
-	if ((tf->lbam == 0x69) && (tf->lbah == 0x96)) {
-		DPRINTK("found PMP device by sig\n");
+	if (tf->lbam == 0x69 && tf->lbah == 0x96)
 		return ATA_DEV_PMP;
-	}
 
-	if ((tf->lbam == 0x3c) && (tf->lbah == 0xc3)) {
-		DPRINTK("found SEMB device by sig (could be ATA device)\n");
+	if (tf->lbam == 0x3c && tf->lbah == 0xc3)
 		return ATA_DEV_SEMB;
-	}
 
-	if ((tf->lbam == 0xcd) && (tf->lbah == 0xab)) {
-		DPRINTK("found ZAC device by sig\n");
+	if (tf->lbam == 0xcd && tf->lbah == 0xab)
 		return ATA_DEV_ZAC;
-	}
 
-	DPRINTK("unknown device\n");
 	return ATA_DEV_UNKNOWN;
 }
 EXPORT_SYMBOL_GPL(ata_dev_classify);
@@ -1107,16 +1155,16 @@ static u64 ata_id_n_sectors(const u16 *id)
 	if (ata_id_has_lba(id)) {
 		if (ata_id_has_lba48(id))
 			return ata_id_u64(id, ATA_ID_LBA_CAPACITY_2);
-		else
-			return ata_id_u32(id, ATA_ID_LBA_CAPACITY);
-	} else {
-		if (ata_id_current_chs_valid(id))
-			return id[ATA_ID_CUR_CYLS] * id[ATA_ID_CUR_HEADS] *
-			       id[ATA_ID_CUR_SECTORS];
-		else
-			return id[ATA_ID_CYLS] * id[ATA_ID_HEADS] *
-			       id[ATA_ID_SECTORS];
+
+		return ata_id_u32(id, ATA_ID_LBA_CAPACITY);
 	}
+
+	if (ata_id_current_chs_valid(id))
+		return (u32)id[ATA_ID_CUR_CYLS] * (u32)id[ATA_ID_CUR_HEADS] *
+		       (u32)id[ATA_ID_CUR_SECTORS];
+
+	return (u32)id[ATA_ID_CYLS] * (u32)id[ATA_ID_HEADS] *
+	       (u32)id[ATA_ID_SECTORS];
 }
 
 u64 ata_tf_to_lba48(const struct ata_taskfile *tf)
@@ -1182,7 +1230,7 @@ static int ata_read_native_max_address(struct ata_device *dev, u64 *max_sectors)
 		ata_dev_warn(dev,
 			     "failed to read native max address (err_mask=0x%x)\n",
 			     err_mask);
-		if (err_mask == AC_ERR_DEV && (tf.feature & ATA_ABORTED))
+		if (err_mask == AC_ERR_DEV && (tf.error & ATA_ABORTED))
 			return -EACCES;
 		return -EIO;
 	}
@@ -1191,7 +1239,7 @@ static int ata_read_native_max_address(struct ata_device *dev, u64 *max_sectors)
 		*max_sectors = ata_tf_to_lba48(&tf) + 1;
 	else
 		*max_sectors = ata_tf_to_lba(&tf) + 1;
-	if (dev->horkage & ATA_HORKAGE_HPA_SIZE)
+	if (dev->quirks & ATA_QUIRK_HPA_SIZE)
 		(*max_sectors)--;
 	return 0;
 }
@@ -1246,7 +1294,7 @@ static int ata_set_max_sectors(struct ata_device *dev, u64 new_sectors)
 			     "failed to set max address (err_mask=0x%x)\n",
 			     err_mask);
 		if (err_mask == AC_ERR_DEV &&
-		    (tf.feature & (ATA_ABORTED | ATA_IDNF)))
+		    (tf.error & (ATA_ABORTED | ATA_IDNF)))
 			return -EACCES;
 		return -EIO;
 	}
@@ -1267,8 +1315,7 @@ static int ata_set_max_sectors(struct ata_device *dev, u64 new_sectors)
  */
 static int ata_hpa_resize(struct ata_device *dev)
 {
-	struct ata_eh_context *ehc = &dev->link->eh_context;
-	int print_info = ehc->i.flags & ATA_EHI_PRINTINFO;
+	bool print_info = ata_dev_print_info(dev);
 	bool unlock_hpa = ata_ignore_hpa || dev->flags & ATA_DFLAG_UNLOCK_HPA;
 	u64 sectors = ata_id_n_sectors(dev->id);
 	u64 native_sectors;
@@ -1277,7 +1324,7 @@ static int ata_hpa_resize(struct ata_device *dev)
 	/* do we need to do it? */
 	if ((dev->class != ATA_DEV_ATA && dev->class != ATA_DEV_ZAC) ||
 	    !ata_id_has_lba(dev->id) || !ata_id_hpa_enabled(dev->id) ||
-	    (dev->horkage & ATA_HORKAGE_BROKEN_HPA))
+	    (dev->quirks & ATA_QUIRK_BROKEN_HPA))
 		return 0;
 
 	/* read native max address */
@@ -1289,7 +1336,7 @@ static int ata_hpa_resize(struct ata_device *dev)
 		if (rc == -EACCES || !unlock_hpa) {
 			ata_dev_warn(dev,
 				     "HPA support seems broken, skipping HPA handling\n");
-			dev->horkage |= ATA_HORKAGE_BROKEN_HPA;
+			dev->quirks |= ATA_QUIRK_BROKEN_HPA;
 
 			/* we can continue if device aborted the command */
 			if (rc == -EACCES)
@@ -1326,7 +1373,7 @@ static int ata_hpa_resize(struct ata_device *dev)
 			     "device aborted resize (%llu -> %llu), skipping HPA handling\n",
 			     (unsigned long long)sectors,
 			     (unsigned long long)native_sectors);
-		dev->horkage |= ATA_HORKAGE_BROKEN_HPA;
+		dev->quirks |= ATA_QUIRK_BROKEN_HPA;
 		return 0;
 	} else if (rc)
 		return rc;
@@ -1353,6 +1400,7 @@ static int ata_hpa_resize(struct ata_device *dev)
 
 /**
  *	ata_dump_id - IDENTIFY DEVICE info debugging output
+ *	@dev: device from which the information is fetched
  *	@id: IDENTIFY DEVICE page to dump
  *
  *	Dump selected 16-bit words from the given IDENTIFY DEVICE
@@ -1362,32 +1410,14 @@ static int ata_hpa_resize(struct ata_device *dev)
  *	caller.
  */
 
-static inline void ata_dump_id(const u16 *id)
-{
-	DPRINTK("49==0x%04x  "
-		"53==0x%04x  "
-		"63==0x%04x  "
-		"64==0x%04x  "
-		"75==0x%04x  \n",
-		id[49],
-		id[53],
-		id[63],
-		id[64],
-		id[75]);
-	DPRINTK("80==0x%04x  "
-		"81==0x%04x  "
-		"82==0x%04x  "
-		"83==0x%04x  "
-		"84==0x%04x  \n",
-		id[80],
-		id[81],
-		id[82],
-		id[83],
-		id[84]);
-	DPRINTK("88==0x%04x  "
-		"93==0x%04x\n",
-		id[88],
-		id[93]);
+static inline void ata_dump_id(struct ata_device *dev, const u16 *id)
+{
+	ata_dev_dbg(dev,
+		"49==0x%04x  53==0x%04x  63==0x%04x  64==0x%04x  75==0x%04x\n"
+		"80==0x%04x  81==0x%04x  82==0x%04x  83==0x%04x  84==0x%04x\n"
+		"88==0x%04x  93==0x%04x\n",
+		id[49], id[53], id[63], id[64], id[75], id[80],
+		id[81], id[82], id[83], id[84], id[88], id[93]);
 }
 
 /**
@@ -1405,9 +1435,9 @@ static inline void ata_dump_id(const u16 *id)
  *	RETURNS:
  *	Computed xfermask
  */
-unsigned long ata_id_xfermask(const u16 *id)
+unsigned int ata_id_xfermask(const u16 *id)
 {
-	unsigned long pio_mask, mwdma_mask, udma_mask;
+	unsigned int pio_mask, mwdma_mask, udma_mask;
 
 	/* Usual case. Word 53 indicates word 64 is valid */
 	if (id[ATA_ID_FIELD_VALID] & (1 << 1)) {
@@ -1427,7 +1457,7 @@ unsigned long ata_id_xfermask(const u16 *id)
 
 		/* But wait.. there's more. Design your standards by
 		 * committee and you too can get a free iordy field to
-		 * process. However its the speeds not the modes that
+		 * process. However it is the speeds not the modes that
 		 * are supported... Note drivers using the timing API
 		 * will get this right anyway
 		 */
@@ -1468,19 +1498,19 @@ static void ata_qc_complete_internal(struct ata_queued_cmd *qc)
 }
 
 /**
- *	ata_exec_internal_sg - execute libata internal command
+ *	ata_exec_internal - execute libata internal command
  *	@dev: Device to which the command is sent
  *	@tf: Taskfile registers for the command and the result
  *	@cdb: CDB for packet command
  *	@dma_dir: Data transfer direction of the command
- *	@sgl: sg list for the data buffer of the command
- *	@n_elem: Number of sg entries
+ *	@buf: Data buffer of the command
+ *	@buflen: Length of data buffer
  *	@timeout: Timeout in msecs (0 for default)
  *
- *	Executes libata internal command with timeout.  @tf contains
- *	command on entry and result on return.  Timeout and error
- *	conditions are reported via return value.  No recovery action
- *	is taken after a command times out.  It's caller's duty to
+ *	Executes libata internal command with timeout. @tf contains
+ *	the command on entry and the result on return. Timeout and error
+ *	conditions are reported via the return value. No recovery action
+ *	is taken after a command times out. It is the caller's duty to
  *	clean up after timeout.
  *
  *	LOCKING:
@@ -1489,34 +1519,38 @@ static void ata_qc_complete_internal(struct ata_queued_cmd *qc)
  *	RETURNS:
  *	Zero on success, AC_ERR_* mask on failure
  */
-unsigned ata_exec_internal_sg(struct ata_device *dev,
-			      struct ata_taskfile *tf, const u8 *cdb,
-			      int dma_dir, struct scatterlist *sgl,
-			      unsigned int n_elem, unsigned long timeout)
+unsigned int ata_exec_internal(struct ata_device *dev, struct ata_taskfile *tf,
+			       const u8 *cdb, enum dma_data_direction dma_dir,
+			       void *buf, unsigned int buflen,
+			       unsigned int timeout)
 {
 	struct ata_link *link = dev->link;
 	struct ata_port *ap = link->ap;
 	u8 command = tf->command;
-	int auto_timeout = 0;
 	struct ata_queued_cmd *qc;
+	struct scatterlist sgl;
 	unsigned int preempted_tag;
 	u32 preempted_sactive;
 	u64 preempted_qc_active;
 	int preempted_nr_active_links;
+	bool auto_timeout = false;
 	DECLARE_COMPLETION_ONSTACK(wait);
 	unsigned long flags;
 	unsigned int err_mask;
 	int rc;
 
+	if (WARN_ON(dma_dir != DMA_NONE && !buf))
+		return AC_ERR_INVALID;
+
 	spin_lock_irqsave(ap->lock, flags);
 
-	/* no internal command while frozen */
-	if (ap->pflags & ATA_PFLAG_FROZEN) {
+	/* No internal command while frozen */
+	if (ata_port_is_frozen(ap)) {
 		spin_unlock_irqrestore(ap->lock, flags);
 		return AC_ERR_SYSTEM;
 	}
 
-	/* initialize internal qc */
+	/* Initialize internal qc */
 	qc = __ata_qc_from_tag(ap, ATA_TAG_INTERNAL);
 
 	qc->tag = ATA_TAG_INTERNAL;
@@ -1535,12 +1569,12 @@ unsigned ata_exec_internal_sg(struct ata_device *dev,
 	ap->qc_active = 0;
 	ap->nr_active_links = 0;
 
-	/* prepare & issue qc */
+	/* Prepare and issue qc */
 	qc->tf = *tf;
 	if (cdb)
 		memcpy(qc->cdb, cdb, ATAPI_CDB_LEN);
 
-	/* some SATA bridges need us to indicate data xfer direction */
+	/* Some SATA bridges need us to indicate data xfer direction */
 	if (tf->protocol == ATAPI_PROT_DMA && (dev->flags & ATA_DFLAG_DMADIR) &&
 	    dma_dir == DMA_FROM_DEVICE)
 		qc->tf.feature |= ATAPI_DMADIR;
@@ -1548,13 +1582,8 @@ unsigned ata_exec_internal_sg(struct ata_device *dev,
 	qc->flags |= ATA_QCFLAG_RESULT_TF;
 	qc->dma_dir = dma_dir;
 	if (dma_dir != DMA_NONE) {
-		unsigned int i, buflen = 0;
-		struct scatterlist *sg;
-
-		for_each_sg(sgl, sg, n_elem, i)
-			buflen += sg->length;
-
-		ata_sg_init(qc, sgl, n_elem);
+		sg_init_one(&sgl, buf, buflen);
+		ata_sg_init(qc, &sgl, 1);
 		qc->nbytes = buflen;
 	}
 
@@ -1566,55 +1595,44 @@ unsigned ata_exec_internal_sg(struct ata_device *dev,
 	spin_unlock_irqrestore(ap->lock, flags);
 
 	if (!timeout) {
-		if (ata_probe_timeout)
+		if (ata_probe_timeout) {
 			timeout = ata_probe_timeout * 1000;
-		else {
+		} else {
 			timeout = ata_internal_cmd_timeout(dev, command);
-			auto_timeout = 1;
+			auto_timeout = true;
 		}
 	}
 
-	if (ap->ops->error_handler)
-		ata_eh_release(ap);
+	ata_eh_release(ap);
 
 	rc = wait_for_completion_timeout(&wait, msecs_to_jiffies(timeout));
 
-	if (ap->ops->error_handler)
-		ata_eh_acquire(ap);
+	ata_eh_acquire(ap);
 
 	ata_sff_flush_pio_task(ap);
 
 	if (!rc) {
-		spin_lock_irqsave(ap->lock, flags);
-
-		/* We're racing with irq here.  If we lose, the
-		 * following test prevents us from completing the qc
-		 * twice.  If we win, the port is frozen and will be
-		 * cleaned up by ->post_internal_cmd().
+		/*
+		 * We are racing with irq here. If we lose, the following test
+		 * prevents us from completing the qc twice. If we win, the port
+		 * is frozen and will be cleaned up by ->post_internal_cmd().
 		 */
+		spin_lock_irqsave(ap->lock, flags);
 		if (qc->flags & ATA_QCFLAG_ACTIVE) {
 			qc->err_mask |= AC_ERR_TIMEOUT;
-
-			if (ap->ops->error_handler)
-				ata_port_freeze(ap);
-			else
-				ata_qc_complete(qc);
-
-			if (ata_msg_warn(ap))
-				ata_dev_warn(dev, "qc timeout (cmd 0x%x)\n",
-					     command);
+			ata_port_freeze(ap);
+			ata_dev_warn(dev, "qc timeout after %u msecs (cmd 0x%x)\n",
+				     timeout, command);
 		}
-
 		spin_unlock_irqrestore(ap->lock, flags);
 	}
 
-	/* do post_internal_cmd */
 	if (ap->ops->post_internal_cmd)
 		ap->ops->post_internal_cmd(qc);
 
-	/* perform minimal error analysis */
-	if (qc->flags & ATA_QCFLAG_FAILED) {
-		if (qc->result_tf.command & (ATA_ERR | ATA_DF))
+	/* Perform minimal error analysis */
+	if (qc->flags & ATA_QCFLAG_EH) {
+		if (qc->result_tf.status & (ATA_ERR | ATA_DF))
 			qc->err_mask |= AC_ERR_DEV;
 
 		if (!qc->err_mask)
@@ -1623,10 +1641,10 @@ unsigned ata_exec_internal_sg(struct ata_device *dev,
 		if (qc->err_mask & ~AC_ERR_OTHER)
 			qc->err_mask &= ~AC_ERR_OTHER;
 	} else if (qc->tf.command == ATA_CMD_REQ_SENSE_DATA) {
-		qc->result_tf.command |= ATA_SENSE;
+		qc->result_tf.status |= ATA_SENSE;
 	}
 
-	/* finish up */
+	/* Finish up */
 	spin_lock_irqsave(ap->lock, flags);
 
 	*tf = qc->result_tf;
@@ -1647,44 +1665,6 @@ unsigned ata_exec_internal_sg(struct ata_device *dev,
 }
 
 /**
- *	ata_exec_internal - execute libata internal command
- *	@dev: Device to which the command is sent
- *	@tf: Taskfile registers for the command and the result
- *	@cdb: CDB for packet command
- *	@dma_dir: Data transfer direction of the command
- *	@buf: Data buffer of the command
- *	@buflen: Length of data buffer
- *	@timeout: Timeout in msecs (0 for default)
- *
- *	Wrapper around ata_exec_internal_sg() which takes simple
- *	buffer instead of sg list.
- *
- *	LOCKING:
- *	None.  Should be called with kernel context, might sleep.
- *
- *	RETURNS:
- *	Zero on success, AC_ERR_* mask on failure
- */
-unsigned ata_exec_internal(struct ata_device *dev,
-			   struct ata_taskfile *tf, const u8 *cdb,
-			   int dma_dir, void *buf, unsigned int buflen,
-			   unsigned long timeout)
-{
-	struct scatterlist *psg = NULL, sg;
-	unsigned int n_elem = 0;
-
-	if (dma_dir != DMA_NONE) {
-		WARN_ON(!buf);
-		sg_init_one(&sg, buf, buflen);
-		psg = &sg;
-		n_elem++;
-	}
-
-	return ata_exec_internal_sg(dev, tf, cdb, dma_dir, psg, n_elem,
-				    timeout);
-}
-
-/**
  *	ata_pio_need_iordy	-	check if iordy needed
  *	@adev: ATA device
  *
@@ -1752,7 +1732,7 @@ static u32 ata_pio_mask_no_iordy(const struct ata_device *adev)
  *	this function is wrapped or replaced by the driver
  */
 unsigned int ata_do_dev_read_id(struct ata_device *dev,
-					struct ata_taskfile *tf, u16 *id)
+				struct ata_taskfile *tf, __le16 *id)
 {
 	return ata_exec_internal(dev, tf, NULL, DMA_FROM_DEVICE,
 				     id, sizeof(id[0]) * ATA_ID_WORDS, 0);
@@ -1792,16 +1772,13 @@ int ata_dev_read_id(struct ata_device *dev, unsigned int *p_class,
 	int may_fallback = 1, tried_spinup = 0;
 	int rc;
 
-	if (ata_msg_ctl(ap))
-		ata_dev_dbg(dev, "%s: ENTER\n", __func__);
-
 retry:
 	ata_tf_init(dev, &tf);
 
 	switch (class) {
 	case ATA_DEV_SEMB:
 		class = ATA_DEV_ATA;	/* some hard drives report SEMB sig */
-		/* fall through */
+		fallthrough;
 	case ATA_DEV_ATA:
 	case ATA_DEV_ZAC:
 		tf.command = ATA_CMD_ID_ATA;
@@ -1828,9 +1805,9 @@ retry:
 	tf.flags |= ATA_TFLAG_POLLING;
 
 	if (ap->ops->read_id)
-		err_mask = ap->ops->read_id(dev, &tf, id);
+		err_mask = ap->ops->read_id(dev, &tf, (__le16 *)id);
 	else
-		err_mask = ata_do_dev_read_id(dev, &tf, id);
+		err_mask = ata_do_dev_read_id(dev, &tf, (__le16 *)id);
 
 	if (err_mask) {
 		if (err_mask & AC_ERR_NODEV_HINT) {
@@ -1846,7 +1823,7 @@ retry:
 			return 0;
 		}
 
-		if ((err_mask == AC_ERR_DEV) && (tf.feature & ATA_ABORTED)) {
+		if ((err_mask == AC_ERR_DEV) && (tf.error & ATA_ABORTED)) {
 			/* Device or controller might have reported
 			 * the wrong device class.  Give a shot at the
 			 * other IDENTIFY if the current one is
@@ -1876,11 +1853,11 @@ retry:
 		goto err_out;
 	}
 
-	if (dev->horkage & ATA_HORKAGE_DUMP_ID) {
-		ata_dev_dbg(dev, "dumping IDENTIFY data, "
+	if (dev->quirks & ATA_QUIRK_DUMP_ID) {
+		ata_dev_info(dev, "dumping IDENTIFY data, "
 			    "class=%d may_fallback=%d tried_spinup=%d\n",
 			    class, may_fallback, tried_spinup);
-		print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET,
+		print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
 			       16, 2, id, ATA_ID_WORDS * sizeof(*id), true);
 	}
 
@@ -1964,12 +1941,151 @@ retry:
 	return 0;
 
  err_out:
-	if (ata_msg_warn(ap))
-		ata_dev_warn(dev, "failed to IDENTIFY (%s, err_mask=0x%x)\n",
-			     reason, err_mask);
+	ata_dev_warn(dev, "failed to IDENTIFY (%s, err_mask=0x%x)\n",
+		     reason, err_mask);
 	return rc;
 }
 
+bool ata_dev_power_init_tf(struct ata_device *dev, struct ata_taskfile *tf,
+			   bool set_active)
+{
+	/* Only applies to ATA and ZAC devices */
+	if (dev->class != ATA_DEV_ATA && dev->class != ATA_DEV_ZAC)
+		return false;
+
+	ata_tf_init(dev, tf);
+	tf->flags |= ATA_TFLAG_DEVICE | ATA_TFLAG_ISADDR;
+	tf->protocol = ATA_PROT_NODATA;
+
+	if (set_active) {
+		/* VERIFY for 1 sector at lba=0 */
+		tf->command = ATA_CMD_VERIFY;
+		tf->nsect = 1;
+		if (dev->flags & ATA_DFLAG_LBA) {
+			tf->flags |= ATA_TFLAG_LBA;
+			tf->device |= ATA_LBA;
+		} else {
+			/* CHS */
+			tf->lbal = 0x1; /* sect */
+		}
+	} else {
+		tf->command = ATA_CMD_STANDBYNOW1;
+	}
+
+	return true;
+}
+
+static bool ata_dev_power_is_active(struct ata_device *dev)
+{
+	struct ata_taskfile tf;
+	unsigned int err_mask;
+
+	ata_tf_init(dev, &tf);
+	tf.flags |= ATA_TFLAG_DEVICE | ATA_TFLAG_ISADDR;
+	tf.protocol = ATA_PROT_NODATA;
+	tf.command = ATA_CMD_CHK_POWER;
+
+	err_mask = ata_exec_internal(dev, &tf, NULL, DMA_NONE, NULL, 0, 0);
+	if (err_mask) {
+		ata_dev_err(dev, "Check power mode failed (err_mask=0x%x)\n",
+			    err_mask);
+		/*
+		 * Assume we are in standby mode so that we always force a
+		 * spinup in ata_dev_power_set_active().
+		 */
+		return false;
+	}
+
+	ata_dev_dbg(dev, "Power mode: 0x%02x\n", tf.nsect);
+
+	/* Active or idle */
+	return tf.nsect == 0xff;
+}
+
+/**
+ *	ata_dev_power_set_standby - Set a device power mode to standby
+ *	@dev: target device
+ *
+ *	Issue a STANDBY IMMEDIATE command to set a device power mode to standby.
+ *	For an HDD device, this spins down the disks.
+ *
+ *	LOCKING:
+ *	Kernel thread context (may sleep).
+ */
+void ata_dev_power_set_standby(struct ata_device *dev)
+{
+	unsigned long ap_flags = dev->link->ap->flags;
+	struct ata_taskfile tf;
+	unsigned int err_mask;
+
+	/* If the device is already sleeping or in standby, do nothing. */
+	if ((dev->flags & ATA_DFLAG_SLEEPING) ||
+	    !ata_dev_power_is_active(dev))
+		return;
+
+	/*
+	 * Some odd clown BIOSes issue spindown on power off (ACPI S4 or S5)
+	 * causing some drives to spin up and down again. For these, do nothing
+	 * if we are being called on shutdown.
+	 */
+	if ((ap_flags & ATA_FLAG_NO_POWEROFF_SPINDOWN) &&
+	    system_state == SYSTEM_POWER_OFF)
+		return;
+
+	if ((ap_flags & ATA_FLAG_NO_HIBERNATE_SPINDOWN) &&
+	    system_entering_hibernation())
+		return;
+
+	/* Issue STANDBY IMMEDIATE command only if supported by the device */
+	if (!ata_dev_power_init_tf(dev, &tf, false))
+		return;
+
+	ata_dev_notice(dev, "Entering standby power mode\n");
+
+	err_mask = ata_exec_internal(dev, &tf, NULL, DMA_NONE, NULL, 0, 0);
+	if (err_mask)
+		ata_dev_err(dev, "STANDBY IMMEDIATE failed (err_mask=0x%x)\n",
+			    err_mask);
+}
+
+/**
+ *	ata_dev_power_set_active -  Set a device power mode to active
+ *	@dev: target device
+ *
+ *	Issue a VERIFY command to enter to ensure that the device is in the
+ *	active power mode. For a spun-down HDD (standby or idle power mode),
+ *	the VERIFY command will complete after the disk spins up.
+ *
+ *	LOCKING:
+ *	Kernel thread context (may sleep).
+ */
+void ata_dev_power_set_active(struct ata_device *dev)
+{
+	struct ata_taskfile tf;
+	unsigned int err_mask;
+
+	/*
+	 * Issue READ VERIFY SECTORS command for 1 sector at lba=0 only
+	 * if supported by the device.
+	 */
+	if (!ata_dev_power_init_tf(dev, &tf, true))
+		return;
+
+	/*
+	 * Check the device power state & condition and force a spinup with
+	 * VERIFY command only if the drive is not already ACTIVE or IDLE.
+	 */
+	if (ata_dev_power_is_active(dev))
+		return;
+
+	ata_dev_notice(dev, "Entering active power mode\n");
+
+	err_mask = ata_exec_internal(dev, &tf, NULL, DMA_NONE, NULL, 0, 0);
+	if (err_mask)
+		ata_dev_err(dev, "VERIFY failed (err_mask=0x%x)\n",
+			    err_mask);
+}
+
 /**
  *	ata_read_log_page - read a specific log page
  *	@dev: target device
@@ -1994,7 +2110,7 @@ unsigned int ata_read_log_page(struct ata_device *dev, u8 log,
 	unsigned int err_mask;
 	bool dma = false;
 
-	DPRINTK("read log page - log 0x%x, page 0x%x\n", log, page);
+	ata_dev_dbg(dev, "read log page - log 0x%x, page 0x%x\n", log, page);
 
 	/*
 	 * Return error without actually issuing the command on controllers
@@ -2005,8 +2121,8 @@ unsigned int ata_read_log_page(struct ata_device *dev, u8 log,
 
 retry:
 	ata_tf_init(dev, &tf);
-	if (dev->dma_mode && ata_id_has_read_log_dma_ext(dev->id) &&
-	    !(dev->horkage & ATA_HORKAGE_NO_DMA_LOG)) {
+	if (ata_dma_enabled(dev) && ata_id_has_read_log_dma_ext(dev->id) &&
+	    !(dev->quirks & ATA_QUIRK_NO_DMA_LOG)) {
 		tf.command = ATA_CMD_READ_LOG_DMA_EXT;
 		tf.protocol = ATA_PROT_DMA;
 		dma = true;
@@ -2024,32 +2140,76 @@ retry:
 	err_mask = ata_exec_internal(dev, &tf, NULL, DMA_FROM_DEVICE,
 				     buf, sectors * ATA_SECT_SIZE, 0);
 
-	if (err_mask && dma) {
-		dev->horkage |= ATA_HORKAGE_NO_DMA_LOG;
-		ata_dev_warn(dev, "READ LOG DMA EXT failed, trying PIO\n");
-		goto retry;
+	if (err_mask) {
+		if (dma) {
+			dev->quirks |= ATA_QUIRK_NO_DMA_LOG;
+			if (!ata_port_is_frozen(dev->link->ap))
+				goto retry;
+		}
+		ata_dev_err(dev,
+			    "Read log 0x%02x page 0x%02x failed, Emask 0x%x\n",
+			    (unsigned int)log, (unsigned int)page, err_mask);
 	}
 
-	DPRINTK("EXIT, err_mask=%x\n", err_mask);
 	return err_mask;
 }
 
-static bool ata_log_supported(struct ata_device *dev, u8 log)
+static inline void ata_clear_log_directory(struct ata_device *dev)
 {
-	struct ata_port *ap = dev->link->ap;
+	memset(dev->gp_log_dir, 0, ATA_SECT_SIZE);
+}
 
-	if (ata_read_log_page(dev, ATA_LOG_DIRECTORY, 0, ap->sector_buf, 1))
-		return false;
-	return get_unaligned_le16(&ap->sector_buf[log * 2]) ? true : false;
+static int ata_read_log_directory(struct ata_device *dev)
+{
+	u16 version;
+
+	/* If the log page is already cached, do nothing. */
+	version = get_unaligned_le16(&dev->gp_log_dir[0]);
+	if (version == 0x0001)
+		return 0;
+
+	if (ata_read_log_page(dev, ATA_LOG_DIRECTORY, 0, dev->gp_log_dir, 1)) {
+		ata_clear_log_directory(dev);
+		return -EIO;
+	}
+
+	version = get_unaligned_le16(&dev->gp_log_dir[0]);
+	if (version != 0x0001)
+		ata_dev_warn_once(dev,
+				  "Invalid log directory version 0x%04x\n",
+				  version);
+
+	return 0;
+}
+
+static int ata_log_supported(struct ata_device *dev, u8 log)
+{
+	if (dev->quirks & ATA_QUIRK_NO_LOG_DIR)
+		return 0;
+
+	if (ata_read_log_directory(dev))
+		return 0;
+
+	return get_unaligned_le16(&dev->gp_log_dir[log * 2]);
 }
 
 static bool ata_identify_page_supported(struct ata_device *dev, u8 page)
 {
-	struct ata_port *ap = dev->link->ap;
 	unsigned int err, i;
 
+	if (dev->quirks & ATA_QUIRK_NO_ID_DEV_LOG)
+		return false;
+
 	if (!ata_log_supported(dev, ATA_LOG_IDENTIFY_DEVICE)) {
-		ata_dev_warn(dev, "ATA Identify Device Log not supported\n");
+		/*
+		 * IDENTIFY DEVICE data log is defined as mandatory starting
+		 * with ACS-3 (ATA version 10). Warn about the missing log
+		 * for drives which implement this ATA level or above.
+		 */
+		if (ata_id_major_version(dev->id) >= 10)
+			ata_dev_warn(dev,
+				"ATA Identify Device Log not supported\n");
+		dev->quirks |= ATA_QUIRK_NO_ID_DEV_LOG;
 		return false;
 	}
 
@@ -2057,24 +2217,20 @@ static bool ata_identify_page_supported(struct ata_device *dev, u8 page)
 	 * Read IDENTIFY DEVICE data log, page 0, to figure out if the page is
 	 * supported.
 	 */
-	err = ata_read_log_page(dev, ATA_LOG_IDENTIFY_DEVICE, 0, ap->sector_buf,
-				1);
-	if (err) {
-		ata_dev_info(dev,
-			     "failed to get Device Identify Log Emask 0x%x\n",
-			     err);
+	err = ata_read_log_page(dev, ATA_LOG_IDENTIFY_DEVICE, 0,
+				dev->sector_buf, 1);
+	if (err)
 		return false;
-	}
 
-	for (i = 0; i < ap->sector_buf[8]; i++) {
-		if (ap->sector_buf[9 + i] == page)
+	for (i = 0; i < dev->sector_buf[8]; i++) {
+		if (dev->sector_buf[9 + i] == page)
 			return true;
 	}
 
 	return false;
 }
 
-static int ata_do_link_spd_horkage(struct ata_device *dev)
+static int ata_do_link_spd_quirk(struct ata_device *dev)
 {
 	struct ata_link *plink = ata_dev_phys_link(dev);
 	u32 target, target_limit;
@@ -2082,7 +2238,7 @@ static int ata_do_link_spd_horkage(struct ata_device *dev)
 	if (!sata_scr_valid(plink))
 		return 0;
 
-	if (dev->horkage & ATA_HORKAGE_1_5_GBPS)
+	if (dev->quirks & ATA_QUIRK_1_5_GBPS)
 		target = 1;
 	else
 		return 0;
@@ -2100,26 +2256,25 @@ static int ata_do_link_spd_horkage(struct ata_device *dev)
 	 * guaranteed by setting sata_spd_limit to target_limit above.
 	 */
 	if (plink->sata_spd > target) {
-		ata_dev_info(dev, "applying link speed limit horkage to %s\n",
+		ata_dev_info(dev, "applying link speed limit quirk to %s\n",
 			     sata_spd_string(target));
 		return -EAGAIN;
 	}
 	return 0;
 }
 
-static inline u8 ata_dev_knobble(struct ata_device *dev)
+static inline bool ata_dev_knobble(struct ata_device *dev)
 {
 	struct ata_port *ap = dev->link->ap;
 
-	if (ata_dev_blacklisted(dev) & ATA_HORKAGE_BRIDGE_OK)
-		return 0;
+	if (ata_dev_quirks(dev) & ATA_QUIRK_BRIDGE_OK)
+		return false;
 
 	return ((ap->cbl == ATA_CBL_SATA) && (!ata_id_is_sata(dev->id)));
 }
 
 static void ata_dev_config_ncq_send_recv(struct ata_device *dev)
 {
-	struct ata_port *ap = dev->link->ap;
 	unsigned int err_mask;
 
 	if (!ata_log_supported(dev, ATA_LOG_NCQ_SEND_RECV)) {
@@ -2127,18 +2282,14 @@ static void ata_dev_config_ncq_send_recv(struct ata_device *dev)
 		return;
 	}
 	err_mask = ata_read_log_page(dev, ATA_LOG_NCQ_SEND_RECV,
-				     0, ap->sector_buf, 1);
-	if (err_mask) {
-		ata_dev_dbg(dev,
-			    "failed to get NCQ Send/Recv Log Emask 0x%x\n",
-			    err_mask);
-	} else {
+				     0, dev->sector_buf, 1);
+	if (!err_mask) {
 		u8 *cmds = dev->ncq_send_recv_cmds;
 
 		dev->flags |= ATA_DFLAG_NCQ_SEND_RECV;
-		memcpy(cmds, ap->sector_buf, ATA_LOG_NCQ_SEND_RECV_SIZE);
+		memcpy(cmds, dev->sector_buf, ATA_LOG_NCQ_SEND_RECV_SIZE);
 
-		if (dev->horkage & ATA_HORKAGE_NO_NCQ_TRIM) {
+		if (dev->quirks & ATA_QUIRK_NO_NCQ_TRIM) {
 			ata_dev_dbg(dev, "disabling queued TRIM support\n");
 			cmds[ATA_LOG_NCQ_SEND_RECV_DSM_OFFSET] &=
 				~ATA_LOG_NCQ_SEND_RECV_DSM_TRIM;
@@ -2148,56 +2299,63 @@ static void ata_dev_config_ncq_send_recv(struct ata_device *dev)
 
 static void ata_dev_config_ncq_non_data(struct ata_device *dev)
 {
-	struct ata_port *ap = dev->link->ap;
 	unsigned int err_mask;
 
 	if (!ata_log_supported(dev, ATA_LOG_NCQ_NON_DATA)) {
 		ata_dev_warn(dev,
-			     "NCQ Send/Recv Log not supported\n");
+			     "NCQ Non-Data Log not supported\n");
 		return;
 	}
 	err_mask = ata_read_log_page(dev, ATA_LOG_NCQ_NON_DATA,
-				     0, ap->sector_buf, 1);
-	if (err_mask) {
-		ata_dev_dbg(dev,
-			    "failed to get NCQ Non-Data Log Emask 0x%x\n",
-			    err_mask);
-	} else {
-		u8 *cmds = dev->ncq_non_data_cmds;
-
-		memcpy(cmds, ap->sector_buf, ATA_LOG_NCQ_NON_DATA_SIZE);
-	}
+				     0, dev->sector_buf, 1);
+	if (!err_mask)
+		memcpy(dev->ncq_non_data_cmds, dev->sector_buf,
+		       ATA_LOG_NCQ_NON_DATA_SIZE);
 }
 
 static void ata_dev_config_ncq_prio(struct ata_device *dev)
 {
-	struct ata_port *ap = dev->link->ap;
 	unsigned int err_mask;
 
-	if (!(dev->flags & ATA_DFLAG_NCQ_PRIO_ENABLE)) {
-		dev->flags &= ~ATA_DFLAG_NCQ_PRIO;
+	if (!ata_identify_page_supported(dev, ATA_LOG_SATA_SETTINGS))
 		return;
-	}
 
 	err_mask = ata_read_log_page(dev,
 				     ATA_LOG_IDENTIFY_DEVICE,
 				     ATA_LOG_SATA_SETTINGS,
-				     ap->sector_buf,
-				     1);
-	if (err_mask) {
-		ata_dev_dbg(dev,
-			    "failed to get Identify Device data, Emask 0x%x\n",
-			    err_mask);
-		return;
-	}
+				     dev->sector_buf, 1);
+	if (err_mask)
+		goto not_supported;
 
-	if (ap->sector_buf[ATA_LOG_NCQ_PRIO_OFFSET] & BIT(3)) {
-		dev->flags |= ATA_DFLAG_NCQ_PRIO;
-	} else {
-		dev->flags &= ~ATA_DFLAG_NCQ_PRIO;
-		ata_dev_dbg(dev, "SATA page does not support priority\n");
+	if (!(dev->sector_buf[ATA_LOG_NCQ_PRIO_OFFSET] & BIT(3)))
+		goto not_supported;
+
+	dev->flags |= ATA_DFLAG_NCQ_PRIO;
+
+	return;
+
+not_supported:
+	dev->flags &= ~ATA_DFLAG_NCQ_PRIO_ENABLED;
+	dev->flags &= ~ATA_DFLAG_NCQ_PRIO;
+}
+
+static bool ata_dev_check_adapter(struct ata_device *dev,
+				  unsigned short vendor_id)
+{
+	struct pci_dev *pcidev = NULL;
+	struct device *parent_dev = NULL;
+
+	for (parent_dev = dev->tdev.parent; parent_dev != NULL;
+	     parent_dev = parent_dev->parent) {
+		if (dev_is_pci(parent_dev)) {
+			pcidev = to_pci_dev(parent_dev);
+			if (pcidev->vendor == vendor_id)
+				return true;
+			break;
+		}
 	}
 
+	return false;
 }
 
 static int ata_dev_config_ncq(struct ata_device *dev,
@@ -2214,16 +2372,23 @@ static int ata_dev_config_ncq(struct ata_device *dev,
 	}
 	if (!IS_ENABLED(CONFIG_SATA_HOST))
 		return 0;
-	if (dev->horkage & ATA_HORKAGE_NONCQ) {
+	if (dev->quirks & ATA_QUIRK_NONCQ) {
 		snprintf(desc, desc_sz, "NCQ (not used)");
 		return 0;
 	}
+
+	if (dev->quirks & ATA_QUIRK_NO_NCQ_ON_ATI &&
+	    ata_dev_check_adapter(dev, PCI_VENDOR_ID_ATI)) {
+		snprintf(desc, desc_sz, "NCQ (not used)");
+		return 0;
+	}
+
 	if (ap->flags & ATA_FLAG_NCQ) {
 		hdepth = min(ap->scsi_host->can_queue, ATA_MAX_QUEUE);
 		dev->flags |= ATA_DFLAG_NCQ;
 	}
 
-	if (!(dev->horkage & ATA_HORKAGE_BROKEN_FPDMA_AA) &&
+	if (!(dev->quirks & ATA_QUIRK_BROKEN_FPDMA_AA) &&
 		(ap->flags & ATA_FLAG_FPDMA_AA) &&
 		ata_id_has_fpdma_aa(dev->id)) {
 		err_mask = ata_dev_set_feature(dev, SETFEATURES_SATA_ENABLE,
@@ -2233,7 +2398,7 @@ static int ata_dev_config_ncq(struct ata_device *dev,
 				    "failed to enable AA (error_mask=0x%x)\n",
 				    err_mask);
 			if (err_mask != AC_ERR_DEV) {
-				dev->horkage |= ATA_HORKAGE_BROKEN_FPDMA_AA;
+				dev->quirks |= ATA_QUIRK_BROKEN_FPDMA_AA;
 				return -EIO;
 			}
 		} else
@@ -2278,26 +2443,14 @@ static void ata_dev_config_sense_reporting(struct ata_device *dev)
 
 static void ata_dev_config_zac(struct ata_device *dev)
 {
-	struct ata_port *ap = dev->link->ap;
 	unsigned int err_mask;
-	u8 *identify_buf = ap->sector_buf;
+	u8 *identify_buf = dev->sector_buf;
 
 	dev->zac_zones_optimal_open = U32_MAX;
 	dev->zac_zones_optimal_nonseq = U32_MAX;
 	dev->zac_zones_max_open = U32_MAX;
 
-	/*
-	 * Always set the 'ZAC' flag for Host-managed devices.
-	 */
-	if (dev->class == ATA_DEV_ZAC)
-		dev->flags |= ATA_DFLAG_ZAC;
-	else if (ata_id_zoned_cap(dev->id) == 0x01)
-		/*
-		 * Check for host-aware devices.
-		 */
-		dev->flags |= ATA_DFLAG_ZAC;
-
-	if (!(dev->flags & ATA_DFLAG_ZAC))
+	if (!ata_dev_is_zac(dev))
 		return;
 
 	if (!ata_identify_page_supported(dev, ATA_LOG_ZONED_INFORMATION)) {
@@ -2332,7 +2485,6 @@ static void ata_dev_config_zac(struct ata_device *dev)
 
 static void ata_dev_config_trusted(struct ata_device *dev)
 {
-	struct ata_port *ap = dev->link->ap;
 	u64 trusted_cap;
 	unsigned int err;
 
@@ -2346,14 +2498,11 @@ static void ata_dev_config_trusted(struct ata_device *dev)
 	}
 
 	err = ata_read_log_page(dev, ATA_LOG_IDENTIFY_DEVICE, ATA_LOG_SECURITY,
-			ap->sector_buf, 1);
-	if (err) {
-		ata_dev_dbg(dev,
-			    "failed to read Security Log, Emask 0x%x\n", err);
+				dev->sector_buf, 1);
+	if (err)
 		return;
-	}
 
-	trusted_cap = get_unaligned_le64(&ap->sector_buf[40]);
+	trusted_cap = get_unaligned_le64(&dev->sector_buf[40]);
 	if (!(trusted_cap & (1ULL << 63))) {
 		ata_dev_dbg(dev,
 			    "Trusted Computing capability qword not valid!\n");
@@ -2364,6 +2513,382 @@ static void ata_dev_config_trusted(struct ata_device *dev)
 		dev->flags |= ATA_DFLAG_TRUSTED;
 }
 
+static void ata_dev_cleanup_cdl_resources(struct ata_device *dev)
+{
+	kfree(dev->cdl);
+	dev->cdl = NULL;
+}
+
+static int ata_dev_init_cdl_resources(struct ata_device *dev)
+{
+	struct ata_cdl *cdl = dev->cdl;
+	unsigned int err_mask;
+
+	if (!cdl) {
+		cdl = kzalloc(sizeof(*cdl), GFP_KERNEL);
+		if (!cdl)
+			return -ENOMEM;
+		dev->cdl = cdl;
+	}
+
+	err_mask = ata_read_log_page(dev, ATA_LOG_CDL, 0, cdl->desc_log_buf,
+				     ATA_LOG_CDL_SIZE / ATA_SECT_SIZE);
+	if (err_mask) {
+		ata_dev_warn(dev, "Read Command Duration Limits log failed\n");
+		ata_dev_cleanup_cdl_resources(dev);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static void ata_dev_config_cdl(struct ata_device *dev)
+{
+	unsigned int err_mask;
+	bool cdl_enabled;
+	u64 val;
+	int ret;
+
+	if (ata_id_major_version(dev->id) < 11)
+		goto not_supported;
+
+	if (!ata_log_supported(dev, ATA_LOG_IDENTIFY_DEVICE) ||
+	    !ata_identify_page_supported(dev, ATA_LOG_SUPPORTED_CAPABILITIES) ||
+	    !ata_identify_page_supported(dev, ATA_LOG_CURRENT_SETTINGS))
+		goto not_supported;
+
+	err_mask = ata_read_log_page(dev, ATA_LOG_IDENTIFY_DEVICE,
+				     ATA_LOG_SUPPORTED_CAPABILITIES,
+				     dev->sector_buf, 1);
+	if (err_mask)
+		goto not_supported;
+
+	/* Check Command Duration Limit Supported bits */
+	val = get_unaligned_le64(&dev->sector_buf[168]);
+	if (!(val & BIT_ULL(63)) || !(val & BIT_ULL(0)))
+		goto not_supported;
+
+	/* Warn the user if command duration guideline is not supported */
+	if (!(val & BIT_ULL(1)))
+		ata_dev_warn(dev,
+			"Command duration guideline is not supported\n");
+
+	/*
+	 * We must have support for the sense data for successful NCQ commands
+	 * log indicated by the successful NCQ command sense data supported bit.
+	 */
+	val = get_unaligned_le64(&dev->sector_buf[8]);
+	if (!(val & BIT_ULL(63)) || !(val & BIT_ULL(47))) {
+		ata_dev_warn(dev,
+			"CDL supported but Successful NCQ Command Sense Data is not supported\n");
+		goto not_supported;
+	}
+
+	/* Without NCQ autosense, the successful NCQ commands log is useless. */
+	if (!ata_id_has_ncq_autosense(dev->id)) {
+		ata_dev_warn(dev,
+			"CDL supported but NCQ autosense is not supported\n");
+		goto not_supported;
+	}
+
+	/*
+	 * If CDL is marked as enabled, make sure the feature is enabled too.
+	 * Conversely, if CDL is disabled, make sure the feature is turned off.
+	 */
+	err_mask = ata_read_log_page(dev, ATA_LOG_IDENTIFY_DEVICE,
+				     ATA_LOG_CURRENT_SETTINGS,
+				     dev->sector_buf, 1);
+	if (err_mask)
+		goto not_supported;
+
+	val = get_unaligned_le64(&dev->sector_buf[8]);
+	cdl_enabled = val & BIT_ULL(63) && val & BIT_ULL(21);
+	if (dev->flags & ATA_DFLAG_CDL_ENABLED) {
+		if (!cdl_enabled) {
+			/* Enable CDL on the device */
+			err_mask = ata_dev_set_feature(dev, SETFEATURES_CDL, 1);
+			if (err_mask) {
+				ata_dev_err(dev,
+					    "Enable CDL feature failed\n");
+				goto not_supported;
+			}
+		}
+	} else {
+		if (cdl_enabled) {
+			/* Disable CDL on the device */
+			err_mask = ata_dev_set_feature(dev, SETFEATURES_CDL, 0);
+			if (err_mask) {
+				ata_dev_err(dev,
+					    "Disable CDL feature failed\n");
+				goto not_supported;
+			}
+		}
+	}
+
+	/*
+	 * While CDL itself has to be enabled using sysfs, CDL requires that
+	 * sense data for successful NCQ commands is enabled to work properly.
+	 * Just like ata_dev_config_sense_reporting(), enable it unconditionally
+	 * if supported.
+	 */
+	if (!(val & BIT_ULL(63)) || !(val & BIT_ULL(18))) {
+		err_mask = ata_dev_set_feature(dev,
+					SETFEATURE_SENSE_DATA_SUCC_NCQ, 0x1);
+		if (err_mask) {
+			ata_dev_warn(dev,
+				     "failed to enable Sense Data for successful NCQ commands, Emask 0x%x\n",
+				     err_mask);
+			goto not_supported;
+		}
+	}
+
+	/* CDL is supported: allocate and initialize needed resources. */
+	ret = ata_dev_init_cdl_resources(dev);
+	if (ret) {
+		ata_dev_warn(dev, "Initialize CDL resources failed\n");
+		goto not_supported;
+	}
+
+	dev->flags |= ATA_DFLAG_CDL;
+
+	return;
+
+not_supported:
+	dev->flags &= ~(ATA_DFLAG_CDL | ATA_DFLAG_CDL_ENABLED);
+	ata_dev_cleanup_cdl_resources(dev);
+}
+
+static int ata_dev_config_lba(struct ata_device *dev)
+{
+	const u16 *id = dev->id;
+	const char *lba_desc;
+	char ncq_desc[32];
+	int ret;
+
+	dev->flags |= ATA_DFLAG_LBA;
+
+	if (ata_id_has_lba48(id)) {
+		lba_desc = "LBA48";
+		dev->flags |= ATA_DFLAG_LBA48;
+		if (dev->n_sectors >= (1UL << 28) &&
+		    ata_id_has_flush_ext(id))
+			dev->flags |= ATA_DFLAG_FLUSH_EXT;
+	} else {
+		lba_desc = "LBA";
+	}
+
+	/* config NCQ */
+	ret = ata_dev_config_ncq(dev, ncq_desc, sizeof(ncq_desc));
+
+	/* print device info to dmesg */
+	if (ata_dev_print_info(dev))
+		ata_dev_info(dev,
+			     "%llu sectors, multi %u: %s %s\n",
+			     (unsigned long long)dev->n_sectors,
+			     dev->multi_count, lba_desc, ncq_desc);
+
+	return ret;
+}
+
+static void ata_dev_config_chs(struct ata_device *dev)
+{
+	const u16 *id = dev->id;
+
+	if (ata_id_current_chs_valid(id)) {
+		/* Current CHS translation is valid. */
+		dev->cylinders = id[54];
+		dev->heads     = id[55];
+		dev->sectors   = id[56];
+	} else {
+		/* Default translation */
+		dev->cylinders	= id[1];
+		dev->heads	= id[3];
+		dev->sectors	= id[6];
+	}
+
+	/* print device info to dmesg */
+	if (ata_dev_print_info(dev))
+		ata_dev_info(dev,
+			     "%llu sectors, multi %u, CHS %u/%u/%u\n",
+			     (unsigned long long)dev->n_sectors,
+			     dev->multi_count, dev->cylinders,
+			     dev->heads, dev->sectors);
+}
+
+static void ata_dev_config_fua(struct ata_device *dev)
+{
+	/* Ignore FUA support if its use is disabled globally */
+	if (!libata_fua)
+		goto nofua;
+
+	/* Ignore devices without support for WRITE DMA FUA EXT */
+	if (!(dev->flags & ATA_DFLAG_LBA48) || !ata_id_has_fua(dev->id))
+		goto nofua;
+
+	/* Ignore known bad devices and devices that lack NCQ support */
+	if (!ata_ncq_supported(dev) || (dev->quirks & ATA_QUIRK_NO_FUA))
+		goto nofua;
+
+	dev->flags |= ATA_DFLAG_FUA;
+
+	return;
+
+nofua:
+	dev->flags &= ~ATA_DFLAG_FUA;
+}
+
+static void ata_dev_config_devslp(struct ata_device *dev)
+{
+	u8 *sata_setting = dev->sector_buf;
+	unsigned int err_mask;
+	int i, j;
+
+	/*
+	 * Check device sleep capability. Get DevSlp timing variables
+	 * from SATA Settings page of Identify Device Data Log.
+	 */
+	if (!ata_id_has_devslp(dev->id) ||
+	    !ata_identify_page_supported(dev, ATA_LOG_SATA_SETTINGS))
+		return;
+
+	err_mask = ata_read_log_page(dev,
+				     ATA_LOG_IDENTIFY_DEVICE,
+				     ATA_LOG_SATA_SETTINGS,
+				     sata_setting, 1);
+	if (err_mask)
+		return;
+
+	dev->flags |= ATA_DFLAG_DEVSLP;
+	for (i = 0; i < ATA_LOG_DEVSLP_SIZE; i++) {
+		j = ATA_LOG_DEVSLP_OFFSET + i;
+		dev->devslp_timing[i] = sata_setting[j];
+	}
+}
+
+static void ata_dev_config_cpr(struct ata_device *dev)
+{
+	unsigned int err_mask;
+	size_t buf_len;
+	int i, nr_cpr = 0;
+	struct ata_cpr_log *cpr_log = NULL;
+	u8 *desc, *buf = NULL;
+
+	if (ata_id_major_version(dev->id) < 11)
+		goto out;
+
+	buf_len = ata_log_supported(dev, ATA_LOG_CONCURRENT_POSITIONING_RANGES);
+	if (buf_len == 0)
+		goto out;
+
+	/*
+	 * Read the concurrent positioning ranges log (0x47). We can have at
+	 * most 255 32B range descriptors plus a 64B header. This log varies in
+	 * size, so use the size reported in the GPL directory. Reading beyond
+	 * the supported length will result in an error.
+	 */
+	buf_len <<= 9;
+	buf = kzalloc(buf_len, GFP_KERNEL);
+	if (!buf)
+		goto out;
+
+	err_mask = ata_read_log_page(dev, ATA_LOG_CONCURRENT_POSITIONING_RANGES,
+				     0, buf, buf_len >> 9);
+	if (err_mask)
+		goto out;
+
+	nr_cpr = buf[0];
+	if (!nr_cpr)
+		goto out;
+
+	cpr_log = kzalloc(struct_size(cpr_log, cpr, nr_cpr), GFP_KERNEL);
+	if (!cpr_log)
+		goto out;
+
+	cpr_log->nr_cpr = nr_cpr;
+	desc = &buf[64];
+	for (i = 0; i < nr_cpr; i++, desc += 32) {
+		cpr_log->cpr[i].num = desc[0];
+		cpr_log->cpr[i].num_storage_elements = desc[1];
+		cpr_log->cpr[i].start_lba = get_unaligned_le64(&desc[8]);
+		cpr_log->cpr[i].num_lbas = get_unaligned_le64(&desc[16]);
+	}
+
+out:
+	swap(dev->cpr_log, cpr_log);
+	kfree(cpr_log);
+	kfree(buf);
+}
+
+/*
+ * Configure features related to link power management.
+ */
+static void ata_dev_config_lpm(struct ata_device *dev)
+{
+	struct ata_port *ap = dev->link->ap;
+	unsigned int err_mask;
+
+	if (ap->flags & ATA_FLAG_NO_LPM) {
+		/*
+		 * When the port does not support LPM, we cannot support it on
+		 * the device either.
+		 */
+		dev->quirks |= ATA_QUIRK_NOLPM;
+	} else {
+		/*
+		 * Some WD SATA-1 drives have issues with LPM, turn on NOLPM for
+		 * them.
+		 */
+		if ((dev->quirks & ATA_QUIRK_WD_BROKEN_LPM) &&
+		    (dev->id[ATA_ID_SATA_CAPABILITY] & 0xe) == 0x2)
+			dev->quirks |= ATA_QUIRK_NOLPM;
+
+		/* ATI specific quirk */
+		if ((dev->quirks & ATA_QUIRK_NO_LPM_ON_ATI) &&
+		    ata_dev_check_adapter(dev, PCI_VENDOR_ID_ATI))
+			dev->quirks |= ATA_QUIRK_NOLPM;
+	}
+
+	if (dev->quirks & ATA_QUIRK_NOLPM &&
+	    ap->target_lpm_policy != ATA_LPM_MAX_POWER) {
+		ata_dev_warn(dev, "LPM support broken, forcing max_power\n");
+		ap->target_lpm_policy = ATA_LPM_MAX_POWER;
+	}
+
+	/*
+	 * Device Initiated Power Management (DIPM) is normally disabled by
+	 * default on a device. However, DIPM may have been enabled and that
+	 * setting kept even after COMRESET because of the Software Settings
+	 * Preservation feature. So if the port does not support DIPM and the
+	 * device does, disable DIPM on the device.
+	 */
+	if (ap->flags & ATA_FLAG_NO_DIPM && ata_id_has_dipm(dev->id)) {
+		err_mask = ata_dev_set_feature(dev,
+					SETFEATURES_SATA_DISABLE, SATA_DIPM);
+		if (err_mask && err_mask != AC_ERR_DEV)
+			ata_dev_err(dev, "Disable DIPM failed, Emask 0x%x\n",
+				    err_mask);
+	}
+}
+
+static void ata_dev_print_features(struct ata_device *dev)
+{
+	if (!(dev->flags & ATA_DFLAG_FEATURES_MASK))
+		return;
+
+	ata_dev_info(dev,
+		     "Features:%s%s%s%s%s%s%s%s%s%s\n",
+		     dev->flags & ATA_DFLAG_FUA ? " FUA" : "",
+		     dev->flags & ATA_DFLAG_TRUSTED ? " Trust" : "",
+		     dev->flags & ATA_DFLAG_DA ? " Dev-Attention" : "",
+		     dev->flags & ATA_DFLAG_DEVSLP ? " Dev-Sleep" : "",
+		     ata_id_has_hipm(dev->id) ? " HIPM" : "",
+		     ata_id_has_dipm(dev->id) ? " DIPM" : "",
+		     dev->flags & ATA_DFLAG_NCQ_SEND_RECV ? " NCQ-sndrcv" : "",
+		     dev->flags & ATA_DFLAG_NCQ_PRIO ? " NCQ-prio" : "",
+		     dev->flags & ATA_DFLAG_CDL ? " CDL" : "",
+		     dev->cpr_log ? " CPR" : "");
+}
+
 /**
  *	ata_dev_configure - Configure the specified ATA/ATAPI device
  *	@dev: Target device to configure
@@ -2380,29 +2905,28 @@ static void ata_dev_config_trusted(struct ata_device *dev)
 int ata_dev_configure(struct ata_device *dev)
 {
 	struct ata_port *ap = dev->link->ap;
-	struct ata_eh_context *ehc = &dev->link->eh_context;
-	int print_info = ehc->i.flags & ATA_EHI_PRINTINFO;
+	bool print_info = ata_dev_print_info(dev);
 	const u16 *id = dev->id;
-	unsigned long xfer_mask;
+	unsigned int xfer_mask;
 	unsigned int err_mask;
 	char revbuf[7];		/* XYZ-99\0 */
 	char fwrevbuf[ATA_ID_FW_REV_LEN+1];
 	char modelbuf[ATA_ID_PROD_LEN+1];
 	int rc;
 
-	if (!ata_dev_enabled(dev) && ata_msg_info(ap)) {
-		ata_dev_info(dev, "%s: ENTER/EXIT -- nodev\n", __func__);
+	if (!ata_dev_enabled(dev)) {
+		ata_dev_dbg(dev, "no device\n");
 		return 0;
 	}
 
-	if (ata_msg_probe(ap))
-		ata_dev_dbg(dev, "%s: ENTER\n", __func__);
+	/* Clear the general purpose log directory cache. */
+	ata_clear_log_directory(dev);
 
-	/* set horkage */
-	dev->horkage |= ata_dev_blacklisted(dev);
-	ata_force_horkage(dev);
+	/* Set quirks */
+	dev->quirks |= ata_dev_quirks(dev);
+	ata_force_quirks(dev);
 
-	if (dev->horkage & ATA_HORKAGE_DISABLE) {
+	if (dev->quirks & ATA_QUIRK_DISABLE) {
 		ata_dev_info(dev, "unsupported device, disabling\n");
 		ata_dev_disable(dev);
 		return 0;
@@ -2417,23 +2941,10 @@ int ata_dev_configure(struct ata_device *dev)
 		return 0;
 	}
 
-	rc = ata_do_link_spd_horkage(dev);
+	rc = ata_do_link_spd_quirk(dev);
 	if (rc)
 		return rc;
 
-	/* some WD SATA-1 drives have issues with LPM, turn on NOLPM for them */
-	if ((dev->horkage & ATA_HORKAGE_WD_BROKEN_LPM) &&
-	    (id[ATA_ID_SATA_CAPABILITY] & 0xe) == 0x2)
-		dev->horkage |= ATA_HORKAGE_NOLPM;
-
-	if (ap->flags & ATA_FLAG_NO_LPM)
-		dev->horkage |= ATA_HORKAGE_NOLPM;
-
-	if (dev->horkage & ATA_HORKAGE_NOLPM) {
-		ata_dev_warn(dev, "LPM support broken, forcing max_power\n");
-		dev->link->ap->target_lpm_policy = ATA_LPM_MAX_POWER;
-	}
-
 	/* let ACPI work its magic */
 	rc = ata_acpi_on_devcfg(dev);
 	if (rc)
@@ -2445,13 +2956,12 @@ int ata_dev_configure(struct ata_device *dev)
 		return rc;
 
 	/* print device capabilities */
-	if (ata_msg_probe(ap))
-		ata_dev_dbg(dev,
-			    "%s: cfg 49:%04x 82:%04x 83:%04x 84:%04x "
-			    "85:%04x 86:%04x 87:%04x 88:%04x\n",
-			    __func__,
-			    id[49], id[82], id[83], id[84],
-			    id[85], id[86], id[87], id[88]);
+	ata_dev_dbg(dev,
+		    "%s: cfg 49:%04x 82:%04x 83:%04x 84:%04x "
+		    "85:%04x 86:%04x 87:%04x 88:%04x\n",
+		    __func__,
+		    id[49], id[82], id[83], id[84],
+		    id[85], id[86], id[87], id[88]);
 
 	/* initialize to-be-configured parameters */
 	dev->flags &= ~ATA_DFLAG_CFG_MASK;
@@ -2470,8 +2980,7 @@ int ata_dev_configure(struct ata_device *dev)
 	/* find max transfer mode; for printk only */
 	xfer_mask = ata_id_xfermask(id);
 
-	if (ata_msg_probe(ap))
-		ata_dump_id(id);
+	ata_dump_id(dev, id);
 
 	/* SCSI only uses 4-char revisions, dump full 8 chars from ATA */
 	ata_id_c_string(dev->id, fwrevbuf, ATA_ID_FW_REV,
@@ -2497,6 +3006,16 @@ int ata_dev_configure(struct ata_device *dev)
 		}
 
 		dev->n_sectors = ata_id_n_sectors(id);
+		if (ata_id_is_locked(id)) {
+			/*
+			 * If Security locked, set capacity to zero to prevent
+			 * any I/O, e.g. partition scanning, as any I/O to a
+			 * locked drive will result in user visible errors.
+			 */
+			ata_dev_info(dev,
+				"Security locked, setting capacity to zero\n");
+			dev->n_sectors = 0;
+		}
 
 		/* get current R/W Multiple count setting */
 		if ((dev->id[47] >> 8) == 0x80 && (dev->id[59] & 0x100)) {
@@ -2508,91 +3027,32 @@ int ata_dev_configure(struct ata_device *dev)
 					dev->multi_count = cnt;
 		}
 
-		if (ata_id_has_lba(id)) {
-			const char *lba_desc;
-			char ncq_desc[24];
-
-			lba_desc = "LBA";
-			dev->flags |= ATA_DFLAG_LBA;
-			if (ata_id_has_lba48(id)) {
-				dev->flags |= ATA_DFLAG_LBA48;
-				lba_desc = "LBA48";
-
-				if (dev->n_sectors >= (1UL << 28) &&
-				    ata_id_has_flush_ext(id))
-					dev->flags |= ATA_DFLAG_FLUSH_EXT;
-			}
+		/* print device info to dmesg */
+		if (print_info)
+			ata_dev_info(dev, "%s: %s, %s, max %s\n",
+				     revbuf, modelbuf, fwrevbuf,
+				     ata_mode_string(xfer_mask));
 
-			/* config NCQ */
-			rc = ata_dev_config_ncq(dev, ncq_desc, sizeof(ncq_desc));
+		if (ata_id_has_lba(id)) {
+			rc = ata_dev_config_lba(dev);
 			if (rc)
 				return rc;
-
-			/* print device info to dmesg */
-			if (ata_msg_drv(ap) && print_info) {
-				ata_dev_info(dev, "%s: %s, %s, max %s\n",
-					     revbuf, modelbuf, fwrevbuf,
-					     ata_mode_string(xfer_mask));
-				ata_dev_info(dev,
-					     "%llu sectors, multi %u: %s %s\n",
-					(unsigned long long)dev->n_sectors,
-					dev->multi_count, lba_desc, ncq_desc);
-			}
 		} else {
-			/* CHS */
-
-			/* Default translation */
-			dev->cylinders	= id[1];
-			dev->heads	= id[3];
-			dev->sectors	= id[6];
-
-			if (ata_id_current_chs_valid(id)) {
-				/* Current CHS translation is valid. */
-				dev->cylinders = id[54];
-				dev->heads     = id[55];
-				dev->sectors   = id[56];
-			}
-
-			/* print device info to dmesg */
-			if (ata_msg_drv(ap) && print_info) {
-				ata_dev_info(dev, "%s: %s, %s, max %s\n",
-					     revbuf,	modelbuf, fwrevbuf,
-					     ata_mode_string(xfer_mask));
-				ata_dev_info(dev,
-					     "%llu sectors, multi %u, CHS %u/%u/%u\n",
-					     (unsigned long long)dev->n_sectors,
-					     dev->multi_count, dev->cylinders,
-					     dev->heads, dev->sectors);
-			}
+			ata_dev_config_chs(dev);
 		}
 
-		/* Check and mark DevSlp capability. Get DevSlp timing variables
-		 * from SATA Settings page of Identify Device Data Log.
-		 */
-		if (ata_id_has_devslp(dev->id)) {
-			u8 *sata_setting = ap->sector_buf;
-			int i, j;
-
-			dev->flags |= ATA_DFLAG_DEVSLP;
-			err_mask = ata_read_log_page(dev,
-						     ATA_LOG_IDENTIFY_DEVICE,
-						     ATA_LOG_SATA_SETTINGS,
-						     sata_setting,
-						     1);
-			if (err_mask)
-				ata_dev_dbg(dev,
-					    "failed to get Identify Device Data, Emask 0x%x\n",
-					    err_mask);
-			else
-				for (i = 0; i < ATA_LOG_DEVSLP_SIZE; i++) {
-					j = ATA_LOG_DEVSLP_OFFSET + i;
-					dev->devslp_timing[i] = sata_setting[j];
-				}
-		}
+		ata_dev_config_lpm(dev);
+		ata_dev_config_fua(dev);
+		ata_dev_config_devslp(dev);
 		ata_dev_config_sense_reporting(dev);
 		ata_dev_config_zac(dev);
 		ata_dev_config_trusted(dev);
+		ata_dev_config_cpr(dev);
+		ata_dev_config_cdl(dev);
 		dev->cdb_len = 32;
+
+		if (print_info)
+			ata_dev_print_features(dev);
 	}
 
 	/* ATAPI-specific feature tests */
@@ -2604,8 +3064,7 @@ int ata_dev_configure(struct ata_device *dev)
 
 		rc = atapi_cdb_len(id);
 		if ((rc < 12) || (rc > ATAPI_CDB_LEN)) {
-			if (ata_msg_warn(ap))
-				ata_dev_warn(dev, "unsupported CDB len\n");
+			ata_dev_warn(dev, "unsupported CDB len %d\n", rc);
 			rc = -EINVAL;
 			goto err_out_nosup;
 		}
@@ -2638,7 +3097,8 @@ int ata_dev_configure(struct ata_device *dev)
 			cdb_intr_string = ", CDB intr";
 		}
 
-		if (atapi_dmadir || (dev->horkage & ATA_HORKAGE_ATAPI_DMADIR) || atapi_id_dmadir(dev->id)) {
+		if (atapi_dmadir || (dev->quirks & ATA_QUIRK_ATAPI_DMADIR) ||
+		    atapi_id_dmadir(dev->id)) {
 			dev->flags |= ATA_DFLAG_DMADIR;
 			dma_dir_string = ", DMADIR";
 		}
@@ -2649,7 +3109,7 @@ int ata_dev_configure(struct ata_device *dev)
 		}
 
 		/* print device info to dmesg */
-		if (ata_msg_drv(ap) && print_info)
+		if (print_info)
 			ata_dev_info(dev,
 				     "ATAPI: %s, %s, max %s%s%s%s\n",
 				     modelbuf, fwrevbuf,
@@ -2666,7 +3126,7 @@ int ata_dev_configure(struct ata_device *dev)
 	/* Limit PATA drive on SATA cable bridge transfers to udma5,
 	   200 sectors */
 	if (ata_dev_knobble(dev)) {
-		if (ata_msg_drv(ap) && print_info)
+		if (print_info)
 			ata_dev_info(dev, "applying bridge limits\n");
 		dev->udma_mask &= ATA_UDMA5;
 		dev->max_sectors = ATA_MAX_SECTORS;
@@ -2675,24 +3135,28 @@ int ata_dev_configure(struct ata_device *dev)
 	if ((dev->class == ATA_DEV_ATAPI) &&
 	    (atapi_command_packet_set(id) == TYPE_TAPE)) {
 		dev->max_sectors = ATA_MAX_SECTORS_TAPE;
-		dev->horkage |= ATA_HORKAGE_STUCK_ERR;
+		dev->quirks |= ATA_QUIRK_STUCK_ERR;
 	}
 
-	if (dev->horkage & ATA_HORKAGE_MAX_SEC_128)
+	if (dev->quirks & ATA_QUIRK_MAX_SEC_128)
 		dev->max_sectors = min_t(unsigned int, ATA_MAX_SECTORS_128,
 					 dev->max_sectors);
 
-	if (dev->horkage & ATA_HORKAGE_MAX_SEC_1024)
+	if (dev->quirks & ATA_QUIRK_MAX_SEC_1024)
 		dev->max_sectors = min_t(unsigned int, ATA_MAX_SECTORS_1024,
 					 dev->max_sectors);
 
-	if (dev->horkage & ATA_HORKAGE_MAX_SEC_LBA48)
+	if (dev->quirks & ATA_QUIRK_MAX_SEC_8191)
+		dev->max_sectors = min_t(unsigned int, ATA_MAX_SECTORS_8191,
+					 dev->max_sectors);
+
+	if (dev->quirks & ATA_QUIRK_MAX_SEC_LBA48)
 		dev->max_sectors = ATA_MAX_SECTORS_LBA48;
 
 	if (ap->ops->dev_config)
 		ap->ops->dev_config(dev);
 
-	if (dev->horkage & ATA_HORKAGE_DIAGNOSTIC) {
+	if (dev->quirks & ATA_QUIRK_DIAGNOSTIC) {
 		/* Let the user know. We don't want to disallow opens for
 		   rescue purposes, or in case the vendor is just a blithering
 		   idiot. Do this after the dev_config call as some controllers
@@ -2707,7 +3171,7 @@ int ata_dev_configure(struct ata_device *dev)
 		}
 	}
 
-	if ((dev->horkage & ATA_HORKAGE_FIRMWARE_WARN) && print_info) {
+	if ((dev->quirks & ATA_QUIRK_FIRMWARE_WARN) && print_info) {
 		ata_dev_warn(dev, "WARNING: device requires firmware update to be fully functional\n");
 		ata_dev_warn(dev, "         contact the vendor or visit http://ata.wiki.kernel.org\n");
 	}
@@ -2715,8 +3179,6 @@ int ata_dev_configure(struct ata_device *dev)
 	return 0;
 
 err_out_nosup:
-	if (ata_msg_probe(ap))
-		ata_dev_dbg(dev, "%s: EXIT, err\n", __func__);
 	return rc;
 }
 
@@ -2788,144 +3250,6 @@ int ata_cable_sata(struct ata_port *ap)
 EXPORT_SYMBOL_GPL(ata_cable_sata);
 
 /**
- *	ata_bus_probe - Reset and probe ATA bus
- *	@ap: Bus to probe
- *
- *	Master ATA bus probing function.  Initiates a hardware-dependent
- *	bus reset, then attempts to identify any devices found on
- *	the bus.
- *
- *	LOCKING:
- *	PCI/etc. bus probe sem.
- *
- *	RETURNS:
- *	Zero on success, negative errno otherwise.
- */
-
-int ata_bus_probe(struct ata_port *ap)
-{
-	unsigned int classes[ATA_MAX_DEVICES];
-	int tries[ATA_MAX_DEVICES];
-	int rc;
-	struct ata_device *dev;
-
-	ata_for_each_dev(dev, &ap->link, ALL)
-		tries[dev->devno] = ATA_PROBE_MAX_TRIES;
-
- retry:
-	ata_for_each_dev(dev, &ap->link, ALL) {
-		/* If we issue an SRST then an ATA drive (not ATAPI)
-		 * may change configuration and be in PIO0 timing. If
-		 * we do a hard reset (or are coming from power on)
-		 * this is true for ATA or ATAPI. Until we've set a
-		 * suitable controller mode we should not touch the
-		 * bus as we may be talking too fast.
-		 */
-		dev->pio_mode = XFER_PIO_0;
-		dev->dma_mode = 0xff;
-
-		/* If the controller has a pio mode setup function
-		 * then use it to set the chipset to rights. Don't
-		 * touch the DMA setup as that will be dealt with when
-		 * configuring devices.
-		 */
-		if (ap->ops->set_piomode)
-			ap->ops->set_piomode(ap, dev);
-	}
-
-	/* reset and determine device classes */
-	ap->ops->phy_reset(ap);
-
-	ata_for_each_dev(dev, &ap->link, ALL) {
-		if (dev->class != ATA_DEV_UNKNOWN)
-			classes[dev->devno] = dev->class;
-		else
-			classes[dev->devno] = ATA_DEV_NONE;
-
-		dev->class = ATA_DEV_UNKNOWN;
-	}
-
-	/* read IDENTIFY page and configure devices. We have to do the identify
-	   specific sequence bass-ackwards so that PDIAG- is released by
-	   the slave device */
-
-	ata_for_each_dev(dev, &ap->link, ALL_REVERSE) {
-		if (tries[dev->devno])
-			dev->class = classes[dev->devno];
-
-		if (!ata_dev_enabled(dev))
-			continue;
-
-		rc = ata_dev_read_id(dev, &dev->class, ATA_READID_POSTRESET,
-				     dev->id);
-		if (rc)
-			goto fail;
-	}
-
-	/* Now ask for the cable type as PDIAG- should have been released */
-	if (ap->ops->cable_detect)
-		ap->cbl = ap->ops->cable_detect(ap);
-
-	/* We may have SATA bridge glue hiding here irrespective of
-	 * the reported cable types and sensed types.  When SATA
-	 * drives indicate we have a bridge, we don't know which end
-	 * of the link the bridge is which is a problem.
-	 */
-	ata_for_each_dev(dev, &ap->link, ENABLED)
-		if (ata_id_is_sata(dev->id))
-			ap->cbl = ATA_CBL_SATA;
-
-	/* After the identify sequence we can now set up the devices. We do
-	   this in the normal order so that the user doesn't get confused */
-
-	ata_for_each_dev(dev, &ap->link, ENABLED) {
-		ap->link.eh_context.i.flags |= ATA_EHI_PRINTINFO;
-		rc = ata_dev_configure(dev);
-		ap->link.eh_context.i.flags &= ~ATA_EHI_PRINTINFO;
-		if (rc)
-			goto fail;
-	}
-
-	/* configure transfer mode */
-	rc = ata_set_mode(&ap->link, &dev);
-	if (rc)
-		goto fail;
-
-	ata_for_each_dev(dev, &ap->link, ENABLED)
-		return 0;
-
-	return -ENODEV;
-
- fail:
-	tries[dev->devno]--;
-
-	switch (rc) {
-	case -EINVAL:
-		/* eeek, something went very wrong, give up */
-		tries[dev->devno] = 0;
-		break;
-
-	case -ENODEV:
-		/* give it just one more chance */
-		tries[dev->devno] = min(tries[dev->devno], 1);
-		/* fall through */
-	case -EIO:
-		if (tries[dev->devno] == 1) {
-			/* This is the last chance, better to slow
-			 * down than lose it.
-			 */
-			sata_down_spd_limit(&ap->link, 0);
-			ata_down_xfermask_limit(dev, ATA_DNXFER_PIO);
-		}
-	}
-
-	if (!tries[dev->devno])
-		ata_dev_disable(dev);
-
-	goto retry;
-}
-
-/**
  *	sata_print_link_status - Print SATA link status
  *	@link: SATA link to printk link status about
  *
@@ -2940,7 +3264,8 @@ static void sata_print_link_status(struct ata_link *link)
 
 	if (sata_scr_read(link, SCR_STATUS, &sstatus))
 		return;
-	sata_scr_read(link, SCR_CONTROL, &scontrol);
+	if (sata_scr_read(link, SCR_CONTROL, &scontrol))
+		return;
 
 	if (ata_phys_link_online(link)) {
 		tmp = (sstatus >> 4) & 0xf;
@@ -2970,86 +3295,6 @@ struct ata_device *ata_dev_pair(struct ata_device *adev)
 }
 EXPORT_SYMBOL_GPL(ata_dev_pair);
 
-/**
- *	sata_down_spd_limit - adjust SATA spd limit downward
- *	@link: Link to adjust SATA spd limit for
- *	@spd_limit: Additional limit
- *
- *	Adjust SATA spd limit of @link downward.  Note that this
- *	function only adjusts the limit.  The change must be applied
- *	using sata_set_spd().
- *
- *	If @spd_limit is non-zero, the speed is limited to equal to or
- *	lower than @spd_limit if such speed is supported.  If
- *	@spd_limit is slower than any supported speed, only the lowest
- *	supported speed is allowed.
- *
- *	LOCKING:
- *	Inherited from caller.
- *
- *	RETURNS:
- *	0 on success, negative errno on failure
- */
-int sata_down_spd_limit(struct ata_link *link, u32 spd_limit)
-{
-	u32 sstatus, spd, mask;
-	int rc, bit;
-
-	if (!sata_scr_valid(link))
-		return -EOPNOTSUPP;
-
-	/* If SCR can be read, use it to determine the current SPD.
-	 * If not, use cached value in link->sata_spd.
-	 */
-	rc = sata_scr_read(link, SCR_STATUS, &sstatus);
-	if (rc == 0 && ata_sstatus_online(sstatus))
-		spd = (sstatus >> 4) & 0xf;
-	else
-		spd = link->sata_spd;
-
-	mask = link->sata_spd_limit;
-	if (mask <= 1)
-		return -EINVAL;
-
-	/* unconditionally mask off the highest bit */
-	bit = fls(mask) - 1;
-	mask &= ~(1 << bit);
-
-	/*
-	 * Mask off all speeds higher than or equal to the current one.  At
-	 * this point, if current SPD is not available and we previously
-	 * recorded the link speed from SStatus, the driver has already
-	 * masked off the highest bit so mask should already be 1 or 0.
-	 * Otherwise, we should not force 1.5Gbps on a link where we have
-	 * not previously recorded speed from SStatus.  Just return in this
-	 * case.
-	 */
-	if (spd > 1)
-		mask &= (1 << (spd - 1)) - 1;
-	else
-		return -EINVAL;
-
-	/* were we already at the bottom? */
-	if (!mask)
-		return -EINVAL;
-
-	if (spd_limit) {
-		if (mask & ((1 << spd_limit) - 1))
-			mask &= (1 << spd_limit) - 1;
-		else {
-			bit = ffs(mask) - 1;
-			mask = 1 << bit;
-		}
-	}
-
-	link->sata_spd_limit = mask;
-
-	ata_link_warn(link, "limiting SATA link speed to %s\n",
-		      sata_spd_string(fls(mask)));
-
-	return 0;
-}
-
 #ifdef CONFIG_ATA_ACPI
 /**
  *	ata_timing_cycle2mode - find xfer mode for the specified cycle duration
@@ -3121,8 +3366,8 @@ u8 ata_timing_cycle2mode(unsigned int xfer_shift, int cycle)
 int ata_down_xfermask_limit(struct ata_device *dev, unsigned int sel)
 {
 	char buf[32];
-	unsigned long orig_mask, xfer_mask;
-	unsigned long pio_mask, mwdma_mask, udma_mask;
+	unsigned int orig_mask, xfer_mask;
+	unsigned int pio_mask, mwdma_mask, udma_mask;
 	int quiet, highbit;
 
 	quiet = !!(sel & ATA_DNXFER_QUIET);
@@ -3159,7 +3404,7 @@ int ata_down_xfermask_limit(struct ata_device *dev, unsigned int sel)
 
 	case ATA_DNXFER_FORCE_PIO0:
 		pio_mask &= 1;
-		/* fall through */
+		fallthrough;
 	case ATA_DNXFER_FORCE_PIO:
 		mwdma_mask = 0;
 		udma_mask = 0;
@@ -3196,7 +3441,7 @@ static int ata_dev_set_mode(struct ata_device *dev)
 {
 	struct ata_port *ap = dev->link->ap;
 	struct ata_eh_context *ehc = &dev->link->eh_context;
-	const bool nosetxfer = dev->horkage & ATA_HORKAGE_NOSETXFER;
+	const bool nosetxfer = dev->quirks & ATA_QUIRK_NOSETXFER;
 	const char *dev_err_whine = "";
 	int ign_dev_err = 0;
 	unsigned int err_mask = 0;
@@ -3259,8 +3504,8 @@ static int ata_dev_set_mode(struct ata_device *dev)
 			dev_err_whine = " (device error ignored)";
 	}
 
-	DPRINTK("xfer_shift=%u, xfer_mode=0x%x\n",
-		dev->xfer_shift, (int)dev->xfer_mode);
+	ata_dev_dbg(dev, "xfer_shift=%u, xfer_mode=0x%x\n",
+		    dev->xfer_shift, (int)dev->xfer_mode);
 
 	if (!(ehc->i.flags & ATA_EHI_QUIET) ||
 	    ehc->i.flags & ATA_EHI_DID_HARDRESET)
@@ -3276,7 +3521,7 @@ static int ata_dev_set_mode(struct ata_device *dev)
 }
 
 /**
- *	ata_do_set_mode - Program timings and issue SET FEATURES - XFER
+ *	ata_set_mode - Program timings and issue SET FEATURES - XFER
  *	@link: link on which timings will be programmed
  *	@r_failed_dev: out parameter for failed device
  *
@@ -3292,7 +3537,7 @@ static int ata_dev_set_mode(struct ata_device *dev)
  *	0 on success, negative errno otherwise
  */
 
-int ata_do_set_mode(struct ata_link *link, struct ata_device **r_failed_dev)
+int ata_set_mode(struct ata_link *link, struct ata_device **r_failed_dev)
 {
 	struct ata_port *ap = link->ap;
 	struct ata_device *dev;
@@ -3300,7 +3545,7 @@ int ata_do_set_mode(struct ata_link *link, struct ata_device **r_failed_dev)
 
 	/* step 1: calculate xfer_mask */
 	ata_for_each_dev(dev, link, ENABLED) {
-		unsigned long pio_mask, dma_mask;
+		unsigned int pio_mask, dma_mask;
 		unsigned int mode_mask;
 
 		mode_mask = ATA_DMA_MASK_ATA;
@@ -3373,7 +3618,7 @@ int ata_do_set_mode(struct ata_link *link, struct ata_device **r_failed_dev)
 		*r_failed_dev = dev;
 	return rc;
 }
-EXPORT_SYMBOL_GPL(ata_do_set_mode);
+EXPORT_SYMBOL_GPL(ata_set_mode);
 
 /**
  *	ata_wait_ready - wait for link to become ready
@@ -3500,13 +3745,13 @@ EXPORT_SYMBOL_GPL(ata_wait_after_reset);
  *	Kernel thread context (may sleep)
  *
  *	RETURNS:
- *	0 on success, -errno otherwise.
+ *	Always 0.
  */
 int ata_std_prereset(struct ata_link *link, unsigned long deadline)
 {
 	struct ata_port *ap = link->ap;
 	struct ata_eh_context *ehc = &link->eh_context;
-	const unsigned long *timing = sata_ehc_deb_timing(ehc);
+	const unsigned int *timing = sata_ehc_deb_timing(ehc);
 	int rc;
 
 	/* if we're about to do hardreset, nothing more to do */
@@ -3532,33 +3777,6 @@ int ata_std_prereset(struct ata_link *link, unsigned long deadline)
 EXPORT_SYMBOL_GPL(ata_std_prereset);
 
 /**
- *	sata_std_hardreset - COMRESET w/o waiting or classification
- *	@link: link to reset
- *	@class: resulting class of attached device
- *	@deadline: deadline jiffies for the operation
- *
- *	Standard SATA COMRESET w/o waiting or classification.
- *
- *	LOCKING:
- *	Kernel thread context (may sleep)
- *
- *	RETURNS:
- *	0 if link offline, -EAGAIN if link online, -errno on errors.
- */
-int sata_std_hardreset(struct ata_link *link, unsigned int *class,
-		       unsigned long deadline)
-{
-	const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
-	bool online;
-	int rc;
-
-	/* do hardreset */
-	rc = sata_link_hardreset(link, timing, deadline, &online, NULL);
-	return online ? -EAGAIN : rc;
-}
-EXPORT_SYMBOL_GPL(sata_std_hardreset);
-
-/**
  *	ata_std_postreset - standard postreset callback
  *	@link: the target ata_link
  *	@classes: classes of attached devices
@@ -3574,16 +3792,12 @@ void ata_std_postreset(struct ata_link *link, unsigned int *classes)
 {
 	u32 serror;
 
-	DPRINTK("ENTER\n");
-
 	/* reset complete, clear SError */
 	if (!sata_scr_read(link, SCR_ERROR, &serror))
 		sata_scr_write(link, SCR_ERROR, serror);
 
 	/* print link status */
 	sata_print_link_status(link);
-
-	DPRINTK("EXIT\n");
 }
 EXPORT_SYMBOL_GPL(ata_std_postreset);
 
@@ -3653,7 +3867,7 @@ static int ata_dev_same_device(struct ata_device *dev, unsigned int new_class,
 int ata_dev_reread_id(struct ata_device *dev, unsigned int readid_flags)
 {
 	unsigned int class = dev->class;
-	u16 *id = (void *)dev->link->ap->sector_buf;
+	u16 *id = (void *)dev->sector_buf;
 	int rc;
 
 	/* read ID data */
@@ -3695,11 +3909,7 @@ int ata_dev_revalidate(struct ata_device *dev, unsigned int new_class,
 		return -ENODEV;
 
 	/* fail early if !ATA && !ATAPI to avoid issuing [P]IDENTIFY to PMP */
-	if (ata_class_enabled(new_class) &&
-	    new_class != ATA_DEV_ATA &&
-	    new_class != ATA_DEV_ATAPI &&
-	    new_class != ATA_DEV_ZAC &&
-	    new_class != ATA_DEV_SEMB) {
+	if (ata_class_enabled(new_class) && new_class == ATA_DEV_PMP) {
 		ata_dev_info(dev, "class mismatch %u != %u\n",
 			     dev->class, new_class);
 		rc = -ENODEV;
@@ -3748,7 +3958,7 @@ int ata_dev_revalidate(struct ata_device *dev, unsigned int new_class,
 	 */
 	if (dev->n_native_sectors == n_native_sectors &&
 	    dev->n_sectors < n_sectors && n_sectors == n_native_sectors &&
-	    !(dev->horkage & ATA_HORKAGE_BROKEN_HPA)) {
+	    !(dev->quirks & ATA_QUIRK_BROKEN_HPA)) {
 		ata_dev_warn(dev,
 			     "old n_sectors matches native, probably "
 			     "late HPA lock, will try to unlock HPA\n");
@@ -3766,197 +3976,307 @@ int ata_dev_revalidate(struct ata_device *dev, unsigned int new_class,
 	return rc;
 }
 
-struct ata_blacklist_entry {
+static const char * const ata_quirk_names[] = {
+	[__ATA_QUIRK_DIAGNOSTIC]	= "diagnostic",
+	[__ATA_QUIRK_NODMA]		= "nodma",
+	[__ATA_QUIRK_NONCQ]		= "noncq",
+	[__ATA_QUIRK_MAX_SEC_128]	= "maxsec128",
+	[__ATA_QUIRK_BROKEN_HPA]	= "brokenhpa",
+	[__ATA_QUIRK_DISABLE]		= "disable",
+	[__ATA_QUIRK_HPA_SIZE]		= "hpasize",
+	[__ATA_QUIRK_IVB]		= "ivb",
+	[__ATA_QUIRK_STUCK_ERR]		= "stuckerr",
+	[__ATA_QUIRK_BRIDGE_OK]		= "bridgeok",
+	[__ATA_QUIRK_ATAPI_MOD16_DMA]	= "atapimod16dma",
+	[__ATA_QUIRK_FIRMWARE_WARN]	= "firmwarewarn",
+	[__ATA_QUIRK_1_5_GBPS]		= "1.5gbps",
+	[__ATA_QUIRK_NOSETXFER]		= "nosetxfer",
+	[__ATA_QUIRK_BROKEN_FPDMA_AA]	= "brokenfpdmaaa",
+	[__ATA_QUIRK_DUMP_ID]		= "dumpid",
+	[__ATA_QUIRK_MAX_SEC_LBA48]	= "maxseclba48",
+	[__ATA_QUIRK_ATAPI_DMADIR]	= "atapidmadir",
+	[__ATA_QUIRK_NO_NCQ_TRIM]	= "noncqtrim",
+	[__ATA_QUIRK_NOLPM]		= "nolpm",
+	[__ATA_QUIRK_WD_BROKEN_LPM]	= "wdbrokenlpm",
+	[__ATA_QUIRK_ZERO_AFTER_TRIM]	= "zeroaftertrim",
+	[__ATA_QUIRK_NO_DMA_LOG]	= "nodmalog",
+	[__ATA_QUIRK_NOTRIM]		= "notrim",
+	[__ATA_QUIRK_MAX_SEC_1024]	= "maxsec1024",
+	[__ATA_QUIRK_MAX_SEC_8191]	= "maxsec8191",
+	[__ATA_QUIRK_MAX_TRIM_128M]	= "maxtrim128m",
+	[__ATA_QUIRK_NO_NCQ_ON_ATI]	= "noncqonati",
+	[__ATA_QUIRK_NO_LPM_ON_ATI]	= "nolpmonati",
+	[__ATA_QUIRK_NO_ID_DEV_LOG]	= "noiddevlog",
+	[__ATA_QUIRK_NO_LOG_DIR]	= "nologdir",
+	[__ATA_QUIRK_NO_FUA]		= "nofua",
+};
+
+static void ata_dev_print_quirks(const struct ata_device *dev,
+				 const char *model, const char *rev,
+				 unsigned int quirks)
+{
+	struct ata_eh_context *ehc = &dev->link->eh_context;
+	int n = 0, i;
+	size_t sz;
+	char *str;
+
+	if (!ata_dev_print_info(dev) || ehc->i.flags & ATA_EHI_DID_PRINT_QUIRKS)
+		return;
+
+	ehc->i.flags |= ATA_EHI_DID_PRINT_QUIRKS;
+
+	if (!quirks)
+		return;
+
+	sz = 64 + ARRAY_SIZE(ata_quirk_names) * 16;
+	str = kmalloc(sz, GFP_KERNEL);
+	if (!str)
+		return;
+
+	n = snprintf(str, sz, "Model '%s', rev '%s', applying quirks:",
+		     model, rev);
+
+	for (i = 0; i < ARRAY_SIZE(ata_quirk_names); i++) {
+		if (quirks & (1U << i))
+			n += snprintf(str + n, sz - n,
+				      " %s", ata_quirk_names[i]);
+	}
+
+	ata_dev_warn(dev, "%s\n", str);
+
+	kfree(str);
+}
+
+struct ata_dev_quirks_entry {
 	const char *model_num;
 	const char *model_rev;
-	unsigned long horkage;
+	unsigned int quirks;
 };
 
-static const struct ata_blacklist_entry ata_device_blacklist [] = {
+static const struct ata_dev_quirks_entry __ata_dev_quirks[] = {
 	/* Devices with DMA related problems under Linux */
-	{ "WDC AC11000H",	NULL,		ATA_HORKAGE_NODMA },
-	{ "WDC AC22100H",	NULL,		ATA_HORKAGE_NODMA },
-	{ "WDC AC32500H",	NULL,		ATA_HORKAGE_NODMA },
-	{ "WDC AC33100H",	NULL,		ATA_HORKAGE_NODMA },
-	{ "WDC AC31600H",	NULL,		ATA_HORKAGE_NODMA },
-	{ "WDC AC32100H",	"24.09P07",	ATA_HORKAGE_NODMA },
-	{ "WDC AC23200L",	"21.10N21",	ATA_HORKAGE_NODMA },
-	{ "Compaq CRD-8241B", 	NULL,		ATA_HORKAGE_NODMA },
-	{ "CRD-8400B",		NULL, 		ATA_HORKAGE_NODMA },
-	{ "CRD-848[02]B",	NULL,		ATA_HORKAGE_NODMA },
-	{ "CRD-84",		NULL,		ATA_HORKAGE_NODMA },
-	{ "SanDisk SDP3B",	NULL,		ATA_HORKAGE_NODMA },
-	{ "SanDisk SDP3B-64",	NULL,		ATA_HORKAGE_NODMA },
-	{ "SANYO CD-ROM CRD",	NULL,		ATA_HORKAGE_NODMA },
-	{ "HITACHI CDR-8",	NULL,		ATA_HORKAGE_NODMA },
-	{ "HITACHI CDR-8[34]35",NULL,		ATA_HORKAGE_NODMA },
-	{ "Toshiba CD-ROM XM-6202B", NULL,	ATA_HORKAGE_NODMA },
-	{ "TOSHIBA CD-ROM XM-1702BC", NULL,	ATA_HORKAGE_NODMA },
-	{ "CD-532E-A", 		NULL,		ATA_HORKAGE_NODMA },
-	{ "E-IDE CD-ROM CR-840",NULL,		ATA_HORKAGE_NODMA },
-	{ "CD-ROM Drive/F5A",	NULL,		ATA_HORKAGE_NODMA },
-	{ "WPI CDD-820", 	NULL,		ATA_HORKAGE_NODMA },
-	{ "SAMSUNG CD-ROM SC-148C", NULL,	ATA_HORKAGE_NODMA },
-	{ "SAMSUNG CD-ROM SC",	NULL,		ATA_HORKAGE_NODMA },
-	{ "ATAPI CD-ROM DRIVE 40X MAXIMUM",NULL,ATA_HORKAGE_NODMA },
-	{ "_NEC DV5800A", 	NULL,		ATA_HORKAGE_NODMA },
-	{ "SAMSUNG CD-ROM SN-124", "N001",	ATA_HORKAGE_NODMA },
-	{ "Seagate STT20000A", NULL,		ATA_HORKAGE_NODMA },
-	{ " 2GB ATA Flash Disk", "ADMA428M",	ATA_HORKAGE_NODMA },
-	{ "VRFDFC22048UCHC-TE*", NULL,		ATA_HORKAGE_NODMA },
+	{ "WDC AC11000H",	NULL,		ATA_QUIRK_NODMA },
+	{ "WDC AC22100H",	NULL,		ATA_QUIRK_NODMA },
+	{ "WDC AC32500H",	NULL,		ATA_QUIRK_NODMA },
+	{ "WDC AC33100H",	NULL,		ATA_QUIRK_NODMA },
+	{ "WDC AC31600H",	NULL,		ATA_QUIRK_NODMA },
+	{ "WDC AC32100H",	"24.09P07",	ATA_QUIRK_NODMA },
+	{ "WDC AC23200L",	"21.10N21",	ATA_QUIRK_NODMA },
+	{ "Compaq CRD-8241B",	NULL,		ATA_QUIRK_NODMA },
+	{ "CRD-8400B",		NULL,		ATA_QUIRK_NODMA },
+	{ "CRD-848[02]B",	NULL,		ATA_QUIRK_NODMA },
+	{ "CRD-84",		NULL,		ATA_QUIRK_NODMA },
+	{ "SanDisk SDP3B",	NULL,		ATA_QUIRK_NODMA },
+	{ "SanDisk SDP3B-64",	NULL,		ATA_QUIRK_NODMA },
+	{ "SANYO CD-ROM CRD",	NULL,		ATA_QUIRK_NODMA },
+	{ "HITACHI CDR-8",	NULL,		ATA_QUIRK_NODMA },
+	{ "HITACHI CDR-8[34]35", NULL,		ATA_QUIRK_NODMA },
+	{ "Toshiba CD-ROM XM-6202B", NULL,	ATA_QUIRK_NODMA },
+	{ "TOSHIBA CD-ROM XM-1702BC", NULL,	ATA_QUIRK_NODMA },
+	{ "CD-532E-A",		NULL,		ATA_QUIRK_NODMA },
+	{ "E-IDE CD-ROM CR-840", NULL,		ATA_QUIRK_NODMA },
+	{ "CD-ROM Drive/F5A",	NULL,		ATA_QUIRK_NODMA },
+	{ "WPI CDD-820",	NULL,		ATA_QUIRK_NODMA },
+	{ "SAMSUNG CD-ROM SC-148C", NULL,	ATA_QUIRK_NODMA },
+	{ "SAMSUNG CD-ROM SC",	NULL,		ATA_QUIRK_NODMA },
+	{ "ATAPI CD-ROM DRIVE 40X MAXIMUM", NULL, ATA_QUIRK_NODMA },
+	{ "_NEC DV5800A",	NULL,		ATA_QUIRK_NODMA },
+	{ "SAMSUNG CD-ROM SN-124", "N001",	ATA_QUIRK_NODMA },
+	{ "Seagate STT20000A", NULL,		ATA_QUIRK_NODMA },
+	{ " 2GB ATA Flash Disk", "ADMA428M",	ATA_QUIRK_NODMA },
+	{ "VRFDFC22048UCHC-TE*", NULL,		ATA_QUIRK_NODMA },
 	/* Odd clown on sil3726/4726 PMPs */
-	{ "Config  Disk",	NULL,		ATA_HORKAGE_DISABLE },
+	{ "Config  Disk",	NULL,		ATA_QUIRK_DISABLE },
+	/* Similar story with ASMedia 1092 */
+	{ "ASMT109x- Config",	NULL,		ATA_QUIRK_DISABLE },
 
 	/* Weird ATAPI devices */
-	{ "TORiSAN DVD-ROM DRD-N216", NULL,	ATA_HORKAGE_MAX_SEC_128 },
-	{ "QUANTUM DAT    DAT72-000", NULL,	ATA_HORKAGE_ATAPI_MOD16_DMA },
-	{ "Slimtype DVD A  DS8A8SH", NULL,	ATA_HORKAGE_MAX_SEC_LBA48 },
-	{ "Slimtype DVD A  DS8A9SH", NULL,	ATA_HORKAGE_MAX_SEC_LBA48 },
+	{ "TORiSAN DVD-ROM DRD-N216", NULL,	ATA_QUIRK_MAX_SEC_128 },
+	{ "QUANTUM DAT    DAT72-000", NULL,	ATA_QUIRK_ATAPI_MOD16_DMA },
+	{ "Slimtype DVD A  DS8A8SH", NULL,	ATA_QUIRK_MAX_SEC_LBA48 },
+	{ "Slimtype DVD A  DS8A9SH", NULL,	ATA_QUIRK_MAX_SEC_LBA48 },
 
 	/*
 	 * Causes silent data corruption with higher max sects.
 	 * http://lkml.kernel.org/g/x49wpy40ysk.fsf@segfault.boston.devel.redhat.com
 	 */
-	{ "ST380013AS",		"3.20",		ATA_HORKAGE_MAX_SEC_1024 },
+	{ "ST380013AS",		"3.20",		ATA_QUIRK_MAX_SEC_1024 },
 
 	/*
 	 * These devices time out with higher max sects.
 	 * https://bugzilla.kernel.org/show_bug.cgi?id=121671
 	 */
-	{ "LITEON CX1-JB*-HP",	NULL,		ATA_HORKAGE_MAX_SEC_1024 },
-	{ "LITEON EP1-*",	NULL,		ATA_HORKAGE_MAX_SEC_1024 },
+	{ "LITEON CX1-JB*-HP",	NULL,		ATA_QUIRK_MAX_SEC_1024 },
+	{ "LITEON EP1-*",	NULL,		ATA_QUIRK_MAX_SEC_1024 },
+
+	/*
+	 * These devices time out with higher max sects.
+	 * https://bugzilla.kernel.org/show_bug.cgi?id=220693
+	 */
+	{ "DELLBOSS VD",	"MV.R00-0",	ATA_QUIRK_MAX_SEC_8191 },
 
 	/* Devices we expect to fail diagnostics */
 
 	/* Devices where NCQ should be avoided */
 	/* NCQ is slow */
-	{ "WDC WD740ADFD-00",	NULL,		ATA_HORKAGE_NONCQ },
-	{ "WDC WD740ADFD-00NLR1", NULL,		ATA_HORKAGE_NONCQ, },
+	{ "WDC WD740ADFD-00",	NULL,		ATA_QUIRK_NONCQ },
+	{ "WDC WD740ADFD-00NLR1", NULL,		ATA_QUIRK_NONCQ },
 	/* http://thread.gmane.org/gmane.linux.ide/14907 */
-	{ "FUJITSU MHT2060BH",	NULL,		ATA_HORKAGE_NONCQ },
+	{ "FUJITSU MHT2060BH",	NULL,		ATA_QUIRK_NONCQ },
 	/* NCQ is broken */
-	{ "Maxtor *",		"BANC*",	ATA_HORKAGE_NONCQ },
-	{ "Maxtor 7V300F0",	"VA111630",	ATA_HORKAGE_NONCQ },
-	{ "ST380817AS",		"3.42",		ATA_HORKAGE_NONCQ },
-	{ "ST3160023AS",	"3.42",		ATA_HORKAGE_NONCQ },
-	{ "OCZ CORE_SSD",	"02.10104",	ATA_HORKAGE_NONCQ },
+	{ "Maxtor *",		"BANC*",	ATA_QUIRK_NONCQ },
+	{ "Maxtor 7V300F0",	"VA111630",	ATA_QUIRK_NONCQ },
+	{ "ST380817AS",		"3.42",		ATA_QUIRK_NONCQ },
+	{ "ST3160023AS",	"3.42",		ATA_QUIRK_NONCQ },
+	{ "OCZ CORE_SSD",	"02.10104",	ATA_QUIRK_NONCQ },
 
 	/* Seagate NCQ + FLUSH CACHE firmware bug */
-	{ "ST31500341AS",	"SD1[5-9]",	ATA_HORKAGE_NONCQ |
-						ATA_HORKAGE_FIRMWARE_WARN },
+	{ "ST31500341AS",	"SD1[5-9]",	ATA_QUIRK_NONCQ |
+						ATA_QUIRK_FIRMWARE_WARN },
 
-	{ "ST31000333AS",	"SD1[5-9]",	ATA_HORKAGE_NONCQ |
-						ATA_HORKAGE_FIRMWARE_WARN },
+	{ "ST31000333AS",	"SD1[5-9]",	ATA_QUIRK_NONCQ |
+						ATA_QUIRK_FIRMWARE_WARN },
 
-	{ "ST3640[36]23AS",	"SD1[5-9]",	ATA_HORKAGE_NONCQ |
-						ATA_HORKAGE_FIRMWARE_WARN },
+	{ "ST3640[36]23AS",	"SD1[5-9]",	ATA_QUIRK_NONCQ |
+						ATA_QUIRK_FIRMWARE_WARN },
 
-	{ "ST3320[68]13AS",	"SD1[5-9]",	ATA_HORKAGE_NONCQ |
-						ATA_HORKAGE_FIRMWARE_WARN },
+	{ "ST3320[68]13AS",	"SD1[5-9]",	ATA_QUIRK_NONCQ |
+						ATA_QUIRK_FIRMWARE_WARN },
 
 	/* drives which fail FPDMA_AA activation (some may freeze afterwards)
 	   the ST disks also have LPM issues */
-	{ "ST1000LM024 HN-M101MBB", NULL,	ATA_HORKAGE_BROKEN_FPDMA_AA |
-						ATA_HORKAGE_NOLPM, },
-	{ "VB0250EAVER",	"HPG7",		ATA_HORKAGE_BROKEN_FPDMA_AA },
+	{ "ST1000LM024 HN-M101MBB", NULL,	ATA_QUIRK_BROKEN_FPDMA_AA |
+						ATA_QUIRK_NOLPM },
+	{ "VB0250EAVER",	"HPG7",		ATA_QUIRK_BROKEN_FPDMA_AA },
 
 	/* Blacklist entries taken from Silicon Image 3124/3132
 	   Windows driver .inf file - also several Linux problem reports */
-	{ "HTS541060G9SA00",    "MB3OC60D",     ATA_HORKAGE_NONCQ, },
-	{ "HTS541080G9SA00",    "MB4OC60D",     ATA_HORKAGE_NONCQ, },
-	{ "HTS541010G9SA00",    "MBZOC60D",     ATA_HORKAGE_NONCQ, },
+	{ "HTS541060G9SA00",    "MB3OC60D",     ATA_QUIRK_NONCQ },
+	{ "HTS541080G9SA00",    "MB4OC60D",     ATA_QUIRK_NONCQ },
+	{ "HTS541010G9SA00",    "MBZOC60D",     ATA_QUIRK_NONCQ },
 
 	/* https://bugzilla.kernel.org/show_bug.cgi?id=15573 */
-	{ "C300-CTFDDAC128MAG",	"0001",		ATA_HORKAGE_NONCQ, },
+	{ "C300-CTFDDAC128MAG",	"0001",		ATA_QUIRK_NONCQ },
 
-	/* Some Sandisk SSDs lock up hard with NCQ enabled.  Reported on
-	   SD7SN6S256G and SD8SN8U256G */
-	{ "SanDisk SD[78]SN*G",	NULL,		ATA_HORKAGE_NONCQ, },
+	/* Sandisk SD7/8/9s lock up hard on large trims */
+	{ "SanDisk SD[789]*",	NULL,		ATA_QUIRK_MAX_TRIM_128M },
 
 	/* devices which puke on READ_NATIVE_MAX */
-	{ "HDS724040KLSA80",	"KFAOA20N",	ATA_HORKAGE_BROKEN_HPA, },
-	{ "WDC WD3200JD-00KLB0", "WD-WCAMR1130137", ATA_HORKAGE_BROKEN_HPA },
-	{ "WDC WD2500JD-00HBB0", "WD-WMAL71490727", ATA_HORKAGE_BROKEN_HPA },
-	{ "MAXTOR 6L080L4",	"A93.0500",	ATA_HORKAGE_BROKEN_HPA },
+	{ "HDS724040KLSA80",	"KFAOA20N",	ATA_QUIRK_BROKEN_HPA },
+	{ "WDC WD3200JD-00KLB0", "WD-WCAMR1130137", ATA_QUIRK_BROKEN_HPA },
+	{ "WDC WD2500JD-00HBB0", "WD-WMAL71490727", ATA_QUIRK_BROKEN_HPA },
+	{ "MAXTOR 6L080L4",	"A93.0500",	ATA_QUIRK_BROKEN_HPA },
 
 	/* this one allows HPA unlocking but fails IOs on the area */
-	{ "OCZ-VERTEX",		    "1.30",	ATA_HORKAGE_BROKEN_HPA },
+	{ "OCZ-VERTEX",		    "1.30",	ATA_QUIRK_BROKEN_HPA },
 
 	/* Devices which report 1 sector over size HPA */
-	{ "ST340823A",		NULL,		ATA_HORKAGE_HPA_SIZE, },
-	{ "ST320413A",		NULL,		ATA_HORKAGE_HPA_SIZE, },
-	{ "ST310211A",		NULL,		ATA_HORKAGE_HPA_SIZE, },
+	{ "ST340823A",		NULL,		ATA_QUIRK_HPA_SIZE },
+	{ "ST320413A",		NULL,		ATA_QUIRK_HPA_SIZE },
+	{ "ST310211A",		NULL,		ATA_QUIRK_HPA_SIZE },
 
 	/* Devices which get the IVB wrong */
-	{ "QUANTUM FIREBALLlct10 05", "A03.0900", ATA_HORKAGE_IVB, },
-	/* Maybe we should just blacklist TSSTcorp... */
-	{ "TSSTcorp CDDVDW SH-S202[HJN]", "SB0[01]",  ATA_HORKAGE_IVB, },
+	{ "QUANTUM FIREBALLlct10 05", "A03.0900", ATA_QUIRK_IVB },
+	/* Maybe we should just add all TSSTcorp devices... */
+	{ "TSSTcorp CDDVDW SH-S202[HJN]", "SB0[01]",  ATA_QUIRK_IVB },
 
 	/* Devices that do not need bridging limits applied */
-	{ "MTRON MSP-SATA*",		NULL,	ATA_HORKAGE_BRIDGE_OK, },
-	{ "BUFFALO HD-QSU2/R5",		NULL,	ATA_HORKAGE_BRIDGE_OK, },
+	{ "MTRON MSP-SATA*",		NULL,	ATA_QUIRK_BRIDGE_OK },
+	{ "BUFFALO HD-QSU2/R5",		NULL,	ATA_QUIRK_BRIDGE_OK },
 
 	/* Devices which aren't very happy with higher link speeds */
-	{ "WD My Book",			NULL,	ATA_HORKAGE_1_5_GBPS, },
-	{ "Seagate FreeAgent GoFlex",	NULL,	ATA_HORKAGE_1_5_GBPS, },
+	{ "WD My Book",			NULL,	ATA_QUIRK_1_5_GBPS },
+	{ "Seagate FreeAgent GoFlex",	NULL,	ATA_QUIRK_1_5_GBPS },
 
 	/*
 	 * Devices which choke on SETXFER.  Applies only if both the
 	 * device and controller are SATA.
 	 */
-	{ "PIONEER DVD-RW  DVRTD08",	NULL,	ATA_HORKAGE_NOSETXFER },
-	{ "PIONEER DVD-RW  DVRTD08A",	NULL,	ATA_HORKAGE_NOSETXFER },
-	{ "PIONEER DVD-RW  DVR-215",	NULL,	ATA_HORKAGE_NOSETXFER },
-	{ "PIONEER DVD-RW  DVR-212D",	NULL,	ATA_HORKAGE_NOSETXFER },
-	{ "PIONEER DVD-RW  DVR-216D",	NULL,	ATA_HORKAGE_NOSETXFER },
+	{ "PIONEER DVD-RW  DVRTD08",	NULL,	ATA_QUIRK_NOSETXFER },
+	{ "PIONEER DVD-RW  DVRTD08A",	NULL,	ATA_QUIRK_NOSETXFER },
+	{ "PIONEER DVD-RW  DVR-215",	NULL,	ATA_QUIRK_NOSETXFER },
+	{ "PIONEER DVD-RW  DVR-212D",	NULL,	ATA_QUIRK_NOSETXFER },
+	{ "PIONEER DVD-RW  DVR-216D",	NULL,	ATA_QUIRK_NOSETXFER },
+
+	/* These specific Pioneer models have LPM issues */
+	{ "PIONEER BD-RW   BDR-207M",	NULL,	ATA_QUIRK_NOLPM },
+	{ "PIONEER BD-RW   BDR-205",	NULL,	ATA_QUIRK_NOLPM },
 
-	/* Crucial BX100 SSD 500GB has broken LPM support */
-	{ "CT500BX100SSD1",		NULL,	ATA_HORKAGE_NOLPM },
+	/* Crucial devices with broken LPM support */
+	{ "CT*0BX*00SSD1",		NULL,	ATA_QUIRK_NOLPM },
 
 	/* 512GB MX100 with MU01 firmware has both queued TRIM and LPM issues */
-	{ "Crucial_CT512MX100*",	"MU01",	ATA_HORKAGE_NO_NCQ_TRIM |
-						ATA_HORKAGE_ZERO_AFTER_TRIM |
-						ATA_HORKAGE_NOLPM, },
+	{ "Crucial_CT512MX100*",	"MU01",	ATA_QUIRK_NO_NCQ_TRIM |
+						ATA_QUIRK_ZERO_AFTER_TRIM |
+						ATA_QUIRK_NOLPM },
 	/* 512GB MX100 with newer firmware has only LPM issues */
-	{ "Crucial_CT512MX100*",	NULL,	ATA_HORKAGE_ZERO_AFTER_TRIM |
-						ATA_HORKAGE_NOLPM, },
+	{ "Crucial_CT512MX100*",	NULL,	ATA_QUIRK_ZERO_AFTER_TRIM |
+						ATA_QUIRK_NOLPM },
 
 	/* 480GB+ M500 SSDs have both queued TRIM and LPM issues */
-	{ "Crucial_CT480M500*",		NULL,	ATA_HORKAGE_NO_NCQ_TRIM |
-						ATA_HORKAGE_ZERO_AFTER_TRIM |
-						ATA_HORKAGE_NOLPM, },
-	{ "Crucial_CT960M500*",		NULL,	ATA_HORKAGE_NO_NCQ_TRIM |
-						ATA_HORKAGE_ZERO_AFTER_TRIM |
-						ATA_HORKAGE_NOLPM, },
+	{ "Crucial_CT480M500*",		NULL,	ATA_QUIRK_NO_NCQ_TRIM |
+						ATA_QUIRK_ZERO_AFTER_TRIM |
+						ATA_QUIRK_NOLPM },
+	{ "Crucial_CT960M500*",		NULL,	ATA_QUIRK_NO_NCQ_TRIM |
+						ATA_QUIRK_ZERO_AFTER_TRIM |
+						ATA_QUIRK_NOLPM },
+
+	/* AMD Radeon devices with broken LPM support */
+	{ "R3SL240G",			NULL,	ATA_QUIRK_NOLPM },
+
+	/* Apacer models with LPM issues */
+	{ "Apacer AS340*",		NULL,	ATA_QUIRK_NOLPM },
+
+	/* Silicon Motion models with LPM issues */
+	{ "MD619HXCLDE3TC",		"TCVAID", ATA_QUIRK_NOLPM },
+	{ "MD619GXCLDE3TC",		"TCV35D", ATA_QUIRK_NOLPM },
 
 	/* These specific Samsung models/firmware-revs do not handle LPM well */
-	{ "SAMSUNG MZMPC128HBFU-000MV", "CXM14M1Q", ATA_HORKAGE_NOLPM, },
-	{ "SAMSUNG SSD PM830 mSATA *",  "CXM13D1Q", ATA_HORKAGE_NOLPM, },
-	{ "SAMSUNG MZ7TD256HAFV-000L9", NULL,       ATA_HORKAGE_NOLPM, },
-	{ "SAMSUNG MZ7TE512HMHP-000L1", "EXT06L0Q", ATA_HORKAGE_NOLPM, },
+	{ "SAMSUNG MZMPC128HBFU-000MV", "CXM14M1Q", ATA_QUIRK_NOLPM },
+	{ "SAMSUNG SSD PM830 mSATA *",  "CXM13D1Q", ATA_QUIRK_NOLPM },
+	{ "SAMSUNG MZ7TD256HAFV-000L9", NULL,       ATA_QUIRK_NOLPM },
+	{ "SAMSUNG MZ7TE512HMHP-000L1", "EXT06L0Q", ATA_QUIRK_NOLPM },
 
 	/* devices that don't properly handle queued TRIM commands */
-	{ "Micron_M500IT_*",		"MU01",	ATA_HORKAGE_NO_NCQ_TRIM |
-						ATA_HORKAGE_ZERO_AFTER_TRIM, },
-	{ "Micron_M500_*",		NULL,	ATA_HORKAGE_NO_NCQ_TRIM |
-						ATA_HORKAGE_ZERO_AFTER_TRIM, },
-	{ "Crucial_CT*M500*",		NULL,	ATA_HORKAGE_NO_NCQ_TRIM |
-						ATA_HORKAGE_ZERO_AFTER_TRIM, },
-	{ "Micron_M5[15]0_*",		"MU01",	ATA_HORKAGE_NO_NCQ_TRIM |
-						ATA_HORKAGE_ZERO_AFTER_TRIM, },
-	{ "Crucial_CT*M550*",		"MU01",	ATA_HORKAGE_NO_NCQ_TRIM |
-						ATA_HORKAGE_ZERO_AFTER_TRIM, },
-	{ "Crucial_CT*MX100*",		"MU01",	ATA_HORKAGE_NO_NCQ_TRIM |
-						ATA_HORKAGE_ZERO_AFTER_TRIM, },
-	{ "Samsung SSD 840*",		NULL,	ATA_HORKAGE_NO_NCQ_TRIM |
-						ATA_HORKAGE_ZERO_AFTER_TRIM, },
-	{ "Samsung SSD 850*",		NULL,	ATA_HORKAGE_NO_NCQ_TRIM |
-						ATA_HORKAGE_ZERO_AFTER_TRIM, },
-	{ "FCCT*M500*",			NULL,	ATA_HORKAGE_NO_NCQ_TRIM |
-						ATA_HORKAGE_ZERO_AFTER_TRIM, },
+	{ "Micron_M500IT_*",		"MU01",	ATA_QUIRK_NO_NCQ_TRIM |
+						ATA_QUIRK_ZERO_AFTER_TRIM },
+	{ "Micron_M500_*",		NULL,	ATA_QUIRK_NO_NCQ_TRIM |
+						ATA_QUIRK_ZERO_AFTER_TRIM },
+	{ "Micron_M5[15]0_*",		"MU01",	ATA_QUIRK_NO_NCQ_TRIM |
+						ATA_QUIRK_ZERO_AFTER_TRIM },
+	{ "Micron_1100_*",		NULL,	ATA_QUIRK_NO_NCQ_TRIM |
+						ATA_QUIRK_ZERO_AFTER_TRIM, },
+	{ "Crucial_CT*M500*",		NULL,	ATA_QUIRK_NO_NCQ_TRIM |
+						ATA_QUIRK_ZERO_AFTER_TRIM },
+	{ "Crucial_CT*M550*",		"MU01",	ATA_QUIRK_NO_NCQ_TRIM |
+						ATA_QUIRK_ZERO_AFTER_TRIM },
+	{ "Crucial_CT*MX100*",		"MU01",	ATA_QUIRK_NO_NCQ_TRIM |
+						ATA_QUIRK_ZERO_AFTER_TRIM },
+	{ "Samsung SSD 840 EVO*",	NULL,	ATA_QUIRK_NO_NCQ_TRIM |
+						ATA_QUIRK_NO_DMA_LOG |
+						ATA_QUIRK_ZERO_AFTER_TRIM },
+	{ "Samsung SSD 840*",		NULL,	ATA_QUIRK_NO_NCQ_TRIM |
+						ATA_QUIRK_ZERO_AFTER_TRIM },
+	{ "Samsung SSD 850*",		NULL,	ATA_QUIRK_NO_NCQ_TRIM |
+						ATA_QUIRK_ZERO_AFTER_TRIM },
+	{ "Samsung SSD 860*",		NULL,	ATA_QUIRK_NO_NCQ_TRIM |
+						ATA_QUIRK_ZERO_AFTER_TRIM |
+						ATA_QUIRK_NO_NCQ_ON_ATI |
+						ATA_QUIRK_NO_LPM_ON_ATI },
+	{ "Samsung SSD 870*",		NULL,	ATA_QUIRK_NO_NCQ_TRIM |
+						ATA_QUIRK_ZERO_AFTER_TRIM |
+						ATA_QUIRK_NO_NCQ_ON_ATI |
+						ATA_QUIRK_NO_LPM_ON_ATI },
+	{ "SAMSUNG*MZ7LH*",		NULL,	ATA_QUIRK_NO_NCQ_TRIM |
+						ATA_QUIRK_ZERO_AFTER_TRIM |
+						ATA_QUIRK_NO_NCQ_ON_ATI |
+						ATA_QUIRK_NO_LPM_ON_ATI },
+	{ "FCCT*M500*",			NULL,	ATA_QUIRK_NO_NCQ_TRIM |
+						ATA_QUIRK_ZERO_AFTER_TRIM },
 
 	/* devices that don't properly handle TRIM commands */
-	{ "SuperSSpeed S238*",		NULL,	ATA_HORKAGE_NOTRIM, },
+	{ "SuperSSpeed S238*",		NULL,	ATA_QUIRK_NOTRIM },
+	{ "M88V29*",			NULL,	ATA_QUIRK_NOTRIM },
 
 	/*
 	 * As defined, the DRAT (Deterministic Read After Trim) and RZAT
@@ -3974,16 +4294,16 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = {
 	 * The intel 510 drive has buggy DRAT/RZAT. Explicitly exclude
 	 * that model before whitelisting all other intel SSDs.
 	 */
-	{ "INTEL*SSDSC2MH*",		NULL,	0, },
+	{ "INTEL*SSDSC2MH*",		NULL,	0 },
 
-	{ "Micron*",			NULL,	ATA_HORKAGE_ZERO_AFTER_TRIM, },
-	{ "Crucial*",			NULL,	ATA_HORKAGE_ZERO_AFTER_TRIM, },
-	{ "INTEL*SSD*", 		NULL,	ATA_HORKAGE_ZERO_AFTER_TRIM, },
-	{ "SSD*INTEL*",			NULL,	ATA_HORKAGE_ZERO_AFTER_TRIM, },
-	{ "Samsung*SSD*",		NULL,	ATA_HORKAGE_ZERO_AFTER_TRIM, },
-	{ "SAMSUNG*SSD*",		NULL,	ATA_HORKAGE_ZERO_AFTER_TRIM, },
-	{ "SAMSUNG*MZ7KM*",		NULL,	ATA_HORKAGE_ZERO_AFTER_TRIM, },
-	{ "ST[1248][0248]0[FH]*",	NULL,	ATA_HORKAGE_ZERO_AFTER_TRIM, },
+	{ "Micron*",			NULL,	ATA_QUIRK_ZERO_AFTER_TRIM },
+	{ "Crucial*",			NULL,	ATA_QUIRK_ZERO_AFTER_TRIM },
+	{ "INTEL*SSD*",			NULL,	ATA_QUIRK_ZERO_AFTER_TRIM },
+	{ "SSD*INTEL*",			NULL,	ATA_QUIRK_ZERO_AFTER_TRIM },
+	{ "Samsung*SSD*",		NULL,	ATA_QUIRK_ZERO_AFTER_TRIM },
+	{ "SAMSUNG*SSD*",		NULL,	ATA_QUIRK_ZERO_AFTER_TRIM },
+	{ "SAMSUNG*MZ7KM*",		NULL,	ATA_QUIRK_ZERO_AFTER_TRIM },
+	{ "ST[1248][0248]0[FH]*",	NULL,	ATA_QUIRK_ZERO_AFTER_TRIM },
 
 	/*
 	 * Some WD SATA-I drives spin up and down erratically when the link
@@ -3994,49 +4314,66 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = {
 	 *
 	 * https://bugzilla.kernel.org/show_bug.cgi?id=57211
 	 */
-	{ "WDC WD800JD-*",		NULL,	ATA_HORKAGE_WD_BROKEN_LPM },
-	{ "WDC WD1200JD-*",		NULL,	ATA_HORKAGE_WD_BROKEN_LPM },
-	{ "WDC WD1600JD-*",		NULL,	ATA_HORKAGE_WD_BROKEN_LPM },
-	{ "WDC WD2000JD-*",		NULL,	ATA_HORKAGE_WD_BROKEN_LPM },
-	{ "WDC WD2500JD-*",		NULL,	ATA_HORKAGE_WD_BROKEN_LPM },
-	{ "WDC WD3000JD-*",		NULL,	ATA_HORKAGE_WD_BROKEN_LPM },
-	{ "WDC WD3200JD-*",		NULL,	ATA_HORKAGE_WD_BROKEN_LPM },
+	{ "WDC WD800JD-*",		NULL,	ATA_QUIRK_WD_BROKEN_LPM },
+	{ "WDC WD1200JD-*",		NULL,	ATA_QUIRK_WD_BROKEN_LPM },
+	{ "WDC WD1600JD-*",		NULL,	ATA_QUIRK_WD_BROKEN_LPM },
+	{ "WDC WD2000JD-*",		NULL,	ATA_QUIRK_WD_BROKEN_LPM },
+	{ "WDC WD2500JD-*",		NULL,	ATA_QUIRK_WD_BROKEN_LPM },
+	{ "WDC WD3000JD-*",		NULL,	ATA_QUIRK_WD_BROKEN_LPM },
+	{ "WDC WD3200JD-*",		NULL,	ATA_QUIRK_WD_BROKEN_LPM },
+
+	/*
+	 * This sata dom device goes on a walkabout when the ATA_LOG_DIRECTORY
+	 * log page is accessed. Ensure we never ask for this log page with
+	 * these devices.
+	 */
+	{ "SATADOM-ML 3ME",		NULL,	ATA_QUIRK_NO_LOG_DIR },
+
+	/* Buggy FUA */
+	{ "Maxtor",		"BANC1G10",	ATA_QUIRK_NO_FUA },
+	{ "WDC*WD2500J*",	NULL,		ATA_QUIRK_NO_FUA },
+	{ "OCZ-VERTEX*",	NULL,		ATA_QUIRK_NO_FUA },
+	{ "INTEL*SSDSC2CT*",	NULL,		ATA_QUIRK_NO_FUA },
 
 	/* End Marker */
 	{ }
 };
 
-static unsigned long ata_dev_blacklisted(const struct ata_device *dev)
+static unsigned int ata_dev_quirks(const struct ata_device *dev)
 {
 	unsigned char model_num[ATA_ID_PROD_LEN + 1];
 	unsigned char model_rev[ATA_ID_FW_REV_LEN + 1];
-	const struct ata_blacklist_entry *ad = ata_device_blacklist;
+	const struct ata_dev_quirks_entry *ad = __ata_dev_quirks;
+
+	/* dev->quirks is an unsigned int. */
+	BUILD_BUG_ON(__ATA_QUIRK_MAX > 32);
 
 	ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
 	ata_id_c_string(dev->id, model_rev, ATA_ID_FW_REV, sizeof(model_rev));
 
 	while (ad->model_num) {
-		if (glob_match(ad->model_num, model_num)) {
-			if (ad->model_rev == NULL)
-				return ad->horkage;
-			if (glob_match(ad->model_rev, model_rev))
-				return ad->horkage;
+		if (glob_match(ad->model_num, model_num) &&
+		    (!ad->model_rev || glob_match(ad->model_rev, model_rev))) {
+			ata_dev_print_quirks(dev, model_num, model_rev,
+					     ad->quirks);
+			return ad->quirks;
 		}
 		ad++;
 	}
 	return 0;
 }
 
-static int ata_dma_blacklisted(const struct ata_device *dev)
+static bool ata_dev_nodma(const struct ata_device *dev)
 {
-	/* We don't support polling DMA.
-	 * DMA blacklist those ATAPI devices with CDB-intr (and use PIO)
-	 * if the LLDD handles only interrupts in the HSM_ST_LAST state.
+	/*
+	 * We do not support polling DMA. Deny DMA for those ATAPI devices
+	 * with CDB-intr (and use PIO) if the LLDD handles only interrupts in
+	 * the HSM_ST_LAST state.
 	 */
 	if ((dev->link->ap->flags & ATA_FLAG_PIO_POLLING) &&
 	    (dev->flags & ATA_DFLAG_CDB_INTR))
-		return 1;
-	return (dev->horkage & ATA_HORKAGE_NODMA) ? 1 : 0;
+		return true;
+	return dev->quirks & ATA_QUIRK_NODMA;
 }
 
 /**
@@ -4049,7 +4386,7 @@ static int ata_dma_blacklisted(const struct ata_device *dev)
 
 static int ata_is_40wire(struct ata_device *dev)
 {
-	if (dev->horkage & ATA_HORKAGE_IVB)
+	if (dev->quirks & ATA_QUIRK_IVB)
 		return ata_drive_40wire_relaxed(dev->id);
 	return ata_drive_40wire(dev->id);
 }
@@ -4111,8 +4448,7 @@ static int cable_is_40wire(struct ata_port *ap)
  *
  *	Compute supported xfermask of @dev and store it in
  *	dev->*_mask.  This function is responsible for applying all
- *	known limits including host controller limits, device
- *	blacklist, etc...
+ *	known limits including host controller limits, device quirks, etc...
  *
  *	LOCKING:
  *	None.
@@ -4122,7 +4458,7 @@ static void ata_dev_xfermask(struct ata_device *dev)
 	struct ata_link *link = dev->link;
 	struct ata_port *ap = link->ap;
 	struct ata_host *host = ap->host;
-	unsigned long xfer_mask;
+	unsigned int xfer_mask;
 
 	/* controller modes available */
 	xfer_mask = ata_pack_xfermask(ap->pio_mask,
@@ -4144,10 +4480,10 @@ static void ata_dev_xfermask(struct ata_device *dev)
 		xfer_mask &= ~(0x03 << (ATA_SHIFT_MWDMA + 3));
 	}
 
-	if (ata_dma_blacklisted(dev)) {
+	if (ata_dev_nodma(dev)) {
 		xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
 		ata_dev_warn(dev,
-			     "device is on DMA blacklist, disabling DMA\n");
+			     "device does not support DMA, disabling DMA\n");
 	}
 
 	if ((host->flags & ATA_HOST_SIMPLEX) &&
@@ -4200,10 +4536,9 @@ static void ata_dev_xfermask(struct ata_device *dev)
 static unsigned int ata_dev_set_xfermode(struct ata_device *dev)
 {
 	struct ata_taskfile tf;
-	unsigned int err_mask;
 
 	/* set up set-features taskfile */
-	DPRINTK("set features - xfer mode\n");
+	ata_dev_dbg(dev, "set features - xfer mode\n");
 
 	/* Some controllers and ATAPI devices show flaky interrupt
 	 * behavior after setting xfer mode.  Use polling instead.
@@ -4222,21 +4557,20 @@ static unsigned int ata_dev_set_xfermode(struct ata_device *dev)
 	else /* In the ancient relic department - skip all of this */
 		return 0;
 
-	/* On some disks, this command causes spin-up, so we need longer timeout */
-	err_mask = ata_exec_internal(dev, &tf, NULL, DMA_NONE, NULL, 0, 15000);
-
-	DPRINTK("EXIT, err_mask=%x\n", err_mask);
-	return err_mask;
+	/*
+	 * On some disks, this command causes spin-up, so we need longer
+	 * timeout.
+	 */
+	return ata_exec_internal(dev, &tf, NULL, DMA_NONE, NULL, 0, 15000);
 }
 
 /**
- *	ata_dev_set_feature - Issue SET FEATURES - SATA FEATURES
+ *	ata_dev_set_feature - Issue SET FEATURES
  *	@dev: Device to which command will be sent
- *	@enable: Whether to enable or disable the feature
- *	@feature: The sector count represents the feature to set
+ *	@subcmd: The SET FEATURES subcommand to be sent
+ *	@action: The sector count represents a subcommand specific action
  *
- *	Issue SET FEATURES - SATA FEATURES command to device @dev
- *	on port @ap with sector count
+ *	Issue SET FEATURES command to device @dev on port @ap with sector count
  *
  *	LOCKING:
  *	PCI/etc. bus probe sem.
@@ -4244,29 +4578,26 @@ static unsigned int ata_dev_set_xfermode(struct ata_device *dev)
  *	RETURNS:
  *	0 on success, AC_ERR_* mask otherwise.
  */
-unsigned int ata_dev_set_feature(struct ata_device *dev, u8 enable, u8 feature)
+unsigned int ata_dev_set_feature(struct ata_device *dev, u8 subcmd, u8 action)
 {
 	struct ata_taskfile tf;
-	unsigned int err_mask;
-	unsigned long timeout = 0;
+	unsigned int timeout = 0;
 
 	/* set up set-features taskfile */
-	DPRINTK("set features - SATA features\n");
+	ata_dev_dbg(dev, "set features\n");
 
 	ata_tf_init(dev, &tf);
 	tf.command = ATA_CMD_SET_FEATURES;
-	tf.feature = enable;
+	tf.feature = subcmd;
 	tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
 	tf.protocol = ATA_PROT_NODATA;
-	tf.nsect = feature;
+	tf.nsect = action;
 
-	if (enable == SETFEATURES_SPINUP)
+	if (subcmd == SETFEATURES_SPINUP)
 		timeout = ata_probe_timeout ?
 			  ata_probe_timeout * 1000 : SETFEATURES_SPINUP_TIMEOUT;
-	err_mask = ata_exec_internal(dev, &tf, NULL, DMA_NONE, NULL, 0, timeout);
 
-	DPRINTK("EXIT, err_mask=%x\n", err_mask);
-	return err_mask;
+	return ata_exec_internal(dev, &tf, NULL, DMA_NONE, NULL, 0, timeout);
 }
 EXPORT_SYMBOL_GPL(ata_dev_set_feature);
 
@@ -4293,7 +4624,7 @@ static unsigned int ata_dev_init_params(struct ata_device *dev,
 		return AC_ERR_INVALID;
 
 	/* set up init dev params taskfile */
-	DPRINTK("init dev params \n");
+	ata_dev_dbg(dev, "init dev params\n");
 
 	ata_tf_init(dev, &tf);
 	tf.command = ATA_CMD_INIT_DEV_PARAMS;
@@ -4306,10 +4637,9 @@ static unsigned int ata_dev_init_params(struct ata_device *dev,
 	/* A clean abort indicates an original or just out of spec drive
 	   and we should continue as we issue the setup based on the
 	   drive reported working geometry */
-	if (err_mask == AC_ERR_DEV && (tf.feature & ATA_ABORTED))
+	if (err_mask == AC_ERR_DEV && (tf.error & ATA_ABORTED))
 		err_mask = 0;
 
-	DPRINTK("EXIT, err_mask=%x\n", err_mask);
 	return err_mask;
 }
 
@@ -4334,9 +4664,9 @@ int atapi_check_dma(struct ata_queued_cmd *qc)
 	/* Don't allow DMA if it isn't multiple of 16 bytes.  Quite a
 	 * few ATAPI devices choke on such DMA requests.
 	 */
-	if (!(qc->dev->horkage & ATA_HORKAGE_ATAPI_MOD16_DMA) &&
+	if (!(qc->dev->quirks & ATA_QUIRK_ATAPI_MOD16_DMA) &&
 	    unlikely(qc->nbytes & 15))
-		return 1;
+		return -EOPNOTSUPP;
 
 	if (ap->ops->check_atapi_dma)
 		return ap->ops->check_atapi_dma(qc);
@@ -4375,12 +4705,6 @@ int ata_std_qc_defer(struct ata_queued_cmd *qc)
 }
 EXPORT_SYMBOL_GPL(ata_std_qc_defer);
 
-enum ata_completion_errors ata_noop_qc_prep(struct ata_queued_cmd *qc)
-{
-	return AC_ERR_OK;
-}
-EXPORT_SYMBOL_GPL(ata_noop_qc_prep);
-
 /**
  *	ata_sg_init - Associate command with scatter-gather table.
  *	@qc: Command to be associated
@@ -4421,8 +4745,6 @@ static void ata_sg_clean(struct ata_queued_cmd *qc)
 
 	WARN_ON_ONCE(sg == NULL);
 
-	VPRINTK("unmapping %u sg elements\n", qc->n_elem);
-
 	if (qc->n_elem)
 		dma_unmap_sg(ap->dev, sg, qc->orig_n_elem, dir);
 
@@ -4448,13 +4770,10 @@ static int ata_sg_setup(struct ata_queued_cmd *qc)
 	struct ata_port *ap = qc->ap;
 	unsigned int n_elem;
 
-	VPRINTK("ENTER, ata%u\n", ap->print_id);
-
 	n_elem = dma_map_sg(ap->dev, qc->sg, qc->n_elem, qc->dma_dir);
 	if (n_elem < 1)
 		return -1;
 
-	VPRINTK("%d sg elements mapped\n", n_elem);
 	qc->orig_n_elem = qc->n_elem;
 	qc->n_elem = n_elem;
 	qc->flags |= ATA_QCFLAG_DMAMAP;
@@ -4492,42 +4811,6 @@ void swap_buf_le16(u16 *buf, unsigned int buf_words)
 }
 
 /**
- *	ata_qc_new_init - Request an available ATA command, and initialize it
- *	@dev: Device from whom we request an available command structure
- *	@tag: tag
- *
- *	LOCKING:
- *	None.
- */
-
-struct ata_queued_cmd *ata_qc_new_init(struct ata_device *dev, int tag)
-{
-	struct ata_port *ap = dev->link->ap;
-	struct ata_queued_cmd *qc;
-
-	/* no command while frozen */
-	if (unlikely(ap->pflags & ATA_PFLAG_FROZEN))
-		return NULL;
-
-	/* libsas case */
-	if (ap->flags & ATA_FLAG_SAS_HOST) {
-		tag = ata_sas_allocate_tag(ap);
-		if (tag < 0)
-			return NULL;
-	}
-
-	qc = __ata_qc_from_tag(ap, tag);
-	qc->tag = qc->hw_tag = tag;
-	qc->scsicmd = NULL;
-	qc->ap = ap;
-	qc->dev = dev;
-
-	ata_qc_reinit(qc);
-
-	return qc;
-}
-
-/**
  *	ata_qc_free - free unused ata_queued_cmd
  *	@qc: Command to complete
  *
@@ -4539,19 +4822,9 @@ struct ata_queued_cmd *ata_qc_new_init(struct ata_device *dev, int tag)
  */
 void ata_qc_free(struct ata_queued_cmd *qc)
 {
-	struct ata_port *ap;
-	unsigned int tag;
-
-	WARN_ON_ONCE(qc == NULL); /* ata_qc_from_tag _might_ return NULL */
-	ap = qc->ap;
-
 	qc->flags = 0;
-	tag = qc->tag;
-	if (ata_tag_valid(tag)) {
+	if (ata_tag_valid(qc->tag))
 		qc->tag = ATA_TAG_POISON;
-		if (ap->flags & ATA_FLAG_SAS_HOST)
-			ata_sas_free_tag(tag, ap);
-	}
 }
 
 void __ata_qc_complete(struct ata_queued_cmd *qc)
@@ -4559,8 +4832,9 @@ void __ata_qc_complete(struct ata_queued_cmd *qc)
 	struct ata_port *ap;
 	struct ata_link *link;
 
-	WARN_ON_ONCE(qc == NULL); /* ata_qc_from_tag _might_ return NULL */
-	WARN_ON_ONCE(!(qc->flags & ATA_QCFLAG_ACTIVE));
+	if (WARN_ON_ONCE(!(qc->flags & ATA_QCFLAG_ACTIVE)))
+		return;
+
 	ap = qc->ap;
 	link = qc->dev->link;
 
@@ -4582,9 +4856,10 @@ void __ata_qc_complete(struct ata_queued_cmd *qc)
 		     ap->excl_link == link))
 		ap->excl_link = NULL;
 
-	/* atapi: mark qc as inactive to prevent the interrupt handler
-	 * from completing the command twice later, before the error handler
-	 * is called. (when rc != 0 and atapi request sense is needed)
+	/*
+	 * Mark qc as inactive to prevent the port interrupt handler from
+	 * completing the command twice later, before the error handler is
+	 * called.
 	 */
 	qc->flags &= ~ATA_QCFLAG_ACTIVE;
 	ap->qc_active &= ~(1ULL << qc->tag);
@@ -4597,8 +4872,16 @@ static void fill_result_tf(struct ata_queued_cmd *qc)
 {
 	struct ata_port *ap = qc->ap;
 
+	/*
+	 * rtf may already be filled (e.g. for successful NCQ commands).
+	 * If that is the case, we have nothing to do.
+	 */
+	if (qc->flags & ATA_QCFLAG_RTF_FILLED)
+		return;
+
 	qc->result_tf.flags = qc->tf.flags;
 	ap->ops->qc_fill_rtf(qc);
+	qc->flags |= ATA_QCFLAG_RTF_FILLED;
 }
 
 static void ata_verify_xfer(struct ata_queued_cmd *qc)
@@ -4632,96 +4915,100 @@ static void ata_verify_xfer(struct ata_queued_cmd *qc)
 void ata_qc_complete(struct ata_queued_cmd *qc)
 {
 	struct ata_port *ap = qc->ap;
+	struct ata_device *dev = qc->dev;
+	struct ata_eh_info *ehi = &dev->link->eh_info;
 
 	/* Trigger the LED (if available) */
 	ledtrig_disk_activity(!!(qc->tf.flags & ATA_TFLAG_WRITE));
 
-	/* XXX: New EH and old EH use different mechanisms to
-	 * synchronize EH with regular execution path.
-	 *
-	 * In new EH, a failed qc is marked with ATA_QCFLAG_FAILED.
-	 * Normal execution path is responsible for not accessing a
-	 * failed qc.  libata core enforces the rule by returning NULL
-	 * from ata_qc_from_tag() for failed qcs.
+	/*
+	 * In order to synchronize EH with the regular execution path, a qc that
+	 * is owned by EH is marked with ATA_QCFLAG_EH.
 	 *
-	 * Old EH depends on ata_qc_complete() nullifying completion
-	 * requests if ATA_QCFLAG_EH_SCHEDULED is set.  Old EH does
-	 * not synchronize with interrupt handler.  Only PIO task is
-	 * taken care of.
+	 * The normal execution path is responsible for not accessing a qc owned
+	 * by EH.  libata core enforces the rule by returning NULL from
+	 * ata_qc_from_tag() for qcs owned by EH.
 	 */
-	if (ap->ops->error_handler) {
-		struct ata_device *dev = qc->dev;
-		struct ata_eh_info *ehi = &dev->link->eh_info;
+	if (unlikely(qc->err_mask))
+		qc->flags |= ATA_QCFLAG_EH;
 
-		if (unlikely(qc->err_mask))
-			qc->flags |= ATA_QCFLAG_FAILED;
+	/*
+	 * Finish internal commands without any further processing and always
+	 * with the result TF filled.
+	 */
+	if (unlikely(ata_tag_internal(qc->tag))) {
+		fill_result_tf(qc);
+		trace_ata_qc_complete_internal(qc);
+		__ata_qc_complete(qc);
+		return;
+	}
 
-		/*
-		 * Finish internal commands without any further processing
-		 * and always with the result TF filled.
-		 */
-		if (unlikely(ata_tag_internal(qc->tag))) {
-			fill_result_tf(qc);
-			trace_ata_qc_complete_internal(qc);
-			__ata_qc_complete(qc);
-			return;
-		}
+	/* Non-internal qc has failed.  Fill the result TF and summon EH. */
+	if (unlikely(qc->flags & ATA_QCFLAG_EH)) {
+		fill_result_tf(qc);
+		trace_ata_qc_complete_failed(qc);
+		ata_qc_schedule_eh(qc);
+		return;
+	}
 
-		/*
-		 * Non-internal qc has failed.  Fill the result TF and
-		 * summon EH.
-		 */
-		if (unlikely(qc->flags & ATA_QCFLAG_FAILED)) {
-			fill_result_tf(qc);
-			trace_ata_qc_complete_failed(qc);
-			ata_qc_schedule_eh(qc);
-			return;
-		}
+	WARN_ON_ONCE(ata_port_is_frozen(ap));
 
-		WARN_ON_ONCE(ap->pflags & ATA_PFLAG_FROZEN);
+	/* read result TF if requested */
+	if (qc->flags & ATA_QCFLAG_RESULT_TF)
+		fill_result_tf(qc);
 
-		/* read result TF if requested */
-		if (qc->flags & ATA_QCFLAG_RESULT_TF)
-			fill_result_tf(qc);
+	trace_ata_qc_complete_done(qc);
 
-		trace_ata_qc_complete_done(qc);
-		/* Some commands need post-processing after successful
-		 * completion.
+	/*
+	 * For CDL commands that completed without an error, check if we have
+	 * sense data (ATA_SENSE is set). If we do, then the command may have
+	 * been aborted by the device due to a limit timeout using the policy
+	 * 0xD. For these commands, invoke EH to get the command sense data.
+	 */
+	if (qc->flags & ATA_QCFLAG_HAS_CDL &&
+	    qc->result_tf.status & ATA_SENSE) {
+		/*
+		 * Tell SCSI EH to not overwrite scmd->result even if this
+		 * command is finished with result SAM_STAT_GOOD.
 		 */
-		switch (qc->tf.command) {
-		case ATA_CMD_SET_FEATURES:
-			if (qc->tf.feature != SETFEATURES_WC_ON &&
-			    qc->tf.feature != SETFEATURES_WC_OFF &&
-			    qc->tf.feature != SETFEATURES_RA_ON &&
-			    qc->tf.feature != SETFEATURES_RA_OFF)
-				break;
-			/* fall through */
-		case ATA_CMD_INIT_DEV_PARAMS: /* CHS translation changed */
-		case ATA_CMD_SET_MULTI: /* multi_count changed */
-			/* revalidate device */
-			ehi->dev_action[dev->devno] |= ATA_EH_REVALIDATE;
-			ata_port_schedule_eh(ap);
-			break;
+		qc->scsicmd->flags |= SCMD_FORCE_EH_SUCCESS;
+		qc->flags |= ATA_QCFLAG_EH_SUCCESS_CMD;
+		ehi->dev_action[dev->devno] |= ATA_EH_GET_SUCCESS_SENSE;
 
-		case ATA_CMD_SLEEP:
-			dev->flags |= ATA_DFLAG_SLEEPING;
-			break;
-		}
+		/*
+		 * set pending so that ata_qc_schedule_eh() does not trigger
+		 * fast drain, and freeze the port.
+		 */
+		ap->pflags |= ATA_PFLAG_EH_PENDING;
+		ata_qc_schedule_eh(qc);
+		return;
+	}
 
-		if (unlikely(dev->flags & ATA_DFLAG_DUBIOUS_XFER))
-			ata_verify_xfer(qc);
+	/* Some commands need post-processing after successful completion. */
+	switch (qc->tf.command) {
+	case ATA_CMD_SET_FEATURES:
+		if (qc->tf.feature != SETFEATURES_WC_ON &&
+		    qc->tf.feature != SETFEATURES_WC_OFF &&
+		    qc->tf.feature != SETFEATURES_RA_ON &&
+		    qc->tf.feature != SETFEATURES_RA_OFF)
+			break;
+		fallthrough;
+	case ATA_CMD_INIT_DEV_PARAMS: /* CHS translation changed */
+	case ATA_CMD_SET_MULTI: /* multi_count changed */
+		/* revalidate device */
+		ehi->dev_action[dev->devno] |= ATA_EH_REVALIDATE;
+		ata_port_schedule_eh(ap);
+		break;
 
-		__ata_qc_complete(qc);
-	} else {
-		if (qc->flags & ATA_QCFLAG_EH_SCHEDULED)
-			return;
+	case ATA_CMD_SLEEP:
+		dev->flags |= ATA_DFLAG_SLEEPING;
+		break;
+	}
 
-		/* read result TF if failed or requested */
-		if (qc->err_mask || qc->flags & ATA_QCFLAG_RESULT_TF)
-			fill_result_tf(qc);
+	if (unlikely(dev->flags & ATA_DFLAG_DUBIOUS_XFER))
+		ata_verify_xfer(qc);
 
-		__ata_qc_complete(qc);
-	}
+	__ata_qc_complete(qc);
 }
 EXPORT_SYMBOL_GPL(ata_qc_complete);
 
@@ -4767,11 +5054,8 @@ void ata_qc_issue(struct ata_queued_cmd *qc)
 	struct ata_link *link = qc->dev->link;
 	u8 prot = qc->tf.protocol;
 
-	/* Make sure only one non-NCQ command is outstanding.  The
-	 * check is skipped for old EH because it reuses active qc to
-	 * request ATAPI sense.
-	 */
-	WARN_ON_ONCE(ap->ops->error_handler && ata_tag_valid(link->active_tag));
+	/* Make sure only one non-NCQ command is outstanding. */
+	WARN_ON_ONCE(ata_tag_valid(link->active_tag));
 
 	if (ata_is_ncq(prot)) {
 		WARN_ON_ONCE(link->sactive & (1 << qc->hw_tag));
@@ -4809,9 +5093,13 @@ void ata_qc_issue(struct ata_queued_cmd *qc)
 		return;
 	}
 
-	qc->err_mask |= ap->ops->qc_prep(qc);
-	if (unlikely(qc->err_mask))
-		goto err;
+	if (ap->ops->qc_prep) {
+		trace_ata_qc_prep(qc);
+		qc->err_mask |= ap->ops->qc_prep(qc);
+		if (unlikely(qc->err_mask))
+			goto err;
+	}
+
 	trace_ata_qc_issue(qc);
 	qc->err_mask |= ap->ops->qc_issue(qc);
 	if (unlikely(qc->err_mask))
@@ -4934,17 +5222,19 @@ static void ata_port_request_pm(struct ata_port *ap, pm_message_t mesg,
 	struct ata_link *link;
 	unsigned long flags;
 
-	/* Previous resume operation might still be in
-	 * progress.  Wait for PM_PENDING to clear.
+	spin_lock_irqsave(ap->lock, flags);
+
+	/*
+	 * A previous PM operation might still be in progress. Wait for
+	 * ATA_PFLAG_PM_PENDING to clear.
 	 */
 	if (ap->pflags & ATA_PFLAG_PM_PENDING) {
+		spin_unlock_irqrestore(ap->lock, flags);
 		ata_port_wait_eh(ap);
-		WARN_ON(ap->pflags & ATA_PFLAG_PM_PENDING);
+		spin_lock_irqsave(ap->lock, flags);
 	}
 
-	/* request PM ops to EH */
-	spin_lock_irqsave(ap->lock, flags);
-
+	/* Request PM operation to EH */
 	ap->pm_mesg = mesg;
 	ap->pflags |= ATA_PFLAG_PM_PENDING;
 	ata_for_each_link(link, ap, HOST_FIRST) {
@@ -4956,31 +5246,33 @@ static void ata_port_request_pm(struct ata_port *ap, pm_message_t mesg,
 
 	spin_unlock_irqrestore(ap->lock, flags);
 
-	if (!async) {
+	if (!async)
 		ata_port_wait_eh(ap);
-		WARN_ON(ap->pflags & ATA_PFLAG_PM_PENDING);
-	}
 }
 
-/*
- * On some hardware, device fails to respond after spun down for suspend.  As
- * the device won't be used before being resumed, we don't need to touch the
- * device.  Ask EH to skip the usual stuff and proceed directly to suspend.
- *
- * http://thread.gmane.org/gmane.linux.ide/46764
- */
-static const unsigned int ata_port_suspend_ehi = ATA_EHI_QUIET
-						 | ATA_EHI_NO_AUTOPSY
-						 | ATA_EHI_NO_RECOVERY;
-
-static void ata_port_suspend(struct ata_port *ap, pm_message_t mesg)
+static void ata_port_suspend(struct ata_port *ap, pm_message_t mesg,
+			     bool async)
 {
-	ata_port_request_pm(ap, mesg, 0, ata_port_suspend_ehi, false);
-}
+	/*
+	 * We are about to suspend the port, so we do not care about
+	 * scsi_rescan_device() calls scheduled by previous resume operations.
+	 * The next resume will schedule the rescan again. So cancel any rescan
+	 * that is not done yet.
+	 */
+	cancel_delayed_work_sync(&ap->scsi_rescan_task);
 
-static void ata_port_suspend_async(struct ata_port *ap, pm_message_t mesg)
-{
-	ata_port_request_pm(ap, mesg, 0, ata_port_suspend_ehi, true);
+	/*
+	 * On some hardware, device fails to respond after spun down for
+	 * suspend. As the device will not be used until being resumed, we
+	 * do not need to touch the device. Ask EH to skip the usual stuff
+	 * and proceed directly to suspend.
+	 *
+	 * http://thread.gmane.org/gmane.linux.ide/46764
+	 */
+	ata_port_request_pm(ap, mesg, 0,
+			    ATA_EHI_QUIET | ATA_EHI_NO_AUTOPSY |
+			    ATA_EHI_NO_RECOVERY,
+			    async);
 }
 
 static int ata_port_pm_suspend(struct device *dev)
@@ -4990,7 +5282,7 @@ static int ata_port_pm_suspend(struct device *dev)
 	if (pm_runtime_suspended(dev))
 		return 0;
 
-	ata_port_suspend(ap, PMSG_SUSPEND);
+	ata_port_suspend(ap, PMSG_SUSPEND, false);
 	return 0;
 }
 
@@ -5001,35 +5293,29 @@ static int ata_port_pm_freeze(struct device *dev)
 	if (pm_runtime_suspended(dev))
 		return 0;
 
-	ata_port_suspend(ap, PMSG_FREEZE);
+	ata_port_suspend(ap, PMSG_FREEZE, false);
 	return 0;
 }
 
 static int ata_port_pm_poweroff(struct device *dev)
 {
-	ata_port_suspend(to_ata_port(dev), PMSG_HIBERNATE);
+	if (!pm_runtime_suspended(dev))
+		ata_port_suspend(to_ata_port(dev), PMSG_HIBERNATE, false);
 	return 0;
 }
 
-static const unsigned int ata_port_resume_ehi = ATA_EHI_NO_AUTOPSY
-						| ATA_EHI_QUIET;
-
-static void ata_port_resume(struct ata_port *ap, pm_message_t mesg)
-{
-	ata_port_request_pm(ap, mesg, ATA_EH_RESET, ata_port_resume_ehi, false);
-}
-
-static void ata_port_resume_async(struct ata_port *ap, pm_message_t mesg)
+static void ata_port_resume(struct ata_port *ap, pm_message_t mesg,
+			    bool async)
 {
-	ata_port_request_pm(ap, mesg, ATA_EH_RESET, ata_port_resume_ehi, true);
+	ata_port_request_pm(ap, mesg, ATA_EH_RESET,
+			    ATA_EHI_NO_AUTOPSY | ATA_EHI_QUIET,
+			    async);
 }
 
 static int ata_port_pm_resume(struct device *dev)
 {
-	ata_port_resume_async(to_ata_port(dev), PMSG_RESUME);
-	pm_runtime_disable(dev);
-	pm_runtime_set_active(dev);
-	pm_runtime_enable(dev);
+	if (!pm_runtime_suspended(dev))
+		ata_port_resume(to_ata_port(dev), PMSG_RESUME, true);
 	return 0;
 }
 
@@ -5059,13 +5345,13 @@ static int ata_port_runtime_idle(struct device *dev)
 
 static int ata_port_runtime_suspend(struct device *dev)
 {
-	ata_port_suspend(to_ata_port(dev), PMSG_AUTO_SUSPEND);
+	ata_port_suspend(to_ata_port(dev), PMSG_AUTO_SUSPEND, false);
 	return 0;
 }
 
 static int ata_port_runtime_resume(struct device *dev)
 {
-	ata_port_resume(to_ata_port(dev), PMSG_AUTO_RESUME);
+	ata_port_resume(to_ata_port(dev), PMSG_AUTO_RESUME, false);
 	return 0;
 }
 
@@ -5089,13 +5375,13 @@ static const struct dev_pm_ops ata_port_pm_ops = {
  */
 void ata_sas_port_suspend(struct ata_port *ap)
 {
-	ata_port_suspend_async(ap, PMSG_SUSPEND);
+	ata_port_suspend(ap, PMSG_SUSPEND, true);
 }
 EXPORT_SYMBOL_GPL(ata_sas_port_suspend);
 
 void ata_sas_port_resume(struct ata_port *ap)
 {
-	ata_port_resume_async(ap, PMSG_RESUME);
+	ata_port_resume(ap, PMSG_RESUME, true);
 }
 EXPORT_SYMBOL_GPL(ata_sas_port_resume);
 
@@ -5106,10 +5392,9 @@ EXPORT_SYMBOL_GPL(ata_sas_port_resume);
  *
  *	Suspend @host.  Actual operation is performed by port suspend.
  */
-int ata_host_suspend(struct ata_host *host, pm_message_t mesg)
+void ata_host_suspend(struct ata_host *host, pm_message_t mesg)
 {
 	host->dev->power.power_state = mesg;
-	return 0;
 }
 EXPORT_SYMBOL_GPL(ata_host_suspend);
 
@@ -5127,7 +5412,7 @@ EXPORT_SYMBOL_GPL(ata_host_resume);
 #endif
 
 const struct device_type ata_port_type = {
-	.name = "ata_port",
+	.name = ATA_PORT_TYPE_NAME,
 #ifdef CONFIG_PM
 	.pm = &ata_port_pm_ops,
 #endif
@@ -5158,7 +5443,7 @@ void ata_dev_init(struct ata_device *dev)
 	 */
 	spin_lock_irqsave(ap->lock, flags);
 	dev->flags &= ~ATA_DFLAG_INIT_MASK;
-	dev->horkage = 0;
+	dev->quirks = 0;
 	spin_unlock_irqrestore(ap->lock, flags);
 
 	memset((void *)dev + ATA_DEVICE_CLEAR_BEGIN, 0,
@@ -5209,7 +5494,7 @@ void ata_link_init(struct ata_port *ap, struct ata_link *link, int pmp)
  *	sata_link_init_spd - Initialize link->sata_spd_limit
  *	@link: Link to configure sata_spd_limit for
  *
- *	Initialize @link->[hw_]sata_spd_limit to the currently
+ *	Initialize ``link->[hw_]sata_spd_limit`` to the currently
  *	configured value.
  *
  *	LOCKING:
@@ -5253,8 +5538,7 @@ int sata_link_init_spd(struct ata_link *link)
 struct ata_port *ata_port_alloc(struct ata_host *host)
 {
 	struct ata_port *ap;
-
-	DPRINTK("ENTER\n");
+	int id;
 
 	ap = kzalloc(sizeof(*ap), GFP_KERNEL);
 	if (!ap)
@@ -5262,23 +5546,18 @@ struct ata_port *ata_port_alloc(struct ata_host *host)
 
 	ap->pflags |= ATA_PFLAG_INITIALIZING | ATA_PFLAG_FROZEN;
 	ap->lock = &host->lock;
-	ap->print_id = -1;
-	ap->local_port_no = -1;
+	id = ida_alloc_min(&ata_ida, 1, GFP_KERNEL);
+	if (id < 0) {
+		kfree(ap);
+		return NULL;
+	}
+	ap->print_id = id;
 	ap->host = host;
 	ap->dev = host->dev;
 
-#if defined(ATA_VERBOSE_DEBUG)
-	/* turn on all debugging levels */
-	ap->msg_enable = 0x00FF;
-#elif defined(ATA_DEBUG)
-	ap->msg_enable = ATA_MSG_DRV | ATA_MSG_INFO | ATA_MSG_CTL | ATA_MSG_WARN | ATA_MSG_ERR;
-#else
-	ap->msg_enable = ATA_MSG_DRV | ATA_MSG_ERR | ATA_MSG_WARN;
-#endif
-
 	mutex_init(&ap->scsi_scan_mutex);
 	INIT_DELAYED_WORK(&ap->hotplug_task, ata_scsi_hotplug);
-	INIT_WORK(&ap->scsi_rescan_task, ata_scsi_dev_rescan);
+	INIT_DELAYED_WORK(&ap->scsi_rescan_task, ata_scsi_dev_rescan);
 	INIT_LIST_HEAD(&ap->eh_done_q);
 	init_waitqueue_head(&ap->eh_wait_q);
 	init_completion(&ap->park_req_pending);
@@ -5295,8 +5574,23 @@ struct ata_port *ata_port_alloc(struct ata_host *host)
 #endif
 	ata_sff_port_init(ap);
 
+	ata_force_pflags(ap);
+
 	return ap;
 }
+EXPORT_SYMBOL_GPL(ata_port_alloc);
+
+void ata_port_free(struct ata_port *ap)
+{
+	if (!ap)
+		return;
+
+	kfree(ap->pmp_link);
+	kfree(ap->slave_link);
+	ida_free(&ata_ida, ap->print_id);
+	kfree(ap);
+}
+EXPORT_SYMBOL_GPL(ata_port_free);
 
 static void ata_devres_release(struct device *gendev, void *res)
 {
@@ -5324,11 +5618,7 @@ static void ata_host_release(struct kref *kref)
 	int i;
 
 	for (i = 0; i < host->n_ports; i++) {
-		struct ata_port *ap = host->ports[i];
-
-		kfree(ap->pmp_link);
-		kfree(ap->slave_link);
-		kfree(ap);
+		ata_port_free(host->ports[i]);
 		host->ports[i] = NULL;
 	}
 	kfree(host);
@@ -5348,44 +5638,41 @@ EXPORT_SYMBOL_GPL(ata_host_put);
 /**
  *	ata_host_alloc - allocate and init basic ATA host resources
  *	@dev: generic device this host is associated with
- *	@max_ports: maximum number of ATA ports associated with this host
+ *	@n_ports: the number of ATA ports associated with this host
  *
  *	Allocate and initialize basic ATA host resources.  LLD calls
  *	this function to allocate a host, initializes it fully and
  *	attaches it using ata_host_register().
  *
- *	@max_ports ports are allocated and host->n_ports is
- *	initialized to @max_ports.  The caller is allowed to decrease
- *	host->n_ports before calling ata_host_register().  The unused
- *	ports will be automatically freed on registration.
- *
  *	RETURNS:
  *	Allocate ATA host on success, NULL on failure.
  *
  *	LOCKING:
  *	Inherited from calling layer (may sleep).
  */
-struct ata_host *ata_host_alloc(struct device *dev, int max_ports)
+struct ata_host *ata_host_alloc(struct device *dev, int n_ports)
 {
 	struct ata_host *host;
 	size_t sz;
 	int i;
 	void *dr;
 
-	DPRINTK("ENTER\n");
-
 	/* alloc a container for our list of ATA ports (buses) */
-	sz = sizeof(struct ata_host) + (max_ports + 1) * sizeof(void *);
+	sz = sizeof(struct ata_host) + n_ports * sizeof(void *);
 	host = kzalloc(sz, GFP_KERNEL);
 	if (!host)
 		return NULL;
 
-	if (!devres_open_group(dev, NULL, GFP_KERNEL))
-		goto err_free;
+	if (!devres_open_group(dev, NULL, GFP_KERNEL)) {
+		kfree(host);
+		return NULL;
+	}
 
 	dr = devres_alloc(ata_devres_release, 0, GFP_KERNEL);
-	if (!dr)
+	if (!dr) {
+		kfree(host);
 		goto err_out;
+	}
 
 	devres_add(dev, dr);
 	dev_set_drvdata(dev, host);
@@ -5393,11 +5680,11 @@ struct ata_host *ata_host_alloc(struct device *dev, int max_ports)
 	spin_lock_init(&host->lock);
 	mutex_init(&host->eh_mutex);
 	host->dev = dev;
-	host->n_ports = max_ports;
+	host->n_ports = n_ports;
 	kref_init(&host->kref);
 
 	/* allocate ports bound to this host */
-	for (i = 0; i < max_ports; i++) {
+	for (i = 0; i < n_ports; i++) {
 		struct ata_port *ap;
 
 		ap = ata_port_alloc(host);
@@ -5413,8 +5700,6 @@ struct ata_host *ata_host_alloc(struct device *dev, int max_ports)
 
  err_out:
 	devres_release_group(dev, NULL);
- err_free:
-	kfree(host);
 	return NULL;
 }
 EXPORT_SYMBOL_GPL(ata_host_alloc);
@@ -5439,7 +5724,7 @@ struct ata_host *ata_host_alloc_pinfo(struct device *dev,
 				      const struct ata_port_info * const * ppi,
 				      int n_ports)
 {
-	const struct ata_port_info *pi;
+	const struct ata_port_info *pi = &ata_dummy_port_info;
 	struct ata_host *host;
 	int i, j;
 
@@ -5447,7 +5732,7 @@ struct ata_host *ata_host_alloc_pinfo(struct device *dev,
 	if (!host)
 		return NULL;
 
-	for (i = 0, j = 0, pi = NULL; i < host->n_ports; i++) {
+	for (i = 0, j = 0; i < host->n_ports; i++) {
 		struct ata_port *ap = host->ports[i];
 
 		if (ppi[j])
@@ -5543,7 +5828,7 @@ static void ata_finalize_port_ops(struct ata_port_operations *ops)
  *	Start and then freeze ports of @host.  Started status is
  *	recorded in host->flags, so this function can be called
  *	multiple times.  Ports are guaranteed to get started only
- *	once.  If host->ops isn't initialized yet, its set to the
+ *	once.  If host->ops is not initialized yet, it is set to the
  *	first non-dummy port ops.
  *
  *	LOCKING:
@@ -5575,7 +5860,7 @@ int ata_host_start(struct ata_host *host)
 			have_stop = 1;
 	}
 
-	if (host->ops->host_stop)
+	if (host->ops && host->ops->host_stop)
 		have_stop = 1;
 
 	if (have_stop) {
@@ -5618,7 +5903,7 @@ int ata_host_start(struct ata_host *host)
 EXPORT_SYMBOL_GPL(ata_host_start);
 
 /**
- *	ata_sas_host_init - Initialize a host struct for sas (ipr, libsas)
+ *	ata_host_init - Initialize a host struct for sas (ipr, libsas)
  *	@host:	host to initialize
  *	@dev:	device host is attached to
  *	@ops:	port_ops
@@ -5636,11 +5921,13 @@ void ata_host_init(struct ata_host *host, struct device *dev,
 }
 EXPORT_SYMBOL_GPL(ata_host_init);
 
-void __ata_port_probe(struct ata_port *ap)
+void ata_port_probe(struct ata_port *ap)
 {
 	struct ata_eh_info *ehi = &ap->link.eh_info;
 	unsigned long flags;
 
+	ata_acpi_port_power_on(ap);
+
 	/* kick EH for boot probing */
 	spin_lock_irqsave(ap->lock, flags);
 
@@ -5654,22 +5941,7 @@ void __ata_port_probe(struct ata_port *ap)
 
 	spin_unlock_irqrestore(ap->lock, flags);
 }
-
-int ata_port_probe(struct ata_port *ap)
-{
-	int rc = 0;
-
-	if (ap->ops->error_handler) {
-		__ata_port_probe(ap);
-		ata_port_wait_eh(ap);
-	} else {
-		DPRINTK("ata%u: bus probe begin\n", ap->print_id);
-		rc = ata_bus_probe(ap);
-		DPRINTK("ata%u: bus probe end\n", ap->print_id);
-	}
-	return rc;
-}
-
+EXPORT_SYMBOL_GPL(ata_port_probe);
 
 static void async_port_probe(void *data, async_cookie_t cookie)
 {
@@ -5685,7 +5957,8 @@ static void async_port_probe(void *data, async_cookie_t cookie)
 	if (!(ap->host->flags & ATA_HOST_PARALLEL_SCAN) && ap->port_no != 0)
 		async_synchronize_cookie(cookie);
 
-	(void)ata_port_probe(ap);
+	ata_port_probe(ap);
+	ata_port_wait_eh(ap);
 
 	/* in order to keep device order, we need to synchronize at this point */
 	async_synchronize_cookie(cookie);
@@ -5709,7 +5982,7 @@ static void async_port_probe(void *data, async_cookie_t cookie)
  *	RETURNS:
  *	0 on success, -errno otherwise.
  */
-int ata_host_register(struct ata_host *host, struct scsi_host_template *sht)
+int ata_host_register(struct ata_host *host, const struct scsi_host_template *sht)
 {
 	int i, rc;
 
@@ -5722,19 +5995,6 @@ int ata_host_register(struct ata_host *host, struct scsi_host_template *sht)
 		return -EINVAL;
 	}
 
-	/* Blow away unused ports.  This happens when LLD can't
-	 * determine the exact number of ports to allocate at
-	 * allocation time.
-	 */
-	for (i = host->n_ports; host->ports[i]; i++)
-		kfree(host->ports[i]);
-
-	/* give ports names and add SCSI hosts */
-	for (i = 0; i < host->n_ports; i++) {
-		host->ports[i]->print_id = atomic_inc_return(&ata_print_id);
-		host->ports[i]->local_port_no = i + 1;
-	}
-
 	/* Create associated sysfs transport objects  */
 	for (i = 0; i < host->n_ports; i++) {
 		rc = ata_tport_add(host->dev,host->ports[i]);
@@ -5750,7 +6010,7 @@ int ata_host_register(struct ata_host *host, struct scsi_host_template *sht)
 	/* set cable, sata_spd_limit and report */
 	for (i = 0; i < host->n_ports; i++) {
 		struct ata_port *ap = host->ports[i];
-		unsigned long xfer_mask;
+		unsigned int xfer_mask;
 
 		/* set SATA cable type if still unset */
 		if (ap->cbl == ATA_CBL_NONE && (ap->flags & ATA_FLAG_SATA))
@@ -5778,7 +6038,7 @@ int ata_host_register(struct ata_host *host, struct scsi_host_template *sht)
 	/* perform each probe asynchronously */
 	for (i = 0; i < host->n_ports; i++) {
 		struct ata_port *ap = host->ports[i];
-		async_schedule(async_port_probe, ap);
+		ap->cookie = async_schedule(async_port_probe, ap);
 	}
 
 	return 0;
@@ -5817,7 +6077,7 @@ EXPORT_SYMBOL_GPL(ata_host_register);
  */
 int ata_host_activate(struct ata_host *host, int irq,
 		      irq_handler_t irq_handler, unsigned long irq_flags,
-		      struct scsi_host_template *sht)
+		      const struct scsi_host_template *sht)
 {
 	int i, rc;
 	char *irq_desc;
@@ -5844,7 +6104,7 @@ int ata_host_activate(struct ata_host *host, int irq,
 		return rc;
 
 	for (i = 0; i < host->n_ports; i++)
-		ata_port_desc(host->ports[i], "irq %d", irq);
+		ata_port_desc_misc(host->ports[i], irq);
 
 	rc = ata_host_register(host, sht);
 	/* if failed, just free the IRQ and leave ports alone */
@@ -5856,6 +6116,23 @@ int ata_host_activate(struct ata_host *host, int irq,
 EXPORT_SYMBOL_GPL(ata_host_activate);
 
 /**
+ *	ata_dev_free_resources - Free a device resources
+ *	@dev: Target ATA device
+ *
+ *	Free resources allocated to support a device features.
+ *
+ *	LOCKING:
+ *	Kernel thread context (may sleep).
+ */
+void ata_dev_free_resources(struct ata_device *dev)
+{
+	if (zpodd_dev_enabled(dev))
+		zpodd_exit(dev);
+
+	ata_dev_cleanup_cdl_resources(dev);
+}
+
+/**
  *	ata_port_detach - Detach ATA port in preparation of device removal
  *	@ap: ATA port to be detached
  *
@@ -5872,14 +6149,33 @@ static void ata_port_detach(struct ata_port *ap)
 	struct ata_link *link;
 	struct ata_device *dev;
 
-	if (!ap->ops->error_handler)
-		goto skip_eh;
+	/* Ensure ata_port probe has completed */
+	async_synchronize_cookie(ap->cookie + 1);
+
+	/* Wait for any ongoing EH */
+	ata_port_wait_eh(ap);
 
-	/* tell EH we're leaving & flush EH */
+	mutex_lock(&ap->scsi_scan_mutex);
 	spin_lock_irqsave(ap->lock, flags);
+
+	/* Remove scsi devices */
+	ata_for_each_link(link, ap, HOST_FIRST) {
+		ata_for_each_dev(dev, link, ALL) {
+			if (dev->sdev) {
+				spin_unlock_irqrestore(ap->lock, flags);
+				scsi_remove_device(dev->sdev);
+				spin_lock_irqsave(ap->lock, flags);
+				dev->sdev = NULL;
+			}
+		}
+	}
+
+	/* Tell EH to disable all devices */
 	ap->pflags |= ATA_PFLAG_UNLOADING;
 	ata_port_schedule_eh(ap);
+
 	spin_unlock_irqrestore(ap->lock, flags);
+	mutex_unlock(&ap->scsi_scan_mutex);
 
 	/* wait till EH commits suicide */
 	ata_port_wait_eh(ap);
@@ -5888,21 +6184,17 @@ static void ata_port_detach(struct ata_port *ap)
 	WARN_ON(!(ap->pflags & ATA_PFLAG_UNLOADED));
 
 	cancel_delayed_work_sync(&ap->hotplug_task);
+	cancel_delayed_work_sync(&ap->scsi_rescan_task);
 
- skip_eh:
-	/* clean up zpodd on port removal */
-	ata_for_each_link(link, ap, HOST_FIRST) {
-		ata_for_each_dev(dev, link, ALL) {
-			if (zpodd_dev_enabled(dev))
-				zpodd_exit(dev);
-		}
-	}
+	/* Delete port multiplier link transport devices */
 	if (ap->pmp_link) {
 		int i;
+
 		for (i = 0; i < SATA_PMP_MAX_PORTS; i++)
 			ata_tlink_delete(&ap->pmp_link[i]);
 	}
-	/* remove the associated SCSI host */
+
+	/* Remove the associated SCSI host */
 	scsi_remove_host(ap->scsi_host);
 	ata_tport_delete(ap);
 }
@@ -5920,9 +6212,6 @@ void ata_host_detach(struct ata_host *host)
 {
 	int i;
 
-	/* Ensure ata_port probe has completed */
-	async_synchronize_full();
-
 	for (i = 0; i < host->n_ports; i++)
 		ata_port_detach(host->ports[i]);
 
@@ -6041,11 +6330,8 @@ EXPORT_SYMBOL_GPL(ata_pci_device_do_resume);
 int ata_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
 {
 	struct ata_host *host = pci_get_drvdata(pdev);
-	int rc = 0;
 
-	rc = ata_host_suspend(host, mesg);
-	if (rc)
-		return rc;
+	ata_host_suspend(host, mesg);
 
 	ata_pci_device_do_suspend(pdev, mesg);
 
@@ -6078,76 +6364,128 @@ EXPORT_SYMBOL_GPL(ata_pci_device_resume);
  *	LOCKING:
  *	Inherited from platform layer (may sleep).
  */
-int ata_platform_remove_one(struct platform_device *pdev)
+void ata_platform_remove_one(struct platform_device *pdev)
 {
 	struct ata_host *host = platform_get_drvdata(pdev);
 
 	ata_host_detach(host);
-
-	return 0;
 }
 EXPORT_SYMBOL_GPL(ata_platform_remove_one);
 
 #ifdef CONFIG_ATA_FORCE
+
+#define force_cbl(name, flag)				\
+	{ #name,	.cbl		= (flag) }
+
+#define force_spd_limit(spd, val)			\
+	{ #spd,	.spd_limit		= (val) }
+
+#define force_xfer(mode, shift)				\
+	{ #mode,	.xfer_mask	= (1UL << (shift)) }
+
+#define force_lflag_on(name, flags)			\
+	{ #name,	.lflags_on	= (flags) }
+
+#define force_lflag_onoff(name, flags)			\
+	{ "no" #name,	.lflags_on	= (flags) },	\
+	{ #name,	.lflags_off	= (flags) }
+
+#define force_pflag_on(name, flags)			\
+	{ #name,	.pflags_on	= (flags) }
+
+#define force_quirk_on(name, flag)			\
+	{ #name,	.quirk_on	= (flag) }
+
+#define force_quirk_onoff(name, flag)			\
+	{ "no" #name,	.quirk_on	= (flag) },	\
+	{ #name,	.quirk_off	= (flag) }
+
+static const struct ata_force_param force_tbl[] __initconst = {
+	force_cbl(40c,			ATA_CBL_PATA40),
+	force_cbl(80c,			ATA_CBL_PATA80),
+	force_cbl(short40c,		ATA_CBL_PATA40_SHORT),
+	force_cbl(unk,			ATA_CBL_PATA_UNK),
+	force_cbl(ign,			ATA_CBL_PATA_IGN),
+	force_cbl(sata,			ATA_CBL_SATA),
+
+	force_spd_limit(1.5Gbps,	1),
+	force_spd_limit(3.0Gbps,	2),
+
+	force_xfer(pio0,		ATA_SHIFT_PIO + 0),
+	force_xfer(pio1,		ATA_SHIFT_PIO + 1),
+	force_xfer(pio2,		ATA_SHIFT_PIO + 2),
+	force_xfer(pio3,		ATA_SHIFT_PIO + 3),
+	force_xfer(pio4,		ATA_SHIFT_PIO + 4),
+	force_xfer(pio5,		ATA_SHIFT_PIO + 5),
+	force_xfer(pio6,		ATA_SHIFT_PIO + 6),
+	force_xfer(mwdma0,		ATA_SHIFT_MWDMA + 0),
+	force_xfer(mwdma1,		ATA_SHIFT_MWDMA + 1),
+	force_xfer(mwdma2,		ATA_SHIFT_MWDMA + 2),
+	force_xfer(mwdma3,		ATA_SHIFT_MWDMA + 3),
+	force_xfer(mwdma4,		ATA_SHIFT_MWDMA + 4),
+	force_xfer(udma0,		ATA_SHIFT_UDMA + 0),
+	force_xfer(udma16,		ATA_SHIFT_UDMA + 0),
+	force_xfer(udma/16,		ATA_SHIFT_UDMA + 0),
+	force_xfer(udma1,		ATA_SHIFT_UDMA + 1),
+	force_xfer(udma25,		ATA_SHIFT_UDMA + 1),
+	force_xfer(udma/25,		ATA_SHIFT_UDMA + 1),
+	force_xfer(udma2,		ATA_SHIFT_UDMA + 2),
+	force_xfer(udma33,		ATA_SHIFT_UDMA + 2),
+	force_xfer(udma/33,		ATA_SHIFT_UDMA + 2),
+	force_xfer(udma3,		ATA_SHIFT_UDMA + 3),
+	force_xfer(udma44,		ATA_SHIFT_UDMA + 3),
+	force_xfer(udma/44,		ATA_SHIFT_UDMA + 3),
+	force_xfer(udma4,		ATA_SHIFT_UDMA + 4),
+	force_xfer(udma66,		ATA_SHIFT_UDMA + 4),
+	force_xfer(udma/66,		ATA_SHIFT_UDMA + 4),
+	force_xfer(udma5,		ATA_SHIFT_UDMA + 5),
+	force_xfer(udma100,		ATA_SHIFT_UDMA + 5),
+	force_xfer(udma/100,		ATA_SHIFT_UDMA + 5),
+	force_xfer(udma6,		ATA_SHIFT_UDMA + 6),
+	force_xfer(udma133,		ATA_SHIFT_UDMA + 6),
+	force_xfer(udma/133,		ATA_SHIFT_UDMA + 6),
+	force_xfer(udma7,		ATA_SHIFT_UDMA + 7),
+
+	force_lflag_on(nohrst,		ATA_LFLAG_NO_HRST),
+	force_lflag_on(nosrst,		ATA_LFLAG_NO_SRST),
+	force_lflag_on(norst,		ATA_LFLAG_NO_HRST | ATA_LFLAG_NO_SRST),
+	force_lflag_on(rstonce,		ATA_LFLAG_RST_ONCE),
+	force_lflag_onoff(dbdelay,	ATA_LFLAG_NO_DEBOUNCE_DELAY),
+
+	force_pflag_on(external,	ATA_PFLAG_EXTERNAL),
+
+	force_quirk_onoff(ncq,		ATA_QUIRK_NONCQ),
+	force_quirk_onoff(ncqtrim,	ATA_QUIRK_NO_NCQ_TRIM),
+	force_quirk_onoff(ncqati,	ATA_QUIRK_NO_NCQ_ON_ATI),
+
+	force_quirk_onoff(trim,		ATA_QUIRK_NOTRIM),
+	force_quirk_on(trim_zero,	ATA_QUIRK_ZERO_AFTER_TRIM),
+	force_quirk_on(max_trim_128m,	ATA_QUIRK_MAX_TRIM_128M),
+
+	force_quirk_onoff(dma,		ATA_QUIRK_NODMA),
+	force_quirk_on(atapi_dmadir,	ATA_QUIRK_ATAPI_DMADIR),
+	force_quirk_on(atapi_mod16_dma,	ATA_QUIRK_ATAPI_MOD16_DMA),
+
+	force_quirk_onoff(dmalog,	ATA_QUIRK_NO_DMA_LOG),
+	force_quirk_onoff(iddevlog,	ATA_QUIRK_NO_ID_DEV_LOG),
+	force_quirk_onoff(logdir,	ATA_QUIRK_NO_LOG_DIR),
+
+	force_quirk_on(max_sec_128,	ATA_QUIRK_MAX_SEC_128),
+	force_quirk_on(max_sec_1024,	ATA_QUIRK_MAX_SEC_1024),
+	force_quirk_on(max_sec_lba48,	ATA_QUIRK_MAX_SEC_LBA48),
+
+	force_quirk_onoff(lpm,		ATA_QUIRK_NOLPM),
+	force_quirk_onoff(setxfer,	ATA_QUIRK_NOSETXFER),
+	force_quirk_on(dump_id,		ATA_QUIRK_DUMP_ID),
+	force_quirk_onoff(fua,		ATA_QUIRK_NO_FUA),
+
+	force_quirk_on(disable,		ATA_QUIRK_DISABLE),
+};
+
 static int __init ata_parse_force_one(char **cur,
 				      struct ata_force_ent *force_ent,
 				      const char **reason)
 {
-	static const struct ata_force_param force_tbl[] __initconst = {
-		{ "40c",	.cbl		= ATA_CBL_PATA40 },
-		{ "80c",	.cbl		= ATA_CBL_PATA80 },
-		{ "short40c",	.cbl		= ATA_CBL_PATA40_SHORT },
-		{ "unk",	.cbl		= ATA_CBL_PATA_UNK },
-		{ "ign",	.cbl		= ATA_CBL_PATA_IGN },
-		{ "sata",	.cbl		= ATA_CBL_SATA },
-		{ "1.5Gbps",	.spd_limit	= 1 },
-		{ "3.0Gbps",	.spd_limit	= 2 },
-		{ "noncq",	.horkage_on	= ATA_HORKAGE_NONCQ },
-		{ "ncq",	.horkage_off	= ATA_HORKAGE_NONCQ },
-		{ "noncqtrim",	.horkage_on	= ATA_HORKAGE_NO_NCQ_TRIM },
-		{ "ncqtrim",	.horkage_off	= ATA_HORKAGE_NO_NCQ_TRIM },
-		{ "dump_id",	.horkage_on	= ATA_HORKAGE_DUMP_ID },
-		{ "pio0",	.xfer_mask	= 1 << (ATA_SHIFT_PIO + 0) },
-		{ "pio1",	.xfer_mask	= 1 << (ATA_SHIFT_PIO + 1) },
-		{ "pio2",	.xfer_mask	= 1 << (ATA_SHIFT_PIO + 2) },
-		{ "pio3",	.xfer_mask	= 1 << (ATA_SHIFT_PIO + 3) },
-		{ "pio4",	.xfer_mask	= 1 << (ATA_SHIFT_PIO + 4) },
-		{ "pio5",	.xfer_mask	= 1 << (ATA_SHIFT_PIO + 5) },
-		{ "pio6",	.xfer_mask	= 1 << (ATA_SHIFT_PIO + 6) },
-		{ "mwdma0",	.xfer_mask	= 1 << (ATA_SHIFT_MWDMA + 0) },
-		{ "mwdma1",	.xfer_mask	= 1 << (ATA_SHIFT_MWDMA + 1) },
-		{ "mwdma2",	.xfer_mask	= 1 << (ATA_SHIFT_MWDMA + 2) },
-		{ "mwdma3",	.xfer_mask	= 1 << (ATA_SHIFT_MWDMA + 3) },
-		{ "mwdma4",	.xfer_mask	= 1 << (ATA_SHIFT_MWDMA + 4) },
-		{ "udma0",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 0) },
-		{ "udma16",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 0) },
-		{ "udma/16",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 0) },
-		{ "udma1",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 1) },
-		{ "udma25",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 1) },
-		{ "udma/25",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 1) },
-		{ "udma2",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 2) },
-		{ "udma33",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 2) },
-		{ "udma/33",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 2) },
-		{ "udma3",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 3) },
-		{ "udma44",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 3) },
-		{ "udma/44",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 3) },
-		{ "udma4",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 4) },
-		{ "udma66",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 4) },
-		{ "udma/66",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 4) },
-		{ "udma5",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 5) },
-		{ "udma100",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 5) },
-		{ "udma/100",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 5) },
-		{ "udma6",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 6) },
-		{ "udma133",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 6) },
-		{ "udma/133",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 6) },
-		{ "udma7",	.xfer_mask	= 1 << (ATA_SHIFT_UDMA + 7) },
-		{ "nohrst",	.lflags		= ATA_LFLAG_NO_HRST },
-		{ "nosrst",	.lflags		= ATA_LFLAG_NO_SRST },
-		{ "norst",	.lflags		= ATA_LFLAG_NO_HRST | ATA_LFLAG_NO_SRST },
-		{ "rstonce",	.lflags		= ATA_LFLAG_RST_ONCE },
-		{ "atapi_dmadir", .horkage_on	= ATA_HORKAGE_ATAPI_DMADIR },
-		{ "disable",	.horkage_on	= ATA_HORKAGE_DISABLE },
-	};
 	char *start = *cur, *p = *cur;
 	char *id, *val, *endp;
 	const struct ata_force_param *match_fp = NULL;
@@ -6229,7 +6567,7 @@ static void __init ata_parse_force_param(void)
 	int last_port = -1, last_device = -1;
 	char *p, *cur, *next;
 
-	/* calculate maximum number of params and allocate force_tbl */
+	/* Calculate maximum number of params and allocate ata_force_tbl */
 	for (p = ata_force_param_buf; *p; p++)
 		if (*p == ',')
 			size++;
@@ -6381,7 +6719,7 @@ EXPORT_SYMBOL_GPL(ata_msleep);
  *	The final register value.
  */
 u32 ata_wait_register(struct ata_port *ap, void __iomem *reg, u32 mask, u32 val,
-		      unsigned long interval, unsigned long timeout)
+		      unsigned int interval, unsigned int timeout)
 {
 	unsigned long deadline;
 	u32 tmp;
@@ -6417,7 +6755,6 @@ static void ata_dummy_error_handler(struct ata_port *ap)
 }
 
 struct ata_port_operations ata_dummy_port_ops = {
-	.qc_prep		= ata_noop_qc_prep,
 	.qc_issue		= ata_dummy_qc_issue,
 	.error_handler		= ata_dummy_error_handler,
 	.sched_eh		= ata_std_sched_eh,
@@ -6430,69 +6767,8 @@ const struct ata_port_info ata_dummy_port_info = {
 };
 EXPORT_SYMBOL_GPL(ata_dummy_port_info);
 
-/*
- * Utility print functions
- */
-void ata_port_printk(const struct ata_port *ap, const char *level,
-		     const char *fmt, ...)
-{
-	struct va_format vaf;
-	va_list args;
-
-	va_start(args, fmt);
-
-	vaf.fmt = fmt;
-	vaf.va = &args;
-
-	printk("%sata%u: %pV", level, ap->print_id, &vaf);
-
-	va_end(args);
-}
-EXPORT_SYMBOL(ata_port_printk);
-
-void ata_link_printk(const struct ata_link *link, const char *level,
-		     const char *fmt, ...)
-{
-	struct va_format vaf;
-	va_list args;
-
-	va_start(args, fmt);
-
-	vaf.fmt = fmt;
-	vaf.va = &args;
-
-	if (sata_pmp_attached(link->ap) || link->ap->slave_link)
-		printk("%sata%u.%02u: %pV",
-		       level, link->ap->print_id, link->pmp, &vaf);
-	else
-		printk("%sata%u: %pV",
-		       level, link->ap->print_id, &vaf);
-
-	va_end(args);
-}
-EXPORT_SYMBOL(ata_link_printk);
-
-void ata_dev_printk(const struct ata_device *dev, const char *level,
-		    const char *fmt, ...)
-{
-	struct va_format vaf;
-	va_list args;
-
-	va_start(args, fmt);
-
-	vaf.fmt = fmt;
-	vaf.va = &args;
-
-	printk("%sata%u.%02u: %pV",
-	       level, dev->link->ap->print_id, dev->link->pmp + dev->devno,
-	       &vaf);
-
-	va_end(args);
-}
-EXPORT_SYMBOL(ata_dev_printk);
-
-void ata_print_version(const struct device *dev, const char *version)
-{
-	dev_printk(KERN_DEBUG, dev, "version %s\n", version);
-}
-EXPORT_SYMBOL(ata_print_version);
+EXPORT_TRACEPOINT_SYMBOL_GPL(ata_tf_load);
+EXPORT_TRACEPOINT_SYMBOL_GPL(ata_exec_command);
+EXPORT_TRACEPOINT_SYMBOL_GPL(ata_bmdma_setup);
+EXPORT_TRACEPOINT_SYMBOL_GPL(ata_bmdma_start);
+EXPORT_TRACEPOINT_SYMBOL_GPL(ata_bmdma_status);
diff --git a/drivers/ata/libata-eh.c b/drivers/ata/libata-eh.c
index 474c6c34fe02..2586e77ebf45 100644
--- a/drivers/ata/libata-eh.c
+++ b/drivers/ata/libata-eh.c
@@ -78,38 +78,44 @@ enum {
  * are mostly for error handling, hotplug and those outlier devices that
  * take an exceptionally long time to recover from reset.
  */
-static const unsigned long ata_eh_reset_timeouts[] = {
+static const unsigned int ata_eh_reset_timeouts[] = {
 	10000,	/* most drives spin up by 10sec */
 	10000,	/* > 99% working drives spin up before 20sec */
 	35000,	/* give > 30 secs of idleness for outlier devices */
 	 5000,	/* and sweet one last chance */
-	ULONG_MAX, /* > 1 min has elapsed, give up */
+	UINT_MAX, /* > 1 min has elapsed, give up */
 };
 
-static const unsigned long ata_eh_identify_timeouts[] = {
+static const unsigned int ata_eh_identify_timeouts[] = {
 	 5000,	/* covers > 99% of successes and not too boring on failures */
 	10000,  /* combined time till here is enough even for media access */
 	30000,	/* for true idiots */
-	ULONG_MAX,
+	UINT_MAX,
 };
 
-static const unsigned long ata_eh_flush_timeouts[] = {
+static const unsigned int ata_eh_revalidate_timeouts[] = {
+	15000,	/* Some drives are slow to read log pages when waking-up */
+	15000,  /* combined time till here is enough even for media access */
+	UINT_MAX,
+};
+
+static const unsigned int ata_eh_flush_timeouts[] = {
 	15000,	/* be generous with flush */
 	15000,  /* ditto */
 	30000,	/* and even more generous */
-	ULONG_MAX,
+	UINT_MAX,
 };
 
-static const unsigned long ata_eh_other_timeouts[] = {
+static const unsigned int ata_eh_other_timeouts[] = {
 	 5000,	/* same rationale as identify timeout */
 	10000,	/* ditto */
 	/* but no merciful 30sec for other commands, it just isn't worth it */
-	ULONG_MAX,
+	UINT_MAX,
 };
 
 struct ata_eh_cmd_timeout_ent {
 	const u8		*commands;
-	const unsigned long	*timeouts;
+	const unsigned int	*timeouts;
 };
 
 /* The following table determines timeouts to use for EH internal
@@ -129,6 +135,8 @@ static const struct ata_eh_cmd_timeout_ent
 ata_eh_cmd_timeout_table[ATA_EH_CMD_TIMEOUT_TABLE_SIZE] = {
 	{ .commands = CMDS(ATA_CMD_ID_ATA, ATA_CMD_ID_ATAPI),
 	  .timeouts = ata_eh_identify_timeouts, },
+	{ .commands = CMDS(ATA_CMD_READ_LOG_EXT, ATA_CMD_READ_LOG_DMA_EXT),
+	  .timeouts = ata_eh_revalidate_timeouts, },
 	{ .commands = CMDS(ATA_CMD_READ_NATIVE_MAX, ATA_CMD_READ_NATIVE_MAX_EXT),
 	  .timeouts = ata_eh_other_timeouts, },
 	{ .commands = CMDS(ATA_CMD_SET_MAX, ATA_CMD_SET_MAX_EXT),
@@ -139,6 +147,8 @@ ata_eh_cmd_timeout_table[ATA_EH_CMD_TIMEOUT_TABLE_SIZE] = {
 	  .timeouts = ata_eh_other_timeouts, },
 	{ .commands = CMDS(ATA_CMD_FLUSH, ATA_CMD_FLUSH_EXT),
 	  .timeouts = ata_eh_flush_timeouts },
+	{ .commands = CMDS(ATA_CMD_VERIFY),
+	  .timeouts = ata_eh_reset_timeouts },
 };
 #undef CMDS
 
@@ -318,7 +328,7 @@ static int ata_lookup_timeout_table(u8 cmd)
  *	RETURNS:
  *	Determined timeout.
  */
-unsigned long ata_internal_cmd_timeout(struct ata_device *dev, u8 cmd)
+unsigned int ata_internal_cmd_timeout(struct ata_device *dev, u8 cmd)
 {
 	struct ata_eh_context *ehc = &dev->link->eh_context;
 	int ent = ata_lookup_timeout_table(cmd);
@@ -353,7 +363,7 @@ void ata_internal_cmd_timed_out(struct ata_device *dev, u8 cmd)
 		return;
 
 	idx = ehc->cmd_timeout_idx[dev->devno][ent];
-	if (ata_eh_cmd_timeout_table[ent].timeouts[idx + 1] != ULONG_MAX)
+	if (ata_eh_cmd_timeout_table[ent].timeouts[idx + 1] != UINT_MAX)
 		ehc->cmd_timeout_idx[dev->devno][ent]++;
 }
 
@@ -482,19 +492,46 @@ void ata_eh_release(struct ata_port *ap)
 	mutex_unlock(&ap->host->eh_mutex);
 }
 
+static void ata_eh_dev_disable(struct ata_device *dev)
+{
+	ata_acpi_on_disable(dev);
+	ata_down_xfermask_limit(dev, ATA_DNXFER_FORCE_PIO0 | ATA_DNXFER_QUIET);
+	dev->class++;
+
+	/*
+	 * From now till the next successful probe, ering is used to
+	 * track probe failures.  Clear accumulated device error info.
+	 */
+	ata_ering_clear(&dev->ering);
+
+	ata_dev_free_resources(dev);
+}
+
 static void ata_eh_unload(struct ata_port *ap)
 {
 	struct ata_link *link;
 	struct ata_device *dev;
 	unsigned long flags;
 
-	/* Restore SControl IPM and SPD for the next driver and
+	/*
+	 * Unless we are restarting, transition all enabled devices to
+	 * standby power mode.
+	 */
+	if (system_state != SYSTEM_RESTART) {
+		ata_for_each_link(link, ap, PMP_FIRST) {
+			ata_for_each_dev(dev, link, ENABLED)
+				ata_dev_power_set_standby(dev);
+		}
+	}
+
+	/*
+	 * Restore SControl IPM and SPD for the next driver and
 	 * disable attached devices.
 	 */
 	ata_for_each_link(link, ap, PMP_FIRST) {
 		sata_scr_write(link, SCR_CONTROL, link->saved_scontrol & 0xff0);
-		ata_for_each_dev(dev, link, ALL)
-			ata_dev_disable(dev);
+		ata_for_each_dev(dev, link, ENABLED)
+			ata_eh_dev_disable(dev);
 	}
 
 	/* freeze and set UNLOADED */
@@ -525,8 +562,6 @@ void ata_scsi_error(struct Scsi_Host *host)
 	unsigned long flags;
 	LIST_HEAD(eh_work_q);
 
-	DPRINTK("ENTER\n");
-
 	spin_lock_irqsave(host->host_lock, flags);
 	list_splice_init(&host->eh_cmd_q, &eh_work_q);
 	spin_unlock_irqrestore(host->host_lock, flags);
@@ -540,7 +575,6 @@ void ata_scsi_error(struct Scsi_Host *host)
 	/* finish or retry handled scmd's and clean up */
 	WARN_ON(!list_empty(&eh_work_q));
 
-	DPRINTK("EXIT\n");
 }
 
 /**
@@ -558,17 +592,20 @@ void ata_scsi_cmd_error_handler(struct Scsi_Host *host, struct ata_port *ap,
 {
 	int i;
 	unsigned long flags;
+	struct scsi_cmnd *scmd, *tmp;
+	int nr_timedout = 0;
 
 	/* make sure sff pio task is not running */
 	ata_sff_flush_pio_task(ap);
 
 	/* synchronize with host lock and sort out timeouts */
 
-	/* For new EH, all qcs are finished in one of three ways -
+	/*
+	 * For EH, all qcs are finished in one of three ways -
 	 * normal completion, error completion, and SCSI timeout.
 	 * Both completions can race against SCSI timeout.  When normal
 	 * completion wins, the qc never reaches EH.  When error
-	 * completion wins, the qc has ATA_QCFLAG_FAILED set.
+	 * completion wins, the qc has ATA_QCFLAG_EH set.
 	 *
 	 * When SCSI timeout wins, things are a bit more complex.
 	 * Normal or error completion can occur after the timeout but
@@ -577,64 +614,70 @@ void ata_scsi_cmd_error_handler(struct Scsi_Host *host, struct ata_port *ap,
 	 * timed out iff its associated qc is active and not failed.
 	 */
 	spin_lock_irqsave(ap->lock, flags);
-	if (ap->ops->error_handler) {
-		struct scsi_cmnd *scmd, *tmp;
-		int nr_timedout = 0;
 
-		/* This must occur under the ap->lock as we don't want
-		   a polled recovery to race the real interrupt handler
-
-		   The lost_interrupt handler checks for any completed but
-		   non-notified command and completes much like an IRQ handler.
-
-		   We then fall into the error recovery code which will treat
-		   this as if normal completion won the race */
+	/*
+	 * This must occur under the ap->lock as we don't want
+	 * a polled recovery to race the real interrupt handler
+	 *
+	 * The lost_interrupt handler checks for any completed but
+	 * non-notified command and completes much like an IRQ handler.
+	 *
+	 * We then fall into the error recovery code which will treat
+	 * this as if normal completion won the race
+	 */
+	if (ap->ops->lost_interrupt)
+		ap->ops->lost_interrupt(ap);
 
-		if (ap->ops->lost_interrupt)
-			ap->ops->lost_interrupt(ap);
+	list_for_each_entry_safe(scmd, tmp, eh_work_q, eh_entry) {
+		struct ata_queued_cmd *qc;
 
-		list_for_each_entry_safe(scmd, tmp, eh_work_q, eh_entry) {
-			struct ata_queued_cmd *qc;
+		/*
+		 * If the scmd was added to EH, via ata_qc_schedule_eh() ->
+		 * scsi_timeout() -> scsi_eh_scmd_add(), scsi_timeout() will
+		 * have set DID_TIME_OUT (since libata does not have an abort
+		 * handler). Thus, to clear DID_TIME_OUT, clear the host byte.
+		 */
+		set_host_byte(scmd, DID_OK);
 
-			ata_qc_for_each_raw(ap, qc, i) {
-				if (qc->flags & ATA_QCFLAG_ACTIVE &&
-				    qc->scsicmd == scmd)
-					break;
-			}
+		ata_qc_for_each_raw(ap, qc, i) {
+			if (qc->flags & ATA_QCFLAG_ACTIVE &&
+			    qc->scsicmd == scmd)
+				break;
+		}
 
-			if (i < ATA_MAX_QUEUE) {
-				/* the scmd has an associated qc */
-				if (!(qc->flags & ATA_QCFLAG_FAILED)) {
-					/* which hasn't failed yet, timeout */
-					qc->err_mask |= AC_ERR_TIMEOUT;
-					qc->flags |= ATA_QCFLAG_FAILED;
-					nr_timedout++;
-				}
-			} else {
-				/* Normal completion occurred after
-				 * SCSI timeout but before this point.
-				 * Successfully complete it.
-				 */
-				scmd->retries = scmd->allowed;
-				scsi_eh_finish_cmd(scmd, &ap->eh_done_q);
+		if (i < ATA_MAX_QUEUE) {
+			/* the scmd has an associated qc */
+			if (!(qc->flags & ATA_QCFLAG_EH)) {
+				/* which hasn't failed yet, timeout */
+				set_host_byte(scmd, DID_TIME_OUT);
+				qc->err_mask |= AC_ERR_TIMEOUT;
+				qc->flags |= ATA_QCFLAG_EH;
+				nr_timedout++;
 			}
+		} else {
+			/* Normal completion occurred after
+			 * SCSI timeout but before this point.
+			 * Successfully complete it.
+			 */
+			scmd->retries = scmd->allowed;
+			scsi_eh_finish_cmd(scmd, &ap->eh_done_q);
 		}
+	}
 
-		/* If we have timed out qcs.  They belong to EH from
-		 * this point but the state of the controller is
-		 * unknown.  Freeze the port to make sure the IRQ
-		 * handler doesn't diddle with those qcs.  This must
-		 * be done atomically w.r.t. setting QCFLAG_FAILED.
-		 */
-		if (nr_timedout)
-			__ata_port_freeze(ap);
+	/*
+	 * If we have timed out qcs.  They belong to EH from
+	 * this point but the state of the controller is
+	 * unknown.  Freeze the port to make sure the IRQ
+	 * handler doesn't diddle with those qcs.  This must
+	 * be done atomically w.r.t. setting ATA_QCFLAG_EH.
+	 */
+	if (nr_timedout)
+		__ata_port_freeze(ap);
 
+	/* initialize eh_tries */
+	ap->eh_tries = ATA_EH_MAX_TRIES;
 
-		/* initialize eh_tries */
-		ap->eh_tries = ATA_EH_MAX_TRIES;
-	}
 	spin_unlock_irqrestore(ap->lock, flags);
-
 }
 EXPORT_SYMBOL(ata_scsi_cmd_error_handler);
 
@@ -649,100 +692,101 @@ EXPORT_SYMBOL(ata_scsi_cmd_error_handler);
 void ata_scsi_port_error_handler(struct Scsi_Host *host, struct ata_port *ap)
 {
 	unsigned long flags;
+	struct ata_link *link;
 
-	/* invoke error handler */
-	if (ap->ops->error_handler) {
-		struct ata_link *link;
-
-		/* acquire EH ownership */
-		ata_eh_acquire(ap);
+	/* acquire EH ownership */
+	ata_eh_acquire(ap);
  repeat:
-		/* kill fast drain timer */
-		del_timer_sync(&ap->fastdrain_timer);
+	/* kill fast drain timer */
+	timer_delete_sync(&ap->fastdrain_timer);
 
-		/* process port resume request */
-		ata_eh_handle_port_resume(ap);
+	/* process port resume request */
+	ata_eh_handle_port_resume(ap);
 
-		/* fetch & clear EH info */
-		spin_lock_irqsave(ap->lock, flags);
+	/* fetch & clear EH info */
+	spin_lock_irqsave(ap->lock, flags);
 
-		ata_for_each_link(link, ap, HOST_FIRST) {
-			struct ata_eh_context *ehc = &link->eh_context;
-			struct ata_device *dev;
+	ata_for_each_link(link, ap, HOST_FIRST) {
+		struct ata_eh_context *ehc = &link->eh_context;
+		struct ata_device *dev;
 
-			memset(&link->eh_context, 0, sizeof(link->eh_context));
-			link->eh_context.i = link->eh_info;
-			memset(&link->eh_info, 0, sizeof(link->eh_info));
+		memset(&link->eh_context, 0, sizeof(link->eh_context));
+		link->eh_context.i = link->eh_info;
+		memset(&link->eh_info, 0, sizeof(link->eh_info));
 
-			ata_for_each_dev(dev, link, ENABLED) {
-				int devno = dev->devno;
+		ata_for_each_dev(dev, link, ENABLED) {
+			int devno = dev->devno;
 
-				ehc->saved_xfer_mode[devno] = dev->xfer_mode;
-				if (ata_ncq_enabled(dev))
-					ehc->saved_ncq_enabled |= 1 << devno;
+			ehc->saved_xfer_mode[devno] = dev->xfer_mode;
+			if (ata_ncq_enabled(dev))
+				ehc->saved_ncq_enabled |= 1 << devno;
+
+			/* If we are resuming, wake up the device */
+			if (ap->pflags & ATA_PFLAG_RESUMING) {
+				dev->flags |= ATA_DFLAG_RESUMING;
+				ehc->i.dev_action[devno] |= ATA_EH_SET_ACTIVE;
 			}
 		}
+	}
 
-		ap->pflags |= ATA_PFLAG_EH_IN_PROGRESS;
-		ap->pflags &= ~ATA_PFLAG_EH_PENDING;
-		ap->excl_link = NULL;	/* don't maintain exclusion over EH */
+	ap->pflags |= ATA_PFLAG_EH_IN_PROGRESS;
+	ap->pflags &= ~ATA_PFLAG_EH_PENDING;
+	ap->excl_link = NULL;	/* don't maintain exclusion over EH */
 
-		spin_unlock_irqrestore(ap->lock, flags);
+	spin_unlock_irqrestore(ap->lock, flags);
 
-		/* invoke EH, skip if unloading or suspended */
-		if (!(ap->pflags & (ATA_PFLAG_UNLOADING | ATA_PFLAG_SUSPENDED)))
-			ap->ops->error_handler(ap);
-		else {
-			/* if unloading, commence suicide */
-			if ((ap->pflags & ATA_PFLAG_UNLOADING) &&
-			    !(ap->pflags & ATA_PFLAG_UNLOADED))
-				ata_eh_unload(ap);
-			ata_eh_finish(ap);
-		}
+	/* invoke EH, skip if unloading or suspended */
+	if (!(ap->pflags & (ATA_PFLAG_UNLOADING | ATA_PFLAG_SUSPENDED)))
+		ap->ops->error_handler(ap);
+	else {
+		/* if unloading, commence suicide */
+		if ((ap->pflags & ATA_PFLAG_UNLOADING) &&
+		    !(ap->pflags & ATA_PFLAG_UNLOADED))
+			ata_eh_unload(ap);
+		ata_eh_finish(ap);
+	}
 
-		/* process port suspend request */
-		ata_eh_handle_port_suspend(ap);
+	/* process port suspend request */
+	ata_eh_handle_port_suspend(ap);
 
-		/* Exception might have happened after ->error_handler
-		 * recovered the port but before this point.  Repeat
-		 * EH in such case.
-		 */
-		spin_lock_irqsave(ap->lock, flags);
+	/*
+	 * Exception might have happened after ->error_handler recovered the
+	 * port but before this point.  Repeat EH in such case.
+	 */
+	spin_lock_irqsave(ap->lock, flags);
 
-		if (ap->pflags & ATA_PFLAG_EH_PENDING) {
-			if (--ap->eh_tries) {
-				spin_unlock_irqrestore(ap->lock, flags);
-				goto repeat;
-			}
-			ata_port_err(ap,
-				     "EH pending after %d tries, giving up\n",
-				     ATA_EH_MAX_TRIES);
-			ap->pflags &= ~ATA_PFLAG_EH_PENDING;
+	if (ap->pflags & ATA_PFLAG_EH_PENDING) {
+		if (--ap->eh_tries) {
+			spin_unlock_irqrestore(ap->lock, flags);
+			goto repeat;
 		}
+		ata_port_err(ap,
+			     "EH pending after %d tries, giving up\n",
+			     ATA_EH_MAX_TRIES);
+		ap->pflags &= ~ATA_PFLAG_EH_PENDING;
+	}
 
-		/* this run is complete, make sure EH info is clear */
-		ata_for_each_link(link, ap, HOST_FIRST)
-			memset(&link->eh_info, 0, sizeof(link->eh_info));
+	/* this run is complete, make sure EH info is clear */
+	ata_for_each_link(link, ap, HOST_FIRST)
+		memset(&link->eh_info, 0, sizeof(link->eh_info));
 
-		/* end eh (clear host_eh_scheduled) while holding
-		 * ap->lock such that if exception occurs after this
-		 * point but before EH completion, SCSI midlayer will
-		 * re-initiate EH.
-		 */
-		ap->ops->end_eh(ap);
+	/*
+	 * end eh (clear host_eh_scheduled) while holding ap->lock such that if
+	 * exception occurs after this point but before EH completion, SCSI
+	 * midlayer will re-initiate EH.
+	 */
+	ap->ops->end_eh(ap);
 
-		spin_unlock_irqrestore(ap->lock, flags);
-		ata_eh_release(ap);
-	} else {
-		WARN_ON(ata_qc_from_tag(ap, ap->link.active_tag) == NULL);
-		ap->ops->eng_timeout(ap);
-	}
+	spin_unlock_irqrestore(ap->lock, flags);
+	ata_eh_release(ap);
 
 	scsi_eh_flush_done_q(&ap->eh_done_q);
 
 	/* clean up */
 	spin_lock_irqsave(ap->lock, flags);
 
+	ap->pflags &= ~ATA_PFLAG_RESUMING;
+
 	if (ap->pflags & ATA_PFLAG_LOADING)
 		ap->pflags &= ~ATA_PFLAG_LOADING;
 	else if ((ap->pflags & ATA_PFLAG_SCSI_HOTPLUG) &&
@@ -779,7 +823,7 @@ void ata_port_wait_eh(struct ata_port *ap)
  retry:
 	spin_lock_irqsave(ap->lock, flags);
 
-	while (ap->pflags & (ATA_PFLAG_EH_PENDING | ATA_PFLAG_EH_IN_PROGRESS)) {
+	while (ata_port_eh_scheduled(ap)) {
 		prepare_to_wait(&ap->eh_wait_q, &wait, TASK_UNINTERRUPTIBLE);
 		spin_unlock_irqrestore(ap->lock, flags);
 		schedule();
@@ -797,11 +841,11 @@ void ata_port_wait_eh(struct ata_port *ap)
 }
 EXPORT_SYMBOL_GPL(ata_port_wait_eh);
 
-static int ata_eh_nr_in_flight(struct ata_port *ap)
+static unsigned int ata_eh_nr_in_flight(struct ata_port *ap)
 {
 	struct ata_queued_cmd *qc;
 	unsigned int tag;
-	int nr = 0;
+	unsigned int nr = 0;
 
 	/* count only non-internal commands */
 	ata_qc_for_each(ap, qc, tag) {
@@ -814,9 +858,9 @@ static int ata_eh_nr_in_flight(struct ata_port *ap)
 
 void ata_eh_fastdrain_timerfn(struct timer_list *t)
 {
-	struct ata_port *ap = from_timer(ap, t, fastdrain_timer);
+	struct ata_port *ap = timer_container_of(ap, t, fastdrain_timer);
 	unsigned long flags;
-	int cnt;
+	unsigned int cnt;
 
 	spin_lock_irqsave(ap->lock, flags);
 
@@ -863,9 +907,9 @@ void ata_eh_fastdrain_timerfn(struct timer_list *t)
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  */
-static void ata_eh_set_pending(struct ata_port *ap, int fastdrain)
+static void ata_eh_set_pending(struct ata_port *ap, bool fastdrain)
 {
-	int cnt;
+	unsigned int cnt;
 
 	/* already scheduled? */
 	if (ap->pflags & ATA_PFLAG_EH_PENDING)
@@ -902,17 +946,15 @@ void ata_qc_schedule_eh(struct ata_queued_cmd *qc)
 {
 	struct ata_port *ap = qc->ap;
 
-	WARN_ON(!ap->ops->error_handler);
-
-	qc->flags |= ATA_QCFLAG_FAILED;
-	ata_eh_set_pending(ap, 1);
+	qc->flags |= ATA_QCFLAG_EH;
+	ata_eh_set_pending(ap, true);
 
 	/* The following will fail if timeout has already expired.
 	 * ata_scsi_error() takes care of such scmds on EH entry.
-	 * Note that ATA_QCFLAG_FAILED is unconditionally set after
+	 * Note that ATA_QCFLAG_EH is unconditionally set after
 	 * this function completes.
 	 */
-	blk_abort_request(qc->scsicmd->request);
+	blk_abort_request(scsi_cmd_to_rq(qc->scsicmd));
 }
 
 /**
@@ -924,15 +966,13 @@ void ata_qc_schedule_eh(struct ata_queued_cmd *qc)
  */
 void ata_std_sched_eh(struct ata_port *ap)
 {
-	WARN_ON(!ap->ops->error_handler);
-
 	if (ap->pflags & ATA_PFLAG_INITIALIZING)
 		return;
 
-	ata_eh_set_pending(ap, 1);
+	ata_eh_set_pending(ap, true);
 	scsi_schedule_eh(ap->scsi_host);
 
-	DPRINTK("port EH scheduled\n");
+	trace_ata_std_sched_eh(ap);
 }
 EXPORT_SYMBOL_GPL(ata_std_sched_eh);
 
@@ -979,15 +1019,13 @@ static int ata_do_link_abort(struct ata_port *ap, struct ata_link *link)
 	struct ata_queued_cmd *qc;
 	int tag, nr_aborted = 0;
 
-	WARN_ON(!ap->ops->error_handler);
-
 	/* we're gonna abort all commands, no need for fast drain */
-	ata_eh_set_pending(ap, 0);
+	ata_eh_set_pending(ap, false);
 
 	/* include internal tag in iteration */
 	ata_qc_for_each_with_internal(ap, qc, tag) {
 		if (qc && (!link || qc->dev->link == link)) {
-			qc->flags |= ATA_QCFLAG_FAILED;
+			qc->flags |= ATA_QCFLAG_EH;
 			ata_qc_complete(qc);
 			nr_aborted++;
 		}
@@ -1055,14 +1093,12 @@ EXPORT_SYMBOL_GPL(ata_port_abort);
  */
 static void __ata_port_freeze(struct ata_port *ap)
 {
-	WARN_ON(!ap->ops->error_handler);
-
 	if (ap->ops->freeze)
 		ap->ops->freeze(ap);
 
 	ap->pflags |= ATA_PFLAG_FROZEN;
 
-	DPRINTK("ata%u port frozen\n", ap->print_id);
+	trace_ata_port_freeze(ap);
 }
 
 /**
@@ -1081,14 +1117,9 @@ static void __ata_port_freeze(struct ata_port *ap)
  */
 int ata_port_freeze(struct ata_port *ap)
 {
-	int nr_aborted;
-
-	WARN_ON(!ap->ops->error_handler);
-
 	__ata_port_freeze(ap);
-	nr_aborted = ata_port_abort(ap);
 
-	return nr_aborted;
+	return ata_port_abort(ap);
 }
 EXPORT_SYMBOL_GPL(ata_port_freeze);
 
@@ -1105,9 +1136,6 @@ void ata_eh_freeze_port(struct ata_port *ap)
 {
 	unsigned long flags;
 
-	if (!ap->ops->error_handler)
-		return;
-
 	spin_lock_irqsave(ap->lock, flags);
 	__ata_port_freeze(ap);
 	spin_unlock_irqrestore(ap->lock, flags);
@@ -1115,7 +1143,7 @@ void ata_eh_freeze_port(struct ata_port *ap)
 EXPORT_SYMBOL_GPL(ata_eh_freeze_port);
 
 /**
- *	ata_port_thaw_port - EH helper to thaw port
+ *	ata_eh_thaw_port - EH helper to thaw port
  *	@ap: ATA port to thaw
  *
  *	Thaw frozen port @ap.
@@ -1127,9 +1155,6 @@ void ata_eh_thaw_port(struct ata_port *ap)
 {
 	unsigned long flags;
 
-	if (!ap->ops->error_handler)
-		return;
-
 	spin_lock_irqsave(ap->lock, flags);
 
 	ap->pflags &= ~ATA_PFLAG_FROZEN;
@@ -1139,7 +1164,7 @@ void ata_eh_thaw_port(struct ata_port *ap)
 
 	spin_unlock_irqrestore(ap->lock, flags);
 
-	DPRINTK("ata%u port thawed\n", ap->print_id);
+	trace_ata_port_thaw(ap);
 }
 
 static void ata_eh_scsidone(struct scsi_cmnd *scmd)
@@ -1209,16 +1234,9 @@ void ata_dev_disable(struct ata_device *dev)
 	if (!ata_dev_enabled(dev))
 		return;
 
-	if (ata_msg_drv(dev->link->ap))
-		ata_dev_warn(dev, "disabled\n");
-	ata_acpi_on_disable(dev);
-	ata_down_xfermask_limit(dev, ATA_DNXFER_FORCE_PIO0 | ATA_DNXFER_QUIET);
-	dev->class++;
+	ata_dev_warn(dev, "disable device\n");
 
-	/* From now till the next successful probe, ering is used to
-	 * track probe failures.  Clear accumulated device error info.
-	 */
-	ata_ering_clear(&dev->ering);
+	ata_eh_dev_disable(dev);
 }
 EXPORT_SYMBOL_GPL(ata_dev_disable);
 
@@ -1238,7 +1256,14 @@ void ata_eh_detach_dev(struct ata_device *dev)
 	struct ata_eh_context *ehc = &link->eh_context;
 	unsigned long flags;
 
-	ata_dev_disable(dev);
+	/*
+	 * If the device is still enabled, transition it to standby power mode
+	 * (i.e. spin down HDDs) and disable it.
+	 */
+	if (ata_dev_enabled(dev)) {
+		ata_dev_power_set_standby(dev);
+		ata_eh_dev_disable(dev);
+	}
 
 	spin_lock_irqsave(ap->lock, flags);
 
@@ -1279,6 +1304,8 @@ void ata_eh_about_to_do(struct ata_link *link, struct ata_device *dev,
 	struct ata_eh_context *ehc = &link->eh_context;
 	unsigned long flags;
 
+	trace_ata_eh_about_to_do(link, dev ? dev->devno : 0, action);
+
 	spin_lock_irqsave(ap->lock, flags);
 
 	ata_eh_clear_action(link, dev, ehi, action);
@@ -1309,6 +1336,8 @@ void ata_eh_done(struct ata_link *link, struct ata_device *dev,
 {
 	struct ata_eh_context *ehc = &link->eh_context;
 
+	trace_ata_eh_done(link, dev ? dev->devno : 0, action);
+
 	ata_eh_clear_action(link, dev, &ehc->i, action);
 }
 
@@ -1378,43 +1407,77 @@ unsigned int atapi_eh_tur(struct ata_device *dev, u8 *r_sense_key)
 
 	err_mask = ata_exec_internal(dev, &tf, cdb, DMA_NONE, NULL, 0, 0);
 	if (err_mask == AC_ERR_DEV)
-		*r_sense_key = tf.feature >> 4;
+		*r_sense_key = tf.error >> 4;
 	return err_mask;
 }
 
 /**
+ *	ata_eh_decide_disposition - Disposition a qc based on sense data
+ *	@qc: qc to examine
+ *
+ *	For a regular SCSI command, the SCSI completion callback (scsi_done())
+ *	will call scsi_complete(), which will call scsi_decide_disposition(),
+ *	which will call scsi_check_sense(). scsi_complete() finally calls
+ *	scsi_finish_command(). This is fine for SCSI, since any eventual sense
+ *	data is usually returned in the completion itself (without invoking SCSI
+ *	EH). However, for a QC, we always need to fetch the sense data
+ *	explicitly using SCSI EH.
+ *
+ *	A command that is completed via SCSI EH will instead be completed using
+ *	scsi_eh_flush_done_q(), which will call scsi_finish_command() directly
+ *	(without ever calling scsi_check_sense()).
+ *
+ *	For a command that went through SCSI EH, it is the responsibility of the
+ *	SCSI EH strategy handler to call scsi_decide_disposition(), see e.g. how
+ *	scsi_eh_get_sense() calls scsi_decide_disposition() for SCSI LLDDs that
+ *	do not get the sense data as part of the completion.
+ *
+ *	Thus, for QC commands that went via SCSI EH, we need to call
+ *	scsi_check_sense() ourselves, similar to how scsi_eh_get_sense() calls
+ *	scsi_decide_disposition(), which calls scsi_check_sense(), in order to
+ *	set the correct SCSI ML byte (if any).
+ *
+ *	LOCKING:
+ *	EH context.
+ *
+ *	RETURNS:
+ *	SUCCESS or FAILED or NEEDS_RETRY or ADD_TO_MLQUEUE
+ */
+enum scsi_disposition ata_eh_decide_disposition(struct ata_queued_cmd *qc)
+{
+	return scsi_check_sense(qc->scsicmd);
+}
+
+/**
  *	ata_eh_request_sense - perform REQUEST_SENSE_DATA_EXT
  *	@qc: qc to perform REQUEST_SENSE_SENSE_DATA_EXT to
- *	@cmd: scsi command for which the sense code should be set
  *
  *	Perform REQUEST_SENSE_DATA_EXT after the device reported CHECK
  *	SENSE.  This function is an EH helper.
  *
  *	LOCKING:
  *	Kernel thread context (may sleep).
+ *
+ *	RETURNS:
+ *	true if sense data could be fetched, false otherwise.
  */
-static void ata_eh_request_sense(struct ata_queued_cmd *qc,
-				 struct scsi_cmnd *cmd)
+static bool ata_eh_request_sense(struct ata_queued_cmd *qc)
 {
+	struct scsi_cmnd *cmd = qc->scsicmd;
 	struct ata_device *dev = qc->dev;
 	struct ata_taskfile tf;
 	unsigned int err_mask;
 
-	if (qc->ap->pflags & ATA_PFLAG_FROZEN) {
+	if (ata_port_is_frozen(qc->ap)) {
 		ata_dev_warn(dev, "sense data available but port frozen\n");
-		return;
+		return false;
 	}
 
-	if (!cmd || qc->flags & ATA_QCFLAG_SENSE_VALID)
-		return;
-
 	if (!ata_id_sense_reporting_enabled(dev->id)) {
 		ata_dev_warn(qc->dev, "sense data reporting disabled\n");
-		return;
+		return false;
 	}
 
-	DPRINTK("ATA request sense\n");
-
 	ata_tf_init(dev, &tf);
 	tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
 	tf.flags |= ATA_TFLAG_LBA | ATA_TFLAG_LBA48;
@@ -1423,13 +1486,21 @@ static void ata_eh_request_sense(struct ata_queued_cmd *qc,
 
 	err_mask = ata_exec_internal(dev, &tf, NULL, DMA_NONE, NULL, 0, 0);
 	/* Ignore err_mask; ATA_ERR might be set */
-	if (tf.command & ATA_SENSE) {
-		ata_scsi_set_sense(dev, cmd, tf.lbah, tf.lbam, tf.lbal);
-		qc->flags |= ATA_QCFLAG_SENSE_VALID;
+	if (tf.status & ATA_SENSE) {
+		if (ata_scsi_sense_is_valid(tf.lbah, tf.lbam, tf.lbal)) {
+			/* Set sense without also setting scsicmd->result */
+			scsi_build_sense_buffer(dev->flags & ATA_DFLAG_D_SENSE,
+						cmd->sense_buffer, tf.lbah,
+						tf.lbam, tf.lbal);
+			qc->flags |= ATA_QCFLAG_SENSE_VALID;
+			return true;
+		}
 	} else {
 		ata_dev_warn(dev, "request sense failed stat %02x emask %x\n",
-			     tf.command, err_mask);
+			     tf.status, err_mask);
 	}
+
+	return false;
 }
 
 /**
@@ -1455,8 +1526,6 @@ unsigned int atapi_eh_request_sense(struct ata_device *dev,
 	struct ata_port *ap = dev->link->ap;
 	struct ata_taskfile tf;
 
-	DPRINTK("ATAPI request sense\n");
-
 	memset(sense_buf, 0, SCSI_SENSE_BUFFERSIZE);
 
 	/* initialize sense_buf with the error register,
@@ -1471,8 +1540,15 @@ unsigned int atapi_eh_request_sense(struct ata_device *dev,
 	tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
 	tf.command = ATA_CMD_PACKET;
 
-	/* is it pointless to prefer PIO for "safety reasons"? */
-	if (ap->flags & ATA_FLAG_PIO_DMA) {
+	/*
+	 * Do not use DMA if the connected device only supports PIO, even if the
+	 * port prefers PIO commands via DMA.
+	 *
+	 * Ideally, we should call atapi_check_dma() to check if it is safe for
+	 * the LLD to use DMA for REQUEST_SENSE, but we don't have a qc.
+	 * Since we can't check the command, perhaps we should only use pio?
+	 */
+	if ((ap->flags & ATA_FLAG_PIO_DMA) && !(dev->flags & ATA_DFLAG_PIO)) {
 		tf.protocol = ATAPI_PROT_DMA;
 		tf.feature |= ATAPI_PKT_DMA;
 	} else {
@@ -1537,7 +1613,6 @@ static void ata_eh_analyze_serror(struct ata_link *link)
 /**
  *	ata_eh_analyze_tf - analyze taskfile of a failed qc
  *	@qc: qc to analyze
- *	@tf: Taskfile registers to analyze
  *
  *	Analyze taskfile of @qc and further determine cause of
  *	failure.  This function also requests ATAPI sense data if
@@ -1549,11 +1624,11 @@ static void ata_eh_analyze_serror(struct ata_link *link)
  *	RETURNS:
  *	Determined recovery action
  */
-static unsigned int ata_eh_analyze_tf(struct ata_queued_cmd *qc,
-				      const struct ata_taskfile *tf)
+static unsigned int ata_eh_analyze_tf(struct ata_queued_cmd *qc)
 {
+	const struct ata_taskfile *tf = &qc->result_tf;
 	unsigned int tmp, action = 0;
-	u8 stat = tf->command, err = tf->feature;
+	u8 stat = tf->status, err = tf->error;
 
 	if ((stat & (ATA_BUSY | ATA_DRQ | ATA_DRDY)) != ATA_DRDY) {
 		qc->err_mask |= AC_ERR_HSM;
@@ -1573,11 +1648,18 @@ static unsigned int ata_eh_analyze_tf(struct ata_queued_cmd *qc,
 	}
 
 	switch (qc->dev->class) {
-	case ATA_DEV_ZAC:
-		if (stat & ATA_SENSE)
-			ata_eh_request_sense(qc, qc->scsicmd);
-		/* fall through */
 	case ATA_DEV_ATA:
+	case ATA_DEV_ZAC:
+		/*
+		 * Fetch the sense data explicitly if:
+		 * -It was a non-NCQ command that failed, or
+		 * -It was a NCQ command that failed, but the sense data
+		 *  was not included in the NCQ command error log
+		 *  (i.e. NCQ autosense is not supported by the device).
+		 */
+		if (!(qc->flags & ATA_QCFLAG_SENSE_VALID) &&
+		    (stat & ATA_SENSE) && ata_eh_request_sense(qc))
+			set_status_byte(qc->scsicmd, SAM_STAT_CHECK_CONDITION);
 		if (err & ATA_ICRC)
 			qc->err_mask |= AC_ERR_ATA_BUS;
 		if (err & (ATA_UNC | ATA_AMNF))
@@ -1587,10 +1669,10 @@ static unsigned int ata_eh_analyze_tf(struct ata_queued_cmd *qc,
 		break;
 
 	case ATA_DEV_ATAPI:
-		if (!(qc->ap->pflags & ATA_PFLAG_FROZEN)) {
+		if (!ata_port_is_frozen(qc->ap)) {
 			tmp = atapi_eh_request_sense(qc->dev,
 						qc->scsicmd->sense_buffer,
-						qc->result_tf.feature >> 4);
+						qc->result_tf.error >> 4);
 			if (!tmp)
 				qc->flags |= ATA_QCFLAG_SENSE_VALID;
 			else
@@ -1599,7 +1681,8 @@ static unsigned int ata_eh_analyze_tf(struct ata_queued_cmd *qc,
 	}
 
 	if (qc->flags & ATA_QCFLAG_SENSE_VALID) {
-		int ret = scsi_check_sense(qc->scsicmd);
+		enum scsi_disposition ret = ata_eh_decide_disposition(qc);
+
 		/*
 		 * SUCCESS here means that the sense code could be
 		 * evaluated and should be passed to the upper layers
@@ -1805,9 +1888,7 @@ static unsigned int ata_eh_speed_down(struct ata_device *dev,
 	verdict = ata_eh_speed_down_verdict(dev);
 
 	/* turn off NCQ? */
-	if ((verdict & ATA_EH_SPDN_NCQ_OFF) &&
-	    (dev->flags & (ATA_DFLAG_PIO | ATA_DFLAG_NCQ |
-			   ATA_DFLAG_NCQ_OFF)) == ATA_DFLAG_NCQ) {
+	if ((verdict & ATA_EH_SPDN_NCQ_OFF) && ata_ncq_enabled(dev)) {
 		dev->flags |= ATA_DFLAG_NCQ_OFF;
 		ata_dev_warn(dev, "NCQ disabled due to excessive errors\n");
 		goto done;
@@ -1893,12 +1974,285 @@ static inline int ata_eh_worth_retry(struct ata_queued_cmd *qc)
  */
 static inline bool ata_eh_quiet(struct ata_queued_cmd *qc)
 {
-	if (qc->scsicmd &&
-	    qc->scsicmd->request->rq_flags & RQF_QUIET)
+	if (qc->scsicmd && scsi_cmd_to_rq(qc->scsicmd)->rq_flags & RQF_QUIET)
 		qc->flags |= ATA_QCFLAG_QUIET;
 	return qc->flags & ATA_QCFLAG_QUIET;
 }
 
+static int ata_eh_get_non_ncq_success_sense(struct ata_link *link)
+{
+	struct ata_port *ap = link->ap;
+	struct ata_queued_cmd *qc;
+
+	qc = __ata_qc_from_tag(ap, link->active_tag);
+	if (!qc)
+		return -EIO;
+
+	if (!(qc->flags & ATA_QCFLAG_EH) ||
+	    !(qc->flags & ATA_QCFLAG_EH_SUCCESS_CMD) ||
+	    qc->err_mask)
+		return -EIO;
+
+	if (!ata_eh_request_sense(qc))
+		return -EIO;
+
+	/*
+	 * No point in checking the return value, since the command has already
+	 * completed successfully.
+	 */
+	ata_eh_decide_disposition(qc);
+
+	return 0;
+}
+
+static void ata_eh_get_success_sense(struct ata_link *link)
+{
+	struct ata_eh_context *ehc = &link->eh_context;
+	struct ata_device *dev = link->device;
+	struct ata_port *ap = link->ap;
+	struct ata_queued_cmd *qc;
+	int tag, ret = 0;
+
+	if (!(ehc->i.dev_action[dev->devno] & ATA_EH_GET_SUCCESS_SENSE))
+		return;
+
+	/* if frozen, we can't do much */
+	if (ata_port_is_frozen(ap)) {
+		ata_dev_warn(dev,
+			"successful sense data available but port frozen\n");
+		goto out;
+	}
+
+	/*
+	 * If the link has sactive set, then we have outstanding NCQ commands
+	 * and have to read the Successful NCQ Commands log to get the sense
+	 * data. Otherwise, we are dealing with a non-NCQ command and use
+	 * request sense ext command to retrieve the sense data.
+	 */
+	if (link->sactive)
+		ret = ata_eh_get_ncq_success_sense(link);
+	else
+		ret = ata_eh_get_non_ncq_success_sense(link);
+	if (ret)
+		goto out;
+
+	ata_eh_done(link, dev, ATA_EH_GET_SUCCESS_SENSE);
+	return;
+
+out:
+	/*
+	 * If we failed to get sense data for a successful command that ought to
+	 * have sense data, we cannot simply return BLK_STS_OK to user space.
+	 * This is because we can't know if the sense data that we couldn't get
+	 * was actually "DATA CURRENTLY UNAVAILABLE". Reporting such a command
+	 * as success to user space would result in a silent data corruption.
+	 * Thus, add a bogus ABORTED_COMMAND sense data to such commands, such
+	 * that SCSI will report these commands as BLK_STS_IOERR to user space.
+	 */
+	ata_qc_for_each_raw(ap, qc, tag) {
+		if (!(qc->flags & ATA_QCFLAG_EH) ||
+		    !(qc->flags & ATA_QCFLAG_EH_SUCCESS_CMD) ||
+		    qc->err_mask ||
+		    ata_dev_phys_link(qc->dev) != link)
+			continue;
+
+		/* We managed to get sense for this success command, skip. */
+		if (qc->flags & ATA_QCFLAG_SENSE_VALID)
+			continue;
+
+		/* This success command did not have any sense data, skip. */
+		if (!(qc->result_tf.status & ATA_SENSE))
+			continue;
+
+		/* This success command had sense data, but we failed to get. */
+		ata_scsi_set_sense(dev, qc->scsicmd, ABORTED_COMMAND, 0, 0);
+		qc->flags |= ATA_QCFLAG_SENSE_VALID;
+	}
+	ata_eh_done(link, dev, ATA_EH_GET_SUCCESS_SENSE);
+}
+
+/*
+ * Check if a link is established. This is a relaxed version of
+ * ata_phys_link_online() which accounts for the fact that this is potentially
+ * called after changing the link power management policy, which may not be
+ * reflected immediately in the SStatus register (e.g., we may still be seeing
+ * the PHY in partial, slumber or devsleep Partial power management state.
+ * So check that:
+ * - A device is still present, that is, DET is 1h (Device presence detected
+ *   but Phy communication not established) or 3h (Device presence detected and
+ *   Phy communication established)
+ * - Communication is established, that is, IPM is not 0h, indicating that PHY
+ *   is online or in a low power state.
+ */
+static bool ata_eh_link_established(struct ata_link *link)
+{
+	u32 sstatus;
+	u8 det, ipm;
+
+	/*
+	 * For old IDE/PATA adapters that do not have a valid scr_read method,
+	 * or if reading the SStatus register fails, assume that the device is
+	 * present. Device probe will determine if that is really the case.
+	 */
+	if (sata_scr_read(link, SCR_STATUS, &sstatus))
+		return true;
+
+	det = sstatus & 0x0f;
+	ipm = (sstatus >> 8) & 0x0f;
+
+	return (det & 0x01) && ipm;
+}
+
+/**
+ *	ata_eh_link_set_lpm - configure SATA interface power management
+ *	@link: link to configure
+ *	@policy: the link power management policy
+ *	@r_failed_dev: out parameter for failed device
+ *
+ *	Enable SATA Interface power management.  This will enable
+ *	Device Interface Power Management (DIPM) for min_power and
+ *	medium_power_with_dipm policies, and then call driver specific
+ *	callbacks for enabling Host Initiated Power management.
+ *
+ *	LOCKING:
+ *	EH context.
+ *
+ *	RETURNS:
+ *	0 on success, -errno on failure.
+ */
+static int ata_eh_link_set_lpm(struct ata_link *link,
+			       enum ata_lpm_policy policy,
+			       struct ata_device **r_failed_dev)
+{
+	struct ata_port *ap = ata_is_host_link(link) ? link->ap : NULL;
+	struct ata_eh_context *ehc = &link->eh_context;
+	struct ata_device *dev, *link_dev = NULL, *lpm_dev = NULL;
+	enum ata_lpm_policy old_policy = link->lpm_policy;
+	bool host_has_dipm = !(link->ap->flags & ATA_FLAG_NO_DIPM);
+	unsigned int hints = ATA_LPM_EMPTY | ATA_LPM_HIPM;
+	unsigned int err_mask;
+	int rc;
+
+	/* if the link or host doesn't do LPM, noop */
+	if (!IS_ENABLED(CONFIG_SATA_HOST) ||
+	    (link->flags & ATA_LFLAG_NO_LPM) || (ap && !ap->ops->set_lpm))
+		return 0;
+
+	/*
+	 * This function currently assumes that it will never be supplied policy
+	 * ATA_LPM_UNKNOWN.
+	 */
+	if (WARN_ON_ONCE(policy == ATA_LPM_UNKNOWN))
+		return 0;
+
+	ata_link_dbg(link, "Set LPM policy: %d -> %d\n", old_policy, policy);
+
+	/*
+	 * DIPM is enabled only for ATA_LPM_MIN_POWER,
+	 * ATA_LPM_MIN_POWER_WITH_PARTIAL, and ATA_LPM_MED_POWER_WITH_DIPM, as
+	 * some devices misbehave when the host NACKs transition to SLUMBER.
+	 */
+	ata_for_each_dev(dev, link, ENABLED) {
+		bool dev_has_hipm = ata_id_has_hipm(dev->id);
+		bool dev_has_dipm = ata_id_has_dipm(dev->id);
+
+		/* find the first enabled and LPM enabled devices */
+		if (!link_dev)
+			link_dev = dev;
+
+		if (!lpm_dev &&
+		    (dev_has_hipm || (dev_has_dipm && host_has_dipm)))
+			lpm_dev = dev;
+
+		hints &= ~ATA_LPM_EMPTY;
+		if (!dev_has_hipm)
+			hints &= ~ATA_LPM_HIPM;
+
+		/* disable DIPM before changing link config */
+		if (dev_has_dipm) {
+			err_mask = ata_dev_set_feature(dev,
+					SETFEATURES_SATA_DISABLE, SATA_DIPM);
+			if (err_mask && err_mask != AC_ERR_DEV) {
+				ata_dev_warn(dev,
+					     "failed to disable DIPM, Emask 0x%x\n",
+					     err_mask);
+				rc = -EIO;
+				goto fail;
+			}
+		}
+	}
+
+	if (ap) {
+		rc = ap->ops->set_lpm(link, policy, hints);
+		if (!rc && ap->slave_link)
+			rc = ap->ops->set_lpm(ap->slave_link, policy, hints);
+	} else
+		rc = sata_pmp_set_lpm(link, policy, hints);
+
+	/*
+	 * Attribute link config failure to the first (LPM) enabled
+	 * device on the link.
+	 */
+	if (rc) {
+		if (rc == -EOPNOTSUPP) {
+			link->flags |= ATA_LFLAG_NO_LPM;
+			return 0;
+		}
+		dev = lpm_dev ? lpm_dev : link_dev;
+		goto fail;
+	}
+
+	/*
+	 * Low level driver acked the transition.  Issue DIPM command
+	 * with the new policy set.
+	 */
+	link->lpm_policy = policy;
+	if (ap && ap->slave_link)
+		ap->slave_link->lpm_policy = policy;
+
+	/*
+	 * Host config updated, enable DIPM if transitioning to
+	 * ATA_LPM_MIN_POWER, ATA_LPM_MIN_POWER_WITH_PARTIAL, or
+	 * ATA_LPM_MED_POWER_WITH_DIPM.
+	 */
+	ata_for_each_dev(dev, link, ENABLED) {
+		bool dev_has_dipm = ata_id_has_dipm(dev->id);
+
+		if (policy >= ATA_LPM_MED_POWER_WITH_DIPM && host_has_dipm &&
+		    dev_has_dipm) {
+			err_mask = ata_dev_set_feature(dev,
+					SETFEATURES_SATA_ENABLE, SATA_DIPM);
+			if (err_mask && err_mask != AC_ERR_DEV) {
+				ata_dev_warn(dev,
+					"failed to enable DIPM, Emask 0x%x\n",
+					err_mask);
+				rc = -EIO;
+				goto fail;
+			}
+		}
+	}
+
+	link->last_lpm_change = jiffies;
+	link->flags |= ATA_LFLAG_CHANGED;
+
+	return 0;
+
+fail:
+	/* restore the old policy */
+	link->lpm_policy = old_policy;
+	if (ap && ap->slave_link)
+		ap->slave_link->lpm_policy = old_policy;
+
+	/* if no device or only one more chance is left, disable LPM */
+	if (!dev || ehc->tries[dev->devno] <= 2) {
+		ata_link_warn(link, "disabling LPM on the link\n");
+		link->flags |= ATA_LFLAG_NO_LPM;
+	}
+	if (r_failed_dev)
+		*r_failed_dev = dev;
+	return rc;
+}
+
 /**
  *	ata_eh_link_autopsy - analyze error and determine recovery action
  *	@link: host link to perform autopsy on
@@ -1921,8 +2275,6 @@ static void ata_eh_link_autopsy(struct ata_link *link)
 	u32 serror;
 	int rc;
 
-	DPRINTK("ENTER\n");
-
 	if (ehc->i.flags & ATA_EHI_NO_AUTOPSY)
 		return;
 
@@ -1941,6 +2293,14 @@ static void ata_eh_link_autopsy(struct ata_link *link)
 	/* analyze NCQ failure */
 	ata_eh_analyze_ncq_error(link);
 
+	/*
+	 * Check if this was a successful command that simply needs sense data.
+	 * Since the sense data is not part of the completion, we need to fetch
+	 * it using an additional command. Since this can't be done from irq
+	 * context, the sense data for successful commands are fetched by EH.
+	 */
+	ata_eh_get_success_sense(link);
+
 	/* any real error trumps AC_ERR_OTHER */
 	if (ehc->i.err_mask & ~AC_ERR_OTHER)
 		ehc->i.err_mask &= ~AC_ERR_OTHER;
@@ -1948,7 +2308,9 @@ static void ata_eh_link_autopsy(struct ata_link *link)
 	all_err_mask |= ehc->i.err_mask;
 
 	ata_qc_for_each_raw(ap, qc, tag) {
-		if (!(qc->flags & ATA_QCFLAG_FAILED) ||
+		if (!(qc->flags & ATA_QCFLAG_EH) ||
+		    qc->flags & ATA_QCFLAG_RETRY ||
+		    qc->flags & ATA_QCFLAG_EH_SUCCESS_CMD ||
 		    ata_dev_phys_link(qc->dev) != link)
 			continue;
 
@@ -1956,7 +2318,7 @@ static void ata_eh_link_autopsy(struct ata_link *link)
 		qc->err_mask |= ehc->i.err_mask;
 
 		/* analyze TF */
-		ehc->i.action |= ata_eh_analyze_tf(qc, &qc->result_tf);
+		ehc->i.action |= ata_eh_analyze_tf(qc);
 
 		/* DEV errors are probably spurious in case of ATA_BUS error */
 		if (qc->err_mask & AC_ERR_ATA_BUS)
@@ -1997,7 +2359,7 @@ static void ata_eh_link_autopsy(struct ata_link *link)
 		ehc->i.flags |= ATA_EHI_QUIET;
 
 	/* enforce default EH actions */
-	if (ap->pflags & ATA_PFLAG_FROZEN ||
+	if (ata_port_is_frozen(ap) ||
 	    all_err_mask & (AC_ERR_HSM | AC_ERR_TIMEOUT))
 		ehc->i.action |= ATA_EH_RESET;
 	else if (((eflags & ATA_EFLAG_IS_IO) && all_err_mask) ||
@@ -2029,7 +2391,6 @@ static void ata_eh_link_autopsy(struct ata_link *link)
 		ehc->i.action |= ata_eh_speed_down(dev, eflags, all_err_mask);
 		trace_ata_eh_link_autopsy(dev, ehc->i.action, all_err_mask);
 	}
-	DPRINTK("EXIT\n");
 }
 
 /**
@@ -2079,16 +2440,15 @@ void ata_eh_autopsy(struct ata_port *ap)
 }
 
 /**
- *	ata_get_cmd_descript - get description for ATA command
- *	@command: ATA command code to get description for
+ *	ata_get_cmd_name - get name for ATA command
+ *	@command: ATA command code to get name for
  *
- *	Return a textual description of the given command, or NULL if the
- *	command is not known.
+ *	Return a textual name of the given command or "unknown"
  *
  *	LOCKING:
  *	None
  */
-const char *ata_get_cmd_descript(u8 command)
+const char *ata_get_cmd_name(u8 command)
 {
 #ifdef CONFIG_ATA_VERBOSE_ERROR
 	static const struct
@@ -2123,6 +2483,7 @@ const char *ata_get_cmd_descript(u8 command)
 		{ ATA_CMD_WRITE_QUEUED_FUA_EXT, "WRITE DMA QUEUED FUA EXT" },
 		{ ATA_CMD_FPDMA_READ,		"READ FPDMA QUEUED" },
 		{ ATA_CMD_FPDMA_WRITE,		"WRITE FPDMA QUEUED" },
+		{ ATA_CMD_NCQ_NON_DATA,		"NCQ NON-DATA" },
 		{ ATA_CMD_FPDMA_SEND,		"SEND FPDMA QUEUED" },
 		{ ATA_CMD_FPDMA_RECV,		"RECEIVE FPDMA QUEUED" },
 		{ ATA_CMD_PIO_READ,		"READ SECTOR(S)" },
@@ -2196,9 +2557,9 @@ const char *ata_get_cmd_descript(u8 command)
 			return cmd_descr[i].text;
 #endif
 
-	return NULL;
+	return "unknown";
 }
-EXPORT_SYMBOL_GPL(ata_get_cmd_descript);
+EXPORT_SYMBOL_GPL(ata_get_cmd_name);
 
 /**
  *	ata_eh_link_report - report error handling to user
@@ -2215,7 +2576,7 @@ static void ata_eh_link_report(struct ata_link *link)
 	struct ata_eh_context *ehc = &link->eh_context;
 	struct ata_queued_cmd *qc;
 	const char *frozen, *desc;
-	char tries_buf[6] = "";
+	char tries_buf[16] = "";
 	int tag, nr_failed = 0;
 
 	if (ehc->i.flags & ATA_EHI_QUIET)
@@ -2226,7 +2587,7 @@ static void ata_eh_link_report(struct ata_link *link)
 		desc = ehc->i.desc;
 
 	ata_qc_for_each_raw(ap, qc, tag) {
-		if (!(qc->flags & ATA_QCFLAG_FAILED) ||
+		if (!(qc->flags & ATA_QCFLAG_EH) ||
 		    ata_dev_phys_link(qc->dev) != link ||
 		    ((qc->flags & ATA_QCFLAG_QUIET) &&
 		     qc->err_mask == AC_ERR_DEV))
@@ -2241,7 +2602,7 @@ static void ata_eh_link_report(struct ata_link *link)
 		return;
 
 	frozen = "";
-	if (ap->pflags & ATA_PFLAG_FROZEN)
+	if (ata_port_is_frozen(ap))
 		frozen = " frozen";
 
 	if (ap->eh_tries < ATA_EH_MAX_TRIES)
@@ -2292,7 +2653,7 @@ static void ata_eh_link_report(struct ata_link *link)
 		char data_buf[20] = "";
 		char cdb_buf[70] = "";
 
-		if (!(qc->flags & ATA_QCFLAG_FAILED) ||
+		if (!(qc->flags & ATA_QCFLAG_EH) ||
 		    ata_dev_phys_link(qc->dev) != link || !qc->err_mask)
 			continue;
 
@@ -2347,12 +2708,9 @@ static void ata_eh_link_report(struct ata_link *link)
 			}
 			__scsi_format_command(cdb_buf, sizeof(cdb_buf),
 					      cdb, cdb_len);
-		} else {
-			const char *descr = ata_get_cmd_descript(cmd->command);
-			if (descr)
-				ata_dev_err(qc->dev, "failed command: %s\n",
-					    descr);
-		}
+		} else
+			ata_dev_err(qc->dev, "failed command: %s\n",
+				    ata_get_cmd_name(cmd->command));
 
 		ata_dev_err(qc->dev,
 			"cmd %02x/%02x:%02x:%02x:%02x:%02x/%02x:%02x:%02x:%02x:%02x/%02x "
@@ -2364,7 +2722,7 @@ static void ata_eh_link_report(struct ata_link *link)
 			cmd->hob_feature, cmd->hob_nsect,
 			cmd->hob_lbal, cmd->hob_lbam, cmd->hob_lbah,
 			cmd->device, qc->tag, data_buf, cdb_buf,
-			res->command, res->feature, res->nsect,
+			res->status, res->error, res->nsect,
 			res->lbal, res->lbam, res->lbah,
 			res->hob_feature, res->hob_nsect,
 			res->hob_lbal, res->hob_lbam, res->hob_lbah,
@@ -2372,28 +2730,28 @@ static void ata_eh_link_report(struct ata_link *link)
 			qc->err_mask & AC_ERR_NCQ ? " <F>" : "");
 
 #ifdef CONFIG_ATA_VERBOSE_ERROR
-		if (res->command & (ATA_BUSY | ATA_DRDY | ATA_DF | ATA_DRQ |
-				    ATA_SENSE | ATA_ERR)) {
-			if (res->command & ATA_BUSY)
+		if (res->status & (ATA_BUSY | ATA_DRDY | ATA_DF | ATA_DRQ |
+				   ATA_SENSE | ATA_ERR)) {
+			if (res->status & ATA_BUSY)
 				ata_dev_err(qc->dev, "status: { Busy }\n");
 			else
 				ata_dev_err(qc->dev, "status: { %s%s%s%s%s}\n",
-				  res->command & ATA_DRDY ? "DRDY " : "",
-				  res->command & ATA_DF ? "DF " : "",
-				  res->command & ATA_DRQ ? "DRQ " : "",
-				  res->command & ATA_SENSE ? "SENSE " : "",
-				  res->command & ATA_ERR ? "ERR " : "");
+				  res->status & ATA_DRDY ? "DRDY " : "",
+				  res->status & ATA_DF ? "DF " : "",
+				  res->status & ATA_DRQ ? "DRQ " : "",
+				  res->status & ATA_SENSE ? "SENSE " : "",
+				  res->status & ATA_ERR ? "ERR " : "");
 		}
 
 		if (cmd->command != ATA_CMD_PACKET &&
-		    (res->feature & (ATA_ICRC | ATA_UNC | ATA_AMNF |
-				     ATA_IDNF | ATA_ABORTED)))
+		    (res->error & (ATA_ICRC | ATA_UNC | ATA_AMNF | ATA_IDNF |
+				   ATA_ABORTED)))
 			ata_dev_err(qc->dev, "error: { %s%s%s%s%s}\n",
-			  res->feature & ATA_ICRC ? "ICRC " : "",
-			  res->feature & ATA_UNC ? "UNC " : "",
-			  res->feature & ATA_AMNF ? "AMNF " : "",
-			  res->feature & ATA_IDNF ? "IDNF " : "",
-			  res->feature & ATA_ABORTED ? "ABRT " : "");
+				    res->error & ATA_ICRC ? "ICRC " : "",
+				    res->error & ATA_UNC ? "UNC " : "",
+				    res->error & ATA_AMNF ? "AMNF " : "",
+				    res->error & ATA_IDNF ? "IDNF " : "",
+				    res->error & ATA_ABORTED ? "ABRT " : "");
 #endif
 	}
 }
@@ -2428,25 +2786,28 @@ static int ata_do_reset(struct ata_link *link, ata_reset_fn_t reset,
 	return reset(link, classes, deadline);
 }
 
-static int ata_eh_followup_srst_needed(struct ata_link *link, int rc)
+static bool ata_eh_followup_srst_needed(struct ata_link *link, int rc)
 {
 	if ((link->flags & ATA_LFLAG_NO_SRST) || ata_link_offline(link))
-		return 0;
+		return false;
 	if (rc == -EAGAIN)
-		return 1;
+		return true;
 	if (sata_pmp_supported(link->ap) && ata_is_host_link(link))
-		return 1;
-	return 0;
+		return true;
+	return false;
 }
 
 int ata_eh_reset(struct ata_link *link, int classify,
-		 ata_prereset_fn_t prereset, ata_reset_fn_t softreset,
-		 ata_reset_fn_t hardreset, ata_postreset_fn_t postreset)
+		 struct ata_reset_operations *reset_ops)
 {
 	struct ata_port *ap = link->ap;
 	struct ata_link *slave = ap->slave_link;
 	struct ata_eh_context *ehc = &link->eh_context;
 	struct ata_eh_context *sehc = slave ? &slave->eh_context : NULL;
+	ata_reset_fn_t hardreset = reset_ops->hardreset;
+	ata_reset_fn_t softreset = reset_ops->softreset;
+	ata_prereset_fn_t prereset = reset_ops->prereset;
+	ata_postreset_fn_t postreset = reset_ops->postreset;
 	unsigned int *classes = ehc->classes;
 	unsigned int lflags = link->flags;
 	int verbose = !(ehc->i.flags & ATA_EHI_QUIET);
@@ -2462,7 +2823,7 @@ int ata_eh_reset(struct ata_link *link, int classify,
 	/*
 	 * Prepare to reset
 	 */
-	while (ata_eh_reset_timeouts[max_tries] != ULONG_MAX)
+	while (ata_eh_reset_timeouts[max_tries] != UINT_MAX)
 		max_tries++;
 	if (link->flags & ATA_LFLAG_RST_ONCE)
 		max_tries = 1;
@@ -2565,8 +2926,7 @@ int ata_eh_reset(struct ata_link *link, int classify,
 		if (reset && !(ehc->i.action & ATA_EH_RESET)) {
 			ata_for_each_dev(dev, link, ALL)
 				classes[dev->devno] = ATA_DEV_NONE;
-			if ((ap->pflags & ATA_PFLAG_FROZEN) &&
-			    ata_is_host_link(link))
+			if (ata_port_is_frozen(ap) && ata_is_host_link(link))
 				ata_eh_thaw_port(ap);
 			rc = 0;
 			goto out;
@@ -2589,12 +2949,19 @@ int ata_eh_reset(struct ata_link *link, int classify,
 
 		/* mark that this EH session started with reset */
 		ehc->last_reset = jiffies;
-		if (reset == hardreset)
+		if (reset == hardreset) {
 			ehc->i.flags |= ATA_EHI_DID_HARDRESET;
-		else
+			trace_ata_link_hardreset_begin(link, classes, deadline);
+		} else {
 			ehc->i.flags |= ATA_EHI_DID_SOFTRESET;
+			trace_ata_link_softreset_begin(link, classes, deadline);
+		}
 
 		rc = ata_do_reset(link, reset, classes, deadline, true);
+		if (reset == hardreset)
+			trace_ata_link_hardreset_end(link, classes, rc);
+		else
+			trace_ata_link_softreset_end(link, classes, rc);
 		if (rc && rc != -EAGAIN) {
 			failed_link = link;
 			goto fail;
@@ -2608,11 +2975,15 @@ int ata_eh_reset(struct ata_link *link, int classify,
 				ata_link_info(slave, "hard resetting link\n");
 
 			ata_eh_about_to_do(slave, NULL, ATA_EH_RESET);
+			trace_ata_slave_hardreset_begin(slave, classes,
+							deadline);
 			tmp = ata_do_reset(slave, reset, classes, deadline,
 					   false);
+			trace_ata_slave_hardreset_end(slave, classes, tmp);
 			switch (tmp) {
 			case -EAGAIN:
 				rc = -EAGAIN;
+				break;
 			case 0:
 				break;
 			default:
@@ -2636,7 +3007,9 @@ int ata_eh_reset(struct ata_link *link, int classify,
 			}
 
 			ata_eh_about_to_do(link, NULL, ATA_EH_RESET);
+			trace_ata_link_softreset_begin(link, classes, deadline);
 			rc = ata_do_reset(link, reset, classes, deadline, true);
+			trace_ata_link_softreset_end(link, classes, rc);
 			if (rc) {
 				failed_link = link;
 				goto fail;
@@ -2690,27 +3063,20 @@ int ata_eh_reset(struct ata_link *link, int classify,
 	 */
 	if (postreset) {
 		postreset(link, classes);
-		if (slave)
+		trace_ata_link_postreset(link, classes, rc);
+		if (slave) {
 			postreset(slave, classes);
+			trace_ata_slave_postreset(slave, classes, rc);
+		}
 	}
 
-	/*
-	 * Some controllers can't be frozen very well and may set spurious
-	 * error conditions during reset.  Clear accumulated error
-	 * information and re-thaw the port if frozen.  As reset is the
-	 * final recovery action and we cross check link onlineness against
-	 * device classification later, no hotplug event is lost by this.
-	 */
+	/* clear cached SError */
 	spin_lock_irqsave(link->ap->lock, flags);
-	memset(&link->eh_info, 0, sizeof(link->eh_info));
+	link->eh_info.serror = 0;
 	if (slave)
-		memset(&slave->eh_info, 0, sizeof(link->eh_info));
-	ap->pflags &= ~ATA_PFLAG_EH_PENDING;
+		slave->eh_info.serror = 0;
 	spin_unlock_irqrestore(link->ap->lock, flags);
 
-	if (ap->pflags & ATA_PFLAG_FROZEN)
-		ata_eh_thaw_port(ap);
-
 	/*
 	 * Make sure onlineness and classification result correspond.
 	 * Hotplug could have happened during reset and some
@@ -2790,6 +3156,8 @@ int ata_eh_reset(struct ata_link *link, int classify,
 		 */
 		if (ata_is_host_link(link))
 			ata_eh_thaw_port(ap);
+		ata_link_warn(link, "%s failed\n",
+			      reset == hardreset ? "hardreset" : "softreset");
 		goto out;
 	}
 
@@ -2913,8 +3281,6 @@ static int ata_eh_revalidate_and_attach(struct ata_link *link,
 	unsigned long flags;
 	int rc = 0;
 
-	DPRINTK("ENTER\n");
-
 	/* For PATA drive side cable detection to work, IDENTIFY must
 	 * be done backwards such that PDIAG- is released by the slave
 	 * device before the master device is identified.
@@ -2929,7 +3295,24 @@ static int ata_eh_revalidate_and_attach(struct ata_link *link,
 		if ((action & ATA_EH_REVALIDATE) && ata_dev_enabled(dev)) {
 			WARN_ON(dev->class == ATA_DEV_PMP);
 
-			if (ata_phys_link_offline(ata_dev_phys_link(dev))) {
+			/*
+			 * The link may be in a deep sleep, wake it up.
+			 *
+			 * If the link is in deep sleep, ata_phys_link_offline()
+			 * will return true, causing the revalidation to fail,
+			 * which leads to a (potentially) needless hard reset.
+			 *
+			 * ata_eh_recover() will later restore the link policy
+			 * to ap->target_lpm_policy after revalidation is done.
+			 */
+			if (link->lpm_policy > ATA_LPM_MAX_POWER) {
+				rc = ata_eh_link_set_lpm(link, ATA_LPM_MAX_POWER,
+							 r_failed_dev);
+				if (rc)
+					goto err;
+			}
+
+			if (!ata_eh_link_established(ata_dev_phys_link(dev))) {
 				rc = -EIO;
 				goto err;
 			}
@@ -2948,7 +3331,7 @@ static int ata_eh_revalidate_and_attach(struct ata_link *link,
 			ehc->i.flags |= ATA_EHI_SETMODE;
 
 			/* schedule the scsi_rescan_device() here */
-			schedule_work(&(ap->scsi_rescan_task));
+			schedule_delayed_work(&ap->scsi_rescan_task, 0);
 		} else if (dev->class == ATA_DEV_UNKNOWN &&
 			   ehc->tries[dev->devno] &&
 			   ata_class_enabled(ehc->classes[dev->devno])) {
@@ -3027,18 +3410,18 @@ static int ata_eh_revalidate_and_attach(struct ata_link *link,
 	return 0;
 
  err:
+	dev->flags &= ~ATA_DFLAG_RESUMING;
 	*r_failed_dev = dev;
-	DPRINTK("EXIT rc=%d\n", rc);
 	return rc;
 }
 
 /**
- *	ata_set_mode - Program timings and issue SET FEATURES - XFER
+ *	ata_eh_set_mode - Program timings and issue SET FEATURES - XFER
  *	@link: link on which timings will be programmed
  *	@r_failed_dev: out parameter for failed device
  *
  *	Set ATA device disk transfer mode (PIO3, UDMA6, etc.).  If
- *	ata_set_mode() fails, pointer to the failing device is
+ *	ata_eh_set_mode() fails, pointer to the failing device is
  *	returned in @r_failed_dev.
  *
  *	LOCKING:
@@ -3047,7 +3430,8 @@ static int ata_eh_revalidate_and_attach(struct ata_link *link,
  *	RETURNS:
  *	0 on success, negative errno otherwise
  */
-int ata_set_mode(struct ata_link *link, struct ata_device **r_failed_dev)
+static int ata_eh_set_mode(struct ata_link *link,
+			   struct ata_device **r_failed_dev)
 {
 	struct ata_port *ap = link->ap;
 	struct ata_device *dev;
@@ -3068,7 +3452,7 @@ int ata_set_mode(struct ata_link *link, struct ata_device **r_failed_dev)
 	if (ap->ops->set_mode)
 		rc = ap->ops->set_mode(link, r_failed_dev);
 	else
-		rc = ata_do_set_mode(link, r_failed_dev);
+		rc = ata_set_mode(link, r_failed_dev);
 
 	/* if transfer mode has changed, set DUBIOUS_XFER on device */
 	ata_for_each_dev(dev, link, ENABLED) {
@@ -3103,7 +3487,7 @@ static int atapi_eh_clear_ua(struct ata_device *dev)
 	int i;
 
 	for (i = 0; i < ATA_EH_UA_TRIES; i++) {
-		u8 *sense_buffer = dev->link->ap->sector_buf;
+		u8 *sense_buffer = dev->sector_buf;
 		u8 sense_key = 0;
 		unsigned int err_mask;
 
@@ -3201,147 +3585,13 @@ static int ata_eh_maybe_retry_flush(struct ata_device *dev)
 		if (err_mask & AC_ERR_DEV) {
 			qc->err_mask |= AC_ERR_DEV;
 			qc->result_tf = tf;
-			if (!(ap->pflags & ATA_PFLAG_FROZEN))
+			if (!ata_port_is_frozen(ap))
 				rc = 0;
 		}
 	}
 	return rc;
 }
 
-/**
- *	ata_eh_set_lpm - configure SATA interface power management
- *	@link: link to configure power management
- *	@policy: the link power management policy
- *	@r_failed_dev: out parameter for failed device
- *
- *	Enable SATA Interface power management.  This will enable
- *	Device Interface Power Management (DIPM) for min_power and
- *	medium_power_with_dipm policies, and then call driver specific
- *	callbacks for enabling Host Initiated Power management.
- *
- *	LOCKING:
- *	EH context.
- *
- *	RETURNS:
- *	0 on success, -errno on failure.
- */
-static int ata_eh_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
-			  struct ata_device **r_failed_dev)
-{
-	struct ata_port *ap = ata_is_host_link(link) ? link->ap : NULL;
-	struct ata_eh_context *ehc = &link->eh_context;
-	struct ata_device *dev, *link_dev = NULL, *lpm_dev = NULL;
-	enum ata_lpm_policy old_policy = link->lpm_policy;
-	bool no_dipm = link->ap->flags & ATA_FLAG_NO_DIPM;
-	unsigned int hints = ATA_LPM_EMPTY | ATA_LPM_HIPM;
-	unsigned int err_mask;
-	int rc;
-
-	/* if the link or host doesn't do LPM, noop */
-	if (!IS_ENABLED(CONFIG_SATA_HOST) ||
-	    (link->flags & ATA_LFLAG_NO_LPM) || (ap && !ap->ops->set_lpm))
-		return 0;
-
-	/*
-	 * DIPM is enabled only for MIN_POWER as some devices
-	 * misbehave when the host NACKs transition to SLUMBER.  Order
-	 * device and link configurations such that the host always
-	 * allows DIPM requests.
-	 */
-	ata_for_each_dev(dev, link, ENABLED) {
-		bool hipm = ata_id_has_hipm(dev->id);
-		bool dipm = ata_id_has_dipm(dev->id) && !no_dipm;
-
-		/* find the first enabled and LPM enabled devices */
-		if (!link_dev)
-			link_dev = dev;
-
-		if (!lpm_dev && (hipm || dipm))
-			lpm_dev = dev;
-
-		hints &= ~ATA_LPM_EMPTY;
-		if (!hipm)
-			hints &= ~ATA_LPM_HIPM;
-
-		/* disable DIPM before changing link config */
-		if (policy < ATA_LPM_MED_POWER_WITH_DIPM && dipm) {
-			err_mask = ata_dev_set_feature(dev,
-					SETFEATURES_SATA_DISABLE, SATA_DIPM);
-			if (err_mask && err_mask != AC_ERR_DEV) {
-				ata_dev_warn(dev,
-					     "failed to disable DIPM, Emask 0x%x\n",
-					     err_mask);
-				rc = -EIO;
-				goto fail;
-			}
-		}
-	}
-
-	if (ap) {
-		rc = ap->ops->set_lpm(link, policy, hints);
-		if (!rc && ap->slave_link)
-			rc = ap->ops->set_lpm(ap->slave_link, policy, hints);
-	} else
-		rc = sata_pmp_set_lpm(link, policy, hints);
-
-	/*
-	 * Attribute link config failure to the first (LPM) enabled
-	 * device on the link.
-	 */
-	if (rc) {
-		if (rc == -EOPNOTSUPP) {
-			link->flags |= ATA_LFLAG_NO_LPM;
-			return 0;
-		}
-		dev = lpm_dev ? lpm_dev : link_dev;
-		goto fail;
-	}
-
-	/*
-	 * Low level driver acked the transition.  Issue DIPM command
-	 * with the new policy set.
-	 */
-	link->lpm_policy = policy;
-	if (ap && ap->slave_link)
-		ap->slave_link->lpm_policy = policy;
-
-	/* host config updated, enable DIPM if transitioning to MIN_POWER */
-	ata_for_each_dev(dev, link, ENABLED) {
-		if (policy >= ATA_LPM_MED_POWER_WITH_DIPM && !no_dipm &&
-		    ata_id_has_dipm(dev->id)) {
-			err_mask = ata_dev_set_feature(dev,
-					SETFEATURES_SATA_ENABLE, SATA_DIPM);
-			if (err_mask && err_mask != AC_ERR_DEV) {
-				ata_dev_warn(dev,
-					"failed to enable DIPM, Emask 0x%x\n",
-					err_mask);
-				rc = -EIO;
-				goto fail;
-			}
-		}
-	}
-
-	link->last_lpm_change = jiffies;
-	link->flags |= ATA_LFLAG_CHANGED;
-
-	return 0;
-
-fail:
-	/* restore the old policy */
-	link->lpm_policy = old_policy;
-	if (ap && ap->slave_link)
-		ap->slave_link->lpm_policy = old_policy;
-
-	/* if no device or only one more chance is left, disable LPM */
-	if (!dev || ehc->tries[dev->devno] <= 2) {
-		ata_link_warn(link, "disabling LPM on the link\n");
-		link->flags |= ATA_LFLAG_NO_LPM;
-	}
-	if (r_failed_dev)
-		*r_failed_dev = dev;
-	return rc;
-}
-
 int ata_link_nr_enabled(struct ata_link *link)
 {
 	struct ata_device *dev;
@@ -3378,7 +3628,7 @@ static int ata_eh_skip_recovery(struct ata_link *link)
 		return 1;
 
 	/* thaw frozen port and recover failed devices */
-	if ((ap->pflags & ATA_PFLAG_FROZEN) || ata_link_nr_enabled(link))
+	if (ata_port_is_frozen(ap) || ata_link_nr_enabled(link))
 		return 0;
 
 	/* reset at least once if reset is requested */
@@ -3473,11 +3723,11 @@ static int ata_eh_handle_dev_fail(struct ata_device *dev, int err)
 	case -ENODEV:
 		/* device missing or wrong IDENTIFY data, schedule probing */
 		ehc->i.probe_mask |= (1 << dev->devno);
-		/* fall through */
+		fallthrough;
 	case -EINVAL:
 		/* give it just one more chance */
 		ehc->tries[dev->devno] = min(ehc->tries[dev->devno], 1);
-		/* fall through */
+		fallthrough;
 	case -EIO:
 		if (ehc->tries[dev->devno] == 1) {
 			/* This is the last chance, better to slow
@@ -3514,10 +3764,7 @@ static int ata_eh_handle_dev_fail(struct ata_device *dev, int err)
 /**
  *	ata_eh_recover - recover host port after error
  *	@ap: host port to recover
- *	@prereset: prereset method (can be NULL)
- *	@softreset: softreset method (can be NULL)
- *	@hardreset: hardreset method (can be NULL)
- *	@postreset: postreset method (can be NULL)
+ *	@reset_ops: The set of reset operations to use
  *	@r_failed_link: out parameter for failed link
  *
  *	This is the alpha and omega, eum and yang, heart and soul of
@@ -3533,9 +3780,7 @@ static int ata_eh_handle_dev_fail(struct ata_device *dev, int err)
  *	RETURNS:
  *	0 on success, -errno on failure.
  */
-int ata_eh_recover(struct ata_port *ap, ata_prereset_fn_t prereset,
-		   ata_reset_fn_t softreset, ata_reset_fn_t hardreset,
-		   ata_postreset_fn_t postreset,
+int ata_eh_recover(struct ata_port *ap, struct ata_reset_operations *reset_ops,
 		   struct ata_link **r_failed_link)
 {
 	struct ata_link *link;
@@ -3543,8 +3788,6 @@ int ata_eh_recover(struct ata_port *ap, ata_prereset_fn_t prereset,
 	int rc, nr_fails;
 	unsigned long flags, deadline;
 
-	DPRINTK("ENTER\n");
-
 	/* prep for recovery */
 	ata_for_each_link(link, ap, EDGE) {
 		struct ata_eh_context *ehc = &link->eh_context;
@@ -3605,8 +3848,7 @@ int ata_eh_recover(struct ata_port *ap, ata_prereset_fn_t prereset,
 		if (!(ehc->i.action & ATA_EH_RESET))
 			continue;
 
-		rc = ata_eh_reset(link, ata_link_nr_vacant(link),
-				  prereset, softreset, hardreset, postreset);
+		rc = ata_eh_reset(link, ata_link_nr_vacant(link), reset_ops);
 		if (rc) {
 			ata_link_err(link, "reset failed, giving up\n");
 			goto out;
@@ -3687,7 +3929,7 @@ int ata_eh_recover(struct ata_port *ap, ata_prereset_fn_t prereset,
 
 		/* configure transfer mode if necessary */
 		if (ehc->i.flags & ATA_EHI_SETMODE) {
-			rc = ata_set_mode(link, &dev);
+			rc = ata_eh_set_mode(link, &dev);
 			if (rc)
 				goto rest_fail;
 			ehc->i.flags &= ~ATA_EHI_SETMODE;
@@ -3708,6 +3950,17 @@ int ata_eh_recover(struct ata_port *ap, ata_prereset_fn_t prereset,
 			}
 		}
 
+		/*
+		 * Make sure to transition devices to the active power mode
+		 * if needed (e.g. if we were scheduled on system resume).
+		 */
+		ata_for_each_dev(dev, link, ENABLED) {
+			if (ehc->i.dev_action[dev->devno] & ATA_EH_SET_ACTIVE) {
+				ata_dev_power_set_active(dev);
+				ata_eh_done(link, dev, ATA_EH_SET_ACTIVE);
+			}
+		}
+
 		/* retry flush if necessary */
 		ata_for_each_dev(dev, link, ALL) {
 			if (dev->class != ATA_DEV_ATA &&
@@ -3721,7 +3974,8 @@ int ata_eh_recover(struct ata_port *ap, ata_prereset_fn_t prereset,
 	config_lpm:
 		/* configure link power saving */
 		if (link->lpm_policy != ap->target_lpm_policy) {
-			rc = ata_eh_set_lpm(link, ap->target_lpm_policy, &dev);
+			rc = ata_eh_link_set_lpm(link, ap->target_lpm_policy,
+						 &dev);
 			if (rc)
 				goto rest_fail;
 		}
@@ -3735,7 +3989,7 @@ int ata_eh_recover(struct ata_port *ap, ata_prereset_fn_t prereset,
 		if (dev)
 			ata_eh_handle_dev_fail(dev, rc);
 
-		if (ap->pflags & ATA_PFLAG_FROZEN) {
+		if (ata_port_is_frozen(ap)) {
 			/* PMP reset requires working host port.
 			 * Can't retry if it's frozen.
 			 */
@@ -3752,7 +4006,6 @@ int ata_eh_recover(struct ata_port *ap, ata_prereset_fn_t prereset,
 	if (rc && r_failed_link)
 		*r_failed_link = link;
 
-	DPRINTK("EXIT, rc=%d\n", rc);
 	return rc;
 }
 
@@ -3773,7 +4026,7 @@ void ata_eh_finish(struct ata_port *ap)
 
 	/* retry or finish qcs */
 	ata_qc_for_each_raw(ap, qc, tag) {
-		if (!(qc->flags & ATA_QCFLAG_FAILED))
+		if (!(qc->flags & ATA_QCFLAG_EH))
 			continue;
 
 		if (qc->err_mask) {
@@ -3781,16 +4034,30 @@ void ata_eh_finish(struct ata_port *ap)
 			 * generate sense data in this function,
 			 * considering both err_mask and tf.
 			 */
-			if (qc->flags & ATA_QCFLAG_RETRY)
+			if (qc->flags & ATA_QCFLAG_RETRY) {
+				/*
+				 * Since qc->err_mask is set, ata_eh_qc_retry()
+				 * will not increment scmd->allowed, so upper
+				 * layer will only retry the command if it has
+				 * not already been retried too many times.
+				 */
 				ata_eh_qc_retry(qc);
-			else
+			} else {
 				ata_eh_qc_complete(qc);
+			}
 		} else {
-			if (qc->flags & ATA_QCFLAG_SENSE_VALID) {
+			if (qc->flags & ATA_QCFLAG_SENSE_VALID ||
+			    qc->flags & ATA_QCFLAG_EH_SUCCESS_CMD) {
 				ata_eh_qc_complete(qc);
 			} else {
 				/* feed zero TF to sense generation */
 				memset(&qc->result_tf, 0, sizeof(qc->result_tf));
+				/*
+				 * Since qc->err_mask is not set,
+				 * ata_eh_qc_retry() will increment
+				 * scmd->allowed, so upper layer is guaranteed
+				 * to retry the command.
+				 */
 				ata_eh_qc_retry(qc);
 			}
 		}
@@ -3802,59 +4069,39 @@ void ata_eh_finish(struct ata_port *ap)
 }
 
 /**
- *	ata_do_eh - do standard error handling
+ *	ata_std_error_handler - standard error handler
  *	@ap: host port to handle error for
  *
- *	@prereset: prereset method (can be NULL)
- *	@softreset: softreset method (can be NULL)
- *	@hardreset: hardreset method (can be NULL)
- *	@postreset: postreset method (can be NULL)
- *
  *	Perform standard error handling sequence.
  *
  *	LOCKING:
  *	Kernel thread context (may sleep).
  */
-void ata_do_eh(struct ata_port *ap, ata_prereset_fn_t prereset,
-	       ata_reset_fn_t softreset, ata_reset_fn_t hardreset,
-	       ata_postreset_fn_t postreset)
+void ata_std_error_handler(struct ata_port *ap)
 {
-	struct ata_device *dev;
+	struct ata_reset_operations *reset_ops = &ap->ops->reset;
+	struct ata_link *link = &ap->link;
 	int rc;
 
+	/* Ignore built-in hardresets if SCR access is not available */
+	if ((reset_ops->hardreset == sata_std_hardreset ||
+	     reset_ops->hardreset == sata_sff_hardreset) &&
+	    !sata_scr_valid(link))
+		link->flags |= ATA_LFLAG_NO_HRST;
+
 	ata_eh_autopsy(ap);
 	ata_eh_report(ap);
 
-	rc = ata_eh_recover(ap, prereset, softreset, hardreset, postreset,
-			    NULL);
+	rc = ata_eh_recover(ap, reset_ops, NULL);
 	if (rc) {
-		ata_for_each_dev(dev, &ap->link, ALL)
+		struct ata_device *dev;
+
+		ata_for_each_dev(dev, link, ALL)
 			ata_dev_disable(dev);
 	}
 
 	ata_eh_finish(ap);
 }
-
-/**
- *	ata_std_error_handler - standard error handler
- *	@ap: host port to handle error for
- *
- *	Standard error handler
- *
- *	LOCKING:
- *	Kernel thread context (may sleep).
- */
-void ata_std_error_handler(struct ata_port *ap)
-{
-	struct ata_port_operations *ops = ap->ops;
-	ata_reset_fn_t hardreset = ops->hardreset;
-
-	/* ignore built-in hardreset if SCR access is not available */
-	if (hardreset == sata_std_hardreset && !sata_scr_valid(&ap->link))
-		hardreset = NULL;
-
-	ata_do_eh(ap, ops->prereset, ops->softreset, hardreset, ops->postreset);
-}
 EXPORT_SYMBOL_GPL(ata_std_error_handler);
 
 #ifdef CONFIG_PM
@@ -3872,6 +4119,7 @@ static void ata_eh_handle_port_suspend(struct ata_port *ap)
 	unsigned long flags;
 	int rc = 0;
 	struct ata_device *dev;
+	struct ata_link *link;
 
 	/* are we suspending? */
 	spin_lock_irqsave(ap->lock, flags);
@@ -3885,6 +4133,22 @@ static void ata_eh_handle_port_suspend(struct ata_port *ap)
 	WARN_ON(ap->pflags & ATA_PFLAG_SUSPENDED);
 
 	/*
+	 * We will reach this point for all of the PM events:
+	 * PM_EVENT_SUSPEND (if runtime pm, PM_EVENT_AUTO will also be set)
+	 * PM_EVENT_FREEZE, and PM_EVENT_HIBERNATE.
+	 *
+	 * We do not want to perform disk spin down for PM_EVENT_FREEZE.
+	 * (Spin down will be performed by the subsequent PM_EVENT_HIBERNATE.)
+	 */
+	if (!(ap->pm_mesg.event & PM_EVENT_FREEZE)) {
+		/* Set all devices attached to the port in standby mode */
+		ata_for_each_link(link, ap, HOST_FIRST) {
+			ata_for_each_dev(dev, link, ENABLED)
+				ata_dev_power_set_standby(dev);
+		}
+	}
+
+	/*
 	 * If we have a ZPODD attached, check its zero
 	 * power ready status before the port is frozen.
 	 * Only needed for runtime suspend.
@@ -3896,11 +4160,6 @@ static void ata_eh_handle_port_suspend(struct ata_port *ap)
 		}
 	}
 
-	/* tell ACPI we're suspending */
-	rc = ata_acpi_on_suspend(ap);
-	if (rc)
-		goto out;
-
 	/* suspend */
 	ata_eh_freeze_port(ap);
 
@@ -3908,14 +4167,14 @@ static void ata_eh_handle_port_suspend(struct ata_port *ap)
 		rc = ap->ops->port_suspend(ap, ap->pm_mesg);
 
 	ata_acpi_set_state(ap, ap->pm_mesg);
- out:
+
 	/* update the flags */
 	spin_lock_irqsave(ap->lock, flags);
 
 	ap->pflags &= ~ATA_PFLAG_PM_PENDING;
 	if (rc == 0)
 		ap->pflags |= ATA_PFLAG_SUSPENDED;
-	else if (ap->pflags & ATA_PFLAG_FROZEN)
+	else if (ata_port_is_frozen(ap))
 		ata_port_schedule_eh(ap);
 
 	spin_unlock_irqrestore(ap->lock, flags);
@@ -3971,6 +4230,7 @@ static void ata_eh_handle_port_resume(struct ata_port *ap)
 	/* update the flags */
 	spin_lock_irqsave(ap->lock, flags);
 	ap->pflags &= ~(ATA_PFLAG_PM_PENDING | ATA_PFLAG_SUSPENDED);
+	ap->pflags |= ATA_PFLAG_RESUMING;
 	spin_unlock_irqrestore(ap->lock, flags);
 }
 #endif /* CONFIG_PM */
diff --git a/drivers/ata/libata-pmp.c b/drivers/ata/libata-pmp.c
index 79f2aeeb482a..57023324a56f 100644
--- a/drivers/ata/libata-pmp.c
+++ b/drivers/ata/libata-pmp.c
@@ -15,9 +15,9 @@
 
 const struct ata_port_operations sata_pmp_port_ops = {
 	.inherits		= &sata_port_ops,
-	.pmp_prereset		= ata_std_prereset,
-	.pmp_hardreset		= sata_std_hardreset,
-	.pmp_postreset		= ata_std_postreset,
+	.pmp_reset.prereset	= ata_std_prereset,
+	.pmp_reset.hardreset	= sata_std_hardreset,
+	.pmp_reset.postreset	= ata_std_postreset,
 	.error_handler		= sata_pmp_error_handler,
 };
 
@@ -62,7 +62,7 @@ static unsigned int sata_pmp_read(struct ata_link *link, int reg, u32 *r_val)
  *	sata_pmp_write - write PMP register
  *	@link: link to write PMP register for
  *	@reg: register to write
- *	@r_val: value to write
+ *	@val: value to write
  *
  *	Write PMP register.
  *
@@ -648,12 +648,9 @@ static int sata_pmp_same_pmp(struct ata_device *dev, const u32 *new_gscr)
 static int sata_pmp_revalidate(struct ata_device *dev, unsigned int new_class)
 {
 	struct ata_link *link = dev->link;
-	struct ata_port *ap = link->ap;
-	u32 *gscr = (void *)ap->sector_buf;
+	u32 *gscr = (void *)dev->sector_buf;
 	int rc;
 
-	DPRINTK("ENTER\n");
-
 	ata_eh_about_to_do(link, NULL, ATA_EH_REVALIDATE);
 
 	if (!ata_dev_enabled(dev)) {
@@ -686,12 +683,10 @@ static int sata_pmp_revalidate(struct ata_device *dev, unsigned int new_class)
 
 	ata_eh_done(link, NULL, ATA_EH_REVALIDATE);
 
-	DPRINTK("EXIT, rc=0\n");
 	return 0;
 
  fail:
 	ata_dev_err(dev, "PMP revalidation failed (errno=%d)\n", rc);
-	DPRINTK("EXIT, rc=%d\n", rc);
 	return rc;
 }
 
@@ -732,10 +727,7 @@ static int sata_pmp_revalidate_quick(struct ata_device *dev)
 /**
  *	sata_pmp_eh_recover_pmp - recover PMP
  *	@ap: ATA port PMP is attached to
- *	@prereset: prereset method (can be NULL)
- *	@softreset: softreset method
- *	@hardreset: hardreset method
- *	@postreset: postreset method (can be NULL)
+ *	@reset_ops: The set of reset operations to use
  *
  *	Recover PMP attached to @ap.  Recovery procedure is somewhat
  *	similar to that of ata_eh_recover() except that reset should
@@ -749,8 +741,7 @@ static int sata_pmp_revalidate_quick(struct ata_device *dev)
  *	0 on success, -errno on failure.
  */
 static int sata_pmp_eh_recover_pmp(struct ata_port *ap,
-		ata_prereset_fn_t prereset, ata_reset_fn_t softreset,
-		ata_reset_fn_t hardreset, ata_postreset_fn_t postreset)
+				   struct ata_reset_operations *reset_ops)
 {
 	struct ata_link *link = &ap->link;
 	struct ata_eh_context *ehc = &link->eh_context;
@@ -759,8 +750,6 @@ static int sata_pmp_eh_recover_pmp(struct ata_port *ap,
 	int detach = 0, rc = 0;
 	int reval_failed = 0;
 
-	DPRINTK("ENTER\n");
-
 	if (dev->flags & ATA_DFLAG_DETACH) {
 		detach = 1;
 		rc = -ENODEV;
@@ -774,8 +763,7 @@ static int sata_pmp_eh_recover_pmp(struct ata_port *ap,
 		struct ata_link *tlink;
 
 		/* reset */
-		rc = ata_eh_reset(link, 0, prereset, softreset, hardreset,
-				  postreset);
+		rc = ata_eh_reset(link, 0, reset_ops);
 		if (rc) {
 			ata_link_err(link, "failed to reset PMP, giving up\n");
 			goto fail;
@@ -828,7 +816,6 @@ static int sata_pmp_eh_recover_pmp(struct ata_port *ap,
 	/* okay, PMP resurrected */
 	ehc->i.flags = 0;
 
-	DPRINTK("EXIT, rc=0\n");
 	return 0;
 
  fail:
@@ -838,7 +825,6 @@ static int sata_pmp_eh_recover_pmp(struct ata_port *ap,
 	else
 		ata_dev_disable(dev);
 
-	DPRINTK("EXIT, rc=%d\n", rc);
 	return rc;
 }
 
@@ -941,8 +927,7 @@ static int sata_pmp_eh_recover(struct ata_port *ap)
  retry:
 	/* PMP attached? */
 	if (!sata_pmp_attached(ap)) {
-		rc = ata_eh_recover(ap, ops->prereset, ops->softreset,
-				    ops->hardreset, ops->postreset, NULL);
+		rc = ata_eh_recover(ap, &ops->reset, NULL);
 		if (rc) {
 			ata_for_each_dev(dev, &ap->link, ALL)
 				ata_dev_disable(dev);
@@ -960,8 +945,7 @@ static int sata_pmp_eh_recover(struct ata_port *ap)
 	}
 
 	/* recover pmp */
-	rc = sata_pmp_eh_recover_pmp(ap, ops->prereset, ops->softreset,
-				     ops->hardreset, ops->postreset);
+	rc = sata_pmp_eh_recover_pmp(ap, &ops->reset);
 	if (rc)
 		goto pmp_fail;
 
@@ -987,8 +971,7 @@ static int sata_pmp_eh_recover(struct ata_port *ap)
 		goto pmp_fail;
 
 	/* recover links */
-	rc = ata_eh_recover(ap, ops->pmp_prereset, ops->pmp_softreset,
-			    ops->pmp_hardreset, ops->pmp_postreset, &link);
+	rc = ata_eh_recover(ap, &ops->pmp_reset, &link);
 	if (rc)
 		goto link_fail;
 
diff --git a/drivers/ata/libata-sata.c b/drivers/ata/libata-sata.c
index c16423e44525..b2817a2995d6 100644
--- a/drivers/ata/libata-sata.c
+++ b/drivers/ata/libata-sata.c
@@ -11,17 +11,19 @@
 #include <linux/module.h>
 #include <scsi/scsi_cmnd.h>
 #include <scsi/scsi_device.h>
+#include <scsi/scsi_eh.h>
 #include <linux/libata.h>
+#include <linux/unaligned.h>
 
 #include "libata.h"
 #include "libata-transport.h"
 
 /* debounce timing parameters in msecs { interval, duration, timeout } */
-const unsigned long sata_deb_timing_normal[]		= {   5,  100, 2000 };
+const unsigned int sata_deb_timing_normal[]		= {   5,  100, 2000 };
 EXPORT_SYMBOL_GPL(sata_deb_timing_normal);
-const unsigned long sata_deb_timing_hotplug[]		= {  25,  500, 2000 };
+const unsigned int sata_deb_timing_hotplug[]		= {  25,  500, 2000 };
 EXPORT_SYMBOL_GPL(sata_deb_timing_hotplug);
-const unsigned long sata_deb_timing_long[]		= { 100, 2000, 5000 };
+const unsigned int sata_deb_timing_long[]		= { 100, 2000, 5000 };
 EXPORT_SYMBOL_GPL(sata_deb_timing_long);
 
 /**
@@ -191,8 +193,8 @@ EXPORT_SYMBOL_GPL(ata_tf_to_fis);
 
 void ata_tf_from_fis(const u8 *fis, struct ata_taskfile *tf)
 {
-	tf->command	= fis[2];	/* status */
-	tf->feature	= fis[3];	/* error */
+	tf->status	= fis[2];
+	tf->error	= fis[3];
 
 	tf->lbal	= fis[4];
 	tf->lbam	= fis[5];
@@ -230,11 +232,11 @@ EXPORT_SYMBOL_GPL(ata_tf_from_fis);
  *	RETURNS:
  *	0 on success, -errno on failure.
  */
-int sata_link_debounce(struct ata_link *link, const unsigned long *params,
+int sata_link_debounce(struct ata_link *link, const unsigned int *params,
 		       unsigned long deadline)
 {
-	unsigned long interval = params[0];
-	unsigned long duration = params[1];
+	unsigned int interval = params[0];
+	unsigned int duration = params[1];
 	unsigned long last_jiffies, t;
 	u32 last, cur;
 	int rc;
@@ -293,7 +295,7 @@ EXPORT_SYMBOL_GPL(sata_link_debounce);
  *	RETURNS:
  *	0 on success, -errno on failure.
  */
-int sata_link_resume(struct ata_link *link, const unsigned long *params,
+int sata_link_resume(struct ata_link *link, const unsigned int *params,
 		     unsigned long deadline)
 {
 	int tries = ATA_LINK_RESUME_TRIES;
@@ -317,7 +319,7 @@ int sata_link_resume(struct ata_link *link, const unsigned long *params,
 		 * immediately after resuming.  Delay 200ms before
 		 * debouncing.
 		 */
-		if (!(link->flags & ATA_LFLAG_NO_DB_DELAY))
+		if (!(link->flags & ATA_LFLAG_NO_DEBOUNCE_DELAY))
 			ata_msleep(link->ap, 200);
 
 		/* is SControl restored correctly? */
@@ -394,10 +396,23 @@ int sata_link_scr_lpm(struct ata_link *link, enum ata_lpm_policy policy,
 	case ATA_LPM_MED_POWER_WITH_DIPM:
 	case ATA_LPM_MIN_POWER_WITH_PARTIAL:
 	case ATA_LPM_MIN_POWER:
-		if (ata_link_nr_enabled(link) > 0)
-			/* no restrictions on LPM transitions */
+		if (ata_link_nr_enabled(link) > 0) {
+			/* assume no restrictions on LPM transitions */
 			scontrol &= ~(0x7 << 8);
-		else {
+
+			/*
+			 * If the controller does not support partial, slumber,
+			 * or devsleep, then disallow these transitions.
+			 */
+			if (link->ap->host->flags & ATA_HOST_NO_PART)
+				scontrol |= (0x1 << 8);
+
+			if (link->ap->host->flags & ATA_HOST_NO_SSC)
+				scontrol |= (0x2 << 8);
+
+			if (link->ap->host->flags & ATA_HOST_NO_DEVSLP)
+				scontrol |= (0x4 << 8);
+		} else {
 			/* empty port, power off */
 			scontrol &= ~0xf;
 			scontrol |= (0x1 << 2);
@@ -503,6 +518,86 @@ int sata_set_spd(struct ata_link *link)
 EXPORT_SYMBOL_GPL(sata_set_spd);
 
 /**
+ *	sata_down_spd_limit - adjust SATA spd limit downward
+ *	@link: Link to adjust SATA spd limit for
+ *	@spd_limit: Additional limit
+ *
+ *	Adjust SATA spd limit of @link downward.  Note that this
+ *	function only adjusts the limit.  The change must be applied
+ *	using sata_set_spd().
+ *
+ *	If @spd_limit is non-zero, the speed is limited to equal to or
+ *	lower than @spd_limit if such speed is supported.  If
+ *	@spd_limit is slower than any supported speed, only the lowest
+ *	supported speed is allowed.
+ *
+ *	LOCKING:
+ *	Inherited from caller.
+ *
+ *	RETURNS:
+ *	0 on success, negative errno on failure
+ */
+int sata_down_spd_limit(struct ata_link *link, u32 spd_limit)
+{
+	u32 sstatus, spd, mask;
+	int rc, bit;
+
+	if (!sata_scr_valid(link))
+		return -EOPNOTSUPP;
+
+	/* If SCR can be read, use it to determine the current SPD.
+	 * If not, use cached value in link->sata_spd.
+	 */
+	rc = sata_scr_read(link, SCR_STATUS, &sstatus);
+	if (rc == 0 && ata_sstatus_online(sstatus))
+		spd = (sstatus >> 4) & 0xf;
+	else
+		spd = link->sata_spd;
+
+	mask = link->sata_spd_limit;
+	if (mask <= 1)
+		return -EINVAL;
+
+	/* unconditionally mask off the highest bit */
+	bit = fls(mask) - 1;
+	mask &= ~(1 << bit);
+
+	/*
+	 * Mask off all speeds higher than or equal to the current one.  At
+	 * this point, if current SPD is not available and we previously
+	 * recorded the link speed from SStatus, the driver has already
+	 * masked off the highest bit so mask should already be 1 or 0.
+	 * Otherwise, we should not force 1.5Gbps on a link where we have
+	 * not previously recorded speed from SStatus.  Just return in this
+	 * case.
+	 */
+	if (spd > 1)
+		mask &= (1 << (spd - 1)) - 1;
+	else if (link->sata_spd)
+		return -EINVAL;
+
+	/* were we already at the bottom? */
+	if (!mask)
+		return -EINVAL;
+
+	if (spd_limit) {
+		if (mask & ((1 << spd_limit) - 1))
+			mask &= (1 << spd_limit) - 1;
+		else {
+			bit = ffs(mask) - 1;
+			mask = 1 << bit;
+		}
+	}
+
+	link->sata_spd_limit = mask;
+
+	ata_link_warn(link, "limiting SATA link speed to %s\n",
+		      sata_spd_string(fls(mask)));
+
+	return 0;
+}
+
+/**
  *	sata_link_hardreset - reset link via SATA phy reset
  *	@link: link to reset
  *	@timing: timing parameters { interval, duration, timeout } in msec
@@ -526,15 +621,13 @@ EXPORT_SYMBOL_GPL(sata_set_spd);
  *	RETURNS:
  *	0 on success, -errno otherwise.
  */
-int sata_link_hardreset(struct ata_link *link, const unsigned long *timing,
+int sata_link_hardreset(struct ata_link *link, const unsigned int *timing,
 			unsigned long deadline,
 			bool *online, int (*check_ready)(struct ata_link *))
 {
 	u32 scontrol;
 	int rc;
 
-	DPRINTK("ENTER\n");
-
 	if (online)
 		*online = false;
 
@@ -608,14 +701,40 @@ int sata_link_hardreset(struct ata_link *link, const unsigned long *timing,
 		/* online is set iff link is online && reset succeeded */
 		if (online)
 			*online = false;
-		ata_link_err(link, "COMRESET failed (errno=%d)\n", rc);
 	}
-	DPRINTK("EXIT, rc=%d\n", rc);
 	return rc;
 }
 EXPORT_SYMBOL_GPL(sata_link_hardreset);
 
 /**
+ *	sata_std_hardreset - COMRESET w/o waiting or classification
+ *	@link: link to reset
+ *	@class: resulting class of attached device
+ *	@deadline: deadline jiffies for the operation
+ *
+ *	Standard SATA COMRESET w/o waiting or classification.
+ *
+ *	LOCKING:
+ *	Kernel thread context (may sleep)
+ *
+ *	RETURNS:
+ *	0 if link offline, -EAGAIN if link online, -errno on errors.
+ */
+int sata_std_hardreset(struct ata_link *link, unsigned int *class,
+		       unsigned long deadline)
+{
+	const unsigned int *timing = sata_ehc_deb_timing(&link->eh_context);
+	bool online;
+	int rc;
+
+	rc = sata_link_hardreset(link, timing, deadline, &online, NULL);
+	if (online)
+		return -EAGAIN;
+	return rc;
+}
+EXPORT_SYMBOL_GPL(sata_std_hardreset);
+
+/**
  *	ata_qc_complete_multiple - Complete multiple qcs successfully
  *	@ap: port in question
  *	@qc_active: new qc_active mask
@@ -658,6 +777,9 @@ int ata_qc_complete_multiple(struct ata_port *ap, u64 qc_active)
 		return -EINVAL;
 	}
 
+	if (ap->ops->qc_ncq_fill_rtf)
+		ap->ops->qc_ncq_fill_rtf(ap, done_mask);
+
 	while (done_mask) {
 		struct ata_queued_cmd *qc;
 		unsigned int tag = __ffs64(done_mask);
@@ -770,7 +892,7 @@ bool sata_lpm_ignore_phy_events(struct ata_link *link)
 EXPORT_SYMBOL_GPL(sata_lpm_ignore_phy_events);
 
 static const char *ata_lpm_policy_names[] = {
-	[ATA_LPM_UNKNOWN]		= "max_performance",
+	[ATA_LPM_UNKNOWN]		= "keep_firmware_settings",
 	[ATA_LPM_MAX_POWER]		= "max_performance",
 	[ATA_LPM_MED_POWER]		= "medium_power",
 	[ATA_LPM_MED_POWER_WITH_DIPM]	= "med_power_with_dipm",
@@ -778,14 +900,52 @@ static const char *ata_lpm_policy_names[] = {
 	[ATA_LPM_MIN_POWER]		= "min_power",
 };
 
+/*
+ * Check if a port supports link power management.
+ * Must be called with the port locked.
+ */
+static bool ata_scsi_lpm_supported(struct ata_port *ap)
+{
+	struct ata_link *link;
+	struct ata_device *dev;
+
+	if (ap->flags & ATA_FLAG_NO_LPM)
+		return false;
+
+	ata_for_each_link(link, ap, EDGE) {
+		ata_for_each_dev(dev, &ap->link, ENABLED) {
+			if (dev->quirks & ATA_QUIRK_NOLPM)
+				return false;
+		}
+	}
+
+	return true;
+}
+
+static ssize_t ata_scsi_lpm_supported_show(struct device *dev,
+				 struct device_attribute *attr, char *buf)
+{
+	struct Scsi_Host *shost = class_to_shost(dev);
+	struct ata_port *ap = ata_shost_to_port(shost);
+	unsigned long flags;
+	bool supported;
+
+	spin_lock_irqsave(ap->lock, flags);
+	supported = ata_scsi_lpm_supported(ap);
+	spin_unlock_irqrestore(ap->lock, flags);
+
+	return sysfs_emit(buf, "%d\n", supported);
+}
+DEVICE_ATTR(link_power_management_supported, S_IRUGO,
+	    ata_scsi_lpm_supported_show, NULL);
+EXPORT_SYMBOL_GPL(dev_attr_link_power_management_supported);
+
 static ssize_t ata_scsi_lpm_store(struct device *device,
 				  struct device_attribute *attr,
 				  const char *buf, size_t count)
 {
 	struct Scsi_Host *shost = class_to_shost(device);
 	struct ata_port *ap = ata_shost_to_port(shost);
-	struct ata_link *link;
-	struct ata_device *dev;
 	enum ata_lpm_policy policy;
 	unsigned long flags;
 
@@ -802,13 +962,9 @@ static ssize_t ata_scsi_lpm_store(struct device *device,
 
 	spin_lock_irqsave(ap->lock, flags);
 
-	ata_for_each_link(link, ap, EDGE) {
-		ata_for_each_dev(dev, &ap->link, ENABLED) {
-			if (dev->horkage & ATA_HORKAGE_NOLPM) {
-				count = -EOPNOTSUPP;
-				goto out_unlock;
-			}
-		}
+	if (!ata_scsi_lpm_supported(ap)) {
+		count = -EOPNOTSUPP;
+		goto out_unlock;
 	}
 
 	ap->target_lpm_policy = policy;
@@ -827,96 +983,208 @@ static ssize_t ata_scsi_lpm_show(struct device *dev,
 	if (ap->target_lpm_policy >= ARRAY_SIZE(ata_lpm_policy_names))
 		return -EINVAL;
 
-	return snprintf(buf, PAGE_SIZE, "%s\n",
+	return sysfs_emit(buf, "%s\n",
 			ata_lpm_policy_names[ap->target_lpm_policy]);
 }
 DEVICE_ATTR(link_power_management_policy, S_IRUGO | S_IWUSR,
 	    ata_scsi_lpm_show, ata_scsi_lpm_store);
 EXPORT_SYMBOL_GPL(dev_attr_link_power_management_policy);
 
+/**
+ *	ata_ncq_prio_supported - Check if device supports NCQ Priority
+ *	@ap: ATA port of the target device
+ *	@sdev: SCSI device
+ *	@supported: Address of a boolean to store the result
+ *
+ *	Helper to check if device supports NCQ Priority feature.
+ *
+ *	Context: Any context. Takes and releases @ap->lock.
+ *
+ *	Return:
+ *	* %0		- OK. Status is stored into @supported
+ *	* %-ENODEV	- Failed to find the ATA device
+ */
+int ata_ncq_prio_supported(struct ata_port *ap, struct scsi_device *sdev,
+			   bool *supported)
+{
+	struct ata_device *dev;
+	unsigned long flags;
+	int rc = 0;
+
+	spin_lock_irqsave(ap->lock, flags);
+	dev = ata_scsi_find_dev(ap, sdev);
+	if (!dev)
+		rc = -ENODEV;
+	else
+		*supported = dev->flags & ATA_DFLAG_NCQ_PRIO;
+	spin_unlock_irqrestore(ap->lock, flags);
+
+	return rc;
+}
+EXPORT_SYMBOL_GPL(ata_ncq_prio_supported);
+
+static ssize_t ata_ncq_prio_supported_show(struct device *device,
+					   struct device_attribute *attr,
+					   char *buf)
+{
+	struct scsi_device *sdev = to_scsi_device(device);
+	struct ata_port *ap = ata_shost_to_port(sdev->host);
+	bool supported;
+	int rc;
+
+	rc = ata_ncq_prio_supported(ap, sdev, &supported);
+	if (rc)
+		return rc;
+
+	return sysfs_emit(buf, "%d\n", supported);
+}
+
+DEVICE_ATTR(ncq_prio_supported, S_IRUGO, ata_ncq_prio_supported_show, NULL);
+EXPORT_SYMBOL_GPL(dev_attr_ncq_prio_supported);
+
+/**
+ *	ata_ncq_prio_enabled - Check if NCQ Priority is enabled
+ *	@ap: ATA port of the target device
+ *	@sdev: SCSI device
+ *	@enabled: Address of a boolean to store the result
+ *
+ *	Helper to check if NCQ Priority feature is enabled.
+ *
+ *	Context: Any context. Takes and releases @ap->lock.
+ *
+ *	Return:
+ *	* %0		- OK. Status is stored into @enabled
+ *	* %-ENODEV	- Failed to find the ATA device
+ */
+int ata_ncq_prio_enabled(struct ata_port *ap, struct scsi_device *sdev,
+			 bool *enabled)
+{
+	struct ata_device *dev;
+	unsigned long flags;
+	int rc = 0;
+
+	spin_lock_irqsave(ap->lock, flags);
+	dev = ata_scsi_find_dev(ap, sdev);
+	if (!dev)
+		rc = -ENODEV;
+	else
+		*enabled = dev->flags & ATA_DFLAG_NCQ_PRIO_ENABLED;
+	spin_unlock_irqrestore(ap->lock, flags);
+
+	return rc;
+}
+EXPORT_SYMBOL_GPL(ata_ncq_prio_enabled);
+
 static ssize_t ata_ncq_prio_enable_show(struct device *device,
 					struct device_attribute *attr,
 					char *buf)
 {
 	struct scsi_device *sdev = to_scsi_device(device);
-	struct ata_port *ap;
+	struct ata_port *ap = ata_shost_to_port(sdev->host);
+	bool enabled;
+	int rc;
+
+	rc = ata_ncq_prio_enabled(ap, sdev, &enabled);
+	if (rc)
+		return rc;
+
+	return sysfs_emit(buf, "%d\n", enabled);
+}
+
+/**
+ *	ata_ncq_prio_enable - Enable/disable NCQ Priority
+ *	@ap: ATA port of the target device
+ *	@sdev: SCSI device
+ *	@enable: true - enable NCQ Priority, false - disable NCQ Priority
+ *
+ *	Helper to enable/disable NCQ Priority feature.
+ *
+ *	Context: Any context. Takes and releases @ap->lock.
+ *
+ *	Return:
+ *	* %0		- OK. Status is stored into @enabled
+ *	* %-ENODEV	- Failed to find the ATA device
+ *	* %-EINVAL	- NCQ Priority is not supported or CDL is enabled
+ */
+int ata_ncq_prio_enable(struct ata_port *ap, struct scsi_device *sdev,
+			bool enable)
+{
 	struct ata_device *dev;
-	bool ncq_prio_enable;
+	unsigned long flags;
 	int rc = 0;
 
-	ap = ata_shost_to_port(sdev->host);
+	spin_lock_irqsave(ap->lock, flags);
 
-	spin_lock_irq(ap->lock);
 	dev = ata_scsi_find_dev(ap, sdev);
 	if (!dev) {
 		rc = -ENODEV;
 		goto unlock;
 	}
 
-	ncq_prio_enable = dev->flags & ATA_DFLAG_NCQ_PRIO_ENABLE;
+	if (!(dev->flags & ATA_DFLAG_NCQ_PRIO)) {
+		rc = -EINVAL;
+		goto unlock;
+	}
+
+	if (enable) {
+		if (dev->flags & ATA_DFLAG_CDL_ENABLED) {
+			ata_dev_err(dev,
+				"CDL must be disabled to enable NCQ priority\n");
+			rc = -EINVAL;
+			goto unlock;
+		}
+		dev->flags |= ATA_DFLAG_NCQ_PRIO_ENABLED;
+	} else {
+		dev->flags &= ~ATA_DFLAG_NCQ_PRIO_ENABLED;
+	}
 
 unlock:
-	spin_unlock_irq(ap->lock);
+	spin_unlock_irqrestore(ap->lock, flags);
 
-	return rc ? rc : snprintf(buf, 20, "%u\n", ncq_prio_enable);
+	return rc;
 }
+EXPORT_SYMBOL_GPL(ata_ncq_prio_enable);
 
 static ssize_t ata_ncq_prio_enable_store(struct device *device,
 					 struct device_attribute *attr,
 					 const char *buf, size_t len)
 {
 	struct scsi_device *sdev = to_scsi_device(device);
-	struct ata_port *ap;
-	struct ata_device *dev;
-	long int input;
+	struct ata_port *ap = ata_shost_to_port(sdev->host);
+	bool enable;
 	int rc;
 
-	rc = kstrtol(buf, 10, &input);
+	rc = kstrtobool(buf, &enable);
 	if (rc)
 		return rc;
-	if ((input < 0) || (input > 1))
-		return -EINVAL;
-
-	ap = ata_shost_to_port(sdev->host);
-	dev = ata_scsi_find_dev(ap, sdev);
-	if (unlikely(!dev))
-		return  -ENODEV;
-
-	spin_lock_irq(ap->lock);
-	if (input)
-		dev->flags |= ATA_DFLAG_NCQ_PRIO_ENABLE;
-	else
-		dev->flags &= ~ATA_DFLAG_NCQ_PRIO_ENABLE;
-
-	dev->link->eh_info.action |= ATA_EH_REVALIDATE;
-	dev->link->eh_info.flags |= ATA_EHI_QUIET;
-	ata_port_schedule_eh(ap);
-	spin_unlock_irq(ap->lock);
 
-	ata_port_wait_eh(ap);
-
-	if (input) {
-		spin_lock_irq(ap->lock);
-		if (!(dev->flags & ATA_DFLAG_NCQ_PRIO)) {
-			dev->flags &= ~ATA_DFLAG_NCQ_PRIO_ENABLE;
-			rc = -EIO;
-		}
-		spin_unlock_irq(ap->lock);
-	}
+	rc = ata_ncq_prio_enable(ap, sdev, enable);
+	if (rc)
+		return rc;
 
-	return rc ? rc : len;
+	return len;
 }
 
 DEVICE_ATTR(ncq_prio_enable, S_IRUGO | S_IWUSR,
 	    ata_ncq_prio_enable_show, ata_ncq_prio_enable_store);
 EXPORT_SYMBOL_GPL(dev_attr_ncq_prio_enable);
 
-struct device_attribute *ata_ncq_sdev_attrs[] = {
-	&dev_attr_unload_heads,
-	&dev_attr_ncq_prio_enable,
+static struct attribute *ata_ncq_sdev_attrs[] = {
+	&dev_attr_unload_heads.attr,
+	&dev_attr_ncq_prio_enable.attr,
+	&dev_attr_ncq_prio_supported.attr,
 	NULL
 };
-EXPORT_SYMBOL_GPL(ata_ncq_sdev_attrs);
+
+static const struct attribute_group ata_ncq_sdev_attr_group = {
+	.attrs = ata_ncq_sdev_attrs
+};
+
+const struct attribute_group *ata_ncq_sdev_groups[] = {
+	&ata_ncq_sdev_attr_group,
+	NULL
+};
+EXPORT_SYMBOL_GPL(ata_ncq_sdev_groups);
 
 static ssize_t
 ata_scsi_em_message_store(struct device *dev, struct device_attribute *attr,
@@ -951,7 +1219,7 @@ ata_scsi_em_message_type_show(struct device *dev, struct device_attribute *attr,
 	struct Scsi_Host *shost = class_to_shost(dev);
 	struct ata_port *ap = ata_shost_to_port(shost);
 
-	return snprintf(buf, 23, "%d\n", ap->em_message_type);
+	return sysfs_emit(buf, "%d\n", ap->em_message_type);
 }
 DEVICE_ATTR(em_message_type, S_IRUGO,
 		  ata_scsi_em_message_type_show, NULL);
@@ -1000,48 +1268,60 @@ DEVICE_ATTR(sw_activity, S_IWUSR | S_IRUGO, ata_scsi_activity_show,
 EXPORT_SYMBOL_GPL(dev_attr_sw_activity);
 
 /**
- *	__ata_change_queue_depth - helper for ata_scsi_change_queue_depth
- *	@ap: ATA port to which the device change the queue depth
+ *	ata_change_queue_depth - Set a device maximum queue depth
+ *	@ap: ATA port of the target device
  *	@sdev: SCSI device to configure queue depth for
  *	@queue_depth: new queue depth
  *
- *	libsas and libata have different approaches for associating a sdev to
- *	its ata_port.
+ *	Helper to set a device maximum queue depth, usable with both libsas
+ *	and libata.
  *
  */
-int __ata_change_queue_depth(struct ata_port *ap, struct scsi_device *sdev,
-			     int queue_depth)
+int ata_change_queue_depth(struct ata_port *ap, struct scsi_device *sdev,
+			   int queue_depth)
 {
 	struct ata_device *dev;
 	unsigned long flags;
+	int max_queue_depth;
 
-	if (queue_depth < 1 || queue_depth == sdev->queue_depth)
-		return sdev->queue_depth;
+	spin_lock_irqsave(ap->lock, flags);
 
 	dev = ata_scsi_find_dev(ap, sdev);
-	if (!dev || !ata_dev_enabled(dev))
+	if (!dev || queue_depth < 1 || queue_depth == sdev->queue_depth) {
+		spin_unlock_irqrestore(ap->lock, flags);
 		return sdev->queue_depth;
+	}
 
-	/* NCQ enabled? */
-	spin_lock_irqsave(ap->lock, flags);
-	dev->flags &= ~ATA_DFLAG_NCQ_OFF;
-	if (queue_depth == 1 || !ata_ncq_enabled(dev)) {
+	/*
+	 * Make sure that the queue depth requested does not exceed the device
+	 * capabilities.
+	 */
+	max_queue_depth = min(ATA_MAX_QUEUE, sdev->host->can_queue);
+	max_queue_depth = min(max_queue_depth, ata_id_queue_depth(dev->id));
+	if (queue_depth > max_queue_depth) {
+		spin_unlock_irqrestore(ap->lock, flags);
+		return -EINVAL;
+	}
+
+	/*
+	 * If NCQ is not supported by the device or if the target queue depth
+	 * is 1 (to disable drive side command queueing), turn off NCQ.
+	 */
+	if (queue_depth == 1 || !ata_ncq_supported(dev)) {
 		dev->flags |= ATA_DFLAG_NCQ_OFF;
 		queue_depth = 1;
+	} else {
+		dev->flags &= ~ATA_DFLAG_NCQ_OFF;
 	}
-	spin_unlock_irqrestore(ap->lock, flags);
 
-	/* limit and apply queue depth */
-	queue_depth = min(queue_depth, sdev->host->can_queue);
-	queue_depth = min(queue_depth, ata_id_queue_depth(dev->id));
-	queue_depth = min(queue_depth, ATA_MAX_QUEUE);
+	spin_unlock_irqrestore(ap->lock, flags);
 
-	if (sdev->queue_depth == queue_depth)
-		return -EINVAL;
+	if (queue_depth == sdev->queue_depth)
+		return sdev->queue_depth;
 
 	return scsi_change_queue_depth(sdev, queue_depth);
 }
-EXPORT_SYMBOL_GPL(__ata_change_queue_depth);
+EXPORT_SYMBOL_GPL(ata_change_queue_depth);
 
 /**
  *	ata_scsi_change_queue_depth - SCSI callback for queue depth config
@@ -1062,169 +1342,29 @@ int ata_scsi_change_queue_depth(struct scsi_device *sdev, int queue_depth)
 {
 	struct ata_port *ap = ata_shost_to_port(sdev->host);
 
-	return __ata_change_queue_depth(ap, sdev, queue_depth);
+	return ata_change_queue_depth(ap, sdev, queue_depth);
 }
 EXPORT_SYMBOL_GPL(ata_scsi_change_queue_depth);
 
 /**
- *	port_alloc - Allocate port for a SAS attached SATA device
- *	@host: ATA host container for all SAS ports
- *	@port_info: Information from low-level host driver
- *	@shost: SCSI host that the scsi device is attached to
- *
- *	LOCKING:
- *	PCI/etc. bus probe sem.
- *
- *	RETURNS:
- *	ata_port pointer on success / NULL on failure.
- */
-
-struct ata_port *ata_sas_port_alloc(struct ata_host *host,
-				    struct ata_port_info *port_info,
-				    struct Scsi_Host *shost)
-{
-	struct ata_port *ap;
-
-	ap = ata_port_alloc(host);
-	if (!ap)
-		return NULL;
-
-	ap->port_no = 0;
-	ap->lock = &host->lock;
-	ap->pio_mask = port_info->pio_mask;
-	ap->mwdma_mask = port_info->mwdma_mask;
-	ap->udma_mask = port_info->udma_mask;
-	ap->flags |= port_info->flags;
-	ap->ops = port_info->port_ops;
-	ap->cbl = ATA_CBL_SATA;
-
-	return ap;
-}
-EXPORT_SYMBOL_GPL(ata_sas_port_alloc);
-
-/**
- *	ata_sas_port_start - Set port up for dma.
- *	@ap: Port to initialize
- *
- *	Called just after data structures for each port are
- *	initialized.
- *
- *	May be used as the port_start() entry in ata_port_operations.
- *
- *	LOCKING:
- *	Inherited from caller.
- */
-int ata_sas_port_start(struct ata_port *ap)
-{
-	/*
-	 * the port is marked as frozen at allocation time, but if we don't
-	 * have new eh, we won't thaw it
-	 */
-	if (!ap->ops->error_handler)
-		ap->pflags &= ~ATA_PFLAG_FROZEN;
-	return 0;
-}
-EXPORT_SYMBOL_GPL(ata_sas_port_start);
-
-/**
- *	ata_port_stop - Undo ata_sas_port_start()
- *	@ap: Port to shut down
- *
- *	May be used as the port_stop() entry in ata_port_operations.
- *
- *	LOCKING:
- *	Inherited from caller.
- */
-
-void ata_sas_port_stop(struct ata_port *ap)
-{
-}
-EXPORT_SYMBOL_GPL(ata_sas_port_stop);
-
-/**
- * ata_sas_async_probe - simply schedule probing and return
- * @ap: Port to probe
- *
- * For batch scheduling of probe for sas attached ata devices, assumes
- * the port has already been through ata_sas_port_init()
- */
-void ata_sas_async_probe(struct ata_port *ap)
-{
-	__ata_port_probe(ap);
-}
-EXPORT_SYMBOL_GPL(ata_sas_async_probe);
-
-int ata_sas_sync_probe(struct ata_port *ap)
-{
-	return ata_port_probe(ap);
-}
-EXPORT_SYMBOL_GPL(ata_sas_sync_probe);
-
-
-/**
- *	ata_sas_port_init - Initialize a SATA device
- *	@ap: SATA port to initialize
- *
- *	LOCKING:
- *	PCI/etc. bus probe sem.
- *
- *	RETURNS:
- *	Zero on success, non-zero on error.
- */
-
-int ata_sas_port_init(struct ata_port *ap)
-{
-	int rc = ap->ops->port_start(ap);
-
-	if (rc)
-		return rc;
-	ap->print_id = atomic_inc_return(&ata_print_id);
-	return 0;
-}
-EXPORT_SYMBOL_GPL(ata_sas_port_init);
-
-int ata_sas_tport_add(struct device *parent, struct ata_port *ap)
-{
-	return ata_tport_add(parent, ap);
-}
-EXPORT_SYMBOL_GPL(ata_sas_tport_add);
-
-void ata_sas_tport_delete(struct ata_port *ap)
-{
-	ata_tport_delete(ap);
-}
-EXPORT_SYMBOL_GPL(ata_sas_tport_delete);
-
-/**
- *	ata_sas_port_destroy - Destroy a SATA port allocated by ata_sas_port_alloc
- *	@ap: SATA port to destroy
- *
- */
-
-void ata_sas_port_destroy(struct ata_port *ap)
-{
-	if (ap->ops->port_stop)
-		ap->ops->port_stop(ap);
-	kfree(ap);
-}
-EXPORT_SYMBOL_GPL(ata_sas_port_destroy);
-
-/**
- *	ata_sas_slave_configure - Default slave_config routine for libata devices
+ *	ata_sas_sdev_configure - Default sdev_configure routine for libata
+ *				   devices
  *	@sdev: SCSI device to configure
+ *	@lim: queue limits
  *	@ap: ATA port to which SCSI device is attached
  *
  *	RETURNS:
  *	Zero.
  */
 
-int ata_sas_slave_configure(struct scsi_device *sdev, struct ata_port *ap)
+int ata_sas_sdev_configure(struct scsi_device *sdev, struct queue_limits *lim,
+			   struct ata_port *ap)
 {
 	ata_scsi_sdev_config(sdev);
-	ata_scsi_dev_config(sdev, ap->link.device);
-	return 0;
+
+	return ata_scsi_dev_config(sdev, lim, ap->link.device);
 }
-EXPORT_SYMBOL_GPL(ata_sas_slave_configure);
+EXPORT_SYMBOL_GPL(ata_sas_sdev_configure);
 
 /**
  *	ata_sas_queuecmd - Issue SCSI cdb to libata-managed device
@@ -1240,43 +1380,16 @@ int ata_sas_queuecmd(struct scsi_cmnd *cmd, struct ata_port *ap)
 {
 	int rc = 0;
 
-	ata_scsi_dump_cdb(ap, cmd);
-
 	if (likely(ata_dev_enabled(ap->link.device)))
 		rc = __ata_scsi_queuecmd(cmd, ap->link.device);
 	else {
 		cmd->result = (DID_BAD_TARGET << 16);
-		cmd->scsi_done(cmd);
+		scsi_done(cmd);
 	}
 	return rc;
 }
 EXPORT_SYMBOL_GPL(ata_sas_queuecmd);
 
-int ata_sas_allocate_tag(struct ata_port *ap)
-{
-	unsigned int max_queue = ap->host->n_tags;
-	unsigned int i, tag;
-
-	for (i = 0, tag = ap->sas_last_tag + 1; i < max_queue; i++, tag++) {
-		tag = tag < max_queue ? tag : 0;
-
-		/* the last tag is reserved for internal command. */
-		if (ata_tag_internal(tag))
-			continue;
-
-		if (!test_and_set_bit(tag, &ap->sas_tag_allocated)) {
-			ap->sas_last_tag = tag;
-			return tag;
-		}
-	}
-	return -1;
-}
-
-void ata_sas_free_tag(unsigned int tag, struct ata_port *ap)
-{
-	clear_bit(tag, &ap->sas_tag_allocated);
-}
-
 /**
  *	sata_async_notification - SATA async notification handler
  *	@ap: ATA port where async notification is received
@@ -1369,7 +1482,7 @@ EXPORT_SYMBOL_GPL(sata_async_notification);
 static int ata_eh_read_log_10h(struct ata_device *dev,
 			       int *tag, struct ata_taskfile *tf)
 {
-	u8 *buf = dev->link->ap->sector_buf;
+	u8 *buf = dev->sector_buf;
 	unsigned int err_mask;
 	u8 csum;
 	int i;
@@ -1390,8 +1503,8 @@ static int ata_eh_read_log_10h(struct ata_device *dev,
 
 	*tag = buf[0] & 0x1f;
 
-	tf->command = buf[2];
-	tf->feature = buf[3];
+	tf->status = buf[2];
+	tf->error = buf[3];
 	tf->lbal = buf[4];
 	tf->lbam = buf[5];
 	tf->lbah = buf[6];
@@ -1401,13 +1514,114 @@ static int ata_eh_read_log_10h(struct ata_device *dev,
 	tf->hob_lbah = buf[10];
 	tf->nsect = buf[12];
 	tf->hob_nsect = buf[13];
-	if (dev->class == ATA_DEV_ZAC && ata_id_has_ncq_autosense(dev->id))
+	if (ata_id_has_ncq_autosense(dev->id) && (tf->status & ATA_SENSE))
 		tf->auxiliary = buf[14] << 16 | buf[15] << 8 | buf[16];
 
 	return 0;
 }
 
 /**
+ *	ata_eh_get_ncq_success_sense - Read and process the sense data for
+ *				       successful NCQ commands log page
+ *	@link: ATA link to get sense data for
+ *
+ *	Read the sense data for successful NCQ commands log page to obtain
+ *	sense data for all NCQ commands that completed successfully with
+ *	the sense data available bit set.
+ *
+ *	LOCKING:
+ *	Kernel thread context (may sleep).
+ *
+ *	RETURNS:
+ *	0 on success, -errno otherwise.
+ */
+int ata_eh_get_ncq_success_sense(struct ata_link *link)
+{
+	struct ata_device *dev = link->device;
+	struct ata_port *ap = dev->link->ap;
+	u8 *buf = dev->cdl->ncq_sense_log_buf;
+	struct ata_queued_cmd *qc;
+	unsigned int err_mask, tag;
+	u8 *sense, sk = 0, asc = 0, ascq = 0;
+	u16 extended_sense;
+	bool aux_icc_valid;
+	u32 sense_valid;
+	u64 val;
+	int ret = 0;
+
+	err_mask = ata_read_log_page(dev, ATA_LOG_SENSE_NCQ, 0, buf, 2);
+	if (err_mask) {
+		ata_dev_err(dev,
+			"Failed to read Sense Data for Successful NCQ Commands log\n");
+		return -EIO;
+	}
+
+	/* Check the log header */
+	val = get_unaligned_le64(&buf[0]);
+	if ((val & 0xffff) != 1 || ((val >> 16) & 0xff) != 0x0f) {
+		ata_dev_err(dev,
+			"Invalid Sense Data for Successful NCQ Commands log\n");
+		return -EIO;
+	}
+
+	sense_valid = get_unaligned_le32(&buf[8]);
+	extended_sense = get_unaligned_le16(&buf[14]);
+	aux_icc_valid = extended_sense & BIT(15);
+
+	ata_qc_for_each_raw(ap, qc, tag) {
+		if (!(qc->flags & ATA_QCFLAG_EH) ||
+		    !(qc->flags & ATA_QCFLAG_EH_SUCCESS_CMD) ||
+		    qc->err_mask ||
+		    ata_dev_phys_link(qc->dev) != link)
+			continue;
+
+		/*
+		 * If the command does not have any sense data, clear ATA_SENSE.
+		 * Keep ATA_QCFLAG_EH_SUCCESS_CMD so that command is finished.
+		 */
+		if (!(sense_valid & BIT(tag))) {
+			qc->result_tf.status &= ~ATA_SENSE;
+			continue;
+		}
+
+		sense = &buf[32 + 24 * tag];
+		sk = sense[0];
+		asc = sense[1];
+		ascq = sense[2];
+
+		if (!ata_scsi_sense_is_valid(sk, asc, ascq)) {
+			ret = -EIO;
+			continue;
+		}
+
+		qc->result_tf.nsect = sense[6];
+		qc->result_tf.hob_nsect = sense[7];
+		qc->result_tf.lbal = sense[8];
+		qc->result_tf.lbam = sense[9];
+		qc->result_tf.lbah = sense[10];
+		qc->result_tf.hob_lbal = sense[11];
+		qc->result_tf.hob_lbam = sense[12];
+		qc->result_tf.hob_lbah = sense[13];
+		if (aux_icc_valid)
+			qc->result_tf.auxiliary = get_unaligned_le32(&sense[16]);
+
+		/* Set sense without also setting scsicmd->result */
+		scsi_build_sense_buffer(dev->flags & ATA_DFLAG_D_SENSE,
+					qc->scsicmd->sense_buffer, sk,
+					asc, ascq);
+		qc->flags |= ATA_QCFLAG_SENSE_VALID;
+
+		/*
+		 * No point in checking the return value, since the command has
+		 * already completed successfully.
+		 */
+		ata_eh_decide_disposition(qc);
+	}
+
+	return ret;
+}
+
+/**
  *	ata_eh_analyze_ncq_error - analyze NCQ error
  *	@link: ATA link to analyze NCQ error for
  *
@@ -1429,7 +1643,7 @@ void ata_eh_analyze_ncq_error(struct ata_link *link)
 	int tag, rc;
 
 	/* if frozen, we can't do much */
-	if (ap->pflags & ATA_PFLAG_FROZEN)
+	if (ata_port_is_frozen(ap))
 		return;
 
 	/* is it NCQ device error? */
@@ -1438,7 +1652,7 @@ void ata_eh_analyze_ncq_error(struct ata_link *link)
 
 	/* has LLDD analyzed already? */
 	ata_qc_for_each_raw(ap, qc, tag) {
-		if (!(qc->flags & ATA_QCFLAG_FAILED))
+		if (!(qc->flags & ATA_QCFLAG_EH))
 			continue;
 
 		if (qc->err_mask)
@@ -1454,7 +1668,7 @@ void ata_eh_analyze_ncq_error(struct ata_link *link)
 		return;
 	}
 
-	if (!(link->sactive & (1 << tag))) {
+	if (!(link->sactive & BIT(tag))) {
 		ata_link_err(link, "log page 10h reported inactive tag %d\n",
 			     tag);
 		return;
@@ -1465,19 +1679,60 @@ void ata_eh_analyze_ncq_error(struct ata_link *link)
 	memcpy(&qc->result_tf, &tf, sizeof(tf));
 	qc->result_tf.flags = ATA_TFLAG_ISADDR | ATA_TFLAG_LBA | ATA_TFLAG_LBA48;
 	qc->err_mask |= AC_ERR_DEV | AC_ERR_NCQ;
-	if (dev->class == ATA_DEV_ZAC &&
-	    ((qc->result_tf.command & ATA_SENSE) || qc->result_tf.auxiliary)) {
+
+	/*
+	 * If the device supports NCQ autosense, ata_eh_read_log_10h() will have
+	 * stored the sense data in qc->result_tf.auxiliary.
+	 */
+	if (qc->result_tf.auxiliary) {
 		char sense_key, asc, ascq;
 
 		sense_key = (qc->result_tf.auxiliary >> 16) & 0xff;
 		asc = (qc->result_tf.auxiliary >> 8) & 0xff;
 		ascq = qc->result_tf.auxiliary & 0xff;
-		ata_scsi_set_sense(dev, qc->scsicmd, sense_key, asc, ascq);
-		ata_scsi_set_sense_information(dev, qc->scsicmd,
-					       &qc->result_tf);
-		qc->flags |= ATA_QCFLAG_SENSE_VALID;
+		if (ata_scsi_sense_is_valid(sense_key, asc, ascq)) {
+			ata_scsi_set_sense(dev, qc->scsicmd, sense_key, asc,
+					   ascq);
+			qc->flags |= ATA_QCFLAG_SENSE_VALID;
+		}
+	}
+
+	ata_qc_for_each_raw(ap, qc, tag) {
+		if (!(qc->flags & ATA_QCFLAG_EH) ||
+		    qc->flags & ATA_QCFLAG_EH_SUCCESS_CMD ||
+		    ata_dev_phys_link(qc->dev) != link)
+			continue;
+
+		/* Skip the single QC which caused the NCQ error. */
+		if (qc->err_mask)
+			continue;
+
+		/*
+		 * For SATA, the STATUS and ERROR fields are shared for all NCQ
+		 * commands that were completed with the same SDB FIS.
+		 * Therefore, we have to clear the ATA_ERR bit for all QCs
+		 * except the one that caused the NCQ error.
+		 */
+		qc->result_tf.status &= ~ATA_ERR;
+		qc->result_tf.error = 0;
+
+		/*
+		 * If we get a NCQ error, that means that a single command was
+		 * aborted. All other failed commands for our link should be
+		 * retried and has no business of going though further scrutiny
+		 * by ata_eh_link_autopsy().
+		 */
+		qc->flags |= ATA_QCFLAG_RETRY;
 	}
 
 	ehc->i.err_mask &= ~AC_ERR_DEV;
 }
 EXPORT_SYMBOL_GPL(ata_eh_analyze_ncq_error);
+
+const struct ata_port_operations sata_port_ops = {
+	.inherits		= &ata_base_port_ops,
+
+	.qc_defer		= ata_std_qc_defer,
+	.reset.hardreset	= sata_std_hardreset,
+};
+EXPORT_SYMBOL_GPL(sata_port_ops);
diff --git a/drivers/ata/libata-scsi.c b/drivers/ata/libata-scsi.c
index 36e588d88b95..721d3f270c8e 100644
--- a/drivers/ata/libata-scsi.c
+++ b/drivers/ata/libata-scsi.c
@@ -30,14 +30,14 @@
 #include <linux/hdreg.h>
 #include <linux/uaccess.h>
 #include <linux/suspend.h>
-#include <asm/unaligned.h>
+#include <linux/unaligned.h>
 #include <linux/ioprio.h>
 #include <linux/of.h>
 
 #include "libata.h"
 #include "libata-transport.h"
 
-#define ATA_SCSI_RBUF_SIZE	576
+#define ATA_SCSI_RBUF_SIZE	2048
 
 static DEFINE_SPINLOCK(ata_scsi_rbuf_lock);
 static u8 ata_scsi_rbuf[ATA_SCSI_RBUF_SIZE];
@@ -47,15 +47,19 @@ typedef unsigned int (*ata_xlat_func_t)(struct ata_queued_cmd *qc);
 static struct ata_device *__ata_scsi_find_dev(struct ata_port *ap,
 					const struct scsi_device *scsidev);
 
-#define RW_RECOVERY_MPAGE 0x1
-#define RW_RECOVERY_MPAGE_LEN 12
-#define CACHE_MPAGE 0x8
-#define CACHE_MPAGE_LEN 20
-#define CONTROL_MPAGE 0xa
-#define CONTROL_MPAGE_LEN 12
-#define ALL_MPAGES 0x3f
-#define ALL_SUB_MPAGES 0xff
-
+#define RW_RECOVERY_MPAGE		0x1
+#define RW_RECOVERY_MPAGE_LEN		12
+#define CACHE_MPAGE			0x8
+#define CACHE_MPAGE_LEN			20
+#define CONTROL_MPAGE			0xa
+#define CONTROL_MPAGE_LEN		12
+#define ALL_MPAGES			0x3f
+#define ALL_SUB_MPAGES			0xff
+#define CDL_T2A_SUB_MPAGE		0x07
+#define CDL_T2B_SUB_MPAGE		0x08
+#define CDL_T2_SUB_MPAGE_LEN		232
+#define ATA_FEATURE_SUB_MPAGE		0xf2
+#define ATA_FEATURE_SUB_MPAGE_LEN	16
 
 static const u8 def_rw_recovery_mpage[RW_RECOVERY_MPAGE_LEN] = {
 	RW_RECOVERY_MPAGE,
@@ -93,7 +97,7 @@ static ssize_t ata_scsi_park_show(struct device *device,
 	struct ata_link *link;
 	struct ata_device *dev;
 	unsigned long now;
-	unsigned int uninitialized_var(msecs);
+	unsigned int msecs;
 	int rc = 0;
 
 	ap = ata_shost_to_port(sdev->host);
@@ -121,7 +125,7 @@ static ssize_t ata_scsi_park_show(struct device *device,
 unlock:
 	spin_unlock_irq(ap->lock);
 
-	return rc ? rc : snprintf(buf, 20, "%u\n", msecs);
+	return rc ? rc : sysfs_emit(buf, "%u\n", msecs);
 }
 
 static ssize_t ata_scsi_park_store(struct device *device,
@@ -131,11 +135,11 @@ static ssize_t ata_scsi_park_store(struct device *device,
 	struct scsi_device *sdev = to_scsi_device(device);
 	struct ata_port *ap;
 	struct ata_device *dev;
-	long int input;
+	int input;
 	unsigned long flags;
 	int rc;
 
-	rc = kstrtol(buf, 10, &input);
+	rc = kstrtoint(buf, 10, &input);
 	if (rc)
 		return rc;
 	if (input < -2)
@@ -188,36 +192,129 @@ DEVICE_ATTR(unload_heads, S_IRUGO | S_IWUSR,
 	    ata_scsi_park_show, ata_scsi_park_store);
 EXPORT_SYMBOL_GPL(dev_attr_unload_heads);
 
+bool ata_scsi_sense_is_valid(u8 sk, u8 asc, u8 ascq)
+{
+	/*
+	 * If sk == NO_SENSE, and asc + ascq == NO ADDITIONAL SENSE INFORMATION,
+	 * then there is no sense data to add.
+	 */
+	if (sk == 0 && asc == 0 && ascq == 0)
+		return false;
+
+	/* If sk > COMPLETED, sense data is bogus. */
+	if (sk > COMPLETED)
+		return false;
+
+	return true;
+}
+
 void ata_scsi_set_sense(struct ata_device *dev, struct scsi_cmnd *cmd,
 			u8 sk, u8 asc, u8 ascq)
 {
 	bool d_sense = (dev->flags & ATA_DFLAG_D_SENSE);
 
-	if (!cmd)
-		return;
-
-	cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION;
-
-	scsi_build_sense_buffer(d_sense, cmd->sense_buffer, sk, asc, ascq);
+	scsi_build_sense(cmd, d_sense, sk, asc, ascq);
 }
 
-void ata_scsi_set_sense_information(struct ata_device *dev,
-				    struct scsi_cmnd *cmd,
-				    const struct ata_taskfile *tf)
+static void ata_scsi_set_sense_information(struct ata_queued_cmd *qc)
 {
 	u64 information;
 
-	if (!cmd)
+	if (!(qc->flags & ATA_QCFLAG_RTF_FILLED)) {
+		ata_dev_dbg(qc->dev,
+			    "missing result TF: can't set INFORMATION sense field\n");
 		return;
+	}
 
-	information = ata_tf_read_block(tf, dev);
+	information = ata_tf_read_block(&qc->result_tf, qc->dev);
 	if (information == U64_MAX)
 		return;
 
-	scsi_set_sense_information(cmd->sense_buffer,
+	scsi_set_sense_information(qc->scsicmd->sense_buffer,
 				   SCSI_SENSE_BUFFERSIZE, information);
 }
 
+/**
+ *	ata_scsi_set_passthru_sense_fields - Set ATA fields in sense buffer
+ *	@qc: ATA PASS-THROUGH command.
+ *
+ *	Populates "ATA Status Return sense data descriptor" / "Fixed format
+ *	sense data" with ATA taskfile fields.
+ *
+ *	LOCKING:
+ *	None.
+ */
+static void ata_scsi_set_passthru_sense_fields(struct ata_queued_cmd *qc)
+{
+	struct ata_device *dev = qc->dev;
+	struct scsi_cmnd *cmd = qc->scsicmd;
+	struct ata_taskfile *tf = &qc->result_tf;
+	unsigned char *sb = cmd->sense_buffer;
+
+	if (!(qc->flags & ATA_QCFLAG_RTF_FILLED)) {
+		ata_dev_dbg(dev,
+			    "missing result TF: can't set ATA PT sense fields\n");
+		return;
+	}
+
+	if ((sb[0] & 0x7f) >= 0x72) {
+		unsigned char *desc;
+		u8 len;
+
+		/* descriptor format */
+		len = sb[7];
+		desc = (char *)scsi_sense_desc_find(sb, len + 8, 9);
+		if (!desc) {
+			if (SCSI_SENSE_BUFFERSIZE < len + 14)
+				return;
+			sb[7] = len + 14;
+			desc = sb + 8 + len;
+		}
+		desc[0] = 9;
+		desc[1] = 12;
+		/*
+		 * Copy registers into sense buffer.
+		 */
+		desc[2] = 0x00;
+		desc[3] = tf->error;
+		desc[5] = tf->nsect;
+		desc[7] = tf->lbal;
+		desc[9] = tf->lbam;
+		desc[11] = tf->lbah;
+		desc[12] = tf->device;
+		desc[13] = tf->status;
+
+		/*
+		 * Fill in Extend bit, and the high order bytes
+		 * if applicable.
+		 */
+		if (tf->flags & ATA_TFLAG_LBA48) {
+			desc[2] |= 0x01;
+			desc[4] = tf->hob_nsect;
+			desc[6] = tf->hob_lbal;
+			desc[8] = tf->hob_lbam;
+			desc[10] = tf->hob_lbah;
+		}
+	} else {
+		/* Fixed sense format */
+		sb[0] |= 0x80;
+		sb[3] = tf->error;
+		sb[4] = tf->status;
+		sb[5] = tf->device;
+		sb[6] = tf->nsect;
+		if (tf->flags & ATA_TFLAG_LBA48)  {
+			sb[8] |= 0x80;
+			if (tf->hob_nsect)
+				sb[8] |= 0x40;
+			if (tf->hob_lbal || tf->hob_lbam || tf->hob_lbah)
+				sb[8] |= 0x20;
+		}
+		sb[9] = tf->lbal;
+		sb[10] = tf->lbam;
+		sb[11] = tf->lbah;
+	}
+}
+
 static void ata_scsi_set_invalid_field(struct ata_device *dev,
 				       struct scsi_cmnd *cmd, u16 field, u8 bit)
 {
@@ -236,16 +333,25 @@ static void ata_scsi_set_invalid_parameter(struct ata_device *dev,
 				     field, 0xff, 0);
 }
 
-struct device_attribute *ata_common_sdev_attrs[] = {
-	&dev_attr_unload_heads,
+static struct attribute *ata_common_sdev_attrs[] = {
+	&dev_attr_unload_heads.attr,
+	NULL
+};
+
+static const struct attribute_group ata_common_sdev_attr_group = {
+	.attrs = ata_common_sdev_attrs
+};
+
+const struct attribute_group *ata_common_sdev_groups[] = {
+	&ata_common_sdev_attr_group,
 	NULL
 };
-EXPORT_SYMBOL_GPL(ata_common_sdev_attrs);
+EXPORT_SYMBOL_GPL(ata_common_sdev_groups);
 
 /**
  *	ata_std_bios_param - generic bios head/sector/cylinder calculator used by sd.
  *	@sdev: SCSI device for which BIOS geometry is to be determined
- *	@bdev: block device associated with @sdev
+ *	@unused: gendisk associated with @sdev
  *	@capacity: capacity of SCSI device
  *	@geom: location to which geometry will be output
  *
@@ -260,7 +366,7 @@ EXPORT_SYMBOL_GPL(ata_common_sdev_attrs);
  *	RETURNS:
  *	Zero.
  */
-int ata_std_bios_param(struct scsi_device *sdev, struct block_device *bdev,
+int ata_std_bios_param(struct scsi_device *sdev, struct gendisk *unused,
 		       sector_t capacity, int geom[])
 {
 	geom[0] = 255;
@@ -360,8 +466,12 @@ int ata_cmd_ioctl(struct scsi_device *scsidev, void __user *arg)
 	u8 scsi_cmd[MAX_COMMAND_SIZE];
 	u8 args[4], *argbuf = NULL;
 	int argsize = 0;
-	enum dma_data_direction data_dir;
 	struct scsi_sense_hdr sshdr;
+	const struct scsi_exec_args exec_args = {
+		.sshdr = &sshdr,
+		.sense = sensebuf,
+		.sense_len = sizeof(sensebuf),
+	};
 	int cmd_result;
 
 	if (arg == NULL)
@@ -384,11 +494,9 @@ int ata_cmd_ioctl(struct scsi_device *scsidev, void __user *arg)
 		scsi_cmd[1]  = (4 << 1); /* PIO Data-in */
 		scsi_cmd[2]  = 0x0e;     /* no off.line or cc, read from dev,
 					    block count in sector count field */
-		data_dir = DMA_FROM_DEVICE;
 	} else {
 		scsi_cmd[1]  = (3 << 1); /* Non-data */
 		scsi_cmd[2]  = 0x20;     /* cc but no off.line or data xfer */
-		data_dir = DMA_NONE;
 	}
 
 	scsi_cmd[0] = ATA_16;
@@ -406,16 +514,18 @@ int ata_cmd_ioctl(struct scsi_device *scsidev, void __user *arg)
 
 	/* Good values for timeout and retries?  Values below
 	   from scsi_ioctl_send_command() for default case... */
-	cmd_result = scsi_execute(scsidev, scsi_cmd, data_dir, argbuf, argsize,
-				  sensebuf, &sshdr, (10*HZ), 5, 0, 0, NULL);
-
-	if (driver_byte(cmd_result) == DRIVER_SENSE) {/* sense data available */
+	cmd_result = scsi_execute_cmd(scsidev, scsi_cmd, REQ_OP_DRV_IN, argbuf,
+				      argsize, 10 * HZ, 5, &exec_args);
+	if (cmd_result < 0) {
+		rc = cmd_result;
+		goto error;
+	}
+	if (scsi_sense_valid(&sshdr)) {/* sense data available */
 		u8 *desc = sensebuf + 8;
-		cmd_result &= ~(0xFF<<24); /* DRIVER_SENSE is not an error */
 
 		/* If we set cc then ATA pass-through will cause a
 		 * check condition even if no error. Filter that. */
-		if (cmd_result & SAM_STAT_CHECK_CONDITION) {
+		if (scsi_status_is_check_condition(cmd_result)) {
 			if (sshdr.sense_key == RECOVERED_ERROR &&
 			    sshdr.asc == 0 && sshdr.ascq == 0x1d)
 				cmd_result &= ~SAM_STAT_CHECK_CONDITION;
@@ -465,6 +575,11 @@ int ata_task_ioctl(struct scsi_device *scsidev, void __user *arg)
 	u8 args[7];
 	struct scsi_sense_hdr sshdr;
 	int cmd_result;
+	const struct scsi_exec_args exec_args = {
+		.sshdr = &sshdr,
+		.sense = sensebuf,
+		.sense_len = sizeof(sensebuf),
+	};
 
 	if (arg == NULL)
 		return -EINVAL;
@@ -487,12 +602,14 @@ int ata_task_ioctl(struct scsi_device *scsidev, void __user *arg)
 
 	/* Good values for timeout and retries?  Values below
 	   from scsi_ioctl_send_command() for default case... */
-	cmd_result = scsi_execute(scsidev, scsi_cmd, DMA_NONE, NULL, 0,
-				sensebuf, &sshdr, (10*HZ), 5, 0, 0, NULL);
-
-	if (driver_byte(cmd_result) == DRIVER_SENSE) {/* sense data available */
+	cmd_result = scsi_execute_cmd(scsidev, scsi_cmd, REQ_OP_DRV_IN, NULL,
+				      0, 10 * HZ, 5, &exec_args);
+	if (cmd_result < 0) {
+		rc = cmd_result;
+		goto error;
+	}
+	if (scsi_sense_valid(&sshdr)) {/* sense data available */
 		u8 *desc = sensebuf + 8;
-		cmd_result &= ~(0xFF<<24); /* DRIVER_SENSE is not an error */
 
 		/* If we set cc then ATA pass-through will cause a
 		 * check condition even if no error. Filter that. */
@@ -526,13 +643,13 @@ int ata_task_ioctl(struct scsi_device *scsidev, void __user *arg)
 	return rc;
 }
 
-static int ata_ioc32(struct ata_port *ap)
+static bool ata_ioc32(struct ata_port *ap)
 {
 	if (ap->flags & ATA_FLAG_PIO_DMA)
-		return 1;
+		return true;
 	if (ap->pflags & ATA_PFLAG_PIO32)
-		return 1;
-	return 0;
+		return true;
+	return false;
 }
 
 /*
@@ -625,89 +742,65 @@ EXPORT_SYMBOL_GPL(ata_scsi_ioctl);
 static struct ata_queued_cmd *ata_scsi_qc_new(struct ata_device *dev,
 					      struct scsi_cmnd *cmd)
 {
+	struct ata_port *ap = dev->link->ap;
 	struct ata_queued_cmd *qc;
+	int tag;
 
-	qc = ata_qc_new_init(dev, cmd->request->tag);
-	if (qc) {
-		qc->scsicmd = cmd;
-		qc->scsidone = cmd->scsi_done;
-
-		qc->sg = scsi_sglist(cmd);
-		qc->n_elem = scsi_sg_count(cmd);
+	if (unlikely(ata_port_is_frozen(ap)))
+		goto fail;
 
-		if (cmd->request->rq_flags & RQF_QUIET)
-			qc->flags |= ATA_QCFLAG_QUIET;
+	if (ap->flags & ATA_FLAG_SAS_HOST) {
+		/*
+		 * SAS hosts may queue > ATA_MAX_QUEUE commands so use
+		 * unique per-device budget token as a tag.
+		 */
+		if (WARN_ON_ONCE(cmd->budget_token >= ATA_MAX_QUEUE))
+			goto fail;
+		tag = cmd->budget_token;
 	} else {
-		cmd->result = (DID_OK << 16) | (QUEUE_FULL << 1);
-		cmd->scsi_done(cmd);
+		tag = scsi_cmd_to_rq(cmd)->tag;
 	}
 
+	qc = __ata_qc_from_tag(ap, tag);
+	qc->tag = qc->hw_tag = tag;
+	qc->ap = ap;
+	qc->dev = dev;
+
+	ata_qc_reinit(qc);
+
+	qc->scsicmd = cmd;
+	qc->scsidone = scsi_done;
+
+	qc->sg = scsi_sglist(cmd);
+	qc->n_elem = scsi_sg_count(cmd);
+
+	if (scsi_cmd_to_rq(cmd)->rq_flags & RQF_QUIET)
+		qc->flags |= ATA_QCFLAG_QUIET;
+
 	return qc;
+
+fail:
+	set_host_byte(cmd, DID_OK);
+	set_status_byte(cmd, SAM_STAT_TASK_SET_FULL);
+	scsi_done(cmd);
+	return NULL;
 }
 
 static void ata_qc_set_pc_nbytes(struct ata_queued_cmd *qc)
 {
 	struct scsi_cmnd *scmd = qc->scsicmd;
 
-	qc->extrabytes = scmd->request->extra_len;
+	qc->extrabytes = scmd->extra_len;
 	qc->nbytes = scsi_bufflen(scmd) + qc->extrabytes;
 }
 
 /**
- *	ata_dump_status - user friendly display of error info
- *	@id: id of the port in question
- *	@tf: ptr to filled out taskfile
- *
- *	Decode and dump the ATA error/status registers for the user so
- *	that they have some idea what really happened at the non
- *	make-believe layer.
- *
- *	LOCKING:
- *	inherited from caller
- */
-static void ata_dump_status(unsigned id, struct ata_taskfile *tf)
-{
-	u8 stat = tf->command, err = tf->feature;
-
-	pr_warn("ata%u: status=0x%02x { ", id, stat);
-	if (stat & ATA_BUSY) {
-		pr_cont("Busy }\n");	/* Data is not valid in this case */
-	} else {
-		if (stat & ATA_DRDY)	pr_cont("DriveReady ");
-		if (stat & ATA_DF)	pr_cont("DeviceFault ");
-		if (stat & ATA_DSC)	pr_cont("SeekComplete ");
-		if (stat & ATA_DRQ)	pr_cont("DataRequest ");
-		if (stat & ATA_CORR)	pr_cont("CorrectedError ");
-		if (stat & ATA_SENSE)	pr_cont("Sense ");
-		if (stat & ATA_ERR)	pr_cont("Error ");
-		pr_cont("}\n");
-
-		if (err) {
-			pr_warn("ata%u: error=0x%02x { ", id, err);
-			if (err & ATA_ABORTED)	pr_cont("DriveStatusError ");
-			if (err & ATA_ICRC) {
-				if (err & ATA_ABORTED)
-						pr_cont("BadCRC ");
-				else		pr_cont("Sector ");
-			}
-			if (err & ATA_UNC)	pr_cont("UncorrectableError ");
-			if (err & ATA_IDNF)	pr_cont("SectorIdNotFound ");
-			if (err & ATA_TRK0NF)	pr_cont("TrackZeroNotFound ");
-			if (err & ATA_AMNF)	pr_cont("AddrMarkNotFound ");
-			pr_cont("}\n");
-		}
-	}
-}
-
-/**
  *	ata_to_sense_error - convert ATA error to SCSI error
- *	@id: ATA device number
  *	@drv_stat: value contained in ATA status register
  *	@drv_err: value contained in ATA error register
  *	@sk: the sense key we'll fill out
  *	@asc: the additional sense code we'll fill out
  *	@ascq: the additional sense code qualifier we'll fill out
- *	@verbose: be verbose
  *
  *	Converts an ATA error into a SCSI error.  Fill out pointers to
  *	SK, ASC, and ASCQ bytes for later use in fixed or descriptor
@@ -716,8 +809,8 @@ static void ata_dump_status(unsigned id, struct ata_taskfile *tf)
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  */
-static void ata_to_sense_error(unsigned id, u8 drv_stat, u8 drv_err, u8 *sk,
-			       u8 *asc, u8 *ascq, int verbose)
+static void ata_to_sense_error(u8 drv_stat, u8 drv_err, u8 *sk, u8 *asc,
+			       u8 *ascq)
 {
 	int i;
 
@@ -766,18 +859,14 @@ static void ata_to_sense_error(unsigned id, u8 drv_stat, u8 drv_err, u8 *sk,
 		{0xFF, 0xFF, 0xFF, 0xFF}, // END mark
 	};
 	static const unsigned char stat_table[][4] = {
-		/* Must be first because BUSY means no other bits valid */
-		{0x80,		ABORTED_COMMAND, 0x47, 0x00},
-		// Busy, fake parity for now
-		{0x40,		ILLEGAL_REQUEST, 0x21, 0x04},
-		// Device ready, unaligned write command
-		{0x20,		HARDWARE_ERROR,  0x44, 0x00},
-		// Device fault, internal target failure
-		{0x08,		ABORTED_COMMAND, 0x47, 0x00},
-		// Timed out in xfer, fake parity for now
-		{0x04,		RECOVERED_ERROR, 0x11, 0x00},
-		// Recovered ECC error	  Medium error, recovered
-		{0xFF, 0xFF, 0xFF, 0xFF}, // END mark
+		/* Busy: must be first because BUSY means no other bits valid */
+		{ ATA_BUSY,	ABORTED_COMMAND, 0x00, 0x00 },
+		/* Device fault: INTERNAL TARGET FAILURE */
+		{ ATA_DF,	HARDWARE_ERROR,  0x44, 0x00 },
+		/* Corrected data error */
+		{ ATA_CORR,	RECOVERED_ERROR, 0x00, 0x00 },
+
+		{ 0xFF, 0xFF, 0xFF, 0xFF }, /* END mark */
 	};
 
 	/*
@@ -796,7 +885,7 @@ static void ata_to_sense_error(unsigned id, u8 drv_stat, u8 drv_err, u8 *sk,
 				*sk = sense_table[i][1];
 				*asc = sense_table[i][2];
 				*ascq = sense_table[i][3];
-				goto translate_done;
+				return;
 			}
 		}
 	}
@@ -811,7 +900,7 @@ static void ata_to_sense_error(unsigned id, u8 drv_stat, u8 drv_err, u8 *sk,
 			*sk = stat_table[i][1];
 			*asc = stat_table[i][2];
 			*ascq = stat_table[i][3];
-			goto translate_done;
+			return;
 		}
 	}
 
@@ -822,22 +911,14 @@ static void ata_to_sense_error(unsigned id, u8 drv_stat, u8 drv_err, u8 *sk,
 	*sk = ABORTED_COMMAND;
 	*asc = 0x00;
 	*ascq = 0x00;
-
- translate_done:
-	if (verbose)
-		pr_err("ata%u: translated ATA stat/err 0x%02x/%02x to SCSI SK/ASC/ASCQ 0x%x/%02x/%02x\n",
-		       id, drv_stat, drv_err, *sk, *asc, *ascq);
-	return;
 }
 
 /*
  *	ata_gen_passthru_sense - Generate check condition sense block.
  *	@qc: Command that completed.
  *
- *	This function is specific to the ATA descriptor format sense
- *	block specified for the ATA pass through commands.  Regardless
- *	of whether the command errored or not, return a sense
- *	block. Copy all controller registers into the sense
+ *	This function is specific to the ATA pass through commands.
+ *	Regardless of whether the command errored or not, return a sense
  *	block. If there was no error, we get the request from an ATA
  *	passthrough command, so we use the following sense data:
  *	sk = RECOVERED ERROR
@@ -849,89 +930,42 @@ static void ata_to_sense_error(unsigned id, u8 drv_stat, u8 drv_err, u8 *sk,
  */
 static void ata_gen_passthru_sense(struct ata_queued_cmd *qc)
 {
+	struct ata_device *dev = qc->dev;
 	struct scsi_cmnd *cmd = qc->scsicmd;
 	struct ata_taskfile *tf = &qc->result_tf;
-	unsigned char *sb = cmd->sense_buffer;
-	unsigned char *desc = sb + 8;
-	int verbose = qc->ap->ops->error_handler == NULL;
 	u8 sense_key, asc, ascq;
 
-	memset(sb, 0, SCSI_SENSE_BUFFERSIZE);
-
-	cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION;
+	if (!(qc->flags & ATA_QCFLAG_RTF_FILLED)) {
+		ata_dev_dbg(dev,
+			    "missing result TF: can't generate ATA PT sense data\n");
+		if (qc->err_mask)
+			ata_scsi_set_sense(dev, cmd, ABORTED_COMMAND, 0, 0);
+		return;
+	}
 
 	/*
 	 * Use ata_to_sense_error() to map status register bits
 	 * onto sense key, asc & ascq.
 	 */
 	if (qc->err_mask ||
-	    tf->command & (ATA_BUSY | ATA_DF | ATA_ERR | ATA_DRQ)) {
-		ata_to_sense_error(qc->ap->print_id, tf->command, tf->feature,
-				   &sense_key, &asc, &ascq, verbose);
+	    tf->status & (ATA_BUSY | ATA_DF | ATA_ERR | ATA_DRQ)) {
+		ata_to_sense_error(tf->status, tf->error,
+				   &sense_key, &asc, &ascq);
 		ata_scsi_set_sense(qc->dev, cmd, sense_key, asc, ascq);
 	} else {
 		/*
 		 * ATA PASS-THROUGH INFORMATION AVAILABLE
-		 * Always in descriptor format sense.
-		 */
-		scsi_build_sense_buffer(1, cmd->sense_buffer,
-					RECOVERED_ERROR, 0, 0x1D);
-	}
-
-	if ((cmd->sense_buffer[0] & 0x7f) >= 0x72) {
-		u8 len;
-
-		/* descriptor format */
-		len = sb[7];
-		desc = (char *)scsi_sense_desc_find(sb, len + 8, 9);
-		if (!desc) {
-			if (SCSI_SENSE_BUFFERSIZE < len + 14)
-				return;
-			sb[7] = len + 14;
-			desc = sb + 8 + len;
-		}
-		desc[0] = 9;
-		desc[1] = 12;
-		/*
-		 * Copy registers into sense buffer.
-		 */
-		desc[2] = 0x00;
-		desc[3] = tf->feature;	/* == error reg */
-		desc[5] = tf->nsect;
-		desc[7] = tf->lbal;
-		desc[9] = tf->lbam;
-		desc[11] = tf->lbah;
-		desc[12] = tf->device;
-		desc[13] = tf->command; /* == status reg */
-
-		/*
-		 * Fill in Extend bit, and the high order bytes
-		 * if applicable.
+		 *
+		 * Note: we are supposed to call ata_scsi_set_sense(), which
+		 * respects the D_SENSE bit, instead of unconditionally
+		 * generating the sense data in descriptor format. However,
+		 * because hdparm, hddtemp, and udisks incorrectly assume sense
+		 * data in descriptor format, without even looking at the
+		 * RESPONSE CODE field in the returned sense data (to see which
+		 * format the returned sense data is in), we are stuck with
+		 * being bug compatible with older kernels.
 		 */
-		if (tf->flags & ATA_TFLAG_LBA48) {
-			desc[2] |= 0x01;
-			desc[4] = tf->hob_nsect;
-			desc[6] = tf->hob_lbal;
-			desc[8] = tf->hob_lbam;
-			desc[10] = tf->hob_lbah;
-		}
-	} else {
-		/* Fixed sense format */
-		desc[0] = tf->feature;
-		desc[1] = tf->command; /* status */
-		desc[2] = tf->device;
-		desc[3] = tf->nsect;
-		desc[7] = 0;
-		if (tf->flags & ATA_TFLAG_LBA48)  {
-			desc[8] |= 0x80;
-			if (tf->hob_nsect)
-				desc[8] |= 0x40;
-			if (tf->hob_lbal || tf->hob_lbam || tf->hob_lbah)
-				desc[8] |= 0x20;
-		}
-		desc[9] = tf->lbal;
-		desc[10] = tf->lbam;
-		desc[11] = tf->lbah;
+		scsi_build_sense(cmd, 1, RECOVERED_ERROR, 0, 0x1D);
 	}
 }
 
@@ -939,8 +973,7 @@ static void ata_gen_passthru_sense(struct ata_queued_cmd *qc)
  *	ata_gen_ata_sense - generate a SCSI fixed sense block
  *	@qc: Command that we are erroring out
  *
- *	Generate sense block for a failed ATA command @qc.  Descriptor
- *	format is used to accommodate LBA48 block address.
+ *	Generate sense block for a failed ATA command @qc.
  *
  *	LOCKING:
  *	None.
@@ -950,42 +983,45 @@ static void ata_gen_ata_sense(struct ata_queued_cmd *qc)
 	struct ata_device *dev = qc->dev;
 	struct scsi_cmnd *cmd = qc->scsicmd;
 	struct ata_taskfile *tf = &qc->result_tf;
-	unsigned char *sb = cmd->sense_buffer;
-	int verbose = qc->ap->ops->error_handler == NULL;
-	u64 block;
 	u8 sense_key, asc, ascq;
 
-	memset(sb, 0, SCSI_SENSE_BUFFERSIZE);
-
-	cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION;
-
 	if (ata_dev_disabled(dev)) {
 		/* Device disabled after error recovery */
 		/* LOGICAL UNIT NOT READY, HARD RESET REQUIRED */
 		ata_scsi_set_sense(dev, cmd, NOT_READY, 0x04, 0x21);
 		return;
 	}
+
+	if (ata_id_is_locked(dev->id)) {
+		/* Security locked */
+		/* LOGICAL UNIT ACCESS NOT AUTHORIZED */
+		ata_scsi_set_sense(dev, cmd, DATA_PROTECT, 0x74, 0x71);
+		return;
+	}
+
+	if (!(qc->flags & ATA_QCFLAG_RTF_FILLED)) {
+		ata_dev_dbg(dev,
+			    "Missing result TF: reporting aborted command\n");
+		goto aborted;
+	}
+
 	/* Use ata_to_sense_error() to map status register bits
 	 * onto sense key, asc & ascq.
 	 */
 	if (qc->err_mask ||
-	    tf->command & (ATA_BUSY | ATA_DF | ATA_ERR | ATA_DRQ)) {
-		ata_to_sense_error(qc->ap->print_id, tf->command, tf->feature,
-				   &sense_key, &asc, &ascq, verbose);
+	    tf->status & (ATA_BUSY | ATA_DF | ATA_ERR | ATA_DRQ)) {
+		ata_to_sense_error(tf->status, tf->error,
+				   &sense_key, &asc, &ascq);
 		ata_scsi_set_sense(dev, cmd, sense_key, asc, ascq);
-	} else {
-		/* Could not decode error */
-		ata_dev_warn(dev, "could not decode error status 0x%x err_mask 0x%x\n",
-			     tf->command, qc->err_mask);
-		ata_scsi_set_sense(dev, cmd, ABORTED_COMMAND, 0, 0);
 		return;
 	}
 
-	block = ata_tf_read_block(&qc->result_tf, dev);
-	if (block == U64_MAX)
-		return;
-
-	scsi_set_sense_information(sb, SCSI_SENSE_BUFFERSIZE, block);
+	/* Could not decode error */
+	ata_dev_warn(dev,
+		"Could not decode error 0x%x, status 0x%x (err_mask=0x%x)\n",
+		tf->error, tf->status, qc->err_mask);
+aborted:
+	ata_scsi_set_sense(dev, cmd, ABORTED_COMMAND, 0, 0);
 }
 
 void ata_scsi_sdev_config(struct scsi_device *sdev)
@@ -1003,7 +1039,7 @@ void ata_scsi_sdev_config(struct scsi_device *sdev)
 }
 
 /**
- *	atapi_drain_needed - Check whether data transfer may overflow
+ *	ata_scsi_dma_need_drain - Check whether data transfer may overflow
  *	@rq: request to be checked
  *
  *	ATAPI commands which transfer variable length data to host
@@ -1017,46 +1053,57 @@ void ata_scsi_sdev_config(struct scsi_device *sdev)
  *	RETURNS:
  *	1 if ; otherwise, 0.
  */
-static int atapi_drain_needed(struct request *rq)
+bool ata_scsi_dma_need_drain(struct request *rq)
 {
-	if (likely(!blk_rq_is_passthrough(rq)))
-		return 0;
+	struct scsi_cmnd *scmd = blk_mq_rq_to_pdu(rq);
 
-	if (!blk_rq_bytes(rq) || op_is_write(req_op(rq)))
-		return 0;
-
-	return atapi_cmd_type(scsi_req(rq)->cmd[0]) == ATAPI_MISC;
+	return atapi_cmd_type(scmd->cmnd[0]) == ATAPI_MISC;
 }
+EXPORT_SYMBOL_GPL(ata_scsi_dma_need_drain);
 
-int ata_scsi_dev_config(struct scsi_device *sdev, struct ata_device *dev)
+int ata_scsi_dev_config(struct scsi_device *sdev, struct queue_limits *lim,
+		struct ata_device *dev)
 {
-	struct request_queue *q = sdev->request_queue;
+	int depth = 1;
 
 	if (!ata_id_has_unload(dev->id))
 		dev->flags |= ATA_DFLAG_NO_UNLOAD;
 
 	/* configure max sectors */
-	blk_queue_max_hw_sectors(q, dev->max_sectors);
+	dev->max_sectors = min(dev->max_sectors, sdev->host->max_sectors);
+	lim->max_hw_sectors = dev->max_sectors;
 
 	if (dev->class == ATA_DEV_ATAPI) {
-		void *buf;
-
 		sdev->sector_size = ATA_SECT_SIZE;
 
 		/* set DMA padding */
-		blk_queue_update_dma_pad(q, ATA_DMA_PAD_SZ - 1);
+		lim->dma_pad_mask = ATA_DMA_PAD_SZ - 1;
 
-		/* configure draining */
-		buf = kmalloc(ATAPI_MAX_DRAIN, q->bounce_gfp | GFP_KERNEL);
-		if (!buf) {
+		/* make room for appending the drain */
+		lim->max_segments--;
+
+		sdev->dma_drain_len = ATAPI_MAX_DRAIN;
+		sdev->dma_drain_buf = kmalloc(sdev->dma_drain_len, GFP_NOIO);
+		if (!sdev->dma_drain_buf) {
 			ata_dev_err(dev, "drain buffer allocation failed\n");
 			return -ENOMEM;
 		}
-
-		blk_queue_dma_drain(q, atapi_drain_needed, buf, ATAPI_MAX_DRAIN);
 	} else {
 		sdev->sector_size = ata_id_logical_sector_size(dev->id);
-		sdev->manage_start_stop = 1;
+
+		/*
+		 * Ask the sd driver to issue START STOP UNIT on runtime suspend
+		 * and resume and shutdown only. For system level suspend/resume,
+		 * devices power state is handled directly by libata EH.
+		 * Given that disks are always spun up on system resume, also
+		 * make sure that the sd driver forces runtime suspended disks
+		 * to be resumed to correctly reflect the power state of the
+		 * device.
+		 */
+		sdev->manage_runtime_start_stop = 1;
+		sdev->manage_shutdown = 1;
+		sdev->manage_restart = ata_acpi_dev_manage_restart(dev);
+		sdev->force_runtime_start_on_system_start = 1;
 	}
 
 	/*
@@ -1071,18 +1118,15 @@ int ata_scsi_dev_config(struct scsi_device *sdev, struct ata_device *dev)
 			"sector_size=%u > PAGE_SIZE, PIO may malfunction\n",
 			sdev->sector_size);
 
-	blk_queue_update_dma_alignment(q, sdev->sector_size - 1);
+	lim->dma_alignment = sdev->sector_size - 1;
 
 	if (dev->flags & ATA_DFLAG_AN)
 		set_bit(SDEV_EVT_MEDIA_CHANGE, sdev->supported_events);
 
-	if (dev->flags & ATA_DFLAG_NCQ) {
-		int depth;
-
+	if (ata_ncq_supported(dev))
 		depth = min(sdev->host->can_queue, ata_id_queue_depth(dev->id));
-		depth = min(ATA_MAX_QUEUE, depth);
-		scsi_change_queue_depth(sdev, depth);
-	}
+	depth = min(ATA_MAX_QUEUE, depth);
+	scsi_change_queue_depth(sdev, depth);
 
 	if (dev->flags & ATA_DFLAG_TRUSTED)
 		sdev->security_supported = 1;
@@ -1092,8 +1136,45 @@ int ata_scsi_dev_config(struct scsi_device *sdev, struct ata_device *dev)
 }
 
 /**
- *	ata_scsi_slave_config - Set SCSI device attributes
+ *	ata_scsi_sdev_init - Early setup of SCSI device
+ *	@sdev: SCSI device to examine
+ *
+ *	This is called from scsi_alloc_sdev() when the scsi device
+ *	associated with an ATA device is scanned on a port.
+ *
+ *	LOCKING:
+ *	Defined by SCSI layer.  We don't really care.
+ */
+
+int ata_scsi_sdev_init(struct scsi_device *sdev)
+{
+	struct ata_port *ap = ata_shost_to_port(sdev->host);
+	struct device_link *link;
+
+	ata_scsi_sdev_config(sdev);
+
+	/*
+	 * Create a link from the ata_port device to the scsi device to ensure
+	 * that PM does suspend/resume in the correct order: the scsi device is
+	 * consumer (child) and the ata port the supplier (parent).
+	 */
+	link = device_link_add(&sdev->sdev_gendev, &ap->tdev,
+			       DL_FLAG_STATELESS |
+			       DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE);
+	if (!link) {
+		ata_port_err(ap, "Failed to create link to scsi device %s\n",
+			     dev_name(&sdev->sdev_gendev));
+		return -ENODEV;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(ata_scsi_sdev_init);
+
+/**
+ *	ata_scsi_sdev_configure - Set SCSI device attributes
  *	@sdev: SCSI device to examine
+ *	@lim: queue limits
  *
  *	This is called before we actually start reading
  *	and writing to the device, to configure certain
@@ -1103,23 +1184,20 @@ int ata_scsi_dev_config(struct scsi_device *sdev, struct ata_device *dev)
  *	Defined by SCSI layer.  We don't really care.
  */
 
-int ata_scsi_slave_config(struct scsi_device *sdev)
+int ata_scsi_sdev_configure(struct scsi_device *sdev, struct queue_limits *lim)
 {
 	struct ata_port *ap = ata_shost_to_port(sdev->host);
 	struct ata_device *dev = __ata_scsi_find_dev(ap, sdev);
-	int rc = 0;
-
-	ata_scsi_sdev_config(sdev);
 
 	if (dev)
-		rc = ata_scsi_dev_config(sdev, dev);
+		return ata_scsi_dev_config(sdev, lim, dev);
 
-	return rc;
+	return 0;
 }
-EXPORT_SYMBOL_GPL(ata_scsi_slave_config);
+EXPORT_SYMBOL_GPL(ata_scsi_sdev_configure);
 
 /**
- *	ata_scsi_slave_destroy - SCSI device is about to be destroyed
+ *	ata_scsi_sdev_destroy - SCSI device is about to be destroyed
  *	@sdev: SCSI device to be destroyed
  *
  *	@sdev is about to be destroyed for hot/warm unplugging.  If
@@ -1132,15 +1210,13 @@ EXPORT_SYMBOL_GPL(ata_scsi_slave_config);
  *	LOCKING:
  *	Defined by SCSI layer.  We don't really care.
  */
-void ata_scsi_slave_destroy(struct scsi_device *sdev)
+void ata_scsi_sdev_destroy(struct scsi_device *sdev)
 {
 	struct ata_port *ap = ata_shost_to_port(sdev->host);
-	struct request_queue *q = sdev->request_queue;
 	unsigned long flags;
 	struct ata_device *dev;
 
-	if (!ap->ops->error_handler)
-		return;
+	device_link_remove(&sdev->sdev_gendev, &ap->tdev);
 
 	spin_lock_irqsave(ap->lock, flags);
 	dev = __ata_scsi_find_dev(ap, sdev);
@@ -1152,11 +1228,9 @@ void ata_scsi_slave_destroy(struct scsi_device *sdev)
 	}
 	spin_unlock_irqrestore(ap->lock, flags);
 
-	kfree(q->dma_drain_buffer);
-	q->dma_drain_buffer = NULL;
-	q->dma_drain_size = 0;
+	kfree(sdev->dma_drain_buf);
 }
-EXPORT_SYMBOL_GPL(ata_scsi_slave_destroy);
+EXPORT_SYMBOL_GPL(ata_scsi_sdev_destroy);
 
 /**
  *	ata_scsi_start_stop_xlat - Translate SCSI START STOP UNIT command
@@ -1176,7 +1250,6 @@ EXPORT_SYMBOL_GPL(ata_scsi_slave_destroy);
 static unsigned int ata_scsi_start_stop_xlat(struct ata_queued_cmd *qc)
 {
 	struct scsi_cmnd *scmd = qc->scsicmd;
-	struct ata_taskfile *tf = &qc->tf;
 	const u8 *cdb = scmd->cmnd;
 	u16 fp;
 	u8 bp = 0xff;
@@ -1186,54 +1259,24 @@ static unsigned int ata_scsi_start_stop_xlat(struct ata_queued_cmd *qc)
 		goto invalid_fld;
 	}
 
-	tf->flags |= ATA_TFLAG_DEVICE | ATA_TFLAG_ISADDR;
-	tf->protocol = ATA_PROT_NODATA;
-	if (cdb[1] & 0x1) {
-		;	/* ignore IMMED bit, violates sat-r05 */
-	}
+	/* LOEJ bit set not supported */
 	if (cdb[4] & 0x2) {
 		fp = 4;
 		bp = 1;
-		goto invalid_fld;       /* LOEJ bit set not supported */
+		goto invalid_fld;
 	}
+
+	/* Power conditions not supported */
 	if (((cdb[4] >> 4) & 0xf) != 0) {
 		fp = 4;
 		bp = 3;
-		goto invalid_fld;       /* power conditions not supported */
+		goto invalid_fld;
 	}
 
-	if (cdb[4] & 0x1) {
-		tf->nsect = 1;	/* 1 sector, lba=0 */
-
-		if (qc->dev->flags & ATA_DFLAG_LBA) {
-			tf->flags |= ATA_TFLAG_LBA;
-
-			tf->lbah = 0x0;
-			tf->lbam = 0x0;
-			tf->lbal = 0x0;
-			tf->device |= ATA_LBA;
-		} else {
-			/* CHS */
-			tf->lbal = 0x1; /* sect */
-			tf->lbam = 0x0; /* cyl low */
-			tf->lbah = 0x0; /* cyl high */
-		}
-
-		tf->command = ATA_CMD_VERIFY;	/* READ VERIFY */
-	} else {
-		/* Some odd clown BIOSen issue spindown on power off (ACPI S4
-		 * or S5) causing some drives to spin up and down again.
-		 */
-		if ((qc->ap->flags & ATA_FLAG_NO_POWEROFF_SPINDOWN) &&
-		    system_state == SYSTEM_POWER_OFF)
-			goto skip;
-
-		if ((qc->ap->flags & ATA_FLAG_NO_HIBERNATE_SPINDOWN) &&
-		     system_entering_hibernation())
-			goto skip;
-
-		/* Issue ATA STANDBY IMMEDIATE command */
-		tf->command = ATA_CMD_STANDBYNOW1;
+	/* Ignore IMMED bit (cdb[1] & 0x1), violates sat-r05 */
+	if (!ata_dev_power_init_tf(qc->dev, &qc->tf, cdb[4] & 0x1)) {
+		ata_scsi_set_sense(qc->dev, scmd, ABORTED_COMMAND, 0, 0);
+		return 1;
 	}
 
 	/*
@@ -1248,12 +1291,8 @@ static unsigned int ata_scsi_start_stop_xlat(struct ata_queued_cmd *qc)
  invalid_fld:
 	ata_scsi_set_invalid_field(qc->dev, scmd, fp, bp);
 	return 1;
- skip:
-	scmd->result = SAM_STAT_GOOD;
-	return 1;
 }
 
-
 /**
  *	ata_scsi_flush_xlat - Translate SCSI SYNCHRONIZE CACHE command
  *	@qc: Storage for translated ATA taskfile
@@ -1297,19 +1336,8 @@ static unsigned int ata_scsi_flush_xlat(struct ata_queued_cmd *qc)
  */
 static void scsi_6_lba_len(const u8 *cdb, u64 *plba, u32 *plen)
 {
-	u64 lba = 0;
-	u32 len;
-
-	VPRINTK("six-byte command\n");
-
-	lba |= ((u64)(cdb[1] & 0x1f)) << 16;
-	lba |= ((u64)cdb[2]) << 8;
-	lba |= ((u64)cdb[3]);
-
-	len = cdb[4];
-
-	*plba = lba;
-	*plen = len;
+	*plba = get_unaligned_be24(&cdb[1]) & 0x1fffff;
+	*plen = cdb[4];
 }
 
 /**
@@ -1322,23 +1350,10 @@ static void scsi_6_lba_len(const u8 *cdb, u64 *plba, u32 *plen)
  *	@plba: the LBA
  *	@plen: the transfer length
  */
-static void scsi_10_lba_len(const u8 *cdb, u64 *plba, u32 *plen)
+static inline void scsi_10_lba_len(const u8 *cdb, u64 *plba, u32 *plen)
 {
-	u64 lba = 0;
-	u32 len = 0;
-
-	VPRINTK("ten-byte command\n");
-
-	lba |= ((u64)cdb[2]) << 24;
-	lba |= ((u64)cdb[3]) << 16;
-	lba |= ((u64)cdb[4]) << 8;
-	lba |= ((u64)cdb[5]);
-
-	len |= ((u32)cdb[7]) << 8;
-	len |= ((u32)cdb[8]);
-
-	*plba = lba;
-	*plen = len;
+	*plba = get_unaligned_be32(&cdb[2]);
+	*plen = get_unaligned_be16(&cdb[7]);
 }
 
 /**
@@ -1351,29 +1366,22 @@ static void scsi_10_lba_len(const u8 *cdb, u64 *plba, u32 *plen)
  *	@plba: the LBA
  *	@plen: the transfer length
  */
-static void scsi_16_lba_len(const u8 *cdb, u64 *plba, u32 *plen)
+static inline void scsi_16_lba_len(const u8 *cdb, u64 *plba, u32 *plen)
+{
+	*plba = get_unaligned_be64(&cdb[2]);
+	*plen = get_unaligned_be32(&cdb[10]);
+}
+
+/**
+ *	scsi_dld - Get duration limit descriptor index
+ *	@cdb: SCSI command to translate
+ *
+ *	Returns the dld bits indicating the index of a command duration limit
+ *	descriptor.
+ */
+static inline int scsi_dld(const u8 *cdb)
 {
-	u64 lba = 0;
-	u32 len = 0;
-
-	VPRINTK("sixteen-byte command\n");
-
-	lba |= ((u64)cdb[2]) << 56;
-	lba |= ((u64)cdb[3]) << 48;
-	lba |= ((u64)cdb[4]) << 40;
-	lba |= ((u64)cdb[5]) << 32;
-	lba |= ((u64)cdb[6]) << 24;
-	lba |= ((u64)cdb[7]) << 16;
-	lba |= ((u64)cdb[8]) << 8;
-	lba |= ((u64)cdb[9]);
-
-	len |= ((u32)cdb[10]) << 24;
-	len |= ((u32)cdb[11]) << 16;
-	len |= ((u32)cdb[12]) << 8;
-	len |= ((u32)cdb[13]);
-
-	*plba = lba;
-	*plen = len;
+	return ((cdb[1] & 0x01) << 2) | ((cdb[14] >> 6) & 0x03);
 }
 
 /**
@@ -1402,19 +1410,22 @@ static unsigned int ata_scsi_verify_xlat(struct ata_queued_cmd *qc)
 	tf->flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
 	tf->protocol = ATA_PROT_NODATA;
 
-	if (cdb[0] == VERIFY) {
+	switch (cdb[0]) {
+	case VERIFY:
 		if (scmd->cmd_len < 10) {
 			fp = 9;
 			goto invalid_fld;
 		}
 		scsi_10_lba_len(cdb, &block, &n_block);
-	} else if (cdb[0] == VERIFY_16) {
+		break;
+	case VERIFY_16:
 		if (scmd->cmd_len < 16) {
 			fp = 15;
 			goto invalid_fld;
 		}
 		scsi_16_lba_len(cdb, &block, &n_block);
-	} else {
+		break;
+	default:
 		fp = 0;
 		goto invalid_fld;
 	}
@@ -1470,9 +1481,6 @@ static unsigned int ata_scsi_verify_xlat(struct ata_queued_cmd *qc)
 		head  = track % dev->heads;
 		sect  = (u32)block % dev->sectors + 1;
 
-		DPRINTK("block %u track %u cyl %u head %u sect %u\n",
-			(u32)block, track, cyl, head, sect);
-
 		/* Check whether the converted CHS can fit.
 		   Cylinder: 0-65535
 		   Head: 0-15
@@ -1506,7 +1514,7 @@ nothing_to_do:
 
 static bool ata_check_nblocks(struct scsi_cmnd *scmd, u32 n_blocks)
 {
-	struct request *rq = scmd->request;
+	struct request *rq = scsi_cmd_to_rq(scmd);
 	u32 req_blocks;
 
 	if (!blk_rq_is_passthrough(rq))
@@ -1541,16 +1549,22 @@ static unsigned int ata_scsi_rw_xlat(struct ata_queued_cmd *qc)
 {
 	struct scsi_cmnd *scmd = qc->scsicmd;
 	const u8 *cdb = scmd->cmnd;
-	struct request *rq = scmd->request;
+	struct request *rq = scsi_cmd_to_rq(scmd);
 	int class = IOPRIO_PRIO_CLASS(req_get_ioprio(rq));
 	unsigned int tf_flags = 0;
+	int dld = 0;
 	u64 block;
 	u32 n_block;
 	int rc;
 	u16 fp = 0;
 
-	if (cdb[0] == WRITE_10 || cdb[0] == WRITE_6 || cdb[0] == WRITE_16)
+	switch (cdb[0]) {
+	case WRITE_6:
+	case WRITE_10:
+	case WRITE_16:
 		tf_flags |= ATA_TFLAG_WRITE;
+		break;
+	}
 
 	/* Calculate the SCSI LBA, transfer length and FUA. */
 	switch (cdb[0]) {
@@ -1589,13 +1603,13 @@ static unsigned int ata_scsi_rw_xlat(struct ata_queued_cmd *qc)
 			goto invalid_fld;
 		}
 		scsi_16_lba_len(cdb, &block, &n_block);
+		dld = scsi_dld(cdb);
 		if (cdb[1] & (1 << 3))
 			tf_flags |= ATA_TFLAG_FUA;
 		if (!ata_check_nblocks(scmd, n_block))
 			goto invalid_fld;
 		break;
 	default:
-		DPRINTK("no-byte command\n");
 		fp = 0;
 		goto invalid_fld;
 	}
@@ -1614,9 +1628,7 @@ static unsigned int ata_scsi_rw_xlat(struct ata_queued_cmd *qc)
 	qc->flags |= ATA_QCFLAG_IO;
 	qc->nbytes = n_block * scmd->device->sector_size;
 
-	rc = ata_build_rw_tf(&qc->tf, qc->dev, block, n_block, tf_flags,
-			     qc->hw_tag, class);
-
+	rc = ata_build_rw_tf(qc, block, n_block, tf_flags, dld, class);
 	if (likely(rc == 0))
 		return 0;
 
@@ -1648,32 +1660,33 @@ static void ata_qc_done(struct ata_queued_cmd *qc)
 
 static void ata_scsi_qc_complete(struct ata_queued_cmd *qc)
 {
-	struct ata_port *ap = qc->ap;
 	struct scsi_cmnd *cmd = qc->scsicmd;
 	u8 *cdb = cmd->cmnd;
-	int need_sense = (qc->err_mask != 0);
+	bool have_sense = qc->flags & ATA_QCFLAG_SENSE_VALID;
+	bool is_ata_passthru = cdb[0] == ATA_16 || cdb[0] == ATA_12;
+	bool is_ck_cond_request = cdb[2] & 0x20;
+	bool is_error = qc->err_mask != 0;
 
 	/* For ATA pass thru (SAT) commands, generate a sense block if
 	 * user mandated it or if there's an error.  Note that if we
-	 * generate because the user forced us to [CK_COND =1], a check
+	 * generate because the user forced us to [CK_COND=1], a check
 	 * condition is generated and the ATA register values are returned
 	 * whether the command completed successfully or not. If there
-	 * was no error, we use the following sense data:
+	 * was no error, and CK_COND=1, we use the following sense data:
 	 * sk = RECOVERED ERROR
 	 * asc,ascq = ATA PASS-THROUGH INFORMATION AVAILABLE
 	 */
-	if (((cdb[0] == ATA_16) || (cdb[0] == ATA_12)) &&
-	    ((cdb[2] & 0x20) || need_sense))
-		ata_gen_passthru_sense(qc);
-	else if (qc->flags & ATA_QCFLAG_SENSE_VALID)
-		cmd->result = SAM_STAT_CHECK_CONDITION;
-	else if (need_sense)
-		ata_gen_ata_sense(qc);
-	else
-		cmd->result = SAM_STAT_GOOD;
-
-	if (need_sense && !ap->ops->error_handler)
-		ata_dump_status(ap->print_id, &qc->result_tf);
+	if (is_ata_passthru && (is_ck_cond_request || is_error || have_sense)) {
+		if (!have_sense)
+			ata_gen_passthru_sense(qc);
+		ata_scsi_set_passthru_sense_fields(qc);
+		if (is_ck_cond_request)
+			set_status_byte(qc->scsicmd, SAM_STAT_CHECK_CONDITION);
+	} else if (is_error) {
+		if (!have_sense)
+			ata_gen_ata_sense(qc);
+		ata_scsi_set_sense_information(qc);
+	}
 
 	ata_qc_done(qc);
 }
@@ -1711,8 +1724,6 @@ static int ata_scsi_translate(struct ata_device *dev, struct scsi_cmnd *cmd,
 	struct ata_queued_cmd *qc;
 	int rc;
 
-	VPRINTK("ENTER\n");
-
 	qc = ata_scsi_qc_new(dev, cmd);
 	if (!qc)
 		goto err_mem;
@@ -1743,88 +1754,32 @@ static int ata_scsi_translate(struct ata_device *dev, struct scsi_cmnd *cmd,
 	/* select device, send command to hardware */
 	ata_qc_issue(qc);
 
-	VPRINTK("EXIT\n");
 	return 0;
 
 early_finish:
 	ata_qc_free(qc);
-	cmd->scsi_done(cmd);
-	DPRINTK("EXIT - early finish (good or error)\n");
+	scsi_done(cmd);
 	return 0;
 
 err_did:
 	ata_qc_free(qc);
 	cmd->result = (DID_ERROR << 16);
-	cmd->scsi_done(cmd);
+	scsi_done(cmd);
 err_mem:
-	DPRINTK("EXIT - internal\n");
 	return 0;
 
 defer:
 	ata_qc_free(qc);
-	DPRINTK("EXIT - defer\n");
 	if (rc == ATA_DEFER_LINK)
 		return SCSI_MLQUEUE_DEVICE_BUSY;
 	else
 		return SCSI_MLQUEUE_HOST_BUSY;
 }
 
-struct ata_scsi_args {
-	struct ata_device	*dev;
-	u16			*id;
-	struct scsi_cmnd	*cmd;
-};
-
-/**
- *	ata_scsi_rbuf_get - Map response buffer.
- *	@cmd: SCSI command containing buffer to be mapped.
- *	@flags: unsigned long variable to store irq enable status
- *	@copy_in: copy in from user buffer
- *
- *	Prepare buffer for simulated SCSI commands.
- *
- *	LOCKING:
- *	spin_lock_irqsave(ata_scsi_rbuf_lock) on success
- *
- *	RETURNS:
- *	Pointer to response buffer.
- */
-static void *ata_scsi_rbuf_get(struct scsi_cmnd *cmd, bool copy_in,
-			       unsigned long *flags)
-{
-	spin_lock_irqsave(&ata_scsi_rbuf_lock, *flags);
-
-	memset(ata_scsi_rbuf, 0, ATA_SCSI_RBUF_SIZE);
-	if (copy_in)
-		sg_copy_to_buffer(scsi_sglist(cmd), scsi_sg_count(cmd),
-				  ata_scsi_rbuf, ATA_SCSI_RBUF_SIZE);
-	return ata_scsi_rbuf;
-}
-
-/**
- *	ata_scsi_rbuf_put - Unmap response buffer.
- *	@cmd: SCSI command containing buffer to be unmapped.
- *	@copy_out: copy out result
- *	@flags: @flags passed to ata_scsi_rbuf_get()
- *
- *	Returns rbuf buffer.  The result is copied to @cmd's buffer if
- *	@copy_back is true.
- *
- *	LOCKING:
- *	Unlocks ata_scsi_rbuf_lock.
- */
-static inline void ata_scsi_rbuf_put(struct scsi_cmnd *cmd, bool copy_out,
-				     unsigned long *flags)
-{
-	if (copy_out)
-		sg_copy_from_buffer(scsi_sglist(cmd), scsi_sg_count(cmd),
-				    ata_scsi_rbuf, ATA_SCSI_RBUF_SIZE);
-	spin_unlock_irqrestore(&ata_scsi_rbuf_lock, *flags);
-}
-
 /**
  *	ata_scsi_rbuf_fill - wrapper for SCSI command simulators
- *	@args: device IDENTIFY data / SCSI command of interest.
+ *	@dev: Target device.
+ *	@cmd: SCSI command of interest.
  *	@actor: Callback hook for desired SCSI command simulator
  *
  *	Takes care of the hard work of simulating a SCSI command...
@@ -1837,25 +1792,32 @@ static inline void ata_scsi_rbuf_put(struct scsi_cmnd *cmd, bool copy_out,
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  */
-static void ata_scsi_rbuf_fill(struct ata_scsi_args *args,
-		unsigned int (*actor)(struct ata_scsi_args *args, u8 *rbuf))
+static void ata_scsi_rbuf_fill(struct ata_device *dev, struct scsi_cmnd *cmd,
+		unsigned int (*actor)(struct ata_device *dev,
+				      struct scsi_cmnd *cmd, u8 *rbuf))
 {
-	u8 *rbuf;
-	unsigned int rc;
-	struct scsi_cmnd *cmd = args->cmd;
 	unsigned long flags;
+	unsigned int len;
 
-	rbuf = ata_scsi_rbuf_get(cmd, false, &flags);
-	rc = actor(args, rbuf);
-	ata_scsi_rbuf_put(cmd, rc == 0, &flags);
+	spin_lock_irqsave(&ata_scsi_rbuf_lock, flags);
 
-	if (rc == 0)
+	memset(ata_scsi_rbuf, 0, ATA_SCSI_RBUF_SIZE);
+	len = actor(dev, cmd, ata_scsi_rbuf);
+	if (len) {
+		sg_copy_from_buffer(scsi_sglist(cmd), scsi_sg_count(cmd),
+				    ata_scsi_rbuf, ATA_SCSI_RBUF_SIZE);
 		cmd->result = SAM_STAT_GOOD;
+		if (scsi_bufflen(cmd) > len)
+			scsi_set_resid(cmd, scsi_bufflen(cmd) - len);
+	}
+
+	spin_unlock_irqrestore(&ata_scsi_rbuf_lock, flags);
 }
 
 /**
- *	ata_scsiop_inq_std - Simulate INQUIRY command
- *	@args: device IDENTIFY data / SCSI command of interest.
+ *	ata_scsiop_inq_std - Simulate standard INQUIRY command
+ *	@dev: Target device.
+ *	@cmd: SCSI command of interest.
  *	@rbuf: Response buffer, to which simulated SCSI cmd output is sent.
  *
  *	Returns standard device identification data associated
@@ -1864,7 +1826,8 @@ static void ata_scsi_rbuf_fill(struct ata_scsi_args *args,
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  */
-static unsigned int ata_scsiop_inq_std(struct ata_scsi_args *args, u8 *rbuf)
+static unsigned int ata_scsiop_inq_std(struct ata_device *dev,
+				       struct scsi_cmnd *cmd, u8 *rbuf)
 {
 	static const u8 versions[] = {
 		0x00,
@@ -1901,43 +1864,49 @@ static unsigned int ata_scsiop_inq_std(struct ata_scsi_args *args, u8 *rbuf)
 		2
 	};
 
-	VPRINTK("ENTER\n");
-
-	/* set scsi removable (RMB) bit per ata bit, or if the
-	 * AHCI port says it's external (Hotplug-capable, eSATA).
+	/*
+	 * Set the SCSI Removable Media Bit (RMB) if the ATA removable media
+	 * device bit (obsolete since ATA-8 ACS) is set.
 	 */
-	if (ata_id_removable(args->id) ||
-	    (args->dev->link->ap->pflags & ATA_PFLAG_EXTERNAL))
+	if (ata_id_removable(dev->id))
 		hdr[1] |= (1 << 7);
 
-	if (args->dev->class == ATA_DEV_ZAC) {
+	if (dev->class == ATA_DEV_ZAC) {
 		hdr[0] = TYPE_ZBC;
 		hdr[2] = 0x7; /* claim SPC-5 version compatibility */
 	}
 
+	if (dev->flags & ATA_DFLAG_CDL)
+		hdr[2] = 0xd; /* claim SPC-6 version compatibility */
+
 	memcpy(rbuf, hdr, sizeof(hdr));
 	memcpy(&rbuf[8], "ATA     ", 8);
-	ata_id_string(args->id, &rbuf[16], ATA_ID_PROD, 16);
+	ata_id_string(dev->id, &rbuf[16], ATA_ID_PROD, 16);
 
 	/* From SAT, use last 2 words from fw rev unless they are spaces */
-	ata_id_string(args->id, &rbuf[32], ATA_ID_FW_REV + 2, 4);
+	ata_id_string(dev->id, &rbuf[32], ATA_ID_FW_REV + 2, 4);
 	if (strncmp(&rbuf[32], "    ", 4) == 0)
-		ata_id_string(args->id, &rbuf[32], ATA_ID_FW_REV, 4);
+		ata_id_string(dev->id, &rbuf[32], ATA_ID_FW_REV, 4);
 
 	if (rbuf[32] == 0 || rbuf[32] == ' ')
 		memcpy(&rbuf[32], "n/a ", 4);
 
-	if (ata_id_zoned_cap(args->id) || args->dev->class == ATA_DEV_ZAC)
+	if (ata_id_zoned_cap(dev->id) || dev->class == ATA_DEV_ZAC)
 		memcpy(rbuf + 58, versions_zbc, sizeof(versions_zbc));
 	else
 		memcpy(rbuf + 58, versions, sizeof(versions));
 
-	return 0;
+	/*
+	 * Include all 8 possible version descriptors, even if not all of
+	 * them are popoulated.
+	 */
+	return 96;
 }
 
 /**
  *	ata_scsiop_inq_00 - Simulate INQUIRY VPD page 0, list of pages
- *	@args: device IDENTIFY data / SCSI command of interest.
+ *	@dev: Target device.
+ *	@cmd: SCSI command of interest.
  *	@rbuf: Response buffer, to which simulated SCSI cmd output is sent.
  *
  *	Returns list of inquiry VPD pages available.
@@ -1945,9 +1914,10 @@ static unsigned int ata_scsiop_inq_std(struct ata_scsi_args *args, u8 *rbuf)
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  */
-static unsigned int ata_scsiop_inq_00(struct ata_scsi_args *args, u8 *rbuf)
+static unsigned int ata_scsiop_inq_00(struct ata_device *dev,
+				      struct scsi_cmnd *cmd, u8 *rbuf)
 {
-	int num_pages;
+	int i, num_pages = 0;
 	static const u8 pages[] = {
 		0x00,	/* page 0x00, this page */
 		0x80,	/* page 0x80, unit serial no page */
@@ -1957,19 +1927,24 @@ static unsigned int ata_scsiop_inq_00(struct ata_scsi_args *args, u8 *rbuf)
 		0xb1,	/* page 0xb1, block device characteristics page */
 		0xb2,	/* page 0xb2, thin provisioning page */
 		0xb6,	/* page 0xb6, zoned block device characteristics */
+		0xb9,	/* page 0xb9, concurrent positioning ranges */
 	};
 
-	num_pages = sizeof(pages);
-	if (!(args->dev->flags & ATA_DFLAG_ZAC))
-		num_pages--;
+	for (i = 0; i < sizeof(pages); i++) {
+		if (pages[i] == 0xb6 && !ata_dev_is_zac(dev))
+			continue;
+		rbuf[num_pages + 4] = pages[i];
+		num_pages++;
+	}
 	rbuf[3] = num_pages;	/* number of supported VPD pages */
-	memcpy(rbuf + 4, pages, num_pages);
-	return 0;
+
+	return get_unaligned_be16(&rbuf[2]) + 4;
 }
 
 /**
  *	ata_scsiop_inq_80 - Simulate INQUIRY VPD page 80, device serial number
- *	@args: device IDENTIFY data / SCSI command of interest.
+ *	@dev: Target device.
+ *	@cmd: SCSI command of interest.
  *	@rbuf: Response buffer, to which simulated SCSI cmd output is sent.
  *
  *	Returns ATA device serial number.
@@ -1977,7 +1952,8 @@ static unsigned int ata_scsiop_inq_00(struct ata_scsi_args *args, u8 *rbuf)
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  */
-static unsigned int ata_scsiop_inq_80(struct ata_scsi_args *args, u8 *rbuf)
+static unsigned int ata_scsiop_inq_80(struct ata_device *dev,
+				      struct scsi_cmnd *cmd, u8 *rbuf)
 {
 	static const u8 hdr[] = {
 		0,
@@ -1987,14 +1963,16 @@ static unsigned int ata_scsiop_inq_80(struct ata_scsi_args *args, u8 *rbuf)
 	};
 
 	memcpy(rbuf, hdr, sizeof(hdr));
-	ata_id_string(args->id, (unsigned char *) &rbuf[4],
+	ata_id_string(dev->id, (unsigned char *) &rbuf[4],
 		      ATA_ID_SERNO, ATA_ID_SERNO_LEN);
-	return 0;
+
+	return get_unaligned_be16(&rbuf[2]) + 4;
 }
 
 /**
  *	ata_scsiop_inq_83 - Simulate INQUIRY VPD page 83, device identity
- *	@args: device IDENTIFY data / SCSI command of interest.
+ *	@dev: Target device.
+ *	@cmd: SCSI command of interest.
  *	@rbuf: Response buffer, to which simulated SCSI cmd output is sent.
  *
  *	Yields two logical unit device identification designators:
@@ -2005,7 +1983,8 @@ static unsigned int ata_scsiop_inq_80(struct ata_scsi_args *args, u8 *rbuf)
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  */
-static unsigned int ata_scsiop_inq_83(struct ata_scsi_args *args, u8 *rbuf)
+static unsigned int ata_scsiop_inq_83(struct ata_device *dev,
+				      struct scsi_cmnd *cmd, u8 *rbuf)
 {
 	const int sat_model_serial_desc_len = 68;
 	int num;
@@ -2017,7 +1996,7 @@ static unsigned int ata_scsiop_inq_83(struct ata_scsi_args *args, u8 *rbuf)
 	rbuf[num + 0] = 2;
 	rbuf[num + 3] = ATA_ID_SERNO_LEN;
 	num += 4;
-	ata_id_string(args->id, (unsigned char *) rbuf + num,
+	ata_id_string(dev->id, (unsigned char *) rbuf + num,
 		      ATA_ID_SERNO, ATA_ID_SERNO_LEN);
 	num += ATA_ID_SERNO_LEN;
 
@@ -2029,31 +2008,33 @@ static unsigned int ata_scsiop_inq_83(struct ata_scsi_args *args, u8 *rbuf)
 	num += 4;
 	memcpy(rbuf + num, "ATA     ", 8);
 	num += 8;
-	ata_id_string(args->id, (unsigned char *) rbuf + num, ATA_ID_PROD,
+	ata_id_string(dev->id, (unsigned char *) rbuf + num, ATA_ID_PROD,
 		      ATA_ID_PROD_LEN);
 	num += ATA_ID_PROD_LEN;
-	ata_id_string(args->id, (unsigned char *) rbuf + num, ATA_ID_SERNO,
+	ata_id_string(dev->id, (unsigned char *) rbuf + num, ATA_ID_SERNO,
 		      ATA_ID_SERNO_LEN);
 	num += ATA_ID_SERNO_LEN;
 
-	if (ata_id_has_wwn(args->id)) {
+	if (ata_id_has_wwn(dev->id)) {
 		/* SAT defined lu world wide name */
 		/* piv=0, assoc=lu, code_set=binary, designator=NAA */
 		rbuf[num + 0] = 1;
 		rbuf[num + 1] = 3;
 		rbuf[num + 3] = ATA_ID_WWN_LEN;
 		num += 4;
-		ata_id_string(args->id, (unsigned char *) rbuf + num,
+		ata_id_string(dev->id, (unsigned char *) rbuf + num,
 			      ATA_ID_WWN, ATA_ID_WWN_LEN);
 		num += ATA_ID_WWN_LEN;
 	}
 	rbuf[3] = num - 4;    /* page len (assume less than 256 bytes) */
-	return 0;
+
+	return get_unaligned_be16(&rbuf[2]) + 4;
 }
 
 /**
  *	ata_scsiop_inq_89 - Simulate INQUIRY VPD page 89, ATA info
- *	@args: device IDENTIFY data / SCSI command of interest.
+ *	@dev: Target device.
+ *	@cmd: SCSI command of interest.
  *	@rbuf: Response buffer, to which simulated SCSI cmd output is sent.
  *
  *	Yields SAT-specified ATA VPD page.
@@ -2061,7 +2042,8 @@ static unsigned int ata_scsiop_inq_83(struct ata_scsi_args *args, u8 *rbuf)
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  */
-static unsigned int ata_scsiop_inq_89(struct ata_scsi_args *args, u8 *rbuf)
+static unsigned int ata_scsiop_inq_89(struct ata_device *dev,
+				      struct scsi_cmnd *cmd, u8 *rbuf)
 {
 	rbuf[1] = 0x89;			/* our page code */
 	rbuf[2] = (0x238 >> 8);		/* page size fixed at 238h */
@@ -2082,11 +2064,24 @@ static unsigned int ata_scsiop_inq_89(struct ata_scsi_args *args, u8 *rbuf)
 
 	rbuf[56] = ATA_CMD_ID_ATA;
 
-	memcpy(&rbuf[60], &args->id[0], 512);
-	return 0;
+	memcpy(&rbuf[60], &dev->id[0], 512);
+
+	return get_unaligned_be16(&rbuf[2]) + 4;
 }
 
-static unsigned int ata_scsiop_inq_b0(struct ata_scsi_args *args, u8 *rbuf)
+/**
+ *	ata_scsiop_inq_b0 - Simulate INQUIRY VPD page B0, Block Limits
+ *	@dev: Target device.
+ *	@cmd: SCSI command of interest.
+ *	@rbuf: Response buffer, to which simulated SCSI cmd output is sent.
+ *
+ *	Return data for the VPD page B0h (Block Limits).
+ *
+ *	LOCKING:
+ *	spin_lock_irqsave(host lock)
+ */
+static unsigned int ata_scsiop_inq_b0(struct ata_device *dev,
+				      struct scsi_cmnd *cmd, u8 *rbuf)
 {
 	u16 min_io_sectors;
 
@@ -2100,7 +2095,7 @@ static unsigned int ata_scsiop_inq_b0(struct ata_scsi_args *args, u8 *rbuf)
 	 * logical than physical sector size we need to figure out what the
 	 * latter is.
 	 */
-	min_io_sectors = 1 << ata_id_log2_per_physical_sector(args->id);
+	min_io_sectors = 1 << ata_id_log2_per_physical_sector(dev->id);
 	put_unaligned_be16(min_io_sectors, &rbuf[6]);
 
 	/*
@@ -2112,19 +2107,37 @@ static unsigned int ata_scsiop_inq_b0(struct ata_scsi_args *args, u8 *rbuf)
 	 * that we support some form of unmap - in thise case via WRITE SAME
 	 * with the unmap bit set.
 	 */
-	if (ata_id_has_trim(args->id)) {
-		put_unaligned_be64(65535 * ATA_MAX_TRIM_RNUM, &rbuf[36]);
+	if (ata_id_has_trim(dev->id)) {
+		u64 max_blocks = 65535 * ATA_MAX_TRIM_RNUM;
+
+		if (dev->quirks & ATA_QUIRK_MAX_TRIM_128M)
+			max_blocks = 128 << (20 - SECTOR_SHIFT);
+
+		put_unaligned_be64(max_blocks, &rbuf[36]);
 		put_unaligned_be32(1, &rbuf[28]);
 	}
 
-	return 0;
+	return get_unaligned_be16(&rbuf[2]) + 4;
 }
 
-static unsigned int ata_scsiop_inq_b1(struct ata_scsi_args *args, u8 *rbuf)
+/**
+ *	ata_scsiop_inq_b1 - Simulate INQUIRY VPD page B1, Block Device
+ *			    Characteristics
+ *	@dev: Target device.
+ *	@cmd: SCSI command of interest.
+ *	@rbuf: Response buffer, to which simulated SCSI cmd output is sent.
+ *
+ *	Return data for the VPD page B1h (Block Device Characteristics).
+ *
+ *	LOCKING:
+ *	spin_lock_irqsave(host lock)
+ */
+static unsigned int ata_scsiop_inq_b1(struct ata_device *dev,
+				      struct scsi_cmnd *cmd, u8 *rbuf)
 {
-	int form_factor = ata_id_form_factor(args->id);
-	int media_rotation_rate = ata_id_rotation_rate(args->id);
-	u8 zoned = ata_id_zoned_cap(args->id);
+	int form_factor = ata_id_form_factor(dev->id);
+	int media_rotation_rate = ata_id_rotation_rate(dev->id);
+	u8 zoned = ata_id_zoned_cap(dev->id);
 
 	rbuf[1] = 0xb1;
 	rbuf[3] = 0x3c;
@@ -2134,21 +2147,52 @@ static unsigned int ata_scsiop_inq_b1(struct ata_scsi_args *args, u8 *rbuf)
 	if (zoned)
 		rbuf[8] = (zoned << 4);
 
-	return 0;
+	return get_unaligned_be16(&rbuf[2]) + 4;
 }
 
-static unsigned int ata_scsiop_inq_b2(struct ata_scsi_args *args, u8 *rbuf)
+/**
+ *	ata_scsiop_inq_b2 - Simulate INQUIRY VPD page B2, Logical Block
+ *			    Provisioning
+ *	@dev: Target device.
+ *	@cmd: SCSI command of interest.
+ *	@rbuf: Response buffer, to which simulated SCSI cmd output is sent.
+ *
+ *	Return data for the VPD page B2h (Logical Block Provisioning).
+ *
+ *	LOCKING:
+ *	spin_lock_irqsave(host lock)
+ */
+static unsigned int ata_scsiop_inq_b2(struct ata_device *dev,
+				      struct scsi_cmnd *cmd, u8 *rbuf)
 {
 	/* SCSI Thin Provisioning VPD page: SBC-3 rev 22 or later */
 	rbuf[1] = 0xb2;
 	rbuf[3] = 0x4;
 	rbuf[5] = 1 << 6;	/* TPWS */
 
-	return 0;
+	return get_unaligned_be16(&rbuf[2]) + 4;
 }
 
-static unsigned int ata_scsiop_inq_b6(struct ata_scsi_args *args, u8 *rbuf)
+/**
+ *	ata_scsiop_inq_b6 - Simulate INQUIRY VPD page B6, Zoned Block Device
+ *			    Characteristics
+ *	@dev: Target device.
+ *	@cmd: SCSI command of interest.
+ *	@rbuf: Response buffer, to which simulated SCSI cmd output is sent.
+ *
+ *	Return data for the VPD page B2h (Zoned Block Device Characteristics).
+ *
+ *	LOCKING:
+ *	spin_lock_irqsave(host lock)
+ */
+static unsigned int ata_scsiop_inq_b6(struct ata_device *dev,
+				      struct scsi_cmnd *cmd, u8 *rbuf)
 {
+	if (!ata_dev_is_zac(dev)) {
+		ata_scsi_set_invalid_field(dev, cmd, 2, 0xff);
+		return 0;
+	}
+
 	/*
 	 * zbc-r05 SCSI Zoned Block device characteristics VPD page
 	 */
@@ -2158,13 +2202,102 @@ static unsigned int ata_scsiop_inq_b6(struct ata_scsi_args *args, u8 *rbuf)
 	/*
 	 * URSWRZ bit is only meaningful for host-managed ZAC drives
 	 */
-	if (args->dev->zac_zoned_cap & 1)
+	if (dev->zac_zoned_cap & 1)
 		rbuf[4] |= 1;
-	put_unaligned_be32(args->dev->zac_zones_optimal_open, &rbuf[8]);
-	put_unaligned_be32(args->dev->zac_zones_optimal_nonseq, &rbuf[12]);
-	put_unaligned_be32(args->dev->zac_zones_max_open, &rbuf[16]);
+	put_unaligned_be32(dev->zac_zones_optimal_open, &rbuf[8]);
+	put_unaligned_be32(dev->zac_zones_optimal_nonseq, &rbuf[12]);
+	put_unaligned_be32(dev->zac_zones_max_open, &rbuf[16]);
 
-	return 0;
+	return get_unaligned_be16(&rbuf[2]) + 4;
+}
+
+/**
+ *	ata_scsiop_inq_b9 - Simulate INQUIRY VPD page B9, Concurrent Positioning
+ *			    Ranges
+ *	@dev: Target device.
+ *	@cmd: SCSI command of interest.
+ *	@rbuf: Response buffer, to which simulated SCSI cmd output is sent.
+ *
+ *	Return data for the VPD page B9h (Concurrent Positioning Ranges).
+ *
+ *	LOCKING:
+ *	spin_lock_irqsave(host lock)
+ */
+static unsigned int ata_scsiop_inq_b9(struct ata_device *dev,
+				      struct scsi_cmnd *cmd, u8 *rbuf)
+{
+	struct ata_cpr_log *cpr_log = dev->cpr_log;
+	u8 *desc = &rbuf[64];
+	int i;
+
+	if (!cpr_log) {
+		ata_scsi_set_invalid_field(dev, cmd, 2, 0xff);
+		return 0;
+	}
+
+	/* SCSI Concurrent Positioning Ranges VPD page: SBC-5 rev 1 or later */
+	rbuf[1] = 0xb9;
+	put_unaligned_be16(64 + (int)cpr_log->nr_cpr * 32 - 4, &rbuf[2]);
+
+	for (i = 0; i < cpr_log->nr_cpr; i++, desc += 32) {
+		desc[0] = cpr_log->cpr[i].num;
+		desc[1] = cpr_log->cpr[i].num_storage_elements;
+		put_unaligned_be64(cpr_log->cpr[i].start_lba, &desc[8]);
+		put_unaligned_be64(cpr_log->cpr[i].num_lbas, &desc[16]);
+	}
+
+	return get_unaligned_be16(&rbuf[2]) + 4;
+}
+
+/**
+ *	ata_scsiop_inquiry - Simulate INQUIRY command
+ *	@dev: Target device.
+ *	@cmd: SCSI command of interest.
+ *	@rbuf: Response buffer, to which simulated SCSI cmd output is sent.
+ *
+ *	Returns data associated with an INQUIRY command output.
+ *
+ *	LOCKING:
+ *	spin_lock_irqsave(host lock)
+ */
+static unsigned int ata_scsiop_inquiry(struct ata_device *dev,
+				       struct scsi_cmnd *cmd, u8 *rbuf)
+{
+	const u8 *scsicmd = cmd->cmnd;
+
+	/* is CmdDt set?  */
+	if (scsicmd[1] & 2) {
+		ata_scsi_set_invalid_field(dev, cmd, 1, 0xff);
+		return 0;
+	}
+
+	/* Is EVPD clear? */
+	if ((scsicmd[1] & 1) == 0)
+		return ata_scsiop_inq_std(dev, cmd, rbuf);
+
+	switch (scsicmd[2]) {
+	case 0x00:
+		return ata_scsiop_inq_00(dev, cmd, rbuf);
+	case 0x80:
+		return ata_scsiop_inq_80(dev, cmd, rbuf);
+	case 0x83:
+		return ata_scsiop_inq_83(dev, cmd, rbuf);
+	case 0x89:
+		return ata_scsiop_inq_89(dev, cmd, rbuf);
+	case 0xb0:
+		return ata_scsiop_inq_b0(dev, cmd, rbuf);
+	case 0xb1:
+		return ata_scsiop_inq_b1(dev, cmd, rbuf);
+	case 0xb2:
+		return ata_scsiop_inq_b2(dev, cmd, rbuf);
+	case 0xb6:
+		return ata_scsiop_inq_b6(dev, cmd, rbuf);
+	case 0xb9:
+		return ata_scsiop_inq_b9(dev, cmd, rbuf);
+	default:
+		ata_scsi_set_invalid_field(dev, cmd, 2, 0xff);
+		return 0;
+	}
 }
 
 /**
@@ -2215,10 +2348,128 @@ static unsigned int ata_msense_caching(u16 *id, u8 *buf, bool changeable)
 	return sizeof(def_cache_mpage);
 }
 
+/*
+ * Simulate MODE SENSE control mode page, sub-page 0.
+ */
+static unsigned int ata_msense_control_spg0(struct ata_device *dev, u8 *buf,
+					    bool changeable)
+{
+	modecpy(buf, def_control_mpage,
+		sizeof(def_control_mpage), changeable);
+	if (changeable) {
+		/* ata_mselect_control() */
+		buf[2] |= (1 << 2);
+	} else {
+		bool d_sense = (dev->flags & ATA_DFLAG_D_SENSE);
+
+		/* descriptor format sense data */
+		buf[2] |= (d_sense << 2);
+	}
+
+	return sizeof(def_control_mpage);
+}
+
+/*
+ * Translate an ATA duration limit in microseconds to a SCSI duration limit
+ * using the t2cdlunits 0xa (10ms). Since the SCSI duration limits are 2-bytes
+ * only, take care of overflows.
+ */
+static inline u16 ata_xlat_cdl_limit(u8 *buf)
+{
+	u32 limit = get_unaligned_le32(buf);
+
+	return min_t(u32, limit / 10000, 65535);
+}
+
+/*
+ * Simulate MODE SENSE control mode page, sub-pages 07h and 08h
+ * (command duration limits T2A and T2B mode pages).
+ */
+static unsigned int ata_msense_control_spgt2(struct ata_device *dev, u8 *buf,
+					     u8 spg)
+{
+	u8 *b, *cdl, *desc;
+	u32 policy;
+	int i;
+
+	if (!(dev->flags & ATA_DFLAG_CDL) || !dev->cdl)
+		return 0;
+
+	cdl = dev->cdl->desc_log_buf;
+
+	/*
+	 * Fill the subpage. The first four bytes of the T2A/T2B mode pages
+	 * are a header. The PAGE LENGTH field is the size of the page
+	 * excluding the header.
+	 */
+	buf[0] = CONTROL_MPAGE;
+	buf[1] = spg;
+	put_unaligned_be16(CDL_T2_SUB_MPAGE_LEN - 4, &buf[2]);
+	if (spg == CDL_T2A_SUB_MPAGE) {
+		/*
+		 * Read descriptors map to the T2A page:
+		 * set perf_vs_duration_guidleine.
+		 */
+		buf[7] = (cdl[0] & 0x03) << 4;
+		desc = cdl + 64;
+	} else {
+		/* Write descriptors map to the T2B page */
+		desc = cdl + 288;
+	}
+
+	/* Fill the T2 page descriptors */
+	b = &buf[8];
+	policy = get_unaligned_le32(&cdl[0]);
+	for (i = 0; i < 7; i++, b += 32, desc += 32) {
+		/* t2cdlunits: fixed to 10ms */
+		b[0] = 0x0a;
+
+		/* Max inactive time and its policy */
+		put_unaligned_be16(ata_xlat_cdl_limit(&desc[8]), &b[2]);
+		b[6] = ((policy >> 8) & 0x0f) << 4;
+
+		/* Max active time and its policy */
+		put_unaligned_be16(ata_xlat_cdl_limit(&desc[4]), &b[4]);
+		b[6] |= (policy >> 4) & 0x0f;
+
+		/* Command duration guideline and its policy */
+		put_unaligned_be16(ata_xlat_cdl_limit(&desc[16]), &b[10]);
+		b[14] = policy & 0x0f;
+	}
+
+	return CDL_T2_SUB_MPAGE_LEN;
+}
+
+/*
+ * Simulate MODE SENSE control mode page, sub-page f2h
+ * (ATA feature control mode page).
+ */
+static unsigned int ata_msense_control_ata_feature(struct ata_device *dev,
+						   u8 *buf)
+{
+	/* PS=0, SPF=1 */
+	buf[0] = CONTROL_MPAGE | (1 << 6);
+	buf[1] = ATA_FEATURE_SUB_MPAGE;
+
+	/*
+	 * The first four bytes of ATA Feature Control mode page are a header.
+	 * The PAGE LENGTH field is the size of the page excluding the header.
+	 */
+	put_unaligned_be16(ATA_FEATURE_SUB_MPAGE_LEN - 4, &buf[2]);
+
+	if (dev->flags & ATA_DFLAG_CDL_ENABLED)
+		buf[4] = 0x02; /* T2A and T2B pages enabled */
+	else
+		buf[4] = 0;
+
+	return ATA_FEATURE_SUB_MPAGE_LEN;
+}
+
 /**
  *	ata_msense_control - Simulate MODE SENSE control mode page
  *	@dev: ATA device of interest
  *	@buf: output buffer
+ *	@spg: sub-page code
  *	@changeable: whether changeable parameters are requested
  *
  *	Generate a generic MODE SENSE control mode page.
@@ -2227,17 +2478,27 @@ static unsigned int ata_msense_caching(u16 *id, u8 *buf, bool changeable)
  *	None.
  */
 static unsigned int ata_msense_control(struct ata_device *dev, u8 *buf,
-					bool changeable)
+				       u8 spg, bool changeable)
 {
-	modecpy(buf, def_control_mpage, sizeof(def_control_mpage), changeable);
-	if (changeable) {
-		buf[2] |= (1 << 2);	/* ata_mselect_control() */
-	} else {
-		bool d_sense = (dev->flags & ATA_DFLAG_D_SENSE);
-
-		buf[2] |= (d_sense << 2);	/* descriptor format sense data */
+	unsigned int n;
+
+	switch (spg) {
+	case 0:
+		return ata_msense_control_spg0(dev, buf, changeable);
+	case CDL_T2A_SUB_MPAGE:
+	case CDL_T2B_SUB_MPAGE:
+		return ata_msense_control_spgt2(dev, buf, spg);
+	case ATA_FEATURE_SUB_MPAGE:
+		return ata_msense_control_ata_feature(dev, buf);
+	case ALL_SUB_MPAGES:
+		n = ata_msense_control_spg0(dev, buf, changeable);
+		n += ata_msense_control_spgt2(dev, buf + n, CDL_T2A_SUB_MPAGE);
+		n += ata_msense_control_spgt2(dev, buf + n, CDL_T2B_SUB_MPAGE);
+		n += ata_msense_control_ata_feature(dev, buf + n);
+		return n;
+	default:
+		return 0;
 	}
-	return sizeof(def_control_mpage);
 }
 
 /**
@@ -2257,33 +2518,10 @@ static unsigned int ata_msense_rw_recovery(u8 *buf, bool changeable)
 	return sizeof(def_rw_recovery_mpage);
 }
 
-/*
- * We can turn this into a real blacklist if it's needed, for now just
- * blacklist any Maxtor BANC1G10 revision firmware
- */
-static int ata_dev_supports_fua(u16 *id)
-{
-	unsigned char model[ATA_ID_PROD_LEN + 1], fw[ATA_ID_FW_REV_LEN + 1];
-
-	if (!libata_fua)
-		return 0;
-	if (!ata_id_has_fua(id))
-		return 0;
-
-	ata_id_c_string(id, model, ATA_ID_PROD, sizeof(model));
-	ata_id_c_string(id, fw, ATA_ID_FW_REV, sizeof(fw));
-
-	if (strcmp(model, "Maxtor"))
-		return 1;
-	if (strcmp(fw, "BANC1G10"))
-		return 1;
-
-	return 0; /* blacklisted */
-}
-
 /**
  *	ata_scsiop_mode_sense - Simulate MODE SENSE 6, 10 commands
- *	@args: device IDENTIFY data / SCSI command of interest.
+ *	@dev: Target device.
+ *	@cmd: SCSI command of interest.
  *	@rbuf: Response buffer, to which simulated SCSI cmd output is sent.
  *
  *	Simulate MODE SENSE commands. Assume this is invoked for direct
@@ -2293,10 +2531,10 @@ static int ata_dev_supports_fua(u16 *id)
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  */
-static unsigned int ata_scsiop_mode_sense(struct ata_scsi_args *args, u8 *rbuf)
+static unsigned int ata_scsiop_mode_sense(struct ata_device *dev,
+					  struct scsi_cmnd *cmd, u8 *rbuf)
 {
-	struct ata_device *dev = args->dev;
-	u8 *scsicmd = args->cmd->cmnd, *p = rbuf;
+	u8 *scsicmd = cmd->cmnd, *p = rbuf;
 	static const u8 sat_blk_desc[] = {
 		0, 0, 0, 0,	/* number of blocks: sat unspecified */
 		0,
@@ -2304,11 +2542,9 @@ static unsigned int ata_scsiop_mode_sense(struct ata_scsi_args *args, u8 *rbuf)
 	};
 	u8 pg, spg;
 	unsigned int ebd, page_control, six_byte;
-	u8 dpofua, bp = 0xff;
+	u8 dpofua = 0, bp = 0xff;
 	u16 fp;
 
-	VPRINTK("ENTER\n");
-
 	six_byte = (scsicmd[0] == MODE_SENSE);
 	ebd = !(scsicmd[1] & 0x8);      /* dbd bit inverted == edb */
 	/*
@@ -2336,13 +2572,25 @@ static unsigned int ata_scsiop_mode_sense(struct ata_scsi_args *args, u8 *rbuf)
 
 	pg = scsicmd[2] & 0x3f;
 	spg = scsicmd[3];
+
 	/*
-	 * No mode subpages supported (yet) but asking for _all_
-	 * subpages may be valid
+	 * Supported subpages: all subpages and sub-pages 07h, 08h and f2h of
+	 * the control page.
 	 */
-	if (spg && (spg != ALL_SUB_MPAGES)) {
-		fp = 3;
-		goto invalid_fld;
+	if (spg) {
+		switch (spg) {
+		case ALL_SUB_MPAGES:
+			break;
+		case CDL_T2A_SUB_MPAGE:
+		case CDL_T2B_SUB_MPAGE:
+		case ATA_FEATURE_SUB_MPAGE:
+			if (dev->flags & ATA_DFLAG_CDL && pg == CONTROL_MPAGE)
+				break;
+			fallthrough;
+		default:
+			fp = 3;
+			goto invalid_fld;
+		}
 	}
 
 	switch(pg) {
@@ -2351,17 +2599,17 @@ static unsigned int ata_scsiop_mode_sense(struct ata_scsi_args *args, u8 *rbuf)
 		break;
 
 	case CACHE_MPAGE:
-		p += ata_msense_caching(args->id, p, page_control == 1);
+		p += ata_msense_caching(dev->id, p, page_control == 1);
 		break;
 
 	case CONTROL_MPAGE:
-		p += ata_msense_control(args->dev, p, page_control == 1);
+		p += ata_msense_control(dev, p, spg, page_control == 1);
 		break;
 
 	case ALL_MPAGES:
 		p += ata_msense_rw_recovery(p, page_control == 1);
-		p += ata_msense_caching(args->id, p, page_control == 1);
-		p += ata_msense_control(args->dev, p, page_control == 1);
+		p += ata_msense_caching(dev->id, p, page_control == 1);
+		p += ata_msense_control(dev, p, spg, page_control == 1);
 		break;
 
 	default:		/* invalid page code */
@@ -2369,9 +2617,7 @@ static unsigned int ata_scsiop_mode_sense(struct ata_scsi_args *args, u8 *rbuf)
 		goto invalid_fld;
 	}
 
-	dpofua = 0;
-	if (ata_dev_supports_fua(args->id) && (dev->flags & ATA_DFLAG_LBA48) &&
-	    (!(dev->flags & ATA_DFLAG_PIO) || dev->multi_count))
+	if (dev->flags & ATA_DFLAG_FUA)
 		dpofua = 1 << 4;
 
 	if (six_byte) {
@@ -2381,32 +2627,33 @@ static unsigned int ata_scsiop_mode_sense(struct ata_scsi_args *args, u8 *rbuf)
 			rbuf[3] = sizeof(sat_blk_desc);
 			memcpy(rbuf + 4, sat_blk_desc, sizeof(sat_blk_desc));
 		}
-	} else {
-		unsigned int output_len = p - rbuf - 2;
 
-		rbuf[0] = output_len >> 8;
-		rbuf[1] = output_len;
-		rbuf[3] |= dpofua;
-		if (ebd) {
-			rbuf[7] = sizeof(sat_blk_desc);
-			memcpy(rbuf + 8, sat_blk_desc, sizeof(sat_blk_desc));
-		}
+		return rbuf[0] + 1;
 	}
-	return 0;
+
+	put_unaligned_be16(p - rbuf - 2, &rbuf[0]);
+	rbuf[3] |= dpofua;
+	if (ebd) {
+		rbuf[7] = sizeof(sat_blk_desc);
+		memcpy(rbuf + 8, sat_blk_desc, sizeof(sat_blk_desc));
+	}
+
+	return get_unaligned_be16(&rbuf[0]) + 2;
 
 invalid_fld:
-	ata_scsi_set_invalid_field(dev, args->cmd, fp, bp);
-	return 1;
+	ata_scsi_set_invalid_field(dev, cmd, fp, bp);
+	return 0;
 
 saving_not_supp:
-	ata_scsi_set_sense(dev, args->cmd, ILLEGAL_REQUEST, 0x39, 0x0);
+	ata_scsi_set_sense(dev, cmd, ILLEGAL_REQUEST, 0x39, 0x0);
 	 /* "Saving parameters not supported" */
-	return 1;
+	return 0;
 }
 
 /**
  *	ata_scsiop_read_cap - Simulate READ CAPACITY[ 16] commands
- *	@args: device IDENTIFY data / SCSI command of interest.
+ *	@dev: Target device.
+ *	@cmd: SCSI command of interest.
  *	@rbuf: Response buffer, to which simulated SCSI cmd output is sent.
  *
  *	Simulate READ CAPACITY commands.
@@ -2414,9 +2661,10 @@ saving_not_supp:
  *	LOCKING:
  *	None.
  */
-static unsigned int ata_scsiop_read_cap(struct ata_scsi_args *args, u8 *rbuf)
+static unsigned int ata_scsiop_read_cap(struct ata_device *dev,
+					struct scsi_cmnd *cmd, u8 *rbuf)
 {
-	struct ata_device *dev = args->dev;
+	u8 *scsicmd = cmd->cmnd;
 	u64 last_lba = dev->n_sectors - 1; /* LBA of the last block */
 	u32 sector_size; /* physical sector size in bytes */
 	u8 log2_per_phys;
@@ -2426,9 +2674,7 @@ static unsigned int ata_scsiop_read_cap(struct ata_scsi_args *args, u8 *rbuf)
 	log2_per_phys = ata_id_log2_per_physical_sector(dev->id);
 	lowest_aligned = ata_id_logical_sector_offset(dev->id, log2_per_phys);
 
-	VPRINTK("ENTER\n");
-
-	if (args->cmd->cmnd[0] == READ_CAPACITY) {
+	if (scsicmd[0] == READ_CAPACITY) {
 		if (last_lba >= 0xffffffffULL)
 			last_lba = 0xffffffff;
 
@@ -2443,48 +2689,59 @@ static unsigned int ata_scsiop_read_cap(struct ata_scsi_args *args, u8 *rbuf)
 		rbuf[5] = sector_size >> (8 * 2);
 		rbuf[6] = sector_size >> (8 * 1);
 		rbuf[7] = sector_size;
-	} else {
-		/* sector count, 64-bit */
-		rbuf[0] = last_lba >> (8 * 7);
-		rbuf[1] = last_lba >> (8 * 6);
-		rbuf[2] = last_lba >> (8 * 5);
-		rbuf[3] = last_lba >> (8 * 4);
-		rbuf[4] = last_lba >> (8 * 3);
-		rbuf[5] = last_lba >> (8 * 2);
-		rbuf[6] = last_lba >> (8 * 1);
-		rbuf[7] = last_lba;
 
-		/* sector size */
-		rbuf[ 8] = sector_size >> (8 * 3);
-		rbuf[ 9] = sector_size >> (8 * 2);
-		rbuf[10] = sector_size >> (8 * 1);
-		rbuf[11] = sector_size;
-
-		rbuf[12] = 0;
-		rbuf[13] = log2_per_phys;
-		rbuf[14] = (lowest_aligned >> 8) & 0x3f;
-		rbuf[15] = lowest_aligned;
-
-		if (ata_id_has_trim(args->id) &&
-		    !(dev->horkage & ATA_HORKAGE_NOTRIM)) {
-			rbuf[14] |= 0x80; /* LBPME */
-
-			if (ata_id_has_zero_after_trim(args->id) &&
-			    dev->horkage & ATA_HORKAGE_ZERO_AFTER_TRIM) {
-				ata_dev_info(dev, "Enabling discard_zeroes_data\n");
-				rbuf[14] |= 0x40; /* LBPRZ */
-			}
+		return 8;
+	}
+
+	/*
+	 * READ CAPACITY 16 command is defined as a service action
+	 * (SERVICE_ACTION_IN_16 command).
+	 */
+	if (scsicmd[0] != SERVICE_ACTION_IN_16 ||
+	    (scsicmd[1] & 0x1f) != SAI_READ_CAPACITY_16) {
+		ata_scsi_set_invalid_field(dev, cmd, 1, 0xff);
+		return 0;
+	}
+
+	/* sector count, 64-bit */
+	rbuf[0] = last_lba >> (8 * 7);
+	rbuf[1] = last_lba >> (8 * 6);
+	rbuf[2] = last_lba >> (8 * 5);
+	rbuf[3] = last_lba >> (8 * 4);
+	rbuf[4] = last_lba >> (8 * 3);
+	rbuf[5] = last_lba >> (8 * 2);
+	rbuf[6] = last_lba >> (8 * 1);
+	rbuf[7] = last_lba;
+
+	/* sector size */
+	rbuf[ 8] = sector_size >> (8 * 3);
+	rbuf[ 9] = sector_size >> (8 * 2);
+	rbuf[10] = sector_size >> (8 * 1);
+	rbuf[11] = sector_size;
+
+	if (ata_id_zoned_cap(dev->id) || dev->class == ATA_DEV_ZAC)
+		rbuf[12] = (1 << 4); /* RC_BASIS */
+	rbuf[13] = log2_per_phys;
+	rbuf[14] = (lowest_aligned >> 8) & 0x3f;
+	rbuf[15] = lowest_aligned;
+
+	if (ata_id_has_trim(dev->id) && !(dev->quirks & ATA_QUIRK_NOTRIM)) {
+		rbuf[14] |= 0x80; /* LBPME */
+
+		if (ata_id_has_zero_after_trim(dev->id) &&
+		    dev->quirks & ATA_QUIRK_ZERO_AFTER_TRIM) {
+			ata_dev_info(dev, "Enabling discard_zeroes_data\n");
+			rbuf[14] |= 0x40; /* LBPRZ */
 		}
-		if (ata_id_zoned_cap(args->id) ||
-		    args->dev->class == ATA_DEV_ZAC)
-			rbuf[12] = (1 << 4); /* RC_BASIS */
 	}
-	return 0;
+
+	return 16;
 }
 
 /**
  *	ata_scsiop_report_luns - Simulate REPORT LUNS command
- *	@args: device IDENTIFY data / SCSI command of interest.
+ *	@dev: Target device.
+ *	@cmd: SCSI command of interest.
  *	@rbuf: Response buffer, to which simulated SCSI cmd output is sent.
  *
  *	Simulate REPORT LUNS command.
@@ -2492,81 +2749,12 @@ static unsigned int ata_scsiop_read_cap(struct ata_scsi_args *args, u8 *rbuf)
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  */
-static unsigned int ata_scsiop_report_luns(struct ata_scsi_args *args, u8 *rbuf)
+static unsigned int ata_scsiop_report_luns(struct ata_device *dev,
+					   struct scsi_cmnd *cmd, u8 *rbuf)
 {
-	VPRINTK("ENTER\n");
 	rbuf[3] = 8;	/* just one lun, LUN 0, size 8 bytes */
 
-	return 0;
-}
-
-static void atapi_sense_complete(struct ata_queued_cmd *qc)
-{
-	if (qc->err_mask && ((qc->err_mask & AC_ERR_DEV) == 0)) {
-		/* FIXME: not quite right; we don't want the
-		 * translation of taskfile registers into
-		 * a sense descriptors, since that's only
-		 * correct for ATA, not ATAPI
-		 */
-		ata_gen_passthru_sense(qc);
-	}
-
-	ata_qc_done(qc);
-}
-
-/* is it pointless to prefer PIO for "safety reasons"? */
-static inline int ata_pio_use_silly(struct ata_port *ap)
-{
-	return (ap->flags & ATA_FLAG_PIO_DMA);
-}
-
-static void atapi_request_sense(struct ata_queued_cmd *qc)
-{
-	struct ata_port *ap = qc->ap;
-	struct scsi_cmnd *cmd = qc->scsicmd;
-
-	DPRINTK("ATAPI request sense\n");
-
-	memset(cmd->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
-
-#ifdef CONFIG_ATA_SFF
-	if (ap->ops->sff_tf_read)
-		ap->ops->sff_tf_read(ap, &qc->tf);
-#endif
-
-	/* fill these in, for the case where they are -not- overwritten */
-	cmd->sense_buffer[0] = 0x70;
-	cmd->sense_buffer[2] = qc->tf.feature >> 4;
-
-	ata_qc_reinit(qc);
-
-	/* setup sg table and init transfer direction */
-	sg_init_one(&qc->sgent, cmd->sense_buffer, SCSI_SENSE_BUFFERSIZE);
-	ata_sg_init(qc, &qc->sgent, 1);
-	qc->dma_dir = DMA_FROM_DEVICE;
-
-	memset(&qc->cdb, 0, qc->dev->cdb_len);
-	qc->cdb[0] = REQUEST_SENSE;
-	qc->cdb[4] = SCSI_SENSE_BUFFERSIZE;
-
-	qc->tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
-	qc->tf.command = ATA_CMD_PACKET;
-
-	if (ata_pio_use_silly(ap)) {
-		qc->tf.protocol = ATAPI_PROT_DMA;
-		qc->tf.feature |= ATAPI_PKT_DMA;
-	} else {
-		qc->tf.protocol = ATAPI_PROT_PIO;
-		qc->tf.lbam = SCSI_SENSE_BUFFERSIZE;
-		qc->tf.lbah = 0;
-	}
-	qc->nbytes = SCSI_SENSE_BUFFERSIZE;
-
-	qc->complete_fn = atapi_sense_complete;
-
-	ata_qc_issue(qc);
-
-	DPRINTK("EXIT\n");
+	return 16;
 }
 
 /*
@@ -2594,20 +2782,11 @@ static void atapi_qc_complete(struct ata_queued_cmd *qc)
 	struct scsi_cmnd *cmd = qc->scsicmd;
 	unsigned int err_mask = qc->err_mask;
 
-	VPRINTK("ENTER, err_mask 0x%X\n", err_mask);
-
-	/* handle completion from new EH */
-	if (unlikely(qc->ap->ops->error_handler &&
-		     (err_mask || qc->flags & ATA_QCFLAG_SENSE_VALID))) {
+	/* handle completion from EH */
+	if (unlikely(err_mask || qc->flags & ATA_QCFLAG_SENSE_VALID)) {
 
-		if (!(qc->flags & ATA_QCFLAG_SENSE_VALID)) {
-			/* FIXME: not quite right; we don't want the
-			 * translation of taskfile registers into a
-			 * sense descriptors, since that's only
-			 * correct for ATA, not ATAPI
-			 */
+		if (!(qc->flags & ATA_QCFLAG_SENSE_VALID))
 			ata_gen_passthru_sense(qc);
-		}
 
 		/* SCSI EH automatically locks door if sdev->locked is
 		 * set.  Sometimes door lock request continues to
@@ -2630,23 +2809,10 @@ static void atapi_qc_complete(struct ata_queued_cmd *qc)
 		return;
 	}
 
-	/* successful completion or old EH failure path */
-	if (unlikely(err_mask & AC_ERR_DEV)) {
-		cmd->result = SAM_STAT_CHECK_CONDITION;
-		atapi_request_sense(qc);
-		return;
-	} else if (unlikely(err_mask)) {
-		/* FIXME: not quite right; we don't want the
-		 * translation of taskfile registers into
-		 * a sense descriptors, since that's only
-		 * correct for ATA, not ATAPI
-		 */
-		ata_gen_passthru_sense(qc);
-	} else {
-		if (cmd->cmnd[0] == INQUIRY && (cmd->cmnd[1] & 0x03) == 0)
-			atapi_fixup_inquiry(cmd);
-		cmd->result = SAM_STAT_GOOD;
-	}
+	/* successful completion path */
+	if (cmd->cmnd[0] == INQUIRY && (cmd->cmnd[1] & 0x03) == 0)
+		atapi_fixup_inquiry(cmd);
+	cmd->result = SAM_STAT_GOOD;
 
 	ata_qc_done(qc);
 }
@@ -2676,7 +2842,6 @@ static unsigned int atapi_xlat(struct ata_queued_cmd *qc)
 	qc->tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
 	if (scmd->sc_data_direction == DMA_TO_DEVICE) {
 		qc->tf.flags |= ATA_TFLAG_WRITE;
-		DPRINTK("direction: write\n");
 	}
 
 	qc->tf.command = ATA_CMD_PACKET;
@@ -2744,18 +2909,36 @@ static unsigned int atapi_xlat(struct ata_queued_cmd *qc)
 	return 0;
 }
 
-static struct ata_device *ata_find_dev(struct ata_port *ap, int devno)
+static struct ata_device *ata_find_dev(struct ata_port *ap, unsigned int devno)
 {
-	if (!sata_pmp_attached(ap)) {
-		if (likely(devno >= 0 &&
-			   devno < ata_link_max_devices(&ap->link)))
+	/*
+	 * For the non-PMP case, ata_link_max_devices() returns 1 (SATA case),
+	 * or 2 (IDE master + slave case). However, the former case includes
+	 * libsas hosted devices which are numbered per scsi host, leading
+	 * to devno potentially being larger than 0 but with each struct
+	 * ata_device having its own struct ata_port and struct ata_link.
+	 * To accommodate these, ignore devno and always use device number 0.
+	 */
+	if (likely(!sata_pmp_attached(ap))) {
+		int link_max_devices = ata_link_max_devices(&ap->link);
+
+		if (link_max_devices == 1)
+			return &ap->link.device[0];
+
+		if (devno < link_max_devices)
 			return &ap->link.device[devno];
-	} else {
-		if (likely(devno >= 0 &&
-			   devno < ap->nr_pmp_links))
-			return &ap->pmp_link[devno].device[0];
+
+		return NULL;
 	}
 
+	/*
+	 * For PMP-attached devices, the device number corresponds to C
+	 * (channel) of SCSI [H:C:I:L], indicating the port pmp link
+	 * for the device.
+	 */
+	if (devno < ap->nr_pmp_links)
+		return &ap->pmp_link[devno].device[0];
+
 	return NULL;
 }
 
@@ -2872,8 +3055,19 @@ static unsigned int ata_scsi_pass_thru(struct ata_queued_cmd *qc)
 		goto invalid_fld;
 	}
 
-	if (ata_is_ncq(tf->protocol) && (cdb[2 + cdb_offset] & 0x3) == 0)
-		tf->protocol = ATA_PROT_NCQ_NODATA;
+	if ((cdb[2 + cdb_offset] & 0x3) == 0) {
+		/*
+		 * When T_LENGTH is zero (No data is transferred), dir should
+		 * be DMA_NONE.
+		 */
+		if (scmd->sc_data_direction != DMA_NONE) {
+			fp = 2 + cdb_offset;
+			goto invalid_fld;
+		}
+
+		if (ata_is_ncq(tf->protocol))
+			tf->protocol = ATA_PROT_NCQ_NODATA;
+	}
 
 	/* enable LBA */
 	tf->flags |= ATA_TFLAG_LBA;
@@ -2882,7 +3076,8 @@ static unsigned int ata_scsi_pass_thru(struct ata_queued_cmd *qc)
 	 * 12 and 16 byte CDBs use different offsets to
 	 * provide the various register values.
 	 */
-	if (cdb[0] == ATA_16) {
+	switch (cdb[0]) {
+	case ATA_16:
 		/*
 		 * 16-byte CDB - may contain extended commands.
 		 *
@@ -2908,7 +3103,8 @@ static unsigned int ata_scsi_pass_thru(struct ata_queued_cmd *qc)
 		tf->lbah = cdb[12];
 		tf->device = cdb[13];
 		tf->command = cdb[14];
-	} else if (cdb[0] == ATA_12) {
+		break;
+	case ATA_12:
 		/*
 		 * 12-byte CDB - incapable of extended commands.
 		 */
@@ -2921,7 +3117,8 @@ static unsigned int ata_scsi_pass_thru(struct ata_queued_cmd *qc)
 		tf->lbah = cdb[7];
 		tf->device = cdb[8];
 		tf->command = cdb[9];
-	} else {
+		break;
+	default:
 		/*
 		 * 32-byte CDB - may contain extended command fields.
 		 *
@@ -2945,6 +3142,7 @@ static unsigned int ata_scsi_pass_thru(struct ata_queued_cmd *qc)
 		tf->device = cdb[24];
 		tf->command = cdb[25];
 		tf->auxiliary = get_unaligned_be32(&cdb[28]);
+		break;
 	}
 
 	/* For NCQ commands copy the tag value */
@@ -3027,7 +3225,7 @@ static unsigned int ata_scsi_pass_thru(struct ata_queued_cmd *qc)
 	ata_qc_set_pc_nbytes(qc);
 
 	/* We may not issue DMA commands if no DMA mode is set */
-	if (tf->protocol == ATA_PROT_DMA && dev->dma_mode == 0) {
+	if (tf->protocol == ATA_PROT_DMA && !ata_dma_enabled(dev)) {
 		fp = 1;
 		goto invalid_fld;
 	}
@@ -3177,7 +3375,7 @@ static unsigned int ata_scsi_write_same_xlat(struct ata_queued_cmd *qc)
 	u8 unmap = cdb[1] & 0x8;
 
 	/* we may not issue DMA commands if no DMA mode is set */
-	if (unlikely(!dev->dma_mode))
+	if (unlikely(!ata_dma_enabled(dev)))
 		goto invalid_opcode;
 
 	/*
@@ -3185,7 +3383,7 @@ static unsigned int ata_scsi_write_same_xlat(struct ata_queued_cmd *qc)
 	 * as it modifies the DATA OUT buffer, which would corrupt user
 	 * memory for SG_IO commands.
 	 */
-	if (unlikely(blk_rq_is_passthrough(scmd->request)))
+	if (unlikely(blk_rq_is_passthrough(scsi_cmd_to_rq(scmd))))
 		goto invalid_opcode;
 
 	if (unlikely(scmd->cmd_len < 16)) {
@@ -3194,8 +3392,7 @@ static unsigned int ata_scsi_write_same_xlat(struct ata_queued_cmd *qc)
 	}
 	scsi_16_lba_len(cdb, &block, &n_block);
 
-	if (!unmap ||
-	    (dev->horkage & ATA_HORKAGE_NOTRIM) ||
+	if (!unmap || (dev->quirks & ATA_QUIRK_NOTRIM) ||
 	    !ata_id_has_trim(dev->id)) {
 		fp = 1;
 		bp = 3;
@@ -3265,7 +3462,8 @@ invalid_opcode:
 
 /**
  *	ata_scsiop_maint_in - Simulate a subset of MAINTENANCE_IN
- *	@args: device MAINTENANCE_IN data / SCSI command of interest.
+ *	@dev: Target device.
+ *	@cmd: SCSI command of interest.
  *	@rbuf: Response buffer, to which simulated SCSI cmd output is sent.
  *
  *	Yields a subset to satisfy scsi_report_opcode()
@@ -3273,18 +3471,23 @@ invalid_opcode:
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  */
-static unsigned int ata_scsiop_maint_in(struct ata_scsi_args *args, u8 *rbuf)
+static unsigned int ata_scsiop_maint_in(struct ata_device *dev,
+					struct scsi_cmnd *cmd, u8 *rbuf)
 {
-	struct ata_device *dev = args->dev;
-	u8 *cdb = args->cmd->cmnd;
-	u8 supported = 0;
-	unsigned int err = 0;
+	u8 *cdb = cmd->cmnd;
+	u8 supported = 0, cdlp = 0, rwcdlp = 0;
+
+	if ((cdb[1] & 0x1f) != MI_REPORT_SUPPORTED_OPERATION_CODES) {
+		ata_scsi_set_invalid_field(dev, cmd, 1, 0xff);
+		return 0;
+	}
 
-	if (cdb[2] != 1) {
+	if (cdb[2] != 1 && cdb[2] != 3) {
 		ata_dev_warn(dev, "invalid command format %d\n", cdb[2]);
-		err = 2;
-		goto out;
+		ata_scsi_set_invalid_field(dev, cmd, 1, 0xff);
+		return 0;
 	}
+
 	switch (cdb[3]) {
 	case INQUIRY:
 	case MODE_SENSE:
@@ -3294,6 +3497,7 @@ static unsigned int ata_scsiop_maint_in(struct ata_scsi_args *args, u8 *rbuf)
 	case REPORT_LUNS:
 	case REQUEST_SENSE:
 	case SYNCHRONIZE_CACHE:
+	case SYNCHRONIZE_CACHE_16:
 	case REZERO_UNIT:
 	case SEEK_6:
 	case SEEK_10:
@@ -3302,10 +3506,8 @@ static unsigned int ata_scsiop_maint_in(struct ata_scsi_args *args, u8 *rbuf)
 	case MAINTENANCE_IN:
 	case READ_6:
 	case READ_10:
-	case READ_16:
 	case WRITE_6:
 	case WRITE_10:
-	case WRITE_16:
 	case ATA_12:
 	case ATA_16:
 	case VERIFY:
@@ -3315,6 +3517,28 @@ static unsigned int ata_scsiop_maint_in(struct ata_scsi_args *args, u8 *rbuf)
 	case START_STOP:
 		supported = 3;
 		break;
+	case READ_16:
+		supported = 3;
+		if (dev->flags & ATA_DFLAG_CDL) {
+			/*
+			 * CDL read descriptors map to the T2A page, that is,
+			 * rwcdlp = 0x01 and cdlp = 0x01
+			 */
+			rwcdlp = 0x01;
+			cdlp = 0x01 << 3;
+		}
+		break;
+	case WRITE_16:
+		supported = 3;
+		if (dev->flags & ATA_DFLAG_CDL) {
+			/*
+			 * CDL write descriptors map to the T2B page, that is,
+			 * rwcdlp = 0x01 and cdlp = 0x02
+			 */
+			rwcdlp = 0x01;
+			cdlp = 0x02 << 3;
+		}
+		break;
 	case ZBC_IN:
 	case ZBC_OUT:
 		if (ata_id_zoned_cap(dev->id) ||
@@ -3329,9 +3553,12 @@ static unsigned int ata_scsiop_maint_in(struct ata_scsi_args *args, u8 *rbuf)
 	default:
 		break;
 	}
-out:
-	rbuf[1] = supported; /* supported */
-	return err;
+
+	/* One command format */
+	rbuf[0] = rwcdlp;
+	rbuf[1] = cdlp | supported;
+
+	return 4;
 }
 
 /**
@@ -3593,10 +3820,7 @@ static int ata_mselect_caching(struct ata_queued_cmd *qc,
 	 */
 
 	if (len != CACHE_MPAGE_LEN - 2) {
-		if (len < CACHE_MPAGE_LEN - 2)
-			*fp = len;
-		else
-			*fp = CACHE_MPAGE_LEN - 2;
+		*fp = min(len, CACHE_MPAGE_LEN - 2);
 		return -EINVAL;
 	}
 
@@ -3623,20 +3847,11 @@ static int ata_mselect_caching(struct ata_queued_cmd *qc,
 	return 0;
 }
 
-/**
- *	ata_mselect_control - Simulate MODE SELECT for control page
- *	@qc: Storage for translated ATA taskfile
- *	@buf: input buffer
- *	@len: number of valid bytes in the input buffer
- *	@fp: out parameter for the failed field on error
- *
- *	Prepare a taskfile to modify caching information for the device.
- *
- *	LOCKING:
- *	None.
+/*
+ * Simulate MODE SELECT control mode page, sub-page 0.
  */
-static int ata_mselect_control(struct ata_queued_cmd *qc,
-			       const u8 *buf, int len, u16 *fp)
+static int ata_mselect_control_spg0(struct ata_queued_cmd *qc,
+				    const u8 *buf, int len, u16 *fp)
 {
 	struct ata_device *dev = qc->dev;
 	u8 mpage[CONTROL_MPAGE_LEN];
@@ -3649,10 +3864,7 @@ static int ata_mselect_control(struct ata_queued_cmd *qc,
 	 */
 
 	if (len != CONTROL_MPAGE_LEN - 2) {
-		if (len < CONTROL_MPAGE_LEN - 2)
-			*fp = len;
-		else
-			*fp = CONTROL_MPAGE_LEN - 2;
+		*fp = min(len, CONTROL_MPAGE_LEN - 2);
 		return -EINVAL;
 	}
 
@@ -3661,7 +3873,7 @@ static int ata_mselect_control(struct ata_queued_cmd *qc,
 	/*
 	 * Check that read-only bits are not modified.
 	 */
-	ata_msense_control(dev, mpage, false);
+	ata_msense_control_spg0(dev, mpage, false);
 	for (i = 0; i < CONTROL_MPAGE_LEN - 2; i++) {
 		if (i == 0)
 			continue;
@@ -3677,6 +3889,88 @@ static int ata_mselect_control(struct ata_queued_cmd *qc,
 	return 0;
 }
 
+/*
+ * Translate MODE SELECT control mode page, sub-page f2h (ATA feature mode
+ * page) into a SET FEATURES command.
+ */
+static int ata_mselect_control_ata_feature(struct ata_queued_cmd *qc,
+					   const u8 *buf, int len, u16 *fp)
+{
+	struct ata_device *dev = qc->dev;
+	struct ata_taskfile *tf = &qc->tf;
+	u8 cdl_action;
+
+	/*
+	 * The first four bytes of ATA Feature Control mode page are a header,
+	 * so offsets in mpage are off by 4 compared to buf.  Same for len.
+	 */
+	if (len != ATA_FEATURE_SUB_MPAGE_LEN - 4) {
+		*fp = min(len, ATA_FEATURE_SUB_MPAGE_LEN - 4);
+		return -EINVAL;
+	}
+
+	/* Check cdl_ctrl */
+	switch (buf[0] & 0x03) {
+	case 0:
+		/* Disable CDL */
+		ata_dev_dbg(dev, "Disabling CDL\n");
+		cdl_action = 0;
+		dev->flags &= ~ATA_DFLAG_CDL_ENABLED;
+		break;
+	case 0x02:
+		/*
+		 * Enable CDL. Since CDL is mutually exclusive with NCQ
+		 * priority, allow this only if NCQ priority is disabled.
+		 */
+		if (dev->flags & ATA_DFLAG_NCQ_PRIO_ENABLED) {
+			ata_dev_err(dev,
+				"NCQ priority must be disabled to enable CDL\n");
+			return -EINVAL;
+		}
+		ata_dev_dbg(dev, "Enabling CDL\n");
+		cdl_action = 1;
+		dev->flags |= ATA_DFLAG_CDL_ENABLED;
+		break;
+	default:
+		*fp = 0;
+		return -EINVAL;
+	}
+
+	tf->flags |= ATA_TFLAG_DEVICE | ATA_TFLAG_ISADDR;
+	tf->protocol = ATA_PROT_NODATA;
+	tf->command = ATA_CMD_SET_FEATURES;
+	tf->feature = SETFEATURES_CDL;
+	tf->nsect = cdl_action;
+
+	return 1;
+}
+
+/**
+ *	ata_mselect_control - Simulate MODE SELECT for control page
+ *	@qc: Storage for translated ATA taskfile
+ *	@spg: target sub-page of the control page
+ *	@buf: input buffer
+ *	@len: number of valid bytes in the input buffer
+ *	@fp: out parameter for the failed field on error
+ *
+ *	Prepare a taskfile to modify caching information for the device.
+ *
+ *	LOCKING:
+ *	None.
+ */
+static int ata_mselect_control(struct ata_queued_cmd *qc, u8 spg,
+			       const u8 *buf, int len, u16 *fp)
+{
+	switch (spg) {
+	case 0:
+		return ata_mselect_control_spg0(qc, buf, len, fp);
+	case ATA_FEATURE_SUB_MPAGE:
+		return ata_mselect_control_ata_feature(qc, buf, len, fp);
+	default:
+		return -EINVAL;
+	}
+}
+
 /**
  *	ata_scsi_mode_select_xlat - Simulate MODE SELECT 6, 10 commands
  *	@qc: Storage for translated ATA taskfile
@@ -3692,14 +3986,13 @@ static unsigned int ata_scsi_mode_select_xlat(struct ata_queued_cmd *qc)
 {
 	struct scsi_cmnd *scmd = qc->scsicmd;
 	const u8 *cdb = scmd->cmnd;
-	const u8 *p;
 	u8 pg, spg;
 	unsigned six_byte, pg_len, hdr_len, bd_len;
-	int len;
+	int len, ret;
 	u16 fp = (u16)-1;
 	u8 bp = 0xff;
-
-	VPRINTK("ENTER\n");
+	u8 buffer[64];
+	const u8 *p = buffer;
 
 	six_byte = (cdb[0] == MODE_SELECT);
 	if (six_byte) {
@@ -3716,7 +4009,7 @@ static unsigned int ata_scsi_mode_select_xlat(struct ata_queued_cmd *qc)
 			goto invalid_fld;
 		}
 
-		len = (cdb[7] << 8) + cdb[8];
+		len = get_unaligned_be16(&cdb[7]);
 		hdr_len = 8;
 	}
 
@@ -3731,16 +4024,18 @@ static unsigned int ata_scsi_mode_select_xlat(struct ata_queued_cmd *qc)
 	if (!scsi_sg_count(scmd) || scsi_sglist(scmd)->length < len)
 		goto invalid_param_len;
 
-	p = page_address(sg_page(scsi_sglist(scmd)));
-
 	/* Move past header and block descriptors.  */
 	if (len < hdr_len)
 		goto invalid_param_len;
 
+	if (!sg_copy_to_buffer(scsi_sglist(scmd), scsi_sg_count(scmd),
+			       buffer, sizeof(buffer)))
+		goto invalid_param_len;
+
 	if (six_byte)
 		bd_len = p[3];
 	else
-		bd_len = (p[6] << 8) + p[7];
+		bd_len = get_unaligned_be16(&p[6]);
 
 	len -= hdr_len;
 	p += hdr_len;
@@ -3764,7 +4059,7 @@ static unsigned int ata_scsi_mode_select_xlat(struct ata_queued_cmd *qc)
 			goto invalid_param_len;
 
 		spg = p[1];
-		pg_len = (p[2] << 8) | p[3];
+		pg_len = get_unaligned_be16(&p[2]);
 		p += 4;
 		len -= 4;
 	} else {
@@ -3778,13 +4073,29 @@ static unsigned int ata_scsi_mode_select_xlat(struct ata_queued_cmd *qc)
 	}
 
 	/*
-	 * No mode subpages supported (yet) but asking for _all_
-	 * subpages may be valid
+	 * Supported subpages: all subpages and ATA feature sub-page f2h of
+	 * the control page.
 	 */
-	if (spg && (spg != ALL_SUB_MPAGES)) {
-		fp = (p[0] & 0x40) ? 1 : 0;
-		fp += hdr_len + bd_len;
-		goto invalid_param;
+	if (spg) {
+		switch (spg) {
+		case ALL_SUB_MPAGES:
+			/* All subpages is not supported for the control page */
+			if (pg == CONTROL_MPAGE) {
+				fp = (p[0] & 0x40) ? 1 : 0;
+				fp += hdr_len + bd_len;
+				goto invalid_param;
+			}
+			break;
+		case ATA_FEATURE_SUB_MPAGE:
+			if (qc->dev->flags & ATA_DFLAG_CDL &&
+			    pg == CONTROL_MPAGE)
+				break;
+			fallthrough;
+		default:
+			fp = (p[0] & 0x40) ? 1 : 0;
+			fp += hdr_len + bd_len;
+			goto invalid_param;
+		}
 	}
 	if (pg_len > len)
 		goto invalid_param_len;
@@ -3797,14 +4108,16 @@ static unsigned int ata_scsi_mode_select_xlat(struct ata_queued_cmd *qc)
 		}
 		break;
 	case CONTROL_MPAGE:
-		if (ata_mselect_control(qc, p, pg_len, &fp) < 0) {
+		ret = ata_mselect_control(qc, spg, p, pg_len, &fp);
+		if (ret < 0) {
 			fp += hdr_len + bd_len;
 			goto invalid_param;
-		} else {
-			goto skip; /* No ATA command to send */
 		}
+		if (!ret)
+			goto skip; /* No ATA command to send */
 		break;
-	default:		/* invalid page code */
+	default:
+		/* Invalid page code */
 		fp = bd_len + hdr_len;
 		goto invalid_param;
 	}
@@ -3957,6 +4270,7 @@ static inline ata_xlat_func_t ata_get_xlat_func(struct ata_device *dev, u8 cmd)
 		return ata_scsi_write_same_xlat;
 
 	case SYNCHRONIZE_CACHE:
+	case SYNCHRONIZE_CACHE_16:
 		if (ata_try_flush_cache(dev))
 			return ata_scsi_flush_xlat;
 		break;
@@ -3975,7 +4289,6 @@ static inline ata_xlat_func_t ata_get_xlat_func(struct ata_device *dev, u8 cmd)
 	case MODE_SELECT:
 	case MODE_SELECT_10:
 		return ata_scsi_mode_select_xlat;
-		break;
 
 	case ZBC_IN:
 		return ata_scsi_zbc_in_xlat;
@@ -3996,72 +4309,58 @@ static inline ata_xlat_func_t ata_get_xlat_func(struct ata_device *dev, u8 cmd)
 	return NULL;
 }
 
-/**
- *	ata_scsi_dump_cdb - dump SCSI command contents to dmesg
- *	@ap: ATA port to which the command was being sent
- *	@cmd: SCSI command to dump
- *
- *	Prints the contents of a SCSI command via printk().
- */
-
-void ata_scsi_dump_cdb(struct ata_port *ap, struct scsi_cmnd *cmd)
-{
-#ifdef ATA_VERBOSE_DEBUG
-	struct scsi_device *scsidev = cmd->device;
-
-	VPRINTK("CDB (%u:%d,%d,%lld) %9ph\n",
-		ap->print_id,
-		scsidev->channel, scsidev->id, scsidev->lun,
-		cmd->cmnd);
-#endif
-}
-
 int __ata_scsi_queuecmd(struct scsi_cmnd *scmd, struct ata_device *dev)
 {
+	struct ata_port *ap = dev->link->ap;
 	u8 scsi_op = scmd->cmnd[0];
 	ata_xlat_func_t xlat_func;
-	int rc = 0;
+
+	/*
+	 * scsi_queue_rq() will defer commands if scsi_host_in_recovery().
+	 * However, this check is done without holding the ap->lock (a libata
+	 * specific lock), so we can have received an error irq since then,
+	 * therefore we must check if EH is pending or running, while holding
+	 * ap->lock.
+	 */
+	if (ata_port_eh_scheduled(ap))
+		return SCSI_MLQUEUE_DEVICE_BUSY;
+
+	if (unlikely(!scmd->cmd_len))
+		goto bad_cdb_len;
 
 	if (dev->class == ATA_DEV_ATA || dev->class == ATA_DEV_ZAC) {
-		if (unlikely(!scmd->cmd_len || scmd->cmd_len > dev->cdb_len))
+		if (unlikely(scmd->cmd_len > dev->cdb_len))
 			goto bad_cdb_len;
 
 		xlat_func = ata_get_xlat_func(dev, scsi_op);
-	} else {
-		if (unlikely(!scmd->cmd_len))
-			goto bad_cdb_len;
+	} else if (likely((scsi_op != ATA_16) || !atapi_passthru16)) {
+		/* relay SCSI command to ATAPI device */
+		int len = COMMAND_SIZE(scsi_op);
 
-		xlat_func = NULL;
-		if (likely((scsi_op != ATA_16) || !atapi_passthru16)) {
-			/* relay SCSI command to ATAPI device */
-			int len = COMMAND_SIZE(scsi_op);
-			if (unlikely(len > scmd->cmd_len ||
-				     len > dev->cdb_len ||
-				     scmd->cmd_len > ATAPI_CDB_LEN))
-				goto bad_cdb_len;
+		if (unlikely(len > scmd->cmd_len ||
+			     len > dev->cdb_len ||
+			     scmd->cmd_len > ATAPI_CDB_LEN))
+			goto bad_cdb_len;
 
-			xlat_func = atapi_xlat;
-		} else {
-			/* ATA_16 passthru, treat as an ATA command */
-			if (unlikely(scmd->cmd_len > 16))
-				goto bad_cdb_len;
+		xlat_func = atapi_xlat;
+	} else {
+		/* ATA_16 passthru, treat as an ATA command */
+		if (unlikely(scmd->cmd_len > 16))
+			goto bad_cdb_len;
 
-			xlat_func = ata_get_xlat_func(dev, scsi_op);
-		}
+		xlat_func = ata_get_xlat_func(dev, scsi_op);
 	}
 
 	if (xlat_func)
-		rc = ata_scsi_translate(dev, scmd, xlat_func);
-	else
-		ata_scsi_simulate(dev, scmd);
+		return ata_scsi_translate(dev, scmd, xlat_func);
 
-	return rc;
+	ata_scsi_simulate(dev, scmd);
+
+	return 0;
 
  bad_cdb_len:
-	DPRINTK("bad CDB len=%u, scsi_op=0x%02x, max=%u\n",
-		scmd->cmd_len, scsi_op, dev->cdb_len);
 	scmd->result = DID_ERROR << 16;
-	scmd->scsi_done(scmd);
+	scsi_done(scmd);
 	return 0;
 }
 
@@ -4096,14 +4395,12 @@ int ata_scsi_queuecmd(struct Scsi_Host *shost, struct scsi_cmnd *cmd)
 
 	spin_lock_irqsave(ap->lock, irq_flags);
 
-	ata_scsi_dump_cdb(ap, cmd);
-
 	dev = ata_scsi_find_dev(ap, scsidev);
 	if (likely(dev))
 		rc = __ata_scsi_queuecmd(cmd, dev);
 	else {
 		cmd->result = (DID_BAD_TARGET << 16);
-		cmd->scsi_done(cmd);
+		scsi_done(cmd);
 	}
 
 	spin_unlock_irqrestore(ap->lock, irq_flags);
@@ -4126,84 +4423,38 @@ EXPORT_SYMBOL_GPL(ata_scsi_queuecmd);
 
 void ata_scsi_simulate(struct ata_device *dev, struct scsi_cmnd *cmd)
 {
-	struct ata_scsi_args args;
 	const u8 *scsicmd = cmd->cmnd;
 	u8 tmp8;
 
-	args.dev = dev;
-	args.id = dev->id;
-	args.cmd = cmd;
-
 	switch(scsicmd[0]) {
 	case INQUIRY:
-		if (scsicmd[1] & 2)		   /* is CmdDt set?  */
-			ata_scsi_set_invalid_field(dev, cmd, 1, 0xff);
-		else if ((scsicmd[1] & 1) == 0)    /* is EVPD clear? */
-			ata_scsi_rbuf_fill(&args, ata_scsiop_inq_std);
-		else switch (scsicmd[2]) {
-		case 0x00:
-			ata_scsi_rbuf_fill(&args, ata_scsiop_inq_00);
-			break;
-		case 0x80:
-			ata_scsi_rbuf_fill(&args, ata_scsiop_inq_80);
-			break;
-		case 0x83:
-			ata_scsi_rbuf_fill(&args, ata_scsiop_inq_83);
-			break;
-		case 0x89:
-			ata_scsi_rbuf_fill(&args, ata_scsiop_inq_89);
-			break;
-		case 0xb0:
-			ata_scsi_rbuf_fill(&args, ata_scsiop_inq_b0);
-			break;
-		case 0xb1:
-			ata_scsi_rbuf_fill(&args, ata_scsiop_inq_b1);
-			break;
-		case 0xb2:
-			ata_scsi_rbuf_fill(&args, ata_scsiop_inq_b2);
-			break;
-		case 0xb6:
-			if (dev->flags & ATA_DFLAG_ZAC) {
-				ata_scsi_rbuf_fill(&args, ata_scsiop_inq_b6);
-				break;
-			}
-			/* Fallthrough */
-		default:
-			ata_scsi_set_invalid_field(dev, cmd, 2, 0xff);
-			break;
-		}
+		ata_scsi_rbuf_fill(dev, cmd, ata_scsiop_inquiry);
 		break;
 
 	case MODE_SENSE:
 	case MODE_SENSE_10:
-		ata_scsi_rbuf_fill(&args, ata_scsiop_mode_sense);
+		ata_scsi_rbuf_fill(dev, cmd, ata_scsiop_mode_sense);
 		break;
 
 	case READ_CAPACITY:
-		ata_scsi_rbuf_fill(&args, ata_scsiop_read_cap);
-		break;
-
 	case SERVICE_ACTION_IN_16:
-		if ((scsicmd[1] & 0x1f) == SAI_READ_CAPACITY_16)
-			ata_scsi_rbuf_fill(&args, ata_scsiop_read_cap);
-		else
-			ata_scsi_set_invalid_field(dev, cmd, 1, 0xff);
+		ata_scsi_rbuf_fill(dev, cmd, ata_scsiop_read_cap);
 		break;
 
 	case REPORT_LUNS:
-		ata_scsi_rbuf_fill(&args, ata_scsiop_report_luns);
+		ata_scsi_rbuf_fill(dev, cmd, ata_scsiop_report_luns);
 		break;
 
 	case REQUEST_SENSE:
 		ata_scsi_set_sense(dev, cmd, 0, 0, 0);
-		cmd->result = (DRIVER_SENSE << 24);
 		break;
 
 	/* if we reach this, then writeback caching is disabled,
 	 * turning this into a no-op.
 	 */
 	case SYNCHRONIZE_CACHE:
-		/* fall through */
+	case SYNCHRONIZE_CACHE_16:
+		fallthrough;
 
 	/* no-op's, complete with success */
 	case REZERO_UNIT:
@@ -4219,10 +4470,7 @@ void ata_scsi_simulate(struct ata_device *dev, struct scsi_cmnd *cmd)
 		break;
 
 	case MAINTENANCE_IN:
-		if (scsicmd[1] == MI_REPORT_SUPPORTED_OPERATION_CODES)
-			ata_scsi_rbuf_fill(&args, ata_scsiop_maint_in);
-		else
-			ata_scsi_set_invalid_field(dev, cmd, 1, 0xff);
+		ata_scsi_rbuf_fill(dev, cmd, ata_scsiop_maint_in);
 		break;
 
 	/* all other commands */
@@ -4232,10 +4480,10 @@ void ata_scsi_simulate(struct ata_device *dev, struct scsi_cmnd *cmd)
 		break;
 	}
 
-	cmd->scsi_done(cmd);
+	scsi_done(cmd);
 }
 
-int ata_scsi_add_hosts(struct ata_host *host, struct scsi_host_template *sht)
+int ata_scsi_add_hosts(struct ata_host *host, const struct scsi_host_template *sht)
 {
 	int i, rc;
 
@@ -4389,24 +4637,23 @@ void ata_scsi_scan_host(struct ata_port *ap, int sync)
  *	ata_scsi_offline_dev - offline attached SCSI device
  *	@dev: ATA device to offline attached SCSI device for
  *
- *	This function is called from ata_eh_hotplug() and responsible
- *	for taking the SCSI device attached to @dev offline.  This
- *	function is called with host lock which protects dev->sdev
- *	against clearing.
+ *	This function is called from ata_eh_detach_dev() and is responsible for
+ *	taking the SCSI device attached to @dev offline.  This function is
+ *	called with host lock which protects dev->sdev against clearing.
  *
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
  *
  *	RETURNS:
- *	1 if attached SCSI device exists, 0 otherwise.
+ *	true if attached SCSI device exists, false otherwise.
  */
-int ata_scsi_offline_dev(struct ata_device *dev)
+bool ata_scsi_offline_dev(struct ata_device *dev)
 {
 	if (dev->sdev) {
 		scsi_device_set_state(dev->sdev, SDEV_OFFLINE);
-		return 1;
+		return true;
 	}
-	return 0;
+	return false;
 }
 
 /**
@@ -4476,16 +4723,15 @@ static void ata_scsi_handle_link_detach(struct ata_link *link)
 	ata_for_each_dev(dev, link, ALL) {
 		unsigned long flags;
 
-		if (!(dev->flags & ATA_DFLAG_DETACHED))
+		spin_lock_irqsave(ap->lock, flags);
+		if (!(dev->flags & ATA_DFLAG_DETACHED)) {
+			spin_unlock_irqrestore(ap->lock, flags);
 			continue;
+		}
 
-		spin_lock_irqsave(ap->lock, flags);
 		dev->flags &= ~ATA_DFLAG_DETACHED;
 		spin_unlock_irqrestore(ap->lock, flags);
 
-		if (zpodd_dev_enabled(dev))
-			zpodd_exit(dev);
-
 		ata_scsi_remove_dev(dev);
 	}
 }
@@ -4525,12 +4771,9 @@ void ata_scsi_hotplug(struct work_struct *work)
 		container_of(work, struct ata_port, hotplug_task.work);
 	int i;
 
-	if (ap->pflags & ATA_PFLAG_UNLOADING) {
-		DPRINTK("ENTER/EXIT - unloading\n");
+	if (ap->pflags & ATA_PFLAG_UNLOADING)
 		return;
-	}
 
-	DPRINTK("ENTER\n");
 	mutex_lock(&ap->scsi_scan_mutex);
 
 	/* Unplug detached devices.  We cannot use link iterator here
@@ -4546,7 +4789,6 @@ void ata_scsi_hotplug(struct work_struct *work)
 	ata_scsi_scan_host(ap, 0);
 
 	mutex_unlock(&ap->scsi_scan_mutex);
-	DPRINTK("EXIT\n");
 }
 
 /**
@@ -4572,9 +4814,6 @@ int ata_scsi_user_scan(struct Scsi_Host *shost, unsigned int channel,
 	unsigned long flags;
 	int devno, rc = 0;
 
-	if (!ap->ops->error_handler)
-		return -EOPNOTSUPP;
-
 	if (lun != SCAN_WILD_CARD && lun)
 		return -EINVAL;
 
@@ -4632,10 +4871,12 @@ int ata_scsi_user_scan(struct Scsi_Host *shost, unsigned int channel,
 void ata_scsi_dev_rescan(struct work_struct *work)
 {
 	struct ata_port *ap =
-		container_of(work, struct ata_port, scsi_rescan_task);
+		container_of(work, struct ata_port, scsi_rescan_task.work);
 	struct ata_link *link;
 	struct ata_device *dev;
 	unsigned long flags;
+	bool do_resume;
+	int ret = 0;
 
 	mutex_lock(&ap->scsi_scan_mutex);
 	spin_lock_irqsave(ap->lock, flags);
@@ -4644,18 +4885,45 @@ void ata_scsi_dev_rescan(struct work_struct *work)
 		ata_for_each_dev(dev, link, ENABLED) {
 			struct scsi_device *sdev = dev->sdev;
 
+			/*
+			 * If the port was suspended before this was scheduled,
+			 * bail out.
+			 */
+			if (ap->pflags & ATA_PFLAG_SUSPENDED)
+				goto unlock_ap;
+
 			if (!sdev)
 				continue;
 			if (scsi_device_get(sdev))
 				continue;
 
+			do_resume = dev->flags & ATA_DFLAG_RESUMING;
+
 			spin_unlock_irqrestore(ap->lock, flags);
-			scsi_rescan_device(&(sdev->sdev_gendev));
+			if (do_resume) {
+				ret = scsi_resume_device(sdev);
+				if (ret == -EWOULDBLOCK) {
+					scsi_device_put(sdev);
+					goto unlock_scan;
+				}
+				dev->flags &= ~ATA_DFLAG_RESUMING;
+			}
+			ret = scsi_rescan_device(sdev);
 			scsi_device_put(sdev);
 			spin_lock_irqsave(ap->lock, flags);
+
+			if (ret)
+				goto unlock_ap;
 		}
 	}
 
+unlock_ap:
 	spin_unlock_irqrestore(ap->lock, flags);
+unlock_scan:
 	mutex_unlock(&ap->scsi_scan_mutex);
+
+	/* Reschedule with a delay if scsi_rescan_device() returned an error */
+	if (ret)
+		schedule_delayed_work(&ap->scsi_rescan_task,
+				      msecs_to_jiffies(5));
 }
diff --git a/drivers/ata/libata-sff.c b/drivers/ata/libata-sff.c
index ae7189d1a568..785b6e371abf 100644
--- a/drivers/ata/libata-sff.c
+++ b/drivers/ata/libata-sff.c
@@ -18,7 +18,7 @@
 #include <linux/module.h>
 #include <linux/libata.h>
 #include <linux/highmem.h>
-
+#include <trace/events/libata.h>
 #include "libata.h"
 
 static struct workqueue_struct *ata_sff_wq;
@@ -26,16 +26,15 @@ static struct workqueue_struct *ata_sff_wq;
 const struct ata_port_operations ata_sff_port_ops = {
 	.inherits		= &ata_base_port_ops,
 
-	.qc_prep		= ata_noop_qc_prep,
 	.qc_issue		= ata_sff_qc_issue,
 	.qc_fill_rtf		= ata_sff_qc_fill_rtf,
 
 	.freeze			= ata_sff_freeze,
 	.thaw			= ata_sff_thaw,
-	.prereset		= ata_sff_prereset,
-	.softreset		= ata_sff_softreset,
-	.hardreset		= sata_sff_hardreset,
-	.postreset		= ata_sff_postreset,
+	.reset.prereset		= ata_sff_prereset,
+	.reset.softreset	= ata_sff_softreset,
+	.reset.hardreset	= sata_sff_hardreset,
+	.reset.postreset	= ata_sff_postreset,
 	.error_handler		= ata_sff_error_handler,
 
 	.sff_dev_select		= ata_sff_dev_select,
@@ -70,22 +69,35 @@ EXPORT_SYMBOL_GPL(ata_sff_check_status);
 /**
  *	ata_sff_altstatus - Read device alternate status reg
  *	@ap: port where the device is
+ *	@status: pointer to a status value
  *
- *	Reads ATA taskfile alternate status register for
- *	currently-selected device and return its value.
+ *	Reads ATA alternate status register for currently-selected device
+ *	and return its value.
  *
- *	Note: may NOT be used as the check_altstatus() entry in
- *	ata_port_operations.
+ *	RETURN:
+ *	true if the register exists, false if not.
  *
  *	LOCKING:
  *	Inherited from caller.
  */
-static u8 ata_sff_altstatus(struct ata_port *ap)
+static bool ata_sff_altstatus(struct ata_port *ap, u8 *status)
 {
-	if (ap->ops->sff_check_altstatus)
-		return ap->ops->sff_check_altstatus(ap);
+	u8 tmp;
 
-	return ioread8(ap->ioaddr.altstatus_addr);
+	if (ap->ops->sff_check_altstatus) {
+		tmp = ap->ops->sff_check_altstatus(ap);
+		goto read;
+	}
+	if (ap->ioaddr.altstatus_addr) {
+		tmp = ioread8(ap->ioaddr.altstatus_addr);
+		goto read;
+	}
+	return false;
+
+read:
+	if (status)
+		*status = tmp;
+	return true;
 }
 
 /**
@@ -104,12 +116,9 @@ static u8 ata_sff_irq_status(struct ata_port *ap)
 {
 	u8 status;
 
-	if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) {
-		status = ata_sff_altstatus(ap);
-		/* Not us: We are busy */
-		if (status & ATA_BUSY)
-			return status;
-	}
+	/* Not us: We are busy */
+	if (ata_sff_altstatus(ap, &status) && (status & ATA_BUSY))
+		return status;
 	/* Clear INTRQ latch */
 	status = ap->ops->sff_check_status(ap);
 	return status;
@@ -129,10 +138,7 @@ static u8 ata_sff_irq_status(struct ata_port *ap)
 
 static void ata_sff_sync(struct ata_port *ap)
 {
-	if (ap->ops->sff_check_altstatus)
-		ap->ops->sff_check_altstatus(ap);
-	else if (ap->ioaddr.altstatus_addr)
-		ioread8(ap->ioaddr.altstatus_addr);
+	ata_sff_altstatus(ap, NULL);
 }
 
 /**
@@ -164,12 +170,12 @@ EXPORT_SYMBOL_GPL(ata_sff_pause);
 
 void ata_sff_dma_pause(struct ata_port *ap)
 {
-	if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) {
-		/* An altstatus read will cause the needed delay without
-		   messing up the IRQ status */
-		ata_sff_altstatus(ap);
+	/*
+	 * An altstatus read will cause the needed delay without
+	 * messing up the IRQ status
+	 */
+	if (ata_sff_altstatus(ap, NULL))
 		return;
-	}
 	/* There are no DMA controllers without ctl. BUG here to ensure
 	   we never violate the HDMA1:0 transition timing and risk
 	   corruption. */
@@ -177,62 +183,6 @@ void ata_sff_dma_pause(struct ata_port *ap)
 }
 EXPORT_SYMBOL_GPL(ata_sff_dma_pause);
 
-/**
- *	ata_sff_busy_sleep - sleep until BSY clears, or timeout
- *	@ap: port containing status register to be polled
- *	@tmout_pat: impatience timeout in msecs
- *	@tmout: overall timeout in msecs
- *
- *	Sleep until ATA Status register bit BSY clears,
- *	or a timeout occurs.
- *
- *	LOCKING:
- *	Kernel thread context (may sleep).
- *
- *	RETURNS:
- *	0 on success, -errno otherwise.
- */
-int ata_sff_busy_sleep(struct ata_port *ap,
-		       unsigned long tmout_pat, unsigned long tmout)
-{
-	unsigned long timer_start, timeout;
-	u8 status;
-
-	status = ata_sff_busy_wait(ap, ATA_BUSY, 300);
-	timer_start = jiffies;
-	timeout = ata_deadline(timer_start, tmout_pat);
-	while (status != 0xff && (status & ATA_BUSY) &&
-	       time_before(jiffies, timeout)) {
-		ata_msleep(ap, 50);
-		status = ata_sff_busy_wait(ap, ATA_BUSY, 3);
-	}
-
-	if (status != 0xff && (status & ATA_BUSY))
-		ata_port_warn(ap,
-			      "port is slow to respond, please be patient (Status 0x%x)\n",
-			      status);
-
-	timeout = ata_deadline(timer_start, tmout);
-	while (status != 0xff && (status & ATA_BUSY) &&
-	       time_before(jiffies, timeout)) {
-		ata_msleep(ap, 50);
-		status = ap->ops->sff_check_status(ap);
-	}
-
-	if (status == 0xff)
-		return -ENODEV;
-
-	if (status & ATA_BUSY) {
-		ata_port_err(ap,
-			     "port failed to respond (%lu secs, Status 0x%x)\n",
-			     DIV_ROUND_UP(tmout, 1000), status);
-		return -EBUSY;
-	}
-
-	return 0;
-}
-EXPORT_SYMBOL_GPL(ata_sff_busy_sleep);
-
 static int ata_sff_check_ready(struct ata_link *link)
 {
 	u8 status = link->ap->ops->sff_check_status(link->ap);
@@ -265,20 +215,26 @@ EXPORT_SYMBOL_GPL(ata_sff_wait_ready);
  *	@ap: port where the device is
  *	@ctl: value to write
  *
- *	Writes ATA taskfile device control register.
+ *	Writes ATA device control register.
  *
- *	Note: may NOT be used as the sff_set_devctl() entry in
- *	ata_port_operations.
+ *	RETURN:
+ *	true if the register exists, false if not.
  *
  *	LOCKING:
  *	Inherited from caller.
  */
-static void ata_sff_set_devctl(struct ata_port *ap, u8 ctl)
+static bool ata_sff_set_devctl(struct ata_port *ap, u8 ctl)
 {
-	if (ap->ops->sff_set_devctl)
+	if (ap->ops->sff_set_devctl) {
 		ap->ops->sff_set_devctl(ap, ctl);
-	else
+		return true;
+	}
+	if (ap->ioaddr.ctl_addr) {
 		iowrite8(ctl, ap->ioaddr.ctl_addr);
+		return true;
+	}
+
+	return false;
 }
 
 /**
@@ -330,10 +286,6 @@ EXPORT_SYMBOL_GPL(ata_sff_dev_select);
 static void ata_dev_select(struct ata_port *ap, unsigned int device,
 			   unsigned int wait, unsigned int can_sleep)
 {
-	if (ata_msg_probe(ap))
-		ata_port_info(ap, "ata_dev_select: ENTER, device %u, wait %u\n",
-			      device, wait);
-
 	if (wait)
 		ata_wait_idle(ap);
 
@@ -361,8 +313,6 @@ static void ata_dev_select(struct ata_port *ap, unsigned int device,
  */
 void ata_sff_irq_on(struct ata_port *ap)
 {
-	struct ata_ioports *ioaddr = &ap->ioaddr;
-
 	if (ap->ops->sff_irq_on) {
 		ap->ops->sff_irq_on(ap);
 		return;
@@ -371,8 +321,7 @@ void ata_sff_irq_on(struct ata_port *ap)
 	ap->ctl &= ~ATA_NIEN;
 	ap->last_ctl = ap->ctl;
 
-	if (ap->ops->sff_set_devctl || ioaddr->ctl_addr)
-		ata_sff_set_devctl(ap, ap->ctl);
+	ata_sff_set_devctl(ap, ap->ctl);
 	ata_wait_idle(ap);
 
 	if (ap->ops->sff_irq_clear)
@@ -409,12 +358,6 @@ void ata_sff_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
 		iowrite8(tf->hob_lbal, ioaddr->lbal_addr);
 		iowrite8(tf->hob_lbam, ioaddr->lbam_addr);
 		iowrite8(tf->hob_lbah, ioaddr->lbah_addr);
-		VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
-			tf->hob_feature,
-			tf->hob_nsect,
-			tf->hob_lbal,
-			tf->hob_lbam,
-			tf->hob_lbah);
 	}
 
 	if (is_addr) {
@@ -423,18 +366,10 @@ void ata_sff_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
 		iowrite8(tf->lbal, ioaddr->lbal_addr);
 		iowrite8(tf->lbam, ioaddr->lbam_addr);
 		iowrite8(tf->lbah, ioaddr->lbah_addr);
-		VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
-			tf->feature,
-			tf->nsect,
-			tf->lbal,
-			tf->lbam,
-			tf->lbah);
 	}
 
-	if (tf->flags & ATA_TFLAG_DEVICE) {
+	if (tf->flags & ATA_TFLAG_DEVICE)
 		iowrite8(tf->device, ioaddr->device_addr);
-		VPRINTK("device 0x%X\n", tf->device);
-	}
 
 	ata_wait_idle(ap);
 }
@@ -457,8 +392,8 @@ void ata_sff_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
 {
 	struct ata_ioports *ioaddr = &ap->ioaddr;
 
-	tf->command = ata_sff_check_status(ap);
-	tf->feature = ioread8(ioaddr->error_addr);
+	tf->status = ata_sff_check_status(ap);
+	tf->error = ioread8(ioaddr->error_addr);
 	tf->nsect = ioread8(ioaddr->nsect_addr);
 	tf->lbal = ioread8(ioaddr->lbal_addr);
 	tf->lbam = ioread8(ioaddr->lbam_addr);
@@ -494,8 +429,6 @@ EXPORT_SYMBOL_GPL(ata_sff_tf_read);
  */
 void ata_sff_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
 {
-	DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
-
 	iowrite8(tf->command, ap->ioaddr.command_addr);
 	ata_sff_pause(ap);
 }
@@ -505,6 +438,7 @@ EXPORT_SYMBOL_GPL(ata_sff_exec_command);
  *	ata_tf_to_host - issue ATA taskfile to host controller
  *	@ap: port to which command is being issued
  *	@tf: ATA taskfile register set
+ *	@tag: tag of the associated command
  *
  *	Issues ATA taskfile register set to ATA host controller,
  *	with proper synchronization with interrupt handler and
@@ -514,9 +448,12 @@ EXPORT_SYMBOL_GPL(ata_sff_exec_command);
  *	spin_lock_irqsave(host lock)
  */
 static inline void ata_tf_to_host(struct ata_port *ap,
-				  const struct ata_taskfile *tf)
+				  const struct ata_taskfile *tf,
+				  unsigned int tag)
 {
+	trace_ata_tf_load(ap, tf);
 	ap->ops->sff_tf_load(ap, tf);
+	trace_ata_exec_command(ap, tf, tag);
 	ap->ops->sff_exec_command(ap, tf);
 }
 
@@ -637,6 +574,20 @@ unsigned int ata_sff_data_xfer32(struct ata_queued_cmd *qc, unsigned char *buf,
 }
 EXPORT_SYMBOL_GPL(ata_sff_data_xfer32);
 
+static void ata_pio_xfer(struct ata_queued_cmd *qc, struct page *page,
+		unsigned int offset, size_t xfer_size)
+{
+	bool do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
+	unsigned char *buf;
+
+	buf = kmap_atomic(page);
+	qc->ap->ops->sff_data_xfer(qc, buf + offset, xfer_size, do_write);
+	kunmap_atomic(buf);
+
+	if (!do_write && !PageSlab(page))
+		flush_dcache_page(page);
+}
+
 /**
  *	ata_pio_sector - Transfer a sector of data.
  *	@qc: Command on going
@@ -648,11 +599,9 @@ EXPORT_SYMBOL_GPL(ata_sff_data_xfer32);
  */
 static void ata_pio_sector(struct ata_queued_cmd *qc)
 {
-	int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
 	struct ata_port *ap = qc->ap;
 	struct page *page;
-	unsigned int offset;
-	unsigned char *buf;
+	unsigned int offset, count;
 
 	if (!qc->cursg) {
 		qc->curbytes = qc->nbytes;
@@ -665,21 +614,30 @@ static void ata_pio_sector(struct ata_queued_cmd *qc)
 	offset = qc->cursg->offset + qc->cursg_ofs;
 
 	/* get the current page and offset */
-	page = nth_page(page, (offset >> PAGE_SHIFT));
+	page += offset >> PAGE_SHIFT;
 	offset %= PAGE_SIZE;
 
-	DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
+	/* don't overrun current sg */
+	count = min(qc->cursg->length - qc->cursg_ofs, qc->sect_size);
 
-	/* do the actual data transfer */
-	buf = kmap_atomic(page);
-	ap->ops->sff_data_xfer(qc, buf + offset, qc->sect_size, do_write);
-	kunmap_atomic(buf);
+	trace_ata_sff_pio_transfer_data(qc, offset, count);
 
-	if (!do_write && !PageSlab(page))
-		flush_dcache_page(page);
+	/*
+	 * Split the transfer when it splits a page boundary.  Note that the
+	 * split still has to be dword aligned like all ATA data transfers.
+	 */
+	WARN_ON_ONCE(offset % 4);
+	if (offset + count > PAGE_SIZE) {
+		unsigned int split_len = PAGE_SIZE - offset;
 
-	qc->curbytes += qc->sect_size;
-	qc->cursg_ofs += qc->sect_size;
+		ata_pio_xfer(qc, page, offset, split_len);
+		ata_pio_xfer(qc, page + 1, 0, count - split_len);
+	} else {
+		ata_pio_xfer(qc, page, offset, count);
+	}
+
+	qc->curbytes += count;
+	qc->cursg_ofs += count;
 
 	if (qc->cursg_ofs == qc->cursg->length) {
 		qc->cursg = sg_next(qc->cursg);
@@ -731,7 +689,7 @@ static void ata_pio_sectors(struct ata_queued_cmd *qc)
 static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc)
 {
 	/* send SCSI cdb */
-	DPRINTK("send cdb\n");
+	trace_atapi_send_cdb(qc, 0, qc->dev->cdb_len);
 	WARN_ON_ONCE(qc->dev->cdb_len < 12);
 
 	ap->ops->sff_data_xfer(qc, qc->cdb, qc->dev->cdb_len, 1);
@@ -749,6 +707,7 @@ static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc)
 	case ATAPI_PROT_DMA:
 		ap->hsm_task_state = HSM_ST_LAST;
 		/* initiate bmdma */
+		trace_ata_bmdma_start(ap, &qc->tf, qc->tag);
 		ap->ops->bmdma_start(qc);
 		break;
 #endif /* CONFIG_ATA_BMDMA */
@@ -762,7 +721,7 @@ static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc)
  *	@qc: Command on going
  *	@bytes: number of bytes
  *
- *	Transfer Transfer data from/to the ATAPI device.
+ *	Transfer data from/to the ATAPI device.
  *
  *	LOCKING:
  *	Inherited from caller.
@@ -792,7 +751,7 @@ next_sg:
 	offset = sg->offset + qc->cursg_ofs;
 
 	/* get the current page and offset */
-	page = nth_page(page, (offset >> PAGE_SHIFT));
+	page += offset >> PAGE_SHIFT;
 	offset %= PAGE_SIZE;
 
 	/* don't overrun current sg */
@@ -801,7 +760,7 @@ next_sg:
 	/* don't cross page boundaries */
 	count = min(count, (unsigned int)PAGE_SIZE - offset);
 
-	DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
+	trace_atapi_pio_transfer_data(qc, offset, count);
 
 	/* do the actual data transfer */
 	buf = kmap_atomic(page);
@@ -869,8 +828,6 @@ static void atapi_pio_bytes(struct ata_queued_cmd *qc)
 	if (unlikely(!bytes))
 		goto atapi_check;
 
-	VPRINTK("ata%u: xfering %d bytes\n", ap->print_id, bytes);
-
 	if (unlikely(__atapi_pio_bytes(qc, bytes)))
 		goto err_out;
 	ata_sff_sync(ap); /* flush */
@@ -927,31 +884,21 @@ static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
 {
 	struct ata_port *ap = qc->ap;
 
-	if (ap->ops->error_handler) {
-		if (in_wq) {
-			/* EH might have kicked in while host lock is
-			 * released.
-			 */
-			qc = ata_qc_from_tag(ap, qc->tag);
-			if (qc) {
-				if (likely(!(qc->err_mask & AC_ERR_HSM))) {
-					ata_sff_irq_on(ap);
-					ata_qc_complete(qc);
-				} else
-					ata_port_freeze(ap);
-			}
-		} else {
-			if (likely(!(qc->err_mask & AC_ERR_HSM)))
+	if (in_wq) {
+		/* EH might have kicked in while host lock is released. */
+		qc = ata_qc_from_tag(ap, qc->tag);
+		if (qc) {
+			if (likely(!(qc->err_mask & AC_ERR_HSM))) {
+				ata_sff_irq_on(ap);
 				ata_qc_complete(qc);
-			else
+			} else
 				ata_port_freeze(ap);
 		}
 	} else {
-		if (in_wq) {
-			ata_sff_irq_on(ap);
-			ata_qc_complete(qc);
-		} else
+		if (likely(!(qc->err_mask & AC_ERR_HSM)))
 			ata_qc_complete(qc);
+		else
+			ata_port_freeze(ap);
 	}
 }
 
@@ -983,8 +930,7 @@ int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
 	WARN_ON_ONCE(in_wq != ata_hsm_ok_in_wq(ap, qc));
 
 fsm_start:
-	DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n",
-		ap->print_id, qc->tf.protocol, ap->hsm_task_state, status);
+	trace_ata_sff_hsm_state(qc, status);
 
 	switch (ap->hsm_task_state) {
 	case HSM_ST_FIRST:
@@ -1025,7 +971,7 @@ fsm_start:
 			 * We ignore ERR here to workaround and proceed sending
 			 * the CDB.
 			 */
-			if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) {
+			if (!(qc->dev->quirks & ATA_QUIRK_STUCK_ERR)) {
 				ata_ehi_push_desc(ehi, "ST_FIRST: "
 					"DRQ=1 with device error, "
 					"dev_stat 0x%X", status);
@@ -1100,8 +1046,8 @@ fsm_start:
 					 * IDENTIFY, it's likely a phantom
 					 * device.  Mark hint.
 					 */
-					if (qc->dev->horkage &
-					    ATA_HORKAGE_DIAGNOSTIC)
+					if (qc->dev->quirks &
+					    ATA_QUIRK_DIAGNOSTIC)
 						qc->err_mask |=
 							AC_ERR_NODEV_HINT;
 				} else {
@@ -1185,8 +1131,7 @@ fsm_start:
 		}
 
 		/* no more data to transfer */
-		DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n",
-			ap->print_id, qc->dev->devno, status);
+		trace_ata_sff_hsm_command_complete(qc, status);
 
 		WARN_ON_ONCE(qc->err_mask & (AC_ERR_DEV | AC_ERR_HSM));
 
@@ -1243,7 +1188,7 @@ EXPORT_SYMBOL_GPL(ata_sff_queue_pio_task);
 
 void ata_sff_flush_pio_task(struct ata_port *ap)
 {
-	DPRINTK("ENTER\n");
+	trace_ata_sff_flush_pio_task(ap);
 
 	cancel_delayed_work_sync(&ap->sff_pio_task);
 
@@ -1260,9 +1205,6 @@ void ata_sff_flush_pio_task(struct ata_port *ap)
 	spin_unlock_irq(ap->lock);
 
 	ap->sff_pio_task_link = NULL;
-
-	if (ata_msg_ctl(ap))
-		ata_port_dbg(ap, "%s: EXIT\n", __func__);
 }
 
 static void ata_sff_pio_task(struct work_struct *work)
@@ -1357,7 +1299,7 @@ unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc)
 		if (qc->tf.flags & ATA_TFLAG_POLLING)
 			ata_qc_set_polling(qc);
 
-		ata_tf_to_host(ap, &qc->tf);
+		ata_tf_to_host(ap, &qc->tf, qc->tag);
 		ap->hsm_task_state = HSM_ST_LAST;
 
 		if (qc->tf.flags & ATA_TFLAG_POLLING)
@@ -1369,7 +1311,7 @@ unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc)
 		if (qc->tf.flags & ATA_TFLAG_POLLING)
 			ata_qc_set_polling(qc);
 
-		ata_tf_to_host(ap, &qc->tf);
+		ata_tf_to_host(ap, &qc->tf, qc->tag);
 
 		if (qc->tf.flags & ATA_TFLAG_WRITE) {
 			/* PIO data out protocol */
@@ -1399,7 +1341,7 @@ unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc)
 		if (qc->tf.flags & ATA_TFLAG_POLLING)
 			ata_qc_set_polling(qc);
 
-		ata_tf_to_host(ap, &qc->tf);
+		ata_tf_to_host(ap, &qc->tf, qc->tag);
 
 		ap->hsm_task_state = HSM_ST_FIRST;
 
@@ -1426,14 +1368,10 @@ EXPORT_SYMBOL_GPL(ata_sff_qc_issue);
  *
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
- *
- *	RETURNS:
- *	true indicating that result TF is successfully filled.
  */
-bool ata_sff_qc_fill_rtf(struct ata_queued_cmd *qc)
+void ata_sff_qc_fill_rtf(struct ata_queued_cmd *qc)
 {
 	qc->ap->ops->sff_tf_read(qc->ap, &qc->result_tf);
-	return true;
 }
 EXPORT_SYMBOL_GPL(ata_sff_qc_fill_rtf);
 
@@ -1459,8 +1397,7 @@ static unsigned int __ata_sff_port_intr(struct ata_port *ap,
 {
 	u8 status;
 
-	VPRINTK("ata%u: protocol %d task_state %d\n",
-		ap->print_id, qc->tf.protocol, ap->hsm_task_state);
+	trace_ata_sff_port_intr(qc, hsmv_on_idle);
 
 	/* Check whether we are expecting interrupt in this state */
 	switch (ap->hsm_task_state) {
@@ -1628,7 +1565,7 @@ EXPORT_SYMBOL_GPL(ata_sff_interrupt);
 
 void ata_sff_lost_interrupt(struct ata_port *ap)
 {
-	u8 status;
+	u8 status = 0;
 	struct ata_queued_cmd *qc;
 
 	/* Only one outstanding command per SFF channel */
@@ -1638,14 +1575,14 @@ void ata_sff_lost_interrupt(struct ata_port *ap)
 		return;
 	/* See if the controller thinks it is still busy - if so the command
 	   isn't a lost IRQ but is still in progress */
-	status = ata_sff_altstatus(ap);
+	if (WARN_ON_ONCE(!ata_sff_altstatus(ap, &status)))
+		return;
 	if (status & ATA_BUSY)
 		return;
 
 	/* There was a command running, we are no longer busy and we have
 	   no interrupt. */
-	ata_port_warn(ap, "lost interrupt (Status 0x%x)\n",
-								status);
+	ata_port_warn(ap, "lost interrupt (Status 0x%x)\n", status);
 	/* Run the host interrupt logic as if the interrupt had not been
 	   lost */
 	ata_sff_port_intr(ap, qc);
@@ -1666,8 +1603,7 @@ void ata_sff_freeze(struct ata_port *ap)
 	ap->ctl |= ATA_NIEN;
 	ap->last_ctl = ap->ctl;
 
-	if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr)
-		ata_sff_set_devctl(ap, ap->ctl);
+	ata_sff_set_devctl(ap, ap->ctl);
 
 	/* Under certain circumstances, some controllers raise IRQ on
 	 * ATA_NIEN manipulation.  Also, many controllers fail to mask
@@ -1712,16 +1648,15 @@ EXPORT_SYMBOL_GPL(ata_sff_thaw);
  *	Kernel thread context (may sleep)
  *
  *	RETURNS:
- *	0 on success, -errno otherwise.
+ *	Always 0.
  */
 int ata_sff_prereset(struct ata_link *link, unsigned long deadline)
 {
 	struct ata_eh_context *ehc = &link->eh_context;
 	int rc;
 
-	rc = ata_std_prereset(link, deadline);
-	if (rc)
-		return rc;
+	/* The standard prereset is best-effort and always returns 0 */
+	ata_std_prereset(link, deadline);
 
 	/* if we're about to do hardreset, nothing more to do */
 	if (ehc->i.action & ATA_EH_HARDRESET)
@@ -1756,10 +1691,13 @@ EXPORT_SYMBOL_GPL(ata_sff_prereset);
  *	correctly storing and echoing back the
  *	ATA shadow register contents.
  *
+ *	RETURN:
+ *	true if device is present, false if not.
+ *
  *	LOCKING:
  *	caller.
  */
-static unsigned int ata_devchk(struct ata_port *ap, unsigned int device)
+static bool ata_devchk(struct ata_port *ap, unsigned int device)
 {
 	struct ata_ioports *ioaddr = &ap->ioaddr;
 	u8 nsect, lbal;
@@ -1779,9 +1717,9 @@ static unsigned int ata_devchk(struct ata_port *ap, unsigned int device)
 	lbal = ioread8(ioaddr->lbal_addr);
 
 	if ((nsect == 0x55) && (lbal == 0xaa))
-		return 1;	/* we found a device */
+		return true;	/* we found a device */
 
-	return 0;		/* nothing found */
+	return false;		/* nothing found */
 }
 
 /**
@@ -1818,14 +1756,14 @@ unsigned int ata_sff_dev_classify(struct ata_device *dev, int present,
 	memset(&tf, 0, sizeof(tf));
 
 	ap->ops->sff_tf_read(ap, &tf);
-	err = tf.feature;
+	err = tf.error;
 	if (r_err)
 		*r_err = err;
 
 	/* see if device passed diags: continue and warn later */
 	if (err == 0)
 		/* diagnostic fail : do nothing _YET_ */
-		dev->horkage |= ATA_HORKAGE_DIAGNOSTIC;
+		dev->quirks |= ATA_QUIRK_DIAGNOSTIC;
 	else if (err == 1)
 		/* do nothing */ ;
 	else if ((dev->devno == 0) && (err == 0x81))
@@ -1834,23 +1772,26 @@ unsigned int ata_sff_dev_classify(struct ata_device *dev, int present,
 		return ATA_DEV_NONE;
 
 	/* determine if device is ATA or ATAPI */
-	class = ata_dev_classify(&tf);
-
-	if (class == ATA_DEV_UNKNOWN) {
-		/* If the device failed diagnostic, it's likely to
+	class = ata_port_classify(ap, &tf);
+	switch (class) {
+	case ATA_DEV_UNKNOWN:
+		/*
+		 * If the device failed diagnostic, it's likely to
 		 * have reported incorrect device signature too.
 		 * Assume ATA device if the device seems present but
 		 * device signature is invalid with diagnostic
 		 * failure.
 		 */
-		if (present && (dev->horkage & ATA_HORKAGE_DIAGNOSTIC))
+		if (present && (dev->quirks & ATA_QUIRK_DIAGNOSTIC))
 			class = ATA_DEV_ATA;
 		else
 			class = ATA_DEV_NONE;
-	} else if ((class == ATA_DEV_ATA) &&
-		   (ap->ops->sff_check_status(ap) == 0))
-		class = ATA_DEV_NONE;
-
+		break;
+	case ATA_DEV_ATA:
+		if (ap->ops->sff_check_status(ap) == 0)
+			class = ATA_DEV_NONE;
+		break;
+	}
 	return class;
 }
 EXPORT_SYMBOL_GPL(ata_sff_dev_classify);
@@ -1937,8 +1878,6 @@ static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask,
 {
 	struct ata_ioports *ioaddr = &ap->ioaddr;
 
-	DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
-
 	if (ap->ioaddr.ctl_addr) {
 		/* software reset.  causes dev0 to be selected */
 		iowrite8(ap->ctl, ioaddr->ctl_addr);
@@ -1976,8 +1915,6 @@ int ata_sff_softreset(struct ata_link *link, unsigned int *classes,
 	int rc;
 	u8 err;
 
-	DPRINTK("ENTER\n");
-
 	/* determine if device 0/1 are present */
 	if (ata_devchk(ap, 0))
 		devmask |= (1 << 0);
@@ -1988,7 +1925,6 @@ int ata_sff_softreset(struct ata_link *link, unsigned int *classes,
 	ap->ops->sff_dev_select(ap, 0);
 
 	/* issue bus reset */
-	DPRINTK("about to softreset, devmask=%x\n", devmask);
 	rc = ata_bus_softreset(ap, devmask, deadline);
 	/* if link is occupied, -ENODEV too is an error */
 	if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
@@ -2003,7 +1939,6 @@ int ata_sff_softreset(struct ata_link *link, unsigned int *classes,
 		classes[1] = ata_sff_dev_classify(&link->device[1],
 						  devmask & (1 << 1), &err);
 
-	DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
 	return 0;
 }
 EXPORT_SYMBOL_GPL(ata_sff_softreset);
@@ -2027,7 +1962,7 @@ int sata_sff_hardreset(struct ata_link *link, unsigned int *class,
 		       unsigned long deadline)
 {
 	struct ata_eh_context *ehc = &link->eh_context;
-	const unsigned long *timing = sata_ehc_deb_timing(ehc);
+	const unsigned int *timing = sata_ehc_deb_timing(ehc);
 	bool online;
 	int rc;
 
@@ -2036,7 +1971,6 @@ int sata_sff_hardreset(struct ata_link *link, unsigned int *class,
 	if (online)
 		*class = ata_sff_dev_classify(link->device, 1, NULL);
 
-	DPRINTK("EXIT, class=%u\n", *class);
 	return rc;
 }
 EXPORT_SYMBOL_GPL(sata_sff_hardreset);
@@ -2066,16 +2000,12 @@ void ata_sff_postreset(struct ata_link *link, unsigned int *classes)
 		ap->ops->sff_dev_select(ap, 0);
 
 	/* bail out if no device is present */
-	if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
-		DPRINTK("EXIT, no device\n");
+	if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE)
 		return;
-	}
 
 	/* set up device control */
-	if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr) {
-		ata_sff_set_devctl(ap, ap->ctl);
+	if (ata_sff_set_devctl(ap, ap->ctl))
 		ap->last_ctl = ap->ctl;
-	}
 }
 EXPORT_SYMBOL_GPL(ata_sff_postreset);
 
@@ -2104,7 +2034,6 @@ void ata_sff_drain_fifo(struct ata_queued_cmd *qc)
 						&& count < 65536; count += 2)
 		ioread16(ap->ioaddr.data_addr);
 
-	/* Can become DEBUG later */
 	if (count)
 		ata_port_dbg(ap, "drained %d bytes to clear DRQ\n", count);
 
@@ -2125,13 +2054,11 @@ EXPORT_SYMBOL_GPL(ata_sff_drain_fifo);
  */
 void ata_sff_error_handler(struct ata_port *ap)
 {
-	ata_reset_fn_t softreset = ap->ops->softreset;
-	ata_reset_fn_t hardreset = ap->ops->hardreset;
 	struct ata_queued_cmd *qc;
 	unsigned long flags;
 
 	qc = __ata_qc_from_tag(ap, ap->link.active_tag);
-	if (qc && !(qc->flags & ATA_QCFLAG_FAILED))
+	if (qc && !(qc->flags & ATA_QCFLAG_EH))
 		qc = NULL;
 
 	spin_lock_irqsave(ap->lock, flags);
@@ -2148,13 +2075,7 @@ void ata_sff_error_handler(struct ata_port *ap)
 
 	spin_unlock_irqrestore(ap->lock, flags);
 
-	/* ignore built-in hardresets if SCR access is not available */
-	if ((hardreset == sata_std_hardreset ||
-	     hardreset == sata_sff_hardreset) && !sata_scr_valid(&ap->link))
-		hardreset = NULL;
-
-	ata_do_eh(ap, ap->ops->prereset, softreset, hardreset,
-		  ap->ops->postreset);
+	ata_std_error_handler(ap);
 }
 EXPORT_SYMBOL_GPL(ata_sff_error_handler);
 
@@ -2186,18 +2107,18 @@ EXPORT_SYMBOL_GPL(ata_sff_std_ports);
 
 #ifdef CONFIG_PCI
 
-static int ata_resources_present(struct pci_dev *pdev, int port)
+static bool ata_resources_present(struct pci_dev *pdev, int port)
 {
 	int i;
 
 	/* Check the PCI resources for this channel are enabled */
-	port = port * 2;
+	port *= 2;
 	for (i = 0; i < 2; i++) {
 		if (pci_resource_start(pdev, port + i) == 0 ||
 		    pci_resource_len(pdev, port + i) == 0)
-			return 0;
+			return false;
 	}
-	return 1;
+	return true;
 }
 
 /**
@@ -2343,7 +2264,7 @@ EXPORT_SYMBOL_GPL(ata_pci_sff_prepare_host);
  */
 int ata_pci_sff_activate_host(struct ata_host *host,
 			      irq_handler_t irq_handler,
-			      struct scsi_host_template *sht)
+			      const struct scsi_host_template *sht)
 {
 	struct device *dev = host->dev;
 	struct pci_dev *pdev = to_pci_dev(dev);
@@ -2388,7 +2309,7 @@ int ata_pci_sff_activate_host(struct ata_host *host,
 		for (i = 0; i < 2; i++) {
 			if (ata_port_is_dummy(host->ports[i]))
 				continue;
-			ata_port_desc(host->ports[i], "irq %d", pdev->irq);
+			ata_port_desc_misc(host->ports[i], pdev->irq);
 		}
 	} else if (legacy_mode) {
 		if (!ata_port_is_dummy(host->ports[0])) {
@@ -2398,8 +2319,8 @@ int ata_pci_sff_activate_host(struct ata_host *host,
 			if (rc)
 				goto out;
 
-			ata_port_desc(host->ports[0], "irq %d",
-				      ATA_PRIMARY_IRQ(pdev));
+			ata_port_desc_misc(host->ports[0],
+					   ATA_PRIMARY_IRQ(pdev));
 		}
 
 		if (!ata_port_is_dummy(host->ports[1])) {
@@ -2409,8 +2330,8 @@ int ata_pci_sff_activate_host(struct ata_host *host,
 			if (rc)
 				goto out;
 
-			ata_port_desc(host->ports[1], "irq %d",
-				      ATA_SECONDARY_IRQ(pdev));
+			ata_port_desc_misc(host->ports[1],
+					   ATA_SECONDARY_IRQ(pdev));
 		}
 	}
 
@@ -2440,7 +2361,7 @@ static const struct ata_port_info *ata_sff_find_valid_pi(
 
 static int ata_pci_init_one(struct pci_dev *pdev,
 		const struct ata_port_info * const *ppi,
-		struct scsi_host_template *sht, void *host_priv,
+		const struct scsi_host_template *sht, void *host_priv,
 		int hflags, bool bmdma)
 {
 	struct device *dev = &pdev->dev;
@@ -2448,8 +2369,6 @@ static int ata_pci_init_one(struct pci_dev *pdev,
 	struct ata_host *host = NULL;
 	int rc;
 
-	DPRINTK("ENTER\n");
-
 	pi = ata_sff_find_valid_pi(ppi);
 	if (!pi) {
 		dev_err(&pdev->dev, "no valid port_info specified\n");
@@ -2516,7 +2435,7 @@ out:
  */
 int ata_pci_sff_init_one(struct pci_dev *pdev,
 		 const struct ata_port_info * const *ppi,
-		 struct scsi_host_template *sht, void *host_priv, int hflag)
+		 const struct scsi_host_template *sht, void *host_priv, int hflag)
 {
 	return ata_pci_init_one(pdev, ppi, sht, host_priv, hflag, 0);
 }
@@ -2595,7 +2514,6 @@ static void ata_bmdma_fill_sg(struct ata_queued_cmd *qc)
 
 			prd[pi].addr = cpu_to_le32(addr);
 			prd[pi].flags_len = cpu_to_le32(len & 0xffff);
-			VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
 
 			pi++;
 			sg_len -= len;
@@ -2655,7 +2573,6 @@ static void ata_bmdma_fill_sg_dumb(struct ata_queued_cmd *qc)
 				prd[++pi].addr = cpu_to_le32(addr + 0x8000);
 			}
 			prd[pi].flags_len = cpu_to_le32(blen);
-			VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
 
 			pi++;
 			sg_len -= len;
@@ -2737,8 +2654,11 @@ unsigned int ata_bmdma_qc_issue(struct ata_queued_cmd *qc)
 	case ATA_PROT_DMA:
 		WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
 
+		trace_ata_tf_load(ap, &qc->tf);
 		ap->ops->sff_tf_load(ap, &qc->tf);  /* load tf registers */
+		trace_ata_bmdma_setup(ap, &qc->tf, qc->tag);
 		ap->ops->bmdma_setup(qc);	    /* set up bmdma */
+		trace_ata_bmdma_start(ap, &qc->tf, qc->tag);
 		ap->ops->bmdma_start(qc);	    /* initiate bmdma */
 		ap->hsm_task_state = HSM_ST_LAST;
 		break;
@@ -2746,7 +2666,9 @@ unsigned int ata_bmdma_qc_issue(struct ata_queued_cmd *qc)
 	case ATAPI_PROT_DMA:
 		WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
 
+		trace_ata_tf_load(ap, &qc->tf);
 		ap->ops->sff_tf_load(ap, &qc->tf);  /* load tf registers */
+		trace_ata_bmdma_setup(ap, &qc->tf, qc->tag);
 		ap->ops->bmdma_setup(qc);	    /* set up bmdma */
 		ap->hsm_task_state = HSM_ST_FIRST;
 
@@ -2787,13 +2709,14 @@ unsigned int ata_bmdma_port_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
 	if (ap->hsm_task_state == HSM_ST_LAST && ata_is_dma(qc->tf.protocol)) {
 		/* check status of DMA engine */
 		host_stat = ap->ops->bmdma_status(ap);
-		VPRINTK("ata%u: host_stat 0x%X\n", ap->print_id, host_stat);
+		trace_ata_bmdma_status(ap, host_stat);
 
 		/* if it's not our irq... */
 		if (!(host_stat & ATA_DMA_INTR))
 			return ata_sff_idle_irq(ap);
 
 		/* before we do anything else, clear DMA-Start bit */
+		trace_ata_bmdma_stop(ap, &qc->tf, qc->tag);
 		ap->ops->bmdma_stop(qc);
 		bmdma_stopped = true;
 
@@ -2852,7 +2775,7 @@ void ata_bmdma_error_handler(struct ata_port *ap)
 	bool thaw = false;
 
 	qc = __ata_qc_from_tag(ap, ap->link.active_tag);
-	if (qc && !(qc->flags & ATA_QCFLAG_FAILED))
+	if (qc && !(qc->flags & ATA_QCFLAG_EH))
 		qc = NULL;
 
 	/* reset PIO HSM and stop DMA engine */
@@ -2862,6 +2785,7 @@ void ata_bmdma_error_handler(struct ata_port *ap)
 		u8 host_stat;
 
 		host_stat = ap->ops->bmdma_status(ap);
+		trace_ata_bmdma_status(ap, host_stat);
 
 		/* BMDMA controllers indicate host bus error by
 		 * setting DMA_ERR bit and timing out.  As it wasn't
@@ -2873,6 +2797,7 @@ void ata_bmdma_error_handler(struct ata_port *ap)
 			thaw = true;
 		}
 
+		trace_ata_bmdma_stop(ap, &qc->tf, qc->tag);
 		ap->ops->bmdma_stop(qc);
 
 		/* if we're gonna thaw, make sure IRQ is clear */
@@ -2906,6 +2831,7 @@ void ata_bmdma_post_internal_cmd(struct ata_queued_cmd *qc)
 
 	if (ata_is_dma(qc->tf.protocol)) {
 		spin_lock_irqsave(ap->lock, flags);
+		trace_ata_bmdma_stop(ap, &qc->tf, qc->tag);
 		ap->ops->bmdma_stop(qc);
 		spin_unlock_irqrestore(ap->lock, flags);
 	}
@@ -3099,6 +3025,7 @@ EXPORT_SYMBOL_GPL(ata_bmdma_port_start32);
  */
 int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev)
 {
+#ifdef CONFIG_HAS_IOPORT
 	unsigned long bmdma = pci_resource_start(pdev, 4);
 	u8 simplex;
 
@@ -3111,6 +3038,9 @@ int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev)
 	if (simplex & 0x80)
 		return -EOPNOTSUPP;
 	return 0;
+#else
+	return -ENOENT;
+#endif /* CONFIG_HAS_IOPORT */
 }
 EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex);
 
@@ -3232,7 +3162,7 @@ EXPORT_SYMBOL_GPL(ata_pci_bmdma_prepare_host);
  */
 int ata_pci_bmdma_init_one(struct pci_dev *pdev,
 			   const struct ata_port_info * const * ppi,
-			   struct scsi_host_template *sht, void *host_priv,
+			   const struct scsi_host_template *sht, void *host_priv,
 			   int hflags)
 {
 	return ata_pci_init_one(pdev, ppi, sht, host_priv, hflags, 1);
@@ -3261,7 +3191,8 @@ void ata_sff_port_init(struct ata_port *ap)
 
 int __init ata_sff_init(void)
 {
-	ata_sff_wq = alloc_workqueue("ata_sff", WQ_MEM_RECLAIM, WQ_MAX_ACTIVE);
+	ata_sff_wq = alloc_workqueue("ata_sff", WQ_MEM_RECLAIM | WQ_PERCPU,
+				     WQ_MAX_ACTIVE);
 	if (!ata_sff_wq)
 		return -ENOMEM;
 
diff --git a/drivers/ata/libata-trace.c b/drivers/ata/libata-trace.c
index 08e001303a82..9b5363fd0ab0 100644
--- a/drivers/ata/libata-trace.c
+++ b/drivers/ata/libata-trace.c
@@ -39,6 +39,24 @@ libata_trace_parse_status(struct trace_seq *p, unsigned char status)
 }
 
 const char *
+libata_trace_parse_host_stat(struct trace_seq *p, unsigned char host_stat)
+{
+	const char *ret = trace_seq_buffer_ptr(p);
+
+	trace_seq_printf(p, "{ ");
+	if (host_stat & ATA_DMA_INTR)
+		trace_seq_printf(p, "INTR ");
+	if (host_stat & ATA_DMA_ERR)
+		trace_seq_printf(p, "ERR ");
+	if (host_stat & ATA_DMA_ACTIVE)
+		trace_seq_printf(p, "ACTIVE ");
+	trace_seq_putc(p, '}');
+	trace_seq_putc(p, 0);
+
+	return ret;
+}
+
+const char *
 libata_trace_parse_eh_action(struct trace_seq *p, unsigned int eh_action)
 {
 	const char *ret = trace_seq_buffer_ptr(p);
@@ -124,7 +142,7 @@ libata_trace_parse_qc_flags(struct trace_seq *p, unsigned int qc_flags)
 			trace_seq_printf(p, "QUIET ");
 		if (qc_flags & ATA_QCFLAG_RETRY)
 			trace_seq_printf(p, "RETRY ");
-		if (qc_flags & ATA_QCFLAG_FAILED)
+		if (qc_flags & ATA_QCFLAG_EH)
 			trace_seq_printf(p, "FAILED ");
 		if (qc_flags & ATA_QCFLAG_SENSE_VALID)
 			trace_seq_printf(p, "SENSE_VALID ");
@@ -138,6 +156,35 @@ libata_trace_parse_qc_flags(struct trace_seq *p, unsigned int qc_flags)
 }
 
 const char *
+libata_trace_parse_tf_flags(struct trace_seq *p, unsigned int tf_flags)
+{
+	const char *ret = trace_seq_buffer_ptr(p);
+
+	trace_seq_printf(p, "%x", tf_flags);
+	if (tf_flags) {
+		trace_seq_printf(p, "{ ");
+		if (tf_flags & ATA_TFLAG_LBA48)
+			trace_seq_printf(p, "LBA48 ");
+		if (tf_flags & ATA_TFLAG_ISADDR)
+			trace_seq_printf(p, "ISADDR ");
+		if (tf_flags & ATA_TFLAG_DEVICE)
+			trace_seq_printf(p, "DEV ");
+		if (tf_flags & ATA_TFLAG_WRITE)
+			trace_seq_printf(p, "WRITE ");
+		if (tf_flags & ATA_TFLAG_LBA)
+			trace_seq_printf(p, "LBA ");
+		if (tf_flags & ATA_TFLAG_FUA)
+			trace_seq_printf(p, "FUA ");
+		if (tf_flags & ATA_TFLAG_POLLING)
+			trace_seq_printf(p, "POLL ");
+		trace_seq_putc(p, '}');
+	}
+	trace_seq_putc(p, 0);
+
+	return ret;
+}
+
+const char *
 libata_trace_parse_subcmd(struct trace_seq *p, unsigned char cmd,
 			  unsigned char feature, unsigned char hob_nsect)
 {
diff --git a/drivers/ata/libata-transport.c b/drivers/ata/libata-transport.c
index 6a40e3c6cf49..62415fe67a11 100644
--- a/drivers/ata/libata-transport.c
+++ b/drivers/ata/libata-transport.c
@@ -9,7 +9,7 @@
  * and various sysfs attributes to expose these topologies and management
  * interfaces to user-space.
  *
- * There are 3 objects defined in in this class:
+ * There are 3 objects defined in this class:
  * - ata_port
  * - ata_link
  * - ata_device
@@ -80,12 +80,6 @@ struct ata_internal {
 #define transport_class_to_port(dev)				\
 	tdev_to_port((dev)->parent)
 
-
-/* Device objects are always created whit link objects */
-static int ata_tdev_add(struct ata_device *dev);
-static void ata_tdev_delete(struct ata_device *dev);
-
-
 /*
  * Hack to allow attributes of the same name in different objects.
  */
@@ -163,7 +157,7 @@ static struct {
 	{ AC_ERR_INVALID,		"InvalidArg" },
 	{ AC_ERR_OTHER,			"Unknown" },
 	{ AC_ERR_NODEV_HINT,		"NoDeviceHint" },
-	{ AC_ERR_NCQ,		 	"NCQError" }
+	{ AC_ERR_NCQ,			"NCQError" }
 };
 ata_bitfield_name_match(err, ata_err_names)
 
@@ -196,7 +190,7 @@ static struct {
 	{ XFER_PIO_0,			"XFER_PIO_0" },
 	{ XFER_PIO_SLOW,		"XFER_PIO_SLOW" }
 };
-ata_bitfield_name_match(xfer,ata_xfer_names)
+ata_bitfield_name_search(xfer, ata_xfer_names)
 
 /*
  * ATA Port attributes
@@ -208,7 +202,7 @@ show_ata_port_##name(struct device *dev,				\
 {									\
 	struct ata_port *ap = transport_class_to_port(dev);		\
 									\
-	return scnprintf(buf, 20, format_string, cast ap->field);	\
+	return sysfs_emit(buf, format_string, cast ap->field);	        \
 }
 
 #define ata_port_simple_attr(field, name, format_string, type)		\
@@ -217,7 +211,8 @@ static DEVICE_ATTR(name, S_IRUGO, show_ata_port_##name, NULL)
 
 ata_port_simple_attr(nr_pmp_links, nr_pmp_links, "%d\n", int);
 ata_port_simple_attr(stats.idle_irq, idle_irq, "%ld\n", unsigned long);
-ata_port_simple_attr(local_port_no, port_no, "%u\n", unsigned int);
+/* We want the port_no sysfs attibute to start at 1 (ap->port_no starts at 0) */
+ata_port_simple_attr(port_no + 1, port_no, "%u\n", unsigned int);
 
 static DECLARE_TRANSPORT_CLASS(ata_port_class,
 			       "ata_port", NULL, NULL, NULL);
@@ -250,7 +245,7 @@ static int ata_tport_match(struct attribute_container *cont,
 
 /**
  * ata_tport_delete  --  remove ATA PORT
- * @port:	ATA PORT to remove
+ * @ap:	ATA PORT to remove
  *
  * Removes the specified ATA PORT.  Remove the associated link as well.
  */
@@ -265,6 +260,11 @@ void ata_tport_delete(struct ata_port *ap)
 	transport_destroy_device(dev);
 	put_device(dev);
 }
+EXPORT_SYMBOL_GPL(ata_tport_delete);
+
+static const struct device_type ata_port_sas_type = {
+	.name = ATA_PORT_TYPE_NAME,
+};
 
 /** ata_tport_add - initialize a transport ATA port structure
  *
@@ -283,7 +283,10 @@ int ata_tport_add(struct device *parent,
 	struct device *dev = &ap->tdev;
 
 	device_initialize(dev);
-	dev->type = &ata_port_type;
+	if (ap->flags & ATA_FLAG_SAS_HOST)
+		dev->type = &ata_port_sas_type;
+	else
+		dev->type = &ata_port_type;
 
 	dev->parent = parent;
 	ata_host_get(ap->host);
@@ -301,7 +304,9 @@ int ata_tport_add(struct device *parent,
 	pm_runtime_enable(dev);
 	pm_runtime_forbid(dev);
 
-	transport_add_device(dev);
+	error = transport_add_device(dev);
+	if (error)
+		goto tport_transport_add_err;
 	transport_configure_device(dev);
 
 	error = ata_tlink_add(&ap->link);
@@ -312,141 +317,46 @@ int ata_tport_add(struct device *parent,
 
  tport_link_err:
 	transport_remove_device(dev);
+ tport_transport_add_err:
 	device_del(dev);
 
  tport_err:
 	transport_destroy_device(dev);
 	put_device(dev);
-	ata_host_put(ap->host);
 	return error;
 }
-
-
-/*
- * ATA link attributes
- */
-static int noop(int x) { return x; }
-
-#define ata_link_show_linkspeed(field, format)			        \
-static ssize_t								\
-show_ata_link_##field(struct device *dev,				\
-		      struct device_attribute *attr, char *buf)		\
-{									\
-	struct ata_link *link = transport_class_to_link(dev);		\
-									\
-	return sprintf(buf, "%s\n", sata_spd_string(format(link->field))); \
-}
-
-#define ata_link_linkspeed_attr(field, format)				\
-	ata_link_show_linkspeed(field, format)				\
-static DEVICE_ATTR(field, S_IRUGO, show_ata_link_##field, NULL)
-
-ata_link_linkspeed_attr(hw_sata_spd_limit, fls);
-ata_link_linkspeed_attr(sata_spd_limit, fls);
-ata_link_linkspeed_attr(sata_spd, noop);
-
-
-static DECLARE_TRANSPORT_CLASS(ata_link_class,
-		"ata_link", NULL, NULL, NULL);
-
-static void ata_tlink_release(struct device *dev)
-{
-}
+EXPORT_SYMBOL_GPL(ata_tport_add);
 
 /**
- * ata_is_link --  check if a struct device represents a ATA link
- * @dev:	device to check
+ *     ata_port_classify - determine device type based on ATA-spec signature
+ *     @ap: ATA port device on which the classification should be run
+ *     @tf: ATA taskfile register set for device to be identified
  *
- * Returns:
- *	%1 if the device represents a ATA link, %0 else
- */
-static int ata_is_link(const struct device *dev)
-{
-	return dev->release == ata_tlink_release;
-}
-
-static int ata_tlink_match(struct attribute_container *cont,
-			   struct device *dev)
-{
-	struct ata_internal* i = to_ata_internal(ata_scsi_transport_template);
-	if (!ata_is_link(dev))
-		return 0;
-	return &i->link_attr_cont.ac == cont;
-}
-
-/**
- * ata_tlink_delete  --  remove ATA LINK
- * @port:	ATA LINK to remove
+ *     A wrapper around ata_dev_classify() to provide additional logging
  *
- * Removes the specified ATA LINK.  remove associated ATA device(s) as well.
+ *     RETURNS:
+ *     Device type, %ATA_DEV_ATA, %ATA_DEV_ATAPI, %ATA_DEV_PMP,
+ *     %ATA_DEV_ZAC, or %ATA_DEV_UNKNOWN the event of failure.
  */
-void ata_tlink_delete(struct ata_link *link)
+unsigned int ata_port_classify(struct ata_port *ap,
+			       const struct ata_taskfile *tf)
 {
-	struct device *dev = &link->tdev;
-	struct ata_device *ata_dev;
-
-	ata_for_each_dev(ata_dev, link, ALL) {
-		ata_tdev_delete(ata_dev);
-	}
-
-	transport_remove_device(dev);
-	device_del(dev);
-	transport_destroy_device(dev);
-	put_device(dev);
-}
-
-/**
- * ata_tlink_add  --  initialize a transport ATA link structure
- * @link:	allocated ata_link structure.
- *
- * Initialize an ATA LINK structure for sysfs.  It will be added in the
- * device tree below the ATA PORT it belongs to.
- *
- * Returns %0 on success
- */
-int ata_tlink_add(struct ata_link *link)
-{
-	struct device *dev = &link->tdev;
-	struct ata_port *ap = link->ap;
-	struct ata_device *ata_dev;
-	int error;
-
-	device_initialize(dev);
-	dev->parent = &ap->tdev;
-	dev->release = ata_tlink_release;
-	if (ata_is_host_link(link))
-		dev_set_name(dev, "link%d", ap->print_id);
-        else
-		dev_set_name(dev, "link%d.%d", ap->print_id, link->pmp);
-
-	transport_setup_device(dev);
-
-	error = device_add(dev);
-	if (error) {
-		goto tlink_err;
-	}
-
-	transport_add_device(dev);
-	transport_configure_device(dev);
-
-	ata_for_each_dev(ata_dev, link, ALL) {
-		error = ata_tdev_add(ata_dev);
-		if (error) {
-			goto tlink_dev_err;
+	int i;
+	unsigned int class = ata_dev_classify(tf);
+
+	/* Start with index '1' to skip the 'unknown' entry */
+	for (i = 1; i < ARRAY_SIZE(ata_class_names); i++) {
+		if (ata_class_names[i].value == class) {
+			ata_port_dbg(ap, "found %s device by sig\n",
+				     ata_class_names[i].name);
+			return class;
 		}
 	}
-	return 0;
-  tlink_dev_err:
-	while (--ata_dev >= link->device) {
-		ata_tdev_delete(ata_dev);
-	}
-	transport_remove_device(dev);
-	device_del(dev);
-  tlink_err:
-	transport_destroy_device(dev);
-	put_device(dev);
-	return error;
+
+	ata_port_info(ap, "found unknown device (class %u)\n", class);
+	return class;
 }
+EXPORT_SYMBOL_GPL(ata_port_classify);
 
 /*
  * ATA device attributes
@@ -472,19 +382,19 @@ ata_dev_attr(xfer, dma_mode);
 ata_dev_attr(xfer, xfer_mode);
 
 
-#define ata_dev_show_simple(field, format_string, cast)		\
+#define ata_dev_show_simple(field, format_string, cast)			\
 static ssize_t								\
 show_ata_dev_##field(struct device *dev,				\
 		     struct device_attribute *attr, char *buf)		\
 {									\
 	struct ata_device *ata_dev = transport_class_to_dev(dev);	\
 									\
-	return scnprintf(buf, 20, format_string, cast ata_dev->field);	\
+	return sysfs_emit(buf, format_string, cast ata_dev->field);	\
 }
 
-#define ata_dev_simple_attr(field, format_string, type)	\
+#define ata_dev_simple_attr(field, format_string, type)		\
 	ata_dev_show_simple(field, format_string, (type))	\
-static DEVICE_ATTR(field, S_IRUGO, 			\
+	static DEVICE_ATTR(field, S_IRUGO,			\
 		   show_ata_dev_##field, NULL)
 
 ata_dev_simple_attr(spdn_cnt, "%d\n", int);
@@ -502,7 +412,7 @@ static int ata_show_ering(struct ata_ering_entry *ent, void *void_arg)
 
 	seconds = div_u64_rem(ent->timestamp, HZ, &rem);
 	arg->written += sprintf(arg->buf + arg->written,
-			        "[%5llu.%09lu]", seconds,
+				"[%5llu.%09lu]", seconds,
 				rem * NSEC_PER_SEC / HZ);
 	arg->written += get_ata_err_names(ent->err_mask,
 					  arg->buf + arg->written);
@@ -572,10 +482,10 @@ show_ata_dev_trim(struct device *dev,
 
 	if (!ata_id_has_trim(ata_dev->id))
 		mode = "unsupported";
-	else if (ata_dev->horkage & ATA_HORKAGE_NOTRIM)
+	else if (ata_dev->quirks & ATA_QUIRK_NOTRIM)
 		mode = "forced_unsupported";
-	else if (ata_dev->horkage & ATA_HORKAGE_NO_NCQ_TRIM)
-			mode = "forced_unqueued";
+	else if (ata_dev->quirks & ATA_QUIRK_NO_NCQ_TRIM)
+		mode = "forced_unqueued";
 	else if (ata_fpdma_dsm_supported(ata_dev))
 		mode = "queued";
 	else
@@ -598,9 +508,9 @@ static void ata_tdev_release(struct device *dev)
  * @dev:	device to check
  *
  * Returns:
- *	%1 if the device represents a ATA device, %0 else
+ *	true if the device represents a ATA device, false otherwise
  */
-static int ata_is_ata_dev(const struct device *dev)
+static bool ata_is_ata_dev(const struct device *dev)
 {
 	return dev->release == ata_tdev_release;
 }
@@ -608,21 +518,22 @@ static int ata_is_ata_dev(const struct device *dev)
 static int ata_tdev_match(struct attribute_container *cont,
 			  struct device *dev)
 {
-	struct ata_internal* i = to_ata_internal(ata_scsi_transport_template);
+	struct ata_internal *i = to_ata_internal(ata_scsi_transport_template);
+
 	if (!ata_is_ata_dev(dev))
 		return 0;
 	return &i->dev_attr_cont.ac == cont;
 }
 
 /**
- * ata_tdev_free  --  free a ATA LINK
- * @dev:	ATA PHY to free
+ * ata_tdev_free  --  free an ATA transport device
+ * @dev:	struct ata_device owning the transport device to free
  *
- * Frees the specified ATA PHY.
+ * Free the ATA transport device for the specified ATA device.
  *
  * Note:
- *   This function must only be called on a PHY that has not
- *   successfully been added using ata_tdev_add().
+ *   This function must only be called for a ATA transport device that has not
+ *   yet successfully been added using ata_tdev_add().
  */
 static void ata_tdev_free(struct ata_device *dev)
 {
@@ -631,10 +542,10 @@ static void ata_tdev_free(struct ata_device *dev)
 }
 
 /**
- * ata_tdev_delete  --  remove ATA device
- * @port:	ATA PORT to remove
+ * ata_tdev_delete  --  remove an ATA transport device
+ * @ata_dev:	struct ata_device owning the transport device to delete
  *
- * Removes the specified ATA device.
+ * Removes the ATA transport device for the specified ATA device.
  */
 static void ata_tdev_delete(struct ata_device *ata_dev)
 {
@@ -645,15 +556,14 @@ static void ata_tdev_delete(struct ata_device *ata_dev)
 	ata_tdev_free(ata_dev);
 }
 
-
 /**
- * ata_tdev_add  --  initialize a transport ATA device structure.
- * @ata_dev:	ata_dev structure.
+ * ata_tdev_add  --  initialize an ATA transport device
+ * @ata_dev:	struct ata_device owning the transport device to add
  *
- * Initialize an ATA device structure for sysfs.  It will be added in the
- * device tree below the ATA LINK device it belongs to.
+ * Initialize an ATA transport device for sysfs.  It will be added in the
+ * device tree below the ATA link device it belongs to.
  *
- * Returns %0 on success
+ * Returns %0 on success and a negative error code on error.
  */
 static int ata_tdev_add(struct ata_device *ata_dev)
 {
@@ -667,7 +577,7 @@ static int ata_tdev_add(struct ata_device *ata_dev)
 	dev->release = ata_tdev_release;
 	if (ata_is_host_link(link))
 		dev_set_name(dev, "dev%d.%d", ap->print_id,ata_dev->devno);
-        else
+	else
 		dev_set_name(dev, "dev%d.%d.0", ap->print_id, link->pmp);
 
 	transport_setup_device(dev);
@@ -678,18 +588,154 @@ static int ata_tdev_add(struct ata_device *ata_dev)
 		return error;
 	}
 
-	transport_add_device(dev);
+	error = transport_add_device(dev);
+	if (error) {
+		device_del(dev);
+		ata_tdev_free(ata_dev);
+		return error;
+	}
+
 	transport_configure_device(dev);
 	return 0;
 }
 
+/*
+ * ATA link attributes
+ */
+static int noop(int x)
+{
+	return x;
+}
+
+#define ata_link_show_linkspeed(field, format)			\
+static ssize_t							\
+show_ata_link_##field(struct device *dev,			\
+		      struct device_attribute *attr, char *buf)	\
+{								\
+	struct ata_link *link = transport_class_to_link(dev);	\
+								\
+	return sprintf(buf, "%s\n",				\
+		       sata_spd_string(format(link->field)));	\
+}
+
+#define ata_link_linkspeed_attr(field, format)			\
+	ata_link_show_linkspeed(field, format)			\
+static DEVICE_ATTR(field, 0444, show_ata_link_##field, NULL)
+
+ata_link_linkspeed_attr(hw_sata_spd_limit, fls);
+ata_link_linkspeed_attr(sata_spd_limit, fls);
+ata_link_linkspeed_attr(sata_spd, noop);
+
+static DECLARE_TRANSPORT_CLASS(ata_link_class,
+		"ata_link", NULL, NULL, NULL);
+
+static void ata_tlink_release(struct device *dev)
+{
+}
+
+/**
+ * ata_is_link --  check if a struct device represents a ATA link
+ * @dev:	device to check
+ *
+ * Returns:
+ *	true if the device represents a ATA link, false otherwise
+ */
+static bool ata_is_link(const struct device *dev)
+{
+	return dev->release == ata_tlink_release;
+}
+
+static int ata_tlink_match(struct attribute_container *cont,
+			    struct device *dev)
+{
+	struct ata_internal *i = to_ata_internal(ata_scsi_transport_template);
+
+	if (!ata_is_link(dev))
+		return 0;
+	return &i->link_attr_cont.ac == cont;
+}
+
+/**
+ * ata_tlink_delete  --  remove an ATA link transport device
+ * @link:	struct ata_link owning the link transport device to remove
+ *
+ * Removes the link transport device of the specified ATA link. This also
+ * removes the ATA device(s) associated with the link as well.
+ */
+void ata_tlink_delete(struct ata_link *link)
+{
+	struct device *dev = &link->tdev;
+	struct ata_device *ata_dev;
+
+	ata_for_each_dev(ata_dev, link, ALL) {
+		ata_tdev_delete(ata_dev);
+	}
+
+	transport_remove_device(dev);
+	device_del(dev);
+	transport_destroy_device(dev);
+	put_device(dev);
+}
+
+/**
+ * ata_tlink_add  --  initialize an ATA link transport device
+ * @link:	struct ata_link owning the link transport device to initialize
+ *
+ * Initialize an ATA link transport device for sysfs. It will be added in the
+ * device tree below the ATA port it belongs to.
+ *
+ * Returns %0 on success and a negative error code on error.
+ */
+int ata_tlink_add(struct ata_link *link)
+{
+	struct device *dev = &link->tdev;
+	struct ata_port *ap = link->ap;
+	struct ata_device *ata_dev;
+	int error;
+
+	device_initialize(dev);
+	dev->parent = &ap->tdev;
+	dev->release = ata_tlink_release;
+	if (ata_is_host_link(link))
+		dev_set_name(dev, "link%d", ap->print_id);
+	else
+		dev_set_name(dev, "link%d.%d", ap->print_id, link->pmp);
+
+	transport_setup_device(dev);
+
+	error = device_add(dev);
+	if (error)
+		goto tlink_err;
+
+	error = transport_add_device(dev);
+	if (error)
+		goto tlink_transport_err;
+	transport_configure_device(dev);
+
+	ata_for_each_dev(ata_dev, link, ALL) {
+		error = ata_tdev_add(ata_dev);
+		if (error)
+			goto tlink_dev_err;
+	}
+	return 0;
+ tlink_dev_err:
+	while (--ata_dev >= link->device)
+		ata_tdev_delete(ata_dev);
+	transport_remove_device(dev);
+ tlink_transport_err:
+	device_del(dev);
+ tlink_err:
+	transport_destroy_device(dev);
+	put_device(dev);
+	return error;
+}
 
 /*
  * Setup / Teardown code
  */
 
 #define SETUP_TEMPLATE(attrb, field, perm, test)			\
-	i->private_##attrb[count] = dev_attr_##field;		       	\
+	i->private_##attrb[count] = dev_attr_##field;			\
 	i->private_##attrb[count].attr.mode = perm;			\
 	i->attrb[count] = &i->private_##attrb[count];			\
 	if (test)							\
diff --git a/drivers/ata/libata-transport.h b/drivers/ata/libata-transport.h
index 08a57fb9dc61..50cd2cbe8eea 100644
--- a/drivers/ata/libata-transport.h
+++ b/drivers/ata/libata-transport.h
@@ -8,9 +8,6 @@ extern struct scsi_transport_template *ata_scsi_transport_template;
 int ata_tlink_add(struct ata_link *link);
 void ata_tlink_delete(struct ata_link *link);
 
-int ata_tport_add(struct device *parent, struct ata_port *ap);
-void ata_tport_delete(struct ata_port *ap);
-
 struct scsi_transport_template *ata_attach_transport(void);
 void ata_release_transport(struct scsi_transport_template *t);
 
diff --git a/drivers/ata/libata-zpodd.c b/drivers/ata/libata-zpodd.c
index eefda51f97d3..799531218ea2 100644
--- a/drivers/ata/libata-zpodd.c
+++ b/drivers/ata/libata-zpodd.c
@@ -112,7 +112,7 @@ static bool zpready(struct ata_device *dev)
 	if (!ret || sense_key != NOT_READY)
 		return false;
 
-	sense_buf = dev->link->ap->sector_buf;
+	sense_buf = dev->sector_buf;
 	ret = atapi_eh_request_sense(dev, sense_buf, sense_key);
 	if (ret)
 		return false;
@@ -160,8 +160,7 @@ void zpodd_on_suspend(struct ata_device *dev)
 		return;
 	}
 
-	expires = zpodd->last_ready +
-		  msecs_to_jiffies(zpodd_poweroff_delay * 1000);
+	expires = zpodd->last_ready + secs_to_jiffies(zpodd_poweroff_delay);
 	if (time_before(jiffies, expires))
 		return;
 
diff --git a/drivers/ata/libata.h b/drivers/ata/libata.h
index 68cdd81d747c..0e7ecac73680 100644
--- a/drivers/ata/libata.h
+++ b/drivers/ata/libata.h
@@ -30,13 +30,32 @@ enum {
 	ATA_DNXFER_QUIET	= (1 << 31),
 };
 
-extern atomic_t ata_print_id;
+#define ATA_PORT_TYPE_NAME	"ata_port"
+
 extern int atapi_passthru16;
 extern int libata_fua;
 extern int libata_noacpi;
 extern int libata_allow_tpm;
 extern const struct device_type ata_port_type;
 extern struct ata_link *ata_dev_phys_link(struct ata_device *dev);
+
+static inline bool ata_sstatus_online(u32 sstatus)
+{
+	return (sstatus & 0xf) == 0x3;
+}
+
+static inline bool ata_dev_is_zac(struct ata_device *dev)
+{
+	/* Host managed device or host aware device */
+	return dev->class == ATA_DEV_ZAC ||
+		ata_id_zoned_cap(dev->id) == 0x01;
+}
+
+static inline bool ata_port_eh_scheduled(struct ata_port *ap)
+{
+	return ap->pflags & (ATA_PFLAG_EH_PENDING | ATA_PFLAG_EH_IN_PROGRESS);
+}
+
 #ifdef CONFIG_ATA_FORCE
 extern void ata_force_cbl(struct ata_port *ap);
 #else
@@ -44,20 +63,14 @@ static inline void ata_force_cbl(struct ata_port *ap) { }
 #endif
 extern u64 ata_tf_to_lba(const struct ata_taskfile *tf);
 extern u64 ata_tf_to_lba48(const struct ata_taskfile *tf);
-extern struct ata_queued_cmd *ata_qc_new_init(struct ata_device *dev, int tag);
-extern int ata_build_rw_tf(struct ata_taskfile *tf, struct ata_device *dev,
-			   u64 block, u32 n_block, unsigned int tf_flags,
-			   unsigned int tag, int class);
+extern int ata_build_rw_tf(struct ata_queued_cmd *qc, u64 block, u32 n_block,
+			   unsigned int tf_flags, int dld, int class);
 extern u64 ata_tf_read_block(const struct ata_taskfile *tf,
 			     struct ata_device *dev);
-extern unsigned ata_exec_internal(struct ata_device *dev,
-				  struct ata_taskfile *tf, const u8 *cdb,
-				  int dma_dir, void *buf, unsigned int buflen,
-				  unsigned long timeout);
-extern unsigned ata_exec_internal_sg(struct ata_device *dev,
-				     struct ata_taskfile *tf, const u8 *cdb,
-				     int dma_dir, struct scatterlist *sg,
-				     unsigned int n_elem, unsigned long timeout);
+unsigned int ata_exec_internal(struct ata_device *dev, struct ata_taskfile *tf,
+			       const u8 *cdb, enum dma_data_direction dma_dir,
+			       void *buf, unsigned int buflen,
+			       unsigned int timeout);
 extern int ata_wait_ready(struct ata_link *link, unsigned long deadline,
 			  int (*check_ready)(struct ata_link *link));
 extern int ata_dev_read_id(struct ata_device *dev, unsigned int *p_class,
@@ -66,10 +79,14 @@ extern int ata_dev_reread_id(struct ata_device *dev, unsigned int readid_flags);
 extern int ata_dev_revalidate(struct ata_device *dev, unsigned int new_class,
 			      unsigned int readid_flags);
 extern int ata_dev_configure(struct ata_device *dev);
-extern int sata_down_spd_limit(struct ata_link *link, u32 spd_limit);
+extern bool ata_dev_power_init_tf(struct ata_device *dev,
+				  struct ata_taskfile *tf, bool set_active);
+extern void ata_dev_power_set_standby(struct ata_device *dev);
+extern void ata_dev_power_set_active(struct ata_device *dev);
+void ata_dev_free_resources(struct ata_device *dev);
 extern int ata_down_xfermask_limit(struct ata_device *dev, unsigned int sel);
 extern unsigned int ata_dev_set_feature(struct ata_device *dev,
-					u8 enable, u8 feature);
+					u8 subcmd, u8 action);
 extern void ata_qc_free(struct ata_queued_cmd *qc);
 extern void ata_qc_issue(struct ata_queued_cmd *qc);
 extern void __ata_qc_complete(struct ata_queued_cmd *qc);
@@ -82,10 +99,7 @@ extern void ata_link_init(struct ata_port *ap, struct ata_link *link, int pmp);
 extern int sata_link_init_spd(struct ata_link *link);
 extern int ata_task_ioctl(struct scsi_device *scsidev, void __user *arg);
 extern int ata_cmd_ioctl(struct scsi_device *scsidev, void __user *arg);
-extern struct ata_port *ata_port_alloc(struct ata_host *host);
 extern const char *sata_spd_string(unsigned int spd);
-extern int ata_port_probe(struct ata_port *ap);
-extern void __ata_port_probe(struct ata_port *ap);
 extern unsigned int ata_read_log_page(struct ata_device *dev, u8 log,
 				      u8 page, void *buf, unsigned int sectors);
 
@@ -93,31 +107,34 @@ extern unsigned int ata_read_log_page(struct ata_device *dev, u8 log,
 
 /* libata-sata.c */
 #ifdef CONFIG_SATA_HOST
-int ata_sas_allocate_tag(struct ata_port *ap);
-void ata_sas_free_tag(unsigned int tag, struct ata_port *ap);
+int sata_down_spd_limit(struct ata_link *link, u32 spd_limit);
+int ata_eh_get_ncq_success_sense(struct ata_link *link);
 #else
-static inline int ata_sas_allocate_tag(struct ata_port *ap)
+static inline int sata_down_spd_limit(struct ata_link *link, u32 spd_limit)
+{
+	return -EOPNOTSUPP;
+}
+static inline int ata_eh_get_ncq_success_sense(struct ata_link *link)
 {
 	return -EOPNOTSUPP;
 }
-static inline void ata_sas_free_tag(unsigned int tag, struct ata_port *ap) { }
 #endif
 
 /* libata-acpi.c */
 #ifdef CONFIG_ATA_ACPI
 extern unsigned int ata_acpi_gtf_filter;
 extern void ata_acpi_dissociate(struct ata_host *host);
-extern int ata_acpi_on_suspend(struct ata_port *ap);
 extern void ata_acpi_on_resume(struct ata_port *ap);
 extern int ata_acpi_on_devcfg(struct ata_device *dev);
 extern void ata_acpi_on_disable(struct ata_device *dev);
 extern void ata_acpi_set_state(struct ata_port *ap, pm_message_t state);
 extern void ata_acpi_bind_port(struct ata_port *ap);
 extern void ata_acpi_bind_dev(struct ata_device *dev);
+extern void ata_acpi_port_power_on(struct ata_port *ap);
+extern bool ata_acpi_dev_manage_restart(struct ata_device *dev);
 extern acpi_handle ata_dev_acpi_handle(struct ata_device *dev);
 #else
 static inline void ata_acpi_dissociate(struct ata_host *host) { }
-static inline int ata_acpi_on_suspend(struct ata_port *ap) { return 0; }
 static inline void ata_acpi_on_resume(struct ata_port *ap) { }
 static inline int ata_acpi_on_devcfg(struct ata_device *dev) { return 0; }
 static inline void ata_acpi_on_disable(struct ata_device *dev) { }
@@ -125,34 +142,32 @@ static inline void ata_acpi_set_state(struct ata_port *ap,
 				      pm_message_t state) { }
 static inline void ata_acpi_bind_port(struct ata_port *ap) {}
 static inline void ata_acpi_bind_dev(struct ata_device *dev) {}
+static inline void ata_acpi_port_power_on(struct ata_port *ap) {}
+static inline bool ata_acpi_dev_manage_restart(struct ata_device *dev) { return 0; }
 #endif
 
 /* libata-scsi.c */
 extern struct ata_device *ata_scsi_find_dev(struct ata_port *ap,
 					    const struct scsi_device *scsidev);
 extern int ata_scsi_add_hosts(struct ata_host *host,
-			      struct scsi_host_template *sht);
+			      const struct scsi_host_template *sht);
 extern void ata_scsi_scan_host(struct ata_port *ap, int sync);
-extern int ata_scsi_offline_dev(struct ata_device *dev);
+extern bool ata_scsi_offline_dev(struct ata_device *dev);
+extern bool ata_scsi_sense_is_valid(u8 sk, u8 asc, u8 ascq);
 extern void ata_scsi_set_sense(struct ata_device *dev,
 			       struct scsi_cmnd *cmd, u8 sk, u8 asc, u8 ascq);
-extern void ata_scsi_set_sense_information(struct ata_device *dev,
-					   struct scsi_cmnd *cmd,
-					   const struct ata_taskfile *tf);
 extern void ata_scsi_media_change_notify(struct ata_device *dev);
 extern void ata_scsi_hotplug(struct work_struct *work);
-extern void ata_schedule_scsi_eh(struct Scsi_Host *shost);
 extern void ata_scsi_dev_rescan(struct work_struct *work);
-extern int ata_bus_probe(struct ata_port *ap);
 extern int ata_scsi_user_scan(struct Scsi_Host *shost, unsigned int channel,
 			      unsigned int id, u64 lun);
 void ata_scsi_sdev_config(struct scsi_device *sdev);
-int ata_scsi_dev_config(struct scsi_device *sdev, struct ata_device *dev);
-void ata_scsi_dump_cdb(struct ata_port *ap, struct scsi_cmnd *cmd);
+int ata_scsi_dev_config(struct scsi_device *sdev, struct queue_limits *lim,
+		struct ata_device *dev);
 int __ata_scsi_queuecmd(struct scsi_cmnd *scmd, struct ata_device *dev);
 
 /* libata-eh.c */
-extern unsigned long ata_internal_cmd_timeout(struct ata_device *dev, u8 cmd);
+extern unsigned int ata_internal_cmd_timeout(struct ata_device *dev, u8 cmd);
 extern void ata_internal_cmd_timed_out(struct ata_device *dev, u8 cmd);
 extern void ata_eh_acquire(struct ata_port *ap);
 extern void ata_eh_release(struct ata_port *ap);
@@ -166,20 +181,18 @@ extern void ata_eh_about_to_do(struct ata_link *link, struct ata_device *dev,
 extern void ata_eh_done(struct ata_link *link, struct ata_device *dev,
 			unsigned int action);
 extern void ata_eh_autopsy(struct ata_port *ap);
-const char *ata_get_cmd_descript(u8 command);
+const char *ata_get_cmd_name(u8 command);
 extern void ata_eh_report(struct ata_port *ap);
 extern int ata_eh_reset(struct ata_link *link, int classify,
-			ata_prereset_fn_t prereset, ata_reset_fn_t softreset,
-			ata_reset_fn_t hardreset, ata_postreset_fn_t postreset);
-extern int ata_set_mode(struct ata_link *link, struct ata_device **r_failed_dev);
-extern int ata_eh_recover(struct ata_port *ap, ata_prereset_fn_t prereset,
-			  ata_reset_fn_t softreset, ata_reset_fn_t hardreset,
-			  ata_postreset_fn_t postreset,
+			struct ata_reset_operations *reset_ops);
+extern int ata_eh_recover(struct ata_port *ap,
+			  struct ata_reset_operations *reset_ops,
 			  struct ata_link **r_failed_disk);
 extern void ata_eh_finish(struct ata_port *ap);
 extern int ata_ering_map(struct ata_ering *ering,
 			 int (*map_fn)(struct ata_ering_entry *, void *),
-		  	 void *arg);
+			 void *arg);
+enum scsi_disposition ata_eh_decide_disposition(struct ata_queued_cmd *qc);
 extern unsigned int atapi_eh_tur(struct ata_device *dev, u8 *r_sense_key);
 extern unsigned int atapi_eh_request_sense(struct ata_device *dev,
 					   u8 *sense_buf, u8 dfl_sense_key);
diff --git a/drivers/ata/pata_acpi.c b/drivers/ata/pata_acpi.c
index fa2bfc344a97..23fff10af2ac 100644
--- a/drivers/ata/pata_acpi.c
+++ b/drivers/ata/pata_acpi.c
@@ -28,7 +28,7 @@ struct pata_acpi {
 
 /**
  *	pacpi_pre_reset	-	check for 40/80 pin
- *	@ap: Port
+ *	@link: ATA link
  *	@deadline: deadline jiffies for the operation
  *
  *	Perform the PATA port setup we need.
@@ -63,8 +63,8 @@ static int pacpi_cable_detect(struct ata_port *ap)
 
 /**
  *	pacpi_discover_modes	-	filter non ACPI modes
+ *	@ap: ATA port
  *	@adev: ATA device
- *	@mask: proposed modes
  *
  *	Try the modes available and see which ones the ACPI method will
  *	set up sensibly. From this we get a mask of ACPI modes we can use
@@ -97,7 +97,7 @@ static unsigned long pacpi_discover_modes(struct ata_port *ap, struct ata_device
  *	this case the list of discovered valid modes obtained by ACPI probing
  */
 
-static unsigned long pacpi_mode_filter(struct ata_device *adev, unsigned long mask)
+static unsigned int pacpi_mode_filter(struct ata_device *adev, unsigned int mask)
 {
 	struct pata_acpi *acpi = adev->link->ap->private_data;
 	return mask & acpi->mask[adev->devno];
@@ -205,7 +205,7 @@ static int pacpi_port_start(struct ata_port *ap)
 	return ata_bmdma_port_start(ap);
 }
 
-static struct scsi_host_template pacpi_sht = {
+static const struct scsi_host_template pacpi_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
@@ -216,7 +216,7 @@ static struct ata_port_operations pacpi_ops = {
 	.mode_filter		= pacpi_mode_filter,
 	.set_piomode		= pacpi_set_piomode,
 	.set_dmamode		= pacpi_set_dmamode,
-	.prereset		= pacpi_pre_reset,
+	.reset.prereset		= pacpi_pre_reset,
 	.port_start		= pacpi_port_start,
 };
 
@@ -224,7 +224,7 @@ static struct ata_port_operations pacpi_ops = {
 /**
  *	pacpi_init_one - Register ACPI ATA PCI device with kernel services
  *	@pdev: PCI device to register
- *	@ent: Entry in pacpi_pci_tbl matching with @pdev
+ *	@id: PCI device ID
  *
  *	Called from kernel PCI layer.
  *
diff --git a/drivers/ata/pata_ali.c b/drivers/ata/pata_ali.c
index 0b122f903b8a..9d5cb9c34c52 100644
--- a/drivers/ata/pata_ali.c
+++ b/drivers/ata/pata_ali.c
@@ -37,7 +37,7 @@
 #define DRV_NAME "pata_ali"
 #define DRV_VERSION "0.7.8"
 
-static int ali_atapi_dma = 0;
+static int ali_atapi_dma;
 module_param_named(atapi_dma, ali_atapi_dma, int, 0644);
 MODULE_PARM_DESC(atapi_dma, "Enable ATAPI DMA (0=disable, 1=enable)");
 
@@ -108,14 +108,14 @@ static int ali_c2_cable_detect(struct ata_port *ap)
 
 /**
  *	ali_20_filter		-	filter for earlier ALI DMA
- *	@ap: ALi ATA port
- *	@adev: attached device
+ *	@adev: ATA device
+ *	@mask: received mask to manipulate and pass back
  *
  *	Ensure that we do not do DMA on CD devices. We may be able to
  *	fix that later on. Also ensure we do not do UDMA on WDC drives
  */
 
-static unsigned long ali_20_filter(struct ata_device *adev, unsigned long mask)
+static unsigned int ali_20_filter(struct ata_device *adev, unsigned int mask)
 {
 	char model_num[ATA_ID_PROD_LEN + 1];
 	/* No DMA on anything but a disk for now */
@@ -123,7 +123,7 @@ static unsigned long ali_20_filter(struct ata_device *adev, unsigned long mask)
 		mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
 	ata_id_c_string(adev->id, model_num, ATA_ID_PROD, sizeof(model_num));
 	if (strstr(model_num, "WDC"))
-		return mask &= ~ATA_MASK_UDMA;
+		mask &= ~ATA_MASK_UDMA;
 	return mask;
 }
 
@@ -215,7 +215,7 @@ static void ali_set_piomode(struct ata_port *ap, struct ata_device *adev)
 		struct ata_timing p;
 		ata_timing_compute(pair, pair->pio_mode, &p, T, 1);
 		ata_timing_merge(&p, &t, &t, ATA_TIMING_SETUP|ATA_TIMING_8BIT);
-		if (pair->dma_mode) {
+		if (ata_dma_enabled(pair)) {
 			ata_timing_compute(pair, pair->dma_mode, &p, T, 1);
 			ata_timing_merge(&p, &t, &t, ATA_TIMING_SETUP|ATA_TIMING_8BIT);
 		}
@@ -264,7 +264,7 @@ static void ali_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 			struct ata_timing p;
 			ata_timing_compute(pair, pair->pio_mode, &p, T, 1);
 			ata_timing_merge(&p, &t, &t, ATA_TIMING_SETUP|ATA_TIMING_8BIT);
-			if (pair->dma_mode) {
+			if (ata_dma_enabled(pair)) {
 				ata_timing_compute(pair, pair->dma_mode, &p, T, 1);
 				ata_timing_merge(&p, &t, &t, ATA_TIMING_SETUP|ATA_TIMING_8BIT);
 			}
@@ -313,7 +313,7 @@ static void ali_lock_sectors(struct ata_device *adev)
 
 /**
  *	ali_check_atapi_dma	-	DMA check for most ALi controllers
- *	@adev: Device
+ *	@qc: Command to complete
  *
  *	Called to decide whether commands should be sent by DMA or PIO
  */
@@ -355,7 +355,7 @@ static void ali_c2_c3_postreset(struct ata_link *link, unsigned int *classes)
 	ata_sff_postreset(link, classes);
 }
 
-static struct scsi_host_template ali_sht = {
+static const struct scsi_host_template ali_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
@@ -392,11 +392,11 @@ static struct ata_port_operations ali_20_port_ops = {
  *	Port operations for DMA capable ALi with cable detect
  */
 static struct ata_port_operations ali_c2_port_ops = {
-	.inherits	= &ali_dma_base_ops,
-	.check_atapi_dma = ali_check_atapi_dma,
-	.cable_detect	= ali_c2_cable_detect,
-	.dev_config	= ali_lock_sectors,
-	.postreset	= ali_c2_c3_postreset,
+	.inherits		= &ali_dma_base_ops,
+	.check_atapi_dma	= ali_check_atapi_dma,
+	.cable_detect		= ali_c2_cable_detect,
+	.dev_config		= ali_lock_sectors,
+	.reset.postreset	= ali_c2_c3_postreset,
 };
 
 /*
diff --git a/drivers/ata/pata_amd.c b/drivers/ata/pata_amd.c
index 987967f976cb..a2fecadc927d 100644
--- a/drivers/ata/pata_amd.c
+++ b/drivers/ata/pata_amd.c
@@ -66,7 +66,7 @@ static void timing_setup(struct ata_port *ap, struct ata_device *adev, int offse
 
 	if (peer) {
 		/* This may be over conservative */
-		if (peer->dma_mode) {
+		if (ata_dma_enabled(peer)) {
 			ata_timing_compute(peer, peer->dma_mode, &apeer, T, UT);
 			ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
 		}
@@ -167,7 +167,6 @@ static int amd_cable_detect(struct ata_port *ap)
 /**
  *	amd_fifo_setup		-	set the PIO FIFO for ATA/ATAPI
  *	@ap: ATA interface
- *	@adev: ATA device
  *
  *	Set the PCI fifo for this device according to the devices present
  *	on the bus at this point in time. We need to turn the post write buffer
@@ -265,8 +264,8 @@ static void amd133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
  * cached during driver attach and are consulted to select transfer
  * mode.
  */
-static unsigned long nv_mode_filter(struct ata_device *dev,
-				    unsigned long xfer_mask)
+static unsigned int nv_mode_filter(struct ata_device *dev,
+				   unsigned int xfer_mask)
 {
 	static const unsigned int udma_mask_map[] =
 		{ ATA_UDMA2, ATA_UDMA1, ATA_UDMA0, 0,
@@ -275,7 +274,7 @@ static unsigned long nv_mode_filter(struct ata_device *dev,
 	char acpi_str[32] = "";
 	u32 saved_udma, udma;
 	const struct ata_acpi_gtm *gtm;
-	unsigned long bios_limit = 0, acpi_limit = 0, limit;
+	unsigned int bios_limit = 0, acpi_limit = 0, limit;
 
 	/* find out what BIOS configured */
 	udma = saved_udma = (unsigned long)ap->host->private_data;
@@ -311,17 +310,18 @@ static unsigned long nv_mode_filter(struct ata_device *dev,
 	   cable detection result */
 	limit |= ata_pack_xfermask(ATA_PIO4, ATA_MWDMA2, ATA_UDMA2);
 
-	ata_port_dbg(ap, "nv_mode_filter: 0x%lx&0x%lx->0x%lx, "
-			"BIOS=0x%lx (0x%x) ACPI=0x%lx%s\n",
-			xfer_mask, limit, xfer_mask & limit, bios_limit,
-			saved_udma, acpi_limit, acpi_str);
+	ata_port_dbg(ap,
+		     "nv_mode_filter: 0x%x&0x%x->0x%x, BIOS=0x%x (0x%x) ACPI=0x%x%s\n",
+		     xfer_mask, limit, xfer_mask & limit, bios_limit,
+		     saved_udma, acpi_limit, acpi_str);
 
 	return xfer_mask & limit;
 }
 
 /**
- *	nv_probe_init	-	cable detection
- *	@lin: ATA link
+ *	nv_pre_reset	-	cable detection
+ *	@link: ATA link
+ *	@deadline: deadline jiffies for the operation
  *
  *	Perform cable detection. The BIOS stores this in PCI config
  *	space for us.
@@ -388,13 +388,13 @@ static void nv_host_stop(struct ata_host *host)
 	pci_write_config_dword(to_pci_dev(host->dev), 0x60, udma);
 }
 
-static struct scsi_host_template amd_sht = {
+static const struct scsi_host_template amd_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
 static const struct ata_port_operations amd_base_port_ops = {
 	.inherits	= &ata_bmdma32_port_ops,
-	.prereset	= amd_pre_reset,
+	.reset.prereset	= amd_pre_reset,
 };
 
 static struct ata_port_operations amd33_port_ops = {
@@ -429,7 +429,7 @@ static const struct ata_port_operations nv_base_port_ops = {
 	.inherits	= &ata_bmdma_port_ops,
 	.cable_detect	= ata_cable_ignore,
 	.mode_filter	= nv_mode_filter,
-	.prereset	= nv_pre_reset,
+	.reset.prereset	= nv_pre_reset,
 	.host_stop	= nv_host_stop,
 };
 
diff --git a/drivers/ata/pata_arasan_cf.c b/drivers/ata/pata_arasan_cf.c
index e9cf31f38450..514d549286b5 100644
--- a/drivers/ata/pata_arasan_cf.c
+++ b/drivers/ata/pata_arasan_cf.c
@@ -39,6 +39,7 @@
 #include <linux/spinlock.h>
 #include <linux/types.h>
 #include <linux/workqueue.h>
+#include <trace/events/libata.h>
 
 #define DRIVER_NAME	"arasan_cf"
 #define TIMEOUT		msecs_to_jiffies(3000)
@@ -217,7 +218,7 @@ struct arasan_cf_dev {
 	struct ata_queued_cmd *qc;
 };
 
-static struct scsi_host_template arasan_cf_sht = {
+static const struct scsi_host_template arasan_cf_sht = {
 	ATA_BASE_SHT(DRIVER_NAME),
 	.dma_boundary = 0xFFFFFFFFUL,
 };
@@ -528,7 +529,8 @@ static void data_xfer(struct work_struct *work)
 	/* dma_request_channel may sleep, so calling from process context */
 	acdev->dma_chan = dma_request_chan(acdev->host->dev, "data");
 	if (IS_ERR(acdev->dma_chan)) {
-		dev_err(acdev->host->dev, "Unable to get dma_chan\n");
+		dev_err_probe(acdev->host->dev, PTR_ERR(acdev->dma_chan),
+			      "Unable to get dma_chan\n");
 		acdev->dma_chan = NULL;
 		goto chan_request_fail;
 	}
@@ -703,9 +705,11 @@ static unsigned int arasan_cf_qc_issue(struct ata_queued_cmd *qc)
 	case ATA_PROT_DMA:
 		WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
 
+		trace_ata_tf_load(ap, &qc->tf);
 		ap->ops->sff_tf_load(ap, &qc->tf);
 		acdev->dma_status = 0;
 		acdev->qc = qc;
+		trace_ata_bmdma_start(ap, &qc->tf, qc->tag);
 		arasan_cf_dma_start(acdev);
 		ap->hsm_task_state = HSM_ST_LAST;
 		break;
@@ -818,12 +822,19 @@ static int arasan_cf_probe(struct platform_device *pdev)
 	else
 		quirk = CF_BROKEN_UDMA; /* as it is on spear1340 */
 
-	/* if irq is 0, support only PIO */
-	acdev->irq = platform_get_irq(pdev, 0);
-	if (acdev->irq)
+	/*
+	 * If there's an error getting IRQ (or we do get IRQ0),
+	 * support only PIO
+	 */
+	ret = platform_get_irq(pdev, 0);
+	if (ret > 0) {
+		acdev->irq = ret;
 		irq_handler = arasan_cf_interrupt;
-	else
+	} else	if (ret == -EPROBE_DEFER) {
+		return ret;
+	} else	{
 		quirk |= CF_BROKEN_MWDMA | CF_BROKEN_UDMA;
+	}
 
 	acdev->pbase = res->start;
 	acdev->vbase = devm_ioremap(&pdev->dev, res->start,
@@ -906,15 +917,13 @@ static int arasan_cf_probe(struct platform_device *pdev)
 	return ret;
 }
 
-static int arasan_cf_remove(struct platform_device *pdev)
+static void arasan_cf_remove(struct platform_device *pdev)
 {
 	struct ata_host *host = platform_get_drvdata(pdev);
 	struct arasan_cf_dev *acdev = host->ports[0]->private_data;
 
 	ata_host_detach(host);
 	cf_exit(acdev);
-
-	return 0;
 }
 
 #ifdef CONFIG_PM_SLEEP
@@ -927,7 +936,8 @@ static int arasan_cf_suspend(struct device *dev)
 		dmaengine_terminate_all(acdev->dma_chan);
 
 	cf_exit(acdev);
-	return ata_host_suspend(host, PMSG_SUSPEND);
+	ata_host_suspend(host, PMSG_SUSPEND);
+	return 0;
 }
 
 static int arasan_cf_resume(struct device *dev)
diff --git a/drivers/ata/pata_artop.c b/drivers/ata/pata_artop.c
index 6bd2228bb6ff..6160414172a3 100644
--- a/drivers/ata/pata_artop.c
+++ b/drivers/ata/pata_artop.c
@@ -28,7 +28,7 @@
 #include <linux/ata.h>
 
 #define DRV_NAME	"pata_artop"
-#define DRV_VERSION	"0.4.6"
+#define DRV_VERSION	"0.4.8"
 
 /*
  *	The ARTOP has 33 Mhz and "over clocked" timing tables. Until we
@@ -268,7 +268,7 @@ static void artop6260_set_dmamode (struct ata_port *ap, struct ata_device *adev)
 }
 
 /**
- *	artop_6210_qc_defer	-	implement serialization
+ *	artop6210_qc_defer	-	implement serialization
  *	@qc: command
  *
  *	Issue commands per host on this chip.
@@ -292,7 +292,7 @@ static int artop6210_qc_defer(struct ata_queued_cmd *qc)
 	return 0;
 }
 
-static struct scsi_host_template artop_sht = {
+static const struct scsi_host_template artop_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
@@ -301,7 +301,7 @@ static struct ata_port_operations artop6210_ops = {
 	.cable_detect		= ata_cable_40wire,
 	.set_piomode		= artop6210_set_piomode,
 	.set_dmamode		= artop6210_set_dmamode,
-	.prereset		= artop62x0_pre_reset,
+	.reset.prereset		= artop62x0_pre_reset,
 	.qc_defer		= artop6210_qc_defer,
 };
 
@@ -310,17 +310,20 @@ static struct ata_port_operations artop6260_ops = {
 	.cable_detect		= artop6260_cable_detect,
 	.set_piomode		= artop6260_set_piomode,
 	.set_dmamode		= artop6260_set_dmamode,
-	.prereset		= artop62x0_pre_reset,
+	.reset.prereset		= artop62x0_pre_reset,
 };
 
 static void atp8xx_fixup(struct pci_dev *pdev)
 {
-	if (pdev->device == 0x0005)
+	u8 reg;
+
+	switch (pdev->device) {
+	case 0x0005:
 		/* BIOS may have left us in UDMA, clear it before libata probe */
 		pci_write_config_byte(pdev, 0x54, 0);
-	else if (pdev->device == 0x0008 || pdev->device == 0x0009) {
-		u8 reg;
-
+		break;
+	case 0x0008:
+	case 0x0009:
 		/* Mac systems come up with some registers not set as we
 		   will need them */
 
@@ -338,13 +341,14 @@ static void atp8xx_fixup(struct pci_dev *pdev)
 		/* Enable IRQ output and burst mode */
 		pci_read_config_byte(pdev, 0x4a, &reg);
 		pci_write_config_byte(pdev, 0x4a, (reg & ~0x01) | 0x80);
+		break;
 	}
 }
 
 /**
  *	artop_init_one - Register ARTOP ATA PCI device with kernel services
  *	@pdev: PCI device to register
- *	@ent: Entry in artop_pci_tbl matching with @pdev
+ *	@id: PCI device ID
  *
  *	Called from kernel PCI layer.
  *
@@ -394,16 +398,19 @@ static int artop_init_one (struct pci_dev *pdev, const struct pci_device_id *id)
 	if (rc)
 		return rc;
 
-	if (id->driver_data == 0)	/* 6210 variant */
+	switch (id->driver_data) {
+	case 0:		/* 6210 variant */
 		ppi[0] = &info_6210;
-	else if (id->driver_data == 1)	/* 6260 */
+		break;
+	case 1:		/* 6260 */
 		ppi[0] = &info_626x;
-	else if (id->driver_data == 2)	{ /* 6280 or 6280 + fast */
-		unsigned long io = pci_resource_start(pdev, 4);
-
-		ppi[0] = &info_628x;
-		if (inb(io) & 0x10)
+		break;
+	case 2:		/* 6280 or 6280 + fast */
+		if (inb(pci_resource_start(pdev, 4)) & 0x10)
 			ppi[0] = &info_628x_fast;
+		else
+			ppi[0] = &info_628x;
+		break;
 	}
 
 	BUG_ON(ppi[0] == NULL);
diff --git a/drivers/ata/pata_atiixp.c b/drivers/ata/pata_atiixp.c
index c68aa3f585f2..4c612f9543f6 100644
--- a/drivers/ata/pata_atiixp.c
+++ b/drivers/ata/pata_atiixp.c
@@ -93,6 +93,7 @@ static int atiixp_prereset(struct ata_link *link, unsigned long deadline)
  *	atiixp_set_pio_timing	-	set initial PIO mode data
  *	@ap: ATA interface
  *	@adev: ATA device
+ *	@pio: Requested PIO
  *
  *	Called by both the pio and dma setup functions to set the controller
  *	timings for PIO transfers. We must load both the mode number and
@@ -101,7 +102,7 @@ static int atiixp_prereset(struct ata_link *link, unsigned long deadline)
 
 static void atiixp_set_pio_timing(struct ata_port *ap, struct ata_device *adev, int pio)
 {
-	static u8 pio_timings[5] = { 0x5D, 0x47, 0x34, 0x22, 0x20 };
+	static const u8 pio_timings[5] = { 0x5D, 0x47, 0x34, 0x22, 0x20 };
 
 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 	int dn = 2 * ap->port_no + adev->devno;
@@ -148,7 +149,7 @@ static void atiixp_set_piomode(struct ata_port *ap, struct ata_device *adev)
 
 static void atiixp_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 {
-	static u8 mwdma_timings[5] = { 0x77, 0x21, 0x20 };
+	static const u8 mwdma_timings[5] = { 0x77, 0x21, 0x20 };
 
 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 	int dma = adev->dma_mode;
@@ -227,7 +228,7 @@ static void atiixp_bmdma_start(struct ata_queued_cmd *qc)
 }
 
 /**
- *	atiixp_dma_stop	-	DMA stop callback
+ *	atiixp_bmdma_stop	-	DMA stop callback
  *	@qc: Command in progress
  *
  *	DMA has completed. Clear the UDMA flag as the next operations will
@@ -250,9 +251,10 @@ static void atiixp_bmdma_stop(struct ata_queued_cmd *qc)
 	ata_bmdma_stop(qc);
 }
 
-static struct scsi_host_template atiixp_sht = {
-	ATA_BMDMA_SHT(DRV_NAME),
+static const struct scsi_host_template atiixp_sht = {
+	ATA_BASE_SHT(DRV_NAME),
 	.sg_tablesize		= LIBATA_DUMB_MAX_PRD,
+	.dma_boundary		= ATA_DMA_BOUNDARY,
 };
 
 static struct ata_port_operations atiixp_port_ops = {
@@ -262,7 +264,7 @@ static struct ata_port_operations atiixp_port_ops = {
 	.bmdma_start 	= atiixp_bmdma_start,
 	.bmdma_stop	= atiixp_bmdma_stop,
 
-	.prereset	= atiixp_prereset,
+	.reset.prereset	= atiixp_prereset,
 	.cable_detect	= atiixp_cable_detect,
 	.set_piomode	= atiixp_set_piomode,
 	.set_dmamode	= atiixp_set_dmamode,
diff --git a/drivers/ata/pata_atp867x.c b/drivers/ata/pata_atp867x.c
index e01a3a6e4d46..308f86f9e2f0 100644
--- a/drivers/ata/pata_atp867x.c
+++ b/drivers/ata/pata_atp867x.c
@@ -155,9 +155,9 @@ static int atp867x_get_active_clocks_shifted(struct ata_port *ap,
 	case 1 ... 6:
 		break;
 	default:
-		printk(KERN_WARNING "ATP867X: active %dclk is invalid. "
+		ata_port_warn(ap, "ATP867X: active %dclk is invalid. "
 			"Using 12clk.\n", clk);
-		/* fall through */
+		fallthrough;
 	case 9 ... 12:
 		clocks = 7;	/* 12 clk */
 		break;
@@ -171,7 +171,8 @@ active_clock_shift_done:
 	return clocks << ATP867X_IO_PIOSPD_ACTIVE_SHIFT;
 }
 
-static int atp867x_get_recover_clocks_shifted(unsigned int clk)
+static int atp867x_get_recover_clocks_shifted(struct ata_port *ap,
+					      unsigned int clk)
 {
 	unsigned char clocks = clk;
 
@@ -188,9 +189,9 @@ static int atp867x_get_recover_clocks_shifted(unsigned int clk)
 	case 15:
 		break;
 	default:
-		printk(KERN_WARNING "ATP867X: recover %dclk is invalid. "
+		ata_port_warn(ap, "ATP867X: recover %dclk is invalid. "
 			"Using default 12clk.\n", clk);
-		/* fall through */
+		fallthrough;
 	case 12:	/* default 12 clk */
 		clocks = 0;
 		break;
@@ -225,7 +226,7 @@ static void atp867x_set_piomode(struct ata_port *ap, struct ata_device *adev)
 	iowrite8(b, dp->dma_mode);
 
 	b = atp867x_get_active_clocks_shifted(ap, t.active) |
-	    atp867x_get_recover_clocks_shifted(t.recover);
+		atp867x_get_recover_clocks_shifted(ap, t.recover);
 
 	if (adev->devno & 1)
 		iowrite8(b, dp->slave_piospd);
@@ -233,7 +234,7 @@ static void atp867x_set_piomode(struct ata_port *ap, struct ata_device *adev)
 		iowrite8(b, dp->mstr_piospd);
 
 	b = atp867x_get_active_clocks_shifted(ap, t.act8b) |
-	    atp867x_get_recover_clocks_shifted(t.rec8b);
+		atp867x_get_recover_clocks_shifted(ap, t.rec8b);
 
 	iowrite8(b, dp->eightb_piospd);
 }
@@ -258,7 +259,7 @@ static int atp867x_cable_detect(struct ata_port *ap)
 	return ATA_CBL_PATA_UNK;
 }
 
-static struct scsi_host_template atp867x_sht = {
+static const struct scsi_host_template atp867x_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
@@ -270,7 +271,6 @@ static struct ata_port_operations atp867x_ops = {
 };
 
 
-#ifdef	ATP867X_DEBUG
 static void atp867x_check_res(struct pci_dev *pdev)
 {
 	int i;
@@ -280,7 +280,7 @@ static void atp867x_check_res(struct pci_dev *pdev)
 	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
 		start = pci_resource_start(pdev, i);
 		len   = pci_resource_len(pdev, i);
-		printk(KERN_DEBUG "ATP867X: resource start:len=%lx:%lx\n",
+		dev_dbg(&pdev->dev, "ATP867X: resource start:len=%lx:%lx\n",
 			start, len);
 	}
 }
@@ -290,49 +290,48 @@ static void atp867x_check_ports(struct ata_port *ap, int port)
 	struct ata_ioports *ioaddr = &ap->ioaddr;
 	struct atp867x_priv *dp = ap->private_data;
 
-	printk(KERN_DEBUG "ATP867X: port[%d] addresses\n"
-		"  cmd_addr	=0x%llx, 0x%llx\n"
-		"  ctl_addr	=0x%llx, 0x%llx\n"
-		"  bmdma_addr	=0x%llx, 0x%llx\n"
-		"  data_addr	=0x%llx\n"
-		"  error_addr	=0x%llx\n"
-		"  feature_addr	=0x%llx\n"
-		"  nsect_addr	=0x%llx\n"
-		"  lbal_addr	=0x%llx\n"
-		"  lbam_addr	=0x%llx\n"
-		"  lbah_addr	=0x%llx\n"
-		"  device_addr	=0x%llx\n"
-		"  status_addr	=0x%llx\n"
-		"  command_addr	=0x%llx\n"
-		"  dp->dma_mode	=0x%llx\n"
-		"  dp->mstr_piospd	=0x%llx\n"
-		"  dp->slave_piospd	=0x%llx\n"
-		"  dp->eightb_piospd	=0x%llx\n"
+	ata_port_dbg(ap, "ATP867X: port[%d] addresses\n"
+		"  cmd_addr	=0x%lx, 0x%lx\n"
+		"  ctl_addr	=0x%lx, 0x%lx\n"
+		"  bmdma_addr	=0x%lx, 0x%lx\n"
+		"  data_addr	=0x%lx\n"
+		"  error_addr	=0x%lx\n"
+		"  feature_addr	=0x%lx\n"
+		"  nsect_addr	=0x%lx\n"
+		"  lbal_addr	=0x%lx\n"
+		"  lbam_addr	=0x%lx\n"
+		"  lbah_addr	=0x%lx\n"
+		"  device_addr	=0x%lx\n"
+		"  status_addr	=0x%lx\n"
+		"  command_addr	=0x%lx\n"
+		"  dp->dma_mode	=0x%lx\n"
+		"  dp->mstr_piospd	=0x%lx\n"
+		"  dp->slave_piospd	=0x%lx\n"
+		"  dp->eightb_piospd	=0x%lx\n"
 		"  dp->pci66mhz		=0x%lx\n",
 		port,
-		(unsigned long long)ioaddr->cmd_addr,
-		(unsigned long long)ATP867X_IO_PORTBASE(ap, port),
-		(unsigned long long)ioaddr->ctl_addr,
-		(unsigned long long)ATP867X_IO_ALTSTATUS(ap, port),
-		(unsigned long long)ioaddr->bmdma_addr,
-		(unsigned long long)ATP867X_IO_DMABASE(ap, port),
-		(unsigned long long)ioaddr->data_addr,
-		(unsigned long long)ioaddr->error_addr,
-		(unsigned long long)ioaddr->feature_addr,
-		(unsigned long long)ioaddr->nsect_addr,
-		(unsigned long long)ioaddr->lbal_addr,
-		(unsigned long long)ioaddr->lbam_addr,
-		(unsigned long long)ioaddr->lbah_addr,
-		(unsigned long long)ioaddr->device_addr,
-		(unsigned long long)ioaddr->status_addr,
-		(unsigned long long)ioaddr->command_addr,
-		(unsigned long long)dp->dma_mode,
-		(unsigned long long)dp->mstr_piospd,
-		(unsigned long long)dp->slave_piospd,
-		(unsigned long long)dp->eightb_piospd,
+		(unsigned long)ioaddr->cmd_addr,
+		(unsigned long)ATP867X_IO_PORTBASE(ap, port),
+		(unsigned long)ioaddr->ctl_addr,
+		(unsigned long)ATP867X_IO_ALTSTATUS(ap, port),
+		(unsigned long)ioaddr->bmdma_addr,
+		(unsigned long)ATP867X_IO_DMABASE(ap, port),
+		(unsigned long)ioaddr->data_addr,
+		(unsigned long)ioaddr->error_addr,
+		(unsigned long)ioaddr->feature_addr,
+		(unsigned long)ioaddr->nsect_addr,
+		(unsigned long)ioaddr->lbal_addr,
+		(unsigned long)ioaddr->lbam_addr,
+		(unsigned long)ioaddr->lbah_addr,
+		(unsigned long)ioaddr->device_addr,
+		(unsigned long)ioaddr->status_addr,
+		(unsigned long)ioaddr->command_addr,
+		(unsigned long)dp->dma_mode,
+		(unsigned long)dp->mstr_piospd,
+		(unsigned long)dp->slave_piospd,
+		(unsigned long)dp->eightb_piospd,
 		(unsigned long)dp->pci66mhz);
 }
-#endif
 
 static int atp867x_set_priv(struct ata_port *ap)
 {
@@ -370,8 +369,7 @@ static void atp867x_fixup(struct ata_host *host)
 	if (v < 0x80) {
 		v = 0x80;
 		pci_write_config_byte(pdev, PCI_LATENCY_TIMER, v);
-		printk(KERN_DEBUG "ATP867X: set latency timer of device %s"
-			" to %d\n", pci_name(pdev), v);
+		dev_dbg(&pdev->dev, "ATP867X: set latency timer to %d\n", v);
 	}
 
 	/*
@@ -419,13 +417,11 @@ static int atp867x_ata_pci_sff_init_host(struct ata_host *host)
 		return rc;
 	host->iomap = pcim_iomap_table(pdev);
 
-#ifdef	ATP867X_DEBUG
 	atp867x_check_res(pdev);
 
 	for (i = 0; i < PCI_STD_NUM_BARS; i++)
-		printk(KERN_DEBUG "ATP867X: iomap[%d]=0x%llx\n", i,
-			(unsigned long long)(host->iomap[i]));
-#endif
+		dev_dbg(gdev, "ATP867X: iomap[%d]=0x%p\n", i,
+			host->iomap[i]);
 
 	/*
 	 * request, iomap BARs and init port addresses accordingly
@@ -444,9 +440,8 @@ static int atp867x_ata_pci_sff_init_host(struct ata_host *host)
 		if (rc)
 			return rc;
 
-#ifdef	ATP867X_DEBUG
 		atp867x_check_ports(ap, i);
-#endif
+
 		ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx",
 			(unsigned long)ioaddr->cmd_addr,
 			(unsigned long)ioaddr->ctl_addr);
@@ -486,7 +481,7 @@ static int atp867x_init_one(struct pci_dev *pdev,
 	if (rc)
 		return rc;
 
-	printk(KERN_INFO "ATP867X: ATP867 ATA UDMA133 controller (rev %02X)",
+	dev_info(&pdev->dev, "ATP867X: ATP867 ATA UDMA133 controller (rev %02X)",
 		pdev->device);
 
 	host = ata_host_alloc_pinfo(&pdev->dev, ppi, ATP867X_NUM_PORTS);
@@ -530,7 +525,7 @@ static int atp867x_reinit_one(struct pci_dev *pdev)
 }
 #endif
 
-static struct pci_device_id atp867x_pci_tbl[] = {
+static const struct pci_device_id atp867x_pci_tbl[] = {
 	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP867A),	0 },
 	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP867B),	0 },
 	{ },
diff --git a/drivers/ata/pata_bk3710.c b/drivers/ata/pata_bk3710.c
deleted file mode 100644
index fad95cfecced..000000000000
--- a/drivers/ata/pata_bk3710.c
+++ /dev/null
@@ -1,380 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-
-/*
- * Palmchip BK3710 PATA controller driver
- *
- * Copyright (c) 2017 Samsung Electronics Co., Ltd.
- *		http://www.samsung.com
- *
- * Based on palm_bk3710.c:
- *
- * Copyright (C) 2006 Texas Instruments.
- * Copyright (C) 2007 MontaVista Software, Inc., <source@mvista.com>
- */
-
-#include <linux/ata.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/kernel.h>
-#include <linux/libata.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/types.h>
-
-#define DRV_NAME "pata_bk3710"
-
-#define BK3710_TF_OFFSET	0x1F0
-#define BK3710_CTL_OFFSET	0x3F6
-
-#define BK3710_BMISP		0x02
-#define BK3710_IDETIMP		0x40
-#define BK3710_UDMACTL		0x48
-#define BK3710_MISCCTL		0x50
-#define BK3710_REGSTB		0x54
-#define BK3710_REGRCVR		0x58
-#define BK3710_DATSTB		0x5C
-#define BK3710_DATRCVR		0x60
-#define BK3710_DMASTB		0x64
-#define BK3710_DMARCVR		0x68
-#define BK3710_UDMASTB		0x6C
-#define BK3710_UDMATRP		0x70
-#define BK3710_UDMAENV		0x74
-#define BK3710_IORDYTMP		0x78
-
-static struct scsi_host_template pata_bk3710_sht = {
-	ATA_BMDMA_SHT(DRV_NAME),
-};
-
-static unsigned int ideclk_period; /* in nanoseconds */
-
-struct pata_bk3710_udmatiming {
-	unsigned int rptime;	/* tRP -- Ready to pause time (nsec) */
-	unsigned int cycletime;	/* tCYCTYP2/2 -- avg Cycle Time (nsec) */
-				/* tENV is always a minimum of 20 nsec */
-};
-
-static const struct pata_bk3710_udmatiming pata_bk3710_udmatimings[6] = {
-	{ 160, 240 / 2 },	/* UDMA Mode 0 */
-	{ 125, 160 / 2 },	/* UDMA Mode 1 */
-	{ 100, 120 / 2 },	/* UDMA Mode 2 */
-	{ 100,  90 / 2 },	/* UDMA Mode 3 */
-	{ 100,  60 / 2 },	/* UDMA Mode 4 */
-	{  85,  40 / 2 },	/* UDMA Mode 5 */
-};
-
-static void pata_bk3710_setudmamode(void __iomem *base, unsigned int dev,
-				    unsigned int mode)
-{
-	u32 val32;
-	u16 val16;
-	u8 tenv, trp, t0;
-
-	/* DMA Data Setup */
-	t0 = DIV_ROUND_UP(pata_bk3710_udmatimings[mode].cycletime,
-			  ideclk_period) - 1;
-	tenv = DIV_ROUND_UP(20, ideclk_period) - 1;
-	trp = DIV_ROUND_UP(pata_bk3710_udmatimings[mode].rptime,
-			   ideclk_period) - 1;
-
-	/* udmastb Ultra DMA Access Strobe Width */
-	val32 = ioread32(base + BK3710_UDMASTB) & (0xFF << (dev ? 0 : 8));
-	val32 |= t0 << (dev ? 8 : 0);
-	iowrite32(val32, base + BK3710_UDMASTB);
-
-	/* udmatrp Ultra DMA Ready to Pause Time */
-	val32 = ioread32(base + BK3710_UDMATRP) & (0xFF << (dev ? 0 : 8));
-	val32 |= trp << (dev ? 8 : 0);
-	iowrite32(val32, base + BK3710_UDMATRP);
-
-	/* udmaenv Ultra DMA envelop Time */
-	val32 = ioread32(base + BK3710_UDMAENV) & (0xFF << (dev ? 0 : 8));
-	val32 |= tenv << (dev ? 8 : 0);
-	iowrite32(val32, base + BK3710_UDMAENV);
-
-	/* Enable UDMA for Device */
-	val16 = ioread16(base + BK3710_UDMACTL) | (1 << dev);
-	iowrite16(val16, base + BK3710_UDMACTL);
-}
-
-static void pata_bk3710_setmwdmamode(void __iomem *base, unsigned int dev,
-				     unsigned short min_cycle,
-				     unsigned int mode)
-{
-	const struct ata_timing *t;
-	int cycletime;
-	u32 val32;
-	u16 val16;
-	u8 td, tkw, t0;
-
-	t = ata_timing_find_mode(mode);
-	cycletime = max_t(int, t->cycle, min_cycle);
-
-	/* DMA Data Setup */
-	t0 = DIV_ROUND_UP(cycletime, ideclk_period);
-	td = DIV_ROUND_UP(t->active, ideclk_period);
-	tkw = t0 - td - 1;
-	td--;
-
-	val32 = ioread32(base + BK3710_DMASTB) & (0xFF << (dev ? 0 : 8));
-	val32 |= td << (dev ? 8 : 0);
-	iowrite32(val32, base + BK3710_DMASTB);
-
-	val32 = ioread32(base + BK3710_DMARCVR) & (0xFF << (dev ? 0 : 8));
-	val32 |= tkw << (dev ? 8 : 0);
-	iowrite32(val32, base + BK3710_DMARCVR);
-
-	/* Disable UDMA for Device */
-	val16 = ioread16(base + BK3710_UDMACTL) & ~(1 << dev);
-	iowrite16(val16, base + BK3710_UDMACTL);
-}
-
-static void pata_bk3710_set_dmamode(struct ata_port *ap,
-				    struct ata_device *adev)
-{
-	void __iomem *base = (void __iomem *)ap->ioaddr.bmdma_addr;
-	int is_slave = adev->devno;
-	const u8 xferspeed = adev->dma_mode;
-
-	if (xferspeed >= XFER_UDMA_0)
-		pata_bk3710_setudmamode(base, is_slave,
-					xferspeed - XFER_UDMA_0);
-	else
-		pata_bk3710_setmwdmamode(base, is_slave,
-					 adev->id[ATA_ID_EIDE_DMA_MIN],
-					 xferspeed);
-}
-
-static void pata_bk3710_setpiomode(void __iomem *base, struct ata_device *pair,
-				   unsigned int dev, unsigned int cycletime,
-				   unsigned int mode)
-{
-	const struct ata_timing *t;
-	u32 val32;
-	u8 t2, t2i, t0;
-
-	t = ata_timing_find_mode(XFER_PIO_0 + mode);
-
-	/* PIO Data Setup */
-	t0 = DIV_ROUND_UP(cycletime, ideclk_period);
-	t2 = DIV_ROUND_UP(t->active, ideclk_period);
-
-	t2i = t0 - t2 - 1;
-	t2--;
-
-	val32 = ioread32(base + BK3710_DATSTB) & (0xFF << (dev ? 0 : 8));
-	val32 |= t2 << (dev ? 8 : 0);
-	iowrite32(val32, base + BK3710_DATSTB);
-
-	val32 = ioread32(base + BK3710_DATRCVR) & (0xFF << (dev ? 0 : 8));
-	val32 |= t2i << (dev ? 8 : 0);
-	iowrite32(val32, base + BK3710_DATRCVR);
-
-	/* FIXME: this is broken also in the old driver */
-	if (pair) {
-		u8 mode2 = pair->pio_mode - XFER_PIO_0;
-
-		if (mode2 < mode)
-			mode = mode2;
-	}
-
-	/* TASKFILE Setup */
-	t0 = DIV_ROUND_UP(t->cyc8b, ideclk_period);
-	t2 = DIV_ROUND_UP(t->act8b, ideclk_period);
-
-	t2i = t0 - t2 - 1;
-	t2--;
-
-	val32 = ioread32(base + BK3710_REGSTB) & (0xFF << (dev ? 0 : 8));
-	val32 |= t2 << (dev ? 8 : 0);
-	iowrite32(val32, base + BK3710_REGSTB);
-
-	val32 = ioread32(base + BK3710_REGRCVR) & (0xFF << (dev ? 0 : 8));
-	val32 |= t2i << (dev ? 8 : 0);
-	iowrite32(val32, base + BK3710_REGRCVR);
-}
-
-static void pata_bk3710_set_piomode(struct ata_port *ap,
-				    struct ata_device *adev)
-{
-	void __iomem *base = (void __iomem *)ap->ioaddr.bmdma_addr;
-	struct ata_device *pair = ata_dev_pair(adev);
-	const struct ata_timing *t = ata_timing_find_mode(adev->pio_mode);
-	const u16 *id = adev->id;
-	unsigned int cycle_time = 0;
-	int is_slave = adev->devno;
-	const u8 pio = adev->pio_mode - XFER_PIO_0;
-
-	if (id[ATA_ID_FIELD_VALID] & 2) {
-		if (ata_id_has_iordy(id))
-			cycle_time = id[ATA_ID_EIDE_PIO_IORDY];
-		else
-			cycle_time = id[ATA_ID_EIDE_PIO];
-
-		/* conservative "downgrade" for all pre-ATA2 drives */
-		if (pio < 3 && cycle_time < t->cycle)
-			cycle_time = 0; /* use standard timing */
-	}
-
-	if (!cycle_time)
-		cycle_time = t->cycle;
-
-	pata_bk3710_setpiomode(base, pair, is_slave, cycle_time, pio);
-}
-
-static void pata_bk3710_chipinit(void __iomem *base)
-{
-	/*
-	 * REVISIT:  the ATA reset signal needs to be managed through a
-	 * GPIO, which means it should come from platform_data.  Until
-	 * we get and use such information, we have to trust that things
-	 * have been reset before we get here.
-	 */
-
-	/*
-	 * Program the IDETIMP Register Value based on the following assumptions
-	 *
-	 * (ATA_IDETIMP_IDEEN		, ENABLE ) |
-	 * (ATA_IDETIMP_PREPOST1	, DISABLE) |
-	 * (ATA_IDETIMP_PREPOST0	, DISABLE) |
-	 *
-	 * DM6446 silicon rev 2.1 and earlier have no observed net benefit
-	 * from enabling prefetch/postwrite.
-	 */
-	iowrite16(BIT(15), base + BK3710_IDETIMP);
-
-	/*
-	 * UDMACTL Ultra-ATA DMA Control
-	 * (ATA_UDMACTL_UDMAP1	, 0 ) |
-	 * (ATA_UDMACTL_UDMAP0	, 0 )
-	 *
-	 */
-	iowrite16(0, base + BK3710_UDMACTL);
-
-	/*
-	 * MISCCTL Miscellaneous Conrol Register
-	 * (ATA_MISCCTL_HWNHLD1P	, 1 cycle)
-	 * (ATA_MISCCTL_HWNHLD0P	, 1 cycle)
-	 * (ATA_MISCCTL_TIMORIDE	, 1)
-	 */
-	iowrite32(0x001, base + BK3710_MISCCTL);
-
-	/*
-	 * IORDYTMP IORDY Timer for Primary Register
-	 * (ATA_IORDYTMP_IORDYTMP	, DISABLE)
-	 */
-	iowrite32(0, base + BK3710_IORDYTMP);
-
-	/*
-	 * Configure BMISP Register
-	 * (ATA_BMISP_DMAEN1	, DISABLE )	|
-	 * (ATA_BMISP_DMAEN0	, DISABLE )	|
-	 * (ATA_BMISP_IORDYINT	, CLEAR)	|
-	 * (ATA_BMISP_INTRSTAT	, CLEAR)	|
-	 * (ATA_BMISP_DMAERROR	, CLEAR)
-	 */
-	iowrite16(0xE, base + BK3710_BMISP);
-
-	pata_bk3710_setpiomode(base, NULL, 0, 600, 0);
-	pata_bk3710_setpiomode(base, NULL, 1, 600, 0);
-}
-
-static struct ata_port_operations pata_bk3710_ports_ops = {
-	.inherits		= &ata_bmdma_port_ops,
-	.cable_detect		= ata_cable_80wire,
-
-	.set_piomode		= pata_bk3710_set_piomode,
-	.set_dmamode		= pata_bk3710_set_dmamode,
-};
-
-static int __init pata_bk3710_probe(struct platform_device *pdev)
-{
-	struct clk *clk;
-	struct resource *mem;
-	struct ata_host *host;
-	struct ata_port *ap;
-	void __iomem *base;
-	unsigned long rate;
-	int irq;
-
-	clk = devm_clk_get(&pdev->dev, NULL);
-	if (IS_ERR(clk))
-		return -ENODEV;
-
-	clk_enable(clk);
-	rate = clk_get_rate(clk);
-	if (!rate)
-		return -EINVAL;
-
-	/* NOTE:  round *down* to meet minimum timings; we count in clocks */
-	ideclk_period = 1000000000UL / rate;
-
-	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-
-	irq = platform_get_irq(pdev, 0);
-	if (irq < 0) {
-		pr_err(DRV_NAME ": failed to get IRQ resource\n");
-		return irq;
-	}
-
-	base = devm_ioremap_resource(&pdev->dev, mem);
-	if (IS_ERR(base))
-		return PTR_ERR(base);
-
-	/* configure the Palmchip controller */
-	pata_bk3710_chipinit(base);
-
-	/* allocate host */
-	host = ata_host_alloc(&pdev->dev, 1);
-	if (!host)
-		return -ENOMEM;
-	ap = host->ports[0];
-
-	ap->ops = &pata_bk3710_ports_ops;
-	ap->pio_mask = ATA_PIO4;
-	ap->mwdma_mask = ATA_MWDMA2;
-	ap->udma_mask = rate < 100000000 ? ATA_UDMA4 : ATA_UDMA5;
-	ap->flags |= ATA_FLAG_SLAVE_POSS;
-
-	ap->ioaddr.data_addr		= base + BK3710_TF_OFFSET;
-	ap->ioaddr.error_addr		= base + BK3710_TF_OFFSET + 1;
-	ap->ioaddr.feature_addr		= base + BK3710_TF_OFFSET + 1;
-	ap->ioaddr.nsect_addr		= base + BK3710_TF_OFFSET + 2;
-	ap->ioaddr.lbal_addr		= base + BK3710_TF_OFFSET + 3;
-	ap->ioaddr.lbam_addr		= base + BK3710_TF_OFFSET + 4;
-	ap->ioaddr.lbah_addr		= base + BK3710_TF_OFFSET + 5;
-	ap->ioaddr.device_addr		= base + BK3710_TF_OFFSET + 6;
-	ap->ioaddr.status_addr		= base + BK3710_TF_OFFSET + 7;
-	ap->ioaddr.command_addr		= base + BK3710_TF_OFFSET + 7;
-
-	ap->ioaddr.altstatus_addr	= base + BK3710_CTL_OFFSET;
-	ap->ioaddr.ctl_addr		= base + BK3710_CTL_OFFSET;
-
-	ap->ioaddr.bmdma_addr		= base;
-
-	ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx",
-		      (unsigned long)base + BK3710_TF_OFFSET,
-		      (unsigned long)base + BK3710_CTL_OFFSET);
-
-	/* activate */
-	return ata_host_activate(host, irq, ata_sff_interrupt, 0,
-				 &pata_bk3710_sht);
-}
-
-/* work with hotplug and coldplug */
-MODULE_ALIAS("platform:palm_bk3710");
-
-static struct platform_driver pata_bk3710_driver = {
-	.driver = {
-		.name = "palm_bk3710",
-	},
-};
-
-static int __init pata_bk3710_init(void)
-{
-	return platform_driver_probe(&pata_bk3710_driver, pata_bk3710_probe);
-}
-
-module_init(pata_bk3710_init);
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/ata/pata_buddha.c b/drivers/ata/pata_buddha.c
index 27d4c417fc60..c36ee991d5e5 100644
--- a/drivers/ata/pata_buddha.c
+++ b/drivers/ata/pata_buddha.c
@@ -27,7 +27,6 @@
 
 #include <asm/amigahw.h>
 #include <asm/amigaints.h>
-#include <asm/ide.h>
 #include <asm/setup.h>
 
 #define DRV_NAME "pata_buddha"
@@ -57,7 +56,7 @@ static unsigned int xsurf_bases[2] = {
 	XSURF_BASE1, XSURF_BASE2
 };
 
-static struct scsi_host_template pata_buddha_sht = {
+static const struct scsi_host_template pata_buddha_sht = {
 	ATA_PIO_SHT(DRV_NAME),
 };
 
diff --git a/drivers/ata/pata_cmd640.c b/drivers/ata/pata_cmd640.c
index d0bcabb58b44..45a7217b136e 100644
--- a/drivers/ata/pata_cmd640.c
+++ b/drivers/ata/pata_cmd640.c
@@ -61,7 +61,7 @@ static void cmd640_set_piomode(struct ata_port *ap, struct ata_device *adev)
 	struct ata_device *pair = ata_dev_pair(adev);
 
 	if (ata_timing_compute(adev, adev->pio_mode, &t, T, 0) < 0) {
-		printk(KERN_ERR DRV_NAME ": mode computation failed.\n");
+		ata_dev_err(adev, DRV_NAME ": mode computation failed.\n");
 		return;
 	}
 
@@ -172,7 +172,7 @@ static bool cmd640_sff_irq_check(struct ata_port *ap)
 	return irq_stat & irq_mask;
 }
 
-static struct scsi_host_template cmd640_sht = {
+static const struct scsi_host_template cmd640_sht = {
 	ATA_PIO_SHT(DRV_NAME),
 };
 
diff --git a/drivers/ata/pata_cmd64x.c b/drivers/ata/pata_cmd64x.c
index 3134eaec9e3d..fafea2b79145 100644
--- a/drivers/ata/pata_cmd64x.c
+++ b/drivers/ata/pata_cmd64x.c
@@ -116,7 +116,7 @@ static void cmd64x_set_timing(struct ata_port *ap, struct ata_device *adev, u8 m
 	/* ata_timing_compute is smart and will produce timings for MWDMA
 	   that don't violate the drives PIO capabilities. */
 	if (ata_timing_compute(adev, mode, &t, T, 0) < 0) {
-		printk(KERN_ERR DRV_NAME ": mode computation failed.\n");
+		ata_dev_err(adev, DRV_NAME ": mode computation failed.\n");
 		return;
 	}
 	if (ap->port_no) {
@@ -130,7 +130,7 @@ static void cmd64x_set_timing(struct ata_port *ap, struct ata_device *adev, u8 m
 		}
 	}
 
-	printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n",
+	ata_dev_dbg(adev, DRV_NAME ": active %d recovery %d setup %d.\n",
 		t.active, t.recover, t.setup);
 	if (t.recover > 16) {
 		t.active += t.recover - 16;
@@ -319,7 +319,7 @@ static void cmd646r1_bmdma_stop(struct ata_queued_cmd *qc)
 	ata_bmdma_stop(qc);
 }
 
-static struct scsi_host_template cmd64x_sht = {
+static const struct scsi_host_template cmd64x_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
@@ -461,7 +461,7 @@ static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
 		case 1:
 			ppi[0] = &cmd_info[4];
 			ppi[1] = &cmd_info[4];
-			/* FALL THRU */
+			fallthrough;
 		/* Early revs have no CNTRL_CH0 */
 		case 2:
 		case 0:
diff --git a/drivers/ata/pata_cs5520.c b/drivers/ata/pata_cs5520.c
index 9052148b306d..3163c8d9cef5 100644
--- a/drivers/ata/pata_cs5520.c
+++ b/drivers/ata/pata_cs5520.c
@@ -8,9 +8,9 @@
  *	PIO mode and smarter silicon.
  *
  *	The practical upshot of this is that we must always tune the
- *	drive for the right PIO mode. We must also ignore all the blacklists
- *	and the drive bus mastering DMA information. Also to confuse matters
- *	further we can do DMA on PIO only drives.
+ *	drive for the right PIO mode and ignore the drive bus mastering DMA
+ *	information. Also to confuse matters further we can do DMA on PIO only
+ *	drives.
  *
  *	DMA on the 5510 also requires we disable_hlt() during DMA on early
  *	revisions.
@@ -52,6 +52,7 @@ static const struct pio_clocks cs5520_pio_clocks[]={
  *	cs5520_set_timings	-	program PIO timings
  *	@ap: ATA port
  *	@adev: ATA device
+ *	@pio: PIO ID
  *
  *	Program the PIO mode timings for the controller according to the pio
  *	clocking table.
@@ -93,9 +94,10 @@ static void cs5520_set_piomode(struct ata_port *ap, struct ata_device *adev)
 	cs5520_set_timings(ap, adev, adev->pio_mode);
 }
 
-static struct scsi_host_template cs5520_sht = {
-	ATA_BMDMA_SHT(DRV_NAME),
+static const struct scsi_host_template cs5520_sht = {
+	ATA_BASE_SHT(DRV_NAME),
 	.sg_tablesize		= LIBATA_DUMB_MAX_PRD,
+	.dma_boundary		= ATA_DMA_BOUNDARY,
 };
 
 static struct ata_port_operations cs5520_port_ops = {
@@ -149,14 +151,8 @@ static int cs5520_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
 	if (!host)
 		return -ENOMEM;
 
-	/* Perform set up for DMA */
-	if (pci_enable_device_io(pdev)) {
-		printk(KERN_ERR DRV_NAME ": unable to configure BAR2.\n");
-		return -ENODEV;
-	}
-
 	if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32))) {
-		printk(KERN_ERR DRV_NAME ": unable to configure DMA mask.\n");
+		dev_err(&pdev->dev, "unable to configure DMA mask.\n");
 		return -ENODEV;
 	}
 
@@ -210,7 +206,7 @@ static int cs5520_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
 		if (rc)
 			return rc;
 
-		ata_port_desc(ap, "irq %d", irq[i]);
+		ata_port_desc_misc(ap, irq[i]);
 	}
 
 	return ata_host_register(host, &cs5520_sht);
@@ -246,6 +242,7 @@ static int cs5520_reinit_one(struct pci_dev *pdev)
 /**
  *	cs5520_pci_device_suspend	-	device suspend
  *	@pdev: PCI device
+ *	@mesg: PM event message
  *
  *	We have to cut and waste bits from the standard method because
  *	the 5520 is a bit odd and not just a pure ATA device. As a result
@@ -256,11 +253,8 @@ static int cs5520_reinit_one(struct pci_dev *pdev)
 static int cs5520_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
 {
 	struct ata_host *host = pci_get_drvdata(pdev);
-	int rc = 0;
 
-	rc = ata_host_suspend(host, mesg);
-	if (rc)
-		return rc;
+	ata_host_suspend(host, mesg);
 
 	pci_save_state(pdev);
 	return 0;
diff --git a/drivers/ata/pata_cs5530.c b/drivers/ata/pata_cs5530.c
index ad75d02b6dac..1e67b0f8db43 100644
--- a/drivers/ata/pata_cs5530.c
+++ b/drivers/ata/pata_cs5530.c
@@ -146,9 +146,10 @@ static unsigned int cs5530_qc_issue(struct ata_queued_cmd *qc)
 	return ata_bmdma_qc_issue(qc);
 }
 
-static struct scsi_host_template cs5530_sht = {
-	ATA_BMDMA_SHT(DRV_NAME),
+static const struct scsi_host_template cs5530_sht = {
+	ATA_BASE_SHT(DRV_NAME),
 	.sg_tablesize	= LIBATA_DUMB_MAX_PRD,
+	.dma_boundary	= ATA_DMA_BOUNDARY,
 };
 
 static struct ata_port_operations cs5530_port_ops = {
@@ -271,7 +272,7 @@ fail_put:
 
 /**
  *	cs5530_init_one		-	Initialise a CS5530
- *	@dev: PCI device
+ *	@pdev: PCI device
  *	@id: Entry in match table
  *
  *	Install a driver for the newly found CS5530 companion chip. Most of
diff --git a/drivers/ata/pata_cs5535.c b/drivers/ata/pata_cs5535.c
index 6725931f3c35..d793fc441b46 100644
--- a/drivers/ata/pata_cs5535.c
+++ b/drivers/ata/pata_cs5535.c
@@ -90,7 +90,7 @@ static void cs5535_set_piomode(struct ata_port *ap, struct ata_device *adev)
 	static const u16 pio_cmd_timings[5] = {
 		0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131
 	};
-	u32 reg, dummy;
+	u32 reg, __maybe_unused dummy;
 	struct ata_device *pair = ata_dev_pair(adev);
 
 	int mode = adev->pio_mode - XFER_PIO_0;
@@ -129,7 +129,7 @@ static void cs5535_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 	static const u32 mwdma_timings[3] = {
 		0x7F0FFFF3, 0x7F035352, 0x7F024241
 	};
-	u32 reg, dummy;
+	u32 reg, __maybe_unused dummy;
 	int mode = adev->dma_mode;
 
 	rdmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, dummy);
@@ -141,7 +141,7 @@ static void cs5535_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 	wrmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, 0);
 }
 
-static struct scsi_host_template cs5535_sht = {
+static const struct scsi_host_template cs5535_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
diff --git a/drivers/ata/pata_cs5536.c b/drivers/ata/pata_cs5536.c
index 760ac6e65216..73e81e160c91 100644
--- a/drivers/ata/pata_cs5536.c
+++ b/drivers/ata/pata_cs5536.c
@@ -27,7 +27,7 @@
 #include <scsi/scsi_host.h>
 #include <linux/dmi.h>
 
-#ifdef CONFIG_X86_32
+#if defined(CONFIG_X86) && defined(CONFIG_X86_32)
 #include <asm/msr.h>
 static int use_msr;
 module_param_named(msr, use_msr, int, 0644);
@@ -217,7 +217,7 @@ static void cs5536_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 	cs5536_write(pdev, ETC, etc);
 }
 
-static struct scsi_host_template cs5536_sht = {
+static const struct scsi_host_template cs5536_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
@@ -263,12 +263,12 @@ static int cs5536_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 	ppi[1] = &ata_dummy_port_info;
 
 	if (use_msr)
-		printk(KERN_ERR DRV_NAME ": Using MSR regs instead of PCI\n");
+		dev_err(&dev->dev, DRV_NAME ": Using MSR regs instead of PCI\n");
 
 	cs5536_read(dev, CFG, &cfg);
 
 	if ((cfg & IDE_CFG_CHANEN) == 0) {
-		printk(KERN_ERR DRV_NAME ": disabled by BIOS\n");
+		dev_err(&dev->dev, DRV_NAME ": disabled by BIOS\n");
 		return -ENODEV;
 	}
 
diff --git a/drivers/ata/pata_cypress.c b/drivers/ata/pata_cypress.c
index e1486fe298ae..ae347b5c2871 100644
--- a/drivers/ata/pata_cypress.c
+++ b/drivers/ata/pata_cypress.c
@@ -41,6 +41,10 @@ enum {
 	CY82_INDEX_TIMEOUT	= 0x32
 };
 
+static bool enable_dma = true;
+module_param(enable_dma, bool, 0);
+MODULE_PARM_DESC(enable_dma, "Enable bus master DMA operations");
+
 /**
  *	cy82c693_set_piomode	-	set initial PIO mode data
  *	@ap: ATA interface
@@ -58,7 +62,7 @@ static void cy82c693_set_piomode(struct ata_port *ap, struct ata_device *adev)
 	u32 addr;
 
 	if (ata_timing_compute(adev, adev->pio_mode, &t, T, 1) < 0) {
-		printk(KERN_ERR DRV_NAME ": mome computation failed.\n");
+		ata_dev_err(adev, DRV_NAME ": mome computation failed.\n");
 		return;
 	}
 
@@ -111,7 +115,7 @@ static void cy82c693_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 	outb(0x50, 0x23);
 }
 
-static struct scsi_host_template cy82c693_sht = {
+static const struct scsi_host_template cy82c693_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
@@ -124,14 +128,16 @@ static struct ata_port_operations cy82c693_port_ops = {
 
 static int cy82c693_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
 {
-	static const struct ata_port_info info = {
+	static struct ata_port_info info = {
 		.flags = ATA_FLAG_SLAVE_POSS,
 		.pio_mask = ATA_PIO4,
-		.mwdma_mask = ATA_MWDMA2,
 		.port_ops = &cy82c693_port_ops
 	};
 	const struct ata_port_info *ppi[] = { &info, &ata_dummy_port_info };
 
+	if (enable_dma)
+		info.mwdma_mask = ATA_MWDMA2;
+
 	/* Devfn 1 is the ATA primary. The secondary is magic and on devfn2.
 	   For the moment we don't handle the secondary. FIXME */
 
diff --git a/drivers/ata/pata_efar.c b/drivers/ata/pata_efar.c
index 21da59f35b41..6fe49b303fee 100644
--- a/drivers/ata/pata_efar.c
+++ b/drivers/ata/pata_efar.c
@@ -234,7 +234,7 @@ static void efar_set_dmamode (struct ata_port *ap, struct ata_device *adev)
 	spin_unlock_irqrestore(&efar_lock, flags);
 }
 
-static struct scsi_host_template efar_sht = {
+static const struct scsi_host_template efar_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
@@ -243,7 +243,7 @@ static struct ata_port_operations efar_ops = {
 	.cable_detect		= efar_cable_detect,
 	.set_piomode		= efar_set_piomode,
 	.set_dmamode		= efar_set_dmamode,
-	.prereset		= efar_pre_reset,
+	.reset.prereset		= efar_pre_reset,
 };
 
 
diff --git a/drivers/ata/pata_ep93xx.c b/drivers/ata/pata_ep93xx.c
index badab6708893..b2b9e0058333 100644
--- a/drivers/ata/pata_ep93xx.c
+++ b/drivers/ata/pata_ep93xx.c
@@ -40,11 +40,12 @@
 #include <linux/ata.h>
 #include <linux/libata.h>
 #include <linux/platform_device.h>
+#include <linux/sys_soc.h>
 #include <linux/delay.h>
 #include <linux/dmaengine.h>
 #include <linux/ktime.h>
+#include <linux/mod_devicetable.h>
 
-#include <linux/platform_data/dma-ep93xx.h>
 #include <linux/soc/cirrus/ep93xx.h>
 
 #define DRV_NAME	"ep93xx-ide"
@@ -125,7 +126,7 @@ enum {
 };
 
 struct ep93xx_pata_data {
-	const struct platform_device *pdev;
+	struct platform_device *pdev;
 	void __iomem *ide_base;
 	struct ata_timing t;
 	bool iordy;
@@ -134,9 +135,7 @@ struct ep93xx_pata_data {
 	unsigned long udma_out_phys;
 
 	struct dma_chan *dma_rx_channel;
-	struct ep93xx_dma_data dma_rx_data;
 	struct dma_chan *dma_tx_channel;
-	struct ep93xx_dma_data dma_tx_data;
 };
 
 static void ep93xx_pata_clear_regs(void __iomem *base)
@@ -416,8 +415,8 @@ static void ep93xx_pata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
 {
 	struct ep93xx_pata_data *drv_data = ap->host->private_data;
 
-	tf->command = ep93xx_pata_check_status(ap);
-	tf->feature = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_FEATURE);
+	tf->status = ep93xx_pata_check_status(ap);
+	tf->error = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_FEATURE);
 	tf->nsect = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_NSECT);
 	tf->lbal = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_LBAL);
 	tf->lbam = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_LBAM);
@@ -636,20 +635,13 @@ static void ep93xx_pata_release_dma(struct ep93xx_pata_data *drv_data)
 	}
 }
 
-static bool ep93xx_pata_dma_filter(struct dma_chan *chan, void *filter_param)
+static int ep93xx_pata_dma_init(struct ep93xx_pata_data *drv_data)
 {
-	if (ep93xx_dma_chan_is_m2p(chan))
-		return false;
-
-	chan->private = filter_param;
-	return true;
-}
-
-static void ep93xx_pata_dma_init(struct ep93xx_pata_data *drv_data)
-{
-	const struct platform_device *pdev = drv_data->pdev;
+	struct platform_device *pdev = drv_data->pdev;
+	struct device *dev = &pdev->dev;
 	dma_cap_mask_t mask;
 	struct dma_slave_config conf;
+	int ret;
 
 	dma_cap_zero(mask);
 	dma_cap_set(DMA_SLAVE, mask);
@@ -659,22 +651,16 @@ static void ep93xx_pata_dma_init(struct ep93xx_pata_data *drv_data)
 	 * to request only one channel, and reprogram it's direction at
 	 * start of new transfer.
 	 */
-	drv_data->dma_rx_data.port = EP93XX_DMA_IDE;
-	drv_data->dma_rx_data.direction = DMA_DEV_TO_MEM;
-	drv_data->dma_rx_data.name = "ep93xx-pata-rx";
-	drv_data->dma_rx_channel = dma_request_channel(mask,
-		ep93xx_pata_dma_filter, &drv_data->dma_rx_data);
-	if (!drv_data->dma_rx_channel)
-		return;
-
-	drv_data->dma_tx_data.port = EP93XX_DMA_IDE;
-	drv_data->dma_tx_data.direction = DMA_MEM_TO_DEV;
-	drv_data->dma_tx_data.name = "ep93xx-pata-tx";
-	drv_data->dma_tx_channel = dma_request_channel(mask,
-		ep93xx_pata_dma_filter, &drv_data->dma_tx_data);
-	if (!drv_data->dma_tx_channel) {
-		dma_release_channel(drv_data->dma_rx_channel);
-		return;
+	drv_data->dma_rx_channel = dma_request_chan(dev, "rx");
+	if (IS_ERR(drv_data->dma_rx_channel))
+		return dev_err_probe(dev, PTR_ERR(drv_data->dma_rx_channel),
+				     "rx DMA setup failed\n");
+
+	drv_data->dma_tx_channel = dma_request_chan(&pdev->dev, "tx");
+	if (IS_ERR(drv_data->dma_tx_channel)) {
+		ret = dev_err_probe(dev, PTR_ERR(drv_data->dma_tx_channel),
+				    "tx DMA setup failed\n");
+		goto fail_release_rx;
 	}
 
 	/* Configure receive channel direction and source address */
@@ -682,10 +668,10 @@ static void ep93xx_pata_dma_init(struct ep93xx_pata_data *drv_data)
 	conf.direction = DMA_DEV_TO_MEM;
 	conf.src_addr = drv_data->udma_in_phys;
 	conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
-	if (dmaengine_slave_config(drv_data->dma_rx_channel, &conf)) {
-		dev_err(&pdev->dev, "failed to configure rx dma channel\n");
-		ep93xx_pata_release_dma(drv_data);
-		return;
+	ret = dmaengine_slave_config(drv_data->dma_rx_channel, &conf);
+	if (ret) {
+		dev_err_probe(dev, ret, "failed to configure rx dma channel");
+		goto fail_release_dma;
 	}
 
 	/* Configure transmit channel direction and destination address */
@@ -693,10 +679,20 @@ static void ep93xx_pata_dma_init(struct ep93xx_pata_data *drv_data)
 	conf.direction = DMA_MEM_TO_DEV;
 	conf.dst_addr = drv_data->udma_out_phys;
 	conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
-	if (dmaengine_slave_config(drv_data->dma_tx_channel, &conf)) {
-		dev_err(&pdev->dev, "failed to configure tx dma channel\n");
-		ep93xx_pata_release_dma(drv_data);
+	ret = dmaengine_slave_config(drv_data->dma_tx_channel, &conf);
+	if (ret) {
+		dev_err_probe(dev, ret, "failed to configure tx dma channel");
+		goto fail_release_dma;
 	}
+
+	return 0;
+
+fail_release_rx:
+	dma_release_channel(drv_data->dma_rx_channel);
+fail_release_dma:
+	ep93xx_pata_release_dma(drv_data);
+
+	return ret;
 }
 
 static void ep93xx_pata_dma_start(struct ata_queued_cmd *qc)
@@ -855,7 +851,6 @@ static void ep93xx_pata_drain_fifo(struct ata_queued_cmd *qc)
 		     && count < 65536; count += 2)
 		ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_DATA);
 
-	/* Can become DEBUG later */
 	if (count)
 		ata_port_dbg(ap, "drained %d bytes to clear DRQ.\n", count);
 
@@ -873,7 +868,7 @@ static int ep93xx_pata_port_start(struct ata_port *ap)
 	return 0;
 }
 
-static struct scsi_host_template ep93xx_pata_sht = {
+static const struct scsi_host_template ep93xx_pata_sht = {
 	ATA_BASE_SHT(DRV_NAME),
 	/* ep93xx dma implementation limit */
 	.sg_tablesize		= 32,
@@ -884,10 +879,8 @@ static struct scsi_host_template ep93xx_pata_sht = {
 static struct ata_port_operations ep93xx_pata_port_ops = {
 	.inherits		= &ata_bmdma_port_ops,
 
-	.qc_prep		= ata_noop_qc_prep,
-
-	.softreset		= ep93xx_pata_softreset,
-	.hardreset		= ATA_OP_NULL,
+	.reset.softreset	= ep93xx_pata_softreset,
+	.reset.hardreset	= ATA_OP_NULL,
 
 	.sff_dev_select		= ep93xx_pata_dev_select,
 	.sff_set_devctl		= ep93xx_pata_set_devctl,
@@ -911,6 +904,12 @@ static struct ata_port_operations ep93xx_pata_port_ops = {
 	.port_start		= ep93xx_pata_port_start,
 };
 
+static const struct soc_device_attribute ep93xx_soc_table[] = {
+	{ .revision = "E1", .data = (void *)ATA_UDMA3 },
+	{ .revision = "E2", .data = (void *)ATA_UDMA4 },
+	{ /* sentinel */ }
+};
+
 static int ep93xx_pata_probe(struct platform_device *pdev)
 {
 	struct ep93xx_pata_data *drv_data;
@@ -921,40 +920,31 @@ static int ep93xx_pata_probe(struct platform_device *pdev)
 	void __iomem *ide_base;
 	int err;
 
-	err = ep93xx_ide_acquire_gpio(pdev);
-	if (err)
-		return err;
-
 	/* INT[3] (IRQ_EP93XX_EXT3) line connected as pull down */
 	irq = platform_get_irq(pdev, 0);
-	if (irq < 0) {
-		err = -ENXIO;
-		goto err_rel_gpio;
-	}
+	if (irq < 0)
+		return irq;
 
-	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	ide_base = devm_ioremap_resource(&pdev->dev, mem_res);
-	if (IS_ERR(ide_base)) {
-		err = PTR_ERR(ide_base);
-		goto err_rel_gpio;
-	}
+	ide_base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem_res);
+	if (IS_ERR(ide_base))
+		return PTR_ERR(ide_base);
 
 	drv_data = devm_kzalloc(&pdev->dev, sizeof(*drv_data), GFP_KERNEL);
-	if (!drv_data) {
-		err = -ENXIO;
-		goto err_rel_gpio;
-	}
+	if (!drv_data)
+		return -ENOMEM;
 
 	drv_data->pdev = pdev;
 	drv_data->ide_base = ide_base;
 	drv_data->udma_in_phys = mem_res->start + IDEUDMADATAIN;
 	drv_data->udma_out_phys = mem_res->start + IDEUDMADATAOUT;
-	ep93xx_pata_dma_init(drv_data);
+	err = ep93xx_pata_dma_init(drv_data);
+	if (err)
+		return err;
 
 	/* allocate host */
 	host = ata_host_alloc(&pdev->dev, 1);
 	if (!host) {
-		err = -ENXIO;
+		err = -ENOMEM;
 		goto err_rel_dma;
 	}
 
@@ -978,12 +968,11 @@ static int ep93xx_pata_probe(struct platform_device *pdev)
 	 * so this driver supports only UDMA modes.
 	 */
 	if (drv_data->dma_rx_channel && drv_data->dma_tx_channel) {
-		int chip_rev = ep93xx_chip_revision();
+		const struct soc_device_attribute *match;
 
-		if (chip_rev == EP93XX_CHIP_REV_E1)
-			ap->udma_mask = ATA_UDMA3;
-		else if (chip_rev == EP93XX_CHIP_REV_E2)
-			ap->udma_mask = ATA_UDMA4;
+		match = soc_device_match(ep93xx_soc_table);
+		if (match)
+			ap->udma_mask = (unsigned int) match->data;
 		else
 			ap->udma_mask = ATA_UDMA2;
 	}
@@ -1001,12 +990,10 @@ static int ep93xx_pata_probe(struct platform_device *pdev)
 
 err_rel_dma:
 	ep93xx_pata_release_dma(drv_data);
-err_rel_gpio:
-	ep93xx_ide_release_gpio(pdev);
 	return err;
 }
 
-static int ep93xx_pata_remove(struct platform_device *pdev)
+static void ep93xx_pata_remove(struct platform_device *pdev)
 {
 	struct ata_host *host = platform_get_drvdata(pdev);
 	struct ep93xx_pata_data *drv_data = host->private_data;
@@ -1014,13 +1001,18 @@ static int ep93xx_pata_remove(struct platform_device *pdev)
 	ata_host_detach(host);
 	ep93xx_pata_release_dma(drv_data);
 	ep93xx_pata_clear_regs(drv_data->ide_base);
-	ep93xx_ide_release_gpio(pdev);
-	return 0;
 }
 
+static const struct of_device_id ep93xx_pata_of_ids[] = {
+	{ .compatible = "cirrus,ep9312-pata" },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, ep93xx_pata_of_ids);
+
 static struct platform_driver ep93xx_pata_platform_driver = {
 	.driver = {
 		.name = DRV_NAME,
+		.of_match_table = ep93xx_pata_of_ids,
 	},
 	.probe = ep93xx_pata_probe,
 	.remove = ep93xx_pata_remove,
diff --git a/drivers/ata/pata_falcon.c b/drivers/ata/pata_falcon.c
index 27b0952fde6b..334c4eea41ec 100644
--- a/drivers/ata/pata_falcon.c
+++ b/drivers/ata/pata_falcon.c
@@ -28,14 +28,16 @@
 #include <asm/atarihw.h>
 #include <asm/atariints.h>
 #include <asm/atari_stdma.h>
-#include <asm/ide.h>
 
 #define DRV_NAME "pata_falcon"
 #define DRV_VERSION "0.1.0"
 
-#define ATA_HD_CONTROL	0x39
+static int pata_falcon_swap_mask;
 
-static struct scsi_host_template pata_falcon_sht = {
+module_param_named(data_swab, pata_falcon_swap_mask, int, 0444);
+MODULE_PARM_DESC(data_swab, "Data byte swap enable/disable bitmap (0x1==drive1, 0x2==drive2, 0x4==drive3, 0x8==drive4, default==0)");
+
+static const struct scsi_host_template pata_falcon_sht = {
 	ATA_PIO_SHT(DRV_NAME),
 };
 
@@ -50,21 +52,21 @@ static unsigned int pata_falcon_data_xfer(struct ata_queued_cmd *qc,
 	struct scsi_cmnd *cmd = qc->scsicmd;
 	bool swap = 1;
 
-	if (dev->class == ATA_DEV_ATA && cmd && cmd->request &&
-	    !blk_rq_is_passthrough(cmd->request))
-		swap = 0;
+	if (dev->class == ATA_DEV_ATA && cmd &&
+	    !blk_rq_is_passthrough(scsi_cmd_to_rq(cmd)))
+		swap = (uintptr_t)ap->private_data & BIT(dev->devno);
 
 	/* Transfer multiple of 2 bytes */
 	if (rw == READ) {
 		if (swap)
-			raw_insw_swapw((u16 *)data_addr, (u16 *)buf, words);
+			raw_insw_swapw(data_addr, (u16 *)buf, words);
 		else
-			raw_insw((u16 *)data_addr, (u16 *)buf, words);
+			raw_insw(data_addr, (u16 *)buf, words);
 	} else {
 		if (swap)
-			raw_outsw_swapw((u16 *)data_addr, (u16 *)buf, words);
+			raw_outsw_swapw(data_addr, (u16 *)buf, words);
 		else
-			raw_outsw((u16 *)data_addr, (u16 *)buf, words);
+			raw_outsw(data_addr, (u16 *)buf, words);
 	}
 
 	/* Transfer trailing byte, if any. */
@@ -76,16 +78,16 @@ static unsigned int pata_falcon_data_xfer(struct ata_queued_cmd *qc,
 
 		if (rw == READ) {
 			if (swap)
-				raw_insw_swapw((u16 *)data_addr, (u16 *)pad, 1);
+				raw_insw_swapw(data_addr, (u16 *)pad, 1);
 			else
-				raw_insw((u16 *)data_addr, (u16 *)pad, 1);
+				raw_insw(data_addr, (u16 *)pad, 1);
 			*buf = pad[0];
 		} else {
 			pad[0] = *buf;
 			if (swap)
-				raw_outsw_swapw((u16 *)data_addr, (u16 *)pad, 1);
+				raw_outsw_swapw(data_addr, (u16 *)pad, 1);
 			else
-				raw_outsw((u16 *)data_addr, (u16 *)pad, 1);
+				raw_outsw(data_addr, (u16 *)pad, 1);
 		}
 		words++;
 	}
@@ -119,25 +121,45 @@ static struct ata_port_operations pata_falcon_ops = {
 	.set_mode	= pata_falcon_set_mode,
 };
 
-static int __init pata_falcon_init_one(struct platform_device *pdev)
+static int pata_falcon_init_one(struct platform_device *pdev)
 {
-	struct resource *res;
+	struct resource *base_mem_res, *ctl_mem_res;
+	struct resource *base_res, *ctl_res, *irq_res;
 	struct ata_host *host;
 	struct ata_port *ap;
-	void __iomem *base;
+	void __iomem *base, *ctl_base;
+	int mask_shift = 0; /* Q40 & Falcon default */
+	int irq = 0, io_offset = 1, reg_shift = 2; /* Falcon defaults */
 
-	dev_info(&pdev->dev, "Atari Falcon PATA controller\n");
+	dev_info(&pdev->dev, "Atari Falcon and Q40/Q60 PATA controller\n");
 
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (!res)
-		return -ENODEV;
+	base_res = platform_get_resource(pdev, IORESOURCE_IO, 0);
+	if (base_res && !devm_request_region(&pdev->dev, base_res->start,
+					   resource_size(base_res), DRV_NAME)) {
+		dev_err(&pdev->dev, "resources busy\n");
+		return -EBUSY;
+	}
 
-	if (!devm_request_mem_region(&pdev->dev, res->start,
-				     resource_size(res), DRV_NAME)) {
+	ctl_res = platform_get_resource(pdev, IORESOURCE_IO, 1);
+	if (ctl_res && !devm_request_region(&pdev->dev, ctl_res->start,
+					    resource_size(ctl_res), DRV_NAME)) {
 		dev_err(&pdev->dev, "resources busy\n");
 		return -EBUSY;
 	}
 
+	base_mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!base_mem_res)
+		return -ENODEV;
+	if (!devm_request_mem_region(&pdev->dev, base_mem_res->start,
+				     resource_size(base_mem_res), DRV_NAME)) {
+		dev_err(&pdev->dev, "resources busy\n");
+		return -EBUSY;
+	}
+
+	ctl_mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	if (!ctl_mem_res)
+		return -ENODEV;
+
 	/* allocate host */
 	host = ata_host_alloc(&pdev->dev, 1);
 	if (!host)
@@ -147,47 +169,69 @@ static int __init pata_falcon_init_one(struct platform_device *pdev)
 	ap->ops = &pata_falcon_ops;
 	ap->pio_mask = ATA_PIO4;
 	ap->flags |= ATA_FLAG_SLAVE_POSS | ATA_FLAG_NO_IORDY;
-	ap->flags |= ATA_FLAG_PIO_POLLING;
-
-	base = (void __iomem *)res->start;
-	ap->ioaddr.data_addr		= base;
-	ap->ioaddr.error_addr		= base + 1 + 1 * 4;
-	ap->ioaddr.feature_addr		= base + 1 + 1 * 4;
-	ap->ioaddr.nsect_addr		= base + 1 + 2 * 4;
-	ap->ioaddr.lbal_addr		= base + 1 + 3 * 4;
-	ap->ioaddr.lbam_addr		= base + 1 + 4 * 4;
-	ap->ioaddr.lbah_addr		= base + 1 + 5 * 4;
-	ap->ioaddr.device_addr		= base + 1 + 6 * 4;
-	ap->ioaddr.status_addr		= base + 1 + 7 * 4;
-	ap->ioaddr.command_addr		= base + 1 + 7 * 4;
-
-	ap->ioaddr.altstatus_addr	= base + ATA_HD_CONTROL;
-	ap->ioaddr.ctl_addr		= base + ATA_HD_CONTROL;
-
-	ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", (unsigned long)base,
-		      (unsigned long)base + ATA_HD_CONTROL);
+
+	/* N.B. this assumes data_addr will be used for word-sized I/O only */
+	ap->ioaddr.data_addr = (void __iomem *)base_mem_res->start;
+
+	if (base_res) {		/* only Q40 has IO resources */
+		io_offset = 0x10000;
+		reg_shift = 0;
+		base = (void __iomem *)base_res->start;
+		ctl_base = (void __iomem *)ctl_res->start;
+	} else {
+		base = (void __iomem *)base_mem_res->start;
+		ctl_base = (void __iomem *)ctl_mem_res->start;
+	}
+
+	ap->ioaddr.error_addr	= base + io_offset + (1 << reg_shift);
+	ap->ioaddr.feature_addr	= base + io_offset + (1 << reg_shift);
+	ap->ioaddr.nsect_addr	= base + io_offset + (2 << reg_shift);
+	ap->ioaddr.lbal_addr	= base + io_offset + (3 << reg_shift);
+	ap->ioaddr.lbam_addr	= base + io_offset + (4 << reg_shift);
+	ap->ioaddr.lbah_addr	= base + io_offset + (5 << reg_shift);
+	ap->ioaddr.device_addr	= base + io_offset + (6 << reg_shift);
+	ap->ioaddr.status_addr	= base + io_offset + (7 << reg_shift);
+	ap->ioaddr.command_addr	= base + io_offset + (7 << reg_shift);
+
+	ap->ioaddr.altstatus_addr	= ctl_base + io_offset;
+	ap->ioaddr.ctl_addr		= ctl_base + io_offset;
+
+	ata_port_desc(ap, "cmd %px ctl %px data %px",
+		      base, ctl_base, ap->ioaddr.data_addr);
+
+	if (pdev->id > 0)
+		mask_shift = 2;
+	ap->private_data = (void *)(uintptr_t)(pata_falcon_swap_mask >> mask_shift);
+
+	irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (irq_res && irq_res->start > 0) {
+		irq = irq_res->start;
+	} else {
+		ap->flags |= ATA_FLAG_PIO_POLLING;
+		ata_port_desc(ap, "no IRQ, using PIO polling");
+	}
 
 	/* activate */
-	return ata_host_activate(host, 0, NULL, 0, &pata_falcon_sht);
+	return ata_host_activate(host, irq, irq ? ata_sff_interrupt : NULL,
+				 IRQF_SHARED, &pata_falcon_sht);
 }
 
-static int __exit pata_falcon_remove_one(struct platform_device *pdev)
+static void pata_falcon_remove_one(struct platform_device *pdev)
 {
 	struct ata_host *host = platform_get_drvdata(pdev);
 
 	ata_host_detach(host);
-
-	return 0;
 }
 
 static struct platform_driver pata_falcon_driver = {
-	.remove = __exit_p(pata_falcon_remove_one),
-	.driver   = {
+	.probe = pata_falcon_init_one,
+	.remove = pata_falcon_remove_one,
+	.driver = {
 		.name	= "atari-falcon-ide",
 	},
 };
 
-module_platform_driver_probe(pata_falcon_driver, pata_falcon_init_one);
+module_platform_driver(pata_falcon_driver);
 
 MODULE_AUTHOR("Bartlomiej Zolnierkiewicz");
 MODULE_DESCRIPTION("low-level driver for Atari Falcon PATA");
diff --git a/drivers/ata/pata_ftide010.c b/drivers/ata/pata_ftide010.c
index 34cb104f6b43..c3a8384c3e04 100644
--- a/drivers/ata/pata_ftide010.c
+++ b/drivers/ata/pata_ftide010.c
@@ -14,8 +14,7 @@
 #include <linux/module.h>
 #include <linux/libata.h>
 #include <linux/bitops.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
 #include <linux/clk.h>
 #include "sata_gemini.h"
 
@@ -84,7 +83,7 @@ struct ftide010 {
 #define FTIDE010_CLK_MOD_DEV0_UDMA_EN	BIT(4)
 #define FTIDE010_CLK_MOD_DEV1_UDMA_EN	BIT(5)
 
-static struct scsi_host_template pata_ftide010_sht = {
+static const struct scsi_host_template pata_ftide010_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
@@ -470,11 +469,7 @@ static int pata_ftide010_probe(struct platform_device *pdev)
 	if (irq < 0)
 		return irq;
 
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (!res)
-		return -ENODEV;
-
-	ftide->base = devm_ioremap_resource(dev, res);
+	ftide->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
 	if (IS_ERR(ftide->base))
 		return PTR_ERR(ftide->base);
 
@@ -536,40 +531,37 @@ static int pata_ftide010_probe(struct platform_device *pdev)
 	return 0;
 
 err_dis_clk:
-	if (!IS_ERR(ftide->pclk))
-		clk_disable_unprepare(ftide->pclk);
+	clk_disable_unprepare(ftide->pclk);
+
 	return ret;
 }
 
-static int pata_ftide010_remove(struct platform_device *pdev)
+static void pata_ftide010_remove(struct platform_device *pdev)
 {
 	struct ata_host *host = platform_get_drvdata(pdev);
 	struct ftide010 *ftide = host->private_data;
 
 	ata_host_detach(ftide->host);
-	if (!IS_ERR(ftide->pclk))
-		clk_disable_unprepare(ftide->pclk);
-
-	return 0;
+	clk_disable_unprepare(ftide->pclk);
 }
 
 static const struct of_device_id pata_ftide010_of_match[] = {
-	{
-		.compatible = "faraday,ftide010",
-	},
-	{},
+	{ .compatible = "faraday,ftide010", },
+	{ /* sentinel */ }
 };
+MODULE_DEVICE_TABLE(of, pata_ftide010_of_match);
 
 static struct platform_driver pata_ftide010_driver = {
 	.driver = {
 		.name = DRV_NAME,
-		.of_match_table = of_match_ptr(pata_ftide010_of_match),
+		.of_match_table = pata_ftide010_of_match,
 	},
 	.probe = pata_ftide010_probe,
 	.remove = pata_ftide010_remove,
 };
 module_platform_driver(pata_ftide010_driver);
 
+MODULE_DESCRIPTION("low level driver for Faraday Technology FTIDE010");
 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
 MODULE_LICENSE("GPL");
 MODULE_ALIAS("platform:" DRV_NAME);
diff --git a/drivers/ata/pata_gayle.c b/drivers/ata/pata_gayle.c
index 65bc9f3042ce..8602c3889948 100644
--- a/drivers/ata/pata_gayle.c
+++ b/drivers/ata/pata_gayle.c
@@ -27,7 +27,6 @@
 #include <asm/amigahw.h>
 #include <asm/amigaints.h>
 #include <asm/amigayle.h>
-#include <asm/ide.h>
 #include <asm/setup.h>
 
 #define DRV_NAME "pata_gayle"
@@ -35,7 +34,7 @@
 
 #define GAYLE_CONTROL	0x101a
 
-static struct scsi_host_template pata_gayle_sht = {
+static const struct scsi_host_template pata_gayle_sht = {
 	ATA_PIO_SHT(DRV_NAME),
 };
 
@@ -125,7 +124,7 @@ static struct ata_port_operations pata_gayle_a4000_ops = {
 	.set_mode	= pata_gayle_set_mode,
 };
 
-static int __init pata_gayle_init_one(struct platform_device *pdev)
+static int pata_gayle_init_one(struct platform_device *pdev)
 {
 	struct resource *res;
 	struct gayle_ide_platform_data *pdata;
@@ -194,23 +193,22 @@ static int __init pata_gayle_init_one(struct platform_device *pdev)
 	return 0;
 }
 
-static int __exit pata_gayle_remove_one(struct platform_device *pdev)
+static void pata_gayle_remove_one(struct platform_device *pdev)
 {
 	struct ata_host *host = platform_get_drvdata(pdev);
 
 	ata_host_detach(host);
-
-	return 0;
 }
 
 static struct platform_driver pata_gayle_driver = {
-	.remove = __exit_p(pata_gayle_remove_one),
-	.driver   = {
-		.name	= "amiga-gayle-ide",
+	.probe = pata_gayle_init_one,
+	.remove = pata_gayle_remove_one,
+	.driver = {
+		.name = "amiga-gayle-ide",
 	},
 };
 
-module_platform_driver_probe(pata_gayle_driver, pata_gayle_init_one);
+module_platform_driver(pata_gayle_driver);
 
 MODULE_AUTHOR("Bartlomiej Zolnierkiewicz");
 MODULE_DESCRIPTION("low-level driver for Amiga Gayle PATA");
diff --git a/drivers/ata/pata_hpt366.c b/drivers/ata/pata_hpt366.c
index 2574d6fbb1ad..b96e8bd2a3f8 100644
--- a/drivers/ata/pata_hpt366.c
+++ b/drivers/ata/pata_hpt366.c
@@ -14,9 +14,6 @@
  * TODO
  *	Look into engine reset on timeout errors. Should not be required.
  */
-
-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
-
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/pci.h>
@@ -26,7 +23,7 @@
 #include <linux/libata.h>
 
 #define DRV_NAME	"pata_hpt366"
-#define DRV_VERSION	"0.6.11"
+#define DRV_VERSION	"0.6.13"
 
 struct hpt_clock {
 	u8	xfer_mode;
@@ -173,8 +170,8 @@ static const char * const bad_ata66_3[] = {
 	NULL
 };
 
-static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr,
-			       const char * const list[])
+static int hpt_dma_broken(const struct ata_device *dev, char *modestr,
+			  const char * const list[])
 {
 	unsigned char model_num[ATA_ID_PROD_LEN + 1];
 	int i;
@@ -183,7 +180,7 @@ static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr,
 
 	i = match_string(list, -1, model_num);
 	if (i >= 0) {
-		pr_warn("%s is not supported for %s\n", modestr, list[i]);
+		ata_dev_warn(dev, "%s is not supported for %s\n", modestr, list[i]);
 		return 1;
 	}
 	return 0;
@@ -192,18 +189,19 @@ static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr,
 /**
  *	hpt366_filter	-	mode selection filter
  *	@adev: ATA device
+ *	@mask: Current mask to manipulate and pass back
  *
  *	Block UDMA on devices that cause trouble with this controller.
  */
 
-static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask)
+static unsigned int hpt366_filter(struct ata_device *adev, unsigned int mask)
 {
 	if (adev->class == ATA_DEV_ATA) {
-		if (hpt_dma_blacklisted(adev, "UDMA",  bad_ata33))
+		if (hpt_dma_broken(adev, "UDMA",  bad_ata33))
 			mask &= ~ATA_MASK_UDMA;
-		if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3))
+		if (hpt_dma_broken(adev, "UDMA3", bad_ata66_3))
 			mask &= ~(0xF8 << ATA_SHIFT_UDMA);
-		if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4))
+		if (hpt_dma_broken(adev, "UDMA4", bad_ata66_4))
 			mask &= ~(0xF0 << ATA_SHIFT_UDMA);
 	} else if (adev->class == ATA_DEV_ATAPI)
 		mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
@@ -280,7 +278,41 @@ static void hpt366_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 	hpt366_set_mode(ap, adev, adev->dma_mode);
 }
 
-static struct scsi_host_template hpt36x_sht = {
+/**
+ *	hpt366_prereset		-	reset the hpt36x bus
+ *	@link: ATA link to reset
+ *	@deadline: deadline jiffies for the operation
+ *
+ *	Perform the initial reset handling for the 36x series controllers.
+ *	Reset the hardware and state machine,
+ */
+
+static int hpt366_prereset(struct ata_link *link, unsigned long deadline)
+{
+	struct ata_port *ap = link->ap;
+	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
+	/*
+	 * HPT36x chips have one channel per function and have
+	 * both channel enable bits located differently and visible
+	 * to both functions -- really stupid design decision... :-(
+	 * Bit 4 is for the primary channel, bit 5 for the secondary.
+	 */
+	static const struct pci_bits hpt366_enable_bits = {
+		0x50, 1, 0x30, 0x30
+	};
+	u8 mcr2;
+
+	if (!pci_test_config_bits(pdev, &hpt366_enable_bits))
+		return -ENOENT;
+
+	pci_read_config_byte(pdev, 0x51, &mcr2);
+	if (mcr2 & 0x80)
+		pci_write_config_byte(pdev, 0x51, mcr2 & ~0x80);
+
+	return ata_sff_prereset(link, deadline);
+}
+
+static const struct scsi_host_template hpt36x_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
@@ -290,6 +322,7 @@ static struct scsi_host_template hpt36x_sht = {
 
 static struct ata_port_operations hpt366_port_ops = {
 	.inherits	= &ata_bmdma_port_ops,
+	.reset.prereset	= hpt366_prereset,
 	.cable_detect	= hpt36x_cable_detect,
 	.mode_filter	= hpt366_filter,
 	.set_piomode	= hpt366_set_piomode,
@@ -306,16 +339,20 @@ static struct ata_port_operations hpt366_port_ops = {
 
 static void hpt36x_init_chipset(struct pci_dev *dev)
 {
-	u8 drive_fast;
+	u8 mcr1;
 
 	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
 	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
 	pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
 	pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
 
-	pci_read_config_byte(dev, 0x51, &drive_fast);
-	if (drive_fast & 0x80)
-		pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
+	/*
+	 * Now we'll have to force both channels enabled if at least one
+	 * of them has been enabled by BIOS...
+	 */
+	pci_read_config_byte(dev, 0x50, &mcr1);
+	if (mcr1 & 0x30)
+		pci_write_config_byte(dev, 0x50, mcr1 | 0x30);
 }
 
 /**
diff --git a/drivers/ata/pata_hpt37x.c b/drivers/ata/pata_hpt37x.c
index fad6c6a87313..07e3a984cbb1 100644
--- a/drivers/ata/pata_hpt37x.c
+++ b/drivers/ata/pata_hpt37x.c
@@ -14,9 +14,6 @@
  * TODO
  *	Look into engine reset on timeout errors. Should not be	required.
  */
-
-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
-
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/pci.h>
@@ -26,7 +23,7 @@
 #include <linux/libata.h>
 
 #define DRV_NAME	"pata_hpt37x"
-#define DRV_VERSION	"0.6.23"
+#define DRV_VERSION	"0.6.30"
 
 struct hpt_clock {
 	u8	xfer_speed;
@@ -221,8 +218,8 @@ static u32 hpt37x_find_mode(struct ata_port *ap, int speed)
 	return 0xffffffffU;	/* silence compiler warning */
 }
 
-static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr,
-			       const char * const list[])
+static int hpt_dma_broken(const struct ata_device *dev, char *modestr,
+			  const char * const list[])
 {
 	unsigned char model_num[ATA_ID_PROD_LEN + 1];
 	int i;
@@ -231,7 +228,8 @@ static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr,
 
 	i = match_string(list, -1, model_num);
 	if (i >= 0) {
-		pr_warn("%s is not supported for %s\n", modestr, list[i]);
+		ata_dev_warn(dev, "%s is not supported for %s\n",
+			     modestr, list[i]);
 		return 1;
 	}
 	return 0;
@@ -275,16 +273,17 @@ static const char * const bad_ata100_5[] = {
 /**
  *	hpt370_filter	-	mode selection filter
  *	@adev: ATA device
+ *	@mask: mode mask
  *
  *	Block UDMA on devices that cause trouble with this controller.
  */
 
-static unsigned long hpt370_filter(struct ata_device *adev, unsigned long mask)
+static unsigned int hpt370_filter(struct ata_device *adev, unsigned int mask)
 {
 	if (adev->class == ATA_DEV_ATA) {
-		if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
+		if (hpt_dma_broken(adev, "UDMA", bad_ata33))
 			mask &= ~ATA_MASK_UDMA;
-		if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
+		if (hpt_dma_broken(adev, "UDMA100", bad_ata100_5))
 			mask &= ~(0xE0 << ATA_SHIFT_UDMA);
 	}
 	return mask;
@@ -293,14 +292,15 @@ static unsigned long hpt370_filter(struct ata_device *adev, unsigned long mask)
 /**
  *	hpt370a_filter	-	mode selection filter
  *	@adev: ATA device
+ *	@mask: mode mask
  *
  *	Block UDMA on devices that cause trouble with this controller.
  */
 
-static unsigned long hpt370a_filter(struct ata_device *adev, unsigned long mask)
+static unsigned int hpt370a_filter(struct ata_device *adev, unsigned int mask)
 {
 	if (adev->class == ATA_DEV_ATA) {
-		if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
+		if (hpt_dma_broken(adev, "UDMA100", bad_ata100_5))
 			mask &= ~(0xE0 << ATA_SHIFT_UDMA);
 	}
 	return mask;
@@ -314,7 +314,7 @@ static unsigned long hpt370a_filter(struct ata_device *adev, unsigned long mask)
  *	The Marvell bridge chips used on the HighPoint SATA cards do not seem
  *	to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
  */
-static unsigned long hpt372_filter(struct ata_device *adev, unsigned long mask)
+static unsigned int hpt372_filter(struct ata_device *adev, unsigned int mask)
 {
 	if (ata_id_is_sata(adev->id))
 		mask &= ~((0xE << ATA_SHIFT_UDMA) | ATA_MASK_MWDMA);
@@ -394,6 +394,7 @@ static int hpt37x_pre_reset(struct ata_link *link, unsigned long deadline)
 		{ 0x50, 1, 0x04, 0x04 },
 		{ 0x54, 1, 0x04, 0x04 }
 	};
+	u8 mcr2;
 
 	if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no]))
 		return -ENOENT;
@@ -402,25 +403,29 @@ static int hpt37x_pre_reset(struct ata_link *link, unsigned long deadline)
 	pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
 	udelay(100);
 
+	/*
+	 * Disable the "fast interrupt" prediction.  Don't hold off
+	 * on interrupts. (== 0x01 despite what the docs say)
+	 */
+	pci_read_config_byte(pdev, 0x51 + 4 * ap->port_no, &mcr2);
+	/* Is it HPT370/A? */
+	if (pdev->device == PCI_DEVICE_ID_TTI_HPT366 && pdev->revision < 5) {
+		mcr2 &= ~0x02;
+		mcr2 |= 0x01;
+	} else {
+		mcr2 &= ~0x07;
+	}
+	pci_write_config_byte(pdev, 0x51 + 4 * ap->port_no, mcr2);
+
 	return ata_sff_prereset(link, deadline);
 }
 
-static void hpt370_set_mode(struct ata_port *ap, struct ata_device *adev,
+static void hpt37x_set_mode(struct ata_port *ap, struct ata_device *adev,
 			    u8 mode)
 {
 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
-	u32 addr1, addr2;
+	int addr = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
 	u32 reg, timing, mask;
-	u8 fast;
-
-	addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
-	addr2 = 0x51 + 4 * ap->port_no;
-
-	/* Fast interrupt prediction disable, hold off interrupt disable */
-	pci_read_config_byte(pdev, addr2, &fast);
-	fast &= ~0x02;
-	fast |= 0x01;
-	pci_write_config_byte(pdev, addr2, fast);
 
 	/* Determine timing mask and find matching mode entry */
 	if (mode < XFER_MW_DMA_0)
@@ -432,38 +437,38 @@ static void hpt370_set_mode(struct ata_port *ap, struct ata_device *adev,
 
 	timing = hpt37x_find_mode(ap, mode);
 
-	pci_read_config_dword(pdev, addr1, &reg);
+	pci_read_config_dword(pdev, addr, &reg);
 	reg = (reg & ~mask) | (timing & mask);
-	pci_write_config_dword(pdev, addr1, reg);
+	pci_write_config_dword(pdev, addr, reg);
 }
 /**
- *	hpt370_set_piomode		-	PIO setup
+ *	hpt37x_set_piomode		-	PIO setup
  *	@ap: ATA interface
  *	@adev: device on the interface
  *
  *	Perform PIO mode setup.
  */
 
-static void hpt370_set_piomode(struct ata_port *ap, struct ata_device *adev)
+static void hpt37x_set_piomode(struct ata_port *ap, struct ata_device *adev)
 {
-	hpt370_set_mode(ap, adev, adev->pio_mode);
+	hpt37x_set_mode(ap, adev, adev->pio_mode);
 }
 
 /**
- *	hpt370_set_dmamode		-	DMA timing setup
+ *	hpt37x_set_dmamode		-	DMA timing setup
  *	@ap: ATA interface
  *	@adev: Device being configured
  *
  *	Set up the channel for MWDMA or UDMA modes.
  */
 
-static void hpt370_set_dmamode(struct ata_port *ap, struct ata_device *adev)
+static void hpt37x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 {
-	hpt370_set_mode(ap, adev, adev->dma_mode);
+	hpt37x_set_mode(ap, adev, adev->dma_mode);
 }
 
 /**
- *	hpt370_bmdma_end		-	DMA engine stop
+ *	hpt370_bmdma_stop		-	DMA engine stop
  *	@qc: ATA command
  *
  *	Work around the HPT370 DMA engine.
@@ -499,65 +504,8 @@ static void hpt370_bmdma_stop(struct ata_queued_cmd *qc)
 	ata_bmdma_stop(qc);
 }
 
-static void hpt372_set_mode(struct ata_port *ap, struct ata_device *adev,
-			    u8 mode)
-{
-	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
-	u32 addr1, addr2;
-	u32 reg, timing, mask;
-	u8 fast;
-
-	addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
-	addr2 = 0x51 + 4 * ap->port_no;
-
-	/* Fast interrupt prediction disable, hold off interrupt disable */
-	pci_read_config_byte(pdev, addr2, &fast);
-	fast &= ~0x07;
-	pci_write_config_byte(pdev, addr2, fast);
-
-	/* Determine timing mask and find matching mode entry */
-	if (mode < XFER_MW_DMA_0)
-		mask = 0xcfc3ffff;
-	else if (mode < XFER_UDMA_0)
-		mask = 0x31c001ff;
-	else
-		mask = 0x303c0000;
-
-	timing = hpt37x_find_mode(ap, mode);
-
-	pci_read_config_dword(pdev, addr1, &reg);
-	reg = (reg & ~mask) | (timing & mask);
-	pci_write_config_dword(pdev, addr1, reg);
-}
-
-/**
- *	hpt372_set_piomode		-	PIO setup
- *	@ap: ATA interface
- *	@adev: device on the interface
- *
- *	Perform PIO mode setup.
- */
-
-static void hpt372_set_piomode(struct ata_port *ap, struct ata_device *adev)
-{
-	hpt372_set_mode(ap, adev, adev->pio_mode);
-}
-
 /**
- *	hpt372_set_dmamode		-	DMA timing setup
- *	@ap: ATA interface
- *	@adev: Device being configured
- *
- *	Set up the channel for MWDMA or UDMA modes.
- */
-
-static void hpt372_set_dmamode(struct ata_port *ap, struct ata_device *adev)
-{
-	hpt372_set_mode(ap, adev, adev->dma_mode);
-}
-
-/**
- *	hpt37x_bmdma_end		-	DMA engine stop
+ *	hpt37x_bmdma_stop		-	DMA engine stop
  *	@qc: ATA command
  *
  *	Clean up after the HPT372 and later DMA engine
@@ -578,7 +526,7 @@ static void hpt37x_bmdma_stop(struct ata_queued_cmd *qc)
 }
 
 
-static struct scsi_host_template hpt37x_sht = {
+static const struct scsi_host_template hpt37x_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
@@ -593,9 +541,9 @@ static struct ata_port_operations hpt370_port_ops = {
 
 	.mode_filter	= hpt370_filter,
 	.cable_detect	= hpt37x_cable_detect,
-	.set_piomode	= hpt370_set_piomode,
-	.set_dmamode	= hpt370_set_dmamode,
-	.prereset	= hpt37x_pre_reset,
+	.set_piomode	= hpt37x_set_piomode,
+	.set_dmamode	= hpt37x_set_dmamode,
+	.reset.prereset	= hpt37x_pre_reset,
 };
 
 /*
@@ -608,8 +556,7 @@ static struct ata_port_operations hpt370a_port_ops = {
 };
 
 /*
- *	Configuration for HPT371 and HPT302. Slightly different PIO and DMA
- *	mode setting functionality.
+ *	Configuration for HPT371 and HPT302.
  */
 
 static struct ata_port_operations hpt302_port_ops = {
@@ -618,9 +565,9 @@ static struct ata_port_operations hpt302_port_ops = {
 	.bmdma_stop	= hpt37x_bmdma_stop,
 
 	.cable_detect	= hpt37x_cable_detect,
-	.set_piomode	= hpt372_set_piomode,
-	.set_dmamode	= hpt372_set_dmamode,
-	.prereset	= hpt37x_pre_reset,
+	.set_piomode	= hpt37x_set_piomode,
+	.set_dmamode	= hpt37x_set_dmamode,
+	.reset.prereset	= hpt37x_pre_reset,
 };
 
 /*
@@ -645,21 +592,19 @@ static struct ata_port_operations hpt374_fn1_port_ops = {
 
 /**
  *	hpt37x_clock_slot	-	Turn timing to PC clock entry
- *	@freq: Reported frequency timing
- *	@base: Base timing
+ *	@freq: Reported frequency in MHz
  *
- *	Turn the timing data intoa clock slot (0 for 33, 1 for 40, 2 for 50
+ *	Turn the timing data into a clock slot (0 for 33, 1 for 40, 2 for 50
  *	and 3 for 66Mhz)
  */
 
-static int hpt37x_clock_slot(unsigned int freq, unsigned int base)
+static int hpt37x_clock_slot(unsigned int freq)
 {
-	unsigned int f = (base * freq) / 192;	/* Mhz */
-	if (f < 40)
+	if (freq < 40)
 		return 0;	/* 33Mhz slot */
-	if (f < 45)
+	if (freq < 45)
 		return 1;	/* 40Mhz slot */
-	if (f < 55)
+	if (freq < 55)
 		return 2;	/* 50Mhz slot */
 	return 3;		/* 60Mhz slot */
 }
@@ -699,24 +644,57 @@ static int hpt37x_calibrate_dpll(struct pci_dev *dev)
 	return 0;
 }
 
-static u32 hpt374_read_freq(struct pci_dev *pdev)
+static int hpt37x_pci_clock(struct pci_dev *pdev, unsigned int base)
 {
-	u32 freq;
-	unsigned long io_base = pci_resource_start(pdev, 4);
+	unsigned int freq;
+	u32 fcnt;
 
-	if (PCI_FUNC(pdev->devfn) & 1) {
-		struct pci_dev *pdev_0;
+	/*
+	 * Some devices do not let this value be accessed via PCI space
+	 * according to the old driver. In addition we must use the value
+	 * from FN 0 on the HPT374.
+	 */
+	if (pdev->device == PCI_DEVICE_ID_TTI_HPT374 &&
+	    (PCI_FUNC(pdev->devfn) & 1)) {
+		struct pci_dev *pdev_fn0;
 
-		pdev_0 = pci_get_slot(pdev->bus, pdev->devfn - 1);
-		/* Someone hot plugged the controller on us ? */
-		if (pdev_0 == NULL)
+		pdev_fn0 = pci_get_slot(pdev->bus, pdev->devfn - 1);
+		/* Someone hot plugged the controller on us? */
+		if (!pdev_fn0)
 			return 0;
-		io_base = pci_resource_start(pdev_0, 4);
-		freq = inl(io_base + 0x90);
-		pci_dev_put(pdev_0);
-	} else
-		freq = inl(io_base + 0x90);
-	return freq;
+		fcnt = inl(pci_resource_start(pdev_fn0, 4) + 0x90);
+		pci_dev_put(pdev_fn0);
+	} else	{
+		fcnt = inl(pci_resource_start(pdev, 4) + 0x90);
+	}
+
+	if ((fcnt >> 12) != 0xABCDE) {
+		u32 total = 0;
+		int i;
+		u16 sr;
+
+		dev_warn(&pdev->dev, "BIOS clock data not set\n");
+
+		/* This is the process the HPT371 BIOS is reported to use */
+		for (i = 0; i < 128; i++) {
+			pci_read_config_word(pdev, 0x78, &sr);
+			total += sr & 0x1FF;
+			udelay(15);
+		}
+		fcnt = total / 128;
+	}
+	fcnt &= 0x1FF;
+
+	freq = (fcnt * base) / 192;	/* in MHz */
+
+	/* Clamp to bands */
+	if (freq < 40)
+		return 33;
+	if (freq < 45)
+		return 40;
+	if (freq < 55)
+		return 50;
+	return 66;
 }
 
 /**
@@ -823,7 +801,7 @@ static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 	u8 rev = dev->revision;
 	u8 irqmask;
 	u8 mcr1;
-	u32 freq;
+	unsigned int freq; /* MHz */
 	int prefer_dpll = 1;
 
 	unsigned long iobase = pci_resource_start(dev, 4);
@@ -862,7 +840,8 @@ static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 			chip_table = &hpt372;
 			break;
 		default:
-			pr_err("Unknown HPT366 subtype, please report (%d)\n",
+			dev_err(&dev->dev,
+				"Unknown HPT366 subtype, please report (%d)\n",
 			       rev);
 			return -ENODEV;
 		}
@@ -903,7 +882,8 @@ static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 			*ppi = &info_hpt374_fn1;
 		break;
 	default:
-		pr_err("PCI table is bogus, please report (%d)\n", dev->device);
+		dev_err(&dev->dev, "PCI table is bogus, please report (%d)\n",
+			dev->device);
 		return -ENODEV;
 	}
 	/* Ok so this is a chip we support */
@@ -918,6 +898,20 @@ static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 	pci_write_config_byte(dev, 0x5a, irqmask);
 
 	/*
+	 * HPT371 chips physically have only one channel, the secondary one,
+	 * but the primary channel registers do exist!  Go figure...
+	 * So,  we manually disable the non-existing channel here
+	 * (if the BIOS hasn't done this already).
+	 */
+	if (dev->device == PCI_DEVICE_ID_TTI_HPT371) {
+		u8 mcr1;
+
+		pci_read_config_byte(dev, 0x50, &mcr1);
+		mcr1 &= ~0x04;
+		pci_write_config_byte(dev, 0x50, mcr1);
+	}
+
+	/*
 	 * default to pci clock. make sure MA15/16 are set to output
 	 * to prevent drives having problems with 40-pin cables. Needed
 	 * for some drives such as IBM-DTLA which will not enter ready
@@ -933,42 +927,16 @@ static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 	if (chip_table == &hpt372a)
 		outb(0x0e, iobase + 0x9c);
 
-	/*
-	 * Some devices do not let this value be accessed via PCI space
-	 * according to the old driver. In addition we must use the value
-	 * from FN 0 on the HPT374.
-	 */
-
-	if (chip_table == &hpt374) {
-		freq = hpt374_read_freq(dev);
-		if (freq == 0)
-			return -ENODEV;
-	} else
-		freq = inl(iobase + 0x90);
-
-	if ((freq >> 12) != 0xABCDE) {
-		int i;
-		u8 sr;
-		u32 total = 0;
-
-		pr_warn("BIOS has not set timing clocks\n");
-
-		/* This is the process the HPT371 BIOS is reported to use */
-		for (i = 0; i < 128; i++) {
-			pci_read_config_byte(dev, 0x78, &sr);
-			total += sr & 0x1FF;
-			udelay(15);
-		}
-		freq = total / 128;
-	}
-	freq &= 0x1FF;
+	freq = hpt37x_pci_clock(dev, chip_table->base);
+	if (!freq)
+		return -ENODEV;
 
 	/*
 	 *	Turn the frequency check into a band and then find a timing
 	 *	table to match it.
 	 */
 
-	clock_slot = hpt37x_clock_slot(freq, chip_table->base);
+	clock_slot = hpt37x_clock_slot(freq);
 	if (chip_table->clocks[clock_slot] == NULL || prefer_dpll) {
 		/*
 		 *	We need to try PLL mode instead
@@ -1007,7 +975,7 @@ static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 					       (f_high << 16) | f_low | 0x100);
 		}
 		if (adjust == 8) {
-			pr_err("DPLL did not stabilize!\n");
+			dev_err(&dev->dev, "DPLL did not stabilize!\n");
 			return -ENODEV;
 		}
 		if (dpll == 3)
@@ -1015,7 +983,7 @@ static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 		else
 			private_data = (void *)hpt37x_timings_50;
 
-		pr_info("bus clock %dMHz, using %dMHz DPLL\n",
+		dev_info(&dev->dev, "bus clock %dMHz, using %dMHz DPLL\n",
 			MHz[clock_slot], MHz[dpll]);
 	} else {
 		private_data = (void *)chip_table->clocks[clock_slot];
@@ -1030,7 +998,7 @@ static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 		if (clock_slot < 2 && ppi[0] == &info_hpt370a)
 			ppi[0] = &info_hpt370a_33;
 
-		pr_info("%s using %dMHz bus clock\n",
+		dev_info(&dev->dev, "%s using %dMHz bus clock\n",
 			chip_table->name, MHz[clock_slot]);
 	}
 
diff --git a/drivers/ata/pata_hpt3x2n.c b/drivers/ata/pata_hpt3x2n.c
index 9cb2d50db876..2cc57fcf2c46 100644
--- a/drivers/ata/pata_hpt3x2n.c
+++ b/drivers/ata/pata_hpt3x2n.c
@@ -15,9 +15,6 @@
  * TODO
  *	Work out best PLL policy
  */
-
-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
-
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/pci.h>
@@ -27,10 +24,9 @@
 #include <linux/libata.h>
 
 #define DRV_NAME	"pata_hpt3x2n"
-#define DRV_VERSION	"0.3.15"
+#define DRV_VERSION	"0.3.19"
 
 enum {
-	HPT_PCI_FAST	=	(1 << 31),
 	PCI66		=	(1 << 1),
 	USE_DPLL	=	(1 << 0)
 };
@@ -40,11 +36,6 @@ struct hpt_clock {
 	u32	timing;
 };
 
-struct hpt_chip {
-	const char *name;
-	struct hpt_clock *clocks[3];
-};
-
 /* key for bus clock timings
  * bit
  * 0:3    data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
@@ -122,7 +113,7 @@ static u32 hpt3x2n_find_mode(struct ata_port *ap, int speed)
  *	The Marvell bridge chips used on the HighPoint SATA cards do not seem
  *	to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
  */
-static unsigned long hpt372n_filter(struct ata_device *adev, unsigned long mask)
+static unsigned int hpt372n_filter(struct ata_device *adev, unsigned int mask)
 {
 	if (ata_id_is_sata(adev->id))
 		mask &= ~((0xE << ATA_SHIFT_UDMA) | ATA_MASK_MWDMA);
@@ -171,11 +162,24 @@ static int hpt3x2n_pre_reset(struct ata_link *link, unsigned long deadline)
 {
 	struct ata_port *ap = link->ap;
 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
+	static const struct pci_bits hpt3x2n_enable_bits[] = {
+		{ 0x50, 1, 0x04, 0x04 },
+		{ 0x54, 1, 0x04, 0x04 }
+	};
+	u8 mcr2;
+
+	if (!pci_test_config_bits(pdev, &hpt3x2n_enable_bits[ap->port_no]))
+		return -ENOENT;
 
 	/* Reset the state machine */
 	pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
 	udelay(100);
 
+	/* Fast interrupt prediction disable, hold off interrupt disable */
+	pci_read_config_byte(pdev, 0x51 + 4 * ap->port_no, &mcr2);
+	mcr2 &= ~0x07;
+	pci_write_config_byte(pdev, 0x51 + 4 * ap->port_no, mcr2);
+
 	return ata_sff_prereset(link, deadline);
 }
 
@@ -183,17 +187,8 @@ static void hpt3x2n_set_mode(struct ata_port *ap, struct ata_device *adev,
 			     u8 mode)
 {
 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
-	u32 addr1, addr2;
+	int addr = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
 	u32 reg, timing, mask;
-	u8 fast;
-
-	addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
-	addr2 = 0x51 + 4 * ap->port_no;
-
-	/* Fast interrupt prediction disable, hold off interrupt disable */
-	pci_read_config_byte(pdev, addr2, &fast);
-	fast &= ~0x07;
-	pci_write_config_byte(pdev, addr2, fast);
 
 	/* Determine timing mask and find matching mode entry */
 	if (mode < XFER_MW_DMA_0)
@@ -205,9 +200,9 @@ static void hpt3x2n_set_mode(struct ata_port *ap, struct ata_device *adev,
 
 	timing = hpt3x2n_find_mode(ap, mode);
 
-	pci_read_config_dword(pdev, addr1, &reg);
+	pci_read_config_dword(pdev, addr, &reg);
 	reg = (reg & ~mask) | (timing & mask);
-	pci_write_config_dword(pdev, addr1, reg);
+	pci_write_config_dword(pdev, addr, reg);
 }
 
 /**
@@ -237,7 +232,7 @@ static void hpt3x2n_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 }
 
 /**
- *	hpt3x2n_bmdma_end		-	DMA engine stop
+ *	hpt3x2n_bmdma_stop		-	DMA engine stop
  *	@qc: ATA command
  *
  *	Clean up after the HPT3x2n and later DMA engine
@@ -247,7 +242,7 @@ static void hpt3x2n_bmdma_stop(struct ata_queued_cmd *qc)
 {
 	struct ata_port *ap = qc->ap;
 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
-	int mscreg = 0x50 + 2 * ap->port_no;
+	int mscreg = 0x50 + 4 * ap->port_no;
 	u8 bwsr_stat, msc_stat;
 
 	pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
@@ -342,7 +337,7 @@ static unsigned int hpt3x2n_qc_issue(struct ata_queued_cmd *qc)
 	return ata_bmdma_qc_issue(qc);
 }
 
-static struct scsi_host_template hpt3x2n_sht = {
+static const struct scsi_host_template hpt3x2n_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
@@ -361,7 +356,7 @@ static struct ata_port_operations hpt3xxn_port_ops = {
 	.cable_detect	= hpt3x2n_cable_detect,
 	.set_piomode	= hpt3x2n_set_piomode,
 	.set_dmamode	= hpt3x2n_set_dmamode,
-	.prereset	= hpt3x2n_pre_reset,
+	.reset.prereset	= hpt3x2n_pre_reset,
 };
 
 /*
@@ -408,19 +403,22 @@ static int hpt3xn_calibrate_dpll(struct pci_dev *dev)
 	return 0;
 }
 
-static int hpt3x2n_pci_clock(struct pci_dev *pdev)
+static int hpt3x2n_pci_clock(struct pci_dev *pdev, unsigned int base)
 {
-	unsigned long freq;
+	unsigned int freq;
 	u32 fcnt;
-	unsigned long iobase = pci_resource_start(pdev, 4);
 
-	fcnt = inl(iobase + 0x90);	/* Not PCI readable for some chips */
+	/*
+	 * Some devices do not let this value be accessed via PCI space
+	 * according to the old driver.
+	 */
+	fcnt = inl(pci_resource_start(pdev, 4) + 0x90);
 	if ((fcnt >> 12) != 0xABCDE) {
+		u32 total = 0;
 		int i;
 		u16 sr;
-		u32 total = 0;
 
-		pr_warn("BIOS clock data not set\n");
+		dev_warn(&pdev->dev, "BIOS clock data not set\n");
 
 		/* This is the process the HPT371 BIOS is reported to use */
 		for (i = 0; i < 128; i++) {
@@ -432,7 +430,7 @@ static int hpt3x2n_pci_clock(struct pci_dev *pdev)
 	}
 	fcnt &= 0x1FF;
 
-	freq = (fcnt * 77) / 192;
+	freq = (fcnt * base) / 192;	/* in MHz */
 
 	/* Clamp to bands */
 	if (freq < 40)
@@ -530,7 +528,8 @@ hpt372n:
 		ppi[0] = &info_hpt372n;
 		break;
 	default:
-		pr_err("PCI table is bogus, please report (%d)\n", dev->device);
+		dev_err(&dev->dev,"PCI table is bogus, please report (%d)\n",
+			dev->device);
 		return -ENODEV;
 	}
 
@@ -563,7 +562,7 @@ hpt372n:
 	 * 50 for UDMA100. Right now we always use 66
 	 */
 
-	pci_mhz = hpt3x2n_pci_clock(dev);
+	pci_mhz = hpt3x2n_pci_clock(dev, 77);
 
 	f_low = (pci_mhz * 48) / 66;	/* PCI Mhz for 66Mhz DPLL */
 	f_high = f_low + 2;		/* Tolerance */
@@ -579,11 +578,11 @@ hpt372n:
 		pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low);
 	}
 	if (adjust == 8) {
-		pr_err("DPLL did not stabilize!\n");
+		dev_err(&dev->dev, "DPLL did not stabilize!\n");
 		return -ENODEV;
 	}
 
-	pr_info("bus clock %dMHz, using 66MHz DPLL\n", pci_mhz);
+	dev_info(&dev->dev, "bus clock %dMHz, using 66MHz DPLL\n", pci_mhz);
 
 	/*
 	 * Set our private data up. We only need a few flags
diff --git a/drivers/ata/pata_hpt3x3.c b/drivers/ata/pata_hpt3x3.c
index 83974d5eb387..d65c586b5ad0 100644
--- a/drivers/ata/pata_hpt3x3.c
+++ b/drivers/ata/pata_hpt3x3.c
@@ -136,7 +136,7 @@ static int hpt3x3_atapi_dma(struct ata_queued_cmd *qc)
 
 #endif /* CONFIG_PATA_HPT3X3_DMA */
 
-static struct scsi_host_template hpt3x3_sht = {
+static const struct scsi_host_template hpt3x3_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
diff --git a/drivers/ata/pata_icside.c b/drivers/ata/pata_icside.c
index 08543aeb0093..70f056e47e6b 100644
--- a/drivers/ata/pata_icside.c
+++ b/drivers/ata/pata_icside.c
@@ -202,14 +202,19 @@ static void pata_icside_set_dmamode(struct ata_port *ap, struct ata_device *adev
 	 * Choose the IOMD cycle timing which ensure that the interface
 	 * satisfies the measured active, recovery and cycle times.
 	 */
-	if (t.active <= 50 && t.recover <= 375 && t.cycle <= 425)
-		iomd_type = 'D', cycle = 187;
-	else if (t.active <= 125 && t.recover <= 375 && t.cycle <= 500)
-		iomd_type = 'C', cycle = 250;
-	else if (t.active <= 200 && t.recover <= 550 && t.cycle <= 750)
-		iomd_type = 'B', cycle = 437;
-	else
-		iomd_type = 'A', cycle = 562;
+	if (t.active <= 50 && t.recover <= 375 && t.cycle <= 425) {
+		iomd_type = 'D';
+		cycle = 187;
+	} else if (t.active <= 125 && t.recover <= 375 && t.cycle <= 500) {
+		iomd_type = 'C';
+		cycle = 250;
+	} else if (t.active <= 200 && t.recover <= 550 && t.cycle <= 750) {
+		iomd_type = 'B';
+		cycle = 437;
+	} else {
+		iomd_type = 'A';
+		cycle = 562;
+	}
 
 	ata_dev_info(adev, "timings: act %dns rec %dns cyc %dns (%c)\n",
 		     t.active, t.recover, t.cycle, iomd_type);
@@ -293,7 +298,7 @@ static int icside_dma_init(struct pata_icside_info *info)
 }
 
 
-static struct scsi_host_template pata_icside_sht = {
+static const struct scsi_host_template pata_icside_sht = {
 	ATA_BASE_SHT(DRV_NAME),
 	.sg_tablesize		= SG_MAX_SEGMENTS,
 	.dma_boundary		= IOMD_DMA_BOUNDARY,
@@ -323,8 +328,6 @@ static void pata_icside_postreset(struct ata_link *link, unsigned int *classes)
 
 static struct ata_port_operations pata_icside_port_ops = {
 	.inherits		= &ata_bmdma_port_ops,
-	/* no need to build any PRD tables for DMA */
-	.qc_prep		= ata_noop_qc_prep,
 	.sff_data_xfer		= ata_sff_data_xfer32,
 	.bmdma_setup		= pata_icside_bmdma_setup,
 	.bmdma_start		= pata_icside_bmdma_start,
@@ -333,7 +336,7 @@ static struct ata_port_operations pata_icside_port_ops = {
 
 	.cable_detect		= ata_cable_40wire,
 	.set_dmamode		= pata_icside_set_dmamode,
-	.postreset		= pata_icside_postreset,
+	.reset.postreset	= pata_icside_postreset,
 
 	.port_start		= ATA_OP_NULL,	/* don't need PRD table */
 };
diff --git a/drivers/ata/pata_imx.c b/drivers/ata/pata_imx.c
index 2e538726802b..b37682b0578f 100644
--- a/drivers/ata/pata_imx.c
+++ b/drivers/ata/pata_imx.c
@@ -97,7 +97,7 @@ static void pata_imx_set_piomode(struct ata_port *ap, struct ata_device *adev)
 	__raw_writel(val, priv->host_regs + PATA_IMX_ATA_CONTROL);
 }
 
-static struct scsi_host_template pata_imx_sht = {
+static const struct scsi_host_template pata_imx_sht = {
 	ATA_PIO_SHT(DRV_NAME),
 };
 
@@ -141,21 +141,15 @@ static int pata_imx_probe(struct platform_device *pdev)
 	if (!priv)
 		return -ENOMEM;
 
-	priv->clk = devm_clk_get(&pdev->dev, NULL);
+	priv->clk = devm_clk_get_enabled(&pdev->dev, NULL);
 	if (IS_ERR(priv->clk)) {
-		dev_err(&pdev->dev, "Failed to get clock\n");
+		dev_err(&pdev->dev, "Failed to get and enable clock\n");
 		return PTR_ERR(priv->clk);
 	}
 
-	ret = clk_prepare_enable(priv->clk);
-	if (ret)
-		return ret;
-
 	host = ata_host_alloc(&pdev->dev, 1);
-	if (!host) {
-		ret = -ENOMEM;
-		goto err;
-	}
+	if (!host)
+		return -ENOMEM;
 
 	host->private_data = priv;
 	ap = host->ports[0];
@@ -164,12 +158,9 @@ static int pata_imx_probe(struct platform_device *pdev)
 	ap->pio_mask = ATA_PIO4;
 	ap->flags |= ATA_FLAG_SLAVE_POSS;
 
-	io_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	priv->host_regs = devm_ioremap_resource(&pdev->dev, io_res);
-	if (IS_ERR(priv->host_regs)) {
-		ret = PTR_ERR(priv->host_regs);
-		goto err;
-	}
+	priv->host_regs = devm_platform_get_and_ioremap_resource(pdev, 0, &io_res);
+	if (IS_ERR(priv->host_regs))
+		return PTR_ERR(priv->host_regs);
 
 	ap->ioaddr.cmd_addr = priv->host_regs + PATA_IMX_DRIVE_DATA;
 	ap->ioaddr.ctl_addr = priv->host_regs + PATA_IMX_DRIVE_CONTROL;
@@ -195,16 +186,12 @@ static int pata_imx_probe(struct platform_device *pdev)
 				&pata_imx_sht);
 
 	if (ret)
-		goto err;
+		return ret;
 
 	return 0;
-err:
-	clk_disable_unprepare(priv->clk);
-
-	return ret;
 }
 
-static int pata_imx_remove(struct platform_device *pdev)
+static void pata_imx_remove(struct platform_device *pdev)
 {
 	struct ata_host *host = platform_get_drvdata(pdev);
 	struct pata_imx_priv *priv = host->private_data;
@@ -212,10 +199,6 @@ static int pata_imx_remove(struct platform_device *pdev)
 	ata_host_detach(host);
 
 	__raw_writel(0, priv->host_regs + PATA_IMX_ATA_INT_EN);
-
-	clk_disable_unprepare(priv->clk);
-
-	return 0;
 }
 
 #ifdef CONFIG_PM_SLEEP
@@ -223,17 +206,14 @@ static int pata_imx_suspend(struct device *dev)
 {
 	struct ata_host *host = dev_get_drvdata(dev);
 	struct pata_imx_priv *priv = host->private_data;
-	int ret;
 
-	ret = ata_host_suspend(host, PMSG_SUSPEND);
-	if (!ret) {
-		__raw_writel(0, priv->host_regs + PATA_IMX_ATA_INT_EN);
-		priv->ata_ctl =
-			__raw_readl(priv->host_regs + PATA_IMX_ATA_CONTROL);
-		clk_disable_unprepare(priv->clk);
-	}
+	ata_host_suspend(host, PMSG_SUSPEND);
 
-	return ret;
+	__raw_writel(0, priv->host_regs + PATA_IMX_ATA_INT_EN);
+	priv->ata_ctl = __raw_readl(priv->host_regs + PATA_IMX_ATA_CONTROL);
+	clk_disable_unprepare(priv->clk);
+
+	return 0;
 }
 
 static int pata_imx_resume(struct device *dev)
diff --git a/drivers/ata/pata_isapnp.c b/drivers/ata/pata_isapnp.c
index 43bb224430d3..0f77e0424066 100644
--- a/drivers/ata/pata_isapnp.c
+++ b/drivers/ata/pata_isapnp.c
@@ -20,7 +20,7 @@
 #define DRV_NAME "pata_isapnp"
 #define DRV_VERSION "0.2.5"
 
-static struct scsi_host_template isapnp_sht = {
+static const struct scsi_host_template isapnp_sht = {
 	ATA_PIO_SHT(DRV_NAME),
 };
 
@@ -82,6 +82,9 @@ static int isapnp_init_one(struct pnp_dev *idev, const struct pnp_device_id *dev
 	if (pnp_port_valid(idev, 1)) {
 		ctl_addr = devm_ioport_map(&idev->dev,
 					   pnp_port_start(idev, 1), 1);
+		if (!ctl_addr)
+			return -ENOMEM;
+
 		ap->ioaddr.altstatus_addr = ctl_addr;
 		ap->ioaddr.ctl_addr = ctl_addr;
 		ap->ops = &isapnp_port_ops;
diff --git a/drivers/ata/pata_it8213.c b/drivers/ata/pata_it8213.c
index 8a3e8778163c..a6f2cfc1602e 100644
--- a/drivers/ata/pata_it8213.c
+++ b/drivers/ata/pata_it8213.c
@@ -81,7 +81,7 @@ static void it8213_set_piomode (struct ata_port *ap, struct ata_device *adev)
 	int control = 0;
 
 	/*
-	 *	See Intel Document 298600-004 for the timing programing rules
+	 *	See Intel Document 298600-004 for the timing programming rules
 	 *	for PIIX/ICH. The 8213 is a clone so very similar
 	 */
 
@@ -228,7 +228,7 @@ static void it8213_set_dmamode (struct ata_port *ap, struct ata_device *adev)
 	pci_write_config_byte(dev, 0x48, udma_enable);
 }
 
-static struct scsi_host_template it8213_sht = {
+static const struct scsi_host_template it8213_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
@@ -238,7 +238,7 @@ static struct ata_port_operations it8213_ops = {
 	.cable_detect		= it8213_cable_detect,
 	.set_piomode		= it8213_set_piomode,
 	.set_dmamode		= it8213_set_dmamode,
-	.prereset		= it8213_pre_reset,
+	.reset.prereset		= it8213_pre_reset,
 };
 
 
diff --git a/drivers/ata/pata_it821x.c b/drivers/ata/pata_it821x.c
index 9bac79edbc2c..fc762dcc61bf 100644
--- a/drivers/ata/pata_it821x.c
+++ b/drivers/ata/pata_it821x.c
@@ -75,6 +75,7 @@
 #include <linux/blkdev.h>
 #include <linux/delay.h>
 #include <linux/slab.h>
+#include <linux/string.h>
 #include <scsi/scsi_host.h>
 #include <linux/libata.h>
 
@@ -334,7 +335,7 @@ static void it821x_passthru_set_dmamode(struct ata_port *ap, struct ata_device *
 }
 
 /**
- *	it821x_passthru_dma_start	-	DMA start callback
+ *	it821x_passthru_bmdma_start	-	DMA start callback
  *	@qc: Command in progress
  *
  *	Usually drivers set the DMA timing at the point the set_dmamode call
@@ -357,7 +358,7 @@ static void it821x_passthru_bmdma_start(struct ata_queued_cmd *qc)
 }
 
 /**
- *	it821x_passthru_dma_stop	-	DMA stop callback
+ *	it821x_passthru_bmdma_stop	-	DMA stop callback
  *	@qc: ATA command
  *
  *	We loaded new timings in dma_start, as a result we need to restore
@@ -431,7 +432,8 @@ static unsigned int it821x_smart_qc_issue(struct ata_queued_cmd *qc)
 		case ATA_CMD_SET_FEATURES:
 			return ata_bmdma_qc_issue(qc);
 	}
-	printk(KERN_DEBUG "it821x: can't process command 0x%02X\n", qc->tf.command);
+	ata_dev_dbg(qc->dev, "it821x: can't process command 0x%02X\n",
+		    qc->tf.command);
 	return AC_ERR_DEV;
 }
 
@@ -507,18 +509,20 @@ static void it821x_dev_config(struct ata_device *adev)
 
 	if (strstr(model_num, "Integrated Technology Express")) {
 		/* RAID mode */
-		ata_dev_info(adev, "%sRAID%d volume",
-			     adev->id[147] ? "Bootable " : "",
-			     adev->id[129]);
-		if (adev->id[129] != 1)
-			pr_cont("(%dK stripe)", adev->id[146]);
-		pr_cont("\n");
+		if (adev->id[129] == 1)
+			ata_dev_info(adev, "%sRAID%d volume\n",
+				     adev->id[147] ? "Bootable " : "",
+				     adev->id[129]);
+		else
+			ata_dev_info(adev, "%sRAID%d volume (%dK stripe)\n",
+				     adev->id[147] ? "Bootable " : "",
+				     adev->id[129], adev->id[146]);
 	}
 	/* This is a controller firmware triggered funny, don't
 	   report the drive faulty! */
-	adev->horkage &= ~ATA_HORKAGE_DIAGNOSTIC;
+	adev->quirks &= ~ATA_QUIRK_DIAGNOSTIC;
 	/* No HPA in 'smart' mode */
-	adev->horkage |= ATA_HORKAGE_BROKEN_HPA;
+	adev->quirks |= ATA_QUIRK_BROKEN_HPA;
 }
 
 /**
@@ -534,7 +538,7 @@ static void it821x_dev_config(struct ata_device *adev)
  */
 
 static unsigned int it821x_read_id(struct ata_device *adev,
-					struct ata_taskfile *tf, u16 *id)
+				   struct ata_taskfile *tf, __le16 *id)
 {
 	unsigned int err_mask;
 	unsigned char model_num[ATA_ID_PROD_LEN + 1];
@@ -542,21 +546,20 @@ static unsigned int it821x_read_id(struct ata_device *adev,
 	err_mask = ata_do_dev_read_id(adev, tf, id);
 	if (err_mask)
 		return err_mask;
-	ata_id_c_string(id, model_num, ATA_ID_PROD, sizeof(model_num));
+	ata_id_c_string((u16 *)id, model_num, ATA_ID_PROD, sizeof(model_num));
 
-	id[83] &= ~(1 << 12);	/* Cache flush is firmware handled */
-	id[83] &= ~(1 << 13);	/* Ditto for LBA48 flushes */
-	id[84] &= ~(1 << 6);	/* No FUA */
-	id[85] &= ~(1 << 10);	/* No HPA */
-	id[76] = 0;		/* No NCQ/AN etc */
+	id[83] &= cpu_to_le16(~(1 << 12)); /* Cache flush is firmware handled */
+	id[84] &= cpu_to_le16(~(1 << 6));  /* No FUA */
+	id[85] &= cpu_to_le16(~(1 << 10)); /* No HPA */
+	id[76] = 0;			   /* No NCQ/AN etc */
 
 	if (strstr(model_num, "Integrated Technology Express")) {
 		/* Set feature bits the firmware neglects */
-		id[49] |= 0x0300;	/* LBA, DMA */
-		id[83] &= 0x7FFF;
-		id[83] |= 0x4400;	/* Word 83 is valid and LBA48 */
-		id[86] |= 0x0400;	/* LBA48 on */
-		id[ATA_ID_MAJOR_VER] |= 0x1F;
+		id[49] |= cpu_to_le16(0x0300);	/* LBA, DMA */
+		id[83] &= cpu_to_le16(0x7FFF);
+		id[83] |= cpu_to_le16(0x4400);	/* Word 83 is valid and LBA48 */
+		id[86] |= cpu_to_le16(0x0400);	/* LBA48 on */
+		id[ATA_ID_MAJOR_VER] |= cpu_to_le16(0x1F);
 		/* Clear the serial number because it's different each boot
 		   which breaks validation on resume */
 		memset(&id[ATA_ID_SERNO], 0x20, ATA_ID_SERNO_LEN);
@@ -593,6 +596,7 @@ static int it821x_check_atapi_dma(struct ata_queued_cmd *qc)
 
 /**
  *	it821x_display_disk	-	display disk setup
+ *	@ap: ATA port
  *	@n: Device number
  *	@buf: Buffer block from firmware
  *
@@ -600,7 +604,7 @@ static int it821x_check_atapi_dma(struct ata_queued_cmd *qc)
  *	by the firmware.
  */
 
-static void it821x_display_disk(int n, u8 *buf)
+static void it821x_display_disk(struct ata_port *ap, int n, u8 *buf)
 {
 	unsigned char id[41];
 	int mode = 0;
@@ -629,17 +633,17 @@ static void it821x_display_disk(int n, u8 *buf)
 		cbl = "";
 
 	if (mode)
-		snprintf(mbuf, 8, "%5s%d", mtype, mode - 1);
+		snprintf(mbuf, sizeof(mbuf), "%5s%d", mtype, mode - 1);
 	else
-		strcpy(mbuf, "PIO");
+		strscpy(mbuf, "PIO");
 	if (buf[52] == 4)
-		printk(KERN_INFO "%d: %-6s %-8s          %s %s\n",
+		ata_port_info(ap, "%d: %-6s %-8s          %s %s\n",
 				n, mbuf, types[buf[52]], id, cbl);
 	else
-		printk(KERN_INFO "%d: %-6s %-8s Volume: %1d %s %s\n",
+		ata_port_info(ap, "%d: %-6s %-8s Volume: %1d %s %s\n",
 				n, mbuf, types[buf[52]], buf[53], id, cbl);
 	if (buf[125] < 100)
-		printk(KERN_INFO "%d: Rebuilding: %d%%\n", n, buf[125]);
+		ata_port_info(ap, "%d: Rebuilding: %d%%\n", n, buf[125]);
 }
 
 /**
@@ -676,7 +680,7 @@ static u8 *it821x_firmware_command(struct ata_port *ap, u8 cmd, int len)
 		status = ioread8(ap->ioaddr.status_addr);
 		if (status & ATA_ERR) {
 			kfree(buf);
-			printk(KERN_ERR "it821x_firmware_command: rejected\n");
+			ata_port_err(ap, "%s: rejected\n", __func__);
 			return NULL;
 		}
 		if (status & ATA_DRQ) {
@@ -686,7 +690,7 @@ static u8 *it821x_firmware_command(struct ata_port *ap, u8 cmd, int len)
 		usleep_range(500, 1000);
 	}
 	kfree(buf);
-	printk(KERN_ERR "it821x_firmware_command: timeout\n");
+	ata_port_err(ap, "%s: timeout\n", __func__);
 	return NULL;
 }
 
@@ -709,13 +713,13 @@ static void it821x_probe_firmware(struct ata_port *ap)
 	buf = it821x_firmware_command(ap, 0xFA, 512);
 
 	if (buf != NULL) {
-		printk(KERN_INFO "pata_it821x: Firmware %02X/%02X/%02X%02X\n",
+		ata_port_info(ap, "pata_it821x: Firmware %02X/%02X/%02X%02X\n",
 				buf[505],
 				buf[506],
 				buf[507],
 				buf[508]);
 		for (i = 0; i < 4; i++)
- 			it821x_display_disk(i, buf + 128 * i);
+			it821x_display_disk(ap, i, buf + 128 * i);
 		kfree(buf);
 	}
 }
@@ -771,7 +775,8 @@ static int it821x_port_start(struct ata_port *ap)
 		itdev->timing10 = 1;
 		/* Need to disable ATAPI DMA for this case */
 		if (!itdev->smart)
-			printk(KERN_WARNING DRV_NAME": Revision 0x10, workarounds activated.\n");
+			dev_warn(&pdev->dev,
+				 "Revision 0x10, workarounds activated.\n");
 	}
 
 	return 0;
@@ -796,7 +801,7 @@ static int it821x_rdc_cable(struct ata_port *ap)
 	return ATA_CBL_PATA80;
 }
 
-static struct scsi_host_template it821x_sht = {
+static const struct scsi_host_template it821x_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
@@ -919,14 +924,14 @@ static int it821x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
 	} else {
 		/* Force the card into bypass mode if so requested */
 		if (it8212_noraid) {
-			printk(KERN_INFO DRV_NAME ": forcing bypass mode.\n");
+			dev_info(&pdev->dev, "forcing bypass mode.\n");
 			it821x_disable_raid(pdev);
 		}
 		pci_read_config_byte(pdev, 0x50, &conf);
 		conf &= 1;
 
-		printk(KERN_INFO DRV_NAME": controller in %s mode.\n",
-								mode[conf]);
+		dev_info(&pdev->dev, "controller in %s mode.\n", mode[conf]);
+
 		if (conf == 0)
 			ppi[0] = &info_passthru;
 		else
diff --git a/drivers/ata/pata_ixp4xx_cf.c b/drivers/ata/pata_ixp4xx_cf.c
index d1644a8ef9fa..80f6a91acf6f 100644
--- a/drivers/ata/pata_ixp4xx_cf.c
+++ b/drivers/ata/pata_ixp4xx_cf.c
@@ -13,44 +13,135 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
 #include <linux/module.h>
 #include <linux/libata.h>
 #include <linux/irq.h>
+#include <linux/of.h>
 #include <linux/platform_device.h>
+#include <linux/regmap.h>
 #include <scsi/scsi_host.h>
 
 #define DRV_NAME	"pata_ixp4xx_cf"
-#define DRV_VERSION	"0.2"
+#define DRV_VERSION	"1.0"
 
-static int ixp4xx_set_mode(struct ata_link *link, struct ata_device **error)
+struct ixp4xx_pata {
+	struct ata_host *host;
+	struct regmap *rmap;
+	u32 cmd_csreg;
+	void __iomem *cmd;
+	void __iomem *ctl;
+};
+
+#define IXP4XX_EXP_TIMING_STRIDE	0x04
+/* The timings for the chipselect is in bits 29..16 */
+#define IXP4XX_EXP_T1_T5_MASK	GENMASK(29, 16)
+#define IXP4XX_EXP_PIO_0_8	0x0a470000
+#define IXP4XX_EXP_PIO_1_8	0x06430000
+#define IXP4XX_EXP_PIO_2_8	0x02410000
+#define IXP4XX_EXP_PIO_3_8	0x00820000
+#define IXP4XX_EXP_PIO_4_8	0x00400000
+#define IXP4XX_EXP_PIO_0_16	0x29640000
+#define IXP4XX_EXP_PIO_1_16	0x05030000
+#define IXP4XX_EXP_PIO_2_16	0x00b20000
+#define IXP4XX_EXP_PIO_3_16	0x00820000
+#define IXP4XX_EXP_PIO_4_16	0x00400000
+#define IXP4XX_EXP_BW_MASK	(BIT(6)|BIT(0))
+#define IXP4XX_EXP_BYTE_RD16	BIT(6) /* Byte reads on half-word devices */
+#define IXP4XX_EXP_BYTE_EN	BIT(0) /* Use 8bit data bus if set */
+
+static void ixp4xx_set_8bit_timing(struct ixp4xx_pata *ixpp, u8 pio_mode)
+{
+	switch (pio_mode) {
+	case XFER_PIO_0:
+		regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
+				   IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_0_8);
+		break;
+	case XFER_PIO_1:
+		regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
+				   IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_1_8);
+		break;
+	case XFER_PIO_2:
+		regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
+				   IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_2_8);
+		break;
+	case XFER_PIO_3:
+		regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
+				   IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_3_8);
+		break;
+	case XFER_PIO_4:
+		regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
+				   IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_4_8);
+		break;
+	default:
+		break;
+	}
+	regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
+			   IXP4XX_EXP_BW_MASK, IXP4XX_EXP_BYTE_RD16|IXP4XX_EXP_BYTE_EN);
+}
+
+static void ixp4xx_set_16bit_timing(struct ixp4xx_pata *ixpp, u8 pio_mode)
 {
-	struct ata_device *dev;
-
-	ata_for_each_dev(dev, link, ENABLED) {
-		ata_dev_info(dev, "configured for PIO0\n");
-		dev->pio_mode = XFER_PIO_0;
-		dev->xfer_mode = XFER_PIO_0;
-		dev->xfer_shift = ATA_SHIFT_PIO;
-		dev->flags |= ATA_DFLAG_PIO;
+	switch (pio_mode){
+	case XFER_PIO_0:
+		regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
+				   IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_0_16);
+		break;
+	case XFER_PIO_1:
+		regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
+				   IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_1_16);
+		break;
+	case XFER_PIO_2:
+		regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
+				   IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_2_16);
+		break;
+	case XFER_PIO_3:
+		regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
+				   IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_3_16);
+		break;
+	case XFER_PIO_4:
+		regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
+				   IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_4_16);
+		break;
+	default:
+		break;
 	}
-	return 0;
+	regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
+			   IXP4XX_EXP_BW_MASK, IXP4XX_EXP_BYTE_RD16);
 }
 
+/* This sets up the timing on the chipselect CMD accordingly */
+static void ixp4xx_set_piomode(struct ata_port *ap, struct ata_device *adev)
+{
+	struct ixp4xx_pata *ixpp = ap->host->private_data;
+
+	ata_dev_info(adev, "configured for PIO%d 8bit\n",
+		       adev->pio_mode - XFER_PIO_0);
+	ixp4xx_set_8bit_timing(ixpp, adev->pio_mode);
+}
+
+
 static unsigned int ixp4xx_mmio_data_xfer(struct ata_queued_cmd *qc,
-				unsigned char *buf, unsigned int buflen, int rw)
+					  unsigned char *buf, unsigned int buflen, int rw)
 {
 	unsigned int i;
 	unsigned int words = buflen >> 1;
 	u16 *buf16 = (u16 *) buf;
+	struct ata_device *adev = qc->dev;
 	struct ata_port *ap = qc->dev->link->ap;
 	void __iomem *mmio = ap->ioaddr.data_addr;
-	struct ixp4xx_pata_data *data = dev_get_platdata(ap->host->dev);
+	struct ixp4xx_pata *ixpp = ap->host->private_data;
+	unsigned long flags;
+
+	ata_dev_dbg(adev, "%s %d bytes\n", (rw == READ) ? "READ" : "WRITE",
+		    buflen);
+	spin_lock_irqsave(ap->lock, flags);
 
 	/* set the expansion bus in 16bit mode and restore
 	 * 8 bit mode after the transaction.
 	 */
-	*data->cs0_cfg &= ~(0x01);
-	udelay(100);
+	ixp4xx_set_16bit_timing(ixpp, adev->pio_mode);
+	udelay(5);
 
 	/* Transfer multiple of 2 bytes */
 	if (rw == READ)
@@ -75,13 +166,15 @@ static unsigned int ixp4xx_mmio_data_xfer(struct ata_queued_cmd *qc,
 		words++;
 	}
 
-	udelay(100);
-	*data->cs0_cfg |= 0x01;
+	ixp4xx_set_8bit_timing(ixpp, adev->pio_mode);
+	udelay(5);
+
+	spin_unlock_irqrestore(ap->lock, flags);
 
 	return words << 1;
 }
 
-static struct scsi_host_template ixp4xx_sht = {
+static const struct scsi_host_template ixp4xx_sht = {
 	ATA_PIO_SHT(DRV_NAME),
 };
 
@@ -89,106 +182,120 @@ static struct ata_port_operations ixp4xx_port_ops = {
 	.inherits		= &ata_sff_port_ops,
 	.sff_data_xfer		= ixp4xx_mmio_data_xfer,
 	.cable_detect		= ata_cable_40wire,
-	.set_mode		= ixp4xx_set_mode,
+	.set_piomode		= ixp4xx_set_piomode,
+};
+
+static struct ata_port_info ixp4xx_port_info = {
+	.flags		= ATA_FLAG_NO_ATAPI,
+	.pio_mask	= ATA_PIO4,
+	.port_ops	= &ixp4xx_port_ops,
 };
 
 static void ixp4xx_setup_port(struct ata_port *ap,
-			      struct ixp4xx_pata_data *data,
-			      unsigned long raw_cs0, unsigned long raw_cs1)
+			      struct ixp4xx_pata *ixpp,
+			      unsigned long raw_cmd, unsigned long raw_ctl)
 {
 	struct ata_ioports *ioaddr = &ap->ioaddr;
-	unsigned long raw_cmd = raw_cs0;
-	unsigned long raw_ctl = raw_cs1 + 0x06;
 
-	ioaddr->cmd_addr	= data->cs0;
-	ioaddr->altstatus_addr	= data->cs1 + 0x06;
-	ioaddr->ctl_addr	= data->cs1 + 0x06;
+	raw_ctl += 0x06;
+	ioaddr->cmd_addr	= ixpp->cmd;
+	ioaddr->altstatus_addr	= ixpp->ctl + 0x06;
+	ioaddr->ctl_addr	= ixpp->ctl + 0x06;
 
 	ata_sff_std_ports(ioaddr);
 
-#ifndef __ARMEB__
-
-	/* adjust the addresses to handle the address swizzling of the
-	 * ixp4xx in little endian mode.
-	 */
-
-	*(unsigned long *)&ioaddr->data_addr		^= 0x02;
-	*(unsigned long *)&ioaddr->cmd_addr		^= 0x03;
-	*(unsigned long *)&ioaddr->altstatus_addr	^= 0x03;
-	*(unsigned long *)&ioaddr->ctl_addr		^= 0x03;
-	*(unsigned long *)&ioaddr->error_addr		^= 0x03;
-	*(unsigned long *)&ioaddr->feature_addr		^= 0x03;
-	*(unsigned long *)&ioaddr->nsect_addr		^= 0x03;
-	*(unsigned long *)&ioaddr->lbal_addr		^= 0x03;
-	*(unsigned long *)&ioaddr->lbam_addr		^= 0x03;
-	*(unsigned long *)&ioaddr->lbah_addr		^= 0x03;
-	*(unsigned long *)&ioaddr->device_addr		^= 0x03;
-	*(unsigned long *)&ioaddr->status_addr		^= 0x03;
-	*(unsigned long *)&ioaddr->command_addr		^= 0x03;
-
-	raw_cmd ^= 0x03;
-	raw_ctl ^= 0x03;
-#endif
+	if (!IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) {
+		/* adjust the addresses to handle the address swizzling of the
+		 * ixp4xx in little endian mode.
+		 */
+
+		*(unsigned long *)&ioaddr->data_addr		^= 0x02;
+		*(unsigned long *)&ioaddr->cmd_addr		^= 0x03;
+		*(unsigned long *)&ioaddr->altstatus_addr	^= 0x03;
+		*(unsigned long *)&ioaddr->ctl_addr		^= 0x03;
+		*(unsigned long *)&ioaddr->error_addr		^= 0x03;
+		*(unsigned long *)&ioaddr->feature_addr		^= 0x03;
+		*(unsigned long *)&ioaddr->nsect_addr		^= 0x03;
+		*(unsigned long *)&ioaddr->lbal_addr		^= 0x03;
+		*(unsigned long *)&ioaddr->lbam_addr		^= 0x03;
+		*(unsigned long *)&ioaddr->lbah_addr		^= 0x03;
+		*(unsigned long *)&ioaddr->device_addr		^= 0x03;
+		*(unsigned long *)&ioaddr->status_addr		^= 0x03;
+		*(unsigned long *)&ioaddr->command_addr		^= 0x03;
+
+		raw_cmd ^= 0x03;
+		raw_ctl ^= 0x03;
+	}
 
 	ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", raw_cmd, raw_ctl);
 }
 
 static int ixp4xx_pata_probe(struct platform_device *pdev)
 {
-	unsigned int irq;
-	struct resource *cs0, *cs1;
-	struct ata_host *host;
-	struct ata_port *ap;
-	struct ixp4xx_pata_data *data = dev_get_platdata(&pdev->dev);
+	struct resource *cmd, *ctl;
+	struct ata_port_info pi = ixp4xx_port_info;
+	const struct ata_port_info *ppi[] = { &pi, NULL };
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	struct ixp4xx_pata *ixpp;
+	u32 csindex;
 	int ret;
+	int irq;
 
-	cs0 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	cs1 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	ixpp = devm_kzalloc(dev, sizeof(*ixpp), GFP_KERNEL);
+	if (!ixpp)
+		return -ENOMEM;
 
-	if (!cs0 || !cs1)
-		return -EINVAL;
+	ixpp->rmap = syscon_node_to_regmap(np->parent);
+	if (IS_ERR(ixpp->rmap))
+		return dev_err_probe(dev, PTR_ERR(ixpp->rmap), "no regmap\n");
+	/* Inspect our address to figure out what chipselect the CMD is on */
+	ret = of_property_read_u32_index(np, "reg", 0, &csindex);
+	if (ret)
+		return dev_err_probe(dev, ret, "can't inspect CMD address\n");
+	dev_info(dev, "using CS%d for PIO timing configuration\n", csindex);
+	ixpp->cmd_csreg = csindex * IXP4XX_EXP_TIMING_STRIDE;
 
-	/* allocate host */
-	host = ata_host_alloc(&pdev->dev, 1);
-	if (!host)
+	ixpp->host = ata_host_alloc_pinfo(dev, ppi, 1);
+	if (!ixpp->host)
 		return -ENOMEM;
+	ixpp->host->private_data = ixpp;
 
-	/* acquire resources and fill host */
-	ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
+	ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
 	if (ret)
 		return ret;
 
-	data->cs0 = devm_ioremap(&pdev->dev, cs0->start, 0x1000);
-	data->cs1 = devm_ioremap(&pdev->dev, cs1->start, 0x1000);
+	ixpp->cmd = devm_platform_get_and_ioremap_resource(pdev, 0, &cmd);
+	if (IS_ERR(ixpp->cmd))
+		return PTR_ERR(ixpp->cmd);
 
-	if (!data->cs0 || !data->cs1)
-		return -ENOMEM;
+	ixpp->ctl = devm_platform_get_and_ioremap_resource(pdev, 1, &ctl);
+	if (IS_ERR(ixpp->ctl))
+		return PTR_ERR(ixpp->ctl);
 
 	irq = platform_get_irq(pdev, 0);
-	if (irq)
-		irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
-
-	/* Setup expansion bus chip selects */
-	*data->cs0_cfg = data->cs0_bits;
-	*data->cs1_cfg = data->cs1_bits;
-
-	ap = host->ports[0];
+	if (irq < 0)
+		return irq;
+	irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
 
-	ap->ops	= &ixp4xx_port_ops;
-	ap->pio_mask = ATA_PIO4;
-	ap->flags |= ATA_FLAG_NO_ATAPI;
+	/* Just one port to set up */
+	ixp4xx_setup_port(ixpp->host->ports[0], ixpp, cmd->start, ctl->start);
 
-	ixp4xx_setup_port(ap, data, cs0->start, cs1->start);
+	ata_print_version_once(dev, DRV_VERSION);
 
-	ata_print_version_once(&pdev->dev, DRV_VERSION);
-
-	/* activate host */
-	return ata_host_activate(host, irq, ata_sff_interrupt, 0, &ixp4xx_sht);
+	return ata_host_activate(ixpp->host, irq, ata_sff_interrupt, 0, &ixp4xx_sht);
 }
 
+static const struct of_device_id ixp4xx_pata_of_match[] = {
+	{ .compatible = "intel,ixp4xx-compact-flash", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, ixp4xx_pata_of_match);
+
 static struct platform_driver ixp4xx_pata_platform_driver = {
 	.driver	 = {
 		.name   = DRV_NAME,
+		.of_match_table = ixp4xx_pata_of_match,
 	},
 	.probe		= ixp4xx_pata_probe,
 	.remove		= ata_platform_remove_one,
diff --git a/drivers/ata/pata_jmicron.c b/drivers/ata/pata_jmicron.c
index c3dedd3e71fb..b885f33e8980 100644
--- a/drivers/ata/pata_jmicron.c
+++ b/drivers/ata/pata_jmicron.c
@@ -107,20 +107,20 @@ static int jmicron_pre_reset(struct ata_link *link, unsigned long deadline)
 
 /* No PIO or DMA methods needed for this device */
 
-static struct scsi_host_template jmicron_sht = {
+static const struct scsi_host_template jmicron_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
 static struct ata_port_operations jmicron_ops = {
 	.inherits		= &ata_bmdma_port_ops,
-	.prereset		= jmicron_pre_reset,
+	.reset.prereset		= jmicron_pre_reset,
 };
 
 
 /**
  *	jmicron_init_one - Register Jmicron ATA PCI device with kernel services
  *	@pdev: PCI device to register
- *	@ent: Entry in jmicron_pci_tbl matching with @pdev
+ *	@id: PCI device ID
  *
  *	Called from kernel PCI layer.
  *
diff --git a/drivers/ata/pata_legacy.c b/drivers/ata/pata_legacy.c
index 4fd12b20df23..e7ac142c2423 100644
--- a/drivers/ata/pata_legacy.c
+++ b/drivers/ata/pata_legacy.c
@@ -63,7 +63,66 @@
 
 static int all;
 module_param(all, int, 0444);
-MODULE_PARM_DESC(all, "Grab all legacy port devices, even if PCI(0=off, 1=on)");
+MODULE_PARM_DESC(all,
+		 "Set to probe unclaimed pri/sec ISA port ranges even if PCI");
+
+static int probe_all;
+module_param(probe_all, int, 0);
+MODULE_PARM_DESC(probe_all,
+		 "Set to probe tertiary+ ISA port ranges even if PCI");
+
+static int probe_mask = ~0;
+module_param(probe_mask, int, 0);
+MODULE_PARM_DESC(probe_mask, "Probe mask for legacy ISA PATA ports");
+
+static int autospeed;
+module_param(autospeed, int, 0);
+MODULE_PARM_DESC(autospeed, "Chip present that snoops speed changes");
+
+static int pio_mask = ATA_PIO4;
+module_param(pio_mask, int, 0);
+MODULE_PARM_DESC(pio_mask, "PIO range for autospeed devices");
+
+static int iordy_mask = 0xFFFFFFFF;
+module_param(iordy_mask, int, 0);
+MODULE_PARM_DESC(iordy_mask, "Use IORDY if available");
+
+static int ht6560a;
+module_param(ht6560a, int, 0);
+MODULE_PARM_DESC(ht6560a, "HT 6560A on primary 1, second 2, both 3");
+
+static int ht6560b;
+module_param(ht6560b, int, 0);
+MODULE_PARM_DESC(ht6560b, "HT 6560B on primary 1, secondary 2, both 3");
+
+static int opti82c611a;
+module_param(opti82c611a, int, 0);
+MODULE_PARM_DESC(opti82c611a,
+		 "Opti 82c611A on primary 1, secondary 2, both 3");
+
+static int opti82c46x;
+module_param(opti82c46x, int, 0);
+MODULE_PARM_DESC(opti82c46x,
+		 "Opti 82c465MV on primary 1, secondary 2, both 3");
+
+#ifdef CONFIG_PATA_QDI_MODULE
+static int qdi = 1;
+#else
+static int qdi;
+#endif
+module_param(qdi, int, 0);
+MODULE_PARM_DESC(qdi, "Set to probe QDI controllers");
+
+#ifdef CONFIG_PATA_WINBOND_VLB_MODULE
+static int winbond = 1;
+#else
+static int winbond;
+#endif
+module_param(winbond, int, 0);
+MODULE_PARM_DESC(winbond,
+		 "Set to probe Winbond controllers, "
+		 "give I/O port if non standard");
+
 
 enum controller {
 	BIOS = 0,
@@ -114,32 +173,6 @@ static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 };
 static struct legacy_probe probe_list[NR_HOST];
 static struct legacy_data legacy_data[NR_HOST];
 static struct ata_host *legacy_host[NR_HOST];
-static int nr_legacy_host;
-
-
-static int probe_all;		/* Set to check all ISA port ranges */
-static int ht6560a;		/* HT 6560A on primary 1, second 2, both 3 */
-static int ht6560b;		/* HT 6560A on primary 1, second 2, both 3 */
-static int opti82c611a;		/* Opti82c611A on primary 1, sec 2, both 3 */
-static int opti82c46x;		/* Opti 82c465MV present(pri/sec autodetect) */
-static int autospeed;		/* Chip present which snoops speed changes */
-static int pio_mask = ATA_PIO4;	/* PIO range for autospeed devices */
-static int iordy_mask = 0xFFFFFFFF;	/* Use iordy if available */
-
-/* Set to probe QDI controllers */
-#ifdef CONFIG_PATA_QDI_MODULE
-static int qdi = 1;
-#else
-static int qdi;
-#endif
-
-#ifdef CONFIG_PATA_WINBOND_VLB_MODULE
-static int winbond = 1;		/* Set to probe Winbond controllers,
-					give I/O port if non standard */
-#else
-static int winbond;		/* Set to probe Winbond controllers,
-					give I/O port if non standard */
-#endif
 
 /**
  *	legacy_probe_add	-	Add interface to probe list
@@ -168,6 +201,8 @@ static int legacy_probe_add(unsigned long port, unsigned int irq,
 			free = lp;
 		/* Matching port, or the correct slot for ordering */
 		if (lp->port == port || legacy_port[i] == port) {
+			if (!(probe_mask & 1 << i))
+				return -1;
 			free = lp;
 			break;
 		}
@@ -213,7 +248,7 @@ static int legacy_set_mode(struct ata_link *link, struct ata_device **unused)
 	return 0;
 }
 
-static struct scsi_host_template legacy_sht = {
+static const struct scsi_host_template legacy_sht = {
 	ATA_PIO_SHT(DRV_NAME),
 };
 
@@ -278,9 +313,10 @@ static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev)
 	outb(inb(0x1F4) & 0x07, 0x1F4);
 
 	rt = inb(0x1F3);
-	rt &= 0x07 << (3 * adev->devno);
+	rt &= ~(0x07 << (3 * !adev->devno));
 	if (pio)
-		rt |= (1 + 3 * pio) << (3 * adev->devno);
+		rt |= (1 + 3 * pio) << (3 * !adev->devno);
+	outb(rt, 0x1F3);
 
 	udelay(100);
 	outb(inb(0x1F2) | 0x01, 0x1F2);
@@ -315,7 +351,8 @@ static unsigned int pdc_data_xfer_vlb(struct ata_queued_cmd *qc,
 			iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
 
 		if (unlikely(slop)) {
-			__le32 pad;
+			__le32 pad = 0;
+
 			if (rw == READ) {
 				pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));
 				memcpy(buf + buflen - slop, &pad, slop);
@@ -588,7 +625,7 @@ static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev)
 }
 
 /**
- *	opt82c465mv_qc_issue		-	command issue
+ *	opti82c46x_qc_issue		-	command issue
  *	@qc: command pending
  *
  *	Called when the libata layer is about to issue a command. We wrap
@@ -705,7 +742,8 @@ static unsigned int vlb32_data_xfer(struct ata_queued_cmd *qc,
 			ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
 
 		if (unlikely(slop)) {
-			__le32 pad;
+			__le32 pad = 0;
+
 			if (rw == WRITE) {
 				memcpy(&pad, buf + buflen - slop, slop);
 				iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);
@@ -923,7 +961,7 @@ static __init int probe_chip_type(struct legacy_probe *probe)
 
 /**
  *	legacy_init_one		-	attach a legacy interface
- *	@pl: probe record
+ *	@probe: probe record
  *
  *	Register an ISA bus IDE interface. Such interfaces are PIO and we
  *	assume do not support IRQ sharing.
@@ -1009,8 +1047,8 @@ fail:
 /**
  *	legacy_check_special_cases	-	ATA special cases
  *	@p: PCI device to check
- *	@master: set this if we find an ATA master
- *	@master: set this if we find an ATA secondary
+ *	@primary: set this if we find an ATA master
+ *	@secondary: set this if we find an ATA secondary
  *
  *	A small number of vendors implemented early PCI ATA interfaces
  *	on bridge logic without the ATA interface being PCI visible.
@@ -1236,9 +1274,11 @@ static __exit void legacy_exit(void)
 {
 	int i;
 
-	for (i = 0; i < nr_legacy_host; i++) {
+	for (i = 0; i < NR_HOST; i++) {
 		struct legacy_data *ld = &legacy_data[i];
-		ata_host_detach(legacy_host[i]);
+
+		if (legacy_host[i])
+			ata_host_detach(legacy_host[i]);
 		platform_device_unregister(ld->platform_dev);
 	}
 }
@@ -1250,16 +1290,5 @@ MODULE_VERSION(DRV_VERSION);
 MODULE_ALIAS("pata_qdi");
 MODULE_ALIAS("pata_winbond");
 
-module_param(probe_all, int, 0);
-module_param(autospeed, int, 0);
-module_param(ht6560a, int, 0);
-module_param(ht6560b, int, 0);
-module_param(opti82c611a, int, 0);
-module_param(opti82c46x, int, 0);
-module_param(qdi, int, 0);
-module_param(winbond, int, 0);
-module_param(pio_mask, int, 0);
-module_param(iordy_mask, int, 0);
-
 module_init(legacy_init);
 module_exit(legacy_exit);
diff --git a/drivers/ata/pata_macio.c b/drivers/ata/pata_macio.c
index e47a28271f5b..9eefdc5df5df 100644
--- a/drivers/ata/pata_macio.c
+++ b/drivers/ata/pata_macio.c
@@ -21,6 +21,7 @@
 #include <linux/adb.h>
 #include <linux/pmu.h>
 #include <linux/scatterlist.h>
+#include <linux/irqdomain.h>
 #include <linux/of.h>
 #include <linux/gfp.h>
 #include <linux/pci.h>
@@ -207,6 +208,19 @@ static const char* macio_ata_names[] = {
 /* Don't let a DMA segment go all the way to 64K */
 #define MAX_DBDMA_SEG		0xff00
 
+#ifdef CONFIG_PAGE_SIZE_64KB
+/*
+ * The SCSI core requires the segment size to cover at least a page, so
+ * for 64K page size kernels it must be at least 64K. However the
+ * hardware can't handle 64K, so pata_macio_qc_prep() will split large
+ * requests. To handle the split requests the tablesize must be halved.
+ */
+#define PATA_MACIO_MAX_SEGMENT_SIZE	SZ_64K
+#define PATA_MACIO_SG_TABLESIZE		(MAX_DCMDS / 2)
+#else
+#define PATA_MACIO_MAX_SEGMENT_SIZE	MAX_DBDMA_SEG
+#define PATA_MACIO_SG_TABLESIZE		MAX_DCMDS
+#endif
 
 /*
  * Wait 1s for disk to answer on IDE bus after a hard reset
@@ -540,7 +554,8 @@ static enum ata_completion_errors pata_macio_qc_prep(struct ata_queued_cmd *qc)
 
 		while (sg_len) {
 			/* table overflow should never happen */
-			BUG_ON (pi++ >= MAX_DCMDS);
+			if (WARN_ON_ONCE(pi >= MAX_DCMDS))
+				return AC_ERR_SYSTEM;
 
 			len = (sg_len < MAX_DBDMA_SEG) ? sg_len : MAX_DBDMA_SEG;
 			table->command = cpu_to_le16(write ? OUTPUT_MORE: INPUT_MORE);
@@ -552,11 +567,13 @@ static enum ata_completion_errors pata_macio_qc_prep(struct ata_queued_cmd *qc)
 			addr += len;
 			sg_len -= len;
 			++table;
+			++pi;
 		}
 	}
 
 	/* Should never happen according to Tejun */
-	BUG_ON(!pi);
+	if (WARN_ON_ONCE(!pi))
+		return AC_ERR_SYSTEM;
 
 	/* Convert the last command to an input/output */
 	table--;
@@ -666,8 +683,7 @@ static u8 pata_macio_bmdma_status(struct ata_port *ap)
 	 * a multi-block transfer.
 	 *
 	 * - The dbdma fifo hasn't yet finished flushing to
-	 * to system memory when the disk interrupt occurs.
-	 *
+	 * system memory when the disk interrupt occurs.
 	 */
 
 	/* First check for errors */
@@ -742,7 +758,7 @@ static void pata_macio_irq_clear(struct ata_port *ap)
 
 static void pata_macio_reset_hw(struct pata_macio_priv *priv, int resume)
 {
-	dev_dbg(priv->dev, "Enabling & resetting... \n");
+	dev_dbg(priv->dev, "Enabling & resetting...\n");
 
 	if (priv->mediabay)
 		return;
@@ -796,7 +812,8 @@ static void pata_macio_reset_hw(struct pata_macio_priv *priv, int resume)
 /* Hook the standard slave config to fixup some HW related alignment
  * restrictions
  */
-static int pata_macio_slave_config(struct scsi_device *sdev)
+static int pata_macio_sdev_configure(struct scsi_device *sdev,
+				     struct queue_limits *lim)
 {
 	struct ata_port *ap = ata_shost_to_port(sdev->host);
 	struct pata_macio_priv *priv = ap->private_data;
@@ -805,7 +822,7 @@ static int pata_macio_slave_config(struct scsi_device *sdev)
 	int rc;
 
 	/* First call original */
-	rc = ata_scsi_slave_config(sdev);
+	rc = ata_scsi_sdev_configure(sdev, lim);
 	if (rc)
 		return rc;
 
@@ -814,8 +831,8 @@ static int pata_macio_slave_config(struct scsi_device *sdev)
 
 	/* OHare has issues with non cache aligned DMA on some chipsets */
 	if (priv->kind == controller_ohare) {
-		blk_queue_update_dma_alignment(sdev->request_queue, 31);
-		blk_queue_update_dma_pad(sdev->request_queue, 31);
+		lim->dma_alignment = 31;
+		lim->dma_pad_mask = 31;
 
 		/* Tell the world about it */
 		ata_dev_info(dev, "OHare alignment limits applied\n");
@@ -829,8 +846,8 @@ static int pata_macio_slave_config(struct scsi_device *sdev)
 	/* Shasta and K2 seem to have "issues" with reads ... */
 	if (priv->kind == controller_sh_ata6 || priv->kind == controller_k2_ata6) {
 		/* Allright these are bad, apply restrictions */
-		blk_queue_update_dma_alignment(sdev->request_queue, 15);
-		blk_queue_update_dma_pad(sdev->request_queue, 15);
+		lim->dma_alignment = 15;
+		lim->dma_pad_mask = 15;
 
 		/* We enable MWI and hack cache line size directly here, this
 		 * is specific to this chipset and not normal values, we happen
@@ -853,12 +870,8 @@ static int pata_macio_slave_config(struct scsi_device *sdev)
 #ifdef CONFIG_PM_SLEEP
 static int pata_macio_do_suspend(struct pata_macio_priv *priv, pm_message_t mesg)
 {
-	int rc;
-
 	/* First, core libata suspend to do most of the work */
-	rc = ata_host_suspend(priv->host, mesg);
-	if (rc)
-		return rc;
+	ata_host_suspend(priv->host, mesg);
 
 	/* Restore to default timings */
 	pata_macio_default_timings(priv);
@@ -913,16 +926,16 @@ static int pata_macio_do_resume(struct pata_macio_priv *priv)
 }
 #endif /* CONFIG_PM_SLEEP */
 
-static struct scsi_host_template pata_macio_sht = {
-	ATA_BASE_SHT(DRV_NAME),
-	.sg_tablesize		= MAX_DCMDS,
+static const struct scsi_host_template pata_macio_sht = {
+	__ATA_BASE_SHT(DRV_NAME),
+	.sg_tablesize		= PATA_MACIO_SG_TABLESIZE,
 	/* We may not need that strict one */
 	.dma_boundary		= ATA_DMA_BOUNDARY,
-	/* Not sure what the real max is but we know it's less than 64K, let's
-	 * use 64K minus 256
-	 */
-	.max_segment_size	= MAX_DBDMA_SEG,
-	.slave_configure	= pata_macio_slave_config,
+	.max_segment_size	= PATA_MACIO_MAX_SEGMENT_SIZE,
+	.sdev_configure		= pata_macio_sdev_configure,
+	.sdev_groups		= ata_common_sdev_groups,
+	.can_queue		= ATA_DEF_QUEUE,
+	.tag_alloc_policy_rr	= true,
 };
 
 static struct ata_port_operations pata_macio_ops = {
@@ -1029,7 +1042,7 @@ static void pmac_macio_calc_timing_masks(struct pata_macio_priv *priv,
 		}
 		i++;
 	}
-	dev_dbg(priv->dev, "Supported masks: PIO=%lx, MWDMA=%lx, UDMA=%lx\n",
+	dev_dbg(priv->dev, "Supported masks: PIO=%x, MWDMA=%x, UDMA=%x\n",
 		pinfo->pio_mask, pinfo->mwdma_mask, pinfo->udma_mask);
 }
 
@@ -1189,7 +1202,7 @@ static int pata_macio_attach(struct macio_dev *mdev,
 	return rc;
 }
 
-static int pata_macio_detach(struct macio_dev *mdev)
+static void pata_macio_detach(struct macio_dev *mdev)
 {
 	struct ata_host *host = macio_get_drvdata(mdev);
 	struct pata_macio_priv *priv = host->private_data;
@@ -1204,8 +1217,6 @@ static int pata_macio_detach(struct macio_dev *mdev)
 	ata_host_detach(host);
 
 	unlock_media_bay(priv->mdev->media_bay);
-
-	return 0;
 }
 
 #ifdef CONFIG_PM_SLEEP
@@ -1287,7 +1298,7 @@ static int pata_macio_pci_attach(struct pci_dev *pdev,
 	priv->dev = &pdev->dev;
 
 	/* Get MMIO regions */
-	if (pci_request_regions(pdev, "pata-macio")) {
+	if (pcim_request_all_regions(pdev, "pata-macio")) {
 		dev_err(&pdev->dev,
 			"Cannot obtain PCI resources\n");
 		return -EBUSY;
@@ -1330,19 +1341,11 @@ static int pata_macio_pci_resume(struct pci_dev *pdev)
 
 static const struct of_device_id pata_macio_match[] =
 {
-	{
-	.name 		= "IDE",
-	},
-	{
-	.name 		= "ATA",
-	},
-	{
-	.type		= "ide",
-	},
-	{
-	.type		= "ata",
-	},
-	{},
+	{ .name = "IDE", },
+	{ .name = "ATA", },
+	{ .type = "ide", },
+	{ .type = "ata", },
+	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, pata_macio_match);
 
@@ -1382,9 +1385,6 @@ static struct pci_driver pata_macio_pci_driver = {
 	.suspend	= pata_macio_pci_suspend,
 	.resume		= pata_macio_pci_resume,
 #endif
-	.driver = {
-		.owner		= THIS_MODULE,
-	},
 };
 MODULE_DEVICE_TABLE(pci, pata_macio_pci_match);
 
diff --git a/drivers/ata/pata_marvell.c b/drivers/ata/pata_marvell.c
index b066809ba9a1..deab67328388 100644
--- a/drivers/ata/pata_marvell.c
+++ b/drivers/ata/pata_marvell.c
@@ -32,7 +32,6 @@
 
 static int marvell_pata_active(struct pci_dev *pdev)
 {
-	int i;
 	u32 devices;
 	void __iomem *barp;
 
@@ -44,11 +43,6 @@ static int marvell_pata_active(struct pci_dev *pdev)
 	if (barp == NULL)
 		return -ENOMEM;
 
-	printk("BAR5:");
-	for(i = 0; i <= 0x0F; i++)
-		printk("%02X:%02X ", i, ioread8(barp + i));
-	printk("\n");
-
 	devices = ioread32(barp + 0x0C);
 	pci_iounmap(pdev, barp);
 
@@ -83,6 +77,8 @@ static int marvell_cable_detect(struct ata_port *ap)
 	switch(ap->port_no)
 	{
 	case 0:
+		if (!ap->ioaddr.bmdma_addr)
+			return ATA_CBL_PATA_UNK;
 		if (ioread8(ap->ioaddr.bmdma_addr + 1) & 1)
 			return ATA_CBL_PATA40;
 		return ATA_CBL_PATA80;
@@ -96,21 +92,21 @@ static int marvell_cable_detect(struct ata_port *ap)
 
 /* No PIO or DMA methods needed for this device */
 
-static struct scsi_host_template marvell_sht = {
+static const struct scsi_host_template marvell_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
 static struct ata_port_operations marvell_ops = {
 	.inherits		= &ata_bmdma_port_ops,
 	.cable_detect		= marvell_cable_detect,
-	.prereset		= marvell_pre_reset,
+	.reset.prereset		= marvell_pre_reset,
 };
 
 
 /**
  *	marvell_init_one - Register Marvell ATA PCI device with kernel services
  *	@pdev: PCI device to register
- *	@ent: Entry in marvell_pci_tbl matching with @pdev
+ *	@id: PCI device ID
  *
  *	Called from kernel PCI layer.
  *
@@ -149,7 +145,8 @@ static int marvell_init_one (struct pci_dev *pdev, const struct pci_device_id *i
 
 #if IS_ENABLED(CONFIG_SATA_AHCI)
 	if (!marvell_pata_active(pdev)) {
-		printk(KERN_INFO DRV_NAME ": PATA port not active, deferring to AHCI driver.\n");
+		dev_info(&pdev->dev,
+			 "PATA port not active, deferring to AHCI driver.\n");
 		return -ENODEV;
 	}
 #endif
diff --git a/drivers/ata/pata_mpc52xx.c b/drivers/ata/pata_mpc52xx.c
index f1d352d5f128..210a63283f62 100644
--- a/drivers/ata/pata_mpc52xx.c
+++ b/drivers/ata/pata_mpc52xx.c
@@ -19,11 +19,13 @@
 #include <linux/gfp.h>
 #include <linux/delay.h>
 #include <linux/libata.h>
-#include <linux/of_platform.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
 #include <linux/types.h>
 
 #include <asm/cacheflush.h>
-#include <asm/prom.h>
 #include <asm/mpc52xx.h>
 
 #include <linux/fsl/bestcomm/bestcomm.h>
@@ -605,7 +607,7 @@ mpc52xx_ata_task_irq(int irq, void *vpriv)
 	return IRQ_HANDLED;
 }
 
-static struct scsi_host_template mpc52xx_ata_sht = {
+static const struct scsi_host_template mpc52xx_ata_sht = {
 	ATA_PIO_SHT(DRV_NAME),
 };
 
@@ -618,7 +620,6 @@ static struct ata_port_operations mpc52xx_ata_port_ops = {
 	.bmdma_start		= mpc52xx_bmdma_start,
 	.bmdma_stop		= mpc52xx_bmdma_stop,
 	.bmdma_status		= mpc52xx_bmdma_status,
-	.qc_prep		= ata_noop_qc_prep,
 };
 
 static int mpc52xx_ata_init_one(struct device *dev,
@@ -682,7 +683,7 @@ static int mpc52xx_ata_probe(struct platform_device *op)
 	struct bcom_task *dmatsk;
 
 	/* Get ipb frequency */
-	ipb_freq = mpc5xxx_get_bus_frequency(op->dev.of_node);
+	ipb_freq = mpc5xxx_get_bus_frequency(&op->dev);
 	if (!ipb_freq) {
 		dev_err(&op->dev, "could not determine IPB bus frequency\n");
 		return -ENODEV;
@@ -730,13 +731,13 @@ static int mpc52xx_ata_probe(struct platform_device *op)
 		udma_mask = ATA_UDMA2 & ((1 << (*prop + 1)) - 1);
 
 	ata_irq = irq_of_parse_and_map(op->dev.of_node, 0);
-	if (ata_irq == NO_IRQ) {
+	if (!ata_irq) {
 		dev_err(&op->dev, "error mapping irq\n");
 		return -EINVAL;
 	}
 
 	/* Prepare our private structure */
-	priv = devm_kzalloc(&op->dev, sizeof(*priv), GFP_ATOMIC);
+	priv = devm_kzalloc(&op->dev, sizeof(*priv), GFP_KERNEL);
 	if (!priv) {
 		rv = -ENOMEM;
 		goto err1;
@@ -799,8 +800,7 @@ static int mpc52xx_ata_probe(struct platform_device *op)
 	return rv;
 }
 
-static int
-mpc52xx_ata_remove(struct platform_device *op)
+static void mpc52xx_ata_remove(struct platform_device *op)
 {
 	struct ata_host *host = platform_get_drvdata(op);
 	struct mpc52xx_ata_priv *priv = host->private_data;
@@ -814,8 +814,6 @@ mpc52xx_ata_remove(struct platform_device *op)
 	irq_dispose_mapping(task_irq);
 	bcom_ata_release(priv->dmatsk);
 	irq_dispose_mapping(priv->ata_irq);
-
-	return 0;
 }
 
 #ifdef CONFIG_PM_SLEEP
@@ -824,7 +822,8 @@ mpc52xx_ata_suspend(struct platform_device *op, pm_message_t state)
 {
 	struct ata_host *host = platform_get_drvdata(op);
 
-	return ata_host_suspend(host, state);
+	ata_host_suspend(host, state);
+	return 0;
 }
 
 static int
@@ -849,7 +848,7 @@ mpc52xx_ata_resume(struct platform_device *op)
 static const struct of_device_id mpc52xx_ata_of_match[] = {
 	{ .compatible = "fsl,mpc5200-ata", },
 	{ .compatible = "mpc5200-ata", },
-	{},
+	{ /* sentinel */ }
 };
 
 
diff --git a/drivers/ata/pata_mpiix.c b/drivers/ata/pata_mpiix.c
index 8fda0e32c1ab..ce310ae7c93a 100644
--- a/drivers/ata/pata_mpiix.c
+++ b/drivers/ata/pata_mpiix.c
@@ -136,7 +136,7 @@ static unsigned int mpiix_qc_issue(struct ata_queued_cmd *qc)
 	return ata_sff_qc_issue(qc);
 }
 
-static struct scsi_host_template mpiix_sht = {
+static const struct scsi_host_template mpiix_sht = {
 	ATA_PIO_SHT(DRV_NAME),
 };
 
@@ -145,7 +145,7 @@ static struct ata_port_operations mpiix_port_ops = {
 	.qc_issue	= mpiix_qc_issue,
 	.cable_detect	= ata_cable_40wire,
 	.set_piomode	= mpiix_set_piomode,
-	.prereset	= mpiix_pre_reset,
+	.reset.prereset	= mpiix_pre_reset,
 	.sff_data_xfer	= ata_sff_data_xfer32,
 };
 
diff --git a/drivers/ata/pata_netcell.c b/drivers/ata/pata_netcell.c
index a7ecc1a204b5..c0b2897fcf40 100644
--- a/drivers/ata/pata_netcell.c
+++ b/drivers/ata/pata_netcell.c
@@ -21,16 +21,17 @@
 /* No PIO or DMA methods needed for this device */
 
 static unsigned int netcell_read_id(struct ata_device *adev,
-					struct ata_taskfile *tf, u16 *id)
+				    struct ata_taskfile *tf, __le16 *id)
 {
 	unsigned int err_mask = ata_do_dev_read_id(adev, tf, id);
+
 	/* Firmware forgets to mark words 85-87 valid */
 	if (err_mask == 0)
-		id[ATA_ID_CSF_DEFAULT] |= 0x4000;
+		id[ATA_ID_CSF_DEFAULT] |= cpu_to_le16(0x4000);
 	return err_mask;
 }
 
-static struct scsi_host_template netcell_sht = {
+static const struct scsi_host_template netcell_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
diff --git a/drivers/ata/pata_ninja32.c b/drivers/ata/pata_ninja32.c
index f9255d6fd194..76a91013d27d 100644
--- a/drivers/ata/pata_ninja32.c
+++ b/drivers/ata/pata_ninja32.c
@@ -77,7 +77,7 @@ static void ninja32_dev_select(struct ata_port *ap, unsigned int device)
 	}
 }
 
-static struct scsi_host_template ninja32_sht = {
+static const struct scsi_host_template ninja32_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
diff --git a/drivers/ata/pata_ns87410.c b/drivers/ata/pata_ns87410.c
index ca3ab2736fef..bdb55c1a3280 100644
--- a/drivers/ata/pata_ns87410.c
+++ b/drivers/ata/pata_ns87410.c
@@ -114,7 +114,7 @@ static unsigned int ns87410_qc_issue(struct ata_queued_cmd *qc)
 	return ata_sff_qc_issue(qc);
 }
 
-static struct scsi_host_template ns87410_sht = {
+static const struct scsi_host_template ns87410_sht = {
 	ATA_PIO_SHT(DRV_NAME),
 };
 
@@ -123,7 +123,7 @@ static struct ata_port_operations ns87410_port_ops = {
 	.qc_issue	= ns87410_qc_issue,
 	.cable_detect	= ata_cable_40wire,
 	.set_piomode	= ns87410_set_piomode,
-	.prereset	= ns87410_pre_reset,
+	.reset.prereset	= ns87410_pre_reset,
 };
 
 static int ns87410_init_one(struct pci_dev *dev, const struct pci_device_id *id)
diff --git a/drivers/ata/pata_ns87415.c b/drivers/ata/pata_ns87415.c
index 4b2ba813dcab..c697219a61a2 100644
--- a/drivers/ata/pata_ns87415.c
+++ b/drivers/ata/pata_ns87415.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- *    pata_ns87415.c - NS87415 (non PARISC) PATA
+ *    pata_ns87415.c - NS87415 (and PARISC SUPERIO 87560) PATA
  *
  *	(C) 2005 Red Hat <alan@lxorguk.ukuu.org.uk>
  *
@@ -16,7 +16,6 @@
  *    systems. This has its own special mountain of errata.
  *
  *    TODO:
- *	Test PARISC SuperIO
  *	Get someone to test on SPARC
  *	Implement lazy pio/dma switching for better performance
  *	8bit shared timing.
@@ -114,7 +113,7 @@ static void ns87415_set_piomode(struct ata_port *ap, struct ata_device *adev)
  *	ns87415_bmdma_setup		-	Set up DMA
  *	@qc: Command block
  *
- *	Set up for bus masterng DMA. We have to do this ourselves
+ *	Set up for bus mastering DMA. We have to do this ourselves
  *	rather than use the helper due to a chip erratum
  */
 
@@ -175,7 +174,7 @@ static void ns87415_bmdma_stop(struct ata_queued_cmd *qc)
  *	ns87415_irq_clear		-	Clear interrupt
  *	@ap: Channel to clear
  *
- *	Erratum: Due to a chip bug regisers 02 and 0A bit 1 and 2 (the
+ *	Erratum: Due to a chip bug registers 02 and 0A bit 1 and 2 (the
  *	error bits) are reset by writing to register 00 or 08.
  */
 
@@ -261,12 +260,12 @@ static u8 ns87560_check_status(struct ata_port *ap)
  *	LOCKING:
  *	Inherited from caller.
  */
-void ns87560_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
+static void ns87560_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
 {
 	struct ata_ioports *ioaddr = &ap->ioaddr;
 
-	tf->command = ns87560_check_status(ap);
-	tf->feature = ioread8(ioaddr->error_addr);
+	tf->status = ns87560_check_status(ap);
+	tf->error = ioread8(ioaddr->error_addr);
 	tf->nsect = ioread8(ioaddr->nsect_addr);
 	tf->lbal = ioread8(ioaddr->lbal_addr);
 	tf->lbam = ioread8(ioaddr->lbam_addr);
@@ -321,7 +320,7 @@ static struct ata_port_operations ns87560_pata_ops = {
 };
 #endif
 
-static struct scsi_host_template ns87415_sht = {
+static const struct scsi_host_template ns87415_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
diff --git a/drivers/ata/pata_octeon_cf.c b/drivers/ata/pata_octeon_cf.c
index bd87476ab481..df42ebe98db7 100644
--- a/drivers/ata/pata_octeon_cf.c
+++ b/drivers/ata/pata_octeon_cf.c
@@ -16,10 +16,11 @@
 #include <linux/slab.h>
 #include <linux/irq.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
 #include <linux/of_platform.h>
 #include <linux/platform_device.h>
 #include <scsi/scsi_host.h>
-
+#include <trace/events/libata.h>
 #include <asm/byteorder.h>
 #include <asm/octeon/octeon.h>
 
@@ -58,7 +59,7 @@ struct octeon_cf_port {
 	u64 dma_base;
 };
 
-static struct scsi_host_template octeon_cf_sht = {
+static const struct scsi_host_template octeon_cf_sht = {
 	ATA_PIO_SHT(DRV_NAME),
 };
 
@@ -67,22 +68,18 @@ module_param(enable_dma, int, 0444);
 MODULE_PARM_DESC(enable_dma,
 		 "Enable use of DMA on interfaces that support it (0=no dma [default], 1=use dma)");
 
-/**
+/*
  * Convert nanosecond based time to setting used in the
  * boot bus timing register, based on timing multiple
  */
 static unsigned int ns_to_tim_reg(unsigned int tim_mult, unsigned int nsecs)
 {
-	unsigned int val;
-
 	/*
 	 * Compute # of eclock periods to get desired duration in
 	 * nanoseconds.
 	 */
-	val = DIV_ROUND_UP(nsecs * (octeon_get_io_clock_rate() / 1000000),
+	return DIV_ROUND_UP(nsecs * (octeon_get_io_clock_rate() / 1000000),
 			  1000 * tim_mult);
-
-	return val;
 }
 
 static void octeon_cf_set_boot_reg_cfg(int cs, unsigned int multiplier)
@@ -118,7 +115,7 @@ static void octeon_cf_set_boot_reg_cfg(int cs, unsigned int multiplier)
 	cvmx_write_csr(CVMX_MIO_BOOT_REG_CFGX(cs), reg_cfg.u64);
 }
 
-/**
+/*
  * Called after libata determines the needed PIO mode. This
  * function programs the Octeon bootbus regions to support the
  * timing requirements of the PIO mode.
@@ -186,7 +183,7 @@ static void octeon_cf_set_piomode(struct ata_port *ap, struct ata_device *dev)
 	reg_tim.s.ale = 0;
 	/* Not used */
 	reg_tim.s.page = 0;
-	/* Time after IORDY to coninue to assert the data */
+	/* Time after IORDY to continue to assert the data */
 	reg_tim.s.wait = 0;
 	/* Time to wait to complete the cycle. */
 	reg_tim.s.pause = pause;
@@ -273,16 +270,16 @@ static void octeon_cf_set_dmamode(struct ata_port *ap, struct ata_device *dev)
 	dma_tim.s.we_n = ns_to_tim_reg(tim_mult, oe_n);
 	dma_tim.s.we_a = ns_to_tim_reg(tim_mult, oe_a);
 
-	pr_debug("ns to ticks (mult %d) of %d is: %d\n", tim_mult, 60,
+	ata_dev_dbg(dev, "ns to ticks (mult %d) of %d is: %d\n", tim_mult, 60,
 		 ns_to_tim_reg(tim_mult, 60));
-	pr_debug("oe_n: %d, oe_a: %d, dmack_s: %d, dmack_h: %d, dmarq: %d, pause: %d\n",
+	ata_dev_dbg(dev, "oe_n: %d, oe_a: %d, dmack_s: %d, dmack_h: %d, dmarq: %d, pause: %d\n",
 		 dma_tim.s.oe_n, dma_tim.s.oe_a, dma_tim.s.dmack_s,
 		 dma_tim.s.dmack_h, dma_tim.s.dmarq, dma_tim.s.pause);
 
 	cvmx_write_csr(cf_port->dma_base + DMA_TIM, dma_tim.u64);
 }
 
-/**
+/*
  * Handle an 8 bit I/O request.
  *
  * @qc:         Queued command
@@ -321,7 +318,7 @@ static unsigned int octeon_cf_data_xfer8(struct ata_queued_cmd *qc,
 	return buflen;
 }
 
-/**
+/*
  * Handle a 16 bit I/O request.
  *
  * @qc:         Queued command
@@ -376,7 +373,7 @@ static unsigned int octeon_cf_data_xfer16(struct ata_queued_cmd *qc,
 	return buflen;
 }
 
-/**
+/*
  * Read the taskfile for 16bit non-True IDE only.
  */
 static void octeon_cf_tf_read16(struct ata_port *ap, struct ata_taskfile *tf)
@@ -386,7 +383,7 @@ static void octeon_cf_tf_read16(struct ata_port *ap, struct ata_taskfile *tf)
 	void __iomem *base = ap->ioaddr.data_addr;
 
 	blob = __raw_readw(base + 0xc);
-	tf->feature = blob >> 8;
+	tf->error = blob >> 8;
 
 	blob = __raw_readw(base + 2);
 	tf->nsect = blob & 0xff;
@@ -398,7 +395,7 @@ static void octeon_cf_tf_read16(struct ata_port *ap, struct ata_taskfile *tf)
 
 	blob = __raw_readw(base + 6);
 	tf->device = blob & 0xff;
-	tf->command = blob >> 8;
+	tf->status = blob >> 8;
 
 	if (tf->flags & ATA_TFLAG_LBA48) {
 		if (likely(ap->ioaddr.ctl_addr)) {
@@ -440,7 +437,6 @@ static int octeon_cf_softreset16(struct ata_link *link, unsigned int *classes,
 	int rc;
 	u8 err;
 
-	DPRINTK("about to softreset\n");
 	__raw_writew(ap->ctl, base + 0xe);
 	udelay(20);
 	__raw_writew(ap->ctl | ATA_SRST, base + 0xe);
@@ -455,11 +451,10 @@ static int octeon_cf_softreset16(struct ata_link *link, unsigned int *classes,
 
 	/* determine by signature whether we have ATA or ATAPI devices */
 	classes[0] = ata_sff_dev_classify(&link->device[0], 1, &err);
-	DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
 	return 0;
 }
 
-/**
+/*
  * Load the taskfile for 16bit non-True IDE only.  The device_addr is
  * not loaded, we do this as part of octeon_cf_exec_command16.
  */
@@ -479,23 +474,11 @@ static void octeon_cf_tf_load16(struct ata_port *ap,
 		__raw_writew(tf->hob_feature << 8, base + 0xc);
 		__raw_writew(tf->hob_nsect | tf->hob_lbal << 8, base + 2);
 		__raw_writew(tf->hob_lbam | tf->hob_lbah << 8, base + 4);
-		VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
-			tf->hob_feature,
-			tf->hob_nsect,
-			tf->hob_lbal,
-			tf->hob_lbam,
-			tf->hob_lbah);
 	}
 	if (is_addr) {
 		__raw_writew(tf->feature << 8, base + 0xc);
 		__raw_writew(tf->nsect | tf->lbal << 8, base + 2);
 		__raw_writew(tf->lbam | tf->lbah << 8, base + 4);
-		VPRINTK("feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
-			tf->feature,
-			tf->nsect,
-			tf->lbal,
-			tf->lbam,
-			tf->lbah);
 	}
 	ata_wait_idle(ap);
 }
@@ -516,20 +499,14 @@ static void octeon_cf_exec_command16(struct ata_port *ap,
 {
 	/* The base of the registers is at ioaddr.data_addr. */
 	void __iomem *base = ap->ioaddr.data_addr;
-	u16 blob;
+	u16 blob = 0;
 
-	if (tf->flags & ATA_TFLAG_DEVICE) {
-		VPRINTK("device 0x%X\n", tf->device);
+	if (tf->flags & ATA_TFLAG_DEVICE)
 		blob = tf->device;
-	} else {
-		blob = 0;
-	}
 
-	DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
 	blob |= (tf->command << 8);
 	__raw_writew(blob, base + 6);
 
-
 	ata_wait_idle(ap);
 }
 
@@ -543,15 +520,13 @@ static void octeon_cf_dma_setup(struct ata_queued_cmd *qc)
 	struct octeon_cf_port *cf_port;
 
 	cf_port = ap->private_data;
-	DPRINTK("ENTER\n");
 	/* issue r/w command */
 	qc->cursg = qc->sg;
 	cf_port->dma_finished = 0;
 	ap->ops->sff_exec_command(ap, &qc->tf);
-	DPRINTK("EXIT\n");
 }
 
-/**
+/*
  * Start a DMA transfer that was already setup
  *
  * @qc:     Information about the DMA
@@ -563,8 +538,6 @@ static void octeon_cf_dma_start(struct ata_queued_cmd *qc)
 	union cvmx_mio_boot_dma_intx mio_boot_dma_int;
 	struct scatterlist *sg;
 
-	VPRINTK("%d scatterlists\n", qc->n_elem);
-
 	/* Get the scatter list entry we need to DMA into */
 	sg = qc->cursg;
 	BUG_ON(!sg);
@@ -605,14 +578,10 @@ static void octeon_cf_dma_start(struct ata_queued_cmd *qc)
 
 	mio_boot_dma_cfg.s.adr = sg_dma_address(sg);
 
-	VPRINTK("%s %d bytes address=%p\n",
-		(mio_boot_dma_cfg.s.rw) ? "write" : "read", sg->length,
-		(void *)(unsigned long)mio_boot_dma_cfg.s.adr);
-
 	cvmx_write_csr(cf_port->dma_base + DMA_CFG, mio_boot_dma_cfg.u64);
 }
 
-/**
+/*
  *
  *	LOCKING:
  *	spin_lock_irqsave(host lock)
@@ -627,9 +596,7 @@ static unsigned int octeon_cf_dma_finished(struct ata_port *ap,
 	union cvmx_mio_boot_dma_intx dma_int;
 	u8 status;
 
-	VPRINTK("ata%u: protocol %d task_state %d\n",
-		ap->print_id, qc->tf.protocol, ap->hsm_task_state);
-
+	trace_ata_bmdma_stop(ap, &qc->tf, qc->tag);
 
 	if (ap->hsm_task_state != HSM_ST_LAST)
 		return 0;
@@ -678,7 +645,6 @@ static irqreturn_t octeon_cf_interrupt(int irq, void *dev_instance)
 
 	spin_lock_irqsave(&host->lock, flags);
 
-	DPRINTK("ENTER\n");
 	for (i = 0; i < host->n_ports; i++) {
 		u8 status;
 		struct ata_port *ap;
@@ -701,6 +667,7 @@ static irqreturn_t octeon_cf_interrupt(int irq, void *dev_instance)
 			if (!sg_is_last(qc->cursg)) {
 				qc->cursg = sg_next(qc->cursg);
 				handled = 1;
+				trace_ata_bmdma_start(ap, &qc->tf, qc->tag);
 				octeon_cf_dma_start(qc);
 				continue;
 			} else {
@@ -732,7 +699,6 @@ static irqreturn_t octeon_cf_interrupt(int irq, void *dev_instance)
 		}
 	}
 	spin_unlock_irqrestore(&host->lock, flags);
-	DPRINTK("EXIT\n");
 	return IRQ_RETVAL(handled);
 }
 
@@ -800,8 +766,11 @@ static unsigned int octeon_cf_qc_issue(struct ata_queued_cmd *qc)
 	case ATA_PROT_DMA:
 		WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING);
 
+		trace_ata_tf_load(ap, &qc->tf);
 		ap->ops->sff_tf_load(ap, &qc->tf);  /* load tf registers */
+		trace_ata_bmdma_setup(ap, &qc->tf, qc->tag);
 		octeon_cf_dma_setup(qc);	    /* set up dma */
+		trace_ata_bmdma_start(ap, &qc->tf, qc->tag);
 		octeon_cf_dma_start(qc);	    /* initiate dma */
 		ap->hsm_task_state = HSM_ST_LAST;
 		break;
@@ -820,7 +789,6 @@ static unsigned int octeon_cf_qc_issue(struct ata_queued_cmd *qc)
 static struct ata_port_operations octeon_cf_ops = {
 	.inherits		= &ata_sff_port_ops,
 	.check_atapi_dma	= octeon_cf_check_atapi_dma,
-	.qc_prep		= ata_noop_qc_prep,
 	.qc_issue		= octeon_cf_qc_issue,
 	.sff_dev_select		= octeon_cf_dev_select,
 	.sff_irq_on		= octeon_cf_ata_port_noaction,
@@ -836,9 +804,7 @@ static int octeon_cf_probe(struct platform_device *pdev)
 	struct resource *res_cs0, *res_cs1;
 
 	bool is_16bit;
-	const __be32 *cs_num;
-	struct property *reg_prop;
-	int n_addr, n_size, reg_len;
+	u64 reg;
 	struct device_node *node;
 	void __iomem *cs0;
 	void __iomem *cs1 = NULL;
@@ -848,8 +814,8 @@ static int octeon_cf_probe(struct platform_device *pdev)
 	irq_handler_t irq_handler = NULL;
 	void __iomem *base;
 	struct octeon_cf_port *cf_port;
-	int rv = -ENOMEM;
 	u32 bus_width;
+	int rv;
 
 	node = pdev->dev.of_node;
 	if (node == NULL)
@@ -866,15 +832,10 @@ static int octeon_cf_probe(struct platform_device *pdev)
 	else
 		is_16bit = false;
 
-	n_addr = of_n_addr_cells(node);
-	n_size = of_n_size_cells(node);
-
-	reg_prop = of_find_property(node, "reg", &reg_len);
-	if (!reg_prop || reg_len < sizeof(__be32))
-		return -EINVAL;
-
-	cs_num = reg_prop->value;
-	cf_port->cs0 = be32_to_cpup(cs_num);
+	rv = of_property_read_reg(node, 0, &reg, NULL);
+	if (rv < 0)
+		return rv;
+	cf_port->cs0 = upper_32_bits(reg);
 
 	if (cf_port->is_true_ide) {
 		struct device_node *dma_node;
@@ -888,20 +849,24 @@ static int octeon_cf_probe(struct platform_device *pdev)
 				int i;
 				res_dma = platform_get_resource(dma_dev, IORESOURCE_MEM, 0);
 				if (!res_dma) {
+					put_device(&dma_dev->dev);
 					of_node_put(dma_node);
 					return -EINVAL;
 				}
 				cf_port->dma_base = (u64)devm_ioremap(&pdev->dev, res_dma->start,
 									 resource_size(res_dma));
 				if (!cf_port->dma_base) {
+					put_device(&dma_dev->dev);
 					of_node_put(dma_node);
 					return -EINVAL;
 				}
 
-				irq_handler = octeon_cf_interrupt;
 				i = platform_get_irq(dma_dev, 0);
-				if (i > 0)
+				if (i > 0) {
 					irq = i;
+					irq_handler = octeon_cf_interrupt;
+				}
+				put_device(&dma_dev->dev);
 			}
 			of_node_put(dma_node);
 		}
@@ -912,13 +877,12 @@ static int octeon_cf_probe(struct platform_device *pdev)
 		cs1 = devm_ioremap(&pdev->dev, res_cs1->start,
 					   resource_size(res_cs1));
 		if (!cs1)
-			return rv;
-
-		if (reg_len < (n_addr + n_size + 1) * sizeof(__be32))
 			return -EINVAL;
 
-		cs_num += n_addr + n_size;
-		cf_port->cs1 = be32_to_cpup(cs_num);
+		rv = of_property_read_reg(node, 1, &reg, NULL);
+		if (rv < 0)
+			return rv;
+		cf_port->cs1 = upper_32_bits(reg);
 	}
 
 	res_cs0 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -928,12 +892,12 @@ static int octeon_cf_probe(struct platform_device *pdev)
 	cs0 = devm_ioremap(&pdev->dev, res_cs0->start,
 				   resource_size(res_cs0));
 	if (!cs0)
-		return rv;
+		return -ENOMEM;
 
 	/* allocate host */
 	host = ata_host_alloc(&pdev->dev, 1);
 	if (!host)
-		return rv;
+		return -ENOMEM;
 
 	ap = host->ports[0];
 	ap->private_data = cf_port;
@@ -971,14 +935,13 @@ static int octeon_cf_probe(struct platform_device *pdev)
 		ap->mwdma_mask	= enable_dma ? ATA_MWDMA4 : 0;
 
 		/* True IDE mode needs a timer to poll for not-busy.  */
-		hrtimer_init(&cf_port->delayed_finish, CLOCK_MONOTONIC,
-			     HRTIMER_MODE_REL);
-		cf_port->delayed_finish.function = octeon_cf_delayed_finish;
+		hrtimer_setup(&cf_port->delayed_finish, octeon_cf_delayed_finish, CLOCK_MONOTONIC,
+			      HRTIMER_MODE_REL);
 	} else {
 		/* 16 bit but not True IDE */
 		base = cs0 + 0x800;
 		octeon_cf_ops.sff_data_xfer	= octeon_cf_data_xfer16;
-		octeon_cf_ops.softreset		= octeon_cf_softreset16;
+		octeon_cf_ops.reset.softreset	= octeon_cf_softreset16;
 		octeon_cf_ops.sff_check_status	= octeon_cf_check_status16;
 		octeon_cf_ops.sff_tf_read	= octeon_cf_tf_read16;
 		octeon_cf_ops.sff_tf_load	= octeon_cf_tf_load16;
@@ -1037,10 +1000,8 @@ static void octeon_cf_shutdown(struct device *dev)
 }
 
 static const struct of_device_id octeon_cf_match[] = {
-	{
-		.compatible = "cavium,ebt3000-compact-flash",
-	},
-	{},
+	{ .compatible = "cavium,ebt3000-compact-flash", },
+	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, octeon_cf_match);
 
diff --git a/drivers/ata/pata_of_platform.c b/drivers/ata/pata_of_platform.c
index 35aa158fc976..178b28eff170 100644
--- a/drivers/ata/pata_of_platform.c
+++ b/drivers/ata/pata_of_platform.c
@@ -15,7 +15,7 @@
 
 #define DRV_NAME "pata_of_platform"
 
-static struct scsi_host_template pata_platform_sht = {
+static const struct scsi_host_template pata_platform_sht = {
 	ATA_PIO_SHT(DRV_NAME),
 };
 
@@ -25,11 +25,12 @@ static int pata_of_platform_probe(struct platform_device *ofdev)
 	struct device_node *dn = ofdev->dev.of_node;
 	struct resource io_res;
 	struct resource ctl_res;
-	struct resource *irq_res;
+	struct resource irq_res;
 	unsigned int reg_shift = 0;
 	int pio_mode = 0;
 	int pio_mask;
 	bool use16bit;
+	int irq;
 
 	ret = of_address_to_resource(dn, 0, &io_res);
 	if (ret) {
@@ -45,7 +46,15 @@ static int pata_of_platform_probe(struct platform_device *ofdev)
 		return -EINVAL;
 	}
 
-	irq_res = platform_get_resource(ofdev, IORESOURCE_IRQ, 0);
+	memset(&irq_res, 0, sizeof(irq_res));
+
+	irq = platform_get_irq_optional(ofdev, 0);
+	if (irq < 0 && irq != -ENXIO)
+		return irq;
+	if (irq > 0) {
+		irq_res.start = irq;
+		irq_res.end = irq;
+	}
 
 	of_property_read_u32(dn, "reg-shift", &reg_shift);
 
@@ -63,14 +72,14 @@ static int pata_of_platform_probe(struct platform_device *ofdev)
 	pio_mask = 1 << pio_mode;
 	pio_mask |= (1 << pio_mode) - 1;
 
-	return __pata_platform_probe(&ofdev->dev, &io_res, &ctl_res, irq_res,
+	return __pata_platform_probe(&ofdev->dev, &io_res, &ctl_res, irq > 0 ? &irq_res : NULL,
 				     reg_shift, pio_mask, &pata_platform_sht,
 				     use16bit);
 }
 
 static const struct of_device_id pata_of_platform_match[] = {
 	{ .compatible = "ata-generic", },
-	{ },
+	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, pata_of_platform_match);
 
diff --git a/drivers/ata/pata_oldpiix.c b/drivers/ata/pata_oldpiix.c
index 22a020374410..81a7f3eb5654 100644
--- a/drivers/ata/pata_oldpiix.c
+++ b/drivers/ata/pata_oldpiix.c
@@ -70,7 +70,7 @@ static void oldpiix_set_piomode (struct ata_port *ap, struct ata_device *adev)
 	int control = 0;
 
 	/*
-	 *	See Intel Document 298600-004 for the timing programing rules
+	 *	See Intel Document 298600-004 for the timing programming rules
 	 *	for PIIX/ICH. Note that the early PIIX does not have the slave
 	 *	timing port at 0x44.
 	 */
@@ -204,7 +204,7 @@ static unsigned int oldpiix_qc_issue(struct ata_queued_cmd *qc)
 }
 
 
-static struct scsi_host_template oldpiix_sht = {
+static const struct scsi_host_template oldpiix_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
@@ -214,7 +214,7 @@ static struct ata_port_operations oldpiix_pata_ops = {
 	.cable_detect		= ata_cable_40wire,
 	.set_piomode		= oldpiix_set_piomode,
 	.set_dmamode		= oldpiix_set_dmamode,
-	.prereset		= oldpiix_pre_reset,
+	.reset.prereset		= oldpiix_pre_reset,
 };
 
 
diff --git a/drivers/ata/pata_opti.c b/drivers/ata/pata_opti.c
index 06a800a3b070..3db1b95d1404 100644
--- a/drivers/ata/pata_opti.c
+++ b/drivers/ata/pata_opti.c
@@ -69,7 +69,7 @@ static int opti_pre_reset(struct ata_link *link, unsigned long deadline)
 /**
  *	opti_write_reg		-	control register setup
  *	@ap: ATA port
- *	@value: value
+ *	@val: value
  *	@reg: control register number
  *
  *	The Opti uses magic 'trapdoor' register accesses to do configuration
@@ -148,7 +148,7 @@ static void opti_set_piomode(struct ata_port *ap, struct ata_device *adev)
 	opti_write_reg(ap, 0x85, CNTRL_REG);
 }
 
-static struct scsi_host_template opti_sht = {
+static const struct scsi_host_template opti_sht = {
 	ATA_PIO_SHT(DRV_NAME),
 };
 
@@ -156,7 +156,7 @@ static struct ata_port_operations opti_port_ops = {
 	.inherits	= &ata_sff_port_ops,
 	.cable_detect	= ata_cable_40wire,
 	.set_piomode	= opti_set_piomode,
-	.prereset	= opti_pre_reset,
+	.reset.prereset	= opti_pre_reset,
 };
 
 static int opti_init_one(struct pci_dev *dev, const struct pci_device_id *id)
diff --git a/drivers/ata/pata_optidma.c b/drivers/ata/pata_optidma.c
index fbcf0af34924..b42dba5f4e05 100644
--- a/drivers/ata/pata_optidma.c
+++ b/drivers/ata/pata_optidma.c
@@ -153,7 +153,7 @@ static void optidma_mode_setup(struct ata_port *ap, struct ata_device *adev, u8
 	if (pair) {
 		u8 pair_addr;
 		/* Hardware constraint */
-		if (pair->dma_mode)
+		if (ata_dma_enabled(pair))
 			pair_addr = 0;
 		else
 			pair_addr = addr_timing[pci_clock][pair->pio_mode - XFER_PIO_0];
@@ -287,7 +287,7 @@ static void optiplus_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
 }
 
 /**
- *	optidma_make_bits	-	PCI setup helper
+ *	optidma_make_bits43	-	PCI setup helper
  *	@adev: ATA device
  *
  *	Turn the ATA device setup into PCI configuration bits
@@ -301,7 +301,7 @@ static u8 optidma_make_bits43(struct ata_device *adev)
 	};
 	if (!ata_dev_enabled(adev))
 		return 0;
-	if (adev->dma_mode)
+	if (ata_dma_enabled(adev))
 		return adev->dma_mode - XFER_MW_DMA_0;
 	return bits43[adev->pio_mode - XFER_PIO_0];
 }
@@ -309,6 +309,7 @@ static u8 optidma_make_bits43(struct ata_device *adev)
 /**
  *	optidma_set_mode	-	mode setup
  *	@link: link to set up
+ *	@r_failed: out parameter for failed device
  *
  *	Use the standard setup to tune the chipset and then finalise the
  *	configuration by writing the nibble of extra bits of data into
@@ -321,7 +322,9 @@ static int optidma_set_mode(struct ata_link *link, struct ata_device **r_failed)
 	u8 r;
 	int nybble = 4 * ap->port_no;
 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
-	int rc  = ata_do_set_mode(link, r_failed);
+	int rc;
+
+	rc = ata_set_mode(link, r_failed);
 	if (rc == 0) {
 		pci_read_config_byte(pdev, 0x43, &r);
 
@@ -333,7 +336,7 @@ static int optidma_set_mode(struct ata_link *link, struct ata_device **r_failed)
 	return rc;
 }
 
-static struct scsi_host_template optidma_sht = {
+static const struct scsi_host_template optidma_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
@@ -343,7 +346,7 @@ static struct ata_port_operations optidma_port_ops = {
 	.set_piomode	= optidma_set_pio_mode,
 	.set_dmamode	= optidma_set_dma_mode,
 	.set_mode	= optidma_set_mode,
-	.prereset	= optidma_pre_reset,
+	.reset.prereset	= optidma_pre_reset,
 };
 
 static struct ata_port_operations optiplus_port_ops = {
@@ -354,7 +357,7 @@ static struct ata_port_operations optiplus_port_ops = {
 
 /**
  *	optiplus_with_udma	-	Look for UDMA capable setup
- *	@pdev; ATA controller
+ *	@pdev: ATA controller
  */
 
 static int optiplus_with_udma(struct pci_dev *pdev)
diff --git a/drivers/ata/pata_palmld.c b/drivers/ata/pata_palmld.c
deleted file mode 100644
index 2448441571ed..000000000000
--- a/drivers/ata/pata_palmld.c
+++ /dev/null
@@ -1,138 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * drivers/ata/pata_palmld.c
- *
- * Driver for IDE channel in Palm LifeDrive
- *
- * Based on research of:
- *		Alex Osborne <ato@meshy.org>
- *
- * Rewrite for mainline:
- *		Marek Vasut <marek.vasut@gmail.com>
- *
- * Rewritten version based on pata_ixp4xx_cf.c:
- * ixp4xx PATA/Compact Flash driver
- * Copyright (C) 2006-07 Tower Technologies
- * Author: Alessandro Zummo <a.zummo@towertech.it>
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/libata.h>
-#include <linux/irq.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/gpio/consumer.h>
-
-#include <scsi/scsi_host.h>
-#include <mach/palmld.h>
-
-#define DRV_NAME "pata_palmld"
-
-struct palmld_pata {
-	struct ata_host *host;
-	struct gpio_desc *power;
-	struct gpio_desc *reset;
-};
-
-static struct scsi_host_template palmld_sht = {
-	ATA_PIO_SHT(DRV_NAME),
-};
-
-static struct ata_port_operations palmld_port_ops = {
-	.inherits		= &ata_sff_port_ops,
-	.sff_data_xfer		= ata_sff_data_xfer32,
-	.cable_detect		= ata_cable_40wire,
-};
-
-static int palmld_pata_probe(struct platform_device *pdev)
-{
-	struct palmld_pata *lda;
-	struct ata_port *ap;
-	void __iomem *mem;
-	struct device *dev = &pdev->dev;
-	int ret;
-
-	lda = devm_kzalloc(dev, sizeof(*lda), GFP_KERNEL);
-	if (!lda)
-		return -ENOMEM;
-
-	/* allocate host */
-	lda->host = ata_host_alloc(dev, 1);
-	if (!lda->host)
-		return -ENOMEM;
-
-	/* remap drive's physical memory address */
-	mem = devm_ioremap(dev, PALMLD_IDE_PHYS, 0x1000);
-	if (!mem)
-		return -ENOMEM;
-
-	/* request and activate power and reset GPIOs */
-	lda->power = devm_gpiod_get(dev, "power", GPIOD_OUT_HIGH);
-	if (IS_ERR(lda->power))
-		return PTR_ERR(lda->power);
-	lda->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
-	if (IS_ERR(lda->reset)) {
-		gpiod_set_value(lda->power, 0);
-		return PTR_ERR(lda->reset);
-	}
-
-	/* Assert reset to reset the drive */
-	gpiod_set_value(lda->reset, 1);
-	msleep(30);
-	gpiod_set_value(lda->reset, 0);
-	msleep(30);
-
-	/* setup the ata port */
-	ap = lda->host->ports[0];
-	ap->ops	= &palmld_port_ops;
-	ap->pio_mask = ATA_PIO4;
-	ap->flags |= ATA_FLAG_PIO_POLLING;
-
-	/* memory mapping voodoo */
-	ap->ioaddr.cmd_addr = mem + 0x10;
-	ap->ioaddr.altstatus_addr = mem + 0xe;
-	ap->ioaddr.ctl_addr = mem + 0xe;
-
-	/* start the port */
-	ata_sff_std_ports(&ap->ioaddr);
-
-	/* activate host */
-	ret = ata_host_activate(lda->host, 0, NULL, IRQF_TRIGGER_RISING,
-				&palmld_sht);
-	/* power down on failure */
-	if (ret) {
-		gpiod_set_value(lda->power, 0);
-		return ret;
-	}
-
-	platform_set_drvdata(pdev, lda);
-	return 0;
-}
-
-static int palmld_pata_remove(struct platform_device *pdev)
-{
-	struct palmld_pata *lda = platform_get_drvdata(pdev);
-
-	ata_platform_remove_one(pdev);
-
-	/* power down the HDD */
-	gpiod_set_value(lda->power, 0);
-
-	return 0;
-}
-
-static struct platform_driver palmld_pata_platform_driver = {
-	.driver	 = {
-		.name   = DRV_NAME,
-	},
-	.probe		= palmld_pata_probe,
-	.remove		= palmld_pata_remove,
-};
-
-module_platform_driver(palmld_pata_platform_driver);
-
-MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>");
-MODULE_DESCRIPTION("PalmLD PATA driver");
-MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform:" DRV_NAME);
diff --git a/drivers/ata/pata_parport/Kconfig b/drivers/ata/pata_parport/Kconfig
new file mode 100644
index 000000000000..2c953f5d1396
--- /dev/null
+++ b/drivers/ata/pata_parport/Kconfig
@@ -0,0 +1,141 @@
+# SPDX-License-Identifier: GPL-2.0
+
+comment "Parallel IDE protocol modules"
+	depends on PATA_PARPORT
+
+config PATA_PARPORT_ATEN
+	tristate "ATEN EH-100 protocol"
+	depends on PATA_PARPORT
+	help
+	  This option enables support for the ATEN EH-100 parallel port IDE
+	  protocol. This protocol is used in some inexpensive low performance
+	  parallel port kits made in Hong Kong.
+
+config PATA_PARPORT_BPCK
+	tristate "MicroSolutions backpack (Series 5) protocol"
+	depends on PATA_PARPORT
+	help
+	  This option enables support for the Micro Solutions BACKPACK
+	  parallel port Series 5 IDE protocol.  (Most BACKPACK drives made
+	  before 1999 were Series 5) Series 5 drives will NOT always have the
+	  Series noted on the bottom of the drive. Series 6 drivers will.
+
+	  In other words, if your BACKPACK drive doesn't say "Series 6" on the
+	  bottom, enable this option.
+
+config PATA_PARPORT_BPCK6
+	tristate "MicroSolutions backpack (Series 6) protocol"
+	depends on PATA_PARPORT
+	help
+	  This option enables support for the Micro Solutions BACKPACK
+	  parallel port Series 6 IDE protocol.  (Most BACKPACK drives made
+	  after 1999 were Series 6) Series 6 drives will have the Series noted
+	  on the bottom of the drive.  Series 5 drivers don't always have it
+	  noted.
+
+	  In other words, if your BACKPACK drive says "Series 6" on the
+	  bottom, enable this option.
+
+config PATA_PARPORT_COMM
+	tristate "DataStor Commuter protocol"
+	depends on PATA_PARPORT
+	help
+	  This option enables support for the Commuter parallel port IDE
+	  protocol from DataStor.
+
+config PATA_PARPORT_DSTR
+	tristate "DataStor EP-2000 protocol"
+	depends on PATA_PARPORT
+	help
+	  This option enables support for the EP-2000 parallel port IDE
+	  protocol from DataStor
+
+config PATA_PARPORT_FIT2
+	tristate "FIT TD-2000 protocol"
+	depends on PATA_PARPORT
+	help
+	  This option enables support for the TD-2000 parallel port IDE
+	  protocol from Fidelity International Technology. This is a simple
+	  (low speed) adapter that is used in some portable hard drives.
+
+config PATA_PARPORT_FIT3
+	tristate "FIT TD-3000 protocol"
+	depends on PATA_PARPORT
+	help
+	  This option enables support for the TD-3000 parallel port IDE
+	  protocol from Fidelity International Technology. This protocol is
+	  used in newer models of their portable disk, CD-ROM and PD/CD
+	  devices.
+
+config PATA_PARPORT_EPAT
+	tristate "Shuttle EPAT/EPEZ protocol"
+	depends on PATA_PARPORT
+	help
+	  This option enables support for the EPAT parallel port IDE protocol.
+	  EPAT is a parallel port IDE adapter manufactured by Shuttle
+	  Technology and widely used in devices from major vendors such as
+	  Hewlett-Packard, SyQuest, Imation and Avatar.
+
+config PATA_PARPORT_EPATC8
+	bool "Support c7/c8 chips"
+	depends on PATA_PARPORT_EPAT
+	help
+	  This option enables support for the newer Shuttle EP1284 (aka c7 and
+	  c8) chip. You need this if you are using any recent Imation SuperDisk
+	  (LS-120) drive.
+
+config PATA_PARPORT_EPIA
+	tristate "Shuttle EPIA protocol"
+	depends on PATA_PARPORT
+	help
+	  This option enables support for the (obsolete) EPIA parallel port
+	  IDE protocol from Shuttle Technology. This adapter can still be
+	  found in some no-name kits.
+
+config PATA_PARPORT_FRIQ
+	tristate "Freecom IQ ASIC-2 protocol"
+	depends on PATA_PARPORT
+	help
+	  This option enables support for version 2 of the Freecom IQ parallel
+	  port IDE adapter.  This adapter is used by the Maxell Superdisk
+	  drive.
+
+config PATA_PARPORT_FRPW
+	tristate "FreeCom power protocol"
+	depends on PATA_PARPORT
+	help
+	  This option enables support for the Freecom power parallel port IDE
+	  protocol.
+
+config PATA_PARPORT_KBIC
+	tristate "KingByte KBIC-951A/971A protocols"
+	depends on PATA_PARPORT
+	help
+	  This option enables support for the KBIC-951A and KBIC-971A parallel
+	  port IDE protocols from KingByte Information Corp. KingByte's
+	  adapters appear in many no-name portable disk and CD-ROM products,
+	  especially in Europe.
+
+config PATA_PARPORT_KTTI
+	tristate "KT PHd protocol"
+	depends on PATA_PARPORT
+	help
+	  This option enables support for the "PHd" parallel port IDE protocol
+	  from KT Technology. This is a simple (low speed) adapter that is
+	  used in some 2.5" portable hard drives.
+
+config PATA_PARPORT_ON20
+	tristate "OnSpec 90c20 protocol"
+	depends on PATA_PARPORT
+	help
+	  This option enables support for the (obsolete) 90c20 parallel port
+	  IDE protocol from OnSpec (often marketed under the ValuStore brand
+	  name).
+
+config PATA_PARPORT_ON26
+	tristate "OnSpec 90c26 protocol"
+	depends on PATA_PARPORT
+	help
+	  This option enables support for the 90c26 parallel port IDE protocol
+	  from OnSpec Electronics (often marketed under the ValuStore brand
+	  name).
diff --git a/drivers/ata/pata_parport/Makefile b/drivers/ata/pata_parport/Makefile
new file mode 100644
index 000000000000..0932c8d55b91
--- /dev/null
+++ b/drivers/ata/pata_parport/Makefile
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_PATA_PARPORT)      += pata_parport.o
+
+obj-$(CONFIG_PATA_PARPORT_ATEN)	+= aten.o
+obj-$(CONFIG_PATA_PARPORT_BPCK)	+= bpck.o
+obj-$(CONFIG_PATA_PARPORT_COMM)	+= comm.o
+obj-$(CONFIG_PATA_PARPORT_DSTR)	+= dstr.o
+obj-$(CONFIG_PATA_PARPORT_KBIC)	+= kbic.o
+obj-$(CONFIG_PATA_PARPORT_EPAT)	+= epat.o
+obj-$(CONFIG_PATA_PARPORT_EPIA)	+= epia.o
+obj-$(CONFIG_PATA_PARPORT_FRPW)	+= frpw.o
+obj-$(CONFIG_PATA_PARPORT_FRIQ)	+= friq.o
+obj-$(CONFIG_PATA_PARPORT_FIT2)	+= fit2.o
+obj-$(CONFIG_PATA_PARPORT_FIT3)	+= fit3.o
+obj-$(CONFIG_PATA_PARPORT_ON20)	+= on20.o
+obj-$(CONFIG_PATA_PARPORT_ON26)	+= on26.o
+obj-$(CONFIG_PATA_PARPORT_KTTI)	+= ktti.o
+obj-$(CONFIG_PATA_PARPORT_BPCK6) += bpck6.o
diff --git a/drivers/ata/pata_parport/aten.c b/drivers/ata/pata_parport/aten.c
new file mode 100644
index 000000000000..620ce6c8da5c
--- /dev/null
+++ b/drivers/ata/pata_parport/aten.c
@@ -0,0 +1,144 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (c) 1997-8  Grant R. Guenther <grant@torque.net>
+ *
+ * aten.c is a low-level protocol driver for the ATEN EH-100
+ * parallel port adapter.  The EH-100 supports 4-bit and 8-bit
+ * modes only.  There is also an EH-132 which supports EPP mode
+ * transfers.  The EH-132 is not yet supported.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/wait.h>
+#include <linux/types.h>
+#include <asm/io.h>
+#include "pata_parport.h"
+
+#define j44(a,b)                ((((a>>4)&0x0f)|(b&0xf0))^0x88)
+
+/*
+ * cont = 0 - access the IDE register file
+ * cont = 1 - access the IDE command set
+ */
+static int  cont_map[2] = { 0x08, 0x20 };
+
+static void aten_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
+{
+	int r = regr + cont_map[cont] + 0x80;
+
+	w0(r); w2(0xe); w2(6); w0(val); w2(7); w2(6); w2(0xc);
+}
+
+static int aten_read_regr(struct pi_adapter *pi, int cont, int regr)
+{
+	int  a, b, r;
+
+	r = regr + cont_map[cont] + 0x40;
+
+	switch (pi->mode) {
+
+	case 0:
+		w0(r); w2(0xe); w2(6);
+		w2(7); w2(6); w2(0);
+		a = r1(); w0(0x10); b = r1(); w2(0xc);
+		return j44(a,b);
+
+	case 1:
+		r |= 0x10;
+		w0(r); w2(0xe); w2(6); w0(0xff);
+		w2(0x27); w2(0x26); w2(0x20);
+		a = r0();
+		w2(0x26); w2(0xc);
+		return a;
+	}
+	return -1;
+}
+
+static void aten_read_block(struct pi_adapter *pi, char *buf, int count)
+{
+	int  k, a, b, c, d;
+
+	switch (pi->mode) {
+
+	case 0:
+		w0(0x48); w2(0xe); w2(6);
+		for (k = 0; k < count / 2; k++) {
+			w2(7); w2(6); w2(2);
+			a = r1(); w0(0x58); b = r1();
+			w2(0); d = r1(); w0(0x48); c = r1();
+			buf[2 * k] = j44(c, d);
+			buf[2 * k + 1] = j44(a, b);
+		}
+		w2(0xc);
+		break;
+
+	case 1:
+		w0(0x58); w2(0xe); w2(6);
+		for (k = 0; k < count / 2; k++) {
+			w2(0x27); w2(0x26); w2(0x22);
+			a = r0(); w2(0x20); b = r0();
+			buf[2 * k] = b;
+			buf[2 * k + 1] = a;
+		}
+		w2(0x26); w2(0xc);
+		break;
+	}
+}
+
+static void aten_write_block(struct pi_adapter *pi, char *buf, int count)
+{
+	int k;
+
+	w0(0x88); w2(0xe); w2(6);
+	for (k = 0; k < count / 2; k++) {
+		w0(buf[2 * k + 1]); w2(0xe); w2(6);
+		w0(buf[2 * k]); w2(7); w2(6);
+	}
+	w2(0xc);
+}
+
+static void aten_connect(struct pi_adapter *pi)
+{
+	pi->saved_r0 = r0();
+	pi->saved_r2 = r2();
+	w2(0xc);
+}
+
+static void aten_disconnect(struct pi_adapter *pi)
+{
+	w0(pi->saved_r0);
+	w2(pi->saved_r2);
+}
+
+static void aten_log_adapter(struct pi_adapter *pi)
+{
+	char *mode_string[2] = { "4-bit", "8-bit" };
+
+	dev_info(&pi->dev,
+		 "ATEN EH-100 at 0x%x, mode %d (%s), delay %d\n",
+		 pi->port, pi->mode, mode_string[pi->mode], pi->delay);
+}
+
+static struct pi_protocol aten = {
+	.owner		= THIS_MODULE,
+	.name		= "aten",
+	.max_mode	= 2,
+	.epp_first	= 2,
+	.default_delay	= 1,
+	.max_units	= 1,
+	.write_regr	= aten_write_regr,
+	.read_regr	= aten_read_regr,
+	.write_block	= aten_write_block,
+	.read_block	= aten_read_block,
+	.connect	= aten_connect,
+	.disconnect	= aten_disconnect,
+	.log_adapter	= aten_log_adapter,
+};
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Grant R. Guenther <grant@torque.net>");
+MODULE_DESCRIPTION("ATEN EH-100 parallel port IDE adapter protocol driver");
+module_pata_parport_driver(aten);
diff --git a/drivers/ata/pata_parport/bpck.c b/drivers/ata/pata_parport/bpck.c
new file mode 100644
index 000000000000..bba1eda65f36
--- /dev/null
+++ b/drivers/ata/pata_parport/bpck.c
@@ -0,0 +1,507 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (c) 1996-1998  Grant R. Guenther <grant@torque.net>
+ *
+ * bpck.c is a low-level protocol driver for the MicroSolutions
+ * "backpack" parallel port IDE adapter.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/wait.h>
+#include <asm/io.h>
+#include "pata_parport.h"
+
+#undef r2
+#undef w2
+#undef PC
+
+#define PC			pi->private
+#define r2()			(PC=(in_p(2) & 0xff))
+#define w2(byte)  		{out_p(2,byte); PC = byte;}
+#define t2(pat)   		{PC ^= pat; out_p(2,PC);}
+#define e2()			{PC &= 0xfe; out_p(2,PC);}
+#define o2()			{PC |= 1; out_p(2,PC);}
+
+#define j44(l,h)     (((l>>3)&0x7)|((l>>4)&0x8)|((h<<1)&0x70)|(h&0x80))
+
+/*
+ * cont = 0 - access the IDE register file
+ * cont = 1 - access the IDE command set
+ * cont = 2 - use internal bpck register addressing
+ */
+static int  cont_map[3] = { 0x40, 0x48, 0 };
+
+static int bpck_read_regr(struct pi_adapter *pi, int cont, int regr)
+{
+	int r, l, h;
+
+	r = regr + cont_map[cont];
+
+	switch (pi->mode) {
+	case 0:
+		w0(r & 0xf); w0(r); t2(2); t2(4);
+	        l = r1();
+		t2(4);
+		h = r1();
+		return j44(l, h);
+	case 1:
+		w0(r & 0xf); w0(r); t2(2);
+		e2(); t2(0x20);
+		t2(4); h = r0();
+		t2(1); t2(0x20);
+		return h;
+	case 2:
+	case 3:
+	case 4:
+		w0(r); w2(9); w2(0); w2(0x20);
+		h = r4();
+		w2(0);
+		return h;
+
+	}
+	return -1;
+}
+
+static void bpck_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
+{
+	int r;
+
+        r = regr + cont_map[cont];
+
+	switch (pi->mode) {
+	case 0:
+	case 1: w0(r);
+		t2(2);
+		w0(val);
+		o2(); t2(4); t2(1);
+		break;
+	case 2:
+	case 3:
+	case 4: w0(r); w2(9); w2(0);
+		w0(val); w2(1); w2(3); w2(0);
+		break;
+
+	}
+}
+
+/* These macros access the bpck registers in native addressing */
+
+#define WR(r,v)		bpck_write_regr(pi,2,r,v)
+#define RR(r)		(bpck_read_regr(pi,2,r))
+
+static void bpck_write_block(struct pi_adapter *pi, char *buf, int count)
+{
+	int i;
+
+	switch (pi->mode) {
+
+	case 0:
+		WR(4, 0x40);
+		w0(0x40); t2(2); t2(1);
+		for (i = 0; i < count; i++) {
+			w0(buf[i]);
+			t2(4);
+		}
+		WR(4, 0);
+		break;
+
+	case 1:
+		WR(4, 0x50);
+		w0(0x40); t2(2); t2(1);
+		for (i = 0; i < count; i++) {
+			w0(buf[i]);
+			t2(4);
+		}
+		WR(4, 0x10);
+		break;
+
+	case 2:
+		WR(4, 0x48);
+		w0(0x40); w2(9); w2(0); w2(1);
+		for (i = 0; i < count; i++)
+			w4(buf[i]);
+		w2(0);
+		WR(4, 8);
+		break;
+
+	case 3:
+		WR(4, 0x48);
+		w0(0x40); w2(9); w2(0); w2(1);
+		for (i = 0; i < count / 2; i++)
+			w4w(((u16 *)buf)[i]);
+		w2(0);
+		WR(4, 8);
+		break;
+
+	case 4:
+		WR(4, 0x48);
+		w0(0x40); w2(9); w2(0); w2(1);
+		for (i = 0; i < count / 4; i++)
+			w4l(((u32 *)buf)[i]);
+		w2(0);
+		WR(4, 8);
+		break;
+ 	}
+}
+
+static void bpck_read_block(struct pi_adapter *pi, char *buf, int count)
+{
+	int i, l, h;
+
+	switch (pi->mode) {
+
+	case 0:
+		WR(4, 0x40);
+		w0(0x40); t2(2);
+		for (i = 0; i < count; i++) {
+			t2(4); l = r1();
+			t2(4); h = r1();
+			buf[i] = j44(l, h);
+		}
+		WR(4, 0);
+		break;
+
+	case 1:
+		WR(4, 0x50);
+		w0(0x40); t2(2); t2(0x20);
+		for (i = 0; i < count; i++) {
+			t2(4);
+			buf[i] = r0();
+		}
+		t2(1); t2(0x20);
+		WR(4, 0x10);
+		break;
+
+	case 2:
+		WR(4, 0x48);
+		w0(0x40); w2(9); w2(0); w2(0x20);
+		for (i = 0; i < count; i++)
+			buf[i] = r4();
+		w2(0);
+		WR(4, 8);
+		break;
+
+	case 3:
+		WR(4, 0x48);
+		w0(0x40); w2(9); w2(0); w2(0x20);
+		for (i = 0; i < count / 2; i++)
+			((u16 *)buf)[i] = r4w();
+		w2(0);
+		WR(4, 8);
+		break;
+
+	case 4:
+		WR(4, 0x48);
+		w0(0x40); w2(9); w2(0); w2(0x20);
+		for (i = 0; i < count / 4; i++)
+			((u32 *)buf)[i] = r4l();
+		w2(0);
+		WR(4, 8);
+		break;
+
+	}
+}
+
+static int bpck_probe_unit(struct pi_adapter *pi)
+{
+	int o1, o0, f7, id;
+	int t, s;
+
+	id = pi->unit;
+	s = 0;
+	w2(4); w2(0xe); r2(); t2(2);
+	o1 = r1()&0xf8;
+	o0 = r0();
+	w0(255-id); w2(4); w0(id);
+	t2(8); t2(8); t2(8);
+	t2(2); t = r1()&0xf8;
+	f7 = ((id % 8) == 7);
+	if ((f7) || (t != o1)) {
+		t2(2);
+		s = r1() & 0xf8;
+	}
+	if ((t == o1) && ((!f7) || (s == o1)))  {
+		w2(0x4c); w0(o0);
+		return 0;
+	}
+	t2(8); w0(0); t2(2); w2(0x4c); w0(o0);
+	return 1;
+}
+
+static void bpck_connect(struct pi_adapter *pi)
+{
+	pi->saved_r0 = r0();
+	w0(0xff-pi->unit); w2(4); w0(pi->unit);
+	t2(8); t2(8); t2(8);
+	t2(2); t2(2);
+
+	switch (pi->mode) {
+	case 0:
+		t2(8); WR(4, 0);
+		break;
+	case 1:
+		t2(8); WR(4, 0x10);
+		break;
+	case 2:
+	case 3:
+	case 4:
+		w2(0); WR(4, 8);
+		break;
+	}
+
+	WR(5,8);
+
+	/*
+	 * Possibly wrong, purpose unknown (fiddle with ESS logic ???)
+	 * if (pi->devtype == PI_PCD) {
+	 */
+	WR(0x46, 0x10);
+	WR(0x4c, 0x38);
+	WR(0x4d, 0x88);
+	WR(0x46, 0xa0);
+	WR(0x41, 0);
+	WR(0x4e, 8);
+	/* } */
+}
+
+static void bpck_disconnect(struct pi_adapter *pi)
+{
+	w0(0);
+	if (pi->mode >= 2) {
+		w2(9); w2(0);
+	} else {
+		t2(2);
+	}
+	w2(0x4c); w0(pi->saved_r0);
+}
+
+static void bpck_force_spp(struct pi_adapter *pi)
+{
+	/* This fakes the EPP protocol to turn off EPP ... */
+	pi->saved_r0 = r0();
+	w0(0xff-pi->unit); w2(4); w0(pi->unit);
+	t2(8); t2(8); t2(8);
+	t2(2); t2(2);
+
+	w2(0);
+	w0(4); w2(9); w2(0);
+	w0(0); w2(1); w2(3); w2(0);
+	w0(0); w2(9); w2(0);
+	w2(0x4c); w0(pi->saved_r0);
+}
+
+#define TEST_LEN  16
+
+static int bpck_test_proto(struct pi_adapter *pi)
+{
+	int i, e, l, h, om;
+	char buf[TEST_LEN];
+
+	bpck_force_spp(pi);
+
+	switch (pi->mode) {
+
+	case 0:
+		bpck_connect(pi);
+		WR(0x13, 0x7f);
+		w0(0x13); t2(2);
+		for (i = 0; i < TEST_LEN; i++) {
+			t2(4); l = r1();
+			t2(4); h = r1();
+			buf[i] = j44(l, h);
+		}
+		bpck_disconnect(pi);
+		break;
+
+	case 1:
+		bpck_connect(pi);
+		WR(0x13, 0x7f);
+		w0(0x13); t2(2); t2(0x20);
+		for (i = 0; i < TEST_LEN; i++) {
+			t2(4);
+			buf[i] = r0();
+		}
+		t2(1); t2(0x20);
+		bpck_disconnect(pi);
+		break;
+
+	case 2:
+	case 3:
+	case 4:
+		om = pi->mode;
+		pi->mode = 0;
+		bpck_connect(pi);
+		WR(7, 3);
+		WR(4, 8);
+		bpck_disconnect(pi);
+
+		pi->mode = om;
+		bpck_connect(pi);
+		w0(0x13); w2(9); w2(1); w0(0); w2(3); w2(0); w2(0xe0);
+
+		switch (pi->mode) {
+		case 2:
+			for (i = 0; i < TEST_LEN; i++)
+				buf[i] = r4();
+			break;
+		case 3:
+			for (i = 0; i < TEST_LEN / 2; i++)
+				((u16 *)buf)[i] = r4w();
+			break;
+		case 4:
+			for (i = 0; i < TEST_LEN / 4; i++)
+				((u32 *)buf)[i] = r4l();
+			break;
+		}
+
+		w2(0);
+		WR(7, 0);
+		bpck_disconnect(pi);
+		break;
+
+	}
+
+	dev_dbg(&pi->dev, "bpck: 0x%x unit %d mode %d: ",
+		pi->port, pi->unit, pi->mode);
+	print_hex_dump_debug("bpck: ", DUMP_PREFIX_NONE, TEST_LEN, 1, buf,
+			     TEST_LEN, false);
+
+	e = 0;
+	for (i = 0; i < TEST_LEN; i++) {
+		if (buf[i] != i + 1)
+			e++;
+	}
+
+	return e;
+}
+
+static void bpck_read_eeprom(struct pi_adapter *pi, char *buf)
+{
+	int i, j, k, p, v, f, om, od;
+
+	bpck_force_spp(pi);
+
+	om = pi->mode;  od = pi->delay;
+	pi->mode = 0; pi->delay = 6;
+
+	bpck_connect(pi);
+
+	WR(4, 0);
+	for (i = 0; i < 64; i++) {
+		WR(6, 8);
+		WR(6, 0xc);
+		p = 0x100;
+		for (k = 0; k < 9; k++) {
+			f = (((i + 0x180) & p) != 0) * 2;
+			WR(6, f + 0xc);
+			WR(6, f + 0xd);
+			WR(6, f + 0xc);
+			p = (p >> 1);
+		}
+		for (j = 0; j < 2; j++) {
+			v = 0;
+			for (k = 0; k < 8; k++) {
+				WR(6, 0xc);
+				WR(6, 0xd);
+				WR(6, 0xc);
+				f = RR(0);
+				v = 2 * v + (f == 0x84);
+			}
+			buf[2 * i + 1 - j] = v;
+		}
+	}
+	WR(6, 8);
+	WR(6, 0);
+	WR(5, 8);
+
+	bpck_disconnect(pi);
+
+        if (om >= 2) {
+		bpck_connect(pi);
+		WR(7, 3);
+		WR(4, 8);
+		bpck_disconnect(pi);
+        }
+
+	pi->mode = om; pi->delay = od;
+}
+
+static int bpck_test_port(struct pi_adapter *pi)
+{
+	int i, r, m;
+
+	/* Check for 8-bit port */
+	w2(0x2c); i = r0(); w0(255-i); r = r0(); w0(i);
+	m = -1;
+	if (r == i)
+		m = 2;
+	if (r == (255-i))
+		m = 0;
+
+	w2(0xc);
+	i = r0();
+	w0(255-i);
+	r = r0();
+	w0(i);
+	if (r != (255-i))
+		m = -1;
+
+	if (m == 0) {
+		w2(6);
+		w2(0xc);
+		r = r0();
+		w0(0xaa);
+		w0(r);
+		w0(0xaa);
+	}
+	if (m == 2) {
+		w2(0x26);
+		w2(0xc);
+	}
+
+	if (m == -1)
+		return 0;
+
+	return 5;
+}
+
+static void bpck_log_adapter(struct pi_adapter *pi)
+{
+	char *mode_str[5] = { "4-bit", "8-bit", "EPP-8", "EPP-16", "EPP-32" };
+	char scratch[128];
+
+	bpck_read_eeprom(pi,scratch);
+	print_hex_dump_bytes("bpck EEPROM: ", DUMP_PREFIX_NONE, scratch, 128);
+	dev_info(&pi->dev,
+		 "backpack %8.8s unit %d at 0x%x, mode %d (%s), delay %d\n",
+		 &scratch[110], pi->unit, pi->port, pi->mode,
+		 mode_str[pi->mode], pi->delay);
+}
+
+static struct pi_protocol bpck = {
+	.owner		= THIS_MODULE,
+	.name		= "bpck",
+	.max_mode	= 5,
+	.epp_first	= 2,
+	.default_delay	= 4,
+	.max_units	= 255,
+	.write_regr	= bpck_write_regr,
+	.read_regr	= bpck_read_regr,
+	.write_block	= bpck_write_block,
+	.read_block	= bpck_read_block,
+	.connect	= bpck_connect,
+	.disconnect	= bpck_disconnect,
+	.test_port	= bpck_test_port,
+	.probe_unit	= bpck_probe_unit,
+	.test_proto	= bpck_test_proto,
+	.log_adapter	= bpck_log_adapter,
+};
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Grant R. Guenther <grant@torque.net>");
+MODULE_DESCRIPTION("MicroSolutions BACKPACK parallel port IDE adapter protocol driver");
+module_pata_parport_driver(bpck);
diff --git a/drivers/ata/pata_parport/bpck6.c b/drivers/ata/pata_parport/bpck6.c
new file mode 100644
index 000000000000..62c2b53325e1
--- /dev/null
+++ b/drivers/ata/pata_parport/bpck6.c
@@ -0,0 +1,464 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (c) 2001 Micro Solutions Inc.
+ *
+ * backpack.c is a low-level protocol driver for the Micro Solutions
+ * "BACKPACK" parallel port IDE adapter (works on Series 6 drives).
+ *
+ * Written by: Ken Hahn (linux-dev@micro-solutions.com)
+ *             Clive Turvey (linux-dev@micro-solutions.com)
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/parport.h>
+#include "pata_parport.h"
+
+/* 60772 Commands */
+#define ACCESS_REG		0x00
+#define ACCESS_PORT		0x40
+
+#define ACCESS_READ		0x00
+#define ACCESS_WRITE		0x20
+
+/* 60772 Command Prefix */
+#define CMD_PREFIX_SET		0xe0	// Special command that modifies next command's operation
+#define CMD_PREFIX_RESET	0xc0	// Resets current cmd modifier reg bits
+ #define PREFIX_IO16		0x01	// perform 16-bit wide I/O
+ #define PREFIX_FASTWR		0x04	// enable PPC mode fast-write
+ #define PREFIX_BLK		0x08	// enable block transfer mode
+
+/* 60772 Registers */
+#define REG_STATUS		0x00	// status register
+ #define STATUS_IRQA		0x01	// Peripheral IRQA line
+ #define STATUS_EEPROM_DO	0x40	// Serial EEPROM data bit
+#define REG_VERSION		0x01	// PPC version register (read)
+#define REG_HWCFG		0x02	// Hardware Config register
+#define REG_RAMSIZE		0x03	// Size of RAM Buffer
+ #define RAMSIZE_128K		0x02
+#define REG_EEPROM		0x06	// EEPROM control register
+ #define EEPROM_SK		0x01	// eeprom SK bit
+ #define EEPROM_DI		0x02	// eeprom DI bit
+ #define EEPROM_CS		0x04	// eeprom CS bit
+ #define EEPROM_EN		0x08	// eeprom output enable
+#define REG_BLKSIZE		0x08	// Block transfer len (24 bit)
+
+/* flags */
+#define fifo_wait		0x10
+
+/* DONT CHANGE THESE LEST YOU BREAK EVERYTHING - BIT FIELD DEPENDENCIES */
+#define PPCMODE_UNI_SW		0
+#define PPCMODE_UNI_FW		1
+#define PPCMODE_BI_SW		2
+#define PPCMODE_BI_FW		3
+#define PPCMODE_EPP_BYTE	4
+#define PPCMODE_EPP_WORD	5
+#define PPCMODE_EPP_DWORD	6
+
+static int mode_map[] = { PPCMODE_UNI_FW, PPCMODE_BI_FW, PPCMODE_EPP_BYTE,
+			  PPCMODE_EPP_WORD, PPCMODE_EPP_DWORD };
+
+static void bpck6_send_cmd(struct pi_adapter *pi, u8 cmd)
+{
+	switch (mode_map[pi->mode]) {
+	case PPCMODE_UNI_SW:
+	case PPCMODE_UNI_FW:
+	case PPCMODE_BI_SW:
+	case PPCMODE_BI_FW:
+		parport_write_data(pi->pardev->port, cmd);
+		parport_frob_control(pi->pardev->port, 0, PARPORT_CONTROL_AUTOFD);
+		break;
+	case PPCMODE_EPP_BYTE:
+	case PPCMODE_EPP_WORD:
+	case PPCMODE_EPP_DWORD:
+		pi->pardev->port->ops->epp_write_addr(pi->pardev->port, &cmd, 1, 0);
+		break;
+	}
+}
+
+static u8 bpck6_rd_data_byte(struct pi_adapter *pi)
+{
+	u8 data = 0;
+
+	switch (mode_map[pi->mode]) {
+	case PPCMODE_UNI_SW:
+	case PPCMODE_UNI_FW:
+		parport_frob_control(pi->pardev->port, PARPORT_CONTROL_STROBE,
+							PARPORT_CONTROL_INIT);
+		data = parport_read_status(pi->pardev->port);
+		data = ((data & 0x80) >> 1) | ((data & 0x38) >> 3);
+		parport_frob_control(pi->pardev->port, PARPORT_CONTROL_STROBE,
+							PARPORT_CONTROL_STROBE);
+		data |= parport_read_status(pi->pardev->port) & 0xB8;
+		break;
+	case PPCMODE_BI_SW:
+	case PPCMODE_BI_FW:
+		parport_data_reverse(pi->pardev->port);
+		parport_frob_control(pi->pardev->port, PARPORT_CONTROL_STROBE,
+				PARPORT_CONTROL_STROBE | PARPORT_CONTROL_INIT);
+		data = parport_read_data(pi->pardev->port);
+		parport_frob_control(pi->pardev->port, PARPORT_CONTROL_STROBE, 0);
+		parport_data_forward(pi->pardev->port);
+		break;
+	case PPCMODE_EPP_BYTE:
+	case PPCMODE_EPP_WORD:
+	case PPCMODE_EPP_DWORD:
+		pi->pardev->port->ops->epp_read_data(pi->pardev->port, &data, 1, 0);
+		break;
+	}
+
+	return data;
+}
+
+static void bpck6_wr_data_byte(struct pi_adapter *pi, u8 data)
+{
+	switch (mode_map[pi->mode]) {
+	case PPCMODE_UNI_SW:
+	case PPCMODE_UNI_FW:
+	case PPCMODE_BI_SW:
+	case PPCMODE_BI_FW:
+		parport_write_data(pi->pardev->port, data);
+		parport_frob_control(pi->pardev->port, 0, PARPORT_CONTROL_INIT);
+		break;
+	case PPCMODE_EPP_BYTE:
+	case PPCMODE_EPP_WORD:
+	case PPCMODE_EPP_DWORD:
+		pi->pardev->port->ops->epp_write_data(pi->pardev->port, &data, 1, 0);
+		break;
+	}
+}
+
+static int bpck6_read_regr(struct pi_adapter *pi, int cont, int reg)
+{
+	u8 port = cont ? reg | 8 : reg;
+
+	bpck6_send_cmd(pi, port | ACCESS_PORT | ACCESS_READ);
+	return bpck6_rd_data_byte(pi);
+}
+
+static void bpck6_write_regr(struct pi_adapter *pi, int cont, int reg, int val)
+{
+	u8 port = cont ? reg | 8 : reg;
+
+	bpck6_send_cmd(pi, port | ACCESS_PORT | ACCESS_WRITE);
+	bpck6_wr_data_byte(pi, val);
+}
+
+static void bpck6_wait_for_fifo(struct pi_adapter *pi)
+{
+	int i;
+
+	if (pi->private & fifo_wait) {
+		for (i = 0; i < 20; i++)
+			parport_read_status(pi->pardev->port);
+	}
+}
+
+static void bpck6_write_block(struct pi_adapter *pi, char *buf, int len)
+{
+	u8 this, last;
+
+	bpck6_send_cmd(pi, REG_BLKSIZE | ACCESS_REG | ACCESS_WRITE);
+	bpck6_wr_data_byte(pi, (u8)len);
+	bpck6_wr_data_byte(pi, (u8)(len >> 8));
+	bpck6_wr_data_byte(pi, 0);
+
+	bpck6_send_cmd(pi, CMD_PREFIX_SET | PREFIX_IO16 | PREFIX_BLK);
+	bpck6_send_cmd(pi, ATA_REG_DATA | ACCESS_PORT | ACCESS_WRITE);
+
+	switch (mode_map[pi->mode]) {
+	case PPCMODE_UNI_SW:
+	case PPCMODE_BI_SW:
+		while (len--) {
+			parport_write_data(pi->pardev->port, *buf++);
+			parport_frob_control(pi->pardev->port, 0,
+							PARPORT_CONTROL_INIT);
+		}
+		break;
+	case PPCMODE_UNI_FW:
+	case PPCMODE_BI_FW:
+		bpck6_send_cmd(pi, CMD_PREFIX_SET | PREFIX_FASTWR);
+
+		parport_frob_control(pi->pardev->port, PARPORT_CONTROL_STROBE,
+							PARPORT_CONTROL_STROBE);
+
+		last = *buf;
+
+		parport_write_data(pi->pardev->port, last);
+
+		while (len) {
+			this = *buf++;
+			len--;
+
+			if (this == last) {
+				parport_frob_control(pi->pardev->port, 0,
+							PARPORT_CONTROL_INIT);
+			} else {
+				parport_write_data(pi->pardev->port, this);
+				last = this;
+			}
+		}
+
+		parport_frob_control(pi->pardev->port, PARPORT_CONTROL_STROBE,
+							0);
+		bpck6_send_cmd(pi, CMD_PREFIX_RESET | PREFIX_FASTWR);
+		break;
+	case PPCMODE_EPP_BYTE:
+		pi->pardev->port->ops->epp_write_data(pi->pardev->port, buf,
+						len, PARPORT_EPP_FAST_8);
+		bpck6_wait_for_fifo(pi);
+		break;
+	case PPCMODE_EPP_WORD:
+		pi->pardev->port->ops->epp_write_data(pi->pardev->port, buf,
+						len, PARPORT_EPP_FAST_16);
+		bpck6_wait_for_fifo(pi);
+		break;
+	case PPCMODE_EPP_DWORD:
+		pi->pardev->port->ops->epp_write_data(pi->pardev->port, buf,
+						len, PARPORT_EPP_FAST_32);
+		bpck6_wait_for_fifo(pi);
+		break;
+	}
+
+	bpck6_send_cmd(pi, CMD_PREFIX_RESET | PREFIX_IO16 | PREFIX_BLK);
+}
+
+static void bpck6_read_block(struct pi_adapter *pi, char *buf, int len)
+{
+	bpck6_send_cmd(pi, REG_BLKSIZE | ACCESS_REG | ACCESS_WRITE);
+	bpck6_wr_data_byte(pi, (u8)len);
+	bpck6_wr_data_byte(pi, (u8)(len >> 8));
+	bpck6_wr_data_byte(pi, 0);
+
+	bpck6_send_cmd(pi, CMD_PREFIX_SET | PREFIX_IO16 | PREFIX_BLK);
+	bpck6_send_cmd(pi, ATA_REG_DATA | ACCESS_PORT | ACCESS_READ);
+
+	switch (mode_map[pi->mode]) {
+	case PPCMODE_UNI_SW:
+	case PPCMODE_UNI_FW:
+		while (len) {
+			u8 d;
+
+			parport_frob_control(pi->pardev->port,
+					PARPORT_CONTROL_STROBE,
+					PARPORT_CONTROL_INIT); /* DATA STROBE */
+			d = parport_read_status(pi->pardev->port);
+			d = ((d & 0x80) >> 1) | ((d & 0x38) >> 3);
+			parport_frob_control(pi->pardev->port,
+					PARPORT_CONTROL_STROBE,
+					PARPORT_CONTROL_STROBE);
+			d |= parport_read_status(pi->pardev->port) & 0xB8;
+			*buf++ = d;
+			len--;
+		}
+		break;
+	case PPCMODE_BI_SW:
+	case PPCMODE_BI_FW:
+		parport_data_reverse(pi->pardev->port);
+		while (len) {
+			parport_frob_control(pi->pardev->port,
+				PARPORT_CONTROL_STROBE,
+				PARPORT_CONTROL_STROBE | PARPORT_CONTROL_INIT);
+			*buf++ = parport_read_data(pi->pardev->port);
+			len--;
+		}
+		parport_frob_control(pi->pardev->port, PARPORT_CONTROL_STROBE,
+					0);
+		parport_data_forward(pi->pardev->port);
+		break;
+	case PPCMODE_EPP_BYTE:
+		pi->pardev->port->ops->epp_read_data(pi->pardev->port, buf, len,
+						PARPORT_EPP_FAST_8);
+		break;
+	case PPCMODE_EPP_WORD:
+		pi->pardev->port->ops->epp_read_data(pi->pardev->port, buf, len,
+						PARPORT_EPP_FAST_16);
+		break;
+	case PPCMODE_EPP_DWORD:
+		pi->pardev->port->ops->epp_read_data(pi->pardev->port, buf, len,
+						PARPORT_EPP_FAST_32);
+		break;
+	}
+
+	bpck6_send_cmd(pi, CMD_PREFIX_RESET | PREFIX_IO16 | PREFIX_BLK);
+}
+
+static int bpck6_open(struct pi_adapter *pi)
+{
+	u8 i, j, k;
+
+	pi->saved_r0 = parport_read_data(pi->pardev->port);
+	pi->saved_r2 = parport_read_control(pi->pardev->port) & 0x5F;
+
+	parport_frob_control(pi->pardev->port, PARPORT_CONTROL_SELECT,
+						PARPORT_CONTROL_SELECT);
+	if (pi->saved_r0 == 'b')
+		parport_write_data(pi->pardev->port, 'x');
+	parport_write_data(pi->pardev->port, 'b');
+	parport_write_data(pi->pardev->port, 'p');
+	parport_write_data(pi->pardev->port, pi->unit);
+	parport_write_data(pi->pardev->port, ~pi->unit);
+
+	parport_frob_control(pi->pardev->port, PARPORT_CONTROL_SELECT, 0);
+	parport_write_control(pi->pardev->port, PARPORT_CONTROL_INIT);
+
+	i = mode_map[pi->mode] & 0x0C;
+	if (i == 0)
+		i = (mode_map[pi->mode] & 2) | 1;
+	parport_write_data(pi->pardev->port, i);
+
+	parport_frob_control(pi->pardev->port, PARPORT_CONTROL_SELECT,
+						PARPORT_CONTROL_SELECT);
+	parport_frob_control(pi->pardev->port, PARPORT_CONTROL_AUTOFD,
+						PARPORT_CONTROL_AUTOFD);
+
+	j = ((i & 0x08) << 4) | ((i & 0x07) << 3);
+	k = parport_read_status(pi->pardev->port) & 0xB8;
+	if (j != k)
+		goto fail;
+
+	parport_frob_control(pi->pardev->port, PARPORT_CONTROL_AUTOFD, 0);
+	k = (parport_read_status(pi->pardev->port) & 0xB8) ^ 0xB8;
+	if (j != k)
+		goto fail;
+
+	if (i & 4) {
+		/* EPP */
+		parport_frob_control(pi->pardev->port,
+			PARPORT_CONTROL_SELECT | PARPORT_CONTROL_INIT, 0);
+	} else {
+		/* PPC/ECP */
+		parport_frob_control(pi->pardev->port, PARPORT_CONTROL_SELECT, 0);
+	}
+
+	pi->private = 0;
+
+	bpck6_send_cmd(pi, ACCESS_REG | ACCESS_WRITE | REG_RAMSIZE);
+	bpck6_wr_data_byte(pi, RAMSIZE_128K);
+
+	bpck6_send_cmd(pi, ACCESS_REG | ACCESS_READ | REG_VERSION);
+	if ((bpck6_rd_data_byte(pi) & 0x3F) == 0x0C)
+		pi->private |= fifo_wait;
+
+	return 1;
+
+fail:
+	parport_write_control(pi->pardev->port, pi->saved_r2);
+	parport_write_data(pi->pardev->port, pi->saved_r0);
+
+	return 0;
+}
+
+static void bpck6_deselect(struct pi_adapter *pi)
+{
+	if (mode_map[pi->mode] & 4) {
+		/* EPP */
+		parport_frob_control(pi->pardev->port, PARPORT_CONTROL_INIT,
+				     PARPORT_CONTROL_INIT);
+	} else {
+		/* PPC/ECP */
+		parport_frob_control(pi->pardev->port, PARPORT_CONTROL_SELECT,
+				     PARPORT_CONTROL_SELECT);
+	}
+
+	parport_write_data(pi->pardev->port, pi->saved_r0);
+	parport_write_control(pi->pardev->port,
+			pi->saved_r2 | PARPORT_CONTROL_SELECT);
+	parport_write_control(pi->pardev->port, pi->saved_r2);
+}
+
+static void bpck6_wr_extout(struct pi_adapter *pi, u8 regdata)
+{
+	bpck6_send_cmd(pi, REG_VERSION | ACCESS_REG | ACCESS_WRITE);
+	bpck6_wr_data_byte(pi, (u8)((regdata & 0x03) << 6));
+}
+
+static void bpck6_connect(struct pi_adapter *pi)
+{
+	dev_dbg(&pi->dev, "connect\n");
+
+	bpck6_open(pi);
+	bpck6_wr_extout(pi, 0x3);
+}
+
+static void bpck6_disconnect(struct pi_adapter *pi)
+{
+	dev_dbg(&pi->dev, "disconnect\n");
+	bpck6_wr_extout(pi, 0x0);
+	bpck6_deselect(pi);
+}
+
+/* check for 8-bit port */
+static int bpck6_test_port(struct pi_adapter *pi)
+{
+	dev_dbg(&pi->dev, "PARPORT indicates modes=%x for lp=0x%lx\n",
+		pi->pardev->port->modes, pi->pardev->port->base);
+
+	/* look at the parport device to see what modes we can use */
+	if (pi->pardev->port->modes & PARPORT_MODE_EPP)
+		return 5; /* Can do EPP */
+	if (pi->pardev->port->modes & PARPORT_MODE_TRISTATE)
+		return 2;
+	return 1; /* Just flat SPP */
+}
+
+static int bpck6_probe_unit(struct pi_adapter *pi)
+{
+	int out, saved_mode;
+
+	dev_dbg(&pi->dev, "PROBE UNIT %x on port:%x\n", pi->unit, pi->port);
+
+	saved_mode = pi->mode;
+	/*LOWER DOWN TO UNIDIRECTIONAL*/
+	pi->mode = 0;
+
+	out = bpck6_open(pi);
+
+	dev_dbg(&pi->dev, "ppc_open returned %2x\n", out);
+
+	if (out) {
+		bpck6_deselect(pi);
+		dev_dbg(&pi->dev, "leaving probe\n");
+		pi->mode = saved_mode;
+		return 1;
+	}
+
+	dev_dbg(&pi->dev, "Failed open\n");
+	pi->mode = saved_mode;
+
+	return 0;
+}
+
+static void bpck6_log_adapter(struct pi_adapter *pi)
+{
+	char *mode_string[5] = { "4-bit", "8-bit", "EPP-8", "EPP-16", "EPP-32" };
+
+	dev_info(&pi->dev,
+		 "Micro Solutions BACKPACK Drive unit %d at 0x%x, mode:%d (%s), delay %d\n",
+		 pi->unit, pi->port, pi->mode, mode_string[pi->mode], pi->delay);
+}
+
+static struct pi_protocol bpck6 = {
+	.owner		= THIS_MODULE,
+	.name		= "bpck6",
+	.max_mode	= 5,
+	.epp_first	= 2, /* 2-5 use epp (need 8 ports) */
+	.max_units	= 255,
+	.write_regr	= bpck6_write_regr,
+	.read_regr	= bpck6_read_regr,
+	.write_block	= bpck6_write_block,
+	.read_block	= bpck6_read_block,
+	.connect	= bpck6_connect,
+	.disconnect	= bpck6_disconnect,
+	.test_port	= bpck6_test_port,
+	.probe_unit	= bpck6_probe_unit,
+	.log_adapter	= bpck6_log_adapter,
+};
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Micro Solutions Inc.");
+MODULE_DESCRIPTION("Micro Solutions BACKPACK parallel port IDE adapter "
+		   "(version 6 drives) protocol driver");
+module_pata_parport_driver(bpck6);
diff --git a/drivers/ata/pata_parport/comm.c b/drivers/ata/pata_parport/comm.c
new file mode 100644
index 000000000000..94b8d352102e
--- /dev/null
+++ b/drivers/ata/pata_parport/comm.c
@@ -0,0 +1,205 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (c) 1997-1998  Grant R. Guenther <grant@torque.net>
+ *
+ * comm.c is a low-level protocol driver for some older models of the DataStor
+ * "Commuter" parallel to IDE adapter. Some of the parallel port devices
+ * marketed by Arista currently use this adapter.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/wait.h>
+#include <asm/io.h>
+#include "pata_parport.h"
+
+/*
+ * mode codes:  0  nybble reads, 8-bit writes
+ *              1  8-bit reads and writes
+ *              2  8-bit EPP mode
+ */
+
+#define j44(a, b)	(((a >> 3) & 0x0f) | ((b << 1) & 0xf0))
+
+#define P1	w2(5);w2(0xd);w2(0xd);w2(5);w2(4);
+#define P2	w2(5);w2(7);w2(7);w2(5);w2(4);
+
+/*
+ * cont = 0 - access the IDE register file
+ * cont = 1 - access the IDE command set
+ */
+static int  cont_map[2] = { 0x08, 0x10 };
+
+static int comm_read_regr(struct pi_adapter *pi, int cont, int regr)
+{
+	int l, h, r;
+
+	r = regr + cont_map[cont];
+
+	switch (pi->mode) {
+	case 0:
+		w0(r); P1; w0(0);
+		w2(6); l = r1(); w0(0x80); h = r1(); w2(4);
+		return j44(l, h);
+
+	case 1:
+		w0(r+0x20); P1;
+		w0(0); w2(0x26); h = r0(); w2(4);
+		return h;
+
+	case 2:
+	case 3:
+	case 4:
+		w3(r+0x20); (void)r1();
+		w2(0x24); h = r4(); w2(4);
+		return h;
+	}
+
+	return -1;
+}
+
+static void comm_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
+{
+	int r = regr + cont_map[cont];
+
+	switch (pi->mode) {
+	case 0:
+	case 1:
+		w0(r); P1; w0(val); P2;
+		break;
+	case 2:
+	case 3:
+	case 4:
+		w3(r); (void)r1(); w4(val);
+		break;
+	}
+}
+
+static void comm_connect(struct pi_adapter *pi)
+{
+	pi->saved_r0 = r0();
+	pi->saved_r2 = r2();
+	w2(4); w0(0xff); w2(6);
+	w2(4); w0(0xaa); w2(6);
+	w2(4); w0(0x00); w2(6);
+	w2(4); w0(0x87); w2(6);
+	w2(4); w0(0xe0); w2(0xc); w2(0xc); w2(4);
+}
+
+static void comm_disconnect(struct pi_adapter *pi)
+{
+	w2(0); w2(0); w2(0); w2(4);
+	w0(pi->saved_r0);
+	w2(pi->saved_r2);
+}
+
+static void comm_read_block(struct pi_adapter *pi, char *buf, int count)
+{
+	int i, l, h;
+
+	switch (pi->mode) {
+	case 0:
+		w0(0x48); P1;
+		for (i = 0; i < count; i++) {
+			w0(0); w2(6); l = r1();
+			w0(0x80); h = r1(); w2(4);
+			buf[i] = j44(l, h);
+		}
+		break;
+	case 1:
+		w0(0x68); P1; w0(0);
+		for (i = 0; i < count; i++) {
+			w2(0x26);
+			buf[i] = r0();
+			w2(0x24);
+		}
+		w2(4);
+		break;
+	case 2:
+		w3(0x68); (void)r1(); w2(0x24);
+		for (i = 0; i < count; i++)
+			buf[i] = r4();
+		w2(4);
+		break;
+	case 3:
+		w3(0x68); (void)r1(); w2(0x24);
+		for (i = 0; i < count / 2; i++)
+			((u16 *)buf)[i] = r4w();
+		w2(4);
+		break;
+	case 4:
+		w3(0x68); (void)r1(); w2(0x24);
+		for (i = 0; i < count / 4; i++)
+			((u32 *)buf)[i] = r4l();
+		w2(4);
+		break;
+	}
+}
+
+/* NB: Watch out for the byte swapped writes ! */
+static void comm_write_block(struct pi_adapter *pi, char *buf, int count)
+{
+	int k;
+
+	switch (pi->mode) {
+	case 0:
+	case 1:
+		w0(0x68); P1;
+		for (k = 0; k < count; k++) {
+			w2(5);
+			w0(buf[k ^ 1]);
+			w2(7);
+		}
+		w2(5); w2(4);
+		break;
+	case 2:
+		w3(0x48); (void)r1();
+		for (k = 0; k < count; k++)
+			w4(buf[k ^ 1]);
+		break;
+	case 3:
+		w3(0x48); (void)r1();
+		for (k = 0; k < count / 2; k++)
+			w4w(swab16(((u16 *)buf)[k]));
+		break;
+	case 4:
+		w3(0x48); (void)r1();
+		for (k = 0; k < count / 4; k++)
+			w4l(swab16(((u16 *)buf)[2 * k]) |
+			    swab16(((u16 *)buf)[2 * k + 1]) << 16);
+		break;
+	}
+}
+
+static void comm_log_adapter(struct pi_adapter *pi)
+{
+	char *mode_string[5] = { "4-bit", "8-bit", "EPP-8", "EPP-16", "EPP-32" };
+
+	dev_info(&pi->dev,
+		 "DataStor Commuter at 0x%x, mode %d (%s), delay %d\n",
+		 pi->port, pi->mode, mode_string[pi->mode], pi->delay);
+}
+
+static struct pi_protocol comm = {
+	.owner		= THIS_MODULE,
+	.name		= "comm",
+	.max_mode	= 5,
+	.epp_first	= 2,
+	.default_delay	= 1,
+	.max_units	= 1,
+	.write_regr	= comm_write_regr,
+	.read_regr	= comm_read_regr,
+	.write_block	= comm_write_block,
+	.read_block	= comm_read_block,
+	.connect	= comm_connect,
+	.disconnect	= comm_disconnect,
+	.log_adapter	= comm_log_adapter,
+};
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Grant R. Guenther <grant@torque.net>");
+MODULE_DESCRIPTION("DataStor Commuter parallel port IDE adapter protocol driver");
+module_pata_parport_driver(comm);
diff --git a/drivers/ata/pata_parport/dstr.c b/drivers/ata/pata_parport/dstr.c
new file mode 100644
index 000000000000..88930bb1f07e
--- /dev/null
+++ b/drivers/ata/pata_parport/dstr.c
@@ -0,0 +1,235 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (c) 1997-1998  Grant R. Guenther <grant@torque.net>
+ *
+ * dstr.c is a low-level protocol driver for the DataStor EP2000 parallel
+ * to IDE adapter chip.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/wait.h>
+#include <asm/io.h>
+#include "pata_parport.h"
+
+/*
+ * mode codes:  0  nybble reads, 8-bit writes
+ *		1  8-bit reads and writes
+ *		2  8-bit EPP mode
+ *		3  EPP-16
+ *		4  EPP-32
+ */
+
+#define j44(a, b)  (((a >> 3) & 0x07) | ((~a >> 4) & 0x08) | \
+		    ((b << 1) & 0x70) | ((~b) & 0x80))
+
+#define P1	w2(5);w2(0xd);w2(5);w2(4);
+#define P2	w2(5);w2(7);w2(5);w2(4);
+#define P3      w2(6);w2(4);w2(6);w2(4);
+
+/*
+ * cont = 0 - access the IDE register file
+ * cont = 1 - access the IDE command set
+ */
+static int  cont_map[2] = { 0x20, 0x40 };
+
+static int dstr_read_regr(struct pi_adapter *pi, int cont, int regr)
+{
+	int a, b, r;
+
+	r = regr + cont_map[cont];
+
+	w0(0x81); P1;
+	if (pi->mode)
+		w0(0x11);
+	else
+		w0(1);
+	P2; w0(r); P1;
+
+	switch (pi->mode) {
+	case 0:
+		w2(6); a = r1(); w2(4); w2(6); b = r1(); w2(4);
+		return j44(a, b);
+	case 1:
+		w0(0); w2(0x26); a = r0(); w2(4);
+		return a;
+	case 2:
+	case 3:
+	case 4:
+		w2(0x24); a = r4(); w2(4);
+		return a;
+	}
+
+	return -1;
+}
+
+static void dstr_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
+{
+	int  r = regr + cont_map[cont];
+
+	w0(0x81); P1;
+	if (pi->mode >= 2)
+		w0(0x11);
+	else
+		w0(1);
+	P2; w0(r); P1;
+
+	switch (pi->mode)  {
+	case 0:
+	case 1:
+		w0(val); w2(5); w2(7); w2(5); w2(4);
+		break;
+	case 2:
+	case 3:
+	case 4:
+		w4(val);
+		break;
+	}
+}
+
+#define  CCP(x)						\
+	do {						\
+		w0(0xff); w2(0xc); w2(4);		\
+		w0(0xaa); w0(0x55); w0(0); w0(0xff);	\
+		w0(0x87); w0(0x78);			\
+		w0(x); w2(5); w2(4);			\
+	} while (0)
+
+static void dstr_connect(struct pi_adapter *pi)
+{
+	pi->saved_r0 = r0();
+	pi->saved_r2 = r2();
+	w2(4); CCP(0xe0); w0(0xff);
+}
+
+static void dstr_disconnect(struct pi_adapter *pi)
+{
+	CCP(0x30);
+	w0(pi->saved_r0);
+	w2(pi->saved_r2);
+}
+
+static void dstr_read_block(struct pi_adapter *pi, char *buf, int count)
+{
+	int k, a, b;
+
+        w0(0x81); P1;
+	if (pi->mode)
+		w0(0x19);
+	else
+		w0(9);
+	P2; w0(0x82); P1; P3; w0(0x20); P1;
+
+	switch (pi->mode) {
+	case 0:
+		for (k = 0; k < count; k++) {
+			w2(6); a = r1(); w2(4);
+			w2(6); b = r1(); w2(4);
+			buf[k] = j44(a, b);
+		}
+		break;
+	case 1:
+		w0(0);
+		for (k = 0; k < count; k++) {
+			w2(0x26);
+			buf[k] = r0();
+			w2(0x24);
+		}
+		w2(4);
+		break;
+	case 2:
+		w2(0x24);
+		for (k = 0; k < count; k++)
+			buf[k] = r4();
+		w2(4);
+		break;
+	case 3:
+		w2(0x24);
+		for (k = 0; k < count / 2; k++)
+			((u16 *)buf)[k] = r4w();
+		w2(4);
+		break;
+	case 4:
+		w2(0x24);
+		for (k = 0; k < count / 4; k++)
+			((u32 *)buf)[k] = r4l();
+		w2(4);
+		break;
+	}
+}
+
+static void dstr_write_block(struct pi_adapter *pi, char *buf, int count)
+{
+	int k;
+
+	w0(0x81); P1;
+	if (pi->mode)
+		w0(0x19);
+	else
+		w0(9);
+	P2; w0(0x82); P1; P3; w0(0x20); P1;
+
+	switch (pi->mode) {
+	case 0:
+	case 1:
+		for (k = 0; k < count; k++) {
+			w2(5);
+			w0(buf[k]);
+			w2(7);
+		}
+		w2(5); w2(4);
+		break;
+	case 2:
+		w2(0xc5);
+		for (k = 0; k < count; k++)
+			w4(buf[k]);
+		w2(0xc4);
+		break;
+	case 3:
+		w2(0xc5);
+		for (k = 0; k < count / 2; k++)
+			w4w(((u16 *)buf)[k]);
+		w2(0xc4);
+		break;
+	case 4:
+		w2(0xc5);
+		for (k = 0; k < count / 4; k++)
+			w4l(((u32 *)buf)[k]);
+		w2(0xc4);
+		break;
+	}
+}
+
+static void dstr_log_adapter(struct pi_adapter *pi)
+
+{
+	char *mode_string[5] = { "4-bit", "8-bit", "EPP-8", "EPP-16", "EPP-32" };
+
+	dev_info(&pi->dev,
+		 "DataStor EP2000 at 0x%x, mode %d (%s), delay %d\n",
+		 pi->port, pi->mode, mode_string[pi->mode], pi->delay);
+}
+
+static struct pi_protocol dstr = {
+	.owner		= THIS_MODULE,
+	.name		= "dstr",
+	.max_mode	= 5,
+	.epp_first	= 2,
+	.default_delay	= 1,
+	.max_units	= 1,
+	.write_regr	= dstr_write_regr,
+	.read_regr	= dstr_read_regr,
+	.write_block	= dstr_write_block,
+	.read_block	= dstr_read_block,
+	.connect	= dstr_connect,
+	.disconnect	= dstr_disconnect,
+	.log_adapter	= dstr_log_adapter,
+};
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Grant R. Guenther <grant@torque.net>");
+MODULE_DESCRIPTION("DataStor EP2000 parallel port IDE adapter protocol driver");
+module_pata_parport_driver(dstr);
diff --git a/drivers/ata/pata_parport/epat.c b/drivers/ata/pata_parport/epat.c
new file mode 100644
index 000000000000..3cb54fcbf0d0
--- /dev/null
+++ b/drivers/ata/pata_parport/epat.c
@@ -0,0 +1,365 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (c) 1997-1998  Grant R. Guenther <grant@torque.net>
+ *
+ * This is the low level protocol driver for the EPAT parallel
+ * to IDE adapter from Shuttle Technologies.  This adapter is
+ * used in many popular parallel port disk products such as the
+ * SyQuest EZ drives, the Avatar Shark and the Imation SuperDisk.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/wait.h>
+#include <asm/io.h>
+#include "pata_parport.h"
+
+#define j44(a, b)	(((a >> 4) & 0x0f) + (b & 0xf0))
+#define j53(a, b)	(((a >> 3) & 0x1f) + ((b << 4) & 0xe0))
+
+static int epatc8;
+
+module_param(epatc8, int, 0);
+MODULE_PARM_DESC(epatc8,
+		 "support for the Shuttle EP1284 chip, "
+		 "used in any recent Imation SuperDisk (LS-120) drive.");
+
+/*
+ * cont =  0   IDE register file
+ * cont =  1   IDE control registers
+ * cont =  2   internal EPAT registers
+ */
+static int cont_map[3] = { 0x18, 0x10, 0 };
+
+static void epat_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
+{
+	int r = regr + cont_map[cont];
+
+	switch (pi->mode) {
+	case 0:
+	case 1:
+	case 2:
+		w0(0x60+r); w2(1); w0(val); w2(4);
+		break;
+	case 3:
+	case 4:
+	case 5:
+		w3(0x40+r); w4(val);
+		break;
+	}
+}
+
+static int epat_read_regr(struct pi_adapter *pi, int cont, int regr)
+{
+	int  a, b, r;
+
+	r = regr + cont_map[cont];
+
+	switch (pi->mode) {
+
+	case 0:
+		w0(r); w2(1); w2(3);
+		a = r1(); w2(4); b = r1();
+		return j44(a, b);
+	case 1:
+		w0(0x40+r); w2(1); w2(4);
+		a = r1(); b = r2(); w0(0xff);
+		return j53(a, b);
+	case 2:
+		w0(0x20+r); w2(1); w2(0x25);
+		a = r0(); w2(4);
+		return a;
+	case 3:
+	case 4:
+	case 5:
+		w3(r); w2(0x24); a = r4(); w2(4);
+		return a;
+	}
+
+	return -1;	/* never gets here */
+}
+
+static void epat_read_block(struct pi_adapter *pi, char *buf, int count)
+{
+	int  k, ph, a, b;
+
+	switch (pi->mode) {
+
+	case 0:
+		w0(7); w2(1); w2(3); w0(0xff);
+		ph = 0;
+		for (k = 0; k < count; k++) {
+			if (k == count-1)
+				w0(0xfd);
+			w2(6 + ph); a = r1();
+			if (a & 8) {
+				b = a;
+			} else {
+				w2(4+ph); b = r1();
+			}
+			buf[k] = j44(a, b);
+			ph =  1 - ph;
+		}
+		w0(0); w2(4);
+		break;
+
+	case 1:
+		w0(0x47); w2(1); w2(5); w0(0xff);
+		ph = 0;
+		for (k = 0; k < count; k++) {
+			if (k == count - 1)
+				w0(0xfd);
+			w2(4 + ph);
+			a = r1(); b = r2();
+			buf[k] = j53(a, b);
+			ph = 1 - ph;
+		}
+		w0(0); w2(4);
+		break;
+
+	case 2:
+		w0(0x27); w2(1); w2(0x25); w0(0);
+		ph = 0;
+		for (k = 0; k < count - 1; k++) {
+			w2(0x24 + ph);
+			buf[k] = r0();
+			ph = 1 - ph;
+		}
+		w2(0x26); w2(0x27);
+		buf[count - 1] = r0();
+		w2(0x25); w2(4);
+		break;
+
+	case 3:
+		w3(0x80); w2(0x24);
+		for (k = 0; k < count - 1; k++)
+			buf[k] = r4();
+		w2(4); w3(0xa0); w2(0x24);
+		buf[count - 1] = r4();
+		w2(4);
+		break;
+
+	case 4:
+		w3(0x80); w2(0x24);
+		for (k = 0; k < count / 2 - 1; k++)
+			((u16 *)buf)[k] = r4w();
+		buf[count - 2] = r4();
+		w2(4); w3(0xa0); w2(0x24);
+		buf[count - 1] = r4();
+		w2(4);
+		break;
+
+	case 5:
+		w3(0x80); w2(0x24);
+		for (k = 0; k < count / 4 - 1; k++)
+			((u32 *)buf)[k] = r4l();
+		for (k = count - 4; k < count - 1; k++)
+			buf[k] = r4();
+		w2(4); w3(0xa0); w2(0x24);
+		buf[count - 1] = r4();
+		w2(4);
+		break;
+	}
+}
+
+static void epat_write_block(struct pi_adapter *pi, char *buf, int count)
+{
+	int ph, k;
+
+	switch (pi->mode) {
+	case 0:
+	case 1:
+	case 2:
+		w0(0x67); w2(1); w2(5);
+		ph = 0;
+		for (k = 0; k < count; k++) {
+		  	w0(buf[k]);
+			w2(4 + ph);
+			ph = 1 - ph;
+		}
+		w2(7); w2(4);
+		break;
+	case 3:
+		w3(0xc0);
+		for (k = 0; k < count; k++)
+			w4(buf[k]);
+		w2(4);
+		break;
+	case 4:
+		w3(0xc0);
+		for (k = 0; k < count / 2; k++)
+			w4w(((u16 *)buf)[k]);
+		w2(4);
+		break;
+	case 5:
+		w3(0xc0);
+		for (k = 0; k < count / 4; k++)
+			w4l(((u32 *)buf)[k]);
+		w2(4);
+		break;
+	}
+}
+
+/* these macros access the EPAT registers in native addressing */
+
+#define	WR(r, v)	epat_write_regr(pi, 2, r, v)
+#define	RR(r)		epat_read_regr(pi, 2, r)
+
+/* and these access the IDE task file */
+
+#define WRi(r, v)	epat_write_regr(pi, 0, r, v)
+#define RRi(r)		epat_read_regr(pi, 0, r)
+
+/* FIXME:  the CPP stuff should be fixed to handle multiple EPATs on a chain */
+
+#define CPP(x)					\
+	do {					\
+		w2(4); w0(0x22); w0(0xaa);	\
+		w0(0x55); w0(0); w0(0xff);	\
+		w0(0x87); w0(0x78); w0(x);	\
+		w2(4); w2(5); w2(4); w0(0xff);	\
+	} while (0)
+
+static void epat_connect(struct pi_adapter *pi)
+{
+	pi->saved_r0 = r0();
+	pi->saved_r2 = r2();
+
+ 	/* Initialize the chip */
+	CPP(0);
+
+	if (epatc8) {
+		CPP(0x40); CPP(0xe0);
+		w0(0); w2(1); w2(4);
+		WR(0x8, 0x12);
+		WR(0xc, 0x14);
+		WR(0x12, 0x10);
+		WR(0xe, 0xf);
+		WR(0xf, 4);
+		/* WR(0xe,0xa);WR(0xf,4); */
+		WR(0xe, 0xd);
+		WR(0xf, 0);
+		/* CPP(0x30); */
+	}
+
+        /* Connect to the chip */
+	CPP(0xe0);
+	w0(0); w2(1); w2(4); /* Idle into SPP */
+        if (pi->mode >= 3) {
+		w0(0); w2(1); w2(4); w2(0xc);
+		/* Request EPP */
+		w0(0x40); w2(6); w2(7); w2(4); w2(0xc); w2(4);
+        }
+
+	if (!epatc8) {
+		WR(8, 0x10);
+		WR(0xc, 0x14);
+		WR(0xa, 0x38);
+		WR(0x12, 0x10);
+	}
+}
+
+static void epat_disconnect(struct pi_adapter *pi)
+{
+	CPP(0x30);
+	w0(pi->saved_r0);
+	w2(pi->saved_r2);
+}
+
+static int epat_test_proto(struct pi_adapter *pi)
+{
+	int k, j, f, cc;
+	int e[2] = { 0, 0 };
+	char scratch[512];
+
+	epat_connect(pi);
+	cc = RR(0xd);
+	epat_disconnect(pi);
+
+	epat_connect(pi);
+	for (j=0;j<2;j++) {
+		WRi(6, 0xa0 + j * 0x10);
+		for (k = 0; k < 256; k++) {
+			WRi(2, k ^ 0xaa);
+			WRi(3, k ^ 0x55);
+			if (RRi(2) != (k ^ 0xaa))
+				e[j]++;
+		}
+	}
+	epat_disconnect(pi);
+
+	f = 0;
+	epat_connect(pi);
+	WR(0x13, 1); WR(0x13, 0); WR(0xa, 0x11);
+	epat_read_block(pi, scratch, 512);
+
+	for (k = 0; k < 256; k++) {
+		if ((scratch[2 * k] & 0xff) != k)
+			f++;
+		if ((scratch[2 * k + 1] & 0xff) != 0xff - k)
+			f++;
+	}
+	epat_disconnect(pi);
+
+	dev_dbg(&pi->dev,
+		"epat: port 0x%x, mode %d, ccr %x, test=(%d,%d,%d)\n",
+		pi->port, pi->mode, cc, e[0], e[1], f);
+
+	return (e[0] && e[1]) || f;
+}
+
+static void epat_log_adapter(struct pi_adapter *pi)
+{
+	int ver;
+	char *mode_string[6] =
+		{ "4-bit", "5/3", "8-bit", "EPP-8", "EPP-16", "EPP-32" };
+
+	epat_connect(pi);
+	WR(0xa, 0x38);		/* read the version code */
+	ver = RR(0xb);
+	epat_disconnect(pi);
+
+	dev_info(&pi->dev,
+		 "Shuttle EPAT chip %x at 0x%x, mode %d (%s), delay %d\n",
+		 ver, pi->port, pi->mode, mode_string[pi->mode], pi->delay);
+}
+
+static struct pi_protocol epat = {
+	.owner		= THIS_MODULE,
+	.name		= "epat",
+	.max_mode	= 6,
+	.epp_first	= 3,
+	.default_delay	= 1,
+	.max_units	= 1,
+	.write_regr	= epat_write_regr,
+	.read_regr	= epat_read_regr,
+	.write_block	= epat_write_block,
+	.read_block	= epat_read_block,
+	.connect	= epat_connect,
+	.disconnect	= epat_disconnect,
+	.test_proto	= epat_test_proto,
+	.log_adapter	= epat_log_adapter,
+};
+
+static int __init epat_init(void)
+{
+#ifdef CONFIG_PATA_PARPORT_EPATC8
+	epatc8 = 1;
+#endif
+	return pata_parport_register_driver(&epat);
+}
+
+static void __exit epat_exit(void)
+{
+	pata_parport_unregister_driver(&epat);
+}
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Grant R. Guenther <grant@torque.net>");
+MODULE_DESCRIPTION("Shuttle Technologies EPAT parallel port IDE adapter "
+		   "protocol driver");
+module_init(epat_init)
+module_exit(epat_exit)
diff --git a/drivers/ata/pata_parport/epia.c b/drivers/ata/pata_parport/epia.c
new file mode 100644
index 000000000000..7aaba474c671
--- /dev/null
+++ b/drivers/ata/pata_parport/epia.c
@@ -0,0 +1,312 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (c) 1997-1998  Grant R. Guenther <grant@torque.net>
+ *
+ * epia.c is a low-level protocol driver for Shuttle Technologies
+ * EPIA parallel to IDE adapter chip.  This device is now obsolete
+ * and has been replaced with the EPAT chip, which is supported
+ * by epat.c, however, some devices based on EPIA are still
+ * available.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/wait.h>
+#include <asm/io.h>
+#include "pata_parport.h"
+
+/*
+ * mode codes:  0  nybble reads on port 1, 8-bit writes
+ *		1  5/3 reads on ports 1 & 2, 8-bit writes
+ *		2  8-bit reads and writes
+ *		3  8-bit EPP mode
+ *		4  16-bit EPP
+ *		5  32-bit EPP
+ */
+
+#define j44(a, b)	(((a >> 4) & 0x0f) + (b & 0xf0))
+#define j53(a, b)	(((a >> 3) & 0x1f) + ((b << 4) & 0xe0))
+
+/*
+ * cont =  0   IDE register file
+ * cont =  1   IDE control registers
+ */
+static int cont_map[2] = { 0, 0x80 };
+
+static int epia_read_regr(struct pi_adapter *pi, int cont, int regr)
+{
+	int a, b, r;
+
+	regr += cont_map[cont];
+
+	switch (pi->mode)  {
+	case 0:
+		r = regr ^ 0x39;
+		w0(r); w2(1); w2(3); w0(r);
+		a = r1(); w2(1); b = r1(); w2(4);
+		return j44(a, b);
+	case 1:
+		r = regr ^ 0x31;
+		w0(r); w2(1); w0(r & 0x37);
+		w2(3); w2(5); w0(r | 0xf0);
+		a = r1(); b = r2(); w2(4);
+		return j53(a, b);
+	case 2:
+		r = regr^0x29;
+		w0(r); w2(1); w2(0X21); w2(0x23);
+		a = r0(); w2(4);
+		return a;
+	case 3:
+	case 4:
+	case 5:
+		w3(regr); w2(0x24); a = r4(); w2(4);
+		return a;
+	}
+
+	return -1;
+}
+
+static void epia_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
+{
+	int  r;
+
+	regr += cont_map[cont];
+
+	switch (pi->mode)  {
+	case 0:
+	case 1:
+	case 2:
+		r = regr ^ 0x19;
+		w0(r); w2(1); w0(val); w2(3); w2(4);
+		break;
+	case 3:
+	case 4:
+	case 5:
+		r = regr ^ 0x40;
+		w3(r); w4(val); w2(4);
+		break;
+	}
+}
+
+#define WR(r, v)	epia_write_regr(pi, 0, r, v)
+#define RR(r)		epia_read_regr(pi, 0, r)
+
+/*
+ * The use of register 0x84 is entirely unclear - it seems to control
+ * some EPP counters ...  currently we know about 3 different block
+ * sizes:  the standard 512 byte reads and writes, 12 byte writes and
+ * 2048 byte reads (the last two being used in the CDrom drivers.
+ */
+static void epia_connect(struct pi_adapter *pi)
+{
+	pi->saved_r0 = r0();
+	pi->saved_r2 = r2();
+
+	w2(4); w0(0xa0); w0(0x50); w0(0xc0); w0(0x30); w0(0xa0); w0(0);
+	w2(1); w2(4);
+	if (pi->mode >= 3) {
+		w0(0xa); w2(1); w2(4); w0(0x82); w2(4); w2(0xc); w2(4);
+		w2(0x24); w2(0x26); w2(4);
+	}
+	WR(0x86, 8);
+}
+
+static void epia_disconnect(struct pi_adapter *pi)
+{
+	/* WR(0x84,0x10); */
+	w0(pi->saved_r0);
+	w2(1); w2(4);
+	w0(pi->saved_r0);
+	w2(pi->saved_r2);
+}
+
+static void epia_read_block(struct pi_adapter *pi, char *buf, int count)
+
+{
+	int k, ph, a, b;
+
+	switch (pi->mode) {
+	case 0:
+		w0(0x81); w2(1); w2(3); w0(0xc1);
+		ph = 1;
+		for (k = 0; k < count; k++) {
+			w2(2+ph); a = r1();
+			w2(4+ph); b = r1();
+			buf[k] = j44(a, b);
+			ph = 1 - ph;
+		}
+		w0(0); w2(4);
+		break;
+	case 1:
+		w0(0x91); w2(1); w0(0x10); w2(3);
+		w0(0x51); w2(5); w0(0xd1);
+		ph = 1;
+		for (k = 0; k < count; k++) {
+			w2(4 + ph);
+			a = r1(); b = r2();
+			buf[k] = j53(a, b);
+			ph = 1 - ph;
+		}
+		w0(0); w2(4);
+		break;
+	case 2:
+		w0(0x89); w2(1); w2(0x23); w2(0x21);
+		ph = 1;
+		for (k = 0; k < count; k++) {
+			w2(0x24 + ph);
+			buf[k] = r0();
+			ph = 1 - ph;
+		}
+		w2(6); w2(4);
+		break;
+	case 3:
+		if (count > 512)
+			WR(0x84, 3);
+		w3(0); w2(0x24);
+		for (k = 0; k < count; k++)
+			buf[k] = r4();
+		w2(4); WR(0x84, 0);
+		break;
+	case 4:
+		if (count > 512)
+			WR(0x84, 3);
+		w3(0); w2(0x24);
+		for (k = 0; k < count / 2; k++)
+			((u16 *)buf)[k] = r4w();
+		w2(4); WR(0x84, 0);
+		break;
+	case 5:
+		if (count > 512)
+			WR(0x84, 3);
+		w3(0); w2(0x24);
+		for (k = 0; k < count / 4; k++)
+			((u32 *)buf)[k] = r4l();
+		w2(4); WR(0x84, 0);
+		break;
+	}
+}
+
+static void epia_write_block(struct pi_adapter *pi, char *buf, int count)
+{
+	int ph, k, last, d;
+
+	switch (pi->mode) {
+	case 0:
+	case 1:
+	case 2:
+		w0(0xa1); w2(1); w2(3); w2(1); w2(5);
+		ph = 0;  last = 0x8000;
+		for (k = 0; k < count; k++) {
+			d = buf[k];
+			if (d != last) {
+				last = d;
+				w0(d);
+			}
+			w2(4 + ph);
+			ph = 1 - ph;
+		}
+		w2(7); w2(4);
+		break;
+	case 3:
+		if (count < 512)
+			WR(0x84, 1);
+		w3(0x40);
+		for (k = 0; k < count; k++)
+			w4(buf[k]);
+		if (count < 512)
+			WR(0x84, 0);
+		break;
+	case 4:
+		if (count < 512)
+			WR(0x84, 1);
+		w3(0x40);
+		for (k = 0; k < count / 2; k++)
+			w4w(((u16 *)buf)[k]);
+		if (count < 512)
+			WR(0x84, 0);
+		break;
+	case 5:
+		if (count < 512)
+			WR(0x84, 1);
+		w3(0x40);
+		for (k = 0; k < count / 4; k++)
+			w4l(((u32 *)buf)[k]);
+		if (count < 512)
+			WR(0x84, 0);
+		break;
+	}
+}
+
+static int epia_test_proto(struct pi_adapter *pi)
+{
+	int j, k, f;
+	int e[2] = { 0, 0 };
+	char scratch[512];
+
+	epia_connect(pi);
+	for (j = 0; j < 2; j++) {
+		WR(6, 0xa0 + j * 0x10);
+		for (k = 0; k < 256; k++) {
+			WR(2, k ^ 0xaa);
+			WR(3, k ^ 0x55);
+			if (RR(2) != (k ^ 0xaa))
+				e[j]++;
+		}
+		WR(2, 1); WR(3, 1);
+	}
+	epia_disconnect(pi);
+
+	f = 0;
+	epia_connect(pi);
+	WR(0x84, 8);
+	epia_read_block(pi, scratch, 512);
+	for (k = 0; k < 256; k++) {
+		if ((scratch[2 * k] & 0xff) != ((k + 1) & 0xff))
+			f++;
+		if ((scratch[2 * k + 1] & 0xff) != ((-2 - k) & 0xff))
+			f++;
+	}
+	WR(0x84, 0);
+	epia_disconnect(pi);
+
+	dev_dbg(&pi->dev, "epia: port 0x%x, mode %d, test=(%d,%d,%d)\n",
+		pi->port, pi->mode, e[0], e[1], f);
+
+	return (e[0] && e[1]) || f;
+}
+
+
+static void epia_log_adapter(struct pi_adapter *pi)
+{
+	char *mode[6] = { "4-bit", "5/3", "8-bit", "EPP-8", "EPP-16", "EPP-32"};
+
+	dev_info(&pi->dev,
+		 "Shuttle EPIA at 0x%x, mode %d (%s), delay %d\n",
+		 pi->port, pi->mode, mode[pi->mode], pi->delay);
+}
+
+static struct pi_protocol epia = {
+	.owner		= THIS_MODULE,
+	.name		= "epia",
+	.max_mode	= 6,
+	.epp_first	= 3,
+	.default_delay	= 1,
+	.max_units	= 1,
+	.write_regr	= epia_write_regr,
+	.read_regr	= epia_read_regr,
+	.write_block	= epia_write_block,
+	.read_block	= epia_read_block,
+	.connect	= epia_connect,
+	.disconnect	= epia_disconnect,
+	.test_proto	= epia_test_proto,
+	.log_adapter	= epia_log_adapter,
+};
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Grant R. Guenther <grant@torque.net>");
+MODULE_DESCRIPTION("Shuttle Technologies EPIA parallel port IDE adapter "
+		   "protocol driver");
+module_pata_parport_driver(epia);
diff --git a/drivers/ata/pata_parport/fit2.c b/drivers/ata/pata_parport/fit2.c
new file mode 100644
index 000000000000..de79cf91ad5f
--- /dev/null
+++ b/drivers/ata/pata_parport/fit2.c
@@ -0,0 +1,138 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (c) 1998  Grant R. Guenther <grant@torque.net>
+ *
+ * fit2.c is a low-level protocol driver for the older version
+ * of the Fidelity International Technology parallel port adapter.
+ * This adapter is used in their TransDisk 2000 and older TransDisk
+ * 3000 portable hard-drives.  As far as I can tell, this device
+ * supports 4-bit mode _only_.
+ *
+ * Newer models of the FIT products use an enhanced protocol.
+ * The "fit3" protocol module should support current drives.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/wait.h>
+#include <asm/io.h>
+#include "pata_parport.h"
+
+#define j44(a, b)	(((a >> 4) & 0x0f) | (b & 0xf0))
+
+/*
+ * cont = 0 - access the IDE register file
+ * cont = 1 - access the IDE command set
+ *
+ * NB: The FIT adapter does not appear to use the control registers.
+ * So, we map ALT_STATUS to STATUS and NO-OP writes to the device
+ * control register - this means that IDE reset will not work on these
+ * devices.
+ */
+
+static void fit2_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
+{
+	if (cont == 1)
+		return;
+	w2(0xc); w0(regr); w2(4); w0(val); w2(5); w0(0); w2(4);
+}
+
+static int fit2_read_regr(struct pi_adapter *pi, int cont, int regr)
+{
+	int  a, b, r;
+
+	if (cont) {
+		if (regr != 6)
+			return 0xff;
+		r = 7;
+	} else {
+		r = regr + 0x10;
+	}
+
+	w2(0xc); w0(r); w2(4); w2(5);
+	w0(0); a = r1();
+	w0(1); b = r1();
+	w2(4);
+
+	return j44(a, b);
+}
+
+static void fit2_read_block(struct pi_adapter *pi, char *buf, int count)
+{
+	int  k, a, b, c, d;
+
+	w2(0xc); w0(0x10);
+
+	for (k = 0; k < count / 4; k++) {
+		w2(4); w2(5);
+		w0(0); a = r1(); w0(1); b = r1();
+		w0(3); c = r1(); w0(2); d = r1();
+		buf[4 * k + 0] = j44(a, b);
+		buf[4 * k + 1] = j44(d, c);
+
+		w2(4); w2(5);
+		a = r1(); w0(3); b = r1();
+		w0(1); c = r1(); w0(0); d = r1();
+		buf[4 * k + 2] = j44(d, c);
+		buf[4 * k + 3] = j44(a, b);
+	}
+
+	w2(4);
+}
+
+static void fit2_write_block(struct pi_adapter *pi, char *buf, int count)
+{
+	int k;
+
+	w2(0xc); w0(0);
+	for (k = 0; k < count / 2; k++) {
+		w2(4); w0(buf[2 * k]);
+		w2(5); w0(buf[2 * k + 1]);
+	}
+	w2(4);
+}
+
+static void fit2_connect(struct pi_adapter *pi)
+{
+	pi->saved_r0 = r0();
+	pi->saved_r2 = r2();
+	w2(0xcc);
+}
+
+static void fit2_disconnect(struct pi_adapter *pi)
+{
+	w0(pi->saved_r0);
+	w2(pi->saved_r2);
+}
+
+static void fit2_log_adapter(struct pi_adapter *pi)
+{
+	dev_info(&pi->dev, "FIT 2000 adapter at 0x%x, delay %d\n",
+		 pi->port, pi->delay);
+
+}
+
+static struct pi_protocol fit2 = {
+	.owner		= THIS_MODULE,
+	.name		= "fit2",
+	.max_mode	= 1,
+	.epp_first	= 2,
+	.default_delay	= 1,
+	.max_units	= 1,
+	.write_regr	= fit2_write_regr,
+	.read_regr	= fit2_read_regr,
+	.write_block	= fit2_write_block,
+	.read_block	= fit2_read_block,
+	.connect	= fit2_connect,
+	.disconnect	= fit2_disconnect,
+	.log_adapter	= fit2_log_adapter,
+};
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Grant R. Guenther <grant@torque.net>");
+MODULE_DESCRIPTION("Fidelity International Technology parallel port IDE adapter"
+		   "(older models) protocol driver");
+module_pata_parport_driver(fit2);
diff --git a/drivers/ata/pata_parport/fit3.c b/drivers/ata/pata_parport/fit3.c
new file mode 100644
index 000000000000..d2b81cf2e16d
--- /dev/null
+++ b/drivers/ata/pata_parport/fit3.c
@@ -0,0 +1,189 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (c) 1998  Grant R. Guenther <grant@torque.net>
+ *
+ * fit3.c is a low-level protocol driver for newer models
+ * of the Fidelity International Technology parallel port adapter.
+ * This adapter is used in their TransDisk 3000 portable
+ * hard-drives, as well as CD-ROM, PD-CD and other devices.
+ *
+ * The TD-2000 and certain older devices use a different protocol.
+ * Try the fit2 protocol module with them.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/wait.h>
+#include <asm/io.h>
+#include "pata_parport.h"
+
+#define j44(a, b)	(((a >> 3) & 0x0f) | ((b << 1) & 0xf0))
+
+#define w7(byte)	out_p(7, byte)
+#define r7()		(in_p(7) & 0xff)
+
+/*
+ * cont = 0 - access the IDE register file
+ * cont = 1 - access the IDE command set
+ */
+
+static void fit3_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
+{
+	regr += cont << 3;
+
+	switch (pi->mode) {
+	case 0:
+	case 1:
+		w2(0xc); w0(regr); w2(0x8); w2(0xc);
+		w0(val); w2(0xd);
+		w0(0);   w2(0xc);
+		break;
+	case 2:
+		w2(0xc); w0(regr); w2(0x8); w2(0xc);
+		w4(val); w4(0);
+		w2(0xc);
+		break;
+	}
+}
+
+static int fit3_read_regr(struct pi_adapter *pi, int cont, int regr)
+{
+	int  a, b;
+
+	regr += cont << 3;
+
+	switch (pi->mode) {
+	case 0:
+		w2(0xc); w0(regr + 0x10); w2(0x8); w2(0xc);
+		w2(0xd); a = r1();
+		w2(0xf); b = r1();
+		w2(0xc);
+		return j44(a, b);
+	case 1:
+		w2(0xc); w0(regr + 0x90); w2(0x8); w2(0xc);
+		w2(0xec); w2(0xee); w2(0xef); a = r0();
+		w2(0xc);
+		return a;
+	case 2:
+		w2(0xc); w0(regr + 0x90); w2(0x8); w2(0xc);
+		w2(0xec);
+		a = r4(); b = r4();
+		w2(0xc);
+		return a;
+	}
+
+	return -1;
+}
+
+static void fit3_read_block(struct pi_adapter *pi, char *buf, int count)
+{
+	int  k, a, b, c, d;
+
+	switch (pi->mode) {
+	case 0:
+		w2(0xc); w0(0x10); w2(0x8); w2(0xc);
+		for (k = 0; k < count / 2; k++) {
+			w2(0xd); a = r1();
+			w2(0xf); b = r1();
+			w2(0xc); c = r1();
+			w2(0xe); d = r1();
+			buf[2 * k] = j44(a, b);
+			buf[2 * k + 1] = j44(c, d);
+		}
+		w2(0xc);
+		break;
+	case 1:
+		w2(0xc); w0(0x90); w2(0x8); w2(0xc);
+		w2(0xec); w2(0xee);
+		for (k = 0; k < count / 2; k++) {
+			w2(0xef); a = r0();
+			w2(0xee); b = r0();
+			buf[2 * k] = a;
+			buf[2 * k + 1] = b;
+		}
+		w2(0xec);
+		w2(0xc);
+		break;
+	case 2:
+		w2(0xc); w0(0x90); w2(0x8); w2(0xc);
+		w2(0xec);
+		for (k = 0; k < count; k++)
+			buf[k] = r4();
+		w2(0xc);
+		break;
+	}
+}
+
+static void fit3_write_block(struct pi_adapter *pi, char *buf, int count)
+{
+	int k;
+
+	switch (pi->mode) {
+	case 0:
+	case 1:
+		w2(0xc); w0(0); w2(0x8); w2(0xc);
+		for (k = 0; k < count / 2; k++) {
+			w0(buf[2 * k]); w2(0xd);
+			w0(buf[2 * k + 1]); w2(0xc);
+		}
+		break;
+	case 2:
+		w2(0xc); w0(0); w2(0x8); w2(0xc);
+		for (k = 0; k < count; k++)
+			w4(buf[k]);
+		w2(0xc);
+		break;
+	}
+}
+
+static void fit3_connect(struct pi_adapter *pi)
+{
+	pi->saved_r0 = r0();
+	pi->saved_r2 = r2();
+	w2(0xc); w0(0); w2(0xa);
+	if (pi->mode == 2) {
+		w2(0xc); w0(0x9);
+		w2(0x8); w2(0xc);
+	}
+}
+
+static void fit3_disconnect(struct pi_adapter *pi)
+{
+	w2(0xc); w0(0xa); w2(0x8); w2(0xc);
+	w0(pi->saved_r0);
+	w2(pi->saved_r2);
+}
+
+static void fit3_log_adapter(struct pi_adapter *pi)
+{
+	char *mode_string[3] = { "4-bit", "8-bit", "EPP"};
+
+	dev_info(&pi->dev,
+		 "FIT 3000 adapter at 0x%x, mode %d (%s), delay %d\n",
+		 pi->port, pi->mode, mode_string[pi->mode], pi->delay);
+}
+
+static struct pi_protocol fit3 = {
+	.owner		= THIS_MODULE,
+	.name		= "fit3",
+	.max_mode	= 3,
+	.epp_first	= 2,
+	.default_delay	= 1,
+	.max_units	= 1,
+	.write_regr	= fit3_write_regr,
+	.read_regr	= fit3_read_regr,
+	.write_block	= fit3_write_block,
+	.read_block	= fit3_read_block,
+	.connect	= fit3_connect,
+	.disconnect	= fit3_disconnect,
+	.log_adapter	= fit3_log_adapter,
+};
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Grant R. Guenther <grant@torque.net>");
+MODULE_DESCRIPTION("Fidelity International Technology parallel port IDE adapter"
+		   "(newer models) protocol driver");
+module_pata_parport_driver(fit3);
diff --git a/drivers/ata/pata_parport/friq.c b/drivers/ata/pata_parport/friq.c
new file mode 100644
index 000000000000..7abe2ff40685
--- /dev/null
+++ b/drivers/ata/pata_parport/friq.c
@@ -0,0 +1,264 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (c) 1998    Grant R. Guenther <grant@torque.net>
+ *
+ * friq.c is a low-level protocol driver for the Freecom "IQ"
+ * parallel port IDE adapter.   Early versions of this adapter
+ * use the 'frpw' protocol.
+ *
+ * Freecom uses this adapter in a battery powered external
+ * CD-ROM drive.  It is also used in LS-120 drives by
+ * Maxell and Panasonic, and other devices.
+ *
+ * The battery powered drive requires software support to
+ * control the power to the drive.  This module enables the
+ * drive power when the high level driver (pcd) is loaded
+ * and disables it when the module is unloaded.  Note, if
+ * the friq module is built in to the kernel, the power
+ * will never be switched off, so other means should be
+ * used to conserve battery power.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/wait.h>
+#include <asm/io.h>
+#include "pata_parport.h"
+
+#define CMD(x)							\
+	do {							\
+		w2(4); w0(0xff); w0(0xff); w0(0x73); w0(0x73);	\
+		w0(0xc9); w0(0xc9); w0(0x26);			\
+		w0(0x26); w0(x); w0(x);				\
+	} while (0)
+
+#define j44(l, h)	(((l >> 4) & 0x0f) | (h & 0xf0))
+
+/*
+ * cont = 0 - access the IDE register file
+ * cont = 1 - access the IDE command set
+ */
+static int cont_map[2] = { 0x08, 0x10 };
+
+static int friq_read_regr(struct pi_adapter *pi, int cont, int regr)
+{
+	int h, l, r;
+
+	r = regr + cont_map[cont];
+
+	CMD(r);
+	w2(6); l = r1();
+	w2(4); h = r1();
+	w2(4);
+
+	return j44(l, h);
+}
+
+static void friq_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
+{
+	int r = regr + cont_map[cont];
+
+	CMD(r);
+	w0(val);
+	w2(5); w2(7); w2(5); w2(4);
+}
+
+static void friq_read_block_int(struct pi_adapter *pi, char *buf, int count, int regr)
+{
+	int h, l, k, ph;
+
+	switch (pi->mode) {
+	case 0:
+		CMD(regr);
+		for (k = 0; k < count; k++) {
+			w2(6); l = r1();
+			w2(4); h = r1();
+			buf[k] = j44(l, h);
+		}
+		w2(4);
+		break;
+	case 1:
+		ph = 2;
+		CMD(regr + 0xc0);
+		w0(0xff);
+		for (k = 0; k < count; k++) {
+			w2(0xa4 + ph);
+			buf[k] = r0();
+			ph = 2 - ph;
+		}
+		w2(0xac); w2(0xa4); w2(4);
+		break;
+	case 2:
+		CMD(regr + 0x80);
+		for (k = 0; k < count - 2; k++)
+			buf[k] = r4();
+		w2(0xac); w2(0xa4);
+		buf[count - 2] = r4();
+		buf[count - 1] = r4();
+		w2(4);
+		break;
+	case 3:
+		CMD(regr + 0x80);
+		for (k = 0; k < count / 2 - 1; k++)
+			((u16 *)buf)[k] = r4w();
+		w2(0xac); w2(0xa4);
+		buf[count - 2] = r4();
+		buf[count - 1] = r4();
+		w2(4);
+		break;
+	case 4:
+		CMD(regr + 0x80);
+		for (k = 0; k < count / 4 - 1; k++)
+			((u32 *)buf)[k] = r4l();
+		buf[count - 4] = r4();
+		buf[count - 3] = r4();
+		w2(0xac); w2(0xa4);
+		buf[count - 2] = r4();
+		buf[count - 1] = r4();
+		w2(4);
+		break;
+	}
+}
+
+static void friq_read_block(struct pi_adapter *pi, char *buf, int count)
+{
+	friq_read_block_int(pi, buf, count, 0x08);
+}
+
+static void friq_write_block(struct pi_adapter *pi, char *buf, int count)
+{
+	int k;
+
+	switch (pi->mode) {
+	case 0:
+	case 1:
+		CMD(8); w2(5);
+		for (k = 0; k < count; k++) {
+			w0(buf[k]);
+			w2(7); w2(5);
+		}
+		w2(4);
+		break;
+	case 2:
+		CMD(0xc8); w2(5);
+		for (k = 0; k < count; k++)
+			w4(buf[k]);
+		w2(4);
+		break;
+	case 3:
+		CMD(0xc8); w2(5);
+		for (k = 0; k < count / 2; k++)
+			w4w(((u16 *)buf)[k]);
+		w2(4);
+		break;
+	case 4:
+		CMD(0xc8); w2(5);
+		for (k = 0; k < count / 4; k++)
+			w4l(((u32 *)buf)[k]);
+		w2(4);
+		break;
+}
+}
+
+static void friq_connect(struct pi_adapter *pi)
+{
+	pi->saved_r0 = r0();
+	pi->saved_r2 = r2();
+	w2(4);
+}
+
+static void friq_disconnect(struct pi_adapter *pi)
+{
+	CMD(0x20);
+	w0(pi->saved_r0);
+	w2(pi->saved_r2);
+}
+
+static int friq_test_proto(struct pi_adapter *pi)
+{
+	int j, k, r;
+	int e[2] = { 0, 0 };
+	char scratch[512];
+
+	pi->saved_r0 = r0();
+	w0(0xff); udelay(20); CMD(0x3d); /* turn the power on */
+	udelay(500);
+	w0(pi->saved_r0);
+
+	friq_connect(pi);
+	for (j = 0; j < 2; j++) {
+		friq_write_regr(pi, 0, 6, 0xa0 + j * 0x10);
+		for (k = 0; k < 256; k++) {
+			friq_write_regr(pi, 0, 2, k ^ 0xaa);
+			friq_write_regr(pi, 0, 3, k ^ 0x55);
+			if (friq_read_regr(pi, 0, 2) != (k ^ 0xaa))
+				e[j]++;
+		}
+	}
+	friq_disconnect(pi);
+
+	friq_connect(pi);
+	friq_read_block_int(pi, scratch, 512, 0x10);
+	r = 0;
+	for (k = 0; k < 128; k++) {
+		if (scratch[k] != k)
+			r++;
+	}
+	friq_disconnect(pi);
+
+	dev_dbg(&pi->dev,
+		"friq: port 0x%x, mode %d, test=(%d,%d,%d)\n",
+		pi->port, pi->mode, e[0], e[1], r);
+
+	return r || (e[0] && e[1]);
+}
+
+static void friq_log_adapter(struct pi_adapter *pi)
+{
+	char *mode_string[6] = { "4-bit", "8-bit", "EPP-8", "EPP-16", "EPP-32"};
+
+	dev_info(&pi->dev,
+		 "Freecom IQ ASIC-2 adapter at 0x%x, mode %d (%s), delay %d\n",
+		 pi->port, pi->mode, mode_string[pi->mode], pi->delay);
+
+	pi->private = 1;
+	friq_connect(pi);
+	CMD(0x9e);  		/* disable sleep timer */
+	friq_disconnect(pi);
+}
+
+static void friq_release_proto(struct pi_adapter *pi)
+{
+	if (pi->private) {		/* turn off the power */
+		friq_connect(pi);
+		CMD(0x1d); CMD(0x1e);
+		friq_disconnect(pi);
+		pi->private = 0;
+	}
+}
+
+static struct pi_protocol friq = {
+	.owner		= THIS_MODULE,
+	.name		= "friq",
+	.max_mode	= 5,
+	.epp_first	= 2,
+	.default_delay	= 1,
+	.max_units	= 1,
+	.write_regr	= friq_write_regr,
+	.read_regr	= friq_read_regr,
+	.write_block	= friq_write_block,
+	.read_block	= friq_read_block,
+	.connect	= friq_connect,
+	.disconnect	= friq_disconnect,
+	.test_proto	= friq_test_proto,
+	.log_adapter	= friq_log_adapter,
+	.release_proto	= friq_release_proto,
+};
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Grant R. Guenther <grant@torque.net>");
+MODULE_DESCRIPTION("Freecom IQ parallel port IDE adapter protocol driver");
+module_pata_parport_driver(friq);
diff --git a/drivers/ata/pata_parport/frpw.c b/drivers/ata/pata_parport/frpw.c
new file mode 100644
index 000000000000..7fa9b9857321
--- /dev/null
+++ b/drivers/ata/pata_parport/frpw.c
@@ -0,0 +1,298 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (c) 1996-1998  Grant R. Guenther <grant@torque.net>
+ *
+ * frpw.c is a low-level protocol driver for the Freecom "Power" parallel port
+ * IDE adapter.
+ *
+ * Some applications of this adapter may require a "printer" reset prior to
+ * loading the driver.  This can be done by loading and unloading the "lp"
+ * driver, or it can be done by this driver if you define FRPW_HARD_RESET.
+ * The latter is not recommended as it may upset devices on other ports.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/wait.h>
+#include <asm/io.h>
+#include "pata_parport.h"
+
+#define cec4		w2(0xc);w2(0xe);w2(0xe);w2(0xc);w2(4);w2(4);w2(4);
+#define j44(l,h)	(((l>>4)&0x0f)|(h&0xf0))
+
+/*
+ * cont = 0 - access the IDE register file
+ * cont = 1 - access the IDE command set
+ */
+static int  cont_map[2] = { 0x08, 0x10 };
+
+static int frpw_read_regr(struct pi_adapter *pi, int cont, int regr)
+{
+	int h, l, r;
+
+	r = regr + cont_map[cont];
+
+	w2(4);
+	w0(r); cec4;
+	w2(6); l = r1();
+	w2(4); h = r1();
+	w2(4);
+
+	return j44(l, h);
+}
+
+static void frpw_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
+{
+	int r = regr + cont_map[cont];
+
+	w2(4); w0(r); cec4;
+	w0(val);
+	w2(5); w2(7); w2(5); w2(4);
+}
+
+static void frpw_read_block_int(struct pi_adapter *pi, char *buf, int count,
+				int regr)
+{
+	int h, l, k, ph;
+
+	switch (pi->mode) {
+	case 0:
+		w2(4); w0(regr); cec4;
+		for (k = 0; k < count; k++) {
+			w2(6); l = r1();
+			w2(4); h = r1();
+			buf[k] = j44(l, h);
+		}
+		w2(4);
+		break;
+
+	case 1:
+		ph = 2;
+		w2(4); w0(regr + 0xc0); cec4;
+		w0(0xff);
+		for (k = 0; k < count; k++) {
+			w2(0xa4 + ph);
+			buf[k] = r0();
+			ph = 2 - ph;
+		}
+		w2(0xac); w2(0xa4); w2(4);
+		break;
+
+	case 2:
+		w2(4); w0(regr + 0x80); cec4;
+		for (k = 0; k < count; k++)
+			buf[k] = r4();
+		w2(0xac); w2(0xa4);
+		w2(4);
+		break;
+
+	case 3:
+		w2(4); w0(regr + 0x80); cec4;
+		for (k = 0; k < count - 2; k++)
+			buf[k] = r4();
+		w2(0xac); w2(0xa4);
+		buf[count - 2] = r4();
+		buf[count - 1] = r4();
+		w2(4);
+		break;
+
+	case 4:
+		w2(4); w0(regr + 0x80); cec4;
+		for (k = 0; k < count / 2 - 1; k++)
+			((u16 *)buf)[k] = r4w();
+		w2(0xac); w2(0xa4);
+		buf[count - 2] = r4();
+		buf[count - 1] = r4();
+		w2(4);
+		break;
+
+	case 5:
+		w2(4); w0(regr + 0x80); cec4;
+		for (k = 0; k < count / 4 - 1; k++)
+			((u32 *)buf)[k] = r4l();
+		buf[count - 4] = r4();
+		buf[count - 3] = r4();
+		w2(0xac); w2(0xa4);
+		buf[count - 2] = r4();
+		buf[count - 1] = r4();
+		w2(4);
+		break;
+        }
+}
+
+static void frpw_read_block(struct pi_adapter *pi, char *buf, int count)
+{
+	frpw_read_block_int(pi, buf, count, 0x08);
+}
+
+static void frpw_write_block(struct pi_adapter *pi, char *buf, int count)
+{
+	int k;
+
+	switch (pi->mode) {
+	case 0:
+	case 1:
+	case 2:
+		w2(4); w0(8); cec4; w2(5);
+		for (k = 0; k < count; k++) {
+			w0(buf[k]);
+			w2(7); w2(5);
+		}
+		w2(4);
+		break;
+
+	case 3:
+		w2(4); w0(0xc8); cec4; w2(5);
+		for (k = 0; k < count; k++)
+			w4(buf[k]);
+		w2(4);
+		break;
+
+	case 4:
+		w2(4); w0(0xc8); cec4; w2(5);
+		for (k = 0; k < count / 2; k++)
+			w4w(((u16 *)buf)[k]);
+		w2(4);
+		break;
+
+	case 5:
+		w2(4); w0(0xc8); cec4; w2(5);
+		for (k = 0; k < count / 4; k++)
+			w4l(((u32 *)buf)[k]);
+		w2(4);
+		break;
+	}
+}
+
+static void frpw_connect(struct pi_adapter *pi)
+{
+	pi->saved_r0 = r0();
+	pi->saved_r2 = r2();
+	w2(4);
+}
+
+static void frpw_disconnect(struct pi_adapter *pi)
+{
+	w2(4); w0(0x20); cec4;
+	w0(pi->saved_r0);
+	w2(pi->saved_r2);
+}
+
+/*
+ * Stub logic to see if PNP string is available - used to distinguish
+ * between the Xilinx and ASIC implementations of the Freecom adapter.
+ * returns chip_type:   0 = Xilinx, 1 = ASIC
+ */
+static int frpw_test_pnp(struct pi_adapter *pi)
+{
+	int olddelay, a, b;
+
+#ifdef FRPW_HARD_RESET
+        w0(0); w2(8); udelay(50); w2(0xc);   /* parallel bus reset */
+        mdelay(1500);
+#endif
+
+	olddelay = pi->delay;
+	pi->delay = 10;
+
+	pi->saved_r0 = r0();
+        pi->saved_r2 = r2();
+
+	w2(4); w0(4); w2(6); w2(7);
+	a = r1() & 0xff; w2(4); b = r1() & 0xff;
+	w2(0xc); w2(0xe); w2(4);
+
+	pi->delay = olddelay;
+        w0(pi->saved_r0);
+        w2(pi->saved_r2);
+
+	return ((~a & 0x40) && (b & 0x40));
+}
+
+/*
+ * We use the pi->private to remember the result of the PNP test.
+ * To make this work, private = port*2 + chip.  Yes, I know it's a hack :-(
+ */
+static int frpw_test_proto(struct pi_adapter *pi)
+{
+	int j, k, r;
+	int e[2] = { 0, 0 };
+	char scratch[512];
+
+	if ((pi->private >> 1) != pi->port)
+		pi->private = frpw_test_pnp(pi) + 2*pi->port;
+
+	if (((pi->private & 0x1) == 0) && (pi->mode > 2)) {
+		dev_dbg(&pi->dev,
+			"frpw: Xilinx does not support mode %d\n", pi->mode);
+		return 1;
+	}
+
+	if (((pi->private & 0x1) == 1) && (pi->mode == 2)) {
+		dev_dbg(&pi->dev, "frpw: ASIC does not support mode 2\n");
+		return 1;
+	}
+
+	frpw_connect(pi);
+	for (j = 0; j < 2; j++) {
+		frpw_write_regr(pi, 0, 6, 0xa0 + j * 0x10);
+		for (k = 0; k < 256; k++) {
+			frpw_write_regr(pi, 0, 2, k ^ 0xaa);
+			frpw_write_regr(pi, 0, 3, k ^ 0x55);
+			if (frpw_read_regr(pi, 0, 2) != (k ^ 0xaa))
+				e[j]++;
+		}
+	}
+	frpw_disconnect(pi);
+
+	frpw_connect(pi);
+	frpw_read_block_int(pi, scratch, 512, 0x10);
+	r = 0;
+	for (k = 0; k < 128; k++) {
+		if (scratch[k] != k)
+			r++;
+	}
+	frpw_disconnect(pi);
+
+	dev_dbg(&pi->dev,
+		"frpw: port 0x%x, chip %ld, mode %d, test=(%d,%d,%d)\n",
+		pi->port, (pi->private%2), pi->mode, e[0], e[1], r);
+
+	return r || (e[0] && e[1]);
+}
+
+static void frpw_log_adapter(struct pi_adapter *pi)
+
+{
+	char *mode[6] = { "4-bit", "8-bit", "EPP", "EPP-8", "EPP-16", "EPP-32"};
+
+	dev_info(&pi->dev,
+		 "Freecom (%s) adapter at 0x%x, mode %d (%s), delay %d\n",
+		 ((pi->private & 0x1) == 0) ? "Xilinx" : "ASIC",
+		 pi->port, pi->mode, mode[pi->mode], pi->delay);
+}
+
+static struct pi_protocol frpw = {
+	.owner		= THIS_MODULE,
+	.name		= "frpw",
+	.max_mode	= 6,
+	.epp_first	= 2,
+	.default_delay	= 2,
+	.max_units	= 1,
+	.write_regr	= frpw_write_regr,
+	.read_regr	= frpw_read_regr,
+	.write_block	= frpw_write_block,
+	.read_block	= frpw_read_block,
+	.connect	= frpw_connect,
+	.disconnect	= frpw_disconnect,
+	.test_proto	= frpw_test_proto,
+	.log_adapter	= frpw_log_adapter,
+};
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Grant R. Guenther <grant@torque.net>");
+MODULE_DESCRIPTION("Freecom Power parallel port IDE adapter protocol driver");
+module_pata_parport_driver(frpw);
diff --git a/drivers/ata/pata_parport/kbic.c b/drivers/ata/pata_parport/kbic.c
new file mode 100644
index 000000000000..fca322627b82
--- /dev/null
+++ b/drivers/ata/pata_parport/kbic.c
@@ -0,0 +1,308 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (c) 1997-1998  Grant R. Guenther <grant@torque.net>
+ *
+ * This is a low-level driver for the KBIC-951A and KBIC-971A
+ * parallel to IDE adapter chips from KingByte Information Systems.
+ *
+ * The chips are almost identical, however, the wakeup code
+ * required for the 971A interferes with the correct operation of
+ * the 951A, so this driver registers itself twice, once for
+ * each chip.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/wait.h>
+#include <asm/io.h>
+#include "pata_parport.h"
+
+#define r12w()		(delay_p, inw(pi->port + 1) & 0xffff)
+
+#define j44(a, b)	((((a >> 4) & 0x0f) | (b & 0xf0)) ^ 0x88)
+#define j53(w)		(((w >> 3) & 0x1f) | ((w >> 4) & 0xe0))
+
+
+/*
+ * cont = 0 - access the IDE register file
+ * cont = 1 - access the IDE command set
+ */
+static int cont_map[2] = { 0x80, 0x40 };
+
+static int kbic_read_regr(struct pi_adapter *pi, int cont, int regr)
+{
+	int a, b, s;
+
+	s = cont_map[cont];
+
+	switch (pi->mode) {
+	case 0:
+		w0(regr | 0x18 | s); w2(4); w2(6); w2(4); w2(1); w0(8);
+		a = r1(); w0(0x28); b = r1(); w2(4);
+		return j44(a, b);
+	case 1:
+		w0(regr|0x38 | s); w2(4); w2(6); w2(4); w2(5); w0(8);
+		a = r12w(); w2(4);
+		return j53(a);
+	case 2:
+		w0(regr | 0x08 | s); w2(4); w2(6); w2(4); w2(0xa5); w2(0xa1);
+		a = r0(); w2(4);
+		return a;
+	case 3:
+	case 4:
+	case 5:
+		w0(0x20 | s); w2(4); w2(6); w2(4); w3(regr);
+		a = r4(); b = r4(); w2(4); w2(0); w2(4);
+		return a;
+	}
+
+	return -1;
+}
+
+static void kbic_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
+{
+	int s = cont_map[cont];
+
+	switch (pi->mode) {
+	case 0:
+	case 1:
+	case 2:
+		w0(regr | 0x10 | s); w2(4); w2(6); w2(4);
+		w0(val); w2(5); w2(4);
+		break;
+	case 3:
+	case 4:
+	case 5:
+		w0(0x20 | s); w2(4); w2(6); w2(4); w3(regr);
+		w4(val); w4(val);
+		w2(4); w2(0); w2(4);
+		break;
+	}
+}
+
+static void k951_connect(struct pi_adapter *pi)
+{
+	pi->saved_r0 = r0();
+	pi->saved_r2 = r2();
+	w2(4);
+}
+
+static void k951_disconnect(struct pi_adapter *pi)
+{
+	w0(pi->saved_r0);
+	w2(pi->saved_r2);
+}
+
+#define	CCP(x)						\
+	do {						\
+		w2(0xc4); w0(0xaa); w0(0x55);		\
+		w0(0); w0(0xff); w0(0x87);		\
+		w0(0x78); w0(x); w2(0xc5);		\
+		w2(0xc4); w0(0xff);			\
+	} while (0)
+
+static void k971_connect(struct pi_adapter *pi)
+{
+	pi->saved_r0 = r0();
+	pi->saved_r2 = r2();
+	CCP(0x20);
+	w2(4);
+}
+
+static void k971_disconnect(struct pi_adapter *pi)
+{
+	CCP(0x30);
+	w0(pi->saved_r0);
+	w2(pi->saved_r2);
+}
+
+/*
+ * count must be congruent to 0 MOD 4, but all known applications
+ *have this property.
+ */
+static void kbic_read_block(struct pi_adapter *pi, char *buf, int count)
+{
+	int k, a, b;
+
+	switch (pi->mode) {
+	case 0:
+		w0(0x98); w2(4); w2(6); w2(4);
+		for (k = 0; k < count / 2; k++) {
+			w2(1); w0(8);
+			a = r1();
+			w0(0x28);
+			b = r1();
+			buf[2 * k] = j44(a, b);
+			w2(5);
+			b = r1();
+			w0(8);
+			a = r1();
+			buf[2 * k + 1] = j44(a, b);
+			w2(4);
+		}
+		break;
+	case 1:
+		w0(0xb8); w2(4); w2(6); w2(4);
+		for (k = 0; k < count / 4; k++) {
+			w0(0xb8);
+			w2(4); w2(5);
+			w0(8);
+			buf[4 * k] = j53(r12w());
+			w0(0xb8);
+			buf[4 * k + 1] = j53(r12w());
+			w2(4); w2(5);
+			buf[4 * k + 3] = j53(r12w());
+			w0(8);
+			buf[4 * k + 2] = j53(r12w());
+		}
+		w2(4);
+		break;
+	case 2:
+		w0(0x88); w2(4); w2(6); w2(4);
+		for (k = 0; k < count / 2; k++) {
+			w2(0xa0); w2(0xa1);
+			buf[2 * k] = r0();
+			w2(0xa5);
+			buf[2 * k + 1] = r0();
+		}
+		w2(4);
+		break;
+	case 3:
+		w0(0xa0); w2(4); w2(6); w2(4); w3(0);
+		for (k = 0; k < count; k++)
+			buf[k] = r4();
+		w2(4); w2(0); w2(4);
+		break;
+	case 4:
+		w0(0xa0); w2(4); w2(6); w2(4); w3(0);
+		for (k = 0; k < count / 2; k++)
+			((u16 *)buf)[k] = r4w();
+		w2(4); w2(0); w2(4);
+		break;
+	case 5:
+		w0(0xa0); w2(4); w2(6); w2(4); w3(0);
+		for (k = 0; k < count / 4; k++)
+			((u32 *)buf)[k] = r4l();
+		w2(4); w2(0); w2(4);
+		break;
+	}
+}
+
+static void kbic_write_block(struct pi_adapter *pi, char *buf, int count)
+{
+	int k;
+
+	switch (pi->mode) {
+	case 0:
+	case 1:
+	case 2:
+		w0(0x90); w2(4); w2(6); w2(4);
+		for (k = 0; k < count / 2; k++) {
+			w0(buf[2 * k + 1]);
+			w2(0); w2(4);
+			w0(buf[2 * k]);
+			w2(5); w2(4);
+		}
+		break;
+	case 3:
+		w0(0xa0); w2(4); w2(6); w2(4); w3(0);
+		for (k = 0; k < count / 2; k++) {
+			w4(buf[2 * k + 1]);
+			w4(buf[2 * k]);
+		}
+		w2(4); w2(0); w2(4);
+		break;
+	case 4:
+		w0(0xa0); w2(4); w2(6); w2(4); w3(0);
+		for (k = 0; k < count / 2; k++)
+			w4w(swab16(((u16 *)buf)[k]));
+		w2(4); w2(0); w2(4);
+		break;
+	case 5:
+		w0(0xa0); w2(4); w2(6); w2(4); w3(0);
+		for (k = 0; k < count / 4; k++)
+			w4l(swab16(((u16 *)buf)[2 * k]) |
+			    swab16(((u16 *)buf)[2 * k + 1]) << 16);
+		w2(4); w2(0); w2(4);
+		break;
+	}
+}
+
+static void kbic_log_adapter(struct pi_adapter *pi, char *chip)
+{
+	char *mode[6] = { "4-bit", "5/3", "8-bit", "EPP-8", "EPP_16", "EPP-32"};
+
+	dev_info(&pi->dev, "KingByte %s at 0x%x, mode %d (%s), delay %d\n",
+		 chip, pi->port, pi->mode, mode[pi->mode], pi->delay);
+}
+
+static void k951_log_adapter(struct pi_adapter *pi)
+{
+	kbic_log_adapter(pi, "KBIC-951A");
+}
+
+static void k971_log_adapter(struct pi_adapter *pi)
+{
+	kbic_log_adapter(pi, "KBIC-971A");
+}
+
+static struct pi_protocol k951 = {
+	.owner		= THIS_MODULE,
+	.name		= "k951",
+	.max_mode	= 6,
+	.epp_first	= 3,
+	.default_delay	= 1,
+	.max_units	= 1,
+	.write_regr	= kbic_write_regr,
+	.read_regr	= kbic_read_regr,
+	.write_block	= kbic_write_block,
+	.read_block	= kbic_read_block,
+	.connect	= k951_connect,
+	.disconnect	= k951_disconnect,
+	.log_adapter	= k951_log_adapter,
+};
+
+static struct pi_protocol k971 = {
+	.owner		= THIS_MODULE,
+	.name		= "k971",
+	.max_mode	= 6,
+	.epp_first	= 3,
+	.default_delay	= 1,
+	.max_units	= 1,
+	.write_regr	= kbic_write_regr,
+	.read_regr	= kbic_read_regr,
+	.write_block	= kbic_write_block,
+	.read_block	= kbic_read_block,
+	.connect	= k971_connect,
+	.disconnect	= k971_disconnect,
+	.log_adapter	= k971_log_adapter,
+};
+
+static int __init kbic_init(void)
+{
+	int rv;
+
+	rv = pata_parport_register_driver(&k951);
+	if (rv < 0)
+		return rv;
+	rv = pata_parport_register_driver(&k971);
+	if (rv < 0)
+		pata_parport_unregister_driver(&k951);
+	return rv;
+}
+
+static void __exit kbic_exit(void)
+{
+	pata_parport_unregister_driver(&k951);
+	pata_parport_unregister_driver(&k971);
+}
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Grant R. Guenther <grant@torque.net>");
+MODULE_DESCRIPTION("KingByte Information Systems KBIC-951A and KBIC-971A "
+		   "parallel port IDE adapter protocol driver");
+module_init(kbic_init)
+module_exit(kbic_exit)
diff --git a/drivers/ata/pata_parport/ktti.c b/drivers/ata/pata_parport/ktti.c
new file mode 100644
index 000000000000..c078d1934862
--- /dev/null
+++ b/drivers/ata/pata_parport/ktti.c
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (c) 1998  Grant R. Guenther <grant@torque.net>
+ *
+ * ktti.c is a low-level protocol driver for the KT Technology
+ * parallel port adapter.  This adapter is used in the "PHd"
+ * portable hard-drives.  As far as I can tell, this device
+ * supports 4-bit mode _only_.
+*/
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/wait.h>
+#include <asm/io.h>
+#include "pata_parport.h"
+
+#define j44(a, b)	(((a >> 4) & 0x0f) | (b & 0xf0))
+
+/*
+ * cont = 0 - access the IDE register file
+ * cont = 1 - access the IDE command set
+ */
+static int cont_map[2] = { 0x10, 0x08 };
+
+static void ktti_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
+{
+	int r = regr + cont_map[cont];
+
+	w0(r); w2(0xb); w2(0xa); w2(3); w2(6);
+	w0(val); w2(3); w0(0); w2(6); w2(0xb);
+}
+
+static int ktti_read_regr(struct pi_adapter *pi, int cont, int regr)
+{
+	int a, b, r;
+
+        r = regr + cont_map[cont];
+
+	w0(r); w2(0xb); w2(0xa); w2(9); w2(0xc); w2(9);
+	a = r1(); w2(0xc);  b = r1(); w2(9); w2(0xc); w2(9);
+	return j44(a, b);
+}
+
+static void ktti_read_block(struct pi_adapter *pi, char *buf, int count)
+{
+	int k, a, b;
+
+	for (k = 0; k < count / 2; k++) {
+		w0(0x10); w2(0xb); w2(0xa); w2(9); w2(0xc); w2(9);
+		a = r1(); w2(0xc); b = r1(); w2(9);
+		buf[2*k] = j44(a, b);
+		a = r1(); w2(0xc); b = r1(); w2(9);
+		buf[2*k+1] = j44(a, b);
+	}
+}
+
+static void ktti_write_block(struct pi_adapter *pi, char *buf, int count)
+{
+	int k;
+
+	for (k = 0; k < count / 2; k++) {
+		w0(0x10); w2(0xb); w2(0xa); w2(3); w2(6);
+		w0(buf[2 * k]); w2(3);
+		w0(buf[2 * k + 1]); w2(6);
+		w2(0xb);
+	}
+}
+
+static void ktti_connect(struct pi_adapter *pi)
+{
+	pi->saved_r0 = r0();
+	pi->saved_r2 = r2();
+	w2(0xb); w2(0xa); w0(0); w2(3); w2(6);
+}
+
+static void ktti_disconnect(struct pi_adapter *pi)
+{
+	w2(0xb); w2(0xa); w0(0xa0); w2(3); w2(4);
+	w0(pi->saved_r0);
+	w2(pi->saved_r2);
+}
+
+static void ktti_log_adapter(struct pi_adapter *pi)
+{
+	dev_info(&pi->dev, "KT adapter at 0x%x, delay %d\n",
+		 pi->port, pi->delay);
+}
+
+static struct pi_protocol ktti = {
+	.owner		= THIS_MODULE,
+	.name		= "ktti",
+	.max_mode	= 1,
+	.epp_first	= 2,
+	.default_delay	= 1,
+	.max_units	= 1,
+	.write_regr	= ktti_write_regr,
+	.read_regr	= ktti_read_regr,
+	.write_block	= ktti_write_block,
+	.read_block	= ktti_read_block,
+	.connect	= ktti_connect,
+	.disconnect	= ktti_disconnect,
+	.log_adapter	= ktti_log_adapter,
+};
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Grant R. Guenther <grant@torque.net>");
+MODULE_DESCRIPTION("KT Technology parallel port IDE adapter protocol driver");
+module_pata_parport_driver(ktti);
diff --git a/drivers/ata/pata_parport/on20.c b/drivers/ata/pata_parport/on20.c
new file mode 100644
index 000000000000..7c70e5b13a2a
--- /dev/null
+++ b/drivers/ata/pata_parport/on20.c
@@ -0,0 +1,147 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (c) 1996-1998  Grant R. Guenther <grant@torque.net>
+ *
+ * on20.c is a low-level protocol driver for the
+ * Onspec 90c20 parallel to IDE adapter.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/wait.h>
+#include <asm/io.h>
+#include "pata_parport.h"
+
+#define op(f)					\
+	do {					\
+		w2(4); w0(f); w2(5); w2(0xd);	\
+		w2(5); w2(0xd); w2(5); w2(4);	\
+	} while (0)
+
+#define vl(v)					\
+	do {					\
+		w2(4); w0(v); w2(5);		\
+		w2(7); w2(5); w2(4);		\
+	} while (0)
+
+#define j44(a, b)	(((a >> 4) & 0x0f) | (b & 0xf0))
+
+/*
+ * cont = 0 - access the IDE register file
+ * cont = 1 - access the IDE command set
+ */
+
+static int on20_read_regr(struct pi_adapter *pi, int cont, int regr)
+{
+	int h, l, r;
+
+	r = (regr << 2) + 1 + cont;
+
+	op(1); vl(r); op(0);
+
+	switch (pi->mode) {
+	case 0:
+		w2(4); w2(6); l = r1();
+		w2(4); w2(6); h = r1();
+		w2(4); w2(6); w2(4); w2(6); w2(4);
+		return j44(l, h);
+	case 1:
+		w2(4); w2(0x26); r = r0();
+		w2(4); w2(0x26); w2(4);
+		return r;
+	}
+
+	return -1;
+}
+
+static void on20_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
+{
+	int r = (regr << 2) + 1 + cont;
+
+	op(1); vl(r);
+	op(0); vl(val);
+	op(0); vl(val);
+}
+
+static void on20_connect(struct pi_adapter *pi)
+{
+	pi->saved_r0 = r0();
+	pi->saved_r2 = r2();
+
+	w2(4); w0(0); w2(0xc); w2(4); w2(6); w2(4); w2(6); w2(4);
+	if (pi->mode) {
+		op(2); vl(8); op(2); vl(9);
+	} else {
+		op(2); vl(0); op(2); vl(8);
+	}
+}
+
+static void on20_disconnect(struct pi_adapter *pi)
+{
+	w2(4); w0(7); w2(4); w2(0xc); w2(4);
+	w0(pi->saved_r0);
+	w2(pi->saved_r2);
+}
+
+static void on20_read_block(struct pi_adapter *pi, char *buf, int count)
+{
+	int k, l, h;
+
+	op(1); vl(1); op(0);
+
+	for (k = 0; k < count; k++) {
+		if (pi->mode) {
+			w2(4); w2(0x26); buf[k] = r0();
+		} else {
+			w2(6); l = r1(); w2(4);
+			w2(6); h = r1(); w2(4);
+			buf[k] = j44(l, h);
+		}
+	}
+	w2(4);
+}
+
+static void on20_write_block(struct pi_adapter *pi, char *buf, int count)
+{
+	int k;
+
+	op(1); vl(1); op(0);
+
+	for (k = 0; k < count; k++) {
+		w2(5); w0(buf[k]); w2(7);
+	}
+	w2(4);
+}
+
+static void on20_log_adapter(struct pi_adapter *pi)
+{
+	char *mode_string[2] = { "4-bit", "8-bit" };
+
+	dev_info(&pi->dev,
+		 "OnSpec 90c20 at 0x%x, mode %d (%s), delay %d\n",
+		 pi->port, pi->mode, mode_string[pi->mode], pi->delay);
+}
+
+static struct pi_protocol on20 = {
+	.owner		= THIS_MODULE,
+	.name		= "on20",
+	.max_mode	= 2,
+	.epp_first	= 2,
+	.default_delay	= 1,
+	.max_units	= 1,
+	.write_regr	= on20_write_regr,
+	.read_regr	= on20_read_regr,
+	.write_block	= on20_write_block,
+	.read_block	= on20_read_block,
+	.connect	= on20_connect,
+	.disconnect	= on20_disconnect,
+	.log_adapter	= on20_log_adapter,
+};
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Grant R. Guenther <grant@torque.net>");
+MODULE_DESCRIPTION("Onspec 90c20 parallel port IDE adapter protocol driver");
+module_pata_parport_driver(on20);
diff --git a/drivers/ata/pata_parport/on26.c b/drivers/ata/pata_parport/on26.c
new file mode 100644
index 000000000000..c88e5d6f203e
--- /dev/null
+++ b/drivers/ata/pata_parport/on26.c
@@ -0,0 +1,315 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (c) 1997-1998  Grant R. Guenther <grant@torque.net>
+ *
+ * on26.c is a low-level protocol driver for the
+ * OnSpec 90c26 parallel to IDE adapter chip.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/wait.h>
+#include <asm/io.h>
+#include "pata_parport.h"
+
+/*
+ * mode codes:  0  nybble reads, 8-bit writes
+ *		1  8-bit reads and writes
+ *		2  8-bit EPP mode
+ *		3  EPP-16
+ *		4  EPP-32
+ */
+
+#define j44(a, b)	(((a >> 4) & 0x0f) | (b & 0xf0))
+
+#define P1						      \
+	do {						      \
+		w2(5); w2(0xd); w2(5); w2(0xd); w2(5); w2(4); \
+	} while (0)
+
+#define P2					\
+	do {					\
+		w2(5); w2(7); w2(5); w2(4);	\
+	} while (0)
+
+/*
+ * cont = 0 - access the IDE register file
+ * cont = 1 - access the IDE command set
+ */
+
+static int on26_read_regr(struct pi_adapter *pi, int cont, int regr)
+{
+	int a, b, r;
+
+	r = (regr << 2) + 1 + cont;
+
+	switch (pi->mode) {
+	case 0:
+		w0(1); P1; w0(r); P2; w0(0); P1;
+		w2(6); a = r1(); w2(4);
+		w2(6); b = r1(); w2(4);
+		w2(6); w2(4); w2(6); w2(4);
+		return j44(a, b);
+	case 1:
+		w0(1); P1; w0(r); P2; w0(0); P1;
+		w2(0x26); a = r0(); w2(4); w2(0x26); w2(4);
+		return a;
+	case 2:
+	case 3:
+	case 4:
+		w3(1); w3(1); w2(5); w4(r); w2(4);
+		w3(0); w3(0); w2(0x24); a = r4(); w2(4);
+		w2(0x24); (void)r4(); w2(4);
+		return a;
+	}
+
+	return -1;
+}
+
+static void on26_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
+{
+	int r = (regr << 2) + 1 + cont;
+
+	switch (pi->mode) {
+	case 0:
+	case 1:
+		w0(1); P1; w0(r); P2; w0(0); P1;
+		w0(val); P2; w0(val); P2;
+		break;
+	case 2:
+	case 3:
+	case 4:
+		w3(1); w3(1); w2(5); w4(r); w2(4);
+		w3(0); w3(0);
+		w2(5); w4(val); w2(4);
+		w2(5); w4(val); w2(4);
+		break;
+	}
+}
+
+#define CCP(x)						\
+	do {						\
+		w0(0xfe); w0(0xaa); w0(0x55); w0(0);	\
+		w0(0xff); w0(0x87); w0(0x78); w0(x);	\
+		w2(4); w2(5); w2(4); w0(0xff);		\
+	} while (0)
+
+static void on26_connect(struct pi_adapter *pi)
+{
+	int x;
+
+	pi->saved_r0 = r0();
+	pi->saved_r2 = r2();
+
+	CCP(0x20);
+	if (pi->mode)
+		x = 9;
+	else
+		x = 8;
+
+	w0(2); P1; w0(8); P2;
+	w0(2); P1; w0(x); P2;
+}
+
+static void on26_disconnect(struct pi_adapter *pi)
+{
+	if (pi->mode >= 2) {
+		w3(4); w3(4); w3(4); w3(4);
+	} else {
+		w0(4); P1; w0(4); P1;
+	}
+	CCP(0x30);
+	w0(pi->saved_r0);
+	w2(pi->saved_r2);
+}
+
+#define	RESET_WAIT  200
+
+/* hard reset */
+static int on26_test_port(struct pi_adapter *pi)
+{
+	int i, m, d, x = 0, y = 0;
+
+	pi->saved_r0 = r0();
+	pi->saved_r2 = r2();
+
+	d = pi->delay;
+	m = pi->mode;
+	pi->delay = 5;
+	pi->mode = 0;
+
+	w2(0xc);
+
+	CCP(0x30); CCP(0);
+
+	w0(0xfe); w0(0xaa); w0(0x55); w0(0); w0(0xff);
+	i = ((r1() & 0xf0) << 4); w0(0x87);
+	i |= (r1() & 0xf0); w0(0x78);
+	w0(0x20); w2(4); w2(5);
+	i |= ((r1() & 0xf0) >> 4);
+	w2(4); w0(0xff);
+
+	if (i == 0xb5f) {
+		w0(2); P1; w0(0);   P2;
+		w0(3); P1; w0(0);   P2;
+		w0(2); P1; w0(8);   P2; udelay(100);
+		w0(2); P1; w0(0xa); P2; udelay(100);
+		w0(2); P1; w0(8);   P2; udelay(1000);
+
+		on26_write_regr(pi, 0, 6, 0xa0);
+
+		for (i = 0; i < RESET_WAIT; i++) {
+			on26_write_regr(pi, 0, 6, 0xa0);
+			x = on26_read_regr(pi, 0, 7);
+			on26_write_regr(pi, 0, 6, 0xb0);
+			y = on26_read_regr(pi, 0, 7);
+			if (!((x & 0x80) || (y & 0x80)))
+				break;
+			mdelay(100);
+		}
+
+		if (i == RESET_WAIT)
+			dev_err(&pi->dev,
+				"on26: Device reset failed (%x,%x)\n", x, y);
+
+		w0(4); P1; w0(4); P1;
+	}
+
+	CCP(0x30);
+
+	pi->delay = d;
+	pi->mode = m;
+	w0(pi->saved_r0);
+	w2(pi->saved_r2);
+
+	return 5;
+}
+
+static void on26_read_block(struct pi_adapter *pi, char *buf, int count)
+{
+	int k, a, b;
+
+	switch (pi->mode) {
+	case 0:
+		w0(1); P1; w0(1); P2; w0(2); P1; w0(0x18); P2; w0(0); P1;
+		udelay(10);
+		for (k = 0; k < count; k++) {
+			w2(6); a = r1();
+			w2(4); b = r1();
+			buf[k] = j44(a, b);
+		}
+		w0(2); P1; w0(8); P2;
+		break;
+	case 1:
+		w0(1); P1; w0(1); P2; w0(2); P1; w0(0x19); P2; w0(0); P1;
+		udelay(10);
+		for (k = 0; k < count / 2; k++) {
+			w2(0x26); buf[2 * k] = r0();
+			w2(0x24); buf[2 * k + 1] = r0();
+		}
+		w0(2); P1; w0(9); P2;
+		break;
+	case 2:
+		w3(1); w3(1); w2(5); w4(1); w2(4);
+		w3(0); w3(0); w2(0x24);
+		udelay(10);
+		for (k = 0; k < count; k++)
+			buf[k] = r4();
+		w2(4);
+		break;
+	case 3:
+		w3(1); w3(1); w2(5); w4(1); w2(4);
+		w3(0); w3(0); w2(0x24);
+		udelay(10);
+		for (k = 0; k < count / 2; k++)
+			((u16 *)buf)[k] = r4w();
+		w2(4);
+		break;
+	case 4:
+		w3(1); w3(1); w2(5); w4(1); w2(4);
+		w3(0); w3(0); w2(0x24);
+		udelay(10);
+		for (k = 0; k < count / 4; k++)
+			((u32 *)buf)[k] = r4l();
+		w2(4);
+		break;
+	}
+}
+
+static void on26_write_block(struct pi_adapter *pi, char *buf, int count)
+{
+	int k;
+
+	switch (pi->mode) {
+	case 0:
+	case 1:
+		w0(1); P1; w0(1); P2;
+		w0(2); P1; w0(0x18 + pi->mode); P2; w0(0); P1;
+		udelay(10);
+		for (k = 0; k < count / 2; k++) {
+			w2(5); w0(buf[2 * k]);
+			w2(7); w0(buf[2 * k + 1]);
+		}
+		w2(5); w2(4);
+		w0(2); P1; w0(8 + pi->mode); P2;
+		break;
+	case 2:
+		w3(1); w3(1); w2(5); w4(1); w2(4);
+		w3(0); w3(0); w2(0xc5);
+		udelay(10);
+		for (k = 0; k < count; k++)
+			w4(buf[k]);
+		w2(0xc4);
+		break;
+	case 3:
+		w3(1); w3(1); w2(5); w4(1); w2(4);
+		w3(0); w3(0); w2(0xc5);
+		udelay(10);
+		for (k = 0; k < count / 2; k++)
+			w4w(((u16 *)buf)[k]);
+		w2(0xc4);
+		break;
+	case 4:
+		w3(1); w3(1); w2(5); w4(1); w2(4);
+		w3(0); w3(0); w2(0xc5);
+		udelay(10);
+		for (k = 0; k < count / 4; k++)
+			w4l(((u32 *)buf)[k]);
+		w2(0xc4);
+		break;
+	}
+}
+
+static void on26_log_adapter(struct pi_adapter *pi)
+{
+	char *mode_string[5] = { "4-bit", "8-bit", "EPP-8", "EPP-16", "EPP-32" };
+
+	dev_info(&pi->dev,
+		 "OnSpec 90c26 at 0x%x, mode %d (%s), delay %d\n",
+		 pi->port, pi->mode, mode_string[pi->mode], pi->delay);
+}
+
+static struct pi_protocol on26 = {
+	.owner		= THIS_MODULE,
+	.name		= "on26",
+	.max_mode	= 5,
+	.epp_first	= 2,
+	.default_delay	= 1,
+	.max_units	= 1,
+	.write_regr	= on26_write_regr,
+	.read_regr	= on26_read_regr,
+	.write_block	= on26_write_block,
+	.read_block	= on26_read_block,
+	.connect	= on26_connect,
+	.disconnect	= on26_disconnect,
+	.test_port	= on26_test_port,
+	.log_adapter	= on26_log_adapter,
+};
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Grant R. Guenther <grant@torque.net>");
+MODULE_DESCRIPTION("Onspec 90c26 parallel port IDE adapter protocol driver");
+module_pata_parport_driver(on26);
diff --git a/drivers/ata/pata_parport/pata_parport.c b/drivers/ata/pata_parport/pata_parport.c
new file mode 100644
index 000000000000..22bd3ff6b7ae
--- /dev/null
+++ b/drivers/ata/pata_parport/pata_parport.c
@@ -0,0 +1,835 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2023 Ondrej Zary
+ * based on paride.c by Grant R. Guenther <grant@torque.net>
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/parport.h>
+#include "pata_parport.h"
+
+#define DRV_NAME "pata_parport"
+
+static DEFINE_IDR(parport_list);
+static DEFINE_IDR(protocols);
+static DEFINE_IDA(pata_parport_bus_dev_ids);
+static DEFINE_MUTEX(pi_mutex);
+
+static bool probe = true;
+module_param(probe, bool, 0644);
+MODULE_PARM_DESC(probe, "Enable automatic device probing (0=off, 1=on [default])");
+
+/*
+ * libata drivers cannot sleep so this driver claims parport before activating
+ * the ata host and keeps it claimed (and protocol connected) until the ata
+ * host is removed. Unfortunately, this means that you cannot use any chained
+ * devices (neither other pata_parport devices nor a printer).
+ */
+static void pi_connect(struct pi_adapter *pi)
+{
+	parport_claim_or_block(pi->pardev);
+	pi->proto->connect(pi);
+}
+
+static void pi_disconnect(struct pi_adapter *pi)
+{
+	pi->proto->disconnect(pi);
+	parport_release(pi->pardev);
+}
+
+static void pata_parport_dev_select(struct ata_port *ap, unsigned int device)
+{
+	struct pi_adapter *pi = ap->host->private_data;
+	u8 tmp;
+
+	if (device == 0)
+		tmp = ATA_DEVICE_OBS;
+	else
+		tmp = ATA_DEVICE_OBS | ATA_DEV1;
+
+	pi->proto->write_regr(pi, 0, ATA_REG_DEVICE, tmp);
+	ata_sff_pause(ap);
+}
+
+static void pata_parport_set_devctl(struct ata_port *ap, u8 ctl)
+{
+	struct pi_adapter *pi = ap->host->private_data;
+
+	pi->proto->write_regr(pi, 1, 6, ctl);
+}
+
+static bool pata_parport_devchk(struct ata_port *ap, unsigned int device)
+{
+	struct pi_adapter *pi = ap->host->private_data;
+	u8 nsect, lbal;
+
+	pata_parport_dev_select(ap, device);
+
+	pi->proto->write_regr(pi, 0, ATA_REG_NSECT, 0x55);
+	pi->proto->write_regr(pi, 0, ATA_REG_LBAL, 0xaa);
+
+	pi->proto->write_regr(pi, 0, ATA_REG_NSECT, 0xaa);
+	pi->proto->write_regr(pi, 0, ATA_REG_LBAL, 0x55);
+
+	pi->proto->write_regr(pi, 0, ATA_REG_NSECT, 0x55);
+	pi->proto->write_regr(pi, 0, ATA_REG_LBAL, 0xaa);
+
+	nsect = pi->proto->read_regr(pi, 0, ATA_REG_NSECT);
+	lbal = pi->proto->read_regr(pi, 0, ATA_REG_LBAL);
+
+	return (nsect == 0x55) && (lbal == 0xaa);
+}
+
+static int pata_parport_wait_after_reset(struct ata_link *link,
+					 unsigned int devmask,
+					 unsigned long deadline)
+{
+	struct ata_port *ap = link->ap;
+	struct pi_adapter *pi = ap->host->private_data;
+	unsigned int dev0 = devmask & (1 << 0);
+	unsigned int dev1 = devmask & (1 << 1);
+	int rc, ret = 0;
+
+	ata_msleep(ap, ATA_WAIT_AFTER_RESET);
+
+	/* always check readiness of the master device */
+	rc = ata_sff_wait_ready(link, deadline);
+	if (rc) {
+		/*
+		 * some adapters return bogus values if master device is not
+		 * present, so don't abort now if a slave device is present
+		 */
+		if (!dev1)
+			return rc;
+		ret = -ENODEV;
+	}
+
+	/*
+	 * if device 1 was found in ata_devchk, wait for register
+	 * access briefly, then wait for BSY to clear.
+	 */
+	if (dev1) {
+		int i;
+
+		pata_parport_dev_select(ap, 1);
+
+		/*
+		 * Wait for register access.  Some ATAPI devices fail
+		 * to set nsect/lbal after reset, so don't waste too
+		 * much time on it.  We're gonna wait for !BSY anyway.
+		 */
+		for (i = 0; i < 2; i++) {
+			u8 nsect, lbal;
+
+			nsect = pi->proto->read_regr(pi, 0, ATA_REG_NSECT);
+			lbal = pi->proto->read_regr(pi, 0, ATA_REG_LBAL);
+			if (nsect == 1 && lbal == 1)
+				break;
+			/* give drive a breather */
+			ata_msleep(ap, 50);
+		}
+
+		rc = ata_sff_wait_ready(link, deadline);
+		if (rc) {
+			if (rc != -ENODEV)
+				return rc;
+			ret = rc;
+		}
+	}
+
+	pata_parport_dev_select(ap, 0);
+	if (dev1)
+		pata_parport_dev_select(ap, 1);
+	if (dev0)
+		pata_parport_dev_select(ap, 0);
+
+	return ret;
+}
+
+static int pata_parport_bus_softreset(struct ata_port *ap, unsigned int devmask,
+				      unsigned long deadline)
+{
+	struct pi_adapter *pi = ap->host->private_data;
+
+	/* software reset.  causes dev0 to be selected */
+	pi->proto->write_regr(pi, 1, 6, ap->ctl);
+	udelay(20);
+	pi->proto->write_regr(pi, 1, 6, ap->ctl | ATA_SRST);
+	udelay(20);
+	pi->proto->write_regr(pi, 1, 6, ap->ctl);
+	ap->last_ctl = ap->ctl;
+
+	/* wait the port to become ready */
+	return pata_parport_wait_after_reset(&ap->link, devmask, deadline);
+}
+
+static int pata_parport_softreset(struct ata_link *link, unsigned int *classes,
+				  unsigned long deadline)
+{
+	struct ata_port *ap = link->ap;
+	unsigned int devmask = 0;
+	int rc;
+	u8 err;
+
+	/* determine if device 0/1 are present */
+	if (pata_parport_devchk(ap, 0))
+		devmask |= (1 << 0);
+	if (pata_parport_devchk(ap, 1))
+		devmask |= (1 << 1);
+
+	/* select device 0 again */
+	pata_parport_dev_select(ap, 0);
+
+	/* issue bus reset */
+	rc = pata_parport_bus_softreset(ap, devmask, deadline);
+	if (rc && rc != -ENODEV) {
+		ata_link_err(link, "SRST failed (errno=%d)\n", rc);
+		return rc;
+	}
+
+	/* determine by signature whether we have ATA or ATAPI devices */
+	classes[0] = ata_sff_dev_classify(&link->device[0],
+					  devmask & (1 << 0), &err);
+	if (err != 0x81)
+		classes[1] = ata_sff_dev_classify(&link->device[1],
+						  devmask & (1 << 1), &err);
+
+	return 0;
+}
+
+static u8 pata_parport_check_status(struct ata_port *ap)
+{
+	struct pi_adapter *pi = ap->host->private_data;
+
+	return pi->proto->read_regr(pi, 0, ATA_REG_STATUS);
+}
+
+static u8 pata_parport_check_altstatus(struct ata_port *ap)
+{
+	struct pi_adapter *pi = ap->host->private_data;
+
+	return pi->proto->read_regr(pi, 1, 6);
+}
+
+static void pata_parport_tf_load(struct ata_port *ap,
+				 const struct ata_taskfile *tf)
+{
+	struct pi_adapter *pi = ap->host->private_data;
+
+	if (tf->ctl != ap->last_ctl) {
+		pi->proto->write_regr(pi, 1, 6, tf->ctl);
+		ap->last_ctl = tf->ctl;
+		ata_wait_idle(ap);
+	}
+
+	if (tf->flags & ATA_TFLAG_ISADDR) {
+		if (tf->flags & ATA_TFLAG_LBA48) {
+			pi->proto->write_regr(pi, 0, ATA_REG_FEATURE,
+					      tf->hob_feature);
+			pi->proto->write_regr(pi, 0, ATA_REG_NSECT,
+					      tf->hob_nsect);
+			pi->proto->write_regr(pi, 0, ATA_REG_LBAL,
+					      tf->hob_lbal);
+			pi->proto->write_regr(pi, 0, ATA_REG_LBAM,
+					      tf->hob_lbam);
+			pi->proto->write_regr(pi, 0, ATA_REG_LBAH,
+					      tf->hob_lbah);
+		}
+		pi->proto->write_regr(pi, 0, ATA_REG_FEATURE, tf->feature);
+		pi->proto->write_regr(pi, 0, ATA_REG_NSECT, tf->nsect);
+		pi->proto->write_regr(pi, 0, ATA_REG_LBAL, tf->lbal);
+		pi->proto->write_regr(pi, 0, ATA_REG_LBAM, tf->lbam);
+		pi->proto->write_regr(pi, 0, ATA_REG_LBAH, tf->lbah);
+	}
+
+	if (tf->flags & ATA_TFLAG_DEVICE)
+		pi->proto->write_regr(pi, 0, ATA_REG_DEVICE, tf->device);
+
+	ata_wait_idle(ap);
+}
+
+static void pata_parport_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
+{
+	struct pi_adapter *pi = ap->host->private_data;
+
+	tf->status = pi->proto->read_regr(pi, 0, ATA_REG_STATUS);
+	tf->error = pi->proto->read_regr(pi, 0, ATA_REG_ERR);
+	tf->nsect = pi->proto->read_regr(pi, 0, ATA_REG_NSECT);
+	tf->lbal = pi->proto->read_regr(pi, 0, ATA_REG_LBAL);
+	tf->lbam = pi->proto->read_regr(pi, 0, ATA_REG_LBAM);
+	tf->lbah = pi->proto->read_regr(pi, 0, ATA_REG_LBAH);
+	tf->device = pi->proto->read_regr(pi, 0, ATA_REG_DEVICE);
+
+	if (tf->flags & ATA_TFLAG_LBA48) {
+		pi->proto->write_regr(pi, 1, 6, tf->ctl | ATA_HOB);
+		tf->hob_feature = pi->proto->read_regr(pi, 0, ATA_REG_ERR);
+		tf->hob_nsect = pi->proto->read_regr(pi, 0, ATA_REG_NSECT);
+		tf->hob_lbal = pi->proto->read_regr(pi, 0, ATA_REG_LBAL);
+		tf->hob_lbam = pi->proto->read_regr(pi, 0, ATA_REG_LBAM);
+		tf->hob_lbah = pi->proto->read_regr(pi, 0, ATA_REG_LBAH);
+		pi->proto->write_regr(pi, 1, 6, tf->ctl);
+		ap->last_ctl = tf->ctl;
+	}
+}
+
+static void pata_parport_exec_command(struct ata_port *ap,
+				      const struct ata_taskfile *tf)
+{
+	struct pi_adapter *pi = ap->host->private_data;
+
+	pi->proto->write_regr(pi, 0, ATA_REG_CMD, tf->command);
+	ata_sff_pause(ap);
+}
+
+static unsigned int pata_parport_data_xfer(struct ata_queued_cmd *qc,
+				unsigned char *buf, unsigned int buflen, int rw)
+{
+	struct ata_port *ap = qc->dev->link->ap;
+	struct pi_adapter *pi = ap->host->private_data;
+
+	if (rw == READ)
+		pi->proto->read_block(pi, buf, buflen);
+	else
+		pi->proto->write_block(pi, buf, buflen);
+
+	return buflen;
+}
+
+static void pata_parport_drain_fifo(struct ata_queued_cmd *qc)
+{
+	int count;
+	struct ata_port *ap;
+	struct pi_adapter *pi;
+	char junk[2];
+
+	/* We only need to flush incoming data when a command was running */
+	if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE)
+		return;
+
+	ap = qc->ap;
+	pi = ap->host->private_data;
+	/* Drain up to 64K of data before we give up this recovery method */
+	for (count = 0; (pata_parport_check_status(ap) & ATA_DRQ)
+						&& count < 65536; count += 2) {
+		pi->proto->read_block(pi, junk, 2);
+	}
+
+	if (count)
+		ata_port_dbg(ap, "drained %d bytes to clear DRQ\n", count);
+}
+
+static struct ata_port_operations pata_parport_port_ops = {
+	.inherits		= &ata_sff_port_ops,
+
+	.reset.softreset	= pata_parport_softreset,
+	.reset.hardreset	= NULL,
+
+	.sff_dev_select		= pata_parport_dev_select,
+	.sff_set_devctl		= pata_parport_set_devctl,
+	.sff_check_status	= pata_parport_check_status,
+	.sff_check_altstatus	= pata_parport_check_altstatus,
+	.sff_tf_load		= pata_parport_tf_load,
+	.sff_tf_read		= pata_parport_tf_read,
+	.sff_exec_command	= pata_parport_exec_command,
+	.sff_data_xfer		= pata_parport_data_xfer,
+	.sff_drain_fifo		= pata_parport_drain_fifo,
+};
+
+static const struct ata_port_info pata_parport_port_info = {
+	.flags		= ATA_FLAG_SLAVE_POSS | ATA_FLAG_PIO_POLLING,
+	.pio_mask	= ATA_PIO0,
+	/* No DMA */
+	.port_ops	= &pata_parport_port_ops,
+};
+
+static void pi_release(struct pi_adapter *pi)
+{
+	parport_unregister_device(pi->pardev);
+	if (pi->proto->release_proto)
+		pi->proto->release_proto(pi);
+	module_put(pi->proto->owner);
+}
+
+static int default_test_proto(struct pi_adapter *pi)
+{
+	int j, k;
+	int e[2] = { 0, 0 };
+
+	pi->proto->connect(pi);
+
+	for (j = 0; j < 2; j++) {
+		pi->proto->write_regr(pi, 0, 6, 0xa0 + j * 0x10);
+		for (k = 0; k < 256; k++) {
+			pi->proto->write_regr(pi, 0, 2, k ^ 0xaa);
+			pi->proto->write_regr(pi, 0, 3, k ^ 0x55);
+			if (pi->proto->read_regr(pi, 0, 2) != (k ^ 0xaa))
+				e[j]++;
+		}
+	}
+	pi->proto->disconnect(pi);
+
+	dev_dbg(&pi->dev, "%s: port 0x%x, mode %d, test=(%d,%d)\n",
+		pi->proto->name, pi->port, pi->mode, e[0], e[1]);
+
+	return e[0] && e[1];	/* not here if both > 0 */
+}
+
+static int pi_test_proto(struct pi_adapter *pi)
+{
+	int res;
+
+	parport_claim_or_block(pi->pardev);
+	if (pi->proto->test_proto)
+		res = pi->proto->test_proto(pi);
+	else
+		res = default_test_proto(pi);
+	parport_release(pi->pardev);
+
+	return res;
+}
+
+static bool pi_probe_mode(struct pi_adapter *pi, int max)
+{
+	int best, range;
+
+	if (pi->mode != -1) {
+		if (pi->mode >= max)
+			return false;
+		range = 3;
+		if (pi->mode >= pi->proto->epp_first)
+			range = 8;
+		if (range == 8 && pi->port % 8)
+			return false;
+		return !pi_test_proto(pi);
+	}
+	best = -1;
+	for (pi->mode = 0; pi->mode < max; pi->mode++) {
+		range = 3;
+		if (pi->mode >= pi->proto->epp_first)
+			range = 8;
+		if (range == 8 && pi->port % 8)
+			break;
+		if (!pi_test_proto(pi))
+			best = pi->mode;
+	}
+	pi->mode = best;
+	return best > -1;
+}
+
+static bool pi_probe_unit(struct pi_adapter *pi, int unit)
+{
+	int max, s, e;
+
+	s = unit;
+	e = s + 1;
+
+	if (s == -1) {
+		s = 0;
+		e = pi->proto->max_units;
+	}
+
+	if (pi->proto->test_port) {
+		parport_claim_or_block(pi->pardev);
+		max = pi->proto->test_port(pi);
+		parport_release(pi->pardev);
+	} else {
+		max = pi->proto->max_mode;
+	}
+
+	if (pi->proto->probe_unit) {
+		parport_claim_or_block(pi->pardev);
+		for (pi->unit = s; pi->unit < e; pi->unit++) {
+			if (pi->proto->probe_unit(pi)) {
+				parport_release(pi->pardev);
+				return pi_probe_mode(pi, max);
+			}
+		}
+		parport_release(pi->pardev);
+		return false;
+	}
+
+	return pi_probe_mode(pi, max);
+}
+
+static void pata_parport_dev_release(struct device *dev)
+{
+	struct pi_adapter *pi = container_of(dev, struct pi_adapter, dev);
+
+	ida_free(&pata_parport_bus_dev_ids, dev->id);
+	kfree(pi);
+}
+
+static void pata_parport_bus_release(struct device *dev)
+{
+	/* nothing to do here but required to avoid warning on device removal */
+}
+
+static const struct bus_type pata_parport_bus_type = {
+	.name = DRV_NAME,
+};
+
+static struct device pata_parport_bus = {
+	.init_name = DRV_NAME,
+	.release = pata_parport_bus_release,
+};
+
+static const struct scsi_host_template pata_parport_sht = {
+	PATA_PARPORT_SHT("pata_parport")
+};
+
+struct pi_device_match {
+	struct parport *parport;
+	struct pi_protocol *proto;
+};
+
+static int pi_find_dev(struct device *dev, void *data)
+{
+	struct pi_adapter *pi = container_of(dev, struct pi_adapter, dev);
+	struct pi_device_match *match = data;
+
+	return pi->pardev->port == match->parport && pi->proto == match->proto;
+}
+
+static struct pi_adapter *pi_init_one(struct parport *parport,
+			struct pi_protocol *pr, int mode, int unit, int delay)
+{
+	struct pardev_cb par_cb = { };
+	const struct ata_port_info *ppi[] = { &pata_parport_port_info };
+	struct ata_host *host;
+	struct pi_adapter *pi;
+	struct pi_device_match match = { .parport = parport, .proto = pr };
+	int id;
+
+	/*
+	 * Abort if there's a device already registered on the same parport
+	 * using the same protocol.
+	 */
+	if (bus_for_each_dev(&pata_parport_bus_type, NULL, &match, pi_find_dev))
+		return NULL;
+
+	id = ida_alloc(&pata_parport_bus_dev_ids, GFP_KERNEL);
+	if (id < 0)
+		return NULL;
+
+	pi = kzalloc(sizeof(struct pi_adapter), GFP_KERNEL);
+	if (!pi) {
+		ida_free(&pata_parport_bus_dev_ids, id);
+		return NULL;
+	}
+
+	/* set up pi->dev before pi_probe_unit() so it can use dev_printk() */
+	pi->dev.parent = &pata_parport_bus;
+	pi->dev.bus = &pata_parport_bus_type;
+	pi->dev.driver = &pr->driver;
+	pi->dev.release = pata_parport_dev_release;
+	pi->dev.id = id;
+	dev_set_name(&pi->dev, "pata_parport.%u", pi->dev.id);
+	if (device_register(&pi->dev)) {
+		put_device(&pi->dev);
+		/* pata_parport_dev_release will do ida_free(dev->id) and kfree(pi) */
+		return NULL;
+	}
+
+	pi->proto = pr;
+
+	if (!try_module_get(pi->proto->owner))
+		goto out_unreg_dev;
+	if (pi->proto->init_proto && pi->proto->init_proto(pi) < 0)
+		goto out_module_put;
+
+	pi->delay = (delay == -1) ? pi->proto->default_delay : delay;
+	pi->mode = mode;
+	pi->port = parport->base;
+
+	par_cb.private = pi;
+	pi->pardev = parport_register_dev_model(parport, DRV_NAME, &par_cb, id);
+	if (!pi->pardev)
+		goto out_module_put;
+
+	if (!pi_probe_unit(pi, unit)) {
+		dev_info(&pi->dev, "Adapter not found\n");
+		goto out_unreg_parport;
+	}
+
+	pi->proto->log_adapter(pi);
+
+	host = ata_host_alloc_pinfo(&pi->pardev->dev, ppi, 1);
+	if (!host)
+		goto out_unreg_parport;
+	dev_set_drvdata(&pi->dev, host);
+	host->private_data = pi;
+
+	ata_port_desc(host->ports[0], "port %s", pi->pardev->port->name);
+	ata_port_desc(host->ports[0], "protocol %s", pi->proto->name);
+
+	pi_connect(pi);
+	if (ata_host_activate(host, 0, NULL, 0, &pata_parport_sht))
+		goto out_disconnect;
+
+	return pi;
+
+out_disconnect:
+	pi_disconnect(pi);
+out_unreg_parport:
+	parport_unregister_device(pi->pardev);
+	if (pi->proto->release_proto)
+		pi->proto->release_proto(pi);
+out_module_put:
+	module_put(pi->proto->owner);
+out_unreg_dev:
+	device_unregister(&pi->dev);
+	/* pata_parport_dev_release will do ida_free(dev->id) and kfree(pi) */
+	return NULL;
+}
+
+int pata_parport_register_driver(struct pi_protocol *pr)
+{
+	int error;
+	struct parport *parport;
+	int port_num;
+
+	pr->driver.bus = &pata_parport_bus_type;
+	pr->driver.name = pr->name;
+	error = driver_register(&pr->driver);
+	if (error)
+		return error;
+
+	mutex_lock(&pi_mutex);
+	error = idr_alloc(&protocols, pr, 0, 0, GFP_KERNEL);
+	if (error < 0) {
+		driver_unregister(&pr->driver);
+		mutex_unlock(&pi_mutex);
+		return error;
+	}
+
+	pr_info("pata_parport: protocol %s registered\n", pr->name);
+
+	if (probe) {
+		/* probe all parports using this protocol */
+		idr_for_each_entry(&parport_list, parport, port_num)
+			pi_init_one(parport, pr, -1, -1, -1);
+	}
+	mutex_unlock(&pi_mutex);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(pata_parport_register_driver);
+
+void pata_parport_unregister_driver(struct pi_protocol *pr)
+{
+	struct pi_protocol *pr_iter;
+	int id = -1;
+
+	mutex_lock(&pi_mutex);
+	idr_for_each_entry(&protocols, pr_iter, id) {
+		if (pr_iter == pr)
+			break;
+	}
+	idr_remove(&protocols, id);
+	mutex_unlock(&pi_mutex);
+	driver_unregister(&pr->driver);
+}
+EXPORT_SYMBOL_GPL(pata_parport_unregister_driver);
+
+static ssize_t new_device_store(const struct bus_type *bus, const char *buf, size_t count)
+{
+	char port[12] = "auto";
+	char protocol[8] = "auto";
+	int mode = -1, unit = -1, delay = -1;
+	struct pi_protocol *pr, *pr_wanted;
+	struct device_driver *drv;
+	struct parport *parport;
+	int port_num, port_wanted, pr_num;
+	bool ok = false;
+
+	if (sscanf(buf, "%11s %7s %d %d %d",
+			port, protocol, &mode, &unit, &delay) < 1)
+		return -EINVAL;
+
+	if (sscanf(port, "parport%u", &port_wanted) < 1) {
+		if (strcmp(port, "auto")) {
+			pr_err("invalid port name %s\n", port);
+			return -EINVAL;
+		}
+		port_wanted = -1;
+	}
+
+	drv = driver_find(protocol, &pata_parport_bus_type);
+	if (!drv) {
+		if (strcmp(protocol, "auto")) {
+			pr_err("protocol %s not found\n", protocol);
+			return -EINVAL;
+		}
+		pr_wanted = NULL;
+	} else {
+		pr_wanted = container_of(drv, struct pi_protocol, driver);
+	}
+
+	mutex_lock(&pi_mutex);
+	/* walk all parports */
+	idr_for_each_entry(&parport_list, parport, port_num) {
+		if (port_num == port_wanted || port_wanted == -1) {
+			parport = parport_find_number(port_num);
+			if (!parport) {
+				pr_err("no such port %s\n", port);
+				mutex_unlock(&pi_mutex);
+				return -ENODEV;
+			}
+			/* walk all protocols */
+			idr_for_each_entry(&protocols, pr, pr_num) {
+				if (pr == pr_wanted || !pr_wanted)
+					if (pi_init_one(parport, pr, mode, unit,
+							delay))
+						ok = true;
+			}
+			parport_put_port(parport);
+		}
+	}
+	mutex_unlock(&pi_mutex);
+	if (!ok)
+		return -ENODEV;
+
+	return count;
+}
+static BUS_ATTR_WO(new_device);
+
+static void pi_remove_one(struct device *dev)
+{
+	struct ata_host *host = dev_get_drvdata(dev);
+	struct pi_adapter *pi = host->private_data;
+
+	ata_host_detach(host);
+	pi_disconnect(pi);
+	pi_release(pi);
+	device_unregister(dev);
+	/* pata_parport_dev_release will do ida_free(dev->id) and kfree(pi) */
+}
+
+static ssize_t delete_device_store(const struct bus_type *bus, const char *buf, size_t count)
+{
+	struct device *dev;
+
+	mutex_lock(&pi_mutex);
+	dev = bus_find_device_by_name(bus, NULL, buf);
+	if (!dev) {
+		mutex_unlock(&pi_mutex);
+		return -ENODEV;
+	}
+
+	pi_remove_one(dev);
+	put_device(dev);
+	mutex_unlock(&pi_mutex);
+
+	return count;
+}
+static BUS_ATTR_WO(delete_device);
+
+static void pata_parport_attach(struct parport *port)
+{
+	struct pi_protocol *pr;
+	int pr_num, id;
+
+	mutex_lock(&pi_mutex);
+	id = idr_alloc(&parport_list, port, port->number, port->number,
+		       GFP_KERNEL);
+	if (id < 0) {
+		mutex_unlock(&pi_mutex);
+		return;
+	}
+
+	if (probe) {
+		/* probe this port using all protocols */
+		idr_for_each_entry(&protocols, pr, pr_num)
+			pi_init_one(port, pr, -1, -1, -1);
+	}
+	mutex_unlock(&pi_mutex);
+}
+
+static int pi_remove_port(struct device *dev, void *p)
+{
+	struct ata_host *host = dev_get_drvdata(dev);
+	struct pi_adapter *pi = host->private_data;
+
+	if (pi->pardev->port == p)
+		pi_remove_one(dev);
+
+	return 0;
+}
+
+static void pata_parport_detach(struct parport *port)
+{
+	mutex_lock(&pi_mutex);
+	bus_for_each_dev(&pata_parport_bus_type, NULL, port, pi_remove_port);
+	idr_remove(&parport_list, port->number);
+	mutex_unlock(&pi_mutex);
+}
+
+static struct parport_driver pata_parport_driver = {
+	.name = DRV_NAME,
+	.match_port = pata_parport_attach,
+	.detach = pata_parport_detach,
+};
+
+static __init int pata_parport_init(void)
+{
+	int error;
+
+	error = bus_register(&pata_parport_bus_type);
+	if (error) {
+		pr_err("failed to register pata_parport bus, error: %d\n", error);
+		return error;
+	}
+
+	error = device_register(&pata_parport_bus);
+	if (error) {
+		pr_err("failed to register pata_parport bus, error: %d\n", error);
+		goto out_unregister_bus;
+	}
+
+	error = bus_create_file(&pata_parport_bus_type, &bus_attr_new_device);
+	if (error) {
+		pr_err("unable to create sysfs file, error: %d\n", error);
+		goto out_unregister_dev;
+	}
+
+	error = bus_create_file(&pata_parport_bus_type, &bus_attr_delete_device);
+	if (error) {
+		pr_err("unable to create sysfs file, error: %d\n", error);
+		goto out_remove_new;
+	}
+
+	error = parport_register_driver(&pata_parport_driver);
+	if (error) {
+		pr_err("unable to register parport driver, error: %d\n", error);
+		goto out_remove_del;
+	}
+
+	return 0;
+
+out_remove_del:
+	bus_remove_file(&pata_parport_bus_type, &bus_attr_delete_device);
+out_remove_new:
+	bus_remove_file(&pata_parport_bus_type, &bus_attr_new_device);
+out_unregister_dev:
+	device_unregister(&pata_parport_bus);
+out_unregister_bus:
+	bus_unregister(&pata_parport_bus_type);
+	return error;
+}
+
+static __exit void pata_parport_exit(void)
+{
+	parport_unregister_driver(&pata_parport_driver);
+	bus_remove_file(&pata_parport_bus_type, &bus_attr_new_device);
+	bus_remove_file(&pata_parport_bus_type, &bus_attr_delete_device);
+	device_unregister(&pata_parport_bus);
+	bus_unregister(&pata_parport_bus_type);
+}
+
+MODULE_AUTHOR("Ondrej Zary");
+MODULE_DESCRIPTION("driver for parallel port ATA adapters");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("paride");
+
+module_init(pata_parport_init);
+module_exit(pata_parport_exit);
diff --git a/drivers/ata/pata_parport/pata_parport.h b/drivers/ata/pata_parport/pata_parport.h
new file mode 100644
index 000000000000..bbfa4e63ee85
--- /dev/null
+++ b/drivers/ata/pata_parport/pata_parport.h
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ *	pata_parport.h	(c) 1997-8  Grant R. Guenther <grant@torque.net>
+ *				    Under the terms of the GPL.
+ *
+ * This file defines the interface for parallel port IDE adapter chip drivers.
+ */
+
+#ifndef LINUX_PATA_PARPORT_H
+#define LINUX_PATA_PARPORT_H
+
+#include <linux/libata.h>
+
+struct pi_adapter {
+	struct device dev;
+	struct pi_protocol *proto;	/* adapter protocol */
+	int port;			/* base address of parallel port */
+	int mode;			/* transfer mode in use */
+	int delay;			/* adapter delay setting */
+	int unit;			/* unit number for chained adapters */
+	int saved_r0;			/* saved port state */
+	int saved_r2;			/* saved port state */
+	unsigned long private;		/* for protocol module */
+	struct pardevice *pardev;	/* pointer to pardevice */
+};
+
+/* registers are addressed as (cont,regr)
+ *	cont: 0 for command register file, 1 for control register(s)
+ *	regr: 0-7 for register number.
+ */
+
+/* macros and functions exported to the protocol modules */
+#define delay_p			(pi->delay ? udelay(pi->delay) : (void)0)
+#define out_p(offs, byte)	do { outb(byte, pi->port + offs); delay_p; } while (0)
+#define in_p(offs)		(delay_p, inb(pi->port + offs))
+
+#define w0(byte)		out_p(0, byte)
+#define r0()			in_p(0)
+#define w1(byte)		out_p(1, byte)
+#define r1()			in_p(1)
+#define w2(byte)		out_p(2, byte)
+#define r2()			in_p(2)
+#define w3(byte)		out_p(3, byte)
+#define w4(byte)		out_p(4, byte)
+#define r4()			in_p(4)
+#define w4w(data)		do { outw(data, pi->port + 4); delay_p; } while (0)
+#define w4l(data)		do { outl(data, pi->port + 4); delay_p; } while (0)
+#define r4w()			(delay_p, inw(pi->port + 4))
+#define r4l()			(delay_p, inl(pi->port + 4))
+
+struct pi_protocol {
+	char name[8];
+
+	int max_mode;
+	int epp_first;		/* modes >= this use 8 ports */
+
+	int default_delay;
+	int max_units;		/* max chained units probed for */
+
+	void (*write_regr)(struct pi_adapter *pi, int cont, int regr, int val);
+	int (*read_regr)(struct pi_adapter *pi, int cont, int regr);
+	void (*write_block)(struct pi_adapter *pi, char *buf, int count);
+	void (*read_block)(struct pi_adapter *pi, char *buf, int count);
+
+	void (*connect)(struct pi_adapter *pi);
+	void (*disconnect)(struct pi_adapter *pi);
+
+	int (*test_port)(struct pi_adapter *pi);
+	int (*probe_unit)(struct pi_adapter *pi);
+	int (*test_proto)(struct pi_adapter *pi);
+	void (*log_adapter)(struct pi_adapter *pi);
+
+	int (*init_proto)(struct pi_adapter *pi);
+	void (*release_proto)(struct pi_adapter *pi);
+	struct module *owner;
+	struct device_driver driver;
+	struct scsi_host_template sht;
+};
+
+#define PATA_PARPORT_SHT ATA_PIO_SHT
+
+int pata_parport_register_driver(struct pi_protocol *pr);
+void pata_parport_unregister_driver(struct pi_protocol *pr);
+
+/**
+ * module_pata_parport_driver() - Helper macro for registering a pata_parport driver
+ * @__pi_protocol: pi_protocol struct
+ *
+ * Helper macro for pata_parport drivers which do not do anything special in module
+ * init/exit. This eliminates a lot of boilerplate. Each module may only
+ * use this macro once, and calling it replaces module_init() and module_exit()
+ */
+#define module_pata_parport_driver(__pi_protocol) \
+	module_driver(__pi_protocol, pata_parport_register_driver, pata_parport_unregister_driver)
+
+#endif /* LINUX_PATA_PARPORT_H */
diff --git a/drivers/ata/pata_pcmcia.c b/drivers/ata/pata_pcmcia.c
index 8eb066abbd9c..caefcd8c4b3c 100644
--- a/drivers/ata/pata_pcmcia.c
+++ b/drivers/ata/pata_pcmcia.c
@@ -46,7 +46,7 @@ static int pcmcia_set_mode(struct ata_link *link, struct ata_device **r_failed_d
 	struct ata_device *slave = &link->device[1];
 
 	if (!ata_dev_enabled(master) || !ata_dev_enabled(slave))
-		return ata_do_set_mode(link, r_failed_dev);
+		return ata_set_mode(link, r_failed_dev);
 
 	if (memcmp(master->id + ATA_ID_FW_REV,  slave->id + ATA_ID_FW_REV,
 			   ATA_ID_FW_REV_LEN + ATA_ID_PROD_LEN) == 0) {
@@ -58,7 +58,7 @@ static int pcmcia_set_mode(struct ata_link *link, struct ata_device **r_failed_d
 			ata_dev_disable(slave);
 		}
 	}
-	return ata_do_set_mode(link, r_failed_dev);
+	return ata_set_mode(link, r_failed_dev);
 }
 
 /**
@@ -132,7 +132,7 @@ static void pcmcia_8bit_drain_fifo(struct ata_queued_cmd *qc)
 
 }
 
-static struct scsi_host_template pcmcia_sht = {
+static const struct scsi_host_template pcmcia_sht = {
 	ATA_PIO_SHT(DRV_NAME),
 };
 
@@ -344,6 +344,7 @@ static const struct pcmcia_device_id pcmcia_devices[] = {
 	PCMCIA_DEVICE_PROD_ID2("NinjaATA-", 0xebe0bd79),
 	PCMCIA_DEVICE_PROD_ID12("PCMCIA", "CD-ROM", 0x281f1c5d, 0x66536591),
 	PCMCIA_DEVICE_PROD_ID12("PCMCIA", "PnPIDE", 0x281f1c5d, 0x0c694728),
+	PCMCIA_DEVICE_PROD_ID2("PCMCIA ATA/ATAPI Adapter", 0x888d7b73),
 	PCMCIA_DEVICE_PROD_ID12("SHUTTLE TECHNOLOGY LTD.", "PCCARD-IDE/ATAPI Adapter", 0x4a3f0ba0, 0x322560e1),
 	PCMCIA_DEVICE_PROD_ID12("SEAGATE", "ST1", 0x87c1b330, 0xe1f30883),
 	PCMCIA_DEVICE_PROD_ID12("SAMSUNG", "04/05/06", 0x43d74cb4, 0x6a22777d),
diff --git a/drivers/ata/pata_pdc2027x.c b/drivers/ata/pata_pdc2027x.c
index de834fbb6dfe..ae914dcb0c83 100644
--- a/drivers/ata/pata_pdc2027x.c
+++ b/drivers/ata/pata_pdc2027x.c
@@ -30,13 +30,6 @@
 
 #define DRV_NAME	"pata_pdc2027x"
 #define DRV_VERSION	"1.0"
-#undef PDC_DEBUG
-
-#ifdef PDC_DEBUG
-#define PDPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
-#else
-#define PDPRINTK(fmt, args...)
-#endif
 
 enum {
 	PDC_MMIO_BAR		= 5,
@@ -64,7 +57,7 @@ static int pdc2027x_prereset(struct ata_link *link, unsigned long deadline);
 static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev);
 static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev);
 static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc);
-static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask);
+static unsigned int pdc2027x_mode_filter(struct ata_device *adev, unsigned int mask);
 static int pdc2027x_cable_detect(struct ata_port *ap);
 static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed);
 
@@ -129,7 +122,7 @@ static struct pci_driver pdc2027x_pci_driver = {
 #endif
 };
 
-static struct scsi_host_template pdc2027x_sht = {
+static const struct scsi_host_template pdc2027x_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
@@ -137,7 +130,7 @@ static struct ata_port_operations pdc2027x_pata100_ops = {
 	.inherits		= &ata_bmdma_port_ops,
 	.check_atapi_dma	= pdc2027x_check_atapi_dma,
 	.cable_detect		= pdc2027x_cable_detect,
-	.prereset		= pdc2027x_prereset,
+	.reset.prereset		= pdc2027x_prereset,
 };
 
 static struct ata_port_operations pdc2027x_pata133_ops = {
@@ -196,7 +189,7 @@ static inline void __iomem *dev_mmio(struct ata_port *ap, struct ata_device *ade
 }
 
 /**
- *	pdc2027x_pata_cable_detect - Probe host controller cable detect info
+ *	pdc2027x_cable_detect - Probe host controller cable detect info
  *	@ap: Port for which cable detect info is desired
  *
  *	Read 80c cable indicator from Promise extended register.
@@ -214,11 +207,11 @@ static int pdc2027x_cable_detect(struct ata_port *ap)
 	if (cgcr & (1 << 26))
 		goto cbl40;
 
-	PDPRINTK("No cable or 80-conductor cable on port %d\n", ap->port_no);
+	ata_port_dbg(ap, "No cable or 80-conductor cable\n");
 
 	return ATA_CBL_PATA80;
 cbl40:
-	printk(KERN_INFO DRV_NAME ": 40-conductor cable detected on port %d\n", ap->port_no);
+	ata_port_info(ap, DRV_NAME ":40-conductor cable detected\n");
 	return ATA_CBL_PATA40;
 }
 
@@ -251,14 +244,14 @@ static int pdc2027x_prereset(struct ata_link *link, unsigned long deadline)
 }
 
 /**
- *	pdc2720x_mode_filter	-	mode selection filter
+ *	pdc2027x_mode_filter	-	mode selection filter
  *	@adev: ATA device
  *	@mask: list of modes proposed
  *
  *	Block UDMA on devices that cause trouble with this controller.
  */
 
-static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask)
+static unsigned int pdc2027x_mode_filter(struct ata_device *adev, unsigned int mask)
 {
 	unsigned char model_num[ATA_ID_PROD_LEN + 1];
 	struct ata_device *pair = ata_dev_pair(adev);
@@ -292,17 +285,17 @@ static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev)
 	unsigned int pio = adev->pio_mode - XFER_PIO_0;
 	u32 ctcr0, ctcr1;
 
-	PDPRINTK("adev->pio_mode[%X]\n", adev->pio_mode);
+	ata_port_dbg(ap, "adev->pio_mode[%X]\n", adev->pio_mode);
 
 	/* Sanity check */
 	if (pio > 4) {
-		printk(KERN_ERR DRV_NAME ": Unknown pio mode [%d] ignored\n", pio);
+		ata_port_err(ap, "Unknown pio mode [%d] ignored\n", pio);
 		return;
 
 	}
 
 	/* Set the PIO timing registers using value table for 133MHz */
-	PDPRINTK("Set pio regs... \n");
+	ata_port_dbg(ap, "Set PIO regs...\n");
 
 	ctcr0 = ioread32(dev_mmio(ap, adev, PDC_CTCR0));
 	ctcr0 &= 0xffff0000;
@@ -315,9 +308,7 @@ static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev)
 	ctcr1 |= (pdc2027x_pio_timing_tbl[pio].value2 << 24);
 	iowrite32(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
 
-	PDPRINTK("Set pio regs done\n");
-
-	PDPRINTK("Set to pio mode[%u] \n", pio);
+	ata_port_dbg(ap, "Set to PIO mode[%u]\n", pio);
 }
 
 /**
@@ -350,7 +341,7 @@ static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 			iowrite32(ctcr1 & ~(1 << 7), dev_mmio(ap, adev, PDC_CTCR1));
 		}
 
-		PDPRINTK("Set udma regs... \n");
+		ata_port_dbg(ap, "Set UDMA regs...\n");
 
 		ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1));
 		ctcr1 &= 0xff000000;
@@ -359,16 +350,14 @@ static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 			(pdc2027x_udma_timing_tbl[udma_mode].value2 << 16);
 		iowrite32(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
 
-		PDPRINTK("Set udma regs done\n");
-
-		PDPRINTK("Set to udma mode[%u] \n", udma_mode);
+		ata_port_dbg(ap, "Set to UDMA mode[%u]\n", udma_mode);
 
 	} else  if ((dma_mode >= XFER_MW_DMA_0) &&
 		   (dma_mode <= XFER_MW_DMA_2)) {
 		/* Set the MDMA timing registers with value table for 133MHz */
 		unsigned int mdma_mode = dma_mode & 0x07;
 
-		PDPRINTK("Set mdma regs... \n");
+		ata_port_dbg(ap, "Set MDMA regs...\n");
 		ctcr0 = ioread32(dev_mmio(ap, adev, PDC_CTCR0));
 
 		ctcr0 &= 0x0000ffff;
@@ -376,11 +365,10 @@ static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 			(pdc2027x_mdma_timing_tbl[mdma_mode].value1 << 24);
 
 		iowrite32(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
-		PDPRINTK("Set mdma regs done\n");
 
-		PDPRINTK("Set to mdma mode[%u] \n", mdma_mode);
+		ata_port_dbg(ap, "Set to MDMA mode[%u]\n", mdma_mode);
 	} else {
-		printk(KERN_ERR DRV_NAME ": Unknown dma mode [%u] ignored\n", dma_mode);
+		ata_port_err(ap, "Unknown dma mode [%u] ignored\n", dma_mode);
 	}
 }
 
@@ -399,7 +387,7 @@ static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed
 	struct ata_device *dev;
 	int rc;
 
-	rc = ata_do_set_mode(link, r_failed);
+	rc = ata_set_mode(link, r_failed);
 	if (rc < 0)
 		return rc;
 
@@ -414,7 +402,7 @@ static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed
 			ctcr1 |= (1 << 25);
 			iowrite32(ctcr1, dev_mmio(ap, dev, PDC_CTCR1));
 
-			PDPRINTK("Turn on prefetch\n");
+			ata_dev_dbg(dev, "Turn on prefetch\n");
 		} else {
 			pdc2027x_set_dmamode(ap, dev);
 		}
@@ -485,8 +473,8 @@ retry:
 
 	counter = (bccrh << 15) | bccrl;
 
-	PDPRINTK("bccrh [%X] bccrl [%X]\n", bccrh,  bccrl);
-	PDPRINTK("bccrhv[%X] bccrlv[%X]\n", bccrhv, bccrlv);
+	dev_dbg(host->dev, "bccrh [%X] bccrl [%X]\n", bccrh,  bccrl);
+	dev_dbg(host->dev, "bccrhv[%X] bccrlv[%X]\n", bccrhv, bccrlv);
 
 	/*
 	 * The 30-bit decreasing counter are read by 2 pieces.
@@ -495,7 +483,7 @@ retry:
 	 */
 	if (retry && !(bccrh == bccrhv && bccrl >= bccrlv)) {
 		retry--;
-		PDPRINTK("rereading counter\n");
+		dev_dbg(host->dev, "rereading counter\n");
 		goto retry;
 	}
 
@@ -503,11 +491,11 @@ retry:
 }
 
 /**
- * adjust_pll - Adjust the PLL input clock in Hz.
+ * pdc_adjust_pll - Adjust the PLL input clock in Hz.
  *
- * @pdc_controller: controller specific information
  * @host: target ATA host
  * @pll_clock: The input of PLL in HZ
+ * @board_idx: board identifier
  */
 static void pdc_adjust_pll(struct ata_host *host, long pll_clock, unsigned int board_idx)
 {
@@ -520,20 +508,19 @@ static void pdc_adjust_pll(struct ata_host *host, long pll_clock, unsigned int b
 
 	/* Sanity check */
 	if (unlikely(pll_clock_khz < 5000L || pll_clock_khz > 70000L)) {
-		printk(KERN_ERR DRV_NAME ": Invalid PLL input clock %ldkHz, give up!\n", pll_clock_khz);
+		dev_err(host->dev, "Invalid PLL input clock %ldkHz, give up!\n",
+			pll_clock_khz);
 		return;
 	}
 
-#ifdef PDC_DEBUG
-	PDPRINTK("pout_required is %ld\n", pout_required);
+	dev_dbg(host->dev, "pout_required is %ld\n", pout_required);
 
 	/* Show the current clock value of PLL control register
 	 * (maybe already configured by the firmware)
 	 */
 	pll_ctl = ioread16(mmio_base + PDC_PLL_CTL);
 
-	PDPRINTK("pll_ctl[%X]\n", pll_ctl);
-#endif
+	dev_dbg(host->dev, "pll_ctl[%X]\n", pll_ctl);
 
 	/*
 	 * Calculate the ratio of F, R and OD
@@ -552,7 +539,7 @@ static void pdc_adjust_pll(struct ata_host *host, long pll_clock, unsigned int b
 		R = 0x00;
 	} else {
 		/* Invalid ratio */
-		printk(KERN_ERR DRV_NAME ": Invalid ratio %ld, give up!\n", ratio);
+		dev_err(host->dev, "Invalid ratio %ld, give up!\n", ratio);
 		return;
 	}
 
@@ -560,15 +547,15 @@ static void pdc_adjust_pll(struct ata_host *host, long pll_clock, unsigned int b
 
 	if (unlikely(F < 0 || F > 127)) {
 		/* Invalid F */
-		printk(KERN_ERR DRV_NAME ": F[%d] invalid!\n", F);
+		dev_err(host->dev, "F[%d] invalid!\n", F);
 		return;
 	}
 
-	PDPRINTK("F[%d] R[%d] ratio*1000[%ld]\n", F, R, ratio);
+	dev_dbg(host->dev, "F[%d] R[%d] ratio*1000[%ld]\n", F, R, ratio);
 
 	pll_ctl = (R << 8) | F;
 
-	PDPRINTK("Writing pll_ctl[%X]\n", pll_ctl);
+	dev_dbg(host->dev, "Writing pll_ctl[%X]\n", pll_ctl);
 
 	iowrite16(pll_ctl, mmio_base + PDC_PLL_CTL);
 	ioread16(mmio_base + PDC_PLL_CTL); /* flush */
@@ -576,21 +563,19 @@ static void pdc_adjust_pll(struct ata_host *host, long pll_clock, unsigned int b
 	/* Wait the PLL circuit to be stable */
 	msleep(30);
 
-#ifdef PDC_DEBUG
 	/*
 	 *  Show the current clock value of PLL control register
 	 * (maybe configured by the firmware)
 	 */
 	pll_ctl = ioread16(mmio_base + PDC_PLL_CTL);
 
-	PDPRINTK("pll_ctl[%X]\n", pll_ctl);
-#endif
+	dev_dbg(host->dev, "pll_ctl[%X]\n", pll_ctl);
 
 	return;
 }
 
 /**
- * detect_pll_input_clock - Detect the PLL input clock in Hz.
+ * pdc_detect_pll_input_clock - Detect the PLL input clock in Hz.
  * @host: target ATA host
  * Ex. 16949000 on 33MHz PCI bus for pdc20275.
  *     Half of the PCI clock.
@@ -605,7 +590,7 @@ static long pdc_detect_pll_input_clock(struct ata_host *host)
 
 	/* Start the test mode */
 	scr = ioread32(mmio_base + PDC_SYS_CTL);
-	PDPRINTK("scr[%X]\n", scr);
+	dev_dbg(host->dev, "scr[%X]\n", scr);
 	iowrite32(scr | (0x01 << 14), mmio_base + PDC_SYS_CTL);
 	ioread32(mmio_base + PDC_SYS_CTL); /* flush */
 
@@ -622,7 +607,7 @@ static long pdc_detect_pll_input_clock(struct ata_host *host)
 
 	/* Stop the test mode */
 	scr = ioread32(mmio_base + PDC_SYS_CTL);
-	PDPRINTK("scr[%X]\n", scr);
+	dev_dbg(host->dev, "scr[%X]\n", scr);
 	iowrite32(scr & ~(0x01 << 14), mmio_base + PDC_SYS_CTL);
 	ioread32(mmio_base + PDC_SYS_CTL); /* flush */
 
@@ -632,8 +617,8 @@ static long pdc_detect_pll_input_clock(struct ata_host *host)
 	pll_clock = ((start_count - end_count) & 0x3fffffff) / 100 *
 		(100000000 / usec_elapsed);
 
-	PDPRINTK("start[%ld] end[%ld] \n", start_count, end_count);
-	PDPRINTK("PLL input clock[%ld]Hz\n", pll_clock);
+	dev_dbg(host->dev, "start[%ld] end[%ld] PLL input clock[%ld]HZ\n",
+		     start_count, end_count, pll_clock);
 
 	return pll_clock;
 }
diff --git a/drivers/ata/pata_pdc202xx_old.c b/drivers/ata/pata_pdc202xx_old.c
index 378ed9ea97e9..a32723e46357 100644
--- a/drivers/ata/pata_pdc202xx_old.c
+++ b/drivers/ata/pata_pdc202xx_old.c
@@ -38,8 +38,6 @@ static int pdc2026x_cable_detect(struct ata_port *ap)
 static void pdc202xx_exec_command(struct ata_port *ap,
 				  const struct ata_taskfile *tf)
 {
-	DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
-
 	iowrite8(tf->command, ap->ioaddr.command_addr);
 	ndelay(400);
 }
@@ -80,7 +78,7 @@ static void pdc202xx_configure_piomode(struct ata_port *ap, struct ata_device *a
 {
 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 	int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
-	static u16 pio_timing[5] = {
+	static const u16 pio_timing[5] = {
 		0x0913, 0x050C , 0x0308, 0x0206, 0x0104
 	};
 	u8 r_ap, r_bp;
@@ -115,7 +113,7 @@ static void pdc202xx_set_piomode(struct ata_port *ap, struct ata_device *adev)
 }
 
 /**
- *	pdc202xx_configure_dmamode	-	set DMA mode in chip
+ *	pdc202xx_set_dmamode	-	set DMA mode in chip
  *	@ap: ATA interface
  *	@adev: ATA device
  *
@@ -214,7 +212,7 @@ static void pdc2026x_bmdma_start(struct ata_queued_cmd *qc)
 }
 
 /**
- *	pdc2026x_bmdma_end		-	DMA engine stop
+ *	pdc2026x_bmdma_stop		-	DMA engine stop
  *	@qc: ATA command
  *
  *	After a DMA completes we need to put the clock back to 33MHz for
@@ -291,7 +289,7 @@ static int pdc2026x_check_atapi_dma(struct ata_queued_cmd *qc)
 	return 1;
 }
 
-static struct scsi_host_template pdc202xx_sht = {
+static const struct scsi_host_template pdc202xx_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
diff --git a/drivers/ata/pata_piccolo.c b/drivers/ata/pata_piccolo.c
index 35cb0e263237..beb53bd990be 100644
--- a/drivers/ata/pata_piccolo.c
+++ b/drivers/ata/pata_piccolo.c
@@ -62,7 +62,7 @@ static void tosh_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 }
 
 
-static struct scsi_host_template tosh_sht = {
+static const struct scsi_host_template tosh_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
@@ -74,7 +74,7 @@ static struct ata_port_operations tosh_port_ops = {
 };
 
 /**
- *	ata_tosh_init		-	attach generic IDE
+ *	ata_tosh_init_one		-	attach generic IDE
  *	@dev: PCI device found
  *	@id: match entry
  *
@@ -97,7 +97,7 @@ static int ata_tosh_init_one(struct pci_dev *dev, const struct pci_device_id *id
 	return ata_pci_bmdma_init_one(dev, ppi, &tosh_sht, NULL, 0);
 }
 
-static struct pci_device_id ata_tosh[] = {
+static const struct pci_device_id ata_tosh[] = {
 	{ PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_1), },
 	{ PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_2),  },
 	{ PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_3),  },
diff --git a/drivers/ata/pata_platform.c b/drivers/ata/pata_platform.c
index 5aba691f09af..87479bc893b2 100644
--- a/drivers/ata/pata_platform.c
+++ b/drivers/ata/pata_platform.c
@@ -24,6 +24,8 @@
 #define DRV_VERSION "1.2"
 
 static int pio_mask = 1;
+module_param(pio_mask, int, 0);
+MODULE_PARM_DESC(pio_mask, "PIO modes supported, mode 0 only by default");
 
 /*
  * Provide our own set_mode() as we don't want to change anything that has
@@ -43,7 +45,7 @@ static int pata_platform_set_mode(struct ata_link *link, struct ata_device **unu
 	return 0;
 }
 
-static struct scsi_host_template pata_platform_sht = {
+static const struct scsi_host_template pata_platform_sht = {
 	ATA_PIO_SHT(DRV_NAME),
 };
 
@@ -95,7 +97,7 @@ static void pata_platform_setup_port(struct ata_ioports *ioaddr,
 int __pata_platform_probe(struct device *dev, struct resource *io_res,
 			  struct resource *ctl_res, struct resource *irq_res,
 			  unsigned int ioport_shift, int __pio_mask,
-			  struct scsi_host_template *sht, bool use16bit)
+			  const struct scsi_host_template *sht, bool use16bit)
 {
 	struct ata_host *host;
 	struct ata_port *ap;
@@ -126,6 +128,8 @@ int __pata_platform_probe(struct device *dev, struct resource *io_res,
 	ap = host->ports[0];
 
 	ap->ops = devm_kzalloc(dev, sizeof(*ap->ops), GFP_KERNEL);
+	if (!ap->ops)
+		return -ENOMEM;
 	ap->ops->inherits = &ata_sff_port_ops;
 	ap->ops->cable_detect = ata_cable_unknown;
 	ap->ops->set_mode = pata_platform_set_mode;
@@ -196,22 +200,16 @@ static int pata_platform_probe(struct platform_device *pdev)
 	/*
 	 * Get the I/O base first
 	 */
-	io_res = platform_get_resource(pdev, IORESOURCE_IO, 0);
-	if (io_res == NULL) {
-		io_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-		if (unlikely(io_res == NULL))
-			return -EINVAL;
-	}
+	io_res = platform_get_mem_or_io(pdev, 0);
+	if (!io_res)
+		return -EINVAL;
 
 	/*
 	 * Then the CTL base
 	 */
-	ctl_res = platform_get_resource(pdev, IORESOURCE_IO, 1);
-	if (ctl_res == NULL) {
-		ctl_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-		if (unlikely(ctl_res == NULL))
-			return -EINVAL;
-	}
+	ctl_res = platform_get_mem_or_io(pdev, 1);
+	if (!ctl_res)
+		return -EINVAL;
 
 	/*
 	 * And the IRQ
@@ -233,8 +231,6 @@ static struct platform_driver pata_platform_driver = {
 
 module_platform_driver(pata_platform_driver);
 
-module_param(pio_mask, int, 0);
-
 MODULE_AUTHOR("Paul Mundt");
 MODULE_DESCRIPTION("low-level driver for platform device ATA");
 MODULE_LICENSE("GPL");
diff --git a/drivers/ata/pata_pxa.c b/drivers/ata/pata_pxa.c
index 41430f79663c..03dbaf4a13a7 100644
--- a/drivers/ata/pata_pxa.c
+++ b/drivers/ata/pata_pxa.c
@@ -136,7 +136,7 @@ static int pxa_check_atapi_dma(struct ata_queued_cmd *qc)
 	return -EOPNOTSUPP;
 }
 
-static struct scsi_host_template pxa_ata_sht = {
+static const struct scsi_host_template pxa_ata_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
@@ -164,10 +164,10 @@ static int pxa_ata_probe(struct platform_device *pdev)
 	struct resource *cmd_res;
 	struct resource *ctl_res;
 	struct resource *dma_res;
-	struct resource *irq_res;
 	struct pata_pxa_pdata *pdata = dev_get_platdata(&pdev->dev);
 	struct dma_slave_config	config;
 	int ret = 0;
+	int irq;
 
 	/*
 	 * Resource validation, three resources are needed:
@@ -205,9 +205,9 @@ static int pxa_ata_probe(struct platform_device *pdev)
 	/*
 	 * IRQ pin
 	 */
-	irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-	if (unlikely(irq_res == NULL))
-		return -EINVAL;
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0)
+		return irq;
 
 	/*
 	 * Allocate the host
@@ -223,10 +223,16 @@ static int pxa_ata_probe(struct platform_device *pdev)
 
 	ap->ioaddr.cmd_addr	= devm_ioremap(&pdev->dev, cmd_res->start,
 						resource_size(cmd_res));
+	if (!ap->ioaddr.cmd_addr)
+		return -ENOMEM;
 	ap->ioaddr.ctl_addr	= devm_ioremap(&pdev->dev, ctl_res->start,
 						resource_size(ctl_res));
+	if (!ap->ioaddr.ctl_addr)
+		return -ENOMEM;
 	ap->ioaddr.bmdma_addr	= devm_ioremap(&pdev->dev, dma_res->start,
 						resource_size(dma_res));
+	if (!ap->ioaddr.bmdma_addr)
+		return -ENOMEM;
 
 	/*
 	 * Adjust register offsets
@@ -274,10 +280,9 @@ static int pxa_ata_probe(struct platform_device *pdev)
 	/*
 	 * Request the DMA channel
 	 */
-	data->dma_chan =
-		dma_request_slave_channel(&pdev->dev, "data");
-	if (!data->dma_chan)
-		return -EBUSY;
+	data->dma_chan = dma_request_chan(&pdev->dev, "data");
+	if (IS_ERR(data->dma_chan))
+		return PTR_ERR(data->dma_chan);
 	ret = dmaengine_slave_config(data->dma_chan, &config);
 	if (ret < 0) {
 		dev_err(&pdev->dev, "dma configuration failed: %d\n", ret);
@@ -287,7 +292,7 @@ static int pxa_ata_probe(struct platform_device *pdev)
 	/*
 	 * Activate the ATA host
 	 */
-	ret = ata_host_activate(host, irq_res->start, ata_sff_interrupt,
+	ret = ata_host_activate(host, irq, ata_sff_interrupt,
 				pdata->irq_flags, &pxa_ata_sht);
 	if (ret)
 		dma_release_channel(data->dma_chan);
@@ -295,7 +300,7 @@ static int pxa_ata_probe(struct platform_device *pdev)
 	return ret;
 }
 
-static int pxa_ata_remove(struct platform_device *pdev)
+static void pxa_ata_remove(struct platform_device *pdev)
 {
 	struct ata_host *host = platform_get_drvdata(pdev);
 	struct pata_pxa_data *data = host->ports[0]->private_data;
@@ -303,8 +308,6 @@ static int pxa_ata_remove(struct platform_device *pdev)
 	dma_release_channel(data->dma_chan);
 
 	ata_host_detach(host);
-
-	return 0;
 }
 
 static struct platform_driver pxa_ata_driver = {
diff --git a/drivers/ata/pata_radisys.c b/drivers/ata/pata_radisys.c
index 8fde4a86401b..40ef8072c159 100644
--- a/drivers/ata/pata_radisys.c
+++ b/drivers/ata/pata_radisys.c
@@ -45,7 +45,7 @@ static void radisys_set_piomode (struct ata_port *ap, struct ata_device *adev)
 	int control = 0;
 
 	/*
-	 *	See Intel Document 298600-004 for the timing programing rules
+	 *	See Intel Document 298600-004 for the timing programming rules
 	 *	for PIIX/ICH. Note that the early PIIX does not have the slave
 	 *	timing port at 0x44. The Radisys is a relative of the PIIX
 	 *	but not the same so be careful.
@@ -172,8 +172,8 @@ static unsigned int radisys_qc_issue(struct ata_queued_cmd *qc)
 
 	if (adev != ap->private_data) {
 		/* UDMA timing is not shared */
-		if (adev->dma_mode < XFER_UDMA_0) {
-			if (adev->dma_mode)
+		if (adev->dma_mode < XFER_UDMA_0 || !ata_dma_enabled(adev)) {
+			if (ata_dma_enabled(adev))
 				radisys_set_dmamode(ap, adev);
 			else if (adev->pio_mode)
 				radisys_set_piomode(ap, adev);
@@ -183,7 +183,7 @@ static unsigned int radisys_qc_issue(struct ata_queued_cmd *qc)
 }
 
 
-static struct scsi_host_template radisys_sht = {
+static const struct scsi_host_template radisys_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
diff --git a/drivers/ata/pata_rb532_cf.c b/drivers/ata/pata_rb532_cf.c
index 479c4b29b856..fd81e75c9402 100644
--- a/drivers/ata/pata_rb532_cf.c
+++ b/drivers/ata/pata_rb532_cf.c
@@ -73,7 +73,7 @@ static struct ata_port_operations rb532_pata_port_ops = {
 
 /* ------------------------------------------------------------------------ */
 
-static struct scsi_host_template rb532_pata_sht = {
+static const struct scsi_host_template rb532_pata_sht = {
 	ATA_PIO_SHT(DRV_NAME),
 };
 
@@ -115,10 +115,10 @@ static int rb532_pata_driver_probe(struct platform_device *pdev)
 	}
 
 	irq = platform_get_irq(pdev, 0);
-	if (irq <= 0) {
-		dev_err(&pdev->dev, "no IRQ resource found\n");
-		return -ENOENT;
-	}
+	if (irq < 0)
+		return irq;
+	if (!irq)
+		return -EINVAL;
 
 	gpiod = devm_gpiod_get(&pdev->dev, NULL, GPIOD_IN);
 	if (IS_ERR(gpiod)) {
@@ -155,13 +155,11 @@ static int rb532_pata_driver_probe(struct platform_device *pdev)
 	return 0;
 }
 
-static int rb532_pata_driver_remove(struct platform_device *pdev)
+static void rb532_pata_driver_remove(struct platform_device *pdev)
 {
 	struct ata_host *ah = platform_get_drvdata(pdev);
 
 	ata_host_detach(ah);
-
-	return 0;
 }
 
 static struct platform_driver rb532_pata_platform_driver = {
diff --git a/drivers/ata/pata_rdc.c b/drivers/ata/pata_rdc.c
index ecb229c2c1a2..6ff4c11e937d 100644
--- a/drivers/ata/pata_rdc.c
+++ b/drivers/ata/pata_rdc.c
@@ -276,7 +276,7 @@ static struct ata_port_operations rdc_pata_ops = {
 	.cable_detect		= rdc_pata_cable_detect,
 	.set_piomode		= rdc_set_piomode,
 	.set_dmamode		= rdc_set_dmamode,
-	.prereset		= rdc_pata_prereset,
+	.reset.prereset		= rdc_pata_prereset,
 };
 
 static const struct ata_port_info rdc_port_info = {
@@ -288,7 +288,7 @@ static const struct ata_port_info rdc_port_info = {
 	.port_ops	= &rdc_pata_ops,
 };
 
-static struct scsi_host_template rdc_sht = {
+static const struct scsi_host_template rdc_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
@@ -340,7 +340,7 @@ static int rdc_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 		return rc;
 	host->private_data = hpriv;
 
-	pci_intx(pdev, 1);
+	pcim_intx(pdev, 1);
 
 	host->flags |= ATA_HOST_PARALLEL_SCAN;
 
@@ -359,8 +359,8 @@ static void rdc_remove_one(struct pci_dev *pdev)
 }
 
 static const struct pci_device_id rdc_pci_tbl[] = {
-	{ PCI_DEVICE(0x17F3, 0x1011), },
-	{ PCI_DEVICE(0x17F3, 0x1012), },
+	{ PCI_VDEVICE(RDC, 0x1011) },
+	{ PCI_VDEVICE(RDC, 0x1012) },
 	{ }	/* terminate list */
 };
 
diff --git a/drivers/ata/pata_rz1000.c b/drivers/ata/pata_rz1000.c
index 3722a67083fd..8e2606793091 100644
--- a/drivers/ata/pata_rz1000.c
+++ b/drivers/ata/pata_rz1000.c
@@ -50,7 +50,7 @@ static int rz1000_set_mode(struct ata_link *link, struct ata_device **unused)
 }
 
 
-static struct scsi_host_template rz1000_sht = {
+static const struct scsi_host_template rz1000_sht = {
 	ATA_PIO_SHT(DRV_NAME),
 };
 
@@ -69,7 +69,7 @@ static int rz1000_fifo_disable(struct pci_dev *pdev)
 	reg &= 0xDFFF;
 	if (pci_write_config_word(pdev, 0x40, reg) != 0)
 		return -1;
-	printk(KERN_INFO DRV_NAME ": disabled chipset readahead.\n");
+	dev_info(&pdev->dev, "disabled chipset readahead.\n");
 	return 0;
 }
 
@@ -97,7 +97,7 @@ static int rz1000_init_one (struct pci_dev *pdev, const struct pci_device_id *en
 	if (rz1000_fifo_disable(pdev) == 0)
 		return ata_pci_sff_init_one(pdev, ppi, &rz1000_sht, NULL, 0);
 
-	printk(KERN_ERR DRV_NAME ": failed to disable read-ahead on chipset..\n");
+	dev_err(&pdev->dev, "failed to disable read-ahead on chipset.\n");
 	/* Not safe to use so skip */
 	return -ENODEV;
 }
diff --git a/drivers/ata/pata_samsung_cf.c b/drivers/ata/pata_samsung_cf.c
deleted file mode 100644
index 3da0e8e30286..000000000000
--- a/drivers/ata/pata_samsung_cf.c
+++ /dev/null
@@ -1,662 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *		http://www.samsung.com
- *
- * PATA driver for Samsung SoCs.
- * Supports CF Interface in True IDE mode. Currently only PIO mode has been
- * implemented; UDMA support has to be added.
- *
- * Based on:
- *	PATA driver for AT91SAM9260 Static Memory Controller
- *	PATA driver for Toshiba SCC controller
-*/
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/mod_devicetable.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/libata.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-
-#include <linux/platform_data/ata-samsung_cf.h>
-
-#define DRV_NAME "pata_samsung_cf"
-#define DRV_VERSION "0.1"
-
-#define S3C_CFATA_REG(x)	(x)
-#define S3C_CFATA_MUX		S3C_CFATA_REG(0x0)
-#define S3C_ATA_CTRL		S3C_CFATA_REG(0x0)
-#define S3C_ATA_CMD		S3C_CFATA_REG(0x8)
-#define S3C_ATA_IRQ		S3C_CFATA_REG(0x10)
-#define S3C_ATA_IRQ_MSK		S3C_CFATA_REG(0x14)
-#define S3C_ATA_CFG		S3C_CFATA_REG(0x18)
-
-#define S3C_ATA_PIO_TIME	S3C_CFATA_REG(0x2c)
-#define S3C_ATA_PIO_DTR		S3C_CFATA_REG(0x54)
-#define S3C_ATA_PIO_FED		S3C_CFATA_REG(0x58)
-#define S3C_ATA_PIO_SCR		S3C_CFATA_REG(0x5c)
-#define S3C_ATA_PIO_LLR		S3C_CFATA_REG(0x60)
-#define S3C_ATA_PIO_LMR		S3C_CFATA_REG(0x64)
-#define S3C_ATA_PIO_LHR		S3C_CFATA_REG(0x68)
-#define S3C_ATA_PIO_DVR		S3C_CFATA_REG(0x6c)
-#define S3C_ATA_PIO_CSD		S3C_CFATA_REG(0x70)
-#define S3C_ATA_PIO_DAD		S3C_CFATA_REG(0x74)
-#define S3C_ATA_PIO_RDATA	S3C_CFATA_REG(0x7c)
-
-#define S3C_CFATA_MUX_TRUEIDE	0x01
-#define S3C_ATA_CFG_SWAP	0x40
-#define S3C_ATA_CFG_IORDYEN	0x02
-
-enum s3c_cpu_type {
-	TYPE_S3C64XX,
-	TYPE_S5PV210,
-};
-
-/*
- * struct s3c_ide_info - S3C PATA instance.
- * @clk: The clock resource for this controller.
- * @ide_addr: The area mapped for the hardware registers.
- * @sfr_addr: The area mapped for the special function registers.
- * @irq: The IRQ number we are using.
- * @cpu_type: The exact type of this controller.
- * @fifo_status_reg: The ATA_FIFO_STATUS register offset.
- */
-struct s3c_ide_info {
-	struct clk *clk;
-	void __iomem *ide_addr;
-	void __iomem *sfr_addr;
-	int irq;
-	enum s3c_cpu_type cpu_type;
-	unsigned int fifo_status_reg;
-};
-
-static void pata_s3c_set_endian(void __iomem *s3c_ide_regbase, u8 mode)
-{
-	u32 reg = readl(s3c_ide_regbase + S3C_ATA_CFG);
-	reg = mode ? (reg & ~S3C_ATA_CFG_SWAP) : (reg | S3C_ATA_CFG_SWAP);
-	writel(reg, s3c_ide_regbase + S3C_ATA_CFG);
-}
-
-static void pata_s3c_cfg_mode(void __iomem *s3c_ide_sfrbase)
-{
-	/* Select true-ide as the internal operating mode */
-	writel(readl(s3c_ide_sfrbase + S3C_CFATA_MUX) | S3C_CFATA_MUX_TRUEIDE,
-		s3c_ide_sfrbase + S3C_CFATA_MUX);
-}
-
-static unsigned long
-pata_s3c_setup_timing(struct s3c_ide_info *info, const struct ata_timing *ata)
-{
-	int t1 = ata->setup;
-	int t2 = ata->act8b;
-	int t2i = ata->rec8b;
-	ulong piotime;
-
-	piotime = ((t2i & 0xff) << 12) | ((t2 & 0xff) << 4) | (t1 & 0xf);
-
-	return piotime;
-}
-
-static void pata_s3c_set_piomode(struct ata_port *ap, struct ata_device *adev)
-{
-	struct s3c_ide_info *info = ap->host->private_data;
-	struct ata_timing timing;
-	int cycle_time;
-	ulong ata_cfg = readl(info->ide_addr + S3C_ATA_CFG);
-	ulong piotime;
-
-	/* Enables IORDY if mode requires it */
-	if (ata_pio_need_iordy(adev))
-		ata_cfg |= S3C_ATA_CFG_IORDYEN;
-	else
-		ata_cfg &= ~S3C_ATA_CFG_IORDYEN;
-
-	cycle_time = (int)(1000000000UL / clk_get_rate(info->clk));
-
-	ata_timing_compute(adev, adev->pio_mode, &timing,
-					cycle_time * 1000, 0);
-
-	piotime = pata_s3c_setup_timing(info, &timing);
-
-	writel(ata_cfg, info->ide_addr + S3C_ATA_CFG);
-	writel(piotime, info->ide_addr + S3C_ATA_PIO_TIME);
-}
-
-/*
- * Waits until the IDE controller is able to perform next read/write
- * operation to the disk. Needed for 64XX series boards only.
- */
-static int wait_for_host_ready(struct s3c_ide_info *info)
-{
-	ulong timeout;
-	void __iomem *fifo_reg = info->ide_addr + info->fifo_status_reg;
-
-	/* wait for maximum of 20 msec */
-	timeout = jiffies + msecs_to_jiffies(20);
-	while (time_before(jiffies, timeout)) {
-		if ((readl(fifo_reg) >> 28) == 0)
-			return 0;
-	}
-	return -EBUSY;
-}
-
-/*
- * Writes to one of the task file registers.
- */
-static void ata_outb(struct ata_host *host, u8 addr, void __iomem *reg)
-{
-	struct s3c_ide_info *info = host->private_data;
-
-	wait_for_host_ready(info);
-	writeb(addr, reg);
-}
-
-/*
- * Reads from one of the task file registers.
- */
-static u8 ata_inb(struct ata_host *host, void __iomem *reg)
-{
-	struct s3c_ide_info *info = host->private_data;
-	u8 temp;
-
-	wait_for_host_ready(info);
-	(void) readb(reg);
-	wait_for_host_ready(info);
-	temp = readb(info->ide_addr + S3C_ATA_PIO_RDATA);
-	return temp;
-}
-
-/*
- * pata_s3c_tf_load - send taskfile registers to host controller
- */
-static void pata_s3c_tf_load(struct ata_port *ap,
-				const struct ata_taskfile *tf)
-{
-	struct ata_ioports *ioaddr = &ap->ioaddr;
-	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
-
-	if (tf->ctl != ap->last_ctl) {
-		ata_outb(ap->host, tf->ctl, ioaddr->ctl_addr);
-		ap->last_ctl = tf->ctl;
-		ata_wait_idle(ap);
-	}
-
-	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
-		ata_outb(ap->host, tf->hob_feature, ioaddr->feature_addr);
-		ata_outb(ap->host, tf->hob_nsect, ioaddr->nsect_addr);
-		ata_outb(ap->host, tf->hob_lbal, ioaddr->lbal_addr);
-		ata_outb(ap->host, tf->hob_lbam, ioaddr->lbam_addr);
-		ata_outb(ap->host, tf->hob_lbah, ioaddr->lbah_addr);
-	}
-
-	if (is_addr) {
-		ata_outb(ap->host, tf->feature, ioaddr->feature_addr);
-		ata_outb(ap->host, tf->nsect, ioaddr->nsect_addr);
-		ata_outb(ap->host, tf->lbal, ioaddr->lbal_addr);
-		ata_outb(ap->host, tf->lbam, ioaddr->lbam_addr);
-		ata_outb(ap->host, tf->lbah, ioaddr->lbah_addr);
-	}
-
-	if (tf->flags & ATA_TFLAG_DEVICE)
-		ata_outb(ap->host, tf->device, ioaddr->device_addr);
-
-	ata_wait_idle(ap);
-}
-
-/*
- * pata_s3c_tf_read - input device's ATA taskfile shadow registers
- */
-static void pata_s3c_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
-{
-	struct ata_ioports *ioaddr = &ap->ioaddr;
-
-	tf->feature = ata_inb(ap->host, ioaddr->error_addr);
-	tf->nsect = ata_inb(ap->host, ioaddr->nsect_addr);
-	tf->lbal = ata_inb(ap->host, ioaddr->lbal_addr);
-	tf->lbam = ata_inb(ap->host, ioaddr->lbam_addr);
-	tf->lbah = ata_inb(ap->host, ioaddr->lbah_addr);
-	tf->device = ata_inb(ap->host, ioaddr->device_addr);
-
-	if (tf->flags & ATA_TFLAG_LBA48) {
-		ata_outb(ap->host, tf->ctl | ATA_HOB, ioaddr->ctl_addr);
-		tf->hob_feature = ata_inb(ap->host, ioaddr->error_addr);
-		tf->hob_nsect = ata_inb(ap->host, ioaddr->nsect_addr);
-		tf->hob_lbal = ata_inb(ap->host, ioaddr->lbal_addr);
-		tf->hob_lbam = ata_inb(ap->host, ioaddr->lbam_addr);
-		tf->hob_lbah = ata_inb(ap->host, ioaddr->lbah_addr);
-		ata_outb(ap->host, tf->ctl, ioaddr->ctl_addr);
-		ap->last_ctl = tf->ctl;
-	}
-}
-
-/*
- * pata_s3c_exec_command - issue ATA command to host controller
- */
-static void pata_s3c_exec_command(struct ata_port *ap,
-				const struct ata_taskfile *tf)
-{
-	ata_outb(ap->host, tf->command, ap->ioaddr.command_addr);
-	ata_sff_pause(ap);
-}
-
-/*
- * pata_s3c_check_status - Read device status register
- */
-static u8 pata_s3c_check_status(struct ata_port *ap)
-{
-	return ata_inb(ap->host, ap->ioaddr.status_addr);
-}
-
-/*
- * pata_s3c_check_altstatus - Read alternate device status register
- */
-static u8 pata_s3c_check_altstatus(struct ata_port *ap)
-{
-	return ata_inb(ap->host, ap->ioaddr.altstatus_addr);
-}
-
-/*
- * pata_s3c_data_xfer - Transfer data by PIO
- */
-static unsigned int pata_s3c_data_xfer(struct ata_queued_cmd *qc,
-				unsigned char *buf, unsigned int buflen, int rw)
-{
-	struct ata_port *ap = qc->dev->link->ap;
-	struct s3c_ide_info *info = ap->host->private_data;
-	void __iomem *data_addr = ap->ioaddr.data_addr;
-	unsigned int words = buflen >> 1, i;
-	u16 *data_ptr = (u16 *)buf;
-
-	/* Requires wait same as in ata_inb/ata_outb */
-	if (rw == READ)
-		for (i = 0; i < words; i++, data_ptr++) {
-			wait_for_host_ready(info);
-			(void) readw(data_addr);
-			wait_for_host_ready(info);
-			*data_ptr = readw(info->ide_addr
-					+ S3C_ATA_PIO_RDATA);
-		}
-	else
-		for (i = 0; i < words; i++, data_ptr++) {
-			wait_for_host_ready(info);
-			writew(*data_ptr, data_addr);
-		}
-
-	if (buflen & 0x01)
-		dev_err(ap->dev, "unexpected trailing data\n");
-
-	return words << 1;
-}
-
-/*
- * pata_s3c_dev_select - Select device on ATA bus
- */
-static void pata_s3c_dev_select(struct ata_port *ap, unsigned int device)
-{
-	u8 tmp = ATA_DEVICE_OBS;
-
-	if (device != 0)
-		tmp |= ATA_DEV1;
-
-	ata_outb(ap->host, tmp, ap->ioaddr.device_addr);
-	ata_sff_pause(ap);
-}
-
-/*
- * pata_s3c_devchk - PATA device presence detection
- */
-static unsigned int pata_s3c_devchk(struct ata_port *ap,
-				unsigned int device)
-{
-	struct ata_ioports *ioaddr = &ap->ioaddr;
-	u8 nsect, lbal;
-
-	pata_s3c_dev_select(ap, device);
-
-	ata_outb(ap->host, 0x55, ioaddr->nsect_addr);
-	ata_outb(ap->host, 0xaa, ioaddr->lbal_addr);
-
-	ata_outb(ap->host, 0xaa, ioaddr->nsect_addr);
-	ata_outb(ap->host, 0x55, ioaddr->lbal_addr);
-
-	ata_outb(ap->host, 0x55, ioaddr->nsect_addr);
-	ata_outb(ap->host, 0xaa, ioaddr->lbal_addr);
-
-	nsect = ata_inb(ap->host, ioaddr->nsect_addr);
-	lbal = ata_inb(ap->host, ioaddr->lbal_addr);
-
-	if ((nsect == 0x55) && (lbal == 0xaa))
-		return 1;	/* we found a device */
-
-	return 0;		/* nothing found */
-}
-
-/*
- * pata_s3c_wait_after_reset - wait for devices to become ready after reset
- */
-static int pata_s3c_wait_after_reset(struct ata_link *link,
-		unsigned long deadline)
-{
-	int rc;
-
-	ata_msleep(link->ap, ATA_WAIT_AFTER_RESET);
-
-	/* always check readiness of the master device */
-	rc = ata_sff_wait_ready(link, deadline);
-	/* -ENODEV means the odd clown forgot the D7 pulldown resistor
-	 * and TF status is 0xff, bail out on it too.
-	 */
-	if (rc)
-		return rc;
-
-	return 0;
-}
-
-/*
- * pata_s3c_bus_softreset - PATA device software reset
- */
-static int pata_s3c_bus_softreset(struct ata_port *ap,
-		unsigned long deadline)
-{
-	struct ata_ioports *ioaddr = &ap->ioaddr;
-
-	/* software reset.  causes dev0 to be selected */
-	ata_outb(ap->host, ap->ctl, ioaddr->ctl_addr);
-	udelay(20);
-	ata_outb(ap->host, ap->ctl | ATA_SRST, ioaddr->ctl_addr);
-	udelay(20);
-	ata_outb(ap->host, ap->ctl, ioaddr->ctl_addr);
-	ap->last_ctl = ap->ctl;
-
-	return pata_s3c_wait_after_reset(&ap->link, deadline);
-}
-
-/*
- * pata_s3c_softreset - reset host port via ATA SRST
- */
-static int pata_s3c_softreset(struct ata_link *link, unsigned int *classes,
-			 unsigned long deadline)
-{
-	struct ata_port *ap = link->ap;
-	unsigned int devmask = 0;
-	int rc;
-	u8 err;
-
-	/* determine if device 0 is present */
-	if (pata_s3c_devchk(ap, 0))
-		devmask |= (1 << 0);
-
-	/* select device 0 again */
-	pata_s3c_dev_select(ap, 0);
-
-	/* issue bus reset */
-	rc = pata_s3c_bus_softreset(ap, deadline);
-	/* if link is occupied, -ENODEV too is an error */
-	if (rc && rc != -ENODEV) {
-		ata_link_err(link, "SRST failed (errno=%d)\n", rc);
-		return rc;
-	}
-
-	/* determine by signature whether we have ATA or ATAPI devices */
-	classes[0] = ata_sff_dev_classify(&ap->link.device[0],
-					  devmask & (1 << 0), &err);
-
-	return 0;
-}
-
-/*
- * pata_s3c_set_devctl - Write device control register
- */
-static void pata_s3c_set_devctl(struct ata_port *ap, u8 ctl)
-{
-	ata_outb(ap->host, ctl, ap->ioaddr.ctl_addr);
-}
-
-static struct scsi_host_template pata_s3c_sht = {
-	ATA_PIO_SHT(DRV_NAME),
-};
-
-static struct ata_port_operations pata_s3c_port_ops = {
-	.inherits		= &ata_sff_port_ops,
-	.sff_check_status	= pata_s3c_check_status,
-	.sff_check_altstatus    = pata_s3c_check_altstatus,
-	.sff_tf_load		= pata_s3c_tf_load,
-	.sff_tf_read		= pata_s3c_tf_read,
-	.sff_data_xfer		= pata_s3c_data_xfer,
-	.sff_exec_command	= pata_s3c_exec_command,
-	.sff_dev_select         = pata_s3c_dev_select,
-	.sff_set_devctl         = pata_s3c_set_devctl,
-	.softreset		= pata_s3c_softreset,
-	.set_piomode		= pata_s3c_set_piomode,
-};
-
-static struct ata_port_operations pata_s5p_port_ops = {
-	.inherits		= &ata_sff_port_ops,
-	.set_piomode		= pata_s3c_set_piomode,
-};
-
-static void pata_s3c_enable(void __iomem *s3c_ide_regbase, bool state)
-{
-	u32 temp = readl(s3c_ide_regbase + S3C_ATA_CTRL);
-	temp = state ? (temp | 1) : (temp & ~1);
-	writel(temp, s3c_ide_regbase + S3C_ATA_CTRL);
-}
-
-static irqreturn_t pata_s3c_irq(int irq, void *dev_instance)
-{
-	struct ata_host *host = dev_instance;
-	struct s3c_ide_info *info = host->private_data;
-	u32 reg;
-
-	reg = readl(info->ide_addr + S3C_ATA_IRQ);
-	writel(reg, info->ide_addr + S3C_ATA_IRQ);
-
-	return ata_sff_interrupt(irq, dev_instance);
-}
-
-static void pata_s3c_hwinit(struct s3c_ide_info *info,
-				struct s3c_ide_platdata *pdata)
-{
-	switch (info->cpu_type) {
-	case TYPE_S3C64XX:
-		/* Configure as big endian */
-		pata_s3c_cfg_mode(info->sfr_addr);
-		pata_s3c_set_endian(info->ide_addr, 1);
-		pata_s3c_enable(info->ide_addr, true);
-		msleep(100);
-
-		/* Remove IRQ Status */
-		writel(0x1f, info->ide_addr + S3C_ATA_IRQ);
-		writel(0x1b, info->ide_addr + S3C_ATA_IRQ_MSK);
-		break;
-
-	case TYPE_S5PV210:
-		/* Configure as little endian */
-		pata_s3c_set_endian(info->ide_addr, 0);
-		pata_s3c_enable(info->ide_addr, true);
-		msleep(100);
-
-		/* Remove IRQ Status */
-		writel(0x3f, info->ide_addr + S3C_ATA_IRQ);
-		writel(0x3f, info->ide_addr + S3C_ATA_IRQ_MSK);
-		break;
-
-	default:
-		BUG();
-	}
-}
-
-static int __init pata_s3c_probe(struct platform_device *pdev)
-{
-	struct s3c_ide_platdata *pdata = dev_get_platdata(&pdev->dev);
-	struct device *dev = &pdev->dev;
-	struct s3c_ide_info *info;
-	struct resource *res;
-	struct ata_port *ap;
-	struct ata_host *host;
-	enum s3c_cpu_type cpu_type;
-	int ret;
-
-	cpu_type = platform_get_device_id(pdev)->driver_data;
-
-	info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
-	if (!info)
-		return -ENOMEM;
-
-	info->irq = platform_get_irq(pdev, 0);
-
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-
-	info->ide_addr = devm_ioremap_resource(dev, res);
-	if (IS_ERR(info->ide_addr))
-		return PTR_ERR(info->ide_addr);
-
-	info->clk = devm_clk_get(&pdev->dev, "cfcon");
-	if (IS_ERR(info->clk)) {
-		dev_err(dev, "failed to get access to cf controller clock\n");
-		ret = PTR_ERR(info->clk);
-		info->clk = NULL;
-		return ret;
-	}
-
-	clk_enable(info->clk);
-
-	/* init ata host */
-	host = ata_host_alloc(dev, 1);
-	if (!host) {
-		dev_err(dev, "failed to allocate ide host\n");
-		ret = -ENOMEM;
-		goto stop_clk;
-	}
-
-	ap = host->ports[0];
-	ap->pio_mask = ATA_PIO4;
-
-	if (cpu_type == TYPE_S3C64XX) {
-		ap->ops = &pata_s3c_port_ops;
-		info->sfr_addr = info->ide_addr + 0x1800;
-		info->ide_addr += 0x1900;
-		info->fifo_status_reg = 0x94;
-	} else {
-		ap->ops = &pata_s5p_port_ops;
-		info->fifo_status_reg = 0x84;
-	}
-
-	info->cpu_type = cpu_type;
-
-	if (info->irq <= 0) {
-		ap->flags |= ATA_FLAG_PIO_POLLING;
-		info->irq = 0;
-		ata_port_desc(ap, "no IRQ, using PIO polling\n");
-	}
-
-	ap->ioaddr.cmd_addr =  info->ide_addr + S3C_ATA_CMD;
-	ap->ioaddr.data_addr = info->ide_addr + S3C_ATA_PIO_DTR;
-	ap->ioaddr.error_addr = info->ide_addr + S3C_ATA_PIO_FED;
-	ap->ioaddr.feature_addr = info->ide_addr + S3C_ATA_PIO_FED;
-	ap->ioaddr.nsect_addr = info->ide_addr + S3C_ATA_PIO_SCR;
-	ap->ioaddr.lbal_addr = info->ide_addr + S3C_ATA_PIO_LLR;
-	ap->ioaddr.lbam_addr = info->ide_addr + S3C_ATA_PIO_LMR;
-	ap->ioaddr.lbah_addr = info->ide_addr + S3C_ATA_PIO_LHR;
-	ap->ioaddr.device_addr = info->ide_addr + S3C_ATA_PIO_DVR;
-	ap->ioaddr.status_addr = info->ide_addr + S3C_ATA_PIO_CSD;
-	ap->ioaddr.command_addr = info->ide_addr + S3C_ATA_PIO_CSD;
-	ap->ioaddr.altstatus_addr = info->ide_addr + S3C_ATA_PIO_DAD;
-	ap->ioaddr.ctl_addr = info->ide_addr + S3C_ATA_PIO_DAD;
-
-	ata_port_desc(ap, "mmio cmd 0x%llx ",
-			(unsigned long long)res->start);
-
-	host->private_data = info;
-
-	if (pdata && pdata->setup_gpio)
-		pdata->setup_gpio();
-
-	/* Set endianness and enable the interface */
-	pata_s3c_hwinit(info, pdata);
-
-	ret = ata_host_activate(host, info->irq,
-				info->irq ? pata_s3c_irq : NULL,
-				0, &pata_s3c_sht);
-	if (ret)
-		goto stop_clk;
-
-	return 0;
-
-stop_clk:
-	clk_disable(info->clk);
-	return ret;
-}
-
-static int __exit pata_s3c_remove(struct platform_device *pdev)
-{
-	struct ata_host *host = platform_get_drvdata(pdev);
-	struct s3c_ide_info *info = host->private_data;
-
-	ata_host_detach(host);
-
-	clk_disable(info->clk);
-
-	return 0;
-}
-
-#ifdef CONFIG_PM_SLEEP
-static int pata_s3c_suspend(struct device *dev)
-{
-	struct ata_host *host = dev_get_drvdata(dev);
-
-	return ata_host_suspend(host, PMSG_SUSPEND);
-}
-
-static int pata_s3c_resume(struct device *dev)
-{
-	struct ata_host *host = dev_get_drvdata(dev);
-	struct s3c_ide_platdata *pdata = dev_get_platdata(dev);
-	struct s3c_ide_info *info = host->private_data;
-
-	pata_s3c_hwinit(info, pdata);
-	ata_host_resume(host);
-
-	return 0;
-}
-
-static const struct dev_pm_ops pata_s3c_pm_ops = {
-	.suspend	= pata_s3c_suspend,
-	.resume		= pata_s3c_resume,
-};
-#endif
-
-/* driver device registration */
-static const struct platform_device_id pata_s3c_driver_ids[] = {
-	{
-		.name		= "s3c64xx-pata",
-		.driver_data	= TYPE_S3C64XX,
-	}, {
-		.name		= "s5pv210-pata",
-		.driver_data	= TYPE_S5PV210,
-	},
-	{ }
-};
-
-MODULE_DEVICE_TABLE(platform, pata_s3c_driver_ids);
-
-static struct platform_driver pata_s3c_driver = {
-	.remove		= __exit_p(pata_s3c_remove),
-	.id_table	= pata_s3c_driver_ids,
-	.driver		= {
-		.name	= DRV_NAME,
-#ifdef CONFIG_PM_SLEEP
-		.pm	= &pata_s3c_pm_ops,
-#endif
-	},
-};
-
-module_platform_driver_probe(pata_s3c_driver, pata_s3c_probe);
-
-MODULE_AUTHOR("Abhilash Kesavan, <a.kesavan@samsung.com>");
-MODULE_DESCRIPTION("low-level driver for Samsung PATA controller");
-MODULE_LICENSE("GPL");
-MODULE_VERSION(DRV_VERSION);
diff --git a/drivers/ata/pata_sc1200.c b/drivers/ata/pata_sc1200.c
index 3b8c111140bd..a388dfb97ad8 100644
--- a/drivers/ata/pata_sc1200.c
+++ b/drivers/ata/pata_sc1200.c
@@ -192,9 +192,10 @@ static int sc1200_qc_defer(struct ata_queued_cmd *qc)
 	return 0;
 }
 
-static struct scsi_host_template sc1200_sht = {
-	ATA_BMDMA_SHT(DRV_NAME),
+static const struct scsi_host_template sc1200_sht = {
+	ATA_BASE_SHT(DRV_NAME),
 	.sg_tablesize	= LIBATA_DUMB_MAX_PRD,
+	.dma_boundary	= ATA_DMA_BOUNDARY,
 };
 
 static struct ata_port_operations sc1200_port_ops = {
diff --git a/drivers/ata/pata_sch.c b/drivers/ata/pata_sch.c
index 4f9c2aefd807..8356f1f2a025 100644
--- a/drivers/ata/pata_sch.c
+++ b/drivers/ata/pata_sch.c
@@ -57,7 +57,7 @@ static struct pci_driver sch_pci_driver = {
 #endif
 };
 
-static struct scsi_host_template sch_sht = {
+static const struct scsi_host_template sch_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
diff --git a/drivers/ata/pata_serverworks.c b/drivers/ata/pata_serverworks.c
index 916bf024d737..4edddf6bcc15 100644
--- a/drivers/ata/pata_serverworks.c
+++ b/drivers/ata/pata_serverworks.c
@@ -46,10 +46,11 @@
 #define SVWKS_CSB5_REVISION_NEW	0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
 #define SVWKS_CSB6_REVISION	0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
 
-/* Seagate Barracuda ATA IV Family drives in UDMA mode 5
- * can overrun their FIFOs when used with the CSB5 */
-
-static const char *csb_bad_ata100[] = {
+/*
+ * Seagate Barracuda ATA IV Family drives in UDMA mode 5
+ * can overrun their FIFOs when used with the CSB5.
+ */
+static const char * const csb_bad_ata100[] = {
 	"ST320011A",
 	"ST340016A",
 	"ST360021A",
@@ -150,7 +151,7 @@ static u8 serverworks_is_csb(struct pci_dev *pdev)
  *	bug we hit.
  */
 
-static unsigned long serverworks_osb4_filter(struct ata_device *adev, unsigned long mask)
+static unsigned int serverworks_osb4_filter(struct ata_device *adev, unsigned int mask)
 {
 	if (adev->class == ATA_DEV_ATA)
 		mask &= ~ATA_MASK_UDMA;
@@ -163,10 +164,11 @@ static unsigned long serverworks_osb4_filter(struct ata_device *adev, unsigned l
  *	@adev: ATA device
  *	@mask: Mask of proposed modes
  *
- *	Check the blacklist and disable UDMA5 if matched
+ *	Check the list of devices with broken UDMA5 and
+ *	disable UDMA5 if matched.
  */
-
-static unsigned long serverworks_csb_filter(struct ata_device *adev, unsigned long mask)
+static unsigned int serverworks_csb_filter(struct ata_device *adev,
+					   unsigned int mask)
 {
 	const char *p;
 	char model_num[ATA_ID_PROD_LEN + 1];
@@ -252,12 +254,13 @@ static void serverworks_set_dmamode(struct ata_port *ap, struct ata_device *adev
 	pci_write_config_byte(pdev, 0x54, ultra_cfg);
 }
 
-static struct scsi_host_template serverworks_osb4_sht = {
-	ATA_BMDMA_SHT(DRV_NAME),
+static const struct scsi_host_template serverworks_osb4_sht = {
+	ATA_BASE_SHT(DRV_NAME),
 	.sg_tablesize	= LIBATA_DUMB_MAX_PRD,
+	.dma_boundary	= ATA_DMA_BOUNDARY,
 };
 
-static struct scsi_host_template serverworks_csb_sht = {
+static const struct scsi_host_template serverworks_csb_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
@@ -285,13 +288,13 @@ static int serverworks_fixup_osb4(struct pci_dev *pdev)
 		pci_read_config_dword(isa_dev, 0x64, &reg);
 		reg &= ~0x00002000; /* disable 600ns interrupt mask */
 		if (!(reg & 0x00004000))
-			printk(KERN_DEBUG DRV_NAME ": UDMA not BIOS enabled.\n");
+			dev_info(&pdev->dev, "UDMA not BIOS enabled.\n");
 		reg |=  0x00004000; /* enable UDMA/33 support */
 		pci_write_config_dword(isa_dev, 0x64, reg);
 		pci_dev_put(isa_dev);
 		return 0;
 	}
-	printk(KERN_WARNING DRV_NAME ": Unable to find bridge.\n");
+	dev_warn(&pdev->dev, "Unable to find bridge.\n");
 	return -ENODEV;
 }
 
@@ -369,7 +372,7 @@ static int serverworks_fixup(struct pci_dev *pdev)
 		break;
 	case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
 		ata_pci_bmdma_clear_simplex(pdev);
-		/* fall through */
+		fallthrough;
 	case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
 	case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
 		rc = serverworks_fixup_csb(pdev);
@@ -412,7 +415,7 @@ static int serverworks_init_one(struct pci_dev *pdev, const struct pci_device_id
 		}
 	};
 	const struct ata_port_info *ppi[] = { &info[id->driver_data], NULL };
-	struct scsi_host_template *sht = &serverworks_csb_sht;
+	const struct scsi_host_template *sht = &serverworks_csb_sht;
 	int rc;
 
 	rc = pcim_enable_device(pdev);
diff --git a/drivers/ata/pata_sil680.c b/drivers/ata/pata_sil680.c
index 7ab9aea3b630..abe64b5f83cf 100644
--- a/drivers/ata/pata_sil680.c
+++ b/drivers/ata/pata_sil680.c
@@ -47,16 +47,15 @@
  *	criticial.
  */
 
-static unsigned long sil680_selreg(struct ata_port *ap, int r)
+static int sil680_selreg(struct ata_port *ap, int r)
 {
-	unsigned long base = 0xA0 + r;
-	base += (ap->port_no << 4);
-	return base;
+	return 0xA0 + (ap->port_no << 4) + r;
 }
 
 /**
  *	sil680_seldev		-	return register base
  *	@ap: ATA interface
+ *	@adev: ATA device
  *	@r: config offset
  *
  *	Turn a config register offset into the right address in PCI space
@@ -64,12 +63,9 @@ static unsigned long sil680_selreg(struct ata_port *ap, int r)
  *	the unit shift.
  */
 
-static unsigned long sil680_seldev(struct ata_port *ap, struct ata_device *adev, int r)
+static int sil680_seldev(struct ata_port *ap, struct ata_device *adev, int r)
 {
-	unsigned long base = 0xA0 + r;
-	base += (ap->port_no << 4);
-	base |= adev->devno ? 2 : 0;
-	return base;
+	return 0xA0 + (ap->port_no << 4) + r + (adev->devno << 1);
 }
 
 
@@ -84,8 +80,9 @@ static unsigned long sil680_seldev(struct ata_port *ap, struct ata_device *adev,
 static int sil680_cable_detect(struct ata_port *ap)
 {
 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
-	unsigned long addr = sil680_selreg(ap, 0);
+	int addr = sil680_selreg(ap, 0);
 	u8 ata66;
+
 	pci_read_config_byte(pdev, addr, &ata66);
 	if (ata66 & 1)
 		return ATA_CBL_PATA80;
@@ -112,9 +109,9 @@ static void sil680_set_piomode(struct ata_port *ap, struct ata_device *adev)
 		0x328A, 0x2283, 0x1281, 0x10C3, 0x10C1
 	};
 
-	unsigned long tfaddr = sil680_selreg(ap, 0x02);
-	unsigned long addr = sil680_seldev(ap, adev, 0x04);
-	unsigned long addr_mask = 0x80 + 4 * ap->port_no;
+	int tfaddr = sil680_selreg(ap, 0x02);
+	int addr = sil680_seldev(ap, adev, 0x04);
+	int addr_mask = 0x80 + 4 * ap->port_no;
 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 	int pio = adev->pio_mode - XFER_PIO_0;
 	int lowest_pio = pio;
@@ -164,9 +161,9 @@ static void sil680_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 	static const u16 dma_table[3] = { 0x2208, 0x10C2, 0x10C1 };
 
 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
-	unsigned long ma = sil680_seldev(ap, adev, 0x08);
-	unsigned long ua = sil680_seldev(ap, adev, 0x0C);
-	unsigned long addr_mask = 0x80 + 4 * ap->port_no;
+	int ma = sil680_seldev(ap, adev, 0x08);
+	int ua = sil680_seldev(ap, adev, 0x0C);
+	int addr_mask = 0x80 + 4 * ap->port_no;
 	int port_shift = adev->devno * 4;
 	u8 scsc, mode;
 	u16 multi, ultra;
@@ -211,7 +208,6 @@ static void sil680_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 static void sil680_sff_exec_command(struct ata_port *ap,
 				    const struct ata_taskfile *tf)
 {
-	DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
 	iowrite8(tf->command, ap->ioaddr.command_addr);
 	ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
 }
@@ -219,7 +215,7 @@ static void sil680_sff_exec_command(struct ata_port *ap,
 static bool sil680_sff_irq_check(struct ata_port *ap)
 {
 	struct pci_dev *pdev	= to_pci_dev(ap->host->dev);
-	unsigned long addr	= sil680_selreg(ap, 1);
+	int addr		= sil680_selreg(ap, 1);
 	u8 val;
 
 	pci_read_config_byte(pdev, addr, &val);
@@ -227,7 +223,7 @@ static bool sil680_sff_irq_check(struct ata_port *ap)
 	return val & 0x08;
 }
 
-static struct scsi_host_template sil680_sht = {
+static const struct scsi_host_template sil680_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
@@ -244,6 +240,7 @@ static struct ata_port_operations sil680_port_ops = {
 /**
  *	sil680_init_chip		-	chip setup
  *	@pdev: PCI device
+ *	@try_mmio: Indicates to caller whether MMIO should be attempted
  *
  *	Perform all the chip setup which must be done both when the device
  *	is powered up on boot and when we resume in case we resumed from RAM.
@@ -307,17 +304,17 @@ static u8 sil680_init_chip(struct pci_dev *pdev, int *try_mmio)
 
 	switch (tmpbyte & 0x30) {
 	case 0x00:
-		printk(KERN_INFO "sil680: 100MHz clock.\n");
+		dev_info(&pdev->dev, "sil680: 100MHz clock.\n");
 		break;
 	case 0x10:
-		printk(KERN_INFO "sil680: 133MHz clock.\n");
+		dev_info(&pdev->dev, "sil680: 133MHz clock.\n");
 		break;
 	case 0x20:
-		printk(KERN_INFO "sil680: Using PCI clock.\n");
+		dev_info(&pdev->dev, "sil680: Using PCI clock.\n");
 		break;
 	/* This last case is _NOT_ ok */
 	case 0x30:
-		printk(KERN_ERR "sil680: Clock disabled ?\n");
+		dev_err(&pdev->dev, "sil680: Clock disabled ?\n");
 	}
 	return tmpbyte & 0x30;
 }
diff --git a/drivers/ata/pata_sis.c b/drivers/ata/pata_sis.c
index d7cd39a9888a..2b751e393771 100644
--- a/drivers/ata/pata_sis.c
+++ b/drivers/ata/pata_sis.c
@@ -114,7 +114,6 @@ static int sis_port_base(struct ata_device *adev)
 /**
  *	sis_133_cable_detect - check for 40/80 pin
  *	@ap: Port
- *	@deadline: deadline jiffies for the operation
  *
  *	Perform cable detection for the later UDMA133 capable
  *	SiS chipset.
@@ -521,11 +520,12 @@ static void sis_133_set_dmamode (struct ata_port *ap, struct ata_device *adev)
 /**
  *	sis_133_mode_filter - mode selection filter
  *	@adev: ATA device
+ *	@mask: received mask to manipulate and pass back
  *
  *	Block UDMA6 on devices that do not support it.
  */
 
-static unsigned long sis_133_mode_filter(struct ata_device *adev, unsigned long mask)
+static unsigned int sis_133_mode_filter(struct ata_device *adev, unsigned int mask)
 {
 	struct ata_port *ap = adev->link->ap;
 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
@@ -539,7 +539,7 @@ static unsigned long sis_133_mode_filter(struct ata_device *adev, unsigned long
 	return mask;
 }
 
-static struct scsi_host_template sis_sht = {
+static const struct scsi_host_template sis_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
@@ -552,7 +552,7 @@ static struct ata_port_operations sis_133_for_sata_ops = {
 
 static struct ata_port_operations sis_base_ops = {
 	.inherits		= &ata_bmdma_port_ops,
-	.prereset		= sis_pre_reset,
+	.reset.prereset		= sis_pre_reset,
 };
 
 static struct ata_port_operations sis_133_ops = {
diff --git a/drivers/ata/pata_sl82c105.c b/drivers/ata/pata_sl82c105.c
index ac7ddd87f188..2d24c6b3e9d9 100644
--- a/drivers/ata/pata_sl82c105.c
+++ b/drivers/ata/pata_sl82c105.c
@@ -173,15 +173,14 @@ static void sl82c105_bmdma_start(struct ata_queued_cmd *qc)
 }
 
 /**
- *	sl82c105_bmdma_end		-	DMA engine stop
+ *	sl82c105_bmdma_stop		-	DMA engine stop
  *	@qc: ATA command
  *
  *	Reset the DMA engine each use as recommended by the errata
  *	document.
  *
  *	This function is also called to turn off DMA when a timeout occurs
- *	during DMA operation. In both cases we need to reset the engine,
- *	so no actual eng_timeout handler is required.
+ *	during DMA operation. In both cases we need to reset the engine.
  *
  *	We assume bmdma_stop is always called if bmdma_start as called. If
  *	not then we may need to wrap qc_issue.
@@ -238,7 +237,7 @@ static bool sl82c105_sff_irq_check(struct ata_port *ap)
 	return val & mask;
 }
 
-static struct scsi_host_template sl82c105_sht = {
+static const struct scsi_host_template sl82c105_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
@@ -249,7 +248,7 @@ static struct ata_port_operations sl82c105_port_ops = {
 	.bmdma_stop	= sl82c105_bmdma_stop,
 	.cable_detect	= ata_cable_40wire,
 	.set_piomode	= sl82c105_set_piomode,
-	.prereset	= sl82c105_pre_reset,
+	.reset.prereset	= sl82c105_pre_reset,
 	.sff_irq_check	= sl82c105_sff_irq_check,
 };
 
diff --git a/drivers/ata/pata_triflex.c b/drivers/ata/pata_triflex.c
index 2a4d38b98026..596e86a031b3 100644
--- a/drivers/ata/pata_triflex.c
+++ b/drivers/ata/pata_triflex.c
@@ -129,7 +129,7 @@ static void triflex_set_piomode(struct ata_port *ap, struct ata_device *adev)
 }
 
 /**
- *	triflex_dma_start	-	DMA start callback
+ *	triflex_bmdma_start	-	DMA start callback
  *	@qc: Command in progress
  *
  *	Usually drivers set the DMA timing at the point the set_dmamode call
@@ -146,9 +146,8 @@ static void triflex_bmdma_start(struct ata_queued_cmd *qc)
 }
 
 /**
- *	triflex_dma_stop	-	DMA stop callback
- *	@ap: ATA interface
- *	@adev: ATA device
+ *	triflex_bmdma_stop	-	DMA stop callback
+ *	@qc: ATA command
  *
  *	We loaded new timings in dma_start, as a result we need to restore
  *	the PIO timings in dma_stop so that the next command issue gets the
@@ -161,7 +160,7 @@ static void triflex_bmdma_stop(struct ata_queued_cmd *qc)
 	triflex_load_timing(qc->ap, qc->dev, qc->dev->pio_mode);
 }
 
-static struct scsi_host_template triflex_sht = {
+static const struct scsi_host_template triflex_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
@@ -171,7 +170,7 @@ static struct ata_port_operations triflex_port_ops = {
 	.bmdma_stop	= triflex_bmdma_stop,
 	.cable_detect	= ata_cable_40wire,
 	.set_piomode	= triflex_set_piomode,
-	.prereset	= triflex_prereset,
+	.reset.prereset	= triflex_prereset,
 };
 
 static int triflex_init_one(struct pci_dev *dev, const struct pci_device_id *id)
@@ -199,11 +198,8 @@ static const struct pci_device_id triflex[] = {
 static int triflex_ata_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
 {
 	struct ata_host *host = pci_get_drvdata(pdev);
-	int rc = 0;
 
-	rc = ata_host_suspend(host, mesg);
-	if (rc)
-		return rc;
+	ata_host_suspend(host, mesg);
 
 	/*
 	 * We must not disable or powerdown the device.
diff --git a/drivers/ata/pata_via.c b/drivers/ata/pata_via.c
index 38044e679795..a8c9cf685b4b 100644
--- a/drivers/ata/pata_via.c
+++ b/drivers/ata/pata_via.c
@@ -201,11 +201,9 @@ static int via_cable_detect(struct ata_port *ap) {
 	   two drives */
 	if (ata66 & (0x10100000 >> (16 * ap->port_no)))
 		return ATA_CBL_PATA80;
+
 	/* Check with ACPI so we can spot BIOS reported SATA bridges */
-	if (ata_acpi_init_gtm(ap) &&
-	    ata_acpi_cbl_80wire(ap, ata_acpi_init_gtm(ap)))
-		return ATA_CBL_PATA80;
-	return ATA_CBL_PATA40;
+	return ata_acpi_cbl_pata_type(ap);
 }
 
 static int via_pre_reset(struct ata_link *link, unsigned long deadline)
@@ -248,9 +246,9 @@ static void via_do_set_mode(struct ata_port *ap, struct ata_device *adev,
 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 	struct ata_device *peer = ata_dev_pair(adev);
 	struct ata_timing t, p;
-	static int via_clock = 33333;	/* Bus clock in kHZ */
-	unsigned long T =  1000000000 / via_clock;
-	unsigned long UT = T;
+	const int via_clock = 33333;	/* Bus clock in kHz */
+	const int T = 1000000000 / via_clock;
+	int UT = T;
 	int ut;
 	int offset = 3 - (2*ap->port_no) - adev->devno;
 
@@ -352,7 +350,7 @@ static void via_set_dmamode(struct ata_port *ap, struct ata_device *adev)
  *	one breed of Transcend SSD. Return the updated mask.
  */
 
-static unsigned long via_mode_filter(struct ata_device *dev, unsigned long mask)
+static unsigned int via_mode_filter(struct ata_device *dev, unsigned int mask)
 {
 	struct ata_host *host = dev->link->ap->host;
 	const struct via_isa_bridge *config = host->private_data;
@@ -368,7 +366,8 @@ static unsigned long via_mode_filter(struct ata_device *dev, unsigned long mask)
 	}
 
 	if (dev->class == ATA_DEV_ATAPI &&
-	    dmi_check_system(no_atapi_dma_dmi_table)) {
+	    (dmi_check_system(no_atapi_dma_dmi_table) ||
+	     config->id == PCI_DEVICE_ID_VIA_6415)) {
 		ata_dev_warn(dev, "controller locks up on ATAPI DMA, forcing PIO\n");
 		mask &= ATA_MASK_PIO;
 	}
@@ -414,12 +413,6 @@ static void via_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
 		iowrite8(tf->hob_lbal, ioaddr->lbal_addr);
 		iowrite8(tf->hob_lbam, ioaddr->lbam_addr);
 		iowrite8(tf->hob_lbah, ioaddr->lbah_addr);
-		VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
-			tf->hob_feature,
-			tf->hob_nsect,
-			tf->hob_lbal,
-			tf->hob_lbam,
-			tf->hob_lbah);
 	}
 
 	if (is_addr) {
@@ -428,12 +421,6 @@ static void via_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
 		iowrite8(tf->lbal, ioaddr->lbal_addr);
 		iowrite8(tf->lbam, ioaddr->lbam_addr);
 		iowrite8(tf->lbah, ioaddr->lbah_addr);
-		VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
-			tf->feature,
-			tf->nsect,
-			tf->lbal,
-			tf->lbam,
-			tf->lbah);
 	}
 
 	ata_wait_idle(ap);
@@ -455,7 +442,7 @@ static int via_port_start(struct ata_port *ap)
 	return 0;
 }
 
-static struct scsi_host_template via_sht = {
+static const struct scsi_host_template via_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
@@ -464,7 +451,7 @@ static struct ata_port_operations via_port_ops = {
 	.cable_detect	= via_cable_detect,
 	.set_piomode	= via_set_piomode,
 	.set_dmamode	= via_set_dmamode,
-	.prereset	= via_pre_reset,
+	.reset.prereset	= via_pre_reset,
 	.sff_tf_load	= via_tf_load,
 	.port_start	= via_port_start,
 	.mode_filter	= via_mode_filter,
@@ -663,7 +650,7 @@ static int via_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
 #ifdef CONFIG_PM_SLEEP
 /**
  *	via_reinit_one		-	reinit after resume
- *	@pdev; PCI device
+ *	@pdev: PCI device
  *
  *	Called when the VIA PATA device is resumed. We must then
  *	reconfigure the fifo and other setup we may have altered. In
diff --git a/drivers/ata/pdc_adma.c b/drivers/ata/pdc_adma.c
index 5db55e1e2a61..17a5a59861c3 100644
--- a/drivers/ata/pdc_adma.c
+++ b/drivers/ata/pdc_adma.c
@@ -123,7 +123,7 @@ static void adma_freeze(struct ata_port *ap);
 static void adma_thaw(struct ata_port *ap);
 static int adma_prereset(struct ata_link *link, unsigned long deadline);
 
-static struct scsi_host_template adma_ata_sht = {
+static const struct scsi_host_template adma_ata_sht = {
 	ATA_BASE_SHT(DRV_NAME),
 	.sg_tablesize		= LIBATA_MAX_PRD,
 	.dma_boundary		= ADMA_DMA_BOUNDARY,
@@ -140,7 +140,7 @@ static struct ata_port_operations adma_ata_ops = {
 
 	.freeze			= adma_freeze,
 	.thaw			= adma_thaw,
-	.prereset		= adma_prereset,
+	.reset.prereset		= adma_prereset,
 
 	.port_start		= adma_port_start,
 	.port_stop		= adma_port_stop,
@@ -284,9 +284,6 @@ static int adma_fill_sg(struct ata_queued_cmd *qc)
 		*(__le32 *)(buf + i) =
 			(pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4);
 		i += 4;
-
-		VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", i/4,
-					(unsigned long)addr, len);
 	}
 
 	if (likely(last_buf))
@@ -302,8 +299,6 @@ static enum ata_completion_errors adma_qc_prep(struct ata_queued_cmd *qc)
 	u32 pkt_dma = (u32)pp->pkt_dma;
 	int i = 0;
 
-	VPRINTK("ENTER\n");
-
 	adma_enter_reg_mode(qc->ap);
 	if (qc->tf.protocol != ATA_PROT_DMA)
 		return AC_ERR_OK;
@@ -355,22 +350,6 @@ static enum ata_completion_errors adma_qc_prep(struct ata_queued_cmd *qc)
 
 	i = adma_fill_sg(qc);
 	wmb();	/* flush PRDs and pkt to memory */
-#if 0
-	/* dump out CPB + PRDs for debug */
-	{
-		int j, len = 0;
-		static char obuf[2048];
-		for (j = 0; j < i; ++j) {
-			len += sprintf(obuf+len, "%02x ", buf[j]);
-			if ((j & 7) == 7) {
-				printk("%s\n", obuf);
-				len = 0;
-			}
-		}
-		if (len)
-			printk("%s\n", obuf);
-	}
-#endif
 	return AC_ERR_OK;
 }
 
@@ -379,8 +358,6 @@ static inline void adma_packet_start(struct ata_queued_cmd *qc)
 	struct ata_port *ap = qc->ap;
 	void __iomem *chan = ADMA_PORT_REGS(ap);
 
-	VPRINTK("ENTER, ap %p\n", ap);
-
 	/* fire up the ADMA engine */
 	writew(aPIOMD4 | aGO, chan + ADMA_CONTROL);
 }
@@ -475,8 +452,6 @@ static inline unsigned int adma_intr_mmio(struct ata_host *host)
 			u8 status = ata_sff_check_status(ap);
 			if ((status & ATA_BUSY))
 				continue;
-			DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
-				ap->print_id, qc->tf.protocol, status);
 
 			/* complete taskfile transaction */
 			pp->state = adma_state_idle;
@@ -504,14 +479,10 @@ static irqreturn_t adma_intr(int irq, void *dev_instance)
 	struct ata_host *host = dev_instance;
 	unsigned int handled = 0;
 
-	VPRINTK("ENTER\n");
-
 	spin_lock(&host->lock);
 	handled  = adma_intr_pkt(host) | adma_intr_mmio(host);
 	spin_unlock(&host->lock);
 
-	VPRINTK("EXIT\n");
-
 	return IRQ_RETVAL(handled);
 }
 
@@ -547,8 +518,8 @@ static int adma_port_start(struct ata_port *ap)
 		return -ENOMEM;
 	/* paranoia? */
 	if ((pp->pkt_dma & 7) != 0) {
-		printk(KERN_ERR "bad alignment for pp->pkt_dma: %08x\n",
-						(u32)pp->pkt_dma);
+		ata_port_err(ap, "bad alignment for pp->pkt_dma: %08x\n",
+			     (u32)pp->pkt_dma);
 		return -ENOMEM;
 	}
 	ap->private_data = pp;
diff --git a/drivers/ata/sata_dwc_460ex.c b/drivers/ata/sata_dwc_460ex.c
index 9dcef6ac643b..7a4f59202156 100644
--- a/drivers/ata/sata_dwc_460ex.c
+++ b/drivers/ata/sata_dwc_460ex.c
@@ -14,26 +14,17 @@
  *          COPYRIGHT (C) 2005  SYNOPSYS, INC.  ALL RIGHTS RESERVED
  */
 
-#ifdef CONFIG_SATA_DWC_DEBUG
-#define DEBUG
-#endif
-
-#ifdef CONFIG_SATA_DWC_VDEBUG
-#define VERBOSE_DEBUG
-#define DEBUG_NCQ
-#endif
-
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/device.h>
 #include <linux/dmaengine.h>
-#include <linux/of_address.h>
+#include <linux/of.h>
 #include <linux/of_irq.h>
-#include <linux/of_platform.h>
 #include <linux/platform_device.h>
 #include <linux/phy/phy.h>
 #include <linux/libata.h>
 #include <linux/slab.h>
+#include <trace/events/libata.h>
 
 #include "libata.h"
 
@@ -50,10 +41,6 @@
 #define sata_dwc_writel(a, v)	writel_relaxed(v, a)
 #define sata_dwc_readl(a)	readl_relaxed(a)
 
-#ifndef NO_IRQ
-#define NO_IRQ		0
-#endif
-
 #define AHB_DMA_BRST_DFLT	64	/* 16 data items burst length */
 
 enum {
@@ -145,7 +132,11 @@ struct sata_dwc_device {
 #endif
 };
 
-#define SATA_DWC_QCMD_MAX	32
+/*
+ * Allow one extra special slot for commands and DMA management
+ * to account for libata internal commands.
+ */
+#define SATA_DWC_QCMD_MAX	(ATA_MAX_QUEUE + 1)
 
 struct sata_dwc_device_port {
 	struct sata_dwc_device	*hsdev;
@@ -182,10 +173,8 @@ enum {
  * Prototypes
  */
 static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag);
-static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
-				u32 check_status);
-static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status);
-static void sata_dwc_port_stop(struct ata_port *ap);
+static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc);
+static void sata_dwc_dma_xfer_complete(struct ata_port *ap);
 static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag);
 
 #ifdef CONFIG_SATA_DWC_OLD_DMA
@@ -215,9 +204,10 @@ static int sata_dwc_dma_get_channel_old(struct sata_dwc_device_port *hsdevp)
 {
 	struct sata_dwc_device *hsdev = hsdevp->hsdev;
 	struct dw_dma_slave *dws = &sata_dwc_dma_dws;
+	struct device *dev = hsdev->dev;
 	dma_cap_mask_t mask;
 
-	dws->dma_dev = hsdev->dev;
+	dws->dma_dev = dev;
 
 	dma_cap_zero(mask);
 	dma_cap_set(DMA_SLAVE, mask);
@@ -225,8 +215,7 @@ static int sata_dwc_dma_get_channel_old(struct sata_dwc_device_port *hsdevp)
 	/* Acquire DMA channel */
 	hsdevp->chan = dma_request_channel(mask, sata_dwc_dma_filter, hsdevp);
 	if (!hsdevp->chan) {
-		dev_err(hsdev->dev, "%s: dma channel unavailable\n",
-			 __func__);
+		dev_err(dev, "%s: dma channel unavailable\n", __func__);
 		return -EAGAIN;
 	}
 
@@ -236,26 +225,25 @@ static int sata_dwc_dma_get_channel_old(struct sata_dwc_device_port *hsdevp)
 static int sata_dwc_dma_init_old(struct platform_device *pdev,
 				 struct sata_dwc_device *hsdev)
 {
-	struct device_node *np = pdev->dev.of_node;
-	struct resource *res;
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
 
-	hsdev->dma = devm_kzalloc(&pdev->dev, sizeof(*hsdev->dma), GFP_KERNEL);
+	hsdev->dma = devm_kzalloc(dev, sizeof(*hsdev->dma), GFP_KERNEL);
 	if (!hsdev->dma)
 		return -ENOMEM;
 
-	hsdev->dma->dev = &pdev->dev;
+	hsdev->dma->dev = dev;
 	hsdev->dma->id = pdev->id;
 
 	/* Get SATA DMA interrupt number */
 	hsdev->dma->irq = irq_of_parse_and_map(np, 1);
-	if (hsdev->dma->irq == NO_IRQ) {
-		dev_err(&pdev->dev, "no SATA DMA irq\n");
+	if (!hsdev->dma->irq) {
+		dev_err(dev, "no SATA DMA irq\n");
 		return -ENODEV;
 	}
 
 	/* Get physical SATA DMA register base address */
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-	hsdev->dma->regs = devm_ioremap_resource(&pdev->dev, res);
+	hsdev->dma->regs = devm_platform_ioremap_resource(pdev, 1);
 	if (IS_ERR(hsdev->dma->regs))
 		return PTR_ERR(hsdev->dma->regs);
 
@@ -297,35 +285,6 @@ static const char *get_prot_descript(u8 protocol)
 	}
 }
 
-static const char *get_dma_dir_descript(int dma_dir)
-{
-	switch ((enum dma_data_direction)dma_dir) {
-	case DMA_BIDIRECTIONAL:
-		return "bidirectional";
-	case DMA_TO_DEVICE:
-		return "to device";
-	case DMA_FROM_DEVICE:
-		return "from device";
-	default:
-		return "none";
-	}
-}
-
-static void sata_dwc_tf_dump(struct ata_port *ap, struct ata_taskfile *tf)
-{
-	dev_vdbg(ap->dev,
-		"taskfile cmd: 0x%02x protocol: %s flags: 0x%lx device: %x\n",
-		tf->command, get_prot_descript(tf->protocol), tf->flags,
-		tf->device);
-	dev_vdbg(ap->dev,
-		"feature: 0x%02x nsect: 0x%x lbal: 0x%x lbam: 0x%x lbah: 0x%x\n",
-		tf->feature, tf->nsect, tf->lbal, tf->lbam, tf->lbah);
-	dev_vdbg(ap->dev,
-		"hob_feature: 0x%02x hob_nsect: 0x%x hob_lbal: 0x%x hob_lbam: 0x%x hob_lbah: 0x%x\n",
-		tf->hob_feature, tf->hob_nsect, tf->hob_lbal, tf->hob_lbam,
-		tf->hob_lbah);
-}
-
 static void dma_dwc_xfer_done(void *hsdev_instance)
 {
 	unsigned long flags;
@@ -355,7 +314,7 @@ static void dma_dwc_xfer_done(void *hsdev_instance)
 	}
 
 	if ((hsdevp->dma_interrupt_count % 2) == 0)
-		sata_dwc_dma_xfer_complete(ap, 1);
+		sata_dwc_dma_xfer_complete(ap);
 
 	spin_unlock_irqrestore(&host->lock, flags);
 }
@@ -508,7 +467,7 @@ static irqreturn_t sata_dwc_isr(int irq, void *dev_instance)
 	struct ata_queued_cmd *qc;
 	unsigned long flags;
 	u8 status, tag;
-	int handled, num_processed, port = 0;
+	int handled, port = 0;
 	uint intpr, sactive, sactive2, tag_mask;
 	struct sata_dwc_device_port *hsdevp;
 	hsdev->sactive_issued = 0;
@@ -543,11 +502,17 @@ static irqreturn_t sata_dwc_isr(int irq, void *dev_instance)
 		hsdev->sactive_issued |= qcmd_tag_to_mask(tag);
 
 		qc = ata_qc_from_tag(ap, tag);
+		if (unlikely(!qc)) {
+			dev_err(ap->dev, "failed to get qc");
+			handled = 1;
+			goto DONE;
+		}
 		/*
 		 * Start FP DMA for NCQ command.  At this point the tag is the
 		 * active tag.  It is the tag that matches the command about to
 		 * be completed.
 		 */
+		trace_ata_bmdma_start(ap, &qc->tf, tag);
 		qc->ap->link.active_tag = tag;
 		sata_dwc_bmdma_start_by_tag(qc, tag);
 
@@ -581,7 +546,7 @@ static irqreturn_t sata_dwc_isr(int irq, void *dev_instance)
 
 		if (status & ATA_ERR) {
 			dev_dbg(ap->dev, "interrupt ATA_ERR (0x%x)\n", status);
-			sata_dwc_qc_complete(ap, qc, 1);
+			sata_dwc_qc_complete(ap, qc);
 			handled = 1;
 			goto DONE;
 		}
@@ -606,13 +571,13 @@ DRVSTILLBUSY:
 			}
 
 			if ((hsdevp->dma_interrupt_count % 2) == 0)
-				sata_dwc_dma_xfer_complete(ap, 1);
+				sata_dwc_dma_xfer_complete(ap);
 		} else if (ata_is_pio(qc->tf.protocol)) {
 			ata_sff_hsm_move(ap, qc, status, 0);
 			handled = 1;
 			goto DONE;
 		} else {
-			if (unlikely(sata_dwc_qc_complete(ap, qc, 1)))
+			if (unlikely(sata_dwc_qc_complete(ap, qc)))
 				goto DRVSTILLBUSY;
 		}
 
@@ -648,9 +613,7 @@ DRVSTILLBUSY:
 	dev_dbg(ap->dev, "%s ATA status register=0x%x\n", __func__, status);
 
 	tag = 0;
-	num_processed = 0;
 	while (tag_mask) {
-		num_processed++;
 		while (!(tag_mask & 0x00000001)) {
 			tag++;
 			tag_mask <<= 1;
@@ -658,6 +621,11 @@ DRVSTILLBUSY:
 
 		tag_mask &= (~0x00000001);
 		qc = ata_qc_from_tag(ap, tag);
+		if (unlikely(!qc)) {
+			dev_err(ap->dev, "failed to get qc");
+			handled = 1;
+			goto DONE;
+		}
 
 		/* To be picked up by completion functions */
 		qc->ap->link.active_tag = tag;
@@ -667,7 +635,7 @@ DRVSTILLBUSY:
 		if (status & ATA_ERR) {
 			dev_dbg(ap->dev, "%s ATA_ERR (0x%x)\n", __func__,
 				status);
-			sata_dwc_qc_complete(ap, qc, 1);
+			sata_dwc_qc_complete(ap, qc);
 			handled = 1;
 			goto DONE;
 		}
@@ -682,9 +650,9 @@ DRVSTILLBUSY:
 				dev_warn(ap->dev, "%s: DMA not pending?\n",
 					__func__);
 			if ((hsdevp->dma_interrupt_count % 2) == 0)
-				sata_dwc_dma_xfer_complete(ap, 1);
+				sata_dwc_dma_xfer_complete(ap);
 		} else {
-			if (unlikely(sata_dwc_qc_complete(ap, qc, 1)))
+			if (unlikely(sata_dwc_qc_complete(ap, qc)))
 				goto STILLBUSY;
 		}
 		continue;
@@ -739,7 +707,7 @@ static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag)
 	}
 }
 
-static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status)
+static void sata_dwc_dma_xfer_complete(struct ata_port *ap)
 {
 	struct ata_queued_cmd *qc;
 	struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
@@ -753,17 +721,6 @@ static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status)
 		return;
 	}
 
-#ifdef DEBUG_NCQ
-	if (tag > 0) {
-		dev_info(ap->dev,
-			 "%s tag=%u cmd=0x%02x dma dir=%s proto=%s dmacr=0x%08x\n",
-			 __func__, qc->hw_tag, qc->tf.command,
-			 get_dma_dir_descript(qc->dma_dir),
-			 get_prot_descript(qc->tf.protocol),
-			 sata_dwc_readl(&hsdev->sata_dwc_regs->dmacr));
-	}
-#endif
-
 	if (ata_is_dma(qc->tf.protocol)) {
 		if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_NONE) {
 			dev_err(ap->dev,
@@ -773,15 +730,14 @@ static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status)
 		}
 
 		hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_NONE;
-		sata_dwc_qc_complete(ap, qc, check_status);
+		sata_dwc_qc_complete(ap, qc);
 		ap->link.active_tag = ATA_TAG_POISON;
 	} else {
-		sata_dwc_qc_complete(ap, qc, check_status);
+		sata_dwc_qc_complete(ap, qc);
 	}
 }
 
-static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
-				u32 check_status)
+static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc)
 {
 	u8 status = 0;
 	u32 mask = 0x0;
@@ -789,7 +745,6 @@ static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
 	struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
 	struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
 	hsdev->sactive_queued = 0;
-	dev_dbg(ap->dev, "%s checkstatus? %x\n", __func__, check_status);
 
 	if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX)
 		dev_err(ap->dev, "TX DMA PENDING\n");
@@ -854,7 +809,7 @@ static int sata_dwc_dma_get_channel(struct sata_dwc_device_port *hsdevp)
 	struct device *dev = hsdev->dev;
 
 #ifdef CONFIG_SATA_DWC_OLD_DMA
-	if (!of_find_property(dev->of_node, "dmas", NULL))
+	if (!of_property_present(dev->of_node, "dmas"))
 		return sata_dwc_dma_get_channel_old(hsdevp);
 #endif
 
@@ -970,9 +925,6 @@ static void sata_dwc_exec_command_by_tag(struct ata_port *ap,
 {
 	struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
 
-	dev_dbg(ap->dev, "%s cmd(0x%02x): %s tag=%d\n", __func__, tf->command,
-		ata_get_cmd_descript(tf->command), tag);
-
 	hsdevp->cmd_issued[tag] = cmd_issued;
 
 	/*
@@ -995,12 +947,9 @@ static void sata_dwc_bmdma_setup(struct ata_queued_cmd *qc)
 {
 	u8 tag = qc->hw_tag;
 
-	if (ata_is_ncq(qc->tf.protocol)) {
-		dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n",
-			__func__, qc->ap->link.sactive, tag);
-	} else {
+	if (!ata_is_ncq(qc->tf.protocol))
 		tag = 0;
-	}
+
 	sata_dwc_bmdma_setup_by_tag(qc, tag);
 }
 
@@ -1027,12 +976,6 @@ static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag)
 		start_dma = 0;
 	}
 
-	dev_dbg(ap->dev,
-		"%s qc=%p tag: %x cmd: 0x%02x dma_dir: %s start_dma? %x\n",
-		__func__, qc, tag, qc->tf.command,
-		get_dma_dir_descript(qc->dma_dir), start_dma);
-	sata_dwc_tf_dump(ap, &qc->tf);
-
 	if (start_dma) {
 		sata_dwc_scr_read(&ap->link, SCR_ERROR, &reg);
 		if (reg & SATA_DWC_SERROR_ERR_BITS) {
@@ -1057,13 +1000,9 @@ static void sata_dwc_bmdma_start(struct ata_queued_cmd *qc)
 {
 	u8 tag = qc->hw_tag;
 
-	if (ata_is_ncq(qc->tf.protocol)) {
-		dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n",
-			__func__, qc->ap->link.sactive, tag);
-	} else {
+	if (!ata_is_ncq(qc->tf.protocol))
 		tag = 0;
-	}
-	dev_dbg(qc->ap->dev, "%s\n", __func__);
+
 	sata_dwc_bmdma_start_by_tag(qc, tag);
 }
 
@@ -1074,16 +1013,6 @@ static unsigned int sata_dwc_qc_issue(struct ata_queued_cmd *qc)
 	struct ata_port *ap = qc->ap;
 	struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
 
-#ifdef DEBUG_NCQ
-	if (qc->hw_tag > 0 || ap->link.sactive > 1)
-		dev_info(ap->dev,
-			 "%s ap id=%d cmd(0x%02x)=%s qc tag=%d prot=%s ap active_tag=0x%08x ap sactive=0x%08x\n",
-			 __func__, ap->print_id, qc->tf.command,
-			 ata_get_cmd_descript(qc->tf.command),
-			 qc->hw_tag, get_prot_descript(qc->tf.protocol),
-			 ap->link.active_tag, ap->link.sactive);
-#endif
-
 	if (!ata_is_ncq(qc->tf.protocol))
 		tag = 0;
 
@@ -1100,11 +1029,9 @@ static unsigned int sata_dwc_qc_issue(struct ata_queued_cmd *qc)
 		sactive |= (0x00000001 << tag);
 		sata_dwc_scr_write(&ap->link, SCR_ACTIVE, sactive);
 
-		dev_dbg(qc->ap->dev,
-			"%s: tag=%d ap->link.sactive = 0x%08x sactive=0x%08x\n",
-			__func__, tag, qc->ap->link.sactive, sactive);
-
+		trace_ata_tf_load(ap, &qc->tf);
 		ap->ops->sff_tf_load(ap, &qc->tf);
+		trace_ata_exec_command(ap, &qc->tf, tag);
 		sata_dwc_exec_command_by_tag(ap, &qc->tf, tag,
 					     SATA_DWC_CMD_ISSUED_PEND);
 	} else {
@@ -1148,7 +1075,7 @@ static void sata_dwc_dev_select(struct ata_port *ap, unsigned int device)
 /*
  * scsi mid-layer and libata interface structures
  */
-static struct scsi_host_template sata_dwc_sht = {
+static const struct scsi_host_template sata_dwc_sht = {
 	ATA_NCQ_SHT(DRV_NAME),
 	/*
 	 * test-only: Currently this driver doesn't handle NCQ
@@ -1170,7 +1097,7 @@ static struct ata_port_operations sata_dwc_ops = {
 	.inherits		= &ata_sff_port_ops,
 
 	.error_handler		= sata_dwc_error_handler,
-	.hardreset		= sata_dwc_hardreset,
+	.reset.hardreset	= sata_dwc_hardreset,
 
 	.qc_issue		= sata_dwc_qc_issue,
 
@@ -1197,6 +1124,8 @@ static const struct ata_port_info sata_dwc_port_info[] = {
 
 static int sata_dwc_probe(struct platform_device *ofdev)
 {
+	struct device *dev = &ofdev->dev;
+	struct device_node *np = dev->of_node;
 	struct sata_dwc_device *hsdev;
 	u32 idr, versionr;
 	char *ver = (char *)&versionr;
@@ -1206,23 +1135,21 @@ static int sata_dwc_probe(struct platform_device *ofdev)
 	struct ata_host *host;
 	struct ata_port_info pi = sata_dwc_port_info[0];
 	const struct ata_port_info *ppi[] = { &pi, NULL };
-	struct device_node *np = ofdev->dev.of_node;
 	struct resource *res;
 
 	/* Allocate DWC SATA device */
-	host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_DWC_MAX_PORTS);
-	hsdev = devm_kzalloc(&ofdev->dev, sizeof(*hsdev), GFP_KERNEL);
+	host = ata_host_alloc_pinfo(dev, ppi, SATA_DWC_MAX_PORTS);
+	hsdev = devm_kzalloc(dev, sizeof(*hsdev), GFP_KERNEL);
 	if (!host || !hsdev)
 		return -ENOMEM;
 
 	host->private_data = hsdev;
 
 	/* Ioremap SATA registers */
-	res = platform_get_resource(ofdev, IORESOURCE_MEM, 0);
-	base = devm_ioremap_resource(&ofdev->dev, res);
+	base = devm_platform_get_and_ioremap_resource(ofdev, 0, &res);
 	if (IS_ERR(base))
 		return PTR_ERR(base);
-	dev_dbg(&ofdev->dev, "ioremap done for SATA register address\n");
+	dev_dbg(dev, "ioremap done for SATA register address\n");
 
 	/* Synopsys DWC SATA specific Registers */
 	hsdev->sata_dwc_regs = base + SATA_DWC_REG_OFFSET;
@@ -1236,37 +1163,32 @@ static int sata_dwc_probe(struct platform_device *ofdev)
 	/* Read the ID and Version Registers */
 	idr = sata_dwc_readl(&hsdev->sata_dwc_regs->idr);
 	versionr = sata_dwc_readl(&hsdev->sata_dwc_regs->versionr);
-	dev_notice(&ofdev->dev, "id %d, controller version %c.%c%c\n",
-		   idr, ver[0], ver[1], ver[2]);
+	dev_notice(dev, "id %d, controller version %c.%c%c\n", idr, ver[0], ver[1], ver[2]);
 
 	/* Save dev for later use in dev_xxx() routines */
-	hsdev->dev = &ofdev->dev;
+	hsdev->dev = dev;
 
 	/* Enable SATA Interrupts */
 	sata_dwc_enable_interrupts(hsdev);
 
 	/* Get SATA interrupt number */
 	irq = irq_of_parse_and_map(np, 0);
-	if (irq == NO_IRQ) {
-		dev_err(&ofdev->dev, "no SATA DMA irq\n");
-		err = -ENODEV;
-		goto error_out;
+	if (!irq) {
+		dev_err(dev, "no SATA DMA irq\n");
+		return -ENODEV;
 	}
 
 #ifdef CONFIG_SATA_DWC_OLD_DMA
-	if (!of_find_property(np, "dmas", NULL)) {
+	if (!of_property_present(np, "dmas")) {
 		err = sata_dwc_dma_init_old(ofdev, hsdev);
 		if (err)
-			goto error_out;
+			return err;
 	}
 #endif
 
-	hsdev->phy = devm_phy_optional_get(hsdev->dev, "sata-phy");
-	if (IS_ERR(hsdev->phy)) {
-		err = PTR_ERR(hsdev->phy);
-		hsdev->phy = NULL;
-		goto error_out;
-	}
+	hsdev->phy = devm_phy_optional_get(dev, "sata-phy");
+	if (IS_ERR(hsdev->phy))
+		return PTR_ERR(hsdev->phy);
 
 	err = phy_init(hsdev->phy);
 	if (err)
@@ -1279,7 +1201,7 @@ static int sata_dwc_probe(struct platform_device *ofdev)
 	 */
 	err = ata_host_activate(host, irq, sata_dwc_isr, 0, &sata_dwc_sht);
 	if (err)
-		dev_err(&ofdev->dev, "failed to activate host");
+		dev_err(dev, "failed to activate host");
 
 	return 0;
 
@@ -1288,7 +1210,7 @@ error_out:
 	return err;
 }
 
-static int sata_dwc_remove(struct platform_device *ofdev)
+static void sata_dwc_remove(struct platform_device *ofdev)
 {
 	struct device *dev = &ofdev->dev;
 	struct ata_host *host = dev_get_drvdata(dev);
@@ -1303,8 +1225,7 @@ static int sata_dwc_remove(struct platform_device *ofdev)
 	sata_dwc_dma_exit_old(hsdev);
 #endif
 
-	dev_dbg(&ofdev->dev, "done\n");
-	return 0;
+	dev_dbg(dev, "done\n");
 }
 
 static const struct of_device_id sata_dwc_match[] = {
diff --git a/drivers/ata/sata_fsl.c b/drivers/ata/sata_fsl.c
index d55ee244d693..84da8d6ef28e 100644
--- a/drivers/ata/sata_fsl.c
+++ b/drivers/ata/sata_fsl.c
@@ -12,6 +12,9 @@
 
 #include <linux/kernel.h>
 #include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 
@@ -19,9 +22,6 @@
 #include <scsi/scsi_cmnd.h>
 #include <linux/libata.h>
 #include <asm/io.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/of_platform.h>
 
 static unsigned int intr_coalescing_count;
 module_param(intr_coalescing_count, int, S_IRUGO);
@@ -221,10 +221,10 @@ enum {
  * 4 Dwords per command slot, command header size ==  64 Dwords.
  */
 struct cmdhdr_tbl_entry {
-	u32 cda;
-	u32 prde_fis_len;
-	u32 ttl;
-	u32 desc_info;
+	__le32 cda;
+	__le32 prde_fis_len;
+	__le32 ttl;
+	__le32 desc_info;
 };
 
 /*
@@ -246,8 +246,10 @@ enum {
 struct command_desc {
 	u8 cfis[8 * 4];
 	u8 sfis[8 * 4];
-	u8 acmd[4 * 4];
-	u8 fill[4 * 4];
+	struct_group(cdb,
+		u8 acmd[4 * 4];
+		u8 fill[4 * 4];
+	);
 	u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4];
 	u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4];
 };
@@ -257,9 +259,9 @@ struct command_desc {
  */
 
 struct prde {
-	u32 dba;
+	__le32 dba;
 	u8 fill[2 * 4];
-	u32 ddc_and_ext;
+	__le32 ddc_and_ext;
 };
 
 /*
@@ -311,16 +313,16 @@ static void fsl_sata_set_irq_coalescing(struct ata_host *host,
 	intr_coalescing_ticks = ticks;
 	spin_unlock_irqrestore(&host->lock, flags);
 
-	DPRINTK("interrupt coalescing, count = 0x%x, ticks = %x\n",
-			intr_coalescing_count, intr_coalescing_ticks);
-	DPRINTK("ICC register status: (hcr base: 0x%x) = 0x%x\n",
-			hcr_base, ioread32(hcr_base + ICC));
+	dev_dbg(host->dev, "interrupt coalescing, count = 0x%x, ticks = %x\n",
+		intr_coalescing_count, intr_coalescing_ticks);
+	dev_dbg(host->dev, "ICC register status: (hcr base: 0x%p) = 0x%x\n",
+		hcr_base, ioread32(hcr_base + ICC));
 }
 
 static ssize_t fsl_sata_intr_coalescing_show(struct device *dev,
 		struct device_attribute *attr, char *buf)
 {
-	return sprintf(buf, "%d	%d\n",
+	return sysfs_emit(buf, "%u	%u\n",
 			intr_coalescing_count, intr_coalescing_ticks);
 }
 
@@ -330,10 +332,8 @@ static ssize_t fsl_sata_intr_coalescing_store(struct device *dev,
 {
 	unsigned int coalescing_count,	coalescing_ticks;
 
-	if (sscanf(buf, "%d%d",
-				&coalescing_count,
-				&coalescing_ticks) != 2) {
-		printk(KERN_ERR "fsl-sata: wrong parameter format.\n");
+	if (sscanf(buf, "%u%u", &coalescing_count, &coalescing_ticks) != 2) {
+		dev_err(dev, "fsl-sata: wrong parameter format.\n");
 		return -EINVAL;
 	}
 
@@ -355,9 +355,9 @@ static ssize_t fsl_sata_rx_watermark_show(struct device *dev,
 	spin_lock_irqsave(&host->lock, flags);
 	rx_watermark = ioread32(csr_base + TRANSCFG);
 	rx_watermark &= 0x1f;
-
 	spin_unlock_irqrestore(&host->lock, flags);
-	return sprintf(buf, "%d\n", rx_watermark);
+
+	return sysfs_emit(buf, "%u\n", rx_watermark);
 }
 
 static ssize_t fsl_sata_rx_watermark_store(struct device *dev,
@@ -371,8 +371,8 @@ static ssize_t fsl_sata_rx_watermark_store(struct device *dev,
 	void __iomem *csr_base = host_priv->csr_base;
 	u32 temp;
 
-	if (sscanf(buf, "%d", &rx_watermark) != 1) {
-		printk(KERN_ERR "fsl-sata: wrong parameter format.\n");
+	if (kstrtouint(buf, 10, &rx_watermark) < 0) {
+		dev_err(dev, "fsl-sata: wrong parameter format.\n");
 		return -EINVAL;
 	}
 
@@ -380,30 +380,32 @@ static ssize_t fsl_sata_rx_watermark_store(struct device *dev,
 	temp = ioread32(csr_base + TRANSCFG);
 	temp &= 0xffffffe0;
 	iowrite32(temp | rx_watermark, csr_base + TRANSCFG);
-
 	spin_unlock_irqrestore(&host->lock, flags);
+
 	return strlen(buf);
 }
 
-static inline unsigned int sata_fsl_tag(unsigned int tag,
+static inline unsigned int sata_fsl_tag(struct ata_port *ap,
+					unsigned int tag,
 					void __iomem *hcr_base)
 {
 	/* We let libATA core do actual (queue) tag allocation */
 
 	if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) {
-		DPRINTK("tag %d invalid : out of range\n", tag);
+		ata_port_dbg(ap, "tag %d invalid : out of range\n", tag);
 		return 0;
 	}
 
 	if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) {
-		DPRINTK("tag %d invalid : in use!!\n", tag);
+		ata_port_dbg(ap, "tag %d invalid : in use!!\n", tag);
 		return 0;
 	}
 
 	return tag;
 }
 
-static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp,
+static void sata_fsl_setup_cmd_hdr_entry(struct ata_port *ap,
+					 struct sata_fsl_port_priv *pp,
 					 unsigned int tag, u32 desc_info,
 					 u32 data_xfer_len, u8 num_prde,
 					 u8 fis_len)
@@ -421,11 +423,11 @@ static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp,
 	pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03);
 	pp->cmdslot[tag].desc_info = cpu_to_le32(desc_info | (tag & 0x1F));
 
-	VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n",
-		pp->cmdslot[tag].cda,
-		pp->cmdslot[tag].prde_fis_len,
-		pp->cmdslot[tag].ttl, pp->cmdslot[tag].desc_info);
-
+	ata_port_dbg(ap, "cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n",
+		     le32_to_cpu(pp->cmdslot[tag].cda),
+		     le32_to_cpu(pp->cmdslot[tag].prde_fis_len),
+		     le32_to_cpu(pp->cmdslot[tag].ttl),
+		     le32_to_cpu(pp->cmdslot[tag].desc_info));
 }
 
 static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc,
@@ -447,8 +449,6 @@ static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc,
 	dma_addr_t indirect_ext_segment_paddr;
 	unsigned int si;
 
-	VPRINTK("SATA FSL : cd = 0x%p, prd = 0x%p\n", cmd_desc, prd);
-
 	indirect_ext_segment_paddr = cmd_desc_paddr +
 	    SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16;
 
@@ -456,9 +456,6 @@ static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc,
 		dma_addr_t sg_addr = sg_dma_address(sg);
 		u32 sg_len = sg_dma_len(sg);
 
-		VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%llx, sg_len = %d\n",
-			(unsigned long long)sg_addr, sg_len);
-
 		/* warn if each s/g element is not dword aligned */
 		if (unlikely(sg_addr & 0x03))
 			ata_port_err(qc->ap, "s/g addr unaligned : 0x%llx\n",
@@ -469,7 +466,6 @@ static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc,
 
 		if (num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1) &&
 		    sg_next(sg) != NULL) {
-			VPRINTK("setting indirect prde\n");
 			prd_ptr_to_indirect_ext = prd;
 			prd->dba = cpu_to_le32(indirect_ext_segment_paddr);
 			indirect_ext_segment_sz = 0;
@@ -481,9 +477,6 @@ static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc,
 		prd->dba = cpu_to_le32(sg_addr);
 		prd->ddc_and_ext = cpu_to_le32(data_snoop | (sg_len & ~0x03));
 
-		VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n",
-			ttl_dwords, prd->dba, prd->ddc_and_ext);
-
 		++num_prde;
 		++prd;
 		if (prd_ptr_to_indirect_ext)
@@ -508,7 +501,7 @@ static enum ata_completion_errors sata_fsl_qc_prep(struct ata_queued_cmd *qc)
 	struct sata_fsl_port_priv *pp = ap->private_data;
 	struct sata_fsl_host_priv *host_priv = ap->host->private_data;
 	void __iomem *hcr_base = host_priv->hcr_base;
-	unsigned int tag = sata_fsl_tag(qc->hw_tag, hcr_base);
+	unsigned int tag = sata_fsl_tag(ap, qc->hw_tag, hcr_base);
 	struct command_desc *cd;
 	u32 desc_info = CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE;
 	u32 num_prde = 0;
@@ -520,19 +513,11 @@ static enum ata_completion_errors sata_fsl_qc_prep(struct ata_queued_cmd *qc)
 
 	ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, (u8 *) &cd->cfis);
 
-	VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n",
-		cd->cfis[0], cd->cfis[1], cd->cfis[2]);
-
-	if (qc->tf.protocol == ATA_PROT_NCQ) {
-		VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n",
-			cd->cfis[3], cd->cfis[11]);
-	}
-
 	/* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */
 	if (ata_is_atapi(qc->tf.protocol)) {
 		desc_info |= ATAPI_CMD;
-		memset((void *)&cd->acmd, 0, 32);
-		memcpy((void *)&cd->acmd, qc->cdb, qc->dev->cdb_len);
+		memset(&cd->cdb, 0, sizeof(cd->cdb));
+		memcpy(&cd->cdb, qc->cdb, qc->dev->cdb_len);
 	}
 
 	if (qc->flags & ATA_QCFLAG_DMAMAP)
@@ -543,10 +528,10 @@ static enum ata_completion_errors sata_fsl_qc_prep(struct ata_queued_cmd *qc)
 	if (qc->tf.protocol == ATA_PROT_NCQ)
 		desc_info |= FPDMA_QUEUED_CMD;
 
-	sata_fsl_setup_cmd_hdr_entry(pp, tag, desc_info, ttl_dwords,
+	sata_fsl_setup_cmd_hdr_entry(ap, pp, tag, desc_info, ttl_dwords,
 				     num_prde, 5);
 
-	VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n",
+	ata_port_dbg(ap, "SATA FSL : di = 0x%x, ttl = %d, num_prde = %d\n",
 		desc_info, ttl_dwords, num_prde);
 
 	return AC_ERR_OK;
@@ -557,9 +542,9 @@ static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc)
 	struct ata_port *ap = qc->ap;
 	struct sata_fsl_host_priv *host_priv = ap->host->private_data;
 	void __iomem *hcr_base = host_priv->hcr_base;
-	unsigned int tag = sata_fsl_tag(qc->hw_tag, hcr_base);
+	unsigned int tag = sata_fsl_tag(ap, qc->hw_tag, hcr_base);
 
-	VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n",
+	ata_port_dbg(ap, "CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n",
 		ioread32(CQ + hcr_base),
 		ioread32(CA + hcr_base),
 		ioread32(CE + hcr_base), ioread32(CC + hcr_base));
@@ -569,10 +554,10 @@ static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc)
 	/* Simply queue command to the controller/device */
 	iowrite32(1 << tag, CQ + hcr_base);
 
-	VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n",
+	ata_port_dbg(ap, "tag=%d, CQ=0x%x, CA=0x%x\n",
 		tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base));
 
-	VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n",
+	ata_port_dbg(ap, "CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n",
 		ioread32(CE + hcr_base),
 		ioread32(DE + hcr_base),
 		ioread32(CC + hcr_base),
@@ -581,18 +566,17 @@ static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc)
 	return 0;
 }
 
-static bool sata_fsl_qc_fill_rtf(struct ata_queued_cmd *qc)
+static void sata_fsl_qc_fill_rtf(struct ata_queued_cmd *qc)
 {
 	struct sata_fsl_port_priv *pp = qc->ap->private_data;
 	struct sata_fsl_host_priv *host_priv = qc->ap->host->private_data;
 	void __iomem *hcr_base = host_priv->hcr_base;
-	unsigned int tag = sata_fsl_tag(qc->hw_tag, hcr_base);
+	unsigned int tag = sata_fsl_tag(qc->ap, qc->hw_tag, hcr_base);
 	struct command_desc *cd;
 
 	cd = pp->cmdentry + tag;
 
 	ata_tf_from_fis(cd->sfis, &qc->result_tf);
-	return true;
 }
 
 static int sata_fsl_scr_write(struct ata_link *link,
@@ -613,7 +597,7 @@ static int sata_fsl_scr_write(struct ata_link *link,
 		return -EINVAL;
 	}
 
-	VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg);
+	ata_link_dbg(link, "reg_in = %d\n", sc_reg);
 
 	iowrite32(val, ssr_base + (sc_reg * 4));
 	return 0;
@@ -637,7 +621,7 @@ static int sata_fsl_scr_read(struct ata_link *link,
 		return -EINVAL;
 	}
 
-	VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg);
+	ata_link_dbg(link, "reg_in = %d\n", sc_reg);
 
 	*val = ioread32(ssr_base + (sc_reg * 4));
 	return 0;
@@ -649,18 +633,18 @@ static void sata_fsl_freeze(struct ata_port *ap)
 	void __iomem *hcr_base = host_priv->hcr_base;
 	u32 temp;
 
-	VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n",
+	ata_port_dbg(ap, "CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n",
 		ioread32(CQ + hcr_base),
 		ioread32(CA + hcr_base),
 		ioread32(CE + hcr_base), ioread32(DE + hcr_base));
-	VPRINTK("CmdStat = 0x%x\n",
+	ata_port_dbg(ap, "CmdStat = 0x%x\n",
 		ioread32(host_priv->csr_base + COMMANDSTAT));
 
 	/* disable interrupts on the controller/port */
 	temp = ioread32(hcr_base + HCONTROL);
 	iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
 
-	VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n",
+	ata_port_dbg(ap, "HControl = 0x%x, HStatus = 0x%x\n",
 		ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
 }
 
@@ -673,7 +657,7 @@ static void sata_fsl_thaw(struct ata_port *ap)
 	/* ack. any pending IRQs for this controller/port */
 	temp = ioread32(hcr_base + HSTATUS);
 
-	VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp & 0x3F));
+	ata_port_dbg(ap, "pending IRQs = 0x%x\n", (temp & 0x3F));
 
 	if (temp & 0x3F)
 		iowrite32((temp & 0x3F), hcr_base + HSTATUS);
@@ -682,7 +666,7 @@ static void sata_fsl_thaw(struct ata_port *ap)
 	temp = ioread32(hcr_base + HCONTROL);
 	iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
 
-	VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n",
+	ata_port_dbg(ap, "HControl = 0x%x, HStatus = 0x%x\n",
 		ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
 }
 
@@ -744,8 +728,9 @@ static int sata_fsl_port_start(struct ata_port *ap)
 
 	ap->private_data = pp;
 
-	VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n",
-		pp->cmdslot_paddr, pp->cmdentry_paddr);
+	ata_port_dbg(ap, "CHBA = 0x%lx, cmdentry_phys = 0x%lx\n",
+		(unsigned long)pp->cmdslot_paddr,
+		(unsigned long)pp->cmdentry_paddr);
 
 	/* Now, update the CHBA register in host controller cmd register set */
 	iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
@@ -761,9 +746,9 @@ static int sata_fsl_port_start(struct ata_port *ap)
 	temp = ioread32(hcr_base + HCONTROL);
 	iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL);
 
-	VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
-	VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
-	VPRINTK("CHBA  = 0x%x\n", ioread32(hcr_base + CHBA));
+	ata_port_dbg(ap, "HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
+	ata_port_dbg(ap, "HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
+	ata_port_dbg(ap, "CHBA  = 0x%x\n", ioread32(hcr_base + CHBA));
 
 	return 0;
 }
@@ -803,16 +788,15 @@ static unsigned int sata_fsl_dev_classify(struct ata_port *ap)
 
 	temp = ioread32(hcr_base + SIGNATURE);
 
-	VPRINTK("raw sig = 0x%x\n", temp);
-	VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
-	VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
+	ata_port_dbg(ap, "HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
+	ata_port_dbg(ap, "HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
 
 	tf.lbah = (temp >> 24) & 0xff;
 	tf.lbam = (temp >> 16) & 0xff;
 	tf.lbal = (temp >> 8) & 0xff;
 	tf.nsect = temp & 0xff;
 
-	return ata_dev_classify(&tf);
+	return ata_port_classify(ap, &tf);
 }
 
 static int sata_fsl_hardreset(struct ata_link *link, unsigned int *class,
@@ -825,8 +809,6 @@ static int sata_fsl_hardreset(struct ata_link *link, unsigned int *class,
 	int i = 0;
 	unsigned long start_jiffies;
 
-	DPRINTK("in xx_hardreset\n");
-
 try_offline_again:
 	/*
 	 * Force host controller to go off-line, aborting current operations
@@ -852,9 +834,10 @@ try_offline_again:
 			goto try_offline_again;
 	}
 
-	DPRINTK("hardreset, controller off-lined\n");
-	VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
-	VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
+	ata_port_dbg(ap, "hardreset, controller off-lined\n"
+		     "HStatus = 0x%x HControl = 0x%x\n",
+		     ioread32(hcr_base + HSTATUS),
+		     ioread32(hcr_base + HCONTROL));
 
 	/*
 	 * PHY reset should remain asserted for atleast 1ms
@@ -882,9 +865,10 @@ try_offline_again:
 		goto err;
 	}
 
-	DPRINTK("hardreset, controller off-lined & on-lined\n");
-	VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
-	VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
+	ata_port_dbg(ap, "controller off-lined & on-lined\n"
+		     "HStatus = 0x%x HControl = 0x%x\n",
+		     ioread32(hcr_base + HSTATUS),
+		     ioread32(hcr_base + HCONTROL));
 
 	/*
 	 * First, wait for the PHYRDY change to occur before waiting for
@@ -941,10 +925,7 @@ static int sata_fsl_softreset(struct ata_link *link, unsigned int *class,
 	u8 *cfis;
 	u32 Serror;
 
-	DPRINTK("in xx_softreset\n");
-
 	if (ata_link_offline(link)) {
-		DPRINTK("PHY reports no device\n");
 		*class = ATA_DEV_NONE;
 		return 0;
 	}
@@ -957,19 +938,17 @@ static int sata_fsl_softreset(struct ata_link *link, unsigned int *class,
 	 * reached here, we can send a command to the target device
 	 */
 
-	DPRINTK("Sending SRST/device reset\n");
-
 	ata_tf_init(link->device, &tf);
 	cfis = (u8 *) &pp->cmdentry->cfis;
 
 	/* device reset/SRST is a control register update FIS, uses tag0 */
-	sata_fsl_setup_cmd_hdr_entry(pp, 0,
+	sata_fsl_setup_cmd_hdr_entry(ap, pp, 0,
 		SRST_CMD | CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 0, 0, 5);
 
 	tf.ctl |= ATA_SRST;	/* setup SRST bit in taskfile control reg */
 	ata_tf_to_fis(&tf, pmp, 0, cfis);
 
-	DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n",
+	ata_port_dbg(ap, "Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n",
 		cfis[0], cfis[1], cfis[2], cfis[3]);
 
 	/*
@@ -977,7 +956,7 @@ static int sata_fsl_softreset(struct ata_link *link, unsigned int *class,
 	 * other commands are active on the controller/device
 	 */
 
-	DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n",
+	ata_port_dbg(ap, "CQ = 0x%x, CA = 0x%x, CC = 0x%x\n",
 		ioread32(CQ + hcr_base),
 		ioread32(CA + hcr_base), ioread32(CC + hcr_base));
 
@@ -990,15 +969,16 @@ static int sata_fsl_softreset(struct ata_link *link, unsigned int *class,
 	if (temp & 0x1) {
 		ata_port_warn(ap, "ATA_SRST issue failed\n");
 
-		DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n",
+		ata_port_dbg(ap, "Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n",
 			ioread32(CQ + hcr_base),
 			ioread32(CA + hcr_base), ioread32(CC + hcr_base));
 
 		sata_fsl_scr_read(&ap->link, SCR_ERROR, &Serror);
 
-		DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
-		DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
-		DPRINTK("Serror = 0x%x\n", Serror);
+		ata_port_dbg(ap, "HStatus = 0x%x HControl = 0x%x Serror = 0x%x\n",
+			     ioread32(hcr_base + HSTATUS),
+			     ioread32(hcr_base + HCONTROL),
+			     Serror);
 		goto err;
 	}
 
@@ -1012,8 +992,9 @@ static int sata_fsl_softreset(struct ata_link *link, unsigned int *class,
 	 * using ATA signature D2H register FIS to the host controller.
 	 */
 
-	sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE,
-				      0, 0, 5);
+	sata_fsl_setup_cmd_hdr_entry(ap, pp, 0,
+				     CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE,
+				     0, 0, 5);
 
 	tf.ctl &= ~ATA_SRST;	/* 2nd H2D Ctl. register FIS */
 	ata_tf_to_fis(&tf, pmp, 0, cfis);
@@ -1030,8 +1011,6 @@ static int sata_fsl_softreset(struct ata_link *link, unsigned int *class,
 	 */
 	iowrite32(0x01, CC + hcr_base);	/* We know it will be cmd#0 always */
 
-	DPRINTK("SATA FSL : Now checking device signature\n");
-
 	*class = ATA_DEV_NONE;
 
 	/* Verify if SStatus indicates device presence */
@@ -1045,9 +1024,8 @@ static int sata_fsl_softreset(struct ata_link *link, unsigned int *class,
 
 		*class = sata_fsl_dev_classify(ap);
 
-		DPRINTK("class = %d\n", *class);
-		VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC));
-		VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE));
+		ata_port_dbg(ap, "ccreg = 0x%x\n", ioread32(hcr_base + CC));
+		ata_port_dbg(ap, "cereg = 0x%x\n", ioread32(hcr_base + CE));
 	}
 
 	return 0;
@@ -1058,15 +1036,12 @@ err:
 
 static void sata_fsl_error_handler(struct ata_port *ap)
 {
-
-	DPRINTK("in xx_error_handler\n");
 	sata_pmp_error_handler(ap);
-
 }
 
 static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc)
 {
-	if (qc->flags & ATA_QCFLAG_FAILED)
+	if (qc->flags & ATA_QCFLAG_EH)
 		qc->err_mask |= AC_ERR_OTHER;
 
 	if (qc->err_mask) {
@@ -1102,7 +1077,7 @@ static void sata_fsl_error_intr(struct ata_port *ap)
 	if (unlikely(SError & 0xFFFF0000))
 		sata_fsl_scr_write(&ap->link, SCR_ERROR, SError);
 
-	DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n",
+	ata_port_dbg(ap, "hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n",
 		hstatus, cereg, ioread32(hcr_base + DE), SError);
 
 	/* handle fatal errors */
@@ -1119,7 +1094,7 @@ static void sata_fsl_error_intr(struct ata_port *ap)
 
 	/* Handle PHYRDY change notification */
 	if (hstatus & INT_ON_PHYRDY_CHG) {
-		DPRINTK("SATA FSL: PHYRDY change indication\n");
+		ata_port_dbg(ap, "PHYRDY change indication\n");
 
 		/* Setup a soft-reset EH action */
 		ata_ehi_hotplugged(ehi);
@@ -1140,7 +1115,7 @@ static void sata_fsl_error_intr(struct ata_port *ap)
 		 */
 		abort = 1;
 
-		DPRINTK("single device error, CE=0x%x, DE=0x%x\n",
+		ata_port_dbg(ap, "single device error, CE=0x%x, DE=0x%x\n",
 			ioread32(hcr_base + CE), ioread32(hcr_base + DE));
 
 		/* find out the offending link and qc */
@@ -1245,18 +1220,18 @@ static void sata_fsl_host_intr(struct ata_port *ap)
 	}
 
 	if (unlikely(SError & 0xFFFF0000)) {
-		DPRINTK("serror @host_intr : 0x%x\n", SError);
+		ata_port_dbg(ap, "serror @host_intr : 0x%x\n", SError);
 		sata_fsl_error_intr(ap);
 	}
 
 	if (unlikely(hstatus & status_mask)) {
-		DPRINTK("error interrupt!!\n");
+		ata_port_dbg(ap, "error interrupt!!\n");
 		sata_fsl_error_intr(ap);
 		return;
 	}
 
-	VPRINTK("Status of all queues :\n");
-	VPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%llx\n",
+	ata_port_dbg(ap, "Status of all queues :\n");
+	ata_port_dbg(ap, "done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%llx\n",
 		done_mask,
 		ioread32(hcr_base + CA),
 		ioread32(hcr_base + CE),
@@ -1268,15 +1243,13 @@ static void sata_fsl_host_intr(struct ata_port *ap)
 		/* clear CC bit, this will also complete the interrupt */
 		iowrite32(done_mask, hcr_base + CC);
 
-		DPRINTK("Status of all queues :\n");
-		DPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x\n",
+		ata_port_dbg(ap, "Status of all queues: done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x\n",
 			done_mask, ioread32(hcr_base + CA),
 			ioread32(hcr_base + CE));
 
 		for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) {
 			if (done_mask & (1 << i))
-				DPRINTK
-				    ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n",
+				ata_port_dbg(ap, "completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n",
 				     i, ioread32(hcr_base + CC),
 				     ioread32(hcr_base + CA));
 		}
@@ -1287,7 +1260,7 @@ static void sata_fsl_host_intr(struct ata_port *ap)
 		iowrite32(1, hcr_base + CC);
 		qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL);
 
-		DPRINTK("completing non-ncq cmd, CC=0x%x\n",
+		ata_port_dbg(ap, "completing non-ncq cmd, CC=0x%x\n",
 			 ioread32(hcr_base + CC));
 
 		if (qc) {
@@ -1295,7 +1268,7 @@ static void sata_fsl_host_intr(struct ata_port *ap)
 		}
 	} else {
 		/* Spurious Interrupt!! */
-		DPRINTK("spurious interrupt!!, CC = 0x%x\n",
+		ata_port_dbg(ap, "spurious interrupt!!, CC = 0x%x\n",
 			ioread32(hcr_base + CC));
 		iowrite32(done_mask, hcr_base + CC);
 		return;
@@ -1315,8 +1288,6 @@ static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance)
 	interrupt_enables = ioread32(hcr_base + HSTATUS);
 	interrupt_enables &= 0x3F;
 
-	DPRINTK("interrupt status 0x%x\n", interrupt_enables);
-
 	if (!interrupt_enables)
 		return IRQ_NONE;
 
@@ -1369,7 +1340,7 @@ static int sata_fsl_init_controller(struct ata_host *host)
 	iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
 
 	/* Disable interrupt coalescing control(icc), for the moment */
-	DPRINTK("icc = 0x%x\n", ioread32(hcr_base + ICC));
+	dev_dbg(host->dev, "icc = 0x%x\n", ioread32(hcr_base + ICC));
 	iowrite32(0x01000000, hcr_base + ICC);
 
 	/* clear error registers, SError is cleared by libATA  */
@@ -1388,18 +1359,25 @@ static int sata_fsl_init_controller(struct ata_host *host)
 	 * callback, that should also initiate the OOB, COMINIT sequence
 	 */
 
-	DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
-	DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
+	dev_dbg(host->dev, "HStatus = 0x%x HControl = 0x%x\n",
+		ioread32(hcr_base + HSTATUS), ioread32(hcr_base + HCONTROL));
 
 	return 0;
 }
 
+static void sata_fsl_host_stop(struct ata_host *host)
+{
+        struct sata_fsl_host_priv *host_priv = host->private_data;
+
+        iounmap(host_priv->hcr_base);
+        kfree(host_priv);
+}
+
 /*
  * scsi mid-layer and libata interface structures
  */
-static struct scsi_host_template sata_fsl_sht = {
-	ATA_NCQ_SHT("sata_fsl"),
-	.can_queue = SATA_FSL_QUEUE_DEPTH,
+static const struct scsi_host_template sata_fsl_sht = {
+	ATA_NCQ_SHT_QD("sata_fsl", SATA_FSL_QUEUE_DEPTH),
 	.sg_tablesize = SATA_FSL_MAX_PRD_USABLE,
 	.dma_boundary = ATA_DMA_BOUNDARY,
 };
@@ -1417,15 +1395,17 @@ static struct ata_port_operations sata_fsl_ops = {
 
 	.freeze = sata_fsl_freeze,
 	.thaw = sata_fsl_thaw,
-	.softreset = sata_fsl_softreset,
-	.hardreset = sata_fsl_hardreset,
-	.pmp_softreset = sata_fsl_softreset,
+	.reset.softreset = sata_fsl_softreset,
+	.reset.hardreset = sata_fsl_hardreset,
+	.pmp_reset.softreset = sata_fsl_softreset,
 	.error_handler = sata_fsl_error_handler,
 	.post_internal_cmd = sata_fsl_post_internal_cmd,
 
 	.port_start = sata_fsl_port_start,
 	.port_stop = sata_fsl_port_stop,
 
+	.host_stop      = sata_fsl_host_stop,
+
 	.pmp_attach = sata_fsl_pmp_attach,
 	.pmp_detach = sata_fsl_pmp_detach,
 };
@@ -1468,9 +1448,8 @@ static int sata_fsl_probe(struct platform_device *ofdev)
 		iowrite32(temp | TRANSCFG_RX_WATER_MARK, csr_base + TRANSCFG);
 	}
 
-	DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG));
-	DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc));
-	DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE);
+	dev_dbg(&ofdev->dev, "@reset i/o = 0x%x\n",
+		ioread32(csr_base + TRANSCFG));
 
 	host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL);
 	if (!host_priv)
@@ -1480,9 +1459,9 @@ static int sata_fsl_probe(struct platform_device *ofdev)
 	host_priv->ssr_base = ssr_base;
 	host_priv->csr_base = csr_base;
 
-	irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
-	if (!irq) {
-		dev_err(&ofdev->dev, "invalid irq from platform\n");
+	irq = platform_get_irq(ofdev, 0);
+	if (irq < 0) {
+		retval = irq;
 		goto error_exit_with_cleanup;
 	}
 	host_priv->irq = irq;
@@ -1547,7 +1526,7 @@ error_exit_with_cleanup:
 	return retval;
 }
 
-static int sata_fsl_remove(struct platform_device *ofdev)
+static void sata_fsl_remove(struct platform_device *ofdev)
 {
 	struct ata_host *host = platform_get_drvdata(ofdev);
 	struct sata_fsl_host_priv *host_priv = host->private_data;
@@ -1556,19 +1535,15 @@ static int sata_fsl_remove(struct platform_device *ofdev)
 	device_remove_file(&ofdev->dev, &host_priv->rx_watermark);
 
 	ata_host_detach(host);
-
-	irq_dispose_mapping(host_priv->irq);
-	iounmap(host_priv->hcr_base);
-	kfree(host_priv);
-
-	return 0;
 }
 
 #ifdef CONFIG_PM_SLEEP
 static int sata_fsl_suspend(struct platform_device *op, pm_message_t state)
 {
 	struct ata_host *host = platform_get_drvdata(op);
-	return ata_host_suspend(host, state);
+
+	ata_host_suspend(host, state);
+	return 0;
 }
 
 static int sata_fsl_resume(struct platform_device *op)
@@ -1601,13 +1576,9 @@ static int sata_fsl_resume(struct platform_device *op)
 #endif
 
 static const struct of_device_id fsl_sata_match[] = {
-	{
-		.compatible = "fsl,pq-sata",
-	},
-	{
-		.compatible = "fsl,pq-sata-v2",
-	},
-	{},
+	{ .compatible = "fsl,pq-sata", },
+	{ .compatible = "fsl,pq-sata-v2", },
+	{ /* sentinel */ }
 };
 
 MODULE_DEVICE_TABLE(of, fsl_sata_match);
diff --git a/drivers/ata/sata_gemini.c b/drivers/ata/sata_gemini.c
index f793564f3d78..530ee26b3012 100644
--- a/drivers/ata/sata_gemini.c
+++ b/drivers/ata/sata_gemini.c
@@ -11,9 +11,7 @@
 #include <linux/mfd/syscon.h>
 #include <linux/regmap.h>
 #include <linux/delay.h>
-#include <linux/reset.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/pinctrl/consumer.h>
@@ -28,8 +26,6 @@
  * @muxmode: the current muxing mode
  * @ide_pins: if the device is using the plain IDE interface pins
  * @sata_bridge: if the device enables the SATA bridge
- * @sata0_reset: SATA0 reset handler
- * @sata1_reset: SATA1 reset handler
  * @sata0_pclk: SATA0 PCLK handler
  * @sata1_pclk: SATA1 PCLK handler
  */
@@ -39,8 +35,6 @@ struct sata_gemini {
 	enum gemini_muxmode muxmode;
 	bool ide_pins;
 	bool sata_bridge;
-	struct reset_control *sata0_reset;
-	struct reset_control *sata1_reset;
 	struct clk *sata0_pclk;
 	struct clk *sata1_pclk;
 };
@@ -201,7 +195,10 @@ int gemini_sata_start_bridge(struct sata_gemini *sg, unsigned int bridge)
 		pclk = sg->sata0_pclk;
 	else
 		pclk = sg->sata1_pclk;
-	clk_enable(pclk);
+	ret = clk_enable(pclk);
+	if (ret)
+		return ret;
+
 	msleep(10);
 
 	/* Do not keep clocking a bridge that is not online */
@@ -222,18 +219,6 @@ void gemini_sata_stop_bridge(struct sata_gemini *sg, unsigned int bridge)
 }
 EXPORT_SYMBOL(gemini_sata_stop_bridge);
 
-int gemini_sata_reset_bridge(struct sata_gemini *sg,
-			     unsigned int bridge)
-{
-	if (bridge == 0)
-		reset_control_reset(sg->sata0_reset);
-	else
-		reset_control_reset(sg->sata1_reset);
-	msleep(10);
-	return gemini_sata_setup_bridge(sg, bridge);
-}
-EXPORT_SYMBOL(gemini_sata_reset_bridge);
-
 static int gemini_sata_bridge_init(struct sata_gemini *sg)
 {
 	struct device *dev = sg->dev;
@@ -253,31 +238,16 @@ static int gemini_sata_bridge_init(struct sata_gemini *sg)
 
 	ret = clk_prepare_enable(sg->sata0_pclk);
 	if (ret) {
-		pr_err("failed to enable SATA0 PCLK\n");
+		dev_err(dev, "failed to enable SATA0 PCLK\n");
 		return ret;
 	}
 	ret = clk_prepare_enable(sg->sata1_pclk);
 	if (ret) {
-		pr_err("failed to enable SATA1 PCLK\n");
+		dev_err(dev, "failed to enable SATA1 PCLK\n");
 		clk_disable_unprepare(sg->sata0_pclk);
 		return ret;
 	}
 
-	sg->sata0_reset = devm_reset_control_get_exclusive(dev, "sata0");
-	if (IS_ERR(sg->sata0_reset)) {
-		dev_err(dev, "no SATA0 reset controller\n");
-		clk_disable_unprepare(sg->sata1_pclk);
-		clk_disable_unprepare(sg->sata0_pclk);
-		return PTR_ERR(sg->sata0_reset);
-	}
-	sg->sata1_reset = devm_reset_control_get_exclusive(dev, "sata1");
-	if (IS_ERR(sg->sata1_reset)) {
-		dev_err(dev, "no SATA1 reset controller\n");
-		clk_disable_unprepare(sg->sata1_pclk);
-		clk_disable_unprepare(sg->sata0_pclk);
-		return PTR_ERR(sg->sata1_reset);
-	}
-
 	sata_id = readl(sg->base + GEMINI_SATA_ID);
 	sata_phy_id = readl(sg->base + GEMINI_SATA_PHY_ID);
 	sg->sata_bridge = true;
@@ -318,7 +288,6 @@ static int gemini_sata_probe(struct platform_device *pdev)
 	struct device_node *np = dev->of_node;
 	struct sata_gemini *sg;
 	struct regmap *map;
-	struct resource *res;
 	enum gemini_muxmode muxmode;
 	u32 gmode;
 	u32 gmask;
@@ -329,11 +298,7 @@ static int gemini_sata_probe(struct platform_device *pdev)
 		return -ENOMEM;
 	sg->dev = dev;
 
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (!res)
-		return -ENODEV;
-
-	sg->base = devm_ioremap_resource(dev, res);
+	sg->base = devm_platform_ioremap_resource(pdev, 0);
 	if (IS_ERR(sg->base))
 		return PTR_ERR(sg->base);
 
@@ -405,7 +370,7 @@ out_unprep_clk:
 	return ret;
 }
 
-static int gemini_sata_remove(struct platform_device *pdev)
+static void gemini_sata_remove(struct platform_device *pdev)
 {
 	struct sata_gemini *sg = platform_get_drvdata(pdev);
 
@@ -414,27 +379,25 @@ static int gemini_sata_remove(struct platform_device *pdev)
 		clk_unprepare(sg->sata0_pclk);
 	}
 	sg_singleton = NULL;
-
-	return 0;
 }
 
 static const struct of_device_id gemini_sata_of_match[] = {
-	{
-		.compatible = "cortina,gemini-sata-bridge",
-	},
-	{},
+	{ .compatible = "cortina,gemini-sata-bridge", },
+	{ /* sentinel */ }
 };
+MODULE_DEVICE_TABLE(of, gemini_sata_of_match);
 
 static struct platform_driver gemini_sata_driver = {
 	.driver = {
 		.name = DRV_NAME,
-		.of_match_table = of_match_ptr(gemini_sata_of_match),
+		.of_match_table = gemini_sata_of_match,
 	},
 	.probe = gemini_sata_probe,
 	.remove = gemini_sata_remove,
 };
 module_platform_driver(gemini_sata_driver);
 
+MODULE_DESCRIPTION("low level driver for Cortina Systems Gemini SATA bridge");
 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
 MODULE_LICENSE("GPL");
 MODULE_ALIAS("platform:" DRV_NAME);
diff --git a/drivers/ata/sata_gemini.h b/drivers/ata/sata_gemini.h
index 6f6e691d6007..b6e4a5c86e01 100644
--- a/drivers/ata/sata_gemini.h
+++ b/drivers/ata/sata_gemini.h
@@ -17,6 +17,5 @@ bool gemini_sata_bridge_enabled(struct sata_gemini *sg, bool is_ata1);
 enum gemini_muxmode gemini_sata_get_muxmode(struct sata_gemini *sg);
 int gemini_sata_start_bridge(struct sata_gemini *sg, unsigned int bridge);
 void gemini_sata_stop_bridge(struct sata_gemini *sg, unsigned int bridge);
-int gemini_sata_reset_bridge(struct sata_gemini *sg, unsigned int bridge);
 
 #endif
diff --git a/drivers/ata/sata_highbank.c b/drivers/ata/sata_highbank.c
index ad3893c62572..3421039f4bae 100644
--- a/drivers/ata/sata_highbank.c
+++ b/drivers/ata/sata_highbank.c
@@ -13,7 +13,7 @@
 #include <linux/io.h>
 #include <linux/spinlock.h>
 #include <linux/device.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/platform_device.h>
 #include <linux/libata.h>
@@ -348,6 +348,7 @@ static int highbank_initialize_phys(struct device *dev, void __iomem *addr)
 			phy_nodes[phy] = phy_data.np;
 			cphy_base[phy] = of_iomap(phy_nodes[phy], 0);
 			if (cphy_base[phy] == NULL) {
+				of_node_put(phy_data.np);
 				return 0;
 			}
 			phy_count += 1;
@@ -385,7 +386,7 @@ static int highbank_initialize_phys(struct device *dev, void __iomem *addr)
 static int ahci_highbank_hardreset(struct ata_link *link, unsigned int *class,
 				unsigned long deadline)
 {
-	static const unsigned long timing[] = { 5, 100, 500};
+	static const unsigned int timing[] = { 5, 100, 500};
 	struct ata_port *ap = link->ap;
 	struct ahci_port_priv *pp = ap->private_data;
 	struct ahci_host_priv *hpriv = ap->host->private_data;
@@ -400,7 +401,7 @@ static int ahci_highbank_hardreset(struct ata_link *link, unsigned int *class,
 
 	/* clear D2H reception area to properly wait for D2H FIS */
 	ata_tf_init(link->device, &tf);
-	tf.command = ATA_BUSY;
+	tf.status = ATA_BUSY;
 	ata_tf_to_fis(&tf, 0, 0, d2h_fis);
 
 	do {
@@ -427,7 +428,7 @@ static int ahci_highbank_hardreset(struct ata_link *link, unsigned int *class,
 
 static struct ata_port_operations ahci_highbank_ops = {
 	.inherits		= &ahci_ops,
-	.hardreset		= ahci_highbank_hardreset,
+	.reset.hardreset	= ahci_highbank_hardreset,
 	.transmit_led_message   = ecx_transmit_led_message,
 };
 
@@ -438,13 +439,13 @@ static const struct ata_port_info ahci_highbank_port_info = {
 	.port_ops       = &ahci_highbank_ops,
 };
 
-static struct scsi_host_template ahci_highbank_platform_sht = {
+static const struct scsi_host_template ahci_highbank_platform_sht = {
 	AHCI_SHT("sata_highbank"),
 };
 
 static const struct of_device_id ahci_of_match[] = {
 	{ .compatible = "calxeda,hb-ahci" },
-	{},
+	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, ahci_of_match);
 
@@ -469,10 +470,10 @@ static int ahci_highbank_probe(struct platform_device *pdev)
 	}
 
 	irq = platform_get_irq(pdev, 0);
-	if (irq <= 0) {
-		dev_err(dev, "no irq\n");
+	if (irq < 0)
+		return irq;
+	if (!irq)
 		return -EINVAL;
-	}
 
 	hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
 	if (!hpriv) {
@@ -571,7 +572,6 @@ static int ahci_highbank_suspend(struct device *dev)
 	struct ahci_host_priv *hpriv = host->private_data;
 	void __iomem *mmio = hpriv->mmio;
 	u32 ctl;
-	int rc;
 
 	if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
 		dev_err(dev, "firmware update required for suspend/resume\n");
@@ -588,10 +588,7 @@ static int ahci_highbank_suspend(struct device *dev)
 	writel(ctl, mmio + HOST_CTL);
 	readl(mmio + HOST_CTL); /* flush */
 
-	rc = ata_host_suspend(host, PMSG_SUSPEND);
-	if (rc)
-		return rc;
-
+	ata_host_suspend(host, PMSG_SUSPEND);
 	return 0;
 }
 
@@ -619,11 +616,11 @@ static SIMPLE_DEV_PM_OPS(ahci_highbank_pm_ops,
 
 static struct platform_driver ahci_highbank_driver = {
 	.remove = ata_platform_remove_one,
-        .driver = {
-                .name = "highbank-ahci",
-                .of_match_table = ahci_of_match,
-                .pm = &ahci_highbank_pm_ops,
-        },
+	.driver = {
+		.name = "highbank-ahci",
+		.of_match_table = ahci_of_match,
+		.pm = &ahci_highbank_pm_ops,
+	},
 	.probe = ahci_highbank_probe,
 };
 
diff --git a/drivers/ata/sata_inic162x.c b/drivers/ata/sata_inic162x.c
index e517bd8822a5..46a8c20daf18 100644
--- a/drivers/ata/sata_inic162x.c
+++ b/drivers/ata/sata_inic162x.c
@@ -242,7 +242,7 @@ struct inic_port_priv {
 	dma_addr_t	cpb_tbl_dma;
 };
 
-static struct scsi_host_template inic_sht = {
+static const struct scsi_host_template inic_sht = {
 	ATA_BASE_SHT(DRV_NAME),
 	.sg_tablesize		= LIBATA_MAX_PRD, /* maybe it can be larger? */
 
@@ -488,8 +488,6 @@ static enum ata_completion_errors inic_qc_prep(struct ata_queued_cmd *qc)
 	bool is_data = ata_is_data(qc->tf.protocol);
 	unsigned int cdb_len = 0;
 
-	VPRINTK("ENTER\n");
-
 	if (is_atapi)
 		cdb_len = qc->dev->cdb_len;
 
@@ -559,16 +557,16 @@ static void inic_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
 {
 	void __iomem *port_base = inic_port_base(ap);
 
-	tf->feature	= readb(port_base + PORT_TF_FEATURE);
+	tf->error	= readb(port_base + PORT_TF_FEATURE);
 	tf->nsect	= readb(port_base + PORT_TF_NSECT);
 	tf->lbal	= readb(port_base + PORT_TF_LBAL);
 	tf->lbam	= readb(port_base + PORT_TF_LBAM);
 	tf->lbah	= readb(port_base + PORT_TF_LBAH);
 	tf->device	= readb(port_base + PORT_TF_DEVICE);
-	tf->command	= readb(port_base + PORT_TF_COMMAND);
+	tf->status	= readb(port_base + PORT_TF_COMMAND);
 }
 
-static bool inic_qc_fill_rtf(struct ata_queued_cmd *qc)
+static void inic_qc_fill_rtf(struct ata_queued_cmd *qc)
 {
 	struct ata_taskfile *rtf = &qc->result_tf;
 	struct ata_taskfile tf;
@@ -582,12 +580,10 @@ static bool inic_qc_fill_rtf(struct ata_queued_cmd *qc)
 	 */
 	inic_tf_read(qc->ap, &tf);
 
-	if (!(tf.command & ATA_ERR))
-		return false;
-
-	rtf->command = tf.command;
-	rtf->feature = tf.feature;
-	return true;
+	if (tf.status & ATA_ERR) {
+		rtf->status = tf.status;
+		rtf->error = tf.error;
+	}
 }
 
 static void inic_freeze(struct ata_port *ap)
@@ -623,7 +619,7 @@ static int inic_hardreset(struct ata_link *link, unsigned int *class,
 	struct ata_port *ap = link->ap;
 	void __iomem *port_base = inic_port_base(ap);
 	void __iomem *idma_ctl = port_base + PORT_IDMA_CTL;
-	const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
+	const unsigned int *timing = sata_ehc_deb_timing(&link->eh_context);
 	int rc;
 
 	/* hammer it into sane state */
@@ -657,7 +653,7 @@ static int inic_hardreset(struct ata_link *link, unsigned int *class,
 		}
 
 		inic_tf_read(ap, &tf);
-		*class = ata_dev_classify(&tf);
+		*class = ata_port_classify(ap, &tf);
 	}
 
 	return 0;
@@ -674,7 +670,7 @@ static void inic_error_handler(struct ata_port *ap)
 static void inic_post_internal_cmd(struct ata_queued_cmd *qc)
 {
 	/* make DMA engine forget about the failed command */
-	if (qc->flags & ATA_QCFLAG_FAILED)
+	if (qc->flags & ATA_QCFLAG_EH)
 		inic_reset_port(inic_port_base(qc->ap));
 }
 
@@ -734,7 +730,7 @@ static struct ata_port_operations inic_port_ops = {
 
 	.freeze			= inic_freeze,
 	.thaw			= inic_thaw,
-	.hardreset		= inic_hardreset,
+	.reset.hardreset	= inic_hardreset,
 	.error_handler		= inic_error_handler,
 	.post_internal_cmd	= inic_post_internal_cmd,
 
diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c
index d7228f8e9297..ffb396f61731 100644
--- a/drivers/ata/sata_mv.c
+++ b/drivers/ata/sata_mv.c
@@ -579,7 +579,7 @@ struct mv_hw_ops {
 	void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
 	void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
 			   void __iomem *mmio);
-	int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
+	int (*reset_hc)(struct ata_host *host, void __iomem *mmio,
 			unsigned int n_hc);
 	void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
 	void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
@@ -606,7 +606,7 @@ static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
 			   void __iomem *mmio);
-static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
+static int mv5_reset_hc(struct ata_host *host, void __iomem *mmio,
 			unsigned int n_hc);
 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
@@ -616,14 +616,14 @@ static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
 			   void __iomem *mmio);
-static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
+static int mv6_reset_hc(struct ata_host *host, void __iomem *mmio,
 			unsigned int n_hc);
 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
 				      void __iomem *mmio);
 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
 				      void __iomem *mmio);
-static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
+static int mv_soc_reset_hc(struct ata_host *host,
 				  void __iomem *mmio, unsigned int n_hc);
 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
 				      void __iomem *mmio);
@@ -659,17 +659,21 @@ static u8 mv_sff_check_status(struct ata_port *ap);
  * PRDs for 64K boundaries in mv_fill_sg().
  */
 #ifdef CONFIG_PCI
-static struct scsi_host_template mv5_sht = {
+static const struct scsi_host_template mv5_sht = {
 	ATA_BASE_SHT(DRV_NAME),
 	.sg_tablesize		= MV_MAX_SG_CT / 2,
 	.dma_boundary		= MV_DMA_BOUNDARY,
 };
 #endif
-static struct scsi_host_template mv6_sht = {
-	ATA_NCQ_SHT(DRV_NAME),
+static const struct scsi_host_template mv6_sht = {
+	__ATA_BASE_SHT(DRV_NAME),
 	.can_queue		= MV_MAX_Q_DEPTH - 1,
 	.sg_tablesize		= MV_MAX_SG_CT / 2,
 	.dma_boundary		= MV_DMA_BOUNDARY,
+	.sdev_groups		= ata_ncq_sdev_groups,
+	.change_queue_depth	= ata_scsi_change_queue_depth,
+	.tag_alloc_policy_rr	= true,
+	.sdev_configure		= ata_scsi_sdev_configure
 };
 
 static struct ata_port_operations mv5_ops = {
@@ -683,7 +687,7 @@ static struct ata_port_operations mv5_ops = {
 
 	.freeze			= mv_eh_freeze,
 	.thaw			= mv_eh_thaw,
-	.hardreset		= mv_hardreset,
+	.reset.hardreset	= mv_hardreset,
 
 	.scr_read		= mv5_scr_read,
 	.scr_write		= mv5_scr_write,
@@ -705,10 +709,10 @@ static struct ata_port_operations mv6_ops = {
 
 	.freeze			= mv_eh_freeze,
 	.thaw			= mv_eh_thaw,
-	.hardreset		= mv_hardreset,
-	.softreset		= mv_softreset,
-	.pmp_hardreset		= mv_pmp_hardreset,
-	.pmp_softreset		= mv_softreset,
+	.reset.hardreset	= mv_hardreset,
+	.reset.softreset	= mv_softreset,
+	.pmp_reset.hardreset	= mv_pmp_hardreset,
+	.pmp_reset.softreset	= mv_softreset,
 	.error_handler		= mv_pmp_error_handler,
 
 	.scr_read		= mv_scr_read,
@@ -783,37 +787,6 @@ static const struct ata_port_info mv_port_info[] = {
 	},
 };
 
-static const struct pci_device_id mv_pci_tbl[] = {
-	{ PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
-	{ PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
-	{ PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
-	{ PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
-	/* RocketRAID 1720/174x have different identifiers */
-	{ PCI_VDEVICE(TTI, 0x1720), chip_6042 },
-	{ PCI_VDEVICE(TTI, 0x1740), chip_6042 },
-	{ PCI_VDEVICE(TTI, 0x1742), chip_6042 },
-
-	{ PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
-	{ PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
-	{ PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
-	{ PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
-	{ PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
-
-	{ PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
-
-	/* Adaptec 1430SA */
-	{ PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
-
-	/* Marvell 7042 support */
-	{ PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
-
-	/* Highpoint RocketRAID PCIe series */
-	{ PCI_VDEVICE(TTI, 0x2300), chip_7042 },
-	{ PCI_VDEVICE(TTI, 0x2310), chip_7042 },
-
-	{ }			/* terminate list */
-};
-
 static const struct mv_hw_ops mv5xxx_ops = {
 	.phy_errata		= mv5_phy_errata,
 	.enable_leds		= mv5_enable_leds,
@@ -1146,9 +1119,8 @@ static void mv_set_irq_coalescing(struct ata_host *host,
 	spin_unlock_irqrestore(&host->lock, flags);
 }
 
-/**
+/*
  *      mv_start_edma - Enable eDMA engine
- *      @base: port base address
  *      @pp: port private data
  *
  *      Verify the local cache of the eDMA state is accurate with a
@@ -1245,81 +1217,74 @@ static int mv_stop_edma(struct ata_port *ap)
 	return err;
 }
 
-#ifdef ATA_DEBUG
-static void mv_dump_mem(void __iomem *start, unsigned bytes)
+static void mv_dump_mem(struct device *dev, void __iomem *start, unsigned bytes)
 {
-	int b, w;
+	int b, w, o;
+	unsigned char linebuf[38];
+
 	for (b = 0; b < bytes; ) {
-		DPRINTK("%p: ", start + b);
-		for (w = 0; b < bytes && w < 4; w++) {
-			printk("%08x ", readl(start + b));
+		for (w = 0, o = 0; b < bytes && w < 4; w++) {
+			o += scnprintf(linebuf + o, sizeof(linebuf) - o,
+				       "%08x ", readl(start + b));
 			b += sizeof(u32);
 		}
-		printk("\n");
+		dev_dbg(dev, "%s: %p: %s\n",
+			__func__, start + b, linebuf);
 	}
 }
-#endif
-#if defined(ATA_DEBUG) || defined(CONFIG_PCI)
+
 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
 {
-#ifdef ATA_DEBUG
-	int b, w;
-	u32 dw;
+	int b, w, o;
+	u32 dw = 0;
+	unsigned char linebuf[38];
+
 	for (b = 0; b < bytes; ) {
-		DPRINTK("%02x: ", b);
-		for (w = 0; b < bytes && w < 4; w++) {
+		for (w = 0, o = 0; b < bytes && w < 4; w++) {
 			(void) pci_read_config_dword(pdev, b, &dw);
-			printk("%08x ", dw);
+			o += snprintf(linebuf + o, sizeof(linebuf) - o,
+				      "%08x ", dw);
 			b += sizeof(u32);
 		}
-		printk("\n");
+		dev_dbg(&pdev->dev, "%s: %02x: %s\n",
+			__func__, b, linebuf);
 	}
-#endif
 }
-#endif
-static void mv_dump_all_regs(void __iomem *mmio_base, int port,
+
+static void mv_dump_all_regs(void __iomem *mmio_base,
 			     struct pci_dev *pdev)
 {
-#ifdef ATA_DEBUG
-	void __iomem *hc_base = mv_hc_base(mmio_base,
-					   port >> MV_PORT_HC_SHIFT);
+	void __iomem *hc_base;
 	void __iomem *port_base;
 	int start_port, num_ports, p, start_hc, num_hcs, hc;
 
-	if (0 > port) {
-		start_hc = start_port = 0;
-		num_ports = 8;		/* shld be benign for 4 port devs */
-		num_hcs = 2;
-	} else {
-		start_hc = port >> MV_PORT_HC_SHIFT;
-		start_port = port;
-		num_ports = num_hcs = 1;
-	}
-	DPRINTK("All registers for port(s) %u-%u:\n", start_port,
-		num_ports > 1 ? num_ports - 1 : start_port);
+	start_hc = start_port = 0;
+	num_ports = 8;		/* should be benign for 4 port devs */
+	num_hcs = 2;
+	dev_dbg(&pdev->dev,
+		"%s: All registers for port(s) %u-%u:\n", __func__,
+		start_port, num_ports > 1 ? num_ports - 1 : start_port);
 
-	if (NULL != pdev) {
-		DPRINTK("PCI config space regs:\n");
-		mv_dump_pci_cfg(pdev, 0x68);
-	}
-	DPRINTK("PCI regs:\n");
-	mv_dump_mem(mmio_base+0xc00, 0x3c);
-	mv_dump_mem(mmio_base+0xd00, 0x34);
-	mv_dump_mem(mmio_base+0xf00, 0x4);
-	mv_dump_mem(mmio_base+0x1d00, 0x6c);
+	dev_dbg(&pdev->dev, "%s: PCI config space regs:\n", __func__);
+	mv_dump_pci_cfg(pdev, 0x68);
+
+	dev_dbg(&pdev->dev, "%s: PCI regs:\n", __func__);
+	mv_dump_mem(&pdev->dev, mmio_base+0xc00, 0x3c);
+	mv_dump_mem(&pdev->dev, mmio_base+0xd00, 0x34);
+	mv_dump_mem(&pdev->dev, mmio_base+0xf00, 0x4);
+	mv_dump_mem(&pdev->dev, mmio_base+0x1d00, 0x6c);
 	for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
 		hc_base = mv_hc_base(mmio_base, hc);
-		DPRINTK("HC regs (HC %i):\n", hc);
-		mv_dump_mem(hc_base, 0x1c);
+		dev_dbg(&pdev->dev, "%s: HC regs (HC %i):\n", __func__, hc);
+		mv_dump_mem(&pdev->dev, hc_base, 0x1c);
 	}
 	for (p = start_port; p < start_port + num_ports; p++) {
 		port_base = mv_port_base(mmio_base, p);
-		DPRINTK("EDMA regs (port %i):\n", p);
-		mv_dump_mem(port_base, 0x54);
-		DPRINTK("SATA regs (port %i):\n", p);
-		mv_dump_mem(port_base+0x300, 0x60);
+		dev_dbg(&pdev->dev, "%s: EDMA regs (port %i):\n", __func__, p);
+		mv_dump_mem(&pdev->dev, port_base, 0x54);
+		dev_dbg(&pdev->dev, "%s: SATA regs (port %i):\n", __func__, p);
+		mv_dump_mem(&pdev->dev, port_base+0x300, 0x60);
 	}
-#endif
 }
 
 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
@@ -1519,7 +1484,7 @@ static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
 		writel(new, hpriv->base + GPIO_PORT_CTL);
 }
 
-/**
+/*
  *	mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma
  *	@ap: Port being initialized
  *
@@ -1918,8 +1883,8 @@ static void mv_bmdma_start(struct ata_queued_cmd *qc)
 }
 
 /**
- *	mv_bmdma_stop - Stop BMDMA transfer
- *	@qc: queued command to stop DMA on.
+ *	mv_bmdma_stop_ap - Stop BMDMA transfer
+ *	@ap: port to stop
  *
  *	Clears the ATA_DMA_START flag in the bmdma control register
  *
@@ -2010,7 +1975,7 @@ static void mv_rw_multi_errata_sata24(struct ata_queued_cmd *qc)
 				break;
 			case ATA_CMD_WRITE_MULTI_FUA_EXT:
 				tf->flags &= ~ATA_TFLAG_FUA; /* ugh */
-				/* fall through */
+				fallthrough;
 			case ATA_CMD_WRITE_MULTI_EXT:
 				tf->command = ATA_CMD_PIO_WRITE_EXT;
 				break;
@@ -2044,7 +2009,7 @@ static enum ata_completion_errors mv_qc_prep(struct ata_queued_cmd *qc)
 	case ATA_PROT_DMA:
 		if (tf->command == ATA_CMD_DSM)
 			return AC_ERR_OK;
-		/* fall-thru */
+		fallthrough;
 	case ATA_PROT_NCQ:
 		break;	/* continue below */
 	case ATA_PROT_PIO:
@@ -2221,6 +2186,7 @@ static u8 mv_sff_check_status(struct ata_port *ap)
 
 /**
  *	mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register
+ *	@ap: ATA port to send a FIS
  *	@fis: fis to be sent
  *	@nwords: number of 32-bit words in the fis
  */
@@ -2296,7 +2262,7 @@ static unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc)
 	switch (qc->tf.protocol) {
 	case ATAPI_PROT_PIO:
 		pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
-		/* fall through */
+		fallthrough;
 	case ATAPI_PROT_NODATA:
 		ap->hsm_task_state = HSM_ST_FIRST;
 		break;
@@ -2347,7 +2313,7 @@ static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
 				return AC_ERR_OTHER;
 			break;  /* use bmdma for this */
 		}
-		/* fall thru */
+		fallthrough;
 	case ATA_PROT_NCQ:
 		mv_start_edma(ap, port_mmio, pp, qc->tf.protocol);
 		pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
@@ -2376,7 +2342,7 @@ static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
 				      ": attempting PIO w/multiple DRQ: "
 				      "this may fail due to h/w errata\n");
 		}
-		/* fall through */
+		fallthrough;
 	case ATA_PROT_NODATA:
 	case ATAPI_PROT_PIO:
 	case ATAPI_PROT_NODATA:
@@ -2958,8 +2924,8 @@ static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
 
 	dev_err(host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", err_cause);
 
-	DPRINTK("All regs @ PCI error\n");
-	mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
+	dev_dbg(host->dev, "%s: All regs @ PCI error\n", __func__);
+	mv_dump_all_regs(mmio, to_pci_dev(host->dev));
 
 	writelfl(0, mmio + hpriv->irq_cause_offset);
 
@@ -3197,9 +3163,10 @@ static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
 }
 #undef ZERO
 
-static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
+static int mv5_reset_hc(struct ata_host *host, void __iomem *mmio,
 			unsigned int n_hc)
 {
+	struct mv_host_priv *hpriv = host->private_data;
 	unsigned int hc, port;
 
 	for (hc = 0; hc < n_hc; hc++) {
@@ -3249,7 +3216,7 @@ static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
 	writel(tmp, mmio + GPIO_PORT_CTL);
 }
 
-/**
+/*
  *      mv6_reset_hc - Perform the 6xxx global soft reset
  *      @mmio: base address of the HBA
  *
@@ -3258,7 +3225,7 @@ static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
  *      LOCKING:
  *      Inherited from caller.
  */
-static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
+static int mv6_reset_hc(struct ata_host *host, void __iomem *mmio,
 			unsigned int n_hc)
 {
 	void __iomem *reg = mmio + PCI_MAIN_CMD_STS;
@@ -3278,7 +3245,7 @@ static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
 			break;
 	}
 	if (!(PCI_MASTER_EMPTY & t)) {
-		printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
+		dev_err(host->dev, "PCI master won't flush\n");
 		rc = 1;
 		goto done;
 	}
@@ -3292,7 +3259,7 @@ static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
 	} while (!(GLOB_SFT_RST & t) && (i-- > 0));
 
 	if (!(GLOB_SFT_RST & t)) {
-		printk(KERN_ERR DRV_NAME ": can't set global reset\n");
+		dev_err(host->dev, "can't set global reset\n");
 		rc = 1;
 		goto done;
 	}
@@ -3306,7 +3273,7 @@ static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
 	} while ((GLOB_SFT_RST & t) && (i-- > 0));
 
 	if (GLOB_SFT_RST & t) {
-		printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
+		dev_err(host->dev, "can't clear global reset\n");
 		rc = 1;
 	}
 done:
@@ -3475,9 +3442,10 @@ static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
 
 #undef ZERO
 
-static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
+static int mv_soc_reset_hc(struct ata_host *host,
 				  void __iomem *mmio, unsigned int n_hc)
 {
+	struct mv_host_priv *hpriv = host->private_data;
 	unsigned int port;
 
 	for (port = 0; port < hpriv->n_ports; port++)
@@ -3530,7 +3498,7 @@ static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
 	writel(reg, port_mmio + PHY_MODE9_GEN1);
 }
 
-/**
+/*
  *	soc_is_65 - check if the soc is 65 nano device
  *
  *	Detect the type of the SoC, this is done by reading the PHYCFG_OFS
@@ -3634,7 +3602,7 @@ static int mv_hardreset(struct ata_link *link, unsigned int *class,
 
 	/* Workaround for errata FEr SATA#10 (part 2) */
 	do {
-		const unsigned long *timing =
+		const unsigned int *timing =
 				sata_ehc_deb_timing(&link->eh_context);
 
 		rc = sata_link_hardreset(link, timing, deadline + extra,
@@ -3719,11 +3687,6 @@ static void mv_port_init(struct ata_ioports *port,  void __iomem *port_mmio)
 
 	/* unmask all non-transient EDMA error interrupts */
 	writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK);
-
-	VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
-		readl(port_mmio + EDMA_CFG),
-		readl(port_mmio + EDMA_ERR_IRQ_CAUSE),
-		readl(port_mmio + EDMA_ERR_IRQ_MASK));
 }
 
 static unsigned int mv_in_pcix_mode(struct ata_host *host)
@@ -3855,16 +3818,16 @@ static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
 			 *
 			 * Warn the user, lest they think we're just buggy.
 			 */
-			printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
+			dev_warn(&pdev->dev, "Highpoint RocketRAID"
 				" BIOS CORRUPTS DATA on all attached drives,"
 				" regardless of if/how they are configured."
 				" BEWARE!\n");
-			printk(KERN_WARNING DRV_NAME ": For data safety, do not"
+			dev_warn(&pdev->dev, "For data safety, do not"
 				" use sectors 8-9 on \"Legacy\" drives,"
 				" and avoid the final two gigabytes on"
 				" all RocketRAID BIOS initialized drives.\n");
 		}
-		/* fall through */
+		fallthrough;
 	case chip_6042:
 		hpriv->ops = &mv6xxx_ops;
 		hp_flags |= MV_HP_GEN_IIE;
@@ -3892,8 +3855,8 @@ static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
 		break;
 
 	default:
-		dev_err(host->dev, "BUG: invalid board index %u\n", board_idx);
-		return 1;
+		dev_alert(host->dev, "BUG: invalid board index %u\n", board_idx);
+		return -EINVAL;
 	}
 
 	hpriv->hp_flags = hp_flags;
@@ -3950,7 +3913,7 @@ static int mv_init_host(struct ata_host *host)
 		if (hpriv->ops->read_preamp)
 			hpriv->ops->read_preamp(hpriv, port, mmio);
 
-	rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
+	rc = hpriv->ops->reset_hc(host, mmio, n_hc);
 	if (rc)
 		goto done;
 
@@ -3968,7 +3931,7 @@ static int mv_init_host(struct ata_host *host)
 	for (hc = 0; hc < n_hc; hc++) {
 		void __iomem *hc_mmio = mv_hc_base(mmio, hc);
 
-		VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
+		dev_dbg(host->dev, "HC%i: HC config=0x%08x HC IRQ cause "
 			"(before clear)=0x%08x\n", hc,
 			readl(hc_mmio + HC_CFG),
 			readl(hc_mmio + HC_IRQ_CAUSE));
@@ -4063,7 +4026,7 @@ static int mv_platform_probe(struct platform_device *pdev)
 	/*
 	 * Simple resource validation ..
 	 */
-	if (unlikely(pdev->num_resources != 2)) {
+	if (unlikely(pdev->num_resources != 1)) {
 		dev_err(&pdev->dev, "invalid number of resources\n");
 		return -EINVAL;
 	}
@@ -4097,6 +4060,10 @@ static int mv_platform_probe(struct platform_device *pdev)
 		n_ports = mv_platform_data->n_ports;
 		irq = platform_get_irq(pdev, 0);
 	}
+	if (irq < 0)
+		return irq;
+	if (!irq)
+		return -EINVAL;
 
 	host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
 	hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
@@ -4125,10 +4092,13 @@ static int mv_platform_probe(struct platform_device *pdev)
 	hpriv->base -= SATAHC0_REG_BASE;
 
 	hpriv->clk = clk_get(&pdev->dev, NULL);
-	if (IS_ERR(hpriv->clk))
+	if (IS_ERR(hpriv->clk)) {
 		dev_notice(&pdev->dev, "cannot get optional clkdev\n");
-	else
-		clk_prepare_enable(hpriv->clk);
+	} else {
+		rc = clk_prepare_enable(hpriv->clk);
+		if (rc)
+			goto err;
+	}
 
 	for (port = 0; port < n_ports; port++) {
 		char port_number[16];
@@ -4212,7 +4182,7 @@ err:
  *      A platform bus SATA device has been unplugged. Perform the needed
  *      cleanup. Also called on module unload for any active devices.
  */
-static int mv_platform_remove(struct platform_device *pdev)
+static void mv_platform_remove(struct platform_device *pdev)
 {
 	struct ata_host *host = platform_get_drvdata(pdev);
 	struct mv_host_priv *hpriv = host->private_data;
@@ -4230,17 +4200,16 @@ static int mv_platform_remove(struct platform_device *pdev)
 		}
 		phy_power_off(hpriv->port_phys[port]);
 	}
-	return 0;
 }
 
 #ifdef CONFIG_PM_SLEEP
 static int mv_platform_suspend(struct platform_device *pdev, pm_message_t state)
 {
 	struct ata_host *host = platform_get_drvdata(pdev);
+
 	if (host)
-		return ata_host_suspend(host, state);
-	else
-		return 0;
+		ata_host_suspend(host, state);
+	return 0;
 }
 
 static int mv_platform_resume(struct platform_device *pdev)
@@ -4262,7 +4231,7 @@ static int mv_platform_resume(struct platform_device *pdev)
 		/* initialize adapter */
 		ret = mv_init_host(host);
 		if (ret) {
-			printk(KERN_ERR DRV_NAME ": Error during HW init\n");
+			dev_err(&pdev->dev, "Error during HW init\n");
 			return ret;
 		}
 		ata_host_resume(host);
@@ -4279,7 +4248,7 @@ static int mv_platform_resume(struct platform_device *pdev)
 static const struct of_device_id mv_sata_dt_ids[] = {
 	{ .compatible = "marvell,armada-370-sata", },
 	{ .compatible = "marvell,orion-sata", },
-	{},
+	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, mv_sata_dt_ids);
 #endif
@@ -4303,6 +4272,36 @@ static int mv_pci_init_one(struct pci_dev *pdev,
 static int mv_pci_device_resume(struct pci_dev *pdev);
 #endif
 
+static const struct pci_device_id mv_pci_tbl[] = {
+	{ PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
+	{ PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
+	{ PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
+	{ PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
+	/* RocketRAID 1720/174x have different identifiers */
+	{ PCI_VDEVICE(TTI, 0x1720), chip_6042 },
+	{ PCI_VDEVICE(TTI, 0x1740), chip_6042 },
+	{ PCI_VDEVICE(TTI, 0x1742), chip_6042 },
+
+	{ PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
+	{ PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
+	{ PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
+	{ PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
+	{ PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
+
+	{ PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
+
+	/* Adaptec 1430SA */
+	{ PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
+
+	/* Marvell 7042 support */
+	{ PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
+
+	/* Highpoint RocketRAID PCIe series */
+	{ PCI_VDEVICE(TTI, 0x2300), chip_7042 },
+	{ PCI_VDEVICE(TTI, 0x2310), chip_7042 },
+
+	{ }			/* terminate list */
+};
 
 static struct pci_driver mv_pci_driver = {
 	.name			= DRV_NAME,
@@ -4315,6 +4314,7 @@ static struct pci_driver mv_pci_driver = {
 #endif
 
 };
+MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
 
 /**
  *      mv_print_info - Dump key info to kernel log for perusal.
@@ -4487,7 +4487,6 @@ static void __exit mv_exit(void)
 MODULE_AUTHOR("Brett Russ");
 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
 MODULE_LICENSE("GPL v2");
-MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
 MODULE_VERSION(DRV_VERSION);
 MODULE_ALIAS("platform:" DRV_NAME);
 
diff --git a/drivers/ata/sata_nv.c b/drivers/ata/sata_nv.c
index eb9dc14e5147..841e7de2bba6 100644
--- a/drivers/ata/sata_nv.c
+++ b/drivers/ata/sata_nv.c
@@ -31,6 +31,7 @@
 #include <scsi/scsi_host.h>
 #include <scsi/scsi_device.h>
 #include <linux/libata.h>
+#include <trace/events/libata.h>
 
 #define DRV_NAME			"sata_nv"
 #define DRV_VERSION			"3.5"
@@ -295,7 +296,8 @@ static void nv_nf2_freeze(struct ata_port *ap);
 static void nv_nf2_thaw(struct ata_port *ap);
 static void nv_ck804_freeze(struct ata_port *ap);
 static void nv_ck804_thaw(struct ata_port *ap);
-static int nv_adma_slave_config(struct scsi_device *sdev);
+static int nv_adma_sdev_configure(struct scsi_device *sdev,
+				  struct queue_limits *lim);
 static int nv_adma_check_atapi_dma(struct ata_queued_cmd *qc);
 static enum ata_completion_errors nv_adma_qc_prep(struct ata_queued_cmd *qc);
 static unsigned int nv_adma_qc_issue(struct ata_queued_cmd *qc);
@@ -317,7 +319,8 @@ static void nv_adma_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
 static void nv_mcp55_thaw(struct ata_port *ap);
 static void nv_mcp55_freeze(struct ata_port *ap);
 static void nv_swncq_error_handler(struct ata_port *ap);
-static int nv_swncq_slave_config(struct scsi_device *sdev);
+static int nv_swncq_sdev_configure(struct scsi_device *sdev,
+				   struct queue_limits *lim);
 static int nv_swncq_port_start(struct ata_port *ap);
 static enum ata_completion_errors nv_swncq_qc_prep(struct ata_queued_cmd *qc);
 static void nv_swncq_fill_sg(struct ata_queued_cmd *qc);
@@ -370,24 +373,30 @@ static struct pci_driver nv_pci_driver = {
 	.remove			= ata_pci_remove_one,
 };
 
-static struct scsi_host_template nv_sht = {
+static const struct scsi_host_template nv_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
-static struct scsi_host_template nv_adma_sht = {
-	ATA_NCQ_SHT(DRV_NAME),
+static const struct scsi_host_template nv_adma_sht = {
+	__ATA_BASE_SHT(DRV_NAME),
 	.can_queue		= NV_ADMA_MAX_CPBS,
 	.sg_tablesize		= NV_ADMA_SGTBL_TOTAL_LEN,
 	.dma_boundary		= NV_ADMA_DMA_BOUNDARY,
-	.slave_configure	= nv_adma_slave_config,
+	.sdev_configure		= nv_adma_sdev_configure,
+	.sdev_groups		= ata_ncq_sdev_groups,
+	.change_queue_depth     = ata_scsi_change_queue_depth,
+	.tag_alloc_policy_rr	= true,
 };
 
-static struct scsi_host_template nv_swncq_sht = {
-	ATA_NCQ_SHT(DRV_NAME),
+static const struct scsi_host_template nv_swncq_sht = {
+	__ATA_BASE_SHT(DRV_NAME),
 	.can_queue		= ATA_MAX_QUEUE - 1,
 	.sg_tablesize		= LIBATA_MAX_PRD,
 	.dma_boundary		= ATA_DMA_BOUNDARY,
-	.slave_configure	= nv_swncq_slave_config,
+	.sdev_configure		= nv_swncq_sdev_configure,
+	.sdev_groups		= ata_ncq_sdev_groups,
+	.change_queue_depth     = ata_scsi_change_queue_depth,
+	.tag_alloc_policy_rr	= true,
 };
 
 /*
@@ -453,7 +462,7 @@ static struct ata_port_operations nv_generic_ops = {
 	.lost_interrupt		= ATA_OP_NULL,
 	.scr_read		= nv_scr_read,
 	.scr_write		= nv_scr_write,
-	.hardreset		= nv_hardreset,
+	.reset.hardreset	= nv_hardreset,
 };
 
 static struct ata_port_operations nv_nf2_ops = {
@@ -513,7 +522,7 @@ static struct ata_port_operations nv_swncq_ops = {
 
 struct nv_pi_priv {
 	irq_handler_t			irq_handler;
-	struct scsi_host_template	*sht;
+	const struct scsi_host_template	*sht;
 };
 
 #define NV_PI_PRIV(_irq_handler, _sht) \
@@ -654,7 +663,8 @@ static void nv_adma_mode(struct ata_port *ap)
 	pp->flags &= ~NV_ADMA_PORT_REGISTER_MODE;
 }
 
-static int nv_adma_slave_config(struct scsi_device *sdev)
+static int nv_adma_sdev_configure(struct scsi_device *sdev,
+				  struct queue_limits *lim)
 {
 	struct ata_port *ap = ata_shost_to_port(sdev->host);
 	struct nv_adma_port_priv *pp = ap->private_data;
@@ -666,7 +676,7 @@ static int nv_adma_slave_config(struct scsi_device *sdev)
 	int adma_enable;
 	u32 current_reg, new_reg, config_mask;
 
-	rc = ata_scsi_slave_config(sdev);
+	rc = ata_scsi_sdev_configure(sdev, lim);
 
 	if (sdev->id >= ATA_MAX_DEVICES || sdev->channel || sdev->lun)
 		/* Not a proper libata device, ignore */
@@ -733,8 +743,8 @@ static int nv_adma_slave_config(struct scsi_device *sdev)
 		rc = dma_set_mask(&pdev->dev, pp->adma_dma_mask);
 	}
 
-	blk_queue_segment_boundary(sdev->request_queue, segment_boundary);
-	blk_queue_max_segments(sdev->request_queue, sg_tablesize);
+	lim->seg_boundary_mask = segment_boundary;
+	lim->max_segments = sg_tablesize;
 	ata_port_info(ap,
 		      "DMA mask 0x%llX, segment boundary 0x%lX, hw segs %hu\n",
 		      (unsigned long long)*ap->host->dev->dma_mask,
@@ -802,7 +812,7 @@ static int nv_adma_check_cpb(struct ata_port *ap, int cpb_num, int force_err)
 	struct nv_adma_port_priv *pp = ap->private_data;
 	u8 flags = pp->cpb[cpb_num].resp_flags;
 
-	VPRINTK("CPB %d, flags=0x%x\n", cpb_num, flags);
+	ata_port_dbg(ap, "CPB %d, flags=0x%x\n", cpb_num, flags);
 
 	if (unlikely((force_err ||
 		     flags & (NV_CPB_RESP_ATA_ERR |
@@ -1094,8 +1104,6 @@ static int nv_adma_port_start(struct ata_port *ap)
 	struct pci_dev *pdev = to_pci_dev(dev);
 	u16 tmp;
 
-	VPRINTK("ENTER\n");
-
 	/*
 	 * Ensure DMA mask is set to 32-bit before allocating legacy PRD and
 	 * pad buffers.
@@ -1184,7 +1192,6 @@ static void nv_adma_port_stop(struct ata_port *ap)
 	struct nv_adma_port_priv *pp = ap->private_data;
 	void __iomem *mmio = pp->ctl_block;
 
-	VPRINTK("ENTER\n");
 	writew(0, mmio + NV_ADMA_CTL);
 }
 
@@ -1246,8 +1253,6 @@ static void nv_adma_setup_port(struct ata_port *ap)
 	void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR];
 	struct ata_ioports *ioport = &ap->ioaddr;
 
-	VPRINTK("ENTER\n");
-
 	mmio += NV_ADMA_PORT + ap->port_no * NV_ADMA_PORT_SIZE;
 
 	ioport->cmd_addr	= mmio;
@@ -1271,8 +1276,6 @@ static int nv_adma_host_init(struct ata_host *host)
 	unsigned int i;
 	u32 tmp32;
 
-	VPRINTK("ENTER\n");
-
 	/* enable ADMA on the ports */
 	pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32);
 	tmp32 |= NV_MCP_SATA_CFG_20_PORT0_EN |
@@ -1314,8 +1317,6 @@ static void nv_adma_fill_sg(struct ata_queued_cmd *qc, struct nv_adma_cpb *cpb)
 	struct scatterlist *sg;
 	unsigned int si;
 
-	VPRINTK("ENTER\n");
-
 	for_each_sg(qc->sg, sg, qc->n_elem, si) {
 		aprd = (si < 5) ? &cpb->aprd[si] :
 			&pp->aprd[NV_ADMA_SGTBL_LEN * qc->hw_tag + (si-5)];
@@ -1372,8 +1373,6 @@ static enum ata_completion_errors nv_adma_qc_prep(struct ata_queued_cmd *qc)
 	if (qc->tf.protocol == ATA_PROT_NCQ)
 		ctl_flags |= NV_CPB_CTL_QUEUE | NV_CPB_CTL_FPDMA;
 
-	VPRINTK("qc->flags = 0x%lx\n", qc->flags);
-
 	nv_adma_tf_to_cpb(&qc->tf, cpb->tf);
 
 	if (qc->flags & ATA_QCFLAG_DMAMAP) {
@@ -1398,8 +1397,6 @@ static unsigned int nv_adma_qc_issue(struct ata_queued_cmd *qc)
 	void __iomem *mmio = pp->ctl_block;
 	int curr_ncq = (qc->tf.protocol == ATA_PROT_NCQ);
 
-	VPRINTK("ENTER\n");
-
 	/* We can't handle result taskfile with NCQ commands, since
 	   retrieving the taskfile switches us out of ADMA mode and would abort
 	   existing commands. */
@@ -1411,7 +1408,6 @@ static unsigned int nv_adma_qc_issue(struct ata_queued_cmd *qc)
 
 	if (nv_adma_use_reg_mode(qc)) {
 		/* use ATA register mode */
-		VPRINTK("using ATA register mode: 0x%lx\n", qc->flags);
 		BUG_ON(!(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) &&
 			(qc->flags & ATA_QCFLAG_DMAMAP));
 		nv_adma_register_mode(qc->ap);
@@ -1432,8 +1428,6 @@ static unsigned int nv_adma_qc_issue(struct ata_queued_cmd *qc)
 
 	writew(qc->hw_tag, mmio + NV_ADMA_APPEND);
 
-	DPRINTK("Issued tag %u\n", qc->hw_tag);
-
 	return 0;
 }
 
@@ -1538,7 +1532,7 @@ static int nv_hardreset(struct ata_link *link, unsigned int *class,
 		sata_link_hardreset(link, sata_deb_timing_hotplug, deadline,
 				    NULL, NULL);
 	else {
-		const unsigned long *timing = sata_ehc_deb_timing(ehc);
+		const unsigned int *timing = sata_ehc_deb_timing(ehc);
 		int rc;
 
 		if (!(ehc->i.flags & ATA_EHI_QUIET))
@@ -1865,19 +1859,20 @@ static void nv_swncq_host_init(struct ata_host *host)
 
 	/* enable swncq */
 	tmp = readl(mmio + NV_CTL_MCP55);
-	VPRINTK("HOST_CTL:0x%X\n", tmp);
+	dev_dbg(&pdev->dev, "HOST_CTL:0x%X\n", tmp);
 	writel(tmp | NV_CTL_PRI_SWNCQ | NV_CTL_SEC_SWNCQ, mmio + NV_CTL_MCP55);
 
 	/* enable irq intr */
 	tmp = readl(mmio + NV_INT_ENABLE_MCP55);
-	VPRINTK("HOST_ENABLE:0x%X\n", tmp);
+	dev_dbg(&pdev->dev, "HOST_ENABLE:0x%X\n", tmp);
 	writel(tmp | 0x00fd00fd, mmio + NV_INT_ENABLE_MCP55);
 
 	/*  clear port irq */
 	writel(~0x0, mmio + NV_INT_STATUS_MCP55);
 }
 
-static int nv_swncq_slave_config(struct scsi_device *sdev)
+static int nv_swncq_sdev_configure(struct scsi_device *sdev,
+				   struct queue_limits *lim)
 {
 	struct ata_port *ap = ata_shost_to_port(sdev->host);
 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
@@ -1887,7 +1882,7 @@ static int nv_swncq_slave_config(struct scsi_device *sdev)
 	u8 check_maxtor = 0;
 	unsigned char model_num[ATA_ID_PROD_LEN + 1];
 
-	rc = ata_scsi_slave_config(sdev);
+	rc = ata_scsi_sdev_configure(sdev, lim);
 	if (sdev->id >= ATA_MAX_DEVICES || sdev->channel || sdev->lun)
 		/* Not a proper libata device, ignore */
 		return rc;
@@ -2011,19 +2006,17 @@ static unsigned int nv_swncq_issue_atacmd(struct ata_port *ap,
 	if (qc == NULL)
 		return 0;
 
-	DPRINTK("Enter\n");
-
 	writel((1 << qc->hw_tag), pp->sactive_block);
 	pp->last_issue_tag = qc->hw_tag;
 	pp->dhfis_bits &= ~(1 << qc->hw_tag);
 	pp->dmafis_bits &= ~(1 << qc->hw_tag);
 	pp->qc_active |= (0x1 << qc->hw_tag);
 
+	trace_ata_tf_load(ap, &qc->tf);
 	ap->ops->sff_tf_load(ap, &qc->tf);	 /* load tf registers */
+	trace_ata_exec_command(ap, &qc->tf, qc->hw_tag);
 	ap->ops->sff_exec_command(ap, &qc->tf);
 
-	DPRINTK("Issued tag %u\n", qc->hw_tag);
-
 	return 0;
 }
 
@@ -2035,8 +2028,6 @@ static unsigned int nv_swncq_qc_issue(struct ata_queued_cmd *qc)
 	if (qc->tf.protocol != ATA_PROT_NCQ)
 		return ata_bmdma_qc_issue(qc);
 
-	DPRINTK("Enter\n");
-
 	if (!pp->qc_active)
 		nv_swncq_issue_atacmd(ap, qc);
 	else
@@ -2081,6 +2072,7 @@ static int nv_swncq_sdbfis(struct ata_port *ap)
 	u8 lack_dhfis = 0;
 
 	host_stat = ap->ops->bmdma_status(ap);
+	trace_ata_bmdma_status(ap, host_stat);
 	if (unlikely(host_stat & ATA_DMA_ERR)) {
 		/* error when transferring data to/from memory */
 		ata_ehi_clear_desc(ehi);
@@ -2100,10 +2092,10 @@ static int nv_swncq_sdbfis(struct ata_port *ap)
 	pp->dhfis_bits &= ~done_mask;
 	pp->dmafis_bits &= ~done_mask;
 	pp->sdbfis_bits |= done_mask;
-	ata_qc_complete_multiple(ap, ap->qc_active ^ done_mask);
+	ata_qc_complete_multiple(ap, ata_qc_get_active(ap) ^ done_mask);
 
 	if (!ap->qc_active) {
-		DPRINTK("over\n");
+		ata_port_dbg(ap, "over\n");
 		nv_swncq_pp_reinit(ap);
 		return 0;
 	}
@@ -2118,12 +2110,12 @@ static int nv_swncq_sdbfis(struct ata_port *ap)
 		 */
 		lack_dhfis = 1;
 
-	DPRINTK("id 0x%x QC: qc_active 0x%x,"
-		"SWNCQ:qc_active 0x%X defer_bits %X "
-		"dhfis 0x%X dmafis 0x%X last_issue_tag %x\n",
-		ap->print_id, ap->qc_active, pp->qc_active,
-		pp->defer_queue.defer_bits, pp->dhfis_bits,
-		pp->dmafis_bits, pp->last_issue_tag);
+	ata_port_dbg(ap, "QC: qc_active 0x%llx,"
+		     "SWNCQ:qc_active 0x%X defer_bits %X "
+		     "dhfis 0x%X dmafis 0x%X last_issue_tag %x\n",
+		     ap->qc_active, pp->qc_active,
+		     pp->defer_queue.defer_bits, pp->dhfis_bits,
+		     pp->dmafis_bits, pp->last_issue_tag);
 
 	nv_swncq_fis_reinit(ap);
 
@@ -2163,7 +2155,7 @@ static void nv_swncq_dmafis(struct ata_port *ap)
 	__ata_bmdma_stop(ap);
 	tag = nv_swncq_tag(ap);
 
-	DPRINTK("dma setup tag 0x%x\n", tag);
+	ata_port_dbg(ap, "dma setup tag 0x%x\n", tag);
 	qc = ata_qc_from_tag(ap, tag);
 
 	if (unlikely(!qc))
@@ -2197,7 +2189,7 @@ static void nv_swncq_host_interrupt(struct ata_port *ap, u16 fis)
 	if (!fis)
 		return;
 
-	if (ap->pflags & ATA_PFLAG_FROZEN)
+	if (ata_port_is_frozen(ap))
 		return;
 
 	if (fis & NV_SWNCQ_IRQ_HOTPLUG) {
@@ -2231,9 +2223,9 @@ static void nv_swncq_host_interrupt(struct ata_port *ap, u16 fis)
 
 	if (fis & NV_SWNCQ_IRQ_SDBFIS) {
 		pp->ncq_flags |= ncq_saw_sdb;
-		DPRINTK("id 0x%x SWNCQ: qc_active 0x%X "
+		ata_port_dbg(ap, "SWNCQ: qc_active 0x%X "
 			"dhfis 0x%X dmafis 0x%X sactive 0x%X\n",
-			ap->print_id, pp->qc_active, pp->dhfis_bits,
+			pp->qc_active, pp->dhfis_bits,
 			pp->dmafis_bits, readl(pp->sactive_block));
 		if (nv_swncq_sdbfis(ap) < 0)
 			goto irq_error;
@@ -2259,7 +2251,7 @@ static void nv_swncq_host_interrupt(struct ata_port *ap, u16 fis)
 				goto irq_exit;
 
 			if (pp->defer_queue.defer_bits) {
-				DPRINTK("send next command\n");
+				ata_port_dbg(ap, "send next command\n");
 				qc = nv_swncq_qc_from_dq(ap);
 				nv_swncq_issue_atacmd(ap, qc);
 			}
diff --git a/drivers/ata/sata_promise.c b/drivers/ata/sata_promise.c
index 8729f78cef5f..2a005aede123 100644
--- a/drivers/ata/sata_promise.c
+++ b/drivers/ata/sata_promise.c
@@ -158,7 +158,7 @@ static void pdc_error_handler(struct ata_port *ap);
 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
 static int pdc_pata_cable_detect(struct ata_port *ap);
 
-static struct scsi_host_template pdc_ata_sht = {
+static const struct scsi_host_template pdc_ata_sht = {
 	ATA_BASE_SHT(DRV_NAME),
 	.sg_tablesize		= PDC_MAX_PRD,
 	.dma_boundary		= ATA_DMA_BOUNDARY,
@@ -188,7 +188,7 @@ static struct ata_port_operations pdc_sata_ops = {
 	.scr_read		= pdc_sata_scr_read,
 	.scr_write		= pdc_sata_scr_write,
 	.port_start		= pdc_sata_port_start,
-	.hardreset		= pdc_sata_hardreset,
+	.reset.hardreset	= pdc_sata_hardreset,
 };
 
 /* First-generation chips need a more restrictive ->check_atapi_dma op,
@@ -206,7 +206,7 @@ static struct ata_port_operations pdc_pata_ops = {
 	.freeze			= pdc_freeze,
 	.thaw			= pdc_thaw,
 	.port_start		= pdc_common_port_start,
-	.softreset		= pdc_pata_softreset,
+	.reset.softreset	= pdc_pata_softreset,
 };
 
 static const struct ata_port_info pdc_port_info[] = {
@@ -596,7 +596,8 @@ static void pdc_fill_sg(struct ata_queued_cmd *qc)
 
 			prd[idx].addr = cpu_to_le32(addr);
 			prd[idx].flags_len = cpu_to_le32(len & 0xffff);
-			VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
+			ata_port_dbg(ap, "PRD[%u] = (0x%X, 0x%X)\n",
+				     idx, addr, len);
 
 			idx++;
 			sg_len -= len;
@@ -609,17 +610,16 @@ static void pdc_fill_sg(struct ata_queued_cmd *qc)
 	if (len > SG_COUNT_ASIC_BUG) {
 		u32 addr;
 
-		VPRINTK("Splitting last PRD.\n");
-
 		addr = le32_to_cpu(prd[idx - 1].addr);
 		prd[idx - 1].flags_len = cpu_to_le32(len - SG_COUNT_ASIC_BUG);
-		VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx - 1, addr, SG_COUNT_ASIC_BUG);
+		ata_port_dbg(ap, "PRD[%u] = (0x%X, 0x%X)\n",
+			     idx - 1, addr, SG_COUNT_ASIC_BUG);
 
 		addr = addr + len - SG_COUNT_ASIC_BUG;
 		len = SG_COUNT_ASIC_BUG;
 		prd[idx].addr = cpu_to_le32(addr);
 		prd[idx].flags_len = cpu_to_le32(len);
-		VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
+		ata_port_dbg(ap, "PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
 
 		idx++;
 	}
@@ -632,12 +632,10 @@ static enum ata_completion_errors pdc_qc_prep(struct ata_queued_cmd *qc)
 	struct pdc_port_priv *pp = qc->ap->private_data;
 	unsigned int i;
 
-	VPRINTK("ENTER\n");
-
 	switch (qc->tf.protocol) {
 	case ATA_PROT_DMA:
 		pdc_fill_sg(qc);
-		/*FALLTHROUGH*/
+		fallthrough;
 	case ATA_PROT_NODATA:
 		i = pdc_pkt_header(&qc->tf, qc->ap->bmdma_prd_dma,
 				   qc->dev->devno, pp->pkt);
@@ -652,7 +650,7 @@ static enum ata_completion_errors pdc_qc_prep(struct ata_queued_cmd *qc)
 		break;
 	case ATAPI_PROT_DMA:
 		pdc_fill_sg(qc);
-		/*FALLTHROUGH*/
+		fallthrough;
 	case ATAPI_PROT_NODATA:
 		pdc_atapi_pkt(qc);
 		break;
@@ -819,7 +817,7 @@ static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class,
 
 static void pdc_error_handler(struct ata_port *ap)
 {
-	if (!(ap->pflags & ATA_PFLAG_FROZEN))
+	if (!ata_port_is_frozen(ap))
 		pdc_reset_port(ap);
 
 	ata_sff_error_handler(ap);
@@ -830,7 +828,7 @@ static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
 	struct ata_port *ap = qc->ap;
 
 	/* make DMA engine forget about the failed command */
-	if (qc->flags & ATA_QCFLAG_FAILED)
+	if (qc->flags & ATA_QCFLAG_EH)
 		pdc_reset_port(ap);
 }
 
@@ -922,12 +920,8 @@ static irqreturn_t pdc_interrupt(int irq, void *dev_instance)
 	u32 hotplug_status;
 	int is_sataii_tx4;
 
-	VPRINTK("ENTER\n");
-
-	if (!host || !host->iomap[PDC_MMIO_BAR]) {
-		VPRINTK("QUICK EXIT\n");
+	if (!host || !host->iomap[PDC_MMIO_BAR])
 		return IRQ_NONE;
-	}
 
 	host_mmio = host->iomap[PDC_MMIO_BAR];
 
@@ -946,23 +940,18 @@ static irqreturn_t pdc_interrupt(int irq, void *dev_instance)
 	/* reading should also clear interrupts */
 	mask = readl(host_mmio + PDC_INT_SEQMASK);
 
-	if (mask == 0xffffffff && hotplug_status == 0) {
-		VPRINTK("QUICK EXIT 2\n");
+	if (mask == 0xffffffff && hotplug_status == 0)
 		goto done_irq;
-	}
 
 	mask &= 0xffff;		/* only 16 SEQIDs possible */
-	if (mask == 0 && hotplug_status == 0) {
-		VPRINTK("QUICK EXIT 3\n");
+	if (mask == 0 && hotplug_status == 0)
 		goto done_irq;
-	}
 
 	writel(mask, host_mmio + PDC_INT_SEQMASK);
 
 	is_sataii_tx4 = pdc_is_sataii_tx4(host->ports[0]->flags);
 
 	for (i = 0; i < host->n_ports; i++) {
-		VPRINTK("port %u\n", i);
 		ap = host->ports[i];
 
 		/* check for a plug or unplug event */
@@ -989,8 +978,6 @@ static irqreturn_t pdc_interrupt(int irq, void *dev_instance)
 		}
 	}
 
-	VPRINTK("EXIT\n");
-
 done_irq:
 	spin_unlock(&host->lock);
 	return IRQ_RETVAL(handled);
@@ -1005,8 +992,6 @@ static void pdc_packet_start(struct ata_queued_cmd *qc)
 	unsigned int port_no = ap->port_no;
 	u8 seq = (u8) (port_no + 1);
 
-	VPRINTK("ENTER, ap %p\n", ap);
-
 	writel(0x00000001, host_mmio + (seq * 4));
 	readl(host_mmio + (seq * 4));	/* flush */
 
@@ -1022,11 +1007,11 @@ static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc)
 	case ATAPI_PROT_NODATA:
 		if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
 			break;
-		/*FALLTHROUGH*/
+		fallthrough;
 	case ATA_PROT_NODATA:
 		if (qc->tf.flags & ATA_TFLAG_POLLING)
 			break;
-		/*FALLTHROUGH*/
+		fallthrough;
 	case ATAPI_PROT_DMA:
 	case ATA_PROT_DMA:
 		pdc_packet_start(qc);
diff --git a/drivers/ata/sata_qstor.c b/drivers/ata/sata_qstor.c
index ef00ab644afb..cfb9b5b61cd7 100644
--- a/drivers/ata/sata_qstor.c
+++ b/drivers/ata/sata_qstor.c
@@ -108,7 +108,7 @@ static void qs_thaw(struct ata_port *ap);
 static int qs_prereset(struct ata_link *link, unsigned long deadline);
 static void qs_error_handler(struct ata_port *ap);
 
-static struct scsi_host_template qs_ata_sht = {
+static const struct scsi_host_template qs_ata_sht = {
 	ATA_BASE_SHT(DRV_NAME),
 	.sg_tablesize		= QS_MAX_PRD,
 	.dma_boundary		= QS_DMA_BOUNDARY,
@@ -123,8 +123,8 @@ static struct ata_port_operations qs_ata_ops = {
 
 	.freeze			= qs_freeze,
 	.thaw			= qs_thaw,
-	.prereset		= qs_prereset,
-	.softreset		= ATA_OP_NULL,
+	.reset.prereset		= qs_prereset,
+	.reset.softreset	= ATA_OP_NULL,
 	.error_handler		= qs_error_handler,
 	.lost_interrupt		= ATA_OP_NULL,
 
@@ -252,9 +252,6 @@ static unsigned int qs_fill_sg(struct ata_queued_cmd *qc)
 		len = sg_dma_len(sg);
 		*(__le32 *)prd = cpu_to_le32(len);
 		prd += sizeof(u64);
-
-		VPRINTK("PRD[%u] = (0x%llX, 0x%X)\n", si,
-					(unsigned long long)addr, len);
 	}
 
 	return si;
@@ -268,8 +265,6 @@ static enum ata_completion_errors qs_qc_prep(struct ata_queued_cmd *qc)
 	u64 addr;
 	unsigned int nelem;
 
-	VPRINTK("ENTER\n");
-
 	qs_enter_reg_mode(qc->ap);
 	if (qc->tf.protocol != ATA_PROT_DMA)
 		return AC_ERR_OK;
@@ -304,8 +299,6 @@ static inline void qs_packet_start(struct ata_queued_cmd *qc)
 	struct ata_port *ap = qc->ap;
 	u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
 
-	VPRINTK("ENTER, ap %p\n", ap);
-
 	writeb(QS_CTR0_CLER, chan + QS_CCT_CTR0);
 	wmb();                             /* flush PRDs and pkt to memory */
 	writel(QS_CCF_RUN_PKT, chan + QS_CCT_CFF);
@@ -374,8 +367,8 @@ static inline unsigned int qs_intr_pkt(struct ata_host *host)
 			struct qs_port_priv *pp = ap->private_data;
 			struct ata_queued_cmd *qc;
 
-			DPRINTK("SFF=%08x%08x: sCHAN=%u sHST=%d sDST=%02x\n",
-					sff1, sff0, port_no, sHST, sDST);
+			dev_dbg(host->dev, "SFF=%08x%08x: sHST=%d sDST=%02x\n",
+				sff1, sff0, sHST, sDST);
 			handled = 1;
 			if (!pp || pp->state != qs_state_pkt)
 				continue;
@@ -435,14 +428,10 @@ static irqreturn_t qs_intr(int irq, void *dev_instance)
 	unsigned int handled = 0;
 	unsigned long flags;
 
-	VPRINTK("ENTER\n");
-
 	spin_lock_irqsave(&host->lock, flags);
 	handled  = qs_intr_pkt(host) | qs_intr_mmio(host);
 	spin_unlock_irqrestore(&host->lock, flags);
 
-	VPRINTK("EXIT\n");
-
 	return IRQ_RETVAL(handled);
 }
 
diff --git a/drivers/ata/sata_rcar.c b/drivers/ata/sata_rcar.c
index 980aacdbcf3b..487eadd4073f 100644
--- a/drivers/ata/sata_rcar.c
+++ b/drivers/ata/sata_rcar.c
@@ -11,17 +11,13 @@
 #include <linux/module.h>
 #include <linux/ata.h>
 #include <linux/libata.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
 #include <linux/err.h>
 
 #define DRV_NAME "sata_rcar"
 
-/* SH-Navi2G/ATAPI-ATA compatible task registers */
-#define DATA_REG			0x100
-#define SDEVCON_REG			0x138
-
 /* SH-Navi2G/ATAPI module compatible control registers */
 #define ATAPI_CONTROL1_REG		0x180
 #define ATAPI_STATUS_REG		0x184
@@ -120,7 +116,7 @@
 /* Descriptor table word 0 bit (when DTA32M = 1) */
 #define SATA_RCAR_DTEND			BIT(0)
 
-#define SATA_RCAR_DMA_BOUNDARY		0x1FFFFFFEUL
+#define SATA_RCAR_DMA_BOUNDARY		0x1FFFFFFFUL
 
 /* Gen2 Physical Layer Control Registers */
 #define RCAR_GEN2_PHY_CTL1_REG		0x1704
@@ -283,8 +279,7 @@ static void sata_rcar_dev_select(struct ata_port *ap, unsigned int device)
 	ata_sff_pause(ap);	/* needed; also flushes, for mmio */
 }
 
-static unsigned int sata_rcar_ata_devchk(struct ata_port *ap,
-					 unsigned int device)
+static bool sata_rcar_ata_devchk(struct ata_port *ap, unsigned int device)
 {
 	struct ata_ioports *ioaddr = &ap->ioaddr;
 	u8 nsect, lbal;
@@ -304,9 +299,9 @@ static unsigned int sata_rcar_ata_devchk(struct ata_port *ap,
 	lbal  = ioread32(ioaddr->lbal_addr);
 
 	if (nsect == 0x55 && lbal == 0xaa)
-		return 1;	/* found a device */
+		return true;	/* found a device */
 
-	return 0;		/* nothing found */
+	return false;		/* nothing found */
 }
 
 static int sata_rcar_wait_after_reset(struct ata_link *link,
@@ -323,8 +318,6 @@ static int sata_rcar_bus_softreset(struct ata_port *ap, unsigned long deadline)
 {
 	struct ata_ioports *ioaddr = &ap->ioaddr;
 
-	DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
-
 	/* software reset.  causes dev0 to be selected */
 	iowrite32(ap->ctl, ioaddr->ctl_addr);
 	udelay(20);
@@ -350,7 +343,6 @@ static int sata_rcar_softreset(struct ata_link *link, unsigned int *classes,
 		devmask |= 1 << 0;
 
 	/* issue bus reset */
-	DPRINTK("about to softreset, devmask=%x\n", devmask);
 	rc = sata_rcar_bus_softreset(ap, deadline);
 	/* if link is occupied, -ENODEV too is an error */
 	if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
@@ -361,7 +353,6 @@ static int sata_rcar_softreset(struct ata_link *link, unsigned int *classes,
 	/* determine by signature whether we have ATA or ATAPI devices */
 	classes[0] = ata_sff_dev_classify(&link->device[0], devmask, &err);
 
-	DPRINTK("classes[0]=%u\n", classes[0]);
 	return 0;
 }
 
@@ -383,12 +374,6 @@ static void sata_rcar_tf_load(struct ata_port *ap,
 		iowrite32(tf->hob_lbal, ioaddr->lbal_addr);
 		iowrite32(tf->hob_lbam, ioaddr->lbam_addr);
 		iowrite32(tf->hob_lbah, ioaddr->lbah_addr);
-		VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
-			tf->hob_feature,
-			tf->hob_nsect,
-			tf->hob_lbal,
-			tf->hob_lbam,
-			tf->hob_lbah);
 	}
 
 	if (is_addr) {
@@ -397,18 +382,10 @@ static void sata_rcar_tf_load(struct ata_port *ap,
 		iowrite32(tf->lbal, ioaddr->lbal_addr);
 		iowrite32(tf->lbam, ioaddr->lbam_addr);
 		iowrite32(tf->lbah, ioaddr->lbah_addr);
-		VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
-			tf->feature,
-			tf->nsect,
-			tf->lbal,
-			tf->lbam,
-			tf->lbah);
 	}
 
-	if (tf->flags & ATA_TFLAG_DEVICE) {
+	if (tf->flags & ATA_TFLAG_DEVICE)
 		iowrite32(tf->device, ioaddr->device_addr);
-		VPRINTK("device 0x%X\n", tf->device);
-	}
 
 	ata_wait_idle(ap);
 }
@@ -417,8 +394,8 @@ static void sata_rcar_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
 {
 	struct ata_ioports *ioaddr = &ap->ioaddr;
 
-	tf->command = sata_rcar_check_status(ap);
-	tf->feature = ioread32(ioaddr->error_addr);
+	tf->status = sata_rcar_check_status(ap);
+	tf->error = ioread32(ioaddr->error_addr);
 	tf->nsect = ioread32(ioaddr->nsect_addr);
 	tf->lbal = ioread32(ioaddr->lbal_addr);
 	tf->lbam = ioread32(ioaddr->lbam_addr);
@@ -440,8 +417,6 @@ static void sata_rcar_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
 static void sata_rcar_exec_command(struct ata_port *ap,
 				   const struct ata_taskfile *tf)
 {
-	DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
-
 	iowrite32(tf->command, ap->ioaddr.command_addr);
 	ata_sff_pause(ap);
 }
@@ -499,7 +474,6 @@ static void sata_rcar_drain_fifo(struct ata_queued_cmd *qc)
 			count < 65536; count += 2)
 		ioread32(ap->ioaddr.data_addr);
 
-	/* Can become DEBUG later */
 	if (count)
 		ata_port_dbg(ap, "drained %d bytes to clear DRQ\n", count);
 }
@@ -543,7 +517,6 @@ static void sata_rcar_bmdma_fill_sg(struct ata_queued_cmd *qc)
 
 		prd[si].addr = cpu_to_le32(addr);
 		prd[si].flags_len = cpu_to_le32(sg_len);
-		VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", si, addr, sg_len);
 	}
 
 	/* end-of-table flag */
@@ -635,7 +608,7 @@ static u8 sata_rcar_bmdma_status(struct ata_port *ap)
 	return host_stat;
 }
 
-static struct scsi_host_template sata_rcar_sht = {
+static const struct scsi_host_template sata_rcar_sht = {
 	ATA_BASE_SHT(DRV_NAME),
 	/*
 	 * This controller allows transfer chunks up to 512MB which cross 64KB
@@ -651,7 +624,7 @@ static struct ata_port_operations sata_rcar_port_ops = {
 
 	.freeze			= sata_rcar_freeze,
 	.thaw			= sata_rcar_thaw,
-	.softreset		= sata_rcar_softreset,
+	.reset.softreset	= sata_rcar_softreset,
 
 	.scr_read		= sata_rcar_scr_read,
 	.scr_write		= sata_rcar_scr_write,
@@ -685,7 +658,7 @@ static void sata_rcar_serr_interrupt(struct ata_port *ap)
 	if (!serror)
 		return;
 
-	DPRINTK("SError @host_intr: 0x%x\n", serror);
+	ata_port_dbg(ap, "SError @host_intr: 0x%x\n", serror);
 
 	/* first, analyze and record host port events */
 	ata_ehi_clear_desc(ehi);
@@ -879,7 +852,7 @@ static const struct of_device_id sata_rcar_match[] = {
 		.compatible = "renesas,rcar-gen3-sata",
 		.data = (void *)RCAR_GEN3_SATA
 	},
-	{ },
+	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, sata_rcar_match);
 
@@ -888,26 +861,22 @@ static int sata_rcar_probe(struct platform_device *pdev)
 	struct device *dev = &pdev->dev;
 	struct ata_host *host;
 	struct sata_rcar_priv *priv;
-	struct resource *mem;
-	int irq;
-	int ret = 0;
+	int irq, ret;
 
 	irq = platform_get_irq(pdev, 0);
 	if (irq < 0)
 		return irq;
-	if (!irq)
-		return -EINVAL;
 
 	priv = devm_kzalloc(dev, sizeof(struct sata_rcar_priv), GFP_KERNEL);
 	if (!priv)
 		return -ENOMEM;
 
-	priv->type = (enum sata_rcar_type)of_device_get_match_data(dev);
+	priv->type = (unsigned long)of_device_get_match_data(dev);
 
 	pm_runtime_enable(dev);
 	ret = pm_runtime_get_sync(dev);
 	if (ret < 0)
-		goto err_pm_disable;
+		goto err_pm_put;
 
 	host = ata_host_alloc(dev, 1);
 	if (!host) {
@@ -917,8 +886,7 @@ static int sata_rcar_probe(struct platform_device *pdev)
 
 	host->private_data = priv;
 
-	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	priv->base = devm_ioremap_resource(dev, mem);
+	priv->base = devm_platform_ioremap_resource(pdev, 0);
 	if (IS_ERR(priv->base)) {
 		ret = PTR_ERR(priv->base);
 		goto err_pm_put;
@@ -937,12 +905,11 @@ static int sata_rcar_probe(struct platform_device *pdev)
 
 err_pm_put:
 	pm_runtime_put(dev);
-err_pm_disable:
 	pm_runtime_disable(dev);
 	return ret;
 }
 
-static int sata_rcar_remove(struct platform_device *pdev)
+static void sata_rcar_remove(struct platform_device *pdev)
 {
 	struct ata_host *host = platform_get_drvdata(pdev);
 	struct sata_rcar_priv *priv = host->private_data;
@@ -958,8 +925,6 @@ static int sata_rcar_remove(struct platform_device *pdev)
 
 	pm_runtime_put(&pdev->dev);
 	pm_runtime_disable(&pdev->dev);
-
-	return 0;
 }
 
 #ifdef CONFIG_PM_SLEEP
@@ -968,19 +933,17 @@ static int sata_rcar_suspend(struct device *dev)
 	struct ata_host *host = dev_get_drvdata(dev);
 	struct sata_rcar_priv *priv = host->private_data;
 	void __iomem *base = priv->base;
-	int ret;
 
-	ret = ata_host_suspend(host, PMSG_SUSPEND);
-	if (!ret) {
-		/* disable interrupts */
-		iowrite32(0, base + ATAPI_INT_ENABLE_REG);
-		/* mask */
-		iowrite32(priv->sataint_mask, base + SATAINTMASK_REG);
+	ata_host_suspend(host, PMSG_SUSPEND);
 
-		pm_runtime_put(dev);
-	}
+	/* disable interrupts */
+	iowrite32(0, base + ATAPI_INT_ENABLE_REG);
+	/* mask */
+	iowrite32(priv->sataint_mask, base + SATAINTMASK_REG);
 
-	return ret;
+	pm_runtime_put(dev);
+
+	return 0;
 }
 
 static int sata_rcar_resume(struct device *dev)
@@ -991,8 +954,10 @@ static int sata_rcar_resume(struct device *dev)
 	int ret;
 
 	ret = pm_runtime_get_sync(dev);
-	if (ret < 0)
+	if (ret < 0) {
+		pm_runtime_put(dev);
 		return ret;
+	}
 
 	if (priv->type == RCAR_GEN3_SATA) {
 		sata_rcar_init_module(priv);
@@ -1017,8 +982,10 @@ static int sata_rcar_restore(struct device *dev)
 	int ret;
 
 	ret = pm_runtime_get_sync(dev);
-	if (ret < 0)
+	if (ret < 0) {
+		pm_runtime_put(dev);
 		return ret;
+	}
 
 	sata_rcar_setup_port(host);
 
diff --git a/drivers/ata/sata_sil.c b/drivers/ata/sata_sil.c
index 75321f1ceba5..1b6dc950a42a 100644
--- a/drivers/ata/sata_sil.c
+++ b/drivers/ata/sata_sil.c
@@ -128,7 +128,7 @@ static const struct pci_device_id sil_pci_tbl[] = {
 static const struct sil_drivelist {
 	const char *product;
 	unsigned int quirk;
-} sil_blacklist [] = {
+} sil_quirks[] = {
 	{ "ST320012AS",		SIL_QUIRK_MOD15WRITE },
 	{ "ST330013AS",		SIL_QUIRK_MOD15WRITE },
 	{ "ST340017AS",		SIL_QUIRK_MOD15WRITE },
@@ -156,7 +156,7 @@ static struct pci_driver sil_pci_driver = {
 #endif
 };
 
-static struct scsi_host_template sil_sht = {
+static const struct scsi_host_template sil_sht = {
 	ATA_BASE_SHT(DRV_NAME),
 	/** These controllers support Large Block Transfer which allows
 	    transfer chunks up to 2GB and which cross 64KB boundaries,
@@ -307,7 +307,6 @@ static void sil_fill_sg(struct ata_queued_cmd *qc)
 
 		prd->addr = cpu_to_le32(addr);
 		prd->flags_len = cpu_to_le32(sg_len);
-		VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", si, addr, sg_len);
 
 		last_prd = prd;
 		prd++;
@@ -352,7 +351,7 @@ static int sil_set_mode(struct ata_link *link, struct ata_device **r_failed)
 	u32 tmp, dev_mode[2] = { };
 	int rc;
 
-	rc = ata_do_set_mode(link, r_failed);
+	rc = ata_set_mode(link, r_failed);
 	if (rc)
 		return rc;
 
@@ -601,8 +600,8 @@ static void sil_thaw(struct ata_port *ap)
  *	list, and apply the fixups to only the specific
  *	devices/hosts/firmwares that need it.
  *
- *	20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
- *	The Maxtor quirk is in the blacklist, but I'm keeping the original
+ *	20040111 - Seagate drives affected by the Mod15Write bug are quirked
+ *	The Maxtor quirk is in sil_quirks, but I'm keeping the original
  *	pessimistic fix for the following reasons...
  *	- There seems to be less info on it, only one device gleaned off the
  *	Windows	driver, maybe only one is affected.  More info would be greatly
@@ -617,13 +616,13 @@ static void sil_dev_config(struct ata_device *dev)
 	unsigned char model_num[ATA_ID_PROD_LEN + 1];
 
 	/* This controller doesn't support trim */
-	dev->horkage |= ATA_HORKAGE_NOTRIM;
+	dev->quirks |= ATA_QUIRK_NOTRIM;
 
 	ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
 
-	for (n = 0; sil_blacklist[n].product; n++)
-		if (!strcmp(sil_blacklist[n].product, model_num)) {
-			quirks = sil_blacklist[n].quirk;
+	for (n = 0; sil_quirks[n].product; n++)
+		if (!strcmp(sil_quirks[n].product, model_num)) {
+			quirks = sil_quirks[n].quirk;
 			break;
 		}
 
diff --git a/drivers/ata/sata_sil24.c b/drivers/ata/sata_sil24.c
index 560070d4f1d0..d642ece9f07a 100644
--- a/drivers/ata/sata_sil24.c
+++ b/drivers/ata/sata_sil24.c
@@ -328,7 +328,7 @@ static int sil24_scr_write(struct ata_link *link, unsigned sc_reg, u32 val);
 static int sil24_qc_defer(struct ata_queued_cmd *qc);
 static enum ata_completion_errors sil24_qc_prep(struct ata_queued_cmd *qc);
 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
-static bool sil24_qc_fill_rtf(struct ata_queued_cmd *qc);
+static void sil24_qc_fill_rtf(struct ata_queued_cmd *qc);
 static void sil24_pmp_attach(struct ata_port *ap);
 static void sil24_pmp_detach(struct ata_port *ap);
 static void sil24_freeze(struct ata_port *ap);
@@ -373,12 +373,14 @@ static struct pci_driver sil24_pci_driver = {
 #endif
 };
 
-static struct scsi_host_template sil24_sht = {
-	ATA_NCQ_SHT(DRV_NAME),
+static const struct scsi_host_template sil24_sht = {
+	__ATA_BASE_SHT(DRV_NAME),
 	.can_queue		= SIL24_MAX_CMDS,
 	.sg_tablesize		= SIL24_MAX_SGE,
 	.dma_boundary		= ATA_DMA_BOUNDARY,
-	.tag_alloc_policy	= BLK_TAG_ALLOC_FIFO,
+	.sdev_groups		= ata_ncq_sdev_groups,
+	.change_queue_depth	= ata_scsi_change_queue_depth,
+	.sdev_configure		= ata_scsi_sdev_configure
 };
 
 static struct ata_port_operations sil24_ops = {
@@ -391,10 +393,10 @@ static struct ata_port_operations sil24_ops = {
 
 	.freeze			= sil24_freeze,
 	.thaw			= sil24_thaw,
-	.softreset		= sil24_softreset,
-	.hardreset		= sil24_hardreset,
-	.pmp_softreset		= sil24_softreset,
-	.pmp_hardreset		= sil24_pmp_hardreset,
+	.reset.softreset	= sil24_softreset,
+	.reset.hardreset	= sil24_hardreset,
+	.pmp_reset.softreset	= sil24_softreset,
+	.pmp_reset.hardreset	= sil24_pmp_hardreset,
 	.error_handler		= sil24_error_handler,
 	.post_internal_cmd	= sil24_post_internal_cmd,
 	.dev_config		= sil24_dev_config,
@@ -594,7 +596,7 @@ static int sil24_init_port(struct ata_port *ap)
 static int sil24_exec_polled_cmd(struct ata_port *ap, int pmp,
 				 const struct ata_taskfile *tf,
 				 int is_cmd, u32 ctrl,
-				 unsigned long timeout_msec)
+				 unsigned int timeout_msec)
 {
 	void __iomem *port = sil24_port_base(ap);
 	struct sil24_port_priv *pp = ap->private_data;
@@ -648,13 +650,11 @@ static int sil24_softreset(struct ata_link *link, unsigned int *class,
 {
 	struct ata_port *ap = link->ap;
 	int pmp = sata_srst_pmp(link);
-	unsigned long timeout_msec = 0;
+	unsigned int timeout_msec = 0;
 	struct ata_taskfile tf;
 	const char *reason;
 	int rc;
 
-	DPRINTK("ENTER\n");
-
 	/* put the port into known state */
 	if (sil24_init_port(ap)) {
 		reason = "port not ready";
@@ -677,9 +677,8 @@ static int sil24_softreset(struct ata_link *link, unsigned int *class,
 	}
 
 	sil24_read_tf(ap, 0, &tf);
-	*class = ata_dev_classify(&tf);
+	*class = ata_port_classify(ap, &tf);
 
-	DPRINTK("EXIT, class=%u\n", *class);
 	return 0;
 
  err:
@@ -901,10 +900,9 @@ static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
 	return 0;
 }
 
-static bool sil24_qc_fill_rtf(struct ata_queued_cmd *qc)
+static void sil24_qc_fill_rtf(struct ata_queued_cmd *qc)
 {
 	sil24_read_tf(qc->ap, qc->hw_tag, &qc->result_tf);
-	return true;
 }
 
 static void sil24_pmp_attach(struct ata_port *ap)
@@ -1185,7 +1183,7 @@ static void sil24_post_internal_cmd(struct ata_queued_cmd *qc)
 	struct ata_port *ap = qc->ap;
 
 	/* make DMA engine forget about the failed command */
-	if ((qc->flags & ATA_QCFLAG_FAILED) && sil24_init_port(ap))
+	if ((qc->flags & ATA_QCFLAG_EH) && sil24_init_port(ap))
 		ata_eh_freeze_port(ap);
 }
 
@@ -1318,7 +1316,7 @@ static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 
 	if (sata_sil24_msi && !pci_enable_msi(pdev)) {
 		dev_info(&pdev->dev, "Using MSI\n");
-		pci_intx(pdev, 0);
+		pcim_intx(pdev, 0);
 	}
 
 	pci_set_master(pdev);
diff --git a/drivers/ata/sata_sis.c b/drivers/ata/sata_sis.c
index 316237362aa9..b8b6d9eff3b8 100644
--- a/drivers/ata/sata_sis.c
+++ b/drivers/ata/sata_sis.c
@@ -72,7 +72,7 @@ static struct pci_driver sis_pci_driver = {
 #endif
 };
 
-static struct scsi_host_template sis_sht = {
+static const struct scsi_host_template sis_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
@@ -290,7 +290,7 @@ static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 	}
 
 	pci_set_master(pdev);
-	pci_intx(pdev, 1);
+	pcim_intx(pdev, 1);
 	return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
 				 IRQF_SHARED, &sis_sht);
 }
diff --git a/drivers/ata/sata_svw.c b/drivers/ata/sata_svw.c
index f8552559db7f..c5d6aa36c9c3 100644
--- a/drivers/ata/sata_svw.c
+++ b/drivers/ata/sata_svw.c
@@ -32,6 +32,7 @@
 #include <scsi/scsi.h>
 #include <linux/libata.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
 
 #define DRV_NAME	"sata_svw"
 #define DRV_VERSION	"2.3"
@@ -194,24 +195,24 @@ static void k2_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
 static void k2_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
 {
 	struct ata_ioports *ioaddr = &ap->ioaddr;
-	u16 nsect, lbal, lbam, lbah, feature;
+	u16 nsect, lbal, lbam, lbah, error;
 
-	tf->command = k2_stat_check_status(ap);
+	tf->status = k2_stat_check_status(ap);
 	tf->device = readw(ioaddr->device_addr);
-	feature = readw(ioaddr->error_addr);
+	error = readw(ioaddr->error_addr);
 	nsect = readw(ioaddr->nsect_addr);
 	lbal = readw(ioaddr->lbal_addr);
 	lbam = readw(ioaddr->lbam_addr);
 	lbah = readw(ioaddr->lbah_addr);
 
-	tf->feature = feature;
+	tf->error = error;
 	tf->nsect = nsect;
 	tf->lbal = lbal;
 	tf->lbam = lbam;
 	tf->lbah = lbah;
 
 	if (tf->flags & ATA_TFLAG_LBA48) {
-		tf->hob_feature = feature >> 8;
+		tf->hob_feature = error >> 8;
 		tf->hob_nsect = nsect >> 8;
 		tf->hob_lbal = lbal >> 8;
 		tf->hob_lbam = lbam >> 8;
@@ -319,10 +320,11 @@ static int k2_sata_show_info(struct seq_file *m, struct Scsi_Host *shost)
 	/* Match it to a port node */
 	index = (ap == ap->host->ports[0]) ? 0 : 1;
 	for (np = np->child; np != NULL; np = np->sibling) {
-		const u32 *reg = of_get_property(np, "reg", NULL);
-		if (!reg)
+		u64 reg;
+
+		if (of_property_read_reg(np, 0, &reg, NULL))
 			continue;
-		if (index == *reg) {
+		if (index == reg) {
 			seq_printf(m, "devspec: %pOF\n", np);
 			break;
 		}
@@ -330,7 +332,7 @@ static int k2_sata_show_info(struct seq_file *m, struct Scsi_Host *shost)
 	return 0;
 }
 
-static struct scsi_host_template k2_sata_sht = {
+static const struct scsi_host_template k2_sata_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 	.show_info		= k2_sata_show_info,
 };
@@ -338,8 +340,8 @@ static struct scsi_host_template k2_sata_sht = {
 
 static struct ata_port_operations k2_sata_ops = {
 	.inherits		= &ata_bmdma_port_ops,
-	.softreset              = k2_sata_softreset,
-	.hardreset              = k2_sata_hardreset,
+	.reset.softreset	= k2_sata_softreset,
+	.reset.hardreset	= k2_sata_hardreset,
 	.sff_tf_load		= k2_sata_tf_load,
 	.sff_tf_read		= k2_sata_tf_read,
 	.sff_check_status	= k2_stat_check_status,
diff --git a/drivers/ata/sata_sx4.c b/drivers/ata/sata_sx4.c
index 2c7b30c5ea3d..0986ebd1eb4e 100644
--- a/drivers/ata/sata_sx4.c
+++ b/drivers/ata/sata_sx4.c
@@ -78,6 +78,9 @@
 #define DRV_NAME	"sata_sx4"
 #define DRV_VERSION	"0.12"
 
+static int dimm_test;
+module_param(dimm_test, int, 0644);
+MODULE_PARM_DESC(dimm_test, "Enable DIMM test during startup (1 = enabled)");
 
 enum {
 	PDC_MMIO_BAR		= 3,
@@ -211,10 +214,8 @@ static unsigned int pdc20621_i2c_read(struct ata_host *host,
 				      u32 device, u32 subaddr, u32 *pdata);
 static int pdc20621_prog_dimm0(struct ata_host *host);
 static unsigned int pdc20621_prog_dimm_global(struct ata_host *host);
-#ifdef ATA_VERBOSE_DEBUG
 static void pdc20621_get_from_dimm(struct ata_host *host,
 				   void *psource, u32 offset, u32 size);
-#endif
 static void pdc20621_put_to_dimm(struct ata_host *host,
 				 void *psource, u32 offset, u32 size);
 static void pdc20621_irq_clear(struct ata_port *ap);
@@ -225,13 +226,12 @@ static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
 
 
-static struct scsi_host_template pdc_sata_sht = {
+static const struct scsi_host_template pdc_sata_sht = {
 	ATA_BASE_SHT(DRV_NAME),
 	.sg_tablesize		= LIBATA_MAX_PRD,
 	.dma_boundary		= ATA_DMA_BOUNDARY,
 };
 
-/* TODO: inherit from base port_ops after converting to new EH */
 static struct ata_port_operations pdc_20621_ops = {
 	.inherits		= &ata_sff_port_ops,
 
@@ -241,7 +241,7 @@ static struct ata_port_operations pdc_20621_ops = {
 
 	.freeze			= pdc_freeze,
 	.thaw			= pdc_thaw,
-	.softreset		= pdc_softreset,
+	.reset.softreset	= pdc_softreset,
 	.error_handler		= pdc_error_handler,
 	.lost_interrupt		= ATA_OP_NULL,
 	.post_internal_cmd	= pdc_post_internal_cmd,
@@ -308,15 +308,9 @@ static inline void pdc20621_ata_sg(u8 *buf, unsigned int portno,
 	/* output ATA packet S/G table */
 	addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
 	       (PDC_DIMM_DATA_STEP * portno);
-	VPRINTK("ATA sg addr 0x%x, %d\n", addr, addr);
+
 	buf32[dw] = cpu_to_le32(addr);
 	buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
-
-	VPRINTK("ATA PSG @ %x == (0x%x, 0x%x)\n",
-		PDC_20621_DIMM_BASE +
-		       (PDC_DIMM_WINDOW_STEP * portno) +
-		       PDC_DIMM_APKT_PRD,
-		buf32[dw], buf32[dw + 1]);
 }
 
 static inline void pdc20621_host_sg(u8 *buf, unsigned int portno,
@@ -332,12 +326,6 @@ static inline void pdc20621_host_sg(u8 *buf, unsigned int portno,
 
 	buf32[dw] = cpu_to_le32(addr);
 	buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
-
-	VPRINTK("HOST PSG @ %x == (0x%x, 0x%x)\n",
-		PDC_20621_DIMM_BASE +
-		       (PDC_DIMM_WINDOW_STEP * portno) +
-		       PDC_DIMM_HPKT_PRD,
-		buf32[dw], buf32[dw + 1]);
 }
 
 static inline unsigned int pdc20621_ata_pkt(struct ata_taskfile *tf,
@@ -351,7 +339,6 @@ static inline unsigned int pdc20621_ata_pkt(struct ata_taskfile *tf,
 	unsigned int dimm_sg = PDC_20621_DIMM_BASE +
 			       (PDC_DIMM_WINDOW_STEP * portno) +
 			       PDC_DIMM_APKT_PRD;
-	VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
 
 	i = PDC_DIMM_ATA_PKT;
 
@@ -406,8 +393,6 @@ static inline void pdc20621_host_pkt(struct ata_taskfile *tf, u8 *buf,
 	unsigned int dimm_sg = PDC_20621_DIMM_BASE +
 			       (PDC_DIMM_WINDOW_STEP * portno) +
 			       PDC_DIMM_HPKT_PRD;
-	VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
-	VPRINTK("host_sg == 0x%x, %d\n", host_sg, host_sg);
 
 	dw = PDC_DIMM_HOST_PKT >> 2;
 
@@ -424,14 +409,6 @@ static inline void pdc20621_host_pkt(struct ata_taskfile *tf, u8 *buf,
 	buf32[dw + 1] = cpu_to_le32(host_sg);
 	buf32[dw + 2] = cpu_to_le32(dimm_sg);
 	buf32[dw + 3] = 0;
-
-	VPRINTK("HOST PKT @ %x == (0x%x 0x%x 0x%x 0x%x)\n",
-		PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * portno) +
-			PDC_DIMM_HOST_PKT,
-		buf32[dw + 0],
-		buf32[dw + 1],
-		buf32[dw + 2],
-		buf32[dw + 3]);
 }
 
 static void pdc20621_dma_prep(struct ata_queued_cmd *qc)
@@ -447,8 +424,6 @@ static void pdc20621_dma_prep(struct ata_queued_cmd *qc)
 
 	WARN_ON(!(qc->flags & ATA_QCFLAG_DMAMAP));
 
-	VPRINTK("ata%u: ENTER\n", ap->print_id);
-
 	/* hard-code chip #0 */
 	mmio += PDC_CHIP0_OFS;
 
@@ -492,7 +467,8 @@ static void pdc20621_dma_prep(struct ata_queued_cmd *qc)
 
 	readl(dimm_mmio);	/* MMIO PCI posting flush */
 
-	VPRINTK("ata pkt buf ofs %u, prd size %u, mmio copied\n", i, sgt_len);
+	ata_port_dbg(ap, "ata pkt buf ofs %u, prd size %u, mmio copied\n",
+		     i, sgt_len);
 }
 
 static void pdc20621_nodata_prep(struct ata_queued_cmd *qc)
@@ -504,8 +480,6 @@ static void pdc20621_nodata_prep(struct ata_queued_cmd *qc)
 	unsigned int portno = ap->port_no;
 	unsigned int i;
 
-	VPRINTK("ata%u: ENTER\n", ap->print_id);
-
 	/* hard-code chip #0 */
 	mmio += PDC_CHIP0_OFS;
 
@@ -527,7 +501,7 @@ static void pdc20621_nodata_prep(struct ata_queued_cmd *qc)
 
 	readl(dimm_mmio);	/* MMIO PCI posting flush */
 
-	VPRINTK("ata pkt buf ofs %u, mmio copied\n", i);
+	ata_port_dbg(ap, "ata pkt buf ofs %u, mmio copied\n", i);
 }
 
 static enum ata_completion_errors pdc20621_qc_prep(struct ata_queued_cmd *qc)
@@ -601,7 +575,6 @@ static void pdc20621_pop_hdma(struct ata_queued_cmd *qc)
 	pp->hdma_cons++;
 }
 
-#ifdef ATA_VERBOSE_DEBUG
 static void pdc20621_dump_hdma(struct ata_queued_cmd *qc)
 {
 	struct ata_port *ap = qc->ap;
@@ -611,14 +584,10 @@ static void pdc20621_dump_hdma(struct ata_queued_cmd *qc)
 	dimm_mmio += (port_no * PDC_DIMM_WINDOW_STEP);
 	dimm_mmio += PDC_DIMM_HOST_PKT;
 
-	printk(KERN_ERR "HDMA[0] == 0x%08X\n", readl(dimm_mmio));
-	printk(KERN_ERR "HDMA[1] == 0x%08X\n", readl(dimm_mmio + 4));
-	printk(KERN_ERR "HDMA[2] == 0x%08X\n", readl(dimm_mmio + 8));
-	printk(KERN_ERR "HDMA[3] == 0x%08X\n", readl(dimm_mmio + 12));
+	ata_port_dbg(ap, "HDMA 0x%08X 0x%08X 0x%08X 0x%08X\n",
+		     readl(dimm_mmio), readl(dimm_mmio + 4),
+		     readl(dimm_mmio + 8), readl(dimm_mmio + 12));
 }
-#else
-static inline void pdc20621_dump_hdma(struct ata_queued_cmd *qc) { }
-#endif /* ATA_VERBOSE_DEBUG */
 
 static void pdc20621_packet_start(struct ata_queued_cmd *qc)
 {
@@ -633,8 +602,6 @@ static void pdc20621_packet_start(struct ata_queued_cmd *qc)
 	/* hard-code chip #0 */
 	mmio += PDC_CHIP0_OFS;
 
-	VPRINTK("ata%u: ENTER\n", ap->print_id);
-
 	wmb();			/* flush PRD, pkt writes */
 
 	port_ofs = PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
@@ -645,7 +612,7 @@ static void pdc20621_packet_start(struct ata_queued_cmd *qc)
 
 		pdc20621_dump_hdma(qc);
 		pdc20621_push_hdma(qc, seq, port_ofs + PDC_DIMM_HOST_PKT);
-		VPRINTK("queued ofs 0x%x (%u), seq %u\n",
+		ata_port_dbg(ap, "queued ofs 0x%x (%u), seq %u\n",
 			port_ofs + PDC_DIMM_HOST_PKT,
 			port_ofs + PDC_DIMM_HOST_PKT,
 			seq);
@@ -656,7 +623,7 @@ static void pdc20621_packet_start(struct ata_queued_cmd *qc)
 		writel(port_ofs + PDC_DIMM_ATA_PKT,
 		       ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
 		readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
-		VPRINTK("submitted ofs 0x%x (%u), seq %u\n",
+		ata_port_dbg(ap, "submitted ofs 0x%x (%u), seq %u\n",
 			port_ofs + PDC_DIMM_ATA_PKT,
 			port_ofs + PDC_DIMM_ATA_PKT,
 			seq);
@@ -669,7 +636,7 @@ static unsigned int pdc20621_qc_issue(struct ata_queued_cmd *qc)
 	case ATA_PROT_NODATA:
 		if (qc->tf.flags & ATA_TFLAG_POLLING)
 			break;
-		/*FALLTHROUGH*/
+		fallthrough;
 	case ATA_PROT_DMA:
 		pdc20621_packet_start(qc);
 		return 0;
@@ -696,14 +663,12 @@ static inline unsigned int pdc20621_host_intr(struct ata_port *ap,
 	u8 status;
 	unsigned int handled = 0;
 
-	VPRINTK("ENTER\n");
-
 	if ((qc->tf.protocol == ATA_PROT_DMA) &&	/* read */
 	    (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
 
 		/* step two - DMA from DIMM to host */
 		if (doing_hdma) {
-			VPRINTK("ata%u: read hdma, 0x%x 0x%x\n", ap->print_id,
+			ata_port_dbg(ap, "read hdma, 0x%x 0x%x\n",
 				readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
 			/* get drive status; clear intr; complete txn */
 			qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
@@ -714,7 +679,7 @@ static inline unsigned int pdc20621_host_intr(struct ata_port *ap,
 		/* step one - exec ATA command */
 		else {
 			u8 seq = (u8) (port_no + 1 + 4);
-			VPRINTK("ata%u: read ata, 0x%x 0x%x\n", ap->print_id,
+			ata_port_dbg(ap, "read ata, 0x%x 0x%x\n",
 				readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
 
 			/* submit hdma pkt */
@@ -729,7 +694,7 @@ static inline unsigned int pdc20621_host_intr(struct ata_port *ap,
 		/* step one - DMA from host to DIMM */
 		if (doing_hdma) {
 			u8 seq = (u8) (port_no + 1);
-			VPRINTK("ata%u: write hdma, 0x%x 0x%x\n", ap->print_id,
+			ata_port_dbg(ap, "write hdma, 0x%x 0x%x\n",
 				readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
 
 			/* submit ata pkt */
@@ -742,7 +707,7 @@ static inline unsigned int pdc20621_host_intr(struct ata_port *ap,
 
 		/* step two - execute ATA command */
 		else {
-			VPRINTK("ata%u: write ata, 0x%x 0x%x\n", ap->print_id,
+			ata_port_dbg(ap, "write ata, 0x%x 0x%x\n",
 				readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
 			/* get drive status; clear intr; complete txn */
 			qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
@@ -755,7 +720,7 @@ static inline unsigned int pdc20621_host_intr(struct ata_port *ap,
 	} else if (qc->tf.protocol == ATA_PROT_NODATA) {
 
 		status = ata_sff_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
-		DPRINTK("BUS_NODATA (drv_stat 0x%X)\n", status);
+		ata_port_dbg(ap, "BUS_NODATA (drv_stat 0x%X)\n", status);
 		qc->err_mask |= ac_err_mask(status);
 		ata_qc_complete(qc);
 		handled = 1;
@@ -781,29 +746,21 @@ static irqreturn_t pdc20621_interrupt(int irq, void *dev_instance)
 	unsigned int handled = 0;
 	void __iomem *mmio_base;
 
-	VPRINTK("ENTER\n");
-
-	if (!host || !host->iomap[PDC_MMIO_BAR]) {
-		VPRINTK("QUICK EXIT\n");
+	if (!host || !host->iomap[PDC_MMIO_BAR])
 		return IRQ_NONE;
-	}
 
 	mmio_base = host->iomap[PDC_MMIO_BAR];
 
 	/* reading should also clear interrupts */
 	mmio_base += PDC_CHIP0_OFS;
 	mask = readl(mmio_base + PDC_20621_SEQMASK);
-	VPRINTK("mask == 0x%x\n", mask);
 
-	if (mask == 0xffffffff) {
-		VPRINTK("QUICK EXIT 2\n");
+	if (mask == 0xffffffff)
 		return IRQ_NONE;
-	}
+
 	mask &= 0xffff;		/* only 16 tags possible */
-	if (!mask) {
-		VPRINTK("QUICK EXIT 3\n");
+	if (!mask)
 		return IRQ_NONE;
-	}
 
 	spin_lock(&host->lock);
 
@@ -816,7 +773,8 @@ static irqreturn_t pdc20621_interrupt(int irq, void *dev_instance)
 		else
 			ap = host->ports[port_no];
 		tmp = mask & (1 << i);
-		VPRINTK("seq %u, port_no %u, ap %p, tmp %x\n", i, port_no, ap, tmp);
+		if (ap)
+			ata_port_dbg(ap, "seq %u, tmp %x\n", i, tmp);
 		if (tmp && ap) {
 			struct ata_queued_cmd *qc;
 
@@ -829,10 +787,6 @@ static irqreturn_t pdc20621_interrupt(int irq, void *dev_instance)
 
 	spin_unlock(&host->lock);
 
-	VPRINTK("mask == 0x%x\n", mask);
-
-	VPRINTK("EXIT\n");
-
 	return IRQ_RETVAL(handled);
 }
 
@@ -900,7 +854,7 @@ static int pdc_softreset(struct ata_link *link, unsigned int *class,
 
 static void pdc_error_handler(struct ata_port *ap)
 {
-	if (!(ap->pflags & ATA_PFLAG_FROZEN))
+	if (!ata_port_is_frozen(ap))
 		pdc_reset_port(ap);
 
 	ata_sff_error_handler(ap);
@@ -911,7 +865,7 @@ static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
 	struct ata_port *ap = qc->ap;
 
 	/* make DMA engine forget about the failed command */
-	if (qc->flags & ATA_QCFLAG_FAILED)
+	if (qc->flags & ATA_QCFLAG_EH)
 		pdc_reset_port(ap);
 }
 
@@ -979,7 +933,6 @@ static void pdc_sata_setup_port(struct ata_ioports *port, void __iomem *base)
 }
 
 
-#ifdef ATA_VERBOSE_DEBUG
 static void pdc20621_get_from_dimm(struct ata_host *host, void *psource,
 				   u32 offset, u32 size)
 {
@@ -1004,8 +957,7 @@ static void pdc20621_get_from_dimm(struct ata_host *host, void *psource,
 
 	offset -= (idx * window_size);
 	idx++;
-	dist = ((long) (window_size - (offset + size))) >= 0 ? size :
-		(long) (window_size - offset);
+	dist = min(size, window_size - offset);
 	memcpy_fromio(psource, dimm_mmio + offset / 4, dist);
 
 	psource += dist;
@@ -1029,7 +981,6 @@ static void pdc20621_get_from_dimm(struct ata_host *host, void *psource,
 		memcpy_fromio(psource, dimm_mmio, size / 4);
 	}
 }
-#endif
 
 
 static void pdc20621_put_to_dimm(struct ata_host *host, void *psource,
@@ -1053,8 +1004,7 @@ static void pdc20621_put_to_dimm(struct ata_host *host, void *psource,
 	readl(mmio + PDC_DIMM_WINDOW_CTLR);
 	offset -= (idx * window_size);
 	idx++;
-	dist = ((long)(s32)(window_size - (offset + size))) >= 0 ? size :
-		(long) (window_size - offset);
+	dist = min(size, window_size - offset);
 	memcpy_toio(dimm_mmio + offset / 4, psource, dist);
 	writel(0x01, mmio + PDC_GENERAL_CTLR);
 	readl(mmio + PDC_GENERAL_CTLR);
@@ -1167,9 +1117,14 @@ static int pdc20621_prog_dimm0(struct ata_host *host)
 	mmio += PDC_CHIP0_OFS;
 
 	for (i = 0; i < ARRAY_SIZE(pdc_i2c_read_data); i++)
-		pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
-				  pdc_i2c_read_data[i].reg,
-				  &spd0[pdc_i2c_read_data[i].ofs]);
+		if (!pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
+				       pdc_i2c_read_data[i].reg,
+				       &spd0[pdc_i2c_read_data[i].ofs])) {
+			dev_err(host->dev,
+				"Failed in i2c read at index %d: device=%#x, reg=%#x\n",
+				i, PDC_DIMM0_SPD_DEV_ADDRESS, pdc_i2c_read_data[i].reg);
+			return -EIO;
+		}
 
 	data |= (spd0[4] - 8) | ((spd0[21] != 0) << 3) | ((spd0[3]-11) << 4);
 	data |= ((spd0[17] / 4) << 6) | ((spd0[5] / 2) << 7) |
@@ -1226,15 +1181,16 @@ static unsigned int pdc20621_prog_dimm_global(struct ata_host *host)
 	/* Turn on for ECC */
 	if (!pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
 			       PDC_DIMM_SPD_TYPE, &spd0)) {
-		pr_err("Failed in i2c read: device=%#x, subaddr=%#x\n",
-		       PDC_DIMM0_SPD_DEV_ADDRESS, PDC_DIMM_SPD_TYPE);
+		dev_err(host->dev,
+			"Failed in i2c read: device=%#x, subaddr=%#x\n",
+			PDC_DIMM0_SPD_DEV_ADDRESS, PDC_DIMM_SPD_TYPE);
 		return 1;
 	}
 	if (spd0 == 0x02) {
 		data |= (0x01 << 16);
 		writel(data, mmio + PDC_SDRAM_CONTROL);
 		readl(mmio + PDC_SDRAM_CONTROL);
-		printk(KERN_ERR "Local DIMM ECC Enabled\n");
+		dev_err(host->dev, "Local DIMM ECC Enabled\n");
 	}
 
 	/* DIMM Initialization Select/Enable (bit 18/19) */
@@ -1274,7 +1230,7 @@ static unsigned int pdc20621_dimm_init(struct ata_host *host)
 	/* Initialize Time Period Register */
 	writel(0xffffffff, mmio + PDC_TIME_PERIOD);
 	time_period = readl(mmio + PDC_TIME_PERIOD);
-	VPRINTK("Time Period Register (0x40): 0x%x\n", time_period);
+	dev_dbg(host->dev, "Time Period Register (0x40): 0x%x\n", time_period);
 
 	/* Enable timer */
 	writel(PDC_TIMER_DEFAULT, mmio + PDC_TIME_CONTROL);
@@ -1289,7 +1245,7 @@ static unsigned int pdc20621_dimm_init(struct ata_host *host)
 	*/
 
 	tcount = readl(mmio + PDC_TIME_COUNTER);
-	VPRINTK("Time Counter Register (0x44): 0x%x\n", tcount);
+	dev_dbg(host->dev, "Time Counter Register (0x44): 0x%x\n", tcount);
 
 	/*
 	   If SX4 is on PCI-X bus, after 3 seconds, the timer counter
@@ -1297,17 +1253,19 @@ static unsigned int pdc20621_dimm_init(struct ata_host *host)
 	*/
 	if (tcount >= PCI_X_TCOUNT) {
 		ticks = (time_period - tcount);
-		VPRINTK("Num counters 0x%x (%d)\n", ticks, ticks);
+		dev_dbg(host->dev, "Num counters 0x%x (%d)\n", ticks, ticks);
 
 		clock = (ticks / 300000);
-		VPRINTK("10 * Internal clk = 0x%x (%d)\n", clock, clock);
+		dev_dbg(host->dev, "10 * Internal clk = 0x%x (%d)\n",
+			clock, clock);
 
 		clock = (clock * 33);
-		VPRINTK("10 * Internal clk * 33 = 0x%x (%d)\n", clock, clock);
+		dev_dbg(host->dev, "10 * Internal clk * 33 = 0x%x (%d)\n",
+			clock, clock);
 
 		/* PLL F Param (bit 22:16) */
 		fparam = (1400000 / clock) - 2;
-		VPRINTK("PLL F Param: 0x%x (%d)\n", fparam, fparam);
+		dev_dbg(host->dev, "PLL F Param: 0x%x (%d)\n", fparam, fparam);
 
 		/* OD param = 0x2 (bit 31:30), R param = 0x5 (bit 29:25) */
 		pci_status = (0x8a001824 | (fparam << 16));
@@ -1315,7 +1273,7 @@ static unsigned int pdc20621_dimm_init(struct ata_host *host)
 		pci_status = PCI_PLL_INIT;
 
 	/* Initialize PLL. */
-	VPRINTK("pci_status: 0x%x\n", pci_status);
+	dev_dbg(host->dev, "pci_status: 0x%x\n", pci_status);
 	writel(pci_status, mmio + PDC_CTL_STATUS);
 	readl(mmio + PDC_CTL_STATUS);
 
@@ -1324,61 +1282,65 @@ static unsigned int pdc20621_dimm_init(struct ata_host *host)
 	   and program the DIMM Module Controller.
 	*/
 	if (!(speed = pdc20621_detect_dimm(host))) {
-		printk(KERN_ERR "Detect Local DIMM Fail\n");
+		dev_err(host->dev, "Detect Local DIMM Fail\n");
 		return 1;	/* DIMM error */
 	}
-	VPRINTK("Local DIMM Speed = %d\n", speed);
+	dev_dbg(host->dev, "Local DIMM Speed = %d\n", speed);
 
 	/* Programming DIMM0 Module Control Register (index_CID0:80h) */
 	size = pdc20621_prog_dimm0(host);
-	VPRINTK("Local DIMM Size = %dMB\n", size);
+	if (size < 0)
+		return size;
+	dev_dbg(host->dev, "Local DIMM Size = %dMB\n", size);
 
 	/* Programming DIMM Module Global Control Register (index_CID0:88h) */
 	if (pdc20621_prog_dimm_global(host)) {
-		printk(KERN_ERR "Programming DIMM Module Global Control Register Fail\n");
+		dev_err(host->dev,
+			"Programming DIMM Module Global Control Register Fail\n");
 		return 1;
 	}
 
-#ifdef ATA_VERBOSE_DEBUG
-	{
-		u8 test_parttern1[40] =
+	if (dimm_test) {
+		u8 test_pattern1[40] =
 			{0x55,0xAA,'P','r','o','m','i','s','e',' ',
 			'N','o','t',' ','Y','e','t',' ',
 			'D','e','f','i','n','e','d',' ',
 			'1','.','1','0',
 			'9','8','0','3','1','6','1','2',0,0};
-		u8 test_parttern2[40] = {0};
+		u8 test_pattern2[40] = {0};
 
-		pdc20621_put_to_dimm(host, test_parttern2, 0x10040, 40);
-		pdc20621_put_to_dimm(host, test_parttern2, 0x40, 40);
+		pdc20621_put_to_dimm(host, test_pattern2, 0x10040, 40);
+		pdc20621_put_to_dimm(host, test_pattern2, 0x40, 40);
 
-		pdc20621_put_to_dimm(host, test_parttern1, 0x10040, 40);
-		pdc20621_get_from_dimm(host, test_parttern2, 0x40, 40);
-		printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
-		       test_parttern2[1], &(test_parttern2[2]));
-		pdc20621_get_from_dimm(host, test_parttern2, 0x10040,
+		pdc20621_put_to_dimm(host, test_pattern1, 0x10040, 40);
+		pdc20621_get_from_dimm(host, test_pattern2, 0x40, 40);
+		dev_info(host->dev, "DIMM test pattern 1: %x, %x, %s\n", test_pattern2[0],
+		       test_pattern2[1], &(test_pattern2[2]));
+		pdc20621_get_from_dimm(host, test_pattern2, 0x10040,
 				       40);
-		printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
-		       test_parttern2[1], &(test_parttern2[2]));
-
-		pdc20621_put_to_dimm(host, test_parttern1, 0x40, 40);
-		pdc20621_get_from_dimm(host, test_parttern2, 0x40, 40);
-		printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
-		       test_parttern2[1], &(test_parttern2[2]));
+		dev_info(host->dev, "DIMM test pattern 2: %x, %x, %s\n",
+			 test_pattern2[0],
+			 test_pattern2[1], &(test_pattern2[2]));
+
+		pdc20621_put_to_dimm(host, test_pattern1, 0x40, 40);
+		pdc20621_get_from_dimm(host, test_pattern2, 0x40, 40);
+		dev_info(host->dev, "DIMM test pattern 3: %x, %x, %s\n",
+			 test_pattern2[0],
+			 test_pattern2[1], &(test_pattern2[2]));
 	}
-#endif
 
 	/* ECC initiliazation. */
 
 	if (!pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
 			       PDC_DIMM_SPD_TYPE, &spd0)) {
-		pr_err("Failed in i2c read: device=%#x, subaddr=%#x\n",
+		dev_err(host->dev,
+			"Failed in i2c read: device=%#x, subaddr=%#x\n",
 		       PDC_DIMM0_SPD_DEV_ADDRESS, PDC_DIMM_SPD_TYPE);
 		return 1;
 	}
 	if (spd0 == 0x02) {
 		void *buf;
-		VPRINTK("Start ECC initialization\n");
+		dev_dbg(host->dev, "Start ECC initialization\n");
 		addr = 0;
 		length = size * 1024 * 1024;
 		buf = kzalloc(ECC_ERASE_BUF_SZ, GFP_KERNEL);
@@ -1390,7 +1352,7 @@ static unsigned int pdc20621_dimm_init(struct ata_host *host)
 			addr += ECC_ERASE_BUF_SZ;
 		}
 		kfree(buf);
-		VPRINTK("Finish ECC initialization\n");
+		dev_dbg(host->dev, "Finish ECC initialization\n");
 	}
 	return 0;
 }
diff --git a/drivers/ata/sata_uli.c b/drivers/ata/sata_uli.c
index 815e6af75310..44985796cc47 100644
--- a/drivers/ata/sata_uli.c
+++ b/drivers/ata/sata_uli.c
@@ -59,7 +59,7 @@ static struct pci_driver uli_pci_driver = {
 	.remove			= ata_pci_remove_one,
 };
 
-static struct scsi_host_template uli_sht = {
+static const struct scsi_host_template uli_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
@@ -67,7 +67,7 @@ static struct ata_port_operations uli_ops = {
 	.inherits		= &ata_bmdma_port_ops,
 	.scr_read		= uli_scr_read,
 	.scr_write		= uli_scr_write,
-	.hardreset		= ATA_OP_NULL,
+	.reset.hardreset	= ATA_OP_NULL,
 };
 
 static const struct ata_port_info uli_port_info = {
@@ -221,7 +221,7 @@ static int uli_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 	}
 
 	pci_set_master(pdev);
-	pci_intx(pdev, 1);
+	pcim_intx(pdev, 1);
 	return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
 				 IRQF_SHARED, &uli_sht);
 }
diff --git a/drivers/ata/sata_via.c b/drivers/ata/sata_via.c
index c7891cc84ea0..68e9003ec2d4 100644
--- a/drivers/ata/sata_via.c
+++ b/drivers/ata/sata_via.c
@@ -25,6 +25,7 @@
 #include <scsi/scsi_cmnd.h>
 #include <scsi/scsi_host.h>
 #include <linux/libata.h>
+#include <linux/string_choices.h>
 
 #define DRV_NAME	"sata_via"
 #define DRV_VERSION	"2.6"
@@ -107,7 +108,7 @@ static struct pci_driver svia_pci_driver = {
 	.remove			= ata_pci_remove_one,
 };
 
-static struct scsi_host_template svia_sht = {
+static const struct scsi_host_template svia_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
@@ -119,7 +120,7 @@ static struct ata_port_operations svia_base_ops = {
 static struct ata_port_operations vt6420_sata_ops = {
 	.inherits		= &svia_base_ops,
 	.freeze			= svia_noop_freeze,
-	.prereset		= vt6420_prereset,
+	.reset.prereset		= vt6420_prereset,
 	.bmdma_start		= vt6420_bmdma_start,
 };
 
@@ -139,7 +140,7 @@ static struct ata_port_operations vt6421_sata_ops = {
 
 static struct ata_port_operations vt8251_ops = {
 	.inherits		= &svia_base_ops,
-	.hardreset		= sata_std_hardreset,
+	.reset.hardreset	= sata_std_hardreset,
 	.scr_read		= vt8251_scr_read,
 	.scr_write		= vt8251_scr_write,
 };
@@ -359,7 +360,7 @@ static int vt6420_prereset(struct ata_link *link, unsigned long deadline)
 
 	ata_port_info(ap,
 		      "SATA link %s 1.5 Gbps (SStatus %X SControl %X)\n",
-		      online ? "up" : "down", sstatus, scontrol);
+		      str_up_down(online), sstatus, scontrol);
 
 	/* SStatus is read one more time */
 	svia_scr_read(link, SCR_STATUS, &sstatus);
diff --git a/drivers/ata/sata_vsc.c b/drivers/ata/sata_vsc.c
index 8fa952cb9f7f..a53a2dfc1e17 100644
--- a/drivers/ata/sata_vsc.c
+++ b/drivers/ata/sata_vsc.c
@@ -183,24 +183,24 @@ static void vsc_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
 static void vsc_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
 {
 	struct ata_ioports *ioaddr = &ap->ioaddr;
-	u16 nsect, lbal, lbam, lbah, feature;
+	u16 nsect, lbal, lbam, lbah, error;
 
-	tf->command = ata_sff_check_status(ap);
+	tf->status = ata_sff_check_status(ap);
 	tf->device = readw(ioaddr->device_addr);
-	feature = readw(ioaddr->error_addr);
+	error = readw(ioaddr->error_addr);
 	nsect = readw(ioaddr->nsect_addr);
 	lbal = readw(ioaddr->lbal_addr);
 	lbam = readw(ioaddr->lbam_addr);
 	lbah = readw(ioaddr->lbah_addr);
 
-	tf->feature = feature;
+	tf->error = error;
 	tf->nsect = nsect;
 	tf->lbal = lbal;
 	tf->lbam = lbam;
 	tf->lbah = lbah;
 
 	if (tf->flags & ATA_TFLAG_LBA48) {
-		tf->hob_feature = feature >> 8;
+		tf->hob_feature = error >> 8;
 		tf->hob_nsect = nsect >> 8;
 		tf->hob_lbal = lbal >> 8;
 		tf->hob_lbam = lbam >> 8;
@@ -277,7 +277,7 @@ out:
 }
 
 
-static struct scsi_host_template vsc_sata_sht = {
+static const struct scsi_host_template vsc_sata_sht = {
 	ATA_BMDMA_SHT(DRV_NAME),
 };
 
@@ -384,7 +384,7 @@ static int vsc_sata_init_one(struct pci_dev *pdev,
 		pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);
 
 	if (pci_enable_msi(pdev) == 0)
-		pci_intx(pdev, 0);
+		pcim_intx(pdev, 0);
 
 	/*
 	 * Config offset 0x98 is "Extended Control and Status Register 0"
diff --git a/drivers/atm/Kconfig b/drivers/atm/Kconfig
index 8c37294f1d1e..63cdb46a3439 100644
--- a/drivers/atm/Kconfig
+++ b/drivers/atm/Kconfig
@@ -7,7 +7,7 @@ menuconfig ATM_DRIVERS
 	bool "ATM drivers"
 	depends on NETDEVICES && ATM
 	default y
-	---help---
+	help
 	  Say Y here to get to see options for Asynchronous Transfer Mode
 	  device drivers. This option alone does not add any kernel code.
 
@@ -40,7 +40,7 @@ config ATM_LANAI
 config ATM_ENI
 	tristate "Efficient Networks ENI155P"
 	depends on PCI
-	---help---
+	help
 	  Driver for the Efficient Networks ENI155p series and SMC ATM
 	  Power155 155 Mbps ATM adapters. Both, the versions with 512KB and
 	  2MB on-board RAM (Efficient calls them "C" and "S", respectively),
@@ -64,7 +64,7 @@ config ATM_ENI_DEBUG
 config ATM_ENI_TUNE_BURST
 	bool "Fine-tune burst settings"
 	depends on ATM_ENI
-	---help---
+	help
 	  In order to obtain good throughput, the ENI NIC can transfer
 	  multiple words of data per PCI bus access cycle. Such a multi-word
 	  transfer is called a burst.
@@ -146,36 +146,6 @@ config ATM_ENI_BURST_RX_2W
 	  try this if you have disabled 4W and 8W bursts. Enabling 2W if 4W or
 	  8W are also set may or may not improve throughput.
 
-config ATM_FIRESTREAM
-	tristate "Fujitsu FireStream (FS50/FS155) "
-	depends on PCI && VIRT_TO_BUS
-	help
-	  Driver for the Fujitsu FireStream 155 (MB86697) and
-	  FireStream 50 (MB86695) ATM PCI chips.
-
-	  To compile this driver as a module, choose M here: the module will
-	  be called firestream.
-
-config ATM_ZATM
-	tristate "ZeitNet ZN1221/ZN1225"
-	depends on PCI && VIRT_TO_BUS
-	help
-	  Driver for the ZeitNet ZN1221 (MMF) and ZN1225 (UTP-5) 155 Mbps ATM
-	  adapters.
-
-	  To compile this driver as a module, choose M here: the module will
-	  be called zatm.
-
-config ATM_ZATM_DEBUG
-	bool "Enable extended debugging"
-	depends on ATM_ZATM
-	help
-	  Extended debugging records various events and displays that list
-	  when an inconsistency is detected. This mechanism is faster than
-	  generally using printks, but still has some impact on performance.
-	  Note that extended debugging may create certain race conditions
-	  itself. Enable this ONLY if you suspect problems with the driver.
-
 config ATM_NICSTAR
 	tristate "IDT 77201 (NICStAR) (ForeRunnerLE)"
 	depends on PCI
@@ -244,59 +214,10 @@ config ATM_IDT77252_USE_SUNI
 	depends on ATM_IDT77252
 	default y
 
-config ATM_AMBASSADOR
-	tristate "Madge Ambassador (Collage PCI 155 Server)"
-	depends on PCI && VIRT_TO_BUS
-	select BITREVERSE
-	help
-	  This is a driver for ATMizer based ATM card produced by Madge
-	  Networks Ltd. Say Y (or M to compile as a module named ambassador)
-	  here if you have one of these cards.
-
-config ATM_AMBASSADOR_DEBUG
-	bool "Enable debugging messages"
-	depends on ATM_AMBASSADOR
-	---help---
-	  Somewhat useful debugging messages are available. The choice of
-	  messages is controlled by a bitmap.  This may be specified as a
-	  module argument (kernel command line argument as well?), changed
-	  dynamically using an ioctl (not yet) or changed by sending the
-	  string "Dxxxx" to VCI 1023 (where x is a hex digit).  See the file
-	  <file:drivers/atm/ambassador.h> for the meanings of the bits in the
-	  mask.
-
-	  When active, these messages can have a significant impact on the
-	  speed of the driver, and the size of your syslog files! When
-	  inactive, they will have only a modest impact on performance.
-
-config ATM_HORIZON
-	tristate "Madge Horizon [Ultra] (Collage PCI 25 and Collage PCI 155 Client)"
-	depends on PCI && VIRT_TO_BUS
-	help
-	  This is a driver for the Horizon chipset ATM adapter cards once
-	  produced by Madge Networks Ltd. Say Y (or M to compile as a module
-	  named horizon) here if you have one of these cards.
-
-config ATM_HORIZON_DEBUG
-	bool "Enable debugging messages"
-	depends on ATM_HORIZON
-	---help---
-	  Somewhat useful debugging messages are available. The choice of
-	  messages is controlled by a bitmap.  This may be specified as a
-	  module argument (kernel command line argument as well?), changed
-	  dynamically using an ioctl (not yet) or changed by sending the
-	  string "Dxxxx" to VCI 1023 (where x is a hex digit).  See the file
-	  <file:drivers/atm/horizon.h> for the meanings of the bits in the
-	  mask.
-
-	  When active, these messages can have a significant impact on the
-	  speed of the driver, and the size of your syslog files! When
-	  inactive, they will have only a modest impact on performance.
-
 config ATM_IA
 	tristate "Interphase ATM PCI x575/x525/x531"
 	depends on PCI
-	---help---
+	help
 	  This is a driver for the Interphase (i)ChipSAR adapter cards
 	  which include a variety of variants in term of the size of the
 	  control memory (128K-1KVC, 512K-4KVC), the size of the packet
@@ -306,13 +227,14 @@ config ATM_IA
 	  for more info about the cards. Say Y (or M to compile as a module
 	  named iphase) here if you have one of these cards.
 
-	  See the file <file:Documentation/networking/iphase.txt> for further
-	  details.
+	  See the file
+	  <file:Documentation/networking/device_drivers/atm/iphase.rst>
+	  for further details.
 
 config ATM_IA_DEBUG
 	bool "Enable debugging messages"
 	depends on ATM_IA
-	---help---
+	help
 	  Somewhat useful debugging messages are available. The choice of
 	  messages is controlled by a bitmap. This may be specified as a
 	  module argument (kernel command line argument as well?), changed
@@ -330,13 +252,14 @@ config ATM_FORE200E
 	tristate "FORE Systems 200E-series"
 	depends on (PCI || SBUS)
 	select FW_LOADER
-	---help---
+	help
 	  This is a driver for the FORE Systems 200E-series ATM adapter
 	  cards. It simultaneously supports PCA-200E and SBA-200E models
 	  on PCI and SBUS hosts. Say Y (or M to compile as a module
 	  named fore_200e) here if you have one of these ATM adapters.
 
-	  See the file <file:Documentation/networking/fore200e.txt> for
+	  See the file
+	  <file:Documentation/networking/device_drivers/atm/fore200e.rst> for
 	  further details.
 
 config ATM_FORE200E_USE_TASKLET
@@ -352,7 +275,7 @@ config ATM_FORE200E_TX_RETRY
 	int "Maximum number of tx retries"
 	depends on ATM_FORE200E
 	default "16"
-	---help---
+	help
 	  Specifies the number of times the driver attempts to transmit
 	  a message before giving up, if the transmit queue of the ATM card
 	  is transiently saturated.
diff --git a/drivers/atm/Makefile b/drivers/atm/Makefile
index aa191616a72e..c9eade92019b 100644
--- a/drivers/atm/Makefile
+++ b/drivers/atm/Makefile
@@ -5,10 +5,7 @@
 
 fore_200e-y	:= fore200e.o
 
-obj-$(CONFIG_ATM_ZATM)		+= zatm.o uPD98402.o
 obj-$(CONFIG_ATM_NICSTAR)	+= nicstar.o
-obj-$(CONFIG_ATM_AMBASSADOR)	+= ambassador.o
-obj-$(CONFIG_ATM_HORIZON)	+= horizon.o
 obj-$(CONFIG_ATM_IA)		+= iphase.o suni.o
 obj-$(CONFIG_ATM_FORE200E)	+= fore_200e.o
 obj-$(CONFIG_ATM_ENI)		+= eni.o suni.o
@@ -27,7 +24,6 @@ endif
 
 obj-$(CONFIG_ATM_DUMMY)		+= adummy.o
 obj-$(CONFIG_ATM_TCP)		+= atmtcp.o
-obj-$(CONFIG_ATM_FIRESTREAM)	+= firestream.o
 obj-$(CONFIG_ATM_LANAI)		+= lanai.o
 
 obj-$(CONFIG_ATM_HE)		+= he.o
diff --git a/drivers/atm/ambassador.c b/drivers/atm/ambassador.c
deleted file mode 100644
index c039b8a4fefe..000000000000
--- a/drivers/atm/ambassador.c
+++ /dev/null
@@ -1,2400 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
-  Madge Ambassador ATM Adapter driver.
-  Copyright (C) 1995-1999  Madge Networks Ltd.
-
-*/
-
-/* * dedicated to the memory of Graham Gordon 1971-1998 * */
-
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/atmdev.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/poison.h>
-#include <linux/bitrev.h>
-#include <linux/mutex.h>
-#include <linux/firmware.h>
-#include <linux/ihex.h>
-#include <linux/slab.h>
-
-#include <linux/atomic.h>
-#include <asm/io.h>
-#include <asm/byteorder.h>
-
-#include "ambassador.h"
-
-#define maintainer_string "Giuliano Procida at Madge Networks <gprocida@madge.com>"
-#define description_string "Madge ATM Ambassador driver"
-#define version_string "1.2.4"
-
-static inline void __init show_version (void) {
-  printk ("%s version %s\n", description_string, version_string);
-}
-
-/*
-  
-  Theory of Operation
-  
-  I Hardware, detection, initialisation and shutdown.
-  
-  1. Supported Hardware
-  
-  This driver is for the PCI ATMizer-based Ambassador card (except
-  very early versions). It is not suitable for the similar EISA "TR7"
-  card. Commercially, both cards are known as Collage Server ATM
-  adapters.
-  
-  The loader supports image transfer to the card, image start and few
-  other miscellaneous commands.
-  
-  Only AAL5 is supported with vpi = 0 and vci in the range 0 to 1023.
-  
-  The cards are big-endian.
-  
-  2. Detection
-  
-  Standard PCI stuff, the early cards are detected and rejected.
-  
-  3. Initialisation
-  
-  The cards are reset and the self-test results are checked. The
-  microcode image is then transferred and started. This waits for a
-  pointer to a descriptor containing details of the host-based queues
-  and buffers and various parameters etc. Once they are processed
-  normal operations may begin. The BIA is read using a microcode
-  command.
-  
-  4. Shutdown
-  
-  This may be accomplished either by a card reset or via the microcode
-  shutdown command. Further investigation required.
-  
-  5. Persistent state
-  
-  The card reset does not affect PCI configuration (good) or the
-  contents of several other "shared run-time registers" (bad) which
-  include doorbell and interrupt control as well as EEPROM and PCI
-  control. The driver must be careful when modifying these registers
-  not to touch bits it does not use and to undo any changes at exit.
-  
-  II Driver software
-  
-  0. Generalities
-  
-  The adapter is quite intelligent (fast) and has a simple interface
-  (few features). VPI is always zero, 1024 VCIs are supported. There
-  is limited cell rate support. UBR channels can be capped and ABR
-  (explicit rate, but not EFCI) is supported. There is no CBR or VBR
-  support.
-  
-  1. Driver <-> Adapter Communication
-  
-  Apart from the basic loader commands, the driver communicates
-  through three entities: the command queue (CQ), the transmit queue
-  pair (TXQ) and the receive queue pairs (RXQ). These three entities
-  are set up by the host and passed to the microcode just after it has
-  been started.
-  
-  All queues are host-based circular queues. They are contiguous and
-  (due to hardware limitations) have some restrictions as to their
-  locations in (bus) memory. They are of the "full means the same as
-  empty so don't do that" variety since the adapter uses pointers
-  internally.
-  
-  The queue pairs work as follows: one queue is for supply to the
-  adapter, items in it are pending and are owned by the adapter; the
-  other is the queue for return from the adapter, items in it have
-  been dealt with by the adapter. The host adds items to the supply
-  (TX descriptors and free RX buffer descriptors) and removes items
-  from the return (TX and RX completions). The adapter deals with out
-  of order completions.
-  
-  Interrupts (card to host) and the doorbell (host to card) are used
-  for signalling.
-  
-  1. CQ
-  
-  This is to communicate "open VC", "close VC", "get stats" etc. to
-  the adapter. At most one command is retired every millisecond by the
-  card. There is no out of order completion or notification. The
-  driver needs to check the return code of the command, waiting as
-  appropriate.
-  
-  2. TXQ
-  
-  TX supply items are of variable length (scatter gather support) and
-  so the queue items are (more or less) pointers to the real thing.
-  Each TX supply item contains a unique, host-supplied handle (the skb
-  bus address seems most sensible as this works for Alphas as well,
-  there is no need to do any endian conversions on the handles).
-  
-  TX return items consist of just the handles above.
-  
-  3. RXQ (up to 4 of these with different lengths and buffer sizes)
-  
-  RX supply items consist of a unique, host-supplied handle (the skb
-  bus address again) and a pointer to the buffer data area.
-  
-  RX return items consist of the handle above, the VC, length and a
-  status word. This just screams "oh so easy" doesn't it?
-
-  Note on RX pool sizes:
-   
-  Each pool should have enough buffers to handle a back-to-back stream
-  of minimum sized frames on a single VC. For example:
-  
-    frame spacing = 3us (about right)
-    
-    delay = IRQ lat + RX handling + RX buffer replenish = 20 (us)  (a guess)
-    
-    min number of buffers for one VC = 1 + delay/spacing (buffers)
-
-    delay/spacing = latency = (20+2)/3 = 7 (buffers)  (rounding up)
-    
-  The 20us delay assumes that there is no need to sleep; if we need to
-  sleep to get buffers we are going to drop frames anyway.
-  
-  In fact, each pool should have enough buffers to support the
-  simultaneous reassembly of a separate frame on each VC and cope with
-  the case in which frames complete in round robin cell fashion on
-  each VC.
-  
-  Only one frame can complete at each cell arrival, so if "n" VCs are
-  open, the worst case is to have them all complete frames together
-  followed by all starting new frames together.
-  
-    desired number of buffers = n + delay/spacing
-    
-  These are the extreme requirements, however, they are "n+k" for some
-  "k" so we have only the constant to choose. This is the argument
-  rx_lats which current defaults to 7.
-  
-  Actually, "n ? n+k : 0" is better and this is what is implemented,
-  subject to the limit given by the pool size.
-  
-  4. Driver locking
-  
-  Simple spinlocks are used around the TX and RX queue mechanisms.
-  Anyone with a faster, working method is welcome to implement it.
-  
-  The adapter command queue is protected with a spinlock. We always
-  wait for commands to complete.
-  
-  A more complex form of locking is used around parts of the VC open
-  and close functions. There are three reasons for a lock: 1. we need
-  to do atomic rate reservation and release (not used yet), 2. Opening
-  sometimes involves two adapter commands which must not be separated
-  by another command on the same VC, 3. the changes to RX pool size
-  must be atomic. The lock needs to work over context switches, so we
-  use a semaphore.
-  
-  III Hardware Features and Microcode Bugs
-  
-  1. Byte Ordering
-  
-  *%^"$&%^$*&^"$(%^$#&^%$(&#%$*(&^#%!"!"!*!
-  
-  2. Memory access
-  
-  All structures that are not accessed using DMA must be 4-byte
-  aligned (not a problem) and must not cross 4MB boundaries.
-  
-  There is a DMA memory hole at E0000000-E00000FF (groan).
-  
-  TX fragments (DMA read) must not cross 4MB boundaries (would be 16MB
-  but for a hardware bug).
-  
-  RX buffers (DMA write) must not cross 16MB boundaries and must
-  include spare trailing bytes up to the next 4-byte boundary; they
-  will be written with rubbish.
-  
-  The PLX likes to prefetch; if reading up to 4 u32 past the end of
-  each TX fragment is not a problem, then TX can be made to go a
-  little faster by passing a flag at init that disables a prefetch
-  workaround. We do not pass this flag. (new microcode only)
-  
-  Now we:
-  . Note that alloc_skb rounds up size to a 16byte boundary.  
-  . Ensure all areas do not traverse 4MB boundaries.
-  . Ensure all areas do not start at a E00000xx bus address.
-  (I cannot be certain, but this may always hold with Linux)
-  . Make all failures cause a loud message.
-  . Discard non-conforming SKBs (causes TX failure or RX fill delay).
-  . Discard non-conforming TX fragment descriptors (the TX fails).
-  In the future we could:
-  . Allow RX areas that traverse 4MB (but not 16MB) boundaries.
-  . Segment TX areas into some/more fragments, when necessary.
-  . Relax checks for non-DMA items (ignore hole).
-  . Give scatter-gather (iovec) requirements using ???. (?)
-  
-  3. VC close is broken (only for new microcode)
-  
-  The VC close adapter microcode command fails to do anything if any
-  frames have been received on the VC but none have been transmitted.
-  Frames continue to be reassembled and passed (with IRQ) to the
-  driver.
-  
-  IV To Do List
-  
-  . Fix bugs!
-  
-  . Timer code may be broken.
-  
-  . Deal with buggy VC close (somehow) in microcode 12.
-  
-  . Handle interrupted and/or non-blocking writes - is this a job for
-    the protocol layer?
-  
-  . Add code to break up TX fragments when they span 4MB boundaries.
-  
-  . Add SUNI phy layer (need to know where SUNI lives on card).
-  
-  . Implement a tx_alloc fn to (a) satisfy TX alignment etc. and (b)
-    leave extra headroom space for Ambassador TX descriptors.
-  
-  . Understand these elements of struct atm_vcc: recvq (proto?),
-    sleep, callback, listenq, backlog_quota, reply and user_back.
-  
-  . Adjust TX/RX skb allocation to favour IP with LANE/CLIP (configurable).
-  
-  . Impose a TX-pending limit (2?) on each VC, help avoid TX q overflow.
-  
-  . Decide whether RX buffer recycling is or can be made completely safe;
-    turn it back on. It looks like Werner is going to axe this.
-  
-  . Implement QoS changes on open VCs (involves extracting parts of VC open
-    and close into separate functions and using them to make changes).
-  
-  . Hack on command queue so that someone can issue multiple commands and wait
-    on the last one (OR only "no-op" or "wait" commands are waited for).
-  
-  . Eliminate need for while-schedule around do_command.
-  
-*/
-
-static void do_housekeeping (struct timer_list *t);
-/********** globals **********/
-
-static unsigned short debug = 0;
-static unsigned int cmds = 8;
-static unsigned int txs = 32;
-static unsigned int rxs[NUM_RX_POOLS] = { 64, 64, 64, 64 };
-static unsigned int rxs_bs[NUM_RX_POOLS] = { 4080, 12240, 36720, 65535 };
-static unsigned int rx_lats = 7;
-static unsigned char pci_lat = 0;
-
-static const unsigned long onegigmask = -1 << 30;
-
-/********** access to adapter **********/
-
-static inline void wr_plain (const amb_dev * dev, size_t addr, u32 data) {
-  PRINTD (DBG_FLOW|DBG_REGS, "wr: %08zx <- %08x", addr, data);
-#ifdef AMB_MMIO
-  dev->membase[addr / sizeof(u32)] = data;
-#else
-  outl (data, dev->iobase + addr);
-#endif
-}
-
-static inline u32 rd_plain (const amb_dev * dev, size_t addr) {
-#ifdef AMB_MMIO
-  u32 data = dev->membase[addr / sizeof(u32)];
-#else
-  u32 data = inl (dev->iobase + addr);
-#endif
-  PRINTD (DBG_FLOW|DBG_REGS, "rd: %08zx -> %08x", addr, data);
-  return data;
-}
-
-static inline void wr_mem (const amb_dev * dev, size_t addr, u32 data) {
-  __be32 be = cpu_to_be32 (data);
-  PRINTD (DBG_FLOW|DBG_REGS, "wr: %08zx <- %08x b[%08x]", addr, data, be);
-#ifdef AMB_MMIO
-  dev->membase[addr / sizeof(u32)] = be;
-#else
-  outl (be, dev->iobase + addr);
-#endif
-}
-
-static inline u32 rd_mem (const amb_dev * dev, size_t addr) {
-#ifdef AMB_MMIO
-  __be32 be = dev->membase[addr / sizeof(u32)];
-#else
-  __be32 be = inl (dev->iobase + addr);
-#endif
-  u32 data = be32_to_cpu (be);
-  PRINTD (DBG_FLOW|DBG_REGS, "rd: %08zx -> %08x b[%08x]", addr, data, be);
-  return data;
-}
-
-/********** dump routines **********/
-
-static inline void dump_registers (const amb_dev * dev) {
-#ifdef DEBUG_AMBASSADOR
-  if (debug & DBG_REGS) {
-    size_t i;
-    PRINTD (DBG_REGS, "reading PLX control: ");
-    for (i = 0x00; i < 0x30; i += sizeof(u32))
-      rd_mem (dev, i);
-    PRINTD (DBG_REGS, "reading mailboxes: ");
-    for (i = 0x40; i < 0x60; i += sizeof(u32))
-      rd_mem (dev, i);
-    PRINTD (DBG_REGS, "reading doorb irqev irqen reset:");
-    for (i = 0x60; i < 0x70; i += sizeof(u32))
-      rd_mem (dev, i);
-  }
-#else
-  (void) dev;
-#endif
-  return;
-}
-
-static inline void dump_loader_block (volatile loader_block * lb) {
-#ifdef DEBUG_AMBASSADOR
-  unsigned int i;
-  PRINTDB (DBG_LOAD, "lb @ %p; res: %d, cmd: %d, pay:",
-	   lb, be32_to_cpu (lb->result), be32_to_cpu (lb->command));
-  for (i = 0; i < MAX_COMMAND_DATA; ++i)
-    PRINTDM (DBG_LOAD, " %08x", be32_to_cpu (lb->payload.data[i]));
-  PRINTDE (DBG_LOAD, ", vld: %08x", be32_to_cpu (lb->valid));
-#else
-  (void) lb;
-#endif
-  return;
-}
-
-static inline void dump_command (command * cmd) {
-#ifdef DEBUG_AMBASSADOR
-  unsigned int i;
-  PRINTDB (DBG_CMD, "cmd @ %p, req: %08x, pars:",
-	   cmd, /*be32_to_cpu*/ (cmd->request));
-  for (i = 0; i < 3; ++i)
-    PRINTDM (DBG_CMD, " %08x", /*be32_to_cpu*/ (cmd->args.par[i]));
-  PRINTDE (DBG_CMD, "");
-#else
-  (void) cmd;
-#endif
-  return;
-}
-
-static inline void dump_skb (char * prefix, unsigned int vc, struct sk_buff * skb) {
-#ifdef DEBUG_AMBASSADOR
-  unsigned int i;
-  unsigned char * data = skb->data;
-  PRINTDB (DBG_DATA, "%s(%u) ", prefix, vc);
-  for (i=0; i<skb->len && i < 256;i++)
-    PRINTDM (DBG_DATA, "%02x ", data[i]);
-  PRINTDE (DBG_DATA,"");
-#else
-  (void) prefix;
-  (void) vc;
-  (void) skb;
-#endif
-  return;
-}
-
-/********** check memory areas for use by Ambassador **********/
-
-/* see limitations under Hardware Features */
-
-static int check_area (void * start, size_t length) {
-  // assumes length > 0
-  const u32 fourmegmask = -1 << 22;
-  const u32 twofivesixmask = -1 << 8;
-  const u32 starthole = 0xE0000000;
-  u32 startaddress = virt_to_bus (start);
-  u32 lastaddress = startaddress+length-1;
-  if ((startaddress ^ lastaddress) & fourmegmask ||
-      (startaddress & twofivesixmask) == starthole) {
-    PRINTK (KERN_ERR, "check_area failure: [%x,%x] - mail maintainer!",
-	    startaddress, lastaddress);
-    return -1;
-  } else {
-    return 0;
-  }
-}
-
-/********** free an skb (as per ATM device driver documentation) **********/
-
-static void amb_kfree_skb (struct sk_buff * skb) {
-  if (ATM_SKB(skb)->vcc->pop) {
-    ATM_SKB(skb)->vcc->pop (ATM_SKB(skb)->vcc, skb);
-  } else {
-    dev_kfree_skb_any (skb);
-  }
-}
-
-/********** TX completion **********/
-
-static void tx_complete (amb_dev * dev, tx_out * tx) {
-  tx_simple * tx_descr = bus_to_virt (tx->handle);
-  struct sk_buff * skb = tx_descr->skb;
-  
-  PRINTD (DBG_FLOW|DBG_TX, "tx_complete %p %p", dev, tx);
-  
-  // VC layer stats
-  atomic_inc(&ATM_SKB(skb)->vcc->stats->tx);
-  
-  // free the descriptor
-  kfree (tx_descr);
-  
-  // free the skb
-  amb_kfree_skb (skb);
-  
-  dev->stats.tx_ok++;
-  return;
-}
-
-/********** RX completion **********/
-
-static void rx_complete (amb_dev * dev, rx_out * rx) {
-  struct sk_buff * skb = bus_to_virt (rx->handle);
-  u16 vc = be16_to_cpu (rx->vc);
-  // unused: u16 lec_id = be16_to_cpu (rx->lec_id);
-  u16 status = be16_to_cpu (rx->status);
-  u16 rx_len = be16_to_cpu (rx->length);
-  
-  PRINTD (DBG_FLOW|DBG_RX, "rx_complete %p %p (len=%hu)", dev, rx, rx_len);
-  
-  // XXX move this in and add to VC stats ???
-  if (!status) {
-    struct atm_vcc * atm_vcc = dev->rxer[vc];
-    dev->stats.rx.ok++;
-    
-    if (atm_vcc) {
-      
-      if (rx_len <= atm_vcc->qos.rxtp.max_sdu) {
-	
-	if (atm_charge (atm_vcc, skb->truesize)) {
-	  
-	  // prepare socket buffer
-	  ATM_SKB(skb)->vcc = atm_vcc;
-	  skb_put (skb, rx_len);
-	  
-	  dump_skb ("<<<", vc, skb);
-	  
-	  // VC layer stats
-	  atomic_inc(&atm_vcc->stats->rx);
-	  __net_timestamp(skb);
-	  // end of our responsibility
-	  atm_vcc->push (atm_vcc, skb);
-	  return;
-	  
-	} else {
-	  // someone fix this (message), please!
-	  PRINTD (DBG_INFO|DBG_RX, "dropped thanks to atm_charge (vc %hu, truesize %u)", vc, skb->truesize);
-	  // drop stats incremented in atm_charge
-	}
-	
-      } else {
-      	PRINTK (KERN_INFO, "dropped over-size frame");
-	// should we count this?
-	atomic_inc(&atm_vcc->stats->rx_drop);
-      }
-      
-    } else {
-      PRINTD (DBG_WARN|DBG_RX, "got frame but RX closed for channel %hu", vc);
-      // this is an adapter bug, only in new version of microcode
-    }
-    
-  } else {
-    dev->stats.rx.error++;
-    if (status & CRC_ERR)
-      dev->stats.rx.badcrc++;
-    if (status & LEN_ERR)
-      dev->stats.rx.toolong++;
-    if (status & ABORT_ERR)
-      dev->stats.rx.aborted++;
-    if (status & UNUSED_ERR)
-      dev->stats.rx.unused++;
-  }
-  
-  dev_kfree_skb_any (skb);
-  return;
-}
-
-/*
-  
-  Note on queue handling.
-  
-  Here "give" and "take" refer to queue entries and a queue (pair)
-  rather than frames to or from the host or adapter. Empty frame
-  buffers are given to the RX queue pair and returned unused or
-  containing RX frames. TX frames (well, pointers to TX fragment
-  lists) are given to the TX queue pair, completions are returned.
-  
-*/
-
-/********** command queue **********/
-
-// I really don't like this, but it's the best I can do at the moment
-
-// also, the callers are responsible for byte order as the microcode
-// sometimes does 16-bit accesses (yuk yuk yuk)
-
-static int command_do (amb_dev * dev, command * cmd) {
-  amb_cq * cq = &dev->cq;
-  volatile amb_cq_ptrs * ptrs = &cq->ptrs;
-  command * my_slot;
-  
-  PRINTD (DBG_FLOW|DBG_CMD, "command_do %p", dev);
-  
-  if (test_bit (dead, &dev->flags))
-    return 0;
-  
-  spin_lock (&cq->lock);
-  
-  // if not full...
-  if (cq->pending < cq->maximum) {
-    // remember my slot for later
-    my_slot = ptrs->in;
-    PRINTD (DBG_CMD, "command in slot %p", my_slot);
-    
-    dump_command (cmd);
-    
-    // copy command in
-    *ptrs->in = *cmd;
-    cq->pending++;
-    ptrs->in = NEXTQ (ptrs->in, ptrs->start, ptrs->limit);
-    
-    // mail the command
-    wr_mem (dev, offsetof(amb_mem, mb.adapter.cmd_address), virt_to_bus (ptrs->in));
-    
-    if (cq->pending > cq->high)
-      cq->high = cq->pending;
-    spin_unlock (&cq->lock);
-    
-    // these comments were in a while-loop before, msleep removes the loop
-    // go to sleep
-    // PRINTD (DBG_CMD, "wait: sleeping %lu for command", timeout);
-    msleep(cq->pending);
-    
-    // wait for my slot to be reached (all waiters are here or above, until...)
-    while (ptrs->out != my_slot) {
-      PRINTD (DBG_CMD, "wait: command slot (now at %p)", ptrs->out);
-      set_current_state(TASK_UNINTERRUPTIBLE);
-      schedule();
-    }
-    
-    // wait on my slot (... one gets to its slot, and... )
-    while (ptrs->out->request != cpu_to_be32 (SRB_COMPLETE)) {
-      PRINTD (DBG_CMD, "wait: command slot completion");
-      set_current_state(TASK_UNINTERRUPTIBLE);
-      schedule();
-    }
-    
-    PRINTD (DBG_CMD, "command complete");
-    // update queue (... moves the queue along to the next slot)
-    spin_lock (&cq->lock);
-    cq->pending--;
-    // copy command out
-    *cmd = *ptrs->out;
-    ptrs->out = NEXTQ (ptrs->out, ptrs->start, ptrs->limit);
-    spin_unlock (&cq->lock);
-    
-    return 0;
-  } else {
-    cq->filled++;
-    spin_unlock (&cq->lock);
-    return -EAGAIN;
-  }
-  
-}
-
-/********** TX queue pair **********/
-
-static int tx_give (amb_dev * dev, tx_in * tx) {
-  amb_txq * txq = &dev->txq;
-  unsigned long flags;
-  
-  PRINTD (DBG_FLOW|DBG_TX, "tx_give %p", dev);
-
-  if (test_bit (dead, &dev->flags))
-    return 0;
-  
-  spin_lock_irqsave (&txq->lock, flags);
-  
-  if (txq->pending < txq->maximum) {
-    PRINTD (DBG_TX, "TX in slot %p", txq->in.ptr);
-
-    *txq->in.ptr = *tx;
-    txq->pending++;
-    txq->in.ptr = NEXTQ (txq->in.ptr, txq->in.start, txq->in.limit);
-    // hand over the TX and ring the bell
-    wr_mem (dev, offsetof(amb_mem, mb.adapter.tx_address), virt_to_bus (txq->in.ptr));
-    wr_mem (dev, offsetof(amb_mem, doorbell), TX_FRAME);
-    
-    if (txq->pending > txq->high)
-      txq->high = txq->pending;
-    spin_unlock_irqrestore (&txq->lock, flags);
-    return 0;
-  } else {
-    txq->filled++;
-    spin_unlock_irqrestore (&txq->lock, flags);
-    return -EAGAIN;
-  }
-}
-
-static int tx_take (amb_dev * dev) {
-  amb_txq * txq = &dev->txq;
-  unsigned long flags;
-  
-  PRINTD (DBG_FLOW|DBG_TX, "tx_take %p", dev);
-  
-  spin_lock_irqsave (&txq->lock, flags);
-  
-  if (txq->pending && txq->out.ptr->handle) {
-    // deal with TX completion
-    tx_complete (dev, txq->out.ptr);
-    // mark unused again
-    txq->out.ptr->handle = 0;
-    // remove item
-    txq->pending--;
-    txq->out.ptr = NEXTQ (txq->out.ptr, txq->out.start, txq->out.limit);
-    
-    spin_unlock_irqrestore (&txq->lock, flags);
-    return 0;
-  } else {
-    
-    spin_unlock_irqrestore (&txq->lock, flags);
-    return -1;
-  }
-}
-
-/********** RX queue pairs **********/
-
-static int rx_give (amb_dev * dev, rx_in * rx, unsigned char pool) {
-  amb_rxq * rxq = &dev->rxq[pool];
-  unsigned long flags;
-  
-  PRINTD (DBG_FLOW|DBG_RX, "rx_give %p[%hu]", dev, pool);
-  
-  spin_lock_irqsave (&rxq->lock, flags);
-  
-  if (rxq->pending < rxq->maximum) {
-    PRINTD (DBG_RX, "RX in slot %p", rxq->in.ptr);
-
-    *rxq->in.ptr = *rx;
-    rxq->pending++;
-    rxq->in.ptr = NEXTQ (rxq->in.ptr, rxq->in.start, rxq->in.limit);
-    // hand over the RX buffer
-    wr_mem (dev, offsetof(amb_mem, mb.adapter.rx_address[pool]), virt_to_bus (rxq->in.ptr));
-    
-    spin_unlock_irqrestore (&rxq->lock, flags);
-    return 0;
-  } else {
-    spin_unlock_irqrestore (&rxq->lock, flags);
-    return -1;
-  }
-}
-
-static int rx_take (amb_dev * dev, unsigned char pool) {
-  amb_rxq * rxq = &dev->rxq[pool];
-  unsigned long flags;
-  
-  PRINTD (DBG_FLOW|DBG_RX, "rx_take %p[%hu]", dev, pool);
-  
-  spin_lock_irqsave (&rxq->lock, flags);
-  
-  if (rxq->pending && (rxq->out.ptr->status || rxq->out.ptr->length)) {
-    // deal with RX completion
-    rx_complete (dev, rxq->out.ptr);
-    // mark unused again
-    rxq->out.ptr->status = 0;
-    rxq->out.ptr->length = 0;
-    // remove item
-    rxq->pending--;
-    rxq->out.ptr = NEXTQ (rxq->out.ptr, rxq->out.start, rxq->out.limit);
-    
-    if (rxq->pending < rxq->low)
-      rxq->low = rxq->pending;
-    spin_unlock_irqrestore (&rxq->lock, flags);
-    return 0;
-  } else {
-    if (!rxq->pending && rxq->buffers_wanted)
-      rxq->emptied++;
-    spin_unlock_irqrestore (&rxq->lock, flags);
-    return -1;
-  }
-}
-
-/********** RX Pool handling **********/
-
-/* pre: buffers_wanted = 0, post: pending = 0 */
-static void drain_rx_pool (amb_dev * dev, unsigned char pool) {
-  amb_rxq * rxq = &dev->rxq[pool];
-  
-  PRINTD (DBG_FLOW|DBG_POOL, "drain_rx_pool %p %hu", dev, pool);
-  
-  if (test_bit (dead, &dev->flags))
-    return;
-  
-  /* we are not quite like the fill pool routines as we cannot just
-     remove one buffer, we have to remove all of them, but we might as
-     well pretend... */
-  if (rxq->pending > rxq->buffers_wanted) {
-    command cmd;
-    cmd.request = cpu_to_be32 (SRB_FLUSH_BUFFER_Q);
-    cmd.args.flush.flags = cpu_to_be32 (pool << SRB_POOL_SHIFT);
-    while (command_do (dev, &cmd))
-      schedule();
-    /* the pool may also be emptied via the interrupt handler */
-    while (rxq->pending > rxq->buffers_wanted)
-      if (rx_take (dev, pool))
-	schedule();
-  }
-  
-  return;
-}
-
-static void drain_rx_pools (amb_dev * dev) {
-  unsigned char pool;
-  
-  PRINTD (DBG_FLOW|DBG_POOL, "drain_rx_pools %p", dev);
-  
-  for (pool = 0; pool < NUM_RX_POOLS; ++pool)
-    drain_rx_pool (dev, pool);
-}
-
-static void fill_rx_pool (amb_dev * dev, unsigned char pool,
-                                 gfp_t priority)
-{
-  rx_in rx;
-  amb_rxq * rxq;
-  
-  PRINTD (DBG_FLOW|DBG_POOL, "fill_rx_pool %p %hu %x", dev, pool, priority);
-  
-  if (test_bit (dead, &dev->flags))
-    return;
-  
-  rxq = &dev->rxq[pool];
-  while (rxq->pending < rxq->maximum && rxq->pending < rxq->buffers_wanted) {
-    
-    struct sk_buff * skb = alloc_skb (rxq->buffer_size, priority);
-    if (!skb) {
-      PRINTD (DBG_SKB|DBG_POOL, "failed to allocate skb for RX pool %hu", pool);
-      return;
-    }
-    if (check_area (skb->data, skb->truesize)) {
-      dev_kfree_skb_any (skb);
-      return;
-    }
-    // cast needed as there is no %? for pointer differences
-    PRINTD (DBG_SKB, "allocated skb at %p, head %p, area %li",
-	    skb, skb->head, (long) skb_end_offset(skb));
-    rx.handle = virt_to_bus (skb);
-    rx.host_address = cpu_to_be32 (virt_to_bus (skb->data));
-    if (rx_give (dev, &rx, pool))
-      dev_kfree_skb_any (skb);
-    
-  }
-  
-  return;
-}
-
-// top up all RX pools
-static void fill_rx_pools (amb_dev * dev) {
-  unsigned char pool;
-  
-  PRINTD (DBG_FLOW|DBG_POOL, "fill_rx_pools %p", dev);
-  
-  for (pool = 0; pool < NUM_RX_POOLS; ++pool)
-    fill_rx_pool (dev, pool, GFP_ATOMIC);
-  
-  return;
-}
-
-/********** enable host interrupts **********/
-
-static void interrupts_on (amb_dev * dev) {
-  wr_plain (dev, offsetof(amb_mem, interrupt_control),
-	    rd_plain (dev, offsetof(amb_mem, interrupt_control))
-	    | AMB_INTERRUPT_BITS);
-}
-
-/********** disable host interrupts **********/
-
-static void interrupts_off (amb_dev * dev) {
-  wr_plain (dev, offsetof(amb_mem, interrupt_control),
-	    rd_plain (dev, offsetof(amb_mem, interrupt_control))
-	    &~ AMB_INTERRUPT_BITS);
-}
-
-/********** interrupt handling **********/
-
-static irqreturn_t interrupt_handler(int irq, void *dev_id) {
-  amb_dev * dev = dev_id;
-  
-  PRINTD (DBG_IRQ|DBG_FLOW, "interrupt_handler: %p", dev_id);
-  
-  {
-    u32 interrupt = rd_plain (dev, offsetof(amb_mem, interrupt));
-  
-    // for us or someone else sharing the same interrupt
-    if (!interrupt) {
-      PRINTD (DBG_IRQ, "irq not for me: %d", irq);
-      return IRQ_NONE;
-    }
-    
-    // definitely for us
-    PRINTD (DBG_IRQ, "FYI: interrupt was %08x", interrupt);
-    wr_plain (dev, offsetof(amb_mem, interrupt), -1);
-  }
-  
-  {
-    unsigned int irq_work = 0;
-    unsigned char pool;
-    for (pool = 0; pool < NUM_RX_POOLS; ++pool)
-      while (!rx_take (dev, pool))
-	++irq_work;
-    while (!tx_take (dev))
-      ++irq_work;
-  
-    if (irq_work) {
-      fill_rx_pools (dev);
-
-      PRINTD (DBG_IRQ, "work done: %u", irq_work);
-    } else {
-      PRINTD (DBG_IRQ|DBG_WARN, "no work done");
-    }
-  }
-  
-  PRINTD (DBG_IRQ|DBG_FLOW, "interrupt_handler done: %p", dev_id);
-  return IRQ_HANDLED;
-}
-
-/********** make rate (not quite as much fun as Horizon) **********/
-
-static int make_rate (unsigned int rate, rounding r,
-		      u16 * bits, unsigned int * actual) {
-  unsigned char exp = -1; // hush gcc
-  unsigned int man = -1;  // hush gcc
-  
-  PRINTD (DBG_FLOW|DBG_QOS, "make_rate %u", rate);
-  
-  // rates in cells per second, ITU format (nasty 16-bit floating-point)
-  // given 5-bit e and 9-bit m:
-  // rate = EITHER (1+m/2^9)*2^e    OR 0
-  // bits = EITHER 1<<14 | e<<9 | m OR 0
-  // (bit 15 is "reserved", bit 14 "non-zero")
-  // smallest rate is 0 (special representation)
-  // largest rate is (1+511/512)*2^31 = 4290772992 (< 2^32-1)
-  // smallest non-zero rate is (1+0/512)*2^0 = 1 (> 0)
-  // simple algorithm:
-  // find position of top bit, this gives e
-  // remove top bit and shift (rounding if feeling clever) by 9-e
-  
-  // ucode bug: please don't set bit 14! so 0 rate not representable
-  
-  if (rate > 0xffc00000U) {
-    // larger than largest representable rate
-    
-    if (r == round_up) {
-	return -EINVAL;
-    } else {
-      exp = 31;
-      man = 511;
-    }
-    
-  } else if (rate) {
-    // representable rate
-    
-    exp = 31;
-    man = rate;
-    
-    // invariant: rate = man*2^(exp-31)
-    while (!(man & (1<<31))) {
-      exp = exp - 1;
-      man = man<<1;
-    }
-    
-    // man has top bit set
-    // rate = (2^31+(man-2^31))*2^(exp-31)
-    // rate = (1+(man-2^31)/2^31)*2^exp
-    man = man<<1;
-    man &= 0xffffffffU; // a nop on 32-bit systems
-    // rate = (1+man/2^32)*2^exp
-    
-    // exp is in the range 0 to 31, man is in the range 0 to 2^32-1
-    // time to lose significance... we want m in the range 0 to 2^9-1
-    // rounding presents a minor problem... we first decide which way
-    // we are rounding (based on given rounding direction and possibly
-    // the bits of the mantissa that are to be discarded).
-    
-    switch (r) {
-      case round_down: {
-	// just truncate
-	man = man>>(32-9);
-	break;
-      }
-      case round_up: {
-	// check all bits that we are discarding
-	if (man & (~0U>>9)) {
-	  man = (man>>(32-9)) + 1;
-	  if (man == (1<<9)) {
-	    // no need to check for round up outside of range
-	    man = 0;
-	    exp += 1;
-	  }
-	} else {
-	  man = (man>>(32-9));
-	}
-	break;
-      }
-      case round_nearest: {
-	// check msb that we are discarding
-	if (man & (1<<(32-9-1))) {
-	  man = (man>>(32-9)) + 1;
-	  if (man == (1<<9)) {
-	    // no need to check for round up outside of range
-	    man = 0;
-	    exp += 1;
-	  }
-	} else {
-	  man = (man>>(32-9));
-	}
-	break;
-      }
-    }
-    
-  } else {
-    // zero rate - not representable
-    
-    if (r == round_down) {
-      return -EINVAL;
-    } else {
-      exp = 0;
-      man = 0;
-    }
-    
-  }
-  
-  PRINTD (DBG_QOS, "rate: man=%u, exp=%hu", man, exp);
-  
-  if (bits)
-    *bits = /* (1<<14) | */ (exp<<9) | man;
-  
-  if (actual)
-    *actual = (exp >= 9)
-      ? (1 << exp) + (man << (exp-9))
-      : (1 << exp) + ((man + (1<<(9-exp-1))) >> (9-exp));
-  
-  return 0;
-}
-
-/********** Linux ATM Operations **********/
-
-// some are not yet implemented while others do not make sense for
-// this device
-
-/********** Open a VC **********/
-
-static int amb_open (struct atm_vcc * atm_vcc)
-{
-  int error;
-  
-  struct atm_qos * qos;
-  struct atm_trafprm * txtp;
-  struct atm_trafprm * rxtp;
-  u16 tx_rate_bits = -1; // hush gcc
-  u16 tx_vc_bits = -1; // hush gcc
-  u16 tx_frame_bits = -1; // hush gcc
-  
-  amb_dev * dev = AMB_DEV(atm_vcc->dev);
-  amb_vcc * vcc;
-  unsigned char pool = -1; // hush gcc
-  short vpi = atm_vcc->vpi;
-  int vci = atm_vcc->vci;
-  
-  PRINTD (DBG_FLOW|DBG_VCC, "amb_open %x %x", vpi, vci);
-  
-#ifdef ATM_VPI_UNSPEC
-  // UNSPEC is deprecated, remove this code eventually
-  if (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC) {
-    PRINTK (KERN_WARNING, "rejecting open with unspecified VPI/VCI (deprecated)");
-    return -EINVAL;
-  }
-#endif
-  
-  if (!(0 <= vpi && vpi < (1<<NUM_VPI_BITS) &&
-	0 <= vci && vci < (1<<NUM_VCI_BITS))) {
-    PRINTD (DBG_WARN|DBG_VCC, "VPI/VCI out of range: %hd/%d", vpi, vci);
-    return -EINVAL;
-  }
-  
-  qos = &atm_vcc->qos;
-  
-  if (qos->aal != ATM_AAL5) {
-    PRINTD (DBG_QOS, "AAL not supported");
-    return -EINVAL;
-  }
-  
-  // traffic parameters
-  
-  PRINTD (DBG_QOS, "TX:");
-  txtp = &qos->txtp;
-  if (txtp->traffic_class != ATM_NONE) {
-    switch (txtp->traffic_class) {
-      case ATM_UBR: {
-	// we take "the PCR" as a rate-cap
-	int pcr = atm_pcr_goal (txtp);
-	if (!pcr) {
-	  // no rate cap
-	  tx_rate_bits = 0;
-	  tx_vc_bits = TX_UBR;
-	  tx_frame_bits = TX_FRAME_NOTCAP;
-	} else {
-	  rounding r;
-	  if (pcr < 0) {
-	    r = round_down;
-	    pcr = -pcr;
-	  } else {
-	    r = round_up;
-	  }
-	  error = make_rate (pcr, r, &tx_rate_bits, NULL);
-	  if (error)
-	    return error;
-	  tx_vc_bits = TX_UBR_CAPPED;
-	  tx_frame_bits = TX_FRAME_CAPPED;
-	}
-	break;
-      }
-#if 0
-      case ATM_ABR: {
-	pcr = atm_pcr_goal (txtp);
-	PRINTD (DBG_QOS, "pcr goal = %d", pcr);
-	break;
-      }
-#endif
-      default: {
-	// PRINTD (DBG_QOS, "request for non-UBR/ABR denied");
-	PRINTD (DBG_QOS, "request for non-UBR denied");
-	return -EINVAL;
-      }
-    }
-    PRINTD (DBG_QOS, "tx_rate_bits=%hx, tx_vc_bits=%hx",
-	    tx_rate_bits, tx_vc_bits);
-  }
-  
-  PRINTD (DBG_QOS, "RX:");
-  rxtp = &qos->rxtp;
-  if (rxtp->traffic_class == ATM_NONE) {
-    // do nothing
-  } else {
-    // choose an RX pool (arranged in increasing size)
-    for (pool = 0; pool < NUM_RX_POOLS; ++pool)
-      if ((unsigned int) rxtp->max_sdu <= dev->rxq[pool].buffer_size) {
-	PRINTD (DBG_VCC|DBG_QOS|DBG_POOL, "chose pool %hu (max_sdu %u <= %u)",
-		pool, rxtp->max_sdu, dev->rxq[pool].buffer_size);
-	break;
-      }
-    if (pool == NUM_RX_POOLS) {
-      PRINTD (DBG_WARN|DBG_VCC|DBG_QOS|DBG_POOL,
-	      "no pool suitable for VC (RX max_sdu %d is too large)",
-	      rxtp->max_sdu);
-      return -EINVAL;
-    }
-    
-    switch (rxtp->traffic_class) {
-      case ATM_UBR: {
-	break;
-      }
-#if 0
-      case ATM_ABR: {
-	pcr = atm_pcr_goal (rxtp);
-	PRINTD (DBG_QOS, "pcr goal = %d", pcr);
-	break;
-      }
-#endif
-      default: {
-	// PRINTD (DBG_QOS, "request for non-UBR/ABR denied");
-	PRINTD (DBG_QOS, "request for non-UBR denied");
-	return -EINVAL;
-      }
-    }
-  }
-  
-  // get space for our vcc stuff
-  vcc = kmalloc (sizeof(amb_vcc), GFP_KERNEL);
-  if (!vcc) {
-    PRINTK (KERN_ERR, "out of memory!");
-    return -ENOMEM;
-  }
-  atm_vcc->dev_data = (void *) vcc;
-  
-  // no failures beyond this point
-  
-  // we are not really "immediately before allocating the connection
-  // identifier in hardware", but it will just have to do!
-  set_bit(ATM_VF_ADDR,&atm_vcc->flags);
-  
-  if (txtp->traffic_class != ATM_NONE) {
-    command cmd;
-    
-    vcc->tx_frame_bits = tx_frame_bits;
-    
-    mutex_lock(&dev->vcc_sf);
-    if (dev->rxer[vci]) {
-      // RXer on the channel already, just modify rate...
-      cmd.request = cpu_to_be32 (SRB_MODIFY_VC_RATE);
-      cmd.args.modify_rate.vc = cpu_to_be32 (vci);  // vpi 0
-      cmd.args.modify_rate.rate = cpu_to_be32 (tx_rate_bits << SRB_RATE_SHIFT);
-      while (command_do (dev, &cmd))
-	schedule();
-      // ... and TX flags, preserving the RX pool
-      cmd.request = cpu_to_be32 (SRB_MODIFY_VC_FLAGS);
-      cmd.args.modify_flags.vc = cpu_to_be32 (vci);  // vpi 0
-      cmd.args.modify_flags.flags = cpu_to_be32
-	( (AMB_VCC(dev->rxer[vci])->rx_info.pool << SRB_POOL_SHIFT)
-	  | (tx_vc_bits << SRB_FLAGS_SHIFT) );
-      while (command_do (dev, &cmd))
-	schedule();
-    } else {
-      // no RXer on the channel, just open (with pool zero)
-      cmd.request = cpu_to_be32 (SRB_OPEN_VC);
-      cmd.args.open.vc = cpu_to_be32 (vci);  // vpi 0
-      cmd.args.open.flags = cpu_to_be32 (tx_vc_bits << SRB_FLAGS_SHIFT);
-      cmd.args.open.rate = cpu_to_be32 (tx_rate_bits << SRB_RATE_SHIFT);
-      while (command_do (dev, &cmd))
-	schedule();
-    }
-    dev->txer[vci].tx_present = 1;
-    mutex_unlock(&dev->vcc_sf);
-  }
-  
-  if (rxtp->traffic_class != ATM_NONE) {
-    command cmd;
-    
-    vcc->rx_info.pool = pool;
-    
-    mutex_lock(&dev->vcc_sf);
-    /* grow RX buffer pool */
-    if (!dev->rxq[pool].buffers_wanted)
-      dev->rxq[pool].buffers_wanted = rx_lats;
-    dev->rxq[pool].buffers_wanted += 1;
-    fill_rx_pool (dev, pool, GFP_KERNEL);
-    
-    if (dev->txer[vci].tx_present) {
-      // TXer on the channel already
-      // switch (from pool zero) to this pool, preserving the TX bits
-      cmd.request = cpu_to_be32 (SRB_MODIFY_VC_FLAGS);
-      cmd.args.modify_flags.vc = cpu_to_be32 (vci);  // vpi 0
-      cmd.args.modify_flags.flags = cpu_to_be32
-	( (pool << SRB_POOL_SHIFT)
-	  | (dev->txer[vci].tx_vc_bits << SRB_FLAGS_SHIFT) );
-    } else {
-      // no TXer on the channel, open the VC (with no rate info)
-      cmd.request = cpu_to_be32 (SRB_OPEN_VC);
-      cmd.args.open.vc = cpu_to_be32 (vci);  // vpi 0
-      cmd.args.open.flags = cpu_to_be32 (pool << SRB_POOL_SHIFT);
-      cmd.args.open.rate = cpu_to_be32 (0);
-    }
-    while (command_do (dev, &cmd))
-      schedule();
-    // this link allows RX frames through
-    dev->rxer[vci] = atm_vcc;
-    mutex_unlock(&dev->vcc_sf);
-  }
-  
-  // indicate readiness
-  set_bit(ATM_VF_READY,&atm_vcc->flags);
-  
-  return 0;
-}
-
-/********** Close a VC **********/
-
-static void amb_close (struct atm_vcc * atm_vcc) {
-  amb_dev * dev = AMB_DEV (atm_vcc->dev);
-  amb_vcc * vcc = AMB_VCC (atm_vcc);
-  u16 vci = atm_vcc->vci;
-  
-  PRINTD (DBG_VCC|DBG_FLOW, "amb_close");
-  
-  // indicate unreadiness
-  clear_bit(ATM_VF_READY,&atm_vcc->flags);
-  
-  // disable TXing
-  if (atm_vcc->qos.txtp.traffic_class != ATM_NONE) {
-    command cmd;
-    
-    mutex_lock(&dev->vcc_sf);
-    if (dev->rxer[vci]) {
-      // RXer still on the channel, just modify rate... XXX not really needed
-      cmd.request = cpu_to_be32 (SRB_MODIFY_VC_RATE);
-      cmd.args.modify_rate.vc = cpu_to_be32 (vci);  // vpi 0
-      cmd.args.modify_rate.rate = cpu_to_be32 (0);
-      // ... and clear TX rate flags (XXX to stop RM cell output?), preserving RX pool
-    } else {
-      // no RXer on the channel, close channel
-      cmd.request = cpu_to_be32 (SRB_CLOSE_VC);
-      cmd.args.close.vc = cpu_to_be32 (vci); // vpi 0
-    }
-    dev->txer[vci].tx_present = 0;
-    while (command_do (dev, &cmd))
-      schedule();
-    mutex_unlock(&dev->vcc_sf);
-  }
-  
-  // disable RXing
-  if (atm_vcc->qos.rxtp.traffic_class != ATM_NONE) {
-    command cmd;
-    
-    // this is (the?) one reason why we need the amb_vcc struct
-    unsigned char pool = vcc->rx_info.pool;
-    
-    mutex_lock(&dev->vcc_sf);
-    if (dev->txer[vci].tx_present) {
-      // TXer still on the channel, just go to pool zero XXX not really needed
-      cmd.request = cpu_to_be32 (SRB_MODIFY_VC_FLAGS);
-      cmd.args.modify_flags.vc = cpu_to_be32 (vci);  // vpi 0
-      cmd.args.modify_flags.flags = cpu_to_be32
-	(dev->txer[vci].tx_vc_bits << SRB_FLAGS_SHIFT);
-    } else {
-      // no TXer on the channel, close the VC
-      cmd.request = cpu_to_be32 (SRB_CLOSE_VC);
-      cmd.args.close.vc = cpu_to_be32 (vci); // vpi 0
-    }
-    // forget the rxer - no more skbs will be pushed
-    if (atm_vcc != dev->rxer[vci])
-      PRINTK (KERN_ERR, "%s vcc=%p rxer[vci]=%p",
-	      "arghhh! we're going to die!",
-	      vcc, dev->rxer[vci]);
-    dev->rxer[vci] = NULL;
-    while (command_do (dev, &cmd))
-      schedule();
-    
-    /* shrink RX buffer pool */
-    dev->rxq[pool].buffers_wanted -= 1;
-    if (dev->rxq[pool].buffers_wanted == rx_lats) {
-      dev->rxq[pool].buffers_wanted = 0;
-      drain_rx_pool (dev, pool);
-    }
-    mutex_unlock(&dev->vcc_sf);
-  }
-  
-  // free our structure
-  kfree (vcc);
-  
-  // say the VPI/VCI is free again
-  clear_bit(ATM_VF_ADDR,&atm_vcc->flags);
-
-  return;
-}
-
-/********** Send **********/
-
-static int amb_send (struct atm_vcc * atm_vcc, struct sk_buff * skb) {
-  amb_dev * dev = AMB_DEV(atm_vcc->dev);
-  amb_vcc * vcc = AMB_VCC(atm_vcc);
-  u16 vc = atm_vcc->vci;
-  unsigned int tx_len = skb->len;
-  unsigned char * tx_data = skb->data;
-  tx_simple * tx_descr;
-  tx_in tx;
-  
-  if (test_bit (dead, &dev->flags))
-    return -EIO;
-  
-  PRINTD (DBG_FLOW|DBG_TX, "amb_send vc %x data %p len %u",
-	  vc, tx_data, tx_len);
-  
-  dump_skb (">>>", vc, skb);
-  
-  if (!dev->txer[vc].tx_present) {
-    PRINTK (KERN_ERR, "attempt to send on RX-only VC %x", vc);
-    return -EBADFD;
-  }
-  
-  // this is a driver private field so we have to set it ourselves,
-  // despite the fact that we are _required_ to use it to check for a
-  // pop function
-  ATM_SKB(skb)->vcc = atm_vcc;
-  
-  if (skb->len > (size_t) atm_vcc->qos.txtp.max_sdu) {
-    PRINTK (KERN_ERR, "sk_buff length greater than agreed max_sdu, dropping...");
-    return -EIO;
-  }
-  
-  if (check_area (skb->data, skb->len)) {
-    atomic_inc(&atm_vcc->stats->tx_err);
-    return -ENOMEM; // ?
-  }
-  
-  // allocate memory for fragments
-  tx_descr = kmalloc (sizeof(tx_simple), GFP_KERNEL);
-  if (!tx_descr) {
-    PRINTK (KERN_ERR, "could not allocate TX descriptor");
-    return -ENOMEM;
-  }
-  if (check_area (tx_descr, sizeof(tx_simple))) {
-    kfree (tx_descr);
-    return -ENOMEM;
-  }
-  PRINTD (DBG_TX, "fragment list allocated at %p", tx_descr);
-  
-  tx_descr->skb = skb;
-  
-  tx_descr->tx_frag.bytes = cpu_to_be32 (tx_len);
-  tx_descr->tx_frag.address = cpu_to_be32 (virt_to_bus (tx_data));
-  
-  tx_descr->tx_frag_end.handle = virt_to_bus (tx_descr);
-  tx_descr->tx_frag_end.vc = 0;
-  tx_descr->tx_frag_end.next_descriptor_length = 0;
-  tx_descr->tx_frag_end.next_descriptor = 0;
-#ifdef AMB_NEW_MICROCODE
-  tx_descr->tx_frag_end.cpcs_uu = 0;
-  tx_descr->tx_frag_end.cpi = 0;
-  tx_descr->tx_frag_end.pad = 0;
-#endif
-  
-  tx.vc = cpu_to_be16 (vcc->tx_frame_bits | vc);
-  tx.tx_descr_length = cpu_to_be16 (sizeof(tx_frag)+sizeof(tx_frag_end));
-  tx.tx_descr_addr = cpu_to_be32 (virt_to_bus (&tx_descr->tx_frag));
-  
-  while (tx_give (dev, &tx))
-    schedule();
-  return 0;
-}
-
-/********** Change QoS on a VC **********/
-
-// int amb_change_qos (struct atm_vcc * atm_vcc, struct atm_qos * qos, int flags);
-
-/********** Free RX Socket Buffer **********/
-
-#if 0
-static void amb_free_rx_skb (struct atm_vcc * atm_vcc, struct sk_buff * skb) {
-  amb_dev * dev = AMB_DEV (atm_vcc->dev);
-  amb_vcc * vcc = AMB_VCC (atm_vcc);
-  unsigned char pool = vcc->rx_info.pool;
-  rx_in rx;
-  
-  // This may be unsafe for various reasons that I cannot really guess
-  // at. However, I note that the ATM layer calls kfree_skb rather
-  // than dev_kfree_skb at this point so we are least covered as far
-  // as buffer locking goes. There may be bugs if pcap clones RX skbs.
-
-  PRINTD (DBG_FLOW|DBG_SKB, "amb_rx_free skb %p (atm_vcc %p, vcc %p)",
-	  skb, atm_vcc, vcc);
-  
-  rx.handle = virt_to_bus (skb);
-  rx.host_address = cpu_to_be32 (virt_to_bus (skb->data));
-  
-  skb->data = skb->head;
-  skb_reset_tail_pointer(skb);
-  skb->len = 0;
-  
-  if (!rx_give (dev, &rx, pool)) {
-    // success
-    PRINTD (DBG_SKB|DBG_POOL, "recycled skb for pool %hu", pool);
-    return;
-  }
-  
-  // just do what the ATM layer would have done
-  dev_kfree_skb_any (skb);
-  
-  return;
-}
-#endif
-
-/********** Proc File Output **********/
-
-static int amb_proc_read (struct atm_dev * atm_dev, loff_t * pos, char * page) {
-  amb_dev * dev = AMB_DEV (atm_dev);
-  int left = *pos;
-  unsigned char pool;
-  
-  PRINTD (DBG_FLOW, "amb_proc_read");
-  
-  /* more diagnostics here? */
-  
-  if (!left--) {
-    amb_stats * s = &dev->stats;
-    return sprintf (page,
-		    "frames: TX OK %lu, RX OK %lu, RX bad %lu "
-		    "(CRC %lu, long %lu, aborted %lu, unused %lu).\n",
-		    s->tx_ok, s->rx.ok, s->rx.error,
-		    s->rx.badcrc, s->rx.toolong,
-		    s->rx.aborted, s->rx.unused);
-  }
-  
-  if (!left--) {
-    amb_cq * c = &dev->cq;
-    return sprintf (page, "cmd queue [cur/hi/max]: %u/%u/%u. ",
-		    c->pending, c->high, c->maximum);
-  }
-  
-  if (!left--) {
-    amb_txq * t = &dev->txq;
-    return sprintf (page, "TX queue [cur/max high full]: %u/%u %u %u.\n",
-		    t->pending, t->maximum, t->high, t->filled);
-  }
-  
-  if (!left--) {
-    unsigned int count = sprintf (page, "RX queues [cur/max/req low empty]:");
-    for (pool = 0; pool < NUM_RX_POOLS; ++pool) {
-      amb_rxq * r = &dev->rxq[pool];
-      count += sprintf (page+count, " %u/%u/%u %u %u",
-			r->pending, r->maximum, r->buffers_wanted, r->low, r->emptied);
-    }
-    count += sprintf (page+count, ".\n");
-    return count;
-  }
-  
-  if (!left--) {
-    unsigned int count = sprintf (page, "RX buffer sizes:");
-    for (pool = 0; pool < NUM_RX_POOLS; ++pool) {
-      amb_rxq * r = &dev->rxq[pool];
-      count += sprintf (page+count, " %u", r->buffer_size);
-    }
-    count += sprintf (page+count, ".\n");
-    return count;
-  }
-  
-#if 0
-  if (!left--) {
-    // suni block etc?
-  }
-#endif
-  
-  return 0;
-}
-
-/********** Operation Structure **********/
-
-static const struct atmdev_ops amb_ops = {
-  .open         = amb_open,
-  .close	= amb_close,
-  .send         = amb_send,
-  .proc_read	= amb_proc_read,
-  .owner	= THIS_MODULE,
-};
-
-/********** housekeeping **********/
-static void do_housekeeping (struct timer_list *t) {
-  amb_dev * dev = from_timer(dev, t, housekeeping);
-  
-  // could collect device-specific (not driver/atm-linux) stats here
-      
-  // last resort refill once every ten seconds
-  fill_rx_pools (dev);
-  mod_timer(&dev->housekeeping, jiffies + 10*HZ);
-  
-  return;
-}
-
-/********** creation of communication queues **********/
-
-static int create_queues(amb_dev *dev, unsigned int cmds, unsigned int txs,
-			 unsigned int *rxs, unsigned int *rx_buffer_sizes)
-{
-  unsigned char pool;
-  size_t total = 0;
-  void * memory;
-  void * limit;
-  
-  PRINTD (DBG_FLOW, "create_queues %p", dev);
-  
-  total += cmds * sizeof(command);
-  
-  total += txs * (sizeof(tx_in) + sizeof(tx_out));
-  
-  for (pool = 0; pool < NUM_RX_POOLS; ++pool)
-    total += rxs[pool] * (sizeof(rx_in) + sizeof(rx_out));
-  
-  memory = kmalloc (total, GFP_KERNEL);
-  if (!memory) {
-    PRINTK (KERN_ERR, "could not allocate queues");
-    return -ENOMEM;
-  }
-  if (check_area (memory, total)) {
-    PRINTK (KERN_ERR, "queues allocated in nasty area");
-    kfree (memory);
-    return -ENOMEM;
-  }
-  
-  limit = memory + total;
-  PRINTD (DBG_INIT, "queues from %p to %p", memory, limit);
-  
-  PRINTD (DBG_CMD, "command queue at %p", memory);
-  
-  {
-    command * cmd = memory;
-    amb_cq * cq = &dev->cq;
-    
-    cq->pending = 0;
-    cq->high = 0;
-    cq->maximum = cmds - 1;
-    
-    cq->ptrs.start = cmd;
-    cq->ptrs.in = cmd;
-    cq->ptrs.out = cmd;
-    cq->ptrs.limit = cmd + cmds;
-    
-    memory = cq->ptrs.limit;
-  }
-  
-  PRINTD (DBG_TX, "TX queue pair at %p", memory);
-  
-  {
-    tx_in * in = memory;
-    tx_out * out;
-    amb_txq * txq = &dev->txq;
-    
-    txq->pending = 0;
-    txq->high = 0;
-    txq->filled = 0;
-    txq->maximum = txs - 1;
-    
-    txq->in.start = in;
-    txq->in.ptr = in;
-    txq->in.limit = in + txs;
-    
-    memory = txq->in.limit;
-    out = memory;
-    
-    txq->out.start = out;
-    txq->out.ptr = out;
-    txq->out.limit = out + txs;
-    
-    memory = txq->out.limit;
-  }
-  
-  PRINTD (DBG_RX, "RX queue pairs at %p", memory);
-  
-  for (pool = 0; pool < NUM_RX_POOLS; ++pool) {
-    rx_in * in = memory;
-    rx_out * out;
-    amb_rxq * rxq = &dev->rxq[pool];
-    
-    rxq->buffer_size = rx_buffer_sizes[pool];
-    rxq->buffers_wanted = 0;
-    
-    rxq->pending = 0;
-    rxq->low = rxs[pool] - 1;
-    rxq->emptied = 0;
-    rxq->maximum = rxs[pool] - 1;
-    
-    rxq->in.start = in;
-    rxq->in.ptr = in;
-    rxq->in.limit = in + rxs[pool];
-    
-    memory = rxq->in.limit;
-    out = memory;
-    
-    rxq->out.start = out;
-    rxq->out.ptr = out;
-    rxq->out.limit = out + rxs[pool];
-    
-    memory = rxq->out.limit;
-  }
-  
-  if (memory == limit) {
-    return 0;
-  } else {
-    PRINTK (KERN_ERR, "bad queue alloc %p != %p (tell maintainer)", memory, limit);
-    kfree (limit - total);
-    return -ENOMEM;
-  }
-  
-}
-
-/********** destruction of communication queues **********/
-
-static void destroy_queues (amb_dev * dev) {
-  // all queues assumed empty
-  void * memory = dev->cq.ptrs.start;
-  // includes txq.in, txq.out, rxq[].in and rxq[].out
-  
-  PRINTD (DBG_FLOW, "destroy_queues %p", dev);
-  
-  PRINTD (DBG_INIT, "freeing queues at %p", memory);
-  kfree (memory);
-  
-  return;
-}
-
-/********** basic loader commands and error handling **********/
-// centisecond timeouts - guessing away here
-static unsigned int command_timeouts [] = {
-	[host_memory_test]     = 15,
-	[read_adapter_memory]  = 2,
-	[write_adapter_memory] = 2,
-	[adapter_start]        = 50,
-	[get_version_number]   = 10,
-	[interrupt_host]       = 1,
-	[flash_erase_sector]   = 1,
-	[adap_download_block]  = 1,
-	[adap_erase_flash]     = 1,
-	[adap_run_in_iram]     = 1,
-	[adap_end_download]    = 1
-};
-
-
-static unsigned int command_successes [] = {
-	[host_memory_test]     = COMMAND_PASSED_TEST,
-	[read_adapter_memory]  = COMMAND_READ_DATA_OK,
-	[write_adapter_memory] = COMMAND_WRITE_DATA_OK,
-	[adapter_start]        = COMMAND_COMPLETE,
-	[get_version_number]   = COMMAND_COMPLETE,
-	[interrupt_host]       = COMMAND_COMPLETE,
-	[flash_erase_sector]   = COMMAND_COMPLETE,
-	[adap_download_block]  = COMMAND_COMPLETE,
-	[adap_erase_flash]     = COMMAND_COMPLETE,
-	[adap_run_in_iram]     = COMMAND_COMPLETE,
-	[adap_end_download]    = COMMAND_COMPLETE
-};
-  
-static  int decode_loader_result (loader_command cmd, u32 result)
-{
-	int res;
-	const char *msg;
-
-	if (result == command_successes[cmd])
-		return 0;
-
-	switch (result) {
-		case BAD_COMMAND:
-			res = -EINVAL;
-			msg = "bad command";
-			break;
-		case COMMAND_IN_PROGRESS:
-			res = -ETIMEDOUT;
-			msg = "command in progress";
-			break;
-		case COMMAND_PASSED_TEST:
-			res = 0;
-			msg = "command passed test";
-			break;
-		case COMMAND_FAILED_TEST:
-			res = -EIO;
-			msg = "command failed test";
-			break;
-		case COMMAND_READ_DATA_OK:
-			res = 0;
-			msg = "command read data ok";
-			break;
-		case COMMAND_READ_BAD_ADDRESS:
-			res = -EINVAL;
-			msg = "command read bad address";
-			break;
-		case COMMAND_WRITE_DATA_OK:
-			res = 0;
-			msg = "command write data ok";
-			break;
-		case COMMAND_WRITE_BAD_ADDRESS:
-			res = -EINVAL;
-			msg = "command write bad address";
-			break;
-		case COMMAND_WRITE_FLASH_FAILURE:
-			res = -EIO;
-			msg = "command write flash failure";
-			break;
-		case COMMAND_COMPLETE:
-			res = 0;
-			msg = "command complete";
-			break;
-		case COMMAND_FLASH_ERASE_FAILURE:
-			res = -EIO;
-			msg = "command flash erase failure";
-			break;
-		case COMMAND_WRITE_BAD_DATA:
-			res = -EINVAL;
-			msg = "command write bad data";
-			break;
-		default:
-			res = -EINVAL;
-			msg = "unknown error";
-			PRINTD (DBG_LOAD|DBG_ERR,
-				"decode_loader_result got %d=%x !",
-				result, result);
-			break;
-	}
-
-	PRINTK (KERN_ERR, "%s", msg);
-	return res;
-}
-
-static int do_loader_command(volatile loader_block *lb, const amb_dev *dev,
-			     loader_command cmd)
-{
-  
-  unsigned long timeout;
-  
-  PRINTD (DBG_FLOW|DBG_LOAD, "do_loader_command");
-  
-  /* do a command
-     
-     Set the return value to zero, set the command type and set the
-     valid entry to the right magic value. The payload is already
-     correctly byte-ordered so we leave it alone. Hit the doorbell
-     with the bus address of this structure.
-     
-  */
-  
-  lb->result = 0;
-  lb->command = cpu_to_be32 (cmd);
-  lb->valid = cpu_to_be32 (DMA_VALID);
-  // dump_registers (dev);
-  // dump_loader_block (lb);
-  wr_mem (dev, offsetof(amb_mem, doorbell), virt_to_bus (lb) & ~onegigmask);
-  
-  timeout = command_timeouts[cmd] * 10;
-  
-  while (!lb->result || lb->result == cpu_to_be32 (COMMAND_IN_PROGRESS))
-    if (timeout) {
-      timeout = msleep_interruptible(timeout);
-    } else {
-      PRINTD (DBG_LOAD|DBG_ERR, "command %d timed out", cmd);
-      dump_registers (dev);
-      dump_loader_block (lb);
-      return -ETIMEDOUT;
-    }
-  
-  if (cmd == adapter_start) {
-    // wait for start command to acknowledge...
-    timeout = 100;
-    while (rd_plain (dev, offsetof(amb_mem, doorbell)))
-      if (timeout) {
-	timeout = msleep_interruptible(timeout);
-      } else {
-	PRINTD (DBG_LOAD|DBG_ERR, "start command did not clear doorbell, res=%08x",
-		be32_to_cpu (lb->result));
-	dump_registers (dev);
-	return -ETIMEDOUT;
-      }
-    return 0;
-  } else {
-    return decode_loader_result (cmd, be32_to_cpu (lb->result));
-  }
-  
-}
-
-/* loader: determine loader version */
-
-static int get_loader_version(loader_block *lb, const amb_dev *dev,
-			      u32 *version)
-{
-  int res;
-  
-  PRINTD (DBG_FLOW|DBG_LOAD, "get_loader_version");
-  
-  res = do_loader_command (lb, dev, get_version_number);
-  if (res)
-    return res;
-  if (version)
-    *version = be32_to_cpu (lb->payload.version);
-  return 0;
-}
-
-/* loader: write memory data blocks */
-
-static int loader_write(loader_block *lb, const amb_dev *dev,
-			const struct ihex_binrec *rec)
-{
-  transfer_block * tb = &lb->payload.transfer;
-  
-  PRINTD (DBG_FLOW|DBG_LOAD, "loader_write");
-
-  tb->address = rec->addr;
-  tb->count = cpu_to_be32(be16_to_cpu(rec->len) / 4);
-  memcpy(tb->data, rec->data, be16_to_cpu(rec->len));
-  return do_loader_command (lb, dev, write_adapter_memory);
-}
-
-/* loader: verify memory data blocks */
-
-static int loader_verify(loader_block *lb, const amb_dev *dev,
-			 const struct ihex_binrec *rec)
-{
-  transfer_block * tb = &lb->payload.transfer;
-  int res;
-  
-  PRINTD (DBG_FLOW|DBG_LOAD, "loader_verify");
-  
-  tb->address = rec->addr;
-  tb->count = cpu_to_be32(be16_to_cpu(rec->len) / 4);
-  res = do_loader_command (lb, dev, read_adapter_memory);
-  if (!res && memcmp(tb->data, rec->data, be16_to_cpu(rec->len)))
-    res = -EINVAL;
-  return res;
-}
-
-/* loader: start microcode */
-
-static int loader_start(loader_block *lb, const amb_dev *dev, u32 address)
-{
-  PRINTD (DBG_FLOW|DBG_LOAD, "loader_start");
-  
-  lb->payload.start = cpu_to_be32 (address);
-  return do_loader_command (lb, dev, adapter_start);
-}
-
-/********** reset card **********/
-
-static inline void sf (const char * msg)
-{
-	PRINTK (KERN_ERR, "self-test failed: %s", msg);
-}
-
-static int amb_reset (amb_dev * dev, int diags) {
-  u32 word;
-  
-  PRINTD (DBG_FLOW|DBG_LOAD, "amb_reset");
-  
-  word = rd_plain (dev, offsetof(amb_mem, reset_control));
-  // put card into reset state
-  wr_plain (dev, offsetof(amb_mem, reset_control), word | AMB_RESET_BITS);
-  // wait a short while
-  udelay (10);
-#if 1
-  // put card into known good state
-  wr_plain (dev, offsetof(amb_mem, interrupt_control), AMB_DOORBELL_BITS);
-  // clear all interrupts just in case
-  wr_plain (dev, offsetof(amb_mem, interrupt), -1);
-#endif
-  // clear self-test done flag
-  wr_plain (dev, offsetof(amb_mem, mb.loader.ready), 0);
-  // take card out of reset state
-  wr_plain (dev, offsetof(amb_mem, reset_control), word &~ AMB_RESET_BITS);
-  
-  if (diags) { 
-    unsigned long timeout;
-    // 4.2 second wait
-    msleep(4200);
-    // half second time-out
-    timeout = 500;
-    while (!rd_plain (dev, offsetof(amb_mem, mb.loader.ready)))
-      if (timeout) {
-	timeout = msleep_interruptible(timeout);
-      } else {
-	PRINTD (DBG_LOAD|DBG_ERR, "reset timed out");
-	return -ETIMEDOUT;
-      }
-    
-    // get results of self-test
-    // XXX double check byte-order
-    word = rd_mem (dev, offsetof(amb_mem, mb.loader.result));
-    if (word & SELF_TEST_FAILURE) {
-      if (word & GPINT_TST_FAILURE)
-	sf ("interrupt");
-      if (word & SUNI_DATA_PATTERN_FAILURE)
-	sf ("SUNI data pattern");
-      if (word & SUNI_DATA_BITS_FAILURE)
-	sf ("SUNI data bits");
-      if (word & SUNI_UTOPIA_FAILURE)
-	sf ("SUNI UTOPIA interface");
-      if (word & SUNI_FIFO_FAILURE)
-	sf ("SUNI cell buffer FIFO");
-      if (word & SRAM_FAILURE)
-	sf ("bad SRAM");
-      // better return value?
-      return -EIO;
-    }
-    
-  }
-  return 0;
-}
-
-/********** transfer and start the microcode **********/
-
-static int ucode_init(loader_block *lb, amb_dev *dev)
-{
-  const struct firmware *fw;
-  unsigned long start_address;
-  const struct ihex_binrec *rec;
-  const char *errmsg = NULL;
-  int res;
-
-  res = request_ihex_firmware(&fw, "atmsar11.fw", &dev->pci_dev->dev);
-  if (res) {
-    PRINTK (KERN_ERR, "Cannot load microcode data");
-    return res;
-  }
-
-  /* First record contains just the start address */
-  rec = (const struct ihex_binrec *)fw->data;
-  if (be16_to_cpu(rec->len) != sizeof(__be32) || be32_to_cpu(rec->addr)) {
-    errmsg = "no start record";
-    goto fail;
-  }
-  start_address = be32_to_cpup((__be32 *)rec->data);
-
-  rec = ihex_next_binrec(rec);
-
-  PRINTD (DBG_FLOW|DBG_LOAD, "ucode_init");
-
-  while (rec) {
-    PRINTD (DBG_LOAD, "starting region (%x, %u)", be32_to_cpu(rec->addr),
-	    be16_to_cpu(rec->len));
-    if (be16_to_cpu(rec->len) > 4 * MAX_TRANSFER_DATA) {
-	    errmsg = "record too long";
-	    goto fail;
-    }
-    if (be16_to_cpu(rec->len) & 3) {
-	    errmsg = "odd number of bytes";
-	    goto fail;
-    }
-    res = loader_write(lb, dev, rec);
-    if (res)
-      break;
-
-    res = loader_verify(lb, dev, rec);
-    if (res)
-      break;
-    rec = ihex_next_binrec(rec);
-  }
-  release_firmware(fw);
-  if (!res)
-    res = loader_start(lb, dev, start_address);
-
-  return res;
-fail:
-  release_firmware(fw);
-  PRINTK(KERN_ERR, "Bad microcode data (%s)", errmsg);
-  return -EINVAL;
-}
-
-/********** give adapter parameters **********/
-  
-static inline __be32 bus_addr(void * addr) {
-    return cpu_to_be32 (virt_to_bus (addr));
-}
-
-static int amb_talk(amb_dev *dev)
-{
-  adap_talk_block a;
-  unsigned char pool;
-  unsigned long timeout;
-  
-  PRINTD (DBG_FLOW, "amb_talk %p", dev);
-  
-  a.command_start = bus_addr (dev->cq.ptrs.start);
-  a.command_end   = bus_addr (dev->cq.ptrs.limit);
-  a.tx_start      = bus_addr (dev->txq.in.start);
-  a.tx_end        = bus_addr (dev->txq.in.limit);
-  a.txcom_start   = bus_addr (dev->txq.out.start);
-  a.txcom_end     = bus_addr (dev->txq.out.limit);
-  
-  for (pool = 0; pool < NUM_RX_POOLS; ++pool) {
-    // the other "a" items are set up by the adapter
-    a.rec_struct[pool].buffer_start = bus_addr (dev->rxq[pool].in.start);
-    a.rec_struct[pool].buffer_end   = bus_addr (dev->rxq[pool].in.limit);
-    a.rec_struct[pool].rx_start     = bus_addr (dev->rxq[pool].out.start);
-    a.rec_struct[pool].rx_end       = bus_addr (dev->rxq[pool].out.limit);
-    a.rec_struct[pool].buffer_size = cpu_to_be32 (dev->rxq[pool].buffer_size);
-  }
-  
-#ifdef AMB_NEW_MICROCODE
-  // disable fast PLX prefetching
-  a.init_flags = 0;
-#endif
-  
-  // pass the structure
-  wr_mem (dev, offsetof(amb_mem, doorbell), virt_to_bus (&a));
-  
-  // 2.2 second wait (must not touch doorbell during 2 second DMA test)
-  msleep(2200);
-  // give the adapter another half second?
-  timeout = 500;
-  while (rd_plain (dev, offsetof(amb_mem, doorbell)))
-    if (timeout) {
-      timeout = msleep_interruptible(timeout);
-    } else {
-      PRINTD (DBG_INIT|DBG_ERR, "adapter init timed out");
-      return -ETIMEDOUT;
-    }
-  
-  return 0;
-}
-
-// get microcode version
-static void amb_ucode_version(amb_dev *dev)
-{
-  u32 major;
-  u32 minor;
-  command cmd;
-  cmd.request = cpu_to_be32 (SRB_GET_VERSION);
-  while (command_do (dev, &cmd)) {
-    set_current_state(TASK_UNINTERRUPTIBLE);
-    schedule();
-  }
-  major = be32_to_cpu (cmd.args.version.major);
-  minor = be32_to_cpu (cmd.args.version.minor);
-  PRINTK (KERN_INFO, "microcode version is %u.%u", major, minor);
-}
-  
-// get end station address
-static void amb_esi(amb_dev *dev, u8 *esi)
-{
-  u32 lower4;
-  u16 upper2;
-  command cmd;
-  
-  cmd.request = cpu_to_be32 (SRB_GET_BIA);
-  while (command_do (dev, &cmd)) {
-    set_current_state(TASK_UNINTERRUPTIBLE);
-    schedule();
-  }
-  lower4 = be32_to_cpu (cmd.args.bia.lower4);
-  upper2 = be32_to_cpu (cmd.args.bia.upper2);
-  PRINTD (DBG_LOAD, "BIA: lower4: %08x, upper2 %04x", lower4, upper2);
-  
-  if (esi) {
-    unsigned int i;
-    
-    PRINTDB (DBG_INIT, "ESI:");
-    for (i = 0; i < ESI_LEN; ++i) {
-      if (i < 4)
-	  esi[i] = bitrev8(lower4>>(8*i));
-      else
-	  esi[i] = bitrev8(upper2>>(8*(i-4)));
-      PRINTDM (DBG_INIT, " %02x", esi[i]);
-    }
-    
-    PRINTDE (DBG_INIT, "");
-  }
-  
-  return;
-}
-  
-static void fixup_plx_window (amb_dev *dev, loader_block *lb)
-{
-	// fix up the PLX-mapped window base address to match the block
-	unsigned long blb;
-	u32 mapreg;
-	blb = virt_to_bus(lb);
-	// the kernel stack had better not ever cross a 1Gb boundary!
-	mapreg = rd_plain (dev, offsetof(amb_mem, stuff[10]));
-	mapreg &= ~onegigmask;
-	mapreg |= blb & onegigmask;
-	wr_plain (dev, offsetof(amb_mem, stuff[10]), mapreg);
-	return;
-}
-
-static int amb_init(amb_dev *dev)
-{
-  loader_block lb;
-  
-  u32 version;
-  
-  if (amb_reset (dev, 1)) {
-    PRINTK (KERN_ERR, "card reset failed!");
-  } else {
-    fixup_plx_window (dev, &lb);
-    
-    if (get_loader_version (&lb, dev, &version)) {
-      PRINTK (KERN_INFO, "failed to get loader version");
-    } else {
-      PRINTK (KERN_INFO, "loader version is %08x", version);
-      
-      if (ucode_init (&lb, dev)) {
-	PRINTK (KERN_ERR, "microcode failure");
-      } else if (create_queues (dev, cmds, txs, rxs, rxs_bs)) {
-	PRINTK (KERN_ERR, "failed to get memory for queues");
-      } else {
-	
-	if (amb_talk (dev)) {
-	  PRINTK (KERN_ERR, "adapter did not accept queues");
-	} else {
-	  
-	  amb_ucode_version (dev);
-	  return 0;
-	  
-	} /* amb_talk */
-	
-	destroy_queues (dev);
-      } /* create_queues, ucode_init */
-      
-      amb_reset (dev, 0);
-    } /* get_loader_version */
-    
-  } /* amb_reset */
-  
-  return -EINVAL;
-}
-
-static void setup_dev(amb_dev *dev, struct pci_dev *pci_dev) 
-{
-      unsigned char pool;
-      
-      // set up known dev items straight away
-      dev->pci_dev = pci_dev; 
-      pci_set_drvdata(pci_dev, dev);
-      
-      dev->iobase = pci_resource_start (pci_dev, 1);
-      dev->irq = pci_dev->irq; 
-      dev->membase = bus_to_virt(pci_resource_start(pci_dev, 0));
-      
-      // flags (currently only dead)
-      dev->flags = 0;
-      
-      // Allocate cell rates (fibre)
-      // ATM_OC3_PCR = 1555200000/8/270*260/53 - 29/53
-      // to be really pedantic, this should be ATM_OC3c_PCR
-      dev->tx_avail = ATM_OC3_PCR;
-      dev->rx_avail = ATM_OC3_PCR;
-      
-      // semaphore for txer/rxer modifications - we cannot use a
-      // spinlock as the critical region needs to switch processes
-      mutex_init(&dev->vcc_sf);
-      // queue manipulation spinlocks; we want atomic reads and
-      // writes to the queue descriptors (handles IRQ and SMP)
-      // consider replacing "int pending" -> "atomic_t available"
-      // => problem related to who gets to move queue pointers
-      spin_lock_init (&dev->cq.lock);
-      spin_lock_init (&dev->txq.lock);
-      for (pool = 0; pool < NUM_RX_POOLS; ++pool)
-	spin_lock_init (&dev->rxq[pool].lock);
-}
-
-static void setup_pci_dev(struct pci_dev *pci_dev)
-{
-	unsigned char lat;
-      
-	// enable bus master accesses
-	pci_set_master(pci_dev);
-
-	// frobnicate latency (upwards, usually)
-	pci_read_config_byte (pci_dev, PCI_LATENCY_TIMER, &lat);
-
-	if (!pci_lat)
-		pci_lat = (lat < MIN_PCI_LATENCY) ? MIN_PCI_LATENCY : lat;
-
-	if (lat != pci_lat) {
-		PRINTK (KERN_INFO, "Changing PCI latency timer from %hu to %hu",
-			lat, pci_lat);
-		pci_write_config_byte(pci_dev, PCI_LATENCY_TIMER, pci_lat);
-	}
-}
-
-static int amb_probe(struct pci_dev *pci_dev,
-		     const struct pci_device_id *pci_ent)
-{
-	amb_dev * dev;
-	int err;
-	unsigned int irq;
-      
-	err = pci_enable_device(pci_dev);
-	if (err < 0) {
-		PRINTK (KERN_ERR, "skipped broken (PLX rev 2) card");
-		goto out;
-	}
-
-	// read resources from PCI configuration space
-	irq = pci_dev->irq;
-
-	if (pci_dev->device == PCI_DEVICE_ID_MADGE_AMBASSADOR_BAD) {
-		PRINTK (KERN_ERR, "skipped broken (PLX rev 2) card");
-		err = -EINVAL;
-		goto out_disable;
-	}
-
-	PRINTD (DBG_INFO, "found Madge ATM adapter (amb) at"
-		" IO %llx, IRQ %u, MEM %p",
-		(unsigned long long)pci_resource_start(pci_dev, 1),
-		irq, bus_to_virt(pci_resource_start(pci_dev, 0)));
-
-	// check IO region
-	err = pci_request_region(pci_dev, 1, DEV_LABEL);
-	if (err < 0) {
-		PRINTK (KERN_ERR, "IO range already in use!");
-		goto out_disable;
-	}
-
-	dev = kzalloc(sizeof(amb_dev), GFP_KERNEL);
-	if (!dev) {
-		PRINTK (KERN_ERR, "out of memory!");
-		err = -ENOMEM;
-		goto out_release;
-	}
-
-	setup_dev(dev, pci_dev);
-
-	err = amb_init(dev);
-	if (err < 0) {
-		PRINTK (KERN_ERR, "adapter initialisation failure");
-		goto out_free;
-	}
-
-	setup_pci_dev(pci_dev);
-
-	// grab (but share) IRQ and install handler
-	err = request_irq(irq, interrupt_handler, IRQF_SHARED, DEV_LABEL, dev);
-	if (err < 0) {
-		PRINTK (KERN_ERR, "request IRQ failed!");
-		goto out_reset;
-	}
-
-	dev->atm_dev = atm_dev_register (DEV_LABEL, &pci_dev->dev, &amb_ops, -1,
-					 NULL);
-	if (!dev->atm_dev) {
-		PRINTD (DBG_ERR, "failed to register Madge ATM adapter");
-		err = -EINVAL;
-		goto out_free_irq;
-	}
-
-	PRINTD (DBG_INFO, "registered Madge ATM adapter (no. %d) (%p) at %p",
-		dev->atm_dev->number, dev, dev->atm_dev);
-	dev->atm_dev->dev_data = (void *) dev;
-
-	// register our address
-	amb_esi (dev, dev->atm_dev->esi);
-
-	// 0 bits for vpi, 10 bits for vci
-	dev->atm_dev->ci_range.vpi_bits = NUM_VPI_BITS;
-	dev->atm_dev->ci_range.vci_bits = NUM_VCI_BITS;
-
-	timer_setup(&dev->housekeeping, do_housekeeping, 0);
-	mod_timer(&dev->housekeeping, jiffies);
-
-	// enable host interrupts
-	interrupts_on (dev);
-
-out:
-	return err;
-
-out_free_irq:
-	free_irq(irq, dev);
-out_reset:
-	amb_reset(dev, 0);
-out_free:
-	kfree(dev);
-out_release:
-	pci_release_region(pci_dev, 1);
-out_disable:
-	pci_disable_device(pci_dev);
-	goto out;
-}
-
-
-static void amb_remove_one(struct pci_dev *pci_dev)
-{
-	struct amb_dev *dev;
-
-	dev = pci_get_drvdata(pci_dev);
-
-	PRINTD(DBG_INFO|DBG_INIT, "closing %p (atm_dev = %p)", dev, dev->atm_dev);
-	del_timer_sync(&dev->housekeeping);
-	// the drain should not be necessary
-	drain_rx_pools(dev);
-	interrupts_off(dev);
-	amb_reset(dev, 0);
-	free_irq(dev->irq, dev);
-	pci_disable_device(pci_dev);
-	destroy_queues(dev);
-	atm_dev_deregister(dev->atm_dev);
-	kfree(dev);
-	pci_release_region(pci_dev, 1);
-}
-
-static void __init amb_check_args (void) {
-  unsigned char pool;
-  unsigned int max_rx_size;
-  
-#ifdef DEBUG_AMBASSADOR
-  PRINTK (KERN_NOTICE, "debug bitmap is %hx", debug &= DBG_MASK);
-#else
-  if (debug)
-    PRINTK (KERN_NOTICE, "no debugging support");
-#endif
-  
-  if (cmds < MIN_QUEUE_SIZE)
-    PRINTK (KERN_NOTICE, "cmds has been raised to %u",
-	    cmds = MIN_QUEUE_SIZE);
-  
-  if (txs < MIN_QUEUE_SIZE)
-    PRINTK (KERN_NOTICE, "txs has been raised to %u",
-	    txs = MIN_QUEUE_SIZE);
-  
-  for (pool = 0; pool < NUM_RX_POOLS; ++pool)
-    if (rxs[pool] < MIN_QUEUE_SIZE)
-      PRINTK (KERN_NOTICE, "rxs[%hu] has been raised to %u",
-	      pool, rxs[pool] = MIN_QUEUE_SIZE);
-  
-  // buffers sizes should be greater than zero and strictly increasing
-  max_rx_size = 0;
-  for (pool = 0; pool < NUM_RX_POOLS; ++pool)
-    if (rxs_bs[pool] <= max_rx_size)
-      PRINTK (KERN_NOTICE, "useless pool (rxs_bs[%hu] = %u)",
-	      pool, rxs_bs[pool]);
-    else
-      max_rx_size = rxs_bs[pool];
-  
-  if (rx_lats < MIN_RX_BUFFERS)
-    PRINTK (KERN_NOTICE, "rx_lats has been raised to %u",
-	    rx_lats = MIN_RX_BUFFERS);
-  
-  return;
-}
-
-/********** module stuff **********/
-
-MODULE_AUTHOR(maintainer_string);
-MODULE_DESCRIPTION(description_string);
-MODULE_LICENSE("GPL");
-MODULE_FIRMWARE("atmsar11.fw");
-module_param(debug,   ushort, 0644);
-module_param(cmds,    uint, 0);
-module_param(txs,     uint, 0);
-module_param_array(rxs,     uint, NULL, 0);
-module_param_array(rxs_bs,  uint, NULL, 0);
-module_param(rx_lats, uint, 0);
-module_param(pci_lat, byte, 0);
-MODULE_PARM_DESC(debug,   "debug bitmap, see .h file");
-MODULE_PARM_DESC(cmds,    "number of command queue entries");
-MODULE_PARM_DESC(txs,     "number of TX queue entries");
-MODULE_PARM_DESC(rxs,     "number of RX queue entries [" __MODULE_STRING(NUM_RX_POOLS) "]");
-MODULE_PARM_DESC(rxs_bs,  "size of RX buffers [" __MODULE_STRING(NUM_RX_POOLS) "]");
-MODULE_PARM_DESC(rx_lats, "number of extra buffers to cope with RX latencies");
-MODULE_PARM_DESC(pci_lat, "PCI latency in bus cycles");
-
-/********** module entry **********/
-
-static const struct pci_device_id amb_pci_tbl[] = {
-	{ PCI_VDEVICE(MADGE, PCI_DEVICE_ID_MADGE_AMBASSADOR), 0 },
-	{ PCI_VDEVICE(MADGE, PCI_DEVICE_ID_MADGE_AMBASSADOR_BAD), 0 },
-	{ 0, }
-};
-
-MODULE_DEVICE_TABLE(pci, amb_pci_tbl);
-
-static struct pci_driver amb_driver = {
-	.name =		"amb",
-	.probe =	amb_probe,
-	.remove =	amb_remove_one,
-	.id_table =	amb_pci_tbl,
-};
-
-static int __init amb_module_init (void)
-{
-  PRINTD (DBG_FLOW|DBG_INIT, "init_module");
-  
-  BUILD_BUG_ON(sizeof(amb_mem) != 4*16 + 4*12);
-  
-  show_version();
-  
-  amb_check_args();
-  
-  // get the juice
-  return pci_register_driver(&amb_driver);
-}
-
-/********** module exit **********/
-
-static void __exit amb_module_exit (void)
-{
-  PRINTD (DBG_FLOW|DBG_INIT, "cleanup_module");
-
-  pci_unregister_driver(&amb_driver);
-}
-
-module_init(amb_module_init);
-module_exit(amb_module_exit);
diff --git a/drivers/atm/ambassador.h b/drivers/atm/ambassador.h
deleted file mode 100644
index 086ceb8568dc..000000000000
--- a/drivers/atm/ambassador.h
+++ /dev/null
@@ -1,648 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
-  Madge Ambassador ATM Adapter driver.
-  Copyright (C) 1995-1999  Madge Networks Ltd.
-
-*/
-
-#ifndef AMBASSADOR_H
-#define AMBASSADOR_H
-
-
-#ifdef CONFIG_ATM_AMBASSADOR_DEBUG
-#define DEBUG_AMBASSADOR
-#endif
-
-#define DEV_LABEL                          "amb"
-
-#ifndef PCI_VENDOR_ID_MADGE
-#define PCI_VENDOR_ID_MADGE                0x10B6
-#endif
-#ifndef PCI_VENDOR_ID_MADGE_AMBASSADOR
-#define PCI_DEVICE_ID_MADGE_AMBASSADOR     0x1001
-#endif
-#ifndef PCI_VENDOR_ID_MADGE_AMBASSADOR_BAD
-#define PCI_DEVICE_ID_MADGE_AMBASSADOR_BAD 0x1002
-#endif
-
-// diagnostic output
-
-#define PRINTK(severity,format,args...) \
-  printk(severity DEV_LABEL ": " format "\n" , ## args)
-
-#ifdef DEBUG_AMBASSADOR
-
-#define DBG_ERR  0x0001
-#define DBG_WARN 0x0002
-#define DBG_INFO 0x0004
-#define DBG_INIT 0x0008
-#define DBG_LOAD 0x0010
-#define DBG_VCC  0x0020
-#define DBG_QOS  0x0040
-#define DBG_CMD  0x0080
-#define DBG_TX   0x0100
-#define DBG_RX   0x0200
-#define DBG_SKB  0x0400
-#define DBG_POOL 0x0800
-#define DBG_IRQ  0x1000
-#define DBG_FLOW 0x2000
-#define DBG_REGS 0x4000
-#define DBG_DATA 0x8000
-#define DBG_MASK 0xffff
-
-/* the ## prevents the annoying double expansion of the macro arguments */
-/* KERN_INFO is used since KERN_DEBUG often does not make it to the console */
-#define PRINTDB(bits,format,args...) \
-  ( (debug & (bits)) ? printk (KERN_INFO DEV_LABEL ": " format , ## args) : 1 )
-#define PRINTDM(bits,format,args...) \
-  ( (debug & (bits)) ? printk (format , ## args) : 1 )
-#define PRINTDE(bits,format,args...) \
-  ( (debug & (bits)) ? printk (format "\n" , ## args) : 1 )
-#define PRINTD(bits,format,args...) \
-  ( (debug & (bits)) ? printk (KERN_INFO DEV_LABEL ": " format "\n" , ## args) : 1 )
-
-#else
-
-#define PRINTD(bits,format,args...)
-#define PRINTDB(bits,format,args...)
-#define PRINTDM(bits,format,args...)
-#define PRINTDE(bits,format,args...)
-
-#endif
-
-#define PRINTDD(bits,format,args...)
-#define PRINTDDB(sec,fmt,args...)
-#define PRINTDDM(sec,fmt,args...)
-#define PRINTDDE(sec,fmt,args...)
-
-// tunable values (?)
-
-/* MUST be powers of two -- why ? */
-#define COM_Q_ENTRIES        8
-#define TX_Q_ENTRIES        32
-#define RX_Q_ENTRIES        64
-
-// fixed values
-
-// guessing
-#define AMB_EXTENT         0x80
-
-// Minimum allowed size for an Ambassador queue
-#define MIN_QUEUE_SIZE     2
-
-// Ambassador microcode allows 1 to 4 pools, we use 4 (simpler)
-#define NUM_RX_POOLS	   4
-
-// minimum RX buffers required to cope with replenishing delay
-#define MIN_RX_BUFFERS	   1
-
-// minimum PCI latency we will tolerate (32 IS TOO SMALL)
-#define MIN_PCI_LATENCY   64 // 255
-
-// VCs supported by card (VPI always 0)
-#define NUM_VPI_BITS       0
-#define NUM_VCI_BITS      10
-#define NUM_VCS         1024
-
-/* The status field bits defined so far. */
-#define RX_ERR		0x8000 // always present if there is an error (hmm)
-#define CRC_ERR		0x4000 // AAL5 CRC error
-#define LEN_ERR		0x2000 // overlength frame
-#define ABORT_ERR	0x1000 // zero length field in received frame
-#define UNUSED_ERR	0x0800 // buffer returned unused
-
-// Adaptor commands
-
-#define SRB_OPEN_VC		0
-/* par_0: dwordswap(VC_number) */
-/* par_1: dwordswap(flags<<16) or wordswap(flags)*/ 
-/* flags:		*/
-
-/* LANE:	0x0004		*/
-/* NOT_UBR:	0x0008		*/
-/* ABR:		0x0010		*/
-
-/* RxPool0:	0x0000		*/
-/* RxPool1:	0x0020		*/
-/* RxPool2:	0x0040		*/
-/* RxPool3:	0x0060		*/
-
-/* par_2: dwordswap(fp_rate<<16) or wordswap(fp_rate) */
-
-#define	SRB_CLOSE_VC		1
-/* par_0: dwordswap(VC_number) */
-
-#define	SRB_GET_BIA		2
-/* returns 		*/
-/* par_0: dwordswap(half BIA) */
-/* par_1: dwordswap(half BIA) */
-
-#define	SRB_GET_SUNI_STATS	3
-/* par_0: dwordswap(physical_host_address) */
-
-#define	SRB_SET_BITS_8		4
-#define	SRB_SET_BITS_16		5
-#define	SRB_SET_BITS_32		6
-#define	SRB_CLEAR_BITS_8	7
-#define	SRB_CLEAR_BITS_16	8
-#define	SRB_CLEAR_BITS_32	9
-/* par_0: dwordswap(ATMizer address)	*/
-/* par_1: dwordswap(mask) */
-
-#define	SRB_SET_8		10
-#define	SRB_SET_16		11
-#define	SRB_SET_32		12
-/* par_0: dwordswap(ATMizer address)	*/
-/* par_1: dwordswap(data) */
-
-#define	SRB_GET_32		13
-/* par_0: dwordswap(ATMizer address)	*/
-/* returns			*/
-/* par_1: dwordswap(ATMizer data) */
-
-#define SRB_GET_VERSION		14
-/* returns 		*/
-/* par_0: dwordswap(Major Version) */
-/* par_1: dwordswap(Minor Version) */
-
-#define SRB_FLUSH_BUFFER_Q	15
-/* Only flags to define which buffer pool; all others must be zero */
-/* par_0: dwordswap(flags<<16) or wordswap(flags)*/ 
-
-#define	SRB_GET_DMA_SPEEDS	16
-/* returns 		*/
-/* par_0: dwordswap(Read speed (bytes/sec)) */
-/* par_1: dwordswap(Write speed (bytes/sec)) */
-
-#define SRB_MODIFY_VC_RATE	17
-/* par_0: dwordswap(VC_number) */
-/* par_1: dwordswap(fp_rate<<16) or wordswap(fp_rate) */
-
-#define SRB_MODIFY_VC_FLAGS	18
-/* par_0: dwordswap(VC_number) */
-/* par_1: dwordswap(flags<<16) or wordswap(flags)*/ 
-
-/* flags:		*/
-
-/* LANE:	0x0004		*/
-/* NOT_UBR:	0x0008		*/
-/* ABR:		0x0010		*/
-
-/* RxPool0:	0x0000		*/
-/* RxPool1:	0x0020		*/
-/* RxPool2:	0x0040		*/
-/* RxPool3:	0x0060		*/
-
-#define SRB_RATE_SHIFT          16
-#define SRB_POOL_SHIFT          (SRB_FLAGS_SHIFT+5)
-#define SRB_FLAGS_SHIFT         16
-
-#define	SRB_STOP_TASKING	19
-#define	SRB_START_TASKING	20
-#define SRB_SHUT_DOWN		21
-#define MAX_SRB			21
-
-#define SRB_COMPLETE		0xffffffff
-
-#define TX_FRAME          	0x80000000
-
-// number of types of SRB MUST be a power of two -- why?
-#define NUM_OF_SRB	32
-
-// number of bits of period info for rate
-#define MAX_RATE_BITS	6
-
-#define TX_UBR          0x0000
-#define TX_UBR_CAPPED   0x0008
-#define TX_ABR          0x0018
-#define TX_FRAME_NOTCAP 0x0000
-#define TX_FRAME_CAPPED 0x8000
-
-#define FP_155_RATE	0x24b1
-#define FP_25_RATE	0x1f9d
-
-/* #define VERSION_NUMBER 0x01000000 // initial release */
-/* #define VERSION_NUMBER 0x01010000 // fixed startup probs PLX MB0 not cleared */
-/* #define VERSION_NUMBER 0x01020000 // changed SUNI reset timings; allowed r/w onchip */
-
-/* #define VERSION_NUMBER 0x01030000 // clear local doorbell int reg on reset */
-/* #define VERSION_NUMBER 0x01040000 // PLX bug work around version PLUS */
-/* remove race conditions on basic interface */
-/* indicate to the host that diagnostics */
-/* have finished; if failed, how and what  */
-/* failed */
-/* fix host memory test to fix PLX bug */
-/* allow flash upgrade and BIA upgrade directly */
-/*  */
-#define VERSION_NUMBER 0x01050025 /* Jason's first hacked version. */
-/* Change in download algorithm */
-
-#define DMA_VALID 0xb728e149 /* completely random */
-
-#define FLASH_BASE 0xa0c00000
-#define FLASH_SIZE 0x00020000			/* 128K */
-#define BIA_BASE (FLASH_BASE+0x0001c000)	/* Flash Sector 7 */
-#define BIA_ADDRESS ((void *)0xa0c1c000)
-#define PLX_BASE 0xe0000000
-
-typedef enum {
-  host_memory_test = 1,
-  read_adapter_memory,
-  write_adapter_memory,
-  adapter_start,
-  get_version_number,
-  interrupt_host,
-  flash_erase_sector,
-  adap_download_block = 0x20,
-  adap_erase_flash,
-  adap_run_in_iram,
-  adap_end_download
-} loader_command;
-
-#define BAD_COMMAND                     (-1)
-#define COMMAND_IN_PROGRESS             1
-#define COMMAND_PASSED_TEST             2
-#define COMMAND_FAILED_TEST             3
-#define COMMAND_READ_DATA_OK            4
-#define COMMAND_READ_BAD_ADDRESS        5
-#define COMMAND_WRITE_DATA_OK           6
-#define COMMAND_WRITE_BAD_ADDRESS       7
-#define COMMAND_WRITE_FLASH_FAILURE     8
-#define COMMAND_COMPLETE                9
-#define COMMAND_FLASH_ERASE_FAILURE	10
-#define COMMAND_WRITE_BAD_DATA		11
-
-/* bit fields for mailbox[0] return values */
-
-#define GPINT_TST_FAILURE               0x00000001      
-#define SUNI_DATA_PATTERN_FAILURE       0x00000002
-#define SUNI_DATA_BITS_FAILURE          0x00000004
-#define SUNI_UTOPIA_FAILURE             0x00000008
-#define SUNI_FIFO_FAILURE               0x00000010
-#define SRAM_FAILURE                    0x00000020
-#define SELF_TEST_FAILURE               0x0000003f
-
-/* mailbox[1] = 0 in progress, -1 on completion */
-/* mailbox[2] = current test 00 00 test(8 bit) phase(8 bit) */
-/* mailbox[3] = last failure, 00 00 test(8 bit) phase(8 bit) */
-/* mailbox[4],mailbox[5],mailbox[6] random failure values */
-
-/* PLX/etc. memory map including command structure */
-
-/* These registers may also be memory mapped in PCI memory */
-
-#define UNUSED_LOADER_MAILBOXES 6
-
-typedef struct {
-  u32 stuff[16];
-  union {
-    struct {
-      u32 result;
-      u32 ready;
-      u32 stuff[UNUSED_LOADER_MAILBOXES];
-    } loader;
-    struct {
-      u32 cmd_address;
-      u32 tx_address;
-      u32 rx_address[NUM_RX_POOLS];
-      u32 gen_counter;
-      u32 spare;
-    } adapter;
-  } mb;
-  u32 doorbell;
-  u32 interrupt;
-  u32 interrupt_control;
-  u32 reset_control;
-} amb_mem;
-
-/* RESET bit, IRQ (card to host) and doorbell (host to card) enable bits */
-#define AMB_RESET_BITS	   0x40000000
-#define AMB_INTERRUPT_BITS 0x00000300
-#define AMB_DOORBELL_BITS  0x00030000
-
-/* loader commands */
-
-#define MAX_COMMAND_DATA 13
-#define MAX_TRANSFER_DATA 11
-
-typedef struct {
-  __be32 address;
-  __be32 count;
-  __be32 data[MAX_TRANSFER_DATA];
-} transfer_block;
-
-typedef struct {
-  __be32 result;
-  __be32 command;
-  union {
-    transfer_block transfer;
-    __be32 version;
-    __be32 start;
-    __be32 data[MAX_COMMAND_DATA];
-  } payload;
-  __be32 valid;
-} loader_block;
-
-/* command queue */
-
-/* Again all data are BIG ENDIAN */
-
-typedef	struct {
-  union {
-    struct {
-      __be32 vc;
-      __be32 flags;
-      __be32 rate;
-    } open;
-    struct {
-      __be32 vc;
-      __be32 rate;
-    } modify_rate;
-    struct {
-      __be32 vc;
-      __be32 flags;
-    } modify_flags;
-    struct {
-      __be32 vc;
-    } close;
-    struct {
-      __be32 lower4;
-      __be32 upper2;
-    } bia;
-    struct {
-      __be32 address;
-    } suni;
-    struct {
-      __be32 major;
-      __be32 minor;
-    } version;
-    struct {
-      __be32 read;
-      __be32 write;
-    } speed;
-    struct {
-      __be32 flags;
-    } flush;
-    struct {
-      __be32 address;
-      __be32 data;
-    } memory;
-    __be32 par[3];
-  } args;
-  __be32 request;
-} command;
-
-/* transmit queues and associated structures */
-
-/* The hosts transmit structure. All BIG ENDIAN; host address
-   restricted to first 1GByte, but address passed to the card must
-   have the top MS bit or'ed in. -- check this */
-
-/* TX is described by 1+ tx_frags followed by a tx_frag_end */
-
-typedef struct {
-  __be32 bytes;
-  __be32 address;
-} tx_frag;
-
-/* apart from handle the fields here are for the adapter to play with
-   and should be set to zero */
-
-typedef struct {
-  u32	handle;
-  u16	vc;
-  u16	next_descriptor_length;
-  u32	next_descriptor;
-#ifdef AMB_NEW_MICROCODE
-  u8    cpcs_uu;
-  u8    cpi;
-  u16   pad;
-#endif
-} tx_frag_end;
-
-typedef struct {
-  tx_frag tx_frag;
-  tx_frag_end tx_frag_end;
-  struct sk_buff * skb;
-} tx_simple;
-
-#if 0
-typedef union {
-  tx_frag	fragment;
-  tx_frag_end	end_of_list;
-} tx_descr;
-#endif
-
-/* this "points" to the sequence of fragments and trailer */
-
-typedef	struct {
-  __be16	vc;
-  __be16	tx_descr_length;
-  __be32	tx_descr_addr;
-} tx_in;
-
-/* handle is the handle from tx_in */
-
-typedef	struct {
-  u32 handle;
-} tx_out;
-
-/* receive frame structure */
-
-/* All BIG ENDIAN; handle is as passed from host; length is zero for
-   aborted frames, and frames with errors. Header is actually VC
-   number, lec-id is NOT yet supported. */
-
-typedef struct {
-  u32  handle;
-  __be16  vc;
-  __be16  lec_id; // unused
-  __be16  status;
-  __be16  length;
-} rx_out;
-
-/* buffer supply structure */
-
-typedef	struct {
-  u32 handle;
-  __be32 host_address;
-} rx_in;
-
-/* This first structure is the area in host memory where the adapter
-   writes its pointer values. These pointer values are BIG ENDIAN and
-   reside in the same 4MB 'page' as this structure. The host gives the
-   adapter the address of this block by sending a doorbell interrupt
-   to the adapter after downloading the code and setting it going. The
-   addresses have the top 10 bits set to 1010000010b -- really?
-   
-   The host must initialise these before handing the block to the
-   adapter. */
-
-typedef struct {
-  __be32 command_start;		/* SRB commands completions */
-  __be32 command_end;		/* SRB commands completions */
-  __be32 tx_start;
-  __be32 tx_end;
-  __be32 txcom_start;		/* tx completions */
-  __be32 txcom_end;		/* tx completions */
-  struct {
-    __be32 buffer_start;
-    __be32 buffer_end;
-    u32 buffer_q_get;
-    u32 buffer_q_end;
-    u32 buffer_aptr;
-    __be32 rx_start;		/* rx completions */
-    __be32 rx_end;
-    u32 rx_ptr;
-    __be32 buffer_size;		/* size of host buffer */
-  } rec_struct[NUM_RX_POOLS];
-#ifdef AMB_NEW_MICROCODE
-  u16 init_flags;
-  u16 talk_block_spare;
-#endif
-} adap_talk_block;
-
-/* This structure must be kept in line with the vcr image in sarmain.h
-   
-   This is the structure in the host filled in by the adapter by
-   GET_SUNI_STATS */
-
-typedef struct {
-  u8	racp_chcs;
-  u8	racp_uhcs;
-  u16	spare;
-  u32	racp_rcell;
-  u32	tacp_tcell;
-  u32	flags;
-  u32	dropped_cells;
-  u32	dropped_frames;
-} suni_stats;
-
-typedef enum {
-  dead
-} amb_flags;
-
-#define NEXTQ(current,start,limit) \
-  ( (current)+1 < (limit) ? (current)+1 : (start) ) 
-
-typedef struct {
-  command * start;
-  command * in;
-  command * out;
-  command * limit;
-} amb_cq_ptrs;
-
-typedef struct {
-  spinlock_t lock;
-  unsigned int pending;
-  unsigned int high;
-  unsigned int filled;
-  unsigned int maximum; // size - 1 (q implementation)
-  amb_cq_ptrs ptrs;
-} amb_cq;
-
-typedef struct {
-  spinlock_t lock;
-  unsigned int pending;
-  unsigned int high;
-  unsigned int filled;
-  unsigned int maximum; // size - 1 (q implementation)
-  struct {
-    tx_in * start;
-    tx_in * ptr;
-    tx_in * limit;
-  } in;
-  struct {
-    tx_out * start;
-    tx_out * ptr;
-    tx_out * limit;
-  } out;
-} amb_txq;
-
-typedef struct {
-  spinlock_t lock;
-  unsigned int pending;
-  unsigned int low;
-  unsigned int emptied;
-  unsigned int maximum; // size - 1 (q implementation)
-  struct {
-    rx_in * start;
-    rx_in * ptr;
-    rx_in * limit;
-  } in;
-  struct {
-    rx_out * start;
-    rx_out * ptr;
-    rx_out * limit;
-  } out;
-  unsigned int buffers_wanted;
-  unsigned int buffer_size;
-} amb_rxq;
-
-typedef struct {
-  unsigned long tx_ok;
-  struct {
-    unsigned long ok;
-    unsigned long error;
-    unsigned long badcrc;
-    unsigned long toolong;
-    unsigned long aborted;
-    unsigned long unused;
-  } rx;
-} amb_stats;
-
-// a single struct pointed to by atm_vcc->dev_data
-
-typedef struct {
-  u8               tx_vc_bits:7;
-  u8               tx_present:1;
-} amb_tx_info;
-
-typedef struct {
-  unsigned char    pool;
-} amb_rx_info;
-
-typedef struct {
-  amb_rx_info      rx_info;
-  u16              tx_frame_bits;
-  unsigned int     tx_rate;
-  unsigned int     rx_rate;
-} amb_vcc;
-
-struct amb_dev {
-  u8               irq;
-  unsigned long	   flags;
-  u32              iobase;
-  u32 *            membase;
-
-  amb_cq           cq;
-  amb_txq          txq;
-  amb_rxq          rxq[NUM_RX_POOLS];
-  
-  struct mutex     vcc_sf;
-  amb_tx_info      txer[NUM_VCS];
-  struct atm_vcc * rxer[NUM_VCS];
-  unsigned int     tx_avail;
-  unsigned int     rx_avail;
-  
-  amb_stats        stats;
-  
-  struct atm_dev * atm_dev;
-  struct pci_dev * pci_dev;
-  struct timer_list housekeeping;
-};
-
-typedef struct amb_dev amb_dev;
-
-#define AMB_DEV(atm_dev) ((amb_dev *) (atm_dev)->dev_data)
-#define AMB_VCC(atm_vcc) ((amb_vcc *) (atm_vcc)->dev_data)
-
-/* rate rounding */
-
-typedef enum {
-  round_up,
-  round_down,
-  round_nearest
-} rounding;
-
-#endif
diff --git a/drivers/atm/atmtcp.c b/drivers/atm/atmtcp.c
index d9fd70280482..fa3c76a2b49d 100644
--- a/drivers/atm/atmtcp.c
+++ b/drivers/atm/atmtcp.c
@@ -279,6 +279,19 @@ static struct atm_vcc *find_vcc(struct atm_dev *dev, short vpi, int vci)
         return NULL;
 }
 
+static int atmtcp_c_pre_send(struct atm_vcc *vcc, struct sk_buff *skb)
+{
+	struct atmtcp_hdr *hdr;
+
+	if (skb->len < sizeof(struct atmtcp_hdr))
+		return -EINVAL;
+
+	hdr = (struct atmtcp_hdr *)skb->data;
+	if (hdr->length == ATMTCP_HDR_MAGIC)
+		return -EINVAL;
+
+	return 0;
+}
 
 static int atmtcp_c_send(struct atm_vcc *vcc,struct sk_buff *skb)
 {
@@ -288,7 +301,6 @@ static int atmtcp_c_send(struct atm_vcc *vcc,struct sk_buff *skb)
 	struct sk_buff *new_skb;
 	int result = 0;
 
-	if (!skb->len) return 0;
 	dev = vcc->dev_data;
 	hdr = (struct atmtcp_hdr *) skb->data;
 	if (hdr->length == ATMTCP_HDR_MAGIC) {
@@ -327,7 +339,7 @@ done:
  */
 
 
-static struct atmdev_ops atmtcp_v_dev_ops = {
+static const struct atmdev_ops atmtcp_v_dev_ops = {
 	.dev_close	= atmtcp_v_dev_close,
 	.open		= atmtcp_v_open,
 	.close		= atmtcp_v_close,
@@ -345,6 +357,7 @@ static struct atmdev_ops atmtcp_v_dev_ops = {
 
 static const struct atmdev_ops atmtcp_c_dev_ops = {
 	.close		= atmtcp_c_close,
+	.pre_send	= atmtcp_c_pre_send,
 	.send		= atmtcp_c_send
 };
 
@@ -433,9 +446,15 @@ static int atmtcp_remove_persistent(int itf)
 		return -EMEDIUMTYPE;
 	}
 	dev_data = PRIV(dev);
-	if (!dev_data->persist) return 0;
+	if (!dev_data->persist) {
+		atm_dev_put(dev);
+		return 0;
+	}
 	dev_data->persist = 0;
-	if (PRIV(dev)->vcc) return 0;
+	if (PRIV(dev)->vcc) {
+		atm_dev_put(dev);
+		return 0;
+	}
 	kfree(dev_data);
 	atm_dev_put(dev);
 	atm_dev_deregister(dev);
@@ -488,6 +507,7 @@ static void __exit atmtcp_exit(void)
 	deregister_atm_ioctl(&atmtcp_ioctl_ops);
 }
 
+MODULE_DESCRIPTION("ATM over TCP");
 MODULE_LICENSE("GPL");
 module_init(atmtcp_init);
 module_exit(atmtcp_exit);
diff --git a/drivers/atm/eni.c b/drivers/atm/eni.c
index 17d47ad03ab7..3011cf1a84a9 100644
--- a/drivers/atm/eni.c
+++ b/drivers/atm/eni.c
@@ -1034,6 +1034,7 @@ static enum enq_res do_tx(struct sk_buff *skb)
 	u32 dma_rd,dma_wr;
 	u32 size; /* in words */
 	int aal5,dma_size,i,j;
+	unsigned char skb_data3;
 
 	DPRINTK(">do_tx\n");
 	NULLCHECK(skb);
@@ -1108,8 +1109,11 @@ DPRINTK("iovcnt = %d\n",skb_shinfo(skb)->nr_frags);
 		    vcc->dev->number);
 		return enq_jam;
 	}
+	skb_data3 = skb->data[3];
 	paddr = dma_map_single(&eni_dev->pci_dev->dev,skb->data,skb->len,
 			       DMA_TO_DEVICE);
+	if (dma_mapping_error(&eni_dev->pci_dev->dev, paddr))
+		return enq_next;
 	ENI_PRV_PADDR(skb) = paddr;
 	/* prepare DMA queue entries */
 	j = 0;
@@ -1150,7 +1154,7 @@ DPRINTK("doing direct send\n"); /* @@@ well, this doesn't work anyway */
 	    (size/(ATM_CELL_PAYLOAD/4)),tx->send+tx->tx_pos*4);
 /*printk("dsc = 0x%08lx\n",(unsigned long) readl(tx->send+tx->tx_pos*4));*/
 	writel((vcc->vci << MID_SEG_VCI_SHIFT) |
-            (aal5 ? 0 : (skb->data[3] & 0xf)) |
+            (aal5 ? 0 : (skb_data3 & 0xf)) |
 	    (ATM_SKB(skb)->atm_options & ATM_ATMOPT_CLP ? MID_SEG_CLP : 0),
 	    tx->send+((tx->tx_pos+1) & (tx->words-1))*4);
 	DPRINTK("size: %d, len:%d\n",size,skb->len);
@@ -2027,21 +2031,6 @@ static int eni_ioctl(struct atm_dev *dev,unsigned int cmd,void __user *arg)
 	return dev->phy->ioctl(dev,cmd,arg);
 }
 
-
-static int eni_getsockopt(struct atm_vcc *vcc,int level,int optname,
-    void __user *optval,int optlen)
-{
-	return -EINVAL;
-}
-
-
-static int eni_setsockopt(struct atm_vcc *vcc,int level,int optname,
-    void __user *optval,unsigned int optlen)
-{
-	return -EINVAL;
-}
-
-
 static int eni_send(struct atm_vcc *vcc,struct sk_buff *skb)
 {
 	enum enq_res res;
@@ -2067,7 +2056,7 @@ static int eni_send(struct atm_vcc *vcc,struct sk_buff *skb)
 	}
 	submitted++;
 	ATM_SKB(skb)->vcc = vcc;
-	tasklet_disable(&ENI_DEV(vcc->dev)->task);
+	tasklet_disable_in_atomic(&ENI_DEV(vcc->dev)->task);
 	res = do_tx(skb);
 	tasklet_enable(&ENI_DEV(vcc->dev)->task);
 	if (res == enq_ok) return 0;
@@ -2215,8 +2204,6 @@ static const struct atmdev_ops ops = {
 	.open		= eni_open,
 	.close		= eni_close,
 	.ioctl		= eni_ioctl,
-	.getsockopt	= eni_getsockopt,
-	.setsockopt	= eni_setsockopt,
 	.send		= eni_send,
 	.phy_put	= eni_phy_put,
 	.phy_get	= eni_phy_get,
@@ -2239,7 +2226,7 @@ static int eni_init_one(struct pci_dev *pci_dev,
 
 	rc = dma_set_mask_and_coherent(&pci_dev->dev, DMA_BIT_MASK(32));
 	if (rc < 0)
-		goto out;
+		goto err_disable;
 
 	rc = -ENOMEM;
 	eni_dev = kmalloc(sizeof(struct eni_dev), GFP_KERNEL);
@@ -2275,7 +2262,8 @@ out:
 	return rc;
 
 err_eni_release:
-	eni_do_release(dev);
+	dev->phy = NULL;
+	iounmap(ENI_DEV(dev)->ioaddr);
 err_unregister:
 	atm_dev_deregister(dev);
 err_free_consistent:
@@ -2330,4 +2318,5 @@ static int __init eni_init(void)
 module_init(eni_init);
 /* @@@ since exit routine not defined, this module can not be unloaded */
 
+MODULE_DESCRIPTION("Efficient Networks ENI155P ATM NIC driver");
 MODULE_LICENSE("GPL");
diff --git a/drivers/atm/firestream.c b/drivers/atm/firestream.c
deleted file mode 100644
index cc87004d5e2d..000000000000
--- a/drivers/atm/firestream.c
+++ /dev/null
@@ -1,2055 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-/* drivers/atm/firestream.c - FireStream 155 (MB86697) and
- *                            FireStream  50 (MB86695) device driver 
- */
- 
-/* Written & (C) 2000 by R.E.Wolff@BitWizard.nl 
- * Copied snippets from zatm.c by Werner Almesberger, EPFL LRC/ICA 
- * and ambassador.c Copyright (C) 1995-1999  Madge Networks Ltd 
- */
-
-/*
-*/
-
-
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/pci.h>
-#include <linux/poison.h>
-#include <linux/errno.h>
-#include <linux/atm.h>
-#include <linux/atmdev.h>
-#include <linux/sonet.h>
-#include <linux/skbuff.h>
-#include <linux/netdevice.h>
-#include <linux/delay.h>
-#include <linux/ioport.h> /* for request_region */
-#include <linux/uio.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/capability.h>
-#include <linux/bitops.h>
-#include <linux/slab.h>
-#include <asm/byteorder.h>
-#include <asm/string.h>
-#include <asm/io.h>
-#include <linux/atomic.h>
-#include <linux/uaccess.h>
-#include <linux/wait.h>
-
-#include "firestream.h"
-
-static int loopback = 0;
-static int num=0x5a;
-
-/* According to measurements (but they look suspicious to me!) done in
- * '97, 37% of the packets are one cell in size. So it pays to have
- * buffers allocated at that size. A large jump in percentage of
- * packets occurs at packets around 536 bytes in length. So it also
- * pays to have those pre-allocated. Unfortunately, we can't fully
- * take advantage of this as the majority of the packets is likely to
- * be TCP/IP (As where obviously the measurement comes from) There the
- * link would be opened with say a 1500 byte MTU, and we can't handle
- * smaller buffers more efficiently than the larger ones. -- REW
- */
-
-/* Due to the way Linux memory management works, specifying "576" as
- * an allocation size here isn't going to help. They are allocated
- * from 1024-byte regions anyway. With the size of the sk_buffs (quite
- * large), it doesn't pay to allocate the smallest size (64) -- REW */
-
-/* This is all guesswork. Hard numbers to back this up or disprove this, 
- * are appreciated. -- REW */
-
-/* The last entry should be about 64k. However, the "buffer size" is
- * passed to the chip in a 16 bit field. I don't know how "65536"
- * would be interpreted. -- REW */
-
-#define NP FS_NR_FREE_POOLS
-static int rx_buf_sizes[NP]  = {128,  256,  512, 1024, 2048, 4096, 16384, 65520};
-/* log2:                 7     8     9    10    11    12    14     16 */
-
-#if 0
-static int rx_pool_sizes[NP] = {1024, 1024, 512, 256,  128,  64,   32,    32};
-#else
-/* debug */
-static int rx_pool_sizes[NP] = {128,  128,  128, 64,   64,   64,   32,    32};
-#endif
-/* log2:                 10    10    9    8     7     6     5      5  */
-/* sumlog2:              17    18    18   18    18    18    19     21 */
-/* mem allocated:        128k  256k  256k 256k  256k  256k  512k   2M */
-/* tot mem: almost 4M */
-
-/* NP is shorter, so that it fits on a single line. */
-#undef NP
-
-
-/* Small hardware gotcha:
-
-   The FS50 CAM (VP/VC match registers) always take the lowest channel
-   number that matches. This is not a problem.
-
-   However, they also ignore whether the channel is enabled or
-   not. This means that if you allocate channel 0 to 1.2 and then
-   channel 1 to 0.0, then disabeling channel 0 and writing 0 to the
-   match channel for channel 0 will "steal" the traffic from channel
-   1, even if you correctly disable channel 0.
-
-   Workaround: 
-
-   - When disabling channels, write an invalid VP/VC value to the
-   match register. (We use 0xffffffff, which in the worst case 
-   matches VP/VC = <maxVP>/<maxVC>, but I expect it not to match
-   anything as some "when not in use, program to 0" bits are now
-   programmed to 1...)
-
-   - Don't initialize the match registers to 0, as 0.0 is a valid
-   channel.
-*/
-
-
-/* Optimization hints and tips.
-
-   The FireStream chips are very capable of reducing the amount of
-   "interrupt-traffic" for the CPU. This driver requests an interrupt on EVERY
-   action. You could try to minimize this a bit. 
-
-   Besides that, the userspace->kernel copy and the PCI bus are the
-   performance limiting issues for this driver.
-
-   You could queue up a bunch of outgoing packets without telling the
-   FireStream. I'm not sure that's going to win you much though. The
-   Linux layer won't tell us in advance when it's not going to give us
-   any more packets in a while. So this is tricky to implement right without
-   introducing extra delays. 
-  
-   -- REW
- */
-
-
-
-
-/* The strings that define what the RX queue entry is all about. */
-/* Fujitsu: Please tell me which ones can have a pointer to a 
-   freepool descriptor! */
-static char *res_strings[] = {
-	"RX OK: streaming not EOP", 
-	"RX OK: streaming EOP", 
-	"RX OK: Single buffer packet", 
-	"RX OK: packet mode", 
-	"RX OK: F4 OAM (end to end)", 
-	"RX OK: F4 OAM (Segment)", 
-	"RX OK: F5 OAM (end to end)", 
-	"RX OK: F5 OAM (Segment)", 
-	"RX OK: RM cell", 
-	"RX OK: TRANSP cell", 
-	"RX OK: TRANSPC cell", 
-	"Unmatched cell", 
-	"reserved 12", 
-	"reserved 13", 
-	"reserved 14", 
-	"Unrecognized cell", 
-	"reserved 16", 
-	"reassembly abort: AAL5 abort", 
-	"packet purged", 
-	"packet ageing timeout", 
-	"channel ageing timeout", 
-	"calculated length error", 
-	"programmed length limit error", 
-	"aal5 crc32 error", 
-	"oam transp or transpc crc10 error", 
-	"reserved 25", 
-	"reserved 26", 
-	"reserved 27", 
-	"reserved 28", 
-	"reserved 29", 
-	"reserved 30", /* FIXME: The strings between 30-40 might be wrong. */
-	"reassembly abort: no buffers", 
-	"receive buffer overflow", 
-	"change in GFC", 
-	"receive buffer full", 
-	"low priority discard - no receive descriptor", 
-	"low priority discard - missing end of packet", 
-	"reserved 37",
-	"reserved 38",
-	"reserved 39",
-	"reserved 40",
-	"reserved 41", 
-	"reserved 42", 
-	"reserved 43", 
-	"reserved 44", 
-	"reserved 45", 
-	"reserved 46", 
-	"reserved 47", 
-	"reserved 48", 
-	"reserved 49", 
-	"reserved 50", 
-	"reserved 51", 
-	"reserved 52", 
-	"reserved 53", 
-	"reserved 54", 
-	"reserved 55", 
-	"reserved 56", 
-	"reserved 57", 
-	"reserved 58", 
-	"reserved 59", 
-	"reserved 60", 
-	"reserved 61", 
-	"reserved 62", 
-	"reserved 63", 
-};  
-
-static char *irq_bitname[] = {
-	"LPCO",
-	"DPCO",
-	"RBRQ0_W",
-	"RBRQ1_W",
-	"RBRQ2_W",
-	"RBRQ3_W",
-	"RBRQ0_NF",
-	"RBRQ1_NF",
-	"RBRQ2_NF",
-	"RBRQ3_NF",
-	"BFP_SC",
-	"INIT",
-	"INIT_ERR",
-	"USCEO",
-	"UPEC0",
-	"VPFCO",
-	"CRCCO",
-	"HECO",
-	"TBRQ_W",
-	"TBRQ_NF",
-	"CTPQ_E",
-	"GFC_C0",
-	"PCI_FTL",
-	"CSQ_W",
-	"CSQ_NF",
-	"EXT_INT",
-	"RXDMA_S"
-};
-
-
-#define PHY_EOF -1
-#define PHY_CLEARALL -2
-
-struct reginit_item {
-	int reg, val;
-};
-
-
-static struct reginit_item PHY_NTC_INIT[] = {
-	{ PHY_CLEARALL, 0x40 }, 
-	{ 0x12,  0x0001 },
-	{ 0x13,  0x7605 },
-	{ 0x1A,  0x0001 },
-	{ 0x1B,  0x0005 },
-	{ 0x38,  0x0003 },
-	{ 0x39,  0x0006 },   /* changed here to make loopback */
-	{ 0x01,  0x5262 },
-	{ 0x15,  0x0213 },
-	{ 0x00,  0x0003 },
-	{ PHY_EOF, 0},    /* -1 signals end of list */
-};
-
-
-/* Safetyfeature: If the card interrupts more than this number of times
-   in a jiffy (1/100th of a second) then we just disable the interrupt and
-   print a message. This prevents the system from hanging. 
-
-   150000 packets per second is close to the limit a PC is going to have
-   anyway. We therefore have to disable this for production. -- REW */
-#undef IRQ_RATE_LIMIT // 100
-
-/* Interrupts work now. Unlike serial cards, ATM cards don't work all
-   that great without interrupts. -- REW */
-#undef FS_POLL_FREQ // 100
-
-/* 
-   This driver can spew a whole lot of debugging output at you. If you
-   need maximum performance, you should disable the DEBUG define. To
-   aid in debugging in the field, I'm leaving the compile-time debug
-   features enabled, and disable them "runtime". That allows me to
-   instruct people with problems to enable debugging without requiring
-   them to recompile... -- REW
-*/
-#define DEBUG
-
-#ifdef DEBUG
-#define fs_dprintk(f, str...) if (fs_debug & f) printk (str)
-#else
-#define fs_dprintk(f, str...) /* nothing */
-#endif
-
-
-static int fs_keystream = 0;
-
-#ifdef DEBUG
-/* I didn't forget to set this to zero before shipping. Hit me with a stick 
-   if you get this with the debug default not set to zero again. -- REW */
-static int fs_debug = 0;
-#else
-#define fs_debug 0
-#endif
-
-#ifdef MODULE
-#ifdef DEBUG 
-module_param(fs_debug, int, 0644);
-#endif
-module_param(loopback, int, 0);
-module_param(num, int, 0);
-module_param(fs_keystream, int, 0);
-/* XXX Add rx_buf_sizes, and rx_pool_sizes As per request Amar. -- REW */
-#endif
-
-
-#define FS_DEBUG_FLOW    0x00000001
-#define FS_DEBUG_OPEN    0x00000002
-#define FS_DEBUG_QUEUE   0x00000004
-#define FS_DEBUG_IRQ     0x00000008
-#define FS_DEBUG_INIT    0x00000010
-#define FS_DEBUG_SEND    0x00000020
-#define FS_DEBUG_PHY     0x00000040
-#define FS_DEBUG_CLEANUP 0x00000080
-#define FS_DEBUG_QOS     0x00000100
-#define FS_DEBUG_TXQ     0x00000200
-#define FS_DEBUG_ALLOC   0x00000400
-#define FS_DEBUG_TXMEM   0x00000800
-#define FS_DEBUG_QSIZE   0x00001000
-
-
-#define func_enter() fs_dprintk(FS_DEBUG_FLOW, "fs: enter %s\n", __func__)
-#define func_exit()  fs_dprintk(FS_DEBUG_FLOW, "fs: exit  %s\n", __func__)
-
-
-static struct fs_dev *fs_boards = NULL;
-
-#ifdef DEBUG
-
-static void my_hd (void *addr, int len)
-{
-	int j, ch;
-	unsigned char *ptr = addr;
-
-	while (len > 0) {
-		printk ("%p ", ptr);
-		for (j=0;j < ((len < 16)?len:16);j++) {
-			printk ("%02x %s", ptr[j], (j==7)?" ":"");
-		}
-		for (  ;j < 16;j++) {
-			printk ("   %s", (j==7)?" ":"");
-		}
-		for (j=0;j < ((len < 16)?len:16);j++) {
-			ch = ptr[j];
-			printk ("%c", (ch < 0x20)?'.':((ch > 0x7f)?'.':ch));
-		}
-		printk ("\n");
-		ptr += 16;
-		len -= 16;
-	}
-}
-#else /* DEBUG */
-static void my_hd (void *addr, int len){}
-#endif /* DEBUG */
-
-/********** free an skb (as per ATM device driver documentation) **********/
-
-/* Hmm. If this is ATM specific, why isn't there an ATM routine for this?
- * I copied it over from the ambassador driver. -- REW */
-
-static inline void fs_kfree_skb (struct sk_buff * skb) 
-{
-	if (ATM_SKB(skb)->vcc->pop)
-		ATM_SKB(skb)->vcc->pop (ATM_SKB(skb)->vcc, skb);
-	else
-		dev_kfree_skb_any (skb);
-}
-
-
-
-
-/* It seems the ATM forum recommends this horribly complicated 16bit
- * floating point format. Turns out the Ambassador uses the exact same
- * encoding. I just copied it over. If Mitch agrees, I'll move it over
- * to the atm_misc file or something like that. (and remove it from 
- * here and the ambassador driver) -- REW
- */
-
-/* The good thing about this format is that it is monotonic. So, 
-   a conversion routine need not be very complicated. To be able to
-   round "nearest" we need to take along a few extra bits. Lets
-   put these after 16 bits, so that we can just return the top 16
-   bits of the 32bit number as the result:
-
-   int mr (unsigned int rate, int r) 
-     {
-     int e = 16+9;
-     static int round[4]={0, 0, 0xffff, 0x8000};
-     if (!rate) return 0;
-     while (rate & 0xfc000000) {
-       rate >>= 1;
-       e++;
-     }
-     while (! (rate & 0xfe000000)) {
-       rate <<= 1;
-       e--;
-     }
-
-// Now the mantissa is in positions bit 16-25. Excepf for the "hidden 1" that's in bit 26.
-     rate &= ~0x02000000;
-// Next add in the exponent
-     rate |= e << (16+9);
-// And perform the rounding:
-     return (rate + round[r]) >> 16;
-   }
-
-   14 lines-of-code. Compare that with the 120 that the Ambassador
-   guys needed. (would be 8 lines shorter if I'd try to really reduce
-   the number of lines:
-
-   int mr (unsigned int rate, int r) 
-   {
-     int e = 16+9;
-     static int round[4]={0, 0, 0xffff, 0x8000};
-     if (!rate) return 0;
-     for (;  rate & 0xfc000000 ;rate >>= 1, e++);
-     for (;!(rate & 0xfe000000);rate <<= 1, e--);
-     return ((rate & ~0x02000000) | (e << (16+9)) + round[r]) >> 16;
-   }
-
-   Exercise for the reader: Remove one more line-of-code, without
-   cheating. (Just joining two lines is cheating). (I know it's
-   possible, don't think you've beat me if you found it... If you
-   manage to lose two lines or more, keep me updated! ;-)
-
-   -- REW */
-
-
-#define ROUND_UP      1
-#define ROUND_DOWN    2
-#define ROUND_NEAREST 3
-/********** make rate (not quite as much fun as Horizon) **********/
-
-static int make_rate(unsigned int rate, int r,
-		      u16 *bits, unsigned int *actual)
-{
-	unsigned char exp = -1; /* hush gcc */
-	unsigned int man = -1;  /* hush gcc */
-  
-	fs_dprintk (FS_DEBUG_QOS, "make_rate %u", rate);
-  
-	/* rates in cells per second, ITU format (nasty 16-bit floating-point)
-	   given 5-bit e and 9-bit m:
-	   rate = EITHER (1+m/2^9)*2^e    OR 0
-	   bits = EITHER 1<<14 | e<<9 | m OR 0
-	   (bit 15 is "reserved", bit 14 "non-zero")
-	   smallest rate is 0 (special representation)
-	   largest rate is (1+511/512)*2^31 = 4290772992 (< 2^32-1)
-	   smallest non-zero rate is (1+0/512)*2^0 = 1 (> 0)
-	   simple algorithm:
-	   find position of top bit, this gives e
-	   remove top bit and shift (rounding if feeling clever) by 9-e
-	*/
-	/* Ambassador ucode bug: please don't set bit 14! so 0 rate not
-	   representable. // This should move into the ambassador driver
-	   when properly merged. -- REW */
-  
-	if (rate > 0xffc00000U) {
-		/* larger than largest representable rate */
-    
-		if (r == ROUND_UP) {
-			return -EINVAL;
-		} else {
-			exp = 31;
-			man = 511;
-		}
-    
-	} else if (rate) {
-		/* representable rate */
-    
-		exp = 31;
-		man = rate;
-    
-		/* invariant: rate = man*2^(exp-31) */
-		while (!(man & (1<<31))) {
-			exp = exp - 1;
-			man = man<<1;
-		}
-    
-		/* man has top bit set
-		   rate = (2^31+(man-2^31))*2^(exp-31)
-		   rate = (1+(man-2^31)/2^31)*2^exp 
-		*/
-		man = man<<1;
-		man &= 0xffffffffU; /* a nop on 32-bit systems */
-		/* rate = (1+man/2^32)*2^exp
-    
-		   exp is in the range 0 to 31, man is in the range 0 to 2^32-1
-		   time to lose significance... we want m in the range 0 to 2^9-1
-		   rounding presents a minor problem... we first decide which way
-		   we are rounding (based on given rounding direction and possibly
-		   the bits of the mantissa that are to be discarded).
-		*/
-
-		switch (r) {
-		case ROUND_DOWN: {
-			/* just truncate */
-			man = man>>(32-9);
-			break;
-		}
-		case ROUND_UP: {
-			/* check all bits that we are discarding */
-			if (man & (~0U>>9)) {
-				man = (man>>(32-9)) + 1;
-				if (man == (1<<9)) {
-					/* no need to check for round up outside of range */
-					man = 0;
-					exp += 1;
-				}
-			} else {
-				man = (man>>(32-9));
-			}
-			break;
-		}
-		case ROUND_NEAREST: {
-			/* check msb that we are discarding */
-			if (man & (1<<(32-9-1))) {
-				man = (man>>(32-9)) + 1;
-				if (man == (1<<9)) {
-					/* no need to check for round up outside of range */
-					man = 0;
-					exp += 1;
-				}
-			} else {
-				man = (man>>(32-9));
-			}
-			break;
-		}
-		}
-    
-	} else {
-		/* zero rate - not representable */
-    
-		if (r == ROUND_DOWN) {
-			return -EINVAL;
-		} else {
-			exp = 0;
-			man = 0;
-		}
-	}
-  
-	fs_dprintk (FS_DEBUG_QOS, "rate: man=%u, exp=%hu", man, exp);
-  
-	if (bits)
-		*bits = /* (1<<14) | */ (exp<<9) | man;
-  
-	if (actual)
-		*actual = (exp >= 9)
-			? (1 << exp) + (man << (exp-9))
-			: (1 << exp) + ((man + (1<<(9-exp-1))) >> (9-exp));
-  
-	return 0;
-}
-
-
-
-
-/* FireStream access routines */
-/* For DEEP-DOWN debugging these can be rigged to intercept accesses to
-   certain registers or to just log all accesses. */
-
-static inline void write_fs (struct fs_dev *dev, int offset, u32 val)
-{
-	writel (val, dev->base + offset);
-}
-
-
-static inline u32  read_fs (struct fs_dev *dev, int offset)
-{
-	return readl (dev->base + offset);
-}
-
-
-
-static inline struct FS_QENTRY *get_qentry (struct fs_dev *dev, struct queue *q)
-{
-	return bus_to_virt (read_fs (dev, Q_WP(q->offset)) & Q_ADDR_MASK);
-}
-
-
-static void submit_qentry (struct fs_dev *dev, struct queue *q, struct FS_QENTRY *qe)
-{
-	u32 wp;
-	struct FS_QENTRY *cqe;
-
-	/* XXX Sanity check: the write pointer can be checked to be 
-	   still the same as the value passed as qe... -- REW */
-	/*  udelay (5); */
-	while ((wp = read_fs (dev, Q_WP (q->offset))) & Q_FULL) {
-		fs_dprintk (FS_DEBUG_TXQ, "Found queue at %x full. Waiting.\n", 
-			    q->offset);
-		schedule ();
-	}
-
-	wp &= ~0xf;
-	cqe = bus_to_virt (wp);
-	if (qe != cqe) {
-		fs_dprintk (FS_DEBUG_TXQ, "q mismatch! %p %p\n", qe, cqe);
-	}
-
-	write_fs (dev, Q_WP(q->offset), Q_INCWRAP);
-
-	{
-		static int c;
-		if (!(c++ % 100))
-			{
-				int rp, wp;
-				rp =  read_fs (dev, Q_RP(q->offset));
-				wp =  read_fs (dev, Q_WP(q->offset));
-				fs_dprintk (FS_DEBUG_TXQ, "q at %d: %x-%x: %x entries.\n", 
-					    q->offset, rp, wp, wp-rp);
-			}
-	}
-}
-
-#ifdef DEBUG_EXTRA
-static struct FS_QENTRY pq[60];
-static int qp;
-
-static struct FS_BPENTRY dq[60];
-static int qd;
-static void *da[60];
-#endif 
-
-static void submit_queue (struct fs_dev *dev, struct queue *q, 
-			  u32 cmd, u32 p1, u32 p2, u32 p3)
-{
-	struct FS_QENTRY *qe;
-
-	qe = get_qentry (dev, q);
-	qe->cmd = cmd;
-	qe->p0 = p1;
-	qe->p1 = p2;
-	qe->p2 = p3;
-	submit_qentry (dev,  q, qe);
-
-#ifdef DEBUG_EXTRA
-	pq[qp].cmd = cmd;
-	pq[qp].p0 = p1;
-	pq[qp].p1 = p2;
-	pq[qp].p2 = p3;
-	qp++;
-	if (qp >= 60) qp = 0;
-#endif
-}
-
-/* Test the "other" way one day... -- REW */
-#if 1
-#define submit_command submit_queue
-#else
-
-static void submit_command (struct fs_dev *dev, struct queue *q, 
-			    u32 cmd, u32 p1, u32 p2, u32 p3)
-{
-	write_fs (dev, CMDR0, cmd);
-	write_fs (dev, CMDR1, p1);
-	write_fs (dev, CMDR2, p2);
-	write_fs (dev, CMDR3, p3);
-}
-#endif
-
-
-
-static void process_return_queue (struct fs_dev *dev, struct queue *q)
-{
-	long rq;
-	struct FS_QENTRY *qe;
-	void *tc;
-  
-	while (!((rq = read_fs (dev, Q_RP(q->offset))) & Q_EMPTY)) {
-		fs_dprintk (FS_DEBUG_QUEUE, "reaping return queue entry at %lx\n", rq); 
-		qe = bus_to_virt (rq);
-    
-		fs_dprintk (FS_DEBUG_QUEUE, "queue entry: %08x %08x %08x %08x. (%d)\n", 
-			    qe->cmd, qe->p0, qe->p1, qe->p2, STATUS_CODE (qe));
-
-		switch (STATUS_CODE (qe)) {
-		case 5:
-			tc = bus_to_virt (qe->p0);
-			fs_dprintk (FS_DEBUG_ALLOC, "Free tc: %p\n", tc);
-			kfree (tc);
-			break;
-		}
-    
-		write_fs (dev, Q_RP(q->offset), Q_INCWRAP);
-	}
-}
-
-
-static void process_txdone_queue (struct fs_dev *dev, struct queue *q)
-{
-	long rq;
-	long tmp;
-	struct FS_QENTRY *qe;
-	struct sk_buff *skb;
-	struct FS_BPENTRY *td;
-
-	while (!((rq = read_fs (dev, Q_RP(q->offset))) & Q_EMPTY)) {
-		fs_dprintk (FS_DEBUG_QUEUE, "reaping txdone entry at %lx\n", rq); 
-		qe = bus_to_virt (rq);
-    
-		fs_dprintk (FS_DEBUG_QUEUE, "queue entry: %08x %08x %08x %08x: %d\n", 
-			    qe->cmd, qe->p0, qe->p1, qe->p2, STATUS_CODE (qe));
-
-		if (STATUS_CODE (qe) != 2)
-			fs_dprintk (FS_DEBUG_TXMEM, "queue entry: %08x %08x %08x %08x: %d\n", 
-				    qe->cmd, qe->p0, qe->p1, qe->p2, STATUS_CODE (qe));
-
-
-		switch (STATUS_CODE (qe)) {
-		case 0x01: /* This is for AAL0 where we put the chip in streaming mode */
-			/* Fall through */
-		case 0x02:
-			/* Process a real txdone entry. */
-			tmp = qe->p0;
-			if (tmp & 0x0f)
-				printk (KERN_WARNING "td not aligned: %ld\n", tmp);
-			tmp &= ~0x0f;
-			td = bus_to_virt (tmp);
-
-			fs_dprintk (FS_DEBUG_QUEUE, "Pool entry: %08x %08x %08x %08x %p.\n", 
-				    td->flags, td->next, td->bsa, td->aal_bufsize, td->skb );
-      
-			skb = td->skb;
-			if (skb == FS_VCC (ATM_SKB(skb)->vcc)->last_skb) {
-				FS_VCC (ATM_SKB(skb)->vcc)->last_skb = NULL;
-				wake_up_interruptible (& FS_VCC (ATM_SKB(skb)->vcc)->close_wait);
-			}
-			td->dev->ntxpckts--;
-
-			{
-				static int c=0;
-	
-				if (!(c++ % 100)) {
-					fs_dprintk (FS_DEBUG_QSIZE, "[%d]", td->dev->ntxpckts);
-				}
-			}
-
-			atomic_inc(&ATM_SKB(skb)->vcc->stats->tx);
-
-			fs_dprintk (FS_DEBUG_TXMEM, "i");
-			fs_dprintk (FS_DEBUG_ALLOC, "Free t-skb: %p\n", skb);
-			fs_kfree_skb (skb);
-
-			fs_dprintk (FS_DEBUG_ALLOC, "Free trans-d: %p\n", td); 
-			memset (td, ATM_POISON_FREE, sizeof(struct FS_BPENTRY));
-			kfree (td);
-			break;
-		default:
-			/* Here we get the tx purge inhibit command ... */
-			/* Action, I believe, is "don't do anything". -- REW */
-			;
-		}
-    
-		write_fs (dev, Q_RP(q->offset), Q_INCWRAP);
-	}
-}
-
-
-static void process_incoming (struct fs_dev *dev, struct queue *q)
-{
-	long rq;
-	struct FS_QENTRY *qe;
-	struct FS_BPENTRY *pe;    
-	struct sk_buff *skb;
-	unsigned int channo;
-	struct atm_vcc *atm_vcc;
-
-	while (!((rq = read_fs (dev, Q_RP(q->offset))) & Q_EMPTY)) {
-		fs_dprintk (FS_DEBUG_QUEUE, "reaping incoming queue entry at %lx\n", rq); 
-		qe = bus_to_virt (rq);
-    
-		fs_dprintk (FS_DEBUG_QUEUE, "queue entry: %08x %08x %08x %08x.  ", 
-			    qe->cmd, qe->p0, qe->p1, qe->p2);
-
-		fs_dprintk (FS_DEBUG_QUEUE, "-> %x: %s\n", 
-			    STATUS_CODE (qe), 
-			    res_strings[STATUS_CODE(qe)]);
-
-		pe = bus_to_virt (qe->p0);
-		fs_dprintk (FS_DEBUG_QUEUE, "Pool entry: %08x %08x %08x %08x %p %p.\n", 
-			    pe->flags, pe->next, pe->bsa, pe->aal_bufsize, 
-			    pe->skb, pe->fp);
-      
-		channo = qe->cmd & 0xffff;
-
-		if (channo < dev->nchannels)
-			atm_vcc = dev->atm_vccs[channo];
-		else
-			atm_vcc = NULL;
-
-		/* Single buffer packet */
-		switch (STATUS_CODE (qe)) {
-		case 0x1:
-			/* Fall through for streaming mode */
-		case 0x2:/* Packet received OK.... */
-			if (atm_vcc) {
-				skb = pe->skb;
-				pe->fp->n--;
-#if 0
-				fs_dprintk (FS_DEBUG_QUEUE, "Got skb: %p\n", skb);
-				if (FS_DEBUG_QUEUE & fs_debug) my_hd (bus_to_virt (pe->bsa), 0x20);
-#endif
-				skb_put (skb, qe->p1 & 0xffff); 
-				ATM_SKB(skb)->vcc = atm_vcc;
-				atomic_inc(&atm_vcc->stats->rx);
-				__net_timestamp(skb);
-				fs_dprintk (FS_DEBUG_ALLOC, "Free rec-skb: %p (pushed)\n", skb);
-				atm_vcc->push (atm_vcc, skb);
-				fs_dprintk (FS_DEBUG_ALLOC, "Free rec-d: %p\n", pe);
-				kfree (pe);
-			} else {
-				printk (KERN_ERR "Got a receive on a non-open channel %d.\n", channo);
-			}
-			break;
-		case 0x17:/* AAL 5 CRC32 error. IFF the length field is nonzero, a buffer
-			     has been consumed and needs to be processed. -- REW */
-			if (qe->p1 & 0xffff) {
-				pe = bus_to_virt (qe->p0);
-				pe->fp->n--;
-				fs_dprintk (FS_DEBUG_ALLOC, "Free rec-skb: %p\n", pe->skb);
-				dev_kfree_skb_any (pe->skb);
-				fs_dprintk (FS_DEBUG_ALLOC, "Free rec-d: %p\n", pe);
-				kfree (pe);
-			}
-			if (atm_vcc)
-				atomic_inc(&atm_vcc->stats->rx_drop);
-			break;
-		case 0x1f: /*  Reassembly abort: no buffers. */
-			/* Silently increment error counter. */
-			if (atm_vcc)
-				atomic_inc(&atm_vcc->stats->rx_drop);
-			break;
-		default: /* Hmm. Haven't written the code to handle the others yet... -- REW */
-			printk (KERN_WARNING "Don't know what to do with RX status %x: %s.\n", 
-				STATUS_CODE(qe), res_strings[STATUS_CODE (qe)]);
-		}
-		write_fs (dev, Q_RP(q->offset), Q_INCWRAP);
-	}
-}
-
-
-
-#define DO_DIRECTION(tp) ((tp)->traffic_class != ATM_NONE)
-
-static int fs_open(struct atm_vcc *atm_vcc)
-{
-	struct fs_dev *dev;
-	struct fs_vcc *vcc;
-	struct fs_transmit_config *tc;
-	struct atm_trafprm * txtp;
-	struct atm_trafprm * rxtp;
-	/*  struct fs_receive_config *rc;*/
-	/*  struct FS_QENTRY *qe; */
-	int error;
-	int bfp;
-	int to;
-	unsigned short tmc0;
-	short vpi = atm_vcc->vpi;
-	int vci = atm_vcc->vci;
-
-	func_enter ();
-
-	dev = FS_DEV(atm_vcc->dev);
-	fs_dprintk (FS_DEBUG_OPEN, "fs: open on dev: %p, vcc at %p\n", 
-		    dev, atm_vcc);
-
-	if (vci != ATM_VPI_UNSPEC && vpi != ATM_VCI_UNSPEC)
-		set_bit(ATM_VF_ADDR, &atm_vcc->flags);
-
-	if ((atm_vcc->qos.aal != ATM_AAL5) &&
-	    (atm_vcc->qos.aal != ATM_AAL2))
-	  return -EINVAL; /* XXX AAL0 */
-
-	fs_dprintk (FS_DEBUG_OPEN, "fs: (itf %d): open %d.%d\n", 
-		    atm_vcc->dev->number, atm_vcc->vpi, atm_vcc->vci);	
-
-	/* XXX handle qos parameters (rate limiting) ? */
-
-	vcc = kmalloc(sizeof(struct fs_vcc), GFP_KERNEL);
-	fs_dprintk (FS_DEBUG_ALLOC, "Alloc VCC: %p(%zd)\n", vcc, sizeof(struct fs_vcc));
-	if (!vcc) {
-		clear_bit(ATM_VF_ADDR, &atm_vcc->flags);
-		return -ENOMEM;
-	}
-  
-	atm_vcc->dev_data = vcc;
-	vcc->last_skb = NULL;
-
-	init_waitqueue_head (&vcc->close_wait);
-
-	txtp = &atm_vcc->qos.txtp;
-	rxtp = &atm_vcc->qos.rxtp;
-
-	if (!test_bit(ATM_VF_PARTIAL, &atm_vcc->flags)) {
-		if (IS_FS50(dev)) {
-			/* Increment the channel numer: take a free one next time.  */
-			for (to=33;to;to--, dev->channo++) {
-				/* We only have 32 channels */
-				if (dev->channo >= 32)
-					dev->channo = 0;
-				/* If we need to do RX, AND the RX is inuse, try the next */
-				if (DO_DIRECTION(rxtp) && dev->atm_vccs[dev->channo])
-					continue;
-				/* If we need to do TX, AND the TX is inuse, try the next */
-				if (DO_DIRECTION(txtp) && test_bit (dev->channo, dev->tx_inuse))
-					continue;
-				/* Ok, both are free! (or not needed) */
-				break;
-			}
-			if (!to) {
-				printk ("No more free channels for FS50..\n");
-				kfree(vcc);
-				return -EBUSY;
-			}
-			vcc->channo = dev->channo;
-			dev->channo &= dev->channel_mask;
-      
-		} else {
-			vcc->channo = (vpi << FS155_VCI_BITS) | (vci);
-			if (((DO_DIRECTION(rxtp) && dev->atm_vccs[vcc->channo])) ||
-			    ( DO_DIRECTION(txtp) && test_bit (vcc->channo, dev->tx_inuse))) {
-				printk ("Channel is in use for FS155.\n");
-				kfree(vcc);
-				return -EBUSY;
-			}
-		}
-		fs_dprintk (FS_DEBUG_OPEN, "OK. Allocated channel %x(%d).\n", 
-			    vcc->channo, vcc->channo);
-	}
-
-	if (DO_DIRECTION (txtp)) {
-		tc = kmalloc (sizeof (struct fs_transmit_config), GFP_KERNEL);
-		fs_dprintk (FS_DEBUG_ALLOC, "Alloc tc: %p(%zd)\n",
-			    tc, sizeof (struct fs_transmit_config));
-		if (!tc) {
-			fs_dprintk (FS_DEBUG_OPEN, "fs: can't alloc transmit_config.\n");
-			kfree(vcc);
-			return -ENOMEM;
-		}
-
-		/* Allocate the "open" entry from the high priority txq. This makes
-		   it most likely that the chip will notice it. It also prevents us
-		   from having to wait for completion. On the other hand, we may
-		   need to wait for completion anyway, to see if it completed
-		   successfully. */
-
-		switch (atm_vcc->qos.aal) {
-		case ATM_AAL2:
-		case ATM_AAL0:
-		  tc->flags = 0
-		    | TC_FLAGS_TRANSPARENT_PAYLOAD
-		    | TC_FLAGS_PACKET
-		    | (1 << 28)
-		    | TC_FLAGS_TYPE_UBR /* XXX Change to VBR -- PVDL */
-		    | TC_FLAGS_CAL0;
-		  break;
-		case ATM_AAL5:
-		  tc->flags = 0
-			| TC_FLAGS_AAL5
-			| TC_FLAGS_PACKET  /* ??? */
-			| TC_FLAGS_TYPE_CBR
-			| TC_FLAGS_CAL0;
-		  break;
-		default:
-			printk ("Unknown aal: %d\n", atm_vcc->qos.aal);
-			tc->flags = 0;
-		}
-		/* Docs are vague about this atm_hdr field. By the way, the FS
-		 * chip makes odd errors if lower bits are set.... -- REW */
-		tc->atm_hdr =  (vpi << 20) | (vci << 4); 
-		tmc0 = 0;
-		{
-			int pcr = atm_pcr_goal (txtp);
-
-			fs_dprintk (FS_DEBUG_OPEN, "pcr = %d.\n", pcr);
-
-			/* XXX Hmm. officially we're only allowed to do this if rounding 
-			   is round_down -- REW */
-			if (IS_FS50(dev)) {
-				if (pcr > 51840000/53/8)  pcr = 51840000/53/8;
-			} else {
-				if (pcr > 155520000/53/8) pcr = 155520000/53/8;
-			}
-			if (!pcr) {
-				/* no rate cap */
-				tmc0 = IS_FS50(dev)?0x61BE:0x64c9; /* Just copied over the bits from Fujitsu -- REW */
-			} else {
-				int r;
-				if (pcr < 0) {
-					r = ROUND_DOWN;
-					pcr = -pcr;
-				} else {
-					r = ROUND_UP;
-				}
-				error = make_rate (pcr, r, &tmc0, NULL);
-				if (error) {
-					kfree(tc);
-					return error;
-				}
-			}
-			fs_dprintk (FS_DEBUG_OPEN, "pcr = %d.\n", pcr);
-		}
-      
-		tc->TMC[0] = tmc0 | 0x4000;
-		tc->TMC[1] = 0; /* Unused */
-		tc->TMC[2] = 0; /* Unused */
-		tc->TMC[3] = 0; /* Unused */
-    
-		tc->spec = 0;    /* UTOPIA address, UDF, HEC: Unused -> 0 */
-		tc->rtag[0] = 0; /* What should I do with routing tags??? 
-				    -- Not used -- AS -- Thanks -- REW*/
-		tc->rtag[1] = 0;
-		tc->rtag[2] = 0;
-
-		if (fs_debug & FS_DEBUG_OPEN) {
-			fs_dprintk (FS_DEBUG_OPEN, "TX config record:\n");
-			my_hd (tc, sizeof (*tc));
-		}
-
-		/* We now use the "submit_command" function to submit commands to
-		   the firestream. There is a define up near the definition of
-		   that routine that switches this routine between immediate write
-		   to the immediate command registers and queuing the commands in
-		   the HPTXQ for execution. This last technique might be more
-		   efficient if we know we're going to submit a whole lot of
-		   commands in one go, but this driver is not setup to be able to
-		   use such a construct. So it probably doen't matter much right
-		   now. -- REW */
-    
-		/* The command is IMMediate and INQueue. The parameters are out-of-line.. */
-		submit_command (dev, &dev->hp_txq, 
-				QE_CMD_CONFIG_TX | QE_CMD_IMM_INQ | vcc->channo,
-				virt_to_bus (tc), 0, 0);
-
-		submit_command (dev, &dev->hp_txq, 
-				QE_CMD_TX_EN | QE_CMD_IMM_INQ | vcc->channo,
-				0, 0, 0);
-		set_bit (vcc->channo, dev->tx_inuse);
-	}
-
-	if (DO_DIRECTION (rxtp)) {
-		dev->atm_vccs[vcc->channo] = atm_vcc;
-
-		for (bfp = 0;bfp < FS_NR_FREE_POOLS; bfp++)
-			if (atm_vcc->qos.rxtp.max_sdu <= dev->rx_fp[bfp].bufsize) break;
-		if (bfp >= FS_NR_FREE_POOLS) {
-			fs_dprintk (FS_DEBUG_OPEN, "No free pool fits sdu: %d.\n", 
-				    atm_vcc->qos.rxtp.max_sdu);
-			/* XXX Cleanup? -- Would just calling fs_close work??? -- REW */
-
-			/* XXX clear tx inuse. Close TX part? */
-			dev->atm_vccs[vcc->channo] = NULL;
-			kfree (vcc);
-			return -EINVAL;
-		}
-
-		switch (atm_vcc->qos.aal) {
-		case ATM_AAL0:
-		case ATM_AAL2:
-			submit_command (dev, &dev->hp_txq,
-					QE_CMD_CONFIG_RX | QE_CMD_IMM_INQ | vcc->channo,
-					RC_FLAGS_TRANSP |
-					RC_FLAGS_BFPS_BFP * bfp |
-					RC_FLAGS_RXBM_PSB, 0, 0);
-			break;
-		case ATM_AAL5:
-			submit_command (dev, &dev->hp_txq,
-					QE_CMD_CONFIG_RX | QE_CMD_IMM_INQ | vcc->channo,
-					RC_FLAGS_AAL5 |
-					RC_FLAGS_BFPS_BFP * bfp |
-					RC_FLAGS_RXBM_PSB, 0, 0);
-			break;
-		}
-		if (IS_FS50 (dev)) {
-			submit_command (dev, &dev->hp_txq, 
-					QE_CMD_REG_WR | QE_CMD_IMM_INQ,
-					0x80 + vcc->channo,
-					(vpi << 16) | vci, 0 ); /* XXX -- Use defines. */
-		}
-		submit_command (dev, &dev->hp_txq, 
-				QE_CMD_RX_EN | QE_CMD_IMM_INQ | vcc->channo,
-				0, 0, 0);
-	}
-    
-	/* Indicate we're done! */
-	set_bit(ATM_VF_READY, &atm_vcc->flags);
-
-	func_exit ();
-	return 0;
-}
-
-
-static void fs_close(struct atm_vcc *atm_vcc)
-{
-	struct fs_dev *dev = FS_DEV (atm_vcc->dev);
-	struct fs_vcc *vcc = FS_VCC (atm_vcc);
-	struct atm_trafprm * txtp;
-	struct atm_trafprm * rxtp;
-
-	func_enter ();
-
-	clear_bit(ATM_VF_READY, &atm_vcc->flags);
-
-	fs_dprintk (FS_DEBUG_QSIZE, "--==**[%d]**==--", dev->ntxpckts);
-	if (vcc->last_skb) {
-		fs_dprintk (FS_DEBUG_QUEUE, "Waiting for skb %p to be sent.\n", 
-			    vcc->last_skb);
-		/* We're going to wait for the last packet to get sent on this VC. It would
-		   be impolite not to send them don't you think? 
-		   XXX
-		   We don't know which packets didn't get sent. So if we get interrupted in 
-		   this sleep_on, we'll lose any reference to these packets. Memory leak!
-		   On the other hand, it's awfully convenient that we can abort a "close" that
-		   is taking too long. Maybe just use non-interruptible sleep on? -- REW */
-		wait_event_interruptible(vcc->close_wait, !vcc->last_skb);
-	}
-
-	txtp = &atm_vcc->qos.txtp;
-	rxtp = &atm_vcc->qos.rxtp;
-  
-
-	/* See App note XXX (Unpublished as of now) for the reason for the 
-	   removal of the "CMD_IMM_INQ" part of the TX_PURGE_INH... -- REW */
-
-	if (DO_DIRECTION (txtp)) {
-		submit_command (dev,  &dev->hp_txq,
-				QE_CMD_TX_PURGE_INH | /*QE_CMD_IMM_INQ|*/ vcc->channo, 0,0,0);
-		clear_bit (vcc->channo, dev->tx_inuse);
-	}
-
-	if (DO_DIRECTION (rxtp)) {
-		submit_command (dev,  &dev->hp_txq,
-				QE_CMD_RX_PURGE_INH | QE_CMD_IMM_INQ | vcc->channo, 0,0,0);
-		dev->atm_vccs [vcc->channo] = NULL;
-  
-		/* This means that this is configured as a receive channel */
-		if (IS_FS50 (dev)) {
-			/* Disable the receive filter. Is 0/0 indeed an invalid receive
-			   channel? -- REW.  Yes it is. -- Hang. Ok. I'll use -1
-			   (0xfff...) -- REW */
-			submit_command (dev, &dev->hp_txq, 
-					QE_CMD_REG_WR | QE_CMD_IMM_INQ,
-					0x80 + vcc->channo, -1, 0 ); 
-		}
-	}
-
-	fs_dprintk (FS_DEBUG_ALLOC, "Free vcc: %p\n", vcc);
-	kfree (vcc);
-
-	func_exit ();
-}
-
-
-static int fs_send (struct atm_vcc *atm_vcc, struct sk_buff *skb)
-{
-	struct fs_dev *dev = FS_DEV (atm_vcc->dev);
-	struct fs_vcc *vcc = FS_VCC (atm_vcc);
-	struct FS_BPENTRY *td;
-
-	func_enter ();
-
-	fs_dprintk (FS_DEBUG_TXMEM, "I");
-	fs_dprintk (FS_DEBUG_SEND, "Send: atm_vcc %p skb %p vcc %p dev %p\n", 
-		    atm_vcc, skb, vcc, dev);
-
-	fs_dprintk (FS_DEBUG_ALLOC, "Alloc t-skb: %p (atm_send)\n", skb);
-
-	ATM_SKB(skb)->vcc = atm_vcc;
-
-	vcc->last_skb = skb;
-
-	td = kmalloc (sizeof (struct FS_BPENTRY), GFP_ATOMIC);
-	fs_dprintk (FS_DEBUG_ALLOC, "Alloc transd: %p(%zd)\n", td, sizeof (struct FS_BPENTRY));
-	if (!td) {
-		/* Oops out of mem */
-		return -ENOMEM;
-	}
-
-	fs_dprintk (FS_DEBUG_SEND, "first word in buffer: %x\n", 
-		    *(int *) skb->data);
-
-	td->flags =  TD_EPI | TD_DATA | skb->len;
-	td->next = 0;
-	td->bsa  = virt_to_bus (skb->data);
-	td->skb = skb;
-	td->dev = dev;
-	dev->ntxpckts++;
-
-#ifdef DEBUG_EXTRA
-	da[qd] = td;
-	dq[qd].flags = td->flags;
-	dq[qd].next  = td->next;
-	dq[qd].bsa   = td->bsa;
-	dq[qd].skb   = td->skb;
-	dq[qd].dev   = td->dev;
-	qd++;
-	if (qd >= 60) qd = 0;
-#endif
-
-	submit_queue (dev, &dev->hp_txq, 
-		      QE_TRANSMIT_DE | vcc->channo,
-		      virt_to_bus (td), 0, 
-		      virt_to_bus (td));
-
-	fs_dprintk (FS_DEBUG_QUEUE, "in send: txq %d txrq %d\n", 
-		    read_fs (dev, Q_EA (dev->hp_txq.offset)) -
-		    read_fs (dev, Q_SA (dev->hp_txq.offset)),
-		    read_fs (dev, Q_EA (dev->tx_relq.offset)) -
-		    read_fs (dev, Q_SA (dev->tx_relq.offset)));
-
-	func_exit ();
-	return 0;
-}
-
-
-/* Some function placeholders for functions we don't yet support. */
-
-#if 0
-static int fs_ioctl(struct atm_dev *dev,unsigned int cmd,void __user *arg)
-{
-	func_enter ();
-	func_exit ();
-	return -ENOIOCTLCMD;
-}
-
-
-static int fs_getsockopt(struct atm_vcc *vcc,int level,int optname,
-			 void __user *optval,int optlen)
-{
-	func_enter ();
-	func_exit ();
-	return 0;
-}
-
-
-static int fs_setsockopt(struct atm_vcc *vcc,int level,int optname,
-			 void __user *optval,unsigned int optlen)
-{
-	func_enter ();
-	func_exit ();
-	return 0;
-}
-
-
-static void fs_phy_put(struct atm_dev *dev,unsigned char value,
-		       unsigned long addr)
-{
-	func_enter ();
-	func_exit ();
-}
-
-
-static unsigned char fs_phy_get(struct atm_dev *dev,unsigned long addr)
-{
-	func_enter ();
-	func_exit ();
-	return 0;
-}
-
-
-static int fs_change_qos(struct atm_vcc *vcc,struct atm_qos *qos,int flags)
-{
-	func_enter ();
-	func_exit ();
-	return 0;
-};
-
-#endif
-
-
-static const struct atmdev_ops ops = {
-	.open =         fs_open,
-	.close =        fs_close,
-	.send =         fs_send,
-	.owner =        THIS_MODULE,
-	/* ioctl:          fs_ioctl, */
-	/* getsockopt:     fs_getsockopt, */
-	/* setsockopt:     fs_setsockopt, */
-	/* change_qos:     fs_change_qos, */
-
-	/* For now implement these internally here... */  
-	/* phy_put:        fs_phy_put, */
-	/* phy_get:        fs_phy_get, */
-};
-
-
-static void undocumented_pci_fix(struct pci_dev *pdev)
-{
-	u32 tint;
-
-	/* The Windows driver says: */
-	/* Switch off FireStream Retry Limit Threshold 
-	 */
-
-	/* The register at 0x28 is documented as "reserved", no further
-	   comments. */
-
-	pci_read_config_dword (pdev, 0x28, &tint);
-	if (tint != 0x80) {
-		tint = 0x80;
-		pci_write_config_dword (pdev, 0x28, tint);
-	}
-}
-
-
-
-/**************************************************************************
- *                              PHY routines                              *
- **************************************************************************/
-
-static void write_phy(struct fs_dev *dev, int regnum, int val)
-{
-	submit_command (dev,  &dev->hp_txq, QE_CMD_PRP_WR | QE_CMD_IMM_INQ,
-			regnum, val, 0);
-}
-
-static int init_phy(struct fs_dev *dev, struct reginit_item *reginit)
-{
-	int i;
-
-	func_enter ();
-	while (reginit->reg != PHY_EOF) {
-		if (reginit->reg == PHY_CLEARALL) {
-			/* "PHY_CLEARALL means clear all registers. Numregisters is in "val". */
-			for (i=0;i<reginit->val;i++) {
-				write_phy (dev, i, 0);
-			}
-		} else {
-			write_phy (dev, reginit->reg, reginit->val);
-		}
-		reginit++;
-	}
-	func_exit ();
-	return 0;
-}
-
-static void reset_chip (struct fs_dev *dev)
-{
-	int i;
-
-	write_fs (dev, SARMODE0, SARMODE0_SRTS0);
-
-	/* Undocumented delay */
-	udelay (128);
-
-	/* The "internal registers are documented to all reset to zero, but 
-	   comments & code in the Windows driver indicates that the pools are
-	   NOT reset. */
-	for (i=0;i < FS_NR_FREE_POOLS;i++) {
-		write_fs (dev, FP_CNF (RXB_FP(i)), 0);
-		write_fs (dev, FP_SA  (RXB_FP(i)), 0);
-		write_fs (dev, FP_EA  (RXB_FP(i)), 0);
-		write_fs (dev, FP_CNT (RXB_FP(i)), 0);
-		write_fs (dev, FP_CTU (RXB_FP(i)), 0);
-	}
-
-	/* The same goes for the match channel registers, although those are
-	   NOT documented that way in the Windows driver. -- REW */
-	/* The Windows driver DOES write 0 to these registers somewhere in
-	   the init sequence. However, a small hardware-feature, will
-	   prevent reception of data on VPI/VCI = 0/0 (Unless the channel
-	   allocated happens to have no disabled channels that have a lower
-	   number. -- REW */
-
-	/* Clear the match channel registers. */
-	if (IS_FS50 (dev)) {
-		for (i=0;i<FS50_NR_CHANNELS;i++) {
-			write_fs (dev, 0x200 + i * 4, -1);
-		}
-	}
-}
-
-static void *aligned_kmalloc(int size, gfp_t flags, int alignment)
-{
-	void  *t;
-
-	if (alignment <= 0x10) {
-		t = kmalloc (size, flags);
-		if ((unsigned long)t & (alignment-1)) {
-			printk ("Kmalloc doesn't align things correctly! %p\n", t);
-			kfree (t);
-			return aligned_kmalloc (size, flags, alignment * 4);
-		}
-		return t;
-	}
-	printk (KERN_ERR "Request for > 0x10 alignment not yet implemented (hard!)\n");
-	return NULL;
-}
-
-static int init_q(struct fs_dev *dev, struct queue *txq, int queue,
-		  int nentries, int is_rq)
-{
-	int sz = nentries * sizeof (struct FS_QENTRY);
-	struct FS_QENTRY *p;
-
-	func_enter ();
-
-	fs_dprintk (FS_DEBUG_INIT, "Initializing queue at %x: %d entries:\n",
-		    queue, nentries);
-
-	p = aligned_kmalloc (sz, GFP_KERNEL, 0x10);
-	fs_dprintk (FS_DEBUG_ALLOC, "Alloc queue: %p(%d)\n", p, sz);
-
-	if (!p) return 0;
-
-	write_fs (dev, Q_SA(queue), virt_to_bus(p));
-	write_fs (dev, Q_EA(queue), virt_to_bus(p+nentries-1));
-	write_fs (dev, Q_WP(queue), virt_to_bus(p));
-	write_fs (dev, Q_RP(queue), virt_to_bus(p));
-	if (is_rq) {
-		/* Configuration for the receive queue: 0: interrupt immediately,
-		   no pre-warning to empty queues: We do our best to keep the
-		   queue filled anyway. */
-		write_fs (dev, Q_CNF(queue), 0 ); 
-	}
-
-	txq->sa = p;
-	txq->ea = p;
-	txq->offset = queue; 
-
-	func_exit ();
-	return 1;
-}
-
-
-static int init_fp(struct fs_dev *dev, struct freepool *fp, int queue,
-		   int bufsize, int nr_buffers)
-{
-	func_enter ();
-
-	fs_dprintk (FS_DEBUG_INIT, "Initializing free pool at %x:\n", queue);
-
-	write_fs (dev, FP_CNF(queue), (bufsize * RBFP_RBS) | RBFP_RBSVAL | RBFP_CME);
-	write_fs (dev, FP_SA(queue),  0);
-	write_fs (dev, FP_EA(queue),  0);
-	write_fs (dev, FP_CTU(queue), 0);
-	write_fs (dev, FP_CNT(queue), 0);
-
-	fp->offset = queue; 
-	fp->bufsize = bufsize;
-	fp->nr_buffers = nr_buffers;
-
-	func_exit ();
-	return 1;
-}
-
-
-static inline int nr_buffers_in_freepool (struct fs_dev *dev, struct freepool *fp)
-{
-#if 0
-	/* This seems to be unreliable.... */
-	return read_fs (dev, FP_CNT (fp->offset));
-#else
-	return fp->n;
-#endif
-}
-
-
-/* Check if this gets going again if a pool ever runs out.  -- Yes, it
-   does. I've seen "receive abort: no buffers" and things started
-   working again after that...  -- REW */
-
-static void top_off_fp (struct fs_dev *dev, struct freepool *fp,
-			gfp_t gfp_flags)
-{
-	struct FS_BPENTRY *qe, *ne;
-	struct sk_buff *skb;
-	int n = 0;
-	u32 qe_tmp;
-
-	fs_dprintk (FS_DEBUG_QUEUE, "Topping off queue at %x (%d-%d/%d)\n", 
-		    fp->offset, read_fs (dev, FP_CNT (fp->offset)), fp->n, 
-		    fp->nr_buffers);
-	while (nr_buffers_in_freepool(dev, fp) < fp->nr_buffers) {
-
-		skb = alloc_skb (fp->bufsize, gfp_flags);
-		fs_dprintk (FS_DEBUG_ALLOC, "Alloc rec-skb: %p(%d)\n", skb, fp->bufsize);
-		if (!skb) break;
-		ne = kmalloc (sizeof (struct FS_BPENTRY), gfp_flags);
-		fs_dprintk (FS_DEBUG_ALLOC, "Alloc rec-d: %p(%zd)\n", ne, sizeof (struct FS_BPENTRY));
-		if (!ne) {
-			fs_dprintk (FS_DEBUG_ALLOC, "Free rec-skb: %p\n", skb);
-			dev_kfree_skb_any (skb);
-			break;
-		}
-
-		fs_dprintk (FS_DEBUG_QUEUE, "Adding skb %p desc %p -> %p(%p) ", 
-			    skb, ne, skb->data, skb->head);
-		n++;
-		ne->flags = FP_FLAGS_EPI | fp->bufsize;
-		ne->next  = virt_to_bus (NULL);
-		ne->bsa   = virt_to_bus (skb->data);
-		ne->aal_bufsize = fp->bufsize;
-		ne->skb = skb;
-		ne->fp = fp;
-
-		/*
-		 * FIXME: following code encodes and decodes
-		 * machine pointers (could be 64-bit) into a
-		 * 32-bit register.
-		 */
-
-		qe_tmp = read_fs (dev, FP_EA(fp->offset));
-		fs_dprintk (FS_DEBUG_QUEUE, "link at %x\n", qe_tmp);
-		if (qe_tmp) {
-			qe = bus_to_virt ((long) qe_tmp);
-			qe->next = virt_to_bus(ne);
-			qe->flags &= ~FP_FLAGS_EPI;
-		} else
-			write_fs (dev, FP_SA(fp->offset), virt_to_bus(ne));
-
-		write_fs (dev, FP_EA(fp->offset), virt_to_bus (ne));
-		fp->n++;   /* XXX Atomic_inc? */
-		write_fs (dev, FP_CTU(fp->offset), 1);
-	}
-
-	fs_dprintk (FS_DEBUG_QUEUE, "Added %d entries. \n", n);
-}
-
-static void free_queue(struct fs_dev *dev, struct queue *txq)
-{
-	func_enter ();
-
-	write_fs (dev, Q_SA(txq->offset), 0);
-	write_fs (dev, Q_EA(txq->offset), 0);
-	write_fs (dev, Q_RP(txq->offset), 0);
-	write_fs (dev, Q_WP(txq->offset), 0);
-	/* Configuration ? */
-
-	fs_dprintk (FS_DEBUG_ALLOC, "Free queue: %p\n", txq->sa);
-	kfree (txq->sa);
-
-	func_exit ();
-}
-
-static void free_freepool(struct fs_dev *dev, struct freepool *fp)
-{
-	func_enter ();
-
-	write_fs (dev, FP_CNF(fp->offset), 0);
-	write_fs (dev, FP_SA (fp->offset), 0);
-	write_fs (dev, FP_EA (fp->offset), 0);
-	write_fs (dev, FP_CNT(fp->offset), 0);
-	write_fs (dev, FP_CTU(fp->offset), 0);
-
-	func_exit ();
-}
-
-
-
-static irqreturn_t fs_irq (int irq, void *dev_id) 
-{
-	int i;
-	u32 status;
-	struct fs_dev *dev = dev_id;
-
-	status = read_fs (dev, ISR);
-	if (!status)
-		return IRQ_NONE;
-
-	func_enter ();
-
-#ifdef IRQ_RATE_LIMIT
-	/* Aaargh! I'm ashamed. This costs more lines-of-code than the actual 
-	   interrupt routine!. (Well, used to when I wrote that comment) -- REW */
-	{
-		static int lastjif;
-		static int nintr=0;
-    
-		if (lastjif == jiffies) {
-			if (++nintr > IRQ_RATE_LIMIT) {
-				free_irq (dev->irq, dev_id);
-				printk (KERN_ERR "fs: Too many interrupts. Turning off interrupt %d.\n", 
-					dev->irq);
-			}
-		} else {
-			lastjif = jiffies;
-			nintr = 0;
-		}
-	}
-#endif
-	fs_dprintk (FS_DEBUG_QUEUE, "in intr: txq %d txrq %d\n", 
-		    read_fs (dev, Q_EA (dev->hp_txq.offset)) -
-		    read_fs (dev, Q_SA (dev->hp_txq.offset)),
-		    read_fs (dev, Q_EA (dev->tx_relq.offset)) -
-		    read_fs (dev, Q_SA (dev->tx_relq.offset)));
-
-	/* print the bits in the ISR register. */
-	if (fs_debug & FS_DEBUG_IRQ) {
-		/* The FS_DEBUG things are unnecessary here. But this way it is
-		   clear for grep that these are debug prints. */
-		fs_dprintk (FS_DEBUG_IRQ,  "IRQ status:");
-		for (i=0;i<27;i++) 
-			if (status & (1 << i)) 
-				fs_dprintk (FS_DEBUG_IRQ, " %s", irq_bitname[i]);
-		fs_dprintk (FS_DEBUG_IRQ, "\n");
-	}
-  
-	if (status & ISR_RBRQ0_W) {
-		fs_dprintk (FS_DEBUG_IRQ, "Iiiin-coming (0)!!!!\n");
-		process_incoming (dev, &dev->rx_rq[0]);
-		/* items mentioned on RBRQ0 are from FP 0 or 1. */
-		top_off_fp (dev, &dev->rx_fp[0], GFP_ATOMIC);
-		top_off_fp (dev, &dev->rx_fp[1], GFP_ATOMIC);
-	}
-
-	if (status & ISR_RBRQ1_W) {
-		fs_dprintk (FS_DEBUG_IRQ, "Iiiin-coming (1)!!!!\n");
-		process_incoming (dev, &dev->rx_rq[1]);
-		top_off_fp (dev, &dev->rx_fp[2], GFP_ATOMIC);
-		top_off_fp (dev, &dev->rx_fp[3], GFP_ATOMIC);
-	}
-
-	if (status & ISR_RBRQ2_W) {
-		fs_dprintk (FS_DEBUG_IRQ, "Iiiin-coming (2)!!!!\n");
-		process_incoming (dev, &dev->rx_rq[2]);
-		top_off_fp (dev, &dev->rx_fp[4], GFP_ATOMIC);
-		top_off_fp (dev, &dev->rx_fp[5], GFP_ATOMIC);
-	}
-
-	if (status & ISR_RBRQ3_W) {
-		fs_dprintk (FS_DEBUG_IRQ, "Iiiin-coming (3)!!!!\n");
-		process_incoming (dev, &dev->rx_rq[3]);
-		top_off_fp (dev, &dev->rx_fp[6], GFP_ATOMIC);
-		top_off_fp (dev, &dev->rx_fp[7], GFP_ATOMIC);
-	}
-
-	if (status & ISR_CSQ_W) {
-		fs_dprintk (FS_DEBUG_IRQ, "Command executed ok!\n");
-		process_return_queue (dev, &dev->st_q);
-	}
-
-	if (status & ISR_TBRQ_W) {
-		fs_dprintk (FS_DEBUG_IRQ, "Data transmitted!\n");
-		process_txdone_queue (dev, &dev->tx_relq);
-	}
-
-	func_exit ();
-	return IRQ_HANDLED;
-}
-
-
-#ifdef FS_POLL_FREQ
-static void fs_poll (struct timer_list *t)
-{
-	struct fs_dev *dev = from_timer(dev, t, timer);
-  
-	fs_irq (0, dev);
-	dev->timer.expires = jiffies + FS_POLL_FREQ;
-	add_timer (&dev->timer);
-}
-#endif
-
-static int fs_init(struct fs_dev *dev)
-{
-	struct pci_dev  *pci_dev;
-	int isr, to;
-	int i;
-
-	func_enter ();
-	pci_dev = dev->pci_dev;
-
-	printk (KERN_INFO "found a FireStream %d card, base %16llx, irq%d.\n",
-		IS_FS50(dev)?50:155,
-		(unsigned long long)pci_resource_start(pci_dev, 0),
-		dev->pci_dev->irq);
-
-	if (fs_debug & FS_DEBUG_INIT)
-		my_hd ((unsigned char *) dev, sizeof (*dev));
-
-	undocumented_pci_fix (pci_dev);
-
-	dev->hw_base = pci_resource_start(pci_dev, 0);
-
-	dev->base = ioremap(dev->hw_base, 0x1000);
-
-	reset_chip (dev);
-  
-	write_fs (dev, SARMODE0, 0 
-		  | (0 * SARMODE0_SHADEN) /* We don't use shadow registers. */
-		  | (1 * SARMODE0_INTMODE_READCLEAR)
-		  | (1 * SARMODE0_CWRE)
-		  | (IS_FS50(dev) ? SARMODE0_PRPWT_FS50_5:
-			  SARMODE0_PRPWT_FS155_3)
-		  | (1 * SARMODE0_CALSUP_1)
-		  | (IS_FS50(dev) ? (0
-				   | SARMODE0_RXVCS_32
-				   | SARMODE0_ABRVCS_32 
-				   | SARMODE0_TXVCS_32):
-		                  (0
-				   | SARMODE0_RXVCS_1k
-				   | SARMODE0_ABRVCS_1k 
-				   | SARMODE0_TXVCS_1k)));
-
-	/* 10ms * 100 is 1 second. That should be enough, as AN3:9 says it takes
-	   1ms. */
-	to = 100;
-	while (--to) {
-		isr = read_fs (dev, ISR);
-
-		/* This bit is documented as "RESERVED" */
-		if (isr & ISR_INIT_ERR) {
-			printk (KERN_ERR "Error initializing the FS... \n");
-			goto unmap;
-		}
-		if (isr & ISR_INIT) {
-			fs_dprintk (FS_DEBUG_INIT, "Ha! Initialized OK!\n");
-			break;
-		}
-
-		/* Try again after 10ms. */
-		msleep(10);
-	}
-
-	if (!to) {
-		printk (KERN_ERR "timeout initializing the FS... \n");
-		goto unmap;
-	}
-
-	/* XXX fix for fs155 */
-	dev->channel_mask = 0x1f; 
-	dev->channo = 0;
-
-	/* AN3: 10 */
-	write_fs (dev, SARMODE1, 0 
-		  | (fs_keystream * SARMODE1_DEFHEC) /* XXX PHY */
-		  | ((loopback == 1) * SARMODE1_TSTLP) /* XXX Loopback mode enable... */
-		  | (1 * SARMODE1_DCRM)
-		  | (1 * SARMODE1_DCOAM)
-		  | (0 * SARMODE1_OAMCRC)
-		  | (0 * SARMODE1_DUMPE)
-		  | (0 * SARMODE1_GPLEN) 
-		  | (0 * SARMODE1_GNAM)
-		  | (0 * SARMODE1_GVAS)
-		  | (0 * SARMODE1_GPAS)
-		  | (1 * SARMODE1_GPRI)
-		  | (0 * SARMODE1_PMS)
-		  | (0 * SARMODE1_GFCR)
-		  | (1 * SARMODE1_HECM2)
-		  | (1 * SARMODE1_HECM1)
-		  | (1 * SARMODE1_HECM0)
-		  | (1 << 12) /* That's what hang's driver does. Program to 0 */
-		  | (0 * 0xff) /* XXX FS155 */);
-
-
-	/* Cal prescale etc */
-
-	/* AN3: 11 */
-	write_fs (dev, TMCONF, 0x0000000f);
-	write_fs (dev, CALPRESCALE, 0x01010101 * num);
-	write_fs (dev, 0x80, 0x000F00E4);
-
-	/* AN3: 12 */
-	write_fs (dev, CELLOSCONF, 0
-		  | (   0 * CELLOSCONF_CEN)
-		  | (       CELLOSCONF_SC1)
-		  | (0x80 * CELLOSCONF_COBS)
-		  | (num  * CELLOSCONF_COPK)  /* Changed from 0xff to 0x5a */
-		  | (num  * CELLOSCONF_COST));/* after a hint from Hang. 
-					       * performance jumped 50->70... */
-
-	/* Magic value by Hang */
-	write_fs (dev, CELLOSCONF_COST, 0x0B809191);
-
-	if (IS_FS50 (dev)) {
-		write_fs (dev, RAS0, RAS0_DCD_XHLT);
-		dev->atm_dev->ci_range.vpi_bits = 12;
-		dev->atm_dev->ci_range.vci_bits = 16;
-		dev->nchannels = FS50_NR_CHANNELS;
-	} else {
-		write_fs (dev, RAS0, RAS0_DCD_XHLT 
-			  | (((1 << FS155_VPI_BITS) - 1) * RAS0_VPSEL)
-			  | (((1 << FS155_VCI_BITS) - 1) * RAS0_VCSEL));
-		/* We can chose the split arbitrarily. We might be able to 
-		   support more. Whatever. This should do for now. */
-		dev->atm_dev->ci_range.vpi_bits = FS155_VPI_BITS;
-		dev->atm_dev->ci_range.vci_bits = FS155_VCI_BITS;
-    
-		/* Address bits we can't use should be compared to 0. */
-		write_fs (dev, RAC, 0);
-
-		/* Manual (AN9, page 6) says ASF1=0 means compare Utopia address
-		 * too.  I can't find ASF1 anywhere. Anyway, we AND with just the
-		 * other bits, then compare with 0, which is exactly what we
-		 * want. */
-		write_fs (dev, RAM, (1 << (28 - FS155_VPI_BITS - FS155_VCI_BITS)) - 1);
-		dev->nchannels = FS155_NR_CHANNELS;
-	}
-	dev->atm_vccs = kcalloc (dev->nchannels, sizeof (struct atm_vcc *),
-				 GFP_KERNEL);
-	fs_dprintk (FS_DEBUG_ALLOC, "Alloc atmvccs: %p(%zd)\n",
-		    dev->atm_vccs, dev->nchannels * sizeof (struct atm_vcc *));
-
-	if (!dev->atm_vccs) {
-		printk (KERN_WARNING "Couldn't allocate memory for VCC buffers. Woops!\n");
-		/* XXX Clean up..... */
-		goto unmap;
-	}
-
-	dev->tx_inuse = kzalloc (dev->nchannels / 8 /* bits/byte */ , GFP_KERNEL);
-	fs_dprintk (FS_DEBUG_ALLOC, "Alloc tx_inuse: %p(%d)\n", 
-		    dev->atm_vccs, dev->nchannels / 8);
-
-	if (!dev->tx_inuse) {
-		printk (KERN_WARNING "Couldn't allocate memory for tx_inuse bits!\n");
-		/* XXX Clean up..... */
-		goto unmap;
-	}
-	/* -- RAS1 : FS155 and 50 differ. Default (0) should be OK for both */
-	/* -- RAS2 : FS50 only: Default is OK. */
-
-	/* DMAMODE, default should be OK. -- REW */
-	write_fs (dev, DMAMR, DMAMR_TX_MODE_FULL);
-
-	init_q (dev, &dev->hp_txq, TX_PQ(TXQ_HP), TXQ_NENTRIES, 0);
-	init_q (dev, &dev->lp_txq, TX_PQ(TXQ_LP), TXQ_NENTRIES, 0);
-	init_q (dev, &dev->tx_relq, TXB_RQ, TXQ_NENTRIES, 1);
-	init_q (dev, &dev->st_q, ST_Q, TXQ_NENTRIES, 1);
-
-	for (i=0;i < FS_NR_FREE_POOLS;i++) {
-		init_fp (dev, &dev->rx_fp[i], RXB_FP(i), 
-			 rx_buf_sizes[i], rx_pool_sizes[i]);
-		top_off_fp (dev, &dev->rx_fp[i], GFP_KERNEL);
-	}
-
-
-	for (i=0;i < FS_NR_RX_QUEUES;i++)
-		init_q (dev, &dev->rx_rq[i], RXB_RQ(i), RXRQ_NENTRIES, 1);
-
-	dev->irq = pci_dev->irq;
-	if (request_irq (dev->irq, fs_irq, IRQF_SHARED, "firestream", dev)) {
-		printk (KERN_WARNING "couldn't get irq %d for firestream.\n", pci_dev->irq);
-		/* XXX undo all previous stuff... */
-		goto unmap;
-	}
-	fs_dprintk (FS_DEBUG_INIT, "Grabbed irq %d for dev at %p.\n", dev->irq, dev);
-  
-	/* We want to be notified of most things. Just the statistics count
-	   overflows are not interesting */
-	write_fs (dev, IMR, 0
-		  | ISR_RBRQ0_W 
-		  | ISR_RBRQ1_W 
-		  | ISR_RBRQ2_W 
-		  | ISR_RBRQ3_W 
-		  | ISR_TBRQ_W
-		  | ISR_CSQ_W);
-
-	write_fs (dev, SARMODE0, 0 
-		  | (0 * SARMODE0_SHADEN) /* We don't use shadow registers. */
-		  | (1 * SARMODE0_GINT)
-		  | (1 * SARMODE0_INTMODE_READCLEAR)
-		  | (0 * SARMODE0_CWRE)
-		  | (IS_FS50(dev)?SARMODE0_PRPWT_FS50_5: 
-		                  SARMODE0_PRPWT_FS155_3)
-		  | (1 * SARMODE0_CALSUP_1)
-		  | (IS_FS50 (dev)?(0
-				    | SARMODE0_RXVCS_32
-				    | SARMODE0_ABRVCS_32 
-				    | SARMODE0_TXVCS_32):
-		                   (0
-				    | SARMODE0_RXVCS_1k
-				    | SARMODE0_ABRVCS_1k 
-				    | SARMODE0_TXVCS_1k))
-		  | (1 * SARMODE0_RUN));
-
-	init_phy (dev, PHY_NTC_INIT);
-
-	if (loopback == 2) {
-		write_phy (dev, 0x39, 0x000e);
-	}
-
-#ifdef FS_POLL_FREQ
-	timer_setup(&dev->timer, fs_poll, 0);
-	dev->timer.expires = jiffies + FS_POLL_FREQ;
-	add_timer (&dev->timer);
-#endif
-
-	dev->atm_dev->dev_data = dev;
-  
-	func_exit ();
-	return 0;
-unmap:
-	iounmap(dev->base);
-	return 1;
-}
-
-static int firestream_init_one(struct pci_dev *pci_dev,
-			       const struct pci_device_id *ent)
-{
-	struct atm_dev *atm_dev;
-	struct fs_dev *fs_dev;
-	
-	if (pci_enable_device(pci_dev)) 
-		goto err_out;
-
-	fs_dev = kzalloc (sizeof (struct fs_dev), GFP_KERNEL);
-	fs_dprintk (FS_DEBUG_ALLOC, "Alloc fs-dev: %p(%zd)\n",
-		    fs_dev, sizeof (struct fs_dev));
-	if (!fs_dev)
-		goto err_out;
-	atm_dev = atm_dev_register("fs", &pci_dev->dev, &ops, -1, NULL);
-	if (!atm_dev)
-		goto err_out_free_fs_dev;
-  
-	fs_dev->pci_dev = pci_dev;
-	fs_dev->atm_dev = atm_dev;
-	fs_dev->flags = ent->driver_data;
-
-	if (fs_init(fs_dev))
-		goto err_out_free_atm_dev;
-
-	fs_dev->next = fs_boards;
-	fs_boards = fs_dev;
-	return 0;
-
- err_out_free_atm_dev:
-	atm_dev_deregister(atm_dev);
- err_out_free_fs_dev:
- 	kfree(fs_dev);
- err_out:
-	return -ENODEV;
-}
-
-static void firestream_remove_one(struct pci_dev *pdev)
-{
-	int i;
-	struct fs_dev *dev, *nxtdev;
-	struct fs_vcc *vcc;
-	struct FS_BPENTRY *fp, *nxt;
-  
-	func_enter ();
-
-#if 0
-	printk ("hptxq:\n");
-	for (i=0;i<60;i++) {
-		printk ("%d: %08x %08x %08x %08x \n", 
-			i, pq[qp].cmd, pq[qp].p0, pq[qp].p1, pq[qp].p2);
-		qp++;
-		if (qp >= 60) qp = 0;
-	}
-
-	printk ("descriptors:\n");
-	for (i=0;i<60;i++) {
-		printk ("%d: %p: %08x %08x %p %p\n", 
-			i, da[qd], dq[qd].flags, dq[qd].bsa, dq[qd].skb, dq[qd].dev);
-		qd++;
-		if (qd >= 60) qd = 0;
-	}
-#endif
-
-	for (dev = fs_boards;dev != NULL;dev=nxtdev) {
-		fs_dprintk (FS_DEBUG_CLEANUP, "Releasing resources for dev at %p.\n", dev);
-
-		/* XXX Hit all the tx channels too! */
-
-		for (i=0;i < dev->nchannels;i++) {
-			if (dev->atm_vccs[i]) {
-				vcc = FS_VCC (dev->atm_vccs[i]);
-				submit_command (dev,  &dev->hp_txq,
-						QE_CMD_TX_PURGE_INH | QE_CMD_IMM_INQ | vcc->channo, 0,0,0);
-				submit_command (dev,  &dev->hp_txq,
-						QE_CMD_RX_PURGE_INH | QE_CMD_IMM_INQ | vcc->channo, 0,0,0);
-
-			}
-		}
-
-		/* XXX Wait a while for the chip to release all buffers. */
-
-		for (i=0;i < FS_NR_FREE_POOLS;i++) {
-			for (fp=bus_to_virt (read_fs (dev, FP_SA(dev->rx_fp[i].offset)));
-			     !(fp->flags & FP_FLAGS_EPI);fp = nxt) {
-				fs_dprintk (FS_DEBUG_ALLOC, "Free rec-skb: %p\n", fp->skb);
-				dev_kfree_skb_any (fp->skb);
-				nxt = bus_to_virt (fp->next);
-				fs_dprintk (FS_DEBUG_ALLOC, "Free rec-d: %p\n", fp);
-				kfree (fp);
-			}
-			fs_dprintk (FS_DEBUG_ALLOC, "Free rec-skb: %p\n", fp->skb);
-			dev_kfree_skb_any (fp->skb);
-			fs_dprintk (FS_DEBUG_ALLOC, "Free rec-d: %p\n", fp);
-			kfree (fp);
-		}
-
-		/* Hang the chip in "reset", prevent it clobbering memory that is
-		   no longer ours. */
-		reset_chip (dev);
-
-		fs_dprintk (FS_DEBUG_CLEANUP, "Freeing irq%d.\n", dev->irq);
-		free_irq (dev->irq, dev);
-		del_timer_sync (&dev->timer);
-
-		atm_dev_deregister(dev->atm_dev);
-		free_queue (dev, &dev->hp_txq);
-		free_queue (dev, &dev->lp_txq);
-		free_queue (dev, &dev->tx_relq);
-		free_queue (dev, &dev->st_q);
-
-		fs_dprintk (FS_DEBUG_ALLOC, "Free atmvccs: %p\n", dev->atm_vccs);
-		kfree (dev->atm_vccs);
-
-		for (i=0;i< FS_NR_FREE_POOLS;i++)
-			free_freepool (dev, &dev->rx_fp[i]);
-    
-		for (i=0;i < FS_NR_RX_QUEUES;i++)
-			free_queue (dev, &dev->rx_rq[i]);
-
-		iounmap(dev->base);
-		fs_dprintk (FS_DEBUG_ALLOC, "Free fs-dev: %p\n", dev);
-		nxtdev = dev->next;
-		kfree (dev);
-	}
-
-	func_exit ();
-}
-
-static const struct pci_device_id firestream_pci_tbl[] = {
-	{ PCI_VDEVICE(FUJITSU_ME, PCI_DEVICE_ID_FUJITSU_FS50), FS_IS50},
-	{ PCI_VDEVICE(FUJITSU_ME, PCI_DEVICE_ID_FUJITSU_FS155), FS_IS155},
-	{ 0, }
-};
-
-MODULE_DEVICE_TABLE(pci, firestream_pci_tbl);
-
-static struct pci_driver firestream_driver = {
-	.name		= "firestream",
-	.id_table	= firestream_pci_tbl,
-	.probe		= firestream_init_one,
-	.remove		= firestream_remove_one,
-};
-
-static int __init firestream_init_module (void)
-{
-	int error;
-
-	func_enter ();
-	error = pci_register_driver(&firestream_driver);
-	func_exit ();
-	return error;
-}
-
-static void __exit firestream_cleanup_module(void)
-{
-	pci_unregister_driver(&firestream_driver);
-}
-
-module_init(firestream_init_module);
-module_exit(firestream_cleanup_module);
-
-MODULE_LICENSE("GPL");
-
-
-
diff --git a/drivers/atm/firestream.h b/drivers/atm/firestream.h
deleted file mode 100644
index 6d684160808d..000000000000
--- a/drivers/atm/firestream.h
+++ /dev/null
@@ -1,502 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* drivers/atm/firestream.h - FireStream 155 (MB86697) and
- *                            FireStream  50 (MB86695) device driver 
- */
- 
-/* Written & (C) 2000 by R.E.Wolff@BitWizard.nl 
- * Copied snippets from zatm.c by Werner Almesberger, EPFL LRC/ICA 
- * and ambassador.c Copyright (C) 1995-1999  Madge Networks Ltd 
- */
-
-/*
-*/
-
-
-/***********************************************************************
- *                  first the defines for the chip.                    *
- ***********************************************************************/
-
-
-/********************* General chip parameters. ************************/
-
-#define FS_NR_FREE_POOLS   8
-#define FS_NR_RX_QUEUES    4
-
-
-/********************* queues and queue access macros ******************/
-
-
-/* A queue entry. */
-struct FS_QENTRY {
-	u32 cmd;
-	u32 p0, p1, p2;
-};
-
-
-/* A freepool entry. */
-struct FS_BPENTRY {
-	u32 flags;
-	u32 next;
-	u32 bsa;
-	u32 aal_bufsize;
-
-	/* The hardware doesn't look at this, but we need the SKB somewhere... */
-	struct sk_buff *skb;
-	struct freepool *fp;
-	struct fs_dev *dev;
-};
-
-
-#define STATUS_CODE(qe)  ((qe->cmd >> 22) & 0x3f)
-
-
-/* OFFSETS against the base of a QUEUE... */
-#define QSA     0x00
-#define QEA     0x04
-#define QRP     0x08
-#define QWP     0x0c
-#define QCNF    0x10   /* Only for Release queues! */
-/* Not for the transmit pending queue. */
-
-
-/* OFFSETS against the base of a FREE POOL... */
-#define FPCNF   0x00
-#define FPSA    0x04
-#define FPEA    0x08
-#define FPCNT   0x0c
-#define FPCTU   0x10
-
-#define Q_SA(b)     (b + QSA )
-#define Q_EA(b)     (b + QEA )
-#define Q_RP(b)     (b + QRP )
-#define Q_WP(b)     (b + QWP )
-#define Q_CNF(b)    (b + QCNF)
-
-#define FP_CNF(b)   (b + FPCNF)
-#define FP_SA(b)    (b + FPSA)
-#define FP_EA(b)    (b + FPEA)
-#define FP_CNT(b)   (b + FPCNT)
-#define FP_CTU(b)   (b + FPCTU)
-
-/* bits in a queue register. */
-#define Q_FULL      0x1
-#define Q_EMPTY     0x2
-#define Q_INCWRAP   0x4
-#define Q_ADDR_MASK 0xfffffff0
-
-/* bits in a FreePool config register */
-#define RBFP_RBS    (0x1 << 16)
-#define RBFP_RBSVAL (0x1 << 15)
-#define RBFP_CME    (0x1 << 12)
-#define RBFP_DLP    (0x1 << 11)
-#define RBFP_BFPWT  (0x1 <<  0)
-
-
-
-
-/* FireStream commands. */
-#define QE_CMD_NULL             (0x00 << 22)
-#define QE_CMD_REG_RD           (0x01 << 22)
-#define QE_CMD_REG_RDM          (0x02 << 22)
-#define QE_CMD_REG_WR           (0x03 << 22)
-#define QE_CMD_REG_WRM          (0x04 << 22)
-#define QE_CMD_CONFIG_TX        (0x05 << 22)
-#define QE_CMD_CONFIG_RX        (0x06 << 22)
-#define QE_CMD_PRP_RD           (0x07 << 22)
-#define QE_CMD_PRP_RDM          (0x2a << 22)
-#define QE_CMD_PRP_WR           (0x09 << 22)
-#define QE_CMD_PRP_WRM          (0x2b << 22)
-#define QE_CMD_RX_EN            (0x0a << 22)
-#define QE_CMD_RX_PURGE         (0x0b << 22)
-#define QE_CMD_RX_PURGE_INH     (0x0c << 22)
-#define QE_CMD_TX_EN            (0x0d << 22)
-#define QE_CMD_TX_PURGE         (0x0e << 22)
-#define QE_CMD_TX_PURGE_INH     (0x0f << 22)
-#define QE_CMD_RST_CG           (0x10 << 22)
-#define QE_CMD_SET_CG           (0x11 << 22)
-#define QE_CMD_RST_CLP          (0x12 << 22)
-#define QE_CMD_SET_CLP          (0x13 << 22)
-#define QE_CMD_OVERRIDE         (0x14 << 22)
-#define QE_CMD_ADD_BFP          (0x15 << 22)
-#define QE_CMD_DUMP_TX          (0x16 << 22)
-#define QE_CMD_DUMP_RX          (0x17 << 22)
-#define QE_CMD_LRAM_RD          (0x18 << 22)
-#define QE_CMD_LRAM_RDM         (0x28 << 22)
-#define QE_CMD_LRAM_WR          (0x19 << 22)
-#define QE_CMD_LRAM_WRM         (0x29 << 22)
-#define QE_CMD_LRAM_BSET        (0x1a << 22)
-#define QE_CMD_LRAM_BCLR        (0x1b << 22)
-#define QE_CMD_CONFIG_SEGM      (0x1c << 22)
-#define QE_CMD_READ_SEGM        (0x1d << 22)
-#define QE_CMD_CONFIG_ROUT      (0x1e << 22)
-#define QE_CMD_READ_ROUT        (0x1f << 22)
-#define QE_CMD_CONFIG_TM        (0x20 << 22)
-#define QE_CMD_READ_TM          (0x21 << 22)
-#define QE_CMD_CONFIG_TXBM      (0x22 << 22)
-#define QE_CMD_READ_TXBM        (0x23 << 22)
-#define QE_CMD_CONFIG_RXBM      (0x24 << 22)
-#define QE_CMD_READ_RXBM        (0x25 << 22)
-#define QE_CMD_CONFIG_REAS      (0x26 << 22)
-#define QE_CMD_READ_REAS        (0x27 << 22)
-
-#define QE_TRANSMIT_DE          (0x0 << 30)
-#define QE_CMD_LINKED           (0x1 << 30)
-#define QE_CMD_IMM              (0x2 << 30)
-#define QE_CMD_IMM_INQ          (0x3 << 30)
-
-#define TD_EPI                  (0x1 << 27)
-#define TD_COMMAND              (0x1 << 28)
-
-#define TD_DATA                 (0x0 << 29)
-#define TD_RM_CELL              (0x1 << 29)
-#define TD_OAM_CELL             (0x2 << 29)
-#define TD_OAM_CELL_SEGMENT     (0x3 << 29)
-
-#define TD_BPI                  (0x1 << 20)
-
-#define FP_FLAGS_EPI            (0x1 << 27)
-
-
-#define TX_PQ(i)  (0x00  + (i) * 0x10)
-#define TXB_RQ    (0x20)
-#define ST_Q      (0x48)
-#define RXB_FP(i) (0x90  + (i) * 0x14)
-#define RXB_RQ(i) (0x134 + (i) * 0x14)
-
-
-#define TXQ_HP 0
-#define TXQ_LP 1
-
-/* Phew. You don't want to know how many revisions these simple queue
- * address macros went through before I got them nice and compact as
- * they are now. -- REW
- */
-
-
-/* And now for something completely different: 
- * The rest of the registers... */
-
-
-#define CMDR0 0x34
-#define CMDR1 0x38
-#define CMDR2 0x3c
-#define CMDR3 0x40
-
-
-#define SARMODE0     0x5c
-
-#define SARMODE0_TXVCS_0    (0x0 << 0)
-#define SARMODE0_TXVCS_1k   (0x1 << 0)
-#define SARMODE0_TXVCS_2k   (0x2 << 0)
-#define SARMODE0_TXVCS_4k   (0x3 << 0)
-#define SARMODE0_TXVCS_8k   (0x4 << 0)
-#define SARMODE0_TXVCS_16k  (0x5 << 0)
-#define SARMODE0_TXVCS_32k  (0x6 << 0)
-#define SARMODE0_TXVCS_64k  (0x7 << 0)
-#define SARMODE0_TXVCS_32   (0x8 << 0)
-
-#define SARMODE0_ABRVCS_0   (0x0 << 4)
-#define SARMODE0_ABRVCS_512 (0x1 << 4)
-#define SARMODE0_ABRVCS_1k  (0x2 << 4)
-#define SARMODE0_ABRVCS_2k  (0x3 << 4)
-#define SARMODE0_ABRVCS_4k  (0x4 << 4)
-#define SARMODE0_ABRVCS_8k  (0x5 << 4)
-#define SARMODE0_ABRVCS_16k (0x6 << 4)
-#define SARMODE0_ABRVCS_32k (0x7 << 4)
-#define SARMODE0_ABRVCS_32  (0x9 << 4) /* The others are "8", this one really has to 
-					  be 9. Tell me you don't believe me. -- REW */
-
-#define SARMODE0_RXVCS_0    (0x0 << 8)
-#define SARMODE0_RXVCS_1k   (0x1 << 8)
-#define SARMODE0_RXVCS_2k   (0x2 << 8)
-#define SARMODE0_RXVCS_4k   (0x3 << 8)
-#define SARMODE0_RXVCS_8k   (0x4 << 8)
-#define SARMODE0_RXVCS_16k  (0x5 << 8)
-#define SARMODE0_RXVCS_32k  (0x6 << 8)
-#define SARMODE0_RXVCS_64k  (0x7 << 8)
-#define SARMODE0_RXVCS_32   (0x8 << 8) 
-
-#define SARMODE0_CALSUP_1  (0x0 << 12)
-#define SARMODE0_CALSUP_2  (0x1 << 12)
-#define SARMODE0_CALSUP_3  (0x2 << 12)
-#define SARMODE0_CALSUP_4  (0x3 << 12)
-
-#define SARMODE0_PRPWT_FS50_0  (0x0 << 14)
-#define SARMODE0_PRPWT_FS50_2  (0x1 << 14)
-#define SARMODE0_PRPWT_FS50_5  (0x2 << 14)
-#define SARMODE0_PRPWT_FS50_11 (0x3 << 14)
-
-#define SARMODE0_PRPWT_FS155_0 (0x0 << 14)
-#define SARMODE0_PRPWT_FS155_1 (0x1 << 14)
-#define SARMODE0_PRPWT_FS155_2 (0x2 << 14)
-#define SARMODE0_PRPWT_FS155_3 (0x3 << 14)
-
-#define SARMODE0_SRTS0     (0x1 << 23)
-#define SARMODE0_SRTS1     (0x1 << 24)
-
-#define SARMODE0_RUN       (0x1 << 25)
-
-#define SARMODE0_UNLOCK    (0x1 << 26)
-#define SARMODE0_CWRE      (0x1 << 27)
-
-
-#define SARMODE0_INTMODE_READCLEAR          (0x0 << 28)
-#define SARMODE0_INTMODE_READNOCLEAR        (0x1 << 28)
-#define SARMODE0_INTMODE_READNOCLEARINHIBIT (0x2 << 28)
-#define SARMODE0_INTMODE_READCLEARINHIBIT   (0x3 << 28)  /* Tell me you don't believe me. */
-
-#define SARMODE0_GINT      (0x1 << 30)
-#define SARMODE0_SHADEN    (0x1 << 31)
-
-
-#define SARMODE1     0x60
-
-
-#define SARMODE1_TRTL_SHIFT 0   /* Program to 0 */
-#define SARMODE1_RRTL_SHIFT 4   /* Program to 0 */
-
-#define SARMODE1_TAGM       (0x1 <<  8)  /* Program to 0 */
-
-#define SARMODE1_HECM0      (0x1 <<  9)
-#define SARMODE1_HECM1      (0x1 << 10)
-#define SARMODE1_HECM2      (0x1 << 11)
-
-#define SARMODE1_GFCE       (0x1 << 14)
-#define SARMODE1_GFCR       (0x1 << 15)
-#define SARMODE1_PMS        (0x1 << 18)
-#define SARMODE1_GPRI       (0x1 << 19)
-#define SARMODE1_GPAS       (0x1 << 20)
-#define SARMODE1_GVAS       (0x1 << 21)
-#define SARMODE1_GNAM       (0x1 << 22)
-#define SARMODE1_GPLEN      (0x1 << 23)
-#define SARMODE1_DUMPE      (0x1 << 24)
-#define SARMODE1_OAMCRC     (0x1 << 25)
-#define SARMODE1_DCOAM      (0x1 << 26)
-#define SARMODE1_DCRM       (0x1 << 27)
-#define SARMODE1_TSTLP      (0x1 << 28)
-#define SARMODE1_DEFHEC     (0x1 << 29)
-
-
-#define ISR      0x64
-#define IUSR     0x68
-#define IMR      0x6c
-
-#define ISR_LPCO          (0x1 <<  0)
-#define ISR_DPCO          (0x1 <<  1)
-#define ISR_RBRQ0_W       (0x1 <<  2)
-#define ISR_RBRQ1_W       (0x1 <<  3)
-#define ISR_RBRQ2_W       (0x1 <<  4)
-#define ISR_RBRQ3_W       (0x1 <<  5)
-#define ISR_RBRQ0_NF      (0x1 <<  6)
-#define ISR_RBRQ1_NF      (0x1 <<  7)
-#define ISR_RBRQ2_NF      (0x1 <<  8)
-#define ISR_RBRQ3_NF      (0x1 <<  9)
-#define ISR_BFP_SC        (0x1 << 10)
-#define ISR_INIT          (0x1 << 11)
-#define ISR_INIT_ERR      (0x1 << 12) /* Documented as "reserved" */
-#define ISR_USCEO         (0x1 << 13)
-#define ISR_UPEC0         (0x1 << 14)
-#define ISR_VPFCO         (0x1 << 15)
-#define ISR_CRCCO         (0x1 << 16)
-#define ISR_HECO          (0x1 << 17)
-#define ISR_TBRQ_W        (0x1 << 18)
-#define ISR_TBRQ_NF       (0x1 << 19)
-#define ISR_CTPQ_E        (0x1 << 20)
-#define ISR_GFC_C0        (0x1 << 21)
-#define ISR_PCI_FTL       (0x1 << 22)
-#define ISR_CSQ_W         (0x1 << 23)
-#define ISR_CSQ_NF        (0x1 << 24)
-#define ISR_EXT_INT       (0x1 << 25)
-#define ISR_RXDMA_S       (0x1 << 26)
-
-
-#define TMCONF 0x78
-/* Bits? */
-
-
-#define CALPRESCALE 0x7c
-/* Bits? */
-
-#define CELLOSCONF 0x84
-#define CELLOSCONF_COTS   (0x1 << 28)
-#define CELLOSCONF_CEN    (0x1 << 27)
-#define CELLOSCONF_SC8    (0x3 << 24)
-#define CELLOSCONF_SC4    (0x2 << 24)
-#define CELLOSCONF_SC2    (0x1 << 24)
-#define CELLOSCONF_SC1    (0x0 << 24)
-
-#define CELLOSCONF_COBS   (0x1 << 16)
-#define CELLOSCONF_COPK   (0x1 <<  8)
-#define CELLOSCONF_COST   (0x1 <<  0)
-/* Bits? */
-
-#define RAS0 0x1bc
-#define RAS0_DCD_XHLT (0x1 << 31)
-
-#define RAS0_VPSEL    (0x1 << 16)
-#define RAS0_VCSEL    (0x1 <<  0)
-
-#define RAS1 0x1c0
-#define RAS1_UTREG    (0x1 << 5)
-
-
-#define DMAMR 0x1cc
-#define DMAMR_TX_MODE_FULL (0x0 << 0)
-#define DMAMR_TX_MODE_PART (0x1 << 0)
-#define DMAMR_TX_MODE_NONE (0x2 << 0) /* And 3 */
-
-
-
-#define RAS2 0x280
-
-#define RAS2_NNI  (0x1 << 0)
-#define RAS2_USEL (0x1 << 1)
-#define RAS2_UBS  (0x1 << 2)
-
-
-
-struct fs_transmit_config {
-	u32 flags;
-	u32 atm_hdr;
-	u32 TMC[4];
-	u32 spec;
-	u32 rtag[3];
-};
-
-#define TC_FLAGS_AAL5      (0x0 << 29)
-#define TC_FLAGS_TRANSPARENT_PAYLOAD (0x1 << 29)
-#define TC_FLAGS_TRANSPARENT_CELL    (0x2 << 29)
-#define TC_FLAGS_STREAMING (0x1 << 28)
-#define TC_FLAGS_PACKET    (0x0) 
-#define TC_FLAGS_TYPE_ABR  (0x0 << 22)
-#define TC_FLAGS_TYPE_CBR  (0x1 << 22)
-#define TC_FLAGS_TYPE_VBR  (0x2 << 22)
-#define TC_FLAGS_TYPE_UBR  (0x3 << 22)
-#define TC_FLAGS_CAL0      (0x0 << 20)
-#define TC_FLAGS_CAL1      (0x1 << 20)
-#define TC_FLAGS_CAL2      (0x2 << 20)
-#define TC_FLAGS_CAL3      (0x3 << 20)
-
-
-#define RC_FLAGS_NAM        (0x1 << 13)
-#define RC_FLAGS_RXBM_PSB   (0x0 << 14)
-#define RC_FLAGS_RXBM_CIF   (0x1 << 14)
-#define RC_FLAGS_RXBM_PMB   (0x2 << 14)
-#define RC_FLAGS_RXBM_STR   (0x4 << 14)
-#define RC_FLAGS_RXBM_SAF   (0x6 << 14)
-#define RC_FLAGS_RXBM_POS   (0x6 << 14)
-#define RC_FLAGS_BFPS       (0x1 << 17)
-
-#define RC_FLAGS_BFPS_BFP   (0x1 << 17)
-
-#define RC_FLAGS_BFPS_BFP0  (0x0 << 17)
-#define RC_FLAGS_BFPS_BFP1  (0x1 << 17)
-#define RC_FLAGS_BFPS_BFP2  (0x2 << 17)
-#define RC_FLAGS_BFPS_BFP3  (0x3 << 17)
-#define RC_FLAGS_BFPS_BFP4  (0x4 << 17)
-#define RC_FLAGS_BFPS_BFP5  (0x5 << 17)
-#define RC_FLAGS_BFPS_BFP6  (0x6 << 17)
-#define RC_FLAGS_BFPS_BFP7  (0x7 << 17)
-#define RC_FLAGS_BFPS_BFP01 (0x8 << 17)
-#define RC_FLAGS_BFPS_BFP23 (0x9 << 17)
-#define RC_FLAGS_BFPS_BFP45 (0xa << 17)
-#define RC_FLAGS_BFPS_BFP67 (0xb << 17)
-#define RC_FLAGS_BFPS_BFP07 (0xc << 17)
-#define RC_FLAGS_BFPS_BFP27 (0xd << 17)
-#define RC_FLAGS_BFPS_BFP47 (0xe << 17)
-
-#define RC_FLAGS_BFPP       (0x1 << 21)
-#define RC_FLAGS_TEVC       (0x1 << 22)
-#define RC_FLAGS_TEP        (0x1 << 23)
-#define RC_FLAGS_AAL5       (0x0 << 24)
-#define RC_FLAGS_TRANSP     (0x1 << 24)
-#define RC_FLAGS_TRANSC     (0x2 << 24)
-#define RC_FLAGS_ML         (0x1 << 27)
-#define RC_FLAGS_TRBRM      (0x1 << 28)
-#define RC_FLAGS_PRI        (0x1 << 29)
-#define RC_FLAGS_HOAM       (0x1 << 30)
-#define RC_FLAGS_CRC10      (0x1 << 31)
-
-
-#define RAC 0x1c8
-#define RAM 0x1c4
-
-
-
-/************************************************************************
- *         Then the datastructures that the DRIVER uses.                *
- ************************************************************************/
-
-#define TXQ_NENTRIES  32
-#define RXRQ_NENTRIES 1024
-
-
-struct fs_vcc {
-	int channo;
-	wait_queue_head_t close_wait;
-	struct sk_buff *last_skb;
-};
-
-
-struct queue {
-	struct FS_QENTRY *sa, *ea;  
-	int offset;
-};
-
-struct freepool {
-	int offset;
-	int bufsize;
-	int nr_buffers;
-	int n;
-};
-
-
-struct fs_dev {
-	struct fs_dev *next;		/* other FS devices */
-	int flags;
-
-	unsigned char irq;		/* IRQ */
-	struct pci_dev *pci_dev;	/* PCI stuff */
-	struct atm_dev *atm_dev;
-	struct timer_list timer;
-
-	unsigned long hw_base;		/* mem base address */
-	void __iomem *base;             /* Mapping of base address */
-	int channo;
-	unsigned long channel_mask;
-
-	struct queue    hp_txq, lp_txq, tx_relq, st_q;
-	struct freepool rx_fp[FS_NR_FREE_POOLS];
-	struct queue    rx_rq[FS_NR_RX_QUEUES];
-
-	int nchannels;
-	struct atm_vcc **atm_vccs;
-	void *tx_inuse;
-	int ntxpckts;
-};
-
-
-
-
-/* Number of channesl that the FS50 supports. */
-#define FS50_CHANNEL_BITS  5
-#define FS50_NR_CHANNELS      (1 << FS50_CHANNEL_BITS)
-
-         
-#define FS_DEV(atm_dev) ((struct fs_dev *) (atm_dev)->dev_data)
-#define FS_VCC(atm_vcc) ((struct fs_vcc *) (atm_vcc)->dev_data)
-
-
-#define FS_IS50  0x1
-#define FS_IS155 0x2
-
-#define IS_FS50(dev)  (dev->flags & FS_IS50)
-#define IS_FS155(dev) (dev->flags & FS_IS155)
- 
-/* Within limits this is user-configurable. */
-/* Note: Currently the sum (10 -> 1k channels) is hardcoded in the driver. */
-#define FS155_VPI_BITS 4
-#define FS155_VCI_BITS 6
-
-#define FS155_CHANNEL_BITS  (FS155_VPI_BITS + FS155_VCI_BITS)
-#define FS155_NR_CHANNELS   (1 << FS155_CHANNEL_BITS)
diff --git a/drivers/atm/fore200e.c b/drivers/atm/fore200e.c
index 8fbd36eb8941..f62e38571440 100644
--- a/drivers/atm/fore200e.c
+++ b/drivers/atm/fore200e.c
@@ -21,10 +21,10 @@
 #include <linux/module.h>
 #include <linux/atmdev.h>
 #include <linux/sonet.h>
-#include <linux/atm_suni.h>
 #include <linux/dma-mapping.h>
 #include <linux/delay.h>
 #include <linux/firmware.h>
+#include <linux/pgtable.h>
 #include <asm/io.h>
 #include <asm/string.h>
 #include <asm/page.h>
@@ -36,11 +36,10 @@
 
 #ifdef CONFIG_SBUS
 #include <linux/of.h>
-#include <linux/of_device.h>
+#include <linux/platform_device.h>
 #include <asm/idprom.h>
 #include <asm/openprom.h>
 #include <asm/oplib.h>
-#include <asm/pgtable.h>
 #endif
 
 #if defined(CONFIG_ATM_FORE200E_USE_TASKLET) /* defer interrupt work to a tasklet */
@@ -95,13 +94,8 @@
 
 static const struct atmdev_ops   fore200e_ops;
 
-static LIST_HEAD(fore200e_boards);
-
-
 MODULE_AUTHOR("Christophe Lizzi - credits to Uwe Dannowski and Heikki Vatiainen");
 MODULE_DESCRIPTION("FORE Systems 200E-series ATM driver - version " FORE200E_VERSION);
-MODULE_SUPPORTED_DEVICE("PCA-200E, SBA-200E");
-
 
 static const int fore200e_rx_buf_nbr[ BUFFER_SCHEME_NBR ][ BUFFER_MAGN_NBR ] = {
     { BUFFER_S1_NBR, BUFFER_L1_NBR },
@@ -376,33 +370,33 @@ fore200e_shutdown(struct fore200e* fore200e)
     case FORE200E_STATE_COMPLETE:
 	kfree(fore200e->stats);
 
-	/* fall through */
+	fallthrough;
     case FORE200E_STATE_IRQ:
 	free_irq(fore200e->irq, fore200e->atm_dev);
 
-	/* fall through */
+	fallthrough;
     case FORE200E_STATE_ALLOC_BUF:
 	fore200e_free_rx_buf(fore200e);
 
-	/* fall through */
+	fallthrough;
     case FORE200E_STATE_INIT_BSQ:
 	fore200e_uninit_bs_queue(fore200e);
 
-	/* fall through */
+	fallthrough;
     case FORE200E_STATE_INIT_RXQ:
 	fore200e_dma_chunk_free(fore200e, &fore200e->host_rxq.status);
 	fore200e_dma_chunk_free(fore200e, &fore200e->host_rxq.rpd);
 
-	/* fall through */
+	fallthrough;
     case FORE200E_STATE_INIT_TXQ:
 	fore200e_dma_chunk_free(fore200e, &fore200e->host_txq.status);
 	fore200e_dma_chunk_free(fore200e, &fore200e->host_txq.tpd);
 
-	/* fall through */
+	fallthrough;
     case FORE200E_STATE_INIT_CMDQ:
 	fore200e_dma_chunk_free(fore200e, &fore200e->host_cmdq.status);
 
-	/* fall through */
+	fallthrough;
     case FORE200E_STATE_INITIALIZE:
 	/* nothing to do for that state */
 
@@ -415,7 +409,7 @@ fore200e_shutdown(struct fore200e* fore200e)
     case FORE200E_STATE_MAP:
 	fore200e->bus->unmap(fore200e);
 
-	/* fall through */
+	fallthrough;
     case FORE200E_STATE_CONFIGURE:
 	/* nothing to do for that state */
 
@@ -423,6 +417,7 @@ fore200e_shutdown(struct fore200e* fore200e)
 	/* XXX shouldn't we *start* by deregistering the device? */
 	atm_dev_deregister(fore200e->atm_dev);
 
+	fallthrough;
     case FORE200E_STATE_BLANK:
 	/* nothing to do for that state */
 	break;
@@ -1379,7 +1374,9 @@ fore200e_open(struct atm_vcc *vcc)
 
 	vcc->dev_data = NULL;
 
+	mutex_lock(&fore200e->rate_mtx);
 	fore200e->available_cell_rate += vcc->qos.txtp.max_pcr;
+	mutex_unlock(&fore200e->rate_mtx);
 
 	kfree(fore200e_vcc);
 	return -EINVAL;
@@ -1710,31 +1707,6 @@ fore200e_getstats(struct fore200e* fore200e)
     return 0;
 }
 
-
-static int
-fore200e_getsockopt(struct atm_vcc* vcc, int level, int optname, void __user *optval, int optlen)
-{
-    /* struct fore200e* fore200e = FORE200E_DEV(vcc->dev); */
-
-    DPRINTK(2, "getsockopt %d.%d.%d, level = %d, optname = 0x%x, optval = 0x%p, optlen = %d\n",
-	    vcc->itf, vcc->vpi, vcc->vci, level, optname, optval, optlen);
-
-    return -EINVAL;
-}
-
-
-static int
-fore200e_setsockopt(struct atm_vcc* vcc, int level, int optname, void __user *optval, unsigned int optlen)
-{
-    /* struct fore200e* fore200e = FORE200E_DEV(vcc->dev); */
-    
-    DPRINTK(2, "setsockopt %d.%d.%d, level = %d, optname = 0x%x, optval = 0x%p, optlen = %d\n",
-	    vcc->itf, vcc->vpi, vcc->vci, level, optname, optval, optlen);
-    
-    return -EINVAL;
-}
-
-
 #if 0 /* currently unused */
 static int
 fore200e_get_oc3(struct fore200e* fore200e, struct oc3_regs* regs)
@@ -2547,18 +2519,12 @@ static int fore200e_init(struct fore200e *fore200e, struct device *parent)
 }
 
 #ifdef CONFIG_SBUS
-static const struct of_device_id fore200e_sba_match[];
 static int fore200e_sba_probe(struct platform_device *op)
 {
-	const struct of_device_id *match;
 	struct fore200e *fore200e;
 	static int index = 0;
 	int err;
 
-	match = of_match_device(fore200e_sba_match, &op->dev);
-	if (!match)
-		return -EINVAL;
-
 	fore200e = kzalloc(sizeof(struct fore200e), GFP_KERNEL);
 	if (!fore200e)
 		return -ENOMEM;
@@ -2583,14 +2549,12 @@ static int fore200e_sba_probe(struct platform_device *op)
 	return 0;
 }
 
-static int fore200e_sba_remove(struct platform_device *op)
+static void fore200e_sba_remove(struct platform_device *op)
 {
 	struct fore200e *fore200e = dev_get_drvdata(&op->dev);
 
 	fore200e_shutdown(fore200e);
 	kfree(fore200e);
-
-	return 0;
 }
 
 static const struct of_device_id fore200e_sba_match[] = {
@@ -3026,8 +2990,6 @@ static const struct atmdev_ops fore200e_ops = {
 	.open       = fore200e_open,
 	.close      = fore200e_close,
 	.ioctl      = fore200e_ioctl,
-	.getsockopt = fore200e_getsockopt,
-	.setsockopt = fore200e_setsockopt,
 	.send       = fore200e_send,
 	.change_qos = fore200e_change_qos,
 	.proc_read  = fore200e_proc_read,
diff --git a/drivers/atm/fore200e.h b/drivers/atm/fore200e.h
index caf0ea6a328a..5d95fe9fd836 100644
--- a/drivers/atm/fore200e.h
+++ b/drivers/atm/fore200e.h
@@ -830,7 +830,6 @@ typedef struct fore200e_vc_map {
 /* per-device data */
 
 typedef struct fore200e {
-    struct       list_head     entry;                  /* next device                        */
     const struct fore200e_bus* bus;                    /* bus-dependent code and data        */
     union        fore200e_regs regs;                   /* bus-dependent registers            */
     struct       atm_dev*      atm_dev;                /* ATM device                         */
diff --git a/drivers/atm/he.c b/drivers/atm/he.c
index 8af793f5e811..ad91cc6a34fc 100644
--- a/drivers/atm/he.c
+++ b/drivers/atm/he.c
@@ -780,14 +780,11 @@ static int he_init_group(struct he_dev *he_dev, int group)
 		  G0_RBPS_BS + (group * 32));
 
 	/* bitmap table */
-	he_dev->rbpl_table = kmalloc_array(BITS_TO_LONGS(RBPL_TABLE_SIZE),
-					   sizeof(*he_dev->rbpl_table),
-					   GFP_KERNEL);
+	he_dev->rbpl_table = bitmap_zalloc(RBPL_TABLE_SIZE, GFP_KERNEL);
 	if (!he_dev->rbpl_table) {
 		hprintk("unable to allocate rbpl bitmap table\n");
 		return -ENOMEM;
 	}
-	bitmap_zero(he_dev->rbpl_table, RBPL_TABLE_SIZE);
 
 	/* rbpl_virt 64-bit pointers */
 	he_dev->rbpl_virt = kmalloc_array(RBPL_TABLE_SIZE,
@@ -902,7 +899,7 @@ out_destroy_rbpl_pool:
 out_free_rbpl_virt:
 	kfree(he_dev->rbpl_virt);
 out_free_rbpl_table:
-	kfree(he_dev->rbpl_table);
+	bitmap_free(he_dev->rbpl_table);
 
 	return -ENOMEM;
 }
@@ -1578,7 +1575,7 @@ he_stop(struct he_dev *he_dev)
 	}
 
 	kfree(he_dev->rbpl_virt);
-	kfree(he_dev->rbpl_table);
+	bitmap_free(he_dev->rbpl_table);
 	dma_pool_destroy(he_dev->rbpl_pool);
 
 	if (he_dev->rbrq_base)
@@ -1944,14 +1941,14 @@ he_tasklet(unsigned long data)
 		switch (type) {
 			case ITYPE_RBRQ_THRESH:
 				HPRINTK("rbrq%d threshold\n", group);
-				/* fall through */
+				fallthrough;
 			case ITYPE_RBRQ_TIMER:
 				if (he_service_rbrq(he_dev, group))
 					he_service_rbpl(he_dev, group);
 				break;
 			case ITYPE_TBRQ_THRESH:
 				HPRINTK("tbrq%d threshold\n", group);
-				/* fall through */
+				fallthrough;
 			case ITYPE_TPD_COMPLETE:
 				he_service_tbrq(he_dev, group);
 				break;
diff --git a/drivers/atm/horizon.c b/drivers/atm/horizon.c
deleted file mode 100644
index e5da51f907a2..000000000000
--- a/drivers/atm/horizon.c
+++ /dev/null
@@ -1,2893 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
-  Madge Horizon ATM Adapter driver.
-  Copyright (C) 1995-1999  Madge Networks Ltd.
-  
-*/
-
-/*
-  IMPORTANT NOTE: Madge Networks no longer makes the adapters
-  supported by this driver and makes no commitment to maintain it.
-*/
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/sched/signal.h>
-#include <linux/mm.h>
-#include <linux/pci.h>
-#include <linux/errno.h>
-#include <linux/atm.h>
-#include <linux/atmdev.h>
-#include <linux/sonet.h>
-#include <linux/skbuff.h>
-#include <linux/time.h>
-#include <linux/delay.h>
-#include <linux/uio.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/wait.h>
-#include <linux/slab.h>
-
-#include <asm/io.h>
-#include <linux/atomic.h>
-#include <linux/uaccess.h>
-#include <asm/string.h>
-#include <asm/byteorder.h>
-
-#include "horizon.h"
-
-#define maintainer_string "Giuliano Procida at Madge Networks <gprocida@madge.com>"
-#define description_string "Madge ATM Horizon [Ultra] driver"
-#define version_string "1.2.1"
-
-static inline void __init show_version (void) {
-  printk ("%s version %s\n", description_string, version_string);
-}
-
-/*
-  
-  CREDITS
-  
-  Driver and documentation by:
-  
-  Chris Aston        Madge Networks
-  Giuliano Procida   Madge Networks
-  Simon Benham       Madge Networks
-  Simon Johnson      Madge Networks
-  Various Others     Madge Networks
-  
-  Some inspiration taken from other drivers by:
-  
-  Alexandru Cucos    UTBv
-  Kari Mettinen      University of Helsinki
-  Werner Almesberger EPFL LRC
-  
-  Theory of Operation
-  
-  I Hardware, detection, initialisation and shutdown.
-  
-  1. Supported Hardware
-  
-  This driver should handle all variants of the PCI Madge ATM adapters
-  with the Horizon chipset. These are all PCI cards supporting PIO, BM
-  DMA and a form of MMIO (registers only, not internal RAM).
-  
-  The driver is only known to work with SONET and UTP Horizon Ultra
-  cards at 155Mb/s. However, code is in place to deal with both the
-  original Horizon and 25Mb/s operation.
-  
-  There are two revisions of the Horizon ASIC: the original and the
-  Ultra. Details of hardware bugs are in section III.
-  
-  The ASIC version can be distinguished by chip markings but is NOT
-  indicated by the PCI revision (all adapters seem to have PCI rev 1).
-  
-  I believe that:
-  
-  Horizon       => Collage  25 PCI Adapter (UTP and STP)
-  Horizon Ultra => Collage 155 PCI Client (UTP or SONET)
-  Ambassador x  => Collage 155 PCI Server (completely different)
-  
-  Horizon (25Mb/s) is fitted with UTP and STP connectors. It seems to
-  have a Madge B154 plus glue logic serializer. I have also found a
-  really ancient version of this with slightly different glue. It
-  comes with the revision 0 (140-025-01) ASIC.
-  
-  Horizon Ultra (155Mb/s) is fitted with either a Pulse Medialink
-  output (UTP) or an HP HFBR 5205 output (SONET). It has either
-  Madge's SAMBA framer or a SUNI-lite device (early versions). It
-  comes with the revision 1 (140-027-01) ASIC.
-  
-  2. Detection
-  
-  All Horizon-based cards present with the same PCI Vendor and Device
-  IDs. The standard Linux 2.2 PCI API is used to locate any cards and
-  to enable bus-mastering (with appropriate latency).
-  
-  ATM_LAYER_STATUS in the control register distinguishes between the
-  two possible physical layers (25 and 155). It is not clear whether
-  the 155 cards can also operate at 25Mbps. We rely on the fact that a
-  card operates at 155 if and only if it has the newer Horizon Ultra
-  ASIC.
-  
-  For 155 cards the two possible framers are probed for and then set
-  up for loop-timing.
-  
-  3. Initialisation
-  
-  The card is reset and then put into a known state. The physical
-  layer is configured for normal operation at the appropriate speed;
-  in the case of the 155 cards, the framer is initialised with
-  line-based timing; the internal RAM is zeroed and the allocation of
-  buffers for RX and TX is made; the Burnt In Address is read and
-  copied to the ATM ESI; various policy settings for RX (VPI bits,
-  unknown VCs, oam cells) are made. Ideally all policy items should be
-  configurable at module load (if not actually on-demand), however,
-  only the vpi vs vci bit allocation can be specified at insmod.
-  
-  4. Shutdown
-  
-  This is in response to module_cleaup. No VCs are in use and the card
-  should be idle; it is reset.
-  
-  II Driver software (as it should be)
-  
-  0. Traffic Parameters
-  
-  The traffic classes (not an enumeration) are currently: ATM_NONE (no
-  traffic), ATM_UBR, ATM_CBR, ATM_VBR and ATM_ABR, ATM_ANYCLASS
-  (compatible with everything). Together with (perhaps only some of)
-  the following items they make up the traffic specification.
-  
-  struct atm_trafprm {
-    unsigned char traffic_class; traffic class (ATM_UBR, ...)
-    int           max_pcr;       maximum PCR in cells per second
-    int           pcr;           desired PCR in cells per second
-    int           min_pcr;       minimum PCR in cells per second
-    int           max_cdv;       maximum CDV in microseconds
-    int           max_sdu;       maximum SDU in bytes
-  };
-  
-  Note that these denote bandwidth available not bandwidth used; the
-  possibilities according to ATMF are:
-  
-  Real Time (cdv and max CDT given)
-  
-  CBR(pcr)             pcr bandwidth always available
-  rtVBR(pcr,scr,mbs)   scr bandwidth always available, up to pcr at mbs too
-  
-  Non Real Time
-  
-  nrtVBR(pcr,scr,mbs)  scr bandwidth always available, up to pcr at mbs too
-  UBR()
-  ABR(mcr,pcr)         mcr bandwidth always available, up to pcr (depending) too
-  
-  mbs is max burst size (bucket)
-  pcr and scr have associated cdvt values
-  mcr is like scr but has no cdtv
-  cdtv may differ at each hop
-  
-  Some of the above items are qos items (as opposed to traffic
-  parameters). We have nothing to do with qos. All except ABR can have
-  their traffic parameters converted to GCRA parameters. The GCRA may
-  be implemented as a (real-number) leaky bucket. The GCRA can be used
-  in complicated ways by switches and in simpler ways by end-stations.
-  It can be used both to filter incoming cells and shape out-going
-  cells.
-  
-  ATM Linux actually supports:
-  
-  ATM_NONE() (no traffic in this direction)
-  ATM_UBR(max_frame_size)
-  ATM_CBR(max/min_pcr, max_cdv, max_frame_size)
-  
-  0 or ATM_MAX_PCR are used to indicate maximum available PCR
-  
-  A traffic specification consists of the AAL type and separate
-  traffic specifications for either direction. In ATM Linux it is:
-  
-  struct atm_qos {
-  struct atm_trafprm txtp;
-  struct atm_trafprm rxtp;
-  unsigned char aal;
-  };
-  
-  AAL types are:
-  
-  ATM_NO_AAL    AAL not specified
-  ATM_AAL0      "raw" ATM cells
-  ATM_AAL1      AAL1 (CBR)
-  ATM_AAL2      AAL2 (VBR)
-  ATM_AAL34     AAL3/4 (data)
-  ATM_AAL5      AAL5 (data)
-  ATM_SAAL      signaling AAL
-  
-  The Horizon has support for AAL frame types: 0, 3/4 and 5. However,
-  it does not implement AAL 3/4 SAR and it has a different notion of
-  "raw cell" to ATM Linux's (48 bytes vs. 52 bytes) so neither are
-  supported by this driver.
-  
-  The Horizon has limited support for ABR (including UBR), VBR and
-  CBR. Each TX channel has a bucket (containing up to 31 cell units)
-  and two timers (PCR and SCR) associated with it that can be used to
-  govern cell emissions and host notification (in the case of ABR this
-  is presumably so that RM cells may be emitted at appropriate times).
-  The timers may either be disabled or may be set to any of 240 values
-  (determined by the clock crystal, a fixed (?) per-device divider, a
-  configurable divider and a configurable timer preload value).
-  
-  At the moment only UBR and CBR are supported by the driver. VBR will
-  be supported as soon as ATM for Linux supports it. ABR support is
-  very unlikely as RM cell handling is completely up to the driver.
-  
-  1. TX (TX channel setup and TX transfer)
-  
-  The TX half of the driver owns the TX Horizon registers. The TX
-  component in the IRQ handler is the BM completion handler. This can
-  only be entered when tx_busy is true (enforced by hardware). The
-  other TX component can only be entered when tx_busy is false
-  (enforced by driver). So TX is single-threaded.
-  
-  Apart from a minor optimisation to not re-select the last channel,
-  the TX send component works as follows:
-  
-  Atomic test and set tx_busy until we succeed; we should implement
-  some sort of timeout so that tx_busy will never be stuck at true.
-  
-  If no TX channel is set up for this VC we wait for an idle one (if
-  necessary) and set it up.
-  
-  At this point we have a TX channel ready for use. We wait for enough
-  buffers to become available then start a TX transmit (set the TX
-  descriptor, schedule transfer, exit).
-  
-  The IRQ component handles TX completion (stats, free buffer, tx_busy
-  unset, exit). We also re-schedule further transfers for the same
-  frame if needed.
-  
-  TX setup in more detail:
-  
-  TX open is a nop, the relevant information is held in the hrz_vcc
-  (vcc->dev_data) structure and is "cached" on the card.
-  
-  TX close gets the TX lock and clears the channel from the "cache".
-  
-  2. RX (Data Available and RX transfer)
-  
-  The RX half of the driver owns the RX registers. There are two RX
-  components in the IRQ handler: the data available handler deals with
-  fresh data that has arrived on the card, the BM completion handler
-  is very similar to the TX completion handler. The data available
-  handler grabs the rx_lock and it is only released once the data has
-  been discarded or completely transferred to the host. The BM
-  completion handler only runs when the lock is held; the data
-  available handler is locked out over the same period.
-  
-  Data available on the card triggers an interrupt. If the data is not
-  suitable for our existing RX channels or we cannot allocate a buffer
-  it is flushed. Otherwise an RX receive is scheduled. Multiple RX
-  transfers may be scheduled for the same frame.
-  
-  RX setup in more detail:
-  
-  RX open...
-  RX close...
-  
-  III Hardware Bugs
-  
-  0. Byte vs Word addressing of adapter RAM.
-  
-  A design feature; see the .h file (especially the memory map).
-  
-  1. Bus Master Data Transfers (original Horizon only, fixed in Ultra)
-  
-  The host must not start a transmit direction transfer at a
-  non-four-byte boundary in host memory. Instead the host should
-  perform a byte, or a two byte, or one byte followed by two byte
-  transfer in order to start the rest of the transfer on a four byte
-  boundary. RX is OK.
-  
-  Simultaneous transmit and receive direction bus master transfers are
-  not allowed.
-  
-  The simplest solution to these two is to always do PIO (never DMA)
-  in the TX direction on the original Horizon. More complicated
-  solutions are likely to hurt my brain.
-  
-  2. Loss of buffer on close VC
-  
-  When a VC is being closed, the buffer associated with it is not
-  returned to the pool. The host must store the reference to this
-  buffer and when opening a new VC then give it to that new VC.
-  
-  The host intervention currently consists of stacking such a buffer
-  pointer at VC close and checking the stack at VC open.
-  
-  3. Failure to close a VC
-  
-  If a VC is currently receiving a frame then closing the VC may fail
-  and the frame continues to be received.
-  
-  The solution is to make sure any received frames are flushed when
-  ready. This is currently done just before the solution to 2.
-  
-  4. PCI bus (original Horizon only, fixed in Ultra)
-  
-  Reading from the data port prior to initialisation will hang the PCI
-  bus. Just don't do that then! We don't.
-  
-  IV To Do List
-  
-  . Timer code may be broken.
-  
-  . Allow users to specify buffer allocation split for TX and RX.
-  
-  . Deal once and for all with buggy VC close.
-  
-  . Handle interrupted and/or non-blocking operations.
-  
-  . Change some macros to functions and move from .h to .c.
-  
-  . Try to limit the number of TX frames each VC may have queued, in
-    order to reduce the chances of TX buffer exhaustion.
-  
-  . Implement VBR (bucket and timers not understood) and ABR (need to
-    do RM cells manually); also no Linux support for either.
-  
-  . Implement QoS changes on open VCs (involves extracting parts of VC open
-    and close into separate functions and using them to make changes).
-  
-*/
-
-/********** globals **********/
-
-static void do_housekeeping (struct timer_list *t);
-
-static unsigned short debug = 0;
-static unsigned short vpi_bits = 0;
-static int max_tx_size = 9000;
-static int max_rx_size = 9000;
-static unsigned char pci_lat = 0;
-
-/********** access functions **********/
-
-/* Read / Write Horizon registers */
-static inline void wr_regl (const hrz_dev * dev, unsigned char reg, u32 data) {
-  outl (cpu_to_le32 (data), dev->iobase + reg);
-}
-
-static inline u32 rd_regl (const hrz_dev * dev, unsigned char reg) {
-  return le32_to_cpu (inl (dev->iobase + reg));
-}
-
-static inline void wr_regw (const hrz_dev * dev, unsigned char reg, u16 data) {
-  outw (cpu_to_le16 (data), dev->iobase + reg);
-}
-
-static inline u16 rd_regw (const hrz_dev * dev, unsigned char reg) {
-  return le16_to_cpu (inw (dev->iobase + reg));
-}
-
-static inline void wrs_regb (const hrz_dev * dev, unsigned char reg, void * addr, u32 len) {
-  outsb (dev->iobase + reg, addr, len);
-}
-
-static inline void rds_regb (const hrz_dev * dev, unsigned char reg, void * addr, u32 len) {
-  insb (dev->iobase + reg, addr, len);
-}
-
-/* Read / Write to a given address in Horizon buffer memory.
-   Interrupts must be disabled between the address register and data
-   port accesses as these must form an atomic operation. */
-static inline void wr_mem (const hrz_dev * dev, HDW * addr, u32 data) {
-  // wr_regl (dev, MEM_WR_ADDR_REG_OFF, (u32) addr);
-  wr_regl (dev, MEM_WR_ADDR_REG_OFF, (addr - (HDW *) 0) * sizeof(HDW));
-  wr_regl (dev, MEMORY_PORT_OFF, data);
-}
-
-static inline u32 rd_mem (const hrz_dev * dev, HDW * addr) {
-  // wr_regl (dev, MEM_RD_ADDR_REG_OFF, (u32) addr);
-  wr_regl (dev, MEM_RD_ADDR_REG_OFF, (addr - (HDW *) 0) * sizeof(HDW));
-  return rd_regl (dev, MEMORY_PORT_OFF);
-}
-
-static inline void wr_framer (const hrz_dev * dev, u32 addr, u32 data) {
-  wr_regl (dev, MEM_WR_ADDR_REG_OFF, (u32) addr | 0x80000000);
-  wr_regl (dev, MEMORY_PORT_OFF, data);
-}
-
-static inline u32 rd_framer (const hrz_dev * dev, u32 addr) {
-  wr_regl (dev, MEM_RD_ADDR_REG_OFF, (u32) addr | 0x80000000);
-  return rd_regl (dev, MEMORY_PORT_OFF);
-}
-
-/********** specialised access functions **********/
-
-/* RX */
-
-static inline void FLUSH_RX_CHANNEL (hrz_dev * dev, u16 channel) {
-  wr_regw (dev, RX_CHANNEL_PORT_OFF, FLUSH_CHANNEL | channel);
-  return;
-}
-
-static void WAIT_FLUSH_RX_COMPLETE (hrz_dev * dev) {
-  while (rd_regw (dev, RX_CHANNEL_PORT_OFF) & FLUSH_CHANNEL)
-    ;
-  return;
-}
-
-static inline void SELECT_RX_CHANNEL (hrz_dev * dev, u16 channel) {
-  wr_regw (dev, RX_CHANNEL_PORT_OFF, channel);
-  return;
-}
-
-static void WAIT_UPDATE_COMPLETE (hrz_dev * dev) {
-  while (rd_regw (dev, RX_CHANNEL_PORT_OFF) & RX_CHANNEL_UPDATE_IN_PROGRESS)
-    ;
-  return;
-}
-
-/* TX */
-
-static inline void SELECT_TX_CHANNEL (hrz_dev * dev, u16 tx_channel) {
-  wr_regl (dev, TX_CHANNEL_PORT_OFF, tx_channel);
-  return;
-}
-
-/* Update or query one configuration parameter of a particular channel. */
-
-static inline void update_tx_channel_config (hrz_dev * dev, short chan, u8 mode, u16 value) {
-  wr_regw (dev, TX_CHANNEL_CONFIG_COMMAND_OFF,
-	   chan * TX_CHANNEL_CONFIG_MULT | mode);
-    wr_regw (dev, TX_CHANNEL_CONFIG_DATA_OFF, value);
-    return;
-}
-
-/********** dump functions **********/
-
-static inline void dump_skb (char * prefix, unsigned int vc, struct sk_buff * skb) {
-#ifdef DEBUG_HORIZON
-  unsigned int i;
-  unsigned char * data = skb->data;
-  PRINTDB (DBG_DATA, "%s(%u) ", prefix, vc);
-  for (i=0; i<skb->len && i < 256;i++)
-    PRINTDM (DBG_DATA, "%02x ", data[i]);
-  PRINTDE (DBG_DATA,"");
-#else
-  (void) prefix;
-  (void) vc;
-  (void) skb;
-#endif
-  return;
-}
-
-static inline void dump_regs (hrz_dev * dev) {
-#ifdef DEBUG_HORIZON
-  PRINTD (DBG_REGS, "CONTROL 0: %#x", rd_regl (dev, CONTROL_0_REG));
-  PRINTD (DBG_REGS, "RX CONFIG: %#x", rd_regw (dev, RX_CONFIG_OFF));
-  PRINTD (DBG_REGS, "TX CONFIG: %#x", rd_regw (dev, TX_CONFIG_OFF));
-  PRINTD (DBG_REGS, "TX STATUS: %#x", rd_regw (dev, TX_STATUS_OFF));
-  PRINTD (DBG_REGS, "IRQ ENBLE: %#x", rd_regl (dev, INT_ENABLE_REG_OFF));
-  PRINTD (DBG_REGS, "IRQ SORCE: %#x", rd_regl (dev, INT_SOURCE_REG_OFF));
-#else
-  (void) dev;
-#endif
-  return;
-}
-
-static inline void dump_framer (hrz_dev * dev) {
-#ifdef DEBUG_HORIZON
-  unsigned int i;
-  PRINTDB (DBG_REGS, "framer registers:");
-  for (i = 0; i < 0x10; ++i)
-    PRINTDM (DBG_REGS, " %02x", rd_framer (dev, i));
-  PRINTDE (DBG_REGS,"");
-#else
-  (void) dev;
-#endif
-  return;
-}
-
-/********** VPI/VCI <-> (RX) channel conversions **********/
-
-/* RX channels are 10 bit integers, these fns are quite paranoid */
-
-static inline int vpivci_to_channel (u16 * channel, const short vpi, const int vci) {
-  unsigned short vci_bits = 10 - vpi_bits;
-  if (0 <= vpi && vpi < 1<<vpi_bits && 0 <= vci && vci < 1<<vci_bits) {
-    *channel = vpi<<vci_bits | vci;
-    return *channel ? 0 : -EINVAL;
-  }
-  return -EINVAL;
-}
-
-/********** decode RX queue entries **********/
-
-static inline u16 rx_q_entry_to_length (u32 x) {
-  return x & RX_Q_ENTRY_LENGTH_MASK;
-}
-
-static inline u16 rx_q_entry_to_rx_channel (u32 x) {
-  return (x>>RX_Q_ENTRY_CHANNEL_SHIFT) & RX_CHANNEL_MASK;
-}
-
-/* Cell Transmit Rate Values
- *
- * the cell transmit rate (cells per sec) can be set to a variety of
- * different values by specifying two parameters: a timer preload from
- * 1 to 16 (stored as 0 to 15) and a clock divider (2 to the power of
- * an exponent from 0 to 14; the special value 15 disables the timer).
- *
- * cellrate = baserate / (preload * 2^divider)
- *
- * The maximum cell rate that can be specified is therefore just the
- * base rate. Halving the preload is equivalent to adding 1 to the
- * divider and so values 1 to 8 of the preload are redundant except
- * in the case of a maximal divider (14).
- *
- * Given a desired cell rate, an algorithm to determine the preload
- * and divider is:
- * 
- * a) x = baserate / cellrate, want p * 2^d = x (as far as possible)
- * b) if x > 16 * 2^14 then set p = 16, d = 14 (min rate), done
- *    if x <= 16 then set p = x, d = 0 (high rates), done
- * c) now have 16 < x <= 2^18, or 1 < x/16 <= 2^14 and we want to
- *    know n such that 2^(n-1) < x/16 <= 2^n, so slide a bit until
- *    we find the range (n will be between 1 and 14), set d = n
- * d) Also have 8 < x/2^n <= 16, so set p nearest x/2^n
- *
- * The algorithm used below is a minor variant of the above.
- *
- * The base rate is derived from the oscillator frequency (Hz) using a
- * fixed divider:
- *
- * baserate = freq / 32 in the case of some Unknown Card
- * baserate = freq / 8  in the case of the Horizon        25
- * baserate = freq / 8  in the case of the Horizon Ultra 155
- *
- * The Horizon cards have oscillators and base rates as follows:
- *
- * Card               Oscillator  Base Rate
- * Unknown Card       33 MHz      1.03125 MHz (33 MHz = PCI freq)
- * Horizon        25  32 MHz      4       MHz
- * Horizon Ultra 155  40 MHz      5       MHz
- *
- * The following defines give the base rates in Hz. These were
- * previously a factor of 100 larger, no doubt someone was using
- * cps*100.
- */
-
-#define BR_UKN 1031250l
-#define BR_HRZ 4000000l
-#define BR_ULT 5000000l
-
-// d is an exponent
-#define CR_MIND 0
-#define CR_MAXD 14
-
-// p ranges from 1 to a power of 2
-#define CR_MAXPEXP 4
- 
-static int make_rate (const hrz_dev * dev, u32 c, rounding r,
-		      u16 * bits, unsigned int * actual)
-{
-	// note: rounding the rate down means rounding 'p' up
-	const unsigned long br = test_bit(ultra, &dev->flags) ? BR_ULT : BR_HRZ;
-  
-	u32 div = CR_MIND;
-	u32 pre;
-  
-	// br_exp and br_man are used to avoid overflowing (c*maxp*2^d) in
-	// the tests below. We could think harder about exact possibilities
-	// of failure...
-  
-	unsigned long br_man = br;
-	unsigned int br_exp = 0;
-  
-	PRINTD (DBG_QOS|DBG_FLOW, "make_rate b=%lu, c=%u, %s", br, c,
-		r == round_up ? "up" : r == round_down ? "down" : "nearest");
-  
-	// avoid div by zero
-	if (!c) {
-		PRINTD (DBG_QOS|DBG_ERR, "zero rate is not allowed!");
-		return -EINVAL;
-	}
-  
-	while (br_exp < CR_MAXPEXP + CR_MIND && (br_man % 2 == 0)) {
-		br_man = br_man >> 1;
-		++br_exp;
-	}
-	// (br >>br_exp) <<br_exp == br and
-	// br_exp <= CR_MAXPEXP+CR_MIND
-  
-	if (br_man <= (c << (CR_MAXPEXP+CR_MIND-br_exp))) {
-		// Equivalent to: B <= (c << (MAXPEXP+MIND))
-		// take care of rounding
-		switch (r) {
-			case round_down:
-				pre = DIV_ROUND_UP(br, c<<div);
-				// but p must be non-zero
-				if (!pre)
-					pre = 1;
-				break;
-			case round_nearest:
-				pre = DIV_ROUND_CLOSEST(br, c<<div);
-				// but p must be non-zero
-				if (!pre)
-					pre = 1;
-				break;
-			default:	/* round_up */
-				pre = br/(c<<div);
-				// but p must be non-zero
-				if (!pre)
-					return -EINVAL;
-		}
-		PRINTD (DBG_QOS, "A: p=%u, d=%u", pre, div);
-		goto got_it;
-	}
-  
-	// at this point we have
-	// d == MIND and (c << (MAXPEXP+MIND)) < B
-	while (div < CR_MAXD) {
-		div++;
-		if (br_man <= (c << (CR_MAXPEXP+div-br_exp))) {
-			// Equivalent to: B <= (c << (MAXPEXP+d))
-			// c << (MAXPEXP+d-1) < B <= c << (MAXPEXP+d)
-			// 1 << (MAXPEXP-1) < B/2^d/c <= 1 << MAXPEXP
-			// MAXP/2 < B/c2^d <= MAXP
-			// take care of rounding
-			switch (r) {
-				case round_down:
-					pre = DIV_ROUND_UP(br, c<<div);
-					break;
-				case round_nearest:
-					pre = DIV_ROUND_CLOSEST(br, c<<div);
-					break;
-				default: /* round_up */
-					pre = br/(c<<div);
-			}
-			PRINTD (DBG_QOS, "B: p=%u, d=%u", pre, div);
-			goto got_it;
-		}
-	}
-	// at this point we have
-	// d == MAXD and (c << (MAXPEXP+MAXD)) < B
-	// but we cannot go any higher
-	// take care of rounding
-	if (r == round_down)
-		return -EINVAL;
-	pre = 1 << CR_MAXPEXP;
-	PRINTD (DBG_QOS, "C: p=%u, d=%u", pre, div);
-got_it:
-	// paranoia
-	if (div > CR_MAXD || (!pre) || pre > 1<<CR_MAXPEXP) {
-		PRINTD (DBG_QOS, "set_cr internal failure: d=%u p=%u",
-			div, pre);
-		return -EINVAL;
-	} else {
-		if (bits)
-			*bits = (div<<CLOCK_SELECT_SHIFT) | (pre-1);
-		if (actual) {
-			*actual = DIV_ROUND_UP(br, pre<<div);
-			PRINTD (DBG_QOS, "actual rate: %u", *actual);
-		}
-		return 0;
-	}
-}
-
-static int make_rate_with_tolerance (const hrz_dev * dev, u32 c, rounding r, unsigned int tol,
-				     u16 * bit_pattern, unsigned int * actual) {
-  unsigned int my_actual;
-  
-  PRINTD (DBG_QOS|DBG_FLOW, "make_rate_with_tolerance c=%u, %s, tol=%u",
-	  c, (r == round_up) ? "up" : (r == round_down) ? "down" : "nearest", tol);
-  
-  if (!actual)
-    // actual rate is not returned
-    actual = &my_actual;
-  
-  if (make_rate (dev, c, round_nearest, bit_pattern, actual))
-    // should never happen as round_nearest always succeeds
-    return -1;
-  
-  if (c - tol <= *actual && *actual <= c + tol)
-    // within tolerance
-    return 0;
-  else
-    // intolerant, try rounding instead
-    return make_rate (dev, c, r, bit_pattern, actual);
-}
-
-/********** Listen on a VC **********/
-
-static int hrz_open_rx (hrz_dev * dev, u16 channel) {
-  // is there any guarantee that we don't get two simulataneous
-  // identical calls of this function from different processes? yes
-  // rate_lock
-  unsigned long flags;
-  u32 channel_type; // u16?
-  
-  u16 buf_ptr = RX_CHANNEL_IDLE;
-  
-  rx_ch_desc * rx_desc = &memmap->rx_descs[channel];
-  
-  PRINTD (DBG_FLOW, "hrz_open_rx %x", channel);
-  
-  spin_lock_irqsave (&dev->mem_lock, flags);
-  channel_type = rd_mem (dev, &rx_desc->wr_buf_type) & BUFFER_PTR_MASK;
-  spin_unlock_irqrestore (&dev->mem_lock, flags);
-  
-  // very serious error, should never occur
-  if (channel_type != RX_CHANNEL_DISABLED) {
-    PRINTD (DBG_ERR|DBG_VCC, "RX channel for VC already open");
-    return -EBUSY; // clean up?
-  }
-  
-  // Give back spare buffer
-  if (dev->noof_spare_buffers) {
-    buf_ptr = dev->spare_buffers[--dev->noof_spare_buffers];
-    PRINTD (DBG_VCC, "using a spare buffer: %u", buf_ptr);
-    // should never occur
-    if (buf_ptr == RX_CHANNEL_DISABLED || buf_ptr == RX_CHANNEL_IDLE) {
-      // but easy to recover from
-      PRINTD (DBG_ERR|DBG_VCC, "bad spare buffer pointer, using IDLE");
-      buf_ptr = RX_CHANNEL_IDLE;
-    }
-  } else {
-    PRINTD (DBG_VCC, "using IDLE buffer pointer");
-  }
-  
-  // Channel is currently disabled so change its status to idle
-  
-  // do we really need to save the flags again?
-  spin_lock_irqsave (&dev->mem_lock, flags);
-  
-  wr_mem (dev, &rx_desc->wr_buf_type,
-	  buf_ptr | CHANNEL_TYPE_AAL5 | FIRST_CELL_OF_AAL5_FRAME);
-  if (buf_ptr != RX_CHANNEL_IDLE)
-    wr_mem (dev, &rx_desc->rd_buf_type, buf_ptr);
-  
-  spin_unlock_irqrestore (&dev->mem_lock, flags);
-  
-  // rxer->rate = make_rate (qos->peak_cells);
-  
-  PRINTD (DBG_FLOW, "hrz_open_rx ok");
-  
-  return 0;
-}
-
-#if 0
-/********** change vc rate for a given vc **********/
-
-static void hrz_change_vc_qos (ATM_RXER * rxer, MAAL_QOS * qos) {
-  rxer->rate = make_rate (qos->peak_cells);
-}
-#endif
-
-/********** free an skb (as per ATM device driver documentation) **********/
-
-static void hrz_kfree_skb (struct sk_buff * skb) {
-  if (ATM_SKB(skb)->vcc->pop) {
-    ATM_SKB(skb)->vcc->pop (ATM_SKB(skb)->vcc, skb);
-  } else {
-    dev_kfree_skb_any (skb);
-  }
-}
-
-/********** cancel listen on a VC **********/
-
-static void hrz_close_rx (hrz_dev * dev, u16 vc) {
-  unsigned long flags;
-  
-  u32 value;
-  
-  u32 r1, r2;
-  
-  rx_ch_desc * rx_desc = &memmap->rx_descs[vc];
-  
-  int was_idle = 0;
-  
-  spin_lock_irqsave (&dev->mem_lock, flags);
-  value = rd_mem (dev, &rx_desc->wr_buf_type) & BUFFER_PTR_MASK;
-  spin_unlock_irqrestore (&dev->mem_lock, flags);
-  
-  if (value == RX_CHANNEL_DISABLED) {
-    // I suppose this could happen once we deal with _NONE traffic properly
-    PRINTD (DBG_VCC, "closing VC: RX channel %u already disabled", vc);
-    return;
-  }
-  if (value == RX_CHANNEL_IDLE)
-    was_idle = 1;
-  
-  spin_lock_irqsave (&dev->mem_lock, flags);
-  
-  for (;;) {
-    wr_mem (dev, &rx_desc->wr_buf_type, RX_CHANNEL_DISABLED);
-    
-    if ((rd_mem (dev, &rx_desc->wr_buf_type) & BUFFER_PTR_MASK) == RX_CHANNEL_DISABLED)
-      break;
-    
-    was_idle = 0;
-  }
-  
-  if (was_idle) {
-    spin_unlock_irqrestore (&dev->mem_lock, flags);
-    return;
-  }
-  
-  WAIT_FLUSH_RX_COMPLETE(dev);
-  
-  // XXX Is this all really necessary? We can rely on the rx_data_av
-  // handler to discard frames that remain queued for delivery. If the
-  // worry is that immediately reopening the channel (perhaps by a
-  // different process) may cause some data to be mis-delivered then
-  // there may still be a simpler solution (such as busy-waiting on
-  // rx_busy once the channel is disabled or before a new one is
-  // opened - does this leave any holes?). Arguably setting up and
-  // tearing down the TX and RX halves of each virtual circuit could
-  // most safely be done within ?x_busy protected regions.
-  
-  // OK, current changes are that Simon's marker is disabled and we DO
-  // look for NULL rxer elsewhere. The code here seems flush frames
-  // and then remember the last dead cell belonging to the channel
-  // just disabled - the cell gets relinked at the next vc_open.
-  // However, when all VCs are closed or only a few opened there are a
-  // handful of buffers that are unusable.
-  
-  // Does anyone feel like documenting spare_buffers properly?
-  // Does anyone feel like fixing this in a nicer way?
-  
-  // Flush any data which is left in the channel
-  for (;;) {
-    // Change the rx channel port to something different to the RX
-    // channel we are trying to close to force Horizon to flush the rx
-    // channel read and write pointers.
-    
-    u16 other = vc^(RX_CHANS/2);
-    
-    SELECT_RX_CHANNEL (dev, other);
-    WAIT_UPDATE_COMPLETE (dev);
-    
-    r1 = rd_mem (dev, &rx_desc->rd_buf_type);
-    
-    // Select this RX channel. Flush doesn't seem to work unless we
-    // select an RX channel before hand
-    
-    SELECT_RX_CHANNEL (dev, vc);
-    WAIT_UPDATE_COMPLETE (dev);
-    
-    // Attempt to flush a frame on this RX channel
-    
-    FLUSH_RX_CHANNEL (dev, vc);
-    WAIT_FLUSH_RX_COMPLETE (dev);
-    
-    // Force Horizon to flush rx channel read and write pointers as before
-    
-    SELECT_RX_CHANNEL (dev, other);
-    WAIT_UPDATE_COMPLETE (dev);
-    
-    r2 = rd_mem (dev, &rx_desc->rd_buf_type);
-    
-    PRINTD (DBG_VCC|DBG_RX, "r1 = %u, r2 = %u", r1, r2);
-    
-    if (r1 == r2) {
-      dev->spare_buffers[dev->noof_spare_buffers++] = (u16)r1;
-      break;
-    }
-  }
-  
-#if 0
-  {
-    rx_q_entry * wr_ptr = &memmap->rx_q_entries[rd_regw (dev, RX_QUEUE_WR_PTR_OFF)];
-    rx_q_entry * rd_ptr = dev->rx_q_entry;
-    
-    PRINTD (DBG_VCC|DBG_RX, "rd_ptr = %u, wr_ptr = %u", rd_ptr, wr_ptr);
-    
-    while (rd_ptr != wr_ptr) {
-      u32 x = rd_mem (dev, (HDW *) rd_ptr);
-      
-      if (vc == rx_q_entry_to_rx_channel (x)) {
-	x |= SIMONS_DODGEY_MARKER;
-	
-	PRINTD (DBG_RX|DBG_VCC|DBG_WARN, "marking a frame as dodgey");
-	
-	wr_mem (dev, (HDW *) rd_ptr, x);
-      }
-      
-      if (rd_ptr == dev->rx_q_wrap)
-	rd_ptr = dev->rx_q_reset;
-      else
-	rd_ptr++;
-    }
-  }
-#endif
-  
-  spin_unlock_irqrestore (&dev->mem_lock, flags);
-  
-  return;
-}
-
-/********** schedule RX transfers **********/
-
-// Note on tail recursion: a GCC developer said that it is not likely
-// to be fixed soon, so do not define TAILRECUSRIONWORKS unless you
-// are sure it does as you may otherwise overflow the kernel stack.
-
-// giving this fn a return value would help GCC, allegedly
-
-static void rx_schedule (hrz_dev * dev, int irq) {
-  unsigned int rx_bytes;
-  
-  int pio_instead = 0;
-#ifndef TAILRECURSIONWORKS
-  pio_instead = 1;
-  while (pio_instead) {
-#endif
-    // bytes waiting for RX transfer
-    rx_bytes = dev->rx_bytes;
-    
-#if 0
-    spin_count = 0;
-    while (rd_regl (dev, MASTER_RX_COUNT_REG_OFF)) {
-      PRINTD (DBG_RX|DBG_WARN, "RX error: other PCI Bus Master RX still in progress!");
-      if (++spin_count > 10) {
-	PRINTD (DBG_RX|DBG_ERR, "spun out waiting PCI Bus Master RX completion");
-	wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0);
-	clear_bit (rx_busy, &dev->flags);
-	hrz_kfree_skb (dev->rx_skb);
-	return;
-      }
-    }
-#endif
-    
-    // this code follows the TX code but (at the moment) there is only
-    // one region - the skb itself. I don't know if this will change,
-    // but it doesn't hurt to have the code here, disabled.
-    
-    if (rx_bytes) {
-      // start next transfer within same region
-      if (rx_bytes <= MAX_PIO_COUNT) {
-	PRINTD (DBG_RX|DBG_BUS, "(pio)");
-	pio_instead = 1;
-      }
-      if (rx_bytes <= MAX_TRANSFER_COUNT) {
-	PRINTD (DBG_RX|DBG_BUS, "(simple or last multi)");
-	dev->rx_bytes = 0;
-      } else {
-	PRINTD (DBG_RX|DBG_BUS, "(continuing multi)");
-	dev->rx_bytes = rx_bytes - MAX_TRANSFER_COUNT;
-	rx_bytes = MAX_TRANSFER_COUNT;
-      }
-    } else {
-      // rx_bytes == 0 -- we're between regions
-      // regions remaining to transfer
-#if 0
-      unsigned int rx_regions = dev->rx_regions;
-#else
-      unsigned int rx_regions = 0;
-#endif
-      
-      if (rx_regions) {
-#if 0
-	// start a new region
-	dev->rx_addr = dev->rx_iovec->iov_base;
-	rx_bytes = dev->rx_iovec->iov_len;
-	++dev->rx_iovec;
-	dev->rx_regions = rx_regions - 1;
-	
-	if (rx_bytes <= MAX_PIO_COUNT) {
-	  PRINTD (DBG_RX|DBG_BUS, "(pio)");
-	  pio_instead = 1;
-	}
-	if (rx_bytes <= MAX_TRANSFER_COUNT) {
-	  PRINTD (DBG_RX|DBG_BUS, "(full region)");
-	  dev->rx_bytes = 0;
-	} else {
-	  PRINTD (DBG_RX|DBG_BUS, "(start multi region)");
-	  dev->rx_bytes = rx_bytes - MAX_TRANSFER_COUNT;
-	  rx_bytes = MAX_TRANSFER_COUNT;
-	}
-#endif
-      } else {
-	// rx_regions == 0
-	// that's all folks - end of frame
-	struct sk_buff * skb = dev->rx_skb;
-	// dev->rx_iovec = 0;
-	
-	FLUSH_RX_CHANNEL (dev, dev->rx_channel);
-	
-	dump_skb ("<<<", dev->rx_channel, skb);
-	
-	PRINTD (DBG_RX|DBG_SKB, "push %p %u", skb->data, skb->len);
-	
-	{
-	  struct atm_vcc * vcc = ATM_SKB(skb)->vcc;
-	  // VC layer stats
-	  atomic_inc(&vcc->stats->rx);
-	  __net_timestamp(skb);
-	  // end of our responsibility
-	  vcc->push (vcc, skb);
-	}
-      }
-    }
-    
-    // note: writing RX_COUNT clears any interrupt condition
-    if (rx_bytes) {
-      if (pio_instead) {
-	if (irq)
-	  wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0);
-	rds_regb (dev, DATA_PORT_OFF, dev->rx_addr, rx_bytes);
-      } else {
-	wr_regl (dev, MASTER_RX_ADDR_REG_OFF, virt_to_bus (dev->rx_addr));
-	wr_regl (dev, MASTER_RX_COUNT_REG_OFF, rx_bytes);
-      }
-      dev->rx_addr += rx_bytes;
-    } else {
-      if (irq)
-	wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0);
-      // allow another RX thread to start
-      YELLOW_LED_ON(dev);
-      clear_bit (rx_busy, &dev->flags);
-      PRINTD (DBG_RX, "cleared rx_busy for dev %p", dev);
-    }
-    
-#ifdef TAILRECURSIONWORKS
-    // and we all bless optimised tail calls
-    if (pio_instead)
-      return rx_schedule (dev, 0);
-    return;
-#else
-    // grrrrrrr!
-    irq = 0;
-  }
-  return;
-#endif
-}
-
-/********** handle RX bus master complete events **********/
-
-static void rx_bus_master_complete_handler (hrz_dev * dev) {
-  if (test_bit (rx_busy, &dev->flags)) {
-    rx_schedule (dev, 1);
-  } else {
-    PRINTD (DBG_RX|DBG_ERR, "unexpected RX bus master completion");
-    // clear interrupt condition on adapter
-    wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0);
-  }
-  return;
-}
-
-/********** (queue to) become the next TX thread **********/
-
-static int tx_hold (hrz_dev * dev) {
-  PRINTD (DBG_TX, "sleeping at tx lock %p %lu", dev, dev->flags);
-  wait_event_interruptible(dev->tx_queue, (!test_and_set_bit(tx_busy, &dev->flags)));
-  PRINTD (DBG_TX, "woken at tx lock %p %lu", dev, dev->flags);
-  if (signal_pending (current))
-    return -1;
-  PRINTD (DBG_TX, "set tx_busy for dev %p", dev);
-  return 0;
-}
-
-/********** allow another TX thread to start **********/
-
-static inline void tx_release (hrz_dev * dev) {
-  clear_bit (tx_busy, &dev->flags);
-  PRINTD (DBG_TX, "cleared tx_busy for dev %p", dev);
-  wake_up_interruptible (&dev->tx_queue);
-}
-
-/********** schedule TX transfers **********/
-
-static void tx_schedule (hrz_dev * const dev, int irq) {
-  unsigned int tx_bytes;
-  
-  int append_desc = 0;
-  
-  int pio_instead = 0;
-#ifndef TAILRECURSIONWORKS
-  pio_instead = 1;
-  while (pio_instead) {
-#endif
-    // bytes in current region waiting for TX transfer
-    tx_bytes = dev->tx_bytes;
-    
-#if 0
-    spin_count = 0;
-    while (rd_regl (dev, MASTER_TX_COUNT_REG_OFF)) {
-      PRINTD (DBG_TX|DBG_WARN, "TX error: other PCI Bus Master TX still in progress!");
-      if (++spin_count > 10) {
-	PRINTD (DBG_TX|DBG_ERR, "spun out waiting PCI Bus Master TX completion");
-	wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0);
-	tx_release (dev);
-	hrz_kfree_skb (dev->tx_skb);
-	return;
-      }
-    }
-#endif
-    
-    if (tx_bytes) {
-      // start next transfer within same region
-      if (!test_bit (ultra, &dev->flags) || tx_bytes <= MAX_PIO_COUNT) {
-	PRINTD (DBG_TX|DBG_BUS, "(pio)");
-	pio_instead = 1;
-      }
-      if (tx_bytes <= MAX_TRANSFER_COUNT) {
-	PRINTD (DBG_TX|DBG_BUS, "(simple or last multi)");
-	if (!dev->tx_iovec) {
-	  // end of last region
-	  append_desc = 1;
-	}
-	dev->tx_bytes = 0;
-      } else {
-	PRINTD (DBG_TX|DBG_BUS, "(continuing multi)");
-	dev->tx_bytes = tx_bytes - MAX_TRANSFER_COUNT;
-	tx_bytes = MAX_TRANSFER_COUNT;
-      }
-    } else {
-      // tx_bytes == 0 -- we're between regions
-      // regions remaining to transfer
-      unsigned int tx_regions = dev->tx_regions;
-      
-      if (tx_regions) {
-	// start a new region
-	dev->tx_addr = dev->tx_iovec->iov_base;
-	tx_bytes = dev->tx_iovec->iov_len;
-	++dev->tx_iovec;
-	dev->tx_regions = tx_regions - 1;
-	
-	if (!test_bit (ultra, &dev->flags) || tx_bytes <= MAX_PIO_COUNT) {
-	  PRINTD (DBG_TX|DBG_BUS, "(pio)");
-	  pio_instead = 1;
-	}
-	if (tx_bytes <= MAX_TRANSFER_COUNT) {
-	  PRINTD (DBG_TX|DBG_BUS, "(full region)");
-	  dev->tx_bytes = 0;
-	} else {
-	  PRINTD (DBG_TX|DBG_BUS, "(start multi region)");
-	  dev->tx_bytes = tx_bytes - MAX_TRANSFER_COUNT;
-	  tx_bytes = MAX_TRANSFER_COUNT;
-	}
-      } else {
-	// tx_regions == 0
-	// that's all folks - end of frame
-	struct sk_buff * skb = dev->tx_skb;
-	dev->tx_iovec = NULL;
-	
-	// VC layer stats
-	atomic_inc(&ATM_SKB(skb)->vcc->stats->tx);
-	
-	// free the skb
-	hrz_kfree_skb (skb);
-      }
-    }
-    
-    // note: writing TX_COUNT clears any interrupt condition
-    if (tx_bytes) {
-      if (pio_instead) {
-	if (irq)
-	  wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0);
-	wrs_regb (dev, DATA_PORT_OFF, dev->tx_addr, tx_bytes);
-	if (append_desc)
-	  wr_regl (dev, TX_DESCRIPTOR_PORT_OFF, cpu_to_be32 (dev->tx_skb->len));
-      } else {
-	wr_regl (dev, MASTER_TX_ADDR_REG_OFF, virt_to_bus (dev->tx_addr));
-	if (append_desc)
-	  wr_regl (dev, TX_DESCRIPTOR_REG_OFF, cpu_to_be32 (dev->tx_skb->len));
-	wr_regl (dev, MASTER_TX_COUNT_REG_OFF,
-		 append_desc
-		 ? tx_bytes | MASTER_TX_AUTO_APPEND_DESC
-		 : tx_bytes);
-      }
-      dev->tx_addr += tx_bytes;
-    } else {
-      if (irq)
-	wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0);
-      YELLOW_LED_ON(dev);
-      tx_release (dev);
-    }
-    
-#ifdef TAILRECURSIONWORKS
-    // and we all bless optimised tail calls
-    if (pio_instead)
-      return tx_schedule (dev, 0);
-    return;
-#else
-    // grrrrrrr!
-    irq = 0;
-  }
-  return;
-#endif
-}
-
-/********** handle TX bus master complete events **********/
-
-static void tx_bus_master_complete_handler (hrz_dev * dev) {
-  if (test_bit (tx_busy, &dev->flags)) {
-    tx_schedule (dev, 1);
-  } else {
-    PRINTD (DBG_TX|DBG_ERR, "unexpected TX bus master completion");
-    // clear interrupt condition on adapter
-    wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0);
-  }
-  return;
-}
-
-/********** move RX Q pointer to next item in circular buffer **********/
-
-// called only from IRQ sub-handler
-static u32 rx_queue_entry_next (hrz_dev * dev) {
-  u32 rx_queue_entry;
-  spin_lock (&dev->mem_lock);
-  rx_queue_entry = rd_mem (dev, &dev->rx_q_entry->entry);
-  if (dev->rx_q_entry == dev->rx_q_wrap)
-    dev->rx_q_entry = dev->rx_q_reset;
-  else
-    dev->rx_q_entry++;
-  wr_regw (dev, RX_QUEUE_RD_PTR_OFF, dev->rx_q_entry - dev->rx_q_reset);
-  spin_unlock (&dev->mem_lock);
-  return rx_queue_entry;
-}
-
-/********** handle RX data received by device **********/
-
-// called from IRQ handler
-static void rx_data_av_handler (hrz_dev * dev) {
-  u32 rx_queue_entry;
-  u32 rx_queue_entry_flags;
-  u16 rx_len;
-  u16 rx_channel;
-  
-  PRINTD (DBG_FLOW, "hrz_data_av_handler");
-  
-  // try to grab rx lock (not possible during RX bus mastering)
-  if (test_and_set_bit (rx_busy, &dev->flags)) {
-    PRINTD (DBG_RX, "locked out of rx lock");
-    return;
-  }
-  PRINTD (DBG_RX, "set rx_busy for dev %p", dev);
-  // lock is cleared if we fail now, o/w after bus master completion
-  
-  YELLOW_LED_OFF(dev);
-  
-  rx_queue_entry = rx_queue_entry_next (dev);
-  
-  rx_len = rx_q_entry_to_length (rx_queue_entry);
-  rx_channel = rx_q_entry_to_rx_channel (rx_queue_entry);
-  
-  WAIT_FLUSH_RX_COMPLETE (dev);
-  
-  SELECT_RX_CHANNEL (dev, rx_channel);
-  
-  PRINTD (DBG_RX, "rx_queue_entry is: %#x", rx_queue_entry);
-  rx_queue_entry_flags = rx_queue_entry & (RX_CRC_32_OK|RX_COMPLETE_FRAME|SIMONS_DODGEY_MARKER);
-  
-  if (!rx_len) {
-    // (at least) bus-mastering breaks if we try to handle a
-    // zero-length frame, besides AAL5 does not support them
-    PRINTK (KERN_ERR, "zero-length frame!");
-    rx_queue_entry_flags &= ~RX_COMPLETE_FRAME;
-  }
-  
-  if (rx_queue_entry_flags & SIMONS_DODGEY_MARKER) {
-    PRINTD (DBG_RX|DBG_ERR, "Simon's marker detected!");
-  }
-  if (rx_queue_entry_flags == (RX_CRC_32_OK | RX_COMPLETE_FRAME)) {
-    struct atm_vcc * atm_vcc;
-    
-    PRINTD (DBG_RX, "got a frame on rx_channel %x len %u", rx_channel, rx_len);
-    
-    atm_vcc = dev->rxer[rx_channel];
-    // if no vcc is assigned to this channel, we should drop the frame
-    // (is this what SIMONS etc. was trying to achieve?)
-    
-    if (atm_vcc) {
-      
-      if (atm_vcc->qos.rxtp.traffic_class != ATM_NONE) {
-	
-	if (rx_len <= atm_vcc->qos.rxtp.max_sdu) {
-	    
-	  struct sk_buff * skb = atm_alloc_charge (atm_vcc, rx_len, GFP_ATOMIC);
-	  if (skb) {
-	    // remember this so we can push it later
-	    dev->rx_skb = skb;
-	    // remember this so we can flush it later
-	    dev->rx_channel = rx_channel;
-	    
-	    // prepare socket buffer
-	    skb_put (skb, rx_len);
-	    ATM_SKB(skb)->vcc = atm_vcc;
-	    
-	    // simple transfer
-	    // dev->rx_regions = 0;
-	    // dev->rx_iovec = 0;
-	    dev->rx_bytes = rx_len;
-	    dev->rx_addr = skb->data;
-	    PRINTD (DBG_RX, "RX start simple transfer (addr %p, len %d)",
-		    skb->data, rx_len);
-	    
-	    // do the business
-	    rx_schedule (dev, 0);
-	    return;
-	    
-	  } else {
-	    PRINTD (DBG_SKB|DBG_WARN, "failed to get skb");
-	  }
-	  
-	} else {
-	  PRINTK (KERN_INFO, "frame received on TX-only VC %x", rx_channel);
-	  // do we count this?
-	}
-	
-      } else {
-	PRINTK (KERN_WARNING, "dropped over-size frame");
-	// do we count this?
-      }
-      
-    } else {
-      PRINTD (DBG_WARN|DBG_VCC|DBG_RX, "no VCC for this frame (VC closed)");
-      // do we count this?
-    }
-    
-  } else {
-    // Wait update complete ? SPONG
-  }
-  
-  // RX was aborted
-  YELLOW_LED_ON(dev);
-  
-  FLUSH_RX_CHANNEL (dev,rx_channel);
-  clear_bit (rx_busy, &dev->flags);
-  
-  return;
-}
-
-/********** interrupt handler **********/
-
-static irqreturn_t interrupt_handler(int irq, void *dev_id)
-{
-  hrz_dev *dev = dev_id;
-  u32 int_source;
-  unsigned int irq_ok;
-  
-  PRINTD (DBG_FLOW, "interrupt_handler: %p", dev_id);
-  
-  // definitely for us
-  irq_ok = 0;
-  while ((int_source = rd_regl (dev, INT_SOURCE_REG_OFF)
-	  & INTERESTING_INTERRUPTS)) {
-    // In the interests of fairness, the handlers below are
-    // called in sequence and without immediate return to the head of
-    // the while loop. This is only of issue for slow hosts (or when
-    // debugging messages are on). Really slow hosts may find a fast
-    // sender keeps them permanently in the IRQ handler. :(
-    
-    // (only an issue for slow hosts) RX completion goes before
-    // rx_data_av as the former implies rx_busy and so the latter
-    // would just abort. If it reschedules another transfer
-    // (continuing the same frame) then it will not clear rx_busy.
-    
-    // (only an issue for slow hosts) TX completion goes before RX
-    // data available as it is a much shorter routine - there is the
-    // chance that any further transfers it schedules will be complete
-    // by the time of the return to the head of the while loop
-    
-    if (int_source & RX_BUS_MASTER_COMPLETE) {
-      ++irq_ok;
-      PRINTD (DBG_IRQ|DBG_BUS|DBG_RX, "rx_bus_master_complete asserted");
-      rx_bus_master_complete_handler (dev);
-    }
-    if (int_source & TX_BUS_MASTER_COMPLETE) {
-      ++irq_ok;
-      PRINTD (DBG_IRQ|DBG_BUS|DBG_TX, "tx_bus_master_complete asserted");
-      tx_bus_master_complete_handler (dev);
-    }
-    if (int_source & RX_DATA_AV) {
-      ++irq_ok;
-      PRINTD (DBG_IRQ|DBG_RX, "rx_data_av asserted");
-      rx_data_av_handler (dev);
-    }
-  }
-  if (irq_ok) {
-    PRINTD (DBG_IRQ, "work done: %u", irq_ok);
-  } else {
-    PRINTD (DBG_IRQ|DBG_WARN, "spurious interrupt source: %#x", int_source);
-  }
-  
-  PRINTD (DBG_IRQ|DBG_FLOW, "interrupt_handler done: %p", dev_id);
-  if (irq_ok)
-	return IRQ_HANDLED;
-  return IRQ_NONE;
-}
-
-/********** housekeeping **********/
-
-static void do_housekeeping (struct timer_list *t) {
-  // just stats at the moment
-  hrz_dev * dev = from_timer(dev, t, housekeeping);
-
-  // collect device-specific (not driver/atm-linux) stats here
-  dev->tx_cell_count += rd_regw (dev, TX_CELL_COUNT_OFF);
-  dev->rx_cell_count += rd_regw (dev, RX_CELL_COUNT_OFF);
-  dev->hec_error_count += rd_regw (dev, HEC_ERROR_COUNT_OFF);
-  dev->unassigned_cell_count += rd_regw (dev, UNASSIGNED_CELL_COUNT_OFF);
-
-  mod_timer (&dev->housekeeping, jiffies + HZ/10);
-
-  return;
-}
-
-/********** find an idle channel for TX and set it up **********/
-
-// called with tx_busy set
-static short setup_idle_tx_channel (hrz_dev * dev, hrz_vcc * vcc) {
-  unsigned short idle_channels;
-  short tx_channel = -1;
-  unsigned int spin_count;
-  PRINTD (DBG_FLOW|DBG_TX, "setup_idle_tx_channel %p", dev);
-  
-  // better would be to fail immediately, the caller can then decide whether
-  // to wait or drop (depending on whether this is UBR etc.)
-  spin_count = 0;
-  while (!(idle_channels = rd_regw (dev, TX_STATUS_OFF) & IDLE_CHANNELS_MASK)) {
-    PRINTD (DBG_TX|DBG_WARN, "waiting for idle TX channel");
-    // delay a bit here
-    if (++spin_count > 100) {
-      PRINTD (DBG_TX|DBG_ERR, "spun out waiting for idle TX channel");
-      return -EBUSY;
-    }
-  }
-  
-  // got an idle channel
-  {
-    // tx_idle ensures we look for idle channels in RR order
-    int chan = dev->tx_idle;
-    
-    int keep_going = 1;
-    while (keep_going) {
-      if (idle_channels & (1<<chan)) {
-	tx_channel = chan;
-	keep_going = 0;
-      }
-      ++chan;
-      if (chan == TX_CHANS)
-	chan = 0;
-    }
-    
-    dev->tx_idle = chan;
-  }
-  
-  // set up the channel we found
-  {
-    // Initialise the cell header in the transmit channel descriptor
-    // a.k.a. prepare the channel and remember that we have done so.
-    
-    tx_ch_desc * tx_desc = &memmap->tx_descs[tx_channel];
-    u32 rd_ptr;
-    u32 wr_ptr;
-    u16 channel = vcc->channel;
-    
-    unsigned long flags;
-    spin_lock_irqsave (&dev->mem_lock, flags);
-    
-    // Update the transmit channel record.
-    dev->tx_channel_record[tx_channel] = channel;
-    
-    // xBR channel
-    update_tx_channel_config (dev, tx_channel, RATE_TYPE_ACCESS,
-			      vcc->tx_xbr_bits);
-    
-    // Update the PCR counter preload value etc.
-    update_tx_channel_config (dev, tx_channel, PCR_TIMER_ACCESS,
-			      vcc->tx_pcr_bits);
-
-#if 0
-    if (vcc->tx_xbr_bits == VBR_RATE_TYPE) {
-      // SCR timer
-      update_tx_channel_config (dev, tx_channel, SCR_TIMER_ACCESS,
-				vcc->tx_scr_bits);
-      
-      // Bucket size...
-      update_tx_channel_config (dev, tx_channel, BUCKET_CAPACITY_ACCESS,
-				vcc->tx_bucket_bits);
-      
-      // ... and fullness
-      update_tx_channel_config (dev, tx_channel, BUCKET_FULLNESS_ACCESS,
-				vcc->tx_bucket_bits);
-    }
-#endif
-
-    // Initialise the read and write buffer pointers
-    rd_ptr = rd_mem (dev, &tx_desc->rd_buf_type) & BUFFER_PTR_MASK;
-    wr_ptr = rd_mem (dev, &tx_desc->wr_buf_type) & BUFFER_PTR_MASK;
-    
-    // idle TX channels should have identical pointers
-    if (rd_ptr != wr_ptr) {
-      PRINTD (DBG_TX|DBG_ERR, "TX buffer pointers are broken!");
-      // spin_unlock... return -E...
-      // I wonder if gcc would get rid of one of the pointer aliases
-    }
-    PRINTD (DBG_TX, "TX buffer pointers are: rd %x, wr %x.",
-	    rd_ptr, wr_ptr);
-    
-    switch (vcc->aal) {
-      case aal0:
-	PRINTD (DBG_QOS|DBG_TX, "tx_channel: aal0");
-	rd_ptr |= CHANNEL_TYPE_RAW_CELLS;
-	wr_ptr |= CHANNEL_TYPE_RAW_CELLS;
-	break;
-      case aal34:
-	PRINTD (DBG_QOS|DBG_TX, "tx_channel: aal34");
-	rd_ptr |= CHANNEL_TYPE_AAL3_4;
-	wr_ptr |= CHANNEL_TYPE_AAL3_4;
-	break;
-      case aal5:
-	rd_ptr |= CHANNEL_TYPE_AAL5;
-	wr_ptr |= CHANNEL_TYPE_AAL5;
-	// Initialise the CRC
-	wr_mem (dev, &tx_desc->partial_crc, INITIAL_CRC);
-	break;
-    }
-    
-    wr_mem (dev, &tx_desc->rd_buf_type, rd_ptr);
-    wr_mem (dev, &tx_desc->wr_buf_type, wr_ptr);
-    
-    // Write the Cell Header
-    // Payload Type, CLP and GFC would go here if non-zero
-    wr_mem (dev, &tx_desc->cell_header, channel);
-    
-    spin_unlock_irqrestore (&dev->mem_lock, flags);
-  }
-  
-  return tx_channel;
-}
-
-/********** send a frame **********/
-
-static int hrz_send (struct atm_vcc * atm_vcc, struct sk_buff * skb) {
-  unsigned int spin_count;
-  int free_buffers;
-  hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
-  hrz_vcc * vcc = HRZ_VCC(atm_vcc);
-  u16 channel = vcc->channel;
-  
-  u32 buffers_required;
-  
-  /* signed for error return */
-  short tx_channel;
-  
-  PRINTD (DBG_FLOW|DBG_TX, "hrz_send vc %x data %p len %u",
-	  channel, skb->data, skb->len);
-  
-  dump_skb (">>>", channel, skb);
-  
-  if (atm_vcc->qos.txtp.traffic_class == ATM_NONE) {
-    PRINTK (KERN_ERR, "attempt to send on RX-only VC %x", channel);
-    hrz_kfree_skb (skb);
-    return -EIO;
-  }
-  
-  // don't understand this
-  ATM_SKB(skb)->vcc = atm_vcc;
-  
-  if (skb->len > atm_vcc->qos.txtp.max_sdu) {
-    PRINTK (KERN_ERR, "sk_buff length greater than agreed max_sdu, dropping...");
-    hrz_kfree_skb (skb);
-    return -EIO;
-  }
-  
-  if (!channel) {
-    PRINTD (DBG_ERR|DBG_TX, "attempt to transmit on zero (rx_)channel");
-    hrz_kfree_skb (skb);
-    return -EIO;
-  }
-  
-#if 0
-  {
-    // where would be a better place for this? housekeeping?
-    u16 status;
-    pci_read_config_word (dev->pci_dev, PCI_STATUS, &status);
-    if (status & PCI_STATUS_REC_MASTER_ABORT) {
-      PRINTD (DBG_BUS|DBG_ERR, "Clearing PCI Master Abort (and cleaning up)");
-      status &= ~PCI_STATUS_REC_MASTER_ABORT;
-      pci_write_config_word (dev->pci_dev, PCI_STATUS, status);
-      if (test_bit (tx_busy, &dev->flags)) {
-	hrz_kfree_skb (dev->tx_skb);
-	tx_release (dev);
-      }
-    }
-  }
-#endif
-  
-#ifdef DEBUG_HORIZON
-  /* wey-hey! */
-  if (channel == 1023) {
-    unsigned int i;
-    unsigned short d = 0;
-    char * s = skb->data;
-    if (*s++ == 'D') {
-	for (i = 0; i < 4; ++i)
-		d = (d << 4) | hex_to_bin(*s++);
-      PRINTK (KERN_INFO, "debug bitmap is now %hx", debug = d);
-    }
-  }
-#endif
-  
-  // wait until TX is free and grab lock
-  if (tx_hold (dev)) {
-    hrz_kfree_skb (skb);
-    return -ERESTARTSYS;
-  }
- 
-  // Wait for enough space to be available in transmit buffer memory.
-  
-  // should be number of cells needed + 2 (according to hardware docs)
-  // = ((framelen+8)+47) / 48 + 2
-  // = (framelen+7) / 48 + 3, hmm... faster to put addition inside XXX
-  buffers_required = (skb->len+(ATM_AAL5_TRAILER-1)) / ATM_CELL_PAYLOAD + 3;
-  
-  // replace with timer and sleep, add dev->tx_buffers_queue (max 1 entry)
-  spin_count = 0;
-  while ((free_buffers = rd_regw (dev, TX_FREE_BUFFER_COUNT_OFF)) < buffers_required) {
-    PRINTD (DBG_TX, "waiting for free TX buffers, got %d of %d",
-	    free_buffers, buffers_required);
-    // what is the appropriate delay? implement a timeout? (depending on line speed?)
-    // mdelay (1);
-    // what happens if we kill (current_pid, SIGKILL) ?
-    schedule();
-    if (++spin_count > 1000) {
-      PRINTD (DBG_TX|DBG_ERR, "spun out waiting for tx buffers, got %d of %d",
-	      free_buffers, buffers_required);
-      tx_release (dev);
-      hrz_kfree_skb (skb);
-      return -ERESTARTSYS;
-    }
-  }
-  
-  // Select a channel to transmit the frame on.
-  if (channel == dev->last_vc) {
-    PRINTD (DBG_TX, "last vc hack: hit");
-    tx_channel = dev->tx_last;
-  } else {
-    PRINTD (DBG_TX, "last vc hack: miss");
-    // Are we currently transmitting this VC on one of the channels?
-    for (tx_channel = 0; tx_channel < TX_CHANS; ++tx_channel)
-      if (dev->tx_channel_record[tx_channel] == channel) {
-	PRINTD (DBG_TX, "vc already on channel: hit");
-	break;
-      }
-    if (tx_channel == TX_CHANS) { 
-      PRINTD (DBG_TX, "vc already on channel: miss");
-      // Find and set up an idle channel.
-      tx_channel = setup_idle_tx_channel (dev, vcc);
-      if (tx_channel < 0) {
-	PRINTD (DBG_TX|DBG_ERR, "failed to get channel");
-	tx_release (dev);
-	return tx_channel;
-      }
-    }
-    
-    PRINTD (DBG_TX, "got channel");
-    SELECT_TX_CHANNEL(dev, tx_channel);
-    
-    dev->last_vc = channel;
-    dev->tx_last = tx_channel;
-  }
-  
-  PRINTD (DBG_TX, "using channel %u", tx_channel);
-  
-  YELLOW_LED_OFF(dev);
-  
-  // TX start transfer
-  
-  {
-    unsigned int tx_len = skb->len;
-    unsigned int tx_iovcnt = skb_shinfo(skb)->nr_frags;
-    // remember this so we can free it later
-    dev->tx_skb = skb;
-    
-    if (tx_iovcnt) {
-      // scatter gather transfer
-      dev->tx_regions = tx_iovcnt;
-      dev->tx_iovec = NULL;		/* @@@ needs rewritten */
-      dev->tx_bytes = 0;
-      PRINTD (DBG_TX|DBG_BUS, "TX start scatter-gather transfer (iovec %p, len %d)",
-	      skb->data, tx_len);
-      tx_release (dev);
-      hrz_kfree_skb (skb);
-      return -EIO;
-    } else {
-      // simple transfer
-      dev->tx_regions = 0;
-      dev->tx_iovec = NULL;
-      dev->tx_bytes = tx_len;
-      dev->tx_addr = skb->data;
-      PRINTD (DBG_TX|DBG_BUS, "TX start simple transfer (addr %p, len %d)",
-	      skb->data, tx_len);
-    }
-    
-    // and do the business
-    tx_schedule (dev, 0);
-    
-  }
-  
-  return 0;
-}
-
-/********** reset a card **********/
-
-static void hrz_reset (const hrz_dev * dev) {
-  u32 control_0_reg = rd_regl (dev, CONTROL_0_REG);
-  
-  // why not set RESET_HORIZON to one and wait for the card to
-  // reassert that bit as zero? Like so:
-  control_0_reg = control_0_reg & RESET_HORIZON;
-  wr_regl (dev, CONTROL_0_REG, control_0_reg);
-  while (control_0_reg & RESET_HORIZON)
-    control_0_reg = rd_regl (dev, CONTROL_0_REG);
-  
-  // old reset code retained:
-  wr_regl (dev, CONTROL_0_REG, control_0_reg |
-	   RESET_ATM | RESET_RX | RESET_TX | RESET_HOST);
-  // just guessing here
-  udelay (1000);
-  
-  wr_regl (dev, CONTROL_0_REG, control_0_reg);
-}
-
-/********** read the burnt in address **********/
-
-static void WRITE_IT_WAIT (const hrz_dev *dev, u32 ctrl)
-{
-	wr_regl (dev, CONTROL_0_REG, ctrl);
-	udelay (5);
-}
-  
-static void CLOCK_IT (const hrz_dev *dev, u32 ctrl)
-{
-	// DI must be valid around rising SK edge
-	WRITE_IT_WAIT(dev, ctrl & ~SEEPROM_SK);
-	WRITE_IT_WAIT(dev, ctrl | SEEPROM_SK);
-}
-
-static u16 read_bia(const hrz_dev *dev, u16 addr)
-{
-  u32 ctrl = rd_regl (dev, CONTROL_0_REG);
-  
-  const unsigned int addr_bits = 6;
-  const unsigned int data_bits = 16;
-  
-  unsigned int i;
-  
-  u16 res;
-  
-  ctrl &= ~(SEEPROM_CS | SEEPROM_SK | SEEPROM_DI);
-  WRITE_IT_WAIT(dev, ctrl);
-  
-  // wake Serial EEPROM and send 110 (READ) command
-  ctrl |=  (SEEPROM_CS | SEEPROM_DI);
-  CLOCK_IT(dev, ctrl);
-  
-  ctrl |= SEEPROM_DI;
-  CLOCK_IT(dev, ctrl);
-  
-  ctrl &= ~SEEPROM_DI;
-  CLOCK_IT(dev, ctrl);
-  
-  for (i=0; i<addr_bits; i++) {
-    if (addr & (1 << (addr_bits-1)))
-      ctrl |= SEEPROM_DI;
-    else
-      ctrl &= ~SEEPROM_DI;
-    
-    CLOCK_IT(dev, ctrl);
-    
-    addr = addr << 1;
-  }
-  
-  // we could check that we have DO = 0 here
-  ctrl &= ~SEEPROM_DI;
-  
-  res = 0;
-  for (i=0;i<data_bits;i++) {
-    res = res >> 1;
-    
-    CLOCK_IT(dev, ctrl);
-    
-    if (rd_regl (dev, CONTROL_0_REG) & SEEPROM_DO)
-      res |= (1 << (data_bits-1));
-  }
-  
-  ctrl &= ~(SEEPROM_SK | SEEPROM_CS);
-  WRITE_IT_WAIT(dev, ctrl);
-  
-  return res;
-}
-
-/********** initialise a card **********/
-
-static int hrz_init(hrz_dev *dev)
-{
-  int onefivefive;
-  
-  u16 chan;
-  
-  int buff_count;
-  
-  HDW * mem;
-  
-  cell_buf * tx_desc;
-  cell_buf * rx_desc;
-  
-  u32 ctrl;
-  
-  ctrl = rd_regl (dev, CONTROL_0_REG);
-  PRINTD (DBG_INFO, "ctrl0reg is %#x", ctrl);
-  onefivefive = ctrl & ATM_LAYER_STATUS;
-  
-  if (onefivefive)
-    printk (DEV_LABEL ": Horizon Ultra (at 155.52 MBps)");
-  else
-    printk (DEV_LABEL ": Horizon (at 25 MBps)");
-  
-  printk (":");
-  // Reset the card to get everything in a known state
-  
-  printk (" reset");
-  hrz_reset (dev);
-  
-  // Clear all the buffer memory
-  
-  printk (" clearing memory");
-  
-  for (mem = (HDW *) memmap; mem < (HDW *) (memmap + 1); ++mem)
-    wr_mem (dev, mem, 0);
-  
-  printk (" tx channels");
-  
-  // All transmit eight channels are set up as AAL5 ABR channels with
-  // a 16us cell spacing. Why?
-  
-  // Channel 0 gets the free buffer at 100h, channel 1 gets the free
-  // buffer at 110h etc.
-  
-  for (chan = 0; chan < TX_CHANS; ++chan) {
-    tx_ch_desc * tx_desc = &memmap->tx_descs[chan];
-    cell_buf * buf = &memmap->inittxbufs[chan];
-    
-    // initialise the read and write buffer pointers
-    wr_mem (dev, &tx_desc->rd_buf_type, BUF_PTR(buf));
-    wr_mem (dev, &tx_desc->wr_buf_type, BUF_PTR(buf));
-    
-    // set the status of the initial buffers to empty
-    wr_mem (dev, &buf->next, BUFF_STATUS_EMPTY);
-  }
-  
-  // Use space bufn3 at the moment for tx buffers
-  
-  printk (" tx buffers");
-  
-  tx_desc = memmap->bufn3;
-  
-  wr_mem (dev, &memmap->txfreebufstart.next, BUF_PTR(tx_desc) | BUFF_STATUS_EMPTY);
-  
-  for (buff_count = 0; buff_count < BUFN3_SIZE-1; buff_count++) {
-    wr_mem (dev, &tx_desc->next, BUF_PTR(tx_desc+1) | BUFF_STATUS_EMPTY);
-    tx_desc++;
-  }
-  
-  wr_mem (dev, &tx_desc->next, BUF_PTR(&memmap->txfreebufend) | BUFF_STATUS_EMPTY);
-  
-  // Initialise the transmit free buffer count
-  wr_regw (dev, TX_FREE_BUFFER_COUNT_OFF, BUFN3_SIZE);
-  
-  printk (" rx channels");
-  
-  // Initialise all of the receive channels to be AAL5 disabled with
-  // an interrupt threshold of 0
-  
-  for (chan = 0; chan < RX_CHANS; ++chan) {
-    rx_ch_desc * rx_desc = &memmap->rx_descs[chan];
-    
-    wr_mem (dev, &rx_desc->wr_buf_type, CHANNEL_TYPE_AAL5 | RX_CHANNEL_DISABLED);
-  }
-  
-  printk (" rx buffers");
-  
-  // Use space bufn4 at the moment for rx buffers
-  
-  rx_desc = memmap->bufn4;
-  
-  wr_mem (dev, &memmap->rxfreebufstart.next, BUF_PTR(rx_desc) | BUFF_STATUS_EMPTY);
-  
-  for (buff_count = 0; buff_count < BUFN4_SIZE-1; buff_count++) {
-    wr_mem (dev, &rx_desc->next, BUF_PTR(rx_desc+1) | BUFF_STATUS_EMPTY);
-    
-    rx_desc++;
-  }
-  
-  wr_mem (dev, &rx_desc->next, BUF_PTR(&memmap->rxfreebufend) | BUFF_STATUS_EMPTY);
-  
-  // Initialise the receive free buffer count
-  wr_regw (dev, RX_FREE_BUFFER_COUNT_OFF, BUFN4_SIZE);
-  
-  // Initialize Horizons registers
-  
-  // TX config
-  wr_regw (dev, TX_CONFIG_OFF,
-	   ABR_ROUND_ROBIN | TX_NORMAL_OPERATION | DRVR_DRVRBAR_ENABLE);
-  
-  // RX config. Use 10-x VC bits, x VP bits, non user cells in channel 0.
-  wr_regw (dev, RX_CONFIG_OFF,
-	   DISCARD_UNUSED_VPI_VCI_BITS_SET | NON_USER_CELLS_IN_ONE_CHANNEL | vpi_bits);
-  
-  // RX line config
-  wr_regw (dev, RX_LINE_CONFIG_OFF,
-	   LOCK_DETECT_ENABLE | FREQUENCY_DETECT_ENABLE | GXTALOUT_SELECT_DIV4);
-  
-  // Set the max AAL5 cell count to be just enough to contain the
-  // largest AAL5 frame that the user wants to receive
-  wr_regw (dev, MAX_AAL5_CELL_COUNT_OFF,
-	   DIV_ROUND_UP(max_rx_size + ATM_AAL5_TRAILER, ATM_CELL_PAYLOAD));
-  
-  // Enable receive
-  wr_regw (dev, RX_CONFIG_OFF, rd_regw (dev, RX_CONFIG_OFF) | RX_ENABLE);
-  
-  printk (" control");
-  
-  // Drive the OE of the LEDs then turn the green LED on
-  ctrl |= GREEN_LED_OE | YELLOW_LED_OE | GREEN_LED | YELLOW_LED;
-  wr_regl (dev, CONTROL_0_REG, ctrl);
-  
-  // Test for a 155-capable card
-  
-  if (onefivefive) {
-    // Select 155 mode... make this a choice (or: how do we detect
-    // external line speed and switch?)
-    ctrl |= ATM_LAYER_SELECT;
-    wr_regl (dev, CONTROL_0_REG, ctrl);
-    
-    // test SUNI-lite vs SAMBA
-    
-    // Register 0x00 in the SUNI will have some of bits 3-7 set, and
-    // they will always be zero for the SAMBA.  Ha!  Bloody hardware
-    // engineers.  It'll never work.
-    
-    if (rd_framer (dev, 0) & 0x00f0) {
-      // SUNI
-      printk (" SUNI");
-      
-      // Reset, just in case
-      wr_framer (dev, 0x00, 0x0080);
-      wr_framer (dev, 0x00, 0x0000);
-      
-      // Configure transmit FIFO
-      wr_framer (dev, 0x63, rd_framer (dev, 0x63) | 0x0002);
-      
-      // Set line timed mode
-      wr_framer (dev, 0x05, rd_framer (dev, 0x05) | 0x0001);
-    } else {
-      // SAMBA
-      printk (" SAMBA");
-      
-      // Reset, just in case
-      wr_framer (dev, 0, rd_framer (dev, 0) | 0x0001);
-      wr_framer (dev, 0, rd_framer (dev, 0) &~ 0x0001);
-      
-      // Turn off diagnostic loopback and enable line-timed mode
-      wr_framer (dev, 0, 0x0002);
-      
-      // Turn on transmit outputs
-      wr_framer (dev, 2, 0x0B80);
-    }
-  } else {
-    // Select 25 mode
-    ctrl &= ~ATM_LAYER_SELECT;
-    
-    // Madge B154 setup
-    // none required?
-  }
-  
-  printk (" LEDs");
-  
-  GREEN_LED_ON(dev);
-  YELLOW_LED_ON(dev);
-  
-  printk (" ESI=");
-  
-  {
-    u16 b = 0;
-    int i;
-    u8 * esi = dev->atm_dev->esi;
-    
-    // in the card I have, EEPROM
-    // addresses 0, 1, 2 contain 0
-    // addresess 5, 6 etc. contain ffff
-    // NB: Madge prefix is 00 00 f6 (which is 00 00 6f in Ethernet bit order)
-    // the read_bia routine gets the BIA in Ethernet bit order
-    
-    for (i=0; i < ESI_LEN; ++i) {
-      if (i % 2 == 0)
-	b = read_bia (dev, i/2 + 2);
-      else
-	b = b >> 8;
-      esi[i] = b & 0xFF;
-      printk ("%02x", esi[i]);
-    }
-  }
-  
-  // Enable RX_Q and ?X_COMPLETE interrupts only
-  wr_regl (dev, INT_ENABLE_REG_OFF, INTERESTING_INTERRUPTS);
-  printk (" IRQ on");
-  
-  printk (".\n");
-  
-  return onefivefive;
-}
-
-/********** check max_sdu **********/
-
-static int check_max_sdu (hrz_aal aal, struct atm_trafprm * tp, unsigned int max_frame_size) {
-  PRINTD (DBG_FLOW|DBG_QOS, "check_max_sdu");
-  
-  switch (aal) {
-    case aal0:
-      if (!(tp->max_sdu)) {
-	PRINTD (DBG_QOS, "defaulting max_sdu");
-	tp->max_sdu = ATM_AAL0_SDU;
-      } else if (tp->max_sdu != ATM_AAL0_SDU) {
-	PRINTD (DBG_QOS|DBG_ERR, "rejecting max_sdu");
-	return -EINVAL;
-      }
-      break;
-    case aal34:
-      if (tp->max_sdu == 0 || tp->max_sdu > ATM_MAX_AAL34_PDU) {
-	PRINTD (DBG_QOS, "%sing max_sdu", tp->max_sdu ? "capp" : "default");
-	tp->max_sdu = ATM_MAX_AAL34_PDU;
-      }
-      break;
-    case aal5:
-      if (tp->max_sdu == 0 || tp->max_sdu > max_frame_size) {
-	PRINTD (DBG_QOS, "%sing max_sdu", tp->max_sdu ? "capp" : "default");
-	tp->max_sdu = max_frame_size;
-      }
-      break;
-  }
-  return 0;
-}
-
-/********** check pcr **********/
-
-// something like this should be part of ATM Linux
-static int atm_pcr_check (struct atm_trafprm * tp, unsigned int pcr) {
-  // we are assuming non-UBR, and non-special values of pcr
-  if (tp->min_pcr == ATM_MAX_PCR)
-    PRINTD (DBG_QOS, "luser gave min_pcr = ATM_MAX_PCR");
-  else if (tp->min_pcr < 0)
-    PRINTD (DBG_QOS, "luser gave negative min_pcr");
-  else if (tp->min_pcr && tp->min_pcr > pcr)
-    PRINTD (DBG_QOS, "pcr less than min_pcr");
-  else
-    // !! max_pcr = UNSPEC (0) is equivalent to max_pcr = MAX (-1)
-    // easier to #define ATM_MAX_PCR 0 and have all rates unsigned?
-    // [this would get rid of next two conditionals]
-    if ((0) && tp->max_pcr == ATM_MAX_PCR)
-      PRINTD (DBG_QOS, "luser gave max_pcr = ATM_MAX_PCR");
-    else if ((tp->max_pcr != ATM_MAX_PCR) && tp->max_pcr < 0)
-      PRINTD (DBG_QOS, "luser gave negative max_pcr");
-    else if (tp->max_pcr && tp->max_pcr != ATM_MAX_PCR && tp->max_pcr < pcr)
-      PRINTD (DBG_QOS, "pcr greater than max_pcr");
-    else {
-      // each limit unspecified or not violated
-      PRINTD (DBG_QOS, "xBR(pcr) OK");
-      return 0;
-    }
-  PRINTD (DBG_QOS, "pcr=%u, tp: min_pcr=%d, pcr=%d, max_pcr=%d",
-	  pcr, tp->min_pcr, tp->pcr, tp->max_pcr);
-  return -EINVAL;
-}
-
-/********** open VC **********/
-
-static int hrz_open (struct atm_vcc *atm_vcc)
-{
-  int error;
-  u16 channel;
-  
-  struct atm_qos * qos;
-  struct atm_trafprm * txtp;
-  struct atm_trafprm * rxtp;
-  
-  hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
-  hrz_vcc vcc;
-  hrz_vcc * vccp; // allocated late
-  short vpi = atm_vcc->vpi;
-  int vci = atm_vcc->vci;
-  PRINTD (DBG_FLOW|DBG_VCC, "hrz_open %x %x", vpi, vci);
-  
-#ifdef ATM_VPI_UNSPEC
-  // UNSPEC is deprecated, remove this code eventually
-  if (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC) {
-    PRINTK (KERN_WARNING, "rejecting open with unspecified VPI/VCI (deprecated)");
-    return -EINVAL;
-  }
-#endif
-  
-  error = vpivci_to_channel (&channel, vpi, vci);
-  if (error) {
-    PRINTD (DBG_WARN|DBG_VCC, "VPI/VCI out of range: %hd/%d", vpi, vci);
-    return error;
-  }
-  
-  vcc.channel = channel;
-  // max speed for the moment
-  vcc.tx_rate = 0x0;
-  
-  qos = &atm_vcc->qos;
-  
-  // check AAL and remember it
-  switch (qos->aal) {
-    case ATM_AAL0:
-      // we would if it were 48 bytes and not 52!
-      PRINTD (DBG_QOS|DBG_VCC, "AAL0");
-      vcc.aal = aal0;
-      break;
-    case ATM_AAL34:
-      // we would if I knew how do the SAR!
-      PRINTD (DBG_QOS|DBG_VCC, "AAL3/4");
-      vcc.aal = aal34;
-      break;
-    case ATM_AAL5:
-      PRINTD (DBG_QOS|DBG_VCC, "AAL5");
-      vcc.aal = aal5;
-      break;
-    default:
-      PRINTD (DBG_QOS|DBG_VCC, "Bad AAL!");
-      return -EINVAL;
-  }
-  
-  // TX traffic parameters
-  
-  // there are two, interrelated problems here: 1. the reservation of
-  // PCR is not a binary choice, we are given bounds and/or a
-  // desirable value; 2. the device is only capable of certain values,
-  // most of which are not integers. It is almost certainly acceptable
-  // to be off by a maximum of 1 to 10 cps.
-  
-  // Pragmatic choice: always store an integral PCR as that which has
-  // been allocated, even if we allocate a little (or a lot) less,
-  // after rounding. The actual allocation depends on what we can
-  // manage with our rate selection algorithm. The rate selection
-  // algorithm is given an integral PCR and a tolerance and told
-  // whether it should round the value up or down if the tolerance is
-  // exceeded; it returns: a) the actual rate selected (rounded up to
-  // the nearest integer), b) a bit pattern to feed to the timer
-  // register, and c) a failure value if no applicable rate exists.
-  
-  // Part of the job is done by atm_pcr_goal which gives us a PCR
-  // specification which says: EITHER grab the maximum available PCR
-  // (and perhaps a lower bound which we musn't pass), OR grab this
-  // amount, rounding down if you have to (and perhaps a lower bound
-  // which we musn't pass) OR grab this amount, rounding up if you
-  // have to (and perhaps an upper bound which we musn't pass). If any
-  // bounds ARE passed we fail. Note that rounding is only rounding to
-  // match device limitations, we do not round down to satisfy
-  // bandwidth availability even if this would not violate any given
-  // lower bound.
-  
-  // Note: telephony = 64kb/s = 48 byte cell payload @ 500/3 cells/s
-  // (say) so this is not even a binary fixpoint cell rate (but this
-  // device can do it). To avoid this sort of hassle we use a
-  // tolerance parameter (currently fixed at 10 cps).
-  
-  PRINTD (DBG_QOS, "TX:");
-  
-  txtp = &qos->txtp;
-  
-  // set up defaults for no traffic
-  vcc.tx_rate = 0;
-  // who knows what would actually happen if you try and send on this?
-  vcc.tx_xbr_bits = IDLE_RATE_TYPE;
-  vcc.tx_pcr_bits = CLOCK_DISABLE;
-#if 0
-  vcc.tx_scr_bits = CLOCK_DISABLE;
-  vcc.tx_bucket_bits = 0;
-#endif
-  
-  if (txtp->traffic_class != ATM_NONE) {
-    error = check_max_sdu (vcc.aal, txtp, max_tx_size);
-    if (error) {
-      PRINTD (DBG_QOS, "TX max_sdu check failed");
-      return error;
-    }
-    
-    switch (txtp->traffic_class) {
-      case ATM_UBR: {
-	// we take "the PCR" as a rate-cap
-	// not reserved
-	vcc.tx_rate = 0;
-	make_rate (dev, 1<<30, round_nearest, &vcc.tx_pcr_bits, NULL);
-	vcc.tx_xbr_bits = ABR_RATE_TYPE;
-	break;
-      }
-#if 0
-      case ATM_ABR: {
-	// reserve min, allow up to max
-	vcc.tx_rate = 0; // ?
-	make_rate (dev, 1<<30, round_nearest, &vcc.tx_pcr_bits, 0);
-	vcc.tx_xbr_bits = ABR_RATE_TYPE;
-	break;
-      }
-#endif
-      case ATM_CBR: {
-	int pcr = atm_pcr_goal (txtp);
-	rounding r;
-	if (!pcr) {
-	  // down vs. up, remaining bandwidth vs. unlimited bandwidth!!
-	  // should really have: once someone gets unlimited bandwidth
-	  // that no more non-UBR channels can be opened until the
-	  // unlimited one closes?? For the moment, round_down means
-	  // greedy people actually get something and not nothing
-	  r = round_down;
-	  // slight race (no locking) here so we may get -EAGAIN
-	  // later; the greedy bastards would deserve it :)
-	  PRINTD (DBG_QOS, "snatching all remaining TX bandwidth");
-	  pcr = dev->tx_avail;
-	} else if (pcr < 0) {
-	  r = round_down;
-	  pcr = -pcr;
-	} else {
-	  r = round_up;
-	}
-	error = make_rate_with_tolerance (dev, pcr, r, 10,
-					  &vcc.tx_pcr_bits, &vcc.tx_rate);
-	if (error) {
-	  PRINTD (DBG_QOS, "could not make rate from TX PCR");
-	  return error;
-	}
-	// not really clear what further checking is needed
-	error = atm_pcr_check (txtp, vcc.tx_rate);
-	if (error) {
-	  PRINTD (DBG_QOS, "TX PCR failed consistency check");
-	  return error;
-	}
-	vcc.tx_xbr_bits = CBR_RATE_TYPE;
-	break;
-      }
-#if 0
-      case ATM_VBR: {
-	int pcr = atm_pcr_goal (txtp);
-	// int scr = atm_scr_goal (txtp);
-	int scr = pcr/2; // just for fun
-	unsigned int mbs = 60; // just for fun
-	rounding pr;
-	rounding sr;
-	unsigned int bucket;
-	if (!pcr) {
-	  pr = round_nearest;
-	  pcr = 1<<30;
-	} else if (pcr < 0) {
-	  pr = round_down;
-	  pcr = -pcr;
-	} else {
-	  pr = round_up;
-	}
-	error = make_rate_with_tolerance (dev, pcr, pr, 10,
-					  &vcc.tx_pcr_bits, 0);
-	if (!scr) {
-	  // see comments for PCR with CBR above
-	  sr = round_down;
-	  // slight race (no locking) here so we may get -EAGAIN
-	  // later; the greedy bastards would deserve it :)
-	  PRINTD (DBG_QOS, "snatching all remaining TX bandwidth");
-	  scr = dev->tx_avail;
-	} else if (scr < 0) {
-	  sr = round_down;
-	  scr = -scr;
-	} else {
-	  sr = round_up;
-	}
-	error = make_rate_with_tolerance (dev, scr, sr, 10,
-					  &vcc.tx_scr_bits, &vcc.tx_rate);
-	if (error) {
-	  PRINTD (DBG_QOS, "could not make rate from TX SCR");
-	  return error;
-	}
-	// not really clear what further checking is needed
-	// error = atm_scr_check (txtp, vcc.tx_rate);
-	if (error) {
-	  PRINTD (DBG_QOS, "TX SCR failed consistency check");
-	  return error;
-	}
-	// bucket calculations (from a piece of paper...) cell bucket
-	// capacity must be largest integer smaller than m(p-s)/p + 1
-	// where m = max burst size, p = pcr, s = scr
-	bucket = mbs*(pcr-scr)/pcr;
-	if (bucket*pcr != mbs*(pcr-scr))
-	  bucket += 1;
-	if (bucket > BUCKET_MAX_SIZE) {
-	  PRINTD (DBG_QOS, "shrinking bucket from %u to %u",
-		  bucket, BUCKET_MAX_SIZE);
-	  bucket = BUCKET_MAX_SIZE;
-	}
-	vcc.tx_xbr_bits = VBR_RATE_TYPE;
-	vcc.tx_bucket_bits = bucket;
-	break;
-      }
-#endif
-      default: {
-	PRINTD (DBG_QOS, "unsupported TX traffic class");
-	return -EINVAL;
-      }
-    }
-  }
-  
-  // RX traffic parameters
-  
-  PRINTD (DBG_QOS, "RX:");
-  
-  rxtp = &qos->rxtp;
-  
-  // set up defaults for no traffic
-  vcc.rx_rate = 0;
-  
-  if (rxtp->traffic_class != ATM_NONE) {
-    error = check_max_sdu (vcc.aal, rxtp, max_rx_size);
-    if (error) {
-      PRINTD (DBG_QOS, "RX max_sdu check failed");
-      return error;
-    }
-    switch (rxtp->traffic_class) {
-      case ATM_UBR: {
-	// not reserved
-	break;
-      }
-#if 0
-      case ATM_ABR: {
-	// reserve min
-	vcc.rx_rate = 0; // ?
-	break;
-      }
-#endif
-      case ATM_CBR: {
-	int pcr = atm_pcr_goal (rxtp);
-	if (!pcr) {
-	  // slight race (no locking) here so we may get -EAGAIN
-	  // later; the greedy bastards would deserve it :)
-	  PRINTD (DBG_QOS, "snatching all remaining RX bandwidth");
-	  pcr = dev->rx_avail;
-	} else if (pcr < 0) {
-	  pcr = -pcr;
-	}
-	vcc.rx_rate = pcr;
-	// not really clear what further checking is needed
-	error = atm_pcr_check (rxtp, vcc.rx_rate);
-	if (error) {
-	  PRINTD (DBG_QOS, "RX PCR failed consistency check");
-	  return error;
-	}
-	break;
-      }
-#if 0
-      case ATM_VBR: {
-	// int scr = atm_scr_goal (rxtp);
-	int scr = 1<<16; // just for fun
-	if (!scr) {
-	  // slight race (no locking) here so we may get -EAGAIN
-	  // later; the greedy bastards would deserve it :)
-	  PRINTD (DBG_QOS, "snatching all remaining RX bandwidth");
-	  scr = dev->rx_avail;
-	} else if (scr < 0) {
-	  scr = -scr;
-	}
-	vcc.rx_rate = scr;
-	// not really clear what further checking is needed
-	// error = atm_scr_check (rxtp, vcc.rx_rate);
-	if (error) {
-	  PRINTD (DBG_QOS, "RX SCR failed consistency check");
-	  return error;
-	}
-	break;
-      }
-#endif
-      default: {
-	PRINTD (DBG_QOS, "unsupported RX traffic class");
-	return -EINVAL;
-      }
-    }
-  }
-  
-  
-  // late abort useful for diagnostics
-  if (vcc.aal != aal5) {
-    PRINTD (DBG_QOS, "AAL not supported");
-    return -EINVAL;
-  }
-  
-  // get space for our vcc stuff and copy parameters into it
-  vccp = kmalloc (sizeof(hrz_vcc), GFP_KERNEL);
-  if (!vccp) {
-    PRINTK (KERN_ERR, "out of memory!");
-    return -ENOMEM;
-  }
-  *vccp = vcc;
-  
-  // clear error and grab cell rate resource lock
-  error = 0;
-  spin_lock (&dev->rate_lock);
-  
-  if (vcc.tx_rate > dev->tx_avail) {
-    PRINTD (DBG_QOS, "not enough TX PCR left");
-    error = -EAGAIN;
-  }
-  
-  if (vcc.rx_rate > dev->rx_avail) {
-    PRINTD (DBG_QOS, "not enough RX PCR left");
-    error = -EAGAIN;
-  }
-  
-  if (!error) {
-    // really consume cell rates
-    dev->tx_avail -= vcc.tx_rate;
-    dev->rx_avail -= vcc.rx_rate;
-    PRINTD (DBG_QOS|DBG_VCC, "reserving %u TX PCR and %u RX PCR",
-	    vcc.tx_rate, vcc.rx_rate);
-  }
-  
-  // release lock and exit on error
-  spin_unlock (&dev->rate_lock);
-  if (error) {
-    PRINTD (DBG_QOS|DBG_VCC, "insufficient cell rate resources");
-    kfree (vccp);
-    return error;
-  }
-  
-  // this is "immediately before allocating the connection identifier
-  // in hardware" - so long as the next call does not fail :)
-  set_bit(ATM_VF_ADDR,&atm_vcc->flags);
-  
-  // any errors here are very serious and should never occur
-  
-  if (rxtp->traffic_class != ATM_NONE) {
-    if (dev->rxer[channel]) {
-      PRINTD (DBG_ERR|DBG_VCC, "VC already open for RX");
-      error = -EBUSY;
-    }
-    if (!error)
-      error = hrz_open_rx (dev, channel);
-    if (error) {
-      kfree (vccp);
-      return error;
-    }
-    // this link allows RX frames through
-    dev->rxer[channel] = atm_vcc;
-  }
-  
-  // success, set elements of atm_vcc
-  atm_vcc->dev_data = (void *) vccp;
-  
-  // indicate readiness
-  set_bit(ATM_VF_READY,&atm_vcc->flags);
-  
-  return 0;
-}
-
-/********** close VC **********/
-
-static void hrz_close (struct atm_vcc * atm_vcc) {
-  hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
-  hrz_vcc * vcc = HRZ_VCC(atm_vcc);
-  u16 channel = vcc->channel;
-  PRINTD (DBG_VCC|DBG_FLOW, "hrz_close");
-  
-  // indicate unreadiness
-  clear_bit(ATM_VF_READY,&atm_vcc->flags);
-
-  if (atm_vcc->qos.txtp.traffic_class != ATM_NONE) {
-    unsigned int i;
-    
-    // let any TX on this channel that has started complete
-    // no restart, just keep trying
-    while (tx_hold (dev))
-      ;
-    // remove record of any tx_channel having been setup for this channel
-    for (i = 0; i < TX_CHANS; ++i)
-      if (dev->tx_channel_record[i] == channel) {
-	dev->tx_channel_record[i] = -1;
-	break;
-      }
-    if (dev->last_vc == channel)
-      dev->tx_last = -1;
-    tx_release (dev);
-  }
-
-  if (atm_vcc->qos.rxtp.traffic_class != ATM_NONE) {
-    // disable RXing - it tries quite hard
-    hrz_close_rx (dev, channel);
-    // forget the vcc - no more skbs will be pushed
-    if (atm_vcc != dev->rxer[channel])
-      PRINTK (KERN_ERR, "%s atm_vcc=%p rxer[channel]=%p",
-	      "arghhh! we're going to die!",
-	      atm_vcc, dev->rxer[channel]);
-    dev->rxer[channel] = NULL;
-  }
-  
-  // atomically release our rate reservation
-  spin_lock (&dev->rate_lock);
-  PRINTD (DBG_QOS|DBG_VCC, "releasing %u TX PCR and %u RX PCR",
-	  vcc->tx_rate, vcc->rx_rate);
-  dev->tx_avail += vcc->tx_rate;
-  dev->rx_avail += vcc->rx_rate;
-  spin_unlock (&dev->rate_lock);
-  
-  // free our structure
-  kfree (vcc);
-  // say the VPI/VCI is free again
-  clear_bit(ATM_VF_ADDR,&atm_vcc->flags);
-}
-
-#if 0
-static int hrz_getsockopt (struct atm_vcc * atm_vcc, int level, int optname,
-			   void *optval, int optlen) {
-  hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
-  PRINTD (DBG_FLOW|DBG_VCC, "hrz_getsockopt");
-  switch (level) {
-    case SOL_SOCKET:
-      switch (optname) {
-//	case SO_BCTXOPT:
-//	  break;
-//	case SO_BCRXOPT:
-//	  break;
-	default:
-	  return -ENOPROTOOPT;
-      };
-      break;
-  }
-  return -EINVAL;
-}
-
-static int hrz_setsockopt (struct atm_vcc * atm_vcc, int level, int optname,
-			   void *optval, unsigned int optlen) {
-  hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
-  PRINTD (DBG_FLOW|DBG_VCC, "hrz_setsockopt");
-  switch (level) {
-    case SOL_SOCKET:
-      switch (optname) {
-//	case SO_BCTXOPT:
-//	  break;
-//	case SO_BCRXOPT:
-//	  break;
-	default:
-	  return -ENOPROTOOPT;
-      };
-      break;
-  }
-  return -EINVAL;
-}
-#endif
-
-#if 0
-static int hrz_ioctl (struct atm_dev * atm_dev, unsigned int cmd, void *arg) {
-  hrz_dev * dev = HRZ_DEV(atm_dev);
-  PRINTD (DBG_FLOW, "hrz_ioctl");
-  return -1;
-}
-
-unsigned char hrz_phy_get (struct atm_dev * atm_dev, unsigned long addr) {
-  hrz_dev * dev = HRZ_DEV(atm_dev);
-  PRINTD (DBG_FLOW, "hrz_phy_get");
-  return 0;
-}
-
-static void hrz_phy_put (struct atm_dev * atm_dev, unsigned char value,
-			 unsigned long addr) {
-  hrz_dev * dev = HRZ_DEV(atm_dev);
-  PRINTD (DBG_FLOW, "hrz_phy_put");
-}
-
-static int hrz_change_qos (struct atm_vcc * atm_vcc, struct atm_qos *qos, int flgs) {
-  hrz_dev * dev = HRZ_DEV(vcc->dev);
-  PRINTD (DBG_FLOW, "hrz_change_qos");
-  return -1;
-}
-#endif
-
-/********** proc file contents **********/
-
-static int hrz_proc_read (struct atm_dev * atm_dev, loff_t * pos, char * page) {
-  hrz_dev * dev = HRZ_DEV(atm_dev);
-  int left = *pos;
-  PRINTD (DBG_FLOW, "hrz_proc_read");
-  
-  /* more diagnostics here? */
-  
-#if 0
-  if (!left--) {
-    unsigned int count = sprintf (page, "vbr buckets:");
-    unsigned int i;
-    for (i = 0; i < TX_CHANS; ++i)
-      count += sprintf (page, " %u/%u",
-			query_tx_channel_config (dev, i, BUCKET_FULLNESS_ACCESS),
-			query_tx_channel_config (dev, i, BUCKET_CAPACITY_ACCESS));
-    count += sprintf (page+count, ".\n");
-    return count;
-  }
-#endif
-  
-  if (!left--)
-    return sprintf (page,
-		    "cells: TX %lu, RX %lu, HEC errors %lu, unassigned %lu.\n",
-		    dev->tx_cell_count, dev->rx_cell_count,
-		    dev->hec_error_count, dev->unassigned_cell_count);
-  
-  if (!left--)
-    return sprintf (page,
-		    "free cell buffers: TX %hu, RX %hu+%hu.\n",
-		    rd_regw (dev, TX_FREE_BUFFER_COUNT_OFF),
-		    rd_regw (dev, RX_FREE_BUFFER_COUNT_OFF),
-		    dev->noof_spare_buffers);
-  
-  if (!left--)
-    return sprintf (page,
-		    "cps remaining: TX %u, RX %u\n",
-		    dev->tx_avail, dev->rx_avail);
-  
-  return 0;
-}
-
-static const struct atmdev_ops hrz_ops = {
-  .open	= hrz_open,
-  .close	= hrz_close,
-  .send	= hrz_send,
-  .proc_read	= hrz_proc_read,
-  .owner	= THIS_MODULE,
-};
-
-static int hrz_probe(struct pci_dev *pci_dev,
-		     const struct pci_device_id *pci_ent)
-{
-	hrz_dev * dev;
-	int err = 0;
-
-	// adapter slot free, read resources from PCI configuration space
-	u32 iobase = pci_resource_start (pci_dev, 0);
-	u32 * membase = bus_to_virt (pci_resource_start (pci_dev, 1));
-	unsigned int irq;
-	unsigned char lat;
-
-	PRINTD (DBG_FLOW, "hrz_probe");
-
-	if (pci_enable_device(pci_dev))
-		return -EINVAL;
-
-	/* XXX DEV_LABEL is a guess */
-	if (!request_region(iobase, HRZ_IO_EXTENT, DEV_LABEL)) {
-		err = -EINVAL;
-		goto out_disable;
-	}
-
-	dev = kzalloc(sizeof(hrz_dev), GFP_KERNEL);
-	if (!dev) {
-		// perhaps we should be nice: deregister all adapters and abort?
-		PRINTD(DBG_ERR, "out of memory");
-		err = -ENOMEM;
-		goto out_release;
-	}
-
-	pci_set_drvdata(pci_dev, dev);
-
-	// grab IRQ and install handler - move this someplace more sensible
-	irq = pci_dev->irq;
-	if (request_irq(irq,
-			interrupt_handler,
-			IRQF_SHARED, /* irqflags guess */
-			DEV_LABEL, /* name guess */
-			dev)) {
-		PRINTD(DBG_WARN, "request IRQ failed!");
-		err = -EINVAL;
-		goto out_free;
-	}
-
-	PRINTD(DBG_INFO, "found Madge ATM adapter (hrz) at: IO %x, IRQ %u, MEM %p",
-	       iobase, irq, membase);
-
-	dev->atm_dev = atm_dev_register(DEV_LABEL, &pci_dev->dev, &hrz_ops, -1,
-					NULL);
-	if (!(dev->atm_dev)) {
-		PRINTD(DBG_ERR, "failed to register Madge ATM adapter");
-		err = -EINVAL;
-		goto out_free_irq;
-	}
-
-	PRINTD(DBG_INFO, "registered Madge ATM adapter (no. %d) (%p) at %p",
-	       dev->atm_dev->number, dev, dev->atm_dev);
-	dev->atm_dev->dev_data = (void *) dev;
-	dev->pci_dev = pci_dev; 
-
-	// enable bus master accesses
-	pci_set_master(pci_dev);
-
-	// frobnicate latency (upwards, usually)
-	pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &lat);
-	if (pci_lat) {
-		PRINTD(DBG_INFO, "%s PCI latency timer from %hu to %hu",
-		       "changing", lat, pci_lat);
-		pci_write_config_byte(pci_dev, PCI_LATENCY_TIMER, pci_lat);
-	} else if (lat < MIN_PCI_LATENCY) {
-		PRINTK(KERN_INFO, "%s PCI latency timer from %hu to %hu",
-		       "increasing", lat, MIN_PCI_LATENCY);
-		pci_write_config_byte(pci_dev, PCI_LATENCY_TIMER, MIN_PCI_LATENCY);
-	}
-
-	dev->iobase = iobase;
-	dev->irq = irq; 
-	dev->membase = membase; 
-
-	dev->rx_q_entry = dev->rx_q_reset = &memmap->rx_q_entries[0];
-	dev->rx_q_wrap  = &memmap->rx_q_entries[RX_CHANS-1];
-
-	// these next three are performance hacks
-	dev->last_vc = -1;
-	dev->tx_last = -1;
-	dev->tx_idle = 0;
-
-	dev->tx_regions = 0;
-	dev->tx_bytes = 0;
-	dev->tx_skb = NULL;
-	dev->tx_iovec = NULL;
-
-	dev->tx_cell_count = 0;
-	dev->rx_cell_count = 0;
-	dev->hec_error_count = 0;
-	dev->unassigned_cell_count = 0;
-
-	dev->noof_spare_buffers = 0;
-
-	{
-		unsigned int i;
-		for (i = 0; i < TX_CHANS; ++i)
-			dev->tx_channel_record[i] = -1;
-	}
-
-	dev->flags = 0;
-
-	// Allocate cell rates and remember ASIC version
-	// Fibre: ATM_OC3_PCR = 1555200000/8/270*260/53 - 29/53
-	// Copper: (WRONG) we want 6 into the above, close to 25Mb/s
-	// Copper: (plagarise!) 25600000/8/270*260/53 - n/53
-
-	if (hrz_init(dev)) {
-		// to be really pedantic, this should be ATM_OC3c_PCR
-		dev->tx_avail = ATM_OC3_PCR;
-		dev->rx_avail = ATM_OC3_PCR;
-		set_bit(ultra, &dev->flags); // NOT "|= ultra" !
-	} else {
-		dev->tx_avail = ((25600000/8)*26)/(27*53);
-		dev->rx_avail = ((25600000/8)*26)/(27*53);
-		PRINTD(DBG_WARN, "Buggy ASIC: no TX bus-mastering.");
-	}
-
-	// rate changes spinlock
-	spin_lock_init(&dev->rate_lock);
-
-	// on-board memory access spinlock; we want atomic reads and
-	// writes to adapter memory (handles IRQ and SMP)
-	spin_lock_init(&dev->mem_lock);
-
-	init_waitqueue_head(&dev->tx_queue);
-
-	// vpi in 0..4, vci in 6..10
-	dev->atm_dev->ci_range.vpi_bits = vpi_bits;
-	dev->atm_dev->ci_range.vci_bits = 10-vpi_bits;
-
-	timer_setup(&dev->housekeeping, do_housekeeping, 0);
-	mod_timer(&dev->housekeeping, jiffies);
-
-out:
-	return err;
-
-out_free_irq:
-	free_irq(irq, dev);
-out_free:
-	kfree(dev);
-out_release:
-	release_region(iobase, HRZ_IO_EXTENT);
-out_disable:
-	pci_disable_device(pci_dev);
-	goto out;
-}
-
-static void hrz_remove_one(struct pci_dev *pci_dev)
-{
-	hrz_dev *dev;
-
-	dev = pci_get_drvdata(pci_dev);
-
-	PRINTD(DBG_INFO, "closing %p (atm_dev = %p)", dev, dev->atm_dev);
-	del_timer_sync(&dev->housekeeping);
-	hrz_reset(dev);
-	atm_dev_deregister(dev->atm_dev);
-	free_irq(dev->irq, dev);
-	release_region(dev->iobase, HRZ_IO_EXTENT);
-	kfree(dev);
-
-	pci_disable_device(pci_dev);
-}
-
-static void __init hrz_check_args (void) {
-#ifdef DEBUG_HORIZON
-  PRINTK (KERN_NOTICE, "debug bitmap is %hx", debug &= DBG_MASK);
-#else
-  if (debug)
-    PRINTK (KERN_NOTICE, "no debug support in this image");
-#endif
-  
-  if (vpi_bits > HRZ_MAX_VPI)
-    PRINTK (KERN_ERR, "vpi_bits has been limited to %hu",
-	    vpi_bits = HRZ_MAX_VPI);
-  
-  if (max_tx_size < 0 || max_tx_size > TX_AAL5_LIMIT)
-    PRINTK (KERN_NOTICE, "max_tx_size has been limited to %hu",
-	    max_tx_size = TX_AAL5_LIMIT);
-  
-  if (max_rx_size < 0 || max_rx_size > RX_AAL5_LIMIT)
-    PRINTK (KERN_NOTICE, "max_rx_size has been limited to %hu",
-	    max_rx_size = RX_AAL5_LIMIT);
-  
-  return;
-}
-
-MODULE_AUTHOR(maintainer_string);
-MODULE_DESCRIPTION(description_string);
-MODULE_LICENSE("GPL");
-module_param(debug, ushort, 0644);
-module_param(vpi_bits, ushort, 0);
-module_param(max_tx_size, int, 0);
-module_param(max_rx_size, int, 0);
-module_param(pci_lat, byte, 0);
-MODULE_PARM_DESC(debug, "debug bitmap, see .h file");
-MODULE_PARM_DESC(vpi_bits, "number of bits (0..4) to allocate to VPIs");
-MODULE_PARM_DESC(max_tx_size, "maximum size of TX AAL5 frames");
-MODULE_PARM_DESC(max_rx_size, "maximum size of RX AAL5 frames");
-MODULE_PARM_DESC(pci_lat, "PCI latency in bus cycles");
-
-static const struct pci_device_id hrz_pci_tbl[] = {
-	{ PCI_VENDOR_ID_MADGE, PCI_DEVICE_ID_MADGE_HORIZON, PCI_ANY_ID, PCI_ANY_ID,
-	  0, 0, 0 },
-	{ 0, }
-};
-
-MODULE_DEVICE_TABLE(pci, hrz_pci_tbl);
-
-static struct pci_driver hrz_driver = {
-	.name =		"horizon",
-	.probe =	hrz_probe,
-	.remove =	hrz_remove_one,
-	.id_table =	hrz_pci_tbl,
-};
-
-/********** module entry **********/
-
-static int __init hrz_module_init (void) {
-  BUILD_BUG_ON(sizeof(struct MEMMAP) != 128*1024/4);
-  
-  show_version();
-  
-  // check arguments
-  hrz_check_args();
-  
-  // get the juice
-  return pci_register_driver(&hrz_driver);
-}
-
-/********** module exit **********/
-
-static void __exit hrz_module_exit (void) {
-  PRINTD (DBG_FLOW, "cleanup_module");
-
-  pci_unregister_driver(&hrz_driver);
-}
-
-module_init(hrz_module_init);
-module_exit(hrz_module_exit);
diff --git a/drivers/atm/horizon.h b/drivers/atm/horizon.h
deleted file mode 100644
index 7523eba19bad..000000000000
--- a/drivers/atm/horizon.h
+++ /dev/null
@@ -1,492 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
-  Madge Horizon ATM Adapter driver.
-  Copyright (C) 1995-1999  Madge Networks Ltd.
-
-*/
-
-/*
-  IMPORTANT NOTE: Madge Networks no longer makes the adapters
-  supported by this driver and makes no commitment to maintain it.
-*/
-
-/* too many macros - change to inline functions */
-
-#ifndef DRIVER_ATM_HORIZON_H
-#define DRIVER_ATM_HORIZON_H
-
-
-#ifdef CONFIG_ATM_HORIZON_DEBUG
-#define DEBUG_HORIZON
-#endif
-
-#define DEV_LABEL                         "hrz"
-
-#ifndef PCI_VENDOR_ID_MADGE
-#define PCI_VENDOR_ID_MADGE               0x10B6
-#endif
-#ifndef PCI_DEVICE_ID_MADGE_HORIZON
-#define PCI_DEVICE_ID_MADGE_HORIZON       0x1000
-#endif
-
-// diagnostic output
-
-#define PRINTK(severity,format,args...) \
-  printk(severity DEV_LABEL ": " format "\n" , ## args)
-
-#ifdef DEBUG_HORIZON
-
-#define DBG_ERR  0x0001
-#define DBG_WARN 0x0002
-#define DBG_INFO 0x0004
-#define DBG_VCC  0x0008
-#define DBG_QOS  0x0010
-#define DBG_TX   0x0020
-#define DBG_RX   0x0040
-#define DBG_SKB  0x0080
-#define DBG_IRQ  0x0100
-#define DBG_FLOW 0x0200
-#define DBG_BUS  0x0400
-#define DBG_REGS 0x0800
-#define DBG_DATA 0x1000
-#define DBG_MASK 0x1fff
-
-/* the ## prevents the annoying double expansion of the macro arguments */
-/* KERN_INFO is used since KERN_DEBUG often does not make it to the console */
-#define PRINTDB(bits,format,args...) \
-  ( (debug & (bits)) ? printk (KERN_INFO DEV_LABEL ": " format , ## args) : 1 )
-#define PRINTDM(bits,format,args...) \
-  ( (debug & (bits)) ? printk (format , ## args) : 1 )
-#define PRINTDE(bits,format,args...) \
-  ( (debug & (bits)) ? printk (format "\n" , ## args) : 1 )
-#define PRINTD(bits,format,args...) \
-  ( (debug & (bits)) ? printk (KERN_INFO DEV_LABEL ": " format "\n" , ## args) : 1 )
-
-#else
-
-#define PRINTD(bits,format,args...)
-#define PRINTDB(bits,format,args...)
-#define PRINTDM(bits,format,args...)
-#define PRINTDE(bits,format,args...)
-
-#endif
-
-#define PRINTDD(sec,fmt,args...)
-#define PRINTDDB(sec,fmt,args...)
-#define PRINTDDM(sec,fmt,args...)
-#define PRINTDDE(sec,fmt,args...)
-
-// fixed constants
-
-#define SPARE_BUFFER_POOL_SIZE            MAX_VCS
-#define HRZ_MAX_VPI                       4
-#define MIN_PCI_LATENCY                   48 // 24 IS TOO SMALL
-
-/*  Horizon specific bits */
-/*  Register offsets */
-
-#define HRZ_IO_EXTENT                     0x80
-
-#define DATA_PORT_OFF                     0x00
-#define TX_CHANNEL_PORT_OFF               0x04
-#define TX_DESCRIPTOR_PORT_OFF            0x08
-#define MEMORY_PORT_OFF                   0x0C
-#define MEM_WR_ADDR_REG_OFF               0x14
-#define MEM_RD_ADDR_REG_OFF               0x18
-#define CONTROL_0_REG                     0x1C
-#define INT_SOURCE_REG_OFF                0x20
-#define INT_ENABLE_REG_OFF                0x24
-#define MASTER_RX_ADDR_REG_OFF            0x28
-#define MASTER_RX_COUNT_REG_OFF           0x2C
-#define MASTER_TX_ADDR_REG_OFF            0x30
-#define MASTER_TX_COUNT_REG_OFF           0x34
-#define TX_DESCRIPTOR_REG_OFF             0x38
-#define TX_CHANNEL_CONFIG_COMMAND_OFF     0x40
-#define TX_CHANNEL_CONFIG_DATA_OFF        0x44
-#define TX_FREE_BUFFER_COUNT_OFF          0x48
-#define RX_FREE_BUFFER_COUNT_OFF          0x4C
-#define TX_CONFIG_OFF                     0x50
-#define TX_STATUS_OFF                     0x54
-#define RX_CONFIG_OFF                     0x58
-#define RX_LINE_CONFIG_OFF                0x5C
-#define RX_QUEUE_RD_PTR_OFF               0x60
-#define RX_QUEUE_WR_PTR_OFF               0x64
-#define MAX_AAL5_CELL_COUNT_OFF           0x68
-#define RX_CHANNEL_PORT_OFF               0x6C
-#define TX_CELL_COUNT_OFF                 0x70
-#define RX_CELL_COUNT_OFF                 0x74
-#define HEC_ERROR_COUNT_OFF               0x78
-#define UNASSIGNED_CELL_COUNT_OFF         0x7C
-
-/*  Register bit definitions */
-
-/* Control 0 register */
-
-#define SEEPROM_DO                        0x00000001
-#define SEEPROM_DI                        0x00000002
-#define SEEPROM_SK                        0x00000004
-#define SEEPROM_CS                        0x00000008
-#define DEBUG_BIT_0                       0x00000010
-#define DEBUG_BIT_1                       0x00000020
-#define DEBUG_BIT_2                       0x00000040
-//      RESERVED                          0x00000080
-#define DEBUG_BIT_0_OE                    0x00000100
-#define DEBUG_BIT_1_OE                    0x00000200
-#define DEBUG_BIT_2_OE                    0x00000400
-//      RESERVED                          0x00000800
-#define DEBUG_BIT_0_STATE                 0x00001000
-#define DEBUG_BIT_1_STATE                 0x00002000
-#define DEBUG_BIT_2_STATE                 0x00004000
-//      RESERVED                          0x00008000
-#define GENERAL_BIT_0                     0x00010000
-#define GENERAL_BIT_1                     0x00020000
-#define GENERAL_BIT_2                     0x00040000
-#define GENERAL_BIT_3                     0x00080000
-#define RESET_HORIZON                     0x00100000
-#define RESET_ATM                         0x00200000
-#define RESET_RX                          0x00400000
-#define RESET_TX                          0x00800000
-#define RESET_HOST                        0x01000000
-//      RESERVED                          0x02000000
-#define TARGET_RETRY_DISABLE              0x04000000
-#define ATM_LAYER_SELECT                  0x08000000
-#define ATM_LAYER_STATUS                  0x10000000
-//      RESERVED                          0xE0000000
-
-/* Interrupt source and enable registers */
-
-#define RX_DATA_AV                        0x00000001
-#define RX_DISABLED                       0x00000002
-#define TIMING_MARKER                     0x00000004
-#define FORCED                            0x00000008
-#define RX_BUS_MASTER_COMPLETE            0x00000010
-#define TX_BUS_MASTER_COMPLETE            0x00000020
-#define ABR_TX_CELL_COUNT_INT             0x00000040
-#define DEBUG_INT                         0x00000080
-//      RESERVED                          0xFFFFFF00
-
-/* PIO and Bus Mastering */
-
-#define MAX_PIO_COUNT                     0x000000ff // 255 - make tunable?
-// 8188 is a hard limit for bus mastering
-#define MAX_TRANSFER_COUNT                0x00001ffc // 8188
-#define MASTER_TX_AUTO_APPEND_DESC        0x80000000
-
-/* TX channel config command port */
-
-#define PCR_TIMER_ACCESS                      0x0000
-#define SCR_TIMER_ACCESS                      0x0001
-#define BUCKET_CAPACITY_ACCESS                0x0002
-#define BUCKET_FULLNESS_ACCESS                0x0003
-#define RATE_TYPE_ACCESS                      0x0004
-//      UNUSED                                0x00F8
-#define TX_CHANNEL_CONFIG_MULT                0x0100
-//      UNUSED                                0xF800
-#define BUCKET_MAX_SIZE                       0x003f
-
-/* TX channel config data port */
-
-#define CLOCK_SELECT_SHIFT                    4
-#define CLOCK_DISABLE                         0x00ff
-
-#define IDLE_RATE_TYPE                       0x0
-#define ABR_RATE_TYPE                        0x1
-#define VBR_RATE_TYPE                        0x2
-#define CBR_RATE_TYPE                        0x3
-
-/* TX config register */
-
-#define DRVR_DRVRBAR_ENABLE                   0x0001
-#define TXCLK_MUX_SELECT_RCLK                 0x0002
-#define TRANSMIT_TIMING_MARKER                0x0004
-#define LOOPBACK_TIMING_MARKER                0x0008
-#define TX_TEST_MODE_16MHz                    0x0000
-#define TX_TEST_MODE_8MHz                     0x0010
-#define TX_TEST_MODE_5_33MHz                  0x0020
-#define TX_TEST_MODE_4MHz                     0x0030
-#define TX_TEST_MODE_3_2MHz                   0x0040
-#define TX_TEST_MODE_2_66MHz                  0x0050
-#define TX_TEST_MODE_2_29MHz                  0x0060
-#define TX_NORMAL_OPERATION                   0x0070
-#define ABR_ROUND_ROBIN                       0x0080
-
-/* TX status register */
-
-#define IDLE_CHANNELS_MASK                    0x00FF
-#define ABR_CELL_COUNT_REACHED_MULT           0x0100 
-#define ABR_CELL_COUNT_REACHED_MASK           0xFF
-
-/* RX config register */
-
-#define NON_USER_CELLS_IN_ONE_CHANNEL         0x0008
-#define RX_ENABLE                             0x0010
-#define IGNORE_UNUSED_VPI_VCI_BITS_SET        0x0000
-#define NON_USER_UNUSED_VPI_VCI_BITS_SET      0x0020
-#define DISCARD_UNUSED_VPI_VCI_BITS_SET       0x0040
-
-/* RX line config register */
-
-#define SIGNAL_LOSS                           0x0001
-#define FREQUENCY_DETECT_ERROR                0x0002
-#define LOCK_DETECT_ERROR                     0x0004
-#define SELECT_INTERNAL_LOOPBACK              0x0008
-#define LOCK_DETECT_ENABLE                    0x0010
-#define FREQUENCY_DETECT_ENABLE               0x0020
-#define USER_FRAQ                             0x0040
-#define GXTALOUT_SELECT_DIV4                  0x0080
-#define GXTALOUT_SELECT_NO_GATING             0x0100
-#define TIMING_MARKER_RECEIVED                0x0200
-
-/* RX channel port */
-
-#define RX_CHANNEL_MASK                       0x03FF
-// UNUSED                                     0x3C00
-#define FLUSH_CHANNEL                         0x4000
-#define RX_CHANNEL_UPDATE_IN_PROGRESS         0x8000
-
-/* Receive queue entry */
-
-#define RX_Q_ENTRY_LENGTH_MASK            0x0000FFFF
-#define RX_Q_ENTRY_CHANNEL_SHIFT          16
-#define SIMONS_DODGEY_MARKER              0x08000000
-#define RX_CONGESTION_EXPERIENCED         0x10000000
-#define RX_CRC_10_OK                      0x20000000
-#define RX_CRC_32_OK                      0x40000000
-#define RX_COMPLETE_FRAME                 0x80000000
-
-/*  Offsets and constants for use with the buffer memory         */
-
-/* Buffer pointers and channel types */
-
-#define BUFFER_PTR_MASK                   0x0000FFFF
-#define RX_INT_THRESHOLD_MULT             0x00010000
-#define RX_INT_THRESHOLD_MASK             0x07FF
-#define INT_EVERY_N_CELLS                 0x08000000
-#define CONGESTION_EXPERIENCED            0x10000000
-#define FIRST_CELL_OF_AAL5_FRAME          0x20000000
-#define CHANNEL_TYPE_AAL5                 0x00000000
-#define CHANNEL_TYPE_RAW_CELLS            0x40000000
-#define CHANNEL_TYPE_AAL3_4               0x80000000
-
-/* Buffer status stuff */
-
-#define BUFF_STATUS_MASK                  0x00030000
-#define BUFF_STATUS_EMPTY                 0x00000000
-#define BUFF_STATUS_CELL_AV               0x00010000
-#define BUFF_STATUS_LAST_CELL_AV          0x00020000
-
-/* Transmit channel stuff */
-
-/* Receive channel stuff */
-
-#define RX_CHANNEL_DISABLED               0x00000000
-#define RX_CHANNEL_IDLE                   0x00000001
-
-/*  General things */
-
-#define INITIAL_CRC                       0xFFFFFFFF
-
-// A Horizon u32, a byte! Really nasty. Horizon pointers are (32 bit)
-// word addresses and so standard C pointer operations break (as they
-// assume byte addresses); so we pretend that Horizon words (and word
-// pointers) are bytes (and byte pointers) for the purposes of having
-// a memory map that works.
-
-typedef u8 HDW;
-
-typedef struct cell_buf {
-  HDW payload[12];
-  HDW next;
-  HDW cell_count;               // AAL5 rx bufs
-  HDW res;
-  union {
-    HDW partial_crc;            // AAL5 rx bufs
-    HDW cell_header;            // RAW     bufs
-  } u;
-} cell_buf;
-
-typedef struct tx_ch_desc {
-  HDW rd_buf_type;
-  HDW wr_buf_type;
-  HDW partial_crc;
-  HDW cell_header;
-} tx_ch_desc;
-
-typedef struct rx_ch_desc {
-  HDW wr_buf_type;
-  HDW rd_buf_type;
-} rx_ch_desc;
-
-typedef struct rx_q_entry {
-  HDW entry;
-} rx_q_entry;
-
-#define TX_CHANS 8
-#define RX_CHANS 1024
-#define RX_QS 1024
-#define MAX_VCS RX_CHANS
-
-/* Horizon buffer memory map */
-
-// TX Channel Descriptors         2
-// TX Initial Buffers             8 // TX_CHANS
-#define BUFN1_SIZE              118 // (126 - TX_CHANS)
-//      RX/TX Start/End Buffers   4
-#define BUFN2_SIZE              124
-//      RX Queue Entries         64
-#define BUFN3_SIZE              192
-//      RX Channel Descriptors  128
-#define BUFN4_SIZE             1408
-//      TOTAL cell_buff chunks 2048
-
-//    cell_buf             bufs[2048];
-//    HDW                  dws[32768];
-
-typedef struct MEMMAP {
-  tx_ch_desc  tx_descs[TX_CHANS];     //  8 *    4 =    32 , 0x0020
-  cell_buf    inittxbufs[TX_CHANS];   // these are really
-  cell_buf    bufn1[BUFN1_SIZE];      // part of this pool
-  cell_buf    txfreebufstart;
-  cell_buf    txfreebufend;
-  cell_buf    rxfreebufstart;
-  cell_buf    rxfreebufend;           // 8+118+1+1+1+1+124 = 254
-  cell_buf    bufn2[BUFN2_SIZE];      // 16 *  254 =  4064 , 0x1000
-  rx_q_entry  rx_q_entries[RX_QS];    //  1 * 1024 =  1024 , 0x1400
-  cell_buf    bufn3[BUFN3_SIZE];      // 16 *  192 =  3072 , 0x2000
-  rx_ch_desc  rx_descs[MAX_VCS];      //  2 * 1024 =  2048 , 0x2800
-  cell_buf    bufn4[BUFN4_SIZE];      // 16 * 1408 = 22528 , 0x8000
-} MEMMAP;
-
-#define memmap ((MEMMAP *)0)
-
-/* end horizon specific bits */
-
-typedef enum {
-  aal0,
-  aal34,
-  aal5
-} hrz_aal;
-
-typedef enum {
-  tx_busy,
-  rx_busy,
-  ultra
-} hrz_flags;
-
-// a single struct pointed to by atm_vcc->dev_data
-
-typedef struct {
-  unsigned int        tx_rate;
-  unsigned int        rx_rate;
-  u16                 channel;
-  u16                 tx_xbr_bits;
-  u16                 tx_pcr_bits;
-#if 0
-  u16                 tx_scr_bits;
-  u16                 tx_bucket_bits;
-#endif
-  hrz_aal             aal;
-} hrz_vcc;
-
-struct hrz_dev {
-  
-  u32                 iobase;
-  u32 *               membase;
-
-  struct sk_buff *    rx_skb;     // skb being RXed
-  unsigned int        rx_bytes;   // bytes remaining to RX within region
-  void *              rx_addr;    // addr to send bytes to (for PIO)
-  unsigned int        rx_channel; // channel that the skb is going out on
-
-  struct sk_buff *    tx_skb;     // skb being TXed
-  unsigned int        tx_bytes;   // bytes remaining to TX within region
-  void *              tx_addr;    // addr to send bytes from (for PIO)
-  struct iovec *      tx_iovec;   // remaining regions
-  unsigned int        tx_regions; // number of remaining regions
-
-  spinlock_t          mem_lock;
-  wait_queue_head_t   tx_queue;
-
-  u8                  irq;
-  unsigned long	      flags;
-  u8                  tx_last;
-  u8                  tx_idle;
-
-  rx_q_entry *        rx_q_reset;
-  rx_q_entry *        rx_q_entry;
-  rx_q_entry *        rx_q_wrap;
-
-  struct atm_dev *    atm_dev;
-
-  u32                 last_vc;
-  
-  int                 noof_spare_buffers;
-  u16                 spare_buffers[SPARE_BUFFER_POOL_SIZE];
-
-  u16                 tx_channel_record[TX_CHANS];
-
-  // this is what we follow when we get incoming data
-  u32              txer[MAX_VCS/32];
-  struct atm_vcc * rxer[MAX_VCS];
-
-  // cell rate allocation
-  spinlock_t       rate_lock;
-  unsigned int     rx_avail;
-  unsigned int     tx_avail;
-  
-  // dev stats
-  unsigned long    tx_cell_count;
-  unsigned long    rx_cell_count;
-  unsigned long    hec_error_count;
-  unsigned long    unassigned_cell_count;
-
-  struct pci_dev * pci_dev;
-  struct timer_list housekeeping;
-};
-
-typedef struct hrz_dev hrz_dev;
-
-/* macros for use later */
-
-#define BUF_PTR(cbptr) ((cbptr) - (cell_buf *) 0)
-
-#define INTERESTING_INTERRUPTS \
-  (RX_DATA_AV | RX_DISABLED | TX_BUS_MASTER_COMPLETE | RX_BUS_MASTER_COMPLETE)
-
-// 190 cells by default (192 TX buffers - 2 elbow room, see docs)
-#define TX_AAL5_LIMIT (190*ATM_CELL_PAYLOAD-ATM_AAL5_TRAILER) // 9112
-
-// Have enough RX buffers (unless we allow other buffer splits)
-#define RX_AAL5_LIMIT ATM_MAX_AAL5_PDU
-
-/* multi-statement macro protector */
-#define DW(x) do{ x } while(0)
-
-#define HRZ_DEV(atm_dev) ((hrz_dev *) (atm_dev)->dev_data)
-#define HRZ_VCC(atm_vcc) ((hrz_vcc *) (atm_vcc)->dev_data)
-
-/* Turn the LEDs on and off                                                 */
-// The LEDs bits are upside down in that setting the bit in the debug
-// register will turn the appropriate LED off.
-
-#define YELLOW_LED    DEBUG_BIT_0
-#define GREEN_LED     DEBUG_BIT_1
-#define YELLOW_LED_OE DEBUG_BIT_0_OE
-#define GREEN_LED_OE  DEBUG_BIT_1_OE
-
-#define GREEN_LED_OFF(dev)                      \
-  wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) | GREEN_LED)
-#define GREEN_LED_ON(dev)                       \
-  wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) &~ GREEN_LED)
-#define YELLOW_LED_OFF(dev)                     \
-  wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) | YELLOW_LED)
-#define YELLOW_LED_ON(dev)                      \
-  wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) &~ YELLOW_LED)
-
-typedef enum {
-  round_up,
-  round_down,
-  round_nearest
-} rounding;
-
-#endif /* DRIVER_ATM_HORIZON_H */
diff --git a/drivers/atm/idt77105.c b/drivers/atm/idt77105.c
index 63871859e6e8..e6a300203e6c 100644
--- a/drivers/atm/idt77105.c
+++ b/drivers/atm/idt77105.c
@@ -192,7 +192,7 @@ static int idt77105_ioctl(struct atm_dev *dev,unsigned int cmd,void __user *arg)
 	switch (cmd) {
 		case IDT77105_GETSTATZ:
 			if (!capable(CAP_NET_ADMIN)) return -EPERM;
-			/* fall through */
+			fallthrough;
 		case IDT77105_GETSTAT:
 			return fetch_stats(dev, arg, cmd == IDT77105_GETSTATZ);
 		case ATM_SETLOOP:
@@ -262,7 +262,7 @@ static int idt77105_start(struct atm_dev *dev)
 {
 	unsigned long flags;
 
-	if (!(dev->dev_data = kmalloc(sizeof(struct idt77105_priv),GFP_KERNEL)))
+	if (!(dev->phy_data = kmalloc(sizeof(struct idt77105_priv),GFP_KERNEL)))
 		return -ENOMEM;
 	PRIV(dev)->dev = dev;
 	spin_lock_irqsave(&idt77105_priv_lock, flags);
@@ -337,7 +337,7 @@ static int idt77105_stop(struct atm_dev *dev)
                 else
                     idt77105_all = walk->next;
 	        dev->phy = NULL;
-                dev->dev_data = NULL;
+                dev->phy_data = NULL;
                 kfree(walk);
                 break;
             }
@@ -366,10 +366,11 @@ EXPORT_SYMBOL(idt77105_init);
 static void __exit idt77105_exit(void)
 {
 	/* turn off timers */
-	del_timer_sync(&stats_timer);
-	del_timer_sync(&restart_timer);
+	timer_delete_sync(&stats_timer);
+	timer_delete_sync(&restart_timer);
 }
 
 module_exit(idt77105_exit);
 
+MODULE_DESCRIPTION("IDT77105 PHY driver");
 MODULE_LICENSE("GPL");
diff --git a/drivers/atm/idt77252.c b/drivers/atm/idt77252.c
index df51680e8931..f2e91b7d79f0 100644
--- a/drivers/atm/idt77252.c
+++ b/drivers/atm/idt77252.c
@@ -835,6 +835,7 @@ queue_skb(struct idt77252_dev *card, struct vc_map *vc,
 	unsigned long flags;
 	int error;
 	int aal;
+	u32 word4;
 
 	if (skb->len == 0) {
 		printk("%s: invalid skb->len (%d)\n", card->name, skb->len);
@@ -846,9 +847,13 @@ queue_skb(struct idt77252_dev *card, struct vc_map *vc,
 
 	tbd = &IDT77252_PRV_TBD(skb);
 	vcc = ATM_SKB(skb)->vcc;
+	word4 = (skb->data[0] << 24) | (skb->data[1] << 16) |
+			(skb->data[2] <<  8) | (skb->data[3] <<  0);
 
 	IDT77252_PRV_PADDR(skb) = dma_map_single(&card->pcidev->dev, skb->data,
 						 skb->len, DMA_TO_DEVICE);
+	if (dma_mapping_error(&card->pcidev->dev, IDT77252_PRV_PADDR(skb)))
+		return -ENOMEM;
 
 	error = -EINVAL;
 
@@ -859,8 +864,7 @@ queue_skb(struct idt77252_dev *card, struct vc_map *vc,
 		tbd->word_1 = SAR_TBD_OAM | ATM_CELL_PAYLOAD | SAR_TBD_EPDU;
 		tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4;
 		tbd->word_3 = 0x00000000;
-		tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) |
-			      (skb->data[2] <<  8) | (skb->data[3] <<  0);
+		tbd->word_4 = word4;
 
 		if (test_bit(VCF_RSV, &vc->flags))
 			vc = card->vcs[0];
@@ -890,8 +894,7 @@ queue_skb(struct idt77252_dev *card, struct vc_map *vc,
 
 		tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4;
 		tbd->word_3 = 0x00000000;
-		tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) |
-			      (skb->data[2] <<  8) | (skb->data[3] <<  0);
+		tbd->word_4 = word4;
 		break;
 
 	case ATM_AAL5:
@@ -1117,8 +1120,8 @@ dequeue_rx(struct idt77252_dev *card, struct rsq_entry *rsqe)
 	rpp->len += skb->len;
 
 	if (stat & SAR_RSQE_EPDU) {
+		unsigned int len, truesize;
 		unsigned char *l1l2;
-		unsigned int len;
 
 		l1l2 = (unsigned char *) ((unsigned long) skb->data + skb->len - 6);
 
@@ -1188,14 +1191,15 @@ dequeue_rx(struct idt77252_dev *card, struct rsq_entry *rsqe)
 		ATM_SKB(skb)->vcc = vcc;
 		__net_timestamp(skb);
 
+		truesize = skb->truesize;
 		vcc->push(vcc, skb);
 		atomic_inc(&vcc->stats->rx);
 
-		if (skb->truesize > SAR_FB_SIZE_3)
+		if (truesize > SAR_FB_SIZE_3)
 			add_rx_skb(card, 3, SAR_FB_SIZE_3, 1);
-		else if (skb->truesize > SAR_FB_SIZE_2)
+		else if (truesize > SAR_FB_SIZE_2)
 			add_rx_skb(card, 2, SAR_FB_SIZE_2, 1);
-		else if (skb->truesize > SAR_FB_SIZE_1)
+		else if (truesize > SAR_FB_SIZE_1)
 			add_rx_skb(card, 1, SAR_FB_SIZE_1, 1);
 		else
 			add_rx_skb(card, 0, SAR_FB_SIZE_0, 1);
@@ -1529,7 +1533,7 @@ idt77252_tx(struct idt77252_dev *card)
 static void
 tst_timer(struct timer_list *t)
 {
-	struct idt77252_dev *card = from_timer(card, t, tst_timer);
+	struct idt77252_dev *card = timer_container_of(card, t, tst_timer);
 	unsigned long base, idle, jump;
 	unsigned long flags;
 	u32 pc;
@@ -1783,12 +1787,6 @@ set_tct(struct idt77252_dev *card, struct vc_map *vc)
 /*****************************************************************************/
 
 static __inline__ int
-idt77252_fbq_level(struct idt77252_dev *card, int queue)
-{
-	return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) & 0x0f;
-}
-
-static __inline__ int
 idt77252_fbq_full(struct idt77252_dev *card, int queue)
 {
 	return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) == 0x0f;
@@ -1861,6 +1859,8 @@ add_rx_skb(struct idt77252_dev *card, int queue,
 		paddr = dma_map_single(&card->pcidev->dev, skb->data,
 				       skb_end_pointer(skb) - skb->data,
 				       DMA_FROM_DEVICE);
+		if (dma_mapping_error(&card->pcidev->dev, paddr))
+			goto outpoolrm;
 		IDT77252_PRV_PADDR(skb) = paddr;
 
 		if (push_rx_skb(card, skb, queue)) {
@@ -1875,6 +1875,7 @@ outunmap:
 	dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
 			 skb_end_pointer(skb) - skb->data, DMA_FROM_DEVICE);
 
+outpoolrm:
 	handle = IDT77252_PRV_POOL(skb);
 	card->sbpool[POOL_QUEUE(handle)].skb[POOL_INDEX(handle)] = NULL;
 
@@ -2074,7 +2075,7 @@ idt77252_rate_logindex(struct idt77252_dev *card, int pcr)
 static void
 idt77252_est_timer(struct timer_list *t)
 {
-	struct rate_estimator *est = from_timer(est, t, timer);
+	struct rate_estimator *est = timer_container_of(est, t, timer);
 	struct vc_map *vc = est->vc;
 	struct idt77252_dev *card = vc->card;
 	unsigned long flags;
@@ -2218,7 +2219,7 @@ idt77252_init_ubr(struct idt77252_dev *card, struct vc_map *vc,
 	}
 	spin_unlock_irqrestore(&vc->lock, flags);
 	if (est) {
-		del_timer_sync(&est->timer);
+		timer_shutdown_sync(&est->timer);
 		kfree(est);
 	}
 
@@ -2535,7 +2536,7 @@ done:
 		vc->tx_vcc = NULL;
 
 		if (vc->estimator) {
-			del_timer(&vc->estimator->timer);
+			timer_shutdown(&vc->estimator->timer);
 			kfree(vc->estimator);
 			vc->estimator = NULL;
 		}
@@ -2914,6 +2915,7 @@ close_card_oam(struct idt77252_dev *card)
 
 				recycle_rx_pool_skb(card, &vc->rcv.rx_pool);
 			}
+			kfree(vc);
 		}
 	}
 }
@@ -2934,6 +2936,8 @@ open_card_ubr0(struct idt77252_dev *card)
 	vc->scq = alloc_scq(card, vc->class);
 	if (!vc->scq) {
 		printk("%s: can't get SCQ.\n", card->name);
+		kfree(card->vcs[0]);
+		card->vcs[0] = NULL;
 		return -ENOMEM;
 	}
 
@@ -2957,6 +2961,15 @@ open_card_ubr0(struct idt77252_dev *card)
 	return 0;
 }
 
+static void
+close_card_ubr0(struct idt77252_dev *card)
+{
+	struct vc_map *vc = card->vcs[0];
+
+	free_scq(card, vc->scq);
+	kfree(vc);
+}
+
 static int
 idt77252_dev_open(struct idt77252_dev *card)
 {
@@ -3006,6 +3019,7 @@ static void idt77252_dev_close(struct atm_dev *dev)
 	struct idt77252_dev *card = dev->dev_data;
 	u32 conf;
 
+	close_card_ubr0(card);
 	close_card_oam(card);
 
 	conf = SAR_CFG_RXPTH |	/* enable receive path           */
@@ -3541,7 +3555,7 @@ static int idt77252_preset(struct idt77252_dev *card)
 		return -1;
 	}
 	if (!(pci_command & PCI_COMMAND_IO)) {
-		printk("%s: PCI_COMMAND: %04x (???)\n",
+		printk("%s: PCI_COMMAND: %04x (?)\n",
 		       card->name, pci_command);
 		deinit_card(card);
 		return (-1);
@@ -3606,7 +3620,7 @@ static int idt77252_init_one(struct pci_dev *pcidev,
 
 	if ((err = dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(32)))) {
 		printk("idt77252: can't enable DMA for PCI device at %s\n", pci_name(pcidev));
-		return err;
+		goto err_out_disable_pdev;
 	}
 
 	card = kzalloc(sizeof(struct idt77252_dev), GFP_KERNEL);
@@ -3742,16 +3756,7 @@ static int __init idt77252_init(void)
 	struct sk_buff *skb;
 
 	printk("%s: at %p\n", __func__, idt77252_init);
-
-	if (sizeof(skb->cb) < sizeof(struct atm_skb_data) +
-			      sizeof(struct idt77252_skb_prv)) {
-		printk(KERN_ERR "%s: skb->cb is too small (%lu < %lu)\n",
-		       __func__, (unsigned long) sizeof(skb->cb),
-		       (unsigned long) sizeof(struct atm_skb_data) +
-				       sizeof(struct idt77252_skb_prv));
-		return -EIO;
-	}
-
+	BUILD_BUG_ON(sizeof(skb->cb) < sizeof(struct idt77252_skb_prv) + sizeof(struct atm_skb_data));
 	return pci_register_driver(&idt77252_driver);
 }
 
@@ -3766,6 +3771,7 @@ static void __exit idt77252_exit(void)
 		card = idt77252_chain;
 		dev = card->atmdev;
 		idt77252_chain = card->next;
+		timer_shutdown_sync(&card->tst_timer);
 
 		if (dev->phy->stop)
 			dev->phy->stop(dev);
diff --git a/drivers/atm/idt77252.h b/drivers/atm/idt77252.h
index 9339197d701c..b059d31364dd 100644
--- a/drivers/atm/idt77252.h
+++ b/drivers/atm/idt77252.h
@@ -789,7 +789,7 @@ struct idt77252_skb_prv {
 	struct scqe	tbd;	/* Transmit Buffer Descriptor */
 	dma_addr_t	paddr;	/* DMA handle */
 	u32		pool;	/* sb_pool handle */
-};
+} __packed;
 
 #define IDT77252_PRV_TBD(skb)	\
 	(((struct idt77252_skb_prv *)(ATM_SKB(skb)+1))->tbd)
diff --git a/drivers/atm/iphase.c b/drivers/atm/iphase.c
index 8c7a996d1f16..301e697e22ad 100644
--- a/drivers/atm/iphase.c
+++ b/drivers/atm/iphase.c
@@ -47,6 +47,7 @@
 #include <linux/errno.h>  
 #include <linux/atm.h>  
 #include <linux/atmdev.h>  
+#include <linux/ctype.h>
 #include <linux/sonet.h>  
 #include <linux/skbuff.h>  
 #include <linux/time.h>  
@@ -89,6 +90,7 @@ module_param(IA_RX_BUF, int, 0);
 module_param(IA_RX_BUF_SZ, int, 0);
 module_param(IADebugFlag, uint, 0644);
 
+MODULE_DESCRIPTION("Driver for Interphase ATM PCI NICs");
 MODULE_LICENSE("GPL");
 
 /**************************** IA_LIB **********************************/
@@ -177,7 +179,6 @@ static void ia_hack_tcq(IADEV *dev) {
 
 static u16 get_desc (IADEV *dev, struct ia_vcc *iavcc) {
   u_short 		desc_num, i;
-  struct sk_buff        *skb;
   struct ia_vcc         *iavcc_r = NULL; 
   unsigned long delta;
   static unsigned long timer = 0;
@@ -201,8 +202,7 @@ static u16 get_desc (IADEV *dev, struct ia_vcc *iavcc) {
            else 
               dev->ffL.tcq_rd -= 2;
            *(u_short *)(dev->seg_ram + dev->ffL.tcq_rd) = i+1;
-           if (!(skb = dev->desc_tbl[i].txskb) || 
-                          !(iavcc_r = dev->desc_tbl[i].iavcc))
+           if (!dev->desc_tbl[i].txskb || !(iavcc_r = dev->desc_tbl[i].iavcc))
               printk("Fatal err, desc table vcc or skb is NULL\n");
            else 
               iavcc_r->vc_desc_cnt--;
@@ -680,7 +680,7 @@ static void ia_tx_poll (IADEV *iadev) {
           skb1 = skb_dequeue(&iavcc->txing_skb);
        }                                                        
        if (!skb1) {
-          IF_EVENT(printk("IA: Vci %d - skb not found requed\n",vcc->vci);)
+          IF_EVENT(printk("IA: Vci %d - skb not found requeued\n",vcc->vci);)
           ia_enque_head_rtn_q (&iadev->tx_return_q, rtne);
           break;
        }
@@ -740,7 +740,7 @@ static u16 ia_eeprom_get (IADEV *iadev, u32 addr)
         u32	t;
 	int	i;
 	/*
-	 * Read the first bit that was clocked with the falling edge of the
+	 * Read the first bit that was clocked with the falling edge of
 	 * the last command data clock
 	 */
 	NVRAM_CMD(IAREAD + addr);
@@ -996,10 +996,12 @@ static void xdump( u_char*  cp, int  length, char*  prefix )
         }
         pBuf += sprintf( pBuf, "  " );
         for(col = 0;count + col < length && col < 16; col++){
-            if (isprint((int)cp[count + col]))
-                pBuf += sprintf( pBuf, "%c", cp[count + col] );
-            else
-                pBuf += sprintf( pBuf, "." );
+		u_char c = cp[count + col];
+
+		if (isascii(c) && isprint(c))
+			pBuf += sprintf(pBuf, "%c", c);
+		else
+			pBuf += sprintf(pBuf, ".");
                 }
         printk("%s\n", prntBuf);
         count += col;
@@ -2290,19 +2292,21 @@ static int get_esi(struct atm_dev *dev)
 static int reset_sar(struct atm_dev *dev)  
 {  
 	IADEV *iadev;  
-	int i, error = 1;  
+	int i, error;
 	unsigned int pci[64];  
 	  
 	iadev = INPH_IA_DEV(dev);  
-	for(i=0; i<64; i++)  
-	  if ((error = pci_read_config_dword(iadev->pci,  
-				i*4, &pci[i])) != PCIBIOS_SUCCESSFUL)  
-  	      return error;  
+	for (i = 0; i < 64; i++) {
+		error = pci_read_config_dword(iadev->pci, i * 4, &pci[i]);
+		if (error != PCIBIOS_SUCCESSFUL)
+			return error;
+	}
 	writel(0, iadev->reg+IPHASE5575_EXT_RESET);  
-	for(i=0; i<64; i++)  
-	  if ((error = pci_write_config_dword(iadev->pci,  
-					i*4, pci[i])) != PCIBIOS_SUCCESSFUL)  
-	    return error;  
+	for (i = 0; i < 64; i++) {
+		error = pci_write_config_dword(iadev->pci, i * 4, pci[i]);
+		if (error != PCIBIOS_SUCCESSFUL)
+			return error;
+	}
 	udelay(5);  
 	return 0;  
 }  
@@ -2880,20 +2884,6 @@ static int ia_ioctl(struct atm_dev *dev, unsigned int cmd, void __user *arg)
    return 0;  
 }  
   
-static int ia_getsockopt(struct atm_vcc *vcc, int level, int optname,   
-	void __user *optval, int optlen)  
-{  
-	IF_EVENT(printk(">ia_getsockopt\n");)  
-	return -EINVAL;  
-}  
-  
-static int ia_setsockopt(struct atm_vcc *vcc, int level, int optname,   
-	void __user *optval, unsigned int optlen)  
-{  
-	IF_EVENT(printk(">ia_setsockopt\n");)  
-	return -EINVAL;  
-}  
-  
 static int ia_pkt_tx (struct atm_vcc *vcc, struct sk_buff *skb) {
         IADEV *iadev;
         struct dle *wr_ptr;
@@ -3164,8 +3154,6 @@ static const struct atmdev_ops ops = {
 	.open		= ia_open,  
 	.close		= ia_close,  
 	.ioctl		= ia_ioctl,  
-	.getsockopt	= ia_getsockopt,  
-	.setsockopt	= ia_setsockopt,  
 	.send		= ia_send,  
 	.phy_put	= ia_phy_put,  
 	.phy_get	= ia_phy_get,  
@@ -3295,7 +3283,7 @@ static void __exit ia_module_exit(void)
 {
 	pci_unregister_driver(&ia_driver);
 
-        del_timer(&ia_timer);
+	timer_delete_sync(&ia_timer);
 }
 
 module_init(ia_module_init);
diff --git a/drivers/atm/iphase.h b/drivers/atm/iphase.h
index 2beacf2fc1ec..2f5f8875cbd1 100644
--- a/drivers/atm/iphase.h
+++ b/drivers/atm/iphase.h
@@ -124,7 +124,6 @@
 #define IF_RXPKT(A)
 #endif /* CONFIG_ATM_IA_DEBUG */ 
 
-#define isprint(a) ((a >=' ')&&(a <= '~'))  
 #define ATM_DESC(skb) (skb->protocol)
 #define IA_SKB_STATE(skb) (skb->protocol)
 #define IA_DLED   1
diff --git a/drivers/atm/lanai.c b/drivers/atm/lanai.c
index 645a6bc1df88..0dfa2cdc897c 100644
--- a/drivers/atm/lanai.c
+++ b/drivers/atm/lanai.c
@@ -755,7 +755,7 @@ static void lanai_shutdown_rx_vci(const struct lanai_vcc *lvcc)
 /* Shutdown transmitting on card.
  * Unfortunately the lanai needs us to wait until all the data
  * drains out of the buffer before we can dealloc it, so this
- * can take awhile -- up to 370ms for a full 128KB buffer
+ * can take a while -- up to 370ms for a full 128KB buffer
  * assuming everone else is quiet.  In theory the time is
  * boundless if there's a CBR VCC holding things up.
  */
@@ -765,8 +765,7 @@ static void lanai_shutdown_tx_vci(struct lanai_dev *lanai,
 	struct sk_buff *skb;
 	unsigned long flags, timeout;
 	int read, write, lastread = -1;
-	APRINTK(!in_interrupt(),
-	    "lanai_shutdown_tx_vci called w/o process context!\n");
+
 	if (lvcc->vbase == NULL)	/* We were never bound to a VCI */
 		return;
 	/* 15.2.1 - wait for queue to drain */
@@ -1759,7 +1758,7 @@ static void iter_dequeue(struct lanai_dev *lanai, vci_t vci)
 
 static void lanai_timed_poll(struct timer_list *t)
 {
-	struct lanai_dev *lanai = from_timer(lanai, t, timer);
+	struct lanai_dev *lanai = timer_container_of(lanai, t, timer);
 #ifndef DEBUG_RW
 	unsigned long flags;
 #ifdef USE_POWERDOWN
@@ -1793,7 +1792,7 @@ static inline void lanai_timed_poll_start(struct lanai_dev *lanai)
 
 static inline void lanai_timed_poll_stop(struct lanai_dev *lanai)
 {
-	del_timer_sync(&lanai->timer);
+	timer_delete_sync(&lanai->timer);
 }
 
 /* -------------------- INTERRUPT SERVICE: */
@@ -2019,7 +2018,7 @@ static int lanai_normalize_ci(struct lanai_dev *lanai,
 	switch (*vpip) {
 		case ATM_VPI_ANY:
 			*vpip = 0;
-			/* FALLTHROUGH */
+			fallthrough;
 		case 0:
 			break;
 		default:
@@ -2234,6 +2233,7 @@ static int lanai_dev_open(struct atm_dev *atmdev)
 	conf1_write(lanai);
 #endif
 	iounmap(lanai->base);
+	lanai->base = NULL;
     error_pci:
 	pci_disable_device(lanai->pci);
     error:
@@ -2246,6 +2246,8 @@ static int lanai_dev_open(struct atm_dev *atmdev)
 static void lanai_dev_close(struct atm_dev *atmdev)
 {
 	struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data;
+	if (lanai->base==NULL)
+		return;
 	printk(KERN_INFO DEV_LABEL "(itf %d): shutting down interface\n",
 	    lanai->number);
 	lanai_timed_poll_stop(lanai);
@@ -2537,8 +2539,6 @@ static const struct atmdev_ops ops = {
 	.dev_close	= lanai_dev_close,
 	.open		= lanai_open,
 	.close		= lanai_close,
-	.getsockopt	= NULL,
-	.setsockopt	= NULL,
 	.send		= lanai_send,
 	.phy_put	= NULL,
 	.phy_get	= NULL,
@@ -2555,7 +2555,7 @@ static int lanai_init_one(struct pci_dev *pci,
 	struct atm_dev *atmdev;
 	int result;
 
-	lanai = kmalloc(sizeof(*lanai), GFP_KERNEL);
+	lanai = kzalloc(sizeof(*lanai), GFP_KERNEL);
 	if (lanai == NULL) {
 		printk(KERN_ERR DEV_LABEL
 		       ": couldn't allocate dev_data structure!\n");
diff --git a/drivers/atm/nicstar.c b/drivers/atm/nicstar.c
index 7af74fb450a0..45952cfea06b 100644
--- a/drivers/atm/nicstar.c
+++ b/drivers/atm/nicstar.c
@@ -130,8 +130,9 @@ static int ns_open(struct atm_vcc *vcc);
 static void ns_close(struct atm_vcc *vcc);
 static void fill_tst(ns_dev * card, int n, vc_map * vc);
 static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb);
+static int ns_send_bh(struct atm_vcc *vcc, struct sk_buff *skb);
 static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd,
-		     struct sk_buff *skb);
+		     struct sk_buff *skb, bool may_sleep);
 static void process_tsq(ns_dev * card);
 static void drain_scq(ns_dev * card, scq_info * scq, int pos);
 static void process_rsq(ns_dev * card);
@@ -160,6 +161,7 @@ static const struct atmdev_ops atm_ops = {
 	.close = ns_close,
 	.ioctl = ns_ioctl,
 	.send = ns_send,
+	.send_bh = ns_send_bh,
 	.phy_put = ns_phy_put,
 	.phy_get = ns_phy_get,
 	.proc_read = ns_proc_read,
@@ -169,6 +171,7 @@ static const struct atmdev_ops atm_ops = {
 static struct timer_list ns_timer;
 static char *mac[NS_MAX_CARDS];
 module_param_array(mac, charp, NULL, 0);
+MODULE_DESCRIPTION("ATM NIC driver for IDT 77201/77211 \"NICStAR\" and Fore ForeRunnerLE.");
 MODULE_LICENSE("GPL");
 
 /* Functions */
@@ -297,7 +300,7 @@ static void __exit nicstar_cleanup(void)
 {
 	XPRINTK("nicstar: nicstar_cleanup() called.\n");
 
-	del_timer(&ns_timer);
+	timer_delete_sync(&ns_timer);
 
 	pci_unregister_driver(&nicstar_driver);
 
@@ -525,6 +528,15 @@ static int ns_init_card(int i, struct pci_dev *pcidev)
 	/* Set the VPI/VCI MSb mask to zero so we can receive OAM cells */
 	writel(0x00000000, card->membase + VPM);
 
+	card->intcnt = 0;
+	if (request_irq
+	    (pcidev->irq, &ns_irq_handler, IRQF_SHARED, "nicstar", card) != 0) {
+		pr_err("nicstar%d: can't allocate IRQ %d.\n", i, pcidev->irq);
+		error = 9;
+		ns_init_card_error(card, error);
+		return error;
+	}
+
 	/* Initialize TSQ */
 	card->tsq.org = dma_alloc_coherent(&card->pcidev->dev,
 					   NS_TSQSIZE + NS_TSQ_ALIGNMENT,
@@ -751,15 +763,6 @@ static int ns_init_card(int i, struct pci_dev *pcidev)
 
 	card->efbie = 1;
 
-	card->intcnt = 0;
-	if (request_irq
-	    (pcidev->irq, &ns_irq_handler, IRQF_SHARED, "nicstar", card) != 0) {
-		printk("nicstar%d: can't allocate IRQ %d.\n", i, pcidev->irq);
-		error = 9;
-		ns_init_card_error(card, error);
-		return error;
-	}
-
 	/* Register device */
 	card->atmdev = atm_dev_register("nicstar", &card->pcidev->dev, &atm_ops,
 					-1, NULL);
@@ -837,10 +840,12 @@ static void ns_init_card_error(ns_dev *card, int error)
 			dev_kfree_skb_any(hb);
 	}
 	if (error >= 12) {
-		kfree(card->rsq.org);
+		dma_free_coherent(&card->pcidev->dev, NS_RSQSIZE + NS_RSQ_ALIGNMENT,
+				card->rsq.org, card->rsq.dma);
 	}
 	if (error >= 11) {
-		kfree(card->tsq.org);
+		dma_free_coherent(&card->pcidev->dev, NS_TSQSIZE + NS_TSQ_ALIGNMENT,
+				card->tsq.org, card->tsq.dma);
 	}
 	if (error >= 10) {
 		free_irq(card->pcidev->irq, card);
@@ -857,7 +862,6 @@ static void ns_init_card_error(ns_dev *card, int error)
 static scq_info *get_scq(ns_dev *card, int size, u32 scd)
 {
 	scq_info *scq;
-	int i;
 
 	if (size != VBR_SCQSIZE && size != CBR_SCQSIZE)
 		return NULL;
@@ -871,9 +875,8 @@ static scq_info *get_scq(ns_dev *card, int size, u32 scd)
 		kfree(scq);
 		return NULL;
 	}
-	scq->skb = kmalloc_array(size / NS_SCQE_SIZE,
-				 sizeof(*scq->skb),
-				 GFP_KERNEL);
+	scq->skb = kcalloc(size / NS_SCQE_SIZE, sizeof(*scq->skb),
+			   GFP_KERNEL);
 	if (!scq->skb) {
 		dma_free_coherent(&card->pcidev->dev,
 				  2 * size, scq->org, scq->dma);
@@ -886,15 +889,11 @@ static scq_info *get_scq(ns_dev *card, int size, u32 scd)
 	scq->last = scq->base + (scq->num_entries - 1);
 	scq->tail = scq->last;
 	scq->scd = scd;
-	scq->num_entries = size / NS_SCQE_SIZE;
 	scq->tbd_count = 0;
 	init_waitqueue_head(&scq->scqfull_waitq);
 	scq->full = 0;
 	spin_lock_init(&scq->lock);
 
-	for (i = 0; i < scq->num_entries; i++)
-		scq->skb[i] = NULL;
-
 	return scq;
 }
 
@@ -1620,7 +1619,7 @@ static void fill_tst(ns_dev * card, int n, vc_map * vc)
 	card->tst_addr = new_tst;
 }
 
-static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb)
+static int _ns_send(struct atm_vcc *vcc, struct sk_buff *skb, bool may_sleep)
 {
 	ns_dev *card;
 	vc_map *vc;
@@ -1704,8 +1703,10 @@ static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb)
 		scq = card->scq0;
 	}
 
-	if (push_scqe(card, vc, scq, &scqe, skb) != 0) {
+	if (push_scqe(card, vc, scq, &scqe, skb, may_sleep) != 0) {
 		atomic_inc(&vcc->stats->tx_err);
+		dma_unmap_single(&card->pcidev->dev, NS_PRV_DMA(skb), skb->len,
+				 DMA_TO_DEVICE);
 		dev_kfree_skb_any(skb);
 		return -EIO;
 	}
@@ -1714,8 +1715,18 @@ static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb)
 	return 0;
 }
 
+static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb)
+{
+	return _ns_send(vcc, skb, true);
+}
+
+static int ns_send_bh(struct atm_vcc *vcc, struct sk_buff *skb)
+{
+	return _ns_send(vcc, skb, false);
+}
+
 static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd,
-		     struct sk_buff *skb)
+		     struct sk_buff *skb, bool may_sleep)
 {
 	unsigned long flags;
 	ns_scqe tsr;
@@ -1726,7 +1737,7 @@ static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd,
 
 	spin_lock_irqsave(&scq->lock, flags);
 	while (scq->tail == scq->next) {
-		if (in_interrupt()) {
+		if (!may_sleep) {
 			spin_unlock_irqrestore(&scq->lock, flags);
 			printk("nicstar%d: Error pushing TBD.\n", card->index);
 			return 1;
@@ -1771,7 +1782,7 @@ static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd,
 		int has_run = 0;
 
 		while (scq->tail == scq->next) {
-			if (in_interrupt()) {
+			if (!may_sleep) {
 				data = scq_virt_to_bus(scq, scq->next);
 				ns_write_sram(card, scq->scd, &data, 1);
 				spin_unlock_irqrestore(&scq->lock, flags);
diff --git a/drivers/atm/nicstarmac.c b/drivers/atm/nicstarmac.c
index e0dda9062e6b..791f69a07ddf 100644
--- a/drivers/atm/nicstarmac.c
+++ b/drivers/atm/nicstarmac.c
@@ -14,11 +14,6 @@ typedef void __iomem *virt_addr_t;
 
 #define CYCLE_DELAY 5
 
-/*
-   This was the original definition
-#define osp_MicroDelay(microsec) \
-    do { int _i = 4*microsec; while (--_i > 0) { __SLOW_DOWN_IO; }} while (0)
-*/
 #define osp_MicroDelay(microsec) {unsigned long useconds = (microsec); \
                                   udelay((useconds));}
 /*
diff --git a/drivers/atm/solos-pci.c b/drivers/atm/solos-pci.c
index c32f7dd9879a..d3c30a28c410 100644
--- a/drivers/atm/solos-pci.c
+++ b/drivers/atm/solos-pci.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Driver for the Solos PCI ADSL2+ card, designed to support Linux by
- *  Traverse Technologies -- http://www.traverse.com.au/
+ *  Traverse Technologies -- https://www.traverse.com.au/
  *  Xrio Limited          -- http://www.xrio.com/
  *
  * Copyright © 2008 Traverse Technologies
@@ -449,9 +449,9 @@ static ssize_t console_show(struct device *dev, struct device_attribute *attr,
 	struct sk_buff *skb;
 	unsigned int len;
 
-	spin_lock(&card->cli_queue_lock);
+	spin_lock_bh(&card->cli_queue_lock);
 	skb = skb_dequeue(&card->cli_queue[SOLOS_CHAN(atmdev)]);
-	spin_unlock(&card->cli_queue_lock);
+	spin_unlock_bh(&card->cli_queue_lock);
 	if(skb == NULL)
 		return sprintf(buf, "No data.\n");
 
@@ -956,14 +956,14 @@ static void pclose(struct atm_vcc *vcc)
 	struct pkt_hdr *header;
 
 	/* Remove any yet-to-be-transmitted packets from the pending queue */
-	spin_lock(&card->tx_queue_lock);
+	spin_lock_bh(&card->tx_queue_lock);
 	skb_queue_walk_safe(&card->tx_queue[port], skb, tmpskb) {
 		if (SKB_CB(skb)->vcc == vcc) {
 			skb_unlink(skb, &card->tx_queue[port]);
 			solos_pop(vcc, skb);
 		}
 	}
-	spin_unlock(&card->tx_queue_lock);
+	spin_unlock_bh(&card->tx_queue_lock);
 
 	skb = alloc_skb(sizeof(*header), GFP_KERNEL);
 	if (!skb) {
@@ -1179,8 +1179,6 @@ static const struct atmdev_ops fpga_ops = {
 	.open =		popen,
 	.close =	pclose,
 	.ioctl =	NULL,
-	.getsockopt =	NULL,
-	.setsockopt =	NULL,
 	.send =		psend,
 	.send_oam =	NULL,
 	.phy_put =	NULL,
diff --git a/drivers/atm/suni.c b/drivers/atm/suni.c
index c920a8c52925..7d0fa729c2fe 100644
--- a/drivers/atm/suni.c
+++ b/drivers/atm/suni.c
@@ -21,7 +21,6 @@
 #include <linux/timer.h>
 #include <linux/init.h>
 #include <linux/capability.h>
-#include <linux/atm_suni.h>
 #include <linux/slab.h>
 #include <asm/param.h>
 #include <linux/uaccess.h>
@@ -348,7 +347,7 @@ static int suni_stop(struct atm_dev *dev)
 	for (walk = &sunis; *walk != PRIV(dev);
 	    walk = &PRIV((*walk)->dev)->next);
 	*walk = PRIV((*walk)->dev)->next;
-	if (!sunis) del_timer_sync(&poll_timer);
+	if (!sunis) timer_delete_sync(&poll_timer);
 	spin_unlock_irqrestore(&sunis_lock,flags);
 	kfree(PRIV(dev));
 
@@ -388,4 +387,5 @@ int suni_init(struct atm_dev *dev)
 
 EXPORT_SYMBOL(suni_init);
 
+MODULE_DESCRIPTION("S/UNI PHY driver");
 MODULE_LICENSE("GPL");
diff --git a/drivers/atm/uPD98401.h b/drivers/atm/uPD98401.h
deleted file mode 100644
index f766a5ef0c5d..000000000000
--- a/drivers/atm/uPD98401.h
+++ /dev/null
@@ -1,293 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* drivers/atm/uPD98401.h - NEC uPD98401 (SAR) declarations */
- 
-/* Written 1995 by Werner Almesberger, EPFL LRC */
- 
-
-#ifndef DRIVERS_ATM_uPD98401_H
-#define DRIVERS_ATM_uPD98401_H
-
-
-#define MAX_CRAM_SIZE	(1 << 18)	/* 2^18 words */
-#define RAM_INCREMENT	1024		/* check in 4 kB increments */
-
-#define uPD98401_PORTS	0x24		/* probably more ? */
-
-
-/*
- * Commands
- */
-
-#define uPD98401_OPEN_CHAN	0x20000000 /* open channel */
-#define uPD98401_CHAN_ADDR	0x0003fff8 /*	channel address */
-#define uPD98401_CHAN_ADDR_SHIFT 3
-#define uPD98401_CLOSE_CHAN	0x24000000 /* close channel */
-#define uPD98401_CHAN_RT	0x02000000 /*	RX/TX (0 TX, 1 RX) */
-#define uPD98401_DEACT_CHAN	0x28000000 /* deactivate channel */
-#define uPD98401_TX_READY	0x30000000 /* TX ready */
-#define uPD98401_ADD_BAT	0x34000000 /* add batches */
-#define uPD98401_POOL		0x000f0000 /* pool number */
-#define uPD98401_POOL_SHIFT	16
-#define uPD98401_POOL_NUMBAT	0x0000ffff /* number of batches */
-#define uPD98401_NOP		0x3f000000 /* NOP */
-#define uPD98401_IND_ACC	0x00000000 /* Indirect Access */
-#define uPD98401_IA_RW		0x10000000 /*	Read/Write (0 W, 1 R) */
-#define uPD98401_IA_B3		0x08000000 /*	Byte select, 1 enable */
-#define uPD98401_IA_B2		0x04000000
-#define uPD98401_IA_B1		0x02000000
-#define uPD98401_IA_B0		0x01000000
-#define uPD98401_IA_BALL	0x0f000000 /*   whole longword */
-#define uPD98401_IA_TGT		0x000c0000 /*	Target */
-#define uPD98401_IA_TGT_SHIFT	18
-#define uPD98401_IA_TGT_CM	0	   /*	- Control Memory */
-#define uPD98401_IA_TGT_SAR	1	   /*	- uPD98401 registers */
-#define uPD98401_IA_TGT_PHY	3	   /*   - PHY device */
-#define uPD98401_IA_ADDR	0x0003ffff
-
-/*
- * Command Register Status
- */
-
-#define uPD98401_BUSY		0x80000000 /* SAR is busy */
-#define uPD98401_LOCKED		0x40000000 /* SAR is locked by other CPU */
-
-/*
- * Indications
- */
-
-/* Normal (AAL5) Receive Indication */
-#define uPD98401_AAL5_UINFO	0xffff0000 /* user-supplied information */
-#define uPD98401_AAL5_UINFO_SHIFT 16
-#define uPD98401_AAL5_SIZE	0x0000ffff /* PDU size (in _CELLS_ !!) */
-#define uPD98401_AAL5_CHAN	0x7fff0000 /* Channel number */
-#define uPD98401_AAL5_CHAN_SHIFT	16
-#define uPD98401_AAL5_ERR	0x00008000 /* Error indication */
-#define uPD98401_AAL5_CI	0x00004000 /* Congestion Indication */
-#define uPD98401_AAL5_CLP	0x00002000 /* CLP (>= 1 cell had CLP=1) */
-#define uPD98401_AAL5_ES	0x00000f00 /* Error Status */
-#define uPD98401_AAL5_ES_SHIFT	8
-#define uPD98401_AAL5_ES_NONE	0	   /*	No error */
-#define uPD98401_AAL5_ES_FREE	1	   /*	Receiver free buf underflow */
-#define uPD98401_AAL5_ES_FIFO	2	   /*	Receiver FIFO overrun */
-#define uPD98401_AAL5_ES_TOOBIG	3	   /*	Maximum length violation */
-#define uPD98401_AAL5_ES_CRC	4	   /*	CRC error */
-#define uPD98401_AAL5_ES_ABORT	5	   /*	User abort */
-#define uPD98401_AAL5_ES_LENGTH	6	   /*   Length violation */
-#define uPD98401_AAL5_ES_T1	7	   /*	T1 error (timeout) */
-#define uPD98401_AAL5_ES_DEACT	8	   /*	Deactivated with DEACT_CHAN */
-#define uPD98401_AAL5_POOL	0x0000001f /* Free buffer pool number */
-
-/* Raw Cell Indication */
-#define uPD98401_RAW_UINFO	uPD98401_AAL5_UINFO
-#define uPD98401_RAW_UINFO_SHIFT uPD98401_AAL5_UINFO_SHIFT
-#define uPD98401_RAW_HEC	0x000000ff /* HEC */
-#define uPD98401_RAW_CHAN	uPD98401_AAL5_CHAN
-#define uPD98401_RAW_CHAN_SHIFT uPD98401_AAL5_CHAN_SHIFT
-
-/* Transmit Indication */
-#define uPD98401_TXI_CONN	0x7fff0000 /* Connection Number */
-#define uPD98401_TXI_CONN_SHIFT	16
-#define uPD98401_TXI_ACTIVE	0x00008000 /* Channel remains active */
-#define uPD98401_TXI_PQP	0x00007fff /* Packet Queue Pointer */
-
-/*
- * Directly Addressable Registers
- */
-
-#define uPD98401_GMR	0x00	/* General Mode Register */
-#define uPD98401_GSR	0x01	/* General Status Register */
-#define uPD98401_IMR	0x02	/* Interrupt Mask Register */
-#define uPD98401_RQU	0x03	/* Receive Queue Underrun */
-#define uPD98401_RQA	0x04	/* Receive Queue Alert */
-#define uPD98401_ADDR	0x05	/* Last Burst Address */
-#define uPD98401_VER	0x06	/* Version Number */
-#define uPD98401_SWR	0x07	/* Software Reset */
-#define uPD98401_CMR	0x08	/* Command Register */
-#define uPD98401_CMR_L	0x09	/* Command Register and Lock/Unlock */
-#define uPD98401_CER	0x0a	/* Command Extension Register */
-#define uPD98401_CER_L	0x0b	/* Command Ext Reg and Lock/Unlock */
-
-#define uPD98401_MSH(n) (0x10+(n))	/* Mailbox n Start Address High */
-#define uPD98401_MSL(n) (0x14+(n))	/* Mailbox n Start Address High */
-#define uPD98401_MBA(n) (0x18+(n))	/* Mailbox n Bottom Address */
-#define uPD98401_MTA(n) (0x1c+(n))	/* Mailbox n Tail Address */
-#define uPD98401_MWA(n) (0x20+(n))	/* Mailbox n Write Address */
-
-/* GMR is at 0x00 */
-#define uPD98401_GMR_ONE	0x80000000 /* Must be set to one */
-#define uPD98401_GMR_SLM	0x40000000 /* Address mode (0 word, 1 byte) */
-#define uPD98401_GMR_CPE	0x00008000 /* Control Memory Parity Enable */
-#define uPD98401_GMR_LP		0x00004000 /* Loopback */
-#define uPD98401_GMR_WA		0x00002000 /* Early Bus Write Abort/RDY */
-#define uPD98401_GMR_RA		0x00001000 /* Early Read Abort/RDY */
-#define uPD98401_GMR_SZ		0x00000f00 /* Burst Size Enable */
-#define uPD98401_BURST16	0x00000800 /*	16-word burst */
-#define uPD98401_BURST8		0x00000400 /*	 8-word burst */
-#define uPD98401_BURST4		0x00000200 /*	 4-word burst */
-#define uPD98401_BURST2		0x00000100 /*	 2-word burst */
-#define uPD98401_GMR_AD		0x00000080 /* Address (burst resolution) Disable */
-#define uPD98401_GMR_BO		0x00000040 /* Byte Order (0 little, 1 big) */
-#define uPD98401_GMR_PM		0x00000020 /* Bus Parity Mode (0 byte, 1 word)*/
-#define uPD98401_GMR_PC		0x00000010 /* Bus Parity Control (0even,1odd) */
-#define uPD98401_GMR_BPE	0x00000008 /* Bus Parity Enable */
-#define uPD98401_GMR_DR		0x00000004 /* Receive Drop Mode (0drop,1don't)*/
-#define uPD98401_GMR_SE		0x00000002 /* Shapers Enable */
-#define uPD98401_GMR_RE		0x00000001 /* Receiver Enable */
-
-/* GSR is at 0x01, IMR is at 0x02 */
-#define uPD98401_INT_PI		0x80000000 /* PHY interrupt */
-#define uPD98401_INT_RQA	0x40000000 /* Receive Queue Alert */
-#define uPD98401_INT_RQU	0x20000000 /* Receive Queue Underrun */
-#define uPD98401_INT_RD		0x10000000 /* Receiver Deactivated */
-#define uPD98401_INT_SPE	0x08000000 /* System Parity Error */
-#define uPD98401_INT_CPE	0x04000000 /* Control Memory Parity Error */
-#define uPD98401_INT_SBE	0x02000000 /* System Bus Error */
-#define uPD98401_INT_IND	0x01000000 /* Initialization Done */
-#define uPD98401_INT_RCR	0x0000ff00 /* Raw Cell Received */
-#define uPD98401_INT_RCR_SHIFT	8
-#define uPD98401_INT_MF		0x000000f0 /* Mailbox Full */
-#define uPD98401_INT_MF_SHIFT	4
-#define uPD98401_INT_MM		0x0000000f /* Mailbox Modified */
-
-/* VER is at 0x06 */
-#define uPD98401_MAJOR		0x0000ff00 /* Major revision */
-#define uPD98401_MAJOR_SHIFT	8
-#define uPD98401_MINOR		0x000000ff /* Minor revision */
-
-/*
- * Indirectly Addressable Registers
- */
-
-#define uPD98401_IM(n)	(0x40000+(n))	/* Scheduler n I and M */
-#define uPD98401_X(n)	(0x40010+(n))	/* Scheduler n X */
-#define uPD98401_Y(n)	(0x40020+(n))	/* Scheduler n Y */
-#define uPD98401_PC(n)	(0x40030+(n))	/* Scheduler n P, C, p and c */
-#define uPD98401_PS(n)	(0x40040+(n))	/* Scheduler n priority and status */
-
-/* IM contents */
-#define uPD98401_IM_I		0xff000000 /* I */
-#define uPD98401_IM_I_SHIFT	24
-#define uPD98401_IM_M		0x00ffffff /* M */
-
-/* PC contents */
-#define uPD98401_PC_P		0xff000000 /* P */
-#define uPD98401_PC_P_SHIFT	24
-#define uPD98401_PC_C		0x00ff0000 /* C */
-#define uPD98401_PC_C_SHIFT	16
-#define uPD98401_PC_p		0x0000ff00 /* p */
-#define uPD98401_PC_p_SHIFT	8
-#define uPD98401_PC_c		0x000000ff /* c */
-
-/* PS contents */
-#define uPD98401_PS_PRIO	0xf0	/* Priority level (0 high, 15 low) */
-#define uPD98401_PS_PRIO_SHIFT	4
-#define uPD98401_PS_S		0x08	/* Scan - must be 0 (internal) */
-#define uPD98401_PS_R		0x04	/* Round Robin (internal) */
-#define uPD98401_PS_A		0x02	/* Active (internal) */
-#define uPD98401_PS_E		0x01	/* Enabled */
-
-#define uPD98401_TOS	0x40100	/* Top of Stack Control Memory Address */
-#define uPD98401_SMA	0x40200	/* Shapers Control Memory Start Address */
-#define uPD98401_PMA	0x40201	/* Receive Pool Control Memory Start Address */
-#define uPD98401_T1R	0x40300	/* T1 Register */
-#define uPD98401_VRR	0x40301	/* VPI/VCI Reduction Register/Recv. Shutdown */
-#define uPD98401_TSR	0x40302	/* Time-Stamp Register */
-
-/* VRR is at 0x40301 */
-#define uPD98401_VRR_SDM	0x80000000 /* Shutdown Mode */
-#define uPD98401_VRR_SHIFT	0x000f0000 /* VPI/VCI Shift */
-#define uPD98401_VRR_SHIFT_SHIFT 16
-#define uPD98401_VRR_MASK	0x0000ffff /* VPI/VCI mask */
-
-/*
- * TX packet descriptor
- */
-
-#define uPD98401_TXPD_SIZE	16	   /* descriptor size (in bytes) */
-
-#define uPD98401_TXPD_V		0x80000000 /* Valid bit */
-#define uPD98401_TXPD_DP	0x40000000 /* Descriptor (1) or Pointer (0) */
-#define uPD98401_TXPD_SM	0x20000000 /* Single (1) or Multiple (0) */
-#define uPD98401_TXPD_CLPM	0x18000000 /* CLP mode */
-#define uPD98401_CLPM_0		0	   /*	00 CLP = 0 */
-#define uPD98401_CLPM_1		3	   /*	11 CLP = 1 */
-#define uPD98401_CLPM_LAST	1	   /*	01 CLP unless last cell */
-#define uPD98401_TXPD_CLPM_SHIFT 27
-#define uPD98401_TXPD_PTI	0x07000000 /* PTI pattern */
-#define uPD98401_TXPD_PTI_SHIFT	24
-#define uPD98401_TXPD_GFC	0x00f00000 /* GFC pattern */
-#define uPD98401_TXPD_GFC_SHIFT	20
-#define uPD98401_TXPD_C10	0x00040000 /* insert CRC-10 */
-#define uPD98401_TXPD_AAL5	0x00020000 /* AAL5 processing */
-#define uPD98401_TXPD_MB	0x00010000 /* TX mailbox number */
-#define uPD98401_TXPD_UU	0x0000ff00 /* CPCS-UU */
-#define uPD98401_TXPD_UU_SHIFT	8
-#define uPD98401_TXPD_CPI	0x000000ff /* CPI */
-
-/*
- * TX buffer descriptor
- */
-
-#define uPD98401_TXBD_SIZE	8	   /* descriptor size (in bytes) */
-
-#define uPD98401_TXBD_LAST	0x80000000 /* last buffer in packet */
-
-/*
- * TX VC table
- */
-
-/* 1st word has the same structure as in a TX packet descriptor */
-#define uPD98401_TXVC_L		0x80000000 /* last buffer */
-#define uPD98401_TXVC_SHP	0x0f000000 /* shaper number */
-#define uPD98401_TXVC_SHP_SHIFT	24
-#define uPD98401_TXVC_VPI	0x00ff0000 /* VPI */
-#define uPD98401_TXVC_VPI_SHIFT	16
-#define uPD98401_TXVC_VCI	0x0000ffff /* VCI */
-#define uPD98401_TXVC_QRP	6	   /* Queue Read Pointer is in word 6 */
-
-/*
- * RX free buffer pools descriptor
- */
-
-#define uPD98401_RXFP_ALERT	0x70000000 /* low water mark */
-#define uPD98401_RXFP_ALERT_SHIFT 28
-#define uPD98401_RXFP_BFSZ	0x0f000000 /* buffer size, 64*2^n */
-#define uPD98401_RXFP_BFSZ_SHIFT 24
-#define uPD98401_RXFP_BTSZ	0x00ff0000 /* batch size, n+1 */
-#define uPD98401_RXFP_BTSZ_SHIFT 16
-#define uPD98401_RXFP_REMAIN	0x0000ffff /* remaining batches in pool */
-
-/*
- * RX VC table
- */
-
-#define uPD98401_RXVC_BTSZ	0xff000000 /* remaining free buffers in batch */
-#define uPD98401_RXVC_BTSZ_SHIFT 24
-#define uPD98401_RXVC_MB	0x00200000 /* RX mailbox number */
-#define uPD98401_RXVC_POOL	0x001f0000 /* free buffer pool number */
-#define uPD98401_RXVC_POOL_SHIFT 16
-#define uPD98401_RXVC_UINFO	0x0000ffff /* user-supplied information */
-#define uPD98401_RXVC_T1	0xffff0000 /* T1 timestamp */
-#define uPD98401_RXVC_T1_SHIFT	16
-#define uPD98401_RXVC_PR	0x00008000 /* Packet Reception, 1 if busy */
-#define uPD98401_RXVC_DR	0x00004000 /* FIFO Drop */
-#define uPD98401_RXVC_OD	0x00001000 /* Drop OAM cells */
-#define uPD98401_RXVC_AR	0x00000800 /* AAL5 or raw cell; 1 if AAL5 */
-#define uPD98401_RXVC_MAXSEG	0x000007ff /* max number of segments per PDU */
-#define uPD98401_RXVC_REM	0xfffe0000 /* remaining words in curr buffer */
-#define uPD98401_RXVC_REM_SHIFT	17
-#define uPD98401_RXVC_CLP	0x00010000 /* CLP received */
-#define uPD98401_RXVC_BFA	0x00008000 /* Buffer Assigned */
-#define uPD98401_RXVC_BTA	0x00004000 /* Batch Assigned */
-#define uPD98401_RXVC_CI	0x00002000 /* Congestion Indication */
-#define uPD98401_RXVC_DD	0x00001000 /* Dropping incoming cells */
-#define uPD98401_RXVC_DP	0x00000800 /* like PR ? */
-#define uPD98401_RXVC_CURSEG	0x000007ff /* Current Segment count */
-
-/*
- * RX lookup table
- */
-
-#define uPD98401_RXLT_ENBL	0x8000	   /* Enable */
-
-#endif
diff --git a/drivers/atm/uPD98402.c b/drivers/atm/uPD98402.c
deleted file mode 100644
index 7850758b5bb8..000000000000
--- a/drivers/atm/uPD98402.c
+++ /dev/null
@@ -1,266 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/* drivers/atm/uPD98402.c - NEC uPD98402 (PHY) declarations */
- 
-/* Written 1995-2000 by Werner Almesberger, EPFL LRC/ICA */
- 
-
-#include <linux/module.h>
-#include <linux/mm.h>
-#include <linux/errno.h>
-#include <linux/atmdev.h>
-#include <linux/sonet.h>
-#include <linux/init.h>
-#include <linux/slab.h>
-#include <linux/uaccess.h>
-#include <linux/atomic.h>
-
-#include "uPD98402.h"
-
-
-#if 0
-#define DPRINTK(format,args...) printk(KERN_DEBUG format,##args)
-#else
-#define DPRINTK(format,args...)
-#endif
-
-
-struct uPD98402_priv {
-	struct k_sonet_stats sonet_stats;/* link diagnostics */
-	unsigned char framing;		/* SONET/SDH framing */
-	int loop_mode;			/* loopback mode */
-	spinlock_t lock;
-};
-
-
-#define PRIV(dev) ((struct uPD98402_priv *) dev->phy_data)
-
-#define PUT(val,reg) dev->ops->phy_put(dev,val,uPD98402_##reg)
-#define GET(reg) dev->ops->phy_get(dev,uPD98402_##reg)
-
-
-static int fetch_stats(struct atm_dev *dev,struct sonet_stats __user *arg,int zero)
-{
-	struct sonet_stats tmp;
- 	int error = 0;
-
-	atomic_add(GET(HECCT),&PRIV(dev)->sonet_stats.uncorr_hcs);
-	sonet_copy_stats(&PRIV(dev)->sonet_stats,&tmp);
-	if (arg) error = copy_to_user(arg,&tmp,sizeof(tmp));
-	if (zero && !error) {
-		/* unused fields are reported as -1, but we must not "adjust"
-		   them */
-		tmp.corr_hcs = tmp.tx_cells = tmp.rx_cells = 0;
-		sonet_subtract_stats(&PRIV(dev)->sonet_stats,&tmp);
-	}
-	return error ? -EFAULT : 0;
-}
-
-
-static int set_framing(struct atm_dev *dev,unsigned char framing)
-{
-	static const unsigned char sonet[] = { 1,2,3,0 };
-	static const unsigned char sdh[] = { 1,0,0,2 };
-	const char *set;
-	unsigned long flags;
- 
-	switch (framing) {
-		case SONET_FRAME_SONET:
-			set = sonet;
-			break;
-		case SONET_FRAME_SDH:
-			set = sdh;
-			break;
-		default:
-			return -EINVAL;
-	}
-	spin_lock_irqsave(&PRIV(dev)->lock, flags);
-	PUT(set[0],C11T);
-	PUT(set[1],C12T);
-	PUT(set[2],C13T);
-	PUT((GET(MDR) & ~uPD98402_MDR_SS_MASK) | (set[3] <<
-	    uPD98402_MDR_SS_SHIFT),MDR);
-	spin_unlock_irqrestore(&PRIV(dev)->lock, flags);
-	return 0;
-}
-
-
-static int get_sense(struct atm_dev *dev,u8 __user *arg)
-{
-	unsigned long flags;
-	unsigned char s[3];
-
-	spin_lock_irqsave(&PRIV(dev)->lock, flags);
-	s[0] = GET(C11R);
-	s[1] = GET(C12R);
-	s[2] = GET(C13R);
-	spin_unlock_irqrestore(&PRIV(dev)->lock, flags);
-	return (put_user(s[0], arg) || put_user(s[1], arg+1) ||
-	    put_user(s[2], arg+2) || put_user(0xff, arg+3) ||
-	    put_user(0xff, arg+4) || put_user(0xff, arg+5)) ? -EFAULT : 0;
-}
-
-
-static int set_loopback(struct atm_dev *dev,int mode)
-{
-	unsigned char mode_reg;
-
-	mode_reg = GET(MDR) & ~(uPD98402_MDR_TPLP | uPD98402_MDR_ALP |
-	    uPD98402_MDR_RPLP);
-	switch (__ATM_LM_XTLOC(mode)) {
-		case __ATM_LM_NONE:
-			break;
-		case __ATM_LM_PHY:
-			mode_reg |= uPD98402_MDR_TPLP;
-			break;
-		case __ATM_LM_ATM:
-			mode_reg |= uPD98402_MDR_ALP;
-			break;
-		default:
-			return -EINVAL;
-	}
-	switch (__ATM_LM_XTRMT(mode)) {
-		case __ATM_LM_NONE:
-			break;
-		case __ATM_LM_PHY:
-			mode_reg |= uPD98402_MDR_RPLP;
-			break;
-		default:
-			return -EINVAL;
-	}
-	PUT(mode_reg,MDR);
-	PRIV(dev)->loop_mode = mode;
-	return 0;
-}
-
-
-static int uPD98402_ioctl(struct atm_dev *dev,unsigned int cmd,void __user *arg)
-{
-	switch (cmd) {
-
-		case SONET_GETSTATZ:
-                case SONET_GETSTAT:
-			return fetch_stats(dev,arg, cmd == SONET_GETSTATZ);
-		case SONET_SETFRAMING:
-			return set_framing(dev, (int)(unsigned long)arg);
-		case SONET_GETFRAMING:
-			return put_user(PRIV(dev)->framing,(int __user *)arg) ?
-			    -EFAULT : 0;
-		case SONET_GETFRSENSE:
-			return get_sense(dev,arg);
-		case ATM_SETLOOP:
-			return set_loopback(dev, (int)(unsigned long)arg);
-		case ATM_GETLOOP:
-			return put_user(PRIV(dev)->loop_mode,(int __user *)arg) ?
-			    -EFAULT : 0;
-		case ATM_QUERYLOOP:
-			return put_user(ATM_LM_LOC_PHY | ATM_LM_LOC_ATM |
-			    ATM_LM_RMT_PHY,(int __user *)arg) ? -EFAULT : 0;
-		default:
-			return -ENOIOCTLCMD;
-	}
-}
-
-
-#define ADD_LIMITED(s,v) \
-    { atomic_add(GET(v),&PRIV(dev)->sonet_stats.s); \
-    if (atomic_read(&PRIV(dev)->sonet_stats.s) < 0) \
-	atomic_set(&PRIV(dev)->sonet_stats.s,INT_MAX); }
-
-
-static void stat_event(struct atm_dev *dev)
-{
-	unsigned char events;
-
-	events = GET(PCR);
-	if (events & uPD98402_PFM_PFEB) ADD_LIMITED(path_febe,PFECB);
-	if (events & uPD98402_PFM_LFEB) ADD_LIMITED(line_febe,LECCT);
-	if (events & uPD98402_PFM_B3E) ADD_LIMITED(path_bip,B3ECT);
-	if (events & uPD98402_PFM_B2E) ADD_LIMITED(line_bip,B2ECT);
-	if (events & uPD98402_PFM_B1E) ADD_LIMITED(section_bip,B1ECT);
-}
-
-
-#undef ADD_LIMITED
-
-
-static void uPD98402_int(struct atm_dev *dev)
-{
-	static unsigned long silence = 0;
-	unsigned char reason;
-
-	while ((reason = GET(PICR))) {
-		if (reason & uPD98402_INT_LOS)
-			printk(KERN_NOTICE "%s(itf %d): signal lost\n",
-			    dev->type,dev->number);
-		if (reason & uPD98402_INT_PFM) stat_event(dev);
-		if (reason & uPD98402_INT_PCO) {
-			(void) GET(PCOCR); /* clear interrupt cause */
-			atomic_add(GET(HECCT),
-			    &PRIV(dev)->sonet_stats.uncorr_hcs);
-		}
-		if ((reason & uPD98402_INT_RFO) && 
-		    (time_after(jiffies, silence) || silence == 0)) {
-			printk(KERN_WARNING "%s(itf %d): uPD98402 receive "
-			    "FIFO overflow\n",dev->type,dev->number);
-			silence = (jiffies+HZ/2)|1;
-		}
-	}
-}
-
-
-static int uPD98402_start(struct atm_dev *dev)
-{
-	DPRINTK("phy_start\n");
-	if (!(dev->dev_data = kmalloc(sizeof(struct uPD98402_priv),GFP_KERNEL)))
-		return -ENOMEM;
-	spin_lock_init(&PRIV(dev)->lock);
-	memset(&PRIV(dev)->sonet_stats,0,sizeof(struct k_sonet_stats));
-	(void) GET(PCR); /* clear performance events */
-	PUT(uPD98402_PFM_FJ,PCMR); /* ignore frequency adj */
-	(void) GET(PCOCR); /* clear overflows */
-	PUT(~uPD98402_PCO_HECC,PCOMR);
-	(void) GET(PICR); /* clear interrupts */
-	PUT(~(uPD98402_INT_PFM | uPD98402_INT_ALM | uPD98402_INT_RFO |
-	  uPD98402_INT_LOS),PIMR); /* enable them */
-	(void) fetch_stats(dev,NULL,1); /* clear kernel counters */
-	atomic_set(&PRIV(dev)->sonet_stats.corr_hcs,-1);
-	atomic_set(&PRIV(dev)->sonet_stats.tx_cells,-1);
-	atomic_set(&PRIV(dev)->sonet_stats.rx_cells,-1);
-	return 0;
-}
-
-
-static int uPD98402_stop(struct atm_dev *dev)
-{
-	/* let SAR driver worry about stopping interrupts */
-	kfree(PRIV(dev));
-	return 0;
-}
-
-
-static const struct atmphy_ops uPD98402_ops = {
-	.start		= uPD98402_start,
-	.ioctl		= uPD98402_ioctl,
-	.interrupt	= uPD98402_int,
-	.stop		= uPD98402_stop,
-};
-
-
-int uPD98402_init(struct atm_dev *dev)
-{
-DPRINTK("phy_init\n");
-	dev->phy = &uPD98402_ops;
-	return 0;
-}
-
-
-MODULE_LICENSE("GPL");
-
-EXPORT_SYMBOL(uPD98402_init);
-
-static __init int uPD98402_module_init(void)
-{
-	return 0;
-}
-module_init(uPD98402_module_init);
-/* module_exit not defined so not unloadable */
diff --git a/drivers/atm/uPD98402.h b/drivers/atm/uPD98402.h
deleted file mode 100644
index 437cfaa20c96..000000000000
--- a/drivers/atm/uPD98402.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* drivers/atm/uPD98402.h - NEC uPD98402 (PHY) declarations */
- 
-/* Written 1995 by Werner Almesberger, EPFL LRC */
-
-
-#ifndef DRIVERS_ATM_uPD98402_H
-#define DRIVERS_ATM_uPD98402_H
-
-/*
- * Registers
- */
-
-#define uPD98402_CMR		0x00	/* Command Register */
-#define uPD98402_MDR		0x01	/* Mode Register */
-#define uPD98402_PICR		0x02	/* PHY Interrupt Cause Register */
-#define uPD98402_PIMR		0x03	/* PHY Interrupt Mask Register */
-#define uPD98402_ACR		0x04	/* Alarm Cause Register */
-#define uPD98402_ACMR		0x05	/* Alarm Cause Mask Register */
-#define uPD98402_PCR		0x06	/* Performance Cause Register */
-#define uPD98402_PCMR		0x07	/* Performance Cause Mask Register */
-#define uPD98402_IACM		0x08	/* Internal Alarm Cause Mask Register */
-#define uPD98402_B1ECT		0x09	/* B1 Error Count Register */
-#define uPD98402_B2ECT		0x0a	/* B2 Error Count Register */
-#define uPD98402_B3ECT		0x0b	/* B3 Error Count Regster */
-#define uPD98402_PFECB		0x0c	/* Path FEBE Count Register */
-#define uPD98402_LECCT		0x0d	/* Line FEBE Count Register */
-#define uPD98402_HECCT		0x0e	/* HEC Error Count Register */
-#define uPD98402_FJCT		0x0f	/* Frequence Justification Count Reg */
-#define uPD98402_PCOCR		0x10	/* Perf. Counter Overflow Cause Reg */
-#define uPD98402_PCOMR		0x11	/* Perf. Counter Overflow Mask Reg */
-#define uPD98402_C11T		0x20	/* C11T Data Register */
-#define uPD98402_C12T		0x21	/* C12T Data Register */
-#define uPD98402_C13T		0x22	/* C13T Data Register */
-#define uPD98402_F1T		0x23	/* F1T Data Register */
-#define uPD98402_K2T		0x25	/* K2T Data Register */
-#define uPD98402_C2T		0x26	/* C2T Data Register */
-#define uPD98402_F2T		0x27	/* F2T Data Register */
-#define uPD98402_C11R		0x30	/* C11T Data Register */
-#define uPD98402_C12R		0x31	/* C12T Data Register */
-#define uPD98402_C13R		0x32	/* C13T Data Register */
-#define uPD98402_F1R		0x33	/* F1T Data Register */
-#define uPD98402_K2R		0x35	/* K2T Data Register */
-#define uPD98402_C2R		0x36	/* C2T Data Register */
-#define uPD98402_F2R		0x37	/* F2T Data Register */
-
-/* CMR is at 0x00 */
-#define uPD98402_CMR_PFRF	0x01	/* Send path FERF */
-#define uPD98402_CMR_LFRF	0x02	/* Send line FERF */
-#define uPD98402_CMR_PAIS	0x04	/* Send path AIS */
-#define uPD98402_CMR_LAIS	0x08	/* Send line AIS */
-
-/* MDR is at 0x01 */
-#define uPD98402_MDR_ALP	0x01	/* ATM layer loopback */
-#define uPD98402_MDR_TPLP	0x02	/* PMD loopback, to host */
-#define uPD98402_MDR_RPLP	0x04	/* PMD loopback, to network */
-#define uPD98402_MDR_SS0	0x08	/* SS0 */
-#define uPD98402_MDR_SS1	0x10	/* SS1 */
-#define uPD98402_MDR_SS_MASK	0x18	/* mask */
-#define uPD98402_MDR_SS_SHIFT	3	/* shift */
-#define uPD98402_MDR_HEC	0x20	/* disable HEC inbound processing */
-#define uPD98402_MDR_FSR	0x40	/* disable frame scrambler */
-#define uPD98402_MDR_CSR	0x80	/* disable cell scrambler */
-
-/* PICR is at 0x02, PIMR is at 0x03 */
-#define uPD98402_INT_PFM	0x01	/* performance counter has changed */
-#define uPD98402_INT_ALM	0x02	/* line fault */
-#define uPD98402_INT_RFO	0x04	/* receive FIFO overflow */
-#define uPD98402_INT_PCO	0x08	/* performance counter overflow */
-#define uPD98402_INT_OTD	0x20	/* OTD has occurred */
-#define uPD98402_INT_LOS	0x40	/* Loss Of Signal */
-#define uPD98402_INT_LOF	0x80	/* Loss Of Frame */
-
-/* ACR is as 0x04, ACMR is at 0x05 */
-#define uPD98402_ALM_PFRF	0x01	/* path FERF */
-#define uPD98402_ALM_LFRF	0x02	/* line FERF */
-#define uPD98402_ALM_PAIS	0x04	/* path AIS */
-#define uPD98402_ALM_LAIS	0x08	/* line AIS */
-#define uPD98402_ALM_LOD	0x10	/* loss of delineation */
-#define uPD98402_ALM_LOP	0x20	/* loss of pointer */
-#define uPD98402_ALM_OOF	0x40	/* out of frame */
-
-/* PCR is at 0x06, PCMR is at 0x07 */
-#define uPD98402_PFM_PFEB	0x01	/* path FEBE */
-#define uPD98402_PFM_LFEB	0x02	/* line FEBE */
-#define uPD98402_PFM_B3E	0x04	/* B3 error */
-#define uPD98402_PFM_B2E	0x08	/* B2 error */
-#define uPD98402_PFM_B1E	0x10	/* B1 error */
-#define uPD98402_PFM_FJ		0x20	/* frequency justification */
-
-/* IACM is at 0x08 */
-#define uPD98402_IACM_PFRF	0x01	/* don't generate path FERF */
-#define uPD98402_IACM_LFRF	0x02	/* don't generate line FERF */
-
-/* PCOCR is at 0x010, PCOMR is at 0x11 */
-#define uPD98402_PCO_B1EC	0x01	/* B1ECT overflow */
-#define uPD98402_PCO_B2EC	0x02	/* B2ECT overflow */
-#define uPD98402_PCO_B3EC	0x04	/* B3ECT overflow */
-#define uPD98402_PCO_PFBC	0x08	/* PFEBC overflow */
-#define uPD98402_PCO_LFBC	0x10	/* LFEVC overflow */
-#define uPD98402_PCO_HECC	0x20	/* HECCT overflow */
-#define uPD98402_PCO_FJC	0x40	/* FJCT overflow */
-
-
-int uPD98402_init(struct atm_dev *dev);
-
-#endif
diff --git a/drivers/atm/zatm.c b/drivers/atm/zatm.c
deleted file mode 100644
index 57f97b95a453..000000000000
--- a/drivers/atm/zatm.c
+++ /dev/null
@@ -1,1668 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/* drivers/atm/zatm.c - ZeitNet ZN122x device driver */
- 
-/* Written 1995-2000 by Werner Almesberger, EPFL LRC/ICA */
-
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/pci.h>
-#include <linux/errno.h>
-#include <linux/atm.h>
-#include <linux/atmdev.h>
-#include <linux/sonet.h>
-#include <linux/skbuff.h>
-#include <linux/netdevice.h>
-#include <linux/delay.h>
-#include <linux/uio.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/dma-mapping.h>
-#include <linux/atm_zatm.h>
-#include <linux/capability.h>
-#include <linux/bitops.h>
-#include <linux/wait.h>
-#include <linux/slab.h>
-#include <asm/byteorder.h>
-#include <asm/string.h>
-#include <asm/io.h>
-#include <linux/atomic.h>
-#include <linux/uaccess.h>
-#include <linux/nospec.h>
-
-#include "uPD98401.h"
-#include "uPD98402.h"
-#include "zeprom.h"
-#include "zatm.h"
-
-
-/*
- * TODO:
- *
- * Minor features
- *  - support 64 kB SDUs (will have to use multibuffer batches then :-( )
- *  - proper use of CDV, credit = max(1,CDVT*PCR)
- *  - AAL0
- *  - better receive timestamps
- *  - OAM
- */
-
-#define ZATM_COPPER	1
-
-#if 0
-#define DPRINTK(format,args...) printk(KERN_DEBUG format,##args)
-#else
-#define DPRINTK(format,args...)
-#endif
-
-#ifndef CONFIG_ATM_ZATM_DEBUG
-
-
-#define NULLCHECK(x)
-
-#define EVENT(s,a,b)
-
-
-static void event_dump(void)
-{
-}
-
-
-#else
-
-
-/* 
- * NULL pointer checking
- */
-
-#define NULLCHECK(x) \
-  if ((unsigned long) (x) < 0x30) printk(KERN_CRIT #x "==0x%x\n", (int) (x))
-
-/*
- * Very extensive activity logging. Greatly improves bug detection speed but
- * costs a few Mbps if enabled.
- */
-
-#define EV 64
-
-static const char *ev[EV];
-static unsigned long ev_a[EV],ev_b[EV];
-static int ec = 0;
-
-
-static void EVENT(const char *s,unsigned long a,unsigned long b)
-{
-	ev[ec] = s; 
-	ev_a[ec] = a;
-	ev_b[ec] = b;
-	ec = (ec+1) % EV;
-}
-
-
-static void event_dump(void)
-{
-	int n,i;
-
-	printk(KERN_NOTICE "----- event dump follows -----\n");
-	for (n = 0; n < EV; n++) {
-		i = (ec+n) % EV;
-		printk(KERN_NOTICE);
-		printk(ev[i] ? ev[i] : "(null)",ev_a[i],ev_b[i]);
-	}
-	printk(KERN_NOTICE "----- event dump ends here -----\n");
-}
-
-
-#endif /* CONFIG_ATM_ZATM_DEBUG */
-
-
-#define RING_BUSY	1	/* indication from do_tx that PDU has to be
-				   backlogged */
-
-static struct atm_dev *zatm_boards = NULL;
-static unsigned long dummy[2] = {0,0};
-
-
-#define zin_n(r) inl(zatm_dev->base+r*4)
-#define zin(r) inl(zatm_dev->base+uPD98401_##r*4)
-#define zout(v,r) outl(v,zatm_dev->base+uPD98401_##r*4)
-#define zwait() do {} while (zin(CMR) & uPD98401_BUSY)
-
-/* RX0, RX1, TX0, TX1 */
-static const int mbx_entries[NR_MBX] = { 1024,1024,1024,1024 };
-static const int mbx_esize[NR_MBX] = { 16,16,4,4 }; /* entry size in bytes */
-
-#define MBX_SIZE(i) (mbx_entries[i]*mbx_esize[i])
-
-
-/*-------------------------------- utilities --------------------------------*/
-
-
-static void zpokel(struct zatm_dev *zatm_dev,u32 value,u32 addr)
-{
-	zwait();
-	zout(value,CER);
-	zout(uPD98401_IND_ACC | uPD98401_IA_BALL |
-	    (uPD98401_IA_TGT_CM << uPD98401_IA_TGT_SHIFT) | addr,CMR);
-}
-
-
-static u32 zpeekl(struct zatm_dev *zatm_dev,u32 addr)
-{
-	zwait();
-	zout(uPD98401_IND_ACC | uPD98401_IA_BALL | uPD98401_IA_RW |
-	  (uPD98401_IA_TGT_CM << uPD98401_IA_TGT_SHIFT) | addr,CMR);
-	zwait();
-	return zin(CER);
-}
-
-
-/*------------------------------- free lists --------------------------------*/
-
-
-/*
- * Free buffer head structure:
- *   [0] pointer to buffer (for SAR)
- *   [1] buffer descr link pointer (for SAR)
- *   [2] back pointer to skb (for poll_rx)
- *   [3] data
- *   ...
- */
-
-struct rx_buffer_head {
-	u32		buffer;	/* pointer to buffer (for SAR) */
-	u32		link;	/* buffer descriptor link pointer (for SAR) */
-	struct sk_buff	*skb;	/* back pointer to skb (for poll_rx) */
-};
-
-
-static void refill_pool(struct atm_dev *dev,int pool)
-{
-	struct zatm_dev *zatm_dev;
-	struct sk_buff *skb;
-	struct rx_buffer_head *first;
-	unsigned long flags;
-	int align,offset,free,count,size;
-
-	EVENT("refill_pool\n",0,0);
-	zatm_dev = ZATM_DEV(dev);
-	size = (64 << (pool <= ZATM_AAL5_POOL_BASE ? 0 :
-	    pool-ZATM_AAL5_POOL_BASE))+sizeof(struct rx_buffer_head);
-	if (size < PAGE_SIZE) {
-		align = 32; /* for 32 byte alignment */
-		offset = sizeof(struct rx_buffer_head);
-	}
-	else {
-		align = 4096;
-		offset = zatm_dev->pool_info[pool].offset+
-		    sizeof(struct rx_buffer_head);
-	}
-	size += align;
-	spin_lock_irqsave(&zatm_dev->lock, flags);
-	free = zpeekl(zatm_dev,zatm_dev->pool_base+2*pool) &
-	    uPD98401_RXFP_REMAIN;
-	spin_unlock_irqrestore(&zatm_dev->lock, flags);
-	if (free >= zatm_dev->pool_info[pool].low_water) return;
-	EVENT("starting ... POOL: 0x%x, 0x%x\n",
-	    zpeekl(zatm_dev,zatm_dev->pool_base+2*pool),
-	    zpeekl(zatm_dev,zatm_dev->pool_base+2*pool+1));
-	EVENT("dummy: 0x%08lx, 0x%08lx\n",dummy[0],dummy[1]);
-	count = 0;
-	first = NULL;
-	while (free < zatm_dev->pool_info[pool].high_water) {
-		struct rx_buffer_head *head;
-
-		skb = alloc_skb(size,GFP_ATOMIC);
-		if (!skb) {
-			printk(KERN_WARNING DEV_LABEL "(Itf %d): got no new "
-			    "skb (%d) with %d free\n",dev->number,size,free);
-			break;
-		}
-		skb_reserve(skb,(unsigned char *) ((((unsigned long) skb->data+
-		    align+offset-1) & ~(unsigned long) (align-1))-offset)-
-		    skb->data);
-		head = (struct rx_buffer_head *) skb->data;
-		skb_reserve(skb,sizeof(struct rx_buffer_head));
-		if (!first) first = head;
-		count++;
-		head->buffer = virt_to_bus(skb->data);
-		head->link = 0;
-		head->skb = skb;
-		EVENT("enq skb 0x%08lx/0x%08lx\n",(unsigned long) skb,
-		    (unsigned long) head);
-		spin_lock_irqsave(&zatm_dev->lock, flags);
-		if (zatm_dev->last_free[pool])
-			((struct rx_buffer_head *) (zatm_dev->last_free[pool]->
-			    data))[-1].link = virt_to_bus(head);
-		zatm_dev->last_free[pool] = skb;
-		skb_queue_tail(&zatm_dev->pool[pool],skb);
-		spin_unlock_irqrestore(&zatm_dev->lock, flags);
-		free++;
-	}
-	if (first) {
-		spin_lock_irqsave(&zatm_dev->lock, flags);
-		zwait();
-		zout(virt_to_bus(first),CER);
-		zout(uPD98401_ADD_BAT | (pool << uPD98401_POOL_SHIFT) | count,
-		    CMR);
-		spin_unlock_irqrestore(&zatm_dev->lock, flags);
-		EVENT ("POOL: 0x%x, 0x%x\n",
-		    zpeekl(zatm_dev,zatm_dev->pool_base+2*pool),
-		    zpeekl(zatm_dev,zatm_dev->pool_base+2*pool+1));
-		EVENT("dummy: 0x%08lx, 0x%08lx\n",dummy[0],dummy[1]);
-	}
-}
-
-
-static void drain_free(struct atm_dev *dev,int pool)
-{
-	skb_queue_purge(&ZATM_DEV(dev)->pool[pool]);
-}
-
-
-static int pool_index(int max_pdu)
-{
-	int i;
-
-	if (max_pdu % ATM_CELL_PAYLOAD)
-		printk(KERN_ERR DEV_LABEL ": driver error in pool_index: "
-		    "max_pdu is %d\n",max_pdu);
-	if (max_pdu > 65536) return -1;
-	for (i = 0; (64 << i) < max_pdu; i++);
-	return i+ZATM_AAL5_POOL_BASE;
-}
-
-
-/* use_pool isn't reentrant */
-
-
-static void use_pool(struct atm_dev *dev,int pool)
-{
-	struct zatm_dev *zatm_dev;
-	unsigned long flags;
-	int size;
-
-	zatm_dev = ZATM_DEV(dev);
-	if (!(zatm_dev->pool_info[pool].ref_count++)) {
-		skb_queue_head_init(&zatm_dev->pool[pool]);
-		size = pool-ZATM_AAL5_POOL_BASE;
-		if (size < 0) size = 0; /* 64B... */
-		else if (size > 10) size = 10; /* ... 64kB */
-		spin_lock_irqsave(&zatm_dev->lock, flags);
-		zpokel(zatm_dev,((zatm_dev->pool_info[pool].low_water/4) <<
-		    uPD98401_RXFP_ALERT_SHIFT) |
-		    (1 << uPD98401_RXFP_BTSZ_SHIFT) |
-		    (size << uPD98401_RXFP_BFSZ_SHIFT),
-		    zatm_dev->pool_base+pool*2);
-		zpokel(zatm_dev,(unsigned long) dummy,zatm_dev->pool_base+
-		    pool*2+1);
-		spin_unlock_irqrestore(&zatm_dev->lock, flags);
-		zatm_dev->last_free[pool] = NULL;
-		refill_pool(dev,pool);
-	}
-	DPRINTK("pool %d: %d\n",pool,zatm_dev->pool_info[pool].ref_count);
-}
-
-
-static void unuse_pool(struct atm_dev *dev,int pool)
-{
-	if (!(--ZATM_DEV(dev)->pool_info[pool].ref_count))
-		drain_free(dev,pool);
-}
-
-/*----------------------------------- RX ------------------------------------*/
-
-
-#if 0
-static void exception(struct atm_vcc *vcc)
-{
-   static int count = 0;
-   struct zatm_dev *zatm_dev = ZATM_DEV(vcc->dev);
-   struct zatm_vcc *zatm_vcc = ZATM_VCC(vcc);
-   unsigned long *qrp;
-   int i;
-
-   if (count++ > 2) return;
-   for (i = 0; i < 8; i++)
-	printk("TX%d: 0x%08lx\n",i,
-	  zpeekl(zatm_dev,zatm_vcc->tx_chan*VC_SIZE/4+i));
-   for (i = 0; i < 5; i++)
-	printk("SH%d: 0x%08lx\n",i,
-	  zpeekl(zatm_dev,uPD98401_IM(zatm_vcc->shaper)+16*i));
-   qrp = (unsigned long *) zpeekl(zatm_dev,zatm_vcc->tx_chan*VC_SIZE/4+
-     uPD98401_TXVC_QRP);
-   printk("qrp=0x%08lx\n",(unsigned long) qrp);
-   for (i = 0; i < 4; i++) printk("QRP[%d]: 0x%08lx",i,qrp[i]);
-}
-#endif
-
-
-static const char *err_txt[] = {
-	"No error",
-	"RX buf underflow",
-	"RX FIFO overrun",
-	"Maximum len violation",
-	"CRC error",
-	"User abort",
-	"Length violation",
-	"T1 error",
-	"Deactivated",
-	"???",
-	"???",
-	"???",
-	"???",
-	"???",
-	"???",
-	"???"
-};
-
-
-static void poll_rx(struct atm_dev *dev,int mbx)
-{
-	struct zatm_dev *zatm_dev;
-	unsigned long pos;
-	u32 x;
-	int error;
-
-	EVENT("poll_rx\n",0,0);
-	zatm_dev = ZATM_DEV(dev);
-	pos = (zatm_dev->mbx_start[mbx] & ~0xffffUL) | zin(MTA(mbx));
-	while (x = zin(MWA(mbx)), (pos & 0xffff) != x) {
-		u32 *here;
-		struct sk_buff *skb;
-		struct atm_vcc *vcc;
-		int cells,size,chan;
-
-		EVENT("MBX: host 0x%lx, nic 0x%x\n",pos,x);
-		here = (u32 *) pos;
-		if (((pos += 16) & 0xffff) == zatm_dev->mbx_end[mbx])
-			pos = zatm_dev->mbx_start[mbx];
-		cells = here[0] & uPD98401_AAL5_SIZE;
-#if 0
-printk("RX IND: 0x%x, 0x%x, 0x%x, 0x%x\n",here[0],here[1],here[2],here[3]);
-{
-unsigned long *x;
-		printk("POOL: 0x%08x, 0x%08x\n",zpeekl(zatm_dev,
-		      zatm_dev->pool_base),
-		      zpeekl(zatm_dev,zatm_dev->pool_base+1));
-		x = (unsigned long *) here[2];
-		printk("[0..3] = 0x%08lx, 0x%08lx, 0x%08lx, 0x%08lx\n",
-		    x[0],x[1],x[2],x[3]);
-}
-#endif
-		error = 0;
-		if (here[3] & uPD98401_AAL5_ERR) {
-			error = (here[3] & uPD98401_AAL5_ES) >>
-			    uPD98401_AAL5_ES_SHIFT;
-			if (error == uPD98401_AAL5_ES_DEACT ||
-			    error == uPD98401_AAL5_ES_FREE) continue;
-		}
-EVENT("error code 0x%x/0x%x\n",(here[3] & uPD98401_AAL5_ES) >>
-  uPD98401_AAL5_ES_SHIFT,error);
-		skb = ((struct rx_buffer_head *) bus_to_virt(here[2]))->skb;
-		__net_timestamp(skb);
-#if 0
-printk("[-3..0] 0x%08lx 0x%08lx 0x%08lx 0x%08lx\n",((unsigned *) skb->data)[-3],
-  ((unsigned *) skb->data)[-2],((unsigned *) skb->data)[-1],
-  ((unsigned *) skb->data)[0]);
-#endif
-		EVENT("skb 0x%lx, here 0x%lx\n",(unsigned long) skb,
-		    (unsigned long) here);
-#if 0
-printk("dummy: 0x%08lx, 0x%08lx\n",dummy[0],dummy[1]);
-#endif
-		size = error ? 0 : ntohs(((__be16 *) skb->data)[cells*
-		    ATM_CELL_PAYLOAD/sizeof(u16)-3]);
-		EVENT("got skb 0x%lx, size %d\n",(unsigned long) skb,size);
-		chan = (here[3] & uPD98401_AAL5_CHAN) >>
-		    uPD98401_AAL5_CHAN_SHIFT;
-		if (chan < zatm_dev->chans && zatm_dev->rx_map[chan]) {
-			int pos;
-			vcc = zatm_dev->rx_map[chan];
-			pos = ZATM_VCC(vcc)->pool;
-			if (skb == zatm_dev->last_free[pos])
-				zatm_dev->last_free[pos] = NULL;
-			skb_unlink(skb, zatm_dev->pool + pos);
-		}
-		else {
-			printk(KERN_ERR DEV_LABEL "(itf %d): RX indication "
-			    "for non-existing channel\n",dev->number);
-			size = 0;
-			vcc = NULL;
-			event_dump();
-		}
-		if (error) {
-			static unsigned long silence = 0;
-			static int last_error = 0;
-
-			if (error != last_error ||
-			    time_after(jiffies, silence)  || silence == 0){
-				printk(KERN_WARNING DEV_LABEL "(itf %d): "
-				    "chan %d error %s\n",dev->number,chan,
-				    err_txt[error]);
-				last_error = error;
-				silence = (jiffies+2*HZ)|1;
-			}
-			size = 0;
-		}
-		if (size && (size > cells*ATM_CELL_PAYLOAD-ATM_AAL5_TRAILER ||
-		    size <= (cells-1)*ATM_CELL_PAYLOAD-ATM_AAL5_TRAILER)) {
-			printk(KERN_ERR DEV_LABEL "(itf %d): size %d with %d "
-			    "cells\n",dev->number,size,cells);
-			size = 0;
-			event_dump();
-		}
-		if (size > ATM_MAX_AAL5_PDU) {
-			printk(KERN_ERR DEV_LABEL "(itf %d): size too big "
-			    "(%d)\n",dev->number,size);
-			size = 0;
-			event_dump();
-		}
-		if (!size) {
-			dev_kfree_skb_irq(skb);
-			if (vcc) atomic_inc(&vcc->stats->rx_err);
-			continue;
-		}
-		if (!atm_charge(vcc,skb->truesize)) {
-			dev_kfree_skb_irq(skb);
-			continue;
-		}
-		skb->len = size;
-		ATM_SKB(skb)->vcc = vcc;
-		vcc->push(vcc,skb);
-		atomic_inc(&vcc->stats->rx);
-	}
-	zout(pos & 0xffff,MTA(mbx));
-#if 0 /* probably a stupid idea */
-	refill_pool(dev,zatm_vcc->pool);
-		/* maybe this saves us a few interrupts */
-#endif
-}
-
-
-static int open_rx_first(struct atm_vcc *vcc)
-{
-	struct zatm_dev *zatm_dev;
-	struct zatm_vcc *zatm_vcc;
-	unsigned long flags;
-	unsigned short chan;
-	int cells;
-
-	DPRINTK("open_rx_first (0x%x)\n",inb_p(0xc053));
-	zatm_dev = ZATM_DEV(vcc->dev);
-	zatm_vcc = ZATM_VCC(vcc);
-	zatm_vcc->rx_chan = 0;
-	if (vcc->qos.rxtp.traffic_class == ATM_NONE) return 0;
-	if (vcc->qos.aal == ATM_AAL5) {
-		if (vcc->qos.rxtp.max_sdu > 65464)
-			vcc->qos.rxtp.max_sdu = 65464;
-			/* fix this - we may want to receive 64kB SDUs
-			   later */
-		cells = DIV_ROUND_UP(vcc->qos.rxtp.max_sdu + ATM_AAL5_TRAILER,
-				ATM_CELL_PAYLOAD);
-		zatm_vcc->pool = pool_index(cells*ATM_CELL_PAYLOAD);
-	}
-	else {
-		cells = 1;
-		zatm_vcc->pool = ZATM_AAL0_POOL;
-	}
-	if (zatm_vcc->pool < 0) return -EMSGSIZE;
-	spin_lock_irqsave(&zatm_dev->lock, flags);
-	zwait();
-	zout(uPD98401_OPEN_CHAN,CMR);
-	zwait();
-	DPRINTK("0x%x 0x%x\n",zin(CMR),zin(CER));
-	chan = (zin(CMR) & uPD98401_CHAN_ADDR) >> uPD98401_CHAN_ADDR_SHIFT;
-	spin_unlock_irqrestore(&zatm_dev->lock, flags);
-	DPRINTK("chan is %d\n",chan);
-	if (!chan) return -EAGAIN;
-	use_pool(vcc->dev,zatm_vcc->pool);
-	DPRINTK("pool %d\n",zatm_vcc->pool);
-	/* set up VC descriptor */
-	spin_lock_irqsave(&zatm_dev->lock, flags);
-	zpokel(zatm_dev,zatm_vcc->pool << uPD98401_RXVC_POOL_SHIFT,
-	    chan*VC_SIZE/4);
-	zpokel(zatm_dev,uPD98401_RXVC_OD | (vcc->qos.aal == ATM_AAL5 ?
-	    uPD98401_RXVC_AR : 0) | cells,chan*VC_SIZE/4+1);
-	zpokel(zatm_dev,0,chan*VC_SIZE/4+2);
-	zatm_vcc->rx_chan = chan;
-	zatm_dev->rx_map[chan] = vcc;
-	spin_unlock_irqrestore(&zatm_dev->lock, flags);
-	return 0;
-}
-
-
-static int open_rx_second(struct atm_vcc *vcc)
-{
-	struct zatm_dev *zatm_dev;
-	struct zatm_vcc *zatm_vcc;
-	unsigned long flags;
-	int pos,shift;
-
-	DPRINTK("open_rx_second (0x%x)\n",inb_p(0xc053));
-	zatm_dev = ZATM_DEV(vcc->dev);
-	zatm_vcc = ZATM_VCC(vcc);
-	if (!zatm_vcc->rx_chan) return 0;
-	spin_lock_irqsave(&zatm_dev->lock, flags);
-	/* should also handle VPI @@@ */
-	pos = vcc->vci >> 1;
-	shift = (1-(vcc->vci & 1)) << 4;
-	zpokel(zatm_dev,(zpeekl(zatm_dev,pos) & ~(0xffff << shift)) |
-	    ((zatm_vcc->rx_chan | uPD98401_RXLT_ENBL) << shift),pos);
-	spin_unlock_irqrestore(&zatm_dev->lock, flags);
-	return 0;
-}
-
-
-static void close_rx(struct atm_vcc *vcc)
-{
-	struct zatm_dev *zatm_dev;
-	struct zatm_vcc *zatm_vcc;
-	unsigned long flags;
-	int pos,shift;
-
-	zatm_vcc = ZATM_VCC(vcc);
-	zatm_dev = ZATM_DEV(vcc->dev);
-	if (!zatm_vcc->rx_chan) return;
-	DPRINTK("close_rx\n");
-	/* disable receiver */
-	if (vcc->vpi != ATM_VPI_UNSPEC && vcc->vci != ATM_VCI_UNSPEC) {
-		spin_lock_irqsave(&zatm_dev->lock, flags);
-		pos = vcc->vci >> 1;
-		shift = (1-(vcc->vci & 1)) << 4;
-		zpokel(zatm_dev,zpeekl(zatm_dev,pos) & ~(0xffff << shift),pos);
-		zwait();
-		zout(uPD98401_NOP,CMR);
-		zwait();
-		zout(uPD98401_NOP,CMR);
-		spin_unlock_irqrestore(&zatm_dev->lock, flags);
-	}
-	spin_lock_irqsave(&zatm_dev->lock, flags);
-	zwait();
-	zout(uPD98401_DEACT_CHAN | uPD98401_CHAN_RT | (zatm_vcc->rx_chan <<
-	    uPD98401_CHAN_ADDR_SHIFT),CMR);
-	zwait();
-	udelay(10); /* why oh why ... ? */
-	zout(uPD98401_CLOSE_CHAN | uPD98401_CHAN_RT | (zatm_vcc->rx_chan <<
-	    uPD98401_CHAN_ADDR_SHIFT),CMR);
-	zwait();
-	if (!(zin(CMR) & uPD98401_CHAN_ADDR))
-		printk(KERN_CRIT DEV_LABEL "(itf %d): can't close RX channel "
-		    "%d\n",vcc->dev->number,zatm_vcc->rx_chan);
-	spin_unlock_irqrestore(&zatm_dev->lock, flags);
-	zatm_dev->rx_map[zatm_vcc->rx_chan] = NULL;
-	zatm_vcc->rx_chan = 0;
-	unuse_pool(vcc->dev,zatm_vcc->pool);
-}
-
-
-static int start_rx(struct atm_dev *dev)
-{
-	struct zatm_dev *zatm_dev;
-	int i;
-
-	DPRINTK("start_rx\n");
-	zatm_dev = ZATM_DEV(dev);
-	zatm_dev->rx_map = kcalloc(zatm_dev->chans,
-				   sizeof(*zatm_dev->rx_map),
-				   GFP_KERNEL);
-	if (!zatm_dev->rx_map) return -ENOMEM;
-	/* set VPI/VCI split (use all VCIs and give what's left to VPIs) */
-	zpokel(zatm_dev,(1 << dev->ci_range.vci_bits)-1,uPD98401_VRR);
-	/* prepare free buffer pools */
-	for (i = 0; i <= ZATM_LAST_POOL; i++) {
-		zatm_dev->pool_info[i].ref_count = 0;
-		zatm_dev->pool_info[i].rqa_count = 0;
-		zatm_dev->pool_info[i].rqu_count = 0;
-		zatm_dev->pool_info[i].low_water = LOW_MARK;
-		zatm_dev->pool_info[i].high_water = HIGH_MARK;
-		zatm_dev->pool_info[i].offset = 0;
-		zatm_dev->pool_info[i].next_off = 0;
-		zatm_dev->pool_info[i].next_cnt = 0;
-		zatm_dev->pool_info[i].next_thres = OFF_CNG_THRES;
-	}
-	return 0;
-}
-
-
-/*----------------------------------- TX ------------------------------------*/
-
-
-static int do_tx(struct sk_buff *skb)
-{
-	struct atm_vcc *vcc;
-	struct zatm_dev *zatm_dev;
-	struct zatm_vcc *zatm_vcc;
-	u32 *dsc;
-	unsigned long flags;
-
-	EVENT("do_tx\n",0,0);
-	DPRINTK("sending skb %p\n",skb);
-	vcc = ATM_SKB(skb)->vcc;
-	zatm_dev = ZATM_DEV(vcc->dev);
-	zatm_vcc = ZATM_VCC(vcc);
-	EVENT("iovcnt=%d\n",skb_shinfo(skb)->nr_frags,0);
-	spin_lock_irqsave(&zatm_dev->lock, flags);
-	if (!skb_shinfo(skb)->nr_frags) {
-		if (zatm_vcc->txing == RING_ENTRIES-1) {
-			spin_unlock_irqrestore(&zatm_dev->lock, flags);
-			return RING_BUSY;
-		}
-		zatm_vcc->txing++;
-		dsc = zatm_vcc->ring+zatm_vcc->ring_curr;
-		zatm_vcc->ring_curr = (zatm_vcc->ring_curr+RING_WORDS) &
-		    (RING_ENTRIES*RING_WORDS-1);
-		dsc[1] = 0;
-		dsc[2] = skb->len;
-		dsc[3] = virt_to_bus(skb->data);
-		mb();
-		dsc[0] = uPD98401_TXPD_V | uPD98401_TXPD_DP | uPD98401_TXPD_SM
-		    | (vcc->qos.aal == ATM_AAL5 ? uPD98401_TXPD_AAL5 : 0 |
-		    (ATM_SKB(skb)->atm_options & ATM_ATMOPT_CLP ?
-		    uPD98401_CLPM_1 : uPD98401_CLPM_0));
-		EVENT("dsc (0x%lx)\n",(unsigned long) dsc,0);
-	}
-	else {
-printk("NONONONOO!!!!\n");
-		dsc = NULL;
-#if 0
-		u32 *put;
-		int i;
-
-		dsc = kmalloc(uPD98401_TXPD_SIZE * 2 +
-			uPD98401_TXBD_SIZE * ATM_SKB(skb)->iovcnt, GFP_ATOMIC);
-		if (!dsc) {
-			if (vcc->pop)
-				vcc->pop(vcc, skb);
-			else
-				dev_kfree_skb_irq(skb);
-			return -EAGAIN;
-		}
-		/* @@@ should check alignment */
-		put = dsc+8;
-		dsc[0] = uPD98401_TXPD_V | uPD98401_TXPD_DP |
-		    (vcc->aal == ATM_AAL5 ? uPD98401_TXPD_AAL5 : 0 |
-		    (ATM_SKB(skb)->atm_options & ATM_ATMOPT_CLP ?
-		    uPD98401_CLPM_1 : uPD98401_CLPM_0));
-		dsc[1] = 0;
-		dsc[2] = ATM_SKB(skb)->iovcnt * uPD98401_TXBD_SIZE;
-		dsc[3] = virt_to_bus(put);
-		for (i = 0; i < ATM_SKB(skb)->iovcnt; i++) {
-			*put++ = ((struct iovec *) skb->data)[i].iov_len;
-			*put++ = virt_to_bus(((struct iovec *)
-			    skb->data)[i].iov_base);
-		}
-		put[-2] |= uPD98401_TXBD_LAST;
-#endif
-	}
-	ZATM_PRV_DSC(skb) = dsc;
-	skb_queue_tail(&zatm_vcc->tx_queue,skb);
-	DPRINTK("QRP=0x%08lx\n",zpeekl(zatm_dev,zatm_vcc->tx_chan*VC_SIZE/4+
-	  uPD98401_TXVC_QRP));
-	zwait();
-	zout(uPD98401_TX_READY | (zatm_vcc->tx_chan <<
-	    uPD98401_CHAN_ADDR_SHIFT),CMR);
-	spin_unlock_irqrestore(&zatm_dev->lock, flags);
-	EVENT("done\n",0,0);
-	return 0;
-}
-
-
-static inline void dequeue_tx(struct atm_vcc *vcc)
-{
-	struct zatm_vcc *zatm_vcc;
-	struct sk_buff *skb;
-
-	EVENT("dequeue_tx\n",0,0);
-	zatm_vcc = ZATM_VCC(vcc);
-	skb = skb_dequeue(&zatm_vcc->tx_queue);
-	if (!skb) {
-		printk(KERN_CRIT DEV_LABEL "(itf %d): dequeue_tx but not "
-		    "txing\n",vcc->dev->number);
-		return;
-	}
-#if 0 /* @@@ would fail on CLP */
-if (*ZATM_PRV_DSC(skb) != (uPD98401_TXPD_V | uPD98401_TXPD_DP |
-  uPD98401_TXPD_SM | uPD98401_TXPD_AAL5)) printk("@#*$!!!!  (%08x)\n",
-  *ZATM_PRV_DSC(skb));
-#endif
-	*ZATM_PRV_DSC(skb) = 0; /* mark as invalid */
-	zatm_vcc->txing--;
-	if (vcc->pop) vcc->pop(vcc,skb);
-	else dev_kfree_skb_irq(skb);
-	while ((skb = skb_dequeue(&zatm_vcc->backlog)))
-		if (do_tx(skb) == RING_BUSY) {
-			skb_queue_head(&zatm_vcc->backlog,skb);
-			break;
-		}
-	atomic_inc(&vcc->stats->tx);
-	wake_up(&zatm_vcc->tx_wait);
-}
-
-
-static void poll_tx(struct atm_dev *dev,int mbx)
-{
-	struct zatm_dev *zatm_dev;
-	unsigned long pos;
-	u32 x;
-
-	EVENT("poll_tx\n",0,0);
-	zatm_dev = ZATM_DEV(dev);
-	pos = (zatm_dev->mbx_start[mbx] & ~0xffffUL) | zin(MTA(mbx));
-	while (x = zin(MWA(mbx)), (pos & 0xffff) != x) {
-		int chan;
-
-#if 1
-		u32 data,*addr;
-
-		EVENT("MBX: host 0x%lx, nic 0x%x\n",pos,x);
-		addr = (u32 *) pos;
-		data = *addr;
-		chan = (data & uPD98401_TXI_CONN) >> uPD98401_TXI_CONN_SHIFT;
-		EVENT("addr = 0x%lx, data = 0x%08x,",(unsigned long) addr,
-		    data);
-		EVENT("chan = %d\n",chan,0);
-#else
-NO !
-		chan = (zatm_dev->mbx_start[mbx][pos >> 2] & uPD98401_TXI_CONN)
-		>> uPD98401_TXI_CONN_SHIFT;
-#endif
-		if (chan < zatm_dev->chans && zatm_dev->tx_map[chan])
-			dequeue_tx(zatm_dev->tx_map[chan]);
-		else {
-			printk(KERN_CRIT DEV_LABEL "(itf %d): TX indication "
-			    "for non-existing channel %d\n",dev->number,chan);
-			event_dump();
-		}
-		if (((pos += 4) & 0xffff) == zatm_dev->mbx_end[mbx])
-			pos = zatm_dev->mbx_start[mbx];
-	}
-	zout(pos & 0xffff,MTA(mbx));
-}
-
-
-/*
- * BUG BUG BUG: Doesn't handle "new-style" rate specification yet.
- */
-
-static int alloc_shaper(struct atm_dev *dev,int *pcr,int min,int max,int ubr)
-{
-	struct zatm_dev *zatm_dev;
-	unsigned long flags;
-	unsigned long i,m,c;
-	int shaper;
-
-	DPRINTK("alloc_shaper (min = %d, max = %d)\n",min,max);
-	zatm_dev = ZATM_DEV(dev);
-	if (!zatm_dev->free_shapers) return -EAGAIN;
-	for (shaper = 0; !((zatm_dev->free_shapers >> shaper) & 1); shaper++);
-	zatm_dev->free_shapers &= ~1 << shaper;
-	if (ubr) {
-		c = 5;
-		i = m = 1;
-		zatm_dev->ubr_ref_cnt++;
-		zatm_dev->ubr = shaper;
-		*pcr = 0;
-	}
-	else {
-		if (min) {
-			if (min <= 255) {
-				i = min;
-				m = ATM_OC3_PCR;
-			}
-			else {
-				i = 255;
-				m = ATM_OC3_PCR*255/min;
-			}
-		}
-		else {
-			if (max > zatm_dev->tx_bw) max = zatm_dev->tx_bw;
-			if (max <= 255) {
-				i = max;
-				m = ATM_OC3_PCR;
-			}
-			else {
-				i = 255;
-				m = DIV_ROUND_UP(ATM_OC3_PCR*255, max);
-			}
-		}
-		if (i > m) {
-			printk(KERN_CRIT DEV_LABEL "shaper algorithm botched "
-			    "[%d,%d] -> i=%ld,m=%ld\n",min,max,i,m);
-			m = i;
-		}
-		*pcr = i*ATM_OC3_PCR/m;
-		c = 20; /* @@@ should use max_cdv ! */
-		if ((min && *pcr < min) || (max && *pcr > max)) return -EINVAL;
-		if (zatm_dev->tx_bw < *pcr) return -EAGAIN;
-		zatm_dev->tx_bw -= *pcr;
-	}
-	spin_lock_irqsave(&zatm_dev->lock, flags);
-	DPRINTK("i = %d, m = %d, PCR = %d\n",i,m,*pcr);
-	zpokel(zatm_dev,(i << uPD98401_IM_I_SHIFT) | m,uPD98401_IM(shaper));
-	zpokel(zatm_dev,c << uPD98401_PC_C_SHIFT,uPD98401_PC(shaper));
-	zpokel(zatm_dev,0,uPD98401_X(shaper));
-	zpokel(zatm_dev,0,uPD98401_Y(shaper));
-	zpokel(zatm_dev,uPD98401_PS_E,uPD98401_PS(shaper));
-	spin_unlock_irqrestore(&zatm_dev->lock, flags);
-	return shaper;
-}
-
-
-static void dealloc_shaper(struct atm_dev *dev,int shaper)
-{
-	struct zatm_dev *zatm_dev;
-	unsigned long flags;
-
-	zatm_dev = ZATM_DEV(dev);
-	if (shaper == zatm_dev->ubr) {
-		if (--zatm_dev->ubr_ref_cnt) return;
-		zatm_dev->ubr = -1;
-	}
-	spin_lock_irqsave(&zatm_dev->lock, flags);
-	zpokel(zatm_dev,zpeekl(zatm_dev,uPD98401_PS(shaper)) & ~uPD98401_PS_E,
-	    uPD98401_PS(shaper));
-	spin_unlock_irqrestore(&zatm_dev->lock, flags);
-	zatm_dev->free_shapers |= 1 << shaper;
-}
-
-
-static void close_tx(struct atm_vcc *vcc)
-{
-	struct zatm_dev *zatm_dev;
-	struct zatm_vcc *zatm_vcc;
-	unsigned long flags;
-	int chan;
-
-	zatm_vcc = ZATM_VCC(vcc);
-	zatm_dev = ZATM_DEV(vcc->dev);
-	chan = zatm_vcc->tx_chan;
-	if (!chan) return;
-	DPRINTK("close_tx\n");
-	if (skb_peek(&zatm_vcc->backlog)) {
-		printk("waiting for backlog to drain ...\n");
-		event_dump();
-		wait_event(zatm_vcc->tx_wait, !skb_peek(&zatm_vcc->backlog));
-	}
-	if (skb_peek(&zatm_vcc->tx_queue)) {
-		printk("waiting for TX queue to drain ...\n");
-		event_dump();
-		wait_event(zatm_vcc->tx_wait, !skb_peek(&zatm_vcc->tx_queue));
-	}
-	spin_lock_irqsave(&zatm_dev->lock, flags);
-#if 0
-	zwait();
-	zout(uPD98401_DEACT_CHAN | (chan << uPD98401_CHAN_ADDR_SHIFT),CMR);
-#endif
-	zwait();
-	zout(uPD98401_CLOSE_CHAN | (chan << uPD98401_CHAN_ADDR_SHIFT),CMR);
-	zwait();
-	if (!(zin(CMR) & uPD98401_CHAN_ADDR))
-		printk(KERN_CRIT DEV_LABEL "(itf %d): can't close TX channel "
-		    "%d\n",vcc->dev->number,chan);
-	spin_unlock_irqrestore(&zatm_dev->lock, flags);
-	zatm_vcc->tx_chan = 0;
-	zatm_dev->tx_map[chan] = NULL;
-	if (zatm_vcc->shaper != zatm_dev->ubr) {
-		zatm_dev->tx_bw += vcc->qos.txtp.min_pcr;
-		dealloc_shaper(vcc->dev,zatm_vcc->shaper);
-	}
-	kfree(zatm_vcc->ring);
-}
-
-
-static int open_tx_first(struct atm_vcc *vcc)
-{
-	struct zatm_dev *zatm_dev;
-	struct zatm_vcc *zatm_vcc;
-	unsigned long flags;
-	u32 *loop;
-	unsigned short chan;
-	int unlimited;
-
-	DPRINTK("open_tx_first\n");
-	zatm_dev = ZATM_DEV(vcc->dev);
-	zatm_vcc = ZATM_VCC(vcc);
-	zatm_vcc->tx_chan = 0;
-	if (vcc->qos.txtp.traffic_class == ATM_NONE) return 0;
-	spin_lock_irqsave(&zatm_dev->lock, flags);
-	zwait();
-	zout(uPD98401_OPEN_CHAN,CMR);
-	zwait();
-	DPRINTK("0x%x 0x%x\n",zin(CMR),zin(CER));
-	chan = (zin(CMR) & uPD98401_CHAN_ADDR) >> uPD98401_CHAN_ADDR_SHIFT;
-	spin_unlock_irqrestore(&zatm_dev->lock, flags);
-	DPRINTK("chan is %d\n",chan);
-	if (!chan) return -EAGAIN;
-	unlimited = vcc->qos.txtp.traffic_class == ATM_UBR &&
-	    (!vcc->qos.txtp.max_pcr || vcc->qos.txtp.max_pcr == ATM_MAX_PCR ||
-	    vcc->qos.txtp.max_pcr >= ATM_OC3_PCR);
-	if (unlimited && zatm_dev->ubr != -1) zatm_vcc->shaper = zatm_dev->ubr;
-	else {
-		int uninitialized_var(pcr);
-
-		if (unlimited) vcc->qos.txtp.max_sdu = ATM_MAX_AAL5_PDU;
-		if ((zatm_vcc->shaper = alloc_shaper(vcc->dev,&pcr,
-		    vcc->qos.txtp.min_pcr,vcc->qos.txtp.max_pcr,unlimited))
-		    < 0) {
-			close_tx(vcc);
-			return zatm_vcc->shaper;
-		}
-		if (pcr > ATM_OC3_PCR) pcr = ATM_OC3_PCR;
-		vcc->qos.txtp.min_pcr = vcc->qos.txtp.max_pcr = pcr;
-	}
-	zatm_vcc->tx_chan = chan;
-	skb_queue_head_init(&zatm_vcc->tx_queue);
-	init_waitqueue_head(&zatm_vcc->tx_wait);
-	/* initialize ring */
-	zatm_vcc->ring = kzalloc(RING_SIZE,GFP_KERNEL);
-	if (!zatm_vcc->ring) return -ENOMEM;
-	loop = zatm_vcc->ring+RING_ENTRIES*RING_WORDS;
-	loop[0] = uPD98401_TXPD_V;
-	loop[1] = loop[2] = 0;
-	loop[3] = virt_to_bus(zatm_vcc->ring);
-	zatm_vcc->ring_curr = 0;
-	zatm_vcc->txing = 0;
-	skb_queue_head_init(&zatm_vcc->backlog);
-	zpokel(zatm_dev,virt_to_bus(zatm_vcc->ring),
-	    chan*VC_SIZE/4+uPD98401_TXVC_QRP);
-	return 0;
-}
-
-
-static int open_tx_second(struct atm_vcc *vcc)
-{
-	struct zatm_dev *zatm_dev;
-	struct zatm_vcc *zatm_vcc;
-	unsigned long flags;
-
-	DPRINTK("open_tx_second\n");
-	zatm_dev = ZATM_DEV(vcc->dev);
-	zatm_vcc = ZATM_VCC(vcc);
-	if (!zatm_vcc->tx_chan) return 0;
-	/* set up VC descriptor */
-	spin_lock_irqsave(&zatm_dev->lock, flags);
-	zpokel(zatm_dev,0,zatm_vcc->tx_chan*VC_SIZE/4);
-	zpokel(zatm_dev,uPD98401_TXVC_L | (zatm_vcc->shaper <<
-	    uPD98401_TXVC_SHP_SHIFT) | (vcc->vpi << uPD98401_TXVC_VPI_SHIFT) |
-	    vcc->vci,zatm_vcc->tx_chan*VC_SIZE/4+1);
-	zpokel(zatm_dev,0,zatm_vcc->tx_chan*VC_SIZE/4+2);
-	spin_unlock_irqrestore(&zatm_dev->lock, flags);
-	zatm_dev->tx_map[zatm_vcc->tx_chan] = vcc;
-	return 0;
-}
-
-
-static int start_tx(struct atm_dev *dev)
-{
-	struct zatm_dev *zatm_dev;
-	int i;
-
-	DPRINTK("start_tx\n");
-	zatm_dev = ZATM_DEV(dev);
-	zatm_dev->tx_map = kmalloc_array(zatm_dev->chans,
-					 sizeof(*zatm_dev->tx_map),
-					 GFP_KERNEL);
-	if (!zatm_dev->tx_map) return -ENOMEM;
-	zatm_dev->tx_bw = ATM_OC3_PCR;
-	zatm_dev->free_shapers = (1 << NR_SHAPERS)-1;
-	zatm_dev->ubr = -1;
-	zatm_dev->ubr_ref_cnt = 0;
-	/* initialize shapers */
-	for (i = 0; i < NR_SHAPERS; i++) zpokel(zatm_dev,0,uPD98401_PS(i));
-	return 0;
-}
-
-
-/*------------------------------- interrupts --------------------------------*/
-
-
-static irqreturn_t zatm_int(int irq,void *dev_id)
-{
-	struct atm_dev *dev;
-	struct zatm_dev *zatm_dev;
-	u32 reason;
-	int handled = 0;
-
-	dev = dev_id;
-	zatm_dev = ZATM_DEV(dev);
-	while ((reason = zin(GSR))) {
-		handled = 1;
-		EVENT("reason 0x%x\n",reason,0);
-		if (reason & uPD98401_INT_PI) {
-			EVENT("PHY int\n",0,0);
-			dev->phy->interrupt(dev);
-		}
-		if (reason & uPD98401_INT_RQA) {
-			unsigned long pools;
-			int i;
-
-			pools = zin(RQA);
-			EVENT("RQA (0x%08x)\n",pools,0);
-			for (i = 0; pools; i++) {
-				if (pools & 1) {
-					refill_pool(dev,i);
-					zatm_dev->pool_info[i].rqa_count++;
-				}
-				pools >>= 1;
-			}
-		}
-		if (reason & uPD98401_INT_RQU) {
-			unsigned long pools;
-			int i;
-			pools = zin(RQU);
-			printk(KERN_WARNING DEV_LABEL "(itf %d): RQU 0x%08lx\n",
-			    dev->number,pools);
-			event_dump();
-			for (i = 0; pools; i++) {
-				if (pools & 1) {
-					refill_pool(dev,i);
-					zatm_dev->pool_info[i].rqu_count++;
-				}
-				pools >>= 1;
-			}
-		}
-		/* don't handle RD */
-		if (reason & uPD98401_INT_SPE)
-			printk(KERN_ALERT DEV_LABEL "(itf %d): system parity "
-			    "error at 0x%08x\n",dev->number,zin(ADDR));
-		if (reason & uPD98401_INT_CPE)
-			printk(KERN_ALERT DEV_LABEL "(itf %d): control memory "
-			    "parity error at 0x%08x\n",dev->number,zin(ADDR));
-		if (reason & uPD98401_INT_SBE) {
-			printk(KERN_ALERT DEV_LABEL "(itf %d): system bus "
-			    "error at 0x%08x\n",dev->number,zin(ADDR));
-			event_dump();
-		}
-		/* don't handle IND */
-		if (reason & uPD98401_INT_MF) {
-			printk(KERN_CRIT DEV_LABEL "(itf %d): mailbox full "
-			    "(0x%x)\n",dev->number,(reason & uPD98401_INT_MF)
-			    >> uPD98401_INT_MF_SHIFT);
-			event_dump();
-			    /* @@@ should try to recover */
-		}
-		if (reason & uPD98401_INT_MM) {
-			if (reason & 1) poll_rx(dev,0);
-			if (reason & 2) poll_rx(dev,1);
-			if (reason & 4) poll_tx(dev,2);
-			if (reason & 8) poll_tx(dev,3);
-		}
-		/* @@@ handle RCRn */
-	}
-	return IRQ_RETVAL(handled);
-}
-
-
-/*----------------------------- (E)EPROM access -----------------------------*/
-
-
-static void eprom_set(struct zatm_dev *zatm_dev, unsigned long value,
-		      unsigned short cmd)
-{
-	int error;
-
-	if ((error = pci_write_config_dword(zatm_dev->pci_dev,cmd,value)))
-		printk(KERN_ERR DEV_LABEL ": PCI write failed (0x%02x)\n",
-		    error);
-}
-
-
-static unsigned long eprom_get(struct zatm_dev *zatm_dev, unsigned short cmd)
-{
-	unsigned int value;
-	int error;
-
-	if ((error = pci_read_config_dword(zatm_dev->pci_dev,cmd,&value)))
-		printk(KERN_ERR DEV_LABEL ": PCI read failed (0x%02x)\n",
-		    error);
-	return value;
-}
-
-
-static void eprom_put_bits(struct zatm_dev *zatm_dev, unsigned long data,
-			   int bits, unsigned short cmd)
-{
-	unsigned long value;
-	int i;
-
-	for (i = bits-1; i >= 0; i--) {
-		value = ZEPROM_CS | (((data >> i) & 1) ? ZEPROM_DI : 0);
-		eprom_set(zatm_dev,value,cmd);
-		eprom_set(zatm_dev,value | ZEPROM_SK,cmd);
-		eprom_set(zatm_dev,value,cmd);
-	}
-}
-
-
-static void eprom_get_byte(struct zatm_dev *zatm_dev, unsigned char *byte,
-			   unsigned short cmd)
-{
-	int i;
-
-	*byte = 0;
-	for (i = 8; i; i--) {
-		eprom_set(zatm_dev,ZEPROM_CS,cmd);
-		eprom_set(zatm_dev,ZEPROM_CS | ZEPROM_SK,cmd);
-		*byte <<= 1;
-		if (eprom_get(zatm_dev,cmd) & ZEPROM_DO) *byte |= 1;
-		eprom_set(zatm_dev,ZEPROM_CS,cmd);
-	}
-}
-
-
-static int eprom_try_esi(struct atm_dev *dev, unsigned short cmd, int offset,
-			 int swap)
-{
-	unsigned char buf[ZEPROM_SIZE];
-	struct zatm_dev *zatm_dev;
-	int i;
-
-	zatm_dev = ZATM_DEV(dev);
-	for (i = 0; i < ZEPROM_SIZE; i += 2) {
-		eprom_set(zatm_dev,ZEPROM_CS,cmd); /* select EPROM */
-		eprom_put_bits(zatm_dev,ZEPROM_CMD_READ,ZEPROM_CMD_LEN,cmd);
-		eprom_put_bits(zatm_dev,i >> 1,ZEPROM_ADDR_LEN,cmd);
-		eprom_get_byte(zatm_dev,buf+i+swap,cmd);
-		eprom_get_byte(zatm_dev,buf+i+1-swap,cmd);
-		eprom_set(zatm_dev,0,cmd); /* deselect EPROM */
-	}
-	memcpy(dev->esi,buf+offset,ESI_LEN);
-	return memcmp(dev->esi,"\0\0\0\0\0",ESI_LEN); /* assumes ESI_LEN == 6 */
-}
-
-
-static void eprom_get_esi(struct atm_dev *dev)
-{
-	if (eprom_try_esi(dev,ZEPROM_V1_REG,ZEPROM_V1_ESI_OFF,1)) return;
-	(void) eprom_try_esi(dev,ZEPROM_V2_REG,ZEPROM_V2_ESI_OFF,0);
-}
-
-
-/*--------------------------------- entries ---------------------------------*/
-
-
-static int zatm_init(struct atm_dev *dev)
-{
-	struct zatm_dev *zatm_dev;
-	struct pci_dev *pci_dev;
-	unsigned short command;
-	int error,i,last;
-	unsigned long t0,t1,t2;
-
-	DPRINTK(">zatm_init\n");
-	zatm_dev = ZATM_DEV(dev);
-	spin_lock_init(&zatm_dev->lock);
-	pci_dev = zatm_dev->pci_dev;
-	zatm_dev->base = pci_resource_start(pci_dev, 0);
-	zatm_dev->irq = pci_dev->irq;
-	if ((error = pci_read_config_word(pci_dev,PCI_COMMAND,&command))) {
-		printk(KERN_ERR DEV_LABEL "(itf %d): init error 0x%02x\n",
-		    dev->number,error);
-		return -EINVAL;
-	}
-	if ((error = pci_write_config_word(pci_dev,PCI_COMMAND,
-	    command | PCI_COMMAND_IO | PCI_COMMAND_MASTER))) {
-		printk(KERN_ERR DEV_LABEL "(itf %d): can't enable IO (0x%02x)"
-		    "\n",dev->number,error);
-		return -EIO;
-	}
-	eprom_get_esi(dev);
-	printk(KERN_NOTICE DEV_LABEL "(itf %d): rev.%d,base=0x%x,irq=%d,",
-	    dev->number,pci_dev->revision,zatm_dev->base,zatm_dev->irq);
-	/* reset uPD98401 */
-	zout(0,SWR);
-	while (!(zin(GSR) & uPD98401_INT_IND));
-	zout(uPD98401_GMR_ONE /*uPD98401_BURST4*/,GMR);
-	last = MAX_CRAM_SIZE;
-	for (i = last-RAM_INCREMENT; i >= 0; i -= RAM_INCREMENT) {
-		zpokel(zatm_dev,0x55555555,i);
-		if (zpeekl(zatm_dev,i) != 0x55555555) last = i;
-		else {
-			zpokel(zatm_dev,0xAAAAAAAA,i);
-			if (zpeekl(zatm_dev,i) != 0xAAAAAAAA) last = i;
-			else zpokel(zatm_dev,i,i);
-		}
-	}
-	for (i = 0; i < last; i += RAM_INCREMENT)
-		if (zpeekl(zatm_dev,i) != i) break;
-	zatm_dev->mem = i << 2;
-	while (i) zpokel(zatm_dev,0,--i);
-	/* reset again to rebuild memory pointers */
-	zout(0,SWR);
-	while (!(zin(GSR) & uPD98401_INT_IND));
-	zout(uPD98401_GMR_ONE | uPD98401_BURST8 | uPD98401_BURST4 |
-	    uPD98401_BURST2 | uPD98401_GMR_PM | uPD98401_GMR_DR,GMR);
-	/* TODO: should shrink allocation now */
-	printk("mem=%dkB,%s (",zatm_dev->mem >> 10,zatm_dev->copper ? "UTP" :
-	    "MMF");
-	for (i = 0; i < ESI_LEN; i++)
-		printk("%02X%s",dev->esi[i],i == ESI_LEN-1 ? ")\n" : "-");
-	do {
-		unsigned long flags;
-
-		spin_lock_irqsave(&zatm_dev->lock, flags);
-		t0 = zpeekl(zatm_dev,uPD98401_TSR);
-		udelay(10);
-		t1 = zpeekl(zatm_dev,uPD98401_TSR);
-		udelay(1010);
-		t2 = zpeekl(zatm_dev,uPD98401_TSR);
-		spin_unlock_irqrestore(&zatm_dev->lock, flags);
-	}
-	while (t0 > t1 || t1 > t2); /* loop if wrapping ... */
-	zatm_dev->khz = t2-2*t1+t0;
-	printk(KERN_NOTICE DEV_LABEL "(itf %d): uPD98401 %d.%d at %d.%03d "
-	    "MHz\n",dev->number,
-	    (zin(VER) & uPD98401_MAJOR) >> uPD98401_MAJOR_SHIFT,
-            zin(VER) & uPD98401_MINOR,zatm_dev->khz/1000,zatm_dev->khz % 1000);
-	return uPD98402_init(dev);
-}
-
-
-static int zatm_start(struct atm_dev *dev)
-{
-	struct zatm_dev *zatm_dev = ZATM_DEV(dev);
-	struct pci_dev *pdev = zatm_dev->pci_dev;
-	unsigned long curr;
-	int pools,vccs,rx;
-	int error, i, ld;
-
-	DPRINTK("zatm_start\n");
-	zatm_dev->rx_map = zatm_dev->tx_map = NULL;
- 	for (i = 0; i < NR_MBX; i++)
- 		zatm_dev->mbx_start[i] = 0;
- 	error = request_irq(zatm_dev->irq, zatm_int, IRQF_SHARED, DEV_LABEL, dev);
-	if (error < 0) {
- 		printk(KERN_ERR DEV_LABEL "(itf %d): IRQ%d is already in use\n",
- 		    dev->number,zatm_dev->irq);
-		goto done;
-	}
-	/* define memory regions */
-	pools = NR_POOLS;
-	if (NR_SHAPERS*SHAPER_SIZE > pools*POOL_SIZE)
-		pools = NR_SHAPERS*SHAPER_SIZE/POOL_SIZE;
-	vccs = (zatm_dev->mem-NR_SHAPERS*SHAPER_SIZE-pools*POOL_SIZE)/
-	    (2*VC_SIZE+RX_SIZE);
-	ld = -1;
-	for (rx = 1; rx < vccs; rx <<= 1) ld++;
-	dev->ci_range.vpi_bits = 0; /* @@@ no VPI for now */
-	dev->ci_range.vci_bits = ld;
-	dev->link_rate = ATM_OC3_PCR;
-	zatm_dev->chans = vccs; /* ??? */
-	curr = rx*RX_SIZE/4;
-	DPRINTK("RX pool 0x%08lx\n",curr);
-	zpokel(zatm_dev,curr,uPD98401_PMA); /* receive pool */
-	zatm_dev->pool_base = curr;
-	curr += pools*POOL_SIZE/4;
-	DPRINTK("Shapers 0x%08lx\n",curr);
-	zpokel(zatm_dev,curr,uPD98401_SMA); /* shapers */
-	curr += NR_SHAPERS*SHAPER_SIZE/4;
-	DPRINTK("Free    0x%08lx\n",curr);
-	zpokel(zatm_dev,curr,uPD98401_TOS); /* free pool */
-	printk(KERN_INFO DEV_LABEL "(itf %d): %d shapers, %d pools, %d RX, "
-	    "%ld VCs\n",dev->number,NR_SHAPERS,pools,rx,
-	    (zatm_dev->mem-curr*4)/VC_SIZE);
-	/* create mailboxes */
-	for (i = 0; i < NR_MBX; i++) {
-		void *mbx;
-		dma_addr_t mbx_dma;
-
-		if (!mbx_entries[i])
-			continue;
-		mbx = dma_alloc_coherent(&pdev->dev,
-					 2 * MBX_SIZE(i), &mbx_dma, GFP_KERNEL);
-		if (!mbx) {
-			error = -ENOMEM;
-			goto out;
-		}
-		/*
-		 * Alignment provided by dma_alloc_coherent() isn't enough
-		 * for this device.
-		 */
-		if (((unsigned long)mbx ^ mbx_dma) & 0xffff) {
-			printk(KERN_ERR DEV_LABEL "(itf %d): system "
-			       "bus incompatible with driver\n", dev->number);
-			dma_free_coherent(&pdev->dev, 2*MBX_SIZE(i), mbx, mbx_dma);
-			error = -ENODEV;
-			goto out;
-		}
-		DPRINTK("mbx@0x%08lx-0x%08lx\n", mbx, mbx + MBX_SIZE(i));
-		zatm_dev->mbx_start[i] = (unsigned long)mbx;
-		zatm_dev->mbx_dma[i] = mbx_dma;
-		zatm_dev->mbx_end[i] = (zatm_dev->mbx_start[i] + MBX_SIZE(i)) &
-					0xffff;
-		zout(mbx_dma >> 16, MSH(i));
-		zout(mbx_dma, MSL(i));
-		zout(zatm_dev->mbx_end[i], MBA(i));
-		zout((unsigned long)mbx & 0xffff, MTA(i));
-		zout((unsigned long)mbx & 0xffff, MWA(i));
-	}
-	error = start_tx(dev);
-	if (error)
-		goto out;
-	error = start_rx(dev);
-	if (error)
-		goto out_tx;
-	error = dev->phy->start(dev);
-	if (error)
-		goto out_rx;
-	zout(0xffffffff,IMR); /* enable interrupts */
-	/* enable TX & RX */
-	zout(zin(GMR) | uPD98401_GMR_SE | uPD98401_GMR_RE,GMR);
-done:
-	return error;
-
-out_rx:
-	kfree(zatm_dev->rx_map);
-out_tx:
-	kfree(zatm_dev->tx_map);
-out:
-	while (i-- > 0) {
-		dma_free_coherent(&pdev->dev, 2 * MBX_SIZE(i),
-				  (void *)zatm_dev->mbx_start[i],
-				  zatm_dev->mbx_dma[i]);
-	}
-	free_irq(zatm_dev->irq, dev);
-	goto done;
-}
-
-
-static void zatm_close(struct atm_vcc *vcc)
-{
-        DPRINTK(">zatm_close\n");
-        if (!ZATM_VCC(vcc)) return;
-	clear_bit(ATM_VF_READY,&vcc->flags);
-        close_rx(vcc);
-	EVENT("close_tx\n",0,0);
-        close_tx(vcc);
-        DPRINTK("zatm_close: done waiting\n");
-        /* deallocate memory */
-        kfree(ZATM_VCC(vcc));
-	vcc->dev_data = NULL;
-	clear_bit(ATM_VF_ADDR,&vcc->flags);
-}
-
-
-static int zatm_open(struct atm_vcc *vcc)
-{
-	struct zatm_vcc *zatm_vcc;
-	short vpi = vcc->vpi;
-	int vci = vcc->vci;
-	int error;
-
-	DPRINTK(">zatm_open\n");
-	if (!test_bit(ATM_VF_PARTIAL,&vcc->flags))
-		vcc->dev_data = NULL;
-	if (vci != ATM_VPI_UNSPEC && vpi != ATM_VCI_UNSPEC)
-		set_bit(ATM_VF_ADDR,&vcc->flags);
-	if (vcc->qos.aal != ATM_AAL5) return -EINVAL; /* @@@ AAL0 */
-	DPRINTK(DEV_LABEL "(itf %d): open %d.%d\n",vcc->dev->number,vcc->vpi,
-	    vcc->vci);
-	if (!test_bit(ATM_VF_PARTIAL,&vcc->flags)) {
-		zatm_vcc = kmalloc(sizeof(*zatm_vcc), GFP_KERNEL);
-		if (!zatm_vcc) {
-			clear_bit(ATM_VF_ADDR,&vcc->flags);
-			return -ENOMEM;
-		}
-		vcc->dev_data = zatm_vcc;
-		ZATM_VCC(vcc)->tx_chan = 0; /* for zatm_close after open_rx */
-		if ((error = open_rx_first(vcc))) {
-	                zatm_close(vcc);
-	                return error;
-	        }
-		if ((error = open_tx_first(vcc))) {
-			zatm_close(vcc);
-			return error;
-	        }
-	}
-	if (vci == ATM_VPI_UNSPEC || vpi == ATM_VCI_UNSPEC) return 0;
-	if ((error = open_rx_second(vcc))) {
-		zatm_close(vcc);
-		return error;
-        }
-	if ((error = open_tx_second(vcc))) {
-		zatm_close(vcc);
-		return error;
-        }
-	set_bit(ATM_VF_READY,&vcc->flags);
-        return 0;
-}
-
-
-static int zatm_change_qos(struct atm_vcc *vcc,struct atm_qos *qos,int flags)
-{
-	printk("Not yet implemented\n");
-	return -ENOSYS;
-	/* @@@ */
-}
-
-
-static int zatm_ioctl(struct atm_dev *dev,unsigned int cmd,void __user *arg)
-{
-	struct zatm_dev *zatm_dev;
-	unsigned long flags;
-
-	zatm_dev = ZATM_DEV(dev);
-	switch (cmd) {
-		case ZATM_GETPOOLZ:
-			if (!capable(CAP_NET_ADMIN)) return -EPERM;
-			/* fall through */
-		case ZATM_GETPOOL:
-			{
-				struct zatm_pool_info info;
-				int pool;
-
-				if (get_user(pool,
-				    &((struct zatm_pool_req __user *) arg)->pool_num))
-					return -EFAULT;
-				if (pool < 0 || pool > ZATM_LAST_POOL)
-					return -EINVAL;
-				pool = array_index_nospec(pool,
-							  ZATM_LAST_POOL + 1);
-				spin_lock_irqsave(&zatm_dev->lock, flags);
-				info = zatm_dev->pool_info[pool];
-				if (cmd == ZATM_GETPOOLZ) {
-					zatm_dev->pool_info[pool].rqa_count = 0;
-					zatm_dev->pool_info[pool].rqu_count = 0;
-				}
-				spin_unlock_irqrestore(&zatm_dev->lock, flags);
-				return copy_to_user(
-				    &((struct zatm_pool_req __user *) arg)->info,
-				    &info,sizeof(info)) ? -EFAULT : 0;
-			}
-		case ZATM_SETPOOL:
-			{
-				struct zatm_pool_info info;
-				int pool;
-
-				if (!capable(CAP_NET_ADMIN)) return -EPERM;
-				if (get_user(pool,
-				    &((struct zatm_pool_req __user *) arg)->pool_num))
-					return -EFAULT;
-				if (pool < 0 || pool > ZATM_LAST_POOL)
-					return -EINVAL;
-				pool = array_index_nospec(pool,
-							  ZATM_LAST_POOL + 1);
-				if (copy_from_user(&info,
-				    &((struct zatm_pool_req __user *) arg)->info,
-				    sizeof(info))) return -EFAULT;
-				if (!info.low_water)
-					info.low_water = zatm_dev->
-					    pool_info[pool].low_water;
-				if (!info.high_water)
-					info.high_water = zatm_dev->
-					    pool_info[pool].high_water;
-				if (!info.next_thres)
-					info.next_thres = zatm_dev->
-					    pool_info[pool].next_thres;
-				if (info.low_water >= info.high_water ||
-				    info.low_water < 0)
-					return -EINVAL;
-				spin_lock_irqsave(&zatm_dev->lock, flags);
-				zatm_dev->pool_info[pool].low_water =
-				    info.low_water;
-				zatm_dev->pool_info[pool].high_water =
-				    info.high_water;
-				zatm_dev->pool_info[pool].next_thres =
-				    info.next_thres;
-				spin_unlock_irqrestore(&zatm_dev->lock, flags);
-				return 0;
-			}
-		default:
-        		if (!dev->phy->ioctl) return -ENOIOCTLCMD;
-		        return dev->phy->ioctl(dev,cmd,arg);
-	}
-}
-
-
-static int zatm_getsockopt(struct atm_vcc *vcc,int level,int optname,
-    void __user *optval,int optlen)
-{
-	return -EINVAL;
-}
-
-
-static int zatm_setsockopt(struct atm_vcc *vcc,int level,int optname,
-    void __user *optval,unsigned int optlen)
-{
-	return -EINVAL;
-}
-
-static int zatm_send(struct atm_vcc *vcc,struct sk_buff *skb)
-{
-	int error;
-
-	EVENT(">zatm_send 0x%lx\n",(unsigned long) skb,0);
-	if (!ZATM_VCC(vcc)->tx_chan || !test_bit(ATM_VF_READY,&vcc->flags)) {
-		if (vcc->pop) vcc->pop(vcc,skb);
-		else dev_kfree_skb(skb);
-		return -EINVAL;
-	}
-	if (!skb) {
-		printk(KERN_CRIT "!skb in zatm_send ?\n");
-		if (vcc->pop) vcc->pop(vcc,skb);
-		return -EINVAL;
-	}
-	ATM_SKB(skb)->vcc = vcc;
-	error = do_tx(skb);
-	if (error != RING_BUSY) return error;
-	skb_queue_tail(&ZATM_VCC(vcc)->backlog,skb);
-	return 0;
-}
-
-
-static void zatm_phy_put(struct atm_dev *dev,unsigned char value,
-    unsigned long addr)
-{
-	struct zatm_dev *zatm_dev;
-
-	zatm_dev = ZATM_DEV(dev);
-	zwait();
-	zout(value,CER);
-	zout(uPD98401_IND_ACC | uPD98401_IA_B0 |
-	    (uPD98401_IA_TGT_PHY << uPD98401_IA_TGT_SHIFT) | addr,CMR);
-}
-
-
-static unsigned char zatm_phy_get(struct atm_dev *dev,unsigned long addr)
-{
-	struct zatm_dev *zatm_dev;
-
-	zatm_dev = ZATM_DEV(dev);
-	zwait();
-	zout(uPD98401_IND_ACC | uPD98401_IA_B0 | uPD98401_IA_RW |
-	  (uPD98401_IA_TGT_PHY << uPD98401_IA_TGT_SHIFT) | addr,CMR);
-	zwait();
-	return zin(CER) & 0xff;
-}
-
-
-static const struct atmdev_ops ops = {
-	.open		= zatm_open,
-	.close		= zatm_close,
-	.ioctl		= zatm_ioctl,
-	.getsockopt	= zatm_getsockopt,
-	.setsockopt	= zatm_setsockopt,
-	.send		= zatm_send,
-	.phy_put	= zatm_phy_put,
-	.phy_get	= zatm_phy_get,
-	.change_qos	= zatm_change_qos,
-};
-
-static int zatm_init_one(struct pci_dev *pci_dev,
-			 const struct pci_device_id *ent)
-{
-	struct atm_dev *dev;
-	struct zatm_dev *zatm_dev;
-	int ret = -ENOMEM;
-
-	zatm_dev = kmalloc(sizeof(*zatm_dev), GFP_KERNEL);
-	if (!zatm_dev) {
-		printk(KERN_EMERG "%s: memory shortage\n", DEV_LABEL);
-		goto out;
-	}
-
-	dev = atm_dev_register(DEV_LABEL, &pci_dev->dev, &ops, -1, NULL);
-	if (!dev)
-		goto out_free;
-
-	ret = pci_enable_device(pci_dev);
-	if (ret < 0)
-		goto out_deregister;
-
-	ret = pci_request_regions(pci_dev, DEV_LABEL);
-	if (ret < 0)
-		goto out_disable;
-
-	ret = dma_set_mask_and_coherent(&pci_dev->dev, DMA_BIT_MASK(32));
-	if (ret < 0)
-		goto out_release;
-
-	zatm_dev->pci_dev = pci_dev;
-	dev->dev_data = zatm_dev;
-	zatm_dev->copper = (int)ent->driver_data;
-	if ((ret = zatm_init(dev)) || (ret = zatm_start(dev)))
-		goto out_release;
-
-	pci_set_drvdata(pci_dev, dev);
-	zatm_dev->more = zatm_boards;
-	zatm_boards = dev;
-	ret = 0;
-out:
-	return ret;
-
-out_release:
-	pci_release_regions(pci_dev);
-out_disable:
-	pci_disable_device(pci_dev);
-out_deregister:
-	atm_dev_deregister(dev);
-out_free:
-	kfree(zatm_dev);
-	goto out;
-}
-
-
-MODULE_LICENSE("GPL");
-
-static const struct pci_device_id zatm_pci_tbl[] = {
-	{ PCI_VDEVICE(ZEITNET, PCI_DEVICE_ID_ZEITNET_1221), ZATM_COPPER },
-	{ PCI_VDEVICE(ZEITNET, PCI_DEVICE_ID_ZEITNET_1225), 0 },
-	{ 0, }
-};
-MODULE_DEVICE_TABLE(pci, zatm_pci_tbl);
-
-static struct pci_driver zatm_driver = {
-	.name =		DEV_LABEL,
-	.id_table =	zatm_pci_tbl,
-	.probe =	zatm_init_one,
-};
-
-static int __init zatm_init_module(void)
-{
-	return pci_register_driver(&zatm_driver);
-}
-
-module_init(zatm_init_module);
-/* module_exit not defined so not unloadable */
diff --git a/drivers/atm/zatm.h b/drivers/atm/zatm.h
deleted file mode 100644
index 8204369fe825..000000000000
--- a/drivers/atm/zatm.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* drivers/atm/zatm.h - ZeitNet ZN122x device driver declarations */
-
-/* Written 1995-1998 by Werner Almesberger, EPFL LRC/ICA */
-
-
-#ifndef DRIVER_ATM_ZATM_H
-#define DRIVER_ATM_ZATM_H
-
-#include <linux/skbuff.h>
-#include <linux/atm.h>
-#include <linux/atmdev.h>
-#include <linux/sonet.h>
-#include <linux/pci.h>
-
-
-#define DEV_LABEL	"zatm"
-
-#define MAX_AAL5_PDU	10240	/* allocate for AAL5 PDUs of this size */
-#define MAX_RX_SIZE_LD	14	/* ceil(log2((MAX_AAL5_PDU+47)/48)) */
-
-#define LOW_MARK	12	/* start adding new buffers if less than 12 */
-#define HIGH_MARK	30	/* stop adding buffers after reaching 30 */
-#define OFF_CNG_THRES	5	/* threshold for offset changes */
-
-#define RX_SIZE		2	/* RX lookup entry size (in bytes) */
-#define NR_POOLS	32	/* number of free buffer pointers */
-#define POOL_SIZE	8	/* buffer entry size (in bytes) */
-#define NR_SHAPERS	16	/* number of shapers */
-#define SHAPER_SIZE	4	/* shaper entry size (in bytes) */
-#define VC_SIZE		32	/* VC dsc (TX or RX) size (in bytes) */
-
-#define RING_ENTRIES	32	/* ring entries (without back pointer) */
-#define RING_WORDS	4	/* ring element size */
-#define RING_SIZE	(sizeof(unsigned long)*(RING_ENTRIES+1)*RING_WORDS)
-
-#define NR_MBX		4	/* four mailboxes */
-#define MBX_RX_0	0	/* mailbox indices */
-#define MBX_RX_1	1
-#define MBX_TX_0	2
-#define MBX_TX_1	3
-
-struct zatm_vcc {
-	/*-------------------------------- RX part */
-	int rx_chan;			/* RX channel, 0 if none */
-	int pool;			/* free buffer pool */
-	/*-------------------------------- TX part */
-	int tx_chan;			/* TX channel, 0 if none */
-	int shaper;			/* shaper, <0 if none */
-	struct sk_buff_head tx_queue;	/* list of buffers in transit */
-	wait_queue_head_t tx_wait;	/* for close */
-	u32 *ring;			/* transmit ring */
-	int ring_curr;			/* current write position */
-	int txing;			/* number of transmits in progress */
-	struct sk_buff_head backlog;	/* list of buffers waiting for ring */
-};
-
-struct zatm_dev {
-	/*-------------------------------- TX part */
-	int tx_bw;			/* remaining bandwidth */
-	u32 free_shapers;		/* bit set */
-	int ubr;			/* UBR shaper; -1 if none */
-	int ubr_ref_cnt;		/* number of VCs using UBR shaper */
-	/*-------------------------------- RX part */
-	int pool_ref[NR_POOLS];		/* free buffer pool usage counters */
-	volatile struct sk_buff *last_free[NR_POOLS];
-					/* last entry in respective pool */
-	struct sk_buff_head pool[NR_POOLS];/* free buffer pools */
-	struct zatm_pool_info pool_info[NR_POOLS]; /* pool information */
-	/*-------------------------------- maps */
-	struct atm_vcc **tx_map;	/* TX VCCs */
-	struct atm_vcc **rx_map;	/* RX VCCs */
-	int chans;			/* map size, must be 2^n */
-	/*-------------------------------- mailboxes */
-	unsigned long mbx_start[NR_MBX];/* start addresses */
-	dma_addr_t mbx_dma[NR_MBX];
-	u16 mbx_end[NR_MBX];		/* end offset (in bytes) */
-	/*-------------------------------- other pointers */
-	u32 pool_base;			/* Free buffer pool dsc (word addr) */
-	/*-------------------------------- ZATM links */
-	struct atm_dev *more;		/* other ZATM devices */
-	/*-------------------------------- general information */
-	int mem;			/* RAM on board (in bytes) */
-	int khz;			/* timer clock */
-	int copper;			/* PHY type */
-	unsigned char irq;		/* IRQ */
-	unsigned int base;		/* IO base address */
-	struct pci_dev *pci_dev;	/* PCI stuff */
-	spinlock_t lock;
-};
-
-
-#define ZATM_DEV(d) ((struct zatm_dev *) (d)->dev_data)
-#define ZATM_VCC(d) ((struct zatm_vcc *) (d)->dev_data)
-
-
-struct zatm_skb_prv {
-	struct atm_skb_data _;		/* reserved */
-	u32 *dsc;			/* pointer to skb's descriptor */
-};
-
-#define ZATM_PRV_DSC(skb) (((struct zatm_skb_prv *) (skb)->cb)->dsc)
-
-#endif
diff --git a/drivers/atm/zeprom.h b/drivers/atm/zeprom.h
index 88e01f808a86..8e8819a3840d 100644
--- a/drivers/atm/zeprom.h
+++ b/drivers/atm/zeprom.h
@@ -12,7 +12,7 @@
 #define ZEPROM_V1_REG	PCI_VENDOR_ID	/* PCI register */
 #define ZEPROM_V2_REG	0x40
 
-/* Bits in contol register */
+/* Bits in control register */
 
 #define ZEPROM_SK	0x80000000	/* strobe (probably on raising edge) */
 #define ZEPROM_CS	0x40000000	/* Chip Select */
diff --git a/drivers/auxdisplay/Kconfig b/drivers/auxdisplay/Kconfig
index 48efa7a047f3..bedc6133f970 100644
--- a/drivers/auxdisplay/Kconfig
+++ b/drivers/auxdisplay/Kconfig
@@ -8,7 +8,7 @@
 
 menuconfig AUXDISPLAY
 	bool "Auxiliary Display support"
-	---help---
+	help
 	  Say Y here to get to see options for auxiliary display drivers.
 	  This option alone does not add any kernel code.
 
@@ -16,159 +16,54 @@ menuconfig AUXDISPLAY
 
 if AUXDISPLAY
 
+#
+# Character LCD section
+#
+config CHARLCD
+	tristate "Character LCD core support" if COMPILE_TEST
+	help
+	  This is the base system for character-based LCD displays.
+	  It makes no sense to have this alone, you select your display driver
+	  and if it needs the charlcd core, it will select it automatically.
+	  This is some character LCD core interface that multiple drivers can
+	  use.
+
+config HD44780_COMMON
+	tristate "Common functions for HD44780 (and compatibles) LCD displays" if COMPILE_TEST
+	select CHARLCD
+	help
+	  This is a module with the common symbols for HD44780 (and compatibles)
+	  displays. This is the code that multiple other modules use. It is not
+	  useful alone. If you have some sort of HD44780 compatible display,
+	  you very likely use this. It is selected automatically by selecting
+	  your concrete display.
+
 config HD44780
 	tristate "HD44780 Character LCD support"
 	depends on GPIOLIB || COMPILE_TEST
-	select CHARLCD
-	---help---
+	select HD44780_COMMON
+	help
 	  Enable support for Character LCDs using a HD44780 controller.
 	  The LCD is accessible through the /dev/lcd char device (10, 156).
 	  This code can either be compiled as a module, or linked into the
 	  kernel and started at boot.
 	  If you don't understand what all this is about, say N.
 
-config KS0108
-	tristate "KS0108 LCD Controller"
-	depends on PARPORT_PC
-	default n
-	---help---
-	  If you have a LCD controlled by one or more KS0108
-	  controllers, say Y. You will need also another more specific
-	  driver for your LCD.
-
-	  Depends on Parallel Port support. If you say Y at
-	  parport, you will be able to compile this as a module (M)
-	  and built-in as well (Y).
-
-	  To compile this as a module, choose M here:
-	  the module will be called ks0108.
-
-	  If unsure, say N.
-
-config KS0108_PORT
-	hex "Parallel port where the LCD is connected"
-	depends on KS0108
-	default 0x378
-	---help---
-	  The address of the parallel port where the LCD is connected.
-
-	  The first  standard parallel port address is 0x378.
-	  The second standard parallel port address is 0x278.
-	  The third  standard parallel port address is 0x3BC.
-
-	  You can specify a different address if you need.
-
-	  If you don't know what I'm talking about, load the parport module,
-	  and execute "dmesg" or "cat /proc/ioports". You can see there how
-	  many parallel ports are present and which address each one has.
-
-	  Usually you only need to use 0x378.
-
-	  If you compile this as a module, you can still override this
-	  using the module parameters.
-
-config KS0108_DELAY
-	int "Delay between each control writing (microseconds)"
-	depends on KS0108
-	default "2"
-	---help---
-	  Amount of time the ks0108 should wait between each control write
-	  to the parallel port.
-
-	  If your LCD seems to miss random writings, increment this.
-
-	  If you don't know what I'm talking about, ignore it.
-
-	  If you compile this as a module, you can still override this
-	  value using the module parameters.
-
-config CFAG12864B
-	tristate "CFAG12864B LCD"
-	depends on X86
-	depends on FB
-	depends on KS0108
-	select FB_SYS_FILLRECT
-	select FB_SYS_COPYAREA
-	select FB_SYS_IMAGEBLIT
-	select FB_SYS_FOPS
-	default n
-	---help---
-	  If you have a Crystalfontz 128x64 2-color LCD, cfag12864b Series,
-	  say Y. You also need the ks0108 LCD Controller driver.
-
-	  For help about how to wire your LCD to the parallel port,
-	  check Documentation/admin-guide/auxdisplay/cfag12864b.rst
-
-	  Depends on the x86 arch and the framebuffer support.
-
-	  The LCD framebuffer driver can be attached to a console.
-	  It will work fine. However, you can't attach it to the fbdev driver
-	  of the xorg server.
-
-	  To compile this as a module, choose M here:
-	  the modules will be called cfag12864b and cfag12864bfb.
-
-	  If unsure, say N.
-
-config CFAG12864B_RATE
-	int "Refresh rate (hertz)"
-	depends on CFAG12864B
-	default "20"
-	---help---
-	  Refresh rate of the LCD.
-
-	  As the LCD is not memory mapped, the driver has to make the work by
-	  software. This means you should be careful setting this value higher.
-	  If your CPUs are really slow or you feel the system is slowed down,
-	  decrease the value.
-
-	  Be careful modifying this value to a very high value:
-	  You can freeze the computer, or the LCD maybe can't draw as fast as you
-	  are requesting.
-
-	  If you don't know what I'm talking about, ignore it.
-
-	  If you compile this as a module, you can still override this
-	  value using the module parameters.
-
-config IMG_ASCII_LCD
-	tristate "Imagination Technologies ASCII LCD Display"
-	depends on HAS_IOMEM
-	default y if MIPS_MALTA
-	select MFD_SYSCON
-	help
-	  Enable this to support the simple ASCII LCD displays found on
-	  development boards such as the MIPS Boston, MIPS Malta & MIPS SEAD3
-	  from Imagination Technologies.
-
-config HT16K33
-	tristate "Holtek Ht16K33 LED controller with keyscan"
-	depends on FB && OF && I2C && INPUT
-	select FB_SYS_FOPS
-	select FB_SYS_FILLRECT
-	select FB_SYS_COPYAREA
-	select FB_SYS_IMAGEBLIT
-	select INPUT_MATRIXKMAP
-	select FB_BACKLIGHT
-	help
-	  Say yes here to add support for Holtek HT16K33, RAM mapping 16*8
-	  LED controller driver with keyscan.
-
-config ARM_CHARLCD
-	bool "ARM Ltd. Character LCD Driver"
-	depends on PLAT_VERSATILE
+config LCD2S
+	tristate "lcd2s 20x4 character display over I2C console"
+	depends on I2C
+	select CHARLCD
 	help
-	  This is a driver for the character LCD found on the ARM Ltd.
-	  Versatile and RealView Platform Baseboards. It doesn't do
-	  very much more than display the text "ARM Linux" on the first
-	  line and the Linux version on the second line, but that's
-	  still useful.
+	  This is a driver that lets you use the lcd2s 20x4 character display
+	  from Modtronix engineering as a console output device. The display
+	  is a simple single color character display. You have to connect it
+	  to an I2C bus.
 
 menuconfig PARPORT_PANEL
 	tristate "Parallel port LCD/Keypad Panel support"
 	depends on PARPORT
-	select CHARLCD
-	---help---
+	select HD44780_COMMON
+	help
 	  Say Y here if you have an HD44780 or KS-0074 LCD connected to your
 	  parallel port. This driver also features 4 and 6-key keypads. The LCD
 	  is accessible through the /dev/lcd char device (10, 156), and the
@@ -182,7 +77,7 @@ config PANEL_PARPORT
 	int "Default parallel port number (0=LPT1)"
 	range 0 255
 	default "0"
-	---help---
+	help
 	  This is the index of the parallel port the panel is connected to. One
 	  driver instance only supports one parallel port, so if your keypad
 	  and LCD are connected to two separate ports, you have to start two
@@ -193,7 +88,7 @@ config PANEL_PROFILE
 	int "Default panel profile (0-5, 0=custom)"
 	range 0 5
 	default "5"
-	---help---
+	help
 	  To ease configuration, the driver supports different configuration
 	  profiles for past and recent wirings. These profiles can also be
 	  used to define an approximative configuration, completed by a few
@@ -215,7 +110,7 @@ config PANEL_KEYPAD
 	int "Keypad type (0=none, 1=old 6 keys, 2=new 6 keys, 3=Nexcom 4 keys)"
 	range 0 3
 	default 0
-	---help---
+	help
 	  This enables and configures a keypad connected to the parallel port.
 	  The keys will be read from character device 10,185. Valid values are :
 
@@ -232,7 +127,7 @@ config PANEL_LCD
 	int "LCD type (0=none, 1=custom, 2=old //, 3=ks0074, 4=hantronix, 5=Nexcom)"
 	range 0 5
 	default 0
-	---help---
+	help
 	   This enables and configures an LCD connected to the parallel port.
 	   The driver includes an interpreter for escape codes starting with
 	   '\e[L' which are specific to the LCD, and a few ANSI codes. The
@@ -255,7 +150,7 @@ config PANEL_LCD_HEIGHT
 	int "Number of lines on the LCD (1-2)"
 	range 1 2
 	default 2
-	---help---
+	help
 	  This is the number of visible character lines on the LCD in custom profile.
 	  It can either be 1 or 2.
 
@@ -264,7 +159,7 @@ config PANEL_LCD_WIDTH
 	int "Number of characters per line on the LCD (1-40)"
 	range 1 40
 	default 40
-	---help---
+	help
 	  This is the number of characters per line on the LCD in custom profile.
 	  Common values are 16,20,24,40.
 
@@ -273,7 +168,7 @@ config PANEL_LCD_BWIDTH
 	int "Internal LCD line width (1-40, 40 by default)"
 	range 1 40
 	default 40
-	---help---
+	help
 	  Most LCDs use a standard controller which supports hardware lines of 40
 	  characters, although sometimes only 16, 20 or 24 of them are really wired
 	  to the terminal. This results in some non-visible but addressable characters,
@@ -289,7 +184,7 @@ config PANEL_LCD_HWIDTH
 	int "Hardware LCD line width (1-64, 64 by default)"
 	range 1 64
 	default 64
-	---help---
+	help
 	  Most LCDs use a single address bit to differentiate line 0 and line 1. Since
 	  some of them need to be able to address 40 chars with the lower bits, they
 	  often use the immediately superior power of 2, which is 64, to address the
@@ -303,7 +198,7 @@ config PANEL_LCD_CHARSET
 	int "LCD character set (0=normal, 1=KS0074)"
 	range 0 1
 	default 0
-	---help---
+	help
 	  Some controllers such as the KS0074 use a somewhat strange character set
 	  where many symbols are at unusual places. The driver knows how to map
 	  'standard' ASCII characters to the character sets used by these controllers.
@@ -319,7 +214,7 @@ config PANEL_LCD_PROTO
 	int "LCD communication mode (0=parallel 8 bits, 1=serial)"
 	range 0 1
 	default 0
-	---help---
+	help
 	  This driver now supports any serial or parallel LCD wired to a parallel
 	  port. But before assigning signals, the driver needs to know if it will
 	  be driving a serial LCD or a parallel one. Serial LCDs only use 2 wires
@@ -332,7 +227,7 @@ config PANEL_LCD_PIN_E
 	int "Parallel port pin number & polarity connected to the LCD E signal (-17...17) "
 	range -17 17
 	default 14
-	---help---
+	help
 	  This describes the number of the parallel port pin to which the LCD 'E'
 	  signal has been connected. It can be :
 
@@ -347,7 +242,7 @@ config PANEL_LCD_PIN_RS
 	int "Parallel port pin number & polarity connected to the LCD RS signal (-17...17) "
 	range -17 17
 	default 17
-	---help---
+	help
 	  This describes the number of the parallel port pin to which the LCD 'RS'
 	  signal has been connected. It can be :
 
@@ -362,7 +257,7 @@ config PANEL_LCD_PIN_RW
 	int "Parallel port pin number & polarity connected to the LCD RW signal (-17...17) "
 	range -17 17
 	default 16
-	---help---
+	help
 	  This describes the number of the parallel port pin to which the LCD 'RW'
 	  signal has been connected. It can be :
 
@@ -377,7 +272,7 @@ config PANEL_LCD_PIN_SCL
 	int "Parallel port pin number & polarity connected to the LCD SCL signal (-17...17) "
 	range -17 17
 	default 1
-	---help---
+	help
 	  This describes the number of the parallel port pin to which the serial
 	  LCD 'SCL' signal has been connected. It can be :
 
@@ -392,7 +287,7 @@ config PANEL_LCD_PIN_SDA
 	int "Parallel port pin number & polarity connected to the LCD SDA signal (-17...17) "
 	range -17 17
 	default 2
-	---help---
+	help
 	  This describes the number of the parallel port pin to which the serial
 	  LCD 'SDA' signal has been connected. It can be :
 
@@ -407,7 +302,7 @@ config PANEL_LCD_PIN_BL
 	int "Parallel port pin number & polarity connected to the LCD backlight signal (-17...17) "
 	range -17 17
 	default 0
-	---help---
+	help
 	  This describes the number of the parallel port pin to which the LCD 'BL' signal
 	  has been connected. It can be :
 
@@ -421,9 +316,8 @@ endif # PARPORT_PANEL
 
 config PANEL_CHANGE_MESSAGE
 	bool "Change LCD initialization message ?"
-	depends on CHARLCD
-	default "n"
-	---help---
+	depends on CHARLCD || LINEDISP
+	help
 	  This allows you to replace the boot message indicating the kernel version
 	  and the driver version with a custom message. This is useful on appliances
 	  where a simple 'Starting system' message can be enough to stop a customer
@@ -436,7 +330,7 @@ config PANEL_BOOT_MESSAGE
 	depends on PANEL_CHANGE_MESSAGE="y"
 	string "New initialization message"
 	default ""
-	---help---
+	help
 	  This allows you to replace the boot message indicating the kernel version
 	  and the driver version with a custom message. This is useful on appliances
 	  where a simple 'Starting system' message can be enough to stop a customer
@@ -448,7 +342,7 @@ config PANEL_BOOT_MESSAGE
 choice
 	prompt "Backlight initial state"
 	default CHARLCD_BL_FLASH
-	---help---
+	help
 	  Select the initial backlight state on boot or module load.
 
 	  Previously, there was no option for this: the backlight flashed
@@ -471,13 +365,187 @@ choice
 
 endchoice
 
+#
+# Samsung KS0108 LCD controller section
+#
+config KS0108
+	tristate "KS0108 LCD Controller"
+	depends on PARPORT_PC
+	help
+	  If you have a LCD controlled by one or more KS0108
+	  controllers, say Y. You will need also another more specific
+	  driver for your LCD.
+
+	  Depends on Parallel Port support. If you say Y at
+	  parport, you will be able to compile this as a module (M)
+	  and built-in as well (Y).
+
+	  To compile this as a module, choose M here:
+	  the module will be called ks0108.
+
+	  If unsure, say N.
+
+config KS0108_PORT
+	hex "Parallel port where the LCD is connected"
+	depends on KS0108
+	default 0x378
+	help
+	  The address of the parallel port where the LCD is connected.
+
+	  The first  standard parallel port address is 0x378.
+	  The second standard parallel port address is 0x278.
+	  The third  standard parallel port address is 0x3BC.
+
+	  You can specify a different address if you need.
+
+	  If you don't know what I'm talking about, load the parport module,
+	  and execute "dmesg" or "cat /proc/ioports". You can see there how
+	  many parallel ports are present and which address each one has.
+
+	  Usually you only need to use 0x378.
+
+	  If you compile this as a module, you can still override this
+	  using the module parameters.
+
+config KS0108_DELAY
+	int "Delay between each control writing (microseconds)"
+	depends on KS0108
+	default "2"
+	help
+	  Amount of time the ks0108 should wait between each control write
+	  to the parallel port.
+
+	  If your LCD seems to miss random writings, increment this.
+
+	  If you don't know what I'm talking about, ignore it.
+
+	  If you compile this as a module, you can still override this
+	  value using the module parameters.
+
+config CFAG12864B
+	tristate "CFAG12864B LCD"
+	depends on X86
+	depends on FB
+	depends on KS0108
+	select FB_SYSMEM_HELPERS
+	help
+	  If you have a Crystalfontz 128x64 2-color LCD, cfag12864b Series,
+	  say Y. You also need the ks0108 LCD Controller driver.
+
+	  For help about how to wire your LCD to the parallel port,
+	  check Documentation/admin-guide/auxdisplay/cfag12864b.rst
+
+	  Depends on the x86 arch and the framebuffer support.
+
+	  The LCD framebuffer driver can be attached to a console.
+	  It will work fine. However, you can't attach it to the fbdev driver
+	  of the xorg server.
+
+	  To compile this as a module, choose M here:
+	  the modules will be called cfag12864b and cfag12864bfb.
+
+	  If unsure, say N.
+
+config CFAG12864B_RATE
+	int "Refresh rate (hertz)"
+	depends on CFAG12864B
+	default "20"
+	help
+	  Refresh rate of the LCD.
+
+	  As the LCD is not memory mapped, the driver has to make the work by
+	  software. This means you should be careful setting this value higher.
+	  If your CPUs are really slow or you feel the system is slowed down,
+	  decrease the value.
+
+	  Be careful modifying this value to a very high value:
+	  You can freeze the computer, or the LCD maybe can't draw as fast as you
+	  are requesting.
+
+	  If you don't know what I'm talking about, ignore it.
+
+	  If you compile this as a module, you can still override this
+	  value using the module parameters.
+
+#
+# Single character line display section
+#
+config LINEDISP
+	tristate "Character line display core support" if COMPILE_TEST
+	help
+	  This is the core support for single-line character displays, to be
+	  selected by drivers that use it.
+
+config IMG_ASCII_LCD
+	tristate "Imagination Technologies ASCII LCD Display"
+	depends on HAS_IOMEM
+	default y if MIPS_MALTA
+	select MFD_SYSCON
+	select LINEDISP
+	help
+	  Enable this to support the simple ASCII LCD displays found on
+	  development boards such as the MIPS Boston, MIPS Malta & MIPS SEAD3
+	  from Imagination Technologies.
+
+config HT16K33
+	tristate "Holtek Ht16K33 LED controller with keyscan"
+	depends on FB && I2C && INPUT && BACKLIGHT_CLASS_DEVICE
+	select FB_SYSMEM_HELPERS
+	select INPUT_MATRIXKMAP
+	select FB_BACKLIGHT
+	select NEW_LEDS
+	select LEDS_CLASS
+	select LINEDISP
+	help
+	  Say yes here to add support for Holtek HT16K33, RAM mapping 16*8
+	  LED controller driver with keyscan.
+
+config MAX6959
+	tristate "Maxim MAX6958/6959 7-segment LED controller"
+	depends on I2C
+	select BITREVERSE
+	select REGMAP_I2C
+	select LINEDISP
+	help
+	  If you say yes here you get support for the following Maxim chips
+	  (I2C 7-segment LED display controller):
+	  - MAX6958
+	  - MAX6959 (input support)
+
+	  This driver can also be built as a module. If so, the module
+	  will be called max6959.
+
+config SEG_LED_GPIO
+	tristate "Generic 7-segment LED display"
+	depends on GPIOLIB || COMPILE_TEST
+	select LINEDISP
+	help
+	  This driver supports a generic 7-segment LED display made up
+	  of GPIO pins connected to the individual segments.
+
+	  This driver can also be built as a module. If so, the module
+	  will be called seg-led-gpio.
+
+#
+# Character LCD with non-conforming interface section
+#
+config ARM_CHARLCD
+	bool "ARM Ltd. Character LCD Driver"
+	depends on PLAT_VERSATILE
+	help
+	  This is a driver for the character LCD found on the ARM Ltd.
+	  Versatile and RealView Platform Baseboards. It doesn't do
+	  very much more than display the text "ARM Linux" on the first
+	  line and the Linux version on the second line, but that's
+	  still useful.
+
 endif # AUXDISPLAY
 
+#
+# Deprecated options
+#
 config PANEL
 	tristate "Parallel port LCD/Keypad Panel support (OLD OPTION)"
 	depends on PARPORT
 	select AUXDISPLAY
 	select PARPORT_PANEL
-
-config CHARLCD
-	tristate "Character LCD core support" if COMPILE_TEST
diff --git a/drivers/auxdisplay/Makefile b/drivers/auxdisplay/Makefile
index cf54b5efb07e..f5c13ed1cd4f 100644
--- a/drivers/auxdisplay/Makefile
+++ b/drivers/auxdisplay/Makefile
@@ -3,11 +3,16 @@
 # Makefile for the kernel auxiliary displays device drivers.
 #
 
-obj-$(CONFIG_CHARLCD)		+= charlcd.o
 obj-$(CONFIG_ARM_CHARLCD)	+= arm-charlcd.o
-obj-$(CONFIG_KS0108)		+= ks0108.o
 obj-$(CONFIG_CFAG12864B)	+= cfag12864b.o cfag12864bfb.o
-obj-$(CONFIG_IMG_ASCII_LCD)	+= img-ascii-lcd.o
+obj-$(CONFIG_CHARLCD)		+= charlcd.o
+obj-$(CONFIG_HD44780_COMMON)	+= hd44780_common.o
 obj-$(CONFIG_HD44780)		+= hd44780.o
 obj-$(CONFIG_HT16K33)		+= ht16k33.o
+obj-$(CONFIG_IMG_ASCII_LCD)	+= img-ascii-lcd.o
+obj-$(CONFIG_KS0108)		+= ks0108.o
+obj-$(CONFIG_LCD2S)		+= lcd2s.o
+obj-$(CONFIG_LINEDISP)		+= line-display.o
+obj-$(CONFIG_MAX6959)		+= max6959.o
 obj-$(CONFIG_PARPORT_PANEL)	+= panel.o
+obj-$(CONFIG_SEG_LED_GPIO)	+= seg-led-gpio.o
diff --git a/drivers/auxdisplay/arm-charlcd.c b/drivers/auxdisplay/arm-charlcd.c
index dea031484cc4..a7eae99a48f7 100644
--- a/drivers/auxdisplay/arm-charlcd.c
+++ b/drivers/auxdisplay/arm-charlcd.c
@@ -2,7 +2,7 @@
 /*
  * Driver for the on-board character LCD found on some ARM reference boards
  * This is basically an Hitachi HD44780 LCD with a custom IP block to drive it
- * http://en.wikipedia.org/wiki/HD44780_Character_LCD
+ * https://en.wikipedia.org/wiki/HD44780_Character_LCD
  * Currently it will just display the text "ARM Linux" and the linux version
  *
  * Author: Linus Walleij <triad@df.lth.se>
@@ -270,7 +270,7 @@ static int __init charlcd_probe(struct platform_device *pdev)
 	struct charlcd *lcd;
 	struct resource *res;
 
-	lcd = kzalloc(sizeof(struct charlcd), GFP_KERNEL);
+	lcd = kzalloc(sizeof(*lcd), GFP_KERNEL);
 	if (!lcd)
 		return -ENOMEM;
 
diff --git a/drivers/auxdisplay/cfag12864b.c b/drivers/auxdisplay/cfag12864b.c
index 7eebae7e322c..e1a94ae3eb0c 100644
--- a/drivers/auxdisplay/cfag12864b.c
+++ b/drivers/auxdisplay/cfag12864b.c
@@ -5,7 +5,7 @@
  * Description: cfag12864b LCD driver
  *     Depends: ks0108
  *
- *      Author: Copyright (C) Miguel Ojeda Sandonis
+ *      Author: Copyright (C) Miguel Ojeda <ojeda@kernel.org>
  *        Date: 2006-10-31
  */
 
@@ -33,15 +33,10 @@
  */
 
 static unsigned int cfag12864b_rate = CONFIG_CFAG12864B_RATE;
-module_param(cfag12864b_rate, uint, S_IRUGO);
+module_param(cfag12864b_rate, uint, 0444);
 MODULE_PARM_DESC(cfag12864b_rate,
 	"Refresh rate (hertz)");
 
-unsigned int cfag12864b_getrate(void)
-{
-	return cfag12864b_rate;
-}
-
 /*
  * cfag12864b Commands
  *
@@ -249,11 +244,6 @@ void cfag12864b_disable(void)
 	mutex_unlock(&cfag12864b_mutex);
 }
 
-unsigned char cfag12864b_isenabled(void)
-{
-	return cfag12864b_updating;
-}
-
 static void cfag12864b_update(struct work_struct *work)
 {
 	unsigned char c;
@@ -293,10 +283,8 @@ static void cfag12864b_update(struct work_struct *work)
  */
 
 EXPORT_SYMBOL_GPL(cfag12864b_buffer);
-EXPORT_SYMBOL_GPL(cfag12864b_getrate);
 EXPORT_SYMBOL_GPL(cfag12864b_enable);
 EXPORT_SYMBOL_GPL(cfag12864b_disable);
-EXPORT_SYMBOL_GPL(cfag12864b_isenabled);
 
 /*
  * Is the module inited?
@@ -376,5 +364,5 @@ module_init(cfag12864b_init);
 module_exit(cfag12864b_exit);
 
 MODULE_LICENSE("GPL v2");
-MODULE_AUTHOR("Miguel Ojeda Sandonis <miguel.ojeda.sandonis@gmail.com>");
+MODULE_AUTHOR("Miguel Ojeda <ojeda@kernel.org>");
 MODULE_DESCRIPTION("cfag12864b LCD driver");
diff --git a/drivers/auxdisplay/cfag12864bfb.c b/drivers/auxdisplay/cfag12864bfb.c
index 2002291ab338..24baf6b2c587 100644
--- a/drivers/auxdisplay/cfag12864bfb.c
+++ b/drivers/auxdisplay/cfag12864bfb.c
@@ -5,20 +5,17 @@
  * Description: cfag12864b LCD framebuffer driver
  *     Depends: cfag12864b
  *
- *      Author: Copyright (C) Miguel Ojeda Sandonis
+ *      Author: Copyright (C) Miguel Ojeda <ojeda@kernel.org>
  *        Date: 2006-10-31
  */
 
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/kernel.h>
-#include <linux/delay.h>
 #include <linux/errno.h>
 #include <linux/fb.h>
 #include <linux/mm.h>
 #include <linux/platform_device.h>
-#include <linux/string.h>
-#include <linux/uaccess.h>
 #include <linux/cfag12864b.h>
 
 #define CFAG12864BFB_NAME "cfag12864bfb"
@@ -41,8 +38,8 @@ static const struct fb_var_screeninfo cfag12864bfb_var = {
 	.yres_virtual = CFAG12864B_HEIGHT,
 	.bits_per_pixel = 1,
 	.red = { 0, 1, 0 },
-      	.green = { 0, 1, 0 },
-      	.blue = { 0, 1, 0 },
+	.green = { 0, 1, 0 },
+	.blue = { 0, 1, 0 },
 	.left_margin = 0,
 	.right_margin = 0,
 	.upper_margin = 0,
@@ -54,35 +51,34 @@ static int cfag12864bfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
 {
 	struct page *pages = virt_to_page(cfag12864b_buffer);
 
+	vma->vm_page_prot = pgprot_decrypted(vma->vm_page_prot);
+
 	return vm_map_pages_zero(vma, &pages, 1);
 }
 
 static const struct fb_ops cfag12864bfb_ops = {
 	.owner = THIS_MODULE,
-	.fb_read = fb_sys_read,
-	.fb_write = fb_sys_write,
-	.fb_fillrect = sys_fillrect,
-	.fb_copyarea = sys_copyarea,
-	.fb_imageblit = sys_imageblit,
+	__FB_DEFAULT_SYSMEM_OPS_RDWR,
+	__FB_DEFAULT_SYSMEM_OPS_DRAW,
 	.fb_mmap = cfag12864bfb_mmap,
 };
 
 static int cfag12864bfb_probe(struct platform_device *device)
 {
 	int ret = -EINVAL;
- 	struct fb_info *info = framebuffer_alloc(0, &device->dev);
+	struct fb_info *info = framebuffer_alloc(0, &device->dev);
 
 	if (!info)
 		goto none;
 
-	info->screen_base = (char __iomem *) cfag12864b_buffer;
+	info->flags = FBINFO_VIRTFB;
+	info->screen_buffer = cfag12864b_buffer;
 	info->screen_size = CFAG12864B_SIZE;
 	info->fbops = &cfag12864bfb_ops;
 	info->fix = cfag12864bfb_fix;
 	info->var = cfag12864bfb_var;
 	info->pseudo_palette = NULL;
 	info->par = NULL;
-	info->flags = FBINFO_FLAG_DEFAULT;
 
 	if (register_framebuffer(info) < 0)
 		goto fballoced;
@@ -100,7 +96,7 @@ none:
 	return ret;
 }
 
-static int cfag12864bfb_remove(struct platform_device *device)
+static void cfag12864bfb_remove(struct platform_device *device)
 {
 	struct fb_info *info = platform_get_drvdata(device);
 
@@ -108,8 +104,6 @@ static int cfag12864bfb_remove(struct platform_device *device)
 		unregister_framebuffer(info);
 		framebuffer_release(info);
 	}
-
-	return 0;
 }
 
 static struct platform_driver cfag12864bfb_driver = {
@@ -171,5 +165,5 @@ module_init(cfag12864bfb_init);
 module_exit(cfag12864bfb_exit);
 
 MODULE_LICENSE("GPL v2");
-MODULE_AUTHOR("Miguel Ojeda Sandonis <miguel.ojeda.sandonis@gmail.com>");
+MODULE_AUTHOR("Miguel Ojeda <ojeda@kernel.org>");
 MODULE_DESCRIPTION("cfag12864b LCD framebuffer driver");
diff --git a/drivers/auxdisplay/charlcd.c b/drivers/auxdisplay/charlcd.c
index d58278ae9e4a..09020bb8ad15 100644
--- a/drivers/auxdisplay/charlcd.c
+++ b/drivers/auxdisplay/charlcd.c
@@ -8,7 +8,6 @@
 
 #include <linux/atomic.h>
 #include <linux/ctype.h>
-#include <linux/delay.h>
 #include <linux/fs.h>
 #include <linux/miscdevice.h>
 #include <linux/module.h>
@@ -18,47 +17,15 @@
 #include <linux/uaccess.h>
 #include <linux/workqueue.h>
 
+#ifndef CONFIG_PANEL_BOOT_MESSAGE
 #include <generated/utsrelease.h>
+#endif
 
 #include "charlcd.h"
 
-#define DEFAULT_LCD_BWIDTH      40
-#define DEFAULT_LCD_HWIDTH      64
-
 /* Keep the backlight on this many seconds for each flash */
 #define LCD_BL_TEMPO_PERIOD	4
 
-#define LCD_FLAG_B		0x0004	/* Blink on */
-#define LCD_FLAG_C		0x0008	/* Cursor on */
-#define LCD_FLAG_D		0x0010	/* Display on */
-#define LCD_FLAG_F		0x0020	/* Large font mode */
-#define LCD_FLAG_N		0x0040	/* 2-rows mode */
-#define LCD_FLAG_L		0x0080	/* Backlight enabled */
-
-/* LCD commands */
-#define LCD_CMD_DISPLAY_CLEAR	0x01	/* Clear entire display */
-
-#define LCD_CMD_ENTRY_MODE	0x04	/* Set entry mode */
-#define LCD_CMD_CURSOR_INC	0x02	/* Increment cursor */
-
-#define LCD_CMD_DISPLAY_CTRL	0x08	/* Display control */
-#define LCD_CMD_DISPLAY_ON	0x04	/* Set display on */
-#define LCD_CMD_CURSOR_ON	0x02	/* Set cursor on */
-#define LCD_CMD_BLINK_ON	0x01	/* Set blink on */
-
-#define LCD_CMD_SHIFT		0x10	/* Shift cursor/display */
-#define LCD_CMD_DISPLAY_SHIFT	0x08	/* Shift display instead of cursor */
-#define LCD_CMD_SHIFT_RIGHT	0x04	/* Shift display/cursor to the right */
-
-#define LCD_CMD_FUNCTION_SET	0x20	/* Set function */
-#define LCD_CMD_DATA_LEN_8BITS	0x10	/* Set data length to 8 bits */
-#define LCD_CMD_TWO_LINES	0x08	/* Set to two display lines */
-#define LCD_CMD_FONT_5X10_DOTS	0x04	/* Set char font to 5x10 dots */
-
-#define LCD_CMD_SET_CGRAM_ADDR	0x40	/* Set char generator RAM address */
-
-#define LCD_CMD_SET_DDRAM_ADDR	0x80	/* Set display data RAM address */
-
 #define LCD_ESCAPE_LEN		24	/* Max chars for LCD escape command */
 #define LCD_ESCAPE_CHAR		27	/* Use char 27 for escape command */
 
@@ -72,13 +39,7 @@ struct charlcd_priv {
 	bool must_clear;
 
 	/* contains the LCD config state */
-	unsigned long int flags;
-
-	/* Contains the LCD X and Y offset */
-	struct {
-		unsigned long int x;
-		unsigned long int y;
-	} addr;
+	unsigned long flags;
 
 	/* Current escape sequence and it's length or -1 if outside */
 	struct {
@@ -94,14 +55,8 @@ struct charlcd_priv {
 /* Device single-open policy control */
 static atomic_t charlcd_available = ATOMIC_INIT(1);
 
-/* sleeps that many milliseconds with a reschedule */
-static void long_sleep(int ms)
-{
-	schedule_timeout_interruptible(msecs_to_jiffies(ms));
-}
-
 /* turn the backlight on or off */
-static void charlcd_backlight(struct charlcd *lcd, int on)
+void charlcd_backlight(struct charlcd *lcd, enum charlcd_onoff on)
 {
 	struct charlcd_priv *priv = charlcd_to_priv(lcd);
 
@@ -113,6 +68,7 @@ static void charlcd_backlight(struct charlcd *lcd, int on)
 		lcd->ops->backlight(lcd, on);
 	mutex_unlock(&priv->bl_tempo_lock);
 }
+EXPORT_SYMBOL_GPL(charlcd_backlight);
 
 static void charlcd_bl_off(struct work_struct *work)
 {
@@ -124,7 +80,7 @@ static void charlcd_bl_off(struct work_struct *work)
 	if (priv->bl_tempo) {
 		priv->bl_tempo = false;
 		if (!(priv->flags & LCD_FLAG_L))
-			priv->lcd.ops->backlight(&priv->lcd, 0);
+			priv->lcd.ops->backlight(&priv->lcd, CHARLCD_OFF);
 	}
 	mutex_unlock(&priv->bl_tempo_lock);
 }
@@ -141,148 +97,41 @@ void charlcd_poke(struct charlcd *lcd)
 
 	mutex_lock(&priv->bl_tempo_lock);
 	if (!priv->bl_tempo && !(priv->flags & LCD_FLAG_L))
-		lcd->ops->backlight(lcd, 1);
+		lcd->ops->backlight(lcd, CHARLCD_ON);
 	priv->bl_tempo = true;
 	schedule_delayed_work(&priv->bl_work, LCD_BL_TEMPO_PERIOD * HZ);
 	mutex_unlock(&priv->bl_tempo_lock);
 }
 EXPORT_SYMBOL_GPL(charlcd_poke);
 
-static void charlcd_gotoxy(struct charlcd *lcd)
-{
-	struct charlcd_priv *priv = charlcd_to_priv(lcd);
-	unsigned int addr;
-
-	/*
-	 * we force the cursor to stay at the end of the
-	 * line if it wants to go farther
-	 */
-	addr = priv->addr.x < lcd->bwidth ? priv->addr.x & (lcd->hwidth - 1)
-					  : lcd->bwidth - 1;
-	if (priv->addr.y & 1)
-		addr += lcd->hwidth;
-	if (priv->addr.y & 2)
-		addr += lcd->bwidth;
-	lcd->ops->write_cmd(lcd, LCD_CMD_SET_DDRAM_ADDR | addr);
-}
-
 static void charlcd_home(struct charlcd *lcd)
 {
-	struct charlcd_priv *priv = charlcd_to_priv(lcd);
-
-	priv->addr.x = 0;
-	priv->addr.y = 0;
-	charlcd_gotoxy(lcd);
+	lcd->addr.x = 0;
+	lcd->addr.y = 0;
+	lcd->ops->home(lcd);
 }
 
 static void charlcd_print(struct charlcd *lcd, char c)
 {
-	struct charlcd_priv *priv = charlcd_to_priv(lcd);
-
-	if (priv->addr.x < lcd->bwidth) {
-		if (lcd->char_conv)
-			c = lcd->char_conv[(unsigned char)c];
-		lcd->ops->write_data(lcd, c);
-		priv->addr.x++;
-
-		/* prevents the cursor from wrapping onto the next line */
-		if (priv->addr.x == lcd->bwidth)
-			charlcd_gotoxy(lcd);
-	}
-}
-
-static void charlcd_clear_fast(struct charlcd *lcd)
-{
-	int pos;
+	if (lcd->addr.x >= lcd->width)
+		return;
 
-	charlcd_home(lcd);
+	if (lcd->char_conv)
+		c = lcd->char_conv[(unsigned char)c];
 
-	if (lcd->ops->clear_fast)
-		lcd->ops->clear_fast(lcd);
-	else
-		for (pos = 0; pos < min(2, lcd->height) * lcd->hwidth; pos++)
-			lcd->ops->write_data(lcd, ' ');
+	if (!lcd->ops->print(lcd, c))
+		lcd->addr.x++;
 
-	charlcd_home(lcd);
+	/* prevents the cursor from wrapping onto the next line */
+	if (lcd->addr.x == lcd->width)
+		lcd->ops->gotoxy(lcd, lcd->addr.x - 1, lcd->addr.y);
 }
 
-/* clears the display and resets X/Y */
 static void charlcd_clear_display(struct charlcd *lcd)
 {
-	struct charlcd_priv *priv = charlcd_to_priv(lcd);
-
-	lcd->ops->write_cmd(lcd, LCD_CMD_DISPLAY_CLEAR);
-	priv->addr.x = 0;
-	priv->addr.y = 0;
-	/* we must wait a few milliseconds (15) */
-	long_sleep(15);
-}
-
-static int charlcd_init_display(struct charlcd *lcd)
-{
-	void (*write_cmd_raw)(struct charlcd *lcd, int cmd);
-	struct charlcd_priv *priv = charlcd_to_priv(lcd);
-	u8 init;
-
-	if (lcd->ifwidth != 4 && lcd->ifwidth != 8)
-		return -EINVAL;
-
-	priv->flags = ((lcd->height > 1) ? LCD_FLAG_N : 0) | LCD_FLAG_D |
-		      LCD_FLAG_C | LCD_FLAG_B;
-
-	long_sleep(20);		/* wait 20 ms after power-up for the paranoid */
-
-	/*
-	 * 8-bit mode, 1 line, small fonts; let's do it 3 times, to make sure
-	 * the LCD is in 8-bit mode afterwards
-	 */
-	init = LCD_CMD_FUNCTION_SET | LCD_CMD_DATA_LEN_8BITS;
-	if (lcd->ifwidth == 4) {
-		init >>= 4;
-		write_cmd_raw = lcd->ops->write_cmd_raw4;
-	} else {
-		write_cmd_raw = lcd->ops->write_cmd;
-	}
-	write_cmd_raw(lcd, init);
-	long_sleep(10);
-	write_cmd_raw(lcd, init);
-	long_sleep(10);
-	write_cmd_raw(lcd, init);
-	long_sleep(10);
-
-	if (lcd->ifwidth == 4) {
-		/* Switch to 4-bit mode, 1 line, small fonts */
-		lcd->ops->write_cmd_raw4(lcd, LCD_CMD_FUNCTION_SET >> 4);
-		long_sleep(10);
-	}
-
-	/* set font height and lines number */
-	lcd->ops->write_cmd(lcd,
-		LCD_CMD_FUNCTION_SET |
-		((lcd->ifwidth == 8) ? LCD_CMD_DATA_LEN_8BITS : 0) |
-		((priv->flags & LCD_FLAG_F) ? LCD_CMD_FONT_5X10_DOTS : 0) |
-		((priv->flags & LCD_FLAG_N) ? LCD_CMD_TWO_LINES : 0));
-	long_sleep(10);
-
-	/* display off, cursor off, blink off */
-	lcd->ops->write_cmd(lcd, LCD_CMD_DISPLAY_CTRL);
-	long_sleep(10);
-
-	lcd->ops->write_cmd(lcd,
-		LCD_CMD_DISPLAY_CTRL |	/* set display mode */
-		((priv->flags & LCD_FLAG_D) ? LCD_CMD_DISPLAY_ON : 0) |
-		((priv->flags & LCD_FLAG_C) ? LCD_CMD_CURSOR_ON : 0) |
-		((priv->flags & LCD_FLAG_B) ? LCD_CMD_BLINK_ON : 0));
-
-	charlcd_backlight(lcd, (priv->flags & LCD_FLAG_L) ? 1 : 0);
-
-	long_sleep(10);
-
-	/* entry mode set : increment, cursor shifting */
-	lcd->ops->write_cmd(lcd, LCD_CMD_ENTRY_MODE | LCD_CMD_CURSOR_INC);
-
-	charlcd_clear_display(lcd);
-	return 0;
+	lcd->ops->clear_display(lcd);
+	lcd->addr.x = 0;
+	lcd->addr.y = 0;
 }
 
 /*
@@ -360,34 +209,58 @@ static inline int handle_lcd_special_code(struct charlcd *lcd)
 	switch (*esc) {
 	case 'D':	/* Display ON */
 		priv->flags |= LCD_FLAG_D;
+		if (priv->flags != oldflags)
+			lcd->ops->display(lcd, CHARLCD_ON);
+
 		processed = 1;
 		break;
 	case 'd':	/* Display OFF */
 		priv->flags &= ~LCD_FLAG_D;
+		if (priv->flags != oldflags)
+			lcd->ops->display(lcd, CHARLCD_OFF);
+
 		processed = 1;
 		break;
 	case 'C':	/* Cursor ON */
 		priv->flags |= LCD_FLAG_C;
+		if (priv->flags != oldflags)
+			lcd->ops->cursor(lcd, CHARLCD_ON);
+
 		processed = 1;
 		break;
 	case 'c':	/* Cursor OFF */
 		priv->flags &= ~LCD_FLAG_C;
+		if (priv->flags != oldflags)
+			lcd->ops->cursor(lcd, CHARLCD_OFF);
+
 		processed = 1;
 		break;
 	case 'B':	/* Blink ON */
 		priv->flags |= LCD_FLAG_B;
+		if (priv->flags != oldflags)
+			lcd->ops->blink(lcd, CHARLCD_ON);
+
 		processed = 1;
 		break;
 	case 'b':	/* Blink OFF */
 		priv->flags &= ~LCD_FLAG_B;
+		if (priv->flags != oldflags)
+			lcd->ops->blink(lcd, CHARLCD_OFF);
+
 		processed = 1;
 		break;
 	case '+':	/* Back light ON */
 		priv->flags |= LCD_FLAG_L;
+		if (priv->flags != oldflags)
+			charlcd_backlight(lcd, CHARLCD_ON);
+
 		processed = 1;
 		break;
 	case '-':	/* Back light OFF */
 		priv->flags &= ~LCD_FLAG_L;
+		if (priv->flags != oldflags)
+			charlcd_backlight(lcd, CHARLCD_OFF);
+
 		processed = 1;
 		break;
 	case '*':	/* Flash back light */
@@ -396,163 +269,98 @@ static inline int handle_lcd_special_code(struct charlcd *lcd)
 		break;
 	case 'f':	/* Small Font */
 		priv->flags &= ~LCD_FLAG_F;
+		if (priv->flags != oldflags)
+			lcd->ops->fontsize(lcd, CHARLCD_FONTSIZE_SMALL);
+
 		processed = 1;
 		break;
 	case 'F':	/* Large Font */
 		priv->flags |= LCD_FLAG_F;
+		if (priv->flags != oldflags)
+			lcd->ops->fontsize(lcd, CHARLCD_FONTSIZE_LARGE);
+
 		processed = 1;
 		break;
 	case 'n':	/* One Line */
 		priv->flags &= ~LCD_FLAG_N;
+		if (priv->flags != oldflags)
+			lcd->ops->lines(lcd, CHARLCD_LINES_1);
+
 		processed = 1;
 		break;
 	case 'N':	/* Two Lines */
 		priv->flags |= LCD_FLAG_N;
+		if (priv->flags != oldflags)
+			lcd->ops->lines(lcd, CHARLCD_LINES_2);
+
 		processed = 1;
 		break;
 	case 'l':	/* Shift Cursor Left */
-		if (priv->addr.x > 0) {
-			/* back one char if not at end of line */
-			if (priv->addr.x < lcd->bwidth)
-				lcd->ops->write_cmd(lcd, LCD_CMD_SHIFT);
-			priv->addr.x--;
+		if (lcd->addr.x > 0) {
+			if (!lcd->ops->shift_cursor(lcd, CHARLCD_SHIFT_LEFT))
+				lcd->addr.x--;
 		}
+
 		processed = 1;
 		break;
 	case 'r':	/* shift cursor right */
-		if (priv->addr.x < lcd->width) {
-			/* allow the cursor to pass the end of the line */
-			if (priv->addr.x < (lcd->bwidth - 1))
-				lcd->ops->write_cmd(lcd,
-					LCD_CMD_SHIFT | LCD_CMD_SHIFT_RIGHT);
-			priv->addr.x++;
+		if (lcd->addr.x < lcd->width) {
+			if (!lcd->ops->shift_cursor(lcd, CHARLCD_SHIFT_RIGHT))
+				lcd->addr.x++;
 		}
+
 		processed = 1;
 		break;
 	case 'L':	/* shift display left */
-		lcd->ops->write_cmd(lcd, LCD_CMD_SHIFT | LCD_CMD_DISPLAY_SHIFT);
+		lcd->ops->shift_display(lcd, CHARLCD_SHIFT_LEFT);
 		processed = 1;
 		break;
 	case 'R':	/* shift display right */
-		lcd->ops->write_cmd(lcd,
-				    LCD_CMD_SHIFT | LCD_CMD_DISPLAY_SHIFT |
-				    LCD_CMD_SHIFT_RIGHT);
+		lcd->ops->shift_display(lcd, CHARLCD_SHIFT_RIGHT);
 		processed = 1;
 		break;
 	case 'k': {	/* kill end of line */
-		int x;
+		int x, xs, ys;
 
-		for (x = priv->addr.x; x < lcd->bwidth; x++)
-			lcd->ops->write_data(lcd, ' ');
+		xs = lcd->addr.x;
+		ys = lcd->addr.y;
+		for (x = lcd->addr.x; x < lcd->width; x++)
+			lcd->ops->print(lcd, ' ');
 
 		/* restore cursor position */
-		charlcd_gotoxy(lcd);
+		lcd->addr.x = xs;
+		lcd->addr.y = ys;
+		lcd->ops->gotoxy(lcd, lcd->addr.x, lcd->addr.y);
 		processed = 1;
 		break;
 	}
 	case 'I':	/* reinitialize display */
-		charlcd_init_display(lcd);
+		lcd->ops->init_display(lcd);
+		priv->flags = ((lcd->height > 1) ? LCD_FLAG_N : 0) | LCD_FLAG_D |
+			LCD_FLAG_C | LCD_FLAG_B;
 		processed = 1;
 		break;
-	case 'G': {
-		/* Generator : LGcxxxxx...xx; must have <c> between '0'
-		 * and '7', representing the numerical ASCII code of the
-		 * redefined character, and <xx...xx> a sequence of 16
-		 * hex digits representing 8 bytes for each character.
-		 * Most LCDs will only use 5 lower bits of the 7 first
-		 * bytes.
-		 */
-
-		unsigned char cgbytes[8];
-		unsigned char cgaddr;
-		int cgoffset;
-		int shift;
-		char value;
-		int addr;
-
-		if (!strchr(esc, ';'))
-			break;
-
-		esc++;
-
-		cgaddr = *(esc++) - '0';
-		if (cgaddr > 7) {
+	case 'G':
+		if (lcd->ops->redefine_char)
+			processed = lcd->ops->redefine_char(lcd, esc);
+		else
 			processed = 1;
-			break;
-		}
-
-		cgoffset = 0;
-		shift = 0;
-		value = 0;
-		while (*esc && cgoffset < 8) {
-			shift ^= 4;
-			if (*esc >= '0' && *esc <= '9') {
-				value |= (*esc - '0') << shift;
-			} else if (*esc >= 'A' && *esc <= 'F') {
-				value |= (*esc - 'A' + 10) << shift;
-			} else if (*esc >= 'a' && *esc <= 'f') {
-				value |= (*esc - 'a' + 10) << shift;
-			} else {
-				esc++;
-				continue;
-			}
-
-			if (shift == 0) {
-				cgbytes[cgoffset++] = value;
-				value = 0;
-			}
-
-			esc++;
-		}
-
-		lcd->ops->write_cmd(lcd, LCD_CMD_SET_CGRAM_ADDR | (cgaddr * 8));
-		for (addr = 0; addr < cgoffset; addr++)
-			lcd->ops->write_data(lcd, cgbytes[addr]);
-
-		/* ensures that we stop writing to CGRAM */
-		charlcd_gotoxy(lcd);
-		processed = 1;
 		break;
-	}
+
 	case 'x':	/* gotoxy : LxXXX[yYYY]; */
 	case 'y':	/* gotoxy : LyYYY[xXXX]; */
 		if (priv->esc_seq.buf[priv->esc_seq.len - 1] != ';')
 			break;
 
 		/* If the command is valid, move to the new address */
-		if (parse_xy(esc, &priv->addr.x, &priv->addr.y))
-			charlcd_gotoxy(lcd);
+		if (parse_xy(esc, &lcd->addr.x, &lcd->addr.y))
+			lcd->ops->gotoxy(lcd, lcd->addr.x, lcd->addr.y);
 
 		/* Regardless of its validity, mark as processed */
 		processed = 1;
 		break;
 	}
 
-	/* TODO: This indent party here got ugly, clean it! */
-	/* Check whether one flag was changed */
-	if (oldflags == priv->flags)
-		return processed;
-
-	/* check whether one of B,C,D flags were changed */
-	if ((oldflags ^ priv->flags) &
-	    (LCD_FLAG_B | LCD_FLAG_C | LCD_FLAG_D))
-		/* set display mode */
-		lcd->ops->write_cmd(lcd,
-			LCD_CMD_DISPLAY_CTRL |
-			((priv->flags & LCD_FLAG_D) ? LCD_CMD_DISPLAY_ON : 0) |
-			((priv->flags & LCD_FLAG_C) ? LCD_CMD_CURSOR_ON : 0) |
-			((priv->flags & LCD_FLAG_B) ? LCD_CMD_BLINK_ON : 0));
-	/* check whether one of F,N flags was changed */
-	else if ((oldflags ^ priv->flags) & (LCD_FLAG_F | LCD_FLAG_N))
-		lcd->ops->write_cmd(lcd,
-			LCD_CMD_FUNCTION_SET |
-			((lcd->ifwidth == 8) ? LCD_CMD_DATA_LEN_8BITS : 0) |
-			((priv->flags & LCD_FLAG_F) ? LCD_CMD_FONT_5X10_DOTS : 0) |
-			((priv->flags & LCD_FLAG_N) ? LCD_CMD_TWO_LINES : 0));
-	/* check whether L flag was changed */
-	else if ((oldflags ^ priv->flags) & LCD_FLAG_L)
-		charlcd_backlight(lcd, !!(priv->flags & LCD_FLAG_L));
-
 	return processed;
 }
 
@@ -577,40 +385,39 @@ static void charlcd_write_char(struct charlcd *lcd, char c)
 			break;
 		case '\b':
 			/* go back one char and clear it */
-			if (priv->addr.x > 0) {
-				/*
-				 * check if we're not at the
-				 * end of the line
-				 */
-				if (priv->addr.x < lcd->bwidth)
-					/* back one char */
-					lcd->ops->write_cmd(lcd, LCD_CMD_SHIFT);
-				priv->addr.x--;
+			if (lcd->addr.x > 0) {
+				/* back one char */
+				if (!lcd->ops->shift_cursor(lcd,
+							CHARLCD_SHIFT_LEFT))
+					lcd->addr.x--;
 			}
 			/* replace with a space */
-			lcd->ops->write_data(lcd, ' ');
+			charlcd_print(lcd, ' ');
 			/* back one char again */
-			lcd->ops->write_cmd(lcd, LCD_CMD_SHIFT);
+			if (!lcd->ops->shift_cursor(lcd, CHARLCD_SHIFT_LEFT))
+				lcd->addr.x--;
+
 			break;
 		case '\f':
 			/* quickly clear the display */
-			charlcd_clear_fast(lcd);
+			charlcd_clear_display(lcd);
 			break;
 		case '\n':
 			/*
 			 * flush the remainder of the current line and
 			 * go to the beginning of the next line
 			 */
-			for (; priv->addr.x < lcd->bwidth; priv->addr.x++)
-				lcd->ops->write_data(lcd, ' ');
-			priv->addr.x = 0;
-			priv->addr.y = (priv->addr.y + 1) % lcd->height;
-			charlcd_gotoxy(lcd);
+			for (; lcd->addr.x < lcd->width; lcd->addr.x++)
+				lcd->ops->print(lcd, ' ');
+
+			lcd->addr.x = 0;
+			lcd->addr.y = (lcd->addr.y + 1) % lcd->height;
+			lcd->ops->gotoxy(lcd, lcd->addr.x, lcd->addr.y);
 			break;
 		case '\r':
 			/* go to the beginning of the same line */
-			priv->addr.x = 0;
-			charlcd_gotoxy(lcd);
+			lcd->addr.x = 0;
+			lcd->ops->gotoxy(lcd, lcd->addr.x, lcd->addr.y);
 			break;
 		case '\t':
 			/* print a space instead of the tab */
@@ -632,7 +439,7 @@ static void charlcd_write_char(struct charlcd *lcd, char c)
 
 		if (!strcmp(priv->esc_seq.buf, "[2J")) {
 			/* clear the display */
-			charlcd_clear_fast(lcd);
+			charlcd_clear_display(lcd);
 			processed = 1;
 		} else if (!strcmp(priv->esc_seq.buf, "[H")) {
 			/* cursor to home */
@@ -665,12 +472,14 @@ static ssize_t charlcd_write(struct file *file, const char __user *buf,
 	char c;
 
 	for (; count-- > 0; (*ppos)++, tmp++) {
-		if (!in_interrupt() && (((count + 1) & 0x1f) == 0))
+		if (((count + 1) & 0x1f) == 0) {
 			/*
-			 * let's be a little nice with other processes
-			 * that need some CPU
+			 * charlcd_write() is invoked as a VFS->write() callback
+			 * and as such it is always invoked from preemptible
+			 * context and may sleep.
 			 */
-			schedule();
+			cond_resched();
+		}
 
 		if (get_user(c, tmp))
 			return -EFAULT;
@@ -695,8 +504,10 @@ static int charlcd_open(struct inode *inode, struct file *file)
 		goto fail;
 
 	if (priv->must_clear) {
-		charlcd_clear_display(&priv->lcd);
+		priv->lcd.ops->clear_display(&priv->lcd);
 		priv->must_clear = false;
+		priv->lcd.addr.x = 0;
+		priv->lcd.addr.y = 0;
 	}
 	return nonseekable_open(inode, file);
 
@@ -715,7 +526,6 @@ static const struct file_operations charlcd_fops = {
 	.write   = charlcd_write,
 	.open    = charlcd_open,
 	.release = charlcd_release,
-	.llseek  = no_llseek,
 };
 
 static struct miscdevice charlcd_dev = {
@@ -730,12 +540,8 @@ static void charlcd_puts(struct charlcd *lcd, const char *s)
 	int count = strlen(s);
 
 	for (; count-- > 0; tmp++) {
-		if (!in_interrupt() && (((count + 1) & 0x1f) == 0))
-			/*
-			 * let's be a little nice with other processes
-			 * that need some CPU
-			 */
-			schedule();
+		if (((count + 1) & 0x1f) == 0)
+			cond_resched();
 
 		charlcd_write_char(lcd, *tmp);
 	}
@@ -761,6 +567,8 @@ static int charlcd_init(struct charlcd *lcd)
 	struct charlcd_priv *priv = charlcd_to_priv(lcd);
 	int ret;
 
+	priv->flags = ((lcd->height > 1) ? LCD_FLAG_N : 0) | LCD_FLAG_D |
+		      LCD_FLAG_C | LCD_FLAG_B;
 	if (lcd->ops->backlight) {
 		mutex_init(&priv->bl_tempo_lock);
 		INIT_DELAYED_WORK(&priv->bl_work, charlcd_bl_off);
@@ -771,7 +579,10 @@ static int charlcd_init(struct charlcd *lcd)
 	 * Since charlcd_init_display() needs to write data, we have to
 	 * enable mark the LCD initialized just before.
 	 */
-	ret = charlcd_init_display(lcd);
+	if (WARN_ON(!lcd->ops->init_display))
+		return -EINVAL;
+
+	ret = lcd->ops->init_display(lcd);
 	if (ret)
 		return ret;
 
@@ -796,9 +607,6 @@ struct charlcd *charlcd_alloc(unsigned int drvdata_size)
 	priv->esc_seq.len = -1;
 
 	lcd = &priv->lcd;
-	lcd->ifwidth = 8;
-	lcd->bwidth = DEFAULT_LCD_BWIDTH;
-	lcd->hwidth = DEFAULT_LCD_HWIDTH;
 	lcd->drvdata = priv->drvdata;
 
 	return lcd;
@@ -834,9 +642,7 @@ static int panel_notify_sys(struct notifier_block *this, unsigned long code,
 }
 
 static struct notifier_block panel_notifier = {
-	panel_notify_sys,
-	NULL,
-	0
+	.notifier_call = panel_notify_sys,
 };
 
 int charlcd_register(struct charlcd *lcd)
@@ -867,11 +673,12 @@ int charlcd_unregister(struct charlcd *lcd)
 	the_charlcd = NULL;
 	if (lcd->ops->backlight) {
 		cancel_delayed_work_sync(&priv->bl_work);
-		priv->lcd.ops->backlight(&priv->lcd, 0);
+		priv->lcd.ops->backlight(&priv->lcd, CHARLCD_OFF);
 	}
 
 	return 0;
 }
 EXPORT_SYMBOL_GPL(charlcd_unregister);
 
+MODULE_DESCRIPTION("Character LCD core support");
 MODULE_LICENSE("GPL");
diff --git a/drivers/auxdisplay/charlcd.h b/drivers/auxdisplay/charlcd.h
index 00911ad0f3de..d10b89740bca 100644
--- a/drivers/auxdisplay/charlcd.h
+++ b/drivers/auxdisplay/charlcd.h
@@ -9,30 +9,93 @@
 #ifndef _CHARLCD_H
 #define _CHARLCD_H
 
+#define LCD_FLAG_B		0x0004	/* Blink on */
+#define LCD_FLAG_C		0x0008	/* Cursor on */
+#define LCD_FLAG_D		0x0010	/* Display on */
+#define LCD_FLAG_F		0x0020	/* Large font mode */
+#define LCD_FLAG_N		0x0040	/* 2-rows mode */
+#define LCD_FLAG_L		0x0080	/* Backlight enabled */
+
+enum charlcd_onoff {
+	CHARLCD_OFF = 0,
+	CHARLCD_ON,
+};
+
+enum charlcd_shift_dir {
+	CHARLCD_SHIFT_LEFT,
+	CHARLCD_SHIFT_RIGHT,
+};
+
+enum charlcd_fontsize {
+	CHARLCD_FONTSIZE_SMALL,
+	CHARLCD_FONTSIZE_LARGE,
+};
+
+enum charlcd_lines {
+	CHARLCD_LINES_1,
+	CHARLCD_LINES_2,
+};
+
+struct charlcd_ops;
+
 struct charlcd {
 	const struct charlcd_ops *ops;
 	const unsigned char *char_conv;	/* Optional */
 
-	int ifwidth;			/* 4-bit or 8-bit (default) */
 	int height;
 	int width;
-	int bwidth;			/* Default set by charlcd_alloc() */
-	int hwidth;			/* Default set by charlcd_alloc() */
+
+	/* Contains the LCD X and Y offset */
+	struct {
+		unsigned long x;
+		unsigned long y;
+	} addr;
 
 	void *drvdata;			/* Set by charlcd_alloc() */
 };
 
+/**
+ * struct charlcd_ops - Functions used by charlcd. Drivers have to implement
+ * these.
+ * @backlight: Turn backlight on or off. Optional.
+ * @print: Print one character to the display at current cursor position.
+ * The buffered cursor position is advanced by charlcd. The cursor should not
+ * wrap to the next line at the end of a line.
+ * @gotoxy: Set cursor to x, y. The x and y values to set the cursor to are
+ * previously set in addr.x and addr.y by charlcd.
+ * @home: Set cursor to 0, 0. The values in addr.x and addr.y are set to 0, 0 by
+ * charlcd prior to calling this function.
+ * @clear_display: Clear the whole display and set the cursor to 0, 0. The
+ * values in addr.x and addr.y are set to 0, 0 by charlcd after to calling this
+ * function.
+ * @init_display: Initialize the display.
+ * @shift_cursor: Shift cursor left or right one position.
+ * @shift_display: Shift whole display content left or right.
+ * @display: Turn display on or off.
+ * @cursor: Turn cursor on or off.
+ * @blink: Turn cursor blink on or off.
+ * @lines: One or two lines.
+ * @redefine_char: Redefine the actual pixel matrix of character.
+ */
 struct charlcd_ops {
-	/* Required */
-	void (*write_cmd)(struct charlcd *lcd, int cmd);
-	void (*write_data)(struct charlcd *lcd, int data);
-
-	/* Optional */
-	void (*write_cmd_raw4)(struct charlcd *lcd, int cmd);	/* 4-bit only */
-	void (*clear_fast)(struct charlcd *lcd);
-	void (*backlight)(struct charlcd *lcd, int on);
+	void (*backlight)(struct charlcd *lcd, enum charlcd_onoff on);
+	int (*print)(struct charlcd *lcd, int c);
+	int (*gotoxy)(struct charlcd *lcd, unsigned int x, unsigned int y);
+	int (*home)(struct charlcd *lcd);
+	int (*clear_display)(struct charlcd *lcd);
+	int (*init_display)(struct charlcd *lcd);
+	int (*shift_cursor)(struct charlcd *lcd, enum charlcd_shift_dir dir);
+	int (*shift_display)(struct charlcd *lcd, enum charlcd_shift_dir dir);
+	int (*display)(struct charlcd *lcd, enum charlcd_onoff on);
+	int (*cursor)(struct charlcd *lcd, enum charlcd_onoff on);
+	int (*blink)(struct charlcd *lcd, enum charlcd_onoff on);
+	int (*fontsize)(struct charlcd *lcd, enum charlcd_fontsize size);
+	int (*lines)(struct charlcd *lcd, enum charlcd_lines lines);
+	int (*redefine_char)(struct charlcd *lcd, char *esc);
 };
 
+void charlcd_backlight(struct charlcd *lcd, enum charlcd_onoff on);
+
 struct charlcd *charlcd_alloc(unsigned int drvdata_size);
 void charlcd_free(struct charlcd *lcd);
 
diff --git a/drivers/auxdisplay/hd44780.c b/drivers/auxdisplay/hd44780.c
index bcbe13092327..cef42656c4b0 100644
--- a/drivers/auxdisplay/hd44780.c
+++ b/drivers/auxdisplay/hd44780.c
@@ -15,6 +15,7 @@
 #include <linux/slab.h>
 
 #include "charlcd.h"
+#include "hd44780_common.h"
 
 enum hd44780_pin {
 	/* Order does matter due to writing to GPIO array subsets! */
@@ -37,9 +38,10 @@ struct hd44780 {
 	struct gpio_desc *pins[PIN_NUM];
 };
 
-static void hd44780_backlight(struct charlcd *lcd, int on)
+static void hd44780_backlight(struct charlcd *lcd, enum charlcd_onoff on)
 {
-	struct hd44780 *hd = lcd->drvdata;
+	struct hd44780_common *hdc = lcd->drvdata;
+	struct hd44780 *hd = hdc->hd44780;
 
 	if (hd->pins[PIN_CTRL_BL])
 		gpiod_set_value_cansleep(hd->pins[PIN_CTRL_BL], on);
@@ -101,9 +103,9 @@ static void hd44780_write_gpio4(struct hd44780 *hd, u8 val, unsigned int rs)
 }
 
 /* Send a command to the LCD panel in 8 bit GPIO mode */
-static void hd44780_write_cmd_gpio8(struct charlcd *lcd, int cmd)
+static void hd44780_write_cmd_gpio8(struct hd44780_common *hdc, int cmd)
 {
-	struct hd44780 *hd = lcd->drvdata;
+	struct hd44780 *hd = hdc->hd44780;
 
 	hd44780_write_gpio8(hd, cmd, 0);
 
@@ -112,9 +114,9 @@ static void hd44780_write_cmd_gpio8(struct charlcd *lcd, int cmd)
 }
 
 /* Send data to the LCD panel in 8 bit GPIO mode */
-static void hd44780_write_data_gpio8(struct charlcd *lcd, int data)
+static void hd44780_write_data_gpio8(struct hd44780_common *hdc, int data)
 {
-	struct hd44780 *hd = lcd->drvdata;
+	struct hd44780 *hd = hdc->hd44780;
 
 	hd44780_write_gpio8(hd, data, 1);
 
@@ -123,15 +125,26 @@ static void hd44780_write_data_gpio8(struct charlcd *lcd, int data)
 }
 
 static const struct charlcd_ops hd44780_ops_gpio8 = {
-	.write_cmd	= hd44780_write_cmd_gpio8,
-	.write_data	= hd44780_write_data_gpio8,
 	.backlight	= hd44780_backlight,
+	.print		= hd44780_common_print,
+	.gotoxy		= hd44780_common_gotoxy,
+	.home		= hd44780_common_home,
+	.clear_display	= hd44780_common_clear_display,
+	.init_display	= hd44780_common_init_display,
+	.shift_cursor	= hd44780_common_shift_cursor,
+	.shift_display	= hd44780_common_shift_display,
+	.display	= hd44780_common_display,
+	.cursor		= hd44780_common_cursor,
+	.blink		= hd44780_common_blink,
+	.fontsize	= hd44780_common_fontsize,
+	.lines		= hd44780_common_lines,
+	.redefine_char	= hd44780_common_redefine_char,
 };
 
 /* Send a command to the LCD panel in 4 bit GPIO mode */
-static void hd44780_write_cmd_gpio4(struct charlcd *lcd, int cmd)
+static void hd44780_write_cmd_gpio4(struct hd44780_common *hdc, int cmd)
 {
-	struct hd44780 *hd = lcd->drvdata;
+	struct hd44780 *hd = hdc->hd44780;
 
 	hd44780_write_gpio4(hd, cmd, 0);
 
@@ -140,10 +153,10 @@ static void hd44780_write_cmd_gpio4(struct charlcd *lcd, int cmd)
 }
 
 /* Send 4-bits of a command to the LCD panel in raw 4 bit GPIO mode */
-static void hd44780_write_cmd_raw_gpio4(struct charlcd *lcd, int cmd)
+static void hd44780_write_cmd_raw_gpio4(struct hd44780_common *hdc, int cmd)
 {
 	DECLARE_BITMAP(values, 6); /* for DATA[4-7], RS, RW */
-	struct hd44780 *hd = lcd->drvdata;
+	struct hd44780 *hd = hdc->hd44780;
 	unsigned int n;
 
 	/* Command nibble + RS, RW */
@@ -157,9 +170,9 @@ static void hd44780_write_cmd_raw_gpio4(struct charlcd *lcd, int cmd)
 }
 
 /* Send data to the LCD panel in 4 bit GPIO mode */
-static void hd44780_write_data_gpio4(struct charlcd *lcd, int data)
+static void hd44780_write_data_gpio4(struct hd44780_common *hdc, int data)
 {
-	struct hd44780 *hd = lcd->drvdata;
+	struct hd44780 *hd = hdc->hd44780;
 
 	hd44780_write_gpio4(hd, data, 1);
 
@@ -168,10 +181,20 @@ static void hd44780_write_data_gpio4(struct charlcd *lcd, int data)
 }
 
 static const struct charlcd_ops hd44780_ops_gpio4 = {
-	.write_cmd	= hd44780_write_cmd_gpio4,
-	.write_cmd_raw4	= hd44780_write_cmd_raw_gpio4,
-	.write_data	= hd44780_write_data_gpio4,
 	.backlight	= hd44780_backlight,
+	.print		= hd44780_common_print,
+	.gotoxy		= hd44780_common_gotoxy,
+	.home		= hd44780_common_home,
+	.clear_display	= hd44780_common_clear_display,
+	.init_display	= hd44780_common_init_display,
+	.shift_cursor	= hd44780_common_shift_cursor,
+	.shift_display	= hd44780_common_shift_display,
+	.display	= hd44780_common_display,
+	.cursor		= hd44780_common_cursor,
+	.blink		= hd44780_common_blink,
+	.fontsize	= hd44780_common_fontsize,
+	.lines		= hd44780_common_lines,
+	.redefine_char	= hd44780_common_redefine_char,
 };
 
 static int hd44780_probe(struct platform_device *pdev)
@@ -179,8 +202,9 @@ static int hd44780_probe(struct platform_device *pdev)
 	struct device *dev = &pdev->dev;
 	unsigned int i, base;
 	struct charlcd *lcd;
+	struct hd44780_common *hdc;
 	struct hd44780 *hd;
-	int ifwidth, ret;
+	int ifwidth, ret = -ENOMEM;
 
 	/* Required pins */
 	ifwidth = gpiod_count(dev, "data");
@@ -198,31 +222,36 @@ static int hd44780_probe(struct platform_device *pdev)
 		return -EINVAL;
 	}
 
-	lcd = charlcd_alloc(sizeof(struct hd44780));
+	lcd = hd44780_common_alloc();
 	if (!lcd)
 		return -ENOMEM;
 
-	hd = lcd->drvdata;
+	hd = kzalloc(sizeof(*hd), GFP_KERNEL);
+	if (!hd)
+		goto fail2;
+
+	hdc = lcd->drvdata;
+	hdc->hd44780 = hd;
 
 	for (i = 0; i < ifwidth; i++) {
 		hd->pins[base + i] = devm_gpiod_get_index(dev, "data", i,
 							  GPIOD_OUT_LOW);
 		if (IS_ERR(hd->pins[base + i])) {
 			ret = PTR_ERR(hd->pins[base + i]);
-			goto fail;
+			goto fail3;
 		}
 	}
 
 	hd->pins[PIN_CTRL_E] = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);
 	if (IS_ERR(hd->pins[PIN_CTRL_E])) {
 		ret = PTR_ERR(hd->pins[PIN_CTRL_E]);
-		goto fail;
+		goto fail3;
 	}
 
 	hd->pins[PIN_CTRL_RS] = devm_gpiod_get(dev, "rs", GPIOD_OUT_HIGH);
 	if (IS_ERR(hd->pins[PIN_CTRL_RS])) {
 		ret = PTR_ERR(hd->pins[PIN_CTRL_RS]);
-		goto fail;
+		goto fail3;
 	}
 
 	/* Optional pins */
@@ -230,58 +259,69 @@ static int hd44780_probe(struct platform_device *pdev)
 							GPIOD_OUT_LOW);
 	if (IS_ERR(hd->pins[PIN_CTRL_RW])) {
 		ret = PTR_ERR(hd->pins[PIN_CTRL_RW]);
-		goto fail;
+		goto fail3;
 	}
 
 	hd->pins[PIN_CTRL_BL] = devm_gpiod_get_optional(dev, "backlight",
 							GPIOD_OUT_LOW);
 	if (IS_ERR(hd->pins[PIN_CTRL_BL])) {
 		ret = PTR_ERR(hd->pins[PIN_CTRL_BL]);
-		goto fail;
+		goto fail3;
 	}
 
 	/* Required properties */
 	ret = device_property_read_u32(dev, "display-height-chars",
 				       &lcd->height);
 	if (ret)
-		goto fail;
+		goto fail3;
 	ret = device_property_read_u32(dev, "display-width-chars", &lcd->width);
 	if (ret)
-		goto fail;
+		goto fail3;
 
 	/*
 	 * On displays with more than two rows, the internal buffer width is
 	 * usually equal to the display width
 	 */
 	if (lcd->height > 2)
-		lcd->bwidth = lcd->width;
+		hdc->bwidth = lcd->width;
 
 	/* Optional properties */
-	device_property_read_u32(dev, "internal-buffer-width", &lcd->bwidth);
-
-	lcd->ifwidth = ifwidth;
-	lcd->ops = ifwidth == 8 ? &hd44780_ops_gpio8 : &hd44780_ops_gpio4;
+	device_property_read_u32(dev, "internal-buffer-width", &hdc->bwidth);
+
+	hdc->ifwidth = ifwidth;
+	if (ifwidth == 8) {
+		lcd->ops = &hd44780_ops_gpio8;
+		hdc->write_data = hd44780_write_data_gpio8;
+		hdc->write_cmd = hd44780_write_cmd_gpio8;
+	} else {
+		lcd->ops = &hd44780_ops_gpio4;
+		hdc->write_data = hd44780_write_data_gpio4;
+		hdc->write_cmd = hd44780_write_cmd_gpio4;
+		hdc->write_cmd_raw4 = hd44780_write_cmd_raw_gpio4;
+	}
 
 	ret = charlcd_register(lcd);
 	if (ret)
-		goto fail;
+		goto fail3;
 
 	platform_set_drvdata(pdev, lcd);
 	return 0;
 
-fail:
-	charlcd_free(lcd);
+fail3:
+	kfree(hd);
+fail2:
+	hd44780_common_free(lcd);
 	return ret;
 }
 
-static int hd44780_remove(struct platform_device *pdev)
+static void hd44780_remove(struct platform_device *pdev)
 {
 	struct charlcd *lcd = platform_get_drvdata(pdev);
+	struct hd44780_common *hdc = lcd->drvdata;
 
 	charlcd_unregister(lcd);
-
-	charlcd_free(lcd);
-	return 0;
+	kfree(hdc->hd44780);
+	hd44780_common_free(lcd);
 }
 
 static const struct of_device_id hd44780_of_match[] = {
diff --git a/drivers/auxdisplay/hd44780_common.c b/drivers/auxdisplay/hd44780_common.c
new file mode 100644
index 000000000000..1792fe2a4460
--- /dev/null
+++ b/drivers/auxdisplay/hd44780_common.c
@@ -0,0 +1,378 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+
+#include "charlcd.h"
+#include "hd44780_common.h"
+
+/* LCD commands */
+#define LCD_CMD_DISPLAY_CLEAR	0x01	/* Clear entire display */
+
+#define LCD_CMD_ENTRY_MODE	0x04	/* Set entry mode */
+#define LCD_CMD_CURSOR_INC	0x02	/* Increment cursor */
+
+#define LCD_CMD_DISPLAY_CTRL	0x08	/* Display control */
+#define LCD_CMD_DISPLAY_ON	0x04	/* Set display on */
+#define LCD_CMD_CURSOR_ON	0x02	/* Set cursor on */
+#define LCD_CMD_BLINK_ON	0x01	/* Set blink on */
+
+#define LCD_CMD_SHIFT		0x10	/* Shift cursor/display */
+#define LCD_CMD_DISPLAY_SHIFT	0x08	/* Shift display instead of cursor */
+#define LCD_CMD_SHIFT_RIGHT	0x04	/* Shift display/cursor to the right */
+
+#define LCD_CMD_FUNCTION_SET	0x20	/* Set function */
+#define LCD_CMD_DATA_LEN_8BITS	0x10	/* Set data length to 8 bits */
+#define LCD_CMD_TWO_LINES	0x08	/* Set to two display lines */
+#define LCD_CMD_FONT_5X10_DOTS	0x04	/* Set char font to 5x10 dots */
+
+#define LCD_CMD_SET_CGRAM_ADDR	0x40	/* Set char generator RAM address */
+
+#define LCD_CMD_SET_DDRAM_ADDR	0x80	/* Set display data RAM address */
+
+/* sleeps that many milliseconds with a reschedule */
+static void long_sleep(int ms)
+{
+	schedule_timeout_interruptible(msecs_to_jiffies(ms));
+}
+
+int hd44780_common_print(struct charlcd *lcd, int c)
+{
+	struct hd44780_common *hdc = lcd->drvdata;
+
+	if (lcd->addr.x < hdc->bwidth) {
+		hdc->write_data(hdc, c);
+		return 0;
+	}
+
+	return 1;
+}
+EXPORT_SYMBOL_GPL(hd44780_common_print);
+
+int hd44780_common_gotoxy(struct charlcd *lcd, unsigned int x, unsigned int y)
+{
+	struct hd44780_common *hdc = lcd->drvdata;
+	unsigned int addr;
+
+	/*
+	 * we force the cursor to stay at the end of the
+	 * line if it wants to go farther
+	 */
+	addr = x < hdc->bwidth ? x & (hdc->hwidth - 1) : hdc->bwidth - 1;
+	if (y & 1)
+		addr += hdc->hwidth;
+	if (y & 2)
+		addr += hdc->bwidth;
+	hdc->write_cmd(hdc, LCD_CMD_SET_DDRAM_ADDR | addr);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(hd44780_common_gotoxy);
+
+int hd44780_common_home(struct charlcd *lcd)
+{
+	return hd44780_common_gotoxy(lcd, 0, 0);
+}
+EXPORT_SYMBOL_GPL(hd44780_common_home);
+
+/* clears the display and resets X/Y */
+int hd44780_common_clear_display(struct charlcd *lcd)
+{
+	struct hd44780_common *hdc = lcd->drvdata;
+
+	hdc->write_cmd(hdc, LCD_CMD_DISPLAY_CLEAR);
+	/* datasheet says to wait 1,64 milliseconds */
+	long_sleep(2);
+
+	/*
+	 * The Hitachi HD44780 controller (and compatible ones) reset the DDRAM
+	 * address when executing the DISPLAY_CLEAR command, thus the
+	 * following call is not required. However, other controllers do not
+	 * (e.g. NewHaven NHD-0220DZW-AG5), thus move the cursor to home
+	 * unconditionally to support both.
+	 */
+	return hd44780_common_home(lcd);
+}
+EXPORT_SYMBOL_GPL(hd44780_common_clear_display);
+
+int hd44780_common_init_display(struct charlcd *lcd)
+{
+	struct hd44780_common *hdc = lcd->drvdata;
+
+	void (*write_cmd_raw)(struct hd44780_common *hdc, int cmd);
+	u8 init;
+
+	if (hdc->ifwidth != 4 && hdc->ifwidth != 8)
+		return -EINVAL;
+
+	hdc->hd44780_common_flags = ((lcd->height > 1) ? LCD_FLAG_N : 0) |
+		LCD_FLAG_D | LCD_FLAG_C | LCD_FLAG_B;
+
+	long_sleep(20);		/* wait 20 ms after power-up for the paranoid */
+
+	/*
+	 * 8-bit mode, 1 line, small fonts; let's do it 3 times, to make sure
+	 * the LCD is in 8-bit mode afterwards
+	 */
+	init = LCD_CMD_FUNCTION_SET | LCD_CMD_DATA_LEN_8BITS;
+	if (hdc->ifwidth == 4) {
+		init >>= 4;
+		write_cmd_raw = hdc->write_cmd_raw4;
+	} else {
+		write_cmd_raw = hdc->write_cmd;
+	}
+	write_cmd_raw(hdc, init);
+	long_sleep(10);
+	write_cmd_raw(hdc, init);
+	long_sleep(10);
+	write_cmd_raw(hdc, init);
+	long_sleep(10);
+
+	if (hdc->ifwidth == 4) {
+		/* Switch to 4-bit mode, 1 line, small fonts */
+		hdc->write_cmd_raw4(hdc, LCD_CMD_FUNCTION_SET >> 4);
+		long_sleep(10);
+	}
+
+	/* set font height and lines number */
+	hdc->write_cmd(hdc,
+		LCD_CMD_FUNCTION_SET |
+		((hdc->ifwidth == 8) ? LCD_CMD_DATA_LEN_8BITS : 0) |
+		((hdc->hd44780_common_flags & LCD_FLAG_F) ?
+			LCD_CMD_FONT_5X10_DOTS : 0) |
+		((hdc->hd44780_common_flags & LCD_FLAG_N) ?
+			LCD_CMD_TWO_LINES : 0));
+	long_sleep(10);
+
+	/* display off, cursor off, blink off */
+	hdc->write_cmd(hdc, LCD_CMD_DISPLAY_CTRL);
+	long_sleep(10);
+
+	hdc->write_cmd(hdc,
+		LCD_CMD_DISPLAY_CTRL |	/* set display mode */
+		((hdc->hd44780_common_flags & LCD_FLAG_D) ?
+			LCD_CMD_DISPLAY_ON : 0) |
+		((hdc->hd44780_common_flags & LCD_FLAG_C) ?
+			LCD_CMD_CURSOR_ON : 0) |
+		((hdc->hd44780_common_flags & LCD_FLAG_B) ?
+			LCD_CMD_BLINK_ON : 0));
+
+	charlcd_backlight(lcd,
+			(hdc->hd44780_common_flags & LCD_FLAG_L) ? 1 : 0);
+
+	long_sleep(10);
+
+	/* entry mode set : increment, cursor shifting */
+	hdc->write_cmd(hdc, LCD_CMD_ENTRY_MODE | LCD_CMD_CURSOR_INC);
+
+	hd44780_common_clear_display(lcd);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(hd44780_common_init_display);
+
+int hd44780_common_shift_cursor(struct charlcd *lcd, enum charlcd_shift_dir dir)
+{
+	struct hd44780_common *hdc = lcd->drvdata;
+
+	if (dir == CHARLCD_SHIFT_LEFT) {
+		/* back one char if not at end of line */
+		if (lcd->addr.x < hdc->bwidth)
+			hdc->write_cmd(hdc, LCD_CMD_SHIFT);
+	} else if (dir == CHARLCD_SHIFT_RIGHT) {
+		/* allow the cursor to pass the end of the line */
+		if (lcd->addr.x < (hdc->bwidth - 1))
+			hdc->write_cmd(hdc,
+					LCD_CMD_SHIFT | LCD_CMD_SHIFT_RIGHT);
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(hd44780_common_shift_cursor);
+
+int hd44780_common_shift_display(struct charlcd *lcd,
+		enum charlcd_shift_dir dir)
+{
+	struct hd44780_common *hdc = lcd->drvdata;
+
+	if (dir == CHARLCD_SHIFT_LEFT)
+		hdc->write_cmd(hdc, LCD_CMD_SHIFT | LCD_CMD_DISPLAY_SHIFT);
+	else if (dir == CHARLCD_SHIFT_RIGHT)
+		hdc->write_cmd(hdc, LCD_CMD_SHIFT | LCD_CMD_DISPLAY_SHIFT |
+			LCD_CMD_SHIFT_RIGHT);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(hd44780_common_shift_display);
+
+static void hd44780_common_set_mode(struct hd44780_common *hdc)
+{
+	hdc->write_cmd(hdc,
+		LCD_CMD_DISPLAY_CTRL |
+		((hdc->hd44780_common_flags & LCD_FLAG_D) ?
+			LCD_CMD_DISPLAY_ON : 0) |
+		((hdc->hd44780_common_flags & LCD_FLAG_C) ?
+			LCD_CMD_CURSOR_ON : 0) |
+		((hdc->hd44780_common_flags & LCD_FLAG_B) ?
+			LCD_CMD_BLINK_ON : 0));
+}
+
+int hd44780_common_display(struct charlcd *lcd, enum charlcd_onoff on)
+{
+	struct hd44780_common *hdc = lcd->drvdata;
+
+	if (on == CHARLCD_ON)
+		hdc->hd44780_common_flags |= LCD_FLAG_D;
+	else
+		hdc->hd44780_common_flags &= ~LCD_FLAG_D;
+
+	hd44780_common_set_mode(hdc);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(hd44780_common_display);
+
+int hd44780_common_cursor(struct charlcd *lcd, enum charlcd_onoff on)
+{
+	struct hd44780_common *hdc = lcd->drvdata;
+
+	if (on == CHARLCD_ON)
+		hdc->hd44780_common_flags |= LCD_FLAG_C;
+	else
+		hdc->hd44780_common_flags &= ~LCD_FLAG_C;
+
+	hd44780_common_set_mode(hdc);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(hd44780_common_cursor);
+
+int hd44780_common_blink(struct charlcd *lcd, enum charlcd_onoff on)
+{
+	struct hd44780_common *hdc = lcd->drvdata;
+
+	if (on == CHARLCD_ON)
+		hdc->hd44780_common_flags |= LCD_FLAG_B;
+	else
+		hdc->hd44780_common_flags &= ~LCD_FLAG_B;
+
+	hd44780_common_set_mode(hdc);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(hd44780_common_blink);
+
+static void hd44780_common_set_function(struct hd44780_common *hdc)
+{
+	hdc->write_cmd(hdc,
+		LCD_CMD_FUNCTION_SET |
+		((hdc->ifwidth == 8) ? LCD_CMD_DATA_LEN_8BITS : 0) |
+		((hdc->hd44780_common_flags & LCD_FLAG_F) ?
+			LCD_CMD_FONT_5X10_DOTS : 0) |
+		((hdc->hd44780_common_flags & LCD_FLAG_N) ?
+			LCD_CMD_TWO_LINES : 0));
+}
+
+int hd44780_common_fontsize(struct charlcd *lcd, enum charlcd_fontsize size)
+{
+	struct hd44780_common *hdc = lcd->drvdata;
+
+	if (size == CHARLCD_FONTSIZE_LARGE)
+		hdc->hd44780_common_flags |= LCD_FLAG_F;
+	else
+		hdc->hd44780_common_flags &= ~LCD_FLAG_F;
+
+	hd44780_common_set_function(hdc);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(hd44780_common_fontsize);
+
+int hd44780_common_lines(struct charlcd *lcd, enum charlcd_lines lines)
+{
+	struct hd44780_common *hdc = lcd->drvdata;
+
+	if (lines == CHARLCD_LINES_2)
+		hdc->hd44780_common_flags |= LCD_FLAG_N;
+	else
+		hdc->hd44780_common_flags &= ~LCD_FLAG_N;
+
+	hd44780_common_set_function(hdc);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(hd44780_common_lines);
+
+int hd44780_common_redefine_char(struct charlcd *lcd, char *esc)
+{
+	/* Generator : LGcxxxxx...xx; must have <c> between '0'
+	 * and '7', representing the numerical ASCII code of the
+	 * redefined character, and <xx...xx> a sequence of 16
+	 * hex digits representing 8 bytes for each character.
+	 * Most LCDs will only use 5 lower bits of the 7 first
+	 * bytes.
+	 */
+
+	struct hd44780_common *hdc = lcd->drvdata;
+	unsigned char cgbytes[8];
+	unsigned char cgaddr;
+	int cgoffset;
+	int shift;
+	char value;
+	int addr;
+
+	if (!strchr(esc, ';'))
+		return 0;
+
+	esc++;
+
+	cgaddr = *(esc++) - '0';
+	if (cgaddr > 7)
+		return 1;
+
+	cgoffset = 0;
+	shift = 0;
+	value = 0;
+	while (*esc && cgoffset < 8) {
+		int half;
+
+		shift ^= 4;
+		half = hex_to_bin(*esc++);
+		if (half < 0)
+			continue;
+
+		value |= half << shift;
+		if (shift == 0) {
+			cgbytes[cgoffset++] = value;
+			value = 0;
+		}
+	}
+
+	hdc->write_cmd(hdc, LCD_CMD_SET_CGRAM_ADDR | (cgaddr * 8));
+	for (addr = 0; addr < cgoffset; addr++)
+		hdc->write_data(hdc, cgbytes[addr]);
+
+	/* ensures that we stop writing to CGRAM */
+	lcd->ops->gotoxy(lcd, lcd->addr.x, lcd->addr.y);
+	return 1;
+}
+EXPORT_SYMBOL_GPL(hd44780_common_redefine_char);
+
+struct charlcd *hd44780_common_alloc(void)
+{
+	struct hd44780_common *hdc;
+	struct charlcd *lcd;
+
+	lcd = charlcd_alloc(sizeof(*hdc));
+	if (!lcd)
+		return NULL;
+
+	hdc = lcd->drvdata;
+	hdc->ifwidth = 8;
+	hdc->bwidth = DEFAULT_LCD_BWIDTH;
+	hdc->hwidth = DEFAULT_LCD_HWIDTH;
+	return lcd;
+}
+EXPORT_SYMBOL_GPL(hd44780_common_alloc);
+
+void hd44780_common_free(struct charlcd *lcd)
+{
+	charlcd_free(lcd);
+}
+EXPORT_SYMBOL_GPL(hd44780_common_free);
+
+MODULE_DESCRIPTION("Common functions for HD44780 (and compatibles) LCD displays");
+MODULE_LICENSE("GPL");
diff --git a/drivers/auxdisplay/hd44780_common.h b/drivers/auxdisplay/hd44780_common.h
new file mode 100644
index 000000000000..4c87f55722b6
--- /dev/null
+++ b/drivers/auxdisplay/hd44780_common.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#define DEFAULT_LCD_BWIDTH      40
+#define DEFAULT_LCD_HWIDTH      64
+
+struct hd44780_common {
+	int ifwidth;			/* 4-bit or 8-bit (default) */
+	int bwidth;			/* Default set by hd44780_alloc() */
+	int hwidth;			/* Default set by hd44780_alloc() */
+	unsigned long hd44780_common_flags;
+	void (*write_data)(struct hd44780_common *hdc, int data);
+	void (*write_cmd)(struct hd44780_common *hdc, int cmd);
+	/* write_cmd_raw4 is for 4-bit connected displays only */
+	void (*write_cmd_raw4)(struct hd44780_common *hdc, int cmd);
+	void *hd44780;
+};
+
+int hd44780_common_print(struct charlcd *lcd, int c);
+int hd44780_common_gotoxy(struct charlcd *lcd, unsigned int x, unsigned int y);
+int hd44780_common_home(struct charlcd *lcd);
+int hd44780_common_clear_display(struct charlcd *lcd);
+int hd44780_common_init_display(struct charlcd *lcd);
+int hd44780_common_shift_cursor(struct charlcd *lcd,
+		enum charlcd_shift_dir dir);
+int hd44780_common_shift_display(struct charlcd *lcd,
+		enum charlcd_shift_dir dir);
+int hd44780_common_display(struct charlcd *lcd, enum charlcd_onoff on);
+int hd44780_common_cursor(struct charlcd *lcd, enum charlcd_onoff on);
+int hd44780_common_blink(struct charlcd *lcd, enum charlcd_onoff on);
+int hd44780_common_fontsize(struct charlcd *lcd, enum charlcd_fontsize size);
+int hd44780_common_lines(struct charlcd *lcd, enum charlcd_lines lines);
+int hd44780_common_redefine_char(struct charlcd *lcd, char *esc);
+
+struct charlcd *hd44780_common_alloc(void);
+void hd44780_common_free(struct charlcd *lcd);
diff --git a/drivers/auxdisplay/ht16k33.c b/drivers/auxdisplay/ht16k33.c
index d951d54b26f5..0b8ba754b343 100644
--- a/drivers/auxdisplay/ht16k33.c
+++ b/drivers/auxdisplay/ht16k33.c
@@ -5,27 +5,40 @@
  * Author: Robin van der Gracht <robin@protonic.nl>
  *
  * Copyright: (C) 2016 Protonic Holland.
+ * Copyright (C) 2021 Glider bv
  */
 
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/interrupt.h>
 #include <linux/i2c.h>
-#include <linux/of.h>
+#include <linux/property.h>
 #include <linux/fb.h>
-#include <linux/slab.h>
 #include <linux/backlight.h>
+#include <linux/container_of.h>
 #include <linux/input.h>
 #include <linux/input/matrix_keypad.h>
+#include <linux/leds.h>
 #include <linux/workqueue.h>
 #include <linux/mm.h>
 
+#include <linux/map_to_7segment.h>
+#include <linux/map_to_14segment.h>
+
+#include <linux/unaligned.h>
+
+#include "line-display.h"
+
 /* Registers */
 #define REG_SYSTEM_SETUP		0x20
 #define REG_SYSTEM_SETUP_OSC_ON		BIT(0)
 
 #define REG_DISPLAY_SETUP		0x80
 #define REG_DISPLAY_SETUP_ON		BIT(0)
+#define REG_DISPLAY_SETUP_BLINK_OFF	(0 << 1)
+#define REG_DISPLAY_SETUP_BLINK_2HZ	(1 << 1)
+#define REG_DISPLAY_SETUP_BLINK_1HZ	(2 << 1)
+#define REG_DISPLAY_SETUP_BLINK_0HZ5	(3 << 1)
 
 #define REG_ROWINT_SET			0xA0
 #define REG_ROWINT_SET_INT_EN		BIT(0)
@@ -47,6 +60,12 @@
 #define BYTES_PER_ROW		(HT16K33_MATRIX_LED_MAX_ROWS / 8)
 #define HT16K33_FB_SIZE		(HT16K33_MATRIX_LED_MAX_COLS * BYTES_PER_ROW)
 
+enum display_type {
+	DISP_MATRIX = 0,
+	DISP_QUAD_7SEG,
+	DISP_QUAD_14SEG,
+};
+
 struct ht16k33_keypad {
 	struct i2c_client *client;
 	struct input_dev *dev;
@@ -65,15 +84,30 @@ struct ht16k33_fbdev {
 	uint32_t refresh_rate;
 	uint8_t *buffer;
 	uint8_t *cache;
-	struct delayed_work work;
 };
 
 struct ht16k33_priv {
 	struct i2c_client *client;
+	struct delayed_work work;
+	struct led_classdev led;
 	struct ht16k33_keypad keypad;
-	struct ht16k33_fbdev fbdev;
+	union {
+		struct ht16k33_fbdev fbdev;
+		struct linedisp linedisp;
+	};
+	enum display_type type;
+	uint8_t blink;
 };
 
+#define ht16k33_work_to_priv(p)				\
+	container_of(p, struct ht16k33_priv, work.work)
+
+#define ht16k33_led_to_priv(p)				\
+	container_of(p, struct ht16k33_priv, led)
+
+#define ht16k33_linedisp_to_priv(p)			\
+	container_of(p, struct ht16k33_priv, linedisp)
+
 static const struct fb_fix_screeninfo ht16k33_fb_fix = {
 	.id		= DRIVER_NAME,
 	.type		= FB_TYPE_PACKED_PIXELS,
@@ -103,7 +137,7 @@ static const struct fb_var_screeninfo ht16k33_fb_var = {
 
 static int ht16k33_display_on(struct ht16k33_priv *priv)
 {
-	uint8_t data = REG_DISPLAY_SETUP | REG_DISPLAY_SETUP_ON;
+	uint8_t data = REG_DISPLAY_SETUP | REG_DISPLAY_SETUP_ON | priv->blink;
 
 	return i2c_smbus_write_byte(priv->client, data);
 }
@@ -113,12 +147,70 @@ static int ht16k33_display_off(struct ht16k33_priv *priv)
 	return i2c_smbus_write_byte(priv->client, REG_DISPLAY_SETUP);
 }
 
+static int ht16k33_brightness_set(struct ht16k33_priv *priv,
+				  unsigned int brightness)
+{
+	int err;
+
+	if (brightness == 0) {
+		priv->blink = REG_DISPLAY_SETUP_BLINK_OFF;
+		return ht16k33_display_off(priv);
+	}
+
+	err = ht16k33_display_on(priv);
+	if (err)
+		return err;
+
+	return i2c_smbus_write_byte(priv->client,
+				    REG_BRIGHTNESS | (brightness - 1));
+}
+
+static int ht16k33_brightness_set_blocking(struct led_classdev *led_cdev,
+					   enum led_brightness brightness)
+{
+	struct ht16k33_priv *priv = ht16k33_led_to_priv(led_cdev);
+
+	return ht16k33_brightness_set(priv, brightness);
+}
+
+static int ht16k33_blink_set(struct led_classdev *led_cdev,
+			     unsigned long *delay_on, unsigned long *delay_off)
+{
+	struct ht16k33_priv *priv = ht16k33_led_to_priv(led_cdev);
+	unsigned int delay;
+	uint8_t blink;
+	int err;
+
+	if (!*delay_on && !*delay_off) {
+		blink = REG_DISPLAY_SETUP_BLINK_1HZ;
+		delay = 1000;
+	} else if (*delay_on <= 750) {
+		blink = REG_DISPLAY_SETUP_BLINK_2HZ;
+		delay = 500;
+	} else if (*delay_on <= 1500) {
+		blink = REG_DISPLAY_SETUP_BLINK_1HZ;
+		delay = 1000;
+	} else {
+		blink = REG_DISPLAY_SETUP_BLINK_0HZ5;
+		delay = 2000;
+	}
+
+	err = i2c_smbus_write_byte(priv->client,
+				   REG_DISPLAY_SETUP | REG_DISPLAY_SETUP_ON |
+				   blink);
+	if (err)
+		return err;
+
+	priv->blink = blink;
+	*delay_on = *delay_off = delay;
+	return 0;
+}
+
 static void ht16k33_fb_queue(struct ht16k33_priv *priv)
 {
 	struct ht16k33_fbdev *fbdev = &priv->fbdev;
 
-	schedule_delayed_work(&fbdev->work,
-			      msecs_to_jiffies(HZ / fbdev->refresh_rate));
+	schedule_delayed_work(&priv->work, HZ / fbdev->refresh_rate);
 }
 
 /*
@@ -126,10 +218,8 @@ static void ht16k33_fb_queue(struct ht16k33_priv *priv)
  */
 static void ht16k33_fb_update(struct work_struct *work)
 {
-	struct ht16k33_fbdev *fbdev =
-		container_of(work, struct ht16k33_fbdev, work.work);
-	struct ht16k33_priv *priv =
-		container_of(fbdev, struct ht16k33_priv, fbdev);
+	struct ht16k33_priv *priv = ht16k33_work_to_priv(work);
+	struct ht16k33_fbdev *fbdev = &priv->fbdev;
 
 	uint8_t *p1, *p2;
 	int len, pos = 0, first = -1;
@@ -169,9 +259,9 @@ requeue:
 
 static int ht16k33_initialize(struct ht16k33_priv *priv)
 {
+	uint8_t data[HT16K33_FB_SIZE];
 	uint8_t byte;
 	int err;
-	uint8_t data[HT16K33_MATRIX_LED_MAX_COLS * 2];
 
 	/* Clear RAM (8 * 16 bits) */
 	memset(data, 0, sizeof(data));
@@ -194,47 +284,40 @@ static int ht16k33_initialize(struct ht16k33_priv *priv)
 
 static int ht16k33_bl_update_status(struct backlight_device *bl)
 {
-	int brightness = bl->props.brightness;
+	const int brightness = backlight_get_brightness(bl);
 	struct ht16k33_priv *priv = bl_get_data(bl);
 
-	if (bl->props.power != FB_BLANK_UNBLANK ||
-	    bl->props.fb_blank != FB_BLANK_UNBLANK ||
-	    bl->props.state & BL_CORE_FBBLANK || brightness == 0) {
-		return ht16k33_display_off(priv);
-	}
-
-	ht16k33_display_on(priv);
-	return i2c_smbus_write_byte(priv->client,
-				    REG_BRIGHTNESS | (brightness - 1));
-}
-
-static int ht16k33_bl_check_fb(struct backlight_device *bl, struct fb_info *fi)
-{
-	struct ht16k33_priv *priv = bl_get_data(bl);
-
-	return (fi == NULL) || (fi->par == priv);
+	return ht16k33_brightness_set(priv, brightness);
 }
 
 static const struct backlight_ops ht16k33_bl_ops = {
 	.update_status	= ht16k33_bl_update_status,
-	.check_fb	= ht16k33_bl_check_fb,
 };
 
+/*
+ * Blank events will be passed to the actual device handling the backlight when
+ * we return zero here.
+ */
+static int ht16k33_blank(int blank, struct fb_info *info)
+{
+	return 0;
+}
+
 static int ht16k33_mmap(struct fb_info *info, struct vm_area_struct *vma)
 {
 	struct ht16k33_priv *priv = info->par;
 	struct page *pages = virt_to_page(priv->fbdev.buffer);
 
+	vma->vm_page_prot = pgprot_decrypted(vma->vm_page_prot);
+
 	return vm_map_pages_zero(vma, &pages, 1);
 }
 
 static const struct fb_ops ht16k33_fb_ops = {
 	.owner = THIS_MODULE,
-	.fb_read = fb_sys_read,
-	.fb_write = fb_sys_write,
-	.fb_fillrect = sys_fillrect,
-	.fb_copyarea = sys_copyarea,
-	.fb_imageblit = sys_imageblit,
+	__FB_DEFAULT_SYSMEM_OPS_RDWR,
+	.fb_blank = ht16k33_blank,
+	__FB_DEFAULT_SYSMEM_OPS_DRAW,
 	.fb_mmap = ht16k33_mmap,
 };
 
@@ -314,10 +397,103 @@ static void ht16k33_keypad_stop(struct input_dev *dev)
 	disable_irq(keypad->client->irq);
 }
 
+static void ht16k33_seg7_update(struct work_struct *work)
+{
+	struct ht16k33_priv *priv = ht16k33_work_to_priv(work);
+	struct linedisp_map *map = priv->linedisp.map;
+	char *s = priv->linedisp.buf;
+	uint8_t buf[9];
+
+	buf[0] = map_to_seg7(&map->map.seg7, *s++);
+	buf[1] = 0;
+	buf[2] = map_to_seg7(&map->map.seg7, *s++);
+	buf[3] = 0;
+	buf[4] = 0;
+	buf[5] = 0;
+	buf[6] = map_to_seg7(&map->map.seg7, *s++);
+	buf[7] = 0;
+	buf[8] = map_to_seg7(&map->map.seg7, *s++);
+
+	i2c_smbus_write_i2c_block_data(priv->client, 0, ARRAY_SIZE(buf), buf);
+}
+
+static void ht16k33_seg14_update(struct work_struct *work)
+{
+	struct ht16k33_priv *priv = ht16k33_work_to_priv(work);
+	struct linedisp_map *map = priv->linedisp.map;
+	char *s = priv->linedisp.buf;
+	uint8_t buf[8];
+
+	put_unaligned_le16(map_to_seg14(&map->map.seg14, *s++), buf + 0);
+	put_unaligned_le16(map_to_seg14(&map->map.seg14, *s++), buf + 2);
+	put_unaligned_le16(map_to_seg14(&map->map.seg14, *s++), buf + 4);
+	put_unaligned_le16(map_to_seg14(&map->map.seg14, *s++), buf + 6);
+
+	i2c_smbus_write_i2c_block_data(priv->client, 0, ARRAY_SIZE(buf), buf);
+}
+
+static int ht16k33_linedisp_get_map_type(struct linedisp *linedisp)
+{
+	struct ht16k33_priv *priv = ht16k33_linedisp_to_priv(linedisp);
+
+	switch (priv->type) {
+	case DISP_QUAD_7SEG:
+		INIT_DELAYED_WORK(&priv->work, ht16k33_seg7_update);
+		return LINEDISP_MAP_SEG7;
+
+	case DISP_QUAD_14SEG:
+		INIT_DELAYED_WORK(&priv->work, ht16k33_seg14_update);
+		return LINEDISP_MAP_SEG14;
+
+	default:
+		return -EINVAL;
+	}
+}
+
+static void ht16k33_linedisp_update(struct linedisp *linedisp)
+{
+	struct ht16k33_priv *priv = ht16k33_linedisp_to_priv(linedisp);
+
+	schedule_delayed_work(&priv->work, 0);
+}
+
+static const struct linedisp_ops ht16k33_linedisp_ops = {
+	.get_map_type = ht16k33_linedisp_get_map_type,
+	.update = ht16k33_linedisp_update,
+};
+
+static int ht16k33_led_probe(struct device *dev, struct led_classdev *led,
+			     unsigned int brightness)
+{
+	struct led_init_data init_data = {};
+	int err;
+
+	/* The LED is optional */
+	init_data.fwnode = device_get_named_child_node(dev, "led");
+	if (!init_data.fwnode)
+		return 0;
+
+	init_data.devicename = "auxdisplay";
+	init_data.devname_mandatory = true;
+
+	led->brightness_set_blocking = ht16k33_brightness_set_blocking;
+	led->blink_set = ht16k33_blink_set;
+	led->flags = LED_CORE_SUSPENDRESUME;
+	led->brightness = brightness;
+	led->max_brightness = MAX_BRIGHTNESS;
+
+	err = devm_led_classdev_register_ext(dev, led, &init_data);
+	fwnode_handle_put(init_data.fwnode);
+	if (err)
+		dev_err(dev, "Failed to register LED\n");
+
+	return err;
+}
+
 static int ht16k33_keypad_probe(struct i2c_client *client,
 				struct ht16k33_keypad *keypad)
 {
-	struct device_node *node = client->dev.of_node;
+	struct device *dev = &client->dev;
 	u32 rows = HT16K33_MATRIX_KEYPAD_MAX_ROWS;
 	u32 cols = HT16K33_MATRIX_KEYPAD_MAX_COLS;
 	int err;
@@ -325,7 +501,7 @@ static int ht16k33_keypad_probe(struct i2c_client *client,
 	keypad->client = client;
 	init_waitqueue_head(&keypad->wait);
 
-	keypad->dev = devm_input_allocate_device(&client->dev);
+	keypad->dev = devm_input_allocate_device(dev);
 	if (!keypad->dev)
 		return -ENOMEM;
 
@@ -336,23 +512,23 @@ static int ht16k33_keypad_probe(struct i2c_client *client,
 	keypad->dev->open = ht16k33_keypad_start;
 	keypad->dev->close = ht16k33_keypad_stop;
 
-	if (!of_get_property(node, "linux,no-autorepeat", NULL))
+	if (!device_property_read_bool(dev, "linux,no-autorepeat"))
 		__set_bit(EV_REP, keypad->dev->evbit);
 
-	err = of_property_read_u32(node, "debounce-delay-ms",
-				   &keypad->debounce_ms);
+	err = device_property_read_u32(dev, "debounce-delay-ms",
+				       &keypad->debounce_ms);
 	if (err) {
-		dev_err(&client->dev, "key debounce delay not specified\n");
+		dev_err(dev, "key debounce delay not specified\n");
 		return err;
 	}
 
-	err = matrix_keypad_parse_of_params(&client->dev, &rows, &cols);
+	err = matrix_keypad_parse_properties(dev, &rows, &cols);
 	if (err)
 		return err;
 	if (rows > HT16K33_MATRIX_KEYPAD_MAX_ROWS ||
 	    cols > HT16K33_MATRIX_KEYPAD_MAX_COLS) {
-		dev_err(&client->dev, "%u rows or %u cols out of range in DT\n",
-			rows, cols);
+		dev_err(dev, "%u rows or %u cols out of range in DT\n", rows,
+			cols);
 		return -ERANGE;
 	}
 
@@ -363,168 +539,230 @@ static int ht16k33_keypad_probe(struct i2c_client *client,
 	err = matrix_keypad_build_keymap(NULL, NULL, rows, cols, NULL,
 					 keypad->dev);
 	if (err) {
-		dev_err(&client->dev, "failed to build keymap\n");
+		dev_err(dev, "failed to build keymap\n");
 		return err;
 	}
 
-	err = devm_request_threaded_irq(&client->dev, client->irq,
-					NULL, ht16k33_keypad_irq_thread,
+	err = devm_request_threaded_irq(dev, client->irq, NULL,
+					ht16k33_keypad_irq_thread,
 					IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
 					DRIVER_NAME, keypad);
 	if (err) {
-		dev_err(&client->dev, "irq request failed %d, error %d\n",
-			client->irq, err);
+		dev_err(dev, "irq request failed %d, error %d\n", client->irq,
+			err);
 		return err;
 	}
 
 	ht16k33_keypad_stop(keypad->dev);
 
-	err = input_register_device(keypad->dev);
-	if (err)
-		return err;
-
-	return 0;
+	return input_register_device(keypad->dev);
 }
 
-static int ht16k33_probe(struct i2c_client *client,
-				  const struct i2c_device_id *id)
+static int ht16k33_fbdev_probe(struct device *dev, struct ht16k33_priv *priv,
+			       uint32_t brightness)
 {
+	struct ht16k33_fbdev *fbdev = &priv->fbdev;
+	struct backlight_device *bl = NULL;
 	int err;
-	uint32_t dft_brightness;
-	struct backlight_device *bl;
-	struct backlight_properties bl_props;
-	struct ht16k33_priv *priv;
-	struct ht16k33_fbdev *fbdev;
-	struct device_node *node = client->dev.of_node;
 
-	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
-		dev_err(&client->dev, "i2c_check_functionality error\n");
-		return -EIO;
-	}
+	if (priv->led.dev) {
+		err = ht16k33_brightness_set(priv, brightness);
+		if (err)
+			return err;
+	} else {
+		/* backwards compatibility with DT lacking an led subnode */
+		struct backlight_properties bl_props;
+
+		memset(&bl_props, 0, sizeof(struct backlight_properties));
+		bl_props.type = BACKLIGHT_RAW;
+		bl_props.max_brightness = MAX_BRIGHTNESS;
+
+		bl = devm_backlight_device_register(dev, DRIVER_NAME"-bl", dev,
+						    priv, &ht16k33_bl_ops,
+						    &bl_props);
+		if (IS_ERR(bl)) {
+			dev_err(dev, "failed to register backlight\n");
+			return PTR_ERR(bl);
+		}
 
-	if (client->irq <= 0) {
-		dev_err(&client->dev, "No IRQ specified\n");
-		return -EINVAL;
+		bl->props.brightness = brightness;
+		ht16k33_bl_update_status(bl);
 	}
 
-	priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
-	if (!priv)
-		return -ENOMEM;
-
-	priv->client = client;
-	i2c_set_clientdata(client, priv);
-	fbdev = &priv->fbdev;
-
-	err = ht16k33_initialize(priv);
-	if (err)
-		return err;
-
 	/* Framebuffer (2 bytes per column) */
 	BUILD_BUG_ON(PAGE_SIZE < HT16K33_FB_SIZE);
 	fbdev->buffer = (unsigned char *) get_zeroed_page(GFP_KERNEL);
 	if (!fbdev->buffer)
 		return -ENOMEM;
 
-	fbdev->cache = devm_kmalloc(&client->dev, HT16K33_FB_SIZE, GFP_KERNEL);
+	fbdev->cache = devm_kmalloc(dev, HT16K33_FB_SIZE, GFP_KERNEL);
 	if (!fbdev->cache) {
 		err = -ENOMEM;
 		goto err_fbdev_buffer;
 	}
 
-	fbdev->info = framebuffer_alloc(0, &client->dev);
+	fbdev->info = framebuffer_alloc(0, dev);
 	if (!fbdev->info) {
 		err = -ENOMEM;
 		goto err_fbdev_buffer;
 	}
 
-	err = of_property_read_u32(node, "refresh-rate-hz",
-		&fbdev->refresh_rate);
+	err = device_property_read_u32(dev, "refresh-rate-hz",
+				       &fbdev->refresh_rate);
 	if (err) {
-		dev_err(&client->dev, "refresh rate not specified\n");
+		dev_err(dev, "refresh rate not specified\n");
 		goto err_fbdev_info;
 	}
 	fb_bl_default_curve(fbdev->info, 0, MIN_BRIGHTNESS, MAX_BRIGHTNESS);
 
-	INIT_DELAYED_WORK(&fbdev->work, ht16k33_fb_update);
+	INIT_DELAYED_WORK(&priv->work, ht16k33_fb_update);
 	fbdev->info->fbops = &ht16k33_fb_ops;
-	fbdev->info->screen_base = (char __iomem *) fbdev->buffer;
+	fbdev->info->flags |= FBINFO_VIRTFB;
+	fbdev->info->screen_buffer = fbdev->buffer;
 	fbdev->info->screen_size = HT16K33_FB_SIZE;
 	fbdev->info->fix = ht16k33_fb_fix;
 	fbdev->info->var = ht16k33_fb_var;
+	fbdev->info->bl_dev = bl;
 	fbdev->info->pseudo_palette = NULL;
-	fbdev->info->flags = FBINFO_FLAG_DEFAULT;
 	fbdev->info->par = priv;
 
 	err = register_framebuffer(fbdev->info);
 	if (err)
 		goto err_fbdev_info;
 
-	err = ht16k33_keypad_probe(client, &priv->keypad);
+	ht16k33_fb_queue(priv);
+	return 0;
+
+err_fbdev_info:
+	framebuffer_release(fbdev->info);
+err_fbdev_buffer:
+	free_page((unsigned long) fbdev->buffer);
+
+	return err;
+}
+
+static int ht16k33_seg_probe(struct device *dev, struct ht16k33_priv *priv,
+			     uint32_t brightness)
+{
+	struct linedisp *linedisp = &priv->linedisp;
+	int err;
+
+	err = ht16k33_brightness_set(priv, brightness);
 	if (err)
-		goto err_fbdev_unregister;
-
-	/* Backlight */
-	memset(&bl_props, 0, sizeof(struct backlight_properties));
-	bl_props.type = BACKLIGHT_RAW;
-	bl_props.max_brightness = MAX_BRIGHTNESS;
-
-	bl = devm_backlight_device_register(&client->dev, DRIVER_NAME"-bl",
-					    &client->dev, priv,
-					    &ht16k33_bl_ops, &bl_props);
-	if (IS_ERR(bl)) {
-		dev_err(&client->dev, "failed to register backlight\n");
-		err = PTR_ERR(bl);
-		goto err_fbdev_unregister;
+		return err;
+
+	return linedisp_register(linedisp, dev, 4, &ht16k33_linedisp_ops);
+}
+
+static int ht16k33_probe(struct i2c_client *client)
+{
+	struct device *dev = &client->dev;
+	struct ht16k33_priv *priv;
+	uint32_t dft_brightness;
+	int err;
+
+	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
+		dev_err(dev, "i2c_check_functionality error\n");
+		return -EIO;
 	}
 
-	err = of_property_read_u32(node, "default-brightness-level",
-				   &dft_brightness);
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->client = client;
+	priv->type = (uintptr_t)i2c_get_match_data(client);
+
+	i2c_set_clientdata(client, priv);
+
+	err = ht16k33_initialize(priv);
+	if (err)
+		return err;
+
+	err = device_property_read_u32(dev, "default-brightness-level",
+				       &dft_brightness);
 	if (err) {
 		dft_brightness = MAX_BRIGHTNESS;
 	} else if (dft_brightness > MAX_BRIGHTNESS) {
-		dev_warn(&client->dev,
+		dev_warn(dev,
 			 "invalid default brightness level: %u, using %u\n",
 			 dft_brightness, MAX_BRIGHTNESS);
 		dft_brightness = MAX_BRIGHTNESS;
 	}
 
-	bl->props.brightness = dft_brightness;
-	ht16k33_bl_update_status(bl);
+	/* LED */
+	err = ht16k33_led_probe(dev, &priv->led, dft_brightness);
+	if (err)
+		return err;
 
-	ht16k33_fb_queue(priv);
-	return 0;
+	/* Keypad */
+	if (client->irq > 0) {
+		err = ht16k33_keypad_probe(client, &priv->keypad);
+		if (err)
+			return err;
+	}
 
-err_fbdev_unregister:
-	unregister_framebuffer(fbdev->info);
-err_fbdev_info:
-	framebuffer_release(fbdev->info);
-err_fbdev_buffer:
-	free_page((unsigned long) fbdev->buffer);
+	switch (priv->type) {
+	case DISP_MATRIX:
+		/* Frame Buffer Display */
+		err = ht16k33_fbdev_probe(dev, priv, dft_brightness);
+		break;
 
+	case DISP_QUAD_7SEG:
+	case DISP_QUAD_14SEG:
+		/* Segment Display */
+		err = ht16k33_seg_probe(dev, priv, dft_brightness);
+		break;
+
+	default:
+		return -EINVAL;
+	}
 	return err;
 }
 
-static int ht16k33_remove(struct i2c_client *client)
+static void ht16k33_remove(struct i2c_client *client)
 {
 	struct ht16k33_priv *priv = i2c_get_clientdata(client);
 	struct ht16k33_fbdev *fbdev = &priv->fbdev;
 
-	cancel_delayed_work_sync(&fbdev->work);
-	unregister_framebuffer(fbdev->info);
-	framebuffer_release(fbdev->info);
-	free_page((unsigned long) fbdev->buffer);
+	cancel_delayed_work_sync(&priv->work);
 
-	return 0;
+	switch (priv->type) {
+	case DISP_MATRIX:
+		unregister_framebuffer(fbdev->info);
+		framebuffer_release(fbdev->info);
+		free_page((unsigned long)fbdev->buffer);
+		break;
+
+	case DISP_QUAD_7SEG:
+	case DISP_QUAD_14SEG:
+		linedisp_unregister(&priv->linedisp);
+		break;
+
+	default:
+		break;
+	}
 }
 
 static const struct i2c_device_id ht16k33_i2c_match[] = {
-	{ "ht16k33", 0 },
+	{ "3108", DISP_QUAD_7SEG },
+	{ "3130", DISP_QUAD_14SEG },
+	{ "ht16k33", DISP_MATRIX },
 	{ }
 };
 MODULE_DEVICE_TABLE(i2c, ht16k33_i2c_match);
 
 static const struct of_device_id ht16k33_of_match[] = {
-	{ .compatible = "holtek,ht16k33", },
+	{
+		/* 0.56" 4-Digit 7-Segment FeatherWing Display (Red) */
+		.compatible = "adafruit,3108", .data = (void *)DISP_QUAD_7SEG,
+	}, {
+		/* 0.54" Quad Alphanumeric FeatherWing Display (Red) */
+		.compatible = "adafruit,3130", .data = (void *)DISP_QUAD_14SEG,
+	}, {
+		/* Generic, assumed Dot-Matrix Display */
+		.compatible = "holtek,ht16k33", .data = (void *)DISP_MATRIX,
+	},
 	{ }
 };
 MODULE_DEVICE_TABLE(of, ht16k33_of_match);
@@ -534,7 +772,7 @@ static struct i2c_driver ht16k33_driver = {
 	.remove		= ht16k33_remove,
 	.driver		= {
 		.name		= DRIVER_NAME,
-		.of_match_table	= of_match_ptr(ht16k33_of_match),
+		.of_match_table	= ht16k33_of_match,
 	},
 	.id_table = ht16k33_i2c_match,
 };
@@ -542,4 +780,5 @@ module_i2c_driver(ht16k33_driver);
 
 MODULE_DESCRIPTION("Holtek HT16K33 driver");
 MODULE_LICENSE("GPL");
+MODULE_IMPORT_NS("LINEDISP");
 MODULE_AUTHOR("Robin van der Gracht <robin@protonic.nl>");
diff --git a/drivers/auxdisplay/img-ascii-lcd.c b/drivers/auxdisplay/img-ascii-lcd.c
index 1cce409ce5ca..32e1863ef4b2 100644
--- a/drivers/auxdisplay/img-ascii-lcd.c
+++ b/drivers/auxdisplay/img-ascii-lcd.c
@@ -4,17 +4,17 @@
  * Author: Paul Burton <paul.burton@mips.com>
  */
 
-#include <generated/utsrelease.h>
 #include <linux/kernel.h>
 #include <linux/io.h>
 #include <linux/mfd/syscon.h>
 #include <linux/module.h>
-#include <linux/of_address.h>
-#include <linux/of_platform.h>
+#include <linux/of.h>
 #include <linux/platform_device.h>
+#include <linux/property.h>
 #include <linux/regmap.h>
 #include <linux/slab.h>
-#include <linux/sysfs.h>
+
+#include "line-display.h"
 
 struct img_ascii_lcd_ctx;
 
@@ -22,82 +22,74 @@ struct img_ascii_lcd_ctx;
  * struct img_ascii_lcd_config - Configuration information about an LCD model
  * @num_chars: the number of characters the LCD can display
  * @external_regmap: true if registers are in a system controller, else false
- * @update: function called to update the LCD
+ * @ops: character line display operations
  */
 struct img_ascii_lcd_config {
 	unsigned int num_chars;
 	bool external_regmap;
-	void (*update)(struct img_ascii_lcd_ctx *ctx);
+	const struct linedisp_ops ops;
 };
 
 /**
  * struct img_ascii_lcd_ctx - Private data structure
- * @pdev: the ASCII LCD platform device
+ * @linedisp: line display structure
  * @base: the base address of the LCD registers
  * @regmap: the regmap through which LCD registers are accessed
  * @offset: the offset within regmap to the start of the LCD registers
- * @cfg: pointer to the LCD model configuration
- * @message: the full message to display or scroll on the LCD
- * @message_len: the length of the @message string
- * @scroll_pos: index of the first character of @message currently displayed
- * @scroll_rate: scroll interval in jiffies
- * @timer: timer used to implement scrolling
- * @curr: the string currently displayed on the LCD
  */
 struct img_ascii_lcd_ctx {
-	struct platform_device *pdev;
+	struct linedisp linedisp;
 	union {
 		void __iomem *base;
 		struct regmap *regmap;
 	};
 	u32 offset;
-	const struct img_ascii_lcd_config *cfg;
-	char *message;
-	unsigned int message_len;
-	unsigned int scroll_pos;
-	unsigned int scroll_rate;
-	struct timer_list timer;
-	char curr[] __aligned(8);
 };
 
 /*
  * MIPS Boston development board
  */
 
-static void boston_update(struct img_ascii_lcd_ctx *ctx)
+static void boston_update(struct linedisp *linedisp)
 {
+	struct img_ascii_lcd_ctx *ctx =
+		container_of(linedisp, struct img_ascii_lcd_ctx, linedisp);
 	ulong val;
 
 #if BITS_PER_LONG == 64
-	val = *((u64 *)&ctx->curr[0]);
+	val = *((u64 *)&linedisp->buf[0]);
 	__raw_writeq(val, ctx->base);
 #elif BITS_PER_LONG == 32
-	val = *((u32 *)&ctx->curr[0]);
+	val = *((u32 *)&linedisp->buf[0]);
 	__raw_writel(val, ctx->base);
-	val = *((u32 *)&ctx->curr[4]);
+	val = *((u32 *)&linedisp->buf[4]);
 	__raw_writel(val, ctx->base + 4);
 #else
 # error Not 32 or 64 bit
 #endif
 }
 
-static struct img_ascii_lcd_config boston_config = {
+static const struct img_ascii_lcd_config boston_config = {
 	.num_chars = 8,
-	.update = boston_update,
+	.ops = {
+		.update = boston_update,
+	},
 };
 
 /*
  * MIPS Malta development board
  */
 
-static void malta_update(struct img_ascii_lcd_ctx *ctx)
+static void malta_update(struct linedisp *linedisp)
 {
+	struct img_ascii_lcd_ctx *ctx =
+		container_of(linedisp, struct img_ascii_lcd_ctx, linedisp);
 	unsigned int i;
 	int err = 0;
 
-	for (i = 0; i < ctx->cfg->num_chars; i++) {
+	for (i = 0; i < linedisp->num_chars; i++) {
 		err = regmap_write(ctx->regmap,
-				   ctx->offset + (i * 8), ctx->curr[i]);
+				   ctx->offset + (i * 8), linedisp->buf[i]);
 		if (err)
 			break;
 	}
@@ -106,10 +98,12 @@ static void malta_update(struct img_ascii_lcd_ctx *ctx)
 		pr_err_ratelimited("Failed to update LCD display: %d\n", err);
 }
 
-static struct img_ascii_lcd_config malta_config = {
+static const struct img_ascii_lcd_config malta_config = {
 	.num_chars = 8,
 	.external_regmap = true,
-	.update = malta_update,
+	.ops = {
+		.update = malta_update,
+	},
 };
 
 /*
@@ -173,12 +167,14 @@ static int sead3_wait_lcd_idle(struct img_ascii_lcd_ctx *ctx)
 	return 0;
 }
 
-static void sead3_update(struct img_ascii_lcd_ctx *ctx)
+static void sead3_update(struct linedisp *linedisp)
 {
+	struct img_ascii_lcd_ctx *ctx =
+		container_of(linedisp, struct img_ascii_lcd_ctx, linedisp);
 	unsigned int i;
 	int err = 0;
 
-	for (i = 0; i < ctx->cfg->num_chars; i++) {
+	for (i = 0; i < linedisp->num_chars; i++) {
 		err = sead3_wait_lcd_idle(ctx);
 		if (err)
 			break;
@@ -195,7 +191,7 @@ static void sead3_update(struct img_ascii_lcd_ctx *ctx)
 
 		err = regmap_write(ctx->regmap,
 				   ctx->offset + SEAD3_REG_LCD_DATA,
-				   ctx->curr[i]);
+				   linedisp->buf[i]);
 		if (err)
 			break;
 	}
@@ -204,10 +200,12 @@ static void sead3_update(struct img_ascii_lcd_ctx *ctx)
 		pr_err_ratelimited("Failed to update LCD display: %d\n", err);
 }
 
-static struct img_ascii_lcd_config sead3_config = {
+static const struct img_ascii_lcd_config sead3_config = {
 	.num_chars = 16,
 	.external_regmap = true,
-	.update = sead3_update,
+	.ops = {
+		.update = sead3_update,
+	},
 };
 
 static const struct of_device_id img_ascii_lcd_matches[] = {
@@ -219,130 +217,6 @@ static const struct of_device_id img_ascii_lcd_matches[] = {
 MODULE_DEVICE_TABLE(of, img_ascii_lcd_matches);
 
 /**
- * img_ascii_lcd_scroll() - scroll the display by a character
- * @t: really a pointer to the private data structure
- *
- * Scroll the current message along the LCD by one character, rearming the
- * timer if required.
- */
-static void img_ascii_lcd_scroll(struct timer_list *t)
-{
-	struct img_ascii_lcd_ctx *ctx = from_timer(ctx, t, timer);
-	unsigned int i, ch = ctx->scroll_pos;
-	unsigned int num_chars = ctx->cfg->num_chars;
-
-	/* update the current message string */
-	for (i = 0; i < num_chars;) {
-		/* copy as many characters from the string as possible */
-		for (; i < num_chars && ch < ctx->message_len; i++, ch++)
-			ctx->curr[i] = ctx->message[ch];
-
-		/* wrap around to the start of the string */
-		ch = 0;
-	}
-
-	/* update the LCD */
-	ctx->cfg->update(ctx);
-
-	/* move on to the next character */
-	ctx->scroll_pos++;
-	ctx->scroll_pos %= ctx->message_len;
-
-	/* rearm the timer */
-	if (ctx->message_len > ctx->cfg->num_chars)
-		mod_timer(&ctx->timer, jiffies + ctx->scroll_rate);
-}
-
-/**
- * img_ascii_lcd_display() - set the message to be displayed
- * @ctx: pointer to the private data structure
- * @msg: the message to display
- * @count: length of msg, or -1
- *
- * Display a new message @msg on the LCD. @msg can be longer than the number of
- * characters the LCD can display, in which case it will begin scrolling across
- * the LCD display.
- *
- * Return: 0 on success, -ENOMEM on memory allocation failure
- */
-static int img_ascii_lcd_display(struct img_ascii_lcd_ctx *ctx,
-			     const char *msg, ssize_t count)
-{
-	char *new_msg;
-
-	/* stop the scroll timer */
-	del_timer_sync(&ctx->timer);
-
-	if (count == -1)
-		count = strlen(msg);
-
-	/* if the string ends with a newline, trim it */
-	if (msg[count - 1] == '\n')
-		count--;
-
-	new_msg = devm_kmalloc(&ctx->pdev->dev, count + 1, GFP_KERNEL);
-	if (!new_msg)
-		return -ENOMEM;
-
-	memcpy(new_msg, msg, count);
-	new_msg[count] = 0;
-
-	if (ctx->message)
-		devm_kfree(&ctx->pdev->dev, ctx->message);
-
-	ctx->message = new_msg;
-	ctx->message_len = count;
-	ctx->scroll_pos = 0;
-
-	/* update the LCD */
-	img_ascii_lcd_scroll(&ctx->timer);
-
-	return 0;
-}
-
-/**
- * message_show() - read message via sysfs
- * @dev: the LCD device
- * @attr: the LCD message attribute
- * @buf: the buffer to read the message into
- *
- * Read the current message being displayed or scrolled across the LCD display
- * into @buf, for reads from sysfs.
- *
- * Return: the number of characters written to @buf
- */
-static ssize_t message_show(struct device *dev, struct device_attribute *attr,
-			    char *buf)
-{
-	struct img_ascii_lcd_ctx *ctx = dev_get_drvdata(dev);
-
-	return sprintf(buf, "%s\n", ctx->message);
-}
-
-/**
- * message_store() - write a new message via sysfs
- * @dev: the LCD device
- * @attr: the LCD message attribute
- * @buf: the buffer containing the new message
- * @count: the size of the message in @buf
- *
- * Write a new message to display or scroll across the LCD display from sysfs.
- *
- * Return: the size of the message on success, else -ERRNO
- */
-static ssize_t message_store(struct device *dev, struct device_attribute *attr,
-			     const char *buf, size_t count)
-{
-	struct img_ascii_lcd_ctx *ctx = dev_get_drvdata(dev);
-	int err;
-
-	err = img_ascii_lcd_display(ctx, buf, count);
-	return err ?: count;
-}
-
-static DEVICE_ATTR_RW(message);
-
-/**
  * img_ascii_lcd_probe() - probe an LCD display device
  * @pdev: the LCD platform device
  *
@@ -353,28 +227,21 @@ static DEVICE_ATTR_RW(message);
  */
 static int img_ascii_lcd_probe(struct platform_device *pdev)
 {
-	const struct of_device_id *match;
-	const struct img_ascii_lcd_config *cfg;
+	struct device *dev = &pdev->dev;
+	const struct img_ascii_lcd_config *cfg = device_get_match_data(dev);
 	struct img_ascii_lcd_ctx *ctx;
 	int err;
 
-	match = of_match_device(img_ascii_lcd_matches, &pdev->dev);
-	if (!match)
-		return -ENODEV;
-
-	cfg = match->data;
-	ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx) + cfg->num_chars,
-			   GFP_KERNEL);
+	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
 	if (!ctx)
 		return -ENOMEM;
 
 	if (cfg->external_regmap) {
-		ctx->regmap = syscon_node_to_regmap(pdev->dev.parent->of_node);
+		ctx->regmap = syscon_node_to_regmap(dev->parent->of_node);
 		if (IS_ERR(ctx->regmap))
 			return PTR_ERR(ctx->regmap);
 
-		if (of_property_read_u32(pdev->dev.of_node, "offset",
-					 &ctx->offset))
+		if (of_property_read_u32(dev->of_node, "offset", &ctx->offset))
 			return -EINVAL;
 	} else {
 		ctx->base = devm_platform_ioremap_resource(pdev, 0);
@@ -382,29 +249,22 @@ static int img_ascii_lcd_probe(struct platform_device *pdev)
 			return PTR_ERR(ctx->base);
 	}
 
-	ctx->pdev = pdev;
-	ctx->cfg = cfg;
-	ctx->message = NULL;
-	ctx->scroll_pos = 0;
-	ctx->scroll_rate = HZ / 2;
-
-	/* initialise a timer for scrolling the message */
-	timer_setup(&ctx->timer, img_ascii_lcd_scroll, 0);
-
-	platform_set_drvdata(pdev, ctx);
-
-	/* display a default message */
-	err = img_ascii_lcd_display(ctx, "Linux " UTS_RELEASE "       ", -1);
+	err = linedisp_register(&ctx->linedisp, dev, cfg->num_chars, &cfg->ops);
 	if (err)
-		goto out_del_timer;
+		return err;
 
-	err = device_create_file(&pdev->dev, &dev_attr_message);
+	/* for backwards compatibility */
+	err = compat_only_sysfs_link_entry_to_kobj(&dev->kobj,
+						   &ctx->linedisp.dev.kobj,
+						   "message", NULL);
 	if (err)
-		goto out_del_timer;
+		goto err_unregister;
 
+	platform_set_drvdata(pdev, ctx);
 	return 0;
-out_del_timer:
-	del_timer_sync(&ctx->timer);
+
+err_unregister:
+	linedisp_unregister(&ctx->linedisp);
 	return err;
 }
 
@@ -414,16 +274,13 @@ out_del_timer:
  *
  * Remove an LCD display device, freeing private resources & ensuring that the
  * driver stops using the LCD display registers.
- *
- * Return: 0
  */
-static int img_ascii_lcd_remove(struct platform_device *pdev)
+static void img_ascii_lcd_remove(struct platform_device *pdev)
 {
 	struct img_ascii_lcd_ctx *ctx = platform_get_drvdata(pdev);
 
-	device_remove_file(&pdev->dev, &dev_attr_message);
-	del_timer_sync(&ctx->timer);
-	return 0;
+	sysfs_remove_link(&pdev->dev.kobj, "message");
+	linedisp_unregister(&ctx->linedisp);
 }
 
 static struct platform_driver img_ascii_lcd_driver = {
@@ -432,10 +289,11 @@ static struct platform_driver img_ascii_lcd_driver = {
 		.of_match_table	= img_ascii_lcd_matches,
 	},
 	.probe	= img_ascii_lcd_probe,
-	.remove	= img_ascii_lcd_remove,
+	.remove = img_ascii_lcd_remove,
 };
 module_platform_driver(img_ascii_lcd_driver);
 
 MODULE_DESCRIPTION("Imagination Technologies ASCII LCD Display");
 MODULE_AUTHOR("Paul Burton <paul.burton@mips.com>");
 MODULE_LICENSE("GPL");
+MODULE_IMPORT_NS("LINEDISP");
diff --git a/drivers/auxdisplay/ks0108.c b/drivers/auxdisplay/ks0108.c
index abfe3fa9e6f4..51587f0fdaae 100644
--- a/drivers/auxdisplay/ks0108.c
+++ b/drivers/auxdisplay/ks0108.c
@@ -5,7 +5,7 @@
  * Description: ks0108 LCD Controller driver
  *     Depends: parport
  *
- *      Author: Copyright (C) Miguel Ojeda Sandonis
+ *      Author: Copyright (C) Miguel Ojeda <ojeda@kernel.org>
  *        Date: 2006-10-31
  */
 
@@ -15,10 +15,7 @@
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/delay.h>
-#include <linux/fs.h>
-#include <linux/io.h>
 #include <linux/parport.h>
-#include <linux/uaccess.h>
 #include <linux/ks0108.h>
 
 #define KS0108_NAME "ks0108"
@@ -28,11 +25,11 @@
  */
 
 static unsigned int ks0108_port = CONFIG_KS0108_PORT;
-module_param(ks0108_port, uint, S_IRUGO);
+module_param(ks0108_port, uint, 0444);
 MODULE_PARM_DESC(ks0108_port, "Parallel port where the LCD is connected");
 
 static unsigned int ks0108_delay = CONFIG_KS0108_DELAY;
-module_param(ks0108_delay, uint, S_IRUGO);
+module_param(ks0108_delay, uint, 0444);
 MODULE_PARM_DESC(ks0108_delay, "Delay between each control writing (microseconds)");
 
 /*
@@ -165,23 +162,10 @@ static struct parport_driver ks0108_parport_driver = {
 	.name = "ks0108",
 	.match_port = ks0108_parport_attach,
 	.detach = ks0108_parport_detach,
-	.devmodel = true,
 };
-
-static int __init ks0108_init(void)
-{
-	return parport_register_driver(&ks0108_parport_driver);
-}
-
-static void __exit ks0108_exit(void)
-{
-	parport_unregister_driver(&ks0108_parport_driver);
-}
-
-module_init(ks0108_init);
-module_exit(ks0108_exit);
+module_parport_driver(ks0108_parport_driver);
 
 MODULE_LICENSE("GPL v2");
-MODULE_AUTHOR("Miguel Ojeda Sandonis <miguel.ojeda.sandonis@gmail.com>");
+MODULE_AUTHOR("Miguel Ojeda <ojeda@kernel.org>");
 MODULE_DESCRIPTION("ks0108 LCD Controller driver");
 
diff --git a/drivers/auxdisplay/lcd2s.c b/drivers/auxdisplay/lcd2s.c
new file mode 100644
index 000000000000..045dbef49dee
--- /dev/null
+++ b/drivers/auxdisplay/lcd2s.c
@@ -0,0 +1,372 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ *  Console driver for LCD2S 4x20 character displays connected through i2c.
+ *  The display also has a SPI interface, but the driver does not support
+ *  this yet.
+ *
+ *  This is a driver allowing you to use a LCD2S 4x20 from Modtronix
+ *  engineering as auxdisplay character device.
+ *
+ *  (C) 2019 by Lemonage Software GmbH
+ *  Author: Lars Pöschel <poeschel@lemonage.de>
+ *  All rights reserved.
+ */
+#include <linux/kernel.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/property.h>
+#include <linux/slab.h>
+#include <linux/i2c.h>
+#include <linux/delay.h>
+
+#include "charlcd.h"
+
+#define LCD2S_CMD_CUR_MOVES_FWD		0x09
+#define LCD2S_CMD_CUR_BLINK_OFF		0x10
+#define LCD2S_CMD_CUR_UL_OFF		0x11
+#define LCD2S_CMD_DISPLAY_OFF		0x12
+#define LCD2S_CMD_CUR_BLINK_ON		0x18
+#define LCD2S_CMD_CUR_UL_ON		0x19
+#define LCD2S_CMD_DISPLAY_ON		0x1a
+#define LCD2S_CMD_BACKLIGHT_OFF		0x20
+#define LCD2S_CMD_BACKLIGHT_ON		0x28
+#define LCD2S_CMD_WRITE			0x80
+#define LCD2S_CMD_MOV_CUR_RIGHT		0x83
+#define LCD2S_CMD_MOV_CUR_LEFT		0x84
+#define LCD2S_CMD_SHIFT_RIGHT		0x85
+#define LCD2S_CMD_SHIFT_LEFT		0x86
+#define LCD2S_CMD_SHIFT_UP		0x87
+#define LCD2S_CMD_SHIFT_DOWN		0x88
+#define LCD2S_CMD_CUR_ADDR		0x89
+#define LCD2S_CMD_CUR_POS		0x8a
+#define LCD2S_CMD_CUR_RESET		0x8b
+#define LCD2S_CMD_CLEAR			0x8c
+#define LCD2S_CMD_DEF_CUSTOM_CHAR	0x92
+#define LCD2S_CMD_READ_STATUS		0xd0
+
+#define LCD2S_CHARACTER_SIZE		8
+
+#define LCD2S_STATUS_BUF_MASK		0x7f
+
+struct lcd2s_data {
+	struct i2c_client *i2c;
+	struct charlcd *charlcd;
+};
+
+static s32 lcd2s_wait_buf_free(const struct i2c_client *client, int count)
+{
+	s32 status;
+
+	status = i2c_smbus_read_byte_data(client, LCD2S_CMD_READ_STATUS);
+	if (status < 0)
+		return status;
+
+	while ((status & LCD2S_STATUS_BUF_MASK) < count) {
+		mdelay(1);
+		status = i2c_smbus_read_byte_data(client,
+						  LCD2S_CMD_READ_STATUS);
+		if (status < 0)
+			return status;
+	}
+	return 0;
+}
+
+static int lcd2s_i2c_master_send(const struct i2c_client *client,
+				 const char *buf, int count)
+{
+	s32 status;
+
+	status = lcd2s_wait_buf_free(client, count);
+	if (status < 0)
+		return status;
+
+	return i2c_master_send(client, buf, count);
+}
+
+static int lcd2s_i2c_smbus_write_byte(const struct i2c_client *client, u8 value)
+{
+	s32 status;
+
+	status = lcd2s_wait_buf_free(client, 1);
+	if (status < 0)
+		return status;
+
+	return i2c_smbus_write_byte(client, value);
+}
+
+static int lcd2s_print(struct charlcd *lcd, int c)
+{
+	struct lcd2s_data *lcd2s = lcd->drvdata;
+	u8 buf[2] = { LCD2S_CMD_WRITE, c };
+
+	lcd2s_i2c_master_send(lcd2s->i2c, buf, sizeof(buf));
+	return 0;
+}
+
+static int lcd2s_gotoxy(struct charlcd *lcd, unsigned int x, unsigned int y)
+{
+	struct lcd2s_data *lcd2s = lcd->drvdata;
+	u8 buf[3] = { LCD2S_CMD_CUR_POS, y + 1, x + 1 };
+
+	lcd2s_i2c_master_send(lcd2s->i2c, buf, sizeof(buf));
+
+	return 0;
+}
+
+static int lcd2s_home(struct charlcd *lcd)
+{
+	struct lcd2s_data *lcd2s = lcd->drvdata;
+
+	lcd2s_i2c_smbus_write_byte(lcd2s->i2c, LCD2S_CMD_CUR_RESET);
+	return 0;
+}
+
+static int lcd2s_init_display(struct charlcd *lcd)
+{
+	struct lcd2s_data *lcd2s = lcd->drvdata;
+
+	/* turn everything off, but display on */
+	lcd2s_i2c_smbus_write_byte(lcd2s->i2c, LCD2S_CMD_DISPLAY_ON);
+	lcd2s_i2c_smbus_write_byte(lcd2s->i2c, LCD2S_CMD_BACKLIGHT_OFF);
+	lcd2s_i2c_smbus_write_byte(lcd2s->i2c, LCD2S_CMD_CUR_MOVES_FWD);
+	lcd2s_i2c_smbus_write_byte(lcd2s->i2c, LCD2S_CMD_CUR_BLINK_OFF);
+	lcd2s_i2c_smbus_write_byte(lcd2s->i2c, LCD2S_CMD_CUR_UL_OFF);
+	lcd2s_i2c_smbus_write_byte(lcd2s->i2c, LCD2S_CMD_CLEAR);
+
+	return 0;
+}
+
+static int lcd2s_shift_cursor(struct charlcd *lcd, enum charlcd_shift_dir dir)
+{
+	struct lcd2s_data *lcd2s = lcd->drvdata;
+
+	if (dir == CHARLCD_SHIFT_LEFT)
+		lcd2s_i2c_smbus_write_byte(lcd2s->i2c, LCD2S_CMD_MOV_CUR_LEFT);
+	else
+		lcd2s_i2c_smbus_write_byte(lcd2s->i2c, LCD2S_CMD_MOV_CUR_RIGHT);
+
+	return 0;
+}
+
+static int lcd2s_shift_display(struct charlcd *lcd, enum charlcd_shift_dir dir)
+{
+	struct lcd2s_data *lcd2s = lcd->drvdata;
+
+	if (dir == CHARLCD_SHIFT_LEFT)
+		lcd2s_i2c_smbus_write_byte(lcd2s->i2c, LCD2S_CMD_SHIFT_LEFT);
+	else
+		lcd2s_i2c_smbus_write_byte(lcd2s->i2c, LCD2S_CMD_SHIFT_RIGHT);
+
+	return 0;
+}
+
+static void lcd2s_backlight(struct charlcd *lcd, enum charlcd_onoff on)
+{
+	struct lcd2s_data *lcd2s = lcd->drvdata;
+
+	if (on)
+		lcd2s_i2c_smbus_write_byte(lcd2s->i2c, LCD2S_CMD_BACKLIGHT_ON);
+	else
+		lcd2s_i2c_smbus_write_byte(lcd2s->i2c, LCD2S_CMD_BACKLIGHT_OFF);
+}
+
+static int lcd2s_display(struct charlcd *lcd, enum charlcd_onoff on)
+{
+	struct lcd2s_data *lcd2s = lcd->drvdata;
+
+	if (on)
+		lcd2s_i2c_smbus_write_byte(lcd2s->i2c, LCD2S_CMD_DISPLAY_ON);
+	else
+		lcd2s_i2c_smbus_write_byte(lcd2s->i2c, LCD2S_CMD_DISPLAY_OFF);
+
+	return 0;
+}
+
+static int lcd2s_cursor(struct charlcd *lcd, enum charlcd_onoff on)
+{
+	struct lcd2s_data *lcd2s = lcd->drvdata;
+
+	if (on)
+		lcd2s_i2c_smbus_write_byte(lcd2s->i2c, LCD2S_CMD_CUR_UL_ON);
+	else
+		lcd2s_i2c_smbus_write_byte(lcd2s->i2c, LCD2S_CMD_CUR_UL_OFF);
+
+	return 0;
+}
+
+static int lcd2s_blink(struct charlcd *lcd, enum charlcd_onoff on)
+{
+	struct lcd2s_data *lcd2s = lcd->drvdata;
+
+	if (on)
+		lcd2s_i2c_smbus_write_byte(lcd2s->i2c, LCD2S_CMD_CUR_BLINK_ON);
+	else
+		lcd2s_i2c_smbus_write_byte(lcd2s->i2c, LCD2S_CMD_CUR_BLINK_OFF);
+
+	return 0;
+}
+
+static int lcd2s_fontsize(struct charlcd *lcd, enum charlcd_fontsize size)
+{
+	return 0;
+}
+
+static int lcd2s_lines(struct charlcd *lcd, enum charlcd_lines lines)
+{
+	return 0;
+}
+
+/*
+ * Generator: LGcxxxxx...xx; must have <c> between '0' and '7',
+ * representing the numerical ASCII code of the redefined character,
+ * and <xx...xx> a sequence of 16 hex digits representing 8 bytes
+ * for each character. Most LCDs will only use 5 lower bits of
+ * the 7 first bytes.
+ */
+static int lcd2s_redefine_char(struct charlcd *lcd, char *esc)
+{
+	struct lcd2s_data *lcd2s = lcd->drvdata;
+	u8 buf[LCD2S_CHARACTER_SIZE + 2] = { LCD2S_CMD_DEF_CUSTOM_CHAR };
+	u8 value;
+	int shift, i;
+
+	if (!strchr(esc, ';'))
+		return 0;
+
+	esc++;
+
+	buf[1] = *(esc++) - '0';
+	if (buf[1] > 7)
+		return 1;
+
+	i = 2;
+	shift = 0;
+	value = 0;
+	while (*esc && i < LCD2S_CHARACTER_SIZE + 2) {
+		int half;
+
+		shift ^= 4;
+		half = hex_to_bin(*esc++);
+		if (half < 0)
+			continue;
+
+		value |= half << shift;
+		if (shift == 0) {
+			buf[i++] = value;
+			value = 0;
+		}
+	}
+
+	lcd2s_i2c_master_send(lcd2s->i2c, buf, sizeof(buf));
+	return 1;
+}
+
+static int lcd2s_clear_display(struct charlcd *lcd)
+{
+	struct lcd2s_data *lcd2s = lcd->drvdata;
+
+	/* This implicitly sets cursor to first row and column */
+	lcd2s_i2c_smbus_write_byte(lcd2s->i2c, LCD2S_CMD_CLEAR);
+	return 0;
+}
+
+static const struct charlcd_ops lcd2s_ops = {
+	.print		= lcd2s_print,
+	.backlight	= lcd2s_backlight,
+	.gotoxy		= lcd2s_gotoxy,
+	.home		= lcd2s_home,
+	.clear_display	= lcd2s_clear_display,
+	.init_display	= lcd2s_init_display,
+	.shift_cursor	= lcd2s_shift_cursor,
+	.shift_display	= lcd2s_shift_display,
+	.display	= lcd2s_display,
+	.cursor		= lcd2s_cursor,
+	.blink		= lcd2s_blink,
+	.fontsize	= lcd2s_fontsize,
+	.lines		= lcd2s_lines,
+	.redefine_char	= lcd2s_redefine_char,
+};
+
+static int lcd2s_i2c_probe(struct i2c_client *i2c)
+{
+	struct charlcd *lcd;
+	struct lcd2s_data *lcd2s;
+	int err;
+
+	if (!i2c_check_functionality(i2c->adapter,
+			I2C_FUNC_SMBUS_WRITE_BYTE_DATA |
+			I2C_FUNC_SMBUS_WRITE_BLOCK_DATA))
+		return -EIO;
+
+	/* Test, if the display is responding */
+	err = lcd2s_i2c_smbus_write_byte(i2c, LCD2S_CMD_DISPLAY_OFF);
+	if (err < 0)
+		return err;
+
+	lcd = charlcd_alloc(sizeof(*lcd2s));
+	if (!lcd)
+		return -ENOMEM;
+
+	lcd->ops = &lcd2s_ops;
+
+	lcd2s = lcd->drvdata;
+	lcd2s->i2c = i2c;
+	lcd2s->charlcd = lcd;
+
+	/* Required properties */
+	err = device_property_read_u32(&i2c->dev, "display-height-chars",
+			&lcd->height);
+	if (err)
+		goto fail1;
+
+	err = device_property_read_u32(&i2c->dev, "display-width-chars",
+			&lcd->width);
+	if (err)
+		goto fail1;
+
+	err = charlcd_register(lcd2s->charlcd);
+	if (err)
+		goto fail1;
+
+	i2c_set_clientdata(i2c, lcd2s);
+	return 0;
+
+fail1:
+	charlcd_free(lcd2s->charlcd);
+	return err;
+}
+
+static void lcd2s_i2c_remove(struct i2c_client *i2c)
+{
+	struct lcd2s_data *lcd2s = i2c_get_clientdata(i2c);
+
+	charlcd_unregister(lcd2s->charlcd);
+	charlcd_free(lcd2s->charlcd);
+}
+
+static const struct i2c_device_id lcd2s_i2c_id[] = {
+	{ "lcd2s" },
+	{ }
+};
+MODULE_DEVICE_TABLE(i2c, lcd2s_i2c_id);
+
+static const struct of_device_id lcd2s_of_table[] = {
+	{ .compatible = "modtronix,lcd2s" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, lcd2s_of_table);
+
+static struct i2c_driver lcd2s_i2c_driver = {
+	.driver = {
+		.name = "lcd2s",
+		.of_match_table = lcd2s_of_table,
+	},
+	.probe = lcd2s_i2c_probe,
+	.remove = lcd2s_i2c_remove,
+	.id_table = lcd2s_i2c_id,
+};
+module_i2c_driver(lcd2s_i2c_driver);
+
+MODULE_DESCRIPTION("LCD2S character display driver");
+MODULE_AUTHOR("Lars Poeschel");
+MODULE_LICENSE("GPL");
diff --git a/drivers/auxdisplay/line-display.c b/drivers/auxdisplay/line-display.c
new file mode 100644
index 000000000000..4e22373fcc1a
--- /dev/null
+++ b/drivers/auxdisplay/line-display.c
@@ -0,0 +1,596 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Character line display core support
+ *
+ * Copyright (C) 2016 Imagination Technologies
+ * Author: Paul Burton <paul.burton@mips.com>
+ *
+ * Copyright (C) 2021 Glider bv
+ * Copyright (C) 2025 Jean-François Lessard
+ */
+
+#ifndef CONFIG_PANEL_BOOT_MESSAGE
+#include <generated/utsrelease.h>
+#endif
+
+#include <linux/cleanup.h>
+#include <linux/device.h>
+#include <linux/export.h>
+#include <linux/idr.h>
+#include <linux/jiffies.h>
+#include <linux/kstrtox.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/string.h>
+#include <linux/sysfs.h>
+#include <linux/timer.h>
+
+#include <linux/map_to_7segment.h>
+#include <linux/map_to_14segment.h>
+
+#include "line-display.h"
+
+#define DEFAULT_SCROLL_RATE	(HZ / 2)
+
+/**
+ * struct linedisp_attachment - Holds the device to linedisp mapping
+ * @list: List entry for the linedisp_attachments list
+ * @device: Pointer to the device where linedisp attributes are added
+ * @linedisp: Pointer to the linedisp mapped to the device
+ * @direct: true for directly attached device using linedisp_attach(),
+ *	    false for child registered device using linedisp_register()
+ */
+struct linedisp_attachment {
+	struct list_head list;
+	struct device *device;
+	struct linedisp *linedisp;
+	bool direct;
+};
+
+static LIST_HEAD(linedisp_attachments);
+static DEFINE_SPINLOCK(linedisp_attachments_lock);
+
+static int create_attachment(struct device *dev, struct linedisp *linedisp, bool direct)
+{
+	struct linedisp_attachment *attachment;
+
+	attachment = kzalloc(sizeof(*attachment), GFP_KERNEL);
+	if (!attachment)
+		return -ENOMEM;
+
+	attachment->device = dev;
+	attachment->linedisp = linedisp;
+	attachment->direct = direct;
+
+	guard(spinlock)(&linedisp_attachments_lock);
+	list_add(&attachment->list, &linedisp_attachments);
+
+	return 0;
+}
+
+static struct linedisp *delete_attachment(struct device *dev, bool direct)
+{
+	struct linedisp_attachment *attachment;
+	struct linedisp *linedisp;
+
+	guard(spinlock)(&linedisp_attachments_lock);
+
+	list_for_each_entry(attachment, &linedisp_attachments, list) {
+		if (attachment->device == dev &&
+		    attachment->direct == direct)
+			break;
+	}
+
+	if (list_entry_is_head(attachment, &linedisp_attachments, list))
+		return NULL;
+
+	linedisp = attachment->linedisp;
+	list_del(&attachment->list);
+	kfree(attachment);
+
+	return linedisp;
+}
+
+static struct linedisp *to_linedisp(struct device *dev)
+{
+	struct linedisp_attachment *attachment;
+
+	guard(spinlock)(&linedisp_attachments_lock);
+
+	list_for_each_entry(attachment, &linedisp_attachments, list) {
+		if (attachment->device == dev)
+			break;
+	}
+
+	if (list_entry_is_head(attachment, &linedisp_attachments, list))
+		return NULL;
+
+	return attachment->linedisp;
+}
+
+static inline bool should_scroll(struct linedisp *linedisp)
+{
+	return linedisp->message_len > linedisp->num_chars && linedisp->scroll_rate;
+}
+
+/**
+ * linedisp_scroll() - scroll the display by a character
+ * @t: really a pointer to the private data structure
+ *
+ * Scroll the current message along the display by one character, rearming the
+ * timer if required.
+ */
+static void linedisp_scroll(struct timer_list *t)
+{
+	struct linedisp *linedisp = timer_container_of(linedisp, t, timer);
+	unsigned int i, ch = linedisp->scroll_pos;
+	unsigned int num_chars = linedisp->num_chars;
+
+	/* update the current message string */
+	for (i = 0; i < num_chars;) {
+		/* copy as many characters from the string as possible */
+		for (; i < num_chars && ch < linedisp->message_len; i++, ch++)
+			linedisp->buf[i] = linedisp->message[ch];
+
+		/* wrap around to the start of the string */
+		ch = 0;
+	}
+
+	/* update the display */
+	linedisp->ops->update(linedisp);
+
+	/* move on to the next character */
+	linedisp->scroll_pos++;
+	linedisp->scroll_pos %= linedisp->message_len;
+
+	/* rearm the timer */
+	mod_timer(&linedisp->timer, jiffies + linedisp->scroll_rate);
+}
+
+/**
+ * linedisp_display() - set the message to be displayed
+ * @linedisp: pointer to the private data structure
+ * @msg: the message to display
+ * @count: length of msg, or -1
+ *
+ * Display a new message @msg on the display. @msg can be longer than the
+ * number of characters the display can display, in which case it will begin
+ * scrolling across the display.
+ *
+ * Return: 0 on success, -ENOMEM on memory allocation failure
+ */
+static int linedisp_display(struct linedisp *linedisp, const char *msg,
+			    ssize_t count)
+{
+	char *new_msg;
+
+	/* stop the scroll timer */
+	timer_delete_sync(&linedisp->timer);
+
+	if (count == -1)
+		count = strlen(msg);
+
+	/* if the string ends with a newline, trim it */
+	if (msg[count - 1] == '\n')
+		count--;
+
+	if (!count) {
+		/* Clear the display */
+		kfree(linedisp->message);
+		linedisp->message = NULL;
+		linedisp->message_len = 0;
+		memset(linedisp->buf, ' ', linedisp->num_chars);
+		linedisp->ops->update(linedisp);
+		return 0;
+	}
+
+	new_msg = kmemdup_nul(msg, count, GFP_KERNEL);
+	if (!new_msg)
+		return -ENOMEM;
+
+	kfree(linedisp->message);
+
+	linedisp->message = new_msg;
+	linedisp->message_len = count;
+	linedisp->scroll_pos = 0;
+
+	if (should_scroll(linedisp)) {
+		/* display scrolling message */
+		linedisp_scroll(&linedisp->timer);
+	} else {
+		/* display static message */
+		memset(linedisp->buf, ' ', linedisp->num_chars);
+		memcpy(linedisp->buf, linedisp->message,
+		       umin(linedisp->num_chars, linedisp->message_len));
+		linedisp->ops->update(linedisp);
+	}
+
+	return 0;
+}
+
+/**
+ * message_show() - read message via sysfs
+ * @dev: the display device
+ * @attr: the display message attribute
+ * @buf: the buffer to read the message into
+ *
+ * Read the current message being displayed or scrolled across the display into
+ * @buf, for reads from sysfs.
+ *
+ * Return: the number of characters written to @buf
+ */
+static ssize_t message_show(struct device *dev, struct device_attribute *attr,
+			    char *buf)
+{
+	struct linedisp *linedisp = to_linedisp(dev);
+
+	return sysfs_emit(buf, "%s\n", linedisp->message);
+}
+
+/**
+ * message_store() - write a new message via sysfs
+ * @dev: the display device
+ * @attr: the display message attribute
+ * @buf: the buffer containing the new message
+ * @count: the size of the message in @buf
+ *
+ * Write a new message to display or scroll across the display from sysfs.
+ *
+ * Return: the size of the message on success, else -ERRNO
+ */
+static ssize_t message_store(struct device *dev, struct device_attribute *attr,
+			     const char *buf, size_t count)
+{
+	struct linedisp *linedisp = to_linedisp(dev);
+	int err;
+
+	err = linedisp_display(linedisp, buf, count);
+	return err ?: count;
+}
+
+static DEVICE_ATTR_RW(message);
+
+static ssize_t num_chars_show(struct device *dev, struct device_attribute *attr,
+			      char *buf)
+{
+	struct linedisp *linedisp = to_linedisp(dev);
+
+	return sysfs_emit(buf, "%u\n", linedisp->num_chars);
+}
+
+static DEVICE_ATTR_RO(num_chars);
+
+static ssize_t scroll_step_ms_show(struct device *dev,
+				   struct device_attribute *attr, char *buf)
+{
+	struct linedisp *linedisp = to_linedisp(dev);
+
+	return sysfs_emit(buf, "%u\n", jiffies_to_msecs(linedisp->scroll_rate));
+}
+
+static ssize_t scroll_step_ms_store(struct device *dev,
+				    struct device_attribute *attr,
+				    const char *buf, size_t count)
+{
+	struct linedisp *linedisp = to_linedisp(dev);
+	unsigned int ms;
+	int err;
+
+	err = kstrtouint(buf, 10, &ms);
+	if (err)
+		return err;
+
+	timer_delete_sync(&linedisp->timer);
+
+	linedisp->scroll_rate = msecs_to_jiffies(ms);
+
+	if (should_scroll(linedisp))
+		linedisp_scroll(&linedisp->timer);
+
+	return count;
+}
+
+static DEVICE_ATTR_RW(scroll_step_ms);
+
+static ssize_t map_seg_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+	struct linedisp *linedisp = to_linedisp(dev);
+	struct linedisp_map *map = linedisp->map;
+
+	memcpy(buf, &map->map, map->size);
+	return map->size;
+}
+
+static ssize_t map_seg_store(struct device *dev, struct device_attribute *attr,
+			     const char *buf, size_t count)
+{
+	struct linedisp *linedisp = to_linedisp(dev);
+	struct linedisp_map *map = linedisp->map;
+
+	if (count != map->size)
+		return -EINVAL;
+
+	memcpy(&map->map, buf, count);
+	return count;
+}
+
+static const SEG7_DEFAULT_MAP(initial_map_seg7);
+static DEVICE_ATTR(map_seg7, 0644, map_seg_show, map_seg_store);
+
+static const SEG14_DEFAULT_MAP(initial_map_seg14);
+static DEVICE_ATTR(map_seg14, 0644, map_seg_show, map_seg_store);
+
+static struct attribute *linedisp_attrs[] = {
+	&dev_attr_message.attr,
+	&dev_attr_num_chars.attr,
+	&dev_attr_scroll_step_ms.attr,
+	&dev_attr_map_seg7.attr,
+	&dev_attr_map_seg14.attr,
+	NULL
+};
+
+static umode_t linedisp_attr_is_visible(struct kobject *kobj, struct attribute *attr, int n)
+{
+	struct device *dev = kobj_to_dev(kobj);
+	struct linedisp *linedisp = to_linedisp(dev);
+	struct linedisp_map *map = linedisp->map;
+	umode_t mode = attr->mode;
+
+	if (attr == &dev_attr_map_seg7.attr) {
+		if (!map)
+			return 0;
+		if (map->type != LINEDISP_MAP_SEG7)
+			return 0;
+	}
+
+	if (attr == &dev_attr_map_seg14.attr) {
+		if (!map)
+			return 0;
+		if (map->type != LINEDISP_MAP_SEG14)
+			return 0;
+	}
+
+	return mode;
+};
+
+static const struct attribute_group linedisp_group = {
+	.is_visible	= linedisp_attr_is_visible,
+	.attrs		= linedisp_attrs,
+};
+__ATTRIBUTE_GROUPS(linedisp);
+
+static DEFINE_IDA(linedisp_id);
+
+static void linedisp_release(struct device *dev)
+{
+	struct linedisp *linedisp = to_linedisp(dev);
+
+	kfree(linedisp->map);
+	kfree(linedisp->message);
+	kfree(linedisp->buf);
+	ida_free(&linedisp_id, linedisp->id);
+}
+
+static const struct device_type linedisp_type = {
+	.groups	= linedisp_groups,
+	.release = linedisp_release,
+};
+
+static int linedisp_init_map(struct linedisp *linedisp)
+{
+	struct linedisp_map *map;
+	int err;
+
+	if (!linedisp->ops->get_map_type)
+		return 0;
+
+	err = linedisp->ops->get_map_type(linedisp);
+	if (err < 0)
+		return err;
+
+	map = kmalloc(sizeof(*map), GFP_KERNEL);
+	if (!map)
+		return -ENOMEM;
+
+	map->type = err;
+
+	/* assign initial mapping */
+	switch (map->type) {
+	case LINEDISP_MAP_SEG7:
+		map->map.seg7 = initial_map_seg7;
+		map->size = sizeof(map->map.seg7);
+		break;
+	case LINEDISP_MAP_SEG14:
+		map->map.seg14 = initial_map_seg14;
+		map->size = sizeof(map->map.seg14);
+		break;
+	default:
+		kfree(map);
+		return -EINVAL;
+	}
+
+	linedisp->map = map;
+
+	return 0;
+}
+
+#ifdef CONFIG_PANEL_BOOT_MESSAGE
+#define LINEDISP_INIT_TEXT CONFIG_PANEL_BOOT_MESSAGE
+#else
+#define LINEDISP_INIT_TEXT "Linux " UTS_RELEASE "       "
+#endif
+
+/**
+ * linedisp_attach - attach a character line display
+ * @linedisp: pointer to character line display structure
+ * @dev: pointer of the device to attach to
+ * @num_chars: the number of characters that can be displayed
+ * @ops: character line display operations
+ *
+ * Directly attach the line-display sysfs attributes to the passed device.
+ * The caller is responsible for calling linedisp_detach() to release resources
+ * after use.
+ *
+ * Return: zero on success, else a negative error code.
+ */
+int linedisp_attach(struct linedisp *linedisp, struct device *dev,
+		    unsigned int num_chars, const struct linedisp_ops *ops)
+{
+	int err;
+
+	memset(linedisp, 0, sizeof(*linedisp));
+	linedisp->ops = ops;
+	linedisp->num_chars = num_chars;
+	linedisp->scroll_rate = DEFAULT_SCROLL_RATE;
+
+	linedisp->buf = kzalloc(linedisp->num_chars, GFP_KERNEL);
+	if (!linedisp->buf)
+		return -ENOMEM;
+
+	/* initialise a character mapping, if required */
+	err = linedisp_init_map(linedisp);
+	if (err)
+		goto out_free_buf;
+
+	/* initialise a timer for scrolling the message */
+	timer_setup(&linedisp->timer, linedisp_scroll, 0);
+
+	err = create_attachment(dev, linedisp, true);
+	if (err)
+		goto out_del_timer;
+
+	/* display a default message */
+	err = linedisp_display(linedisp, LINEDISP_INIT_TEXT, -1);
+	if (err)
+		goto out_del_attach;
+
+	/* add attribute groups to target device */
+	err = device_add_groups(dev, linedisp_groups);
+	if (err)
+		goto out_del_attach;
+
+	return 0;
+
+out_del_attach:
+	delete_attachment(dev, true);
+out_del_timer:
+	timer_delete_sync(&linedisp->timer);
+out_free_buf:
+	kfree(linedisp->buf);
+	return err;
+}
+EXPORT_SYMBOL_NS_GPL(linedisp_attach, "LINEDISP");
+
+/**
+ * linedisp_detach - detach a character line display
+ * @dev: pointer of the device to detach from, that was previously
+ *	 attached with linedisp_attach()
+ */
+void linedisp_detach(struct device *dev)
+{
+	struct linedisp *linedisp;
+
+	linedisp = delete_attachment(dev, true);
+	if (!linedisp)
+		return;
+
+	timer_delete_sync(&linedisp->timer);
+
+	device_remove_groups(dev, linedisp_groups);
+
+	kfree(linedisp->map);
+	kfree(linedisp->message);
+	kfree(linedisp->buf);
+}
+EXPORT_SYMBOL_NS_GPL(linedisp_detach, "LINEDISP");
+
+/**
+ * linedisp_register - register a character line display
+ * @linedisp: pointer to character line display structure
+ * @parent: parent device
+ * @num_chars: the number of characters that can be displayed
+ * @ops: character line display operations
+ *
+ * Register the line-display sysfs attributes to a new device named
+ * "linedisp.N" added to the passed parent device.
+ * The caller is responsible for calling linedisp_unregister() to release
+ * resources after use.
+ *
+ * Return: zero on success, else a negative error code.
+ */
+int linedisp_register(struct linedisp *linedisp, struct device *parent,
+		      unsigned int num_chars, const struct linedisp_ops *ops)
+{
+	int err;
+
+	memset(linedisp, 0, sizeof(*linedisp));
+	linedisp->dev.parent = parent;
+	linedisp->dev.type = &linedisp_type;
+	linedisp->ops = ops;
+	linedisp->num_chars = num_chars;
+	linedisp->scroll_rate = DEFAULT_SCROLL_RATE;
+
+	err = ida_alloc(&linedisp_id, GFP_KERNEL);
+	if (err < 0)
+		return err;
+	linedisp->id = err;
+
+	device_initialize(&linedisp->dev);
+	dev_set_name(&linedisp->dev, "linedisp.%u", linedisp->id);
+
+	err = -ENOMEM;
+	linedisp->buf = kzalloc(linedisp->num_chars, GFP_KERNEL);
+	if (!linedisp->buf)
+		goto out_put_device;
+
+	/* initialise a character mapping, if required */
+	err = linedisp_init_map(linedisp);
+	if (err)
+		goto out_put_device;
+
+	/* initialise a timer for scrolling the message */
+	timer_setup(&linedisp->timer, linedisp_scroll, 0);
+
+	err = create_attachment(&linedisp->dev, linedisp, false);
+	if (err)
+		goto out_del_timer;
+
+	/* display a default message */
+	err = linedisp_display(linedisp, LINEDISP_INIT_TEXT, -1);
+	if (err)
+		goto out_del_attach;
+
+	err = device_add(&linedisp->dev);
+	if (err)
+		goto out_del_attach;
+
+	return 0;
+
+out_del_attach:
+	delete_attachment(&linedisp->dev, false);
+out_del_timer:
+	timer_delete_sync(&linedisp->timer);
+out_put_device:
+	put_device(&linedisp->dev);
+	return err;
+}
+EXPORT_SYMBOL_NS_GPL(linedisp_register, "LINEDISP");
+
+/**
+ * linedisp_unregister - unregister a character line display
+ * @linedisp: pointer to character line display structure registered previously
+ *	      with linedisp_register()
+ */
+void linedisp_unregister(struct linedisp *linedisp)
+{
+	device_del(&linedisp->dev);
+	delete_attachment(&linedisp->dev, false);
+	timer_delete_sync(&linedisp->timer);
+	put_device(&linedisp->dev);
+}
+EXPORT_SYMBOL_NS_GPL(linedisp_unregister, "LINEDISP");
+
+MODULE_DESCRIPTION("Character line display core support");
+MODULE_LICENSE("GPL");
diff --git a/drivers/auxdisplay/line-display.h b/drivers/auxdisplay/line-display.h
new file mode 100644
index 000000000000..36853b639711
--- /dev/null
+++ b/drivers/auxdisplay/line-display.h
@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Character line display core support
+ *
+ * Copyright (C) 2016 Imagination Technologies
+ * Author: Paul Burton <paul.burton@mips.com>
+ *
+ * Copyright (C) 2021 Glider bv
+ * Copyright (C) 2025 Jean-François Lessard
+ */
+
+#ifndef _LINEDISP_H
+#define _LINEDISP_H
+
+#include <linux/device.h>
+#include <linux/timer_types.h>
+
+#include <linux/map_to_7segment.h>
+#include <linux/map_to_14segment.h>
+
+struct linedisp;
+
+/**
+ * enum linedisp_map_type - type of the character mapping
+ * @LINEDISP_MAP_SEG7: Map characters to 7 segment display
+ * @LINEDISP_MAP_SEG14: Map characters to 14 segment display
+ */
+enum linedisp_map_type {
+	LINEDISP_MAP_SEG7,
+	LINEDISP_MAP_SEG14,
+};
+
+/**
+ * struct linedisp_map - character mapping
+ * @type: type of the character mapping
+ * @map: conversion character mapping
+ * @size: size of the @map
+ */
+struct linedisp_map {
+	enum linedisp_map_type type;
+	union {
+		struct seg7_conversion_map seg7;
+		struct seg14_conversion_map seg14;
+	} map;
+	unsigned int size;
+};
+
+/**
+ * struct linedisp_ops - character line display operations
+ * @get_map_type: Function called to get the character mapping, if required
+ * @update: Function called to update the display. This must not sleep!
+ */
+struct linedisp_ops {
+	int (*get_map_type)(struct linedisp *linedisp);
+	void (*update)(struct linedisp *linedisp);
+};
+
+/**
+ * struct linedisp - character line display private data structure
+ * @dev: the line display device
+ * @timer: timer used to implement scrolling
+ * @ops: character line display operations
+ * @buf: pointer to the buffer for the string currently displayed
+ * @message: the full message to display or scroll on the display
+ * @num_chars: the number of characters that can be displayed
+ * @message_len: the length of the @message string
+ * @scroll_pos: index of the first character of @message currently displayed
+ * @scroll_rate: scroll interval in jiffies
+ * @id: instance id of this display
+ */
+struct linedisp {
+	struct device dev;
+	struct timer_list timer;
+	const struct linedisp_ops *ops;
+	struct linedisp_map *map;
+	char *buf;
+	char *message;
+	unsigned int num_chars;
+	unsigned int message_len;
+	unsigned int scroll_pos;
+	unsigned int scroll_rate;
+	unsigned int id;
+};
+
+int linedisp_attach(struct linedisp *linedisp, struct device *dev,
+		    unsigned int num_chars, const struct linedisp_ops *ops);
+void linedisp_detach(struct device *dev);
+int linedisp_register(struct linedisp *linedisp, struct device *parent,
+		      unsigned int num_chars, const struct linedisp_ops *ops);
+void linedisp_unregister(struct linedisp *linedisp);
+
+#endif /* LINEDISP_H */
diff --git a/drivers/auxdisplay/max6959.c b/drivers/auxdisplay/max6959.c
new file mode 100644
index 000000000000..962488197b9e
--- /dev/null
+++ b/drivers/auxdisplay/max6959.c
@@ -0,0 +1,194 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MAX6958/6959 7-segment LED display controller
+ * Datasheet:
+ * https://www.analog.com/media/en/technical-documentation/data-sheets/MAX6958-MAX6959.pdf
+ *
+ * Copyright (c) 2024, Intel Corporation.
+ * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+ */
+#include <linux/array_size.h>
+#include <linux/bitrev.h>
+#include <linux/bits.h>
+#include <linux/container_of.h>
+#include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/pm.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+#include <linux/workqueue.h>
+
+#include <linux/map_to_7segment.h>
+
+#include "line-display.h"
+
+/* Registers */
+#define REG_DECODE_MODE			0x01
+#define REG_INTENSITY			0x02
+#define REG_SCAN_LIMIT			0x03
+#define REG_CONFIGURATION		0x04
+#define REG_CONFIGURATION_S_BIT		BIT(0)
+
+#define REG_DIGIT(x)			(0x20 + (x))
+#define REG_DIGIT0			0x20
+#define REG_DIGIT1			0x21
+#define REG_DIGIT2			0x22
+#define REG_DIGIT3			0x23
+
+#define REG_SEGMENTS			0x24
+#define REG_MAX				REG_SEGMENTS
+
+struct max6959_priv {
+	struct linedisp linedisp;
+	struct delayed_work work;
+	struct regmap *regmap;
+};
+
+static void max6959_disp_update(struct work_struct *work)
+{
+	struct max6959_priv *priv = container_of(work, struct max6959_priv, work.work);
+	struct linedisp *linedisp = &priv->linedisp;
+	struct linedisp_map *map = linedisp->map;
+	char *s = linedisp->buf;
+	u8 buf[4];
+
+	/* Map segments according to datasheet */
+	buf[0] = bitrev8(map_to_seg7(&map->map.seg7, *s++)) >> 1;
+	buf[1] = bitrev8(map_to_seg7(&map->map.seg7, *s++)) >> 1;
+	buf[2] = bitrev8(map_to_seg7(&map->map.seg7, *s++)) >> 1;
+	buf[3] = bitrev8(map_to_seg7(&map->map.seg7, *s++)) >> 1;
+
+	regmap_bulk_write(priv->regmap, REG_DIGIT(0), buf, ARRAY_SIZE(buf));
+}
+
+static int max6959_linedisp_get_map_type(struct linedisp *linedisp)
+{
+	struct max6959_priv *priv = container_of(linedisp, struct max6959_priv, linedisp);
+
+	INIT_DELAYED_WORK(&priv->work, max6959_disp_update);
+	return LINEDISP_MAP_SEG7;
+}
+
+static void max6959_linedisp_update(struct linedisp *linedisp)
+{
+	struct max6959_priv *priv = container_of(linedisp, struct max6959_priv, linedisp);
+
+	schedule_delayed_work(&priv->work, 0);
+}
+
+static const struct linedisp_ops max6959_linedisp_ops = {
+	.get_map_type = max6959_linedisp_get_map_type,
+	.update = max6959_linedisp_update,
+};
+
+static int max6959_enable(struct max6959_priv *priv, bool enable)
+{
+	u8 mask = REG_CONFIGURATION_S_BIT;
+	u8 value = enable ? mask : 0;
+
+	return regmap_update_bits(priv->regmap, REG_CONFIGURATION, mask, value);
+}
+
+static void max6959_power_off(void *priv)
+{
+	max6959_enable(priv, false);
+}
+
+static int max6959_power_on(struct max6959_priv *priv)
+{
+	struct device *dev = regmap_get_device(priv->regmap);
+	int ret;
+
+	ret = max6959_enable(priv, true);
+	if (ret)
+		return ret;
+
+	return devm_add_action_or_reset(dev, max6959_power_off, priv);
+}
+
+static const struct regmap_config max6959_regmap_config = {
+	.reg_bits = 8,
+	.val_bits = 8,
+
+	.max_register = REG_MAX,
+	.cache_type = REGCACHE_MAPLE,
+};
+
+static int max6959_i2c_probe(struct i2c_client *client)
+{
+	struct device *dev = &client->dev;
+	struct max6959_priv *priv;
+	int ret;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->regmap = devm_regmap_init_i2c(client, &max6959_regmap_config);
+	if (IS_ERR(priv->regmap))
+		return PTR_ERR(priv->regmap);
+
+	ret = max6959_power_on(priv);
+	if (ret)
+		return ret;
+
+	ret = linedisp_register(&priv->linedisp, dev, 4, &max6959_linedisp_ops);
+	if (ret)
+		return ret;
+
+	i2c_set_clientdata(client, priv);
+
+	return 0;
+}
+
+static void max6959_i2c_remove(struct i2c_client *client)
+{
+	struct max6959_priv *priv = i2c_get_clientdata(client);
+
+	cancel_delayed_work_sync(&priv->work);
+	linedisp_unregister(&priv->linedisp);
+}
+
+static int max6959_suspend(struct device *dev)
+{
+	return max6959_enable(dev_get_drvdata(dev), false);
+}
+
+static int max6959_resume(struct device *dev)
+{
+	return max6959_enable(dev_get_drvdata(dev), true);
+}
+
+static DEFINE_SIMPLE_DEV_PM_OPS(max6959_pm_ops, max6959_suspend, max6959_resume);
+
+static const struct i2c_device_id max6959_i2c_id[] = {
+	{ "max6959" },
+	{ }
+};
+MODULE_DEVICE_TABLE(i2c, max6959_i2c_id);
+
+static const struct of_device_id max6959_of_table[] = {
+	{ .compatible = "maxim,max6959" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, max6959_of_table);
+
+static struct i2c_driver max6959_i2c_driver = {
+	.driver = {
+		.name = "max6959",
+		.pm = pm_sleep_ptr(&max6959_pm_ops),
+		.of_match_table = max6959_of_table,
+	},
+	.probe = max6959_i2c_probe,
+	.remove = max6959_i2c_remove,
+	.id_table = max6959_i2c_id,
+};
+module_i2c_driver(max6959_i2c_driver);
+
+MODULE_DESCRIPTION("MAX6958/6959 7-segment LED controller");
+MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
+MODULE_LICENSE("GPL");
+MODULE_IMPORT_NS("LINEDISP");
diff --git a/drivers/auxdisplay/panel.c b/drivers/auxdisplay/panel.c
index 99980aa3644b..958c0e31e84a 100644
--- a/drivers/auxdisplay/panel.c
+++ b/drivers/auxdisplay/panel.c
@@ -56,6 +56,7 @@
 #include <linux/uaccess.h>
 
 #include "charlcd.h"
+#include "hd44780_common.h"
 
 #define LCD_MAXBYTES		256	/* max burst write */
 
@@ -298,8 +299,6 @@ static unsigned char lcd_bits[LCD_PORTS][LCD_BITS][BIT_STATES];
 #define DEFAULT_LCD_TYPE        LCD_TYPE_OLD
 #define DEFAULT_LCD_HEIGHT      2
 #define DEFAULT_LCD_WIDTH       40
-#define DEFAULT_LCD_BWIDTH      40
-#define DEFAULT_LCD_HWIDTH      64
 #define DEFAULT_LCD_CHARSET     LCD_CHARSET_NORMAL
 #define DEFAULT_LCD_PROTO       LCD_PROTO_PARALLEL
 
@@ -708,7 +707,7 @@ static void lcd_send_serial(int byte)
 }
 
 /* turn the backlight on or off */
-static void lcd_backlight(struct charlcd *charlcd, int on)
+static void lcd_backlight(struct charlcd *charlcd, enum charlcd_onoff on)
 {
 	if (lcd.pins.bl == PIN_NONE)
 		return;
@@ -724,7 +723,7 @@ static void lcd_backlight(struct charlcd *charlcd, int on)
 }
 
 /* send a command to the LCD panel in serial mode */
-static void lcd_write_cmd_s(struct charlcd *charlcd, int cmd)
+static void lcd_write_cmd_s(struct hd44780_common *hdc, int cmd)
 {
 	spin_lock_irq(&pprt_lock);
 	lcd_send_serial(0x1F);	/* R/W=W, RS=0 */
@@ -735,7 +734,7 @@ static void lcd_write_cmd_s(struct charlcd *charlcd, int cmd)
 }
 
 /* send data to the LCD panel in serial mode */
-static void lcd_write_data_s(struct charlcd *charlcd, int data)
+static void lcd_write_data_s(struct hd44780_common *hdc, int data)
 {
 	spin_lock_irq(&pprt_lock);
 	lcd_send_serial(0x5F);	/* R/W=W, RS=1 */
@@ -746,7 +745,7 @@ static void lcd_write_data_s(struct charlcd *charlcd, int data)
 }
 
 /* send a command to the LCD panel in 8 bits parallel mode */
-static void lcd_write_cmd_p8(struct charlcd *charlcd, int cmd)
+static void lcd_write_cmd_p8(struct hd44780_common *hdc, int cmd)
 {
 	spin_lock_irq(&pprt_lock);
 	/* present the data to the data port */
@@ -768,7 +767,7 @@ static void lcd_write_cmd_p8(struct charlcd *charlcd, int cmd)
 }
 
 /* send data to the LCD panel in 8 bits parallel mode */
-static void lcd_write_data_p8(struct charlcd *charlcd, int data)
+static void lcd_write_data_p8(struct hd44780_common *hdc, int data)
 {
 	spin_lock_irq(&pprt_lock);
 	/* present the data to the data port */
@@ -790,7 +789,7 @@ static void lcd_write_data_p8(struct charlcd *charlcd, int data)
 }
 
 /* send a command to the TI LCD panel */
-static void lcd_write_cmd_tilcd(struct charlcd *charlcd, int cmd)
+static void lcd_write_cmd_tilcd(struct hd44780_common *hdc, int cmd)
 {
 	spin_lock_irq(&pprt_lock);
 	/* present the data to the control port */
@@ -800,7 +799,7 @@ static void lcd_write_cmd_tilcd(struct charlcd *charlcd, int cmd)
 }
 
 /* send data to the TI LCD panel */
-static void lcd_write_data_tilcd(struct charlcd *charlcd, int data)
+static void lcd_write_data_tilcd(struct hd44780_common *hdc, int data)
 {
 	spin_lock_irq(&pprt_lock);
 	/* present the data to the data port */
@@ -809,105 +808,44 @@ static void lcd_write_data_tilcd(struct charlcd *charlcd, int data)
 	spin_unlock_irq(&pprt_lock);
 }
 
-/* fills the display with spaces and resets X/Y */
-static void lcd_clear_fast_s(struct charlcd *charlcd)
-{
-	int pos;
-
-	spin_lock_irq(&pprt_lock);
-	for (pos = 0; pos < charlcd->height * charlcd->hwidth; pos++) {
-		lcd_send_serial(0x5F);	/* R/W=W, RS=1 */
-		lcd_send_serial(' ' & 0x0F);
-		lcd_send_serial((' ' >> 4) & 0x0F);
-		/* the shortest data takes at least 40 us */
-		udelay(40);
-	}
-	spin_unlock_irq(&pprt_lock);
-}
-
-/* fills the display with spaces and resets X/Y */
-static void lcd_clear_fast_p8(struct charlcd *charlcd)
-{
-	int pos;
-
-	spin_lock_irq(&pprt_lock);
-	for (pos = 0; pos < charlcd->height * charlcd->hwidth; pos++) {
-		/* present the data to the data port */
-		w_dtr(pprt, ' ');
-
-		/* maintain the data during 20 us before the strobe */
-		udelay(20);
-
-		set_bit(LCD_BIT_E, bits);
-		set_bit(LCD_BIT_RS, bits);
-		clear_bit(LCD_BIT_RW, bits);
-		set_ctrl_bits();
-
-		/* maintain the strobe during 40 us */
-		udelay(40);
-
-		clear_bit(LCD_BIT_E, bits);
-		set_ctrl_bits();
-
-		/* the shortest data takes at least 45 us */
-		udelay(45);
-	}
-	spin_unlock_irq(&pprt_lock);
-}
-
-/* fills the display with spaces and resets X/Y */
-static void lcd_clear_fast_tilcd(struct charlcd *charlcd)
-{
-	int pos;
-
-	spin_lock_irq(&pprt_lock);
-	for (pos = 0; pos < charlcd->height * charlcd->hwidth; pos++) {
-		/* present the data to the data port */
-		w_dtr(pprt, ' ');
-		udelay(60);
-	}
-
-	spin_unlock_irq(&pprt_lock);
-}
-
-static const struct charlcd_ops charlcd_serial_ops = {
-	.write_cmd	= lcd_write_cmd_s,
-	.write_data	= lcd_write_data_s,
-	.clear_fast	= lcd_clear_fast_s,
-	.backlight	= lcd_backlight,
-};
-
-static const struct charlcd_ops charlcd_parallel_ops = {
-	.write_cmd	= lcd_write_cmd_p8,
-	.write_data	= lcd_write_data_p8,
-	.clear_fast	= lcd_clear_fast_p8,
-	.backlight	= lcd_backlight,
-};
-
-static const struct charlcd_ops charlcd_tilcd_ops = {
-	.write_cmd	= lcd_write_cmd_tilcd,
-	.write_data	= lcd_write_data_tilcd,
-	.clear_fast	= lcd_clear_fast_tilcd,
+static const struct charlcd_ops charlcd_ops = {
 	.backlight	= lcd_backlight,
+	.print		= hd44780_common_print,
+	.gotoxy		= hd44780_common_gotoxy,
+	.home		= hd44780_common_home,
+	.clear_display	= hd44780_common_clear_display,
+	.init_display	= hd44780_common_init_display,
+	.shift_cursor	= hd44780_common_shift_cursor,
+	.shift_display	= hd44780_common_shift_display,
+	.display	= hd44780_common_display,
+	.cursor		= hd44780_common_cursor,
+	.blink		= hd44780_common_blink,
+	.fontsize	= hd44780_common_fontsize,
+	.lines		= hd44780_common_lines,
+	.redefine_char	= hd44780_common_redefine_char,
 };
 
 /* initialize the LCD driver */
 static void lcd_init(void)
 {
 	struct charlcd *charlcd;
+	struct hd44780_common *hdc;
 
-	charlcd = charlcd_alloc(0);
+	charlcd = hd44780_common_alloc();
 	if (!charlcd)
 		return;
 
+	hdc = charlcd->drvdata;
+	hdc->hd44780 = &lcd;
+
 	/*
 	 * Init lcd struct with load-time values to preserve exact
 	 * current functionality (at least for now).
 	 */
 	charlcd->height = lcd_height;
 	charlcd->width = lcd_width;
-	charlcd->bwidth = lcd_bwidth;
-	charlcd->hwidth = lcd_hwidth;
+	hdc->bwidth = lcd_bwidth;
+	hdc->hwidth = lcd_hwidth;
 
 	switch (selected_lcd_type) {
 	case LCD_TYPE_OLD:
@@ -918,8 +856,8 @@ static void lcd_init(void)
 		lcd.pins.rs = PIN_AUTOLF;
 
 		charlcd->width = 40;
-		charlcd->bwidth = 40;
-		charlcd->hwidth = 64;
+		hdc->bwidth = 40;
+		hdc->hwidth = 64;
 		charlcd->height = 2;
 		break;
 	case LCD_TYPE_KS0074:
@@ -931,8 +869,8 @@ static void lcd_init(void)
 		lcd.pins.da = PIN_D0;
 
 		charlcd->width = 16;
-		charlcd->bwidth = 40;
-		charlcd->hwidth = 16;
+		hdc->bwidth = 40;
+		hdc->hwidth = 16;
 		charlcd->height = 2;
 		break;
 	case LCD_TYPE_NEXCOM:
@@ -944,8 +882,8 @@ static void lcd_init(void)
 		lcd.pins.rw = PIN_INITP;
 
 		charlcd->width = 16;
-		charlcd->bwidth = 40;
-		charlcd->hwidth = 64;
+		hdc->bwidth = 40;
+		hdc->hwidth = 64;
 		charlcd->height = 2;
 		break;
 	case LCD_TYPE_CUSTOM:
@@ -963,8 +901,8 @@ static void lcd_init(void)
 		lcd.pins.rs = PIN_SELECP;
 
 		charlcd->width = 16;
-		charlcd->bwidth = 40;
-		charlcd->hwidth = 64;
+		hdc->bwidth = 40;
+		hdc->hwidth = 64;
 		charlcd->height = 2;
 		break;
 	}
@@ -975,9 +913,9 @@ static void lcd_init(void)
 	if (lcd_width != NOT_SET)
 		charlcd->width = lcd_width;
 	if (lcd_bwidth != NOT_SET)
-		charlcd->bwidth = lcd_bwidth;
+		hdc->bwidth = lcd_bwidth;
 	if (lcd_hwidth != NOT_SET)
-		charlcd->hwidth = lcd_hwidth;
+		hdc->hwidth = lcd_hwidth;
 	if (lcd_charset != NOT_SET)
 		lcd.charset = lcd_charset;
 	if (lcd_proto != NOT_SET)
@@ -998,15 +936,17 @@ static void lcd_init(void)
 	/* this is used to catch wrong and default values */
 	if (charlcd->width <= 0)
 		charlcd->width = DEFAULT_LCD_WIDTH;
-	if (charlcd->bwidth <= 0)
-		charlcd->bwidth = DEFAULT_LCD_BWIDTH;
-	if (charlcd->hwidth <= 0)
-		charlcd->hwidth = DEFAULT_LCD_HWIDTH;
+	if (hdc->bwidth <= 0)
+		hdc->bwidth = DEFAULT_LCD_BWIDTH;
+	if (hdc->hwidth <= 0)
+		hdc->hwidth = DEFAULT_LCD_HWIDTH;
 	if (charlcd->height <= 0)
 		charlcd->height = DEFAULT_LCD_HEIGHT;
 
 	if (lcd.proto == LCD_PROTO_SERIAL) {	/* SERIAL */
-		charlcd->ops = &charlcd_serial_ops;
+		charlcd->ops = &charlcd_ops;
+		hdc->write_data = lcd_write_data_s;
+		hdc->write_cmd = lcd_write_cmd_s;
 
 		if (lcd.pins.cl == PIN_NOT_SET)
 			lcd.pins.cl = DEFAULT_LCD_PIN_SCL;
@@ -1014,7 +954,9 @@ static void lcd_init(void)
 			lcd.pins.da = DEFAULT_LCD_PIN_SDA;
 
 	} else if (lcd.proto == LCD_PROTO_PARALLEL) {	/* PARALLEL */
-		charlcd->ops = &charlcd_parallel_ops;
+		charlcd->ops = &charlcd_ops;
+		hdc->write_data = lcd_write_data_p8;
+		hdc->write_cmd = lcd_write_cmd_p8;
 
 		if (lcd.pins.e == PIN_NOT_SET)
 			lcd.pins.e = DEFAULT_LCD_PIN_E;
@@ -1023,7 +965,9 @@ static void lcd_init(void)
 		if (lcd.pins.rw == PIN_NOT_SET)
 			lcd.pins.rw = DEFAULT_LCD_PIN_RW;
 	} else {
-		charlcd->ops = &charlcd_tilcd_ops;
+		charlcd->ops = &charlcd_ops;
+		hdc->write_data = lcd_write_data_tilcd;
+		hdc->write_cmd = lcd_write_cmd_tilcd;
 	}
 
 	if (lcd.pins.bl == PIN_NOT_SET)
@@ -1365,7 +1309,7 @@ static void panel_process_inputs(void)
 				break;
 			input->rise_timer = 0;
 			input->state = INPUT_ST_RISING;
-			/* fall through */
+			fallthrough;
 		case INPUT_ST_RISING:
 			if ((phys_curr & input->mask) != input->value) {
 				input->state = INPUT_ST_LOW;
@@ -1378,11 +1322,11 @@ static void panel_process_inputs(void)
 			}
 			input->high_timer = 0;
 			input->state = INPUT_ST_HIGH;
-			/* fall through */
+			fallthrough;
 		case INPUT_ST_HIGH:
 			if (input_state_high(input))
 				break;
-			/* fall through */
+			fallthrough;
 		case INPUT_ST_FALLING:
 			input_state_falling(input);
 		}
@@ -1499,10 +1443,9 @@ static struct logical_input *panel_bind_key(const char *name, const char *press,
 	key->rise_time = 1;
 	key->fall_time = 1;
 
-	strncpy(key->u.kbd.press_str, press, sizeof(key->u.kbd.press_str));
-	strncpy(key->u.kbd.repeat_str, repeat, sizeof(key->u.kbd.repeat_str));
-	strncpy(key->u.kbd.release_str, release,
-		sizeof(key->u.kbd.release_str));
+	strtomem_pad(key->u.kbd.press_str, press, '\0');
+	strtomem_pad(key->u.kbd.repeat_str, repeat, '\0');
+	strtomem_pad(key->u.kbd.release_str, release, '\0');
 	list_add(&key->list, &logical_inputs);
 	return key;
 }
@@ -1570,105 +1513,9 @@ static void keypad_init(void)
 
 static void panel_attach(struct parport *port)
 {
+	int selected_keypad_type = NOT_SET;
 	struct pardev_cb panel_cb;
 
-	if (port->number != parport)
-		return;
-
-	if (pprt) {
-		pr_err("%s: port->number=%d parport=%d, already registered!\n",
-		       __func__, port->number, parport);
-		return;
-	}
-
-	memset(&panel_cb, 0, sizeof(panel_cb));
-	panel_cb.private = &pprt;
-	/* panel_cb.flags = 0 should be PARPORT_DEV_EXCL? */
-
-	pprt = parport_register_dev_model(port, "panel", &panel_cb, 0);
-	if (!pprt) {
-		pr_err("%s: port->number=%d parport=%d, parport_register_device() failed\n",
-		       __func__, port->number, parport);
-		return;
-	}
-
-	if (parport_claim(pprt)) {
-		pr_err("could not claim access to parport%d. Aborting.\n",
-		       parport);
-		goto err_unreg_device;
-	}
-
-	/* must init LCD first, just in case an IRQ from the keypad is
-	 * generated at keypad init
-	 */
-	if (lcd.enabled) {
-		lcd_init();
-		if (!lcd.charlcd || charlcd_register(lcd.charlcd))
-			goto err_unreg_device;
-	}
-
-	if (keypad.enabled) {
-		keypad_init();
-		if (misc_register(&keypad_dev))
-			goto err_lcd_unreg;
-	}
-	return;
-
-err_lcd_unreg:
-	if (scan_timer.function)
-		del_timer_sync(&scan_timer);
-	if (lcd.enabled)
-		charlcd_unregister(lcd.charlcd);
-err_unreg_device:
-	charlcd_free(lcd.charlcd);
-	lcd.charlcd = NULL;
-	parport_unregister_device(pprt);
-	pprt = NULL;
-}
-
-static void panel_detach(struct parport *port)
-{
-	if (port->number != parport)
-		return;
-
-	if (!pprt) {
-		pr_err("%s: port->number=%d parport=%d, nothing to unregister.\n",
-		       __func__, port->number, parport);
-		return;
-	}
-	if (scan_timer.function)
-		del_timer_sync(&scan_timer);
-
-	if (keypad.enabled) {
-		misc_deregister(&keypad_dev);
-		keypad_initialized = 0;
-	}
-
-	if (lcd.enabled) {
-		charlcd_unregister(lcd.charlcd);
-		lcd.initialized = false;
-		charlcd_free(lcd.charlcd);
-		lcd.charlcd = NULL;
-	}
-
-	/* TODO: free all input signals */
-	parport_release(pprt);
-	parport_unregister_device(pprt);
-	pprt = NULL;
-}
-
-static struct parport_driver panel_driver = {
-	.name = "panel",
-	.match_port = panel_attach,
-	.detach = panel_detach,
-	.devmodel = true,
-};
-
-/* init function */
-static int __init panel_init_module(void)
-{
-	int selected_keypad_type = NOT_SET, err;
-
 	/* take care of an eventual profile */
 	switch (profile) {
 	case PANEL_PROFILE_CUSTOM:
@@ -1760,36 +1607,100 @@ static int __init panel_init_module(void)
 	if (!lcd.enabled && !keypad.enabled) {
 		/* no device enabled, let's exit */
 		pr_err("panel driver disabled.\n");
-		return -ENODEV;
+		return;
+	}
+
+	if (port->number != parport)
+		return;
+
+	if (pprt) {
+		pr_err("%s: port->number=%d parport=%d, already registered!\n",
+		       __func__, port->number, parport);
+		return;
 	}
 
-	err = parport_register_driver(&panel_driver);
-	if (err) {
-		pr_err("could not register with parport. Aborting.\n");
-		return err;
+	memset(&panel_cb, 0, sizeof(panel_cb));
+	panel_cb.private = &pprt;
+	/* panel_cb.flags = 0 should be PARPORT_DEV_EXCL? */
+
+	pprt = parport_register_dev_model(port, "panel", &panel_cb, 0);
+	if (!pprt) {
+		pr_err("%s: port->number=%d parport=%d, parport_register_device() failed\n",
+		       __func__, port->number, parport);
+		return;
 	}
 
-	if (pprt)
-		pr_info("panel driver registered on parport%d (io=0x%lx).\n",
-			parport, pprt->port->base);
-	else
-		pr_info("panel driver not yet registered\n");
-	return 0;
+	if (parport_claim(pprt)) {
+		pr_err("could not claim access to parport%d. Aborting.\n",
+		       parport);
+		goto err_unreg_device;
+	}
+
+	/* must init LCD first, just in case an IRQ from the keypad is
+	 * generated at keypad init
+	 */
+	if (lcd.enabled) {
+		lcd_init();
+		if (!lcd.charlcd || charlcd_register(lcd.charlcd))
+			goto err_unreg_device;
+	}
+
+	if (keypad.enabled) {
+		keypad_init();
+		if (misc_register(&keypad_dev))
+			goto err_lcd_unreg;
+	}
+	return;
+
+err_lcd_unreg:
+	if (scan_timer.function)
+		timer_delete_sync(&scan_timer);
+	if (lcd.enabled)
+		charlcd_unregister(lcd.charlcd);
+err_unreg_device:
+	hd44780_common_free(lcd.charlcd);
+	lcd.charlcd = NULL;
+	parport_unregister_device(pprt);
+	pprt = NULL;
 }
 
-static void __exit panel_cleanup_module(void)
+static void panel_detach(struct parport *port)
 {
-	parport_unregister_driver(&panel_driver);
+	if (port->number != parport)
+		return;
+
+	if (!pprt) {
+		pr_err("%s: port->number=%d parport=%d, nothing to unregister.\n",
+		       __func__, port->number, parport);
+		return;
+	}
+	if (scan_timer.function)
+		timer_delete_sync(&scan_timer);
+
+	if (keypad.enabled) {
+		misc_deregister(&keypad_dev);
+		keypad_initialized = 0;
+	}
+
+	if (lcd.enabled) {
+		charlcd_unregister(lcd.charlcd);
+		lcd.initialized = false;
+		hd44780_common_free(lcd.charlcd);
+		lcd.charlcd = NULL;
+	}
+
+	/* TODO: free all input signals */
+	parport_release(pprt);
+	parport_unregister_device(pprt);
+	pprt = NULL;
 }
 
-module_init(panel_init_module);
-module_exit(panel_cleanup_module);
+static struct parport_driver panel_driver = {
+	.name = "panel",
+	.match_port = panel_attach,
+	.detach = panel_detach,
+};
+module_parport_driver(panel_driver);
+
 MODULE_AUTHOR("Willy Tarreau");
 MODULE_LICENSE("GPL");
-
-/*
- * Local variables:
- *  c-indent-level: 4
- *  tab-width: 8
- * End:
- */
diff --git a/drivers/auxdisplay/seg-led-gpio.c b/drivers/auxdisplay/seg-led-gpio.c
new file mode 100644
index 000000000000..dfb62e9ce9b4
--- /dev/null
+++ b/drivers/auxdisplay/seg-led-gpio.c
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Driver for a 7-segment LED display
+ *
+ * The decimal point LED present on some devices is currently not
+ * supported.
+ *
+ * Copyright (C) Allied Telesis Labs
+ */
+
+#include <linux/bitmap.h>
+#include <linux/container_of.h>
+#include <linux/errno.h>
+#include <linux/gpio/consumer.h>
+#include <linux/map_to_7segment.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
+#include <linux/workqueue.h>
+
+#include "line-display.h"
+
+struct seg_led_priv {
+	struct linedisp linedisp;
+	struct delayed_work work;
+	struct gpio_descs *segment_gpios;
+};
+
+static void seg_led_update(struct work_struct *work)
+{
+	struct seg_led_priv *priv = container_of(work, struct seg_led_priv, work.work);
+	struct linedisp *linedisp = &priv->linedisp;
+	struct linedisp_map *map = linedisp->map;
+	DECLARE_BITMAP(values, 8) = { };
+
+	bitmap_set_value8(values, map_to_seg7(&map->map.seg7, linedisp->buf[0]), 0);
+
+	gpiod_multi_set_value_cansleep(priv->segment_gpios, values);
+}
+
+static int seg_led_linedisp_get_map_type(struct linedisp *linedisp)
+{
+	struct seg_led_priv *priv = container_of(linedisp, struct seg_led_priv, linedisp);
+
+	INIT_DELAYED_WORK(&priv->work, seg_led_update);
+	return LINEDISP_MAP_SEG7;
+}
+
+static void seg_led_linedisp_update(struct linedisp *linedisp)
+{
+	struct seg_led_priv *priv = container_of(linedisp, struct seg_led_priv, linedisp);
+
+	schedule_delayed_work(&priv->work, 0);
+}
+
+static const struct linedisp_ops seg_led_linedisp_ops = {
+	.get_map_type = seg_led_linedisp_get_map_type,
+	.update = seg_led_linedisp_update,
+};
+
+static int seg_led_probe(struct platform_device *pdev)
+{
+	struct seg_led_priv *priv;
+	struct device *dev = &pdev->dev;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	platform_set_drvdata(pdev, priv);
+
+	priv->segment_gpios = devm_gpiod_get_array(dev, "segment", GPIOD_OUT_LOW);
+	if (IS_ERR(priv->segment_gpios))
+		return PTR_ERR(priv->segment_gpios);
+
+	if (priv->segment_gpios->ndescs < 7 || priv->segment_gpios->ndescs > 8)
+		return -EINVAL;
+
+	return linedisp_register(&priv->linedisp, dev, 1, &seg_led_linedisp_ops);
+}
+
+static void seg_led_remove(struct platform_device *pdev)
+{
+	struct seg_led_priv *priv = platform_get_drvdata(pdev);
+
+	cancel_delayed_work_sync(&priv->work);
+	linedisp_unregister(&priv->linedisp);
+}
+
+static const struct of_device_id seg_led_of_match[] = {
+	{ .compatible = "gpio-7-segment"},
+	{}
+};
+MODULE_DEVICE_TABLE(of, seg_led_of_match);
+
+static struct platform_driver seg_led_driver = {
+	.probe = seg_led_probe,
+	.remove = seg_led_remove,
+	.driver = {
+		.name = "seg-led-gpio",
+		.of_match_table = seg_led_of_match,
+	},
+};
+module_platform_driver(seg_led_driver);
+
+MODULE_AUTHOR("Chris Packham <chris.packham@alliedtelesis.co.nz>");
+MODULE_DESCRIPTION("7 segment LED driver");
+MODULE_LICENSE("GPL");
+MODULE_IMPORT_NS("LINEDISP");
diff --git a/drivers/base/Kconfig b/drivers/base/Kconfig
index 5f0bc74d2409..1786d87b29e2 100644
--- a/drivers/base/Kconfig
+++ b/drivers/base/Kconfig
@@ -1,6 +1,9 @@
 # SPDX-License-Identifier: GPL-2.0
 menu "Generic Driver Options"
 
+config AUXILIARY_BUS
+	bool
+
 config UEVENT_HELPER
 	bool "Support for uevent helper"
 	help
@@ -59,6 +62,17 @@ config DEVTMPFS_MOUNT
 	  rescue mode with init=/bin/sh, even when the /dev directory
 	  on the rootfs is completely empty.
 
+config DEVTMPFS_SAFE
+	bool "Use nosuid,noexec mount options on devtmpfs"
+	depends on DEVTMPFS
+	help
+	  This instructs the kernel to include the MS_NOEXEC and MS_NOSUID mount
+	  flags when mounting devtmpfs.
+
+	  Notice: If enabled, things like /dev/mem cannot be mmapped
+	  with the PROT_EXEC flag. This can break, for example, non-KMS
+	  video drivers.
+
 config STANDALONE
 	bool "Select only drivers that don't need compile-time external firmware"
 	default y
@@ -149,15 +163,22 @@ config DEBUG_TEST_DRIVER_REMOVE
 	  test this functionality.
 
 config PM_QOS_KUNIT_TEST
-	bool "KUnit Test for PM QoS features"
+	bool "KUnit Test for PM QoS features" if !KUNIT_ALL_TESTS
 	depends on KUNIT=y
+	default KUNIT_ALL_TESTS
+
+config PM_RUNTIME_KUNIT_TEST
+	tristate "KUnit Tests for runtime PM" if !KUNIT_ALL_TESTS
+	depends on KUNIT
+	depends on PM
+	default KUNIT_ALL_TESTS
 
 config HMEM_REPORTING
 	bool
 	default n
 	depends on NUMA
 	help
-	  Enable reporting for heterogenous memory access attributes under
+	  Enable reporting for heterogeneous memory access attributes under
 	  their non-uniform memory nodes.
 
 source "drivers/base/test/Kconfig"
@@ -209,4 +230,23 @@ config GENERIC_ARCH_TOPOLOGY
 	  appropriate scaling, sysfs interface for reading capacity values at
 	  runtime.
 
+config GENERIC_ARCH_NUMA
+	bool
+	select NUMA_MEMBLKS
+	help
+	  Enable support for generic NUMA implementation. Currently, RISC-V
+	  and ARM64 use it.
+
+config FW_DEVLINK_SYNC_STATE_TIMEOUT
+	bool "sync_state() behavior defaults to timeout instead of strict"
+	help
+	  This is build time equivalent of adding kernel command line parameter
+	  "fw_devlink.sync_state=timeout". Give up waiting on consumers and
+	  call sync_state() on any devices that haven't yet received their
+	  sync_state() calls after deferred_probe_timeout has expired or by
+	  late_initcall() if !CONFIG_MODULES. You should almost always want to
+	  select N here unless you have already successfully tested with the
+	  command line option on every system/board your kernel is expected to
+	  work on.
+
 endmenu
diff --git a/drivers/base/Makefile b/drivers/base/Makefile
index 157452080f3d..8074a10183dc 100644
--- a/drivers/base/Makefile
+++ b/drivers/base/Makefile
@@ -6,25 +6,32 @@ obj-y			:= component.o core.o bus.o dd.o syscore.o \
 			   cpu.o firmware.o init.o map.o devres.o \
 			   attribute_container.o transport_class.o \
 			   topology.o container.o property.o cacheinfo.o \
-			   devcon.o swnode.o
+			   swnode.o faux.o
+obj-$(CONFIG_AUXILIARY_BUS) += auxiliary.o
 obj-$(CONFIG_DEVTMPFS)	+= devtmpfs.o
 obj-y			+= power/
 obj-$(CONFIG_ISA_BUS_API)	+= isa.o
 obj-y				+= firmware_loader/
 obj-$(CONFIG_NUMA)	+= node.o
-obj-$(CONFIG_MEMORY_HOTPLUG_SPARSE) += memory.o
+obj-$(CONFIG_MEMORY_HOTPLUG) += memory.o
 ifeq ($(CONFIG_SYSFS),y)
 obj-$(CONFIG_MODULES)	+= module.o
+obj-$(CONFIG_AUXILIARY_BUS) += auxiliary_sysfs.o
 endif
 obj-$(CONFIG_SYS_HYPERVISOR) += hypervisor.o
 obj-$(CONFIG_REGMAP)	+= regmap/
 obj-$(CONFIG_SOC_BUS) += soc.o
 obj-$(CONFIG_PINCTRL) += pinctrl.o
 obj-$(CONFIG_DEV_COREDUMP) += devcoredump.o
-obj-$(CONFIG_GENERIC_MSI_IRQ_DOMAIN) += platform-msi.o
+obj-$(CONFIG_GENERIC_MSI_IRQ) += platform-msi.o
 obj-$(CONFIG_GENERIC_ARCH_TOPOLOGY) += arch_topology.o
+obj-$(CONFIG_GENERIC_ARCH_NUMA) += arch_numa.o
+obj-$(CONFIG_ACPI) += physical_location.o
 
 obj-y			+= test/
 
 ccflags-$(CONFIG_DEBUG_DRIVER) := -DDEBUG
 
+# define_trace.h needs to know how to find our header
+CFLAGS_trace.o		:= -I$(src)
+obj-$(CONFIG_TRACING)	+= trace.o
diff --git a/drivers/base/arch_numa.c b/drivers/base/arch_numa.c
new file mode 100644
index 000000000000..c99f2ab105e5
--- /dev/null
+++ b/drivers/base/arch_numa.c
@@ -0,0 +1,379 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * NUMA support, based on the x86 implementation.
+ *
+ * Copyright (C) 2015 Cavium Inc.
+ * Author: Ganapatrao Kulkarni <gkulkarni@cavium.com>
+ */
+
+#define pr_fmt(fmt) "NUMA: " fmt
+
+#include <linux/acpi.h>
+#include <linux/memblock.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/numa_memblks.h>
+
+#include <asm/sections.h>
+
+static int cpu_to_node_map[NR_CPUS] = { [0 ... NR_CPUS-1] = NUMA_NO_NODE };
+
+bool numa_off;
+
+static __init int numa_parse_early_param(char *opt)
+{
+	if (!opt)
+		return -EINVAL;
+	if (str_has_prefix(opt, "off"))
+		numa_off = true;
+	if (!strncmp(opt, "fake=", 5))
+		return numa_emu_cmdline(opt + 5);
+
+	return 0;
+}
+early_param("numa", numa_parse_early_param);
+
+cpumask_var_t node_to_cpumask_map[MAX_NUMNODES];
+EXPORT_SYMBOL(node_to_cpumask_map);
+
+#ifdef CONFIG_DEBUG_PER_CPU_MAPS
+
+/*
+ * Returns a pointer to the bitmask of CPUs on Node 'node'.
+ */
+const struct cpumask *cpumask_of_node(int node)
+{
+
+	if (node == NUMA_NO_NODE)
+		return cpu_all_mask;
+
+	if (WARN_ON(node < 0 || node >= nr_node_ids))
+		return cpu_none_mask;
+
+	if (WARN_ON(node_to_cpumask_map[node] == NULL))
+		return cpu_online_mask;
+
+	return node_to_cpumask_map[node];
+}
+EXPORT_SYMBOL(cpumask_of_node);
+
+#endif
+
+#ifndef CONFIG_NUMA_EMU
+static void numa_update_cpu(unsigned int cpu, bool remove)
+{
+	int nid = cpu_to_node(cpu);
+
+	if (nid == NUMA_NO_NODE)
+		return;
+
+	if (remove)
+		cpumask_clear_cpu(cpu, node_to_cpumask_map[nid]);
+	else
+		cpumask_set_cpu(cpu, node_to_cpumask_map[nid]);
+}
+
+void numa_add_cpu(unsigned int cpu)
+{
+	numa_update_cpu(cpu, false);
+}
+
+void numa_remove_cpu(unsigned int cpu)
+{
+	numa_update_cpu(cpu, true);
+}
+#endif
+
+void numa_clear_node(unsigned int cpu)
+{
+	numa_remove_cpu(cpu);
+	set_cpu_numa_node(cpu, NUMA_NO_NODE);
+}
+
+/*
+ * Allocate node_to_cpumask_map based on number of available nodes
+ * Requires node_possible_map to be valid.
+ *
+ * Note: cpumask_of_node() is not valid until after this is done.
+ * (Use CONFIG_DEBUG_PER_CPU_MAPS to check this.)
+ */
+static void __init setup_node_to_cpumask_map(void)
+{
+	int node;
+
+	/* setup nr_node_ids if not done yet */
+	if (nr_node_ids == MAX_NUMNODES)
+		setup_nr_node_ids();
+
+	/* allocate and clear the mapping */
+	for (node = 0; node < nr_node_ids; node++) {
+		alloc_bootmem_cpumask_var(&node_to_cpumask_map[node]);
+		cpumask_clear(node_to_cpumask_map[node]);
+	}
+
+	/* cpumask_of_node() will now work */
+	pr_debug("Node to cpumask map for %u nodes\n", nr_node_ids);
+}
+
+/*
+ * Set the cpu to node and mem mapping
+ */
+void numa_store_cpu_info(unsigned int cpu)
+{
+	set_cpu_numa_node(cpu, cpu_to_node_map[cpu]);
+}
+
+void __init early_map_cpu_to_node(unsigned int cpu, int nid)
+{
+	/* fallback to node 0 */
+	if (nid < 0 || nid >= MAX_NUMNODES || numa_off)
+		nid = 0;
+
+	cpu_to_node_map[cpu] = nid;
+
+	/*
+	 * We should set the numa node of cpu0 as soon as possible, because it
+	 * has already been set up online before. cpu_to_node(0) will soon be
+	 * called.
+	 */
+	if (!cpu)
+		set_cpu_numa_node(cpu, nid);
+}
+
+#ifdef CONFIG_HAVE_SETUP_PER_CPU_AREA
+unsigned long __per_cpu_offset[NR_CPUS] __read_mostly;
+EXPORT_SYMBOL(__per_cpu_offset);
+
+int early_cpu_to_node(int cpu)
+{
+	return cpu_to_node_map[cpu];
+}
+
+static int __init pcpu_cpu_distance(unsigned int from, unsigned int to)
+{
+	return node_distance(early_cpu_to_node(from), early_cpu_to_node(to));
+}
+
+void __init setup_per_cpu_areas(void)
+{
+	unsigned long delta;
+	unsigned int cpu;
+	int rc = -EINVAL;
+
+	if (pcpu_chosen_fc != PCPU_FC_PAGE) {
+		/*
+		 * Always reserve area for module percpu variables.  That's
+		 * what the legacy allocator did.
+		 */
+		rc = pcpu_embed_first_chunk(PERCPU_MODULE_RESERVE,
+					    PERCPU_DYNAMIC_RESERVE, PAGE_SIZE,
+					    pcpu_cpu_distance,
+					    early_cpu_to_node);
+#ifdef CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK
+		if (rc < 0)
+			pr_warn("PERCPU: %s allocator failed (%d), falling back to page size\n",
+				   pcpu_fc_names[pcpu_chosen_fc], rc);
+#endif
+	}
+
+#ifdef CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK
+	if (rc < 0)
+		rc = pcpu_page_first_chunk(PERCPU_MODULE_RESERVE, early_cpu_to_node);
+#endif
+	if (rc < 0)
+		panic("Failed to initialize percpu areas (err=%d).", rc);
+
+	delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
+	for_each_possible_cpu(cpu)
+		__per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu];
+}
+#endif
+
+/*
+ * Initialize NODE_DATA for a node on the local memory
+ */
+static void __init setup_node_data(int nid, u64 start_pfn, u64 end_pfn)
+{
+	if (start_pfn >= end_pfn)
+		pr_info("Initmem setup node %d [<memory-less node>]\n", nid);
+
+	alloc_node_data(nid);
+
+	NODE_DATA(nid)->node_id = nid;
+	NODE_DATA(nid)->node_start_pfn = start_pfn;
+	NODE_DATA(nid)->node_spanned_pages = end_pfn - start_pfn;
+}
+
+static int __init numa_register_nodes(void)
+{
+	int nid;
+
+	/* Check the validity of the memblock/node mapping */
+	if (!memblock_validate_numa_coverage(0))
+		return -EINVAL;
+
+	/* Finally register nodes. */
+	for_each_node_mask(nid, numa_nodes_parsed) {
+		unsigned long start_pfn, end_pfn;
+
+		get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
+		setup_node_data(nid, start_pfn, end_pfn);
+		node_set_online(nid);
+	}
+
+	/* Setup online nodes to actual nodes*/
+	node_possible_map = numa_nodes_parsed;
+
+	return 0;
+}
+
+static int __init numa_init(int (*init_func)(void))
+{
+	int ret;
+
+	nodes_clear(numa_nodes_parsed);
+	nodes_clear(node_possible_map);
+	nodes_clear(node_online_map);
+
+	ret = numa_memblks_init(init_func, /* memblock_force_top_down */ false);
+	if (ret < 0)
+		goto out_free_distance;
+
+	if (nodes_empty(numa_nodes_parsed)) {
+		pr_info("No NUMA configuration found\n");
+		ret = -EINVAL;
+		goto out_free_distance;
+	}
+
+	ret = numa_register_nodes();
+	if (ret < 0)
+		goto out_free_distance;
+
+	setup_node_to_cpumask_map();
+
+	return 0;
+out_free_distance:
+	numa_reset_distance();
+	return ret;
+}
+
+/**
+ * dummy_numa_init() - Fallback dummy NUMA init
+ *
+ * Used if there's no underlying NUMA architecture, NUMA initialization
+ * fails, or NUMA is disabled on the command line.
+ *
+ * Must online at least one node (node 0) and add memory blocks that cover all
+ * allowed memory. It is unlikely that this function fails.
+ *
+ * Return: 0 on success, -errno on failure.
+ */
+static int __init dummy_numa_init(void)
+{
+	phys_addr_t start = memblock_start_of_DRAM();
+	phys_addr_t end = memblock_end_of_DRAM() - 1;
+	int ret;
+
+	if (numa_off)
+		pr_info("NUMA disabled\n"); /* Forced off on command line. */
+	pr_info("Faking a node at [mem %pap-%pap]\n", &start, &end);
+
+	ret = numa_add_memblk(0, start, end + 1);
+	if (ret) {
+		pr_err("NUMA init failed\n");
+		return ret;
+	}
+	node_set(0, numa_nodes_parsed);
+
+	numa_off = true;
+	return 0;
+}
+
+#ifdef CONFIG_ACPI_NUMA
+static int __init arch_acpi_numa_init(void)
+{
+	int ret;
+
+	ret = acpi_numa_init();
+	if (ret) {
+		pr_debug("Failed to initialise from firmware\n");
+		return ret;
+	}
+
+	return srat_disabled() ? -EINVAL : 0;
+}
+#else
+static int __init arch_acpi_numa_init(void)
+{
+	return -EOPNOTSUPP;
+}
+#endif
+
+/**
+ * arch_numa_init() - Initialize NUMA
+ *
+ * Try each configured NUMA initialization method until one succeeds. The
+ * last fallback is dummy single node config encompassing whole memory.
+ */
+void __init arch_numa_init(void)
+{
+	if (!numa_off) {
+		if (!acpi_disabled && !numa_init(arch_acpi_numa_init))
+			return;
+		if (acpi_disabled && !numa_init(of_numa_init))
+			return;
+	}
+
+	numa_init(dummy_numa_init);
+}
+
+#ifdef CONFIG_NUMA_EMU
+void __init numa_emu_update_cpu_to_node(int *emu_nid_to_phys,
+					unsigned int nr_emu_nids)
+{
+	int i, j;
+
+	/*
+	 * Transform cpu_to_node_map table to use emulated nids by
+	 * reverse-mapping phys_nid.  The maps should always exist but fall
+	 * back to zero just in case.
+	 */
+	for (i = 0; i < ARRAY_SIZE(cpu_to_node_map); i++) {
+		if (cpu_to_node_map[i] == NUMA_NO_NODE)
+			continue;
+		for (j = 0; j < nr_emu_nids; j++)
+			if (cpu_to_node_map[i] == emu_nid_to_phys[j])
+				break;
+		cpu_to_node_map[i] = j < nr_emu_nids ? j : 0;
+	}
+}
+
+u64 __init numa_emu_dma_end(void)
+{
+	return memblock_start_of_DRAM() + SZ_4G;
+}
+
+void debug_cpumask_set_cpu(unsigned int cpu, int node, bool enable)
+{
+	struct cpumask *mask;
+
+	if (node == NUMA_NO_NODE)
+		return;
+
+	mask = node_to_cpumask_map[node];
+	if (!cpumask_available(mask)) {
+		pr_err("node_to_cpumask_map[%i] NULL\n", node);
+		dump_stack();
+		return;
+	}
+
+	if (enable)
+		cpumask_set_cpu(cpu, mask);
+	else
+		cpumask_clear_cpu(cpu, mask);
+
+	pr_debug("%s cpu %d node %d: mask now %*pbl\n",
+		 enable ? "numa_add_cpu" : "numa_remove_cpu",
+		 cpu, node, cpumask_pr_args(mask));
+}
+#endif /* CONFIG_NUMA_EMU */
diff --git a/drivers/base/arch_topology.c b/drivers/base/arch_topology.c
index 4d0a0038b476..84ec92bff642 100644
--- a/drivers/base/arch_topology.c
+++ b/drivers/base/arch_topology.c
@@ -7,85 +7,200 @@
  */
 
 #include <linux/acpi.h>
+#include <linux/cacheinfo.h>
+#include <linux/cleanup.h>
 #include <linux/cpu.h>
 #include <linux/cpufreq.h>
+#include <linux/cpu_smt.h>
 #include <linux/device.h>
 #include <linux/of.h>
 #include <linux/slab.h>
-#include <linux/string.h>
 #include <linux/sched/topology.h>
 #include <linux/cpuset.h>
 #include <linux/cpumask.h>
 #include <linux/init.h>
-#include <linux/percpu.h>
+#include <linux/rcupdate.h>
 #include <linux/sched.h>
-#include <linux/smp.h>
+#include <linux/units.h>
 
-__weak bool arch_freq_counters_available(struct cpumask *cpus)
+#define CREATE_TRACE_POINTS
+#include <trace/events/hw_pressure.h>
+
+static DEFINE_PER_CPU(struct scale_freq_data __rcu *, sft_data);
+static struct cpumask scale_freq_counters_mask;
+static bool scale_freq_invariant;
+DEFINE_PER_CPU(unsigned long, capacity_freq_ref) = 0;
+EXPORT_PER_CPU_SYMBOL_GPL(capacity_freq_ref);
+
+static bool supports_scale_freq_counters(const struct cpumask *cpus)
+{
+	return cpumask_subset(cpus, &scale_freq_counters_mask);
+}
+
+bool topology_scale_freq_invariant(void)
+{
+	return cpufreq_supports_freq_invariance() ||
+	       supports_scale_freq_counters(cpu_online_mask);
+}
+
+static void update_scale_freq_invariant(bool status)
 {
-	return false;
+	if (scale_freq_invariant == status)
+		return;
+
+	/*
+	 * Task scheduler behavior depends on frequency invariance support,
+	 * either cpufreq or counter driven. If the support status changes as
+	 * a result of counter initialisation and use, retrigger the build of
+	 * scheduling domains to ensure the information is propagated properly.
+	 */
+	if (topology_scale_freq_invariant() == status) {
+		scale_freq_invariant = status;
+		rebuild_sched_domains_energy();
+	}
+}
+
+void topology_set_scale_freq_source(struct scale_freq_data *data,
+				    const struct cpumask *cpus)
+{
+	struct scale_freq_data *sfd;
+	int cpu;
+
+	/*
+	 * Avoid calling rebuild_sched_domains() unnecessarily if FIE is
+	 * supported by cpufreq.
+	 */
+	if (cpumask_empty(&scale_freq_counters_mask))
+		scale_freq_invariant = topology_scale_freq_invariant();
+
+	rcu_read_lock();
+
+	for_each_cpu(cpu, cpus) {
+		sfd = rcu_dereference(*per_cpu_ptr(&sft_data, cpu));
+
+		/* Use ARCH provided counters whenever possible */
+		if (!sfd || sfd->source != SCALE_FREQ_SOURCE_ARCH) {
+			rcu_assign_pointer(per_cpu(sft_data, cpu), data);
+			cpumask_set_cpu(cpu, &scale_freq_counters_mask);
+		}
+	}
+
+	rcu_read_unlock();
+
+	update_scale_freq_invariant(true);
 }
-DEFINE_PER_CPU(unsigned long, freq_scale) = SCHED_CAPACITY_SCALE;
+EXPORT_SYMBOL_GPL(topology_set_scale_freq_source);
 
-void arch_set_freq_scale(struct cpumask *cpus, unsigned long cur_freq,
-			 unsigned long max_freq)
+void topology_clear_scale_freq_source(enum scale_freq_source source,
+				      const struct cpumask *cpus)
+{
+	struct scale_freq_data *sfd;
+	int cpu;
+
+	rcu_read_lock();
+
+	for_each_cpu(cpu, cpus) {
+		sfd = rcu_dereference(*per_cpu_ptr(&sft_data, cpu));
+
+		if (sfd && sfd->source == source) {
+			rcu_assign_pointer(per_cpu(sft_data, cpu), NULL);
+			cpumask_clear_cpu(cpu, &scale_freq_counters_mask);
+		}
+	}
+
+	rcu_read_unlock();
+
+	/*
+	 * Make sure all references to previous sft_data are dropped to avoid
+	 * use-after-free races.
+	 */
+	synchronize_rcu();
+
+	update_scale_freq_invariant(false);
+}
+EXPORT_SYMBOL_GPL(topology_clear_scale_freq_source);
+
+void topology_scale_freq_tick(void)
+{
+	struct scale_freq_data *sfd = rcu_dereference_sched(*this_cpu_ptr(&sft_data));
+
+	if (sfd)
+		sfd->set_freq_scale();
+}
+
+DEFINE_PER_CPU(unsigned long, arch_freq_scale) = SCHED_CAPACITY_SCALE;
+EXPORT_PER_CPU_SYMBOL_GPL(arch_freq_scale);
+
+void topology_set_freq_scale(const struct cpumask *cpus, unsigned long cur_freq,
+			     unsigned long max_freq)
 {
 	unsigned long scale;
 	int i;
 
+	if (WARN_ON_ONCE(!cur_freq || !max_freq))
+		return;
+
 	/*
 	 * If the use of counters for FIE is enabled, just return as we don't
 	 * want to update the scale factor with information from CPUFREQ.
 	 * Instead the scale factor will be updated from arch_scale_freq_tick.
 	 */
-	if (arch_freq_counters_available(cpus))
+	if (supports_scale_freq_counters(cpus))
 		return;
 
 	scale = (cur_freq << SCHED_CAPACITY_SHIFT) / max_freq;
 
 	for_each_cpu(i, cpus)
-		per_cpu(freq_scale, i) = scale;
+		per_cpu(arch_freq_scale, i) = scale;
 }
 
-DEFINE_PER_CPU(unsigned long, cpu_scale) = SCHED_CAPACITY_SCALE;
-
-void topology_set_cpu_scale(unsigned int cpu, unsigned long capacity)
-{
-	per_cpu(cpu_scale, cpu) = capacity;
-}
+DEFINE_PER_CPU(unsigned long, hw_pressure);
 
-static ssize_t cpu_capacity_show(struct device *dev,
-				 struct device_attribute *attr,
-				 char *buf)
+/**
+ * topology_update_hw_pressure() - Update HW pressure for CPUs
+ * @cpus        : The related CPUs for which capacity has been reduced
+ * @capped_freq : The maximum allowed frequency that CPUs can run at
+ *
+ * Update the value of HW pressure for all @cpus in the mask. The
+ * cpumask should include all (online+offline) affected CPUs, to avoid
+ * operating on stale data when hot-plug is used for some CPUs. The
+ * @capped_freq reflects the currently allowed max CPUs frequency due to
+ * HW capping. It might be also a boost frequency value, which is bigger
+ * than the internal 'capacity_freq_ref' max frequency. In such case the
+ * pressure value should simply be removed, since this is an indication that
+ * there is no HW throttling. The @capped_freq must be provided in kHz.
+ */
+void topology_update_hw_pressure(const struct cpumask *cpus,
+				      unsigned long capped_freq)
 {
-	struct cpu *cpu = container_of(dev, struct cpu, dev);
+	unsigned long max_capacity, capacity, pressure;
+	u32 max_freq;
+	int cpu;
 
-	return sprintf(buf, "%lu\n", topology_get_cpu_scale(cpu->dev.id));
-}
+	cpu = cpumask_first(cpus);
+	max_capacity = arch_scale_cpu_capacity(cpu);
+	max_freq = arch_scale_freq_ref(cpu);
 
-static void update_topology_flags_workfn(struct work_struct *work);
-static DECLARE_WORK(update_topology_flags_work, update_topology_flags_workfn);
-
-static DEVICE_ATTR_RO(cpu_capacity);
+	/*
+	 * Handle properly the boost frequencies, which should simply clean
+	 * the HW pressure value.
+	 */
+	if (max_freq <= capped_freq)
+		capacity = max_capacity;
+	else
+		capacity = mult_frac(max_capacity, capped_freq, max_freq);
 
-static int register_cpu_capacity_sysctl(void)
-{
-	int i;
-	struct device *cpu;
+	pressure = max_capacity - capacity;
 
-	for_each_possible_cpu(i) {
-		cpu = get_cpu_device(i);
-		if (!cpu) {
-			pr_err("%s: too early to get CPU%d device!\n",
-			       __func__, i);
-			continue;
-		}
-		device_create_file(cpu, &dev_attr_cpu_capacity);
-	}
+	trace_hw_pressure_update(cpu, pressure);
 
-	return 0;
+	for_each_cpu(cpu, cpus)
+		WRITE_ONCE(per_cpu(hw_pressure, cpu), pressure);
 }
-subsys_initcall(register_cpu_capacity_sysctl);
+EXPORT_SYMBOL_GPL(topology_update_hw_pressure);
+
+static void update_topology_flags_workfn(struct work_struct *work);
+static DECLARE_WORK(update_topology_flags_work, update_topology_flags_workfn);
 
 static int update_topology;
 
@@ -106,7 +221,6 @@ static void update_topology_flags_workfn(struct work_struct *work)
 	update_topology = 0;
 }
 
-static DEFINE_PER_CPU(u32, freq_factor) = 1;
 static u32 *raw_capacity;
 
 static int free_raw_capacity(void)
@@ -128,13 +242,15 @@ void topology_normalize_cpu_scale(void)
 
 	capacity_scale = 1;
 	for_each_possible_cpu(cpu) {
-		capacity = raw_capacity[cpu] * per_cpu(freq_factor, cpu);
+		capacity = raw_capacity[cpu] *
+			   (per_cpu(capacity_freq_ref, cpu) ?: 1);
 		capacity_scale = max(capacity, capacity_scale);
 	}
 
 	pr_debug("cpu_capacity: capacity_scale=%llu\n", capacity_scale);
 	for_each_possible_cpu(cpu) {
-		capacity = raw_capacity[cpu] * per_cpu(freq_factor, cpu);
+		capacity = raw_capacity[cpu] *
+			   (per_cpu(capacity_freq_ref, cpu) ?: 1);
 		capacity = div64_u64(capacity << SCHED_CAPACITY_SHIFT,
 			capacity_scale);
 		topology_set_cpu_scale(cpu, capacity);
@@ -170,15 +286,15 @@ bool __init topology_parse_cpu_capacity(struct device_node *cpu_node, int cpu)
 			cpu_node, raw_capacity[cpu]);
 
 		/*
-		 * Update freq_factor for calculating early boot cpu capacities.
+		 * Update capacity_freq_ref for calculating early boot CPU capacities.
 		 * For non-clk CPU DVFS mechanism, there's no way to get the
 		 * frequency value now, assuming they are running at the same
-		 * frequency (by keeping the initial freq_factor value).
+		 * frequency (by keeping the initial capacity_freq_ref value).
 		 */
 		cpu_clk = of_clk_get(cpu_node, 0);
-		if (!PTR_ERR_OR_ZERO(cpu_clk)) {
-			per_cpu(freq_factor, cpu) =
-				clk_get_rate(cpu_clk) / 1000;
+		if (!IS_ERR_OR_NULL(cpu_clk)) {
+			per_cpu(capacity_freq_ref, cpu) =
+				clk_get_rate(cpu_clk) / HZ_PER_KHZ;
 			clk_put(cpu_clk);
 		}
 	} else {
@@ -194,6 +310,70 @@ bool __init topology_parse_cpu_capacity(struct device_node *cpu_node, int cpu)
 	return !ret;
 }
 
+void __weak freq_inv_set_max_ratio(int cpu, u64 max_rate)
+{
+}
+
+#ifdef CONFIG_ACPI_CPPC_LIB
+#include <acpi/cppc_acpi.h>
+
+static inline void topology_init_cpu_capacity_cppc(void)
+{
+	u64 capacity, capacity_scale = 0;
+	struct cppc_perf_caps perf_caps;
+	int cpu;
+
+	if (likely(!acpi_cpc_valid()))
+		return;
+
+	raw_capacity = kcalloc(num_possible_cpus(), sizeof(*raw_capacity),
+			       GFP_KERNEL);
+	if (!raw_capacity)
+		return;
+
+	for_each_possible_cpu(cpu) {
+		if (!cppc_get_perf_caps(cpu, &perf_caps) &&
+		    (perf_caps.highest_perf >= perf_caps.nominal_perf) &&
+		    (perf_caps.highest_perf >= perf_caps.lowest_perf)) {
+			raw_capacity[cpu] = perf_caps.highest_perf;
+			capacity_scale = max_t(u64, capacity_scale, raw_capacity[cpu]);
+
+			per_cpu(capacity_freq_ref, cpu) = cppc_perf_to_khz(&perf_caps, raw_capacity[cpu]);
+
+			pr_debug("cpu_capacity: CPU%d cpu_capacity=%u (raw).\n",
+				 cpu, raw_capacity[cpu]);
+			continue;
+		}
+
+		pr_err("cpu_capacity: CPU%d missing/invalid highest performance.\n", cpu);
+		pr_err("cpu_capacity: partial information: fallback to 1024 for all CPUs\n");
+		goto exit;
+	}
+
+	for_each_possible_cpu(cpu) {
+		freq_inv_set_max_ratio(cpu,
+				       per_cpu(capacity_freq_ref, cpu) * HZ_PER_KHZ);
+
+		capacity = raw_capacity[cpu];
+		capacity = div64_u64(capacity << SCHED_CAPACITY_SHIFT,
+				     capacity_scale);
+		topology_set_cpu_scale(cpu, capacity);
+		pr_debug("cpu_capacity: CPU%d cpu_capacity=%lu\n",
+			cpu, topology_get_cpu_scale(cpu));
+	}
+
+	schedule_work(&update_topology_flags_work);
+	pr_debug("cpu_capacity: cpu_capacity initialization done\n");
+
+exit:
+	free_raw_capacity();
+}
+void acpi_processor_init_invariance_cppc(void)
+{
+	topology_init_cpu_capacity_cppc();
+}
+#endif
+
 #ifdef CONFIG_CPU_FREQ
 static cpumask_var_t cpus_to_visit;
 static void parsing_done_workfn(struct work_struct *work);
@@ -207,9 +387,6 @@ init_cpu_capacity_callback(struct notifier_block *nb,
 	struct cpufreq_policy *policy = data;
 	int cpu;
 
-	if (!raw_capacity)
-		return 0;
-
 	if (val != CPUFREQ_CREATE_POLICY)
 		return 0;
 
@@ -219,13 +396,18 @@ init_cpu_capacity_callback(struct notifier_block *nb,
 
 	cpumask_andnot(cpus_to_visit, cpus_to_visit, policy->related_cpus);
 
-	for_each_cpu(cpu, policy->related_cpus)
-		per_cpu(freq_factor, cpu) = policy->cpuinfo.max_freq / 1000;
+	for_each_cpu(cpu, policy->related_cpus) {
+		per_cpu(capacity_freq_ref, cpu) = policy->cpuinfo.max_freq;
+		freq_inv_set_max_ratio(cpu,
+				       per_cpu(capacity_freq_ref, cpu) * HZ_PER_KHZ);
+	}
 
 	if (cpumask_empty(cpus_to_visit)) {
-		topology_normalize_cpu_scale();
-		schedule_work(&update_topology_flags_work);
-		free_raw_capacity();
+		if (raw_capacity) {
+			topology_normalize_cpu_scale();
+			schedule_work(&update_topology_flags_work);
+			free_raw_capacity();
+		}
 		pr_debug("cpu_capacity: parsing done\n");
 		schedule_work(&parsing_done_work);
 	}
@@ -242,11 +424,10 @@ static int __init register_cpufreq_notifier(void)
 	int ret;
 
 	/*
-	 * on ACPI-based systems we need to use the default cpu capacity
-	 * until we have the necessary code to parse the cpu capacity, so
-	 * skip registering cpufreq notifier.
+	 * On ACPI-based systems skip registering cpufreq notifier as cpufreq
+	 * information is not needed for cpu capacity initialization.
 	 */
-	if (!acpi_disabled || !raw_capacity)
+	if (!acpi_disabled)
 		return -EINVAL;
 
 	if (!alloc_cpumask_var(&cpus_to_visit, GFP_KERNEL))
@@ -276,6 +457,10 @@ core_initcall(free_raw_capacity);
 #endif
 
 #if defined(CONFIG_ARM64) || defined(CONFIG_RISCV)
+
+/* Used to enable the SMT control */
+static unsigned int max_smt_thread_num = 1;
+
 /*
  * This function returns the logic cpu number of the node.
  * There are basically three kinds of return values:
@@ -288,10 +473,10 @@ core_initcall(free_raw_capacity);
  */
 static int __init get_cpu_for_node(struct device_node *node)
 {
-	struct device_node *cpu_node;
 	int cpu;
+	struct device_node *cpu_node __free(device_node) =
+		of_parse_phandle(node, "cpu", 0);
 
-	cpu_node = of_parse_phandle(node, "cpu", 0);
 	if (!cpu_node)
 		return -1;
 
@@ -302,38 +487,40 @@ static int __init get_cpu_for_node(struct device_node *node)
 		pr_info("CPU node for %pOF exist but the possible cpu range is :%*pbl\n",
 			cpu_node, cpumask_pr_args(cpu_possible_mask));
 
-	of_node_put(cpu_node);
 	return cpu;
 }
 
 static int __init parse_core(struct device_node *core, int package_id,
-			     int core_id)
+			     int cluster_id, int core_id)
 {
 	char name[20];
 	bool leaf = true;
 	int i = 0;
 	int cpu;
-	struct device_node *t;
 
 	do {
 		snprintf(name, sizeof(name), "thread%d", i);
-		t = of_get_child_by_name(core, name);
-		if (t) {
-			leaf = false;
-			cpu = get_cpu_for_node(t);
-			if (cpu >= 0) {
-				cpu_topology[cpu].package_id = package_id;
-				cpu_topology[cpu].core_id = core_id;
-				cpu_topology[cpu].thread_id = i;
-			} else if (cpu != -ENODEV) {
-				pr_err("%pOF: Can't get CPU for thread\n", t);
-				of_node_put(t);
-				return -EINVAL;
-			}
-			of_node_put(t);
+		struct device_node *t __free(device_node) =
+			of_get_child_by_name(core, name);
+
+		if (!t)
+			break;
+
+		leaf = false;
+		cpu = get_cpu_for_node(t);
+		if (cpu >= 0) {
+			cpu_topology[cpu].package_id = package_id;
+			cpu_topology[cpu].cluster_id = cluster_id;
+			cpu_topology[cpu].core_id = core_id;
+			cpu_topology[cpu].thread_id = i;
+		} else if (cpu != -ENODEV) {
+			pr_err("%pOF: Can't get CPU for thread\n", t);
+			return -EINVAL;
 		}
 		i++;
-	} while (t);
+	} while (1);
+
+	max_smt_thread_num = max_t(unsigned int, max_smt_thread_num, i);
 
 	cpu = get_cpu_for_node(core);
 	if (cpu >= 0) {
@@ -344,6 +531,7 @@ static int __init parse_core(struct device_node *core, int package_id,
 		}
 
 		cpu_topology[cpu].package_id = package_id;
+		cpu_topology[cpu].cluster_id = cluster_id;
 		cpu_topology[cpu].core_id = core_id;
 	} else if (leaf && cpu != -ENODEV) {
 		pr_err("%pOF: Can't get CPU for leaf core\n", core);
@@ -353,13 +541,12 @@ static int __init parse_core(struct device_node *core, int package_id,
 	return 0;
 }
 
-static int __init parse_cluster(struct device_node *cluster, int depth)
+static int __init parse_cluster(struct device_node *cluster, int package_id,
+				int cluster_id, int depth)
 {
 	char name[20];
 	bool leaf = true;
 	bool has_cores = false;
-	struct device_node *c;
-	static int package_id __initdata;
 	int core_id = 0;
 	int i, ret;
 
@@ -371,63 +558,103 @@ static int __init parse_cluster(struct device_node *cluster, int depth)
 	i = 0;
 	do {
 		snprintf(name, sizeof(name), "cluster%d", i);
-		c = of_get_child_by_name(cluster, name);
-		if (c) {
-			leaf = false;
-			ret = parse_cluster(c, depth + 1);
-			of_node_put(c);
-			if (ret != 0)
-				return ret;
-		}
+		struct device_node *c __free(device_node) =
+			of_get_child_by_name(cluster, name);
+
+		if (!c)
+			break;
+
+		leaf = false;
+		ret = parse_cluster(c, package_id, i, depth + 1);
+		if (depth > 0)
+			pr_warn("Topology for clusters of clusters not yet supported\n");
+		if (ret != 0)
+			return ret;
 		i++;
-	} while (c);
+	} while (1);
 
 	/* Now check for cores */
 	i = 0;
 	do {
 		snprintf(name, sizeof(name), "core%d", i);
-		c = of_get_child_by_name(cluster, name);
-		if (c) {
-			has_cores = true;
-
-			if (depth == 0) {
-				pr_err("%pOF: cpu-map children should be clusters\n",
-				       c);
-				of_node_put(c);
-				return -EINVAL;
-			}
+		struct device_node *c __free(device_node) =
+			of_get_child_by_name(cluster, name);
 
-			if (leaf) {
-				ret = parse_core(c, package_id, core_id++);
-			} else {
-				pr_err("%pOF: Non-leaf cluster with core %s\n",
-				       cluster, name);
-				ret = -EINVAL;
-			}
+		if (!c)
+			break;
 
-			of_node_put(c);
+		has_cores = true;
+
+		if (depth == 0) {
+			pr_err("%pOF: cpu-map children should be clusters\n", c);
+			return -EINVAL;
+		}
+
+		if (leaf) {
+			ret = parse_core(c, package_id, cluster_id, core_id++);
 			if (ret != 0)
 				return ret;
+		} else {
+			pr_err("%pOF: Non-leaf cluster with core %s\n",
+			       cluster, name);
+			return -EINVAL;
 		}
+
 		i++;
-	} while (c);
+	} while (1);
 
 	if (leaf && !has_cores)
 		pr_warn("%pOF: empty cluster\n", cluster);
 
-	if (leaf)
+	return 0;
+}
+
+static int __init parse_socket(struct device_node *socket)
+{
+	char name[20];
+	bool has_socket = false;
+	int package_id = 0, ret;
+
+	do {
+		snprintf(name, sizeof(name), "socket%d", package_id);
+		struct device_node *c __free(device_node) =
+			of_get_child_by_name(socket, name);
+
+		if (!c)
+			break;
+
+		has_socket = true;
+		ret = parse_cluster(c, package_id, -1, 0);
+		if (ret != 0)
+			return ret;
+
 		package_id++;
+	} while (1);
 
-	return 0;
+	if (!has_socket)
+		ret = parse_cluster(socket, 0, -1, 0);
+
+	/*
+	 * Reset the max_smt_thread_num to 1 on failure. Since on failure
+	 * we need to notify the framework the SMT is not supported, but
+	 * max_smt_thread_num can be initialized to the SMT thread number
+	 * of the cores which are successfully parsed.
+	 */
+	if (ret)
+		max_smt_thread_num = 1;
+
+	cpu_smt_set_num_threads(max_smt_thread_num, max_smt_thread_num);
+
+	return ret;
 }
 
 static int __init parse_dt_topology(void)
 {
-	struct device_node *cn, *map;
 	int ret = 0;
 	int cpu;
+	struct device_node *cn __free(device_node) =
+		of_find_node_by_path("/cpus");
 
-	cn = of_find_node_by_path("/cpus");
 	if (!cn) {
 		pr_err("No CPU information found in DT\n");
 		return 0;
@@ -437,13 +664,15 @@ static int __init parse_dt_topology(void)
 	 * When topology is provided cpu-map is essentially a root
 	 * cluster with restricted subnodes.
 	 */
-	map = of_get_child_by_name(cn, "cpu-map");
+	struct device_node *map __free(device_node) =
+		of_get_child_by_name(cn, "cpu-map");
+
 	if (!map)
-		goto out;
+		return ret;
 
-	ret = parse_cluster(map, 0);
+	ret = parse_socket(map);
 	if (ret != 0)
-		goto out_map;
+		return ret;
 
 	topology_normalize_cpu_scale();
 
@@ -452,13 +681,10 @@ static int __init parse_dt_topology(void)
 	 * only mark cores described in the DT as possible.
 	 */
 	for_each_possible_cpu(cpu)
-		if (cpu_topology[cpu].package_id == -1)
-			ret = -EINVAL;
+		if (cpu_topology[cpu].package_id < 0) {
+			return -EINVAL;
+		}
 
-out_map:
-	of_node_put(map);
-out:
-	of_node_put(cn);
 	return ret;
 }
 #endif
@@ -478,24 +704,51 @@ const struct cpumask *cpu_coregroup_mask(int cpu)
 		/* not numa in package, lets use the package siblings */
 		core_mask = &cpu_topology[cpu].core_sibling;
 	}
-	if (cpu_topology[cpu].llc_id != -1) {
+
+	if (last_level_cache_is_valid(cpu)) {
 		if (cpumask_subset(&cpu_topology[cpu].llc_sibling, core_mask))
 			core_mask = &cpu_topology[cpu].llc_sibling;
 	}
 
+	/*
+	 * For systems with no shared cpu-side LLC but with clusters defined,
+	 * extend core_mask to cluster_siblings. The sched domain builder will
+	 * then remove MC as redundant with CLS if SCHED_CLUSTER is enabled.
+	 */
+	if (IS_ENABLED(CONFIG_SCHED_CLUSTER) &&
+	    cpumask_subset(core_mask, &cpu_topology[cpu].cluster_sibling))
+		core_mask = &cpu_topology[cpu].cluster_sibling;
+
 	return core_mask;
 }
 
+const struct cpumask *cpu_clustergroup_mask(int cpu)
+{
+	/*
+	 * Forbid cpu_clustergroup_mask() to span more or the same CPUs as
+	 * cpu_coregroup_mask().
+	 */
+	if (cpumask_subset(cpu_coregroup_mask(cpu),
+			   &cpu_topology[cpu].cluster_sibling))
+		return topology_sibling_cpumask(cpu);
+
+	return &cpu_topology[cpu].cluster_sibling;
+}
+
 void update_siblings_masks(unsigned int cpuid)
 {
 	struct cpu_topology *cpu_topo, *cpuid_topo = &cpu_topology[cpuid];
-	int cpu;
+	int cpu, ret;
+
+	ret = detect_cache_attributes(cpuid);
+	if (ret && ret != -ENOENT)
+		pr_info("Early cacheinfo allocation failed, ret = %d\n", ret);
 
 	/* update core and thread sibling masks */
 	for_each_online_cpu(cpu) {
 		cpu_topo = &cpu_topology[cpu];
 
-		if (cpuid_topo->llc_id == cpu_topo->llc_id) {
+		if (last_level_cache_is_shared(cpu, cpuid)) {
 			cpumask_set_cpu(cpu, &cpuid_topo->llc_sibling);
 			cpumask_set_cpu(cpuid, &cpu_topo->llc_sibling);
 		}
@@ -506,6 +759,14 @@ void update_siblings_masks(unsigned int cpuid)
 		cpumask_set_cpu(cpuid, &cpu_topo->core_sibling);
 		cpumask_set_cpu(cpu, &cpuid_topo->core_sibling);
 
+		if (cpuid_topo->cluster_id != cpu_topo->cluster_id)
+			continue;
+
+		if (cpuid_topo->cluster_id >= 0) {
+			cpumask_set_cpu(cpu, &cpuid_topo->cluster_sibling);
+			cpumask_set_cpu(cpuid, &cpu_topo->cluster_sibling);
+		}
+
 		if (cpuid_topo->core_id != cpu_topo->core_id)
 			continue;
 
@@ -521,6 +782,9 @@ static void clear_cpu_topology(int cpu)
 	cpumask_clear(&cpu_topo->llc_sibling);
 	cpumask_set_cpu(cpu, &cpu_topo->llc_sibling);
 
+	cpumask_clear(&cpu_topo->cluster_sibling);
+	cpumask_set_cpu(cpu, &cpu_topo->cluster_sibling);
+
 	cpumask_clear(&cpu_topo->core_sibling);
 	cpumask_set_cpu(cpu, &cpu_topo->core_sibling);
 	cpumask_clear(&cpu_topo->thread_sibling);
@@ -536,8 +800,8 @@ void __init reset_cpu_topology(void)
 
 		cpu_topo->thread_id = -1;
 		cpu_topo->core_id = -1;
+		cpu_topo->cluster_id = -1;
 		cpu_topo->package_id = -1;
-		cpu_topo->llc_id = -1;
 
 		clear_cpu_topology(cpu);
 	}
@@ -551,29 +815,158 @@ void remove_cpu_topology(unsigned int cpu)
 		cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
 	for_each_cpu(sibling, topology_sibling_cpumask(cpu))
 		cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
+	for_each_cpu(sibling, topology_cluster_cpumask(cpu))
+		cpumask_clear_cpu(cpu, topology_cluster_cpumask(sibling));
 	for_each_cpu(sibling, topology_llc_cpumask(cpu))
 		cpumask_clear_cpu(cpu, topology_llc_cpumask(sibling));
 
 	clear_cpu_topology(cpu);
 }
 
+#if defined(CONFIG_ARM64) || defined(CONFIG_RISCV)
+struct cpu_smt_info {
+	unsigned int thread_num;
+	int core_id;
+};
+
+static bool __init acpi_cpu_is_threaded(int cpu)
+{
+	int is_threaded = acpi_pptt_cpu_is_thread(cpu);
+
+	/*
+	 * if the PPTT doesn't have thread information, check for architecture
+	 * specific fallback if available
+	 */
+	if (is_threaded < 0)
+		is_threaded = arch_cpu_is_threaded();
+
+	return !!is_threaded;
+}
+
+/*
+ * Propagate the topology information of the processor_topology_node tree to the
+ * cpu_topology array.
+ */
 __weak int __init parse_acpi_topology(void)
 {
+	unsigned int max_smt_thread_num = 1;
+	struct cpu_smt_info *entry;
+	struct xarray hetero_cpu;
+	unsigned long hetero_id;
+	int cpu, topology_id;
+
+	if (acpi_disabled)
+		return 0;
+
+	xa_init(&hetero_cpu);
+
+	for_each_possible_cpu(cpu) {
+		topology_id = find_acpi_cpu_topology(cpu, 0);
+		if (topology_id < 0)
+			return topology_id;
+
+		if (acpi_cpu_is_threaded(cpu)) {
+			cpu_topology[cpu].thread_id = topology_id;
+			topology_id = find_acpi_cpu_topology(cpu, 1);
+			cpu_topology[cpu].core_id   = topology_id;
+
+			/*
+			 * In the PPTT, CPUs below a node with the 'identical
+			 * implementation' flag have the same number of threads.
+			 * Count the number of threads for only one CPU (i.e.
+			 * one core_id) among those with the same hetero_id.
+			 * See the comment of find_acpi_cpu_topology_hetero_id()
+			 * for more details.
+			 *
+			 * One entry is created for each node having:
+			 * - the 'identical implementation' flag
+			 * - its parent not having the flag
+			 */
+			hetero_id = find_acpi_cpu_topology_hetero_id(cpu);
+			entry = xa_load(&hetero_cpu, hetero_id);
+			if (!entry) {
+				entry = kzalloc(sizeof(*entry), GFP_KERNEL);
+				WARN_ON_ONCE(!entry);
+
+				if (entry) {
+					entry->core_id = topology_id;
+					entry->thread_num = 1;
+					xa_store(&hetero_cpu, hetero_id,
+						 entry, GFP_KERNEL);
+				}
+			} else if (entry->core_id == topology_id) {
+				entry->thread_num++;
+			}
+		} else {
+			cpu_topology[cpu].thread_id  = -1;
+			cpu_topology[cpu].core_id    = topology_id;
+		}
+		topology_id = find_acpi_cpu_topology_cluster(cpu);
+		cpu_topology[cpu].cluster_id = topology_id;
+		topology_id = find_acpi_cpu_topology_package(cpu);
+		cpu_topology[cpu].package_id = topology_id;
+	}
+
+	/*
+	 * This is a short loop since the number of XArray elements is the
+	 * number of heterogeneous CPU clusters. On a homogeneous system
+	 * there's only one entry in the XArray.
+	 */
+	xa_for_each(&hetero_cpu, hetero_id, entry) {
+		max_smt_thread_num = max(max_smt_thread_num, entry->thread_num);
+		xa_erase(&hetero_cpu, hetero_id);
+		kfree(entry);
+	}
+
+	cpu_smt_set_num_threads(max_smt_thread_num, max_smt_thread_num);
+	xa_destroy(&hetero_cpu);
 	return 0;
 }
 
-#if defined(CONFIG_ARM64) || defined(CONFIG_RISCV)
 void __init init_cpu_topology(void)
 {
+	int cpu, ret;
+
 	reset_cpu_topology();
+	ret = parse_acpi_topology();
+	if (!ret)
+		ret = of_have_populated_dt() && parse_dt_topology();
 
-	/*
-	 * Discard anything that was parsed if we hit an error so we
-	 * don't use partial information.
-	 */
-	if (parse_acpi_topology())
-		reset_cpu_topology();
-	else if (of_have_populated_dt() && parse_dt_topology())
+	if (ret) {
+		/*
+		 * Discard anything that was parsed if we hit an error so we
+		 * don't use partial information. But do not return yet to give
+		 * arch-specific early cache level detection a chance to run.
+		 */
 		reset_cpu_topology();
+	}
+
+	for_each_possible_cpu(cpu) {
+		ret = fetch_cache_info(cpu);
+		if (!ret)
+			continue;
+		else if (ret != -ENOENT)
+			pr_err("Early cacheinfo failed, ret = %d\n", ret);
+		return;
+	}
+}
+
+void store_cpu_topology(unsigned int cpuid)
+{
+	struct cpu_topology *cpuid_topo = &cpu_topology[cpuid];
+
+	if (cpuid_topo->package_id != -1)
+		goto topology_populated;
+
+	cpuid_topo->thread_id = -1;
+	cpuid_topo->core_id = cpuid;
+	cpuid_topo->package_id = cpu_to_node(cpuid);
+
+	pr_debug("CPU%u: package %d core %d thread %d\n",
+		 cpuid, cpuid_topo->package_id, cpuid_topo->core_id,
+		 cpuid_topo->thread_id);
+
+topology_populated:
+	update_siblings_masks(cpuid);
 }
 #endif
diff --git a/drivers/base/attribute_container.c b/drivers/base/attribute_container.c
index f7bd0f4db13d..b6f941a6ab69 100644
--- a/drivers/base/attribute_container.c
+++ b/drivers/base/attribute_container.c
@@ -284,8 +284,8 @@ fail:
  * matching classdev or fail all of them.
  *
  * @dev:  The generic device to run the trigger for
- * @fn	  the function to execute for each classdev.
- * @undo  A function to undo the work previously done in case of error
+ * @fn:   the function to execute for each classdev.
+ * @undo: A function to undo the work previously done in case of error
  *
  * This function is a safe version of
  * attribute_container_device_trigger. It stops on the first error and
@@ -343,11 +343,10 @@ attribute_container_device_trigger_safe(struct device *dev,
  * attribute_container_device_trigger - execute a trigger for each matching classdev
  *
  * @dev:  The generic device to run the trigger for
- * @fn	  the function to execute for each classdev.
+ * @fn:   the function to execute for each classdev.
  *
  * This function is for executing a trigger when you need to know both
- * the container and the classdev.  If you only care about the
- * container, then use attribute_container_trigger() instead.
+ * the container and the classdev.
  */
 void
 attribute_container_device_trigger(struct device *dev,
@@ -379,33 +378,6 @@ attribute_container_device_trigger(struct device *dev,
 }
 
 /**
- * attribute_container_trigger - trigger a function for each matching container
- *
- * @dev:  The generic device to activate the trigger for
- * @fn:	  the function to trigger
- *
- * This routine triggers a function that only needs to know the
- * matching containers (not the classdev) associated with a device.
- * It is more lightweight than attribute_container_device_trigger, so
- * should be used in preference unless the triggering function
- * actually needs to know the classdev.
- */
-void
-attribute_container_trigger(struct device *dev,
-			    int (*fn)(struct attribute_container *,
-				      struct device *))
-{
-	struct attribute_container *cont;
-
-	mutex_lock(&attribute_container_mutex);
-	list_for_each_entry(cont, &attribute_container_list, node) {
-		if (cont->match(cont, dev))
-			fn(cont, dev);
-	}
-	mutex_unlock(&attribute_container_mutex);
-}
-
-/**
  * attribute_container_add_attrs - add attributes
  *
  * @classdev: The class device
@@ -459,20 +431,6 @@ attribute_container_add_class_device(struct device *classdev)
 }
 
 /**
- * attribute_container_add_class_device_adapter - simple adapter for triggers
- *
- * This function is identical to attribute_container_add_class_device except
- * that it is designed to be called from the triggers
- */
-int
-attribute_container_add_class_device_adapter(struct attribute_container *cont,
-					     struct device *dev,
-					     struct device *classdev)
-{
-	return attribute_container_add_class_device(classdev);
-}
-
-/**
  * attribute_container_remove_attrs - remove any attribute files
  *
  * @classdev: The class device to remove the files from
diff --git a/drivers/base/auxiliary.c b/drivers/base/auxiliary.c
new file mode 100644
index 000000000000..04bdbff4dbe5
--- /dev/null
+++ b/drivers/base/auxiliary.c
@@ -0,0 +1,508 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2019-2020 Intel Corporation
+ *
+ * Please see Documentation/driver-api/auxiliary_bus.rst for more information.
+ */
+
+#define pr_fmt(fmt) "%s:%s: " fmt, KBUILD_MODNAME, __func__
+
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_runtime.h>
+#include <linux/string.h>
+#include <linux/auxiliary_bus.h>
+#include "base.h"
+
+/**
+ * DOC: PURPOSE
+ *
+ * In some subsystems, the functionality of the core device (PCI/ACPI/other) is
+ * too complex for a single device to be managed by a monolithic driver (e.g.
+ * Sound Open Firmware), multiple devices might implement a common intersection
+ * of functionality (e.g. NICs + RDMA), or a driver may want to export an
+ * interface for another subsystem to drive (e.g. SIOV Physical Function export
+ * Virtual Function management).  A split of the functionality into child-
+ * devices representing sub-domains of functionality makes it possible to
+ * compartmentalize, layer, and distribute domain-specific concerns via a Linux
+ * device-driver model.
+ *
+ * An example for this kind of requirement is the audio subsystem where a
+ * single IP is handling multiple entities such as HDMI, Soundwire, local
+ * devices such as mics/speakers etc. The split for the core's functionality
+ * can be arbitrary or be defined by the DSP firmware topology and include
+ * hooks for test/debug. This allows for the audio core device to be minimal
+ * and focused on hardware-specific control and communication.
+ *
+ * Each auxiliary_device represents a part of its parent functionality. The
+ * generic behavior can be extended and specialized as needed by encapsulating
+ * an auxiliary_device within other domain-specific structures and the use of
+ * .ops callbacks. Devices on the auxiliary bus do not share any structures and
+ * the use of a communication channel with the parent is domain-specific.
+ *
+ * Note that ops are intended as a way to augment instance behavior within a
+ * class of auxiliary devices, it is not the mechanism for exporting common
+ * infrastructure from the parent. Consider EXPORT_SYMBOL_NS() to convey
+ * infrastructure from the parent module to the auxiliary module(s).
+ */
+
+/**
+ * DOC: USAGE
+ *
+ * The auxiliary bus is to be used when a driver and one or more kernel
+ * modules, who share a common header file with the driver, need a mechanism to
+ * connect and provide access to a shared object allocated by the
+ * auxiliary_device's registering driver.  The registering driver for the
+ * auxiliary_device(s) and the kernel module(s) registering auxiliary_drivers
+ * can be from the same subsystem, or from multiple subsystems.
+ *
+ * The emphasis here is on a common generic interface that keeps subsystem
+ * customization out of the bus infrastructure.
+ *
+ * One example is a PCI network device that is RDMA-capable and exports a child
+ * device to be driven by an auxiliary_driver in the RDMA subsystem.  The PCI
+ * driver allocates and registers an auxiliary_device for each physical
+ * function on the NIC.  The RDMA driver registers an auxiliary_driver that
+ * claims each of these auxiliary_devices.  This conveys data/ops published by
+ * the parent PCI device/driver to the RDMA auxiliary_driver.
+ *
+ * Another use case is for the PCI device to be split out into multiple sub
+ * functions.  For each sub function an auxiliary_device is created.  A PCI sub
+ * function driver binds to such devices that creates its own one or more class
+ * devices.  A PCI sub function auxiliary device is likely to be contained in a
+ * struct with additional attributes such as user defined sub function number
+ * and optional attributes such as resources and a link to the parent device.
+ * These attributes could be used by systemd/udev; and hence should be
+ * initialized before a driver binds to an auxiliary_device.
+ *
+ * A key requirement for utilizing the auxiliary bus is that there is no
+ * dependency on a physical bus, device, register accesses or regmap support.
+ * These individual devices split from the core cannot live on the platform bus
+ * as they are not physical devices that are controlled by DT/ACPI.  The same
+ * argument applies for not using MFD in this scenario as MFD relies on
+ * individual function devices being physical devices.
+ */
+
+/**
+ * DOC: EXAMPLE
+ *
+ * Auxiliary devices are created and registered by a subsystem-level core
+ * device that needs to break up its functionality into smaller fragments. One
+ * way to extend the scope of an auxiliary_device is to encapsulate it within a
+ * domain-specific structure defined by the parent device. This structure
+ * contains the auxiliary_device and any associated shared data/callbacks
+ * needed to establish the connection with the parent.
+ *
+ * An example is:
+ *
+ * .. code-block:: c
+ *
+ *         struct foo {
+ *		struct auxiliary_device auxdev;
+ *		void (*connect)(struct auxiliary_device *auxdev);
+ *		void (*disconnect)(struct auxiliary_device *auxdev);
+ *		void *data;
+ *        };
+ *
+ * The parent device then registers the auxiliary_device by calling
+ * auxiliary_device_init(), and then auxiliary_device_add(), with the pointer
+ * to the auxdev member of the above structure. The parent provides a name for
+ * the auxiliary_device that, combined with the parent's KBUILD_MODNAME,
+ * creates a match_name that is be used for matching and binding with a driver.
+ *
+ * Whenever an auxiliary_driver is registered, based on the match_name, the
+ * auxiliary_driver's probe() is invoked for the matching devices.  The
+ * auxiliary_driver can also be encapsulated inside custom drivers that make
+ * the core device's functionality extensible by adding additional
+ * domain-specific ops as follows:
+ *
+ * .. code-block:: c
+ *
+ *	struct my_ops {
+ *		void (*send)(struct auxiliary_device *auxdev);
+ *		void (*receive)(struct auxiliary_device *auxdev);
+ *	};
+ *
+ *
+ *	struct my_driver {
+ *		struct auxiliary_driver auxiliary_drv;
+ *		const struct my_ops ops;
+ *	};
+ *
+ * An example of this type of usage is:
+ *
+ * .. code-block:: c
+ *
+ *	const struct auxiliary_device_id my_auxiliary_id_table[] = {
+ *		{ .name = "foo_mod.foo_dev" },
+ *		{ },
+ *	};
+ *
+ *	const struct my_ops my_custom_ops = {
+ *		.send = my_tx,
+ *		.receive = my_rx,
+ *	};
+ *
+ *	const struct my_driver my_drv = {
+ *		.auxiliary_drv = {
+ *			.name = "myauxiliarydrv",
+ *			.id_table = my_auxiliary_id_table,
+ *			.probe = my_probe,
+ *			.remove = my_remove,
+ *			.shutdown = my_shutdown,
+ *		},
+ *		.ops = my_custom_ops,
+ *	};
+ *
+ * Please note that such custom ops approach is valid, but it is hard to implement
+ * it right without global locks per-device to protect from auxiliary_drv removal
+ * during call to that ops. In addition, this implementation lacks proper module
+ * dependency, which causes to load/unload races between auxiliary parent and devices
+ * modules.
+ *
+ * The most easiest way to provide these ops reliably without needing to
+ * have a lock is to EXPORT_SYMBOL*() them and rely on already existing
+ * modules infrastructure for validity and correct dependencies chains.
+ */
+
+static const struct auxiliary_device_id *auxiliary_match_id(const struct auxiliary_device_id *id,
+							    const struct auxiliary_device *auxdev)
+{
+	const char *auxdev_name = dev_name(&auxdev->dev);
+	const char *p = strrchr(auxdev_name, '.');
+	int match_size;
+
+	if (!p)
+		return NULL;
+	match_size = p - auxdev_name;
+
+	for (; id->name[0]; id++) {
+		/* use dev_name(&auxdev->dev) prefix before last '.' char to match to */
+		if (strlen(id->name) == match_size &&
+		    !strncmp(auxdev_name, id->name, match_size))
+			return id;
+	}
+	return NULL;
+}
+
+static int auxiliary_match(struct device *dev, const struct device_driver *drv)
+{
+	struct auxiliary_device *auxdev = to_auxiliary_dev(dev);
+	const struct auxiliary_driver *auxdrv = to_auxiliary_drv(drv);
+
+	return !!auxiliary_match_id(auxdrv->id_table, auxdev);
+}
+
+static int auxiliary_uevent(const struct device *dev, struct kobj_uevent_env *env)
+{
+	const char *name, *p;
+
+	name = dev_name(dev);
+	p = strrchr(name, '.');
+
+	return add_uevent_var(env, "MODALIAS=%s%.*s", AUXILIARY_MODULE_PREFIX,
+			      (int)(p - name), name);
+}
+
+static const struct dev_pm_ops auxiliary_dev_pm_ops = {
+	SET_RUNTIME_PM_OPS(pm_generic_runtime_suspend, pm_generic_runtime_resume, NULL)
+	SET_SYSTEM_SLEEP_PM_OPS(pm_generic_suspend, pm_generic_resume)
+};
+
+static int auxiliary_bus_probe(struct device *dev)
+{
+	const struct auxiliary_driver *auxdrv = to_auxiliary_drv(dev->driver);
+	struct auxiliary_device *auxdev = to_auxiliary_dev(dev);
+	int ret;
+
+	ret = dev_pm_domain_attach(dev, PD_FLAG_ATTACH_POWER_ON |
+					PD_FLAG_DETACH_POWER_OFF);
+	if (ret) {
+		dev_warn(dev, "Failed to attach to PM Domain : %d\n", ret);
+		return ret;
+	}
+
+	return auxdrv->probe(auxdev, auxiliary_match_id(auxdrv->id_table, auxdev));
+}
+
+static void auxiliary_bus_remove(struct device *dev)
+{
+	const struct auxiliary_driver *auxdrv = to_auxiliary_drv(dev->driver);
+	struct auxiliary_device *auxdev = to_auxiliary_dev(dev);
+
+	if (auxdrv->remove)
+		auxdrv->remove(auxdev);
+}
+
+static void auxiliary_bus_shutdown(struct device *dev)
+{
+	const struct auxiliary_driver *auxdrv = NULL;
+	struct auxiliary_device *auxdev;
+
+	if (dev->driver) {
+		auxdrv = to_auxiliary_drv(dev->driver);
+		auxdev = to_auxiliary_dev(dev);
+	}
+
+	if (auxdrv && auxdrv->shutdown)
+		auxdrv->shutdown(auxdev);
+}
+
+static const struct bus_type auxiliary_bus_type = {
+	.name = "auxiliary",
+	.probe = auxiliary_bus_probe,
+	.remove = auxiliary_bus_remove,
+	.shutdown = auxiliary_bus_shutdown,
+	.match = auxiliary_match,
+	.uevent = auxiliary_uevent,
+	.pm = &auxiliary_dev_pm_ops,
+};
+
+/**
+ * auxiliary_device_init - check auxiliary_device and initialize
+ * @auxdev: auxiliary device struct
+ *
+ * This is the second step in the three-step process to register an
+ * auxiliary_device.
+ *
+ * When this function returns an error code, then the device_initialize will
+ * *not* have been performed, and the caller will be responsible to free any
+ * memory allocated for the auxiliary_device in the error path directly.
+ *
+ * It returns 0 on success.  On success, the device_initialize has been
+ * performed.  After this point any error unwinding will need to include a call
+ * to auxiliary_device_uninit().  In this post-initialize error scenario, a call
+ * to the device's .release callback will be triggered, and all memory clean-up
+ * is expected to be handled there.
+ */
+int auxiliary_device_init(struct auxiliary_device *auxdev)
+{
+	struct device *dev = &auxdev->dev;
+
+	if (!dev->parent) {
+		pr_err("auxiliary_device has a NULL dev->parent\n");
+		return -EINVAL;
+	}
+
+	if (!auxdev->name) {
+		pr_err("auxiliary_device has a NULL name\n");
+		return -EINVAL;
+	}
+
+	dev->bus = &auxiliary_bus_type;
+	device_initialize(&auxdev->dev);
+	mutex_init(&auxdev->sysfs.lock);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(auxiliary_device_init);
+
+/**
+ * __auxiliary_device_add - add an auxiliary bus device
+ * @auxdev: auxiliary bus device to add to the bus
+ * @modname: name of the parent device's driver module
+ *
+ * This is the third step in the three-step process to register an
+ * auxiliary_device.
+ *
+ * This function must be called after a successful call to
+ * auxiliary_device_init(), which will perform the device_initialize.  This
+ * means that if this returns an error code, then a call to
+ * auxiliary_device_uninit() must be performed so that the .release callback
+ * will be triggered to free the memory associated with the auxiliary_device.
+ *
+ * The expectation is that users will call the "auxiliary_device_add" macro so
+ * that the caller's KBUILD_MODNAME is automatically inserted for the modname
+ * parameter.  Only if a user requires a custom name would this version be
+ * called directly.
+ */
+int __auxiliary_device_add(struct auxiliary_device *auxdev, const char *modname)
+{
+	struct device *dev = &auxdev->dev;
+	int ret;
+
+	if (!modname) {
+		dev_err(dev, "auxiliary device modname is NULL\n");
+		return -EINVAL;
+	}
+
+	ret = dev_set_name(dev, "%s.%s.%d", modname, auxdev->name, auxdev->id);
+	if (ret) {
+		dev_err(dev, "auxiliary device dev_set_name failed: %d\n", ret);
+		return ret;
+	}
+
+	ret = device_add(dev);
+	if (ret)
+		dev_err(dev, "adding auxiliary device failed!: %d\n", ret);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(__auxiliary_device_add);
+
+/**
+ * __auxiliary_driver_register - register a driver for auxiliary bus devices
+ * @auxdrv: auxiliary_driver structure
+ * @owner: owning module/driver
+ * @modname: KBUILD_MODNAME for parent driver
+ *
+ * The expectation is that users will call the "auxiliary_driver_register"
+ * macro so that the caller's KBUILD_MODNAME is automatically inserted for the
+ * modname parameter.  Only if a user requires a custom name would this version
+ * be called directly.
+ */
+int __auxiliary_driver_register(struct auxiliary_driver *auxdrv,
+				struct module *owner, const char *modname)
+{
+	int ret;
+
+	if (WARN_ON(!auxdrv->probe) || WARN_ON(!auxdrv->id_table))
+		return -EINVAL;
+
+	if (auxdrv->name)
+		auxdrv->driver.name = kasprintf(GFP_KERNEL, "%s.%s", modname,
+						auxdrv->name);
+	else
+		auxdrv->driver.name = kasprintf(GFP_KERNEL, "%s", modname);
+	if (!auxdrv->driver.name)
+		return -ENOMEM;
+
+	auxdrv->driver.owner = owner;
+	auxdrv->driver.bus = &auxiliary_bus_type;
+	auxdrv->driver.mod_name = modname;
+
+	ret = driver_register(&auxdrv->driver);
+	if (ret)
+		kfree(auxdrv->driver.name);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(__auxiliary_driver_register);
+
+/**
+ * auxiliary_driver_unregister - unregister a driver
+ * @auxdrv: auxiliary_driver structure
+ */
+void auxiliary_driver_unregister(struct auxiliary_driver *auxdrv)
+{
+	driver_unregister(&auxdrv->driver);
+	kfree(auxdrv->driver.name);
+}
+EXPORT_SYMBOL_GPL(auxiliary_driver_unregister);
+
+static void auxiliary_device_release(struct device *dev)
+{
+	struct auxiliary_device *auxdev = to_auxiliary_dev(dev);
+
+	of_node_put(dev->of_node);
+	kfree(auxdev);
+}
+
+/**
+ * auxiliary_device_create - create a device on the auxiliary bus
+ * @dev: parent device
+ * @modname: module name used to create the auxiliary driver name.
+ * @devname: auxiliary bus device name
+ * @platform_data: auxiliary bus device platform data
+ * @id: auxiliary bus device id
+ *
+ * Helper to create an auxiliary bus device.
+ * The device created matches driver 'modname.devname' on the auxiliary bus.
+ */
+struct auxiliary_device *auxiliary_device_create(struct device *dev,
+						 const char *modname,
+						 const char *devname,
+						 void *platform_data,
+						 int id)
+{
+	struct auxiliary_device *auxdev;
+	int ret;
+
+	auxdev = kzalloc(sizeof(*auxdev), GFP_KERNEL);
+	if (!auxdev)
+		return NULL;
+
+	auxdev->id = id;
+	auxdev->name = devname;
+	auxdev->dev.parent = dev;
+	auxdev->dev.platform_data = platform_data;
+	auxdev->dev.release = auxiliary_device_release;
+	device_set_of_node_from_dev(&auxdev->dev, dev);
+
+	ret = auxiliary_device_init(auxdev);
+	if (ret) {
+		of_node_put(auxdev->dev.of_node);
+		kfree(auxdev);
+		return NULL;
+	}
+
+	ret = __auxiliary_device_add(auxdev, modname);
+	if (ret) {
+		/*
+		 * It may look odd but auxdev should not be freed here.
+		 * auxiliary_device_uninit() calls device_put() which call
+		 * the device release function, freeing auxdev.
+		 */
+		auxiliary_device_uninit(auxdev);
+		return NULL;
+	}
+
+	return auxdev;
+}
+EXPORT_SYMBOL_GPL(auxiliary_device_create);
+
+/**
+ * auxiliary_device_destroy - remove an auxiliary device
+ * @auxdev: pointer to the auxdev to be removed
+ *
+ * Helper to remove an auxiliary device created with
+ * auxiliary_device_create()
+ */
+void auxiliary_device_destroy(void *auxdev)
+{
+	struct auxiliary_device *_auxdev = auxdev;
+
+	auxiliary_device_delete(_auxdev);
+	auxiliary_device_uninit(_auxdev);
+}
+EXPORT_SYMBOL_GPL(auxiliary_device_destroy);
+
+/**
+ * __devm_auxiliary_device_create - create a managed device on the auxiliary bus
+ * @dev: parent device
+ * @modname: module name used to create the auxiliary driver name.
+ * @devname: auxiliary bus device name
+ * @platform_data: auxiliary bus device platform data
+ * @id: auxiliary bus device id
+ *
+ * Device managed helper to create an auxiliary bus device.
+ * The device created matches driver 'modname.devname' on the auxiliary bus.
+ */
+struct auxiliary_device *__devm_auxiliary_device_create(struct device *dev,
+							const char *modname,
+							const char *devname,
+							void *platform_data,
+							int id)
+{
+	struct auxiliary_device *auxdev;
+	int ret;
+
+	auxdev = auxiliary_device_create(dev, modname, devname, platform_data, id);
+	if (!auxdev)
+		return NULL;
+
+	ret = devm_add_action_or_reset(dev, auxiliary_device_destroy,
+				       auxdev);
+	if (ret)
+		return NULL;
+
+	return auxdev;
+}
+EXPORT_SYMBOL_GPL(__devm_auxiliary_device_create);
+
+void __init auxiliary_bus_init(void)
+{
+	WARN_ON(bus_register(&auxiliary_bus_type));
+}
diff --git a/drivers/base/auxiliary_sysfs.c b/drivers/base/auxiliary_sysfs.c
new file mode 100644
index 000000000000..754f21730afd
--- /dev/null
+++ b/drivers/base/auxiliary_sysfs.c
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES
+ */
+
+#include <linux/auxiliary_bus.h>
+#include <linux/slab.h>
+
+#define AUXILIARY_MAX_IRQ_NAME 11
+
+struct auxiliary_irq_info {
+	struct device_attribute sysfs_attr;
+	char name[AUXILIARY_MAX_IRQ_NAME];
+};
+
+static struct attribute *auxiliary_irq_attrs[] = {
+	NULL
+};
+
+static const struct attribute_group auxiliary_irqs_group = {
+	.name = "irqs",
+	.attrs = auxiliary_irq_attrs,
+};
+
+static int auxiliary_irq_dir_prepare(struct auxiliary_device *auxdev)
+{
+	int ret = 0;
+
+	guard(mutex)(&auxdev->sysfs.lock);
+	if (auxdev->sysfs.irq_dir_exists)
+		return 0;
+
+	ret = devm_device_add_group(&auxdev->dev, &auxiliary_irqs_group);
+	if (ret)
+		return ret;
+
+	auxdev->sysfs.irq_dir_exists = true;
+	xa_init(&auxdev->sysfs.irqs);
+	return 0;
+}
+
+/**
+ * auxiliary_device_sysfs_irq_add - add a sysfs entry for the given IRQ
+ * @auxdev: auxiliary bus device to add the sysfs entry.
+ * @irq: The associated interrupt number.
+ *
+ * This function should be called after auxiliary device have successfully
+ * received the irq.
+ * The driver is responsible to add a unique irq for the auxiliary device. The
+ * driver can invoke this function from multiple thread context safely for
+ * unique irqs of the auxiliary devices. The driver must not invoke this API
+ * multiple times if the irq is already added previously.
+ *
+ * Return: zero on success or an error code on failure.
+ */
+int auxiliary_device_sysfs_irq_add(struct auxiliary_device *auxdev, int irq)
+{
+	struct auxiliary_irq_info *info __free(kfree) = NULL;
+	struct device *dev = &auxdev->dev;
+	int ret;
+
+	ret = auxiliary_irq_dir_prepare(auxdev);
+	if (ret)
+		return ret;
+
+	info = kzalloc(sizeof(*info), GFP_KERNEL);
+	if (!info)
+		return -ENOMEM;
+
+	sysfs_attr_init(&info->sysfs_attr.attr);
+	snprintf(info->name, AUXILIARY_MAX_IRQ_NAME, "%d", irq);
+
+	ret = xa_insert(&auxdev->sysfs.irqs, irq, info, GFP_KERNEL);
+	if (ret)
+		return ret;
+
+	info->sysfs_attr.attr.name = info->name;
+	ret = sysfs_add_file_to_group(&dev->kobj, &info->sysfs_attr.attr,
+				      auxiliary_irqs_group.name);
+	if (ret)
+		goto sysfs_add_err;
+
+	xa_store(&auxdev->sysfs.irqs, irq, no_free_ptr(info), GFP_KERNEL);
+	return 0;
+
+sysfs_add_err:
+	xa_erase(&auxdev->sysfs.irqs, irq);
+	return ret;
+}
+EXPORT_SYMBOL_GPL(auxiliary_device_sysfs_irq_add);
+
+/**
+ * auxiliary_device_sysfs_irq_remove - remove a sysfs entry for the given IRQ
+ * @auxdev: auxiliary bus device to add the sysfs entry.
+ * @irq: the IRQ to remove.
+ *
+ * This function should be called to remove an IRQ sysfs entry.
+ * The driver must invoke this API when IRQ is released by the device.
+ */
+void auxiliary_device_sysfs_irq_remove(struct auxiliary_device *auxdev, int irq)
+{
+	struct auxiliary_irq_info *info __free(kfree) = xa_load(&auxdev->sysfs.irqs, irq);
+	struct device *dev = &auxdev->dev;
+
+	if (!info) {
+		dev_err(&auxdev->dev, "IRQ %d doesn't exist\n", irq);
+		return;
+	}
+	sysfs_remove_file_from_group(&dev->kobj, &info->sysfs_attr.attr,
+				     auxiliary_irqs_group.name);
+	xa_erase(&auxdev->sysfs.irqs, irq);
+}
+EXPORT_SYMBOL_GPL(auxiliary_device_sysfs_irq_remove);
diff --git a/drivers/base/base.h b/drivers/base/base.h
index 40fb069a8a7e..430cbefbc97f 100644
--- a/drivers/base/base.h
+++ b/drivers/base/base.h
@@ -27,11 +27,13 @@
  *                 on this bus.
  * @bus - pointer back to the struct bus_type that this structure is associated
  *        with.
+ * @dev_root: Default device to use as the parent.
  *
  * @glue_dirs - "glue" directory to put in-between the parent device to
  *              avoid namespace conflicts
  * @class - pointer back to the struct class that this structure is associated
  *          with.
+ * @lock_key:	Lock class key for use by the lock validator
  *
  * This structure is the one that is the actual kobject allowing struct
  * bus_type/class to be statically allocated safely.  Nothing outside of the
@@ -48,12 +50,31 @@ struct subsys_private {
 	struct klist klist_drivers;
 	struct blocking_notifier_head bus_notifier;
 	unsigned int drivers_autoprobe:1;
-	struct bus_type *bus;
+	const struct bus_type *bus;
+	struct device *dev_root;
 
 	struct kset glue_dirs;
-	struct class *class;
+	const struct class *class;
+
+	struct lock_class_key lock_key;
 };
-#define to_subsys_private(obj) container_of(obj, struct subsys_private, subsys.kobj)
+#define to_subsys_private(obj) container_of_const(obj, struct subsys_private, subsys.kobj)
+
+static inline struct subsys_private *subsys_get(struct subsys_private *sp)
+{
+	if (sp)
+		kset_get(&sp->subsys);
+	return sp;
+}
+
+static inline void subsys_put(struct subsys_private *sp)
+{
+	if (sp)
+		kset_put(&sp->subsys);
+}
+
+struct subsys_private *bus_to_subsys(const struct bus_type *bus);
+struct subsys_private *class_to_subsys(const struct class *class);
 
 struct driver_private {
 	struct kobject kobj;
@@ -64,6 +85,18 @@ struct driver_private {
 };
 #define to_driver(obj) container_of(obj, struct driver_private, kobj)
 
+#ifdef CONFIG_RUST
+/**
+ * struct driver_type - Representation of a Rust driver type.
+ */
+struct driver_type {
+	/**
+	 * @id: Representation of core::any::TypeId.
+	 */
+	u8 id[16];
+} __packed;
+#endif
+
 /**
  * struct device_private - structure to hold the private to the driver core portions of the device structure.
  *
@@ -79,6 +112,7 @@ struct driver_private {
  * @async_driver - pointer to device driver awaiting probe via async_probe
  * @device - pointer back to the struct device that this structure is
  * associated with.
+ * @driver_type - The type of the bound Rust driver.
  * @dead - This device is currently either in the process of or has been
  *	removed from the system. Any asynchronous events scheduled for this
  *	device should exit without taking any action.
@@ -92,8 +126,12 @@ struct device_private {
 	struct klist_node knode_bus;
 	struct klist_node knode_class;
 	struct list_head deferred_probe;
-	struct device_driver *async_driver;
+	const struct device_driver *async_driver;
+	char *deferred_probe_reason;
 	struct device *device;
+#ifdef CONFIG_RUST
+	struct driver_type driver_type;
+#endif
 	u8 dead:1;
 };
 #define to_device_private_parent(obj)	\
@@ -106,83 +144,137 @@ struct device_private {
 	container_of(obj, struct device_private, knode_class)
 
 /* initialisation functions */
-extern int devices_init(void);
-extern int buses_init(void);
-extern int classes_init(void);
-extern int firmware_init(void);
+int devices_init(void);
+int buses_init(void);
+int classes_init(void);
+int firmware_init(void);
 #ifdef CONFIG_SYS_HYPERVISOR
-extern int hypervisor_init(void);
+int hypervisor_init(void);
 #else
 static inline int hypervisor_init(void) { return 0; }
 #endif
-extern int platform_bus_init(void);
-extern void cpu_dev_init(void);
-extern void container_dev_init(void);
-
-struct kobject *virtual_device_parent(struct device *dev);
-
-extern int bus_add_device(struct device *dev);
-extern void bus_probe_device(struct device *dev);
-extern void bus_remove_device(struct device *dev);
-
-extern int bus_add_driver(struct device_driver *drv);
-extern void bus_remove_driver(struct device_driver *drv);
-extern void device_release_driver_internal(struct device *dev,
-					   struct device_driver *drv,
-					   struct device *parent);
-
-extern void driver_detach(struct device_driver *drv);
-extern int driver_probe_device(struct device_driver *drv, struct device *dev);
-extern void driver_deferred_probe_del(struct device *dev);
-static inline int driver_match_device(struct device_driver *drv,
+int platform_bus_init(void);
+int faux_bus_init(void);
+void cpu_dev_init(void);
+void container_dev_init(void);
+#ifdef CONFIG_AUXILIARY_BUS
+void auxiliary_bus_init(void);
+#else
+static inline void auxiliary_bus_init(void) { }
+#endif
+
+struct kobject *virtual_device_parent(void);
+
+int bus_add_device(struct device *dev);
+void bus_probe_device(struct device *dev);
+void bus_remove_device(struct device *dev);
+void bus_notify(struct device *dev, enum bus_notifier_event value);
+bool bus_is_registered(const struct bus_type *bus);
+
+int bus_add_driver(struct device_driver *drv);
+void bus_remove_driver(struct device_driver *drv);
+void device_release_driver_internal(struct device *dev, const struct device_driver *drv,
+				    struct device *parent);
+
+void driver_detach(const struct device_driver *drv);
+void driver_deferred_probe_del(struct device *dev);
+void device_set_deferred_probe_reason(const struct device *dev, struct va_format *vaf);
+static inline int driver_match_device(const struct device_driver *drv,
 				      struct device *dev)
 {
 	return drv->bus->match ? drv->bus->match(dev, drv) : 1;
 }
-extern bool driver_allows_async_probing(struct device_driver *drv);
 
-extern int driver_add_groups(struct device_driver *drv,
-			     const struct attribute_group **groups);
-extern void driver_remove_groups(struct device_driver *drv,
-				 const struct attribute_group **groups);
-int device_driver_attach(struct device_driver *drv, struct device *dev);
+static inline void dev_sync_state(struct device *dev)
+{
+	if (dev->bus->sync_state)
+		dev->bus->sync_state(dev);
+	else if (dev->driver && dev->driver->sync_state)
+		dev->driver->sync_state(dev);
+}
+
+int driver_add_groups(const struct device_driver *drv, const struct attribute_group **groups);
+void driver_remove_groups(const struct device_driver *drv, const struct attribute_group **groups);
 void device_driver_detach(struct device *dev);
 
-extern char *make_class_name(const char *name, struct kobject *kobj);
+static inline void device_set_driver(struct device *dev, const struct device_driver *drv)
+{
+	/*
+	 * Majority (all?) read accesses to dev->driver happens either
+	 * while holding device lock or in bus/driver code that is only
+	 * invoked when the device is bound to a driver and there is no
+	 * concern of the pointer being changed while it is being read.
+	 * However when reading device's uevent file we read driver pointer
+	 * without taking device lock (so we do not block there for
+	 * arbitrary amount of time). We use WRITE_ONCE() here to prevent
+	 * tearing so that READ_ONCE() can safely be used in uevent code.
+	 */
+	// FIXME - this cast should not be needed "soon"
+	WRITE_ONCE(dev->driver, (struct device_driver *)drv);
+}
 
-extern int devres_release_all(struct device *dev);
-extern void device_block_probing(void);
-extern void device_unblock_probing(void);
+int devres_release_all(struct device *dev);
+void device_block_probing(void);
+void device_unblock_probing(void);
+void deferred_probe_extend_timeout(void);
+void driver_deferred_probe_trigger(void);
+const char *device_get_devnode(const struct device *dev, umode_t *mode,
+			       kuid_t *uid, kgid_t *gid, const char **tmp);
 
 /* /sys/devices directory */
 extern struct kset *devices_kset;
-extern void devices_kset_move_last(struct device *dev);
+void devices_kset_move_last(struct device *dev);
 
 #if defined(CONFIG_MODULES) && defined(CONFIG_SYSFS)
-extern void module_add_driver(struct module *mod, struct device_driver *drv);
-extern void module_remove_driver(struct device_driver *drv);
+int module_add_driver(struct module *mod, const struct device_driver *drv);
+void module_remove_driver(const struct device_driver *drv);
 #else
-static inline void module_add_driver(struct module *mod,
-				     struct device_driver *drv) { }
+static inline int module_add_driver(struct module *mod,
+				    struct device_driver *drv)
+{
+	return 0;
+}
 static inline void module_remove_driver(struct device_driver *drv) { }
 #endif
 
 #ifdef CONFIG_DEVTMPFS
-extern int devtmpfs_init(void);
+int devtmpfs_init(void);
 #else
 static inline int devtmpfs_init(void) { return 0; }
 #endif
 
+#ifdef CONFIG_BLOCK
+extern const struct class block_class;
+static inline bool is_blockdev(struct device *dev)
+{
+	return dev->class == &block_class;
+}
+#else
+static inline bool is_blockdev(struct device *dev) { return false; }
+#endif
+
 /* Device links support */
-extern int device_links_read_lock(void);
-extern void device_links_read_unlock(int idx);
-extern int device_links_read_lock_held(void);
-extern int device_links_check_suppliers(struct device *dev);
-extern void device_links_driver_bound(struct device *dev);
-extern void device_links_driver_cleanup(struct device *dev);
-extern void device_links_no_driver(struct device *dev);
-extern bool device_links_busy(struct device *dev);
-extern void device_links_unbind_consumers(struct device *dev);
+int device_links_read_lock(void);
+void device_links_read_unlock(int idx);
+int device_links_read_lock_held(void);
+int device_links_check_suppliers(struct device *dev);
+void device_links_force_bind(struct device *dev);
+void device_links_driver_bound(struct device *dev);
+void device_links_driver_cleanup(struct device *dev);
+void device_links_no_driver(struct device *dev);
+bool device_links_busy(struct device *dev);
+void device_links_unbind_consumers(struct device *dev);
+bool device_link_flag_is_sync_state_only(u32 flags);
+void fw_devlink_drivers_done(void);
+void fw_devlink_probing_done(void);
+
+#define dev_for_each_link_to_supplier(__link, __dev)	\
+	list_for_each_entry_srcu(__link, &(__dev)->links.suppliers, c_node, \
+				 device_links_read_lock_held())
+
+#define dev_for_each_link_to_consumer(__link, __dev)	\
+	list_for_each_entry_srcu(__link, &(__dev)->links.consumers, s_node, \
+				 device_links_read_lock_held())
 
 /* device pm support */
 void device_pm_move_to_tail(struct device *dev);
@@ -194,3 +286,6 @@ int devtmpfs_delete_node(struct device *dev);
 static inline int devtmpfs_create_node(struct device *dev) { return 0; }
 static inline int devtmpfs_delete_node(struct device *dev) { return 0; }
 #endif
+
+void software_node_notify(struct device *dev);
+void software_node_notify_remove(struct device *dev);
diff --git a/drivers/base/bus.c b/drivers/base/bus.c
index 886e9054999a..9eb7771706f0 100644
--- a/drivers/base/bus.c
+++ b/drivers/base/bus.c
@@ -6,6 +6,7 @@
  * Copyright (c) 2002-3 Open Source Development Labs
  * Copyright (c) 2007 Greg Kroah-Hartman <gregkh@suse.de>
  * Copyright (c) 2007 Novell Inc.
+ * Copyright (c) 2023 Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  */
 
 #include <linux/async.h>
@@ -24,6 +25,9 @@
 /* /sys/devices/system */
 static struct kset *system_kset;
 
+/* /sys/bus */
+static struct kset *bus_kset;
+
 #define to_bus_attr(_attr) container_of(_attr, struct bus_attribute, attr)
 
 /*
@@ -39,19 +43,63 @@ static struct kset *system_kset;
 static int __must_check bus_rescan_devices_helper(struct device *dev,
 						void *data);
 
-static struct bus_type *bus_get(struct bus_type *bus)
+/**
+ * bus_to_subsys - Turn a struct bus_type into a struct subsys_private
+ *
+ * @bus: pointer to the struct bus_type to look up
+ *
+ * The driver core internals needs to work on the subsys_private structure, not
+ * the external struct bus_type pointer.  This function walks the list of
+ * registered busses in the system and finds the matching one and returns the
+ * internal struct subsys_private that relates to that bus.
+ *
+ * Note, the reference count of the return value is INCREMENTED if it is not
+ * NULL.  A call to subsys_put() must be done when finished with the pointer in
+ * order for it to be properly freed.
+ */
+struct subsys_private *bus_to_subsys(const struct bus_type *bus)
 {
-	if (bus) {
-		kset_get(&bus->p->subsys);
-		return bus;
+	struct subsys_private *sp = NULL;
+	struct kobject *kobj;
+
+	if (!bus || !bus_kset)
+		return NULL;
+
+	spin_lock(&bus_kset->list_lock);
+
+	if (list_empty(&bus_kset->list))
+		goto done;
+
+	list_for_each_entry(kobj, &bus_kset->list, entry) {
+		struct kset *kset = container_of(kobj, struct kset, kobj);
+
+		sp = container_of_const(kset, struct subsys_private, subsys);
+		if (sp->bus == bus)
+			goto done;
 	}
+	sp = NULL;
+done:
+	sp = subsys_get(sp);
+	spin_unlock(&bus_kset->list_lock);
+	return sp;
+}
+
+static const struct bus_type *bus_get(const struct bus_type *bus)
+{
+	struct subsys_private *sp = bus_to_subsys(bus);
+
+	if (sp)
+		return bus;
 	return NULL;
 }
 
-static void bus_put(struct bus_type *bus)
+static void bus_put(const struct bus_type *bus)
 {
-	if (bus)
-		kset_put(&bus->p->subsys);
+	struct subsys_private *sp = bus_to_subsys(bus);
+
+	/* two puts are required as the call to bus_to_subsys incremented it again */
+	subsys_put(sp);
+	subsys_put(sp);
 }
 
 static ssize_t drv_attr_show(struct kobject *kobj, struct attribute *attr,
@@ -91,7 +139,7 @@ static void driver_release(struct kobject *kobj)
 	kfree(drv_priv);
 }
 
-static struct kobj_type driver_ktype = {
+static const struct kobj_type driver_ktype = {
 	.sysfs_ops	= &driver_sysfs_ops,
 	.release	= driver_release,
 };
@@ -104,7 +152,8 @@ static ssize_t bus_attr_show(struct kobject *kobj, struct attribute *attr,
 {
 	struct bus_attribute *bus_attr = to_bus_attr(attr);
 	struct subsys_private *subsys_priv = to_subsys_private(kobj);
-	ssize_t ret = 0;
+	/* return -EIO for reading a bus attribute without show() */
+	ssize_t ret = -EIO;
 
 	if (bus_attr->show)
 		ret = bus_attr->show(subsys_priv->bus, buf);
@@ -116,7 +165,8 @@ static ssize_t bus_attr_store(struct kobject *kobj, struct attribute *attr,
 {
 	struct bus_attribute *bus_attr = to_bus_attr(attr);
 	struct subsys_private *subsys_priv = to_subsys_private(kobj);
-	ssize_t ret = 0;
+	/* return -EIO for writing a bus attribute without store() */
+	ssize_t ret = -EIO;
 
 	if (bus_attr->store)
 		ret = bus_attr->store(subsys_priv->bus, buf, count);
@@ -128,44 +178,49 @@ static const struct sysfs_ops bus_sysfs_ops = {
 	.store	= bus_attr_store,
 };
 
-int bus_create_file(struct bus_type *bus, struct bus_attribute *attr)
+int bus_create_file(const struct bus_type *bus, struct bus_attribute *attr)
 {
+	struct subsys_private *sp = bus_to_subsys(bus);
 	int error;
-	if (bus_get(bus)) {
-		error = sysfs_create_file(&bus->p->subsys.kobj, &attr->attr);
-		bus_put(bus);
-	} else
-		error = -EINVAL;
+
+	if (!sp)
+		return -EINVAL;
+
+	error = sysfs_create_file(&sp->subsys.kobj, &attr->attr);
+
+	subsys_put(sp);
 	return error;
 }
 EXPORT_SYMBOL_GPL(bus_create_file);
 
-void bus_remove_file(struct bus_type *bus, struct bus_attribute *attr)
+void bus_remove_file(const struct bus_type *bus, struct bus_attribute *attr)
 {
-	if (bus_get(bus)) {
-		sysfs_remove_file(&bus->p->subsys.kobj, &attr->attr);
-		bus_put(bus);
-	}
+	struct subsys_private *sp = bus_to_subsys(bus);
+
+	if (!sp)
+		return;
+
+	sysfs_remove_file(&sp->subsys.kobj, &attr->attr);
+	subsys_put(sp);
 }
 EXPORT_SYMBOL_GPL(bus_remove_file);
 
 static void bus_release(struct kobject *kobj)
 {
 	struct subsys_private *priv = to_subsys_private(kobj);
-	struct bus_type *bus = priv->bus;
 
+	lockdep_unregister_key(&priv->lock_key);
 	kfree(priv);
-	bus->p = NULL;
 }
 
-static struct kobj_type bus_ktype = {
+static const struct kobj_type bus_ktype = {
 	.sysfs_ops	= &bus_sysfs_ops,
 	.release	= bus_release,
 };
 
-static int bus_uevent_filter(struct kset *kset, struct kobject *kobj)
+static int bus_uevent_filter(const struct kobject *kobj)
 {
-	struct kobj_type *ktype = get_ktype(kobj);
+	const struct kobj_type *ktype = get_ktype(kobj);
 
 	if (ktype == &bus_ktype)
 		return 1;
@@ -176,13 +231,11 @@ static const struct kset_uevent_ops bus_uevent_ops = {
 	.filter = bus_uevent_filter,
 };
 
-static struct kset *bus_kset;
-
 /* Manually detach a device from its associated driver. */
 static ssize_t unbind_store(struct device_driver *drv, const char *buf,
 			    size_t count)
 {
-	struct bus_type *bus = bus_get(drv->bus);
+	const struct bus_type *bus = bus_get(drv->bus);
 	struct device *dev;
 	int err = -ENODEV;
 
@@ -195,7 +248,7 @@ static ssize_t unbind_store(struct device_driver *drv, const char *buf,
 	bus_put(bus);
 	return err;
 }
-static DRIVER_ATTR_IGNORE_LOCKDEP(unbind, S_IWUSR, NULL, unbind_store);
+static DRIVER_ATTR_IGNORE_LOCKDEP(unbind, 0200, NULL, unbind_store);
 
 /*
  * Manually attach a device to a driver.
@@ -205,44 +258,55 @@ static DRIVER_ATTR_IGNORE_LOCKDEP(unbind, S_IWUSR, NULL, unbind_store);
 static ssize_t bind_store(struct device_driver *drv, const char *buf,
 			  size_t count)
 {
-	struct bus_type *bus = bus_get(drv->bus);
+	const struct bus_type *bus = bus_get(drv->bus);
 	struct device *dev;
 	int err = -ENODEV;
 
 	dev = bus_find_device_by_name(bus, NULL, buf);
-	if (dev && dev->driver == NULL && driver_match_device(drv, dev)) {
+	if (dev && driver_match_device(drv, dev)) {
 		err = device_driver_attach(drv, dev);
-
-		if (err > 0) {
+		if (!err) {
 			/* success */
 			err = count;
-		} else if (err == 0) {
-			/* driver didn't accept device */
-			err = -ENODEV;
 		}
 	}
 	put_device(dev);
 	bus_put(bus);
 	return err;
 }
-static DRIVER_ATTR_IGNORE_LOCKDEP(bind, S_IWUSR, NULL, bind_store);
+static DRIVER_ATTR_IGNORE_LOCKDEP(bind, 0200, NULL, bind_store);
 
-static ssize_t drivers_autoprobe_show(struct bus_type *bus, char *buf)
+static ssize_t drivers_autoprobe_show(const struct bus_type *bus, char *buf)
 {
-	return sprintf(buf, "%d\n", bus->p->drivers_autoprobe);
+	struct subsys_private *sp = bus_to_subsys(bus);
+	int ret;
+
+	if (!sp)
+		return -EINVAL;
+
+	ret = sysfs_emit(buf, "%d\n", sp->drivers_autoprobe);
+	subsys_put(sp);
+	return ret;
 }
 
-static ssize_t drivers_autoprobe_store(struct bus_type *bus,
+static ssize_t drivers_autoprobe_store(const struct bus_type *bus,
 				       const char *buf, size_t count)
 {
+	struct subsys_private *sp = bus_to_subsys(bus);
+
+	if (!sp)
+		return -EINVAL;
+
 	if (buf[0] == '0')
-		bus->p->drivers_autoprobe = 0;
+		sp->drivers_autoprobe = 0;
 	else
-		bus->p->drivers_autoprobe = 1;
+		sp->drivers_autoprobe = 1;
+
+	subsys_put(sp);
 	return count;
 }
 
-static ssize_t drivers_probe_store(struct bus_type *bus,
+static ssize_t drivers_probe_store(const struct bus_type *bus,
 				   const char *buf, size_t count)
 {
 	struct device *dev;
@@ -270,6 +334,19 @@ static struct device *next_device(struct klist_iter *i)
 	return dev;
 }
 
+static struct device *prev_device(struct klist_iter *i)
+{
+	struct klist_node *n = klist_prev(i);
+	struct device *dev = NULL;
+	struct device_private *dev_prv;
+
+	if (n) {
+		dev_prv = to_device_private_bus(n);
+		dev = dev_prv->device;
+	}
+	return dev;
+}
+
 /**
  * bus_for_each_dev - device iterator.
  * @bus: bus type.
@@ -289,21 +366,23 @@ static struct device *next_device(struct klist_iter *i)
  * to retain this data, it should do so, and increment the reference
  * count in the supplied callback.
  */
-int bus_for_each_dev(struct bus_type *bus, struct device *start,
-		     void *data, int (*fn)(struct device *, void *))
+int bus_for_each_dev(const struct bus_type *bus, struct device *start,
+		     void *data, device_iter_t fn)
 {
+	struct subsys_private *sp = bus_to_subsys(bus);
 	struct klist_iter i;
 	struct device *dev;
 	int error = 0;
 
-	if (!bus || !bus->p)
+	if (!sp)
 		return -EINVAL;
 
-	klist_iter_init_node(&bus->p->klist_devices, &i,
+	klist_iter_init_node(&sp->klist_devices, &i,
 			     (start ? &start->p->knode_bus : NULL));
 	while (!error && (dev = next_device(&i)))
 		error = fn(dev, data);
 	klist_iter_exit(&i);
+	subsys_put(sp);
 	return error;
 }
 EXPORT_SYMBOL_GPL(bus_for_each_dev);
@@ -323,66 +402,55 @@ EXPORT_SYMBOL_GPL(bus_for_each_dev);
  * if it does.  If the callback returns non-zero, this function will
  * return to the caller and not iterate over any more devices.
  */
-struct device *bus_find_device(struct bus_type *bus,
+struct device *bus_find_device(const struct bus_type *bus,
 			       struct device *start, const void *data,
-			       int (*match)(struct device *dev, const void *data))
+			       device_match_t match)
 {
+	struct subsys_private *sp = bus_to_subsys(bus);
 	struct klist_iter i;
 	struct device *dev;
 
-	if (!bus || !bus->p)
+	if (!sp)
 		return NULL;
 
-	klist_iter_init_node(&bus->p->klist_devices, &i,
+	klist_iter_init_node(&sp->klist_devices, &i,
 			     (start ? &start->p->knode_bus : NULL));
-	while ((dev = next_device(&i)))
-		if (match(dev, data) && get_device(dev))
+	while ((dev = next_device(&i))) {
+		if (match(dev, data)) {
+			get_device(dev);
 			break;
+		}
+	}
 	klist_iter_exit(&i);
+	subsys_put(sp);
 	return dev;
 }
 EXPORT_SYMBOL_GPL(bus_find_device);
 
-/**
- * subsys_find_device_by_id - find a device with a specific enumeration number
- * @subsys: subsystem
- * @id: index 'id' in struct device
- * @hint: device to check first
- *
- * Check the hint's next object and if it is a match return it directly,
- * otherwise, fall back to a full list search. Either way a reference for
- * the returned object is taken.
- */
-struct device *subsys_find_device_by_id(struct bus_type *subsys, unsigned int id,
-					struct device *hint)
+struct device *bus_find_device_reverse(const struct bus_type *bus,
+				       struct device *start, const void *data,
+				       device_match_t match)
 {
+	struct subsys_private *sp = bus_to_subsys(bus);
 	struct klist_iter i;
 	struct device *dev;
 
-	if (!subsys)
+	if (!sp)
 		return NULL;
 
-	if (hint) {
-		klist_iter_init_node(&subsys->p->klist_devices, &i, &hint->p->knode_bus);
-		dev = next_device(&i);
-		if (dev && dev->id == id && get_device(dev)) {
-			klist_iter_exit(&i);
-			return dev;
-		}
-		klist_iter_exit(&i);
-	}
-
-	klist_iter_init_node(&subsys->p->klist_devices, &i, NULL);
-	while ((dev = next_device(&i))) {
-		if (dev->id == id && get_device(dev)) {
-			klist_iter_exit(&i);
-			return dev;
+	klist_iter_init_node(&sp->klist_devices, &i,
+			     (start ? &start->p->knode_bus : NULL));
+	while ((dev = prev_device(&i))) {
+		if (match(dev, data)) {
+			get_device(dev);
+			break;
 		}
 	}
 	klist_iter_exit(&i);
-	return NULL;
+	subsys_put(sp);
+	return dev;
 }
-EXPORT_SYMBOL_GPL(subsys_find_device_by_id);
+EXPORT_SYMBOL_GPL(bus_find_device_reverse);
 
 static struct device_driver *next_driver(struct klist_iter *i)
 {
@@ -415,21 +483,23 @@ static struct device_driver *next_driver(struct klist_iter *i)
  * in the callback. It must also be sure to increment the refcount
  * so it doesn't disappear before returning to the caller.
  */
-int bus_for_each_drv(struct bus_type *bus, struct device_driver *start,
+int bus_for_each_drv(const struct bus_type *bus, struct device_driver *start,
 		     void *data, int (*fn)(struct device_driver *, void *))
 {
+	struct subsys_private *sp = bus_to_subsys(bus);
 	struct klist_iter i;
 	struct device_driver *drv;
 	int error = 0;
 
-	if (!bus)
+	if (!sp)
 		return -EINVAL;
 
-	klist_iter_init_node(&bus->p->klist_drivers, &i,
+	klist_iter_init_node(&sp->klist_drivers, &i,
 			     start ? &start->p->knode_bus : NULL);
 	while ((drv = next_driver(&i)) && !error)
 		error = fn(drv, data);
 	klist_iter_exit(&i);
+	subsys_put(sp);
 	return error;
 }
 EXPORT_SYMBOL_GPL(bus_for_each_drv);
@@ -444,32 +514,46 @@ EXPORT_SYMBOL_GPL(bus_for_each_drv);
  */
 int bus_add_device(struct device *dev)
 {
-	struct bus_type *bus = bus_get(dev->bus);
-	int error = 0;
+	struct subsys_private *sp = bus_to_subsys(dev->bus);
+	int error;
 
-	if (bus) {
-		pr_debug("bus: '%s': add device %s\n", bus->name, dev_name(dev));
-		error = device_add_groups(dev, bus->dev_groups);
-		if (error)
-			goto out_put;
-		error = sysfs_create_link(&bus->p->devices_kset->kobj,
-						&dev->kobj, dev_name(dev));
-		if (error)
-			goto out_groups;
-		error = sysfs_create_link(&dev->kobj,
-				&dev->bus->p->subsys.kobj, "subsystem");
-		if (error)
-			goto out_subsys;
-		klist_add_tail(&dev->p->knode_bus, &bus->p->klist_devices);
+	if (!sp) {
+		/*
+		 * This is a normal operation for many devices that do not
+		 * have a bus assigned to them, just say that all went
+		 * well.
+		 */
+		return 0;
 	}
+
+	/*
+	 * Reference in sp is now incremented and will be dropped when
+	 * the device is removed from the bus
+	 */
+
+	pr_debug("bus: '%s': add device %s\n", sp->bus->name, dev_name(dev));
+
+	error = device_add_groups(dev, sp->bus->dev_groups);
+	if (error)
+		goto out_put;
+
+	error = sysfs_create_link(&sp->devices_kset->kobj, &dev->kobj, dev_name(dev));
+	if (error)
+		goto out_groups;
+
+	error = sysfs_create_link(&dev->kobj, &sp->subsys.kobj, "subsystem");
+	if (error)
+		goto out_subsys;
+
+	klist_add_tail(&dev->p->knode_bus, &sp->klist_devices);
 	return 0;
 
 out_subsys:
-	sysfs_remove_link(&bus->p->devices_kset->kobj, dev_name(dev));
+	sysfs_remove_link(&sp->devices_kset->kobj, dev_name(dev));
 out_groups:
-	device_remove_groups(dev, bus->dev_groups);
+	device_remove_groups(dev, sp->bus->dev_groups);
 out_put:
-	bus_put(dev->bus);
+	subsys_put(sp);
 	return error;
 }
 
@@ -481,20 +565,20 @@ out_put:
  */
 void bus_probe_device(struct device *dev)
 {
-	struct bus_type *bus = dev->bus;
+	struct subsys_private *sp = bus_to_subsys(dev->bus);
 	struct subsys_interface *sif;
 
-	if (!bus)
+	if (!sp)
 		return;
 
-	if (bus->p->drivers_autoprobe)
-		device_initial_probe(dev);
+	device_initial_probe(dev);
 
-	mutex_lock(&bus->p->mutex);
-	list_for_each_entry(sif, &bus->p->interfaces, node)
+	mutex_lock(&sp->mutex);
+	list_for_each_entry(sif, &sp->interfaces, node)
 		if (sif->add_dev)
 			sif->add_dev(dev, sif);
-	mutex_unlock(&bus->p->mutex);
+	mutex_unlock(&sp->mutex);
+	subsys_put(sp);
 }
 
 /**
@@ -509,21 +593,20 @@ void bus_probe_device(struct device *dev)
  */
 void bus_remove_device(struct device *dev)
 {
-	struct bus_type *bus = dev->bus;
+	struct subsys_private *sp = bus_to_subsys(dev->bus);
 	struct subsys_interface *sif;
 
-	if (!bus)
+	if (!sp)
 		return;
 
-	mutex_lock(&bus->p->mutex);
-	list_for_each_entry(sif, &bus->p->interfaces, node)
+	mutex_lock(&sp->mutex);
+	list_for_each_entry(sif, &sp->interfaces, node)
 		if (sif->remove_dev)
 			sif->remove_dev(dev, sif);
-	mutex_unlock(&bus->p->mutex);
+	mutex_unlock(&sp->mutex);
 
 	sysfs_remove_link(&dev->kobj, "subsystem");
-	sysfs_remove_link(&dev->bus->p->devices_kset->kobj,
-			  dev_name(dev));
+	sysfs_remove_link(&sp->devices_kset->kobj, dev_name(dev));
 	device_remove_groups(dev, dev->bus->dev_groups);
 	if (klist_node_attached(&dev->p->knode_bus))
 		klist_del(&dev->p->knode_bus);
@@ -531,7 +614,14 @@ void bus_remove_device(struct device *dev)
 	pr_debug("bus: '%s': remove device %s\n",
 		 dev->bus->name, dev_name(dev));
 	device_release_driver(dev);
-	bus_put(dev->bus);
+
+	/*
+	 * Decrement the reference count twice, once for the bus_to_subsys()
+	 * call in the start of this function, and the second one from the
+	 * reference increment in bus_add_device()
+	 */
+	subsys_put(sp);
+	subsys_put(sp);
 }
 
 static int __must_check add_bind_files(struct device_driver *drv)
@@ -556,7 +646,7 @@ static void remove_bind_files(struct device_driver *drv)
 static BUS_ATTR_WO(drivers_probe);
 static BUS_ATTR_RW(drivers_autoprobe);
 
-static int add_probe_files(struct bus_type *bus)
+static int add_probe_files(const struct bus_type *bus)
 {
 	int retval;
 
@@ -571,7 +661,7 @@ out:
 	return retval;
 }
 
-static void remove_probe_files(struct bus_type *bus)
+static void remove_probe_files(const struct bus_type *bus)
 {
 	bus_remove_file(bus, &bus_attr_drivers_autoprobe);
 	bus_remove_file(bus, &bus_attr_drivers_probe);
@@ -593,15 +683,18 @@ static DRIVER_ATTR_WO(uevent);
  */
 int bus_add_driver(struct device_driver *drv)
 {
-	struct bus_type *bus;
+	struct subsys_private *sp = bus_to_subsys(drv->bus);
 	struct driver_private *priv;
 	int error = 0;
 
-	bus = bus_get(drv->bus);
-	if (!bus)
+	if (!sp)
 		return -EINVAL;
 
-	pr_debug("bus: '%s': add driver %s\n", bus->name, drv->name);
+	/*
+	 * Reference in sp is now incremented and will be dropped when
+	 * the driver is removed from the bus
+	 */
+	pr_debug("bus: '%s': add driver %s\n", sp->bus->name, drv->name);
 
 	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 	if (!priv) {
@@ -611,29 +704,34 @@ int bus_add_driver(struct device_driver *drv)
 	klist_init(&priv->klist_devices, NULL, NULL);
 	priv->driver = drv;
 	drv->p = priv;
-	priv->kobj.kset = bus->p->drivers_kset;
+	priv->kobj.kset = sp->drivers_kset;
 	error = kobject_init_and_add(&priv->kobj, &driver_ktype, NULL,
 				     "%s", drv->name);
 	if (error)
 		goto out_unregister;
 
-	klist_add_tail(&priv->knode_bus, &bus->p->klist_drivers);
-	if (drv->bus->p->drivers_autoprobe) {
+	klist_add_tail(&priv->knode_bus, &sp->klist_drivers);
+	if (sp->drivers_autoprobe) {
 		error = driver_attach(drv);
 		if (error)
-			goto out_unregister;
+			goto out_del_list;
+	}
+	error = module_add_driver(drv->owner, drv);
+	if (error) {
+		printk(KERN_ERR "%s: failed to create module links for %s\n",
+			__func__, drv->name);
+		goto out_detach;
 	}
-	module_add_driver(drv->owner, drv);
 
 	error = driver_create_file(drv, &driver_attr_uevent);
 	if (error) {
 		printk(KERN_ERR "%s: uevent attr (%s) failed\n",
 			__func__, drv->name);
 	}
-	error = driver_add_groups(drv, bus->drv_groups);
+	error = driver_add_groups(drv, sp->bus->drv_groups);
 	if (error) {
 		/* How the hell do we get out of this pickle? Give up */
-		printk(KERN_ERR "%s: driver_create_groups(%s) failed\n",
+		printk(KERN_ERR "%s: driver_add_groups(%s) failed\n",
 			__func__, drv->name);
 	}
 
@@ -648,12 +746,16 @@ int bus_add_driver(struct device_driver *drv)
 
 	return 0;
 
+out_detach:
+	driver_detach(drv);
+out_del_list:
+	klist_del(&priv->knode_bus);
 out_unregister:
 	kobject_put(&priv->kobj);
 	/* drv->p is freed in driver_release()  */
 	drv->p = NULL;
 out_put_bus:
-	bus_put(bus);
+	subsys_put(sp);
 	return error;
 }
 
@@ -667,19 +769,29 @@ out_put_bus:
  */
 void bus_remove_driver(struct device_driver *drv)
 {
-	if (!drv->bus)
+	struct subsys_private *sp = bus_to_subsys(drv->bus);
+
+	if (!sp)
 		return;
 
+	pr_debug("bus: '%s': remove driver %s\n", sp->bus->name, drv->name);
+
 	if (!drv->suppress_bind_attrs)
 		remove_bind_files(drv);
-	driver_remove_groups(drv, drv->bus->drv_groups);
+	driver_remove_groups(drv, sp->bus->drv_groups);
 	driver_remove_file(drv, &driver_attr_uevent);
 	klist_remove(&drv->p->knode_bus);
-	pr_debug("bus: '%s': remove driver %s\n", drv->bus->name, drv->name);
 	driver_detach(drv);
 	module_remove_driver(drv);
 	kobject_put(&drv->p->kobj);
-	bus_put(drv->bus);
+
+	/*
+	 * Decrement the reference count twice, once for the bus_to_subsys()
+	 * call in the start of this function, and the second one from the
+	 * reference increment in bus_add_driver()
+	 */
+	subsys_put(sp);
+	subsys_put(sp);
 }
 
 /* Helper for bus_rescan_devices's iter */
@@ -706,7 +818,7 @@ static int __must_check bus_rescan_devices_helper(struct device *dev,
  * attached and rescan it against existing drivers to see if it matches
  * any by calling device_attach() for the unbound devices.
  */
-int bus_rescan_devices(struct bus_type *bus)
+int bus_rescan_devices(const struct bus_type *bus)
 {
 	return bus_for_each_dev(bus, NULL, NULL, bus_rescan_devices_helper);
 }
@@ -729,35 +841,6 @@ int device_reprobe(struct device *dev)
 }
 EXPORT_SYMBOL_GPL(device_reprobe);
 
-/**
- * find_bus - locate bus by name.
- * @name: name of bus.
- *
- * Call kset_find_obj() to iterate over list of buses to
- * find a bus by name. Return bus if found.
- *
- * Note that kset_find_obj increments bus' reference count.
- */
-#if 0
-struct bus_type *find_bus(char *name)
-{
-	struct kobject *k = kset_find_obj(bus_kset, name);
-	return k ? to_bus(k) : NULL;
-}
-#endif  /*  0  */
-
-static int bus_add_groups(struct bus_type *bus,
-			  const struct attribute_group **groups)
-{
-	return sysfs_create_groups(&bus->p->subsys.kobj, groups);
-}
-
-static void bus_remove_groups(struct bus_type *bus,
-			      const struct attribute_group **groups)
-{
-	sysfs_remove_groups(&bus->p->subsys.kobj, groups);
-}
-
 static void klist_devices_get(struct klist_node *n)
 {
 	struct device_private *dev_prv = to_device_private_bus(n);
@@ -774,13 +857,21 @@ static void klist_devices_put(struct klist_node *n)
 	put_device(dev);
 }
 
-static ssize_t bus_uevent_store(struct bus_type *bus,
+static ssize_t bus_uevent_store(const struct bus_type *bus,
 				const char *buf, size_t count)
 {
-	int rc;
+	struct subsys_private *sp = bus_to_subsys(bus);
+	int ret;
 
-	rc = kobject_synth_uevent(&bus->p->subsys.kobj, buf, count);
-	return rc ? rc : count;
+	if (!sp)
+		return -EINVAL;
+
+	ret = kobject_synth_uevent(&sp->subsys.kobj, buf, count);
+	subsys_put(sp);
+
+	if (ret)
+		return ret;
+	return count;
 }
 /*
  * "open code" the old BUS_ATTR() macro here.  We want to use BUS_ATTR_WO()
@@ -788,7 +879,7 @@ static ssize_t bus_uevent_store(struct bus_type *bus,
  * DEVICE_ATTR_WO(uevent), which would cause a clash with the with the store
  * function name.
  */
-static struct bus_attribute bus_attr_uevent = __ATTR(uevent, S_IWUSR, NULL,
+static struct bus_attribute bus_attr_uevent = __ATTR(uevent, 0200, NULL,
 						     bus_uevent_store);
 
 /**
@@ -799,27 +890,28 @@ static struct bus_attribute bus_attr_uevent = __ATTR(uevent, S_IWUSR, NULL,
  * infrastructure, then register the children subsystems it has:
  * the devices and drivers that belong to the subsystem.
  */
-int bus_register(struct bus_type *bus)
+int bus_register(const struct bus_type *bus)
 {
 	int retval;
 	struct subsys_private *priv;
-	struct lock_class_key *key = &bus->lock_key;
+	struct kobject *bus_kobj;
+	struct lock_class_key *key;
 
 	priv = kzalloc(sizeof(struct subsys_private), GFP_KERNEL);
 	if (!priv)
 		return -ENOMEM;
 
 	priv->bus = bus;
-	bus->p = priv;
 
 	BLOCKING_INIT_NOTIFIER_HEAD(&priv->bus_notifier);
 
-	retval = kobject_set_name(&priv->subsys.kobj, "%s", bus->name);
+	bus_kobj = &priv->subsys.kobj;
+	retval = kobject_set_name(bus_kobj, "%s", bus->name);
 	if (retval)
 		goto out;
 
-	priv->subsys.kobj.kset = bus_kset;
-	priv->subsys.kobj.ktype = &bus_ktype;
+	bus_kobj->kset = bus_kset;
+	bus_kobj->ktype = &bus_ktype;
 	priv->drivers_autoprobe = 1;
 
 	retval = kset_register(&priv->subsys);
@@ -830,21 +922,21 @@ int bus_register(struct bus_type *bus)
 	if (retval)
 		goto bus_uevent_fail;
 
-	priv->devices_kset = kset_create_and_add("devices", NULL,
-						 &priv->subsys.kobj);
+	priv->devices_kset = kset_create_and_add("devices", NULL, bus_kobj);
 	if (!priv->devices_kset) {
 		retval = -ENOMEM;
 		goto bus_devices_fail;
 	}
 
-	priv->drivers_kset = kset_create_and_add("drivers", NULL,
-						 &priv->subsys.kobj);
+	priv->drivers_kset = kset_create_and_add("drivers", NULL, bus_kobj);
 	if (!priv->drivers_kset) {
 		retval = -ENOMEM;
 		goto bus_drivers_fail;
 	}
 
 	INIT_LIST_HEAD(&priv->interfaces);
+	key = &priv->lock_key;
+	lockdep_register_key(key);
 	__mutex_init(&priv->mutex, "subsys mutex", key);
 	klist_init(&priv->klist_devices, klist_devices_get, klist_devices_put);
 	klist_init(&priv->klist_drivers, NULL, NULL);
@@ -853,7 +945,7 @@ int bus_register(struct bus_type *bus)
 	if (retval)
 		goto bus_probe_files_fail;
 
-	retval = bus_add_groups(bus, bus->bus_groups);
+	retval = sysfs_create_groups(bus_kobj, bus->bus_groups);
 	if (retval)
 		goto bus_groups_fail;
 
@@ -863,16 +955,17 @@ int bus_register(struct bus_type *bus)
 bus_groups_fail:
 	remove_probe_files(bus);
 bus_probe_files_fail:
-	kset_unregister(bus->p->drivers_kset);
+	kset_unregister(priv->drivers_kset);
 bus_drivers_fail:
-	kset_unregister(bus->p->devices_kset);
+	kset_unregister(priv->devices_kset);
 bus_devices_fail:
 	bus_remove_file(bus, &bus_attr_uevent);
 bus_uevent_fail:
-	kset_unregister(&bus->p->subsys);
+	kset_unregister(&priv->subsys);
+	/* Above kset_unregister() will kfree @priv */
+	priv = NULL;
 out:
-	kfree(bus->p);
-	bus->p = NULL;
+	kfree(priv);
 	return retval;
 }
 EXPORT_SYMBOL_GPL(bus_register);
@@ -884,43 +977,82 @@ EXPORT_SYMBOL_GPL(bus_register);
  * Unregister the child subsystems and the bus itself.
  * Finally, we call bus_put() to release the refcount
  */
-void bus_unregister(struct bus_type *bus)
+void bus_unregister(const struct bus_type *bus)
 {
+	struct subsys_private *sp = bus_to_subsys(bus);
+	struct kobject *bus_kobj;
+
+	if (!sp)
+		return;
+
 	pr_debug("bus: '%s': unregistering\n", bus->name);
-	if (bus->dev_root)
-		device_unregister(bus->dev_root);
-	bus_remove_groups(bus, bus->bus_groups);
+	if (sp->dev_root)
+		device_unregister(sp->dev_root);
+
+	bus_kobj = &sp->subsys.kobj;
+	sysfs_remove_groups(bus_kobj, bus->bus_groups);
 	remove_probe_files(bus);
-	kset_unregister(bus->p->drivers_kset);
-	kset_unregister(bus->p->devices_kset);
 	bus_remove_file(bus, &bus_attr_uevent);
-	kset_unregister(&bus->p->subsys);
+
+	kset_unregister(sp->drivers_kset);
+	kset_unregister(sp->devices_kset);
+	kset_unregister(&sp->subsys);
+	subsys_put(sp);
 }
 EXPORT_SYMBOL_GPL(bus_unregister);
 
-int bus_register_notifier(struct bus_type *bus, struct notifier_block *nb)
+int bus_register_notifier(const struct bus_type *bus, struct notifier_block *nb)
 {
-	return blocking_notifier_chain_register(&bus->p->bus_notifier, nb);
+	struct subsys_private *sp = bus_to_subsys(bus);
+	int retval;
+
+	if (!sp)
+		return -EINVAL;
+
+	retval = blocking_notifier_chain_register(&sp->bus_notifier, nb);
+	subsys_put(sp);
+	return retval;
 }
 EXPORT_SYMBOL_GPL(bus_register_notifier);
 
-int bus_unregister_notifier(struct bus_type *bus, struct notifier_block *nb)
+int bus_unregister_notifier(const struct bus_type *bus, struct notifier_block *nb)
 {
-	return blocking_notifier_chain_unregister(&bus->p->bus_notifier, nb);
+	struct subsys_private *sp = bus_to_subsys(bus);
+	int retval;
+
+	if (!sp)
+		return -EINVAL;
+	retval = blocking_notifier_chain_unregister(&sp->bus_notifier, nb);
+	subsys_put(sp);
+	return retval;
 }
 EXPORT_SYMBOL_GPL(bus_unregister_notifier);
 
-struct kset *bus_get_kset(struct bus_type *bus)
+void bus_notify(struct device *dev, enum bus_notifier_event value)
 {
-	return &bus->p->subsys;
+	struct subsys_private *sp = bus_to_subsys(dev->bus);
+
+	if (!sp)
+		return;
+
+	blocking_notifier_call_chain(&sp->bus_notifier, value, dev);
+	subsys_put(sp);
 }
-EXPORT_SYMBOL_GPL(bus_get_kset);
 
-struct klist *bus_get_device_klist(struct bus_type *bus)
+struct kset *bus_get_kset(const struct bus_type *bus)
 {
-	return &bus->p->klist_devices;
+	struct subsys_private *sp = bus_to_subsys(bus);
+	struct kset *kset;
+
+	if (!sp)
+		return NULL;
+
+	kset = &sp->subsys;
+	subsys_put(sp);
+
+	return kset;
 }
-EXPORT_SYMBOL_GPL(bus_get_device_klist);
+EXPORT_SYMBOL_GPL(bus_get_kset);
 
 /*
  * Yes, this forcibly breaks the klist abstraction temporarily.  It
@@ -949,17 +1081,20 @@ static void device_insertion_sort_klist(struct device *a, struct list_head *list
 	list_move_tail(&a->p->knode_bus.n_node, list);
 }
 
-void bus_sort_breadthfirst(struct bus_type *bus,
+void bus_sort_breadthfirst(const struct bus_type *bus,
 			   int (*compare)(const struct device *a,
 					  const struct device *b))
 {
+	struct subsys_private *sp = bus_to_subsys(bus);
 	LIST_HEAD(sorted_devices);
 	struct klist_node *n, *tmp;
 	struct device_private *dev_prv;
 	struct device *dev;
 	struct klist *device_klist;
 
-	device_klist = bus_get_device_klist(bus);
+	if (!sp)
+		return;
+	device_klist = &sp->klist_devices;
 
 	spin_lock(&device_klist->k_lock);
 	list_for_each_entry_safe(n, tmp, &device_klist->k_list, n_node) {
@@ -969,13 +1104,19 @@ void bus_sort_breadthfirst(struct bus_type *bus,
 	}
 	list_splice(&sorted_devices, &device_klist->k_list);
 	spin_unlock(&device_klist->k_lock);
+	subsys_put(sp);
 }
 EXPORT_SYMBOL_GPL(bus_sort_breadthfirst);
 
+struct subsys_dev_iter {
+	struct klist_iter		ki;
+	const struct device_type	*type;
+};
+
 /**
  * subsys_dev_iter_init - initialize subsys device iterator
  * @iter: subsys iterator to initialize
- * @subsys: the subsys we wanna iterate over
+ * @sp: the subsys private (i.e. bus) we wanna iterate over
  * @start: the device to start iterating from, if any
  * @type: device_type of the devices to iterate over, NULL for all
  *
@@ -984,17 +1125,16 @@ EXPORT_SYMBOL_GPL(bus_sort_breadthfirst);
  * otherwise if it is NULL, the iteration starts at the beginning of
  * the list.
  */
-void subsys_dev_iter_init(struct subsys_dev_iter *iter, struct bus_type *subsys,
-			  struct device *start, const struct device_type *type)
+static void subsys_dev_iter_init(struct subsys_dev_iter *iter, struct subsys_private *sp,
+				 struct device *start, const struct device_type *type)
 {
 	struct klist_node *start_knode = NULL;
 
 	if (start)
 		start_knode = &start->p->knode_bus;
-	klist_iter_init_node(&subsys->p->klist_devices, &iter->ki, start_knode);
+	klist_iter_init_node(&sp->klist_devices, &iter->ki, start_knode);
 	iter->type = type;
 }
-EXPORT_SYMBOL_GPL(subsys_dev_iter_init);
 
 /**
  * subsys_dev_iter_next - iterate to the next device
@@ -1008,7 +1148,7 @@ EXPORT_SYMBOL_GPL(subsys_dev_iter_init);
  * free to do whatever it wants to do with the device including
  * calling back into subsys code.
  */
-struct device *subsys_dev_iter_next(struct subsys_dev_iter *iter)
+static struct device *subsys_dev_iter_next(struct subsys_dev_iter *iter)
 {
 	struct klist_node *knode;
 	struct device *dev;
@@ -1022,7 +1162,6 @@ struct device *subsys_dev_iter_next(struct subsys_dev_iter *iter)
 			return dev;
 	}
 }
-EXPORT_SYMBOL_GPL(subsys_dev_iter_next);
 
 /**
  * subsys_dev_iter_exit - finish iteration
@@ -1031,34 +1170,38 @@ EXPORT_SYMBOL_GPL(subsys_dev_iter_next);
  * Finish an iteration.  Always call this function after iteration is
  * complete whether the iteration ran till the end or not.
  */
-void subsys_dev_iter_exit(struct subsys_dev_iter *iter)
+static void subsys_dev_iter_exit(struct subsys_dev_iter *iter)
 {
 	klist_iter_exit(&iter->ki);
 }
-EXPORT_SYMBOL_GPL(subsys_dev_iter_exit);
 
 int subsys_interface_register(struct subsys_interface *sif)
 {
-	struct bus_type *subsys;
+	struct subsys_private *sp;
 	struct subsys_dev_iter iter;
 	struct device *dev;
 
 	if (!sif || !sif->subsys)
 		return -ENODEV;
 
-	subsys = bus_get(sif->subsys);
-	if (!subsys)
+	sp = bus_to_subsys(sif->subsys);
+	if (!sp)
 		return -EINVAL;
 
-	mutex_lock(&subsys->p->mutex);
-	list_add_tail(&sif->node, &subsys->p->interfaces);
+	/*
+	 * Reference in sp is now incremented and will be dropped when
+	 * the interface is removed from the bus
+	 */
+
+	mutex_lock(&sp->mutex);
+	list_add_tail(&sif->node, &sp->interfaces);
 	if (sif->add_dev) {
-		subsys_dev_iter_init(&iter, subsys, NULL, NULL);
+		subsys_dev_iter_init(&iter, sp, NULL, NULL);
 		while ((dev = subsys_dev_iter_next(&iter)))
 			sif->add_dev(dev, sif);
 		subsys_dev_iter_exit(&iter);
 	}
-	mutex_unlock(&subsys->p->mutex);
+	mutex_unlock(&sp->mutex);
 
 	return 0;
 }
@@ -1066,26 +1209,34 @@ EXPORT_SYMBOL_GPL(subsys_interface_register);
 
 void subsys_interface_unregister(struct subsys_interface *sif)
 {
-	struct bus_type *subsys;
+	struct subsys_private *sp;
 	struct subsys_dev_iter iter;
 	struct device *dev;
 
 	if (!sif || !sif->subsys)
 		return;
 
-	subsys = sif->subsys;
+	sp = bus_to_subsys(sif->subsys);
+	if (!sp)
+		return;
 
-	mutex_lock(&subsys->p->mutex);
+	mutex_lock(&sp->mutex);
 	list_del_init(&sif->node);
 	if (sif->remove_dev) {
-		subsys_dev_iter_init(&iter, subsys, NULL, NULL);
+		subsys_dev_iter_init(&iter, sp, NULL, NULL);
 		while ((dev = subsys_dev_iter_next(&iter)))
 			sif->remove_dev(dev, sif);
 		subsys_dev_iter_exit(&iter);
 	}
-	mutex_unlock(&subsys->p->mutex);
-
-	bus_put(subsys);
+	mutex_unlock(&sp->mutex);
+
+	/*
+	 * Decrement the reference count twice, once for the bus_to_subsys()
+	 * call in the start of this function, and the second one from the
+	 * reference increment in subsys_interface_register()
+	 */
+	subsys_put(sp);
+	subsys_put(sp);
 }
 EXPORT_SYMBOL_GPL(subsys_interface_unregister);
 
@@ -1094,10 +1245,11 @@ static void system_root_device_release(struct device *dev)
 	kfree(dev);
 }
 
-static int subsys_register(struct bus_type *subsys,
+static int subsys_register(const struct bus_type *subsys,
 			   const struct attribute_group **groups,
 			   struct kobject *parent_of_root)
 {
+	struct subsys_private *sp;
 	struct device *dev;
 	int err;
 
@@ -1105,6 +1257,12 @@ static int subsys_register(struct bus_type *subsys,
 	if (err < 0)
 		return err;
 
+	sp = bus_to_subsys(subsys);
+	if (!sp) {
+		err = -EINVAL;
+		goto err_sp;
+	}
+
 	dev = kzalloc(sizeof(struct device), GFP_KERNEL);
 	if (!dev) {
 		err = -ENOMEM;
@@ -1123,7 +1281,8 @@ static int subsys_register(struct bus_type *subsys,
 	if (err < 0)
 		goto err_dev_reg;
 
-	subsys->dev_root = dev;
+	sp->dev_root = dev;
+	subsys_put(sp);
 	return 0;
 
 err_dev_reg:
@@ -1132,6 +1291,8 @@ err_dev_reg:
 err_name:
 	kfree(dev);
 err_dev:
+	subsys_put(sp);
+err_sp:
 	bus_unregister(subsys);
 	return err;
 }
@@ -1154,7 +1315,7 @@ err_dev:
  * directory itself and not some create fake root-device placed in
  * /sys/devices/system/<name>.
  */
-int subsys_system_register(struct bus_type *subsys,
+int subsys_system_register(const struct bus_type *subsys,
 			   const struct attribute_group **groups)
 {
 	return subsys_register(subsys, groups, &system_kset->kobj);
@@ -1167,17 +1328,17 @@ EXPORT_SYMBOL_GPL(subsys_system_register);
  * @groups: default attributes for the root device
  *
  * All 'virtual' subsystems have a /sys/devices/system/<name> root device
- * with the name of the subystem.  The root device can carry subsystem-wide
+ * with the name of the subsystem.  The root device can carry subsystem-wide
  * attributes.  All registered devices are below this single root device.
  * There's no restriction on device naming.  This is for kernel software
  * constructs which need sysfs interface.
  */
-int subsys_virtual_register(struct bus_type *subsys,
+int subsys_virtual_register(const struct bus_type *subsys,
 			    const struct attribute_group **groups)
 {
 	struct kobject *virtual_dir;
 
-	virtual_dir = virtual_device_parent(NULL);
+	virtual_dir = virtual_device_parent();
 	if (!virtual_dir)
 		return -ENOMEM;
 
@@ -1185,6 +1346,82 @@ int subsys_virtual_register(struct bus_type *subsys,
 }
 EXPORT_SYMBOL_GPL(subsys_virtual_register);
 
+/**
+ * driver_find - locate driver on a bus by its name.
+ * @name: name of the driver.
+ * @bus: bus to scan for the driver.
+ *
+ * Call kset_find_obj() to iterate over list of drivers on
+ * a bus to find driver by name. Return driver if found.
+ *
+ * This routine provides no locking to prevent the driver it returns
+ * from being unregistered or unloaded while the caller is using it.
+ * The caller is responsible for preventing this.
+ */
+struct device_driver *driver_find(const char *name, const struct bus_type *bus)
+{
+	struct subsys_private *sp = bus_to_subsys(bus);
+	struct kobject *k;
+	struct driver_private *priv;
+
+	if (!sp)
+		return NULL;
+
+	k = kset_find_obj(sp->drivers_kset, name);
+	subsys_put(sp);
+	if (!k)
+		return NULL;
+
+	priv = to_driver(k);
+
+	/* Drop reference added by kset_find_obj() */
+	kobject_put(k);
+	return priv->driver;
+}
+EXPORT_SYMBOL_GPL(driver_find);
+
+/*
+ * Warning, the value could go to "removed" instantly after calling this function, so be very
+ * careful when calling it...
+ */
+bool bus_is_registered(const struct bus_type *bus)
+{
+	struct subsys_private *sp = bus_to_subsys(bus);
+	bool is_initialized = false;
+
+	if (sp) {
+		is_initialized = true;
+		subsys_put(sp);
+	}
+	return is_initialized;
+}
+
+/**
+ * bus_get_dev_root - return a pointer to the "device root" of a bus
+ * @bus: bus to return the device root of.
+ *
+ * If a bus has a "device root" structure, return it, WITH THE REFERENCE
+ * COUNT INCREMENTED.
+ *
+ * Note, when finished with the device, a call to put_device() is required.
+ *
+ * If the device root is not present (or bus is not a valid pointer), NULL
+ * will be returned.
+ */
+struct device *bus_get_dev_root(const struct bus_type *bus)
+{
+	struct subsys_private *sp = bus_to_subsys(bus);
+	struct device *dev_root;
+
+	if (!sp)
+		return NULL;
+
+	dev_root = get_device(sp->dev_root);
+	subsys_put(sp);
+	return dev_root;
+}
+EXPORT_SYMBOL_GPL(bus_get_dev_root);
+
 int __init buses_init(void)
 {
 	bus_kset = kset_create_and_add("bus", &bus_uevent_ops, NULL);
@@ -1192,8 +1429,13 @@ int __init buses_init(void)
 		return -ENOMEM;
 
 	system_kset = kset_create_and_add("system", NULL, &devices_kset->kobj);
-	if (!system_kset)
+	if (!system_kset) {
+		/* Do error handling here as devices_init() do */
+		kset_unregister(bus_kset);
+		bus_kset = NULL;
+		pr_err("%s: failed to create and add kset 'bus'\n", __func__);
 		return -ENOMEM;
+	}
 
 	return 0;
 }
diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c
index 8d553c92cd32..613410705a47 100644
--- a/drivers/base/cacheinfo.c
+++ b/drivers/base/cacheinfo.c
@@ -8,6 +8,7 @@
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 
 #include <linux/acpi.h>
+#include <linux/bitfield.h>
 #include <linux/bitops.h>
 #include <linux/cacheinfo.h>
 #include <linux/compiler.h>
@@ -25,19 +26,66 @@ static DEFINE_PER_CPU(struct cpu_cacheinfo, ci_cpu_cacheinfo);
 #define ci_cacheinfo(cpu)	(&per_cpu(ci_cpu_cacheinfo, cpu))
 #define cache_leaves(cpu)	(ci_cacheinfo(cpu)->num_leaves)
 #define per_cpu_cacheinfo(cpu)	(ci_cacheinfo(cpu)->info_list)
+#define per_cpu_cacheinfo_idx(cpu, idx)		\
+				(per_cpu_cacheinfo(cpu) + (idx))
+
+/* Set if no cache information is found in DT/ACPI. */
+static bool use_arch_info;
 
 struct cpu_cacheinfo *get_cpu_cacheinfo(unsigned int cpu)
 {
 	return ci_cacheinfo(cpu);
 }
 
-#ifdef CONFIG_OF
 static inline bool cache_leaves_are_shared(struct cacheinfo *this_leaf,
 					   struct cacheinfo *sib_leaf)
 {
+	/*
+	 * For non DT/ACPI systems, assume unique level 1 caches,
+	 * system-wide shared caches for all other levels.
+	 */
+	if (!(IS_ENABLED(CONFIG_OF) || IS_ENABLED(CONFIG_ACPI)) ||
+	    use_arch_info)
+		return (this_leaf->level != 1) && (sib_leaf->level != 1);
+
+	if ((sib_leaf->attributes & CACHE_ID) &&
+	    (this_leaf->attributes & CACHE_ID))
+		return sib_leaf->id == this_leaf->id;
+
 	return sib_leaf->fw_token == this_leaf->fw_token;
 }
 
+bool last_level_cache_is_valid(unsigned int cpu)
+{
+	struct cacheinfo *llc;
+
+	if (!cache_leaves(cpu) || !per_cpu_cacheinfo(cpu))
+		return false;
+
+	llc = per_cpu_cacheinfo_idx(cpu, cache_leaves(cpu) - 1);
+
+	return (llc->attributes & CACHE_ID) || !!llc->fw_token;
+
+}
+
+bool last_level_cache_is_shared(unsigned int cpu_x, unsigned int cpu_y)
+{
+	struct cacheinfo *llc_x, *llc_y;
+
+	if (!last_level_cache_is_valid(cpu_x) ||
+	    !last_level_cache_is_valid(cpu_y))
+		return false;
+
+	llc_x = per_cpu_cacheinfo_idx(cpu_x, cache_leaves(cpu_x) - 1);
+	llc_y = per_cpu_cacheinfo_idx(cpu_y, cache_leaves(cpu_y) - 1);
+
+	return cache_leaves_are_shared(llc_x, llc_y);
+}
+
+#ifdef CONFIG_OF
+
+static bool of_check_cache_nodes(struct device_node *np);
+
 /* OF properties to query for a given cache type */
 struct cache_type_info {
 	const char *size_prop;
@@ -136,6 +184,54 @@ static bool cache_node_is_unified(struct cacheinfo *this_leaf,
 	return of_property_read_bool(np, "cache-unified");
 }
 
+static bool match_cache_node(struct device_node *cpu,
+			     const struct device_node *cache_node)
+{
+	struct device_node *prev, *cache = of_find_next_cache_node(cpu);
+
+	while (cache) {
+		if (cache == cache_node) {
+			of_node_put(cache);
+			return true;
+		}
+
+		prev = cache;
+		cache = of_find_next_cache_node(cache);
+		of_node_put(prev);
+	}
+
+	return false;
+}
+
+#ifndef arch_compact_of_hwid
+#define arch_compact_of_hwid(_x)	(_x)
+#endif
+
+static void cache_of_set_id(struct cacheinfo *this_leaf,
+			    struct device_node *cache_node)
+{
+	struct device_node *cpu;
+	u32 min_id = ~0;
+
+	for_each_of_cpu_node(cpu) {
+		u64 id = of_get_cpu_hwid(cpu, 0);
+
+		id = arch_compact_of_hwid(id);
+		if (FIELD_GET(GENMASK_ULL(63, 32), id)) {
+			of_node_put(cpu);
+			return;
+		}
+
+		if (match_cache_node(cpu, cache_node))
+			min_id = min(min_id, id);
+	}
+
+	if (min_id != ~0) {
+		this_leaf->id = min_id;
+		this_leaf->attributes |= CACHE_ID;
+	}
+}
+
 static void cache_of_set_props(struct cacheinfo *this_leaf,
 			       struct device_node *np)
 {
@@ -151,39 +247,32 @@ static void cache_of_set_props(struct cacheinfo *this_leaf,
 	cache_get_line_size(this_leaf, np);
 	cache_nr_sets(this_leaf, np);
 	cache_associativity(this_leaf);
+	cache_of_set_id(this_leaf, np);
 }
 
 static int cache_setup_of_node(unsigned int cpu)
 {
-	struct device_node *np;
 	struct cacheinfo *this_leaf;
-	struct device *cpu_dev = get_cpu_device(cpu);
-	struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
 	unsigned int index = 0;
 
-	/* skip if fw_token is already populated */
-	if (this_cpu_ci->info_list->fw_token) {
-		return 0;
-	}
-
-	if (!cpu_dev) {
-		pr_err("No cpu device for CPU %d\n", cpu);
-		return -ENODEV;
-	}
-	np = cpu_dev->of_node;
+	struct device_node *np __free(device_node) = of_cpu_device_node_get(cpu);
 	if (!np) {
 		pr_err("Failed to find cpu%d device node\n", cpu);
 		return -ENOENT;
 	}
 
+	if (!of_check_cache_nodes(np)) {
+		return -ENOENT;
+	}
+
 	while (index < cache_leaves(cpu)) {
-		this_leaf = this_cpu_ci->info_list + index;
-		if (this_leaf->level != 1)
+		this_leaf = per_cpu_cacheinfo_idx(cpu, index);
+		if (this_leaf->level != 1) {
+			struct device_node *prev __free(device_node) = np;
 			np = of_find_next_cache_node(np);
-		else
-			np = of_node_get(np);/* cpu node itself */
-		if (!np)
-			break;
+			if (!np)
+				break;
+		}
 		cache_of_set_props(this_leaf, np);
 		this_leaf->fw_token = np;
 		index++;
@@ -194,18 +283,87 @@ static int cache_setup_of_node(unsigned int cpu)
 
 	return 0;
 }
-#else
-static inline int cache_setup_of_node(unsigned int cpu) { return 0; }
-static inline bool cache_leaves_are_shared(struct cacheinfo *this_leaf,
-					   struct cacheinfo *sib_leaf)
+
+static bool of_check_cache_nodes(struct device_node *np)
 {
-	/*
-	 * For non-DT/ACPI systems, assume unique level 1 caches, system-wide
-	 * shared caches for all other levels. This will be used only if
-	 * arch specific code has not populated shared_cpu_map
-	 */
-	return !(this_leaf->level == 1);
+	if (of_property_present(np, "cache-size")   ||
+	    of_property_present(np, "i-cache-size") ||
+	    of_property_present(np, "d-cache-size") ||
+	    of_property_present(np, "cache-unified"))
+		return true;
+
+	struct device_node *next __free(device_node) = of_find_next_cache_node(np);
+	if (next) {
+		return true;
+	}
+
+	return false;
+}
+
+static int of_count_cache_leaves(struct device_node *np)
+{
+	unsigned int leaves = 0;
+
+	if (of_property_present(np, "cache-size"))
+		++leaves;
+	if (of_property_present(np, "i-cache-size"))
+		++leaves;
+	if (of_property_present(np, "d-cache-size"))
+		++leaves;
+
+	if (!leaves) {
+		/* The '[i-|d-|]cache-size' property is required, but
+		 * if absent, fallback on the 'cache-unified' property.
+		 */
+		if (of_property_read_bool(np, "cache-unified"))
+			return 1;
+		else
+			return 2;
+	}
+
+	return leaves;
+}
+
+int init_of_cache_level(unsigned int cpu)
+{
+	struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
+	struct device_node *np __free(device_node) = of_cpu_device_node_get(cpu);
+	unsigned int levels = 0, leaves, level;
+
+	if (!of_check_cache_nodes(np)) {
+		return -ENOENT;
+	}
+
+	leaves = of_count_cache_leaves(np);
+	if (leaves > 0)
+		levels = 1;
+
+	while (1) {
+		struct device_node *prev __free(device_node) = np;
+		np = of_find_next_cache_node(np);
+		if (!np)
+			break;
+
+		if (!of_device_is_compatible(np, "cache"))
+			return -EINVAL;
+		if (of_property_read_u32(np, "cache-level", &level))
+			return -EINVAL;
+		if (level <= levels)
+			return -EINVAL;
+
+		leaves += of_count_cache_leaves(np);
+		levels = level;
+	}
+
+	this_cpu_ci->num_levels = levels;
+	this_cpu_ci->num_leaves = leaves;
+
+	return 0;
 }
+
+#else
+static inline int cache_setup_of_node(unsigned int cpu) { return 0; }
+int init_of_cache_level(unsigned int cpu) { return 0; }
 #endif
 
 int __weak cache_setup_acpi(unsigned int cpu)
@@ -215,42 +373,69 @@ int __weak cache_setup_acpi(unsigned int cpu)
 
 unsigned int coherency_max_size;
 
+static int cache_setup_properties(unsigned int cpu)
+{
+	int ret = 0;
+
+	if (of_have_populated_dt())
+		ret = cache_setup_of_node(cpu);
+	else if (!acpi_disabled)
+		ret = cache_setup_acpi(cpu);
+
+	// Assume there is no cache information available in DT/ACPI from now.
+	if (ret && use_arch_cache_info())
+		use_arch_info = true;
+
+	return ret;
+}
+
 static int cache_shared_cpu_map_setup(unsigned int cpu)
 {
 	struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
 	struct cacheinfo *this_leaf, *sib_leaf;
-	unsigned int index;
+	unsigned int index, sib_index;
 	int ret = 0;
 
 	if (this_cpu_ci->cpu_map_populated)
 		return 0;
 
-	if (of_have_populated_dt())
-		ret = cache_setup_of_node(cpu);
-	else if (!acpi_disabled)
-		ret = cache_setup_acpi(cpu);
-
-	if (ret)
-		return ret;
+	/*
+	 * skip setting up cache properties if LLC is valid, just need
+	 * to update the shared cpu_map if the cache attributes were
+	 * populated early before all the cpus are brought online
+	 */
+	if (!last_level_cache_is_valid(cpu) && !use_arch_info) {
+		ret = cache_setup_properties(cpu);
+		if (ret)
+			return ret;
+	}
 
 	for (index = 0; index < cache_leaves(cpu); index++) {
 		unsigned int i;
 
-		this_leaf = this_cpu_ci->info_list + index;
-		/* skip if shared_cpu_map is already populated */
-		if (!cpumask_empty(&this_leaf->shared_cpu_map))
-			continue;
+		this_leaf = per_cpu_cacheinfo_idx(cpu, index);
 
 		cpumask_set_cpu(cpu, &this_leaf->shared_cpu_map);
 		for_each_online_cpu(i) {
-			struct cpu_cacheinfo *sib_cpu_ci = get_cpu_cacheinfo(i);
-
-			if (i == cpu || !sib_cpu_ci->info_list)
+			if (i == cpu || !per_cpu_cacheinfo(i))
 				continue;/* skip if itself or no cacheinfo */
-			sib_leaf = sib_cpu_ci->info_list + index;
-			if (cache_leaves_are_shared(this_leaf, sib_leaf)) {
-				cpumask_set_cpu(cpu, &sib_leaf->shared_cpu_map);
-				cpumask_set_cpu(i, &this_leaf->shared_cpu_map);
+			for (sib_index = 0; sib_index < cache_leaves(i); sib_index++) {
+				sib_leaf = per_cpu_cacheinfo_idx(i, sib_index);
+
+				/*
+				 * Comparing cache IDs only makes sense if the leaves
+				 * belong to the same cache level of same type. Skip
+				 * the check if level and type do not match.
+				 */
+				if (sib_leaf->level != this_leaf->level ||
+				    sib_leaf->type != this_leaf->type)
+					continue;
+
+				if (cache_leaves_are_shared(this_leaf, sib_leaf)) {
+					cpumask_set_cpu(cpu, &sib_leaf->shared_cpu_map);
+					cpumask_set_cpu(i, &this_leaf->shared_cpu_map);
+					break;
+				}
 			}
 		}
 		/* record the maximum cache line size */
@@ -258,6 +443,8 @@ static int cache_shared_cpu_map_setup(unsigned int cpu)
 			coherency_max_size = this_leaf->coherency_line_size;
 	}
 
+	/* shared_cpu_map is now populated for the cpu */
+	this_cpu_ci->cpu_map_populated = true;
 	return 0;
 }
 
@@ -265,27 +452,37 @@ static void cache_shared_cpu_map_remove(unsigned int cpu)
 {
 	struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
 	struct cacheinfo *this_leaf, *sib_leaf;
-	unsigned int sibling, index;
+	unsigned int sibling, index, sib_index;
 
 	for (index = 0; index < cache_leaves(cpu); index++) {
-		this_leaf = this_cpu_ci->info_list + index;
+		this_leaf = per_cpu_cacheinfo_idx(cpu, index);
 		for_each_cpu(sibling, &this_leaf->shared_cpu_map) {
-			struct cpu_cacheinfo *sib_cpu_ci;
-
-			if (sibling == cpu) /* skip itself */
-				continue;
-
-			sib_cpu_ci = get_cpu_cacheinfo(sibling);
-			if (!sib_cpu_ci->info_list)
-				continue;
+			if (sibling == cpu || !per_cpu_cacheinfo(sibling))
+				continue;/* skip if itself or no cacheinfo */
 
-			sib_leaf = sib_cpu_ci->info_list + index;
-			cpumask_clear_cpu(cpu, &sib_leaf->shared_cpu_map);
-			cpumask_clear_cpu(sibling, &this_leaf->shared_cpu_map);
+			for (sib_index = 0; sib_index < cache_leaves(sibling); sib_index++) {
+				sib_leaf = per_cpu_cacheinfo_idx(sibling, sib_index);
+
+				/*
+				 * Comparing cache IDs only makes sense if the leaves
+				 * belong to the same cache level of same type. Skip
+				 * the check if level and type do not match.
+				 */
+				if (sib_leaf->level != this_leaf->level ||
+				    sib_leaf->type != this_leaf->type)
+					continue;
+
+				if (cache_leaves_are_shared(this_leaf, sib_leaf)) {
+					cpumask_clear_cpu(cpu, &sib_leaf->shared_cpu_map);
+					cpumask_clear_cpu(sibling, &this_leaf->shared_cpu_map);
+					break;
+				}
+			}
 		}
-		if (of_have_populated_dt())
-			of_node_put(this_leaf->fw_token);
 	}
+
+	/* cpu is no longer populated in the shared map */
+	this_cpu_ci->cpu_map_populated = false;
 }
 
 static void free_cache_attributes(unsigned int cpu)
@@ -294,9 +491,11 @@ static void free_cache_attributes(unsigned int cpu)
 		return;
 
 	cache_shared_cpu_map_remove(cpu);
+}
 
-	kfree(per_cpu_cacheinfo(cpu));
-	per_cpu_cacheinfo(cpu) = NULL;
+int __weak early_cache_level(unsigned int cpu)
+{
+	return -ENOENT;
 }
 
 int __weak init_cache_level(unsigned int cpu)
@@ -309,25 +508,113 @@ int __weak populate_cache_leaves(unsigned int cpu)
 	return -ENOENT;
 }
 
-static int detect_cache_attributes(unsigned int cpu)
+static inline int allocate_cache_info(int cpu)
+{
+	per_cpu_cacheinfo(cpu) = kcalloc(cache_leaves(cpu), sizeof(struct cacheinfo), GFP_ATOMIC);
+	if (!per_cpu_cacheinfo(cpu)) {
+		cache_leaves(cpu) = 0;
+		return -ENOMEM;
+	}
+
+	return 0;
+}
+
+int fetch_cache_info(unsigned int cpu)
 {
+	struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
+	unsigned int levels = 0, split_levels = 0;
 	int ret;
 
+	if (acpi_disabled) {
+		ret = init_of_cache_level(cpu);
+	} else {
+		ret = acpi_get_cache_info(cpu, &levels, &split_levels);
+		if (!ret) {
+			this_cpu_ci->num_levels = levels;
+			/*
+			 * This assumes that:
+			 * - there cannot be any split caches (data/instruction)
+			 *   above a unified cache
+			 * - data/instruction caches come by pair
+			 */
+			this_cpu_ci->num_leaves = levels + split_levels;
+		}
+	}
+
+	if (ret || !cache_leaves(cpu)) {
+		ret = early_cache_level(cpu);
+		if (ret)
+			return ret;
+
+		if (!cache_leaves(cpu))
+			return -ENOENT;
+
+		this_cpu_ci->early_ci_levels = true;
+	}
+
+	return allocate_cache_info(cpu);
+}
+
+static inline int init_level_allocate_ci(unsigned int cpu)
+{
+	unsigned int early_leaves = cache_leaves(cpu);
+
+	/* Since early initialization/allocation of the cacheinfo is allowed
+	 * via fetch_cache_info() and this also gets called as CPU hotplug
+	 * callbacks via cacheinfo_cpu_online, the init/alloc can be skipped
+	 * as it will happen only once (the cacheinfo memory is never freed).
+	 * Just populate the cacheinfo. However, if the cacheinfo has been
+	 * allocated early through the arch-specific early_cache_level() call,
+	 * there is a chance the info is wrong (this can happen on arm64). In
+	 * that case, call init_cache_level() anyway to give the arch-specific
+	 * code a chance to make things right.
+	 */
+	if (per_cpu_cacheinfo(cpu) && !ci_cacheinfo(cpu)->early_ci_levels)
+		return 0;
+
 	if (init_cache_level(cpu) || !cache_leaves(cpu))
 		return -ENOENT;
 
-	per_cpu_cacheinfo(cpu) = kcalloc(cache_leaves(cpu),
-					 sizeof(struct cacheinfo), GFP_KERNEL);
-	if (per_cpu_cacheinfo(cpu) == NULL)
-		return -ENOMEM;
+	/*
+	 * Now that we have properly initialized the cache level info, make
+	 * sure we don't try to do that again the next time we are called
+	 * (e.g. as CPU hotplug callbacks).
+	 */
+	ci_cacheinfo(cpu)->early_ci_levels = false;
 
 	/*
-	 * populate_cache_leaves() may completely setup the cache leaves and
-	 * shared_cpu_map or it may leave it partially setup.
+	 * Some architectures (e.g., x86) do not use early initialization.
+	 * Allocate memory now in such case.
 	 */
-	ret = populate_cache_leaves(cpu);
+	if (cache_leaves(cpu) <= early_leaves && per_cpu_cacheinfo(cpu))
+		return 0;
+
+	kfree(per_cpu_cacheinfo(cpu));
+	return allocate_cache_info(cpu);
+}
+
+int detect_cache_attributes(unsigned int cpu)
+{
+	int ret;
+
+	ret = init_level_allocate_ci(cpu);
 	if (ret)
-		goto free_ci;
+		return ret;
+
+	/*
+	 * If LLC is valid the cache leaves were already populated so just go to
+	 * update the cpu map.
+	 */
+	if (!last_level_cache_is_valid(cpu)) {
+		/*
+		 * populate_cache_leaves() may completely setup the cache leaves and
+		 * shared_cpu_map or it may leave it partially setup.
+		 */
+		ret = populate_cache_leaves(cpu);
+		if (ret)
+			goto free_ci;
+	}
+
 	/*
 	 * For systems using DT for cache hierarchy, fw_token
 	 * and shared_cpu_map will be set up here only if they are
@@ -362,7 +649,7 @@ static ssize_t file_name##_show(struct device *dev,		\
 		struct device_attribute *attr, char *buf)	\
 {								\
 	struct cacheinfo *this_leaf = dev_get_drvdata(dev);	\
-	return sprintf(buf, "%u\n", this_leaf->object);		\
+	return sysfs_emit(buf, "%u\n", this_leaf->object);	\
 }
 
 show_one(id, id);
@@ -377,44 +664,48 @@ static ssize_t size_show(struct device *dev,
 {
 	struct cacheinfo *this_leaf = dev_get_drvdata(dev);
 
-	return sprintf(buf, "%uK\n", this_leaf->size >> 10);
+	return sysfs_emit(buf, "%uK\n", this_leaf->size >> 10);
 }
 
-static ssize_t shared_cpumap_show_func(struct device *dev, bool list, char *buf)
+static ssize_t shared_cpu_map_show(struct device *dev,
+				   struct device_attribute *attr, char *buf)
 {
 	struct cacheinfo *this_leaf = dev_get_drvdata(dev);
 	const struct cpumask *mask = &this_leaf->shared_cpu_map;
 
-	return cpumap_print_to_pagebuf(list, buf, mask);
-}
-
-static ssize_t shared_cpu_map_show(struct device *dev,
-				   struct device_attribute *attr, char *buf)
-{
-	return shared_cpumap_show_func(dev, false, buf);
+	return sysfs_emit(buf, "%*pb\n", nr_cpu_ids, mask);
 }
 
 static ssize_t shared_cpu_list_show(struct device *dev,
 				    struct device_attribute *attr, char *buf)
 {
-	return shared_cpumap_show_func(dev, true, buf);
+	struct cacheinfo *this_leaf = dev_get_drvdata(dev);
+	const struct cpumask *mask = &this_leaf->shared_cpu_map;
+
+	return sysfs_emit(buf, "%*pbl\n", nr_cpu_ids, mask);
 }
 
 static ssize_t type_show(struct device *dev,
 			 struct device_attribute *attr, char *buf)
 {
 	struct cacheinfo *this_leaf = dev_get_drvdata(dev);
+	const char *output;
 
 	switch (this_leaf->type) {
 	case CACHE_TYPE_DATA:
-		return sprintf(buf, "Data\n");
+		output = "Data";
+		break;
 	case CACHE_TYPE_INST:
-		return sprintf(buf, "Instruction\n");
+		output = "Instruction";
+		break;
 	case CACHE_TYPE_UNIFIED:
-		return sprintf(buf, "Unified\n");
+		output = "Unified";
+		break;
 	default:
 		return -EINVAL;
 	}
+
+	return sysfs_emit(buf, "%s\n", output);
 }
 
 static ssize_t allocation_policy_show(struct device *dev,
@@ -422,15 +713,18 @@ static ssize_t allocation_policy_show(struct device *dev,
 {
 	struct cacheinfo *this_leaf = dev_get_drvdata(dev);
 	unsigned int ci_attr = this_leaf->attributes;
-	int n = 0;
+	const char *output;
 
 	if ((ci_attr & CACHE_READ_ALLOCATE) && (ci_attr & CACHE_WRITE_ALLOCATE))
-		n = sprintf(buf, "ReadWriteAllocate\n");
+		output = "ReadWriteAllocate";
 	else if (ci_attr & CACHE_READ_ALLOCATE)
-		n = sprintf(buf, "ReadAllocate\n");
+		output = "ReadAllocate";
 	else if (ci_attr & CACHE_WRITE_ALLOCATE)
-		n = sprintf(buf, "WriteAllocate\n");
-	return n;
+		output = "WriteAllocate";
+	else
+		return 0;
+
+	return sysfs_emit(buf, "%s\n", output);
 }
 
 static ssize_t write_policy_show(struct device *dev,
@@ -441,9 +735,9 @@ static ssize_t write_policy_show(struct device *dev,
 	int n = 0;
 
 	if (ci_attr & CACHE_WRITE_THROUGH)
-		n = sprintf(buf, "WriteThrough\n");
+		n = sysfs_emit(buf, "WriteThrough\n");
 	else if (ci_attr & CACHE_WRITE_BACK)
-		n = sprintf(buf, "WriteBack\n");
+		n = sysfs_emit(buf, "WriteBack\n");
 	return n;
 }
 
@@ -606,7 +900,6 @@ static int cache_add_dev(unsigned int cpu)
 	int rc;
 	struct device *ci_dev, *parent;
 	struct cacheinfo *this_leaf;
-	struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
 	const struct attribute_group **cache_groups;
 
 	rc = cpu_cache_sysfs_init(cpu);
@@ -615,7 +908,7 @@ static int cache_add_dev(unsigned int cpu)
 
 	parent = per_cpu_cache_dev(cpu);
 	for (i = 0; i < cache_leaves(cpu); i++) {
-		this_leaf = this_cpu_ci->info_list + i;
+		this_leaf = per_cpu_cacheinfo_idx(cpu, i);
 		if (this_leaf->disable_sysfs)
 			continue;
 		if (this_leaf->type == CACHE_TYPE_NOCACHE)
@@ -637,24 +930,111 @@ err:
 	return rc;
 }
 
+static unsigned int cpu_map_shared_cache(bool online, unsigned int cpu,
+					 cpumask_t **map)
+{
+	struct cacheinfo *llc, *sib_llc;
+	unsigned int sibling;
+
+	if (!last_level_cache_is_valid(cpu))
+		return 0;
+
+	llc = per_cpu_cacheinfo_idx(cpu, cache_leaves(cpu) - 1);
+
+	if (llc->type != CACHE_TYPE_DATA && llc->type != CACHE_TYPE_UNIFIED)
+		return 0;
+
+	if (online) {
+		*map = &llc->shared_cpu_map;
+		return cpumask_weight(*map);
+	}
+
+	/* shared_cpu_map of offlined CPU will be cleared, so use sibling map */
+	for_each_cpu(sibling, &llc->shared_cpu_map) {
+		if (sibling == cpu || !last_level_cache_is_valid(sibling))
+			continue;
+		sib_llc = per_cpu_cacheinfo_idx(sibling, cache_leaves(sibling) - 1);
+		*map = &sib_llc->shared_cpu_map;
+		return cpumask_weight(*map);
+	}
+
+	return 0;
+}
+
+/*
+ * Calculate the size of the per-CPU data cache slice.  This can be
+ * used to estimate the size of the data cache slice that can be used
+ * by one CPU under ideal circumstances.  UNIFIED caches are counted
+ * in addition to DATA caches.  So, please consider code cache usage
+ * when use the result.
+ *
+ * Because the cache inclusive/non-inclusive information isn't
+ * available, we just use the size of the per-CPU slice of LLC to make
+ * the result more predictable across architectures.
+ */
+static void update_per_cpu_data_slice_size_cpu(unsigned int cpu)
+{
+	struct cpu_cacheinfo *ci;
+	struct cacheinfo *llc;
+	unsigned int nr_shared;
+
+	if (!last_level_cache_is_valid(cpu))
+		return;
+
+	ci = ci_cacheinfo(cpu);
+	llc = per_cpu_cacheinfo_idx(cpu, cache_leaves(cpu) - 1);
+
+	if (llc->type != CACHE_TYPE_DATA && llc->type != CACHE_TYPE_UNIFIED)
+		return;
+
+	nr_shared = cpumask_weight(&llc->shared_cpu_map);
+	if (nr_shared)
+		ci->per_cpu_data_slice_size = llc->size / nr_shared;
+}
+
+static void update_per_cpu_data_slice_size(bool cpu_online, unsigned int cpu,
+					   cpumask_t *cpu_map)
+{
+	unsigned int icpu;
+
+	for_each_cpu(icpu, cpu_map) {
+		if (!cpu_online && icpu == cpu)
+			continue;
+		update_per_cpu_data_slice_size_cpu(icpu);
+		setup_pcp_cacheinfo(icpu);
+	}
+}
+
 static int cacheinfo_cpu_online(unsigned int cpu)
 {
 	int rc = detect_cache_attributes(cpu);
+	cpumask_t *cpu_map;
 
 	if (rc)
 		return rc;
 	rc = cache_add_dev(cpu);
 	if (rc)
-		free_cache_attributes(cpu);
+		goto err;
+	if (cpu_map_shared_cache(true, cpu, &cpu_map))
+		update_per_cpu_data_slice_size(true, cpu, cpu_map);
+	return 0;
+err:
+	free_cache_attributes(cpu);
 	return rc;
 }
 
 static int cacheinfo_cpu_pre_down(unsigned int cpu)
 {
+	cpumask_t *cpu_map;
+	unsigned int nr_shared;
+
+	nr_shared = cpu_map_shared_cache(false, cpu, &cpu_map);
 	if (cpumask_test_and_clear_cpu(cpu, &cache_dev_map))
 		cpu_cache_sysfs_exit(cpu);
 
 	free_cache_attributes(cpu);
+	if (nr_shared > 1)
+		update_per_cpu_data_slice_size(false, cpu, cpu_map);
 	return 0;
 }
 
diff --git a/drivers/base/class.c b/drivers/base/class.c
index bcd410e6d70a..2526c57d924e 100644
--- a/drivers/base/class.c
+++ b/drivers/base/class.c
@@ -16,12 +16,56 @@
 #include <linux/kdev_t.h>
 #include <linux/err.h>
 #include <linux/slab.h>
-#include <linux/genhd.h>
+#include <linux/blkdev.h>
 #include <linux/mutex.h>
 #include "base.h"
 
+/* /sys/class */
+static struct kset *class_kset;
+
 #define to_class_attr(_attr) container_of(_attr, struct class_attribute, attr)
 
+/**
+ * class_to_subsys - Turn a struct class into a struct subsys_private
+ *
+ * @class: pointer to the struct bus_type to look up
+ *
+ * The driver core internals need to work on the subsys_private structure, not
+ * the external struct class pointer.  This function walks the list of
+ * registered classes in the system and finds the matching one and returns the
+ * internal struct subsys_private that relates to that class.
+ *
+ * Note, the reference count of the return value is INCREMENTED if it is not
+ * NULL.  A call to subsys_put() must be done when finished with the pointer in
+ * order for it to be properly freed.
+ */
+struct subsys_private *class_to_subsys(const struct class *class)
+{
+	struct subsys_private *sp = NULL;
+	struct kobject *kobj;
+
+	if (!class || !class_kset)
+		return NULL;
+
+	spin_lock(&class_kset->list_lock);
+
+	if (list_empty(&class_kset->list))
+		goto done;
+
+	list_for_each_entry(kobj, &class_kset->list, entry) {
+		struct kset *kset = container_of(kobj, struct kset, kobj);
+
+		sp = container_of_const(kset, struct subsys_private, subsys);
+		if (sp->class == class)
+			goto done;
+	}
+	sp = NULL;
+done:
+	sp = subsys_get(sp);
+	spin_unlock(&class_kset->list_lock);
+	return sp;
+}
+
 static ssize_t class_attr_show(struct kobject *kobj, struct attribute *attr,
 			       char *buf)
 {
@@ -49,7 +93,7 @@ static ssize_t class_attr_store(struct kobject *kobj, struct attribute *attr,
 static void class_release(struct kobject *kobj)
 {
 	struct subsys_private *cp = to_subsys_private(kobj);
-	struct class *class = cp->class;
+	const struct class *class = cp->class;
 
 	pr_debug("class '%s': release.\n", class->name);
 
@@ -59,13 +103,14 @@ static void class_release(struct kobject *kobj)
 		pr_debug("class '%s' does not have a release() function, "
 			 "be careful\n", class->name);
 
+	lockdep_unregister_key(&cp->lock_key);
 	kfree(cp);
 }
 
-static const struct kobj_ns_type_operations *class_child_ns_type(struct kobject *kobj)
+static const struct kobj_ns_type_operations *class_child_ns_type(const struct kobject *kobj)
 {
-	struct subsys_private *cp = to_subsys_private(kobj);
-	struct class *class = cp->class;
+	const struct subsys_private *cp = to_subsys_private(kobj);
+	const struct class *class = cp->class;
 
 	return class->ns_type;
 }
@@ -75,48 +120,40 @@ static const struct sysfs_ops class_sysfs_ops = {
 	.store	   = class_attr_store,
 };
 
-static struct kobj_type class_ktype = {
+static const struct kobj_type class_ktype = {
 	.sysfs_ops	= &class_sysfs_ops,
 	.release	= class_release,
 	.child_ns_type	= class_child_ns_type,
 };
 
-/* Hotplug events for classes go to the class subsys */
-static struct kset *class_kset;
-
-
-int class_create_file_ns(struct class *cls, const struct class_attribute *attr,
+int class_create_file_ns(const struct class *cls, const struct class_attribute *attr,
 			 const void *ns)
 {
+	struct subsys_private *sp = class_to_subsys(cls);
 	int error;
 
-	if (cls)
-		error = sysfs_create_file_ns(&cls->p->subsys.kobj,
-					     &attr->attr, ns);
-	else
-		error = -EINVAL;
+	if (!sp)
+		return -EINVAL;
+
+	error = sysfs_create_file_ns(&sp->subsys.kobj, &attr->attr, ns);
+	subsys_put(sp);
+
 	return error;
 }
+EXPORT_SYMBOL_GPL(class_create_file_ns);
 
-void class_remove_file_ns(struct class *cls, const struct class_attribute *attr,
+void class_remove_file_ns(const struct class *cls, const struct class_attribute *attr,
 			  const void *ns)
 {
-	if (cls)
-		sysfs_remove_file_ns(&cls->p->subsys.kobj, &attr->attr, ns);
-}
+	struct subsys_private *sp = class_to_subsys(cls);
 
-static struct class *class_get(struct class *cls)
-{
-	if (cls)
-		kset_get(&cls->p->subsys);
-	return cls;
-}
+	if (!sp)
+		return;
 
-static void class_put(struct class *cls)
-{
-	if (cls)
-		kset_put(&cls->p->subsys);
+	sysfs_remove_file_ns(&sp->subsys.kobj, &attr->attr, ns);
+	subsys_put(sp);
 }
+EXPORT_SYMBOL_GPL(class_remove_file_ns);
 
 static struct device *klist_class_to_dev(struct klist_node *n)
 {
@@ -138,72 +175,77 @@ static void klist_class_dev_put(struct klist_node *n)
 	put_device(dev);
 }
 
-static int class_add_groups(struct class *cls,
-			    const struct attribute_group **groups)
-{
-	return sysfs_create_groups(&cls->p->subsys.kobj, groups);
-}
-
-static void class_remove_groups(struct class *cls,
-				const struct attribute_group **groups)
-{
-	return sysfs_remove_groups(&cls->p->subsys.kobj, groups);
-}
-
-int __class_register(struct class *cls, struct lock_class_key *key)
+int class_register(const struct class *cls)
 {
 	struct subsys_private *cp;
+	struct lock_class_key *key;
 	int error;
 
 	pr_debug("device class '%s': registering\n", cls->name);
 
+	if (cls->ns_type && !cls->namespace) {
+		pr_err("%s: class '%s' does not have namespace\n",
+		       __func__, cls->name);
+		return -EINVAL;
+	}
+	if (!cls->ns_type && cls->namespace) {
+		pr_err("%s: class '%s' does not have ns_type\n",
+		       __func__, cls->name);
+		return -EINVAL;
+	}
+
 	cp = kzalloc(sizeof(*cp), GFP_KERNEL);
 	if (!cp)
 		return -ENOMEM;
 	klist_init(&cp->klist_devices, klist_class_dev_get, klist_class_dev_put);
 	INIT_LIST_HEAD(&cp->interfaces);
 	kset_init(&cp->glue_dirs);
+	key = &cp->lock_key;
+	lockdep_register_key(key);
 	__mutex_init(&cp->mutex, "subsys mutex", key);
 	error = kobject_set_name(&cp->subsys.kobj, "%s", cls->name);
-	if (error) {
-		kfree(cp);
-		return error;
-	}
-
-	/* set the default /sys/dev directory for devices of this class */
-	if (!cls->dev_kobj)
-		cls->dev_kobj = sysfs_dev_char_kobj;
+	if (error)
+		goto err_out;
 
-#if defined(CONFIG_BLOCK)
-	/* let the block class directory show up in the root of sysfs */
-	if (!sysfs_deprecated || cls != &block_class)
-		cp->subsys.kobj.kset = class_kset;
-#else
 	cp->subsys.kobj.kset = class_kset;
-#endif
 	cp->subsys.kobj.ktype = &class_ktype;
 	cp->class = cls;
-	cls->p = cp;
 
 	error = kset_register(&cp->subsys);
+	if (error)
+		goto err_out;
+
+	error = sysfs_create_groups(&cp->subsys.kobj, cls->class_groups);
 	if (error) {
-		kfree(cp);
-		return error;
+		kobject_del(&cp->subsys.kobj);
+		kfree_const(cp->subsys.kobj.name);
+		goto err_out;
 	}
-	error = class_add_groups(class_get(cls), cls->class_groups);
-	class_put(cls);
+	return 0;
+
+err_out:
+	lockdep_unregister_key(key);
+	kfree(cp);
 	return error;
 }
-EXPORT_SYMBOL_GPL(__class_register);
+EXPORT_SYMBOL_GPL(class_register);
 
-void class_unregister(struct class *cls)
+void class_unregister(const struct class *cls)
 {
+	struct subsys_private *sp = class_to_subsys(cls);
+
+	if (!sp)
+		return;
+
 	pr_debug("device class '%s': unregistering\n", cls->name);
-	class_remove_groups(cls, cls->class_groups);
-	kset_unregister(&cls->p->subsys);
+
+	sysfs_remove_groups(&sp->subsys.kobj, cls->class_groups);
+	kset_unregister(&sp->subsys);
+	subsys_put(sp);
 }
+EXPORT_SYMBOL_GPL(class_unregister);
 
-static void class_create_release(struct class *cls)
+static void class_create_release(const struct class *cls)
 {
 	pr_debug("%s called for %s\n", __func__, cls->name);
 	kfree(cls);
@@ -211,9 +253,7 @@ static void class_create_release(struct class *cls)
 
 /**
  * class_create - create a struct class structure
- * @owner: pointer to the module that is to "own" this struct class
  * @name: pointer to a string for the name of this class.
- * @key: the lock_class_key for this class; used by mutex lock debugging
  *
  * This is used to create a struct class pointer that can then be used
  * in calls to device_create().
@@ -223,8 +263,7 @@ static void class_create_release(struct class *cls)
  * Note, the pointer created here is to be destroyed when finished by
  * making a call to class_destroy().
  */
-struct class *__class_create(struct module *owner, const char *name,
-			     struct lock_class_key *key)
+struct class *class_create(const char *name)
 {
 	struct class *cls;
 	int retval;
@@ -236,10 +275,9 @@ struct class *__class_create(struct module *owner, const char *name,
 	}
 
 	cls->name = name;
-	cls->owner = owner;
 	cls->class_release = class_create_release;
 
-	retval = __class_register(cls, key);
+	retval = class_register(cls);
 	if (retval)
 		goto error;
 
@@ -249,7 +287,7 @@ error:
 	kfree(cls);
 	return ERR_PTR(retval);
 }
-EXPORT_SYMBOL_GPL(__class_create);
+EXPORT_SYMBOL_GPL(class_create);
 
 /**
  * class_destroy - destroys a struct class structure
@@ -258,13 +296,14 @@ EXPORT_SYMBOL_GPL(__class_create);
  * Note, the pointer to be destroyed must have been created with a call
  * to class_create().
  */
-void class_destroy(struct class *cls)
+void class_destroy(const struct class *cls)
 {
-	if ((cls == NULL) || (IS_ERR(cls)))
+	if (IS_ERR_OR_NULL(cls))
 		return;
 
 	class_unregister(cls);
 }
+EXPORT_SYMBOL_GPL(class_destroy);
 
 /**
  * class_dev_iter_init - initialize class device iterator
@@ -278,15 +317,24 @@ void class_destroy(struct class *cls)
  * otherwise if it is NULL, the iteration starts at the beginning of
  * the list.
  */
-void class_dev_iter_init(struct class_dev_iter *iter, struct class *class,
-			 struct device *start, const struct device_type *type)
+void class_dev_iter_init(struct class_dev_iter *iter, const struct class *class,
+			 const struct device *start, const struct device_type *type)
 {
+	struct subsys_private *sp = class_to_subsys(class);
 	struct klist_node *start_knode = NULL;
 
+	memset(iter, 0, sizeof(*iter));
+	if (!sp) {
+		pr_crit("%s: class %p was not registered yet\n",
+			__func__, class);
+		return;
+	}
+
 	if (start)
 		start_knode = &start->p->knode_class;
-	klist_iter_init_node(&class->p->klist_devices, &iter->ki, start_knode);
+	klist_iter_init_node(&sp->klist_devices, &iter->ki, start_knode);
 	iter->type = type;
+	iter->sp = sp;
 }
 EXPORT_SYMBOL_GPL(class_dev_iter_init);
 
@@ -307,6 +355,9 @@ struct device *class_dev_iter_next(struct class_dev_iter *iter)
 	struct klist_node *knode;
 	struct device *dev;
 
+	if (!iter->sp)
+		return NULL;
+
 	while (1) {
 		knode = klist_next(&iter->ki);
 		if (!knode)
@@ -328,6 +379,7 @@ EXPORT_SYMBOL_GPL(class_dev_iter_next);
 void class_dev_iter_exit(struct class_dev_iter *iter)
 {
 	klist_iter_exit(&iter->ki);
+	subsys_put(iter->sp);
 }
 EXPORT_SYMBOL_GPL(class_dev_iter_exit);
 
@@ -349,17 +401,18 @@ EXPORT_SYMBOL_GPL(class_dev_iter_exit);
  * @fn is allowed to do anything including calling back into class
  * code.  There's no locking restriction.
  */
-int class_for_each_device(struct class *class, struct device *start,
-			  void *data, int (*fn)(struct device *, void *))
+int class_for_each_device(const struct class *class, const struct device *start,
+			  void *data, device_iter_t fn)
 {
+	struct subsys_private *sp = class_to_subsys(class);
 	struct class_dev_iter iter;
 	struct device *dev;
 	int error = 0;
 
 	if (!class)
 		return -EINVAL;
-	if (!class->p) {
-		WARN(1, "%s called for class '%s' before it was initialized",
+	if (!sp) {
+		WARN(1, "%s called for class '%s' before it was registered",
 		     __func__, class->name);
 		return -EINVAL;
 	}
@@ -371,6 +424,7 @@ int class_for_each_device(struct class *class, struct device *start,
 			break;
 	}
 	class_dev_iter_exit(&iter);
+	subsys_put(sp);
 
 	return error;
 }
@@ -396,17 +450,17 @@ EXPORT_SYMBOL_GPL(class_for_each_device);
  * @match is allowed to do anything including calling back into class
  * code.  There's no locking restriction.
  */
-struct device *class_find_device(struct class *class, struct device *start,
-				 const void *data,
-				 int (*match)(struct device *, const void *))
+struct device *class_find_device(const struct class *class, const struct device *start,
+				 const void *data, device_match_t match)
 {
+	struct subsys_private *sp = class_to_subsys(class);
 	struct class_dev_iter iter;
 	struct device *dev;
 
 	if (!class)
 		return NULL;
-	if (!class->p) {
-		WARN(1, "%s called for class '%s' before it was initialized",
+	if (!sp) {
+		WARN(1, "%s called for class '%s' before it was registered",
 		     __func__, class->name);
 		return NULL;
 	}
@@ -419,6 +473,7 @@ struct device *class_find_device(struct class *class, struct device *start,
 		}
 	}
 	class_dev_iter_exit(&iter);
+	subsys_put(sp);
 
 	return dev;
 }
@@ -426,59 +481,79 @@ EXPORT_SYMBOL_GPL(class_find_device);
 
 int class_interface_register(struct class_interface *class_intf)
 {
-	struct class *parent;
+	struct subsys_private *sp;
+	const struct class *parent;
 	struct class_dev_iter iter;
 	struct device *dev;
 
 	if (!class_intf || !class_intf->class)
 		return -ENODEV;
 
-	parent = class_get(class_intf->class);
-	if (!parent)
+	parent = class_intf->class;
+	sp = class_to_subsys(parent);
+	if (!sp)
 		return -EINVAL;
 
-	mutex_lock(&parent->p->mutex);
-	list_add_tail(&class_intf->node, &parent->p->interfaces);
+	/*
+	 * Reference in sp is now incremented and will be dropped when
+	 * the interface is removed in the call to class_interface_unregister()
+	 */
+
+	mutex_lock(&sp->mutex);
+	list_add_tail(&class_intf->node, &sp->interfaces);
 	if (class_intf->add_dev) {
 		class_dev_iter_init(&iter, parent, NULL, NULL);
 		while ((dev = class_dev_iter_next(&iter)))
-			class_intf->add_dev(dev, class_intf);
+			class_intf->add_dev(dev);
 		class_dev_iter_exit(&iter);
 	}
-	mutex_unlock(&parent->p->mutex);
+	mutex_unlock(&sp->mutex);
 
 	return 0;
 }
+EXPORT_SYMBOL_GPL(class_interface_register);
 
 void class_interface_unregister(struct class_interface *class_intf)
 {
-	struct class *parent = class_intf->class;
+	struct subsys_private *sp;
+	const struct class *parent = class_intf->class;
 	struct class_dev_iter iter;
 	struct device *dev;
 
 	if (!parent)
 		return;
 
-	mutex_lock(&parent->p->mutex);
+	sp = class_to_subsys(parent);
+	if (!sp)
+		return;
+
+	mutex_lock(&sp->mutex);
 	list_del_init(&class_intf->node);
 	if (class_intf->remove_dev) {
 		class_dev_iter_init(&iter, parent, NULL, NULL);
 		while ((dev = class_dev_iter_next(&iter)))
-			class_intf->remove_dev(dev, class_intf);
+			class_intf->remove_dev(dev);
 		class_dev_iter_exit(&iter);
 	}
-	mutex_unlock(&parent->p->mutex);
+	mutex_unlock(&sp->mutex);
 
-	class_put(parent);
+	/*
+	 * Decrement the reference count twice, once for the class_to_subsys()
+	 * call in the start of this function, and the second one from the
+	 * reference increment in class_interface_register()
+	 */
+	subsys_put(sp);
+	subsys_put(sp);
 }
+EXPORT_SYMBOL_GPL(class_interface_unregister);
 
-ssize_t show_class_attr_string(struct class *class,
-			       struct class_attribute *attr, char *buf)
+ssize_t show_class_attr_string(const struct class *class,
+			       const struct class_attribute *attr, char *buf)
 {
 	struct class_attribute_string *cs;
 
 	cs = container_of(attr, struct class_attribute_string, attr);
-	return snprintf(buf, PAGE_SIZE, "%s\n", cs->str);
+	return sysfs_emit(buf, "%s\n", cs->str);
 }
 
 EXPORT_SYMBOL_GPL(show_class_attr_string);
@@ -526,30 +601,10 @@ EXPORT_SYMBOL_GPL(class_compat_unregister);
  *			      a bus device
  * @cls: the compatibility class
  * @dev: the target bus device
- * @device_link: an optional device to which a "device" link should be created
  */
-int class_compat_create_link(struct class_compat *cls, struct device *dev,
-			     struct device *device_link)
+int class_compat_create_link(struct class_compat *cls, struct device *dev)
 {
-	int error;
-
-	error = sysfs_create_link(cls->kobj, &dev->kobj, dev_name(dev));
-	if (error)
-		return error;
-
-	/*
-	 * Optionally add a "device" link (typically to the parent), as a
-	 * class device would have one and we want to provide as much
-	 * backwards compatibility as possible.
-	 */
-	if (device_link) {
-		error = sysfs_create_link(&dev->kobj, &device_link->kobj,
-					  "device");
-		if (error)
-			sysfs_remove_link(cls->kobj, dev_name(dev));
-	}
-
-	return error;
+	return sysfs_create_link(cls->kobj, &dev->kobj, dev_name(dev));
 }
 EXPORT_SYMBOL_GPL(class_compat_create_link);
 
@@ -558,18 +613,38 @@ EXPORT_SYMBOL_GPL(class_compat_create_link);
  *			      a bus device
  * @cls: the compatibility class
  * @dev: the target bus device
- * @device_link: an optional device to which a "device" link was previously
- * 		 created
  */
-void class_compat_remove_link(struct class_compat *cls, struct device *dev,
-			      struct device *device_link)
+void class_compat_remove_link(struct class_compat *cls, struct device *dev)
 {
-	if (device_link)
-		sysfs_remove_link(&dev->kobj, "device");
 	sysfs_remove_link(cls->kobj, dev_name(dev));
 }
 EXPORT_SYMBOL_GPL(class_compat_remove_link);
 
+/**
+ * class_is_registered - determine if at this moment in time, a class is
+ *			 registered in the driver core or not.
+ * @class: the class to check
+ *
+ * Returns a boolean to state if the class is registered in the driver core
+ * or not.  Note that the value could switch right after this call is made,
+ * so only use this in places where you "know" it is safe to do so (usually
+ * to determine if the specific class has been registered yet or not).
+ *
+ * Be careful in using this.
+ */
+bool class_is_registered(const struct class *class)
+{
+	struct subsys_private *sp = class_to_subsys(class);
+	bool is_initialized = false;
+
+	if (sp) {
+		is_initialized = true;
+		subsys_put(sp);
+	}
+	return is_initialized;
+}
+EXPORT_SYMBOL_GPL(class_is_registered);
+
 int __init classes_init(void)
 {
 	class_kset = kset_create_and_add("class", NULL, NULL);
@@ -577,11 +652,3 @@ int __init classes_init(void)
 		return -ENOMEM;
 	return 0;
 }
-
-EXPORT_SYMBOL_GPL(class_create_file_ns);
-EXPORT_SYMBOL_GPL(class_remove_file_ns);
-EXPORT_SYMBOL_GPL(class_unregister);
-EXPORT_SYMBOL_GPL(class_destroy);
-
-EXPORT_SYMBOL_GPL(class_interface_register);
-EXPORT_SYMBOL_GPL(class_interface_unregister);
diff --git a/drivers/base/component.c b/drivers/base/component.c
index e97704104784..024ad9471b8a 100644
--- a/drivers/base/component.c
+++ b/drivers/base/component.c
@@ -1,17 +1,12 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
  * Componentized device handling.
- *
- * This is work in progress.  We gather up the component devices into a list,
- * and bind them when instructed.  At the moment, we're specific to the DRM
- * subsystem, and only handles one master device, but this doesn't have to be
- * the case.
  */
 #include <linux/component.h>
 #include <linux/device.h>
-#include <linux/kref.h>
 #include <linux/list.h>
 #include <linux/mutex.h>
+#include <linux/of.h>
 #include <linux/slab.h>
 #include <linux/debugfs.h>
 
@@ -58,19 +53,18 @@ struct component_match {
 	struct component_match_array *compare;
 };
 
-struct master {
+struct aggregate_device {
 	struct list_head node;
 	bool bound;
 
 	const struct component_master_ops *ops;
-	struct device *dev;
+	struct device *parent;
 	struct component_match *match;
-	struct dentry *dentry;
 };
 
 struct component {
 	struct list_head node;
-	struct master *master;
+	struct aggregate_device *adev;
 	bool bound;
 
 	const struct component_ops *ops;
@@ -80,7 +74,7 @@ struct component {
 
 static DEFINE_MUTEX(component_mutex);
 static LIST_HEAD(component_list);
-static LIST_HEAD(masters);
+static LIST_HEAD(aggregate_devices);
 
 #ifdef CONFIG_DEBUG_FS
 
@@ -88,22 +82,22 @@ static struct dentry *component_debugfs_dir;
 
 static int component_devices_show(struct seq_file *s, void *data)
 {
-	struct master *m = s->private;
+	struct aggregate_device *m = s->private;
 	struct component_match *match = m->match;
 	size_t i;
 
 	mutex_lock(&component_mutex);
-	seq_printf(s, "%-40s %20s\n", "master name", "status");
-	seq_puts(s, "-------------------------------------------------------------\n");
-	seq_printf(s, "%-40s %20s\n\n",
-		   dev_name(m->dev), m->bound ? "bound" : "not bound");
+	seq_printf(s, "%-50s %20s\n", "aggregate_device name", "status");
+	seq_puts(s, "-----------------------------------------------------------------------\n");
+	seq_printf(s, "%-50s %20s\n\n",
+		   dev_name(m->parent), m->bound ? "bound" : "not bound");
 
-	seq_printf(s, "%-40s %20s\n", "device name", "status");
-	seq_puts(s, "-------------------------------------------------------------\n");
+	seq_printf(s, "%-50s %20s\n", "device name", "status");
+	seq_puts(s, "-----------------------------------------------------------------------\n");
 	for (i = 0; i < match->num; i++) {
 		struct component *component = match->compare[i].component;
 
-		seq_printf(s, "%-40s %20s\n",
+		seq_printf(s, "%-50s %20s\n",
 			   component ? dev_name(component->dev) : "(unknown)",
 			   component ? (component->bound ? "bound" : "not bound") : "not registered");
 	}
@@ -123,48 +117,46 @@ static int __init component_debug_init(void)
 
 core_initcall(component_debug_init);
 
-static void component_master_debugfs_add(struct master *m)
+static void component_debugfs_add(struct aggregate_device *m)
 {
-	m->dentry = debugfs_create_file(dev_name(m->dev), 0444,
-					component_debugfs_dir,
-					m, &component_devices_fops);
+	debugfs_create_file(dev_name(m->parent), 0444, component_debugfs_dir, m,
+			    &component_devices_fops);
 }
 
-static void component_master_debugfs_del(struct master *m)
+static void component_debugfs_del(struct aggregate_device *m)
 {
-	debugfs_remove(m->dentry);
-	m->dentry = NULL;
+	debugfs_lookup_and_remove(dev_name(m->parent), component_debugfs_dir);
 }
 
 #else
 
-static void component_master_debugfs_add(struct master *m)
+static void component_debugfs_add(struct aggregate_device *m)
 { }
 
-static void component_master_debugfs_del(struct master *m)
+static void component_debugfs_del(struct aggregate_device *m)
 { }
 
 #endif
 
-static struct master *__master_find(struct device *dev,
+static struct aggregate_device *__aggregate_find(struct device *parent,
 	const struct component_master_ops *ops)
 {
-	struct master *m;
+	struct aggregate_device *m;
 
-	list_for_each_entry(m, &masters, node)
-		if (m->dev == dev && (!ops || m->ops == ops))
+	list_for_each_entry(m, &aggregate_devices, node)
+		if (m->parent == parent && (!ops || m->ops == ops))
 			return m;
 
 	return NULL;
 }
 
-static struct component *find_component(struct master *master,
+static struct component *find_component(struct aggregate_device *adev,
 	struct component_match_array *mc)
 {
 	struct component *c;
 
 	list_for_each_entry(c, &component_list, node) {
-		if (c->master && c->master != master)
+		if (c->adev && c->adev != adev)
 			continue;
 
 		if (mc->compare && mc->compare(c->dev, mc->data))
@@ -178,100 +170,103 @@ static struct component *find_component(struct master *master,
 	return NULL;
 }
 
-static int find_components(struct master *master)
+static int find_components(struct aggregate_device *adev)
 {
-	struct component_match *match = master->match;
+	struct component_match *match = adev->match;
 	size_t i;
 	int ret = 0;
 
 	/*
 	 * Scan the array of match functions and attach
-	 * any components which are found to this master.
+	 * any components which are found to this adev.
 	 */
 	for (i = 0; i < match->num; i++) {
 		struct component_match_array *mc = &match->compare[i];
 		struct component *c;
 
-		dev_dbg(master->dev, "Looking for component %zu\n", i);
+		dev_dbg(adev->parent, "Looking for component %zu\n", i);
 
 		if (match->compare[i].component)
 			continue;
 
-		c = find_component(master, mc);
+		c = find_component(adev, mc);
 		if (!c) {
 			ret = -ENXIO;
 			break;
 		}
 
-		dev_dbg(master->dev, "found component %s, duplicate %u\n", dev_name(c->dev), !!c->master);
+		dev_dbg(adev->parent, "found component %s, duplicate %u\n",
+			dev_name(c->dev), !!c->adev);
 
-		/* Attach this component to the master */
-		match->compare[i].duplicate = !!c->master;
+		/* Attach this component to the adev */
+		match->compare[i].duplicate = !!c->adev;
 		match->compare[i].component = c;
-		c->master = master;
+		c->adev = adev;
 	}
 	return ret;
 }
 
-/* Detach component from associated master */
-static void remove_component(struct master *master, struct component *c)
+/* Detach component from associated aggregate_device */
+static void remove_component(struct aggregate_device *adev, struct component *c)
 {
 	size_t i;
 
-	/* Detach the component from this master. */
-	for (i = 0; i < master->match->num; i++)
-		if (master->match->compare[i].component == c)
-			master->match->compare[i].component = NULL;
+	/* Detach the component from this adev. */
+	for (i = 0; i < adev->match->num; i++)
+		if (adev->match->compare[i].component == c)
+			adev->match->compare[i].component = NULL;
 }
 
 /*
- * Try to bring up a master.  If component is NULL, we're interested in
- * this master, otherwise it's a component which must be present to try
- * and bring up the master.
+ * Try to bring up an aggregate device.  If component is NULL, we're interested
+ * in this aggregate device, otherwise it's a component which must be present
+ * to try and bring up the aggregate device.
  *
  * Returns 1 for successful bringup, 0 if not ready, or -ve errno.
  */
-static int try_to_bring_up_master(struct master *master,
+static int try_to_bring_up_aggregate_device(struct aggregate_device *adev,
 	struct component *component)
 {
 	int ret;
 
-	dev_dbg(master->dev, "trying to bring up master\n");
+	dev_dbg(adev->parent, "trying to bring up adev\n");
 
-	if (find_components(master)) {
-		dev_dbg(master->dev, "master has incomplete components\n");
+	if (find_components(adev)) {
+		dev_dbg(adev->parent, "master has incomplete components\n");
 		return 0;
 	}
 
-	if (component && component->master != master) {
-		dev_dbg(master->dev, "master is not for this component (%s)\n",
+	if (component && component->adev != adev) {
+		dev_dbg(adev->parent, "master is not for this component (%s)\n",
 			dev_name(component->dev));
 		return 0;
 	}
 
-	if (!devres_open_group(master->dev, NULL, GFP_KERNEL))
+	if (!devres_open_group(adev->parent, adev, GFP_KERNEL))
 		return -ENOMEM;
 
 	/* Found all components */
-	ret = master->ops->bind(master->dev);
+	ret = adev->ops->bind(adev->parent);
 	if (ret < 0) {
-		devres_release_group(master->dev, NULL);
-		dev_info(master->dev, "master bind failed: %d\n", ret);
+		devres_release_group(adev->parent, NULL);
+		if (ret != -EPROBE_DEFER)
+			dev_info(adev->parent, "adev bind failed: %d\n", ret);
 		return ret;
 	}
 
-	master->bound = true;
+	devres_close_group(adev->parent, NULL);
+	adev->bound = true;
 	return 1;
 }
 
 static int try_to_bring_up_masters(struct component *component)
 {
-	struct master *m;
+	struct aggregate_device *adev;
 	int ret = 0;
 
-	list_for_each_entry(m, &masters, node) {
-		if (!m->bound) {
-			ret = try_to_bring_up_master(m, component);
+	list_for_each_entry(adev, &aggregate_devices, node) {
+		if (!adev->bound) {
+			ret = try_to_bring_up_aggregate_device(adev, component);
 			if (ret != 0)
 				break;
 		}
@@ -280,37 +275,88 @@ static int try_to_bring_up_masters(struct component *component)
 	return ret;
 }
 
-static void take_down_master(struct master *master)
+static void take_down_aggregate_device(struct aggregate_device *adev)
 {
-	if (master->bound) {
-		master->ops->unbind(master->dev);
-		devres_release_group(master->dev, NULL);
-		master->bound = false;
+	if (adev->bound) {
+		adev->ops->unbind(adev->parent);
+		devres_release_group(adev->parent, adev);
+		adev->bound = false;
 	}
 }
 
-static void component_match_release(struct device *master,
-	struct component_match *match)
+/**
+ * component_compare_of - A common component compare function for of_node
+ * @dev: component device
+ * @data: @compare_data from component_match_add_release()
+ *
+ * A common compare function when compare_data is device of_node. e.g.
+ * component_match_add_release(masterdev, &match, component_release_of,
+ * component_compare_of, component_dev_of_node)
+ */
+int component_compare_of(struct device *dev, void *data)
+{
+	return device_match_of_node(dev, data);
+}
+EXPORT_SYMBOL_GPL(component_compare_of);
+
+/**
+ * component_release_of - A common component release function for of_node
+ * @dev: component device
+ * @data: @compare_data from component_match_add_release()
+ *
+ * About the example, Please see component_compare_of().
+ */
+void component_release_of(struct device *dev, void *data)
 {
+	of_node_put(data);
+}
+EXPORT_SYMBOL_GPL(component_release_of);
+
+/**
+ * component_compare_dev - A common component compare function for dev
+ * @dev: component device
+ * @data: @compare_data from component_match_add_release()
+ *
+ * A common compare function when compare_data is struce device. e.g.
+ * component_match_add(masterdev, &match, component_compare_dev, component_dev)
+ */
+int component_compare_dev(struct device *dev, void *data)
+{
+	return dev == data;
+}
+EXPORT_SYMBOL_GPL(component_compare_dev);
+
+/**
+ * component_compare_dev_name - A common component compare function for device name
+ * @dev: component device
+ * @data: @compare_data from component_match_add_release()
+ *
+ * A common compare function when compare_data is device name string. e.g.
+ * component_match_add(masterdev, &match, component_compare_dev_name,
+ * "component_dev_name")
+ */
+int component_compare_dev_name(struct device *dev, void *data)
+{
+	return device_match_name(dev, data);
+}
+EXPORT_SYMBOL_GPL(component_compare_dev_name);
+
+static void devm_component_match_release(struct device *parent, void *res)
+{
+	struct component_match *match = res;
 	unsigned int i;
 
 	for (i = 0; i < match->num; i++) {
 		struct component_match_array *mc = &match->compare[i];
 
 		if (mc->release)
-			mc->release(master, mc->data);
+			mc->release(parent, mc->data);
 	}
 
 	kfree(match->compare);
 }
 
-static void devm_component_match_release(struct device *dev, void *res)
-{
-	component_match_release(dev, res);
-}
-
-static int component_match_realloc(struct device *dev,
-	struct component_match *match, size_t num)
+static int component_match_realloc(struct component_match *match, size_t num)
 {
 	struct component_match_array *new;
 
@@ -332,7 +378,7 @@ static int component_match_realloc(struct device *dev,
 	return 0;
 }
 
-static void __component_match_add(struct device *master,
+static void __component_match_add(struct device *parent,
 	struct component_match **matchptr,
 	void (*release)(struct device *, void *),
 	int (*compare)(struct device *, void *),
@@ -352,7 +398,7 @@ static void __component_match_add(struct device *master,
 			return;
 		}
 
-		devres_add(master, match);
+		devres_add(parent, match);
 
 		*matchptr = match;
 	}
@@ -361,7 +407,7 @@ static void __component_match_add(struct device *master,
 		size_t new_size = match->alloc + 16;
 		int ret;
 
-		ret = component_match_realloc(master, match, new_size);
+		ret = component_match_realloc(match, new_size);
 		if (ret) {
 			*matchptr = ERR_PTR(ret);
 			return;
@@ -378,13 +424,13 @@ static void __component_match_add(struct device *master,
 
 /**
  * component_match_add_release - add a component match entry with release callback
- * @master: device with the aggregate driver
+ * @parent: parent device of the aggregate driver
  * @matchptr: pointer to the list of component matches
  * @release: release function for @compare_data
  * @compare: compare function to match against all components
  * @compare_data: opaque pointer passed to the @compare function
  *
- * Adds a new component match to the list stored in @matchptr, which the @master
+ * Adds a new component match to the list stored in @matchptr, which the
  * aggregate driver needs to function. The list of component matches pointed to
  * by @matchptr must be initialized to NULL before adding the first match. This
  * only matches against components added with component_add().
@@ -396,24 +442,24 @@ static void __component_match_add(struct device *master,
  *
  * See also component_match_add() and component_match_add_typed().
  */
-void component_match_add_release(struct device *master,
+void component_match_add_release(struct device *parent,
 	struct component_match **matchptr,
 	void (*release)(struct device *, void *),
 	int (*compare)(struct device *, void *), void *compare_data)
 {
-	__component_match_add(master, matchptr, release, compare, NULL,
+	__component_match_add(parent, matchptr, release, compare, NULL,
 			      compare_data);
 }
 EXPORT_SYMBOL(component_match_add_release);
 
 /**
  * component_match_add_typed - add a component match entry for a typed component
- * @master: device with the aggregate driver
+ * @parent: parent device of the aggregate driver
  * @matchptr: pointer to the list of component matches
  * @compare_typed: compare function to match against all typed components
  * @compare_data: opaque pointer passed to the @compare function
  *
- * Adds a new component match to the list stored in @matchptr, which the @master
+ * Adds a new component match to the list stored in @matchptr, which the
  * aggregate driver needs to function. The list of component matches pointed to
  * by @matchptr must be initialized to NULL before adding the first match. This
  * only matches against components added with component_add_typed().
@@ -423,37 +469,37 @@ EXPORT_SYMBOL(component_match_add_release);
  *
  * See also component_match_add_release() and component_match_add_typed().
  */
-void component_match_add_typed(struct device *master,
+void component_match_add_typed(struct device *parent,
 	struct component_match **matchptr,
 	int (*compare_typed)(struct device *, int, void *), void *compare_data)
 {
-	__component_match_add(master, matchptr, NULL, NULL, compare_typed,
+	__component_match_add(parent, matchptr, NULL, NULL, compare_typed,
 			      compare_data);
 }
 EXPORT_SYMBOL(component_match_add_typed);
 
-static void free_master(struct master *master)
+static void free_aggregate_device(struct aggregate_device *adev)
 {
-	struct component_match *match = master->match;
+	struct component_match *match = adev->match;
 	int i;
 
-	component_master_debugfs_del(master);
-	list_del(&master->node);
+	component_debugfs_del(adev);
+	list_del(&adev->node);
 
 	if (match) {
 		for (i = 0; i < match->num; i++) {
 			struct component *c = match->compare[i].component;
 			if (c)
-				c->master = NULL;
+				c->adev = NULL;
 		}
 	}
 
-	kfree(master);
+	kfree(adev);
 }
 
 /**
  * component_master_add_with_match - register an aggregate driver
- * @dev: device with the aggregate driver
+ * @parent: parent device of the aggregate driver
  * @ops: callbacks for the aggregate driver
  * @match: component match list for the aggregate driver
  *
@@ -463,35 +509,35 @@ static void free_master(struct master *master)
  * &component_master_ops.bind from @ops. Must be unregistered by calling
  * component_master_del().
  */
-int component_master_add_with_match(struct device *dev,
+int component_master_add_with_match(struct device *parent,
 	const struct component_master_ops *ops,
 	struct component_match *match)
 {
-	struct master *master;
+	struct aggregate_device *adev;
 	int ret;
 
 	/* Reallocate the match array for its true size */
-	ret = component_match_realloc(dev, match, match->num);
+	ret = component_match_realloc(match, match->num);
 	if (ret)
 		return ret;
 
-	master = kzalloc(sizeof(*master), GFP_KERNEL);
-	if (!master)
+	adev = kzalloc(sizeof(*adev), GFP_KERNEL);
+	if (!adev)
 		return -ENOMEM;
 
-	master->dev = dev;
-	master->ops = ops;
-	master->match = match;
+	adev->parent = parent;
+	adev->ops = ops;
+	adev->match = match;
 
-	component_master_debugfs_add(master);
-	/* Add to the list of available masters. */
+	component_debugfs_add(adev);
+	/* Add to the list of available aggregate devices. */
 	mutex_lock(&component_mutex);
-	list_add(&master->node, &masters);
+	list_add(&adev->node, &aggregate_devices);
 
-	ret = try_to_bring_up_master(master, NULL);
+	ret = try_to_bring_up_aggregate_device(adev, NULL);
 
 	if (ret < 0)
-		free_master(master);
+		free_aggregate_device(adev);
 
 	mutex_unlock(&component_mutex);
 
@@ -501,35 +547,53 @@ EXPORT_SYMBOL_GPL(component_master_add_with_match);
 
 /**
  * component_master_del - unregister an aggregate driver
- * @dev: device with the aggregate driver
+ * @parent: parent device of the aggregate driver
  * @ops: callbacks for the aggregate driver
  *
  * Unregisters an aggregate driver registered with
  * component_master_add_with_match(). If necessary the aggregate driver is first
  * disassembled by calling &component_master_ops.unbind from @ops.
  */
-void component_master_del(struct device *dev,
+void component_master_del(struct device *parent,
 	const struct component_master_ops *ops)
 {
-	struct master *master;
+	struct aggregate_device *adev;
 
 	mutex_lock(&component_mutex);
-	master = __master_find(dev, ops);
-	if (master) {
-		take_down_master(master);
-		free_master(master);
+	adev = __aggregate_find(parent, ops);
+	if (adev) {
+		take_down_aggregate_device(adev);
+		free_aggregate_device(adev);
 	}
 	mutex_unlock(&component_mutex);
 }
 EXPORT_SYMBOL_GPL(component_master_del);
 
+bool component_master_is_bound(struct device *parent,
+	const struct component_master_ops *ops)
+{
+	struct aggregate_device *adev;
+
+	guard(mutex)(&component_mutex);
+	adev = __aggregate_find(parent, ops);
+	if (!adev)
+		return 0;
+
+	return adev->bound;
+}
+EXPORT_SYMBOL_GPL(component_master_is_bound);
+
 static void component_unbind(struct component *component,
-	struct master *master, void *data)
+	struct aggregate_device *adev, void *data)
 {
-	WARN_ON(!component->bound);
+	if (WARN_ON(!component->bound))
+		return;
+
+	dev_dbg(adev->parent, "unbinding %s component %p (ops %ps)\n",
+		dev_name(component->dev), component, component->ops);
 
 	if (component->ops && component->ops->unbind)
-		component->ops->unbind(component->dev, master->dev, data);
+		component->ops->unbind(component->dev, adev->parent, data);
 	component->bound = false;
 
 	/* Release all resources claimed in the binding of this component */
@@ -538,35 +602,35 @@ static void component_unbind(struct component *component,
 
 /**
  * component_unbind_all - unbind all components of an aggregate driver
- * @master_dev: device with the aggregate driver
+ * @parent: parent device of the aggregate driver
  * @data: opaque pointer, passed to all components
  *
- * Unbinds all components of the aggregate @dev by passing @data to their
+ * Unbinds all components of the aggregate device by passing @data to their
  * &component_ops.unbind functions. Should be called from
  * &component_master_ops.unbind.
  */
-void component_unbind_all(struct device *master_dev, void *data)
+void component_unbind_all(struct device *parent, void *data)
 {
-	struct master *master;
+	struct aggregate_device *adev;
 	struct component *c;
 	size_t i;
 
 	WARN_ON(!mutex_is_locked(&component_mutex));
 
-	master = __master_find(master_dev, NULL);
-	if (!master)
+	adev = __aggregate_find(parent, NULL);
+	if (!adev)
 		return;
 
 	/* Unbind components in reverse order */
-	for (i = master->match->num; i--; )
-		if (!master->match->compare[i].duplicate) {
-			c = master->match->compare[i].component;
-			component_unbind(c, master, data);
+	for (i = adev->match->num; i--; )
+		if (!adev->match->compare[i].duplicate) {
+			c = adev->match->compare[i].component;
+			component_unbind(c, adev, data);
 		}
 }
 EXPORT_SYMBOL_GPL(component_unbind_all);
 
-static int component_bind(struct component *component, struct master *master,
+static int component_bind(struct component *component, struct aggregate_device *adev,
 	void *data)
 {
 	int ret;
@@ -576,7 +640,7 @@ static int component_bind(struct component *component, struct master *master,
 	 * This allows us to roll-back a failed component without
 	 * affecting anything else.
 	 */
-	if (!devres_open_group(master->dev, NULL, GFP_KERNEL))
+	if (!devres_open_group(adev->parent, NULL, GFP_KERNEL))
 		return -ENOMEM;
 
 	/*
@@ -585,14 +649,14 @@ static int component_bind(struct component *component, struct master *master,
 	 * at the appropriate moment.
 	 */
 	if (!devres_open_group(component->dev, component, GFP_KERNEL)) {
-		devres_release_group(master->dev, NULL);
+		devres_release_group(adev->parent, NULL);
 		return -ENOMEM;
 	}
 
-	dev_dbg(master->dev, "binding %s (ops %ps)\n",
+	dev_dbg(adev->parent, "binding %s (ops %ps)\n",
 		dev_name(component->dev), component->ops);
 
-	ret = component->ops->bind(component->dev, master->dev, data);
+	ret = component->ops->bind(component->dev, adev->parent, data);
 	if (!ret) {
 		component->bound = true;
 
@@ -603,16 +667,17 @@ static int component_bind(struct component *component, struct master *master,
 		 * can clean those resources up independently.
 		 */
 		devres_close_group(component->dev, NULL);
-		devres_remove_group(master->dev, NULL);
+		devres_remove_group(adev->parent, NULL);
 
-		dev_info(master->dev, "bound %s (ops %ps)\n",
+		dev_info(adev->parent, "bound %s (ops %ps)\n",
 			 dev_name(component->dev), component->ops);
 	} else {
 		devres_release_group(component->dev, NULL);
-		devres_release_group(master->dev, NULL);
+		devres_release_group(adev->parent, NULL);
 
-		dev_err(master->dev, "failed to bind %s (ops %ps): %d\n",
-			dev_name(component->dev), component->ops, ret);
+		if (ret != -EPROBE_DEFER)
+			dev_err(adev->parent, "failed to bind %s (ops %ps): %d\n",
+				dev_name(component->dev), component->ops, ret);
 	}
 
 	return ret;
@@ -620,40 +685,40 @@ static int component_bind(struct component *component, struct master *master,
 
 /**
  * component_bind_all - bind all components of an aggregate driver
- * @master_dev: device with the aggregate driver
+ * @parent: parent device of the aggregate driver
  * @data: opaque pointer, passed to all components
  *
  * Binds all components of the aggregate @dev by passing @data to their
  * &component_ops.bind functions. Should be called from
  * &component_master_ops.bind.
  */
-int component_bind_all(struct device *master_dev, void *data)
+int component_bind_all(struct device *parent, void *data)
 {
-	struct master *master;
+	struct aggregate_device *adev;
 	struct component *c;
 	size_t i;
 	int ret = 0;
 
 	WARN_ON(!mutex_is_locked(&component_mutex));
 
-	master = __master_find(master_dev, NULL);
-	if (!master)
+	adev = __aggregate_find(parent, NULL);
+	if (!adev)
 		return -EINVAL;
 
 	/* Bind components in match order */
-	for (i = 0; i < master->match->num; i++)
-		if (!master->match->compare[i].duplicate) {
-			c = master->match->compare[i].component;
-			ret = component_bind(c, master, data);
+	for (i = 0; i < adev->match->num; i++)
+		if (!adev->match->compare[i].duplicate) {
+			c = adev->match->compare[i].component;
+			ret = component_bind(c, adev, data);
 			if (ret)
 				break;
 		}
 
 	if (ret != 0) {
 		for (; i > 0; i--)
-			if (!master->match->compare[i - 1].duplicate) {
-				c = master->match->compare[i - 1].component;
-				component_unbind(c, master, data);
+			if (!adev->match->compare[i - 1].duplicate) {
+				c = adev->match->compare[i - 1].component;
+				component_unbind(c, adev, data);
 			}
 	}
 
@@ -682,8 +747,8 @@ static int __component_add(struct device *dev, const struct component_ops *ops,
 
 	ret = try_to_bring_up_masters(component);
 	if (ret < 0) {
-		if (component->master)
-			remove_component(component->master, component);
+		if (component->adev)
+			remove_component(component->adev, component);
 		list_del(&component->node);
 
 		kfree(component);
@@ -704,7 +769,7 @@ static int __component_add(struct device *dev, const struct component_ops *ops,
  * component_bind_all(). See also &struct component_ops.
  *
  * @subcomponent must be nonzero and is used to differentiate between multiple
- * components registerd on the same device @dev. These components are match
+ * components registered on the same device @dev. These components are match
  * using component_match_add_typed().
  *
  * The component needs to be unregistered at driver unload/disconnect by
@@ -734,7 +799,7 @@ EXPORT_SYMBOL_GPL(component_add_typed);
  * The component needs to be unregistered at driver unload/disconnect by
  * calling component_del().
  *
- * See also component_add_typed() for a variant that allows multipled different
+ * See also component_add_typed() for a variant that allows multiple different
  * components on the same device.
  */
 int component_add(struct device *dev, const struct component_ops *ops)
@@ -764,9 +829,9 @@ void component_del(struct device *dev, const struct component_ops *ops)
 			break;
 		}
 
-	if (component && component->master) {
-		take_down_master(component->master);
-		remove_component(component->master, component);
+	if (component && component->adev) {
+		take_down_aggregate_device(component->adev);
+		remove_component(component->adev, component);
 	}
 
 	mutex_unlock(&component_mutex);
diff --git a/drivers/base/container.c b/drivers/base/container.c
index 1ba42d2d3532..f40588ebc3f5 100644
--- a/drivers/base/container.c
+++ b/drivers/base/container.c
@@ -24,7 +24,7 @@ static int container_offline(struct device *dev)
 	return cdev->offline ? cdev->offline(cdev) : 0;
 }
 
-struct bus_type container_subsys = {
+const struct bus_type container_subsys = {
 	.name = CONTAINER_BUS_NAME,
 	.dev_name = CONTAINER_BUS_NAME,
 	.online = trivial_online,
diff --git a/drivers/base/core.c b/drivers/base/core.c
index 139cdf7e7327..40de2f51a1b1 100644
--- a/drivers/base/core.c
+++ b/drivers/base/core.c
@@ -9,48 +9,232 @@
  */
 
 #include <linux/acpi.h>
+#include <linux/blkdev.h>
+#include <linux/cleanup.h>
 #include <linux/cpufreq.h>
 #include <linux/device.h>
+#include <linux/dma-map-ops.h> /* for dma_default_coherent */
 #include <linux/err.h>
 #include <linux/fwnode.h>
 #include <linux/init.h>
-#include <linux/module.h>
-#include <linux/slab.h>
-#include <linux/string.h>
 #include <linux/kdev_t.h>
+#include <linux/kstrtox.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/netdevice.h>
 #include <linux/notifier.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
-#include <linux/genhd.h>
-#include <linux/mutex.h>
 #include <linux/pm_runtime.h>
-#include <linux/netdevice.h>
+#include <linux/sched/mm.h>
 #include <linux/sched/signal.h>
+#include <linux/slab.h>
+#include <linux/string_helpers.h>
+#include <linux/swiotlb.h>
 #include <linux/sysfs.h>
 
 #include "base.h"
+#include "physical_location.h"
 #include "power/power.h"
 
-#ifdef CONFIG_SYSFS_DEPRECATED
-#ifdef CONFIG_SYSFS_DEPRECATED_V2
-long sysfs_deprecated = 1;
-#else
-long sysfs_deprecated = 0;
-#endif
-static int __init sysfs_deprecated_setup(char *arg)
-{
-	return kstrtol(arg, 10, &sysfs_deprecated);
-}
-early_param("sysfs.deprecated", sysfs_deprecated_setup);
-#endif
-
 /* Device links support. */
-static LIST_HEAD(wait_for_suppliers);
-static DEFINE_MUTEX(wfs_lock);
 static LIST_HEAD(deferred_sync);
 static unsigned int defer_sync_state_count = 1;
+static DEFINE_MUTEX(fwnode_link_lock);
+static bool fw_devlink_is_permissive(void);
+static void __fw_devlink_link_to_consumers(struct device *dev);
+static bool fw_devlink_drv_reg_done;
+static bool fw_devlink_best_effort;
+static struct workqueue_struct *device_link_wq;
+
+/**
+ * __fwnode_link_add - Create a link between two fwnode_handles.
+ * @con: Consumer end of the link.
+ * @sup: Supplier end of the link.
+ * @flags: Link flags.
+ *
+ * Create a fwnode link between fwnode handles @con and @sup. The fwnode link
+ * represents the detail that the firmware lists @sup fwnode as supplying a
+ * resource to @con.
+ *
+ * The driver core will use the fwnode link to create a device link between the
+ * two device objects corresponding to @con and @sup when they are created. The
+ * driver core will automatically delete the fwnode link between @con and @sup
+ * after doing that.
+ *
+ * Attempts to create duplicate links between the same pair of fwnode handles
+ * are ignored and there is no reference counting.
+ */
+static int __fwnode_link_add(struct fwnode_handle *con,
+			     struct fwnode_handle *sup, u8 flags)
+{
+	struct fwnode_link *link;
+
+	list_for_each_entry(link, &sup->consumers, s_hook)
+		if (link->consumer == con) {
+			link->flags |= flags;
+			return 0;
+		}
+
+	link = kzalloc(sizeof(*link), GFP_KERNEL);
+	if (!link)
+		return -ENOMEM;
+
+	link->supplier = sup;
+	INIT_LIST_HEAD(&link->s_hook);
+	link->consumer = con;
+	INIT_LIST_HEAD(&link->c_hook);
+	link->flags = flags;
+
+	list_add(&link->s_hook, &sup->consumers);
+	list_add(&link->c_hook, &con->suppliers);
+	pr_debug("%pfwf Linked as a fwnode consumer to %pfwf\n",
+		 con, sup);
+
+	return 0;
+}
+
+int fwnode_link_add(struct fwnode_handle *con, struct fwnode_handle *sup,
+		    u8 flags)
+{
+	guard(mutex)(&fwnode_link_lock);
+
+	return __fwnode_link_add(con, sup, flags);
+}
+
+/**
+ * __fwnode_link_del - Delete a link between two fwnode_handles.
+ * @link: the fwnode_link to be deleted
+ *
+ * The fwnode_link_lock needs to be held when this function is called.
+ */
+static void __fwnode_link_del(struct fwnode_link *link)
+{
+	pr_debug("%pfwf Dropping the fwnode link to %pfwf\n",
+		 link->consumer, link->supplier);
+	list_del(&link->s_hook);
+	list_del(&link->c_hook);
+	kfree(link);
+}
+
+/**
+ * __fwnode_link_cycle - Mark a fwnode link as being part of a cycle.
+ * @link: the fwnode_link to be marked
+ *
+ * The fwnode_link_lock needs to be held when this function is called.
+ */
+static void __fwnode_link_cycle(struct fwnode_link *link)
+{
+	pr_debug("%pfwf: cycle: depends on %pfwf\n",
+		 link->consumer, link->supplier);
+	link->flags |= FWLINK_FLAG_CYCLE;
+}
+
+/**
+ * fwnode_links_purge_suppliers - Delete all supplier links of fwnode_handle.
+ * @fwnode: fwnode whose supplier links need to be deleted
+ *
+ * Deletes all supplier links connecting directly to @fwnode.
+ */
+static void fwnode_links_purge_suppliers(struct fwnode_handle *fwnode)
+{
+	struct fwnode_link *link, *tmp;
+
+	guard(mutex)(&fwnode_link_lock);
+
+	list_for_each_entry_safe(link, tmp, &fwnode->suppliers, c_hook)
+		__fwnode_link_del(link);
+}
+
+/**
+ * fwnode_links_purge_consumers - Delete all consumer links of fwnode_handle.
+ * @fwnode: fwnode whose consumer links need to be deleted
+ *
+ * Deletes all consumer links connecting directly to @fwnode.
+ */
+static void fwnode_links_purge_consumers(struct fwnode_handle *fwnode)
+{
+	struct fwnode_link *link, *tmp;
+
+	guard(mutex)(&fwnode_link_lock);
+
+	list_for_each_entry_safe(link, tmp, &fwnode->consumers, s_hook)
+		__fwnode_link_del(link);
+}
+
+/**
+ * fwnode_links_purge - Delete all links connected to a fwnode_handle.
+ * @fwnode: fwnode whose links needs to be deleted
+ *
+ * Deletes all links connecting directly to a fwnode.
+ */
+void fwnode_links_purge(struct fwnode_handle *fwnode)
+{
+	fwnode_links_purge_suppliers(fwnode);
+	fwnode_links_purge_consumers(fwnode);
+}
+
+void fw_devlink_purge_absent_suppliers(struct fwnode_handle *fwnode)
+{
+	struct fwnode_handle *child;
+
+	/* Don't purge consumer links of an added child */
+	if (fwnode->dev)
+		return;
+
+	fwnode->flags |= FWNODE_FLAG_NOT_DEVICE;
+	fwnode_links_purge_consumers(fwnode);
+
+	fwnode_for_each_available_child_node(fwnode, child)
+		fw_devlink_purge_absent_suppliers(child);
+}
+EXPORT_SYMBOL_GPL(fw_devlink_purge_absent_suppliers);
+
+/**
+ * __fwnode_links_move_consumers - Move consumer from @from to @to fwnode_handle
+ * @from: move consumers away from this fwnode
+ * @to: move consumers to this fwnode
+ *
+ * Move all consumer links from @from fwnode to @to fwnode.
+ */
+static void __fwnode_links_move_consumers(struct fwnode_handle *from,
+					  struct fwnode_handle *to)
+{
+	struct fwnode_link *link, *tmp;
+
+	list_for_each_entry_safe(link, tmp, &from->consumers, s_hook) {
+		__fwnode_link_add(link->consumer, to, link->flags);
+		__fwnode_link_del(link);
+	}
+}
+
+/**
+ * __fw_devlink_pickup_dangling_consumers - Pick up dangling consumers
+ * @fwnode: fwnode from which to pick up dangling consumers
+ * @new_sup: fwnode of new supplier
+ *
+ * If the @fwnode has a corresponding struct device and the device supports
+ * probing (that is, added to a bus), then we want to let fw_devlink create
+ * MANAGED device links to this device, so leave @fwnode and its descendant's
+ * fwnode links alone.
+ *
+ * Otherwise, move its consumers to the new supplier @new_sup.
+ */
+static void __fw_devlink_pickup_dangling_consumers(struct fwnode_handle *fwnode,
+						   struct fwnode_handle *new_sup)
+{
+	struct fwnode_handle *child;
+
+	if (fwnode->dev && fwnode->dev->bus)
+		return;
+
+	fwnode->flags |= FWNODE_FLAG_NOT_DEVICE;
+	__fwnode_links_move_consumers(fwnode, new_sup);
+
+	fwnode_for_each_available_child_node(fwnode, child)
+		__fw_devlink_pickup_dangling_consumers(child, new_sup);
+}
 
-#ifdef CONFIG_SRCU
 static DEFINE_MUTEX(device_links_lock);
 DEFINE_STATIC_SRCU(device_links_srcu);
 
@@ -78,37 +262,35 @@ int device_links_read_lock_held(void)
 {
 	return srcu_read_lock_held(&device_links_srcu);
 }
-#else /* !CONFIG_SRCU */
-static DECLARE_RWSEM(device_links_lock);
-
-static inline void device_links_write_lock(void)
-{
-	down_write(&device_links_lock);
-}
 
-static inline void device_links_write_unlock(void)
+static void device_link_synchronize_removal(void)
 {
-	up_write(&device_links_lock);
+	synchronize_srcu(&device_links_srcu);
 }
 
-int device_links_read_lock(void)
+static void device_link_remove_from_lists(struct device_link *link)
 {
-	down_read(&device_links_lock);
-	return 0;
+	list_del_rcu(&link->s_node);
+	list_del_rcu(&link->c_node);
 }
 
-void device_links_read_unlock(int not_used)
+static bool device_is_ancestor(struct device *dev, struct device *target)
 {
-	up_read(&device_links_lock);
+	while (target->parent) {
+		target = target->parent;
+		if (dev == target)
+			return true;
+	}
+	return false;
 }
 
-#ifdef CONFIG_DEBUG_LOCK_ALLOC
-int device_links_read_lock_held(void)
+#define DL_MARKER_FLAGS		(DL_FLAG_INFERRED | \
+				 DL_FLAG_CYCLE | \
+				 DL_FLAG_MANAGED)
+bool device_link_flag_is_sync_state_only(u32 flags)
 {
-	return lockdep_is_held(&device_links_lock);
+	return (flags & ~DL_MARKER_FLAGS) == DL_FLAG_SYNC_STATE_ONLY;
 }
-#endif
-#endif /* !CONFIG_SRCU */
 
 /**
  * device_is_dependent - Check if one device depends on another one
@@ -123,7 +305,12 @@ static int device_is_dependent(struct device *dev, void *target)
 	struct device_link *link;
 	int ret;
 
-	if (dev == target)
+	/*
+	 * The "ancestors" check is needed to catch the case when the target
+	 * device has not been completely initialized yet and it is still
+	 * missing from the list of children of its parent device.
+	 */
+	if (dev == target || device_is_ancestor(dev, target))
 		return 1;
 
 	ret = device_for_each_child(dev, target, device_is_dependent);
@@ -131,7 +318,7 @@ static int device_is_dependent(struct device *dev, void *target)
 		return ret;
 
 	list_for_each_entry(link, &dev->links.consumers, s_node) {
-		if (link->flags == (DL_FLAG_SYNC_STATE_ONLY | DL_FLAG_MANAGED))
+		if (device_link_flag_is_sync_state_only(link->flags))
 			continue;
 
 		if (link->consumer == target)
@@ -204,7 +391,7 @@ static int device_reorder_to_tail(struct device *dev, void *not_used)
 
 	device_for_each_child(dev, NULL, device_reorder_to_tail);
 	list_for_each_entry(link, &dev->links.consumers, s_node) {
-		if (link->flags == (DL_FLAG_SYNC_STATE_ONLY | DL_FLAG_MANAGED))
+		if (device_link_flag_is_sync_state_only(link->flags))
 			continue;
 		device_reorder_to_tail(link->consumer, NULL);
 	}
@@ -232,10 +419,248 @@ void device_pm_move_to_tail(struct device *dev)
 	device_links_read_unlock(idx);
 }
 
+#define to_devlink(dev)	container_of((dev), struct device_link, link_dev)
+
+static ssize_t status_show(struct device *dev,
+			   struct device_attribute *attr, char *buf)
+{
+	const char *output;
+
+	switch (to_devlink(dev)->status) {
+	case DL_STATE_NONE:
+		output = "not tracked";
+		break;
+	case DL_STATE_DORMANT:
+		output = "dormant";
+		break;
+	case DL_STATE_AVAILABLE:
+		output = "available";
+		break;
+	case DL_STATE_CONSUMER_PROBE:
+		output = "consumer probing";
+		break;
+	case DL_STATE_ACTIVE:
+		output = "active";
+		break;
+	case DL_STATE_SUPPLIER_UNBIND:
+		output = "supplier unbinding";
+		break;
+	default:
+		output = "unknown";
+		break;
+	}
+
+	return sysfs_emit(buf, "%s\n", output);
+}
+static DEVICE_ATTR_RO(status);
+
+static ssize_t auto_remove_on_show(struct device *dev,
+				   struct device_attribute *attr, char *buf)
+{
+	struct device_link *link = to_devlink(dev);
+	const char *output;
+
+	if (device_link_test(link, DL_FLAG_AUTOREMOVE_SUPPLIER))
+		output = "supplier unbind";
+	else if (device_link_test(link, DL_FLAG_AUTOREMOVE_CONSUMER))
+		output = "consumer unbind";
+	else
+		output = "never";
+
+	return sysfs_emit(buf, "%s\n", output);
+}
+static DEVICE_ATTR_RO(auto_remove_on);
+
+static ssize_t runtime_pm_show(struct device *dev,
+			       struct device_attribute *attr, char *buf)
+{
+	struct device_link *link = to_devlink(dev);
+
+	return sysfs_emit(buf, "%d\n", device_link_test(link, DL_FLAG_PM_RUNTIME));
+}
+static DEVICE_ATTR_RO(runtime_pm);
+
+static ssize_t sync_state_only_show(struct device *dev,
+				    struct device_attribute *attr, char *buf)
+{
+	struct device_link *link = to_devlink(dev);
+
+	return sysfs_emit(buf, "%d\n", device_link_test(link, DL_FLAG_SYNC_STATE_ONLY));
+}
+static DEVICE_ATTR_RO(sync_state_only);
+
+static struct attribute *devlink_attrs[] = {
+	&dev_attr_status.attr,
+	&dev_attr_auto_remove_on.attr,
+	&dev_attr_runtime_pm.attr,
+	&dev_attr_sync_state_only.attr,
+	NULL,
+};
+ATTRIBUTE_GROUPS(devlink);
+
+static void device_link_release_fn(struct work_struct *work)
+{
+	struct device_link *link = container_of(work, struct device_link, rm_work);
+
+	/* Ensure that all references to the link object have been dropped. */
+	device_link_synchronize_removal();
+
+	pm_runtime_release_supplier(link);
+	/*
+	 * If supplier_preactivated is set, the link has been dropped between
+	 * the pm_runtime_get_suppliers() and pm_runtime_put_suppliers() calls
+	 * in __driver_probe_device().  In that case, drop the supplier's
+	 * PM-runtime usage counter to remove the reference taken by
+	 * pm_runtime_get_suppliers().
+	 */
+	if (link->supplier_preactivated)
+		pm_runtime_put_noidle(link->supplier);
+
+	pm_request_idle(link->supplier);
+
+	put_device(link->consumer);
+	put_device(link->supplier);
+	kfree(link);
+}
+
+static void devlink_dev_release(struct device *dev)
+{
+	struct device_link *link = to_devlink(dev);
+
+	INIT_WORK(&link->rm_work, device_link_release_fn);
+	/*
+	 * It may take a while to complete this work because of the SRCU
+	 * synchronization in device_link_release_fn() and if the consumer or
+	 * supplier devices get deleted when it runs, so put it into the
+	 * dedicated workqueue.
+	 */
+	queue_work(device_link_wq, &link->rm_work);
+}
+
+/**
+ * device_link_wait_removal - Wait for ongoing devlink removal jobs to terminate
+ */
+void device_link_wait_removal(void)
+{
+	/*
+	 * devlink removal jobs are queued in the dedicated work queue.
+	 * To be sure that all removal jobs are terminated, ensure that any
+	 * scheduled work has run to completion.
+	 */
+	flush_workqueue(device_link_wq);
+}
+EXPORT_SYMBOL_GPL(device_link_wait_removal);
+
+static const struct class devlink_class = {
+	.name = "devlink",
+	.dev_groups = devlink_groups,
+	.dev_release = devlink_dev_release,
+};
+
+static int devlink_add_symlinks(struct device *dev)
+{
+	char *buf_con __free(kfree) = NULL, *buf_sup __free(kfree) = NULL;
+	int ret;
+	struct device_link *link = to_devlink(dev);
+	struct device *sup = link->supplier;
+	struct device *con = link->consumer;
+
+	ret = sysfs_create_link(&link->link_dev.kobj, &sup->kobj, "supplier");
+	if (ret)
+		goto out;
+
+	ret = sysfs_create_link(&link->link_dev.kobj, &con->kobj, "consumer");
+	if (ret)
+		goto err_con;
+
+	buf_con = kasprintf(GFP_KERNEL, "consumer:%s:%s", dev_bus_name(con), dev_name(con));
+	if (!buf_con) {
+		ret = -ENOMEM;
+		goto err_con_dev;
+	}
+
+	ret = sysfs_create_link(&sup->kobj, &link->link_dev.kobj, buf_con);
+	if (ret)
+		goto err_con_dev;
+
+	buf_sup = kasprintf(GFP_KERNEL, "supplier:%s:%s", dev_bus_name(sup), dev_name(sup));
+	if (!buf_sup) {
+		ret = -ENOMEM;
+		goto err_sup_dev;
+	}
+
+	ret = sysfs_create_link(&con->kobj, &link->link_dev.kobj, buf_sup);
+	if (ret)
+		goto err_sup_dev;
+
+	goto out;
+
+err_sup_dev:
+	sysfs_remove_link(&sup->kobj, buf_con);
+err_con_dev:
+	sysfs_remove_link(&link->link_dev.kobj, "consumer");
+err_con:
+	sysfs_remove_link(&link->link_dev.kobj, "supplier");
+out:
+	return ret;
+}
+
+static void devlink_remove_symlinks(struct device *dev)
+{
+	char *buf_con __free(kfree) = NULL, *buf_sup __free(kfree) = NULL;
+	struct device_link *link = to_devlink(dev);
+	struct device *sup = link->supplier;
+	struct device *con = link->consumer;
+
+	sysfs_remove_link(&link->link_dev.kobj, "consumer");
+	sysfs_remove_link(&link->link_dev.kobj, "supplier");
+
+	if (device_is_registered(con)) {
+		buf_sup = kasprintf(GFP_KERNEL, "supplier:%s:%s", dev_bus_name(sup), dev_name(sup));
+		if (!buf_sup)
+			goto out;
+		sysfs_remove_link(&con->kobj, buf_sup);
+	}
+
+	buf_con = kasprintf(GFP_KERNEL, "consumer:%s:%s", dev_bus_name(con), dev_name(con));
+	if (!buf_con)
+		goto out;
+	sysfs_remove_link(&sup->kobj, buf_con);
+
+	return;
+
+out:
+	WARN(1, "Unable to properly free device link symlinks!\n");
+}
+
+static struct class_interface devlink_class_intf = {
+	.class = &devlink_class,
+	.add_dev = devlink_add_symlinks,
+	.remove_dev = devlink_remove_symlinks,
+};
+
+static int __init devlink_class_init(void)
+{
+	int ret;
+
+	ret = class_register(&devlink_class);
+	if (ret)
+		return ret;
+
+	ret = class_interface_register(&devlink_class_intf);
+	if (ret)
+		class_unregister(&devlink_class);
+
+	return ret;
+}
+postcore_initcall(devlink_class_init);
+
 #define DL_MANAGED_LINK_FLAGS (DL_FLAG_AUTOREMOVE_CONSUMER | \
 			       DL_FLAG_AUTOREMOVE_SUPPLIER | \
 			       DL_FLAG_AUTOPROBE_CONSUMER  | \
-			       DL_FLAG_SYNC_STATE_ONLY)
+			       DL_FLAG_SYNC_STATE_ONLY | \
+			       DL_FLAG_INFERRED | \
+			       DL_FLAG_CYCLE)
 
 #define DL_ADD_VALID_FLAGS (DL_MANAGED_LINK_FLAGS | DL_FLAG_STATELESS | \
 			    DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE)
@@ -246,11 +671,14 @@ void device_pm_move_to_tail(struct device *dev)
  * @supplier: Supplier end of the link.
  * @flags: Link flags.
  *
+ * Return: On success, a device_link struct will be returned.
+ *         On error or invalid flag settings, NULL will be returned.
+ *
  * The caller is responsible for the proper synchronization of the link creation
  * with runtime PM.  First, setting the DL_FLAG_PM_RUNTIME flag will cause the
  * runtime PM framework to take the link into account.  Second, if the
  * DL_FLAG_RPM_ACTIVE flag is set in addition to it, the supplier devices will
- * be forced into the active metastate and reference-counted upon the creation
+ * be forced into the active meta state and reference-counted upon the creation
  * of the link.  If DL_FLAG_PM_RUNTIME is not set, DL_FLAG_RPM_ACTIVE will be
  * ignored.
  *
@@ -273,7 +701,7 @@ void device_pm_move_to_tail(struct device *dev)
  * Also, if DL_FLAG_STATELESS, DL_FLAG_AUTOREMOVE_CONSUMER and
  * DL_FLAG_AUTOREMOVE_SUPPLIER are not set in @flags (that is, a persistent
  * managed device link is being added), the DL_FLAG_AUTOPROBE_CONSUMER flag can
- * be used to request the driver core to automaticall probe for a consmer
+ * be used to request the driver core to automatically probe for a consumer
  * driver after successfully binding a driver to the supplier device.
  *
  * The combination of DL_FLAG_STATELESS and one of DL_FLAG_AUTOREMOVE_CONSUMER,
@@ -301,10 +729,9 @@ struct device_link *device_link_add(struct device *consumer,
 {
 	struct device_link *link;
 
-	if (!consumer || !supplier || flags & ~DL_ADD_VALID_FLAGS ||
+	if (!consumer || !supplier || consumer == supplier ||
+	    flags & ~DL_ADD_VALID_FLAGS ||
 	    (flags & DL_FLAG_STATELESS && flags & DL_MANAGED_LINK_FLAGS) ||
-	    (flags & DL_FLAG_SYNC_STATE_ONLY &&
-	     flags != DL_FLAG_SYNC_STATE_ONLY) ||
 	    (flags & DL_FLAG_AUTOPROBE_CONSUMER &&
 	     flags & (DL_FLAG_AUTOREMOVE_CONSUMER |
 		      DL_FLAG_AUTOREMOVE_SUPPLIER)))
@@ -320,6 +747,10 @@ struct device_link *device_link_add(struct device *consumer,
 	if (!(flags & DL_FLAG_STATELESS))
 		flags |= DL_FLAG_MANAGED;
 
+	if (flags & DL_FLAG_SYNC_STATE_ONLY &&
+	    !device_link_flag_is_sync_state_only(flags))
+		return NULL;
+
 	device_links_write_lock();
 	device_pm_lock();
 
@@ -338,6 +769,17 @@ struct device_link *device_link_add(struct device *consumer,
 	}
 
 	/*
+	 * SYNC_STATE_ONLY links are useless once a consumer device has probed.
+	 * So, only create it if the consumer hasn't probed yet.
+	 */
+	if (flags & DL_FLAG_SYNC_STATE_ONLY &&
+	    consumer->links.status != DL_DEV_NO_DRIVER &&
+	    consumer->links.status != DL_DEV_PROBING) {
+		link = NULL;
+		goto out;
+	}
+
+	/*
 	 * DL_FLAG_AUTOREMOVE_SUPPLIER indicates that the link will be needed
 	 * longer than for DL_FLAG_AUTOREMOVE_CONSUMER and setting them both
 	 * together doesn't make sense, so prefer DL_FLAG_AUTOREMOVE_SUPPLIER.
@@ -349,8 +791,12 @@ struct device_link *device_link_add(struct device *consumer,
 		if (link->consumer != consumer)
 			continue;
 
+		if (device_link_test(link, DL_FLAG_INFERRED) &&
+		    !(flags & DL_FLAG_INFERRED))
+			link->flags &= ~DL_FLAG_INFERRED;
+
 		if (flags & DL_FLAG_PM_RUNTIME) {
-			if (!(link->flags & DL_FLAG_PM_RUNTIME)) {
+			if (!device_link_test(link, DL_FLAG_PM_RUNTIME)) {
 				pm_runtime_new_link(consumer);
 				link->flags |= DL_FLAG_PM_RUNTIME;
 			}
@@ -360,11 +806,12 @@ struct device_link *device_link_add(struct device *consumer,
 
 		if (flags & DL_FLAG_STATELESS) {
 			kref_get(&link->kref);
-			if (link->flags & DL_FLAG_SYNC_STATE_ONLY &&
-			    !(link->flags & DL_FLAG_STATELESS)) {
+			if (device_link_test(link, DL_FLAG_SYNC_STATE_ONLY) &&
+			    !device_link_test(link, DL_FLAG_STATELESS)) {
 				link->flags |= DL_FLAG_STATELESS;
 				goto reorder;
 			} else {
+				link->flags |= DL_FLAG_STATELESS;
 				goto out;
 			}
 		}
@@ -375,7 +822,7 @@ struct device_link *device_link_add(struct device *consumer,
 		 * update the existing link to stay around longer.
 		 */
 		if (flags & DL_FLAG_AUTOREMOVE_SUPPLIER) {
-			if (link->flags & DL_FLAG_AUTOREMOVE_CONSUMER) {
+			if (device_link_test(link, DL_FLAG_AUTOREMOVE_CONSUMER)) {
 				link->flags &= ~DL_FLAG_AUTOREMOVE_CONSUMER;
 				link->flags |= DL_FLAG_AUTOREMOVE_SUPPLIER;
 			}
@@ -383,12 +830,12 @@ struct device_link *device_link_add(struct device *consumer,
 			link->flags &= ~(DL_FLAG_AUTOREMOVE_CONSUMER |
 					 DL_FLAG_AUTOREMOVE_SUPPLIER);
 		}
-		if (!(link->flags & DL_FLAG_MANAGED)) {
+		if (!device_link_test(link, DL_FLAG_MANAGED)) {
 			kref_get(&link->kref);
 			link->flags |= DL_FLAG_MANAGED;
 			device_link_init_status(link, consumer, supplier);
 		}
-		if (link->flags & DL_FLAG_SYNC_STATE_ONLY &&
+		if (device_link_test(link, DL_FLAG_SYNC_STATE_ONLY) &&
 		    !(flags & DL_FLAG_SYNC_STATE_ONLY)) {
 			link->flags &= ~DL_FLAG_SYNC_STATE_ONLY;
 			goto reorder;
@@ -403,13 +850,6 @@ struct device_link *device_link_add(struct device *consumer,
 
 	refcount_set(&link->rpm_active, 1);
 
-	if (flags & DL_FLAG_PM_RUNTIME) {
-		if (flags & DL_FLAG_RPM_ACTIVE)
-			refcount_inc(&link->rpm_active);
-
-		pm_runtime_new_link(consumer);
-	}
-
 	get_device(supplier);
 	link->supplier = supplier;
 	INIT_LIST_HEAD(&link->s_node);
@@ -419,6 +859,24 @@ struct device_link *device_link_add(struct device *consumer,
 	link->flags = flags;
 	kref_init(&link->kref);
 
+	link->link_dev.class = &devlink_class;
+	device_set_pm_not_required(&link->link_dev);
+	dev_set_name(&link->link_dev, "%s:%s--%s:%s",
+		     dev_bus_name(supplier), dev_name(supplier),
+		     dev_bus_name(consumer), dev_name(consumer));
+	if (device_register(&link->link_dev)) {
+		put_device(&link->link_dev);
+		link = NULL;
+		goto out;
+	}
+
+	if (flags & DL_FLAG_PM_RUNTIME) {
+		if (flags & DL_FLAG_RPM_ACTIVE)
+			refcount_inc(&link->rpm_active);
+
+		pm_runtime_new_link(consumer);
+	}
+
 	/* Determine the initial link state. */
 	if (flags & DL_FLAG_STATELESS)
 		link->status = DL_STATE_NONE;
@@ -433,12 +891,16 @@ struct device_link *device_link_add(struct device *consumer,
 	    flags & DL_FLAG_PM_RUNTIME)
 		pm_runtime_resume(supplier);
 
+	list_add_tail_rcu(&link->s_node, &supplier->links.consumers);
+	list_add_tail_rcu(&link->c_node, &consumer->links.suppliers);
+
 	if (flags & DL_FLAG_SYNC_STATE_ONLY) {
 		dev_dbg(consumer,
 			"Linked as a sync state only consumer to %s\n",
 			dev_name(supplier));
 		goto out;
 	}
+
 reorder:
 	/*
 	 * Move the consumer and all of the devices depending on it to the end
@@ -449,12 +911,9 @@ reorder:
 	 */
 	device_reorder_to_tail(consumer, NULL);
 
-	list_add_tail_rcu(&link->s_node, &supplier->links.consumers);
-	list_add_tail_rcu(&link->c_node, &consumer->links.suppliers);
-
 	dev_dbg(consumer, "Linked as a consumer to %s\n", dev_name(supplier));
 
- out:
+out:
 	device_pm_unlock();
 	device_links_write_unlock();
 
@@ -465,90 +924,6 @@ reorder:
 }
 EXPORT_SYMBOL_GPL(device_link_add);
 
-/**
- * device_link_wait_for_supplier - Add device to wait_for_suppliers list
- * @consumer: Consumer device
- *
- * Marks the @consumer device as waiting for suppliers to become available by
- * adding it to the wait_for_suppliers list. The consumer device will never be
- * probed until it's removed from the wait_for_suppliers list.
- *
- * The caller is responsible for adding the links to the supplier devices once
- * they are available and removing the @consumer device from the
- * wait_for_suppliers list once links to all the suppliers have been created.
- *
- * This function is NOT meant to be called from the probe function of the
- * consumer but rather from code that creates/adds the consumer device.
- */
-static void device_link_wait_for_supplier(struct device *consumer,
-					  bool need_for_probe)
-{
-	mutex_lock(&wfs_lock);
-	list_add_tail(&consumer->links.needs_suppliers, &wait_for_suppliers);
-	consumer->links.need_for_probe = need_for_probe;
-	mutex_unlock(&wfs_lock);
-}
-
-static void device_link_wait_for_mandatory_supplier(struct device *consumer)
-{
-	device_link_wait_for_supplier(consumer, true);
-}
-
-static void device_link_wait_for_optional_supplier(struct device *consumer)
-{
-	device_link_wait_for_supplier(consumer, false);
-}
-
-/**
- * device_link_add_missing_supplier_links - Add links from consumer devices to
- *					    supplier devices, leaving any
- *					    consumer with inactive suppliers on
- *					    the wait_for_suppliers list
- *
- * Loops through all consumers waiting on suppliers and tries to add all their
- * supplier links. If that succeeds, the consumer device is removed from
- * wait_for_suppliers list. Otherwise, they are left in the wait_for_suppliers
- * list.  Devices left on the wait_for_suppliers list will not be probed.
- *
- * The fwnode add_links callback is expected to return 0 if it has found and
- * added all the supplier links for the consumer device. It should return an
- * error if it isn't able to do so.
- *
- * The caller of device_link_wait_for_supplier() is expected to call this once
- * it's aware of potential suppliers becoming available.
- */
-static void device_link_add_missing_supplier_links(void)
-{
-	struct device *dev, *tmp;
-
-	mutex_lock(&wfs_lock);
-	list_for_each_entry_safe(dev, tmp, &wait_for_suppliers,
-				 links.needs_suppliers) {
-		int ret = fwnode_call_int_op(dev->fwnode, add_links, dev);
-		if (!ret)
-			list_del_init(&dev->links.needs_suppliers);
-		else if (ret != -ENODEV)
-			dev->links.need_for_probe = false;
-	}
-	mutex_unlock(&wfs_lock);
-}
-
-static void device_link_free(struct device_link *link)
-{
-	while (refcount_dec_not_one(&link->rpm_active))
-		pm_runtime_put(link->supplier);
-
-	put_device(link->consumer);
-	put_device(link->supplier);
-	kfree(link);
-}
-
-#ifdef CONFIG_SRCU
-static void __device_link_free_srcu(struct rcu_head *rhead)
-{
-	device_link_free(container_of(rhead, struct device_link, rcu_head));
-}
-
 static void __device_link_del(struct kref *kref)
 {
 	struct device_link *link = container_of(kref, struct device_link, kref);
@@ -556,34 +931,18 @@ static void __device_link_del(struct kref *kref)
 	dev_dbg(link->consumer, "Dropping the link to %s\n",
 		dev_name(link->supplier));
 
-	if (link->flags & DL_FLAG_PM_RUNTIME)
-		pm_runtime_drop_link(link->consumer);
-
-	list_del_rcu(&link->s_node);
-	list_del_rcu(&link->c_node);
-	call_srcu(&device_links_srcu, &link->rcu_head, __device_link_free_srcu);
-}
-#else /* !CONFIG_SRCU */
-static void __device_link_del(struct kref *kref)
-{
-	struct device_link *link = container_of(kref, struct device_link, kref);
-
-	dev_info(link->consumer, "Dropping the link to %s\n",
-		 dev_name(link->supplier));
+	pm_runtime_drop_link(link);
 
-	if (link->flags & DL_FLAG_PM_RUNTIME)
-		pm_runtime_drop_link(link->consumer);
-
-	list_del(&link->s_node);
-	list_del(&link->c_node);
-	device_link_free(link);
+	device_link_remove_from_lists(link);
+	device_unregister(&link->link_dev);
 }
-#endif /* !CONFIG_SRCU */
 
 static void device_link_put_kref(struct device_link *link)
 {
-	if (link->flags & DL_FLAG_STATELESS)
+	if (device_link_test(link, DL_FLAG_STATELESS))
 		kref_put(&link->kref, __device_link_del);
+	else if (!device_is_registered(link->consumer))
+		__device_link_del(&link->kref);
 	else
 		WARN(1, "Unable to drop a managed device link reference\n");
 }
@@ -600,9 +959,7 @@ static void device_link_put_kref(struct device_link *link)
 void device_link_del(struct device_link *link)
 {
 	device_links_write_lock();
-	device_pm_lock();
 	device_link_put_kref(link);
-	device_pm_unlock();
 	device_links_write_unlock();
 }
 EXPORT_SYMBOL_GPL(device_link_del);
@@ -623,7 +980,6 @@ void device_link_remove(void *consumer, struct device *supplier)
 		return;
 
 	device_links_write_lock();
-	device_pm_lock();
 
 	list_for_each_entry(link, &supplier->links.consumers, s_node) {
 		if (link->consumer == consumer) {
@@ -632,7 +988,6 @@ void device_link_remove(void *consumer, struct device *supplier)
 		}
 	}
 
-	device_pm_unlock();
 	device_links_write_unlock();
 }
 EXPORT_SYMBOL_GPL(device_link_remove);
@@ -641,9 +996,39 @@ static void device_links_missing_supplier(struct device *dev)
 {
 	struct device_link *link;
 
-	list_for_each_entry(link, &dev->links.suppliers, c_node)
-		if (link->status == DL_STATE_CONSUMER_PROBE)
+	list_for_each_entry(link, &dev->links.suppliers, c_node) {
+		if (link->status != DL_STATE_CONSUMER_PROBE)
+			continue;
+
+		if (link->supplier->links.status == DL_DEV_DRIVER_BOUND) {
 			WRITE_ONCE(link->status, DL_STATE_AVAILABLE);
+		} else {
+			WARN_ON(!device_link_test(link, DL_FLAG_SYNC_STATE_ONLY));
+			WRITE_ONCE(link->status, DL_STATE_DORMANT);
+		}
+	}
+}
+
+static bool dev_is_best_effort(struct device *dev)
+{
+	return (fw_devlink_best_effort && dev->can_match) ||
+		(dev->fwnode && (dev->fwnode->flags & FWNODE_FLAG_BEST_EFFORT));
+}
+
+static struct fwnode_handle *fwnode_links_check_suppliers(
+						struct fwnode_handle *fwnode)
+{
+	struct fwnode_link *link;
+
+	if (!fwnode || fw_devlink_is_permissive())
+		return NULL;
+
+	list_for_each_entry(link, &fwnode->suppliers, c_hook)
+		if (!(link->flags &
+		      (FWLINK_FLAG_CYCLE | FWLINK_FLAG_IGNORE)))
+			return link->supplier;
+
+	return NULL;
 }
 
 /**
@@ -665,30 +1050,43 @@ static void device_links_missing_supplier(struct device *dev)
 int device_links_check_suppliers(struct device *dev)
 {
 	struct device_link *link;
-	int ret = 0;
+	int ret = 0, fwnode_ret = 0;
+	struct fwnode_handle *sup_fw;
 
 	/*
 	 * Device waiting for supplier to become available is not allowed to
 	 * probe.
 	 */
-	mutex_lock(&wfs_lock);
-	if (!list_empty(&dev->links.needs_suppliers) &&
-	    dev->links.need_for_probe) {
-		mutex_unlock(&wfs_lock);
-		return -EPROBE_DEFER;
+	scoped_guard(mutex, &fwnode_link_lock) {
+		sup_fw = fwnode_links_check_suppliers(dev->fwnode);
+		if (sup_fw) {
+			if (dev_is_best_effort(dev))
+				fwnode_ret = -EAGAIN;
+			else
+				return dev_err_probe(dev, -EPROBE_DEFER,
+						     "wait for supplier %pfwf\n", sup_fw);
+		}
 	}
-	mutex_unlock(&wfs_lock);
 
 	device_links_write_lock();
 
 	list_for_each_entry(link, &dev->links.suppliers, c_node) {
-		if (!(link->flags & DL_FLAG_MANAGED) ||
-		    link->flags & DL_FLAG_SYNC_STATE_ONLY)
+		if (!device_link_test(link, DL_FLAG_MANAGED))
 			continue;
 
-		if (link->status != DL_STATE_AVAILABLE) {
+		if (link->status != DL_STATE_AVAILABLE &&
+		    !device_link_test(link, DL_FLAG_SYNC_STATE_ONLY)) {
+
+			if (dev_is_best_effort(dev) &&
+			    device_link_test(link, DL_FLAG_INFERRED) &&
+			    !link->supplier->can_match) {
+				ret = -EAGAIN;
+				continue;
+			}
+
 			device_links_missing_supplier(dev);
-			ret = -EPROBE_DEFER;
+			ret = dev_err_probe(dev, -EPROBE_DEFER,
+					    "supplier %s not ready\n", dev_name(link->supplier));
 			break;
 		}
 		WRITE_ONCE(link->status, DL_STATE_CONSUMER_PROBE);
@@ -696,7 +1094,8 @@ int device_links_check_suppliers(struct device *dev)
 	dev->links.status = DL_DEV_PROBING;
 
 	device_links_write_unlock();
-	return ret;
+
+	return ret ? ret : fwnode_ret;
 }
 
 /**
@@ -728,7 +1127,7 @@ static void __device_links_queue_sync_state(struct device *dev,
 		return;
 
 	list_for_each_entry(link, &dev->links.consumers, s_node) {
-		if (!(link->flags & DL_FLAG_MANAGED))
+		if (!device_link_test(link, DL_FLAG_MANAGED))
 			continue;
 		if (link->status != DL_STATE_ACTIVE)
 			return;
@@ -769,10 +1168,7 @@ static void device_links_flush_sync_list(struct list_head *list,
 		if (dev != dont_lock_dev)
 			device_lock(dev);
 
-		if (dev->bus->sync_state)
-			dev->bus->sync_state(dev);
-		else if (dev->driver && dev->driver->sync_state)
-			dev->driver->sync_state(dev);
+		dev_sync_state(dev);
 
 		if (dev != dont_lock_dev)
 			device_unlock(dev);
@@ -829,6 +1225,62 @@ static void __device_links_supplier_defer_sync(struct device *sup)
 		list_add_tail(&sup->links.defer_sync, &deferred_sync);
 }
 
+static void device_link_drop_managed(struct device_link *link)
+{
+	link->flags &= ~DL_FLAG_MANAGED;
+	WRITE_ONCE(link->status, DL_STATE_NONE);
+	kref_put(&link->kref, __device_link_del);
+}
+
+static ssize_t waiting_for_supplier_show(struct device *dev,
+					 struct device_attribute *attr,
+					 char *buf)
+{
+	bool val;
+
+	device_lock(dev);
+	scoped_guard(mutex, &fwnode_link_lock)
+		val = !!fwnode_links_check_suppliers(dev->fwnode);
+	device_unlock(dev);
+	return sysfs_emit(buf, "%u\n", val);
+}
+static DEVICE_ATTR_RO(waiting_for_supplier);
+
+/**
+ * device_links_force_bind - Prepares device to be force bound
+ * @dev: Consumer device.
+ *
+ * device_bind_driver() force binds a device to a driver without calling any
+ * driver probe functions. So the consumer really isn't going to wait for any
+ * supplier before it's bound to the driver. We still want the device link
+ * states to be sensible when this happens.
+ *
+ * In preparation for device_bind_driver(), this function goes through each
+ * supplier device links and checks if the supplier is bound. If it is, then
+ * the device link status is set to CONSUMER_PROBE. Otherwise, the device link
+ * is dropped. Links without the DL_FLAG_MANAGED flag set are ignored.
+ */
+void device_links_force_bind(struct device *dev)
+{
+	struct device_link *link, *ln;
+
+	device_links_write_lock();
+
+	list_for_each_entry_safe(link, ln, &dev->links.suppliers, c_node) {
+		if (!device_link_test(link, DL_FLAG_MANAGED))
+			continue;
+
+		if (link->status != DL_STATE_AVAILABLE) {
+			device_link_drop_managed(link);
+			continue;
+		}
+		WRITE_ONCE(link->status, DL_STATE_CONSUMER_PROBE);
+	}
+	dev->links.status = DL_DEV_PROBING;
+
+	device_links_write_unlock();
+}
+
 /**
  * device_links_driver_bound - Update device links after probing its driver.
  * @dev: Device to update the links for.
@@ -842,22 +1294,41 @@ static void __device_links_supplier_defer_sync(struct device *sup)
  */
 void device_links_driver_bound(struct device *dev)
 {
-	struct device_link *link;
+	struct device_link *link, *ln;
 	LIST_HEAD(sync_list);
 
 	/*
-	 * If a device probes successfully, it's expected to have created all
+	 * If a device binds successfully, it's expected to have created all
 	 * the device links it needs to or make new device links as it needs
-	 * them. So, it no longer needs to wait on any suppliers.
+	 * them. So, fw_devlink no longer needs to create device links to any
+	 * of the device's suppliers.
+	 *
+	 * Also, if a child firmware node of this bound device is not added as a
+	 * device by now, assume it is never going to be added. Make this bound
+	 * device the fallback supplier to the dangling consumers of the child
+	 * firmware node because this bound device is probably implementing the
+	 * child firmware node functionality and we don't want the dangling
+	 * consumers to defer probe indefinitely waiting for a device for the
+	 * child firmware node.
 	 */
-	mutex_lock(&wfs_lock);
-	list_del_init(&dev->links.needs_suppliers);
-	mutex_unlock(&wfs_lock);
+	if (dev->fwnode && dev->fwnode->dev == dev) {
+		struct fwnode_handle *child;
+
+		fwnode_links_purge_suppliers(dev->fwnode);
+
+		guard(mutex)(&fwnode_link_lock);
+
+		fwnode_for_each_available_child_node(dev->fwnode, child)
+			__fw_devlink_pickup_dangling_consumers(child,
+							       dev->fwnode);
+		__fw_devlink_link_to_consumers(dev);
+	}
+	device_remove_file(dev, &dev_attr_waiting_for_supplier);
 
 	device_links_write_lock();
 
 	list_for_each_entry(link, &dev->links.consumers, s_node) {
-		if (!(link->flags & DL_FLAG_MANAGED))
+		if (!device_link_test(link, DL_FLAG_MANAGED))
 			continue;
 
 		/*
@@ -873,7 +1344,7 @@ void device_links_driver_bound(struct device *dev)
 		WARN_ON(link->status != DL_STATE_DORMANT);
 		WRITE_ONCE(link->status, DL_STATE_AVAILABLE);
 
-		if (link->flags & DL_FLAG_AUTOPROBE_CONSUMER)
+		if (device_link_test(link, DL_FLAG_AUTOPROBE_CONSUMER))
 			driver_deferred_probe_add(link->consumer);
 	}
 
@@ -882,18 +1353,47 @@ void device_links_driver_bound(struct device *dev)
 	else
 		__device_links_queue_sync_state(dev, &sync_list);
 
-	list_for_each_entry(link, &dev->links.suppliers, c_node) {
-		if (!(link->flags & DL_FLAG_MANAGED))
+	list_for_each_entry_safe(link, ln, &dev->links.suppliers, c_node) {
+		struct device *supplier;
+
+		if (!device_link_test(link, DL_FLAG_MANAGED))
 			continue;
 
-		WARN_ON(link->status != DL_STATE_CONSUMER_PROBE);
-		WRITE_ONCE(link->status, DL_STATE_ACTIVE);
+		supplier = link->supplier;
+		if (device_link_test(link, DL_FLAG_SYNC_STATE_ONLY)) {
+			/*
+			 * When DL_FLAG_SYNC_STATE_ONLY is set, it means no
+			 * other DL_MANAGED_LINK_FLAGS have been set. So, it's
+			 * save to drop the managed link completely.
+			 */
+			device_link_drop_managed(link);
+		} else if (dev_is_best_effort(dev) &&
+			   device_link_test(link, DL_FLAG_INFERRED) &&
+			   link->status != DL_STATE_CONSUMER_PROBE &&
+			   !link->supplier->can_match) {
+			/*
+			 * When dev_is_best_effort() is true, we ignore device
+			 * links to suppliers that don't have a driver.  If the
+			 * consumer device still managed to probe, there's no
+			 * point in maintaining a device link in a weird state
+			 * (consumer probed before supplier). So delete it.
+			 */
+			device_link_drop_managed(link);
+		} else {
+			WARN_ON(link->status != DL_STATE_CONSUMER_PROBE);
+			WRITE_ONCE(link->status, DL_STATE_ACTIVE);
+		}
 
+		/*
+		 * This needs to be done even for the deleted
+		 * DL_FLAG_SYNC_STATE_ONLY device link in case it was the last
+		 * device link that was preventing the supplier from getting a
+		 * sync_state() call.
+		 */
 		if (defer_sync_state_count)
-			__device_links_supplier_defer_sync(link->supplier);
+			__device_links_supplier_defer_sync(supplier);
 		else
-			__device_links_queue_sync_state(link->supplier,
-							&sync_list);
+			__device_links_queue_sync_state(supplier, &sync_list);
 	}
 
 	dev->links.status = DL_DEV_DRIVER_BOUND;
@@ -903,13 +1403,6 @@ void device_links_driver_bound(struct device *dev)
 	device_links_flush_sync_list(&sync_list, dev);
 }
 
-static void device_link_drop_managed(struct device_link *link)
-{
-	link->flags &= ~DL_FLAG_MANAGED;
-	WRITE_ONCE(link->status, DL_STATE_NONE);
-	kref_put(&link->kref, __device_link_del);
-}
-
 /**
  * __device_links_no_driver - Update links of a device without a driver.
  * @dev: Device without a drvier.
@@ -927,14 +1420,24 @@ static void __device_links_no_driver(struct device *dev)
 	struct device_link *link, *ln;
 
 	list_for_each_entry_safe_reverse(link, ln, &dev->links.suppliers, c_node) {
-		if (!(link->flags & DL_FLAG_MANAGED))
+		if (!device_link_test(link, DL_FLAG_MANAGED))
 			continue;
 
-		if (link->flags & DL_FLAG_AUTOREMOVE_CONSUMER)
+		if (device_link_test(link, DL_FLAG_AUTOREMOVE_CONSUMER)) {
 			device_link_drop_managed(link);
-		else if (link->status == DL_STATE_CONSUMER_PROBE ||
-			 link->status == DL_STATE_ACTIVE)
+			continue;
+		}
+
+		if (link->status != DL_STATE_CONSUMER_PROBE &&
+		    link->status != DL_STATE_ACTIVE)
+			continue;
+
+		if (link->supplier->links.status == DL_DEV_DRIVER_BOUND) {
 			WRITE_ONCE(link->status, DL_STATE_AVAILABLE);
+		} else {
+			WARN_ON(!device_link_test(link, DL_FLAG_SYNC_STATE_ONLY));
+			WRITE_ONCE(link->status, DL_STATE_DORMANT);
+		}
 	}
 
 	dev->links.status = DL_DEV_NO_DRIVER;
@@ -957,7 +1460,7 @@ void device_links_no_driver(struct device *dev)
 	device_links_write_lock();
 
 	list_for_each_entry(link, &dev->links.consumers, s_node) {
-		if (!(link->flags & DL_FLAG_MANAGED))
+		if (!device_link_test(link, DL_FLAG_MANAGED))
 			continue;
 
 		/*
@@ -994,10 +1497,10 @@ void device_links_driver_cleanup(struct device *dev)
 	device_links_write_lock();
 
 	list_for_each_entry_safe(link, ln, &dev->links.consumers, s_node) {
-		if (!(link->flags & DL_FLAG_MANAGED))
+		if (!device_link_test(link, DL_FLAG_MANAGED))
 			continue;
 
-		WARN_ON(link->flags & DL_FLAG_AUTOREMOVE_CONSUMER);
+		WARN_ON(device_link_test(link, DL_FLAG_AUTOREMOVE_CONSUMER));
 		WARN_ON(link->status != DL_STATE_SUPPLIER_UNBIND);
 
 		/*
@@ -1006,7 +1509,7 @@ void device_links_driver_cleanup(struct device *dev)
 		 * has moved to DL_STATE_SUPPLIER_UNBIND.
 		 */
 		if (link->status == DL_STATE_SUPPLIER_UNBIND &&
-		    link->flags & DL_FLAG_AUTOREMOVE_SUPPLIER)
+		    device_link_test(link, DL_FLAG_AUTOREMOVE_SUPPLIER))
 			device_link_drop_managed(link);
 
 		WRITE_ONCE(link->status, DL_STATE_DORMANT);
@@ -1040,7 +1543,7 @@ bool device_links_busy(struct device *dev)
 	device_links_write_lock();
 
 	list_for_each_entry(link, &dev->links.consumers, s_node) {
-		if (!(link->flags & DL_FLAG_MANAGED))
+		if (!device_link_test(link, DL_FLAG_MANAGED))
 			continue;
 
 		if (link->status == DL_STATE_CONSUMER_PROBE
@@ -1082,8 +1585,8 @@ void device_links_unbind_consumers(struct device *dev)
 	list_for_each_entry(link, &dev->links.consumers, s_node) {
 		enum device_link_state status;
 
-		if (!(link->flags & DL_FLAG_MANAGED) ||
-		    link->flags & DL_FLAG_SYNC_STATE_ONLY)
+		if (!device_link_test(link, DL_FLAG_MANAGED) ||
+		    device_link_test(link, DL_FLAG_SYNC_STATE_ONLY))
 			continue;
 
 		status = link->status;
@@ -1119,9 +1622,8 @@ static void device_links_purge(struct device *dev)
 {
 	struct device_link *link, *ln;
 
-	mutex_lock(&wfs_lock);
-	list_del(&dev->links.needs_suppliers);
-	mutex_unlock(&wfs_lock);
+	if (dev->class == &devlink_class)
+		return;
 
 	/*
 	 * Delete all of the remaining links from this device to any other
@@ -1143,13 +1645,698 @@ static void device_links_purge(struct device *dev)
 	device_links_write_unlock();
 }
 
+#define FW_DEVLINK_FLAGS_PERMISSIVE	(DL_FLAG_INFERRED | \
+					 DL_FLAG_SYNC_STATE_ONLY)
+#define FW_DEVLINK_FLAGS_ON		(DL_FLAG_INFERRED | \
+					 DL_FLAG_AUTOPROBE_CONSUMER)
+#define FW_DEVLINK_FLAGS_RPM		(FW_DEVLINK_FLAGS_ON | \
+					 DL_FLAG_PM_RUNTIME)
+
+static u32 fw_devlink_flags = FW_DEVLINK_FLAGS_RPM;
+static int __init fw_devlink_setup(char *arg)
+{
+	if (!arg)
+		return -EINVAL;
+
+	if (strcmp(arg, "off") == 0) {
+		fw_devlink_flags = 0;
+	} else if (strcmp(arg, "permissive") == 0) {
+		fw_devlink_flags = FW_DEVLINK_FLAGS_PERMISSIVE;
+	} else if (strcmp(arg, "on") == 0) {
+		fw_devlink_flags = FW_DEVLINK_FLAGS_ON;
+	} else if (strcmp(arg, "rpm") == 0) {
+		fw_devlink_flags = FW_DEVLINK_FLAGS_RPM;
+	}
+	return 0;
+}
+early_param("fw_devlink", fw_devlink_setup);
+
+static bool fw_devlink_strict;
+static int __init fw_devlink_strict_setup(char *arg)
+{
+	return kstrtobool(arg, &fw_devlink_strict);
+}
+early_param("fw_devlink.strict", fw_devlink_strict_setup);
+
+#define FW_DEVLINK_SYNC_STATE_STRICT	0
+#define FW_DEVLINK_SYNC_STATE_TIMEOUT	1
+
+#ifndef CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT
+static int fw_devlink_sync_state;
+#else
+static int fw_devlink_sync_state = FW_DEVLINK_SYNC_STATE_TIMEOUT;
+#endif
+
+static int __init fw_devlink_sync_state_setup(char *arg)
+{
+	if (!arg)
+		return -EINVAL;
+
+	if (strcmp(arg, "strict") == 0) {
+		fw_devlink_sync_state = FW_DEVLINK_SYNC_STATE_STRICT;
+		return 0;
+	} else if (strcmp(arg, "timeout") == 0) {
+		fw_devlink_sync_state = FW_DEVLINK_SYNC_STATE_TIMEOUT;
+		return 0;
+	}
+	return -EINVAL;
+}
+early_param("fw_devlink.sync_state", fw_devlink_sync_state_setup);
+
+static inline u32 fw_devlink_get_flags(u8 fwlink_flags)
+{
+	if (fwlink_flags & FWLINK_FLAG_CYCLE)
+		return FW_DEVLINK_FLAGS_PERMISSIVE | DL_FLAG_CYCLE;
+
+	return fw_devlink_flags;
+}
+
+static bool fw_devlink_is_permissive(void)
+{
+	return fw_devlink_flags == FW_DEVLINK_FLAGS_PERMISSIVE;
+}
+
+bool fw_devlink_is_strict(void)
+{
+	return fw_devlink_strict && !fw_devlink_is_permissive();
+}
+
+static void fw_devlink_parse_fwnode(struct fwnode_handle *fwnode)
+{
+	if (fwnode->flags & FWNODE_FLAG_LINKS_ADDED)
+		return;
+
+	fwnode_call_int_op(fwnode, add_links);
+	fwnode->flags |= FWNODE_FLAG_LINKS_ADDED;
+}
+
+static void fw_devlink_parse_fwtree(struct fwnode_handle *fwnode)
+{
+	struct fwnode_handle *child = NULL;
+
+	fw_devlink_parse_fwnode(fwnode);
+
+	while ((child = fwnode_get_next_available_child_node(fwnode, child)))
+		fw_devlink_parse_fwtree(child);
+}
+
+static void fw_devlink_relax_link(struct device_link *link)
+{
+	if (!device_link_test(link, DL_FLAG_INFERRED))
+		return;
+
+	if (device_link_flag_is_sync_state_only(link->flags))
+		return;
+
+	pm_runtime_drop_link(link);
+	link->flags = DL_FLAG_MANAGED | FW_DEVLINK_FLAGS_PERMISSIVE;
+	dev_dbg(link->consumer, "Relaxing link with %s\n",
+		dev_name(link->supplier));
+}
+
+static int fw_devlink_no_driver(struct device *dev, void *data)
+{
+	struct device_link *link = to_devlink(dev);
+
+	if (!link->supplier->can_match)
+		fw_devlink_relax_link(link);
+
+	return 0;
+}
+
+void fw_devlink_drivers_done(void)
+{
+	fw_devlink_drv_reg_done = true;
+	device_links_write_lock();
+	class_for_each_device(&devlink_class, NULL, NULL,
+			      fw_devlink_no_driver);
+	device_links_write_unlock();
+}
+
+static int fw_devlink_dev_sync_state(struct device *dev, void *data)
+{
+	struct device_link *link = to_devlink(dev);
+	struct device *sup = link->supplier;
+
+	if (!device_link_test(link, DL_FLAG_MANAGED) ||
+	    link->status == DL_STATE_ACTIVE || sup->state_synced ||
+	    !dev_has_sync_state(sup))
+		return 0;
+
+	if (fw_devlink_sync_state == FW_DEVLINK_SYNC_STATE_STRICT) {
+		dev_info(sup, "sync_state() pending due to %s\n",
+			 dev_name(link->consumer));
+		return 0;
+	}
+
+	if (!list_empty(&sup->links.defer_sync))
+		return 0;
+
+	dev_warn(sup, "Timed out. Forcing sync_state()\n");
+	sup->state_synced = true;
+	get_device(sup);
+	list_add_tail(&sup->links.defer_sync, data);
+
+	return 0;
+}
+
+void fw_devlink_probing_done(void)
+{
+	LIST_HEAD(sync_list);
+
+	device_links_write_lock();
+	class_for_each_device(&devlink_class, NULL, &sync_list,
+			      fw_devlink_dev_sync_state);
+	device_links_write_unlock();
+	device_links_flush_sync_list(&sync_list, NULL);
+}
+
+/**
+ * wait_for_init_devices_probe - Try to probe any device needed for init
+ *
+ * Some devices might need to be probed and bound successfully before the kernel
+ * boot sequence can finish and move on to init/userspace. For example, a
+ * network interface might need to be bound to be able to mount a NFS rootfs.
+ *
+ * With fw_devlink=on by default, some of these devices might be blocked from
+ * probing because they are waiting on a optional supplier that doesn't have a
+ * driver. While fw_devlink will eventually identify such devices and unblock
+ * the probing automatically, it might be too late by the time it unblocks the
+ * probing of devices. For example, the IP4 autoconfig might timeout before
+ * fw_devlink unblocks probing of the network interface.
+ *
+ * This function is available to temporarily try and probe all devices that have
+ * a driver even if some of their suppliers haven't been added or don't have
+ * drivers.
+ *
+ * The drivers can then decide which of the suppliers are optional vs mandatory
+ * and probe the device if possible. By the time this function returns, all such
+ * "best effort" probes are guaranteed to be completed. If a device successfully
+ * probes in this mode, we delete all fw_devlink discovered dependencies of that
+ * device where the supplier hasn't yet probed successfully because they have to
+ * be optional dependencies.
+ *
+ * Any devices that didn't successfully probe go back to being treated as if
+ * this function was never called.
+ *
+ * This also means that some devices that aren't needed for init and could have
+ * waited for their optional supplier to probe (when the supplier's module is
+ * loaded later on) would end up probing prematurely with limited functionality.
+ * So call this function only when boot would fail without it.
+ */
+void __init wait_for_init_devices_probe(void)
+{
+	if (!fw_devlink_flags || fw_devlink_is_permissive())
+		return;
+
+	/*
+	 * Wait for all ongoing probes to finish so that the "best effort" is
+	 * only applied to devices that can't probe otherwise.
+	 */
+	wait_for_device_probe();
+
+	pr_info("Trying to probe devices needed for running init ...\n");
+	fw_devlink_best_effort = true;
+	driver_deferred_probe_trigger();
+
+	/*
+	 * Wait for all "best effort" probes to finish before going back to
+	 * normal enforcement.
+	 */
+	wait_for_device_probe();
+	fw_devlink_best_effort = false;
+}
+
+static void fw_devlink_unblock_consumers(struct device *dev)
+{
+	struct device_link *link;
+
+	if (!fw_devlink_flags || fw_devlink_is_permissive())
+		return;
+
+	device_links_write_lock();
+	list_for_each_entry(link, &dev->links.consumers, s_node)
+		fw_devlink_relax_link(link);
+	device_links_write_unlock();
+}
+
+static bool fwnode_init_without_drv(struct fwnode_handle *fwnode)
+{
+	struct device *dev;
+	bool ret;
+
+	if (!(fwnode->flags & FWNODE_FLAG_INITIALIZED))
+		return false;
+
+	dev = get_dev_from_fwnode(fwnode);
+	ret = !dev || dev->links.status == DL_DEV_NO_DRIVER;
+	put_device(dev);
+
+	return ret;
+}
+
+static bool fwnode_ancestor_init_without_drv(struct fwnode_handle *fwnode)
+{
+	struct fwnode_handle *parent;
+
+	fwnode_for_each_parent_node(fwnode, parent) {
+		if (fwnode_init_without_drv(parent)) {
+			fwnode_handle_put(parent);
+			return true;
+		}
+	}
+
+	return false;
+}
+
+/**
+ * fwnode_is_ancestor_of - Test if @ancestor is ancestor of @child
+ * @ancestor: Firmware which is tested for being an ancestor
+ * @child: Firmware which is tested for being the child
+ *
+ * A node is considered an ancestor of itself too.
+ *
+ * Return: true if @ancestor is an ancestor of @child. Otherwise, returns false.
+ */
+static bool fwnode_is_ancestor_of(const struct fwnode_handle *ancestor,
+				  const struct fwnode_handle *child)
+{
+	struct fwnode_handle *parent;
+
+	if (IS_ERR_OR_NULL(ancestor))
+		return false;
+
+	if (child == ancestor)
+		return true;
+
+	fwnode_for_each_parent_node(child, parent) {
+		if (parent == ancestor) {
+			fwnode_handle_put(parent);
+			return true;
+		}
+	}
+	return false;
+}
+
+/**
+ * fwnode_get_next_parent_dev - Find device of closest ancestor fwnode
+ * @fwnode: firmware node
+ *
+ * Given a firmware node (@fwnode), this function finds its closest ancestor
+ * firmware node that has a corresponding struct device and returns that struct
+ * device.
+ *
+ * The caller is responsible for calling put_device() on the returned device
+ * pointer.
+ *
+ * Return: a pointer to the device of the @fwnode's closest ancestor.
+ */
+static struct device *fwnode_get_next_parent_dev(const struct fwnode_handle *fwnode)
+{
+	struct fwnode_handle *parent;
+	struct device *dev;
+
+	fwnode_for_each_parent_node(fwnode, parent) {
+		dev = get_dev_from_fwnode(parent);
+		if (dev) {
+			fwnode_handle_put(parent);
+			return dev;
+		}
+	}
+	return NULL;
+}
+
+/**
+ * __fw_devlink_relax_cycles - Relax and mark dependency cycles.
+ * @con_handle: Potential consumer device fwnode.
+ * @sup_handle: Potential supplier's fwnode.
+ *
+ * Needs to be called with fwnode_lock and device link lock held.
+ *
+ * Check if @sup_handle or any of its ancestors or suppliers direct/indirectly
+ * depend on @con. This function can detect multiple cyles between @sup_handle
+ * and @con. When such dependency cycles are found, convert all device links
+ * created solely by fw_devlink into SYNC_STATE_ONLY device links. Also, mark
+ * all fwnode links in the cycle with FWLINK_FLAG_CYCLE so that when they are
+ * converted into a device link in the future, they are created as
+ * SYNC_STATE_ONLY device links. This is the equivalent of doing
+ * fw_devlink=permissive just between the devices in the cycle. We need to do
+ * this because, at this point, fw_devlink can't tell which of these
+ * dependencies is not a real dependency.
+ *
+ * Return true if one or more cycles were found. Otherwise, return false.
+ */
+static bool __fw_devlink_relax_cycles(struct fwnode_handle *con_handle,
+				 struct fwnode_handle *sup_handle)
+{
+	struct device *sup_dev = NULL, *par_dev = NULL, *con_dev = NULL;
+	struct fwnode_link *link;
+	struct device_link *dev_link;
+	bool ret = false;
+
+	if (!sup_handle)
+		return false;
+
+	/*
+	 * We aren't trying to find all cycles. Just a cycle between con and
+	 * sup_handle.
+	 */
+	if (sup_handle->flags & FWNODE_FLAG_VISITED)
+		return false;
+
+	sup_handle->flags |= FWNODE_FLAG_VISITED;
+
+	/* Termination condition. */
+	if (sup_handle == con_handle) {
+		pr_debug("----- cycle: start -----\n");
+		ret = true;
+		goto out;
+	}
+
+	sup_dev = get_dev_from_fwnode(sup_handle);
+	con_dev = get_dev_from_fwnode(con_handle);
+	/*
+	 * If sup_dev is bound to a driver and @con hasn't started binding to a
+	 * driver, sup_dev can't be a consumer of @con. So, no need to check
+	 * further.
+	 */
+	if (sup_dev && sup_dev->links.status ==  DL_DEV_DRIVER_BOUND &&
+	    con_dev && con_dev->links.status == DL_DEV_NO_DRIVER) {
+		ret = false;
+		goto out;
+	}
+
+	list_for_each_entry(link, &sup_handle->suppliers, c_hook) {
+		if (link->flags & FWLINK_FLAG_IGNORE)
+			continue;
+
+		if (__fw_devlink_relax_cycles(con_handle, link->supplier)) {
+			__fwnode_link_cycle(link);
+			ret = true;
+		}
+	}
+
+	/*
+	 * Give priority to device parent over fwnode parent to account for any
+	 * quirks in how fwnodes are converted to devices.
+	 */
+	if (sup_dev)
+		par_dev = get_device(sup_dev->parent);
+	else
+		par_dev = fwnode_get_next_parent_dev(sup_handle);
+
+	if (par_dev && __fw_devlink_relax_cycles(con_handle, par_dev->fwnode)) {
+		pr_debug("%pfwf: cycle: child of %pfwf\n", sup_handle,
+			 par_dev->fwnode);
+		ret = true;
+	}
+
+	if (!sup_dev)
+		goto out;
+
+	list_for_each_entry(dev_link, &sup_dev->links.suppliers, c_node) {
+		/*
+		 * Ignore a SYNC_STATE_ONLY flag only if it wasn't marked as
+		 * such due to a cycle.
+		 */
+		if (device_link_flag_is_sync_state_only(dev_link->flags) &&
+		    !device_link_test(dev_link, DL_FLAG_CYCLE))
+			continue;
+
+		if (__fw_devlink_relax_cycles(con_handle,
+					      dev_link->supplier->fwnode)) {
+			pr_debug("%pfwf: cycle: depends on %pfwf\n", sup_handle,
+				 dev_link->supplier->fwnode);
+			fw_devlink_relax_link(dev_link);
+			dev_link->flags |= DL_FLAG_CYCLE;
+			ret = true;
+		}
+	}
+
+out:
+	sup_handle->flags &= ~FWNODE_FLAG_VISITED;
+	put_device(sup_dev);
+	put_device(con_dev);
+	put_device(par_dev);
+	return ret;
+}
+
+/**
+ * fw_devlink_create_devlink - Create a device link from a consumer to fwnode
+ * @con: consumer device for the device link
+ * @sup_handle: fwnode handle of supplier
+ * @link: fwnode link that's being converted to a device link
+ *
+ * This function will try to create a device link between the consumer device
+ * @con and the supplier device represented by @sup_handle.
+ *
+ * The supplier has to be provided as a fwnode because incorrect cycles in
+ * fwnode links can sometimes cause the supplier device to never be created.
+ * This function detects such cases and returns an error if it cannot create a
+ * device link from the consumer to a missing supplier.
+ *
+ * Returns,
+ * 0 on successfully creating a device link
+ * -EINVAL if the device link cannot be created as expected
+ * -EAGAIN if the device link cannot be created right now, but it may be
+ *  possible to do that in the future
+ */
+static int fw_devlink_create_devlink(struct device *con,
+				     struct fwnode_handle *sup_handle,
+				     struct fwnode_link *link)
+{
+	struct device *sup_dev;
+	int ret = 0;
+	u32 flags;
+
+	if (link->flags & FWLINK_FLAG_IGNORE)
+		return 0;
+
+	/*
+	 * In some cases, a device P might also be a supplier to its child node
+	 * C. However, this would defer the probe of C until the probe of P
+	 * completes successfully. This is perfectly fine in the device driver
+	 * model. device_add() doesn't guarantee probe completion of the device
+	 * by the time it returns.
+	 *
+	 * However, there are a few drivers that assume C will finish probing
+	 * as soon as it's added and before P finishes probing. So, we provide
+	 * a flag to let fw_devlink know not to delay the probe of C until the
+	 * probe of P completes successfully.
+	 *
+	 * When such a flag is set, we can't create device links where P is the
+	 * supplier of C as that would delay the probe of C.
+	 */
+	if (sup_handle->flags & FWNODE_FLAG_NEEDS_CHILD_BOUND_ON_ADD &&
+	    fwnode_is_ancestor_of(sup_handle, con->fwnode))
+		return -EINVAL;
+
+	/*
+	 * Don't try to optimize by not calling the cycle detection logic under
+	 * certain conditions. There's always some corner case that won't get
+	 * detected.
+	 */
+	device_links_write_lock();
+	if (__fw_devlink_relax_cycles(link->consumer, sup_handle)) {
+		__fwnode_link_cycle(link);
+		pr_debug("----- cycle: end -----\n");
+		pr_info("%pfwf: Fixed dependency cycle(s) with %pfwf\n",
+			link->consumer, sup_handle);
+	}
+	device_links_write_unlock();
+
+	if (con->fwnode == link->consumer)
+		flags = fw_devlink_get_flags(link->flags);
+	else
+		flags = FW_DEVLINK_FLAGS_PERMISSIVE;
+
+	if (sup_handle->flags & FWNODE_FLAG_NOT_DEVICE)
+		sup_dev = fwnode_get_next_parent_dev(sup_handle);
+	else
+		sup_dev = get_dev_from_fwnode(sup_handle);
+
+	if (sup_dev) {
+		/*
+		 * If it's one of those drivers that don't actually bind to
+		 * their device using driver core, then don't wait on this
+		 * supplier device indefinitely.
+		 */
+		if (sup_dev->links.status == DL_DEV_NO_DRIVER &&
+		    sup_handle->flags & FWNODE_FLAG_INITIALIZED) {
+			dev_dbg(con,
+				"Not linking %pfwf - dev might never probe\n",
+				sup_handle);
+			ret = -EINVAL;
+			goto out;
+		}
+
+		if (con != sup_dev && !device_link_add(con, sup_dev, flags)) {
+			dev_err(con, "Failed to create device link (0x%x) with supplier %s for %pfwf\n",
+				flags, dev_name(sup_dev), link->consumer);
+			ret = -EINVAL;
+		}
+
+		goto out;
+	}
+
+	/*
+	 * Supplier or supplier's ancestor already initialized without a struct
+	 * device or being probed by a driver.
+	 */
+	if (fwnode_init_without_drv(sup_handle) ||
+	    fwnode_ancestor_init_without_drv(sup_handle)) {
+		dev_dbg(con, "Not linking %pfwf - might never become dev\n",
+			sup_handle);
+		return -EINVAL;
+	}
+
+	ret = -EAGAIN;
+out:
+	put_device(sup_dev);
+	return ret;
+}
+
+/**
+ * __fw_devlink_link_to_consumers - Create device links to consumers of a device
+ * @dev: Device that needs to be linked to its consumers
+ *
+ * This function looks at all the consumer fwnodes of @dev and creates device
+ * links between the consumer device and @dev (supplier).
+ *
+ * If the consumer device has not been added yet, then this function creates a
+ * SYNC_STATE_ONLY link between @dev (supplier) and the closest ancestor device
+ * of the consumer fwnode. This is necessary to make sure @dev doesn't get a
+ * sync_state() callback before the real consumer device gets to be added and
+ * then probed.
+ *
+ * Once device links are created from the real consumer to @dev (supplier), the
+ * fwnode links are deleted.
+ */
+static void __fw_devlink_link_to_consumers(struct device *dev)
+{
+	struct fwnode_handle *fwnode = dev->fwnode;
+	struct fwnode_link *link, *tmp;
+
+	list_for_each_entry_safe(link, tmp, &fwnode->consumers, s_hook) {
+		struct device *con_dev;
+		bool own_link = true;
+		int ret;
+
+		con_dev = get_dev_from_fwnode(link->consumer);
+		/*
+		 * If consumer device is not available yet, make a "proxy"
+		 * SYNC_STATE_ONLY link from the consumer's parent device to
+		 * the supplier device. This is necessary to make sure the
+		 * supplier doesn't get a sync_state() callback before the real
+		 * consumer can create a device link to the supplier.
+		 *
+		 * This proxy link step is needed to handle the case where the
+		 * consumer's parent device is added before the supplier.
+		 */
+		if (!con_dev) {
+			con_dev = fwnode_get_next_parent_dev(link->consumer);
+			/*
+			 * However, if the consumer's parent device is also the
+			 * parent of the supplier, don't create a
+			 * consumer-supplier link from the parent to its child
+			 * device. Such a dependency is impossible.
+			 */
+			if (con_dev &&
+			    fwnode_is_ancestor_of(con_dev->fwnode, fwnode)) {
+				put_device(con_dev);
+				con_dev = NULL;
+			} else {
+				own_link = false;
+			}
+		}
+
+		if (!con_dev)
+			continue;
+
+		ret = fw_devlink_create_devlink(con_dev, fwnode, link);
+		put_device(con_dev);
+		if (!own_link || ret == -EAGAIN)
+			continue;
+
+		__fwnode_link_del(link);
+	}
+}
+
+/**
+ * __fw_devlink_link_to_suppliers - Create device links to suppliers of a device
+ * @dev: The consumer device that needs to be linked to its suppliers
+ * @fwnode: Root of the fwnode tree that is used to create device links
+ *
+ * This function looks at all the supplier fwnodes of fwnode tree rooted at
+ * @fwnode and creates device links between @dev (consumer) and all the
+ * supplier devices of the entire fwnode tree at @fwnode.
+ *
+ * The function creates normal (non-SYNC_STATE_ONLY) device links between @dev
+ * and the real suppliers of @dev. Once these device links are created, the
+ * fwnode links are deleted.
+ *
+ * In addition, it also looks at all the suppliers of the entire fwnode tree
+ * because some of the child devices of @dev that have not been added yet
+ * (because @dev hasn't probed) might already have their suppliers added to
+ * driver core. So, this function creates SYNC_STATE_ONLY device links between
+ * @dev (consumer) and these suppliers to make sure they don't execute their
+ * sync_state() callbacks before these child devices have a chance to create
+ * their device links. The fwnode links that correspond to the child devices
+ * aren't delete because they are needed later to create the device links
+ * between the real consumer and supplier devices.
+ */
+static void __fw_devlink_link_to_suppliers(struct device *dev,
+					   struct fwnode_handle *fwnode)
+{
+	bool own_link = (dev->fwnode == fwnode);
+	struct fwnode_link *link, *tmp;
+	struct fwnode_handle *child = NULL;
+
+	list_for_each_entry_safe(link, tmp, &fwnode->suppliers, c_hook) {
+		int ret;
+		struct fwnode_handle *sup = link->supplier;
+
+		ret = fw_devlink_create_devlink(dev, sup, link);
+		if (!own_link || ret == -EAGAIN)
+			continue;
+
+		__fwnode_link_del(link);
+	}
+
+	/*
+	 * Make "proxy" SYNC_STATE_ONLY device links to represent the needs of
+	 * all the descendants. This proxy link step is needed to handle the
+	 * case where the supplier is added before the consumer's parent device
+	 * (@dev).
+	 */
+	while ((child = fwnode_get_next_available_child_node(fwnode, child)))
+		__fw_devlink_link_to_suppliers(dev, child);
+}
+
+static void fw_devlink_link_device(struct device *dev)
+{
+	struct fwnode_handle *fwnode = dev->fwnode;
+
+	if (!fw_devlink_flags)
+		return;
+
+	fw_devlink_parse_fwtree(fwnode);
+
+	guard(mutex)(&fwnode_link_lock);
+
+	__fw_devlink_link_to_consumers(dev);
+	__fw_devlink_link_to_suppliers(dev, fwnode);
+}
+
 /* Device links support end. */
 
-int (*platform_notify)(struct device *dev) = NULL;
-int (*platform_notify_remove)(struct device *dev) = NULL;
 static struct kobject *dev_kobj;
-struct kobject *sysfs_dev_char_kobj;
-struct kobject *sysfs_dev_block_kobj;
+
+/* /sys/dev/char */
+static struct kobject *sysfs_dev_char_kobj;
+
+/* /sys/dev/block */
+static struct kobject *sysfs_dev_block_kobj;
 
 static DEFINE_MUTEX(device_hotplug_lock);
 
@@ -1185,24 +2372,18 @@ static inline int device_is_not_partition(struct device *dev)
 }
 #endif
 
-static int
-device_platform_notify(struct device *dev, enum kobject_action action)
+static void device_platform_notify(struct device *dev)
 {
-	int ret;
+	acpi_device_notify(dev);
 
-	ret = acpi_platform_notify(dev, action);
-	if (ret)
-		return ret;
+	software_node_notify(dev);
+}
 
-	ret = software_node_notify(dev, action);
-	if (ret)
-		return ret;
+static void device_platform_notify_remove(struct device *dev)
+{
+	software_node_notify_remove(dev);
 
-	if (platform_notify && action == KOBJ_ADD)
-		platform_notify(dev);
-	else if (platform_notify_remove && action == KOBJ_REMOVE)
-		platform_notify_remove(dev);
-	return 0;
+	acpi_device_notify_remove(dev);
 }
 
 /**
@@ -1223,9 +2404,7 @@ const char *dev_driver_string(const struct device *dev)
 	 * never change once they are set, so they don't need special care.
 	 */
 	drv = READ_ONCE(dev->driver);
-	return drv ? drv->name :
-			(dev->bus ? dev->bus->name :
-			(dev->class ? dev->class->name : ""));
+	return drv ? drv->name : dev_bus_name(dev);
 }
 EXPORT_SYMBOL(dev_driver_string);
 
@@ -1288,7 +2467,7 @@ ssize_t device_show_ulong(struct device *dev,
 			  char *buf)
 {
 	struct dev_ext_attribute *ea = to_ext_attr(attr);
-	return snprintf(buf, PAGE_SIZE, "%lx\n", *(unsigned long *)(ea->var));
+	return sysfs_emit(buf, "%lx\n", *(unsigned long *)(ea->var));
 }
 EXPORT_SYMBOL_GPL(device_show_ulong);
 
@@ -1318,7 +2497,7 @@ ssize_t device_show_int(struct device *dev,
 {
 	struct dev_ext_attribute *ea = to_ext_attr(attr);
 
-	return snprintf(buf, PAGE_SIZE, "%d\n", *(int *)(ea->var));
+	return sysfs_emit(buf, "%d\n", *(int *)(ea->var));
 }
 EXPORT_SYMBOL_GPL(device_show_int);
 
@@ -1327,7 +2506,7 @@ ssize_t device_store_bool(struct device *dev, struct device_attribute *attr,
 {
 	struct dev_ext_attribute *ea = to_ext_attr(attr);
 
-	if (strtobool(buf, ea->var) < 0)
+	if (kstrtobool(buf, ea->var) < 0)
 		return -EINVAL;
 
 	return size;
@@ -1339,10 +2518,19 @@ ssize_t device_show_bool(struct device *dev, struct device_attribute *attr,
 {
 	struct dev_ext_attribute *ea = to_ext_attr(attr);
 
-	return snprintf(buf, PAGE_SIZE, "%d\n", *(bool *)(ea->var));
+	return sysfs_emit(buf, "%d\n", *(bool *)(ea->var));
 }
 EXPORT_SYMBOL_GPL(device_show_bool);
 
+ssize_t device_show_string(struct device *dev,
+			   struct device_attribute *attr, char *buf)
+{
+	struct dev_ext_attribute *ea = to_ext_attr(attr);
+
+	return sysfs_emit(buf, "%s\n", (char *)ea->var);
+}
+EXPORT_SYMBOL_GPL(device_show_string);
+
 /**
  * device_release - free device structure.
  * @kobj: device's kobject.
@@ -1367,6 +2555,8 @@ static void device_release(struct kobject *kobj)
 	 */
 	devres_release_all(dev);
 
+	kfree(dev->dma_range_map);
+
 	if (dev->release)
 		dev->release(dev);
 	else if (dev->type && dev->type->release)
@@ -1374,31 +2564,31 @@ static void device_release(struct kobject *kobj)
 	else if (dev->class && dev->class->dev_release)
 		dev->class->dev_release(dev);
 	else
-		WARN(1, KERN_ERR "Device '%s' does not have a release() function, it is broken and must be fixed. See Documentation/kobject.txt.\n",
+		WARN(1, KERN_ERR "Device '%s' does not have a release() function, it is broken and must be fixed. See Documentation/core-api/kobject.rst.\n",
 			dev_name(dev));
 	kfree(p);
 }
 
-static const void *device_namespace(struct kobject *kobj)
+static const void *device_namespace(const struct kobject *kobj)
 {
-	struct device *dev = kobj_to_dev(kobj);
+	const struct device *dev = kobj_to_dev(kobj);
 	const void *ns = NULL;
 
-	if (dev->class && dev->class->ns_type)
+	if (dev->class && dev->class->namespace)
 		ns = dev->class->namespace(dev);
 
 	return ns;
 }
 
-static void device_get_ownership(struct kobject *kobj, kuid_t *uid, kgid_t *gid)
+static void device_get_ownership(const struct kobject *kobj, kuid_t *uid, kgid_t *gid)
 {
-	struct device *dev = kobj_to_dev(kobj);
+	const struct device *dev = kobj_to_dev(kobj);
 
 	if (dev->class && dev->class->get_ownership)
 		dev->class->get_ownership(dev, uid, gid);
 }
 
-static struct kobj_type device_ktype = {
+static const struct kobj_type device_ktype = {
 	.release	= device_release,
 	.sysfs_ops	= &dev_sysfs_ops,
 	.namespace	= device_namespace,
@@ -1406,12 +2596,12 @@ static struct kobj_type device_ktype = {
 };
 
 
-static int dev_uevent_filter(struct kset *kset, struct kobject *kobj)
+static int dev_uevent_filter(const struct kobject *kobj)
 {
-	struct kobj_type *ktype = get_ktype(kobj);
+	const struct kobj_type *ktype = get_ktype(kobj);
 
 	if (ktype == &device_ktype) {
-		struct device *dev = kobj_to_dev(kobj);
+		const struct device *dev = kobj_to_dev(kobj);
 		if (dev->bus)
 			return 1;
 		if (dev->class)
@@ -1420,9 +2610,9 @@ static int dev_uevent_filter(struct kset *kset, struct kobject *kobj)
 	return 0;
 }
 
-static const char *dev_uevent_name(struct kset *kset, struct kobject *kobj)
+static const char *dev_uevent_name(const struct kobject *kobj)
 {
-	struct device *dev = kobj_to_dev(kobj);
+	const struct device *dev = kobj_to_dev(kobj);
 
 	if (dev->bus)
 		return dev->bus->name;
@@ -1431,10 +2621,38 @@ static const char *dev_uevent_name(struct kset *kset, struct kobject *kobj)
 	return NULL;
 }
 
-static int dev_uevent(struct kset *kset, struct kobject *kobj,
-		      struct kobj_uevent_env *env)
+/*
+ * Try filling "DRIVER=<name>" uevent variable for a device. Because this
+ * function may race with binding and unbinding the device from a driver,
+ * we need to be careful. Binding is generally safe, at worst we miss the
+ * fact that the device is already bound to a driver (but the driver
+ * information that is delivered through uevents is best-effort, it may
+ * become obsolete as soon as it is generated anyways). Unbinding is more
+ * risky as driver pointer is transitioning to NULL, so READ_ONCE() should
+ * be used to make sure we are dealing with the same pointer, and to
+ * ensure that driver structure is not going to disappear from under us
+ * we take bus' drivers klist lock. The assumption that only registered
+ * driver can be bound to a device, and to unregister a driver bus code
+ * will take the same lock.
+ */
+static void dev_driver_uevent(const struct device *dev, struct kobj_uevent_env *env)
 {
-	struct device *dev = kobj_to_dev(kobj);
+	struct subsys_private *sp = bus_to_subsys(dev->bus);
+
+	if (sp) {
+		scoped_guard(spinlock, &sp->klist_drivers.k_lock) {
+			struct device_driver *drv = READ_ONCE(dev->driver);
+			if (drv)
+				add_uevent_var(env, "DRIVER=%s", drv->name);
+		}
+
+		subsys_put(sp);
+	}
+}
+
+static int dev_uevent(const struct kobject *kobj, struct kobj_uevent_env *env)
+{
+	const struct device *dev = kobj_to_dev(kobj);
 	int retval = 0;
 
 	/* add device node properties if present */
@@ -1463,8 +2681,8 @@ static int dev_uevent(struct kset *kset, struct kobject *kobj,
 	if (dev->type && dev->type->name)
 		add_uevent_var(env, "DEVTYPE=%s", dev->type->name);
 
-	if (dev->driver)
-		add_uevent_var(env, "DRIVER=%s", dev->driver->name);
+	/* Add "DRIVER=%s" variable if the device is bound to a driver */
+	dev_driver_uevent(dev, env);
 
 	/* Add common DT information about the device */
 	of_device_uevent(dev, env);
@@ -1511,7 +2729,7 @@ static ssize_t uevent_show(struct device *dev, struct device_attribute *attr,
 	struct kset *kset;
 	struct kobj_uevent_env *env = NULL;
 	int i;
-	size_t count = 0;
+	int len = 0;
 	int retval;
 
 	/* search the kset, the device belongs to */
@@ -1527,7 +2745,7 @@ static ssize_t uevent_show(struct device *dev, struct device_attribute *attr,
 
 	/* respect filter */
 	if (kset->uevent_ops && kset->uevent_ops->filter)
-		if (!kset->uevent_ops->filter(kset, &dev->kobj))
+		if (!kset->uevent_ops->filter(&dev->kobj))
 			goto out;
 
 	env = kzalloc(sizeof(struct kobj_uevent_env), GFP_KERNEL);
@@ -1535,16 +2753,16 @@ static ssize_t uevent_show(struct device *dev, struct device_attribute *attr,
 		return -ENOMEM;
 
 	/* let the kset specific function add its keys */
-	retval = kset->uevent_ops->uevent(kset, &dev->kobj, env);
+	retval = kset->uevent_ops->uevent(&dev->kobj, env);
 	if (retval)
 		goto out;
 
 	/* copy keys to file */
 	for (i = 0; i < env->envp_idx; i++)
-		count += sprintf(&buf[count], "%s\n", env->envp[i]);
+		len += sysfs_emit_at(buf, len, "%s\n", env->envp[i]);
 out:
 	kfree(env);
-	return count;
+	return len;
 }
 
 static ssize_t uevent_store(struct device *dev, struct device_attribute *attr,
@@ -1555,7 +2773,7 @@ static ssize_t uevent_store(struct device *dev, struct device_attribute *attr,
 	rc = kobject_synth_uevent(&dev->kobj, buf, count);
 
 	if (rc) {
-		dev_err(dev, "uevent: failed to send synthetic uevent\n");
+		dev_err(dev, "uevent: failed to send synthetic uevent: %d\n", rc);
 		return rc;
 	}
 
@@ -1571,7 +2789,7 @@ static ssize_t online_show(struct device *dev, struct device_attribute *attr,
 	device_lock(dev);
 	val = !dev->offline;
 	device_unlock(dev);
-	return sprintf(buf, "%u\n", val);
+	return sysfs_emit(buf, "%u\n", val);
 }
 
 static ssize_t online_store(struct device *dev, struct device_attribute *attr,
@@ -1580,7 +2798,7 @@ static ssize_t online_store(struct device *dev, struct device_attribute *attr,
 	bool val;
 	int ret;
 
-	ret = strtobool(buf, &val);
+	ret = kstrtobool(buf, &val);
 	if (ret < 0)
 		return ret;
 
@@ -1594,6 +2812,25 @@ static ssize_t online_store(struct device *dev, struct device_attribute *attr,
 }
 static DEVICE_ATTR_RW(online);
 
+static ssize_t removable_show(struct device *dev, struct device_attribute *attr,
+			      char *buf)
+{
+	const char *loc;
+
+	switch (dev->removable) {
+	case DEVICE_REMOVABLE:
+		loc = "removable";
+		break;
+	case DEVICE_FIXED:
+		loc = "fixed";
+		break;
+	default:
+		loc = "unknown";
+	}
+	return sysfs_emit(buf, "%s\n", loc);
+}
+static DEVICE_ATTR_RO(removable);
+
 int device_add_groups(struct device *dev, const struct attribute_group **groups)
 {
 	return sysfs_create_groups(&dev->kobj, groups);
@@ -1612,11 +2849,6 @@ union device_attr_group_devres {
 	const struct attribute_group **groups;
 };
 
-static int devm_attr_group_match(struct device *dev, void *res, void *data)
-{
-	return ((union device_attr_group_devres *)res)->group == data;
-}
-
 static void devm_attr_group_remove(struct device *dev, void *res)
 {
 	union device_attr_group_devres *devres = res;
@@ -1626,15 +2858,6 @@ static void devm_attr_group_remove(struct device *dev, void *res)
 	sysfs_remove_group(&dev->kobj, group);
 }
 
-static void devm_attr_groups_remove(struct device *dev, void *res)
-{
-	union device_attr_group_devres *devres = res;
-	const struct attribute_group **groups = devres->groups;
-
-	dev_dbg(dev, "%s: removing groups %p\n", __func__, groups);
-	sysfs_remove_groups(&dev->kobj, groups);
-}
-
 /**
  * devm_device_add_group - given a device, create a managed attribute group
  * @dev:	The device to create the group for
@@ -1667,79 +2890,9 @@ int devm_device_add_group(struct device *dev, const struct attribute_group *grp)
 }
 EXPORT_SYMBOL_GPL(devm_device_add_group);
 
-/**
- * devm_device_remove_group: remove a managed group from a device
- * @dev:	device to remove the group from
- * @grp:	group to remove
- *
- * This function removes a group of attributes from a device. The attributes
- * previously have to have been created for this group, otherwise it will fail.
- */
-void devm_device_remove_group(struct device *dev,
-			      const struct attribute_group *grp)
-{
-	WARN_ON(devres_release(dev, devm_attr_group_remove,
-			       devm_attr_group_match,
-			       /* cast away const */ (void *)grp));
-}
-EXPORT_SYMBOL_GPL(devm_device_remove_group);
-
-/**
- * devm_device_add_groups - create a bunch of managed attribute groups
- * @dev:	The device to create the group for
- * @groups:	The attribute groups to create, NULL terminated
- *
- * This function creates a bunch of managed attribute groups.  If an error
- * occurs when creating a group, all previously created groups will be
- * removed, unwinding everything back to the original state when this
- * function was called.  It will explicitly warn and error if any of the
- * attribute files being created already exist.
- *
- * Returns 0 on success or error code from sysfs_create_group on failure.
- */
-int devm_device_add_groups(struct device *dev,
-			   const struct attribute_group **groups)
-{
-	union device_attr_group_devres *devres;
-	int error;
-
-	devres = devres_alloc(devm_attr_groups_remove,
-			      sizeof(*devres), GFP_KERNEL);
-	if (!devres)
-		return -ENOMEM;
-
-	error = sysfs_create_groups(&dev->kobj, groups);
-	if (error) {
-		devres_free(devres);
-		return error;
-	}
-
-	devres->groups = groups;
-	devres_add(dev, devres);
-	return 0;
-}
-EXPORT_SYMBOL_GPL(devm_device_add_groups);
-
-/**
- * devm_device_remove_groups - remove a list of managed groups
- *
- * @dev:	The device for the groups to be removed from
- * @groups:	NULL terminated list of groups to be removed
- *
- * If groups is not NULL, remove the specified groups from the device.
- */
-void devm_device_remove_groups(struct device *dev,
-			       const struct attribute_group **groups)
-{
-	WARN_ON(devres_release(dev, devm_attr_groups_remove,
-			       devm_attr_group_match,
-			       /* cast away const */ (void *)groups));
-}
-EXPORT_SYMBOL_GPL(devm_device_remove_groups);
-
 static int device_add_attrs(struct device *dev)
 {
-	struct class *class = dev->class;
+	const struct class *class = dev->class;
 	const struct device_type *type = dev->type;
 	int error;
 
@@ -1765,8 +2918,33 @@ static int device_add_attrs(struct device *dev)
 			goto err_remove_dev_groups;
 	}
 
+	if (fw_devlink_flags && !fw_devlink_is_permissive() && dev->fwnode) {
+		error = device_create_file(dev, &dev_attr_waiting_for_supplier);
+		if (error)
+			goto err_remove_dev_online;
+	}
+
+	if (dev_removable_is_valid(dev)) {
+		error = device_create_file(dev, &dev_attr_removable);
+		if (error)
+			goto err_remove_dev_waiting_for_supplier;
+	}
+
+	if (dev_add_physical_location(dev)) {
+		error = device_add_group(dev,
+			&dev_attr_physical_location_group);
+		if (error)
+			goto err_remove_dev_removable;
+	}
+
 	return 0;
 
+ err_remove_dev_removable:
+	device_remove_file(dev, &dev_attr_removable);
+ err_remove_dev_waiting_for_supplier:
+	device_remove_file(dev, &dev_attr_waiting_for_supplier);
+ err_remove_dev_online:
+	device_remove_file(dev, &dev_attr_online);
  err_remove_dev_groups:
 	device_remove_groups(dev, dev->groups);
  err_remove_type_groups:
@@ -1781,9 +2959,16 @@ static int device_add_attrs(struct device *dev)
 
 static void device_remove_attrs(struct device *dev)
 {
-	struct class *class = dev->class;
+	const struct class *class = dev->class;
 	const struct device_type *type = dev->type;
 
+	if (dev->physical_location) {
+		device_remove_group(dev, &dev_attr_physical_location_group);
+		kfree(dev->physical_location);
+	}
+
+	device_remove_file(dev, &dev_attr_removable);
+	device_remove_file(dev, &dev_attr_waiting_for_supplier);
 	device_remove_file(dev, &dev_attr_online);
 	device_remove_groups(dev, dev->groups);
 
@@ -1974,26 +3159,25 @@ void device_initialize(struct device *dev)
 	kobject_init(&dev->kobj, &device_ktype);
 	INIT_LIST_HEAD(&dev->dma_pools);
 	mutex_init(&dev->mutex);
-#ifdef CONFIG_PROVE_LOCKING
-	mutex_init(&dev->lockdep_mutex);
-#endif
 	lockdep_set_novalidate_class(&dev->mutex);
 	spin_lock_init(&dev->devres_lock);
 	INIT_LIST_HEAD(&dev->devres_head);
 	device_pm_init(dev);
-	set_dev_node(dev, -1);
-#ifdef CONFIG_GENERIC_MSI_IRQ
-	INIT_LIST_HEAD(&dev->msi_list);
-#endif
+	set_dev_node(dev, NUMA_NO_NODE);
 	INIT_LIST_HEAD(&dev->links.consumers);
 	INIT_LIST_HEAD(&dev->links.suppliers);
-	INIT_LIST_HEAD(&dev->links.needs_suppliers);
 	INIT_LIST_HEAD(&dev->links.defer_sync);
 	dev->links.status = DL_DEV_NO_DRIVER;
+#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \
+    defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \
+    defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL)
+	dev->dma_coherent = dma_default_coherent;
+#endif
+	swiotlb_dev_init(dev);
 }
 EXPORT_SYMBOL_GPL(device_initialize);
 
-struct kobject *virtual_device_parent(struct device *dev)
+struct kobject *virtual_device_parent(void)
 {
 	static struct kobject *virtual_dir = NULL;
 
@@ -2006,7 +3190,7 @@ struct kobject *virtual_device_parent(struct device *dev)
 
 struct class_dir {
 	struct kobject kobj;
-	struct class *class;
+	const struct class *class;
 };
 
 #define to_class_dir(obj) container_of(obj, struct class_dir, kobj)
@@ -2018,20 +3202,20 @@ static void class_dir_release(struct kobject *kobj)
 }
 
 static const
-struct kobj_ns_type_operations *class_dir_child_ns_type(struct kobject *kobj)
+struct kobj_ns_type_operations *class_dir_child_ns_type(const struct kobject *kobj)
 {
-	struct class_dir *dir = to_class_dir(kobj);
+	const struct class_dir *dir = to_class_dir(kobj);
 	return dir->class->ns_type;
 }
 
-static struct kobj_type class_dir_ktype = {
+static const struct kobj_type class_dir_ktype = {
 	.release	= class_dir_release,
 	.sysfs_ops	= &kobj_sysfs_ops,
 	.child_ns_type	= class_dir_child_ns_type
 };
 
-static struct kobject *
-class_dir_create_and_add(struct class *class, struct kobject *parent_kobj)
+static struct kobject *class_dir_create_and_add(struct subsys_private *sp,
+						struct kobject *parent_kobj)
 {
 	struct class_dir *dir;
 	int retval;
@@ -2040,12 +3224,12 @@ class_dir_create_and_add(struct class *class, struct kobject *parent_kobj)
 	if (!dir)
 		return ERR_PTR(-ENOMEM);
 
-	dir->class = class;
+	dir->class = sp->class;
 	kobject_init(&dir->kobj, &class_dir_ktype);
 
-	dir->kobj.kset = &class->p->glue_dirs;
+	dir->kobj.kset = &sp->glue_dirs;
 
-	retval = kobject_add(&dir->kobj, parent_kobj, "%s", class->name);
+	retval = kobject_add(&dir->kobj, parent_kobj, "%s", sp->class->name);
 	if (retval < 0) {
 		kobject_put(&dir->kobj);
 		return ERR_PTR(retval);
@@ -2058,57 +3242,61 @@ static DEFINE_MUTEX(gdp_mutex);
 static struct kobject *get_device_parent(struct device *dev,
 					 struct device *parent)
 {
-	if (dev->class) {
-		struct kobject *kobj = NULL;
+	struct subsys_private *sp = class_to_subsys(dev->class);
+	struct kobject *kobj = NULL;
+
+	if (sp) {
 		struct kobject *parent_kobj;
 		struct kobject *k;
 
-#ifdef CONFIG_BLOCK
-		/* block disks show up in /sys/block */
-		if (sysfs_deprecated && dev->class == &block_class) {
-			if (parent && parent->class == &block_class)
-				return &parent->kobj;
-			return &block_class.p->subsys.kobj;
-		}
-#endif
-
 		/*
 		 * If we have no parent, we live in "virtual".
 		 * Class-devices with a non class-device as parent, live
 		 * in a "glue" directory to prevent namespace collisions.
 		 */
 		if (parent == NULL)
-			parent_kobj = virtual_device_parent(dev);
-		else if (parent->class && !dev->class->ns_type)
+			parent_kobj = virtual_device_parent();
+		else if (parent->class && !dev->class->ns_type) {
+			subsys_put(sp);
 			return &parent->kobj;
-		else
+		} else {
 			parent_kobj = &parent->kobj;
+		}
 
 		mutex_lock(&gdp_mutex);
 
 		/* find our class-directory at the parent and reference it */
-		spin_lock(&dev->class->p->glue_dirs.list_lock);
-		list_for_each_entry(k, &dev->class->p->glue_dirs.list, entry)
+		spin_lock(&sp->glue_dirs.list_lock);
+		list_for_each_entry(k, &sp->glue_dirs.list, entry)
 			if (k->parent == parent_kobj) {
 				kobj = kobject_get(k);
 				break;
 			}
-		spin_unlock(&dev->class->p->glue_dirs.list_lock);
+		spin_unlock(&sp->glue_dirs.list_lock);
 		if (kobj) {
 			mutex_unlock(&gdp_mutex);
+			subsys_put(sp);
 			return kobj;
 		}
 
 		/* or create a new class-directory at the parent device */
-		k = class_dir_create_and_add(dev->class, parent_kobj);
+		k = class_dir_create_and_add(sp, parent_kobj);
 		/* do not emit an uevent for this simple "glue" directory */
 		mutex_unlock(&gdp_mutex);
+		subsys_put(sp);
 		return k;
 	}
 
 	/* subsystems can specify a default root directory for their devices */
-	if (!parent && dev->bus && dev->bus->dev_root)
-		return &dev->bus->dev_root->kobj;
+	if (!parent && dev->bus) {
+		struct device *dev_root = bus_get_dev_root(dev->bus);
+
+		if (dev_root) {
+			kobj = &dev_root->kobj;
+			put_device(dev_root);
+			return kobj;
+		}
+	}
 
 	if (parent)
 		return &parent->kobj;
@@ -2118,10 +3306,23 @@ static struct kobject *get_device_parent(struct device *dev,
 static inline bool live_in_glue_dir(struct kobject *kobj,
 				    struct device *dev)
 {
-	if (!kobj || !dev->class ||
-	    kobj->kset != &dev->class->p->glue_dirs)
+	struct subsys_private *sp;
+	bool retval;
+
+	if (!kobj || !dev->class)
 		return false;
-	return true;
+
+	sp = class_to_subsys(dev->class);
+	if (!sp)
+		return false;
+
+	if (kobj->kset == &sp->glue_dirs)
+		retval = true;
+	else
+		retval = false;
+
+	subsys_put(sp);
+	return retval;
 }
 
 static inline struct kobject *get_glue_dir(struct device *dev)
@@ -2129,6 +3330,23 @@ static inline struct kobject *get_glue_dir(struct device *dev)
 	return dev->kobj.parent;
 }
 
+/**
+ * kobject_has_children - Returns whether a kobject has children.
+ * @kobj: the object to test
+ *
+ * This will return whether a kobject has other kobjects as children.
+ *
+ * It does NOT account for the presence of attribute files, only sub
+ * directories. It also assumes there is no concurrent addition or
+ * removal of such children, and thus relies on external locking.
+ */
+static inline bool kobject_has_children(struct kobject *kobj)
+{
+	WARN_ON_ONCE(kref_read(&kobj->kref) == 0);
+
+	return kobj->sd && kobj->sd->dir.subdirs;
+}
+
 /*
  * make sure cleaning up dir as the last step, we need to make
  * sure .release handler of kobject is run with holding the
@@ -2201,6 +3419,7 @@ static void cleanup_glue_dir(struct device *dev, struct kobject *glue_dir)
 static int device_add_class_symlinks(struct device *dev)
 {
 	struct device_node *of_node = dev_of_node(dev);
+	struct subsys_private *sp;
 	int error;
 
 	if (of_node) {
@@ -2210,12 +3429,11 @@ static int device_add_class_symlinks(struct device *dev)
 		/* An error here doesn't warrant bringing down the device */
 	}
 
-	if (!dev->class)
+	sp = class_to_subsys(dev->class);
+	if (!sp)
 		return 0;
 
-	error = sysfs_create_link(&dev->kobj,
-				  &dev->class->p->subsys.kobj,
-				  "subsystem");
+	error = sysfs_create_link(&dev->kobj, &sp->subsys.kobj, "subsystem");
 	if (error)
 		goto out_devnode;
 
@@ -2226,46 +3444,38 @@ static int device_add_class_symlinks(struct device *dev)
 			goto out_subsys;
 	}
 
-#ifdef CONFIG_BLOCK
-	/* /sys/block has directories and does not need symlinks */
-	if (sysfs_deprecated && dev->class == &block_class)
-		return 0;
-#endif
-
 	/* link in the class directory pointing to the device */
-	error = sysfs_create_link(&dev->class->p->subsys.kobj,
-				  &dev->kobj, dev_name(dev));
+	error = sysfs_create_link(&sp->subsys.kobj, &dev->kobj, dev_name(dev));
 	if (error)
 		goto out_device;
-
-	return 0;
+	goto exit;
 
 out_device:
 	sysfs_remove_link(&dev->kobj, "device");
-
 out_subsys:
 	sysfs_remove_link(&dev->kobj, "subsystem");
 out_devnode:
 	sysfs_remove_link(&dev->kobj, "of_node");
+exit:
+	subsys_put(sp);
 	return error;
 }
 
 static void device_remove_class_symlinks(struct device *dev)
 {
+	struct subsys_private *sp = class_to_subsys(dev->class);
+
 	if (dev_of_node(dev))
 		sysfs_remove_link(&dev->kobj, "of_node");
 
-	if (!dev->class)
+	if (!sp)
 		return;
 
 	if (dev->parent && device_is_not_partition(dev))
 		sysfs_remove_link(&dev->kobj, "device");
 	sysfs_remove_link(&dev->kobj, "subsystem");
-#ifdef CONFIG_BLOCK
-	if (sysfs_deprecated && dev->class == &block_class)
-		return;
-#endif
-	sysfs_delete_link(&dev->class->p->subsys.kobj, &dev->kobj, dev_name(dev));
+	sysfs_delete_link(&sp->subsys.kobj, &dev->kobj, dev_name(dev));
+	subsys_put(sp);
 }
 
 /**
@@ -2285,27 +3495,13 @@ int dev_set_name(struct device *dev, const char *fmt, ...)
 }
 EXPORT_SYMBOL_GPL(dev_set_name);
 
-/**
- * device_to_dev_kobj - select a /sys/dev/ directory for the device
- * @dev: device
- *
- * By default we select char/ for new entries.  Setting class->dev_obj
- * to NULL prevents an entry from being created.  class->dev_kobj must
- * be set (or cleared) before any devices are registered to the class
- * otherwise device_create_sys_dev_entry() and
- * device_remove_sys_dev_entry() will disagree about the presence of
- * the link.
- */
+/* select a /sys/dev/ directory for the device */
 static struct kobject *device_to_dev_kobj(struct device *dev)
 {
-	struct kobject *kobj;
-
-	if (dev->class)
-		kobj = dev->class->dev_kobj;
+	if (is_blockdev(dev))
+		return sysfs_dev_block_kobj;
 	else
-		kobj = sysfs_dev_char_kobj;
-
-	return kobj;
+		return sysfs_dev_char_kobj;
 }
 
 static int device_create_sys_dev_entry(struct device *dev)
@@ -2345,31 +3541,6 @@ static int device_private_init(struct device *dev)
 	return 0;
 }
 
-static u32 fw_devlink_flags;
-static int __init fw_devlink_setup(char *arg)
-{
-	if (!arg)
-		return -EINVAL;
-
-	if (strcmp(arg, "off") == 0) {
-		fw_devlink_flags = 0;
-	} else if (strcmp(arg, "permissive") == 0) {
-		fw_devlink_flags = DL_FLAG_SYNC_STATE_ONLY;
-	} else if (strcmp(arg, "on") == 0) {
-		fw_devlink_flags = DL_FLAG_AUTOPROBE_CONSUMER;
-	} else if (strcmp(arg, "rpm") == 0) {
-		fw_devlink_flags = DL_FLAG_AUTOPROBE_CONSUMER |
-				   DL_FLAG_PM_RUNTIME;
-	}
-	return 0;
-}
-early_param("fw_devlink", fw_devlink_setup);
-
-u32 fw_devlink_get_flags(void)
-{
-	return fw_devlink_flags;
-}
-
 /**
  * device_add - add device to device hierarchy.
  * @dev: device.
@@ -2399,12 +3570,12 @@ u32 fw_devlink_get_flags(void)
  */
 int device_add(struct device *dev)
 {
+	struct subsys_private *sp;
 	struct device *parent;
 	struct kobject *kobj;
 	struct class_interface *class_intf;
-	int error = -EINVAL, fw_ret;
+	int error = -EINVAL;
 	struct kobject *glue_dir = NULL;
-	bool is_fwnode_dev = false;
 
 	dev = get_device(dev);
 	if (!dev)
@@ -2422,18 +3593,19 @@ int device_add(struct device *dev)
 	 * the name, and force the use of dev_name()
 	 */
 	if (dev->init_name) {
-		dev_set_name(dev, "%s", dev->init_name);
+		error = dev_set_name(dev, "%s", dev->init_name);
 		dev->init_name = NULL;
 	}
 
+	if (dev_name(dev))
+		error = 0;
 	/* subsystems can specify simple device enumeration */
-	if (!dev_name(dev) && dev->bus && dev->bus->dev_name)
-		dev_set_name(dev, "%s%u", dev->bus->dev_name, dev->id);
-
-	if (!dev_name(dev)) {
+	else if (dev->bus && dev->bus->dev_name)
+		error = dev_set_name(dev, "%s%u", dev->bus->dev_name, dev->id);
+	else
 		error = -EINVAL;
+	if (error)
 		goto name_error;
-	}
 
 	pr_debug("device: '%s': %s\n", dev_name(dev), __func__);
 
@@ -2454,14 +3626,12 @@ int device_add(struct device *dev)
 	/* we require the name to be set before, and pass NULL */
 	error = kobject_add(&dev->kobj, dev->kobj.parent, NULL);
 	if (error) {
-		glue_dir = get_glue_dir(dev);
+		glue_dir = kobj;
 		goto Error;
 	}
 
 	/* notify platform of device entry */
-	error = device_platform_notify(dev, KOBJ_ADD);
-	if (error)
-		goto platform_error;
+	device_platform_notify(dev);
 
 	error = device_create_file(dev, &dev_attr_uevent);
 	if (error)
@@ -2496,17 +3666,9 @@ int device_add(struct device *dev)
 	/* Notify clients of device addition.  This call must come
 	 * after dpm_sysfs_add() and before kobject_uevent().
 	 */
-	if (dev->bus)
-		blocking_notifier_call_chain(&dev->bus->p->bus_notifier,
-					     BUS_NOTIFY_ADD_DEVICE, dev);
-
+	bus_notify(dev, BUS_NOTIFY_ADD_DEVICE);
 	kobject_uevent(&dev->kobj, KOBJ_ADD);
 
-	if (dev->fwnode && !dev->fwnode->dev) {
-		dev->fwnode->dev = dev;
-		is_fwnode_dev = true;
-	}
-
 	/*
 	 * Check if any of the other devices (consumers) have been waiting for
 	 * this device (supplier) to be added so that they can create a device
@@ -2515,38 +3677,41 @@ int device_add(struct device *dev)
 	 * This needs to happen after device_pm_add() because device_link_add()
 	 * requires the supplier be registered before it's called.
 	 *
-	 * But this also needs to happe before bus_probe_device() to make sure
+	 * But this also needs to happen before bus_probe_device() to make sure
 	 * waiting consumers can link to it before the driver is bound to the
 	 * device and the driver sync_state callback is called for this device.
 	 */
-	device_link_add_missing_supplier_links();
-
-	if (fw_devlink_flags && is_fwnode_dev &&
-	    fwnode_has_op(dev->fwnode, add_links)) {
-		fw_ret = fwnode_call_int_op(dev->fwnode, add_links, dev);
-		if (fw_ret == -ENODEV)
-			device_link_wait_for_mandatory_supplier(dev);
-		else if (fw_ret)
-			device_link_wait_for_optional_supplier(dev);
+	if (dev->fwnode && !dev->fwnode->dev) {
+		dev->fwnode->dev = dev;
+		fw_devlink_link_device(dev);
 	}
 
 	bus_probe_device(dev);
+
+	/*
+	 * If all driver registration is done and a newly added device doesn't
+	 * match with any driver, don't block its consumers from probing in
+	 * case the consumer device is able to operate without this supplier.
+	 */
+	if (dev->fwnode && fw_devlink_drv_reg_done && !dev->can_match)
+		fw_devlink_unblock_consumers(dev);
+
 	if (parent)
 		klist_add_tail(&dev->p->knode_parent,
 			       &parent->p->klist_children);
 
-	if (dev->class) {
-		mutex_lock(&dev->class->p->mutex);
+	sp = class_to_subsys(dev->class);
+	if (sp) {
+		mutex_lock(&sp->mutex);
 		/* tie the class to the device */
-		klist_add_tail(&dev->p->knode_class,
-			       &dev->class->p->klist_devices);
+		klist_add_tail(&dev->p->knode_class, &sp->klist_devices);
 
 		/* notify any interfaces that the device is here */
-		list_for_each_entry(class_intf,
-				    &dev->class->p->interfaces, node)
+		list_for_each_entry(class_intf, &sp->interfaces, node)
 			if (class_intf->add_dev)
-				class_intf->add_dev(dev, class_intf);
-		mutex_unlock(&dev->class->p->mutex);
+				class_intf->add_dev(dev);
+		mutex_unlock(&sp->mutex);
+		subsys_put(sp);
 	}
 done:
 	put_device(dev);
@@ -2558,6 +3723,7 @@ done:
 	device_pm_remove(dev);
 	dpm_sysfs_remove(dev);
  DPMError:
+	device_set_driver(dev, NULL);
 	bus_remove_device(dev);
  BusError:
 	device_remove_attrs(dev);
@@ -2566,8 +3732,7 @@ done:
  SymlinkError:
 	device_remove_file(dev, &dev_attr_uevent);
  attrError:
-	device_platform_notify(dev, KOBJ_REMOVE);
-platform_error:
+	device_platform_notify_remove(dev);
 	kobject_uevent(&dev->kobj, KOBJ_REMOVE);
 	glue_dir = get_glue_dir(dev);
 	kobject_del(&dev->kobj);
@@ -2642,7 +3807,7 @@ bool kill_device(struct device *dev)
 	 * to run while we are tearing out the bus/class/sysfs from
 	 * underneath the device.
 	 */
-	lockdep_assert_held(&dev->mutex);
+	device_lock_assert(dev);
 
 	if (dev->p->dead)
 		return false;
@@ -2666,9 +3831,11 @@ EXPORT_SYMBOL_GPL(kill_device);
  */
 void device_del(struct device *dev)
 {
+	struct subsys_private *sp;
 	struct device *parent = dev->parent;
 	struct kobject *glue_dir = NULL;
 	struct class_interface *class_intf;
+	unsigned int noio_flag;
 
 	device_lock(dev);
 	kill_device(dev);
@@ -2680,9 +3847,8 @@ void device_del(struct device *dev)
 	/* Notify clients of device removal.  This call must come
 	 * before dpm_sysfs_remove().
 	 */
-	if (dev->bus)
-		blocking_notifier_call_chain(&dev->bus->p->bus_notifier,
-					     BUS_NOTIFY_DEL_DEVICE, dev);
+	noio_flag = memalloc_noio_save();
+	bus_notify(dev, BUS_NOTIFY_DEL_DEVICE);
 
 	dpm_sysfs_remove(dev);
 	if (parent)
@@ -2692,35 +3858,46 @@ void device_del(struct device *dev)
 		device_remove_sys_dev_entry(dev);
 		device_remove_file(dev, &dev_attr_dev);
 	}
-	if (dev->class) {
+
+	sp = class_to_subsys(dev->class);
+	if (sp) {
 		device_remove_class_symlinks(dev);
 
-		mutex_lock(&dev->class->p->mutex);
+		mutex_lock(&sp->mutex);
 		/* notify any interfaces that the device is now gone */
-		list_for_each_entry(class_intf,
-				    &dev->class->p->interfaces, node)
+		list_for_each_entry(class_intf, &sp->interfaces, node)
 			if (class_intf->remove_dev)
-				class_intf->remove_dev(dev, class_intf);
+				class_intf->remove_dev(dev);
 		/* remove the device from the class list */
 		klist_del(&dev->p->knode_class);
-		mutex_unlock(&dev->class->p->mutex);
+		mutex_unlock(&sp->mutex);
+		subsys_put(sp);
 	}
 	device_remove_file(dev, &dev_attr_uevent);
 	device_remove_attrs(dev);
 	bus_remove_device(dev);
 	device_pm_remove(dev);
 	driver_deferred_probe_del(dev);
-	device_platform_notify(dev, KOBJ_REMOVE);
-	device_remove_properties(dev);
+	device_platform_notify_remove(dev);
 	device_links_purge(dev);
 
-	if (dev->bus)
-		blocking_notifier_call_chain(&dev->bus->p->bus_notifier,
-					     BUS_NOTIFY_REMOVED_DEVICE, dev);
+	/*
+	 * If a device does not have a driver attached, we need to clean
+	 * up any managed resources. We do this in device_release(), but
+	 * it's never called (and we leak the device) if a managed
+	 * resource holds a reference to the device. So release all
+	 * managed resources here, like we do in driver_detach(). We
+	 * still need to do so again in device_release() in case someone
+	 * adds a new resource after this point, though.
+	 */
+	devres_release_all(dev);
+
+	bus_notify(dev, BUS_NOTIFY_REMOVED_DEVICE);
 	kobject_uevent(&dev->kobj, KOBJ_REMOVE);
 	glue_dir = get_glue_dir(dev);
 	kobject_del(&dev->kobj);
 	cleanup_glue_dir(dev, glue_dir);
+	memalloc_noio_restore(noio_flag);
 	put_device(parent);
 }
 EXPORT_SYMBOL_GPL(device_del);
@@ -2783,7 +3960,7 @@ static struct device *next_device(struct klist_iter *i)
  * a name. This memory is returned in tmp and needs to be
  * freed by the caller.
  */
-const char *device_get_devnode(struct device *dev,
+const char *device_get_devnode(const struct device *dev,
 			       umode_t *mode, kuid_t *uid, kgid_t *gid,
 			       const char **tmp)
 {
@@ -2808,18 +3985,17 @@ const char *device_get_devnode(struct device *dev,
 		return dev_name(dev);
 
 	/* replace '!' in the name with '/' */
-	s = kstrdup(dev_name(dev), GFP_KERNEL);
+	s = kstrdup_and_replace(dev_name(dev), '!', '/', GFP_KERNEL);
 	if (!s)
 		return NULL;
-	strreplace(s, '!', '/');
 	return *tmp = s;
 }
 
 /**
  * device_for_each_child - device child iterator.
  * @parent: parent struct device.
- * @fn: function to be called for each device.
  * @data: data for the callback.
+ * @fn: function to be called for each device.
  *
  * Iterate over @parent's child devices, and call @fn for each,
  * passing it @data.
@@ -2828,13 +4004,13 @@ const char *device_get_devnode(struct device *dev,
  * other than 0, we break out and return that value.
  */
 int device_for_each_child(struct device *parent, void *data,
-			  int (*fn)(struct device *dev, void *data))
+			  device_iter_t fn)
 {
 	struct klist_iter i;
 	struct device *child;
 	int error = 0;
 
-	if (!parent->p)
+	if (!parent || !parent->p)
 		return 0;
 
 	klist_iter_init(&parent->p->klist_children, &i);
@@ -2848,8 +4024,8 @@ EXPORT_SYMBOL_GPL(device_for_each_child);
 /**
  * device_for_each_child_reverse - device child iterator in reversed order.
  * @parent: parent struct device.
- * @fn: function to be called for each device.
  * @data: data for the callback.
+ * @fn: function to be called for each device.
  *
  * Iterate over @parent's child devices, and call @fn for each,
  * passing it @data.
@@ -2858,13 +4034,13 @@ EXPORT_SYMBOL_GPL(device_for_each_child);
  * other than 0, we break out and return that value.
  */
 int device_for_each_child_reverse(struct device *parent, void *data,
-				  int (*fn)(struct device *dev, void *data))
+				  device_iter_t fn)
 {
 	struct klist_iter i;
 	struct device *child;
 	int error = 0;
 
-	if (!parent->p)
+	if (!parent || !parent->p)
 		return 0;
 
 	klist_iter_init(&parent->p->klist_children, &i);
@@ -2876,67 +4052,77 @@ int device_for_each_child_reverse(struct device *parent, void *data,
 EXPORT_SYMBOL_GPL(device_for_each_child_reverse);
 
 /**
- * device_find_child - device iterator for locating a particular device.
- * @parent: parent struct device
- * @match: Callback function to check device
- * @data: Data to pass to match function
- *
- * This is similar to the device_for_each_child() function above, but it
- * returns a reference to a device that is 'found' for later use, as
- * determined by the @match callback.
+ * device_for_each_child_reverse_from - device child iterator in reversed order.
+ * @parent: parent struct device.
+ * @from: optional starting point in child list
+ * @data: data for the callback.
+ * @fn: function to be called for each device.
  *
- * The callback should return 0 if the device doesn't match and non-zero
- * if it does.  If the callback returns non-zero and a reference to the
- * current device can be obtained, this function will return to the caller
- * and not iterate over any more devices.
+ * Iterate over @parent's child devices, starting at @from, and call @fn
+ * for each, passing it @data. This helper is identical to
+ * device_for_each_child_reverse() when @from is NULL.
  *
- * NOTE: you will need to drop the reference with put_device() after use.
+ * @fn is checked each iteration. If it returns anything other than 0,
+ * iteration stop and that value is returned to the caller of
+ * device_for_each_child_reverse_from();
  */
-struct device *device_find_child(struct device *parent, void *data,
-				 int (*match)(struct device *dev, void *data))
+int device_for_each_child_reverse_from(struct device *parent,
+				       struct device *from, void *data,
+				       device_iter_t fn)
 {
 	struct klist_iter i;
 	struct device *child;
+	int error = 0;
 
-	if (!parent)
-		return NULL;
+	if (!parent || !parent->p)
+		return 0;
 
-	klist_iter_init(&parent->p->klist_children, &i);
-	while ((child = next_device(&i)))
-		if (match(child, data) && get_device(child))
-			break;
+	klist_iter_init_node(&parent->p->klist_children, &i,
+			     (from ? &from->p->knode_parent : NULL));
+	while ((child = prev_device(&i)) && !error)
+		error = fn(child, data);
 	klist_iter_exit(&i);
-	return child;
+	return error;
 }
-EXPORT_SYMBOL_GPL(device_find_child);
+EXPORT_SYMBOL_GPL(device_for_each_child_reverse_from);
 
 /**
- * device_find_child_by_name - device iterator for locating a child device.
+ * device_find_child - device iterator for locating a particular device.
  * @parent: parent struct device
- * @name: name of the child device
+ * @data: Data to pass to match function
+ * @match: Callback function to check device
  *
- * This is similar to the device_find_child() function above, but it
- * returns a reference to a device that has the name @name.
+ * This is similar to the device_for_each_child() function above, but it
+ * returns a reference to a device that is 'found' for later use, as
+ * determined by the @match callback.
+ *
+ * The callback should return 0 if the device doesn't match and non-zero
+ * if it does.  If the callback returns non-zero and a reference to the
+ * current device can be obtained, this function will return to the caller
+ * and not iterate over any more devices.
  *
  * NOTE: you will need to drop the reference with put_device() after use.
  */
-struct device *device_find_child_by_name(struct device *parent,
-					 const char *name)
+struct device *device_find_child(struct device *parent, const void *data,
+				 device_match_t match)
 {
 	struct klist_iter i;
 	struct device *child;
 
-	if (!parent)
+	if (!parent || !parent->p)
 		return NULL;
 
 	klist_iter_init(&parent->p->klist_children, &i);
-	while ((child = next_device(&i)))
-		if (!strcmp(dev_name(child), name) && get_device(child))
+	while ((child = next_device(&i))) {
+		if (match(child, data)) {
+			get_device(child);
 			break;
+		}
+	}
 	klist_iter_exit(&i);
 	return child;
 }
-EXPORT_SYMBOL_GPL(device_find_child_by_name);
+EXPORT_SYMBOL_GPL(device_find_child);
 
 int __init devices_init(void)
 {
@@ -2952,9 +4138,14 @@ int __init devices_init(void)
 	sysfs_dev_char_kobj = kobject_create_and_add("char", dev_kobj);
 	if (!sysfs_dev_char_kobj)
 		goto char_kobj_err;
+	device_link_wq = alloc_workqueue("device_link_wq", WQ_PERCPU, 0);
+	if (!device_link_wq)
+		goto wq_err;
 
 	return 0;
 
+ wq_err:
+	kobject_put(sysfs_dev_char_kobj);
  char_kobj_err:
 	kobject_put(sysfs_dev_block_kobj);
  block_kobj_err:
@@ -3148,7 +4339,7 @@ static void device_create_release(struct device *dev)
 }
 
 static __printf(6, 0) struct device *
-device_create_groups_vargs(struct class *class, struct device *parent,
+device_create_groups_vargs(const struct class *class, struct device *parent,
 			   dev_t devt, void *drvdata,
 			   const struct attribute_group **groups,
 			   const char *fmt, va_list args)
@@ -3156,7 +4347,7 @@ device_create_groups_vargs(struct class *class, struct device *parent,
 	struct device *dev = NULL;
 	int retval = -ENODEV;
 
-	if (class == NULL || IS_ERR(class))
+	if (IS_ERR_OR_NULL(class))
 		goto error;
 
 	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
@@ -3189,40 +4380,6 @@ error:
 }
 
 /**
- * device_create_vargs - creates a device and registers it with sysfs
- * @class: pointer to the struct class that this device should be registered to
- * @parent: pointer to the parent struct device of this new device, if any
- * @devt: the dev_t for the char device to be added
- * @drvdata: the data to be added to the device for callbacks
- * @fmt: string for the device's name
- * @args: va_list for the device's name
- *
- * This function can be used by char device classes.  A struct device
- * will be created in sysfs, registered to the specified class.
- *
- * A "dev" file will be created, showing the dev_t for the device, if
- * the dev_t is not 0,0.
- * If a pointer to a parent struct device is passed in, the newly created
- * struct device will be a child of that device in sysfs.
- * The pointer to the struct device will be returned from the call.
- * Any further sysfs files that might be required can be created using this
- * pointer.
- *
- * Returns &struct device pointer on success, or ERR_PTR() on error.
- *
- * Note: the struct class passed to this function must have previously
- * been created with a call to class_create().
- */
-struct device *device_create_vargs(struct class *class, struct device *parent,
-				   dev_t devt, void *drvdata, const char *fmt,
-				   va_list args)
-{
-	return device_create_groups_vargs(class, parent, devt, drvdata, NULL,
-					  fmt, args);
-}
-EXPORT_SYMBOL_GPL(device_create_vargs);
-
-/**
  * device_create - creates a device and registers it with sysfs
  * @class: pointer to the struct class that this device should be registered to
  * @parent: pointer to the parent struct device of this new device, if any
@@ -3242,18 +4399,16 @@ EXPORT_SYMBOL_GPL(device_create_vargs);
  * pointer.
  *
  * Returns &struct device pointer on success, or ERR_PTR() on error.
- *
- * Note: the struct class passed to this function must have previously
- * been created with a call to class_create().
  */
-struct device *device_create(struct class *class, struct device *parent,
+struct device *device_create(const struct class *class, struct device *parent,
 			     dev_t devt, void *drvdata, const char *fmt, ...)
 {
 	va_list vargs;
 	struct device *dev;
 
 	va_start(vargs, fmt);
-	dev = device_create_vargs(class, parent, devt, drvdata, fmt, vargs);
+	dev = device_create_groups_vargs(class, parent, devt, drvdata, NULL,
+					  fmt, vargs);
 	va_end(vargs);
 	return dev;
 }
@@ -3282,11 +4437,8 @@ EXPORT_SYMBOL_GPL(device_create);
  * pointer.
  *
  * Returns &struct device pointer on success, or ERR_PTR() on error.
- *
- * Note: the struct class passed to this function must have previously
- * been created with a call to class_create().
  */
-struct device *device_create_with_groups(struct class *class,
+struct device *device_create_with_groups(const struct class *class,
 					 struct device *parent, dev_t devt,
 					 void *drvdata,
 					 const struct attribute_group **groups,
@@ -3311,7 +4463,7 @@ EXPORT_SYMBOL_GPL(device_create_with_groups);
  * This call unregisters and cleans up a device that was created with a
  * call to device_create().
  */
-void device_destroy(struct class *class, dev_t devt)
+void device_destroy(const struct class *class, dev_t devt)
 {
 	struct device *dev;
 
@@ -3333,9 +4485,12 @@ EXPORT_SYMBOL_GPL(device_destroy);
  * on the same device to ensure that new_name is valid and
  * won't conflict with other devices.
  *
- * Note: Don't call this function.  Currently, the networking layer calls this
- * function, but that will change.  The following text from Kay Sievers offers
- * some insight:
+ * Note: given that some subsystems (networking and infiniband) use this
+ * function, with no immediate plans for this to change, we cannot assume or
+ * require that this function not be called at all.
+ *
+ * However, if you're writing new code, do not call this function. The following
+ * text from Kay Sievers offers some insight:
  *
  * Renaming devices is racy at many levels, symlinks and other stuff are not
  * replaced atomically, and you get a "move" uevent, but it's not easy to
@@ -3349,13 +4504,6 @@ EXPORT_SYMBOL_GPL(device_destroy);
  * kernel device renaming. Besides that, it's not even implemented now for
  * other things than (driver-core wise very simple) network devices.
  *
- * We are currently about to change network renaming in udev to completely
- * disallow renaming of devices in the same namespace as the kernel uses,
- * because we can't solve the problems properly, that arise with swapping names
- * of multiple interfaces without races. Means, renaming of eth[0-9]* will only
- * be allowed to some other name than eth[0-9]*, for the aforementioned
- * reasons.
- *
  * Make up a "real" name in the driver before you register anything, or add
  * some other attributes for userspace to find the device, or use udev to add
  * symlinks -- but never rename kernel devices later, it's a complete mess. We
@@ -3364,9 +4512,11 @@ EXPORT_SYMBOL_GPL(device_destroy);
  */
 int device_rename(struct device *dev, const char *new_name)
 {
+	struct subsys_private *sp = NULL;
 	struct kobject *kobj = &dev->kobj;
 	char *old_device_name = NULL;
 	int error;
+	bool is_link_renamed = false;
 
 	dev = get_device(dev);
 	if (!dev)
@@ -3381,18 +4531,28 @@ int device_rename(struct device *dev, const char *new_name)
 	}
 
 	if (dev->class) {
-		error = sysfs_rename_link_ns(&dev->class->p->subsys.kobj,
-					     kobj, old_device_name,
+		sp = class_to_subsys(dev->class);
+
+		if (!sp) {
+			error = -EINVAL;
+			goto out;
+		}
+
+		error = sysfs_rename_link_ns(&sp->subsys.kobj, kobj, old_device_name,
 					     new_name, kobject_namespace(kobj));
 		if (error)
 			goto out;
+
+		is_link_renamed = true;
 	}
 
 	error = kobject_rename(kobj, new_name);
-	if (error)
-		goto out;
-
 out:
+	if (error && is_link_renamed)
+		sysfs_rename_link_ns(&sp->subsys.kobj, kobj, new_name,
+				     old_device_name, kobject_namespace(kobj));
+	subsys_put(sp);
+
 	put_device(dev);
 
 	kfree(old_device_name);
@@ -3508,7 +4668,7 @@ static int device_attrs_change_owner(struct device *dev, kuid_t kuid,
 				     kgid_t kgid)
 {
 	struct kobject *kobj = &dev->kobj;
-	struct class *class = dev->class;
+	const struct class *class = dev->class;
 	const struct device_type *type = dev->type;
 	int error;
 
@@ -3566,6 +4726,7 @@ int device_change_owner(struct device *dev, kuid_t kuid, kgid_t kgid)
 {
 	int error;
 	struct kobject *kobj = &dev->kobj;
+	struct subsys_private *sp;
 
 	dev = get_device(dev);
 	if (!dev)
@@ -3602,21 +4763,19 @@ int device_change_owner(struct device *dev, kuid_t kuid, kgid_t kgid)
 	if (error)
 		goto out;
 
-#ifdef CONFIG_BLOCK
-	if (sysfs_deprecated && dev->class == &block_class)
-		goto out;
-#endif
-
 	/*
 	 * Change the owner of the symlink located in the class directory of
 	 * the device class associated with @dev which points to the actual
 	 * directory entry for @dev to @kuid/@kgid. This ensures that the
 	 * symlink shows the same permissions as its target.
 	 */
-	error = sysfs_link_change_owner(&dev->class->p->subsys.kobj, &dev->kobj,
-					dev_name(dev), kuid, kgid);
-	if (error)
+	sp = class_to_subsys(dev->class);
+	if (!sp) {
+		error = -EINVAL;
 		goto out;
+	}
+	error = sysfs_link_change_owner(&sp->subsys.kobj, &dev->kobj, dev_name(dev), kuid, kgid);
+	subsys_put(sp);
 
 out:
 	put_device(dev);
@@ -3701,22 +4860,21 @@ void device_shutdown(void)
  */
 
 #ifdef CONFIG_PRINTK
-static int
-create_syslog_header(const struct device *dev, char *hdr, size_t hdrlen)
+static void
+set_dev_info(const struct device *dev, struct dev_printk_info *dev_info)
 {
 	const char *subsys;
-	size_t pos = 0;
+
+	memset(dev_info, 0, sizeof(*dev_info));
 
 	if (dev->class)
 		subsys = dev->class->name;
 	else if (dev->bus)
 		subsys = dev->bus->name;
 	else
-		return 0;
+		return;
 
-	pos += snprintf(hdr + pos, hdrlen - pos, "SUBSYSTEM=%s", subsys);
-	if (pos >= hdrlen)
-		goto overflow;
+	strscpy(dev_info->subsystem, subsys);
 
 	/*
 	 * Add device identifier DEVICE=:
@@ -3732,41 +4890,28 @@ create_syslog_header(const struct device *dev, char *hdr, size_t hdrlen)
 			c = 'b';
 		else
 			c = 'c';
-		pos++;
-		pos += snprintf(hdr + pos, hdrlen - pos,
-				"DEVICE=%c%u:%u",
-				c, MAJOR(dev->devt), MINOR(dev->devt));
+
+		snprintf(dev_info->device, sizeof(dev_info->device),
+			 "%c%u:%u", c, MAJOR(dev->devt), MINOR(dev->devt));
 	} else if (strcmp(subsys, "net") == 0) {
 		struct net_device *net = to_net_dev(dev);
 
-		pos++;
-		pos += snprintf(hdr + pos, hdrlen - pos,
-				"DEVICE=n%u", net->ifindex);
+		snprintf(dev_info->device, sizeof(dev_info->device),
+			 "n%u", net->ifindex);
 	} else {
-		pos++;
-		pos += snprintf(hdr + pos, hdrlen - pos,
-				"DEVICE=+%s:%s", subsys, dev_name(dev));
+		snprintf(dev_info->device, sizeof(dev_info->device),
+			 "+%s:%s", subsys, dev_name(dev));
 	}
-
-	if (pos >= hdrlen)
-		goto overflow;
-
-	return pos;
-
-overflow:
-	dev_WARN(dev, "device/subsystem name too long");
-	return 0;
 }
 
 int dev_vprintk_emit(int level, const struct device *dev,
 		     const char *fmt, va_list args)
 {
-	char hdr[128];
-	size_t hdrlen;
+	struct dev_printk_info dev_info;
 
-	hdrlen = create_syslog_header(dev, hdr, sizeof(hdr));
+	set_dev_info(dev, &dev_info);
 
-	return vprintk_emit(0, level, hdrlen ? hdr : NULL, hdrlen, fmt, args);
+	return vprintk_emit(0, level, &dev_info, fmt, args);
 }
 EXPORT_SYMBOL(dev_vprintk_emit);
 
@@ -3795,8 +4940,8 @@ static void __dev_printk(const char *level, const struct device *dev,
 		printk("%s(NULL device *): %pV", level, vaf);
 }
 
-void dev_printk(const char *level, const struct device *dev,
-		const char *fmt, ...)
+void _dev_printk(const char *level, const struct device *dev,
+		 const char *fmt, ...)
 {
 	struct va_format vaf;
 	va_list args;
@@ -3810,7 +4955,7 @@ void dev_printk(const char *level, const struct device *dev,
 
 	va_end(args);
 }
-EXPORT_SYMBOL(dev_printk);
+EXPORT_SYMBOL(_dev_printk);
 
 #define define_dev_printk_level(func, kern_level)		\
 void func(const struct device *dev, const char *fmt, ...)	\
@@ -3839,6 +4984,145 @@ define_dev_printk_level(_dev_info, KERN_INFO);
 
 #endif
 
+static void __dev_probe_failed(const struct device *dev, int err, bool fatal,
+			       const char *fmt, va_list vargsp)
+{
+	struct va_format vaf;
+	va_list vargs;
+
+	/*
+	 * On x86_64 and possibly on other architectures, va_list is actually a
+	 * size-1 array containing a structure.  As a result, function parameter
+	 * vargsp decays from T[1] to T*, and &vargsp has type T** rather than
+	 * T(*)[1], which is expected by its assignment to vaf.va below.
+	 *
+	 * One standard way to solve this mess is by creating a copy in a local
+	 * variable of type va_list and then using a pointer to that local copy
+	 * instead, which is the approach employed here.
+	 */
+	va_copy(vargs, vargsp);
+
+	vaf.fmt = fmt;
+	vaf.va = &vargs;
+
+	switch (err) {
+	case -EPROBE_DEFER:
+		device_set_deferred_probe_reason(dev, &vaf);
+		dev_dbg(dev, "error %pe: %pV", ERR_PTR(err), &vaf);
+		break;
+
+	case -ENOMEM:
+		/* Don't print anything on -ENOMEM, there's already enough output */
+		break;
+
+	default:
+		/* Log fatal final failures as errors, otherwise produce warnings */
+		if (fatal)
+			dev_err(dev, "error %pe: %pV", ERR_PTR(err), &vaf);
+		else
+			dev_warn(dev, "error %pe: %pV", ERR_PTR(err), &vaf);
+		break;
+	}
+
+	va_end(vargs);
+}
+
+/**
+ * dev_err_probe - probe error check and log helper
+ * @dev: the pointer to the struct device
+ * @err: error value to test
+ * @fmt: printf-style format string
+ * @...: arguments as specified in the format string
+ *
+ * This helper implements common pattern present in probe functions for error
+ * checking: print debug or error message depending if the error value is
+ * -EPROBE_DEFER and propagate error upwards.
+ * In case of -EPROBE_DEFER it sets also defer probe reason, which can be
+ * checked later by reading devices_deferred debugfs attribute.
+ * It replaces the following code sequence::
+ *
+ * 	if (err != -EPROBE_DEFER)
+ * 		dev_err(dev, ...);
+ * 	else
+ * 		dev_dbg(dev, ...);
+ * 	return err;
+ *
+ * with::
+ *
+ * 	return dev_err_probe(dev, err, ...);
+ *
+ * Using this helper in your probe function is totally fine even if @err
+ * is known to never be -EPROBE_DEFER.
+ * The benefit compared to a normal dev_err() is the standardized format
+ * of the error code, which is emitted symbolically (i.e. you get "EAGAIN"
+ * instead of "-35"), and having the error code returned allows more
+ * compact error paths.
+ *
+ * Returns @err.
+ */
+int dev_err_probe(const struct device *dev, int err, const char *fmt, ...)
+{
+	va_list vargs;
+
+	va_start(vargs, fmt);
+
+	/* Use dev_err() for logging when err doesn't equal -EPROBE_DEFER */
+	__dev_probe_failed(dev, err, true, fmt, vargs);
+
+	va_end(vargs);
+
+	return err;
+}
+EXPORT_SYMBOL_GPL(dev_err_probe);
+
+/**
+ * dev_warn_probe - probe error check and log helper
+ * @dev: the pointer to the struct device
+ * @err: error value to test
+ * @fmt: printf-style format string
+ * @...: arguments as specified in the format string
+ *
+ * This helper implements common pattern present in probe functions for error
+ * checking: print debug or warning message depending if the error value is
+ * -EPROBE_DEFER and propagate error upwards.
+ * In case of -EPROBE_DEFER it sets also defer probe reason, which can be
+ * checked later by reading devices_deferred debugfs attribute.
+ * It replaces the following code sequence::
+ *
+ * 	if (err != -EPROBE_DEFER)
+ * 		dev_warn(dev, ...);
+ * 	else
+ * 		dev_dbg(dev, ...);
+ * 	return err;
+ *
+ * with::
+ *
+ * 	return dev_warn_probe(dev, err, ...);
+ *
+ * Using this helper in your probe function is totally fine even if @err
+ * is known to never be -EPROBE_DEFER.
+ * The benefit compared to a normal dev_warn() is the standardized format
+ * of the error code, which is emitted symbolically (i.e. you get "EAGAIN"
+ * instead of "-35"), and having the error code returned allows more
+ * compact error paths.
+ *
+ * Returns @err.
+ */
+int dev_warn_probe(const struct device *dev, int err, const char *fmt, ...)
+{
+	va_list vargs;
+
+	va_start(vargs, fmt);
+
+	/* Use dev_warn() for logging when err doesn't equal -EPROBE_DEFER */
+	__dev_probe_failed(dev, err, false, fmt, vargs);
+
+	va_end(vargs);
+
+	return err;
+}
+EXPORT_SYMBOL_GPL(dev_warn_probe);
+
 static inline bool fwnode_is_primary(struct fwnode_handle *fwnode)
 {
 	return fwnode && !IS_ERR(fwnode->secondary);
@@ -3851,12 +5135,19 @@ static inline bool fwnode_is_primary(struct fwnode_handle *fwnode)
  *
  * Set the device's firmware node pointer to @fwnode, but if a secondary
  * firmware node of the device is present, preserve it.
+ *
+ * Valid fwnode cases are:
+ *  - primary --> secondary --> -ENODEV
+ *  - primary --> NULL
+ *  - secondary --> -ENODEV
+ *  - NULL
  */
 void set_primary_fwnode(struct device *dev, struct fwnode_handle *fwnode)
 {
-	if (fwnode) {
-		struct fwnode_handle *fn = dev->fwnode;
+	struct device *parent = dev->parent;
+	struct fwnode_handle *fn = dev->fwnode;
 
+	if (fwnode) {
 		if (fwnode_is_primary(fn))
 			fn = fn->secondary;
 
@@ -3866,8 +5157,18 @@ void set_primary_fwnode(struct device *dev, struct fwnode_handle *fwnode)
 		}
 		dev->fwnode = fwnode;
 	} else {
-		dev->fwnode = fwnode_is_primary(dev->fwnode) ?
-			dev->fwnode->secondary : NULL;
+		if (fwnode_is_primary(fn)) {
+			dev->fwnode = fn->secondary;
+
+			/* Skip nullifying fn->secondary if the primary is shared */
+			if (parent && fn == parent->fwnode)
+				return;
+
+			/* Set fn->secondary = NULL, so fn remains the primary fwnode */
+			fn->secondary = NULL;
+		} else {
+			dev->fwnode = NULL;
+		}
 	}
 }
 EXPORT_SYMBOL_GPL(set_primary_fwnode);
@@ -3891,6 +5192,68 @@ void set_secondary_fwnode(struct device *dev, struct fwnode_handle *fwnode)
 	else
 		dev->fwnode = fwnode;
 }
+EXPORT_SYMBOL_GPL(set_secondary_fwnode);
+
+/**
+ * device_remove_of_node - Remove an of_node from a device
+ * @dev: device whose device tree node is being removed
+ */
+void device_remove_of_node(struct device *dev)
+{
+	dev = get_device(dev);
+	if (!dev)
+		return;
+
+	if (!dev->of_node)
+		goto end;
+
+	if (dev->fwnode == of_fwnode_handle(dev->of_node))
+		dev->fwnode = NULL;
+
+	of_node_put(dev->of_node);
+	dev->of_node = NULL;
+
+end:
+	put_device(dev);
+}
+EXPORT_SYMBOL_GPL(device_remove_of_node);
+
+/**
+ * device_add_of_node - Add an of_node to an existing device
+ * @dev: device whose device tree node is being added
+ * @of_node: of_node to add
+ *
+ * Return: 0 on success or error code on failure.
+ */
+int device_add_of_node(struct device *dev, struct device_node *of_node)
+{
+	int ret;
+
+	if (!of_node)
+		return -EINVAL;
+
+	dev = get_device(dev);
+	if (!dev)
+		return -EINVAL;
+
+	if (dev->of_node) {
+		dev_err(dev, "Cannot replace node %pOF with %pOF\n",
+			dev->of_node, of_node);
+		ret = -EBUSY;
+		goto end;
+	}
+
+	dev->of_node = of_node_get(of_node);
+
+	if (!dev->fwnode)
+		dev->fwnode = of_fwnode_handle(of_node);
+
+	ret = 0;
+end:
+	put_device(dev);
+	return ret;
+}
+EXPORT_SYMBOL_GPL(device_add_of_node);
 
 /**
  * device_set_of_node_from_dev - reuse device-tree node of another device
@@ -3908,21 +5271,59 @@ void device_set_of_node_from_dev(struct device *dev, const struct device *dev2)
 }
 EXPORT_SYMBOL_GPL(device_set_of_node_from_dev);
 
+void device_set_node(struct device *dev, struct fwnode_handle *fwnode)
+{
+	dev->fwnode = fwnode;
+	dev->of_node = to_of_node(fwnode);
+}
+EXPORT_SYMBOL_GPL(device_set_node);
+
+/**
+ * get_dev_from_fwnode - Obtain a reference count of the struct device the
+ * struct fwnode_handle is associated with.
+ * @fwnode: The pointer to the struct fwnode_handle to obtain the struct device
+ * reference count of.
+ *
+ * This function obtains a reference count of the device the device pointer
+ * embedded in the struct fwnode_handle points to.
+ *
+ * Note that the struct device pointer embedded in struct fwnode_handle does
+ * *not* have a reference count of the struct device itself.
+ *
+ * Hence, it is a UAF (and thus a bug) to call this function if the caller can't
+ * guarantee that the last reference count of the corresponding struct device is
+ * not dropped concurrently.
+ *
+ * This is possible since struct fwnode_handle has its own reference count and
+ * hence can out-live the struct device it is associated with.
+ */
+struct device *get_dev_from_fwnode(struct fwnode_handle *fwnode)
+{
+	return get_device((fwnode)->dev);
+}
+EXPORT_SYMBOL_GPL(get_dev_from_fwnode);
+
 int device_match_name(struct device *dev, const void *name)
 {
 	return sysfs_streq(dev_name(dev), name);
 }
 EXPORT_SYMBOL_GPL(device_match_name);
 
+int device_match_type(struct device *dev, const void *type)
+{
+	return dev->type == type;
+}
+EXPORT_SYMBOL_GPL(device_match_type);
+
 int device_match_of_node(struct device *dev, const void *np)
 {
-	return dev->of_node == np;
+	return np && dev->of_node == np;
 }
 EXPORT_SYMBOL_GPL(device_match_of_node);
 
 int device_match_fwnode(struct device *dev, const void *fwnode)
 {
-	return dev_fwnode(dev) == fwnode;
+	return fwnode && dev_fwnode(dev) == fwnode;
 }
 EXPORT_SYMBOL_GPL(device_match_fwnode);
 
@@ -3934,10 +5335,16 @@ EXPORT_SYMBOL_GPL(device_match_devt);
 
 int device_match_acpi_dev(struct device *dev, const void *adev)
 {
-	return ACPI_COMPANION(dev) == adev;
+	return adev && ACPI_COMPANION(dev) == adev;
 }
 EXPORT_SYMBOL(device_match_acpi_dev);
 
+int device_match_acpi_handle(struct device *dev, const void *handle)
+{
+	return handle && ACPI_HANDLE(dev) == handle;
+}
+EXPORT_SYMBOL(device_match_acpi_handle);
+
 int device_match_any(struct device *dev, const void *unused)
 {
 	return 1;
diff --git a/drivers/base/cpu.c b/drivers/base/cpu.c
index 9a1c00fbbaef..c6c57b6f61c6 100644
--- a/drivers/base/cpu.c
+++ b/drivers/base/cpu.c
@@ -19,13 +19,14 @@
 #include <linux/cpufeature.h>
 #include <linux/tick.h>
 #include <linux/pm_qos.h>
+#include <linux/delay.h>
 #include <linux/sched/isolation.h>
 
 #include "base.h"
 
 static DEFINE_PER_CPU(struct device *, cpu_sys_devices);
 
-static int cpu_subsys_match(struct device *dev, struct device_driver *drv)
+static int cpu_subsys_match(struct device *dev, const struct device_driver *drv)
 {
 	/* ACPI style match is the only one that may succeed. */
 	if (acpi_driver_match_device(dev, drv))
@@ -50,12 +51,30 @@ static int cpu_subsys_online(struct device *dev)
 	int cpuid = dev->id;
 	int from_nid, to_nid;
 	int ret;
+	int retries = 0;
 
 	from_nid = cpu_to_node(cpuid);
 	if (from_nid == NUMA_NO_NODE)
 		return -ENODEV;
 
+retry:
 	ret = cpu_device_up(dev);
+
+	/*
+	 * If -EBUSY is returned, it is likely that hotplug is temporarily
+	 * disabled when cpu_hotplug_disable() was called. This condition is
+	 * transient. So we retry after waiting for an exponentially
+	 * increasing delay up to a total of at least 620ms as some PCI
+	 * device initialization can take quite a while.
+	 */
+	if (ret == -EBUSY) {
+		retries++;
+		if (retries > 5)
+			return ret;
+		msleep(10 * (1 << retries));
+		goto retry;
+	}
+
 	/*
 	 * When hot adding memory to memoryless node and enabling a cpu
 	 * on the node, node number of the cpu may internally change.
@@ -76,6 +95,7 @@ void unregister_cpu(struct cpu *cpu)
 {
 	int logical_cpu = cpu->dev.id;
 
+	set_cpu_enabled(logical_cpu, false);
 	unregister_cpu_under_node(logical_cpu, cpu_to_node(logical_cpu));
 
 	device_unregister(&cpu->dev);
@@ -125,25 +145,14 @@ static DEVICE_ATTR(release, S_IWUSR, NULL, cpu_release_store);
 #endif /* CONFIG_ARCH_CPU_PROBE_RELEASE */
 #endif /* CONFIG_HOTPLUG_CPU */
 
-struct bus_type cpu_subsys = {
-	.name = "cpu",
-	.dev_name = "cpu",
-	.match = cpu_subsys_match,
-#ifdef CONFIG_HOTPLUG_CPU
-	.online = cpu_subsys_online,
-	.offline = cpu_subsys_offline,
-#endif
-};
-EXPORT_SYMBOL_GPL(cpu_subsys);
-
-#ifdef CONFIG_KEXEC
+#ifdef CONFIG_CRASH_DUMP
 #include <linux/kexec.h>
 
-static ssize_t show_crash_notes(struct device *dev, struct device_attribute *attr,
+static ssize_t crash_notes_show(struct device *dev,
+				struct device_attribute *attr,
 				char *buf)
 {
 	struct cpu *cpu = container_of(dev, struct cpu, dev);
-	ssize_t rc;
 	unsigned long long addr;
 	int cpunum;
 
@@ -156,21 +165,18 @@ static ssize_t show_crash_notes(struct device *dev, struct device_attribute *att
 	 * operation should be safe. No locking required.
 	 */
 	addr = per_cpu_ptr_to_phys(per_cpu_ptr(crash_notes, cpunum));
-	rc = sprintf(buf, "%Lx\n", addr);
-	return rc;
+
+	return sysfs_emit(buf, "%llx\n", addr);
 }
-static DEVICE_ATTR(crash_notes, 0400, show_crash_notes, NULL);
+static DEVICE_ATTR_ADMIN_RO(crash_notes);
 
-static ssize_t show_crash_notes_size(struct device *dev,
+static ssize_t crash_notes_size_show(struct device *dev,
 				     struct device_attribute *attr,
 				     char *buf)
 {
-	ssize_t rc;
-
-	rc = sprintf(buf, "%zu\n", sizeof(note_buf_t));
-	return rc;
+	return sysfs_emit(buf, "%zu\n", sizeof(note_buf_t));
 }
-static DEVICE_ATTR(crash_notes_size, 0400, show_crash_notes_size, NULL);
+static DEVICE_ATTR_ADMIN_RO(crash_notes_size);
 
 static struct attribute *crash_note_cpu_attrs[] = {
 	&dev_attr_crash_notes.attr,
@@ -178,20 +184,20 @@ static struct attribute *crash_note_cpu_attrs[] = {
 	NULL
 };
 
-static struct attribute_group crash_note_cpu_attr_group = {
+static const struct attribute_group crash_note_cpu_attr_group = {
 	.attrs = crash_note_cpu_attrs,
 };
 #endif
 
 static const struct attribute_group *common_cpu_attr_groups[] = {
-#ifdef CONFIG_KEXEC
+#ifdef CONFIG_CRASH_DUMP
 	&crash_note_cpu_attr_group,
 #endif
 	NULL
 };
 
 static const struct attribute_group *hotplugable_cpu_attr_groups[] = {
-#ifdef CONFIG_KEXEC
+#ifdef CONFIG_CRASH_DUMP
 	&crash_note_cpu_attr_group,
 #endif
 	NULL
@@ -231,7 +237,7 @@ static struct cpu_attr cpu_attrs[] = {
 static ssize_t print_cpus_kernel_max(struct device *dev,
 				     struct device_attribute *attr, char *buf)
 {
-	return sprintf(buf, "%d\n", NR_CPUS - 1);
+	return sysfs_emit(buf, "%d\n", NR_CPUS - 1);
 }
 static DEVICE_ATTR(kernel_max, 0444, print_cpus_kernel_max, NULL);
 
@@ -241,59 +247,93 @@ unsigned int total_cpus;
 static ssize_t print_cpus_offline(struct device *dev,
 				  struct device_attribute *attr, char *buf)
 {
-	int n = 0, len = PAGE_SIZE-2;
+	int len = 0;
 	cpumask_var_t offline;
 
 	/* display offline cpus < nr_cpu_ids */
 	if (!alloc_cpumask_var(&offline, GFP_KERNEL))
 		return -ENOMEM;
 	cpumask_andnot(offline, cpu_possible_mask, cpu_online_mask);
-	n = scnprintf(buf, len, "%*pbl", cpumask_pr_args(offline));
+	len += sysfs_emit_at(buf, len, "%*pbl", cpumask_pr_args(offline));
 	free_cpumask_var(offline);
 
 	/* display offline cpus >= nr_cpu_ids */
 	if (total_cpus && nr_cpu_ids < total_cpus) {
-		if (n && n < len)
-			buf[n++] = ',';
+		len += sysfs_emit_at(buf, len, ",");
 
 		if (nr_cpu_ids == total_cpus-1)
-			n += scnprintf(&buf[n], len - n, "%u", nr_cpu_ids);
+			len += sysfs_emit_at(buf, len, "%u", nr_cpu_ids);
 		else
-			n += scnprintf(&buf[n], len - n, "%u-%d",
-						      nr_cpu_ids, total_cpus-1);
+			len += sysfs_emit_at(buf, len, "%u-%d",
+					     nr_cpu_ids, total_cpus - 1);
 	}
 
-	n += scnprintf(&buf[n], len - n, "\n");
-	return n;
+	len += sysfs_emit_at(buf, len, "\n");
+
+	return len;
 }
 static DEVICE_ATTR(offline, 0444, print_cpus_offline, NULL);
 
+static ssize_t print_cpus_enabled(struct device *dev,
+				  struct device_attribute *attr, char *buf)
+{
+	return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(cpu_enabled_mask));
+}
+static DEVICE_ATTR(enabled, 0444, print_cpus_enabled, NULL);
+
 static ssize_t print_cpus_isolated(struct device *dev,
 				  struct device_attribute *attr, char *buf)
 {
-	int n;
+	int len;
 	cpumask_var_t isolated;
 
 	if (!alloc_cpumask_var(&isolated, GFP_KERNEL))
 		return -ENOMEM;
 
 	cpumask_andnot(isolated, cpu_possible_mask,
-		       housekeeping_cpumask(HK_FLAG_DOMAIN));
-	n = sprintf(buf, "%*pbl\n", cpumask_pr_args(isolated));
+		       housekeeping_cpumask(HK_TYPE_DOMAIN));
+	len = sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(isolated));
 
 	free_cpumask_var(isolated);
 
-	return n;
+	return len;
 }
 static DEVICE_ATTR(isolated, 0444, print_cpus_isolated, NULL);
 
+static ssize_t housekeeping_show(struct device *dev,
+			     struct device_attribute *attr, char *buf)
+{
+	const struct cpumask *hk_mask;
+
+	hk_mask = housekeeping_cpumask(HK_TYPE_KERNEL_NOISE);
+
+	if (housekeeping_enabled(HK_TYPE_KERNEL_NOISE))
+		return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(hk_mask));
+	return sysfs_emit(buf, "\n");
+}
+static DEVICE_ATTR_RO(housekeeping);
+
 #ifdef CONFIG_NO_HZ_FULL
-static ssize_t print_cpus_nohz_full(struct device *dev,
-				  struct device_attribute *attr, char *buf)
+static ssize_t nohz_full_show(struct device *dev,
+				    struct device_attribute *attr,
+				    char *buf)
 {
-	return sprintf(buf, "%*pbl\n", cpumask_pr_args(tick_nohz_full_mask));
+	if (cpumask_available(tick_nohz_full_mask))
+		return sysfs_emit(buf, "%*pbl\n",
+				  cpumask_pr_args(tick_nohz_full_mask));
+	return sysfs_emit(buf, "\n");
 }
-static DEVICE_ATTR(nohz_full, 0444, print_cpus_nohz_full, NULL);
+static DEVICE_ATTR_RO(nohz_full);
+#endif
+
+#ifdef CONFIG_CRASH_HOTPLUG
+static ssize_t crash_hotplug_show(struct device *dev,
+				     struct device_attribute *attr,
+				     char *buf)
+{
+	return sysfs_emit(buf, "%d\n", crash_check_hotplug_support());
+}
+static DEVICE_ATTR_RO(crash_hotplug);
 #endif
 
 static void cpu_device_release(struct device *dev)
@@ -302,7 +342,7 @@ static void cpu_device_release(struct device *dev)
 	 * This is an empty function to prevent the driver core from spitting a
 	 * warning at us.  Yes, I know this is directly opposite of what the
 	 * documentation for the driver core and kobjects say, and the author
-	 * of this code has already been publically ridiculed for doing
+	 * of this code has already been publicly ridiculed for doing
 	 * something as foolish as this.  However, at this point in time, it is
 	 * the only way to handle the issue of statically allocated cpu
 	 * devices.  The different architectures will have their cpu device
@@ -320,25 +360,26 @@ static ssize_t print_cpu_modalias(struct device *dev,
 				  struct device_attribute *attr,
 				  char *buf)
 {
-	ssize_t n;
+	int len = 0;
 	u32 i;
 
-	n = sprintf(buf, "cpu:type:" CPU_FEATURE_TYPEFMT ":feature:",
-		    CPU_FEATURE_TYPEVAL);
+	len += sysfs_emit_at(buf, len,
+			     "cpu:type:" CPU_FEATURE_TYPEFMT ":feature:",
+			     CPU_FEATURE_TYPEVAL);
 
 	for (i = 0; i < MAX_CPU_FEATURES; i++)
 		if (cpu_have_feature(i)) {
-			if (PAGE_SIZE < n + sizeof(",XXXX\n")) {
+			if (len + sizeof(",XXXX\n") >= PAGE_SIZE) {
 				WARN(1, "CPU features overflow page\n");
 				break;
 			}
-			n += sprintf(&buf[n], ",%04X", i);
+			len += sysfs_emit_at(buf, len, ",%04X", i);
 		}
-	buf[n++] = '\n';
-	return n;
+	len += sysfs_emit_at(buf, len, "\n");
+	return len;
 }
 
-static int cpu_uevent(struct device *dev, struct kobj_uevent_env *env)
+static int cpu_uevent(const struct device *dev, struct kobj_uevent_env *env)
 {
 	char *buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
 	if (buf) {
@@ -350,6 +391,20 @@ static int cpu_uevent(struct device *dev, struct kobj_uevent_env *env)
 }
 #endif
 
+const struct bus_type cpu_subsys = {
+	.name = "cpu",
+	.dev_name = "cpu",
+	.match = cpu_subsys_match,
+#ifdef CONFIG_HOTPLUG_CPU
+	.online = cpu_subsys_online,
+	.offline = cpu_subsys_offline,
+#endif
+#ifdef CONFIG_GENERIC_CPU_AUTOPROBE
+	.uevent = cpu_uevent,
+#endif
+};
+EXPORT_SYMBOL_GPL(cpu_subsys);
+
 /*
  * register_cpu - Setup a sysfs device for a CPU.
  * @cpu - cpu->hotpluggable field set to 1 will generate a control file in
@@ -370,9 +425,6 @@ int register_cpu(struct cpu *cpu, int num)
 	cpu->dev.offline_disabled = !cpu->hotpluggable;
 	cpu->dev.offline = !cpu_online(num);
 	cpu->dev.of_node = of_get_cpu_node(num, NULL);
-#ifdef CONFIG_GENERIC_CPU_AUTOPROBE
-	cpu->dev.bus->uevent = cpu_uevent;
-#endif
 	cpu->dev.groups = common_cpu_attr_groups;
 	if (cpu->hotpluggable)
 		cpu->dev.groups = hotplugable_cpu_attr_groups;
@@ -386,11 +438,12 @@ int register_cpu(struct cpu *cpu, int num)
 	register_cpu_under_node(num, cpu_to_node(num));
 	dev_pm_qos_expose_latency_limit(&cpu->dev,
 					PM_QOS_RESUME_LATENCY_NO_CONSTRAINT);
+	set_cpu_enabled(num, true);
 
 	return 0;
 }
 
-struct device *get_cpu_device(unsigned cpu)
+struct device *get_cpu_device(unsigned int cpu)
 {
 	if (cpu < nr_cpu_ids && cpu_possible(cpu))
 		return per_cpu(cpu_sys_devices, cpu);
@@ -411,13 +464,11 @@ __cpu_device_create(struct device *parent, void *drvdata,
 		    const char *fmt, va_list args)
 {
 	struct device *dev = NULL;
-	int retval = -ENODEV;
+	int retval = -ENOMEM;
 
 	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
-	if (!dev) {
-		retval = -ENOMEM;
+	if (!dev)
 		goto error;
-	}
 
 	device_initialize(dev);
 	dev->parent = parent;
@@ -469,17 +520,22 @@ static struct attribute *cpu_root_attrs[] = {
 	&cpu_attrs[2].attr.attr,
 	&dev_attr_kernel_max.attr,
 	&dev_attr_offline.attr,
+	&dev_attr_enabled.attr,
 	&dev_attr_isolated.attr,
+	&dev_attr_housekeeping.attr,
 #ifdef CONFIG_NO_HZ_FULL
 	&dev_attr_nohz_full.attr,
 #endif
+#ifdef CONFIG_CRASH_HOTPLUG
+	&dev_attr_crash_hotplug.attr,
+#endif
 #ifdef CONFIG_GENERIC_CPU_AUTOPROBE
 	&dev_attr_modalias.attr,
 #endif
 	NULL
 };
 
-static struct attribute_group cpu_root_attr_group = {
+static const struct attribute_group cpu_root_attr_group = {
 	.attrs = cpu_root_attrs,
 };
 
@@ -488,79 +544,84 @@ static const struct attribute_group *cpu_root_attr_groups[] = {
 	NULL,
 };
 
-bool cpu_is_hotpluggable(unsigned cpu)
+bool cpu_is_hotpluggable(unsigned int cpu)
 {
 	struct device *dev = get_cpu_device(cpu);
-	return dev && container_of(dev, struct cpu, dev)->hotpluggable;
+	return dev && container_of(dev, struct cpu, dev)->hotpluggable
+		&& tick_nohz_cpu_hotpluggable(cpu);
 }
 EXPORT_SYMBOL_GPL(cpu_is_hotpluggable);
 
 #ifdef CONFIG_GENERIC_CPU_DEVICES
-static DEFINE_PER_CPU(struct cpu, cpu_devices);
-#endif
+DEFINE_PER_CPU(struct cpu, cpu_devices);
 
-static void __init cpu_dev_register_generic(void)
+bool __weak arch_cpu_is_hotpluggable(int cpu)
 {
-#ifdef CONFIG_GENERIC_CPU_DEVICES
-	int i;
-
-	for_each_possible_cpu(i) {
-		if (register_cpu(&per_cpu(cpu_devices, i), i))
-			panic("Failed to register CPU device");
-	}
-#endif
+	return false;
 }
 
-#ifdef CONFIG_GENERIC_CPU_VULNERABILITIES
-
-ssize_t __weak cpu_show_meltdown(struct device *dev,
-				 struct device_attribute *attr, char *buf)
+int __weak arch_register_cpu(int cpu)
 {
-	return sprintf(buf, "Not affected\n");
-}
+	struct cpu *c = &per_cpu(cpu_devices, cpu);
 
-ssize_t __weak cpu_show_spectre_v1(struct device *dev,
-				   struct device_attribute *attr, char *buf)
-{
-	return sprintf(buf, "Not affected\n");
-}
+	c->hotpluggable = arch_cpu_is_hotpluggable(cpu);
 
-ssize_t __weak cpu_show_spectre_v2(struct device *dev,
-				   struct device_attribute *attr, char *buf)
-{
-	return sprintf(buf, "Not affected\n");
+	return register_cpu(c, cpu);
 }
 
-ssize_t __weak cpu_show_spec_store_bypass(struct device *dev,
-					  struct device_attribute *attr, char *buf)
+#ifdef CONFIG_HOTPLUG_CPU
+void __weak arch_unregister_cpu(int num)
 {
-	return sprintf(buf, "Not affected\n");
+	unregister_cpu(&per_cpu(cpu_devices, num));
 }
+#endif /* CONFIG_HOTPLUG_CPU */
+#endif /* CONFIG_GENERIC_CPU_DEVICES */
 
-ssize_t __weak cpu_show_l1tf(struct device *dev,
-			     struct device_attribute *attr, char *buf)
+static void __init cpu_dev_register_generic(void)
 {
-	return sprintf(buf, "Not affected\n");
-}
+	int i, ret;
 
-ssize_t __weak cpu_show_mds(struct device *dev,
-			    struct device_attribute *attr, char *buf)
-{
-	return sprintf(buf, "Not affected\n");
-}
+	if (!IS_ENABLED(CONFIG_GENERIC_CPU_DEVICES))
+		return;
 
-ssize_t __weak cpu_show_tsx_async_abort(struct device *dev,
-					struct device_attribute *attr,
-					char *buf)
-{
-	return sprintf(buf, "Not affected\n");
+	for_each_present_cpu(i) {
+		ret = arch_register_cpu(i);
+		if (ret && ret != -EPROBE_DEFER)
+			pr_warn("register_cpu %d failed (%d)\n", i, ret);
+	}
 }
 
-ssize_t __weak cpu_show_itlb_multihit(struct device *dev,
-			    struct device_attribute *attr, char *buf)
-{
-	return sprintf(buf, "Not affected\n");
-}
+#ifdef CONFIG_GENERIC_CPU_VULNERABILITIES
+static ssize_t cpu_show_not_affected(struct device *dev,
+			      struct device_attribute *attr, char *buf)
+{
+	return sysfs_emit(buf, "Not affected\n");
+}
+
+#define CPU_SHOW_VULN_FALLBACK(func)					\
+	ssize_t cpu_show_##func(struct device *,			\
+				  struct device_attribute *, char *)	\
+		 __attribute__((weak, alias("cpu_show_not_affected")))
+
+CPU_SHOW_VULN_FALLBACK(meltdown);
+CPU_SHOW_VULN_FALLBACK(spectre_v1);
+CPU_SHOW_VULN_FALLBACK(spectre_v2);
+CPU_SHOW_VULN_FALLBACK(spec_store_bypass);
+CPU_SHOW_VULN_FALLBACK(l1tf);
+CPU_SHOW_VULN_FALLBACK(mds);
+CPU_SHOW_VULN_FALLBACK(tsx_async_abort);
+CPU_SHOW_VULN_FALLBACK(itlb_multihit);
+CPU_SHOW_VULN_FALLBACK(srbds);
+CPU_SHOW_VULN_FALLBACK(mmio_stale_data);
+CPU_SHOW_VULN_FALLBACK(retbleed);
+CPU_SHOW_VULN_FALLBACK(spec_rstack_overflow);
+CPU_SHOW_VULN_FALLBACK(gds);
+CPU_SHOW_VULN_FALLBACK(reg_file_data_sampling);
+CPU_SHOW_VULN_FALLBACK(ghostwrite);
+CPU_SHOW_VULN_FALLBACK(old_microcode);
+CPU_SHOW_VULN_FALLBACK(indirect_target_selection);
+CPU_SHOW_VULN_FALLBACK(tsa);
+CPU_SHOW_VULN_FALLBACK(vmscape);
 
 static DEVICE_ATTR(meltdown, 0444, cpu_show_meltdown, NULL);
 static DEVICE_ATTR(spectre_v1, 0444, cpu_show_spectre_v1, NULL);
@@ -570,6 +631,17 @@ static DEVICE_ATTR(l1tf, 0444, cpu_show_l1tf, NULL);
 static DEVICE_ATTR(mds, 0444, cpu_show_mds, NULL);
 static DEVICE_ATTR(tsx_async_abort, 0444, cpu_show_tsx_async_abort, NULL);
 static DEVICE_ATTR(itlb_multihit, 0444, cpu_show_itlb_multihit, NULL);
+static DEVICE_ATTR(srbds, 0444, cpu_show_srbds, NULL);
+static DEVICE_ATTR(mmio_stale_data, 0444, cpu_show_mmio_stale_data, NULL);
+static DEVICE_ATTR(retbleed, 0444, cpu_show_retbleed, NULL);
+static DEVICE_ATTR(spec_rstack_overflow, 0444, cpu_show_spec_rstack_overflow, NULL);
+static DEVICE_ATTR(gather_data_sampling, 0444, cpu_show_gds, NULL);
+static DEVICE_ATTR(reg_file_data_sampling, 0444, cpu_show_reg_file_data_sampling, NULL);
+static DEVICE_ATTR(ghostwrite, 0444, cpu_show_ghostwrite, NULL);
+static DEVICE_ATTR(old_microcode, 0444, cpu_show_old_microcode, NULL);
+static DEVICE_ATTR(indirect_target_selection, 0444, cpu_show_indirect_target_selection, NULL);
+static DEVICE_ATTR(tsa, 0444, cpu_show_tsa, NULL);
+static DEVICE_ATTR(vmscape, 0444, cpu_show_vmscape, NULL);
 
 static struct attribute *cpu_root_vulnerabilities_attrs[] = {
 	&dev_attr_meltdown.attr,
@@ -580,6 +652,17 @@ static struct attribute *cpu_root_vulnerabilities_attrs[] = {
 	&dev_attr_mds.attr,
 	&dev_attr_tsx_async_abort.attr,
 	&dev_attr_itlb_multihit.attr,
+	&dev_attr_srbds.attr,
+	&dev_attr_mmio_stale_data.attr,
+	&dev_attr_retbleed.attr,
+	&dev_attr_spec_rstack_overflow.attr,
+	&dev_attr_gather_data_sampling.attr,
+	&dev_attr_reg_file_data_sampling.attr,
+	&dev_attr_ghostwrite.attr,
+	&dev_attr_old_microcode.attr,
+	&dev_attr_indirect_target_selection.attr,
+	&dev_attr_tsa.attr,
+	&dev_attr_vmscape.attr,
 	NULL
 };
 
@@ -590,9 +673,13 @@ static const struct attribute_group cpu_root_vulnerabilities_group = {
 
 static void __init cpu_register_vulnerabilities(void)
 {
-	if (sysfs_create_group(&cpu_subsys.dev_root->kobj,
-			       &cpu_root_vulnerabilities_group))
-		pr_err("Unable to register CPU vulnerabilities\n");
+	struct device *dev = bus_get_dev_root(&cpu_subsys);
+
+	if (dev) {
+		if (sysfs_create_group(&dev->kobj, &cpu_root_vulnerabilities_group))
+			pr_err("Unable to register CPU vulnerabilities\n");
+		put_device(dev);
+	}
 }
 
 #else
diff --git a/drivers/base/dd.c b/drivers/base/dd.c
index 06ec0e851fa1..349f31bedfa1 100644
--- a/drivers/base/dd.c
+++ b/drivers/base/dd.c
@@ -19,14 +19,16 @@
 #include <linux/debugfs.h>
 #include <linux/device.h>
 #include <linux/delay.h>
-#include <linux/dma-mapping.h>
+#include <linux/dma-map-ops.h>
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/kthread.h>
 #include <linux/wait.h>
 #include <linux/async.h>
+#include <linux/pm_domain.h>
 #include <linux/pm_runtime.h>
 #include <linux/pinctrl/devinfo.h>
+#include <linux/slab.h>
 
 #include "base.h"
 #include "power/power.h"
@@ -54,12 +56,12 @@ static DEFINE_MUTEX(deferred_probe_mutex);
 static LIST_HEAD(deferred_probe_pending_list);
 static LIST_HEAD(deferred_probe_active_list);
 static atomic_t deferred_trigger_count = ATOMIC_INIT(0);
-static struct dentry *deferred_devices;
 static bool initcalls_done;
 
 /* Save the async probe drivers' name from kernel cmdline */
 #define ASYNC_DRV_NAMES_MAX_LEN	256
 static char async_probe_drv_names[ASYNC_DRV_NAMES_MAX_LEN];
+static bool async_probe_default;
 
 /*
  * In some cases, like suspend to RAM or hibernation, It might be reasonable
@@ -68,6 +70,12 @@ static char async_probe_drv_names[ASYNC_DRV_NAMES_MAX_LEN];
  */
 static bool defer_all_probes;
 
+static void __device_set_deferred_probe_reason(const struct device *dev, char *reason)
+{
+	kfree(dev->p->deferred_probe_reason);
+	dev->p->deferred_probe_reason = reason;
+}
+
 /*
  * deferred_probe_work_func() - Retry probing devices in the active list.
  */
@@ -96,6 +104,8 @@ static void deferred_probe_work_func(struct work_struct *work)
 
 		get_device(dev);
 
+		__device_set_deferred_probe_reason(dev, NULL);
+
 		/*
 		 * Drop the mutex while probing each device; the probe path may
 		 * manipulate the deferred list
@@ -122,6 +132,9 @@ static DECLARE_WORK(deferred_probe_work, deferred_probe_work_func);
 
 void driver_deferred_probe_add(struct device *dev)
 {
+	if (!dev->can_match)
+		return;
+
 	mutex_lock(&deferred_probe_mutex);
 	if (list_empty(&dev->p->deferred_probe)) {
 		dev_dbg(dev, "Added to deferred list\n");
@@ -136,11 +149,12 @@ void driver_deferred_probe_del(struct device *dev)
 	if (!list_empty(&dev->p->deferred_probe)) {
 		dev_dbg(dev, "Removed from deferred list\n");
 		list_del_init(&dev->p->deferred_probe);
+		__device_set_deferred_probe_reason(dev, NULL);
 	}
 	mutex_unlock(&deferred_probe_mutex);
 }
 
-static bool driver_deferred_probe_enable = false;
+static bool driver_deferred_probe_enable;
 /**
  * driver_deferred_probe_trigger() - Kick off re-probing deferred devices
  *
@@ -159,7 +173,7 @@ static bool driver_deferred_probe_enable = false;
  * changes in the midst of a probe, then deferred processing should be triggered
  * again.
  */
-static void driver_deferred_probe_trigger(void)
+void driver_deferred_probe_trigger(void)
 {
 	if (!driver_deferred_probe_enable)
 		return;
@@ -179,7 +193,7 @@ static void driver_deferred_probe_trigger(void)
 	 * Kick the re-probe thread.  It may already be scheduled, but it is
 	 * safe to kick it again.
 	 */
-	schedule_work(&deferred_probe_work);
+	queue_work(system_dfl_wq, &deferred_probe_work);
 }
 
 /**
@@ -206,6 +220,24 @@ void device_unblock_probing(void)
 	driver_deferred_probe_trigger();
 }
 
+/**
+ * device_set_deferred_probe_reason() - Set defer probe reason message for device
+ * @dev: the pointer to the struct device
+ * @vaf: the pointer to va_format structure with message
+ */
+void device_set_deferred_probe_reason(const struct device *dev, struct va_format *vaf)
+{
+	const char *drv = dev_driver_string(dev);
+	char *reason;
+
+	mutex_lock(&deferred_probe_mutex);
+
+	reason = kasprintf(GFP_KERNEL, "%s: %pV", drv, vaf);
+	__device_set_deferred_probe_reason(dev, reason);
+
+	mutex_unlock(&deferred_probe_mutex);
+}
+
 /*
  * deferred_devs_show() - Show the devices in the deferred probe pending list.
  */
@@ -216,7 +248,8 @@ static int deferred_devs_show(struct seq_file *s, void *data)
 	mutex_lock(&deferred_probe_mutex);
 
 	list_for_each_entry(curr, &deferred_probe_pending_list, deferred_probe)
-		seq_printf(s, "%s\n", dev_name(curr->device));
+		seq_printf(s, "%s\t%s", dev_name(curr->device),
+			   curr->deferred_probe_reason ?: "\n");
 
 	mutex_unlock(&deferred_probe_mutex);
 
@@ -225,16 +258,10 @@ static int deferred_devs_show(struct seq_file *s, void *data)
 DEFINE_SHOW_ATTRIBUTE(deferred_devs);
 
 #ifdef CONFIG_MODULES
-/*
- * In the case of modules, set the default probe timeout to
- * 30 seconds to give userland some time to load needed modules
- */
-int driver_deferred_probe_timeout = 30;
+static int driver_deferred_probe_timeout = 10;
 #else
-/* In the case of !modules, no probe timeout needed */
-int driver_deferred_probe_timeout = -1;
+static int driver_deferred_probe_timeout;
 #endif
-EXPORT_SYMBOL_GPL(driver_deferred_probe_timeout);
 
 static int __init deferred_probe_timeout_setup(char *str)
 {
@@ -251,10 +278,10 @@ __setup("deferred_probe_timeout=", deferred_probe_timeout_setup);
  * @dev: device to check
  *
  * Return:
- * -ENODEV if initcalls have completed and modules are disabled.
- * -ETIMEDOUT if the deferred probe timeout was set and has expired
- *  and modules are enabled.
- * -EPROBE_DEFER in other cases.
+ * * -ENODEV if initcalls have completed and modules are disabled.
+ * * -ETIMEDOUT if the deferred probe timeout was set and has expired
+ *   and modules are enabled.
+ * * -EPROBE_DEFER in other cases.
  *
  * Drivers or subsystems can opt-in to calling this function instead of directly
  * returning -EPROBE_DEFER.
@@ -262,31 +289,52 @@ __setup("deferred_probe_timeout=", deferred_probe_timeout_setup);
 int driver_deferred_probe_check_state(struct device *dev)
 {
 	if (!IS_ENABLED(CONFIG_MODULES) && initcalls_done) {
-		dev_warn(dev, "ignoring dependency for device, assuming no driver");
+		dev_warn(dev, "ignoring dependency for device, assuming no driver\n");
 		return -ENODEV;
 	}
 
-	if (!driver_deferred_probe_timeout) {
-		dev_WARN(dev, "deferred probe timeout, ignoring dependency");
+	if (!driver_deferred_probe_timeout && initcalls_done) {
+		dev_warn(dev, "deferred probe timeout, ignoring dependency\n");
 		return -ETIMEDOUT;
 	}
 
 	return -EPROBE_DEFER;
 }
+EXPORT_SYMBOL_GPL(driver_deferred_probe_check_state);
 
 static void deferred_probe_timeout_work_func(struct work_struct *work)
 {
-	struct device_private *private, *p;
+	struct device_private *p;
+
+	fw_devlink_drivers_done();
 
 	driver_deferred_probe_timeout = 0;
 	driver_deferred_probe_trigger();
 	flush_work(&deferred_probe_work);
 
-	list_for_each_entry_safe(private, p, &deferred_probe_pending_list, deferred_probe)
-		dev_info(private->device, "deferred probe pending");
+	mutex_lock(&deferred_probe_mutex);
+	list_for_each_entry(p, &deferred_probe_pending_list, deferred_probe)
+		dev_warn(p->device, "deferred probe pending: %s", p->deferred_probe_reason ?: "(reason unknown)\n");
+	mutex_unlock(&deferred_probe_mutex);
+
+	fw_devlink_probing_done();
 }
 static DECLARE_DELAYED_WORK(deferred_probe_timeout_work, deferred_probe_timeout_work_func);
 
+void deferred_probe_extend_timeout(void)
+{
+	/*
+	 * If the work hasn't been queued yet or if the work expired, don't
+	 * start a new one.
+	 */
+	if (cancel_delayed_work(&deferred_probe_timeout_work)) {
+		schedule_delayed_work(&deferred_probe_timeout_work,
+				driver_deferred_probe_timeout * HZ);
+		pr_debug("Extended deferred probe timeout by %d secs\n",
+					driver_deferred_probe_timeout);
+	}
+}
+
 /**
  * deferred_probe_initcall() - Enable probing of deferred devices
  *
@@ -296,8 +344,8 @@ static DECLARE_DELAYED_WORK(deferred_probe_timeout_work, deferred_probe_timeout_
  */
 static int deferred_probe_initcall(void)
 {
-	deferred_devices = debugfs_create_file("devices_deferred", 0444, NULL,
-					       NULL, &deferred_devs_fops);
+	debugfs_create_file("devices_deferred", 0444, NULL, NULL,
+			    &deferred_devs_fops);
 
 	driver_deferred_probe_enable = true;
 	driver_deferred_probe_trigger();
@@ -305,6 +353,9 @@ static int deferred_probe_initcall(void)
 	flush_work(&deferred_probe_work);
 	initcalls_done = true;
 
+	if (!IS_ENABLED(CONFIG_MODULES))
+		fw_devlink_drivers_done();
+
 	/*
 	 * Trigger deferred probe again, this time we won't defer anything
 	 * that is optional
@@ -316,13 +367,17 @@ static int deferred_probe_initcall(void)
 		schedule_delayed_work(&deferred_probe_timeout_work,
 			driver_deferred_probe_timeout * HZ);
 	}
+
+	if (!IS_ENABLED(CONFIG_MODULES))
+		fw_devlink_probing_done();
+
 	return 0;
 }
 late_initcall(deferred_probe_initcall);
 
 static void __exit deferred_probe_exit(void)
 {
-	debugfs_remove_recursive(deferred_devices);
+	debugfs_lookup_and_remove("devices_deferred", NULL);
 }
 __exitcall(deferred_probe_exit);
 
@@ -339,17 +394,17 @@ bool device_is_bound(struct device *dev)
 {
 	return dev->p && klist_node_attached(&dev->p->knode_driver);
 }
+EXPORT_SYMBOL_GPL(device_is_bound);
 
 static void driver_bound(struct device *dev)
 {
 	if (device_is_bound(dev)) {
-		printk(KERN_WARNING "%s: device %s already bound\n",
-			__func__, kobject_name(&dev->kobj));
+		dev_warn(dev, "%s: device already bound\n", __func__);
 		return;
 	}
 
-	pr_debug("driver: '%s': %s: bound to device '%s'\n", dev->driver->name,
-		 __func__, dev_name(dev));
+	dev_dbg(dev, "driver: '%s': %s: bound to device\n", dev->driver->name,
+		__func__);
 
 	klist_add_tail(&dev->p->knode_driver, &dev->driver->p->klist_devices);
 	device_links_driver_bound(dev);
@@ -363,10 +418,7 @@ static void driver_bound(struct device *dev)
 	driver_deferred_probe_del(dev);
 	driver_deferred_probe_trigger();
 
-	if (dev->bus)
-		blocking_notifier_call_chain(&dev->bus->p->bus_notifier,
-					     BUS_NOTIFY_BOUND_DRIVER, dev);
-
+	bus_notify(dev, BUS_NOTIFY_BOUND_DRIVER);
 	kobject_uevent(&dev->kobj, KOBJ_BIND);
 }
 
@@ -385,9 +437,7 @@ static int driver_sysfs_add(struct device *dev)
 {
 	int ret;
 
-	if (dev->bus)
-		blocking_notifier_call_chain(&dev->bus->p->bus_notifier,
-					     BUS_NOTIFY_BIND_DRIVER, dev);
+	bus_notify(dev, BUS_NOTIFY_BIND_DRIVER);
 
 	ret = sysfs_create_link(&dev->driver->p->kobj, &dev->kobj,
 				kobject_name(&dev->kobj));
@@ -399,8 +449,11 @@ static int driver_sysfs_add(struct device *dev)
 	if (ret)
 		goto rm_dev;
 
-	if (!IS_ENABLED(CONFIG_DEV_COREDUMP) || !dev->driver->coredump ||
-	    !device_create_file(dev, &dev_attr_coredump))
+	if (!IS_ENABLED(CONFIG_DEV_COREDUMP) || !dev->driver->coredump)
+		return 0;
+
+	ret = device_create_file(dev, &dev_attr_coredump);
+	if (!ret)
 		return 0;
 
 	sysfs_remove_link(&dev->kobj, "driver");
@@ -432,23 +485,25 @@ static void driver_sysfs_remove(struct device *dev)
  * Allow manual attachment of a driver to a device.
  * Caller must have already set @dev->driver.
  *
- * Note that this does not modify the bus reference count
- * nor take the bus's rwsem. Please verify those are accounted
- * for before calling this. (It is ok to call with no other effort
- * from a driver's probe() method.)
+ * Note that this does not modify the bus reference count.
+ * Please verify that is accounted for before calling this.
+ * (It is ok to call with no other effort from a driver's probe() method.)
  *
  * This function must be called with the device lock held.
+ *
+ * Callers should prefer to use device_driver_attach() instead.
  */
 int device_bind_driver(struct device *dev)
 {
 	int ret;
 
 	ret = driver_sysfs_add(dev);
-	if (!ret)
+	if (!ret) {
+		device_links_force_bind(dev);
 		driver_bound(dev);
-	else if (dev->bus)
-		blocking_notifier_call_chain(&dev->bus->p->bus_notifier,
-					     BUS_NOTIFY_DRIVER_NOT_BOUND, dev);
+	}
+	else
+		bus_notify(dev, BUS_NOTIFY_DRIVER_NOT_BOUND);
 	return ret;
 }
 EXPORT_SYMBOL_GPL(device_bind_driver);
@@ -456,21 +511,102 @@ EXPORT_SYMBOL_GPL(device_bind_driver);
 static atomic_t probe_count = ATOMIC_INIT(0);
 static DECLARE_WAIT_QUEUE_HEAD(probe_waitqueue);
 
-static void driver_deferred_probe_add_trigger(struct device *dev,
-					      int local_trigger_count)
+static ssize_t state_synced_store(struct device *dev,
+				  struct device_attribute *attr,
+				  const char *buf, size_t count)
+{
+	int ret = 0;
+
+	if (strcmp("1", buf))
+		return -EINVAL;
+
+	device_lock(dev);
+	if (!dev->state_synced) {
+		dev->state_synced = true;
+		dev_sync_state(dev);
+	} else {
+		ret = -EINVAL;
+	}
+	device_unlock(dev);
+
+	return ret ? ret : count;
+}
+
+static ssize_t state_synced_show(struct device *dev,
+				 struct device_attribute *attr, char *buf)
+{
+	bool val;
+
+	device_lock(dev);
+	val = dev->state_synced;
+	device_unlock(dev);
+
+	return sysfs_emit(buf, "%u\n", val);
+}
+static DEVICE_ATTR_RW(state_synced);
+
+static void device_unbind_cleanup(struct device *dev)
+{
+	devres_release_all(dev);
+	arch_teardown_dma_ops(dev);
+	kfree(dev->dma_range_map);
+	dev->dma_range_map = NULL;
+	device_set_driver(dev, NULL);
+	dev_set_drvdata(dev, NULL);
+	dev_pm_domain_detach(dev, dev->power.detach_power_off);
+	if (dev->pm_domain && dev->pm_domain->dismiss)
+		dev->pm_domain->dismiss(dev);
+	pm_runtime_reinit(dev);
+	dev_pm_set_driver_flags(dev, 0);
+}
+
+static void device_remove(struct device *dev)
 {
-	driver_deferred_probe_add(dev);
-	/* Did a trigger occur while probing? Need to re-trigger if yes */
-	if (local_trigger_count != atomic_read(&deferred_trigger_count))
-		driver_deferred_probe_trigger();
+	device_remove_file(dev, &dev_attr_state_synced);
+	device_remove_groups(dev, dev->driver->dev_groups);
+
+	if (dev->bus && dev->bus->remove)
+		dev->bus->remove(dev);
+	else if (dev->driver->remove)
+		dev->driver->remove(dev);
 }
 
-static int really_probe(struct device *dev, struct device_driver *drv)
+static int call_driver_probe(struct device *dev, const struct device_driver *drv)
+{
+	int ret = 0;
+
+	if (dev->bus->probe)
+		ret = dev->bus->probe(dev);
+	else if (drv->probe)
+		ret = drv->probe(dev);
+
+	switch (ret) {
+	case 0:
+		break;
+	case -EPROBE_DEFER:
+		/* Driver requested deferred probing */
+		dev_dbg(dev, "Driver %s requests probe deferral\n", drv->name);
+		break;
+	case -ENODEV:
+	case -ENXIO:
+		dev_dbg(dev, "probe with driver %s rejects match %d\n",
+			drv->name, ret);
+		break;
+	default:
+		/* driver matched but the probe failed */
+		dev_err(dev, "probe with driver %s failed with error %d\n",
+			drv->name, ret);
+		break;
+	}
+
+	return ret;
+}
+
+static int really_probe(struct device *dev, const struct device_driver *drv)
 {
-	int ret = -EPROBE_DEFER;
-	int local_trigger_count = atomic_read(&deferred_trigger_count);
 	bool test_remove = IS_ENABLED(CONFIG_DEBUG_TEST_DRIVER_REMOVE) &&
 			   !drv->suppress_bind_attrs;
+	int ret, link_ret;
 
 	if (defer_all_probes) {
 		/*
@@ -479,26 +615,23 @@ static int really_probe(struct device *dev, struct device_driver *drv)
 		 * wait_for_device_probe() right after that to avoid any races.
 		 */
 		dev_dbg(dev, "Driver %s force probe deferral\n", drv->name);
-		driver_deferred_probe_add(dev);
-		return ret;
+		return -EPROBE_DEFER;
 	}
 
-	ret = device_links_check_suppliers(dev);
-	if (ret == -EPROBE_DEFER)
-		driver_deferred_probe_add_trigger(dev, local_trigger_count);
-	if (ret)
-		return ret;
+	link_ret = device_links_check_suppliers(dev);
+	if (link_ret == -EPROBE_DEFER)
+		return link_ret;
 
-	atomic_inc(&probe_count);
-	pr_debug("bus: '%s': %s: probing driver %s with device %s\n",
-		 drv->bus->name, __func__, drv->name, dev_name(dev));
+	dev_dbg(dev, "bus: '%s': %s: probing driver %s with device\n",
+		drv->bus->name, __func__, drv->name);
 	if (!list_empty(&dev->devres_head)) {
 		dev_crit(dev, "Resources present before probing\n");
-		return -EBUSY;
+		ret = -EBUSY;
+		goto done;
 	}
 
 re_probe:
-	dev->driver = drv;
+	device_set_driver(dev, drv);
 
 	/* If using pinctrl, bind pins now before probing */
 	ret = pinctrl_bind_pins(dev);
@@ -508,13 +641,13 @@ re_probe:
 	if (dev->bus->dma_configure) {
 		ret = dev->bus->dma_configure(dev);
 		if (ret)
-			goto probe_failed;
+			goto pinctrl_bind_failed;
 	}
 
-	if (driver_sysfs_add(dev)) {
-		printk(KERN_ERR "%s: driver_sysfs_add(%s) failed\n",
-			__func__, dev_name(dev));
-		goto probe_failed;
+	ret = driver_sysfs_add(dev);
+	if (ret) {
+		dev_err(dev, "%s: driver_sysfs_add failed\n", __func__);
+		goto sysfs_failed;
 	}
 
 	if (dev->pm_domain && dev->pm_domain->activate) {
@@ -523,38 +656,47 @@ re_probe:
 			goto probe_failed;
 	}
 
-	if (dev->bus->probe) {
-		ret = dev->bus->probe(dev);
-		if (ret)
-			goto probe_failed;
-	} else if (drv->probe) {
-		ret = drv->probe(dev);
-		if (ret)
-			goto probe_failed;
+	ret = call_driver_probe(dev, drv);
+	if (ret) {
+		/*
+		 * If fw_devlink_best_effort is active (denoted by -EAGAIN), the
+		 * device might actually probe properly once some of its missing
+		 * suppliers have probed. So, treat this as if the driver
+		 * returned -EPROBE_DEFER.
+		 */
+		if (link_ret == -EAGAIN)
+			ret = -EPROBE_DEFER;
+
+		/*
+		 * Return probe errors as positive values so that the callers
+		 * can distinguish them from other errors.
+		 */
+		ret = -ret;
+		goto probe_failed;
 	}
 
-	if (device_add_groups(dev, drv->dev_groups)) {
+	ret = device_add_groups(dev, drv->dev_groups);
+	if (ret) {
 		dev_err(dev, "device_add_groups() failed\n");
 		goto dev_groups_failed;
 	}
 
+	if (dev_has_sync_state(dev)) {
+		ret = device_create_file(dev, &dev_attr_state_synced);
+		if (ret) {
+			dev_err(dev, "state_synced sysfs add failed\n");
+			goto dev_sysfs_state_synced_failed;
+		}
+	}
+
 	if (test_remove) {
 		test_remove = false;
 
-		device_remove_groups(dev, drv->dev_groups);
-
-		if (dev->bus->remove)
-			dev->bus->remove(dev);
-		else if (drv->remove)
-			drv->remove(dev);
-
-		devres_release_all(dev);
+		device_remove(dev);
 		driver_sysfs_remove(dev);
-		dev->driver = NULL;
-		dev_set_drvdata(dev, NULL);
-		if (dev->pm_domain && dev->pm_domain->dismiss)
-			dev->pm_domain->dismiss(dev);
-		pm_runtime_reinit(dev);
+		if (dev->bus && dev->bus->dma_cleanup)
+			dev->bus->dma_cleanup(dev);
+		device_unbind_cleanup(dev);
 
 		goto re_probe;
 	}
@@ -565,74 +707,44 @@ re_probe:
 		dev->pm_domain->sync(dev);
 
 	driver_bound(dev);
-	ret = 1;
-	pr_debug("bus: '%s': %s: bound device %s to driver %s\n",
-		 drv->bus->name, __func__, dev_name(dev), drv->name);
+	dev_dbg(dev, "bus: '%s': %s: bound device to driver %s\n",
+		drv->bus->name, __func__, drv->name);
 	goto done;
 
+dev_sysfs_state_synced_failed:
 dev_groups_failed:
-	if (dev->bus->remove)
-		dev->bus->remove(dev);
-	else if (drv->remove)
-		drv->remove(dev);
+	device_remove(dev);
 probe_failed:
-	if (dev->bus)
-		blocking_notifier_call_chain(&dev->bus->p->bus_notifier,
-					     BUS_NOTIFY_DRIVER_NOT_BOUND, dev);
+	driver_sysfs_remove(dev);
+sysfs_failed:
+	bus_notify(dev, BUS_NOTIFY_DRIVER_NOT_BOUND);
+	if (dev->bus && dev->bus->dma_cleanup)
+		dev->bus->dma_cleanup(dev);
 pinctrl_bind_failed:
 	device_links_no_driver(dev);
-	devres_release_all(dev);
-	arch_teardown_dma_ops(dev);
-	driver_sysfs_remove(dev);
-	dev->driver = NULL;
-	dev_set_drvdata(dev, NULL);
-	if (dev->pm_domain && dev->pm_domain->dismiss)
-		dev->pm_domain->dismiss(dev);
-	pm_runtime_reinit(dev);
-	dev_pm_set_driver_flags(dev, 0);
-
-	switch (ret) {
-	case -EPROBE_DEFER:
-		/* Driver requested deferred probing */
-		dev_dbg(dev, "Driver %s requests probe deferral\n", drv->name);
-		driver_deferred_probe_add_trigger(dev, local_trigger_count);
-		break;
-	case -ENODEV:
-	case -ENXIO:
-		pr_debug("%s: probe of %s rejects match %d\n",
-			 drv->name, dev_name(dev), ret);
-		break;
-	default:
-		/* driver matched but the probe failed */
-		printk(KERN_WARNING
-		       "%s: probe of %s failed with error %d\n",
-		       drv->name, dev_name(dev), ret);
-	}
-	/*
-	 * Ignore errors returned by ->probe so that the next driver can try
-	 * its luck.
-	 */
-	ret = 0;
+	device_unbind_cleanup(dev);
 done:
-	atomic_dec(&probe_count);
-	wake_up(&probe_waitqueue);
 	return ret;
 }
 
 /*
  * For initcall_debug, show the driver probe time.
  */
-static int really_probe_debug(struct device *dev, struct device_driver *drv)
+static int really_probe_debug(struct device *dev, const struct device_driver *drv)
 {
-	ktime_t calltime, delta, rettime;
+	ktime_t calltime, rettime;
 	int ret;
 
 	calltime = ktime_get();
 	ret = really_probe(dev, drv);
 	rettime = ktime_get();
-	delta = ktime_sub(rettime, calltime);
+	/*
+	 * Don't change this to pr_debug() because that requires
+	 * CONFIG_DYNAMIC_DEBUG and we want a simple 'initcall_debug' on the
+	 * kernel commandline to print this all the time at the debug level.
+	 */
 	printk(KERN_DEBUG "probe of %s returned %d after %lld usecs\n",
-	       dev_name(dev), ret, (s64) ktime_to_us(delta));
+		 dev_name(dev), ret, ktime_us_delta(rettime, calltime));
 	return ret;
 }
 
@@ -642,14 +754,12 @@ static int really_probe_debug(struct device *dev, struct device_driver *drv)
  *
  * Should somehow figure out how to use a semaphore, not an atomic variable...
  */
-int driver_probe_done(void)
+bool __init driver_probe_done(void)
 {
 	int local_probe_count = atomic_read(&probe_count);
 
 	pr_debug("%s: probe_count = %d\n", __func__, local_probe_count);
-	if (local_probe_count)
-		return -EBUSY;
-	return 0;
+	return !local_probe_count;
 }
 
 /**
@@ -667,28 +777,18 @@ void wait_for_device_probe(void)
 }
 EXPORT_SYMBOL_GPL(wait_for_device_probe);
 
-/**
- * driver_probe_device - attempt to bind device & driver together
- * @drv: driver to bind a device to
- * @dev: device to try to bind to the driver
- *
- * This function returns -ENODEV if the device is not registered,
- * 1 if the device is bound successfully and 0 otherwise.
- *
- * This function must be called with @dev lock held.  When called for a
- * USB interface, @dev->parent lock must be held as well.
- *
- * If the device has a parent, runtime-resume the parent before driver probing.
- */
-int driver_probe_device(struct device_driver *drv, struct device *dev)
+static int __driver_probe_device(const struct device_driver *drv, struct device *dev)
 {
 	int ret = 0;
 
-	if (!device_is_registered(dev))
+	if (dev->p->dead || !device_is_registered(dev))
 		return -ENODEV;
+	if (dev->driver)
+		return -EBUSY;
 
-	pr_debug("bus: '%s': %s: matched device %s with driver %s\n",
-		 drv->bus->name, __func__, dev_name(dev), drv->name);
+	dev->can_match = true;
+	dev_dbg(dev, "bus: '%s': %s: matched device with driver %s\n",
+		drv->bus->name, __func__, drv->name);
 
 	pm_runtime_get_suppliers(dev);
 	if (dev->parent)
@@ -708,24 +808,65 @@ int driver_probe_device(struct device_driver *drv, struct device *dev)
 	return ret;
 }
 
+/**
+ * driver_probe_device - attempt to bind device & driver together
+ * @drv: driver to bind a device to
+ * @dev: device to try to bind to the driver
+ *
+ * This function returns -ENODEV if the device is not registered, -EBUSY if it
+ * already has a driver, 0 if the device is bound successfully and a positive
+ * (inverted) error code for failures from the ->probe method.
+ *
+ * This function must be called with @dev lock held.  When called for a
+ * USB interface, @dev->parent lock must be held as well.
+ *
+ * If the device has a parent, runtime-resume the parent before driver probing.
+ */
+static int driver_probe_device(const struct device_driver *drv, struct device *dev)
+{
+	int trigger_count = atomic_read(&deferred_trigger_count);
+	int ret;
+
+	atomic_inc(&probe_count);
+	ret = __driver_probe_device(drv, dev);
+	if (ret == -EPROBE_DEFER || ret == EPROBE_DEFER) {
+		driver_deferred_probe_add(dev);
+
+		/*
+		 * Did a trigger occur while probing? Need to re-trigger if yes
+		 */
+		if (trigger_count != atomic_read(&deferred_trigger_count) &&
+		    !defer_all_probes)
+			driver_deferred_probe_trigger();
+	}
+	atomic_dec(&probe_count);
+	wake_up_all(&probe_waitqueue);
+	return ret;
+}
+
 static inline bool cmdline_requested_async_probing(const char *drv_name)
 {
-	return parse_option_str(async_probe_drv_names, drv_name);
+	bool async_drv;
+
+	async_drv = parse_option_str(async_probe_drv_names, drv_name);
+
+	return (async_probe_default != async_drv);
 }
 
 /* The option format is "driver_async_probe=drv_name1,drv_name2,..." */
 static int __init save_async_options(char *buf)
 {
 	if (strlen(buf) >= ASYNC_DRV_NAMES_MAX_LEN)
-		printk(KERN_WARNING
-			"Too long list of driver names for 'driver_async_probe'!\n");
+		pr_warn("Too long list of driver names for 'driver_async_probe'!\n");
 
-	strlcpy(async_probe_drv_names, buf, ASYNC_DRV_NAMES_MAX_LEN);
-	return 0;
+	strscpy(async_probe_drv_names, buf, ASYNC_DRV_NAMES_MAX_LEN);
+	async_probe_default = parse_option_str(async_probe_drv_names, "*");
+
+	return 1;
 }
 __setup("driver_async_probe=", save_async_options);
 
-bool driver_allows_async_probing(struct device_driver *drv)
+static bool driver_allows_async_probing(const struct device_driver *drv)
 {
 	switch (drv->probe_type) {
 	case PROBE_PREFER_ASYNCHRONOUS:
@@ -749,7 +890,7 @@ struct device_attach_data {
 	struct device *dev;
 
 	/*
-	 * Indicates whether we are are considering asynchronous probing or
+	 * Indicates whether we are considering asynchronous probing or
 	 * not. Only initial binding after device or driver registration
 	 * (including deferral processing) may be done asynchronously, the
 	 * rest is always synchronous, as we expect it is being done by
@@ -791,9 +932,15 @@ static int __device_attach_driver(struct device_driver *drv, void *_data)
 		return 0;
 	} else if (ret == -EPROBE_DEFER) {
 		dev_dbg(dev, "Device match requests probe deferral\n");
+		dev->can_match = true;
 		driver_deferred_probe_add(dev);
+		/*
+		 * Device can't match with a driver right now, so don't attempt
+		 * to match or bind with other drivers on the bus.
+		 */
+		return ret;
 	} else if (ret < 0) {
-		dev_dbg(dev, "Bus failed to match device: %d", ret);
+		dev_dbg(dev, "Bus failed to match device: %d\n", ret);
 		return ret;
 	} /* ret > 0 means positive match */
 
@@ -805,7 +952,14 @@ static int __device_attach_driver(struct device_driver *drv, void *_data)
 	if (data->check_async && async_allowed != data->want_async)
 		return 0;
 
-	return driver_probe_device(drv, dev);
+	/*
+	 * Ignore errors returned by ->probe so that the next driver can try
+	 * its luck.
+	 */
+	ret = driver_probe_device(drv, dev);
+	if (ret < 0)
+		return ret;
+	return ret == 0;
 }
 
 static void __device_attach_async_helper(void *_dev, async_cookie_t cookie)
@@ -847,9 +1001,12 @@ out_unlock:
 static int __device_attach(struct device *dev, bool allow_async)
 {
 	int ret = 0;
+	bool async = false;
 
 	device_lock(dev);
-	if (dev->driver) {
+	if (dev->p->dead) {
+		goto out_unlock;
+	} else if (dev->driver) {
 		if (device_is_bound(dev)) {
 			ret = 1;
 			goto out_unlock;
@@ -858,7 +1015,7 @@ static int __device_attach(struct device *dev, bool allow_async)
 		if (ret == 0)
 			ret = 1;
 		else {
-			dev->driver = NULL;
+			device_set_driver(dev, NULL);
 			ret = 0;
 		}
 	} else {
@@ -883,7 +1040,7 @@ static int __device_attach(struct device *dev, bool allow_async)
 			 */
 			dev_dbg(dev, "scheduling asynchronous probe\n");
 			get_device(dev);
-			async_schedule_dev(__device_attach_async_helper, dev);
+			async = true;
 		} else {
 			pm_request_idle(dev);
 		}
@@ -893,6 +1050,8 @@ static int __device_attach(struct device *dev, bool allow_async)
 	}
 out_unlock:
 	device_unlock(dev);
+	if (async)
+		async_schedule_dev(__device_attach_async_helper, dev);
 	return ret;
 }
 
@@ -918,7 +1077,15 @@ EXPORT_SYMBOL_GPL(device_attach);
 
 void device_initial_probe(struct device *dev)
 {
-	__device_attach(dev, true);
+	struct subsys_private *sp = bus_to_subsys(dev->bus);
+
+	if (!sp)
+		return;
+
+	if (sp->drivers_autoprobe)
+		__device_attach(dev, true);
+
+	subsys_put(sp);
 }
 
 /*
@@ -943,7 +1110,7 @@ static void __device_driver_lock(struct device *dev, struct device *parent)
  * @parent: Parent device. Needed if the bus requires parent lock
  *
  * This function will release the required locks for manipulating dev->drv.
- * Normally this will just be the the @dev lock, but when called for a
+ * Normally this will just be the @dev lock, but when called for a
  * USB interface, @parent lock will be released as well.
  */
 static void __device_driver_unlock(struct device *dev, struct device *parent)
@@ -959,43 +1126,35 @@ static void __device_driver_unlock(struct device *dev, struct device *parent)
  * @dev: Device to attach it to
  *
  * Manually attach driver to a device. Will acquire both @dev lock and
- * @dev->parent lock if needed.
+ * @dev->parent lock if needed. Returns 0 on success, -ERR on failure.
  */
-int device_driver_attach(struct device_driver *drv, struct device *dev)
+int device_driver_attach(const struct device_driver *drv, struct device *dev)
 {
-	int ret = 0;
+	int ret;
 
 	__device_driver_lock(dev, dev->parent);
-
-	/*
-	 * If device has been removed or someone has already successfully
-	 * bound a driver before us just skip the driver probe call.
-	 */
-	if (!dev->p->dead && !dev->driver)
-		ret = driver_probe_device(drv, dev);
-
+	ret = __driver_probe_device(drv, dev);
 	__device_driver_unlock(dev, dev->parent);
 
+	/* also return probe errors as normal negative errnos */
+	if (ret > 0)
+		ret = -ret;
+	if (ret == -EPROBE_DEFER)
+		return -EAGAIN;
 	return ret;
 }
+EXPORT_SYMBOL_GPL(device_driver_attach);
 
 static void __driver_attach_async_helper(void *_dev, async_cookie_t cookie)
 {
 	struct device *dev = _dev;
-	struct device_driver *drv;
-	int ret = 0;
+	const struct device_driver *drv;
+	int ret;
 
 	__device_driver_lock(dev, dev->parent);
-
 	drv = dev->p->async_driver;
-
-	/*
-	 * If device has been removed or someone has already successfully
-	 * bound a driver before us just skip the driver probe call.
-	 */
-	if (!dev->p->dead && !dev->driver)
-		ret = driver_probe_device(drv, dev);
-
+	dev->p->async_driver = NULL;
+	ret = driver_probe_device(drv, dev);
 	__device_driver_unlock(dev, dev->parent);
 
 	dev_dbg(dev, "driver %s async attach completed: %d\n", drv->name, ret);
@@ -1005,7 +1164,8 @@ static void __driver_attach_async_helper(void *_dev, async_cookie_t cookie)
 
 static int __driver_attach(struct device *dev, void *data)
 {
-	struct device_driver *drv = data;
+	const struct device_driver *drv = data;
+	bool async = false;
 	int ret;
 
 	/*
@@ -1024,10 +1184,20 @@ static int __driver_attach(struct device *dev, void *data)
 		return 0;
 	} else if (ret == -EPROBE_DEFER) {
 		dev_dbg(dev, "Device match requests probe deferral\n");
+		dev->can_match = true;
 		driver_deferred_probe_add(dev);
+		/*
+		 * Driver could not match with device, but may match with
+		 * another device on the bus.
+		 */
+		return 0;
 	} else if (ret < 0) {
-		dev_dbg(dev, "Bus failed to match device: %d", ret);
-		return ret;
+		dev_dbg(dev, "Bus failed to match device: %d\n", ret);
+		/*
+		 * Driver could not match with device, but may match with
+		 * another device on the bus.
+		 */
+		return 0;
 	} /* ret > 0 means positive match */
 
 	if (driver_allows_async_probing(drv)) {
@@ -1040,16 +1210,20 @@ static int __driver_attach(struct device *dev, void *data)
 		 */
 		dev_dbg(dev, "probing driver %s asynchronously\n", drv->name);
 		device_lock(dev);
-		if (!dev->driver) {
+		if (!dev->driver && !dev->p->async_driver) {
 			get_device(dev);
 			dev->p->async_driver = drv;
-			async_schedule_dev(__driver_attach_async_helper, dev);
+			async = true;
 		}
 		device_unlock(dev);
+		if (async)
+			async_schedule_dev(__driver_attach_async_helper, dev);
 		return 0;
 	}
 
-	device_driver_attach(drv, dev);
+	__device_driver_lock(dev, dev->parent);
+	driver_probe_device(drv, dev);
+	__device_driver_unlock(dev, dev->parent);
 
 	return 0;
 }
@@ -1063,9 +1237,10 @@ static int __driver_attach(struct device *dev, void *data)
  * returns 0 and the @dev->driver is set, we've found a
  * compatible pair.
  */
-int driver_attach(struct device_driver *drv)
+int driver_attach(const struct device_driver *drv)
 {
-	return bus_for_each_dev(drv->bus, NULL, drv, __driver_attach);
+	/* The (void *) will be put back to const * in __driver_attach() */
+	return bus_for_each_dev(drv->bus, NULL, (void *)drv, __driver_attach);
 }
 EXPORT_SYMBOL_GPL(driver_attach);
 
@@ -1079,6 +1254,8 @@ static void __device_release_driver(struct device *dev, struct device *parent)
 
 	drv = dev->driver;
 	if (drv) {
+		pm_runtime_get_sync(dev);
+
 		while (device_links_busy(dev)) {
 			__device_driver_unlock(dev, parent);
 
@@ -1090,53 +1267,36 @@ static void __device_release_driver(struct device *dev, struct device *parent)
 			 * have released the driver successfully while this one
 			 * was waiting, so check for that.
 			 */
-			if (dev->driver != drv)
+			if (dev->driver != drv) {
+				pm_runtime_put(dev);
 				return;
+			}
 		}
 
-		pm_runtime_get_sync(dev);
-		pm_runtime_clean_up_links(dev);
-
 		driver_sysfs_remove(dev);
 
-		if (dev->bus)
-			blocking_notifier_call_chain(&dev->bus->p->bus_notifier,
-						     BUS_NOTIFY_UNBIND_DRIVER,
-						     dev);
+		bus_notify(dev, BUS_NOTIFY_UNBIND_DRIVER);
 
 		pm_runtime_put_sync(dev);
 
-		device_remove_groups(dev, drv->dev_groups);
+		device_remove(dev);
 
-		if (dev->bus && dev->bus->remove)
-			dev->bus->remove(dev);
-		else if (drv->remove)
-			drv->remove(dev);
+		if (dev->bus && dev->bus->dma_cleanup)
+			dev->bus->dma_cleanup(dev);
 
+		device_unbind_cleanup(dev);
 		device_links_driver_cleanup(dev);
 
-		devres_release_all(dev);
-		arch_teardown_dma_ops(dev);
-		dev->driver = NULL;
-		dev_set_drvdata(dev, NULL);
-		if (dev->pm_domain && dev->pm_domain->dismiss)
-			dev->pm_domain->dismiss(dev);
-		pm_runtime_reinit(dev);
-		dev_pm_set_driver_flags(dev, 0);
-
 		klist_remove(&dev->p->knode_driver);
 		device_pm_check_callbacks(dev);
-		if (dev->bus)
-			blocking_notifier_call_chain(&dev->bus->p->bus_notifier,
-						     BUS_NOTIFY_UNBOUND_DRIVER,
-						     dev);
 
+		bus_notify(dev, BUS_NOTIFY_UNBOUND_DRIVER);
 		kobject_uevent(&dev->kobj, KOBJ_UNBIND);
 	}
 }
 
 void device_release_driver_internal(struct device *dev,
-				    struct device_driver *drv,
+				    const struct device_driver *drv,
 				    struct device *parent)
 {
 	__device_driver_lock(dev, parent);
@@ -1185,7 +1345,7 @@ void device_driver_detach(struct device *dev)
  * driver_detach - detach driver from all devices it controls.
  * @drv: driver.
  */
-void driver_detach(struct device_driver *drv)
+void driver_detach(const struct device_driver *drv)
 {
 	struct device_private *dev_prv;
 	struct device *dev;
diff --git a/drivers/base/devcon.c b/drivers/base/devcon.c
deleted file mode 100644
index 14e2178e09f8..000000000000
--- a/drivers/base/devcon.c
+++ /dev/null
@@ -1,231 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/**
- * Device connections
- *
- * Copyright (C) 2018 Intel Corporation
- * Author: Heikki Krogerus <heikki.krogerus@linux.intel.com>
- */
-
-#include <linux/device.h>
-#include <linux/property.h>
-
-static DEFINE_MUTEX(devcon_lock);
-static LIST_HEAD(devcon_list);
-
-static void *
-fwnode_graph_devcon_match(struct fwnode_handle *fwnode, const char *con_id,
-			  void *data, devcon_match_fn_t match)
-{
-	struct device_connection con = { .id = con_id };
-	struct fwnode_handle *ep;
-	void *ret;
-
-	fwnode_graph_for_each_endpoint(fwnode, ep) {
-		con.fwnode = fwnode_graph_get_remote_port_parent(ep);
-		if (!fwnode_device_is_available(con.fwnode))
-			continue;
-
-		ret = match(&con, -1, data);
-		fwnode_handle_put(con.fwnode);
-		if (ret) {
-			fwnode_handle_put(ep);
-			return ret;
-		}
-	}
-	return NULL;
-}
-
-static void *
-fwnode_devcon_match(struct fwnode_handle *fwnode, const char *con_id,
-		    void *data, devcon_match_fn_t match)
-{
-	struct device_connection con = { };
-	void *ret;
-	int i;
-
-	for (i = 0; ; i++) {
-		con.fwnode = fwnode_find_reference(fwnode, con_id, i);
-		if (IS_ERR(con.fwnode))
-			break;
-
-		ret = match(&con, -1, data);
-		fwnode_handle_put(con.fwnode);
-		if (ret)
-			return ret;
-	}
-
-	return NULL;
-}
-
-/**
- * fwnode_connection_find_match - Find connection from a device node
- * @fwnode: Device node with the connection
- * @con_id: Identifier for the connection
- * @data: Data for the match function
- * @match: Function to check and convert the connection description
- *
- * Find a connection with unique identifier @con_id between @fwnode and another
- * device node. @match will be used to convert the connection description to
- * data the caller is expecting to be returned.
- */
-void *fwnode_connection_find_match(struct fwnode_handle *fwnode,
-				   const char *con_id, void *data,
-				   devcon_match_fn_t match)
-{
-	void *ret;
-
-	if (!fwnode || !match)
-		return NULL;
-
-	ret = fwnode_graph_devcon_match(fwnode, con_id, data, match);
-	if (ret)
-		return ret;
-
-	return fwnode_devcon_match(fwnode, con_id, data, match);
-}
-EXPORT_SYMBOL_GPL(fwnode_connection_find_match);
-
-/**
- * device_connection_find_match - Find physical connection to a device
- * @dev: Device with the connection
- * @con_id: Identifier for the connection
- * @data: Data for the match function
- * @match: Function to check and convert the connection description
- *
- * Find a connection with unique identifier @con_id between @dev and another
- * device. @match will be used to convert the connection description to data the
- * caller is expecting to be returned.
- */
-void *device_connection_find_match(struct device *dev, const char *con_id,
-				   void *data, devcon_match_fn_t match)
-{
-	struct fwnode_handle *fwnode = dev_fwnode(dev);
-	const char *devname = dev_name(dev);
-	struct device_connection *con;
-	void *ret = NULL;
-	int ep;
-
-	if (!match)
-		return NULL;
-
-	ret = fwnode_connection_find_match(fwnode, con_id, data, match);
-	if (ret)
-		return ret;
-
-	mutex_lock(&devcon_lock);
-
-	list_for_each_entry(con, &devcon_list, list) {
-		ep = match_string(con->endpoint, 2, devname);
-		if (ep < 0)
-			continue;
-
-		if (con_id && strcmp(con->id, con_id))
-			continue;
-
-		ret = match(con, !ep, data);
-		if (ret)
-			break;
-	}
-
-	mutex_unlock(&devcon_lock);
-
-	return ret;
-}
-EXPORT_SYMBOL_GPL(device_connection_find_match);
-
-extern struct bus_type platform_bus_type;
-extern struct bus_type pci_bus_type;
-extern struct bus_type i2c_bus_type;
-extern struct bus_type spi_bus_type;
-
-static struct bus_type *generic_match_buses[] = {
-	&platform_bus_type,
-#ifdef CONFIG_PCI
-	&pci_bus_type,
-#endif
-#ifdef CONFIG_I2C
-	&i2c_bus_type,
-#endif
-#ifdef CONFIG_SPI_MASTER
-	&spi_bus_type,
-#endif
-	NULL,
-};
-
-static void *device_connection_fwnode_match(struct device_connection *con)
-{
-	struct bus_type *bus;
-	struct device *dev;
-
-	for (bus = generic_match_buses[0]; bus; bus++) {
-		dev = bus_find_device_by_fwnode(bus, con->fwnode);
-		if (dev && !strncmp(dev_name(dev), con->id, strlen(con->id)))
-			return dev;
-
-		put_device(dev);
-	}
-	return NULL;
-}
-
-/* This tries to find the device from the most common bus types by name. */
-static void *generic_match(struct device_connection *con, int ep, void *data)
-{
-	struct bus_type *bus;
-	struct device *dev;
-
-	if (con->fwnode)
-		return device_connection_fwnode_match(con);
-
-	for (bus = generic_match_buses[0]; bus; bus++) {
-		dev = bus_find_device_by_name(bus, NULL, con->endpoint[ep]);
-		if (dev)
-			return dev;
-	}
-
-	/*
-	 * We only get called if a connection was found, tell the caller to
-	 * wait for the other device to show up.
-	 */
-	return ERR_PTR(-EPROBE_DEFER);
-}
-
-/**
- * device_connection_find - Find two devices connected together
- * @dev: Device with the connection
- * @con_id: Identifier for the connection
- *
- * Find a connection with unique identifier @con_id between @dev and
- * another device. On success returns handle to the device that is connected
- * to @dev, with the reference count for the found device incremented. Returns
- * NULL if no matching connection was found, or ERR_PTR(-EPROBE_DEFER) when a
- * connection was found but the other device has not been enumerated yet.
- */
-struct device *device_connection_find(struct device *dev, const char *con_id)
-{
-	return device_connection_find_match(dev, con_id, NULL, generic_match);
-}
-EXPORT_SYMBOL_GPL(device_connection_find);
-
-/**
- * device_connection_add - Register a connection description
- * @con: The connection description to be registered
- */
-void device_connection_add(struct device_connection *con)
-{
-	mutex_lock(&devcon_lock);
-	list_add_tail(&con->list, &devcon_list);
-	mutex_unlock(&devcon_lock);
-}
-EXPORT_SYMBOL_GPL(device_connection_add);
-
-/**
- * device_connections_remove - Unregister connection description
- * @con: The connection description to be unregistered
- */
-void device_connection_remove(struct device_connection *con)
-{
-	mutex_lock(&devcon_lock);
-	list_del(&con->list);
-	mutex_unlock(&devcon_lock);
-}
-EXPORT_SYMBOL_GPL(device_connection_remove);
diff --git a/drivers/base/devcoredump.c b/drivers/base/devcoredump.c
index e42d0b514384..55bdc7f5e59d 100644
--- a/drivers/base/devcoredump.c
+++ b/drivers/base/devcoredump.c
@@ -3,10 +3,6 @@
  * Copyright(c) 2014 Intel Mobile Communications GmbH
  * Copyright(c) 2015 Intel Deutschland GmbH
  *
- * Contact Information:
- *  Intel Linux Wireless <ilw@linux.intel.com>
- * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
- *
  * Author: Johannes Berg <johannes@sipsolutions.net>
  */
 #include <linux/module.h>
@@ -22,17 +18,51 @@ static struct class devcd_class;
 /* global disable flag, for security purposes */
 static bool devcd_disabled;
 
-/* if data isn't read by userspace after 5 minutes then delete it */
-#define DEVCD_TIMEOUT	(HZ * 60 * 5)
-
 struct devcd_entry {
 	struct device devcd_dev;
 	void *data;
 	size_t datalen;
+	/*
+	 * There are 2 races for which mutex is required.
+	 *
+	 * The first race is between device creation and userspace writing to
+	 * schedule immediately destruction.
+	 *
+	 * This race is handled by arming the timer before device creation, but
+	 * when device creation fails the timer still exists.
+	 *
+	 * To solve this, hold the mutex during device_add(), and set
+	 * init_completed on success before releasing the mutex.
+	 *
+	 * That way the timer will never fire until device_add() is called,
+	 * it will do nothing if init_completed is not set. The timer is also
+	 * cancelled in that case.
+	 *
+	 * The second race involves multiple parallel invocations of devcd_free(),
+	 * add a deleted flag so only 1 can call the destructor.
+	 */
+	struct mutex mutex;
+	bool init_completed, deleted;
 	struct module *owner;
 	ssize_t (*read)(char *buffer, loff_t offset, size_t count,
 			void *data, size_t datalen);
 	void (*free)(void *data);
+	/*
+	 * If nothing interferes and device_add() was returns success,
+	 * del_wk will destroy the device after the timer fires.
+	 *
+	 * Multiple userspace processes can interfere in the working of the timer:
+	 * - Writing to the coredump will reschedule the timer to run immediately,
+	 *   if still armed.
+	 *
+	 *   This is handled by using "if (cancel_delayed_work()) {
+	 *   schedule_delayed_work() }", to prevent re-arming after having
+	 *   been previously fired.
+	 * - Writing to /sys/class/devcoredump/disabled will destroy the
+	 *   coredump synchronously.
+	 *   This is handled by using disable_delayed_work_sync(), and then
+	 *   checking if deleted flag is set with &devcd->mutex held.
+	 */
 	struct delayed_work del_wk;
 	struct device *failing_dev;
 };
@@ -61,18 +91,31 @@ static void devcd_dev_release(struct device *dev)
 	kfree(devcd);
 }
 
+static void __devcd_del(struct devcd_entry *devcd)
+{
+	devcd->deleted = true;
+	device_del(&devcd->devcd_dev);
+	put_device(&devcd->devcd_dev);
+}
+
 static void devcd_del(struct work_struct *wk)
 {
 	struct devcd_entry *devcd;
+	bool init_completed;
 
 	devcd = container_of(wk, struct devcd_entry, del_wk.work);
 
-	device_del(&devcd->devcd_dev);
-	put_device(&devcd->devcd_dev);
+	/* devcd->mutex serializes against dev_coredumpm_timeout */
+	mutex_lock(&devcd->mutex);
+	init_completed = devcd->init_completed;
+	mutex_unlock(&devcd->mutex);
+
+	if (init_completed)
+		__devcd_del(devcd);
 }
 
 static ssize_t devcd_data_read(struct file *filp, struct kobject *kobj,
-			       struct bin_attribute *bin_attr,
+			       const struct bin_attribute *bin_attr,
 			       char *buffer, loff_t offset, size_t count)
 {
 	struct device *dev = kobj_to_dev(kobj);
@@ -82,25 +125,26 @@ static ssize_t devcd_data_read(struct file *filp, struct kobject *kobj,
 }
 
 static ssize_t devcd_data_write(struct file *filp, struct kobject *kobj,
-				struct bin_attribute *bin_attr,
+				const struct bin_attribute *bin_attr,
 				char *buffer, loff_t offset, size_t count)
 {
 	struct device *dev = kobj_to_dev(kobj);
 	struct devcd_entry *devcd = dev_to_devcd(dev);
 
-	mod_delayed_work(system_wq, &devcd->del_wk, 0);
+	/*
+	 * Although it's tempting to use mod_delayed work here,
+	 * that will cause a reschedule if the timer already fired.
+	 */
+	if (cancel_delayed_work(&devcd->del_wk))
+		schedule_delayed_work(&devcd->del_wk, 0);
 
 	return count;
 }
 
-static struct bin_attribute devcd_attr_data = {
-	.attr = { .name = "data", .mode = S_IRUSR | S_IWUSR, },
-	.size = 0,
-	.read = devcd_data_read,
-	.write = devcd_data_write,
-};
+static const struct bin_attribute devcd_attr_data =
+	__BIN_ATTR(data, 0600, devcd_data_read, devcd_data_write, 0);
 
-static struct bin_attribute *devcd_dev_bin_attrs[] = {
+static const struct bin_attribute *const devcd_dev_bin_attrs[] = {
 	&devcd_attr_data, NULL,
 };
 
@@ -116,17 +160,54 @@ static int devcd_free(struct device *dev, void *data)
 {
 	struct devcd_entry *devcd = dev_to_devcd(dev);
 
-	flush_delayed_work(&devcd->del_wk);
+	/*
+	 * To prevent a race with devcd_data_write(), disable work and
+	 * complete manually instead.
+	 *
+	 * We cannot rely on the return value of
+	 * disable_delayed_work_sync() here, because it might be in the
+	 * middle of a cancel_delayed_work + schedule_delayed_work pair.
+	 *
+	 * devcd->mutex here guards against multiple parallel invocations
+	 * of devcd_free().
+	 */
+	disable_delayed_work_sync(&devcd->del_wk);
+	mutex_lock(&devcd->mutex);
+	if (!devcd->deleted)
+		__devcd_del(devcd);
+	mutex_unlock(&devcd->mutex);
 	return 0;
 }
 
-static ssize_t disabled_show(struct class *class, struct class_attribute *attr,
+static ssize_t disabled_show(const struct class *class, const struct class_attribute *attr,
 			     char *buf)
 {
-	return sprintf(buf, "%d\n", devcd_disabled);
+	return sysfs_emit(buf, "%d\n", devcd_disabled);
 }
 
-static ssize_t disabled_store(struct class *class, struct class_attribute *attr,
+/*
+ *
+ *	disabled_store()                                	worker()
+ *	 class_for_each_device(&devcd_class,
+ *		NULL, NULL, devcd_free)
+ *         ...
+ *         ...
+ *	   while ((dev = class_dev_iter_next(&iter))
+ *                                                             devcd_del()
+ *                                                               device_del()
+ *                                                                 put_device() <- last reference
+ *             error = fn(dev, data)                           devcd_dev_release()
+ *             devcd_free(dev, data)                           kfree(devcd)
+ *
+ *
+ * In the above diagram, it looks like disabled_store() would be racing with parallelly
+ * running devcd_del() and result in memory abort after dropping its last reference with
+ * put_device(). However, this will not happens as fn(dev, data) runs
+ * with its own reference to device via klist_node so it is not its last reference.
+ * so, above situation would not occur.
+ */
+
+static ssize_t disabled_store(const struct class *class, const struct class_attribute *attr,
 			      const char *buf, size_t count)
 {
 	long tmp = simple_strtol(buf, NULL, 10);
@@ -155,7 +236,6 @@ ATTRIBUTE_GROUPS(devcd_class);
 
 static struct class devcd_class = {
 	.name		= "devcoredump",
-	.owner		= THIS_MODULE,
 	.dev_release	= devcd_dev_release,
 	.dev_groups	= devcd_dev_groups,
 	.class_groups	= devcd_class_groups,
@@ -202,7 +282,7 @@ static int devcd_match_failing(struct device *dev, const void *failing)
  * NOTE: if two tables allocated with devcd_alloc_sgtable and then chained
  * using the sg_chain function then that function should be called only once
  * on the chained table
- * @table: pointer to sg_table to free
+ * @data: pointer to sg_table to free
  */
 static void devcd_free_sgtable(void *data)
 {
@@ -210,7 +290,7 @@ static void devcd_free_sgtable(void *data)
 }
 
 /**
- * devcd_read_from_table - copy data from sg_table to a given buffer
+ * devcd_read_from_sgtable - copy data from sg_table to a given buffer
  * and return the number of bytes read
  * @buffer: the buffer to copy the data to it
  * @buf_len: the length of the buffer
@@ -218,6 +298,8 @@ static void devcd_free_sgtable(void *data)
  * @offset: start copy from @offset@ bytes from the head of the data
  *	in the given scatterlist
  * @data_len: the length of the data in the sg_table
+ *
+ * Returns: the number of bytes copied
  */
 static ssize_t devcd_read_from_sgtable(char *buffer, loff_t offset,
 				       size_t buf_len, void *data,
@@ -235,7 +317,31 @@ static ssize_t devcd_read_from_sgtable(char *buffer, loff_t offset,
 }
 
 /**
- * dev_coredumpm - create device coredump with read/free methods
+ * dev_coredump_put - remove device coredump
+ * @dev: the struct device for the crashed device
+ *
+ * dev_coredump_put() removes coredump, if exists, for a given device from
+ * the file system and free its associated data otherwise, does nothing.
+ *
+ * It is useful for modules that do not want to keep coredump
+ * available after its unload.
+ */
+void dev_coredump_put(struct device *dev)
+{
+	struct device *existing;
+
+	existing = class_find_device(&devcd_class, NULL, dev,
+				     devcd_match_failing);
+	if (existing) {
+		devcd_free(existing, NULL);
+		put_device(existing);
+	}
+}
+EXPORT_SYMBOL_GPL(dev_coredump_put);
+
+/**
+ * dev_coredumpm_timeout - create device coredump with read/free methods with a
+ * custom timeout.
  * @dev: the struct device for the crashed device
  * @owner: the module that contains the read/free functions, use %THIS_MODULE
  * @data: data cookie for the @read/@free functions
@@ -243,17 +349,20 @@ static ssize_t devcd_read_from_sgtable(char *buffer, loff_t offset,
  * @gfp: allocation flags
  * @read: function to read from the given buffer
  * @free: function to free the given buffer
+ * @timeout: time in jiffies to remove coredump
  *
  * Creates a new device coredump for the given device. If a previous one hasn't
  * been read yet, the new coredump is discarded. The data lifetime is determined
  * by the device coredump framework and when it is no longer needed the @free
  * function will be called to free the data.
  */
-void dev_coredumpm(struct device *dev, struct module *owner,
-		   void *data, size_t datalen, gfp_t gfp,
-		   ssize_t (*read)(char *buffer, loff_t offset, size_t count,
-				   void *data, size_t datalen),
-		   void (*free)(void *data))
+void dev_coredumpm_timeout(struct device *dev, struct module *owner,
+			   void *data, size_t datalen, gfp_t gfp,
+			   ssize_t (*read)(char *buffer, loff_t offset,
+					   size_t count, void *data,
+					   size_t datalen),
+			   void (*free)(void *data),
+			   unsigned long timeout)
 {
 	static atomic_t devcd_count = ATOMIC_INIT(0);
 	struct devcd_entry *devcd;
@@ -282,36 +391,59 @@ void dev_coredumpm(struct device *dev, struct module *owner,
 	devcd->read = read;
 	devcd->free = free;
 	devcd->failing_dev = get_device(dev);
+	devcd->deleted = false;
 
+	mutex_init(&devcd->mutex);
 	device_initialize(&devcd->devcd_dev);
 
 	dev_set_name(&devcd->devcd_dev, "devcd%d",
 		     atomic_inc_return(&devcd_count));
 	devcd->devcd_dev.class = &devcd_class;
 
+	dev_set_uevent_suppress(&devcd->devcd_dev, true);
+
+	/* devcd->mutex prevents devcd_del() completing until init finishes */
+	mutex_lock(&devcd->mutex);
+	devcd->init_completed = false;
+	INIT_DELAYED_WORK(&devcd->del_wk, devcd_del);
+	schedule_delayed_work(&devcd->del_wk, timeout);
+
 	if (device_add(&devcd->devcd_dev))
 		goto put_device;
 
+	/*
+	 * These should normally not fail, but there is no problem
+	 * continuing without the links, so just warn instead of
+	 * failing.
+	 */
 	if (sysfs_create_link(&devcd->devcd_dev.kobj, &dev->kobj,
-			      "failing_device"))
-		/* nothing - symlink will be missing */;
-
-	if (sysfs_create_link(&dev->kobj, &devcd->devcd_dev.kobj,
-			      "devcoredump"))
-		/* nothing - symlink will be missing */;
+			      "failing_device") ||
+	    sysfs_create_link(&dev->kobj, &devcd->devcd_dev.kobj,
+		              "devcoredump"))
+		dev_warn(dev, "devcoredump create_link failed\n");
 
-	INIT_DELAYED_WORK(&devcd->del_wk, devcd_del);
-	schedule_delayed_work(&devcd->del_wk, DEVCD_TIMEOUT);
+	dev_set_uevent_suppress(&devcd->devcd_dev, false);
+	kobject_uevent(&devcd->devcd_dev.kobj, KOBJ_ADD);
 
+	/*
+	 * Safe to run devcd_del() now that we are done with devcd_dev.
+	 * Alternatively we could have taken a ref on devcd_dev before
+	 * dropping the lock.
+	 */
+	devcd->init_completed = true;
+	mutex_unlock(&devcd->mutex);
 	return;
  put_device:
+	mutex_unlock(&devcd->mutex);
+	cancel_delayed_work_sync(&devcd->del_wk);
 	put_device(&devcd->devcd_dev);
+
  put_module:
 	module_put(owner);
  free:
 	free(data);
 }
-EXPORT_SYMBOL_GPL(dev_coredumpm);
+EXPORT_SYMBOL_GPL(dev_coredumpm_timeout);
 
 /**
  * dev_coredumpsg - create device coredump that uses scatterlist as data
diff --git a/drivers/base/devres.c b/drivers/base/devres.c
index 0bbb328bd17f..f54db6d138ab 100644
--- a/drivers/base/devres.c
+++ b/drivers/base/devres.c
@@ -14,14 +14,13 @@
 #include <asm/sections.h>
 
 #include "base.h"
+#include "trace.h"
 
 struct devres_node {
 	struct list_head		entry;
 	dr_release_t			release;
-#ifdef CONFIG_DEBUG_DEVRES
 	const char			*name;
 	size_t				size;
-#endif
 };
 
 struct devres {
@@ -30,10 +29,10 @@ struct devres {
 	 * Some archs want to perform DMA into kmalloc caches
 	 * and need a guaranteed alignment larger than
 	 * the alignment of a 64-bit integer.
-	 * Thus we use ARCH_KMALLOC_MINALIGN here and get exactly the same
-	 * buffer alignment as if it was allocated by plain kmalloc().
+	 * Thus we use ARCH_DMA_MINALIGN for data[] which will force the same
+	 * alignment for struct devres when allocated by kmalloc().
 	 */
-	u8 __aligned(ARCH_KMALLOC_MINALIGN) data[];
+	u8 __aligned(ARCH_DMA_MINALIGN) data[];
 };
 
 struct devres_group {
@@ -43,10 +42,6 @@ struct devres_group {
 	/* -- 8 pointers */
 };
 
-#ifdef CONFIG_DEBUG_DEVRES
-static int log_devres = 0;
-module_param_named(log, log_devres, int, S_IRUGO | S_IWUSR);
-
 static void set_node_dbginfo(struct devres_node *node, const char *name,
 			     size_t size)
 {
@@ -54,18 +49,28 @@ static void set_node_dbginfo(struct devres_node *node, const char *name,
 	node->size = size;
 }
 
-static void devres_log(struct device *dev, struct devres_node *node,
+#ifdef CONFIG_DEBUG_DEVRES
+static int log_devres = 0;
+module_param_named(log, log_devres, int, S_IRUGO | S_IWUSR);
+
+static void devres_dbg(struct device *dev, struct devres_node *node,
 		       const char *op)
 {
 	if (unlikely(log_devres))
-		dev_err(dev, "DEVRES %3s %p %s (%lu bytes)\n",
-			op, node, node->name, (unsigned long)node->size);
+		dev_err(dev, "DEVRES %3s %p %s (%zu bytes)\n",
+			op, node, node->name, node->size);
 }
 #else /* CONFIG_DEBUG_DEVRES */
-#define set_node_dbginfo(node, n, s)	do {} while (0)
-#define devres_log(dev, node, op)	do {} while (0)
+#define devres_dbg(dev, node, op)	do {} while (0)
 #endif /* CONFIG_DEBUG_DEVRES */
 
+static void devres_log(struct device *dev, struct devres_node *node,
+		       const char *op)
+{
+	trace_devres_log(dev, op, node, node->name, node->size);
+	devres_dbg(dev, node, op);
+}
+
 /*
  * Release functions for devres group.  These callbacks are used only
  * for identification.
@@ -80,7 +85,7 @@ static void group_close_release(struct device *dev, void *res)
 	/* noop */
 }
 
-static struct devres_group * node_to_group(struct devres_node *node)
+static struct devres_group *node_to_group(struct devres_node *node)
 {
 	if (node->release == &group_open_release)
 		return container_of(node, struct devres_group, node[0]);
@@ -89,22 +94,35 @@ static struct devres_group * node_to_group(struct devres_node *node)
 	return NULL;
 }
 
-static __always_inline struct devres * alloc_dr(dr_release_t release,
-						size_t size, gfp_t gfp, int nid)
+static bool check_dr_size(size_t size, size_t *tot_size)
+{
+	/* We must catch any near-SIZE_MAX cases that could overflow. */
+	if (unlikely(check_add_overflow(sizeof(struct devres),
+					size, tot_size)))
+		return false;
+
+	/* Actually allocate the full kmalloc bucket size. */
+	*tot_size = kmalloc_size_roundup(*tot_size);
+
+	return true;
+}
+
+static __always_inline struct devres *alloc_dr(dr_release_t release,
+					       size_t size, gfp_t gfp, int nid)
 {
 	size_t tot_size;
 	struct devres *dr;
 
-	/* We must catch any near-SIZE_MAX cases that could overflow. */
-	if (unlikely(check_add_overflow(sizeof(struct devres), size,
-					&tot_size)))
+	if (!check_dr_size(size, &tot_size))
 		return NULL;
 
 	dr = kmalloc_node_track_caller(tot_size, gfp, nid);
 	if (unlikely(!dr))
 		return NULL;
 
-	memset(dr, 0, offsetof(struct devres, data));
+	/* No need to clear memory twice */
+	if (!(gfp & __GFP_ZERO))
+		memset(dr, 0, offsetof(struct devres, data));
 
 	INIT_LIST_HEAD(&dr->node.entry);
 	dr->node.release = release;
@@ -118,26 +136,21 @@ static void add_dr(struct device *dev, struct devres_node *node)
 	list_add_tail(&node->entry, &dev->devres_head);
 }
 
-#ifdef CONFIG_DEBUG_DEVRES
-void * __devres_alloc_node(dr_release_t release, size_t size, gfp_t gfp, int nid,
-		      const char *name)
+static void replace_dr(struct device *dev,
+		       struct devres_node *old, struct devres_node *new)
 {
-	struct devres *dr;
-
-	dr = alloc_dr(release, size, gfp | __GFP_ZERO, nid);
-	if (unlikely(!dr))
-		return NULL;
-	set_node_dbginfo(&dr->node, name, size);
-	return dr->data;
+	devres_log(dev, old, "REPLACE");
+	BUG_ON(!list_empty(&new->entry));
+	list_replace(&old->entry, &new->entry);
 }
-EXPORT_SYMBOL_GPL(__devres_alloc_node);
-#else
+
 /**
- * devres_alloc - Allocate device resource data
+ * __devres_alloc_node - Allocate device resource data
  * @release: Release function devres will be associated with
  * @size: Allocation size
  * @gfp: Allocation flags
  * @nid: NUMA node
+ * @name: Name of the resource
  *
  * Allocate devres of @size bytes.  The allocated area is zeroed, then
  * associated with @release.  The returned pointer can be passed to
@@ -146,17 +159,18 @@ EXPORT_SYMBOL_GPL(__devres_alloc_node);
  * RETURNS:
  * Pointer to allocated devres on success, NULL on failure.
  */
-void * devres_alloc_node(dr_release_t release, size_t size, gfp_t gfp, int nid)
+void *__devres_alloc_node(dr_release_t release, size_t size, gfp_t gfp, int nid,
+			  const char *name)
 {
 	struct devres *dr;
 
 	dr = alloc_dr(release, size, gfp | __GFP_ZERO, nid);
 	if (unlikely(!dr))
 		return NULL;
+	set_node_dbginfo(&dr->node, name, size);
 	return dr->data;
 }
-EXPORT_SYMBOL_GPL(devres_alloc_node);
-#endif
+EXPORT_SYMBOL_GPL(__devres_alloc_node);
 
 /**
  * devres_for_each_res - Resource iterator
@@ -269,8 +283,8 @@ static struct devres *find_dr(struct device *dev, dr_release_t release,
  * RETURNS:
  * Pointer to found devres, NULL if not found.
  */
-void * devres_find(struct device *dev, dr_release_t release,
-		   dr_match_t match, void *match_data)
+void *devres_find(struct device *dev, dr_release_t release,
+		  dr_match_t match, void *match_data)
 {
 	struct devres *dr;
 	unsigned long flags;
@@ -299,8 +313,8 @@ EXPORT_SYMBOL_GPL(devres_find);
  * RETURNS:
  * Pointer to found or added devres.
  */
-void * devres_get(struct device *dev, void *new_res,
-		  dr_match_t match, void *match_data)
+void *devres_get(struct device *dev, void *new_res,
+		 dr_match_t match, void *match_data)
 {
 	struct devres *new_dr = container_of(new_res, struct devres, data);
 	struct devres *dr;
@@ -335,8 +349,8 @@ EXPORT_SYMBOL_GPL(devres_get);
  * RETURNS:
  * Pointer to removed devres on success, NULL if not found.
  */
-void * devres_remove(struct device *dev, dr_release_t release,
-		     dr_match_t match, void *match_data)
+void *devres_remove(struct device *dev, dr_release_t release,
+		    dr_match_t match, void *match_data)
 {
 	struct devres *dr;
 	unsigned long flags;
@@ -422,20 +436,16 @@ static int remove_nodes(struct device *dev,
 			struct list_head *first, struct list_head *end,
 			struct list_head *todo)
 {
+	struct devres_node *node, *n;
 	int cnt = 0, nr_groups = 0;
-	struct list_head *cur;
 
 	/* First pass - move normal devres entries to @todo and clear
 	 * devres_group colors.
 	 */
-	cur = first;
-	while (cur != end) {
-		struct devres_node *node;
+	node = list_entry(first, struct devres_node, entry);
+	list_for_each_entry_safe_from(node, n, end, entry) {
 		struct devres_group *grp;
 
-		node = list_entry(cur, struct devres_node, entry);
-		cur = cur->next;
-
 		grp = node_to_group(node);
 		if (grp) {
 			/* clear color of group markers in the first pass */
@@ -455,18 +465,14 @@ static int remove_nodes(struct device *dev,
 
 	/* Second pass - Scan groups and color them.  A group gets
 	 * color value of two iff the group is wholly contained in
-	 * [cur, end).  That is, for a closed group, both opening and
-	 * closing markers should be in the range, while just the
+	 * [current node, end). That is, for a closed group, both opening
+	 * and closing markers should be in the range, while just the
 	 * opening marker is enough for an open group.
 	 */
-	cur = first;
-	while (cur != end) {
-		struct devres_node *node;
+	node = list_entry(first, struct devres_node, entry);
+	list_for_each_entry_safe_from(node, n, end, entry) {
 		struct devres_group *grp;
 
-		node = list_entry(cur, struct devres_node, entry);
-		cur = cur->next;
-
 		grp = node_to_group(node);
 		BUG_ON(!grp || list_empty(&grp->node[0].entry));
 
@@ -476,7 +482,7 @@ static int remove_nodes(struct device *dev,
 
 		BUG_ON(grp->color <= 0 || grp->color > 2);
 		if (grp->color == 2) {
-			/* No need to update cur or end.  The removed
+			/* No need to update current node or end. The removed
 			 * nodes are always before both.
 			 */
 			list_move_tail(&grp->node[0].entry, todo);
@@ -487,28 +493,18 @@ static int remove_nodes(struct device *dev,
 	return cnt;
 }
 
-static int release_nodes(struct device *dev, struct list_head *first,
-			 struct list_head *end, unsigned long flags)
-	__releases(&dev->devres_lock)
+static void release_nodes(struct device *dev, struct list_head *todo)
 {
-	LIST_HEAD(todo);
-	int cnt;
 	struct devres *dr, *tmp;
 
-	cnt = remove_nodes(dev, first, end, &todo);
-
-	spin_unlock_irqrestore(&dev->devres_lock, flags);
-
 	/* Release.  Note that both devres and devres_group are
 	 * handled as devres in the following loop.  This is safe.
 	 */
-	list_for_each_entry_safe_reverse(dr, tmp, &todo, node.entry) {
+	list_for_each_entry_safe_reverse(dr, tmp, todo, node.entry) {
 		devres_log(dev, &dr->node, "REL");
 		dr->node.release(dev, dr->data);
 		kfree(dr);
 	}
-
-	return cnt;
 }
 
 /**
@@ -521,13 +517,23 @@ static int release_nodes(struct device *dev, struct list_head *first,
 int devres_release_all(struct device *dev)
 {
 	unsigned long flags;
+	LIST_HEAD(todo);
+	int cnt;
 
 	/* Looks like an uninitialized device structure */
 	if (WARN_ON(dev->devres_head.next == NULL))
 		return -ENODEV;
+
+	/* Nothing to release if list is empty */
+	if (list_empty(&dev->devres_head))
+		return 0;
+
 	spin_lock_irqsave(&dev->devres_lock, flags);
-	return release_nodes(dev, dev->devres_head.next, &dev->devres_head,
-			     flags);
+	cnt = remove_nodes(dev, dev->devres_head.next, &dev->devres_head, &todo);
+	spin_unlock_irqrestore(&dev->devres_lock, flags);
+
+	release_nodes(dev, &todo);
+	return cnt;
 }
 
 /**
@@ -543,7 +549,7 @@ int devres_release_all(struct device *dev)
  * RETURNS:
  * ID of the new group, NULL on failure.
  */
-void * devres_open_group(struct device *dev, void *id, gfp_t gfp)
+void *devres_open_group(struct device *dev, void *id, gfp_t gfp)
 {
 	struct devres_group *grp;
 	unsigned long flags;
@@ -561,6 +567,7 @@ void * devres_open_group(struct device *dev, void *id, gfp_t gfp)
 	grp->id = grp;
 	if (id)
 		grp->id = id;
+	grp->color = 0;
 
 	spin_lock_irqsave(&dev->devres_lock, flags);
 	add_dr(dev, &grp->node[0]);
@@ -569,8 +576,11 @@ void * devres_open_group(struct device *dev, void *id, gfp_t gfp)
 }
 EXPORT_SYMBOL_GPL(devres_open_group);
 
-/* Find devres group with ID @id.  If @id is NULL, look for the latest. */
-static struct devres_group * find_group(struct device *dev, void *id)
+/*
+ * Find devres group with ID @id.  If @id is NULL, look for the latest open
+ * group.
+ */
+static struct devres_group *find_group(struct device *dev, void *id)
 {
 	struct devres_node *node;
 
@@ -663,6 +673,7 @@ int devres_release_group(struct device *dev, void *id)
 {
 	struct devres_group *grp;
 	unsigned long flags;
+	LIST_HEAD(todo);
 	int cnt = 0;
 
 	spin_lock_irqsave(&dev->devres_lock, flags);
@@ -675,7 +686,17 @@ int devres_release_group(struct device *dev, void *id)
 		if (!list_empty(&grp->node[1].entry))
 			end = grp->node[1].entry.next;
 
-		cnt = release_nodes(dev, first, end, flags);
+		cnt = remove_nodes(dev, first, end, &todo);
+		spin_unlock_irqrestore(&dev->devres_lock, flags);
+
+		release_nodes(dev, &todo);
+	} else if (list_empty(&dev->devres_head)) {
+		/*
+		 * dev is probably dying via devres_release_all(): groups
+		 * have already been removed and are on the process of
+		 * being released - don't touch and don't warn.
+		 */
+		spin_unlock_irqrestore(&dev->devres_lock, flags);
 	} else {
 		WARN_ON(1);
 		spin_unlock_irqrestore(&dev->devres_lock, flags);
@@ -687,7 +708,7 @@ EXPORT_SYMBOL_GPL(devres_release_group);
 
 /*
  * Custom devres actions allow inserting a simple function call
- * into the teadown sequence.
+ * into the teardown sequence.
  */
 
 struct action_devres {
@@ -712,20 +733,21 @@ static void devm_action_release(struct device *dev, void *res)
 }
 
 /**
- * devm_add_action() - add a custom action to list of managed resources
+ * __devm_add_action() - add a custom action to list of managed resources
  * @dev: Device that owns the action
  * @action: Function that should be called
  * @data: Pointer to data passed to @action implementation
+ * @name: Name of the resource (for debugging purposes)
  *
  * This adds a custom action to the list of managed resources so that
  * it gets executed as part of standard resource unwinding.
  */
-int devm_add_action(struct device *dev, void (*action)(void *), void *data)
+int __devm_add_action(struct device *dev, void (*action)(void *), void *data, const char *name)
 {
 	struct action_devres *devres;
 
-	devres = devres_alloc(devm_action_release,
-			      sizeof(struct action_devres), GFP_KERNEL);
+	devres = __devres_alloc_node(devm_action_release, sizeof(struct action_devres),
+				     GFP_KERNEL, NUMA_NO_NODE, name);
 	if (!devres)
 		return -ENOMEM;
 
@@ -735,28 +757,52 @@ int devm_add_action(struct device *dev, void (*action)(void *), void *data)
 	devres_add(dev, devres);
 	return 0;
 }
-EXPORT_SYMBOL_GPL(devm_add_action);
+EXPORT_SYMBOL_GPL(__devm_add_action);
+
+bool devm_is_action_added(struct device *dev, void (*action)(void *), void *data)
+{
+	struct action_devres devres = {
+		.data = data,
+		.action = action,
+	};
+
+	return devres_find(dev, devm_action_release, devm_action_match, &devres);
+}
+EXPORT_SYMBOL_GPL(devm_is_action_added);
 
 /**
- * devm_remove_action() - removes previously added custom action
+ * devm_remove_action_nowarn() - removes previously added custom action
  * @dev: Device that owns the action
  * @action: Function implementing the action
  * @data: Pointer to data passed to @action implementation
  *
  * Removes instance of @action previously added by devm_add_action().
  * Both action and data should match one of the existing entries.
+ *
+ * In contrast to devm_remove_action(), this function does not WARN() if no
+ * entry could have been found.
+ *
+ * This should only be used if the action is contained in an object with
+ * independent lifetime management, e.g. the Devres rust abstraction.
+ *
+ * Causing the warning from regular driver code most likely indicates an abuse
+ * of the devres API.
+ *
+ * Returns: 0 on success, -ENOENT if no entry could have been found.
  */
-void devm_remove_action(struct device *dev, void (*action)(void *), void *data)
+int devm_remove_action_nowarn(struct device *dev,
+			      void (*action)(void *),
+			      void *data)
 {
 	struct action_devres devres = {
 		.data = data,
 		.action = action,
 	};
 
-	WARN_ON(devres_destroy(dev, devm_action_release, devm_action_match,
-			       &devres));
+	return devres_destroy(dev, devm_action_release, devm_action_match,
+			      &devres);
 }
-EXPORT_SYMBOL_GPL(devm_remove_action);
+EXPORT_SYMBOL_GPL(devm_remove_action_nowarn);
 
 /**
  * devm_release_action() - release previously added custom action
@@ -807,10 +853,13 @@ static int devm_kmalloc_match(struct device *dev, void *res, void *data)
  * RETURNS:
  * Pointer to allocated memory on success, NULL on failure.
  */
-void * devm_kmalloc(struct device *dev, size_t size, gfp_t gfp)
+void *devm_kmalloc(struct device *dev, size_t size, gfp_t gfp)
 {
 	struct devres *dr;
 
+	if (unlikely(!size))
+		return ZERO_SIZE_PTR;
+
 	/* use raw alloc_dr for kmalloc caller tracing */
 	dr = alloc_dr(devm_kmalloc_release, size, gfp, dev_to_node(dev));
 	if (unlikely(!dr))
@@ -827,6 +876,106 @@ void * devm_kmalloc(struct device *dev, size_t size, gfp_t gfp)
 EXPORT_SYMBOL_GPL(devm_kmalloc);
 
 /**
+ * devm_krealloc - Resource-managed krealloc()
+ * @dev: Device to re-allocate memory for
+ * @ptr: Pointer to the memory chunk to re-allocate
+ * @new_size: New allocation size
+ * @gfp: Allocation gfp flags
+ *
+ * Managed krealloc(). Resizes the memory chunk allocated with devm_kmalloc().
+ * Behaves similarly to regular krealloc(): if @ptr is NULL or ZERO_SIZE_PTR,
+ * it's the equivalent of devm_kmalloc(). If new_size is zero, it frees the
+ * previously allocated memory and returns ZERO_SIZE_PTR. This function doesn't
+ * change the order in which the release callback for the re-alloc'ed devres
+ * will be called (except when falling back to devm_kmalloc() or when freeing
+ * resources when new_size is zero). The contents of the memory are preserved
+ * up to the lesser of new and old sizes.
+ */
+void *devm_krealloc(struct device *dev, void *ptr, size_t new_size, gfp_t gfp)
+{
+	size_t total_new_size, total_old_size;
+	struct devres *old_dr, *new_dr;
+	unsigned long flags;
+
+	if (unlikely(!new_size)) {
+		devm_kfree(dev, ptr);
+		return ZERO_SIZE_PTR;
+	}
+
+	if (unlikely(ZERO_OR_NULL_PTR(ptr)))
+		return devm_kmalloc(dev, new_size, gfp);
+
+	if (WARN_ON(is_kernel_rodata((unsigned long)ptr)))
+		/*
+		 * We cannot reliably realloc a const string returned by
+		 * devm_kstrdup_const().
+		 */
+		return NULL;
+
+	if (!check_dr_size(new_size, &total_new_size))
+		return NULL;
+
+	total_old_size = ksize(container_of(ptr, struct devres, data));
+	if (total_old_size == 0) {
+		WARN(1, "Pointer doesn't point to dynamically allocated memory.");
+		return NULL;
+	}
+
+	/*
+	 * If new size is smaller or equal to the actual number of bytes
+	 * allocated previously - just return the same pointer.
+	 */
+	if (total_new_size <= total_old_size)
+		return ptr;
+
+	/*
+	 * Otherwise: allocate new, larger chunk. We need to allocate before
+	 * taking the lock as most probably the caller uses GFP_KERNEL.
+	 * alloc_dr() will call check_dr_size() to reserve extra memory
+	 * for struct devres automatically, so size @new_size user request
+	 * is delivered to it directly as devm_kmalloc() does.
+	 */
+	new_dr = alloc_dr(devm_kmalloc_release,
+			  new_size, gfp, dev_to_node(dev));
+	if (!new_dr)
+		return NULL;
+
+	/*
+	 * The spinlock protects the linked list against concurrent
+	 * modifications but not the resource itself.
+	 */
+	spin_lock_irqsave(&dev->devres_lock, flags);
+
+	old_dr = find_dr(dev, devm_kmalloc_release, devm_kmalloc_match, ptr);
+	if (!old_dr) {
+		spin_unlock_irqrestore(&dev->devres_lock, flags);
+		kfree(new_dr);
+		WARN(1, "Memory chunk not managed or managed by a different device.");
+		return NULL;
+	}
+
+	replace_dr(dev, &old_dr->node, &new_dr->node);
+
+	spin_unlock_irqrestore(&dev->devres_lock, flags);
+
+	/*
+	 * We can copy the memory contents after releasing the lock as we're
+	 * no longer modifying the list links.
+	 */
+	memcpy(new_dr->data, old_dr->data,
+	       total_old_size - offsetof(struct devres, data));
+	/*
+	 * Same for releasing the old devres - it's now been removed from the
+	 * list. This is also the reason why we must not use devm_kfree() - the
+	 * links are no longer valid.
+	 */
+	kfree(old_dr);
+
+	return new_dr->data;
+}
+EXPORT_SYMBOL_GPL(devm_krealloc);
+
+/**
  * devm_kstrdup - Allocate resource managed space and
  *                copy an existing string into that.
  * @dev: Device to allocate memory for
@@ -838,17 +987,10 @@ EXPORT_SYMBOL_GPL(devm_kmalloc);
  */
 char *devm_kstrdup(struct device *dev, const char *s, gfp_t gfp)
 {
-	size_t size;
-	char *buf;
-
 	if (!s)
 		return NULL;
 
-	size = strlen(s) + 1;
-	buf = devm_kmalloc(dev, size, gfp);
-	if (buf)
-		memcpy(buf, s, size);
-	return buf;
+	return devm_kmemdup(dev, s, strlen(s) + 1, gfp);
 }
 EXPORT_SYMBOL_GPL(devm_kstrdup);
 
@@ -942,10 +1084,10 @@ void devm_kfree(struct device *dev, const void *p)
 	int rc;
 
 	/*
-	 * Special case: pointer to a string in .rodata returned by
-	 * devm_kstrdup_const().
+	 * Special cases: pointer to a string in .rodata returned by
+	 * devm_kstrdup_const() or NULL/ZERO ptr.
 	 */
-	if (unlikely(is_kernel_rodata((unsigned long)p)))
+	if (unlikely(is_kernel_rodata((unsigned long)p) || ZERO_OR_NULL_PTR(p)))
 		return;
 
 	rc = devres_destroy(dev, devm_kmalloc_release,
@@ -975,6 +1117,27 @@ void *devm_kmemdup(struct device *dev, const void *src, size_t len, gfp_t gfp)
 }
 EXPORT_SYMBOL_GPL(devm_kmemdup);
 
+/**
+ * devm_kmemdup_const - conditionally duplicate and manage a region of memory
+ *
+ * @dev: Device this memory belongs to
+ * @src: memory region to duplicate
+ * @len: memory region length,
+ * @gfp: GFP mask to use
+ *
+ * Return: source address if it is in .rodata or the return value of kmemdup()
+ * to which the function falls back otherwise.
+ */
+const void *
+devm_kmemdup_const(struct device *dev, const void *src, size_t len, gfp_t gfp)
+{
+	if (is_kernel_rodata((unsigned long)src))
+		return src;
+
+	return devm_kmemdup(dev, src, len, gfp);
+}
+EXPORT_SYMBOL_GPL(devm_kmemdup_const);
+
 struct pages_devres {
 	unsigned long addr;
 	unsigned int order;
@@ -1059,13 +1222,6 @@ static void devm_percpu_release(struct device *dev, void *pdata)
 	free_percpu(p);
 }
 
-static int devm_percpu_match(struct device *dev, void *data, void *p)
-{
-	struct devres *devr = container_of(data, struct devres, data);
-
-	return *(void **)devr->data == p;
-}
-
 /**
  * __devm_alloc_percpu - Resource-managed alloc_percpu
  * @dev: Device to allocate per-cpu memory for
@@ -1101,17 +1257,3 @@ void __percpu *__devm_alloc_percpu(struct device *dev, size_t size,
 	return pcpu;
 }
 EXPORT_SYMBOL_GPL(__devm_alloc_percpu);
-
-/**
- * devm_free_percpu - Resource-managed free_percpu
- * @dev: Device this memory belongs to
- * @pdata: Per-cpu memory to free
- *
- * Free memory allocated with devm_alloc_percpu().
- */
-void devm_free_percpu(struct device *dev, void __percpu *pdata)
-{
-	WARN_ON(devres_destroy(dev, devm_percpu_release, devm_percpu_match,
-			       (void *)pdata));
-}
-EXPORT_SYMBOL_GPL(devm_free_percpu);
diff --git a/drivers/base/devtmpfs.c b/drivers/base/devtmpfs.c
index c9017e0584c0..194b44075ac7 100644
--- a/drivers/base/devtmpfs.c
+++ b/drivers/base/devtmpfs.c
@@ -13,11 +13,13 @@
  * overwrite the default setting if needed.
  */
 
+#define pr_fmt(fmt) "devtmpfs: " fmt
+
 #include <linux/kernel.h>
 #include <linux/syscalls.h>
 #include <linux/mount.h>
 #include <linux/device.h>
-#include <linux/genhd.h>
+#include <linux/blkdev.h>
 #include <linux/namei.h>
 #include <linux/fs.h>
 #include <linux/shmem_fs.h>
@@ -25,9 +27,16 @@
 #include <linux/sched.h>
 #include <linux/slab.h>
 #include <linux/kthread.h>
+#include <linux/init_syscalls.h>
 #include <uapi/linux/mount.h>
 #include "base.h"
 
+#ifdef CONFIG_DEVTMPFS_SAFE
+#define DEVTMPFS_MFLAGS       (MS_SILENT | MS_NOEXEC | MS_NOSUID)
+#else
+#define DEVTMPFS_MFLAGS       (MS_SILENT)
+#endif
+
 static struct task_struct *thread;
 
 static int __initdata mount_dev = IS_ENABLED(CONFIG_DEVTMPFS_MOUNT);
@@ -54,40 +63,51 @@ __setup("devtmpfs.mount=", mount_param);
 
 static struct vfsmount *mnt;
 
-static struct dentry *public_dev_mount(struct file_system_type *fs_type, int flags,
-		      const char *dev_name, void *data)
-{
-	struct super_block *s = mnt->mnt_sb;
-	atomic_inc(&s->s_active);
-	down_write(&s->s_umount);
-	return dget(s->s_root);
-}
-
 static struct file_system_type internal_fs_type = {
 	.name = "devtmpfs",
 #ifdef CONFIG_TMPFS
 	.init_fs_context = shmem_init_fs_context,
-	.parameters	= shmem_fs_parameters,
 #else
 	.init_fs_context = ramfs_init_fs_context,
-	.parameters	= ramfs_fs_parameters,
 #endif
-	.kill_sb = kill_litter_super,
-};
-
-static struct file_system_type dev_fs_type = {
-	.name = "devtmpfs",
-	.mount = public_dev_mount,
+	.kill_sb = kill_anon_super,
 };
 
-#ifdef CONFIG_BLOCK
-static inline int is_blockdev(struct device *dev)
+/* Simply take a ref on the existing mount */
+static int devtmpfs_get_tree(struct fs_context *fc)
 {
-	return dev->class == &block_class;
+	struct super_block *sb = mnt->mnt_sb;
+
+	atomic_inc(&sb->s_active);
+	down_write(&sb->s_umount);
+	fc->root = dget(sb->s_root);
+	return 0;
 }
+
+/* Ops are filled in during init depending on underlying shmem or ramfs type */
+struct fs_context_operations devtmpfs_context_ops = {};
+
+/* Call the underlying initialization and set to our ops */
+static int devtmpfs_init_fs_context(struct fs_context *fc)
+{
+	int ret;
+#ifdef CONFIG_TMPFS
+	ret = shmem_init_fs_context(fc);
 #else
-static inline int is_blockdev(struct device *dev) { return 0; }
+	ret = ramfs_init_fs_context(fc);
 #endif
+	if (ret < 0)
+		return ret;
+
+	fc->ops = &devtmpfs_context_ops;
+
+	return 0;
+}
+
+static struct file_system_type dev_fs_type = {
+	.name = "devtmpfs",
+	.init_fs_context = devtmpfs_init_fs_context,
+};
 
 static int devtmpfs_submit_req(struct req *req, const char *tmp)
 {
@@ -155,18 +175,17 @@ static int dev_mkdir(const char *name, umode_t mode)
 {
 	struct dentry *dentry;
 	struct path path;
-	int err;
 
-	dentry = kern_path_create(AT_FDCWD, name, &path, LOOKUP_DIRECTORY);
+	dentry = start_creating_path(AT_FDCWD, name, &path, LOOKUP_DIRECTORY);
 	if (IS_ERR(dentry))
 		return PTR_ERR(dentry);
 
-	err = vfs_mkdir(d_inode(path.dentry), dentry, mode);
-	if (!err)
+	dentry = vfs_mkdir(&nop_mnt_idmap, d_inode(path.dentry), dentry, mode, NULL);
+	if (!IS_ERR(dentry))
 		/* mark as kernel-created inode */
 		d_inode(dentry)->i_private = &thread;
-	done_path_create(&path, dentry);
-	return err;
+	end_creating_path(&path, dentry);
+	return PTR_ERR_OR_ZERO(dentry);
 }
 
 static int create_path(const char *nodepath)
@@ -203,15 +222,16 @@ static int handle_create(const char *nodename, umode_t mode, kuid_t uid,
 	struct path path;
 	int err;
 
-	dentry = kern_path_create(AT_FDCWD, nodename, &path, 0);
+	dentry = start_creating_path(AT_FDCWD, nodename, &path, 0);
 	if (dentry == ERR_PTR(-ENOENT)) {
 		create_path(nodename);
-		dentry = kern_path_create(AT_FDCWD, nodename, &path, 0);
+		dentry = start_creating_path(AT_FDCWD, nodename, &path, 0);
 	}
 	if (IS_ERR(dentry))
 		return PTR_ERR(dentry);
 
-	err = vfs_mknod(d_inode(path.dentry), dentry, mode, dev->devt);
+	err = vfs_mknod(&nop_mnt_idmap, d_inode(path.dentry), dentry, mode,
+			dev->devt, NULL);
 	if (!err) {
 		struct iattr newattrs;
 
@@ -220,13 +240,13 @@ static int handle_create(const char *nodename, umode_t mode, kuid_t uid,
 		newattrs.ia_gid = gid;
 		newattrs.ia_valid = ATTR_MODE|ATTR_UID|ATTR_GID;
 		inode_lock(d_inode(dentry));
-		notify_change(dentry, &newattrs, NULL);
+		notify_change(&nop_mnt_idmap, dentry, &newattrs, NULL);
 		inode_unlock(d_inode(dentry));
 
 		/* mark as kernel-created inode */
 		d_inode(dentry)->i_private = &thread;
 	}
-	done_path_create(&path, dentry);
+	end_creating_path(&path, dentry);
 	return err;
 }
 
@@ -236,20 +256,16 @@ static int dev_rmdir(const char *name)
 	struct dentry *dentry;
 	int err;
 
-	dentry = kern_path_locked(name, &parent);
+	dentry = start_removing_path(name, &parent);
 	if (IS_ERR(dentry))
 		return PTR_ERR(dentry);
-	if (d_really_is_positive(dentry)) {
-		if (d_inode(dentry)->i_private == &thread)
-			err = vfs_rmdir(d_inode(parent.dentry), dentry);
-		else
-			err = -EPERM;
-	} else {
-		err = -ENOENT;
-	}
-	dput(dentry);
-	inode_unlock(d_inode(parent.dentry));
-	path_put(&parent);
+	if (d_inode(dentry)->i_private == &thread)
+		err = vfs_rmdir(&nop_mnt_idmap, d_inode(parent.dentry),
+				dentry, NULL);
+	else
+		err = -EPERM;
+
+	end_removing_path(&parent, dentry);
 	return err;
 }
 
@@ -278,7 +294,7 @@ static int delete_path(const char *nodepath)
 	return err;
 }
 
-static int dev_mynode(struct device *dev, struct inode *inode, struct kstat *stat)
+static int dev_mynode(struct device *dev, struct inode *inode)
 {
 	/* did we create it */
 	if (inode->i_private != &thread)
@@ -286,13 +302,13 @@ static int dev_mynode(struct device *dev, struct inode *inode, struct kstat *sta
 
 	/* does the dev_t match */
 	if (is_blockdev(dev)) {
-		if (!S_ISBLK(stat->mode))
+		if (!S_ISBLK(inode->i_mode))
 			return 0;
 	} else {
-		if (!S_ISCHR(stat->mode))
+		if (!S_ISCHR(inode->i_mode))
 			return 0;
 	}
-	if (stat->rdev != dev->devt)
+	if (inode->i_rdev != dev->devt)
 		return 0;
 
 	/* ours */
@@ -303,43 +319,36 @@ static int handle_remove(const char *nodename, struct device *dev)
 {
 	struct path parent;
 	struct dentry *dentry;
+	struct inode *inode;
 	int deleted = 0;
-	int err;
+	int err = 0;
 
-	dentry = kern_path_locked(nodename, &parent);
+	dentry = start_removing_path(nodename, &parent);
 	if (IS_ERR(dentry))
 		return PTR_ERR(dentry);
 
-	if (d_really_is_positive(dentry)) {
-		struct kstat stat;
-		struct path p = {.mnt = parent.mnt, .dentry = dentry};
-		err = vfs_getattr(&p, &stat, STATX_TYPE | STATX_MODE,
-				  AT_STATX_SYNC_AS_STAT);
-		if (!err && dev_mynode(dev, d_inode(dentry), &stat)) {
-			struct iattr newattrs;
-			/*
-			 * before unlinking this node, reset permissions
-			 * of possible references like hardlinks
-			 */
-			newattrs.ia_uid = GLOBAL_ROOT_UID;
-			newattrs.ia_gid = GLOBAL_ROOT_GID;
-			newattrs.ia_mode = stat.mode & ~0777;
-			newattrs.ia_valid =
-				ATTR_UID|ATTR_GID|ATTR_MODE;
-			inode_lock(d_inode(dentry));
-			notify_change(dentry, &newattrs, NULL);
-			inode_unlock(d_inode(dentry));
-			err = vfs_unlink(d_inode(parent.dentry), dentry, NULL);
-			if (!err || err == -ENOENT)
-				deleted = 1;
-		}
-	} else {
-		err = -ENOENT;
+	inode = d_inode(dentry);
+	if (dev_mynode(dev, inode)) {
+		struct iattr newattrs;
+		/*
+		 * before unlinking this node, reset permissions
+		 * of possible references like hardlinks
+		 */
+		newattrs.ia_uid = GLOBAL_ROOT_UID;
+		newattrs.ia_gid = GLOBAL_ROOT_GID;
+		newattrs.ia_mode = inode->i_mode & ~0777;
+		newattrs.ia_valid =
+			ATTR_UID|ATTR_GID|ATTR_MODE;
+		inode_lock(d_inode(dentry));
+		notify_change(&nop_mnt_idmap, dentry, &newattrs, NULL);
+		inode_unlock(d_inode(dentry));
+		err = vfs_unlink(&nop_mnt_idmap, d_inode(parent.dentry),
+				 dentry, NULL);
+		if (!err || err == -ENOENT)
+			deleted = 1;
 	}
-	dput(dentry);
-	inode_unlock(d_inode(parent.dentry));
+	end_removing_path(&parent, dentry);
 
-	path_put(&parent);
 	if (deleted && strchr(nodename, '/'))
 		delete_path(nodename);
 	return err;
@@ -359,15 +368,15 @@ int __init devtmpfs_mount(void)
 	if (!thread)
 		return 0;
 
-	err = do_mount("devtmpfs", "dev", "devtmpfs", MS_SILENT, NULL);
+	err = init_mount("devtmpfs", "dev", "devtmpfs", DEVTMPFS_MFLAGS, NULL);
 	if (err)
-		printk(KERN_INFO "devtmpfs: error mounting %i\n", err);
+		pr_info("error mounting %d\n", err);
 	else
-		printk(KERN_INFO "devtmpfs: mounted\n");
+		pr_info("mounted\n");
 	return err;
 }
 
-static DECLARE_COMPLETION(setup_done);
+static __initdata DECLARE_COMPLETION(setup_done);
 
 static int handle(const char *name, umode_t mode, kuid_t uid, kgid_t gid,
 		  struct device *dev)
@@ -378,30 +387,8 @@ static int handle(const char *name, umode_t mode, kuid_t uid, kgid_t gid,
 		return handle_remove(name, dev);
 }
 
-static int devtmpfs_setup(void *p)
+static void __noreturn devtmpfs_work_loop(void)
 {
-	int err;
-
-	err = ksys_unshare(CLONE_NEWNS);
-	if (err)
-		goto out;
-	err = do_mount("devtmpfs", "/", "devtmpfs", MS_SILENT, NULL);
-	if (err)
-		goto out;
-	ksys_chdir("/.."); /* will traverse into overmounted root */
-	ksys_chroot(".");
-out:
-	*(int *)p = err;
-	complete(&setup_done);
-	return err;
-}
-
-static int devtmpfsd(void *p)
-{
-	int err = devtmpfs_setup(p);
-
-	if (err)
-		return err;
 	while (1) {
 		spin_lock(&req_lock);
 		while (requests) {
@@ -421,6 +408,63 @@ static int devtmpfsd(void *p)
 		spin_unlock(&req_lock);
 		schedule();
 	}
+}
+
+static noinline int __init devtmpfs_setup(void *p)
+{
+	int err;
+
+	err = ksys_unshare(CLONE_NEWNS);
+	if (err)
+		goto out;
+	err = init_mount("devtmpfs", "/", "devtmpfs", DEVTMPFS_MFLAGS, NULL);
+	if (err)
+		goto out;
+	init_chdir("/.."); /* will traverse into overmounted root */
+	init_chroot(".");
+out:
+	*(int *)p = err;
+	return err;
+}
+
+/*
+ * The __ref is because devtmpfs_setup needs to be __init for the routines it
+ * calls.  That call is done while devtmpfs_init, which is marked __init,
+ * synchronously waits for it to complete.
+ */
+static int __ref devtmpfsd(void *p)
+{
+	int err = devtmpfs_setup(p);
+
+	complete(&setup_done);
+	if (err)
+		return err;
+	devtmpfs_work_loop();
+	return 0;
+}
+
+/*
+ * Get the underlying (shmem/ramfs) context ops to build ours
+ */
+static int devtmpfs_configure_context(void)
+{
+	struct fs_context *fc;
+
+	fc = fs_context_for_reconfigure(mnt->mnt_root, mnt->mnt_sb->s_flags,
+					MS_RMT_MASK);
+	if (IS_ERR(fc))
+		return PTR_ERR(fc);
+
+	/* Set up devtmpfs_context_ops based on underlying type */
+	devtmpfs_context_ops.free	      = fc->ops->free;
+	devtmpfs_context_ops.dup	      = fc->ops->dup;
+	devtmpfs_context_ops.parse_param      = fc->ops->parse_param;
+	devtmpfs_context_ops.parse_monolithic = fc->ops->parse_monolithic;
+	devtmpfs_context_ops.get_tree	      = &devtmpfs_get_tree;
+	devtmpfs_context_ops.reconfigure      = fc->ops->reconfigure;
+
+	put_fs_context(fc);
+
 	return 0;
 }
 
@@ -435,14 +479,19 @@ int __init devtmpfs_init(void)
 
 	mnt = vfs_kern_mount(&internal_fs_type, 0, "devtmpfs", opts);
 	if (IS_ERR(mnt)) {
-		printk(KERN_ERR "devtmpfs: unable to create devtmpfs %ld\n",
-				PTR_ERR(mnt));
+		pr_err("unable to create devtmpfs %ld\n", PTR_ERR(mnt));
 		return PTR_ERR(mnt);
 	}
+
+	err = devtmpfs_configure_context();
+	if (err) {
+		pr_err("unable to configure devtmpfs type %d\n", err);
+		return err;
+	}
+
 	err = register_filesystem(&dev_fs_type);
 	if (err) {
-		printk(KERN_ERR "devtmpfs: unable to register devtmpfs "
-		       "type %i\n", err);
+		pr_err("unable to register devtmpfs type %d\n", err);
 		return err;
 	}
 
@@ -455,11 +504,12 @@ int __init devtmpfs_init(void)
 	}
 
 	if (err) {
-		printk(KERN_ERR "devtmpfs: unable to create devtmpfs %i\n", err);
+		pr_err("unable to create devtmpfs %d\n", err);
 		unregister_filesystem(&dev_fs_type);
+		thread = NULL;
 		return err;
 	}
 
-	printk(KERN_INFO "devtmpfs: initialized\n");
+	pr_info("initialized\n");
 	return 0;
 }
diff --git a/drivers/base/driver.c b/drivers/base/driver.c
index 57c68769e157..8ab010ddf709 100644
--- a/drivers/base/driver.c
+++ b/drivers/base/driver.c
@@ -31,6 +31,81 @@ static struct device *next_device(struct klist_iter *i)
 }
 
 /**
+ * driver_set_override() - Helper to set or clear driver override.
+ * @dev: Device to change
+ * @override: Address of string to change (e.g. &device->driver_override);
+ *            The contents will be freed and hold newly allocated override.
+ * @s: NUL-terminated string, new driver name to force a match, pass empty
+ *     string to clear it ("" or "\n", where the latter is only for sysfs
+ *     interface).
+ * @len: length of @s
+ *
+ * Helper to set or clear driver override in a device, intended for the cases
+ * when the driver_override field is allocated by driver/bus code.
+ *
+ * Returns: 0 on success or a negative error code on failure.
+ */
+int driver_set_override(struct device *dev, const char **override,
+			const char *s, size_t len)
+{
+	const char *new, *old;
+	char *cp;
+
+	if (!override || !s)
+		return -EINVAL;
+
+	/*
+	 * The stored value will be used in sysfs show callback (sysfs_emit()),
+	 * which has a length limit of PAGE_SIZE and adds a trailing newline.
+	 * Thus we can store one character less to avoid truncation during sysfs
+	 * show.
+	 */
+	if (len >= (PAGE_SIZE - 1))
+		return -EINVAL;
+
+	/*
+	 * Compute the real length of the string in case userspace sends us a
+	 * bunch of \0 characters like python likes to do.
+	 */
+	len = strlen(s);
+
+	if (!len) {
+		/* Empty string passed - clear override */
+		device_lock(dev);
+		old = *override;
+		*override = NULL;
+		device_unlock(dev);
+		kfree(old);
+
+		return 0;
+	}
+
+	cp = strnchr(s, len, '\n');
+	if (cp)
+		len = cp - s;
+
+	new = kstrndup(s, len, GFP_KERNEL);
+	if (!new)
+		return -ENOMEM;
+
+	device_lock(dev);
+	old = *override;
+	if (cp != s) {
+		*override = new;
+	} else {
+		/* "\n" passed - clear override */
+		kfree(new);
+		*override = NULL;
+	}
+	device_unlock(dev);
+
+	kfree(old);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(driver_set_override);
+
+/**
  * driver_for_each_device - Iterator for devices bound to a driver.
  * @drv: Driver we're iterating.
  * @start: Device to begin with
@@ -40,7 +115,7 @@ static struct device *next_device(struct klist_iter *i)
  * Iterate over the @drv's list of devices calling @fn for each one.
  */
 int driver_for_each_device(struct device_driver *drv, struct device *start,
-			   void *data, int (*fn)(struct device *, void *))
+			   void *data, device_iter_t fn)
 {
 	struct klist_iter i;
 	struct device *dev;
@@ -73,9 +148,9 @@ EXPORT_SYMBOL_GPL(driver_for_each_device);
  * if it does.  If the callback returns non-zero, this function will
  * return to the caller and not iterate over any more devices.
  */
-struct device *driver_find_device(struct device_driver *drv,
+struct device *driver_find_device(const struct device_driver *drv,
 				  struct device *start, const void *data,
-				  int (*match)(struct device *dev, const void *data))
+				  device_match_t match)
 {
 	struct klist_iter i;
 	struct device *dev;
@@ -85,9 +160,12 @@ struct device *driver_find_device(struct device_driver *drv,
 
 	klist_iter_init_node(&drv->p->klist_devices, &i,
 			     (start ? &start->p->knode_driver : NULL));
-	while ((dev = next_device(&i)))
-		if (match(dev, data) && get_device(dev))
+	while ((dev = next_device(&i))) {
+		if (match(dev, data)) {
+			get_device(dev);
 			break;
+		}
+	}
 	klist_iter_exit(&i);
 	return dev;
 }
@@ -98,7 +176,7 @@ EXPORT_SYMBOL_GPL(driver_find_device);
  * @drv: driver.
  * @attr: driver attribute descriptor.
  */
-int driver_create_file(struct device_driver *drv,
+int driver_create_file(const struct device_driver *drv,
 		       const struct driver_attribute *attr)
 {
 	int error;
@@ -116,7 +194,7 @@ EXPORT_SYMBOL_GPL(driver_create_file);
  * @drv: driver.
  * @attr: driver attribute descriptor.
  */
-void driver_remove_file(struct device_driver *drv,
+void driver_remove_file(const struct device_driver *drv,
 			const struct driver_attribute *attr)
 {
 	if (drv)
@@ -124,13 +202,13 @@ void driver_remove_file(struct device_driver *drv,
 }
 EXPORT_SYMBOL_GPL(driver_remove_file);
 
-int driver_add_groups(struct device_driver *drv,
+int driver_add_groups(const struct device_driver *drv,
 		      const struct attribute_group **groups)
 {
 	return sysfs_create_groups(&drv->p->kobj, groups);
 }
 
-void driver_remove_groups(struct device_driver *drv,
+void driver_remove_groups(const struct device_driver *drv,
 			  const struct attribute_group **groups)
 {
 	sysfs_remove_groups(&drv->p->kobj, groups);
@@ -149,7 +227,7 @@ int driver_register(struct device_driver *drv)
 	int ret;
 	struct device_driver *other;
 
-	if (!drv->bus->p) {
+	if (!bus_is_registered(drv->bus)) {
 		pr_err("Driver '%s' was unable to register with bus_type '%s' because the bus was not initialized.\n",
 			   drv->name, drv->bus->name);
 		return -EINVAL;
@@ -158,12 +236,12 @@ int driver_register(struct device_driver *drv)
 	if ((drv->bus->probe && drv->probe) ||
 	    (drv->bus->remove && drv->remove) ||
 	    (drv->bus->shutdown && drv->shutdown))
-		printk(KERN_WARNING "Driver '%s' needs updating - please use "
+		pr_warn("Driver '%s' needs updating - please use "
 			"bus_type methods\n", drv->name);
 
 	other = driver_find(drv->name, drv->bus);
 	if (other) {
-		printk(KERN_ERR "Error: Driver '%s' is already registered, "
+		pr_err("Error: Driver '%s' is already registered, "
 			"aborting...\n", drv->name);
 		return -EBUSY;
 	}
@@ -177,6 +255,7 @@ int driver_register(struct device_driver *drv)
 		return ret;
 	}
 	kobject_uevent(&drv->p->kobj, KOBJ_ADD);
+	deferred_probe_extend_timeout();
 
 	return ret;
 }
@@ -198,30 +277,3 @@ void driver_unregister(struct device_driver *drv)
 	bus_remove_driver(drv);
 }
 EXPORT_SYMBOL_GPL(driver_unregister);
-
-/**
- * driver_find - locate driver on a bus by its name.
- * @name: name of the driver.
- * @bus: bus to scan for the driver.
- *
- * Call kset_find_obj() to iterate over list of drivers on
- * a bus to find driver by name. Return driver if found.
- *
- * This routine provides no locking to prevent the driver it returns
- * from being unregistered or unloaded while the caller is using it.
- * The caller is responsible for preventing this.
- */
-struct device_driver *driver_find(const char *name, struct bus_type *bus)
-{
-	struct kobject *k = kset_find_obj(bus->p->drivers_kset, name);
-	struct driver_private *priv;
-
-	if (k) {
-		/* Drop reference added by kset_find_obj() */
-		kobject_put(k);
-		priv = to_driver(k);
-		return priv->driver;
-	}
-	return NULL;
-}
-EXPORT_SYMBOL_GPL(driver_find);
diff --git a/drivers/base/faux.c b/drivers/base/faux.c
new file mode 100644
index 000000000000..21dd02124231
--- /dev/null
+++ b/drivers/base/faux.c
@@ -0,0 +1,261 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2025 Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+ * Copyright (c) 2025 The Linux Foundation
+ *
+ * A "simple" faux bus that allows devices to be created and added
+ * automatically to it.  This is to be used whenever you need to create a
+ * device that is not associated with any "real" system resources, and do
+ * not want to have to deal with a bus/driver binding logic.  It is
+ * intended to be very simple, with only a create and a destroy function
+ * available.
+ */
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/container_of.h>
+#include <linux/device/faux.h>
+#include "base.h"
+
+/*
+ * Internal wrapper structure so we can hold a pointer to the
+ * faux_device_ops for this device.
+ */
+struct faux_object {
+	struct faux_device faux_dev;
+	const struct faux_device_ops *faux_ops;
+	const struct attribute_group **groups;
+};
+#define to_faux_object(dev) container_of_const(dev, struct faux_object, faux_dev.dev)
+
+static struct device faux_bus_root = {
+	.init_name	= "faux",
+};
+
+static int faux_match(struct device *dev, const struct device_driver *drv)
+{
+	/* Match always succeeds, we only have one driver */
+	return 1;
+}
+
+static int faux_probe(struct device *dev)
+{
+	struct faux_object *faux_obj = to_faux_object(dev);
+	struct faux_device *faux_dev = &faux_obj->faux_dev;
+	const struct faux_device_ops *faux_ops = faux_obj->faux_ops;
+	int ret;
+
+	if (faux_ops && faux_ops->probe) {
+		ret = faux_ops->probe(faux_dev);
+		if (ret)
+			return ret;
+	}
+
+	/*
+	 * Add groups after the probe succeeds to ensure resources are
+	 * initialized correctly
+	 */
+	ret = device_add_groups(dev, faux_obj->groups);
+	if (ret && faux_ops && faux_ops->remove)
+		faux_ops->remove(faux_dev);
+
+	return ret;
+}
+
+static void faux_remove(struct device *dev)
+{
+	struct faux_object *faux_obj = to_faux_object(dev);
+	struct faux_device *faux_dev = &faux_obj->faux_dev;
+	const struct faux_device_ops *faux_ops = faux_obj->faux_ops;
+
+	device_remove_groups(dev, faux_obj->groups);
+
+	if (faux_ops && faux_ops->remove)
+		faux_ops->remove(faux_dev);
+}
+
+static const struct bus_type faux_bus_type = {
+	.name		= "faux",
+	.match		= faux_match,
+	.probe		= faux_probe,
+	.remove		= faux_remove,
+};
+
+static struct device_driver faux_driver = {
+	.name		= "faux_driver",
+	.bus		= &faux_bus_type,
+	.probe_type	= PROBE_FORCE_SYNCHRONOUS,
+	.suppress_bind_attrs = true,
+};
+
+static void faux_device_release(struct device *dev)
+{
+	struct faux_object *faux_obj = to_faux_object(dev);
+
+	kfree(faux_obj);
+}
+
+/**
+ * faux_device_create_with_groups - Create and register with the driver
+ *		core a faux device and populate the device with an initial
+ *		set of sysfs attributes.
+ * @name:	The name of the device we are adding, must be unique for
+ *		all faux devices.
+ * @parent:	Pointer to a potential parent struct device.  If set to
+ *		NULL, the device will be created in the "root" of the faux
+ *		device tree in sysfs.
+ * @faux_ops:	struct faux_device_ops that the new device will call back
+ *		into, can be NULL.
+ * @groups:	The set of sysfs attributes that will be created for this
+ *		device when it is registered with the driver core.
+ *
+ * Create a new faux device and register it in the driver core properly.
+ * If present, callbacks in @faux_ops will be called with the device that
+ * for the caller to do something with at the proper time given the
+ * device's lifecycle.
+ *
+ * Note, when this function is called, the functions specified in struct
+ * faux_ops can be called before the function returns, so be prepared for
+ * everything to be properly initialized before that point in time.  If the
+ * probe callback (if one is present) does NOT succeed, the creation of the
+ * device will fail and NULL will be returned.
+ *
+ * Return:
+ * * NULL if an error happened with creating the device
+ * * pointer to a valid struct faux_device that is registered with sysfs
+ */
+struct faux_device *faux_device_create_with_groups(const char *name,
+						   struct device *parent,
+						   const struct faux_device_ops *faux_ops,
+						   const struct attribute_group **groups)
+{
+	struct faux_object *faux_obj;
+	struct faux_device *faux_dev;
+	struct device *dev;
+	int ret;
+
+	faux_obj = kzalloc(sizeof(*faux_obj), GFP_KERNEL);
+	if (!faux_obj)
+		return NULL;
+
+	/* Save off the callbacks and groups so we can use them in the future */
+	faux_obj->faux_ops = faux_ops;
+	faux_obj->groups = groups;
+
+	/* Initialize the device portion and register it with the driver core */
+	faux_dev = &faux_obj->faux_dev;
+	dev = &faux_dev->dev;
+
+	device_initialize(dev);
+	dev->release = faux_device_release;
+	if (parent)
+		dev->parent = parent;
+	else
+		dev->parent = &faux_bus_root;
+	dev->bus = &faux_bus_type;
+	dev_set_name(dev, "%s", name);
+	device_set_pm_not_required(dev);
+
+	ret = device_add(dev);
+	if (ret) {
+		pr_err("%s: device_add for faux device '%s' failed with %d\n",
+		       __func__, name, ret);
+		put_device(dev);
+		return NULL;
+	}
+
+	/*
+	 * Verify that we did bind the driver to the device (i.e. probe worked),
+	 * if not, let's fail the creation as trying to guess if probe was
+	 * successful is almost impossible to determine by the caller.
+	 */
+	if (!dev->driver) {
+		dev_dbg(dev, "probe did not succeed, tearing down the device\n");
+		faux_device_destroy(faux_dev);
+		faux_dev = NULL;
+	}
+
+	return faux_dev;
+}
+EXPORT_SYMBOL_GPL(faux_device_create_with_groups);
+
+/**
+ * faux_device_create - create and register with the driver core a faux device
+ * @name:	The name of the device we are adding, must be unique for all
+ *		faux devices.
+ * @parent:	Pointer to a potential parent struct device.  If set to
+ *		NULL, the device will be created in the "root" of the faux
+ *		device tree in sysfs.
+ * @faux_ops:	struct faux_device_ops that the new device will call back
+ *		into, can be NULL.
+ *
+ * Create a new faux device and register it in the driver core properly.
+ * If present, callbacks in @faux_ops will be called with the device that
+ * for the caller to do something with at the proper time given the
+ * device's lifecycle.
+ *
+ * Note, when this function is called, the functions specified in struct
+ * faux_ops can be called before the function returns, so be prepared for
+ * everything to be properly initialized before that point in time.
+ *
+ * Return:
+ * * NULL if an error happened with creating the device
+ * * pointer to a valid struct faux_device that is registered with sysfs
+ */
+struct faux_device *faux_device_create(const char *name,
+				       struct device *parent,
+				       const struct faux_device_ops *faux_ops)
+{
+	return faux_device_create_with_groups(name, parent, faux_ops, NULL);
+}
+EXPORT_SYMBOL_GPL(faux_device_create);
+
+/**
+ * faux_device_destroy - destroy a faux device
+ * @faux_dev:	faux device to destroy
+ *
+ * Unregisters and cleans up a device that was created with a call to
+ * faux_device_create()
+ */
+void faux_device_destroy(struct faux_device *faux_dev)
+{
+	struct device *dev = &faux_dev->dev;
+
+	if (!faux_dev)
+		return;
+
+	device_del(dev);
+
+	/* The final put_device() will clean up the memory we allocated for this device. */
+	put_device(dev);
+}
+EXPORT_SYMBOL_GPL(faux_device_destroy);
+
+int __init faux_bus_init(void)
+{
+	int ret;
+
+	ret = device_register(&faux_bus_root);
+	if (ret) {
+		put_device(&faux_bus_root);
+		return ret;
+	}
+
+	ret = bus_register(&faux_bus_type);
+	if (ret)
+		goto error_bus;
+
+	ret = driver_register(&faux_driver);
+	if (ret)
+		goto error_driver;
+
+	return ret;
+
+error_driver:
+	bus_unregister(&faux_bus_type);
+
+error_bus:
+	device_unregister(&faux_bus_root);
+	return ret;
+}
diff --git a/drivers/base/firmware_loader/Kconfig b/drivers/base/firmware_loader/Kconfig
index 5b24f3959255..15eff8a4b505 100644
--- a/drivers/base/firmware_loader/Kconfig
+++ b/drivers/base/firmware_loader/Kconfig
@@ -3,6 +3,7 @@ menu "Firmware loader"
 
 config FW_LOADER
 	tristate "Firmware loading facility" if EXPERT
+	select CRYPTO_LIB_SHA256 if FW_LOADER_DEBUG
 	default y
 	help
 	  This enables the firmware loading facility in the kernel. The kernel
@@ -24,11 +25,31 @@ config FW_LOADER
 	  You also want to be sure to enable this built-in if you are going to
 	  enable built-in firmware (CONFIG_EXTRA_FIRMWARE).
 
+config FW_LOADER_DEBUG
+	bool "Log filenames and checksums for loaded firmware"
+	depends on DYNAMIC_DEBUG
+	depends on FW_LOADER
+	default FW_LOADER
+	help
+	  Select this option to use dynamic debug to log firmware filenames and
+	  SHA256 checksums to the kernel log for each firmware file that is
+	  loaded.
+
+config RUST_FW_LOADER_ABSTRACTIONS
+	bool "Rust Firmware Loader abstractions"
+	depends on RUST
+	select FW_LOADER
+	help
+	  This enables the Rust abstractions for the firmware loader API.
+
 if FW_LOADER
 
 config FW_LOADER_PAGED_BUF
 	bool
 
+config FW_LOADER_SYSFS
+	bool
+
 config EXTRA_FIRMWARE
 	string "Build named firmware blobs into the kernel binary"
 	help
@@ -60,6 +81,8 @@ config EXTRA_FIRMWARE
 	  image since it combines both GPL and non-GPL work. You should
 	  consult a lawyer of your own before distributing such an image.
 
+	  NOTE: Compressed files are not supported in EXTRA_FIRMWARE.
+
 config EXTRA_FIRMWARE_DIR
 	string "Firmware blobs root directory"
 	depends on EXTRA_FIRMWARE != ""
@@ -70,6 +93,7 @@ config EXTRA_FIRMWARE_DIR
 
 config FW_LOADER_USER_HELPER
 	bool "Enable the firmware sysfs fallback mechanism"
+	select FW_LOADER_SYSFS
 	select FW_LOADER_PAGED_BUF
 	help
 	  This option enables a sysfs loading facility to enable firmware
@@ -157,17 +181,33 @@ config FW_LOADER_USER_HELPER_FALLBACK
 
 config FW_LOADER_COMPRESS
 	bool "Enable compressed firmware support"
-	select FW_LOADER_PAGED_BUF
-	select XZ_DEC
 	help
 	  This option enables the support for loading compressed firmware
 	  files. The caller of firmware API receives the decompressed file
 	  content. The compressed file is loaded as a fallback, only after
 	  loading the raw file failed at first.
 
-	  Currently only XZ-compressed files are supported, and they have to
-	  be compressed with either none or crc32 integrity check type (pass
-	  "-C crc32" option to xz command).
+	  Compressed firmware support does not apply to firmware images
+	  that are built into the kernel image (CONFIG_EXTRA_FIRMWARE).
+
+if FW_LOADER_COMPRESS
+config FW_LOADER_COMPRESS_XZ
+	bool "Enable XZ-compressed firmware support"
+	select FW_LOADER_PAGED_BUF
+	select XZ_DEC
+	default y
+	help
+	  This option adds the support for XZ-compressed files.
+	  The files have to be compressed with either none or crc32
+	  integrity check type (pass "-C crc32" option to xz command).
+
+config FW_LOADER_COMPRESS_ZSTD
+	bool "Enable ZSTD-compressed firmware support"
+	select ZSTD_DECOMPRESS
+	help
+	  This option adds the support for ZSTD-compressed files.
+
+endif # FW_LOADER_COMPRESS
 
 config FW_CACHE
 	bool "Enable firmware caching during suspend"
@@ -181,5 +221,19 @@ config FW_CACHE
 
 	  If unsure, say Y.
 
+config FW_UPLOAD
+	bool "Enable users to initiate firmware updates using sysfs"
+	select FW_LOADER_SYSFS
+	select FW_LOADER_PAGED_BUF
+	help
+	  Enabling this option will allow device drivers to expose a persistent
+	  sysfs interface that allows firmware updates to be initiated from
+	  userspace. For example, FPGA based PCIe cards load firmware and FPGA
+	  images from local FLASH when the card boots. The images in FLASH may
+	  be updated with new images provided by the user. Enable this device
+	  to support cards that rely on user-initiated updates for firmware files.
+
+	  If unsure, say N.
+
 endif # FW_LOADER
 endmenu
diff --git a/drivers/base/firmware_loader/Makefile b/drivers/base/firmware_loader/Makefile
index e87843408fe6..60d19f9e0ddc 100644
--- a/drivers/base/firmware_loader/Makefile
+++ b/drivers/base/firmware_loader/Makefile
@@ -6,5 +6,7 @@ obj-$(CONFIG_FW_LOADER)	+= firmware_class.o
 firmware_class-objs := main.o
 firmware_class-$(CONFIG_FW_LOADER_USER_HELPER) += fallback.o
 firmware_class-$(CONFIG_EFI_EMBEDDED_FIRMWARE) += fallback_platform.o
+firmware_class-$(CONFIG_FW_LOADER_SYSFS) += sysfs.o
+firmware_class-$(CONFIG_FW_UPLOAD) += sysfs_upload.o
 
 obj-y += builtin/
diff --git a/drivers/base/firmware_loader/builtin/Makefile b/drivers/base/firmware_loader/builtin/Makefile
index 5fa7ce3745a0..6c067dedc01e 100644
--- a/drivers/base/firmware_loader/builtin/Makefile
+++ b/drivers/base/firmware_loader/builtin/Makefile
@@ -1,14 +1,15 @@
 # SPDX-License-Identifier: GPL-2.0
+obj-y  += main.o
 
 # Create $(fwdir) from $(CONFIG_EXTRA_FIRMWARE_DIR) -- if it doesn't have a
 # leading /, it's relative to $(srctree).
-fwdir := $(subst $(quote),,$(CONFIG_EXTRA_FIRMWARE_DIR))
+fwdir := $(CONFIG_EXTRA_FIRMWARE_DIR)
 fwdir := $(addprefix $(srctree)/,$(filter-out /%,$(fwdir)))$(filter /%,$(fwdir))
 
-obj-y  := $(addsuffix .gen.o, $(subst $(quote),,$(CONFIG_EXTRA_FIRMWARE)))
+firmware  := $(addsuffix .gen.o, $(CONFIG_EXTRA_FIRMWARE))
+obj-y += $(firmware)
 
 FWNAME    = $(patsubst $(obj)/%.gen.S,%,$@)
-comma     := ,
 FWSTR     = $(subst $(comma),_,$(subst /,_,$(subst .,_,$(subst -,_,$(FWNAME)))))
 ASM_WORD  = $(if $(CONFIG_64BIT),.quad,.long)
 ASM_ALIGN = $(if $(CONFIG_64BIT),3,2)
@@ -35,7 +36,7 @@ $(obj)/%.gen.S: FORCE
 	$(call filechk,fwbin)
 
 # The .o files depend on the binaries directly; the .S files don't.
-$(addprefix $(obj)/, $(obj-y)): $(obj)/%.gen.o: $(fwdir)/%
+$(addprefix $(obj)/, $(firmware)): $(obj)/%.gen.o: $(fwdir)/%
 
 targets := $(patsubst $(obj)/%,%, \
                                 $(shell find $(obj) -name \*.gen.S 2>/dev/null))
diff --git a/drivers/base/firmware_loader/builtin/main.c b/drivers/base/firmware_loader/builtin/main.c
new file mode 100644
index 000000000000..d36befebb1b9
--- /dev/null
+++ b/drivers/base/firmware_loader/builtin/main.c
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Builtin firmware support */
+
+#include <linux/firmware.h>
+#include "../firmware.h"
+
+/* Only if FW_LOADER=y */
+#ifdef CONFIG_FW_LOADER
+
+struct builtin_fw {
+	char *name;
+	void *data;
+	unsigned long size;
+};
+
+extern struct builtin_fw __start_builtin_fw[];
+extern struct builtin_fw __end_builtin_fw[];
+
+static bool fw_copy_to_prealloc_buf(struct firmware *fw,
+				    void *buf, size_t size)
+{
+	if (!buf)
+		return true;
+	if (size < fw->size)
+		return false;
+	memcpy(buf, fw->data, fw->size);
+	return true;
+}
+
+/**
+ * firmware_request_builtin() - load builtin firmware
+ * @fw: pointer to firmware struct
+ * @name: name of firmware file
+ *
+ * Some use cases in the kernel have a requirement so that no memory allocator
+ * is involved as these calls take place early in boot process. An example is
+ * the x86 CPU microcode loader. In these cases all the caller wants is to see
+ * if the firmware was built-in and if so use it right away. This can be used
+ * for such cases.
+ *
+ * This looks for the firmware in the built-in kernel. Only if the kernel was
+ * built-in with the firmware you are looking for will this return successfully.
+ *
+ * Callers of this API do not need to use release_firmware() as the pointer to
+ * the firmware is expected to be provided locally on the stack of the caller.
+ **/
+bool firmware_request_builtin(struct firmware *fw, const char *name)
+{
+	struct builtin_fw *b_fw;
+
+	if (!fw)
+		return false;
+
+	for (b_fw = __start_builtin_fw; b_fw != __end_builtin_fw; b_fw++) {
+		if (strcmp(name, b_fw->name) == 0) {
+			fw->size = b_fw->size;
+			fw->data = b_fw->data;
+			return true;
+		}
+	}
+
+	return false;
+}
+EXPORT_SYMBOL_NS_GPL(firmware_request_builtin, "TEST_FIRMWARE");
+
+/**
+ * firmware_request_builtin_buf() - load builtin firmware into optional buffer
+ * @fw: pointer to firmware struct
+ * @name: name of firmware file
+ * @buf: If set this lets you use a pre-allocated buffer so that the built-in
+ *	firmware into is copied into. This field can be NULL. It is used by
+ *	callers such as request_firmware_into_buf() and
+ *	request_partial_firmware_into_buf()
+ * @size: if buf was provided, the max size of the allocated buffer available.
+ *	If the built-in firmware does not fit into the pre-allocated @buf this
+ *	call will fail.
+ *
+ * This looks for the firmware in the built-in kernel. Only if the kernel was
+ * built-in with the firmware you are looking for will this call possibly
+ * succeed. If you passed a @buf the firmware will be copied into it *iff* the
+ * built-in firmware fits into the pre-allocated buffer size specified in
+ * @size.
+ *
+ * This caller is to be used internally by the firmware_loader only.
+ **/
+bool firmware_request_builtin_buf(struct firmware *fw, const char *name,
+				  void *buf, size_t size)
+{
+	if (!firmware_request_builtin(fw, name))
+		return false;
+
+	return fw_copy_to_prealloc_buf(fw, buf, size);
+}
+
+bool firmware_is_builtin(const struct firmware *fw)
+{
+	struct builtin_fw *b_fw;
+
+	for (b_fw = __start_builtin_fw; b_fw != __end_builtin_fw; b_fw++)
+		if (fw->data == b_fw->data)
+			return true;
+
+	return false;
+}
+
+#endif
diff --git a/drivers/base/firmware_loader/fallback.c b/drivers/base/firmware_loader/fallback.c
index 1e9c96e3ed63..3ef0b312ae71 100644
--- a/drivers/base/firmware_loader/fallback.c
+++ b/drivers/base/firmware_loader/fallback.c
@@ -3,12 +3,10 @@
 #include <linux/types.h>
 #include <linux/kconfig.h>
 #include <linux/list.h>
-#include <linux/slab.h>
 #include <linux/security.h>
-#include <linux/highmem.h>
 #include <linux/umh.h>
 #include <linux/sysctl.h>
-#include <linux/vmalloc.h>
+#include <linux/module.h>
 
 #include "fallback.h"
 #include "firmware.h"
@@ -17,20 +15,6 @@
  * firmware fallback mechanism
  */
 
-extern struct firmware_fallback_config fw_fallback_config;
-
-/* These getters are vetted to use int properly */
-static inline int __firmware_loading_timeout(void)
-{
-	return fw_fallback_config.loading_timeout;
-}
-
-/* These setters are vetted to use int properly */
-static void __fw_fallback_set_timeout(int timeout)
-{
-	fw_fallback_config.loading_timeout = timeout;
-}
-
 /*
  * use small loading timeout for caching devices' firmware because all these
  * firmware images have been loaded successfully at lease once, also system is
@@ -55,56 +39,14 @@ static long firmware_loading_timeout(void)
 		__firmware_loading_timeout() * HZ : MAX_JIFFY_OFFSET;
 }
 
-static inline bool fw_sysfs_done(struct fw_priv *fw_priv)
-{
-	return __fw_state_check(fw_priv, FW_STATUS_DONE);
-}
-
-static inline bool fw_sysfs_loading(struct fw_priv *fw_priv)
-{
-	return __fw_state_check(fw_priv, FW_STATUS_LOADING);
-}
-
 static inline int fw_sysfs_wait_timeout(struct fw_priv *fw_priv,  long timeout)
 {
 	return __fw_state_wait_common(fw_priv, timeout);
 }
 
-struct fw_sysfs {
-	bool nowait;
-	struct device dev;
-	struct fw_priv *fw_priv;
-	struct firmware *fw;
-};
-
-static struct fw_sysfs *to_fw_sysfs(struct device *dev)
-{
-	return container_of(dev, struct fw_sysfs, dev);
-}
-
-static void __fw_load_abort(struct fw_priv *fw_priv)
-{
-	/*
-	 * There is a small window in which user can write to 'loading'
-	 * between loading done and disappearance of 'loading'
-	 */
-	if (fw_sysfs_done(fw_priv))
-		return;
-
-	list_del_init(&fw_priv->pending_list);
-	fw_state_aborted(fw_priv);
-}
-
-static void fw_load_abort(struct fw_sysfs *fw_sysfs)
-{
-	struct fw_priv *fw_priv = fw_sysfs->fw_priv;
-
-	__fw_load_abort(fw_priv);
-}
-
 static LIST_HEAD(pending_fw_head);
 
-void kill_pending_fw_fallback_reqs(bool only_kill_custom)
+void kill_pending_fw_fallback_reqs(bool kill_all)
 {
 	struct fw_priv *fw_priv;
 	struct fw_priv *next;
@@ -112,388 +54,24 @@ void kill_pending_fw_fallback_reqs(bool only_kill_custom)
 	mutex_lock(&fw_lock);
 	list_for_each_entry_safe(fw_priv, next, &pending_fw_head,
 				 pending_list) {
-		if (!fw_priv->need_uevent || !only_kill_custom)
+		if (kill_all || !fw_priv->need_uevent)
 			 __fw_load_abort(fw_priv);
 	}
-	mutex_unlock(&fw_lock);
-}
-
-static ssize_t timeout_show(struct class *class, struct class_attribute *attr,
-			    char *buf)
-{
-	return sprintf(buf, "%d\n", __firmware_loading_timeout());
-}
-
-/**
- * firmware_timeout_store() - set number of seconds to wait for firmware
- * @class: device class pointer
- * @attr: device attribute pointer
- * @buf: buffer to scan for timeout value
- * @count: number of bytes in @buf
- *
- *	Sets the number of seconds to wait for the firmware.  Once
- *	this expires an error will be returned to the driver and no
- *	firmware will be provided.
- *
- *	Note: zero means 'wait forever'.
- **/
-static ssize_t timeout_store(struct class *class, struct class_attribute *attr,
-			     const char *buf, size_t count)
-{
-	int tmp_loading_timeout = simple_strtol(buf, NULL, 10);
 
-	if (tmp_loading_timeout < 0)
-		tmp_loading_timeout = 0;
+	if (kill_all)
+		fw_load_abort_all = true;
 
-	__fw_fallback_set_timeout(tmp_loading_timeout);
-
-	return count;
-}
-static CLASS_ATTR_RW(timeout);
-
-static struct attribute *firmware_class_attrs[] = {
-	&class_attr_timeout.attr,
-	NULL,
-};
-ATTRIBUTE_GROUPS(firmware_class);
-
-static void fw_dev_release(struct device *dev)
-{
-	struct fw_sysfs *fw_sysfs = to_fw_sysfs(dev);
-
-	kfree(fw_sysfs);
-}
-
-static int do_firmware_uevent(struct fw_sysfs *fw_sysfs, struct kobj_uevent_env *env)
-{
-	if (add_uevent_var(env, "FIRMWARE=%s", fw_sysfs->fw_priv->fw_name))
-		return -ENOMEM;
-	if (add_uevent_var(env, "TIMEOUT=%i", __firmware_loading_timeout()))
-		return -ENOMEM;
-	if (add_uevent_var(env, "ASYNC=%d", fw_sysfs->nowait))
-		return -ENOMEM;
-
-	return 0;
-}
-
-static int firmware_uevent(struct device *dev, struct kobj_uevent_env *env)
-{
-	struct fw_sysfs *fw_sysfs = to_fw_sysfs(dev);
-	int err = 0;
-
-	mutex_lock(&fw_lock);
-	if (fw_sysfs->fw_priv)
-		err = do_firmware_uevent(fw_sysfs, env);
-	mutex_unlock(&fw_lock);
-	return err;
-}
-
-static struct class firmware_class = {
-	.name		= "firmware",
-	.class_groups	= firmware_class_groups,
-	.dev_uevent	= firmware_uevent,
-	.dev_release	= fw_dev_release,
-};
-
-int register_sysfs_loader(void)
-{
-	return class_register(&firmware_class);
-}
-
-void unregister_sysfs_loader(void)
-{
-	class_unregister(&firmware_class);
-}
-
-static ssize_t firmware_loading_show(struct device *dev,
-				     struct device_attribute *attr, char *buf)
-{
-	struct fw_sysfs *fw_sysfs = to_fw_sysfs(dev);
-	int loading = 0;
-
-	mutex_lock(&fw_lock);
-	if (fw_sysfs->fw_priv)
-		loading = fw_sysfs_loading(fw_sysfs->fw_priv);
 	mutex_unlock(&fw_lock);
-
-	return sprintf(buf, "%d\n", loading);
-}
-
-/**
- * firmware_loading_store() - set value in the 'loading' control file
- * @dev: device pointer
- * @attr: device attribute pointer
- * @buf: buffer to scan for loading control value
- * @count: number of bytes in @buf
- *
- *	The relevant values are:
- *
- *	 1: Start a load, discarding any previous partial load.
- *	 0: Conclude the load and hand the data to the driver code.
- *	-1: Conclude the load with an error and discard any written data.
- **/
-static ssize_t firmware_loading_store(struct device *dev,
-				      struct device_attribute *attr,
-				      const char *buf, size_t count)
-{
-	struct fw_sysfs *fw_sysfs = to_fw_sysfs(dev);
-	struct fw_priv *fw_priv;
-	ssize_t written = count;
-	int loading = simple_strtol(buf, NULL, 10);
-
-	mutex_lock(&fw_lock);
-	fw_priv = fw_sysfs->fw_priv;
-	if (fw_state_is_aborted(fw_priv))
-		goto out;
-
-	switch (loading) {
-	case 1:
-		/* discarding any previous partial load */
-		if (!fw_sysfs_done(fw_priv)) {
-			fw_free_paged_buf(fw_priv);
-			fw_state_start(fw_priv);
-		}
-		break;
-	case 0:
-		if (fw_sysfs_loading(fw_priv)) {
-			int rc;
-
-			/*
-			 * Several loading requests may be pending on
-			 * one same firmware buf, so let all requests
-			 * see the mapped 'buf->data' once the loading
-			 * is completed.
-			 * */
-			rc = fw_map_paged_buf(fw_priv);
-			if (rc)
-				dev_err(dev, "%s: map pages failed\n",
-					__func__);
-			else
-				rc = security_kernel_post_read_file(NULL,
-						fw_priv->data, fw_priv->size,
-						READING_FIRMWARE);
-
-			/*
-			 * Same logic as fw_load_abort, only the DONE bit
-			 * is ignored and we set ABORT only on failure.
-			 */
-			list_del_init(&fw_priv->pending_list);
-			if (rc) {
-				fw_state_aborted(fw_priv);
-				written = rc;
-			} else {
-				fw_state_done(fw_priv);
-			}
-			break;
-		}
-		/* fallthrough */
-	default:
-		dev_err(dev, "%s: unexpected value (%d)\n", __func__, loading);
-		/* fallthrough */
-	case -1:
-		fw_load_abort(fw_sysfs);
-		break;
-	}
-out:
-	mutex_unlock(&fw_lock);
-	return written;
-}
-
-static DEVICE_ATTR(loading, 0644, firmware_loading_show, firmware_loading_store);
-
-static void firmware_rw_data(struct fw_priv *fw_priv, char *buffer,
-			   loff_t offset, size_t count, bool read)
-{
-	if (read)
-		memcpy(buffer, fw_priv->data + offset, count);
-	else
-		memcpy(fw_priv->data + offset, buffer, count);
-}
-
-static void firmware_rw(struct fw_priv *fw_priv, char *buffer,
-			loff_t offset, size_t count, bool read)
-{
-	while (count) {
-		void *page_data;
-		int page_nr = offset >> PAGE_SHIFT;
-		int page_ofs = offset & (PAGE_SIZE-1);
-		int page_cnt = min_t(size_t, PAGE_SIZE - page_ofs, count);
-
-		page_data = kmap(fw_priv->pages[page_nr]);
-
-		if (read)
-			memcpy(buffer, page_data + page_ofs, page_cnt);
-		else
-			memcpy(page_data + page_ofs, buffer, page_cnt);
-
-		kunmap(fw_priv->pages[page_nr]);
-		buffer += page_cnt;
-		offset += page_cnt;
-		count -= page_cnt;
-	}
-}
-
-static ssize_t firmware_data_read(struct file *filp, struct kobject *kobj,
-				  struct bin_attribute *bin_attr,
-				  char *buffer, loff_t offset, size_t count)
-{
-	struct device *dev = kobj_to_dev(kobj);
-	struct fw_sysfs *fw_sysfs = to_fw_sysfs(dev);
-	struct fw_priv *fw_priv;
-	ssize_t ret_count;
-
-	mutex_lock(&fw_lock);
-	fw_priv = fw_sysfs->fw_priv;
-	if (!fw_priv || fw_sysfs_done(fw_priv)) {
-		ret_count = -ENODEV;
-		goto out;
-	}
-	if (offset > fw_priv->size) {
-		ret_count = 0;
-		goto out;
-	}
-	if (count > fw_priv->size - offset)
-		count = fw_priv->size - offset;
-
-	ret_count = count;
-
-	if (fw_priv->data)
-		firmware_rw_data(fw_priv, buffer, offset, count, true);
-	else
-		firmware_rw(fw_priv, buffer, offset, count, true);
-
-out:
-	mutex_unlock(&fw_lock);
-	return ret_count;
-}
-
-static int fw_realloc_pages(struct fw_sysfs *fw_sysfs, int min_size)
-{
-	int err;
-
-	err = fw_grow_paged_buf(fw_sysfs->fw_priv,
-				PAGE_ALIGN(min_size) >> PAGE_SHIFT);
-	if (err)
-		fw_load_abort(fw_sysfs);
-	return err;
-}
-
-/**
- * firmware_data_write() - write method for firmware
- * @filp: open sysfs file
- * @kobj: kobject for the device
- * @bin_attr: bin_attr structure
- * @buffer: buffer being written
- * @offset: buffer offset for write in total data store area
- * @count: buffer size
- *
- *	Data written to the 'data' attribute will be later handed to
- *	the driver as a firmware image.
- **/
-static ssize_t firmware_data_write(struct file *filp, struct kobject *kobj,
-				   struct bin_attribute *bin_attr,
-				   char *buffer, loff_t offset, size_t count)
-{
-	struct device *dev = kobj_to_dev(kobj);
-	struct fw_sysfs *fw_sysfs = to_fw_sysfs(dev);
-	struct fw_priv *fw_priv;
-	ssize_t retval;
-
-	if (!capable(CAP_SYS_RAWIO))
-		return -EPERM;
-
-	mutex_lock(&fw_lock);
-	fw_priv = fw_sysfs->fw_priv;
-	if (!fw_priv || fw_sysfs_done(fw_priv)) {
-		retval = -ENODEV;
-		goto out;
-	}
-
-	if (fw_priv->data) {
-		if (offset + count > fw_priv->allocated_size) {
-			retval = -ENOMEM;
-			goto out;
-		}
-		firmware_rw_data(fw_priv, buffer, offset, count, false);
-		retval = count;
-	} else {
-		retval = fw_realloc_pages(fw_sysfs, offset + count);
-		if (retval)
-			goto out;
-
-		retval = count;
-		firmware_rw(fw_priv, buffer, offset, count, false);
-	}
-
-	fw_priv->size = max_t(size_t, offset + count, fw_priv->size);
-out:
-	mutex_unlock(&fw_lock);
-	return retval;
-}
-
-static struct bin_attribute firmware_attr_data = {
-	.attr = { .name = "data", .mode = 0644 },
-	.size = 0,
-	.read = firmware_data_read,
-	.write = firmware_data_write,
-};
-
-static struct attribute *fw_dev_attrs[] = {
-	&dev_attr_loading.attr,
-	NULL
-};
-
-static struct bin_attribute *fw_dev_bin_attrs[] = {
-	&firmware_attr_data,
-	NULL
-};
-
-static const struct attribute_group fw_dev_attr_group = {
-	.attrs = fw_dev_attrs,
-	.bin_attrs = fw_dev_bin_attrs,
-};
-
-static const struct attribute_group *fw_dev_attr_groups[] = {
-	&fw_dev_attr_group,
-	NULL
-};
-
-static struct fw_sysfs *
-fw_create_instance(struct firmware *firmware, const char *fw_name,
-		   struct device *device, enum fw_opt opt_flags)
-{
-	struct fw_sysfs *fw_sysfs;
-	struct device *f_dev;
-
-	fw_sysfs = kzalloc(sizeof(*fw_sysfs), GFP_KERNEL);
-	if (!fw_sysfs) {
-		fw_sysfs = ERR_PTR(-ENOMEM);
-		goto exit;
-	}
-
-	fw_sysfs->nowait = !!(opt_flags & FW_OPT_NOWAIT);
-	fw_sysfs->fw = firmware;
-	f_dev = &fw_sysfs->dev;
-
-	device_initialize(f_dev);
-	dev_set_name(f_dev, "%s", fw_name);
-	f_dev->parent = device;
-	f_dev->class = &firmware_class;
-	f_dev->groups = fw_dev_attr_groups;
-exit:
-	return fw_sysfs;
 }
 
 /**
  * fw_load_sysfs_fallback() - load a firmware via the sysfs fallback mechanism
  * @fw_sysfs: firmware sysfs information for the firmware to load
- * @opt_flags: flags of options, FW_OPT_*
  * @timeout: timeout to wait for the load
  *
  * In charge of constructing a sysfs fallback interface for firmware loading.
  **/
-static int fw_load_sysfs_fallback(struct fw_sysfs *fw_sysfs,
-				  enum fw_opt opt_flags, long timeout)
+static int fw_load_sysfs_fallback(struct fw_sysfs *fw_sysfs, long timeout)
 {
 	int retval = 0;
 	struct device *f_dev = &fw_sysfs->dev;
@@ -512,10 +90,15 @@ static int fw_load_sysfs_fallback(struct fw_sysfs *fw_sysfs,
 	}
 
 	mutex_lock(&fw_lock);
+	if (fw_load_abort_all || fw_state_is_aborted(fw_priv)) {
+		mutex_unlock(&fw_lock);
+		retval = -EINTR;
+		goto out;
+	}
 	list_add(&fw_priv->pending_list, &pending_fw_head);
 	mutex_unlock(&fw_lock);
 
-	if (opt_flags & FW_OPT_UEVENT) {
+	if (fw_priv->opt_flags & FW_OPT_UEVENT) {
 		fw_priv->need_uevent = true;
 		dev_set_uevent_suppress(f_dev, false);
 		dev_dbg(f_dev, "firmware: requesting %s\n", fw_priv->fw_name);
@@ -534,11 +117,10 @@ static int fw_load_sysfs_fallback(struct fw_sysfs *fw_sysfs,
 	if (fw_state_is_aborted(fw_priv)) {
 		if (retval == -ERESTARTSYS)
 			retval = -EINTR;
-		else
-			retval = -EAGAIN;
 	} else if (fw_priv->is_paged_buf && !fw_priv->data)
 		retval = -ENOMEM;
 
+out:
 	device_del(f_dev);
 err_put_dev:
 	put_device(f_dev);
@@ -547,7 +129,7 @@ err_put_dev:
 
 static int fw_load_from_user_helper(struct firmware *firmware,
 				    const char *name, struct device *device,
-				    enum fw_opt opt_flags)
+				    u32 opt_flags)
 {
 	struct fw_sysfs *fw_sysfs;
 	long timeout;
@@ -577,10 +159,10 @@ static int fw_load_from_user_helper(struct firmware *firmware,
 	}
 
 	fw_sysfs->fw_priv = firmware->priv;
-	ret = fw_load_sysfs_fallback(fw_sysfs, opt_flags, timeout);
+	ret = fw_load_sysfs_fallback(fw_sysfs, timeout);
 
 	if (!ret)
-		ret = assign_fw(firmware, device, opt_flags);
+		ret = assign_fw(firmware, device);
 
 out_unlock:
 	usermodehelper_read_unlock();
@@ -588,7 +170,7 @@ out_unlock:
 	return ret;
 }
 
-static bool fw_force_sysfs_fallback(enum fw_opt opt_flags)
+static bool fw_force_sysfs_fallback(u32 opt_flags)
 {
 	if (fw_fallback_config.force_sysfs_fallback)
 		return true;
@@ -597,7 +179,7 @@ static bool fw_force_sysfs_fallback(enum fw_opt opt_flags)
 	return true;
 }
 
-static bool fw_run_sysfs_fallback(enum fw_opt opt_flags)
+static bool fw_run_sysfs_fallback(u32 opt_flags)
 {
 	int ret;
 
@@ -610,7 +192,7 @@ static bool fw_run_sysfs_fallback(enum fw_opt opt_flags)
 		return false;
 
 	/* Also permit LSMs and IMA to fail firmware sysfs fallback */
-	ret = security_kernel_load_data(LOADING_FIRMWARE);
+	ret = security_kernel_load_data(LOADING_FIRMWARE, true);
 	if (ret < 0)
 		return false;
 
@@ -622,7 +204,8 @@ static bool fw_run_sysfs_fallback(enum fw_opt opt_flags)
  * @fw: pointer to firmware image
  * @name: name of firmware file to look for
  * @device: device for which firmware is being loaded
- * @opt_flags: options to control firmware loading behaviour
+ * @opt_flags: options to control firmware loading behaviour, as defined by
+ *	       &enum fw_opt
  * @ret: return value from direct lookup which triggered the fallback mechanism
  *
  * This function is called if direct lookup for the firmware failed, it enables
@@ -640,7 +223,7 @@ static bool fw_run_sysfs_fallback(enum fw_opt opt_flags)
  **/
 int firmware_fallback_sysfs(struct firmware *fw, const char *name,
 			    struct device *device,
-			    enum fw_opt opt_flags,
+			    u32 opt_flags,
 			    int ret)
 {
 	if (!fw_run_sysfs_fallback(opt_flags))
diff --git a/drivers/base/firmware_loader/fallback.h b/drivers/base/firmware_loader/fallback.h
index 06f4577733a8..ccf912bef6ca 100644
--- a/drivers/base/firmware_loader/fallback.h
+++ b/drivers/base/firmware_loader/fallback.h
@@ -6,71 +6,37 @@
 #include <linux/device.h>
 
 #include "firmware.h"
-
-/**
- * struct firmware_fallback_config - firmware fallback configuration settings
- *
- * Helps describe and fine tune the fallback mechanism.
- *
- * @force_sysfs_fallback: force the sysfs fallback mechanism to be used
- * 	as if one had enabled CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y.
- * 	Useful to help debug a CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y
- * 	functionality on a kernel where that config entry has been disabled.
- * @ignore_sysfs_fallback: force to disable the sysfs fallback mechanism.
- * 	This emulates the behaviour as if we had set the kernel
- * 	config CONFIG_FW_LOADER_USER_HELPER=n.
- * @old_timeout: for internal use
- * @loading_timeout: the timeout to wait for the fallback mechanism before
- * 	giving up, in seconds.
- */
-struct firmware_fallback_config {
-	unsigned int force_sysfs_fallback;
-	unsigned int ignore_sysfs_fallback;
-	int old_timeout;
-	int loading_timeout;
-};
+#include "sysfs.h"
 
 #ifdef CONFIG_FW_LOADER_USER_HELPER
 int firmware_fallback_sysfs(struct firmware *fw, const char *name,
 			    struct device *device,
-			    enum fw_opt opt_flags,
+			    u32 opt_flags,
 			    int ret);
-void kill_pending_fw_fallback_reqs(bool only_kill_custom);
+void kill_pending_fw_fallback_reqs(bool kill_all);
 
 void fw_fallback_set_cache_timeout(void);
 void fw_fallback_set_default_timeout(void);
 
-int register_sysfs_loader(void);
-void unregister_sysfs_loader(void);
 #else /* CONFIG_FW_LOADER_USER_HELPER */
 static inline int firmware_fallback_sysfs(struct firmware *fw, const char *name,
 					  struct device *device,
-					  enum fw_opt opt_flags,
+					  u32 opt_flags,
 					  int ret)
 {
 	/* Keep carrying over the same error */
 	return ret;
 }
 
-static inline void kill_pending_fw_fallback_reqs(bool only_kill_custom) { }
+static inline void kill_pending_fw_fallback_reqs(bool kill_all) { }
 static inline void fw_fallback_set_cache_timeout(void) { }
 static inline void fw_fallback_set_default_timeout(void) { }
-
-static inline int register_sysfs_loader(void)
-{
-	return 0;
-}
-
-static inline void unregister_sysfs_loader(void)
-{
-}
 #endif /* CONFIG_FW_LOADER_USER_HELPER */
 
 #ifdef CONFIG_EFI_EMBEDDED_FIRMWARE
-int firmware_fallback_platform(struct fw_priv *fw_priv, enum fw_opt opt_flags);
+int firmware_fallback_platform(struct fw_priv *fw_priv);
 #else
-static inline int firmware_fallback_platform(struct fw_priv *fw_priv,
-					     enum fw_opt opt_flags)
+static inline int firmware_fallback_platform(struct fw_priv *fw_priv)
 {
 	return -ENOENT;
 }
diff --git a/drivers/base/firmware_loader/fallback_platform.c b/drivers/base/firmware_loader/fallback_platform.c
index c88c745590fe..00af99f0aff2 100644
--- a/drivers/base/firmware_loader/fallback_platform.c
+++ b/drivers/base/firmware_loader/fallback_platform.c
@@ -8,16 +8,16 @@
 #include "fallback.h"
 #include "firmware.h"
 
-int firmware_fallback_platform(struct fw_priv *fw_priv, enum fw_opt opt_flags)
+int firmware_fallback_platform(struct fw_priv *fw_priv)
 {
 	const u8 *data;
 	size_t size;
 	int rc;
 
-	if (!(opt_flags & FW_OPT_FALLBACK_PLATFORM))
+	if (!(fw_priv->opt_flags & FW_OPT_FALLBACK_PLATFORM))
 		return -ENOENT;
 
-	rc = security_kernel_load_data(LOADING_FIRMWARE_EFI_EMBEDDED);
+	rc = security_kernel_load_data(LOADING_FIRMWARE, true);
 	if (rc)
 		return rc;
 
@@ -25,7 +25,16 @@ int firmware_fallback_platform(struct fw_priv *fw_priv, enum fw_opt opt_flags)
 	if (rc)
 		return rc; /* rc == -ENOENT when the fw was not found */
 
-	fw_priv->data = vmalloc(size);
+	if (fw_priv->data && size > fw_priv->allocated_size)
+		return -ENOMEM;
+
+	rc = security_kernel_post_load_data((u8 *)data, size, LOADING_FIRMWARE,
+						"platform");
+	if (rc)
+		return rc;
+
+	if (!fw_priv->data)
+		fw_priv->data = vmalloc(size);
 	if (!fw_priv->data)
 		return -ENOMEM;
 
diff --git a/drivers/base/firmware_loader/fallback_table.c b/drivers/base/firmware_loader/fallback_table.c
index a182e318bd09..c8afc501a8a4 100644
--- a/drivers/base/firmware_loader/fallback_table.c
+++ b/drivers/base/firmware_loader/fallback_table.c
@@ -4,6 +4,7 @@
 #include <linux/kconfig.h>
 #include <linux/list.h>
 #include <linux/slab.h>
+#include <linux/export.h>
 #include <linux/security.h>
 #include <linux/highmem.h>
 #include <linux/umh.h>
@@ -21,10 +22,10 @@ struct firmware_fallback_config fw_fallback_config = {
 	.loading_timeout = 60,
 	.old_timeout = 60,
 };
-EXPORT_SYMBOL_GPL(fw_fallback_config);
+EXPORT_SYMBOL_NS_GPL(fw_fallback_config, "FIRMWARE_LOADER_PRIVATE");
 
 #ifdef CONFIG_SYSCTL
-struct ctl_table firmware_config_table[] = {
+static const struct ctl_table firmware_config_table[] = {
 	{
 		.procname	= "force_sysfs_fallback",
 		.data		= &fw_fallback_config.force_sysfs_fallback,
@@ -43,6 +44,25 @@ struct ctl_table firmware_config_table[] = {
 		.extra1		= SYSCTL_ZERO,
 		.extra2		= SYSCTL_ONE,
 	},
-	{ }
 };
-#endif
+
+static struct ctl_table_header *firmware_config_sysct_table_header;
+int register_firmware_config_sysctl(void)
+{
+	firmware_config_sysct_table_header =
+		register_sysctl("kernel/firmware_config",
+				firmware_config_table);
+	if (!firmware_config_sysct_table_header)
+		return -ENOMEM;
+	return 0;
+}
+EXPORT_SYMBOL_NS_GPL(register_firmware_config_sysctl, "FIRMWARE_LOADER_PRIVATE");
+
+void unregister_firmware_config_sysctl(void)
+{
+	unregister_sysctl_table(firmware_config_sysct_table_header);
+	firmware_config_sysct_table_header = NULL;
+}
+EXPORT_SYMBOL_NS_GPL(unregister_firmware_config_sysctl, "FIRMWARE_LOADER_PRIVATE");
+
+#endif /* CONFIG_SYSCTL */
diff --git a/drivers/base/firmware_loader/firmware.h b/drivers/base/firmware_loader/firmware.h
index 25836a6afc9f..e891742ba264 100644
--- a/drivers/base/firmware_loader/firmware.h
+++ b/drivers/base/firmware_loader/firmware.h
@@ -9,8 +9,6 @@
 #include <linux/list.h>
 #include <linux/completion.h>
 
-#include <generated/utsrelease.h>
-
 /**
  * enum fw_opt - options to control firmware loading behaviour
  *
@@ -32,6 +30,8 @@
  * @FW_OPT_FALLBACK_PLATFORM: Enable fallback to device fw copy embedded in
  *	the platform's main firmware. If both this fallback and the sysfs
  *      fallback are enabled, then this fallback will be tried first.
+ * @FW_OPT_PARTIAL: Allow partial read of firmware instead of needing to read
+ *	entire file.
  */
 enum fw_opt {
 	FW_OPT_UEVENT			= BIT(0),
@@ -41,6 +41,7 @@ enum fw_opt {
 	FW_OPT_NOCACHE			= BIT(4),
 	FW_OPT_NOFALLBACK_SYSFS		= BIT(5),
 	FW_OPT_FALLBACK_PLATFORM	= BIT(6),
+	FW_OPT_PARTIAL			= BIT(7),
 };
 
 enum fw_status {
@@ -68,6 +69,8 @@ struct fw_priv {
 	void *data;
 	size_t size;
 	size_t allocated_size;
+	size_t offset;
+	u32 opt_flags;
 #ifdef CONFIG_FW_LOADER_PAGED_BUF
 	bool is_paged_buf;
 	struct page **pages;
@@ -82,6 +85,8 @@ struct fw_priv {
 };
 
 extern struct mutex fw_lock;
+extern struct firmware_cache fw_cache;
+extern bool fw_load_abort_all;
 
 static inline bool __fw_state_check(struct fw_priv *fw_priv,
 				    enum fw_status status)
@@ -112,8 +117,16 @@ static inline void __fw_state_set(struct fw_priv *fw_priv,
 
 	WRITE_ONCE(fw_st->status, status);
 
-	if (status == FW_STATUS_DONE || status == FW_STATUS_ABORTED)
+	if (status == FW_STATUS_DONE || status == FW_STATUS_ABORTED) {
+#ifdef CONFIG_FW_LOADER_USER_HELPER
+		/*
+		 * Doing this here ensures that the fw_priv is deleted from
+		 * the pending list in all abort/done paths.
+		 */
+		list_del_init(&fw_priv->pending_list);
+#endif
 		complete_all(&fw_st->completion);
+	}
 }
 
 static inline void fw_state_aborted(struct fw_priv *fw_priv)
@@ -136,17 +149,50 @@ static inline void fw_state_done(struct fw_priv *fw_priv)
 	__fw_state_set(fw_priv, FW_STATUS_DONE);
 }
 
-int assign_fw(struct firmware *fw, struct device *device,
-	      enum fw_opt opt_flags);
+static inline bool fw_state_is_done(struct fw_priv *fw_priv)
+{
+	return __fw_state_check(fw_priv, FW_STATUS_DONE);
+}
+
+static inline bool fw_state_is_loading(struct fw_priv *fw_priv)
+{
+	return __fw_state_check(fw_priv, FW_STATUS_LOADING);
+}
+
+int alloc_lookup_fw_priv(const char *fw_name, struct firmware_cache *fwc,
+			 struct fw_priv **fw_priv, void *dbuf, size_t size,
+			 size_t offset, u32 opt_flags);
+int assign_fw(struct firmware *fw, struct device *device);
+void free_fw_priv(struct fw_priv *fw_priv);
+void fw_state_init(struct fw_priv *fw_priv);
+
+#ifdef CONFIG_FW_LOADER
+bool firmware_is_builtin(const struct firmware *fw);
+bool firmware_request_builtin_buf(struct firmware *fw, const char *name,
+				  void *buf, size_t size);
+#else /* module case */
+static inline bool firmware_is_builtin(const struct firmware *fw)
+{
+	return false;
+}
+static inline bool firmware_request_builtin_buf(struct firmware *fw,
+						const char *name,
+						void *buf, size_t size)
+{
+	return false;
+}
+#endif
 
 #ifdef CONFIG_FW_LOADER_PAGED_BUF
 void fw_free_paged_buf(struct fw_priv *fw_priv);
 int fw_grow_paged_buf(struct fw_priv *fw_priv, int pages_needed);
 int fw_map_paged_buf(struct fw_priv *fw_priv);
+bool fw_is_paged_buf(struct fw_priv *fw_priv);
 #else
 static inline void fw_free_paged_buf(struct fw_priv *fw_priv) {}
 static inline int fw_grow_paged_buf(struct fw_priv *fw_priv, int pages_needed) { return -ENXIO; }
 static inline int fw_map_paged_buf(struct fw_priv *fw_priv) { return -ENXIO; }
+static inline bool fw_is_paged_buf(struct fw_priv *fw_priv) { return false; }
 #endif
 
 #endif /* __FIRMWARE_LOADER_H */
diff --git a/drivers/base/firmware_loader/main.c b/drivers/base/firmware_loader/main.c
index 76f79913916d..4ebdca9e4da4 100644
--- a/drivers/base/firmware_loader/main.c
+++ b/drivers/base/firmware_loader/main.c
@@ -12,8 +12,10 @@
 
 #include <linux/capability.h>
 #include <linux/device.h>
+#include <linux/kernel_read_file.h>
 #include <linux/module.h>
 #include <linux/init.h>
+#include <linux/initrd.h>
 #include <linux/timer.h>
 #include <linux/vmalloc.h>
 #include <linux/interrupt.h>
@@ -33,6 +35,7 @@
 #include <linux/syscore_ops.h>
 #include <linux/reboot.h>
 #include <linux/security.h>
+#include <linux/zstd.h>
 #include <linux/xz.h>
 
 #include <generated/utsrelease.h>
@@ -89,68 +92,10 @@ static inline struct fw_priv *to_fw_priv(struct kref *ref)
  * guarding for corner cases a global lock should be OK */
 DEFINE_MUTEX(fw_lock);
 
-static struct firmware_cache fw_cache;
+struct firmware_cache fw_cache;
+bool fw_load_abort_all;
 
-/* Builtin firmware support */
-
-#ifdef CONFIG_FW_LOADER
-
-extern struct builtin_fw __start_builtin_fw[];
-extern struct builtin_fw __end_builtin_fw[];
-
-static void fw_copy_to_prealloc_buf(struct firmware *fw,
-				    void *buf, size_t size)
-{
-	if (!buf || size < fw->size)
-		return;
-	memcpy(buf, fw->data, fw->size);
-}
-
-static bool fw_get_builtin_firmware(struct firmware *fw, const char *name,
-				    void *buf, size_t size)
-{
-	struct builtin_fw *b_fw;
-
-	for (b_fw = __start_builtin_fw; b_fw != __end_builtin_fw; b_fw++) {
-		if (strcmp(name, b_fw->name) == 0) {
-			fw->size = b_fw->size;
-			fw->data = b_fw->data;
-			fw_copy_to_prealloc_buf(fw, buf, size);
-
-			return true;
-		}
-	}
-
-	return false;
-}
-
-static bool fw_is_builtin_firmware(const struct firmware *fw)
-{
-	struct builtin_fw *b_fw;
-
-	for (b_fw = __start_builtin_fw; b_fw != __end_builtin_fw; b_fw++)
-		if (fw->data == b_fw->data)
-			return true;
-
-	return false;
-}
-
-#else /* Module case - no builtin firmware support */
-
-static inline bool fw_get_builtin_firmware(struct firmware *fw,
-					   const char *name, void *buf,
-					   size_t size)
-{
-	return false;
-}
-
-static inline bool fw_is_builtin_firmware(const struct firmware *fw)
-{
-	return false;
-}
-#endif
-
-static void fw_state_init(struct fw_priv *fw_priv)
+void fw_state_init(struct fw_priv *fw_priv)
 {
 	struct fw_state *fw_st = &fw_priv->fw_st;
 
@@ -163,14 +108,25 @@ static inline int fw_state_wait(struct fw_priv *fw_priv)
 	return __fw_state_wait_common(fw_priv, MAX_SCHEDULE_TIMEOUT);
 }
 
-static int fw_cache_piggyback_on_request(const char *name);
+static void fw_cache_piggyback_on_request(struct fw_priv *fw_priv);
 
 static struct fw_priv *__allocate_fw_priv(const char *fw_name,
 					  struct firmware_cache *fwc,
-					  void *dbuf, size_t size)
+					  void *dbuf,
+					  size_t size,
+					  size_t offset,
+					  u32 opt_flags)
 {
 	struct fw_priv *fw_priv;
 
+	/* For a partial read, the buffer must be preallocated. */
+	if ((opt_flags & FW_OPT_PARTIAL) && !dbuf)
+		return NULL;
+
+	/* Only partial reads are allowed to use an offset. */
+	if (offset != 0 && !(opt_flags & FW_OPT_PARTIAL))
+		return NULL;
+
 	fw_priv = kzalloc(sizeof(*fw_priv), GFP_ATOMIC);
 	if (!fw_priv)
 		return NULL;
@@ -185,6 +141,8 @@ static struct fw_priv *__allocate_fw_priv(const char *fw_name,
 	fw_priv->fwc = fwc;
 	fw_priv->data = dbuf;
 	fw_priv->allocated_size = size;
+	fw_priv->offset = offset;
+	fw_priv->opt_flags = opt_flags;
 	fw_state_init(fw_priv);
 #ifdef CONFIG_FW_LOADER_USER_HELPER
 	INIT_LIST_HEAD(&fw_priv->pending_list);
@@ -207,15 +165,18 @@ static struct fw_priv *__lookup_fw_priv(const char *fw_name)
 }
 
 /* Returns 1 for batching firmware requests with the same name */
-static int alloc_lookup_fw_priv(const char *fw_name,
-				struct firmware_cache *fwc,
-				struct fw_priv **fw_priv, void *dbuf,
-				size_t size, enum fw_opt opt_flags)
+int alloc_lookup_fw_priv(const char *fw_name, struct firmware_cache *fwc,
+			 struct fw_priv **fw_priv, void *dbuf, size_t size,
+			 size_t offset, u32 opt_flags)
 {
 	struct fw_priv *tmp;
 
 	spin_lock(&fwc->lock);
-	if (!(opt_flags & FW_OPT_NOCACHE)) {
+	/*
+	 * Do not merge requests that are marked to be non-cached or
+	 * are performing partial reads.
+	 */
+	if (!(opt_flags & (FW_OPT_NOCACHE | FW_OPT_PARTIAL))) {
 		tmp = __lookup_fw_priv(fw_name);
 		if (tmp) {
 			kref_get(&tmp->ref);
@@ -226,7 +187,7 @@ static int alloc_lookup_fw_priv(const char *fw_name,
 		}
 	}
 
-	tmp = __allocate_fw_priv(fw_name, fwc, dbuf, size);
+	tmp = __allocate_fw_priv(fw_name, fwc, dbuf, size, offset, opt_flags);
 	if (tmp) {
 		INIT_LIST_HEAD(&tmp->list);
 		if (!(opt_flags & FW_OPT_NOCACHE))
@@ -252,14 +213,16 @@ static void __free_fw_priv(struct kref *ref)
 	list_del(&fw_priv->list);
 	spin_unlock(&fwc->lock);
 
-	fw_free_paged_buf(fw_priv); /* free leftover pages */
-	if (!fw_priv->allocated_size)
+	if (fw_is_paged_buf(fw_priv))
+		fw_free_paged_buf(fw_priv);
+	else if (!fw_priv->allocated_size)
 		vfree(fw_priv->data);
+
 	kfree_const(fw_priv->fw_name);
 	kfree(fw_priv);
 }
 
-static void free_fw_priv(struct fw_priv *fw_priv)
+void free_fw_priv(struct fw_priv *fw_priv)
 {
 	struct firmware_cache *fwc = fw_priv->fwc;
 	spin_lock(&fwc->lock);
@@ -268,6 +231,11 @@ static void free_fw_priv(struct fw_priv *fw_priv)
 }
 
 #ifdef CONFIG_FW_LOADER_PAGED_BUF
+bool fw_is_paged_buf(struct fw_priv *fw_priv)
+{
+	return fw_priv->is_paged_buf;
+}
+
 void fw_free_paged_buf(struct fw_priv *fw_priv)
 {
 	int i;
@@ -275,12 +243,16 @@ void fw_free_paged_buf(struct fw_priv *fw_priv)
 	if (!fw_priv->pages)
 		return;
 
+	vunmap(fw_priv->data);
+
 	for (i = 0; i < fw_priv->nr_pages; i++)
 		__free_page(fw_priv->pages[i]);
 	kvfree(fw_priv->pages);
 	fw_priv->pages = NULL;
 	fw_priv->page_array_size = 0;
 	fw_priv->nr_pages = 0;
+	fw_priv->data = NULL;
+	fw_priv->size = 0;
 }
 
 int fw_grow_paged_buf(struct fw_priv *fw_priv, int pages_needed)
@@ -328,18 +300,78 @@ int fw_map_paged_buf(struct fw_priv *fw_priv)
 	if (!fw_priv->data)
 		return -ENOMEM;
 
-	/* page table is no longer needed after mapping, let's free */
-	kvfree(fw_priv->pages);
-	fw_priv->pages = NULL;
-
 	return 0;
 }
 #endif
 
 /*
+ * ZSTD-compressed firmware support
+ */
+#ifdef CONFIG_FW_LOADER_COMPRESS_ZSTD
+static int fw_decompress_zstd(struct device *dev, struct fw_priv *fw_priv,
+			      size_t in_size, const void *in_buffer)
+{
+	size_t len, out_size, workspace_size;
+	void *workspace, *out_buf;
+	zstd_dctx *ctx;
+	int err;
+
+	if (fw_priv->allocated_size) {
+		out_size = fw_priv->allocated_size;
+		out_buf = fw_priv->data;
+	} else {
+		zstd_frame_header params;
+
+		if (zstd_get_frame_header(&params, in_buffer, in_size) ||
+		    params.frameContentSize == ZSTD_CONTENTSIZE_UNKNOWN) {
+			dev_dbg(dev, "%s: invalid zstd header\n", __func__);
+			return -EINVAL;
+		}
+		out_size = params.frameContentSize;
+		out_buf = vzalloc(out_size);
+		if (!out_buf)
+			return -ENOMEM;
+	}
+
+	workspace_size = zstd_dctx_workspace_bound();
+	workspace = kvzalloc(workspace_size, GFP_KERNEL);
+	if (!workspace) {
+		err = -ENOMEM;
+		goto error;
+	}
+
+	ctx = zstd_init_dctx(workspace, workspace_size);
+	if (!ctx) {
+		dev_dbg(dev, "%s: failed to initialize context\n", __func__);
+		err = -EINVAL;
+		goto error;
+	}
+
+	len = zstd_decompress_dctx(ctx, out_buf, out_size, in_buffer, in_size);
+	if (zstd_is_error(len)) {
+		dev_dbg(dev, "%s: failed to decompress: %d\n", __func__,
+			zstd_get_error_code(len));
+		err = -EINVAL;
+		goto error;
+	}
+
+	if (!fw_priv->allocated_size)
+		fw_priv->data = out_buf;
+	fw_priv->size = len;
+	err = 0;
+
+ error:
+	kvfree(workspace);
+	if (err && !fw_priv->allocated_size)
+		vfree(out_buf);
+	return err;
+}
+#endif /* CONFIG_FW_LOADER_COMPRESS_ZSTD */
+
+/*
  * XZ-compressed firmware support
  */
-#ifdef CONFIG_FW_LOADER_COMPRESS
+#ifdef CONFIG_FW_LOADER_COMPRESS_XZ
 /* show an error and return the standard error code */
 static int fw_decompress_xz_error(struct device *dev, enum xz_ret xz_ret)
 {
@@ -404,11 +436,11 @@ static int fw_decompress_xz_pages(struct device *dev, struct fw_priv *fw_priv,
 
 		/* decompress onto the new allocated page */
 		page = fw_priv->pages[fw_priv->nr_pages - 1];
-		xz_buf.out = kmap(page);
+		xz_buf.out = kmap_local_page(page);
 		xz_buf.out_pos = 0;
 		xz_buf.out_size = PAGE_SIZE;
 		xz_ret = xz_dec_run(xz_dec, &xz_buf);
-		kunmap(page);
+		kunmap_local(xz_buf.out);
 		fw_priv->size += xz_buf.out_pos;
 		/* partial decompression means either end or error */
 		if (xz_buf.out_pos != PAGE_SIZE)
@@ -433,7 +465,7 @@ static int fw_decompress_xz(struct device *dev, struct fw_priv *fw_priv,
 	else
 		return fw_decompress_xz_pages(dev, fw_priv, in_size, in_buffer);
 }
-#endif /* CONFIG_FW_LOADER_COMPRESS */
+#endif /* CONFIG_FW_LOADER_COMPRESS_XZ */
 
 /* direct firmware loading support */
 static char fw_path_para[256];
@@ -461,18 +493,16 @@ fw_get_filesystem_firmware(struct device *device, struct fw_priv *fw_priv,
 					     size_t in_size,
 					     const void *in_buffer))
 {
-	loff_t size;
-	int i, len;
+	size_t size;
+	int i, len, maxlen = 0;
 	int rc = -ENOENT;
-	char *path;
-	enum kernel_read_file_id id = READING_FIRMWARE;
+	char *path, *nt = NULL;
 	size_t msize = INT_MAX;
 	void *buffer = NULL;
 
 	/* Already populated data member means we're loading into a buffer */
 	if (!decompress && fw_priv->data) {
 		buffer = fw_priv->data;
-		id = READING_FIRMWARE_PREALLOC_BUFFER;
 		msize = fw_priv->allocated_size;
 	}
 
@@ -480,13 +510,26 @@ fw_get_filesystem_firmware(struct device *device, struct fw_priv *fw_priv,
 	if (!path)
 		return -ENOMEM;
 
+	wait_for_initramfs();
 	for (i = 0; i < ARRAY_SIZE(fw_path); i++) {
+		size_t file_size = 0;
+		size_t *file_size_ptr = NULL;
+
 		/* skip the unset customized path */
 		if (!fw_path[i][0])
 			continue;
 
-		len = snprintf(path, PATH_MAX, "%s/%s%s",
-			       fw_path[i], fw_priv->fw_name, suffix);
+		/* strip off \n from customized path */
+		maxlen = strlen(fw_path[i]);
+		if (i == 0) {
+			nt = strchr(fw_path[i], '\n');
+			if (nt)
+				maxlen = nt - fw_path[i];
+		}
+
+		len = snprintf(path, PATH_MAX, "%.*s/%s%s",
+			       maxlen, fw_path[i],
+			       fw_priv->fw_name, suffix);
 		if (len >= PATH_MAX) {
 			rc = -ENAMETOOLONG;
 			break;
@@ -494,18 +537,35 @@ fw_get_filesystem_firmware(struct device *device, struct fw_priv *fw_priv,
 
 		fw_priv->size = 0;
 
+		/*
+		 * The total file size is only examined when doing a partial
+		 * read; the "full read" case needs to fail if the whole
+		 * firmware was not completely loaded.
+		 */
+		if ((fw_priv->opt_flags & FW_OPT_PARTIAL) && buffer)
+			file_size_ptr = &file_size;
+
 		/* load firmware files from the mount namespace of init */
-		rc = kernel_read_file_from_path_initns(path, &buffer,
-						       &size, msize, id);
-		if (rc) {
-			if (rc != -ENOENT)
-				dev_warn(device, "loading %s failed with error %d\n",
-					 path, rc);
-			else
-				dev_dbg(device, "loading %s failed for no such file or directory.\n",
-					 path);
+		rc = kernel_read_file_from_path_initns(path, fw_priv->offset,
+						       &buffer, msize,
+						       file_size_ptr,
+						       READING_FIRMWARE);
+		if (rc < 0) {
+			if (!(fw_priv->opt_flags & FW_OPT_NO_WARN)) {
+				if (rc != -ENOENT)
+					dev_warn(device,
+						 "loading %s failed with error %d\n",
+						 path, rc);
+				else
+					dev_dbg(device,
+						"loading %s failed for no such file or directory.\n",
+						path);
+			}
 			continue;
 		}
+		size = rc;
+		rc = 0;
+
 		dev_dbg(device, "Loading firmware from %s\n", path);
 		if (decompress) {
 			dev_dbg(device, "f/w decompressing %s\n",
@@ -548,9 +608,6 @@ static void firmware_free_data(const struct firmware *fw)
 static void fw_set_page_data(struct fw_priv *fw_priv, struct firmware *fw)
 {
 	fw->priv = fw_priv;
-#ifdef CONFIG_FW_LOADER_USER_HELPER
-	fw->pages = fw_priv->pages;
-#endif
 	fw->size = fw_priv->size;
 	fw->data = fw_priv->data;
 
@@ -635,8 +692,7 @@ static int fw_add_devm_name(struct device *dev, const char *name)
 }
 #endif
 
-int assign_fw(struct firmware *fw, struct device *device,
-	      enum fw_opt opt_flags)
+int assign_fw(struct firmware *fw, struct device *device)
 {
 	struct fw_priv *fw_priv = fw->priv;
 	int ret;
@@ -655,8 +711,8 @@ int assign_fw(struct firmware *fw, struct device *device,
 	 * should be fixed in devres or driver core.
 	 */
 	/* don't cache firmware handled without uevent */
-	if (device && (opt_flags & FW_OPT_UEVENT) &&
-	    !(opt_flags & FW_OPT_NOCACHE)) {
+	if (device && (fw_priv->opt_flags & FW_OPT_UEVENT) &&
+	    !(fw_priv->opt_flags & FW_OPT_NOCACHE)) {
 		ret = fw_add_devm_name(device, fw_priv->fw_name);
 		if (ret) {
 			mutex_unlock(&fw_lock);
@@ -668,11 +724,9 @@ int assign_fw(struct firmware *fw, struct device *device,
 	 * After caching firmware image is started, let it piggyback
 	 * on request firmware.
 	 */
-	if (!(opt_flags & FW_OPT_NOCACHE) &&
-	    fw_priv->fwc->state == FW_LOADER_START_CACHE) {
-		if (fw_cache_piggyback_on_request(fw_priv->fw_name))
-			kref_get(&fw_priv->ref);
-	}
+	if (!(fw_priv->opt_flags & FW_OPT_NOCACHE) &&
+	    fw_priv->fwc->state == FW_LOADER_START_CACHE)
+		fw_cache_piggyback_on_request(fw_priv);
 
 	/* pass the pages buffer to driver at the last minute */
 	fw_set_page_data(fw_priv, fw);
@@ -687,7 +741,7 @@ int assign_fw(struct firmware *fw, struct device *device,
 static int
 _request_firmware_prepare(struct firmware **firmware_p, const char *name,
 			  struct device *device, void *dbuf, size_t size,
-			  enum fw_opt opt_flags)
+			  size_t offset, u32 opt_flags)
 {
 	struct firmware *firmware;
 	struct fw_priv *fw_priv;
@@ -700,13 +754,13 @@ _request_firmware_prepare(struct firmware **firmware_p, const char *name,
 		return -ENOMEM;
 	}
 
-	if (fw_get_builtin_firmware(firmware, name, dbuf, size)) {
+	if (firmware_request_builtin_buf(firmware, name, dbuf, size)) {
 		dev_dbg(device, "using built-in %s\n", name);
 		return 0; /* assigned */
 	}
 
 	ret = alloc_lookup_fw_priv(name, &fw_cache, &fw_priv, dbuf, size,
-				  opt_flags);
+				   offset, opt_flags);
 
 	/*
 	 * bind with 'priv' now to avoid warning in failure path
@@ -745,17 +799,37 @@ static void fw_abort_batch_reqs(struct firmware *fw)
 		return;
 
 	fw_priv = fw->priv;
+	mutex_lock(&fw_lock);
 	if (!fw_state_is_aborted(fw_priv))
 		fw_state_aborted(fw_priv);
+	mutex_unlock(&fw_lock);
 }
 
+#if defined(CONFIG_FW_LOADER_DEBUG)
+#include <crypto/sha2.h>
+
+static void fw_log_firmware_info(const struct firmware *fw, const char *name, struct device *device)
+{
+	u8 digest[SHA256_DIGEST_SIZE];
+
+	sha256(fw->data, fw->size, digest);
+	dev_dbg(device, "Loaded FW: %s, sha256: %*phN\n",
+		name, SHA256_DIGEST_SIZE, digest);
+}
+#else
+static void fw_log_firmware_info(const struct firmware *fw, const char *name,
+				 struct device *device)
+{}
+#endif
+
 /* called from request_firmware() and request_firmware_work_func() */
 static int
 _request_firmware(const struct firmware **firmware_p, const char *name,
 		  struct device *device, void *buf, size_t size,
-		  enum fw_opt opt_flags)
+		  size_t offset, u32 opt_flags)
 {
 	struct firmware *fw = NULL;
+	bool nondirect = false;
 	int ret;
 
 	if (!firmware_p)
@@ -766,35 +840,75 @@ _request_firmware(const struct firmware **firmware_p, const char *name,
 		goto out;
 	}
 
+
+	/*
+	 * Reject firmware file names with ".." path components.
+	 * There are drivers that construct firmware file names from
+	 * device-supplied strings, and we don't want some device to be
+	 * able to tell us "I would like to be sent my firmware from
+	 * ../../../etc/shadow, please".
+	 *
+	 * This intentionally only looks at the firmware name, not at
+	 * the firmware base directory or at symlink contents.
+	 */
+	if (name_contains_dotdot(name)) {
+		dev_warn(device,
+			 "Firmware load for '%s' refused, path contains '..' component\n",
+			 name);
+		ret = -EINVAL;
+		goto out;
+	}
+
 	ret = _request_firmware_prepare(&fw, name, device, buf, size,
-					opt_flags);
+					offset, opt_flags);
 	if (ret <= 0) /* error or already assigned */
 		goto out;
 
-	ret = fw_get_filesystem_firmware(device, fw->priv, "", NULL);
-#ifdef CONFIG_FW_LOADER_COMPRESS
-	if (ret == -ENOENT)
-		ret = fw_get_filesystem_firmware(device, fw->priv, ".xz",
-						 fw_decompress_xz);
-#endif
+	/*
+	 * We are about to try to access the firmware file. Because we may have been
+	 * called by a driver when serving an unrelated request from userland, we use
+	 * the kernel credentials to read the file.
+	 */
+	scoped_with_kernel_creds() {
+		ret = fw_get_filesystem_firmware(device, fw->priv, "", NULL);
 
-	if (ret == -ENOENT)
-		ret = firmware_fallback_platform(fw->priv, opt_flags);
+		/* Only full reads can support decompression, platform, and sysfs. */
+		if (!(opt_flags & FW_OPT_PARTIAL))
+			nondirect = true;
 
-	if (ret) {
-		if (!(opt_flags & FW_OPT_NO_WARN))
-			dev_warn(device,
-				 "Direct firmware load for %s failed with error %d\n",
-				 name, ret);
-		ret = firmware_fallback_sysfs(fw, name, device, opt_flags, ret);
-	} else
-		ret = assign_fw(fw, device, opt_flags);
+#ifdef CONFIG_FW_LOADER_COMPRESS_ZSTD
+		if (ret == -ENOENT && nondirect)
+			ret = fw_get_filesystem_firmware(device, fw->priv, ".zst",
+							 fw_decompress_zstd);
+#endif
+#ifdef CONFIG_FW_LOADER_COMPRESS_XZ
+		if (ret == -ENOENT && nondirect)
+			ret = fw_get_filesystem_firmware(device, fw->priv, ".xz",
+							 fw_decompress_xz);
+#endif
+		if (ret == -ENOENT && nondirect)
+			ret = firmware_fallback_platform(fw->priv);
 
- out:
+		if (ret) {
+			if (!(opt_flags & FW_OPT_NO_WARN))
+				dev_warn(device,
+					 "Direct firmware load for %s failed with error %d\n",
+					 name, ret);
+			if (nondirect)
+				ret = firmware_fallback_sysfs(fw, name, device,
+							      opt_flags, ret);
+		} else {
+			ret = assign_fw(fw, device);
+		}
+	}
+
+out:
 	if (ret < 0) {
 		fw_abort_batch_reqs(fw);
 		release_firmware(fw);
 		fw = NULL;
+	} else {
+		fw_log_firmware_info(fw, name, device);
 	}
 
 	*firmware_p = fw;
@@ -815,6 +929,8 @@ _request_firmware(const struct firmware **firmware_p, const char *name,
  *      @name will be used as $FIRMWARE in the uevent environment and
  *      should be distinctive enough not to be confused with any other
  *      firmware image for this or any other device.
+ *	It must not contain any ".." path components - "foo/bar..bin" is
+ *	allowed, but "foo/../bar.bin" is not.
  *
  *	Caller must hold the reference count of @device.
  *
@@ -829,7 +945,7 @@ request_firmware(const struct firmware **firmware_p, const char *name,
 
 	/* Need to pin this module until return */
 	__module_get(THIS_MODULE);
-	ret = _request_firmware(firmware_p, name, device, NULL, 0,
+	ret = _request_firmware(firmware_p, name, device, NULL, 0, 0,
 				FW_OPT_UEVENT);
 	module_put(THIS_MODULE);
 	return ret;
@@ -842,12 +958,12 @@ EXPORT_SYMBOL(request_firmware);
  * @name: name of firmware file
  * @device: device for which firmware is being loaded
  *
- * This function is similar in behaviour to request_firmware(), except
- * it doesn't produce warning messages when the file is not found.
- * The sysfs fallback mechanism is enabled if direct filesystem lookup fails,
- * however, however failures to find the firmware file with it are still
- * suppressed. It is therefore up to the driver to check for the return value
- * of this call and to decide when to inform the users of errors.
+ * This function is similar in behaviour to request_firmware(), except it
+ * doesn't produce warning messages when the file is not found. The sysfs
+ * fallback mechanism is enabled if direct filesystem lookup fails. However,
+ * failures to find the firmware file with it are still suppressed. It is
+ * therefore up to the driver to check for the return value of this call and to
+ * decide when to inform the users of errors.
  **/
 int firmware_request_nowarn(const struct firmware **firmware, const char *name,
 			    struct device *device)
@@ -856,7 +972,7 @@ int firmware_request_nowarn(const struct firmware **firmware, const char *name,
 
 	/* Need to pin this module until return */
 	__module_get(THIS_MODULE);
-	ret = _request_firmware(firmware, name, device, NULL, 0,
+	ret = _request_firmware(firmware, name, device, NULL, 0, 0,
 				FW_OPT_UEVENT | FW_OPT_NO_WARN);
 	module_put(THIS_MODULE);
 	return ret;
@@ -880,7 +996,7 @@ int request_firmware_direct(const struct firmware **firmware_p,
 	int ret;
 
 	__module_get(THIS_MODULE);
-	ret = _request_firmware(firmware_p, name, device, NULL, 0,
+	ret = _request_firmware(firmware_p, name, device, NULL, 0, 0,
 				FW_OPT_UEVENT | FW_OPT_NO_WARN |
 				FW_OPT_NOFALLBACK_SYSFS);
 	module_put(THIS_MODULE);
@@ -905,7 +1021,7 @@ int firmware_request_platform(const struct firmware **firmware,
 
 	/* Need to pin this module until return */
 	__module_get(THIS_MODULE);
-	ret = _request_firmware(firmware, name, device, NULL, 0,
+	ret = _request_firmware(firmware, name, device, NULL, 0, 0,
 				FW_OPT_UEVENT | FW_OPT_FALLBACK_PLATFORM);
 	module_put(THIS_MODULE);
 	return ret;
@@ -914,8 +1030,8 @@ EXPORT_SYMBOL_GPL(firmware_request_platform);
 
 /**
  * firmware_request_cache() - cache firmware for suspend so resume can use it
- * @name: name of firmware file
  * @device: device for which firmware should be cached for
+ * @name: name of firmware file
  *
  * There are some devices with an optimization that enables the device to not
  * require loading firmware on system reboot. This optimization may still
@@ -961,7 +1077,7 @@ request_firmware_into_buf(const struct firmware **firmware_p, const char *name,
 		return -EOPNOTSUPP;
 
 	__module_get(THIS_MODULE);
-	ret = _request_firmware(firmware_p, name, device, buf, size,
+	ret = _request_firmware(firmware_p, name, device, buf, size, 0,
 				FW_OPT_UEVENT | FW_OPT_NOCACHE);
 	module_put(THIS_MODULE);
 	return ret;
@@ -969,13 +1085,44 @@ request_firmware_into_buf(const struct firmware **firmware_p, const char *name,
 EXPORT_SYMBOL(request_firmware_into_buf);
 
 /**
+ * request_partial_firmware_into_buf() - load partial firmware into a previously allocated buffer
+ * @firmware_p: pointer to firmware image
+ * @name: name of firmware file
+ * @device: device for which firmware is being loaded and DMA region allocated
+ * @buf: address of buffer to load firmware into
+ * @size: size of buffer
+ * @offset: offset into file to read
+ *
+ * This function works pretty much like request_firmware_into_buf except
+ * it allows a partial read of the file.
+ */
+int
+request_partial_firmware_into_buf(const struct firmware **firmware_p,
+				  const char *name, struct device *device,
+				  void *buf, size_t size, size_t offset)
+{
+	int ret;
+
+	if (fw_cache_is_setup(device, name))
+		return -EOPNOTSUPP;
+
+	__module_get(THIS_MODULE);
+	ret = _request_firmware(firmware_p, name, device, buf, size, offset,
+				FW_OPT_UEVENT | FW_OPT_NOCACHE |
+				FW_OPT_PARTIAL);
+	module_put(THIS_MODULE);
+	return ret;
+}
+EXPORT_SYMBOL(request_partial_firmware_into_buf);
+
+/**
  * release_firmware() - release the resource associated with a firmware image
  * @fw: firmware resource to release
  **/
 void release_firmware(const struct firmware *fw)
 {
 	if (fw) {
-		if (!fw_is_builtin_firmware(fw))
+		if (!firmware_is_builtin(fw))
 			firmware_free_data(fw);
 		kfree(fw);
 	}
@@ -990,7 +1137,7 @@ struct firmware_work {
 	struct device *device;
 	void *context;
 	void (*cont)(const struct firmware *fw, void *context);
-	enum fw_opt opt_flags;
+	u32 opt_flags;
 };
 
 static void request_firmware_work_func(struct work_struct *work)
@@ -1000,7 +1147,7 @@ static void request_firmware_work_func(struct work_struct *work)
 
 	fw_work = container_of(work, struct firmware_work, work);
 
-	_request_firmware(&fw, fw_work->name, fw_work->device, NULL, 0,
+	_request_firmware(&fw, fw_work->name, fw_work->device, NULL, 0, 0,
 			  fw_work->opt_flags);
 	fw_work->cont(fw, fw_work->context);
 	put_device(fw_work->device); /* taken in request_firmware_nowait() */
@@ -1010,34 +1157,11 @@ static void request_firmware_work_func(struct work_struct *work)
 	kfree(fw_work);
 }
 
-/**
- * request_firmware_nowait() - asynchronous version of request_firmware
- * @module: module requesting the firmware
- * @uevent: sends uevent to copy the firmware image if this flag
- *	is non-zero else the firmware copy must be done manually.
- * @name: name of firmware file
- * @device: device for which firmware is being loaded
- * @gfp: allocation flags
- * @context: will be passed over to @cont, and
- *	@fw may be %NULL if firmware request fails.
- * @cont: function will be called asynchronously when the firmware
- *	request is over.
- *
- *	Caller must hold the reference count of @device.
- *
- *	Asynchronous variant of request_firmware() for user contexts:
- *		- sleep for as small periods as possible since it may
- *		  increase kernel boot time of built-in device drivers
- *		  requesting firmware in their ->probe() methods, if
- *		  @gfp is GFP_KERNEL.
- *
- *		- can't sleep at all if @gfp is GFP_ATOMIC.
- **/
-int
-request_firmware_nowait(
+
+static int _request_firmware_nowait(
 	struct module *module, bool uevent,
 	const char *name, struct device *device, gfp_t gfp, void *context,
-	void (*cont)(const struct firmware *fw, void *context))
+	void (*cont)(const struct firmware *fw, void *context), bool nowarn)
 {
 	struct firmware_work *fw_work;
 
@@ -1055,7 +1179,8 @@ request_firmware_nowait(
 	fw_work->context = context;
 	fw_work->cont = cont;
 	fw_work->opt_flags = FW_OPT_NOWAIT |
-		(uevent ? FW_OPT_UEVENT : FW_OPT_USERHELPER);
+		(uevent ? FW_OPT_UEVENT : FW_OPT_USERHELPER) |
+		(nowarn ? FW_OPT_NO_WARN : 0);
 
 	if (!uevent && fw_cache_is_setup(device, name)) {
 		kfree_const(fw_work->name);
@@ -1074,8 +1199,66 @@ request_firmware_nowait(
 	schedule_work(&fw_work->work);
 	return 0;
 }
+
+/**
+ * request_firmware_nowait() - asynchronous version of request_firmware
+ * @module: module requesting the firmware
+ * @uevent: sends uevent to copy the firmware image if this flag
+ *	is non-zero else the firmware copy must be done manually.
+ * @name: name of firmware file
+ * @device: device for which firmware is being loaded
+ * @gfp: allocation flags
+ * @context: will be passed over to @cont, and
+ *	@fw may be %NULL if firmware request fails.
+ * @cont: function will be called asynchronously when the firmware
+ *	request is over.
+ *
+ *	Caller must hold the reference count of @device.
+ *
+ *	Asynchronous variant of request_firmware() for user contexts:
+ *		- sleep for as small periods as possible since it may
+ *		  increase kernel boot time of built-in device drivers
+ *		  requesting firmware in their ->probe() methods, if
+ *		  @gfp is GFP_KERNEL.
+ *
+ *		- can't sleep at all if @gfp is GFP_ATOMIC.
+ **/
+int request_firmware_nowait(
+	struct module *module, bool uevent,
+	const char *name, struct device *device, gfp_t gfp, void *context,
+	void (*cont)(const struct firmware *fw, void *context))
+{
+	return _request_firmware_nowait(module, uevent, name, device, gfp,
+					context, cont, false);
+
+}
 EXPORT_SYMBOL(request_firmware_nowait);
 
+/**
+ * firmware_request_nowait_nowarn() - async version of request_firmware_nowarn
+ * @module: module requesting the firmware
+ * @name: name of firmware file
+ * @device: device for which firmware is being loaded
+ * @gfp: allocation flags
+ * @context: will be passed over to @cont, and
+ *	@fw may be %NULL if firmware request fails.
+ * @cont: function will be called asynchronously when the firmware
+ *	request is over.
+ *
+ * Similar in function to request_firmware_nowait(), but doesn't print a warning
+ * when the firmware file could not be found and always sends a uevent to copy
+ * the firmware image.
+ */
+int firmware_request_nowait_nowarn(
+	struct module *module, const char *name,
+	struct device *device, gfp_t gfp, void *context,
+	void (*cont)(const struct firmware *fw, void *context))
+{
+	return _request_firmware_nowait(module, FW_ACTION_UEVENT, name, device,
+					gfp, context, cont, true);
+}
+EXPORT_SYMBOL_GPL(firmware_request_nowait_nowarn);
+
 #ifdef CONFIG_FW_CACHE
 static ASYNC_DOMAIN_EXCLUSIVE(fw_cache_domain);
 
@@ -1139,7 +1322,7 @@ static int uncache_firmware(const char *fw_name)
 
 	pr_debug("%s: %s\n", __func__, fw_name);
 
-	if (fw_get_builtin_firmware(&fw, fw_name, NULL, 0))
+	if (firmware_request_builtin(&fw, fw_name))
 		return 0;
 
 	fw_priv = lookup_fw_priv(fw_name);
@@ -1181,11 +1364,11 @@ static int __fw_entry_found(const char *name)
 	return 0;
 }
 
-static int fw_cache_piggyback_on_request(const char *name)
+static void fw_cache_piggyback_on_request(struct fw_priv *fw_priv)
 {
-	struct firmware_cache *fwc = &fw_cache;
+	const char *name = fw_priv->fw_name;
+	struct firmware_cache *fwc = fw_priv->fwc;
 	struct fw_cache_entry *fce;
-	int ret = 0;
 
 	spin_lock(&fwc->name_lock);
 	if (__fw_entry_found(name))
@@ -1193,13 +1376,12 @@ static int fw_cache_piggyback_on_request(const char *name)
 
 	fce = alloc_fw_cache_entry(name);
 	if (fce) {
-		ret = 1;
 		list_add(&fce->list, &fwc->fw_names);
+		kref_get(&fw_priv->ref);
 		pr_debug("%s: fw: %s\n", __func__, name);
 	}
 found:
 	spin_unlock(&fwc->name_lock);
-	return ret;
 }
 
 static void free_fw_cache_entry(struct fw_cache_entry *fce)
@@ -1368,10 +1550,10 @@ static int fw_pm_notify(struct notifier_block *notify_block,
 	case PM_SUSPEND_PREPARE:
 	case PM_RESTORE_PREPARE:
 		/*
-		 * kill pending fallback requests with a custom fallback
-		 * to avoid stalling suspend.
+		 * Here, kill pending fallback requests will only kill
+		 * non-uevent firmware request to avoid stalling suspend.
 		 */
-		kill_pending_fw_fallback_reqs(true);
+		kill_pending_fw_fallback_reqs(false);
 		device_cache_fw_images();
 		break;
 
@@ -1394,16 +1576,20 @@ static int fw_pm_notify(struct notifier_block *notify_block,
 }
 
 /* stop caching firmware once syscore_suspend is reached */
-static int fw_suspend(void)
+static int fw_suspend(void *data)
 {
 	fw_cache.state = FW_LOADER_NO_CACHE;
 	return 0;
 }
 
-static struct syscore_ops fw_syscore_ops = {
+static const struct syscore_ops fw_syscore_ops = {
 	.suspend = fw_suspend,
 };
 
+static struct syscore fw_syscore = {
+	.ops = &fw_syscore_ops,
+};
+
 static int __init register_fw_pm_ops(void)
 {
 	int ret;
@@ -1419,20 +1605,19 @@ static int __init register_fw_pm_ops(void)
 	if (ret)
 		return ret;
 
-	register_syscore_ops(&fw_syscore_ops);
+	register_syscore(&fw_syscore);
 
 	return ret;
 }
 
 static inline void unregister_fw_pm_ops(void)
 {
-	unregister_syscore_ops(&fw_syscore_ops);
+	unregister_syscore(&fw_syscore);
 	unregister_pm_notifier(&fw_cache.pm_notify);
 }
 #else
-static int fw_cache_piggyback_on_request(const char *name)
+static void fw_cache_piggyback_on_request(struct fw_priv *fw_priv)
 {
-	return 0;
 }
 static inline int register_fw_pm_ops(void)
 {
@@ -1457,7 +1642,7 @@ static int fw_shutdown_notify(struct notifier_block *unused1,
 	 * Kill all pending fallback requests to avoid both stalling shutdown,
 	 * and avoid a deadlock with the usermode_lock.
 	 */
-	kill_pending_fw_fallback_reqs(false);
+	kill_pending_fw_fallback_reqs(true);
 
 	return NOTIFY_DONE;
 }
diff --git a/drivers/base/firmware_loader/sysfs.c b/drivers/base/firmware_loader/sysfs.c
new file mode 100644
index 000000000000..92e91050f96a
--- /dev/null
+++ b/drivers/base/firmware_loader/sysfs.c
@@ -0,0 +1,425 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <linux/highmem.h>
+#include <linux/module.h>
+#include <linux/security.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+
+#include "sysfs.h"
+
+/*
+ * sysfs support for firmware loader
+ */
+
+void __fw_load_abort(struct fw_priv *fw_priv)
+{
+	/*
+	 * There is a small window in which user can write to 'loading'
+	 * between loading done/aborted and disappearance of 'loading'
+	 */
+	if (fw_state_is_aborted(fw_priv) || fw_state_is_done(fw_priv))
+		return;
+
+	fw_state_aborted(fw_priv);
+}
+
+#ifdef CONFIG_FW_LOADER_USER_HELPER
+static ssize_t timeout_show(const struct class *class, const struct class_attribute *attr,
+			    char *buf)
+{
+	return sysfs_emit(buf, "%d\n", __firmware_loading_timeout());
+}
+
+/**
+ * timeout_store() - set number of seconds to wait for firmware
+ * @class: device class pointer
+ * @attr: device attribute pointer
+ * @buf: buffer to scan for timeout value
+ * @count: number of bytes in @buf
+ *
+ *	Sets the number of seconds to wait for the firmware.  Once
+ *	this expires an error will be returned to the driver and no
+ *	firmware will be provided.
+ *
+ *	Note: zero means 'wait forever'.
+ **/
+static ssize_t timeout_store(const struct class *class, const struct class_attribute *attr,
+			     const char *buf, size_t count)
+{
+	int tmp_loading_timeout;
+
+	if (kstrtoint(buf, 10, &tmp_loading_timeout))
+		return -EINVAL;
+
+	if (tmp_loading_timeout < 0)
+		tmp_loading_timeout = 0;
+
+	__fw_fallback_set_timeout(tmp_loading_timeout);
+
+	return count;
+}
+static CLASS_ATTR_RW(timeout);
+
+static struct attribute *firmware_class_attrs[] = {
+	&class_attr_timeout.attr,
+	NULL,
+};
+ATTRIBUTE_GROUPS(firmware_class);
+
+static int do_firmware_uevent(const struct fw_sysfs *fw_sysfs, struct kobj_uevent_env *env)
+{
+	if (add_uevent_var(env, "FIRMWARE=%s", fw_sysfs->fw_priv->fw_name))
+		return -ENOMEM;
+	if (add_uevent_var(env, "TIMEOUT=%i", __firmware_loading_timeout()))
+		return -ENOMEM;
+	if (add_uevent_var(env, "ASYNC=%d", fw_sysfs->nowait))
+		return -ENOMEM;
+
+	return 0;
+}
+
+static int firmware_uevent(const struct device *dev, struct kobj_uevent_env *env)
+{
+	const struct fw_sysfs *fw_sysfs = to_fw_sysfs(dev);
+	int err = 0;
+
+	mutex_lock(&fw_lock);
+	if (fw_sysfs->fw_priv)
+		err = do_firmware_uevent(fw_sysfs, env);
+	mutex_unlock(&fw_lock);
+	return err;
+}
+#endif /* CONFIG_FW_LOADER_USER_HELPER */
+
+static void fw_dev_release(struct device *dev)
+{
+	struct fw_sysfs *fw_sysfs = to_fw_sysfs(dev);
+
+	if (fw_sysfs->fw_upload_priv)
+		fw_upload_free(fw_sysfs);
+
+	kfree(fw_sysfs);
+}
+
+static struct class firmware_class = {
+	.name		= "firmware",
+#ifdef CONFIG_FW_LOADER_USER_HELPER
+	.class_groups	= firmware_class_groups,
+	.dev_uevent	= firmware_uevent,
+#endif
+	.dev_release	= fw_dev_release,
+};
+
+int register_sysfs_loader(void)
+{
+	int ret = class_register(&firmware_class);
+
+	if (ret != 0)
+		return ret;
+	return register_firmware_config_sysctl();
+}
+
+void unregister_sysfs_loader(void)
+{
+	unregister_firmware_config_sysctl();
+	class_unregister(&firmware_class);
+}
+
+static ssize_t firmware_loading_show(struct device *dev,
+				     struct device_attribute *attr, char *buf)
+{
+	struct fw_sysfs *fw_sysfs = to_fw_sysfs(dev);
+	int loading = 0;
+
+	mutex_lock(&fw_lock);
+	if (fw_sysfs->fw_priv)
+		loading = fw_state_is_loading(fw_sysfs->fw_priv);
+	mutex_unlock(&fw_lock);
+
+	return sysfs_emit(buf, "%d\n", loading);
+}
+
+/**
+ * firmware_loading_store() - set value in the 'loading' control file
+ * @dev: device pointer
+ * @attr: device attribute pointer
+ * @buf: buffer to scan for loading control value
+ * @count: number of bytes in @buf
+ *
+ *	The relevant values are:
+ *
+ *	 1: Start a load, discarding any previous partial load.
+ *	 0: Conclude the load and hand the data to the driver code.
+ *	-1: Conclude the load with an error and discard any written data.
+ **/
+static ssize_t firmware_loading_store(struct device *dev,
+				      struct device_attribute *attr,
+				      const char *buf, size_t count)
+{
+	struct fw_sysfs *fw_sysfs = to_fw_sysfs(dev);
+	struct fw_priv *fw_priv;
+	ssize_t written = count;
+	int loading;
+
+	if (kstrtoint(buf, 10, &loading))
+		return -EINVAL;
+
+	mutex_lock(&fw_lock);
+	fw_priv = fw_sysfs->fw_priv;
+	if (fw_state_is_aborted(fw_priv) || fw_state_is_done(fw_priv))
+		goto out;
+
+	switch (loading) {
+	case 1:
+		/* discarding any previous partial load */
+		fw_free_paged_buf(fw_priv);
+		fw_state_start(fw_priv);
+		break;
+	case 0:
+		if (fw_state_is_loading(fw_priv)) {
+			int rc;
+
+			/*
+			 * Several loading requests may be pending on
+			 * one same firmware buf, so let all requests
+			 * see the mapped 'buf->data' once the loading
+			 * is completed.
+			 */
+			rc = fw_map_paged_buf(fw_priv);
+			if (rc)
+				dev_err(dev, "%s: map pages failed\n",
+					__func__);
+			else
+				rc = security_kernel_post_load_data(fw_priv->data,
+								    fw_priv->size,
+								    LOADING_FIRMWARE,
+								    "blob");
+
+			/*
+			 * Same logic as fw_load_abort, only the DONE bit
+			 * is ignored and we set ABORT only on failure.
+			 */
+			if (rc) {
+				fw_state_aborted(fw_priv);
+				written = rc;
+			} else {
+				fw_state_done(fw_priv);
+
+				/*
+				 * If this is a user-initiated firmware upload
+				 * then start the upload in a worker thread now.
+				 */
+				rc = fw_upload_start(fw_sysfs);
+				if (rc)
+					written = rc;
+			}
+			break;
+		}
+		fallthrough;
+	default:
+		dev_err(dev, "%s: unexpected value (%d)\n", __func__, loading);
+		fallthrough;
+	case -1:
+		fw_load_abort(fw_sysfs);
+		if (fw_sysfs->fw_upload_priv)
+			fw_state_init(fw_sysfs->fw_priv);
+
+		break;
+	}
+out:
+	mutex_unlock(&fw_lock);
+	return written;
+}
+
+DEVICE_ATTR(loading, 0644, firmware_loading_show, firmware_loading_store);
+
+static void firmware_rw_data(struct fw_priv *fw_priv, char *buffer,
+			     loff_t offset, size_t count, bool read)
+{
+	if (read)
+		memcpy(buffer, fw_priv->data + offset, count);
+	else
+		memcpy(fw_priv->data + offset, buffer, count);
+}
+
+static void firmware_rw(struct fw_priv *fw_priv, char *buffer,
+			loff_t offset, size_t count, bool read)
+{
+	while (count) {
+		int page_nr = offset >> PAGE_SHIFT;
+		int page_ofs = offset & (PAGE_SIZE - 1);
+		int page_cnt = min_t(size_t, PAGE_SIZE - page_ofs, count);
+
+		if (read)
+			memcpy_from_page(buffer, fw_priv->pages[page_nr],
+					 page_ofs, page_cnt);
+		else
+			memcpy_to_page(fw_priv->pages[page_nr], page_ofs,
+				       buffer, page_cnt);
+
+		buffer += page_cnt;
+		offset += page_cnt;
+		count -= page_cnt;
+	}
+}
+
+static ssize_t firmware_data_read(struct file *filp, struct kobject *kobj,
+				  const struct bin_attribute *bin_attr,
+				  char *buffer, loff_t offset, size_t count)
+{
+	struct device *dev = kobj_to_dev(kobj);
+	struct fw_sysfs *fw_sysfs = to_fw_sysfs(dev);
+	struct fw_priv *fw_priv;
+	ssize_t ret_count;
+
+	mutex_lock(&fw_lock);
+	fw_priv = fw_sysfs->fw_priv;
+	if (!fw_priv || fw_state_is_done(fw_priv)) {
+		ret_count = -ENODEV;
+		goto out;
+	}
+	if (offset > fw_priv->size) {
+		ret_count = 0;
+		goto out;
+	}
+	if (count > fw_priv->size - offset)
+		count = fw_priv->size - offset;
+
+	ret_count = count;
+
+	if (fw_priv->data)
+		firmware_rw_data(fw_priv, buffer, offset, count, true);
+	else
+		firmware_rw(fw_priv, buffer, offset, count, true);
+
+out:
+	mutex_unlock(&fw_lock);
+	return ret_count;
+}
+
+static int fw_realloc_pages(struct fw_sysfs *fw_sysfs, int min_size)
+{
+	int err;
+
+	err = fw_grow_paged_buf(fw_sysfs->fw_priv,
+				PAGE_ALIGN(min_size) >> PAGE_SHIFT);
+	if (err)
+		fw_load_abort(fw_sysfs);
+	return err;
+}
+
+/**
+ * firmware_data_write() - write method for firmware
+ * @filp: open sysfs file
+ * @kobj: kobject for the device
+ * @bin_attr: bin_attr structure
+ * @buffer: buffer being written
+ * @offset: buffer offset for write in total data store area
+ * @count: buffer size
+ *
+ *	Data written to the 'data' attribute will be later handed to
+ *	the driver as a firmware image.
+ **/
+static ssize_t firmware_data_write(struct file *filp, struct kobject *kobj,
+				   const struct bin_attribute *bin_attr,
+				   char *buffer, loff_t offset, size_t count)
+{
+	struct device *dev = kobj_to_dev(kobj);
+	struct fw_sysfs *fw_sysfs = to_fw_sysfs(dev);
+	struct fw_priv *fw_priv;
+	ssize_t retval;
+
+	if (!capable(CAP_SYS_RAWIO))
+		return -EPERM;
+
+	mutex_lock(&fw_lock);
+	fw_priv = fw_sysfs->fw_priv;
+	if (!fw_priv || fw_state_is_done(fw_priv)) {
+		retval = -ENODEV;
+		goto out;
+	}
+
+	if (fw_priv->data) {
+		if (offset + count > fw_priv->allocated_size) {
+			retval = -ENOMEM;
+			goto out;
+		}
+		firmware_rw_data(fw_priv, buffer, offset, count, false);
+		retval = count;
+	} else {
+		retval = fw_realloc_pages(fw_sysfs, offset + count);
+		if (retval)
+			goto out;
+
+		retval = count;
+		firmware_rw(fw_priv, buffer, offset, count, false);
+	}
+
+	fw_priv->size = max_t(size_t, offset + count, fw_priv->size);
+out:
+	mutex_unlock(&fw_lock);
+	return retval;
+}
+
+static const struct bin_attribute firmware_attr_data = {
+	.attr = { .name = "data", .mode = 0644 },
+	.size = 0,
+	.read = firmware_data_read,
+	.write = firmware_data_write,
+};
+
+static struct attribute *fw_dev_attrs[] = {
+	&dev_attr_loading.attr,
+#ifdef CONFIG_FW_UPLOAD
+	&dev_attr_cancel.attr,
+	&dev_attr_status.attr,
+	&dev_attr_error.attr,
+	&dev_attr_remaining_size.attr,
+#endif
+	NULL
+};
+
+static const struct bin_attribute *const fw_dev_bin_attrs[] = {
+	&firmware_attr_data,
+	NULL
+};
+
+static const struct attribute_group fw_dev_attr_group = {
+	.attrs = fw_dev_attrs,
+	.bin_attrs = fw_dev_bin_attrs,
+#ifdef CONFIG_FW_UPLOAD
+	.is_visible = fw_upload_is_visible,
+#endif
+};
+
+static const struct attribute_group *fw_dev_attr_groups[] = {
+	&fw_dev_attr_group,
+	NULL
+};
+
+struct fw_sysfs *
+fw_create_instance(struct firmware *firmware, const char *fw_name,
+		   struct device *device, u32 opt_flags)
+{
+	struct fw_sysfs *fw_sysfs;
+	struct device *f_dev;
+
+	fw_sysfs = kzalloc(sizeof(*fw_sysfs), GFP_KERNEL);
+	if (!fw_sysfs) {
+		fw_sysfs = ERR_PTR(-ENOMEM);
+		goto exit;
+	}
+
+	fw_sysfs->nowait = !!(opt_flags & FW_OPT_NOWAIT);
+	fw_sysfs->fw = firmware;
+	f_dev = &fw_sysfs->dev;
+
+	device_initialize(f_dev);
+	dev_set_name(f_dev, "%s", fw_name);
+	f_dev->parent = device;
+	f_dev->class = &firmware_class;
+	f_dev->groups = fw_dev_attr_groups;
+exit:
+	return fw_sysfs;
+}
diff --git a/drivers/base/firmware_loader/sysfs.h b/drivers/base/firmware_loader/sysfs.h
new file mode 100644
index 000000000000..1cabea544a40
--- /dev/null
+++ b/drivers/base/firmware_loader/sysfs.h
@@ -0,0 +1,118 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __FIRMWARE_SYSFS_H
+#define __FIRMWARE_SYSFS_H
+
+#include <linux/device.h>
+
+#include "firmware.h"
+
+MODULE_IMPORT_NS("FIRMWARE_LOADER_PRIVATE");
+
+extern struct firmware_fallback_config fw_fallback_config;
+extern struct device_attribute dev_attr_loading;
+
+#ifdef CONFIG_FW_LOADER_USER_HELPER
+/**
+ * struct firmware_fallback_config - firmware fallback configuration settings
+ *
+ * Helps describe and fine tune the fallback mechanism.
+ *
+ * @force_sysfs_fallback: force the sysfs fallback mechanism to be used
+ *	as if one had enabled CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y.
+ *	Useful to help debug a CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y
+ *	functionality on a kernel where that config entry has been disabled.
+ * @ignore_sysfs_fallback: force to disable the sysfs fallback mechanism.
+ *	This emulates the behaviour as if we had set the kernel
+ *	config CONFIG_FW_LOADER_USER_HELPER=n.
+ * @old_timeout: for internal use
+ * @loading_timeout: the timeout to wait for the fallback mechanism before
+ *	giving up, in seconds.
+ */
+struct firmware_fallback_config {
+	unsigned int force_sysfs_fallback;
+	unsigned int ignore_sysfs_fallback;
+	int old_timeout;
+	int loading_timeout;
+};
+
+/* These getters are vetted to use int properly */
+static inline int __firmware_loading_timeout(void)
+{
+	return fw_fallback_config.loading_timeout;
+}
+
+/* These setters are vetted to use int properly */
+static inline void __fw_fallback_set_timeout(int timeout)
+{
+	fw_fallback_config.loading_timeout = timeout;
+}
+#endif
+
+#ifdef CONFIG_FW_LOADER_SYSFS
+int register_sysfs_loader(void);
+void unregister_sysfs_loader(void);
+#if defined(CONFIG_FW_LOADER_USER_HELPER) && defined(CONFIG_SYSCTL)
+int register_firmware_config_sysctl(void);
+void unregister_firmware_config_sysctl(void);
+#else
+static inline int register_firmware_config_sysctl(void)
+{
+	return 0;
+}
+
+static inline void unregister_firmware_config_sysctl(void) { }
+#endif /* CONFIG_FW_LOADER_USER_HELPER && CONFIG_SYSCTL */
+#else /* CONFIG_FW_LOADER_SYSFS */
+static inline int register_sysfs_loader(void)
+{
+	return 0;
+}
+
+static inline void unregister_sysfs_loader(void)
+{
+}
+#endif /* CONFIG_FW_LOADER_SYSFS */
+
+struct fw_sysfs {
+	bool nowait;
+	struct device dev;
+	struct fw_priv *fw_priv;
+	struct firmware *fw;
+	void *fw_upload_priv;
+};
+#define to_fw_sysfs(__dev)	container_of_const(__dev, struct fw_sysfs, dev)
+
+void __fw_load_abort(struct fw_priv *fw_priv);
+
+static inline void fw_load_abort(struct fw_sysfs *fw_sysfs)
+{
+	struct fw_priv *fw_priv = fw_sysfs->fw_priv;
+
+	__fw_load_abort(fw_priv);
+}
+
+struct fw_sysfs *
+fw_create_instance(struct firmware *firmware, const char *fw_name,
+		   struct device *device, u32 opt_flags);
+
+#ifdef CONFIG_FW_UPLOAD
+extern struct device_attribute dev_attr_status;
+extern struct device_attribute dev_attr_error;
+extern struct device_attribute dev_attr_cancel;
+extern struct device_attribute dev_attr_remaining_size;
+
+int fw_upload_start(struct fw_sysfs *fw_sysfs);
+void fw_upload_free(struct fw_sysfs *fw_sysfs);
+umode_t fw_upload_is_visible(struct kobject *kobj, struct attribute *attr, int n);
+#else
+static inline int fw_upload_start(struct fw_sysfs *fw_sysfs)
+{
+	return 0;
+}
+
+static inline void fw_upload_free(struct fw_sysfs *fw_sysfs)
+{
+}
+#endif
+
+#endif /* __FIRMWARE_SYSFS_H */
diff --git a/drivers/base/firmware_loader/sysfs_upload.c b/drivers/base/firmware_loader/sysfs_upload.c
new file mode 100644
index 000000000000..c3797b93c5f5
--- /dev/null
+++ b/drivers/base/firmware_loader/sysfs_upload.c
@@ -0,0 +1,410 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <linux/firmware.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+
+#include "sysfs_upload.h"
+
+/*
+ * Support for user-space to initiate a firmware upload to a device.
+ */
+
+static const char * const fw_upload_prog_str[] = {
+	[FW_UPLOAD_PROG_IDLE]	      = "idle",
+	[FW_UPLOAD_PROG_RECEIVING]    = "receiving",
+	[FW_UPLOAD_PROG_PREPARING]    = "preparing",
+	[FW_UPLOAD_PROG_TRANSFERRING] = "transferring",
+	[FW_UPLOAD_PROG_PROGRAMMING]  = "programming"
+};
+
+static const char * const fw_upload_err_str[] = {
+	[FW_UPLOAD_ERR_NONE]	     = "none",
+	[FW_UPLOAD_ERR_HW_ERROR]     = "hw-error",
+	[FW_UPLOAD_ERR_TIMEOUT]	     = "timeout",
+	[FW_UPLOAD_ERR_CANCELED]     = "user-abort",
+	[FW_UPLOAD_ERR_BUSY]	     = "device-busy",
+	[FW_UPLOAD_ERR_INVALID_SIZE] = "invalid-file-size",
+	[FW_UPLOAD_ERR_RW_ERROR]     = "read-write-error",
+	[FW_UPLOAD_ERR_WEAROUT]	     = "flash-wearout",
+	[FW_UPLOAD_ERR_FW_INVALID]   = "firmware-invalid",
+};
+
+static const char *fw_upload_progress(struct device *dev,
+				      enum fw_upload_prog prog)
+{
+	const char *status = "unknown-status";
+
+	if (prog < FW_UPLOAD_PROG_MAX)
+		status = fw_upload_prog_str[prog];
+	else
+		dev_err(dev, "Invalid status during secure update: %d\n", prog);
+
+	return status;
+}
+
+static const char *fw_upload_error(struct device *dev,
+				   enum fw_upload_err err_code)
+{
+	const char *error = "unknown-error";
+
+	if (err_code < FW_UPLOAD_ERR_MAX)
+		error = fw_upload_err_str[err_code];
+	else
+		dev_err(dev, "Invalid error code during secure update: %d\n",
+			err_code);
+
+	return error;
+}
+
+static ssize_t
+status_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+	struct fw_upload_priv *fwlp = to_fw_sysfs(dev)->fw_upload_priv;
+
+	return sysfs_emit(buf, "%s\n", fw_upload_progress(dev, fwlp->progress));
+}
+DEVICE_ATTR_RO(status);
+
+static ssize_t
+error_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+	struct fw_upload_priv *fwlp = to_fw_sysfs(dev)->fw_upload_priv;
+	int ret;
+
+	mutex_lock(&fwlp->lock);
+
+	if (fwlp->progress != FW_UPLOAD_PROG_IDLE)
+		ret = -EBUSY;
+	else if (!fwlp->err_code)
+		ret = 0;
+	else
+		ret = sysfs_emit(buf, "%s:%s\n",
+				 fw_upload_progress(dev, fwlp->err_progress),
+				 fw_upload_error(dev, fwlp->err_code));
+
+	mutex_unlock(&fwlp->lock);
+
+	return ret;
+}
+DEVICE_ATTR_RO(error);
+
+static ssize_t cancel_store(struct device *dev, struct device_attribute *attr,
+			    const char *buf, size_t count)
+{
+	struct fw_upload_priv *fwlp = to_fw_sysfs(dev)->fw_upload_priv;
+	int ret = count;
+	bool cancel;
+
+	if (kstrtobool(buf, &cancel) || !cancel)
+		return -EINVAL;
+
+	mutex_lock(&fwlp->lock);
+	if (fwlp->progress == FW_UPLOAD_PROG_IDLE) {
+		mutex_unlock(&fwlp->lock);
+		return -ENODEV;
+	}
+
+	fwlp->ops->cancel(fwlp->fw_upload);
+	mutex_unlock(&fwlp->lock);
+
+	return ret;
+}
+DEVICE_ATTR_WO(cancel);
+
+static ssize_t remaining_size_show(struct device *dev,
+				   struct device_attribute *attr, char *buf)
+{
+	struct fw_upload_priv *fwlp = to_fw_sysfs(dev)->fw_upload_priv;
+
+	return sysfs_emit(buf, "%u\n", fwlp->remaining_size);
+}
+DEVICE_ATTR_RO(remaining_size);
+
+umode_t
+fw_upload_is_visible(struct kobject *kobj, struct attribute *attr, int n)
+{
+	static struct fw_sysfs *fw_sysfs;
+
+	fw_sysfs = to_fw_sysfs(kobj_to_dev(kobj));
+
+	if (fw_sysfs->fw_upload_priv || attr == &dev_attr_loading.attr)
+		return attr->mode;
+
+	return 0;
+}
+
+static void fw_upload_update_progress(struct fw_upload_priv *fwlp,
+				      enum fw_upload_prog new_progress)
+{
+	mutex_lock(&fwlp->lock);
+	fwlp->progress = new_progress;
+	mutex_unlock(&fwlp->lock);
+}
+
+static void fw_upload_set_error(struct fw_upload_priv *fwlp,
+				enum fw_upload_err err_code)
+{
+	mutex_lock(&fwlp->lock);
+	fwlp->err_progress = fwlp->progress;
+	fwlp->err_code = err_code;
+	mutex_unlock(&fwlp->lock);
+}
+
+static void fw_upload_prog_complete(struct fw_upload_priv *fwlp)
+{
+	mutex_lock(&fwlp->lock);
+	fwlp->progress = FW_UPLOAD_PROG_IDLE;
+	mutex_unlock(&fwlp->lock);
+}
+
+static void fw_upload_main(struct work_struct *work)
+{
+	struct fw_upload_priv *fwlp;
+	struct fw_sysfs *fw_sysfs;
+	u32 written = 0, offset = 0;
+	enum fw_upload_err ret;
+	struct device *fw_dev;
+	struct fw_upload *fwl;
+
+	fwlp = container_of(work, struct fw_upload_priv, work);
+	fwl = fwlp->fw_upload;
+	fw_sysfs = (struct fw_sysfs *)fwl->priv;
+	fw_dev = &fw_sysfs->dev;
+
+	fw_upload_update_progress(fwlp, FW_UPLOAD_PROG_PREPARING);
+	ret = fwlp->ops->prepare(fwl, fwlp->data, fwlp->remaining_size);
+	if (ret != FW_UPLOAD_ERR_NONE) {
+		fw_upload_set_error(fwlp, ret);
+		goto putdev_exit;
+	}
+
+	fw_upload_update_progress(fwlp, FW_UPLOAD_PROG_TRANSFERRING);
+	while (fwlp->remaining_size) {
+		ret = fwlp->ops->write(fwl, fwlp->data, offset,
+					fwlp->remaining_size, &written);
+		if (ret != FW_UPLOAD_ERR_NONE || !written) {
+			if (ret == FW_UPLOAD_ERR_NONE) {
+				dev_warn(fw_dev, "write-op wrote zero data\n");
+				ret = FW_UPLOAD_ERR_RW_ERROR;
+			}
+			fw_upload_set_error(fwlp, ret);
+			goto done;
+		}
+
+		fwlp->remaining_size -= written;
+		offset += written;
+	}
+
+	fw_upload_update_progress(fwlp, FW_UPLOAD_PROG_PROGRAMMING);
+	ret = fwlp->ops->poll_complete(fwl);
+	if (ret != FW_UPLOAD_ERR_NONE)
+		fw_upload_set_error(fwlp, ret);
+
+done:
+	if (fwlp->ops->cleanup)
+		fwlp->ops->cleanup(fwl);
+
+putdev_exit:
+	put_device(fw_dev->parent);
+
+	/*
+	 * Note: fwlp->remaining_size is left unmodified here to provide
+	 * additional information on errors. It will be reinitialized when
+	 * the next firmeware upload begins.
+	 */
+	mutex_lock(&fw_lock);
+	fw_free_paged_buf(fw_sysfs->fw_priv);
+	fw_state_init(fw_sysfs->fw_priv);
+	mutex_unlock(&fw_lock);
+	fwlp->data = NULL;
+	fw_upload_prog_complete(fwlp);
+}
+
+/*
+ * Start a worker thread to upload data to the parent driver.
+ * Must be called with fw_lock held.
+ */
+int fw_upload_start(struct fw_sysfs *fw_sysfs)
+{
+	struct fw_priv *fw_priv = fw_sysfs->fw_priv;
+	struct device *fw_dev = &fw_sysfs->dev;
+	struct fw_upload_priv *fwlp;
+
+	if (!fw_sysfs->fw_upload_priv)
+		return 0;
+
+	if (!fw_priv->size) {
+		fw_free_paged_buf(fw_priv);
+		fw_state_init(fw_sysfs->fw_priv);
+		return 0;
+	}
+
+	fwlp = fw_sysfs->fw_upload_priv;
+	mutex_lock(&fwlp->lock);
+
+	/* Do not interfere with an on-going fw_upload */
+	if (fwlp->progress != FW_UPLOAD_PROG_IDLE) {
+		mutex_unlock(&fwlp->lock);
+		return -EBUSY;
+	}
+
+	get_device(fw_dev->parent); /* released in fw_upload_main */
+
+	fwlp->progress = FW_UPLOAD_PROG_RECEIVING;
+	fwlp->err_code = 0;
+	fwlp->remaining_size = fw_priv->size;
+	fwlp->data = fw_priv->data;
+
+	pr_debug("%s: fw-%s fw_priv=%p data=%p size=%u\n",
+		 __func__, fw_priv->fw_name,
+		 fw_priv, fw_priv->data,
+		 (unsigned int)fw_priv->size);
+
+	queue_work(system_long_wq, &fwlp->work);
+	mutex_unlock(&fwlp->lock);
+
+	return 0;
+}
+
+void fw_upload_free(struct fw_sysfs *fw_sysfs)
+{
+	struct fw_upload_priv *fw_upload_priv = fw_sysfs->fw_upload_priv;
+
+	free_fw_priv(fw_sysfs->fw_priv);
+	kfree(fw_upload_priv->fw_upload);
+	kfree(fw_upload_priv);
+}
+
+/**
+ * firmware_upload_register() - register for the firmware upload sysfs API
+ * @module: kernel module of this device
+ * @parent: parent device instantiating firmware upload
+ * @name: firmware name to be associated with this device
+ * @ops: pointer to structure of firmware upload ops
+ * @dd_handle: pointer to parent driver private data
+ *
+ *	@name must be unique among all users of firmware upload. The firmware
+ *	sysfs files for this device will be found at /sys/class/firmware/@name.
+ *
+ *	Return: struct fw_upload pointer or ERR_PTR()
+ *
+ **/
+struct fw_upload *
+firmware_upload_register(struct module *module, struct device *parent,
+			 const char *name, const struct fw_upload_ops *ops,
+			 void *dd_handle)
+{
+	u32 opt_flags = FW_OPT_NOCACHE;
+	struct fw_upload *fw_upload;
+	struct fw_upload_priv *fw_upload_priv;
+	struct fw_sysfs *fw_sysfs;
+	struct fw_priv *fw_priv;
+	struct device *fw_dev;
+	int ret;
+
+	if (!name || name[0] == '\0')
+		return ERR_PTR(-EINVAL);
+
+	if (!ops || !ops->cancel || !ops->prepare ||
+	    !ops->write || !ops->poll_complete) {
+		dev_err(parent, "Attempt to register without all required ops\n");
+		return ERR_PTR(-EINVAL);
+	}
+
+	if (!try_module_get(module))
+		return ERR_PTR(-EFAULT);
+
+	fw_upload = kzalloc(sizeof(*fw_upload), GFP_KERNEL);
+	if (!fw_upload) {
+		ret = -ENOMEM;
+		goto exit_module_put;
+	}
+
+	fw_upload_priv = kzalloc(sizeof(*fw_upload_priv), GFP_KERNEL);
+	if (!fw_upload_priv) {
+		ret = -ENOMEM;
+		goto free_fw_upload;
+	}
+
+	fw_upload_priv->fw_upload = fw_upload;
+	fw_upload_priv->ops = ops;
+	mutex_init(&fw_upload_priv->lock);
+	fw_upload_priv->module = module;
+	fw_upload_priv->name = name;
+	fw_upload_priv->err_code = 0;
+	fw_upload_priv->progress = FW_UPLOAD_PROG_IDLE;
+	INIT_WORK(&fw_upload_priv->work, fw_upload_main);
+	fw_upload->dd_handle = dd_handle;
+
+	fw_sysfs = fw_create_instance(NULL, name, parent, opt_flags);
+	if (IS_ERR(fw_sysfs)) {
+		ret = PTR_ERR(fw_sysfs);
+		goto free_fw_upload_priv;
+	}
+	fw_upload->priv = fw_sysfs;
+	fw_sysfs->fw_upload_priv = fw_upload_priv;
+	fw_dev = &fw_sysfs->dev;
+
+	ret = alloc_lookup_fw_priv(name, &fw_cache, &fw_priv,  NULL, 0, 0,
+				   FW_OPT_NOCACHE);
+	if (ret != 0) {
+		if (ret > 0)
+			ret = -EINVAL;
+		goto free_fw_sysfs;
+	}
+	fw_priv->is_paged_buf = true;
+	fw_sysfs->fw_priv = fw_priv;
+
+	ret = device_add(fw_dev);
+	if (ret) {
+		dev_err(fw_dev, "%s: device_register failed\n", __func__);
+		put_device(fw_dev);
+		goto exit_module_put;
+	}
+
+	return fw_upload;
+
+free_fw_sysfs:
+	kfree(fw_sysfs);
+
+free_fw_upload_priv:
+	kfree(fw_upload_priv);
+
+free_fw_upload:
+	kfree(fw_upload);
+
+exit_module_put:
+	module_put(module);
+
+	return ERR_PTR(ret);
+}
+EXPORT_SYMBOL_GPL(firmware_upload_register);
+
+/**
+ * firmware_upload_unregister() - Unregister firmware upload interface
+ * @fw_upload: pointer to struct fw_upload
+ **/
+void firmware_upload_unregister(struct fw_upload *fw_upload)
+{
+	struct fw_sysfs *fw_sysfs = fw_upload->priv;
+	struct fw_upload_priv *fw_upload_priv = fw_sysfs->fw_upload_priv;
+	struct module *module = fw_upload_priv->module;
+
+	mutex_lock(&fw_upload_priv->lock);
+	if (fw_upload_priv->progress == FW_UPLOAD_PROG_IDLE) {
+		mutex_unlock(&fw_upload_priv->lock);
+		goto unregister;
+	}
+
+	fw_upload_priv->ops->cancel(fw_upload);
+	mutex_unlock(&fw_upload_priv->lock);
+
+	/* Ensure lower-level device-driver is finished */
+	flush_work(&fw_upload_priv->work);
+
+unregister:
+	device_unregister(&fw_sysfs->dev);
+	module_put(module);
+}
+EXPORT_SYMBOL_GPL(firmware_upload_unregister);
diff --git a/drivers/base/firmware_loader/sysfs_upload.h b/drivers/base/firmware_loader/sysfs_upload.h
new file mode 100644
index 000000000000..31931ff7808a
--- /dev/null
+++ b/drivers/base/firmware_loader/sysfs_upload.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __SYSFS_UPLOAD_H
+#define __SYSFS_UPLOAD_H
+
+#include <linux/device.h>
+
+#include "sysfs.h"
+
+/**
+ * enum fw_upload_prog - firmware upload progress codes
+ * @FW_UPLOAD_PROG_IDLE: there is no firmware upload in progress
+ * @FW_UPLOAD_PROG_RECEIVING: worker thread is receiving firmware data
+ * @FW_UPLOAD_PROG_PREPARING: target device is preparing for firmware upload
+ * @FW_UPLOAD_PROG_TRANSFERRING: data is being copied to the device
+ * @FW_UPLOAD_PROG_PROGRAMMING: device is performing the firmware update
+ * @FW_UPLOAD_PROG_MAX: Maximum progress code marker
+ */
+enum fw_upload_prog {
+	FW_UPLOAD_PROG_IDLE,
+	FW_UPLOAD_PROG_RECEIVING,
+	FW_UPLOAD_PROG_PREPARING,
+	FW_UPLOAD_PROG_TRANSFERRING,
+	FW_UPLOAD_PROG_PROGRAMMING,
+	FW_UPLOAD_PROG_MAX
+};
+
+struct fw_upload_priv {
+	struct fw_upload *fw_upload;
+	struct module *module;
+	const char *name;
+	const struct fw_upload_ops *ops;
+	struct mutex lock;		  /* protect data structure contents */
+	struct work_struct work;
+	const u8 *data;			  /* pointer to update data */
+	u32 remaining_size;		  /* size remaining to transfer */
+	enum fw_upload_prog progress;
+	enum fw_upload_prog err_progress; /* progress at time of failure */
+	enum fw_upload_err err_code;	  /* security manager error code */
+};
+
+#endif /* __SYSFS_UPLOAD_H */
diff --git a/drivers/base/init.c b/drivers/base/init.c
index 908e6520e804..9d2b06d65dfc 100644
--- a/drivers/base/init.c
+++ b/drivers/base/init.c
@@ -8,6 +8,7 @@
 #include <linux/init.h>
 #include <linux/memory.h>
 #include <linux/of.h>
+#include <linux/backing-dev.h>
 
 #include "base.h"
 
@@ -20,6 +21,7 @@
 void __init driver_init(void)
 {
 	/* These are the core pieces */
+	bdi_init(&noop_backing_dev_info);
 	devtmpfs_init();
 	devices_init();
 	buses_init();
@@ -30,9 +32,12 @@ void __init driver_init(void)
 	/* These are also core pieces, but must come after the
 	 * core core pieces.
 	 */
+	faux_bus_init();
 	of_core_init();
 	platform_bus_init();
-	cpu_dev_init();
+	auxiliary_bus_init();
 	memory_dev_init();
+	node_dev_init();
+	cpu_dev_init();
 	container_dev_init();
 }
diff --git a/drivers/base/isa.c b/drivers/base/isa.c
index 2772f5d1948a..bfd9215c9070 100644
--- a/drivers/base/isa.c
+++ b/drivers/base/isa.c
@@ -23,7 +23,7 @@ struct isa_dev {
 
 #define to_isa_dev(x) container_of((x), struct isa_dev, dev)
 
-static int isa_bus_match(struct device *dev, struct device_driver *driver)
+static int isa_bus_match(struct device *dev, const struct device_driver *driver)
 {
 	struct isa_driver *isa_driver = to_isa_driver(driver);
 
@@ -46,14 +46,12 @@ static int isa_bus_probe(struct device *dev)
 	return 0;
 }
 
-static int isa_bus_remove(struct device *dev)
+static void isa_bus_remove(struct device *dev)
 {
 	struct isa_driver *isa_driver = dev->platform_data;
 
 	if (isa_driver && isa_driver->remove)
-		return isa_driver->remove(dev, to_isa_dev(dev)->id);
-
-	return 0;
+		isa_driver->remove(dev, to_isa_dev(dev)->id);
 }
 
 static void isa_bus_shutdown(struct device *dev)
@@ -84,7 +82,7 @@ static int isa_bus_resume(struct device *dev)
 	return 0;
 }
 
-static struct bus_type isa_bus_type = {
+static const struct bus_type isa_bus_type = {
 	.name		= "isa",
 	.match		= isa_bus_match,
 	.probe		= isa_bus_probe,
@@ -151,11 +149,8 @@ int isa_register_driver(struct isa_driver *isa_driver, unsigned int ndev)
 			break;
 		}
 
-		if (isa_dev->dev.platform_data) {
-			isa_dev->next = isa_driver->devices;
-			isa_driver->devices = &isa_dev->dev;
-		} else
-			device_unregister(&isa_dev->dev);
+		isa_dev->next = isa_driver->devices;
+		isa_driver->devices = &isa_dev->dev;
 	}
 
 	if (!error && !isa_driver->devices)
diff --git a/drivers/base/map.c b/drivers/base/map.c
index 5650ab2b247a..83aeb09ca161 100644
--- a/drivers/base/map.c
+++ b/drivers/base/map.c
@@ -33,9 +33,9 @@ int kobj_map(struct kobj_map *domain, dev_t dev, unsigned long range,
 	     struct module *module, kobj_probe_t *probe,
 	     int (*lock)(dev_t, void *), void *data)
 {
-	unsigned n = MAJOR(dev + range - 1) - MAJOR(dev) + 1;
-	unsigned index = MAJOR(dev);
-	unsigned i;
+	unsigned int n = MAJOR(dev + range - 1) - MAJOR(dev) + 1;
+	unsigned int index = MAJOR(dev);
+	unsigned int i;
 	struct probe *p;
 
 	if (n > 255)
@@ -67,9 +67,9 @@ int kobj_map(struct kobj_map *domain, dev_t dev, unsigned long range,
 
 void kobj_unmap(struct kobj_map *domain, dev_t dev, unsigned long range)
 {
-	unsigned n = MAJOR(dev + range - 1) - MAJOR(dev) + 1;
-	unsigned index = MAJOR(dev);
-	unsigned i;
+	unsigned int n = MAJOR(dev + range - 1) - MAJOR(dev) + 1;
+	unsigned int index = MAJOR(dev);
+	unsigned int i;
 	struct probe *found = NULL;
 
 	if (n > 255)
diff --git a/drivers/base/memory.c b/drivers/base/memory.c
index dbec3a05590a..751f248ca4a8 100644
--- a/drivers/base/memory.c
+++ b/drivers/base/memory.c
@@ -21,6 +21,8 @@
 #include <linux/mm.h>
 #include <linux/stat.h>
 #include <linux/slab.h>
+#include <linux/xarray.h>
+#include <linux/export.h>
 
 #include <linux/atomic.h>
 #include <linux/uaccess.h>
@@ -34,7 +36,7 @@ static const char *const online_type_to_str[] = {
 	[MMOP_ONLINE_MOVABLE] = "online_movable",
 };
 
-int memhp_online_type_from_str(const char *str)
+int mhp_online_type_from_str(const char *str)
 {
 	int i;
 
@@ -47,33 +49,32 @@ int memhp_online_type_from_str(const char *str)
 
 #define to_memory_block(dev) container_of(dev, struct memory_block, dev)
 
-static int sections_per_block;
-
-static inline unsigned long base_memory_block_id(unsigned long section_nr)
-{
-	return section_nr / sections_per_block;
-}
-
-static inline unsigned long pfn_to_block_id(unsigned long pfn)
-{
-	return base_memory_block_id(pfn_to_section_nr(pfn));
-}
-
-static inline unsigned long phys_to_block_id(unsigned long phys)
-{
-	return pfn_to_block_id(PFN_DOWN(phys));
-}
+int sections_per_block;
+EXPORT_SYMBOL(sections_per_block);
 
 static int memory_subsys_online(struct device *dev);
 static int memory_subsys_offline(struct device *dev);
 
-static struct bus_type memory_subsys = {
+static const struct bus_type memory_subsys = {
 	.name = MEMORY_CLASS_NAME,
 	.dev_name = MEMORY_CLASS_NAME,
 	.online = memory_subsys_online,
 	.offline = memory_subsys_offline,
 };
 
+/*
+ * Memory blocks are cached in a local radix tree to avoid
+ * a costly linear search for the corresponding device on
+ * the subsystem bus.
+ */
+static DEFINE_XARRAY(memory_blocks);
+
+/*
+ * Memory groups, indexed by memory group id (mgid).
+ */
+static DEFINE_XARRAY_FLAGS(memory_groups, XA_FLAGS_ALLOC);
+#define MEMORY_GROUP_MARK_DYNAMIC	XA_MARK_1
+
 static BLOCKING_NOTIFIER_HEAD(memory_chain);
 
 int register_memory_notifier(struct notifier_block *nb)
@@ -91,27 +92,75 @@ EXPORT_SYMBOL(unregister_memory_notifier);
 static void memory_block_release(struct device *dev)
 {
 	struct memory_block *mem = to_memory_block(dev);
-
+	/* Verify that the altmap is freed */
+	WARN_ON(mem->altmap);
 	kfree(mem);
 }
 
+
+/* Max block size to be set by memory_block_advise_max_size */
+static unsigned long memory_block_advised_size;
+static bool memory_block_advised_size_queried;
+
+/**
+ * memory_block_advise_max_size() - advise memory hotplug on the max suggested
+ *				    block size, usually for alignment.
+ * @size: suggestion for maximum block size. must be aligned on power of 2.
+ *
+ * Early boot software (pre-allocator init) may advise archs on the max block
+ * size. This value can only decrease after initialization, as the intent is
+ * to identify the largest supported alignment for all sources.
+ *
+ * Use of this value is arch-defined, as is min/max block size.
+ *
+ * Return: 0 on success
+ *	   -EINVAL if size is 0 or not pow2 aligned
+ *	   -EBUSY if value has already been probed
+ */
+int __init memory_block_advise_max_size(unsigned long size)
+{
+	if (!size || !is_power_of_2(size))
+		return -EINVAL;
+
+	if (memory_block_advised_size_queried)
+		return -EBUSY;
+
+	if (memory_block_advised_size)
+		memory_block_advised_size = min(memory_block_advised_size, size);
+	else
+		memory_block_advised_size = size;
+
+	return 0;
+}
+
+/**
+ * memory_block_advised_max_size() - query advised max hotplug block size.
+ *
+ * After the first call, the value can never change. Callers looking for the
+ * actual block size should use memory_block_size_bytes. This interface is
+ * intended for use by arch-init when initializing the hotplug block size.
+ *
+ * Return: advised size in bytes, or 0 if never set.
+ */
+unsigned long memory_block_advised_max_size(void)
+{
+	memory_block_advised_size_queried = true;
+	return memory_block_advised_size;
+}
+
 unsigned long __weak memory_block_size_bytes(void)
 {
 	return MIN_MEMORY_BLOCK_SIZE;
 }
 EXPORT_SYMBOL_GPL(memory_block_size_bytes);
 
-/*
- * Show the first physical section index (number) of this memory block.
- */
+/* Show the memory block ID, relative to the memory block size */
 static ssize_t phys_index_show(struct device *dev,
 			       struct device_attribute *attr, char *buf)
 {
 	struct memory_block *mem = to_memory_block(dev);
-	unsigned long phys_index;
 
-	phys_index = mem->start_section_nr / sections_per_block;
-	return sprintf(buf, "%08lx\n", phys_index);
+	return sysfs_emit(buf, "%08lx\n", memory_block_id(mem->start_section_nr));
 }
 
 /*
@@ -121,7 +170,7 @@ static ssize_t phys_index_show(struct device *dev,
 static ssize_t removable_show(struct device *dev, struct device_attribute *attr,
 			      char *buf)
 {
-	return sprintf(buf, "%d\n", (int)IS_ENABLED(CONFIG_MEMORY_HOTREMOVE));
+	return sysfs_emit(buf, "%d\n", (int)IS_ENABLED(CONFIG_MEMORY_HOTREMOVE));
 }
 
 /*
@@ -131,7 +180,7 @@ static ssize_t state_show(struct device *dev, struct device_attribute *attr,
 			  char *buf)
 {
 	struct memory_block *mem = to_memory_block(dev);
-	ssize_t len = 0;
+	const char *output;
 
 	/*
 	 * We can probably put these states in a nice little array
@@ -139,27 +188,134 @@ static ssize_t state_show(struct device *dev, struct device_attribute *attr,
 	 */
 	switch (mem->state) {
 	case MEM_ONLINE:
-		len = sprintf(buf, "online\n");
+		output = "online";
 		break;
 	case MEM_OFFLINE:
-		len = sprintf(buf, "offline\n");
+		output = "offline";
 		break;
 	case MEM_GOING_OFFLINE:
-		len = sprintf(buf, "going-offline\n");
+		output = "going-offline";
 		break;
 	default:
-		len = sprintf(buf, "ERROR-UNKNOWN-%ld\n",
-				mem->state);
 		WARN_ON(1);
-		break;
+		return sysfs_emit(buf, "ERROR-UNKNOWN-%d\n", mem->state);
 	}
 
-	return len;
+	return sysfs_emit(buf, "%s\n", output);
+}
+
+int memory_notify(enum memory_block_state state, void *v)
+{
+	return blocking_notifier_call_chain(&memory_chain, state, v);
+}
+
+#if defined(CONFIG_MEMORY_FAILURE) && defined(CONFIG_MEMORY_HOTPLUG)
+static unsigned long memblk_nr_poison(struct memory_block *mem);
+#else
+static inline unsigned long memblk_nr_poison(struct memory_block *mem)
+{
+	return 0;
+}
+#endif
+
+/*
+ * Must acquire mem_hotplug_lock in write mode.
+ */
+static int memory_block_online(struct memory_block *mem)
+{
+	unsigned long start_pfn = section_nr_to_pfn(mem->start_section_nr);
+	unsigned long nr_pages = PAGES_PER_SECTION * sections_per_block;
+	unsigned long nr_vmemmap_pages = 0;
+	struct zone *zone;
+	int ret;
+
+	if (memblk_nr_poison(mem))
+		return -EHWPOISON;
+
+	zone = zone_for_pfn_range(mem->online_type, mem->nid, mem->group,
+				  start_pfn, nr_pages);
+
+	/*
+	 * Although vmemmap pages have a different lifecycle than the pages
+	 * they describe (they remain until the memory is unplugged), doing
+	 * their initialization and accounting at memory onlining/offlining
+	 * stage helps to keep accounting easier to follow - e.g vmemmaps
+	 * belong to the same zone as the memory they backed.
+	 */
+	if (mem->altmap)
+		nr_vmemmap_pages = mem->altmap->free;
+
+	mem_hotplug_begin();
+	if (nr_vmemmap_pages) {
+		ret = mhp_init_memmap_on_memory(start_pfn, nr_vmemmap_pages, zone);
+		if (ret)
+			goto out;
+	}
+
+	ret = online_pages(start_pfn + nr_vmemmap_pages,
+			   nr_pages - nr_vmemmap_pages, zone, mem->group);
+	if (ret) {
+		if (nr_vmemmap_pages)
+			mhp_deinit_memmap_on_memory(start_pfn, nr_vmemmap_pages);
+		goto out;
+	}
+
+	/*
+	 * Account once onlining succeeded. If the zone was unpopulated, it is
+	 * now already properly populated.
+	 */
+	if (nr_vmemmap_pages)
+		adjust_present_page_count(pfn_to_page(start_pfn), mem->group,
+					  nr_vmemmap_pages);
+
+	mem->zone = zone;
+out:
+	mem_hotplug_done();
+	return ret;
 }
 
-int memory_notify(unsigned long val, void *v)
+/*
+ * Must acquire mem_hotplug_lock in write mode.
+ */
+static int memory_block_offline(struct memory_block *mem)
 {
-	return blocking_notifier_call_chain(&memory_chain, val, v);
+	unsigned long start_pfn = section_nr_to_pfn(mem->start_section_nr);
+	unsigned long nr_pages = PAGES_PER_SECTION * sections_per_block;
+	unsigned long nr_vmemmap_pages = 0;
+	int ret;
+
+	if (!mem->zone)
+		return -EINVAL;
+
+	/*
+	 * Unaccount before offlining, such that unpopulated zone and kthreads
+	 * can properly be torn down in offline_pages().
+	 */
+	if (mem->altmap)
+		nr_vmemmap_pages = mem->altmap->free;
+
+	mem_hotplug_begin();
+	if (nr_vmemmap_pages)
+		adjust_present_page_count(pfn_to_page(start_pfn), mem->group,
+					  -nr_vmemmap_pages);
+
+	ret = offline_pages(start_pfn + nr_vmemmap_pages,
+			    nr_pages - nr_vmemmap_pages, mem->zone, mem->group);
+	if (ret) {
+		/* offline_pages() failed. Account back. */
+		if (nr_vmemmap_pages)
+			adjust_present_page_count(pfn_to_page(start_pfn),
+						  mem->group, nr_vmemmap_pages);
+		goto out;
+	}
+
+	if (nr_vmemmap_pages)
+		mhp_deinit_memmap_on_memory(start_pfn, nr_vmemmap_pages);
+
+	mem->zone = NULL;
+out:
+	mem_hotplug_done();
+	return ret;
 }
 
 /*
@@ -167,25 +323,20 @@ int memory_notify(unsigned long val, void *v)
  * OK to have direct references to sparsemem variables in here.
  */
 static int
-memory_block_action(unsigned long start_section_nr, unsigned long action,
-		    int online_type, int nid)
+memory_block_action(struct memory_block *mem, unsigned long action)
 {
-	unsigned long start_pfn;
-	unsigned long nr_pages = PAGES_PER_SECTION * sections_per_block;
 	int ret;
 
-	start_pfn = section_nr_to_pfn(start_section_nr);
-
 	switch (action) {
 	case MEM_ONLINE:
-		ret = online_pages(start_pfn, nr_pages, online_type, nid);
+		ret = memory_block_online(mem);
 		break;
 	case MEM_OFFLINE:
-		ret = offline_pages(start_pfn, nr_pages);
+		ret = memory_block_offline(mem);
 		break;
 	default:
 		WARN(1, KERN_WARNING "%s(%ld, %ld) unknown action: "
-		     "%ld\n", __func__, start_section_nr, action, action);
+		     "%ld\n", __func__, mem->start_section_nr, action, action);
 		ret = -EINVAL;
 	}
 
@@ -203,9 +354,7 @@ static int memory_block_change_state(struct memory_block *mem,
 	if (to_state == MEM_OFFLINE)
 		mem->state = MEM_GOING_OFFLINE;
 
-	ret = memory_block_action(mem->start_section_nr, to_state,
-				  mem->online_type, mem->nid);
-
+	ret = memory_block_action(mem, to_state);
 	mem->state = ret ? from_state_req : to_state;
 
 	return ret;
@@ -246,7 +395,7 @@ static int memory_subsys_offline(struct device *dev)
 static ssize_t state_store(struct device *dev, struct device_attribute *attr,
 			   const char *buf, size_t count)
 {
-	const int online_type = memhp_online_type_from_str(buf);
+	const int online_type = mhp_online_type_from_str(buf);
 	struct memory_block *mem = to_memory_block(dev);
 	int ret;
 
@@ -283,33 +432,35 @@ static ssize_t state_store(struct device *dev, struct device_attribute *attr,
 }
 
 /*
- * phys_device is a bad name for this.  What I really want
- * is a way to differentiate between memory ranges that
- * are part of physical devices that constitute
- * a complete removable unit or fru.
- * i.e. do these ranges belong to the same physical device,
- * s.t. if I offline all of these sections I can then
- * remove the physical device?
+ * Legacy interface that we cannot remove: s390x exposes the storage increment
+ * covered by a memory block, allowing for identifying which memory blocks
+ * comprise a storage increment. Since a memory block spans complete
+ * storage increments nowadays, this interface is basically unused. Other
+ * archs never exposed != 0.
  */
 static ssize_t phys_device_show(struct device *dev,
 				struct device_attribute *attr, char *buf)
 {
 	struct memory_block *mem = to_memory_block(dev);
-	return sprintf(buf, "%d\n", mem->phys_device);
+	unsigned long start_pfn = section_nr_to_pfn(mem->start_section_nr);
+
+	return sysfs_emit(buf, "%d\n",
+			  arch_get_memory_phys_device(start_pfn));
 }
 
 #ifdef CONFIG_MEMORY_HOTREMOVE
-static void print_allowed_zone(char *buf, int nid, unsigned long start_pfn,
-		unsigned long nr_pages, int online_type,
-		struct zone *default_zone)
+static int print_allowed_zone(char *buf, int len, int nid,
+			      struct memory_group *group,
+			      unsigned long start_pfn, unsigned long nr_pages,
+			      int online_type, struct zone *default_zone)
 {
 	struct zone *zone;
 
-	zone = zone_for_pfn_range(online_type, nid, start_pfn, nr_pages);
-	if (zone != default_zone) {
-		strcat(buf, " ");
-		strcat(buf, zone->name);
-	}
+	zone = zone_for_pfn_range(online_type, nid, group, start_pfn, nr_pages);
+	if (zone == default_zone)
+		return 0;
+
+	return sysfs_emit_at(buf, len, " %s", zone->name);
 }
 
 static ssize_t valid_zones_show(struct device *dev,
@@ -318,8 +469,10 @@ static ssize_t valid_zones_show(struct device *dev,
 	struct memory_block *mem = to_memory_block(dev);
 	unsigned long start_pfn = section_nr_to_pfn(mem->start_section_nr);
 	unsigned long nr_pages = PAGES_PER_SECTION * sections_per_block;
+	struct memory_group *group = mem->group;
 	struct zone *default_zone;
-	int nid;
+	int nid = mem->nid;
+	int len;
 
 	/*
 	 * Check the existing zone. Make sure that we do that only on the
@@ -327,30 +480,23 @@ static ssize_t valid_zones_show(struct device *dev,
 	 */
 	if (mem->state == MEM_ONLINE) {
 		/*
-		 * The block contains more than one zone can not be offlined.
-		 * This can happen e.g. for ZONE_DMA and ZONE_DMA32
+		 * If !mem->zone, the memory block spans multiple zones and
+		 * cannot get offlined.
 		 */
-		default_zone = test_pages_in_a_zone(start_pfn,
-						    start_pfn + nr_pages);
-		if (!default_zone)
-			return sprintf(buf, "none\n");
-		strcat(buf, default_zone->name);
-		goto out;
+		return sysfs_emit(buf, "%s\n",
+				  mem->zone ? mem->zone->name : "none");
 	}
 
-	nid = mem->nid;
-	default_zone = zone_for_pfn_range(MMOP_ONLINE, nid, start_pfn,
-					  nr_pages);
-	strcat(buf, default_zone->name);
-
-	print_allowed_zone(buf, nid, start_pfn, nr_pages, MMOP_ONLINE_KERNEL,
-			default_zone);
-	print_allowed_zone(buf, nid, start_pfn, nr_pages, MMOP_ONLINE_MOVABLE,
-			default_zone);
-out:
-	strcat(buf, "\n");
+	default_zone = zone_for_pfn_range(MMOP_ONLINE, nid, group,
+					  start_pfn, nr_pages);
 
-	return strlen(buf);
+	len = sysfs_emit(buf, "%s", default_zone->name);
+	len += print_allowed_zone(buf, len, nid, group, start_pfn, nr_pages,
+				  MMOP_ONLINE_KERNEL, default_zone);
+	len += print_allowed_zone(buf, len, nid, group, start_pfn, nr_pages,
+				  MMOP_ONLINE_MOVABLE, default_zone);
+	len += sysfs_emit_at(buf, len, "\n");
+	return len;
 }
 static DEVICE_ATTR_RO(valid_zones);
 #endif
@@ -366,7 +512,7 @@ static DEVICE_ATTR_RO(removable);
 static ssize_t block_size_bytes_show(struct device *dev,
 				     struct device_attribute *attr, char *buf)
 {
-	return sprintf(buf, "%lx\n", memory_block_size_bytes());
+	return sysfs_emit(buf, "%lx\n", memory_block_size_bytes());
 }
 
 static DEVICE_ATTR_RO(block_size_bytes);
@@ -378,25 +524,35 @@ static DEVICE_ATTR_RO(block_size_bytes);
 static ssize_t auto_online_blocks_show(struct device *dev,
 				       struct device_attribute *attr, char *buf)
 {
-	return sprintf(buf, "%s\n",
-		       online_type_to_str[memhp_default_online_type]);
+	return sysfs_emit(buf, "%s\n",
+			  online_type_to_str[mhp_get_default_online_type()]);
 }
 
 static ssize_t auto_online_blocks_store(struct device *dev,
 					struct device_attribute *attr,
 					const char *buf, size_t count)
 {
-	const int online_type = memhp_online_type_from_str(buf);
+	const int online_type = mhp_online_type_from_str(buf);
 
 	if (online_type < 0)
 		return -EINVAL;
 
-	memhp_default_online_type = online_type;
+	mhp_set_default_online_type(online_type);
 	return count;
 }
 
 static DEVICE_ATTR_RW(auto_online_blocks);
 
+#ifdef CONFIG_CRASH_HOTPLUG
+#include <linux/kexec.h>
+static ssize_t crash_hotplug_show(struct device *dev,
+				       struct device_attribute *attr, char *buf)
+{
+	return sysfs_emit(buf, "%d\n", crash_check_hotplug_support());
+}
+static DEVICE_ATTR_RO(crash_hotplug);
+#endif
+
 /*
  * Some architectures will have custom drivers to do this, and
  * will not need to do it from userspace.  The fake hot-add code
@@ -424,7 +580,8 @@ static ssize_t probe_store(struct device *dev, struct device_attribute *attr,
 
 	nid = memory_add_physaddr_to_nid(phys_addr);
 	ret = __add_memory(nid, phys_addr,
-			   MIN_MEMORY_BLOCK_SIZE * sections_per_block);
+			   MIN_MEMORY_BLOCK_SIZE * sections_per_block,
+			   MHP_NONE);
 
 	if (ret)
 		goto out;
@@ -471,7 +628,9 @@ static ssize_t hard_offline_page_store(struct device *dev,
 	if (kstrtoull(buf, 0, &pfn) < 0)
 		return -EINVAL;
 	pfn >>= PAGE_SHIFT;
-	ret = memory_failure(pfn, 0);
+	ret = memory_failure(pfn, MF_SW_SIMULATED);
+	if (ret == -EOPNOTSUPP)
+		ret = 0;
 	return ret ? ret : count;
 }
 
@@ -479,36 +638,33 @@ static DEVICE_ATTR_WO(soft_offline_page);
 static DEVICE_ATTR_WO(hard_offline_page);
 #endif
 
-/*
- * Note that phys_device is optional.  It is here to allow for
- * differentiation between which *physical* devices each
- * section belongs to...
- */
+/* See phys_device_show(). */
 int __weak arch_get_memory_phys_device(unsigned long start_pfn)
 {
 	return 0;
 }
 
-/* A reference for the returned memory block device is acquired. */
-static struct memory_block *find_memory_block_by_id(unsigned long block_id)
+/*
+ * A reference for the returned memory block device is acquired.
+ *
+ * Called under device_hotplug_lock.
+ */
+struct memory_block *find_memory_block_by_id(unsigned long block_id)
 {
-	struct device *dev;
+	struct memory_block *mem;
 
-	dev = subsys_find_device_by_id(&memory_subsys, block_id, NULL);
-	return dev ? to_memory_block(dev) : NULL;
+	mem = xa_load(&memory_blocks, block_id);
+	if (mem)
+		get_device(&mem->dev);
+	return mem;
 }
 
 /*
- * For now, we have a linear search to go find the appropriate
- * memory_block corresponding to a particular phys_index. If
- * this gets to be a real problem, we can always use a radix
- * tree or something here.
- *
- * This could be made generic for all device subsystems.
+ * Called under device_hotplug_lock.
  */
-struct memory_block *find_memory_block(struct mem_section *section)
+struct memory_block *find_memory_block(unsigned long section_nr)
 {
-	unsigned long block_id = base_memory_block_id(__section_nr(section));
+	unsigned long block_id = memory_block_id(section_nr);
 
 	return find_memory_block_by_id(block_id);
 }
@@ -524,7 +680,7 @@ static struct attribute *memory_memblk_attrs[] = {
 	NULL
 };
 
-static struct attribute_group memory_memblk_attr_group = {
+static const struct attribute_group memory_memblk_attr_group = {
 	.attrs = memory_memblk_attrs,
 };
 
@@ -533,11 +689,7 @@ static const struct attribute_group *memory_memblk_attr_groups[] = {
 	NULL,
 };
 
-/*
- * register_memory - Setup a sysfs device for a memory block
- */
-static
-int register_memory(struct memory_block *memory)
+static int __add_memory_block(struct memory_block *memory)
 {
 	int ret;
 
@@ -548,17 +700,99 @@ int register_memory(struct memory_block *memory)
 	memory->dev.offline = memory->state == MEM_OFFLINE;
 
 	ret = device_register(&memory->dev);
-	if (ret)
+	if (ret) {
 		put_device(&memory->dev);
+		return ret;
+	}
+	ret = xa_err(xa_store(&memory_blocks, memory->dev.id, memory,
+			      GFP_KERNEL));
+	if (ret)
+		device_unregister(&memory->dev);
 
 	return ret;
 }
 
-static int init_memory_block(struct memory_block **memory,
-			     unsigned long block_id, unsigned long state)
+static struct zone *early_node_zone_for_memory_block(struct memory_block *mem,
+						     int nid)
+{
+	const unsigned long start_pfn = section_nr_to_pfn(mem->start_section_nr);
+	const unsigned long nr_pages = PAGES_PER_SECTION * sections_per_block;
+	struct zone *zone, *matching_zone = NULL;
+	pg_data_t *pgdat = NODE_DATA(nid);
+	int i;
+
+	/*
+	 * This logic only works for early memory, when the applicable zones
+	 * already span the memory block. We don't expect overlapping zones on
+	 * a single node for early memory. So if we're told that some PFNs
+	 * of a node fall into this memory block, we can assume that all node
+	 * zones that intersect with the memory block are actually applicable.
+	 * No need to look at the memmap.
+	 */
+	for (i = 0; i < MAX_NR_ZONES; i++) {
+		zone = pgdat->node_zones + i;
+		if (!populated_zone(zone))
+			continue;
+		if (!zone_intersects(zone, start_pfn, nr_pages))
+			continue;
+		if (!matching_zone) {
+			matching_zone = zone;
+			continue;
+		}
+		/* Spans multiple zones ... */
+		matching_zone = NULL;
+		break;
+	}
+	return matching_zone;
+}
+
+#ifdef CONFIG_NUMA
+/**
+ * memory_block_add_nid_early() - Indicate that early system RAM falling into
+ *				  this memory block device (partially) belongs
+ *				  to the given node.
+ * @mem: The memory block device.
+ * @nid: The node id.
+ *
+ * Indicate that early system RAM falling into this memory block (partially)
+ * belongs to the given node. This will also properly set/adjust mem->zone based
+ * on the zone ranges of the given node.
+ *
+ * Memory hotplug handles this on memory block creation, where we can only have
+ * a single nid span a memory block.
+ */
+void memory_block_add_nid_early(struct memory_block *mem, int nid)
+{
+	if (mem->nid != nid) {
+		/*
+		 * For early memory we have to determine the zone when setting
+		 * the node id and handle multiple nodes spanning a single
+		 * memory block by indicate via zone == NULL that we're not
+		 * dealing with a single zone. So if we're setting the node id
+		 * the first time, determine if there is a single zone. If we're
+		 * setting the node id a second time to a different node,
+		 * invalidate the single detected zone.
+		 */
+		if (mem->nid == NUMA_NO_NODE)
+			mem->zone = early_node_zone_for_memory_block(mem, nid);
+		else
+			mem->zone = NULL;
+		/*
+		 * If this memory block spans multiple nodes, we only indicate
+		 * the last processed node. If we span multiple nodes (not applicable
+		 * to hotplugged memory), zone == NULL will prohibit memory offlining
+		 * and consequently unplug.
+		 */
+		mem->nid = nid;
+	}
+}
+#endif
+
+static int add_memory_block(unsigned long block_id, int nid, unsigned long state,
+			    struct vmem_altmap *altmap,
+			    struct memory_group *group)
 {
 	struct memory_block *mem;
-	unsigned long start_pfn;
 	int ret = 0;
 
 	mem = find_memory_block_by_id(block_id);
@@ -572,38 +806,45 @@ static int init_memory_block(struct memory_block **memory,
 
 	mem->start_section_nr = block_id * sections_per_block;
 	mem->state = state;
-	start_pfn = section_nr_to_pfn(mem->start_section_nr);
-	mem->phys_device = arch_get_memory_phys_device(start_pfn);
-	mem->nid = NUMA_NO_NODE;
-
-	ret = register_memory(mem);
+	mem->nid = nid;
+	mem->altmap = altmap;
+	INIT_LIST_HEAD(&mem->group_next);
 
-	*memory = mem;
-	return ret;
-}
+#ifndef CONFIG_NUMA
+	if (state == MEM_ONLINE)
+		/*
+		 * MEM_ONLINE at this point implies early memory. With NUMA,
+		 * we'll determine the zone when setting the node id via
+		 * memory_block_add_nid(). Memory hotplug updated the zone
+		 * manually when memory onlining/offlining succeeds.
+		 */
+		mem->zone = early_node_zone_for_memory_block(mem, NUMA_NO_NODE);
+#endif /* CONFIG_NUMA */
 
-static int add_memory_block(unsigned long base_section_nr)
-{
-	int section_count = 0;
-	struct memory_block *mem;
-	unsigned long nr;
+	ret = __add_memory_block(mem);
+	if (ret)
+		return ret;
 
-	for (nr = base_section_nr; nr < base_section_nr + sections_per_block;
-	     nr++)
-		if (present_section_nr(nr))
-			section_count++;
+	if (group) {
+		mem->group = group;
+		list_add(&mem->group_next, &group->memory_blocks);
+	}
 
-	if (section_count == 0)
-		return 0;
-	return init_memory_block(&mem, base_memory_block_id(base_section_nr),
-				 MEM_ONLINE);
+	return 0;
 }
 
-static void unregister_memory(struct memory_block *memory)
+static void remove_memory_block(struct memory_block *memory)
 {
 	if (WARN_ON_ONCE(memory->dev.bus != &memory_subsys))
 		return;
 
+	WARN_ON(xa_erase(&memory_blocks, memory->dev.id) == NULL);
+
+	if (memory->group) {
+		list_del(&memory->group_next);
+		memory->group = NULL;
+	}
+
 	/* drop the ref. we got via find_memory_block() */
 	put_device(&memory->dev);
 	device_unregister(&memory->dev);
@@ -616,7 +857,9 @@ static void unregister_memory(struct memory_block *memory)
  *
  * Called under device_hotplug_lock.
  */
-int create_memory_block_devices(unsigned long start, unsigned long size)
+int create_memory_block_devices(unsigned long start, unsigned long size,
+				int nid, struct vmem_altmap *altmap,
+				struct memory_group *group)
 {
 	const unsigned long start_block_id = pfn_to_block_id(PFN_DOWN(start));
 	unsigned long end_block_id = pfn_to_block_id(PFN_DOWN(start + size));
@@ -629,7 +872,7 @@ int create_memory_block_devices(unsigned long start, unsigned long size)
 		return -EINVAL;
 
 	for (block_id = start_block_id; block_id != end_block_id; block_id++) {
-		ret = init_memory_block(&mem, block_id, MEM_OFFLINE);
+		ret = add_memory_block(block_id, nid, MEM_OFFLINE, altmap, group);
 		if (ret)
 			break;
 	}
@@ -640,7 +883,7 @@ int create_memory_block_devices(unsigned long start, unsigned long size)
 			mem = find_memory_block_by_id(block_id);
 			if (WARN_ON_ONCE(!mem))
 				continue;
-			unregister_memory(mem);
+			remove_memory_block(mem);
 		}
 	}
 	return ret;
@@ -668,17 +911,12 @@ void remove_memory_block_devices(unsigned long start, unsigned long size)
 		mem = find_memory_block_by_id(block_id);
 		if (WARN_ON_ONCE(!mem))
 			continue;
+		num_poisoned_pages_sub(-1UL, memblk_nr_poison(mem));
 		unregister_memory_block_under_nodes(mem);
-		unregister_memory(mem);
+		remove_memory_block(mem);
 	}
 }
 
-/* return true if the memory block is offlined, otherwise, return false */
-bool is_memblock_offlined(struct memory_block *mem)
-{
-	return mem->state == MEM_OFFLINE;
-}
-
 static struct attribute *memory_root_attrs[] = {
 #ifdef CONFIG_ARCH_MEMORY_PROBE
 	&dev_attr_probe.attr,
@@ -691,10 +929,13 @@ static struct attribute *memory_root_attrs[] = {
 
 	&dev_attr_block_size_bytes.attr,
 	&dev_attr_auto_online_blocks.attr,
+#ifdef CONFIG_CRASH_HOTPLUG
+	&dev_attr_crash_hotplug.attr,
+#endif
 	NULL
 };
 
-static struct attribute_group memory_root_attr_group = {
+static const struct attribute_group memory_root_attr_group = {
 	.attrs = memory_root_attrs,
 };
 
@@ -711,7 +952,7 @@ static const struct attribute_group *memory_root_attr_groups[] = {
 void __init memory_dev_init(void)
 {
 	int ret;
-	unsigned long block_sz, nr;
+	unsigned long block_sz, block_id, nr;
 
 	/* Validate the configured memory block size */
 	block_sz = memory_block_size_bytes();
@@ -724,15 +965,23 @@ void __init memory_dev_init(void)
 		panic("%s() failed to register subsystem: %d\n", __func__, ret);
 
 	/*
-	 * Create entries for memory sections that were found
-	 * during boot and have been initialized
+	 * Create entries for memory sections that were found during boot
+	 * and have been initialized. Use @block_id to track the last
+	 * handled block and initialize it to an invalid value (ULONG_MAX)
+	 * to bypass the block ID matching check for the first present
+	 * block so that it can be covered.
 	 */
-	for (nr = 0; nr <= __highest_present_section_nr;
-	     nr += sections_per_block) {
-		ret = add_memory_block(nr);
-		if (ret)
-			panic("%s() failed to add memory block: %d\n", __func__,
-			      ret);
+	block_id = ULONG_MAX;
+	for_each_present_section_nr(0, nr) {
+		if (block_id != ULONG_MAX && memory_block_id(nr) == block_id)
+			continue;
+
+		block_id = memory_block_id(nr);
+		ret = add_memory_block(block_id, NUMA_NO_NODE, MEM_ONLINE, NULL, NULL);
+		if (ret) {
+			panic("%s() failed to add memory block: %d\n",
+			      __func__, ret);
+		}
 	}
 }
 
@@ -750,6 +999,8 @@ void __init memory_dev_init(void)
  *
  * In case func() returns an error, walking is aborted and the error is
  * returned.
+ *
+ * Called under device_hotplug_lock.
  */
 int walk_memory_blocks(unsigned long start, unsigned long size,
 		       void *arg, walk_memory_blocks_func_t func)
@@ -811,3 +1062,189 @@ int for_each_memory_block(void *arg, walk_memory_blocks_func_t func)
 	return bus_for_each_dev(&memory_subsys, NULL, &cb_data,
 				for_each_memory_block_cb);
 }
+
+/*
+ * This is an internal helper to unify allocation and initialization of
+ * memory groups. Note that the passed memory group will be copied to a
+ * dynamically allocated memory group. After this call, the passed
+ * memory group should no longer be used.
+ */
+static int memory_group_register(struct memory_group group)
+{
+	struct memory_group *new_group;
+	uint32_t mgid;
+	int ret;
+
+	if (!node_possible(group.nid))
+		return -EINVAL;
+
+	new_group = kzalloc(sizeof(group), GFP_KERNEL);
+	if (!new_group)
+		return -ENOMEM;
+	*new_group = group;
+	INIT_LIST_HEAD(&new_group->memory_blocks);
+
+	ret = xa_alloc(&memory_groups, &mgid, new_group, xa_limit_31b,
+		       GFP_KERNEL);
+	if (ret) {
+		kfree(new_group);
+		return ret;
+	} else if (group.is_dynamic) {
+		xa_set_mark(&memory_groups, mgid, MEMORY_GROUP_MARK_DYNAMIC);
+	}
+	return mgid;
+}
+
+/**
+ * memory_group_register_static() - Register a static memory group.
+ * @nid: The node id.
+ * @max_pages: The maximum number of pages we'll have in this static memory
+ *	       group.
+ *
+ * Register a new static memory group and return the memory group id.
+ * All memory in the group belongs to a single unit, such as a DIMM. All
+ * memory belonging to a static memory group is added in one go to be removed
+ * in one go -- it's static.
+ *
+ * Returns an error if out of memory, if the node id is invalid, if no new
+ * memory groups can be registered, or if max_pages is invalid (0). Otherwise,
+ * returns the new memory group id.
+ */
+int memory_group_register_static(int nid, unsigned long max_pages)
+{
+	struct memory_group group = {
+		.nid = nid,
+		.s = {
+			.max_pages = max_pages,
+		},
+	};
+
+	if (!max_pages)
+		return -EINVAL;
+	return memory_group_register(group);
+}
+EXPORT_SYMBOL_GPL(memory_group_register_static);
+
+/**
+ * memory_group_register_dynamic() - Register a dynamic memory group.
+ * @nid: The node id.
+ * @unit_pages: Unit in pages in which is memory added/removed in this dynamic
+ *		memory group.
+ *
+ * Register a new dynamic memory group and return the memory group id.
+ * Memory within a dynamic memory group is added/removed dynamically
+ * in unit_pages.
+ *
+ * Returns an error if out of memory, if the node id is invalid, if no new
+ * memory groups can be registered, or if unit_pages is invalid (0, not a
+ * power of two, smaller than a single memory block). Otherwise, returns the
+ * new memory group id.
+ */
+int memory_group_register_dynamic(int nid, unsigned long unit_pages)
+{
+	struct memory_group group = {
+		.nid = nid,
+		.is_dynamic = true,
+		.d = {
+			.unit_pages = unit_pages,
+		},
+	};
+
+	if (!unit_pages || !is_power_of_2(unit_pages) ||
+	    unit_pages < PHYS_PFN(memory_block_size_bytes()))
+		return -EINVAL;
+	return memory_group_register(group);
+}
+EXPORT_SYMBOL_GPL(memory_group_register_dynamic);
+
+/**
+ * memory_group_unregister() - Unregister a memory group.
+ * @mgid: the memory group id
+ *
+ * Unregister a memory group. If any memory block still belongs to this
+ * memory group, unregistering will fail.
+ *
+ * Returns -EINVAL if the memory group id is invalid, returns -EBUSY if some
+ * memory blocks still belong to this memory group and returns 0 if
+ * unregistering succeeded.
+ */
+int memory_group_unregister(int mgid)
+{
+	struct memory_group *group;
+
+	if (mgid < 0)
+		return -EINVAL;
+
+	group = xa_load(&memory_groups, mgid);
+	if (!group)
+		return -EINVAL;
+	if (!list_empty(&group->memory_blocks))
+		return -EBUSY;
+	xa_erase(&memory_groups, mgid);
+	kfree(group);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(memory_group_unregister);
+
+/*
+ * This is an internal helper only to be used in core memory hotplug code to
+ * lookup a memory group. We don't care about locking, as we don't expect a
+ * memory group to get unregistered while adding memory to it -- because
+ * the group and the memory is managed by the same driver.
+ */
+struct memory_group *memory_group_find_by_id(int mgid)
+{
+	return xa_load(&memory_groups, mgid);
+}
+
+/*
+ * This is an internal helper only to be used in core memory hotplug code to
+ * walk all dynamic memory groups excluding a given memory group, either
+ * belonging to a specific node, or belonging to any node.
+ */
+int walk_dynamic_memory_groups(int nid, walk_memory_groups_func_t func,
+			       struct memory_group *excluded, void *arg)
+{
+	struct memory_group *group;
+	unsigned long index;
+	int ret = 0;
+
+	xa_for_each_marked(&memory_groups, index, group,
+			   MEMORY_GROUP_MARK_DYNAMIC) {
+		if (group == excluded)
+			continue;
+#ifdef CONFIG_NUMA
+		if (nid != NUMA_NO_NODE && group->nid != nid)
+			continue;
+#endif /* CONFIG_NUMA */
+		ret = func(group, arg);
+		if (ret)
+			break;
+	}
+	return ret;
+}
+
+#if defined(CONFIG_MEMORY_FAILURE) && defined(CONFIG_MEMORY_HOTPLUG)
+void memblk_nr_poison_inc(unsigned long pfn)
+{
+	const unsigned long block_id = pfn_to_block_id(pfn);
+	struct memory_block *mem = find_memory_block_by_id(block_id);
+
+	if (mem)
+		atomic_long_inc(&mem->nr_hwpoison);
+}
+
+void memblk_nr_poison_sub(unsigned long pfn, long i)
+{
+	const unsigned long block_id = pfn_to_block_id(pfn);
+	struct memory_block *mem = find_memory_block_by_id(block_id);
+
+	if (mem)
+		atomic_long_sub(i, &mem->nr_hwpoison);
+}
+
+static unsigned long memblk_nr_poison(struct memory_block *mem)
+{
+	return atomic_long_read(&mem->nr_hwpoison);
+}
+#endif
diff --git a/drivers/base/module.c b/drivers/base/module.c
index 46ad4d636731..218aaa096455 100644
--- a/drivers/base/module.c
+++ b/drivers/base/module.c
@@ -9,7 +9,7 @@
 #include <linux/string.h>
 #include "base.h"
 
-static char *make_driver_name(struct device_driver *drv)
+static char *make_driver_name(const struct device_driver *drv)
 {
 	char *driver_name;
 
@@ -30,46 +30,67 @@ static void module_create_drivers_dir(struct module_kobject *mk)
 	mutex_unlock(&drivers_dir_mutex);
 }
 
-void module_add_driver(struct module *mod, struct device_driver *drv)
+int module_add_driver(struct module *mod, const struct device_driver *drv)
 {
 	char *driver_name;
-	int no_warn;
 	struct module_kobject *mk = NULL;
+	int ret;
 
 	if (!drv)
-		return;
+		return 0;
 
 	if (mod)
 		mk = &mod->mkobj;
 	else if (drv->mod_name) {
-		struct kobject *mkobj;
-
-		/* Lookup built-in module entry in /sys/modules */
-		mkobj = kset_find_obj(module_kset, drv->mod_name);
-		if (mkobj) {
-			mk = container_of(mkobj, struct module_kobject, kobj);
+		/* Lookup or create built-in module entry in /sys/modules */
+		mk = lookup_or_create_module_kobject(drv->mod_name);
+		if (mk) {
 			/* remember our module structure */
 			drv->p->mkobj = mk;
-			/* kset_find_obj took a reference */
-			kobject_put(mkobj);
+			/* lookup_or_create_module_kobject took a reference */
+			kobject_put(&mk->kobj);
 		}
 	}
 
 	if (!mk)
-		return;
+		return 0;
+
+	ret = sysfs_create_link(&drv->p->kobj, &mk->kobj, "module");
+	if (ret)
+		return ret;
 
-	/* Don't check return codes; these calls are idempotent */
-	no_warn = sysfs_create_link(&drv->p->kobj, &mk->kobj, "module");
 	driver_name = make_driver_name(drv);
-	if (driver_name) {
-		module_create_drivers_dir(mk);
-		no_warn = sysfs_create_link(mk->drivers_dir, &drv->p->kobj,
-					    driver_name);
-		kfree(driver_name);
+	if (!driver_name) {
+		ret = -ENOMEM;
+		goto out_remove_kobj;
 	}
+
+	module_create_drivers_dir(mk);
+	if (!mk->drivers_dir) {
+		ret = -EINVAL;
+		goto out_free_driver_name;
+	}
+
+	ret = sysfs_create_link(mk->drivers_dir, &drv->p->kobj, driver_name);
+	if (ret)
+		goto out_remove_drivers_dir;
+
+	kfree(driver_name);
+
+	return 0;
+
+out_remove_drivers_dir:
+	sysfs_remove_link(mk->drivers_dir, driver_name);
+
+out_free_driver_name:
+	kfree(driver_name);
+
+out_remove_kobj:
+	sysfs_remove_link(&drv->p->kobj, "module");
+	return ret;
 }
 
-void module_remove_driver(struct device_driver *drv)
+void module_remove_driver(const struct device_driver *drv)
 {
 	struct module_kobject *mk = NULL;
 	char *driver_name;
diff --git a/drivers/base/node.c b/drivers/base/node.c
index 10d7e818e118..00cf4532f121 100644
--- a/drivers/base/node.c
+++ b/drivers/base/node.c
@@ -7,6 +7,7 @@
 #include <linux/init.h>
 #include <linux/mm.h>
 #include <linux/memory.h>
+#include <linux/mempolicy.h>
 #include <linux/vmstat.h>
 #include <linux/notifier.h>
 #include <linux/node.h>
@@ -20,45 +21,54 @@
 #include <linux/pm_runtime.h>
 #include <linux/swap.h>
 #include <linux/slab.h>
+#include <linux/memblock.h>
 
-static struct bus_type node_subsys = {
+static const struct bus_type node_subsys = {
 	.name = "node",
 	.dev_name = "node",
 };
 
-
-static ssize_t node_read_cpumap(struct device *dev, bool list, char *buf)
+static inline ssize_t cpumap_read(struct file *file, struct kobject *kobj,
+				  const struct bin_attribute *attr, char *buf,
+				  loff_t off, size_t count)
 {
-	ssize_t n;
-	cpumask_var_t mask;
+	struct device *dev = kobj_to_dev(kobj);
 	struct node *node_dev = to_node(dev);
-
-	/* 2008/04/07: buf currently PAGE_SIZE, need 9 chars per 32 bits. */
-	BUILD_BUG_ON((NR_CPUS/32 * 9) > (PAGE_SIZE-1));
+	cpumask_var_t mask;
+	ssize_t n;
 
 	if (!alloc_cpumask_var(&mask, GFP_KERNEL))
 		return 0;
 
 	cpumask_and(mask, cpumask_of_node(node_dev->dev.id), cpu_online_mask);
-	n = cpumap_print_to_pagebuf(list, buf, mask);
+	n = cpumap_print_bitmask_to_buf(buf, mask, off, count);
 	free_cpumask_var(mask);
 
 	return n;
 }
 
-static inline ssize_t node_read_cpumask(struct device *dev,
-				struct device_attribute *attr, char *buf)
-{
-	return node_read_cpumap(dev, false, buf);
-}
-static inline ssize_t node_read_cpulist(struct device *dev,
-				struct device_attribute *attr, char *buf)
+static const BIN_ATTR_RO(cpumap, CPUMAP_FILE_MAX_BYTES);
+
+static inline ssize_t cpulist_read(struct file *file, struct kobject *kobj,
+				   const struct bin_attribute *attr, char *buf,
+				   loff_t off, size_t count)
 {
-	return node_read_cpumap(dev, true, buf);
+	struct device *dev = kobj_to_dev(kobj);
+	struct node *node_dev = to_node(dev);
+	cpumask_var_t mask;
+	ssize_t n;
+
+	if (!alloc_cpumask_var(&mask, GFP_KERNEL))
+		return 0;
+
+	cpumask_and(mask, cpumask_of_node(node_dev->dev.id), cpu_online_mask);
+	n = cpumap_print_list_to_buf(buf, mask, off, count);
+	free_cpumask_var(mask);
+
+	return n;
 }
 
-static DEVICE_ATTR(cpumap,  S_IRUGO, node_read_cpumask, NULL);
-static DEVICE_ATTR(cpulist, S_IRUGO, node_read_cpulist, NULL);
+static const BIN_ATTR_RO(cpulist, CPULIST_FILE_MAX_BYTES);
 
 /**
  * struct node_access_nodes - Access class device to hold user visible
@@ -66,14 +76,14 @@ static DEVICE_ATTR(cpulist, S_IRUGO, node_read_cpulist, NULL);
  * @dev:	Device for this memory access class
  * @list_node:	List element in the node's access list
  * @access:	The access class rank
- * @hmem_attrs: Heterogeneous memory performance attributes
+ * @coord:	Heterogeneous memory performance coordinates
  */
 struct node_access_nodes {
 	struct device		dev;
 	struct list_head	list_node;
-	unsigned		access;
+	unsigned int		access;
 #ifdef CONFIG_HMEM_REPORTING
-	struct node_hmem_attrs	hmem_attrs;
+	struct access_coordinate	coord;
 #endif
 };
 #define to_access_nodes(dev) container_of(dev, struct node_access_nodes, dev)
@@ -102,6 +112,27 @@ static const struct attribute_group *node_access_node_groups[] = {
 	NULL,
 };
 
+#ifdef CONFIG_MEMORY_HOTPLUG
+static BLOCKING_NOTIFIER_HEAD(node_chain);
+
+int register_node_notifier(struct notifier_block *nb)
+{
+	return blocking_notifier_chain_register(&node_chain, nb);
+}
+EXPORT_SYMBOL(register_node_notifier);
+
+void unregister_node_notifier(struct notifier_block *nb)
+{
+	blocking_notifier_chain_unregister(&node_chain, nb);
+}
+EXPORT_SYMBOL(unregister_node_notifier);
+
+int node_notify(unsigned long val, void *v)
+{
+	return blocking_notifier_call_chain(&node_chain, val, v);
+}
+#endif
+
 static void node_remove_accesses(struct node *node)
 {
 	struct node_access_nodes *c, *cnext;
@@ -118,7 +149,7 @@ static void node_access_release(struct device *dev)
 }
 
 static struct node_access_nodes *node_init_node_access(struct node *node,
-						       unsigned access)
+						       enum access_coordinate_class access)
 {
 	struct node_access_nodes *access_node;
 	struct device *dev;
@@ -153,19 +184,20 @@ free:
 }
 
 #ifdef CONFIG_HMEM_REPORTING
-#define ACCESS_ATTR(name) 						   \
-static ssize_t name##_show(struct device *dev,				   \
-			   struct device_attribute *attr,		   \
-			   char *buf)					   \
-{									   \
-	return sprintf(buf, "%u\n", to_access_nodes(dev)->hmem_attrs.name); \
-}									   \
-static DEVICE_ATTR_RO(name);
+#define ACCESS_ATTR(property)						\
+static ssize_t property##_show(struct device *dev,			\
+			   struct device_attribute *attr,		\
+			   char *buf)					\
+{									\
+	return sysfs_emit(buf, "%u\n",					\
+			  to_access_nodes(dev)->coord.property);	\
+}									\
+static DEVICE_ATTR_RO(property)
 
-ACCESS_ATTR(read_bandwidth)
-ACCESS_ATTR(read_latency)
-ACCESS_ATTR(write_bandwidth)
-ACCESS_ATTR(write_latency)
+ACCESS_ATTR(read_bandwidth);
+ACCESS_ATTR(read_latency);
+ACCESS_ATTR(write_bandwidth);
+ACCESS_ATTR(write_latency);
 
 static struct attribute *access_attrs[] = {
 	&dev_attr_read_bandwidth.attr,
@@ -178,11 +210,11 @@ static struct attribute *access_attrs[] = {
 /**
  * node_set_perf_attrs - Set the performance values for given access class
  * @nid: Node identifier to be set
- * @hmem_attrs: Heterogeneous memory performance attributes
+ * @coord: Heterogeneous memory performance coordinates
  * @access: The access class the for the given attributes
  */
-void node_set_perf_attrs(unsigned int nid, struct node_hmem_attrs *hmem_attrs,
-			 unsigned access)
+void node_set_perf_attrs(unsigned int nid, struct access_coordinate *coord,
+			 enum access_coordinate_class access)
 {
 	struct node_access_nodes *c;
 	struct node *node;
@@ -196,7 +228,7 @@ void node_set_perf_attrs(unsigned int nid, struct node_hmem_attrs *hmem_attrs,
 	if (!c)
 		return;
 
-	c->hmem_attrs = *hmem_attrs;
+	c->coord = *coord;
 	for (i = 0; access_attrs[i] != NULL; i++) {
 		if (sysfs_add_file_to_group(&c->dev.kobj, access_attrs[i],
 					    "initiators")) {
@@ -205,7 +237,54 @@ void node_set_perf_attrs(unsigned int nid, struct node_hmem_attrs *hmem_attrs,
 			break;
 		}
 	}
+
+	/* When setting CPU access coordinates, update mempolicy */
+	if (access == ACCESS_COORDINATE_CPU) {
+		if (mempolicy_set_node_perf(nid, coord)) {
+			pr_info("failed to set mempolicy attrs for node %d\n",
+				nid);
+		}
+	}
+}
+EXPORT_SYMBOL_GPL(node_set_perf_attrs);
+
+/**
+ * node_update_perf_attrs - Update the performance values for given access class
+ * @nid: Node identifier to be updated
+ * @coord: Heterogeneous memory performance coordinates
+ * @access: The access class for the given attributes
+ */
+void node_update_perf_attrs(unsigned int nid, struct access_coordinate *coord,
+			    enum access_coordinate_class access)
+{
+	struct node_access_nodes *access_node;
+	struct node *node;
+	int i;
+
+	if (WARN_ON_ONCE(!node_online(nid)))
+		return;
+
+	node = node_devices[nid];
+	list_for_each_entry(access_node, &node->access_list, list_node) {
+		if (access_node->access != access)
+			continue;
+
+		access_node->coord = *coord;
+		for (i = 0; access_attrs[i]; i++) {
+			sysfs_notify(&access_node->dev.kobj,
+				     NULL, access_attrs[i]->name);
+		}
+		break;
+	}
+
+	/* When setting CPU access coordinates, update mempolicy */
+	if (access != ACCESS_COORDINATE_CPU)
+		return;
+
+	if (mempolicy_set_node_perf(nid, coord))
+		pr_info("failed to set mempolicy attrs for node %d\n", nid);
 }
+EXPORT_SYMBOL_GPL(node_update_perf_attrs);
 
 /**
  * struct node_cache_info - Internal tracking for memory node caches
@@ -225,20 +304,23 @@ static ssize_t name##_show(struct device *dev,				\
 			   struct device_attribute *attr,		\
 			   char *buf)					\
 {									\
-	return sprintf(buf, fmt "\n", to_cache_info(dev)->cache_attrs.name);\
+	return sysfs_emit(buf, fmt "\n",				\
+			  to_cache_info(dev)->cache_attrs.name);	\
 }									\
-DEVICE_ATTR_RO(name);
+static DEVICE_ATTR_RO(name);
 
 CACHE_ATTR(size, "%llu")
 CACHE_ATTR(line_size, "%u")
 CACHE_ATTR(indexing, "%u")
 CACHE_ATTR(write_policy, "%u")
+CACHE_ATTR(address_mode, "%#x")
 
 static struct attribute *cache_attrs[] = {
 	&dev_attr_indexing.attr,
 	&dev_attr_size.attr,
 	&dev_attr_line_size.attr,
 	&dev_attr_write_policy.attr,
+	&dev_attr_address_mode.attr,
 	NULL,
 };
 ATTRIBUTE_GROUPS(cache);
@@ -262,21 +344,20 @@ static void node_init_cache_dev(struct node *node)
 	if (!dev)
 		return;
 
+	device_initialize(dev);
 	dev->parent = &node->dev;
 	dev->release = node_cache_release;
 	if (dev_set_name(dev, "memory_side_cache"))
-		goto free_dev;
+		goto put_device;
 
-	if (device_register(dev))
-		goto free_name;
+	if (device_add(dev))
+		goto put_device;
 
 	pm_runtime_no_callbacks(dev);
 	node->cache_dev = dev;
 	return;
-free_name:
-	kfree_const(dev->kobj.name);
-free_dev:
-	kfree(dev);
+put_device:
+	put_device(dev);
 }
 
 /**
@@ -313,25 +394,24 @@ void node_add_cache(unsigned int nid, struct node_cache_attrs *cache_attrs)
 		return;
 
 	dev = &info->dev;
+	device_initialize(dev);
 	dev->parent = node->cache_dev;
 	dev->release = node_cacheinfo_release;
 	dev->groups = cache_groups;
 	if (dev_set_name(dev, "index%d", cache_attrs->level))
-		goto free_cache;
+		goto put_device;
 
 	info->cache_attrs = *cache_attrs;
-	if (device_register(dev)) {
+	if (device_add(dev)) {
 		dev_warn(&node->dev, "failed to add cache level:%d\n",
 			 cache_attrs->level);
-		goto free_name;
+		goto put_device;
 	}
 	pm_runtime_no_callbacks(dev);
 	list_add_tail(&info->node, &node->cache_attrs);
 	return;
-free_name:
-	kfree_const(dev->kobj.name);
-free_cache:
-	kfree(info);
+put_device:
+	put_device(dev);
 }
 
 static void node_remove_caches(struct node *node)
@@ -361,131 +441,148 @@ static void node_remove_caches(struct node *node) { }
 static ssize_t node_read_meminfo(struct device *dev,
 			struct device_attribute *attr, char *buf)
 {
-	int n;
+	int len = 0;
 	int nid = dev->id;
 	struct pglist_data *pgdat = NODE_DATA(nid);
 	struct sysinfo i;
 	unsigned long sreclaimable, sunreclaimable;
+	unsigned long swapcached = 0;
 
 	si_meminfo_node(&i, nid);
-	sreclaimable = node_page_state(pgdat, NR_SLAB_RECLAIMABLE);
-	sunreclaimable = node_page_state(pgdat, NR_SLAB_UNRECLAIMABLE);
-	n = sprintf(buf,
-		       "Node %d MemTotal:       %8lu kB\n"
-		       "Node %d MemFree:        %8lu kB\n"
-		       "Node %d MemUsed:        %8lu kB\n"
-		       "Node %d Active:         %8lu kB\n"
-		       "Node %d Inactive:       %8lu kB\n"
-		       "Node %d Active(anon):   %8lu kB\n"
-		       "Node %d Inactive(anon): %8lu kB\n"
-		       "Node %d Active(file):   %8lu kB\n"
-		       "Node %d Inactive(file): %8lu kB\n"
-		       "Node %d Unevictable:    %8lu kB\n"
-		       "Node %d Mlocked:        %8lu kB\n",
-		       nid, K(i.totalram),
-		       nid, K(i.freeram),
-		       nid, K(i.totalram - i.freeram),
-		       nid, K(node_page_state(pgdat, NR_ACTIVE_ANON) +
-				node_page_state(pgdat, NR_ACTIVE_FILE)),
-		       nid, K(node_page_state(pgdat, NR_INACTIVE_ANON) +
-				node_page_state(pgdat, NR_INACTIVE_FILE)),
-		       nid, K(node_page_state(pgdat, NR_ACTIVE_ANON)),
-		       nid, K(node_page_state(pgdat, NR_INACTIVE_ANON)),
-		       nid, K(node_page_state(pgdat, NR_ACTIVE_FILE)),
-		       nid, K(node_page_state(pgdat, NR_INACTIVE_FILE)),
-		       nid, K(node_page_state(pgdat, NR_UNEVICTABLE)),
-		       nid, K(sum_zone_node_page_state(nid, NR_MLOCK)));
+	sreclaimable = node_page_state_pages(pgdat, NR_SLAB_RECLAIMABLE_B);
+	sunreclaimable = node_page_state_pages(pgdat, NR_SLAB_UNRECLAIMABLE_B);
+#ifdef CONFIG_SWAP
+	swapcached = node_page_state_pages(pgdat, NR_SWAPCACHE);
+#endif
+	len = sysfs_emit_at(buf, len,
+			    "Node %d MemTotal:       %8lu kB\n"
+			    "Node %d MemFree:        %8lu kB\n"
+			    "Node %d MemUsed:        %8lu kB\n"
+			    "Node %d SwapCached:     %8lu kB\n"
+			    "Node %d Active:         %8lu kB\n"
+			    "Node %d Inactive:       %8lu kB\n"
+			    "Node %d Active(anon):   %8lu kB\n"
+			    "Node %d Inactive(anon): %8lu kB\n"
+			    "Node %d Active(file):   %8lu kB\n"
+			    "Node %d Inactive(file): %8lu kB\n"
+			    "Node %d Unevictable:    %8lu kB\n"
+			    "Node %d Mlocked:        %8lu kB\n",
+			    nid, K(i.totalram),
+			    nid, K(i.freeram),
+			    nid, K(i.totalram - i.freeram),
+			    nid, K(swapcached),
+			    nid, K(node_page_state(pgdat, NR_ACTIVE_ANON) +
+				   node_page_state(pgdat, NR_ACTIVE_FILE)),
+			    nid, K(node_page_state(pgdat, NR_INACTIVE_ANON) +
+				   node_page_state(pgdat, NR_INACTIVE_FILE)),
+			    nid, K(node_page_state(pgdat, NR_ACTIVE_ANON)),
+			    nid, K(node_page_state(pgdat, NR_INACTIVE_ANON)),
+			    nid, K(node_page_state(pgdat, NR_ACTIVE_FILE)),
+			    nid, K(node_page_state(pgdat, NR_INACTIVE_FILE)),
+			    nid, K(node_page_state(pgdat, NR_UNEVICTABLE)),
+			    nid, K(sum_zone_node_page_state(nid, NR_MLOCK)));
 
 #ifdef CONFIG_HIGHMEM
-	n += sprintf(buf + n,
-		       "Node %d HighTotal:      %8lu kB\n"
-		       "Node %d HighFree:       %8lu kB\n"
-		       "Node %d LowTotal:       %8lu kB\n"
-		       "Node %d LowFree:        %8lu kB\n",
-		       nid, K(i.totalhigh),
-		       nid, K(i.freehigh),
-		       nid, K(i.totalram - i.totalhigh),
-		       nid, K(i.freeram - i.freehigh));
+	len += sysfs_emit_at(buf, len,
+			     "Node %d HighTotal:      %8lu kB\n"
+			     "Node %d HighFree:       %8lu kB\n"
+			     "Node %d LowTotal:       %8lu kB\n"
+			     "Node %d LowFree:        %8lu kB\n",
+			     nid, K(i.totalhigh),
+			     nid, K(i.freehigh),
+			     nid, K(i.totalram - i.totalhigh),
+			     nid, K(i.freeram - i.freehigh));
 #endif
-	n += sprintf(buf + n,
-		       "Node %d Dirty:          %8lu kB\n"
-		       "Node %d Writeback:      %8lu kB\n"
-		       "Node %d FilePages:      %8lu kB\n"
-		       "Node %d Mapped:         %8lu kB\n"
-		       "Node %d AnonPages:      %8lu kB\n"
-		       "Node %d Shmem:          %8lu kB\n"
-		       "Node %d KernelStack:    %8lu kB\n"
-		       "Node %d PageTables:     %8lu kB\n"
-		       "Node %d NFS_Unstable:   %8lu kB\n"
-		       "Node %d Bounce:         %8lu kB\n"
-		       "Node %d WritebackTmp:   %8lu kB\n"
-		       "Node %d KReclaimable:   %8lu kB\n"
-		       "Node %d Slab:           %8lu kB\n"
-		       "Node %d SReclaimable:   %8lu kB\n"
-		       "Node %d SUnreclaim:     %8lu kB\n"
+	len += sysfs_emit_at(buf, len,
+			     "Node %d Dirty:          %8lu kB\n"
+			     "Node %d Writeback:      %8lu kB\n"
+			     "Node %d FilePages:      %8lu kB\n"
+			     "Node %d Mapped:         %8lu kB\n"
+			     "Node %d AnonPages:      %8lu kB\n"
+			     "Node %d Shmem:          %8lu kB\n"
+			     "Node %d KernelStack:    %8lu kB\n"
+#ifdef CONFIG_SHADOW_CALL_STACK
+			     "Node %d ShadowCallStack:%8lu kB\n"
+#endif
+			     "Node %d PageTables:     %8lu kB\n"
+			     "Node %d SecPageTables:  %8lu kB\n"
+			     "Node %d NFS_Unstable:   %8lu kB\n"
+			     "Node %d Bounce:         %8lu kB\n"
+			     "Node %d WritebackTmp:   %8lu kB\n"
+			     "Node %d KReclaimable:   %8lu kB\n"
+			     "Node %d Slab:           %8lu kB\n"
+			     "Node %d SReclaimable:   %8lu kB\n"
+			     "Node %d SUnreclaim:     %8lu kB\n"
 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
-		       "Node %d AnonHugePages:  %8lu kB\n"
-		       "Node %d ShmemHugePages: %8lu kB\n"
-		       "Node %d ShmemPmdMapped: %8lu kB\n"
-		       "Node %d FileHugePages: %8lu kB\n"
-		       "Node %d FilePmdMapped: %8lu kB\n"
+			     "Node %d AnonHugePages:  %8lu kB\n"
+			     "Node %d ShmemHugePages: %8lu kB\n"
+			     "Node %d ShmemPmdMapped: %8lu kB\n"
+			     "Node %d FileHugePages:  %8lu kB\n"
+			     "Node %d FilePmdMapped:  %8lu kB\n"
+#endif
+#ifdef CONFIG_UNACCEPTED_MEMORY
+			     "Node %d Unaccepted:     %8lu kB\n"
+#endif
+			     ,
+			     nid, K(node_page_state(pgdat, NR_FILE_DIRTY)),
+			     nid, K(node_page_state(pgdat, NR_WRITEBACK)),
+			     nid, K(node_page_state(pgdat, NR_FILE_PAGES)),
+			     nid, K(node_page_state(pgdat, NR_FILE_MAPPED)),
+			     nid, K(node_page_state(pgdat, NR_ANON_MAPPED)),
+			     nid, K(i.sharedram),
+			     nid, node_page_state(pgdat, NR_KERNEL_STACK_KB),
+#ifdef CONFIG_SHADOW_CALL_STACK
+			     nid, node_page_state(pgdat, NR_KERNEL_SCS_KB),
 #endif
-			,
-		       nid, K(node_page_state(pgdat, NR_FILE_DIRTY)),
-		       nid, K(node_page_state(pgdat, NR_WRITEBACK)),
-		       nid, K(node_page_state(pgdat, NR_FILE_PAGES)),
-		       nid, K(node_page_state(pgdat, NR_FILE_MAPPED)),
-		       nid, K(node_page_state(pgdat, NR_ANON_MAPPED)),
-		       nid, K(i.sharedram),
-		       nid, sum_zone_node_page_state(nid, NR_KERNEL_STACK_KB),
-		       nid, K(sum_zone_node_page_state(nid, NR_PAGETABLE)),
-		       nid, K(node_page_state(pgdat, NR_UNSTABLE_NFS)),
-		       nid, K(sum_zone_node_page_state(nid, NR_BOUNCE)),
-		       nid, K(node_page_state(pgdat, NR_WRITEBACK_TEMP)),
-		       nid, K(sreclaimable +
-			      node_page_state(pgdat, NR_KERNEL_MISC_RECLAIMABLE)),
-		       nid, K(sreclaimable + sunreclaimable),
-		       nid, K(sreclaimable),
-		       nid, K(sunreclaimable)
+			     nid, K(node_page_state(pgdat, NR_PAGETABLE)),
+			     nid, K(node_page_state(pgdat, NR_SECONDARY_PAGETABLE)),
+			     nid, 0UL,
+			     nid, 0UL,
+			     nid, 0UL,
+			     nid, K(sreclaimable +
+				    node_page_state(pgdat, NR_KERNEL_MISC_RECLAIMABLE)),
+			     nid, K(sreclaimable + sunreclaimable),
+			     nid, K(sreclaimable),
+			     nid, K(sunreclaimable)
 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
-		       ,
-		       nid, K(node_page_state(pgdat, NR_ANON_THPS) *
-				       HPAGE_PMD_NR),
-		       nid, K(node_page_state(pgdat, NR_SHMEM_THPS) *
-				       HPAGE_PMD_NR),
-		       nid, K(node_page_state(pgdat, NR_SHMEM_PMDMAPPED) *
-				       HPAGE_PMD_NR),
-		       nid, K(node_page_state(pgdat, NR_FILE_THPS) *
-				       HPAGE_PMD_NR),
-		       nid, K(node_page_state(pgdat, NR_FILE_PMDMAPPED) *
-				       HPAGE_PMD_NR)
+			     ,
+			     nid, K(node_page_state(pgdat, NR_ANON_THPS)),
+			     nid, K(node_page_state(pgdat, NR_SHMEM_THPS)),
+			     nid, K(node_page_state(pgdat, NR_SHMEM_PMDMAPPED)),
+			     nid, K(node_page_state(pgdat, NR_FILE_THPS)),
+			     nid, K(node_page_state(pgdat, NR_FILE_PMDMAPPED))
 #endif
-		       );
-	n += hugetlb_report_node_meminfo(nid, buf + n);
-	return n;
+#ifdef CONFIG_UNACCEPTED_MEMORY
+			     ,
+			     nid, K(sum_zone_node_page_state(nid, NR_UNACCEPTED))
+#endif
+			    );
+	len += hugetlb_report_node_meminfo(buf, len, nid);
+	return len;
 }
 
 #undef K
-static DEVICE_ATTR(meminfo, S_IRUGO, node_read_meminfo, NULL);
+static DEVICE_ATTR(meminfo, 0444, node_read_meminfo, NULL);
 
 static ssize_t node_read_numastat(struct device *dev,
-				struct device_attribute *attr, char *buf)
-{
-	return sprintf(buf,
-		       "numa_hit %lu\n"
-		       "numa_miss %lu\n"
-		       "numa_foreign %lu\n"
-		       "interleave_hit %lu\n"
-		       "local_node %lu\n"
-		       "other_node %lu\n",
-		       sum_zone_numa_state(dev->id, NUMA_HIT),
-		       sum_zone_numa_state(dev->id, NUMA_MISS),
-		       sum_zone_numa_state(dev->id, NUMA_FOREIGN),
-		       sum_zone_numa_state(dev->id, NUMA_INTERLEAVE_HIT),
-		       sum_zone_numa_state(dev->id, NUMA_LOCAL),
-		       sum_zone_numa_state(dev->id, NUMA_OTHER));
-}
-static DEVICE_ATTR(numastat, S_IRUGO, node_read_numastat, NULL);
+				  struct device_attribute *attr, char *buf)
+{
+	fold_vm_numa_events();
+	return sysfs_emit(buf,
+			  "numa_hit %lu\n"
+			  "numa_miss %lu\n"
+			  "numa_foreign %lu\n"
+			  "interleave_hit %lu\n"
+			  "local_node %lu\n"
+			  "other_node %lu\n",
+			  sum_zone_numa_event_state(dev->id, NUMA_HIT),
+			  sum_zone_numa_event_state(dev->id, NUMA_MISS),
+			  sum_zone_numa_event_state(dev->id, NUMA_FOREIGN),
+			  sum_zone_numa_event_state(dev->id, NUMA_INTERLEAVE_HIT),
+			  sum_zone_numa_event_state(dev->id, NUMA_LOCAL),
+			  sum_zone_numa_event_state(dev->id, NUMA_OTHER));
+}
+static DEVICE_ATTR(numastat, 0444, node_read_numastat, NULL);
 
 static ssize_t node_read_vmstat(struct device *dev,
 				struct device_attribute *attr, char *buf)
@@ -493,28 +590,36 @@ static ssize_t node_read_vmstat(struct device *dev,
 	int nid = dev->id;
 	struct pglist_data *pgdat = NODE_DATA(nid);
 	int i;
-	int n = 0;
+	int len = 0;
 
 	for (i = 0; i < NR_VM_ZONE_STAT_ITEMS; i++)
-		n += sprintf(buf+n, "%s %lu\n", zone_stat_name(i),
-			     sum_zone_node_page_state(nid, i));
+		len += sysfs_emit_at(buf, len, "%s %lu\n",
+				     zone_stat_name(i),
+				     sum_zone_node_page_state(nid, i));
 
 #ifdef CONFIG_NUMA
-	for (i = 0; i < NR_VM_NUMA_STAT_ITEMS; i++)
-		n += sprintf(buf+n, "%s %lu\n", numa_stat_name(i),
-			     sum_zone_numa_state(nid, i));
+	fold_vm_numa_events();
+	for (i = 0; i < NR_VM_NUMA_EVENT_ITEMS; i++)
+		len += sysfs_emit_at(buf, len, "%s %lu\n",
+				     numa_stat_name(i),
+				     sum_zone_numa_event_state(nid, i));
+
 #endif
+	for (i = 0; i < NR_VM_NODE_STAT_ITEMS; i++) {
+		unsigned long pages = node_page_state_pages(pgdat, i);
 
-	for (i = 0; i < NR_VM_NODE_STAT_ITEMS; i++)
-		n += sprintf(buf+n, "%s %lu\n", node_stat_name(i),
-			     node_page_state(pgdat, i));
+		if (vmstat_item_print_in_thp(i))
+			pages /= HPAGE_PMD_NR;
+		len += sysfs_emit_at(buf, len, "%s %lu\n", node_stat_name(i),
+				     pages);
+	}
 
-	return n;
+	return len;
 }
-static DEVICE_ATTR(vmstat, S_IRUGO, node_read_vmstat, NULL);
+static DEVICE_ATTR(vmstat, 0444, node_read_vmstat, NULL);
 
 static ssize_t node_read_distance(struct device *dev,
-			struct device_attribute *attr, char *buf)
+				  struct device_attribute *attr, char *buf)
 {
 	int nid = dev->id;
 	int len = 0;
@@ -526,124 +631,49 @@ static ssize_t node_read_distance(struct device *dev,
 	 */
 	BUILD_BUG_ON(MAX_NUMNODES * 4 > PAGE_SIZE);
 
-	for_each_online_node(i)
-		len += sprintf(buf + len, "%s%d", i ? " " : "", node_distance(nid, i));
+	for_each_online_node(i) {
+		len += sysfs_emit_at(buf, len, "%s%d",
+				     i ? " " : "", node_distance(nid, i));
+	}
 
-	len += sprintf(buf + len, "\n");
+	len += sysfs_emit_at(buf, len, "\n");
 	return len;
 }
-static DEVICE_ATTR(distance, S_IRUGO, node_read_distance, NULL);
+static DEVICE_ATTR(distance, 0444, node_read_distance, NULL);
 
 static struct attribute *node_dev_attrs[] = {
-	&dev_attr_cpumap.attr,
-	&dev_attr_cpulist.attr,
 	&dev_attr_meminfo.attr,
 	&dev_attr_numastat.attr,
 	&dev_attr_distance.attr,
 	&dev_attr_vmstat.attr,
 	NULL
 };
-ATTRIBUTE_GROUPS(node_dev);
 
-#ifdef CONFIG_HUGETLBFS
-/*
- * hugetlbfs per node attributes registration interface:
- * When/if hugetlb[fs] subsystem initializes [sometime after this module],
- * it will register its per node attributes for all online nodes with
- * memory.  It will also call register_hugetlbfs_with_node(), below, to
- * register its attribute registration functions with this node driver.
- * Once these hooks have been initialized, the node driver will call into
- * the hugetlb module to [un]register attributes for hot-plugged nodes.
- */
-static node_registration_func_t __hugetlb_register_node;
-static node_registration_func_t __hugetlb_unregister_node;
-
-static inline bool hugetlb_register_node(struct node *node)
-{
-	if (__hugetlb_register_node &&
-			node_state(node->dev.id, N_MEMORY)) {
-		__hugetlb_register_node(node);
-		return true;
-	}
-	return false;
-}
-
-static inline void hugetlb_unregister_node(struct node *node)
-{
-	if (__hugetlb_unregister_node)
-		__hugetlb_unregister_node(node);
-}
+static const struct bin_attribute *node_dev_bin_attrs[] = {
+	&bin_attr_cpumap,
+	&bin_attr_cpulist,
+	NULL
+};
 
-void register_hugetlbfs_with_node(node_registration_func_t doregister,
-				  node_registration_func_t unregister)
-{
-	__hugetlb_register_node   = doregister;
-	__hugetlb_unregister_node = unregister;
-}
-#else
-static inline void hugetlb_register_node(struct node *node) {}
+static const struct attribute_group node_dev_group = {
+	.attrs = node_dev_attrs,
+	.bin_attrs = node_dev_bin_attrs,
+};
 
-static inline void hugetlb_unregister_node(struct node *node) {}
+static const struct attribute_group *node_dev_groups[] = {
+	&node_dev_group,
+#ifdef CONFIG_HAVE_ARCH_NODE_DEV_GROUP
+	&arch_node_dev_group,
 #endif
-
-static void node_device_release(struct device *dev)
-{
-	struct node *node = to_node(dev);
-
-#if defined(CONFIG_MEMORY_HOTPLUG_SPARSE) && defined(CONFIG_HUGETLBFS)
-	/*
-	 * We schedule the work only when a memory section is
-	 * onlined/offlined on this node. When we come here,
-	 * all the memory on this node has been offlined,
-	 * so we won't enqueue new work to this work.
-	 *
-	 * The work is using node->node_work, so we should
-	 * flush work before freeing the memory.
-	 */
-	flush_work(&node->node_work);
+#ifdef CONFIG_MEMORY_FAILURE
+	&memory_failure_attr_group,
 #endif
-	kfree(node);
-}
-
-/*
- * register_node - Setup a sysfs device for a node.
- * @num - Node number to use when creating the device.
- *
- * Initialize and register the node device.
- */
-static int register_node(struct node *node, int num)
-{
-	int error;
-
-	node->dev.id = num;
-	node->dev.bus = &node_subsys;
-	node->dev.release = node_device_release;
-	node->dev.groups = node_dev_groups;
-	error = device_register(&node->dev);
-
-	if (error)
-		put_device(&node->dev);
-	else {
-		hugetlb_register_node(node);
-
-		compaction_register_node(node);
-	}
-	return error;
-}
+	NULL
+};
 
-/**
- * unregister_node - unregister a node device
- * @node: node going away
- *
- * Unregisters a node device @node.  All the devices on the node must be
- * unregistered before calling this function.
- */
-void unregister_node(struct node *node)
+static void node_device_release(struct device *dev)
 {
-	hugetlb_unregister_node(node);		/* no-op, if memoryless node */
-	node_remove_accesses(node);
-	node_remove_caches(node);
-	device_unregister(&node->dev);
+	kfree(to_node(dev));
 }
 
 struct node *node_devices[MAX_NUMNODES];
@@ -689,7 +719,7 @@ int register_cpu_under_node(unsigned int cpu, unsigned int nid)
  */
 int register_memory_node_under_compute_node(unsigned int mem_nid,
 					    unsigned int cpu_nid,
-					    unsigned access)
+					    enum access_coordinate_class access)
 {
 	struct node *init_node, *targ_node;
 	struct node_access_nodes *initiator, *target;
@@ -743,71 +773,40 @@ int unregister_cpu_under_node(unsigned int cpu, unsigned int nid)
 	return 0;
 }
 
-#ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
-static int __ref get_nid_for_pfn(unsigned long pfn)
-{
-	if (!pfn_valid_within(pfn))
-		return -1;
-#ifdef CONFIG_DEFERRED_STRUCT_PAGE_INIT
-	if (system_state < SYSTEM_RUNNING)
-		return early_pfn_to_nid(pfn);
-#endif
-	return pfn_to_nid(pfn);
-}
-
-/* register memory section under specified node if it spans that node */
-static int register_mem_sect_under_node(struct memory_block *mem_blk,
-					 void *arg)
+#ifdef CONFIG_MEMORY_HOTPLUG
+static void do_register_memory_block_under_node(int nid,
+						struct memory_block *mem_blk)
 {
-	unsigned long memory_block_pfns = memory_block_size_bytes() / PAGE_SIZE;
-	unsigned long start_pfn = section_nr_to_pfn(mem_blk->start_section_nr);
-	unsigned long end_pfn = start_pfn + memory_block_pfns - 1;
-	int ret, nid = *(int *)arg;
-	unsigned long pfn;
-
-	for (pfn = start_pfn; pfn <= end_pfn; pfn++) {
-		int page_nid;
-
-		/*
-		 * memory block could have several absent sections from start.
-		 * skip pfn range from absent section
-		 */
-		if (!pfn_in_present_section(pfn)) {
-			pfn = round_down(pfn + PAGES_PER_SECTION,
-					 PAGES_PER_SECTION) - 1;
-			continue;
-		}
-
-		/*
-		 * We need to check if page belongs to nid only for the boot
-		 * case, during hotplug we know that all pages in the memory
-		 * block belong to the same node.
-		 */
-		if (system_state == SYSTEM_BOOTING) {
-			page_nid = get_nid_for_pfn(pfn);
-			if (page_nid < 0)
-				continue;
-			if (page_nid != nid)
-				continue;
-		}
+	int ret;
 
-		/*
-		 * If this memory block spans multiple nodes, we only indicate
-		 * the last processed node.
-		 */
-		mem_blk->nid = nid;
+	ret = sysfs_create_link_nowarn(&node_devices[nid]->dev.kobj,
+				       &mem_blk->dev.kobj,
+				       kobject_name(&mem_blk->dev.kobj));
+	if (ret && ret != -EEXIST)
+		dev_err_ratelimited(&node_devices[nid]->dev,
+				    "can't create link to %s in sysfs (%d)\n",
+				    kobject_name(&mem_blk->dev.kobj), ret);
 
-		ret = sysfs_create_link_nowarn(&node_devices[nid]->dev.kobj,
-					&mem_blk->dev.kobj,
-					kobject_name(&mem_blk->dev.kobj));
-		if (ret)
-			return ret;
-
-		return sysfs_create_link_nowarn(&mem_blk->dev.kobj,
+	ret = sysfs_create_link_nowarn(&mem_blk->dev.kobj,
 				&node_devices[nid]->dev.kobj,
 				kobject_name(&node_devices[nid]->dev.kobj));
-	}
-	/* mem section does not span the specified node */
+	if (ret && ret != -EEXIST)
+		dev_err_ratelimited(&mem_blk->dev,
+				    "can't create link to %s in sysfs (%d)\n",
+				    kobject_name(&node_devices[nid]->dev.kobj),
+				    ret);
+}
+
+/*
+ * During hotplug we know that all pages in the memory block belong to the same
+ * node.
+ */
+static int register_mem_block_under_node_hotplug(struct memory_block *mem_blk,
+						 void *arg)
+{
+	int nid = *(int *)arg;
+
+	do_register_memory_block_under_node(nid, mem_blk);
 	return 0;
 }
 
@@ -826,91 +825,77 @@ void unregister_memory_block_under_nodes(struct memory_block *mem_blk)
 			  kobject_name(&node_devices[mem_blk->nid]->dev.kobj));
 }
 
-int link_mem_sections(int nid, unsigned long start_pfn, unsigned long end_pfn)
+/* register all memory blocks under the corresponding nodes */
+static void register_memory_blocks_under_nodes(void)
 {
-	return walk_memory_blocks(PFN_PHYS(start_pfn),
-				  PFN_PHYS(end_pfn - start_pfn), (void *)&nid,
-				  register_mem_sect_under_node);
-}
+	struct memblock_region *r;
 
-#ifdef CONFIG_HUGETLBFS
-/*
- * Handle per node hstate attribute [un]registration on transistions
- * to/from memoryless state.
- */
-static void node_hugetlb_work(struct work_struct *work)
-{
-	struct node *node = container_of(work, struct node, node_work);
+	for_each_mem_region(r) {
+		const unsigned long start_block_id = phys_to_block_id(r->base);
+		const unsigned long end_block_id = phys_to_block_id(r->base + r->size - 1);
+		const int nid = memblock_get_region_node(r);
+		unsigned long block_id;
 
-	/*
-	 * We only get here when a node transitions to/from memoryless state.
-	 * We can detect which transition occurred by examining whether the
-	 * node has memory now.  hugetlb_register_node() already check this
-	 * so we try to register the attributes.  If that fails, then the
-	 * node has transitioned to memoryless, try to unregister the
-	 * attributes.
-	 */
-	if (!hugetlb_register_node(node))
-		hugetlb_unregister_node(node);
-}
+		if (!node_online(nid))
+			continue;
 
-static void init_node_hugetlb_work(int nid)
-{
-	INIT_WORK(&node_devices[nid]->node_work, node_hugetlb_work);
-}
+		for (block_id = start_block_id; block_id <= end_block_id; block_id++) {
+			struct memory_block *mem;
 
-static int node_memory_callback(struct notifier_block *self,
-				unsigned long action, void *arg)
-{
-	struct memory_notify *mnb = arg;
-	int nid = mnb->status_change_nid;
+			mem = find_memory_block_by_id(block_id);
+			if (!mem)
+				continue;
 
-	switch (action) {
-	case MEM_ONLINE:
-	case MEM_OFFLINE:
-		/*
-		 * offload per node hstate [un]registration to a work thread
-		 * when transitioning to/from memoryless state.
-		 */
-		if (nid != NUMA_NO_NODE)
-			schedule_work(&node_devices[nid]->node_work);
-		break;
+			memory_block_add_nid_early(mem, nid);
+			do_register_memory_block_under_node(nid, mem);
+			put_device(&mem->dev);
+		}
 
-	case MEM_GOING_ONLINE:
-	case MEM_GOING_OFFLINE:
-	case MEM_CANCEL_ONLINE:
-	case MEM_CANCEL_OFFLINE:
-	default:
-		break;
 	}
-
-	return NOTIFY_OK;
 }
-#endif	/* CONFIG_HUGETLBFS */
-#endif /* CONFIG_MEMORY_HOTPLUG_SPARSE */
 
-#if !defined(CONFIG_MEMORY_HOTPLUG_SPARSE) || \
-    !defined(CONFIG_HUGETLBFS)
-static inline int node_memory_callback(struct notifier_block *self,
-				unsigned long action, void *arg)
+void register_memory_blocks_under_node_hotplug(int nid, unsigned long start_pfn,
+					       unsigned long end_pfn)
 {
-	return NOTIFY_OK;
+	walk_memory_blocks(PFN_PHYS(start_pfn), PFN_PHYS(end_pfn - start_pfn),
+			   (void *)&nid, register_mem_block_under_node_hotplug);
+	return;
 }
+#endif /* CONFIG_MEMORY_HOTPLUG */
 
-static void init_node_hugetlb_work(int nid) { }
-
-#endif
-
-int __register_one_node(int nid)
+/**
+ * register_node - Initialize and register the node device.
+ * @nid: Node number to use when creating the device.
+ *
+ * Return: 0 on success, -errno otherwise
+ */
+int register_node(int nid)
 {
 	int error;
 	int cpu;
+	struct node *node;
 
-	node_devices[nid] = kzalloc(sizeof(struct node), GFP_KERNEL);
-	if (!node_devices[nid])
+	node = kzalloc(sizeof(struct node), GFP_KERNEL);
+	if (!node)
 		return -ENOMEM;
 
-	error = register_node(node_devices[nid], nid);
+	INIT_LIST_HEAD(&node->access_list);
+
+	node->dev.id = nid;
+	node->dev.bus = &node_subsys;
+	node->dev.release = node_device_release;
+	node->dev.groups = node_dev_groups;
+
+	error = device_register(&node->dev);
+	if (error) {
+		put_device(&node->dev);
+		return error;
+	}
+
+	node_devices[nid] = node;
+	hugetlb_register_node(node);
+	compaction_register_node(node);
+	reclaim_register_node(node);
 
 	/* link cpu under this node */
 	for_each_present_cpu(cpu) {
@@ -918,20 +903,30 @@ int __register_one_node(int nid)
 			register_cpu_under_node(cpu, nid);
 	}
 
-	INIT_LIST_HEAD(&node_devices[nid]->access_list);
-	/* initialize work queue for memory hot plug */
-	init_node_hugetlb_work(nid);
 	node_init_caches(nid);
 
 	return error;
 }
-
-void unregister_one_node(int nid)
+/**
+ * unregister_node - unregister a node device
+ * @nid: nid of the node going away
+ *
+ * Unregisters the node device at node id @nid. All the devices on the
+ * node must be unregistered before calling this function.
+ */
+void unregister_node(int nid)
 {
-	if (!node_devices[nid])
+	struct node *node = node_devices[nid];
+
+	if (!node)
 		return;
 
-	unregister_node(node_devices[nid]);
+	hugetlb_unregister_node(node);
+	compaction_unregister_node(node);
+	reclaim_unregister_node(node);
+	node_remove_accesses(node);
+	node_remove_caches(node);
+	device_unregister(&node->dev);
 	node_devices[nid] = NULL;
 }
 
@@ -939,17 +934,6 @@ void unregister_one_node(int nid)
  * node states attributes
  */
 
-static ssize_t print_nodes_state(enum node_states state, char *buf)
-{
-	int n;
-
-	n = scnprintf(buf, PAGE_SIZE - 1, "%*pbl",
-		      nodemask_pr_args(&node_states[state]));
-	buf[n++] = '\n';
-	buf[n] = '\0';
-	return n;
-}
-
 struct node_attr {
 	struct device_attribute attr;
 	enum node_states state;
@@ -959,7 +943,9 @@ static ssize_t show_node_state(struct device *dev,
 			       struct device_attribute *attr, char *buf)
 {
 	struct node_attr *na = container_of(attr, struct node_attr, attr);
-	return print_nodes_state(na->state, buf);
+
+	return sysfs_emit(buf, "%*pbl\n",
+			  nodemask_pr_args(&node_states[na->state]));
 }
 
 #define _NODE_ATTR(name, state) \
@@ -974,6 +960,8 @@ static struct node_attr node_state_attr[] = {
 #endif
 	[N_MEMORY] = _NODE_ATTR(has_memory, N_MEMORY),
 	[N_CPU] = _NODE_ATTR(has_cpu, N_CPU),
+	[N_GENERIC_INITIATOR] = _NODE_ATTR(has_generic_initiator,
+					   N_GENERIC_INITIATOR),
 };
 
 static struct attribute *node_state_attrs[] = {
@@ -985,10 +973,11 @@ static struct attribute *node_state_attrs[] = {
 #endif
 	&node_state_attr[N_MEMORY].attr.attr,
 	&node_state_attr[N_CPU].attr.attr,
+	&node_state_attr[N_GENERIC_INITIATOR].attr.attr,
 	NULL
 };
 
-static struct attribute_group memory_root_attr_group = {
+static const struct attribute_group memory_root_attr_group = {
 	.attrs = node_state_attrs,
 };
 
@@ -997,27 +986,26 @@ static const struct attribute_group *cpu_root_attr_groups[] = {
 	NULL,
 };
 
-#define NODE_CALLBACK_PRI	2	/* lower than SLAB */
-static int __init register_node_type(void)
+void __init node_dev_init(void)
 {
-	int ret;
+	int ret, i;
 
  	BUILD_BUG_ON(ARRAY_SIZE(node_state_attr) != NR_NODE_STATES);
  	BUILD_BUG_ON(ARRAY_SIZE(node_state_attrs)-1 != NR_NODE_STATES);
 
 	ret = subsys_system_register(&node_subsys, cpu_root_attr_groups);
-	if (!ret) {
-		static struct notifier_block node_memory_callback_nb = {
-			.notifier_call = node_memory_callback,
-			.priority = NODE_CALLBACK_PRI,
-		};
-		register_hotmemory_notifier(&node_memory_callback_nb);
-	}
+	if (ret)
+		panic("%s() failed to register subsystem: %d\n", __func__, ret);
 
 	/*
-	 * Note:  we're not going to unregister the node class if we fail
-	 * to register the node state class attribute files.
+	 * Create all node devices, which will properly link the node
+	 * to already created cpu devices.
 	 */
-	return ret;
+	for_each_online_node(i) {
+		ret =  register_node(i);
+		if (ret)
+			panic("%s() failed to add node: %d\n", __func__, ret);
+	}
+
+	register_memory_blocks_under_nodes();
 }
-postcore_initcall(register_node_type);
diff --git a/drivers/base/physical_location.c b/drivers/base/physical_location.c
new file mode 100644
index 000000000000..a5539e294d4d
--- /dev/null
+++ b/drivers/base/physical_location.c
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device physical location support
+ *
+ * Author: Won Chung <wonchung@google.com>
+ */
+
+#include <linux/acpi.h>
+#include <linux/sysfs.h>
+#include <linux/string_choices.h>
+
+#include "physical_location.h"
+
+bool dev_add_physical_location(struct device *dev)
+{
+	struct acpi_pld_info *pld;
+
+	if (!has_acpi_companion(dev))
+		return false;
+
+	if (!acpi_get_physical_device_location(ACPI_HANDLE(dev), &pld))
+		return false;
+
+	dev->physical_location =
+		kzalloc(sizeof(*dev->physical_location), GFP_KERNEL);
+	if (!dev->physical_location) {
+		ACPI_FREE(pld);
+		return false;
+	}
+
+	dev->physical_location->panel = pld->panel;
+	dev->physical_location->vertical_position = pld->vertical_position;
+	dev->physical_location->horizontal_position = pld->horizontal_position;
+	dev->physical_location->dock = pld->dock;
+	dev->physical_location->lid = pld->lid;
+
+	ACPI_FREE(pld);
+	return true;
+}
+
+static ssize_t panel_show(struct device *dev, struct device_attribute *attr,
+	char *buf)
+{
+	const char *panel;
+
+	switch (dev->physical_location->panel) {
+	case DEVICE_PANEL_TOP:
+		panel = "top";
+		break;
+	case DEVICE_PANEL_BOTTOM:
+		panel = "bottom";
+		break;
+	case DEVICE_PANEL_LEFT:
+		panel = "left";
+		break;
+	case DEVICE_PANEL_RIGHT:
+		panel = "right";
+		break;
+	case DEVICE_PANEL_FRONT:
+		panel = "front";
+		break;
+	case DEVICE_PANEL_BACK:
+		panel = "back";
+		break;
+	default:
+		panel = "unknown";
+	}
+	return sysfs_emit(buf, "%s\n", panel);
+}
+static DEVICE_ATTR_RO(panel);
+
+static ssize_t vertical_position_show(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	const char *vertical_position;
+
+	switch (dev->physical_location->vertical_position) {
+	case DEVICE_VERT_POS_UPPER:
+		vertical_position = "upper";
+		break;
+	case DEVICE_VERT_POS_CENTER:
+		vertical_position = "center";
+		break;
+	case DEVICE_VERT_POS_LOWER:
+		vertical_position = "lower";
+		break;
+	default:
+		vertical_position = "unknown";
+	}
+	return sysfs_emit(buf, "%s\n", vertical_position);
+}
+static DEVICE_ATTR_RO(vertical_position);
+
+static ssize_t horizontal_position_show(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	const char *horizontal_position;
+
+	switch (dev->physical_location->horizontal_position) {
+	case DEVICE_HORI_POS_LEFT:
+		horizontal_position = "left";
+		break;
+	case DEVICE_HORI_POS_CENTER:
+		horizontal_position = "center";
+		break;
+	case DEVICE_HORI_POS_RIGHT:
+		horizontal_position = "right";
+		break;
+	default:
+		horizontal_position = "unknown";
+	}
+	return sysfs_emit(buf, "%s\n", horizontal_position);
+}
+static DEVICE_ATTR_RO(horizontal_position);
+
+static ssize_t dock_show(struct device *dev, struct device_attribute *attr,
+	char *buf)
+{
+	return sysfs_emit(buf, "%s\n",
+		str_yes_no(dev->physical_location->dock));
+}
+static DEVICE_ATTR_RO(dock);
+
+static ssize_t lid_show(struct device *dev, struct device_attribute *attr,
+	char *buf)
+{
+	return sysfs_emit(buf, "%s\n",
+		str_yes_no(dev->physical_location->lid));
+}
+static DEVICE_ATTR_RO(lid);
+
+static struct attribute *dev_attr_physical_location[] = {
+	&dev_attr_panel.attr,
+	&dev_attr_vertical_position.attr,
+	&dev_attr_horizontal_position.attr,
+	&dev_attr_dock.attr,
+	&dev_attr_lid.attr,
+	NULL,
+};
+
+const struct attribute_group dev_attr_physical_location_group = {
+	.name = "physical_location",
+	.attrs = dev_attr_physical_location,
+};
+
diff --git a/drivers/base/physical_location.h b/drivers/base/physical_location.h
new file mode 100644
index 000000000000..3f3f61307998
--- /dev/null
+++ b/drivers/base/physical_location.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Device physical location support
+ *
+ * Author: Won Chung <wonchung@google.com>
+ */
+
+#include <linux/device.h>
+
+#ifdef CONFIG_ACPI
+bool dev_add_physical_location(struct device *dev);
+extern const struct attribute_group dev_attr_physical_location_group;
+#else
+static inline bool dev_add_physical_location(struct device *dev) { return false; };
+static const struct attribute_group dev_attr_physical_location_group = {};
+#endif
diff --git a/drivers/base/platform-msi.c b/drivers/base/platform-msi.c
index 8da314b81eab..70db08f3ac6f 100644
--- a/drivers/base/platform-msi.c
+++ b/drivers/base/platform-msi.c
@@ -4,409 +4,97 @@
  *
  * Copyright (C) 2015 ARM Limited, All Rights Reserved.
  * Author: Marc Zyngier <marc.zyngier@arm.com>
+ * Copyright (C) 2022 Linutronix GmbH
  */
 
 #include <linux/device.h>
-#include <linux/idr.h>
-#include <linux/irq.h>
 #include <linux/irqdomain.h>
 #include <linux/msi.h>
-#include <linux/slab.h>
-
-#define DEV_ID_SHIFT	21
-#define MAX_DEV_MSIS	(1 << (32 - DEV_ID_SHIFT))
 
 /*
- * Internal data structure containing a (made up, but unique) devid
- * and the callback to write the MSI message.
+ * This indirection can go when platform_device_msi_init_and_alloc_irqs()
+ * is switched to a proper irq_chip::irq_write_msi_msg() callback. Keep it
+ * simple for now.
  */
-struct platform_msi_priv_data {
-	struct device		*dev;
-	void 			*host_data;
-	msi_alloc_info_t	arg;
-	irq_write_msi_msg_t	write_msg;
-	int			devid;
-};
-
-/* The devid allocator */
-static DEFINE_IDA(platform_msi_devid_ida);
-
-#ifdef GENERIC_MSI_DOMAIN_OPS
-/*
- * Convert an msi_desc to a globaly unique identifier (per-device
- * devid + msi_desc position in the msi_list).
- */
-static irq_hw_number_t platform_msi_calc_hwirq(struct msi_desc *desc)
+static void platform_msi_write_msi_msg(struct irq_data *d, struct msi_msg *msg)
 {
-	u32 devid;
-
-	devid = desc->platform.msi_priv_data->devid;
+	irq_write_msi_msg_t cb = d->chip_data;
 
-	return (devid << (32 - DEV_ID_SHIFT)) | desc->platform.msi_index;
+	cb(irq_data_get_msi_desc(d), msg);
 }
 
 static void platform_msi_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc)
 {
 	arg->desc = desc;
-	arg->hwirq = platform_msi_calc_hwirq(desc);
-}
-
-static int platform_msi_init(struct irq_domain *domain,
-			     struct msi_domain_info *info,
-			     unsigned int virq, irq_hw_number_t hwirq,
-			     msi_alloc_info_t *arg)
-{
-	return irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
-					     info->chip, info->chip_data);
-}
-#else
-#define platform_msi_set_desc		NULL
-#define platform_msi_init		NULL
-#endif
-
-static void platform_msi_update_dom_ops(struct msi_domain_info *info)
-{
-	struct msi_domain_ops *ops = info->ops;
-
-	BUG_ON(!ops);
-
-	if (ops->msi_init == NULL)
-		ops->msi_init = platform_msi_init;
-	if (ops->set_desc == NULL)
-		ops->set_desc = platform_msi_set_desc;
-}
-
-static void platform_msi_write_msg(struct irq_data *data, struct msi_msg *msg)
-{
-	struct msi_desc *desc = irq_data_get_msi_desc(data);
-	struct platform_msi_priv_data *priv_data;
-
-	priv_data = desc->platform.msi_priv_data;
-
-	priv_data->write_msg(desc, msg);
-}
-
-static void platform_msi_update_chip_ops(struct msi_domain_info *info)
-{
-	struct irq_chip *chip = info->chip;
-
-	BUG_ON(!chip);
-	if (!chip->irq_mask)
-		chip->irq_mask = irq_chip_mask_parent;
-	if (!chip->irq_unmask)
-		chip->irq_unmask = irq_chip_unmask_parent;
-	if (!chip->irq_eoi)
-		chip->irq_eoi = irq_chip_eoi_parent;
-	if (!chip->irq_set_affinity)
-		chip->irq_set_affinity = msi_domain_set_affinity;
-	if (!chip->irq_write_msi_msg)
-		chip->irq_write_msi_msg = platform_msi_write_msg;
-	if (WARN_ON((info->flags & MSI_FLAG_LEVEL_CAPABLE) &&
-		    !(chip->flags & IRQCHIP_SUPPORTS_LEVEL_MSI)))
-		info->flags &= ~MSI_FLAG_LEVEL_CAPABLE;
+	arg->hwirq = desc->msi_index;
 }
 
-static void platform_msi_free_descs(struct device *dev, int base, int nvec)
-{
-	struct msi_desc *desc, *tmp;
+static const struct msi_domain_template platform_msi_template = {
+	.chip = {
+		.name			= "pMSI",
+		.irq_mask		= irq_chip_mask_parent,
+		.irq_unmask		= irq_chip_unmask_parent,
+		.irq_write_msi_msg	= platform_msi_write_msi_msg,
+		/* The rest is filled in by the platform MSI parent */
+	},
 
-	list_for_each_entry_safe(desc, tmp, dev_to_msi_list(dev), list) {
-		if (desc->platform.msi_index >= base &&
-		    desc->platform.msi_index < (base + nvec)) {
-			list_del(&desc->list);
-			free_msi_entry(desc);
-		}
-	}
-}
-
-static int platform_msi_alloc_descs_with_irq(struct device *dev, int virq,
-					     int nvec,
-					     struct platform_msi_priv_data *data)
+	.ops = {
+		.set_desc		= platform_msi_set_desc,
+	},
 
-{
-	struct msi_desc *desc;
-	int i, base = 0;
-
-	if (!list_empty(dev_to_msi_list(dev))) {
-		desc = list_last_entry(dev_to_msi_list(dev),
-				       struct msi_desc, list);
-		base = desc->platform.msi_index + 1;
-	}
-
-	for (i = 0; i < nvec; i++) {
-		desc = alloc_msi_entry(dev, 1, NULL);
-		if (!desc)
-			break;
-
-		desc->platform.msi_priv_data = data;
-		desc->platform.msi_index = base + i;
-		desc->irq = virq ? virq + i : 0;
-
-		list_add_tail(&desc->list, dev_to_msi_list(dev));
-	}
-
-	if (i != nvec) {
-		/* Clean up the mess */
-		platform_msi_free_descs(dev, base, nvec);
-
-		return -ENOMEM;
-	}
-
-	return 0;
-}
-
-static int platform_msi_alloc_descs(struct device *dev, int nvec,
-				    struct platform_msi_priv_data *data)
-
-{
-	return platform_msi_alloc_descs_with_irq(dev, 0, nvec, data);
-}
-
-/**
- * platform_msi_create_irq_domain - Create a platform MSI interrupt domain
- * @fwnode:		Optional fwnode of the interrupt controller
- * @info:	MSI domain info
- * @parent:	Parent irq domain
- *
- * Updates the domain and chip ops and creates a platform MSI
- * interrupt domain.
- *
- * Returns:
- * A domain pointer or NULL in case of failure.
- */
-struct irq_domain *platform_msi_create_irq_domain(struct fwnode_handle *fwnode,
-						  struct msi_domain_info *info,
-						  struct irq_domain *parent)
-{
-	struct irq_domain *domain;
-
-	if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS)
-		platform_msi_update_dom_ops(info);
-	if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS)
-		platform_msi_update_chip_ops(info);
-
-	domain = msi_create_irq_domain(fwnode, info, parent);
-	if (domain)
-		irq_domain_update_bus_token(domain, DOMAIN_BUS_PLATFORM_MSI);
-
-	return domain;
-}
-
-static struct platform_msi_priv_data *
-platform_msi_alloc_priv_data(struct device *dev, unsigned int nvec,
-			     irq_write_msi_msg_t write_msi_msg)
-{
-	struct platform_msi_priv_data *datap;
-	/*
-	 * Limit the number of interrupts to 2048 per device. Should we
-	 * need to bump this up, DEV_ID_SHIFT should be adjusted
-	 * accordingly (which would impact the max number of MSI
-	 * capable devices).
-	 */
-	if (!dev->msi_domain || !write_msi_msg || !nvec || nvec > MAX_DEV_MSIS)
-		return ERR_PTR(-EINVAL);
-
-	if (dev->msi_domain->bus_token != DOMAIN_BUS_PLATFORM_MSI) {
-		dev_err(dev, "Incompatible msi_domain, giving up\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	/* Already had a helping of MSI? Greed... */
-	if (!list_empty(dev_to_msi_list(dev)))
-		return ERR_PTR(-EBUSY);
-
-	datap = kzalloc(sizeof(*datap), GFP_KERNEL);
-	if (!datap)
-		return ERR_PTR(-ENOMEM);
-
-	datap->devid = ida_simple_get(&platform_msi_devid_ida,
-				      0, 1 << DEV_ID_SHIFT, GFP_KERNEL);
-	if (datap->devid < 0) {
-		int err = datap->devid;
-		kfree(datap);
-		return ERR_PTR(err);
-	}
-
-	datap->write_msg = write_msi_msg;
-	datap->dev = dev;
-
-	return datap;
-}
-
-static void platform_msi_free_priv_data(struct platform_msi_priv_data *data)
-{
-	ida_simple_remove(&platform_msi_devid_ida, data->devid);
-	kfree(data);
-}
+	.info = {
+		.bus_token		= DOMAIN_BUS_DEVICE_MSI,
+	},
+};
 
 /**
- * platform_msi_domain_alloc_irqs - Allocate MSI interrupts for @dev
+ * platform_device_msi_init_and_alloc_irqs - Initialize platform device MSI
+ *					     and allocate interrupts for @dev
  * @dev:		The device for which to allocate interrupts
  * @nvec:		The number of interrupts to allocate
  * @write_msi_msg:	Callback to write an interrupt message for @dev
  *
  * Returns:
  * Zero for success, or an error code in case of failure
- */
-int platform_msi_domain_alloc_irqs(struct device *dev, unsigned int nvec,
-				   irq_write_msi_msg_t write_msi_msg)
-{
-	struct platform_msi_priv_data *priv_data;
-	int err;
-
-	priv_data = platform_msi_alloc_priv_data(dev, nvec, write_msi_msg);
-	if (IS_ERR(priv_data))
-		return PTR_ERR(priv_data);
-
-	err = platform_msi_alloc_descs(dev, nvec, priv_data);
-	if (err)
-		goto out_free_priv_data;
-
-	err = msi_domain_alloc_irqs(dev->msi_domain, dev, nvec);
-	if (err)
-		goto out_free_desc;
-
-	return 0;
-
-out_free_desc:
-	platform_msi_free_descs(dev, 0, nvec);
-out_free_priv_data:
-	platform_msi_free_priv_data(priv_data);
-
-	return err;
-}
-EXPORT_SYMBOL_GPL(platform_msi_domain_alloc_irqs);
-
-/**
- * platform_msi_domain_free_irqs - Free MSI interrupts for @dev
- * @dev:	The device for which to free interrupts
- */
-void platform_msi_domain_free_irqs(struct device *dev)
-{
-	if (!list_empty(dev_to_msi_list(dev))) {
-		struct msi_desc *desc;
-
-		desc = first_msi_entry(dev);
-		platform_msi_free_priv_data(desc->platform.msi_priv_data);
-	}
-
-	msi_domain_free_irqs(dev->msi_domain, dev);
-	platform_msi_free_descs(dev, 0, MAX_DEV_MSIS);
-}
-EXPORT_SYMBOL_GPL(platform_msi_domain_free_irqs);
-
-/**
- * platform_msi_get_host_data - Query the private data associated with
- *                              a platform-msi domain
- * @domain:	The platform-msi domain
- *
- * Returns the private data provided when calling
- * platform_msi_create_device_domain.
- */
-void *platform_msi_get_host_data(struct irq_domain *domain)
-{
-	struct platform_msi_priv_data *data = domain->host_data;
-	return data->host_data;
-}
-
-/**
- * platform_msi_create_device_domain - Create a platform-msi domain
  *
- * @dev:		The device generating the MSIs
- * @nvec:		The number of MSIs that need to be allocated
- * @write_msi_msg:	Callback to write an interrupt message for @dev
- * @ops:		The hierarchy domain operations to use
- * @host_data:		Private data associated to this domain
+ * This creates a MSI domain on @dev which has @dev->msi.domain as
+ * parent. The parent domain sets up the new domain. The domain has
+ * a fixed size of @nvec. The domain is managed by devres and will
+ * be removed when the device is removed.
  *
- * Returns an irqdomain for @nvec interrupts
+ * Note: For migration purposes this falls back to the original platform_msi code
+ *	 up to the point where all platforms have been converted to the MSI
+ *	 parent model.
  */
-struct irq_domain *
-__platform_msi_create_device_domain(struct device *dev,
-				    unsigned int nvec,
-				    bool is_tree,
-				    irq_write_msi_msg_t write_msi_msg,
-				    const struct irq_domain_ops *ops,
-				    void *host_data)
+int platform_device_msi_init_and_alloc_irqs(struct device *dev, unsigned int nvec,
+					    irq_write_msi_msg_t write_msi_msg)
 {
-	struct platform_msi_priv_data *data;
-	struct irq_domain *domain;
-	int err;
-
-	data = platform_msi_alloc_priv_data(dev, nvec, write_msi_msg);
-	if (IS_ERR(data))
-		return NULL;
+	struct irq_domain *domain = dev->msi.domain;
 
-	data->host_data = host_data;
-	domain = irq_domain_create_hierarchy(dev->msi_domain, 0,
-					     is_tree ? 0 : nvec,
-					     dev->fwnode, ops, data);
-	if (!domain)
-		goto free_priv;
+	if (!domain || !write_msi_msg)
+		return -EINVAL;
 
-	err = msi_domain_prepare_irqs(domain->parent, dev, nvec, &data->arg);
-	if (err)
-		goto free_domain;
-
-	return domain;
-
-free_domain:
-	irq_domain_remove(domain);
-free_priv:
-	platform_msi_free_priv_data(data);
-	return NULL;
-}
-
-/**
- * platform_msi_domain_free - Free interrupts associated with a platform-msi
- *                            domain
- *
- * @domain:	The platform-msi domain
- * @virq:	The base irq from which to perform the free operation
- * @nvec:	How many interrupts to free from @virq
- */
-void platform_msi_domain_free(struct irq_domain *domain, unsigned int virq,
-			      unsigned int nvec)
-{
-	struct platform_msi_priv_data *data = domain->host_data;
-	struct msi_desc *desc, *tmp;
-	for_each_msi_entry_safe(desc, tmp, data->dev) {
-		if (WARN_ON(!desc->irq || desc->nvec_used != 1))
-			return;
-		if (!(desc->irq >= virq && desc->irq < (virq + nvec)))
-			continue;
+	/*
+	 * @write_msi_msg is stored in the resulting msi_domain_info::data.
+	 * The underlying domain creation mechanism will assign that
+	 * callback to the resulting irq chip.
+	 */
+	if (!msi_create_device_irq_domain(dev, MSI_DEFAULT_DOMAIN,
+					  &platform_msi_template,
+					  nvec, NULL, write_msi_msg))
+		return -ENODEV;
 
-		irq_domain_free_irqs_common(domain, desc->irq, 1);
-		list_del(&desc->list);
-		free_msi_entry(desc);
-	}
+	return msi_domain_alloc_irqs_range(dev, MSI_DEFAULT_DOMAIN, 0, nvec - 1);
 }
+EXPORT_SYMBOL_GPL(platform_device_msi_init_and_alloc_irqs);
 
 /**
- * platform_msi_domain_alloc - Allocate interrupts associated with
- *			       a platform-msi domain
- *
- * @domain:	The platform-msi domain
- * @virq:	The base irq from which to perform the allocate operation
- * @nvec:	How many interrupts to free from @virq
- *
- * Return 0 on success, or an error code on failure. Must be called
- * with irq_domain_mutex held (which can only be done as part of a
- * top-level interrupt allocation).
+ * platform_device_msi_free_irqs_all - Free all interrupts for @dev
+ * @dev:	The device for which to free interrupts
  */
-int platform_msi_domain_alloc(struct irq_domain *domain, unsigned int virq,
-			      unsigned int nr_irqs)
+void platform_device_msi_free_irqs_all(struct device *dev)
 {
-	struct platform_msi_priv_data *data = domain->host_data;
-	int err;
-
-	err = platform_msi_alloc_descs_with_irq(data->dev, virq, nr_irqs, data);
-	if (err)
-		return err;
-
-	err = msi_domain_populate_irqs(domain->parent, data->dev,
-				       virq, nr_irqs, &data->arg);
-	if (err)
-		platform_msi_domain_free(domain, virq, nr_irqs);
-
-	return err;
+	msi_domain_free_irqs_all(dev, MSI_DEFAULT_DOMAIN);
+	msi_remove_device_irq_domain(dev, MSI_DEFAULT_DOMAIN);
 }
+EXPORT_SYMBOL_GPL(platform_device_msi_free_irqs_all);
diff --git a/drivers/base/platform.c b/drivers/base/platform.c
index 5255550b7c34..b45d41b018ca 100644
--- a/drivers/base/platform.c
+++ b/drivers/base/platform.c
@@ -15,6 +15,8 @@
 #include <linux/of_irq.h>
 #include <linux/module.h>
 #include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
 #include <linux/dma-mapping.h>
 #include <linux/memblock.h>
 #include <linux/err.h>
@@ -28,6 +30,8 @@
 #include <linux/property.h>
 #include <linux/kmemleak.h>
 #include <linux/types.h>
+#include <linux/iommu.h>
+#include <linux/dma-map-ops.h>
 
 #include "base.h"
 #include "power/power.h"
@@ -45,6 +49,8 @@ EXPORT_SYMBOL_GPL(platform_bus);
  * @dev: platform device
  * @type: resource type
  * @num: resource index
+ *
+ * Return: a pointer to the resource or NULL on failure.
  */
 struct resource *platform_get_resource(struct platform_device *dev,
 				       unsigned int type, unsigned int num)
@@ -61,6 +67,21 @@ struct resource *platform_get_resource(struct platform_device *dev,
 }
 EXPORT_SYMBOL_GPL(platform_get_resource);
 
+struct resource *platform_get_mem_or_io(struct platform_device *dev,
+					unsigned int num)
+{
+	u32 i;
+
+	for (i = 0; i < dev->num_resources; i++) {
+		struct resource *r = &dev->resource[i];
+
+		if ((resource_type(r) & (IORESOURCE_MEM|IORESOURCE_IO)) && num-- == 0)
+			return r;
+	}
+	return NULL;
+}
+EXPORT_SYMBOL_GPL(platform_get_mem_or_io);
+
 #ifdef CONFIG_HAS_IOMEM
 /**
  * devm_platform_get_and_ioremap_resource - call devm_ioremap_resource() for a
@@ -70,6 +91,9 @@ EXPORT_SYMBOL_GPL(platform_get_resource);
  *        resource management
  * @index: resource index
  * @res: optional output parameter to store a pointer to the obtained resource.
+ *
+ * Return: a pointer to the remapped memory or an ERR_PTR() encoded error code
+ * on failure.
  */
 void __iomem *
 devm_platform_get_and_ioremap_resource(struct platform_device *pdev,
@@ -91,6 +115,9 @@ EXPORT_SYMBOL_GPL(devm_platform_get_and_ioremap_resource);
  * @pdev: platform device to use both for memory resource lookup as well as
  *        resource management
  * @index: resource index
+ *
+ * Return: a pointer to the remapped memory or an ERR_PTR() encoded error code
+ * on failure.
  */
 void __iomem *devm_platform_ioremap_resource(struct platform_device *pdev,
 					     unsigned int index)
@@ -100,23 +127,6 @@ void __iomem *devm_platform_ioremap_resource(struct platform_device *pdev,
 EXPORT_SYMBOL_GPL(devm_platform_ioremap_resource);
 
 /**
- * devm_platform_ioremap_resource_wc - write-combined variant of
- *                                     devm_platform_ioremap_resource()
- *
- * @pdev: platform device to use both for memory resource lookup as well as
- *        resource management
- * @index: resource index
- */
-void __iomem *devm_platform_ioremap_resource_wc(struct platform_device *pdev,
-						unsigned int index)
-{
-	struct resource *res;
-
-	res = platform_get_resource(pdev, IORESOURCE_MEM, index);
-	return devm_ioremap_resource_wc(&pdev->dev, res);
-}
-
-/**
  * devm_platform_ioremap_resource_byname - call devm_ioremap_resource for
  *					   a platform device, retrieve the
  *					   resource by name
@@ -124,6 +134,9 @@ void __iomem *devm_platform_ioremap_resource_wc(struct platform_device *pdev,
  * @pdev: platform device to use both for memory resource lookup as well as
  *	  resource management
  * @name: name of the resource
+ *
+ * Return: a pointer to the remapped memory or an ERR_PTR() encoded error code
+ * on failure.
  */
 void __iomem *
 devm_platform_ioremap_resource_byname(struct platform_device *pdev,
@@ -137,46 +150,61 @@ devm_platform_ioremap_resource_byname(struct platform_device *pdev,
 EXPORT_SYMBOL_GPL(devm_platform_ioremap_resource_byname);
 #endif /* CONFIG_HAS_IOMEM */
 
+static const struct cpumask *get_irq_affinity(struct platform_device *dev,
+					      unsigned int num)
+{
+	const struct cpumask *mask = NULL;
+#ifndef CONFIG_SPARC
+	struct fwnode_handle *fwnode = dev_fwnode(&dev->dev);
+
+	if (is_of_node(fwnode))
+		mask = of_irq_get_affinity(to_of_node(fwnode), num);
+	else if (is_acpi_device_node(fwnode))
+		mask = acpi_irq_get_affinity(ACPI_HANDLE_FWNODE(fwnode), num);
+#endif
+
+	return mask ?: cpu_possible_mask;
+}
+
 /**
- * platform_get_irq_optional - get an optional IRQ for a device
- * @dev: platform device
- * @num: IRQ number index
- *
- * Gets an IRQ for a platform device. Device drivers should check the return
- * value for errors so as to not pass a negative integer value to the
- * request_irq() APIs. This is the same as platform_get_irq(), except that it
- * does not print an error message if an IRQ can not be obtained.
+ * platform_get_irq_affinity - get an optional IRQ and its affinity for a device
+ * @dev:	platform device
+ * @num:	interrupt number index
+ * @affinity:	optional cpumask pointer to get the affinity of a per-cpu interrupt
  *
- * Example:
- *		int irq = platform_get_irq_optional(pdev, 0);
- *		if (irq < 0)
- *			return irq;
+ * Gets an interupt for a platform device. Device drivers should check the
+ * return value for errors so as to not pass a negative integer value to
+ * the request_irq() APIs. Optional affinity information is provided in the
+ * affinity pointer if available, and NULL otherwise.
  *
- * Return: IRQ number on success, negative error number on failure.
+ * Return: non-zero interrupt number on success, negative error number on failure.
  */
-int platform_get_irq_optional(struct platform_device *dev, unsigned int num)
+int platform_get_irq_affinity(struct platform_device *dev, unsigned int num,
+			      const struct cpumask **affinity)
 {
+	int ret;
 #ifdef CONFIG_SPARC
 	/* sparc does not have irqs represented as IORESOURCE_IRQ resources */
 	if (!dev || num >= dev->archdata.num_irqs)
-		return -ENXIO;
-	return dev->archdata.irqs[num];
+		goto out_not_found;
+	ret = dev->archdata.irqs[num];
+	goto out;
 #else
+	struct fwnode_handle *fwnode = dev_fwnode(&dev->dev);
 	struct resource *r;
-	int ret;
 
-	if (IS_ENABLED(CONFIG_OF_IRQ) && dev->dev.of_node) {
-		ret = of_irq_get(dev->dev.of_node, num);
+	if (is_of_node(fwnode)) {
+		ret = of_irq_get(to_of_node(fwnode), num);
 		if (ret > 0 || ret == -EPROBE_DEFER)
-			return ret;
+			goto out;
 	}
 
 	r = platform_get_resource(dev, IORESOURCE_IRQ, num);
-	if (has_acpi_companion(&dev->dev)) {
+	if (is_acpi_device_node(fwnode)) {
 		if (r && r->flags & IORESOURCE_DISABLED) {
-			ret = acpi_irq_get(ACPI_HANDLE(&dev->dev), num, r);
+			ret = acpi_irq_get(ACPI_HANDLE_FWNODE(fwnode), num, r);
 			if (ret)
-				return ret;
+				goto out;
 		}
 	}
 
@@ -191,12 +219,14 @@ int platform_get_irq_optional(struct platform_device *dev, unsigned int num)
 
 		irqd = irq_get_irq_data(r->start);
 		if (!irqd)
-			return -ENXIO;
+			goto out_not_found;
 		irqd_set_trigger_type(irqd, r->flags & IORESOURCE_BITS);
 	}
 
-	if (r)
-		return r->start;
+	if (r) {
+		ret = r->start;
+		goto out;
+	}
 
 	/*
 	 * For the index 0 interrupt, allow falling back to GpioInt
@@ -205,15 +235,49 @@ int platform_get_irq_optional(struct platform_device *dev, unsigned int num)
 	 * the device will only expose one IRQ, and this fallback
 	 * allows a common code path across either kind of resource.
 	 */
-	if (num == 0 && has_acpi_companion(&dev->dev)) {
-		ret = acpi_dev_gpio_irq_get(ACPI_COMPANION(&dev->dev), num);
+	if (num == 0 && is_acpi_device_node(fwnode)) {
+		ret = acpi_dev_gpio_irq_get(to_acpi_device_node(fwnode), num);
 		/* Our callers expect -ENXIO for missing IRQs. */
 		if (ret >= 0 || ret == -EPROBE_DEFER)
-			return ret;
+			goto out;
 	}
 
-	return -ENXIO;
 #endif
+out_not_found:
+	ret = -ENXIO;
+out:
+	if (WARN(!ret, "0 is an invalid IRQ number\n"))
+		return -EINVAL;
+
+	if (ret > 0 && affinity)
+		*affinity = get_irq_affinity(dev, num);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(platform_get_irq_affinity);
+
+/**
+ * platform_get_irq_optional - get an optional interrupt for a device
+ * @dev:	platform device
+ * @num:	interrupt number index
+ *
+ * Gets an interrupt for a platform device. Device drivers should check the
+ * return value for errors so as to not pass a negative integer value to
+ * the request_irq() APIs. This is the same as platform_get_irq(), except
+ * that it does not print an error message if an interrupt can not be
+ * obtained.
+ *
+ * For example::
+ *
+ *		int irq = platform_get_irq_optional(pdev, 0);
+ *		if (irq < 0)
+ *			return irq;
+ *
+ * Return: non-zero interrupt number on success, negative error number on failure.
+ */
+int platform_get_irq_optional(struct platform_device *dev, unsigned int num)
+{
+	return platform_get_irq_affinity(dev, num, NULL);
 }
 EXPORT_SYMBOL_GPL(platform_get_irq_optional);
 
@@ -226,20 +290,22 @@ EXPORT_SYMBOL_GPL(platform_get_irq_optional);
  * IRQ fails. Device drivers should check the return value for errors so as to
  * not pass a negative integer value to the request_irq() APIs.
  *
- * Example:
+ * For example::
+ *
  *		int irq = platform_get_irq(pdev, 0);
  *		if (irq < 0)
  *			return irq;
  *
- * Return: IRQ number on success, negative error number on failure.
+ * Return: non-zero IRQ number on success, negative error number on failure.
  */
 int platform_get_irq(struct platform_device *dev, unsigned int num)
 {
 	int ret;
 
 	ret = platform_get_irq_optional(dev, num);
-	if (ret < 0 && ret != -EPROBE_DEFER)
-		dev_err(&dev->dev, "IRQ index %u not found\n", num);
+	if (ret < 0)
+		return dev_err_probe(&dev->dev, ret,
+				     "IRQ index %u not found\n", num);
 
 	return ret;
 }
@@ -265,6 +331,127 @@ int platform_irq_count(struct platform_device *dev)
 }
 EXPORT_SYMBOL_GPL(platform_irq_count);
 
+struct irq_affinity_devres {
+	unsigned int count;
+	unsigned int irq[] __counted_by(count);
+};
+
+static void platform_disable_acpi_irq(struct platform_device *pdev, int index)
+{
+	struct resource *r;
+
+	r = platform_get_resource(pdev, IORESOURCE_IRQ, index);
+	if (r)
+		irqresource_disabled(r, 0);
+}
+
+static void devm_platform_get_irqs_affinity_release(struct device *dev,
+						    void *res)
+{
+	struct irq_affinity_devres *ptr = res;
+	int i;
+
+	for (i = 0; i < ptr->count; i++) {
+		irq_dispose_mapping(ptr->irq[i]);
+
+		if (is_acpi_device_node(dev_fwnode(dev)))
+			platform_disable_acpi_irq(to_platform_device(dev), i);
+	}
+}
+
+/**
+ * devm_platform_get_irqs_affinity - devm method to get a set of IRQs for a
+ *				device using an interrupt affinity descriptor
+ * @dev: platform device pointer
+ * @affd: affinity descriptor
+ * @minvec: minimum count of interrupt vectors
+ * @maxvec: maximum count of interrupt vectors
+ * @irqs: pointer holder for IRQ numbers
+ *
+ * Gets a set of IRQs for a platform device, and updates IRQ afffinty according
+ * to the passed affinity descriptor
+ *
+ * Return: Number of vectors on success, negative error number on failure.
+ */
+int devm_platform_get_irqs_affinity(struct platform_device *dev,
+				    struct irq_affinity *affd,
+				    unsigned int minvec,
+				    unsigned int maxvec,
+				    int **irqs)
+{
+	struct irq_affinity_devres *ptr;
+	struct irq_affinity_desc *desc;
+	size_t size;
+	int i, ret, nvec;
+
+	if (!affd)
+		return -EPERM;
+
+	if (maxvec < minvec)
+		return -ERANGE;
+
+	nvec = platform_irq_count(dev);
+	if (nvec < 0)
+		return nvec;
+
+	if (nvec < minvec)
+		return -ENOSPC;
+
+	nvec = irq_calc_affinity_vectors(minvec, nvec, affd);
+	if (nvec < minvec)
+		return -ENOSPC;
+
+	if (nvec > maxvec)
+		nvec = maxvec;
+
+	size = sizeof(*ptr) + sizeof(unsigned int) * nvec;
+	ptr = devres_alloc(devm_platform_get_irqs_affinity_release, size,
+			   GFP_KERNEL);
+	if (!ptr)
+		return -ENOMEM;
+
+	ptr->count = nvec;
+
+	for (i = 0; i < nvec; i++) {
+		int irq = platform_get_irq(dev, i);
+		if (irq < 0) {
+			ret = irq;
+			goto err_free_devres;
+		}
+		ptr->irq[i] = irq;
+	}
+
+	desc = irq_create_affinity_masks(nvec, affd);
+	if (!desc) {
+		ret = -ENOMEM;
+		goto err_free_devres;
+	}
+
+	for (i = 0; i < nvec; i++) {
+		ret = irq_update_affinity_desc(ptr->irq[i], &desc[i]);
+		if (ret) {
+			dev_err(&dev->dev, "failed to update irq%d affinity descriptor (%d)\n",
+				ptr->irq[i], ret);
+			goto err_free_desc;
+		}
+	}
+
+	devres_add(&dev->dev, ptr);
+
+	kfree(desc);
+
+	*irqs = ptr->irq;
+
+	return nvec;
+
+err_free_desc:
+	kfree(desc);
+err_free_devres:
+	devres_free(ptr);
+	return ret;
+}
+EXPORT_SYMBOL_GPL(devm_platform_get_irqs_affinity);
+
 /**
  * platform_get_resource_byname - get a resource for a device by name
  * @dev: platform device
@@ -296,15 +483,16 @@ static int __platform_get_irq_byname(struct platform_device *dev,
 	struct resource *r;
 	int ret;
 
-	if (IS_ENABLED(CONFIG_OF_IRQ) && dev->dev.of_node) {
-		ret = of_irq_get_byname(dev->dev.of_node, name);
-		if (ret > 0 || ret == -EPROBE_DEFER)
-			return ret;
-	}
+	ret = fwnode_irq_get_byname(dev_fwnode(&dev->dev), name);
+	if (ret > 0 || ret == -EPROBE_DEFER)
+		return ret;
 
 	r = platform_get_resource_byname(dev, IORESOURCE_IRQ, name);
-	if (r)
+	if (r) {
+		if (WARN(!r->start, "0 is an invalid IRQ number\n"))
+			return -EINVAL;
 		return r->start;
+	}
 
 	return -ENXIO;
 }
@@ -316,16 +504,16 @@ static int __platform_get_irq_byname(struct platform_device *dev,
  *
  * Get an IRQ like platform_get_irq(), but then by name rather then by index.
  *
- * Return: IRQ number on success, negative error number on failure.
+ * Return: non-zero IRQ number on success, negative error number on failure.
  */
 int platform_get_irq_byname(struct platform_device *dev, const char *name)
 {
 	int ret;
 
 	ret = __platform_get_irq_byname(dev, name);
-	if (ret < 0 && ret != -EPROBE_DEFER)
-		dev_err(&dev->dev, "IRQ %s not found\n", name);
-
+	if (ret < 0)
+		return dev_err_probe(&dev->dev, ret, "IRQ %s not found\n",
+				     name);
 	return ret;
 }
 EXPORT_SYMBOL_GPL(platform_get_irq_byname);
@@ -338,7 +526,7 @@ EXPORT_SYMBOL_GPL(platform_get_irq_byname);
  * Get an optional IRQ by name like platform_get_irq_byname(). Except that it
  * does not print an error message if an IRQ can not be obtained.
  *
- * Return: IRQ number on success, negative error number on failure.
+ * Return: non-zero IRQ number on success, negative error number on failure.
  */
 int platform_get_irq_byname_optional(struct platform_device *dev,
 				     const char *name)
@@ -351,6 +539,8 @@ EXPORT_SYMBOL_GPL(platform_get_irq_byname_optional);
  * platform_add_devices - add a numbers of platform devices
  * @devs: array of platform devices to add
  * @num: number of platform devices in array
+ *
+ * Return: 0 on success, negative error number on failure.
  */
 int platform_add_devices(struct platform_device **devs, int num)
 {
@@ -380,6 +570,8 @@ struct platform_object {
  */
 static void setup_pdev_dma_masks(struct platform_device *pdev)
 {
+	pdev->dev.dma_parms = &pdev->dma_parms;
+
 	if (!pdev->dev.coherent_dma_mask)
 		pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
 	if (!pdev->dev.dma_mask) {
@@ -407,7 +599,7 @@ static void platform_device_release(struct device *dev)
 	struct platform_object *pa = container_of(dev, struct platform_object,
 						  pdev.dev);
 
-	of_device_node_put(&pa->pdev.dev);
+	of_node_put(pa->pdev.dev.of_node);
 	kfree(pa->pdev.dev.platform_data);
 	kfree(pa->pdev.mfd_cell);
 	kfree(pa->pdev.resource);
@@ -457,7 +649,7 @@ int platform_device_add_resources(struct platform_device *pdev,
 	struct resource *r = NULL;
 
 	if (res) {
-		r = kmemdup(res, sizeof(struct resource) * num, GFP_KERNEL);
+		r = kmemdup_array(res, num, sizeof(*r), GFP_KERNEL);
 		if (!r)
 			return -ENOMEM;
 	}
@@ -497,22 +689,6 @@ int platform_device_add_data(struct platform_device *pdev, const void *data,
 EXPORT_SYMBOL_GPL(platform_device_add_data);
 
 /**
- * platform_device_add_properties - add built-in properties to a platform device
- * @pdev: platform device to add properties to
- * @properties: null terminated array of properties to add
- *
- * The function will take deep copy of @properties and attach the copy to the
- * platform device. The memory associated with properties will be freed when the
- * platform device is released.
- */
-int platform_device_add_properties(struct platform_device *pdev,
-				   const struct property_entry *properties)
-{
-	return device_add_properties(&pdev->dev, properties);
-}
-EXPORT_SYMBOL_GPL(platform_device_add_properties);
-
-/**
  * platform_device_add - add a platform device to device hierarchy
  * @pdev: platform device we're adding
  *
@@ -521,23 +697,21 @@ EXPORT_SYMBOL_GPL(platform_device_add_properties);
  */
 int platform_device_add(struct platform_device *pdev)
 {
+	struct device *dev = &pdev->dev;
 	u32 i;
 	int ret;
 
-	if (!pdev)
-		return -EINVAL;
-
-	if (!pdev->dev.parent)
-		pdev->dev.parent = &platform_bus;
+	if (!dev->parent)
+		dev->parent = &platform_bus;
 
-	pdev->dev.bus = &platform_bus_type;
+	dev->bus = &platform_bus_type;
 
 	switch (pdev->id) {
 	default:
-		dev_set_name(&pdev->dev, "%s.%d", pdev->name,  pdev->id);
+		dev_set_name(dev, "%s.%d", pdev->name,  pdev->id);
 		break;
 	case PLATFORM_DEVID_NONE:
-		dev_set_name(&pdev->dev, "%s", pdev->name);
+		dev_set_name(dev, "%s", pdev->name);
 		break;
 	case PLATFORM_DEVID_AUTO:
 		/*
@@ -545,12 +719,12 @@ int platform_device_add(struct platform_device *pdev)
 		 * that we remember it must be freed, and we append a suffix
 		 * to avoid namespace collision with explicit IDs.
 		 */
-		ret = ida_simple_get(&platform_devid_ida, 0, 0, GFP_KERNEL);
+		ret = ida_alloc(&platform_devid_ida, GFP_KERNEL);
 		if (ret < 0)
-			goto err_out;
+			return ret;
 		pdev->id = ret;
 		pdev->id_auto = true;
-		dev_set_name(&pdev->dev, "%s.%d.auto", pdev->name, pdev->id);
+		dev_set_name(dev, "%s.%d.auto", pdev->name, pdev->id);
 		break;
 	}
 
@@ -558,7 +732,7 @@ int platform_device_add(struct platform_device *pdev)
 		struct resource *p, *r = &pdev->resource[i];
 
 		if (r->name == NULL)
-			r->name = dev_name(&pdev->dev);
+			r->name = dev_name(dev);
 
 		p = r->parent;
 		if (!p) {
@@ -571,22 +745,24 @@ int platform_device_add(struct platform_device *pdev)
 		if (p) {
 			ret = insert_resource(p, r);
 			if (ret) {
-				dev_err(&pdev->dev, "failed to claim resource %d: %pR\n", i, r);
+				dev_err(dev, "failed to claim resource %d: %pR\n", i, r);
 				goto failed;
 			}
 		}
 	}
 
-	pr_debug("Registering platform device '%s'. Parent at %s\n",
-		 dev_name(&pdev->dev), dev_name(pdev->dev.parent));
+	pr_debug("Registering platform device '%s'. Parent at %s\n", dev_name(dev),
+		 dev_name(dev->parent));
 
-	ret = device_add(&pdev->dev);
-	if (ret == 0)
-		return ret;
+	ret = device_add(dev);
+	if (ret)
+		goto failed;
+
+	return 0;
 
  failed:
 	if (pdev->id_auto) {
-		ida_simple_remove(&platform_devid_ida, pdev->id);
+		ida_free(&platform_devid_ida, pdev->id);
 		pdev->id = PLATFORM_DEVID_AUTO;
 	}
 
@@ -596,7 +772,6 @@ int platform_device_add(struct platform_device *pdev)
 			release_resource(r);
 	}
 
- err_out:
 	return ret;
 }
 EXPORT_SYMBOL_GPL(platform_device_add);
@@ -617,7 +792,7 @@ void platform_device_del(struct platform_device *pdev)
 		device_del(&pdev->dev);
 
 		if (pdev->id_auto) {
-			ida_simple_remove(&platform_devid_ida, pdev->id);
+			ida_free(&platform_devid_ida, pdev->id);
 			pdev->id = PLATFORM_DEVID_AUTO;
 		}
 
@@ -633,6 +808,10 @@ EXPORT_SYMBOL_GPL(platform_device_del);
 /**
  * platform_device_register - add a platform-level device
  * @pdev: platform device we're adding
+ *
+ * NOTE: _Never_ directly free @pdev after calling this function, even if it
+ * returned an error! Always use platform_device_put() to give up the
+ * reference initialised in this function instead.
  */
 int platform_device_register(struct platform_device *pdev)
 {
@@ -668,7 +847,7 @@ EXPORT_SYMBOL_GPL(platform_device_unregister);
 struct platform_device *platform_device_register_full(
 		const struct platform_device_info *pdevinfo)
 {
-	int ret = -ENOMEM;
+	int ret;
 	struct platform_device *pdev;
 
 	pdev = platform_device_alloc(pdevinfo->name, pdevinfo->id);
@@ -697,8 +876,8 @@ struct platform_device *platform_device_register_full(
 		goto err;
 
 	if (pdevinfo->properties) {
-		ret = platform_device_add_properties(pdev,
-						     pdevinfo->properties);
+		ret = device_create_managed_software_node(&pdev->dev,
+							  pdevinfo->properties, NULL);
 		if (ret)
 			goto err;
 	}
@@ -715,62 +894,6 @@ err:
 }
 EXPORT_SYMBOL_GPL(platform_device_register_full);
 
-static int platform_drv_probe(struct device *_dev)
-{
-	struct platform_driver *drv = to_platform_driver(_dev->driver);
-	struct platform_device *dev = to_platform_device(_dev);
-	int ret;
-
-	ret = of_clk_set_defaults(_dev->of_node, false);
-	if (ret < 0)
-		return ret;
-
-	ret = dev_pm_domain_attach(_dev, true);
-	if (ret)
-		goto out;
-
-	if (drv->probe) {
-		ret = drv->probe(dev);
-		if (ret)
-			dev_pm_domain_detach(_dev, true);
-	}
-
-out:
-	if (drv->prevent_deferred_probe && ret == -EPROBE_DEFER) {
-		dev_warn(_dev, "probe deferral not supported\n");
-		ret = -ENXIO;
-	}
-
-	return ret;
-}
-
-static int platform_drv_probe_fail(struct device *_dev)
-{
-	return -ENXIO;
-}
-
-static int platform_drv_remove(struct device *_dev)
-{
-	struct platform_driver *drv = to_platform_driver(_dev->driver);
-	struct platform_device *dev = to_platform_device(_dev);
-	int ret = 0;
-
-	if (drv->remove)
-		ret = drv->remove(dev);
-	dev_pm_domain_detach(_dev, true);
-
-	return ret;
-}
-
-static void platform_drv_shutdown(struct device *_dev)
-{
-	struct platform_driver *drv = to_platform_driver(_dev->driver);
-	struct platform_device *dev = to_platform_device(_dev);
-
-	if (drv->shutdown)
-		drv->shutdown(dev);
-}
-
 /**
  * __platform_driver_register - register a driver for platform-level devices
  * @drv: platform driver structure
@@ -781,9 +904,6 @@ int __platform_driver_register(struct platform_driver *drv,
 {
 	drv->driver.owner = owner;
 	drv->driver.bus = &platform_bus_type;
-	drv->driver.probe = platform_drv_probe;
-	drv->driver.remove = platform_drv_remove;
-	drv->driver.shutdown = platform_drv_shutdown;
 
 	return driver_register(&drv->driver);
 }
@@ -799,6 +919,18 @@ void platform_driver_unregister(struct platform_driver *drv)
 }
 EXPORT_SYMBOL_GPL(platform_driver_unregister);
 
+static int platform_probe_fail(struct platform_device *pdev)
+{
+	return -ENXIO;
+}
+
+static int is_bound_to_driver(struct device *dev, void *driver)
+{
+	if (dev->driver == driver)
+		return 1;
+	return 0;
+}
+
 /**
  * __platform_driver_probe - register driver for non-hotpluggable device
  * @drv: platform driver structure
@@ -822,7 +954,7 @@ EXPORT_SYMBOL_GPL(platform_driver_unregister);
 int __init_or_module __platform_driver_probe(struct platform_driver *drv,
 		int (*probe)(struct platform_device *), struct module *module)
 {
-	int retval, code;
+	int retval;
 
 	if (drv->driver.probe_type == PROBE_PREFER_ASYNCHRONOUS) {
 		pr_err("%s: drivers registered with %s can not be probed asynchronously\n",
@@ -848,23 +980,21 @@ int __init_or_module __platform_driver_probe(struct platform_driver *drv,
 
 	/* temporary section violation during probe() */
 	drv->probe = probe;
-	retval = code = __platform_driver_register(drv, module);
+	retval = __platform_driver_register(drv, module);
+	if (retval)
+		return retval;
 
-	/*
-	 * Fixup that section violation, being paranoid about code scanning
-	 * the list of drivers in order to probe new devices.  Check to see
-	 * if the probe was successful, and make sure any forced probes of
-	 * new devices fail.
+	/* Force all new probes of this driver to fail */
+	drv->probe = platform_probe_fail;
+
+	/* Walk all platform devices and see if any actually bound to this driver.
+	 * If not, return an error as the device should have done so by now.
 	 */
-	spin_lock(&drv->driver.bus->p->klist_drivers.k_lock);
-	drv->probe = NULL;
-	if (code == 0 && list_empty(&drv->driver.p->klist_devices.k_list))
+	if (!bus_for_each_dev(&platform_bus_type, NULL, &drv->driver, is_bound_to_driver)) {
 		retval = -ENODEV;
-	drv->driver.probe = platform_drv_probe_fail;
-	spin_unlock(&drv->driver.bus->p->klist_drivers.k_lock);
-
-	if (code != retval)
 		platform_driver_unregister(drv);
+	}
+
 	return retval;
 }
 EXPORT_SYMBOL_GPL(__platform_driver_probe);
@@ -893,7 +1023,7 @@ struct platform_device * __init_or_module __platform_create_bundle(
 	struct platform_device *pdev;
 	int error;
 
-	pdev = platform_device_alloc(driver->driver.name, -1);
+	pdev = platform_device_alloc(driver->driver.name, PLATFORM_DEVID_NONE);
 	if (!pdev) {
 		error = -ENOMEM;
 		goto err_out;
@@ -973,7 +1103,7 @@ EXPORT_SYMBOL_GPL(__platform_register_drivers);
  * @drivers: an array of drivers to unregister
  * @count: the number of drivers to unregister
  *
- * Unegisters platform drivers specified by an array. This is typically used
+ * Unregisters platform drivers specified by an array. This is typically used
  * to complement an earlier call to platform_register_drivers(). Drivers are
  * unregistered in the reverse order in which they were registered.
  */
@@ -987,106 +1117,6 @@ void platform_unregister_drivers(struct platform_driver * const *drivers,
 }
 EXPORT_SYMBOL_GPL(platform_unregister_drivers);
 
-/* modalias support enables more hands-off userspace setup:
- * (a) environment variable lets new-style hotplug events work once system is
- *     fully running:  "modprobe $MODALIAS"
- * (b) sysfs attribute lets new-style coldplug recover from hotplug events
- *     mishandled before system is fully running:  "modprobe $(cat modalias)"
- */
-static ssize_t modalias_show(struct device *dev, struct device_attribute *a,
-			     char *buf)
-{
-	struct platform_device	*pdev = to_platform_device(dev);
-	int len;
-
-	len = of_device_modalias(dev, buf, PAGE_SIZE);
-	if (len != -ENODEV)
-		return len;
-
-	len = acpi_device_modalias(dev, buf, PAGE_SIZE -1);
-	if (len != -ENODEV)
-		return len;
-
-	len = snprintf(buf, PAGE_SIZE, "platform:%s\n", pdev->name);
-
-	return (len >= PAGE_SIZE) ? (PAGE_SIZE - 1) : len;
-}
-static DEVICE_ATTR_RO(modalias);
-
-static ssize_t driver_override_store(struct device *dev,
-				     struct device_attribute *attr,
-				     const char *buf, size_t count)
-{
-	struct platform_device *pdev = to_platform_device(dev);
-	char *driver_override, *old, *cp;
-
-	/* We need to keep extra room for a newline */
-	if (count >= (PAGE_SIZE - 1))
-		return -EINVAL;
-
-	driver_override = kstrndup(buf, count, GFP_KERNEL);
-	if (!driver_override)
-		return -ENOMEM;
-
-	cp = strchr(driver_override, '\n');
-	if (cp)
-		*cp = '\0';
-
-	device_lock(dev);
-	old = pdev->driver_override;
-	if (strlen(driver_override)) {
-		pdev->driver_override = driver_override;
-	} else {
-		kfree(driver_override);
-		pdev->driver_override = NULL;
-	}
-	device_unlock(dev);
-
-	kfree(old);
-
-	return count;
-}
-
-static ssize_t driver_override_show(struct device *dev,
-				    struct device_attribute *attr, char *buf)
-{
-	struct platform_device *pdev = to_platform_device(dev);
-	ssize_t len;
-
-	device_lock(dev);
-	len = sprintf(buf, "%s\n", pdev->driver_override);
-	device_unlock(dev);
-	return len;
-}
-static DEVICE_ATTR_RW(driver_override);
-
-
-static struct attribute *platform_dev_attrs[] = {
-	&dev_attr_modalias.attr,
-	&dev_attr_driver_override.attr,
-	NULL,
-};
-ATTRIBUTE_GROUPS(platform_dev);
-
-static int platform_uevent(struct device *dev, struct kobj_uevent_env *env)
-{
-	struct platform_device	*pdev = to_platform_device(dev);
-	int rc;
-
-	/* Some devices have extra OF data and an OF-style MODALIAS */
-	rc = of_device_uevent_modalias(dev, env);
-	if (rc != -ENODEV)
-		return rc;
-
-	rc = acpi_device_uevent_modalias(dev, env);
-	if (rc != -ENODEV)
-		return rc;
-
-	add_uevent_var(env, "MODALIAS=%s%s", PLATFORM_MODULE_PREFIX,
-			pdev->name);
-	return 0;
-}
-
 static const struct platform_device_id *platform_match_id(
 			const struct platform_device_id *id,
 			struct platform_device *pdev)
@@ -1101,44 +1131,6 @@ static const struct platform_device_id *platform_match_id(
 	return NULL;
 }
 
-/**
- * platform_match - bind platform device to platform driver.
- * @dev: device.
- * @drv: driver.
- *
- * Platform device IDs are assumed to be encoded like this:
- * "<name><instance>", where <name> is a short description of the type of
- * device, like "pci" or "floppy", and <instance> is the enumerated
- * instance of the device, like '0' or '42'.  Driver IDs are simply
- * "<name>".  So, extract the <name> from the platform_device structure,
- * and compare it against the name of the driver. Return whether they match
- * or not.
- */
-static int platform_match(struct device *dev, struct device_driver *drv)
-{
-	struct platform_device *pdev = to_platform_device(dev);
-	struct platform_driver *pdrv = to_platform_driver(drv);
-
-	/* When driver_override is set, only bind to the matching driver */
-	if (pdev->driver_override)
-		return !strcmp(pdev->driver_override, drv->name);
-
-	/* Attempt an OF style match first */
-	if (of_driver_match_device(dev, drv))
-		return 1;
-
-	/* Then try ACPI style match */
-	if (acpi_driver_match_device(dev, drv))
-		return 1;
-
-	/* Then try to match against the id table */
-	if (pdrv->id_table)
-		return platform_match_id(pdrv->id_table, pdev) != NULL;
-
-	/* fall-back to driver name match */
-	return (strcmp(pdev->name, drv->name) == 0);
-}
-
 #ifdef CONFIG_PM_SLEEP
 
 static int platform_legacy_suspend(struct device *dev, pm_message_t mesg)
@@ -1171,7 +1163,7 @@ static int platform_legacy_resume(struct device *dev)
 
 int platform_pm_suspend(struct device *dev)
 {
-	struct device_driver *drv = dev->driver;
+	const struct device_driver *drv = dev->driver;
 	int ret = 0;
 
 	if (!drv)
@@ -1189,7 +1181,7 @@ int platform_pm_suspend(struct device *dev)
 
 int platform_pm_resume(struct device *dev)
 {
-	struct device_driver *drv = dev->driver;
+	const struct device_driver *drv = dev->driver;
 	int ret = 0;
 
 	if (!drv)
@@ -1211,7 +1203,7 @@ int platform_pm_resume(struct device *dev)
 
 int platform_pm_freeze(struct device *dev)
 {
-	struct device_driver *drv = dev->driver;
+	const struct device_driver *drv = dev->driver;
 	int ret = 0;
 
 	if (!drv)
@@ -1229,7 +1221,7 @@ int platform_pm_freeze(struct device *dev)
 
 int platform_pm_thaw(struct device *dev)
 {
-	struct device_driver *drv = dev->driver;
+	const struct device_driver *drv = dev->driver;
 	int ret = 0;
 
 	if (!drv)
@@ -1247,7 +1239,7 @@ int platform_pm_thaw(struct device *dev)
 
 int platform_pm_poweroff(struct device *dev)
 {
-	struct device_driver *drv = dev->driver;
+	const struct device_driver *drv = dev->driver;
 	int ret = 0;
 
 	if (!drv)
@@ -1265,7 +1257,7 @@ int platform_pm_poweroff(struct device *dev)
 
 int platform_pm_restore(struct device *dev)
 {
-	struct device_driver *drv = dev->driver;
+	const struct device_driver *drv = dev->driver;
 	int ret = 0;
 
 	if (!drv)
@@ -1283,33 +1275,254 @@ int platform_pm_restore(struct device *dev)
 
 #endif /* CONFIG_HIBERNATE_CALLBACKS */
 
-int platform_dma_configure(struct device *dev)
+/* modalias support enables more hands-off userspace setup:
+ * (a) environment variable lets new-style hotplug events work once system is
+ *     fully running:  "modprobe $MODALIAS"
+ * (b) sysfs attribute lets new-style coldplug recover from hotplug events
+ *     mishandled before system is fully running:  "modprobe $(cat modalias)"
+ */
+static ssize_t modalias_show(struct device *dev,
+			     struct device_attribute *attr, char *buf)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	int len;
+
+	len = of_device_modalias(dev, buf, PAGE_SIZE);
+	if (len != -ENODEV)
+		return len;
+
+	len = acpi_device_modalias(dev, buf, PAGE_SIZE - 1);
+	if (len != -ENODEV)
+		return len;
+
+	return sysfs_emit(buf, "platform:%s\n", pdev->name);
+}
+static DEVICE_ATTR_RO(modalias);
+
+static ssize_t numa_node_show(struct device *dev,
+			      struct device_attribute *attr, char *buf)
+{
+	return sysfs_emit(buf, "%d\n", dev_to_node(dev));
+}
+static DEVICE_ATTR_RO(numa_node);
+
+static ssize_t driver_override_show(struct device *dev,
+				    struct device_attribute *attr, char *buf)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	ssize_t len;
+
+	device_lock(dev);
+	len = sysfs_emit(buf, "%s\n", pdev->driver_override);
+	device_unlock(dev);
+
+	return len;
+}
+
+static ssize_t driver_override_store(struct device *dev,
+				     struct device_attribute *attr,
+				     const char *buf, size_t count)
 {
+	struct platform_device *pdev = to_platform_device(dev);
+	int ret;
+
+	ret = driver_set_override(dev, &pdev->driver_override, buf, count);
+	if (ret)
+		return ret;
+
+	return count;
+}
+static DEVICE_ATTR_RW(driver_override);
+
+static struct attribute *platform_dev_attrs[] = {
+	&dev_attr_modalias.attr,
+	&dev_attr_numa_node.attr,
+	&dev_attr_driver_override.attr,
+	NULL,
+};
+
+static umode_t platform_dev_attrs_visible(struct kobject *kobj, struct attribute *a,
+		int n)
+{
+	struct device *dev = container_of(kobj, typeof(*dev), kobj);
+
+	if (a == &dev_attr_numa_node.attr &&
+			dev_to_node(dev) == NUMA_NO_NODE)
+		return 0;
+
+	return a->mode;
+}
+
+static const struct attribute_group platform_dev_group = {
+	.attrs = platform_dev_attrs,
+	.is_visible = platform_dev_attrs_visible,
+};
+__ATTRIBUTE_GROUPS(platform_dev);
+
+
+/**
+ * platform_match - bind platform device to platform driver.
+ * @dev: device.
+ * @drv: driver.
+ *
+ * Platform device IDs are assumed to be encoded like this:
+ * "<name><instance>", where <name> is a short description of the type of
+ * device, like "pci" or "floppy", and <instance> is the enumerated
+ * instance of the device, like '0' or '42'.  Driver IDs are simply
+ * "<name>".  So, extract the <name> from the platform_device structure,
+ * and compare it against the name of the driver. Return whether they match
+ * or not.
+ */
+static int platform_match(struct device *dev, const struct device_driver *drv)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct platform_driver *pdrv = to_platform_driver(drv);
+
+	/* When driver_override is set, only bind to the matching driver */
+	if (pdev->driver_override)
+		return !strcmp(pdev->driver_override, drv->name);
+
+	/* Attempt an OF style match first */
+	if (of_driver_match_device(dev, drv))
+		return 1;
+
+	/* Then try ACPI style match */
+	if (acpi_driver_match_device(dev, drv))
+		return 1;
+
+	/* Then try to match against the id table */
+	if (pdrv->id_table)
+		return platform_match_id(pdrv->id_table, pdev) != NULL;
+
+	/* fall-back to driver name match */
+	return (strcmp(pdev->name, drv->name) == 0);
+}
+
+static int platform_uevent(const struct device *dev, struct kobj_uevent_env *env)
+{
+	const struct platform_device *pdev = to_platform_device(dev);
+	int rc;
+
+	/* Some devices have extra OF data and an OF-style MODALIAS */
+	rc = of_device_uevent_modalias(dev, env);
+	if (rc != -ENODEV)
+		return rc;
+
+	rc = acpi_device_uevent_modalias(dev, env);
+	if (rc != -ENODEV)
+		return rc;
+
+	add_uevent_var(env, "MODALIAS=%s%s", PLATFORM_MODULE_PREFIX,
+			pdev->name);
+	return 0;
+}
+
+static int platform_probe(struct device *_dev)
+{
+	struct platform_driver *drv = to_platform_driver(_dev->driver);
+	struct platform_device *dev = to_platform_device(_dev);
+	int ret;
+
+	/*
+	 * A driver registered using platform_driver_probe() cannot be bound
+	 * again later because the probe function usually lives in __init code
+	 * and so is gone. For these drivers .probe is set to
+	 * platform_probe_fail in __platform_driver_probe(). Don't even prepare
+	 * clocks and PM domains for these to match the traditional behaviour.
+	 */
+	if (unlikely(drv->probe == platform_probe_fail))
+		return -ENXIO;
+
+	ret = of_clk_set_defaults(_dev->of_node, false);
+	if (ret < 0)
+		return ret;
+
+	ret = dev_pm_domain_attach(_dev, PD_FLAG_ATTACH_POWER_ON |
+					 PD_FLAG_DETACH_POWER_OFF);
+	if (ret)
+		goto out;
+
+	if (drv->probe)
+		ret = drv->probe(dev);
+
+out:
+	if (drv->prevent_deferred_probe && ret == -EPROBE_DEFER) {
+		dev_warn(_dev, "probe deferral not supported\n");
+		ret = -ENXIO;
+	}
+
+	return ret;
+}
+
+static void platform_remove(struct device *_dev)
+{
+	struct platform_driver *drv = to_platform_driver(_dev->driver);
+	struct platform_device *dev = to_platform_device(_dev);
+
+	if (drv->remove)
+		drv->remove(dev);
+}
+
+static void platform_shutdown(struct device *_dev)
+{
+	struct platform_device *dev = to_platform_device(_dev);
+	struct platform_driver *drv;
+
+	if (!_dev->driver)
+		return;
+
+	drv = to_platform_driver(_dev->driver);
+	if (drv->shutdown)
+		drv->shutdown(dev);
+}
+
+static int platform_dma_configure(struct device *dev)
+{
+	struct device_driver *drv = READ_ONCE(dev->driver);
+	struct fwnode_handle *fwnode = dev_fwnode(dev);
 	enum dev_dma_attr attr;
 	int ret = 0;
 
-	if (dev->of_node) {
-		ret = of_dma_configure(dev, dev->of_node, true);
-	} else if (has_acpi_companion(dev)) {
-		attr = acpi_get_dma_attr(to_acpi_device_node(dev->fwnode));
+	if (is_of_node(fwnode)) {
+		ret = of_dma_configure(dev, to_of_node(fwnode), true);
+	} else if (is_acpi_device_node(fwnode)) {
+		attr = acpi_get_dma_attr(to_acpi_device_node(fwnode));
 		ret = acpi_dma_configure(dev, attr);
 	}
+	/* @dev->driver may not be valid when we're called from the IOMMU layer */
+	if (ret || !drv || to_platform_driver(drv)->driver_managed_dma)
+		return ret;
+
+	ret = iommu_device_use_default_domain(dev);
+	if (ret)
+		arch_teardown_dma_ops(dev);
 
 	return ret;
 }
 
+static void platform_dma_cleanup(struct device *dev)
+{
+	struct platform_driver *drv = to_platform_driver(dev->driver);
+
+	if (!drv->driver_managed_dma)
+		iommu_device_unuse_default_domain(dev);
+}
+
 static const struct dev_pm_ops platform_dev_pm_ops = {
-	.runtime_suspend = pm_generic_runtime_suspend,
-	.runtime_resume = pm_generic_runtime_resume,
+	SET_RUNTIME_PM_OPS(pm_generic_runtime_suspend, pm_generic_runtime_resume, NULL)
 	USE_PLATFORM_PM_SLEEP_OPS
 };
 
-struct bus_type platform_bus_type = {
+const struct bus_type platform_bus_type = {
 	.name		= "platform",
 	.dev_groups	= platform_dev_groups,
 	.match		= platform_match,
 	.uevent		= platform_uevent,
+	.probe		= platform_probe,
+	.remove		= platform_remove,
+	.shutdown	= platform_shutdown,
 	.dma_configure	= platform_dma_configure,
+	.dma_cleanup	= platform_dma_cleanup,
 	.pm		= &platform_dev_pm_ops,
 };
 EXPORT_SYMBOL_GPL(platform_bus_type);
@@ -1349,6 +1562,6 @@ int __init platform_bus_init(void)
 	error =  bus_register(&platform_bus_type);
 	if (error)
 		device_unregister(&platform_bus);
-	of_platform_register_reconfig_notifier();
+
 	return error;
 }
diff --git a/drivers/base/power/Makefile b/drivers/base/power/Makefile
index 8fdd0073eeeb..2989e42d0161 100644
--- a/drivers/base/power/Makefile
+++ b/drivers/base/power/Makefile
@@ -2,8 +2,8 @@
 obj-$(CONFIG_PM)	+= sysfs.o generic_ops.o common.o qos.o runtime.o wakeirq.o
 obj-$(CONFIG_PM_SLEEP)	+= main.o wakeup.o wakeup_stats.o
 obj-$(CONFIG_PM_TRACE_RTC)	+= trace.o
-obj-$(CONFIG_PM_GENERIC_DOMAINS)	+=  domain.o domain_governor.o
 obj-$(CONFIG_HAVE_CLK)	+= clock_ops.o
 obj-$(CONFIG_PM_QOS_KUNIT_TEST) += qos-test.o
+obj-$(CONFIG_PM_RUNTIME_KUNIT_TEST) += runtime-test.o
 
 ccflags-$(CONFIG_DEBUG_DRIVER) := -DDEBUG
diff --git a/drivers/base/power/clock_ops.c b/drivers/base/power/clock_ops.c
index ced6863a16a5..b69bcb37c830 100644
--- a/drivers/base/power/clock_ops.c
+++ b/drivers/base/power/clock_ops.c
@@ -23,6 +23,7 @@
 enum pce_status {
 	PCE_STATUS_NONE = 0,
 	PCE_STATUS_ACQUIRED,
+	PCE_STATUS_PREPARED,
 	PCE_STATUS_ENABLED,
 	PCE_STATUS_ERROR,
 };
@@ -32,10 +33,114 @@ struct pm_clock_entry {
 	char *con_id;
 	struct clk *clk;
 	enum pce_status status;
+	bool enabled_when_prepared;
 };
 
 /**
- * pm_clk_enable - Enable a clock, reporting any errors
+ * pm_clk_list_lock - ensure exclusive access for modifying the PM clock
+ *		      entry list.
+ * @psd: pm_subsys_data instance corresponding to the PM clock entry list
+ *	 and clk_op_might_sleep count to be modified.
+ *
+ * Get exclusive access before modifying the PM clock entry list and the
+ * clock_op_might_sleep count to guard against concurrent modifications.
+ * This also protects against a concurrent clock_op_might_sleep and PM clock
+ * entry list usage in pm_clk_suspend()/pm_clk_resume() that may or may not
+ * happen in atomic context, hence both the mutex and the spinlock must be
+ * taken here.
+ */
+static void pm_clk_list_lock(struct pm_subsys_data *psd)
+	__acquires(&psd->lock)
+{
+	mutex_lock(&psd->clock_mutex);
+	spin_lock_irq(&psd->lock);
+}
+
+/**
+ * pm_clk_list_unlock - counterpart to pm_clk_list_lock().
+ * @psd: the same pm_subsys_data instance previously passed to
+ *	 pm_clk_list_lock().
+ */
+static void pm_clk_list_unlock(struct pm_subsys_data *psd)
+	__releases(&psd->lock)
+{
+	spin_unlock_irq(&psd->lock);
+	mutex_unlock(&psd->clock_mutex);
+}
+
+/**
+ * pm_clk_op_lock - ensure exclusive access for performing clock operations.
+ * @psd: pm_subsys_data instance corresponding to the PM clock entry list
+ *	 and clk_op_might_sleep count being used.
+ * @flags: stored irq flags.
+ * @fn: string for the caller function's name.
+ *
+ * This is used by pm_clk_suspend() and pm_clk_resume() to guard
+ * against concurrent modifications to the clock entry list and the
+ * clock_op_might_sleep count. If clock_op_might_sleep is != 0 then
+ * only the mutex can be locked and those functions can only be used in
+ * non atomic context. If clock_op_might_sleep == 0 then these functions
+ * may be used in any context and only the spinlock can be locked.
+ * Returns -EINVAL if called in atomic context when clock ops might sleep.
+ */
+static int pm_clk_op_lock(struct pm_subsys_data *psd, unsigned long *flags,
+			  const char *fn)
+	/* sparse annotations don't work here as exit state isn't static */
+{
+	bool atomic_context = in_atomic() || irqs_disabled();
+
+try_again:
+	spin_lock_irqsave(&psd->lock, *flags);
+	if (!psd->clock_op_might_sleep) {
+		/* the __release is there to work around sparse limitations */
+		__release(&psd->lock);
+		return 0;
+	}
+
+	/* bail out if in atomic context */
+	if (atomic_context) {
+		pr_err("%s: atomic context with clock_ops_might_sleep = %d",
+		       fn, psd->clock_op_might_sleep);
+		spin_unlock_irqrestore(&psd->lock, *flags);
+		might_sleep();
+		return -EPERM;
+	}
+
+	/* we must switch to the mutex */
+	spin_unlock_irqrestore(&psd->lock, *flags);
+	mutex_lock(&psd->clock_mutex);
+
+	/*
+	 * There was a possibility for psd->clock_op_might_sleep
+	 * to become 0 above. Keep the mutex only if not the case.
+	 */
+	if (likely(psd->clock_op_might_sleep))
+		return 0;
+
+	mutex_unlock(&psd->clock_mutex);
+	goto try_again;
+}
+
+/**
+ * pm_clk_op_unlock - counterpart to pm_clk_op_lock().
+ * @psd: the same pm_subsys_data instance previously passed to
+ *	 pm_clk_op_lock().
+ * @flags: irq flags provided by pm_clk_op_lock().
+ */
+static void pm_clk_op_unlock(struct pm_subsys_data *psd, unsigned long *flags)
+	/* sparse annotations don't work here as entry state isn't static */
+{
+	if (psd->clock_op_might_sleep) {
+		mutex_unlock(&psd->clock_mutex);
+	} else {
+		/* the __acquire is there to work around sparse limitations */
+		__acquire(&psd->lock);
+		spin_unlock_irqrestore(&psd->lock, *flags);
+	}
+}
+
+/**
+ * __pm_clk_enable - Enable a clock, reporting any errors
  * @dev: The device for the given clock
  * @ce: PM clock entry corresponding to the clock.
  */
@@ -43,14 +148,21 @@ static inline void __pm_clk_enable(struct device *dev, struct pm_clock_entry *ce
 {
 	int ret;
 
-	if (ce->status < PCE_STATUS_ERROR) {
+	switch (ce->status) {
+	case PCE_STATUS_ACQUIRED:
+		ret = clk_prepare_enable(ce->clk);
+		break;
+	case PCE_STATUS_PREPARED:
 		ret = clk_enable(ce->clk);
-		if (!ret)
-			ce->status = PCE_STATUS_ENABLED;
-		else
-			dev_err(dev, "%s: failed to enable clk %p, error %d\n",
-				__func__, ce->clk, ret);
+		break;
+	default:
+		return;
 	}
+	if (!ret)
+		ce->status = PCE_STATUS_ENABLED;
+	else
+		dev_err(dev, "%s: failed to enable clk %p, error %d\n",
+			__func__, ce->clk, ret);
 }
 
 /**
@@ -64,17 +176,20 @@ static void pm_clk_acquire(struct device *dev, struct pm_clock_entry *ce)
 		ce->clk = clk_get(dev, ce->con_id);
 	if (IS_ERR(ce->clk)) {
 		ce->status = PCE_STATUS_ERROR;
+		return;
+	} else if (clk_is_enabled_when_prepared(ce->clk)) {
+		/* we defer preparing the clock in that case */
+		ce->status = PCE_STATUS_ACQUIRED;
+		ce->enabled_when_prepared = true;
+	} else if (clk_prepare(ce->clk)) {
+		ce->status = PCE_STATUS_ERROR;
+		dev_err(dev, "clk_prepare() failed\n");
+		return;
 	} else {
-		if (clk_prepare(ce->clk)) {
-			ce->status = PCE_STATUS_ERROR;
-			dev_err(dev, "clk_prepare() failed\n");
-		} else {
-			ce->status = PCE_STATUS_ACQUIRED;
-			dev_dbg(dev,
-				"Clock %pC con_id %s managed by runtime PM.\n",
-				ce->clk, ce->con_id);
-		}
+		ce->status = PCE_STATUS_PREPARED;
 	}
+	dev_dbg(dev, "Clock %pC con_id %s managed by runtime PM.\n",
+		ce->clk, ce->con_id);
 }
 
 static int __pm_clk_add(struct device *dev, const char *con_id,
@@ -106,9 +221,11 @@ static int __pm_clk_add(struct device *dev, const char *con_id,
 
 	pm_clk_acquire(dev, ce);
 
-	spin_lock_irq(&psd->lock);
+	pm_clk_list_lock(psd);
 	list_add_tail(&ce->node, &psd->clock_list);
-	spin_unlock_irq(&psd->lock);
+	if (ce->enabled_when_prepared)
+		psd->clock_op_might_sleep++;
+	pm_clk_list_unlock(psd);
 	return 0;
 }
 
@@ -142,39 +259,6 @@ int pm_clk_add_clk(struct device *dev, struct clk *clk)
 }
 EXPORT_SYMBOL_GPL(pm_clk_add_clk);
 
-
-/**
- * of_pm_clk_add_clk - Start using a device clock for power management.
- * @dev: Device whose clock is going to be used for power management.
- * @name: Name of clock that is going to be used for power management.
- *
- * Add the clock described in the 'clocks' device-tree node that matches
- * with the 'name' provided, to the list of clocks used for the power
- * management of @dev. On success, returns 0. Returns a negative error
- * code if the clock is not found or cannot be added.
- */
-int of_pm_clk_add_clk(struct device *dev, const char *name)
-{
-	struct clk *clk;
-	int ret;
-
-	if (!dev || !dev->of_node || !name)
-		return -EINVAL;
-
-	clk = of_clk_get_by_name(dev->of_node, name);
-	if (IS_ERR(clk))
-		return PTR_ERR(clk);
-
-	ret = pm_clk_add_clk(dev, clk);
-	if (ret) {
-		clk_put(clk);
-		return ret;
-	}
-
-	return 0;
-}
-EXPORT_SYMBOL_GPL(of_pm_clk_add_clk);
-
 /**
  * of_pm_clk_add_clks - Start using device clock(s) for power management.
  * @dev: Device whose clock(s) is going to be used for power management.
@@ -239,14 +323,20 @@ static void __pm_clk_remove(struct pm_clock_entry *ce)
 	if (!ce)
 		return;
 
-	if (ce->status < PCE_STATUS_ERROR) {
-		if (ce->status == PCE_STATUS_ENABLED)
-			clk_disable(ce->clk);
-
-		if (ce->status >= PCE_STATUS_ACQUIRED) {
-			clk_unprepare(ce->clk);
+	switch (ce->status) {
+	case PCE_STATUS_ENABLED:
+		clk_disable(ce->clk);
+		fallthrough;
+	case PCE_STATUS_PREPARED:
+		clk_unprepare(ce->clk);
+		fallthrough;
+	case PCE_STATUS_ACQUIRED:
+	case PCE_STATUS_ERROR:
+		if (!IS_ERR(ce->clk))
 			clk_put(ce->clk);
-		}
+		break;
+	default:
+		break;
 	}
 
 	kfree(ce->con_id);
@@ -254,44 +344,6 @@ static void __pm_clk_remove(struct pm_clock_entry *ce)
 }
 
 /**
- * pm_clk_remove - Stop using a device clock for power management.
- * @dev: Device whose clock should not be used for PM any more.
- * @con_id: Connection ID of the clock.
- *
- * Remove the clock represented by @con_id from the list of clocks used for
- * the power management of @dev.
- */
-void pm_clk_remove(struct device *dev, const char *con_id)
-{
-	struct pm_subsys_data *psd = dev_to_psd(dev);
-	struct pm_clock_entry *ce;
-
-	if (!psd)
-		return;
-
-	spin_lock_irq(&psd->lock);
-
-	list_for_each_entry(ce, &psd->clock_list, node) {
-		if (!con_id && !ce->con_id)
-			goto remove;
-		else if (!con_id || !ce->con_id)
-			continue;
-		else if (!strcmp(con_id, ce->con_id))
-			goto remove;
-	}
-
-	spin_unlock_irq(&psd->lock);
-	return;
-
- remove:
-	list_del(&ce->node);
-	spin_unlock_irq(&psd->lock);
-
-	__pm_clk_remove(ce);
-}
-EXPORT_SYMBOL_GPL(pm_clk_remove);
-
-/**
  * pm_clk_remove_clk - Stop using a device clock for power management.
  * @dev: Device whose clock should not be used for PM any more.
  * @clk: Clock pointer
@@ -307,19 +359,21 @@ void pm_clk_remove_clk(struct device *dev, struct clk *clk)
 	if (!psd || !clk)
 		return;
 
-	spin_lock_irq(&psd->lock);
+	pm_clk_list_lock(psd);
 
 	list_for_each_entry(ce, &psd->clock_list, node) {
 		if (clk == ce->clk)
 			goto remove;
 	}
 
-	spin_unlock_irq(&psd->lock);
+	pm_clk_list_unlock(psd);
 	return;
 
  remove:
 	list_del(&ce->node);
-	spin_unlock_irq(&psd->lock);
+	if (ce->enabled_when_prepared)
+		psd->clock_op_might_sleep--;
+	pm_clk_list_unlock(psd);
 
 	__pm_clk_remove(ce);
 }
@@ -330,13 +384,16 @@ EXPORT_SYMBOL_GPL(pm_clk_remove_clk);
  * @dev: Device to initialize the list of PM clocks for.
  *
  * Initialize the lock and clock_list members of the device's pm_subsys_data
- * object.
+ * object, set the count of clocks that might sleep to 0.
  */
 void pm_clk_init(struct device *dev)
 {
 	struct pm_subsys_data *psd = dev_to_psd(dev);
-	if (psd)
+	if (psd) {
 		INIT_LIST_HEAD(&psd->clock_list);
+		mutex_init(&psd->clock_mutex);
+		psd->clock_op_might_sleep = 0;
+	}
 }
 EXPORT_SYMBOL_GPL(pm_clk_init);
 
@@ -372,12 +429,13 @@ void pm_clk_destroy(struct device *dev)
 
 	INIT_LIST_HEAD(&list);
 
-	spin_lock_irq(&psd->lock);
+	pm_clk_list_lock(psd);
 
 	list_for_each_entry_safe_reverse(ce, c, &psd->clock_list, node)
 		list_move(&ce->node, &list);
+	psd->clock_op_might_sleep = 0;
 
-	spin_unlock_irq(&psd->lock);
+	pm_clk_list_unlock(psd);
 
 	dev_pm_put_subsys_data(dev);
 
@@ -388,6 +446,23 @@ void pm_clk_destroy(struct device *dev)
 }
 EXPORT_SYMBOL_GPL(pm_clk_destroy);
 
+static void pm_clk_destroy_action(void *data)
+{
+	pm_clk_destroy(data);
+}
+
+int devm_pm_clk_create(struct device *dev)
+{
+	int ret;
+
+	ret = pm_clk_create(dev);
+	if (ret)
+		return ret;
+
+	return devm_add_action_or_reset(dev, pm_clk_destroy_action, dev);
+}
+EXPORT_SYMBOL_GPL(devm_pm_clk_create);
+
 /**
  * pm_clk_suspend - Disable clocks in a device's PM clock list.
  * @dev: Device to disable the clocks for.
@@ -397,23 +472,30 @@ int pm_clk_suspend(struct device *dev)
 	struct pm_subsys_data *psd = dev_to_psd(dev);
 	struct pm_clock_entry *ce;
 	unsigned long flags;
+	int ret;
 
 	dev_dbg(dev, "%s()\n", __func__);
 
 	if (!psd)
 		return 0;
 
-	spin_lock_irqsave(&psd->lock, flags);
+	ret = pm_clk_op_lock(psd, &flags, __func__);
+	if (ret)
+		return ret;
 
 	list_for_each_entry_reverse(ce, &psd->clock_list, node) {
-		if (ce->status < PCE_STATUS_ERROR) {
-			if (ce->status == PCE_STATUS_ENABLED)
+		if (ce->status == PCE_STATUS_ENABLED) {
+			if (ce->enabled_when_prepared) {
+				clk_disable_unprepare(ce->clk);
+				ce->status = PCE_STATUS_ACQUIRED;
+			} else {
 				clk_disable(ce->clk);
-			ce->status = PCE_STATUS_ACQUIRED;
+				ce->status = PCE_STATUS_PREPARED;
+			}
 		}
 	}
 
-	spin_unlock_irqrestore(&psd->lock, flags);
+	pm_clk_op_unlock(psd, &flags);
 
 	return 0;
 }
@@ -428,18 +510,21 @@ int pm_clk_resume(struct device *dev)
 	struct pm_subsys_data *psd = dev_to_psd(dev);
 	struct pm_clock_entry *ce;
 	unsigned long flags;
+	int ret;
 
 	dev_dbg(dev, "%s()\n", __func__);
 
 	if (!psd)
 		return 0;
 
-	spin_lock_irqsave(&psd->lock, flags);
+	ret = pm_clk_op_lock(psd, &flags, __func__);
+	if (ret)
+		return ret;
 
 	list_for_each_entry(ce, &psd->clock_list, node)
 		__pm_clk_enable(dev, ce);
 
-	spin_unlock_irqrestore(&psd->lock, flags);
+	pm_clk_op_unlock(psd, &flags);
 
 	return 0;
 }
@@ -635,7 +720,7 @@ static int pm_clk_notify(struct notifier_block *nb,
  * the remaining members of @clknb should be populated prior to calling this
  * routine.
  */
-void pm_clk_add_notifier(struct bus_type *bus,
+void pm_clk_add_notifier(const struct bus_type *bus,
 				 struct pm_clk_notifier_block *clknb)
 {
 	if (!bus || !clknb)
diff --git a/drivers/base/power/common.c b/drivers/base/power/common.c
index bbddb267c2e6..6ecf9ce4a4e6 100644
--- a/drivers/base/power/common.c
+++ b/drivers/base/power/common.c
@@ -11,6 +11,7 @@
 #include <linux/pm_clock.h>
 #include <linux/acpi.h>
 #include <linux/pm_domain.h>
+#include <linux/pm_opp.h>
 
 #include "power.h"
 
@@ -82,7 +83,7 @@ EXPORT_SYMBOL_GPL(dev_pm_put_subsys_data);
 /**
  * dev_pm_domain_attach - Attach a device to its PM domain.
  * @dev: Device to attach.
- * @power_on: Used to indicate whether we should power on the device.
+ * @flags: indicate whether we should power on/off the device on attach/detach
  *
  * The @dev may only be attached to a single PM domain. By iterating through
  * the available alternatives we try to find a valid PM domain for the device.
@@ -99,17 +100,20 @@ EXPORT_SYMBOL_GPL(dev_pm_put_subsys_data);
  * Returns 0 on successfully attached PM domain, or when it is found that the
  * device doesn't need a PM domain, else a negative error code.
  */
-int dev_pm_domain_attach(struct device *dev, bool power_on)
+int dev_pm_domain_attach(struct device *dev, u32 flags)
 {
 	int ret;
 
 	if (dev->pm_domain)
 		return 0;
 
-	ret = acpi_dev_pm_attach(dev, power_on);
+	ret = acpi_dev_pm_attach(dev, !!(flags & PD_FLAG_ATTACH_POWER_ON));
 	if (!ret)
 		ret = genpd_dev_pm_attach(dev);
 
+	if (dev->pm_domain)
+		dev->power.detach_power_off = !!(flags & PD_FLAG_DETACH_POWER_OFF);
+
 	return ret < 0 ? ret : 0;
 }
 EXPORT_SYMBOL_GPL(dev_pm_domain_attach);
@@ -168,14 +172,187 @@ struct device *dev_pm_domain_attach_by_name(struct device *dev,
 EXPORT_SYMBOL_GPL(dev_pm_domain_attach_by_name);
 
 /**
+ * dev_pm_domain_attach_list - Associate a device with its PM domains.
+ * @dev: The device used to lookup the PM domains for.
+ * @data: The data used for attaching to the PM domains.
+ * @list: An out-parameter with an allocated list of attached PM domains.
+ *
+ * This function helps to attach a device to its multiple PM domains. The
+ * caller, which is typically a driver's probe function, may provide a list of
+ * names for the PM domains that we should try to attach the device to, but it
+ * may also provide an empty list, in case the attach should be done for all of
+ * the available PM domains.
+ *
+ * Callers must ensure proper synchronization of this function with power
+ * management callbacks.
+ *
+ * Returns the number of attached PM domains or a negative error code in case of
+ * a failure. Note that, to detach the list of PM domains, the driver shall call
+ * dev_pm_domain_detach_list(), typically during the remove phase.
+ */
+int dev_pm_domain_attach_list(struct device *dev,
+			      const struct dev_pm_domain_attach_data *data,
+			      struct dev_pm_domain_list **list)
+{
+	struct device_node *np = dev->of_node;
+	struct dev_pm_domain_list *pds;
+	struct device *pd_dev = NULL;
+	int ret, i, num_pds = 0;
+	bool by_id = true;
+	size_t size;
+	u32 pd_flags = data ? data->pd_flags : 0;
+	u32 link_flags = pd_flags & PD_FLAG_NO_DEV_LINK ? 0 :
+			DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME;
+
+	if (dev->pm_domain)
+		return -EEXIST;
+
+	/* For now this is limited to OF based platforms. */
+	if (!np)
+		return 0;
+
+	if (data && data->pd_names) {
+		num_pds = data->num_pd_names;
+		by_id = false;
+	} else {
+		num_pds = of_count_phandle_with_args(np, "power-domains",
+						     "#power-domain-cells");
+	}
+
+	if (num_pds <= 0)
+		return 0;
+
+	pds = kzalloc(sizeof(*pds), GFP_KERNEL);
+	if (!pds)
+		return -ENOMEM;
+
+	size = sizeof(*pds->pd_devs) + sizeof(*pds->pd_links) +
+	       sizeof(*pds->opp_tokens);
+	pds->pd_devs = kcalloc(num_pds, size, GFP_KERNEL);
+	if (!pds->pd_devs) {
+		ret = -ENOMEM;
+		goto free_pds;
+	}
+	pds->pd_links = (void *)(pds->pd_devs + num_pds);
+	pds->opp_tokens = (void *)(pds->pd_links + num_pds);
+
+	if (link_flags && pd_flags & PD_FLAG_DEV_LINK_ON)
+		link_flags |= DL_FLAG_RPM_ACTIVE;
+
+	for (i = 0; i < num_pds; i++) {
+		if (by_id)
+			pd_dev = dev_pm_domain_attach_by_id(dev, i);
+		else
+			pd_dev = dev_pm_domain_attach_by_name(dev,
+							data->pd_names[i]);
+		if (IS_ERR_OR_NULL(pd_dev)) {
+			ret = pd_dev ? PTR_ERR(pd_dev) : -ENODEV;
+			goto err_attach;
+		}
+
+		if (pd_flags & PD_FLAG_REQUIRED_OPP) {
+			struct dev_pm_opp_config config = {
+				.required_dev = pd_dev,
+				.required_dev_index = i,
+			};
+
+			ret = dev_pm_opp_set_config(dev, &config);
+			if (ret < 0)
+				goto err_link;
+
+			pds->opp_tokens[i] = ret;
+		}
+
+		if (link_flags) {
+			struct device_link *link;
+
+			link = device_link_add(dev, pd_dev, link_flags);
+			if (!link) {
+				ret = -ENODEV;
+				goto err_link;
+			}
+
+			pds->pd_links[i] = link;
+		}
+
+		pds->pd_devs[i] = pd_dev;
+	}
+
+	pds->num_pds = num_pds;
+	*list = pds;
+	return num_pds;
+
+err_link:
+	dev_pm_opp_clear_config(pds->opp_tokens[i]);
+	dev_pm_domain_detach(pd_dev, true);
+err_attach:
+	while (--i >= 0) {
+		dev_pm_opp_clear_config(pds->opp_tokens[i]);
+		if (pds->pd_links[i])
+			device_link_del(pds->pd_links[i]);
+		dev_pm_domain_detach(pds->pd_devs[i], true);
+	}
+	kfree(pds->pd_devs);
+free_pds:
+	kfree(pds);
+	return ret;
+}
+EXPORT_SYMBOL_GPL(dev_pm_domain_attach_list);
+
+/**
+ * devm_pm_domain_detach_list - devres-enabled version of dev_pm_domain_detach_list.
+ * @_list: The list of PM domains to detach.
+ *
+ * This function reverse the actions from devm_pm_domain_attach_list().
+ * it will be invoked during the remove phase from drivers implicitly if driver
+ * uses devm_pm_domain_attach_list() to attach the PM domains.
+ */
+static void devm_pm_domain_detach_list(void *_list)
+{
+	struct dev_pm_domain_list *list = _list;
+
+	dev_pm_domain_detach_list(list);
+}
+
+/**
+ * devm_pm_domain_attach_list - devres-enabled version of dev_pm_domain_attach_list
+ * @dev: The device used to lookup the PM domains for.
+ * @data: The data used for attaching to the PM domains.
+ * @list: An out-parameter with an allocated list of attached PM domains.
+ *
+ * NOTE: this will also handle calling devm_pm_domain_detach_list() for
+ * you during remove phase.
+ *
+ * Returns the number of attached PM domains or a negative error code in case of
+ * a failure.
+ */
+int devm_pm_domain_attach_list(struct device *dev,
+			       const struct dev_pm_domain_attach_data *data,
+			       struct dev_pm_domain_list **list)
+{
+	int ret, num_pds;
+
+	num_pds = dev_pm_domain_attach_list(dev, data, list);
+	if (num_pds <= 0)
+		return num_pds;
+
+	ret = devm_add_action_or_reset(dev, devm_pm_domain_detach_list, *list);
+	if (ret)
+		return ret;
+
+	return num_pds;
+}
+EXPORT_SYMBOL_GPL(devm_pm_domain_attach_list);
+
+/**
  * dev_pm_domain_detach - Detach a device from its PM domain.
  * @dev: Device to detach.
  * @power_off: Used to indicate whether we should power off the device.
  *
- * This functions will reverse the actions from dev_pm_domain_attach() and
- * dev_pm_domain_attach_by_id(), thus it detaches @dev from its PM domain.
- * Typically it should be invoked during the remove phase, either from
- * subsystem level code or from drivers.
+ * This functions will reverse the actions from dev_pm_domain_attach(),
+ * dev_pm_domain_attach_by_id() and dev_pm_domain_attach_by_name(), thus it
+ * detaches @dev from its PM domain.  Typically it should be invoked during the
+ * remove phase, either from subsystem level code or from drivers.
  *
  * Callers must ensure proper synchronization of this function with power
  * management callbacks.
@@ -188,6 +365,35 @@ void dev_pm_domain_detach(struct device *dev, bool power_off)
 EXPORT_SYMBOL_GPL(dev_pm_domain_detach);
 
 /**
+ * dev_pm_domain_detach_list - Detach a list of PM domains.
+ * @list: The list of PM domains to detach.
+ *
+ * This function reverse the actions from dev_pm_domain_attach_list().
+ * Typically it should be invoked during the remove phase from drivers.
+ *
+ * Callers must ensure proper synchronization of this function with power
+ * management callbacks.
+ */
+void dev_pm_domain_detach_list(struct dev_pm_domain_list *list)
+{
+	int i;
+
+	if (!list)
+		return;
+
+	for (i = 0; i < list->num_pds; i++) {
+		dev_pm_opp_clear_config(list->opp_tokens[i]);
+		if (list->pd_links[i])
+			device_link_del(list->pd_links[i]);
+		dev_pm_domain_detach(list->pd_devs[i], true);
+	}
+
+	kfree(list->pd_devs);
+	kfree(list);
+}
+EXPORT_SYMBOL_GPL(dev_pm_domain_detach_list);
+
+/**
  * dev_pm_domain_start - Start the device through its PM domain.
  * @dev: Device to start.
  *
@@ -228,3 +434,24 @@ void dev_pm_domain_set(struct device *dev, struct dev_pm_domain *pd)
 	device_pm_check_callbacks(dev);
 }
 EXPORT_SYMBOL_GPL(dev_pm_domain_set);
+
+/**
+ * dev_pm_domain_set_performance_state - Request a new performance state.
+ * @dev: The device to make the request for.
+ * @state: Target performance state for the device.
+ *
+ * This function should be called when a new performance state needs to be
+ * requested for a device that is attached to a PM domain. Note that, the
+ * support for performance scaling for PM domains is optional.
+ *
+ * Returns 0 on success and when performance scaling isn't supported, negative
+ * error code on failure.
+ */
+int dev_pm_domain_set_performance_state(struct device *dev, unsigned int state)
+{
+	if (dev->pm_domain && dev->pm_domain->set_performance_state)
+		return dev->pm_domain->set_performance_state(dev, state);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(dev_pm_domain_set_performance_state);
diff --git a/drivers/base/power/domain.c b/drivers/base/power/domain.c
deleted file mode 100644
index 0a01df608849..000000000000
--- a/drivers/base/power/domain.c
+++ /dev/null
@@ -1,3089 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * drivers/base/power/domain.c - Common code related to device power domains.
- *
- * Copyright (C) 2011 Rafael J. Wysocki <rjw@sisk.pl>, Renesas Electronics Corp.
- */
-#define pr_fmt(fmt) "PM: " fmt
-
-#include <linux/delay.h>
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/platform_device.h>
-#include <linux/pm_opp.h>
-#include <linux/pm_runtime.h>
-#include <linux/pm_domain.h>
-#include <linux/pm_qos.h>
-#include <linux/pm_clock.h>
-#include <linux/slab.h>
-#include <linux/err.h>
-#include <linux/sched.h>
-#include <linux/suspend.h>
-#include <linux/export.h>
-#include <linux/cpu.h>
-
-#include "power.h"
-
-#define GENPD_RETRY_MAX_MS	250		/* Approximate */
-
-#define GENPD_DEV_CALLBACK(genpd, type, callback, dev)		\
-({								\
-	type (*__routine)(struct device *__d); 			\
-	type __ret = (type)0;					\
-								\
-	__routine = genpd->dev_ops.callback; 			\
-	if (__routine) {					\
-		__ret = __routine(dev); 			\
-	}							\
-	__ret;							\
-})
-
-static LIST_HEAD(gpd_list);
-static DEFINE_MUTEX(gpd_list_lock);
-
-struct genpd_lock_ops {
-	void (*lock)(struct generic_pm_domain *genpd);
-	void (*lock_nested)(struct generic_pm_domain *genpd, int depth);
-	int (*lock_interruptible)(struct generic_pm_domain *genpd);
-	void (*unlock)(struct generic_pm_domain *genpd);
-};
-
-static void genpd_lock_mtx(struct generic_pm_domain *genpd)
-{
-	mutex_lock(&genpd->mlock);
-}
-
-static void genpd_lock_nested_mtx(struct generic_pm_domain *genpd,
-					int depth)
-{
-	mutex_lock_nested(&genpd->mlock, depth);
-}
-
-static int genpd_lock_interruptible_mtx(struct generic_pm_domain *genpd)
-{
-	return mutex_lock_interruptible(&genpd->mlock);
-}
-
-static void genpd_unlock_mtx(struct generic_pm_domain *genpd)
-{
-	return mutex_unlock(&genpd->mlock);
-}
-
-static const struct genpd_lock_ops genpd_mtx_ops = {
-	.lock = genpd_lock_mtx,
-	.lock_nested = genpd_lock_nested_mtx,
-	.lock_interruptible = genpd_lock_interruptible_mtx,
-	.unlock = genpd_unlock_mtx,
-};
-
-static void genpd_lock_spin(struct generic_pm_domain *genpd)
-	__acquires(&genpd->slock)
-{
-	unsigned long flags;
-
-	spin_lock_irqsave(&genpd->slock, flags);
-	genpd->lock_flags = flags;
-}
-
-static void genpd_lock_nested_spin(struct generic_pm_domain *genpd,
-					int depth)
-	__acquires(&genpd->slock)
-{
-	unsigned long flags;
-
-	spin_lock_irqsave_nested(&genpd->slock, flags, depth);
-	genpd->lock_flags = flags;
-}
-
-static int genpd_lock_interruptible_spin(struct generic_pm_domain *genpd)
-	__acquires(&genpd->slock)
-{
-	unsigned long flags;
-
-	spin_lock_irqsave(&genpd->slock, flags);
-	genpd->lock_flags = flags;
-	return 0;
-}
-
-static void genpd_unlock_spin(struct generic_pm_domain *genpd)
-	__releases(&genpd->slock)
-{
-	spin_unlock_irqrestore(&genpd->slock, genpd->lock_flags);
-}
-
-static const struct genpd_lock_ops genpd_spin_ops = {
-	.lock = genpd_lock_spin,
-	.lock_nested = genpd_lock_nested_spin,
-	.lock_interruptible = genpd_lock_interruptible_spin,
-	.unlock = genpd_unlock_spin,
-};
-
-#define genpd_lock(p)			p->lock_ops->lock(p)
-#define genpd_lock_nested(p, d)		p->lock_ops->lock_nested(p, d)
-#define genpd_lock_interruptible(p)	p->lock_ops->lock_interruptible(p)
-#define genpd_unlock(p)			p->lock_ops->unlock(p)
-
-#define genpd_status_on(genpd)		(genpd->status == GPD_STATE_ACTIVE)
-#define genpd_is_irq_safe(genpd)	(genpd->flags & GENPD_FLAG_IRQ_SAFE)
-#define genpd_is_always_on(genpd)	(genpd->flags & GENPD_FLAG_ALWAYS_ON)
-#define genpd_is_active_wakeup(genpd)	(genpd->flags & GENPD_FLAG_ACTIVE_WAKEUP)
-#define genpd_is_cpu_domain(genpd)	(genpd->flags & GENPD_FLAG_CPU_DOMAIN)
-#define genpd_is_rpm_always_on(genpd)	(genpd->flags & GENPD_FLAG_RPM_ALWAYS_ON)
-
-static inline bool irq_safe_dev_in_no_sleep_domain(struct device *dev,
-		const struct generic_pm_domain *genpd)
-{
-	bool ret;
-
-	ret = pm_runtime_is_irq_safe(dev) && !genpd_is_irq_safe(genpd);
-
-	/*
-	 * Warn once if an IRQ safe device is attached to a no sleep domain, as
-	 * to indicate a suboptimal configuration for PM. For an always on
-	 * domain this isn't case, thus don't warn.
-	 */
-	if (ret && !genpd_is_always_on(genpd))
-		dev_warn_once(dev, "PM domain %s will not be powered off\n",
-				genpd->name);
-
-	return ret;
-}
-
-static int genpd_runtime_suspend(struct device *dev);
-
-/*
- * Get the generic PM domain for a particular struct device.
- * This validates the struct device pointer, the PM domain pointer,
- * and checks that the PM domain pointer is a real generic PM domain.
- * Any failure results in NULL being returned.
- */
-static struct generic_pm_domain *dev_to_genpd_safe(struct device *dev)
-{
-	if (IS_ERR_OR_NULL(dev) || IS_ERR_OR_NULL(dev->pm_domain))
-		return NULL;
-
-	/* A genpd's always have its ->runtime_suspend() callback assigned. */
-	if (dev->pm_domain->ops.runtime_suspend == genpd_runtime_suspend)
-		return pd_to_genpd(dev->pm_domain);
-
-	return NULL;
-}
-
-/*
- * This should only be used where we are certain that the pm_domain
- * attached to the device is a genpd domain.
- */
-static struct generic_pm_domain *dev_to_genpd(struct device *dev)
-{
-	if (IS_ERR_OR_NULL(dev->pm_domain))
-		return ERR_PTR(-EINVAL);
-
-	return pd_to_genpd(dev->pm_domain);
-}
-
-static int genpd_stop_dev(const struct generic_pm_domain *genpd,
-			  struct device *dev)
-{
-	return GENPD_DEV_CALLBACK(genpd, int, stop, dev);
-}
-
-static int genpd_start_dev(const struct generic_pm_domain *genpd,
-			   struct device *dev)
-{
-	return GENPD_DEV_CALLBACK(genpd, int, start, dev);
-}
-
-static bool genpd_sd_counter_dec(struct generic_pm_domain *genpd)
-{
-	bool ret = false;
-
-	if (!WARN_ON(atomic_read(&genpd->sd_count) == 0))
-		ret = !!atomic_dec_and_test(&genpd->sd_count);
-
-	return ret;
-}
-
-static void genpd_sd_counter_inc(struct generic_pm_domain *genpd)
-{
-	atomic_inc(&genpd->sd_count);
-	smp_mb__after_atomic();
-}
-
-#ifdef CONFIG_DEBUG_FS
-static void genpd_update_accounting(struct generic_pm_domain *genpd)
-{
-	ktime_t delta, now;
-
-	now = ktime_get();
-	delta = ktime_sub(now, genpd->accounting_time);
-
-	/*
-	 * If genpd->status is active, it means we are just
-	 * out of off and so update the idle time and vice
-	 * versa.
-	 */
-	if (genpd->status == GPD_STATE_ACTIVE) {
-		int state_idx = genpd->state_idx;
-
-		genpd->states[state_idx].idle_time =
-			ktime_add(genpd->states[state_idx].idle_time, delta);
-	} else {
-		genpd->on_time = ktime_add(genpd->on_time, delta);
-	}
-
-	genpd->accounting_time = now;
-}
-#else
-static inline void genpd_update_accounting(struct generic_pm_domain *genpd) {}
-#endif
-
-static int _genpd_reeval_performance_state(struct generic_pm_domain *genpd,
-					   unsigned int state)
-{
-	struct generic_pm_domain_data *pd_data;
-	struct pm_domain_data *pdd;
-	struct gpd_link *link;
-
-	/* New requested state is same as Max requested state */
-	if (state == genpd->performance_state)
-		return state;
-
-	/* New requested state is higher than Max requested state */
-	if (state > genpd->performance_state)
-		return state;
-
-	/* Traverse all devices within the domain */
-	list_for_each_entry(pdd, &genpd->dev_list, list_node) {
-		pd_data = to_gpd_data(pdd);
-
-		if (pd_data->performance_state > state)
-			state = pd_data->performance_state;
-	}
-
-	/*
-	 * Traverse all sub-domains within the domain. This can be
-	 * done without any additional locking as the link->performance_state
-	 * field is protected by the master genpd->lock, which is already taken.
-	 *
-	 * Also note that link->performance_state (subdomain's performance state
-	 * requirement to master domain) is different from
-	 * link->slave->performance_state (current performance state requirement
-	 * of the devices/sub-domains of the subdomain) and so can have a
-	 * different value.
-	 *
-	 * Note that we also take vote from powered-off sub-domains into account
-	 * as the same is done for devices right now.
-	 */
-	list_for_each_entry(link, &genpd->master_links, master_node) {
-		if (link->performance_state > state)
-			state = link->performance_state;
-	}
-
-	return state;
-}
-
-static int _genpd_set_performance_state(struct generic_pm_domain *genpd,
-					unsigned int state, int depth)
-{
-	struct generic_pm_domain *master;
-	struct gpd_link *link;
-	int master_state, ret;
-
-	if (state == genpd->performance_state)
-		return 0;
-
-	/* Propagate to masters of genpd */
-	list_for_each_entry(link, &genpd->slave_links, slave_node) {
-		master = link->master;
-
-		if (!master->set_performance_state)
-			continue;
-
-		/* Find master's performance state */
-		ret = dev_pm_opp_xlate_performance_state(genpd->opp_table,
-							 master->opp_table,
-							 state);
-		if (unlikely(ret < 0))
-			goto err;
-
-		master_state = ret;
-
-		genpd_lock_nested(master, depth + 1);
-
-		link->prev_performance_state = link->performance_state;
-		link->performance_state = master_state;
-		master_state = _genpd_reeval_performance_state(master,
-						master_state);
-		ret = _genpd_set_performance_state(master, master_state, depth + 1);
-		if (ret)
-			link->performance_state = link->prev_performance_state;
-
-		genpd_unlock(master);
-
-		if (ret)
-			goto err;
-	}
-
-	ret = genpd->set_performance_state(genpd, state);
-	if (ret)
-		goto err;
-
-	genpd->performance_state = state;
-	return 0;
-
-err:
-	/* Encountered an error, lets rollback */
-	list_for_each_entry_continue_reverse(link, &genpd->slave_links,
-					     slave_node) {
-		master = link->master;
-
-		if (!master->set_performance_state)
-			continue;
-
-		genpd_lock_nested(master, depth + 1);
-
-		master_state = link->prev_performance_state;
-		link->performance_state = master_state;
-
-		master_state = _genpd_reeval_performance_state(master,
-						master_state);
-		if (_genpd_set_performance_state(master, master_state, depth + 1)) {
-			pr_err("%s: Failed to roll back to %d performance state\n",
-			       master->name, master_state);
-		}
-
-		genpd_unlock(master);
-	}
-
-	return ret;
-}
-
-/**
- * dev_pm_genpd_set_performance_state- Set performance state of device's power
- * domain.
- *
- * @dev: Device for which the performance-state needs to be set.
- * @state: Target performance state of the device. This can be set as 0 when the
- *	   device doesn't have any performance state constraints left (And so
- *	   the device wouldn't participate anymore to find the target
- *	   performance state of the genpd).
- *
- * It is assumed that the users guarantee that the genpd wouldn't be detached
- * while this routine is getting called.
- *
- * Returns 0 on success and negative error values on failures.
- */
-int dev_pm_genpd_set_performance_state(struct device *dev, unsigned int state)
-{
-	struct generic_pm_domain *genpd;
-	struct generic_pm_domain_data *gpd_data;
-	unsigned int prev;
-	int ret;
-
-	genpd = dev_to_genpd_safe(dev);
-	if (!genpd)
-		return -ENODEV;
-
-	if (unlikely(!genpd->set_performance_state))
-		return -EINVAL;
-
-	if (WARN_ON(!dev->power.subsys_data ||
-		     !dev->power.subsys_data->domain_data))
-		return -EINVAL;
-
-	genpd_lock(genpd);
-
-	gpd_data = to_gpd_data(dev->power.subsys_data->domain_data);
-	prev = gpd_data->performance_state;
-	gpd_data->performance_state = state;
-
-	state = _genpd_reeval_performance_state(genpd, state);
-	ret = _genpd_set_performance_state(genpd, state, 0);
-	if (ret)
-		gpd_data->performance_state = prev;
-
-	genpd_unlock(genpd);
-
-	return ret;
-}
-EXPORT_SYMBOL_GPL(dev_pm_genpd_set_performance_state);
-
-static int _genpd_power_on(struct generic_pm_domain *genpd, bool timed)
-{
-	unsigned int state_idx = genpd->state_idx;
-	ktime_t time_start;
-	s64 elapsed_ns;
-	int ret;
-
-	if (!genpd->power_on)
-		return 0;
-
-	if (!timed)
-		return genpd->power_on(genpd);
-
-	time_start = ktime_get();
-	ret = genpd->power_on(genpd);
-	if (ret)
-		return ret;
-
-	elapsed_ns = ktime_to_ns(ktime_sub(ktime_get(), time_start));
-	if (elapsed_ns <= genpd->states[state_idx].power_on_latency_ns)
-		return ret;
-
-	genpd->states[state_idx].power_on_latency_ns = elapsed_ns;
-	genpd->max_off_time_changed = true;
-	pr_debug("%s: Power-%s latency exceeded, new value %lld ns\n",
-		 genpd->name, "on", elapsed_ns);
-
-	return ret;
-}
-
-static int _genpd_power_off(struct generic_pm_domain *genpd, bool timed)
-{
-	unsigned int state_idx = genpd->state_idx;
-	ktime_t time_start;
-	s64 elapsed_ns;
-	int ret;
-
-	if (!genpd->power_off)
-		return 0;
-
-	if (!timed)
-		return genpd->power_off(genpd);
-
-	time_start = ktime_get();
-	ret = genpd->power_off(genpd);
-	if (ret)
-		return ret;
-
-	elapsed_ns = ktime_to_ns(ktime_sub(ktime_get(), time_start));
-	if (elapsed_ns <= genpd->states[state_idx].power_off_latency_ns)
-		return 0;
-
-	genpd->states[state_idx].power_off_latency_ns = elapsed_ns;
-	genpd->max_off_time_changed = true;
-	pr_debug("%s: Power-%s latency exceeded, new value %lld ns\n",
-		 genpd->name, "off", elapsed_ns);
-
-	return 0;
-}
-
-/**
- * genpd_queue_power_off_work - Queue up the execution of genpd_power_off().
- * @genpd: PM domain to power off.
- *
- * Queue up the execution of genpd_power_off() unless it's already been done
- * before.
- */
-static void genpd_queue_power_off_work(struct generic_pm_domain *genpd)
-{
-	queue_work(pm_wq, &genpd->power_off_work);
-}
-
-/**
- * genpd_power_off - Remove power from a given PM domain.
- * @genpd: PM domain to power down.
- * @one_dev_on: If invoked from genpd's ->runtime_suspend|resume() callback, the
- * RPM status of the releated device is in an intermediate state, not yet turned
- * into RPM_SUSPENDED. This means genpd_power_off() must allow one device to not
- * be RPM_SUSPENDED, while it tries to power off the PM domain.
- *
- * If all of the @genpd's devices have been suspended and all of its subdomains
- * have been powered down, remove power from @genpd.
- */
-static int genpd_power_off(struct generic_pm_domain *genpd, bool one_dev_on,
-			   unsigned int depth)
-{
-	struct pm_domain_data *pdd;
-	struct gpd_link *link;
-	unsigned int not_suspended = 0;
-
-	/*
-	 * Do not try to power off the domain in the following situations:
-	 * (1) The domain is already in the "power off" state.
-	 * (2) System suspend is in progress.
-	 */
-	if (!genpd_status_on(genpd) || genpd->prepared_count > 0)
-		return 0;
-
-	/*
-	 * Abort power off for the PM domain in the following situations:
-	 * (1) The domain is configured as always on.
-	 * (2) When the domain has a subdomain being powered on.
-	 */
-	if (genpd_is_always_on(genpd) ||
-			genpd_is_rpm_always_on(genpd) ||
-			atomic_read(&genpd->sd_count) > 0)
-		return -EBUSY;
-
-	list_for_each_entry(pdd, &genpd->dev_list, list_node) {
-		enum pm_qos_flags_status stat;
-
-		stat = dev_pm_qos_flags(pdd->dev, PM_QOS_FLAG_NO_POWER_OFF);
-		if (stat > PM_QOS_FLAGS_NONE)
-			return -EBUSY;
-
-		/*
-		 * Do not allow PM domain to be powered off, when an IRQ safe
-		 * device is part of a non-IRQ safe domain.
-		 */
-		if (!pm_runtime_suspended(pdd->dev) ||
-			irq_safe_dev_in_no_sleep_domain(pdd->dev, genpd))
-			not_suspended++;
-	}
-
-	if (not_suspended > 1 || (not_suspended == 1 && !one_dev_on))
-		return -EBUSY;
-
-	if (genpd->gov && genpd->gov->power_down_ok) {
-		if (!genpd->gov->power_down_ok(&genpd->domain))
-			return -EAGAIN;
-	}
-
-	/* Default to shallowest state. */
-	if (!genpd->gov)
-		genpd->state_idx = 0;
-
-	if (genpd->power_off) {
-		int ret;
-
-		if (atomic_read(&genpd->sd_count) > 0)
-			return -EBUSY;
-
-		/*
-		 * If sd_count > 0 at this point, one of the subdomains hasn't
-		 * managed to call genpd_power_on() for the master yet after
-		 * incrementing it.  In that case genpd_power_on() will wait
-		 * for us to drop the lock, so we can call .power_off() and let
-		 * the genpd_power_on() restore power for us (this shouldn't
-		 * happen very often).
-		 */
-		ret = _genpd_power_off(genpd, true);
-		if (ret)
-			return ret;
-	}
-
-	genpd->status = GPD_STATE_POWER_OFF;
-	genpd_update_accounting(genpd);
-
-	list_for_each_entry(link, &genpd->slave_links, slave_node) {
-		genpd_sd_counter_dec(link->master);
-		genpd_lock_nested(link->master, depth + 1);
-		genpd_power_off(link->master, false, depth + 1);
-		genpd_unlock(link->master);
-	}
-
-	return 0;
-}
-
-/**
- * genpd_power_on - Restore power to a given PM domain and its masters.
- * @genpd: PM domain to power up.
- * @depth: nesting count for lockdep.
- *
- * Restore power to @genpd and all of its masters so that it is possible to
- * resume a device belonging to it.
- */
-static int genpd_power_on(struct generic_pm_domain *genpd, unsigned int depth)
-{
-	struct gpd_link *link;
-	int ret = 0;
-
-	if (genpd_status_on(genpd))
-		return 0;
-
-	/*
-	 * The list is guaranteed not to change while the loop below is being
-	 * executed, unless one of the masters' .power_on() callbacks fiddles
-	 * with it.
-	 */
-	list_for_each_entry(link, &genpd->slave_links, slave_node) {
-		struct generic_pm_domain *master = link->master;
-
-		genpd_sd_counter_inc(master);
-
-		genpd_lock_nested(master, depth + 1);
-		ret = genpd_power_on(master, depth + 1);
-		genpd_unlock(master);
-
-		if (ret) {
-			genpd_sd_counter_dec(master);
-			goto err;
-		}
-	}
-
-	ret = _genpd_power_on(genpd, true);
-	if (ret)
-		goto err;
-
-	genpd->status = GPD_STATE_ACTIVE;
-	genpd_update_accounting(genpd);
-
-	return 0;
-
- err:
-	list_for_each_entry_continue_reverse(link,
-					&genpd->slave_links,
-					slave_node) {
-		genpd_sd_counter_dec(link->master);
-		genpd_lock_nested(link->master, depth + 1);
-		genpd_power_off(link->master, false, depth + 1);
-		genpd_unlock(link->master);
-	}
-
-	return ret;
-}
-
-static int genpd_dev_pm_start(struct device *dev)
-{
-	struct generic_pm_domain *genpd = dev_to_genpd(dev);
-
-	return genpd_start_dev(genpd, dev);
-}
-
-static int genpd_dev_pm_qos_notifier(struct notifier_block *nb,
-				     unsigned long val, void *ptr)
-{
-	struct generic_pm_domain_data *gpd_data;
-	struct device *dev;
-
-	gpd_data = container_of(nb, struct generic_pm_domain_data, nb);
-	dev = gpd_data->base.dev;
-
-	for (;;) {
-		struct generic_pm_domain *genpd;
-		struct pm_domain_data *pdd;
-
-		spin_lock_irq(&dev->power.lock);
-
-		pdd = dev->power.subsys_data ?
-				dev->power.subsys_data->domain_data : NULL;
-		if (pdd) {
-			to_gpd_data(pdd)->td.constraint_changed = true;
-			genpd = dev_to_genpd(dev);
-		} else {
-			genpd = ERR_PTR(-ENODATA);
-		}
-
-		spin_unlock_irq(&dev->power.lock);
-
-		if (!IS_ERR(genpd)) {
-			genpd_lock(genpd);
-			genpd->max_off_time_changed = true;
-			genpd_unlock(genpd);
-		}
-
-		dev = dev->parent;
-		if (!dev || dev->power.ignore_children)
-			break;
-	}
-
-	return NOTIFY_DONE;
-}
-
-/**
- * genpd_power_off_work_fn - Power off PM domain whose subdomain count is 0.
- * @work: Work structure used for scheduling the execution of this function.
- */
-static void genpd_power_off_work_fn(struct work_struct *work)
-{
-	struct generic_pm_domain *genpd;
-
-	genpd = container_of(work, struct generic_pm_domain, power_off_work);
-
-	genpd_lock(genpd);
-	genpd_power_off(genpd, false, 0);
-	genpd_unlock(genpd);
-}
-
-/**
- * __genpd_runtime_suspend - walk the hierarchy of ->runtime_suspend() callbacks
- * @dev: Device to handle.
- */
-static int __genpd_runtime_suspend(struct device *dev)
-{
-	int (*cb)(struct device *__dev);
-
-	if (dev->type && dev->type->pm)
-		cb = dev->type->pm->runtime_suspend;
-	else if (dev->class && dev->class->pm)
-		cb = dev->class->pm->runtime_suspend;
-	else if (dev->bus && dev->bus->pm)
-		cb = dev->bus->pm->runtime_suspend;
-	else
-		cb = NULL;
-
-	if (!cb && dev->driver && dev->driver->pm)
-		cb = dev->driver->pm->runtime_suspend;
-
-	return cb ? cb(dev) : 0;
-}
-
-/**
- * __genpd_runtime_resume - walk the hierarchy of ->runtime_resume() callbacks
- * @dev: Device to handle.
- */
-static int __genpd_runtime_resume(struct device *dev)
-{
-	int (*cb)(struct device *__dev);
-
-	if (dev->type && dev->type->pm)
-		cb = dev->type->pm->runtime_resume;
-	else if (dev->class && dev->class->pm)
-		cb = dev->class->pm->runtime_resume;
-	else if (dev->bus && dev->bus->pm)
-		cb = dev->bus->pm->runtime_resume;
-	else
-		cb = NULL;
-
-	if (!cb && dev->driver && dev->driver->pm)
-		cb = dev->driver->pm->runtime_resume;
-
-	return cb ? cb(dev) : 0;
-}
-
-/**
- * genpd_runtime_suspend - Suspend a device belonging to I/O PM domain.
- * @dev: Device to suspend.
- *
- * Carry out a runtime suspend of a device under the assumption that its
- * pm_domain field points to the domain member of an object of type
- * struct generic_pm_domain representing a PM domain consisting of I/O devices.
- */
-static int genpd_runtime_suspend(struct device *dev)
-{
-	struct generic_pm_domain *genpd;
-	bool (*suspend_ok)(struct device *__dev);
-	struct gpd_timing_data *td = &dev_gpd_data(dev)->td;
-	bool runtime_pm = pm_runtime_enabled(dev);
-	ktime_t time_start;
-	s64 elapsed_ns;
-	int ret;
-
-	dev_dbg(dev, "%s()\n", __func__);
-
-	genpd = dev_to_genpd(dev);
-	if (IS_ERR(genpd))
-		return -EINVAL;
-
-	/*
-	 * A runtime PM centric subsystem/driver may re-use the runtime PM
-	 * callbacks for other purposes than runtime PM. In those scenarios
-	 * runtime PM is disabled. Under these circumstances, we shall skip
-	 * validating/measuring the PM QoS latency.
-	 */
-	suspend_ok = genpd->gov ? genpd->gov->suspend_ok : NULL;
-	if (runtime_pm && suspend_ok && !suspend_ok(dev))
-		return -EBUSY;
-
-	/* Measure suspend latency. */
-	time_start = 0;
-	if (runtime_pm)
-		time_start = ktime_get();
-
-	ret = __genpd_runtime_suspend(dev);
-	if (ret)
-		return ret;
-
-	ret = genpd_stop_dev(genpd, dev);
-	if (ret) {
-		__genpd_runtime_resume(dev);
-		return ret;
-	}
-
-	/* Update suspend latency value if the measured time exceeds it. */
-	if (runtime_pm) {
-		elapsed_ns = ktime_to_ns(ktime_sub(ktime_get(), time_start));
-		if (elapsed_ns > td->suspend_latency_ns) {
-			td->suspend_latency_ns = elapsed_ns;
-			dev_dbg(dev, "suspend latency exceeded, %lld ns\n",
-				elapsed_ns);
-			genpd->max_off_time_changed = true;
-			td->constraint_changed = true;
-		}
-	}
-
-	/*
-	 * If power.irq_safe is set, this routine may be run with
-	 * IRQs disabled, so suspend only if the PM domain also is irq_safe.
-	 */
-	if (irq_safe_dev_in_no_sleep_domain(dev, genpd))
-		return 0;
-
-	genpd_lock(genpd);
-	genpd_power_off(genpd, true, 0);
-	genpd_unlock(genpd);
-
-	return 0;
-}
-
-/**
- * genpd_runtime_resume - Resume a device belonging to I/O PM domain.
- * @dev: Device to resume.
- *
- * Carry out a runtime resume of a device under the assumption that its
- * pm_domain field points to the domain member of an object of type
- * struct generic_pm_domain representing a PM domain consisting of I/O devices.
- */
-static int genpd_runtime_resume(struct device *dev)
-{
-	struct generic_pm_domain *genpd;
-	struct gpd_timing_data *td = &dev_gpd_data(dev)->td;
-	bool runtime_pm = pm_runtime_enabled(dev);
-	ktime_t time_start;
-	s64 elapsed_ns;
-	int ret;
-	bool timed = true;
-
-	dev_dbg(dev, "%s()\n", __func__);
-
-	genpd = dev_to_genpd(dev);
-	if (IS_ERR(genpd))
-		return -EINVAL;
-
-	/*
-	 * As we don't power off a non IRQ safe domain, which holds
-	 * an IRQ safe device, we don't need to restore power to it.
-	 */
-	if (irq_safe_dev_in_no_sleep_domain(dev, genpd)) {
-		timed = false;
-		goto out;
-	}
-
-	genpd_lock(genpd);
-	ret = genpd_power_on(genpd, 0);
-	genpd_unlock(genpd);
-
-	if (ret)
-		return ret;
-
- out:
-	/* Measure resume latency. */
-	time_start = 0;
-	if (timed && runtime_pm)
-		time_start = ktime_get();
-
-	ret = genpd_start_dev(genpd, dev);
-	if (ret)
-		goto err_poweroff;
-
-	ret = __genpd_runtime_resume(dev);
-	if (ret)
-		goto err_stop;
-
-	/* Update resume latency value if the measured time exceeds it. */
-	if (timed && runtime_pm) {
-		elapsed_ns = ktime_to_ns(ktime_sub(ktime_get(), time_start));
-		if (elapsed_ns > td->resume_latency_ns) {
-			td->resume_latency_ns = elapsed_ns;
-			dev_dbg(dev, "resume latency exceeded, %lld ns\n",
-				elapsed_ns);
-			genpd->max_off_time_changed = true;
-			td->constraint_changed = true;
-		}
-	}
-
-	return 0;
-
-err_stop:
-	genpd_stop_dev(genpd, dev);
-err_poweroff:
-	if (!pm_runtime_is_irq_safe(dev) ||
-		(pm_runtime_is_irq_safe(dev) && genpd_is_irq_safe(genpd))) {
-		genpd_lock(genpd);
-		genpd_power_off(genpd, true, 0);
-		genpd_unlock(genpd);
-	}
-
-	return ret;
-}
-
-static bool pd_ignore_unused;
-static int __init pd_ignore_unused_setup(char *__unused)
-{
-	pd_ignore_unused = true;
-	return 1;
-}
-__setup("pd_ignore_unused", pd_ignore_unused_setup);
-
-/**
- * genpd_power_off_unused - Power off all PM domains with no devices in use.
- */
-static int __init genpd_power_off_unused(void)
-{
-	struct generic_pm_domain *genpd;
-
-	if (pd_ignore_unused) {
-		pr_warn("genpd: Not disabling unused power domains\n");
-		return 0;
-	}
-
-	mutex_lock(&gpd_list_lock);
-
-	list_for_each_entry(genpd, &gpd_list, gpd_list_node)
-		genpd_queue_power_off_work(genpd);
-
-	mutex_unlock(&gpd_list_lock);
-
-	return 0;
-}
-late_initcall(genpd_power_off_unused);
-
-#ifdef CONFIG_PM_SLEEP
-
-/**
- * genpd_sync_power_off - Synchronously power off a PM domain and its masters.
- * @genpd: PM domain to power off, if possible.
- * @use_lock: use the lock.
- * @depth: nesting count for lockdep.
- *
- * Check if the given PM domain can be powered off (during system suspend or
- * hibernation) and do that if so.  Also, in that case propagate to its masters.
- *
- * This function is only called in "noirq" and "syscore" stages of system power
- * transitions. The "noirq" callbacks may be executed asynchronously, thus in
- * these cases the lock must be held.
- */
-static void genpd_sync_power_off(struct generic_pm_domain *genpd, bool use_lock,
-				 unsigned int depth)
-{
-	struct gpd_link *link;
-
-	if (!genpd_status_on(genpd) || genpd_is_always_on(genpd))
-		return;
-
-	if (genpd->suspended_count != genpd->device_count
-	    || atomic_read(&genpd->sd_count) > 0)
-		return;
-
-	/* Choose the deepest state when suspending */
-	genpd->state_idx = genpd->state_count - 1;
-	if (_genpd_power_off(genpd, false))
-		return;
-
-	genpd->status = GPD_STATE_POWER_OFF;
-
-	list_for_each_entry(link, &genpd->slave_links, slave_node) {
-		genpd_sd_counter_dec(link->master);
-
-		if (use_lock)
-			genpd_lock_nested(link->master, depth + 1);
-
-		genpd_sync_power_off(link->master, use_lock, depth + 1);
-
-		if (use_lock)
-			genpd_unlock(link->master);
-	}
-}
-
-/**
- * genpd_sync_power_on - Synchronously power on a PM domain and its masters.
- * @genpd: PM domain to power on.
- * @use_lock: use the lock.
- * @depth: nesting count for lockdep.
- *
- * This function is only called in "noirq" and "syscore" stages of system power
- * transitions. The "noirq" callbacks may be executed asynchronously, thus in
- * these cases the lock must be held.
- */
-static void genpd_sync_power_on(struct generic_pm_domain *genpd, bool use_lock,
-				unsigned int depth)
-{
-	struct gpd_link *link;
-
-	if (genpd_status_on(genpd))
-		return;
-
-	list_for_each_entry(link, &genpd->slave_links, slave_node) {
-		genpd_sd_counter_inc(link->master);
-
-		if (use_lock)
-			genpd_lock_nested(link->master, depth + 1);
-
-		genpd_sync_power_on(link->master, use_lock, depth + 1);
-
-		if (use_lock)
-			genpd_unlock(link->master);
-	}
-
-	_genpd_power_on(genpd, false);
-
-	genpd->status = GPD_STATE_ACTIVE;
-}
-
-/**
- * resume_needed - Check whether to resume a device before system suspend.
- * @dev: Device to check.
- * @genpd: PM domain the device belongs to.
- *
- * There are two cases in which a device that can wake up the system from sleep
- * states should be resumed by genpd_prepare(): (1) if the device is enabled
- * to wake up the system and it has to remain active for this purpose while the
- * system is in the sleep state and (2) if the device is not enabled to wake up
- * the system from sleep states and it generally doesn't generate wakeup signals
- * by itself (those signals are generated on its behalf by other parts of the
- * system).  In the latter case it may be necessary to reconfigure the device's
- * wakeup settings during system suspend, because it may have been set up to
- * signal remote wakeup from the system's working state as needed by runtime PM.
- * Return 'true' in either of the above cases.
- */
-static bool resume_needed(struct device *dev,
-			  const struct generic_pm_domain *genpd)
-{
-	bool active_wakeup;
-
-	if (!device_can_wakeup(dev))
-		return false;
-
-	active_wakeup = genpd_is_active_wakeup(genpd);
-	return device_may_wakeup(dev) ? active_wakeup : !active_wakeup;
-}
-
-/**
- * genpd_prepare - Start power transition of a device in a PM domain.
- * @dev: Device to start the transition of.
- *
- * Start a power transition of a device (during a system-wide power transition)
- * under the assumption that its pm_domain field points to the domain member of
- * an object of type struct generic_pm_domain representing a PM domain
- * consisting of I/O devices.
- */
-static int genpd_prepare(struct device *dev)
-{
-	struct generic_pm_domain *genpd;
-	int ret;
-
-	dev_dbg(dev, "%s()\n", __func__);
-
-	genpd = dev_to_genpd(dev);
-	if (IS_ERR(genpd))
-		return -EINVAL;
-
-	/*
-	 * If a wakeup request is pending for the device, it should be woken up
-	 * at this point and a system wakeup event should be reported if it's
-	 * set up to wake up the system from sleep states.
-	 */
-	if (resume_needed(dev, genpd))
-		pm_runtime_resume(dev);
-
-	genpd_lock(genpd);
-
-	if (genpd->prepared_count++ == 0)
-		genpd->suspended_count = 0;
-
-	genpd_unlock(genpd);
-
-	ret = pm_generic_prepare(dev);
-	if (ret < 0) {
-		genpd_lock(genpd);
-
-		genpd->prepared_count--;
-
-		genpd_unlock(genpd);
-	}
-
-	/* Never return 1, as genpd don't cope with the direct_complete path. */
-	return ret >= 0 ? 0 : ret;
-}
-
-/**
- * genpd_finish_suspend - Completion of suspend or hibernation of device in an
- *   I/O pm domain.
- * @dev: Device to suspend.
- * @poweroff: Specifies if this is a poweroff_noirq or suspend_noirq callback.
- *
- * Stop the device and remove power from the domain if all devices in it have
- * been stopped.
- */
-static int genpd_finish_suspend(struct device *dev, bool poweroff)
-{
-	struct generic_pm_domain *genpd;
-	int ret = 0;
-
-	genpd = dev_to_genpd(dev);
-	if (IS_ERR(genpd))
-		return -EINVAL;
-
-	if (poweroff)
-		ret = pm_generic_poweroff_noirq(dev);
-	else
-		ret = pm_generic_suspend_noirq(dev);
-	if (ret)
-		return ret;
-
-	if (dev->power.wakeup_path && genpd_is_active_wakeup(genpd))
-		return 0;
-
-	if (genpd->dev_ops.stop && genpd->dev_ops.start &&
-	    !pm_runtime_status_suspended(dev)) {
-		ret = genpd_stop_dev(genpd, dev);
-		if (ret) {
-			if (poweroff)
-				pm_generic_restore_noirq(dev);
-			else
-				pm_generic_resume_noirq(dev);
-			return ret;
-		}
-	}
-
-	genpd_lock(genpd);
-	genpd->suspended_count++;
-	genpd_sync_power_off(genpd, true, 0);
-	genpd_unlock(genpd);
-
-	return 0;
-}
-
-/**
- * genpd_suspend_noirq - Completion of suspend of device in an I/O PM domain.
- * @dev: Device to suspend.
- *
- * Stop the device and remove power from the domain if all devices in it have
- * been stopped.
- */
-static int genpd_suspend_noirq(struct device *dev)
-{
-	dev_dbg(dev, "%s()\n", __func__);
-
-	return genpd_finish_suspend(dev, false);
-}
-
-/**
- * genpd_resume_noirq - Start of resume of device in an I/O PM domain.
- * @dev: Device to resume.
- *
- * Restore power to the device's PM domain, if necessary, and start the device.
- */
-static int genpd_resume_noirq(struct device *dev)
-{
-	struct generic_pm_domain *genpd;
-	int ret;
-
-	dev_dbg(dev, "%s()\n", __func__);
-
-	genpd = dev_to_genpd(dev);
-	if (IS_ERR(genpd))
-		return -EINVAL;
-
-	if (dev->power.wakeup_path && genpd_is_active_wakeup(genpd))
-		return pm_generic_resume_noirq(dev);
-
-	genpd_lock(genpd);
-	genpd_sync_power_on(genpd, true, 0);
-	genpd->suspended_count--;
-	genpd_unlock(genpd);
-
-	if (genpd->dev_ops.stop && genpd->dev_ops.start &&
-	    !pm_runtime_status_suspended(dev)) {
-		ret = genpd_start_dev(genpd, dev);
-		if (ret)
-			return ret;
-	}
-
-	return pm_generic_resume_noirq(dev);
-}
-
-/**
- * genpd_freeze_noirq - Completion of freezing a device in an I/O PM domain.
- * @dev: Device to freeze.
- *
- * Carry out a late freeze of a device under the assumption that its
- * pm_domain field points to the domain member of an object of type
- * struct generic_pm_domain representing a power domain consisting of I/O
- * devices.
- */
-static int genpd_freeze_noirq(struct device *dev)
-{
-	const struct generic_pm_domain *genpd;
-	int ret = 0;
-
-	dev_dbg(dev, "%s()\n", __func__);
-
-	genpd = dev_to_genpd(dev);
-	if (IS_ERR(genpd))
-		return -EINVAL;
-
-	ret = pm_generic_freeze_noirq(dev);
-	if (ret)
-		return ret;
-
-	if (genpd->dev_ops.stop && genpd->dev_ops.start &&
-	    !pm_runtime_status_suspended(dev))
-		ret = genpd_stop_dev(genpd, dev);
-
-	return ret;
-}
-
-/**
- * genpd_thaw_noirq - Early thaw of device in an I/O PM domain.
- * @dev: Device to thaw.
- *
- * Start the device, unless power has been removed from the domain already
- * before the system transition.
- */
-static int genpd_thaw_noirq(struct device *dev)
-{
-	const struct generic_pm_domain *genpd;
-	int ret = 0;
-
-	dev_dbg(dev, "%s()\n", __func__);
-
-	genpd = dev_to_genpd(dev);
-	if (IS_ERR(genpd))
-		return -EINVAL;
-
-	if (genpd->dev_ops.stop && genpd->dev_ops.start &&
-	    !pm_runtime_status_suspended(dev)) {
-		ret = genpd_start_dev(genpd, dev);
-		if (ret)
-			return ret;
-	}
-
-	return pm_generic_thaw_noirq(dev);
-}
-
-/**
- * genpd_poweroff_noirq - Completion of hibernation of device in an
- *   I/O PM domain.
- * @dev: Device to poweroff.
- *
- * Stop the device and remove power from the domain if all devices in it have
- * been stopped.
- */
-static int genpd_poweroff_noirq(struct device *dev)
-{
-	dev_dbg(dev, "%s()\n", __func__);
-
-	return genpd_finish_suspend(dev, true);
-}
-
-/**
- * genpd_restore_noirq - Start of restore of device in an I/O PM domain.
- * @dev: Device to resume.
- *
- * Make sure the domain will be in the same power state as before the
- * hibernation the system is resuming from and start the device if necessary.
- */
-static int genpd_restore_noirq(struct device *dev)
-{
-	struct generic_pm_domain *genpd;
-	int ret = 0;
-
-	dev_dbg(dev, "%s()\n", __func__);
-
-	genpd = dev_to_genpd(dev);
-	if (IS_ERR(genpd))
-		return -EINVAL;
-
-	/*
-	 * At this point suspended_count == 0 means we are being run for the
-	 * first time for the given domain in the present cycle.
-	 */
-	genpd_lock(genpd);
-	if (genpd->suspended_count++ == 0)
-		/*
-		 * The boot kernel might put the domain into arbitrary state,
-		 * so make it appear as powered off to genpd_sync_power_on(),
-		 * so that it tries to power it on in case it was really off.
-		 */
-		genpd->status = GPD_STATE_POWER_OFF;
-
-	genpd_sync_power_on(genpd, true, 0);
-	genpd_unlock(genpd);
-
-	if (genpd->dev_ops.stop && genpd->dev_ops.start &&
-	    !pm_runtime_status_suspended(dev)) {
-		ret = genpd_start_dev(genpd, dev);
-		if (ret)
-			return ret;
-	}
-
-	return pm_generic_restore_noirq(dev);
-}
-
-/**
- * genpd_complete - Complete power transition of a device in a power domain.
- * @dev: Device to complete the transition of.
- *
- * Complete a power transition of a device (during a system-wide power
- * transition) under the assumption that its pm_domain field points to the
- * domain member of an object of type struct generic_pm_domain representing
- * a power domain consisting of I/O devices.
- */
-static void genpd_complete(struct device *dev)
-{
-	struct generic_pm_domain *genpd;
-
-	dev_dbg(dev, "%s()\n", __func__);
-
-	genpd = dev_to_genpd(dev);
-	if (IS_ERR(genpd))
-		return;
-
-	pm_generic_complete(dev);
-
-	genpd_lock(genpd);
-
-	genpd->prepared_count--;
-	if (!genpd->prepared_count)
-		genpd_queue_power_off_work(genpd);
-
-	genpd_unlock(genpd);
-}
-
-/**
- * genpd_syscore_switch - Switch power during system core suspend or resume.
- * @dev: Device that normally is marked as "always on" to switch power for.
- *
- * This routine may only be called during the system core (syscore) suspend or
- * resume phase for devices whose "always on" flags are set.
- */
-static void genpd_syscore_switch(struct device *dev, bool suspend)
-{
-	struct generic_pm_domain *genpd;
-
-	genpd = dev_to_genpd_safe(dev);
-	if (!genpd)
-		return;
-
-	if (suspend) {
-		genpd->suspended_count++;
-		genpd_sync_power_off(genpd, false, 0);
-	} else {
-		genpd_sync_power_on(genpd, false, 0);
-		genpd->suspended_count--;
-	}
-}
-
-void pm_genpd_syscore_poweroff(struct device *dev)
-{
-	genpd_syscore_switch(dev, true);
-}
-EXPORT_SYMBOL_GPL(pm_genpd_syscore_poweroff);
-
-void pm_genpd_syscore_poweron(struct device *dev)
-{
-	genpd_syscore_switch(dev, false);
-}
-EXPORT_SYMBOL_GPL(pm_genpd_syscore_poweron);
-
-#else /* !CONFIG_PM_SLEEP */
-
-#define genpd_prepare		NULL
-#define genpd_suspend_noirq	NULL
-#define genpd_resume_noirq	NULL
-#define genpd_freeze_noirq	NULL
-#define genpd_thaw_noirq	NULL
-#define genpd_poweroff_noirq	NULL
-#define genpd_restore_noirq	NULL
-#define genpd_complete		NULL
-
-#endif /* CONFIG_PM_SLEEP */
-
-static struct generic_pm_domain_data *genpd_alloc_dev_data(struct device *dev)
-{
-	struct generic_pm_domain_data *gpd_data;
-	int ret;
-
-	ret = dev_pm_get_subsys_data(dev);
-	if (ret)
-		return ERR_PTR(ret);
-
-	gpd_data = kzalloc(sizeof(*gpd_data), GFP_KERNEL);
-	if (!gpd_data) {
-		ret = -ENOMEM;
-		goto err_put;
-	}
-
-	gpd_data->base.dev = dev;
-	gpd_data->td.constraint_changed = true;
-	gpd_data->td.effective_constraint_ns = PM_QOS_RESUME_LATENCY_NO_CONSTRAINT_NS;
-	gpd_data->nb.notifier_call = genpd_dev_pm_qos_notifier;
-
-	spin_lock_irq(&dev->power.lock);
-
-	if (dev->power.subsys_data->domain_data) {
-		ret = -EINVAL;
-		goto err_free;
-	}
-
-	dev->power.subsys_data->domain_data = &gpd_data->base;
-
-	spin_unlock_irq(&dev->power.lock);
-
-	return gpd_data;
-
- err_free:
-	spin_unlock_irq(&dev->power.lock);
-	kfree(gpd_data);
- err_put:
-	dev_pm_put_subsys_data(dev);
-	return ERR_PTR(ret);
-}
-
-static void genpd_free_dev_data(struct device *dev,
-				struct generic_pm_domain_data *gpd_data)
-{
-	spin_lock_irq(&dev->power.lock);
-
-	dev->power.subsys_data->domain_data = NULL;
-
-	spin_unlock_irq(&dev->power.lock);
-
-	kfree(gpd_data);
-	dev_pm_put_subsys_data(dev);
-}
-
-static void genpd_update_cpumask(struct generic_pm_domain *genpd,
-				 int cpu, bool set, unsigned int depth)
-{
-	struct gpd_link *link;
-
-	if (!genpd_is_cpu_domain(genpd))
-		return;
-
-	list_for_each_entry(link, &genpd->slave_links, slave_node) {
-		struct generic_pm_domain *master = link->master;
-
-		genpd_lock_nested(master, depth + 1);
-		genpd_update_cpumask(master, cpu, set, depth + 1);
-		genpd_unlock(master);
-	}
-
-	if (set)
-		cpumask_set_cpu(cpu, genpd->cpus);
-	else
-		cpumask_clear_cpu(cpu, genpd->cpus);
-}
-
-static void genpd_set_cpumask(struct generic_pm_domain *genpd, int cpu)
-{
-	if (cpu >= 0)
-		genpd_update_cpumask(genpd, cpu, true, 0);
-}
-
-static void genpd_clear_cpumask(struct generic_pm_domain *genpd, int cpu)
-{
-	if (cpu >= 0)
-		genpd_update_cpumask(genpd, cpu, false, 0);
-}
-
-static int genpd_get_cpu(struct generic_pm_domain *genpd, struct device *dev)
-{
-	int cpu;
-
-	if (!genpd_is_cpu_domain(genpd))
-		return -1;
-
-	for_each_possible_cpu(cpu) {
-		if (get_cpu_device(cpu) == dev)
-			return cpu;
-	}
-
-	return -1;
-}
-
-static int genpd_add_device(struct generic_pm_domain *genpd, struct device *dev,
-			    struct device *base_dev)
-{
-	struct generic_pm_domain_data *gpd_data;
-	int ret;
-
-	dev_dbg(dev, "%s()\n", __func__);
-
-	if (IS_ERR_OR_NULL(genpd) || IS_ERR_OR_NULL(dev))
-		return -EINVAL;
-
-	gpd_data = genpd_alloc_dev_data(dev);
-	if (IS_ERR(gpd_data))
-		return PTR_ERR(gpd_data);
-
-	gpd_data->cpu = genpd_get_cpu(genpd, base_dev);
-
-	ret = genpd->attach_dev ? genpd->attach_dev(genpd, dev) : 0;
-	if (ret)
-		goto out;
-
-	genpd_lock(genpd);
-
-	genpd_set_cpumask(genpd, gpd_data->cpu);
-	dev_pm_domain_set(dev, &genpd->domain);
-
-	genpd->device_count++;
-	genpd->max_off_time_changed = true;
-
-	list_add_tail(&gpd_data->base.list_node, &genpd->dev_list);
-
-	genpd_unlock(genpd);
- out:
-	if (ret)
-		genpd_free_dev_data(dev, gpd_data);
-	else
-		dev_pm_qos_add_notifier(dev, &gpd_data->nb,
-					DEV_PM_QOS_RESUME_LATENCY);
-
-	return ret;
-}
-
-/**
- * pm_genpd_add_device - Add a device to an I/O PM domain.
- * @genpd: PM domain to add the device to.
- * @dev: Device to be added.
- */
-int pm_genpd_add_device(struct generic_pm_domain *genpd, struct device *dev)
-{
-	int ret;
-
-	mutex_lock(&gpd_list_lock);
-	ret = genpd_add_device(genpd, dev, dev);
-	mutex_unlock(&gpd_list_lock);
-
-	return ret;
-}
-EXPORT_SYMBOL_GPL(pm_genpd_add_device);
-
-static int genpd_remove_device(struct generic_pm_domain *genpd,
-			       struct device *dev)
-{
-	struct generic_pm_domain_data *gpd_data;
-	struct pm_domain_data *pdd;
-	int ret = 0;
-
-	dev_dbg(dev, "%s()\n", __func__);
-
-	pdd = dev->power.subsys_data->domain_data;
-	gpd_data = to_gpd_data(pdd);
-	dev_pm_qos_remove_notifier(dev, &gpd_data->nb,
-				   DEV_PM_QOS_RESUME_LATENCY);
-
-	genpd_lock(genpd);
-
-	if (genpd->prepared_count > 0) {
-		ret = -EAGAIN;
-		goto out;
-	}
-
-	genpd->device_count--;
-	genpd->max_off_time_changed = true;
-
-	genpd_clear_cpumask(genpd, gpd_data->cpu);
-	dev_pm_domain_set(dev, NULL);
-
-	list_del_init(&pdd->list_node);
-
-	genpd_unlock(genpd);
-
-	if (genpd->detach_dev)
-		genpd->detach_dev(genpd, dev);
-
-	genpd_free_dev_data(dev, gpd_data);
-
-	return 0;
-
- out:
-	genpd_unlock(genpd);
-	dev_pm_qos_add_notifier(dev, &gpd_data->nb, DEV_PM_QOS_RESUME_LATENCY);
-
-	return ret;
-}
-
-/**
- * pm_genpd_remove_device - Remove a device from an I/O PM domain.
- * @dev: Device to be removed.
- */
-int pm_genpd_remove_device(struct device *dev)
-{
-	struct generic_pm_domain *genpd = dev_to_genpd_safe(dev);
-
-	if (!genpd)
-		return -EINVAL;
-
-	return genpd_remove_device(genpd, dev);
-}
-EXPORT_SYMBOL_GPL(pm_genpd_remove_device);
-
-static int genpd_add_subdomain(struct generic_pm_domain *genpd,
-			       struct generic_pm_domain *subdomain)
-{
-	struct gpd_link *link, *itr;
-	int ret = 0;
-
-	if (IS_ERR_OR_NULL(genpd) || IS_ERR_OR_NULL(subdomain)
-	    || genpd == subdomain)
-		return -EINVAL;
-
-	/*
-	 * If the domain can be powered on/off in an IRQ safe
-	 * context, ensure that the subdomain can also be
-	 * powered on/off in that context.
-	 */
-	if (!genpd_is_irq_safe(genpd) && genpd_is_irq_safe(subdomain)) {
-		WARN(1, "Parent %s of subdomain %s must be IRQ safe\n",
-				genpd->name, subdomain->name);
-		return -EINVAL;
-	}
-
-	link = kzalloc(sizeof(*link), GFP_KERNEL);
-	if (!link)
-		return -ENOMEM;
-
-	genpd_lock(subdomain);
-	genpd_lock_nested(genpd, SINGLE_DEPTH_NESTING);
-
-	if (!genpd_status_on(genpd) && genpd_status_on(subdomain)) {
-		ret = -EINVAL;
-		goto out;
-	}
-
-	list_for_each_entry(itr, &genpd->master_links, master_node) {
-		if (itr->slave == subdomain && itr->master == genpd) {
-			ret = -EINVAL;
-			goto out;
-		}
-	}
-
-	link->master = genpd;
-	list_add_tail(&link->master_node, &genpd->master_links);
-	link->slave = subdomain;
-	list_add_tail(&link->slave_node, &subdomain->slave_links);
-	if (genpd_status_on(subdomain))
-		genpd_sd_counter_inc(genpd);
-
- out:
-	genpd_unlock(genpd);
-	genpd_unlock(subdomain);
-	if (ret)
-		kfree(link);
-	return ret;
-}
-
-/**
- * pm_genpd_add_subdomain - Add a subdomain to an I/O PM domain.
- * @genpd: Master PM domain to add the subdomain to.
- * @subdomain: Subdomain to be added.
- */
-int pm_genpd_add_subdomain(struct generic_pm_domain *genpd,
-			   struct generic_pm_domain *subdomain)
-{
-	int ret;
-
-	mutex_lock(&gpd_list_lock);
-	ret = genpd_add_subdomain(genpd, subdomain);
-	mutex_unlock(&gpd_list_lock);
-
-	return ret;
-}
-EXPORT_SYMBOL_GPL(pm_genpd_add_subdomain);
-
-/**
- * pm_genpd_remove_subdomain - Remove a subdomain from an I/O PM domain.
- * @genpd: Master PM domain to remove the subdomain from.
- * @subdomain: Subdomain to be removed.
- */
-int pm_genpd_remove_subdomain(struct generic_pm_domain *genpd,
-			      struct generic_pm_domain *subdomain)
-{
-	struct gpd_link *l, *link;
-	int ret = -EINVAL;
-
-	if (IS_ERR_OR_NULL(genpd) || IS_ERR_OR_NULL(subdomain))
-		return -EINVAL;
-
-	genpd_lock(subdomain);
-	genpd_lock_nested(genpd, SINGLE_DEPTH_NESTING);
-
-	if (!list_empty(&subdomain->master_links) || subdomain->device_count) {
-		pr_warn("%s: unable to remove subdomain %s\n",
-			genpd->name, subdomain->name);
-		ret = -EBUSY;
-		goto out;
-	}
-
-	list_for_each_entry_safe(link, l, &genpd->master_links, master_node) {
-		if (link->slave != subdomain)
-			continue;
-
-		list_del(&link->master_node);
-		list_del(&link->slave_node);
-		kfree(link);
-		if (genpd_status_on(subdomain))
-			genpd_sd_counter_dec(genpd);
-
-		ret = 0;
-		break;
-	}
-
-out:
-	genpd_unlock(genpd);
-	genpd_unlock(subdomain);
-
-	return ret;
-}
-EXPORT_SYMBOL_GPL(pm_genpd_remove_subdomain);
-
-static void genpd_free_default_power_state(struct genpd_power_state *states,
-					   unsigned int state_count)
-{
-	kfree(states);
-}
-
-static int genpd_set_default_power_state(struct generic_pm_domain *genpd)
-{
-	struct genpd_power_state *state;
-
-	state = kzalloc(sizeof(*state), GFP_KERNEL);
-	if (!state)
-		return -ENOMEM;
-
-	genpd->states = state;
-	genpd->state_count = 1;
-	genpd->free_states = genpd_free_default_power_state;
-
-	return 0;
-}
-
-static void genpd_lock_init(struct generic_pm_domain *genpd)
-{
-	if (genpd->flags & GENPD_FLAG_IRQ_SAFE) {
-		spin_lock_init(&genpd->slock);
-		genpd->lock_ops = &genpd_spin_ops;
-	} else {
-		mutex_init(&genpd->mlock);
-		genpd->lock_ops = &genpd_mtx_ops;
-	}
-}
-
-/**
- * pm_genpd_init - Initialize a generic I/O PM domain object.
- * @genpd: PM domain object to initialize.
- * @gov: PM domain governor to associate with the domain (may be NULL).
- * @is_off: Initial value of the domain's power_is_off field.
- *
- * Returns 0 on successful initialization, else a negative error code.
- */
-int pm_genpd_init(struct generic_pm_domain *genpd,
-		  struct dev_power_governor *gov, bool is_off)
-{
-	int ret;
-
-	if (IS_ERR_OR_NULL(genpd))
-		return -EINVAL;
-
-	INIT_LIST_HEAD(&genpd->master_links);
-	INIT_LIST_HEAD(&genpd->slave_links);
-	INIT_LIST_HEAD(&genpd->dev_list);
-	genpd_lock_init(genpd);
-	genpd->gov = gov;
-	INIT_WORK(&genpd->power_off_work, genpd_power_off_work_fn);
-	atomic_set(&genpd->sd_count, 0);
-	genpd->status = is_off ? GPD_STATE_POWER_OFF : GPD_STATE_ACTIVE;
-	genpd->device_count = 0;
-	genpd->max_off_time_ns = -1;
-	genpd->max_off_time_changed = true;
-	genpd->provider = NULL;
-	genpd->has_provider = false;
-	genpd->accounting_time = ktime_get();
-	genpd->domain.ops.runtime_suspend = genpd_runtime_suspend;
-	genpd->domain.ops.runtime_resume = genpd_runtime_resume;
-	genpd->domain.ops.prepare = genpd_prepare;
-	genpd->domain.ops.suspend_noirq = genpd_suspend_noirq;
-	genpd->domain.ops.resume_noirq = genpd_resume_noirq;
-	genpd->domain.ops.freeze_noirq = genpd_freeze_noirq;
-	genpd->domain.ops.thaw_noirq = genpd_thaw_noirq;
-	genpd->domain.ops.poweroff_noirq = genpd_poweroff_noirq;
-	genpd->domain.ops.restore_noirq = genpd_restore_noirq;
-	genpd->domain.ops.complete = genpd_complete;
-	genpd->domain.start = genpd_dev_pm_start;
-
-	if (genpd->flags & GENPD_FLAG_PM_CLK) {
-		genpd->dev_ops.stop = pm_clk_suspend;
-		genpd->dev_ops.start = pm_clk_resume;
-	}
-
-	/* Always-on domains must be powered on at initialization. */
-	if ((genpd_is_always_on(genpd) || genpd_is_rpm_always_on(genpd)) &&
-			!genpd_status_on(genpd))
-		return -EINVAL;
-
-	if (genpd_is_cpu_domain(genpd) &&
-	    !zalloc_cpumask_var(&genpd->cpus, GFP_KERNEL))
-		return -ENOMEM;
-
-	/* Use only one "off" state if there were no states declared */
-	if (genpd->state_count == 0) {
-		ret = genpd_set_default_power_state(genpd);
-		if (ret) {
-			if (genpd_is_cpu_domain(genpd))
-				free_cpumask_var(genpd->cpus);
-			return ret;
-		}
-	} else if (!gov && genpd->state_count > 1) {
-		pr_warn("%s: no governor for states\n", genpd->name);
-	}
-
-	device_initialize(&genpd->dev);
-	dev_set_name(&genpd->dev, "%s", genpd->name);
-
-	mutex_lock(&gpd_list_lock);
-	list_add(&genpd->gpd_list_node, &gpd_list);
-	mutex_unlock(&gpd_list_lock);
-
-	return 0;
-}
-EXPORT_SYMBOL_GPL(pm_genpd_init);
-
-static int genpd_remove(struct generic_pm_domain *genpd)
-{
-	struct gpd_link *l, *link;
-
-	if (IS_ERR_OR_NULL(genpd))
-		return -EINVAL;
-
-	genpd_lock(genpd);
-
-	if (genpd->has_provider) {
-		genpd_unlock(genpd);
-		pr_err("Provider present, unable to remove %s\n", genpd->name);
-		return -EBUSY;
-	}
-
-	if (!list_empty(&genpd->master_links) || genpd->device_count) {
-		genpd_unlock(genpd);
-		pr_err("%s: unable to remove %s\n", __func__, genpd->name);
-		return -EBUSY;
-	}
-
-	list_for_each_entry_safe(link, l, &genpd->slave_links, slave_node) {
-		list_del(&link->master_node);
-		list_del(&link->slave_node);
-		kfree(link);
-	}
-
-	list_del(&genpd->gpd_list_node);
-	genpd_unlock(genpd);
-	cancel_work_sync(&genpd->power_off_work);
-	if (genpd_is_cpu_domain(genpd))
-		free_cpumask_var(genpd->cpus);
-	if (genpd->free_states)
-		genpd->free_states(genpd->states, genpd->state_count);
-
-	pr_debug("%s: removed %s\n", __func__, genpd->name);
-
-	return 0;
-}
-
-/**
- * pm_genpd_remove - Remove a generic I/O PM domain
- * @genpd: Pointer to PM domain that is to be removed.
- *
- * To remove the PM domain, this function:
- *  - Removes the PM domain as a subdomain to any parent domains,
- *    if it was added.
- *  - Removes the PM domain from the list of registered PM domains.
- *
- * The PM domain will only be removed, if the associated provider has
- * been removed, it is not a parent to any other PM domain and has no
- * devices associated with it.
- */
-int pm_genpd_remove(struct generic_pm_domain *genpd)
-{
-	int ret;
-
-	mutex_lock(&gpd_list_lock);
-	ret = genpd_remove(genpd);
-	mutex_unlock(&gpd_list_lock);
-
-	return ret;
-}
-EXPORT_SYMBOL_GPL(pm_genpd_remove);
-
-#ifdef CONFIG_PM_GENERIC_DOMAINS_OF
-
-/*
- * Device Tree based PM domain providers.
- *
- * The code below implements generic device tree based PM domain providers that
- * bind device tree nodes with generic PM domains registered in the system.
- *
- * Any driver that registers generic PM domains and needs to support binding of
- * devices to these domains is supposed to register a PM domain provider, which
- * maps a PM domain specifier retrieved from the device tree to a PM domain.
- *
- * Two simple mapping functions have been provided for convenience:
- *  - genpd_xlate_simple() for 1:1 device tree node to PM domain mapping.
- *  - genpd_xlate_onecell() for mapping of multiple PM domains per node by
- *    index.
- */
-
-/**
- * struct of_genpd_provider - PM domain provider registration structure
- * @link: Entry in global list of PM domain providers
- * @node: Pointer to device tree node of PM domain provider
- * @xlate: Provider-specific xlate callback mapping a set of specifier cells
- *         into a PM domain.
- * @data: context pointer to be passed into @xlate callback
- */
-struct of_genpd_provider {
-	struct list_head link;
-	struct device_node *node;
-	genpd_xlate_t xlate;
-	void *data;
-};
-
-/* List of registered PM domain providers. */
-static LIST_HEAD(of_genpd_providers);
-/* Mutex to protect the list above. */
-static DEFINE_MUTEX(of_genpd_mutex);
-
-/**
- * genpd_xlate_simple() - Xlate function for direct node-domain mapping
- * @genpdspec: OF phandle args to map into a PM domain
- * @data: xlate function private data - pointer to struct generic_pm_domain
- *
- * This is a generic xlate function that can be used to model PM domains that
- * have their own device tree nodes. The private data of xlate function needs
- * to be a valid pointer to struct generic_pm_domain.
- */
-static struct generic_pm_domain *genpd_xlate_simple(
-					struct of_phandle_args *genpdspec,
-					void *data)
-{
-	return data;
-}
-
-/**
- * genpd_xlate_onecell() - Xlate function using a single index.
- * @genpdspec: OF phandle args to map into a PM domain
- * @data: xlate function private data - pointer to struct genpd_onecell_data
- *
- * This is a generic xlate function that can be used to model simple PM domain
- * controllers that have one device tree node and provide multiple PM domains.
- * A single cell is used as an index into an array of PM domains specified in
- * the genpd_onecell_data struct when registering the provider.
- */
-static struct generic_pm_domain *genpd_xlate_onecell(
-					struct of_phandle_args *genpdspec,
-					void *data)
-{
-	struct genpd_onecell_data *genpd_data = data;
-	unsigned int idx = genpdspec->args[0];
-
-	if (genpdspec->args_count != 1)
-		return ERR_PTR(-EINVAL);
-
-	if (idx >= genpd_data->num_domains) {
-		pr_err("%s: invalid domain index %u\n", __func__, idx);
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (!genpd_data->domains[idx])
-		return ERR_PTR(-ENOENT);
-
-	return genpd_data->domains[idx];
-}
-
-/**
- * genpd_add_provider() - Register a PM domain provider for a node
- * @np: Device node pointer associated with the PM domain provider.
- * @xlate: Callback for decoding PM domain from phandle arguments.
- * @data: Context pointer for @xlate callback.
- */
-static int genpd_add_provider(struct device_node *np, genpd_xlate_t xlate,
-			      void *data)
-{
-	struct of_genpd_provider *cp;
-
-	cp = kzalloc(sizeof(*cp), GFP_KERNEL);
-	if (!cp)
-		return -ENOMEM;
-
-	cp->node = of_node_get(np);
-	cp->data = data;
-	cp->xlate = xlate;
-
-	mutex_lock(&of_genpd_mutex);
-	list_add(&cp->link, &of_genpd_providers);
-	mutex_unlock(&of_genpd_mutex);
-	pr_debug("Added domain provider from %pOF\n", np);
-
-	return 0;
-}
-
-static bool genpd_present(const struct generic_pm_domain *genpd)
-{
-	const struct generic_pm_domain *gpd;
-
-	list_for_each_entry(gpd, &gpd_list, gpd_list_node)
-		if (gpd == genpd)
-			return true;
-	return false;
-}
-
-/**
- * of_genpd_add_provider_simple() - Register a simple PM domain provider
- * @np: Device node pointer associated with the PM domain provider.
- * @genpd: Pointer to PM domain associated with the PM domain provider.
- */
-int of_genpd_add_provider_simple(struct device_node *np,
-				 struct generic_pm_domain *genpd)
-{
-	int ret = -EINVAL;
-
-	if (!np || !genpd)
-		return -EINVAL;
-
-	mutex_lock(&gpd_list_lock);
-
-	if (!genpd_present(genpd))
-		goto unlock;
-
-	genpd->dev.of_node = np;
-
-	/* Parse genpd OPP table */
-	if (genpd->set_performance_state) {
-		ret = dev_pm_opp_of_add_table(&genpd->dev);
-		if (ret) {
-			dev_err(&genpd->dev, "Failed to add OPP table: %d\n",
-				ret);
-			goto unlock;
-		}
-
-		/*
-		 * Save table for faster processing while setting performance
-		 * state.
-		 */
-		genpd->opp_table = dev_pm_opp_get_opp_table(&genpd->dev);
-		WARN_ON(!genpd->opp_table);
-	}
-
-	ret = genpd_add_provider(np, genpd_xlate_simple, genpd);
-	if (ret) {
-		if (genpd->set_performance_state) {
-			dev_pm_opp_put_opp_table(genpd->opp_table);
-			dev_pm_opp_of_remove_table(&genpd->dev);
-		}
-
-		goto unlock;
-	}
-
-	genpd->provider = &np->fwnode;
-	genpd->has_provider = true;
-
-unlock:
-	mutex_unlock(&gpd_list_lock);
-
-	return ret;
-}
-EXPORT_SYMBOL_GPL(of_genpd_add_provider_simple);
-
-/**
- * of_genpd_add_provider_onecell() - Register a onecell PM domain provider
- * @np: Device node pointer associated with the PM domain provider.
- * @data: Pointer to the data associated with the PM domain provider.
- */
-int of_genpd_add_provider_onecell(struct device_node *np,
-				  struct genpd_onecell_data *data)
-{
-	struct generic_pm_domain *genpd;
-	unsigned int i;
-	int ret = -EINVAL;
-
-	if (!np || !data)
-		return -EINVAL;
-
-	mutex_lock(&gpd_list_lock);
-
-	if (!data->xlate)
-		data->xlate = genpd_xlate_onecell;
-
-	for (i = 0; i < data->num_domains; i++) {
-		genpd = data->domains[i];
-
-		if (!genpd)
-			continue;
-		if (!genpd_present(genpd))
-			goto error;
-
-		genpd->dev.of_node = np;
-
-		/* Parse genpd OPP table */
-		if (genpd->set_performance_state) {
-			ret = dev_pm_opp_of_add_table_indexed(&genpd->dev, i);
-			if (ret) {
-				dev_err(&genpd->dev, "Failed to add OPP table for index %d: %d\n",
-					i, ret);
-				goto error;
-			}
-
-			/*
-			 * Save table for faster processing while setting
-			 * performance state.
-			 */
-			genpd->opp_table = dev_pm_opp_get_opp_table_indexed(&genpd->dev, i);
-			WARN_ON(!genpd->opp_table);
-		}
-
-		genpd->provider = &np->fwnode;
-		genpd->has_provider = true;
-	}
-
-	ret = genpd_add_provider(np, data->xlate, data);
-	if (ret < 0)
-		goto error;
-
-	mutex_unlock(&gpd_list_lock);
-
-	return 0;
-
-error:
-	while (i--) {
-		genpd = data->domains[i];
-
-		if (!genpd)
-			continue;
-
-		genpd->provider = NULL;
-		genpd->has_provider = false;
-
-		if (genpd->set_performance_state) {
-			dev_pm_opp_put_opp_table(genpd->opp_table);
-			dev_pm_opp_of_remove_table(&genpd->dev);
-		}
-	}
-
-	mutex_unlock(&gpd_list_lock);
-
-	return ret;
-}
-EXPORT_SYMBOL_GPL(of_genpd_add_provider_onecell);
-
-/**
- * of_genpd_del_provider() - Remove a previously registered PM domain provider
- * @np: Device node pointer associated with the PM domain provider
- */
-void of_genpd_del_provider(struct device_node *np)
-{
-	struct of_genpd_provider *cp, *tmp;
-	struct generic_pm_domain *gpd;
-
-	mutex_lock(&gpd_list_lock);
-	mutex_lock(&of_genpd_mutex);
-	list_for_each_entry_safe(cp, tmp, &of_genpd_providers, link) {
-		if (cp->node == np) {
-			/*
-			 * For each PM domain associated with the
-			 * provider, set the 'has_provider' to false
-			 * so that the PM domain can be safely removed.
-			 */
-			list_for_each_entry(gpd, &gpd_list, gpd_list_node) {
-				if (gpd->provider == &np->fwnode) {
-					gpd->has_provider = false;
-
-					if (!gpd->set_performance_state)
-						continue;
-
-					dev_pm_opp_put_opp_table(gpd->opp_table);
-					dev_pm_opp_of_remove_table(&gpd->dev);
-				}
-			}
-
-			list_del(&cp->link);
-			of_node_put(cp->node);
-			kfree(cp);
-			break;
-		}
-	}
-	mutex_unlock(&of_genpd_mutex);
-	mutex_unlock(&gpd_list_lock);
-}
-EXPORT_SYMBOL_GPL(of_genpd_del_provider);
-
-/**
- * genpd_get_from_provider() - Look-up PM domain
- * @genpdspec: OF phandle args to use for look-up
- *
- * Looks for a PM domain provider under the node specified by @genpdspec and if
- * found, uses xlate function of the provider to map phandle args to a PM
- * domain.
- *
- * Returns a valid pointer to struct generic_pm_domain on success or ERR_PTR()
- * on failure.
- */
-static struct generic_pm_domain *genpd_get_from_provider(
-					struct of_phandle_args *genpdspec)
-{
-	struct generic_pm_domain *genpd = ERR_PTR(-ENOENT);
-	struct of_genpd_provider *provider;
-
-	if (!genpdspec)
-		return ERR_PTR(-EINVAL);
-
-	mutex_lock(&of_genpd_mutex);
-
-	/* Check if we have such a provider in our array */
-	list_for_each_entry(provider, &of_genpd_providers, link) {
-		if (provider->node == genpdspec->np)
-			genpd = provider->xlate(genpdspec, provider->data);
-		if (!IS_ERR(genpd))
-			break;
-	}
-
-	mutex_unlock(&of_genpd_mutex);
-
-	return genpd;
-}
-
-/**
- * of_genpd_add_device() - Add a device to an I/O PM domain
- * @genpdspec: OF phandle args to use for look-up PM domain
- * @dev: Device to be added.
- *
- * Looks-up an I/O PM domain based upon phandle args provided and adds
- * the device to the PM domain. Returns a negative error code on failure.
- */
-int of_genpd_add_device(struct of_phandle_args *genpdspec, struct device *dev)
-{
-	struct generic_pm_domain *genpd;
-	int ret;
-
-	mutex_lock(&gpd_list_lock);
-
-	genpd = genpd_get_from_provider(genpdspec);
-	if (IS_ERR(genpd)) {
-		ret = PTR_ERR(genpd);
-		goto out;
-	}
-
-	ret = genpd_add_device(genpd, dev, dev);
-
-out:
-	mutex_unlock(&gpd_list_lock);
-
-	return ret;
-}
-EXPORT_SYMBOL_GPL(of_genpd_add_device);
-
-/**
- * of_genpd_add_subdomain - Add a subdomain to an I/O PM domain.
- * @parent_spec: OF phandle args to use for parent PM domain look-up
- * @subdomain_spec: OF phandle args to use for subdomain look-up
- *
- * Looks-up a parent PM domain and subdomain based upon phandle args
- * provided and adds the subdomain to the parent PM domain. Returns a
- * negative error code on failure.
- */
-int of_genpd_add_subdomain(struct of_phandle_args *parent_spec,
-			   struct of_phandle_args *subdomain_spec)
-{
-	struct generic_pm_domain *parent, *subdomain;
-	int ret;
-
-	mutex_lock(&gpd_list_lock);
-
-	parent = genpd_get_from_provider(parent_spec);
-	if (IS_ERR(parent)) {
-		ret = PTR_ERR(parent);
-		goto out;
-	}
-
-	subdomain = genpd_get_from_provider(subdomain_spec);
-	if (IS_ERR(subdomain)) {
-		ret = PTR_ERR(subdomain);
-		goto out;
-	}
-
-	ret = genpd_add_subdomain(parent, subdomain);
-
-out:
-	mutex_unlock(&gpd_list_lock);
-
-	return ret;
-}
-EXPORT_SYMBOL_GPL(of_genpd_add_subdomain);
-
-/**
- * of_genpd_remove_subdomain - Remove a subdomain from an I/O PM domain.
- * @parent_spec: OF phandle args to use for parent PM domain look-up
- * @subdomain_spec: OF phandle args to use for subdomain look-up
- *
- * Looks-up a parent PM domain and subdomain based upon phandle args
- * provided and removes the subdomain from the parent PM domain. Returns a
- * negative error code on failure.
- */
-int of_genpd_remove_subdomain(struct of_phandle_args *parent_spec,
-			      struct of_phandle_args *subdomain_spec)
-{
-	struct generic_pm_domain *parent, *subdomain;
-	int ret;
-
-	mutex_lock(&gpd_list_lock);
-
-	parent = genpd_get_from_provider(parent_spec);
-	if (IS_ERR(parent)) {
-		ret = PTR_ERR(parent);
-		goto out;
-	}
-
-	subdomain = genpd_get_from_provider(subdomain_spec);
-	if (IS_ERR(subdomain)) {
-		ret = PTR_ERR(subdomain);
-		goto out;
-	}
-
-	ret = pm_genpd_remove_subdomain(parent, subdomain);
-
-out:
-	mutex_unlock(&gpd_list_lock);
-
-	return ret;
-}
-EXPORT_SYMBOL_GPL(of_genpd_remove_subdomain);
-
-/**
- * of_genpd_remove_last - Remove the last PM domain registered for a provider
- * @provider: Pointer to device structure associated with provider
- *
- * Find the last PM domain that was added by a particular provider and
- * remove this PM domain from the list of PM domains. The provider is
- * identified by the 'provider' device structure that is passed. The PM
- * domain will only be removed, if the provider associated with domain
- * has been removed.
- *
- * Returns a valid pointer to struct generic_pm_domain on success or
- * ERR_PTR() on failure.
- */
-struct generic_pm_domain *of_genpd_remove_last(struct device_node *np)
-{
-	struct generic_pm_domain *gpd, *tmp, *genpd = ERR_PTR(-ENOENT);
-	int ret;
-
-	if (IS_ERR_OR_NULL(np))
-		return ERR_PTR(-EINVAL);
-
-	mutex_lock(&gpd_list_lock);
-	list_for_each_entry_safe(gpd, tmp, &gpd_list, gpd_list_node) {
-		if (gpd->provider == &np->fwnode) {
-			ret = genpd_remove(gpd);
-			genpd = ret ? ERR_PTR(ret) : gpd;
-			break;
-		}
-	}
-	mutex_unlock(&gpd_list_lock);
-
-	return genpd;
-}
-EXPORT_SYMBOL_GPL(of_genpd_remove_last);
-
-static void genpd_release_dev(struct device *dev)
-{
-	of_node_put(dev->of_node);
-	kfree(dev);
-}
-
-static struct bus_type genpd_bus_type = {
-	.name		= "genpd",
-};
-
-/**
- * genpd_dev_pm_detach - Detach a device from its PM domain.
- * @dev: Device to detach.
- * @power_off: Currently not used
- *
- * Try to locate a corresponding generic PM domain, which the device was
- * attached to previously. If such is found, the device is detached from it.
- */
-static void genpd_dev_pm_detach(struct device *dev, bool power_off)
-{
-	struct generic_pm_domain *pd;
-	unsigned int i;
-	int ret = 0;
-
-	pd = dev_to_genpd(dev);
-	if (IS_ERR(pd))
-		return;
-
-	dev_dbg(dev, "removing from PM domain %s\n", pd->name);
-
-	for (i = 1; i < GENPD_RETRY_MAX_MS; i <<= 1) {
-		ret = genpd_remove_device(pd, dev);
-		if (ret != -EAGAIN)
-			break;
-
-		mdelay(i);
-		cond_resched();
-	}
-
-	if (ret < 0) {
-		dev_err(dev, "failed to remove from PM domain %s: %d",
-			pd->name, ret);
-		return;
-	}
-
-	/* Check if PM domain can be powered off after removing this device. */
-	genpd_queue_power_off_work(pd);
-
-	/* Unregister the device if it was created by genpd. */
-	if (dev->bus == &genpd_bus_type)
-		device_unregister(dev);
-}
-
-static void genpd_dev_pm_sync(struct device *dev)
-{
-	struct generic_pm_domain *pd;
-
-	pd = dev_to_genpd(dev);
-	if (IS_ERR(pd))
-		return;
-
-	genpd_queue_power_off_work(pd);
-}
-
-static int __genpd_dev_pm_attach(struct device *dev, struct device *base_dev,
-				 unsigned int index, bool power_on)
-{
-	struct of_phandle_args pd_args;
-	struct generic_pm_domain *pd;
-	int ret;
-
-	ret = of_parse_phandle_with_args(dev->of_node, "power-domains",
-				"#power-domain-cells", index, &pd_args);
-	if (ret < 0)
-		return ret;
-
-	mutex_lock(&gpd_list_lock);
-	pd = genpd_get_from_provider(&pd_args);
-	of_node_put(pd_args.np);
-	if (IS_ERR(pd)) {
-		mutex_unlock(&gpd_list_lock);
-		dev_dbg(dev, "%s() failed to find PM domain: %ld\n",
-			__func__, PTR_ERR(pd));
-		return driver_deferred_probe_check_state(base_dev);
-	}
-
-	dev_dbg(dev, "adding to PM domain %s\n", pd->name);
-
-	ret = genpd_add_device(pd, dev, base_dev);
-	mutex_unlock(&gpd_list_lock);
-
-	if (ret < 0) {
-		if (ret != -EPROBE_DEFER)
-			dev_err(dev, "failed to add to PM domain %s: %d",
-				pd->name, ret);
-		return ret;
-	}
-
-	dev->pm_domain->detach = genpd_dev_pm_detach;
-	dev->pm_domain->sync = genpd_dev_pm_sync;
-
-	if (power_on) {
-		genpd_lock(pd);
-		ret = genpd_power_on(pd, 0);
-		genpd_unlock(pd);
-	}
-
-	if (ret)
-		genpd_remove_device(pd, dev);
-
-	return ret ? -EPROBE_DEFER : 1;
-}
-
-/**
- * genpd_dev_pm_attach - Attach a device to its PM domain using DT.
- * @dev: Device to attach.
- *
- * Parse device's OF node to find a PM domain specifier. If such is found,
- * attaches the device to retrieved pm_domain ops.
- *
- * Returns 1 on successfully attached PM domain, 0 when the device don't need a
- * PM domain or when multiple power-domains exists for it, else a negative error
- * code. Note that if a power-domain exists for the device, but it cannot be
- * found or turned on, then return -EPROBE_DEFER to ensure that the device is
- * not probed and to re-try again later.
- */
-int genpd_dev_pm_attach(struct device *dev)
-{
-	if (!dev->of_node)
-		return 0;
-
-	/*
-	 * Devices with multiple PM domains must be attached separately, as we
-	 * can only attach one PM domain per device.
-	 */
-	if (of_count_phandle_with_args(dev->of_node, "power-domains",
-				       "#power-domain-cells") != 1)
-		return 0;
-
-	return __genpd_dev_pm_attach(dev, dev, 0, true);
-}
-EXPORT_SYMBOL_GPL(genpd_dev_pm_attach);
-
-/**
- * genpd_dev_pm_attach_by_id - Associate a device with one of its PM domains.
- * @dev: The device used to lookup the PM domain.
- * @index: The index of the PM domain.
- *
- * Parse device's OF node to find a PM domain specifier at the provided @index.
- * If such is found, creates a virtual device and attaches it to the retrieved
- * pm_domain ops. To deal with detaching of the virtual device, the ->detach()
- * callback in the struct dev_pm_domain are assigned to genpd_dev_pm_detach().
- *
- * Returns the created virtual device if successfully attached PM domain, NULL
- * when the device don't need a PM domain, else an ERR_PTR() in case of
- * failures. If a power-domain exists for the device, but cannot be found or
- * turned on, then ERR_PTR(-EPROBE_DEFER) is returned to ensure that the device
- * is not probed and to re-try again later.
- */
-struct device *genpd_dev_pm_attach_by_id(struct device *dev,
-					 unsigned int index)
-{
-	struct device *virt_dev;
-	int num_domains;
-	int ret;
-
-	if (!dev->of_node)
-		return NULL;
-
-	/* Verify that the index is within a valid range. */
-	num_domains = of_count_phandle_with_args(dev->of_node, "power-domains",
-						 "#power-domain-cells");
-	if (index >= num_domains)
-		return NULL;
-
-	/* Allocate and register device on the genpd bus. */
-	virt_dev = kzalloc(sizeof(*virt_dev), GFP_KERNEL);
-	if (!virt_dev)
-		return ERR_PTR(-ENOMEM);
-
-	dev_set_name(virt_dev, "genpd:%u:%s", index, dev_name(dev));
-	virt_dev->bus = &genpd_bus_type;
-	virt_dev->release = genpd_release_dev;
-	virt_dev->of_node = of_node_get(dev->of_node);
-
-	ret = device_register(virt_dev);
-	if (ret) {
-		put_device(virt_dev);
-		return ERR_PTR(ret);
-	}
-
-	/* Try to attach the device to the PM domain at the specified index. */
-	ret = __genpd_dev_pm_attach(virt_dev, dev, index, false);
-	if (ret < 1) {
-		device_unregister(virt_dev);
-		return ret ? ERR_PTR(ret) : NULL;
-	}
-
-	pm_runtime_enable(virt_dev);
-	genpd_queue_power_off_work(dev_to_genpd(virt_dev));
-
-	return virt_dev;
-}
-EXPORT_SYMBOL_GPL(genpd_dev_pm_attach_by_id);
-
-/**
- * genpd_dev_pm_attach_by_name - Associate a device with one of its PM domains.
- * @dev: The device used to lookup the PM domain.
- * @name: The name of the PM domain.
- *
- * Parse device's OF node to find a PM domain specifier using the
- * power-domain-names DT property. For further description see
- * genpd_dev_pm_attach_by_id().
- */
-struct device *genpd_dev_pm_attach_by_name(struct device *dev, const char *name)
-{
-	int index;
-
-	if (!dev->of_node)
-		return NULL;
-
-	index = of_property_match_string(dev->of_node, "power-domain-names",
-					 name);
-	if (index < 0)
-		return NULL;
-
-	return genpd_dev_pm_attach_by_id(dev, index);
-}
-
-static const struct of_device_id idle_state_match[] = {
-	{ .compatible = "domain-idle-state", },
-	{ }
-};
-
-static int genpd_parse_state(struct genpd_power_state *genpd_state,
-				    struct device_node *state_node)
-{
-	int err;
-	u32 residency;
-	u32 entry_latency, exit_latency;
-
-	err = of_property_read_u32(state_node, "entry-latency-us",
-						&entry_latency);
-	if (err) {
-		pr_debug(" * %pOF missing entry-latency-us property\n",
-			 state_node);
-		return -EINVAL;
-	}
-
-	err = of_property_read_u32(state_node, "exit-latency-us",
-						&exit_latency);
-	if (err) {
-		pr_debug(" * %pOF missing exit-latency-us property\n",
-			 state_node);
-		return -EINVAL;
-	}
-
-	err = of_property_read_u32(state_node, "min-residency-us", &residency);
-	if (!err)
-		genpd_state->residency_ns = 1000 * residency;
-
-	genpd_state->power_on_latency_ns = 1000 * exit_latency;
-	genpd_state->power_off_latency_ns = 1000 * entry_latency;
-	genpd_state->fwnode = &state_node->fwnode;
-
-	return 0;
-}
-
-static int genpd_iterate_idle_states(struct device_node *dn,
-				     struct genpd_power_state *states)
-{
-	int ret;
-	struct of_phandle_iterator it;
-	struct device_node *np;
-	int i = 0;
-
-	ret = of_count_phandle_with_args(dn, "domain-idle-states", NULL);
-	if (ret <= 0)
-		return ret == -ENOENT ? 0 : ret;
-
-	/* Loop over the phandles until all the requested entry is found */
-	of_for_each_phandle(&it, ret, dn, "domain-idle-states", NULL, 0) {
-		np = it.node;
-		if (!of_match_node(idle_state_match, np))
-			continue;
-		if (states) {
-			ret = genpd_parse_state(&states[i], np);
-			if (ret) {
-				pr_err("Parsing idle state node %pOF failed with err %d\n",
-				       np, ret);
-				of_node_put(np);
-				return ret;
-			}
-		}
-		i++;
-	}
-
-	return i;
-}
-
-/**
- * of_genpd_parse_idle_states: Return array of idle states for the genpd.
- *
- * @dn: The genpd device node
- * @states: The pointer to which the state array will be saved.
- * @n: The count of elements in the array returned from this function.
- *
- * Returns the device states parsed from the OF node. The memory for the states
- * is allocated by this function and is the responsibility of the caller to
- * free the memory after use. If any or zero compatible domain idle states is
- * found it returns 0 and in case of errors, a negative error code is returned.
- */
-int of_genpd_parse_idle_states(struct device_node *dn,
-			struct genpd_power_state **states, int *n)
-{
-	struct genpd_power_state *st;
-	int ret;
-
-	ret = genpd_iterate_idle_states(dn, NULL);
-	if (ret < 0)
-		return ret;
-
-	if (!ret) {
-		*states = NULL;
-		*n = 0;
-		return 0;
-	}
-
-	st = kcalloc(ret, sizeof(*st), GFP_KERNEL);
-	if (!st)
-		return -ENOMEM;
-
-	ret = genpd_iterate_idle_states(dn, st);
-	if (ret <= 0) {
-		kfree(st);
-		return ret < 0 ? ret : -EINVAL;
-	}
-
-	*states = st;
-	*n = ret;
-
-	return 0;
-}
-EXPORT_SYMBOL_GPL(of_genpd_parse_idle_states);
-
-/**
- * pm_genpd_opp_to_performance_state - Gets performance state of the genpd from its OPP node.
- *
- * @genpd_dev: Genpd's device for which the performance-state needs to be found.
- * @opp: struct dev_pm_opp of the OPP for which we need to find performance
- *	state.
- *
- * Returns performance state encoded in the OPP of the genpd. This calls
- * platform specific genpd->opp_to_performance_state() callback to translate
- * power domain OPP to performance state.
- *
- * Returns performance state on success and 0 on failure.
- */
-unsigned int pm_genpd_opp_to_performance_state(struct device *genpd_dev,
-					       struct dev_pm_opp *opp)
-{
-	struct generic_pm_domain *genpd = NULL;
-	int state;
-
-	genpd = container_of(genpd_dev, struct generic_pm_domain, dev);
-
-	if (unlikely(!genpd->opp_to_performance_state))
-		return 0;
-
-	genpd_lock(genpd);
-	state = genpd->opp_to_performance_state(genpd, opp);
-	genpd_unlock(genpd);
-
-	return state;
-}
-EXPORT_SYMBOL_GPL(pm_genpd_opp_to_performance_state);
-
-static int __init genpd_bus_init(void)
-{
-	return bus_register(&genpd_bus_type);
-}
-core_initcall(genpd_bus_init);
-
-#endif /* CONFIG_PM_GENERIC_DOMAINS_OF */
-
-
-/***        debugfs support        ***/
-
-#ifdef CONFIG_DEBUG_FS
-#include <linux/pm.h>
-#include <linux/device.h>
-#include <linux/debugfs.h>
-#include <linux/seq_file.h>
-#include <linux/init.h>
-#include <linux/kobject.h>
-static struct dentry *genpd_debugfs_dir;
-
-/*
- * TODO: This function is a slightly modified version of rtpm_status_show
- * from sysfs.c, so generalize it.
- */
-static void rtpm_status_str(struct seq_file *s, struct device *dev)
-{
-	static const char * const status_lookup[] = {
-		[RPM_ACTIVE] = "active",
-		[RPM_RESUMING] = "resuming",
-		[RPM_SUSPENDED] = "suspended",
-		[RPM_SUSPENDING] = "suspending"
-	};
-	const char *p = "";
-
-	if (dev->power.runtime_error)
-		p = "error";
-	else if (dev->power.disable_depth)
-		p = "unsupported";
-	else if (dev->power.runtime_status < ARRAY_SIZE(status_lookup))
-		p = status_lookup[dev->power.runtime_status];
-	else
-		WARN_ON(1);
-
-	seq_puts(s, p);
-}
-
-static int genpd_summary_one(struct seq_file *s,
-			struct generic_pm_domain *genpd)
-{
-	static const char * const status_lookup[] = {
-		[GPD_STATE_ACTIVE] = "on",
-		[GPD_STATE_POWER_OFF] = "off"
-	};
-	struct pm_domain_data *pm_data;
-	const char *kobj_path;
-	struct gpd_link *link;
-	char state[16];
-	int ret;
-
-	ret = genpd_lock_interruptible(genpd);
-	if (ret)
-		return -ERESTARTSYS;
-
-	if (WARN_ON(genpd->status >= ARRAY_SIZE(status_lookup)))
-		goto exit;
-	if (!genpd_status_on(genpd))
-		snprintf(state, sizeof(state), "%s-%u",
-			 status_lookup[genpd->status], genpd->state_idx);
-	else
-		snprintf(state, sizeof(state), "%s",
-			 status_lookup[genpd->status]);
-	seq_printf(s, "%-30s  %-15s ", genpd->name, state);
-
-	/*
-	 * Modifications on the list require holding locks on both
-	 * master and slave, so we are safe.
-	 * Also genpd->name is immutable.
-	 */
-	list_for_each_entry(link, &genpd->master_links, master_node) {
-		seq_printf(s, "%s", link->slave->name);
-		if (!list_is_last(&link->master_node, &genpd->master_links))
-			seq_puts(s, ", ");
-	}
-
-	list_for_each_entry(pm_data, &genpd->dev_list, list_node) {
-		kobj_path = kobject_get_path(&pm_data->dev->kobj,
-				genpd_is_irq_safe(genpd) ?
-				GFP_ATOMIC : GFP_KERNEL);
-		if (kobj_path == NULL)
-			continue;
-
-		seq_printf(s, "\n    %-50s  ", kobj_path);
-		rtpm_status_str(s, pm_data->dev);
-		kfree(kobj_path);
-	}
-
-	seq_puts(s, "\n");
-exit:
-	genpd_unlock(genpd);
-
-	return 0;
-}
-
-static int summary_show(struct seq_file *s, void *data)
-{
-	struct generic_pm_domain *genpd;
-	int ret = 0;
-
-	seq_puts(s, "domain                          status          slaves\n");
-	seq_puts(s, "    /device                                             runtime status\n");
-	seq_puts(s, "----------------------------------------------------------------------\n");
-
-	ret = mutex_lock_interruptible(&gpd_list_lock);
-	if (ret)
-		return -ERESTARTSYS;
-
-	list_for_each_entry(genpd, &gpd_list, gpd_list_node) {
-		ret = genpd_summary_one(s, genpd);
-		if (ret)
-			break;
-	}
-	mutex_unlock(&gpd_list_lock);
-
-	return ret;
-}
-
-static int status_show(struct seq_file *s, void *data)
-{
-	static const char * const status_lookup[] = {
-		[GPD_STATE_ACTIVE] = "on",
-		[GPD_STATE_POWER_OFF] = "off"
-	};
-
-	struct generic_pm_domain *genpd = s->private;
-	int ret = 0;
-
-	ret = genpd_lock_interruptible(genpd);
-	if (ret)
-		return -ERESTARTSYS;
-
-	if (WARN_ON_ONCE(genpd->status >= ARRAY_SIZE(status_lookup)))
-		goto exit;
-
-	if (genpd->status == GPD_STATE_POWER_OFF)
-		seq_printf(s, "%s-%u\n", status_lookup[genpd->status],
-			genpd->state_idx);
-	else
-		seq_printf(s, "%s\n", status_lookup[genpd->status]);
-exit:
-	genpd_unlock(genpd);
-	return ret;
-}
-
-static int sub_domains_show(struct seq_file *s, void *data)
-{
-	struct generic_pm_domain *genpd = s->private;
-	struct gpd_link *link;
-	int ret = 0;
-
-	ret = genpd_lock_interruptible(genpd);
-	if (ret)
-		return -ERESTARTSYS;
-
-	list_for_each_entry(link, &genpd->master_links, master_node)
-		seq_printf(s, "%s\n", link->slave->name);
-
-	genpd_unlock(genpd);
-	return ret;
-}
-
-static int idle_states_show(struct seq_file *s, void *data)
-{
-	struct generic_pm_domain *genpd = s->private;
-	unsigned int i;
-	int ret = 0;
-
-	ret = genpd_lock_interruptible(genpd);
-	if (ret)
-		return -ERESTARTSYS;
-
-	seq_puts(s, "State          Time Spent(ms)\n");
-
-	for (i = 0; i < genpd->state_count; i++) {
-		ktime_t delta = 0;
-		s64 msecs;
-
-		if ((genpd->status == GPD_STATE_POWER_OFF) &&
-				(genpd->state_idx == i))
-			delta = ktime_sub(ktime_get(), genpd->accounting_time);
-
-		msecs = ktime_to_ms(
-			ktime_add(genpd->states[i].idle_time, delta));
-		seq_printf(s, "S%-13i %lld\n", i, msecs);
-	}
-
-	genpd_unlock(genpd);
-	return ret;
-}
-
-static int active_time_show(struct seq_file *s, void *data)
-{
-	struct generic_pm_domain *genpd = s->private;
-	ktime_t delta = 0;
-	int ret = 0;
-
-	ret = genpd_lock_interruptible(genpd);
-	if (ret)
-		return -ERESTARTSYS;
-
-	if (genpd->status == GPD_STATE_ACTIVE)
-		delta = ktime_sub(ktime_get(), genpd->accounting_time);
-
-	seq_printf(s, "%lld ms\n", ktime_to_ms(
-				ktime_add(genpd->on_time, delta)));
-
-	genpd_unlock(genpd);
-	return ret;
-}
-
-static int total_idle_time_show(struct seq_file *s, void *data)
-{
-	struct generic_pm_domain *genpd = s->private;
-	ktime_t delta = 0, total = 0;
-	unsigned int i;
-	int ret = 0;
-
-	ret = genpd_lock_interruptible(genpd);
-	if (ret)
-		return -ERESTARTSYS;
-
-	for (i = 0; i < genpd->state_count; i++) {
-
-		if ((genpd->status == GPD_STATE_POWER_OFF) &&
-				(genpd->state_idx == i))
-			delta = ktime_sub(ktime_get(), genpd->accounting_time);
-
-		total = ktime_add(total, genpd->states[i].idle_time);
-	}
-	total = ktime_add(total, delta);
-
-	seq_printf(s, "%lld ms\n", ktime_to_ms(total));
-
-	genpd_unlock(genpd);
-	return ret;
-}
-
-
-static int devices_show(struct seq_file *s, void *data)
-{
-	struct generic_pm_domain *genpd = s->private;
-	struct pm_domain_data *pm_data;
-	const char *kobj_path;
-	int ret = 0;
-
-	ret = genpd_lock_interruptible(genpd);
-	if (ret)
-		return -ERESTARTSYS;
-
-	list_for_each_entry(pm_data, &genpd->dev_list, list_node) {
-		kobj_path = kobject_get_path(&pm_data->dev->kobj,
-				genpd_is_irq_safe(genpd) ?
-				GFP_ATOMIC : GFP_KERNEL);
-		if (kobj_path == NULL)
-			continue;
-
-		seq_printf(s, "%s\n", kobj_path);
-		kfree(kobj_path);
-	}
-
-	genpd_unlock(genpd);
-	return ret;
-}
-
-static int perf_state_show(struct seq_file *s, void *data)
-{
-	struct generic_pm_domain *genpd = s->private;
-
-	if (genpd_lock_interruptible(genpd))
-		return -ERESTARTSYS;
-
-	seq_printf(s, "%u\n", genpd->performance_state);
-
-	genpd_unlock(genpd);
-	return 0;
-}
-
-DEFINE_SHOW_ATTRIBUTE(summary);
-DEFINE_SHOW_ATTRIBUTE(status);
-DEFINE_SHOW_ATTRIBUTE(sub_domains);
-DEFINE_SHOW_ATTRIBUTE(idle_states);
-DEFINE_SHOW_ATTRIBUTE(active_time);
-DEFINE_SHOW_ATTRIBUTE(total_idle_time);
-DEFINE_SHOW_ATTRIBUTE(devices);
-DEFINE_SHOW_ATTRIBUTE(perf_state);
-
-static int __init genpd_debug_init(void)
-{
-	struct dentry *d;
-	struct generic_pm_domain *genpd;
-
-	genpd_debugfs_dir = debugfs_create_dir("pm_genpd", NULL);
-
-	debugfs_create_file("pm_genpd_summary", S_IRUGO, genpd_debugfs_dir,
-			    NULL, &summary_fops);
-
-	list_for_each_entry(genpd, &gpd_list, gpd_list_node) {
-		d = debugfs_create_dir(genpd->name, genpd_debugfs_dir);
-
-		debugfs_create_file("current_state", 0444,
-				d, genpd, &status_fops);
-		debugfs_create_file("sub_domains", 0444,
-				d, genpd, &sub_domains_fops);
-		debugfs_create_file("idle_states", 0444,
-				d, genpd, &idle_states_fops);
-		debugfs_create_file("active_time", 0444,
-				d, genpd, &active_time_fops);
-		debugfs_create_file("total_idle_time", 0444,
-				d, genpd, &total_idle_time_fops);
-		debugfs_create_file("devices", 0444,
-				d, genpd, &devices_fops);
-		if (genpd->set_performance_state)
-			debugfs_create_file("perf_state", 0444,
-					    d, genpd, &perf_state_fops);
-	}
-
-	return 0;
-}
-late_initcall(genpd_debug_init);
-
-static void __exit genpd_debug_exit(void)
-{
-	debugfs_remove_recursive(genpd_debugfs_dir);
-}
-__exitcall(genpd_debug_exit);
-#endif /* CONFIG_DEBUG_FS */
diff --git a/drivers/base/power/domain_governor.c b/drivers/base/power/domain_governor.c
deleted file mode 100644
index daa8c7689f7e..000000000000
--- a/drivers/base/power/domain_governor.c
+++ /dev/null
@@ -1,321 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * drivers/base/power/domain_governor.c - Governors for device PM domains.
- *
- * Copyright (C) 2011 Rafael J. Wysocki <rjw@sisk.pl>, Renesas Electronics Corp.
- */
-#include <linux/kernel.h>
-#include <linux/pm_domain.h>
-#include <linux/pm_qos.h>
-#include <linux/hrtimer.h>
-#include <linux/cpuidle.h>
-#include <linux/cpumask.h>
-#include <linux/ktime.h>
-
-static int dev_update_qos_constraint(struct device *dev, void *data)
-{
-	s64 *constraint_ns_p = data;
-	s64 constraint_ns;
-
-	if (dev->power.subsys_data && dev->power.subsys_data->domain_data) {
-		/*
-		 * Only take suspend-time QoS constraints of devices into
-		 * account, because constraints updated after the device has
-		 * been suspended are not guaranteed to be taken into account
-		 * anyway.  In order for them to take effect, the device has to
-		 * be resumed and suspended again.
-		 */
-		constraint_ns = dev_gpd_data(dev)->td.effective_constraint_ns;
-	} else {
-		/*
-		 * The child is not in a domain and there's no info on its
-		 * suspend/resume latencies, so assume them to be negligible and
-		 * take its current PM QoS constraint (that's the only thing
-		 * known at this point anyway).
-		 */
-		constraint_ns = dev_pm_qos_read_value(dev, DEV_PM_QOS_RESUME_LATENCY);
-		constraint_ns *= NSEC_PER_USEC;
-	}
-
-	if (constraint_ns < *constraint_ns_p)
-		*constraint_ns_p = constraint_ns;
-
-	return 0;
-}
-
-/**
- * default_suspend_ok - Default PM domain governor routine to suspend devices.
- * @dev: Device to check.
- */
-static bool default_suspend_ok(struct device *dev)
-{
-	struct gpd_timing_data *td = &dev_gpd_data(dev)->td;
-	unsigned long flags;
-	s64 constraint_ns;
-
-	dev_dbg(dev, "%s()\n", __func__);
-
-	spin_lock_irqsave(&dev->power.lock, flags);
-
-	if (!td->constraint_changed) {
-		bool ret = td->cached_suspend_ok;
-
-		spin_unlock_irqrestore(&dev->power.lock, flags);
-		return ret;
-	}
-	td->constraint_changed = false;
-	td->cached_suspend_ok = false;
-	td->effective_constraint_ns = 0;
-	constraint_ns = __dev_pm_qos_resume_latency(dev);
-
-	spin_unlock_irqrestore(&dev->power.lock, flags);
-
-	if (constraint_ns == 0)
-		return false;
-
-	constraint_ns *= NSEC_PER_USEC;
-	/*
-	 * We can walk the children without any additional locking, because
-	 * they all have been suspended at this point and their
-	 * effective_constraint_ns fields won't be modified in parallel with us.
-	 */
-	if (!dev->power.ignore_children)
-		device_for_each_child(dev, &constraint_ns,
-				      dev_update_qos_constraint);
-
-	if (constraint_ns == PM_QOS_RESUME_LATENCY_NO_CONSTRAINT_NS) {
-		/* "No restriction", so the device is allowed to suspend. */
-		td->effective_constraint_ns = PM_QOS_RESUME_LATENCY_NO_CONSTRAINT_NS;
-		td->cached_suspend_ok = true;
-	} else if (constraint_ns == 0) {
-		/*
-		 * This triggers if one of the children that don't belong to a
-		 * domain has a zero PM QoS constraint and it's better not to
-		 * suspend then.  effective_constraint_ns is zero already and
-		 * cached_suspend_ok is false, so bail out.
-		 */
-		return false;
-	} else {
-		constraint_ns -= td->suspend_latency_ns +
-				td->resume_latency_ns;
-		/*
-		 * effective_constraint_ns is zero already and cached_suspend_ok
-		 * is false, so if the computed value is not positive, return
-		 * right away.
-		 */
-		if (constraint_ns <= 0)
-			return false;
-
-		td->effective_constraint_ns = constraint_ns;
-		td->cached_suspend_ok = true;
-	}
-
-	/*
-	 * The children have been suspended already, so we don't need to take
-	 * their suspend latencies into account here.
-	 */
-	return td->cached_suspend_ok;
-}
-
-static bool __default_power_down_ok(struct dev_pm_domain *pd,
-				     unsigned int state)
-{
-	struct generic_pm_domain *genpd = pd_to_genpd(pd);
-	struct gpd_link *link;
-	struct pm_domain_data *pdd;
-	s64 min_off_time_ns;
-	s64 off_on_time_ns;
-
-	off_on_time_ns = genpd->states[state].power_off_latency_ns +
-		genpd->states[state].power_on_latency_ns;
-
-	min_off_time_ns = -1;
-	/*
-	 * Check if subdomains can be off for enough time.
-	 *
-	 * All subdomains have been powered off already at this point.
-	 */
-	list_for_each_entry(link, &genpd->master_links, master_node) {
-		struct generic_pm_domain *sd = link->slave;
-		s64 sd_max_off_ns = sd->max_off_time_ns;
-
-		if (sd_max_off_ns < 0)
-			continue;
-
-		/*
-		 * Check if the subdomain is allowed to be off long enough for
-		 * the current domain to turn off and on (that's how much time
-		 * it will have to wait worst case).
-		 */
-		if (sd_max_off_ns <= off_on_time_ns)
-			return false;
-
-		if (min_off_time_ns > sd_max_off_ns || min_off_time_ns < 0)
-			min_off_time_ns = sd_max_off_ns;
-	}
-
-	/*
-	 * Check if the devices in the domain can be off enough time.
-	 */
-	list_for_each_entry(pdd, &genpd->dev_list, list_node) {
-		struct gpd_timing_data *td;
-		s64 constraint_ns;
-
-		/*
-		 * Check if the device is allowed to be off long enough for the
-		 * domain to turn off and on (that's how much time it will
-		 * have to wait worst case).
-		 */
-		td = &to_gpd_data(pdd)->td;
-		constraint_ns = td->effective_constraint_ns;
-		/*
-		 * Zero means "no suspend at all" and this runs only when all
-		 * devices in the domain are suspended, so it must be positive.
-		 */
-		if (constraint_ns == PM_QOS_RESUME_LATENCY_NO_CONSTRAINT_NS)
-			continue;
-
-		if (constraint_ns <= off_on_time_ns)
-			return false;
-
-		if (min_off_time_ns > constraint_ns || min_off_time_ns < 0)
-			min_off_time_ns = constraint_ns;
-	}
-
-	/*
-	 * If the computed minimum device off time is negative, there are no
-	 * latency constraints, so the domain can spend arbitrary time in the
-	 * "off" state.
-	 */
-	if (min_off_time_ns < 0)
-		return true;
-
-	/*
-	 * The difference between the computed minimum subdomain or device off
-	 * time and the time needed to turn the domain on is the maximum
-	 * theoretical time this domain can spend in the "off" state.
-	 */
-	genpd->max_off_time_ns = min_off_time_ns -
-		genpd->states[state].power_on_latency_ns;
-	return true;
-}
-
-/**
- * default_power_down_ok - Default generic PM domain power off governor routine.
- * @pd: PM domain to check.
- *
- * This routine must be executed under the PM domain's lock.
- */
-static bool default_power_down_ok(struct dev_pm_domain *pd)
-{
-	struct generic_pm_domain *genpd = pd_to_genpd(pd);
-	struct gpd_link *link;
-
-	if (!genpd->max_off_time_changed) {
-		genpd->state_idx = genpd->cached_power_down_state_idx;
-		return genpd->cached_power_down_ok;
-	}
-
-	/*
-	 * We have to invalidate the cached results for the masters, so
-	 * use the observation that default_power_down_ok() is not
-	 * going to be called for any master until this instance
-	 * returns.
-	 */
-	list_for_each_entry(link, &genpd->slave_links, slave_node)
-		link->master->max_off_time_changed = true;
-
-	genpd->max_off_time_ns = -1;
-	genpd->max_off_time_changed = false;
-	genpd->cached_power_down_ok = true;
-	genpd->state_idx = genpd->state_count - 1;
-
-	/* Find a state to power down to, starting from the deepest. */
-	while (!__default_power_down_ok(pd, genpd->state_idx)) {
-		if (genpd->state_idx == 0) {
-			genpd->cached_power_down_ok = false;
-			break;
-		}
-		genpd->state_idx--;
-	}
-
-	genpd->cached_power_down_state_idx = genpd->state_idx;
-	return genpd->cached_power_down_ok;
-}
-
-static bool always_on_power_down_ok(struct dev_pm_domain *domain)
-{
-	return false;
-}
-
-#ifdef CONFIG_CPU_IDLE
-static bool cpu_power_down_ok(struct dev_pm_domain *pd)
-{
-	struct generic_pm_domain *genpd = pd_to_genpd(pd);
-	struct cpuidle_device *dev;
-	ktime_t domain_wakeup, next_hrtimer;
-	s64 idle_duration_ns;
-	int cpu, i;
-
-	/* Validate dev PM QoS constraints. */
-	if (!default_power_down_ok(pd))
-		return false;
-
-	if (!(genpd->flags & GENPD_FLAG_CPU_DOMAIN))
-		return true;
-
-	/*
-	 * Find the next wakeup for any of the online CPUs within the PM domain
-	 * and its subdomains. Note, we only need the genpd->cpus, as it already
-	 * contains a mask of all CPUs from subdomains.
-	 */
-	domain_wakeup = ktime_set(KTIME_SEC_MAX, 0);
-	for_each_cpu_and(cpu, genpd->cpus, cpu_online_mask) {
-		dev = per_cpu(cpuidle_devices, cpu);
-		if (dev) {
-			next_hrtimer = READ_ONCE(dev->next_hrtimer);
-			if (ktime_before(next_hrtimer, domain_wakeup))
-				domain_wakeup = next_hrtimer;
-		}
-	}
-
-	/* The minimum idle duration is from now - until the next wakeup. */
-	idle_duration_ns = ktime_to_ns(ktime_sub(domain_wakeup, ktime_get()));
-	if (idle_duration_ns <= 0)
-		return false;
-
-	/*
-	 * Find the deepest idle state that has its residency value satisfied
-	 * and by also taking into account the power off latency for the state.
-	 * Start at the state picked by the dev PM QoS constraint validation.
-	 */
-	i = genpd->state_idx;
-	do {
-		if (idle_duration_ns >= (genpd->states[i].residency_ns +
-		    genpd->states[i].power_off_latency_ns)) {
-			genpd->state_idx = i;
-			return true;
-		}
-	} while (--i >= 0);
-
-	return false;
-}
-
-struct dev_power_governor pm_domain_cpu_gov = {
-	.suspend_ok = default_suspend_ok,
-	.power_down_ok = cpu_power_down_ok,
-};
-#endif
-
-struct dev_power_governor simple_qos_governor = {
-	.suspend_ok = default_suspend_ok,
-	.power_down_ok = default_power_down_ok,
-};
-
-/**
- * pm_genpd_gov_always_on - A governor implementing an always-on policy
- */
-struct dev_power_governor pm_domain_always_on_gov = {
-	.power_down_ok = always_on_power_down_ok,
-	.suspend_ok = default_suspend_ok,
-};
diff --git a/drivers/base/power/generic_ops.c b/drivers/base/power/generic_ops.c
index 4fa525668cb7..af99bbcf281c 100644
--- a/drivers/base/power/generic_ops.c
+++ b/drivers/base/power/generic_ops.c
@@ -8,6 +8,13 @@
 #include <linux/pm_runtime.h>
 #include <linux/export.h>
 
+#define CALL_PM_OP(dev, op) \
+({ \
+	struct device *_dev = (dev); \
+	const struct dev_pm_ops *pm = _dev->driver ? _dev->driver->pm : NULL; \
+	pm && pm->op ? pm->op(_dev) : 0; \
+})
+
 #ifdef CONFIG_PM
 /**
  * pm_generic_runtime_suspend - Generic runtime suspend callback for subsystems.
@@ -19,12 +26,7 @@
  */
 int pm_generic_runtime_suspend(struct device *dev)
 {
-	const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
-	int ret;
-
-	ret = pm && pm->runtime_suspend ? pm->runtime_suspend(dev) : 0;
-
-	return ret;
+	return CALL_PM_OP(dev, runtime_suspend);
 }
 EXPORT_SYMBOL_GPL(pm_generic_runtime_suspend);
 
@@ -38,12 +40,7 @@ EXPORT_SYMBOL_GPL(pm_generic_runtime_suspend);
  */
 int pm_generic_runtime_resume(struct device *dev)
 {
-	const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
-	int ret;
-
-	ret = pm && pm->runtime_resume ? pm->runtime_resume(dev) : 0;
-
-	return ret;
+	return CALL_PM_OP(dev, runtime_resume);
 }
 EXPORT_SYMBOL_GPL(pm_generic_runtime_resume);
 #endif /* CONFIG_PM */
@@ -72,9 +69,7 @@ int pm_generic_prepare(struct device *dev)
  */
 int pm_generic_suspend_noirq(struct device *dev)
 {
-	const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
-
-	return pm && pm->suspend_noirq ? pm->suspend_noirq(dev) : 0;
+	return CALL_PM_OP(dev, suspend_noirq);
 }
 EXPORT_SYMBOL_GPL(pm_generic_suspend_noirq);
 
@@ -84,9 +79,7 @@ EXPORT_SYMBOL_GPL(pm_generic_suspend_noirq);
  */
 int pm_generic_suspend_late(struct device *dev)
 {
-	const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
-
-	return pm && pm->suspend_late ? pm->suspend_late(dev) : 0;
+	return CALL_PM_OP(dev, suspend_late);
 }
 EXPORT_SYMBOL_GPL(pm_generic_suspend_late);
 
@@ -96,9 +89,7 @@ EXPORT_SYMBOL_GPL(pm_generic_suspend_late);
  */
 int pm_generic_suspend(struct device *dev)
 {
-	const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
-
-	return pm && pm->suspend ? pm->suspend(dev) : 0;
+	return CALL_PM_OP(dev, suspend);
 }
 EXPORT_SYMBOL_GPL(pm_generic_suspend);
 
@@ -108,33 +99,17 @@ EXPORT_SYMBOL_GPL(pm_generic_suspend);
  */
 int pm_generic_freeze_noirq(struct device *dev)
 {
-	const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
-
-	return pm && pm->freeze_noirq ? pm->freeze_noirq(dev) : 0;
+	return CALL_PM_OP(dev, freeze_noirq);
 }
 EXPORT_SYMBOL_GPL(pm_generic_freeze_noirq);
 
 /**
- * pm_generic_freeze_late - Generic freeze_late callback for subsystems.
- * @dev: Device to freeze.
- */
-int pm_generic_freeze_late(struct device *dev)
-{
-	const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
-
-	return pm && pm->freeze_late ? pm->freeze_late(dev) : 0;
-}
-EXPORT_SYMBOL_GPL(pm_generic_freeze_late);
-
-/**
  * pm_generic_freeze - Generic freeze callback for subsystems.
  * @dev: Device to freeze.
  */
 int pm_generic_freeze(struct device *dev)
 {
-	const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
-
-	return pm && pm->freeze ? pm->freeze(dev) : 0;
+	return CALL_PM_OP(dev, freeze);
 }
 EXPORT_SYMBOL_GPL(pm_generic_freeze);
 
@@ -144,9 +119,7 @@ EXPORT_SYMBOL_GPL(pm_generic_freeze);
  */
 int pm_generic_poweroff_noirq(struct device *dev)
 {
-	const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
-
-	return pm && pm->poweroff_noirq ? pm->poweroff_noirq(dev) : 0;
+	return CALL_PM_OP(dev, poweroff_noirq);
 }
 EXPORT_SYMBOL_GPL(pm_generic_poweroff_noirq);
 
@@ -156,9 +129,7 @@ EXPORT_SYMBOL_GPL(pm_generic_poweroff_noirq);
  */
 int pm_generic_poweroff_late(struct device *dev)
 {
-	const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
-
-	return pm && pm->poweroff_late ? pm->poweroff_late(dev) : 0;
+	return CALL_PM_OP(dev, poweroff_late);
 }
 EXPORT_SYMBOL_GPL(pm_generic_poweroff_late);
 
@@ -168,9 +139,7 @@ EXPORT_SYMBOL_GPL(pm_generic_poweroff_late);
  */
 int pm_generic_poweroff(struct device *dev)
 {
-	const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
-
-	return pm && pm->poweroff ? pm->poweroff(dev) : 0;
+	return CALL_PM_OP(dev, poweroff);
 }
 EXPORT_SYMBOL_GPL(pm_generic_poweroff);
 
@@ -180,33 +149,17 @@ EXPORT_SYMBOL_GPL(pm_generic_poweroff);
  */
 int pm_generic_thaw_noirq(struct device *dev)
 {
-	const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
-
-	return pm && pm->thaw_noirq ? pm->thaw_noirq(dev) : 0;
+	return CALL_PM_OP(dev, thaw_noirq);
 }
 EXPORT_SYMBOL_GPL(pm_generic_thaw_noirq);
 
 /**
- * pm_generic_thaw_early - Generic thaw_early callback for subsystems.
- * @dev: Device to thaw.
- */
-int pm_generic_thaw_early(struct device *dev)
-{
-	const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
-
-	return pm && pm->thaw_early ? pm->thaw_early(dev) : 0;
-}
-EXPORT_SYMBOL_GPL(pm_generic_thaw_early);
-
-/**
  * pm_generic_thaw - Generic thaw callback for subsystems.
  * @dev: Device to thaw.
  */
 int pm_generic_thaw(struct device *dev)
 {
-	const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
-
-	return pm && pm->thaw ? pm->thaw(dev) : 0;
+	return CALL_PM_OP(dev, thaw);
 }
 EXPORT_SYMBOL_GPL(pm_generic_thaw);
 
@@ -216,9 +169,7 @@ EXPORT_SYMBOL_GPL(pm_generic_thaw);
  */
 int pm_generic_resume_noirq(struct device *dev)
 {
-	const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
-
-	return pm && pm->resume_noirq ? pm->resume_noirq(dev) : 0;
+	return CALL_PM_OP(dev, resume_noirq);
 }
 EXPORT_SYMBOL_GPL(pm_generic_resume_noirq);
 
@@ -228,9 +179,7 @@ EXPORT_SYMBOL_GPL(pm_generic_resume_noirq);
  */
 int pm_generic_resume_early(struct device *dev)
 {
-	const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
-
-	return pm && pm->resume_early ? pm->resume_early(dev) : 0;
+	return CALL_PM_OP(dev, resume_early);
 }
 EXPORT_SYMBOL_GPL(pm_generic_resume_early);
 
@@ -240,9 +189,7 @@ EXPORT_SYMBOL_GPL(pm_generic_resume_early);
  */
 int pm_generic_resume(struct device *dev)
 {
-	const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
-
-	return pm && pm->resume ? pm->resume(dev) : 0;
+	return CALL_PM_OP(dev, resume);
 }
 EXPORT_SYMBOL_GPL(pm_generic_resume);
 
@@ -252,9 +199,7 @@ EXPORT_SYMBOL_GPL(pm_generic_resume);
  */
 int pm_generic_restore_noirq(struct device *dev)
 {
-	const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
-
-	return pm && pm->restore_noirq ? pm->restore_noirq(dev) : 0;
+	return CALL_PM_OP(dev, restore_noirq);
 }
 EXPORT_SYMBOL_GPL(pm_generic_restore_noirq);
 
@@ -264,9 +209,7 @@ EXPORT_SYMBOL_GPL(pm_generic_restore_noirq);
  */
 int pm_generic_restore_early(struct device *dev)
 {
-	const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
-
-	return pm && pm->restore_early ? pm->restore_early(dev) : 0;
+	return CALL_PM_OP(dev, restore_early);
 }
 EXPORT_SYMBOL_GPL(pm_generic_restore_early);
 
@@ -276,9 +219,7 @@ EXPORT_SYMBOL_GPL(pm_generic_restore_early);
  */
 int pm_generic_restore(struct device *dev)
 {
-	const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
-
-	return pm && pm->restore ? pm->restore(dev) : 0;
+	return CALL_PM_OP(dev, restore);
 }
 EXPORT_SYMBOL_GPL(pm_generic_restore);
 
diff --git a/drivers/base/power/main.c b/drivers/base/power/main.c
index 0e07e17c2def..97a8b4fcf471 100644
--- a/drivers/base/power/main.c
+++ b/drivers/base/power/main.c
@@ -16,6 +16,7 @@
  */
 
 #define pr_fmt(fmt) "PM: " fmt
+#define dev_fmt pr_fmt
 
 #include <linux/device.h>
 #include <linux/export.h>
@@ -31,19 +32,15 @@
 #include <linux/suspend.h>
 #include <trace/events/power.h>
 #include <linux/cpufreq.h>
-#include <linux/cpuidle.h>
 #include <linux/devfreq.h>
 #include <linux/timer.h>
+#include <linux/nmi.h>
 
 #include "../base.h"
 #include "power.h"
 
 typedef int (*pm_callback_t)(struct device *);
 
-#define list_for_each_entry_rcu_locked(pos, head, member) \
-	list_for_each_entry_rcu(pos, head, member, \
-			device_links_read_lock_held())
-
 /*
  * The entries in the dpm_list list are in a depth first order, simply
  * because children are guaranteed to be discovered after parents, and
@@ -60,12 +57,26 @@ static LIST_HEAD(dpm_suspended_list);
 static LIST_HEAD(dpm_late_early_list);
 static LIST_HEAD(dpm_noirq_list);
 
-struct suspend_stats suspend_stats;
 static DEFINE_MUTEX(dpm_list_mtx);
 static pm_message_t pm_transition;
 
+static DEFINE_MUTEX(async_wip_mtx);
 static int async_error;
 
+/**
+ * pm_hibernate_is_recovering - if recovering from hibernate due to error.
+ *
+ * Used to query if dev_pm_ops.thaw() is called for normal hibernation case or
+ * recovering from some error.
+ *
+ * Return: true for error case, false for normal case.
+ */
+bool pm_hibernate_is_recovering(void)
+{
+	return pm_transition.event == PM_EVENT_RECOVER;
+}
+EXPORT_SYMBOL_GPL(pm_hibernate_is_recovering);
+
 static const char *pm_verb(int event)
 {
 	switch (event) {
@@ -85,6 +96,8 @@ static const char *pm_verb(int event)
 		return "restore";
 	case PM_EVENT_RECOVER:
 		return "recover";
+	case PM_EVENT_POWEROFF:
+		return "poweroff";
 	default:
 		return "(unknown PM event)";
 	}
@@ -209,7 +222,7 @@ static ktime_t initcall_debug_start(struct device *dev, void *cb)
 	if (!pm_print_times_enabled)
 		return 0;
 
-	dev_info(dev, "calling %pS @ %i, parent: %s\n", cb,
+	dev_info(dev, "calling %ps @ %i, parent: %s\n", cb,
 		 task_pid_nr(current),
 		 dev->parent ? dev_name(dev->parent) : "none");
 	return ktime_get();
@@ -219,16 +232,13 @@ static void initcall_debug_report(struct device *dev, ktime_t calltime,
 				  void *cb, int error)
 {
 	ktime_t rettime;
-	s64 nsecs;
 
 	if (!pm_print_times_enabled)
 		return;
 
 	rettime = ktime_get();
-	nsecs = (s64) ktime_to_ns(ktime_sub(rettime, calltime));
-
-	dev_info(dev, "%pS returned %d after %Ld usecs\n", cb, error,
-		 (unsigned long long)nsecs >> 10);
+	dev_info(dev, "%ps returned %d after %Ld usecs\n", cb, error,
+		 (unsigned long long)ktime_us_delta(rettime, calltime));
 }
 
 /**
@@ -253,7 +263,7 @@ static int dpm_wait_fn(struct device *dev, void *async_ptr)
 
 static void dpm_wait_for_children(struct device *dev, bool async)
 {
-       device_for_each_child(dev, &async, dpm_wait_fn);
+	device_for_each_child(dev, &async, dpm_wait_fn);
 }
 
 static void dpm_wait_for_suppliers(struct device *dev, bool async)
@@ -270,8 +280,9 @@ static void dpm_wait_for_suppliers(struct device *dev, bool async)
 	 * callbacks freeing the link objects for the links in the list we're
 	 * walking.
 	 */
-	list_for_each_entry_rcu_locked(link, &dev->links.suppliers, c_node)
-		if (READ_ONCE(link->status) != DL_STATE_DORMANT)
+	dev_for_each_link_to_supplier(link, dev)
+		if (READ_ONCE(link->status) != DL_STATE_DORMANT &&
+		    !device_link_flag_is_sync_state_only(link->flags))
 			dpm_wait(link->supplier, async);
 
 	device_links_read_unlock(idx);
@@ -327,8 +338,9 @@ static void dpm_wait_for_consumers(struct device *dev, bool async)
 	 * continue instead of trying to continue in parallel with its
 	 * unregistration).
 	 */
-	list_for_each_entry_rcu_locked(link, &dev->links.consumers, s_node)
-		if (READ_ONCE(link->status) != DL_STATE_DORMANT)
+	dev_for_each_link_to_consumer(link, dev)
+		if (READ_ONCE(link->status) != DL_STATE_DORMANT &&
+		    !device_link_flag_is_sync_state_only(link->flags))
 			dpm_wait(link->consumer, async);
 
 	device_links_read_unlock(idx);
@@ -358,12 +370,12 @@ static pm_callback_t pm_op(const struct dev_pm_ops *ops, pm_message_t state)
 	case PM_EVENT_FREEZE:
 	case PM_EVENT_QUIESCE:
 		return ops->freeze;
+	case PM_EVENT_POWEROFF:
 	case PM_EVENT_HIBERNATE:
 		return ops->poweroff;
 	case PM_EVENT_THAW:
 	case PM_EVENT_RECOVER:
 		return ops->thaw;
-		break;
 	case PM_EVENT_RESTORE:
 		return ops->restore;
 #endif /* CONFIG_HIBERNATE_CALLBACKS */
@@ -393,6 +405,7 @@ static pm_callback_t pm_late_early_op(const struct dev_pm_ops *ops,
 	case PM_EVENT_FREEZE:
 	case PM_EVENT_QUIESCE:
 		return ops->freeze_late;
+	case PM_EVENT_POWEROFF:
 	case PM_EVENT_HIBERNATE:
 		return ops->poweroff_late;
 	case PM_EVENT_THAW:
@@ -427,6 +440,7 @@ static pm_callback_t pm_noirq_op(const struct dev_pm_ops *ops, pm_message_t stat
 	case PM_EVENT_FREEZE:
 	case PM_EVENT_QUIESCE:
 		return ops->freeze_noirq;
+	case PM_EVENT_POWEROFF:
 	case PM_EVENT_HIBERNATE:
 		return ops->poweroff_noirq;
 	case PM_EVENT_THAW:
@@ -442,16 +456,16 @@ static pm_callback_t pm_noirq_op(const struct dev_pm_ops *ops, pm_message_t stat
 
 static void pm_dev_dbg(struct device *dev, pm_message_t state, const char *info)
 {
-	dev_dbg(dev, "%s%s%s\n", info, pm_verb(state.event),
+	dev_dbg(dev, "%s%s%s driver flags: %x\n", info, pm_verb(state.event),
 		((state.event & PM_EVENT_SLEEP) && device_may_wakeup(dev)) ?
-		", may wakeup" : "");
+		", may wakeup" : "", dev->power.driver_flags);
 }
 
 static void pm_dev_err(struct device *dev, pm_message_t state, const char *info,
 			int error)
 {
-	pr_err("Device %s failed to %s%s: error %d\n",
-	       dev_name(dev), pm_verb(state.event), info, error);
+	dev_err(dev, "failed to %s%s: error %d\n", pm_verb(state.event), info,
+		error);
 }
 
 static void dpm_show_time(ktime_t starttime, pm_message_t state, int error,
@@ -489,7 +503,7 @@ static int dpm_run_callback(pm_callback_t cb, struct device *dev,
 	trace_device_pm_callback_start(dev, info, state.event);
 	error = cb(dev);
 	trace_device_pm_callback_end(dev, error);
-	suspend_report_result(cb, error);
+	suspend_report_result(dev, cb, error);
 
 	initcall_debug_report(dev, calltime, cb, error);
 
@@ -501,11 +515,17 @@ struct dpm_watchdog {
 	struct device		*dev;
 	struct task_struct	*tsk;
 	struct timer_list	timer;
+	bool			fatal;
 };
 
 #define DECLARE_DPM_WATCHDOG_ON_STACK(wd) \
 	struct dpm_watchdog wd
 
+static bool __read_mostly dpm_watchdog_all_cpu_backtrace;
+module_param(dpm_watchdog_all_cpu_backtrace, bool, 0644);
+MODULE_PARM_DESC(dpm_watchdog_all_cpu_backtrace,
+		 "Backtrace all CPUs on DPM watchdog timeout");
+
 /**
  * dpm_watchdog_handler - Driver suspend / resume watchdog handler.
  * @t: The timer that PM watchdog depends on.
@@ -516,12 +536,28 @@ struct dpm_watchdog {
  */
 static void dpm_watchdog_handler(struct timer_list *t)
 {
-	struct dpm_watchdog *wd = from_timer(wd, t, timer);
+	struct dpm_watchdog *wd = timer_container_of(wd, t, timer);
+	struct timer_list *timer = &wd->timer;
+	unsigned int time_left;
 
-	dev_emerg(wd->dev, "**** DPM device timeout ****\n");
-	show_stack(wd->tsk, NULL);
-	panic("%s %s: unrecoverable failure\n",
-		dev_driver_string(wd->dev), dev_name(wd->dev));
+	if (wd->fatal) {
+		unsigned int this_cpu = smp_processor_id();
+
+		dev_emerg(wd->dev, "**** DPM device timeout ****\n");
+		show_stack(wd->tsk, NULL, KERN_EMERG);
+		if (dpm_watchdog_all_cpu_backtrace)
+			trigger_allbutcpu_cpu_backtrace(this_cpu);
+		panic("%s %s: unrecoverable failure\n",
+			dev_driver_string(wd->dev), dev_name(wd->dev));
+	}
+
+	time_left = CONFIG_DPM_WATCHDOG_TIMEOUT - CONFIG_DPM_WATCHDOG_WARNING_TIMEOUT;
+	dev_warn(wd->dev, "**** DPM device timeout after %u seconds; %u seconds until panic ****\n",
+		 CONFIG_DPM_WATCHDOG_WARNING_TIMEOUT, time_left);
+	show_stack(wd->tsk, NULL, KERN_WARNING);
+
+	wd->fatal = true;
+	mod_timer(timer, jiffies + HZ * time_left);
 }
 
 /**
@@ -535,10 +571,11 @@ static void dpm_watchdog_set(struct dpm_watchdog *wd, struct device *dev)
 
 	wd->dev = dev;
 	wd->tsk = current;
+	wd->fatal = CONFIG_DPM_WATCHDOG_TIMEOUT == CONFIG_DPM_WATCHDOG_WARNING_TIMEOUT;
 
 	timer_setup_on_stack(timer, dpm_watchdog_handler, 0);
 	/* use same timeout value for both suspend and resume */
-	timer->expires = jiffies + HZ * CONFIG_DPM_WATCHDOG_TIMEOUT;
+	timer->expires = jiffies + HZ * CONFIG_DPM_WATCHDOG_WARNING_TIMEOUT;
 	add_timer(timer);
 }
 
@@ -550,8 +587,8 @@ static void dpm_watchdog_clear(struct dpm_watchdog *wd)
 {
 	struct timer_list *timer = &wd->timer;
 
-	del_timer_sync(timer);
-	destroy_timer_on_stack(timer);
+	timer_delete_sync(timer);
+	timer_destroy_on_stack(timer);
 }
 #else
 #define DECLARE_DPM_WATCHDOG_ON_STACK(wd)
@@ -562,71 +599,121 @@ static void dpm_watchdog_clear(struct dpm_watchdog *wd)
 /*------------------------- Resume routines -------------------------*/
 
 /**
- * suspend_event - Return a "suspend" message for given "resume" one.
- * @resume_msg: PM message representing a system-wide resume transition.
+ * dev_pm_skip_resume - System-wide device resume optimization check.
+ * @dev: Target device.
+ *
+ * Return:
+ * - %false if the transition under way is RESTORE.
+ * - Return value of dev_pm_skip_suspend() if the transition under way is THAW.
+ * - The logical negation of %power.must_resume otherwise (that is, when the
+ *   transition under way is RESUME).
  */
-static pm_message_t suspend_event(pm_message_t resume_msg)
+bool dev_pm_skip_resume(struct device *dev)
 {
-	switch (resume_msg.event) {
-	case PM_EVENT_RESUME:
-		return PMSG_SUSPEND;
-	case PM_EVENT_THAW:
-	case PM_EVENT_RESTORE:
-		return PMSG_FREEZE;
-	case PM_EVENT_RECOVER:
-		return PMSG_HIBERNATE;
-	}
-	return PMSG_ON;
+	if (pm_transition.event == PM_EVENT_RESTORE)
+		return false;
+
+	if (pm_transition.event == PM_EVENT_THAW)
+		return dev_pm_skip_suspend(dev);
+
+	return !dev->power.must_resume;
 }
 
-/**
- * dev_pm_may_skip_resume - System-wide device resume optimization check.
- * @dev: Target device.
- *
- * Checks whether or not the device may be left in suspend after a system-wide
- * transition to the working state.
- */
-bool dev_pm_may_skip_resume(struct device *dev)
+static bool is_async(struct device *dev)
 {
-	return !dev->power.must_resume && pm_transition.event != PM_EVENT_RESTORE;
+	return dev->power.async_suspend && pm_async_enabled
+		&& !pm_trace_is_enabled();
 }
 
-static pm_callback_t dpm_subsys_resume_noirq_cb(struct device *dev,
-						pm_message_t state,
-						const char **info_p)
+static bool __dpm_async(struct device *dev, async_func_t func)
 {
-	pm_callback_t callback;
-	const char *info;
+	if (dev->power.work_in_progress)
+		return true;
 
-	if (dev->pm_domain) {
-		info = "noirq power domain ";
-		callback = pm_noirq_op(&dev->pm_domain->ops, state);
-	} else if (dev->type && dev->type->pm) {
-		info = "noirq type ";
-		callback = pm_noirq_op(dev->type->pm, state);
-	} else if (dev->class && dev->class->pm) {
-		info = "noirq class ";
-		callback = pm_noirq_op(dev->class->pm, state);
-	} else if (dev->bus && dev->bus->pm) {
-		info = "noirq bus ";
-		callback = pm_noirq_op(dev->bus->pm, state);
-	} else {
-		return NULL;
-	}
+	if (!is_async(dev))
+		return false;
+
+	dev->power.work_in_progress = true;
+
+	get_device(dev);
+
+	if (async_schedule_dev_nocall(func, dev))
+		return true;
+
+	put_device(dev);
+
+	return false;
+}
 
-	if (info_p)
-		*info_p = info;
+static bool dpm_async_fn(struct device *dev, async_func_t func)
+{
+	guard(mutex)(&async_wip_mtx);
 
-	return callback;
+	return __dpm_async(dev, func);
 }
 
-static pm_callback_t dpm_subsys_suspend_noirq_cb(struct device *dev,
-						 pm_message_t state,
-						 const char **info_p);
+static int dpm_async_with_cleanup(struct device *dev, void *fn)
+{
+	guard(mutex)(&async_wip_mtx);
+
+	if (!__dpm_async(dev, fn))
+		dev->power.work_in_progress = false;
 
-static pm_callback_t dpm_subsys_suspend_late_cb(struct device *dev,
-						pm_message_t state,
-						const char **info_p);
+	return 0;
+}
+
+static void dpm_async_resume_children(struct device *dev, async_func_t func)
+{
+	/*
+	 * Prevent racing with dpm_clear_async_state() during initial list
+	 * walks in dpm_noirq_resume_devices(), dpm_resume_early(), and
+	 * dpm_resume().
+	 */
+	guard(mutex)(&dpm_list_mtx);
+
+	/*
+	 * Start processing "async" children of the device unless it's been
+	 * started already for them.
+	 */
+	device_for_each_child(dev, func, dpm_async_with_cleanup);
+}
+
+static void dpm_async_resume_subordinate(struct device *dev, async_func_t func)
+{
+	struct device_link *link;
+	int idx;
+
+	dpm_async_resume_children(dev, func);
+
+	idx = device_links_read_lock();
+
+	/* Start processing the device's "async" consumers. */
+	dev_for_each_link_to_consumer(link, dev)
+		if (READ_ONCE(link->status) != DL_STATE_DORMANT)
+			dpm_async_with_cleanup(link->consumer, func);
+
+	device_links_read_unlock(idx);
+}
+
+static void dpm_clear_async_state(struct device *dev)
+{
+	reinit_completion(&dev->power.completion);
+	dev->power.work_in_progress = false;
+}
+
+static bool dpm_root_device(struct device *dev)
+{
+	lockdep_assert_held(&dpm_list_mtx);
+
+	/*
+	 * Since this function is required to run under dpm_list_mtx, the
+	 * list_empty() below will only return true if the device's list of
+	 * consumers is actually empty before calling it.
+	 */
+	return !dev->parent && list_empty(&dev->links.suppliers);
+}
+
+static void async_resume_noirq(void *data, async_cookie_t cookie);
 
 /**
  * device_resume_noirq - Execute a "noirq resume" callback for given device.
@@ -637,10 +724,10 @@ static pm_callback_t dpm_subsys_suspend_late_cb(struct device *dev,
  * The driver of @dev will not receive interrupts while this function is being
  * executed.
  */
-static int device_resume_noirq(struct device *dev, pm_message_t state, bool async)
+static void device_resume_noirq(struct device *dev, pm_message_t state, bool async)
 {
-	pm_callback_t callback;
-	const char *info;
+	pm_callback_t callback = NULL;
+	const char *info = NULL;
 	bool skip_resume;
 	int error = 0;
 
@@ -650,43 +737,59 @@ static int device_resume_noirq(struct device *dev, pm_message_t state, bool asyn
 	if (dev->power.syscore || dev->power.direct_complete)
 		goto Out;
 
-	if (!dev->power.is_noirq_suspended)
+	if (!dev->power.is_noirq_suspended) {
+		/*
+		 * This means that system suspend has been aborted in the noirq
+		 * phase before invoking the noirq suspend callback for the
+		 * device, so if device_suspend_late() has left it in suspend,
+		 * device_resume_early() should leave it in suspend either in
+		 * case the early resume of it depends on the noirq resume that
+		 * has not run.
+		 */
+		if (dev_pm_skip_suspend(dev))
+			dev->power.must_resume = false;
+
 		goto Out;
+	}
 
 	if (!dpm_wait_for_superior(dev, async))
 		goto Out;
 
-	skip_resume = dev_pm_may_skip_resume(dev);
+	skip_resume = dev_pm_skip_resume(dev);
+	/*
+	 * If the driver callback is skipped below or by the middle layer
+	 * callback and device_resume_early() also skips the driver callback for
+	 * this device later, it needs to appear as "suspended" to PM-runtime,
+	 * so change its status accordingly.
+	 *
+	 * Otherwise, the device is going to be resumed, so set its PM-runtime
+	 * status to "active" unless its power.smart_suspend flag is clear, in
+	 * which case it is not necessary to update its PM-runtime status.
+	 */
+	if (skip_resume)
+		pm_runtime_set_suspended(dev);
+	else if (dev_pm_smart_suspend(dev))
+		pm_runtime_set_active(dev);
 
-	callback = dpm_subsys_resume_noirq_cb(dev, state, &info);
+	if (dev->pm_domain) {
+		info = "noirq power domain ";
+		callback = pm_noirq_op(&dev->pm_domain->ops, state);
+	} else if (dev->type && dev->type->pm) {
+		info = "noirq type ";
+		callback = pm_noirq_op(dev->type->pm, state);
+	} else if (dev->class && dev->class->pm) {
+		info = "noirq class ";
+		callback = pm_noirq_op(dev->class->pm, state);
+	} else if (dev->bus && dev->bus->pm) {
+		info = "noirq bus ";
+		callback = pm_noirq_op(dev->bus->pm, state);
+	}
 	if (callback)
 		goto Run;
 
 	if (skip_resume)
 		goto Skip;
 
-	if (dev_pm_smart_suspend_and_suspended(dev)) {
-		pm_message_t suspend_msg = suspend_event(state);
-
-		/*
-		 * If "freeze" callbacks have been skipped during a transition
-		 * related to hibernation, the subsequent "thaw" callbacks must
-		 * be skipped too or bad things may happen.  Otherwise, resume
-		 * callbacks are going to be run for the device, so its runtime
-		 * PM status must be changed to reflect the new state after the
-		 * transition under way.
-		 */
-		if (!dpm_subsys_suspend_late_cb(dev, suspend_msg, NULL) &&
-		    !dpm_subsys_suspend_noirq_cb(dev, suspend_msg, NULL)) {
-			if (state.event == PM_EVENT_THAW) {
-				skip_resume = true;
-				goto Skip;
-			} else {
-				pm_runtime_set_active(dev);
-			}
-		}
-	}
-
 	if (dev->driver && dev->driver->pm) {
 		info = "noirq driver ";
 		callback = pm_noirq_op(dev->driver->pm, state);
@@ -698,54 +801,24 @@ Run:
 Skip:
 	dev->power.is_noirq_suspended = false;
 
-	if (skip_resume) {
-		/* Make the next phases of resume skip the device. */
-		dev->power.is_late_suspended = false;
-		dev->power.is_suspended = false;
-		/*
-		 * The device is going to be left in suspend, but it might not
-		 * have been in runtime suspend before the system suspended, so
-		 * its runtime PM status needs to be updated to avoid confusing
-		 * the runtime PM framework when runtime PM is enabled for the
-		 * device again.
-		 */
-		pm_runtime_set_suspended(dev);
-	}
-
 Out:
 	complete_all(&dev->power.completion);
 	TRACE_RESUME(error);
-	return error;
-}
 
-static bool is_async(struct device *dev)
-{
-	return dev->power.async_suspend && pm_async_enabled
-		&& !pm_trace_is_enabled();
-}
-
-static bool dpm_async_fn(struct device *dev, async_func_t func)
-{
-	reinit_completion(&dev->power.completion);
-
-	if (is_async(dev)) {
-		get_device(dev);
-		async_schedule_dev(func, dev);
-		return true;
+	if (error) {
+		WRITE_ONCE(async_error, error);
+		dpm_save_failed_dev(dev_name(dev));
+		pm_dev_err(dev, state, async ? " async noirq" : " noirq", error);
 	}
 
-	return false;
+	dpm_async_resume_subordinate(dev, async_resume_noirq);
 }
 
 static void async_resume_noirq(void *data, async_cookie_t cookie)
 {
-	struct device *dev = (struct device *)data;
-	int error;
-
-	error = device_resume_noirq(dev, pm_transition, true);
-	if (error)
-		pm_dev_err(dev, pm_transition, " async", error);
+	struct device *dev = data;
 
+	device_resume_noirq(dev, pm_transition, true);
 	put_device(dev);
 }
 
@@ -755,41 +828,44 @@ static void dpm_noirq_resume_devices(pm_message_t state)
 	ktime_t starttime = ktime_get();
 
 	trace_suspend_resume(TPS("dpm_resume_noirq"), state.event, true);
-	mutex_lock(&dpm_list_mtx);
+
+	async_error = 0;
 	pm_transition = state;
 
+	mutex_lock(&dpm_list_mtx);
+
 	/*
-	 * Advanced the async threads upfront,
-	 * in case the starting of async threads is
-	 * delayed by non-async resuming devices.
+	 * Start processing "async" root devices upfront so they don't wait for
+	 * the "sync" devices they don't depend on.
 	 */
-	list_for_each_entry(dev, &dpm_noirq_list, power.entry)
-		dpm_async_fn(dev, async_resume_noirq);
+	list_for_each_entry(dev, &dpm_noirq_list, power.entry) {
+		dpm_clear_async_state(dev);
+		if (dpm_root_device(dev))
+			dpm_async_with_cleanup(dev, async_resume_noirq);
+	}
 
 	while (!list_empty(&dpm_noirq_list)) {
 		dev = to_device(dpm_noirq_list.next);
-		get_device(dev);
 		list_move_tail(&dev->power.entry, &dpm_late_early_list);
-		mutex_unlock(&dpm_list_mtx);
 
-		if (!is_async(dev)) {
-			int error;
+		if (!dpm_async_fn(dev, async_resume_noirq)) {
+			get_device(dev);
 
-			error = device_resume_noirq(dev, state, false);
-			if (error) {
-				suspend_stats.failed_resume_noirq++;
-				dpm_save_failed_step(SUSPEND_RESUME_NOIRQ);
-				dpm_save_failed_dev(dev_name(dev));
-				pm_dev_err(dev, state, " noirq", error);
-			}
-		}
+			mutex_unlock(&dpm_list_mtx);
 
-		mutex_lock(&dpm_list_mtx);
-		put_device(dev);
+			device_resume_noirq(dev, state, false);
+
+			put_device(dev);
+
+			mutex_lock(&dpm_list_mtx);
+		}
 	}
 	mutex_unlock(&dpm_list_mtx);
 	async_synchronize_full();
 	dpm_show_time(starttime, state, 0, "noirq");
+	if (READ_ONCE(async_error))
+		dpm_save_failed_step(SUSPEND_RESUME_NOIRQ);
+
 	trace_suspend_resume(TPS("dpm_resume_noirq"), state.event, false);
 }
 
@@ -806,38 +882,9 @@ void dpm_resume_noirq(pm_message_t state)
 
 	resume_device_irqs();
 	device_wakeup_disarm_wake_irqs();
-
-	cpuidle_resume();
 }
 
-static pm_callback_t dpm_subsys_resume_early_cb(struct device *dev,
-						pm_message_t state,
-						const char **info_p)
-{
-	pm_callback_t callback;
-	const char *info;
-
-	if (dev->pm_domain) {
-		info = "early power domain ";
-		callback = pm_late_early_op(&dev->pm_domain->ops, state);
-	} else if (dev->type && dev->type->pm) {
-		info = "early type ";
-		callback = pm_late_early_op(dev->type->pm, state);
-	} else if (dev->class && dev->class->pm) {
-		info = "early class ";
-		callback = pm_late_early_op(dev->class->pm, state);
-	} else if (dev->bus && dev->bus->pm) {
-		info = "early bus ";
-		callback = pm_late_early_op(dev->bus->pm, state);
-	} else {
-		return NULL;
-	}
-
-	if (info_p)
-		*info_p = info;
-
-	return callback;
-}
+static void async_resume_early(void *data, async_cookie_t cookie);
 
 /**
  * device_resume_early - Execute an "early resume" callback for given device.
@@ -847,51 +894,77 @@ static pm_callback_t dpm_subsys_resume_early_cb(struct device *dev,
  *
  * Runtime PM is disabled for @dev while this function is being executed.
  */
-static int device_resume_early(struct device *dev, pm_message_t state, bool async)
+static void device_resume_early(struct device *dev, pm_message_t state, bool async)
 {
-	pm_callback_t callback;
-	const char *info;
+	pm_callback_t callback = NULL;
+	const char *info = NULL;
 	int error = 0;
 
 	TRACE_DEVICE(dev);
 	TRACE_RESUME(0);
 
-	if (dev->power.syscore || dev->power.direct_complete)
+	if (dev->power.direct_complete)
 		goto Out;
 
 	if (!dev->power.is_late_suspended)
 		goto Out;
 
+	if (dev->power.syscore)
+		goto Skip;
+
 	if (!dpm_wait_for_superior(dev, async))
 		goto Out;
 
-	callback = dpm_subsys_resume_early_cb(dev, state, &info);
+	if (dev->pm_domain) {
+		info = "early power domain ";
+		callback = pm_late_early_op(&dev->pm_domain->ops, state);
+	} else if (dev->type && dev->type->pm) {
+		info = "early type ";
+		callback = pm_late_early_op(dev->type->pm, state);
+	} else if (dev->class && dev->class->pm) {
+		info = "early class ";
+		callback = pm_late_early_op(dev->class->pm, state);
+	} else if (dev->bus && dev->bus->pm) {
+		info = "early bus ";
+		callback = pm_late_early_op(dev->bus->pm, state);
+	}
+	if (callback)
+		goto Run;
+
+	if (dev_pm_skip_resume(dev))
+		goto Skip;
 
-	if (!callback && dev->driver && dev->driver->pm) {
+	if (dev->driver && dev->driver->pm) {
 		info = "early driver ";
 		callback = pm_late_early_op(dev->driver->pm, state);
 	}
 
+Run:
 	error = dpm_run_callback(callback, dev, state, info);
+
+Skip:
 	dev->power.is_late_suspended = false;
+	pm_runtime_enable(dev);
 
- Out:
+Out:
 	TRACE_RESUME(error);
 
-	pm_runtime_enable(dev);
 	complete_all(&dev->power.completion);
-	return error;
+
+	if (error) {
+		WRITE_ONCE(async_error, error);
+		dpm_save_failed_dev(dev_name(dev));
+		pm_dev_err(dev, state, async ? " async early" : " early", error);
+	}
+
+	dpm_async_resume_subordinate(dev, async_resume_early);
 }
 
 static void async_resume_early(void *data, async_cookie_t cookie)
 {
-	struct device *dev = (struct device *)data;
-	int error;
-
-	error = device_resume_early(dev, pm_transition, true);
-	if (error)
-		pm_dev_err(dev, pm_transition, " async", error);
+	struct device *dev = data;
 
+	device_resume_early(dev, pm_transition, true);
 	put_device(dev);
 }
 
@@ -905,40 +978,44 @@ void dpm_resume_early(pm_message_t state)
 	ktime_t starttime = ktime_get();
 
 	trace_suspend_resume(TPS("dpm_resume_early"), state.event, true);
-	mutex_lock(&dpm_list_mtx);
+
+	async_error = 0;
 	pm_transition = state;
 
+	mutex_lock(&dpm_list_mtx);
+
 	/*
-	 * Advanced the async threads upfront,
-	 * in case the starting of async threads is
-	 * delayed by non-async resuming devices.
+	 * Start processing "async" root devices upfront so they don't wait for
+	 * the "sync" devices they don't depend on.
 	 */
-	list_for_each_entry(dev, &dpm_late_early_list, power.entry)
-		dpm_async_fn(dev, async_resume_early);
+	list_for_each_entry(dev, &dpm_late_early_list, power.entry) {
+		dpm_clear_async_state(dev);
+		if (dpm_root_device(dev))
+			dpm_async_with_cleanup(dev, async_resume_early);
+	}
 
 	while (!list_empty(&dpm_late_early_list)) {
 		dev = to_device(dpm_late_early_list.next);
-		get_device(dev);
 		list_move_tail(&dev->power.entry, &dpm_suspended_list);
-		mutex_unlock(&dpm_list_mtx);
 
-		if (!is_async(dev)) {
-			int error;
+		if (!dpm_async_fn(dev, async_resume_early)) {
+			get_device(dev);
 
-			error = device_resume_early(dev, state, false);
-			if (error) {
-				suspend_stats.failed_resume_early++;
-				dpm_save_failed_step(SUSPEND_RESUME_EARLY);
-				dpm_save_failed_dev(dev_name(dev));
-				pm_dev_err(dev, state, " early", error);
-			}
+			mutex_unlock(&dpm_list_mtx);
+
+			device_resume_early(dev, state, false);
+
+			put_device(dev);
+
+			mutex_lock(&dpm_list_mtx);
 		}
-		mutex_lock(&dpm_list_mtx);
-		put_device(dev);
 	}
 	mutex_unlock(&dpm_list_mtx);
 	async_synchronize_full();
 	dpm_show_time(starttime, state, 0, "early");
+	if (READ_ONCE(async_error))
+		dpm_save_failed_step(SUSPEND_RESUME_EARLY);
+
 	trace_suspend_resume(TPS("dpm_resume_early"), state.event, false);
 }
 
@@ -953,13 +1030,15 @@ void dpm_resume_start(pm_message_t state)
 }
 EXPORT_SYMBOL_GPL(dpm_resume_start);
 
+static void async_resume(void *data, async_cookie_t cookie);
+
 /**
  * device_resume - Execute "resume" callbacks for given device.
  * @dev: Device to handle.
  * @state: PM transition of the system being carried out.
  * @async: If true, the device is being resumed asynchronously.
  */
-static int device_resume(struct device *dev, pm_message_t state, bool async)
+static void device_resume(struct device *dev, pm_message_t state, bool async)
 {
 	pm_callback_t callback = NULL;
 	const char *info = NULL;
@@ -972,8 +1051,20 @@ static int device_resume(struct device *dev, pm_message_t state, bool async)
 	if (dev->power.syscore)
 		goto Complete;
 
+	if (!dev->power.is_suspended)
+		goto Complete;
+
+	dev->power.is_suspended = false;
+
 	if (dev->power.direct_complete) {
-		/* Match the pm_runtime_disable() in __device_suspend(). */
+		/*
+		 * Allow new children to be added under the device after this
+		 * point if it has no PM callbacks.
+		 */
+		if (dev->power.no_pm_callbacks)
+			dev->power.is_prepared = false;
+
+		/* Match the pm_runtime_disable() in device_suspend(). */
 		pm_runtime_enable(dev);
 		goto Complete;
 	}
@@ -990,9 +1081,6 @@ static int device_resume(struct device *dev, pm_message_t state, bool async)
 	 */
 	dev->power.is_prepared = false;
 
-	if (!dev->power.is_suspended)
-		goto Unlock;
-
 	if (dev->pm_domain) {
 		info = "power domain ";
 		callback = pm_op(&dev->pm_domain->ops, state);
@@ -1030,9 +1118,7 @@ static int device_resume(struct device *dev, pm_message_t state, bool async)
 
  End:
 	error = dpm_run_callback(callback, dev, state, info);
-	dev->power.is_suspended = false;
 
- Unlock:
 	device_unlock(dev);
 	dpm_watchdog_clear(&wd);
 
@@ -1041,17 +1127,20 @@ static int device_resume(struct device *dev, pm_message_t state, bool async)
 
 	TRACE_RESUME(error);
 
-	return error;
+	if (error) {
+		WRITE_ONCE(async_error, error);
+		dpm_save_failed_dev(dev_name(dev));
+		pm_dev_err(dev, state, async ? " async" : "", error);
+	}
+
+	dpm_async_resume_subordinate(dev, async_resume);
 }
 
 static void async_resume(void *data, async_cookie_t cookie)
 {
-	struct device *dev = (struct device *)data;
-	int error;
+	struct device *dev = data;
 
-	error = device_resume(dev, pm_transition, true);
-	if (error)
-		pm_dev_err(dev, pm_transition, " async", error);
+	device_resume(dev, pm_transition, true);
 	put_device(dev);
 }
 
@@ -1068,40 +1157,43 @@ void dpm_resume(pm_message_t state)
 	ktime_t starttime = ktime_get();
 
 	trace_suspend_resume(TPS("dpm_resume"), state.event, true);
-	might_sleep();
 
-	mutex_lock(&dpm_list_mtx);
 	pm_transition = state;
 	async_error = 0;
 
-	list_for_each_entry(dev, &dpm_suspended_list, power.entry)
-		dpm_async_fn(dev, async_resume);
+	mutex_lock(&dpm_list_mtx);
+
+	/*
+	 * Start processing "async" root devices upfront so they don't wait for
+	 * the "sync" devices they don't depend on.
+	 */
+	list_for_each_entry(dev, &dpm_suspended_list, power.entry) {
+		dpm_clear_async_state(dev);
+		if (dpm_root_device(dev))
+			dpm_async_with_cleanup(dev, async_resume);
+	}
 
 	while (!list_empty(&dpm_suspended_list)) {
 		dev = to_device(dpm_suspended_list.next);
-		get_device(dev);
-		if (!is_async(dev)) {
-			int error;
+		list_move_tail(&dev->power.entry, &dpm_prepared_list);
+
+		if (!dpm_async_fn(dev, async_resume)) {
+			get_device(dev);
 
 			mutex_unlock(&dpm_list_mtx);
 
-			error = device_resume(dev, state, false);
-			if (error) {
-				suspend_stats.failed_resume++;
-				dpm_save_failed_step(SUSPEND_RESUME);
-				dpm_save_failed_dev(dev_name(dev));
-				pm_dev_err(dev, state, "", error);
-			}
+			device_resume(dev, state, false);
+
+			put_device(dev);
 
 			mutex_lock(&dpm_list_mtx);
 		}
-		if (!list_empty(&dev->power.entry))
-			list_move_tail(&dev->power.entry, &dpm_prepared_list);
-		put_device(dev);
 	}
 	mutex_unlock(&dpm_list_mtx);
 	async_synchronize_full();
 	dpm_show_time(starttime, state, 0, NULL);
+	if (READ_ONCE(async_error))
+		dpm_save_failed_step(SUSPEND_RESUME);
 
 	cpufreq_resume();
 	devfreq_resume();
@@ -1119,7 +1211,7 @@ static void device_complete(struct device *dev, pm_message_t state)
 	const char *info = NULL;
 
 	if (dev->power.syscore)
-		return;
+		goto out;
 
 	device_lock(dev);
 
@@ -1149,6 +1241,9 @@ static void device_complete(struct device *dev, pm_message_t state)
 
 	device_unlock(dev);
 
+out:
+	/* If enabling runtime PM for the device is blocked, unblock it. */
+	pm_runtime_unblock(dev);
 	pm_runtime_put(dev);
 }
 
@@ -1164,7 +1259,6 @@ void dpm_complete(pm_message_t state)
 	struct list_head list;
 
 	trace_suspend_resume(TPS("dpm_complete"), state.event, true);
-	might_sleep();
 
 	INIT_LIST_HEAD(&list);
 	mutex_lock(&dpm_list_mtx);
@@ -1174,14 +1268,16 @@ void dpm_complete(pm_message_t state)
 		get_device(dev);
 		dev->power.is_prepared = false;
 		list_move(&dev->power.entry, &list);
+
 		mutex_unlock(&dpm_list_mtx);
 
 		trace_device_pm_callback_start(dev, "", state.event);
 		device_complete(dev, state);
 		trace_device_pm_callback_end(dev, 0);
 
-		mutex_lock(&dpm_list_mtx);
 		put_device(dev);
+
+		mutex_lock(&dpm_list_mtx);
 	}
 	list_splice(&list, &dpm_list);
 	mutex_unlock(&dpm_list_mtx);
@@ -1201,6 +1297,7 @@ void dpm_complete(pm_message_t state)
 void dpm_resume_end(pm_message_t state)
 {
 	dpm_resume(state);
+	pm_restore_gfp_mask();
 	dpm_complete(state);
 }
 EXPORT_SYMBOL_GPL(dpm_resume_end);
@@ -1208,6 +1305,82 @@ EXPORT_SYMBOL_GPL(dpm_resume_end);
 
 /*------------------------- Suspend routines -------------------------*/
 
+static bool dpm_leaf_device(struct device *dev)
+{
+	struct device *child;
+
+	lockdep_assert_held(&dpm_list_mtx);
+
+	child = device_find_any_child(dev);
+	if (child) {
+		put_device(child);
+
+		return false;
+	}
+
+	/*
+	 * Since this function is required to run under dpm_list_mtx, the
+	 * list_empty() below will only return true if the device's list of
+	 * consumers is actually empty before calling it.
+	 */
+	return list_empty(&dev->links.consumers);
+}
+
+static bool dpm_async_suspend_parent(struct device *dev, async_func_t func)
+{
+	guard(mutex)(&dpm_list_mtx);
+
+	/*
+	 * If the device is suspended asynchronously and the parent's callback
+	 * deletes both the device and the parent itself, the parent object may
+	 * be freed while this function is running, so avoid that by checking
+	 * if the device has been deleted already as the parent cannot be
+	 * deleted before it.
+	 */
+	if (!device_pm_initialized(dev))
+		return false;
+
+	/* Start processing the device's parent if it is "async". */
+	if (dev->parent)
+		dpm_async_with_cleanup(dev->parent, func);
+
+	return true;
+}
+
+static void dpm_async_suspend_superior(struct device *dev, async_func_t func)
+{
+	struct device_link *link;
+	int idx;
+
+	if (!dpm_async_suspend_parent(dev, func))
+		return;
+
+	idx = device_links_read_lock();
+
+	/* Start processing the device's "async" suppliers. */
+	dev_for_each_link_to_supplier(link, dev)
+		if (READ_ONCE(link->status) != DL_STATE_DORMANT)
+			dpm_async_with_cleanup(link->supplier, func);
+
+	device_links_read_unlock(idx);
+}
+
+static void dpm_async_suspend_complete_all(struct list_head *device_list)
+{
+	struct device *dev;
+
+	guard(mutex)(&async_wip_mtx);
+
+	list_for_each_entry_reverse(dev, device_list, power.entry) {
+		/*
+		 * In case the device is being waited for and async processing
+		 * has not started for it yet, let the waiters make progress.
+		 */
+		if (!dev->power.work_in_progress)
+			complete_all(&dev->power.completion);
+	}
+}
+
 /**
  * resume_event - Return a "resume" message for given "suspend" sleep state.
  * @sleep_state: PM message representing a sleep state.
@@ -1239,69 +1412,16 @@ static void dpm_superior_set_must_resume(struct device *dev)
 
 	idx = device_links_read_lock();
 
-	list_for_each_entry_rcu_locked(link, &dev->links.suppliers, c_node)
+	dev_for_each_link_to_supplier(link, dev)
 		link->supplier->power.must_resume = true;
 
 	device_links_read_unlock(idx);
 }
 
-static pm_callback_t dpm_subsys_suspend_noirq_cb(struct device *dev,
-						 pm_message_t state,
-						 const char **info_p)
-{
-	pm_callback_t callback;
-	const char *info;
-
-	if (dev->pm_domain) {
-		info = "noirq power domain ";
-		callback = pm_noirq_op(&dev->pm_domain->ops, state);
-	} else if (dev->type && dev->type->pm) {
-		info = "noirq type ";
-		callback = pm_noirq_op(dev->type->pm, state);
-	} else if (dev->class && dev->class->pm) {
-		info = "noirq class ";
-		callback = pm_noirq_op(dev->class->pm, state);
-	} else if (dev->bus && dev->bus->pm) {
-		info = "noirq bus ";
-		callback = pm_noirq_op(dev->bus->pm, state);
-	} else {
-		return NULL;
-	}
-
-	if (info_p)
-		*info_p = info;
-
-	return callback;
-}
-
-static bool device_must_resume(struct device *dev, pm_message_t state,
-			       bool no_subsys_suspend_noirq)
-{
-	pm_message_t resume_msg = resume_event(state);
-
-	/*
-	 * If all of the device driver's "noirq", "late" and "early" callbacks
-	 * are invoked directly by the core, the decision to allow the device to
-	 * stay in suspend can be based on its current runtime PM status and its
-	 * wakeup settings.
-	 */
-	if (no_subsys_suspend_noirq &&
-	    !dpm_subsys_suspend_late_cb(dev, state, NULL) &&
-	    !dpm_subsys_resume_early_cb(dev, resume_msg, NULL) &&
-	    !dpm_subsys_resume_noirq_cb(dev, resume_msg, NULL))
-		return !pm_runtime_status_suspended(dev) &&
-			(resume_msg.event != PM_EVENT_RESUME ||
-			 (device_can_wakeup(dev) && !device_may_wakeup(dev)));
-
-	/*
-	 * The only safe strategy here is to require that if the device may not
-	 * be left in suspend, resume callbacks must be invoked for it.
-	 */
-	return !dev->power.may_skip_resume;
-}
+static void async_suspend_noirq(void *data, async_cookie_t cookie);
 
 /**
- * __device_suspend_noirq - Execute a "noirq suspend" callback for given device.
+ * device_suspend_noirq - Execute a "noirq suspend" callback for given device.
  * @dev: Device to handle.
  * @state: PM transition of the system being carried out.
  * @async: If true, the device is being suspended asynchronously.
@@ -1309,11 +1429,10 @@ static bool device_must_resume(struct device *dev, pm_message_t state,
  * The driver of @dev will not receive interrupts while this function is being
  * executed.
  */
-static int __device_suspend_noirq(struct device *dev, pm_message_t state, bool async)
+static void device_suspend_noirq(struct device *dev, pm_message_t state, bool async)
 {
-	pm_callback_t callback;
-	const char *info;
-	bool no_subsys_cb = false;
+	pm_callback_t callback = NULL;
+	const char *info = NULL;
 	int error = 0;
 
 	TRACE_DEVICE(dev);
@@ -1321,19 +1440,29 @@ static int __device_suspend_noirq(struct device *dev, pm_message_t state, bool a
 
 	dpm_wait_for_subordinate(dev, async);
 
-	if (async_error)
+	if (READ_ONCE(async_error))
 		goto Complete;
 
 	if (dev->power.syscore || dev->power.direct_complete)
 		goto Complete;
 
-	callback = dpm_subsys_suspend_noirq_cb(dev, state, &info);
+	if (dev->pm_domain) {
+		info = "noirq power domain ";
+		callback = pm_noirq_op(&dev->pm_domain->ops, state);
+	} else if (dev->type && dev->type->pm) {
+		info = "noirq type ";
+		callback = pm_noirq_op(dev->type->pm, state);
+	} else if (dev->class && dev->class->pm) {
+		info = "noirq class ";
+		callback = pm_noirq_op(dev->class->pm, state);
+	} else if (dev->bus && dev->bus->pm) {
+		info = "noirq bus ";
+		callback = pm_noirq_op(dev->bus->pm, state);
+	}
 	if (callback)
 		goto Run;
 
-	no_subsys_cb = !dpm_subsys_suspend_late_cb(dev, state, NULL);
-
-	if (dev_pm_smart_suspend_and_suspended(dev) && no_subsys_cb)
+	if (dev_pm_skip_suspend(dev))
 		goto Skip;
 
 	if (dev->driver && dev->driver->pm) {
@@ -1344,20 +1473,24 @@ static int __device_suspend_noirq(struct device *dev, pm_message_t state, bool a
 Run:
 	error = dpm_run_callback(callback, dev, state, info);
 	if (error) {
-		async_error = error;
+		WRITE_ONCE(async_error, error);
+		dpm_save_failed_dev(dev_name(dev));
+		pm_dev_err(dev, state, async ? " async noirq" : " noirq", error);
 		goto Complete;
 	}
 
 Skip:
 	dev->power.is_noirq_suspended = true;
 
-	if (dev_pm_test_driver_flags(dev, DPM_FLAG_LEAVE_SUSPENDED)) {
-		dev->power.must_resume = dev->power.must_resume ||
-				atomic_read(&dev->power.usage_count) > 1 ||
-				device_must_resume(dev, state, no_subsys_cb);
-	} else {
+	/*
+	 * Devices must be resumed unless they are explicitly allowed to be left
+	 * in suspend, but even in that case skipping the resume of devices that
+	 * were in use right before the system suspend (as indicated by their
+	 * runtime PM usage counters and child counters) would be suboptimal.
+	 */
+	if (!(dev_pm_test_driver_flags(dev, DPM_FLAG_MAY_SKIP_RESUME) &&
+	      dev->power.may_skip_resume) || !pm_runtime_need_not_resume(dev))
 		dev->power.must_resume = true;
-	}
 
 	if (dev->power.must_resume)
 		dpm_superior_set_must_resume(dev);
@@ -1365,72 +1498,81 @@ Skip:
 Complete:
 	complete_all(&dev->power.completion);
 	TRACE_SUSPEND(error);
-	return error;
-}
-
-static void async_suspend_noirq(void *data, async_cookie_t cookie)
-{
-	struct device *dev = (struct device *)data;
-	int error;
 
-	error = __device_suspend_noirq(dev, pm_transition, true);
-	if (error) {
-		dpm_save_failed_dev(dev_name(dev));
-		pm_dev_err(dev, pm_transition, " async", error);
-	}
+	if (error || READ_ONCE(async_error))
+		return;
 
-	put_device(dev);
+	dpm_async_suspend_superior(dev, async_suspend_noirq);
 }
 
-static int device_suspend_noirq(struct device *dev)
+static void async_suspend_noirq(void *data, async_cookie_t cookie)
 {
-	if (dpm_async_fn(dev, async_suspend_noirq))
-		return 0;
+	struct device *dev = data;
 
-	return __device_suspend_noirq(dev, pm_transition, false);
+	device_suspend_noirq(dev, pm_transition, true);
+	put_device(dev);
 }
 
 static int dpm_noirq_suspend_devices(pm_message_t state)
 {
 	ktime_t starttime = ktime_get();
-	int error = 0;
+	struct device *dev;
+	int error;
 
 	trace_suspend_resume(TPS("dpm_suspend_noirq"), state.event, true);
-	mutex_lock(&dpm_list_mtx);
+
 	pm_transition = state;
 	async_error = 0;
 
+	mutex_lock(&dpm_list_mtx);
+
+	/*
+	 * Start processing "async" leaf devices upfront so they don't need to
+	 * wait for the "sync" devices they don't depend on.
+	 */
+	list_for_each_entry_reverse(dev, &dpm_late_early_list, power.entry) {
+		dpm_clear_async_state(dev);
+		if (dpm_leaf_device(dev))
+			dpm_async_with_cleanup(dev, async_suspend_noirq);
+	}
+
 	while (!list_empty(&dpm_late_early_list)) {
-		struct device *dev = to_device(dpm_late_early_list.prev);
+		dev = to_device(dpm_late_early_list.prev);
+
+		list_move(&dev->power.entry, &dpm_noirq_list);
+
+		if (dpm_async_fn(dev, async_suspend_noirq))
+			continue;
 
 		get_device(dev);
+
 		mutex_unlock(&dpm_list_mtx);
 
-		error = device_suspend_noirq(dev);
+		device_suspend_noirq(dev, state, false);
 
-		mutex_lock(&dpm_list_mtx);
-		if (error) {
-			pm_dev_err(dev, state, " noirq", error);
-			dpm_save_failed_dev(dev_name(dev));
-			put_device(dev);
-			break;
-		}
-		if (!list_empty(&dev->power.entry))
-			list_move(&dev->power.entry, &dpm_noirq_list);
 		put_device(dev);
 
-		if (async_error)
+		mutex_lock(&dpm_list_mtx);
+
+		if (READ_ONCE(async_error)) {
+			dpm_async_suspend_complete_all(&dpm_late_early_list);
+			/*
+			 * Move all devices to the target list to resume them
+			 * properly.
+			 */
+			list_splice_init(&dpm_late_early_list, &dpm_noirq_list);
 			break;
+		}
 	}
+
 	mutex_unlock(&dpm_list_mtx);
+
 	async_synchronize_full();
-	if (!error)
-		error = async_error;
 
-	if (error) {
-		suspend_stats.failed_suspend_noirq++;
+	error = READ_ONCE(async_error);
+	if (error)
 		dpm_save_failed_step(SUSPEND_SUSPEND_NOIRQ);
-	}
+
 	dpm_show_time(starttime, state, error, "noirq");
 	trace_suspend_resume(TPS("dpm_suspend_noirq"), state.event, false);
 	return error;
@@ -1447,8 +1589,6 @@ int dpm_suspend_noirq(pm_message_t state)
 {
 	int ret;
 
-	cpuidle_pause();
-
 	device_wakeup_arm_wake_irqs();
 	suspend_device_irqs();
 
@@ -1468,79 +1608,70 @@ static void dpm_propagate_wakeup_to_parent(struct device *dev)
 
 	spin_lock_irq(&parent->power.lock);
 
-	if (dev->power.wakeup_path && !parent->power.ignore_children)
+	if (device_wakeup_path(dev) && !parent->power.ignore_children)
 		parent->power.wakeup_path = true;
 
 	spin_unlock_irq(&parent->power.lock);
 }
 
-static pm_callback_t dpm_subsys_suspend_late_cb(struct device *dev,
-						pm_message_t state,
-						const char **info_p)
-{
-	pm_callback_t callback;
-	const char *info;
-
-	if (dev->pm_domain) {
-		info = "late power domain ";
-		callback = pm_late_early_op(&dev->pm_domain->ops, state);
-	} else if (dev->type && dev->type->pm) {
-		info = "late type ";
-		callback = pm_late_early_op(dev->type->pm, state);
-	} else if (dev->class && dev->class->pm) {
-		info = "late class ";
-		callback = pm_late_early_op(dev->class->pm, state);
-	} else if (dev->bus && dev->bus->pm) {
-		info = "late bus ";
-		callback = pm_late_early_op(dev->bus->pm, state);
-	} else {
-		return NULL;
-	}
-
-	if (info_p)
-		*info_p = info;
-
-	return callback;
-}
+static void async_suspend_late(void *data, async_cookie_t cookie);
 
 /**
- * __device_suspend_late - Execute a "late suspend" callback for given device.
+ * device_suspend_late - Execute a "late suspend" callback for given device.
  * @dev: Device to handle.
  * @state: PM transition of the system being carried out.
  * @async: If true, the device is being suspended asynchronously.
  *
  * Runtime PM is disabled for @dev while this function is being executed.
  */
-static int __device_suspend_late(struct device *dev, pm_message_t state, bool async)
+static void device_suspend_late(struct device *dev, pm_message_t state, bool async)
 {
-	pm_callback_t callback;
-	const char *info;
+	pm_callback_t callback = NULL;
+	const char *info = NULL;
 	int error = 0;
 
 	TRACE_DEVICE(dev);
 	TRACE_SUSPEND(0);
 
-	__pm_runtime_disable(dev, false);
-
 	dpm_wait_for_subordinate(dev, async);
 
-	if (async_error)
+	if (READ_ONCE(async_error))
 		goto Complete;
 
 	if (pm_wakeup_pending()) {
-		async_error = -EBUSY;
+		WRITE_ONCE(async_error, -EBUSY);
 		goto Complete;
 	}
 
-	if (dev->power.syscore || dev->power.direct_complete)
+	if (dev->power.direct_complete)
 		goto Complete;
 
-	callback = dpm_subsys_suspend_late_cb(dev, state, &info);
+	/*
+	 * Disable runtime PM for the device without checking if there is a
+	 * pending resume request for it.
+	 */
+	__pm_runtime_disable(dev, false);
+
+	if (dev->power.syscore)
+		goto Skip;
+
+	if (dev->pm_domain) {
+		info = "late power domain ";
+		callback = pm_late_early_op(&dev->pm_domain->ops, state);
+	} else if (dev->type && dev->type->pm) {
+		info = "late type ";
+		callback = pm_late_early_op(dev->type->pm, state);
+	} else if (dev->class && dev->class->pm) {
+		info = "late class ";
+		callback = pm_late_early_op(dev->class->pm, state);
+	} else if (dev->bus && dev->bus->pm) {
+		info = "late bus ";
+		callback = pm_late_early_op(dev->bus->pm, state);
+	}
 	if (callback)
 		goto Run;
 
-	if (dev_pm_smart_suspend_and_suspended(dev) &&
-	    !dpm_subsys_suspend_noirq_cb(dev, state, NULL))
+	if (dev_pm_skip_suspend(dev))
 		goto Skip;
 
 	if (dev->driver && dev->driver->pm) {
@@ -1551,7 +1682,10 @@ static int __device_suspend_late(struct device *dev, pm_message_t state, bool as
 Run:
 	error = dpm_run_callback(callback, dev, state, info);
 	if (error) {
-		async_error = error;
+		WRITE_ONCE(async_error, error);
+		dpm_save_failed_dev(dev_name(dev));
+		pm_dev_err(dev, state, async ? " async late" : " late", error);
+		pm_runtime_enable(dev);
 		goto Complete;
 	}
 	dpm_propagate_wakeup_to_parent(dev);
@@ -1562,28 +1696,19 @@ Skip:
 Complete:
 	TRACE_SUSPEND(error);
 	complete_all(&dev->power.completion);
-	return error;
-}
 
-static void async_suspend_late(void *data, async_cookie_t cookie)
-{
-	struct device *dev = (struct device *)data;
-	int error;
+	if (error || READ_ONCE(async_error))
+		return;
 
-	error = __device_suspend_late(dev, pm_transition, true);
-	if (error) {
-		dpm_save_failed_dev(dev_name(dev));
-		pm_dev_err(dev, pm_transition, " async", error);
-	}
-	put_device(dev);
+	dpm_async_suspend_superior(dev, async_suspend_late);
 }
 
-static int device_suspend_late(struct device *dev)
+static void async_suspend_late(void *data, async_cookie_t cookie)
 {
-	if (dpm_async_fn(dev, async_suspend_late))
-		return 0;
+	struct device *dev = data;
 
-	return __device_suspend_late(dev, pm_transition, false);
+	device_suspend_late(dev, pm_transition, true);
+	put_device(dev);
 }
 
 /**
@@ -1593,42 +1718,63 @@ static int device_suspend_late(struct device *dev)
 int dpm_suspend_late(pm_message_t state)
 {
 	ktime_t starttime = ktime_get();
-	int error = 0;
+	struct device *dev;
+	int error;
 
 	trace_suspend_resume(TPS("dpm_suspend_late"), state.event, true);
-	mutex_lock(&dpm_list_mtx);
+
 	pm_transition = state;
 	async_error = 0;
 
+	wake_up_all_idle_cpus();
+
+	mutex_lock(&dpm_list_mtx);
+
+	/*
+	 * Start processing "async" leaf devices upfront so they don't need to
+	 * wait for the "sync" devices they don't depend on.
+	 */
+	list_for_each_entry_reverse(dev, &dpm_suspended_list, power.entry) {
+		dpm_clear_async_state(dev);
+		if (dpm_leaf_device(dev))
+			dpm_async_with_cleanup(dev, async_suspend_late);
+	}
+
 	while (!list_empty(&dpm_suspended_list)) {
-		struct device *dev = to_device(dpm_suspended_list.prev);
+		dev = to_device(dpm_suspended_list.prev);
+
+		list_move(&dev->power.entry, &dpm_late_early_list);
+
+		if (dpm_async_fn(dev, async_suspend_late))
+			continue;
 
 		get_device(dev);
+
 		mutex_unlock(&dpm_list_mtx);
 
-		error = device_suspend_late(dev);
+		device_suspend_late(dev, state, false);
+
+		put_device(dev);
 
 		mutex_lock(&dpm_list_mtx);
-		if (!list_empty(&dev->power.entry))
-			list_move(&dev->power.entry, &dpm_late_early_list);
 
-		if (error) {
-			pm_dev_err(dev, state, " late", error);
-			dpm_save_failed_dev(dev_name(dev));
-			put_device(dev);
+		if (READ_ONCE(async_error)) {
+			dpm_async_suspend_complete_all(&dpm_suspended_list);
+			/*
+			 * Move all devices to the target list to resume them
+			 * properly.
+			 */
+			list_splice_init(&dpm_suspended_list, &dpm_late_early_list);
 			break;
 		}
-		put_device(dev);
-
-		if (async_error)
-			break;
 	}
+
 	mutex_unlock(&dpm_list_mtx);
+
 	async_synchronize_full();
-	if (!error)
-		error = async_error;
+
+	error = READ_ONCE(async_error);
 	if (error) {
-		suspend_stats.failed_suspend_late++;
 		dpm_save_failed_step(SUSPEND_SUSPEND_LATE);
 		dpm_resume_early(resume_event(state));
 	}
@@ -1679,7 +1825,7 @@ static int legacy_suspend(struct device *dev, pm_message_t state,
 	trace_device_pm_callback_start(dev, info, state.event);
 	error = cb(dev, state);
 	trace_device_pm_callback_end(dev, error);
-	suspend_report_result(cb, error);
+	suspend_report_result(dev, cb, error);
 
 	initcall_debug_report(dev, calltime, cb, error);
 
@@ -1699,7 +1845,7 @@ static void dpm_clear_superiors_direct_complete(struct device *dev)
 
 	idx = device_links_read_lock();
 
-	list_for_each_entry_rcu_locked(link, &dev->links.suppliers, c_node) {
+	dev_for_each_link_to_supplier(link, dev) {
 		spin_lock_irq(&link->supplier->power.lock);
 		link->supplier->power.direct_complete = false;
 		spin_unlock_irq(&link->supplier->power.lock);
@@ -1708,13 +1854,15 @@ static void dpm_clear_superiors_direct_complete(struct device *dev)
 	device_links_read_unlock(idx);
 }
 
+static void async_suspend(void *data, async_cookie_t cookie);
+
 /**
- * __device_suspend - Execute "suspend" callbacks for given device.
+ * device_suspend - Execute "suspend" callbacks for given device.
  * @dev: Device to handle.
  * @state: PM transition of the system being carried out.
  * @async: If true, the device is being suspended asynchronously.
  */
-static int __device_suspend(struct device *dev, pm_message_t state, bool async)
+static void device_suspend(struct device *dev, pm_message_t state, bool async)
 {
 	pm_callback_t callback = NULL;
 	const char *info = NULL;
@@ -1726,23 +1874,27 @@ static int __device_suspend(struct device *dev, pm_message_t state, bool async)
 
 	dpm_wait_for_subordinate(dev, async);
 
-	if (async_error) {
+	if (READ_ONCE(async_error)) {
 		dev->power.direct_complete = false;
 		goto Complete;
 	}
 
 	/*
-	 * If a device configured to wake up the system from sleep states
-	 * has been suspended at run time and there's a resume request pending
-	 * for it, this is equivalent to the device signaling wakeup, so the
-	 * system suspend operation should be aborted.
+	 * Wait for possible runtime PM transitions of the device in progress
+	 * to complete and if there's a runtime resume request pending for it,
+	 * resume it before proceeding with invoking the system-wide suspend
+	 * callbacks for it.
+	 *
+	 * If the system-wide suspend callbacks below change the configuration
+	 * of the device, they must disable runtime PM for it or otherwise
+	 * ensure that its runtime-resume callbacks will not be confused by that
+	 * change in case they are invoked going forward.
 	 */
-	if (pm_runtime_barrier(dev) && device_may_wakeup(dev))
-		pm_wakeup_event(dev, 0);
+	pm_runtime_barrier(dev);
 
 	if (pm_wakeup_pending()) {
 		dev->power.direct_complete = false;
-		async_error = -EBUSY;
+		WRITE_ONCE(async_error, -EBUSY);
 		goto Complete;
 	}
 
@@ -1750,7 +1902,7 @@ static int __device_suspend(struct device *dev, pm_message_t state, bool async)
 		goto Complete;
 
 	/* Avoid direct_complete to let wakeup_path propagate. */
-	if (device_may_wakeup(dev) || dev->power.wakeup_path)
+	if (device_may_wakeup(dev) || device_wakeup_path(dev))
 		dev->power.direct_complete = false;
 
 	if (dev->power.direct_complete) {
@@ -1758,6 +1910,7 @@ static int __device_suspend(struct device *dev, pm_message_t state, bool async)
 			pm_runtime_disable(dev);
 			if (pm_runtime_status_suspended(dev)) {
 				pm_dev_dbg(dev, state, "direct-complete ");
+				dev->power.is_suspended = true;
 				goto Complete;
 			}
 
@@ -1766,8 +1919,8 @@ static int __device_suspend(struct device *dev, pm_message_t state, bool async)
 		dev->power.direct_complete = false;
 	}
 
-	dev->power.may_skip_resume = false;
-	dev->power.must_resume = false;
+	dev->power.may_skip_resume = true;
+	dev->power.must_resume = !dev_pm_test_driver_flags(dev, DPM_FLAG_MAY_SKIP_RESUME);
 
 	dpm_watchdog_set(&wd, dev);
 	device_lock(dev);
@@ -1824,34 +1977,27 @@ static int __device_suspend(struct device *dev, pm_message_t state, bool async)
 	dpm_watchdog_clear(&wd);
 
  Complete:
-	if (error)
-		async_error = error;
+	if (error) {
+		WRITE_ONCE(async_error, error);
+		dpm_save_failed_dev(dev_name(dev));
+		pm_dev_err(dev, state, async ? " async" : "", error);
+	}
 
 	complete_all(&dev->power.completion);
 	TRACE_SUSPEND(error);
-	return error;
-}
 
-static void async_suspend(void *data, async_cookie_t cookie)
-{
-	struct device *dev = (struct device *)data;
-	int error;
-
-	error = __device_suspend(dev, pm_transition, true);
-	if (error) {
-		dpm_save_failed_dev(dev_name(dev));
-		pm_dev_err(dev, pm_transition, " async", error);
-	}
+	if (error || READ_ONCE(async_error))
+		return;
 
-	put_device(dev);
+	dpm_async_suspend_superior(dev, async_suspend);
 }
 
-static int device_suspend(struct device *dev)
+static void async_suspend(void *data, async_cookie_t cookie)
 {
-	if (dpm_async_fn(dev, async_suspend))
-		return 0;
+	struct device *dev = data;
 
-	return __device_suspend(dev, pm_transition, false);
+	device_suspend(dev, pm_transition, true);
+	put_device(dev);
 }
 
 /**
@@ -1861,7 +2007,8 @@ static int device_suspend(struct device *dev)
 int dpm_suspend(pm_message_t state)
 {
 	ktime_t starttime = ktime_get();
-	int error = 0;
+	struct device *dev;
+	int error;
 
 	trace_suspend_resume(TPS("dpm_suspend"), state.event, true);
 	might_sleep();
@@ -1869,43 +2016,103 @@ int dpm_suspend(pm_message_t state)
 	devfreq_suspend();
 	cpufreq_suspend();
 
-	mutex_lock(&dpm_list_mtx);
 	pm_transition = state;
 	async_error = 0;
+
+	mutex_lock(&dpm_list_mtx);
+
+	/*
+	 * Start processing "async" leaf devices upfront so they don't need to
+	 * wait for the "sync" devices they don't depend on.
+	 */
+	list_for_each_entry_reverse(dev, &dpm_prepared_list, power.entry) {
+		dpm_clear_async_state(dev);
+		if (dpm_leaf_device(dev))
+			dpm_async_with_cleanup(dev, async_suspend);
+	}
+
 	while (!list_empty(&dpm_prepared_list)) {
-		struct device *dev = to_device(dpm_prepared_list.prev);
+		dev = to_device(dpm_prepared_list.prev);
+
+		list_move(&dev->power.entry, &dpm_suspended_list);
+
+		if (dpm_async_fn(dev, async_suspend))
+			continue;
 
 		get_device(dev);
+
 		mutex_unlock(&dpm_list_mtx);
 
-		error = device_suspend(dev);
+		device_suspend(dev, state, false);
+
+		put_device(dev);
 
 		mutex_lock(&dpm_list_mtx);
-		if (error) {
-			pm_dev_err(dev, state, "", error);
-			dpm_save_failed_dev(dev_name(dev));
-			put_device(dev);
+
+		if (READ_ONCE(async_error)) {
+			dpm_async_suspend_complete_all(&dpm_prepared_list);
+			/*
+			 * Move all devices to the target list to resume them
+			 * properly.
+			 */
+			list_splice_init(&dpm_prepared_list, &dpm_suspended_list);
 			break;
 		}
-		if (!list_empty(&dev->power.entry))
-			list_move(&dev->power.entry, &dpm_suspended_list);
-		put_device(dev);
-		if (async_error)
-			break;
 	}
+
 	mutex_unlock(&dpm_list_mtx);
+
 	async_synchronize_full();
-	if (!error)
-		error = async_error;
-	if (error) {
-		suspend_stats.failed_suspend++;
+
+	error = READ_ONCE(async_error);
+	if (error)
 		dpm_save_failed_step(SUSPEND_SUSPEND);
-	}
+
 	dpm_show_time(starttime, state, error, NULL);
 	trace_suspend_resume(TPS("dpm_suspend"), state.event, false);
 	return error;
 }
 
+static bool device_prepare_smart_suspend(struct device *dev)
+{
+	struct device_link *link;
+	bool ret = true;
+	int idx;
+
+	/*
+	 * The "smart suspend" feature is enabled for devices whose drivers ask
+	 * for it and for devices without PM callbacks.
+	 *
+	 * However, if "smart suspend" is not enabled for the device's parent
+	 * or any of its suppliers that take runtime PM into account, it cannot
+	 * be enabled for the device either.
+	 */
+	if (!dev->power.no_pm_callbacks &&
+	    !dev_pm_test_driver_flags(dev, DPM_FLAG_SMART_SUSPEND))
+		return false;
+
+	if (dev->parent && !dev_pm_smart_suspend(dev->parent) &&
+	    !dev->parent->power.ignore_children && !pm_runtime_blocked(dev->parent))
+		return false;
+
+	idx = device_links_read_lock();
+
+	dev_for_each_link_to_supplier(link, dev) {
+		if (!device_link_test(link, DL_FLAG_PM_RUNTIME))
+			continue;
+
+		if (!dev_pm_smart_suspend(link->supplier) &&
+		    !pm_runtime_blocked(link->supplier)) {
+			ret = false;
+			break;
+		}
+	}
+
+	device_links_read_unlock(idx);
+
+	return ret;
+}
+
 /**
  * device_prepare - Prepare a device for system power transition.
  * @dev: Device to handle.
@@ -1917,11 +2124,9 @@ int dpm_suspend(pm_message_t state)
 static int device_prepare(struct device *dev, pm_message_t state)
 {
 	int (*callback)(struct device *) = NULL;
+	bool smart_suspend;
 	int ret = 0;
 
-	if (dev->power.syscore)
-		return 0;
-
 	/*
 	 * If a device's parent goes into runtime suspend at the wrong time,
 	 * it won't be possible to resume the device.  To prevent this we
@@ -1929,10 +2134,21 @@ static int device_prepare(struct device *dev, pm_message_t state)
 	 * it again during the complete phase.
 	 */
 	pm_runtime_get_noresume(dev);
+	/*
+	 * If runtime PM is disabled for the device at this point and it has
+	 * never been enabled so far, it should not be enabled until this system
+	 * suspend-resume cycle is complete, so prepare to trigger a warning on
+	 * subsequent attempts to enable it.
+	 */
+	smart_suspend = !pm_runtime_block_if_disabled(dev);
+
+	if (dev->power.syscore)
+		return 0;
 
 	device_lock(dev);
 
 	dev->power.wakeup_path = false;
+	dev->power.out_band_wakeup = false;
 
 	if (dev->power.no_pm_callbacks)
 		goto unlock;
@@ -1956,10 +2172,17 @@ unlock:
 	device_unlock(dev);
 
 	if (ret < 0) {
-		suspend_report_result(callback, ret);
+		suspend_report_result(dev, callback, ret);
 		pm_runtime_put(dev);
 		return ret;
 	}
+	/* Do not enable "smart suspend" for devices with disabled runtime PM. */
+	if (smart_suspend)
+		smart_suspend = device_prepare_smart_suspend(dev);
+
+	spin_lock_irq(&dev->power.lock);
+
+	dev->power.smart_suspend = smart_suspend;
 	/*
 	 * A positive return value from ->prepare() means "this device appears
 	 * to be runtime-suspended and its state is fine, so if it really is
@@ -1967,11 +2190,12 @@ unlock:
 	 * will do the same thing with all of its descendants".  This only
 	 * applies to suspend transitions, however.
 	 */
-	spin_lock_irq(&dev->power.lock);
 	dev->power.direct_complete = state.event == PM_EVENT_SUSPEND &&
 		(ret > 0 || dev->power.no_pm_callbacks) &&
-		!dev_pm_test_driver_flags(dev, DPM_FLAG_NEVER_SKIP);
+		!dev_pm_test_driver_flags(dev, DPM_FLAG_NO_DIRECT_COMPLETE);
+
 	spin_unlock_irq(&dev->power.lock);
+
 	return 0;
 }
 
@@ -1986,7 +2210,6 @@ int dpm_prepare(pm_message_t state)
 	int error = 0;
 
 	trace_suspend_resume(TPS("dpm_prepare"), state.event, true);
-	might_sleep();
 
 	/*
 	 * Give a chance for the known devices to complete their probes, before
@@ -2003,10 +2226,11 @@ int dpm_prepare(pm_message_t state)
 	device_block_probing();
 
 	mutex_lock(&dpm_list_mtx);
-	while (!list_empty(&dpm_list)) {
+	while (!list_empty(&dpm_list) && !error) {
 		struct device *dev = to_device(dpm_list.next);
 
 		get_device(dev);
+
 		mutex_unlock(&dpm_list_mtx);
 
 		trace_device_pm_callback_start(dev, "", state.event);
@@ -2014,21 +2238,23 @@ int dpm_prepare(pm_message_t state)
 		trace_device_pm_callback_end(dev, error);
 
 		mutex_lock(&dpm_list_mtx);
-		if (error) {
-			if (error == -EAGAIN) {
-				put_device(dev);
-				error = 0;
-				continue;
-			}
-			pr_info("Device %s not prepared for power transition: code %d\n",
-				dev_name(dev), error);
-			put_device(dev);
-			break;
+
+		if (!error) {
+			dev->power.is_prepared = true;
+			if (!list_empty(&dev->power.entry))
+				list_move_tail(&dev->power.entry, &dpm_prepared_list);
+		} else if (error == -EAGAIN) {
+			error = 0;
+		} else {
+			dev_info(dev, "not prepared for power transition: code %d\n",
+				 error);
 		}
-		dev->power.is_prepared = true;
-		if (!list_empty(&dev->power.entry))
-			list_move_tail(&dev->power.entry, &dpm_prepared_list);
+
+		mutex_unlock(&dpm_list_mtx);
+
 		put_device(dev);
+
+		mutex_lock(&dpm_list_mtx);
 	}
 	mutex_unlock(&dpm_list_mtx);
 	trace_suspend_resume(TPS("dpm_prepare"), state.event, false);
@@ -2048,20 +2274,22 @@ int dpm_suspend_start(pm_message_t state)
 	int error;
 
 	error = dpm_prepare(state);
-	if (error) {
-		suspend_stats.failed_prepare++;
+	if (error)
 		dpm_save_failed_step(SUSPEND_PREPARE);
-	} else
+	else {
+		pm_restrict_gfp_mask();
 		error = dpm_suspend(state);
+	}
+
 	dpm_show_time(starttime, state, error, "start");
 	return error;
 }
 EXPORT_SYMBOL_GPL(dpm_suspend_start);
 
-void __suspend_report_result(const char *function, void *fn, int ret)
+void __suspend_report_result(const char *function, struct device *dev, void *fn, int ret)
 {
 	if (ret)
-		pr_err("%s(): %pS returns %d\n", function, fn, ret);
+		dev_err(dev, "%s(): %ps returns %d\n", function, fn, ret);
 }
 EXPORT_SYMBOL_GPL(__suspend_report_result);
 
@@ -2116,7 +2344,9 @@ static bool pm_ops_is_empty(const struct dev_pm_ops *ops)
 
 void device_pm_check_callbacks(struct device *dev)
 {
-	spin_lock_irq(&dev->power.lock);
+	unsigned long flags;
+
+	spin_lock_irqsave(&dev->power.lock, flags);
 	dev->power.no_pm_callbacks =
 		(!dev->bus || (pm_ops_is_empty(dev->bus->pm) &&
 		 !dev->bus->suspend && !dev->bus->resume)) &&
@@ -2125,11 +2355,10 @@ void device_pm_check_callbacks(struct device *dev)
 		(!dev->pm_domain || pm_ops_is_empty(&dev->pm_domain->ops)) &&
 		(!dev->driver || (pm_ops_is_empty(dev->driver->pm) &&
 		 !dev->driver->suspend && !dev->driver->resume));
-	spin_unlock_irq(&dev->power.lock);
+	spin_unlock_irqrestore(&dev->power.lock, flags);
 }
 
-bool dev_pm_smart_suspend_and_suspended(struct device *dev)
+bool dev_pm_skip_suspend(struct device *dev)
 {
-	return dev_pm_test_driver_flags(dev, DPM_FLAG_SMART_SUSPEND) &&
-		pm_runtime_status_suspended(dev);
+	return dev_pm_smart_suspend(dev) && pm_runtime_status_suspended(dev);
 }
diff --git a/drivers/base/power/power.h b/drivers/base/power/power.h
index 54292cdd7808..922ed457db19 100644
--- a/drivers/base/power/power.h
+++ b/drivers/base/power/power.h
@@ -25,8 +25,11 @@ extern u64 pm_runtime_active_time(struct device *dev);
 
 #define WAKE_IRQ_DEDICATED_ALLOCATED	BIT(0)
 #define WAKE_IRQ_DEDICATED_MANAGED	BIT(1)
+#define WAKE_IRQ_DEDICATED_REVERSE	BIT(2)
 #define WAKE_IRQ_DEDICATED_MASK		(WAKE_IRQ_DEDICATED_ALLOCATED | \
-					 WAKE_IRQ_DEDICATED_MANAGED)
+					 WAKE_IRQ_DEDICATED_MANAGED | \
+					 WAKE_IRQ_DEDICATED_REVERSE)
+#define WAKE_IRQ_DEDICATED_ENABLED	BIT(3)
 
 struct wake_irq {
 	struct device *dev;
@@ -39,7 +42,8 @@ extern void dev_pm_arm_wake_irq(struct wake_irq *wirq);
 extern void dev_pm_disarm_wake_irq(struct wake_irq *wirq);
 extern void dev_pm_enable_wake_irq_check(struct device *dev,
 					 bool can_change_status);
-extern void dev_pm_disable_wake_irq_check(struct device *dev);
+extern void dev_pm_disable_wake_irq_check(struct device *dev, bool cond_disable);
+extern void dev_pm_enable_wake_irq_complete(struct device *dev);
 
 #ifdef CONFIG_PM_SLEEP
 
diff --git a/drivers/base/power/qos.c b/drivers/base/power/qos.c
index 8e93167f1783..ff393cba7649 100644
--- a/drivers/base/power/qos.c
+++ b/drivers/base/power/qos.c
@@ -137,6 +137,7 @@ s32 dev_pm_qos_read_value(struct device *dev, enum dev_pm_qos_req_type type)
 
 	return ret;
 }
+EXPORT_SYMBOL_GPL(dev_pm_qos_read_value);
 
 /**
  * apply_constraint - Add/modify/remove device PM QoS request.
@@ -201,7 +202,7 @@ static int dev_pm_qos_constraints_allocate(struct device *dev)
 	if (!qos)
 		return -ENOMEM;
 
-	n = kzalloc(3 * sizeof(*n), GFP_KERNEL);
+	n = kcalloc(3, sizeof(*n), GFP_KERNEL);
 	if (!n) {
 		kfree(qos);
 		return -ENOMEM;
diff --git a/drivers/base/power/runtime-test.c b/drivers/base/power/runtime-test.c
new file mode 100644
index 000000000000..1535ad2b0264
--- /dev/null
+++ b/drivers/base/power/runtime-test.c
@@ -0,0 +1,249 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2025 Google, Inc.
+ */
+
+#include <linux/cleanup.h>
+#include <linux/pm_runtime.h>
+#include <kunit/device.h>
+#include <kunit/test.h>
+
+#define DEVICE_NAME "pm_runtime_test_device"
+
+static void pm_runtime_depth_test(struct kunit *test)
+{
+	struct device *dev = kunit_device_register(test, DEVICE_NAME);
+
+	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, dev);
+
+	pm_runtime_enable(dev);
+
+	KUNIT_EXPECT_TRUE(test, pm_runtime_suspended(dev));
+	KUNIT_EXPECT_EQ(test, 0, pm_runtime_get_sync(dev));
+	KUNIT_EXPECT_TRUE(test, pm_runtime_active(dev));
+	KUNIT_EXPECT_EQ(test, 1, pm_runtime_get_sync(dev)); /* "already active" */
+	KUNIT_EXPECT_EQ(test, 0, pm_runtime_put_sync(dev));
+	KUNIT_EXPECT_EQ(test, 0, pm_runtime_put_sync(dev));
+	KUNIT_EXPECT_TRUE(test, pm_runtime_suspended(dev));
+}
+
+/* Test pm_runtime_put() and friends when already suspended. */
+static void pm_runtime_already_suspended_test(struct kunit *test)
+{
+	struct device *dev = kunit_device_register(test, DEVICE_NAME);
+
+	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, dev);
+
+	pm_runtime_enable(dev);
+	KUNIT_EXPECT_TRUE(test, pm_runtime_suspended(dev));
+
+	pm_runtime_get_noresume(dev);
+	KUNIT_EXPECT_EQ(test, 1, pm_runtime_put_sync(dev));
+
+	KUNIT_EXPECT_EQ(test, 1, pm_runtime_suspend(dev));
+	KUNIT_EXPECT_EQ(test, 1, pm_runtime_autosuspend(dev));
+	KUNIT_EXPECT_EQ(test, 1, pm_request_autosuspend(dev));
+
+	pm_runtime_get_noresume(dev);
+	KUNIT_EXPECT_EQ(test, 1, pm_runtime_put_sync_autosuspend(dev));
+
+	pm_runtime_get_noresume(dev);
+	pm_runtime_put_autosuspend(dev);
+
+	/* Grab 2 refcounts */
+	pm_runtime_get_noresume(dev);
+	pm_runtime_get_noresume(dev);
+	/* The first put() sees usage_count 1 */
+	KUNIT_EXPECT_EQ(test, 0, pm_runtime_put_sync_autosuspend(dev));
+	/* The second put() sees usage_count 0 but tells us "already suspended". */
+	KUNIT_EXPECT_EQ(test, 1, pm_runtime_put_sync_autosuspend(dev));
+
+	/* Should have remained suspended the whole time. */
+	KUNIT_EXPECT_TRUE(test, pm_runtime_suspended(dev));
+}
+
+static void pm_runtime_idle_test(struct kunit *test)
+{
+	struct device *dev = kunit_device_register(test, DEVICE_NAME);
+
+	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, dev);
+
+	pm_runtime_enable(dev);
+
+	KUNIT_EXPECT_TRUE(test, pm_runtime_suspended(dev));
+	KUNIT_EXPECT_EQ(test, 0, pm_runtime_get_sync(dev));
+	KUNIT_EXPECT_TRUE(test, pm_runtime_active(dev));
+	KUNIT_EXPECT_EQ(test, -EAGAIN, pm_runtime_idle(dev));
+	KUNIT_EXPECT_TRUE(test, pm_runtime_active(dev));
+	pm_runtime_put_noidle(dev);
+	KUNIT_EXPECT_TRUE(test, pm_runtime_active(dev));
+	KUNIT_EXPECT_EQ(test, 0, pm_runtime_idle(dev));
+	KUNIT_EXPECT_TRUE(test, pm_runtime_suspended(dev));
+	KUNIT_EXPECT_EQ(test, -EAGAIN, pm_runtime_idle(dev));
+	KUNIT_EXPECT_EQ(test, -EAGAIN, pm_request_idle(dev));
+}
+
+static void pm_runtime_disabled_test(struct kunit *test)
+{
+	struct device *dev = kunit_device_register(test, DEVICE_NAME);
+
+	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, dev);
+
+	/* Never called pm_runtime_enable() */
+	KUNIT_EXPECT_FALSE(test, pm_runtime_enabled(dev));
+
+	/* "disabled" is treated as "active" */
+	KUNIT_EXPECT_TRUE(test, pm_runtime_active(dev));
+	KUNIT_EXPECT_FALSE(test, pm_runtime_suspended(dev));
+
+	/*
+	 * Note: these "fail", but they still acquire/release refcounts, so
+	 * keep them balanced.
+	 */
+	KUNIT_EXPECT_EQ(test, -EACCES, pm_runtime_get(dev));
+	pm_runtime_put(dev);
+
+	KUNIT_EXPECT_EQ(test, -EACCES, pm_runtime_get_sync(dev));
+	KUNIT_EXPECT_EQ(test, -EACCES, pm_runtime_put_sync(dev));
+
+	KUNIT_EXPECT_EQ(test, -EACCES, pm_runtime_get(dev));
+	pm_runtime_put_autosuspend(dev);
+
+	KUNIT_EXPECT_EQ(test, -EACCES, pm_runtime_resume_and_get(dev));
+	KUNIT_EXPECT_EQ(test, -EACCES, pm_runtime_idle(dev));
+	KUNIT_EXPECT_EQ(test, -EACCES, pm_request_idle(dev));
+	KUNIT_EXPECT_EQ(test, -EACCES, pm_request_resume(dev));
+	KUNIT_EXPECT_EQ(test, -EACCES, pm_request_autosuspend(dev));
+	KUNIT_EXPECT_EQ(test, -EACCES, pm_runtime_suspend(dev));
+	KUNIT_EXPECT_EQ(test, -EACCES, pm_runtime_resume(dev));
+	KUNIT_EXPECT_EQ(test, -EACCES, pm_runtime_autosuspend(dev));
+
+	/* Still disabled */
+	KUNIT_EXPECT_TRUE(test, pm_runtime_active(dev));
+	KUNIT_EXPECT_FALSE(test, pm_runtime_enabled(dev));
+}
+
+static void pm_runtime_error_test(struct kunit *test)
+{
+	struct device *dev = kunit_device_register(test, DEVICE_NAME);
+
+	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, dev);
+
+	pm_runtime_enable(dev);
+	KUNIT_EXPECT_TRUE(test, pm_runtime_suspended(dev));
+
+	/* Fake a .runtime_resume() error */
+	dev->power.runtime_error = -EIO;
+
+	/*
+	 * Note: these "fail", but they still acquire/release refcounts, so
+	 * keep them balanced.
+	 */
+	KUNIT_EXPECT_EQ(test, -EINVAL, pm_runtime_get(dev));
+	pm_runtime_put(dev);
+
+	KUNIT_EXPECT_EQ(test, -EINVAL, pm_runtime_get_sync(dev));
+	KUNIT_EXPECT_EQ(test, -EINVAL, pm_runtime_put_sync(dev));
+
+	KUNIT_EXPECT_EQ(test, -EINVAL, pm_runtime_get(dev));
+	pm_runtime_put_autosuspend(dev);
+
+	KUNIT_EXPECT_EQ(test, -EINVAL, pm_runtime_get(dev));
+	KUNIT_EXPECT_EQ(test, -EINVAL, pm_runtime_put_sync_autosuspend(dev));
+
+	KUNIT_EXPECT_EQ(test, -EINVAL, pm_runtime_resume_and_get(dev));
+	KUNIT_EXPECT_EQ(test, -EINVAL, pm_runtime_idle(dev));
+	KUNIT_EXPECT_EQ(test, -EINVAL, pm_request_idle(dev));
+	KUNIT_EXPECT_EQ(test, -EINVAL, pm_request_resume(dev));
+	KUNIT_EXPECT_EQ(test, -EINVAL, pm_request_autosuspend(dev));
+	KUNIT_EXPECT_EQ(test, -EINVAL, pm_runtime_suspend(dev));
+	KUNIT_EXPECT_EQ(test, -EINVAL, pm_runtime_resume(dev));
+	KUNIT_EXPECT_EQ(test, -EINVAL, pm_runtime_autosuspend(dev));
+
+	/* Error is still pending */
+	KUNIT_EXPECT_TRUE(test, pm_runtime_suspended(dev));
+	KUNIT_EXPECT_EQ(test, -EIO, dev->power.runtime_error);
+	/* Clear error */
+	KUNIT_EXPECT_EQ(test, 0, pm_runtime_set_suspended(dev));
+	KUNIT_EXPECT_EQ(test, 0, dev->power.runtime_error);
+	/* Still suspended */
+	KUNIT_EXPECT_TRUE(test, pm_runtime_suspended(dev));
+
+	KUNIT_EXPECT_EQ(test, 0, pm_runtime_get(dev));
+	pm_runtime_barrier(dev);
+	pm_runtime_put(dev);
+	pm_runtime_suspend(dev); /* flush the put(), to suspend */
+	KUNIT_EXPECT_TRUE(test, pm_runtime_suspended(dev));
+
+	KUNIT_EXPECT_EQ(test, 0, pm_runtime_get_sync(dev));
+	KUNIT_EXPECT_EQ(test, 0, pm_runtime_put_sync(dev));
+
+	KUNIT_EXPECT_EQ(test, 0, pm_runtime_get_sync(dev));
+	pm_runtime_put_autosuspend(dev);
+
+	KUNIT_EXPECT_EQ(test, 0, pm_runtime_resume_and_get(dev));
+
+	/*
+	 * The following should all return -EAGAIN (usage is non-zero) or 1
+	 * (already resumed).
+	 */
+	KUNIT_EXPECT_EQ(test, -EAGAIN, pm_runtime_idle(dev));
+	KUNIT_EXPECT_EQ(test, -EAGAIN, pm_request_idle(dev));
+	KUNIT_EXPECT_EQ(test, 1, pm_request_resume(dev));
+	KUNIT_EXPECT_EQ(test, -EAGAIN, pm_request_autosuspend(dev));
+	KUNIT_EXPECT_EQ(test, -EAGAIN, pm_runtime_suspend(dev));
+	KUNIT_EXPECT_EQ(test, 1, pm_runtime_resume(dev));
+	KUNIT_EXPECT_EQ(test, -EAGAIN, pm_runtime_autosuspend(dev));
+
+	KUNIT_EXPECT_EQ(test, 0, pm_runtime_put_sync(dev));
+
+	/* Suspended again */
+	KUNIT_EXPECT_TRUE(test, pm_runtime_suspended(dev));
+}
+
+/*
+ * Explore a typical probe() sequence in which a device marks itself powered,
+ * but doesn't hold any runtime PM reference, so it suspends as soon as it goes
+ * idle.
+ */
+static void pm_runtime_probe_active_test(struct kunit *test)
+{
+	struct device *dev = kunit_device_register(test, DEVICE_NAME);
+
+	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, dev);
+
+	KUNIT_EXPECT_TRUE(test, pm_runtime_status_suspended(dev));
+
+	KUNIT_EXPECT_EQ(test, 0, pm_runtime_set_active(dev));
+	KUNIT_EXPECT_TRUE(test, pm_runtime_active(dev));
+
+	pm_runtime_enable(dev);
+	KUNIT_EXPECT_TRUE(test, pm_runtime_active(dev));
+
+	/* Nothing to flush. We stay active. */
+	pm_runtime_barrier(dev);
+	KUNIT_EXPECT_TRUE(test, pm_runtime_active(dev));
+
+	/* Ask for idle? Now we suspend. */
+	KUNIT_EXPECT_EQ(test, 0, pm_runtime_idle(dev));
+	KUNIT_EXPECT_TRUE(test, pm_runtime_suspended(dev));
+}
+
+static struct kunit_case pm_runtime_test_cases[] = {
+	KUNIT_CASE(pm_runtime_depth_test),
+	KUNIT_CASE(pm_runtime_already_suspended_test),
+	KUNIT_CASE(pm_runtime_idle_test),
+	KUNIT_CASE(pm_runtime_disabled_test),
+	KUNIT_CASE(pm_runtime_error_test),
+	KUNIT_CASE(pm_runtime_probe_active_test),
+	{}
+};
+
+static struct kunit_suite pm_runtime_test_suite = {
+	.name = "pm_runtime_test_cases",
+	.test_cases = pm_runtime_test_cases,
+};
+
+kunit_test_suite(pm_runtime_test_suite);
+MODULE_DESCRIPTION("Runtime power management unit test suite");
+MODULE_LICENSE("GPL");
diff --git a/drivers/base/power/runtime.c b/drivers/base/power/runtime.c
index 99c7da112c95..84676cc24221 100644
--- a/drivers/base/power/runtime.c
+++ b/drivers/base/power/runtime.c
@@ -11,6 +11,7 @@
 #include <linux/export.h>
 #include <linux/pm_runtime.h>
 #include <linux/pm_wakeirq.h>
+#include <linux/rculist.h>
 #include <trace/events/rpm.h>
 
 #include "../base.h"
@@ -18,10 +19,24 @@
 
 typedef int (*pm_callback_t)(struct device *);
 
+static inline pm_callback_t get_callback_ptr(const void *start, size_t offset)
+{
+	return *(pm_callback_t *)(start + offset);
+}
+
+static pm_callback_t __rpm_get_driver_callback(struct device *dev,
+					       size_t cb_offset)
+{
+	if (dev->driver && dev->driver->pm)
+		return get_callback_ptr(dev->driver->pm, cb_offset);
+
+	return NULL;
+}
+
 static pm_callback_t __rpm_get_callback(struct device *dev, size_t cb_offset)
 {
-	pm_callback_t cb;
 	const struct dev_pm_ops *ops;
+	pm_callback_t cb = NULL;
 
 	if (dev->pm_domain)
 		ops = &dev->pm_domain->ops;
@@ -35,12 +50,10 @@ static pm_callback_t __rpm_get_callback(struct device *dev, size_t cb_offset)
 		ops = NULL;
 
 	if (ops)
-		cb = *(pm_callback_t *)((void *)ops + cb_offset);
-	else
-		cb = NULL;
+		cb = get_callback_ptr(ops, cb_offset);
 
-	if (!cb && dev->driver && dev->driver->pm)
-		cb = *(pm_callback_t *)((void *)dev->driver->pm + cb_offset);
+	if (!cb)
+		cb = __rpm_get_driver_callback(dev, cb_offset);
 
 	return cb;
 }
@@ -77,7 +90,7 @@ static void update_pm_runtime_accounting(struct device *dev)
 	/*
 	 * Because ktime_get_mono_fast_ns() is not monotonic during
 	 * timekeeping updates, ensure that 'now' is after the last saved
-	 * timesptamp.
+	 * timestamp.
 	 */
 	if (now < last)
 		return;
@@ -93,6 +106,7 @@ static void update_pm_runtime_accounting(struct device *dev)
 static void __update_runtime_status(struct device *dev, enum rpm_status status)
 {
 	update_pm_runtime_accounting(dev);
+	trace_rpm_status(dev, status);
 	dev->power.runtime_status = status;
 }
 
@@ -203,7 +217,7 @@ static int dev_memalloc_noio(struct device *dev, void *data)
  *     resume/suspend callback of any one of its ancestors(or the
  *     block device itself), the deadlock may be triggered inside the
  *     memory allocation since it might not complete until the block
- *     device becomes active and the involed page I/O finishes. The
+ *     device becomes active and the involved page I/O finishes. The
  *     situation is pointed out first by Alan Stern. Network device
  *     are involved in iSCSI kind of situation.
  *
@@ -243,8 +257,7 @@ void pm_runtime_set_memalloc_noio(struct device *dev, bool enable)
 		 * flag was set by any one of the descendants.
 		 */
 		if (!dev || (!enable &&
-			     device_for_each_child(dev, NULL,
-						   dev_memalloc_noio)))
+		    device_for_each_child(dev, NULL, dev_memalloc_noio)))
 			break;
 	}
 	mutex_unlock(&dev_hotplug_mutex);
@@ -263,17 +276,15 @@ static int rpm_check_suspend_allowed(struct device *dev)
 		retval = -EINVAL;
 	else if (dev->power.disable_depth > 0)
 		retval = -EACCES;
-	else if (atomic_read(&dev->power.usage_count) > 0)
+	else if (atomic_read(&dev->power.usage_count))
 		retval = -EAGAIN;
-	else if (!dev->power.ignore_children &&
-			atomic_read(&dev->power.child_count))
+	else if (!dev->power.ignore_children && atomic_read(&dev->power.child_count))
 		retval = -EBUSY;
 
 	/* Pending resume requests take precedence over suspends. */
-	else if ((dev->power.deferred_resume
-			&& dev->power.runtime_status == RPM_SUSPENDING)
-	    || (dev->power.request_pending
-			&& dev->power.request == RPM_REQ_RESUME))
+	else if ((dev->power.deferred_resume &&
+	    dev->power.runtime_status == RPM_SUSPENDING) ||
+	    (dev->power.request_pending && dev->power.request == RPM_REQ_RESUME))
 		retval = -EAGAIN;
 	else if (__dev_pm_qos_resume_latency(dev) == 0)
 		retval = -EPERM;
@@ -291,8 +302,7 @@ static int rpm_get_suppliers(struct device *dev)
 				device_links_read_lock_held()) {
 		int retval;
 
-		if (!(link->flags & DL_FLAG_PM_RUNTIME) ||
-		    READ_ONCE(link->status) == DL_STATE_SUPPLIER_UNBIND)
+		if (!device_link_test(link, DL_FLAG_PM_RUNTIME))
 			continue;
 
 		retval = pm_runtime_get_sync(link->supplier);
@@ -306,20 +316,56 @@ static int rpm_get_suppliers(struct device *dev)
 	return 0;
 }
 
-static void rpm_put_suppliers(struct device *dev)
+/**
+ * pm_runtime_release_supplier - Drop references to device link's supplier.
+ * @link: Target device link.
+ *
+ * Drop all runtime PM references associated with @link to its supplier device.
+ */
+void pm_runtime_release_supplier(struct device_link *link)
+{
+	struct device *supplier = link->supplier;
+
+	/*
+	 * The additional power.usage_count check is a safety net in case
+	 * the rpm_active refcount becomes saturated, in which case
+	 * refcount_dec_not_one() would return true forever, but it is not
+	 * strictly necessary.
+	 */
+	while (refcount_dec_not_one(&link->rpm_active) &&
+	       atomic_read(&supplier->power.usage_count) > 0)
+		pm_runtime_put_noidle(supplier);
+}
+
+static void __rpm_put_suppliers(struct device *dev, bool try_to_suspend)
 {
 	struct device_link *link;
 
 	list_for_each_entry_rcu(link, &dev->links.suppliers, c_node,
 				device_links_read_lock_held()) {
-		if (READ_ONCE(link->status) == DL_STATE_SUPPLIER_UNBIND)
-			continue;
-
-		while (refcount_dec_not_one(&link->rpm_active))
-			pm_runtime_put(link->supplier);
+		pm_runtime_release_supplier(link);
+		if (try_to_suspend)
+			pm_request_idle(link->supplier);
 	}
 }
 
+static void rpm_put_suppliers(struct device *dev)
+{
+	__rpm_put_suppliers(dev, true);
+}
+
+static void rpm_suspend_suppliers(struct device *dev)
+{
+	struct device_link *link;
+	int idx = device_links_read_lock();
+
+	list_for_each_entry_rcu(link, &dev->links.suppliers, c_node,
+				device_links_read_lock_held())
+		pm_request_idle(link->supplier);
+
+	device_links_read_unlock(idx);
+}
+
 /**
  * __rpm_callback - Run a given runtime PM callback for a given device.
  * @cb: Runtime PM callback to run.
@@ -328,7 +374,7 @@ static void rpm_put_suppliers(struct device *dev)
 static int __rpm_callback(int (*cb)(struct device *), struct device *dev)
 	__releases(&dev->power.lock) __acquires(&dev->power.lock)
 {
-	int retval, idx;
+	int retval = 0, idx;
 	bool use_links = dev->power.links_count > 0;
 
 	if (dev->power.irq_safe) {
@@ -347,14 +393,17 @@ static int __rpm_callback(int (*cb)(struct device *), struct device *dev)
 			idx = device_links_read_lock();
 
 			retval = rpm_get_suppliers(dev);
-			if (retval)
+			if (retval) {
+				rpm_put_suppliers(dev);
 				goto fail;
+			}
 
 			device_links_read_unlock(idx);
 		}
 	}
 
-	retval = cb(dev);
+	if (cb)
+		retval = cb(dev);
 
 	if (dev->power.irq_safe) {
 		spin_lock(&dev->power.lock);
@@ -366,14 +415,14 @@ static int __rpm_callback(int (*cb)(struct device *), struct device *dev)
 		 *
 		 * Do that if resume fails too.
 		 */
-		if (use_links
-		    && ((dev->power.runtime_status == RPM_SUSPENDING && !retval)
-		    || (dev->power.runtime_status == RPM_RESUMING && retval))) {
+		if (use_links &&
+		    ((dev->power.runtime_status == RPM_SUSPENDING && !retval) ||
+		    (dev->power.runtime_status == RPM_RESUMING && retval))) {
 			idx = device_links_read_lock();
 
- fail:
-			rpm_put_suppliers(dev);
+			__rpm_put_suppliers(dev, false);
 
+fail:
 			device_links_read_unlock(idx);
 		}
 
@@ -384,6 +433,49 @@ static int __rpm_callback(int (*cb)(struct device *), struct device *dev)
 }
 
 /**
+ * rpm_callback - Run a given runtime PM callback for a given device.
+ * @cb: Runtime PM callback to run.
+ * @dev: Device to run the callback for.
+ */
+static int rpm_callback(int (*cb)(struct device *), struct device *dev)
+{
+	int retval;
+
+	if (dev->power.memalloc_noio) {
+		unsigned int noio_flag;
+
+		/*
+		 * Deadlock might be caused if memory allocation with
+		 * GFP_KERNEL happens inside runtime_suspend and
+		 * runtime_resume callbacks of one block device's
+		 * ancestor or the block device itself. Network
+		 * device might be thought as part of iSCSI block
+		 * device, so network device and its ancestor should
+		 * be marked as memalloc_noio too.
+		 */
+		noio_flag = memalloc_noio_save();
+		retval = __rpm_callback(cb, dev);
+		memalloc_noio_restore(noio_flag);
+	} else {
+		retval = __rpm_callback(cb, dev);
+	}
+
+	/*
+	 * Since -EACCES means that runtime PM is disabled for the given device,
+	 * it should not be returned by runtime PM callbacks.  If it is returned
+	 * nevertheless, assume it to be a transient error and convert it to
+	 * -EAGAIN.
+	 */
+	if (retval == -EACCES)
+		retval = -EAGAIN;
+
+	if (retval != -EAGAIN && retval != -EBUSY)
+		dev->power.runtime_error = retval;
+
+	return retval;
+}
+
+/**
  * rpm_idle - Notify device bus type if the device can be suspended.
  * @dev: Device to notify the bus type about.
  * @rpmflags: Flag bits.
@@ -401,11 +493,14 @@ static int rpm_idle(struct device *dev, int rpmflags)
 	int (*callback)(struct device *);
 	int retval;
 
-	trace_rpm_idle_rcuidle(dev, rpmflags);
+	trace_rpm_idle(dev, rpmflags);
 	retval = rpm_check_suspend_allowed(dev);
 	if (retval < 0)
 		;	/* Conditions are wrong. */
 
+	else if ((rpmflags & RPM_GET_PUT) && retval == 1)
+		;	/* put() is allowed in RPM_SUSPENDED */
+
 	/* Idle notifications are allowed only in the RPM_ACTIVE state. */
 	else if (dev->power.runtime_status != RPM_ACTIVE)
 		retval = -EAGAIN;
@@ -421,13 +516,17 @@ static int rpm_idle(struct device *dev, int rpmflags)
 	/* Act as though RPM_NOWAIT is always set. */
 	else if (dev->power.idle_notification)
 		retval = -EINPROGRESS;
+
 	if (retval)
 		goto out;
 
 	/* Pending requests need to be canceled. */
 	dev->power.request = RPM_REQ_NONE;
 
-	if (dev->power.no_callbacks)
+	callback = RPM_GET_CALLBACK(dev, runtime_idle);
+
+	/* If no callback assume success. */
+	if (!callback || dev->power.no_callbacks)
 		goto out;
 
 	/* Carry out an asynchronous or a synchronous idle notification. */
@@ -437,61 +536,33 @@ static int rpm_idle(struct device *dev, int rpmflags)
 			dev->power.request_pending = true;
 			queue_work(pm_wq, &dev->power.work);
 		}
-		trace_rpm_return_int_rcuidle(dev, _THIS_IP_, 0);
+		trace_rpm_return_int(dev, _THIS_IP_, 0);
 		return 0;
 	}
 
 	dev->power.idle_notification = true;
 
-	callback = RPM_GET_CALLBACK(dev, runtime_idle);
+	if (dev->power.irq_safe)
+		spin_unlock(&dev->power.lock);
+	else
+		spin_unlock_irq(&dev->power.lock);
 
-	if (callback)
-		retval = __rpm_callback(callback, dev);
+	retval = callback(dev);
+
+	if (dev->power.irq_safe)
+		spin_lock(&dev->power.lock);
+	else
+		spin_lock_irq(&dev->power.lock);
 
 	dev->power.idle_notification = false;
 	wake_up_all(&dev->power.wait_queue);
 
  out:
-	trace_rpm_return_int_rcuidle(dev, _THIS_IP_, retval);
+	trace_rpm_return_int(dev, _THIS_IP_, retval);
 	return retval ? retval : rpm_suspend(dev, rpmflags | RPM_AUTO);
 }
 
 /**
- * rpm_callback - Run a given runtime PM callback for a given device.
- * @cb: Runtime PM callback to run.
- * @dev: Device to run the callback for.
- */
-static int rpm_callback(int (*cb)(struct device *), struct device *dev)
-{
-	int retval;
-
-	if (!cb)
-		return -ENOSYS;
-
-	if (dev->power.memalloc_noio) {
-		unsigned int noio_flag;
-
-		/*
-		 * Deadlock might be caused if memory allocation with
-		 * GFP_KERNEL happens inside runtime_suspend and
-		 * runtime_resume callbacks of one block device's
-		 * ancestor or the block device itself. Network
-		 * device might be thought as part of iSCSI block
-		 * device, so network device and its ancestor should
-		 * be marked as memalloc_noio too.
-		 */
-		noio_flag = memalloc_noio_save();
-		retval = __rpm_callback(cb, dev);
-		memalloc_noio_restore(noio_flag);
-	} else {
-		retval = __rpm_callback(cb, dev);
-	}
-
-	dev->power.runtime_error = retval;
-	return retval != -EACCES ? retval : -EIO;
-}
-
-/**
  * rpm_suspend - Carry out runtime suspend of given device.
  * @dev: Device to suspend.
  * @rpmflags: Flag bits.
@@ -519,24 +590,22 @@ static int rpm_suspend(struct device *dev, int rpmflags)
 	struct device *parent = NULL;
 	int retval;
 
-	trace_rpm_suspend_rcuidle(dev, rpmflags);
+	trace_rpm_suspend(dev, rpmflags);
 
  repeat:
 	retval = rpm_check_suspend_allowed(dev);
-
 	if (retval < 0)
-		;	/* Conditions are wrong. */
+		goto out;	/* Conditions are wrong. */
 
 	/* Synchronous suspends are not allowed in the RPM_RESUMING state. */
-	else if (dev->power.runtime_status == RPM_RESUMING &&
-	    !(rpmflags & RPM_ASYNC))
+	if (dev->power.runtime_status == RPM_RESUMING && !(rpmflags & RPM_ASYNC))
 		retval = -EAGAIN;
+
 	if (retval)
 		goto out;
 
 	/* If the autosuspend_delay time hasn't expired yet, reschedule. */
-	if ((rpmflags & RPM_AUTO)
-	    && dev->power.runtime_status != RPM_SUSPENDING) {
+	if ((rpmflags & RPM_AUTO) && dev->power.runtime_status != RPM_SUSPENDING) {
 		u64 expires = pm_runtime_autosuspend_expiration(dev);
 
 		if (expires != 0) {
@@ -551,7 +620,7 @@ static int rpm_suspend(struct device *dev, int rpmflags)
 			 * rest.
 			 */
 			if (!(dev->power.timer_expires &&
-					dev->power.timer_expires <= expires)) {
+			    dev->power.timer_expires <= expires)) {
 				/*
 				 * We add a slack of 25% to gather wakeups
 				 * without sacrificing the granularity.
@@ -561,9 +630,9 @@ static int rpm_suspend(struct device *dev, int rpmflags)
 
 				dev->power.timer_expires = expires;
 				hrtimer_start_range_ns(&dev->power.suspend_timer,
-						ns_to_ktime(expires),
-						slack,
-						HRTIMER_MODE_ABS);
+						       ns_to_ktime(expires),
+						       slack,
+						       HRTIMER_MODE_ABS);
 			}
 			dev->power.timer_autosuspends = 1;
 			goto out;
@@ -630,6 +699,8 @@ static int rpm_suspend(struct device *dev, int rpmflags)
 	if (retval)
 		goto fail;
 
+	dev_pm_enable_wake_irq_complete(dev);
+
  no_callback:
 	__update_runtime_status(dev, RPM_SUSPENDED);
 	pm_runtime_deactivate_timer(dev);
@@ -647,8 +718,11 @@ static int rpm_suspend(struct device *dev, int rpmflags)
 		goto out;
 	}
 
+	if (dev->power.irq_safe)
+		goto out;
+
 	/* Maybe the parent is now able to suspend. */
-	if (parent && !parent->power.ignore_children && !dev->power.irq_safe) {
+	if (parent && !parent->power.ignore_children) {
 		spin_unlock(&dev->power.lock);
 
 		spin_lock(&parent->power.lock);
@@ -657,33 +731,38 @@ static int rpm_suspend(struct device *dev, int rpmflags)
 
 		spin_lock(&dev->power.lock);
 	}
+	/* Maybe the suppliers are now able to suspend. */
+	if (dev->power.links_count > 0) {
+		spin_unlock_irq(&dev->power.lock);
+
+		rpm_suspend_suppliers(dev);
+
+		spin_lock_irq(&dev->power.lock);
+	}
 
  out:
-	trace_rpm_return_int_rcuidle(dev, _THIS_IP_, retval);
+	trace_rpm_return_int(dev, _THIS_IP_, retval);
 
 	return retval;
 
  fail:
-	dev_pm_disable_wake_irq_check(dev);
+	dev_pm_disable_wake_irq_check(dev, true);
 	__update_runtime_status(dev, RPM_ACTIVE);
 	dev->power.deferred_resume = false;
 	wake_up_all(&dev->power.wait_queue);
 
-	if (retval == -EAGAIN || retval == -EBUSY) {
-		dev->power.runtime_error = 0;
+	/*
+	 * On transient errors, if the callback routine failed an autosuspend,
+	 * and if the last_busy time has been updated so that there is a new
+	 * autosuspend expiration time, automatically reschedule another
+	 * autosuspend.
+	 */
+	if (!dev->power.runtime_error && (rpmflags & RPM_AUTO) &&
+	    pm_runtime_autosuspend_expiration(dev) != 0)
+		goto repeat;
+
+	pm_runtime_cancel_pending(dev);
 
-		/*
-		 * If the callback routine failed an autosuspend, and
-		 * if the last_busy time has been updated so that there
-		 * is a new autosuspend expiration time, automatically
-		 * reschedule another autosuspend.
-		 */
-		if ((rpmflags & RPM_AUTO) &&
-		    pm_runtime_autosuspend_expiration(dev) != 0)
-			goto repeat;
-	} else {
-		pm_runtime_cancel_pending(dev);
-	}
 	goto out;
 }
 
@@ -711,16 +790,20 @@ static int rpm_resume(struct device *dev, int rpmflags)
 	struct device *parent = NULL;
 	int retval = 0;
 
-	trace_rpm_resume_rcuidle(dev, rpmflags);
+	trace_rpm_resume(dev, rpmflags);
 
  repeat:
-	if (dev->power.runtime_error)
+	if (dev->power.runtime_error) {
 		retval = -EINVAL;
-	else if (dev->power.disable_depth == 1 && dev->power.is_suspended
-	    && dev->power.runtime_status == RPM_ACTIVE)
-		retval = 1;
-	else if (dev->power.disable_depth > 0)
-		retval = -EACCES;
+	} else if (dev->power.disable_depth > 0) {
+		if (dev->power.runtime_status == RPM_ACTIVE &&
+		    dev->power.last_status == RPM_ACTIVE)
+			retval = 1;
+		else if (rpmflags & RPM_TRANSPARENT)
+			goto out;
+		else
+			retval = -EACCES;
+	}
 	if (retval)
 		goto out;
 
@@ -739,15 +822,18 @@ static int rpm_resume(struct device *dev, int rpmflags)
 		goto out;
 	}
 
-	if (dev->power.runtime_status == RPM_RESUMING
-	    || dev->power.runtime_status == RPM_SUSPENDING) {
+	if (dev->power.runtime_status == RPM_RESUMING ||
+	    dev->power.runtime_status == RPM_SUSPENDING) {
 		DEFINE_WAIT(wait);
 
 		if (rpmflags & (RPM_ASYNC | RPM_NOWAIT)) {
-			if (dev->power.runtime_status == RPM_SUSPENDING)
+			if (dev->power.runtime_status == RPM_SUSPENDING) {
 				dev->power.deferred_resume = true;
-			else
+				if (rpmflags & RPM_NOWAIT)
+					retval = -EINPROGRESS;
+			} else {
 				retval = -EINPROGRESS;
+			}
 			goto out;
 		}
 
@@ -764,8 +850,8 @@ static int rpm_resume(struct device *dev, int rpmflags)
 		for (;;) {
 			prepare_to_wait(&dev->power.wait_queue, &wait,
 					TASK_UNINTERRUPTIBLE);
-			if (dev->power.runtime_status != RPM_RESUMING
-			    && dev->power.runtime_status != RPM_SUSPENDING)
+			if (dev->power.runtime_status != RPM_RESUMING &&
+			    dev->power.runtime_status != RPM_SUSPENDING)
 				break;
 
 			spin_unlock_irq(&dev->power.lock);
@@ -785,9 +871,9 @@ static int rpm_resume(struct device *dev, int rpmflags)
 	 */
 	if (dev->power.no_callbacks && !parent && dev->parent) {
 		spin_lock_nested(&dev->parent->power.lock, SINGLE_DEPTH_NESTING);
-		if (dev->parent->power.disable_depth > 0
-		    || dev->parent->power.ignore_children
-		    || dev->parent->power.runtime_status == RPM_ACTIVE) {
+		if (dev->parent->power.disable_depth > 0 ||
+		    dev->parent->power.ignore_children ||
+		    dev->parent->power.runtime_status == RPM_ACTIVE) {
 			atomic_inc(&dev->parent->power.child_count);
 			spin_unlock(&dev->parent->power.lock);
 			retval = 1;
@@ -816,6 +902,7 @@ static int rpm_resume(struct device *dev, int rpmflags)
 		parent = dev->parent;
 		if (dev->power.irq_safe)
 			goto skip_parent;
+
 		spin_unlock(&dev->power.lock);
 
 		pm_runtime_get_noresume(parent);
@@ -825,8 +912,8 @@ static int rpm_resume(struct device *dev, int rpmflags)
 		 * Resume the parent if it has runtime PM enabled and not been
 		 * set to ignore its children.
 		 */
-		if (!parent->power.disable_depth
-		    && !parent->power.ignore_children) {
+		if (!parent->power.disable_depth &&
+		    !parent->power.ignore_children) {
 			rpm_resume(parent, 0);
 			if (parent->power.runtime_status != RPM_ACTIVE)
 				retval = -EBUSY;
@@ -836,6 +923,7 @@ static int rpm_resume(struct device *dev, int rpmflags)
 		spin_lock(&dev->power.lock);
 		if (retval)
 			goto out;
+
 		goto repeat;
 	}
  skip_parent:
@@ -847,7 +935,7 @@ static int rpm_resume(struct device *dev, int rpmflags)
 
 	callback = RPM_GET_CALLBACK(dev, runtime_resume);
 
-	dev_pm_disable_wake_irq_check(dev);
+	dev_pm_disable_wake_irq_check(dev, false);
 	retval = rpm_callback(callback, dev);
 	if (retval) {
 		__update_runtime_status(dev, RPM_SUSPENDED);
@@ -874,7 +962,7 @@ static int rpm_resume(struct device *dev, int rpmflags)
 		spin_lock_irq(&dev->power.lock);
 	}
 
-	trace_rpm_return_int_rcuidle(dev, _THIS_IP_, retval);
+	trace_rpm_return_int(dev, _THIS_IP_, retval);
 
 	return retval;
 }
@@ -923,7 +1011,7 @@ static void pm_runtime_work(struct work_struct *work)
 
 /**
  * pm_suspend_timer_fn - Timer function for pm_schedule_suspend().
- * @data: Device pointer passed by pm_schedule_suspend().
+ * @timer: hrtimer used by pm_schedule_suspend().
  *
  * Check if the time is right and queue a suspend request.
  */
@@ -940,7 +1028,7 @@ static enum hrtimer_restart  pm_suspend_timer_fn(struct hrtimer *timer)
 	 * If 'expires' is after the current time, we've been called
 	 * too early.
 	 */
-	if (expires > 0 && expires < ktime_get_mono_fast_ns()) {
+	if (expires > 0 && expires <= ktime_get_mono_fast_ns()) {
 		dev->power.timer_expires = 0;
 		rpm_suspend(dev, dev->power.timer_autosuspends ?
 		    (RPM_ASYNC | RPM_AUTO) : RPM_ASYNC);
@@ -988,13 +1076,33 @@ int pm_schedule_suspend(struct device *dev, unsigned int delay)
 }
 EXPORT_SYMBOL_GPL(pm_schedule_suspend);
 
+static int rpm_drop_usage_count(struct device *dev)
+{
+	int ret;
+
+	ret = atomic_sub_return(1, &dev->power.usage_count);
+	if (ret >= 0)
+		return ret;
+
+	/*
+	 * Because rpm_resume() does not check the usage counter, it will resume
+	 * the device even if the usage counter is 0 or negative, so it is
+	 * sufficient to increment the usage counter here to reverse the change
+	 * made above.
+	 */
+	atomic_inc(&dev->power.usage_count);
+	dev_warn(dev, "Runtime PM usage count underflow!\n");
+	return -EINVAL;
+}
+
 /**
  * __pm_runtime_idle - Entry point for runtime idle operations.
  * @dev: Device to send idle notification for.
  * @rpmflags: Flag bits.
  *
  * If the RPM_GET_PUT flag is set, decrement the device's usage count and
- * return immediately if it is larger than zero.  Then carry out an idle
+ * return immediately if it is larger than zero (if it becomes negative, log a
+ * warning, increment it, and return an error).  Then carry out an idle
  * notification, either synchronous or asynchronous.
  *
  * This routine may be called in atomic context if the RPM_ASYNC flag is set,
@@ -1006,8 +1114,11 @@ int __pm_runtime_idle(struct device *dev, int rpmflags)
 	int retval;
 
 	if (rpmflags & RPM_GET_PUT) {
-		if (!atomic_dec_and_test(&dev->power.usage_count)) {
-			trace_rpm_usage_rcuidle(dev, rpmflags);
+		retval = rpm_drop_usage_count(dev);
+		if (retval < 0) {
+			return retval;
+		} else if (retval > 0) {
+			trace_rpm_usage(dev, rpmflags);
 			return 0;
 		}
 	}
@@ -1028,7 +1139,8 @@ EXPORT_SYMBOL_GPL(__pm_runtime_idle);
  * @rpmflags: Flag bits.
  *
  * If the RPM_GET_PUT flag is set, decrement the device's usage count and
- * return immediately if it is larger than zero.  Then carry out a suspend,
+ * return immediately if it is larger than zero (if it becomes negative, log a
+ * warning, increment it, and return an error).  Then carry out a suspend,
  * either synchronous or asynchronous.
  *
  * This routine may be called in atomic context if the RPM_ASYNC flag is set,
@@ -1040,8 +1152,11 @@ int __pm_runtime_suspend(struct device *dev, int rpmflags)
 	int retval;
 
 	if (rpmflags & RPM_GET_PUT) {
-		if (!atomic_dec_and_test(&dev->power.usage_count)) {
-			trace_rpm_usage_rcuidle(dev, rpmflags);
+		retval = rpm_drop_usage_count(dev);
+		if (retval < 0) {
+			return retval;
+		} else if (retval > 0) {
+			trace_rpm_usage(dev, rpmflags);
 			return 0;
 		}
 	}
@@ -1087,26 +1202,30 @@ int __pm_runtime_resume(struct device *dev, int rpmflags)
 EXPORT_SYMBOL_GPL(__pm_runtime_resume);
 
 /**
- * pm_runtime_get_if_active - Conditionally bump up the device's usage counter.
+ * pm_runtime_get_conditional - Conditionally bump up device usage counter.
  * @dev: Device to handle.
+ * @ign_usage_count: Whether or not to look at the current usage counter value.
+ *
+ * Return -EINVAL if runtime PM is disabled for @dev.
  *
- * Return -EINVAL if runtime PM is disabled for the device.
+ * Otherwise, if its runtime PM status is %RPM_ACTIVE and (1) @ign_usage_count
+ * is set, or (2) @dev is not ignoring children and its active child count is
+ * nonzero, or (3) the runtime PM usage counter of @dev is not zero, increment
+ * the usage counter of @dev and return 1.
  *
- * Otherwise, if the device's runtime PM status is RPM_ACTIVE and either
- * ign_usage_count is true or the device's usage_count is non-zero, increment
- * the counter and return 1. Otherwise return 0 without changing the counter.
+ * Otherwise, return 0 without changing the usage counter.
  *
- * If ign_usage_count is true, the function can be used to prevent suspending
- * the device when its runtime PM status is RPM_ACTIVE.
+ * If @ign_usage_count is %true, this function can be used to prevent suspending
+ * the device when its runtime PM status is %RPM_ACTIVE.
  *
- * If ign_usage_count is false, the function can be used to prevent suspending
- * the device when both its runtime PM status is RPM_ACTIVE and its usage_count
- * is non-zero.
+ * If @ign_usage_count is %false, this function can be used to prevent
+ * suspending the device when both its runtime PM status is %RPM_ACTIVE and its
+ * runtime PM usage counter is not zero.
  *
- * The caller is resposible for putting the device's usage count when ther
- * return value is greater than zero.
+ * The caller is responsible for decrementing the runtime PM usage counter of
+ * @dev after this function has returned a positive value for it.
  */
-int pm_runtime_get_if_active(struct device *dev, bool ign_usage_count)
+static int pm_runtime_get_conditional(struct device *dev, bool ign_usage_count)
 {
 	unsigned long flags;
 	int retval;
@@ -1116,20 +1235,58 @@ int pm_runtime_get_if_active(struct device *dev, bool ign_usage_count)
 		retval = -EINVAL;
 	} else if (dev->power.runtime_status != RPM_ACTIVE) {
 		retval = 0;
-	} else if (ign_usage_count) {
+	} else if (ign_usage_count || (!dev->power.ignore_children &&
+		   atomic_read(&dev->power.child_count) > 0)) {
 		retval = 1;
 		atomic_inc(&dev->power.usage_count);
 	} else {
 		retval = atomic_inc_not_zero(&dev->power.usage_count);
 	}
-	trace_rpm_usage_rcuidle(dev, 0);
+	trace_rpm_usage(dev, 0);
 	spin_unlock_irqrestore(&dev->power.lock, flags);
 
 	return retval;
 }
+
+/**
+ * pm_runtime_get_if_active - Bump up runtime PM usage counter if the device is
+ *			      in active state
+ * @dev: Target device.
+ *
+ * Increment the runtime PM usage counter of @dev if its runtime PM status is
+ * %RPM_ACTIVE, in which case it returns 1. If the device is in a different
+ * state, 0 is returned. -EINVAL is returned if runtime PM is disabled for the
+ * device, in which case also the usage_count will remain unmodified.
+ */
+int pm_runtime_get_if_active(struct device *dev)
+{
+	return pm_runtime_get_conditional(dev, true);
+}
 EXPORT_SYMBOL_GPL(pm_runtime_get_if_active);
 
 /**
+ * pm_runtime_get_if_in_use - Conditionally bump up runtime PM usage counter.
+ * @dev: Target device.
+ *
+ * Increment the runtime PM usage counter of @dev if its runtime PM status is
+ * %RPM_ACTIVE and its runtime PM usage counter is greater than 0 or it is not
+ * ignoring children and its active child count is nonzero.  1 is returned in
+ * this case.
+ *
+ * If @dev is in a different state or it is not in use (that is, its usage
+ * counter is 0, or it is ignoring children, or its active child count is 0),
+ * 0 is returned.
+ *
+ * -EINVAL is returned if runtime PM is disabled for the device, in which case
+ * also the usage counter of @dev is not updated.
+ */
+int pm_runtime_get_if_in_use(struct device *dev)
+{
+	return pm_runtime_get_conditional(dev, false);
+}
+EXPORT_SYMBOL_GPL(pm_runtime_get_if_in_use);
+
+/**
  * __pm_runtime_set_status - Set runtime PM status of a device.
  * @dev: Device to handle.
  * @status: New runtime PM status of the device.
@@ -1157,12 +1314,13 @@ int __pm_runtime_set_status(struct device *dev, unsigned int status)
 {
 	struct device *parent = dev->parent;
 	bool notify_parent = false;
+	unsigned long flags;
 	int error = 0;
 
 	if (status != RPM_ACTIVE && status != RPM_SUSPENDED)
 		return -EINVAL;
 
-	spin_lock_irq(&dev->power.lock);
+	spin_lock_irqsave(&dev->power.lock, flags);
 
 	/*
 	 * Prevent PM-runtime from being enabled for the device or return an
@@ -1173,7 +1331,7 @@ int __pm_runtime_set_status(struct device *dev, unsigned int status)
 	else
 		error = -EAGAIN;
 
-	spin_unlock_irq(&dev->power.lock);
+	spin_unlock_irqrestore(&dev->power.lock, flags);
 
 	if (error)
 		return error;
@@ -1194,7 +1352,7 @@ int __pm_runtime_set_status(struct device *dev, unsigned int status)
 		device_links_read_unlock(idx);
 	}
 
-	spin_lock_irq(&dev->power.lock);
+	spin_lock_irqsave(&dev->power.lock, flags);
 
 	if (dev->power.runtime_status == status || !parent)
 		goto out_set;
@@ -1210,9 +1368,9 @@ int __pm_runtime_set_status(struct device *dev, unsigned int status)
 		 * not active, has runtime PM enabled and the
 		 * 'power.ignore_children' flag unset.
 		 */
-		if (!parent->power.disable_depth
-		    && !parent->power.ignore_children
-		    && parent->power.runtime_status != RPM_ACTIVE) {
+		if (!parent->power.disable_depth &&
+		    !parent->power.ignore_children &&
+		    parent->power.runtime_status != RPM_ACTIVE) {
 			dev_err(dev, "runtime PM trying to activate child device %s but parent (%s) is not active\n",
 				dev_name(dev),
 				dev_name(parent));
@@ -1235,7 +1393,7 @@ int __pm_runtime_set_status(struct device *dev, unsigned int status)
 		dev->power.runtime_error = 0;
 
  out:
-	spin_unlock_irq(&dev->power.lock);
+	spin_unlock_irqrestore(&dev->power.lock, flags);
 
 	if (notify_parent)
 		pm_request_idle(parent);
@@ -1277,9 +1435,9 @@ static void __pm_runtime_barrier(struct device *dev)
 		dev->power.request_pending = false;
 	}
 
-	if (dev->power.runtime_status == RPM_SUSPENDING
-	    || dev->power.runtime_status == RPM_RESUMING
-	    || dev->power.idle_notification) {
+	if (dev->power.runtime_status == RPM_SUSPENDING ||
+	    dev->power.runtime_status == RPM_RESUMING ||
+	    dev->power.idle_notification) {
 		DEFINE_WAIT(wait);
 
 		/* Suspend, wake-up or idle notification in progress. */
@@ -1309,47 +1467,48 @@ static void __pm_runtime_barrier(struct device *dev)
  * Next, make sure that all pending requests for the device have been flushed
  * from pm_wq and wait for all runtime PM operations involving the device in
  * progress to complete.
- *
- * Return value:
- * 1, if there was a resume request pending and the device had to be woken up,
- * 0, otherwise
  */
-int pm_runtime_barrier(struct device *dev)
+void pm_runtime_barrier(struct device *dev)
 {
-	int retval = 0;
-
 	pm_runtime_get_noresume(dev);
 	spin_lock_irq(&dev->power.lock);
 
 	if (dev->power.request_pending
-	    && dev->power.request == RPM_REQ_RESUME) {
+	    && dev->power.request == RPM_REQ_RESUME)
 		rpm_resume(dev, 0);
-		retval = 1;
-	}
 
 	__pm_runtime_barrier(dev);
 
 	spin_unlock_irq(&dev->power.lock);
 	pm_runtime_put_noidle(dev);
-
-	return retval;
 }
 EXPORT_SYMBOL_GPL(pm_runtime_barrier);
 
-/**
- * __pm_runtime_disable - Disable runtime PM of a device.
- * @dev: Device to handle.
- * @check_resume: If set, check if there's a resume request for the device.
- *
- * Increment power.disable_depth for the device and if it was zero previously,
- * cancel all pending runtime PM requests for the device and wait for all
- * operations in progress to complete.  The device can be either active or
- * suspended after its runtime PM has been disabled.
- *
- * If @check_resume is set and there's a resume request pending when
- * __pm_runtime_disable() is called and power.disable_depth is zero, the
- * function will wake up the device before disabling its runtime PM.
- */
+bool pm_runtime_block_if_disabled(struct device *dev)
+{
+	bool ret;
+
+	spin_lock_irq(&dev->power.lock);
+
+	ret = !pm_runtime_enabled(dev);
+	if (ret && dev->power.last_status == RPM_INVALID)
+		dev->power.last_status = RPM_BLOCKED;
+
+	spin_unlock_irq(&dev->power.lock);
+
+	return ret;
+}
+
+void pm_runtime_unblock(struct device *dev)
+{
+	spin_lock_irq(&dev->power.lock);
+
+	if (dev->power.last_status == RPM_BLOCKED)
+		dev->power.last_status = RPM_INVALID;
+
+	spin_unlock_irq(&dev->power.lock);
+}
+
 void __pm_runtime_disable(struct device *dev, bool check_resume)
 {
 	spin_lock_irq(&dev->power.lock);
@@ -1364,8 +1523,8 @@ void __pm_runtime_disable(struct device *dev, bool check_resume)
 	 * means there probably is some I/O to process and disabling runtime PM
 	 * shouldn't prevent the device from processing the I/O.
 	 */
-	if (check_resume && dev->power.request_pending
-	    && dev->power.request == RPM_REQ_RESUME) {
+	if (check_resume && dev->power.request_pending &&
+	    dev->power.request == RPM_REQ_RESUME) {
 		/*
 		 * Prevent suspends and idle notifications from being carried
 		 * out after we have woken up the device.
@@ -1380,8 +1539,10 @@ void __pm_runtime_disable(struct device *dev, bool check_resume)
 	/* Update time accounting before disabling PM-runtime. */
 	update_pm_runtime_accounting(dev);
 
-	if (!dev->power.disable_depth++)
+	if (!dev->power.disable_depth++) {
 		__pm_runtime_barrier(dev);
+		dev->power.last_status = dev->power.runtime_status;
+	}
 
  out:
 	spin_unlock_irq(&dev->power.lock);
@@ -1398,34 +1559,107 @@ void pm_runtime_enable(struct device *dev)
 
 	spin_lock_irqsave(&dev->power.lock, flags);
 
-	if (dev->power.disable_depth > 0) {
-		dev->power.disable_depth--;
-
-		/* About to enable runtime pm, set accounting_timestamp to now */
-		if (!dev->power.disable_depth)
-			dev->power.accounting_timestamp = ktime_get_mono_fast_ns();
-	} else {
+	if (!dev->power.disable_depth) {
 		dev_warn(dev, "Unbalanced %s!\n", __func__);
+		goto out;
 	}
 
-	WARN(!dev->power.disable_depth &&
-	     dev->power.runtime_status == RPM_SUSPENDED &&
-	     !dev->power.ignore_children &&
-	     atomic_read(&dev->power.child_count) > 0,
-	     "Enabling runtime PM for inactive device (%s) with active children\n",
-	     dev_name(dev));
+	if (--dev->power.disable_depth > 0)
+		goto out;
 
+	if (dev->power.last_status == RPM_BLOCKED) {
+		dev_warn(dev, "Attempt to enable runtime PM when it is blocked\n");
+		dump_stack();
+	}
+	dev->power.last_status = RPM_INVALID;
+	dev->power.accounting_timestamp = ktime_get_mono_fast_ns();
+
+	if (dev->power.runtime_status == RPM_SUSPENDED &&
+	    !dev->power.ignore_children &&
+	    atomic_read(&dev->power.child_count) > 0)
+		dev_warn(dev, "Enabling runtime PM for inactive device with active children\n");
+
+out:
 	spin_unlock_irqrestore(&dev->power.lock, flags);
 }
 EXPORT_SYMBOL_GPL(pm_runtime_enable);
 
+static void pm_runtime_set_suspended_action(void *data)
+{
+	pm_runtime_set_suspended(data);
+}
+
+/**
+ * devm_pm_runtime_set_active_enabled - set_active version of devm_pm_runtime_enable.
+ *
+ * @dev: Device to handle.
+ */
+int devm_pm_runtime_set_active_enabled(struct device *dev)
+{
+	int err;
+
+	err = pm_runtime_set_active(dev);
+	if (err)
+		return err;
+
+	err = devm_add_action_or_reset(dev, pm_runtime_set_suspended_action, dev);
+	if (err)
+		return err;
+
+	return devm_pm_runtime_enable(dev);
+}
+EXPORT_SYMBOL_GPL(devm_pm_runtime_set_active_enabled);
+
+static void pm_runtime_disable_action(void *data)
+{
+	pm_runtime_dont_use_autosuspend(data);
+	pm_runtime_disable(data);
+}
+
+/**
+ * devm_pm_runtime_enable - devres-enabled version of pm_runtime_enable.
+ *
+ * NOTE: this will also handle calling pm_runtime_dont_use_autosuspend() for
+ * you at driver exit time if needed.
+ *
+ * @dev: Device to handle.
+ */
+int devm_pm_runtime_enable(struct device *dev)
+{
+	pm_runtime_enable(dev);
+
+	return devm_add_action_or_reset(dev, pm_runtime_disable_action, dev);
+}
+EXPORT_SYMBOL_GPL(devm_pm_runtime_enable);
+
+static void pm_runtime_put_noidle_action(void *data)
+{
+	pm_runtime_put_noidle(data);
+}
+
+/**
+ * devm_pm_runtime_get_noresume - devres-enabled version of pm_runtime_get_noresume.
+ *
+ * @dev: Device to handle.
+ */
+int devm_pm_runtime_get_noresume(struct device *dev)
+{
+	pm_runtime_get_noresume(dev);
+
+	return devm_add_action_or_reset(dev, pm_runtime_put_noidle_action, dev);
+}
+EXPORT_SYMBOL_GPL(devm_pm_runtime_get_noresume);
+
 /**
  * pm_runtime_forbid - Block runtime PM of a device.
  * @dev: Device to handle.
  *
- * Increase the device's usage count and clear its power.runtime_auto flag,
- * so that it cannot be suspended at run time until pm_runtime_allow() is called
- * for it.
+ * Resume @dev if already suspended and block runtime suspend of @dev in such
+ * a way that it can be unblocked via the /sys/devices/.../power/control
+ * interface, or otherwise by calling pm_runtime_allow().
+ *
+ * Calling this function many times in a row has the same effect as calling it
+ * once.
  */
 void pm_runtime_forbid(struct device *dev)
 {
@@ -1446,19 +1680,28 @@ EXPORT_SYMBOL_GPL(pm_runtime_forbid);
  * pm_runtime_allow - Unblock runtime PM of a device.
  * @dev: Device to handle.
  *
- * Decrease the device's usage count and set its power.runtime_auto flag.
+ * Unblock runtime suspend of @dev after it has been blocked by
+ * pm_runtime_forbid() (for instance, if it has been blocked via the
+ * /sys/devices/.../power/control interface), check if @dev can be
+ * suspended and suspend it in that case.
+ *
+ * Calling this function many times in a row has the same effect as calling it
+ * once.
  */
 void pm_runtime_allow(struct device *dev)
 {
+	int ret;
+
 	spin_lock_irq(&dev->power.lock);
 	if (dev->power.runtime_auto)
 		goto out;
 
 	dev->power.runtime_auto = true;
-	if (atomic_dec_and_test(&dev->power.usage_count))
+	ret = rpm_drop_usage_count(dev);
+	if (ret == 0)
 		rpm_idle(dev, RPM_AUTO | RPM_ASYNC);
-	else
-		trace_rpm_usage_rcuidle(dev, RPM_AUTO | RPM_ASYNC);
+	else if (ret > 0)
+		trace_rpm_usage(dev, RPM_AUTO | RPM_ASYNC);
 
  out:
 	spin_unlock_irq(&dev->power.lock);
@@ -1498,6 +1741,7 @@ void pm_runtime_irq_safe(struct device *dev)
 {
 	if (dev->parent)
 		pm_runtime_get_sync(dev->parent);
+
 	spin_lock_irq(&dev->power.lock);
 	dev->power.irq_safe = 1;
 	spin_unlock_irq(&dev->power.lock);
@@ -1527,7 +1771,7 @@ static void update_autosuspend(struct device *dev, int old_delay, int old_use)
 			atomic_inc(&dev->power.usage_count);
 			rpm_resume(dev, 0);
 		} else {
-			trace_rpm_usage_rcuidle(dev, 0);
+			trace_rpm_usage(dev, 0);
 		}
 	}
 
@@ -1593,6 +1837,7 @@ EXPORT_SYMBOL_GPL(__pm_runtime_use_autosuspend);
 void pm_runtime_init(struct device *dev)
 {
 	dev->power.runtime_status = RPM_SUSPENDED;
+	dev->power.last_status = RPM_INVALID;
 	dev->power.idle_notification = false;
 
 	dev->power.disable_depth = 1;
@@ -1607,11 +1852,12 @@ void pm_runtime_init(struct device *dev)
 	dev->power.request_pending = false;
 	dev->power.request = RPM_REQ_NONE;
 	dev->power.deferred_resume = false;
+	dev->power.needs_force_resume = false;
 	INIT_WORK(&dev->power.work, pm_runtime_work);
 
 	dev->power.timer_expires = 0;
-	hrtimer_init(&dev->power.suspend_timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
-	dev->power.suspend_timer.function = pm_suspend_timer_fn;
+	hrtimer_setup(&dev->power.suspend_timer, pm_suspend_timer_fn, CLOCK_MONOTONIC,
+		      HRTIMER_MODE_ABS);
 
 	init_waitqueue_head(&dev->power.wait_queue);
 }
@@ -1633,6 +1879,11 @@ void pm_runtime_reinit(struct device *dev)
 				pm_runtime_put(dev->parent);
 		}
 	}
+	/*
+	 * Clear power.needs_force_resume in case it has been set by
+	 * pm_runtime_force_suspend() invoked from a driver remove callback.
+	 */
+	dev->power.needs_force_resume = false;
 }
 
 /**
@@ -1646,42 +1897,6 @@ void pm_runtime_remove(struct device *dev)
 }
 
 /**
- * pm_runtime_clean_up_links - Prepare links to consumers for driver removal.
- * @dev: Device whose driver is going to be removed.
- *
- * Check links from this device to any consumers and if any of them have active
- * runtime PM references to the device, drop the usage counter of the device
- * (as many times as needed).
- *
- * Links with the DL_FLAG_MANAGED flag unset are ignored.
- *
- * Since the device is guaranteed to be runtime-active at the point this is
- * called, nothing else needs to be done here.
- *
- * Moreover, this is called after device_links_busy() has returned 'false', so
- * the status of each link is guaranteed to be DL_STATE_SUPPLIER_UNBIND and
- * therefore rpm_active can't be manipulated concurrently.
- */
-void pm_runtime_clean_up_links(struct device *dev)
-{
-	struct device_link *link;
-	int idx;
-
-	idx = device_links_read_lock();
-
-	list_for_each_entry_rcu(link, &dev->links.consumers, s_node,
-				device_links_read_lock_held()) {
-		if (!(link->flags & DL_FLAG_MANAGED))
-			continue;
-
-		while (refcount_dec_not_one(&link->rpm_active))
-			pm_runtime_put_noidle(dev);
-	}
-
-	device_links_read_unlock(idx);
-}
-
-/**
  * pm_runtime_get_suppliers - Resume and reference-count supplier devices.
  * @dev: Consumer device.
  */
@@ -1692,11 +1907,9 @@ void pm_runtime_get_suppliers(struct device *dev)
 
 	idx = device_links_read_lock();
 
-	list_for_each_entry_rcu(link, &dev->links.suppliers, c_node,
-				device_links_read_lock_held())
-		if (link->flags & DL_FLAG_PM_RUNTIME) {
+	dev_for_each_link_to_supplier(link, dev)
+		if (device_link_test(link, DL_FLAG_PM_RUNTIME)) {
 			link->supplier_preactivated = true;
-			refcount_inc(&link->rpm_active);
 			pm_runtime_get_sync(link->supplier);
 		}
 
@@ -1718,8 +1931,7 @@ void pm_runtime_put_suppliers(struct device *dev)
 				device_links_read_lock_held())
 		if (link->supplier_preactivated) {
 			link->supplier_preactivated = false;
-			if (refcount_dec_not_one(&link->rpm_active))
-				pm_runtime_put(link->supplier);
+			pm_runtime_put(link->supplier);
 		}
 
 	device_links_read_unlock(idx);
@@ -1732,7 +1944,7 @@ void pm_runtime_new_link(struct device *dev)
 	spin_unlock_irq(&dev->power.lock);
 }
 
-void pm_runtime_drop_link(struct device *dev)
+static void pm_runtime_drop_link_count(struct device *dev)
 {
 	spin_lock_irq(&dev->power.lock);
 	WARN_ON(dev->power.links_count == 0);
@@ -1740,13 +1952,41 @@ void pm_runtime_drop_link(struct device *dev)
 	spin_unlock_irq(&dev->power.lock);
 }
 
-static bool pm_runtime_need_not_resume(struct device *dev)
+/**
+ * pm_runtime_drop_link - Prepare for device link removal.
+ * @link: Device link going away.
+ *
+ * Drop the link count of the consumer end of @link and decrement the supplier
+ * device's runtime PM usage counter as many times as needed to drop all of the
+ * PM runtime reference to it from the consumer.
+ */
+void pm_runtime_drop_link(struct device_link *link)
 {
-	return atomic_read(&dev->power.usage_count) <= 1 &&
-		(atomic_read(&dev->power.child_count) == 0 ||
-		 dev->power.ignore_children);
+	if (!device_link_test(link, DL_FLAG_PM_RUNTIME))
+		return;
+
+	pm_runtime_drop_link_count(link->consumer);
+	pm_runtime_release_supplier(link);
+	pm_request_idle(link->supplier);
 }
 
+static pm_callback_t get_callback(struct device *dev, size_t cb_offset)
+{
+	/*
+	 * Setting power.strict_midlayer means that the middle layer
+	 * code does not want its runtime PM callbacks to be invoked via
+	 * pm_runtime_force_suspend() and pm_runtime_force_resume(), so
+	 * return a direct pointer to the driver callback in that case.
+	 */
+	if (dev_pm_strict_midlayer_is_set(dev))
+		return __rpm_get_driver_callback(dev, cb_offset);
+
+	return __rpm_get_callback(dev, cb_offset);
+}
+
+#define GET_CALLBACK(dev, callback) \
+		get_callback(dev, offsetof(struct dev_pm_ops, callback))
+
 /**
  * pm_runtime_force_suspend - Force a device into suspend state if needed.
  * @dev: Device to suspend.
@@ -1770,71 +2010,106 @@ int pm_runtime_force_suspend(struct device *dev)
 	int ret;
 
 	pm_runtime_disable(dev);
-	if (pm_runtime_status_suspended(dev))
+	if (pm_runtime_status_suspended(dev) || dev->power.needs_force_resume)
 		return 0;
 
-	callback = RPM_GET_CALLBACK(dev, runtime_suspend);
+	callback = GET_CALLBACK(dev, runtime_suspend);
 
+	dev_pm_enable_wake_irq_check(dev, true);
 	ret = callback ? callback(dev) : 0;
 	if (ret)
 		goto err;
 
+	dev_pm_enable_wake_irq_complete(dev);
+
 	/*
 	 * If the device can stay in suspend after the system-wide transition
 	 * to the working state that will follow, drop the children counter of
-	 * its parent, but set its status to RPM_SUSPENDED anyway in case this
-	 * function will be called again for it in the meantime.
+	 * its parent and the usage counters of its suppliers.  Otherwise, set
+	 * power.needs_force_resume to let pm_runtime_force_resume() know that
+	 * the device needs to be taken care of and to prevent this function
+	 * from handling the device again in case the device is passed to it
+	 * once more subsequently.
 	 */
 	if (pm_runtime_need_not_resume(dev))
 		pm_runtime_set_suspended(dev);
 	else
-		__update_runtime_status(dev, RPM_SUSPENDED);
+		dev->power.needs_force_resume = true;
 
 	return 0;
 
 err:
+	dev_pm_disable_wake_irq_check(dev, true);
 	pm_runtime_enable(dev);
 	return ret;
 }
 EXPORT_SYMBOL_GPL(pm_runtime_force_suspend);
 
+#ifdef CONFIG_PM_SLEEP
+
 /**
  * pm_runtime_force_resume - Force a device into resume state if needed.
  * @dev: Device to resume.
  *
- * Prior invoking this function we expect the user to have brought the device
- * into low power state by a call to pm_runtime_force_suspend(). Here we reverse
- * those actions and bring the device into full power, if it is expected to be
- * used on system resume.  In the other case, we defer the resume to be managed
- * via runtime PM.
+ * This function expects that either pm_runtime_force_suspend() has put the
+ * device into a low-power state prior to calling it, or the device had been
+ * runtime-suspended before the preceding system-wide suspend transition and it
+ * was left in suspend during that transition.
+ *
+ * The actions carried out by pm_runtime_force_suspend(), or by a runtime
+ * suspend in general, are reversed and the device is brought back into full
+ * power if it is expected to be used on system resume, which is the case when
+ * its needs_force_resume flag is set or when its smart_suspend flag is set and
+ * its runtime PM status is "active".
  *
- * Typically this function may be invoked from a system resume callback.
+ * In other cases, the resume is deferred to be managed via runtime PM.
+ *
+ * Typically, this function may be invoked from a system resume callback.
  */
 int pm_runtime_force_resume(struct device *dev)
 {
 	int (*callback)(struct device *);
 	int ret = 0;
 
-	if (!pm_runtime_status_suspended(dev) || pm_runtime_need_not_resume(dev))
+	if (!dev->power.needs_force_resume && (!dev_pm_smart_suspend(dev) ||
+	    pm_runtime_status_suspended(dev)))
 		goto out;
 
-	/*
-	 * The value of the parent's children counter is correct already, so
-	 * just update the status of the device.
-	 */
-	__update_runtime_status(dev, RPM_ACTIVE);
-
-	callback = RPM_GET_CALLBACK(dev, runtime_resume);
+	callback = GET_CALLBACK(dev, runtime_resume);
 
+	dev_pm_disable_wake_irq_check(dev, false);
 	ret = callback ? callback(dev) : 0;
 	if (ret) {
 		pm_runtime_set_suspended(dev);
+		dev_pm_enable_wake_irq_check(dev, false);
 		goto out;
 	}
 
 	pm_runtime_mark_last_busy(dev);
+
 out:
+	/*
+	 * The smart_suspend flag can be cleared here because it is not going
+	 * to be necessary until the next system-wide suspend transition that
+	 * will update it again.
+	 */
+	dev->power.smart_suspend = false;
+	/*
+	 * Also clear needs_force_resume to make this function skip devices that
+	 * have been seen by it once.
+	 */
+	dev->power.needs_force_resume = false;
+
 	pm_runtime_enable(dev);
 	return ret;
 }
 EXPORT_SYMBOL_GPL(pm_runtime_force_resume);
+
+bool pm_runtime_need_not_resume(struct device *dev)
+{
+	return atomic_read(&dev->power.usage_count) <= 1 &&
+		(atomic_read(&dev->power.child_count) == 0 ||
+		 dev->power.ignore_children);
+}
+
+#endif /* CONFIG_PM_SLEEP */
diff --git a/drivers/base/power/sysfs.c b/drivers/base/power/sysfs.c
index 2b99fe1eb207..13b31a3adc77 100644
--- a/drivers/base/power/sysfs.c
+++ b/drivers/base/power/sysfs.c
@@ -1,11 +1,11 @@
 // SPDX-License-Identifier: GPL-2.0
 /* sysfs entries for device PM */
 #include <linux/device.h>
+#include <linux/kobject.h>
 #include <linux/string.h>
 #include <linux/export.h>
 #include <linux/pm_qos.h>
 #include <linux/pm_runtime.h>
-#include <linux/pm_wakeup.h>
 #include <linux/atomic.h>
 #include <linux/jiffies.h>
 #include "power.h"
@@ -100,8 +100,8 @@ static const char ctrl_on[] = "on";
 static ssize_t control_show(struct device *dev, struct device_attribute *attr,
 			    char *buf)
 {
-	return sprintf(buf, "%s\n",
-				dev->power.runtime_auto ? ctrl_auto : ctrl_on);
+	return sysfs_emit(buf, "%s\n",
+			  dev->power.runtime_auto ? ctrl_auto : ctrl_on);
 }
 
 static ssize_t control_store(struct device * dev, struct device_attribute *attr,
@@ -121,67 +121,71 @@ static ssize_t control_store(struct device * dev, struct device_attribute *attr,
 static DEVICE_ATTR_RW(control);
 
 static ssize_t runtime_active_time_show(struct device *dev,
-				struct device_attribute *attr, char *buf)
+					struct device_attribute *attr,
+					char *buf)
 {
-	int ret;
 	u64 tmp = pm_runtime_active_time(dev);
+
 	do_div(tmp, NSEC_PER_MSEC);
-	ret = sprintf(buf, "%llu\n", tmp);
-	return ret;
+
+	return sysfs_emit(buf, "%llu\n", tmp);
 }
 
 static DEVICE_ATTR_RO(runtime_active_time);
 
 static ssize_t runtime_suspended_time_show(struct device *dev,
-				struct device_attribute *attr, char *buf)
+					   struct device_attribute *attr,
+					   char *buf)
 {
-	int ret;
 	u64 tmp = pm_runtime_suspended_time(dev);
+
 	do_div(tmp, NSEC_PER_MSEC);
-	ret = sprintf(buf, "%llu\n", tmp);
-	return ret;
+
+	return sysfs_emit(buf, "%llu\n", tmp);
 }
 
 static DEVICE_ATTR_RO(runtime_suspended_time);
 
 static ssize_t runtime_status_show(struct device *dev,
-				struct device_attribute *attr, char *buf)
+				   struct device_attribute *attr, char *buf)
 {
-	const char *p;
+	const char *output;
 
 	if (dev->power.runtime_error) {
-		p = "error\n";
+		output = "error";
 	} else if (dev->power.disable_depth) {
-		p = "unsupported\n";
+		output = "unsupported";
 	} else {
 		switch (dev->power.runtime_status) {
 		case RPM_SUSPENDED:
-			p = "suspended\n";
+			output = "suspended";
 			break;
 		case RPM_SUSPENDING:
-			p = "suspending\n";
+			output = "suspending";
 			break;
 		case RPM_RESUMING:
-			p = "resuming\n";
+			output = "resuming";
 			break;
 		case RPM_ACTIVE:
-			p = "active\n";
+			output = "active";
 			break;
 		default:
 			return -EIO;
 		}
 	}
-	return sprintf(buf, p);
+	return sysfs_emit(buf, "%s\n", output);
 }
 
 static DEVICE_ATTR_RO(runtime_status);
 
 static ssize_t autosuspend_delay_ms_show(struct device *dev,
-		struct device_attribute *attr, char *buf)
+					 struct device_attribute *attr,
+					 char *buf)
 {
 	if (!dev->power.use_autosuspend)
 		return -EIO;
-	return sprintf(buf, "%d\n", dev->power.autosuspend_delay);
+
+	return sysfs_emit(buf, "%d\n", dev->power.autosuspend_delay);
 }
 
 static ssize_t autosuspend_delay_ms_store(struct device *dev,
@@ -210,11 +214,11 @@ static ssize_t pm_qos_resume_latency_us_show(struct device *dev,
 	s32 value = dev_pm_qos_requested_resume_latency(dev);
 
 	if (value == 0)
-		return sprintf(buf, "n/a\n");
+		return sysfs_emit(buf, "n/a\n");
 	if (value == PM_QOS_RESUME_LATENCY_NO_CONSTRAINT)
 		value = 0;
 
-	return sprintf(buf, "%d\n", value);
+	return sysfs_emit(buf, "%d\n", value);
 }
 
 static ssize_t pm_qos_resume_latency_us_store(struct device *dev,
@@ -254,11 +258,11 @@ static ssize_t pm_qos_latency_tolerance_us_show(struct device *dev,
 	s32 value = dev_pm_qos_get_user_latency_tolerance(dev);
 
 	if (value < 0)
-		return sprintf(buf, "auto\n");
+		return sysfs_emit(buf, "%s\n", "auto");
 	if (value == PM_QOS_LATENCY_ANY)
-		return sprintf(buf, "any\n");
+		return sysfs_emit(buf, "%s\n", "any");
 
-	return sprintf(buf, "%d\n", value);
+	return sysfs_emit(buf, "%d\n", value);
 }
 
 static ssize_t pm_qos_latency_tolerance_us_store(struct device *dev,
@@ -290,8 +294,8 @@ static ssize_t pm_qos_no_power_off_show(struct device *dev,
 					struct device_attribute *attr,
 					char *buf)
 {
-	return sprintf(buf, "%d\n", !!(dev_pm_qos_requested_flags(dev)
-					& PM_QOS_FLAG_NO_POWER_OFF));
+	return sysfs_emit(buf, "%d\n", !!(dev_pm_qos_requested_flags(dev)
+					  & PM_QOS_FLAG_NO_POWER_OFF));
 }
 
 static ssize_t pm_qos_no_power_off_store(struct device *dev,
@@ -319,9 +323,9 @@ static const char _disabled[] = "disabled";
 static ssize_t wakeup_show(struct device *dev, struct device_attribute *attr,
 			   char *buf)
 {
-	return sprintf(buf, "%s\n", device_can_wakeup(dev)
-		? (device_may_wakeup(dev) ? _enabled : _disabled)
-		: "");
+	return sysfs_emit(buf, "%s\n", device_can_wakeup(dev)
+			  ? (device_may_wakeup(dev) ? _enabled : _disabled)
+			  : "");
 }
 
 static ssize_t wakeup_store(struct device *dev, struct device_attribute *attr,
@@ -344,7 +348,7 @@ static DEVICE_ATTR_RW(wakeup);
 static ssize_t wakeup_count_show(struct device *dev,
 				 struct device_attribute *attr, char *buf)
 {
-	unsigned long count = 0;
+	unsigned long count;
 	bool enabled = false;
 
 	spin_lock_irq(&dev->power.lock);
@@ -353,7 +357,10 @@ static ssize_t wakeup_count_show(struct device *dev,
 		enabled = true;
 	}
 	spin_unlock_irq(&dev->power.lock);
-	return enabled ? sprintf(buf, "%lu\n", count) : sprintf(buf, "\n");
+
+	if (!enabled)
+		return sysfs_emit(buf, "\n");
+	return sysfs_emit(buf, "%lu\n", count);
 }
 
 static DEVICE_ATTR_RO(wakeup_count);
@@ -362,7 +369,7 @@ static ssize_t wakeup_active_count_show(struct device *dev,
 					struct device_attribute *attr,
 					char *buf)
 {
-	unsigned long count = 0;
+	unsigned long count;
 	bool enabled = false;
 
 	spin_lock_irq(&dev->power.lock);
@@ -371,7 +378,10 @@ static ssize_t wakeup_active_count_show(struct device *dev,
 		enabled = true;
 	}
 	spin_unlock_irq(&dev->power.lock);
-	return enabled ? sprintf(buf, "%lu\n", count) : sprintf(buf, "\n");
+
+	if (!enabled)
+		return sysfs_emit(buf, "\n");
+	return sysfs_emit(buf, "%lu\n", count);
 }
 
 static DEVICE_ATTR_RO(wakeup_active_count);
@@ -380,7 +390,7 @@ static ssize_t wakeup_abort_count_show(struct device *dev,
 				       struct device_attribute *attr,
 				       char *buf)
 {
-	unsigned long count = 0;
+	unsigned long count;
 	bool enabled = false;
 
 	spin_lock_irq(&dev->power.lock);
@@ -389,7 +399,10 @@ static ssize_t wakeup_abort_count_show(struct device *dev,
 		enabled = true;
 	}
 	spin_unlock_irq(&dev->power.lock);
-	return enabled ? sprintf(buf, "%lu\n", count) : sprintf(buf, "\n");
+
+	if (!enabled)
+		return sysfs_emit(buf, "\n");
+	return sysfs_emit(buf, "%lu\n", count);
 }
 
 static DEVICE_ATTR_RO(wakeup_abort_count);
@@ -398,7 +411,7 @@ static ssize_t wakeup_expire_count_show(struct device *dev,
 					struct device_attribute *attr,
 					char *buf)
 {
-	unsigned long count = 0;
+	unsigned long count;
 	bool enabled = false;
 
 	spin_lock_irq(&dev->power.lock);
@@ -407,7 +420,10 @@ static ssize_t wakeup_expire_count_show(struct device *dev,
 		enabled = true;
 	}
 	spin_unlock_irq(&dev->power.lock);
-	return enabled ? sprintf(buf, "%lu\n", count) : sprintf(buf, "\n");
+
+	if (!enabled)
+		return sysfs_emit(buf, "\n");
+	return sysfs_emit(buf, "%lu\n", count);
 }
 
 static DEVICE_ATTR_RO(wakeup_expire_count);
@@ -415,7 +431,7 @@ static DEVICE_ATTR_RO(wakeup_expire_count);
 static ssize_t wakeup_active_show(struct device *dev,
 				  struct device_attribute *attr, char *buf)
 {
-	unsigned int active = 0;
+	unsigned int active;
 	bool enabled = false;
 
 	spin_lock_irq(&dev->power.lock);
@@ -424,7 +440,10 @@ static ssize_t wakeup_active_show(struct device *dev,
 		enabled = true;
 	}
 	spin_unlock_irq(&dev->power.lock);
-	return enabled ? sprintf(buf, "%u\n", active) : sprintf(buf, "\n");
+
+	if (!enabled)
+		return sysfs_emit(buf, "\n");
+	return sysfs_emit(buf, "%u\n", active);
 }
 
 static DEVICE_ATTR_RO(wakeup_active);
@@ -433,7 +452,7 @@ static ssize_t wakeup_total_time_ms_show(struct device *dev,
 					 struct device_attribute *attr,
 					 char *buf)
 {
-	s64 msec = 0;
+	s64 msec;
 	bool enabled = false;
 
 	spin_lock_irq(&dev->power.lock);
@@ -442,7 +461,10 @@ static ssize_t wakeup_total_time_ms_show(struct device *dev,
 		enabled = true;
 	}
 	spin_unlock_irq(&dev->power.lock);
-	return enabled ? sprintf(buf, "%lld\n", msec) : sprintf(buf, "\n");
+
+	if (!enabled)
+		return sysfs_emit(buf, "\n");
+	return sysfs_emit(buf, "%lld\n", msec);
 }
 
 static DEVICE_ATTR_RO(wakeup_total_time_ms);
@@ -450,7 +472,7 @@ static DEVICE_ATTR_RO(wakeup_total_time_ms);
 static ssize_t wakeup_max_time_ms_show(struct device *dev,
 				       struct device_attribute *attr, char *buf)
 {
-	s64 msec = 0;
+	s64 msec;
 	bool enabled = false;
 
 	spin_lock_irq(&dev->power.lock);
@@ -459,7 +481,10 @@ static ssize_t wakeup_max_time_ms_show(struct device *dev,
 		enabled = true;
 	}
 	spin_unlock_irq(&dev->power.lock);
-	return enabled ? sprintf(buf, "%lld\n", msec) : sprintf(buf, "\n");
+
+	if (!enabled)
+		return sysfs_emit(buf, "\n");
+	return sysfs_emit(buf, "%lld\n", msec);
 }
 
 static DEVICE_ATTR_RO(wakeup_max_time_ms);
@@ -468,7 +493,7 @@ static ssize_t wakeup_last_time_ms_show(struct device *dev,
 					struct device_attribute *attr,
 					char *buf)
 {
-	s64 msec = 0;
+	s64 msec;
 	bool enabled = false;
 
 	spin_lock_irq(&dev->power.lock);
@@ -477,15 +502,10 @@ static ssize_t wakeup_last_time_ms_show(struct device *dev,
 		enabled = true;
 	}
 	spin_unlock_irq(&dev->power.lock);
-	return enabled ? sprintf(buf, "%lld\n", msec) : sprintf(buf, "\n");
-}
 
-static inline int dpm_sysfs_wakeup_change_owner(struct device *dev, kuid_t kuid,
-						kgid_t kgid)
-{
-	if (dev->power.wakeup && dev->power.wakeup->dev)
-		return device_change_owner(dev->power.wakeup->dev, kuid, kgid);
-	return 0;
+	if (!enabled)
+		return sysfs_emit(buf, "\n");
+	return sysfs_emit(buf, "%lld\n", msec);
 }
 
 static DEVICE_ATTR_RO(wakeup_last_time_ms);
@@ -495,7 +515,7 @@ static ssize_t wakeup_prevent_sleep_time_ms_show(struct device *dev,
 						 struct device_attribute *attr,
 						 char *buf)
 {
-	s64 msec = 0;
+	s64 msec;
 	bool enabled = false;
 
 	spin_lock_irq(&dev->power.lock);
@@ -504,11 +524,23 @@ static ssize_t wakeup_prevent_sleep_time_ms_show(struct device *dev,
 		enabled = true;
 	}
 	spin_unlock_irq(&dev->power.lock);
-	return enabled ? sprintf(buf, "%lld\n", msec) : sprintf(buf, "\n");
+
+	if (!enabled)
+		return sysfs_emit(buf, "\n");
+	return sysfs_emit(buf, "%lld\n", msec);
 }
 
 static DEVICE_ATTR_RO(wakeup_prevent_sleep_time_ms);
 #endif /* CONFIG_PM_AUTOSLEEP */
+
+static inline int dpm_sysfs_wakeup_change_owner(struct device *dev, kuid_t kuid,
+						kgid_t kgid)
+{
+	if (dev->power.wakeup && dev->power.wakeup->dev)
+		return device_change_owner(dev->power.wakeup->dev, kuid, kgid);
+	return 0;
+}
+
 #else /* CONFIG_PM_SLEEP */
 static inline int dpm_sysfs_wakeup_change_owner(struct device *dev, kuid_t kuid,
 						kgid_t kgid)
@@ -521,7 +553,7 @@ static inline int dpm_sysfs_wakeup_change_owner(struct device *dev, kuid_t kuid,
 static ssize_t runtime_usage_show(struct device *dev,
 				  struct device_attribute *attr, char *buf)
 {
-	return sprintf(buf, "%d\n", atomic_read(&dev->power.usage_count));
+	return sysfs_emit(buf, "%d\n", atomic_read(&dev->power.usage_count));
 }
 static DEVICE_ATTR_RO(runtime_usage);
 
@@ -529,21 +561,26 @@ static ssize_t runtime_active_kids_show(struct device *dev,
 					struct device_attribute *attr,
 					char *buf)
 {
-	return sprintf(buf, "%d\n", dev->power.ignore_children ?
-		0 : atomic_read(&dev->power.child_count));
+	return sysfs_emit(buf, "%d\n", dev->power.ignore_children ?
+			  0 : atomic_read(&dev->power.child_count));
 }
 static DEVICE_ATTR_RO(runtime_active_kids);
 
 static ssize_t runtime_enabled_show(struct device *dev,
 				    struct device_attribute *attr, char *buf)
 {
-	if (dev->power.disable_depth && (dev->power.runtime_auto == false))
-		return sprintf(buf, "disabled & forbidden\n");
-	if (dev->power.disable_depth)
-		return sprintf(buf, "disabled\n");
-	if (dev->power.runtime_auto == false)
-		return sprintf(buf, "forbidden\n");
-	return sprintf(buf, "enabled\n");
+	const char *output;
+
+	if (dev->power.disable_depth && !dev->power.runtime_auto)
+		output = "disabled & forbidden";
+	else if (dev->power.disable_depth)
+		output = "disabled";
+	else if (!dev->power.runtime_auto)
+		output = "forbidden";
+	else
+		output = "enabled";
+
+	return sysfs_emit(buf, "%s\n", output);
 }
 static DEVICE_ATTR_RO(runtime_enabled);
 
@@ -551,9 +588,9 @@ static DEVICE_ATTR_RO(runtime_enabled);
 static ssize_t async_show(struct device *dev, struct device_attribute *attr,
 			  char *buf)
 {
-	return sprintf(buf, "%s\n",
-			device_async_suspend_enabled(dev) ?
-				_enabled : _disabled);
+	return sysfs_emit(buf, "%s\n",
+			  device_async_suspend_enabled(dev) ?
+			  _enabled : _disabled);
 }
 
 static ssize_t async_store(struct device *dev, struct device_attribute *attr,
@@ -574,15 +611,9 @@ static DEVICE_ATTR_RW(async);
 #endif /* CONFIG_PM_ADVANCED_DEBUG */
 
 static struct attribute *power_attrs[] = {
-#ifdef CONFIG_PM_ADVANCED_DEBUG
-#ifdef CONFIG_PM_SLEEP
+#if defined(CONFIG_PM_ADVANCED_DEBUG) && defined(CONFIG_PM_SLEEP)
 	&dev_attr_async.attr,
 #endif
-	&dev_attr_runtime_status.attr,
-	&dev_attr_runtime_usage.attr,
-	&dev_attr_runtime_active_kids.attr,
-	&dev_attr_runtime_enabled.attr,
-#endif /* CONFIG_PM_ADVANCED_DEBUG */
 	NULL,
 };
 static const struct attribute_group pm_attr_group = {
@@ -613,13 +644,16 @@ static const struct attribute_group pm_wakeup_attr_group = {
 };
 
 static struct attribute *runtime_attrs[] = {
-#ifndef CONFIG_PM_ADVANCED_DEBUG
 	&dev_attr_runtime_status.attr,
-#endif
 	&dev_attr_control.attr,
 	&dev_attr_runtime_suspended_time.attr,
 	&dev_attr_runtime_active_time.attr,
 	&dev_attr_autosuspend_delay_ms.attr,
+#ifdef CONFIG_PM_ADVANCED_DEBUG
+	&dev_attr_runtime_usage.attr,
+	&dev_attr_runtime_active_kids.attr,
+	&dev_attr_runtime_enabled.attr,
+#endif
 	NULL,
 };
 static const struct attribute_group pm_runtime_attr_group = {
@@ -666,7 +700,7 @@ int dpm_sysfs_add(struct device *dev)
 	if (rc)
 		return rc;
 
-	if (pm_runtime_callbacks_present(dev)) {
+	if (!pm_runtime_has_no_callbacks(dev)) {
 		rc = sysfs_merge_group(&dev->kobj, &pm_runtime_attr_group);
 		if (rc)
 			goto err_out;
@@ -709,7 +743,7 @@ int dpm_sysfs_change_owner(struct device *dev, kuid_t kuid, kgid_t kgid)
 	if (rc)
 		return rc;
 
-	if (pm_runtime_callbacks_present(dev)) {
+	if (!pm_runtime_has_no_callbacks(dev)) {
 		rc = sysfs_group_change_owner(
 			&dev->kobj, &pm_runtime_attr_group, kuid, kgid);
 		if (rc)
@@ -739,12 +773,18 @@ int dpm_sysfs_change_owner(struct device *dev, kuid_t kuid, kgid_t kgid)
 
 int wakeup_sysfs_add(struct device *dev)
 {
-	return sysfs_merge_group(&dev->kobj, &pm_wakeup_attr_group);
+	int ret = sysfs_merge_group(&dev->kobj, &pm_wakeup_attr_group);
+
+	if (!ret)
+		kobject_uevent(&dev->kobj, KOBJ_CHANGE);
+
+	return ret;
 }
 
 void wakeup_sysfs_remove(struct device *dev)
 {
 	sysfs_unmerge_group(&dev->kobj, &pm_wakeup_attr_group);
+	kobject_uevent(&dev->kobj, KOBJ_CHANGE);
 }
 
 int pm_qos_sysfs_add_resume_latency(struct device *dev)
diff --git a/drivers/base/power/trace.c b/drivers/base/power/trace.c
index 977d27bd1a22..d8da7195bb00 100644
--- a/drivers/base/power/trace.c
+++ b/drivers/base/power/trace.c
@@ -13,6 +13,7 @@
 #include <linux/export.h>
 #include <linux/rtc.h>
 #include <linux/suspend.h>
+#include <linux/init.h>
 
 #include <linux/mc146818rtc.h>
 
@@ -119,7 +120,11 @@ static unsigned int read_magic_time(void)
 	struct rtc_time time;
 	unsigned int val;
 
-	mc146818_get_time(&time);
+	if (mc146818_get_time(&time, 1000) < 0) {
+		pr_err("Unable to read current time from RTC\n");
+		return 0;
+	}
+
 	pr_info("RTC time: %ptRt, date: %ptRd\n", &time, &time);
 	val = time.tm_year;				/* 100 years */
 	if (val > 100)
@@ -165,6 +170,9 @@ void generate_pm_trace(const void *tracedata, unsigned int user)
 	const char *file = *(const char **)(tracedata + 2);
 	unsigned int user_hash_value, file_hash_value;
 
+	if (!x86_platform.legacy.rtc)
+		return;
+
 	user_hash_value = user % USERHASH;
 	file_hash_value = hash_string(lineno, file, FILEHASH);
 	set_magic_time(user_hash_value, file_hash_value, dev_hash_value);
@@ -230,10 +238,8 @@ int show_trace_dev_match(char *buf, size_t size)
 		unsigned int hash = hash_string(DEVSEED, dev_name(dev),
 						DEVHASH);
 		if (hash == value) {
-			int len = snprintf(buf, size, "%s\n",
+			int len = scnprintf(buf, size, "%s\n",
 					    dev_driver_string(dev));
-			if (len > size)
-				len = size;
 			buf += len;
 			ret += len;
 			size -= len;
@@ -265,18 +271,24 @@ static struct notifier_block pm_trace_nb = {
 	.notifier_call = pm_trace_notify,
 };
 
-static int early_resume_init(void)
+static int __init early_resume_init(void)
 {
+	if (!x86_platform.legacy.rtc)
+		return 0;
+
 	hash_value_early_read = read_magic_time();
 	register_pm_notifier(&pm_trace_nb);
 	return 0;
 }
 
-static int late_resume_init(void)
+static int __init late_resume_init(void)
 {
 	unsigned int val = hash_value_early_read;
 	unsigned int user, file, dev;
 
+	if (!x86_platform.legacy.rtc)
+		return 0;
+
 	user = val % USERHASH;
 	val = val / USERHASH;
 	file = val % FILEHASH;
diff --git a/drivers/base/power/wakeirq.c b/drivers/base/power/wakeirq.c
index 8e021082dba8..8aa28c08b289 100644
--- a/drivers/base/power/wakeirq.c
+++ b/drivers/base/power/wakeirq.c
@@ -12,14 +12,11 @@
 /**
  * dev_pm_attach_wake_irq - Attach device interrupt as a wake IRQ
  * @dev: Device entry
- * @irq: Device wake-up capable interrupt
  * @wirq: Wake irq specific data
  *
- * Internal function to attach either a device IO interrupt or a
- * dedicated wake-up interrupt as a wake IRQ.
+ * Internal function to attach a dedicated wake-up interrupt as a wake IRQ.
  */
-static int dev_pm_attach_wake_irq(struct device *dev, int irq,
-				  struct wake_irq *wirq)
+static int dev_pm_attach_wake_irq(struct device *dev, struct wake_irq *wirq)
 {
 	unsigned long flags;
 
@@ -65,7 +62,7 @@ int dev_pm_set_wake_irq(struct device *dev, int irq)
 	wirq->dev = dev;
 	wirq->irq = irq;
 
-	err = dev_pm_attach_wake_irq(dev, irq, wirq);
+	err = dev_pm_attach_wake_irq(dev, wirq);
 	if (err)
 		kfree(wirq);
 
@@ -106,6 +103,32 @@ void dev_pm_clear_wake_irq(struct device *dev)
 }
 EXPORT_SYMBOL_GPL(dev_pm_clear_wake_irq);
 
+static void devm_pm_clear_wake_irq(void *dev)
+{
+	dev_pm_clear_wake_irq(dev);
+}
+
+/**
+ * devm_pm_set_wake_irq - device-managed variant of dev_pm_set_wake_irq
+ * @dev: Device entry
+ * @irq: Device IO interrupt
+ *
+ *
+ * Attach a device IO interrupt as a wake IRQ, same with dev_pm_set_wake_irq,
+ * but the device will be auto clear wake capability on driver detach.
+ */
+int devm_pm_set_wake_irq(struct device *dev, int irq)
+{
+	int ret;
+
+	ret = dev_pm_set_wake_irq(dev, irq);
+	if (ret)
+		return ret;
+
+	return devm_add_action_or_reset(dev, devm_pm_clear_wake_irq, dev);
+}
+EXPORT_SYMBOL_GPL(devm_pm_set_wake_irq);
+
 /**
  * handle_threaded_wake_irq - Handler for dedicated wake-up interrupts
  * @irq: Device specific dedicated wake-up interrupt
@@ -145,24 +168,7 @@ static irqreturn_t handle_threaded_wake_irq(int irq, void *_wirq)
 	return IRQ_HANDLED;
 }
 
-/**
- * dev_pm_set_dedicated_wake_irq - Request a dedicated wake-up interrupt
- * @dev: Device entry
- * @irq: Device wake-up interrupt
- *
- * Unless your hardware has separate wake-up interrupts in addition
- * to the device IO interrupts, you don't need this.
- *
- * Sets up a threaded interrupt handler for a device that has
- * a dedicated wake-up interrupt in addition to the device IO
- * interrupt.
- *
- * The interrupt starts disabled, and needs to be managed for
- * the device by the bus code or the device driver using
- * dev_pm_enable_wake_irq() and dev_pm_disable_wake_irq()
- * functions.
- */
-int dev_pm_set_dedicated_wake_irq(struct device *dev, int irq)
+static int __dev_pm_set_dedicated_wake_irq(struct device *dev, int irq, unsigned int flag)
 {
 	struct wake_irq *wirq;
 	int err;
@@ -182,7 +188,6 @@ int dev_pm_set_dedicated_wake_irq(struct device *dev, int irq)
 
 	wirq->dev = dev;
 	wirq->irq = irq;
-	irq_set_status_flags(irq, IRQ_NOAUTOEN);
 
 	/* Prevent deferred spurious wakeirqs with disable_irq_nosync() */
 	irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY);
@@ -192,15 +197,16 @@ int dev_pm_set_dedicated_wake_irq(struct device *dev, int irq)
 	 * so we use a threaded irq.
 	 */
 	err = request_threaded_irq(irq, NULL, handle_threaded_wake_irq,
-				   IRQF_ONESHOT, wirq->name, wirq);
+				   IRQF_ONESHOT | IRQF_NO_AUTOEN,
+				   wirq->name, wirq);
 	if (err)
 		goto err_free_name;
 
-	err = dev_pm_attach_wake_irq(dev, irq, wirq);
+	err = dev_pm_attach_wake_irq(dev, wirq);
 	if (err)
 		goto err_free_irq;
 
-	wirq->status = WAKE_IRQ_DEDICATED_ALLOCATED;
+	wirq->status = WAKE_IRQ_DEDICATED_ALLOCATED | flag;
 
 	return err;
 
@@ -213,45 +219,45 @@ err_free:
 
 	return err;
 }
-EXPORT_SYMBOL_GPL(dev_pm_set_dedicated_wake_irq);
 
 /**
- * dev_pm_enable_wake_irq - Enable device wake-up interrupt
- * @dev: Device
+ * dev_pm_set_dedicated_wake_irq - Request a dedicated wake-up interrupt
+ * @dev: Device entry
+ * @irq: Device wake-up interrupt
  *
- * Optionally called from the bus code or the device driver for
- * runtime_resume() to override the PM runtime core managed wake-up
- * interrupt handling to enable the wake-up interrupt.
+ * Unless your hardware has separate wake-up interrupts in addition
+ * to the device IO interrupts, you don't need this.
  *
- * Note that for runtime_suspend()) the wake-up interrupts
- * should be unconditionally enabled unlike for suspend()
- * that is conditional.
+ * Sets up a threaded interrupt handler for a device that has
+ * a dedicated wake-up interrupt in addition to the device IO
+ * interrupt.
  */
-void dev_pm_enable_wake_irq(struct device *dev)
+int dev_pm_set_dedicated_wake_irq(struct device *dev, int irq)
 {
-	struct wake_irq *wirq = dev->power.wakeirq;
-
-	if (wirq && (wirq->status & WAKE_IRQ_DEDICATED_ALLOCATED))
-		enable_irq(wirq->irq);
+	return __dev_pm_set_dedicated_wake_irq(dev, irq, 0);
 }
-EXPORT_SYMBOL_GPL(dev_pm_enable_wake_irq);
+EXPORT_SYMBOL_GPL(dev_pm_set_dedicated_wake_irq);
 
 /**
- * dev_pm_disable_wake_irq - Disable device wake-up interrupt
- * @dev: Device
+ * dev_pm_set_dedicated_wake_irq_reverse - Request a dedicated wake-up interrupt
+ *                                         with reverse enable ordering
+ * @dev: Device entry
+ * @irq: Device wake-up interrupt
  *
- * Optionally called from the bus code or the device driver for
- * runtime_suspend() to override the PM runtime core managed wake-up
- * interrupt handling to disable the wake-up interrupt.
+ * Unless your hardware has separate wake-up interrupts in addition
+ * to the device IO interrupts, you don't need this.
+ *
+ * Sets up a threaded interrupt handler for a device that has a dedicated
+ * wake-up interrupt in addition to the device IO interrupt. It sets
+ * the status of WAKE_IRQ_DEDICATED_REVERSE to tell rpm_suspend()
+ * to enable dedicated wake-up interrupt after running the runtime suspend
+ * callback for @dev.
  */
-void dev_pm_disable_wake_irq(struct device *dev)
+int dev_pm_set_dedicated_wake_irq_reverse(struct device *dev, int irq)
 {
-	struct wake_irq *wirq = dev->power.wakeirq;
-
-	if (wirq && (wirq->status & WAKE_IRQ_DEDICATED_ALLOCATED))
-		disable_irq_nosync(wirq->irq);
+	return __dev_pm_set_dedicated_wake_irq(dev, irq, WAKE_IRQ_DEDICATED_REVERSE);
 }
-EXPORT_SYMBOL_GPL(dev_pm_disable_wake_irq);
+EXPORT_SYMBOL_GPL(dev_pm_set_dedicated_wake_irq_reverse);
 
 /**
  * dev_pm_enable_wake_irq_check - Checks and enables wake-up interrupt
@@ -260,7 +266,7 @@ EXPORT_SYMBOL_GPL(dev_pm_disable_wake_irq);
  *
  * Enables wakeirq conditionally. We need to enable wake-up interrupt
  * lazily on the first rpm_suspend(). This is needed as the consumer device
- * starts in RPM_SUSPENDED state, and the the first pm_runtime_get() would
+ * starts in RPM_SUSPENDED state, and the first pm_runtime_get() would
  * otherwise try to disable already disabled wakeirq. The wake-up interrupt
  * starts disabled with IRQ_NOAUTOEN set.
  *
@@ -285,25 +291,58 @@ void dev_pm_enable_wake_irq_check(struct device *dev,
 	return;
 
 enable:
-	enable_irq(wirq->irq);
+	if (!can_change_status || !(wirq->status & WAKE_IRQ_DEDICATED_REVERSE)) {
+		enable_irq(wirq->irq);
+		wirq->status |= WAKE_IRQ_DEDICATED_ENABLED;
+	}
 }
 
 /**
  * dev_pm_disable_wake_irq_check - Checks and disables wake-up interrupt
  * @dev: Device
+ * @cond_disable: if set, also check WAKE_IRQ_DEDICATED_REVERSE
  *
  * Disables wake-up interrupt conditionally based on status.
  * Should be only called from rpm_suspend() and rpm_resume() path.
  */
-void dev_pm_disable_wake_irq_check(struct device *dev)
+void dev_pm_disable_wake_irq_check(struct device *dev, bool cond_disable)
 {
 	struct wake_irq *wirq = dev->power.wakeirq;
 
 	if (!wirq || !(wirq->status & WAKE_IRQ_DEDICATED_MASK))
 		return;
 
-	if (wirq->status & WAKE_IRQ_DEDICATED_MANAGED)
+	if (cond_disable && (wirq->status & WAKE_IRQ_DEDICATED_REVERSE))
+		return;
+
+	if (wirq->status & WAKE_IRQ_DEDICATED_MANAGED) {
+		wirq->status &= ~WAKE_IRQ_DEDICATED_ENABLED;
 		disable_irq_nosync(wirq->irq);
+	}
+}
+
+/**
+ * dev_pm_enable_wake_irq_complete - enable wake IRQ not enabled before
+ * @dev: Device using the wake IRQ
+ *
+ * Enable wake IRQ conditionally based on status, mainly used if want to
+ * enable wake IRQ after running ->runtime_suspend() which depends on
+ * WAKE_IRQ_DEDICATED_REVERSE.
+ *
+ * Should be only called from rpm_suspend() path.
+ */
+void dev_pm_enable_wake_irq_complete(struct device *dev)
+{
+	struct wake_irq *wirq = dev->power.wakeirq;
+
+	if (!wirq || !(wirq->status & WAKE_IRQ_DEDICATED_MASK))
+		return;
+
+	if (wirq->status & WAKE_IRQ_DEDICATED_MANAGED &&
+	    wirq->status & WAKE_IRQ_DEDICATED_REVERSE) {
+		enable_irq(wirq->irq);
+		wirq->status |= WAKE_IRQ_DEDICATED_ENABLED;
+	}
 }
 
 /**
@@ -320,7 +359,7 @@ void dev_pm_arm_wake_irq(struct wake_irq *wirq)
 
 	if (device_may_wakeup(wirq->dev)) {
 		if (wirq->status & WAKE_IRQ_DEDICATED_ALLOCATED &&
-		    !pm_runtime_status_suspended(wirq->dev))
+		    !(wirq->status & WAKE_IRQ_DEDICATED_ENABLED))
 			enable_irq(wirq->irq);
 
 		enable_irq_wake(wirq->irq);
@@ -343,7 +382,7 @@ void dev_pm_disarm_wake_irq(struct wake_irq *wirq)
 		disable_irq_wake(wirq->irq);
 
 		if (wirq->status & WAKE_IRQ_DEDICATED_ALLOCATED &&
-		    !pm_runtime_status_suspended(wirq->dev))
+		    !(wirq->status & WAKE_IRQ_DEDICATED_ENABLED))
 			disable_irq_nosync(wirq->irq);
 	}
 }
diff --git a/drivers/base/power/wakeup.c b/drivers/base/power/wakeup.c
index 92073ac68473..1e1a0e7eeac5 100644
--- a/drivers/base/power/wakeup.c
+++ b/drivers/base/power/wakeup.c
@@ -19,11 +19,6 @@
 
 #include "power.h"
 
-#ifndef CONFIG_SUSPEND
-suspend_state_t pm_suspend_target_state;
-#define pm_suspend_target_state	(PM_SUSPEND_ON)
-#endif
-
 #define list_for_each_entry_rcu_locked(pos, head, member) \
 	list_for_each_entry_rcu(pos, head, member, \
 		srcu_read_lock_held(&wakeup_srcu))
@@ -34,7 +29,8 @@ suspend_state_t pm_suspend_target_state;
 bool events_check_enabled __read_mostly;
 
 /* First wakeup IRQ seen by the kernel in the last cycle. */
-unsigned int pm_wakeup_irq __read_mostly;
+static unsigned int wakeup_irq[2] __read_mostly;
+static DEFINE_RAW_SPINLOCK(wakeup_irq_lock);
 
 /* If greater than 0 and the system is suspending, terminate the suspend. */
 static atomic_t pm_abort_suspend __read_mostly;
@@ -81,7 +77,7 @@ static DEFINE_IDA(wakeup_ida);
  * wakeup_source_create - Create a struct wakeup_source object.
  * @name: Name of the new wakeup source.
  */
-struct wakeup_source *wakeup_source_create(const char *name)
+static struct wakeup_source *wakeup_source_create(const char *name)
 {
 	struct wakeup_source *ws;
 	const char *ws_name;
@@ -110,7 +106,6 @@ err_name:
 err_ws:
 	return NULL;
 }
-EXPORT_SYMBOL_GPL(wakeup_source_create);
 
 /*
  * Record wakeup_source statistics being deleted into a dummy wakeup_source.
@@ -153,7 +148,7 @@ static void wakeup_source_free(struct wakeup_source *ws)
  *
  * Use only for wakeup source objects created with wakeup_source_create().
  */
-void wakeup_source_destroy(struct wakeup_source *ws)
+static void wakeup_source_destroy(struct wakeup_source *ws)
 {
 	if (!ws)
 		return;
@@ -162,13 +157,12 @@ void wakeup_source_destroy(struct wakeup_source *ws)
 	wakeup_source_record(ws);
 	wakeup_source_free(ws);
 }
-EXPORT_SYMBOL_GPL(wakeup_source_destroy);
 
 /**
  * wakeup_source_add - Add given object to the list of wakeup sources.
  * @ws: Wakeup source object to add to the list.
  */
-void wakeup_source_add(struct wakeup_source *ws)
+static void wakeup_source_add(struct wakeup_source *ws)
 {
 	unsigned long flags;
 
@@ -183,32 +177,29 @@ void wakeup_source_add(struct wakeup_source *ws)
 	list_add_rcu(&ws->entry, &wakeup_sources);
 	raw_spin_unlock_irqrestore(&events_lock, flags);
 }
-EXPORT_SYMBOL_GPL(wakeup_source_add);
 
 /**
  * wakeup_source_remove - Remove given object from the wakeup sources list.
  * @ws: Wakeup source object to remove from the list.
  */
-void wakeup_source_remove(struct wakeup_source *ws)
+static void wakeup_source_remove(struct wakeup_source *ws)
 {
 	unsigned long flags;
 
 	if (WARN_ON(!ws))
 		return;
 
+	/*
+	 * After shutting down the timer, wakeup_source_activate() will warn if
+	 * the given wakeup source is passed to it.
+	 */
+	timer_shutdown_sync(&ws->timer);
+
 	raw_spin_lock_irqsave(&events_lock, flags);
 	list_del_rcu(&ws->entry);
 	raw_spin_unlock_irqrestore(&events_lock, flags);
 	synchronize_srcu(&wakeup_srcu);
-
-	del_timer_sync(&ws->timer);
-	/*
-	 * Clear timer.function to make wakeup_source_not_registered() treat
-	 * this wakeup source as not registered.
-	 */
-	ws->timer.function = NULL;
 }
-EXPORT_SYMBOL_GPL(wakeup_source_remove);
 
 /**
  * wakeup_source_register - Create wakeup source and add it to the list.
@@ -341,7 +332,7 @@ int device_wakeup_enable(struct device *dev)
 	if (!dev || !dev->power.can_wakeup)
 		return -EINVAL;
 
-	if (pm_suspend_target_state != PM_SUSPEND_ON)
+	if (pm_sleep_transition_in_progress())
 		dev_dbg(dev, "Suspicious %s() during system transition!\n", __func__);
 
 	ws = wakeup_source_register(dev, dev_name(dev));
@@ -400,9 +391,9 @@ void device_wakeup_detach_irq(struct device *dev)
 }
 
 /**
- * device_wakeup_arm_wake_irqs(void)
+ * device_wakeup_arm_wake_irqs -
  *
- * Itereates over the list of device wakeirqs to arm them.
+ * Iterates over the list of device wakeirqs to arm them.
  */
 void device_wakeup_arm_wake_irqs(void)
 {
@@ -416,9 +407,9 @@ void device_wakeup_arm_wake_irqs(void)
 }
 
 /**
- * device_wakeup_disarm_wake_irqs(void)
+ * device_wakeup_disarm_wake_irqs -
  *
- * Itereates over the list of device wakeirqs to disarm them.
+ * Iterates over the list of device wakeirqs to disarm them.
  */
 void device_wakeup_disarm_wake_irqs(void)
 {
@@ -455,16 +446,15 @@ static struct wakeup_source *device_wakeup_detach(struct device *dev)
  * Detach the @dev's wakeup source object from it, unregister this wakeup source
  * object and destroy it.
  */
-int device_wakeup_disable(struct device *dev)
+void device_wakeup_disable(struct device *dev)
 {
 	struct wakeup_source *ws;
 
 	if (!dev || !dev->power.can_wakeup)
-		return -EINVAL;
+		return;
 
 	ws = device_wakeup_detach(dev);
 	wakeup_source_unregister(ws);
-	return 0;
 }
 EXPORT_SYMBOL_GPL(device_wakeup_disable);
 
@@ -500,54 +490,29 @@ void device_set_wakeup_capable(struct device *dev, bool capable)
 EXPORT_SYMBOL_GPL(device_set_wakeup_capable);
 
 /**
- * device_init_wakeup - Device wakeup initialization.
- * @dev: Device to handle.
- * @enable: Whether or not to enable @dev as a wakeup device.
- *
- * By default, most devices should leave wakeup disabled.  The exceptions are
- * devices that everyone expects to be wakeup sources: keyboards, power buttons,
- * possibly network interfaces, etc.  Also, devices that don't generate their
- * own wakeup requests but merely forward requests from one bus to another
- * (like PCI bridges) should have wakeup enabled by default.
- */
-int device_init_wakeup(struct device *dev, bool enable)
-{
-	int ret = 0;
-
-	if (!dev)
-		return -EINVAL;
-
-	if (enable) {
-		device_set_wakeup_capable(dev, true);
-		ret = device_wakeup_enable(dev);
-	} else {
-		device_wakeup_disable(dev);
-		device_set_wakeup_capable(dev, false);
-	}
-
-	return ret;
-}
-EXPORT_SYMBOL_GPL(device_init_wakeup);
-
-/**
  * device_set_wakeup_enable - Enable or disable a device to wake up the system.
  * @dev: Device to handle.
+ * @enable: enable/disable flag
  */
 int device_set_wakeup_enable(struct device *dev, bool enable)
 {
-	return enable ? device_wakeup_enable(dev) : device_wakeup_disable(dev);
+	if (enable)
+		return device_wakeup_enable(dev);
+
+	device_wakeup_disable(dev);
+	return 0;
 }
 EXPORT_SYMBOL_GPL(device_set_wakeup_enable);
 
 /**
- * wakeup_source_not_registered - validate the given wakeup source.
+ * wakeup_source_not_usable - validate the given wakeup source.
  * @ws: Wakeup source to be validated.
  */
-static bool wakeup_source_not_registered(struct wakeup_source *ws)
+static bool wakeup_source_not_usable(struct wakeup_source *ws)
 {
 	/*
-	 * Use timer struct to check if the given source is initialized
-	 * by wakeup_source_add.
+	 * Use the timer struct to check if the given wakeup source has been
+	 * initialized by wakeup_source_add() and it is not going away.
 	 */
 	return ws->timer.function != pm_wakeup_timer_fn;
 }
@@ -581,19 +546,18 @@ static bool wakeup_source_not_registered(struct wakeup_source *ws)
  */
 
 /**
- * wakup_source_activate - Mark given wakeup source as active.
+ * wakeup_source_activate - Mark given wakeup source as active.
  * @ws: Wakeup source to handle.
  *
  * Update the @ws' statistics and, if @ws has just been activated, notify the PM
- * core of the event by incrementing the counter of of wakeup events being
+ * core of the event by incrementing the counter of the wakeup events being
  * processed.
  */
 static void wakeup_source_activate(struct wakeup_source *ws)
 {
 	unsigned int cec;
 
-	if (WARN_ONCE(wakeup_source_not_registered(ws),
-			"unregistered wakeup source\n"))
+	if (WARN_ONCE(wakeup_source_not_usable(ws), "unusable wakeup source\n"))
 		return;
 
 	ws->active = true;
@@ -643,7 +607,7 @@ void __pm_stay_awake(struct wakeup_source *ws)
 	spin_lock_irqsave(&ws->lock, flags);
 
 	wakeup_source_report_event(ws, false);
-	del_timer(&ws->timer);
+	timer_delete(&ws->timer);
 	ws->timer_expires = 0;
 
 	spin_unlock_irqrestore(&ws->lock, flags);
@@ -686,7 +650,7 @@ static inline void update_prevent_sleep_time(struct wakeup_source *ws,
 #endif
 
 /**
- * wakup_source_deactivate - Mark given wakeup source as inactive.
+ * wakeup_source_deactivate - Mark given wakeup source as inactive.
  * @ws: Wakeup source to handle.
  *
  * Update the @ws' statistics and notify the PM core that the wakeup source has
@@ -723,7 +687,7 @@ static void wakeup_source_deactivate(struct wakeup_source *ws)
 		ws->max_time = duration;
 
 	ws->last_time = now;
-	del_timer(&ws->timer);
+	timer_delete(&ws->timer);
 	ws->timer_expires = 0;
 
 	if (ws->autosleep_enabled)
@@ -731,7 +695,7 @@ static void wakeup_source_deactivate(struct wakeup_source *ws)
 
 	/*
 	 * Increment the counter of registered wakeup events and decrement the
-	 * couter of wakeup events in progress simultaneously.
+	 * counter of wakeup events in progress simultaneously.
 	 */
 	cec = atomic_add_return(MAX_IN_PROGRESS, &combined_event_count);
 	trace_wakeup_source_deactivate(ws->name, cec);
@@ -785,7 +749,7 @@ EXPORT_SYMBOL_GPL(pm_relax);
 
 /**
  * pm_wakeup_timer_fn - Delayed finalization of a wakeup event.
- * @data: Address of the wakeup source object associated with the event source.
+ * @t: timer list
  *
  * Call wakeup_source_deactivate() for the wakeup source whose address is stored
  * in @data if it is currently active and its timer has not been canceled and
@@ -793,7 +757,7 @@ EXPORT_SYMBOL_GPL(pm_relax);
  */
 static void pm_wakeup_timer_fn(struct timer_list *t)
 {
-	struct wakeup_source *ws = from_timer(ws, t, timer);
+	struct wakeup_source *ws = timer_container_of(ws, t, timer);
 	unsigned long flags;
 
 	spin_lock_irqsave(&ws->lock, flags);
@@ -928,6 +892,7 @@ bool pm_wakeup_pending(void)
 
 	return ret || atomic_read(&pm_abort_suspend) > 0;
 }
+EXPORT_SYMBOL_GPL(pm_wakeup_pending);
 
 void pm_system_wakeup(void)
 {
@@ -941,19 +906,47 @@ void pm_system_cancel_wakeup(void)
 	atomic_dec_if_positive(&pm_abort_suspend);
 }
 
-void pm_wakeup_clear(bool reset)
+void pm_wakeup_clear(unsigned int irq_number)
 {
-	pm_wakeup_irq = 0;
-	if (reset)
+	raw_spin_lock_irq(&wakeup_irq_lock);
+
+	if (irq_number && wakeup_irq[0] == irq_number)
+		wakeup_irq[0] = wakeup_irq[1];
+	else
+		wakeup_irq[0] = 0;
+
+	wakeup_irq[1] = 0;
+
+	raw_spin_unlock_irq(&wakeup_irq_lock);
+
+	if (!irq_number)
 		atomic_set(&pm_abort_suspend, 0);
 }
 
 void pm_system_irq_wakeup(unsigned int irq_number)
 {
-	if (pm_wakeup_irq == 0) {
-		pm_wakeup_irq = irq_number;
+	unsigned long flags;
+
+	raw_spin_lock_irqsave(&wakeup_irq_lock, flags);
+
+	if (wakeup_irq[0] == 0)
+		wakeup_irq[0] = irq_number;
+	else if (wakeup_irq[1] == 0)
+		wakeup_irq[1] = irq_number;
+	else
+		irq_number = 0;
+
+	pm_pr_dbg("Triggering wakeup from IRQ %d\n", irq_number);
+
+	raw_spin_unlock_irqrestore(&wakeup_irq_lock, flags);
+
+	if (irq_number)
 		pm_system_wakeup();
-	}
+}
+
+unsigned int pm_wakeup_irq(void)
+{
+	return wakeup_irq[0];
 }
 
 /**
@@ -1021,7 +1014,7 @@ bool pm_save_wakeup_count(unsigned int count)
 #ifdef CONFIG_PM_AUTOSLEEP
 /**
  * pm_wakep_autosleep_enabled - Modify autosleep_enabled for all wakeup sources.
- * @enabled: Whether to set or to clear the autosleep_enabled flags.
+ * @set: Whether to set or to clear the autosleep_enabled flags.
  */
 void pm_wakep_autosleep_enabled(bool set)
 {
@@ -1179,7 +1172,7 @@ static const struct file_operations wakeup_sources_stats_fops = {
 
 static int __init wakeup_sources_debugfs_init(void)
 {
-	debugfs_create_file("wakeup_sources", S_IRUGO, NULL, NULL,
+	debugfs_create_file("wakeup_sources", 0444, NULL, NULL,
 			    &wakeup_sources_stats_fops);
 	return 0;
 }
diff --git a/drivers/base/power/wakeup_stats.c b/drivers/base/power/wakeup_stats.c
index c7734914d914..3ffd427248e8 100644
--- a/drivers/base/power/wakeup_stats.c
+++ b/drivers/base/power/wakeup_stats.c
@@ -26,7 +26,7 @@ static ssize_t _name##_show(struct device *dev,				\
 {									\
 	struct wakeup_source *ws = dev_get_drvdata(dev);		\
 									\
-	return sprintf(buf, "%lu\n", ws->_name);			\
+	return sysfs_emit(buf, "%lu\n", ws->_name);			\
 }									\
 static DEVICE_ATTR_RO(_name)
 
@@ -34,6 +34,7 @@ wakeup_attr(active_count);
 wakeup_attr(event_count);
 wakeup_attr(wakeup_count);
 wakeup_attr(expire_count);
+wakeup_attr(relax_count);
 
 static ssize_t active_time_ms_show(struct device *dev,
 				   struct device_attribute *attr, char *buf)
@@ -42,7 +43,7 @@ static ssize_t active_time_ms_show(struct device *dev,
 	ktime_t active_time =
 		ws->active ? ktime_sub(ktime_get(), ws->last_time) : 0;
 
-	return sprintf(buf, "%lld\n", ktime_to_ms(active_time));
+	return sysfs_emit(buf, "%lld\n", ktime_to_ms(active_time));
 }
 static DEVICE_ATTR_RO(active_time_ms);
 
@@ -57,7 +58,8 @@ static ssize_t total_time_ms_show(struct device *dev,
 		active_time = ktime_sub(ktime_get(), ws->last_time);
 		total_time = ktime_add(total_time, active_time);
 	}
-	return sprintf(buf, "%lld\n", ktime_to_ms(total_time));
+
+	return sysfs_emit(buf, "%lld\n", ktime_to_ms(total_time));
 }
 static DEVICE_ATTR_RO(total_time_ms);
 
@@ -73,7 +75,8 @@ static ssize_t max_time_ms_show(struct device *dev,
 		if (active_time > max_time)
 			max_time = active_time;
 	}
-	return sprintf(buf, "%lld\n", ktime_to_ms(max_time));
+
+	return sysfs_emit(buf, "%lld\n", ktime_to_ms(max_time));
 }
 static DEVICE_ATTR_RO(max_time_ms);
 
@@ -82,7 +85,7 @@ static ssize_t last_change_ms_show(struct device *dev,
 {
 	struct wakeup_source *ws = dev_get_drvdata(dev);
 
-	return sprintf(buf, "%lld\n", ktime_to_ms(ws->last_time));
+	return sysfs_emit(buf, "%lld\n", ktime_to_ms(ws->last_time));
 }
 static DEVICE_ATTR_RO(last_change_ms);
 
@@ -91,7 +94,7 @@ static ssize_t name_show(struct device *dev, struct device_attribute *attr,
 {
 	struct wakeup_source *ws = dev_get_drvdata(dev);
 
-	return sprintf(buf, "%s\n", ws->name);
+	return sysfs_emit(buf, "%s\n", ws->name);
 }
 static DEVICE_ATTR_RO(name);
 
@@ -106,7 +109,8 @@ static ssize_t prevent_suspend_time_ms_show(struct device *dev,
 		prevent_sleep_time = ktime_add(prevent_sleep_time,
 			ktime_sub(ktime_get(), ws->start_prevent_time));
 	}
-	return sprintf(buf, "%lld\n", ktime_to_ms(prevent_sleep_time));
+
+	return sysfs_emit(buf, "%lld\n", ktime_to_ms(prevent_sleep_time));
 }
 static DEVICE_ATTR_RO(prevent_suspend_time_ms);
 
@@ -116,6 +120,7 @@ static struct attribute *wakeup_source_attrs[] = {
 	&dev_attr_event_count.attr,
 	&dev_attr_wakeup_count.attr,
 	&dev_attr_expire_count.attr,
+	&dev_attr_relax_count.attr,
 	&dev_attr_active_time_ms.attr,
 	&dev_attr_total_time_ms.attr,
 	&dev_attr_max_time_ms.attr,
@@ -134,7 +139,7 @@ static struct device *wakeup_source_device_create(struct device *parent,
 						  struct wakeup_source *ws)
 {
 	struct device *dev = NULL;
-	int retval = -ENODEV;
+	int retval;
 
 	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
 	if (!dev) {
@@ -151,7 +156,7 @@ static struct device *wakeup_source_device_create(struct device *parent,
 	dev_set_drvdata(dev, ws);
 	device_set_pm_not_required(dev);
 
-	retval = kobject_set_name(&dev->kobj, "wakeup%d", ws->id);
+	retval = dev_set_name(dev, "wakeup%d", ws->id);
 	if (retval)
 		goto error;
 
@@ -207,7 +212,7 @@ void wakeup_source_sysfs_remove(struct wakeup_source *ws)
 
 static int __init wakeup_sources_sysfs_init(void)
 {
-	wakeup_class = class_create(THIS_MODULE, "wakeup");
+	wakeup_class = class_create("wakeup");
 
 	return PTR_ERR_OR_ZERO(wakeup_class);
 }
diff --git a/drivers/base/property.c b/drivers/base/property.c
index 5f35c0ccf5e0..6a63860579dd 100644
--- a/drivers/base/property.c
+++ b/drivers/base/property.c
@@ -7,23 +7,30 @@
  *          Mika Westerberg <mika.westerberg@linux.intel.com>
  */
 
-#include <linux/acpi.h>
+#include <linux/device.h>
+#include <linux/err.h>
 #include <linux/export.h>
-#include <linux/kernel.h>
+#include <linux/kconfig.h>
 #include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_graph.h>
-#include <linux/of_irq.h>
 #include <linux/property.h>
-#include <linux/etherdevice.h>
 #include <linux/phy.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/types.h>
 
-struct fwnode_handle *dev_fwnode(struct device *dev)
+struct fwnode_handle *__dev_fwnode(struct device *dev)
 {
 	return IS_ENABLED(CONFIG_OF) && dev->of_node ?
-		&dev->of_node->fwnode : dev->fwnode;
+		of_fwnode_handle(dev->of_node) : dev->fwnode;
 }
-EXPORT_SYMBOL_GPL(dev_fwnode);
+EXPORT_SYMBOL_GPL(__dev_fwnode);
+
+const struct fwnode_handle *__dev_fwnode_const(const struct device *dev)
+{
+	return IS_ENABLED(CONFIG_OF) && dev->of_node ?
+		of_fwnode_handle(dev->of_node) : dev->fwnode;
+}
+EXPORT_SYMBOL_GPL(__dev_fwnode_const);
 
 /**
  * device_property_present - check if a property of a device is present
@@ -31,8 +38,10 @@ EXPORT_SYMBOL_GPL(dev_fwnode);
  * @propname: Name of the property
  *
  * Check if property @propname is present in the device firmware description.
+ *
+ * Return: true if property @propname is present. Otherwise, returns false.
  */
-bool device_property_present(struct device *dev, const char *propname)
+bool device_property_present(const struct device *dev, const char *propname)
 {
 	return fwnode_property_present(dev_fwnode(dev), propname);
 }
@@ -42,22 +51,64 @@ EXPORT_SYMBOL_GPL(device_property_present);
  * fwnode_property_present - check if a property of a firmware node is present
  * @fwnode: Firmware node whose property to check
  * @propname: Name of the property
+ *
+ * Return: true if property @propname is present. Otherwise, returns false.
  */
 bool fwnode_property_present(const struct fwnode_handle *fwnode,
 			     const char *propname)
 {
 	bool ret;
 
+	if (IS_ERR_OR_NULL(fwnode))
+		return false;
+
 	ret = fwnode_call_bool_op(fwnode, property_present, propname);
-	if (ret == false && !IS_ERR_OR_NULL(fwnode) &&
-	    !IS_ERR_OR_NULL(fwnode->secondary))
-		ret = fwnode_call_bool_op(fwnode->secondary, property_present,
-					 propname);
-	return ret;
+	if (ret)
+		return ret;
+
+	return fwnode_call_bool_op(fwnode->secondary, property_present, propname);
 }
 EXPORT_SYMBOL_GPL(fwnode_property_present);
 
 /**
+ * device_property_read_bool - Return the value for a boolean property of a device
+ * @dev: Device whose property is being checked
+ * @propname: Name of the property
+ *
+ * Return if property @propname is true or false in the device firmware description.
+ *
+ * Return: true if property @propname is present. Otherwise, returns false.
+ */
+bool device_property_read_bool(const struct device *dev, const char *propname)
+{
+	return fwnode_property_read_bool(dev_fwnode(dev), propname);
+}
+EXPORT_SYMBOL_GPL(device_property_read_bool);
+
+/**
+ * fwnode_property_read_bool - Return the value for a boolean property of a firmware node
+ * @fwnode: Firmware node whose property to check
+ * @propname: Name of the property
+ *
+ * Return if property @propname is true or false in the firmware description.
+ */
+bool fwnode_property_read_bool(const struct fwnode_handle *fwnode,
+			     const char *propname)
+{
+	bool ret;
+
+	if (IS_ERR_OR_NULL(fwnode))
+		return false;
+
+	ret = fwnode_call_bool_op(fwnode, property_read_bool, propname);
+	if (ret)
+		return ret;
+
+	return fwnode_call_bool_op(fwnode->secondary, property_read_bool, propname);
+}
+EXPORT_SYMBOL_GPL(fwnode_property_read_bool);
+
+/**
  * device_property_read_u8_array - return a u8 array property of a device
  * @dev: Device to get the property of
  * @propname: Name of the property
@@ -67,6 +118,9 @@ EXPORT_SYMBOL_GPL(fwnode_property_present);
  * Function reads an array of u8 properties with @propname from the device
  * firmware description and stores them to @val if found.
  *
+ * It's recommended to call device_property_count_u8() instead of calling
+ * this function with @val equals %NULL and @nval equals 0.
+ *
  * Return: number of values if @val was %NULL,
  *         %0 if the property was found (success),
  *	   %-EINVAL if given arguments are not valid,
@@ -75,7 +129,7 @@ EXPORT_SYMBOL_GPL(fwnode_property_present);
  *	   %-EOVERFLOW if the size of the property is not as expected.
  *	   %-ENXIO if no suitable firmware interface is present.
  */
-int device_property_read_u8_array(struct device *dev, const char *propname,
+int device_property_read_u8_array(const struct device *dev, const char *propname,
 				  u8 *val, size_t nval)
 {
 	return fwnode_property_read_u8_array(dev_fwnode(dev), propname, val, nval);
@@ -92,6 +146,9 @@ EXPORT_SYMBOL_GPL(device_property_read_u8_array);
  * Function reads an array of u16 properties with @propname from the device
  * firmware description and stores them to @val if found.
  *
+ * It's recommended to call device_property_count_u16() instead of calling
+ * this function with @val equals %NULL and @nval equals 0.
+ *
  * Return: number of values if @val was %NULL,
  *         %0 if the property was found (success),
  *	   %-EINVAL if given arguments are not valid,
@@ -100,7 +157,7 @@ EXPORT_SYMBOL_GPL(device_property_read_u8_array);
  *	   %-EOVERFLOW if the size of the property is not as expected.
  *	   %-ENXIO if no suitable firmware interface is present.
  */
-int device_property_read_u16_array(struct device *dev, const char *propname,
+int device_property_read_u16_array(const struct device *dev, const char *propname,
 				   u16 *val, size_t nval)
 {
 	return fwnode_property_read_u16_array(dev_fwnode(dev), propname, val, nval);
@@ -117,6 +174,9 @@ EXPORT_SYMBOL_GPL(device_property_read_u16_array);
  * Function reads an array of u32 properties with @propname from the device
  * firmware description and stores them to @val if found.
  *
+ * It's recommended to call device_property_count_u32() instead of calling
+ * this function with @val equals %NULL and @nval equals 0.
+ *
  * Return: number of values if @val was %NULL,
  *         %0 if the property was found (success),
  *	   %-EINVAL if given arguments are not valid,
@@ -125,7 +185,7 @@ EXPORT_SYMBOL_GPL(device_property_read_u16_array);
  *	   %-EOVERFLOW if the size of the property is not as expected.
  *	   %-ENXIO if no suitable firmware interface is present.
  */
-int device_property_read_u32_array(struct device *dev, const char *propname,
+int device_property_read_u32_array(const struct device *dev, const char *propname,
 				   u32 *val, size_t nval)
 {
 	return fwnode_property_read_u32_array(dev_fwnode(dev), propname, val, nval);
@@ -142,6 +202,9 @@ EXPORT_SYMBOL_GPL(device_property_read_u32_array);
  * Function reads an array of u64 properties with @propname from the device
  * firmware description and stores them to @val if found.
  *
+ * It's recommended to call device_property_count_u64() instead of calling
+ * this function with @val equals %NULL and @nval equals 0.
+ *
  * Return: number of values if @val was %NULL,
  *         %0 if the property was found (success),
  *	   %-EINVAL if given arguments are not valid,
@@ -150,7 +213,7 @@ EXPORT_SYMBOL_GPL(device_property_read_u32_array);
  *	   %-EOVERFLOW if the size of the property is not as expected.
  *	   %-ENXIO if no suitable firmware interface is present.
  */
-int device_property_read_u64_array(struct device *dev, const char *propname,
+int device_property_read_u64_array(const struct device *dev, const char *propname,
 				   u64 *val, size_t nval)
 {
 	return fwnode_property_read_u64_array(dev_fwnode(dev), propname, val, nval);
@@ -167,6 +230,9 @@ EXPORT_SYMBOL_GPL(device_property_read_u64_array);
  * Function reads an array of string properties with @propname from the device
  * firmware description and stores them to @val if found.
  *
+ * It's recommended to call device_property_string_array_count() instead of calling
+ * this function with @val equals %NULL and @nval equals 0.
+ *
  * Return: number of values read on success if @val is non-NULL,
  *	   number of values available on success if @val is NULL,
  *	   %-EINVAL if given arguments are not valid,
@@ -175,7 +241,7 @@ EXPORT_SYMBOL_GPL(device_property_read_u64_array);
  *	   %-EOVERFLOW if the size of the property is not as expected.
  *	   %-ENXIO if no suitable firmware interface is present.
  */
-int device_property_read_string_array(struct device *dev, const char *propname,
+int device_property_read_string_array(const struct device *dev, const char *propname,
 				      const char **val, size_t nval)
 {
 	return fwnode_property_read_string_array(dev_fwnode(dev), propname, val, nval);
@@ -197,7 +263,7 @@ EXPORT_SYMBOL_GPL(device_property_read_string_array);
  *	   %-EPROTO or %-EILSEQ if the property type is not a string.
  *	   %-ENXIO if no suitable firmware interface is present.
  */
-int device_property_read_string(struct device *dev, const char *propname,
+int device_property_read_string(const struct device *dev, const char *propname,
 				const char **val)
 {
 	return fwnode_property_read_string(dev_fwnode(dev), propname, val);
@@ -213,13 +279,13 @@ EXPORT_SYMBOL_GPL(device_property_read_string);
  * Find a given string in a string array and if it is found return the
  * index back.
  *
- * Return: %0 if the property was found (success),
+ * Return: index, starting from %0, if the property was found (success),
  *	   %-EINVAL if given arguments are not valid,
  *	   %-ENODATA if the property does not have a value,
  *	   %-EPROTO if the property is not an array of strings,
  *	   %-ENXIO if no suitable firmware interface is present.
  */
-int device_property_match_string(struct device *dev, const char *propname,
+int device_property_match_string(const struct device *dev, const char *propname,
 				 const char *string)
 {
 	return fwnode_property_match_string(dev_fwnode(dev), propname, string);
@@ -233,15 +299,16 @@ static int fwnode_property_read_int_array(const struct fwnode_handle *fwnode,
 {
 	int ret;
 
+	if (IS_ERR_OR_NULL(fwnode))
+		return -EINVAL;
+
 	ret = fwnode_call_int_op(fwnode, property_read_int_array, propname,
 				 elem_size, val, nval);
-	if (ret == -EINVAL && !IS_ERR_OR_NULL(fwnode) &&
-	    !IS_ERR_OR_NULL(fwnode->secondary))
-		ret = fwnode_call_int_op(
-			fwnode->secondary, property_read_int_array, propname,
-			elem_size, val, nval);
+	if (ret != -EINVAL)
+		return ret;
 
-	return ret;
+	return fwnode_call_int_op(fwnode->secondary, property_read_int_array, propname,
+				  elem_size, val, nval);
 }
 
 /**
@@ -254,6 +321,9 @@ static int fwnode_property_read_int_array(const struct fwnode_handle *fwnode,
  * Read an array of u8 properties with @propname from @fwnode and stores them to
  * @val if found.
  *
+ * It's recommended to call fwnode_property_count_u8() instead of calling
+ * this function with @val equals %NULL and @nval equals 0.
+ *
  * Return: number of values if @val was %NULL,
  *         %0 if the property was found (success),
  *	   %-EINVAL if given arguments are not valid,
@@ -280,6 +350,9 @@ EXPORT_SYMBOL_GPL(fwnode_property_read_u8_array);
  * Read an array of u16 properties with @propname from @fwnode and store them to
  * @val if found.
  *
+ * It's recommended to call fwnode_property_count_u16() instead of calling
+ * this function with @val equals %NULL and @nval equals 0.
+ *
  * Return: number of values if @val was %NULL,
  *         %0 if the property was found (success),
  *	   %-EINVAL if given arguments are not valid,
@@ -306,6 +379,9 @@ EXPORT_SYMBOL_GPL(fwnode_property_read_u16_array);
  * Read an array of u32 properties with @propname from @fwnode store them to
  * @val if found.
  *
+ * It's recommended to call fwnode_property_count_u32() instead of calling
+ * this function with @val equals %NULL and @nval equals 0.
+ *
  * Return: number of values if @val was %NULL,
  *         %0 if the property was found (success),
  *	   %-EINVAL if given arguments are not valid,
@@ -332,6 +408,9 @@ EXPORT_SYMBOL_GPL(fwnode_property_read_u32_array);
  * Read an array of u64 properties with @propname from @fwnode and store them to
  * @val if found.
  *
+ * It's recommended to call fwnode_property_count_u64() instead of calling
+ * this function with @val equals %NULL and @nval equals 0.
+ *
  * Return: number of values if @val was %NULL,
  *         %0 if the property was found (success),
  *	   %-EINVAL if given arguments are not valid,
@@ -358,6 +437,9 @@ EXPORT_SYMBOL_GPL(fwnode_property_read_u64_array);
  * Read an string list property @propname from the given firmware node and store
  * them to @val if found.
  *
+ * It's recommended to call fwnode_property_string_array_count() instead of calling
+ * this function with @val equals %NULL and @nval equals 0.
+ *
  * Return: number of values read on success if @val is non-NULL,
  *	   number of values available on success if @val is NULL,
  *	   %-EINVAL if given arguments are not valid,
@@ -372,14 +454,16 @@ int fwnode_property_read_string_array(const struct fwnode_handle *fwnode,
 {
 	int ret;
 
+	if (IS_ERR_OR_NULL(fwnode))
+		return -EINVAL;
+
 	ret = fwnode_call_int_op(fwnode, property_read_string_array, propname,
 				 val, nval);
-	if (ret == -EINVAL && !IS_ERR_OR_NULL(fwnode) &&
-	    !IS_ERR_OR_NULL(fwnode->secondary))
-		ret = fwnode_call_int_op(fwnode->secondary,
-					 property_read_string_array, propname,
-					 val, nval);
-	return ret;
+	if (ret != -EINVAL)
+		return ret;
+
+	return fwnode_call_int_op(fwnode->secondary, property_read_string_array, propname,
+				  val, nval);
 }
 EXPORT_SYMBOL_GPL(fwnode_property_read_string_array);
 
@@ -416,7 +500,7 @@ EXPORT_SYMBOL_GPL(fwnode_property_read_string);
  * Find a given string in a string array and if it is found return the
  * index back.
  *
- * Return: %0 if the property was found (success),
+ * Return: index, starting from %0, if the property was found (success),
  *	   %-EINVAL if given arguments are not valid,
  *	   %-ENODATA if the property does not have a value,
  *	   %-EPROTO if the property is not an array of strings,
@@ -428,7 +512,7 @@ int fwnode_property_match_string(const struct fwnode_handle *fwnode,
 	const char **values;
 	int nval, ret;
 
-	nval = fwnode_property_read_string_array(fwnode, propname, NULL, 0);
+	nval = fwnode_property_string_array_count(fwnode, propname);
 	if (nval < 0)
 		return nval;
 
@@ -441,35 +525,72 @@ int fwnode_property_match_string(const struct fwnode_handle *fwnode,
 
 	ret = fwnode_property_read_string_array(fwnode, propname, values, nval);
 	if (ret < 0)
-		goto out;
+		goto out_free;
 
 	ret = match_string(values, nval, string);
 	if (ret < 0)
 		ret = -ENODATA;
-out:
+
+out_free:
 	kfree(values);
 	return ret;
 }
 EXPORT_SYMBOL_GPL(fwnode_property_match_string);
 
 /**
+ * fwnode_property_match_property_string - find a property string value in an array and return index
+ * @fwnode: Firmware node to get the property of
+ * @propname: Name of the property holding the string value
+ * @array: String array to search in
+ * @n: Size of the @array
+ *
+ * Find a property string value in a given @array and if it is found return
+ * the index back.
+ *
+ * Return: index, starting from %0, if the string value was found in the @array (success),
+ *	   %-ENOENT when the string value was not found in the @array,
+ *	   %-EINVAL if given arguments are not valid,
+ *	   %-ENODATA if the property does not have a value,
+ *	   %-EPROTO or %-EILSEQ if the property is not a string,
+ *	   %-ENXIO if no suitable firmware interface is present.
+ */
+int fwnode_property_match_property_string(const struct fwnode_handle *fwnode,
+	const char *propname, const char * const *array, size_t n)
+{
+	const char *string;
+	int ret;
+
+	ret = fwnode_property_read_string(fwnode, propname, &string);
+	if (ret)
+		return ret;
+
+	ret = match_string(array, n, string);
+	if (ret < 0)
+		ret = -ENOENT;
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(fwnode_property_match_property_string);
+
+/**
  * fwnode_property_get_reference_args() - Find a reference with arguments
  * @fwnode:	Firmware node where to look for the reference
  * @prop:	The name of the property
  * @nargs_prop:	The name of the property telling the number of
  *		arguments in the referred node. NULL if @nargs is known,
- *		otherwise @nargs is ignored. Only relevant on OF.
+ *		otherwise @nargs is ignored.
  * @nargs:	Number of arguments. Ignored if @nargs_prop is non-NULL.
  * @index:	Index of the reference, from zero onwards.
  * @args:	Result structure with reference and integer arguments.
+ *		May be NULL.
  *
  * Obtain a reference based on a named property in an fwnode, with
  * integer arguments.
  *
- * Caller is responsible to call fwnode_handle_put() on the returned
- * args->fwnode pointer.
+ * The caller is responsible for calling fwnode_handle_put() on the returned
+ * @args->fwnode pointer.
  *
- * Returns: %0 on success
+ * Return: %0 on success
  *	    %-ENOENT when the index is out of bounds, the index has an empty
  *		     reference or the property was not found
  *	    %-EINVAL on parse error
@@ -479,7 +600,20 @@ int fwnode_property_get_reference_args(const struct fwnode_handle *fwnode,
 				       unsigned int nargs, unsigned int index,
 				       struct fwnode_reference_args *args)
 {
-	return fwnode_call_int_op(fwnode, get_reference_args, prop, nargs_prop,
+	int ret;
+
+	if (IS_ERR_OR_NULL(fwnode))
+		return -ENOENT;
+
+	ret = fwnode_call_int_op(fwnode, get_reference_args, prop, nargs_prop,
+				 nargs, index, args);
+	if (ret == 0)
+		return ret;
+
+	if (IS_ERR_OR_NULL(fwnode->secondary))
+		return ret;
+
+	return fwnode_call_int_op(fwnode->secondary, get_reference_args, prop, nargs_prop,
 				  nargs, index, args);
 }
 EXPORT_SYMBOL_GPL(fwnode_property_get_reference_args);
@@ -492,8 +626,11 @@ EXPORT_SYMBOL_GPL(fwnode_property_get_reference_args);
  *
  * @index can be used when the named reference holds a table of references.
  *
- * Returns pointer to the reference fwnode, or ERR_PTR. Caller is responsible to
- * call fwnode_handle_put() on the returned fwnode pointer.
+ * The caller is responsible for calling fwnode_handle_put() on the returned
+ * fwnode pointer.
+ *
+ * Return: a pointer to the reference fwnode, when found. Otherwise,
+ * returns an error pointer.
  */
 struct fwnode_handle *fwnode_find_reference(const struct fwnode_handle *fwnode,
 					    const char *name,
@@ -509,58 +646,10 @@ struct fwnode_handle *fwnode_find_reference(const struct fwnode_handle *fwnode,
 EXPORT_SYMBOL_GPL(fwnode_find_reference);
 
 /**
- * device_remove_properties - Remove properties from a device object.
- * @dev: Device whose properties to remove.
- *
- * The function removes properties previously associated to the device
- * firmware node with device_add_properties(). Memory allocated to the
- * properties will also be released.
- */
-void device_remove_properties(struct device *dev)
-{
-	struct fwnode_handle *fwnode = dev_fwnode(dev);
-
-	if (!fwnode)
-		return;
-
-	if (is_software_node(fwnode->secondary)) {
-		fwnode_remove_software_node(fwnode->secondary);
-		set_secondary_fwnode(dev, NULL);
-	}
-}
-EXPORT_SYMBOL_GPL(device_remove_properties);
-
-/**
- * device_add_properties - Add a collection of properties to a device object.
- * @dev: Device to add properties to.
- * @properties: Collection of properties to add.
- *
- * Associate a collection of device properties represented by @properties with
- * @dev. The function takes a copy of @properties.
- *
- * WARNING: The callers should not use this function if it is known that there
- * is no real firmware node associated with @dev! In that case the callers
- * should create a software node and assign it to @dev directly.
- */
-int device_add_properties(struct device *dev,
-			  const struct property_entry *properties)
-{
-	struct fwnode_handle *fwnode;
-
-	fwnode = fwnode_create_software_node(properties, NULL);
-	if (IS_ERR(fwnode))
-		return PTR_ERR(fwnode);
-
-	set_secondary_fwnode(dev, fwnode);
-	return 0;
-}
-EXPORT_SYMBOL_GPL(device_add_properties);
-
-/**
  * fwnode_get_name - Return the name of a node
  * @fwnode: The firmware node
  *
- * Returns a pointer to the node name.
+ * Return: a pointer to the node name, or %NULL.
  */
 const char *fwnode_get_name(const struct fwnode_handle *fwnode)
 {
@@ -572,7 +661,7 @@ EXPORT_SYMBOL_GPL(fwnode_get_name);
  * fwnode_get_name_prefix - Return the prefix of node for printing purposes
  * @fwnode: The firmware node
  *
- * Returns the prefix of a node, intended to be printed right before the node.
+ * Return: the prefix of a node, intended to be printed right before the node.
  * The prefix works also as a separator between the nodes.
  */
 const char *fwnode_get_name_prefix(const struct fwnode_handle *fwnode)
@@ -581,10 +670,41 @@ const char *fwnode_get_name_prefix(const struct fwnode_handle *fwnode)
 }
 
 /**
+ * fwnode_name_eq - Return true if node name is equal
+ * @fwnode: The firmware node
+ * @name: The name to which to compare the node name
+ *
+ * Compare the name provided as an argument to the name of the node, stopping
+ * the comparison at either NUL or '@' character, whichever comes first. This
+ * function is generally used for comparing node names while ignoring the
+ * possible unit address of the node.
+ *
+ * Return: true if the node name matches with the name provided in the @name
+ * argument, false otherwise.
+ */
+bool fwnode_name_eq(const struct fwnode_handle *fwnode, const char *name)
+{
+	const char *node_name;
+	ptrdiff_t len;
+
+	node_name = fwnode_get_name(fwnode);
+	if (!node_name)
+		return false;
+
+	len = strchrnul(node_name, '@') - node_name;
+
+	return str_has_prefix(node_name, name) == len;
+}
+EXPORT_SYMBOL_GPL(fwnode_name_eq);
+
+/**
  * fwnode_get_parent - Return parent firwmare node
  * @fwnode: Firmware whose parent is retrieved
  *
- * Return parent firmware node of the given node if possible or %NULL if no
+ * The caller is responsible for calling fwnode_handle_put() on the returned
+ * fwnode pointer.
+ *
+ * Return: parent firmware node of the given node if possible or %NULL if no
  * parent was available.
  */
 struct fwnode_handle *fwnode_get_parent(const struct fwnode_handle *fwnode)
@@ -601,8 +721,12 @@ EXPORT_SYMBOL_GPL(fwnode_get_parent);
  * on the passed node, making it suitable for iterating through a
  * node's parents.
  *
- * Returns a node pointer with refcount incremented, use
- * fwnode_handle_node() on it when done.
+ * The caller is responsible for calling fwnode_handle_put() on the returned
+ * fwnode pointer. Note that this function also puts a reference to @fwnode
+ * unconditionally.
+ *
+ * Return: parent firmware node of the given node if possible or %NULL if no
+ * parent was available.
  */
 struct fwnode_handle *fwnode_get_next_parent(struct fwnode_handle *fwnode)
 {
@@ -618,17 +742,15 @@ EXPORT_SYMBOL_GPL(fwnode_get_next_parent);
  * fwnode_count_parents - Return the number of parents a node has
  * @fwnode: The node the parents of which are to be counted
  *
- * Returns the number of parents a node has.
+ * Return: the number of parents a node has.
  */
 unsigned int fwnode_count_parents(const struct fwnode_handle *fwnode)
 {
-	struct fwnode_handle *__fwnode;
-	unsigned int count;
-
-	__fwnode = fwnode_get_parent(fwnode);
+	struct fwnode_handle *parent;
+	unsigned int count = 0;
 
-	for (count = 0; __fwnode; count++)
-		__fwnode = fwnode_get_next_parent(__fwnode);
+	fwnode_for_each_parent_node(fwnode, parent)
+		count++;
 
 	return count;
 }
@@ -639,24 +761,26 @@ EXPORT_SYMBOL_GPL(fwnode_count_parents);
  * @fwnode: The node the parent of which is requested
  * @depth: Distance of the parent from the node
  *
- * Returns the nth parent of a node. If there is no parent at the requested
+ * The caller is responsible for calling fwnode_handle_put() on the returned
+ * fwnode pointer.
+ *
+ * Return: the nth parent of a node. If there is no parent at the requested
  * @depth, %NULL is returned. If @depth is 0, the functionality is equivalent to
  * fwnode_handle_get(). For @depth == 1, it is fwnode_get_parent() and so on.
- *
- * The caller is responsible for calling fwnode_handle_put() for the returned
- * node.
  */
 struct fwnode_handle *fwnode_get_nth_parent(struct fwnode_handle *fwnode,
 					    unsigned int depth)
 {
-	unsigned int i;
+	struct fwnode_handle *parent;
 
-	fwnode_handle_get(fwnode);
+	if (depth == 0)
+		return fwnode_handle_get(fwnode);
 
-	for (i = 0; i < depth && fwnode; i++)
-		fwnode = fwnode_get_next_parent(fwnode);
-
-	return fwnode;
+	fwnode_for_each_parent_node(fwnode, parent) {
+		if (--depth == 0)
+			return parent;
+	}
+	return NULL;
 }
 EXPORT_SYMBOL_GPL(fwnode_get_nth_parent);
 
@@ -664,6 +788,10 @@ EXPORT_SYMBOL_GPL(fwnode_get_nth_parent);
  * fwnode_get_next_child_node - Return the next child node handle for a node
  * @fwnode: Firmware node to find the next child node for.
  * @child: Handle to one of the node's child nodes or a %NULL handle.
+ *
+ * The caller is responsible for calling fwnode_handle_put() on the returned
+ * fwnode pointer. Note that this function also puts a reference to @child
+ * unconditionally.
  */
 struct fwnode_handle *
 fwnode_get_next_child_node(const struct fwnode_handle *fwnode,
@@ -674,10 +802,13 @@ fwnode_get_next_child_node(const struct fwnode_handle *fwnode,
 EXPORT_SYMBOL_GPL(fwnode_get_next_child_node);
 
 /**
- * fwnode_get_next_available_child_node - Return the next
- * available child node handle for a node
+ * fwnode_get_next_available_child_node - Return the next available child node handle for a node
  * @fwnode: Firmware node to find the next child node for.
  * @child: Handle to one of the node's child nodes or a %NULL handle.
+ *
+ * The caller is responsible for calling fwnode_handle_put() on the returned
+ * fwnode pointer. Note that this function also puts a reference to @child
+ * unconditionally.
  */
 struct fwnode_handle *
 fwnode_get_next_available_child_node(const struct fwnode_handle *fwnode,
@@ -685,15 +816,14 @@ fwnode_get_next_available_child_node(const struct fwnode_handle *fwnode,
 {
 	struct fwnode_handle *next_child = child;
 
-	if (!fwnode)
+	if (IS_ERR_OR_NULL(fwnode))
 		return NULL;
 
 	do {
 		next_child = fwnode_get_next_child_node(fwnode, next_child);
-
-		if (!next_child || fwnode_device_is_available(next_child))
-			break;
-	} while (next_child);
+		if (!next_child)
+			return NULL;
+	} while (!fwnode_device_is_available(next_child));
 
 	return next_child;
 }
@@ -702,20 +832,28 @@ EXPORT_SYMBOL_GPL(fwnode_get_next_available_child_node);
 /**
  * device_get_next_child_node - Return the next child node handle for a device
  * @dev: Device to find the next child node for.
- * @child: Handle to one of the device's child nodes or a null handle.
+ * @child: Handle to one of the device's child nodes or a %NULL handle.
+ *
+ * The caller is responsible for calling fwnode_handle_put() on the returned
+ * fwnode pointer. Note that this function also puts a reference to @child
+ * unconditionally.
  */
-struct fwnode_handle *device_get_next_child_node(struct device *dev,
+struct fwnode_handle *device_get_next_child_node(const struct device *dev,
 						 struct fwnode_handle *child)
 {
-	struct acpi_device *adev = ACPI_COMPANION(dev);
-	struct fwnode_handle *fwnode = NULL;
+	const struct fwnode_handle *fwnode = dev_fwnode(dev);
+	struct fwnode_handle *next;
+
+	if (IS_ERR_OR_NULL(fwnode))
+		return NULL;
 
-	if (dev->of_node)
-		fwnode = &dev->of_node->fwnode;
-	else if (adev)
-		fwnode = acpi_fwnode_handle(adev);
+	/* Try to find a child in primary fwnode */
+	next = fwnode_get_next_child_node(fwnode, child);
+	if (next)
+		return next;
 
-	return fwnode_get_next_child_node(fwnode, child);
+	/* When no more children in primary, continue with secondary */
+	return fwnode_get_next_child_node(fwnode->secondary, child);
 }
 EXPORT_SYMBOL_GPL(device_get_next_child_node);
 
@@ -723,6 +861,9 @@ EXPORT_SYMBOL_GPL(device_get_next_child_node);
  * fwnode_get_named_child_node - Return first matching named child node handle
  * @fwnode: Firmware node to find the named child node for.
  * @childname: String to match child node name against.
+ *
+ * The caller is responsible for calling fwnode_handle_put() on the returned
+ * fwnode pointer.
  */
 struct fwnode_handle *
 fwnode_get_named_child_node(const struct fwnode_handle *fwnode,
@@ -736,8 +877,11 @@ EXPORT_SYMBOL_GPL(fwnode_get_named_child_node);
  * device_get_named_child_node - Return first matching named child node handle
  * @dev: Device to find the named child node for.
  * @childname: String to match child node name against.
+ *
+ * The caller is responsible for calling fwnode_handle_put() on the returned
+ * fwnode pointer.
  */
-struct fwnode_handle *device_get_named_child_node(struct device *dev,
+struct fwnode_handle *device_get_named_child_node(const struct device *dev,
 						  const char *childname)
 {
 	return fwnode_get_named_child_node(dev_fwnode(dev), childname);
@@ -748,7 +892,10 @@ EXPORT_SYMBOL_GPL(device_get_named_child_node);
  * fwnode_handle_get - Obtain a reference to a device node
  * @fwnode: Pointer to the device node to obtain the reference to.
  *
- * Returns the fwnode handle.
+ * The caller is responsible for calling fwnode_handle_put() on the returned
+ * fwnode pointer.
+ *
+ * Return: the fwnode handle.
  */
 struct fwnode_handle *fwnode_handle_get(struct fwnode_handle *fwnode)
 {
@@ -760,71 +907,83 @@ struct fwnode_handle *fwnode_handle_get(struct fwnode_handle *fwnode)
 EXPORT_SYMBOL_GPL(fwnode_handle_get);
 
 /**
- * fwnode_handle_put - Drop reference to a device node
- * @fwnode: Pointer to the device node to drop the reference to.
- *
- * This has to be used when terminating device_for_each_child_node() iteration
- * with break or return to prevent stale device node references from being left
- * behind.
- */
-void fwnode_handle_put(struct fwnode_handle *fwnode)
-{
-	fwnode_call_void_op(fwnode, put);
-}
-EXPORT_SYMBOL_GPL(fwnode_handle_put);
-
-/**
  * fwnode_device_is_available - check if a device is available for use
  * @fwnode: Pointer to the fwnode of the device.
+ *
+ * Return: true if device is available for use. Otherwise, returns false.
+ *
+ * For fwnode node types that don't implement the .device_is_available()
+ * operation, this function returns true.
  */
 bool fwnode_device_is_available(const struct fwnode_handle *fwnode)
 {
+	if (IS_ERR_OR_NULL(fwnode))
+		return false;
+
+	if (!fwnode_has_op(fwnode, device_is_available))
+		return true;
+
 	return fwnode_call_bool_op(fwnode, device_is_available);
 }
 EXPORT_SYMBOL_GPL(fwnode_device_is_available);
 
 /**
- * device_get_child_node_count - return the number of child nodes for device
- * @dev: Device to cound the child nodes for
+ * fwnode_get_child_node_count - return the number of child nodes for a given firmware node
+ * @fwnode: Pointer to the parent firmware node
+ *
+ * Return: the number of child nodes for a given firmware node.
  */
-unsigned int device_get_child_node_count(struct device *dev)
+unsigned int fwnode_get_child_node_count(const struct fwnode_handle *fwnode)
 {
 	struct fwnode_handle *child;
 	unsigned int count = 0;
 
-	device_for_each_child_node(dev, child)
+	fwnode_for_each_child_node(fwnode, child)
 		count++;
 
 	return count;
 }
-EXPORT_SYMBOL_GPL(device_get_child_node_count);
+EXPORT_SYMBOL_GPL(fwnode_get_child_node_count);
 
-bool device_dma_supported(struct device *dev)
+/**
+ * fwnode_get_named_child_node_count - number of child nodes with given name
+ * @fwnode: Node which child nodes are counted.
+ * @name: String to match child node name against.
+ *
+ * Scan child nodes and count all the nodes with a specific name. Potential
+ * 'number' -ending after the 'at sign' for scanned names is ignored.
+ * E.g.::
+ *   fwnode_get_named_child_node_count(fwnode, "channel");
+ * would match all the nodes::
+ *   channel { }, channel@0 {}, channel@0xabba {}...
+ *
+ * Return: the number of child nodes with a matching name for a given device.
+ */
+unsigned int fwnode_get_named_child_node_count(const struct fwnode_handle *fwnode,
+					       const char *name)
 {
-	/* For DT, this is always supported.
-	 * For ACPI, this depends on CCA, which
-	 * is determined by the acpi_dma_supported().
-	 */
-	if (IS_ENABLED(CONFIG_OF) && dev->of_node)
-		return true;
+	struct fwnode_handle *child;
+	unsigned int count = 0;
 
-	return acpi_dma_supported(ACPI_COMPANION(dev));
+	fwnode_for_each_named_child_node(fwnode, child, name)
+		count++;
+
+	return count;
 }
-EXPORT_SYMBOL_GPL(device_dma_supported);
+EXPORT_SYMBOL_GPL(fwnode_get_named_child_node_count);
 
-enum dev_dma_attr device_get_dma_attr(struct device *dev)
+bool device_dma_supported(const struct device *dev)
 {
-	enum dev_dma_attr attr = DEV_DMA_NOT_SUPPORTED;
+	return fwnode_call_bool_op(dev_fwnode(dev), device_dma_supported);
+}
+EXPORT_SYMBOL_GPL(device_dma_supported);
 
-	if (IS_ENABLED(CONFIG_OF) && dev->of_node) {
-		if (of_dma_is_coherent(dev->of_node))
-			attr = DEV_DMA_COHERENT;
-		else
-			attr = DEV_DMA_NON_COHERENT;
-	} else
-		attr = acpi_get_dma_attr(ACPI_COMPANION(dev));
+enum dev_dma_attr device_get_dma_attr(const struct device *dev)
+{
+	if (!fwnode_has_op(dev_fwnode(dev), device_get_dma_attr))
+		return DEV_DMA_NOT_SUPPORTED;
 
-	return attr;
+	return fwnode_call_int_op(dev_fwnode(dev), device_get_dma_attr);
 }
 EXPORT_SYMBOL_GPL(device_get_dma_attr);
 
@@ -836,7 +995,7 @@ EXPORT_SYMBOL_GPL(device_get_dma_attr);
  * 'phy-connection-type', and return its index in phy_modes table, or errno in
  * error case.
  */
-int fwnode_get_phy_mode(struct fwnode_handle *fwnode)
+int fwnode_get_phy_mode(const struct fwnode_handle *fwnode)
 {
 	const char *pm;
 	int err, i;
@@ -870,106 +1029,109 @@ int device_get_phy_mode(struct device *dev)
 }
 EXPORT_SYMBOL_GPL(device_get_phy_mode);
 
-static void *fwnode_get_mac_addr(struct fwnode_handle *fwnode,
-				 const char *name, char *addr,
-				 int alen)
-{
-	int ret = fwnode_property_read_u8_array(fwnode, name, addr, alen);
-
-	if (ret == 0 && alen == ETH_ALEN && is_valid_ether_addr(addr))
-		return addr;
-	return NULL;
-}
-
 /**
- * fwnode_get_mac_address - Get the MAC from the firmware node
+ * fwnode_iomap - Maps the memory mapped IO for a given fwnode
  * @fwnode:	Pointer to the firmware node
- * @addr:	Address of buffer to store the MAC in
- * @alen:	Length of the buffer pointed to by addr, should be ETH_ALEN
- *
- * Search the firmware node for the best MAC address to use.  'mac-address' is
- * checked first, because that is supposed to contain to "most recent" MAC
- * address. If that isn't set, then 'local-mac-address' is checked next,
- * because that is the default address.  If that isn't set, then the obsolete
- * 'address' is checked, just in case we're using an old device tree.
- *
- * Note that the 'address' property is supposed to contain a virtual address of
- * the register set, but some DTS files have redefined that property to be the
- * MAC address.
- *
- * All-zero MAC addresses are rejected, because those could be properties that
- * exist in the firmware tables, but were not updated by the firmware.  For
- * example, the DTS could define 'mac-address' and 'local-mac-address', with
- * zero MAC addresses.  Some older U-Boots only initialized 'local-mac-address'.
- * In this case, the real MAC is in 'local-mac-address', and 'mac-address'
- * exists but is all zeros.
-*/
-void *fwnode_get_mac_address(struct fwnode_handle *fwnode, char *addr, int alen)
+ * @index:	Index of the IO range
+ *
+ * Return: a pointer to the mapped memory.
+ */
+void __iomem *fwnode_iomap(struct fwnode_handle *fwnode, int index)
 {
-	char *res;
-
-	res = fwnode_get_mac_addr(fwnode, "mac-address", addr, alen);
-	if (res)
-		return res;
-
-	res = fwnode_get_mac_addr(fwnode, "local-mac-address", addr, alen);
-	if (res)
-		return res;
-
-	return fwnode_get_mac_addr(fwnode, "address", addr, alen);
+	return fwnode_call_ptr_op(fwnode, iomap, index);
 }
-EXPORT_SYMBOL(fwnode_get_mac_address);
+EXPORT_SYMBOL(fwnode_iomap);
 
 /**
- * device_get_mac_address - Get the MAC for a given device
- * @dev:	Pointer to the device
- * @addr:	Address of buffer to store the MAC in
- * @alen:	Length of the buffer pointed to by addr, should be ETH_ALEN
+ * fwnode_irq_get - Get IRQ directly from a fwnode
+ * @fwnode:	Pointer to the firmware node
+ * @index:	Zero-based index of the IRQ
+ *
+ * Return: Linux IRQ number on success. Negative errno on failure.
  */
-void *device_get_mac_address(struct device *dev, char *addr, int alen)
+int fwnode_irq_get(const struct fwnode_handle *fwnode, unsigned int index)
 {
-	return fwnode_get_mac_address(dev_fwnode(dev), addr, alen);
+	int ret;
+
+	ret = fwnode_call_int_op(fwnode, irq_get, index);
+	/* We treat mapping errors as invalid case */
+	if (ret == 0)
+		return -EINVAL;
+
+	return ret;
 }
-EXPORT_SYMBOL(device_get_mac_address);
+EXPORT_SYMBOL(fwnode_irq_get);
 
 /**
- * fwnode_irq_get - Get IRQ directly from a fwnode
+ * fwnode_irq_get_byname - Get IRQ from a fwnode using its name
  * @fwnode:	Pointer to the firmware node
- * @index:	Zero-based index of the IRQ
+ * @name:	IRQ name
+ *
+ * Description:
+ * Find a match to the string @name in the 'interrupt-names' string array
+ * in _DSD for ACPI, or of_node for Device Tree. Then get the Linux IRQ
+ * number of the IRQ resource corresponding to the index of the matched
+ * string.
  *
- * Returns Linux IRQ number on success. Other values are determined
- * accordingly to acpi_/of_ irq_get() operation.
+ * Return: Linux IRQ number on success, or negative errno otherwise.
  */
-int fwnode_irq_get(struct fwnode_handle *fwnode, unsigned int index)
+int fwnode_irq_get_byname(const struct fwnode_handle *fwnode, const char *name)
 {
-	struct device_node *of_node = to_of_node(fwnode);
-	struct resource res;
-	int ret;
+	int index;
 
-	if (IS_ENABLED(CONFIG_OF) && of_node)
-		return of_irq_get(of_node, index);
+	if (!name)
+		return -EINVAL;
 
-	ret = acpi_irq_get(ACPI_HANDLE_FWNODE(fwnode), index, &res);
-	if (ret)
-		return ret;
+	index = fwnode_property_match_string(fwnode, "interrupt-names",  name);
+	if (index < 0)
+		return index;
 
-	return res.start;
+	return fwnode_irq_get(fwnode, index);
 }
-EXPORT_SYMBOL(fwnode_irq_get);
+EXPORT_SYMBOL(fwnode_irq_get_byname);
 
 /**
  * fwnode_graph_get_next_endpoint - Get next endpoint firmware node
  * @fwnode: Pointer to the parent firmware node
  * @prev: Previous endpoint node or %NULL to get the first
  *
- * Returns an endpoint firmware node pointer or %NULL if no more endpoints
+ * The caller is responsible for calling fwnode_handle_put() on the returned
+ * fwnode pointer. Note that this function also puts a reference to @prev
+ * unconditionally.
+ *
+ * Return: an endpoint firmware node pointer or %NULL if no more endpoints
  * are available.
  */
 struct fwnode_handle *
 fwnode_graph_get_next_endpoint(const struct fwnode_handle *fwnode,
 			       struct fwnode_handle *prev)
 {
-	return fwnode_call_ptr_op(fwnode, graph_get_next_endpoint, prev);
+	struct fwnode_handle *ep, *port_parent = NULL;
+	const struct fwnode_handle *parent;
+
+	/*
+	 * If this function is in a loop and the previous iteration returned
+	 * an endpoint from fwnode->secondary, then we need to use the secondary
+	 * as parent rather than @fwnode.
+	 */
+	if (prev) {
+		port_parent = fwnode_graph_get_port_parent(prev);
+		parent = port_parent;
+	} else {
+		parent = fwnode;
+	}
+	if (IS_ERR_OR_NULL(parent))
+		return NULL;
+
+	ep = fwnode_call_ptr_op(parent, graph_get_next_endpoint, prev);
+	if (ep)
+		goto out_put_port_parent;
+
+	ep = fwnode_graph_get_next_endpoint(parent->secondary, NULL);
+
+out_put_port_parent:
+	fwnode_handle_put(port_parent);
+	return ep;
 }
 EXPORT_SYMBOL_GPL(fwnode_graph_get_next_endpoint);
 
@@ -977,6 +1139,9 @@ EXPORT_SYMBOL_GPL(fwnode_graph_get_next_endpoint);
  * fwnode_graph_get_port_parent - Return the device fwnode of a port endpoint
  * @endpoint: Endpoint firmware node of the port
  *
+ * The caller is responsible for calling fwnode_handle_put() on the returned
+ * fwnode pointer.
+ *
  * Return: the firmware node of the device the @endpoint belongs to.
  */
 struct fwnode_handle *
@@ -998,6 +1163,9 @@ EXPORT_SYMBOL_GPL(fwnode_graph_get_port_parent);
  * @fwnode: Endpoint firmware node pointing to the remote endpoint
  *
  * Extracts firmware node of a remote device the @fwnode points to.
+ *
+ * The caller is responsible for calling fwnode_handle_put() on the returned
+ * fwnode pointer.
  */
 struct fwnode_handle *
 fwnode_graph_get_remote_port_parent(const struct fwnode_handle *fwnode)
@@ -1018,6 +1186,9 @@ EXPORT_SYMBOL_GPL(fwnode_graph_get_remote_port_parent);
  * @fwnode: Endpoint firmware node pointing to the remote endpoint
  *
  * Extracts firmware node of a remote port the @fwnode points to.
+ *
+ * The caller is responsible for calling fwnode_handle_put() on the returned
+ * fwnode pointer.
  */
 struct fwnode_handle *
 fwnode_graph_get_remote_port(const struct fwnode_handle *fwnode)
@@ -1031,6 +1202,9 @@ EXPORT_SYMBOL_GPL(fwnode_graph_get_remote_port);
  * @fwnode: Endpoint firmware node pointing to the remote endpoint
  *
  * Extracts firmware node of a remote endpoint the @fwnode points to.
+ *
+ * The caller is responsible for calling fwnode_handle_put() on the returned
+ * fwnode pointer.
  */
 struct fwnode_handle *
 fwnode_graph_get_remote_endpoint(const struct fwnode_handle *fwnode)
@@ -1039,43 +1213,17 @@ fwnode_graph_get_remote_endpoint(const struct fwnode_handle *fwnode)
 }
 EXPORT_SYMBOL_GPL(fwnode_graph_get_remote_endpoint);
 
-/**
- * fwnode_graph_get_remote_node - get remote parent node for given port/endpoint
- * @fwnode: pointer to parent fwnode_handle containing graph port/endpoint
- * @port_id: identifier of the parent port node
- * @endpoint_id: identifier of the endpoint node
- *
- * Return: Remote fwnode handle associated with remote endpoint node linked
- *	   to @node. Use fwnode_node_put() on it when done.
- */
-struct fwnode_handle *
-fwnode_graph_get_remote_node(const struct fwnode_handle *fwnode, u32 port_id,
-			     u32 endpoint_id)
+static bool fwnode_graph_remote_available(struct fwnode_handle *ep)
 {
-	struct fwnode_handle *endpoint = NULL;
+	struct fwnode_handle *dev_node;
+	bool available;
 
-	while ((endpoint = fwnode_graph_get_next_endpoint(fwnode, endpoint))) {
-		struct fwnode_endpoint fwnode_ep;
-		struct fwnode_handle *remote;
-		int ret;
-
-		ret = fwnode_graph_parse_endpoint(endpoint, &fwnode_ep);
-		if (ret < 0)
-			continue;
-
-		if (fwnode_ep.port != port_id || fwnode_ep.id != endpoint_id)
-			continue;
-
-		remote = fwnode_graph_get_remote_port_parent(endpoint);
-		if (!remote)
-			return NULL;
+	dev_node = fwnode_graph_get_remote_port_parent(ep);
+	available = fwnode_device_is_available(dev_node);
+	fwnode_handle_put(dev_node);
 
-		return fwnode_device_is_available(remote) ? remote : NULL;
-	}
-
-	return NULL;
+	return available;
 }
-EXPORT_SYMBOL_GPL(fwnode_graph_get_remote_node);
 
 /**
  * fwnode_graph_get_endpoint_by_id - get endpoint by port and endpoint numbers
@@ -1084,42 +1232,34 @@ EXPORT_SYMBOL_GPL(fwnode_graph_get_remote_node);
  * @endpoint: identifier of the endpoint node under the port node
  * @flags: fwnode lookup flags
  *
- * Return the fwnode handle of the local endpoint corresponding the port and
- * endpoint IDs or NULL if not found.
+ * The caller is responsible for calling fwnode_handle_put() on the returned
+ * fwnode pointer.
+ *
+ * Return: the fwnode handle of the local endpoint corresponding the port and
+ * endpoint IDs or %NULL if not found.
  *
  * If FWNODE_GRAPH_ENDPOINT_NEXT is passed in @flags and the specified endpoint
  * has not been found, look for the closest endpoint ID greater than the
  * specified one and return the endpoint that corresponds to it, if present.
  *
- * Do not return endpoints that belong to disabled devices, unless
- * FWNODE_GRAPH_DEVICE_DISABLED is passed in @flags.
- *
- * The returned endpoint needs to be released by calling fwnode_handle_put() on
- * it when it is not needed any more.
+ * Does not return endpoints that belong to disabled devices or endpoints that
+ * are unconnected, unless FWNODE_GRAPH_DEVICE_DISABLED is passed in @flags.
  */
 struct fwnode_handle *
 fwnode_graph_get_endpoint_by_id(const struct fwnode_handle *fwnode,
 				u32 port, u32 endpoint, unsigned long flags)
 {
-	struct fwnode_handle *ep = NULL, *best_ep = NULL;
+	struct fwnode_handle *ep, *best_ep = NULL;
 	unsigned int best_ep_id = 0;
 	bool endpoint_next = flags & FWNODE_GRAPH_ENDPOINT_NEXT;
 	bool enabled_only = !(flags & FWNODE_GRAPH_DEVICE_DISABLED);
 
-	while ((ep = fwnode_graph_get_next_endpoint(fwnode, ep))) {
+	fwnode_graph_for_each_endpoint(fwnode, ep) {
 		struct fwnode_endpoint fwnode_ep = { 0 };
 		int ret;
 
-		if (enabled_only) {
-			struct fwnode_handle *dev_node;
-			bool available;
-
-			dev_node = fwnode_graph_get_remote_port_parent(ep);
-			available = fwnode_device_is_available(dev_node);
-			fwnode_handle_put(dev_node);
-			if (!available)
-				continue;
-		}
+		if (enabled_only && !fwnode_graph_remote_available(ep))
+			continue;
 
 		ret = fwnode_graph_parse_endpoint(ep, &fwnode_ep);
 		if (ret < 0)
@@ -1153,6 +1293,31 @@ fwnode_graph_get_endpoint_by_id(const struct fwnode_handle *fwnode,
 EXPORT_SYMBOL_GPL(fwnode_graph_get_endpoint_by_id);
 
 /**
+ * fwnode_graph_get_endpoint_count - Count endpoints on a device node
+ * @fwnode: The node related to a device
+ * @flags: fwnode lookup flags
+ * Count endpoints in a device node.
+ *
+ * If FWNODE_GRAPH_DEVICE_DISABLED flag is specified, also unconnected endpoints
+ * and endpoints connected to disabled devices are counted.
+ */
+unsigned int fwnode_graph_get_endpoint_count(const struct fwnode_handle *fwnode,
+					     unsigned long flags)
+{
+	struct fwnode_handle *ep;
+	unsigned int count = 0;
+
+	fwnode_graph_for_each_endpoint(fwnode, ep) {
+		if (flags & FWNODE_GRAPH_DEVICE_DISABLED ||
+		    fwnode_graph_remote_available(ep))
+			count++;
+	}
+
+	return count;
+}
+EXPORT_SYMBOL_GPL(fwnode_graph_get_endpoint_count);
+
+/**
  * fwnode_graph_parse_endpoint - parse common endpoint node properties
  * @fwnode: pointer to endpoint fwnode_handle
  * @endpoint: pointer to the fwnode endpoint data structure
@@ -1170,8 +1335,148 @@ int fwnode_graph_parse_endpoint(const struct fwnode_handle *fwnode,
 }
 EXPORT_SYMBOL(fwnode_graph_parse_endpoint);
 
-const void *device_get_match_data(struct device *dev)
+const void *device_get_match_data(const struct device *dev)
 {
 	return fwnode_call_ptr_op(dev_fwnode(dev), device_get_match_data, dev);
 }
 EXPORT_SYMBOL_GPL(device_get_match_data);
+
+static unsigned int fwnode_graph_devcon_matches(const struct fwnode_handle *fwnode,
+						const char *con_id, void *data,
+						devcon_match_fn_t match,
+						void **matches,
+						unsigned int matches_len)
+{
+	struct fwnode_handle *node;
+	struct fwnode_handle *ep;
+	unsigned int count = 0;
+	void *ret;
+
+	fwnode_graph_for_each_endpoint(fwnode, ep) {
+		if (matches && count >= matches_len) {
+			fwnode_handle_put(ep);
+			break;
+		}
+
+		node = fwnode_graph_get_remote_port_parent(ep);
+		if (!fwnode_device_is_available(node)) {
+			fwnode_handle_put(node);
+			continue;
+		}
+
+		ret = match(node, con_id, data);
+		fwnode_handle_put(node);
+		if (ret) {
+			if (matches)
+				matches[count] = ret;
+			count++;
+		}
+	}
+	return count;
+}
+
+static unsigned int fwnode_devcon_matches(const struct fwnode_handle *fwnode,
+					  const char *con_id, void *data,
+					  devcon_match_fn_t match,
+					  void **matches,
+					  unsigned int matches_len)
+{
+	struct fwnode_handle *node;
+	unsigned int count = 0;
+	unsigned int i;
+	void *ret;
+
+	for (i = 0; ; i++) {
+		if (matches && count >= matches_len)
+			break;
+
+		node = fwnode_find_reference(fwnode, con_id, i);
+		if (IS_ERR(node))
+			break;
+
+		ret = match(node, NULL, data);
+		fwnode_handle_put(node);
+		if (ret) {
+			if (matches)
+				matches[count] = ret;
+			count++;
+		}
+	}
+
+	return count;
+}
+
+/**
+ * fwnode_connection_find_match - Find connection from a device node
+ * @fwnode: Device node with the connection
+ * @con_id: Identifier for the connection
+ * @data: Data for the match function
+ * @match: Function to check and convert the connection description
+ *
+ * Find a connection with unique identifier @con_id between @fwnode and another
+ * device node. @match will be used to convert the connection description to
+ * data the caller is expecting to be returned.
+ */
+void *fwnode_connection_find_match(const struct fwnode_handle *fwnode,
+				   const char *con_id, void *data,
+				   devcon_match_fn_t match)
+{
+	unsigned int count;
+	void *ret;
+
+	if (!fwnode || !match)
+		return NULL;
+
+	count = fwnode_graph_devcon_matches(fwnode, con_id, data, match, &ret, 1);
+	if (count)
+		return ret;
+
+	count = fwnode_devcon_matches(fwnode, con_id, data, match, &ret, 1);
+	return count ? ret : NULL;
+}
+EXPORT_SYMBOL_GPL(fwnode_connection_find_match);
+
+/**
+ * fwnode_connection_find_matches - Find connections from a device node
+ * @fwnode: Device node with the connection
+ * @con_id: Identifier for the connection
+ * @data: Data for the match function
+ * @match: Function to check and convert the connection description
+ * @matches: (Optional) array of pointers to fill with matches
+ * @matches_len: Length of @matches
+ *
+ * Find up to @matches_len connections with unique identifier @con_id between
+ * @fwnode and other device nodes. @match will be used to convert the
+ * connection description to data the caller is expecting to be returned
+ * through the @matches array.
+ *
+ * If @matches is %NULL @matches_len is ignored and the total number of resolved
+ * matches is returned.
+ *
+ * Return: Number of matches resolved, or negative errno.
+ */
+int fwnode_connection_find_matches(const struct fwnode_handle *fwnode,
+				   const char *con_id, void *data,
+				   devcon_match_fn_t match,
+				   void **matches, unsigned int matches_len)
+{
+	unsigned int count_graph;
+	unsigned int count_ref;
+
+	if (!fwnode || !match)
+		return -EINVAL;
+
+	count_graph = fwnode_graph_devcon_matches(fwnode, con_id, data, match,
+						  matches, matches_len);
+
+	if (matches) {
+		matches += count_graph;
+		matches_len -= count_graph;
+	}
+
+	count_ref = fwnode_devcon_matches(fwnode, con_id, data, match,
+					  matches, matches_len);
+
+	return count_graph + count_ref;
+}
+EXPORT_SYMBOL_GPL(fwnode_connection_find_matches);
diff --git a/drivers/base/regmap/Kconfig b/drivers/base/regmap/Kconfig
index 0fd6f97ee523..ffb2ef488298 100644
--- a/drivers/base/regmap/Kconfig
+++ b/drivers/base/regmap/Kconfig
@@ -4,14 +4,32 @@
 # subsystems should select the appropriate symbols.
 
 config REGMAP
-	default y if (REGMAP_I2C || REGMAP_SPI || REGMAP_SPMI || REGMAP_W1 || REGMAP_AC97 || REGMAP_MMIO || REGMAP_IRQ || REGMAP_SCCB || REGMAP_I3C)
-	select IRQ_DOMAIN if REGMAP_IRQ
 	bool
+	default y if (REGMAP_I2C || REGMAP_SPI || REGMAP_SPMI || REGMAP_W1 || REGMAP_AC97 || REGMAP_MMIO || REGMAP_IRQ || REGMAP_SOUNDWIRE || REGMAP_SOUNDWIRE_MBQ || REGMAP_SCCB || REGMAP_I3C || REGMAP_SPI_AVMM || REGMAP_MDIO || REGMAP_FSI)
+	help
+	  Enable support for the Register Map (regmap) access API.
 
-config REGCACHE_COMPRESSED
-	select LZO_COMPRESS
-	select LZO_DECOMPRESS
-	bool
+	  Usually, this option is automatically selected when needed.
+	  However, you may want to enable it manually for running the regmap
+	  KUnit tests.
+
+	  If unsure, say N.
+
+config REGMAP_KUNIT
+	tristate "KUnit tests for regmap"
+	depends on KUNIT && REGMAP
+	default KUNIT_ALL_TESTS
+	select REGMAP_RAM
+
+config REGMAP_BUILD
+	bool "Enable regmap build"
+	depends on KUNIT
+	select REGMAP
+	help
+	  This option exists purely to allow the regmap KUnit tests to
+	  be enabled without having to enable some driver that uses
+	  regmap due to unfortunate issues with how KUnit tests are
+	  normally enabled.
 
 config REGMAP_AC97
 	tristate
@@ -36,16 +54,28 @@ config REGMAP_W1
 	tristate
 	depends on W1
 
+config REGMAP_MDIO
+	tristate
+	select MDIO_BUS
+
 config REGMAP_MMIO
 	tristate
 
 config REGMAP_IRQ
 	bool
+	select IRQ_DOMAIN
+
+config REGMAP_RAM
+	tristate
 
 config REGMAP_SOUNDWIRE
 	tristate
 	depends on SOUNDWIRE
 
+config REGMAP_SOUNDWIRE_MBQ
+	tristate
+	depends on SOUNDWIRE
+
 config REGMAP_SCCB
 	tristate
 	depends on I2C
@@ -53,3 +83,11 @@ config REGMAP_SCCB
 config REGMAP_I3C
 	tristate
 	depends on I3C
+
+config REGMAP_SPI_AVMM
+	tristate
+	depends on SPI
+
+config REGMAP_FSI
+	tristate
+	depends on FSI
diff --git a/drivers/base/regmap/Makefile b/drivers/base/regmap/Makefile
index ff6c7d8ec1cd..5fdd0845b45e 100644
--- a/drivers/base/regmap/Makefile
+++ b/drivers/base/regmap/Makefile
@@ -3,11 +3,12 @@
 CFLAGS_regmap.o := -I$(src)
 
 obj-$(CONFIG_REGMAP) += regmap.o regcache.o
-obj-$(CONFIG_REGMAP) += regcache-rbtree.o regcache-flat.o
-obj-$(CONFIG_REGCACHE_COMPRESSED) += regcache-lzo.o
+obj-$(CONFIG_REGMAP) += regcache-rbtree.o regcache-flat.o regcache-maple.o
 obj-$(CONFIG_DEBUG_FS) += regmap-debugfs.o
+obj-$(CONFIG_REGMAP_KUNIT) += regmap-kunit.o
 obj-$(CONFIG_REGMAP_AC97) += regmap-ac97.o
 obj-$(CONFIG_REGMAP_I2C) += regmap-i2c.o
+obj-$(CONFIG_REGMAP_RAM) += regmap-ram.o regmap-raw-ram.o
 obj-$(CONFIG_REGMAP_SLIMBUS) += regmap-slimbus.o
 obj-$(CONFIG_REGMAP_SPI) += regmap-spi.o
 obj-$(CONFIG_REGMAP_SPMI) += regmap-spmi.o
@@ -15,5 +16,9 @@ obj-$(CONFIG_REGMAP_MMIO) += regmap-mmio.o
 obj-$(CONFIG_REGMAP_IRQ) += regmap-irq.o
 obj-$(CONFIG_REGMAP_W1) += regmap-w1.o
 obj-$(CONFIG_REGMAP_SOUNDWIRE) += regmap-sdw.o
+obj-$(CONFIG_REGMAP_SOUNDWIRE_MBQ) += regmap-sdw-mbq.o
 obj-$(CONFIG_REGMAP_SCCB) += regmap-sccb.o
 obj-$(CONFIG_REGMAP_I3C) += regmap-i3c.o
+obj-$(CONFIG_REGMAP_SPI_AVMM) += regmap-spi-avmm.o
+obj-$(CONFIG_REGMAP_MDIO) += regmap-mdio.o
+obj-$(CONFIG_REGMAP_FSI) += regmap-fsi.o
diff --git a/drivers/base/regmap/internal.h b/drivers/base/regmap/internal.h
index 3d80c4b43f72..1477329410ec 100644
--- a/drivers/base/regmap/internal.h
+++ b/drivers/base/regmap/internal.h
@@ -32,6 +32,7 @@ struct regmap_format {
 	size_t reg_bytes;
 	size_t pad_bytes;
 	size_t val_bytes;
+	s8 reg_shift;
 	void (*format_write)(struct regmap *map,
 			     unsigned int reg, unsigned int val);
 	void (*format_reg)(void *buf, unsigned int reg, unsigned int shift);
@@ -53,11 +54,17 @@ struct regmap {
 			spinlock_t spinlock;
 			unsigned long spinlock_flags;
 		};
+		struct {
+			raw_spinlock_t raw_spinlock;
+			unsigned long raw_spinlock_flags;
+		};
 	};
+	struct lock_class_key *lock_key;
 	regmap_lock lock;
 	regmap_unlock unlock;
 	void *lock_arg; /* This is passed to lock/unlock functions */
 	gfp_t alloc_flags;
+	unsigned int reg_base;
 
 	struct device *dev; /* Device we do I/O on */
 	void *work_buf;     /* Scratch buffer used to format I/O */
@@ -66,12 +73,12 @@ struct regmap {
 	void *bus_context;
 	const char *name;
 
-	bool async;
 	spinlock_t async_lock;
 	wait_queue_head_t async_waitq;
 	struct list_head async_list;
 	struct list_head async_free;
 	int async_ret;
+	bool async;
 
 #ifdef CONFIG_DEBUG_FS
 	bool debugfs_disable;
@@ -87,6 +94,7 @@ struct regmap {
 #endif
 
 	unsigned int max_register;
+	bool max_register_is_set;
 	bool (*writeable_reg)(struct device *dev, unsigned int reg);
 	bool (*readable_reg)(struct device *dev, unsigned int reg);
 	bool (*volatile_reg)(struct device *dev, unsigned int reg);
@@ -104,8 +112,10 @@ struct regmap {
 	int (*reg_write)(void *context, unsigned int reg, unsigned int val);
 	int (*reg_update_bits)(void *context, unsigned int reg,
 			       unsigned int mask, unsigned int val);
-
-	bool defer_caching;
+	/* Bulk read/write */
+	int (*read)(void *context, const void *reg_buf, size_t reg_size,
+		    void *val_buf, size_t val_size);
+	int (*write)(void *context, const void *data, size_t count);
 
 	unsigned long read_flag_mask;
 	unsigned long write_flag_mask;
@@ -115,6 +125,11 @@ struct regmap {
 	int reg_stride;
 	int reg_stride_order;
 
+	bool defer_caching;
+
+	/* If set, will always write field to HW. */
+	bool force_write_field;
+
 	/* regcache specific members */
 	const struct regcache_ops *cache_ops;
 	enum regcache_type cache_type;
@@ -146,6 +161,9 @@ struct regmap {
 	struct reg_sequence *patch;
 	int patch_regs;
 
+	/* if set, the regmap core can sleep */
+	bool can_sleep;
+
 	/* if set, converts bulk read to single read */
 	bool use_single_read;
 	/* if set, converts bulk write to single write */
@@ -168,6 +186,7 @@ struct regcache_ops {
 	enum regcache_type type;
 	int (*init)(struct regmap *map);
 	int (*exit)(struct regmap *map);
+	int (*populate)(struct regmap *map);
 #ifdef CONFIG_DEBUG_FS
 	void (*debugfs_init)(struct regmap *map);
 #endif
@@ -217,7 +236,7 @@ struct regmap_field {
 
 #ifdef CONFIG_DEBUG_FS
 extern void regmap_debugfs_initcall(void);
-extern void regmap_debugfs_init(struct regmap *map, const char *name);
+extern void regmap_debugfs_init(struct regmap *map);
 extern void regmap_debugfs_exit(struct regmap *map);
 
 static inline void regmap_debugfs_disable(struct regmap *map)
@@ -227,7 +246,7 @@ static inline void regmap_debugfs_disable(struct regmap *map)
 
 #else
 static inline void regmap_debugfs_initcall(void) { }
-static inline void regmap_debugfs_init(struct regmap *map, const char *name) { }
+static inline void regmap_debugfs_init(struct regmap *map) { }
 static inline void regmap_debugfs_exit(struct regmap *map) { }
 static inline void regmap_debugfs_disable(struct regmap *map) { }
 #endif
@@ -244,6 +263,8 @@ int regcache_sync_block(struct regmap *map, void *block,
 			unsigned long *cache_present,
 			unsigned int block_base, unsigned int start,
 			unsigned int end);
+bool regcache_reg_needs_sync(struct regmap *map, unsigned int reg,
+			     unsigned int val);
 
 static inline const void *regcache_get_val_addr(struct regmap *map,
 						const void *base,
@@ -254,12 +275,13 @@ static inline const void *regcache_get_val_addr(struct regmap *map,
 
 unsigned int regcache_get_val(struct regmap *map, const void *base,
 			      unsigned int idx);
-bool regcache_set_val(struct regmap *map, void *base, unsigned int idx,
+void regcache_set_val(struct regmap *map, void *base, unsigned int idx,
 		      unsigned int val);
 int regcache_lookup_reg(struct regmap *map, unsigned int reg);
+int regcache_sync_val(struct regmap *map, unsigned int reg, unsigned int val);
 
 int _regmap_raw_write(struct regmap *map, unsigned int reg,
-		      const void *val, size_t val_len);
+		      const void *val, size_t val_len, bool noinc);
 
 void regmap_async_complete_cb(struct regmap_async *async, int ret);
 
@@ -267,8 +289,9 @@ enum regmap_endian regmap_get_val_endian(struct device *dev,
 					 const struct regmap_bus *bus,
 					 const struct regmap_config *config);
 
+extern struct regcache_ops regcache_flat_sparse_ops;
 extern struct regcache_ops regcache_rbtree_ops;
-extern struct regcache_ops regcache_lzo_ops;
+extern struct regcache_ops regcache_maple_ops;
 extern struct regcache_ops regcache_flat_ops;
 
 static inline const char *regmap_name(const struct regmap *map)
@@ -294,4 +317,34 @@ static inline unsigned int regcache_get_index_by_order(const struct regmap *map,
 	return reg >> map->reg_stride_order;
 }
 
+struct regmap_ram_data {
+	unsigned int *vals;  /* Allocatd by caller */
+	bool *read;
+	bool *written;
+	enum regmap_endian reg_endian;
+	bool (*noinc_reg)(struct regmap_ram_data *data, unsigned int reg);
+};
+
+/*
+ * Create a test register map with data stored in RAM, not intended
+ * for practical use.
+ */
+struct regmap *__regmap_init_ram(struct device *dev,
+				 const struct regmap_config *config,
+				 struct regmap_ram_data *data,
+				 struct lock_class_key *lock_key,
+				 const char *lock_name);
+
+#define regmap_init_ram(dev, config, data)					\
+	__regmap_lockdep_wrapper(__regmap_init_ram, #dev, dev, config, data)
+
+struct regmap *__regmap_init_raw_ram(struct device *dev,
+				     const struct regmap_config *config,
+				     struct regmap_ram_data *data,
+				     struct lock_class_key *lock_key,
+				     const char *lock_name);
+
+#define regmap_init_raw_ram(dev, config, data)				\
+	__regmap_lockdep_wrapper(__regmap_init_raw_ram, #dev, dev, config, data)
+
 #endif
diff --git a/drivers/base/regmap/regcache-flat.c b/drivers/base/regmap/regcache-flat.c
index b7e4b2464102..53cc59c84e2f 100644
--- a/drivers/base/regmap/regcache-flat.c
+++ b/drivers/base/regmap/regcache-flat.c
@@ -6,7 +6,11 @@
 //
 // Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
 
+#include <linux/bitmap.h>
+#include <linux/bitops.h>
 #include <linux/device.h>
+#include <linux/limits.h>
+#include <linux/overflow.h>
 #include <linux/seq_file.h>
 #include <linux/slab.h>
 
@@ -18,46 +22,92 @@ static inline unsigned int regcache_flat_get_index(const struct regmap *map,
 	return regcache_get_index_by_order(map, reg);
 }
 
+struct regcache_flat_data {
+	unsigned long *valid;
+	unsigned int data[];
+};
+
 static int regcache_flat_init(struct regmap *map)
 {
-	int i;
-	unsigned int *cache;
+	unsigned int cache_size;
+	struct regcache_flat_data *cache;
 
-	if (!map || map->reg_stride_order < 0 || !map->max_register)
+	if (!map || map->reg_stride_order < 0 || !map->max_register_is_set)
 		return -EINVAL;
 
-	map->cache = kcalloc(regcache_flat_get_index(map, map->max_register)
-			     + 1, sizeof(unsigned int), GFP_KERNEL);
-	if (!map->cache)
+	cache_size = regcache_flat_get_index(map, map->max_register) + 1;
+	cache = kzalloc(struct_size(cache, data, cache_size), map->alloc_flags);
+	if (!cache)
 		return -ENOMEM;
 
-	cache = map->cache;
+	cache->valid = bitmap_zalloc(cache_size, map->alloc_flags);
+	if (!cache->valid)
+		goto err_free;
+
+	map->cache = cache;
+
+	return 0;
+
+err_free:
+	kfree(cache);
+	return -ENOMEM;
+}
+
+static int regcache_flat_exit(struct regmap *map)
+{
+	struct regcache_flat_data *cache = map->cache;
+
+	if (cache)
+		bitmap_free(cache->valid);
+
+	kfree(cache);
+	map->cache = NULL;
+
+	return 0;
+}
+
+static int regcache_flat_populate(struct regmap *map)
+{
+	struct regcache_flat_data *cache = map->cache;
+	unsigned int i;
 
 	for (i = 0; i < map->num_reg_defaults; i++) {
 		unsigned int reg = map->reg_defaults[i].reg;
 		unsigned int index = regcache_flat_get_index(map, reg);
 
-		cache[index] = map->reg_defaults[i].def;
+		cache->data[index] = map->reg_defaults[i].def;
+		__set_bit(index, cache->valid);
 	}
 
 	return 0;
 }
 
-static int regcache_flat_exit(struct regmap *map)
+static int regcache_flat_read(struct regmap *map,
+			      unsigned int reg, unsigned int *value)
 {
-	kfree(map->cache);
-	map->cache = NULL;
+	struct regcache_flat_data *cache = map->cache;
+	unsigned int index = regcache_flat_get_index(map, reg);
+
+	/* legacy behavior: ignore validity, but warn the user */
+	if (unlikely(!test_bit(index, cache->valid)))
+		dev_warn_once(map->dev,
+			"using zero-initialized flat cache, this may cause unexpected behavior");
+
+	*value = cache->data[index];
 
 	return 0;
 }
 
-static int regcache_flat_read(struct regmap *map,
-			      unsigned int reg, unsigned int *value)
+static int regcache_flat_sparse_read(struct regmap *map,
+				     unsigned int reg, unsigned int *value)
 {
-	unsigned int *cache = map->cache;
+	struct regcache_flat_data *cache = map->cache;
 	unsigned int index = regcache_flat_get_index(map, reg);
 
-	*value = cache[index];
+	if (unlikely(!test_bit(index, cache->valid)))
+		return -ENOENT;
+
+	*value = cache->data[index];
 
 	return 0;
 }
@@ -65,10 +115,23 @@ static int regcache_flat_read(struct regmap *map,
 static int regcache_flat_write(struct regmap *map, unsigned int reg,
 			       unsigned int value)
 {
-	unsigned int *cache = map->cache;
+	struct regcache_flat_data *cache = map->cache;
 	unsigned int index = regcache_flat_get_index(map, reg);
 
-	cache[index] = value;
+	cache->data[index] = value;
+	__set_bit(index, cache->valid);
+
+	return 0;
+}
+
+static int regcache_flat_drop(struct regmap *map, unsigned int min,
+			      unsigned int max)
+{
+	struct regcache_flat_data *cache = map->cache;
+	unsigned int bitmap_min = regcache_flat_get_index(map, min);
+	unsigned int bitmap_max = regcache_flat_get_index(map, max);
+
+	bitmap_clear(cache->valid, bitmap_min, bitmap_max + 1 - bitmap_min);
 
 	return 0;
 }
@@ -78,6 +141,18 @@ struct regcache_ops regcache_flat_ops = {
 	.name = "flat",
 	.init = regcache_flat_init,
 	.exit = regcache_flat_exit,
+	.populate = regcache_flat_populate,
 	.read = regcache_flat_read,
 	.write = regcache_flat_write,
 };
+
+struct regcache_ops regcache_flat_sparse_ops = {
+	.type = REGCACHE_FLAT_S,
+	.name = "flat-sparse",
+	.init = regcache_flat_init,
+	.exit = regcache_flat_exit,
+	.populate = regcache_flat_populate,
+	.read = regcache_flat_sparse_read,
+	.write = regcache_flat_write,
+	.drop = regcache_flat_drop,
+};
diff --git a/drivers/base/regmap/regcache-lzo.c b/drivers/base/regmap/regcache-lzo.c
deleted file mode 100644
index 7886303eb026..000000000000
--- a/drivers/base/regmap/regcache-lzo.c
+++ /dev/null
@@ -1,368 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-//
-// Register cache access API - LZO caching support
-//
-// Copyright 2011 Wolfson Microelectronics plc
-//
-// Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
-
-#include <linux/device.h>
-#include <linux/lzo.h>
-#include <linux/slab.h>
-
-#include "internal.h"
-
-static int regcache_lzo_exit(struct regmap *map);
-
-struct regcache_lzo_ctx {
-	void *wmem;
-	void *dst;
-	const void *src;
-	size_t src_len;
-	size_t dst_len;
-	size_t decompressed_size;
-	unsigned long *sync_bmp;
-	int sync_bmp_nbits;
-};
-
-#define LZO_BLOCK_NUM 8
-static int regcache_lzo_block_count(struct regmap *map)
-{
-	return LZO_BLOCK_NUM;
-}
-
-static int regcache_lzo_prepare(struct regcache_lzo_ctx *lzo_ctx)
-{
-	lzo_ctx->wmem = kmalloc(LZO1X_MEM_COMPRESS, GFP_KERNEL);
-	if (!lzo_ctx->wmem)
-		return -ENOMEM;
-	return 0;
-}
-
-static int regcache_lzo_compress(struct regcache_lzo_ctx *lzo_ctx)
-{
-	size_t compress_size;
-	int ret;
-
-	ret = lzo1x_1_compress(lzo_ctx->src, lzo_ctx->src_len,
-			       lzo_ctx->dst, &compress_size, lzo_ctx->wmem);
-	if (ret != LZO_E_OK || compress_size > lzo_ctx->dst_len)
-		return -EINVAL;
-	lzo_ctx->dst_len = compress_size;
-	return 0;
-}
-
-static int regcache_lzo_decompress(struct regcache_lzo_ctx *lzo_ctx)
-{
-	size_t dst_len;
-	int ret;
-
-	dst_len = lzo_ctx->dst_len;
-	ret = lzo1x_decompress_safe(lzo_ctx->src, lzo_ctx->src_len,
-				    lzo_ctx->dst, &dst_len);
-	if (ret != LZO_E_OK || dst_len != lzo_ctx->dst_len)
-		return -EINVAL;
-	return 0;
-}
-
-static int regcache_lzo_compress_cache_block(struct regmap *map,
-		struct regcache_lzo_ctx *lzo_ctx)
-{
-	int ret;
-
-	lzo_ctx->dst_len = lzo1x_worst_compress(PAGE_SIZE);
-	lzo_ctx->dst = kmalloc(lzo_ctx->dst_len, GFP_KERNEL);
-	if (!lzo_ctx->dst) {
-		lzo_ctx->dst_len = 0;
-		return -ENOMEM;
-	}
-
-	ret = regcache_lzo_compress(lzo_ctx);
-	if (ret < 0)
-		return ret;
-	return 0;
-}
-
-static int regcache_lzo_decompress_cache_block(struct regmap *map,
-		struct regcache_lzo_ctx *lzo_ctx)
-{
-	int ret;
-
-	lzo_ctx->dst_len = lzo_ctx->decompressed_size;
-	lzo_ctx->dst = kmalloc(lzo_ctx->dst_len, GFP_KERNEL);
-	if (!lzo_ctx->dst) {
-		lzo_ctx->dst_len = 0;
-		return -ENOMEM;
-	}
-
-	ret = regcache_lzo_decompress(lzo_ctx);
-	if (ret < 0)
-		return ret;
-	return 0;
-}
-
-static inline int regcache_lzo_get_blkindex(struct regmap *map,
-					    unsigned int reg)
-{
-	return ((reg / map->reg_stride) * map->cache_word_size) /
-		DIV_ROUND_UP(map->cache_size_raw,
-			     regcache_lzo_block_count(map));
-}
-
-static inline int regcache_lzo_get_blkpos(struct regmap *map,
-					  unsigned int reg)
-{
-	return (reg / map->reg_stride) %
-		    (DIV_ROUND_UP(map->cache_size_raw,
-				  regcache_lzo_block_count(map)) /
-		     map->cache_word_size);
-}
-
-static inline int regcache_lzo_get_blksize(struct regmap *map)
-{
-	return DIV_ROUND_UP(map->cache_size_raw,
-			    regcache_lzo_block_count(map));
-}
-
-static int regcache_lzo_init(struct regmap *map)
-{
-	struct regcache_lzo_ctx **lzo_blocks;
-	size_t bmp_size;
-	int ret, i, blksize, blkcount;
-	const char *p, *end;
-	unsigned long *sync_bmp;
-
-	ret = 0;
-
-	blkcount = regcache_lzo_block_count(map);
-	map->cache = kcalloc(blkcount, sizeof(*lzo_blocks),
-			     GFP_KERNEL);
-	if (!map->cache)
-		return -ENOMEM;
-	lzo_blocks = map->cache;
-
-	/*
-	 * allocate a bitmap to be used when syncing the cache with
-	 * the hardware.  Each time a register is modified, the corresponding
-	 * bit is set in the bitmap, so we know that we have to sync
-	 * that register.
-	 */
-	bmp_size = map->num_reg_defaults_raw;
-	sync_bmp = bitmap_zalloc(bmp_size, GFP_KERNEL);
-	if (!sync_bmp) {
-		ret = -ENOMEM;
-		goto err;
-	}
-
-	/* allocate the lzo blocks and initialize them */
-	for (i = 0; i < blkcount; i++) {
-		lzo_blocks[i] = kzalloc(sizeof **lzo_blocks,
-					GFP_KERNEL);
-		if (!lzo_blocks[i]) {
-			bitmap_free(sync_bmp);
-			ret = -ENOMEM;
-			goto err;
-		}
-		lzo_blocks[i]->sync_bmp = sync_bmp;
-		lzo_blocks[i]->sync_bmp_nbits = bmp_size;
-		/* alloc the working space for the compressed block */
-		ret = regcache_lzo_prepare(lzo_blocks[i]);
-		if (ret < 0)
-			goto err;
-	}
-
-	blksize = regcache_lzo_get_blksize(map);
-	p = map->reg_defaults_raw;
-	end = map->reg_defaults_raw + map->cache_size_raw;
-	/* compress the register map and fill the lzo blocks */
-	for (i = 0; i < blkcount; i++, p += blksize) {
-		lzo_blocks[i]->src = p;
-		if (p + blksize > end)
-			lzo_blocks[i]->src_len = end - p;
-		else
-			lzo_blocks[i]->src_len = blksize;
-		ret = regcache_lzo_compress_cache_block(map,
-						       lzo_blocks[i]);
-		if (ret < 0)
-			goto err;
-		lzo_blocks[i]->decompressed_size =
-			lzo_blocks[i]->src_len;
-	}
-
-	return 0;
-err:
-	regcache_lzo_exit(map);
-	return ret;
-}
-
-static int regcache_lzo_exit(struct regmap *map)
-{
-	struct regcache_lzo_ctx **lzo_blocks;
-	int i, blkcount;
-
-	lzo_blocks = map->cache;
-	if (!lzo_blocks)
-		return 0;
-
-	blkcount = regcache_lzo_block_count(map);
-	/*
-	 * the pointer to the bitmap used for syncing the cache
-	 * is shared amongst all lzo_blocks.  Ensure it is freed
-	 * only once.
-	 */
-	if (lzo_blocks[0])
-		bitmap_free(lzo_blocks[0]->sync_bmp);
-	for (i = 0; i < blkcount; i++) {
-		if (lzo_blocks[i]) {
-			kfree(lzo_blocks[i]->wmem);
-			kfree(lzo_blocks[i]->dst);
-		}
-		/* each lzo_block is a pointer returned by kmalloc or NULL */
-		kfree(lzo_blocks[i]);
-	}
-	kfree(lzo_blocks);
-	map->cache = NULL;
-	return 0;
-}
-
-static int regcache_lzo_read(struct regmap *map,
-			     unsigned int reg, unsigned int *value)
-{
-	struct regcache_lzo_ctx *lzo_block, **lzo_blocks;
-	int ret, blkindex, blkpos;
-	size_t tmp_dst_len;
-	void *tmp_dst;
-
-	/* index of the compressed lzo block */
-	blkindex = regcache_lzo_get_blkindex(map, reg);
-	/* register index within the decompressed block */
-	blkpos = regcache_lzo_get_blkpos(map, reg);
-	lzo_blocks = map->cache;
-	lzo_block = lzo_blocks[blkindex];
-
-	/* save the pointer and length of the compressed block */
-	tmp_dst = lzo_block->dst;
-	tmp_dst_len = lzo_block->dst_len;
-
-	/* prepare the source to be the compressed block */
-	lzo_block->src = lzo_block->dst;
-	lzo_block->src_len = lzo_block->dst_len;
-
-	/* decompress the block */
-	ret = regcache_lzo_decompress_cache_block(map, lzo_block);
-	if (ret >= 0)
-		/* fetch the value from the cache */
-		*value = regcache_get_val(map, lzo_block->dst, blkpos);
-
-	kfree(lzo_block->dst);
-	/* restore the pointer and length of the compressed block */
-	lzo_block->dst = tmp_dst;
-	lzo_block->dst_len = tmp_dst_len;
-
-	return ret;
-}
-
-static int regcache_lzo_write(struct regmap *map,
-			      unsigned int reg, unsigned int value)
-{
-	struct regcache_lzo_ctx *lzo_block, **lzo_blocks;
-	int ret, blkindex, blkpos;
-	size_t tmp_dst_len;
-	void *tmp_dst;
-
-	/* index of the compressed lzo block */
-	blkindex = regcache_lzo_get_blkindex(map, reg);
-	/* register index within the decompressed block */
-	blkpos = regcache_lzo_get_blkpos(map, reg);
-	lzo_blocks = map->cache;
-	lzo_block = lzo_blocks[blkindex];
-
-	/* save the pointer and length of the compressed block */
-	tmp_dst = lzo_block->dst;
-	tmp_dst_len = lzo_block->dst_len;
-
-	/* prepare the source to be the compressed block */
-	lzo_block->src = lzo_block->dst;
-	lzo_block->src_len = lzo_block->dst_len;
-
-	/* decompress the block */
-	ret = regcache_lzo_decompress_cache_block(map, lzo_block);
-	if (ret < 0) {
-		kfree(lzo_block->dst);
-		goto out;
-	}
-
-	/* write the new value to the cache */
-	if (regcache_set_val(map, lzo_block->dst, blkpos, value)) {
-		kfree(lzo_block->dst);
-		goto out;
-	}
-
-	/* prepare the source to be the decompressed block */
-	lzo_block->src = lzo_block->dst;
-	lzo_block->src_len = lzo_block->dst_len;
-
-	/* compress the block */
-	ret = regcache_lzo_compress_cache_block(map, lzo_block);
-	if (ret < 0) {
-		kfree(lzo_block->dst);
-		kfree(lzo_block->src);
-		goto out;
-	}
-
-	/* set the bit so we know we have to sync this register */
-	set_bit(reg / map->reg_stride, lzo_block->sync_bmp);
-	kfree(tmp_dst);
-	kfree(lzo_block->src);
-	return 0;
-out:
-	lzo_block->dst = tmp_dst;
-	lzo_block->dst_len = tmp_dst_len;
-	return ret;
-}
-
-static int regcache_lzo_sync(struct regmap *map, unsigned int min,
-			     unsigned int max)
-{
-	struct regcache_lzo_ctx **lzo_blocks;
-	unsigned int val;
-	int i;
-	int ret;
-
-	lzo_blocks = map->cache;
-	i = min;
-	for_each_set_bit_from(i, lzo_blocks[0]->sync_bmp,
-			      lzo_blocks[0]->sync_bmp_nbits) {
-		if (i > max)
-			continue;
-
-		ret = regcache_read(map, i, &val);
-		if (ret)
-			return ret;
-
-		/* Is this the hardware default?  If so skip. */
-		ret = regcache_lookup_reg(map, i);
-		if (ret > 0 && val == map->reg_defaults[ret].def)
-			continue;
-
-		map->cache_bypass = true;
-		ret = _regmap_write(map, i, val);
-		map->cache_bypass = false;
-		if (ret)
-			return ret;
-		dev_dbg(map->dev, "Synced register %#x, value %#x\n",
-			i, val);
-	}
-
-	return 0;
-}
-
-struct regcache_ops regcache_lzo_ops = {
-	.type = REGCACHE_COMPRESSED,
-	.name = "lzo",
-	.init = regcache_lzo_init,
-	.exit = regcache_lzo_exit,
-	.read = regcache_lzo_read,
-	.write = regcache_lzo_write,
-	.sync = regcache_lzo_sync
-};
diff --git a/drivers/base/regmap/regcache-maple.c b/drivers/base/regmap/regcache-maple.c
new file mode 100644
index 000000000000..ca1c72b68f31
--- /dev/null
+++ b/drivers/base/regmap/regcache-maple.c
@@ -0,0 +1,395 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Register cache access API - maple tree based cache
+//
+// Copyright 2023 Arm, Ltd
+//
+// Author: Mark Brown <broonie@kernel.org>
+
+#include <linux/debugfs.h>
+#include <linux/device.h>
+#include <linux/maple_tree.h>
+#include <linux/slab.h>
+
+#include "internal.h"
+
+static int regcache_maple_read(struct regmap *map,
+			       unsigned int reg, unsigned int *value)
+{
+	struct maple_tree *mt = map->cache;
+	MA_STATE(mas, mt, reg, reg);
+	unsigned long *entry;
+
+	rcu_read_lock();
+
+	entry = mas_walk(&mas);
+	if (!entry) {
+		rcu_read_unlock();
+		return -ENOENT;
+	}
+
+	*value = entry[reg - mas.index];
+
+	rcu_read_unlock();
+
+	return 0;
+}
+
+static int regcache_maple_write(struct regmap *map, unsigned int reg,
+				unsigned int val)
+{
+	struct maple_tree *mt = map->cache;
+	MA_STATE(mas, mt, reg, reg);
+	unsigned long *entry, *upper, *lower;
+	unsigned long index, last;
+	size_t lower_sz, upper_sz;
+	int ret;
+
+	rcu_read_lock();
+
+	entry = mas_walk(&mas);
+	if (entry) {
+		entry[reg - mas.index] = val;
+		rcu_read_unlock();
+		return 0;
+	}
+
+	/* Any adjacent entries to extend/merge? */
+	mas_set_range(&mas, reg - 1, reg + 1);
+	index = reg;
+	last = reg;
+
+	lower = mas_find(&mas, reg - 1);
+	if (lower) {
+		index = mas.index;
+		lower_sz = (mas.last - mas.index + 1) * sizeof(unsigned long);
+	}
+
+	upper = mas_find(&mas, reg + 1);
+	if (upper) {
+		last = mas.last;
+		upper_sz = (mas.last - mas.index + 1) * sizeof(unsigned long);
+	}
+
+	rcu_read_unlock();
+
+	entry = kmalloc_array(last - index + 1, sizeof(*entry), map->alloc_flags);
+	if (!entry)
+		return -ENOMEM;
+
+	if (lower)
+		memcpy(entry, lower, lower_sz);
+	entry[reg - index] = val;
+	if (upper)
+		memcpy(&entry[reg - index + 1], upper, upper_sz);
+
+	/*
+	 * This is safe because the regmap lock means the Maple lock
+	 * is redundant, but we need to take it due to lockdep asserts
+	 * in the maple tree code.
+	 */
+	mas_lock(&mas);
+
+	mas_set_range(&mas, index, last);
+	ret = mas_store_gfp(&mas, entry, map->alloc_flags);
+
+	mas_unlock(&mas);
+
+	if (ret == 0) {
+		kfree(lower);
+		kfree(upper);
+	}
+	
+	return ret;
+}
+
+static int regcache_maple_drop(struct regmap *map, unsigned int min,
+			       unsigned int max)
+{
+	struct maple_tree *mt = map->cache;
+	MA_STATE(mas, mt, min, max);
+	unsigned long *entry, *lower, *upper;
+	/* initialized to work around false-positive -Wuninitialized warning */
+	unsigned long lower_index = 0, lower_last = 0;
+	unsigned long upper_index, upper_last;
+	int ret = 0;
+
+	lower = NULL;
+	upper = NULL;
+
+	mas_lock(&mas);
+
+	mas_for_each(&mas, entry, max) {
+		/*
+		 * This is safe because the regmap lock means the
+		 * Maple lock is redundant, but we need to take it due
+		 * to lockdep asserts in the maple tree code.
+		 */
+		mas_unlock(&mas);
+
+		/* Do we need to save any of this entry? */
+		if (mas.index < min) {
+			lower_index = mas.index;
+			lower_last = min -1;
+
+			lower = kmemdup_array(entry,
+					      min - mas.index, sizeof(*lower),
+					      map->alloc_flags);
+			if (!lower) {
+				ret = -ENOMEM;
+				goto out_unlocked;
+			}
+		}
+
+		if (mas.last > max) {
+			upper_index = max + 1;
+			upper_last = mas.last;
+
+			upper = kmemdup_array(&entry[max - mas.index + 1],
+					      mas.last - max, sizeof(*upper),
+					      map->alloc_flags);
+			if (!upper) {
+				ret = -ENOMEM;
+				goto out_unlocked;
+			}
+		}
+
+		kfree(entry);
+		mas_lock(&mas);
+		mas_erase(&mas);
+
+		/* Insert new nodes with the saved data */
+		if (lower) {
+			mas_set_range(&mas, lower_index, lower_last);
+			ret = mas_store_gfp(&mas, lower, map->alloc_flags);
+			if (ret != 0)
+				goto out;
+			lower = NULL;
+		}
+
+		if (upper) {
+			mas_set_range(&mas, upper_index, upper_last);
+			ret = mas_store_gfp(&mas, upper, map->alloc_flags);
+			if (ret != 0)
+				goto out;
+			upper = NULL;
+		}
+	}
+
+out:
+	mas_unlock(&mas);
+out_unlocked:
+	kfree(lower);
+	kfree(upper);
+
+	return ret;
+}
+
+static int regcache_maple_sync_block(struct regmap *map, unsigned long *entry,
+				     struct ma_state *mas,
+				     unsigned int min, unsigned int max)
+{
+	void *buf;
+	unsigned long r;
+	size_t val_bytes = map->format.val_bytes;
+	int ret = 0;
+
+	mas_pause(mas);
+	rcu_read_unlock();
+
+	/*
+	 * Use a raw write if writing more than one register to a
+	 * device that supports raw writes to reduce transaction
+	 * overheads.
+	 */
+	if (max - min > 1 && regmap_can_raw_write(map)) {
+		buf = kmalloc_array(max - min, val_bytes, map->alloc_flags);
+		if (!buf) {
+			ret = -ENOMEM;
+			goto out;
+		}
+
+		/* Render the data for a raw write */
+		for (r = min; r < max; r++) {
+			regcache_set_val(map, buf, r - min,
+					 entry[r - mas->index]);
+		}
+
+		ret = _regmap_raw_write(map, min, buf, (max - min) * val_bytes,
+					false);
+
+		kfree(buf);
+	} else {
+		for (r = min; r < max; r++) {
+			ret = _regmap_write(map, r,
+					    entry[r - mas->index]);
+			if (ret != 0)
+				goto out;
+		}
+	}
+
+out:
+	rcu_read_lock();
+
+	return ret;
+}
+
+static int regcache_maple_sync(struct regmap *map, unsigned int min,
+			       unsigned int max)
+{
+	struct maple_tree *mt = map->cache;
+	unsigned long *entry;
+	MA_STATE(mas, mt, min, max);
+	unsigned long lmin = min;
+	unsigned long lmax = max;
+	unsigned int r, v, sync_start;
+	int ret = 0;
+	bool sync_needed = false;
+
+	map->cache_bypass = true;
+
+	rcu_read_lock();
+
+	mas_for_each(&mas, entry, max) {
+		for (r = max(mas.index, lmin); r <= min(mas.last, lmax); r++) {
+			v = entry[r - mas.index];
+
+			if (regcache_reg_needs_sync(map, r, v)) {
+				if (!sync_needed) {
+					sync_start = r;
+					sync_needed = true;
+				}
+				continue;
+			}
+
+			if (!sync_needed)
+				continue;
+
+			ret = regcache_maple_sync_block(map, entry, &mas,
+							sync_start, r);
+			if (ret != 0)
+				goto out;
+			sync_needed = false;
+		}
+
+		if (sync_needed) {
+			ret = regcache_maple_sync_block(map, entry, &mas,
+							sync_start, r);
+			if (ret != 0)
+				goto out;
+			sync_needed = false;
+		}
+	}
+
+out:
+	rcu_read_unlock();
+
+	map->cache_bypass = false;
+
+	return ret;
+}
+
+static int regcache_maple_init(struct regmap *map)
+{
+	struct maple_tree *mt;
+
+	mt = kmalloc(sizeof(*mt), map->alloc_flags);
+	if (!mt)
+		return -ENOMEM;
+	map->cache = mt;
+
+	mt_init(mt);
+
+	if (!mt_external_lock(mt) && map->lock_key)
+		lockdep_set_class_and_subclass(&mt->ma_lock, map->lock_key, 1);
+
+	return 0;
+}
+
+static int regcache_maple_exit(struct regmap *map)
+{
+	struct maple_tree *mt = map->cache;
+	MA_STATE(mas, mt, 0, UINT_MAX);
+	unsigned int *entry;
+
+	/* if we've already been called then just return */
+	if (!mt)
+		return 0;
+
+	mas_lock(&mas);
+	mas_for_each(&mas, entry, UINT_MAX)
+		kfree(entry);
+	__mt_destroy(mt);
+	mas_unlock(&mas);
+
+	kfree(mt);
+	map->cache = NULL;
+
+	return 0;
+}
+
+static int regcache_maple_insert_block(struct regmap *map, int first,
+					int last)
+{
+	struct maple_tree *mt = map->cache;
+	MA_STATE(mas, mt, first, last);
+	unsigned long *entry;
+	int i, ret;
+
+	entry = kmalloc_array(last - first + 1, sizeof(*entry), map->alloc_flags);
+	if (!entry)
+		return -ENOMEM;
+
+	for (i = 0; i < last - first + 1; i++)
+		entry[i] = map->reg_defaults[first + i].def;
+
+	mas_lock(&mas);
+
+	mas_set_range(&mas, map->reg_defaults[first].reg,
+		      map->reg_defaults[last].reg);
+	ret = mas_store_gfp(&mas, entry, map->alloc_flags);
+
+	mas_unlock(&mas);
+
+	if (ret)
+		kfree(entry);
+
+	return ret;
+}
+
+static int regcache_maple_populate(struct regmap *map)
+{
+	int i;
+	int ret;
+	int range_start;
+
+	range_start = 0;
+
+	/* Scan for ranges of contiguous registers */
+	for (i = 1; i < map->num_reg_defaults; i++) {
+		if (map->reg_defaults[i].reg !=
+		    map->reg_defaults[i - 1].reg + 1) {
+			ret = regcache_maple_insert_block(map, range_start,
+							  i - 1);
+			if (ret != 0)
+				return ret;
+
+			range_start = i;
+		}
+	}
+
+	/* Add the last block */
+	return regcache_maple_insert_block(map, range_start, map->num_reg_defaults - 1);
+}
+
+struct regcache_ops regcache_maple_ops = {
+	.type = REGCACHE_MAPLE,
+	.name = "maple",
+	.init = regcache_maple_init,
+	.exit = regcache_maple_exit,
+	.populate = regcache_maple_populate,
+	.read = regcache_maple_read,
+	.write = regcache_maple_write,
+	.drop = regcache_maple_drop,
+	.sync = regcache_maple_sync,
+};
diff --git a/drivers/base/regmap/regcache-rbtree.c b/drivers/base/regmap/regcache-rbtree.c
index cfa29dc89bbf..3344b82c3799 100644
--- a/drivers/base/regmap/regcache-rbtree.c
+++ b/drivers/base/regmap/regcache-rbtree.c
@@ -22,7 +22,7 @@ struct regcache_rbtree_node {
 	/* block of adjacent registers */
 	void *block;
 	/* Which registers are present */
-	long *cache_present;
+	unsigned long *cache_present;
 	/* base register handled by this block */
 	unsigned int base_reg;
 	/* number of registers available in the block */
@@ -184,10 +184,8 @@ static void rbtree_debugfs_init(struct regmap *map)
 static int regcache_rbtree_init(struct regmap *map)
 {
 	struct regcache_rbtree_ctx *rbtree_ctx;
-	int i;
-	int ret;
 
-	map->cache = kmalloc(sizeof *rbtree_ctx, GFP_KERNEL);
+	map->cache = kmalloc(sizeof *rbtree_ctx, map->alloc_flags);
 	if (!map->cache)
 		return -ENOMEM;
 
@@ -195,19 +193,7 @@ static int regcache_rbtree_init(struct regmap *map)
 	rbtree_ctx->root = RB_ROOT;
 	rbtree_ctx->cached_rbnode = NULL;
 
-	for (i = 0; i < map->num_reg_defaults; i++) {
-		ret = regcache_rbtree_write(map,
-					    map->reg_defaults[i].reg,
-					    map->reg_defaults[i].def);
-		if (ret)
-			goto err;
-	}
-
 	return 0;
-
-err:
-	regcache_rbtree_exit(map);
-	return ret;
 }
 
 static int regcache_rbtree_exit(struct regmap *map)
@@ -239,6 +225,22 @@ static int regcache_rbtree_exit(struct regmap *map)
 	return 0;
 }
 
+static int regcache_rbtree_populate(struct regmap *map)
+{
+	unsigned int i;
+	int ret;
+
+	for (i = 0; i < map->num_reg_defaults; i++) {
+		ret = regcache_rbtree_write(map,
+					    map->reg_defaults[i].reg,
+					    map->reg_defaults[i].def);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
 static int regcache_rbtree_read(struct regmap *map,
 				unsigned int reg, unsigned int *value)
 {
@@ -275,20 +277,18 @@ static int regcache_rbtree_insert_to_block(struct regmap *map,
 	pos = (reg - base_reg) / map->reg_stride;
 	offset = (rbnode->base_reg - base_reg) / map->reg_stride;
 
-	blk = krealloc(rbnode->block,
-		       blklen * map->cache_word_size,
-		       GFP_KERNEL);
+	blk = krealloc_array(rbnode->block, blklen, map->cache_word_size, map->alloc_flags);
 	if (!blk)
 		return -ENOMEM;
 
+	rbnode->block = blk;
+
 	if (BITS_TO_LONGS(blklen) > BITS_TO_LONGS(rbnode->blklen)) {
-		present = krealloc(rbnode->cache_present,
-				   BITS_TO_LONGS(blklen) * sizeof(*present),
-				   GFP_KERNEL);
-		if (!present) {
-			kfree(blk);
+		present = krealloc_array(rbnode->cache_present,
+					 BITS_TO_LONGS(blklen), sizeof(*present),
+					 map->alloc_flags);
+		if (!present)
 			return -ENOMEM;
-		}
 
 		memset(present + BITS_TO_LONGS(rbnode->blklen), 0,
 		       (BITS_TO_LONGS(blklen) - BITS_TO_LONGS(rbnode->blklen))
@@ -305,7 +305,6 @@ static int regcache_rbtree_insert_to_block(struct regmap *map,
 	}
 
 	/* update the rbnode block, its size and the base register */
-	rbnode->block = blk;
 	rbnode->blklen = blklen;
 	rbnode->base_reg = base_reg;
 	rbnode->cache_present = present;
@@ -321,7 +320,7 @@ regcache_rbtree_node_alloc(struct regmap *map, unsigned int reg)
 	const struct regmap_range *range;
 	int i;
 
-	rbnode = kzalloc(sizeof(*rbnode), GFP_KERNEL);
+	rbnode = kzalloc(sizeof(*rbnode), map->alloc_flags);
 	if (!rbnode)
 		return NULL;
 
@@ -347,13 +346,13 @@ regcache_rbtree_node_alloc(struct regmap *map, unsigned int reg)
 	}
 
 	rbnode->block = kmalloc_array(rbnode->blklen, map->cache_word_size,
-				      GFP_KERNEL);
+				      map->alloc_flags);
 	if (!rbnode->block)
 		goto err_free;
 
 	rbnode->cache_present = kcalloc(BITS_TO_LONGS(rbnode->blklen),
 					sizeof(*rbnode->cache_present),
-					GFP_KERNEL);
+					map->alloc_flags);
 	if (!rbnode->cache_present)
 		goto err_free_block;
 
@@ -454,7 +453,8 @@ static int regcache_rbtree_write(struct regmap *map, unsigned int reg,
 		if (!rbnode)
 			return -ENOMEM;
 		regcache_rbtree_set_register(map, rbnode,
-					     reg - rbnode->base_reg, value);
+					     (reg - rbnode->base_reg) / map->reg_stride,
+					     value);
 		regcache_rbtree_insert(map, &rbtree_ctx->root, rbnode);
 		rbtree_ctx->cached_rbnode = rbnode;
 	}
@@ -472,6 +472,8 @@ static int regcache_rbtree_sync(struct regmap *map, unsigned int min,
 	unsigned int start, end;
 	int ret;
 
+	map->async = true;
+
 	rbtree_ctx = map->cache;
 	for (node = rb_first(&rbtree_ctx->root); node; node = rb_next(node)) {
 		rbnode = rb_entry(node, struct regcache_rbtree_node, node);
@@ -500,6 +502,8 @@ static int regcache_rbtree_sync(struct regmap *map, unsigned int min,
 			return ret;
 	}
 
+	map->async = false;
+
 	return regmap_async_complete(map);
 }
 
@@ -544,6 +548,7 @@ struct regcache_ops regcache_rbtree_ops = {
 	.name = "rbtree",
 	.init = regcache_rbtree_init,
 	.exit = regcache_rbtree_exit,
+	.populate = regcache_rbtree_populate,
 #ifdef CONFIG_DEBUG_FS
 	.debugfs_init = rbtree_debugfs_init,
 #endif
diff --git a/drivers/base/regmap/regcache.c b/drivers/base/regmap/regcache.c
index a93cafd7be4f..319c342bf5a0 100644
--- a/drivers/base/regmap/regcache.c
+++ b/drivers/base/regmap/regcache.c
@@ -16,13 +16,32 @@
 #include "internal.h"
 
 static const struct regcache_ops *cache_types[] = {
+	&regcache_flat_sparse_ops,
 	&regcache_rbtree_ops,
-#if IS_ENABLED(CONFIG_REGCACHE_COMPRESSED)
-	&regcache_lzo_ops,
-#endif
+	&regcache_maple_ops,
 	&regcache_flat_ops,
 };
 
+static int regcache_defaults_cmp(const void *a, const void *b)
+{
+	const struct reg_default *x = a;
+	const struct reg_default *y = b;
+
+	if (x->reg > y->reg)
+		return 1;
+	else if (x->reg < y->reg)
+		return -1;
+	else
+		return 0;
+}
+
+void regcache_sort_defaults(struct reg_default *defaults, unsigned int ndefaults)
+{
+	sort(defaults, ndefaults, sizeof(*defaults),
+	     regcache_defaults_cmp, NULL);
+}
+EXPORT_SYMBOL_GPL(regcache_sort_defaults);
+
 static int regcache_hw_init(struct regmap *map)
 {
 	int i, j;
@@ -68,7 +87,7 @@ static int regcache_hw_init(struct regmap *map)
 		map->cache_bypass = cache_bypass;
 		if (ret == 0) {
 			map->reg_defaults_raw = tmp_buf;
-			map->cache_free = 1;
+			map->cache_free = true;
 		} else {
 			kfree(tmp_buf);
 		}
@@ -133,6 +152,12 @@ int regcache_init(struct regmap *map, const struct regmap_config *config)
 		return -EINVAL;
 	}
 
+	if (config->num_reg_defaults && !config->reg_defaults) {
+		dev_err(map->dev,
+			"Register defaults number are set without the reg!\n");
+		return -EINVAL;
+	}
+
 	for (i = 0; i < config->num_reg_defaults; i++)
 		if (config->reg_defaults[i].reg % map->reg_stride)
 			return -EINVAL;
@@ -142,7 +167,7 @@ int regcache_init(struct regmap *map, const struct regmap_config *config)
 			break;
 
 	if (i == ARRAY_SIZE(cache_types)) {
-		dev_err(map->dev, "Could not match compress type: %d\n",
+		dev_err(map->dev, "Could not match cache type: %d\n",
 			map->cache_type);
 		return -EINVAL;
 	}
@@ -150,7 +175,7 @@ int regcache_init(struct regmap *map, const struct regmap_config *config)
 	map->num_reg_defaults = config->num_reg_defaults;
 	map->num_reg_defaults_raw = config->num_reg_defaults_raw;
 	map->reg_defaults_raw = config->reg_defaults_raw;
-	map->cache_word_size = DIV_ROUND_UP(config->val_bits, 8);
+	map->cache_word_size = BITS_TO_BYTES(config->val_bits);
 	map->cache_size_raw = map->cache_word_size * config->num_reg_defaults_raw;
 
 	map->cache = NULL;
@@ -166,8 +191,8 @@ int regcache_init(struct regmap *map, const struct regmap_config *config)
 	 * a copy of it.
 	 */
 	if (config->reg_defaults) {
-		tmp_buf = kmemdup(config->reg_defaults, map->num_reg_defaults *
-				  sizeof(struct reg_default), GFP_KERNEL);
+		tmp_buf = kmemdup_array(config->reg_defaults, map->num_reg_defaults,
+					sizeof(*map->reg_defaults), GFP_KERNEL);
 		if (!tmp_buf)
 			return -ENOMEM;
 		map->reg_defaults = tmp_buf;
@@ -183,18 +208,38 @@ int regcache_init(struct regmap *map, const struct regmap_config *config)
 			return 0;
 	}
 
-	if (!map->max_register)
-		map->max_register = map->num_reg_defaults_raw;
+	if (!map->max_register_is_set && map->num_reg_defaults_raw) {
+		map->max_register = (map->num_reg_defaults_raw  - 1) * map->reg_stride;
+		map->max_register_is_set = true;
+	}
 
 	if (map->cache_ops->init) {
 		dev_dbg(map->dev, "Initializing %s cache\n",
 			map->cache_ops->name);
+		map->lock(map->lock_arg);
 		ret = map->cache_ops->init(map);
+		map->unlock(map->lock_arg);
 		if (ret)
 			goto err_free;
 	}
+
+	if (map->num_reg_defaults && map->cache_ops->populate) {
+		dev_dbg(map->dev, "Populating %s cache\n", map->cache_ops->name);
+		map->lock(map->lock_arg);
+		ret = map->cache_ops->populate(map);
+		map->unlock(map->lock_arg);
+		if (ret)
+			goto err_exit;
+	}
 	return 0;
 
+err_exit:
+	if (map->cache_ops->exit) {
+		dev_dbg(map->dev, "Destroying %s cache\n", map->cache_ops->name);
+		map->lock(map->lock_arg);
+		ret = map->cache_ops->exit(map);
+		map->unlock(map->lock_arg);
+	}
 err_free:
 	kfree(map->reg_defaults);
 	if (map->cache_free)
@@ -217,7 +262,9 @@ void regcache_exit(struct regmap *map)
 	if (map->cache_ops->exit) {
 		dev_dbg(map->dev, "Destroying %s cache\n",
 			map->cache_ops->name);
+		map->lock(map->lock_arg);
 		map->cache_ops->exit(map);
+		map->unlock(map->lock_arg);
 	}
 }
 
@@ -236,7 +283,7 @@ int regcache_read(struct regmap *map,
 	int ret;
 
 	if (map->cache_type == REGCACHE_NONE)
-		return -ENOSYS;
+		return -EINVAL;
 
 	BUG_ON(!map->cache_ops);
 
@@ -275,11 +322,14 @@ int regcache_write(struct regmap *map,
 	return 0;
 }
 
-static bool regcache_reg_needs_sync(struct regmap *map, unsigned int reg,
-				    unsigned int val)
+bool regcache_reg_needs_sync(struct regmap *map, unsigned int reg,
+			     unsigned int val)
 {
 	int ret;
 
+	if (!regmap_writeable(map, reg))
+		return false;
+
 	/* If we don't know the chip just got reset, then sync everything. */
 	if (!map->no_sync_defaults)
 		return true;
@@ -305,6 +355,8 @@ static int regcache_default_sync(struct regmap *map, unsigned int min,
 			continue;
 
 		ret = regcache_read(map, reg, &val);
+		if (ret == -ENOENT)
+			continue;
 		if (ret)
 			return ret;
 
@@ -325,6 +377,11 @@ static int regcache_default_sync(struct regmap *map, unsigned int min,
 	return 0;
 }
 
+static int rbtree_all(const void *key, const struct rb_node *node)
+{
+	return 0;
+}
+
 /**
  * regcache_sync - Sync the register cache with the hardware.
  *
@@ -342,6 +399,10 @@ int regcache_sync(struct regmap *map)
 	unsigned int i;
 	const char *name;
 	bool bypass;
+	struct rb_node *node;
+
+	if (WARN_ON(map->cache_type == REGCACHE_NONE))
+		return -EINVAL;
 
 	BUG_ON(!map->cache_ops);
 
@@ -356,8 +417,6 @@ int regcache_sync(struct regmap *map)
 	if (!map->cache_dirty)
 		goto out;
 
-	map->async = true;
-
 	/* Apply any patch first */
 	map->cache_bypass = true;
 	for (i = 0; i < map->patch_regs; i++) {
@@ -380,9 +439,31 @@ int regcache_sync(struct regmap *map)
 
 out:
 	/* Restore the bypass state */
-	map->async = false;
 	map->cache_bypass = bypass;
 	map->no_sync_defaults = false;
+
+	/*
+	 * If we did any paging with cache bypassed and a cached
+	 * paging register then the register and cache state might
+	 * have gone out of sync, force writes of all the paging
+	 * registers.
+	 */
+	rb_for_each(node, NULL, &map->range_tree, rbtree_all) {
+		struct regmap_range_node *this =
+			rb_entry(node, struct regmap_range_node, node);
+
+		/* If there's nothing in the cache there's nothing to sync */
+		if (regcache_read(map, this->selector_reg, &i) != 0)
+			continue;
+
+		ret = _regmap_write(map, this->selector_reg, i);
+		if (ret != 0) {
+			dev_err(map->dev, "Failed to write %x = %x: %d\n",
+				this->selector_reg, i, ret);
+			break;
+		}
+	}
+
 	map->unlock(map->lock_arg);
 
 	regmap_async_complete(map);
@@ -412,6 +493,9 @@ int regcache_sync_region(struct regmap *map, unsigned int min,
 	const char *name;
 	bool bypass;
 
+	if (WARN_ON(map->cache_type == REGCACHE_NONE))
+		return -EINVAL;
+
 	BUG_ON(!map->cache_ops);
 
 	map->lock(map->lock_arg);
@@ -495,7 +579,8 @@ EXPORT_SYMBOL_GPL(regcache_drop_region);
 void regcache_cache_only(struct regmap *map, bool enable)
 {
 	map->lock(map->lock_arg);
-	WARN_ON(map->cache_bypass && enable);
+	WARN_ON(map->cache_type != REGCACHE_NONE &&
+		map->cache_bypass && enable);
 	map->cache_only = enable;
 	trace_regmap_cache_only(map, enable);
 	map->unlock(map->lock_arg);
@@ -531,7 +616,7 @@ EXPORT_SYMBOL_GPL(regcache_mark_dirty);
  * @enable: flag if changes should not be written to the cache
  *
  * When a register map is marked with the cache bypass option, writes
- * to the register map API will only update the hardware and not the
+ * to the register map API will only update the hardware and not
  * the cache directly.  This is useful when syncing the cache back to
  * the hardware.
  */
@@ -545,17 +630,37 @@ void regcache_cache_bypass(struct regmap *map, bool enable)
 }
 EXPORT_SYMBOL_GPL(regcache_cache_bypass);
 
-bool regcache_set_val(struct regmap *map, void *base, unsigned int idx,
-		      unsigned int val)
+/**
+ * regcache_reg_cached - Check if a register is cached
+ *
+ * @map: map to check
+ * @reg: register to check
+ *
+ * Reports if a register is cached.
+ */
+bool regcache_reg_cached(struct regmap *map, unsigned int reg)
 {
-	if (regcache_get_val(map, base, idx) == val)
-		return true;
+	unsigned int val;
+	int ret;
+
+	map->lock(map->lock_arg);
 
+	ret = regcache_read(map, reg, &val);
+
+	map->unlock(map->lock_arg);
+
+	return ret == 0;
+}
+EXPORT_SYMBOL_GPL(regcache_reg_cached);
+
+void regcache_set_val(struct regmap *map, void *base, unsigned int idx,
+		      unsigned int val)
+{
 	/* Use device native format if possible */
 	if (map->format.format_val) {
 		map->format.format_val(base + (map->cache_word_size * idx),
 				       val, 0);
-		return false;
+		return;
 	}
 
 	switch (map->cache_word_size) {
@@ -577,18 +682,9 @@ bool regcache_set_val(struct regmap *map, void *base, unsigned int idx,
 		cache[idx] = val;
 		break;
 	}
-#ifdef CONFIG_64BIT
-	case 8: {
-		u64 *cache = base;
-
-		cache[idx] = val;
-		break;
-	}
-#endif
 	default:
 		BUG();
 	}
-	return false;
 }
 
 unsigned int regcache_get_val(struct regmap *map, const void *base,
@@ -618,13 +714,6 @@ unsigned int regcache_get_val(struct regmap *map, const void *base,
 
 		return cache[idx];
 	}
-#ifdef CONFIG_64BIT
-	case 8: {
-		const u64 *cache = base;
-
-		return cache[idx];
-	}
-#endif
 	default:
 		BUG();
 	}
@@ -665,6 +754,30 @@ static bool regcache_reg_present(unsigned long *cache_present, unsigned int idx)
 	return test_bit(idx, cache_present);
 }
 
+int regcache_sync_val(struct regmap *map, unsigned int reg, unsigned int val)
+{
+	int ret;
+
+	if (!regcache_reg_needs_sync(map, reg, val))
+		return 0;
+
+	map->cache_bypass = true;
+
+	ret = _regmap_write(map, reg, val);
+
+	map->cache_bypass = false;
+
+	if (ret != 0) {
+		dev_err(map->dev, "Unable to sync register %#x. %d\n",
+			reg, ret);
+		return ret;
+	}
+	dev_dbg(map->dev, "Synced register %#x, value %#x\n",
+		reg, val);
+
+	return 0;
+}
+
 static int regcache_sync_block_single(struct regmap *map, void *block,
 				      unsigned long *cache_present,
 				      unsigned int block_base,
@@ -681,21 +794,9 @@ static int regcache_sync_block_single(struct regmap *map, void *block,
 			continue;
 
 		val = regcache_get_val(map, block, i);
-		if (!regcache_reg_needs_sync(map, regtmp, val))
-			continue;
-
-		map->cache_bypass = true;
-
-		ret = _regmap_write(map, regtmp, val);
-
-		map->cache_bypass = false;
-		if (ret != 0) {
-			dev_err(map->dev, "Unable to sync register %#x. %d\n",
-				regtmp, ret);
+		ret = regcache_sync_val(map, regtmp, val);
+		if (ret != 0)
 			return ret;
-		}
-		dev_dbg(map->dev, "Synced register %#x, value %#x\n",
-			regtmp, val);
 	}
 
 	return 0;
@@ -717,7 +818,7 @@ static int regcache_sync_block_raw_flush(struct regmap *map, const void **data,
 
 	map->cache_bypass = true;
 
-	ret = _regmap_raw_write(map, base, *data, count * val_bytes);
+	ret = _regmap_raw_write(map, base, *data, count * val_bytes, false);
 	if (ret)
 		dev_err(map->dev, "Unable to sync registers %#x-%#x. %d\n",
 			base, cur - map->reg_stride, ret);
diff --git a/drivers/base/regmap/regmap-ac97.c b/drivers/base/regmap/regmap-ac97.c
index b9f76bdf74a9..a561971c459c 100644
--- a/drivers/base/regmap/regmap-ac97.c
+++ b/drivers/base/regmap/regmap-ac97.c
@@ -86,4 +86,5 @@ struct regmap *__devm_regmap_init_ac97(struct snd_ac97 *ac97,
 }
 EXPORT_SYMBOL_GPL(__devm_regmap_init_ac97);
 
+MODULE_DESCRIPTION("Register map access API - AC'97 support");
 MODULE_LICENSE("GPL v2");
diff --git a/drivers/base/regmap/regmap-debugfs.c b/drivers/base/regmap/regmap-debugfs.c
index e72843fe41df..c9b4c04b1cf6 100644
--- a/drivers/base/regmap/regmap-debugfs.c
+++ b/drivers/base/regmap/regmap-debugfs.c
@@ -17,7 +17,6 @@
 
 struct regmap_debugfs_node {
 	struct regmap *map;
-	const char *name;
 	struct list_head link;
 };
 
@@ -49,7 +48,7 @@ static ssize_t regmap_name_read_file(struct file *file,
 		name = map->dev->driver->name;
 
 	ret = snprintf(buf, PAGE_SIZE, "%s\n", name);
-	if (ret < 0) {
+	if (ret >= PAGE_SIZE) {
 		kfree(buf);
 		return ret;
 	}
@@ -184,7 +183,7 @@ static inline void regmap_calc_tot_len(struct regmap *map,
 {
 	/* Calculate the length of a fixed format  */
 	if (!map->debugfs_tot_len) {
-		map->debugfs_reg_len = regmap_calc_reg_len(map->max_register),
+		map->debugfs_reg_len = regmap_calc_reg_len(map->max_register);
 		map->debugfs_val_len = 2 * map->format.val_bytes;
 		map->debugfs_tot_len = map->debugfs_reg_len +
 			map->debugfs_val_len + 3;      /* : \n */
@@ -227,6 +226,9 @@ static ssize_t regmap_read_debugfs(struct regmap *map, unsigned int from,
 	if (*ppos < 0 || !count)
 		return -EINVAL;
 
+	if (count > (PAGE_SIZE << MAX_PAGE_ORDER))
+		count = PAGE_SIZE << MAX_PAGE_ORDER;
+
 	buf = kmalloc(count, GFP_KERNEL);
 	if (!buf)
 		return -ENOMEM;
@@ -366,11 +368,14 @@ static ssize_t regmap_reg_ranges_read_file(struct file *file,
 	char *buf;
 	char *entry;
 	int ret;
-	unsigned entry_len;
+	unsigned int entry_len;
 
 	if (*ppos < 0 || !count)
 		return -EINVAL;
 
+	if (count > (PAGE_SIZE << MAX_PAGE_ORDER))
+		count = PAGE_SIZE << MAX_PAGE_ORDER;
+
 	buf = kmalloc(count, GFP_KERNEL);
 	if (!buf)
 		return -ENOMEM;
@@ -457,27 +462,24 @@ static ssize_t regmap_cache_only_write_file(struct file *file,
 {
 	struct regmap *map = container_of(file->private_data,
 					  struct regmap, cache_only);
-	ssize_t result;
-	bool was_enabled, require_sync = false;
+	bool new_val, require_sync = false;
 	int err;
 
-	map->lock(map->lock_arg);
+	err = kstrtobool_from_user(user_buf, count, &new_val);
+	/* Ignore malforned data like debugfs_write_file_bool() */
+	if (err)
+		return count;
 
-	was_enabled = map->cache_only;
-
-	result = debugfs_write_file_bool(file, user_buf, count, ppos);
-	if (result < 0) {
-		map->unlock(map->lock_arg);
-		return result;
-	}
+	map->lock(map->lock_arg);
 
-	if (map->cache_only && !was_enabled) {
+	if (new_val && !map->cache_only) {
 		dev_warn(map->dev, "debugfs cache_only=Y forced\n");
 		add_taint(TAINT_USER, LOCKDEP_STILL_OK);
-	} else if (!map->cache_only && was_enabled) {
+	} else if (!new_val && map->cache_only) {
 		dev_warn(map->dev, "debugfs cache_only=N forced: syncing cache\n");
 		require_sync = true;
 	}
+	map->cache_only = new_val;
 
 	map->unlock(map->lock_arg);
 
@@ -487,7 +489,7 @@ static ssize_t regmap_cache_only_write_file(struct file *file,
 			dev_err(map->dev, "Failed to sync cache %d\n", err);
 	}
 
-	return result;
+	return count;
 }
 
 static const struct file_operations regmap_cache_only_fops = {
@@ -502,28 +504,27 @@ static ssize_t regmap_cache_bypass_write_file(struct file *file,
 {
 	struct regmap *map = container_of(file->private_data,
 					  struct regmap, cache_bypass);
-	ssize_t result;
-	bool was_enabled;
-
-	map->lock(map->lock_arg);
+	bool new_val;
+	int err;
 
-	was_enabled = map->cache_bypass;
+	err = kstrtobool_from_user(user_buf, count, &new_val);
+	/* Ignore malforned data like debugfs_write_file_bool() */
+	if (err)
+		return count;
 
-	result = debugfs_write_file_bool(file, user_buf, count, ppos);
-	if (result < 0)
-		goto out;
+	map->lock(map->lock_arg);
 
-	if (map->cache_bypass && !was_enabled) {
+	if (new_val && !map->cache_bypass) {
 		dev_warn(map->dev, "debugfs cache_bypass=Y forced\n");
 		add_taint(TAINT_USER, LOCKDEP_STILL_OK);
-	} else if (!map->cache_bypass && was_enabled) {
+	} else if (!new_val && map->cache_bypass) {
 		dev_warn(map->dev, "debugfs cache_bypass=N forced\n");
 	}
+	map->cache_bypass = new_val;
 
-out:
 	map->unlock(map->lock_arg);
 
-	return result;
+	return count;
 }
 
 static const struct file_operations regmap_cache_bypass_fops = {
@@ -532,11 +533,12 @@ static const struct file_operations regmap_cache_bypass_fops = {
 	.write = regmap_cache_bypass_write_file,
 };
 
-void regmap_debugfs_init(struct regmap *map, const char *name)
+void regmap_debugfs_init(struct regmap *map)
 {
 	struct rb_node *next;
 	struct regmap_range_node *range_node;
 	const char *devname = "dummy";
+	const char *name = map->name;
 
 	/*
 	 * Userspace can initiate reads from the hardware over debugfs.
@@ -557,7 +559,6 @@ void regmap_debugfs_init(struct regmap *map, const char *name)
 		if (!node)
 			return;
 		node->map = map;
-		node->name = name;
 		mutex_lock(&regmap_debugfs_early_lock);
 		list_add(&node->link, &regmap_debugfs_early_list);
 		mutex_unlock(&regmap_debugfs_early_lock);
@@ -571,8 +572,12 @@ void regmap_debugfs_init(struct regmap *map, const char *name)
 		devname = dev_name(map->dev);
 
 	if (name) {
-		map->debugfs_name = kasprintf(GFP_KERNEL, "%s-%s",
+		if (!map->debugfs_name) {
+			map->debugfs_name = kasprintf(GFP_KERNEL, "%s-%s",
 					      devname, name);
+			if (!map->debugfs_name)
+				return;
+		}
 		name = map->debugfs_name;
 	} else {
 		name = devname;
@@ -580,9 +585,10 @@ void regmap_debugfs_init(struct regmap *map, const char *name)
 
 	if (!strcmp(name, "dummy")) {
 		kfree(map->debugfs_name);
-
 		map->debugfs_name = kasprintf(GFP_KERNEL, "dummy%d",
 						dummy_index);
+		if (!map->debugfs_name)
+			return;
 		name = map->debugfs_name;
 		dummy_index++;
 	}
@@ -620,6 +626,17 @@ void regmap_debugfs_init(struct regmap *map, const char *name)
 				    &regmap_cache_bypass_fops);
 	}
 
+	/*
+	 * This could interfere with driver operation. Therefore, don't provide
+	 * any real compile time configuration option for this feature. One will
+	 * have to modify the source code directly in order to use it.
+	 */
+#undef REGMAP_ALLOW_FORCE_WRITE_FIELD_DEBUGFS
+#ifdef REGMAP_ALLOW_FORCE_WRITE_FIELD_DEBUGFS
+	debugfs_create_bool("force_write_field", 0600, map->debugfs,
+			    &map->force_write_field);
+#endif
+
 	next = rb_first(&map->range_tree);
 	while (next) {
 		range_node = rb_entry(next, struct regmap_range_node, node);
@@ -644,6 +661,7 @@ void regmap_debugfs_exit(struct regmap *map)
 		regmap_debugfs_free_dump_cache(map);
 		mutex_unlock(&map->cache_lock);
 		kfree(map->debugfs_name);
+		map->debugfs_name = NULL;
 	} else {
 		struct regmap_debugfs_node *node, *tmp;
 
@@ -667,7 +685,7 @@ void regmap_debugfs_initcall(void)
 
 	mutex_lock(&regmap_debugfs_early_lock);
 	list_for_each_entry_safe(node, tmp, &regmap_debugfs_early_list, link) {
-		regmap_debugfs_init(node->map, node->name);
+		regmap_debugfs_init(node->map);
 		list_del(&node->link);
 		kfree(node);
 	}
diff --git a/drivers/base/regmap/regmap-fsi.c b/drivers/base/regmap/regmap-fsi.c
new file mode 100644
index 000000000000..3d2f3cb31d5e
--- /dev/null
+++ b/drivers/base/regmap/regmap-fsi.c
@@ -0,0 +1,231 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Register map access API - FSI support
+//
+// Copyright 2022 IBM Corp
+//
+// Author: Eddie James <eajames@linux.ibm.com>
+
+#include <linux/fsi.h>
+#include <linux/module.h>
+#include <linux/regmap.h>
+
+#include "internal.h"
+
+static int regmap_fsi32_reg_read(void *context, unsigned int reg, unsigned int *val)
+{
+	u32 v;
+	int ret;
+
+	ret = fsi_slave_read(context, reg, &v, sizeof(v));
+	if (ret)
+		return ret;
+
+	*val = v;
+	return 0;
+}
+
+static int regmap_fsi32_reg_write(void *context, unsigned int reg, unsigned int val)
+{
+	u32 v = val;
+
+	return fsi_slave_write(context, reg, &v, sizeof(v));
+}
+
+static const struct regmap_bus regmap_fsi32 = {
+	.reg_write = regmap_fsi32_reg_write,
+	.reg_read = regmap_fsi32_reg_read,
+};
+
+static int regmap_fsi32le_reg_read(void *context, unsigned int reg, unsigned int *val)
+{
+	__be32 v;
+	int ret;
+
+	ret = fsi_slave_read(context, reg, &v, sizeof(v));
+	if (ret)
+		return ret;
+
+	*val = be32_to_cpu(v);
+	return 0;
+}
+
+static int regmap_fsi32le_reg_write(void *context, unsigned int reg, unsigned int val)
+{
+	__be32 v = cpu_to_be32(val);
+
+	return fsi_slave_write(context, reg, &v, sizeof(v));
+}
+
+static const struct regmap_bus regmap_fsi32le = {
+	.reg_write = regmap_fsi32le_reg_write,
+	.reg_read = regmap_fsi32le_reg_read,
+};
+
+static int regmap_fsi16_reg_read(void *context, unsigned int reg, unsigned int *val)
+{
+	u16 v;
+	int ret;
+
+	ret = fsi_slave_read(context, reg, &v, sizeof(v));
+	if (ret)
+		return ret;
+
+	*val = v;
+	return 0;
+}
+
+static int regmap_fsi16_reg_write(void *context, unsigned int reg, unsigned int val)
+{
+	u16 v;
+
+	if (val > 0xffff)
+		return -EINVAL;
+
+	v = val;
+	return fsi_slave_write(context, reg, &v, sizeof(v));
+}
+
+static const struct regmap_bus regmap_fsi16 = {
+	.reg_write = regmap_fsi16_reg_write,
+	.reg_read = regmap_fsi16_reg_read,
+};
+
+static int regmap_fsi16le_reg_read(void *context, unsigned int reg, unsigned int *val)
+{
+	__be16 v;
+	int ret;
+
+	ret = fsi_slave_read(context, reg, &v, sizeof(v));
+	if (ret)
+		return ret;
+
+	*val = be16_to_cpu(v);
+	return 0;
+}
+
+static int regmap_fsi16le_reg_write(void *context, unsigned int reg, unsigned int val)
+{
+	__be16 v;
+
+	if (val > 0xffff)
+		return -EINVAL;
+
+	v = cpu_to_be16(val);
+	return fsi_slave_write(context, reg, &v, sizeof(v));
+}
+
+static const struct regmap_bus regmap_fsi16le = {
+	.reg_write = regmap_fsi16le_reg_write,
+	.reg_read = regmap_fsi16le_reg_read,
+};
+
+static int regmap_fsi8_reg_read(void *context, unsigned int reg, unsigned int *val)
+{
+	u8 v;
+	int ret;
+
+	ret = fsi_slave_read(context, reg, &v, sizeof(v));
+	if (ret)
+		return ret;
+
+	*val = v;
+	return 0;
+}
+
+static int regmap_fsi8_reg_write(void *context, unsigned int reg, unsigned int val)
+{
+	u8 v;
+
+	if (val > 0xff)
+		return -EINVAL;
+
+	v = val;
+	return fsi_slave_write(context, reg, &v, sizeof(v));
+}
+
+static const struct regmap_bus regmap_fsi8 = {
+	.reg_write = regmap_fsi8_reg_write,
+	.reg_read = regmap_fsi8_reg_read,
+};
+
+static const struct regmap_bus *regmap_get_fsi_bus(struct fsi_device *fsi_dev,
+						   const struct regmap_config *config)
+{
+	const struct regmap_bus *bus = NULL;
+
+	if (config->reg_bits == 8 || config->reg_bits == 16 || config->reg_bits == 32) {
+		switch (config->val_bits) {
+		case 8:
+			bus = &regmap_fsi8;
+			break;
+		case 16:
+			switch (regmap_get_val_endian(&fsi_dev->dev, NULL, config)) {
+			case REGMAP_ENDIAN_LITTLE:
+#ifdef __LITTLE_ENDIAN
+			case REGMAP_ENDIAN_NATIVE:
+#endif
+				bus = &regmap_fsi16le;
+				break;
+			case REGMAP_ENDIAN_DEFAULT:
+			case REGMAP_ENDIAN_BIG:
+#ifdef __BIG_ENDIAN
+			case REGMAP_ENDIAN_NATIVE:
+#endif
+				bus = &regmap_fsi16;
+				break;
+			default:
+				break;
+			}
+			break;
+		case 32:
+			switch (regmap_get_val_endian(&fsi_dev->dev, NULL, config)) {
+			case REGMAP_ENDIAN_LITTLE:
+#ifdef __LITTLE_ENDIAN
+			case REGMAP_ENDIAN_NATIVE:
+#endif
+				bus = &regmap_fsi32le;
+				break;
+			case REGMAP_ENDIAN_DEFAULT:
+			case REGMAP_ENDIAN_BIG:
+#ifdef __BIG_ENDIAN
+			case REGMAP_ENDIAN_NATIVE:
+#endif
+				bus = &regmap_fsi32;
+				break;
+			default:
+				break;
+			}
+			break;
+		}
+	}
+
+	return bus ?: ERR_PTR(-EOPNOTSUPP);
+}
+
+struct regmap *__regmap_init_fsi(struct fsi_device *fsi_dev, const struct regmap_config *config,
+				 struct lock_class_key *lock_key, const char *lock_name)
+{
+	const struct regmap_bus *bus = regmap_get_fsi_bus(fsi_dev, config);
+
+	if (IS_ERR(bus))
+		return ERR_CAST(bus);
+
+	return __regmap_init(&fsi_dev->dev, bus, fsi_dev->slave, config, lock_key, lock_name);
+}
+EXPORT_SYMBOL_GPL(__regmap_init_fsi);
+
+struct regmap *__devm_regmap_init_fsi(struct fsi_device *fsi_dev,
+				      const struct regmap_config *config,
+				      struct lock_class_key *lock_key, const char *lock_name)
+{
+	const struct regmap_bus *bus = regmap_get_fsi_bus(fsi_dev, config);
+
+	if (IS_ERR(bus))
+		return ERR_CAST(bus);
+
+	return __devm_regmap_init(&fsi_dev->dev, bus, fsi_dev->slave, config, lock_key, lock_name);
+}
+EXPORT_SYMBOL_GPL(__devm_regmap_init_fsi);
+
+MODULE_LICENSE("GPL");
diff --git a/drivers/base/regmap/regmap-i2c.c b/drivers/base/regmap/regmap-i2c.c
index 008f8da69d97..c9b39a02278e 100644
--- a/drivers/base/regmap/regmap-i2c.c
+++ b/drivers/base/regmap/regmap-i2c.c
@@ -242,36 +242,129 @@ static int regmap_i2c_smbus_i2c_read(void *context, const void *reg,
 static const struct regmap_bus regmap_i2c_smbus_i2c_block = {
 	.write = regmap_i2c_smbus_i2c_write,
 	.read = regmap_i2c_smbus_i2c_read,
-	.max_raw_read = I2C_SMBUS_BLOCK_MAX,
-	.max_raw_write = I2C_SMBUS_BLOCK_MAX,
+	.max_raw_read = I2C_SMBUS_BLOCK_MAX - 1,
+	.max_raw_write = I2C_SMBUS_BLOCK_MAX - 1,
+};
+
+static int regmap_i2c_smbus_i2c_write_reg16(void *context, const void *data,
+				      size_t count)
+{
+	struct device *dev = context;
+	struct i2c_client *i2c = to_i2c_client(dev);
+
+	if (count < 2)
+		return -EINVAL;
+
+	count--;
+	return i2c_smbus_write_i2c_block_data(i2c, ((u8 *)data)[0], count,
+					      (u8 *)data + 1);
+}
+
+static int regmap_i2c_smbus_i2c_read_reg16(void *context, const void *reg,
+				     size_t reg_size, void *val,
+				     size_t val_size)
+{
+	struct device *dev = context;
+	struct i2c_client *i2c = to_i2c_client(dev);
+	int ret, count, len = val_size;
+
+	if (reg_size != 2)
+		return -EINVAL;
+
+	ret = i2c_smbus_write_byte_data(i2c, ((u16 *)reg)[0] & 0xff,
+					((u16 *)reg)[0] >> 8);
+	if (ret < 0)
+		return ret;
+
+	count = 0;
+	do {
+		/* Current Address Read */
+		ret = i2c_smbus_read_byte(i2c);
+		if (ret < 0)
+			break;
+
+		*((u8 *)val++) = ret;
+		count++;
+		len--;
+	} while (len > 0);
+
+	if (count == val_size)
+		return 0;
+	else if (ret < 0)
+		return ret;
+	else
+		return -EIO;
+}
+
+static const struct regmap_bus regmap_i2c_smbus_i2c_block_reg16 = {
+	.write = regmap_i2c_smbus_i2c_write_reg16,
+	.read = regmap_i2c_smbus_i2c_read_reg16,
+	.max_raw_read = I2C_SMBUS_BLOCK_MAX - 2,
+	.max_raw_write = I2C_SMBUS_BLOCK_MAX - 2,
 };
 
 static const struct regmap_bus *regmap_get_i2c_bus(struct i2c_client *i2c,
 					const struct regmap_config *config)
 {
+	const struct i2c_adapter_quirks *quirks;
+	const struct regmap_bus *bus = NULL;
+	struct regmap_bus *ret_bus;
+	u16 max_read = 0, max_write = 0;
+
 	if (i2c_check_functionality(i2c->adapter, I2C_FUNC_I2C))
-		return &regmap_i2c;
+		bus = &regmap_i2c;
 	else if (config->val_bits == 8 && config->reg_bits == 8 &&
 		 i2c_check_functionality(i2c->adapter,
 					 I2C_FUNC_SMBUS_I2C_BLOCK))
-		return &regmap_i2c_smbus_i2c_block;
+		bus = &regmap_i2c_smbus_i2c_block;
+	else if (config->val_bits == 8 && config->reg_bits == 16 &&
+		i2c_check_functionality(i2c->adapter,
+					I2C_FUNC_SMBUS_I2C_BLOCK))
+		bus = &regmap_i2c_smbus_i2c_block_reg16;
 	else if (config->val_bits == 16 && config->reg_bits == 8 &&
 		 i2c_check_functionality(i2c->adapter,
 					 I2C_FUNC_SMBUS_WORD_DATA))
 		switch (regmap_get_val_endian(&i2c->dev, NULL, config)) {
 		case REGMAP_ENDIAN_LITTLE:
-			return &regmap_smbus_word;
+			bus = &regmap_smbus_word;
+			break;
 		case REGMAP_ENDIAN_BIG:
-			return &regmap_smbus_word_swapped;
+			bus = &regmap_smbus_word_swapped;
+			break;
 		default:		/* everything else is not supported */
 			break;
 		}
 	else if (config->val_bits == 8 && config->reg_bits == 8 &&
 		 i2c_check_functionality(i2c->adapter,
 					 I2C_FUNC_SMBUS_BYTE_DATA))
-		return &regmap_smbus_byte;
+		bus = &regmap_smbus_byte;
+
+	if (!bus)
+		return ERR_PTR(-ENOTSUPP);
+
+	quirks = i2c->adapter->quirks;
+	if (quirks) {
+		if (quirks->max_read_len &&
+		    (bus->max_raw_read == 0 || bus->max_raw_read > quirks->max_read_len))
+			max_read = quirks->max_read_len;
+
+		if (quirks->max_write_len &&
+		    (bus->max_raw_write == 0 || bus->max_raw_write > quirks->max_write_len))
+			max_write = quirks->max_write_len -
+				(config->reg_bits + config->pad_bits) / BITS_PER_BYTE;
+
+		if (max_read || max_write) {
+			ret_bus = kmemdup(bus, sizeof(*bus), GFP_KERNEL);
+			if (!ret_bus)
+				return ERR_PTR(-ENOMEM);
+			ret_bus->free_on_exit = true;
+			ret_bus->max_raw_read = max_read;
+			ret_bus->max_raw_write = max_write;
+			bus = ret_bus;
+		}
+	}
 
-	return ERR_PTR(-ENOTSUPP);
+	return bus;
 }
 
 struct regmap *__regmap_init_i2c(struct i2c_client *i2c,
@@ -304,4 +397,5 @@ struct regmap *__devm_regmap_init_i2c(struct i2c_client *i2c,
 }
 EXPORT_SYMBOL_GPL(__devm_regmap_init_i2c);
 
+MODULE_DESCRIPTION("Register map access API - I2C support");
 MODULE_LICENSE("GPL");
diff --git a/drivers/base/regmap/regmap-i3c.c b/drivers/base/regmap/regmap-i3c.c
index 1578fb506683..863b348704dc 100644
--- a/drivers/base/regmap/regmap-i3c.c
+++ b/drivers/base/regmap/regmap-i3c.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 // Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
 
+#include <linux/array_size.h>
 #include <linux/regmap.h>
 #include <linux/i3c/device.h>
 #include <linux/i3c/master.h>
@@ -10,7 +11,7 @@ static int regmap_i3c_write(void *context, const void *data, size_t count)
 {
 	struct device *dev = context;
 	struct i3c_device *i3c = dev_to_i3cdev(dev);
-	struct i3c_priv_xfer xfers[] = {
+	struct i3c_xfer xfers[] = {
 		{
 			.rnw = false,
 			.len = count,
@@ -18,7 +19,7 @@ static int regmap_i3c_write(void *context, const void *data, size_t count)
 		},
 	};
 
-	return i3c_device_do_priv_xfers(i3c, xfers, 1);
+	return i3c_device_do_xfers(i3c, xfers, ARRAY_SIZE(xfers), I3C_SDR);
 }
 
 static int regmap_i3c_read(void *context,
@@ -27,7 +28,7 @@ static int regmap_i3c_read(void *context,
 {
 	struct device *dev = context;
 	struct i3c_device *i3c = dev_to_i3cdev(dev);
-	struct i3c_priv_xfer xfers[2];
+	struct i3c_xfer xfers[2];
 
 	xfers[0].rnw = false;
 	xfers[0].len = reg_size;
@@ -37,10 +38,10 @@ static int regmap_i3c_read(void *context,
 	xfers[1].len = val_size;
 	xfers[1].data.in = val;
 
-	return i3c_device_do_priv_xfers(i3c, xfers, 2);
+	return i3c_device_do_xfers(i3c, xfers, ARRAY_SIZE(xfers), I3C_SDR);
 }
 
-static struct regmap_bus regmap_i3c = {
+static const struct regmap_bus regmap_i3c = {
 	.write = regmap_i3c_write,
 	.read = regmap_i3c_read,
 };
@@ -56,5 +57,5 @@ struct regmap *__devm_regmap_init_i3c(struct i3c_device *i3c,
 EXPORT_SYMBOL_GPL(__devm_regmap_init_i3c);
 
 MODULE_AUTHOR("Vitor Soares <vitor.soares@synopsys.com>");
-MODULE_DESCRIPTION("Regmap I3C Module");
+MODULE_DESCRIPTION("regmap I3C Module");
 MODULE_LICENSE("GPL v2");
diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c
index 3d64c9331a82..6112d942499b 100644
--- a/drivers/base/regmap/regmap-irq.c
+++ b/drivers/base/regmap/regmap-irq.c
@@ -6,11 +6,13 @@
 //
 // Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
 
+#include <linux/array_size.h>
 #include <linux/device.h>
 #include <linux/export.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/irqdomain.h>
+#include <linux/overflow.h>
 #include <linux/pm_runtime.h>
 #include <linux/regmap.h>
 #include <linux/slab.h>
@@ -19,6 +21,7 @@
 
 struct regmap_irq_chip_data {
 	struct mutex lock;
+	struct lock_class_key lock_key;
 	struct irq_chip irq_chip;
 
 	struct regmap *map;
@@ -33,16 +36,20 @@ struct regmap_irq_chip_data {
 	void *status_reg_buf;
 	unsigned int *main_status_buf;
 	unsigned int *status_buf;
+	unsigned int *prev_status_buf;
 	unsigned int *mask_buf;
 	unsigned int *mask_buf_def;
 	unsigned int *wake_buf;
 	unsigned int *type_buf;
 	unsigned int *type_buf_def;
+	unsigned int **config_buf;
 
 	unsigned int irq_reg_stride;
-	unsigned int type_reg_stride;
 
-	bool clear_status:1;
+	unsigned int (*get_irq_reg)(struct regmap_irq_chip_data *data,
+				    unsigned int base, int index);
+
+	unsigned int clear_status:1;
 };
 
 static inline const
@@ -52,30 +59,33 @@ struct regmap_irq *irq_to_regmap_irq(struct regmap_irq_chip_data *data,
 	return &data->chip->irqs[irq];
 }
 
-static void regmap_irq_lock(struct irq_data *data)
+static bool regmap_irq_can_bulk_read_status(struct regmap_irq_chip_data *data)
 {
-	struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
+	struct regmap *map = data->map;
 
-	mutex_lock(&d->lock);
+	/*
+	 * While possible that a user-defined ->get_irq_reg() callback might
+	 * be linear enough to support bulk reads, most of the time it won't.
+	 * Therefore only allow them if the default callback is being used.
+	 */
+	return data->irq_reg_stride == 1 && map->reg_stride == 1 &&
+	       data->get_irq_reg == regmap_irq_get_irq_reg_linear &&
+	       !map->use_single_read;
 }
 
-static int regmap_irq_update_bits(struct regmap_irq_chip_data *d,
-				  unsigned int reg, unsigned int mask,
-				  unsigned int val)
+static void regmap_irq_lock(struct irq_data *data)
 {
-	if (d->chip->mask_writeonly)
-		return regmap_write_bits(d->map, reg, mask, val);
-	else
-		return regmap_update_bits(d->map, reg, mask, val);
+	struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
+
+	mutex_lock(&d->lock);
 }
 
 static void regmap_irq_sync_unlock(struct irq_data *data)
 {
 	struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
 	struct regmap *map = d->map;
-	int i, ret;
+	int i, j, ret;
 	u32 reg;
-	u32 unmask_offset;
 	u32 val;
 
 	if (d->chip->runtime_pm) {
@@ -87,8 +97,7 @@ static void regmap_irq_sync_unlock(struct irq_data *data)
 
 	if (d->clear_status) {
 		for (i = 0; i < d->chip->num_regs; i++) {
-			reg = d->chip->status_base +
-				(i * map->reg_stride * d->irq_reg_stride);
+			reg = d->get_irq_reg(d, d->chip->status_base, i);
 
 			ret = regmap_read(map, reg, &val);
 			if (ret)
@@ -105,46 +114,37 @@ static void regmap_irq_sync_unlock(struct irq_data *data)
 	 * suppress pointless writes.
 	 */
 	for (i = 0; i < d->chip->num_regs; i++) {
-		if (!d->chip->mask_base)
-			continue;
+		if (d->chip->handle_mask_sync)
+			d->chip->handle_mask_sync(i, d->mask_buf_def[i],
+						  d->mask_buf[i],
+						  d->chip->irq_drv_data);
+
+		if (d->chip->mask_base && !d->chip->handle_mask_sync) {
+			reg = d->get_irq_reg(d, d->chip->mask_base, i);
+			ret = regmap_update_bits(d->map, reg,
+						 d->mask_buf_def[i],
+						 d->mask_buf[i]);
+			if (ret)
+				dev_err(d->map->dev, "Failed to sync masks in %x\n", reg);
+		}
 
-		reg = d->chip->mask_base +
-			(i * map->reg_stride * d->irq_reg_stride);
-		if (d->chip->mask_invert) {
-			ret = regmap_irq_update_bits(d, reg,
-					 d->mask_buf_def[i], ~d->mask_buf[i]);
-		} else if (d->chip->unmask_base) {
-			/* set mask with mask_base register */
-			ret = regmap_irq_update_bits(d, reg,
+		if (d->chip->unmask_base && !d->chip->handle_mask_sync) {
+			reg = d->get_irq_reg(d, d->chip->unmask_base, i);
+			ret = regmap_update_bits(d->map, reg,
 					d->mask_buf_def[i], ~d->mask_buf[i]);
-			if (ret < 0)
-				dev_err(d->map->dev,
-					"Failed to sync unmasks in %x\n",
+			if (ret)
+				dev_err(d->map->dev, "Failed to sync masks in %x\n",
 					reg);
-			unmask_offset = d->chip->unmask_base -
-							d->chip->mask_base;
-			/* clear mask with unmask_base register */
-			ret = regmap_irq_update_bits(d,
-					reg + unmask_offset,
-					d->mask_buf_def[i],
-					d->mask_buf[i]);
-		} else {
-			ret = regmap_irq_update_bits(d, reg,
-					 d->mask_buf_def[i], d->mask_buf[i]);
 		}
-		if (ret != 0)
-			dev_err(d->map->dev, "Failed to sync masks in %x\n",
-				reg);
 
-		reg = d->chip->wake_base +
-			(i * map->reg_stride * d->irq_reg_stride);
+		reg = d->get_irq_reg(d, d->chip->wake_base, i);
 		if (d->wake_buf) {
 			if (d->chip->wake_invert)
-				ret = regmap_irq_update_bits(d, reg,
+				ret = regmap_update_bits(d->map, reg,
 							 d->mask_buf_def[i],
 							 ~d->wake_buf[i]);
 			else
-				ret = regmap_irq_update_bits(d, reg,
+				ret = regmap_update_bits(d->map, reg,
 							 d->mask_buf_def[i],
 							 d->wake_buf[i]);
 			if (ret != 0)
@@ -161,35 +161,33 @@ static void regmap_irq_sync_unlock(struct irq_data *data)
 		 * it'll be ignored in irq handler, then may introduce irq storm
 		 */
 		if (d->mask_buf[i] && (d->chip->ack_base || d->chip->use_ack)) {
-			reg = d->chip->ack_base +
-				(i * map->reg_stride * d->irq_reg_stride);
+			reg = d->get_irq_reg(d, d->chip->ack_base, i);
+
 			/* some chips ack by write 0 */
 			if (d->chip->ack_invert)
 				ret = regmap_write(map, reg, ~d->mask_buf[i]);
 			else
 				ret = regmap_write(map, reg, d->mask_buf[i]);
+			if (d->chip->clear_ack) {
+				if (d->chip->ack_invert && !ret)
+					ret = regmap_write(map, reg, UINT_MAX);
+				else if (!ret)
+					ret = regmap_write(map, reg, 0);
+			}
 			if (ret != 0)
 				dev_err(d->map->dev, "Failed to ack 0x%x: %d\n",
 					reg, ret);
 		}
 	}
 
-	/* Don't update the type bits if we're using mask bits for irq type. */
-	if (!d->chip->type_in_mask) {
-		for (i = 0; i < d->chip->num_type_reg; i++) {
-			if (!d->type_buf_def[i])
-				continue;
-			reg = d->chip->type_base +
-				(i * map->reg_stride * d->type_reg_stride);
-			if (d->chip->type_invert)
-				ret = regmap_irq_update_bits(d, reg,
-					d->type_buf_def[i], ~d->type_buf[i]);
-			else
-				ret = regmap_irq_update_bits(d, reg,
-					d->type_buf_def[i], d->type_buf[i]);
-			if (ret != 0)
-				dev_err(d->map->dev, "Failed to sync type in %x\n",
-					reg);
+	for (i = 0; i < d->chip->num_config_bases; i++) {
+		for (j = 0; j < d->chip->num_config_regs; j++) {
+			reg = d->get_irq_reg(d, d->chip->config_base[i], j);
+			ret = regmap_write(map, reg, d->config_buf[i][j]);
+			if (ret)
+				dev_err(d->map->dev,
+					"Failed to write config %x: %d\n",
+					reg, ret);
 		}
 	}
 
@@ -199,10 +197,10 @@ static void regmap_irq_sync_unlock(struct irq_data *data)
 	/* If we've changed our wakeup count propagate it to the parent */
 	if (d->wake_count < 0)
 		for (i = d->wake_count; i < 0; i++)
-			irq_set_irq_wake(d->irq, 0);
+			disable_irq_wake(d->irq);
 	else if (d->wake_count > 0)
 		for (i = 0; i < d->wake_count; i++)
-			irq_set_irq_wake(d->irq, 1);
+			enable_irq_wake(d->irq);
 
 	d->wake_count = 0;
 
@@ -214,30 +212,28 @@ static void regmap_irq_enable(struct irq_data *data)
 	struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
 	struct regmap *map = d->map;
 	const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
-	unsigned int mask, type;
-
-	type = irq_data->type.type_falling_val | irq_data->type.type_rising_val;
+	unsigned int reg = irq_data->reg_offset / map->reg_stride;
+	unsigned int mask;
 
 	/*
 	 * The type_in_mask flag means that the underlying hardware uses
-	 * separate mask bits for rising and falling edge interrupts, but
-	 * we want to make them into a single virtual interrupt with
-	 * configurable edge.
+	 * separate mask bits for each interrupt trigger type, but we want
+	 * to have a single logical interrupt with a configurable type.
 	 *
-	 * If the interrupt we're enabling defines the falling or rising
-	 * masks then instead of using the regular mask bits for this
-	 * interrupt, use the value previously written to the type buffer
-	 * at the corresponding offset in regmap_irq_set_type().
+	 * If the interrupt we're enabling defines any supported types
+	 * then instead of using the regular mask bits for this interrupt,
+	 * use the value previously written to the type buffer at the
+	 * corresponding offset in regmap_irq_set_type().
 	 */
-	if (d->chip->type_in_mask && type)
-		mask = d->type_buf[irq_data->reg_offset / map->reg_stride];
+	if (d->chip->type_in_mask && irq_data->type.types_supported)
+		mask = d->type_buf[reg] & irq_data->mask;
 	else
 		mask = irq_data->mask;
 
 	if (d->chip->clear_on_unmask)
 		d->clear_status = true;
 
-	d->mask_buf[irq_data->reg_offset / map->reg_stride] &= ~mask;
+	d->mask_buf[reg] &= ~mask;
 }
 
 static void regmap_irq_disable(struct irq_data *data)
@@ -254,7 +250,7 @@ static int regmap_irq_set_type(struct irq_data *data, unsigned int type)
 	struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
 	struct regmap *map = d->map;
 	const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
-	int reg;
+	int reg, ret;
 	const struct regmap_irq_type *t = &irq_data->type;
 
 	if ((t->types_supported & type) != type)
@@ -262,37 +258,20 @@ static int regmap_irq_set_type(struct irq_data *data, unsigned int type)
 
 	reg = t->type_reg_offset / map->reg_stride;
 
-	if (t->type_reg_mask)
-		d->type_buf[reg] &= ~t->type_reg_mask;
-	else
-		d->type_buf[reg] &= ~(t->type_falling_val |
-				      t->type_rising_val |
-				      t->type_level_low_val |
-				      t->type_level_high_val);
-	switch (type) {
-	case IRQ_TYPE_EDGE_FALLING:
-		d->type_buf[reg] |= t->type_falling_val;
-		break;
-
-	case IRQ_TYPE_EDGE_RISING:
-		d->type_buf[reg] |= t->type_rising_val;
-		break;
-
-	case IRQ_TYPE_EDGE_BOTH:
-		d->type_buf[reg] |= (t->type_falling_val |
-					t->type_rising_val);
-		break;
-
-	case IRQ_TYPE_LEVEL_HIGH:
-		d->type_buf[reg] |= t->type_level_high_val;
-		break;
+	if (d->chip->type_in_mask) {
+		ret = regmap_irq_set_type_config_simple(&d->type_buf, type,
+							irq_data, reg, d->chip->irq_drv_data);
+		if (ret)
+			return ret;
+	}
 
-	case IRQ_TYPE_LEVEL_LOW:
-		d->type_buf[reg] |= t->type_level_low_val;
-		break;
-	default:
-		return -EINVAL;
+	if (d->chip->set_type_config) {
+		ret = d->chip->set_type_config(d->config_buf, type, irq_data,
+					       reg, d->chip->irq_drv_data);
+		if (ret)
+			return ret;
 	}
+
 	return 0;
 }
 
@@ -330,22 +309,26 @@ static inline int read_sub_irq_data(struct regmap_irq_chip_data *data,
 					   unsigned int b)
 {
 	const struct regmap_irq_chip *chip = data->chip;
+	const struct regmap_irq_sub_irq_map *subreg;
 	struct regmap *map = data->map;
-	struct regmap_irq_sub_irq_map *subreg;
+	unsigned int reg;
 	int i, ret = 0;
 
 	if (!chip->sub_reg_offsets) {
-		/* Assume linear mapping */
-		ret = regmap_read(map, chip->status_base +
-				  (b * map->reg_stride * data->irq_reg_stride),
-				   &data->status_buf[b]);
+		reg = data->get_irq_reg(data, chip->status_base, b);
+		ret = regmap_read(map, reg, &data->status_buf[b]);
 	} else {
+		/*
+		 * Note we can't use ->get_irq_reg() here because the offsets
+		 * in 'subreg' are *not* interchangeable with indices.
+		 */
 		subreg = &chip->sub_reg_offsets[b];
 		for (i = 0; i < subreg->num_regs; i++) {
 			unsigned int offset = subreg->offset[i];
+			unsigned int index = offset / map->reg_stride;
 
 			ret = regmap_read(map, chip->status_base + offset,
-					  &data->status_buf[offset]);
+					  &data->status_buf[index]);
 			if (ret)
 				break;
 		}
@@ -353,43 +336,29 @@ static inline int read_sub_irq_data(struct regmap_irq_chip_data *data,
 	return ret;
 }
 
-static irqreturn_t regmap_irq_thread(int irq, void *d)
+static int read_irq_data(struct regmap_irq_chip_data *data)
 {
-	struct regmap_irq_chip_data *data = d;
 	const struct regmap_irq_chip *chip = data->chip;
 	struct regmap *map = data->map;
 	int ret, i;
-	bool handled = false;
 	u32 reg;
 
-	if (chip->handle_pre_irq)
-		chip->handle_pre_irq(chip->irq_drv_data);
-
-	if (chip->runtime_pm) {
-		ret = pm_runtime_get_sync(map->dev);
-		if (ret < 0) {
-			dev_err(map->dev, "IRQ thread failed to resume: %d\n",
-				ret);
-			goto exit;
-		}
-	}
-
 	/*
 	 * Read only registers with active IRQs if the chip has 'main status
 	 * register'. Else read in the statuses, using a single bulk read if
 	 * possible in order to reduce the I/O overheads.
 	 */
 
-	if (chip->num_main_regs) {
+	if (chip->no_status) {
+		/* no status register so default to all active */
+		memset32(data->status_buf, GENMASK(31, 0), chip->num_regs);
+	} else if (chip->num_main_regs) {
 		unsigned int max_main_bits;
-		unsigned long size;
-
-		size = chip->num_regs * sizeof(unsigned int);
 
 		max_main_bits = (chip->num_main_status_bits) ?
 				 chip->num_main_status_bits : chip->num_regs;
 		/* Clear the status buf as we don't read all status regs */
-		memset(data->status_buf, 0, size);
+		memset32(data->status_buf, 0, chip->num_regs);
 
 		/* We could support bulk read for main status registers
 		 * but I don't expect to see devices with really many main
@@ -397,15 +366,11 @@ static irqreturn_t regmap_irq_thread(int irq, void *d)
 		 * sake of simplicity. and add bulk reads only if needed
 		 */
 		for (i = 0; i < chip->num_main_regs; i++) {
-			ret = regmap_read(map, chip->main_status +
-				  (i * map->reg_stride
-				   * data->irq_reg_stride),
-				  &data->main_status_buf[i]);
+			reg = data->get_irq_reg(data, chip->main_status, i);
+			ret = regmap_read(map, reg, &data->main_status_buf[i]);
 			if (ret) {
-				dev_err(map->dev,
-					"Failed to read IRQ status %d\n",
-					ret);
-				goto exit;
+				dev_err(map->dev, "Failed to read IRQ status %d\n", ret);
+				return ret;
 			}
 		}
 
@@ -421,16 +386,13 @@ static irqreturn_t regmap_irq_thread(int irq, void *d)
 				ret = read_sub_irq_data(data, b);
 
 				if (ret != 0) {
-					dev_err(map->dev,
-						"Failed to read IRQ status %d\n",
-						ret);
-					goto exit;
+					dev_err(map->dev, "Failed to read IRQ status %d\n", ret);
+					return ret;
 				}
 			}
 
 		}
-	} else if (!map->use_single_read && map->reg_stride == 1 &&
-		   data->irq_reg_stride == 1) {
+	} else if (regmap_irq_can_bulk_read_status(data)) {
 
 		u8 *buf8 = data->status_reg_buf;
 		u16 *buf16 = data->status_reg_buf;
@@ -442,9 +404,8 @@ static irqreturn_t regmap_irq_thread(int irq, void *d)
 				       data->status_reg_buf,
 				       chip->num_regs);
 		if (ret != 0) {
-			dev_err(map->dev, "Failed to read IRQ status: %d\n",
-				ret);
-			goto exit;
+			dev_err(map->dev, "Failed to read IRQ status: %d\n", ret);
+			return ret;
 		}
 
 		for (i = 0; i < data->chip->num_regs; i++) {
@@ -460,29 +421,66 @@ static irqreturn_t regmap_irq_thread(int irq, void *d)
 				break;
 			default:
 				BUG();
-				goto exit;
+				return -EIO;
 			}
 		}
 
 	} else {
 		for (i = 0; i < data->chip->num_regs; i++) {
-			ret = regmap_read(map, chip->status_base +
-					  (i * map->reg_stride
-					   * data->irq_reg_stride),
-					  &data->status_buf[i]);
+			unsigned int reg = data->get_irq_reg(data,
+					data->chip->status_base, i);
+			ret = regmap_read(map, reg, &data->status_buf[i]);
 
 			if (ret != 0) {
-				dev_err(map->dev,
-					"Failed to read IRQ status: %d\n",
-					ret);
-				goto exit;
+				dev_err(map->dev, "Failed to read IRQ status: %d\n", ret);
+				return ret;
 			}
 		}
 	}
 
+	if (chip->status_invert)
+		for (i = 0; i < data->chip->num_regs; i++)
+			data->status_buf[i] = ~data->status_buf[i];
+
+	return 0;
+}
+
+static irqreturn_t regmap_irq_thread(int irq, void *d)
+{
+	struct regmap_irq_chip_data *data = d;
+	const struct regmap_irq_chip *chip = data->chip;
+	struct regmap *map = data->map;
+	int ret, i;
+	bool handled = false;
+	u32 reg;
+
+	if (chip->handle_pre_irq)
+		chip->handle_pre_irq(chip->irq_drv_data);
+
+	if (chip->runtime_pm) {
+		ret = pm_runtime_get_sync(map->dev);
+		if (ret < 0) {
+			dev_err(map->dev, "IRQ thread failed to resume: %d\n", ret);
+			goto exit;
+		}
+	}
+
+	ret = read_irq_data(data);
+	if (ret < 0)
+		goto exit;
+
+	if (chip->status_is_level) {
+		for (i = 0; i < data->chip->num_regs; i++) {
+			unsigned int val = data->status_buf[i];
+
+			data->status_buf[i] ^= data->prev_status_buf[i];
+			data->prev_status_buf[i] = val;
+		}
+	}
+
 	/*
 	 * Ignore masked IRQs and ack if we need to; we ack early so
-	 * there is no race between handling and acknowleding the
+	 * there is no race between handling and acknowledging the
 	 * interrupt.  We assume that typically few of the interrupts
 	 * will fire simultaneously so don't worry about overhead from
 	 * doing a write per register.
@@ -491,9 +489,20 @@ static irqreturn_t regmap_irq_thread(int irq, void *d)
 		data->status_buf[i] &= ~data->mask_buf[i];
 
 		if (data->status_buf[i] && (chip->ack_base || chip->use_ack)) {
-			reg = chip->ack_base +
-				(i * map->reg_stride * data->irq_reg_stride);
-			ret = regmap_write(map, reg, data->status_buf[i]);
+			reg = data->get_irq_reg(data, data->chip->ack_base, i);
+
+			if (chip->ack_invert)
+				ret = regmap_write(map, reg,
+						~data->status_buf[i]);
+			else
+				ret = regmap_write(map, reg,
+						data->status_buf[i]);
+			if (chip->clear_ack) {
+				if (chip->ack_invert && !ret)
+					ret = regmap_write(map, reg, UINT_MAX);
+				else if (!ret)
+					ret = regmap_write(map, reg, 0);
+			}
 			if (ret != 0)
 				dev_err(map->dev, "Failed to ack 0x%x: %d\n",
 					reg, ret);
@@ -509,24 +518,28 @@ static irqreturn_t regmap_irq_thread(int irq, void *d)
 	}
 
 exit:
-	if (chip->runtime_pm)
-		pm_runtime_put(map->dev);
-
 	if (chip->handle_post_irq)
 		chip->handle_post_irq(chip->irq_drv_data);
 
+	if (chip->runtime_pm)
+		pm_runtime_put(map->dev);
+
 	if (handled)
 		return IRQ_HANDLED;
 	else
 		return IRQ_NONE;
 }
 
+static struct lock_class_key regmap_irq_lock_class;
+static struct lock_class_key regmap_irq_request_class;
+
 static int regmap_irq_map(struct irq_domain *h, unsigned int virq,
 			  irq_hw_number_t hw)
 {
 	struct regmap_irq_chip_data *data = h->host_data;
 
 	irq_set_chip_data(virq, data);
+	irq_set_lockdep_class(virq, &regmap_irq_lock_class, &regmap_irq_request_class);
 	irq_set_chip(virq, &data->irq_chip);
 	irq_set_nested_thread(virq, 1);
 	irq_set_parent(virq, data->irq);
@@ -541,8 +554,108 @@ static const struct irq_domain_ops regmap_domain_ops = {
 };
 
 /**
- * regmap_add_irq_chip() - Use standard regmap IRQ controller handling
+ * regmap_irq_get_irq_reg_linear() - Linear IRQ register mapping callback.
+ * @data: Data for the &struct regmap_irq_chip
+ * @base: Base register
+ * @index: Register index
  *
+ * Returns the register address corresponding to the given @base and @index
+ * by the formula ``base + index * regmap_stride * irq_reg_stride``.
+ */
+unsigned int regmap_irq_get_irq_reg_linear(struct regmap_irq_chip_data *data,
+					   unsigned int base, int index)
+{
+	struct regmap *map = data->map;
+
+	return base + index * map->reg_stride * data->irq_reg_stride;
+}
+EXPORT_SYMBOL_GPL(regmap_irq_get_irq_reg_linear);
+
+/**
+ * regmap_irq_set_type_config_simple() - Simple IRQ type configuration callback.
+ * @buf: Buffer containing configuration register values, this is a 2D array of
+ *       `num_config_bases` rows, each of `num_config_regs` elements.
+ * @type: The requested IRQ type.
+ * @irq_data: The IRQ being configured.
+ * @idx: Index of the irq's config registers within each array `buf[i]`
+ * @irq_drv_data: Driver specific IRQ data
+ *
+ * This is a &struct regmap_irq_chip->set_type_config callback suitable for
+ * chips with one config register. Register values are updated according to
+ * the &struct regmap_irq_type data associated with an IRQ.
+ */
+int regmap_irq_set_type_config_simple(unsigned int **buf, unsigned int type,
+				      const struct regmap_irq *irq_data,
+				      int idx, void *irq_drv_data)
+{
+	const struct regmap_irq_type *t = &irq_data->type;
+
+	if (t->type_reg_mask)
+		buf[0][idx] &= ~t->type_reg_mask;
+	else
+		buf[0][idx] &= ~(t->type_falling_val |
+				 t->type_rising_val |
+				 t->type_level_low_val |
+				 t->type_level_high_val);
+
+	switch (type) {
+	case IRQ_TYPE_EDGE_FALLING:
+		buf[0][idx] |= t->type_falling_val;
+		break;
+
+	case IRQ_TYPE_EDGE_RISING:
+		buf[0][idx] |= t->type_rising_val;
+		break;
+
+	case IRQ_TYPE_EDGE_BOTH:
+		buf[0][idx] |= (t->type_falling_val |
+				t->type_rising_val);
+		break;
+
+	case IRQ_TYPE_LEVEL_HIGH:
+		buf[0][idx] |= t->type_level_high_val;
+		break;
+
+	case IRQ_TYPE_LEVEL_LOW:
+		buf[0][idx] |= t->type_level_low_val;
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(regmap_irq_set_type_config_simple);
+
+static int regmap_irq_create_domain(struct fwnode_handle *fwnode, int irq_base,
+				    const struct regmap_irq_chip *chip,
+				    struct regmap_irq_chip_data *d)
+{
+	struct irq_domain_info info = {
+		.fwnode = fwnode,
+		.size = chip->num_irqs,
+		.hwirq_max = chip->num_irqs,
+		.virq_base = irq_base,
+		.ops = &regmap_domain_ops,
+		.host_data = d,
+		.name_suffix = chip->domain_suffix,
+	};
+
+	d->domain = irq_domain_instantiate(&info);
+	if (IS_ERR(d->domain)) {
+		dev_err(d->map->dev, "Failed to create IRQ domain\n");
+		return PTR_ERR(d->domain);
+	}
+
+	return 0;
+}
+
+
+/**
+ * regmap_add_irq_chip_fwnode() - Use standard regmap IRQ controller handling
+ *
+ * @fwnode: The firmware node where the IRQ domain should be added to.
  * @map: The regmap for the device.
  * @irq: The IRQ the device uses to signal interrupts.
  * @irq_flags: The IRQF_ flags to use for the primary interrupt.
@@ -556,16 +669,16 @@ static const struct irq_domain_ops regmap_domain_ops = {
  * register cache.  The chip driver is responsible for restoring the
  * register values used by the IRQ controller over suspend and resume.
  */
-int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
-			int irq_base, const struct regmap_irq_chip *chip,
-			struct regmap_irq_chip_data **data)
+int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode,
+			       struct regmap *map, int irq,
+			       int irq_flags, int irq_base,
+			       const struct regmap_irq_chip *chip,
+			       struct regmap_irq_chip_data **data)
 {
 	struct regmap_irq_chip_data *d;
 	int i;
 	int ret = -ENOMEM;
-	int num_type_reg;
 	u32 reg;
-	u32 unmask_offset;
 
 	if (chip->num_regs <= 0)
 		return -EINVAL;
@@ -573,6 +686,9 @@ int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
 	if (chip->clear_on_unmask && (chip->ack_base || chip->use_ack))
 		return -EINVAL;
 
+	if (chip->mask_base && chip->unmask_base && !chip->mask_unmask_non_inverted)
+		return -EINVAL;
+
 	for (i = 0; i < chip->num_irqs; i++) {
 		if (chip->irqs[i].reg_offset % map->reg_stride)
 			return -EINVAL;
@@ -596,48 +712,71 @@ int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
 
 	if (chip->num_main_regs) {
 		d->main_status_buf = kcalloc(chip->num_main_regs,
-					     sizeof(unsigned int),
+					     sizeof(*d->main_status_buf),
 					     GFP_KERNEL);
 
 		if (!d->main_status_buf)
 			goto err_alloc;
 	}
 
-	d->status_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
+	d->status_buf = kcalloc(chip->num_regs, sizeof(*d->status_buf),
 				GFP_KERNEL);
 	if (!d->status_buf)
 		goto err_alloc;
 
-	d->mask_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
+	if (chip->status_is_level) {
+		d->prev_status_buf = kcalloc(chip->num_regs, sizeof(*d->prev_status_buf),
+					     GFP_KERNEL);
+		if (!d->prev_status_buf)
+			goto err_alloc;
+	}
+
+	d->mask_buf = kcalloc(chip->num_regs, sizeof(*d->mask_buf),
 			      GFP_KERNEL);
 	if (!d->mask_buf)
 		goto err_alloc;
 
-	d->mask_buf_def = kcalloc(chip->num_regs, sizeof(unsigned int),
+	d->mask_buf_def = kcalloc(chip->num_regs, sizeof(*d->mask_buf_def),
 				  GFP_KERNEL);
 	if (!d->mask_buf_def)
 		goto err_alloc;
 
 	if (chip->wake_base) {
-		d->wake_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
+		d->wake_buf = kcalloc(chip->num_regs, sizeof(*d->wake_buf),
 				      GFP_KERNEL);
 		if (!d->wake_buf)
 			goto err_alloc;
 	}
 
-	num_type_reg = chip->type_in_mask ? chip->num_regs : chip->num_type_reg;
-	if (num_type_reg) {
-		d->type_buf_def = kcalloc(num_type_reg,
-					  sizeof(unsigned int), GFP_KERNEL);
+	if (chip->type_in_mask) {
+		d->type_buf_def = kcalloc(chip->num_regs,
+					  sizeof(*d->type_buf_def), GFP_KERNEL);
 		if (!d->type_buf_def)
 			goto err_alloc;
 
-		d->type_buf = kcalloc(num_type_reg, sizeof(unsigned int),
-				      GFP_KERNEL);
+		d->type_buf = kcalloc(chip->num_regs, sizeof(*d->type_buf), GFP_KERNEL);
 		if (!d->type_buf)
 			goto err_alloc;
 	}
 
+	if (chip->num_config_bases && chip->num_config_regs) {
+		/*
+		 * Create config_buf[num_config_bases][num_config_regs]
+		 */
+		d->config_buf = kcalloc(chip->num_config_bases,
+					sizeof(*d->config_buf), GFP_KERNEL);
+		if (!d->config_buf)
+			goto err_alloc;
+
+		for (i = 0; i < chip->num_config_bases; i++) {
+			d->config_buf[i] = kcalloc(chip->num_config_regs,
+						   sizeof(**d->config_buf),
+						   GFP_KERNEL);
+			if (!d->config_buf[i])
+				goto err_alloc;
+		}
+	}
+
 	d->irq_chip = regmap_irq_chip;
 	d->irq_chip.name = chip->name;
 	d->irq = irq;
@@ -650,13 +789,12 @@ int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
 	else
 		d->irq_reg_stride = 1;
 
-	if (chip->type_reg_stride)
-		d->type_reg_stride = chip->type_reg_stride;
+	if (chip->get_irq_reg)
+		d->get_irq_reg = chip->get_irq_reg;
 	else
-		d->type_reg_stride = 1;
+		d->get_irq_reg = regmap_irq_get_irq_reg_linear;
 
-	if (!map->use_single_read && map->reg_stride == 1 &&
-	    d->irq_reg_stride == 1) {
+	if (regmap_irq_can_bulk_read_status(d)) {
 		d->status_reg_buf = kmalloc_array(chip->num_regs,
 						  map->format.val_bytes,
 						  GFP_KERNEL);
@@ -664,7 +802,13 @@ int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
 			goto err_alloc;
 	}
 
-	mutex_init(&d->lock);
+	/*
+	 * If one regmap-irq is the parent of another then we'll try
+	 * to lock the child with the parent locked, use an explicit
+	 * lock_key so lockdep can figure out what's going on.
+	 */
+	lockdep_register_key(&d->lock_key);
+	mutex_init_with_key(&d->lock, &d->lock_key);
 
 	for (i = 0; i < chip->num_irqs; i++)
 		d->mask_buf_def[chip->irqs[i].reg_offset / map->reg_stride]
@@ -673,56 +817,76 @@ int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
 	/* Mask all the interrupts by default */
 	for (i = 0; i < chip->num_regs; i++) {
 		d->mask_buf[i] = d->mask_buf_def[i];
-		if (!chip->mask_base)
-			continue;
 
-		reg = chip->mask_base +
-			(i * map->reg_stride * d->irq_reg_stride);
-		if (chip->mask_invert)
-			ret = regmap_irq_update_bits(d, reg,
-					 d->mask_buf[i], ~d->mask_buf[i]);
-		else if (d->chip->unmask_base) {
-			unmask_offset = d->chip->unmask_base -
-					d->chip->mask_base;
-			ret = regmap_irq_update_bits(d,
-					reg + unmask_offset,
-					d->mask_buf[i],
-					d->mask_buf[i]);
-		} else
-			ret = regmap_irq_update_bits(d, reg,
-					 d->mask_buf[i], d->mask_buf[i]);
-		if (ret != 0) {
-			dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
-				reg, ret);
-			goto err_alloc;
+		if (chip->handle_mask_sync) {
+			ret = chip->handle_mask_sync(i, d->mask_buf_def[i],
+						     d->mask_buf[i],
+						     chip->irq_drv_data);
+			if (ret)
+				goto err_mutex;
+		}
+
+		if (chip->mask_base && !chip->handle_mask_sync) {
+			reg = d->get_irq_reg(d, chip->mask_base, i);
+			ret = regmap_update_bits(d->map, reg,
+						 d->mask_buf_def[i],
+						 d->mask_buf[i]);
+			if (ret) {
+				dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
+					reg, ret);
+				goto err_mutex;
+			}
+		}
+
+		if (chip->unmask_base && !chip->handle_mask_sync) {
+			reg = d->get_irq_reg(d, chip->unmask_base, i);
+			ret = regmap_update_bits(d->map, reg,
+					d->mask_buf_def[i], ~d->mask_buf[i]);
+			if (ret) {
+				dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
+					reg, ret);
+				goto err_mutex;
+			}
 		}
 
 		if (!chip->init_ack_masked)
 			continue;
 
 		/* Ack masked but set interrupts */
-		reg = chip->status_base +
-			(i * map->reg_stride * d->irq_reg_stride);
-		ret = regmap_read(map, reg, &d->status_buf[i]);
-		if (ret != 0) {
-			dev_err(map->dev, "Failed to read IRQ status: %d\n",
-				ret);
-			goto err_alloc;
+		if (d->chip->no_status) {
+			/* no status register so default to all active */
+			d->status_buf[i] = UINT_MAX;
+		} else {
+			reg = d->get_irq_reg(d, d->chip->status_base, i);
+			ret = regmap_read(map, reg, &d->status_buf[i]);
+			if (ret != 0) {
+				dev_err(map->dev, "Failed to read IRQ status: %d\n",
+					ret);
+				goto err_mutex;
+			}
 		}
 
+		if (chip->status_invert)
+			d->status_buf[i] = ~d->status_buf[i];
+
 		if (d->status_buf[i] && (chip->ack_base || chip->use_ack)) {
-			reg = chip->ack_base +
-				(i * map->reg_stride * d->irq_reg_stride);
+			reg = d->get_irq_reg(d, d->chip->ack_base, i);
 			if (chip->ack_invert)
 				ret = regmap_write(map, reg,
 					~(d->status_buf[i] & d->mask_buf[i]));
 			else
 				ret = regmap_write(map, reg,
 					d->status_buf[i] & d->mask_buf[i]);
+			if (chip->clear_ack) {
+				if (chip->ack_invert && !ret)
+					ret = regmap_write(map, reg, UINT_MAX);
+				else if (!ret)
+					ret = regmap_write(map, reg, 0);
+			}
 			if (ret != 0) {
 				dev_err(map->dev, "Failed to ack 0x%x: %d\n",
 					reg, ret);
-				goto err_alloc;
+				goto err_mutex;
 			}
 		}
 	}
@@ -731,56 +895,37 @@ int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
 	if (d->wake_buf) {
 		for (i = 0; i < chip->num_regs; i++) {
 			d->wake_buf[i] = d->mask_buf_def[i];
-			reg = chip->wake_base +
-				(i * map->reg_stride * d->irq_reg_stride);
+			reg = d->get_irq_reg(d, d->chip->wake_base, i);
 
 			if (chip->wake_invert)
-				ret = regmap_irq_update_bits(d, reg,
+				ret = regmap_update_bits(d->map, reg,
 							 d->mask_buf_def[i],
 							 0);
 			else
-				ret = regmap_irq_update_bits(d, reg,
+				ret = regmap_update_bits(d->map, reg,
 							 d->mask_buf_def[i],
 							 d->wake_buf[i]);
 			if (ret != 0) {
 				dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
 					reg, ret);
-				goto err_alloc;
+				goto err_mutex;
 			}
 		}
 	}
 
-	if (chip->num_type_reg && !chip->type_in_mask) {
-		for (i = 0; i < chip->num_type_reg; ++i) {
-			reg = chip->type_base +
-				(i * map->reg_stride * d->type_reg_stride);
-
-			ret = regmap_read(map, reg, &d->type_buf_def[i]);
-
-			if (d->chip->type_invert)
-				d->type_buf_def[i] = ~d->type_buf_def[i];
+	/* Store current levels */
+	if (chip->status_is_level) {
+		ret = read_irq_data(d);
+		if (ret < 0)
+			goto err_mutex;
 
-			if (ret) {
-				dev_err(map->dev, "Failed to get type defaults at 0x%x: %d\n",
-					reg, ret);
-				goto err_alloc;
-			}
-		}
+		memcpy(d->prev_status_buf, d->status_buf,
+		       array_size(d->chip->num_regs, sizeof(d->prev_status_buf[0])));
 	}
 
-	if (irq_base)
-		d->domain = irq_domain_add_legacy(map->dev->of_node,
-						  chip->num_irqs, irq_base, 0,
-						  &regmap_domain_ops, d);
-	else
-		d->domain = irq_domain_add_linear(map->dev->of_node,
-						  chip->num_irqs,
-						  &regmap_domain_ops, d);
-	if (!d->domain) {
-		dev_err(map->dev, "Failed to create IRQ domain\n");
-		ret = -ENOMEM;
-		goto err_alloc;
-	}
+	ret = regmap_irq_create_domain(fwnode, irq_base, chip, d);
+	if (ret)
+		goto err_mutex;
 
 	ret = request_threaded_irq(irq, NULL, regmap_irq_thread,
 				   irq_flags | IRQF_ONESHOT,
@@ -797,17 +942,51 @@ int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
 
 err_domain:
 	/* Should really dispose of the domain but... */
+err_mutex:
+	mutex_destroy(&d->lock);
+	lockdep_unregister_key(&d->lock_key);
 err_alloc:
 	kfree(d->type_buf);
 	kfree(d->type_buf_def);
 	kfree(d->wake_buf);
 	kfree(d->mask_buf_def);
 	kfree(d->mask_buf);
+	kfree(d->main_status_buf);
 	kfree(d->status_buf);
+	kfree(d->prev_status_buf);
 	kfree(d->status_reg_buf);
+	if (d->config_buf) {
+		for (i = 0; i < chip->num_config_bases; i++)
+			kfree(d->config_buf[i]);
+		kfree(d->config_buf);
+	}
 	kfree(d);
 	return ret;
 }
+EXPORT_SYMBOL_GPL(regmap_add_irq_chip_fwnode);
+
+/**
+ * regmap_add_irq_chip() - Use standard regmap IRQ controller handling
+ *
+ * @map: The regmap for the device.
+ * @irq: The IRQ the device uses to signal interrupts.
+ * @irq_flags: The IRQF_ flags to use for the primary interrupt.
+ * @irq_base: Allocate at specific IRQ number if irq_base > 0.
+ * @chip: Configuration for the interrupt controller.
+ * @data: Runtime data structure for the controller, allocated on success.
+ *
+ * Returns 0 on success or an errno on failure.
+ *
+ * This is the same as regmap_add_irq_chip_fwnode, except that the firmware
+ * node of the regmap is used.
+ */
+int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
+			int irq_base, const struct regmap_irq_chip *chip,
+			struct regmap_irq_chip_data **data)
+{
+	return regmap_add_irq_chip_fwnode(dev_fwnode(map->dev), map, irq,
+					  irq_flags, irq_base, chip, data);
+}
 EXPORT_SYMBOL_GPL(regmap_add_irq_chip);
 
 /**
@@ -821,7 +1000,7 @@ EXPORT_SYMBOL_GPL(regmap_add_irq_chip);
 void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d)
 {
 	unsigned int virq;
-	int hwirq;
+	int i, hwirq;
 
 	if (!d)
 		return;
@@ -849,8 +1028,17 @@ void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d)
 	kfree(d->wake_buf);
 	kfree(d->mask_buf_def);
 	kfree(d->mask_buf);
+	kfree(d->main_status_buf);
 	kfree(d->status_reg_buf);
 	kfree(d->status_buf);
+	kfree(d->prev_status_buf);
+	if (d->config_buf) {
+		for (i = 0; i < d->chip->num_config_bases; i++)
+			kfree(d->config_buf[i]);
+		kfree(d->config_buf);
+	}
+	mutex_destroy(&d->lock);
+	lockdep_unregister_key(&d->lock_key);
 	kfree(d);
 }
 EXPORT_SYMBOL_GPL(regmap_del_irq_chip);
@@ -875,9 +1063,10 @@ static int devm_regmap_irq_chip_match(struct device *dev, void *res, void *data)
 }
 
 /**
- * devm_regmap_add_irq_chip() - Resource manager regmap_add_irq_chip()
+ * devm_regmap_add_irq_chip_fwnode() - Resource managed regmap_add_irq_chip_fwnode()
  *
  * @dev: The device pointer on which irq_chip belongs to.
+ * @fwnode: The firmware node where the IRQ domain should be added to.
  * @map: The regmap for the device.
  * @irq: The IRQ the device uses to signal interrupts
  * @irq_flags: The IRQF_ flags to use for the primary interrupt.
@@ -890,10 +1079,12 @@ static int devm_regmap_irq_chip_match(struct device *dev, void *res, void *data)
  * The &regmap_irq_chip_data will be automatically released when the device is
  * unbound.
  */
-int devm_regmap_add_irq_chip(struct device *dev, struct regmap *map, int irq,
-			     int irq_flags, int irq_base,
-			     const struct regmap_irq_chip *chip,
-			     struct regmap_irq_chip_data **data)
+int devm_regmap_add_irq_chip_fwnode(struct device *dev,
+				    struct fwnode_handle *fwnode,
+				    struct regmap *map, int irq,
+				    int irq_flags, int irq_base,
+				    const struct regmap_irq_chip *chip,
+				    struct regmap_irq_chip_data **data)
 {
 	struct regmap_irq_chip_data **ptr, *d;
 	int ret;
@@ -903,8 +1094,8 @@ int devm_regmap_add_irq_chip(struct device *dev, struct regmap *map, int irq,
 	if (!ptr)
 		return -ENOMEM;
 
-	ret = regmap_add_irq_chip(map, irq, irq_flags, irq_base,
-				  chip, &d);
+	ret = regmap_add_irq_chip_fwnode(fwnode, map, irq, irq_flags, irq_base,
+					 chip, &d);
 	if (ret < 0) {
 		devres_free(ptr);
 		return ret;
@@ -915,12 +1106,39 @@ int devm_regmap_add_irq_chip(struct device *dev, struct regmap *map, int irq,
 	*data = d;
 	return 0;
 }
+EXPORT_SYMBOL_GPL(devm_regmap_add_irq_chip_fwnode);
+
+/**
+ * devm_regmap_add_irq_chip() - Resource managed regmap_add_irq_chip()
+ *
+ * @dev: The device pointer on which irq_chip belongs to.
+ * @map: The regmap for the device.
+ * @irq: The IRQ the device uses to signal interrupts
+ * @irq_flags: The IRQF_ flags to use for the primary interrupt.
+ * @irq_base: Allocate at specific IRQ number if irq_base > 0.
+ * @chip: Configuration for the interrupt controller.
+ * @data: Runtime data structure for the controller, allocated on success
+ *
+ * Returns 0 on success or an errno on failure.
+ *
+ * The &regmap_irq_chip_data will be automatically released when the device is
+ * unbound.
+ */
+int devm_regmap_add_irq_chip(struct device *dev, struct regmap *map, int irq,
+			     int irq_flags, int irq_base,
+			     const struct regmap_irq_chip *chip,
+			     struct regmap_irq_chip_data **data)
+{
+	return devm_regmap_add_irq_chip_fwnode(dev, dev_fwnode(map->dev), map,
+					       irq, irq_flags, irq_base, chip,
+					       data);
+}
 EXPORT_SYMBOL_GPL(devm_regmap_add_irq_chip);
 
 /**
  * devm_regmap_del_irq_chip() - Resource managed regmap_del_irq_chip()
  *
- * @dev: Device for which which resource was allocated.
+ * @dev: Device for which the resource was allocated.
  * @irq: Primary IRQ for the device.
  * @data: &regmap_irq_chip_data allocated by regmap_add_irq_chip().
  *
diff --git a/drivers/base/regmap/regmap-kunit.c b/drivers/base/regmap/regmap-kunit.c
new file mode 100644
index 000000000000..f6fc5ed016da
--- /dev/null
+++ b/drivers/base/regmap/regmap-kunit.c
@@ -0,0 +1,2131 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// regmap KUnit tests
+//
+// Copyright 2023 Arm Ltd
+
+#include <kunit/device.h>
+#include <kunit/resource.h>
+#include <kunit/test.h>
+#include "internal.h"
+
+#define BLOCK_TEST_SIZE 12
+
+KUNIT_DEFINE_ACTION_WRAPPER(regmap_exit_action, regmap_exit, struct regmap *);
+
+struct regmap_test_priv {
+	struct device *dev;
+};
+
+struct regmap_test_param {
+	enum regcache_type cache;
+	enum regmap_endian val_endian;
+
+	unsigned int from_reg;
+	bool fast_io;
+};
+
+static void get_changed_bytes(void *orig, void *new, size_t size)
+{
+	char *o = orig;
+	char *n = new;
+	int i;
+
+	get_random_bytes(new, size);
+
+	/*
+	 * This could be nicer and more efficient but we shouldn't
+	 * super care.
+	 */
+	for (i = 0; i < size; i++)
+		while (n[i] == o[i])
+			get_random_bytes(&n[i], 1);
+}
+
+static const struct regmap_config test_regmap_config = {
+	.reg_stride = 1,
+	.val_bits = sizeof(unsigned int) * 8,
+};
+
+static const char *regcache_type_name(enum regcache_type type)
+{
+	switch (type) {
+	case REGCACHE_NONE:
+		return "none";
+	case REGCACHE_FLAT:
+		return "flat";
+	case REGCACHE_FLAT_S:
+		return "flat-sparse";
+	case REGCACHE_RBTREE:
+		return "rbtree";
+	case REGCACHE_MAPLE:
+		return "maple";
+	default:
+		return NULL;
+	}
+}
+
+static const char *regmap_endian_name(enum regmap_endian endian)
+{
+	switch (endian) {
+	case REGMAP_ENDIAN_BIG:
+		return "big";
+	case REGMAP_ENDIAN_LITTLE:
+		return "little";
+	case REGMAP_ENDIAN_DEFAULT:
+		return "default";
+	case REGMAP_ENDIAN_NATIVE:
+		return "native";
+	default:
+		return NULL;
+	}
+}
+
+static void param_to_desc(const struct regmap_test_param *param, char *desc)
+{
+	snprintf(desc, KUNIT_PARAM_DESC_SIZE, "%s-%s%s @%#x",
+		 regcache_type_name(param->cache),
+		 regmap_endian_name(param->val_endian),
+		 param->fast_io ? " fast I/O" : "",
+		 param->from_reg);
+}
+
+static const struct regmap_test_param regcache_types_list[] = {
+	{ .cache = REGCACHE_NONE },
+	{ .cache = REGCACHE_NONE, .fast_io = true },
+	{ .cache = REGCACHE_FLAT },
+	{ .cache = REGCACHE_FLAT, .fast_io = true },
+	{ .cache = REGCACHE_FLAT_S },
+	{ .cache = REGCACHE_FLAT_S, .fast_io = true },
+	{ .cache = REGCACHE_RBTREE },
+	{ .cache = REGCACHE_RBTREE, .fast_io = true },
+	{ .cache = REGCACHE_MAPLE },
+	{ .cache = REGCACHE_MAPLE, .fast_io = true },
+};
+
+KUNIT_ARRAY_PARAM(regcache_types, regcache_types_list, param_to_desc);
+
+static const struct regmap_test_param real_cache_types_only_list[] = {
+	{ .cache = REGCACHE_FLAT },
+	{ .cache = REGCACHE_FLAT, .fast_io = true },
+	{ .cache = REGCACHE_FLAT_S },
+	{ .cache = REGCACHE_FLAT_S, .fast_io = true },
+	{ .cache = REGCACHE_RBTREE },
+	{ .cache = REGCACHE_RBTREE, .fast_io = true },
+	{ .cache = REGCACHE_MAPLE },
+	{ .cache = REGCACHE_MAPLE, .fast_io = true },
+};
+
+KUNIT_ARRAY_PARAM(real_cache_types_only, real_cache_types_only_list, param_to_desc);
+
+static const struct regmap_test_param real_cache_types_list[] = {
+	{ .cache = REGCACHE_FLAT,   .from_reg = 0 },
+	{ .cache = REGCACHE_FLAT,   .from_reg = 0, .fast_io = true },
+	{ .cache = REGCACHE_FLAT,   .from_reg = 0x2001 },
+	{ .cache = REGCACHE_FLAT,   .from_reg = 0x2002 },
+	{ .cache = REGCACHE_FLAT,   .from_reg = 0x2003 },
+	{ .cache = REGCACHE_FLAT,   .from_reg = 0x2004 },
+	{ .cache = REGCACHE_FLAT_S, .from_reg = 0 },
+	{ .cache = REGCACHE_FLAT_S, .from_reg = 0, .fast_io = true },
+	{ .cache = REGCACHE_FLAT_S, .from_reg = 0x2001 },
+	{ .cache = REGCACHE_FLAT_S, .from_reg = 0x2002 },
+	{ .cache = REGCACHE_FLAT_S, .from_reg = 0x2003 },
+	{ .cache = REGCACHE_FLAT_S, .from_reg = 0x2004 },
+	{ .cache = REGCACHE_RBTREE, .from_reg = 0 },
+	{ .cache = REGCACHE_RBTREE, .from_reg = 0, .fast_io = true },
+	{ .cache = REGCACHE_RBTREE, .from_reg = 0x2001 },
+	{ .cache = REGCACHE_RBTREE, .from_reg = 0x2002 },
+	{ .cache = REGCACHE_RBTREE, .from_reg = 0x2003 },
+	{ .cache = REGCACHE_RBTREE, .from_reg = 0x2004 },
+	{ .cache = REGCACHE_MAPLE,  .from_reg = 0 },
+	{ .cache = REGCACHE_MAPLE,  .from_reg = 0, .fast_io = true },
+	{ .cache = REGCACHE_MAPLE,  .from_reg = 0x2001 },
+	{ .cache = REGCACHE_MAPLE,  .from_reg = 0x2002 },
+	{ .cache = REGCACHE_MAPLE,  .from_reg = 0x2003 },
+	{ .cache = REGCACHE_MAPLE,  .from_reg = 0x2004 },
+};
+
+KUNIT_ARRAY_PARAM(real_cache_types, real_cache_types_list, param_to_desc);
+
+static const struct regmap_test_param sparse_cache_types_list[] = {
+	{ .cache = REGCACHE_FLAT_S, .from_reg = 0 },
+	{ .cache = REGCACHE_FLAT_S, .from_reg = 0, .fast_io = true },
+	{ .cache = REGCACHE_FLAT_S, .from_reg = 0x2001 },
+	{ .cache = REGCACHE_FLAT_S, .from_reg = 0x2002 },
+	{ .cache = REGCACHE_FLAT_S, .from_reg = 0x2003 },
+	{ .cache = REGCACHE_FLAT_S, .from_reg = 0x2004 },
+	{ .cache = REGCACHE_RBTREE, .from_reg = 0 },
+	{ .cache = REGCACHE_RBTREE, .from_reg = 0, .fast_io = true },
+	{ .cache = REGCACHE_RBTREE, .from_reg = 0x2001 },
+	{ .cache = REGCACHE_RBTREE, .from_reg = 0x2002 },
+	{ .cache = REGCACHE_RBTREE, .from_reg = 0x2003 },
+	{ .cache = REGCACHE_RBTREE, .from_reg = 0x2004 },
+	{ .cache = REGCACHE_MAPLE,  .from_reg = 0 },
+	{ .cache = REGCACHE_MAPLE,  .from_reg = 0, .fast_io = true },
+	{ .cache = REGCACHE_MAPLE,  .from_reg = 0x2001 },
+	{ .cache = REGCACHE_MAPLE,  .from_reg = 0x2002 },
+	{ .cache = REGCACHE_MAPLE,  .from_reg = 0x2003 },
+	{ .cache = REGCACHE_MAPLE,  .from_reg = 0x2004 },
+};
+
+KUNIT_ARRAY_PARAM(sparse_cache_types, sparse_cache_types_list, param_to_desc);
+
+static struct regmap *gen_regmap(struct kunit *test,
+				 struct regmap_config *config,
+				 struct regmap_ram_data **data)
+{
+	const struct regmap_test_param *param = test->param_value;
+	struct regmap_test_priv *priv = test->priv;
+	unsigned int *buf;
+	struct regmap *ret = ERR_PTR(-ENOMEM);
+	size_t size;
+	int i, error;
+	struct reg_default *defaults;
+
+	config->cache_type = param->cache;
+	config->fast_io = param->fast_io;
+
+	if (config->max_register == 0) {
+		config->max_register = param->from_reg;
+		if (config->num_reg_defaults)
+			config->max_register += (config->num_reg_defaults - 1) *
+						config->reg_stride;
+		else
+			config->max_register += (BLOCK_TEST_SIZE * config->reg_stride);
+	}
+
+	size = array_size(config->max_register + 1, sizeof(*buf));
+	buf = kmalloc(size, GFP_KERNEL);
+	if (!buf)
+		return ERR_PTR(-ENOMEM);
+
+	get_random_bytes(buf, size);
+
+	*data = kzalloc(sizeof(**data), GFP_KERNEL);
+	if (!(*data))
+		goto out_free;
+	(*data)->vals = buf;
+
+	if (config->num_reg_defaults) {
+		defaults = kunit_kcalloc(test,
+					 config->num_reg_defaults,
+					 sizeof(struct reg_default),
+					 GFP_KERNEL);
+		if (!defaults)
+			goto out_free;
+
+		config->reg_defaults = defaults;
+
+		for (i = 0; i < config->num_reg_defaults; i++) {
+			defaults[i].reg = param->from_reg + (i * config->reg_stride);
+			defaults[i].def = buf[param->from_reg + (i * config->reg_stride)];
+		}
+	}
+
+	ret = regmap_init_ram(priv->dev, config, *data);
+	if (IS_ERR(ret))
+		goto out_free;
+
+	/* This calls regmap_exit() on failure, which frees buf and *data */
+	error = kunit_add_action_or_reset(test, regmap_exit_action, ret);
+	if (error)
+		ret = ERR_PTR(error);
+
+	return ret;
+
+out_free:
+	kfree(buf);
+	kfree(*data);
+
+	return ret;
+}
+
+static bool reg_5_false(struct device *dev, unsigned int reg)
+{
+	struct kunit *test = dev_get_drvdata(dev);
+	const struct regmap_test_param *param = test->param_value;
+
+	return reg != (param->from_reg + 5);
+}
+
+static void basic_read_write(struct kunit *test)
+{
+	struct regmap *map;
+	struct regmap_config config;
+	struct regmap_ram_data *data;
+	unsigned int val, rval;
+
+	config = test_regmap_config;
+
+	map = gen_regmap(test, &config, &data);
+	KUNIT_ASSERT_FALSE(test, IS_ERR(map));
+	if (IS_ERR(map))
+		return;
+
+	get_random_bytes(&val, sizeof(val));
+
+	/* If we write a value to a register we can read it back */
+	KUNIT_EXPECT_EQ(test, 0, regmap_write(map, 0, val));
+	KUNIT_EXPECT_EQ(test, 0, regmap_read(map, 0, &rval));
+	KUNIT_EXPECT_EQ(test, val, rval);
+
+	/* If using a cache the cache satisfied the read */
+	KUNIT_EXPECT_EQ(test, config.cache_type == REGCACHE_NONE, data->read[0]);
+}
+
+static void bulk_write(struct kunit *test)
+{
+	struct regmap *map;
+	struct regmap_config config;
+	struct regmap_ram_data *data;
+	unsigned int val[BLOCK_TEST_SIZE], rval[BLOCK_TEST_SIZE];
+	int i;
+
+	config = test_regmap_config;
+
+	map = gen_regmap(test, &config, &data);
+	KUNIT_ASSERT_FALSE(test, IS_ERR(map));
+	if (IS_ERR(map))
+		return;
+
+	get_random_bytes(&val, sizeof(val));
+
+	/*
+	 * Data written via the bulk API can be read back with single
+	 * reads.
+	 */
+	KUNIT_EXPECT_EQ(test, 0, regmap_bulk_write(map, 0, val,
+						   BLOCK_TEST_SIZE));
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		KUNIT_EXPECT_EQ(test, 0, regmap_read(map, i, &rval[i]));
+
+	KUNIT_EXPECT_MEMEQ(test, val, rval, sizeof(val));
+
+	/* If using a cache the cache satisfied the read */
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		KUNIT_EXPECT_EQ(test, config.cache_type == REGCACHE_NONE, data->read[i]);
+}
+
+static void bulk_read(struct kunit *test)
+{
+	struct regmap *map;
+	struct regmap_config config;
+	struct regmap_ram_data *data;
+	unsigned int val[BLOCK_TEST_SIZE], rval[BLOCK_TEST_SIZE];
+	int i;
+
+	config = test_regmap_config;
+
+	map = gen_regmap(test, &config, &data);
+	KUNIT_ASSERT_FALSE(test, IS_ERR(map));
+	if (IS_ERR(map))
+		return;
+
+	get_random_bytes(&val, sizeof(val));
+
+	/* Data written as single writes can be read via the bulk API */
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		KUNIT_EXPECT_EQ(test, 0, regmap_write(map, i, val[i]));
+	KUNIT_EXPECT_EQ(test, 0, regmap_bulk_read(map, 0, rval,
+						  BLOCK_TEST_SIZE));
+	KUNIT_EXPECT_MEMEQ(test, val, rval, sizeof(val));
+
+	/* If using a cache the cache satisfied the read */
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		KUNIT_EXPECT_EQ(test, config.cache_type == REGCACHE_NONE, data->read[i]);
+}
+
+static void multi_write(struct kunit *test)
+{
+	struct regmap *map;
+	struct regmap_config config;
+	struct regmap_ram_data *data;
+	struct reg_sequence sequence[BLOCK_TEST_SIZE];
+	unsigned int val[BLOCK_TEST_SIZE], rval[BLOCK_TEST_SIZE];
+	int i;
+
+	config = test_regmap_config;
+
+	map = gen_regmap(test, &config, &data);
+	KUNIT_ASSERT_FALSE(test, IS_ERR(map));
+	if (IS_ERR(map))
+		return;
+
+	get_random_bytes(&val, sizeof(val));
+
+	/*
+	 * Data written via the multi API can be read back with single
+	 * reads.
+	 */
+	for (i = 0; i < BLOCK_TEST_SIZE; i++) {
+		sequence[i].reg = i;
+		sequence[i].def = val[i];
+		sequence[i].delay_us = 0;
+	}
+	KUNIT_EXPECT_EQ(test, 0,
+			regmap_multi_reg_write(map, sequence, BLOCK_TEST_SIZE));
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		KUNIT_EXPECT_EQ(test, 0, regmap_read(map, i, &rval[i]));
+
+	KUNIT_EXPECT_MEMEQ(test, val, rval, sizeof(val));
+
+	/* If using a cache the cache satisfied the read */
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		KUNIT_EXPECT_EQ(test, config.cache_type == REGCACHE_NONE, data->read[i]);
+}
+
+static void multi_read(struct kunit *test)
+{
+	struct regmap *map;
+	struct regmap_config config;
+	struct regmap_ram_data *data;
+	unsigned int regs[BLOCK_TEST_SIZE];
+	unsigned int val[BLOCK_TEST_SIZE], rval[BLOCK_TEST_SIZE];
+	int i;
+
+	config = test_regmap_config;
+
+	map = gen_regmap(test, &config, &data);
+	KUNIT_ASSERT_FALSE(test, IS_ERR(map));
+	if (IS_ERR(map))
+		return;
+
+	get_random_bytes(&val, sizeof(val));
+
+	/* Data written as single writes can be read via the multi API */
+	for (i = 0; i < BLOCK_TEST_SIZE; i++) {
+		regs[i] = i;
+		KUNIT_EXPECT_EQ(test, 0, regmap_write(map, i, val[i]));
+	}
+	KUNIT_EXPECT_EQ(test, 0,
+			regmap_multi_reg_read(map, regs, rval, BLOCK_TEST_SIZE));
+	KUNIT_EXPECT_MEMEQ(test, val, rval, sizeof(val));
+
+	/* If using a cache the cache satisfied the read */
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		KUNIT_EXPECT_EQ(test, config.cache_type == REGCACHE_NONE, data->read[i]);
+}
+
+static void read_bypassed(struct kunit *test)
+{
+	const struct regmap_test_param *param = test->param_value;
+	struct regmap *map;
+	struct regmap_config config;
+	struct regmap_ram_data *data;
+	unsigned int val[BLOCK_TEST_SIZE], rval;
+	int i;
+
+	config = test_regmap_config;
+
+	map = gen_regmap(test, &config, &data);
+	KUNIT_ASSERT_FALSE(test, IS_ERR(map));
+	if (IS_ERR(map))
+		return;
+
+	KUNIT_EXPECT_FALSE(test, map->cache_bypass);
+
+	get_random_bytes(&val, sizeof(val));
+
+	/* Write some test values */
+	KUNIT_EXPECT_EQ(test, 0, regmap_bulk_write(map, param->from_reg, val, ARRAY_SIZE(val)));
+
+	regcache_cache_only(map, true);
+
+	/*
+	 * While in cache-only regmap_read_bypassed() should return the register
+	 * value and leave the map in cache-only.
+	 */
+	for (i = 0; i < ARRAY_SIZE(val); i++) {
+		/* Put inverted bits in rval to prove we really read the value */
+		rval = ~val[i];
+		KUNIT_EXPECT_EQ(test, 0, regmap_read(map, param->from_reg + i, &rval));
+		KUNIT_EXPECT_EQ(test, val[i], rval);
+
+		rval = ~val[i];
+		KUNIT_EXPECT_EQ(test, 0, regmap_read_bypassed(map, param->from_reg + i, &rval));
+		KUNIT_EXPECT_EQ(test, val[i], rval);
+		KUNIT_EXPECT_TRUE(test, map->cache_only);
+		KUNIT_EXPECT_FALSE(test, map->cache_bypass);
+	}
+
+	/*
+	 * Change the underlying register values to prove it is returning
+	 * real values not cached values.
+	 */
+	for (i = 0; i < ARRAY_SIZE(val); i++) {
+		val[i] = ~val[i];
+		data->vals[param->from_reg + i] = val[i];
+	}
+
+	for (i = 0; i < ARRAY_SIZE(val); i++) {
+		rval = ~val[i];
+		KUNIT_EXPECT_EQ(test, 0, regmap_read(map, param->from_reg + i, &rval));
+		KUNIT_EXPECT_NE(test, val[i], rval);
+
+		rval = ~val[i];
+		KUNIT_EXPECT_EQ(test, 0, regmap_read_bypassed(map, param->from_reg + i, &rval));
+		KUNIT_EXPECT_EQ(test, val[i], rval);
+		KUNIT_EXPECT_TRUE(test, map->cache_only);
+		KUNIT_EXPECT_FALSE(test, map->cache_bypass);
+	}
+}
+
+static void read_bypassed_volatile(struct kunit *test)
+{
+	const struct regmap_test_param *param = test->param_value;
+	struct regmap *map;
+	struct regmap_config config;
+	struct regmap_ram_data *data;
+	unsigned int val[BLOCK_TEST_SIZE], rval;
+	int i;
+
+	config = test_regmap_config;
+	/* All registers except #5 volatile */
+	config.volatile_reg = reg_5_false;
+
+	map = gen_regmap(test, &config, &data);
+	KUNIT_ASSERT_FALSE(test, IS_ERR(map));
+	if (IS_ERR(map))
+		return;
+
+	KUNIT_EXPECT_FALSE(test, map->cache_bypass);
+
+	get_random_bytes(&val, sizeof(val));
+
+	/* Write some test values */
+	KUNIT_EXPECT_EQ(test, 0, regmap_bulk_write(map, param->from_reg, val, ARRAY_SIZE(val)));
+
+	regcache_cache_only(map, true);
+
+	/*
+	 * While in cache-only regmap_read_bypassed() should return the register
+	 * value and leave the map in cache-only.
+	 */
+	for (i = 0; i < ARRAY_SIZE(val); i++) {
+		/* Register #5 is non-volatile so should read from cache */
+		KUNIT_EXPECT_EQ(test, (i == 5) ? 0 : -EBUSY,
+				regmap_read(map, param->from_reg + i, &rval));
+
+		/* Put inverted bits in rval to prove we really read the value */
+		rval = ~val[i];
+		KUNIT_EXPECT_EQ(test, 0, regmap_read_bypassed(map, param->from_reg + i, &rval));
+		KUNIT_EXPECT_EQ(test, val[i], rval);
+		KUNIT_EXPECT_TRUE(test, map->cache_only);
+		KUNIT_EXPECT_FALSE(test, map->cache_bypass);
+	}
+
+	/*
+	 * Change the underlying register values to prove it is returning
+	 * real values not cached values.
+	 */
+	for (i = 0; i < ARRAY_SIZE(val); i++) {
+		val[i] = ~val[i];
+		data->vals[param->from_reg + i] = val[i];
+	}
+
+	for (i = 0; i < ARRAY_SIZE(val); i++) {
+		if (i == 5)
+			continue;
+
+		rval = ~val[i];
+		KUNIT_EXPECT_EQ(test, 0, regmap_read_bypassed(map, param->from_reg + i, &rval));
+		KUNIT_EXPECT_EQ(test, val[i], rval);
+		KUNIT_EXPECT_TRUE(test, map->cache_only);
+		KUNIT_EXPECT_FALSE(test, map->cache_bypass);
+	}
+}
+
+static void write_readonly(struct kunit *test)
+{
+	struct regmap *map;
+	struct regmap_config config;
+	struct regmap_ram_data *data;
+	unsigned int val;
+	int i;
+
+	config = test_regmap_config;
+	config.num_reg_defaults = BLOCK_TEST_SIZE;
+	config.writeable_reg = reg_5_false;
+
+	map = gen_regmap(test, &config, &data);
+	KUNIT_ASSERT_FALSE(test, IS_ERR(map));
+	if (IS_ERR(map))
+		return;
+
+	get_random_bytes(&val, sizeof(val));
+
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		data->written[i] = false;
+
+	/* Change the value of all registers, readonly should fail */
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		KUNIT_EXPECT_EQ(test, i != 5, regmap_write(map, i, val) == 0);
+
+	/* Did that match what we see on the device? */
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		KUNIT_EXPECT_EQ(test, i != 5, data->written[i]);
+}
+
+static void read_writeonly(struct kunit *test)
+{
+	struct regmap *map;
+	struct regmap_config config;
+	struct regmap_ram_data *data;
+	unsigned int val;
+	int i;
+
+	config = test_regmap_config;
+	config.readable_reg = reg_5_false;
+
+	map = gen_regmap(test, &config, &data);
+	KUNIT_ASSERT_FALSE(test, IS_ERR(map));
+	if (IS_ERR(map))
+		return;
+
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		data->read[i] = false;
+
+	/*
+	 * Try to read all the registers, the writeonly one should
+	 * fail if we aren't using the flat cache.
+	 */
+	for (i = 0; i < BLOCK_TEST_SIZE; i++) {
+		if (config.cache_type != REGCACHE_FLAT) {
+			KUNIT_EXPECT_EQ(test, i != 5,
+					regmap_read(map, i, &val) == 0);
+		} else {
+			KUNIT_EXPECT_EQ(test, 0, regmap_read(map, i, &val));
+		}
+	}
+
+	/* Did we trigger a hardware access? */
+	KUNIT_EXPECT_FALSE(test, data->read[5]);
+}
+
+static void reg_defaults(struct kunit *test)
+{
+	struct regmap *map;
+	struct regmap_config config;
+	struct regmap_ram_data *data;
+	unsigned int rval[BLOCK_TEST_SIZE];
+	int i;
+
+	config = test_regmap_config;
+	config.num_reg_defaults = BLOCK_TEST_SIZE;
+
+	map = gen_regmap(test, &config, &data);
+	KUNIT_ASSERT_FALSE(test, IS_ERR(map));
+	if (IS_ERR(map))
+		return;
+
+	/* Read back the expected default data */
+	KUNIT_EXPECT_EQ(test, 0, regmap_bulk_read(map, 0, rval,
+						  BLOCK_TEST_SIZE));
+	KUNIT_EXPECT_MEMEQ(test, data->vals, rval, sizeof(rval));
+
+	/* The data should have been read from cache if there was one */
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		KUNIT_EXPECT_EQ(test, config.cache_type == REGCACHE_NONE, data->read[i]);
+}
+
+static void reg_defaults_read_dev(struct kunit *test)
+{
+	struct regmap *map;
+	struct regmap_config config;
+	struct regmap_ram_data *data;
+	unsigned int rval[BLOCK_TEST_SIZE];
+	int i;
+
+	config = test_regmap_config;
+	config.num_reg_defaults_raw = BLOCK_TEST_SIZE;
+
+	map = gen_regmap(test, &config, &data);
+	KUNIT_ASSERT_FALSE(test, IS_ERR(map));
+	if (IS_ERR(map))
+		return;
+
+	/* We should have read the cache defaults back from the map */
+	for (i = 0; i < BLOCK_TEST_SIZE; i++) {
+		KUNIT_EXPECT_EQ(test, config.cache_type != REGCACHE_NONE, data->read[i]);
+		data->read[i] = false;
+	}
+
+	/* Read back the expected default data */
+	KUNIT_EXPECT_EQ(test, 0, regmap_bulk_read(map, 0, rval,
+						  BLOCK_TEST_SIZE));
+	KUNIT_EXPECT_MEMEQ(test, data->vals, rval, sizeof(rval));
+
+	/* The data should have been read from cache if there was one */
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		KUNIT_EXPECT_EQ(test, config.cache_type == REGCACHE_NONE, data->read[i]);
+}
+
+static void register_patch(struct kunit *test)
+{
+	struct regmap *map;
+	struct regmap_config config;
+	struct regmap_ram_data *data;
+	struct reg_sequence patch[2];
+	unsigned int rval[BLOCK_TEST_SIZE];
+	int i;
+
+	/* We need defaults so readback works */
+	config = test_regmap_config;
+	config.num_reg_defaults = BLOCK_TEST_SIZE;
+
+	map = gen_regmap(test, &config, &data);
+	KUNIT_ASSERT_FALSE(test, IS_ERR(map));
+	if (IS_ERR(map))
+		return;
+
+	/* Stash the original values */
+	KUNIT_EXPECT_EQ(test, 0, regmap_bulk_read(map, 0, rval,
+						  BLOCK_TEST_SIZE));
+
+	/* Patch a couple of values */
+	patch[0].reg = 2;
+	patch[0].def = rval[2] + 1;
+	patch[0].delay_us = 0;
+	patch[1].reg = 5;
+	patch[1].def = rval[5] + 1;
+	patch[1].delay_us = 0;
+	KUNIT_EXPECT_EQ(test, 0, regmap_register_patch(map, patch,
+						       ARRAY_SIZE(patch)));
+
+	/* Only the patched registers are written */
+	for (i = 0; i < BLOCK_TEST_SIZE; i++) {
+		switch (i) {
+		case 2:
+		case 5:
+			KUNIT_EXPECT_TRUE(test, data->written[i]);
+			KUNIT_EXPECT_EQ(test, data->vals[i], rval[i] + 1);
+			break;
+		default:
+			KUNIT_EXPECT_FALSE(test, data->written[i]);
+			KUNIT_EXPECT_EQ(test, data->vals[i], rval[i]);
+			break;
+		}
+	}
+}
+
+static void stride(struct kunit *test)
+{
+	struct regmap *map;
+	struct regmap_config config;
+	struct regmap_ram_data *data;
+	unsigned int rval;
+	int i;
+
+	config = test_regmap_config;
+	config.reg_stride = 2;
+	config.num_reg_defaults = BLOCK_TEST_SIZE / 2;
+
+	/*
+	 * Allow one extra register so that the read/written arrays
+	 * are sized big enough to include an entry for the odd
+	 * address past the final reg_default register.
+	 */
+	config.max_register = BLOCK_TEST_SIZE;
+
+	map = gen_regmap(test, &config, &data);
+	KUNIT_ASSERT_FALSE(test, IS_ERR(map));
+	if (IS_ERR(map))
+		return;
+
+	/* Only even addresses can be accessed, try both read and write */
+	for (i = 0; i < BLOCK_TEST_SIZE; i++) {
+		data->read[i] = false;
+		data->written[i] = false;
+
+		if (i % 2) {
+			KUNIT_EXPECT_NE(test, 0, regmap_read(map, i, &rval));
+			KUNIT_EXPECT_NE(test, 0, regmap_write(map, i, rval));
+			KUNIT_EXPECT_FALSE(test, data->read[i]);
+			KUNIT_EXPECT_FALSE(test, data->written[i]);
+		} else {
+			KUNIT_EXPECT_EQ(test, 0, regmap_read(map, i, &rval));
+			KUNIT_EXPECT_EQ(test, data->vals[i], rval);
+			KUNIT_EXPECT_EQ(test, config.cache_type == REGCACHE_NONE,
+					data->read[i]);
+
+			KUNIT_EXPECT_EQ(test, 0, regmap_write(map, i, rval));
+			KUNIT_EXPECT_TRUE(test, data->written[i]);
+		}
+	}
+}
+
+static const struct regmap_range_cfg test_range = {
+	.selector_reg = 1,
+	.selector_mask = 0xff,
+
+	.window_start = 4,
+	.window_len = 10,
+
+	.range_min = 20,
+	.range_max = 40,
+};
+
+static bool test_range_window_volatile(struct device *dev, unsigned int reg)
+{
+	if (reg >= test_range.window_start &&
+	    reg <= test_range.window_start + test_range.window_len)
+		return true;
+
+	return false;
+}
+
+static bool test_range_all_volatile(struct device *dev, unsigned int reg)
+{
+	if (test_range_window_volatile(dev, reg))
+		return true;
+
+	if (reg >= test_range.range_min && reg <= test_range.range_max)
+		return true;
+
+	return false;
+}
+
+static void basic_ranges(struct kunit *test)
+{
+	struct regmap *map;
+	struct regmap_config config;
+	struct regmap_ram_data *data;
+	unsigned int val;
+	int i;
+
+	config = test_regmap_config;
+	config.volatile_reg = test_range_all_volatile;
+	config.ranges = &test_range;
+	config.num_ranges = 1;
+	config.max_register = test_range.range_max;
+
+	map = gen_regmap(test, &config, &data);
+	KUNIT_ASSERT_FALSE(test, IS_ERR(map));
+	if (IS_ERR(map))
+		return;
+
+	for (i = test_range.range_min; i < test_range.range_max; i++) {
+		data->read[i] = false;
+		data->written[i] = false;
+	}
+
+	/* Reset the page to a non-zero value to trigger a change */
+	KUNIT_EXPECT_EQ(test, 0, regmap_write(map, test_range.selector_reg,
+					      test_range.range_max));
+
+	/* Check we set the page and use the window for writes */
+	data->written[test_range.selector_reg] = false;
+	data->written[test_range.window_start] = false;
+	KUNIT_EXPECT_EQ(test, 0, regmap_write(map, test_range.range_min, 0));
+	KUNIT_EXPECT_TRUE(test, data->written[test_range.selector_reg]);
+	KUNIT_EXPECT_TRUE(test, data->written[test_range.window_start]);
+
+	data->written[test_range.selector_reg] = false;
+	data->written[test_range.window_start] = false;
+	KUNIT_EXPECT_EQ(test, 0, regmap_write(map,
+					      test_range.range_min +
+					      test_range.window_len,
+					      0));
+	KUNIT_EXPECT_TRUE(test, data->written[test_range.selector_reg]);
+	KUNIT_EXPECT_TRUE(test, data->written[test_range.window_start]);
+
+	/* Same for reads */
+	data->written[test_range.selector_reg] = false;
+	data->read[test_range.window_start] = false;
+	KUNIT_EXPECT_EQ(test, 0, regmap_read(map, test_range.range_min, &val));
+	KUNIT_EXPECT_TRUE(test, data->written[test_range.selector_reg]);
+	KUNIT_EXPECT_TRUE(test, data->read[test_range.window_start]);
+
+	data->written[test_range.selector_reg] = false;
+	data->read[test_range.window_start] = false;
+	KUNIT_EXPECT_EQ(test, 0, regmap_read(map,
+					     test_range.range_min +
+					     test_range.window_len,
+					     &val));
+	KUNIT_EXPECT_TRUE(test, data->written[test_range.selector_reg]);
+	KUNIT_EXPECT_TRUE(test, data->read[test_range.window_start]);
+
+	/* No physical access triggered in the virtual range */
+	for (i = test_range.range_min; i < test_range.range_max; i++) {
+		KUNIT_EXPECT_FALSE(test, data->read[i]);
+		KUNIT_EXPECT_FALSE(test, data->written[i]);
+	}
+}
+
+/* Try to stress dynamic creation of cache data structures */
+static void stress_insert(struct kunit *test)
+{
+	struct regmap *map;
+	struct regmap_config config;
+	struct regmap_ram_data *data;
+	unsigned int rval, *vals;
+	size_t buf_sz;
+	int i;
+
+	config = test_regmap_config;
+	config.max_register = 300;
+
+	map = gen_regmap(test, &config, &data);
+	KUNIT_ASSERT_FALSE(test, IS_ERR(map));
+	if (IS_ERR(map))
+		return;
+
+	buf_sz = array_size(sizeof(*vals), config.max_register);
+	vals = kunit_kmalloc(test, buf_sz, GFP_KERNEL);
+	KUNIT_ASSERT_FALSE(test, vals == NULL);
+
+	get_random_bytes(vals, buf_sz);
+
+	/* Write data into the map/cache in ever decreasing strides */
+	for (i = 0; i < config.max_register; i += 100)
+		KUNIT_EXPECT_EQ(test, 0, regmap_write(map, i, vals[i]));
+	for (i = 0; i < config.max_register; i += 50)
+		KUNIT_EXPECT_EQ(test, 0, regmap_write(map, i, vals[i]));
+	for (i = 0; i < config.max_register; i += 25)
+		KUNIT_EXPECT_EQ(test, 0, regmap_write(map, i, vals[i]));
+	for (i = 0; i < config.max_register; i += 10)
+		KUNIT_EXPECT_EQ(test, 0, regmap_write(map, i, vals[i]));
+	for (i = 0; i < config.max_register; i += 5)
+		KUNIT_EXPECT_EQ(test, 0, regmap_write(map, i, vals[i]));
+	for (i = 0; i < config.max_register; i += 3)
+		KUNIT_EXPECT_EQ(test, 0, regmap_write(map, i, vals[i]));
+	for (i = 0; i < config.max_register; i += 2)
+		KUNIT_EXPECT_EQ(test, 0, regmap_write(map, i, vals[i]));
+	for (i = 0; i < config.max_register; i++)
+		KUNIT_EXPECT_EQ(test, 0, regmap_write(map, i, vals[i]));
+
+	/* Do reads from the cache (if there is one) match? */
+	for (i = 0; i < config.max_register; i ++) {
+		KUNIT_EXPECT_EQ(test, 0, regmap_read(map, i, &rval));
+		KUNIT_EXPECT_EQ(test, rval, vals[i]);
+		KUNIT_EXPECT_EQ(test, config.cache_type == REGCACHE_NONE, data->read[i]);
+	}
+}
+
+static void cache_bypass(struct kunit *test)
+{
+	const struct regmap_test_param *param = test->param_value;
+	struct regmap *map;
+	struct regmap_config config;
+	struct regmap_ram_data *data;
+	unsigned int val, rval;
+
+	config = test_regmap_config;
+
+	map = gen_regmap(test, &config, &data);
+	KUNIT_ASSERT_FALSE(test, IS_ERR(map));
+	if (IS_ERR(map))
+		return;
+
+	get_random_bytes(&val, sizeof(val));
+
+	/* Ensure the cache has a value in it */
+	KUNIT_EXPECT_EQ(test, 0, regmap_write(map, param->from_reg, val));
+
+	/* Bypass then write a different value */
+	regcache_cache_bypass(map, true);
+	KUNIT_EXPECT_EQ(test, 0, regmap_write(map, param->from_reg, val + 1));
+
+	/* Read the bypassed value */
+	KUNIT_EXPECT_EQ(test, 0, regmap_read(map, param->from_reg, &rval));
+	KUNIT_EXPECT_EQ(test, val + 1, rval);
+	KUNIT_EXPECT_EQ(test, data->vals[param->from_reg], rval);
+
+	/* Disable bypass, the cache should still return the original value */
+	regcache_cache_bypass(map, false);
+	KUNIT_EXPECT_EQ(test, 0, regmap_read(map, param->from_reg, &rval));
+	KUNIT_EXPECT_EQ(test, val, rval);
+}
+
+static void cache_sync_marked_dirty(struct kunit *test)
+{
+	const struct regmap_test_param *param = test->param_value;
+	struct regmap *map;
+	struct regmap_config config;
+	struct regmap_ram_data *data;
+	unsigned int val[BLOCK_TEST_SIZE];
+	int i;
+
+	config = test_regmap_config;
+
+	map = gen_regmap(test, &config, &data);
+	KUNIT_ASSERT_FALSE(test, IS_ERR(map));
+	if (IS_ERR(map))
+		return;
+
+	get_random_bytes(&val, sizeof(val));
+
+	/* Put some data into the cache */
+	KUNIT_EXPECT_EQ(test, 0, regmap_bulk_write(map, param->from_reg, val,
+						   BLOCK_TEST_SIZE));
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		data->written[param->from_reg + i] = false;
+
+	/* Trash the data on the device itself then resync */
+	regcache_mark_dirty(map);
+	memset(data->vals, 0, sizeof(val));
+	KUNIT_EXPECT_EQ(test, 0, regcache_sync(map));
+
+	/* Did we just write the correct data out? */
+	KUNIT_EXPECT_MEMEQ(test, &data->vals[param->from_reg], val, sizeof(val));
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		KUNIT_EXPECT_EQ(test, true, data->written[param->from_reg + i]);
+}
+
+static void cache_sync_after_cache_only(struct kunit *test)
+{
+	const struct regmap_test_param *param = test->param_value;
+	struct regmap *map;
+	struct regmap_config config;
+	struct regmap_ram_data *data;
+	unsigned int val[BLOCK_TEST_SIZE];
+	unsigned int val_mask;
+	int i;
+
+	config = test_regmap_config;
+
+	map = gen_regmap(test, &config, &data);
+	KUNIT_ASSERT_FALSE(test, IS_ERR(map));
+	if (IS_ERR(map))
+		return;
+
+	val_mask = GENMASK(config.val_bits - 1, 0);
+	get_random_bytes(&val, sizeof(val));
+
+	/* Put some data into the cache */
+	KUNIT_EXPECT_EQ(test, 0, regmap_bulk_write(map, param->from_reg, val,
+						   BLOCK_TEST_SIZE));
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		data->written[param->from_reg + i] = false;
+
+	/* Set cache-only and change the values */
+	regcache_cache_only(map, true);
+	for (i = 0; i < ARRAY_SIZE(val); ++i)
+		val[i] = ~val[i] & val_mask;
+
+	KUNIT_EXPECT_EQ(test, 0, regmap_bulk_write(map, param->from_reg, val,
+						   BLOCK_TEST_SIZE));
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		KUNIT_EXPECT_FALSE(test, data->written[param->from_reg + i]);
+
+	KUNIT_EXPECT_MEMNEQ(test, &data->vals[param->from_reg], val, sizeof(val));
+
+	/* Exit cache-only and sync the cache without marking hardware registers dirty */
+	regcache_cache_only(map, false);
+
+	KUNIT_EXPECT_EQ(test, 0, regcache_sync(map));
+
+	/* Did we just write the correct data out? */
+	KUNIT_EXPECT_MEMEQ(test, &data->vals[param->from_reg], val, sizeof(val));
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		KUNIT_EXPECT_TRUE(test, data->written[param->from_reg + i]);
+}
+
+static void cache_sync_defaults_marked_dirty(struct kunit *test)
+{
+	const struct regmap_test_param *param = test->param_value;
+	struct regmap *map;
+	struct regmap_config config;
+	struct regmap_ram_data *data;
+	unsigned int val;
+	int i;
+
+	config = test_regmap_config;
+	config.num_reg_defaults = BLOCK_TEST_SIZE;
+
+	map = gen_regmap(test, &config, &data);
+	KUNIT_ASSERT_FALSE(test, IS_ERR(map));
+	if (IS_ERR(map))
+		return;
+
+	get_random_bytes(&val, sizeof(val));
+
+	/* Change the value of one register */
+	KUNIT_EXPECT_EQ(test, 0, regmap_write(map, param->from_reg + 2, val));
+
+	/* Resync */
+	regcache_mark_dirty(map);
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		data->written[param->from_reg + i] = false;
+	KUNIT_EXPECT_EQ(test, 0, regcache_sync(map));
+
+	/* Did we just sync the one register we touched? */
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		KUNIT_EXPECT_EQ(test, i == 2, data->written[param->from_reg + i]);
+
+	/* Rewrite registers back to their defaults */
+	for (i = 0; i < config.num_reg_defaults; ++i)
+		KUNIT_EXPECT_EQ(test, 0, regmap_write(map, config.reg_defaults[i].reg,
+						      config.reg_defaults[i].def));
+
+	/*
+	 * Resync after regcache_mark_dirty() should not write out registers
+	 * that are at default value
+	 */
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		data->written[param->from_reg + i] = false;
+	regcache_mark_dirty(map);
+	KUNIT_EXPECT_EQ(test, 0, regcache_sync(map));
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		KUNIT_EXPECT_FALSE(test, data->written[param->from_reg + i]);
+}
+
+static void cache_sync_default_after_cache_only(struct kunit *test)
+{
+	const struct regmap_test_param *param = test->param_value;
+	struct regmap *map;
+	struct regmap_config config;
+	struct regmap_ram_data *data;
+	unsigned int orig_val;
+	int i;
+
+	config = test_regmap_config;
+	config.num_reg_defaults = BLOCK_TEST_SIZE;
+
+	map = gen_regmap(test, &config, &data);
+	KUNIT_ASSERT_FALSE(test, IS_ERR(map));
+	if (IS_ERR(map))
+		return;
+
+	KUNIT_EXPECT_EQ(test, 0, regmap_read(map, param->from_reg + 2, &orig_val));
+
+	/* Enter cache-only and change the value of one register */
+	regcache_cache_only(map, true);
+	KUNIT_EXPECT_EQ(test, 0, regmap_write(map, param->from_reg + 2, orig_val + 1));
+
+	/* Exit cache-only and resync, should write out the changed register */
+	regcache_cache_only(map, false);
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		data->written[param->from_reg + i] = false;
+	KUNIT_EXPECT_EQ(test, 0, regcache_sync(map));
+
+	/* Was the register written out? */
+	KUNIT_EXPECT_TRUE(test, data->written[param->from_reg + 2]);
+	KUNIT_EXPECT_EQ(test, data->vals[param->from_reg + 2], orig_val + 1);
+
+	/* Enter cache-only and write register back to its default value */
+	regcache_cache_only(map, true);
+	KUNIT_EXPECT_EQ(test, 0, regmap_write(map, param->from_reg + 2, orig_val));
+
+	/* Resync should write out the new value */
+	regcache_cache_only(map, false);
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		data->written[param->from_reg + i] = false;
+
+	KUNIT_EXPECT_EQ(test, 0, regcache_sync(map));
+	KUNIT_EXPECT_TRUE(test, data->written[param->from_reg + 2]);
+	KUNIT_EXPECT_EQ(test, data->vals[param->from_reg + 2], orig_val);
+}
+
+static void cache_sync_readonly(struct kunit *test)
+{
+	const struct regmap_test_param *param = test->param_value;
+	struct regmap *map;
+	struct regmap_config config;
+	struct regmap_ram_data *data;
+	unsigned int val;
+	int i;
+
+	config = test_regmap_config;
+	config.writeable_reg = reg_5_false;
+
+	map = gen_regmap(test, &config, &data);
+	KUNIT_ASSERT_FALSE(test, IS_ERR(map));
+	if (IS_ERR(map))
+		return;
+
+	/* Read all registers to fill the cache */
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		KUNIT_EXPECT_EQ(test, 0, regmap_read(map, param->from_reg + i, &val));
+
+	/* Change the value of all registers, readonly should fail */
+	get_random_bytes(&val, sizeof(val));
+	regcache_cache_only(map, true);
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		KUNIT_EXPECT_EQ(test, i != 5, regmap_write(map, param->from_reg + i, val) == 0);
+	regcache_cache_only(map, false);
+
+	/* Resync */
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		data->written[param->from_reg + i] = false;
+	KUNIT_EXPECT_EQ(test, 0, regcache_sync(map));
+
+	/* Did that match what we see on the device? */
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		KUNIT_EXPECT_EQ(test, i != 5, data->written[param->from_reg + i]);
+}
+
+static void cache_sync_patch(struct kunit *test)
+{
+	const struct regmap_test_param *param = test->param_value;
+	struct regmap *map;
+	struct regmap_config config;
+	struct regmap_ram_data *data;
+	struct reg_sequence patch[2];
+	unsigned int rval[BLOCK_TEST_SIZE], val;
+	int i;
+
+	/* We need defaults so readback works */
+	config = test_regmap_config;
+	config.num_reg_defaults = BLOCK_TEST_SIZE;
+
+	map = gen_regmap(test, &config, &data);
+	KUNIT_ASSERT_FALSE(test, IS_ERR(map));
+	if (IS_ERR(map))
+		return;
+
+	/* Stash the original values */
+	KUNIT_EXPECT_EQ(test, 0, regmap_bulk_read(map, param->from_reg, rval,
+						  BLOCK_TEST_SIZE));
+
+	/* Patch a couple of values */
+	patch[0].reg = param->from_reg + 2;
+	patch[0].def = rval[2] + 1;
+	patch[0].delay_us = 0;
+	patch[1].reg = param->from_reg + 5;
+	patch[1].def = rval[5] + 1;
+	patch[1].delay_us = 0;
+	KUNIT_EXPECT_EQ(test, 0, regmap_register_patch(map, patch,
+						       ARRAY_SIZE(patch)));
+
+	/* Sync the cache */
+	regcache_mark_dirty(map);
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		data->written[param->from_reg + i] = false;
+	KUNIT_EXPECT_EQ(test, 0, regcache_sync(map));
+
+	/* The patch should be on the device but not in the cache */
+	for (i = 0; i < BLOCK_TEST_SIZE; i++) {
+		KUNIT_EXPECT_EQ(test, 0, regmap_read(map, param->from_reg + i, &val));
+		KUNIT_EXPECT_EQ(test, val, rval[i]);
+
+		switch (i) {
+		case 2:
+		case 5:
+			KUNIT_EXPECT_EQ(test, true, data->written[param->from_reg + i]);
+			KUNIT_EXPECT_EQ(test, data->vals[param->from_reg + i], rval[i] + 1);
+			break;
+		default:
+			KUNIT_EXPECT_EQ(test, false, data->written[param->from_reg + i]);
+			KUNIT_EXPECT_EQ(test, data->vals[param->from_reg + i], rval[i]);
+			break;
+		}
+	}
+}
+
+static void cache_drop(struct kunit *test)
+{
+	const struct regmap_test_param *param = test->param_value;
+	struct regmap *map;
+	struct regmap_config config;
+	struct regmap_ram_data *data;
+	unsigned int rval[BLOCK_TEST_SIZE];
+	int i;
+
+	config = test_regmap_config;
+	config.num_reg_defaults = BLOCK_TEST_SIZE;
+
+	map = gen_regmap(test, &config, &data);
+	KUNIT_ASSERT_FALSE(test, IS_ERR(map));
+	if (IS_ERR(map))
+		return;
+
+	/* Ensure the data is read from the cache */
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		data->read[param->from_reg + i] = false;
+	KUNIT_EXPECT_EQ(test, 0, regmap_bulk_read(map, param->from_reg, rval,
+						  BLOCK_TEST_SIZE));
+	for (i = 0; i < BLOCK_TEST_SIZE; i++) {
+		KUNIT_EXPECT_FALSE(test, data->read[param->from_reg + i]);
+		data->read[param->from_reg + i] = false;
+	}
+	KUNIT_EXPECT_MEMEQ(test, &data->vals[param->from_reg], rval, sizeof(rval));
+
+	/* Drop some registers */
+	KUNIT_EXPECT_EQ(test, 0, regcache_drop_region(map, param->from_reg + 3,
+						      param->from_reg + 5));
+
+	/* Reread and check only the dropped registers hit the device. */
+	KUNIT_EXPECT_EQ(test, 0, regmap_bulk_read(map, param->from_reg, rval,
+						  BLOCK_TEST_SIZE));
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		KUNIT_EXPECT_EQ(test, data->read[param->from_reg + i], i >= 3 && i <= 5);
+	KUNIT_EXPECT_MEMEQ(test, &data->vals[param->from_reg], rval, sizeof(rval));
+}
+
+static void cache_drop_with_non_contiguous_ranges(struct kunit *test)
+{
+	const struct regmap_test_param *param = test->param_value;
+	struct regmap *map;
+	struct regmap_config config;
+	struct regmap_ram_data *data;
+	unsigned int val[4][BLOCK_TEST_SIZE];
+	unsigned int reg;
+	const int num_ranges = ARRAY_SIZE(val) * 2;
+	int rangeidx, i;
+
+	static_assert(ARRAY_SIZE(val) == 4);
+
+	config = test_regmap_config;
+	config.max_register = param->from_reg + (num_ranges * BLOCK_TEST_SIZE);
+
+	map = gen_regmap(test, &config, &data);
+	KUNIT_ASSERT_FALSE(test, IS_ERR(map));
+	if (IS_ERR(map))
+		return;
+
+	for (i = 0; i < config.max_register + 1; i++)
+		data->written[i] = false;
+
+	/* Create non-contiguous cache blocks by writing every other range */
+	get_random_bytes(&val, sizeof(val));
+	for (rangeidx = 0; rangeidx < num_ranges; rangeidx += 2) {
+		reg = param->from_reg + (rangeidx * BLOCK_TEST_SIZE);
+		KUNIT_EXPECT_EQ(test, 0, regmap_bulk_write(map, reg,
+							   &val[rangeidx / 2],
+							   BLOCK_TEST_SIZE));
+		KUNIT_EXPECT_MEMEQ(test, &data->vals[reg],
+				   &val[rangeidx / 2], sizeof(val[rangeidx / 2]));
+	}
+
+	/* Check that odd ranges weren't written */
+	for (rangeidx = 1; rangeidx < num_ranges; rangeidx += 2) {
+		reg = param->from_reg + (rangeidx * BLOCK_TEST_SIZE);
+		for (i = 0; i < BLOCK_TEST_SIZE; i++)
+			KUNIT_EXPECT_FALSE(test, data->written[reg + i]);
+	}
+
+	/* Drop range 2 */
+	reg = param->from_reg + (2 * BLOCK_TEST_SIZE);
+	KUNIT_EXPECT_EQ(test, 0, regcache_drop_region(map, reg, reg + BLOCK_TEST_SIZE - 1));
+
+	/* Drop part of range 4 */
+	reg = param->from_reg + (4 * BLOCK_TEST_SIZE);
+	KUNIT_EXPECT_EQ(test, 0, regcache_drop_region(map, reg + 3, reg + 5));
+
+	/* Mark dirty and reset mock registers to 0 */
+	regcache_mark_dirty(map);
+	for (i = 0; i < config.max_register + 1; i++) {
+		data->vals[i] = 0;
+		data->written[i] = false;
+	}
+
+	/* The registers that were dropped from range 4 should now remain at 0 */
+	val[4 / 2][3] = 0;
+	val[4 / 2][4] = 0;
+	val[4 / 2][5] = 0;
+
+	/* Sync and check that the expected register ranges were written */
+	KUNIT_EXPECT_EQ(test, 0, regcache_sync(map));
+
+	/* Check that odd ranges weren't written */
+	for (rangeidx = 1; rangeidx < num_ranges; rangeidx += 2) {
+		reg = param->from_reg + (rangeidx * BLOCK_TEST_SIZE);
+		for (i = 0; i < BLOCK_TEST_SIZE; i++)
+			KUNIT_EXPECT_FALSE(test, data->written[reg + i]);
+	}
+
+	/* Check that even ranges (except 2 and 4) were written */
+	for (rangeidx = 0; rangeidx < num_ranges; rangeidx += 2) {
+		if ((rangeidx == 2) || (rangeidx == 4))
+			continue;
+
+		reg = param->from_reg + (rangeidx * BLOCK_TEST_SIZE);
+		for (i = 0; i < BLOCK_TEST_SIZE; i++)
+			KUNIT_EXPECT_TRUE(test, data->written[reg + i]);
+
+		KUNIT_EXPECT_MEMEQ(test, &data->vals[reg],
+				   &val[rangeidx / 2], sizeof(val[rangeidx / 2]));
+	}
+
+	/* Check that range 2 wasn't written */
+	reg = param->from_reg + (2 * BLOCK_TEST_SIZE);
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		KUNIT_EXPECT_FALSE(test, data->written[reg + i]);
+
+	/* Check that range 4 was partially written */
+	reg = param->from_reg + (4 * BLOCK_TEST_SIZE);
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		KUNIT_EXPECT_EQ(test, data->written[reg + i], i < 3 || i > 5);
+
+	KUNIT_EXPECT_MEMEQ(test, &data->vals[reg], &val[4 / 2], sizeof(val[4 / 2]));
+
+	/* Nothing before param->from_reg should have been written */
+	for (i = 0; i < param->from_reg; i++)
+		KUNIT_EXPECT_FALSE(test, data->written[i]);
+}
+
+static void cache_drop_all_and_sync_marked_dirty(struct kunit *test)
+{
+	const struct regmap_test_param *param = test->param_value;
+	struct regmap *map;
+	struct regmap_config config;
+	struct regmap_ram_data *data;
+	unsigned int rval[BLOCK_TEST_SIZE];
+	int i;
+
+	config = test_regmap_config;
+	config.num_reg_defaults = BLOCK_TEST_SIZE;
+
+	map = gen_regmap(test, &config, &data);
+	KUNIT_ASSERT_FALSE(test, IS_ERR(map));
+	if (IS_ERR(map))
+		return;
+
+	/* Ensure the data is read from the cache */
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		data->read[param->from_reg + i] = false;
+	KUNIT_EXPECT_EQ(test, 0, regmap_bulk_read(map, param->from_reg, rval,
+						  BLOCK_TEST_SIZE));
+	KUNIT_EXPECT_MEMEQ(test, &data->vals[param->from_reg], rval, sizeof(rval));
+
+	/* Change all values in cache from defaults */
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		KUNIT_EXPECT_EQ(test, 0, regmap_write(map, param->from_reg + i, rval[i] + 1));
+
+	/* Drop all registers */
+	KUNIT_EXPECT_EQ(test, 0, regcache_drop_region(map, 0, config.max_register));
+
+	/* Mark dirty and cache sync should not write anything. */
+	regcache_mark_dirty(map);
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		data->written[param->from_reg + i] = false;
+
+	KUNIT_EXPECT_EQ(test, 0, regcache_sync(map));
+	for (i = 0; i <= config.max_register; i++)
+		KUNIT_EXPECT_FALSE(test, data->written[i]);
+}
+
+static void cache_drop_all_and_sync_no_defaults(struct kunit *test)
+{
+	const struct regmap_test_param *param = test->param_value;
+	struct regmap *map;
+	struct regmap_config config;
+	struct regmap_ram_data *data;
+	unsigned int rval[BLOCK_TEST_SIZE];
+	int i;
+
+	config = test_regmap_config;
+
+	map = gen_regmap(test, &config, &data);
+	KUNIT_ASSERT_FALSE(test, IS_ERR(map));
+	if (IS_ERR(map))
+		return;
+
+	/* Ensure the data is read from the cache */
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		data->read[param->from_reg + i] = false;
+	KUNIT_EXPECT_EQ(test, 0, regmap_bulk_read(map, param->from_reg, rval,
+						  BLOCK_TEST_SIZE));
+	KUNIT_EXPECT_MEMEQ(test, &data->vals[param->from_reg], rval, sizeof(rval));
+
+	/* Change all values in cache */
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		KUNIT_EXPECT_EQ(test, 0, regmap_write(map, param->from_reg + i, rval[i] + 1));
+
+	/* Drop all registers */
+	KUNIT_EXPECT_EQ(test, 0, regcache_drop_region(map, 0, config.max_register));
+
+	/*
+	 * Sync cache without marking it dirty. All registers were dropped
+	 * so the cache should not have any entries to write out.
+	 */
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		data->written[param->from_reg + i] = false;
+
+	KUNIT_EXPECT_EQ(test, 0, regcache_sync(map));
+	for (i = 0; i <= config.max_register; i++)
+		KUNIT_EXPECT_FALSE(test, data->written[i]);
+}
+
+static void cache_drop_all_and_sync_has_defaults(struct kunit *test)
+{
+	const struct regmap_test_param *param = test->param_value;
+	struct regmap *map;
+	struct regmap_config config;
+	struct regmap_ram_data *data;
+	unsigned int rval[BLOCK_TEST_SIZE];
+	int i;
+
+	config = test_regmap_config;
+	config.num_reg_defaults = BLOCK_TEST_SIZE;
+
+	map = gen_regmap(test, &config, &data);
+	KUNIT_ASSERT_FALSE(test, IS_ERR(map));
+	if (IS_ERR(map))
+		return;
+
+	/* Ensure the data is read from the cache */
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		data->read[param->from_reg + i] = false;
+	KUNIT_EXPECT_EQ(test, 0, regmap_bulk_read(map, param->from_reg, rval,
+						  BLOCK_TEST_SIZE));
+	KUNIT_EXPECT_MEMEQ(test, &data->vals[param->from_reg], rval, sizeof(rval));
+
+	/* Change all values in cache from defaults */
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		KUNIT_EXPECT_EQ(test, 0, regmap_write(map, param->from_reg + i, rval[i] + 1));
+
+	/* Drop all registers */
+	KUNIT_EXPECT_EQ(test, 0, regcache_drop_region(map, 0, config.max_register));
+
+	/*
+	 * Sync cache without marking it dirty. All registers were dropped
+	 * so the cache should not have any entries to write out.
+	 */
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		data->written[param->from_reg + i] = false;
+
+	KUNIT_EXPECT_EQ(test, 0, regcache_sync(map));
+	for (i = 0; i <= config.max_register; i++)
+		KUNIT_EXPECT_FALSE(test, data->written[i]);
+}
+
+static void cache_present(struct kunit *test)
+{
+	const struct regmap_test_param *param = test->param_value;
+	struct regmap *map;
+	struct regmap_config config;
+	struct regmap_ram_data *data;
+	unsigned int val;
+	int i;
+
+	config = test_regmap_config;
+
+	map = gen_regmap(test, &config, &data);
+	KUNIT_ASSERT_FALSE(test, IS_ERR(map));
+	if (IS_ERR(map))
+		return;
+
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		data->read[param->from_reg + i] = false;
+
+	/* No defaults so no registers cached. */
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		KUNIT_ASSERT_FALSE(test, regcache_reg_cached(map, param->from_reg + i));
+
+	/* We didn't trigger any reads */
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		KUNIT_ASSERT_FALSE(test, data->read[param->from_reg + i]);
+
+	/* Fill the cache */
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		KUNIT_EXPECT_EQ(test, 0, regmap_read(map, param->from_reg + i, &val));
+
+	/* Now everything should be cached */
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		KUNIT_ASSERT_TRUE(test, regcache_reg_cached(map, param->from_reg + i));
+}
+
+static void cache_write_zero(struct kunit *test)
+{
+	const struct regmap_test_param *param = test->param_value;
+	struct regmap *map;
+	struct regmap_config config;
+	struct regmap_ram_data *data;
+	unsigned int val;
+	int i;
+
+	config = test_regmap_config;
+
+	map = gen_regmap(test, &config, &data);
+	KUNIT_ASSERT_FALSE(test, IS_ERR(map));
+	if (IS_ERR(map))
+		return;
+
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		data->read[param->from_reg + i] = false;
+
+	/* No defaults so no registers cached. */
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		KUNIT_ASSERT_FALSE(test, regcache_reg_cached(map, param->from_reg + i));
+
+	/* We didn't trigger any reads */
+	for (i = 0; i < BLOCK_TEST_SIZE; i++)
+		KUNIT_ASSERT_FALSE(test, data->read[param->from_reg + i]);
+
+	/* Write a zero value */
+	KUNIT_EXPECT_EQ(test, 0, regmap_write(map, 1, 0));
+
+	/* Read that zero value back */
+	KUNIT_EXPECT_EQ(test, 0, regmap_read(map, 1, &val));
+	KUNIT_EXPECT_EQ(test, 0, val);
+
+	/* From the cache? */
+	KUNIT_ASSERT_TRUE(test, regcache_reg_cached(map, 1));
+
+	/* Try to throw it away */
+	KUNIT_EXPECT_EQ(test, 0, regcache_drop_region(map, 1, 1));
+	KUNIT_ASSERT_FALSE(test, regcache_reg_cached(map, 1));
+}
+
+/* Check that caching the window register works with sync */
+static void cache_range_window_reg(struct kunit *test)
+{
+	struct regmap *map;
+	struct regmap_config config;
+	struct regmap_ram_data *data;
+	unsigned int val;
+	int i;
+
+	config = test_regmap_config;
+	config.volatile_reg = test_range_window_volatile;
+	config.ranges = &test_range;
+	config.num_ranges = 1;
+	config.max_register = test_range.range_max;
+
+	map = gen_regmap(test, &config, &data);
+	KUNIT_ASSERT_FALSE(test, IS_ERR(map));
+	if (IS_ERR(map))
+		return;
+
+	/* Write new values to the entire range */
+	for (i = test_range.range_min; i <= test_range.range_max; i++)
+		KUNIT_ASSERT_EQ(test, 0, regmap_write(map, i, 0));
+
+	val = data->vals[test_range.selector_reg] & test_range.selector_mask;
+	KUNIT_ASSERT_EQ(test, val, 2);
+
+	/* Write to the first register in the range to reset the page */
+	KUNIT_ASSERT_EQ(test, 0, regmap_write(map, test_range.range_min, 0));
+	val = data->vals[test_range.selector_reg] & test_range.selector_mask;
+	KUNIT_ASSERT_EQ(test, val, 0);
+
+	/* Trigger a cache sync */
+	regcache_mark_dirty(map);
+	KUNIT_ASSERT_EQ(test, 0, regcache_sync(map));
+
+	/* Write to the first register again, the page should be reset */
+	KUNIT_ASSERT_EQ(test, 0, regmap_write(map, test_range.range_min, 0));
+	val = data->vals[test_range.selector_reg] & test_range.selector_mask;
+	KUNIT_ASSERT_EQ(test, val, 0);
+
+	/* Trigger another cache sync */
+	regcache_mark_dirty(map);
+	KUNIT_ASSERT_EQ(test, 0, regcache_sync(map));
+
+	/* Write to the last register again, the page should be reset */
+	KUNIT_ASSERT_EQ(test, 0, regmap_write(map, test_range.range_max, 0));
+	val = data->vals[test_range.selector_reg] & test_range.selector_mask;
+	KUNIT_ASSERT_EQ(test, val, 2);
+}
+
+static const struct regmap_test_param raw_types_list[] = {
+	{ .cache = REGCACHE_NONE,   .val_endian = REGMAP_ENDIAN_LITTLE },
+	{ .cache = REGCACHE_NONE,   .val_endian = REGMAP_ENDIAN_BIG },
+	{ .cache = REGCACHE_FLAT,   .val_endian = REGMAP_ENDIAN_LITTLE },
+	{ .cache = REGCACHE_FLAT,   .val_endian = REGMAP_ENDIAN_BIG },
+	{ .cache = REGCACHE_FLAT_S, .val_endian = REGMAP_ENDIAN_LITTLE },
+	{ .cache = REGCACHE_FLAT_S, .val_endian = REGMAP_ENDIAN_BIG },
+	{ .cache = REGCACHE_RBTREE, .val_endian = REGMAP_ENDIAN_LITTLE },
+	{ .cache = REGCACHE_RBTREE, .val_endian = REGMAP_ENDIAN_BIG },
+	{ .cache = REGCACHE_MAPLE,  .val_endian = REGMAP_ENDIAN_LITTLE },
+	{ .cache = REGCACHE_MAPLE,  .val_endian = REGMAP_ENDIAN_BIG },
+};
+
+KUNIT_ARRAY_PARAM(raw_test_types, raw_types_list, param_to_desc);
+
+static const struct regmap_test_param raw_cache_types_list[] = {
+	{ .cache = REGCACHE_FLAT,   .val_endian = REGMAP_ENDIAN_LITTLE },
+	{ .cache = REGCACHE_FLAT,   .val_endian = REGMAP_ENDIAN_BIG },
+	{ .cache = REGCACHE_FLAT_S, .val_endian = REGMAP_ENDIAN_LITTLE },
+	{ .cache = REGCACHE_FLAT_S, .val_endian = REGMAP_ENDIAN_BIG },
+	{ .cache = REGCACHE_RBTREE, .val_endian = REGMAP_ENDIAN_LITTLE },
+	{ .cache = REGCACHE_RBTREE, .val_endian = REGMAP_ENDIAN_BIG },
+	{ .cache = REGCACHE_MAPLE,  .val_endian = REGMAP_ENDIAN_LITTLE },
+	{ .cache = REGCACHE_MAPLE,  .val_endian = REGMAP_ENDIAN_BIG },
+};
+
+KUNIT_ARRAY_PARAM(raw_test_cache_types, raw_cache_types_list, param_to_desc);
+
+static const struct regmap_config raw_regmap_config = {
+	.max_register = BLOCK_TEST_SIZE,
+
+	.reg_format_endian = REGMAP_ENDIAN_LITTLE,
+	.reg_bits = 16,
+	.val_bits = 16,
+};
+
+static struct regmap *gen_raw_regmap(struct kunit *test,
+				     struct regmap_config *config,
+				     struct regmap_ram_data **data)
+{
+	struct regmap_test_priv *priv = test->priv;
+	const struct regmap_test_param *param = test->param_value;
+	u16 *buf;
+	struct regmap *ret = ERR_PTR(-ENOMEM);
+	int i, error;
+	struct reg_default *defaults;
+	size_t size;
+
+	config->cache_type = param->cache;
+	config->val_format_endian = param->val_endian;
+	config->disable_locking = config->cache_type == REGCACHE_RBTREE ||
+					config->cache_type == REGCACHE_MAPLE;
+
+	size = array_size(config->max_register + 1, BITS_TO_BYTES(config->reg_bits));
+	buf = kmalloc(size, GFP_KERNEL);
+	if (!buf)
+		return ERR_PTR(-ENOMEM);
+
+	get_random_bytes(buf, size);
+
+	*data = kzalloc(sizeof(**data), GFP_KERNEL);
+	if (!(*data))
+		goto out_free;
+	(*data)->vals = (void *)buf;
+
+	config->num_reg_defaults = config->max_register + 1;
+	defaults = kunit_kcalloc(test,
+				 config->num_reg_defaults,
+				 sizeof(struct reg_default),
+				 GFP_KERNEL);
+	if (!defaults)
+		goto out_free;
+	config->reg_defaults = defaults;
+
+	for (i = 0; i < config->num_reg_defaults; i++) {
+		defaults[i].reg = i;
+		switch (param->val_endian) {
+		case REGMAP_ENDIAN_LITTLE:
+			defaults[i].def = le16_to_cpu(buf[i]);
+			break;
+		case REGMAP_ENDIAN_BIG:
+			defaults[i].def = be16_to_cpu(buf[i]);
+			break;
+		default:
+			ret = ERR_PTR(-EINVAL);
+			goto out_free;
+		}
+	}
+
+	/*
+	 * We use the defaults in the tests but they don't make sense
+	 * to the core if there's no cache.
+	 */
+	if (config->cache_type == REGCACHE_NONE)
+		config->num_reg_defaults = 0;
+
+	ret = regmap_init_raw_ram(priv->dev, config, *data);
+	if (IS_ERR(ret))
+		goto out_free;
+
+	/* This calls regmap_exit() on failure, which frees buf and *data */
+	error = kunit_add_action_or_reset(test, regmap_exit_action, ret);
+	if (error)
+		ret = ERR_PTR(error);
+
+	return ret;
+
+out_free:
+	kfree(buf);
+	kfree(*data);
+
+	return ret;
+}
+
+static void raw_read_defaults_single(struct kunit *test)
+{
+	struct regmap *map;
+	struct regmap_config config;
+	struct regmap_ram_data *data;
+	unsigned int rval;
+	int i;
+
+	config = raw_regmap_config;
+
+	map = gen_raw_regmap(test, &config, &data);
+	KUNIT_ASSERT_FALSE(test, IS_ERR(map));
+	if (IS_ERR(map))
+		return;
+
+	/* Check that we can read the defaults via the API */
+	for (i = 0; i < config.max_register + 1; i++) {
+		KUNIT_EXPECT_EQ(test, 0, regmap_read(map, i, &rval));
+		KUNIT_EXPECT_EQ(test, config.reg_defaults[i].def, rval);
+	}
+}
+
+static void raw_read_defaults(struct kunit *test)
+{
+	struct regmap *map;
+	struct regmap_config config;
+	struct regmap_ram_data *data;
+	u16 *rval;
+	u16 def;
+	size_t val_len;
+	int i;
+
+	config = raw_regmap_config;
+
+	map = gen_raw_regmap(test, &config, &data);
+	KUNIT_ASSERT_FALSE(test, IS_ERR(map));
+	if (IS_ERR(map))
+		return;
+
+	val_len = array_size(sizeof(*rval), config.max_register + 1);
+	rval = kunit_kmalloc(test, val_len, GFP_KERNEL);
+	KUNIT_ASSERT_TRUE(test, rval != NULL);
+	if (!rval)
+		return;
+
+	/* Check that we can read the defaults via the API */
+	KUNIT_EXPECT_EQ(test, 0, regmap_raw_read(map, 0, rval, val_len));
+	for (i = 0; i < config.max_register + 1; i++) {
+		def = config.reg_defaults[i].def;
+		if (config.val_format_endian == REGMAP_ENDIAN_BIG) {
+			KUNIT_EXPECT_EQ(test, def, be16_to_cpu((__force __be16)rval[i]));
+		} else {
+			KUNIT_EXPECT_EQ(test, def, le16_to_cpu((__force __le16)rval[i]));
+		}
+	}
+}
+
+static void raw_write_read_single(struct kunit *test)
+{
+	struct regmap *map;
+	struct regmap_config config;
+	struct regmap_ram_data *data;
+	u16 val;
+	unsigned int rval;
+
+	config = raw_regmap_config;
+
+	map = gen_raw_regmap(test, &config, &data);
+	KUNIT_ASSERT_FALSE(test, IS_ERR(map));
+	if (IS_ERR(map))
+		return;
+
+	get_random_bytes(&val, sizeof(val));
+
+	/* If we write a value to a register we can read it back */
+	KUNIT_EXPECT_EQ(test, 0, regmap_write(map, 0, val));
+	KUNIT_EXPECT_EQ(test, 0, regmap_read(map, 0, &rval));
+	KUNIT_EXPECT_EQ(test, val, rval);
+}
+
+static void raw_write(struct kunit *test)
+{
+	struct regmap *map;
+	struct regmap_config config;
+	struct regmap_ram_data *data;
+	u16 *hw_buf;
+	u16 val[2];
+	unsigned int rval;
+	int i;
+
+	config = raw_regmap_config;
+
+	map = gen_raw_regmap(test, &config, &data);
+	KUNIT_ASSERT_FALSE(test, IS_ERR(map));
+	if (IS_ERR(map))
+		return;
+
+	hw_buf = (u16 *)data->vals;
+
+	get_random_bytes(&val, sizeof(val));
+
+	/* Do a raw write */
+	KUNIT_EXPECT_EQ(test, 0, regmap_raw_write(map, 2, val, sizeof(val)));
+
+	/* We should read back the new values, and defaults for the rest */
+	for (i = 0; i < config.max_register + 1; i++) {
+		KUNIT_EXPECT_EQ(test, 0, regmap_read(map, i, &rval));
+
+		switch (i) {
+		case 2:
+		case 3:
+			if (config.val_format_endian == REGMAP_ENDIAN_BIG) {
+				KUNIT_EXPECT_EQ(test, rval,
+						be16_to_cpu((__force __be16)val[i % 2]));
+			} else {
+				KUNIT_EXPECT_EQ(test, rval,
+						le16_to_cpu((__force __le16)val[i % 2]));
+			}
+			break;
+		default:
+			KUNIT_EXPECT_EQ(test, config.reg_defaults[i].def, rval);
+			break;
+		}
+	}
+
+	/* The values should appear in the "hardware" */
+	KUNIT_EXPECT_MEMEQ(test, &hw_buf[2], val, sizeof(val));
+}
+
+static bool reg_zero(struct device *dev, unsigned int reg)
+{
+	return reg == 0;
+}
+
+static bool ram_reg_zero(struct regmap_ram_data *data, unsigned int reg)
+{
+	return reg == 0;
+}
+
+static void raw_noinc_write(struct kunit *test)
+{
+	struct regmap *map;
+	struct regmap_config config;
+	struct regmap_ram_data *data;
+	unsigned int val;
+	u16 val_test, val_last;
+	u16 val_array[BLOCK_TEST_SIZE];
+
+	config = raw_regmap_config;
+	config.volatile_reg = reg_zero;
+	config.writeable_noinc_reg = reg_zero;
+	config.readable_noinc_reg = reg_zero;
+
+	map = gen_raw_regmap(test, &config, &data);
+	KUNIT_ASSERT_FALSE(test, IS_ERR(map));
+	if (IS_ERR(map))
+		return;
+
+	data->noinc_reg = ram_reg_zero;
+
+	get_random_bytes(&val_array, sizeof(val_array));
+
+	if (config.val_format_endian == REGMAP_ENDIAN_BIG) {
+		val_test = be16_to_cpu(val_array[1]) + 100;
+		val_last = be16_to_cpu(val_array[BLOCK_TEST_SIZE - 1]);
+	} else {
+		val_test = le16_to_cpu(val_array[1]) + 100;
+		val_last = le16_to_cpu(val_array[BLOCK_TEST_SIZE - 1]);
+	}
+
+	/* Put some data into the register following the noinc register */
+	KUNIT_EXPECT_EQ(test, 0, regmap_write(map, 1, val_test));
+
+	/* Write some data to the noinc register */
+	KUNIT_EXPECT_EQ(test, 0, regmap_noinc_write(map, 0, val_array,
+						    sizeof(val_array)));
+
+	/* We should read back the last value written */
+	KUNIT_EXPECT_EQ(test, 0, regmap_read(map, 0, &val));
+	KUNIT_ASSERT_EQ(test, val_last, val);
+
+	/* Make sure we didn't touch the register after the noinc register */
+	KUNIT_EXPECT_EQ(test, 0, regmap_read(map, 1, &val));
+	KUNIT_ASSERT_EQ(test, val_test, val);
+}
+
+static void raw_sync(struct kunit *test)
+{
+	struct regmap *map;
+	struct regmap_config config;
+	struct regmap_ram_data *data;
+	u16 val[3];
+	u16 *hw_buf;
+	unsigned int rval;
+	int i;
+
+	config = raw_regmap_config;
+
+	map = gen_raw_regmap(test, &config, &data);
+	KUNIT_ASSERT_FALSE(test, IS_ERR(map));
+	if (IS_ERR(map))
+		return;
+
+	hw_buf = (u16 *)data->vals;
+
+	get_changed_bytes(&hw_buf[2], &val[0], sizeof(val));
+
+	/* Do a regular write and a raw write in cache only mode */
+	regcache_cache_only(map, true);
+	KUNIT_EXPECT_EQ(test, 0, regmap_raw_write(map, 2, val,
+						  sizeof(u16) * 2));
+	KUNIT_EXPECT_EQ(test, 0, regmap_write(map, 4, val[2]));
+
+	/* We should read back the new values, and defaults for the rest */
+	for (i = 0; i < config.max_register + 1; i++) {
+		KUNIT_EXPECT_EQ(test, 0, regmap_read(map, i, &rval));
+
+		switch (i) {
+		case 2:
+		case 3:
+			if (config.val_format_endian == REGMAP_ENDIAN_BIG) {
+				KUNIT_EXPECT_EQ(test, rval,
+						be16_to_cpu((__force __be16)val[i - 2]));
+			} else {
+				KUNIT_EXPECT_EQ(test, rval,
+						le16_to_cpu((__force __le16)val[i - 2]));
+			}
+			break;
+		case 4:
+			KUNIT_EXPECT_EQ(test, rval, val[i - 2]);
+			break;
+		default:
+			KUNIT_EXPECT_EQ(test, config.reg_defaults[i].def, rval);
+			break;
+		}
+	}
+
+	/*
+	 * The value written via _write() was translated by the core,
+	 * translate the original copy for comparison purposes.
+	 */
+	if (config.val_format_endian == REGMAP_ENDIAN_BIG)
+		val[2] = cpu_to_be16(val[2]);
+	else
+		val[2] = cpu_to_le16(val[2]);
+
+	/* The values should not appear in the "hardware" */
+	KUNIT_EXPECT_MEMNEQ(test, &hw_buf[2], &val[0], sizeof(val));
+
+	for (i = 0; i < config.max_register + 1; i++)
+		data->written[i] = false;
+
+	/* Do the sync */
+	regcache_cache_only(map, false);
+	regcache_mark_dirty(map);
+	KUNIT_EXPECT_EQ(test, 0, regcache_sync(map));
+
+	/* The values should now appear in the "hardware" */
+	KUNIT_EXPECT_MEMEQ(test, &hw_buf[2], &val[0], sizeof(val));
+}
+
+static void raw_ranges(struct kunit *test)
+{
+	struct regmap *map;
+	struct regmap_config config;
+	struct regmap_ram_data *data;
+	unsigned int val;
+	int i;
+
+	config = raw_regmap_config;
+	config.volatile_reg = test_range_all_volatile;
+	config.ranges = &test_range;
+	config.num_ranges = 1;
+	config.max_register = test_range.range_max;
+
+	map = gen_raw_regmap(test, &config, &data);
+	KUNIT_ASSERT_FALSE(test, IS_ERR(map));
+	if (IS_ERR(map))
+		return;
+
+	/* Reset the page to a non-zero value to trigger a change */
+	KUNIT_EXPECT_EQ(test, 0, regmap_write(map, test_range.selector_reg,
+					      test_range.range_max));
+
+	/* Check we set the page and use the window for writes */
+	data->written[test_range.selector_reg] = false;
+	data->written[test_range.window_start] = false;
+	KUNIT_EXPECT_EQ(test, 0, regmap_write(map, test_range.range_min, 0));
+	KUNIT_EXPECT_TRUE(test, data->written[test_range.selector_reg]);
+	KUNIT_EXPECT_TRUE(test, data->written[test_range.window_start]);
+
+	data->written[test_range.selector_reg] = false;
+	data->written[test_range.window_start] = false;
+	KUNIT_EXPECT_EQ(test, 0, regmap_write(map,
+					      test_range.range_min +
+					      test_range.window_len,
+					      0));
+	KUNIT_EXPECT_TRUE(test, data->written[test_range.selector_reg]);
+	KUNIT_EXPECT_TRUE(test, data->written[test_range.window_start]);
+
+	/* Same for reads */
+	data->written[test_range.selector_reg] = false;
+	data->read[test_range.window_start] = false;
+	KUNIT_EXPECT_EQ(test, 0, regmap_read(map, test_range.range_min, &val));
+	KUNIT_EXPECT_TRUE(test, data->written[test_range.selector_reg]);
+	KUNIT_EXPECT_TRUE(test, data->read[test_range.window_start]);
+
+	data->written[test_range.selector_reg] = false;
+	data->read[test_range.window_start] = false;
+	KUNIT_EXPECT_EQ(test, 0, regmap_read(map,
+					     test_range.range_min +
+					     test_range.window_len,
+					     &val));
+	KUNIT_EXPECT_TRUE(test, data->written[test_range.selector_reg]);
+	KUNIT_EXPECT_TRUE(test, data->read[test_range.window_start]);
+
+	/* No physical access triggered in the virtual range */
+	for (i = test_range.range_min; i < test_range.range_max; i++) {
+		KUNIT_EXPECT_FALSE(test, data->read[i]);
+		KUNIT_EXPECT_FALSE(test, data->written[i]);
+	}
+}
+
+static struct kunit_case regmap_test_cases[] = {
+	KUNIT_CASE_PARAM(basic_read_write, regcache_types_gen_params),
+	KUNIT_CASE_PARAM(read_bypassed, real_cache_types_gen_params),
+	KUNIT_CASE_PARAM(read_bypassed_volatile, real_cache_types_gen_params),
+	KUNIT_CASE_PARAM(bulk_write, regcache_types_gen_params),
+	KUNIT_CASE_PARAM(bulk_read, regcache_types_gen_params),
+	KUNIT_CASE_PARAM(multi_write, regcache_types_gen_params),
+	KUNIT_CASE_PARAM(multi_read, regcache_types_gen_params),
+	KUNIT_CASE_PARAM(write_readonly, regcache_types_gen_params),
+	KUNIT_CASE_PARAM(read_writeonly, regcache_types_gen_params),
+	KUNIT_CASE_PARAM(reg_defaults, regcache_types_gen_params),
+	KUNIT_CASE_PARAM(reg_defaults_read_dev, regcache_types_gen_params),
+	KUNIT_CASE_PARAM(register_patch, regcache_types_gen_params),
+	KUNIT_CASE_PARAM(stride, regcache_types_gen_params),
+	KUNIT_CASE_PARAM(basic_ranges, regcache_types_gen_params),
+	KUNIT_CASE_PARAM(stress_insert, regcache_types_gen_params),
+	KUNIT_CASE_PARAM(cache_bypass, real_cache_types_gen_params),
+	KUNIT_CASE_PARAM(cache_sync_marked_dirty, real_cache_types_gen_params),
+	KUNIT_CASE_PARAM(cache_sync_after_cache_only, real_cache_types_gen_params),
+	KUNIT_CASE_PARAM(cache_sync_defaults_marked_dirty, real_cache_types_gen_params),
+	KUNIT_CASE_PARAM(cache_sync_default_after_cache_only, real_cache_types_gen_params),
+	KUNIT_CASE_PARAM(cache_sync_readonly, real_cache_types_gen_params),
+	KUNIT_CASE_PARAM(cache_sync_patch, real_cache_types_gen_params),
+	KUNIT_CASE_PARAM(cache_drop, sparse_cache_types_gen_params),
+	KUNIT_CASE_PARAM(cache_drop_with_non_contiguous_ranges, sparse_cache_types_gen_params),
+	KUNIT_CASE_PARAM(cache_drop_all_and_sync_marked_dirty, sparse_cache_types_gen_params),
+	KUNIT_CASE_PARAM(cache_drop_all_and_sync_no_defaults, sparse_cache_types_gen_params),
+	KUNIT_CASE_PARAM(cache_drop_all_and_sync_has_defaults, sparse_cache_types_gen_params),
+	KUNIT_CASE_PARAM(cache_present, sparse_cache_types_gen_params),
+	KUNIT_CASE_PARAM(cache_write_zero, sparse_cache_types_gen_params),
+	KUNIT_CASE_PARAM(cache_range_window_reg, real_cache_types_only_gen_params),
+
+	KUNIT_CASE_PARAM(raw_read_defaults_single, raw_test_types_gen_params),
+	KUNIT_CASE_PARAM(raw_read_defaults, raw_test_types_gen_params),
+	KUNIT_CASE_PARAM(raw_write_read_single, raw_test_types_gen_params),
+	KUNIT_CASE_PARAM(raw_write, raw_test_types_gen_params),
+	KUNIT_CASE_PARAM(raw_noinc_write, raw_test_types_gen_params),
+	KUNIT_CASE_PARAM(raw_sync, raw_test_cache_types_gen_params),
+	KUNIT_CASE_PARAM(raw_ranges, raw_test_cache_types_gen_params),
+	{}
+};
+
+static int regmap_test_init(struct kunit *test)
+{
+	struct regmap_test_priv *priv;
+	struct device *dev;
+
+	priv = kunit_kzalloc(test, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	test->priv = priv;
+
+	dev = kunit_device_register(test, "regmap_test");
+	if (IS_ERR(dev))
+		return PTR_ERR(dev);
+
+	priv->dev = get_device(dev);
+	dev_set_drvdata(dev, test);
+
+	return 0;
+}
+
+static void regmap_test_exit(struct kunit *test)
+{
+	struct regmap_test_priv *priv = test->priv;
+
+	/* Destroy the dummy struct device */
+	if (priv && priv->dev)
+		put_device(priv->dev);
+}
+
+static struct kunit_suite regmap_test_suite = {
+	.name = "regmap",
+	.init = regmap_test_init,
+	.exit = regmap_test_exit,
+	.test_cases = regmap_test_cases,
+};
+kunit_test_suite(regmap_test_suite);
+
+MODULE_DESCRIPTION("Regmap KUnit tests");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/base/regmap/regmap-mdio.c b/drivers/base/regmap/regmap-mdio.c
new file mode 100644
index 000000000000..9573bf3b52f4
--- /dev/null
+++ b/drivers/base/regmap/regmap-mdio.c
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <linux/errno.h>
+#include <linux/mdio.h>
+#include <linux/module.h>
+#include <linux/regmap.h>
+
+#define REGVAL_MASK		GENMASK(15, 0)
+#define REGNUM_C22_MASK		GENMASK(4, 0)
+/* Clause-45 mask includes the device type (5 bit) and actual register number (16 bit) */
+#define REGNUM_C45_MASK		GENMASK(20, 0)
+
+static int regmap_mdio_c22_read(void *context, unsigned int reg, unsigned int *val)
+{
+	struct mdio_device *mdio_dev = context;
+	int ret;
+
+	if (unlikely(reg & ~REGNUM_C22_MASK))
+		return -ENXIO;
+
+	ret = mdiodev_read(mdio_dev, reg);
+	if (ret < 0)
+		return ret;
+
+	*val = ret & REGVAL_MASK;
+
+	return 0;
+}
+
+static int regmap_mdio_c22_write(void *context, unsigned int reg, unsigned int val)
+{
+	struct mdio_device *mdio_dev = context;
+
+	if (unlikely(reg & ~REGNUM_C22_MASK))
+		return -ENXIO;
+
+	return mdiodev_write(mdio_dev, reg, val);
+}
+
+static const struct regmap_bus regmap_mdio_c22_bus = {
+	.reg_write = regmap_mdio_c22_write,
+	.reg_read = regmap_mdio_c22_read,
+};
+
+static int regmap_mdio_c45_read(void *context, unsigned int reg, unsigned int *val)
+{
+	struct mdio_device *mdio_dev = context;
+	unsigned int devad;
+	int ret;
+
+	if (unlikely(reg & ~REGNUM_C45_MASK))
+		return -ENXIO;
+
+	devad = reg >> REGMAP_MDIO_C45_DEVAD_SHIFT;
+	reg = reg & REGMAP_MDIO_C45_REGNUM_MASK;
+
+	ret = mdiodev_c45_read(mdio_dev, devad, reg);
+	if (ret < 0)
+		return ret;
+
+	*val = ret & REGVAL_MASK;
+
+	return 0;
+}
+
+static int regmap_mdio_c45_write(void *context, unsigned int reg, unsigned int val)
+{
+	struct mdio_device *mdio_dev = context;
+	unsigned int devad;
+
+	if (unlikely(reg & ~REGNUM_C45_MASK))
+		return -ENXIO;
+
+	devad = reg >> REGMAP_MDIO_C45_DEVAD_SHIFT;
+	reg = reg & REGMAP_MDIO_C45_REGNUM_MASK;
+
+	return mdiodev_c45_write(mdio_dev, devad, reg, val);
+}
+
+static const struct regmap_bus regmap_mdio_c45_bus = {
+	.reg_write = regmap_mdio_c45_write,
+	.reg_read = regmap_mdio_c45_read,
+};
+
+struct regmap *__regmap_init_mdio(struct mdio_device *mdio_dev,
+	const struct regmap_config *config, struct lock_class_key *lock_key,
+	const char *lock_name)
+{
+	const struct regmap_bus *bus;
+
+	if (config->reg_bits == 5 && config->val_bits == 16)
+		bus = &regmap_mdio_c22_bus;
+	else if (config->reg_bits == 21 && config->val_bits == 16)
+		bus = &regmap_mdio_c45_bus;
+	else
+		return ERR_PTR(-EOPNOTSUPP);
+
+	return __regmap_init(&mdio_dev->dev, bus, mdio_dev, config, lock_key, lock_name);
+}
+EXPORT_SYMBOL_GPL(__regmap_init_mdio);
+
+struct regmap *__devm_regmap_init_mdio(struct mdio_device *mdio_dev,
+	const struct regmap_config *config, struct lock_class_key *lock_key,
+	const char *lock_name)
+{
+	const struct regmap_bus *bus;
+
+	if (config->reg_bits == 5 && config->val_bits == 16)
+		bus = &regmap_mdio_c22_bus;
+	else if (config->reg_bits == 21 && config->val_bits == 16)
+		bus = &regmap_mdio_c45_bus;
+	else
+		return ERR_PTR(-EOPNOTSUPP);
+
+	return __devm_regmap_init(&mdio_dev->dev, bus, mdio_dev, config, lock_key, lock_name);
+}
+EXPORT_SYMBOL_GPL(__devm_regmap_init_mdio);
+
+MODULE_AUTHOR("Sander Vanheule <sander@svanheule.net>");
+MODULE_DESCRIPTION("regmap MDIO Module");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/base/regmap/regmap-mmio.c b/drivers/base/regmap/regmap-mmio.c
index af967d8f975e..29e5f3175301 100644
--- a/drivers/base/regmap/regmap-mmio.c
+++ b/drivers/base/regmap/regmap-mmio.c
@@ -10,12 +10,14 @@
 #include <linux/module.h>
 #include <linux/regmap.h>
 #include <linux/slab.h>
+#include <linux/swab.h>
 
 #include "internal.h"
 
 struct regmap_mmio_context {
 	void __iomem *regs;
-	unsigned val_bytes;
+	unsigned int val_bytes;
+	bool big_endian;
 
 	bool attached_clk;
 	struct clk *clk;
@@ -32,9 +34,6 @@ static int regmap_mmio_regbits_check(size_t reg_bits)
 	case 8:
 	case 16:
 	case 32:
-#ifdef CONFIG_64BIT
-	case 64:
-#endif
 		return 0;
 	default:
 		return -EINVAL;
@@ -49,18 +48,13 @@ static int regmap_mmio_get_min_stride(size_t val_bits)
 	case 8:
 		/* The core treats 0 as 1 */
 		min_stride = 0;
-		return 0;
+		break;
 	case 16:
 		min_stride = 2;
 		break;
 	case 32:
 		min_stride = 4;
 		break;
-#ifdef CONFIG_64BIT
-	case 64:
-		min_stride = 8;
-		break;
-#endif
 	default:
 		return -EINVAL;
 	}
@@ -75,6 +69,19 @@ static void regmap_mmio_write8(struct regmap_mmio_context *ctx,
 	writeb(val, ctx->regs + reg);
 }
 
+static void regmap_mmio_write8_relaxed(struct regmap_mmio_context *ctx,
+				unsigned int reg,
+				unsigned int val)
+{
+	writeb_relaxed(val, ctx->regs + reg);
+}
+
+static void regmap_mmio_iowrite8(struct regmap_mmio_context *ctx,
+				 unsigned int reg, unsigned int val)
+{
+	iowrite8(val, ctx->regs + reg);
+}
+
 static void regmap_mmio_write16le(struct regmap_mmio_context *ctx,
 				  unsigned int reg,
 				  unsigned int val)
@@ -82,10 +89,29 @@ static void regmap_mmio_write16le(struct regmap_mmio_context *ctx,
 	writew(val, ctx->regs + reg);
 }
 
+static void regmap_mmio_write16le_relaxed(struct regmap_mmio_context *ctx,
+				  unsigned int reg,
+				  unsigned int val)
+{
+	writew_relaxed(val, ctx->regs + reg);
+}
+
+static void regmap_mmio_iowrite16le(struct regmap_mmio_context *ctx,
+				    unsigned int reg, unsigned int val)
+{
+	iowrite16(val, ctx->regs + reg);
+}
+
 static void regmap_mmio_write16be(struct regmap_mmio_context *ctx,
 				  unsigned int reg,
 				  unsigned int val)
 {
+	writew(swab16(val), ctx->regs + reg);
+}
+
+static void regmap_mmio_iowrite16be(struct regmap_mmio_context *ctx,
+				    unsigned int reg, unsigned int val)
+{
 	iowrite16be(val, ctx->regs + reg);
 }
 
@@ -96,21 +122,31 @@ static void regmap_mmio_write32le(struct regmap_mmio_context *ctx,
 	writel(val, ctx->regs + reg);
 }
 
-static void regmap_mmio_write32be(struct regmap_mmio_context *ctx,
+static void regmap_mmio_write32le_relaxed(struct regmap_mmio_context *ctx,
 				  unsigned int reg,
 				  unsigned int val)
 {
-	iowrite32be(val, ctx->regs + reg);
+	writel_relaxed(val, ctx->regs + reg);
 }
 
-#ifdef CONFIG_64BIT
-static void regmap_mmio_write64le(struct regmap_mmio_context *ctx,
+static void regmap_mmio_iowrite32le(struct regmap_mmio_context *ctx,
+				    unsigned int reg, unsigned int val)
+{
+	iowrite32(val, ctx->regs + reg);
+}
+
+static void regmap_mmio_write32be(struct regmap_mmio_context *ctx,
 				  unsigned int reg,
 				  unsigned int val)
 {
-	writeq(val, ctx->regs + reg);
+	writel(swab32(val), ctx->regs + reg);
+}
+
+static void regmap_mmio_iowrite32be(struct regmap_mmio_context *ctx,
+				    unsigned int reg, unsigned int val)
+{
+	iowrite32be(val, ctx->regs + reg);
 }
-#endif
 
 static int regmap_mmio_write(void *context, unsigned int reg, unsigned int val)
 {
@@ -131,21 +167,114 @@ static int regmap_mmio_write(void *context, unsigned int reg, unsigned int val)
 	return 0;
 }
 
+static int regmap_mmio_noinc_write(void *context, unsigned int reg,
+				   const void *val, size_t val_count)
+{
+	struct regmap_mmio_context *ctx = context;
+	int ret = 0;
+	int i;
+
+	if (!IS_ERR(ctx->clk)) {
+		ret = clk_enable(ctx->clk);
+		if (ret < 0)
+			return ret;
+	}
+
+	/*
+	 * There are no native, assembly-optimized write single register
+	 * operations for big endian, so fall back to emulation if this
+	 * is needed. (Single bytes are fine, they are not affected by
+	 * endianness.)
+	 */
+	if (ctx->big_endian && (ctx->val_bytes > 1)) {
+		switch (ctx->val_bytes) {
+		case 2:
+		{
+			const u16 *valp = (const u16 *)val;
+			for (i = 0; i < val_count; i++)
+				writew(swab16(valp[i]), ctx->regs + reg);
+			goto out_clk;
+		}
+		case 4:
+		{
+			const u32 *valp = (const u32 *)val;
+			for (i = 0; i < val_count; i++)
+				writel(swab32(valp[i]), ctx->regs + reg);
+			goto out_clk;
+		}
+		default:
+			ret = -EINVAL;
+			goto out_clk;
+		}
+	}
+
+	switch (ctx->val_bytes) {
+	case 1:
+		writesb(ctx->regs + reg, (const u8 *)val, val_count);
+		break;
+	case 2:
+		writesw(ctx->regs + reg, (const u16 *)val, val_count);
+		break;
+	case 4:
+		writesl(ctx->regs + reg, (const u32 *)val, val_count);
+		break;
+	default:
+		ret = -EINVAL;
+		break;
+	}
+
+out_clk:
+	if (!IS_ERR(ctx->clk))
+		clk_disable(ctx->clk);
+
+	return ret;
+}
+
 static unsigned int regmap_mmio_read8(struct regmap_mmio_context *ctx,
 				      unsigned int reg)
 {
 	return readb(ctx->regs + reg);
 }
 
+static unsigned int regmap_mmio_read8_relaxed(struct regmap_mmio_context *ctx,
+				      unsigned int reg)
+{
+	return readb_relaxed(ctx->regs + reg);
+}
+
+static unsigned int regmap_mmio_ioread8(struct regmap_mmio_context *ctx,
+					unsigned int reg)
+{
+	return ioread8(ctx->regs + reg);
+}
+
 static unsigned int regmap_mmio_read16le(struct regmap_mmio_context *ctx,
 				         unsigned int reg)
 {
 	return readw(ctx->regs + reg);
 }
 
+static unsigned int regmap_mmio_read16le_relaxed(struct regmap_mmio_context *ctx,
+						 unsigned int reg)
+{
+	return readw_relaxed(ctx->regs + reg);
+}
+
+static unsigned int regmap_mmio_ioread16le(struct regmap_mmio_context *ctx,
+					   unsigned int reg)
+{
+	return ioread16(ctx->regs + reg);
+}
+
 static unsigned int regmap_mmio_read16be(struct regmap_mmio_context *ctx,
 				         unsigned int reg)
 {
+	return swab16(readw(ctx->regs + reg));
+}
+
+static unsigned int regmap_mmio_ioread16be(struct regmap_mmio_context *ctx,
+					   unsigned int reg)
+{
 	return ioread16be(ctx->regs + reg);
 }
 
@@ -155,19 +284,29 @@ static unsigned int regmap_mmio_read32le(struct regmap_mmio_context *ctx,
 	return readl(ctx->regs + reg);
 }
 
+static unsigned int regmap_mmio_read32le_relaxed(struct regmap_mmio_context *ctx,
+						 unsigned int reg)
+{
+	return readl_relaxed(ctx->regs + reg);
+}
+
+static unsigned int regmap_mmio_ioread32le(struct regmap_mmio_context *ctx,
+					   unsigned int reg)
+{
+	return ioread32(ctx->regs + reg);
+}
+
 static unsigned int regmap_mmio_read32be(struct regmap_mmio_context *ctx,
 				         unsigned int reg)
 {
-	return ioread32be(ctx->regs + reg);
+	return swab32(readl(ctx->regs + reg));
 }
 
-#ifdef CONFIG_64BIT
-static unsigned int regmap_mmio_read64le(struct regmap_mmio_context *ctx,
-				         unsigned int reg)
+static unsigned int regmap_mmio_ioread32be(struct regmap_mmio_context *ctx,
+					   unsigned int reg)
 {
-	return readq(ctx->regs + reg);
+	return ioread32be(ctx->regs + reg);
 }
-#endif
 
 static int regmap_mmio_read(void *context, unsigned int reg, unsigned int *val)
 {
@@ -188,6 +327,61 @@ static int regmap_mmio_read(void *context, unsigned int reg, unsigned int *val)
 	return 0;
 }
 
+static int regmap_mmio_noinc_read(void *context, unsigned int reg,
+				  void *val, size_t val_count)
+{
+	struct regmap_mmio_context *ctx = context;
+	int ret = 0;
+
+	if (!IS_ERR(ctx->clk)) {
+		ret = clk_enable(ctx->clk);
+		if (ret < 0)
+			return ret;
+	}
+
+	switch (ctx->val_bytes) {
+	case 1:
+		readsb(ctx->regs + reg, (u8 *)val, val_count);
+		break;
+	case 2:
+		readsw(ctx->regs + reg, (u16 *)val, val_count);
+		break;
+	case 4:
+		readsl(ctx->regs + reg, (u32 *)val, val_count);
+		break;
+	default:
+		ret = -EINVAL;
+		goto out_clk;
+	}
+
+	/*
+	 * There are no native, assembly-optimized write single register
+	 * operations for big endian, so fall back to emulation if this
+	 * is needed. (Single bytes are fine, they are not affected by
+	 * endianness.)
+	 */
+	if (ctx->big_endian && (ctx->val_bytes > 1)) {
+		switch (ctx->val_bytes) {
+		case 2:
+			swab16_array(val, val_count);
+			break;
+		case 4:
+			swab32_array(val, val_count);
+			break;
+		default:
+			ret = -EINVAL;
+			break;
+		}
+	}
+
+out_clk:
+	if (!IS_ERR(ctx->clk))
+		clk_disable(ctx->clk);
+
+	return ret;
+}
+
+
 static void regmap_mmio_free_context(void *context)
 {
 	struct regmap_mmio_context *ctx = context;
@@ -204,6 +398,8 @@ static const struct regmap_bus regmap_mmio = {
 	.fast_io = true,
 	.reg_write = regmap_mmio_write,
 	.reg_read = regmap_mmio_read,
+	.reg_noinc_write = regmap_mmio_noinc_write,
+	.reg_noinc_read = regmap_mmio_noinc_read,
 	.free_context = regmap_mmio_free_context,
 	.val_format_endian_default = REGMAP_ENDIAN_LITTLE,
 };
@@ -228,7 +424,10 @@ static struct regmap_mmio_context *regmap_mmio_gen_context(struct device *dev,
 	if (min_stride < 0)
 		return ERR_PTR(min_stride);
 
-	if (config->reg_stride < min_stride)
+	if (config->reg_stride && config->reg_stride < min_stride)
+		return ERR_PTR(-EINVAL);
+
+	if (config->use_relaxed_mmio && config->io_port)
 		return ERR_PTR(-EINVAL);
 
 	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
@@ -247,23 +446,41 @@ static struct regmap_mmio_context *regmap_mmio_gen_context(struct device *dev,
 #endif
 		switch (config->val_bits) {
 		case 8:
-			ctx->reg_read = regmap_mmio_read8;
-			ctx->reg_write = regmap_mmio_write8;
+			if (config->io_port) {
+				ctx->reg_read = regmap_mmio_ioread8;
+				ctx->reg_write = regmap_mmio_iowrite8;
+			} else if (config->use_relaxed_mmio) {
+				ctx->reg_read = regmap_mmio_read8_relaxed;
+				ctx->reg_write = regmap_mmio_write8_relaxed;
+			} else {
+				ctx->reg_read = regmap_mmio_read8;
+				ctx->reg_write = regmap_mmio_write8;
+			}
 			break;
 		case 16:
-			ctx->reg_read = regmap_mmio_read16le;
-			ctx->reg_write = regmap_mmio_write16le;
+			if (config->io_port) {
+				ctx->reg_read = regmap_mmio_ioread16le;
+				ctx->reg_write = regmap_mmio_iowrite16le;
+			} else if (config->use_relaxed_mmio) {
+				ctx->reg_read = regmap_mmio_read16le_relaxed;
+				ctx->reg_write = regmap_mmio_write16le_relaxed;
+			} else {
+				ctx->reg_read = regmap_mmio_read16le;
+				ctx->reg_write = regmap_mmio_write16le;
+			}
 			break;
 		case 32:
-			ctx->reg_read = regmap_mmio_read32le;
-			ctx->reg_write = regmap_mmio_write32le;
-			break;
-#ifdef CONFIG_64BIT
-		case 64:
-			ctx->reg_read = regmap_mmio_read64le;
-			ctx->reg_write = regmap_mmio_write64le;
+			if (config->io_port) {
+				ctx->reg_read = regmap_mmio_ioread32le;
+				ctx->reg_write = regmap_mmio_iowrite32le;
+			} else if (config->use_relaxed_mmio) {
+				ctx->reg_read = regmap_mmio_read32le_relaxed;
+				ctx->reg_write = regmap_mmio_write32le_relaxed;
+			} else {
+				ctx->reg_read = regmap_mmio_read32le;
+				ctx->reg_write = regmap_mmio_write32le;
+			}
 			break;
-#endif
 		default:
 			ret = -EINVAL;
 			goto err_free;
@@ -273,18 +490,34 @@ static struct regmap_mmio_context *regmap_mmio_gen_context(struct device *dev,
 #ifdef __BIG_ENDIAN
 	case REGMAP_ENDIAN_NATIVE:
 #endif
+		ctx->big_endian = true;
 		switch (config->val_bits) {
 		case 8:
-			ctx->reg_read = regmap_mmio_read8;
-			ctx->reg_write = regmap_mmio_write8;
+			if (config->io_port) {
+				ctx->reg_read = regmap_mmio_ioread8;
+				ctx->reg_write = regmap_mmio_iowrite8;
+			} else {
+				ctx->reg_read = regmap_mmio_read8;
+				ctx->reg_write = regmap_mmio_write8;
+			}
 			break;
 		case 16:
-			ctx->reg_read = regmap_mmio_read16be;
-			ctx->reg_write = regmap_mmio_write16be;
+			if (config->io_port) {
+				ctx->reg_read = regmap_mmio_ioread16be;
+				ctx->reg_write = regmap_mmio_iowrite16be;
+			} else {
+				ctx->reg_read = regmap_mmio_read16be;
+				ctx->reg_write = regmap_mmio_write16be;
+			}
 			break;
 		case 32:
-			ctx->reg_read = regmap_mmio_read32be;
-			ctx->reg_write = regmap_mmio_write32be;
+			if (config->io_port) {
+				ctx->reg_read = regmap_mmio_ioread32be;
+				ctx->reg_write = regmap_mmio_iowrite32be;
+			} else {
+				ctx->reg_read = regmap_mmio_read32be;
+				ctx->reg_write = regmap_mmio_write32be;
+			}
 			break;
 		default:
 			ret = -EINVAL;
@@ -376,4 +609,5 @@ void regmap_mmio_detach_clk(struct regmap *map)
 }
 EXPORT_SYMBOL_GPL(regmap_mmio_detach_clk);
 
+MODULE_DESCRIPTION("regmap MMIO Module");
 MODULE_LICENSE("GPL v2");
diff --git a/drivers/base/regmap/regmap-ram.c b/drivers/base/regmap/regmap-ram.c
new file mode 100644
index 000000000000..4e5b4518ce4d
--- /dev/null
+++ b/drivers/base/regmap/regmap-ram.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Register map access API - Memory region
+//
+// This is intended for testing only
+//
+// Copyright (c) 2023, Arm Ltd
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+#include <linux/swab.h>
+
+#include "internal.h"
+
+static int regmap_ram_write(void *context, unsigned int reg, unsigned int val)
+{
+	struct regmap_ram_data *data = context;
+
+	data->vals[reg] = val;
+	data->written[reg] = true;
+
+	return 0;
+}
+
+static int regmap_ram_read(void *context, unsigned int reg, unsigned int *val)
+{
+	struct regmap_ram_data *data = context;
+
+	*val = data->vals[reg];
+	data->read[reg] = true;
+
+	return 0;
+}
+
+static void regmap_ram_free_context(void *context)
+{
+	struct regmap_ram_data *data = context;
+
+	kfree(data->vals);
+	kfree(data->read);
+	kfree(data->written);
+	kfree(data);
+}
+
+static const struct regmap_bus regmap_ram = {
+	.fast_io = true,
+	.reg_write = regmap_ram_write,
+	.reg_read = regmap_ram_read,
+	.free_context = regmap_ram_free_context,
+};
+
+struct regmap *__regmap_init_ram(struct device *dev,
+				 const struct regmap_config *config,
+				 struct regmap_ram_data *data,
+				 struct lock_class_key *lock_key,
+				 const char *lock_name)
+{
+	struct regmap *map;
+
+	if (!config->max_register) {
+		pr_crit("No max_register specified for RAM regmap\n");
+		return ERR_PTR(-EINVAL);
+	}
+
+	data->read = kcalloc(config->max_register + 1, sizeof(bool),
+			     GFP_KERNEL);
+	if (!data->read)
+		return ERR_PTR(-ENOMEM);
+
+	data->written = kcalloc(config->max_register + 1, sizeof(bool),
+				GFP_KERNEL);
+	if (!data->written)
+		return ERR_PTR(-ENOMEM);
+
+	map = __regmap_init(dev, &regmap_ram, data, config,
+			    lock_key, lock_name);
+
+	return map;
+}
+EXPORT_SYMBOL_GPL(__regmap_init_ram);
+
+MODULE_DESCRIPTION("Register map access API - Memory region");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/base/regmap/regmap-raw-ram.c b/drivers/base/regmap/regmap-raw-ram.c
new file mode 100644
index 000000000000..76c98814fb8a
--- /dev/null
+++ b/drivers/base/regmap/regmap-raw-ram.c
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Register map access API - Memory region with raw access
+//
+// This is intended for testing only
+//
+// Copyright (c) 2023, Arm Ltd
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+#include <linux/swab.h>
+
+#include "internal.h"
+
+static unsigned int decode_reg(enum regmap_endian endian, const void *reg)
+{
+	const u16 *r = reg;
+
+	if (endian == REGMAP_ENDIAN_BIG)
+		return be16_to_cpu(*r);
+	else
+		return le16_to_cpu(*r);
+}
+
+static int regmap_raw_ram_gather_write(void *context,
+				       const void *reg, size_t reg_len,
+				       const void *val, size_t val_len)
+{
+	struct regmap_ram_data *data = context;
+	unsigned int r;
+	u16 *our_buf = (u16 *)data->vals;
+	int i;
+
+	if (reg_len != 2)
+		return -EINVAL;
+	if (val_len % 2)
+		return -EINVAL;
+
+	r = decode_reg(data->reg_endian, reg);
+	if (data->noinc_reg && data->noinc_reg(data, r)) {
+		memcpy(&our_buf[r], val + val_len - 2, 2);
+		data->written[r] = true;
+	} else {
+		memcpy(&our_buf[r], val, val_len);
+
+		for (i = 0; i < val_len / 2; i++)
+			data->written[r + i] = true;
+	}
+	
+	return 0;
+}
+
+static int regmap_raw_ram_write(void *context, const void *data, size_t count)
+{
+	return regmap_raw_ram_gather_write(context, data, 2,
+					   data + 2, count - 2);
+}
+
+static int regmap_raw_ram_read(void *context,
+			       const void *reg, size_t reg_len,
+			       void *val, size_t val_len)
+{
+	struct regmap_ram_data *data = context;
+	unsigned int r;
+	u16 *our_buf = (u16 *)data->vals;
+	int i;
+
+	if (reg_len != 2)
+		return -EINVAL;
+	if (val_len % 2)
+		return -EINVAL;
+
+	r = decode_reg(data->reg_endian, reg);
+	if (data->noinc_reg && data->noinc_reg(data, r)) {
+		for (i = 0; i < val_len; i += 2)
+			memcpy(val + i, &our_buf[r], 2);
+		data->read[r] = true;
+	} else {
+		memcpy(val, &our_buf[r], val_len);
+
+		for (i = 0; i < val_len / 2; i++)
+			data->read[r + i] = true;
+	}
+
+	return 0;
+}
+
+static void regmap_raw_ram_free_context(void *context)
+{
+	struct regmap_ram_data *data = context;
+
+	kfree(data->vals);
+	kfree(data->read);
+	kfree(data->written);
+	kfree(data);
+}
+
+static const struct regmap_bus regmap_raw_ram = {
+	.fast_io = true,
+	.write = regmap_raw_ram_write,
+	.gather_write = regmap_raw_ram_gather_write,
+	.read = regmap_raw_ram_read,
+	.free_context = regmap_raw_ram_free_context,
+};
+
+struct regmap *__regmap_init_raw_ram(struct device *dev,
+				     const struct regmap_config *config,
+				     struct regmap_ram_data *data,
+				     struct lock_class_key *lock_key,
+				     const char *lock_name)
+{
+	struct regmap *map;
+
+	if (config->reg_bits != 16)
+		return ERR_PTR(-EINVAL);
+
+	if (!config->max_register) {
+		pr_crit("No max_register specified for RAM regmap\n");
+		return ERR_PTR(-EINVAL);
+	}
+
+	data->read = kcalloc(config->max_register + 1, sizeof(bool),
+			     GFP_KERNEL);
+	if (!data->read)
+		return ERR_PTR(-ENOMEM);
+
+	data->written = kcalloc(config->max_register + 1, sizeof(bool),
+				GFP_KERNEL);
+	if (!data->written)
+		return ERR_PTR(-ENOMEM);
+
+	data->reg_endian = config->reg_format_endian;
+
+	map = __regmap_init(dev, &regmap_raw_ram, data, config,
+			    lock_key, lock_name);
+
+	return map;
+}
+EXPORT_SYMBOL_GPL(__regmap_init_raw_ram);
+
+MODULE_DESCRIPTION("Register map access API - Memory region with raw access");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/base/regmap/regmap-sccb.c b/drivers/base/regmap/regmap-sccb.c
index 597042e2d009..12bbbb03e5f2 100644
--- a/drivers/base/regmap/regmap-sccb.c
+++ b/drivers/base/regmap/regmap-sccb.c
@@ -80,7 +80,7 @@ static int regmap_sccb_write(void *context, unsigned int reg, unsigned int val)
 	return i2c_smbus_write_byte_data(i2c, reg, val);
 }
 
-static struct regmap_bus regmap_sccb_bus = {
+static const struct regmap_bus regmap_sccb_bus = {
 	.reg_write = regmap_sccb_write,
 	.reg_read = regmap_sccb_read,
 };
@@ -125,4 +125,5 @@ struct regmap *__devm_regmap_init_sccb(struct i2c_client *i2c,
 }
 EXPORT_SYMBOL_GPL(__devm_regmap_init_sccb);
 
+MODULE_DESCRIPTION("Register map access API - SCCB support");
 MODULE_LICENSE("GPL v2");
diff --git a/drivers/base/regmap/regmap-sdw-mbq.c b/drivers/base/regmap/regmap-sdw-mbq.c
new file mode 100644
index 000000000000..6a61629f5f89
--- /dev/null
+++ b/drivers/base/regmap/regmap-sdw-mbq.c
@@ -0,0 +1,278 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright(c) 2020 Intel Corporation.
+
+#include <linux/bits.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/regmap.h>
+#include <linux/soundwire/sdw.h>
+#include <linux/soundwire/sdw_registers.h>
+#include <sound/sdca_function.h>
+#include "internal.h"
+
+struct regmap_mbq_context {
+	struct device *dev;
+	struct sdw_slave *sdw;
+
+	bool (*readable_reg)(struct device *dev, unsigned int reg);
+
+	struct regmap_sdw_mbq_cfg cfg;
+
+	int val_size;
+};
+
+static int regmap_sdw_mbq_size(struct regmap_mbq_context *ctx, unsigned int reg)
+{
+	int size = ctx->val_size;
+
+	if (ctx->cfg.mbq_size) {
+		size = ctx->cfg.mbq_size(ctx->dev, reg);
+		if (!size || size > ctx->val_size)
+			return -EINVAL;
+	}
+
+	return size;
+}
+
+static bool regmap_sdw_mbq_deferrable(struct regmap_mbq_context *ctx, unsigned int reg)
+{
+	if (ctx->cfg.deferrable)
+		return ctx->cfg.deferrable(ctx->dev, reg);
+
+	return false;
+}
+
+static int regmap_sdw_mbq_poll_busy(struct sdw_slave *slave, unsigned int reg,
+				    struct regmap_mbq_context *ctx)
+{
+	struct device *dev = ctx->dev;
+	int val, ret = 0;
+
+	dev_dbg(dev, "Deferring transaction for 0x%x\n", reg);
+
+	reg = SDW_SDCA_CTL(SDW_SDCA_CTL_FUNC(reg), 0,
+			   SDCA_CTL_ENTITY_0_FUNCTION_STATUS, 0);
+
+	if (ctx->readable_reg(dev, reg)) {
+		ret = read_poll_timeout(sdw_read_no_pm, val,
+					val < 0 || !(val & SDCA_CTL_ENTITY_0_FUNCTION_BUSY),
+					ctx->cfg.timeout_us, ctx->cfg.retry_us,
+					false, slave, reg);
+		if (val < 0)
+			return val;
+		if (ret)
+			dev_err(dev, "Function busy timed out 0x%x: %d\n", reg, val);
+	} else {
+		fsleep(ctx->cfg.timeout_us);
+	}
+
+	return ret;
+}
+
+static int regmap_sdw_mbq_write_impl(struct sdw_slave *slave,
+				     unsigned int reg, unsigned int val,
+				     int mbq_size, bool deferrable)
+{
+	int shift = mbq_size * BITS_PER_BYTE;
+	int ret;
+
+	while (--mbq_size > 0) {
+		shift -= BITS_PER_BYTE;
+
+		ret = sdw_write_no_pm(slave, SDW_SDCA_MBQ_CTL(reg),
+				      (val >> shift) & 0xff);
+		if (ret < 0)
+			return ret;
+	}
+
+	ret = sdw_write_no_pm(slave, reg, val & 0xff);
+	if (deferrable && ret == -ENODATA)
+		return -EAGAIN;
+
+	return ret;
+}
+
+static int regmap_sdw_mbq_write(void *context, unsigned int reg, unsigned int val)
+{
+	struct regmap_mbq_context *ctx = context;
+	struct sdw_slave *slave = ctx->sdw;
+	bool deferrable = regmap_sdw_mbq_deferrable(ctx, reg);
+	int mbq_size = regmap_sdw_mbq_size(ctx, reg);
+	int ret;
+
+	if (mbq_size < 0)
+		return mbq_size;
+
+	/*
+	 * Technically the spec does allow a device to set itself to busy for
+	 * internal reasons, but since it doesn't provide any information on
+	 * how to handle timeouts in that case, for now the code will only
+	 * process a single wait/timeout on function busy and a single retry
+	 * of the transaction.
+	 */
+	ret = regmap_sdw_mbq_write_impl(slave, reg, val, mbq_size, deferrable);
+	if (ret == -EAGAIN) {
+		ret = regmap_sdw_mbq_poll_busy(slave, reg, ctx);
+		if (ret)
+			return ret;
+
+		ret = regmap_sdw_mbq_write_impl(slave, reg, val, mbq_size, false);
+	}
+
+	return ret;
+}
+
+static int regmap_sdw_mbq_read_impl(struct sdw_slave *slave,
+				    unsigned int reg, unsigned int *val,
+				    int mbq_size, bool deferrable)
+{
+	int shift = BITS_PER_BYTE;
+	int read;
+
+	read = sdw_read_no_pm(slave, reg);
+	if (read < 0) {
+		if (deferrable && read == -ENODATA)
+			return -EAGAIN;
+
+		return read;
+	}
+
+	*val = read;
+
+	while (--mbq_size > 0) {
+		read = sdw_read_no_pm(slave, SDW_SDCA_MBQ_CTL(reg));
+		if (read < 0)
+			return read;
+
+		*val |= read << shift;
+		shift += BITS_PER_BYTE;
+	}
+
+	return 0;
+}
+
+static int regmap_sdw_mbq_read(void *context, unsigned int reg, unsigned int *val)
+{
+	struct regmap_mbq_context *ctx = context;
+	struct sdw_slave *slave = ctx->sdw;
+	bool deferrable = regmap_sdw_mbq_deferrable(ctx, reg);
+	int mbq_size = regmap_sdw_mbq_size(ctx, reg);
+	int ret;
+
+	if (mbq_size < 0)
+		return mbq_size;
+
+	/*
+	 * Technically the spec does allow a device to set itself to busy for
+	 * internal reasons, but since it doesn't provide any information on
+	 * how to handle timeouts in that case, for now the code will only
+	 * process a single wait/timeout on function busy and a single retry
+	 * of the transaction.
+	 */
+	ret = regmap_sdw_mbq_read_impl(slave, reg, val, mbq_size, deferrable);
+	if (ret == -EAGAIN) {
+		ret = regmap_sdw_mbq_poll_busy(slave, reg, ctx);
+		if (ret)
+			return ret;
+
+		ret = regmap_sdw_mbq_read_impl(slave, reg, val, mbq_size, false);
+	}
+
+	return ret;
+}
+
+static const struct regmap_bus regmap_sdw_mbq = {
+	.reg_read = regmap_sdw_mbq_read,
+	.reg_write = regmap_sdw_mbq_write,
+	.reg_format_endian_default = REGMAP_ENDIAN_LITTLE,
+	.val_format_endian_default = REGMAP_ENDIAN_LITTLE,
+};
+
+static int regmap_sdw_mbq_config_check(const struct regmap_config *config)
+{
+	if (config->val_bits > (sizeof(unsigned int) * BITS_PER_BYTE))
+		return -ENOTSUPP;
+
+	/* Registers are 32 bits wide */
+	if (config->reg_bits != 32)
+		return -ENOTSUPP;
+
+	if (config->pad_bits != 0)
+		return -ENOTSUPP;
+
+	return 0;
+}
+
+static struct regmap_mbq_context *
+regmap_sdw_mbq_gen_context(struct device *dev,
+			   struct sdw_slave *sdw,
+			   const struct regmap_config *config,
+			   const struct regmap_sdw_mbq_cfg *mbq_config)
+{
+	struct regmap_mbq_context *ctx;
+
+	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
+	if (!ctx)
+		return ERR_PTR(-ENOMEM);
+
+	ctx->dev = dev;
+	ctx->sdw = sdw;
+
+	if (mbq_config)
+		ctx->cfg = *mbq_config;
+
+	ctx->val_size = config->val_bits / BITS_PER_BYTE;
+	ctx->readable_reg = config->readable_reg;
+
+	return ctx;
+}
+
+struct regmap *__regmap_init_sdw_mbq(struct device *dev, struct sdw_slave *sdw,
+				     const struct regmap_config *config,
+				     const struct regmap_sdw_mbq_cfg *mbq_config,
+				     struct lock_class_key *lock_key,
+				     const char *lock_name)
+{
+	struct regmap_mbq_context *ctx;
+	int ret;
+
+	ret = regmap_sdw_mbq_config_check(config);
+	if (ret)
+		return ERR_PTR(ret);
+
+	ctx = regmap_sdw_mbq_gen_context(dev, sdw, config, mbq_config);
+	if (IS_ERR(ctx))
+		return ERR_CAST(ctx);
+
+	return __regmap_init(dev, &regmap_sdw_mbq, ctx,
+			     config, lock_key, lock_name);
+}
+EXPORT_SYMBOL_GPL(__regmap_init_sdw_mbq);
+
+struct regmap *__devm_regmap_init_sdw_mbq(struct device *dev, struct sdw_slave *sdw,
+					  const struct regmap_config *config,
+					  const struct regmap_sdw_mbq_cfg *mbq_config,
+					  struct lock_class_key *lock_key,
+					  const char *lock_name)
+{
+	struct regmap_mbq_context *ctx;
+	int ret;
+
+	ret = regmap_sdw_mbq_config_check(config);
+	if (ret)
+		return ERR_PTR(ret);
+
+	ctx = regmap_sdw_mbq_gen_context(dev, sdw, config, mbq_config);
+	if (IS_ERR(ctx))
+		return ERR_CAST(ctx);
+
+	return __devm_regmap_init(dev, &regmap_sdw_mbq, ctx,
+				  config, lock_key, lock_name);
+}
+EXPORT_SYMBOL_GPL(__devm_regmap_init_sdw_mbq);
+
+MODULE_DESCRIPTION("regmap SoundWire MBQ Module");
+MODULE_LICENSE("GPL");
diff --git a/drivers/base/regmap/regmap-sdw.c b/drivers/base/regmap/regmap-sdw.c
index 50a66382d87d..ea631ac7c7ec 100644
--- a/drivers/base/regmap/regmap-sdw.c
+++ b/drivers/base/regmap/regmap-sdw.c
@@ -2,53 +2,67 @@
 // Copyright(c) 2015-17 Intel Corporation.
 
 #include <linux/device.h>
-#include <linux/mod_devicetable.h>
+#include <linux/errno.h>
 #include <linux/module.h>
+#include <linux/regmap.h>
 #include <linux/soundwire/sdw.h>
+#include <linux/types.h>
 #include "internal.h"
 
-static int regmap_sdw_write(void *context, unsigned int reg, unsigned int val)
+static int regmap_sdw_write(void *context, const void *val_buf, size_t val_size)
 {
 	struct device *dev = context;
 	struct sdw_slave *slave = dev_to_sdw_dev(dev);
+	/* First word of buffer contains the destination address */
+	u32 addr = le32_to_cpu(*(const __le32 *)val_buf);
+	const u8 *val = val_buf;
 
-	return sdw_write(slave, reg, val);
+	return sdw_nwrite_no_pm(slave, addr, val_size - sizeof(addr), val + sizeof(addr));
 }
 
-static int regmap_sdw_read(void *context, unsigned int reg, unsigned int *val)
+static int regmap_sdw_gather_write(void *context,
+				   const void *reg_buf, size_t reg_size,
+				   const void *val_buf, size_t val_size)
 {
 	struct device *dev = context;
 	struct sdw_slave *slave = dev_to_sdw_dev(dev);
-	int read;
+	u32 addr = le32_to_cpu(*(const __le32 *)reg_buf);
 
-	read = sdw_read(slave, reg);
-	if (read < 0)
-		return read;
+	return sdw_nwrite_no_pm(slave, addr, val_size, val_buf);
+}
 
-	*val = read;
-	return 0;
+static int regmap_sdw_read(void *context,
+			   const void *reg_buf, size_t reg_size,
+			   void *val_buf, size_t val_size)
+{
+	struct device *dev = context;
+	struct sdw_slave *slave = dev_to_sdw_dev(dev);
+	u32 addr = le32_to_cpu(*(const __le32 *)reg_buf);
+
+	return sdw_nread_no_pm(slave, addr, val_size, val_buf);
 }
 
-static struct regmap_bus regmap_sdw = {
-	.reg_read = regmap_sdw_read,
-	.reg_write = regmap_sdw_write,
+static const struct regmap_bus regmap_sdw = {
+	.write = regmap_sdw_write,
+	.gather_write = regmap_sdw_gather_write,
+	.read = regmap_sdw_read,
 	.reg_format_endian_default = REGMAP_ENDIAN_LITTLE,
 	.val_format_endian_default = REGMAP_ENDIAN_LITTLE,
 };
 
 static int regmap_sdw_config_check(const struct regmap_config *config)
 {
-	/* All register are 8-bits wide as per MIPI Soundwire 1.0 Spec */
-	if (config->val_bits != 8)
-		return -ENOTSUPP;
-
-	/* Registers are 32 bits wide */
+	/* Register addresses are 32 bits wide */
 	if (config->reg_bits != 32)
 		return -ENOTSUPP;
 
 	if (config->pad_bits != 0)
 		return -ENOTSUPP;
 
+	/* Only bulk writes are supported not multi-register writes */
+	if (config->can_multi_write)
+		return -ENOTSUPP;
+
 	return 0;
 }
 
@@ -84,5 +98,5 @@ struct regmap *__devm_regmap_init_sdw(struct sdw_slave *sdw,
 }
 EXPORT_SYMBOL_GPL(__devm_regmap_init_sdw);
 
-MODULE_DESCRIPTION("Regmap SoundWire Module");
+MODULE_DESCRIPTION("regmap SoundWire Module");
 MODULE_LICENSE("GPL v2");
diff --git a/drivers/base/regmap/regmap-slimbus.c b/drivers/base/regmap/regmap-slimbus.c
index 0968059f1ef5..e523fae73004 100644
--- a/drivers/base/regmap/regmap-slimbus.c
+++ b/drivers/base/regmap/regmap-slimbus.c
@@ -22,7 +22,7 @@ static int regmap_slimbus_read(void *context, const void *reg, size_t reg_size,
 	return slim_read(sdev, *(u16 *)reg, val_size, val);
 }
 
-static struct regmap_bus regmap_slimbus_bus = {
+static const struct regmap_bus regmap_slimbus_bus = {
 	.write = regmap_slimbus_write,
 	.read = regmap_slimbus_read,
 	.reg_format_endian_default = REGMAP_ENDIAN_LITTLE,
@@ -48,8 +48,7 @@ struct regmap *__regmap_init_slimbus(struct slim_device *slimbus,
 	if (IS_ERR(bus))
 		return ERR_CAST(bus);
 
-	return __regmap_init(&slimbus->dev, bus, &slimbus->dev, config,
-			     lock_key, lock_name);
+	return __regmap_init(&slimbus->dev, bus, slimbus, config, lock_key, lock_name);
 }
 EXPORT_SYMBOL_GPL(__regmap_init_slimbus);
 
@@ -63,9 +62,9 @@ struct regmap *__devm_regmap_init_slimbus(struct slim_device *slimbus,
 	if (IS_ERR(bus))
 		return ERR_CAST(bus);
 
-	return __devm_regmap_init(&slimbus->dev, bus, &slimbus, config,
-				  lock_key, lock_name);
+	return __devm_regmap_init(&slimbus->dev, bus, slimbus, config, lock_key, lock_name);
 }
 EXPORT_SYMBOL_GPL(__devm_regmap_init_slimbus);
 
+MODULE_DESCRIPTION("Register map access API - SLIMbus support");
 MODULE_LICENSE("GPL v2");
diff --git a/drivers/base/regmap/regmap-spi-avmm.c b/drivers/base/regmap/regmap-spi-avmm.c
new file mode 100644
index 000000000000..d86a06cadcdb
--- /dev/null
+++ b/drivers/base/regmap/regmap-spi-avmm.c
@@ -0,0 +1,714 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Register map access API - SPI AVMM support
+//
+// Copyright (C) 2018-2020 Intel Corporation. All rights reserved.
+
+#include <linux/module.h>
+#include <linux/regmap.h>
+#include <linux/spi/spi.h>
+#include <linux/swab.h>
+
+/*
+ * This driver implements the regmap operations for a generic SPI
+ * master to access the registers of the spi slave chip which has an
+ * Avalone bus in it.
+ *
+ * The "SPI slave to Avalon Master Bridge" (spi-avmm) IP should be integrated
+ * in the spi slave chip. The IP acts as a bridge to convert encoded streams of
+ * bytes from the host to the internal register read/write on Avalon bus. In
+ * order to issue register access requests to the slave chip, the host should
+ * send formatted bytes that conform to the transfer protocol.
+ * The transfer protocol contains 3 layers: transaction layer, packet layer
+ * and physical layer.
+ *
+ * Reference Documents could be found at:
+ * https://www.intel.com/content/www/us/en/programmable/documentation/sfo1400787952932.html
+ *
+ * Chapter "SPI Slave/JTAG to Avalon Master Bridge Cores" is a general
+ * introduction to the protocol.
+ *
+ * Chapter "Avalon Packets to Transactions Converter Core" describes
+ * the transaction layer.
+ *
+ * Chapter "Avalon-ST Bytes to Packets and Packets to Bytes Converter Cores"
+ * describes the packet layer.
+ *
+ * Chapter "Avalon-ST Serial Peripheral Interface Core" describes the
+ * physical layer.
+ *
+ *
+ * When host issues a regmap read/write, the driver will transform the request
+ * to byte stream layer by layer. It formats the register addr, value and
+ * length to the transaction layer request, then converts the request to packet
+ * layer bytes stream and then to physical layer bytes stream. Finally the
+ * driver sends the formatted byte stream over SPI bus to the slave chip.
+ *
+ * The spi-avmm IP on the slave chip decodes the byte stream and initiates
+ * register read/write on its internal Avalon bus, and then encodes the
+ * response to byte stream and sends back to host.
+ *
+ * The driver receives the byte stream, reverses the 3 layers transformation,
+ * and finally gets the response value (read out data for register read,
+ * successful written size for register write).
+ */
+
+#define PKT_SOP			0x7a
+#define PKT_EOP			0x7b
+#define PKT_CHANNEL		0x7c
+#define PKT_ESC			0x7d
+
+#define PHY_IDLE		0x4a
+#define PHY_ESC			0x4d
+
+#define TRANS_CODE_WRITE	0x0
+#define TRANS_CODE_SEQ_WRITE	0x4
+#define TRANS_CODE_READ		0x10
+#define TRANS_CODE_SEQ_READ	0x14
+#define TRANS_CODE_NO_TRANS	0x7f
+
+#define SPI_AVMM_XFER_TIMEOUT	(msecs_to_jiffies(200))
+
+/* slave's register addr is 32 bits */
+#define SPI_AVMM_REG_SIZE		4UL
+/* slave's register value is 32 bits */
+#define SPI_AVMM_VAL_SIZE		4UL
+
+/*
+ * max rx size could be larger. But considering the buffer consuming,
+ * it is proper that we limit 1KB xfer at max.
+ */
+#define MAX_READ_CNT		256UL
+#define MAX_WRITE_CNT		1UL
+
+struct trans_req_header {
+	u8 code;
+	u8 rsvd;
+	__be16 size;
+	__be32 addr;
+} __packed;
+
+struct trans_resp_header {
+	u8 r_code;
+	u8 rsvd;
+	__be16 size;
+} __packed;
+
+#define TRANS_REQ_HD_SIZE	(sizeof(struct trans_req_header))
+#define TRANS_RESP_HD_SIZE	(sizeof(struct trans_resp_header))
+
+/*
+ * In transaction layer,
+ * the write request format is: Transaction request header + data
+ * the read request format is: Transaction request header
+ * the write response format is: Transaction response header
+ * the read response format is: pure data, no Transaction response header
+ */
+#define TRANS_WR_TX_SIZE(n)	(TRANS_REQ_HD_SIZE + SPI_AVMM_VAL_SIZE * (n))
+#define TRANS_RD_TX_SIZE	TRANS_REQ_HD_SIZE
+#define TRANS_TX_MAX		TRANS_WR_TX_SIZE(MAX_WRITE_CNT)
+
+#define TRANS_RD_RX_SIZE(n)	(SPI_AVMM_VAL_SIZE * (n))
+#define TRANS_WR_RX_SIZE	TRANS_RESP_HD_SIZE
+#define TRANS_RX_MAX		TRANS_RD_RX_SIZE(MAX_READ_CNT)
+
+/* tx & rx share one transaction layer buffer */
+#define TRANS_BUF_SIZE		((TRANS_TX_MAX > TRANS_RX_MAX) ?	\
+				 TRANS_TX_MAX : TRANS_RX_MAX)
+
+/*
+ * In tx phase, the host prepares all the phy layer bytes of a request in the
+ * phy buffer and sends them in a batch.
+ *
+ * The packet layer and physical layer defines several special chars for
+ * various purpose, when a transaction layer byte hits one of these special
+ * chars, it should be escaped. The escape rule is, "Escape char first,
+ * following the byte XOR'ed with 0x20".
+ *
+ * This macro defines the max possible length of the phy data. In the worst
+ * case, all transaction layer bytes need to be escaped (so the data length
+ * doubles), plus 4 special chars (SOP, CHANNEL, CHANNEL_NUM, EOP). Finally
+ * we should make sure the length is aligned to SPI BPW.
+ */
+#define PHY_TX_MAX		ALIGN(2 * TRANS_TX_MAX + 4, 4)
+
+/*
+ * Unlike tx, phy rx is affected by possible PHY_IDLE bytes from slave, the max
+ * length of the rx bit stream is unpredictable. So the driver reads the words
+ * one by one, and parses each word immediately into transaction layer buffer.
+ * Only one word length of phy buffer is used for rx.
+ */
+#define PHY_BUF_SIZE		PHY_TX_MAX
+
+/**
+ * struct spi_avmm_bridge - SPI slave to AVMM bus master bridge
+ *
+ * @spi: spi slave associated with this bridge.
+ * @word_len: bytes of word for spi transfer.
+ * @trans_len: length of valid data in trans_buf.
+ * @phy_len: length of valid data in phy_buf.
+ * @trans_buf: the bridge buffer for transaction layer data.
+ * @phy_buf: the bridge buffer for physical layer data.
+ * @swap_words: the word swapping cb for phy data. NULL if not needed.
+ *
+ * As a device's registers are implemented on the AVMM bus address space, it
+ * requires the driver to issue formatted requests to spi slave to AVMM bus
+ * master bridge to perform register access.
+ */
+struct spi_avmm_bridge {
+	struct spi_device *spi;
+	unsigned char word_len;
+	unsigned int trans_len;
+	unsigned int phy_len;
+	/* bridge buffer used in translation between protocol layers */
+	char trans_buf[TRANS_BUF_SIZE];
+	char phy_buf[PHY_BUF_SIZE];
+	void (*swap_words)(void *buf, unsigned int len);
+};
+
+static void br_swap_words_32(void *buf, unsigned int len)
+{
+	swab32_array(buf, len / 4);
+}
+
+/*
+ * Format transaction layer data in br->trans_buf according to the register
+ * access request, Store valid transaction layer data length in br->trans_len.
+ */
+static int br_trans_tx_prepare(struct spi_avmm_bridge *br, bool is_read, u32 reg,
+			       u32 *wr_val, u32 count)
+{
+	struct trans_req_header *header;
+	unsigned int trans_len;
+	u8 code;
+	__le32 *data;
+	int i;
+
+	if (is_read) {
+		if (count == 1)
+			code = TRANS_CODE_READ;
+		else
+			code = TRANS_CODE_SEQ_READ;
+	} else {
+		if (count == 1)
+			code = TRANS_CODE_WRITE;
+		else
+			code = TRANS_CODE_SEQ_WRITE;
+	}
+
+	header = (struct trans_req_header *)br->trans_buf;
+	header->code = code;
+	header->rsvd = 0;
+	header->size = cpu_to_be16((u16)count * SPI_AVMM_VAL_SIZE);
+	header->addr = cpu_to_be32(reg);
+
+	trans_len = TRANS_REQ_HD_SIZE;
+
+	if (!is_read) {
+		trans_len += SPI_AVMM_VAL_SIZE * count;
+		if (trans_len > sizeof(br->trans_buf))
+			return -ENOMEM;
+
+		data = (__le32 *)(br->trans_buf + TRANS_REQ_HD_SIZE);
+
+		for (i = 0; i < count; i++)
+			*data++ = cpu_to_le32(*wr_val++);
+	}
+
+	/* Store valid trans data length for next layer */
+	br->trans_len = trans_len;
+
+	return 0;
+}
+
+/*
+ * Convert transaction layer data (in br->trans_buf) to phy layer data, store
+ * them in br->phy_buf. Pad the phy_buf aligned with SPI's BPW. Store valid phy
+ * layer data length in br->phy_len.
+ *
+ * phy_buf len should be aligned with SPI's BPW. Spare bytes should be padded
+ * with PHY_IDLE, then the slave will just drop them.
+ *
+ * The driver will not simply pad 4a at the tail. The concern is that driver
+ * will not store MISO data during tx phase, if the driver pads 4a at the tail,
+ * it is possible that if the slave is fast enough to response at the padding
+ * time. As a result these rx bytes are lost. In the following case, 7a,7c,00
+ * will lost.
+ * MOSI ...|7a|7c|00|10| |00|00|04|02| |4b|7d|5a|7b| |40|4a|4a|4a| |XX|XX|...
+ * MISO ...|4a|4a|4a|4a| |4a|4a|4a|4a| |4a|4a|4a|4a| |4a|7a|7c|00| |78|56|...
+ *
+ * So the driver moves EOP and bytes after EOP to the end of the aligned size,
+ * then fill the hole with PHY_IDLE. As following:
+ * before pad ...|7a|7c|00|10| |00|00|04|02| |4b|7d|5a|7b| |40|
+ * after pad  ...|7a|7c|00|10| |00|00|04|02| |4b|7d|5a|4a| |4a|4a|7b|40|
+ * Then if the slave will not get the entire packet before the tx phase is
+ * over, it can't responsed to anything either.
+ */
+static int br_pkt_phy_tx_prepare(struct spi_avmm_bridge *br)
+{
+	char *tb, *tb_end, *pb, *pb_limit, *pb_eop = NULL;
+	unsigned int aligned_phy_len, move_size;
+	bool need_esc = false;
+
+	tb = br->trans_buf;
+	tb_end = tb + br->trans_len;
+	pb = br->phy_buf;
+	pb_limit = pb + ARRAY_SIZE(br->phy_buf);
+
+	*pb++ = PKT_SOP;
+
+	/*
+	 * The driver doesn't support multiple channels so the channel number
+	 * is always 0.
+	 */
+	*pb++ = PKT_CHANNEL;
+	*pb++ = 0x0;
+
+	for (; pb < pb_limit && tb < tb_end; pb++) {
+		if (need_esc) {
+			*pb = *tb++ ^ 0x20;
+			need_esc = false;
+			continue;
+		}
+
+		/* EOP should be inserted before the last valid char */
+		if (tb == tb_end - 1 && !pb_eop) {
+			*pb = PKT_EOP;
+			pb_eop = pb;
+			continue;
+		}
+
+		/*
+		 * insert an ESCAPE char if the data value equals any special
+		 * char.
+		 */
+		switch (*tb) {
+		case PKT_SOP:
+		case PKT_EOP:
+		case PKT_CHANNEL:
+		case PKT_ESC:
+			*pb = PKT_ESC;
+			need_esc = true;
+			break;
+		case PHY_IDLE:
+		case PHY_ESC:
+			*pb = PHY_ESC;
+			need_esc = true;
+			break;
+		default:
+			*pb = *tb++;
+			break;
+		}
+	}
+
+	/* The phy buffer is used out but transaction layer data remains */
+	if (tb < tb_end)
+		return -ENOMEM;
+
+	/* Store valid phy data length for spi transfer */
+	br->phy_len = pb - br->phy_buf;
+
+	if (br->word_len == 1)
+		return 0;
+
+	/* Do phy buf padding if word_len > 1 byte. */
+	aligned_phy_len = ALIGN(br->phy_len, br->word_len);
+	if (aligned_phy_len > sizeof(br->phy_buf))
+		return -ENOMEM;
+
+	if (aligned_phy_len == br->phy_len)
+		return 0;
+
+	/* move EOP and bytes after EOP to the end of aligned size */
+	move_size = pb - pb_eop;
+	memmove(&br->phy_buf[aligned_phy_len - move_size], pb_eop, move_size);
+
+	/* fill the hole with PHY_IDLEs */
+	memset(pb_eop, PHY_IDLE, aligned_phy_len - br->phy_len);
+
+	/* update the phy data length */
+	br->phy_len = aligned_phy_len;
+
+	return 0;
+}
+
+/*
+ * In tx phase, the slave only returns PHY_IDLE (0x4a). So the driver will
+ * ignore rx in tx phase.
+ */
+static int br_do_tx(struct spi_avmm_bridge *br)
+{
+	/* reorder words for spi transfer */
+	if (br->swap_words)
+		br->swap_words(br->phy_buf, br->phy_len);
+
+	/* send all data in phy_buf  */
+	return spi_write(br->spi, br->phy_buf, br->phy_len);
+}
+
+/*
+ * This function read the rx byte stream from SPI word by word and convert
+ * them to transaction layer data in br->trans_buf. It also stores the length
+ * of rx transaction layer data in br->trans_len
+ *
+ * The slave may send an unknown number of PHY_IDLEs in rx phase, so we cannot
+ * prepare a fixed length buffer to receive all of the rx data in a batch. We
+ * have to read word by word and convert them to transaction layer data at
+ * once.
+ */
+static int br_do_rx_and_pkt_phy_parse(struct spi_avmm_bridge *br)
+{
+	bool eop_found = false, channel_found = false, esc_found = false;
+	bool valid_word = false, last_try = false;
+	struct device *dev = &br->spi->dev;
+	char *pb, *tb_limit, *tb = NULL;
+	unsigned long poll_timeout;
+	int ret, i;
+
+	tb_limit = br->trans_buf + ARRAY_SIZE(br->trans_buf);
+	pb = br->phy_buf;
+	poll_timeout = jiffies + SPI_AVMM_XFER_TIMEOUT;
+	while (tb < tb_limit) {
+		ret = spi_read(br->spi, pb, br->word_len);
+		if (ret)
+			return ret;
+
+		/* reorder the word back */
+		if (br->swap_words)
+			br->swap_words(pb, br->word_len);
+
+		valid_word = false;
+		for (i = 0; i < br->word_len; i++) {
+			/* drop everything before first SOP */
+			if (!tb && pb[i] != PKT_SOP)
+				continue;
+
+			/* drop PHY_IDLE */
+			if (pb[i] == PHY_IDLE)
+				continue;
+
+			valid_word = true;
+
+			/*
+			 * We don't support multiple channels, so error out if
+			 * a non-zero channel number is found.
+			 */
+			if (channel_found) {
+				if (pb[i] != 0) {
+					dev_err(dev, "%s channel num != 0\n",
+						__func__);
+					return -EFAULT;
+				}
+
+				channel_found = false;
+				continue;
+			}
+
+			switch (pb[i]) {
+			case PKT_SOP:
+				/*
+				 * reset the parsing if a second SOP appears.
+				 */
+				tb = br->trans_buf;
+				eop_found = false;
+				channel_found = false;
+				esc_found = false;
+				break;
+			case PKT_EOP:
+				/*
+				 * No special char is expected after ESC char.
+				 * No special char (except ESC & PHY_IDLE) is
+				 * expected after EOP char.
+				 *
+				 * The special chars are all dropped.
+				 */
+				if (esc_found || eop_found)
+					return -EFAULT;
+
+				eop_found = true;
+				break;
+			case PKT_CHANNEL:
+				if (esc_found || eop_found)
+					return -EFAULT;
+
+				channel_found = true;
+				break;
+			case PKT_ESC:
+			case PHY_ESC:
+				if (esc_found)
+					return -EFAULT;
+
+				esc_found = true;
+				break;
+			default:
+				/* Record the normal byte in trans_buf. */
+				if (esc_found) {
+					*tb++ = pb[i] ^ 0x20;
+					esc_found = false;
+				} else {
+					*tb++ = pb[i];
+				}
+
+				/*
+				 * We get the last normal byte after EOP, it is
+				 * time we finish. Normally the function should
+				 * return here.
+				 */
+				if (eop_found) {
+					br->trans_len = tb - br->trans_buf;
+					return 0;
+				}
+			}
+		}
+
+		if (valid_word) {
+			/* update poll timeout when we get valid word */
+			poll_timeout = jiffies + SPI_AVMM_XFER_TIMEOUT;
+			last_try = false;
+		} else {
+			/*
+			 * We timeout when rx keeps invalid for some time. But
+			 * it is possible we are scheduled out for long time
+			 * after a spi_read. So when we are scheduled in, a SW
+			 * timeout happens. But actually HW may have worked fine and
+			 * has been ready long time ago. So we need to do an extra
+			 * read, if we get a valid word then we could continue rx,
+			 * otherwise real a HW issue happens.
+			 */
+			if (last_try)
+				return -ETIMEDOUT;
+
+			if (time_after(jiffies, poll_timeout))
+				last_try = true;
+		}
+	}
+
+	/*
+	 * We have used out all transfer layer buffer but cannot find the end
+	 * of the byte stream.
+	 */
+	dev_err(dev, "%s transfer buffer is full but rx doesn't end\n",
+		__func__);
+
+	return -EFAULT;
+}
+
+/*
+ * For read transactions, the avmm bus will directly return register values
+ * without transaction response header.
+ */
+static int br_rd_trans_rx_parse(struct spi_avmm_bridge *br,
+				u32 *val, unsigned int expected_count)
+{